kernel 7.0.3-1 (x86_64;znver1) 2026-18059
-9999

Status rejected
Submitter bero [@T] lindev.ch
Platform rolling
Repository main
URL https://abf.openmandriva.org/build_lists/598671
Packages
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cpupower-7.0.3-1.x86_64.binary
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Build Date 2026-05-01 06:31:42 +0000 UTC
Last Updated 2026-05-30 11:57:46.527847417 +0000 UTC
$ git diff --patch-with-stat --summary 22020cf43473ade79812afb37f114137fc478037..d793176bfdfe9528b32e51f592d72ef1bc6822bc

 .abf.yml                                           |      9 +-
 .onedev-buildspec.yml                              |      4 +
 ...-Add-support-for-Acer-Predator-macro-keys.patch |     44 +-
 ...d-new-quirk-for-broken-local-ext-features.patch |     46 -
 ...mdgpu.ppfeaturemask-0xffffffff-as-default.patch |     25 +
 0001-UKSM-for-5.17.patch                           |   6901 -
 0001-UKSM-for-5.18.patch                           |   6948 -
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 ...llwinner-enable-bluetooth-pinetab-pinepho.patch |     45 -
 ...p-setup-USB-type-c-port-as-dual-data-role.patch |     29 -
 ...m-bridge-analogix_dp-Add-enable_psr-param.patch |     24 -
 ...ower-supply-Add-Support-for-RK817-Charger.patch |   1782 -
 ...m-bridge-analogix_dp-Add-enable_psr-param.patch |     24 -
 ...-drm-add-new-display-resolution-2560x1440.patch |     73 -
 ...rockchip-inno-usb2-support-rk356x-usb2phy.patch |    538 -
 0005-staging-add-rtl8723cs-driver.patch            | 446905 ------------------
 0006-HDMI-Audio-on-RK356x-Quartz64-Model-A.patch   |    308 -
 ...-drm-add-new-display-resolution-2560x1440.patch |     73 -
 0006-pinetab-accelerometer.patch                   |     21 -
 ...s-rockchip-Add-Firefly-Station-p1-support.patch |     47 -
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 ...disable-loading-of-DW-HDMI-CEC-sub-driver.patch |    295 -
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 ...ockchip-Add-pcie-bus-scan-delay-to-rockpr.patch |     25 -
 ...-rockchip-support-gamma-control-on-RK3399.patch |    667 -
 0021-drm-panfrost-scheduler-fix.patch              |    109 -
 ...hip-rga-do-proper-error-checking-in-probe.patch |    132 -
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 0023-add-dts-rk3568-station-p2.patch               |    587 -
 ...-rockchip-support-gamma-control-on-RK3399.patch |    667 -
 0024-add-dts-rk3568-radxa-rock3a.patch             |    563 -
 00e0ee4050216dc768704c503860ac4ec82e7e41.patch     |     22 +
 0103-silence-rapl.patch                            |     25 -
 0104-pci-pme-wakeups.patch                         |     27 +-
 0105-ksm-wakeups.patch                             |     49 +-
 0106-intel_idle-tweak-cpuidle-cstates.patch        |    220 -
 0109-initialize-ata-before-graphics.patch          |     16 +-
 ...low-the-memory-tuning-for-tcp-to-go-a-lit.patch |     12 +-
 0120-use-lfence-instead-of-rep-and-nop.patch       |     25 -
 0124-Extend-FEC-enum.patch                         |     11 -
 046fbc970839b287d29053c7a1083e78eecb5822.patch     |     27 +
 06fb8acf220d3bd8d1bffe098c41fbe398b36d07.patch     |     33 +
 0b7853f3fa5807bfcc193af0ebe4174fb7df21f3.patch     |     45 +
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 146008b9d4241d4e14e5b173038aa78262c2bbcd.patch     |     57 +
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 4071b7a0642a41773d61b16ae1d02218bc25345e.patch     |   1784 +
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 52a77da4f18b009c85fbfd30701b93e5fe5e715a.patch     |     51 +
 6.13-rc2-compile.patch                             |     14 +
 6d478d25de6b7550769b77edcbf8d330238542a8.patch     |     74 +
 6da0ae6e419442449ffa7778de518ca37292352b.patch     |    176 +
 7.0-rc1-compile-x86.patch                          |     14 +
 7.0-rc1-compile.patch                              |     12 +
 725cb07d90c7949a971378635e7755ff9a54d25d.patch     |     25 +
 839301464ba91c64483923c9a2a344b1c28e56ed.patch     |    229 +
 899558f6782528d5324322ae6e4c270e150c3d6f.patch     |     39 +
 992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch |     40 +-
 a7a7cf522d7636dc1280adb1b1de7fe45f9b3305.patch     |     61 +
 aarch64-desktop-omv-defconfig                      |  11989 -
 aarch64-server-omv-defconfig                       |  13115 -
 add-rockchip-iep-driver.patch                      |    112 +-
 amdgpu-ignore-min-pcap.patch                       |     75 +
 ...ble-building-ashmem-and-binder-as-modules.patch |     92 +-
 armv7hnl-server-omv-defconfig => arm-omv-defconfig |  19737 +-
 arm64-omv-defconfig                                |   6878 +
 armv7hnl-desktop-omv-defconfig                     |  12720 -
 bc1d59cd423b4a327af19bcd726f108f0f5a5da5.patch     |    770 +
 beba499cda3702062e7708b6b402d07b26d090e5.patch     |     38 +
 bluetooth.fragment                                 |     69 +
 board-rockpi4-FixMMCFreq.patch                     |     10 -
 board-rockpro64-fix-spi1-flash-speed.patch         |     13 -
 bpftool-binutils-2.39.patch                        |     38 -
 c8699f87d802bbb6e5aab8292f2e285c56976a35.patch     |     35 +
 cc17a3358bece56c8932b6a62da242f841feb2e2.patch     |   1010 +
 cd6e4f6d8babdb5e65525c6dd2d1e373558b38ab.patch     |    179 +
 cef2dc6b338e1349b2e9feda9bf41e88510aaf5a.patch     |     23 +
 cgroups.fragment                                   |     19 +
 common-desktop.config                              |     34 -
 common-server.config                               |     36 -
 common.config                                      |   7059 -
 cpu-optimizations.patch                            |    681 +
 d6aa52f8a15e56737de5e73f4f2acbb2632f43c0.patch     |     23 +
 dad4c5aac3a74cf3593fad9f7c7d0e83ae96bfa5.patch     |     22 +
 dd3ada12c3f671e92f67416ba9c267e1b12ed29d.patch     |     45 +
 debug.fragment                                     |     46 +
 dfb6b6ac7b8403a37c94e5afb0b990643409cbed.patch     |     49 +
 ...0001-MultiQueue-Skiplist-Scheduler-v0.196.patch |  10873 -
 disabled/0001-futex.patch                          |   1028 -
 ...01-gcctunes-4.18-merge-graysky-s-patchset.patch |    528 -
 ...ce-a-generic-per-ipc-pointer-and-peripc_o.patch |    162 -
 disabled/0001-lib-Add-xxhash-module.patch          |    862 -
 disabled/0001-nfp-make-friends-with-O3.patch       |     26 -
 ...v3-ITS-Refator-ITS-dt-init-code-to-prepar.patch |    249 -
 ...LLVMLinux-Remove-VLAIS-from-raid10-driver.patch |     60 -
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 ...qchip-gicv3-its-Probe-ITS-in-the-ACPI-way.patch |    115 -
 ...2400-LLVMLinux-Remove-VLAIS-from-wimax-i2.patch |     40 -
 ...its-Use-MADT-ITS-subtable-to-do-PCI-MSI-d.patch |    122 -
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 ...14-objtool-fix-seg-fault-with-gold-linker.patch |     72 -
 disabled/4.14-rc3-drm-amdgpu.patch                 | 240029 ----------
 disabled/4.18-bfq-sq-mq-v8r12-2K180817.patch       |  17959 -
 disabled/MuQSS-export-can_nice-for-binder.patch    |     11 -
 ...itial-implementation-showing-black-screen.patch |    731 -
 ...sh-Add-file-reading-and-picture-rendering.patch |    669 -
 ...ootsplash-Flush-framebuffer-after-drawing.patch |     66 -
 ...3-04-13-bootsplash-Add-corner-positioning.patch |    215 -
 ...v3-05-13-bootsplash-Add-animation-support.patch |    327 -
 ...edraw-bootsplash-fully-on-console_unblank.patch |     79 -
 ...t-Add-keyboard-hook-to-disable-bootsplash.patch |     42 -
 ...-v3-08-13-sysrq-Disable-bootsplash-on-SAK.patch |     21 -
 ...v3-09-13-fbcon-Disable-bootsplash-on-oops.patch |     21 -
 ...ntation-Add-bootsplash-main-documentation.patch |    321 -
 ...sh-sysfs-entries-to-load-and-unload-files.patch |    129 -
 ...ash-Add-a-basic-splash-file-creation-tool.patch |    511 -
 ...Add-script-and-data-to-create-sample-file.patch |    162 -
 disabled/SME-BSP_SME-microcode-update-fixes.patch  |    742 -
 ...cer-wmi-silence-unknow-functions-messages.patch |     39 -
 disabled/extra-dvb-drivers-4.16.patch              |     75 -
 disabled/hauppauge-hvr-1975.patch                  |  23046 -
 disabled/kernel-4.14-K70LUX.patch                  |     12 -
 disabled/kernel-4.17-rc7-add-lima-driver.patch     |   5257 -
 disabled/linux-5.0-rc8-fix-aquantia-ethernet.patch |     69 -
 disabled/pass-ldbfd-4.5.0-linux.patch              |     13 -
 ...l_RSB_on_context_switch_for_affected_CPUs.patch |    175 -
 ...FENCE_to_the_retpoline_filling_RSB_macros.patch |     90 -
 disabled/vbox-modules-5.0.patch                    |     23 -
 disabled/virtualbox-kernel-5.3.patch               |     61 -
 dont-disable-rdseed.patch                          |     16 +
 e0c5c98b4558d336ecb6b5a3c174816b4ed41db2.patch     |    870 +
 evdi-6.14.patch                                    |     13 +
 evdi-6.18.patch                                    |     76 +
 export-symbols-needed-by-android-drivers.patch     |    145 +-
 f0118748bc1f791775c90c52791a1770f4429702.patch     |     37 +
 f45ac0c8b0145582ba277f149a39ad386b0627b1.patch     |     23 +
 filesystems.fragment                               |    456 +
 firmware.fragment                                  |      3 +
 fix_virtualbox.patch                               |     11 -
 framer.fragment                                    |      2 +
 gcc-plugins.fragment                               |      8 +
 general-fix-inno-usb2-phy-init.patch               |     28 -
 ...asing_DMA_block_memory_allocation_to_2048.patch |     23 +-
 general-legacy-rockchip-hwrng.patch                |    393 -
 general-legacy-rockchip-hwrng_5.10.patch           |    495 -
 ...l-rk808-configurable-switch-voltage-steps.patch |     20 +-
 generic-omv-defconfig                              |   1221 +
 hid.fragment                                       |    197 +
 ...desktop-gcc-omv-defconfig => i386-omv-defconfig |  17962 +-
 i686-server-gcc-omv-defconfig                      |  11575 -
 kernel-6.19.patch                                  |    235 +
 kernel.spec                                        |   1052 +-
 linux-2000-v4l-wip-rkvdec-vp9.patch                |   3674 -
 linux-2001-v4l-wip-rkvdec-hevc.patch               |   3472 -
 linux-4.7-intel-dvi-duallink.patch                 |     20 -
 linux-5.11-arm64-lld-no-gc-sections.patch          |     10 -
 ...-5.11-disable-ICF-for-CONFIG_UNWINDER_ORC.patch |     10 +-
 linux-5.11-perf-compile.patch                      |     43 +-
 linux-5.19-prefer-amdgpu-over-radeon.patch         |     32 +-
 linux-5.2.9-riscv-compile.patch                    |     12 -
 linux-5.4.5-fix-build.patch                        |      9 -
 linux-5.5-corsair-strafe-quirks.patch              |     16 +-
 linux-5.6-fix-disassembler-4args-detection.patch   |     13 -
 linux-6.1-binutils-2.40.patch                      |     12 +
 linux-6.18-clang.patch                             |     12 +
 linux-6.19-acpi-clang.patch                        |     21 +
 linux-6.7-BTF-deps.patch                           |     11 +
 linux-7.0.tar.sign                                 |     19 +
 loongarch-omv-defconfig                            |   2237 +
 modules.fragment                                   |     39 +
 networking.fragment                                |   1359 +
 nexus-compile.patch                                |     30 +
 nvme.fragment                                      |     29 +
 perf-5.19-binutils-2.39.patch                      |     34 -
 powerpc-common.config                              |      1 -
 powerpc-omv-defconfig                              |   1445 +
 pps.fragment                                       |      3 +
 ras-fix-build-without-debugfs.patch                |     19 +
 restore-exporting-symbols-needed-by-binder.patch   |     43 +
 ...-721412ed3d819e767cac2b06646bf03aa158aaec.patch |    150 +-
 ...d326ab2dffbed92faddf6a77a84e9-no-Intel-NO.patch |     11 +-
 riscv-omv-defconfig                                |   1458 +
 rk3399-enable-dwc3-xhci-usb-trb-quirk.patch        |      6 +-
 ...i-rockchip-support-ep-gpio-undefined-case.patch |     28 -
 rk3399-rp64-rng.patch                              |      6 +-
 rk3399-sd-drive-level-8ma.patch                    |      6 +-
 rk3399-unlock-temperature.patch                    |    112 +-
 rtla-5.17-fix-make-clean.patch                     |     13 -
 security.fragment                                  |      3 +
 security_tirdad.patch                              |     46 +
 sensors.fragment                                   |    308 +
 temporary-workarounds.overrides                    |      5 +
 tp_smapi-clang.patch                               |     20 +
 trace.fragment                                     |      1 +
 v4l2loopback.c                                     |   3322 +
 v4l2loopback.h                                     |    108 +
 v4l2loopback_formats.h                             |    453 +
 vbox-6.1-fix-build-on-znver1-hosts.patch           |     36 -
 vbox-clang12.patch                                 |     36 -
 vbox-kernel-7.0.patch                              |     12 +
 vbox-modules-6.15.patch                            |     59 +
 vbox-modules-7.1.6-compile.patch                   |     12 +
 vboxvideo-kernel-6.3.patch                         |     90 +
 ...-desktop-gcc-omv-defconfig => x86-omv-defconfig |  18324 +-
 x86_64-server-gcc-omv-defconfig                    |  11246 -
 znver1.overrides                                   |    138 +
 256 files changed, 49301 insertions(+), 891990 deletions(-)
 create mode 100644 .onedev-buildspec.yml
 delete mode 100644 0001-Bluetooth-Add-new-quirk-for-broken-local-ext-features.patch
 create mode 100644 0001-Set-amdgpu.ppfeaturemask-0xffffffff-as-default.patch
 delete mode 100644 0001-UKSM-for-5.17.patch
 delete mode 100644 0001-UKSM-for-5.18.patch
 delete mode 100644 0001-arm64-dts-rockchip-Add-back-cdn_dp-to-Pinebook-Pro.patch
 delete mode 100644 0001-net-smsc95xx-Allow-mac-address-to-be-set-as-a-parame.patch
 delete mode 100644 0001-phy-rockchip-typec-Set-extcon-capabilities.patch
 delete mode 100644 0001-revert-arm64-dts-allwinner-a64-Add-I2S2-node.patch
 delete mode 100644 0002-Bluetooth-Add-new-quirk-for-broken-local-ext-features.patch
 delete mode 100644 0002-Bluetooth-btrtl-add-support-for-the-RTL8723CS.patch
 delete mode 100644 0002-arm64-dts-allwinner-add-hdmi-sound-to-pine-devices.patch
 delete mode 100644 0002-arm64-dts-rockchip-add-usb3-node-to-roc-cc-rock64.patch
 delete mode 100644 0002-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz64a.patch
 delete mode 100644 0002-usb-typec-altmodes-displayport-Add-hacky-generic-altmode.patch
 delete mode 100644 0003-Bluetooth-btrtl-add-support-for-the-RTL8723CS.patch
 delete mode 100644 0003-add-GPU-for-RK356x-SoCs.patch
 delete mode 100644 0003-arm64-allwinner-a64-enable-Bluetooth-On-Pinebook.patch
 delete mode 100644 0003-arm64-dts-allwinner-add-ohci-ehci-to-h5-nanopi.patch
 delete mode 100644 0003-arm64-dts-rockchip-add-typec-extcon-hack.patch
 delete mode 100644 0004-arm64-allwinner-a64-enable-Bluetooth-On-Pinebook.patch
 delete mode 100644 0004-arm64-dts-allwinner-add-ohci-ehci-to-h5-nanopi.patch
 delete mode 100644 0004-arm64-dts-allwinner-enable-bluetooth-pinetab-pinepho.patch
 delete mode 100644 0004-arm64-dts-rockchip-setup-USB-type-c-port-as-dual-data-role.patch
 delete mode 100644 0004-drm-bridge-analogix_dp-Add-enable_psr-param.patch
 delete mode 100644 0004-power-supply-Add-Support-for-RK817-Charger.patch
 delete mode 100644 0005-drm-bridge-analogix_dp-Add-enable_psr-param.patch
 delete mode 100644 0005-gpu-drm-add-new-display-resolution-2560x1440.patch
 delete mode 100644 0005-phy-rockchip-inno-usb2-support-rk356x-usb2phy.patch
 delete mode 100644 0005-staging-add-rtl8723cs-driver.patch
 delete mode 100644 0006-HDMI-Audio-on-RK356x-Quartz64-Model-A.patch
 delete mode 100644 0006-gpu-drm-add-new-display-resolution-2560x1440.patch
 delete mode 100644 0006-pinetab-accelerometer.patch
 delete mode 100644 0007-arm64-dts-rockchip-Add-Firefly-Station-p1-support.patch
 delete mode 100644 0007-enable-jack-detection-pinetab.patch
 delete mode 100644 0007-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch
 delete mode 100644 0007-pinetab-accelerometer.patch
 delete mode 100644 0008-arm64-dts-rockchip-enable-sdmmc1-on-Quartz64-Model-A.patch
 delete mode 100644 0008-enable-jack-detection-pinetab.patch
 delete mode 100644 0008-typec-displayport-some-devices-have-pin-assignments-reversed.patch
 delete mode 100644 0009-Add-megis-extcon-changes-to-fusb302.patch
 delete mode 100644 0009-typec-displayport-some-devices-have-pin-assignments-reversed.patch
 delete mode 100644 0010-usb-typec-Add-megis-typex-to-extcon-bridge-driver.patch
 delete mode 100644 0010-usb-typec-add-extcon-to-tcpm.patch
 delete mode 100644 0011-arm64-rockchip-add-DP-ALT-rockpro64.patch
 delete mode 100644 0012-ayufan-drm-rockchip-add-support-for-modeline-32MHz-e.patch
 delete mode 100644 0013-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch
 delete mode 100644 0014-arm64-dts-rockchip-add-typec-extcon-hack.patch
 delete mode 100644 0014-drm-meson-add-YUV422-output-support.patch
 delete mode 100644 0015-drm-meson-add-YUV422-output-support.patch
 delete mode 100644 0016-add-ugoos-device.patch
 delete mode 100644 0016-arm64-dts-meson-add-initial-Beelink-GT1-Ultimate-dev.patch
 delete mode 100644 0017-add-ugoos-device.patch
 delete mode 100644 0018-drm-bridge-dw-hdmi-disable-loading-of-DW-HDMI-CEC-sub-driver.patch
 delete mode 100644 0018-drm-panfrost-scheduler-fix.patch
 delete mode 100644 0019-arm64-dts-rockchip-Add-pcie-bus-scan-delay-to-rockpr.patch
 delete mode 100644 0020-drm-rockchip-support-gamma-control-on-RK3399.patch
 delete mode 100644 0021-drm-panfrost-scheduler-fix.patch
 delete mode 100644 0021-media-rockchip-rga-do-proper-error-checking-in-probe.patch
 delete mode 100644 0022-arm-dts-rockchip-firefly-station-m2.patch
 delete mode 100644 0023-add-dts-rk3568-station-p2.patch
 delete mode 100644 0023-drm-rockchip-support-gamma-control-on-RK3399.patch
 delete mode 100644 0024-add-dts-rk3568-radxa-rock3a.patch
 create mode 100644 00e0ee4050216dc768704c503860ac4ec82e7e41.patch
 delete mode 100644 0103-silence-rapl.patch
 delete mode 100644 0106-intel_idle-tweak-cpuidle-cstates.patch
 delete mode 100644 0120-use-lfence-instead-of-rep-and-nop.patch
 delete mode 100644 0124-Extend-FEC-enum.patch
 create mode 100644 046fbc970839b287d29053c7a1083e78eecb5822.patch
 create mode 100644 06fb8acf220d3bd8d1bffe098c41fbe398b36d07.patch
 create mode 100644 0b7853f3fa5807bfcc193af0ebe4174fb7df21f3.patch
 create mode 100644 0f13fb4aa5e9aec8fcc30d4cd244a1c94a9ab01f.patch
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 create mode 100644 linux-6.19-acpi-clang.patch
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 create mode 100644 linux-7.0.tar.sign
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 create mode 100644 restore-exporting-symbols-needed-by-binder.patch
 create mode 100644 riscv-omv-defconfig
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 delete mode 100644 rtla-5.17-fix-make-clean.patch
 create mode 100644 security.fragment
 create mode 100644 security_tirdad.patch
 create mode 100644 sensors.fragment
 create mode 100644 temporary-workarounds.overrides
 create mode 100644 tp_smapi-clang.patch
 create mode 100644 trace.fragment
 create mode 100644 v4l2loopback.c
 create mode 100644 v4l2loopback.h
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 delete mode 100644 vbox-clang12.patch
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 rename x86_64-desktop-gcc-omv-defconfig => x86-omv-defconfig (54%)
 delete mode 100644 x86_64-server-gcc-omv-defconfig
 create mode 100644 znver1.overrides

diff --git a/.abf.yml b/.abf.yml
index 31f4bb1..a792003 100644
--- a/.abf.yml
+++ b/.abf.yml
@@ -1,6 +1,9 @@
 sources:
   extra-wifi-drivers-20200301.tar.zst: 3390c738c7d91250714ce0f88d26371e93bc40b8
   saa716x-driver.tar.xz: f9b6ef1cd6f1f71f53d9a8aadfba2cf6b5c3d7b6
-  linux-6.1.tar.xz: 30996d7c1c59ddbd495bd9eb37c8dfdb1a67c1c3
-  linux-6.1.tar.sign: 18021ed9b414ecb69cc726a395b68c0e0a1b331d
-  patch-6.1.4.xz: 9933d8e54dc6dba8cdc9bd86be1a2420557cb8ce
+  hid-tmff2-20260310.tar.gz: 0fb4fec5a0294c7eb5654f28fef2123a5f230324
+  linux-7.0.tar.xz: 0a043b4cdeae371edc7fe956898c4304c8f702c0
+  nexus-20260415.tar.gz: a4766d14e83ffcca1df61b62f1721f5ec08bd724
+  tp_smapi-0.45.tgz: ced1ea185dc6acdf0dd9f2a51cd75fc14a19fa82
+  v1.14.15.tar.gz: 32928095e379eb486aa2ea2a828a2d752ac35a45
+  patch-7.0.3.xz: 7a4c7b53308f5dd8099f0289cdcd4861c199bc79
diff --git a/.onedev-buildspec.yml b/.onedev-buildspec.yml
new file mode 100644
index 0000000..b95f83a
--- /dev/null
+++ b/.onedev-buildspec.yml
@@ -0,0 +1,4 @@
+version: 40
+imports:
+- projectPath: OpenMandriva/Packages
+  revision: mirroring
diff --git a/0001-Add-support-for-Acer-Predator-macro-keys.patch b/0001-Add-support-for-Acer-Predator-macro-keys.patch
index e6df2d1..8097c53 100644
--- a/0001-Add-support-for-Acer-Predator-macro-keys.patch
+++ b/0001-Add-support-for-Acer-Predator-macro-keys.patch
@@ -1,6 +1,6 @@
-diff -up linux-5.15/drivers/platform/x86/acer-wmi.c.4~ linux-5.15/drivers/platform/x86/acer-wmi.c
---- linux-5.15/drivers/platform/x86/acer-wmi.c.4~	2021-10-31 21:53:10.000000000 +0100
-+++ linux-5.15/drivers/platform/x86/acer-wmi.c	2021-11-03 20:17:25.582117524 +0100
+diff -up linux-6.18-rc7/drivers/platform/x86/acer-wmi.c.2~ linux-6.18-rc7/drivers/platform/x86/acer-wmi.c
+--- linux-6.18-rc7/drivers/platform/x86/acer-wmi.c.2~	2025-11-23 23:53:16.000000000 +0100
++++ linux-6.18-rc7/drivers/platform/x86/acer-wmi.c	2025-11-24 22:09:24.104580688 +0100
 @@ -7,6 +7,9 @@
   *  Based on acer_acpi:
   *    Copyright (C) 2005-2007	E.M. Smith
@@ -11,16 +11,16 @@ diff -up linux-5.15/drivers/platform/x86/acer-wmi.c.4~ linux-5.15/drivers/platfo
   */
  
  #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-@@ -87,7 +90,7 @@ MODULE_ALIAS("wmi:676AA15E-6A47-4D9F-A2C
- enum acer_wmi_event_ids {
+@@ -104,7 +107,7 @@ enum acer_wmi_event_ids {
  	WMID_HOTKEY_EVENT = 0x1,
+ 	WMID_BACKLIGHT_EVENT = 0x4,
  	WMID_ACCEL_OR_KBD_DOCK_EVENT = 0x5,
 -	WMID_GAMING_TURBO_KEY_EVENT = 0x7,
 +	WMID_GAMING_KEY_EVENT = 0x7,
+ 	WMID_AC_EVENT = 0x8,
  };
  
- static const struct key_entry acer_wmi_keymap[] __initconst = {
-@@ -125,6 +128,26 @@ static const struct key_entry acer_wmi_k
+@@ -177,6 +180,26 @@ static const struct key_entry acer_wmi_k
  	{KE_KEY, 0x85, {KEY_TOUCHPAD_TOGGLE} },
  	{KE_KEY, 0x86, {KEY_WLAN} },
  	{KE_KEY, 0x87, {KEY_POWER} },
@@ -47,23 +47,22 @@ diff -up linux-5.15/drivers/platform/x86/acer-wmi.c.4~ linux-5.15/drivers/platfo
  	{KE_END, 0}
  };
  
-@@ -252,6 +275,7 @@ static bool ec_raw_mode;
+@@ -301,6 +324,7 @@ static bool ec_raw_mode;
  static bool has_type_aa;
  static u16 commun_func_bitmap;
  static u8 commun_fn_key_number;
 +static u8 macro_key_state = 0;
- 
- module_param(mailled, int, 0444);
- module_param(brightness, int, 0444);
-@@ -2047,9 +2071,32 @@ static void acer_wmi_notify(u32 value, v
+ static bool cycle_gaming_thermal_profile = true;
+ static bool predator_v4;
+ static u64 supported_sensors;
+@@ -2377,12 +2401,30 @@ static void acer_wmi_notify(union acpi_o
  		acer_gsensor_event();
  		acer_kbd_dock_event(&return_value);
  		break;
 -	case WMID_GAMING_TURBO_KEY_EVENT:
 -		if (return_value.key_num == 0x4)
 +	case WMID_GAMING_KEY_EVENT:
-+		switch(return_value.key_num) {
-+		case 0x1:
++		if (return_value.key_num == 0x1) {
 +			/*
 +			 * This is the macro toggle key on Acer Predator
 +			 * laptops (it switches colors and selects which
@@ -75,18 +74,19 @@ diff -up linux-5.15/drivers/platform/x86/acer-wmi.c.4~ linux-5.15/drivers/platfo
 +			else
 +				pr_warn("macro key state %d requested (only values 1 to 3 are known)\n", return_value.device_state);
 +			break;
-+		case 0x2:
++		} else if (return_value.key_num == 0x2) {
 +			if(return_value.device_state >= 1 && return_value.device_state <= 5)
 +				sparse_keymap_report_event(acer_wmi_input_dev, 0xda00 + (macro_key_state<<4) + return_value.device_state-1, 1, true);
 +			else
 +				pr_warn("macro key %d pressed (only 1 to 5 are known)\n", return_value.device_state);
 +			break;
-+		case 0x4:
++		} else if (return_value.key_num == 0x4)
  			acer_toggle_turbo();
-+			break;
-+		default:
-+			pr_warn("Unknown Acer gaming key pressed - %d\n", return_value.key_num);
-+		}
+-		if (return_value.key_num == 0x5 && has_cap(ACER_CAP_PLATFORM_PROFILE))
++		else if (return_value.key_num == 0x5 && has_cap(ACER_CAP_PLATFORM_PROFILE))
+ 			acer_thermal_profile_change();
+-		break;
++ 		break;
+ 	case WMID_AC_EVENT:
+ 		/* We ignore AC events here */
  		break;
- 	default:
- 		pr_warn("Unknown function number - %d - %d\n",
diff --git a/0001-Bluetooth-Add-new-quirk-for-broken-local-ext-features.patch b/0001-Bluetooth-Add-new-quirk-for-broken-local-ext-features.patch
deleted file mode 100644
index 4970a4e..0000000
--- a/0001-Bluetooth-Add-new-quirk-for-broken-local-ext-features.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 942e794211fc05943db36212d41c4e8a68b3c922 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Mon, 17 Aug 2020 21:32:16 +0200
-Subject: [PATCH] Bluetooth-Add-new-quirk-for-broken-local-ext-features
-
----
- include/net/bluetooth/hci.h | 7 +++++++
- net/bluetooth/hci_event.c   | 4 +++-
- 2 files changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h
-index c8e67042a3b1..53f7a8518372 100644
---- a/include/net/bluetooth/hci.h
-+++ b/include/net/bluetooth/hci.h
-@@ -228,6 +228,13 @@ enum {
- 	 */
- 	HCI_QUIRK_VALID_LE_STATES,
- 
-+	/* When this quirk is set, max_page for local extended features
-+	 * is set to 1, even if controller reports higher number. Some
-+	 * controllers (e.g. RTL8723CS) report more pages, but they
-+	 * don't actually support features declared there.
-+	 */
-+	HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE,
-+
- 	/* When this quirk is set, then erroneous data reporting
- 	 * is ignored. This is mainly due to the fact that the HCI
- 	 * Read Default Erroneous Data Reporting command is advertised,
-diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
-index 4b7fc430793c..9b165c8f16de 100644
---- a/net/bluetooth/hci_event.c
-+++ b/net/bluetooth/hci_event.c
-@@ -700,7 +700,9 @@ static void hci_cc_read_local_ext_features(struct hci_dev *hdev,
- 	if (rp->status)
- 		return;
- 
--	if (hdev->max_page < rp->max_page)
-+	if (!test_bit(HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE,
-+		      &hdev->quirks) &&
-+	    hdev->max_page < rp->max_page)
- 		hdev->max_page = rp->max_page;
- 
- 	if (rp->page < HCI_MAX_PAGES)
--- 
-2.28.0
-
diff --git a/0001-Set-amdgpu.ppfeaturemask-0xffffffff-as-default.patch b/0001-Set-amdgpu.ppfeaturemask-0xffffffff-as-default.patch
new file mode 100644
index 0000000..26e3ab7
--- /dev/null
+++ b/0001-Set-amdgpu.ppfeaturemask-0xffffffff-as-default.patch
@@ -0,0 +1,25 @@
+From 9179080ffaaf1d438db6e0a5a37bdf8dafe233a6 Mon Sep 17 00:00:00 2001
+From: Thomas Crider <gloriouseggroll@gmail.com>
+Date: Mon, 27 Nov 2023 16:13:13 -0500
+Subject: [PATCH] Set amdgpu.ppfeaturemask=0xffffffff as default
+
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index e06009966..4e791eb8f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -158,7 +158,7 @@ bool enforce_isolation;
+  * OverDrive(bit 14) disabled by default
+  * GFX DCS(bit 19) disabled by default
+  */
+-uint amdgpu_pp_feature_mask = 0xfff7bfff;
++uint amdgpu_pp_feature_mask = 0xffffffff;
+ uint amdgpu_force_long_training;
+ int amdgpu_lbpw = -1;
+ int amdgpu_compute_multipipe = -1;
+-- 
+2.43.0
+
diff --git a/0001-UKSM-for-5.17.patch b/0001-UKSM-for-5.17.patch
deleted file mode 100644
index 10bcb79..0000000
--- a/0001-UKSM-for-5.17.patch
+++ /dev/null
@@ -1,6901 +0,0 @@
-diff -up linux-5.17/Documentation/vm/uksm.txt.12~ linux-5.17/Documentation/vm/uksm.txt
---- linux-5.17/Documentation/vm/uksm.txt.12~	2022-03-26 17:17:42.867812619 +0100
-+++ linux-5.17/Documentation/vm/uksm.txt	2022-03-26 17:17:42.867812619 +0100
-@@ -0,0 +1,61 @@
-+The Ultra Kernel Samepage Merging feature
-+----------------------------------------------
-+/*
-+ * Ultra KSM. Copyright (C) 2011-2012 Nai Xia
-+ *
-+ * This is an improvement upon KSM. Some basic data structures and routines
-+ * are borrowed from ksm.c .
-+ *
-+ * Its new features:
-+ * 1. Full system scan:
-+ *      It automatically scans all user processes' anonymous VMAs. Kernel-user
-+ *      interaction to submit a memory area to KSM is no longer needed.
-+ *
-+ * 2. Rich area detection:
-+ *      It automatically detects rich areas containing abundant duplicated
-+ *      pages based. Rich areas are given a full scan speed. Poor areas are
-+ *      sampled at a reasonable speed with very low CPU consumption.
-+ *
-+ * 3. Ultra Per-page scan speed improvement:
-+ *      A new hash algorithm is proposed. As a result, on a machine with
-+ *      Core(TM)2 Quad Q9300 CPU in 32-bit mode and 800MHZ DDR2 main memory, it
-+ *      can scan memory areas that does not contain duplicated pages at speed of
-+ *      627MB/sec ~ 2445MB/sec and can merge duplicated areas at speed of
-+ *      477MB/sec ~ 923MB/sec.
-+ *
-+ * 4. Thrashing area avoidance:
-+ *      Thrashing area(an VMA that has frequent Ksm page break-out) can be
-+ *      filtered out. My benchmark shows it's more efficient than KSM's per-page
-+ *      hash value based volatile page detection.
-+ *
-+ *
-+ * 5. Misc changes upon KSM:
-+ *      * It has a fully x86-opitmized memcmp dedicated for 4-byte-aligned page
-+ *        comparison. It's much faster than default C version on x86.
-+ *      * rmap_item now has an struct *page member to loosely cache a
-+ *        address-->page mapping, which reduces too much time-costly
-+ *        follow_page().
-+ *      * The VMA creation/exit procedures are hooked to let the Ultra KSM know.
-+ *      * try_to_merge_two_pages() now can revert a pte if it fails. No break_
-+ *        ksm is needed for this case.
-+ *
-+ * 6. Full Zero Page consideration(contributed by Figo Zhang)
-+ *    Now uksmd consider full zero pages as special pages and merge them to an
-+ *    special unswappable uksm zero page.
-+ */
-+
-+ChangeLog:
-+
-+2012-05-05 The creation of this Doc
-+2012-05-08 UKSM 0.1.1.1 libc crash bug fix, api clean up, doc clean up.
-+2012-05-28 UKSM 0.1.1.2 bug fix release
-+2012-06-26 UKSM 0.1.2-beta1 first beta release for 0.1.2
-+2012-07-2  UKSM 0.1.2-beta2
-+2012-07-10 UKSM 0.1.2-beta3
-+2012-07-26 UKSM 0.1.2 Fine grained speed control, more scan optimization.
-+2012-10-13 UKSM 0.1.2.1 Bug fixes.
-+2012-12-31 UKSM 0.1.2.2 Minor bug fixes.
-+2014-07-02 UKSM 0.1.2.3 Fix a " __this_cpu_read() in preemptible bug".
-+2015-04-22 UKSM 0.1.2.4 Fix a race condition that can sometimes trigger anonying warnings.
-+2016-09-10 UKSM 0.1.2.5 Fix a bug in dedup ratio calculation.
-+2017-02-26 UKSM 0.1.2.6 Fix a bug in hugetlbpage handling and a race bug with page migration.
-diff -up linux-5.17/fs/exec.c.12~ linux-5.17/fs/exec.c
---- linux-5.17/fs/exec.c.12~	2022-03-20 21:14:17.000000000 +0100
-+++ linux-5.17/fs/exec.c	2022-03-26 17:17:42.868812624 +0100
-@@ -66,6 +66,7 @@
- #include <linux/io_uring.h>
- #include <linux/syscall_user_dispatch.h>
- #include <linux/coredump.h>
-+#include <linux/ksm.h>
- 
- #include <linux/uaccess.h>
- #include <asm/mmu_context.h>
-diff -up linux-5.17/fs/proc/meminfo.c.12~ linux-5.17/fs/proc/meminfo.c
---- linux-5.17/fs/proc/meminfo.c.12~	2022-03-20 21:14:17.000000000 +0100
-+++ linux-5.17/fs/proc/meminfo.c	2022-03-26 17:17:42.868812624 +0100
-@@ -108,6 +108,10 @@ static int meminfo_proc_show(struct seq_
- #endif
- 	show_val_kb(m, "PageTables:     ",
- 		    global_node_page_state(NR_PAGETABLE));
-+#ifdef CONFIG_UKSM
-+	show_val_kb(m, "KsmZeroPages:     ",
-+		    global_zone_page_state(NR_UKSM_ZERO_PAGES));
-+#endif
- 
- 	show_val_kb(m, "NFS_Unstable:   ", 0);
- 	show_val_kb(m, "Bounce:         ",
-diff -up linux-5.17/include/linux/ksm.h.12~ linux-5.17/include/linux/ksm.h
---- linux-5.17/include/linux/ksm.h.12~	2022-03-20 21:14:17.000000000 +0100
-+++ linux-5.17/include/linux/ksm.h	2022-03-26 17:17:42.868812624 +0100
-@@ -21,20 +21,16 @@ struct mem_cgroup;
- #ifdef CONFIG_KSM
- int ksm_madvise(struct vm_area_struct *vma, unsigned long start,
- 		unsigned long end, int advice, unsigned long *vm_flags);
--int __ksm_enter(struct mm_struct *mm);
--void __ksm_exit(struct mm_struct *mm);
- 
--static inline int ksm_fork(struct mm_struct *mm, struct mm_struct *oldmm)
-+static inline struct stable_node *page_stable_node(struct page *page)
- {
--	if (test_bit(MMF_VM_MERGEABLE, &oldmm->flags))
--		return __ksm_enter(mm);
--	return 0;
-+	return PageKsm(page) ? page_rmapping(page) : NULL;
- }
- 
--static inline void ksm_exit(struct mm_struct *mm)
-+static inline void set_page_stable_node(struct page *page,
-+					struct stable_node *stable_node)
- {
--	if (test_bit(MMF_VM_MERGEABLE, &mm->flags))
--		__ksm_exit(mm);
-+	page->mapping = (void *)((unsigned long)stable_node | PAGE_MAPPING_KSM);
- }
- 
- /*
-@@ -54,6 +50,33 @@ struct page *ksm_might_need_to_copy(stru
- void rmap_walk_ksm(struct page *page, struct rmap_walk_control *rwc);
- void folio_migrate_ksm(struct folio *newfolio, struct folio *folio);
- 
-+#ifdef CONFIG_KSM_LEGACY
-+int __ksm_enter(struct mm_struct *mm);
-+void __ksm_exit(struct mm_struct *mm);
-+static inline int ksm_fork(struct mm_struct *mm, struct mm_struct *oldmm)
-+{
-+	if (test_bit(MMF_VM_MERGEABLE, &oldmm->flags))
-+		return __ksm_enter(mm);
-+	return 0;
-+}
-+
-+static inline void ksm_exit(struct mm_struct *mm)
-+{
-+	if (test_bit(MMF_VM_MERGEABLE, &mm->flags))
-+		__ksm_exit(mm);
-+}
-+
-+#elif defined(CONFIG_UKSM)
-+static inline int ksm_fork(struct mm_struct *mm, struct mm_struct *oldmm)
-+{
-+	return 0;
-+}
-+
-+static inline void ksm_exit(struct mm_struct *mm)
-+{
-+}
-+#endif /* !CONFIG_UKSM */
-+
- #else  /* !CONFIG_KSM */
- 
- static inline int ksm_fork(struct mm_struct *mm, struct mm_struct *oldmm)
-@@ -89,4 +112,6 @@ static inline void folio_migrate_ksm(str
- #endif /* CONFIG_MMU */
- #endif /* !CONFIG_KSM */
- 
-+#include <linux/uksm.h>
-+
- #endif /* __LINUX_KSM_H */
-diff -up linux-5.17/include/linux/mm_types.h.12~ linux-5.17/include/linux/mm_types.h
---- linux-5.17/include/linux/mm_types.h.12~	2022-03-20 21:14:17.000000000 +0100
-+++ linux-5.17/include/linux/mm_types.h	2022-03-26 17:17:42.868812624 +0100
-@@ -452,6 +452,9 @@ struct vm_area_struct {
- 	struct mempolicy *vm_policy;	/* NUMA policy for the VMA */
- #endif
- 	struct vm_userfaultfd_ctx vm_userfaultfd_ctx;
-+#ifdef CONFIG_UKSM
-+	struct vma_slot *uksm_vma_slot;
-+#endif
- } __randomize_layout;
- 
- struct kioctx_table;
-diff -up linux-5.17/include/linux/mmzone.h.12~ linux-5.17/include/linux/mmzone.h
---- linux-5.17/include/linux/mmzone.h.12~	2022-03-20 21:14:17.000000000 +0100
-+++ linux-5.17/include/linux/mmzone.h	2022-03-26 17:17:42.868812624 +0100
-@@ -158,6 +158,9 @@ enum zone_stat_item {
- 	NR_ZSPAGES,		/* allocated in zsmalloc */
- #endif
- 	NR_FREE_CMA_PAGES,
-+#ifdef CONFIG_UKSM
-+	NR_UKSM_ZERO_PAGES,
-+#endif
- 	NR_VM_ZONE_STAT_ITEMS };
- 
- enum node_stat_item {
-diff -up linux-5.17/include/linux/pgtable.h.12~ linux-5.17/include/linux/pgtable.h
---- linux-5.17/include/linux/pgtable.h.12~	2022-03-20 21:14:17.000000000 +0100
-+++ linux-5.17/include/linux/pgtable.h	2022-03-26 17:17:42.868812624 +0100
-@@ -1146,13 +1146,26 @@ extern void untrack_pfn(struct vm_area_s
- extern void untrack_pfn_moved(struct vm_area_struct *vma);
- #endif
- 
-+#ifdef CONFIG_UKSM
-+static inline int is_uksm_zero_pfn(unsigned long pfn)
-+{
-+	extern unsigned long uksm_zero_pfn;
-+	return pfn == uksm_zero_pfn;
-+}
-+#else
-+static inline int is_uksm_zero_pfn(unsigned long pfn)
-+{
-+	return 0;
-+}
-+#endif
-+
- #ifdef CONFIG_MMU
- #ifdef __HAVE_COLOR_ZERO_PAGE
- static inline int is_zero_pfn(unsigned long pfn)
- {
- 	extern unsigned long zero_pfn;
- 	unsigned long offset_from_zero_pfn = pfn - zero_pfn;
--	return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
-+	return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT) || is_uksm_zero_pfn(pfn);
- }
- 
- #define my_zero_pfn(addr)	page_to_pfn(ZERO_PAGE(addr))
-@@ -1161,7 +1174,7 @@ static inline int is_zero_pfn(unsigned l
- static inline int is_zero_pfn(unsigned long pfn)
- {
- 	extern unsigned long zero_pfn;
--	return pfn == zero_pfn;
-+	return (pfn == zero_pfn) || (is_uksm_zero_pfn(pfn));
- }
- 
- static inline unsigned long my_zero_pfn(unsigned long addr)
-diff -up linux-5.17/include/linux/sradix-tree.h.12~ linux-5.17/include/linux/sradix-tree.h
---- linux-5.17/include/linux/sradix-tree.h.12~	2022-03-26 17:17:42.868812624 +0100
-+++ linux-5.17/include/linux/sradix-tree.h	2022-03-26 17:17:42.868812624 +0100
-@@ -0,0 +1,77 @@
-+#ifndef _LINUX_SRADIX_TREE_H
-+#define _LINUX_SRADIX_TREE_H
-+
-+
-+#define INIT_SRADIX_TREE(root, mask)					\
-+do {									\
-+	(root)->height = 0;						\
-+	(root)->gfp_mask = (mask);					\
-+	(root)->rnode = NULL;						\
-+} while (0)
-+
-+#define ULONG_BITS	(sizeof(unsigned long) * 8)
-+#define SRADIX_TREE_INDEX_BITS  (8 /* CHAR_BIT */ * sizeof(unsigned long))
-+//#define SRADIX_TREE_MAP_SHIFT	6
-+//#define SRADIX_TREE_MAP_SIZE	(1UL << SRADIX_TREE_MAP_SHIFT)
-+//#define SRADIX_TREE_MAP_MASK	(SRADIX_TREE_MAP_SIZE-1)
-+
-+struct sradix_tree_node {
-+	unsigned int	height;		/* Height from the bottom */
-+	unsigned int	count;
-+	unsigned int	fulls;		/* Number of full sublevel trees */
-+	struct sradix_tree_node *parent;
-+	void *stores[0];
-+};
-+
-+/* A simple radix tree implementation */
-+struct sradix_tree_root {
-+	unsigned int            height;
-+	struct sradix_tree_node *rnode;
-+
-+	/* Where found to have available empty stores in its sublevels */
-+	struct sradix_tree_node *enter_node;
-+	unsigned int shift;
-+	unsigned int stores_size;
-+	unsigned int mask;
-+	unsigned long min;	/* The first hole index */
-+	unsigned long num;
-+	//unsigned long *height_to_maxindex;
-+
-+	/* How the node is allocated and freed. */
-+	struct sradix_tree_node *(*alloc)(void);
-+	void (*free)(struct sradix_tree_node *node);
-+
-+	/* When a new node is added and removed */
-+	void (*extend)(struct sradix_tree_node *parent, struct sradix_tree_node *child);
-+	void (*assign)(struct sradix_tree_node *node, unsigned int index, void *item);
-+	void (*rm)(struct sradix_tree_node *node, unsigned int offset);
-+};
-+
-+struct sradix_tree_path {
-+	struct sradix_tree_node *node;
-+	int offset;
-+};
-+
-+static inline
-+void init_sradix_tree_root(struct sradix_tree_root *root, unsigned long shift)
-+{
-+	root->height = 0;
-+	root->rnode = NULL;
-+	root->shift = shift;
-+	root->stores_size = 1UL << shift;
-+	root->mask = root->stores_size - 1;
-+}
-+
-+
-+extern void *sradix_tree_next(struct sradix_tree_root *root,
-+		       struct sradix_tree_node *node, unsigned long index,
-+		       int (*iter)(void *, unsigned long));
-+
-+extern int sradix_tree_enter(struct sradix_tree_root *root, void **item, int num);
-+
-+extern void sradix_tree_delete_from_leaf(struct sradix_tree_root *root,
-+			struct sradix_tree_node *node, unsigned long index);
-+
-+extern void *sradix_tree_lookup(struct sradix_tree_root *root, unsigned long index);
-+
-+#endif /* _LINUX_SRADIX_TREE_H */
-diff -up linux-5.17/include/linux/uksm.h.12~ linux-5.17/include/linux/uksm.h
---- linux-5.17/include/linux/uksm.h.12~	2022-03-26 17:17:42.868812624 +0100
-+++ linux-5.17/include/linux/uksm.h	2022-03-26 17:17:42.868812624 +0100
-@@ -0,0 +1,149 @@
-+#ifndef __LINUX_UKSM_H
-+#define __LINUX_UKSM_H
-+/*
-+ * Memory merging support.
-+ *
-+ * This code enables dynamic sharing of identical pages found in different
-+ * memory areas, even if they are not shared by fork().
-+ */
-+
-+/* if !CONFIG_UKSM this file should not be compiled at all. */
-+#ifdef CONFIG_UKSM
-+
-+#include <linux/bitops.h>
-+#include <linux/mm.h>
-+#include <linux/pagemap.h>
-+#include <linux/rmap.h>
-+#include <linux/sched.h>
-+
-+extern unsigned long zero_pfn __read_mostly;
-+extern unsigned long uksm_zero_pfn __read_mostly;
-+extern struct page *empty_uksm_zero_page;
-+
-+/* must be done before linked to mm */
-+extern void uksm_vma_add_new(struct vm_area_struct *vma);
-+extern void uksm_remove_vma(struct vm_area_struct *vma);
-+
-+#define UKSM_SLOT_NEED_SORT	(1 << 0)
-+#define UKSM_SLOT_NEED_RERAND	(1 << 1)
-+#define UKSM_SLOT_SCANNED	(1 << 2) /* It's scanned in this round */
-+#define UKSM_SLOT_FUL_SCANNED	(1 << 3)
-+#define UKSM_SLOT_IN_UKSM	(1 << 4)
-+
-+struct vma_slot {
-+	struct sradix_tree_node *snode;
-+	unsigned long sindex;
-+
-+	struct list_head slot_list;
-+	unsigned long fully_scanned_round;
-+	unsigned long dedup_num;
-+	unsigned long pages_scanned;
-+	unsigned long this_sampled;
-+	unsigned long last_scanned;
-+	unsigned long pages_to_scan;
-+	struct scan_rung *rung;
-+	struct page **rmap_list_pool;
-+	unsigned int *pool_counts;
-+	unsigned long pool_size;
-+	struct vm_area_struct *vma;
-+	struct mm_struct *mm;
-+	unsigned long ctime_j;
-+	unsigned long pages;
-+	unsigned long flags;
-+	unsigned long pages_cowed; /* pages cowed this round */
-+	unsigned long pages_merged; /* pages merged this round */
-+	unsigned long pages_bemerged;
-+
-+	/* when it has page merged in this eval round */
-+	struct list_head dedup_list;
-+};
-+
-+static inline void uksm_unmap_zero_page(pte_t pte)
-+{
-+	if (pte_pfn(pte) == uksm_zero_pfn)
-+		__dec_zone_page_state(empty_uksm_zero_page, NR_UKSM_ZERO_PAGES);
-+}
-+
-+static inline void uksm_map_zero_page(pte_t pte)
-+{
-+	if (pte_pfn(pte) == uksm_zero_pfn)
-+		__inc_zone_page_state(empty_uksm_zero_page, NR_UKSM_ZERO_PAGES);
-+}
-+
-+static inline void uksm_cow_page(struct vm_area_struct *vma, struct page *page)
-+{
-+	if (vma->uksm_vma_slot && PageKsm(page))
-+		vma->uksm_vma_slot->pages_cowed++;
-+}
-+
-+static inline void uksm_cow_pte(struct vm_area_struct *vma, pte_t pte)
-+{
-+	if (vma->uksm_vma_slot && pte_pfn(pte) == uksm_zero_pfn)
-+		vma->uksm_vma_slot->pages_cowed++;
-+}
-+
-+static inline int uksm_flags_can_scan(unsigned long vm_flags)
-+{
-+#ifdef VM_SAO
-+		if (vm_flags & VM_SAO)
-+			return 0;
-+#endif
-+
-+	return !(vm_flags & (VM_PFNMAP | VM_IO  | VM_DONTEXPAND |
-+			     VM_HUGETLB | VM_MIXEDMAP | VM_SHARED
-+			     | VM_MAYSHARE | VM_GROWSUP | VM_GROWSDOWN));
-+}
-+
-+static inline void uksm_vm_flags_mod(unsigned long *vm_flags_p)
-+{
-+	if (uksm_flags_can_scan(*vm_flags_p))
-+		*vm_flags_p |= VM_MERGEABLE;
-+}
-+
-+/*
-+ * Just a wrapper for BUG_ON for where ksm_zeropage must not be. TODO: it will
-+ * be removed when uksm zero page patch is stable enough.
-+ */
-+static inline void uksm_bugon_zeropage(pte_t pte)
-+{
-+	BUG_ON(pte_pfn(pte) == uksm_zero_pfn);
-+}
-+#else
-+static inline void uksm_vma_add_new(struct vm_area_struct *vma)
-+{
-+}
-+
-+static inline void uksm_remove_vma(struct vm_area_struct *vma)
-+{
-+}
-+
-+static inline void uksm_unmap_zero_page(pte_t pte)
-+{
-+}
-+
-+static inline void uksm_map_zero_page(pte_t pte)
-+{
-+}
-+
-+static inline void uksm_cow_page(struct vm_area_struct *vma, struct page *page)
-+{
-+}
-+
-+static inline void uksm_cow_pte(struct vm_area_struct *vma, pte_t pte)
-+{
-+}
-+
-+static inline int uksm_flags_can_scan(unsigned long vm_flags)
-+{
-+	return 0;
-+}
-+
-+static inline void uksm_vm_flags_mod(unsigned long *vm_flags_p)
-+{
-+}
-+
-+static inline void uksm_bugon_zeropage(pte_t pte)
-+{
-+}
-+#endif /* !CONFIG_UKSM */
-+#endif /* __LINUX_UKSM_H */
-diff -up linux-5.17/kernel/fork.c.12~ linux-5.17/kernel/fork.c
---- linux-5.17/kernel/fork.c.12~	2022-03-20 21:14:17.000000000 +0100
-+++ linux-5.17/kernel/fork.c	2022-03-26 17:17:42.868812624 +0100
-@@ -606,7 +606,7 @@ static __latent_entropy int dup_mmap(str
- 		__vma_link_rb(mm, tmp, rb_link, rb_parent);
- 		rb_link = &tmp->vm_rb.rb_right;
- 		rb_parent = &tmp->vm_rb;
--
-+		uksm_vma_add_new(tmp);
- 		mm->map_count++;
- 		if (!(tmp->vm_flags & VM_WIPEONFORK))
- 			retval = copy_page_range(tmp, mpnt);
-diff -up linux-5.17/lib/Makefile.12~ linux-5.17/lib/Makefile
---- linux-5.17/lib/Makefile.12~	2022-03-20 21:14:17.000000000 +0100
-+++ linux-5.17/lib/Makefile	2022-03-26 17:17:42.868812624 +0100
-@@ -28,7 +28,7 @@ CFLAGS_string.o += -fno-stack-protector
- endif
- 
- lib-y := ctype.o string.o vsprintf.o cmdline.o \
--	 rbtree.o radix-tree.o timerqueue.o xarray.o \
-+	 rbtree.o radix-tree.o sradix-tree.o timerqueue.o xarray.o \
- 	 idr.o extable.o sha1.o irq_regs.o argv_split.o \
- 	 flex_proportions.o ratelimit.o show_mem.o \
- 	 is_single_threaded.o plist.o decompress.o kobject_uevent.o \
-diff -up linux-5.17/lib/sradix-tree.c.12~ linux-5.17/lib/sradix-tree.c
---- linux-5.17/lib/sradix-tree.c.12~	2022-03-26 17:17:42.868812624 +0100
-+++ linux-5.17/lib/sradix-tree.c	2022-03-26 17:17:42.868812624 +0100
-@@ -0,0 +1,476 @@
-+#include <linux/errno.h>
-+#include <linux/mm.h>
-+#include <linux/mman.h>
-+#include <linux/spinlock.h>
-+#include <linux/slab.h>
-+#include <linux/gcd.h>
-+#include <linux/sradix-tree.h>
-+
-+static inline int sradix_node_full(struct sradix_tree_root *root, struct sradix_tree_node *node)
-+{
-+	return node->fulls == root->stores_size ||
-+		(node->height == 1 && node->count == root->stores_size);
-+}
-+
-+/*
-+ *	Extend a sradix tree so it can store key @index.
-+ */
-+static int sradix_tree_extend(struct sradix_tree_root *root, unsigned long index)
-+{
-+	struct sradix_tree_node *node;
-+	unsigned int height;
-+
-+	if (unlikely(root->rnode == NULL)) {
-+		if (!(node = root->alloc()))
-+			return -ENOMEM;
-+
-+		node->height = 1;
-+		root->rnode = node;
-+		root->height = 1;
-+	}
-+
-+	/* Figure out what the height should be.  */
-+	height = root->height;
-+	index >>= root->shift * height;
-+
-+	while (index) {
-+		index >>= root->shift;
-+		height++;
-+	}
-+
-+	while (height > root->height) {
-+		unsigned int newheight;
-+
-+		if (!(node = root->alloc()))
-+			return -ENOMEM;
-+
-+		/* Increase the height.  */
-+		node->stores[0] = root->rnode;
-+		root->rnode->parent = node;
-+		if (root->extend)
-+			root->extend(node, root->rnode);
-+
-+		newheight = root->height + 1;
-+		node->height = newheight;
-+		node->count = 1;
-+		if (sradix_node_full(root, root->rnode))
-+			node->fulls = 1;
-+
-+		root->rnode = node;
-+		root->height = newheight;
-+	}
-+
-+	return 0;
-+}
-+
-+/*
-+ * Search the next item from the current node, that is not NULL
-+ * and can satify root->iter().
-+ */
-+void *sradix_tree_next(struct sradix_tree_root *root,
-+		       struct sradix_tree_node *node, unsigned long index,
-+		       int (*iter)(void *item, unsigned long height))
-+{
-+	unsigned long offset;
-+	void *item;
-+
-+	if (unlikely(node == NULL)) {
-+		node = root->rnode;
-+		for (offset = 0; offset < root->stores_size; offset++) {
-+			item = node->stores[offset];
-+			if (item && (!iter || iter(item, node->height)))
-+				break;
-+		}
-+
-+		if (unlikely(offset >= root->stores_size))
-+			return NULL;
-+
-+		if (node->height == 1)
-+			return item;
-+		else
-+			goto go_down;
-+	}
-+
-+	while (node) {
-+		offset = (index & root->mask) + 1;
-+		for (; offset < root->stores_size; offset++) {
-+			item = node->stores[offset];
-+			if (item && (!iter || iter(item, node->height)))
-+				break;
-+		}
-+
-+		if (offset < root->stores_size)
-+			break;
-+
-+		node = node->parent;
-+		index >>= root->shift;
-+	}
-+
-+	if (!node)
-+		return NULL;
-+
-+	while (node->height > 1) {
-+go_down:
-+		node = item;
-+		for (offset = 0; offset < root->stores_size; offset++) {
-+			item = node->stores[offset];
-+			if (item && (!iter || iter(item, node->height)))
-+				break;
-+		}
-+
-+		if (unlikely(offset >= root->stores_size))
-+			return NULL;
-+	}
-+
-+	BUG_ON(offset > root->stores_size);
-+
-+	return item;
-+}
-+
-+/*
-+ * Blindly insert the item to the tree. Typically, we reuse the
-+ * first empty store item.
-+ */
-+int sradix_tree_enter(struct sradix_tree_root *root, void **item, int num)
-+{
-+	unsigned long index;
-+	unsigned int height;
-+	struct sradix_tree_node *node, *tmp = NULL;
-+	int offset, offset_saved;
-+	void **store = NULL;
-+	int error, i, j, shift;
-+
-+go_on:
-+	index = root->min;
-+
-+	if (root->enter_node && !sradix_node_full(root, root->enter_node)) {
-+		node = root->enter_node;
-+		BUG_ON((index >> (root->shift * root->height)));
-+	} else {
-+		node = root->rnode;
-+		if (node == NULL || (index >> (root->shift * root->height))
-+		    || sradix_node_full(root, node)) {
-+			error = sradix_tree_extend(root, index);
-+			if (error)
-+				return error;
-+
-+			node = root->rnode;
-+		}
-+	}
-+
-+
-+	height = node->height;
-+	shift = (height - 1) * root->shift;
-+	offset = (index >> shift) & root->mask;
-+	while (shift > 0) {
-+		offset_saved = offset;
-+		for (; offset < root->stores_size; offset++) {
-+			store = &node->stores[offset];
-+			tmp = *store;
-+
-+			if (!tmp || !sradix_node_full(root, tmp))
-+				break;
-+		}
-+		BUG_ON(offset >= root->stores_size);
-+
-+		if (offset != offset_saved) {
-+			index += (offset - offset_saved) << shift;
-+			index &= ~((1UL << shift) - 1);
-+		}
-+
-+		if (!tmp) {
-+			if (!(tmp = root->alloc()))
-+				return -ENOMEM;
-+
-+			tmp->height = shift / root->shift;
-+			*store = tmp;
-+			tmp->parent = node;
-+			node->count++;
-+//			if (root->extend)
-+//				root->extend(node, tmp);
-+		}
-+
-+		node = tmp;
-+		shift -= root->shift;
-+		offset = (index >> shift) & root->mask;
-+	}
-+
-+	BUG_ON(node->height != 1);
-+
-+
-+	store = &node->stores[offset];
-+	for (i = 0, j = 0;
-+	      j < root->stores_size - node->count &&
-+	      i < root->stores_size - offset && j < num; i++) {
-+		if (!store[i]) {
-+			store[i] = item[j];
-+			if (root->assign)
-+				root->assign(node, index + i, item[j]);
-+			j++;
-+		}
-+	}
-+
-+	node->count += j;
-+	root->num += j;
-+	num -= j;
-+
-+	while (sradix_node_full(root, node)) {
-+		node = node->parent;
-+		if (!node)
-+			break;
-+
-+		node->fulls++;
-+	}
-+
-+	if (unlikely(!node)) {
-+		/* All nodes are full */
-+		root->min = 1 << (root->height * root->shift);
-+		root->enter_node = NULL;
-+	} else {
-+		root->min = index + i - 1;
-+		root->min |= (1UL << (node->height - 1)) - 1;
-+		root->min++;
-+		root->enter_node = node;
-+	}
-+
-+	if (num) {
-+		item += j;
-+		goto go_on;
-+	}
-+
-+	return 0;
-+}
-+
-+
-+/**
-+ *	sradix_tree_shrink    -    shrink height of a sradix tree to minimal
-+ *      @root		sradix tree root
-+ *
-+ */
-+static inline void sradix_tree_shrink(struct sradix_tree_root *root)
-+{
-+	/* try to shrink tree height */
-+	while (root->height > 1) {
-+		struct sradix_tree_node *to_free = root->rnode;
-+
-+		/*
-+		 * The candidate node has more than one child, or its child
-+		 * is not at the leftmost store, we cannot shrink.
-+		 */
-+		if (to_free->count != 1 || !to_free->stores[0])
-+			break;
-+
-+		root->rnode = to_free->stores[0];
-+		root->rnode->parent = NULL;
-+		root->height--;
-+		if (unlikely(root->enter_node == to_free))
-+			root->enter_node = NULL;
-+		root->free(to_free);
-+	}
-+}
-+
-+/*
-+ * Del the item on the known leaf node and index
-+ */
-+void sradix_tree_delete_from_leaf(struct sradix_tree_root *root,
-+				  struct sradix_tree_node *node, unsigned long index)
-+{
-+	unsigned int offset;
-+	struct sradix_tree_node *start, *end;
-+
-+	BUG_ON(node->height != 1);
-+
-+	start = node;
-+	while (node && !(--node->count))
-+		node = node->parent;
-+
-+	end = node;
-+	if (!node) {
-+		root->rnode = NULL;
-+		root->height = 0;
-+		root->min = 0;
-+		root->num = 0;
-+		root->enter_node = NULL;
-+	} else {
-+		offset = (index >> (root->shift * (node->height - 1))) & root->mask;
-+		if (root->rm)
-+			root->rm(node, offset);
-+		node->stores[offset] = NULL;
-+		root->num--;
-+		if (root->min > index) {
-+			root->min = index;
-+			root->enter_node = node;
-+		}
-+	}
-+
-+	if (start != end) {
-+		do {
-+			node = start;
-+			start = start->parent;
-+			if (unlikely(root->enter_node == node))
-+				root->enter_node = end;
-+			root->free(node);
-+		} while (start != end);
-+
-+		/*
-+		 * Note that shrink may free "end", so enter_node still need to
-+		 * be checked inside.
-+		 */
-+		sradix_tree_shrink(root);
-+	} else if (node->count == root->stores_size - 1) {
-+		/* It WAS a full leaf node. Update the ancestors */
-+		node = node->parent;
-+		while (node) {
-+			node->fulls--;
-+			if (node->fulls != root->stores_size - 1)
-+				break;
-+
-+			node = node->parent;
-+		}
-+	}
-+}
-+
-+void *sradix_tree_lookup(struct sradix_tree_root *root, unsigned long index)
-+{
-+	unsigned int height, offset;
-+	struct sradix_tree_node *node;
-+	int shift;
-+
-+	node = root->rnode;
-+	if (node == NULL || (index >> (root->shift * root->height)))
-+		return NULL;
-+
-+	height = root->height;
-+	shift = (height - 1) * root->shift;
-+
-+	do {
-+		offset = (index >> shift) & root->mask;
-+		node = node->stores[offset];
-+		if (!node)
-+			return NULL;
-+
-+		shift -= root->shift;
-+	} while (shift >= 0);
-+
-+	return node;
-+}
-+
-+/*
-+ * Return the item if it exists, otherwise create it in place
-+ * and return the created item.
-+ */
-+void *sradix_tree_lookup_create(struct sradix_tree_root *root,
-+			unsigned long index, void *(*item_alloc)(void))
-+{
-+	unsigned int height, offset;
-+	struct sradix_tree_node *node, *tmp;
-+	void *item;
-+	int shift, error;
-+
-+	if (root->rnode == NULL || (index >> (root->shift * root->height))) {
-+		if (item_alloc) {
-+			error = sradix_tree_extend(root, index);
-+			if (error)
-+				return NULL;
-+		} else {
-+			return NULL;
-+		}
-+	}
-+
-+	node = root->rnode;
-+	height = root->height;
-+	shift = (height - 1) * root->shift;
-+
-+	do {
-+		offset = (index >> shift) & root->mask;
-+		if (!node->stores[offset]) {
-+			if (!(tmp = root->alloc()))
-+				return NULL;
-+
-+			tmp->height = shift / root->shift;
-+			node->stores[offset] = tmp;
-+			tmp->parent = node;
-+			node->count++;
-+			node = tmp;
-+		} else {
-+			node = node->stores[offset];
-+		}
-+
-+		shift -= root->shift;
-+	} while (shift > 0);
-+
-+	BUG_ON(node->height != 1);
-+	offset = index & root->mask;
-+	if (node->stores[offset]) {
-+		return node->stores[offset];
-+	} else if (item_alloc) {
-+		if (!(item = item_alloc()))
-+			return NULL;
-+
-+		node->stores[offset] = item;
-+
-+		/*
-+		 * NOTE: we do NOT call root->assign here, since this item is
-+		 * newly created by us having no meaning. Caller can call this
-+		 * if it's necessary to do so.
-+		 */
-+
-+		node->count++;
-+		root->num++;
-+
-+		while (sradix_node_full(root, node)) {
-+			node = node->parent;
-+			if (!node)
-+				break;
-+
-+			node->fulls++;
-+		}
-+
-+		if (unlikely(!node)) {
-+			/* All nodes are full */
-+			root->min = 1 << (root->height * root->shift);
-+		} else {
-+			if (root->min == index) {
-+				root->min |= (1UL << (node->height - 1)) - 1;
-+				root->min++;
-+				root->enter_node = node;
-+			}
-+		}
-+
-+		return item;
-+	} else {
-+		return NULL;
-+	}
-+
-+}
-+
-+int sradix_tree_delete(struct sradix_tree_root *root, unsigned long index)
-+{
-+	unsigned int height, offset;
-+	struct sradix_tree_node *node;
-+	int shift;
-+
-+	node = root->rnode;
-+	if (node == NULL || (index >> (root->shift * root->height)))
-+		return -ENOENT;
-+
-+	height = root->height;
-+	shift = (height - 1) * root->shift;
-+
-+	do {
-+		offset = (index >> shift) & root->mask;
-+		node = node->stores[offset];
-+		if (!node)
-+			return -ENOENT;
-+
-+		shift -= root->shift;
-+	} while (shift > 0);
-+
-+	offset = index & root->mask;
-+	if (!node->stores[offset])
-+		return -ENOENT;
-+
-+	sradix_tree_delete_from_leaf(root, node, index);
-+
-+	return 0;
-+}
-diff -up linux-5.17/mm/Kconfig.12~ linux-5.17/mm/Kconfig
---- linux-5.17/mm/Kconfig.12~	2022-03-20 21:14:17.000000000 +0100
-+++ linux-5.17/mm/Kconfig	2022-03-26 17:17:42.869812628 +0100
-@@ -304,6 +304,32 @@ config KSM
- 	  See Documentation/vm/ksm.rst for more information: KSM is inactive
- 	  until a program has madvised that an area is MADV_MERGEABLE, and
- 	  root has set /sys/kernel/mm/ksm/run to 1 (if CONFIG_SYSFS is set).
-+choice
-+	prompt "Choose UKSM/KSM strategy"
-+	default UKSM
-+	depends on KSM
-+	help
-+	  This option allows to select a UKSM/KSM stragety.
-+
-+config UKSM
-+	bool "Ultra-KSM for page merging"
-+	depends on KSM
-+	help
-+	UKSM is inspired by the Linux kernel project \u2014 KSM(Kernel Same
-+	page Merging), but with a fundamentally rewritten core algorithm. With
-+	an advanced algorithm, UKSM now can transparently scans all anonymously
-+	mapped user space applications with an significantly improved scan speed
-+	and CPU efficiency. Since KVM is friendly to KSM, KVM can also benefit from
-+	UKSM. Now UKSM has its first stable release and first real world enterprise user.
-+	For more information, please goto its project page.
-+	(github.com/dolohow/uksm)
-+
-+config KSM_LEGACY
-+	bool "Legacy KSM implementation"
-+	depends on KSM
-+	help
-+	The legacy KSM implementation from Red Hat.
-+endchoice
- 
- config DEFAULT_MMAP_MIN_ADDR
- 	int "Low address space to protect from user allocation"
-diff -up linux-5.17/mm/ksm.c.12~ linux-5.17/mm/ksm.c
---- linux-5.17/mm/ksm.c.12~	2022-03-20 21:14:17.000000000 +0100
-+++ linux-5.17/mm/ksm.c	2022-03-26 17:17:42.869812628 +0100
-@@ -858,17 +858,6 @@ static inline struct stable_node *folio_
- 	return folio_test_ksm(folio) ? folio_raw_mapping(folio) : NULL;
- }
- 
--static inline struct stable_node *page_stable_node(struct page *page)
--{
--	return folio_stable_node(page_folio(page));
--}
--
--static inline void set_page_stable_node(struct page *page,
--					struct stable_node *stable_node)
--{
--	page->mapping = (void *)((unsigned long)stable_node | PAGE_MAPPING_KSM);
--}
--
- #ifdef CONFIG_SYSFS
- /*
-  * Only called through the sysfs control interface:
-diff -up linux-5.17/mm/Makefile.12~ linux-5.17/mm/Makefile
---- linux-5.17/mm/Makefile.12~	2022-03-20 21:14:17.000000000 +0100
-+++ linux-5.17/mm/Makefile	2022-03-26 17:17:42.869812628 +0100
-@@ -83,7 +83,8 @@ obj-$(CONFIG_SPARSEMEM)	+= sparse.o
- obj-$(CONFIG_SPARSEMEM_VMEMMAP) += sparse-vmemmap.o
- obj-$(CONFIG_SLOB) += slob.o
- obj-$(CONFIG_MMU_NOTIFIER) += mmu_notifier.o
--obj-$(CONFIG_KSM) += ksm.o
-+obj-$(CONFIG_KSM_LEGACY) += ksm.o
-+obj-$(CONFIG_UKSM) += uksm.o
- obj-$(CONFIG_PAGE_POISONING) += page_poison.o
- obj-$(CONFIG_SLAB) += slab.o
- obj-$(CONFIG_SLUB) += slub.o
-diff -up linux-5.17/mm/memory.c.12~ linux-5.17/mm/memory.c
---- linux-5.17/mm/memory.c.12~	2022-03-20 21:14:17.000000000 +0100
-+++ linux-5.17/mm/memory.c	2022-03-26 17:19:20.593255743 +0100
-@@ -158,6 +158,25 @@ EXPORT_SYMBOL(zero_pfn);
- 
- unsigned long highest_memmap_pfn __read_mostly;
- 
-+#ifdef CONFIG_UKSM
-+unsigned long uksm_zero_pfn __read_mostly;
-+EXPORT_SYMBOL_GPL(uksm_zero_pfn);
-+struct page *empty_uksm_zero_page;
-+
-+static int __init setup_uksm_zero_page(void)
-+{
-+	empty_uksm_zero_page = alloc_pages(__GFP_ZERO & ~__GFP_MOVABLE, 0);
-+	if (!empty_uksm_zero_page)
-+		panic("Oh boy, that early out of memory?");
-+
-+	SetPageReserved(empty_uksm_zero_page);
-+	uksm_zero_pfn = page_to_pfn(empty_uksm_zero_page);
-+
-+	return 0;
-+}
-+core_initcall(setup_uksm_zero_page);
-+#endif
-+
- /*
-  * CONFIG_MMU architectures set up ZERO_PAGE in their paging_init()
-  */
-@@ -173,6 +192,7 @@ void mm_trace_rss_stat(struct mm_struct
- 	trace_rss_stat(mm, member, count);
- }
- 
-+
- #if defined(SPLIT_RSS_COUNTING)
- 
- void sync_mm_rss(struct mm_struct *mm)
-@@ -958,6 +978,11 @@ copy_present_pte(struct vm_area_struct *
- 		get_page(page);
- 		page_dup_rmap(page, false);
- 		rss[mm_counter(page)]++;
-+
-+		/* Should return NULL in vm_normal_page() */
-+		uksm_bugon_zeropage(pte);
-+	} else {
-+		uksm_map_zero_page(pte);
- 	}
- 
- 	/*
-@@ -1364,8 +1389,10 @@ again:
- 			ptent = ptep_get_and_clear_full(mm, addr, pte,
- 							tlb->fullmm);
- 			tlb_remove_tlb_entry(tlb, pte, addr);
--			if (unlikely(!page))
-+			if (unlikely(!page)) {
-+				uksm_unmap_zero_page(ptent);
- 				continue;
-+			}
- 
- 			if (!PageAnon(page)) {
- 				if (pte_dirty(ptent)) {
-@@ -2762,6 +2789,7 @@ static inline bool cow_user_page(struct
- 
- 	if (likely(src)) {
- 		copy_user_highpage(dst, src, addr, vma);
-+		uksm_cow_page(vma, src);
- 		return true;
- 	}
- 
-@@ -3008,6 +3036,7 @@ static vm_fault_t wp_page_copy(struct vm
- 							      vmf->address);
- 		if (!new_page)
- 			goto oom;
-+		uksm_cow_pte(vma, vmf->orig_pte);
- 	} else {
- 		new_page = alloc_page_vma(GFP_HIGHUSER_MOVABLE, vma,
- 				vmf->address);
-@@ -3050,7 +3079,9 @@ static vm_fault_t wp_page_copy(struct vm
- 						mm_counter_file(old_page));
- 				inc_mm_counter_fast(mm, MM_ANONPAGES);
- 			}
-+			uksm_bugon_zeropage(vmf->orig_pte);
- 		} else {
-+			uksm_unmap_zero_page(vmf->orig_pte);
- 			inc_mm_counter_fast(mm, MM_ANONPAGES);
- 		}
- 		flush_cache_page(vma, vmf->address, pte_pfn(vmf->orig_pte));
-diff -up linux-5.17/mm/mmap.c.12~ linux-5.17/mm/mmap.c
---- linux-5.17/mm/mmap.c.12~	2022-03-20 21:14:17.000000000 +0100
-+++ linux-5.17/mm/mmap.c	2022-03-26 17:17:42.869812628 +0100
-@@ -47,6 +47,7 @@
- #include <linux/moduleparam.h>
- #include <linux/pkeys.h>
- #include <linux/oom.h>
-+#include <linux/ksm.h>
- #include <linux/sched/mm.h>
- 
- #include <linux/uaccess.h>
-@@ -186,6 +187,7 @@ static struct vm_area_struct *remove_vma
- 	if (vma->vm_file)
- 		fput(vma->vm_file);
- 	mpol_put(vma_policy(vma));
-+       uksm_remove_vma(vma);
- 	vm_area_free(vma);
- 	return next;
- }
-@@ -752,9 +754,16 @@ int __vma_adjust(struct vm_area_struct *
- 	long adjust_next = 0;
- 	int remove_next = 0;
- 
-+/*
-+ * to avoid deadlock, ksm_remove_vma must be done before any spin_lock is
-+ * acquired
-+ */
-+	uksm_remove_vma(vma);
-+
- 	if (next && !insert) {
- 		struct vm_area_struct *exporter = NULL, *importer = NULL;
- 
-+		uksm_remove_vma(next);
- 		if (end >= next->vm_end) {
- 			/*
- 			 * vma expands, overlapping all the next, and
-@@ -885,6 +894,7 @@ again:
- 		end_changed = true;
- 	}
- 	vma->vm_pgoff = pgoff;
-+
- 	if (adjust_next) {
- 		next->vm_start += adjust_next;
- 		next->vm_pgoff += adjust_next >> PAGE_SHIFT;
-@@ -989,6 +999,7 @@ again:
- 		if (remove_next == 2) {
- 			remove_next = 1;
- 			end = next->vm_end;
-+			uksm_remove_vma(next);
- 			goto again;
- 		}
- 		else if (next)
-@@ -1015,10 +1026,14 @@ again:
- 			 */
- 			VM_WARN_ON(mm->highest_vm_end != vm_end_gap(vma));
- 		}
-+	} else {
-+		if (next && !insert)
-+			uksm_vma_add_new(next);
- 	}
- 	if (insert && file)
- 		uprobe_mmap(insert);
- 
-+	uksm_vma_add_new(vma);
- 	validate_mm(mm);
- 
- 	return 0;
-@@ -1477,6 +1492,9 @@ unsigned long do_mmap(struct file *file,
- 	vm_flags = calc_vm_prot_bits(prot, pkey) | calc_vm_flag_bits(flags) |
- 			mm->def_flags | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC;
- 
-+	/* If uksm is enabled, we add VM_MERGEABLE to new VMAs. */
-+	uksm_vm_flags_mod(&vm_flags);
-+
- 	if (flags & MAP_LOCKED)
- 		if (!can_do_mlock())
- 			return -EPERM;
-@@ -1849,6 +1867,7 @@ unmap_writable:
- 	if (file && vm_flags & VM_SHARED)
- 		mapping_unmap_writable(file->f_mapping);
- 	file = vma->vm_file;
-+	uksm_vma_add_new(vma);
- out:
- 	perf_event_mmap(vma);
- 
-@@ -1888,6 +1907,7 @@ unmap_and_free_vma:
- 	if (vm_flags & VM_SHARED)
- 		mapping_unmap_writable(file->f_mapping);
- free_vma:
-+	uksm_remove_vma(vma);
- 	vm_area_free(vma);
- unacct_error:
- 	if (charged)
-@@ -2748,6 +2768,8 @@ int __split_vma(struct mm_struct *mm, st
- 	else
- 		err = vma_adjust(vma, vma->vm_start, addr, vma->vm_pgoff, new);
- 
-+	uksm_vma_add_new(new);
-+
- 	/* Success. */
- 	if (!err)
- 		return 0;
-@@ -3037,6 +3059,7 @@ static int do_brk_flags(unsigned long ad
- 	if ((flags & (~VM_EXEC)) != 0)
- 		return -EINVAL;
- 	flags |= VM_DATA_DEFAULT_FLAGS | VM_ACCOUNT | mm->def_flags;
-+	uksm_vm_flags_mod(&flags);
- 
- 	mapped_addr = get_unmapped_area(NULL, addr, len, 0, MAP_FIXED);
- 	if (IS_ERR_VALUE(mapped_addr))
-@@ -3082,6 +3105,7 @@ static int do_brk_flags(unsigned long ad
- 	vma->vm_flags = flags;
- 	vma->vm_page_prot = vm_get_page_prot(flags);
- 	vma_link(mm, vma, prev, rb_link, rb_parent);
-+	uksm_vma_add_new(vma);
- out:
- 	perf_event_mmap(vma);
- 	mm->total_vm += len >> PAGE_SHIFT;
-@@ -3187,6 +3211,8 @@ void exit_mmap(struct mm_struct *mm)
- 		cond_resched();
- 	}
- 	mm->mmap = NULL;
-+	mm->mm_rb = RB_ROOT;
-+	vmacache_invalidate(mm);
- 	mmap_write_unlock(mm);
- 	vm_unacct_memory(nr_accounted);
- }
-@@ -3296,6 +3322,7 @@ struct vm_area_struct *copy_vma(struct v
- 			new_vma->vm_ops->open(new_vma);
- 		vma_link(mm, new_vma, prev, rb_link, rb_parent);
- 		*need_rmap_locks = false;
-+		uksm_vma_add_new(new_vma);
- 	}
- 	return new_vma;
- 
-@@ -3460,6 +3487,7 @@ static struct vm_area_struct *__install_
- 	vm_stat_account(mm, vma->vm_flags, len >> PAGE_SHIFT);
- 
- 	perf_event_mmap(vma);
-+	uksm_vma_add_new(vma);
- 
- 	return vma;
- 
-diff -up linux-5.17/mm/uksm.c.12~ linux-5.17/mm/uksm.c
---- linux-5.17/mm/uksm.c.12~	2022-03-26 17:17:42.870812633 +0100
-+++ linux-5.17/mm/uksm.c	2022-03-26 17:17:42.870812633 +0100
-@@ -0,0 +1,5620 @@
-+/*
-+ * Ultra KSM. Copyright (C) 2011-2012 Nai Xia
-+ *
-+ * This is an improvement upon KSM. Some basic data structures and routines
-+ * are borrowed from ksm.c .
-+ *
-+ * Its new features:
-+ * 1. Full system scan:
-+ *      It automatically scans all user processes' anonymous VMAs. Kernel-user
-+ *      interaction to submit a memory area to KSM is no longer needed.
-+ *
-+ * 2. Rich area detection:
-+ *      It automatically detects rich areas containing abundant duplicated
-+ *      pages based. Rich areas are given a full scan speed. Poor areas are
-+ *      sampled at a reasonable speed with very low CPU consumption.
-+ *
-+ * 3. Ultra Per-page scan speed improvement:
-+ *      A new hash algorithm is proposed. As a result, on a machine with
-+ *      Core(TM)2 Quad Q9300 CPU in 32-bit mode and 800MHZ DDR2 main memory, it
-+ *      can scan memory areas that does not contain duplicated pages at speed of
-+ *      627MB/sec ~ 2445MB/sec and can merge duplicated areas at speed of
-+ *      477MB/sec ~ 923MB/sec.
-+ *
-+ * 4. Thrashing area avoidance:
-+ *      Thrashing area(an VMA that has frequent Ksm page break-out) can be
-+ *      filtered out. My benchmark shows it's more efficient than KSM's per-page
-+ *      hash value based volatile page detection.
-+ *
-+ *
-+ * 5. Misc changes upon KSM:
-+ *      * It has a fully x86-opitmized memcmp dedicated for 4-byte-aligned page
-+ *        comparison. It's much faster than default C version on x86.
-+ *      * rmap_item now has an struct *page member to loosely cache a
-+ *        address-->page mapping, which reduces too much time-costly
-+ *        follow_page().
-+ *      * The VMA creation/exit procedures are hooked to let the Ultra KSM know.
-+ *      * try_to_merge_two_pages() now can revert a pte if it fails. No break_
-+ *        ksm is needed for this case.
-+ *
-+ * 6. Full Zero Page consideration(contributed by Figo Zhang)
-+ *    Now uksmd consider full zero pages as special pages and merge them to an
-+ *    special unswappable uksm zero page.
-+ */
-+
-+#include <linux/errno.h>
-+#include <linux/mm.h>
-+#include <linux/fs.h>
-+#include <linux/mman.h>
-+#include <linux/sched.h>
-+#include <linux/sched/mm.h>
-+#include <linux/sched/coredump.h>
-+#include <linux/sched/cputime.h>
-+#include <linux/rwsem.h>
-+#include <linux/pagemap.h>
-+#include <linux/rmap.h>
-+#include <linux/spinlock.h>
-+#include <linux/jhash.h>
-+#include <linux/delay.h>
-+#include <linux/kthread.h>
-+#include <linux/wait.h>
-+#include <linux/slab.h>
-+#include <linux/rbtree.h>
-+#include <linux/memory.h>
-+#include <linux/mmu_notifier.h>
-+#include <linux/mm_inline.h>
-+#include <linux/swap.h>
-+#include <linux/ksm.h>
-+#include <linux/crypto.h>
-+#include <linux/scatterlist.h>
-+#include <crypto/hash.h>
-+#include <linux/random.h>
-+#include <linux/math64.h>
-+#include <linux/gcd.h>
-+#include <linux/freezer.h>
-+#include <linux/oom.h>
-+#include <linux/numa.h>
-+#include <linux/sradix-tree.h>
-+
-+#include <asm/tlbflush.h>
-+#include "internal.h"
-+
-+#ifdef CONFIG_X86
-+#undef memcmp
-+
-+#ifdef CONFIG_X86_32
-+#define memcmp memcmpx86_32
-+/*
-+ * Compare 4-byte-aligned address s1 and s2, with length n
-+ */
-+int memcmpx86_32(void *s1, void *s2, size_t n)
-+{
-+	size_t num = n / 4;
-+	register int res;
-+
-+	__asm__ __volatile__
-+	(
-+	 "testl %3,%3\n\t"
-+	 "repe; cmpsd\n\t"
-+	 "je        1f\n\t"
-+	 "sbbl      %0,%0\n\t"
-+	 "orl       $1,%0\n"
-+	 "1:"
-+	 : "=&a" (res), "+&S" (s1), "+&D" (s2), "+&c" (num)
-+	 : "0" (0)
-+	 : "cc");
-+
-+	return res;
-+}
-+
-+/*
-+ * Check the page is all zero ?
-+ */
-+static int is_full_zero(const void *s1, size_t len)
-+{
-+	unsigned char same;
-+
-+	len /= 4;
-+
-+	__asm__ __volatile__
-+	("repe; scasl;"
-+	 "sete %0"
-+	 : "=qm" (same), "+D" (s1), "+c" (len)
-+	 : "a" (0)
-+	 : "cc");
-+
-+	return same;
-+}
-+
-+
-+#elif defined(CONFIG_X86_64)
-+#define memcmp memcmpx86_64
-+/*
-+ * Compare 8-byte-aligned address s1 and s2, with length n
-+ */
-+int memcmpx86_64(void *s1, void *s2, size_t n)
-+{
-+	size_t num = n / 8;
-+	register int res;
-+
-+	__asm__ __volatile__
-+	(
-+	 "testq %q3,%q3\n\t"
-+	 "repe; cmpsq\n\t"
-+	 "je        1f\n\t"
-+	 "sbbq      %q0,%q0\n\t"
-+	 "orq       $1,%q0\n"
-+	 "1:"
-+	 : "=&a" (res), "+&S" (s1), "+&D" (s2), "+&c" (num)
-+	 : "0" (0)
-+	 : "cc");
-+
-+	return res;
-+}
-+
-+static int is_full_zero(const void *s1, size_t len)
-+{
-+	unsigned char same;
-+
-+	len /= 8;
-+
-+	__asm__ __volatile__
-+	("repe; scasq;"
-+	 "sete %0"
-+	 : "=qm" (same), "+D" (s1), "+c" (len)
-+	 : "a" (0)
-+	 : "cc");
-+
-+	return same;
-+}
-+
-+#endif
-+#else
-+static int is_full_zero(const void *s1, size_t len)
-+{
-+	unsigned long *src = s1;
-+	int i;
-+
-+	len /= sizeof(*src);
-+
-+	for (i = 0; i < len; i++) {
-+		if (src[i])
-+			return 0;
-+	}
-+
-+	return 1;
-+}
-+#endif
-+
-+#define UKSM_RUNG_ROUND_FINISHED  (1 << 0)
-+#define TIME_RATIO_SCALE	10000
-+
-+#define SLOT_TREE_NODE_SHIFT	8
-+#define SLOT_TREE_NODE_STORE_SIZE	(1UL << SLOT_TREE_NODE_SHIFT)
-+struct slot_tree_node {
-+	unsigned long size;
-+	struct sradix_tree_node snode;
-+	void *stores[SLOT_TREE_NODE_STORE_SIZE];
-+};
-+
-+static struct kmem_cache *slot_tree_node_cachep;
-+
-+static struct sradix_tree_node *slot_tree_node_alloc(void)
-+{
-+	struct slot_tree_node *p;
-+
-+	p = kmem_cache_zalloc(slot_tree_node_cachep, GFP_KERNEL |
-+			      __GFP_NORETRY | __GFP_NOWARN);
-+	if (!p)
-+		return NULL;
-+
-+	return &p->snode;
-+}
-+
-+static void slot_tree_node_free(struct sradix_tree_node *node)
-+{
-+	struct slot_tree_node *p;
-+
-+	p = container_of(node, struct slot_tree_node, snode);
-+	kmem_cache_free(slot_tree_node_cachep, p);
-+}
-+
-+static void slot_tree_node_extend(struct sradix_tree_node *parent,
-+				  struct sradix_tree_node *child)
-+{
-+	struct slot_tree_node *p, *c;
-+
-+	p = container_of(parent, struct slot_tree_node, snode);
-+	c = container_of(child, struct slot_tree_node, snode);
-+
-+	p->size += c->size;
-+}
-+
-+void slot_tree_node_assign(struct sradix_tree_node *node,
-+			   unsigned int index, void *item)
-+{
-+	struct vma_slot *slot = item;
-+	struct slot_tree_node *cur;
-+
-+	slot->snode = node;
-+	slot->sindex = index;
-+
-+	while (node) {
-+		cur = container_of(node, struct slot_tree_node, snode);
-+		cur->size += slot->pages;
-+		node = node->parent;
-+	}
-+}
-+
-+void slot_tree_node_rm(struct sradix_tree_node *node, unsigned int offset)
-+{
-+	struct vma_slot *slot;
-+	struct slot_tree_node *cur;
-+	unsigned long pages;
-+
-+	if (node->height == 1) {
-+		slot = node->stores[offset];
-+		pages = slot->pages;
-+	} else {
-+		cur = container_of(node->stores[offset],
-+				   struct slot_tree_node, snode);
-+		pages = cur->size;
-+	}
-+
-+	while (node) {
-+		cur = container_of(node, struct slot_tree_node, snode);
-+		cur->size -= pages;
-+		node = node->parent;
-+	}
-+}
-+
-+unsigned long slot_iter_index;
-+int slot_iter(void *item,  unsigned long height)
-+{
-+	struct slot_tree_node *node;
-+	struct vma_slot *slot;
-+
-+	if (height == 1) {
-+		slot = item;
-+		if (slot_iter_index < slot->pages) {
-+			/*in this one*/
-+			return 1;
-+		} else {
-+			slot_iter_index -= slot->pages;
-+			return 0;
-+		}
-+
-+	} else {
-+		node = container_of(item, struct slot_tree_node, snode);
-+		if (slot_iter_index < node->size) {
-+			/*in this one*/
-+			return 1;
-+		} else {
-+			slot_iter_index -= node->size;
-+			return 0;
-+		}
-+	}
-+}
-+
-+
-+static inline void slot_tree_init_root(struct sradix_tree_root *root)
-+{
-+	init_sradix_tree_root(root, SLOT_TREE_NODE_SHIFT);
-+	root->alloc = slot_tree_node_alloc;
-+	root->free = slot_tree_node_free;
-+	root->extend = slot_tree_node_extend;
-+	root->assign = slot_tree_node_assign;
-+	root->rm = slot_tree_node_rm;
-+}
-+
-+void slot_tree_init(void)
-+{
-+	slot_tree_node_cachep = kmem_cache_create("slot_tree_node",
-+				sizeof(struct slot_tree_node), 0,
-+				SLAB_PANIC | SLAB_RECLAIM_ACCOUNT,
-+				NULL);
-+}
-+
-+
-+/* Each rung of this ladder is a list of VMAs having a same scan ratio */
-+struct scan_rung {
-+	//struct list_head scanned_list;
-+	struct sradix_tree_root vma_root;
-+	struct sradix_tree_root vma_root2;
-+
-+	struct vma_slot *current_scan;
-+	unsigned long current_offset;
-+
-+	/*
-+	 * The initial value for current_offset, it should loop over
-+	 * [0~ step - 1] to let all slot have its chance to be scanned.
-+	 */
-+	unsigned long offset_init;
-+	unsigned long step; /* dynamic step for current_offset */
-+	unsigned int flags;
-+	unsigned long pages_to_scan;
-+	//unsigned long fully_scanned_slots;
-+	/*
-+	 * a little bit tricky - if cpu_time_ratio > 0, then the value is the
-+	 * the cpu time ratio it can spend in rung_i for every scan
-+	 * period. if < 0, then it is the cpu time ratio relative to the
-+	 * max cpu percentage user specified. Both in unit of
-+	 * 1/TIME_RATIO_SCALE
-+	 */
-+	int cpu_ratio;
-+
-+	/*
-+	 * How long it will take for all slots in this rung to be fully
-+	 * scanned? If it's zero, we don't care about the cover time:
-+	 * it's fully scanned.
-+	 */
-+	unsigned int cover_msecs;
-+	//unsigned long vma_num;
-+	//unsigned long pages; /* Sum of all slot's pages in rung */
-+};
-+
-+/**
-+ * node of either the stable or unstale rbtree
-+ *
-+ */
-+struct tree_node {
-+	struct rb_node node; /* link in the main (un)stable rbtree */
-+	struct rb_root sub_root; /* rb_root for sublevel collision rbtree */
-+	u32 hash;
-+	unsigned long count; /* TODO: merged with sub_root */
-+	struct list_head all_list; /* all tree nodes in stable/unstable tree */
-+};
-+
-+/**
-+ * struct stable_node - node of the stable rbtree
-+ * @node: rb node of this ksm page in the stable tree
-+ * @hlist: hlist head of rmap_items using this ksm page
-+ * @kpfn: page frame number of this ksm page
-+ */
-+struct stable_node {
-+	struct rb_node node; /* link in sub-rbtree */
-+	struct tree_node *tree_node; /* it's tree node root in stable tree, NULL if it's in hell list */
-+	struct hlist_head hlist;
-+	unsigned long kpfn;
-+	u32 hash_max; /* if ==0 then it's not been calculated yet */
-+	struct list_head all_list; /* in a list for all stable nodes */
-+};
-+
-+/**
-+ * struct node_vma - group rmap_items linked in a same stable
-+ * node together.
-+ */
-+struct node_vma {
-+	union {
-+		struct vma_slot *slot;
-+		unsigned long key;  /* slot is used as key sorted on hlist */
-+	};
-+	struct hlist_node hlist;
-+	struct hlist_head rmap_hlist;
-+	struct stable_node *head;
-+};
-+
-+/**
-+ * struct rmap_item - reverse mapping item for virtual addresses
-+ * @rmap_list: next rmap_item in mm_slot's singly-linked rmap_list
-+ * @anon_vma: pointer to anon_vma for this mm,address, when in stable tree
-+ * @mm: the memory structure this rmap_item is pointing into
-+ * @address: the virtual address this rmap_item tracks (+ flags in low bits)
-+ * @node: rb node of this rmap_item in the unstable tree
-+ * @head: pointer to stable_node heading this list in the stable tree
-+ * @hlist: link into hlist of rmap_items hanging off that stable_node
-+ */
-+struct rmap_item {
-+	struct vma_slot *slot;
-+	struct page *page;
-+	unsigned long address;	/* + low bits used for flags below */
-+	unsigned long hash_round;
-+	unsigned long entry_index;
-+	union {
-+		struct {/* when in unstable tree */
-+			struct rb_node node;
-+			struct tree_node *tree_node;
-+			u32 hash_max;
-+		};
-+		struct { /* when in stable tree */
-+			struct node_vma *head;
-+			struct hlist_node hlist;
-+			struct anon_vma *anon_vma;
-+		};
-+	};
-+} __aligned(4);
-+
-+struct rmap_list_entry {
-+	union {
-+		struct rmap_item *item;
-+		unsigned long addr;
-+	};
-+	/* lowest bit is used for is_addr tag */
-+} __aligned(4); /* 4 aligned to fit in to pages*/
-+
-+
-+/* Basic data structure definition ends */
-+
-+
-+/*
-+ * Flags for rmap_item to judge if it's listed in the stable/unstable tree.
-+ * The flags use the low bits of rmap_item.address
-+ */
-+#define UNSTABLE_FLAG	0x1
-+#define STABLE_FLAG	0x2
-+#define get_rmap_addr(x)	((x)->address & PAGE_MASK)
-+
-+/*
-+ * rmap_list_entry helpers
-+ */
-+#define IS_ADDR_FLAG	1
-+#define is_addr(ptr)		((unsigned long)(ptr) & IS_ADDR_FLAG)
-+#define set_is_addr(ptr)	((ptr) |= IS_ADDR_FLAG)
-+#define get_clean_addr(ptr)	(((ptr) & ~(__typeof__(ptr))IS_ADDR_FLAG))
-+
-+
-+/*
-+ * High speed caches for frequently allocated and freed structs
-+ */
-+static struct kmem_cache *rmap_item_cache;
-+static struct kmem_cache *stable_node_cache;
-+static struct kmem_cache *node_vma_cache;
-+static struct kmem_cache *vma_slot_cache;
-+static struct kmem_cache *tree_node_cache;
-+#define UKSM_KMEM_CACHE(__struct, __flags) kmem_cache_create("uksm_"#__struct,\
-+		sizeof(struct __struct), __alignof__(struct __struct),\
-+		(__flags), NULL)
-+
-+/* Array of all scan_rung, uksm_scan_ladder[0] having the minimum scan ratio */
-+#define SCAN_LADDER_SIZE 4
-+static struct scan_rung uksm_scan_ladder[SCAN_LADDER_SIZE];
-+
-+/* The evaluation rounds uksmd has finished */
-+static unsigned long long uksm_eval_round = 1;
-+
-+/*
-+ * we add 1 to this var when we consider we should rebuild the whole
-+ * unstable tree.
-+ */
-+static unsigned long uksm_hash_round = 1;
-+
-+/*
-+ * How many times the whole memory is scanned.
-+ */
-+static unsigned long long fully_scanned_round = 1;
-+
-+/* The total number of virtual pages of all vma slots */
-+static u64 uksm_pages_total;
-+
-+/* The number of pages has been scanned since the start up */
-+static u64 uksm_pages_scanned;
-+
-+static u64 scanned_virtual_pages;
-+
-+/* The number of pages has been scanned since last encode_benefit call */
-+static u64 uksm_pages_scanned_last;
-+
-+/* If the scanned number is tooo large, we encode it here */
-+static u64 pages_scanned_stored;
-+
-+static unsigned long pages_scanned_base;
-+
-+/* The number of nodes in the stable tree */
-+static unsigned long uksm_pages_shared;
-+
-+/* The number of page slots additionally sharing those nodes */
-+static unsigned long uksm_pages_sharing;
-+
-+/* The number of nodes in the unstable tree */
-+static unsigned long uksm_pages_unshared;
-+
-+/*
-+ * Milliseconds ksmd should sleep between scans,
-+ * >= 100ms to be consistent with
-+ * scan_time_to_sleep_msec()
-+ */
-+static unsigned int uksm_sleep_jiffies;
-+
-+/* The real value for the uksmd next sleep */
-+static unsigned int uksm_sleep_real;
-+
-+/* Saved value for user input uksm_sleep_jiffies when it's enlarged */
-+static unsigned int uksm_sleep_saved;
-+
-+/* Max percentage of cpu utilization ksmd can take to scan in one batch */
-+static unsigned int uksm_max_cpu_percentage;
-+
-+static int uksm_cpu_governor;
-+
-+static char *uksm_cpu_governor_str[4] = { "full", "medium", "low", "quiet" };
-+
-+struct uksm_cpu_preset_s {
-+	int cpu_ratio[SCAN_LADDER_SIZE];
-+	unsigned int cover_msecs[SCAN_LADDER_SIZE];
-+	unsigned int max_cpu; /* percentage */
-+};
-+
-+struct uksm_cpu_preset_s uksm_cpu_preset[4] = {
-+	{ {20, 40, -2500, -10000}, {1000, 500, 200, 50}, 95},
-+	{ {20, 30, -2500, -10000}, {1000, 500, 400, 100}, 50},
-+	{ {10, 20, -5000, -10000}, {1500, 1000, 1000, 250}, 20},
-+	{ {10, 20, 40, 75}, {2000, 1000, 1000, 1000}, 1},
-+};
-+
-+/* The default value for uksm_ema_page_time if it's not initialized */
-+#define UKSM_PAGE_TIME_DEFAULT	500
-+
-+/*cost to scan one page by expotional moving average in nsecs */
-+static unsigned long uksm_ema_page_time = UKSM_PAGE_TIME_DEFAULT;
-+
-+/* The expotional moving average alpha weight, in percentage. */
-+#define EMA_ALPHA	20
-+
-+/*
-+ * The threshold used to filter out thrashing areas,
-+ * If it == 0, filtering is disabled, otherwise it's the percentage up-bound
-+ * of the thrashing ratio of all areas. Any area with a bigger thrashing ratio
-+ * will be considered as having a zero duplication ratio.
-+ */
-+static unsigned int uksm_thrash_threshold = 50;
-+
-+/* How much dedup ratio is considered to be abundant*/
-+static unsigned int uksm_abundant_threshold = 10;
-+
-+/* All slots having merged pages in this eval round. */
-+struct list_head vma_slot_dedup = LIST_HEAD_INIT(vma_slot_dedup);
-+
-+/* How many times the ksmd has slept since startup */
-+static unsigned long long uksm_sleep_times;
-+
-+#define UKSM_RUN_STOP	0
-+#define UKSM_RUN_MERGE	1
-+static unsigned int uksm_run = 1;
-+
-+static DECLARE_WAIT_QUEUE_HEAD(uksm_thread_wait);
-+static DEFINE_MUTEX(uksm_thread_mutex);
-+
-+/*
-+ * List vma_slot_new is for newly created vma_slot waiting to be added by
-+ * ksmd. If one cannot be added(e.g. due to it's too small), it's moved to
-+ * vma_slot_noadd. vma_slot_del is the list for vma_slot whose corresponding
-+ * VMA has been removed/freed.
-+ */
-+struct list_head vma_slot_new = LIST_HEAD_INIT(vma_slot_new);
-+struct list_head vma_slot_noadd = LIST_HEAD_INIT(vma_slot_noadd);
-+struct list_head vma_slot_del = LIST_HEAD_INIT(vma_slot_del);
-+static DEFINE_SPINLOCK(vma_slot_list_lock);
-+
-+/* The unstable tree heads */
-+static struct rb_root root_unstable_tree = RB_ROOT;
-+
-+/*
-+ * All tree_nodes are in a list to be freed at once when unstable tree is
-+ * freed after each scan round.
-+ */
-+static struct list_head unstable_tree_node_list =
-+				LIST_HEAD_INIT(unstable_tree_node_list);
-+
-+/* List contains all stable nodes */
-+static struct list_head stable_node_list = LIST_HEAD_INIT(stable_node_list);
-+
-+/*
-+ * When the hash strength is changed, the stable tree must be delta_hashed and
-+ * re-structured. We use two set of below structs to speed up the
-+ * re-structuring of stable tree.
-+ */
-+static struct list_head
-+stable_tree_node_list[2] = {LIST_HEAD_INIT(stable_tree_node_list[0]),
-+			    LIST_HEAD_INIT(stable_tree_node_list[1])};
-+
-+static struct list_head *stable_tree_node_listp = &stable_tree_node_list[0];
-+static struct rb_root root_stable_tree[2] = {RB_ROOT, RB_ROOT};
-+static struct rb_root *root_stable_treep = &root_stable_tree[0];
-+static unsigned long stable_tree_index;
-+
-+/* The hash strength needed to hash a full page */
-+#define HASH_STRENGTH_FULL		(PAGE_SIZE / sizeof(u32))
-+
-+/* The hash strength needed for loop-back hashing */
-+#define HASH_STRENGTH_MAX		(HASH_STRENGTH_FULL + 10)
-+
-+/* The random offsets in a page */
-+static u32 *random_nums;
-+
-+/* The hash strength */
-+static unsigned long hash_strength = HASH_STRENGTH_FULL >> 4;
-+
-+/* The delta value each time the hash strength increases or decreases */
-+static unsigned long hash_strength_delta;
-+#define HASH_STRENGTH_DELTA_MAX	5
-+
-+/* The time we have saved due to random_sample_hash */
-+static u64 rshash_pos;
-+
-+/* The time we have wasted due to hash collision */
-+static u64 rshash_neg;
-+
-+struct uksm_benefit {
-+	u64 pos;
-+	u64 neg;
-+	u64 scanned;
-+	unsigned long base;
-+} benefit;
-+
-+/*
-+ * The relative cost of memcmp, compared to 1 time unit of random sample
-+ * hash, this value is tested when ksm module is initialized
-+ */
-+static unsigned long memcmp_cost;
-+
-+static unsigned long  rshash_neg_cont_zero;
-+static unsigned long  rshash_cont_obscure;
-+
-+/* The possible states of hash strength adjustment heuristic */
-+enum rshash_states {
-+		RSHASH_STILL,
-+		RSHASH_TRYUP,
-+		RSHASH_TRYDOWN,
-+		RSHASH_NEW,
-+		RSHASH_PRE_STILL,
-+};
-+
-+/* The possible direction we are about to adjust hash strength */
-+enum rshash_direct {
-+	GO_UP,
-+	GO_DOWN,
-+	OBSCURE,
-+	STILL,
-+};
-+
-+/* random sampling hash state machine */
-+static struct {
-+	enum rshash_states state;
-+	enum rshash_direct pre_direct;
-+	u8 below_count;
-+	/* Keep a lookup window of size 5, iff above_count/below_count > 3
-+	 * in this window we stop trying.
-+	 */
-+	u8 lookup_window_index;
-+	u64 stable_benefit;
-+	unsigned long turn_point_down;
-+	unsigned long turn_benefit_down;
-+	unsigned long turn_point_up;
-+	unsigned long turn_benefit_up;
-+	unsigned long stable_point;
-+} rshash_state;
-+
-+/*zero page hash table, hash_strength [0 ~ HASH_STRENGTH_MAX]*/
-+static u32 *zero_hash_table;
-+
-+static inline struct node_vma *alloc_node_vma(void)
-+{
-+	struct node_vma *node_vma;
-+
-+	node_vma = kmem_cache_zalloc(node_vma_cache, GFP_KERNEL |
-+				     __GFP_NORETRY | __GFP_NOWARN);
-+	if (node_vma) {
-+		INIT_HLIST_HEAD(&node_vma->rmap_hlist);
-+		INIT_HLIST_NODE(&node_vma->hlist);
-+	}
-+	return node_vma;
-+}
-+
-+static inline void free_node_vma(struct node_vma *node_vma)
-+{
-+	kmem_cache_free(node_vma_cache, node_vma);
-+}
-+
-+
-+static inline struct vma_slot *alloc_vma_slot(void)
-+{
-+	struct vma_slot *slot;
-+
-+	/*
-+	 * In case ksm is not initialized by now.
-+	 * Oops, we need to consider the call site of uksm_init() in the future.
-+	 */
-+	if (!vma_slot_cache)
-+		return NULL;
-+
-+	slot = kmem_cache_zalloc(vma_slot_cache, GFP_KERNEL |
-+				 __GFP_NORETRY | __GFP_NOWARN);
-+	if (slot) {
-+		INIT_LIST_HEAD(&slot->slot_list);
-+		INIT_LIST_HEAD(&slot->dedup_list);
-+		slot->flags |= UKSM_SLOT_NEED_RERAND;
-+	}
-+	return slot;
-+}
-+
-+static inline void free_vma_slot(struct vma_slot *vma_slot)
-+{
-+	kmem_cache_free(vma_slot_cache, vma_slot);
-+}
-+
-+
-+
-+static inline struct rmap_item *alloc_rmap_item(void)
-+{
-+	struct rmap_item *rmap_item;
-+
-+	rmap_item = kmem_cache_zalloc(rmap_item_cache, GFP_KERNEL |
-+				      __GFP_NORETRY | __GFP_NOWARN);
-+	if (rmap_item) {
-+		/* bug on lowest bit is not clear for flag use */
-+		BUG_ON(is_addr(rmap_item));
-+	}
-+	return rmap_item;
-+}
-+
-+static inline void free_rmap_item(struct rmap_item *rmap_item)
-+{
-+	rmap_item->slot = NULL;	/* debug safety */
-+	kmem_cache_free(rmap_item_cache, rmap_item);
-+}
-+
-+static inline struct stable_node *alloc_stable_node(void)
-+{
-+	struct stable_node *node;
-+
-+	node = kmem_cache_alloc(stable_node_cache, GFP_KERNEL |
-+				__GFP_NORETRY | __GFP_NOWARN);
-+	if (!node)
-+		return NULL;
-+
-+	INIT_HLIST_HEAD(&node->hlist);
-+	list_add(&node->all_list, &stable_node_list);
-+	return node;
-+}
-+
-+static inline void free_stable_node(struct stable_node *stable_node)
-+{
-+	list_del(&stable_node->all_list);
-+	kmem_cache_free(stable_node_cache, stable_node);
-+}
-+
-+static inline struct tree_node *alloc_tree_node(struct list_head *list)
-+{
-+	struct tree_node *node;
-+
-+	node = kmem_cache_zalloc(tree_node_cache, GFP_KERNEL |
-+				 __GFP_NORETRY | __GFP_NOWARN);
-+	if (!node)
-+		return NULL;
-+
-+	list_add(&node->all_list, list);
-+	return node;
-+}
-+
-+static inline void free_tree_node(struct tree_node *node)
-+{
-+	list_del(&node->all_list);
-+	kmem_cache_free(tree_node_cache, node);
-+}
-+
-+static void uksm_drop_anon_vma(struct rmap_item *rmap_item)
-+{
-+	struct anon_vma *anon_vma = rmap_item->anon_vma;
-+
-+	put_anon_vma(anon_vma);
-+}
-+
-+
-+/**
-+ * Remove a stable node from stable_tree, may unlink from its tree_node and
-+ * may remove its parent tree_node if no other stable node is pending.
-+ *
-+ * @stable_node	    The node need to be removed
-+ * @unlink_rb	    Will this node be unlinked from the rbtree?
-+ * @remove_tree_    node Will its tree_node be removed if empty?
-+ */
-+static void remove_node_from_stable_tree(struct stable_node *stable_node,
-+					 int unlink_rb,  int remove_tree_node)
-+{
-+	struct node_vma *node_vma;
-+	struct rmap_item *rmap_item;
-+	struct hlist_node *n;
-+
-+	if (!hlist_empty(&stable_node->hlist)) {
-+		hlist_for_each_entry_safe(node_vma, n,
-+					  &stable_node->hlist, hlist) {
-+			hlist_for_each_entry(rmap_item, &node_vma->rmap_hlist, hlist) {
-+				uksm_pages_sharing--;
-+
-+				uksm_drop_anon_vma(rmap_item);
-+				rmap_item->address &= PAGE_MASK;
-+			}
-+			free_node_vma(node_vma);
-+			cond_resched();
-+		}
-+
-+		/* the last one is counted as shared */
-+		uksm_pages_shared--;
-+		uksm_pages_sharing++;
-+	}
-+
-+	if (stable_node->tree_node && unlink_rb) {
-+		rb_erase(&stable_node->node,
-+			 &stable_node->tree_node->sub_root);
-+
-+		if (RB_EMPTY_ROOT(&stable_node->tree_node->sub_root) &&
-+		    remove_tree_node) {
-+			rb_erase(&stable_node->tree_node->node,
-+				 root_stable_treep);
-+			free_tree_node(stable_node->tree_node);
-+		} else {
-+			stable_node->tree_node->count--;
-+		}
-+	}
-+
-+	free_stable_node(stable_node);
-+}
-+
-+
-+/*
-+ * get_uksm_page: checks if the page indicated by the stable node
-+ * is still its ksm page, despite having held no reference to it.
-+ * In which case we can trust the content of the page, and it
-+ * returns the gotten page; but if the page has now been zapped,
-+ * remove the stale node from the stable tree and return NULL.
-+ *
-+ * You would expect the stable_node to hold a reference to the ksm page.
-+ * But if it increments the page's count, swapping out has to wait for
-+ * ksmd to come around again before it can free the page, which may take
-+ * seconds or even minutes: much too unresponsive.  So instead we use a
-+ * "keyhole reference": access to the ksm page from the stable node peeps
-+ * out through its keyhole to see if that page still holds the right key,
-+ * pointing back to this stable node.  This relies on freeing a PageAnon
-+ * page to reset its page->mapping to NULL, and relies on no other use of
-+ * a page to put something that might look like our key in page->mapping.
-+ *
-+ * include/linux/pagemap.h page_cache_get_speculative() is a good reference,
-+ * but this is different - made simpler by uksm_thread_mutex being held, but
-+ * interesting for assuming that no other use of the struct page could ever
-+ * put our expected_mapping into page->mapping (or a field of the union which
-+ * coincides with page->mapping).  The RCU calls are not for KSM at all, but
-+ * to keep the page_count protocol described with page_cache_get_speculative.
-+ *
-+ * Note: it is possible that get_uksm_page() will return NULL one moment,
-+ * then page the next, if the page is in between page_freeze_refs() and
-+ * page_unfreeze_refs(): this shouldn't be a problem anywhere, the page
-+ * is on its way to being freed; but it is an anomaly to bear in mind.
-+ *
-+ * @unlink_rb:			if the removal of this node will firstly unlink from
-+ * its rbtree. stable_node_reinsert will prevent this when restructuring the
-+ * node from its old tree.
-+ *
-+ * @remove_tree_node:	if this is the last one of its tree_node, will the
-+ * tree_node be freed ? If we are inserting stable node, this tree_node may
-+ * be reused, so don't free it.
-+ */
-+static struct page *get_uksm_page(struct stable_node *stable_node,
-+				 int unlink_rb, int remove_tree_node)
-+{
-+	struct page *page;
-+	void *expected_mapping;
-+	unsigned long kpfn;
-+
-+	expected_mapping = (void *)((unsigned long)stable_node |
-+				    PAGE_MAPPING_KSM);
-+again:
-+	kpfn = READ_ONCE(stable_node->kpfn);
-+	page = pfn_to_page(kpfn);
-+
-+	/*
-+	 * page is computed from kpfn, so on most architectures reading
-+	 * page->mapping is naturally ordered after reading node->kpfn,
-+	 * but on Alpha we need to be more careful.
-+	 */
-+	smp_rmb();
-+
-+	if (READ_ONCE(page->mapping) != expected_mapping)
-+		goto stale;
-+
-+	/*
-+	 * We cannot do anything with the page while its refcount is 0.
-+	 * Usually 0 means free, or tail of a higher-order page: in which
-+	 * case this node is no longer referenced, and should be freed;
-+	 * however, it might mean that the page is under page_freeze_refs().
-+	 * The __remove_mapping() case is easy, again the node is now stale;
-+	 * but if page is swapcache in migrate_page_move_mapping(), it might
-+	 * still be our page, in which case it's essential to keep the node.
-+	 */
-+	while (!get_page_unless_zero(page)) {
-+		/*
-+		 * Another check for page->mapping != expected_mapping would
-+		 * work here too.  We have chosen the !PageSwapCache test to
-+		 * optimize the common case, when the page is or is about to
-+		 * be freed: PageSwapCache is cleared (under spin_lock_irq)
-+		 * in the freeze_refs section of __remove_mapping(); but Anon
-+		 * page->mapping reset to NULL later, in free_pages_prepare().
-+		 */
-+		if (!PageSwapCache(page))
-+			goto stale;
-+		cpu_relax();
-+	}
-+
-+	if (READ_ONCE(page->mapping) != expected_mapping) {
-+		put_page(page);
-+		goto stale;
-+	}
-+
-+	lock_page(page);
-+	if (READ_ONCE(page->mapping) != expected_mapping) {
-+		unlock_page(page);
-+		put_page(page);
-+		goto stale;
-+	}
-+	unlock_page(page);
-+	return page;
-+stale:
-+	/*
-+	 * We come here from above when page->mapping or !PageSwapCache
-+	 * suggests that the node is stale; but it might be under migration.
-+	 * We need smp_rmb(), matching the smp_wmb() in folio_migrate_ksm(),
-+	 * before checking whether node->kpfn has been changed.
-+	 */
-+	smp_rmb();
-+	if (stable_node->kpfn != kpfn)
-+		goto again;
-+
-+	remove_node_from_stable_tree(stable_node, unlink_rb, remove_tree_node);
-+
-+	return NULL;
-+}
-+
-+/*
-+ * Removing rmap_item from stable or unstable tree.
-+ * This function will clean the information from the stable/unstable tree.
-+ */
-+static inline void remove_rmap_item_from_tree(struct rmap_item *rmap_item)
-+{
-+	if (rmap_item->address & STABLE_FLAG) {
-+		struct stable_node *stable_node;
-+		struct node_vma *node_vma;
-+		struct page *page;
-+
-+		node_vma = rmap_item->head;
-+		stable_node = node_vma->head;
-+		page = get_uksm_page(stable_node, 1, 1);
-+		if (!page)
-+			goto out;
-+
-+		/*
-+		 * page lock is needed because it's racing with
-+		 * try_to_unmap_ksm(), etc.
-+		 */
-+		lock_page(page);
-+		hlist_del(&rmap_item->hlist);
-+
-+		if (hlist_empty(&node_vma->rmap_hlist)) {
-+			hlist_del(&node_vma->hlist);
-+			free_node_vma(node_vma);
-+		}
-+		unlock_page(page);
-+
-+		put_page(page);
-+		if (hlist_empty(&stable_node->hlist)) {
-+			/* do NOT call remove_node_from_stable_tree() here,
-+			 * it's possible for a forked rmap_item not in
-+			 * stable tree while the in-tree rmap_items were
-+			 * deleted.
-+			 */
-+			uksm_pages_shared--;
-+		} else
-+			uksm_pages_sharing--;
-+
-+
-+		uksm_drop_anon_vma(rmap_item);
-+	} else if (rmap_item->address & UNSTABLE_FLAG) {
-+		if (rmap_item->hash_round == uksm_hash_round) {
-+
-+			rb_erase(&rmap_item->node,
-+				 &rmap_item->tree_node->sub_root);
-+			if (RB_EMPTY_ROOT(&rmap_item->tree_node->sub_root)) {
-+				rb_erase(&rmap_item->tree_node->node,
-+					 &root_unstable_tree);
-+
-+				free_tree_node(rmap_item->tree_node);
-+			} else
-+				rmap_item->tree_node->count--;
-+		}
-+		uksm_pages_unshared--;
-+	}
-+
-+	rmap_item->address &= PAGE_MASK;
-+	rmap_item->hash_max = 0;
-+
-+out:
-+	cond_resched();		/* we're called from many long loops */
-+}
-+
-+static inline int slot_in_uksm(struct vma_slot *slot)
-+{
-+	return list_empty(&slot->slot_list);
-+}
-+
-+/*
-+ * Test if the mm is exiting
-+ */
-+static inline bool uksm_test_exit(struct mm_struct *mm)
-+{
-+	return atomic_read(&mm->mm_users) == 0;
-+}
-+
-+static inline unsigned long vma_pool_size(struct vma_slot *slot)
-+{
-+	return round_up(sizeof(struct rmap_list_entry) * slot->pages,
-+			PAGE_SIZE) >> PAGE_SHIFT;
-+}
-+
-+#define CAN_OVERFLOW_U64(x, delta) (U64_MAX - (x) < (delta))
-+
-+/* must be done with sem locked */
-+static int slot_pool_alloc(struct vma_slot *slot)
-+{
-+	unsigned long pool_size;
-+
-+	if (slot->rmap_list_pool)
-+		return 0;
-+
-+	pool_size = vma_pool_size(slot);
-+	slot->rmap_list_pool = kcalloc(pool_size, sizeof(struct page *),
-+				       GFP_KERNEL);
-+	if (!slot->rmap_list_pool)
-+		return -ENOMEM;
-+
-+	slot->pool_counts = kcalloc(pool_size, sizeof(unsigned int),
-+				    GFP_KERNEL);
-+	if (!slot->pool_counts) {
-+		kfree(slot->rmap_list_pool);
-+		return -ENOMEM;
-+	}
-+
-+	slot->pool_size = pool_size;
-+	BUG_ON(CAN_OVERFLOW_U64(uksm_pages_total, slot->pages));
-+	slot->flags |= UKSM_SLOT_IN_UKSM;
-+	uksm_pages_total += slot->pages;
-+
-+	return 0;
-+}
-+
-+/*
-+ * Called after vma is unlinked from its mm
-+ */
-+void uksm_remove_vma(struct vm_area_struct *vma)
-+{
-+	struct vma_slot *slot;
-+
-+	if (!vma->uksm_vma_slot)
-+		return;
-+
-+	spin_lock(&vma_slot_list_lock);
-+	slot = vma->uksm_vma_slot;
-+	if (!slot)
-+		goto out;
-+
-+	if (slot_in_uksm(slot)) {
-+		/**
-+		 * This slot has been added by ksmd, so move to the del list
-+		 * waiting ksmd to free it.
-+		 */
-+		list_add_tail(&slot->slot_list, &vma_slot_del);
-+	} else {
-+		/**
-+		 * It's still on new list. It's ok to free slot directly.
-+		 */
-+		list_del(&slot->slot_list);
-+		free_vma_slot(slot);
-+	}
-+out:
-+	vma->uksm_vma_slot = NULL;
-+	spin_unlock(&vma_slot_list_lock);
-+}
-+
-+/**
-+ * Need to do two things:
-+ * 1. check if slot was moved to del list
-+ * 2. make sure the mmap_sem is manipulated under valid vma.
-+ *
-+ * My concern here is that in some cases, this may make
-+ * vma_slot_list_lock() waiters to serialized further by some
-+ * sem->wait_lock, can this really be expensive?
-+ *
-+ *
-+ * @return
-+ * 0: if successfully locked mmap_sem
-+ * -ENOENT: this slot was moved to del list
-+ * -EBUSY: vma lock failed
-+ */
-+static int try_down_read_slot_mmap_sem(struct vma_slot *slot)
-+{
-+	struct vm_area_struct *vma;
-+	struct mm_struct *mm;
-+	struct rw_semaphore *sem;
-+
-+	spin_lock(&vma_slot_list_lock);
-+
-+	/* the slot_list was removed and inited from new list, when it enters
-+	 * uksm_list. If now it's not empty, then it must be moved to del list
-+	 */
-+	if (!slot_in_uksm(slot)) {
-+		spin_unlock(&vma_slot_list_lock);
-+		return -ENOENT;
-+	}
-+
-+	BUG_ON(slot->pages != vma_pages(slot->vma));
-+	/* Ok, vma still valid */
-+	vma = slot->vma;
-+	mm = vma->vm_mm;
-+	sem = &mm->mmap_lock;
-+
-+	if (uksm_test_exit(mm)) {
-+		spin_unlock(&vma_slot_list_lock);
-+		return -ENOENT;
-+	}
-+
-+	if (down_read_trylock(sem)) {
-+		spin_unlock(&vma_slot_list_lock);
-+		if (slot_pool_alloc(slot)) {
-+			uksm_remove_vma(vma);
-+			up_read(sem);
-+			return -ENOENT;
-+		}
-+		return 0;
-+	}
-+
-+	spin_unlock(&vma_slot_list_lock);
-+	return -EBUSY;
-+}
-+
-+static inline unsigned long
-+vma_page_address(struct page *page, struct vm_area_struct *vma)
-+{
-+	pgoff_t pgoff = page->index;
-+	unsigned long address;
-+
-+	address = vma->vm_start + ((pgoff - vma->vm_pgoff) << PAGE_SHIFT);
-+	if (unlikely(address < vma->vm_start || address >= vma->vm_end)) {
-+		/* page should be within @vma mapping range */
-+		return -EFAULT;
-+	}
-+	return address;
-+}
-+
-+
-+/* return 0 on success with the item's mmap_sem locked */
-+static inline int get_mergeable_page_lock_mmap(struct rmap_item *item)
-+{
-+	struct mm_struct *mm;
-+	struct vma_slot *slot = item->slot;
-+	int err = -EINVAL;
-+
-+	struct page *page;
-+
-+	/*
-+	 * try_down_read_slot_mmap_sem() returns non-zero if the slot
-+	 * has been removed by uksm_remove_vma().
-+	 */
-+	if (try_down_read_slot_mmap_sem(slot))
-+		return -EBUSY;
-+
-+	mm = slot->vma->vm_mm;
-+
-+	if (uksm_test_exit(mm))
-+		goto failout_up;
-+
-+	page = item->page;
-+	rcu_read_lock();
-+	if (!get_page_unless_zero(page)) {
-+		rcu_read_unlock();
-+		goto failout_up;
-+	}
-+
-+	/* No need to consider huge page here. */
-+	if (item->slot->vma->anon_vma != page_anon_vma(page) ||
-+	    vma_page_address(page, item->slot->vma) != get_rmap_addr(item)) {
-+		/*
-+		 * TODO:
-+		 * should we release this item becase of its stale page
-+		 * mapping?
-+		 */
-+		put_page(page);
-+		rcu_read_unlock();
-+		goto failout_up;
-+	}
-+	rcu_read_unlock();
-+	return 0;
-+
-+failout_up:
-+	mmap_read_unlock(mm);
-+	return err;
-+}
-+
-+/*
-+ * What kind of VMA is considered ?
-+ */
-+static inline int vma_can_enter(struct vm_area_struct *vma)
-+{
-+	return uksm_flags_can_scan(vma->vm_flags);
-+}
-+
-+/*
-+ * Called whenever a fresh new vma is created A new vma_slot.
-+ * is created and inserted into a global list Must be called.
-+ * after vma is inserted to its mm.
-+ */
-+void uksm_vma_add_new(struct vm_area_struct *vma)
-+{
-+	struct vma_slot *slot;
-+
-+	if (!vma_can_enter(vma)) {
-+		vma->uksm_vma_slot = NULL;
-+		return;
-+	}
-+
-+	slot = alloc_vma_slot();
-+	if (!slot) {
-+		vma->uksm_vma_slot = NULL;
-+		return;
-+	}
-+
-+	vma->uksm_vma_slot = slot;
-+	vma->vm_flags |= VM_MERGEABLE;
-+	slot->vma = vma;
-+	slot->mm = vma->vm_mm;
-+	slot->ctime_j = jiffies;
-+	slot->pages = vma_pages(vma);
-+	spin_lock(&vma_slot_list_lock);
-+	list_add_tail(&slot->slot_list, &vma_slot_new);
-+	spin_unlock(&vma_slot_list_lock);
-+}
-+
-+/*   32/3 < they < 32/2 */
-+#define shiftl	8
-+#define shiftr	12
-+
-+#define HASH_FROM_TO(from, to)			\
-+for (index = from; index < to; index++) {	\
-+	pos = random_nums[index];		\
-+	hash += key[pos];			\
-+	hash += (hash << shiftl);		\
-+	hash ^= (hash >> shiftr);		\
-+}
-+
-+
-+#define HASH_FROM_DOWN_TO(from, to)		\
-+for (index = from - 1; index >= to; index--) {	\
-+	hash ^= (hash >> shiftr);		\
-+	hash ^= (hash >> (shiftr*2));		\
-+	hash -= (hash << shiftl);		\
-+	hash += (hash << (shiftl*2));		\
-+	pos = random_nums[index];		\
-+	hash -= key[pos];			\
-+}
-+
-+/*
-+ * The main random sample hash function.
-+ */
-+static u32 random_sample_hash(void *addr, u32 hash_strength)
-+{
-+	u32 hash = 0xdeadbeef;
-+	int index, pos, loop = hash_strength;
-+	u32 *key = (u32 *)addr;
-+
-+	if (loop > HASH_STRENGTH_FULL)
-+		loop = HASH_STRENGTH_FULL;
-+
-+	HASH_FROM_TO(0, loop);
-+
-+	if (hash_strength > HASH_STRENGTH_FULL) {
-+		loop = hash_strength - HASH_STRENGTH_FULL;
-+		HASH_FROM_TO(0, loop);
-+	}
-+
-+	return hash;
-+}
-+
-+
-+/**
-+ * It's used when hash strength is adjusted
-+ *
-+ * @addr The page's virtual address
-+ * @from The original hash strength
-+ * @to   The hash strength changed to
-+ * @hash The hash value generated with "from" hash value
-+ *
-+ * return the hash value
-+ */
-+static u32 delta_hash(void *addr, int from, int to, u32 hash)
-+{
-+	u32 *key = (u32 *)addr;
-+	int index, pos; /* make sure they are int type */
-+
-+	if (to > from) {
-+		if (from >= HASH_STRENGTH_FULL) {
-+			from -= HASH_STRENGTH_FULL;
-+			to -= HASH_STRENGTH_FULL;
-+			HASH_FROM_TO(from, to);
-+		} else if (to <= HASH_STRENGTH_FULL) {
-+			HASH_FROM_TO(from, to);
-+		} else {
-+			HASH_FROM_TO(from, HASH_STRENGTH_FULL);
-+			HASH_FROM_TO(0, to - HASH_STRENGTH_FULL);
-+		}
-+	} else {
-+		if (from <= HASH_STRENGTH_FULL) {
-+			HASH_FROM_DOWN_TO(from, to);
-+		} else if (to >= HASH_STRENGTH_FULL) {
-+			from -= HASH_STRENGTH_FULL;
-+			to -= HASH_STRENGTH_FULL;
-+			HASH_FROM_DOWN_TO(from, to);
-+		} else {
-+			HASH_FROM_DOWN_TO(from - HASH_STRENGTH_FULL, 0);
-+			HASH_FROM_DOWN_TO(HASH_STRENGTH_FULL, to);
-+		}
-+	}
-+
-+	return hash;
-+}
-+
-+/**
-+ *
-+ * Called when: rshash_pos or rshash_neg is about to overflow or a scan round
-+ * has finished.
-+ *
-+ * return 0 if no page has been scanned since last call, 1 otherwise.
-+ */
-+static inline int encode_benefit(void)
-+{
-+	u64 scanned_delta, pos_delta, neg_delta;
-+	unsigned long base = benefit.base;
-+
-+	scanned_delta = uksm_pages_scanned - uksm_pages_scanned_last;
-+
-+	if (!scanned_delta)
-+		return 0;
-+
-+	scanned_delta >>= base;
-+	pos_delta = rshash_pos >> base;
-+	neg_delta = rshash_neg >> base;
-+
-+	if (CAN_OVERFLOW_U64(benefit.pos, pos_delta) ||
-+	    CAN_OVERFLOW_U64(benefit.neg, neg_delta) ||
-+	    CAN_OVERFLOW_U64(benefit.scanned, scanned_delta)) {
-+		benefit.scanned >>= 1;
-+		benefit.neg >>= 1;
-+		benefit.pos >>= 1;
-+		benefit.base++;
-+		scanned_delta >>= 1;
-+		pos_delta >>= 1;
-+		neg_delta >>= 1;
-+	}
-+
-+	benefit.pos += pos_delta;
-+	benefit.neg += neg_delta;
-+	benefit.scanned += scanned_delta;
-+
-+	BUG_ON(!benefit.scanned);
-+
-+	rshash_pos = rshash_neg = 0;
-+	uksm_pages_scanned_last = uksm_pages_scanned;
-+
-+	return 1;
-+}
-+
-+static inline void reset_benefit(void)
-+{
-+	benefit.pos = 0;
-+	benefit.neg = 0;
-+	benefit.base = 0;
-+	benefit.scanned = 0;
-+}
-+
-+static inline void inc_rshash_pos(unsigned long delta)
-+{
-+	if (CAN_OVERFLOW_U64(rshash_pos, delta))
-+		encode_benefit();
-+
-+	rshash_pos += delta;
-+}
-+
-+static inline void inc_rshash_neg(unsigned long delta)
-+{
-+	if (CAN_OVERFLOW_U64(rshash_neg, delta))
-+		encode_benefit();
-+
-+	rshash_neg += delta;
-+}
-+
-+
-+static inline u32 page_hash(struct page *page, unsigned long hash_strength,
-+			    int cost_accounting)
-+{
-+	u32 val;
-+	unsigned long delta;
-+
-+	void *addr = kmap_atomic(page);
-+
-+	val = random_sample_hash(addr, hash_strength);
-+	kunmap_atomic(addr);
-+
-+	if (cost_accounting) {
-+		if (hash_strength < HASH_STRENGTH_FULL)
-+			delta = HASH_STRENGTH_FULL - hash_strength;
-+		else
-+			delta = 0;
-+
-+		inc_rshash_pos(delta);
-+	}
-+
-+	return val;
-+}
-+
-+static int memcmp_pages_with_cost(struct page *page1, struct page *page2,
-+			int cost_accounting)
-+{
-+	char *addr1, *addr2;
-+	int ret;
-+
-+	addr1 = kmap_atomic(page1);
-+	addr2 = kmap_atomic(page2);
-+	ret = memcmp(addr1, addr2, PAGE_SIZE);
-+	kunmap_atomic(addr2);
-+	kunmap_atomic(addr1);
-+
-+	if (cost_accounting)
-+		inc_rshash_neg(memcmp_cost);
-+
-+	return ret;
-+}
-+
-+static inline int pages_identical_with_cost(struct page *page1, struct page *page2)
-+{
-+	return !memcmp_pages_with_cost(page1, page2, 0);
-+}
-+
-+static inline int is_page_full_zero(struct page *page)
-+{
-+	char *addr;
-+	int ret;
-+
-+	addr = kmap_atomic(page);
-+	ret = is_full_zero(addr, PAGE_SIZE);
-+	kunmap_atomic(addr);
-+
-+	return ret;
-+}
-+
-+static int write_protect_page(struct vm_area_struct *vma, struct page *page,
-+			      pte_t *orig_pte, pte_t *old_pte)
-+{
-+	struct mm_struct *mm = vma->vm_mm;
-+	struct page_vma_mapped_walk pvmw = {
-+		.page = page,
-+		.vma = vma,
-+	};
-+       struct mmu_notifier_range range;
-+	int swapped;
-+	int err = -EFAULT;
-+
-+	pvmw.address = page_address_in_vma(page, vma);
-+	if (pvmw.address == -EFAULT)
-+		goto out;
-+
-+	BUG_ON(PageTransCompound(page));
-+
-+        mmu_notifier_range_init(&range, MMU_NOTIFY_CLEAR, 0, vma, mm, pvmw.address,
-+                                pvmw.address + PAGE_SIZE);
-+	mmu_notifier_invalidate_range_start(&range);
-+
-+	if (!page_vma_mapped_walk(&pvmw))
-+		goto out_mn;
-+	if (WARN_ONCE(!pvmw.pte, "Unexpected PMD mapping?"))
-+		goto out_unlock;
-+
-+	if (old_pte)
-+		*old_pte = *pvmw.pte;
-+
-+	if (pte_write(*pvmw.pte) || pte_dirty(*pvmw.pte) ||
-+	    (pte_protnone(*pvmw.pte) && pte_savedwrite(*pvmw.pte)) || mm_tlb_flush_pending(mm)) {
-+		pte_t entry;
-+
-+		swapped = PageSwapCache(page);
-+		flush_cache_page(vma, pvmw.address, page_to_pfn(page));
-+		/*
-+		 * Ok this is tricky, when get_user_pages_fast() run it doesn't
-+		 * take any lock, therefore the check that we are going to make
-+		 * with the pagecount against the mapcount is racey and
-+		 * O_DIRECT can happen right after the check.
-+		 * So we clear the pte and flush the tlb before the check
-+		 * this assure us that no O_DIRECT can happen after the check
-+		 * or in the middle of the check.
-+		 */
-+		entry = ptep_clear_flush_notify(vma, pvmw.address, pvmw.pte);
-+		/*
-+		 * Check that no O_DIRECT or similar I/O is in progress on the
-+		 * page
-+		 */
-+		if (page_mapcount(page) + 1 + swapped != page_count(page)) {
-+			set_pte_at(mm, pvmw.address, pvmw.pte, entry);
-+			goto out_unlock;
-+		}
-+		if (pte_dirty(entry))
-+			set_page_dirty(page);
-+
-+		if (pte_protnone(entry))
-+			entry = pte_mkclean(pte_clear_savedwrite(entry));
-+		else
-+			entry = pte_mkclean(pte_wrprotect(entry));
-+
-+		set_pte_at_notify(mm, pvmw.address, pvmw.pte, entry);
-+	}
-+	*orig_pte = *pvmw.pte;
-+	err = 0;
-+
-+out_unlock:
-+	page_vma_mapped_walk_done(&pvmw);
-+out_mn:
-+	mmu_notifier_invalidate_range_end(&range);
-+out:
-+	return err;
-+}
-+
-+#define MERGE_ERR_PGERR		1 /* the page is invalid cannot continue */
-+#define MERGE_ERR_COLLI		2 /* there is a collision */
-+#define MERGE_ERR_COLLI_MAX	3 /* collision at the max hash strength */
-+#define MERGE_ERR_CHANGED	4 /* the page has changed since last hash */
-+
-+
-+/**
-+ * replace_page - replace page in vma by new ksm page
-+ * @vma:      vma that holds the pte pointing to page
-+ * @page:     the page we are replacing by kpage
-+ * @kpage:    the ksm page we replace page by
-+ * @orig_pte: the original value of the pte
-+ *
-+ * Returns 0 on success, MERGE_ERR_PGERR on failure.
-+ */
-+static int replace_page(struct vm_area_struct *vma, struct page *page,
-+			struct page *kpage, pte_t orig_pte)
-+{
-+	struct mm_struct *mm = vma->vm_mm;
-+       struct mmu_notifier_range range;
-+	pgd_t *pgd;
-+	p4d_t *p4d;
-+	pud_t *pud;
-+	pmd_t *pmd;
-+	pte_t *ptep;
-+	spinlock_t *ptl;
-+	pte_t entry;
-+
-+	unsigned long addr;
-+	int err = MERGE_ERR_PGERR;
-+
-+	addr = page_address_in_vma(page, vma);
-+	if (addr == -EFAULT)
-+		goto out;
-+
-+	pgd = pgd_offset(mm, addr);
-+	if (!pgd_present(*pgd))
-+		goto out;
-+
-+	p4d = p4d_offset(pgd, addr);
-+	pud = pud_offset(p4d, addr);
-+	if (!pud_present(*pud))
-+		goto out;
-+
-+	pmd = pmd_offset(pud, addr);
-+	BUG_ON(pmd_trans_huge(*pmd));
-+	if (!pmd_present(*pmd))
-+		goto out;
-+
-+        mmu_notifier_range_init(&range, MMU_NOTIFY_CLEAR, 0, vma, mm, addr,
-+                                addr + PAGE_SIZE);
-+	mmu_notifier_invalidate_range_start(&range);
-+
-+	ptep = pte_offset_map_lock(mm, pmd, addr, &ptl);
-+	if (!pte_same(*ptep, orig_pte)) {
-+		pte_unmap_unlock(ptep, ptl);
-+		goto out_mn;
-+	}
-+
-+	flush_cache_page(vma, addr, pte_pfn(*ptep));
-+	ptep_clear_flush_notify(vma, addr, ptep);
-+	entry = mk_pte(kpage, vma->vm_page_prot);
-+
-+	/* special treatment is needed for zero_page */
-+	if ((page_to_pfn(kpage) == uksm_zero_pfn) ||
-+				(page_to_pfn(kpage) == zero_pfn)) {
-+		entry = pte_mkspecial(entry);
-+		dec_mm_counter(mm, MM_ANONPAGES);
-+		inc_zone_page_state(page, NR_UKSM_ZERO_PAGES);
-+	} else {
-+		get_page(kpage);
-+		page_add_anon_rmap(kpage, vma, addr, false);
-+	}
-+
-+	set_pte_at_notify(mm, addr, ptep, entry);
-+
-+	page_remove_rmap(page, false);
-+	if (!page_mapped(page))
-+		try_to_free_swap(page);
-+	put_page(page);
-+
-+	pte_unmap_unlock(ptep, ptl);
-+	err = 0;
-+out_mn:
-+	mmu_notifier_invalidate_range_end(&range);
-+out:
-+	return err;
-+}
-+
-+
-+/**
-+ *  Fully hash a page with HASH_STRENGTH_MAX return a non-zero hash value. The
-+ *  zero hash value at HASH_STRENGTH_MAX is used to indicated that its
-+ *  hash_max member has not been calculated.
-+ *
-+ * @page The page needs to be hashed
-+ * @hash_old The hash value calculated with current hash strength
-+ *
-+ * return the new hash value calculated at HASH_STRENGTH_MAX
-+ */
-+static inline u32 page_hash_max(struct page *page, u32 hash_old)
-+{
-+	u32 hash_max = 0;
-+	void *addr;
-+
-+	addr = kmap_atomic(page);
-+	hash_max = delta_hash(addr, hash_strength,
-+			      HASH_STRENGTH_MAX, hash_old);
-+
-+	kunmap_atomic(addr);
-+
-+	if (!hash_max)
-+		hash_max = 1;
-+
-+	inc_rshash_neg(HASH_STRENGTH_MAX - hash_strength);
-+	return hash_max;
-+}
-+
-+/*
-+ * We compare the hash again, to ensure that it is really a hash collision
-+ * instead of being caused by page write.
-+ */
-+static inline int check_collision(struct rmap_item *rmap_item,
-+				  u32 hash)
-+{
-+	int err;
-+	struct page *page = rmap_item->page;
-+
-+	/* if this rmap_item has already been hash_maxed, then the collision
-+	 * must appears in the second-level rbtree search. In this case we check
-+	 * if its hash_max value has been changed. Otherwise, the collision
-+	 * happens in the first-level rbtree search, so we check against it's
-+	 * current hash value.
-+	 */
-+	if (rmap_item->hash_max) {
-+		inc_rshash_neg(memcmp_cost);
-+		inc_rshash_neg(HASH_STRENGTH_MAX - hash_strength);
-+
-+		if (rmap_item->hash_max == page_hash_max(page, hash))
-+			err = MERGE_ERR_COLLI;
-+		else
-+			err = MERGE_ERR_CHANGED;
-+	} else {
-+		inc_rshash_neg(memcmp_cost + hash_strength);
-+
-+		if (page_hash(page, hash_strength, 0) == hash)
-+			err = MERGE_ERR_COLLI;
-+		else
-+			err = MERGE_ERR_CHANGED;
-+	}
-+
-+	return err;
-+}
-+
-+/**
-+ * Try to merge a rmap_item.page with a kpage in stable node. kpage must
-+ * already be a ksm page.
-+ *
-+ * @return 0 if the pages were merged, -EFAULT otherwise.
-+ */
-+static int try_to_merge_with_uksm_page(struct rmap_item *rmap_item,
-+				      struct page *kpage, u32 hash)
-+{
-+	struct vm_area_struct *vma = rmap_item->slot->vma;
-+	struct mm_struct *mm = vma->vm_mm;
-+	pte_t orig_pte = __pte(0);
-+	int err = MERGE_ERR_PGERR;
-+	struct page *page;
-+
-+	if (uksm_test_exit(mm))
-+		goto out;
-+
-+	page = rmap_item->page;
-+
-+	if (page == kpage) { /* ksm page forked */
-+		err = 0;
-+		goto out;
-+	}
-+
-+	/*
-+	 * We need the page lock to read a stable PageSwapCache in
-+	 * write_protect_page().  We use trylock_page() instead of
-+	 * lock_page() because we don't want to wait here - we
-+	 * prefer to continue scanning and merging different pages,
-+	 * then come back to this page when it is unlocked.
-+	 */
-+	if (!trylock_page(page))
-+		goto out;
-+
-+	if (!PageAnon(page) || !PageKsm(kpage))
-+		goto out_unlock;
-+
-+	if (PageTransCompound(page)) {
-+		err = split_huge_page(page);
-+		if (err)
-+			goto out_unlock;
-+	}
-+
-+	/*
-+	 * If this anonymous page is mapped only here, its pte may need
-+	 * to be write-protected.  If it's mapped elsewhere, all of its
-+	 * ptes are necessarily already write-protected.  But in either
-+	 * case, we need to lock and check page_count is not raised.
-+	 */
-+	if (write_protect_page(vma, page, &orig_pte, NULL) == 0) {
-+		if (pages_identical_with_cost(page, kpage))
-+			err = replace_page(vma, page, kpage, orig_pte);
-+		else
-+			err = check_collision(rmap_item, hash);
-+	}
-+
-+	if ((vma->vm_flags & VM_LOCKED) && kpage && !err) {
-+		munlock_vma_page(page);
-+		if (!PageMlocked(kpage)) {
-+			unlock_page(page);
-+			lock_page(kpage);
-+			mlock_vma_page(kpage);
-+			page = kpage;		/* for final unlock */
-+		}
-+	}
-+
-+out_unlock:
-+	unlock_page(page);
-+out:
-+	return err;
-+}
-+
-+
-+
-+/**
-+ * If two pages fail to merge in try_to_merge_two_pages, then we have a chance
-+ * to restore a page mapping that has been changed in try_to_merge_two_pages.
-+ *
-+ * @return 0 on success.
-+ */
-+static int restore_uksm_page_pte(struct vm_area_struct *vma, unsigned long addr,
-+			     pte_t orig_pte, pte_t wprt_pte)
-+{
-+	struct mm_struct *mm = vma->vm_mm;
-+	pgd_t *pgd;
-+	p4d_t *p4d;
-+	pud_t *pud;
-+	pmd_t *pmd;
-+	pte_t *ptep;
-+	spinlock_t *ptl;
-+
-+	int err = -EFAULT;
-+
-+	pgd = pgd_offset(mm, addr);
-+	if (!pgd_present(*pgd))
-+		goto out;
-+
-+	p4d = p4d_offset(pgd, addr);
-+	pud = pud_offset(p4d, addr);
-+	if (!pud_present(*pud))
-+		goto out;
-+
-+	pmd = pmd_offset(pud, addr);
-+	if (!pmd_present(*pmd))
-+		goto out;
-+
-+	ptep = pte_offset_map_lock(mm, pmd, addr, &ptl);
-+	if (!pte_same(*ptep, wprt_pte)) {
-+		/* already copied, let it be */
-+		pte_unmap_unlock(ptep, ptl);
-+		goto out;
-+	}
-+
-+	/*
-+	 * Good boy, still here. When we still get the ksm page, it does not
-+	 * return to the free page pool, there is no way that a pte was changed
-+	 * to other page and gets back to this page. And remind that ksm page
-+	 * do not reuse in do_wp_page(). So it's safe to restore the original
-+	 * pte.
-+	 */
-+	flush_cache_page(vma, addr, pte_pfn(*ptep));
-+	ptep_clear_flush_notify(vma, addr, ptep);
-+	set_pte_at_notify(mm, addr, ptep, orig_pte);
-+
-+	pte_unmap_unlock(ptep, ptl);
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+/**
-+ * try_to_merge_two_pages() - take two identical pages and prepare
-+ * them to be merged into one page(rmap_item->page)
-+ *
-+ * @return 0 if we successfully merged two identical pages into
-+ *         one ksm page. MERGE_ERR_COLLI if it's only a hash collision
-+ *         search in rbtree. MERGE_ERR_CHANGED if rmap_item has been
-+ *         changed since it's hashed. MERGE_ERR_PGERR otherwise.
-+ *
-+ */
-+static int try_to_merge_two_pages(struct rmap_item *rmap_item,
-+				  struct rmap_item *tree_rmap_item,
-+				  u32 hash)
-+{
-+	pte_t orig_pte1 = __pte(0), orig_pte2 = __pte(0);
-+	pte_t wprt_pte1 = __pte(0), wprt_pte2 = __pte(0);
-+	struct vm_area_struct *vma1 = rmap_item->slot->vma;
-+	struct vm_area_struct *vma2 = tree_rmap_item->slot->vma;
-+	struct page *page = rmap_item->page;
-+	struct page *tree_page = tree_rmap_item->page;
-+	int err = MERGE_ERR_PGERR;
-+	struct address_space *saved_mapping;
-+
-+
-+	if (rmap_item->page == tree_rmap_item->page)
-+		goto out;
-+
-+	if (!trylock_page(page))
-+		goto out;
-+
-+	if (!PageAnon(page))
-+		goto out_unlock;
-+
-+	if (PageTransCompound(page)) {
-+		err = split_huge_page(page);
-+		if (err)
-+			goto out_unlock;
-+	}
-+
-+	if (write_protect_page(vma1, page, &wprt_pte1, &orig_pte1) != 0) {
-+		unlock_page(page);
-+		goto out;
-+	}
-+
-+	/*
-+	 * While we hold page lock, upgrade page from
-+	 * PageAnon+anon_vma to PageKsm+NULL stable_node:
-+	 * stable_tree_insert() will update stable_node.
-+	 */
-+	saved_mapping = page->mapping;
-+	set_page_stable_node(page, NULL);
-+	mark_page_accessed(page);
-+	if (!PageDirty(page))
-+		SetPageDirty(page);
-+
-+	unlock_page(page);
-+
-+	if (!trylock_page(tree_page))
-+		goto restore_out;
-+
-+	if (!PageAnon(tree_page)) {
-+		unlock_page(tree_page);
-+		goto restore_out;
-+	}
-+
-+	if (PageTransCompound(tree_page)) {
-+		err = split_huge_page(tree_page);
-+		if (err) {
-+			unlock_page(tree_page);
-+			goto restore_out;
-+		}
-+	}
-+
-+	if (write_protect_page(vma2, tree_page, &wprt_pte2, &orig_pte2) != 0) {
-+		unlock_page(tree_page);
-+		goto restore_out;
-+	}
-+
-+	if (pages_identical_with_cost(page, tree_page)) {
-+		err = replace_page(vma2, tree_page, page, wprt_pte2);
-+		if (err) {
-+			unlock_page(tree_page);
-+			goto restore_out;
-+		}
-+
-+		if ((vma2->vm_flags & VM_LOCKED)) {
-+			munlock_vma_page(tree_page);
-+			if (!PageMlocked(page)) {
-+				unlock_page(tree_page);
-+				lock_page(page);
-+				mlock_vma_page(page);
-+				tree_page = page; /* for final unlock */
-+			}
-+		}
-+
-+		unlock_page(tree_page);
-+
-+		goto out; /* success */
-+
-+	} else {
-+		if (tree_rmap_item->hash_max &&
-+		    tree_rmap_item->hash_max == rmap_item->hash_max) {
-+			err = MERGE_ERR_COLLI_MAX;
-+		} else if (page_hash(page, hash_strength, 0) ==
-+		    page_hash(tree_page, hash_strength, 0)) {
-+			inc_rshash_neg(memcmp_cost + hash_strength * 2);
-+			err = MERGE_ERR_COLLI;
-+		} else {
-+			err = MERGE_ERR_CHANGED;
-+		}
-+
-+		unlock_page(tree_page);
-+	}
-+
-+restore_out:
-+	lock_page(page);
-+	if (!restore_uksm_page_pte(vma1, get_rmap_addr(rmap_item),
-+				  orig_pte1, wprt_pte1))
-+		page->mapping = saved_mapping;
-+
-+out_unlock:
-+	unlock_page(page);
-+out:
-+	return err;
-+}
-+
-+static inline int hash_cmp(u32 new_val, u32 node_val)
-+{
-+	if (new_val > node_val)
-+		return 1;
-+	else if (new_val < node_val)
-+		return -1;
-+	else
-+		return 0;
-+}
-+
-+static inline u32 rmap_item_hash_max(struct rmap_item *item, u32 hash)
-+{
-+	u32 hash_max = item->hash_max;
-+
-+	if (!hash_max) {
-+		hash_max = page_hash_max(item->page, hash);
-+
-+		item->hash_max = hash_max;
-+	}
-+
-+	return hash_max;
-+}
-+
-+
-+
-+/**
-+ * stable_tree_search() - search the stable tree for a page
-+ *
-+ * @item:	the rmap_item we are comparing with
-+ * @hash:	the hash value of this item->page already calculated
-+ *
-+ * @return	the page we have found, NULL otherwise. The page returned has
-+ *			been gotten.
-+ */
-+static struct page *stable_tree_search(struct rmap_item *item, u32 hash)
-+{
-+	struct rb_node *node = root_stable_treep->rb_node;
-+	struct tree_node *tree_node;
-+	unsigned long hash_max;
-+	struct page *page = item->page;
-+	struct stable_node *stable_node;
-+
-+	stable_node = page_stable_node(page);
-+	if (stable_node) {
-+		/* ksm page forked, that is
-+		 * if (PageKsm(page) && !in_stable_tree(rmap_item))
-+		 * it's actually gotten once outside.
-+		 */
-+		get_page(page);
-+		return page;
-+	}
-+
-+	while (node) {
-+		int cmp;
-+
-+		tree_node = rb_entry(node, struct tree_node, node);
-+
-+		cmp = hash_cmp(hash, tree_node->hash);
-+
-+		if (cmp < 0)
-+			node = node->rb_left;
-+		else if (cmp > 0)
-+			node = node->rb_right;
-+		else
-+			break;
-+	}
-+
-+	if (!node)
-+		return NULL;
-+
-+	if (tree_node->count == 1) {
-+		stable_node = rb_entry(tree_node->sub_root.rb_node,
-+				       struct stable_node, node);
-+		BUG_ON(!stable_node);
-+
-+		goto get_page_out;
-+	}
-+
-+	/*
-+	 * ok, we have to search the second
-+	 * level subtree, hash the page to a
-+	 * full strength.
-+	 */
-+	node = tree_node->sub_root.rb_node;
-+	BUG_ON(!node);
-+	hash_max = rmap_item_hash_max(item, hash);
-+
-+	while (node) {
-+		int cmp;
-+
-+		stable_node = rb_entry(node, struct stable_node, node);
-+
-+		cmp = hash_cmp(hash_max, stable_node->hash_max);
-+
-+		if (cmp < 0)
-+			node = node->rb_left;
-+		else if (cmp > 0)
-+			node = node->rb_right;
-+		else
-+			goto get_page_out;
-+	}
-+
-+	return NULL;
-+
-+get_page_out:
-+	page = get_uksm_page(stable_node, 1, 1);
-+	return page;
-+}
-+
-+static int try_merge_rmap_item(struct rmap_item *item,
-+			       struct page *kpage,
-+			       struct page *tree_page)
-+{
-+	struct vm_area_struct *vma = item->slot->vma;
-+	struct page_vma_mapped_walk pvmw = {
-+		.page = kpage,
-+		.vma = vma,
-+	};
-+
-+	pvmw.address = get_rmap_addr(item);
-+	if (!page_vma_mapped_walk(&pvmw))
-+		return 0;
-+
-+	if (pte_write(*pvmw.pte)) {
-+		/* has changed, abort! */
-+		page_vma_mapped_walk_done(&pvmw);
-+		return 0;
-+	}
-+
-+	get_page(tree_page);
-+	page_add_anon_rmap(tree_page, vma, pvmw.address, false);
-+
-+	flush_cache_page(vma, pvmw.address, page_to_pfn(kpage));
-+	ptep_clear_flush_notify(vma, pvmw.address, pvmw.pte);
-+	set_pte_at_notify(vma->vm_mm, pvmw.address, pvmw.pte,
-+			  mk_pte(tree_page, vma->vm_page_prot));
-+
-+	page_remove_rmap(kpage, false);
-+	put_page(kpage);
-+
-+	page_vma_mapped_walk_done(&pvmw);
-+
-+	return 1;
-+}
-+
-+/**
-+ * try_to_merge_with_stable_page() - when two rmap_items need to be inserted
-+ * into stable tree, the page was found to be identical to a stable ksm page,
-+ * this is the last chance we can merge them into one.
-+ *
-+ * @item1:	the rmap_item holding the page which we wanted to insert
-+ *		into stable tree.
-+ * @item2:	the other rmap_item we found when unstable tree search
-+ * @oldpage:	the page currently mapped by the two rmap_items
-+ * @tree_page:	the page we found identical in stable tree node
-+ * @success1:	return if item1 is successfully merged
-+ * @success2:	return if item2 is successfully merged
-+ */
-+static void try_merge_with_stable(struct rmap_item *item1,
-+				  struct rmap_item *item2,
-+				  struct page **kpage,
-+				  struct page *tree_page,
-+				  int *success1, int *success2)
-+{
-+	struct vm_area_struct *vma1 = item1->slot->vma;
-+	struct vm_area_struct *vma2 = item2->slot->vma;
-+	*success1 = 0;
-+	*success2 = 0;
-+
-+	if (unlikely(*kpage == tree_page)) {
-+		/* I don't think this can really happen */
-+		pr_warn("UKSM: unexpected condition detected in "
-+			"%s -- *kpage == tree_page !\n", __func__);
-+		*success1 = 1;
-+		*success2 = 1;
-+		return;
-+	}
-+
-+	if (!PageAnon(*kpage) || !PageKsm(*kpage))
-+		goto failed;
-+
-+	if (!trylock_page(tree_page))
-+		goto failed;
-+
-+	/* If the oldpage is still ksm and still pointed
-+	 * to in the right place, and still write protected,
-+	 * we are confident it's not changed, no need to
-+	 * memcmp anymore.
-+	 * be ware, we cannot take nested pte locks,
-+	 * deadlock risk.
-+	 */
-+	if (!try_merge_rmap_item(item1, *kpage, tree_page))
-+		goto unlock_failed;
-+
-+	/* ok, then vma2, remind that pte1 already set */
-+	if (!try_merge_rmap_item(item2, *kpage, tree_page))
-+		goto success_1;
-+
-+	*success2 = 1;
-+success_1:
-+	*success1 = 1;
-+
-+
-+	if ((*success1 && vma1->vm_flags & VM_LOCKED) ||
-+	    (*success2 && vma2->vm_flags & VM_LOCKED)) {
-+		munlock_vma_page(*kpage);
-+		if (!PageMlocked(tree_page))
-+			mlock_vma_page(tree_page);
-+	}
-+
-+	/*
-+	 * We do not need oldpage any more in the caller, so can break the lock
-+	 * now.
-+	 */
-+	unlock_page(*kpage);
-+	*kpage = tree_page; /* Get unlocked outside. */
-+	return;
-+
-+unlock_failed:
-+	unlock_page(tree_page);
-+failed:
-+	return;
-+}
-+
-+static inline void stable_node_hash_max(struct stable_node *node,
-+					 struct page *page, u32 hash)
-+{
-+	u32 hash_max = node->hash_max;
-+
-+	if (!hash_max) {
-+		hash_max = page_hash_max(page, hash);
-+		node->hash_max = hash_max;
-+	}
-+}
-+
-+static inline
-+struct stable_node *new_stable_node(struct tree_node *tree_node,
-+				    struct page *kpage, u32 hash_max)
-+{
-+	struct stable_node *new_stable_node;
-+
-+	new_stable_node = alloc_stable_node();
-+	if (!new_stable_node)
-+		return NULL;
-+
-+	new_stable_node->kpfn = page_to_pfn(kpage);
-+	new_stable_node->hash_max = hash_max;
-+	new_stable_node->tree_node = tree_node;
-+	set_page_stable_node(kpage, new_stable_node);
-+
-+	return new_stable_node;
-+}
-+
-+static inline
-+struct stable_node *first_level_insert(struct tree_node *tree_node,
-+				       struct rmap_item *rmap_item,
-+				       struct rmap_item *tree_rmap_item,
-+				       struct page **kpage, u32 hash,
-+				       int *success1, int *success2)
-+{
-+	int cmp;
-+	struct page *tree_page;
-+	u32 hash_max = 0;
-+	struct stable_node *stable_node, *new_snode;
-+	struct rb_node *parent = NULL, **new;
-+
-+	/* this tree node contains no sub-tree yet */
-+	stable_node = rb_entry(tree_node->sub_root.rb_node,
-+			       struct stable_node, node);
-+
-+	tree_page = get_uksm_page(stable_node, 1, 0);
-+	if (tree_page) {
-+		cmp = memcmp_pages_with_cost(*kpage, tree_page, 1);
-+		if (!cmp) {
-+			try_merge_with_stable(rmap_item, tree_rmap_item, kpage,
-+					      tree_page, success1, success2);
-+			put_page(tree_page);
-+			if (!*success1 && !*success2)
-+				goto failed;
-+
-+			return stable_node;
-+
-+		} else {
-+			/*
-+			 * collision in first level try to create a subtree.
-+			 * A new node need to be created.
-+			 */
-+			put_page(tree_page);
-+
-+			stable_node_hash_max(stable_node, tree_page,
-+					     tree_node->hash);
-+			hash_max = rmap_item_hash_max(rmap_item, hash);
-+			cmp = hash_cmp(hash_max, stable_node->hash_max);
-+
-+			parent = &stable_node->node;
-+			if (cmp < 0)
-+				new = &parent->rb_left;
-+			else if (cmp > 0)
-+				new = &parent->rb_right;
-+			else
-+				goto failed;
-+		}
-+
-+	} else {
-+		/* the only stable_node deleted, we reuse its tree_node.
-+		 */
-+		parent = NULL;
-+		new = &tree_node->sub_root.rb_node;
-+	}
-+
-+	new_snode = new_stable_node(tree_node, *kpage, hash_max);
-+	if (!new_snode)
-+		goto failed;
-+
-+	rb_link_node(&new_snode->node, parent, new);
-+	rb_insert_color(&new_snode->node, &tree_node->sub_root);
-+	tree_node->count++;
-+	*success1 = *success2 = 1;
-+
-+	return new_snode;
-+
-+failed:
-+	return NULL;
-+}
-+
-+static inline
-+struct stable_node *stable_subtree_insert(struct tree_node *tree_node,
-+					  struct rmap_item *rmap_item,
-+					  struct rmap_item *tree_rmap_item,
-+					  struct page **kpage, u32 hash,
-+					  int *success1, int *success2)
-+{
-+	struct page *tree_page;
-+	u32 hash_max;
-+	struct stable_node *stable_node, *new_snode;
-+	struct rb_node *parent, **new;
-+
-+research:
-+	parent = NULL;
-+	new = &tree_node->sub_root.rb_node;
-+	BUG_ON(!*new);
-+	hash_max = rmap_item_hash_max(rmap_item, hash);
-+	while (*new) {
-+		int cmp;
-+
-+		stable_node = rb_entry(*new, struct stable_node, node);
-+
-+		cmp = hash_cmp(hash_max, stable_node->hash_max);
-+
-+		if (cmp < 0) {
-+			parent = *new;
-+			new = &parent->rb_left;
-+		} else if (cmp > 0) {
-+			parent = *new;
-+			new = &parent->rb_right;
-+		} else {
-+			tree_page = get_uksm_page(stable_node, 1, 0);
-+			if (tree_page) {
-+				cmp = memcmp_pages_with_cost(*kpage, tree_page, 1);
-+				if (!cmp) {
-+					try_merge_with_stable(rmap_item,
-+						tree_rmap_item, kpage,
-+						tree_page, success1, success2);
-+
-+					put_page(tree_page);
-+					if (!*success1 && !*success2)
-+						goto failed;
-+					/*
-+					 * successfully merged with a stable
-+					 * node
-+					 */
-+					return stable_node;
-+				} else {
-+					put_page(tree_page);
-+					goto failed;
-+				}
-+			} else {
-+				/*
-+				 * stable node may be deleted,
-+				 * and subtree maybe
-+				 * restructed, cannot
-+				 * continue, research it.
-+				 */
-+				if (tree_node->count) {
-+					goto research;
-+				} else {
-+					/* reuse the tree node*/
-+					parent = NULL;
-+					new = &tree_node->sub_root.rb_node;
-+				}
-+			}
-+		}
-+	}
-+
-+	new_snode = new_stable_node(tree_node, *kpage, hash_max);
-+	if (!new_snode)
-+		goto failed;
-+
-+	rb_link_node(&new_snode->node, parent, new);
-+	rb_insert_color(&new_snode->node, &tree_node->sub_root);
-+	tree_node->count++;
-+	*success1 = *success2 = 1;
-+
-+	return new_snode;
-+
-+failed:
-+	return NULL;
-+}
-+
-+
-+/**
-+ * stable_tree_insert() - try to insert a merged page in unstable tree to
-+ * the stable tree
-+ *
-+ * @kpage:		the page need to be inserted
-+ * @hash:		the current hash of this page
-+ * @rmap_item:		the rmap_item being scanned
-+ * @tree_rmap_item:	the rmap_item found on unstable tree
-+ * @success1:		return if rmap_item is merged
-+ * @success2:		return if tree_rmap_item is merged
-+ *
-+ * @return		the stable_node on stable tree if at least one
-+ *			rmap_item is inserted into stable tree, NULL
-+ *			otherwise.
-+ */
-+static struct stable_node *
-+stable_tree_insert(struct page **kpage, u32 hash,
-+		   struct rmap_item *rmap_item,
-+		   struct rmap_item *tree_rmap_item,
-+		   int *success1, int *success2)
-+{
-+	struct rb_node **new = &root_stable_treep->rb_node;
-+	struct rb_node *parent = NULL;
-+	struct stable_node *stable_node;
-+	struct tree_node *tree_node;
-+	u32 hash_max = 0;
-+
-+	*success1 = *success2 = 0;
-+
-+	while (*new) {
-+		int cmp;
-+
-+		tree_node = rb_entry(*new, struct tree_node, node);
-+
-+		cmp = hash_cmp(hash, tree_node->hash);
-+
-+		if (cmp < 0) {
-+			parent = *new;
-+			new = &parent->rb_left;
-+		} else if (cmp > 0) {
-+			parent = *new;
-+			new = &parent->rb_right;
-+		} else
-+			break;
-+	}
-+
-+	if (*new) {
-+		if (tree_node->count == 1) {
-+			stable_node = first_level_insert(tree_node, rmap_item,
-+						tree_rmap_item, kpage,
-+						hash, success1, success2);
-+		} else {
-+			stable_node = stable_subtree_insert(tree_node,
-+					rmap_item, tree_rmap_item, kpage,
-+					hash, success1, success2);
-+		}
-+	} else {
-+
-+		/* no tree node found */
-+		tree_node = alloc_tree_node(stable_tree_node_listp);
-+		if (!tree_node) {
-+			stable_node = NULL;
-+			goto out;
-+		}
-+
-+		stable_node = new_stable_node(tree_node, *kpage, hash_max);
-+		if (!stable_node) {
-+			free_tree_node(tree_node);
-+			goto out;
-+		}
-+
-+		tree_node->hash = hash;
-+		rb_link_node(&tree_node->node, parent, new);
-+		rb_insert_color(&tree_node->node, root_stable_treep);
-+		parent = NULL;
-+		new = &tree_node->sub_root.rb_node;
-+
-+		rb_link_node(&stable_node->node, parent, new);
-+		rb_insert_color(&stable_node->node, &tree_node->sub_root);
-+		tree_node->count++;
-+		*success1 = *success2 = 1;
-+	}
-+
-+out:
-+	return stable_node;
-+}
-+
-+
-+/**
-+ * get_tree_rmap_item_page() - try to get the page and lock the mmap_sem
-+ *
-+ * @return	0 on success, -EBUSY if unable to lock the mmap_sem,
-+ *		-EINVAL if the page mapping has been changed.
-+ */
-+static inline int get_tree_rmap_item_page(struct rmap_item *tree_rmap_item)
-+{
-+	int err;
-+
-+	err = get_mergeable_page_lock_mmap(tree_rmap_item);
-+
-+	if (err == -EINVAL) {
-+		/* its page map has been changed, remove it */
-+		remove_rmap_item_from_tree(tree_rmap_item);
-+	}
-+
-+	/* The page is gotten and mmap_sem is locked now. */
-+	return err;
-+}
-+
-+
-+/**
-+ * unstable_tree_search_insert() - search an unstable tree rmap_item with the
-+ * same hash value. Get its page and trylock the mmap_sem
-+ */
-+static inline
-+struct rmap_item *unstable_tree_search_insert(struct rmap_item *rmap_item,
-+					      u32 hash)
-+
-+{
-+	struct rb_node **new = &root_unstable_tree.rb_node;
-+	struct rb_node *parent = NULL;
-+	struct tree_node *tree_node;
-+	u32 hash_max;
-+	struct rmap_item *tree_rmap_item;
-+
-+	while (*new) {
-+		int cmp;
-+
-+		tree_node = rb_entry(*new, struct tree_node, node);
-+
-+		cmp = hash_cmp(hash, tree_node->hash);
-+
-+		if (cmp < 0) {
-+			parent = *new;
-+			new = &parent->rb_left;
-+		} else if (cmp > 0) {
-+			parent = *new;
-+			new = &parent->rb_right;
-+		} else
-+			break;
-+	}
-+
-+	if (*new) {
-+		/* got the tree_node */
-+		if (tree_node->count == 1) {
-+			tree_rmap_item = rb_entry(tree_node->sub_root.rb_node,
-+						  struct rmap_item, node);
-+			BUG_ON(!tree_rmap_item);
-+
-+			goto get_page_out;
-+		}
-+
-+		/* well, search the collision subtree */
-+		new = &tree_node->sub_root.rb_node;
-+		BUG_ON(!*new);
-+		hash_max = rmap_item_hash_max(rmap_item, hash);
-+
-+		while (*new) {
-+			int cmp;
-+
-+			tree_rmap_item = rb_entry(*new, struct rmap_item,
-+						  node);
-+
-+			cmp = hash_cmp(hash_max, tree_rmap_item->hash_max);
-+			parent = *new;
-+			if (cmp < 0)
-+				new = &parent->rb_left;
-+			else if (cmp > 0)
-+				new = &parent->rb_right;
-+			else
-+				goto get_page_out;
-+		}
-+	} else {
-+		/* alloc a new tree_node */
-+		tree_node = alloc_tree_node(&unstable_tree_node_list);
-+		if (!tree_node)
-+			return NULL;
-+
-+		tree_node->hash = hash;
-+		rb_link_node(&tree_node->node, parent, new);
-+		rb_insert_color(&tree_node->node, &root_unstable_tree);
-+		parent = NULL;
-+		new = &tree_node->sub_root.rb_node;
-+	}
-+
-+	/* did not found even in sub-tree */
-+	rmap_item->tree_node = tree_node;
-+	rmap_item->address |= UNSTABLE_FLAG;
-+	rmap_item->hash_round = uksm_hash_round;
-+	rb_link_node(&rmap_item->node, parent, new);
-+	rb_insert_color(&rmap_item->node, &tree_node->sub_root);
-+
-+	uksm_pages_unshared++;
-+	return NULL;
-+
-+get_page_out:
-+	if (tree_rmap_item->page == rmap_item->page)
-+		return NULL;
-+
-+	if (get_tree_rmap_item_page(tree_rmap_item))
-+		return NULL;
-+
-+	return tree_rmap_item;
-+}
-+
-+static void hold_anon_vma(struct rmap_item *rmap_item,
-+			  struct anon_vma *anon_vma)
-+{
-+	rmap_item->anon_vma = anon_vma;
-+	get_anon_vma(anon_vma);
-+}
-+
-+
-+/**
-+ * stable_tree_append() - append a rmap_item to a stable node. Deduplication
-+ * ratio statistics is done in this function.
-+ *
-+ */
-+static void stable_tree_append(struct rmap_item *rmap_item,
-+			       struct stable_node *stable_node, int logdedup)
-+{
-+	struct node_vma *node_vma = NULL, *new_node_vma, *node_vma_cont = NULL;
-+	unsigned long key = (unsigned long)rmap_item->slot;
-+	unsigned long factor = rmap_item->slot->rung->step;
-+
-+	BUG_ON(!stable_node);
-+	rmap_item->address |= STABLE_FLAG;
-+
-+	if (hlist_empty(&stable_node->hlist)) {
-+		uksm_pages_shared++;
-+		goto node_vma_new;
-+	} else {
-+		uksm_pages_sharing++;
-+	}
-+
-+	hlist_for_each_entry(node_vma, &stable_node->hlist, hlist) {
-+		if (node_vma->key >= key)
-+			break;
-+
-+		if (logdedup) {
-+			node_vma->slot->pages_bemerged += factor;
-+			if (list_empty(&node_vma->slot->dedup_list))
-+				list_add(&node_vma->slot->dedup_list,
-+					 &vma_slot_dedup);
-+		}
-+	}
-+
-+	if (node_vma) {
-+		if (node_vma->key == key) {
-+			node_vma_cont = hlist_entry_safe(node_vma->hlist.next, struct node_vma, hlist);
-+			goto node_vma_ok;
-+		} else if (node_vma->key > key) {
-+			node_vma_cont = node_vma;
-+		}
-+	}
-+
-+node_vma_new:
-+	/* no same vma already in node, alloc a new node_vma */
-+	new_node_vma = alloc_node_vma();
-+	BUG_ON(!new_node_vma);
-+	new_node_vma->head = stable_node;
-+	new_node_vma->slot = rmap_item->slot;
-+
-+	if (!node_vma) {
-+		hlist_add_head(&new_node_vma->hlist, &stable_node->hlist);
-+	} else if (node_vma->key != key) {
-+		if (node_vma->key < key)
-+			hlist_add_behind(&new_node_vma->hlist, &node_vma->hlist);
-+		else {
-+			hlist_add_before(&new_node_vma->hlist,
-+					 &node_vma->hlist);
-+		}
-+
-+	}
-+	node_vma = new_node_vma;
-+
-+node_vma_ok: /* ok, ready to add to the list */
-+	rmap_item->head = node_vma;
-+	hlist_add_head(&rmap_item->hlist, &node_vma->rmap_hlist);
-+	hold_anon_vma(rmap_item, rmap_item->slot->vma->anon_vma);
-+	if (logdedup) {
-+		rmap_item->slot->pages_merged++;
-+		if (node_vma_cont) {
-+			node_vma = node_vma_cont;
-+			hlist_for_each_entry_continue(node_vma, hlist) {
-+				node_vma->slot->pages_bemerged += factor;
-+				if (list_empty(&node_vma->slot->dedup_list))
-+					list_add(&node_vma->slot->dedup_list,
-+						 &vma_slot_dedup);
-+			}
-+		}
-+	}
-+}
-+
-+/*
-+ * We use break_ksm to break COW on a ksm page: it's a stripped down
-+ *
-+ *	if (get_user_pages(addr, 1, 1, 1, &page, NULL) == 1)
-+ *		put_page(page);
-+ *
-+ * but taking great care only to touch a ksm page, in a VM_MERGEABLE vma,
-+ * in case the application has unmapped and remapped mm,addr meanwhile.
-+ * Could a ksm page appear anywhere else?  Actually yes, in a VM_PFNMAP
-+ * mmap of /dev/mem or /dev/kmem, where we would not want to touch it.
-+ */
-+static int break_ksm(struct vm_area_struct *vma, unsigned long addr)
-+{
-+	struct page *page;
-+	int ret = 0;
-+
-+	do {
-+		cond_resched();
-+		page = follow_page(vma, addr, FOLL_GET | FOLL_MIGRATION | FOLL_REMOTE);
-+		if (IS_ERR_OR_NULL(page))
-+			break;
-+		if (PageKsm(page)) {
-+			ret = handle_mm_fault(vma, addr,
-+					      FAULT_FLAG_WRITE | FAULT_FLAG_REMOTE,
-+                                             NULL);
-+		} else
-+			ret = VM_FAULT_WRITE;
-+		put_page(page);
-+	} while (!(ret & (VM_FAULT_WRITE | VM_FAULT_SIGBUS | VM_FAULT_SIGSEGV | VM_FAULT_OOM)));
-+	/*
-+	 * We must loop because handle_mm_fault() may back out if there's
-+	 * any difficulty e.g. if pte accessed bit gets updated concurrently.
-+	 *
-+	 * VM_FAULT_WRITE is what we have been hoping for: it indicates that
-+	 * COW has been broken, even if the vma does not permit VM_WRITE;
-+	 * but note that a concurrent fault might break PageKsm for us.
-+	 *
-+	 * VM_FAULT_SIGBUS could occur if we race with truncation of the
-+	 * backing file, which also invalidates anonymous pages: that's
-+	 * okay, that truncation will have unmapped the PageKsm for us.
-+	 *
-+	 * VM_FAULT_OOM: at the time of writing (late July 2009), setting
-+	 * aside mem_cgroup limits, VM_FAULT_OOM would only be set if the
-+	 * current task has TIF_MEMDIE set, and will be OOM killed on return
-+	 * to user; and ksmd, having no mm, would never be chosen for that.
-+	 *
-+	 * But if the mm is in a limited mem_cgroup, then the fault may fail
-+	 * with VM_FAULT_OOM even if the current task is not TIF_MEMDIE; and
-+	 * even ksmd can fail in this way - though it's usually breaking ksm
-+	 * just to undo a merge it made a moment before, so unlikely to oom.
-+	 *
-+	 * That's a pity: we might therefore have more kernel pages allocated
-+	 * than we're counting as nodes in the stable tree; but uksm_do_scan
-+	 * will retry to break_cow on each pass, so should recover the page
-+	 * in due course.  The important thing is to not let VM_MERGEABLE
-+	 * be cleared while any such pages might remain in the area.
-+	 */
-+	return (ret & VM_FAULT_OOM) ? -ENOMEM : 0;
-+}
-+
-+static void break_cow(struct rmap_item *rmap_item)
-+{
-+	struct vm_area_struct *vma = rmap_item->slot->vma;
-+	struct mm_struct *mm = vma->vm_mm;
-+	unsigned long addr = get_rmap_addr(rmap_item);
-+
-+	if (uksm_test_exit(mm))
-+		goto out;
-+
-+	break_ksm(vma, addr);
-+out:
-+	return;
-+}
-+
-+/*
-+ * Though it's very tempting to unmerge in_stable_tree(rmap_item)s rather
-+ * than check every pte of a given vma, the locking doesn't quite work for
-+ * that - an rmap_item is assigned to the stable tree after inserting ksm
-+ * page and upping mmap_sem.  Nor does it fit with the way we skip dup'ing
-+ * rmap_items from parent to child at fork time (so as not to waste time
-+ * if exit comes before the next scan reaches it).
-+ *
-+ * Similarly, although we'd like to remove rmap_items (so updating counts
-+ * and freeing memory) when unmerging an area, it's easier to leave that
-+ * to the next pass of ksmd - consider, for example, how ksmd might be
-+ * in cmp_and_merge_page on one of the rmap_items we would be removing.
-+ */
-+inline int unmerge_uksm_pages(struct vm_area_struct *vma,
-+		      unsigned long start, unsigned long end)
-+{
-+	unsigned long addr;
-+	int err = 0;
-+
-+	for (addr = start; addr < end && !err; addr += PAGE_SIZE) {
-+		if (uksm_test_exit(vma->vm_mm))
-+			break;
-+		if (signal_pending(current))
-+			err = -ERESTARTSYS;
-+		else
-+			err = break_ksm(vma, addr);
-+	}
-+	return err;
-+}
-+
-+static inline struct stable_node *folio_stable_node(struct folio *folio)
-+{
-+	return folio_test_ksm(folio) ? folio_raw_mapping(folio) : NULL;
-+}
-+
-+static inline void inc_uksm_pages_scanned(void)
-+{
-+	u64 delta;
-+
-+
-+	if (uksm_pages_scanned == U64_MAX) {
-+		encode_benefit();
-+
-+		delta = uksm_pages_scanned >> pages_scanned_base;
-+
-+		if (CAN_OVERFLOW_U64(pages_scanned_stored, delta)) {
-+			pages_scanned_stored >>= 1;
-+			delta >>= 1;
-+			pages_scanned_base++;
-+		}
-+
-+		pages_scanned_stored += delta;
-+
-+		uksm_pages_scanned = uksm_pages_scanned_last = 0;
-+	}
-+
-+	uksm_pages_scanned++;
-+}
-+
-+static inline int find_zero_page_hash(int strength, u32 hash)
-+{
-+	return (zero_hash_table[strength] == hash);
-+}
-+
-+static
-+int cmp_and_merge_zero_page(struct vm_area_struct *vma, struct page *page)
-+{
-+	struct page *zero_page = empty_uksm_zero_page;
-+	struct mm_struct *mm = vma->vm_mm;
-+	pte_t orig_pte = __pte(0);
-+	int err = -EFAULT;
-+
-+	if (uksm_test_exit(mm))
-+		goto out;
-+
-+	if (!trylock_page(page))
-+		goto out;
-+
-+	if (!PageAnon(page))
-+		goto out_unlock;
-+
-+	if (PageTransCompound(page)) {
-+		err = split_huge_page(page);
-+		if (err)
-+			goto out_unlock;
-+	}
-+
-+	if (write_protect_page(vma, page, &orig_pte, 0) == 0) {
-+		if (is_page_full_zero(page))
-+			err = replace_page(vma, page, zero_page, orig_pte);
-+	}
-+
-+out_unlock:
-+	unlock_page(page);
-+out:
-+	return err;
-+}
-+
-+/*
-+ * cmp_and_merge_page() - first see if page can be merged into the stable
-+ * tree; if not, compare hash to previous and if it's the same, see if page
-+ * can be inserted into the unstable tree, or merged with a page already there
-+ * and both transferred to the stable tree.
-+ *
-+ * @page: the page that we are searching identical page to.
-+ * @rmap_item: the reverse mapping into the virtual address of this page
-+ */
-+static void cmp_and_merge_page(struct rmap_item *rmap_item, u32 hash)
-+{
-+	struct rmap_item *tree_rmap_item;
-+	struct page *page;
-+	struct page *kpage = NULL;
-+	u32 hash_max;
-+	int err;
-+	unsigned int success1, success2;
-+	struct stable_node *snode;
-+	int cmp;
-+	struct rb_node *parent = NULL, **new;
-+
-+	remove_rmap_item_from_tree(rmap_item);
-+	page = rmap_item->page;
-+
-+	/* We first start with searching the page inside the stable tree */
-+	kpage = stable_tree_search(rmap_item, hash);
-+	if (kpage) {
-+		err = try_to_merge_with_uksm_page(rmap_item, kpage,
-+						 hash);
-+		if (!err) {
-+			/*
-+			 * The page was successfully merged, add
-+			 * its rmap_item to the stable tree.
-+			 * page lock is needed because it's
-+			 * racing with try_to_unmap_ksm(), etc.
-+			 */
-+			lock_page(kpage);
-+			snode = page_stable_node(kpage);
-+			stable_tree_append(rmap_item, snode, 1);
-+			unlock_page(kpage);
-+			put_page(kpage);
-+			return; /* success */
-+		}
-+		put_page(kpage);
-+
-+		/*
-+		 * if it's a collision and it has been search in sub-rbtree
-+		 * (hash_max != 0), we want to abort, because if it is
-+		 * successfully merged in unstable tree, the collision trends to
-+		 * happen again.
-+		 */
-+		if (err == MERGE_ERR_COLLI && rmap_item->hash_max)
-+			return;
-+	}
-+
-+	tree_rmap_item =
-+		unstable_tree_search_insert(rmap_item, hash);
-+	if (tree_rmap_item) {
-+		err = try_to_merge_two_pages(rmap_item, tree_rmap_item, hash);
-+		/*
-+		 * As soon as we merge this page, we want to remove the
-+		 * rmap_item of the page we have merged with from the unstable
-+		 * tree, and insert it instead as new node in the stable tree.
-+		 */
-+		if (!err) {
-+			kpage = page;
-+			remove_rmap_item_from_tree(tree_rmap_item);
-+			lock_page(kpage);
-+			snode = stable_tree_insert(&kpage, hash,
-+						   rmap_item, tree_rmap_item,
-+						   &success1, &success2);
-+
-+			/*
-+			 * Do not log dedup for tree item, it's not counted as
-+			 * scanned in this round.
-+			 */
-+			if (success2)
-+				stable_tree_append(tree_rmap_item, snode, 0);
-+
-+			/*
-+			 * The order of these two stable append is important:
-+			 * we are scanning rmap_item.
-+			 */
-+			if (success1)
-+				stable_tree_append(rmap_item, snode, 1);
-+
-+			/*
-+			 * The original kpage may be unlocked inside
-+			 * stable_tree_insert() already. This page
-+			 * should be unlocked before doing
-+			 * break_cow().
-+			 */
-+			unlock_page(kpage);
-+
-+			if (!success1)
-+				break_cow(rmap_item);
-+
-+			if (!success2)
-+				break_cow(tree_rmap_item);
-+
-+		} else if (err == MERGE_ERR_COLLI) {
-+			BUG_ON(tree_rmap_item->tree_node->count > 1);
-+
-+			rmap_item_hash_max(tree_rmap_item,
-+					   tree_rmap_item->tree_node->hash);
-+
-+			hash_max = rmap_item_hash_max(rmap_item, hash);
-+			cmp = hash_cmp(hash_max, tree_rmap_item->hash_max);
-+			parent = &tree_rmap_item->node;
-+			if (cmp < 0)
-+				new = &parent->rb_left;
-+			else if (cmp > 0)
-+				new = &parent->rb_right;
-+			else
-+				goto put_up_out;
-+
-+			rmap_item->tree_node = tree_rmap_item->tree_node;
-+			rmap_item->address |= UNSTABLE_FLAG;
-+			rmap_item->hash_round = uksm_hash_round;
-+			rb_link_node(&rmap_item->node, parent, new);
-+			rb_insert_color(&rmap_item->node,
-+					&tree_rmap_item->tree_node->sub_root);
-+			rmap_item->tree_node->count++;
-+		} else {
-+			/*
-+			 * either one of the page has changed or they collide
-+			 * at the max hash, we consider them as ill items.
-+			 */
-+			remove_rmap_item_from_tree(tree_rmap_item);
-+		}
-+put_up_out:
-+		put_page(tree_rmap_item->page);
-+		mmap_read_unlock(tree_rmap_item->slot->vma->vm_mm);
-+	}
-+}
-+
-+
-+
-+
-+static inline unsigned long get_pool_index(struct vma_slot *slot,
-+					   unsigned long index)
-+{
-+	unsigned long pool_index;
-+
-+	pool_index = (sizeof(struct rmap_list_entry *) * index) >> PAGE_SHIFT;
-+	if (pool_index >= slot->pool_size)
-+		BUG();
-+	return pool_index;
-+}
-+
-+static inline unsigned long index_page_offset(unsigned long index)
-+{
-+	return offset_in_page(sizeof(struct rmap_list_entry *) * index);
-+}
-+
-+static inline
-+struct rmap_list_entry *get_rmap_list_entry(struct vma_slot *slot,
-+					    unsigned long index, int need_alloc)
-+{
-+	unsigned long pool_index;
-+	struct page *page;
-+	void *addr;
-+
-+
-+	pool_index = get_pool_index(slot, index);
-+	if (!slot->rmap_list_pool[pool_index]) {
-+		if (!need_alloc)
-+			return NULL;
-+
-+		page = alloc_page(GFP_KERNEL | __GFP_ZERO | __GFP_NOWARN);
-+		if (!page)
-+			return NULL;
-+
-+		slot->rmap_list_pool[pool_index] = page;
-+	}
-+
-+	addr = kmap(slot->rmap_list_pool[pool_index]);
-+	addr += index_page_offset(index);
-+
-+	return addr;
-+}
-+
-+static inline void put_rmap_list_entry(struct vma_slot *slot,
-+				       unsigned long index)
-+{
-+	unsigned long pool_index;
-+
-+	pool_index = get_pool_index(slot, index);
-+	BUG_ON(!slot->rmap_list_pool[pool_index]);
-+	kunmap(slot->rmap_list_pool[pool_index]);
-+}
-+
-+static inline int entry_is_new(struct rmap_list_entry *entry)
-+{
-+	return !entry->item;
-+}
-+
-+static inline unsigned long get_index_orig_addr(struct vma_slot *slot,
-+						unsigned long index)
-+{
-+	return slot->vma->vm_start + (index << PAGE_SHIFT);
-+}
-+
-+static inline unsigned long get_entry_address(struct rmap_list_entry *entry)
-+{
-+	unsigned long addr;
-+
-+	if (is_addr(entry->addr))
-+		addr = get_clean_addr(entry->addr);
-+	else if (entry->item)
-+		addr = get_rmap_addr(entry->item);
-+	else
-+		BUG();
-+
-+	return addr;
-+}
-+
-+static inline struct rmap_item *get_entry_item(struct rmap_list_entry *entry)
-+{
-+	if (is_addr(entry->addr))
-+		return NULL;
-+
-+	return entry->item;
-+}
-+
-+static inline void inc_rmap_list_pool_count(struct vma_slot *slot,
-+					    unsigned long index)
-+{
-+	unsigned long pool_index;
-+
-+	pool_index = get_pool_index(slot, index);
-+	BUG_ON(!slot->rmap_list_pool[pool_index]);
-+	slot->pool_counts[pool_index]++;
-+}
-+
-+static inline void dec_rmap_list_pool_count(struct vma_slot *slot,
-+					    unsigned long index)
-+{
-+	unsigned long pool_index;
-+
-+	pool_index = get_pool_index(slot, index);
-+	BUG_ON(!slot->rmap_list_pool[pool_index]);
-+	BUG_ON(!slot->pool_counts[pool_index]);
-+	slot->pool_counts[pool_index]--;
-+}
-+
-+static inline int entry_has_rmap(struct rmap_list_entry *entry)
-+{
-+	return !is_addr(entry->addr) && entry->item;
-+}
-+
-+static inline void swap_entries(struct rmap_list_entry *entry1,
-+				unsigned long index1,
-+				struct rmap_list_entry *entry2,
-+				unsigned long index2)
-+{
-+	struct rmap_list_entry tmp;
-+
-+	/* swapping two new entries is meaningless */
-+	BUG_ON(entry_is_new(entry1) && entry_is_new(entry2));
-+
-+	tmp = *entry1;
-+	*entry1 = *entry2;
-+	*entry2 = tmp;
-+
-+	if (entry_has_rmap(entry1))
-+		entry1->item->entry_index = index1;
-+
-+	if (entry_has_rmap(entry2))
-+		entry2->item->entry_index = index2;
-+
-+	if (entry_has_rmap(entry1) && !entry_has_rmap(entry2)) {
-+		inc_rmap_list_pool_count(entry1->item->slot, index1);
-+		dec_rmap_list_pool_count(entry1->item->slot, index2);
-+	} else if (!entry_has_rmap(entry1) && entry_has_rmap(entry2)) {
-+		inc_rmap_list_pool_count(entry2->item->slot, index2);
-+		dec_rmap_list_pool_count(entry2->item->slot, index1);
-+	}
-+}
-+
-+static inline void free_entry_item(struct rmap_list_entry *entry)
-+{
-+	unsigned long index;
-+	struct rmap_item *item;
-+
-+	if (!is_addr(entry->addr)) {
-+		BUG_ON(!entry->item);
-+		item = entry->item;
-+		entry->addr = get_rmap_addr(item);
-+		set_is_addr(entry->addr);
-+		index = item->entry_index;
-+		remove_rmap_item_from_tree(item);
-+		dec_rmap_list_pool_count(item->slot, index);
-+		free_rmap_item(item);
-+	}
-+}
-+
-+static inline int pool_entry_boundary(unsigned long index)
-+{
-+	unsigned long linear_addr;
-+
-+	linear_addr = sizeof(struct rmap_list_entry *) * index;
-+	return index && !offset_in_page(linear_addr);
-+}
-+
-+static inline void try_free_last_pool(struct vma_slot *slot,
-+				      unsigned long index)
-+{
-+	unsigned long pool_index;
-+
-+	pool_index = get_pool_index(slot, index);
-+	if (slot->rmap_list_pool[pool_index] &&
-+	    !slot->pool_counts[pool_index]) {
-+		__free_page(slot->rmap_list_pool[pool_index]);
-+		slot->rmap_list_pool[pool_index] = NULL;
-+		slot->flags |= UKSM_SLOT_NEED_SORT;
-+	}
-+
-+}
-+
-+static inline unsigned long vma_item_index(struct vm_area_struct *vma,
-+					   struct rmap_item *item)
-+{
-+	return (get_rmap_addr(item) - vma->vm_start) >> PAGE_SHIFT;
-+}
-+
-+static int within_same_pool(struct vma_slot *slot,
-+			    unsigned long i, unsigned long j)
-+{
-+	unsigned long pool_i, pool_j;
-+
-+	pool_i = get_pool_index(slot, i);
-+	pool_j = get_pool_index(slot, j);
-+
-+	return (pool_i == pool_j);
-+}
-+
-+static void sort_rmap_entry_list(struct vma_slot *slot)
-+{
-+	unsigned long i, j;
-+	struct rmap_list_entry *entry, *swap_entry;
-+
-+	entry = get_rmap_list_entry(slot, 0, 0);
-+	for (i = 0; i < slot->pages; ) {
-+
-+		if (!entry)
-+			goto skip_whole_pool;
-+
-+		if (entry_is_new(entry))
-+			goto next_entry;
-+
-+		if (is_addr(entry->addr)) {
-+			entry->addr = 0;
-+			goto next_entry;
-+		}
-+
-+		j = vma_item_index(slot->vma, entry->item);
-+		if (j == i)
-+			goto next_entry;
-+
-+		if (within_same_pool(slot, i, j))
-+			swap_entry = entry + j - i;
-+		else
-+			swap_entry = get_rmap_list_entry(slot, j, 1);
-+
-+		swap_entries(entry, i, swap_entry, j);
-+		if (!within_same_pool(slot, i, j))
-+			put_rmap_list_entry(slot, j);
-+		continue;
-+
-+skip_whole_pool:
-+		i += PAGE_SIZE / sizeof(*entry);
-+		if (i < slot->pages)
-+			entry = get_rmap_list_entry(slot, i, 0);
-+		continue;
-+
-+next_entry:
-+		if (i >= slot->pages - 1 ||
-+		    !within_same_pool(slot, i, i + 1)) {
-+			put_rmap_list_entry(slot, i);
-+			if (i + 1 < slot->pages)
-+				entry = get_rmap_list_entry(slot, i + 1, 0);
-+		} else
-+			entry++;
-+		i++;
-+		continue;
-+	}
-+
-+	/* free empty pool entries which contain no rmap_item */
-+	/* CAN be simplied to based on only pool_counts when bug freed !!!!! */
-+	for (i = 0; i < slot->pool_size; i++) {
-+		unsigned char has_rmap;
-+		void *addr;
-+
-+		if (!slot->rmap_list_pool[i])
-+			continue;
-+
-+		has_rmap = 0;
-+		addr = kmap(slot->rmap_list_pool[i]);
-+		BUG_ON(!addr);
-+		for (j = 0; j < PAGE_SIZE / sizeof(*entry); j++) {
-+			entry = (struct rmap_list_entry *)addr + j;
-+			if (is_addr(entry->addr))
-+				continue;
-+			if (!entry->item)
-+				continue;
-+			has_rmap = 1;
-+		}
-+		kunmap(slot->rmap_list_pool[i]);
-+		if (!has_rmap) {
-+			BUG_ON(slot->pool_counts[i]);
-+			__free_page(slot->rmap_list_pool[i]);
-+			slot->rmap_list_pool[i] = NULL;
-+		}
-+	}
-+
-+	slot->flags &= ~UKSM_SLOT_NEED_SORT;
-+}
-+
-+/*
-+ * vma_fully_scanned() - if all the pages in this slot have been scanned.
-+ */
-+static inline int vma_fully_scanned(struct vma_slot *slot)
-+{
-+	return slot->pages_scanned == slot->pages;
-+}
-+
-+/**
-+ * get_next_rmap_item() - Get the next rmap_item in a vma_slot according to
-+ * its random permutation. This function is embedded with the random
-+ * permutation index management code.
-+ */
-+static struct rmap_item *get_next_rmap_item(struct vma_slot *slot, u32 *hash)
-+{
-+	unsigned long rand_range, addr, swap_index, scan_index;
-+	struct rmap_item *item = NULL;
-+	struct rmap_list_entry *scan_entry, *swap_entry = NULL;
-+	struct page *page;
-+
-+	scan_index = swap_index = slot->pages_scanned % slot->pages;
-+
-+	if (pool_entry_boundary(scan_index))
-+		try_free_last_pool(slot, scan_index - 1);
-+
-+	if (vma_fully_scanned(slot)) {
-+		if (slot->flags & UKSM_SLOT_NEED_SORT)
-+			slot->flags |= UKSM_SLOT_NEED_RERAND;
-+		else
-+			slot->flags &= ~UKSM_SLOT_NEED_RERAND;
-+		if (slot->flags & UKSM_SLOT_NEED_SORT)
-+			sort_rmap_entry_list(slot);
-+	}
-+
-+	scan_entry = get_rmap_list_entry(slot, scan_index, 1);
-+	if (!scan_entry)
-+		return NULL;
-+
-+	if (entry_is_new(scan_entry)) {
-+		scan_entry->addr = get_index_orig_addr(slot, scan_index);
-+		set_is_addr(scan_entry->addr);
-+	}
-+
-+	if (slot->flags & UKSM_SLOT_NEED_RERAND) {
-+		rand_range = slot->pages - scan_index;
-+		BUG_ON(!rand_range);
-+		swap_index = scan_index + (prandom_u32() % rand_range);
-+	}
-+
-+	if (swap_index != scan_index) {
-+		swap_entry = get_rmap_list_entry(slot, swap_index, 1);
-+
-+		if (!swap_entry)
-+			return NULL;
-+
-+		if (entry_is_new(swap_entry)) {
-+			swap_entry->addr = get_index_orig_addr(slot,
-+							       swap_index);
-+			set_is_addr(swap_entry->addr);
-+		}
-+		swap_entries(scan_entry, scan_index, swap_entry, swap_index);
-+	}
-+
-+	addr = get_entry_address(scan_entry);
-+	item = get_entry_item(scan_entry);
-+	BUG_ON(addr > slot->vma->vm_end || addr < slot->vma->vm_start);
-+
-+	page = follow_page(slot->vma, addr, FOLL_GET);
-+	if (IS_ERR_OR_NULL(page))
-+		goto nopage;
-+
-+	if (!PageAnon(page))
-+		goto putpage;
-+
-+	/*check is zero_page pfn or uksm_zero_page*/
-+	if ((page_to_pfn(page) == zero_pfn)
-+			|| (page_to_pfn(page) == uksm_zero_pfn))
-+		goto putpage;
-+
-+	flush_anon_page(slot->vma, page, addr);
-+	flush_dcache_page(page);
-+
-+
-+	*hash = page_hash(page, hash_strength, 1);
-+	inc_uksm_pages_scanned();
-+	/*if the page content all zero, re-map to zero-page*/
-+	if (find_zero_page_hash(hash_strength, *hash)) {
-+		if (!cmp_and_merge_zero_page(slot->vma, page)) {
-+			slot->pages_merged++;
-+
-+			/* For full-zero pages, no need to create rmap item */
-+			goto putpage;
-+		} else {
-+			inc_rshash_neg(memcmp_cost / 2);
-+		}
-+	}
-+
-+	if (!item) {
-+		item = alloc_rmap_item();
-+		if (item) {
-+			/* It has already been zeroed */
-+			item->slot = slot;
-+			item->address = addr;
-+			item->entry_index = scan_index;
-+			scan_entry->item = item;
-+			inc_rmap_list_pool_count(slot, scan_index);
-+		} else
-+			goto putpage;
-+	}
-+
-+	BUG_ON(item->slot != slot);
-+	/* the page may have changed */
-+	item->page = page;
-+	put_rmap_list_entry(slot, scan_index);
-+	if (swap_entry)
-+		put_rmap_list_entry(slot, swap_index);
-+	return item;
-+
-+putpage:
-+	put_page(page);
-+	page = NULL;
-+nopage:
-+	/* no page, store addr back and free rmap_item if possible */
-+	free_entry_item(scan_entry);
-+	put_rmap_list_entry(slot, scan_index);
-+	if (swap_entry)
-+		put_rmap_list_entry(slot, swap_index);
-+	return NULL;
-+}
-+
-+static inline int in_stable_tree(struct rmap_item *rmap_item)
-+{
-+	return rmap_item->address & STABLE_FLAG;
-+}
-+
-+/**
-+ * scan_vma_one_page() - scan the next page in a vma_slot. Called with
-+ * mmap_sem locked.
-+ */
-+static noinline void scan_vma_one_page(struct vma_slot *slot)
-+{
-+	u32 hash;
-+	struct mm_struct *mm;
-+	struct rmap_item *rmap_item = NULL;
-+	struct vm_area_struct *vma = slot->vma;
-+
-+	mm = vma->vm_mm;
-+	BUG_ON(!mm);
-+	BUG_ON(!slot);
-+
-+	rmap_item = get_next_rmap_item(slot, &hash);
-+	if (!rmap_item)
-+		goto out1;
-+
-+	if (PageKsm(rmap_item->page) && in_stable_tree(rmap_item))
-+		goto out2;
-+
-+	cmp_and_merge_page(rmap_item, hash);
-+out2:
-+	put_page(rmap_item->page);
-+out1:
-+	slot->pages_scanned++;
-+	slot->this_sampled++;
-+	if (slot->fully_scanned_round != fully_scanned_round)
-+		scanned_virtual_pages++;
-+
-+	if (vma_fully_scanned(slot))
-+		slot->fully_scanned_round = fully_scanned_round;
-+}
-+
-+static inline unsigned long rung_get_pages(struct scan_rung *rung)
-+{
-+	struct slot_tree_node *node;
-+
-+	if (!rung->vma_root.rnode)
-+		return 0;
-+
-+	node = container_of(rung->vma_root.rnode, struct slot_tree_node, snode);
-+
-+	return node->size;
-+}
-+
-+#define RUNG_SAMPLED_MIN	3
-+
-+static inline
-+void uksm_calc_rung_step(struct scan_rung *rung,
-+			 unsigned long page_time, unsigned long ratio)
-+{
-+	unsigned long sampled, pages;
-+
-+	/* will be fully scanned ? */
-+	if (!rung->cover_msecs) {
-+		rung->step = 1;
-+		return;
-+	}
-+
-+	sampled = rung->cover_msecs * (NSEC_PER_MSEC / TIME_RATIO_SCALE)
-+		  * ratio / page_time;
-+
-+	/*
-+	 *  Before we finsish a scan round and expensive per-round jobs,
-+	 *  we need to have a chance to estimate the per page time. So
-+	 *  the sampled number can not be too small.
-+	 */
-+	if (sampled < RUNG_SAMPLED_MIN)
-+		sampled = RUNG_SAMPLED_MIN;
-+
-+	pages = rung_get_pages(rung);
-+	if (likely(pages > sampled))
-+		rung->step = pages / sampled;
-+	else
-+		rung->step = 1;
-+}
-+
-+static inline int step_need_recalc(struct scan_rung *rung)
-+{
-+	unsigned long pages, stepmax;
-+
-+	pages = rung_get_pages(rung);
-+	stepmax = pages / RUNG_SAMPLED_MIN;
-+
-+	return pages && (rung->step > pages ||
-+			 (stepmax && rung->step > stepmax));
-+}
-+
-+static inline
-+void reset_current_scan(struct scan_rung *rung, int finished, int step_recalc)
-+{
-+	struct vma_slot *slot;
-+
-+	if (finished)
-+		rung->flags |= UKSM_RUNG_ROUND_FINISHED;
-+
-+	if (step_recalc || step_need_recalc(rung)) {
-+		uksm_calc_rung_step(rung, uksm_ema_page_time, rung->cpu_ratio);
-+		BUG_ON(step_need_recalc(rung));
-+	}
-+
-+	slot_iter_index = prandom_u32() % rung->step;
-+	BUG_ON(!rung->vma_root.rnode);
-+	slot = sradix_tree_next(&rung->vma_root, NULL, 0, slot_iter);
-+	BUG_ON(!slot);
-+
-+	rung->current_scan = slot;
-+	rung->current_offset = slot_iter_index;
-+}
-+
-+static inline struct sradix_tree_root *slot_get_root(struct vma_slot *slot)
-+{
-+	return &slot->rung->vma_root;
-+}
-+
-+/*
-+ * return if resetted.
-+ */
-+static int advance_current_scan(struct scan_rung *rung)
-+{
-+	unsigned short n;
-+	struct vma_slot *slot, *next = NULL;
-+
-+	BUG_ON(!rung->vma_root.num);
-+
-+	slot = rung->current_scan;
-+	n = (slot->pages - rung->current_offset) % rung->step;
-+	slot_iter_index = rung->step - n;
-+	next = sradix_tree_next(&rung->vma_root, slot->snode,
-+				slot->sindex, slot_iter);
-+
-+	if (next) {
-+		rung->current_offset = slot_iter_index;
-+		rung->current_scan = next;
-+		return 0;
-+	} else {
-+		reset_current_scan(rung, 1, 0);
-+		return 1;
-+	}
-+}
-+
-+static inline void rung_rm_slot(struct vma_slot *slot)
-+{
-+	struct scan_rung *rung = slot->rung;
-+	struct sradix_tree_root *root;
-+
-+	if (rung->current_scan == slot)
-+		advance_current_scan(rung);
-+
-+	root = slot_get_root(slot);
-+	sradix_tree_delete_from_leaf(root, slot->snode, slot->sindex);
-+	slot->snode = NULL;
-+	if (step_need_recalc(rung)) {
-+		uksm_calc_rung_step(rung, uksm_ema_page_time, rung->cpu_ratio);
-+		BUG_ON(step_need_recalc(rung));
-+	}
-+
-+	/* In case advance_current_scan loop back to this slot again */
-+	if (rung->vma_root.num && rung->current_scan == slot)
-+		reset_current_scan(slot->rung, 1, 0);
-+}
-+
-+static inline void rung_add_new_slots(struct scan_rung *rung,
-+			struct vma_slot **slots, unsigned long num)
-+{
-+	int err;
-+	struct vma_slot *slot;
-+	unsigned long i;
-+	struct sradix_tree_root *root = &rung->vma_root;
-+
-+	err = sradix_tree_enter(root, (void **)slots, num);
-+	BUG_ON(err);
-+
-+	for (i = 0; i < num; i++) {
-+		slot = slots[i];
-+		slot->rung = rung;
-+		BUG_ON(vma_fully_scanned(slot));
-+	}
-+
-+	if (rung->vma_root.num == num)
-+		reset_current_scan(rung, 0, 1);
-+}
-+
-+static inline int rung_add_one_slot(struct scan_rung *rung,
-+				     struct vma_slot *slot)
-+{
-+	int err;
-+
-+	err = sradix_tree_enter(&rung->vma_root, (void **)&slot, 1);
-+	if (err)
-+		return err;
-+
-+	slot->rung = rung;
-+	if (rung->vma_root.num == 1)
-+		reset_current_scan(rung, 0, 1);
-+
-+	return 0;
-+}
-+
-+/*
-+ * Return true if the slot is deleted from its rung.
-+ */
-+static inline int vma_rung_enter(struct vma_slot *slot, struct scan_rung *rung)
-+{
-+	struct scan_rung *old_rung = slot->rung;
-+	int err;
-+
-+	if (old_rung == rung)
-+		return 0;
-+
-+	rung_rm_slot(slot);
-+	err = rung_add_one_slot(rung, slot);
-+	if (err) {
-+		err = rung_add_one_slot(old_rung, slot);
-+		WARN_ON(err); /* OOPS, badly OOM, we lost this slot */
-+	}
-+
-+	return 1;
-+}
-+
-+static inline int vma_rung_up(struct vma_slot *slot)
-+{
-+	struct scan_rung *rung;
-+
-+	rung = slot->rung;
-+	if (slot->rung != &uksm_scan_ladder[SCAN_LADDER_SIZE-1])
-+		rung++;
-+
-+	return vma_rung_enter(slot, rung);
-+}
-+
-+static inline int vma_rung_down(struct vma_slot *slot)
-+{
-+	struct scan_rung *rung;
-+
-+	rung = slot->rung;
-+	if (slot->rung != &uksm_scan_ladder[0])
-+		rung--;
-+
-+	return vma_rung_enter(slot, rung);
-+}
-+
-+/**
-+ * cal_dedup_ratio() - Calculate the deduplication ratio for this slot.
-+ */
-+static unsigned long cal_dedup_ratio(struct vma_slot *slot)
-+{
-+	unsigned long ret;
-+	unsigned long pages;
-+
-+	pages = slot->this_sampled;
-+	if (!pages)
-+		return 0;
-+
-+	BUG_ON(slot->pages_scanned == slot->last_scanned);
-+
-+	ret = slot->pages_merged;
-+
-+	/* Thrashing area filtering */
-+	if (ret && uksm_thrash_threshold) {
-+		if (slot->pages_cowed * 100 / slot->pages_merged
-+		    > uksm_thrash_threshold) {
-+			ret = 0;
-+		} else {
-+			ret = slot->pages_merged - slot->pages_cowed;
-+		}
-+	}
-+
-+	return ret * 100 / pages;
-+}
-+
-+/**
-+ * cal_dedup_ratio() - Calculate the deduplication ratio for this slot.
-+ */
-+static unsigned long cal_dedup_ratio_old(struct vma_slot *slot)
-+{
-+	unsigned long ret;
-+	unsigned long pages;
-+
-+	pages = slot->pages;
-+	if (!pages)
-+		return 0;
-+
-+	ret = slot->pages_bemerged;
-+
-+	/* Thrashing area filtering */
-+	if (ret && uksm_thrash_threshold) {
-+		if (slot->pages_cowed * 100 / slot->pages_bemerged
-+		    > uksm_thrash_threshold) {
-+			ret = 0;
-+		} else {
-+			ret = slot->pages_bemerged - slot->pages_cowed;
-+		}
-+	}
-+
-+	return ret * 100 / pages;
-+}
-+
-+/**
-+ * stable_node_reinsert() - When the hash_strength has been adjusted, the
-+ * stable tree need to be restructured, this is the function re-inserting the
-+ * stable node.
-+ */
-+static inline void stable_node_reinsert(struct stable_node *new_node,
-+					struct page *page,
-+					struct rb_root *root_treep,
-+					struct list_head *tree_node_listp,
-+					u32 hash)
-+{
-+	struct rb_node **new = &root_treep->rb_node;
-+	struct rb_node *parent = NULL;
-+	struct stable_node *stable_node;
-+	struct tree_node *tree_node;
-+	struct page *tree_page;
-+	int cmp;
-+
-+	while (*new) {
-+		int cmp;
-+
-+		tree_node = rb_entry(*new, struct tree_node, node);
-+
-+		cmp = hash_cmp(hash, tree_node->hash);
-+
-+		if (cmp < 0) {
-+			parent = *new;
-+			new = &parent->rb_left;
-+		} else if (cmp > 0) {
-+			parent = *new;
-+			new = &parent->rb_right;
-+		} else
-+			break;
-+	}
-+
-+	if (*new) {
-+		/* find a stable tree node with same first level hash value */
-+		stable_node_hash_max(new_node, page, hash);
-+		if (tree_node->count == 1) {
-+			stable_node = rb_entry(tree_node->sub_root.rb_node,
-+					       struct stable_node, node);
-+			tree_page = get_uksm_page(stable_node, 1, 0);
-+			if (tree_page) {
-+				stable_node_hash_max(stable_node,
-+						      tree_page, hash);
-+				put_page(tree_page);
-+
-+				/* prepare for stable node insertion */
-+
-+				cmp = hash_cmp(new_node->hash_max,
-+						   stable_node->hash_max);
-+				parent = &stable_node->node;
-+				if (cmp < 0)
-+					new = &parent->rb_left;
-+				else if (cmp > 0)
-+					new = &parent->rb_right;
-+				else
-+					goto failed;
-+
-+				goto add_node;
-+			} else {
-+				/* the only stable_node deleted, the tree node
-+				 * was not deleted.
-+				 */
-+				goto tree_node_reuse;
-+			}
-+		}
-+
-+		/* well, search the collision subtree */
-+		new = &tree_node->sub_root.rb_node;
-+		parent = NULL;
-+		BUG_ON(!*new);
-+		while (*new) {
-+			int cmp;
-+
-+			stable_node = rb_entry(*new, struct stable_node, node);
-+
-+			cmp = hash_cmp(new_node->hash_max,
-+					   stable_node->hash_max);
-+
-+			if (cmp < 0) {
-+				parent = *new;
-+				new = &parent->rb_left;
-+			} else if (cmp > 0) {
-+				parent = *new;
-+				new = &parent->rb_right;
-+			} else {
-+				/* oh, no, still a collision */
-+				goto failed;
-+			}
-+		}
-+
-+		goto add_node;
-+	}
-+
-+	/* no tree node found */
-+	tree_node = alloc_tree_node(tree_node_listp);
-+	if (!tree_node) {
-+		pr_err("UKSM: memory allocation error!\n");
-+		goto failed;
-+	} else {
-+		tree_node->hash = hash;
-+		rb_link_node(&tree_node->node, parent, new);
-+		rb_insert_color(&tree_node->node, root_treep);
-+
-+tree_node_reuse:
-+		/* prepare for stable node insertion */
-+		parent = NULL;
-+		new = &tree_node->sub_root.rb_node;
-+	}
-+
-+add_node:
-+	rb_link_node(&new_node->node, parent, new);
-+	rb_insert_color(&new_node->node, &tree_node->sub_root);
-+	new_node->tree_node = tree_node;
-+	tree_node->count++;
-+	return;
-+
-+failed:
-+	/* This can only happen when two nodes have collided
-+	 * in two levels.
-+	 */
-+	new_node->tree_node = NULL;
-+	return;
-+}
-+
-+static inline void free_all_tree_nodes(struct list_head *list)
-+{
-+	struct tree_node *node, *tmp;
-+
-+	list_for_each_entry_safe(node, tmp, list, all_list) {
-+		free_tree_node(node);
-+	}
-+}
-+
-+/**
-+ * stable_tree_delta_hash() - Delta hash the stable tree from previous hash
-+ * strength to the current hash_strength. It re-structures the hole tree.
-+ */
-+static inline void stable_tree_delta_hash(u32 prev_hash_strength)
-+{
-+	struct stable_node *node, *tmp;
-+	struct rb_root *root_new_treep;
-+	struct list_head *new_tree_node_listp;
-+
-+	stable_tree_index = (stable_tree_index + 1) % 2;
-+	root_new_treep = &root_stable_tree[stable_tree_index];
-+	new_tree_node_listp = &stable_tree_node_list[stable_tree_index];
-+	*root_new_treep = RB_ROOT;
-+	BUG_ON(!list_empty(new_tree_node_listp));
-+
-+	/*
-+	 * we need to be safe, the node could be removed by get_uksm_page()
-+	 */
-+	list_for_each_entry_safe(node, tmp, &stable_node_list, all_list) {
-+		void *addr;
-+		struct page *node_page;
-+		u32 hash;
-+
-+		/*
-+		 * We are completely re-structuring the stable nodes to a new
-+		 * stable tree. We don't want to touch the old tree unlinks and
-+		 * old tree_nodes. The old tree_nodes will be freed at once.
-+		 */
-+		node_page = get_uksm_page(node, 0, 0);
-+		if (!node_page)
-+			continue;
-+
-+		if (node->tree_node) {
-+			hash = node->tree_node->hash;
-+
-+			addr = kmap_atomic(node_page);
-+
-+			hash = delta_hash(addr, prev_hash_strength,
-+					  hash_strength, hash);
-+			kunmap_atomic(addr);
-+		} else {
-+			/*
-+			 *it was not inserted to rbtree due to collision in last
-+			 *round scan.
-+			 */
-+			hash = page_hash(node_page, hash_strength, 0);
-+		}
-+
-+		stable_node_reinsert(node, node_page, root_new_treep,
-+				     new_tree_node_listp, hash);
-+		put_page(node_page);
-+	}
-+
-+	root_stable_treep = root_new_treep;
-+	free_all_tree_nodes(stable_tree_node_listp);
-+	BUG_ON(!list_empty(stable_tree_node_listp));
-+	stable_tree_node_listp = new_tree_node_listp;
-+}
-+
-+static inline void inc_hash_strength(unsigned long delta)
-+{
-+	hash_strength += 1 << delta;
-+	if (hash_strength > HASH_STRENGTH_MAX)
-+		hash_strength = HASH_STRENGTH_MAX;
-+}
-+
-+static inline void dec_hash_strength(unsigned long delta)
-+{
-+	unsigned long change = 1 << delta;
-+
-+	if (hash_strength <= change + 1)
-+		hash_strength = 1;
-+	else
-+		hash_strength -= change;
-+}
-+
-+static inline void inc_hash_strength_delta(void)
-+{
-+	hash_strength_delta++;
-+	if (hash_strength_delta > HASH_STRENGTH_DELTA_MAX)
-+		hash_strength_delta = HASH_STRENGTH_DELTA_MAX;
-+}
-+
-+static inline unsigned long get_current_neg_ratio(void)
-+{
-+	u64 pos = benefit.pos;
-+	u64 neg = benefit.neg;
-+
-+	if (!neg)
-+		return 0;
-+
-+	if (!pos || neg > pos)
-+		return 100;
-+
-+	if (neg > div64_u64(U64_MAX, 100))
-+		pos = div64_u64(pos, 100);
-+	else
-+		neg *= 100;
-+
-+	return div64_u64(neg, pos);
-+}
-+
-+static inline unsigned long get_current_benefit(void)
-+{
-+	u64 pos = benefit.pos;
-+	u64 neg = benefit.neg;
-+	u64 scanned = benefit.scanned;
-+
-+	if (neg > pos)
-+		return 0;
-+
-+	return div64_u64((pos - neg), scanned);
-+}
-+
-+static inline int judge_rshash_direction(void)
-+{
-+	u64 current_neg_ratio, stable_benefit;
-+	u64 current_benefit, delta = 0;
-+	int ret = STILL;
-+
-+	/*
-+	 * Try to probe a value after the boot, and in case the system
-+	 * are still for a long time.
-+	 */
-+	if ((fully_scanned_round & 0xFFULL) == 10) {
-+		ret = OBSCURE;
-+		goto out;
-+	}
-+
-+	current_neg_ratio = get_current_neg_ratio();
-+
-+	if (current_neg_ratio == 0) {
-+		rshash_neg_cont_zero++;
-+		if (rshash_neg_cont_zero > 2)
-+			return GO_DOWN;
-+		else
-+			return STILL;
-+	}
-+	rshash_neg_cont_zero = 0;
-+
-+	if (current_neg_ratio > 90) {
-+		ret = GO_UP;
-+		goto out;
-+	}
-+
-+	current_benefit = get_current_benefit();
-+	stable_benefit = rshash_state.stable_benefit;
-+
-+	if (!stable_benefit) {
-+		ret = OBSCURE;
-+		goto out;
-+	}
-+
-+	if (current_benefit > stable_benefit)
-+		delta = current_benefit - stable_benefit;
-+	else if (current_benefit < stable_benefit)
-+		delta = stable_benefit - current_benefit;
-+
-+	delta = div64_u64(100 * delta, stable_benefit);
-+
-+	if (delta > 50) {
-+		rshash_cont_obscure++;
-+		if (rshash_cont_obscure > 2)
-+			return OBSCURE;
-+		else
-+			return STILL;
-+	}
-+
-+out:
-+	rshash_cont_obscure = 0;
-+	return ret;
-+}
-+
-+/**
-+ * rshash_adjust() - The main function to control the random sampling state
-+ * machine for hash strength adapting.
-+ *
-+ * return true if hash_strength has changed.
-+ */
-+static inline int rshash_adjust(void)
-+{
-+	unsigned long prev_hash_strength = hash_strength;
-+
-+	if (!encode_benefit())
-+		return 0;
-+
-+	switch (rshash_state.state) {
-+	case RSHASH_STILL:
-+		switch (judge_rshash_direction()) {
-+		case GO_UP:
-+			if (rshash_state.pre_direct == GO_DOWN)
-+				hash_strength_delta = 0;
-+
-+			inc_hash_strength(hash_strength_delta);
-+			inc_hash_strength_delta();
-+			rshash_state.stable_benefit = get_current_benefit();
-+			rshash_state.pre_direct = GO_UP;
-+			break;
-+
-+		case GO_DOWN:
-+			if (rshash_state.pre_direct == GO_UP)
-+				hash_strength_delta = 0;
-+
-+			dec_hash_strength(hash_strength_delta);
-+			inc_hash_strength_delta();
-+			rshash_state.stable_benefit = get_current_benefit();
-+			rshash_state.pre_direct = GO_DOWN;
-+			break;
-+
-+		case OBSCURE:
-+			rshash_state.stable_point = hash_strength;
-+			rshash_state.turn_point_down = hash_strength;
-+			rshash_state.turn_point_up = hash_strength;
-+			rshash_state.turn_benefit_down = get_current_benefit();
-+			rshash_state.turn_benefit_up = get_current_benefit();
-+			rshash_state.lookup_window_index = 0;
-+			rshash_state.state = RSHASH_TRYDOWN;
-+			dec_hash_strength(hash_strength_delta);
-+			inc_hash_strength_delta();
-+			break;
-+
-+		case STILL:
-+			break;
-+		default:
-+			BUG();
-+		}
-+		break;
-+
-+	case RSHASH_TRYDOWN:
-+		if (rshash_state.lookup_window_index++ % 5 == 0)
-+			rshash_state.below_count = 0;
-+
-+		if (get_current_benefit() < rshash_state.stable_benefit)
-+			rshash_state.below_count++;
-+		else if (get_current_benefit() >
-+			 rshash_state.turn_benefit_down) {
-+			rshash_state.turn_point_down = hash_strength;
-+			rshash_state.turn_benefit_down = get_current_benefit();
-+		}
-+
-+		if (rshash_state.below_count >= 3 ||
-+		    judge_rshash_direction() == GO_UP ||
-+		    hash_strength == 1) {
-+			hash_strength = rshash_state.stable_point;
-+			hash_strength_delta = 0;
-+			inc_hash_strength(hash_strength_delta);
-+			inc_hash_strength_delta();
-+			rshash_state.lookup_window_index = 0;
-+			rshash_state.state = RSHASH_TRYUP;
-+			hash_strength_delta = 0;
-+		} else {
-+			dec_hash_strength(hash_strength_delta);
-+			inc_hash_strength_delta();
-+		}
-+		break;
-+
-+	case RSHASH_TRYUP:
-+		if (rshash_state.lookup_window_index++ % 5 == 0)
-+			rshash_state.below_count = 0;
-+
-+		if (get_current_benefit() < rshash_state.turn_benefit_down)
-+			rshash_state.below_count++;
-+		else if (get_current_benefit() > rshash_state.turn_benefit_up) {
-+			rshash_state.turn_point_up = hash_strength;
-+			rshash_state.turn_benefit_up = get_current_benefit();
-+		}
-+
-+		if (rshash_state.below_count >= 3 ||
-+		    judge_rshash_direction() == GO_DOWN ||
-+		    hash_strength == HASH_STRENGTH_MAX) {
-+			hash_strength = rshash_state.turn_benefit_up >
-+				rshash_state.turn_benefit_down ?
-+				rshash_state.turn_point_up :
-+				rshash_state.turn_point_down;
-+
-+			rshash_state.state = RSHASH_PRE_STILL;
-+		} else {
-+			inc_hash_strength(hash_strength_delta);
-+			inc_hash_strength_delta();
-+		}
-+
-+		break;
-+
-+	case RSHASH_NEW:
-+	case RSHASH_PRE_STILL:
-+		rshash_state.stable_benefit = get_current_benefit();
-+		rshash_state.state = RSHASH_STILL;
-+		hash_strength_delta = 0;
-+		break;
-+	default:
-+		BUG();
-+	}
-+
-+	/* rshash_neg = rshash_pos = 0; */
-+	reset_benefit();
-+
-+	if (prev_hash_strength != hash_strength)
-+		stable_tree_delta_hash(prev_hash_strength);
-+
-+	return prev_hash_strength != hash_strength;
-+}
-+
-+/**
-+ * round_update_ladder() - The main function to do update of all the
-+ * adjustments whenever a scan round is finished.
-+ */
-+static noinline void round_update_ladder(void)
-+{
-+	int i;
-+	unsigned long dedup;
-+	struct vma_slot *slot, *tmp_slot;
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++)
-+		uksm_scan_ladder[i].flags &= ~UKSM_RUNG_ROUND_FINISHED;
-+
-+	list_for_each_entry_safe(slot, tmp_slot, &vma_slot_dedup, dedup_list) {
-+
-+		/* slot may be rung_rm_slot() when mm exits */
-+		if (slot->snode) {
-+			dedup = cal_dedup_ratio_old(slot);
-+			if (dedup && dedup >= uksm_abundant_threshold)
-+				vma_rung_up(slot);
-+		}
-+
-+		slot->pages_bemerged = 0;
-+		slot->pages_cowed = 0;
-+
-+		list_del_init(&slot->dedup_list);
-+	}
-+}
-+
-+static void uksm_del_vma_slot(struct vma_slot *slot)
-+{
-+	int i, j;
-+	struct rmap_list_entry *entry;
-+
-+	if (slot->snode) {
-+		/*
-+		 * In case it just failed when entering the rung, it's not
-+		 * necessary.
-+		 */
-+		rung_rm_slot(slot);
-+	}
-+
-+	if (!list_empty(&slot->dedup_list))
-+		list_del(&slot->dedup_list);
-+
-+	if (!slot->rmap_list_pool || !slot->pool_counts) {
-+		/* In case it OOMed in uksm_vma_enter() */
-+		goto out;
-+	}
-+
-+	for (i = 0; i < slot->pool_size; i++) {
-+		void *addr;
-+
-+		if (!slot->rmap_list_pool[i])
-+			continue;
-+
-+		addr = kmap(slot->rmap_list_pool[i]);
-+		for (j = 0; j < PAGE_SIZE / sizeof(*entry); j++) {
-+			entry = (struct rmap_list_entry *)addr + j;
-+			if (is_addr(entry->addr))
-+				continue;
-+			if (!entry->item)
-+				continue;
-+
-+			remove_rmap_item_from_tree(entry->item);
-+			free_rmap_item(entry->item);
-+			slot->pool_counts[i]--;
-+		}
-+		BUG_ON(slot->pool_counts[i]);
-+		kunmap(slot->rmap_list_pool[i]);
-+		__free_page(slot->rmap_list_pool[i]);
-+	}
-+	kfree(slot->rmap_list_pool);
-+	kfree(slot->pool_counts);
-+
-+out:
-+	slot->rung = NULL;
-+	if (slot->flags & UKSM_SLOT_IN_UKSM) {
-+		BUG_ON(uksm_pages_total < slot->pages);
-+		uksm_pages_total -= slot->pages;
-+	}
-+
-+	if (slot->fully_scanned_round == fully_scanned_round)
-+		scanned_virtual_pages -= slot->pages;
-+	else
-+		scanned_virtual_pages -= slot->pages_scanned;
-+	free_vma_slot(slot);
-+}
-+
-+
-+#define SPIN_LOCK_PERIOD	32
-+static struct vma_slot *cleanup_slots[SPIN_LOCK_PERIOD];
-+static inline void cleanup_vma_slots(void)
-+{
-+	struct vma_slot *slot;
-+	int i;
-+
-+	i = 0;
-+	spin_lock(&vma_slot_list_lock);
-+	while (!list_empty(&vma_slot_del)) {
-+		slot = list_entry(vma_slot_del.next,
-+				  struct vma_slot, slot_list);
-+		list_del(&slot->slot_list);
-+		cleanup_slots[i++] = slot;
-+		if (i == SPIN_LOCK_PERIOD) {
-+			spin_unlock(&vma_slot_list_lock);
-+			while (--i >= 0)
-+				uksm_del_vma_slot(cleanup_slots[i]);
-+			i = 0;
-+			spin_lock(&vma_slot_list_lock);
-+		}
-+	}
-+	spin_unlock(&vma_slot_list_lock);
-+
-+	while (--i >= 0)
-+		uksm_del_vma_slot(cleanup_slots[i]);
-+}
-+
-+/*
-+ * Expotional moving average formula
-+ */
-+static inline unsigned long ema(unsigned long curr, unsigned long last_ema)
-+{
-+	/*
-+	 * For a very high burst, even the ema cannot work well, a false very
-+	 * high per-page time estimation can result in feedback in very high
-+	 * overhead of context switch and rung update -- this will then lead
-+	 * to higher per-paper time, this may not converge.
-+	 *
-+	 * Instead, we try to approach this value in a binary manner.
-+	 */
-+	if (curr > last_ema * 10)
-+		return last_ema * 2;
-+
-+	return (EMA_ALPHA * curr + (100 - EMA_ALPHA) * last_ema) / 100;
-+}
-+
-+/*
-+ * convert cpu ratio in 1/TIME_RATIO_SCALE configured by user to
-+ * nanoseconds based on current uksm_sleep_jiffies.
-+ */
-+static inline unsigned long cpu_ratio_to_nsec(unsigned int ratio)
-+{
-+	return NSEC_PER_USEC * jiffies_to_usecs(uksm_sleep_jiffies) /
-+		(TIME_RATIO_SCALE - ratio) * ratio;
-+}
-+
-+
-+static inline unsigned long rung_real_ratio(int cpu_time_ratio)
-+{
-+	unsigned long ret;
-+
-+	BUG_ON(!cpu_time_ratio);
-+
-+	if (cpu_time_ratio > 0)
-+		ret = cpu_time_ratio;
-+	else
-+		ret = (unsigned long)(-cpu_time_ratio) *
-+			uksm_max_cpu_percentage / 100UL;
-+
-+	return ret ? ret : 1;
-+}
-+
-+static noinline void uksm_calc_scan_pages(void)
-+{
-+	struct scan_rung *ladder = uksm_scan_ladder;
-+	unsigned long sleep_usecs, nsecs;
-+	unsigned long ratio;
-+	int i;
-+	unsigned long per_page;
-+
-+	if (uksm_ema_page_time > 100000 ||
-+	    (((unsigned long) uksm_eval_round & (256UL - 1)) == 0UL))
-+		uksm_ema_page_time = UKSM_PAGE_TIME_DEFAULT;
-+
-+	per_page = uksm_ema_page_time;
-+	BUG_ON(!per_page);
-+
-+	/*
-+	 * For every 8 eval round, we try to probe a uksm_sleep_jiffies value
-+	 * based on saved user input.
-+	 */
-+	if (((unsigned long) uksm_eval_round & (8UL - 1)) == 0UL)
-+		uksm_sleep_jiffies = uksm_sleep_saved;
-+
-+	/* We require a rung scan at least 1 page in a period. */
-+	nsecs = per_page;
-+	ratio = rung_real_ratio(ladder[0].cpu_ratio);
-+	if (cpu_ratio_to_nsec(ratio) < nsecs) {
-+		sleep_usecs = nsecs * (TIME_RATIO_SCALE - ratio) / ratio
-+				/ NSEC_PER_USEC;
-+		uksm_sleep_jiffies = usecs_to_jiffies(sleep_usecs) + 1;
-+	}
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		ratio = rung_real_ratio(ladder[i].cpu_ratio);
-+		ladder[i].pages_to_scan = cpu_ratio_to_nsec(ratio) /
-+					per_page;
-+		BUG_ON(!ladder[i].pages_to_scan);
-+		uksm_calc_rung_step(&ladder[i], per_page, ratio);
-+	}
-+}
-+
-+/*
-+ * From the scan time of this round (ns) to next expected min sleep time
-+ * (ms), be careful of the possible overflows. ratio is taken from
-+ * rung_real_ratio()
-+ */
-+static inline
-+unsigned int scan_time_to_sleep(unsigned long long scan_time, unsigned long ratio)
-+{
-+	scan_time >>= 20; /* to msec level now */
-+	BUG_ON(scan_time > (ULONG_MAX / TIME_RATIO_SCALE));
-+
-+	return (unsigned int) ((unsigned long) scan_time *
-+			       (TIME_RATIO_SCALE - ratio) / ratio);
-+}
-+
-+#define __round_mask(x, y) ((__typeof__(x))((y)-1))
-+#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1)
-+
-+static void uksm_vma_enter(struct vma_slot **slots, unsigned long num)
-+{
-+	struct scan_rung *rung;
-+
-+	rung = &uksm_scan_ladder[0];
-+	rung_add_new_slots(rung, slots, num);
-+}
-+
-+static struct vma_slot *batch_slots[SLOT_TREE_NODE_STORE_SIZE];
-+
-+static void uksm_enter_all_slots(void)
-+{
-+	struct vma_slot *slot;
-+	unsigned long index;
-+	struct list_head empty_vma_list;
-+	int i;
-+
-+	i = 0;
-+	index = 0;
-+	INIT_LIST_HEAD(&empty_vma_list);
-+
-+	spin_lock(&vma_slot_list_lock);
-+	while (!list_empty(&vma_slot_new)) {
-+		slot = list_entry(vma_slot_new.next,
-+				  struct vma_slot, slot_list);
-+
-+		if (!slot->vma->anon_vma) {
-+			list_move(&slot->slot_list, &empty_vma_list);
-+		} else if (vma_can_enter(slot->vma)) {
-+			batch_slots[index++] = slot;
-+			list_del_init(&slot->slot_list);
-+		} else {
-+			list_move(&slot->slot_list, &vma_slot_noadd);
-+		}
-+
-+		if (++i == SPIN_LOCK_PERIOD ||
-+		    (index && !(index % SLOT_TREE_NODE_STORE_SIZE))) {
-+			spin_unlock(&vma_slot_list_lock);
-+
-+			if (index && !(index % SLOT_TREE_NODE_STORE_SIZE)) {
-+				uksm_vma_enter(batch_slots, index);
-+				index = 0;
-+			}
-+			i = 0;
-+			cond_resched();
-+			spin_lock(&vma_slot_list_lock);
-+		}
-+	}
-+
-+	list_splice(&empty_vma_list, &vma_slot_new);
-+
-+	spin_unlock(&vma_slot_list_lock);
-+
-+	if (index)
-+		uksm_vma_enter(batch_slots, index);
-+
-+}
-+
-+static inline int rung_round_finished(struct scan_rung *rung)
-+{
-+	return rung->flags & UKSM_RUNG_ROUND_FINISHED;
-+}
-+
-+static inline void judge_slot(struct vma_slot *slot)
-+{
-+	struct scan_rung *rung = slot->rung;
-+	unsigned long dedup;
-+	int deleted;
-+
-+	dedup = cal_dedup_ratio(slot);
-+	if (vma_fully_scanned(slot) && uksm_thrash_threshold)
-+		deleted = vma_rung_enter(slot, &uksm_scan_ladder[0]);
-+	else if (dedup && dedup >= uksm_abundant_threshold)
-+		deleted = vma_rung_up(slot);
-+	else
-+		deleted = vma_rung_down(slot);
-+
-+	slot->pages_merged = 0;
-+	slot->pages_cowed = 0;
-+	slot->this_sampled = 0;
-+
-+	if (vma_fully_scanned(slot))
-+		slot->pages_scanned = 0;
-+
-+	slot->last_scanned = slot->pages_scanned;
-+
-+	/* If its deleted in above, then rung was already advanced. */
-+	if (!deleted)
-+		advance_current_scan(rung);
-+}
-+
-+
-+static inline int hash_round_finished(void)
-+{
-+	if (scanned_virtual_pages > (uksm_pages_total >> 2)) {
-+		scanned_virtual_pages = 0;
-+		if (uksm_pages_scanned)
-+			fully_scanned_round++;
-+
-+		return 1;
-+	} else {
-+		return 0;
-+	}
-+}
-+
-+#define UKSM_MMSEM_BATCH	5
-+#define BUSY_RETRY		100
-+
-+/**
-+ * uksm_do_scan()  - the main worker function.
-+ */
-+static noinline void uksm_do_scan(void)
-+{
-+	struct vma_slot *slot, *iter;
-+	struct mm_struct *busy_mm;
-+	unsigned char round_finished, all_rungs_emtpy;
-+	int i, err, mmsem_batch;
-+	unsigned long pcost;
-+	long long delta_exec;
-+	unsigned long vpages, max_cpu_ratio;
-+	unsigned long long start_time, end_time, scan_time;
-+	unsigned int expected_jiffies;
-+
-+	might_sleep();
-+
-+	vpages = 0;
-+
-+	start_time = task_sched_runtime(current);
-+	max_cpu_ratio = 0;
-+	mmsem_batch = 0;
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE;) {
-+		struct scan_rung *rung = &uksm_scan_ladder[i];
-+		unsigned long ratio;
-+		int busy_retry;
-+
-+		if (!rung->pages_to_scan) {
-+			i++;
-+			continue;
-+		}
-+
-+		if (!rung->vma_root.num) {
-+			rung->pages_to_scan = 0;
-+			i++;
-+			continue;
-+		}
-+
-+		ratio = rung_real_ratio(rung->cpu_ratio);
-+		if (ratio > max_cpu_ratio)
-+			max_cpu_ratio = ratio;
-+
-+		busy_retry = BUSY_RETRY;
-+		/*
-+		 * Do not consider rung_round_finished() here, just used up the
-+		 * rung->pages_to_scan quota.
-+		 */
-+		while (rung->pages_to_scan && rung->vma_root.num &&
-+		       likely(!freezing(current))) {
-+			int reset = 0;
-+
-+			slot = rung->current_scan;
-+
-+			BUG_ON(vma_fully_scanned(slot));
-+
-+			if (mmsem_batch)
-+				err = 0;
-+			else
-+				err = try_down_read_slot_mmap_sem(slot);
-+
-+			if (err == -ENOENT) {
-+rm_slot:
-+				rung_rm_slot(slot);
-+				continue;
-+			}
-+
-+			busy_mm = slot->mm;
-+
-+			if (err == -EBUSY) {
-+				/* skip other vmas on the same mm */
-+				do {
-+					reset = advance_current_scan(rung);
-+					iter = rung->current_scan;
-+					busy_retry--;
-+					if (iter->vma->vm_mm != busy_mm ||
-+					    !busy_retry || reset)
-+						break;
-+				} while (1);
-+
-+				if (iter->vma->vm_mm != busy_mm) {
-+					continue;
-+				} else {
-+					/* scan round finsished */
-+					break;
-+				}
-+			}
-+
-+			BUG_ON(!vma_can_enter(slot->vma));
-+			if (uksm_test_exit(slot->vma->vm_mm)) {
-+				mmsem_batch = 0;
-+				mmap_read_unlock(slot->vma->vm_mm);
-+				goto rm_slot;
-+			}
-+
-+			if (mmsem_batch)
-+				mmsem_batch--;
-+			else
-+				mmsem_batch = UKSM_MMSEM_BATCH;
-+
-+			/* Ok, we have take the mmap_sem, ready to scan */
-+			scan_vma_one_page(slot);
-+			rung->pages_to_scan--;
-+			vpages++;
-+
-+			if (rung->current_offset + rung->step > slot->pages - 1
-+			    || vma_fully_scanned(slot)) {
-+				mmap_read_unlock(slot->vma->vm_mm);
-+				judge_slot(slot);
-+				mmsem_batch = 0;
-+			} else {
-+				rung->current_offset += rung->step;
-+				if (!mmsem_batch)
-+					mmap_read_unlock(slot->vma->vm_mm);
-+			}
-+
-+			busy_retry = BUSY_RETRY;
-+			cond_resched();
-+		}
-+
-+		if (mmsem_batch) {
-+			mmap_read_unlock(slot->vma->vm_mm);
-+			mmsem_batch = 0;
-+		}
-+
-+		if (freezing(current))
-+			break;
-+
-+		cond_resched();
-+	}
-+	end_time = task_sched_runtime(current);
-+	delta_exec = end_time - start_time;
-+
-+	if (freezing(current))
-+		return;
-+
-+	cleanup_vma_slots();
-+	uksm_enter_all_slots();
-+
-+	round_finished = 1;
-+	all_rungs_emtpy = 1;
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		struct scan_rung *rung = &uksm_scan_ladder[i];
-+
-+		if (rung->vma_root.num) {
-+			all_rungs_emtpy = 0;
-+			if (!rung_round_finished(rung))
-+				round_finished = 0;
-+		}
-+	}
-+
-+	if (all_rungs_emtpy)
-+		round_finished = 0;
-+
-+	if (round_finished) {
-+		round_update_ladder();
-+		uksm_eval_round++;
-+
-+		if (hash_round_finished() && rshash_adjust()) {
-+			/* Reset the unstable root iff hash strength changed */
-+			uksm_hash_round++;
-+			root_unstable_tree = RB_ROOT;
-+			free_all_tree_nodes(&unstable_tree_node_list);
-+		}
-+
-+		/*
-+		 * A number of pages can hang around indefinitely on per-cpu
-+		 * pagevecs, raised page count preventing write_protect_page
-+		 * from merging them.  Though it doesn't really matter much,
-+		 * it is puzzling to see some stuck in pages_volatile until
-+		 * other activity jostles them out, and they also prevented
-+		 * LTP's KSM test from succeeding deterministically; so drain
-+		 * them here (here rather than on entry to uksm_do_scan(),
-+		 * so we don't IPI too often when pages_to_scan is set low).
-+		 */
-+		lru_add_drain_all();
-+	}
-+
-+
-+	if (vpages && delta_exec > 0) {
-+		pcost = (unsigned long) delta_exec / vpages;
-+		if (likely(uksm_ema_page_time))
-+			uksm_ema_page_time = ema(pcost, uksm_ema_page_time);
-+		else
-+			uksm_ema_page_time = pcost;
-+	}
-+
-+	uksm_calc_scan_pages();
-+	uksm_sleep_real = uksm_sleep_jiffies;
-+	/* in case of radical cpu bursts, apply the upper bound */
-+	end_time = task_sched_runtime(current);
-+	if (max_cpu_ratio && end_time > start_time) {
-+		scan_time = end_time - start_time;
-+		expected_jiffies = msecs_to_jiffies(
-+			scan_time_to_sleep(scan_time, max_cpu_ratio));
-+
-+		if (expected_jiffies > uksm_sleep_real)
-+			uksm_sleep_real = expected_jiffies;
-+
-+		/* We have a 1 second up bound for responsiveness. */
-+		if (jiffies_to_msecs(uksm_sleep_real) > MSEC_PER_SEC)
-+			uksm_sleep_real = msecs_to_jiffies(1000);
-+	}
-+
-+	return;
-+}
-+
-+static int ksmd_should_run(void)
-+{
-+	return uksm_run & UKSM_RUN_MERGE;
-+}
-+
-+static int uksm_scan_thread(void *nothing)
-+{
-+	set_freezable();
-+	set_user_nice(current, 5);
-+
-+	while (!kthread_should_stop()) {
-+		mutex_lock(&uksm_thread_mutex);
-+		if (ksmd_should_run())
-+			uksm_do_scan();
-+		mutex_unlock(&uksm_thread_mutex);
-+
-+		try_to_freeze();
-+
-+		if (ksmd_should_run()) {
-+			schedule_timeout_interruptible(uksm_sleep_real);
-+			uksm_sleep_times++;
-+		} else {
-+			wait_event_freezable(uksm_thread_wait,
-+				ksmd_should_run() || kthread_should_stop());
-+		}
-+	}
-+	return 0;
-+}
-+
-+void rmap_walk_ksm(struct page *page, struct rmap_walk_control *rwc)
-+{
-+	struct stable_node *stable_node;
-+	struct node_vma *node_vma;
-+	struct rmap_item *rmap_item;
-+	int search_new_forks = 0;
-+	unsigned long address;
-+
-+	VM_BUG_ON_PAGE(!PageKsm(page), page);
-+	VM_BUG_ON_PAGE(!PageLocked(page), page);
-+
-+	stable_node = page_stable_node(page);
-+	if (!stable_node)
-+		return;
-+again:
-+	hlist_for_each_entry(node_vma, &stable_node->hlist, hlist) {
-+		hlist_for_each_entry(rmap_item, &node_vma->rmap_hlist, hlist) {
-+			struct anon_vma *anon_vma = rmap_item->anon_vma;
-+			struct anon_vma_chain *vmac;
-+			struct vm_area_struct *vma;
-+
-+			cond_resched();
-+			anon_vma_lock_read(anon_vma);
-+			anon_vma_interval_tree_foreach(vmac, &anon_vma->rb_root,
-+						       0, ULONG_MAX) {
-+				cond_resched();
-+				vma = vmac->vma;
-+				address = get_rmap_addr(rmap_item);
-+
-+				if (address < vma->vm_start ||
-+				    address >= vma->vm_end)
-+					continue;
-+
-+				if ((rmap_item->slot->vma == vma) ==
-+				    search_new_forks)
-+					continue;
-+
-+				if (rwc->invalid_vma && rwc->invalid_vma(vma, rwc->arg))
-+					continue;
-+
-+				if (!rwc->rmap_one(page, vma, address, rwc->arg)) {
-+					anon_vma_unlock_read(anon_vma);
-+					return;
-+				}
-+
-+				if (rwc->done && rwc->done(page)) {
-+					anon_vma_unlock_read(anon_vma);
-+					return;
-+				}
-+			}
-+			anon_vma_unlock_read(anon_vma);
-+		}
-+	}
-+	if (!search_new_forks++)
-+		goto again;
-+}
-+
-+#ifdef CONFIG_MIGRATION
-+/* Common ksm interface but may be specific to uksm */
-+void folio_migrate_ksm(struct folio *newfolio, struct folio *folio)
-+{
-+	struct stable_node *stable_node;
-+
-+	VM_BUG_ON_FOLIO(!folio_test_locked(folio), folio);
-+	VM_BUG_ON_FOLIO(!folio_test_locked(newfolio), newfolio);
-+	VM_BUG_ON_FOLIO(newfolio->mapping != folio->mapping, newfolio);
-+
-+	stable_node = folio_stable_node(folio);
-+	if (stable_node) {
-+		VM_BUG_ON_FOLIO(stable_node->kpfn != folio_pfn(folio), folio);
-+		stable_node->kpfn = folio_pfn(newfolio);
-+		/*
-+		 newfolio->mapping was set in advance; now we need smp_wmb()
-+		 * to make sure that the new stable_node->kpfn is visible
-+		 * to get_ksm_page() before it can see that folio->mapping
-+		 * has gone stale (or that folio_test_swapcache has been cleared).
-+		 */
-+		smp_wmb();
-+		set_page_stable_node(&folio->page, NULL);
-+	}
-+}
-+#endif /* CONFIG_MIGRATION */
-+
-+#ifdef CONFIG_MEMORY_HOTREMOVE
-+static struct stable_node *uksm_check_stable_tree(unsigned long start_pfn,
-+						 unsigned long end_pfn)
-+{
-+	struct rb_node *node;
-+
-+	for (node = rb_first(root_stable_treep); node; node = rb_next(node)) {
-+		struct stable_node *stable_node;
-+
-+		stable_node = rb_entry(node, struct stable_node, node);
-+		if (stable_node->kpfn >= start_pfn &&
-+		    stable_node->kpfn < end_pfn)
-+			return stable_node;
-+	}
-+	return NULL;
-+}
-+
-+static int uksm_memory_callback(struct notifier_block *self,
-+			       unsigned long action, void *arg)
-+{
-+	struct memory_notify *mn = arg;
-+	struct stable_node *stable_node;
-+
-+	switch (action) {
-+	case MEM_GOING_OFFLINE:
-+		/*
-+		 * Keep it very simple for now: just lock out ksmd and
-+		 * MADV_UNMERGEABLE while any memory is going offline.
-+		 * mutex_lock_nested() is necessary because lockdep was alarmed
-+		 * that here we take uksm_thread_mutex inside notifier chain
-+		 * mutex, and later take notifier chain mutex inside
-+		 * uksm_thread_mutex to unlock it.   But that's safe because both
-+		 * are inside mem_hotplug_mutex.
-+		 */
-+		mutex_lock_nested(&uksm_thread_mutex, SINGLE_DEPTH_NESTING);
-+		break;
-+
-+	case MEM_OFFLINE:
-+		/*
-+		 * Most of the work is done by page migration; but there might
-+		 * be a few stable_nodes left over, still pointing to struct
-+		 * pages which have been offlined: prune those from the tree.
-+		 */
-+		while ((stable_node = uksm_check_stable_tree(mn->start_pfn,
-+					mn->start_pfn + mn->nr_pages)) != NULL)
-+			remove_node_from_stable_tree(stable_node, 1, 1);
-+		/* fallthrough */
-+
-+	case MEM_CANCEL_OFFLINE:
-+		mutex_unlock(&uksm_thread_mutex);
-+		break;
-+	}
-+	return NOTIFY_OK;
-+}
-+#endif /* CONFIG_MEMORY_HOTREMOVE */
-+
-+#ifdef CONFIG_SYSFS
-+/*
-+ * This all compiles without CONFIG_SYSFS, but is a waste of space.
-+ */
-+
-+#define UKSM_ATTR_RO(_name) \
-+	static struct kobj_attribute _name##_attr = __ATTR_RO(_name)
-+#define UKSM_ATTR(_name) \
-+	static struct kobj_attribute _name##_attr = \
-+		__ATTR(_name, 0644, _name##_show, _name##_store)
-+
-+static ssize_t max_cpu_percentage_show(struct kobject *kobj,
-+				    struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%u\n", uksm_max_cpu_percentage);
-+}
-+
-+static ssize_t max_cpu_percentage_store(struct kobject *kobj,
-+				     struct kobj_attribute *attr,
-+				     const char *buf, size_t count)
-+{
-+	unsigned long max_cpu_percentage;
-+	int err;
-+
-+	err = kstrtoul(buf, 10, &max_cpu_percentage);
-+	if (err || max_cpu_percentage > 100)
-+		return -EINVAL;
-+
-+	if (max_cpu_percentage == 100)
-+		max_cpu_percentage = 99;
-+	else if (max_cpu_percentage < 10)
-+		max_cpu_percentage = 10;
-+
-+	uksm_max_cpu_percentage = max_cpu_percentage;
-+
-+	return count;
-+}
-+UKSM_ATTR(max_cpu_percentage);
-+
-+static ssize_t sleep_millisecs_show(struct kobject *kobj,
-+				    struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%u\n", jiffies_to_msecs(uksm_sleep_jiffies));
-+}
-+
-+static ssize_t sleep_millisecs_store(struct kobject *kobj,
-+				     struct kobj_attribute *attr,
-+				     const char *buf, size_t count)
-+{
-+	unsigned long msecs;
-+	int err;
-+
-+	err = kstrtoul(buf, 10, &msecs);
-+	if (err || msecs > MSEC_PER_SEC)
-+		return -EINVAL;
-+
-+	uksm_sleep_jiffies = msecs_to_jiffies(msecs);
-+	uksm_sleep_saved = uksm_sleep_jiffies;
-+
-+	return count;
-+}
-+UKSM_ATTR(sleep_millisecs);
-+
-+
-+static ssize_t cpu_governor_show(struct kobject *kobj,
-+				  struct kobj_attribute *attr, char *buf)
-+{
-+	int n = sizeof(uksm_cpu_governor_str) / sizeof(char *);
-+	int i;
-+
-+	buf[0] = '\0';
-+	for (i = 0; i < n ; i++) {
-+		if (uksm_cpu_governor == i)
-+			strcat(buf, "[");
-+
-+		strcat(buf, uksm_cpu_governor_str[i]);
-+
-+		if (uksm_cpu_governor == i)
-+			strcat(buf, "]");
-+
-+		strcat(buf, " ");
-+	}
-+	strcat(buf, "\n");
-+
-+	return strlen(buf);
-+}
-+
-+static inline void init_performance_values(void)
-+{
-+	int i;
-+	struct scan_rung *rung;
-+	struct uksm_cpu_preset_s *preset = uksm_cpu_preset + uksm_cpu_governor;
-+
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		rung = uksm_scan_ladder + i;
-+		rung->cpu_ratio = preset->cpu_ratio[i];
-+		rung->cover_msecs = preset->cover_msecs[i];
-+	}
-+
-+	uksm_max_cpu_percentage = preset->max_cpu;
-+}
-+
-+static ssize_t cpu_governor_store(struct kobject *kobj,
-+				   struct kobj_attribute *attr,
-+				   const char *buf, size_t count)
-+{
-+	int n = sizeof(uksm_cpu_governor_str) / sizeof(char *);
-+
-+	for (n--; n >= 0 ; n--) {
-+		if (!strncmp(buf, uksm_cpu_governor_str[n],
-+			     strlen(uksm_cpu_governor_str[n])))
-+			break;
-+	}
-+
-+	if (n < 0)
-+		return -EINVAL;
-+	else
-+		uksm_cpu_governor = n;
-+
-+	init_performance_values();
-+
-+	return count;
-+}
-+UKSM_ATTR(cpu_governor);
-+
-+static ssize_t run_show(struct kobject *kobj, struct kobj_attribute *attr,
-+			char *buf)
-+{
-+	return sprintf(buf, "%u\n", uksm_run);
-+}
-+
-+static ssize_t run_store(struct kobject *kobj, struct kobj_attribute *attr,
-+			 const char *buf, size_t count)
-+{
-+	int err;
-+	unsigned long flags;
-+
-+	err = kstrtoul(buf, 10, &flags);
-+	if (err || flags > UINT_MAX)
-+		return -EINVAL;
-+	if (flags > UKSM_RUN_MERGE)
-+		return -EINVAL;
-+
-+	mutex_lock(&uksm_thread_mutex);
-+	if (uksm_run != flags)
-+		uksm_run = flags;
-+	mutex_unlock(&uksm_thread_mutex);
-+
-+	if (flags & UKSM_RUN_MERGE)
-+		wake_up_interruptible(&uksm_thread_wait);
-+
-+	return count;
-+}
-+UKSM_ATTR(run);
-+
-+static ssize_t abundant_threshold_show(struct kobject *kobj,
-+				     struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%u\n", uksm_abundant_threshold);
-+}
-+
-+static ssize_t abundant_threshold_store(struct kobject *kobj,
-+				      struct kobj_attribute *attr,
-+				      const char *buf, size_t count)
-+{
-+	int err;
-+	unsigned long flags;
-+
-+	err = kstrtoul(buf, 10, &flags);
-+	if (err || flags > 99)
-+		return -EINVAL;
-+
-+	uksm_abundant_threshold = flags;
-+
-+	return count;
-+}
-+UKSM_ATTR(abundant_threshold);
-+
-+static ssize_t thrash_threshold_show(struct kobject *kobj,
-+				     struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%u\n", uksm_thrash_threshold);
-+}
-+
-+static ssize_t thrash_threshold_store(struct kobject *kobj,
-+				      struct kobj_attribute *attr,
-+				      const char *buf, size_t count)
-+{
-+	int err;
-+	unsigned long flags;
-+
-+	err = kstrtoul(buf, 10, &flags);
-+	if (err || flags > 99)
-+		return -EINVAL;
-+
-+	uksm_thrash_threshold = flags;
-+
-+	return count;
-+}
-+UKSM_ATTR(thrash_threshold);
-+
-+static ssize_t cpu_ratios_show(struct kobject *kobj,
-+			       struct kobj_attribute *attr, char *buf)
-+{
-+	int i, size;
-+	struct scan_rung *rung;
-+	char *p = buf;
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		rung = &uksm_scan_ladder[i];
-+
-+		if (rung->cpu_ratio > 0)
-+			size = sprintf(p, "%d ", rung->cpu_ratio);
-+		else
-+			size = sprintf(p, "MAX/%d ",
-+					TIME_RATIO_SCALE / -rung->cpu_ratio);
-+
-+		p += size;
-+	}
-+
-+	*p++ = '\n';
-+	*p = '\0';
-+
-+	return p - buf;
-+}
-+
-+static ssize_t cpu_ratios_store(struct kobject *kobj,
-+				      struct kobj_attribute *attr,
-+				      const char *buf, size_t count)
-+{
-+	int i, cpuratios[SCAN_LADDER_SIZE], err;
-+	unsigned long value;
-+	struct scan_rung *rung;
-+	char *p, *end = NULL;
-+
-+	p = kzalloc(count, GFP_KERNEL);
-+	if (!p)
-+		return -ENOMEM;
-+
-+	memcpy(p, buf, count);
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		if (i != SCAN_LADDER_SIZE - 1) {
-+			end = strchr(p, ' ');
-+			if (!end)
-+				return -EINVAL;
-+
-+			*end = '\0';
-+		}
-+
-+		if (strstr(p, "MAX/")) {
-+			p = strchr(p, '/') + 1;
-+			err = kstrtoul(p, 10, &value);
-+			if (err || value > TIME_RATIO_SCALE || !value)
-+				return -EINVAL;
-+
-+			cpuratios[i] = -(int) (TIME_RATIO_SCALE / value);
-+		} else {
-+			err = kstrtoul(p, 10, &value);
-+			if (err || value > TIME_RATIO_SCALE || !value)
-+				return -EINVAL;
-+
-+			cpuratios[i] = value;
-+		}
-+
-+		p = end + 1;
-+	}
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		rung = &uksm_scan_ladder[i];
-+
-+		rung->cpu_ratio = cpuratios[i];
-+	}
-+
-+	return count;
-+}
-+UKSM_ATTR(cpu_ratios);
-+
-+static ssize_t eval_intervals_show(struct kobject *kobj,
-+			       struct kobj_attribute *attr, char *buf)
-+{
-+	int i, size;
-+	struct scan_rung *rung;
-+	char *p = buf;
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		rung = &uksm_scan_ladder[i];
-+		size = sprintf(p, "%u ", rung->cover_msecs);
-+		p += size;
-+	}
-+
-+	*p++ = '\n';
-+	*p = '\0';
-+
-+	return p - buf;
-+}
-+
-+static ssize_t eval_intervals_store(struct kobject *kobj,
-+				      struct kobj_attribute *attr,
-+				      const char *buf, size_t count)
-+{
-+	int i, err;
-+	unsigned long values[SCAN_LADDER_SIZE];
-+	struct scan_rung *rung;
-+	char *p, *end = NULL;
-+	ssize_t ret = count;
-+
-+	p = kzalloc(count + 2, GFP_KERNEL);
-+	if (!p)
-+		return -ENOMEM;
-+
-+	memcpy(p, buf, count);
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		if (i != SCAN_LADDER_SIZE - 1) {
-+			end = strchr(p, ' ');
-+			if (!end) {
-+				ret = -EINVAL;
-+				goto out;
-+			}
-+
-+			*end = '\0';
-+		}
-+
-+		err = kstrtoul(p, 10, &values[i]);
-+		if (err) {
-+			ret = -EINVAL;
-+			goto out;
-+		}
-+
-+		p = end + 1;
-+	}
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		rung = &uksm_scan_ladder[i];
-+
-+		rung->cover_msecs = values[i];
-+	}
-+
-+out:
-+	kfree(p);
-+	return ret;
-+}
-+UKSM_ATTR(eval_intervals);
-+
-+static ssize_t ema_per_page_time_show(struct kobject *kobj,
-+				 struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%lu\n", uksm_ema_page_time);
-+}
-+UKSM_ATTR_RO(ema_per_page_time);
-+
-+static ssize_t pages_shared_show(struct kobject *kobj,
-+				 struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%lu\n", uksm_pages_shared);
-+}
-+UKSM_ATTR_RO(pages_shared);
-+
-+static ssize_t pages_sharing_show(struct kobject *kobj,
-+				  struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%lu\n", uksm_pages_sharing);
-+}
-+UKSM_ATTR_RO(pages_sharing);
-+
-+static ssize_t pages_unshared_show(struct kobject *kobj,
-+				   struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%lu\n", uksm_pages_unshared);
-+}
-+UKSM_ATTR_RO(pages_unshared);
-+
-+static ssize_t full_scans_show(struct kobject *kobj,
-+			       struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%llu\n", fully_scanned_round);
-+}
-+UKSM_ATTR_RO(full_scans);
-+
-+static ssize_t pages_scanned_show(struct kobject *kobj,
-+				  struct kobj_attribute *attr, char *buf)
-+{
-+	unsigned long base = 0;
-+	u64 delta, ret;
-+
-+	if (pages_scanned_stored) {
-+		base = pages_scanned_base;
-+		ret = pages_scanned_stored;
-+		delta = uksm_pages_scanned >> base;
-+		if (CAN_OVERFLOW_U64(ret, delta)) {
-+			ret >>= 1;
-+			delta >>= 1;
-+			base++;
-+			ret += delta;
-+		}
-+	} else {
-+		ret = uksm_pages_scanned;
-+	}
-+
-+	while (ret > ULONG_MAX) {
-+		ret >>= 1;
-+		base++;
-+	}
-+
-+	if (base)
-+		return sprintf(buf, "%lu * 2^%lu\n", (unsigned long)ret, base);
-+	else
-+		return sprintf(buf, "%lu\n", (unsigned long)ret);
-+}
-+UKSM_ATTR_RO(pages_scanned);
-+
-+static ssize_t hash_strength_show(struct kobject *kobj,
-+				  struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%lu\n", hash_strength);
-+}
-+UKSM_ATTR_RO(hash_strength);
-+
-+static ssize_t sleep_times_show(struct kobject *kobj,
-+				  struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%llu\n", uksm_sleep_times);
-+}
-+UKSM_ATTR_RO(sleep_times);
-+
-+
-+static struct attribute *uksm_attrs[] = {
-+	&max_cpu_percentage_attr.attr,
-+	&sleep_millisecs_attr.attr,
-+	&cpu_governor_attr.attr,
-+	&run_attr.attr,
-+	&ema_per_page_time_attr.attr,
-+	&pages_shared_attr.attr,
-+	&pages_sharing_attr.attr,
-+	&pages_unshared_attr.attr,
-+	&full_scans_attr.attr,
-+	&pages_scanned_attr.attr,
-+	&hash_strength_attr.attr,
-+	&sleep_times_attr.attr,
-+	&thrash_threshold_attr.attr,
-+	&abundant_threshold_attr.attr,
-+	&cpu_ratios_attr.attr,
-+	&eval_intervals_attr.attr,
-+	NULL,
-+};
-+
-+static struct attribute_group uksm_attr_group = {
-+	.attrs = uksm_attrs,
-+	.name = "uksm",
-+};
-+#endif /* CONFIG_SYSFS */
-+
-+static inline void init_scan_ladder(void)
-+{
-+	int i;
-+	struct scan_rung *rung;
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		rung = uksm_scan_ladder + i;
-+		slot_tree_init_root(&rung->vma_root);
-+	}
-+
-+	init_performance_values();
-+	uksm_calc_scan_pages();
-+}
-+
-+static inline int cal_positive_negative_costs(void)
-+{
-+	struct page *p1, *p2;
-+	unsigned char *addr1, *addr2;
-+	unsigned long i, time_start, hash_cost;
-+	unsigned long loopnum = 0;
-+
-+	/*IMPORTANT: volatile is needed to prevent over-optimization by gcc. */
-+	volatile u32 hash;
-+	volatile int ret;
-+
-+	p1 = alloc_page(GFP_KERNEL);
-+	if (!p1)
-+		return -ENOMEM;
-+
-+	p2 = alloc_page(GFP_KERNEL);
-+	if (!p2)
-+		return -ENOMEM;
-+
-+	addr1 = kmap_atomic(p1);
-+	addr2 = kmap_atomic(p2);
-+	memset(addr1, prandom_u32(), PAGE_SIZE);
-+	memcpy(addr2, addr1, PAGE_SIZE);
-+
-+	/* make sure that the two pages differ in last byte */
-+	addr2[PAGE_SIZE-1] = ~addr2[PAGE_SIZE-1];
-+	kunmap_atomic(addr2);
-+	kunmap_atomic(addr1);
-+
-+	time_start = jiffies;
-+	while (jiffies - time_start < 100) {
-+		for (i = 0; i < 100; i++)
-+			hash = page_hash(p1, HASH_STRENGTH_FULL, 0);
-+		loopnum += 100;
-+	}
-+	hash_cost = (jiffies - time_start);
-+
-+	time_start = jiffies;
-+	for (i = 0; i < loopnum; i++)
-+		ret = pages_identical_with_cost(p1, p2);
-+	memcmp_cost = HASH_STRENGTH_FULL * (jiffies - time_start);
-+	memcmp_cost /= hash_cost;
-+	pr_info("UKSM: relative memcmp_cost = %lu "
-+		"hash=%u cmp_ret=%d.\n",
-+		memcmp_cost, hash, ret);
-+
-+	__free_page(p1);
-+	__free_page(p2);
-+	return 0;
-+}
-+
-+static int init_zeropage_hash_table(void)
-+{
-+	struct page *page;
-+	char *addr;
-+	int i;
-+
-+	page = alloc_page(GFP_KERNEL);
-+	if (!page)
-+		return -ENOMEM;
-+
-+	addr = kmap_atomic(page);
-+	memset(addr, 0, PAGE_SIZE);
-+	kunmap_atomic(addr);
-+
-+	zero_hash_table = kmalloc_array(HASH_STRENGTH_MAX, sizeof(u32),
-+		GFP_KERNEL);
-+	if (!zero_hash_table)
-+		return -ENOMEM;
-+
-+	for (i = 0; i < HASH_STRENGTH_MAX; i++)
-+		zero_hash_table[i] = page_hash(page, i, 0);
-+
-+	__free_page(page);
-+
-+	return 0;
-+}
-+
-+static inline int init_random_sampling(void)
-+{
-+	unsigned long i;
-+
-+	random_nums = kmalloc(PAGE_SIZE, GFP_KERNEL);
-+	if (!random_nums)
-+		return -ENOMEM;
-+
-+	for (i = 0; i < HASH_STRENGTH_FULL; i++)
-+		random_nums[i] = i;
-+
-+	for (i = 0; i < HASH_STRENGTH_FULL; i++) {
-+		unsigned long rand_range, swap_index, tmp;
-+
-+		rand_range = HASH_STRENGTH_FULL - i;
-+		swap_index = i + prandom_u32() % rand_range;
-+		tmp = random_nums[i];
-+		random_nums[i] =  random_nums[swap_index];
-+		random_nums[swap_index] = tmp;
-+	}
-+
-+	rshash_state.state = RSHASH_NEW;
-+	rshash_state.below_count = 0;
-+	rshash_state.lookup_window_index = 0;
-+
-+	return cal_positive_negative_costs();
-+}
-+
-+static int __init uksm_slab_init(void)
-+{
-+	rmap_item_cache = UKSM_KMEM_CACHE(rmap_item, 0);
-+	if (!rmap_item_cache)
-+		goto out;
-+
-+	stable_node_cache = UKSM_KMEM_CACHE(stable_node, 0);
-+	if (!stable_node_cache)
-+		goto out_free1;
-+
-+	node_vma_cache = UKSM_KMEM_CACHE(node_vma, 0);
-+	if (!node_vma_cache)
-+		goto out_free2;
-+
-+	vma_slot_cache = UKSM_KMEM_CACHE(vma_slot, 0);
-+	if (!vma_slot_cache)
-+		goto out_free3;
-+
-+	tree_node_cache = UKSM_KMEM_CACHE(tree_node, 0);
-+	if (!tree_node_cache)
-+		goto out_free4;
-+
-+	return 0;
-+
-+out_free4:
-+	kmem_cache_destroy(vma_slot_cache);
-+out_free3:
-+	kmem_cache_destroy(node_vma_cache);
-+out_free2:
-+	kmem_cache_destroy(stable_node_cache);
-+out_free1:
-+	kmem_cache_destroy(rmap_item_cache);
-+out:
-+	return -ENOMEM;
-+}
-+
-+static void __init uksm_slab_free(void)
-+{
-+	kmem_cache_destroy(stable_node_cache);
-+	kmem_cache_destroy(rmap_item_cache);
-+	kmem_cache_destroy(node_vma_cache);
-+	kmem_cache_destroy(vma_slot_cache);
-+	kmem_cache_destroy(tree_node_cache);
-+}
-+
-+/* Common interface to ksm, different to it. */
-+int ksm_madvise(struct vm_area_struct *vma, unsigned long start,
-+		unsigned long end, int advice, unsigned long *vm_flags)
-+{
-+	int err;
-+
-+	switch (advice) {
-+	case MADV_MERGEABLE:
-+		return 0;		/* just ignore the advice */
-+
-+	case MADV_UNMERGEABLE:
-+		if (!(*vm_flags & VM_MERGEABLE) || !uksm_flags_can_scan(*vm_flags))
-+			return 0;		/* just ignore the advice */
-+
-+		if (vma->anon_vma) {
-+			err = unmerge_uksm_pages(vma, start, end);
-+			if (err)
-+				return err;
-+		}
-+
-+		uksm_remove_vma(vma);
-+		*vm_flags &= ~VM_MERGEABLE;
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+/* Common interface to ksm, actually the same. */
-+struct page *ksm_might_need_to_copy(struct page *page,
-+			struct vm_area_struct *vma, unsigned long address)
-+{
-+	struct anon_vma *anon_vma = page_anon_vma(page);
-+	struct page *new_page;
-+
-+	if (PageKsm(page)) {
-+		if (page_stable_node(page))
-+			return page;	/* no need to copy it */
-+	} else if (!anon_vma) {
-+		return page;		/* no need to copy it */
-+	} else if (page->index == linear_page_index(vma, address) &&
-+			anon_vma->root == vma->anon_vma->root) {
-+		return page;		/* still no need to copy it */
-+	}
-+	if (!PageUptodate(page))
-+		return page;		/* let do_swap_page report the error */
-+
-+	new_page = alloc_page_vma(GFP_HIGHUSER_MOVABLE, vma, address);
-+	if (new_page) {
-+		copy_user_highpage(new_page, page, address, vma);
-+
-+		SetPageDirty(new_page);
-+		__SetPageUptodate(new_page);
-+		__SetPageLocked(new_page);
-+	}
-+
-+	return new_page;
-+}
-+
-+/* Copied from mm/ksm.c and required from 5.1 */
-+bool reuse_ksm_page(struct page *page,
-+		    struct vm_area_struct *vma,
-+		    unsigned long address)
-+{
-+#ifdef CONFIG_DEBUG_VM
-+	if (WARN_ON(is_zero_pfn(page_to_pfn(page))) ||
-+			WARN_ON(!page_mapped(page)) ||
-+			WARN_ON(!PageLocked(page))) {
-+		dump_page(page, "reuse_ksm_page");
-+		return false;
-+	}
-+#endif
-+
-+	if (PageSwapCache(page) || !page_stable_node(page))
-+		return false;
-+	/* Prohibit parallel get_ksm_page() */
-+	if (!page_ref_freeze(page, 1))
-+		return false;
-+
-+	page_move_anon_rmap(page, vma);
-+	page->index = linear_page_index(vma, address);
-+	page_ref_unfreeze(page, 1);
-+
-+	return true;
-+}
-+
-+static int __init uksm_init(void)
-+{
-+	struct task_struct *uksm_thread;
-+	int err;
-+
-+	uksm_sleep_jiffies = msecs_to_jiffies(100);
-+	uksm_sleep_saved = uksm_sleep_jiffies;
-+
-+	slot_tree_init();
-+	init_scan_ladder();
-+
-+
-+	err = init_random_sampling();
-+	if (err)
-+		goto out_free2;
-+
-+	err = uksm_slab_init();
-+	if (err)
-+		goto out_free1;
-+
-+	err = init_zeropage_hash_table();
-+	if (err)
-+		goto out_free0;
-+
-+	uksm_thread = kthread_run(uksm_scan_thread, NULL, "uksmd");
-+	if (IS_ERR(uksm_thread)) {
-+		pr_err("uksm: creating kthread failed\n");
-+		err = PTR_ERR(uksm_thread);
-+		goto out_free;
-+	}
-+
-+#ifdef CONFIG_SYSFS
-+	err = sysfs_create_group(mm_kobj, &uksm_attr_group);
-+	if (err) {
-+		pr_err("uksm: register sysfs failed\n");
-+		kthread_stop(uksm_thread);
-+		goto out_free;
-+	}
-+#else
-+	uksm_run = UKSM_RUN_MERGE;	/* no way for user to start it */
-+
-+#endif /* CONFIG_SYSFS */
-+
-+#ifdef CONFIG_MEMORY_HOTREMOVE
-+	/*
-+	 * Choose a high priority since the callback takes uksm_thread_mutex:
-+	 * later callbacks could only be taking locks which nest within that.
-+	 */
-+	hotplug_memory_notifier(uksm_memory_callback, 100);
-+#endif
-+	return 0;
-+
-+out_free:
-+	kfree(zero_hash_table);
-+out_free0:
-+	uksm_slab_free();
-+out_free1:
-+	kfree(random_nums);
-+out_free2:
-+	kfree(uksm_scan_ladder);
-+	return err;
-+}
-+
-+#ifdef MODULE
-+subsys_initcall(ksm_init);
-+#else
-+late_initcall(uksm_init);
-+#endif
-+
-diff -up linux-5.17/mm/vmstat.c.12~ linux-5.17/mm/vmstat.c
---- linux-5.17/mm/vmstat.c.12~	2022-03-20 21:14:17.000000000 +0100
-+++ linux-5.17/mm/vmstat.c	2022-03-26 17:17:42.871812637 +0100
-@@ -1243,6 +1243,9 @@ const char * const vmstat_text[] = {
- 	"nr_swapcached",
- #endif
- 
-+#ifdef CONFIG_UKSM
-+	"nr_uksm_zero_pages",
-+#endif
- 	/* enum writeback_stat_item counters */
- 	"nr_dirty_threshold",
- 	"nr_dirty_background_threshold",
diff --git a/0001-UKSM-for-5.18.patch b/0001-UKSM-for-5.18.patch
deleted file mode 100644
index d502bb7..0000000
--- a/0001-UKSM-for-5.18.patch
+++ /dev/null
@@ -1,6948 +0,0 @@
-From d7684394e05a00bd299e5579d5017294a14e7abd Mon Sep 17 00:00:00 2001
-From: Piotr Gorski <lucjan.lucjanov@gmail.com>
-Date: Mon, 16 May 2022 14:57:25 +0200
-Subject: [PATCH] UKSM for 5.18
-
-Signed-off-by: Piotr Gorski <lucjan.lucjanov@gmail.com>
----
- Documentation/vm/uksm.txt   |   61 +
- fs/exec.c                   |    1 +
- fs/proc/meminfo.c           |    4 +
- include/linux/ksm.h         |   43 +-
- include/linux/mm_types.h    |    3 +
- include/linux/mmzone.h      |    3 +
- include/linux/pgtable.h     |   17 +-
- include/linux/sradix-tree.h |   77 +
- include/linux/uksm.h        |  149 +
- kernel/fork.c               |    2 +-
- lib/Makefile                |    2 +-
- lib/sradix-tree.c           |  476 +++
- mm/Kconfig                  |   26 +
- mm/Makefile                 |    3 +-
- mm/ksm.c                    |   11 -
- mm/memory.c                 |   33 +-
- mm/mmap.c                   |   28 +
- mm/uksm.c                   | 5607 +++++++++++++++++++++++++++++++++++
- mm/vmstat.c                 |    3 +
- 19 files changed, 6523 insertions(+), 26 deletions(-)
- create mode 100644 Documentation/vm/uksm.txt
- create mode 100644 include/linux/sradix-tree.h
- create mode 100644 include/linux/uksm.h
- create mode 100644 lib/sradix-tree.c
- create mode 100644 mm/uksm.c
-
-diff --git a/Documentation/vm/uksm.txt b/Documentation/vm/uksm.txt
-new file mode 100644
-index 000000000..be19a3127
---- /dev/null
-+++ b/Documentation/vm/uksm.txt
-@@ -0,0 +1,61 @@
-+The Ultra Kernel Samepage Merging feature
-+----------------------------------------------
-+/*
-+ * Ultra KSM. Copyright (C) 2011-2012 Nai Xia
-+ *
-+ * This is an improvement upon KSM. Some basic data structures and routines
-+ * are borrowed from ksm.c .
-+ *
-+ * Its new features:
-+ * 1. Full system scan:
-+ *      It automatically scans all user processes' anonymous VMAs. Kernel-user
-+ *      interaction to submit a memory area to KSM is no longer needed.
-+ *
-+ * 2. Rich area detection:
-+ *      It automatically detects rich areas containing abundant duplicated
-+ *      pages based. Rich areas are given a full scan speed. Poor areas are
-+ *      sampled at a reasonable speed with very low CPU consumption.
-+ *
-+ * 3. Ultra Per-page scan speed improvement:
-+ *      A new hash algorithm is proposed. As a result, on a machine with
-+ *      Core(TM)2 Quad Q9300 CPU in 32-bit mode and 800MHZ DDR2 main memory, it
-+ *      can scan memory areas that does not contain duplicated pages at speed of
-+ *      627MB/sec ~ 2445MB/sec and can merge duplicated areas at speed of
-+ *      477MB/sec ~ 923MB/sec.
-+ *
-+ * 4. Thrashing area avoidance:
-+ *      Thrashing area(an VMA that has frequent Ksm page break-out) can be
-+ *      filtered out. My benchmark shows it's more efficient than KSM's per-page
-+ *      hash value based volatile page detection.
-+ *
-+ *
-+ * 5. Misc changes upon KSM:
-+ *      * It has a fully x86-opitmized memcmp dedicated for 4-byte-aligned page
-+ *        comparison. It's much faster than default C version on x86.
-+ *      * rmap_item now has an struct *page member to loosely cache a
-+ *        address-->page mapping, which reduces too much time-costly
-+ *        follow_page().
-+ *      * The VMA creation/exit procedures are hooked to let the Ultra KSM know.
-+ *      * try_to_merge_two_pages() now can revert a pte if it fails. No break_
-+ *        ksm is needed for this case.
-+ *
-+ * 6. Full Zero Page consideration(contributed by Figo Zhang)
-+ *    Now uksmd consider full zero pages as special pages and merge them to an
-+ *    special unswappable uksm zero page.
-+ */
-+
-+ChangeLog:
-+
-+2012-05-05 The creation of this Doc
-+2012-05-08 UKSM 0.1.1.1 libc crash bug fix, api clean up, doc clean up.
-+2012-05-28 UKSM 0.1.1.2 bug fix release
-+2012-06-26 UKSM 0.1.2-beta1 first beta release for 0.1.2
-+2012-07-2  UKSM 0.1.2-beta2
-+2012-07-10 UKSM 0.1.2-beta3
-+2012-07-26 UKSM 0.1.2 Fine grained speed control, more scan optimization.
-+2012-10-13 UKSM 0.1.2.1 Bug fixes.
-+2012-12-31 UKSM 0.1.2.2 Minor bug fixes.
-+2014-07-02 UKSM 0.1.2.3 Fix a " __this_cpu_read() in preemptible bug".
-+2015-04-22 UKSM 0.1.2.4 Fix a race condition that can sometimes trigger anonying warnings.
-+2016-09-10 UKSM 0.1.2.5 Fix a bug in dedup ratio calculation.
-+2017-02-26 UKSM 0.1.2.6 Fix a bug in hugetlbpage handling and a race bug with page migration.
-diff --git a/fs/exec.c b/fs/exec.c
-index e3e55d5e0..0cde46283 100644
---- a/fs/exec.c
-+++ b/fs/exec.c
-@@ -65,6 +65,7 @@
- #include <linux/io_uring.h>
- #include <linux/syscall_user_dispatch.h>
- #include <linux/coredump.h>
-+#include <linux/ksm.h>
- 
- #include <linux/uaccess.h>
- #include <asm/mmu_context.h>
-diff --git a/fs/proc/meminfo.c b/fs/proc/meminfo.c
-index 6fa761c9c..45fd59a0d 100644
---- a/fs/proc/meminfo.c
-+++ b/fs/proc/meminfo.c
-@@ -108,6 +108,10 @@ static int meminfo_proc_show(struct seq_file *m, void *v)
- #endif
- 	show_val_kb(m, "PageTables:     ",
- 		    global_node_page_state(NR_PAGETABLE));
-+#ifdef CONFIG_UKSM
-+	show_val_kb(m, "KsmZeroPages:     ",
-+		    global_zone_page_state(NR_UKSM_ZERO_PAGES));
-+#endif
- 
- 	show_val_kb(m, "NFS_Unstable:   ", 0);
- 	show_val_kb(m, "Bounce:         ",
-diff --git a/include/linux/ksm.h b/include/linux/ksm.h
-index 0630e545f..116adb978 100644
---- a/include/linux/ksm.h
-+++ b/include/linux/ksm.h
-@@ -21,20 +21,16 @@ struct mem_cgroup;
- #ifdef CONFIG_KSM
- int ksm_madvise(struct vm_area_struct *vma, unsigned long start,
- 		unsigned long end, int advice, unsigned long *vm_flags);
--int __ksm_enter(struct mm_struct *mm);
--void __ksm_exit(struct mm_struct *mm);
- 
--static inline int ksm_fork(struct mm_struct *mm, struct mm_struct *oldmm)
-+static inline struct stable_node *page_stable_node(struct page *page)
- {
--	if (test_bit(MMF_VM_MERGEABLE, &oldmm->flags))
--		return __ksm_enter(mm);
--	return 0;
-+	return PageKsm(page) ? page_rmapping(page) : NULL;
- }
- 
--static inline void ksm_exit(struct mm_struct *mm)
-+static inline void set_page_stable_node(struct page *page,
-+					struct stable_node *stable_node)
- {
--	if (test_bit(MMF_VM_MERGEABLE, &mm->flags))
--		__ksm_exit(mm);
-+	page->mapping = (void *)((unsigned long)stable_node | PAGE_MAPPING_KSM);
- }
- 
- /*
-@@ -54,6 +50,33 @@ struct page *ksm_might_need_to_copy(struct page *page,
- void rmap_walk_ksm(struct folio *folio, const struct rmap_walk_control *rwc);
- void folio_migrate_ksm(struct folio *newfolio, struct folio *folio);
- 
-+#ifdef CONFIG_KSM_LEGACY
-+int __ksm_enter(struct mm_struct *mm);
-+void __ksm_exit(struct mm_struct *mm);
-+static inline int ksm_fork(struct mm_struct *mm, struct mm_struct *oldmm)
-+{
-+	if (test_bit(MMF_VM_MERGEABLE, &oldmm->flags))
-+		return __ksm_enter(mm);
-+	return 0;
-+}
-+
-+static inline void ksm_exit(struct mm_struct *mm)
-+{
-+	if (test_bit(MMF_VM_MERGEABLE, &mm->flags))
-+		__ksm_exit(mm);
-+}
-+
-+#elif defined(CONFIG_UKSM)
-+static inline int ksm_fork(struct mm_struct *mm, struct mm_struct *oldmm)
-+{
-+	return 0;
-+}
-+
-+static inline void ksm_exit(struct mm_struct *mm)
-+{
-+}
-+#endif /* !CONFIG_UKSM */
-+
- #else  /* !CONFIG_KSM */
- 
- static inline int ksm_fork(struct mm_struct *mm, struct mm_struct *oldmm)
-@@ -89,4 +112,6 @@ static inline void folio_migrate_ksm(struct folio *newfolio, struct folio *old)
- #endif /* CONFIG_MMU */
- #endif /* !CONFIG_KSM */
- 
-+#include <linux/uksm.h>
-+
- #endif /* __LINUX_KSM_H */
-diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h
-index 8834e38c0..22eea9b91 100644
---- a/include/linux/mm_types.h
-+++ b/include/linux/mm_types.h
-@@ -470,6 +470,9 @@ struct vm_area_struct {
- 	struct mempolicy *vm_policy;	/* NUMA policy for the VMA */
- #endif
- 	struct vm_userfaultfd_ctx vm_userfaultfd_ctx;
-+#ifdef CONFIG_UKSM
-+	struct vma_slot *uksm_vma_slot;
-+#endif
- } __randomize_layout;
- 
- struct kioctx_table;
-diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
-index 46ffab808..b7fde97fd 100644
---- a/include/linux/mmzone.h
-+++ b/include/linux/mmzone.h
-@@ -169,6 +169,9 @@ enum zone_stat_item {
- 	NR_ZSPAGES,		/* allocated in zsmalloc */
- #endif
- 	NR_FREE_CMA_PAGES,
-+#ifdef CONFIG_UKSM
-+	NR_UKSM_ZERO_PAGES,
-+#endif
- 	NR_VM_ZONE_STAT_ITEMS };
- 
- enum node_stat_item {
-diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h
-index f4f4077b9..c3f27907d 100644
---- a/include/linux/pgtable.h
-+++ b/include/linux/pgtable.h
-@@ -1146,13 +1146,26 @@ extern void untrack_pfn(struct vm_area_struct *vma, unsigned long pfn,
- extern void untrack_pfn_moved(struct vm_area_struct *vma);
- #endif
- 
-+#ifdef CONFIG_UKSM
-+static inline int is_uksm_zero_pfn(unsigned long pfn)
-+{
-+	extern unsigned long uksm_zero_pfn;
-+	return pfn == uksm_zero_pfn;
-+}
-+#else
-+static inline int is_uksm_zero_pfn(unsigned long pfn)
-+{
-+	return 0;
-+}
-+#endif
-+
- #ifdef CONFIG_MMU
- #ifdef __HAVE_COLOR_ZERO_PAGE
- static inline int is_zero_pfn(unsigned long pfn)
- {
- 	extern unsigned long zero_pfn;
- 	unsigned long offset_from_zero_pfn = pfn - zero_pfn;
--	return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
-+	return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT) || is_uksm_zero_pfn(pfn);
- }
- 
- #define my_zero_pfn(addr)	page_to_pfn(ZERO_PAGE(addr))
-@@ -1161,7 +1174,7 @@ static inline int is_zero_pfn(unsigned long pfn)
- static inline int is_zero_pfn(unsigned long pfn)
- {
- 	extern unsigned long zero_pfn;
--	return pfn == zero_pfn;
-+	return (pfn == zero_pfn) || (is_uksm_zero_pfn(pfn));
- }
- 
- static inline unsigned long my_zero_pfn(unsigned long addr)
-diff --git a/include/linux/sradix-tree.h b/include/linux/sradix-tree.h
-new file mode 100644
-index 000000000..d71edba6b
---- /dev/null
-+++ b/include/linux/sradix-tree.h
-@@ -0,0 +1,77 @@
-+#ifndef _LINUX_SRADIX_TREE_H
-+#define _LINUX_SRADIX_TREE_H
-+
-+
-+#define INIT_SRADIX_TREE(root, mask)					\
-+do {									\
-+	(root)->height = 0;						\
-+	(root)->gfp_mask = (mask);					\
-+	(root)->rnode = NULL;						\
-+} while (0)
-+
-+#define ULONG_BITS	(sizeof(unsigned long) * 8)
-+#define SRADIX_TREE_INDEX_BITS  (8 /* CHAR_BIT */ * sizeof(unsigned long))
-+//#define SRADIX_TREE_MAP_SHIFT	6
-+//#define SRADIX_TREE_MAP_SIZE	(1UL << SRADIX_TREE_MAP_SHIFT)
-+//#define SRADIX_TREE_MAP_MASK	(SRADIX_TREE_MAP_SIZE-1)
-+
-+struct sradix_tree_node {
-+	unsigned int	height;		/* Height from the bottom */
-+	unsigned int	count;
-+	unsigned int	fulls;		/* Number of full sublevel trees */
-+	struct sradix_tree_node *parent;
-+	void *stores[0];
-+};
-+
-+/* A simple radix tree implementation */
-+struct sradix_tree_root {
-+	unsigned int            height;
-+	struct sradix_tree_node *rnode;
-+
-+	/* Where found to have available empty stores in its sublevels */
-+	struct sradix_tree_node *enter_node;
-+	unsigned int shift;
-+	unsigned int stores_size;
-+	unsigned int mask;
-+	unsigned long min;	/* The first hole index */
-+	unsigned long num;
-+	//unsigned long *height_to_maxindex;
-+
-+	/* How the node is allocated and freed. */
-+	struct sradix_tree_node *(*alloc)(void);
-+	void (*free)(struct sradix_tree_node *node);
-+
-+	/* When a new node is added and removed */
-+	void (*extend)(struct sradix_tree_node *parent, struct sradix_tree_node *child);
-+	void (*assign)(struct sradix_tree_node *node, unsigned int index, void *item);
-+	void (*rm)(struct sradix_tree_node *node, unsigned int offset);
-+};
-+
-+struct sradix_tree_path {
-+	struct sradix_tree_node *node;
-+	int offset;
-+};
-+
-+static inline
-+void init_sradix_tree_root(struct sradix_tree_root *root, unsigned long shift)
-+{
-+	root->height = 0;
-+	root->rnode = NULL;
-+	root->shift = shift;
-+	root->stores_size = 1UL << shift;
-+	root->mask = root->stores_size - 1;
-+}
-+
-+
-+extern void *sradix_tree_next(struct sradix_tree_root *root,
-+		       struct sradix_tree_node *node, unsigned long index,
-+		       int (*iter)(void *, unsigned long));
-+
-+extern int sradix_tree_enter(struct sradix_tree_root *root, void **item, int num);
-+
-+extern void sradix_tree_delete_from_leaf(struct sradix_tree_root *root,
-+			struct sradix_tree_node *node, unsigned long index);
-+
-+extern void *sradix_tree_lookup(struct sradix_tree_root *root, unsigned long index);
-+
-+#endif /* _LINUX_SRADIX_TREE_H */
-diff --git a/include/linux/uksm.h b/include/linux/uksm.h
-new file mode 100644
-index 000000000..bb8651f53
---- /dev/null
-+++ b/include/linux/uksm.h
-@@ -0,0 +1,149 @@
-+#ifndef __LINUX_UKSM_H
-+#define __LINUX_UKSM_H
-+/*
-+ * Memory merging support.
-+ *
-+ * This code enables dynamic sharing of identical pages found in different
-+ * memory areas, even if they are not shared by fork().
-+ */
-+
-+/* if !CONFIG_UKSM this file should not be compiled at all. */
-+#ifdef CONFIG_UKSM
-+
-+#include <linux/bitops.h>
-+#include <linux/mm.h>
-+#include <linux/pagemap.h>
-+#include <linux/rmap.h>
-+#include <linux/sched.h>
-+
-+extern unsigned long zero_pfn __read_mostly;
-+extern unsigned long uksm_zero_pfn __read_mostly;
-+extern struct page *empty_uksm_zero_page;
-+
-+/* must be done before linked to mm */
-+extern void uksm_vma_add_new(struct vm_area_struct *vma);
-+extern void uksm_remove_vma(struct vm_area_struct *vma);
-+
-+#define UKSM_SLOT_NEED_SORT	(1 << 0)
-+#define UKSM_SLOT_NEED_RERAND	(1 << 1)
-+#define UKSM_SLOT_SCANNED	(1 << 2) /* It's scanned in this round */
-+#define UKSM_SLOT_FUL_SCANNED	(1 << 3)
-+#define UKSM_SLOT_IN_UKSM	(1 << 4)
-+
-+struct vma_slot {
-+	struct sradix_tree_node *snode;
-+	unsigned long sindex;
-+
-+	struct list_head slot_list;
-+	unsigned long fully_scanned_round;
-+	unsigned long dedup_num;
-+	unsigned long pages_scanned;
-+	unsigned long this_sampled;
-+	unsigned long last_scanned;
-+	unsigned long pages_to_scan;
-+	struct scan_rung *rung;
-+	struct page **rmap_list_pool;
-+	unsigned int *pool_counts;
-+	unsigned long pool_size;
-+	struct vm_area_struct *vma;
-+	struct mm_struct *mm;
-+	unsigned long ctime_j;
-+	unsigned long pages;
-+	unsigned long flags;
-+	unsigned long pages_cowed; /* pages cowed this round */
-+	unsigned long pages_merged; /* pages merged this round */
-+	unsigned long pages_bemerged;
-+
-+	/* when it has page merged in this eval round */
-+	struct list_head dedup_list;
-+};
-+
-+static inline void uksm_unmap_zero_page(pte_t pte)
-+{
-+	if (pte_pfn(pte) == uksm_zero_pfn)
-+		__dec_zone_page_state(empty_uksm_zero_page, NR_UKSM_ZERO_PAGES);
-+}
-+
-+static inline void uksm_map_zero_page(pte_t pte)
-+{
-+	if (pte_pfn(pte) == uksm_zero_pfn)
-+		__inc_zone_page_state(empty_uksm_zero_page, NR_UKSM_ZERO_PAGES);
-+}
-+
-+static inline void uksm_cow_page(struct vm_area_struct *vma, struct page *page)
-+{
-+	if (vma->uksm_vma_slot && PageKsm(page))
-+		vma->uksm_vma_slot->pages_cowed++;
-+}
-+
-+static inline void uksm_cow_pte(struct vm_area_struct *vma, pte_t pte)
-+{
-+	if (vma->uksm_vma_slot && pte_pfn(pte) == uksm_zero_pfn)
-+		vma->uksm_vma_slot->pages_cowed++;
-+}
-+
-+static inline int uksm_flags_can_scan(unsigned long vm_flags)
-+{
-+#ifdef VM_SAO
-+		if (vm_flags & VM_SAO)
-+			return 0;
-+#endif
-+
-+	return !(vm_flags & (VM_PFNMAP | VM_IO  | VM_DONTEXPAND |
-+			     VM_HUGETLB | VM_MIXEDMAP | VM_SHARED
-+			     | VM_MAYSHARE | VM_GROWSUP | VM_GROWSDOWN));
-+}
-+
-+static inline void uksm_vm_flags_mod(unsigned long *vm_flags_p)
-+{
-+	if (uksm_flags_can_scan(*vm_flags_p))
-+		*vm_flags_p |= VM_MERGEABLE;
-+}
-+
-+/*
-+ * Just a wrapper for BUG_ON for where ksm_zeropage must not be. TODO: it will
-+ * be removed when uksm zero page patch is stable enough.
-+ */
-+static inline void uksm_bugon_zeropage(pte_t pte)
-+{
-+	BUG_ON(pte_pfn(pte) == uksm_zero_pfn);
-+}
-+#else
-+static inline void uksm_vma_add_new(struct vm_area_struct *vma)
-+{
-+}
-+
-+static inline void uksm_remove_vma(struct vm_area_struct *vma)
-+{
-+}
-+
-+static inline void uksm_unmap_zero_page(pte_t pte)
-+{
-+}
-+
-+static inline void uksm_map_zero_page(pte_t pte)
-+{
-+}
-+
-+static inline void uksm_cow_page(struct vm_area_struct *vma, struct page *page)
-+{
-+}
-+
-+static inline void uksm_cow_pte(struct vm_area_struct *vma, pte_t pte)
-+{
-+}
-+
-+static inline int uksm_flags_can_scan(unsigned long vm_flags)
-+{
-+	return 0;
-+}
-+
-+static inline void uksm_vm_flags_mod(unsigned long *vm_flags_p)
-+{
-+}
-+
-+static inline void uksm_bugon_zeropage(pte_t pte)
-+{
-+}
-+#endif /* !CONFIG_UKSM */
-+#endif /* __LINUX_UKSM_H */
-diff --git a/kernel/fork.c b/kernel/fork.c
-index 35a3beff1..191965568 100644
---- a/kernel/fork.c
-+++ b/kernel/fork.c
-@@ -695,7 +695,7 @@ static __latent_entropy int dup_mmap(struct mm_struct *mm,
- 		__vma_link_rb(mm, tmp, rb_link, rb_parent);
- 		rb_link = &tmp->vm_rb.rb_right;
- 		rb_parent = &tmp->vm_rb;
--
-+		uksm_vma_add_new(tmp);
- 		mm->map_count++;
- 		if (!(tmp->vm_flags & VM_WIPEONFORK))
- 			retval = copy_page_range(tmp, mpnt);
-diff --git a/lib/Makefile b/lib/Makefile
-index 6b9ffc1bd..2bb1a2067 100644
---- a/lib/Makefile
-+++ b/lib/Makefile
-@@ -28,7 +28,7 @@ CFLAGS_string.o += -fno-stack-protector
- endif
- 
- lib-y := ctype.o string.o vsprintf.o cmdline.o \
--	 rbtree.o radix-tree.o timerqueue.o xarray.o \
-+	 rbtree.o radix-tree.o sradix-tree.o timerqueue.o xarray.o \
- 	 idr.o extable.o sha1.o irq_regs.o argv_split.o \
- 	 flex_proportions.o ratelimit.o show_mem.o \
- 	 is_single_threaded.o plist.o decompress.o kobject_uevent.o \
-diff --git a/lib/sradix-tree.c b/lib/sradix-tree.c
-new file mode 100644
-index 000000000..ab21e6309
---- /dev/null
-+++ b/lib/sradix-tree.c
-@@ -0,0 +1,476 @@
-+#include <linux/errno.h>
-+#include <linux/mm.h>
-+#include <linux/mman.h>
-+#include <linux/spinlock.h>
-+#include <linux/slab.h>
-+#include <linux/gcd.h>
-+#include <linux/sradix-tree.h>
-+
-+static inline int sradix_node_full(struct sradix_tree_root *root, struct sradix_tree_node *node)
-+{
-+	return node->fulls == root->stores_size ||
-+		(node->height == 1 && node->count == root->stores_size);
-+}
-+
-+/*
-+ *	Extend a sradix tree so it can store key @index.
-+ */
-+static int sradix_tree_extend(struct sradix_tree_root *root, unsigned long index)
-+{
-+	struct sradix_tree_node *node;
-+	unsigned int height;
-+
-+	if (unlikely(root->rnode == NULL)) {
-+		if (!(node = root->alloc()))
-+			return -ENOMEM;
-+
-+		node->height = 1;
-+		root->rnode = node;
-+		root->height = 1;
-+	}
-+
-+	/* Figure out what the height should be.  */
-+	height = root->height;
-+	index >>= root->shift * height;
-+
-+	while (index) {
-+		index >>= root->shift;
-+		height++;
-+	}
-+
-+	while (height > root->height) {
-+		unsigned int newheight;
-+
-+		if (!(node = root->alloc()))
-+			return -ENOMEM;
-+
-+		/* Increase the height.  */
-+		node->stores[0] = root->rnode;
-+		root->rnode->parent = node;
-+		if (root->extend)
-+			root->extend(node, root->rnode);
-+
-+		newheight = root->height + 1;
-+		node->height = newheight;
-+		node->count = 1;
-+		if (sradix_node_full(root, root->rnode))
-+			node->fulls = 1;
-+
-+		root->rnode = node;
-+		root->height = newheight;
-+	}
-+
-+	return 0;
-+}
-+
-+/*
-+ * Search the next item from the current node, that is not NULL
-+ * and can satify root->iter().
-+ */
-+void *sradix_tree_next(struct sradix_tree_root *root,
-+		       struct sradix_tree_node *node, unsigned long index,
-+		       int (*iter)(void *item, unsigned long height))
-+{
-+	unsigned long offset;
-+	void *item;
-+
-+	if (unlikely(node == NULL)) {
-+		node = root->rnode;
-+		for (offset = 0; offset < root->stores_size; offset++) {
-+			item = node->stores[offset];
-+			if (item && (!iter || iter(item, node->height)))
-+				break;
-+		}
-+
-+		if (unlikely(offset >= root->stores_size))
-+			return NULL;
-+
-+		if (node->height == 1)
-+			return item;
-+		else
-+			goto go_down;
-+	}
-+
-+	while (node) {
-+		offset = (index & root->mask) + 1;
-+		for (; offset < root->stores_size; offset++) {
-+			item = node->stores[offset];
-+			if (item && (!iter || iter(item, node->height)))
-+				break;
-+		}
-+
-+		if (offset < root->stores_size)
-+			break;
-+
-+		node = node->parent;
-+		index >>= root->shift;
-+	}
-+
-+	if (!node)
-+		return NULL;
-+
-+	while (node->height > 1) {
-+go_down:
-+		node = item;
-+		for (offset = 0; offset < root->stores_size; offset++) {
-+			item = node->stores[offset];
-+			if (item && (!iter || iter(item, node->height)))
-+				break;
-+		}
-+
-+		if (unlikely(offset >= root->stores_size))
-+			return NULL;
-+	}
-+
-+	BUG_ON(offset > root->stores_size);
-+
-+	return item;
-+}
-+
-+/*
-+ * Blindly insert the item to the tree. Typically, we reuse the
-+ * first empty store item.
-+ */
-+int sradix_tree_enter(struct sradix_tree_root *root, void **item, int num)
-+{
-+	unsigned long index;
-+	unsigned int height;
-+	struct sradix_tree_node *node, *tmp = NULL;
-+	int offset, offset_saved;
-+	void **store = NULL;
-+	int error, i, j, shift;
-+
-+go_on:
-+	index = root->min;
-+
-+	if (root->enter_node && !sradix_node_full(root, root->enter_node)) {
-+		node = root->enter_node;
-+		BUG_ON((index >> (root->shift * root->height)));
-+	} else {
-+		node = root->rnode;
-+		if (node == NULL || (index >> (root->shift * root->height))
-+		    || sradix_node_full(root, node)) {
-+			error = sradix_tree_extend(root, index);
-+			if (error)
-+				return error;
-+
-+			node = root->rnode;
-+		}
-+	}
-+
-+
-+	height = node->height;
-+	shift = (height - 1) * root->shift;
-+	offset = (index >> shift) & root->mask;
-+	while (shift > 0) {
-+		offset_saved = offset;
-+		for (; offset < root->stores_size; offset++) {
-+			store = &node->stores[offset];
-+			tmp = *store;
-+
-+			if (!tmp || !sradix_node_full(root, tmp))
-+				break;
-+		}
-+		BUG_ON(offset >= root->stores_size);
-+
-+		if (offset != offset_saved) {
-+			index += (offset - offset_saved) << shift;
-+			index &= ~((1UL << shift) - 1);
-+		}
-+
-+		if (!tmp) {
-+			if (!(tmp = root->alloc()))
-+				return -ENOMEM;
-+
-+			tmp->height = shift / root->shift;
-+			*store = tmp;
-+			tmp->parent = node;
-+			node->count++;
-+//			if (root->extend)
-+//				root->extend(node, tmp);
-+		}
-+
-+		node = tmp;
-+		shift -= root->shift;
-+		offset = (index >> shift) & root->mask;
-+	}
-+
-+	BUG_ON(node->height != 1);
-+
-+
-+	store = &node->stores[offset];
-+	for (i = 0, j = 0;
-+	      j < root->stores_size - node->count &&
-+	      i < root->stores_size - offset && j < num; i++) {
-+		if (!store[i]) {
-+			store[i] = item[j];
-+			if (root->assign)
-+				root->assign(node, index + i, item[j]);
-+			j++;
-+		}
-+	}
-+
-+	node->count += j;
-+	root->num += j;
-+	num -= j;
-+
-+	while (sradix_node_full(root, node)) {
-+		node = node->parent;
-+		if (!node)
-+			break;
-+
-+		node->fulls++;
-+	}
-+
-+	if (unlikely(!node)) {
-+		/* All nodes are full */
-+		root->min = 1 << (root->height * root->shift);
-+		root->enter_node = NULL;
-+	} else {
-+		root->min = index + i - 1;
-+		root->min |= (1UL << (node->height - 1)) - 1;
-+		root->min++;
-+		root->enter_node = node;
-+	}
-+
-+	if (num) {
-+		item += j;
-+		goto go_on;
-+	}
-+
-+	return 0;
-+}
-+
-+
-+/**
-+ *	sradix_tree_shrink    -    shrink height of a sradix tree to minimal
-+ *      @root		sradix tree root
-+ *
-+ */
-+static inline void sradix_tree_shrink(struct sradix_tree_root *root)
-+{
-+	/* try to shrink tree height */
-+	while (root->height > 1) {
-+		struct sradix_tree_node *to_free = root->rnode;
-+
-+		/*
-+		 * The candidate node has more than one child, or its child
-+		 * is not at the leftmost store, we cannot shrink.
-+		 */
-+		if (to_free->count != 1 || !to_free->stores[0])
-+			break;
-+
-+		root->rnode = to_free->stores[0];
-+		root->rnode->parent = NULL;
-+		root->height--;
-+		if (unlikely(root->enter_node == to_free))
-+			root->enter_node = NULL;
-+		root->free(to_free);
-+	}
-+}
-+
-+/*
-+ * Del the item on the known leaf node and index
-+ */
-+void sradix_tree_delete_from_leaf(struct sradix_tree_root *root,
-+				  struct sradix_tree_node *node, unsigned long index)
-+{
-+	unsigned int offset;
-+	struct sradix_tree_node *start, *end;
-+
-+	BUG_ON(node->height != 1);
-+
-+	start = node;
-+	while (node && !(--node->count))
-+		node = node->parent;
-+
-+	end = node;
-+	if (!node) {
-+		root->rnode = NULL;
-+		root->height = 0;
-+		root->min = 0;
-+		root->num = 0;
-+		root->enter_node = NULL;
-+	} else {
-+		offset = (index >> (root->shift * (node->height - 1))) & root->mask;
-+		if (root->rm)
-+			root->rm(node, offset);
-+		node->stores[offset] = NULL;
-+		root->num--;
-+		if (root->min > index) {
-+			root->min = index;
-+			root->enter_node = node;
-+		}
-+	}
-+
-+	if (start != end) {
-+		do {
-+			node = start;
-+			start = start->parent;
-+			if (unlikely(root->enter_node == node))
-+				root->enter_node = end;
-+			root->free(node);
-+		} while (start != end);
-+
-+		/*
-+		 * Note that shrink may free "end", so enter_node still need to
-+		 * be checked inside.
-+		 */
-+		sradix_tree_shrink(root);
-+	} else if (node->count == root->stores_size - 1) {
-+		/* It WAS a full leaf node. Update the ancestors */
-+		node = node->parent;
-+		while (node) {
-+			node->fulls--;
-+			if (node->fulls != root->stores_size - 1)
-+				break;
-+
-+			node = node->parent;
-+		}
-+	}
-+}
-+
-+void *sradix_tree_lookup(struct sradix_tree_root *root, unsigned long index)
-+{
-+	unsigned int height, offset;
-+	struct sradix_tree_node *node;
-+	int shift;
-+
-+	node = root->rnode;
-+	if (node == NULL || (index >> (root->shift * root->height)))
-+		return NULL;
-+
-+	height = root->height;
-+	shift = (height - 1) * root->shift;
-+
-+	do {
-+		offset = (index >> shift) & root->mask;
-+		node = node->stores[offset];
-+		if (!node)
-+			return NULL;
-+
-+		shift -= root->shift;
-+	} while (shift >= 0);
-+
-+	return node;
-+}
-+
-+/*
-+ * Return the item if it exists, otherwise create it in place
-+ * and return the created item.
-+ */
-+void *sradix_tree_lookup_create(struct sradix_tree_root *root,
-+			unsigned long index, void *(*item_alloc)(void))
-+{
-+	unsigned int height, offset;
-+	struct sradix_tree_node *node, *tmp;
-+	void *item;
-+	int shift, error;
-+
-+	if (root->rnode == NULL || (index >> (root->shift * root->height))) {
-+		if (item_alloc) {
-+			error = sradix_tree_extend(root, index);
-+			if (error)
-+				return NULL;
-+		} else {
-+			return NULL;
-+		}
-+	}
-+
-+	node = root->rnode;
-+	height = root->height;
-+	shift = (height - 1) * root->shift;
-+
-+	do {
-+		offset = (index >> shift) & root->mask;
-+		if (!node->stores[offset]) {
-+			if (!(tmp = root->alloc()))
-+				return NULL;
-+
-+			tmp->height = shift / root->shift;
-+			node->stores[offset] = tmp;
-+			tmp->parent = node;
-+			node->count++;
-+			node = tmp;
-+		} else {
-+			node = node->stores[offset];
-+		}
-+
-+		shift -= root->shift;
-+	} while (shift > 0);
-+
-+	BUG_ON(node->height != 1);
-+	offset = index & root->mask;
-+	if (node->stores[offset]) {
-+		return node->stores[offset];
-+	} else if (item_alloc) {
-+		if (!(item = item_alloc()))
-+			return NULL;
-+
-+		node->stores[offset] = item;
-+
-+		/*
-+		 * NOTE: we do NOT call root->assign here, since this item is
-+		 * newly created by us having no meaning. Caller can call this
-+		 * if it's necessary to do so.
-+		 */
-+
-+		node->count++;
-+		root->num++;
-+
-+		while (sradix_node_full(root, node)) {
-+			node = node->parent;
-+			if (!node)
-+				break;
-+
-+			node->fulls++;
-+		}
-+
-+		if (unlikely(!node)) {
-+			/* All nodes are full */
-+			root->min = 1 << (root->height * root->shift);
-+		} else {
-+			if (root->min == index) {
-+				root->min |= (1UL << (node->height - 1)) - 1;
-+				root->min++;
-+				root->enter_node = node;
-+			}
-+		}
-+
-+		return item;
-+	} else {
-+		return NULL;
-+	}
-+
-+}
-+
-+int sradix_tree_delete(struct sradix_tree_root *root, unsigned long index)
-+{
-+	unsigned int height, offset;
-+	struct sradix_tree_node *node;
-+	int shift;
-+
-+	node = root->rnode;
-+	if (node == NULL || (index >> (root->shift * root->height)))
-+		return -ENOENT;
-+
-+	height = root->height;
-+	shift = (height - 1) * root->shift;
-+
-+	do {
-+		offset = (index >> shift) & root->mask;
-+		node = node->stores[offset];
-+		if (!node)
-+			return -ENOENT;
-+
-+		shift -= root->shift;
-+	} while (shift > 0);
-+
-+	offset = index & root->mask;
-+	if (!node->stores[offset])
-+		return -ENOENT;
-+
-+	sradix_tree_delete_from_leaf(root, node, index);
-+
-+	return 0;
-+}
-diff --git a/mm/Kconfig b/mm/Kconfig
-index 034d87953..72feea3f0 100644
---- a/mm/Kconfig
-+++ b/mm/Kconfig
-@@ -310,6 +310,32 @@ config KSM
- 	  See Documentation/vm/ksm.rst for more information: KSM is inactive
- 	  until a program has madvised that an area is MADV_MERGEABLE, and
- 	  root has set /sys/kernel/mm/ksm/run to 1 (if CONFIG_SYSFS is set).
-+choice
-+	prompt "Choose UKSM/KSM strategy"
-+	default UKSM
-+	depends on KSM
-+	help
-+	  This option allows to select a UKSM/KSM stragety.
-+
-+config UKSM
-+	bool "Ultra-KSM for page merging"
-+	depends on KSM
-+	help
-+	UKSM is inspired by the Linux kernel project \u2014 KSM(Kernel Same
-+	page Merging), but with a fundamentally rewritten core algorithm. With
-+	an advanced algorithm, UKSM now can transparently scans all anonymously
-+	mapped user space applications with an significantly improved scan speed
-+	and CPU efficiency. Since KVM is friendly to KSM, KVM can also benefit from
-+	UKSM. Now UKSM has its first stable release and first real world enterprise user.
-+	For more information, please goto its project page.
-+	(github.com/dolohow/uksm)
-+
-+config KSM_LEGACY
-+	bool "Legacy KSM implementation"
-+	depends on KSM
-+	help
-+	The legacy KSM implementation from Red Hat.
-+endchoice
- 
- config DEFAULT_MMAP_MIN_ADDR
- 	int "Low address space to protect from user allocation"
-diff --git a/mm/Makefile b/mm/Makefile
-index 4cc13f317..a551ae513 100644
---- a/mm/Makefile
-+++ b/mm/Makefile
-@@ -83,7 +83,8 @@ obj-$(CONFIG_SPARSEMEM)	+= sparse.o
- obj-$(CONFIG_SPARSEMEM_VMEMMAP) += sparse-vmemmap.o
- obj-$(CONFIG_SLOB) += slob.o
- obj-$(CONFIG_MMU_NOTIFIER) += mmu_notifier.o
--obj-$(CONFIG_KSM) += ksm.o
-+obj-$(CONFIG_KSM_LEGACY) += ksm.o
-+obj-$(CONFIG_UKSM) += uksm.o
- obj-$(CONFIG_PAGE_POISONING) += page_poison.o
- obj-$(CONFIG_SLAB) += slab.o
- obj-$(CONFIG_SLUB) += slub.o
-diff --git a/mm/ksm.c b/mm/ksm.c
-index 063a48eeb..46fa39d0b 100644
---- a/mm/ksm.c
-+++ b/mm/ksm.c
-@@ -858,17 +858,6 @@ static inline struct stable_node *folio_stable_node(struct folio *folio)
- 	return folio_test_ksm(folio) ? folio_raw_mapping(folio) : NULL;
- }
- 
--static inline struct stable_node *page_stable_node(struct page *page)
--{
--	return folio_stable_node(page_folio(page));
--}
--
--static inline void set_page_stable_node(struct page *page,
--					struct stable_node *stable_node)
--{
--	page->mapping = (void *)((unsigned long)stable_node | PAGE_MAPPING_KSM);
--}
--
- #ifdef CONFIG_SYSFS
- /*
-  * Only called through the sysfs control interface:
-diff --git a/mm/memory.c b/mm/memory.c
-index 76e3af963..bb077166e 100644
---- a/mm/memory.c
-+++ b/mm/memory.c
-@@ -158,6 +158,25 @@ EXPORT_SYMBOL(zero_pfn);
- 
- unsigned long highest_memmap_pfn __read_mostly;
- 
-+#ifdef CONFIG_UKSM
-+unsigned long uksm_zero_pfn __read_mostly;
-+EXPORT_SYMBOL_GPL(uksm_zero_pfn);
-+struct page *empty_uksm_zero_page;
-+
-+static int __init setup_uksm_zero_page(void)
-+{
-+	empty_uksm_zero_page = alloc_pages(__GFP_ZERO & ~__GFP_MOVABLE, 0);
-+	if (!empty_uksm_zero_page)
-+		panic("Oh boy, that early out of memory?");
-+
-+	SetPageReserved(empty_uksm_zero_page);
-+	uksm_zero_pfn = page_to_pfn(empty_uksm_zero_page);
-+
-+	return 0;
-+}
-+core_initcall(setup_uksm_zero_page);
-+#endif
-+
- /*
-  * CONFIG_MMU architectures set up ZERO_PAGE in their paging_init()
-  */
-@@ -173,6 +192,7 @@ void mm_trace_rss_stat(struct mm_struct *mm, int member, long count)
- 	trace_rss_stat(mm, member, count);
- }
- 
-+
- #if defined(SPLIT_RSS_COUNTING)
- 
- void sync_mm_rss(struct mm_struct *mm)
-@@ -955,6 +975,11 @@ copy_present_pte(struct vm_area_struct *dst_vma, struct vm_area_struct *src_vma,
- 		get_page(page);
- 		page_dup_rmap(page, false);
- 		rss[mm_counter(page)]++;
-+
-+		/* Should return NULL in vm_normal_page() */
-+		uksm_bugon_zeropage(pte);
-+	} else {
-+		uksm_map_zero_page(pte);
- 	}
- 
- 	/*
-@@ -1373,8 +1398,10 @@ static unsigned long zap_pte_range(struct mmu_gather *tlb,
- 			ptent = ptep_get_and_clear_full(mm, addr, pte,
- 							tlb->fullmm);
- 			tlb_remove_tlb_entry(tlb, pte, addr);
--			if (unlikely(!page))
-+			if (unlikely(!page)) {
-+				uksm_unmap_zero_page(ptent);
- 				continue;
-+			}
- 
- 			if (!PageAnon(page)) {
- 				if (pte_dirty(ptent)) {
-@@ -2768,6 +2795,7 @@ static inline bool cow_user_page(struct page *dst, struct page *src,
- 
- 	if (likely(src)) {
- 		copy_user_highpage(dst, src, addr, vma);
-+		uksm_cow_page(vma, src);
- 		return true;
- 	}
- 
-@@ -3014,6 +3042,7 @@ static vm_fault_t wp_page_copy(struct vm_fault *vmf)
- 							      vmf->address);
- 		if (!new_page)
- 			goto oom;
-+		uksm_cow_pte(vma, vmf->orig_pte);
- 	} else {
- 		new_page = alloc_page_vma(GFP_HIGHUSER_MOVABLE, vma,
- 				vmf->address);
-@@ -3056,7 +3085,9 @@ static vm_fault_t wp_page_copy(struct vm_fault *vmf)
- 						mm_counter_file(old_page));
- 				inc_mm_counter_fast(mm, MM_ANONPAGES);
- 			}
-+			uksm_bugon_zeropage(vmf->orig_pte);
- 		} else {
-+			uksm_unmap_zero_page(vmf->orig_pte);
- 			inc_mm_counter_fast(mm, MM_ANONPAGES);
- 		}
- 		flush_cache_page(vma, vmf->address, pte_pfn(vmf->orig_pte));
-diff --git a/mm/mmap.c b/mm/mmap.c
-index 313b57d55..031c500d5 100644
---- a/mm/mmap.c
-+++ b/mm/mmap.c
-@@ -47,6 +47,7 @@
- #include <linux/moduleparam.h>
- #include <linux/pkeys.h>
- #include <linux/oom.h>
-+#include <linux/ksm.h>
- #include <linux/sched/mm.h>
- 
- #include <linux/uaccess.h>
-@@ -186,6 +187,7 @@ static struct vm_area_struct *remove_vma(struct vm_area_struct *vma)
- 	if (vma->vm_file)
- 		fput(vma->vm_file);
- 	mpol_put(vma_policy(vma));
-+       uksm_remove_vma(vma);
- 	vm_area_free(vma);
- 	return next;
- }
-@@ -752,9 +754,16 @@ int __vma_adjust(struct vm_area_struct *vma, unsigned long start,
- 	long adjust_next = 0;
- 	int remove_next = 0;
- 
-+/*
-+ * to avoid deadlock, ksm_remove_vma must be done before any spin_lock is
-+ * acquired
-+ */
-+	uksm_remove_vma(vma);
-+
- 	if (next && !insert) {
- 		struct vm_area_struct *exporter = NULL, *importer = NULL;
- 
-+		uksm_remove_vma(next);
- 		if (end >= next->vm_end) {
- 			/*
- 			 * vma expands, overlapping all the next, and
-@@ -885,6 +894,7 @@ int __vma_adjust(struct vm_area_struct *vma, unsigned long start,
- 		end_changed = true;
- 	}
- 	vma->vm_pgoff = pgoff;
-+
- 	if (adjust_next) {
- 		next->vm_start += adjust_next;
- 		next->vm_pgoff += adjust_next >> PAGE_SHIFT;
-@@ -989,6 +999,7 @@ int __vma_adjust(struct vm_area_struct *vma, unsigned long start,
- 		if (remove_next == 2) {
- 			remove_next = 1;
- 			end = next->vm_end;
-+			uksm_remove_vma(next);
- 			goto again;
- 		}
- 		else if (next)
-@@ -1015,10 +1026,14 @@ int __vma_adjust(struct vm_area_struct *vma, unsigned long start,
- 			 */
- 			VM_WARN_ON(mm->highest_vm_end != vm_end_gap(vma));
- 		}
-+	} else {
-+		if (next && !insert)
-+			uksm_vma_add_new(next);
- 	}
- 	if (insert && file)
- 		uprobe_mmap(insert);
- 
-+	uksm_vma_add_new(vma);
- 	validate_mm(mm);
- 
- 	return 0;
-@@ -1477,6 +1492,9 @@ unsigned long do_mmap(struct file *file, unsigned long addr,
- 	vm_flags = calc_vm_prot_bits(prot, pkey) | calc_vm_flag_bits(flags) |
- 			mm->def_flags | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC;
- 
-+	/* If uksm is enabled, we add VM_MERGEABLE to new VMAs. */
-+	uksm_vm_flags_mod(&vm_flags);
-+
- 	if (flags & MAP_LOCKED)
- 		if (!can_do_mlock())
- 			return -EPERM;
-@@ -1847,6 +1865,7 @@ unsigned long mmap_region(struct file *file, unsigned long addr,
- 	if (file && vm_flags & VM_SHARED)
- 		mapping_unmap_writable(file->f_mapping);
- 	file = vma->vm_file;
-+	uksm_vma_add_new(vma);
- out:
- 	perf_event_mmap(vma);
- 
-@@ -1886,6 +1905,7 @@ unsigned long mmap_region(struct file *file, unsigned long addr,
- 	if (vm_flags & VM_SHARED)
- 		mapping_unmap_writable(file->f_mapping);
- free_vma:
-+	uksm_remove_vma(vma);
- 	vm_area_free(vma);
- unacct_error:
- 	if (charged)
-@@ -2740,6 +2760,8 @@ int __split_vma(struct mm_struct *mm, struct vm_area_struct *vma,
- 	else
- 		err = vma_adjust(vma, vma->vm_start, addr, vma->vm_pgoff, new);
- 
-+	uksm_vma_add_new(new);
-+
- 	/* Success. */
- 	if (!err)
- 		return 0;
-@@ -3007,6 +3029,7 @@ static int do_brk_flags(unsigned long addr, unsigned long len, unsigned long fla
- 	if ((flags & (~VM_EXEC)) != 0)
- 		return -EINVAL;
- 	flags |= VM_DATA_DEFAULT_FLAGS | VM_ACCOUNT | mm->def_flags;
-+	uksm_vm_flags_mod(&flags);
- 
- 	mapped_addr = get_unmapped_area(NULL, addr, len, 0, MAP_FIXED);
- 	if (IS_ERR_VALUE(mapped_addr))
-@@ -3052,6 +3075,7 @@ static int do_brk_flags(unsigned long addr, unsigned long len, unsigned long fla
- 	vma->vm_flags = flags;
- 	vma->vm_page_prot = vm_get_page_prot(flags);
- 	vma_link(mm, vma, prev, rb_link, rb_parent);
-+	uksm_vma_add_new(vma);
- out:
- 	perf_event_mmap(vma);
- 	mm->total_vm += len >> PAGE_SHIFT;
-@@ -3149,6 +3173,8 @@ void exit_mmap(struct mm_struct *mm)
- 		cond_resched();
- 	}
- 	mm->mmap = NULL;
-+	mm->mm_rb = RB_ROOT;
-+	vmacache_invalidate(mm);
- 	mmap_write_unlock(mm);
- 	vm_unacct_memory(nr_accounted);
- }
-@@ -3258,6 +3284,7 @@ struct vm_area_struct *copy_vma(struct vm_area_struct **vmap,
- 			new_vma->vm_ops->open(new_vma);
- 		vma_link(mm, new_vma, prev, rb_link, rb_parent);
- 		*need_rmap_locks = false;
-+		uksm_vma_add_new(new_vma);
- 	}
- 	return new_vma;
- 
-@@ -3423,6 +3450,7 @@ static struct vm_area_struct *__install_special_mapping(
- 	vm_stat_account(mm, vma->vm_flags, len >> PAGE_SHIFT);
- 
- 	perf_event_mmap(vma);
-+	uksm_vma_add_new(vma);
- 
- 	return vma;
- 
-diff --git a/mm/uksm.c b/mm/uksm.c
-new file mode 100644
-index 000000000..a9618dca3
---- /dev/null
-+++ b/mm/uksm.c
-@@ -0,0 +1,5607 @@
-+/*
-+ * Ultra KSM. Copyright (C) 2011-2012 Nai Xia
-+ *
-+ * This is an improvement upon KSM. Some basic data structures and routines
-+ * are borrowed from ksm.c .
-+ *
-+ * Its new features:
-+ * 1. Full system scan:
-+ *      It automatically scans all user processes' anonymous VMAs. Kernel-user
-+ *      interaction to submit a memory area to KSM is no longer needed.
-+ *
-+ * 2. Rich area detection:
-+ *      It automatically detects rich areas containing abundant duplicated
-+ *      pages based. Rich areas are given a full scan speed. Poor areas are
-+ *      sampled at a reasonable speed with very low CPU consumption.
-+ *
-+ * 3. Ultra Per-page scan speed improvement:
-+ *      A new hash algorithm is proposed. As a result, on a machine with
-+ *      Core(TM)2 Quad Q9300 CPU in 32-bit mode and 800MHZ DDR2 main memory, it
-+ *      can scan memory areas that does not contain duplicated pages at speed of
-+ *      627MB/sec ~ 2445MB/sec and can merge duplicated areas at speed of
-+ *      477MB/sec ~ 923MB/sec.
-+ *
-+ * 4. Thrashing area avoidance:
-+ *      Thrashing area(an VMA that has frequent Ksm page break-out) can be
-+ *      filtered out. My benchmark shows it's more efficient than KSM's per-page
-+ *      hash value based volatile page detection.
-+ *
-+ *
-+ * 5. Misc changes upon KSM:
-+ *      * It has a fully x86-opitmized memcmp dedicated for 4-byte-aligned page
-+ *        comparison. It's much faster than default C version on x86.
-+ *      * rmap_item now has an struct *page member to loosely cache a
-+ *        address-->page mapping, which reduces too much time-costly
-+ *        follow_page().
-+ *      * The VMA creation/exit procedures are hooked to let the Ultra KSM know.
-+ *      * try_to_merge_two_pages() now can revert a pte if it fails. No break_
-+ *        ksm is needed for this case.
-+ *
-+ * 6. Full Zero Page consideration(contributed by Figo Zhang)
-+ *    Now uksmd consider full zero pages as special pages and merge them to an
-+ *    special unswappable uksm zero page.
-+ */
-+
-+#include <linux/errno.h>
-+#include <linux/mm.h>
-+#include <linux/fs.h>
-+#include <linux/mman.h>
-+#include <linux/sched.h>
-+#include <linux/sched/mm.h>
-+#include <linux/sched/coredump.h>
-+#include <linux/sched/cputime.h>
-+#include <linux/rwsem.h>
-+#include <linux/pagemap.h>
-+#include <linux/rmap.h>
-+#include <linux/spinlock.h>
-+#include <linux/jhash.h>
-+#include <linux/delay.h>
-+#include <linux/kthread.h>
-+#include <linux/wait.h>
-+#include <linux/slab.h>
-+#include <linux/rbtree.h>
-+#include <linux/memory.h>
-+#include <linux/mmu_notifier.h>
-+#include <linux/mm_inline.h>
-+#include <linux/swap.h>
-+#include <linux/ksm.h>
-+#include <linux/crypto.h>
-+#include <linux/scatterlist.h>
-+#include <crypto/hash.h>
-+#include <linux/random.h>
-+#include <linux/math64.h>
-+#include <linux/gcd.h>
-+#include <linux/freezer.h>
-+#include <linux/oom.h>
-+#include <linux/numa.h>
-+#include <linux/sradix-tree.h>
-+
-+#include <asm/tlbflush.h>
-+#include "internal.h"
-+
-+#ifdef CONFIG_X86
-+#undef memcmp
-+
-+#ifdef CONFIG_X86_32
-+#define memcmp memcmpx86_32
-+/*
-+ * Compare 4-byte-aligned address s1 and s2, with length n
-+ */
-+int memcmpx86_32(void *s1, void *s2, size_t n)
-+{
-+	size_t num = n / 4;
-+	register int res;
-+
-+	__asm__ __volatile__
-+	(
-+	 "testl %3,%3\n\t"
-+	 "repe; cmpsd\n\t"
-+	 "je        1f\n\t"
-+	 "sbbl      %0,%0\n\t"
-+	 "orl       $1,%0\n"
-+	 "1:"
-+	 : "=&a" (res), "+&S" (s1), "+&D" (s2), "+&c" (num)
-+	 : "0" (0)
-+	 : "cc");
-+
-+	return res;
-+}
-+
-+/*
-+ * Check the page is all zero ?
-+ */
-+static int is_full_zero(const void *s1, size_t len)
-+{
-+	unsigned char same;
-+
-+	len /= 4;
-+
-+	__asm__ __volatile__
-+	("repe; scasl;"
-+	 "sete %0"
-+	 : "=qm" (same), "+D" (s1), "+c" (len)
-+	 : "a" (0)
-+	 : "cc");
-+
-+	return same;
-+}
-+
-+
-+#elif defined(CONFIG_X86_64)
-+#define memcmp memcmpx86_64
-+/*
-+ * Compare 8-byte-aligned address s1 and s2, with length n
-+ */
-+int memcmpx86_64(void *s1, void *s2, size_t n)
-+{
-+	size_t num = n / 8;
-+	register int res;
-+
-+	__asm__ __volatile__
-+	(
-+	 "testq %q3,%q3\n\t"
-+	 "repe; cmpsq\n\t"
-+	 "je        1f\n\t"
-+	 "sbbq      %q0,%q0\n\t"
-+	 "orq       $1,%q0\n"
-+	 "1:"
-+	 : "=&a" (res), "+&S" (s1), "+&D" (s2), "+&c" (num)
-+	 : "0" (0)
-+	 : "cc");
-+
-+	return res;
-+}
-+
-+static int is_full_zero(const void *s1, size_t len)
-+{
-+	unsigned char same;
-+
-+	len /= 8;
-+
-+	__asm__ __volatile__
-+	("repe; scasq;"
-+	 "sete %0"
-+	 : "=qm" (same), "+D" (s1), "+c" (len)
-+	 : "a" (0)
-+	 : "cc");
-+
-+	return same;
-+}
-+
-+#endif
-+#else
-+static int is_full_zero(const void *s1, size_t len)
-+{
-+	unsigned long *src = s1;
-+	int i;
-+
-+	len /= sizeof(*src);
-+
-+	for (i = 0; i < len; i++) {
-+		if (src[i])
-+			return 0;
-+	}
-+
-+	return 1;
-+}
-+#endif
-+
-+#define UKSM_RUNG_ROUND_FINISHED  (1 << 0)
-+#define TIME_RATIO_SCALE	10000
-+
-+#define SLOT_TREE_NODE_SHIFT	8
-+#define SLOT_TREE_NODE_STORE_SIZE	(1UL << SLOT_TREE_NODE_SHIFT)
-+struct slot_tree_node {
-+	unsigned long size;
-+	struct sradix_tree_node snode;
-+	void *stores[SLOT_TREE_NODE_STORE_SIZE];
-+};
-+
-+static struct kmem_cache *slot_tree_node_cachep;
-+
-+static struct sradix_tree_node *slot_tree_node_alloc(void)
-+{
-+	struct slot_tree_node *p;
-+
-+	p = kmem_cache_zalloc(slot_tree_node_cachep, GFP_KERNEL |
-+			      __GFP_NORETRY | __GFP_NOWARN);
-+	if (!p)
-+		return NULL;
-+
-+	return &p->snode;
-+}
-+
-+static void slot_tree_node_free(struct sradix_tree_node *node)
-+{
-+	struct slot_tree_node *p;
-+
-+	p = container_of(node, struct slot_tree_node, snode);
-+	kmem_cache_free(slot_tree_node_cachep, p);
-+}
-+
-+static void slot_tree_node_extend(struct sradix_tree_node *parent,
-+				  struct sradix_tree_node *child)
-+{
-+	struct slot_tree_node *p, *c;
-+
-+	p = container_of(parent, struct slot_tree_node, snode);
-+	c = container_of(child, struct slot_tree_node, snode);
-+
-+	p->size += c->size;
-+}
-+
-+void slot_tree_node_assign(struct sradix_tree_node *node,
-+			   unsigned int index, void *item)
-+{
-+	struct vma_slot *slot = item;
-+	struct slot_tree_node *cur;
-+
-+	slot->snode = node;
-+	slot->sindex = index;
-+
-+	while (node) {
-+		cur = container_of(node, struct slot_tree_node, snode);
-+		cur->size += slot->pages;
-+		node = node->parent;
-+	}
-+}
-+
-+void slot_tree_node_rm(struct sradix_tree_node *node, unsigned int offset)
-+{
-+	struct vma_slot *slot;
-+	struct slot_tree_node *cur;
-+	unsigned long pages;
-+
-+	if (node->height == 1) {
-+		slot = node->stores[offset];
-+		pages = slot->pages;
-+	} else {
-+		cur = container_of(node->stores[offset],
-+				   struct slot_tree_node, snode);
-+		pages = cur->size;
-+	}
-+
-+	while (node) {
-+		cur = container_of(node, struct slot_tree_node, snode);
-+		cur->size -= pages;
-+		node = node->parent;
-+	}
-+}
-+
-+unsigned long slot_iter_index;
-+int slot_iter(void *item,  unsigned long height)
-+{
-+	struct slot_tree_node *node;
-+	struct vma_slot *slot;
-+
-+	if (height == 1) {
-+		slot = item;
-+		if (slot_iter_index < slot->pages) {
-+			/*in this one*/
-+			return 1;
-+		} else {
-+			slot_iter_index -= slot->pages;
-+			return 0;
-+		}
-+
-+	} else {
-+		node = container_of(item, struct slot_tree_node, snode);
-+		if (slot_iter_index < node->size) {
-+			/*in this one*/
-+			return 1;
-+		} else {
-+			slot_iter_index -= node->size;
-+			return 0;
-+		}
-+	}
-+}
-+
-+
-+static inline void slot_tree_init_root(struct sradix_tree_root *root)
-+{
-+	init_sradix_tree_root(root, SLOT_TREE_NODE_SHIFT);
-+	root->alloc = slot_tree_node_alloc;
-+	root->free = slot_tree_node_free;
-+	root->extend = slot_tree_node_extend;
-+	root->assign = slot_tree_node_assign;
-+	root->rm = slot_tree_node_rm;
-+}
-+
-+void slot_tree_init(void)
-+{
-+	slot_tree_node_cachep = kmem_cache_create("slot_tree_node",
-+				sizeof(struct slot_tree_node), 0,
-+				SLAB_PANIC | SLAB_RECLAIM_ACCOUNT,
-+				NULL);
-+}
-+
-+
-+/* Each rung of this ladder is a list of VMAs having a same scan ratio */
-+struct scan_rung {
-+	//struct list_head scanned_list;
-+	struct sradix_tree_root vma_root;
-+	struct sradix_tree_root vma_root2;
-+
-+	struct vma_slot *current_scan;
-+	unsigned long current_offset;
-+
-+	/*
-+	 * The initial value for current_offset, it should loop over
-+	 * [0~ step - 1] to let all slot have its chance to be scanned.
-+	 */
-+	unsigned long offset_init;
-+	unsigned long step; /* dynamic step for current_offset */
-+	unsigned int flags;
-+	unsigned long pages_to_scan;
-+	//unsigned long fully_scanned_slots;
-+	/*
-+	 * a little bit tricky - if cpu_time_ratio > 0, then the value is the
-+	 * the cpu time ratio it can spend in rung_i for every scan
-+	 * period. if < 0, then it is the cpu time ratio relative to the
-+	 * max cpu percentage user specified. Both in unit of
-+	 * 1/TIME_RATIO_SCALE
-+	 */
-+	int cpu_ratio;
-+
-+	/*
-+	 * How long it will take for all slots in this rung to be fully
-+	 * scanned? If it's zero, we don't care about the cover time:
-+	 * it's fully scanned.
-+	 */
-+	unsigned int cover_msecs;
-+	//unsigned long vma_num;
-+	//unsigned long pages; /* Sum of all slot's pages in rung */
-+};
-+
-+/**
-+ * node of either the stable or unstale rbtree
-+ *
-+ */
-+struct tree_node {
-+	struct rb_node node; /* link in the main (un)stable rbtree */
-+	struct rb_root sub_root; /* rb_root for sublevel collision rbtree */
-+	u32 hash;
-+	unsigned long count; /* TODO: merged with sub_root */
-+	struct list_head all_list; /* all tree nodes in stable/unstable tree */
-+};
-+
-+/**
-+ * struct stable_node - node of the stable rbtree
-+ * @node: rb node of this ksm page in the stable tree
-+ * @hlist: hlist head of rmap_items using this ksm page
-+ * @kpfn: page frame number of this ksm page
-+ */
-+struct stable_node {
-+	struct rb_node node; /* link in sub-rbtree */
-+	struct tree_node *tree_node; /* it's tree node root in stable tree, NULL if it's in hell list */
-+	struct hlist_head hlist;
-+	unsigned long kpfn;
-+	u32 hash_max; /* if ==0 then it's not been calculated yet */
-+	struct list_head all_list; /* in a list for all stable nodes */
-+};
-+
-+/**
-+ * struct node_vma - group rmap_items linked in a same stable
-+ * node together.
-+ */
-+struct node_vma {
-+	union {
-+		struct vma_slot *slot;
-+		unsigned long key;  /* slot is used as key sorted on hlist */
-+	};
-+	struct hlist_node hlist;
-+	struct hlist_head rmap_hlist;
-+	struct stable_node *head;
-+};
-+
-+/**
-+ * struct rmap_item - reverse mapping item for virtual addresses
-+ * @rmap_list: next rmap_item in mm_slot's singly-linked rmap_list
-+ * @anon_vma: pointer to anon_vma for this mm,address, when in stable tree
-+ * @mm: the memory structure this rmap_item is pointing into
-+ * @address: the virtual address this rmap_item tracks (+ flags in low bits)
-+ * @node: rb node of this rmap_item in the unstable tree
-+ * @head: pointer to stable_node heading this list in the stable tree
-+ * @hlist: link into hlist of rmap_items hanging off that stable_node
-+ */
-+struct rmap_item {
-+	struct vma_slot *slot;
-+	struct page *page;
-+	unsigned long address;	/* + low bits used for flags below */
-+	unsigned long hash_round;
-+	unsigned long entry_index;
-+	union {
-+		struct {/* when in unstable tree */
-+			struct rb_node node;
-+			struct tree_node *tree_node;
-+			u32 hash_max;
-+		};
-+		struct { /* when in stable tree */
-+			struct node_vma *head;
-+			struct hlist_node hlist;
-+			struct anon_vma *anon_vma;
-+		};
-+	};
-+} __aligned(4);
-+
-+struct rmap_list_entry {
-+	union {
-+		struct rmap_item *item;
-+		unsigned long addr;
-+	};
-+	/* lowest bit is used for is_addr tag */
-+} __aligned(4); /* 4 aligned to fit in to pages*/
-+
-+
-+/* Basic data structure definition ends */
-+
-+
-+/*
-+ * Flags for rmap_item to judge if it's listed in the stable/unstable tree.
-+ * The flags use the low bits of rmap_item.address
-+ */
-+#define UNSTABLE_FLAG	0x1
-+#define STABLE_FLAG	0x2
-+#define get_rmap_addr(x)	((x)->address & PAGE_MASK)
-+
-+/*
-+ * rmap_list_entry helpers
-+ */
-+#define IS_ADDR_FLAG	1
-+#define is_addr(ptr)		((unsigned long)(ptr) & IS_ADDR_FLAG)
-+#define set_is_addr(ptr)	((ptr) |= IS_ADDR_FLAG)
-+#define get_clean_addr(ptr)	(((ptr) & ~(__typeof__(ptr))IS_ADDR_FLAG))
-+
-+
-+/*
-+ * High speed caches for frequently allocated and freed structs
-+ */
-+static struct kmem_cache *rmap_item_cache;
-+static struct kmem_cache *stable_node_cache;
-+static struct kmem_cache *node_vma_cache;
-+static struct kmem_cache *vma_slot_cache;
-+static struct kmem_cache *tree_node_cache;
-+#define UKSM_KMEM_CACHE(__struct, __flags) kmem_cache_create("uksm_"#__struct,\
-+		sizeof(struct __struct), __alignof__(struct __struct),\
-+		(__flags), NULL)
-+
-+/* Array of all scan_rung, uksm_scan_ladder[0] having the minimum scan ratio */
-+#define SCAN_LADDER_SIZE 4
-+static struct scan_rung uksm_scan_ladder[SCAN_LADDER_SIZE];
-+
-+/* The evaluation rounds uksmd has finished */
-+static unsigned long long uksm_eval_round = 1;
-+
-+/*
-+ * we add 1 to this var when we consider we should rebuild the whole
-+ * unstable tree.
-+ */
-+static unsigned long uksm_hash_round = 1;
-+
-+/*
-+ * How many times the whole memory is scanned.
-+ */
-+static unsigned long long fully_scanned_round = 1;
-+
-+/* The total number of virtual pages of all vma slots */
-+static u64 uksm_pages_total;
-+
-+/* The number of pages has been scanned since the start up */
-+static u64 uksm_pages_scanned;
-+
-+static u64 scanned_virtual_pages;
-+
-+/* The number of pages has been scanned since last encode_benefit call */
-+static u64 uksm_pages_scanned_last;
-+
-+/* If the scanned number is tooo large, we encode it here */
-+static u64 pages_scanned_stored;
-+
-+static unsigned long pages_scanned_base;
-+
-+/* The number of nodes in the stable tree */
-+static unsigned long uksm_pages_shared;
-+
-+/* The number of page slots additionally sharing those nodes */
-+static unsigned long uksm_pages_sharing;
-+
-+/* The number of nodes in the unstable tree */
-+static unsigned long uksm_pages_unshared;
-+
-+/*
-+ * Milliseconds ksmd should sleep between scans,
-+ * >= 100ms to be consistent with
-+ * scan_time_to_sleep_msec()
-+ */
-+static unsigned int uksm_sleep_jiffies;
-+
-+/* The real value for the uksmd next sleep */
-+static unsigned int uksm_sleep_real;
-+
-+/* Saved value for user input uksm_sleep_jiffies when it's enlarged */
-+static unsigned int uksm_sleep_saved;
-+
-+/* Max percentage of cpu utilization ksmd can take to scan in one batch */
-+static unsigned int uksm_max_cpu_percentage;
-+
-+static int uksm_cpu_governor;
-+
-+static char *uksm_cpu_governor_str[4] = { "full", "medium", "low", "quiet" };
-+
-+struct uksm_cpu_preset_s {
-+	int cpu_ratio[SCAN_LADDER_SIZE];
-+	unsigned int cover_msecs[SCAN_LADDER_SIZE];
-+	unsigned int max_cpu; /* percentage */
-+};
-+
-+struct uksm_cpu_preset_s uksm_cpu_preset[4] = {
-+	{ {20, 40, -2500, -10000}, {1000, 500, 200, 50}, 95},
-+	{ {20, 30, -2500, -10000}, {1000, 500, 400, 100}, 50},
-+	{ {10, 20, -5000, -10000}, {1500, 1000, 1000, 250}, 20},
-+	{ {10, 20, 40, 75}, {2000, 1000, 1000, 1000}, 1},
-+};
-+
-+/* The default value for uksm_ema_page_time if it's not initialized */
-+#define UKSM_PAGE_TIME_DEFAULT	500
-+
-+/*cost to scan one page by expotional moving average in nsecs */
-+static unsigned long uksm_ema_page_time = UKSM_PAGE_TIME_DEFAULT;
-+
-+/* The expotional moving average alpha weight, in percentage. */
-+#define EMA_ALPHA	20
-+
-+/*
-+ * The threshold used to filter out thrashing areas,
-+ * If it == 0, filtering is disabled, otherwise it's the percentage up-bound
-+ * of the thrashing ratio of all areas. Any area with a bigger thrashing ratio
-+ * will be considered as having a zero duplication ratio.
-+ */
-+static unsigned int uksm_thrash_threshold = 50;
-+
-+/* How much dedup ratio is considered to be abundant*/
-+static unsigned int uksm_abundant_threshold = 10;
-+
-+/* All slots having merged pages in this eval round. */
-+struct list_head vma_slot_dedup = LIST_HEAD_INIT(vma_slot_dedup);
-+
-+/* How many times the ksmd has slept since startup */
-+static unsigned long long uksm_sleep_times;
-+
-+#define UKSM_RUN_STOP	0
-+#define UKSM_RUN_MERGE	1
-+static unsigned int uksm_run = 1;
-+
-+static DECLARE_WAIT_QUEUE_HEAD(uksm_thread_wait);
-+static DEFINE_MUTEX(uksm_thread_mutex);
-+
-+/*
-+ * List vma_slot_new is for newly created vma_slot waiting to be added by
-+ * ksmd. If one cannot be added(e.g. due to it's too small), it's moved to
-+ * vma_slot_noadd. vma_slot_del is the list for vma_slot whose corresponding
-+ * VMA has been removed/freed.
-+ */
-+struct list_head vma_slot_new = LIST_HEAD_INIT(vma_slot_new);
-+struct list_head vma_slot_noadd = LIST_HEAD_INIT(vma_slot_noadd);
-+struct list_head vma_slot_del = LIST_HEAD_INIT(vma_slot_del);
-+static DEFINE_SPINLOCK(vma_slot_list_lock);
-+
-+/* The unstable tree heads */
-+static struct rb_root root_unstable_tree = RB_ROOT;
-+
-+/*
-+ * All tree_nodes are in a list to be freed at once when unstable tree is
-+ * freed after each scan round.
-+ */
-+static struct list_head unstable_tree_node_list =
-+				LIST_HEAD_INIT(unstable_tree_node_list);
-+
-+/* List contains all stable nodes */
-+static struct list_head stable_node_list = LIST_HEAD_INIT(stable_node_list);
-+
-+/*
-+ * When the hash strength is changed, the stable tree must be delta_hashed and
-+ * re-structured. We use two set of below structs to speed up the
-+ * re-structuring of stable tree.
-+ */
-+static struct list_head
-+stable_tree_node_list[2] = {LIST_HEAD_INIT(stable_tree_node_list[0]),
-+			    LIST_HEAD_INIT(stable_tree_node_list[1])};
-+
-+static struct list_head *stable_tree_node_listp = &stable_tree_node_list[0];
-+static struct rb_root root_stable_tree[2] = {RB_ROOT, RB_ROOT};
-+static struct rb_root *root_stable_treep = &root_stable_tree[0];
-+static unsigned long stable_tree_index;
-+
-+/* The hash strength needed to hash a full page */
-+#define HASH_STRENGTH_FULL		(PAGE_SIZE / sizeof(u32))
-+
-+/* The hash strength needed for loop-back hashing */
-+#define HASH_STRENGTH_MAX		(HASH_STRENGTH_FULL + 10)
-+
-+/* The random offsets in a page */
-+static u32 *random_nums;
-+
-+/* The hash strength */
-+static unsigned long hash_strength = HASH_STRENGTH_FULL >> 4;
-+
-+/* The delta value each time the hash strength increases or decreases */
-+static unsigned long hash_strength_delta;
-+#define HASH_STRENGTH_DELTA_MAX	5
-+
-+/* The time we have saved due to random_sample_hash */
-+static u64 rshash_pos;
-+
-+/* The time we have wasted due to hash collision */
-+static u64 rshash_neg;
-+
-+struct uksm_benefit {
-+	u64 pos;
-+	u64 neg;
-+	u64 scanned;
-+	unsigned long base;
-+} benefit;
-+
-+/*
-+ * The relative cost of memcmp, compared to 1 time unit of random sample
-+ * hash, this value is tested when ksm module is initialized
-+ */
-+static unsigned long memcmp_cost;
-+
-+static unsigned long  rshash_neg_cont_zero;
-+static unsigned long  rshash_cont_obscure;
-+
-+/* The possible states of hash strength adjustment heuristic */
-+enum rshash_states {
-+		RSHASH_STILL,
-+		RSHASH_TRYUP,
-+		RSHASH_TRYDOWN,
-+		RSHASH_NEW,
-+		RSHASH_PRE_STILL,
-+};
-+
-+/* The possible direction we are about to adjust hash strength */
-+enum rshash_direct {
-+	GO_UP,
-+	GO_DOWN,
-+	OBSCURE,
-+	STILL,
-+};
-+
-+/* random sampling hash state machine */
-+static struct {
-+	enum rshash_states state;
-+	enum rshash_direct pre_direct;
-+	u8 below_count;
-+	/* Keep a lookup window of size 5, iff above_count/below_count > 3
-+	 * in this window we stop trying.
-+	 */
-+	u8 lookup_window_index;
-+	u64 stable_benefit;
-+	unsigned long turn_point_down;
-+	unsigned long turn_benefit_down;
-+	unsigned long turn_point_up;
-+	unsigned long turn_benefit_up;
-+	unsigned long stable_point;
-+} rshash_state;
-+
-+/*zero page hash table, hash_strength [0 ~ HASH_STRENGTH_MAX]*/
-+static u32 *zero_hash_table;
-+
-+static inline struct node_vma *alloc_node_vma(void)
-+{
-+	struct node_vma *node_vma;
-+
-+	node_vma = kmem_cache_zalloc(node_vma_cache, GFP_KERNEL |
-+				     __GFP_NORETRY | __GFP_NOWARN);
-+	if (node_vma) {
-+		INIT_HLIST_HEAD(&node_vma->rmap_hlist);
-+		INIT_HLIST_NODE(&node_vma->hlist);
-+	}
-+	return node_vma;
-+}
-+
-+static inline void free_node_vma(struct node_vma *node_vma)
-+{
-+	kmem_cache_free(node_vma_cache, node_vma);
-+}
-+
-+
-+static inline struct vma_slot *alloc_vma_slot(void)
-+{
-+	struct vma_slot *slot;
-+
-+	/*
-+	 * In case ksm is not initialized by now.
-+	 * Oops, we need to consider the call site of uksm_init() in the future.
-+	 */
-+	if (!vma_slot_cache)
-+		return NULL;
-+
-+	slot = kmem_cache_zalloc(vma_slot_cache, GFP_KERNEL |
-+				 __GFP_NORETRY | __GFP_NOWARN);
-+	if (slot) {
-+		INIT_LIST_HEAD(&slot->slot_list);
-+		INIT_LIST_HEAD(&slot->dedup_list);
-+		slot->flags |= UKSM_SLOT_NEED_RERAND;
-+	}
-+	return slot;
-+}
-+
-+static inline void free_vma_slot(struct vma_slot *vma_slot)
-+{
-+	kmem_cache_free(vma_slot_cache, vma_slot);
-+}
-+
-+
-+
-+static inline struct rmap_item *alloc_rmap_item(void)
-+{
-+	struct rmap_item *rmap_item;
-+
-+	rmap_item = kmem_cache_zalloc(rmap_item_cache, GFP_KERNEL |
-+				      __GFP_NORETRY | __GFP_NOWARN);
-+	if (rmap_item) {
-+		/* bug on lowest bit is not clear for flag use */
-+		BUG_ON(is_addr(rmap_item));
-+	}
-+	return rmap_item;
-+}
-+
-+static inline void free_rmap_item(struct rmap_item *rmap_item)
-+{
-+	rmap_item->slot = NULL;	/* debug safety */
-+	kmem_cache_free(rmap_item_cache, rmap_item);
-+}
-+
-+static inline struct stable_node *alloc_stable_node(void)
-+{
-+	struct stable_node *node;
-+
-+	node = kmem_cache_alloc(stable_node_cache, GFP_KERNEL |
-+				__GFP_NORETRY | __GFP_NOWARN);
-+	if (!node)
-+		return NULL;
-+
-+	INIT_HLIST_HEAD(&node->hlist);
-+	list_add(&node->all_list, &stable_node_list);
-+	return node;
-+}
-+
-+static inline void free_stable_node(struct stable_node *stable_node)
-+{
-+	list_del(&stable_node->all_list);
-+	kmem_cache_free(stable_node_cache, stable_node);
-+}
-+
-+static inline struct tree_node *alloc_tree_node(struct list_head *list)
-+{
-+	struct tree_node *node;
-+
-+	node = kmem_cache_zalloc(tree_node_cache, GFP_KERNEL |
-+				 __GFP_NORETRY | __GFP_NOWARN);
-+	if (!node)
-+		return NULL;
-+
-+	list_add(&node->all_list, list);
-+	return node;
-+}
-+
-+static inline void free_tree_node(struct tree_node *node)
-+{
-+	list_del(&node->all_list);
-+	kmem_cache_free(tree_node_cache, node);
-+}
-+
-+static void uksm_drop_anon_vma(struct rmap_item *rmap_item)
-+{
-+	struct anon_vma *anon_vma = rmap_item->anon_vma;
-+
-+	put_anon_vma(anon_vma);
-+}
-+
-+
-+/**
-+ * Remove a stable node from stable_tree, may unlink from its tree_node and
-+ * may remove its parent tree_node if no other stable node is pending.
-+ *
-+ * @stable_node	    The node need to be removed
-+ * @unlink_rb	    Will this node be unlinked from the rbtree?
-+ * @remove_tree_    node Will its tree_node be removed if empty?
-+ */
-+static void remove_node_from_stable_tree(struct stable_node *stable_node,
-+					 int unlink_rb,  int remove_tree_node)
-+{
-+	struct node_vma *node_vma;
-+	struct rmap_item *rmap_item;
-+	struct hlist_node *n;
-+
-+	if (!hlist_empty(&stable_node->hlist)) {
-+		hlist_for_each_entry_safe(node_vma, n,
-+					  &stable_node->hlist, hlist) {
-+			hlist_for_each_entry(rmap_item, &node_vma->rmap_hlist, hlist) {
-+				uksm_pages_sharing--;
-+
-+				uksm_drop_anon_vma(rmap_item);
-+				rmap_item->address &= PAGE_MASK;
-+			}
-+			free_node_vma(node_vma);
-+			cond_resched();
-+		}
-+
-+		/* the last one is counted as shared */
-+		uksm_pages_shared--;
-+		uksm_pages_sharing++;
-+	}
-+
-+	if (stable_node->tree_node && unlink_rb) {
-+		rb_erase(&stable_node->node,
-+			 &stable_node->tree_node->sub_root);
-+
-+		if (RB_EMPTY_ROOT(&stable_node->tree_node->sub_root) &&
-+		    remove_tree_node) {
-+			rb_erase(&stable_node->tree_node->node,
-+				 root_stable_treep);
-+			free_tree_node(stable_node->tree_node);
-+		} else {
-+			stable_node->tree_node->count--;
-+		}
-+	}
-+
-+	free_stable_node(stable_node);
-+}
-+
-+
-+/*
-+ * get_uksm_page: checks if the page indicated by the stable node
-+ * is still its ksm page, despite having held no reference to it.
-+ * In which case we can trust the content of the page, and it
-+ * returns the gotten page; but if the page has now been zapped,
-+ * remove the stale node from the stable tree and return NULL.
-+ *
-+ * You would expect the stable_node to hold a reference to the ksm page.
-+ * But if it increments the page's count, swapping out has to wait for
-+ * ksmd to come around again before it can free the page, which may take
-+ * seconds or even minutes: much too unresponsive.  So instead we use a
-+ * "keyhole reference": access to the ksm page from the stable node peeps
-+ * out through its keyhole to see if that page still holds the right key,
-+ * pointing back to this stable node.  This relies on freeing a PageAnon
-+ * page to reset its page->mapping to NULL, and relies on no other use of
-+ * a page to put something that might look like our key in page->mapping.
-+ *
-+ * include/linux/pagemap.h page_cache_get_speculative() is a good reference,
-+ * but this is different - made simpler by uksm_thread_mutex being held, but
-+ * interesting for assuming that no other use of the struct page could ever
-+ * put our expected_mapping into page->mapping (or a field of the union which
-+ * coincides with page->mapping).  The RCU calls are not for KSM at all, but
-+ * to keep the page_count protocol described with page_cache_get_speculative.
-+ *
-+ * Note: it is possible that get_uksm_page() will return NULL one moment,
-+ * then page the next, if the page is in between page_freeze_refs() and
-+ * page_unfreeze_refs(): this shouldn't be a problem anywhere, the page
-+ * is on its way to being freed; but it is an anomaly to bear in mind.
-+ *
-+ * @unlink_rb:			if the removal of this node will firstly unlink from
-+ * its rbtree. stable_node_reinsert will prevent this when restructuring the
-+ * node from its old tree.
-+ *
-+ * @remove_tree_node:	if this is the last one of its tree_node, will the
-+ * tree_node be freed ? If we are inserting stable node, this tree_node may
-+ * be reused, so don't free it.
-+ */
-+static struct page *get_uksm_page(struct stable_node *stable_node,
-+				 int unlink_rb, int remove_tree_node)
-+{
-+	struct page *page;
-+	void *expected_mapping;
-+	unsigned long kpfn;
-+
-+	expected_mapping = (void *)((unsigned long)stable_node |
-+				    PAGE_MAPPING_KSM);
-+again:
-+	kpfn = READ_ONCE(stable_node->kpfn);
-+	page = pfn_to_page(kpfn);
-+
-+	/*
-+	 * page is computed from kpfn, so on most architectures reading
-+	 * page->mapping is naturally ordered after reading node->kpfn,
-+	 * but on Alpha we need to be more careful.
-+	 */
-+	smp_rmb();
-+
-+	if (READ_ONCE(page->mapping) != expected_mapping)
-+		goto stale;
-+
-+	/*
-+	 * We cannot do anything with the page while its refcount is 0.
-+	 * Usually 0 means free, or tail of a higher-order page: in which
-+	 * case this node is no longer referenced, and should be freed;
-+	 * however, it might mean that the page is under page_freeze_refs().
-+	 * The __remove_mapping() case is easy, again the node is now stale;
-+	 * but if page is swapcache in migrate_page_move_mapping(), it might
-+	 * still be our page, in which case it's essential to keep the node.
-+	 */
-+	while (!get_page_unless_zero(page)) {
-+		/*
-+		 * Another check for page->mapping != expected_mapping would
-+		 * work here too.  We have chosen the !PageSwapCache test to
-+		 * optimize the common case, when the page is or is about to
-+		 * be freed: PageSwapCache is cleared (under spin_lock_irq)
-+		 * in the freeze_refs section of __remove_mapping(); but Anon
-+		 * page->mapping reset to NULL later, in free_pages_prepare().
-+		 */
-+		if (!PageSwapCache(page))
-+			goto stale;
-+		cpu_relax();
-+	}
-+
-+	if (READ_ONCE(page->mapping) != expected_mapping) {
-+		put_page(page);
-+		goto stale;
-+	}
-+
-+	lock_page(page);
-+	if (READ_ONCE(page->mapping) != expected_mapping) {
-+		unlock_page(page);
-+		put_page(page);
-+		goto stale;
-+	}
-+	unlock_page(page);
-+	return page;
-+stale:
-+	/*
-+	 * We come here from above when page->mapping or !PageSwapCache
-+	 * suggests that the node is stale; but it might be under migration.
-+	 * We need smp_rmb(), matching the smp_wmb() in folio_migrate_ksm(),
-+	 * before checking whether node->kpfn has been changed.
-+	 */
-+	smp_rmb();
-+	if (stable_node->kpfn != kpfn)
-+		goto again;
-+
-+	remove_node_from_stable_tree(stable_node, unlink_rb, remove_tree_node);
-+
-+	return NULL;
-+}
-+
-+/*
-+ * Removing rmap_item from stable or unstable tree.
-+ * This function will clean the information from the stable/unstable tree.
-+ */
-+static inline void remove_rmap_item_from_tree(struct rmap_item *rmap_item)
-+{
-+	if (rmap_item->address & STABLE_FLAG) {
-+		struct stable_node *stable_node;
-+		struct node_vma *node_vma;
-+		struct page *page;
-+
-+		node_vma = rmap_item->head;
-+		stable_node = node_vma->head;
-+		page = get_uksm_page(stable_node, 1, 1);
-+		if (!page)
-+			goto out;
-+
-+		/*
-+		 * page lock is needed because it's racing with
-+		 * try_to_unmap_ksm(), etc.
-+		 */
-+		lock_page(page);
-+		hlist_del(&rmap_item->hlist);
-+
-+		if (hlist_empty(&node_vma->rmap_hlist)) {
-+			hlist_del(&node_vma->hlist);
-+			free_node_vma(node_vma);
-+		}
-+		unlock_page(page);
-+
-+		put_page(page);
-+		if (hlist_empty(&stable_node->hlist)) {
-+			/* do NOT call remove_node_from_stable_tree() here,
-+			 * it's possible for a forked rmap_item not in
-+			 * stable tree while the in-tree rmap_items were
-+			 * deleted.
-+			 */
-+			uksm_pages_shared--;
-+		} else
-+			uksm_pages_sharing--;
-+
-+
-+		uksm_drop_anon_vma(rmap_item);
-+	} else if (rmap_item->address & UNSTABLE_FLAG) {
-+		if (rmap_item->hash_round == uksm_hash_round) {
-+
-+			rb_erase(&rmap_item->node,
-+				 &rmap_item->tree_node->sub_root);
-+			if (RB_EMPTY_ROOT(&rmap_item->tree_node->sub_root)) {
-+				rb_erase(&rmap_item->tree_node->node,
-+					 &root_unstable_tree);
-+
-+				free_tree_node(rmap_item->tree_node);
-+			} else
-+				rmap_item->tree_node->count--;
-+		}
-+		uksm_pages_unshared--;
-+	}
-+
-+	rmap_item->address &= PAGE_MASK;
-+	rmap_item->hash_max = 0;
-+
-+out:
-+	cond_resched();		/* we're called from many long loops */
-+}
-+
-+static inline int slot_in_uksm(struct vma_slot *slot)
-+{
-+	return list_empty(&slot->slot_list);
-+}
-+
-+/*
-+ * Test if the mm is exiting
-+ */
-+static inline bool uksm_test_exit(struct mm_struct *mm)
-+{
-+	return atomic_read(&mm->mm_users) == 0;
-+}
-+
-+static inline unsigned long vma_pool_size(struct vma_slot *slot)
-+{
-+	return round_up(sizeof(struct rmap_list_entry) * slot->pages,
-+			PAGE_SIZE) >> PAGE_SHIFT;
-+}
-+
-+#define CAN_OVERFLOW_U64(x, delta) (U64_MAX - (x) < (delta))
-+
-+/* must be done with sem locked */
-+static int slot_pool_alloc(struct vma_slot *slot)
-+{
-+	unsigned long pool_size;
-+
-+	if (slot->rmap_list_pool)
-+		return 0;
-+
-+	pool_size = vma_pool_size(slot);
-+	slot->rmap_list_pool = kcalloc(pool_size, sizeof(struct page *),
-+				       GFP_KERNEL);
-+	if (!slot->rmap_list_pool)
-+		return -ENOMEM;
-+
-+	slot->pool_counts = kcalloc(pool_size, sizeof(unsigned int),
-+				    GFP_KERNEL);
-+	if (!slot->pool_counts) {
-+		kfree(slot->rmap_list_pool);
-+		return -ENOMEM;
-+	}
-+
-+	slot->pool_size = pool_size;
-+	BUG_ON(CAN_OVERFLOW_U64(uksm_pages_total, slot->pages));
-+	slot->flags |= UKSM_SLOT_IN_UKSM;
-+	uksm_pages_total += slot->pages;
-+
-+	return 0;
-+}
-+
-+/*
-+ * Called after vma is unlinked from its mm
-+ */
-+void uksm_remove_vma(struct vm_area_struct *vma)
-+{
-+	struct vma_slot *slot;
-+
-+	if (!vma->uksm_vma_slot)
-+		return;
-+
-+	spin_lock(&vma_slot_list_lock);
-+	slot = vma->uksm_vma_slot;
-+	if (!slot)
-+		goto out;
-+
-+	if (slot_in_uksm(slot)) {
-+		/**
-+		 * This slot has been added by ksmd, so move to the del list
-+		 * waiting ksmd to free it.
-+		 */
-+		list_add_tail(&slot->slot_list, &vma_slot_del);
-+	} else {
-+		/**
-+		 * It's still on new list. It's ok to free slot directly.
-+		 */
-+		list_del(&slot->slot_list);
-+		free_vma_slot(slot);
-+	}
-+out:
-+	vma->uksm_vma_slot = NULL;
-+	spin_unlock(&vma_slot_list_lock);
-+}
-+
-+/**
-+ * Need to do two things:
-+ * 1. check if slot was moved to del list
-+ * 2. make sure the mmap_sem is manipulated under valid vma.
-+ *
-+ * My concern here is that in some cases, this may make
-+ * vma_slot_list_lock() waiters to serialized further by some
-+ * sem->wait_lock, can this really be expensive?
-+ *
-+ *
-+ * @return
-+ * 0: if successfully locked mmap_sem
-+ * -ENOENT: this slot was moved to del list
-+ * -EBUSY: vma lock failed
-+ */
-+static int try_down_read_slot_mmap_sem(struct vma_slot *slot)
-+{
-+	struct vm_area_struct *vma;
-+	struct mm_struct *mm;
-+	struct rw_semaphore *sem;
-+
-+	spin_lock(&vma_slot_list_lock);
-+
-+	/* the slot_list was removed and inited from new list, when it enters
-+	 * uksm_list. If now it's not empty, then it must be moved to del list
-+	 */
-+	if (!slot_in_uksm(slot)) {
-+		spin_unlock(&vma_slot_list_lock);
-+		return -ENOENT;
-+	}
-+
-+	BUG_ON(slot->pages != vma_pages(slot->vma));
-+	/* Ok, vma still valid */
-+	vma = slot->vma;
-+	mm = vma->vm_mm;
-+	sem = &mm->mmap_lock;
-+
-+	if (uksm_test_exit(mm)) {
-+		spin_unlock(&vma_slot_list_lock);
-+		return -ENOENT;
-+	}
-+
-+	if (down_read_trylock(sem)) {
-+		spin_unlock(&vma_slot_list_lock);
-+		if (slot_pool_alloc(slot)) {
-+			uksm_remove_vma(vma);
-+			up_read(sem);
-+			return -ENOENT;
-+		}
-+		return 0;
-+	}
-+
-+	spin_unlock(&vma_slot_list_lock);
-+	return -EBUSY;
-+}
-+
-+static inline unsigned long
-+vma_page_address(struct page *page, struct vm_area_struct *vma)
-+{
-+	pgoff_t pgoff = page->index;
-+	unsigned long address;
-+
-+	address = vma->vm_start + ((pgoff - vma->vm_pgoff) << PAGE_SHIFT);
-+	if (unlikely(address < vma->vm_start || address >= vma->vm_end)) {
-+		/* page should be within @vma mapping range */
-+		return -EFAULT;
-+	}
-+	return address;
-+}
-+
-+
-+/* return 0 on success with the item's mmap_sem locked */
-+static inline int get_mergeable_page_lock_mmap(struct rmap_item *item)
-+{
-+	struct mm_struct *mm;
-+	struct vma_slot *slot = item->slot;
-+	int err = -EINVAL;
-+
-+	struct page *page;
-+
-+	/*
-+	 * try_down_read_slot_mmap_sem() returns non-zero if the slot
-+	 * has been removed by uksm_remove_vma().
-+	 */
-+	if (try_down_read_slot_mmap_sem(slot))
-+		return -EBUSY;
-+
-+	mm = slot->vma->vm_mm;
-+
-+	if (uksm_test_exit(mm))
-+		goto failout_up;
-+
-+	page = item->page;
-+	rcu_read_lock();
-+	if (!get_page_unless_zero(page)) {
-+		rcu_read_unlock();
-+		goto failout_up;
-+	}
-+
-+	/* No need to consider huge page here. */
-+	if (item->slot->vma->anon_vma != page_anon_vma(page) ||
-+	    vma_page_address(page, item->slot->vma) != get_rmap_addr(item)) {
-+		/*
-+		 * TODO:
-+		 * should we release this item becase of its stale page
-+		 * mapping?
-+		 */
-+		put_page(page);
-+		rcu_read_unlock();
-+		goto failout_up;
-+	}
-+	rcu_read_unlock();
-+	return 0;
-+
-+failout_up:
-+	mmap_read_unlock(mm);
-+	return err;
-+}
-+
-+/*
-+ * What kind of VMA is considered ?
-+ */
-+static inline int vma_can_enter(struct vm_area_struct *vma)
-+{
-+	return uksm_flags_can_scan(vma->vm_flags);
-+}
-+
-+/*
-+ * Called whenever a fresh new vma is created A new vma_slot.
-+ * is created and inserted into a global list Must be called.
-+ * after vma is inserted to its mm.
-+ */
-+void uksm_vma_add_new(struct vm_area_struct *vma)
-+{
-+	struct vma_slot *slot;
-+
-+	if (!vma_can_enter(vma)) {
-+		vma->uksm_vma_slot = NULL;
-+		return;
-+	}
-+
-+	slot = alloc_vma_slot();
-+	if (!slot) {
-+		vma->uksm_vma_slot = NULL;
-+		return;
-+	}
-+
-+	vma->uksm_vma_slot = slot;
-+	vma->vm_flags |= VM_MERGEABLE;
-+	slot->vma = vma;
-+	slot->mm = vma->vm_mm;
-+	slot->ctime_j = jiffies;
-+	slot->pages = vma_pages(vma);
-+	spin_lock(&vma_slot_list_lock);
-+	list_add_tail(&slot->slot_list, &vma_slot_new);
-+	spin_unlock(&vma_slot_list_lock);
-+}
-+
-+/*   32/3 < they < 32/2 */
-+#define shiftl	8
-+#define shiftr	12
-+
-+#define HASH_FROM_TO(from, to)			\
-+for (index = from; index < to; index++) {	\
-+	pos = random_nums[index];		\
-+	hash += key[pos];			\
-+	hash += (hash << shiftl);		\
-+	hash ^= (hash >> shiftr);		\
-+}
-+
-+
-+#define HASH_FROM_DOWN_TO(from, to)		\
-+for (index = from - 1; index >= to; index--) {	\
-+	hash ^= (hash >> shiftr);		\
-+	hash ^= (hash >> (shiftr*2));		\
-+	hash -= (hash << shiftl);		\
-+	hash += (hash << (shiftl*2));		\
-+	pos = random_nums[index];		\
-+	hash -= key[pos];			\
-+}
-+
-+/*
-+ * The main random sample hash function.
-+ */
-+static u32 random_sample_hash(void *addr, u32 hash_strength)
-+{
-+	u32 hash = 0xdeadbeef;
-+	int index, pos, loop = hash_strength;
-+	u32 *key = (u32 *)addr;
-+
-+	if (loop > HASH_STRENGTH_FULL)
-+		loop = HASH_STRENGTH_FULL;
-+
-+	HASH_FROM_TO(0, loop);
-+
-+	if (hash_strength > HASH_STRENGTH_FULL) {
-+		loop = hash_strength - HASH_STRENGTH_FULL;
-+		HASH_FROM_TO(0, loop);
-+	}
-+
-+	return hash;
-+}
-+
-+
-+/**
-+ * It's used when hash strength is adjusted
-+ *
-+ * @addr The page's virtual address
-+ * @from The original hash strength
-+ * @to   The hash strength changed to
-+ * @hash The hash value generated with "from" hash value
-+ *
-+ * return the hash value
-+ */
-+static u32 delta_hash(void *addr, int from, int to, u32 hash)
-+{
-+	u32 *key = (u32 *)addr;
-+	int index, pos; /* make sure they are int type */
-+
-+	if (to > from) {
-+		if (from >= HASH_STRENGTH_FULL) {
-+			from -= HASH_STRENGTH_FULL;
-+			to -= HASH_STRENGTH_FULL;
-+			HASH_FROM_TO(from, to);
-+		} else if (to <= HASH_STRENGTH_FULL) {
-+			HASH_FROM_TO(from, to);
-+		} else {
-+			HASH_FROM_TO(from, HASH_STRENGTH_FULL);
-+			HASH_FROM_TO(0, to - HASH_STRENGTH_FULL);
-+		}
-+	} else {
-+		if (from <= HASH_STRENGTH_FULL) {
-+			HASH_FROM_DOWN_TO(from, to);
-+		} else if (to >= HASH_STRENGTH_FULL) {
-+			from -= HASH_STRENGTH_FULL;
-+			to -= HASH_STRENGTH_FULL;
-+			HASH_FROM_DOWN_TO(from, to);
-+		} else {
-+			HASH_FROM_DOWN_TO(from - HASH_STRENGTH_FULL, 0);
-+			HASH_FROM_DOWN_TO(HASH_STRENGTH_FULL, to);
-+		}
-+	}
-+
-+	return hash;
-+}
-+
-+/**
-+ *
-+ * Called when: rshash_pos or rshash_neg is about to overflow or a scan round
-+ * has finished.
-+ *
-+ * return 0 if no page has been scanned since last call, 1 otherwise.
-+ */
-+static inline int encode_benefit(void)
-+{
-+	u64 scanned_delta, pos_delta, neg_delta;
-+	unsigned long base = benefit.base;
-+
-+	scanned_delta = uksm_pages_scanned - uksm_pages_scanned_last;
-+
-+	if (!scanned_delta)
-+		return 0;
-+
-+	scanned_delta >>= base;
-+	pos_delta = rshash_pos >> base;
-+	neg_delta = rshash_neg >> base;
-+
-+	if (CAN_OVERFLOW_U64(benefit.pos, pos_delta) ||
-+	    CAN_OVERFLOW_U64(benefit.neg, neg_delta) ||
-+	    CAN_OVERFLOW_U64(benefit.scanned, scanned_delta)) {
-+		benefit.scanned >>= 1;
-+		benefit.neg >>= 1;
-+		benefit.pos >>= 1;
-+		benefit.base++;
-+		scanned_delta >>= 1;
-+		pos_delta >>= 1;
-+		neg_delta >>= 1;
-+	}
-+
-+	benefit.pos += pos_delta;
-+	benefit.neg += neg_delta;
-+	benefit.scanned += scanned_delta;
-+
-+	BUG_ON(!benefit.scanned);
-+
-+	rshash_pos = rshash_neg = 0;
-+	uksm_pages_scanned_last = uksm_pages_scanned;
-+
-+	return 1;
-+}
-+
-+static inline void reset_benefit(void)
-+{
-+	benefit.pos = 0;
-+	benefit.neg = 0;
-+	benefit.base = 0;
-+	benefit.scanned = 0;
-+}
-+
-+static inline void inc_rshash_pos(unsigned long delta)
-+{
-+	if (CAN_OVERFLOW_U64(rshash_pos, delta))
-+		encode_benefit();
-+
-+	rshash_pos += delta;
-+}
-+
-+static inline void inc_rshash_neg(unsigned long delta)
-+{
-+	if (CAN_OVERFLOW_U64(rshash_neg, delta))
-+		encode_benefit();
-+
-+	rshash_neg += delta;
-+}
-+
-+
-+static inline u32 page_hash(struct page *page, unsigned long hash_strength,
-+			    int cost_accounting)
-+{
-+	u32 val;
-+	unsigned long delta;
-+
-+	void *addr = kmap_atomic(page);
-+
-+	val = random_sample_hash(addr, hash_strength);
-+	kunmap_atomic(addr);
-+
-+	if (cost_accounting) {
-+		if (hash_strength < HASH_STRENGTH_FULL)
-+			delta = HASH_STRENGTH_FULL - hash_strength;
-+		else
-+			delta = 0;
-+
-+		inc_rshash_pos(delta);
-+	}
-+
-+	return val;
-+}
-+
-+static int memcmp_pages_with_cost(struct page *page1, struct page *page2,
-+			int cost_accounting)
-+{
-+	char *addr1, *addr2;
-+	int ret;
-+
-+	addr1 = kmap_atomic(page1);
-+	addr2 = kmap_atomic(page2);
-+	ret = memcmp(addr1, addr2, PAGE_SIZE);
-+	kunmap_atomic(addr2);
-+	kunmap_atomic(addr1);
-+
-+	if (cost_accounting)
-+		inc_rshash_neg(memcmp_cost);
-+
-+	return ret;
-+}
-+
-+static inline int pages_identical_with_cost(struct page *page1, struct page *page2)
-+{
-+	return !memcmp_pages_with_cost(page1, page2, 0);
-+}
-+
-+static inline int is_page_full_zero(struct page *page)
-+{
-+	char *addr;
-+	int ret;
-+
-+	addr = kmap_atomic(page);
-+	ret = is_full_zero(addr, PAGE_SIZE);
-+	kunmap_atomic(addr);
-+
-+	return ret;
-+}
-+
-+static int write_protect_page(struct vm_area_struct *vma, struct page *page,
-+			      pte_t *orig_pte, pte_t *old_pte)
-+{
-+	struct mm_struct *mm = vma->vm_mm;
-+	DEFINE_PAGE_VMA_WALK(pvmw, old, vma, addr, PVMW_SYNC | PVMW_MIGRATION);
-+	struct mmu_notifier_range range;
-+	int swapped;
-+	int err = -EFAULT;
-+
-+	pvmw.address = page_address_in_vma(page, vma);
-+	if (pvmw.address == -EFAULT)
-+		goto out;
-+
-+	BUG_ON(PageTransCompound(page));
-+
-+        mmu_notifier_range_init(&range, MMU_NOTIFY_CLEAR, 0, vma, mm, pvmw.address,
-+                                pvmw.address + PAGE_SIZE);
-+	mmu_notifier_invalidate_range_start(&range);
-+
-+	if (!page_vma_mapped_walk(&pvmw))
-+		goto out_mn;
-+	if (WARN_ONCE(!pvmw.pte, "Unexpected PMD mapping?"))
-+		goto out_unlock;
-+
-+	if (old_pte)
-+		*old_pte = *pvmw.pte;
-+
-+	if (pte_write(*pvmw.pte) || pte_dirty(*pvmw.pte) ||
-+	    (pte_protnone(*pvmw.pte) && pte_savedwrite(*pvmw.pte)) || mm_tlb_flush_pending(mm)) {
-+		pte_t entry;
-+
-+		swapped = PageSwapCache(page);
-+		flush_cache_page(vma, pvmw.address, page_to_pfn(page));
-+		/*
-+		 * Ok this is tricky, when get_user_pages_fast() run it doesn't
-+		 * take any lock, therefore the check that we are going to make
-+		 * with the pagecount against the mapcount is racey and
-+		 * O_DIRECT can happen right after the check.
-+		 * So we clear the pte and flush the tlb before the check
-+		 * this assure us that no O_DIRECT can happen after the check
-+		 * or in the middle of the check.
-+		 */
-+		entry = ptep_clear_flush_notify(vma, pvmw.address, pvmw.pte);
-+		/*
-+		 * Check that no O_DIRECT or similar I/O is in progress on the
-+		 * page
-+		 */
-+		if (page_mapcount(page) + 1 + swapped != page_count(page)) {
-+			set_pte_at(mm, pvmw.address, pvmw.pte, entry);
-+			goto out_unlock;
-+		}
-+		if (pte_dirty(entry))
-+			set_page_dirty(page);
-+
-+		if (pte_protnone(entry))
-+			entry = pte_mkclean(pte_clear_savedwrite(entry));
-+		else
-+			entry = pte_mkclean(pte_wrprotect(entry));
-+
-+		set_pte_at_notify(mm, pvmw.address, pvmw.pte, entry);
-+	}
-+	*orig_pte = *pvmw.pte;
-+	err = 0;
-+
-+out_unlock:
-+	page_vma_mapped_walk_done(&pvmw);
-+out_mn:
-+	mmu_notifier_invalidate_range_end(&range);
-+out:
-+	return err;
-+}
-+
-+#define MERGE_ERR_PGERR		1 /* the page is invalid cannot continue */
-+#define MERGE_ERR_COLLI		2 /* there is a collision */
-+#define MERGE_ERR_COLLI_MAX	3 /* collision at the max hash strength */
-+#define MERGE_ERR_CHANGED	4 /* the page has changed since last hash */
-+
-+
-+/**
-+ * replace_page - replace page in vma by new ksm page
-+ * @vma:      vma that holds the pte pointing to page
-+ * @page:     the page we are replacing by kpage
-+ * @kpage:    the ksm page we replace page by
-+ * @orig_pte: the original value of the pte
-+ *
-+ * Returns 0 on success, MERGE_ERR_PGERR on failure.
-+ */
-+static int replace_page(struct vm_area_struct *vma, struct page *page,
-+			struct page *kpage, pte_t orig_pte)
-+{
-+	struct mm_struct *mm = vma->vm_mm;
-+       struct mmu_notifier_range range;
-+	pgd_t *pgd;
-+	p4d_t *p4d;
-+	pud_t *pud;
-+	pmd_t *pmd;
-+	pte_t *ptep;
-+	spinlock_t *ptl;
-+	pte_t entry;
-+
-+	unsigned long addr;
-+	int err = MERGE_ERR_PGERR;
-+
-+	addr = page_address_in_vma(page, vma);
-+	if (addr == -EFAULT)
-+		goto out;
-+
-+	pgd = pgd_offset(mm, addr);
-+	if (!pgd_present(*pgd))
-+		goto out;
-+
-+	p4d = p4d_offset(pgd, addr);
-+	pud = pud_offset(p4d, addr);
-+	if (!pud_present(*pud))
-+		goto out;
-+
-+	pmd = pmd_offset(pud, addr);
-+	BUG_ON(pmd_trans_huge(*pmd));
-+	if (!pmd_present(*pmd))
-+		goto out;
-+
-+        mmu_notifier_range_init(&range, MMU_NOTIFY_CLEAR, 0, vma, mm, addr,
-+                                addr + PAGE_SIZE);
-+	mmu_notifier_invalidate_range_start(&range);
-+
-+	ptep = pte_offset_map_lock(mm, pmd, addr, &ptl);
-+	if (!pte_same(*ptep, orig_pte)) {
-+		pte_unmap_unlock(ptep, ptl);
-+		goto out_mn;
-+	}
-+
-+	flush_cache_page(vma, addr, pte_pfn(*ptep));
-+	ptep_clear_flush_notify(vma, addr, ptep);
-+	entry = mk_pte(kpage, vma->vm_page_prot);
-+
-+	/* special treatment is needed for zero_page */
-+	if ((page_to_pfn(kpage) == uksm_zero_pfn) ||
-+				(page_to_pfn(kpage) == zero_pfn)) {
-+		entry = pte_mkspecial(entry);
-+		dec_mm_counter(mm, MM_ANONPAGES);
-+		inc_zone_page_state(page, NR_UKSM_ZERO_PAGES);
-+	} else {
-+		get_page(kpage);
-+		page_add_anon_rmap(kpage, vma, addr, false);
-+	}
-+
-+	set_pte_at_notify(mm, addr, ptep, entry);
-+
-+	page_remove_rmap(page, vma, false);
-+	if (!page_mapped(page))
-+		try_to_free_swap(page);
-+	put_page(page);
-+
-+	pte_unmap_unlock(ptep, ptl);
-+	err = 0;
-+out_mn:
-+	mmu_notifier_invalidate_range_end(&range);
-+out:
-+	return err;
-+}
-+
-+
-+/**
-+ *  Fully hash a page with HASH_STRENGTH_MAX return a non-zero hash value. The
-+ *  zero hash value at HASH_STRENGTH_MAX is used to indicated that its
-+ *  hash_max member has not been calculated.
-+ *
-+ * @page The page needs to be hashed
-+ * @hash_old The hash value calculated with current hash strength
-+ *
-+ * return the new hash value calculated at HASH_STRENGTH_MAX
-+ */
-+static inline u32 page_hash_max(struct page *page, u32 hash_old)
-+{
-+	u32 hash_max = 0;
-+	void *addr;
-+
-+	addr = kmap_atomic(page);
-+	hash_max = delta_hash(addr, hash_strength,
-+			      HASH_STRENGTH_MAX, hash_old);
-+
-+	kunmap_atomic(addr);
-+
-+	if (!hash_max)
-+		hash_max = 1;
-+
-+	inc_rshash_neg(HASH_STRENGTH_MAX - hash_strength);
-+	return hash_max;
-+}
-+
-+/*
-+ * We compare the hash again, to ensure that it is really a hash collision
-+ * instead of being caused by page write.
-+ */
-+static inline int check_collision(struct rmap_item *rmap_item,
-+				  u32 hash)
-+{
-+	int err;
-+	struct page *page = rmap_item->page;
-+
-+	/* if this rmap_item has already been hash_maxed, then the collision
-+	 * must appears in the second-level rbtree search. In this case we check
-+	 * if its hash_max value has been changed. Otherwise, the collision
-+	 * happens in the first-level rbtree search, so we check against it's
-+	 * current hash value.
-+	 */
-+	if (rmap_item->hash_max) {
-+		inc_rshash_neg(memcmp_cost);
-+		inc_rshash_neg(HASH_STRENGTH_MAX - hash_strength);
-+
-+		if (rmap_item->hash_max == page_hash_max(page, hash))
-+			err = MERGE_ERR_COLLI;
-+		else
-+			err = MERGE_ERR_CHANGED;
-+	} else {
-+		inc_rshash_neg(memcmp_cost + hash_strength);
-+
-+		if (page_hash(page, hash_strength, 0) == hash)
-+			err = MERGE_ERR_COLLI;
-+		else
-+			err = MERGE_ERR_CHANGED;
-+	}
-+
-+	return err;
-+}
-+
-+/**
-+ * Try to merge a rmap_item.page with a kpage in stable node. kpage must
-+ * already be a ksm page.
-+ *
-+ * @return 0 if the pages were merged, -EFAULT otherwise.
-+ */
-+static int try_to_merge_with_uksm_page(struct rmap_item *rmap_item,
-+				      struct page *kpage, u32 hash)
-+{
-+	struct vm_area_struct *vma = rmap_item->slot->vma;
-+	struct mm_struct *mm = vma->vm_mm;
-+	pte_t orig_pte = __pte(0);
-+	int err = MERGE_ERR_PGERR;
-+	struct page *page;
-+
-+	if (uksm_test_exit(mm))
-+		goto out;
-+
-+	page = rmap_item->page;
-+
-+	if (page == kpage) { /* ksm page forked */
-+		err = 0;
-+		goto out;
-+	}
-+
-+	/*
-+	 * We need the page lock to read a stable PageSwapCache in
-+	 * write_protect_page().  We use trylock_page() instead of
-+	 * lock_page() because we don't want to wait here - we
-+	 * prefer to continue scanning and merging different pages,
-+	 * then come back to this page when it is unlocked.
-+	 */
-+	if (!trylock_page(page))
-+		goto out;
-+
-+	if (!PageAnon(page) || !PageKsm(kpage))
-+		goto out_unlock;
-+
-+	if (PageTransCompound(page)) {
-+		err = split_huge_page(page);
-+		if (err)
-+			goto out_unlock;
-+	}
-+
-+	/*
-+	 * If this anonymous page is mapped only here, its pte may need
-+	 * to be write-protected.  If it's mapped elsewhere, all of its
-+	 * ptes are necessarily already write-protected.  But in either
-+	 * case, we need to lock and check page_count is not raised.
-+	 */
-+	if (write_protect_page(vma, page, &orig_pte, NULL) == 0) {
-+		if (pages_identical_with_cost(page, kpage))
-+			err = replace_page(vma, page, kpage, orig_pte);
-+		else
-+			err = check_collision(rmap_item, hash);
-+	}
-+
-+out_unlock:
-+	unlock_page(page);
-+out:
-+	return err;
-+}
-+
-+
-+
-+/**
-+ * If two pages fail to merge in try_to_merge_two_pages, then we have a chance
-+ * to restore a page mapping that has been changed in try_to_merge_two_pages.
-+ *
-+ * @return 0 on success.
-+ */
-+static int restore_uksm_page_pte(struct vm_area_struct *vma, unsigned long addr,
-+			     pte_t orig_pte, pte_t wprt_pte)
-+{
-+	struct mm_struct *mm = vma->vm_mm;
-+	pgd_t *pgd;
-+	p4d_t *p4d;
-+	pud_t *pud;
-+	pmd_t *pmd;
-+	pte_t *ptep;
-+	spinlock_t *ptl;
-+
-+	int err = -EFAULT;
-+
-+	pgd = pgd_offset(mm, addr);
-+	if (!pgd_present(*pgd))
-+		goto out;
-+
-+	p4d = p4d_offset(pgd, addr);
-+	pud = pud_offset(p4d, addr);
-+	if (!pud_present(*pud))
-+		goto out;
-+
-+	pmd = pmd_offset(pud, addr);
-+	if (!pmd_present(*pmd))
-+		goto out;
-+
-+	ptep = pte_offset_map_lock(mm, pmd, addr, &ptl);
-+	if (!pte_same(*ptep, wprt_pte)) {
-+		/* already copied, let it be */
-+		pte_unmap_unlock(ptep, ptl);
-+		goto out;
-+	}
-+
-+	/*
-+	 * Good boy, still here. When we still get the ksm page, it does not
-+	 * return to the free page pool, there is no way that a pte was changed
-+	 * to other page and gets back to this page. And remind that ksm page
-+	 * do not reuse in do_wp_page(). So it's safe to restore the original
-+	 * pte.
-+	 */
-+	flush_cache_page(vma, addr, pte_pfn(*ptep));
-+	ptep_clear_flush_notify(vma, addr, ptep);
-+	set_pte_at_notify(mm, addr, ptep, orig_pte);
-+
-+	pte_unmap_unlock(ptep, ptl);
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+/**
-+ * try_to_merge_two_pages() - take two identical pages and prepare
-+ * them to be merged into one page(rmap_item->page)
-+ *
-+ * @return 0 if we successfully merged two identical pages into
-+ *         one ksm page. MERGE_ERR_COLLI if it's only a hash collision
-+ *         search in rbtree. MERGE_ERR_CHANGED if rmap_item has been
-+ *         changed since it's hashed. MERGE_ERR_PGERR otherwise.
-+ *
-+ */
-+static int try_to_merge_two_pages(struct rmap_item *rmap_item,
-+				  struct rmap_item *tree_rmap_item,
-+				  u32 hash)
-+{
-+	pte_t orig_pte1 = __pte(0), orig_pte2 = __pte(0);
-+	pte_t wprt_pte1 = __pte(0), wprt_pte2 = __pte(0);
-+	struct vm_area_struct *vma1 = rmap_item->slot->vma;
-+	struct vm_area_struct *vma2 = tree_rmap_item->slot->vma;
-+	struct page *page = rmap_item->page;
-+	struct page *tree_page = tree_rmap_item->page;
-+	int err = MERGE_ERR_PGERR;
-+	struct address_space *saved_mapping;
-+
-+
-+	if (rmap_item->page == tree_rmap_item->page)
-+		goto out;
-+
-+	if (!trylock_page(page))
-+		goto out;
-+
-+	if (!PageAnon(page))
-+		goto out_unlock;
-+
-+	if (PageTransCompound(page)) {
-+		err = split_huge_page(page);
-+		if (err)
-+			goto out_unlock;
-+	}
-+
-+	if (write_protect_page(vma1, page, &wprt_pte1, &orig_pte1) != 0) {
-+		unlock_page(page);
-+		goto out;
-+	}
-+
-+	/*
-+	 * While we hold page lock, upgrade page from
-+	 * PageAnon+anon_vma to PageKsm+NULL stable_node:
-+	 * stable_tree_insert() will update stable_node.
-+	 */
-+	saved_mapping = page->mapping;
-+	set_page_stable_node(page, NULL);
-+	mark_page_accessed(page);
-+	if (!PageDirty(page))
-+		SetPageDirty(page);
-+
-+	unlock_page(page);
-+
-+	if (!trylock_page(tree_page))
-+		goto restore_out;
-+
-+	if (!PageAnon(tree_page)) {
-+		unlock_page(tree_page);
-+		goto restore_out;
-+	}
-+
-+	if (PageTransCompound(tree_page)) {
-+		err = split_huge_page(tree_page);
-+		if (err) {
-+			unlock_page(tree_page);
-+			goto restore_out;
-+		}
-+	}
-+
-+	if (write_protect_page(vma2, tree_page, &wprt_pte2, &orig_pte2) != 0) {
-+		unlock_page(tree_page);
-+		goto restore_out;
-+	}
-+
-+	if (pages_identical_with_cost(page, tree_page)) {
-+		err = replace_page(vma2, tree_page, page, wprt_pte2);
-+		if (err) {
-+			unlock_page(tree_page);
-+			goto restore_out;
-+		}
-+
-+		if ((vma2->vm_flags & VM_LOCKED)) {
-+			munlock_vma_page(tree_page);
-+			if (!PageMlocked(page)) {
-+				unlock_page(tree_page);
-+				lock_page(page);
-+				mlock_vma_page(page);
-+				tree_page = page; /* for final unlock */
-+			}
-+		}
-+
-+		unlock_page(tree_page);
-+
-+		goto out; /* success */
-+
-+	} else {
-+		if (tree_rmap_item->hash_max &&
-+		    tree_rmap_item->hash_max == rmap_item->hash_max) {
-+			err = MERGE_ERR_COLLI_MAX;
-+		} else if (page_hash(page, hash_strength, 0) ==
-+		    page_hash(tree_page, hash_strength, 0)) {
-+			inc_rshash_neg(memcmp_cost + hash_strength * 2);
-+			err = MERGE_ERR_COLLI;
-+		} else {
-+			err = MERGE_ERR_CHANGED;
-+		}
-+
-+		unlock_page(tree_page);
-+	}
-+
-+restore_out:
-+	lock_page(page);
-+	if (!restore_uksm_page_pte(vma1, get_rmap_addr(rmap_item),
-+				  orig_pte1, wprt_pte1))
-+		page->mapping = saved_mapping;
-+
-+out_unlock:
-+	unlock_page(page);
-+out:
-+	return err;
-+}
-+
-+static inline int hash_cmp(u32 new_val, u32 node_val)
-+{
-+	if (new_val > node_val)
-+		return 1;
-+	else if (new_val < node_val)
-+		return -1;
-+	else
-+		return 0;
-+}
-+
-+static inline u32 rmap_item_hash_max(struct rmap_item *item, u32 hash)
-+{
-+	u32 hash_max = item->hash_max;
-+
-+	if (!hash_max) {
-+		hash_max = page_hash_max(item->page, hash);
-+
-+		item->hash_max = hash_max;
-+	}
-+
-+	return hash_max;
-+}
-+
-+
-+
-+/**
-+ * stable_tree_search() - search the stable tree for a page
-+ *
-+ * @item:	the rmap_item we are comparing with
-+ * @hash:	the hash value of this item->page already calculated
-+ *
-+ * @return	the page we have found, NULL otherwise. The page returned has
-+ *			been gotten.
-+ */
-+static struct page *stable_tree_search(struct rmap_item *item, u32 hash)
-+{
-+	struct rb_node *node = root_stable_treep->rb_node;
-+	struct tree_node *tree_node;
-+	unsigned long hash_max;
-+	struct page *page = item->page;
-+	struct stable_node *stable_node;
-+
-+	stable_node = page_stable_node(page);
-+	if (stable_node) {
-+		/* ksm page forked, that is
-+		 * if (PageKsm(page) && !in_stable_tree(rmap_item))
-+		 * it's actually gotten once outside.
-+		 */
-+		get_page(page);
-+		return page;
-+	}
-+
-+	while (node) {
-+		int cmp;
-+
-+		tree_node = rb_entry(node, struct tree_node, node);
-+
-+		cmp = hash_cmp(hash, tree_node->hash);
-+
-+		if (cmp < 0)
-+			node = node->rb_left;
-+		else if (cmp > 0)
-+			node = node->rb_right;
-+		else
-+			break;
-+	}
-+
-+	if (!node)
-+		return NULL;
-+
-+	if (tree_node->count == 1) {
-+		stable_node = rb_entry(tree_node->sub_root.rb_node,
-+				       struct stable_node, node);
-+		BUG_ON(!stable_node);
-+
-+		goto get_page_out;
-+	}
-+
-+	/*
-+	 * ok, we have to search the second
-+	 * level subtree, hash the page to a
-+	 * full strength.
-+	 */
-+	node = tree_node->sub_root.rb_node;
-+	BUG_ON(!node);
-+	hash_max = rmap_item_hash_max(item, hash);
-+
-+	while (node) {
-+		int cmp;
-+
-+		stable_node = rb_entry(node, struct stable_node, node);
-+
-+		cmp = hash_cmp(hash_max, stable_node->hash_max);
-+
-+		if (cmp < 0)
-+			node = node->rb_left;
-+		else if (cmp > 0)
-+			node = node->rb_right;
-+		else
-+			goto get_page_out;
-+	}
-+
-+	return NULL;
-+
-+get_page_out:
-+	page = get_uksm_page(stable_node, 1, 1);
-+	return page;
-+}
-+
-+static int try_merge_rmap_item(struct rmap_item *item,
-+			       struct page *kpage,
-+			       struct page *tree_page)
-+{
-+	struct vm_area_struct *vma = item->slot->vma;
-+	DEFINE_PAGE_VMA_WALK(pvmw, page, vma, 0, 0);
-+
-+	pvmw.address = get_rmap_addr(item);
-+	if (!page_vma_mapped_walk(&pvmw))
-+		return 0;
-+
-+	if (pte_write(*pvmw.pte)) {
-+		/* has changed, abort! */
-+		page_vma_mapped_walk_done(&pvmw);
-+		return 0;
-+	}
-+
-+	get_page(tree_page);
-+	page_add_anon_rmap(tree_page, vma, pvmw.address, false);
-+
-+	flush_cache_page(vma, pvmw.address, page_to_pfn(kpage));
-+	ptep_clear_flush_notify(vma, pvmw.address, pvmw.pte);
-+	set_pte_at_notify(vma->vm_mm, pvmw.address, pvmw.pte,
-+			  mk_pte(tree_page, vma->vm_page_prot));
-+
-+	page_remove_rmap(kpage, false);
-+	put_page(kpage);
-+
-+	page_vma_mapped_walk_done(&pvmw);
-+
-+	return 1;
-+}
-+
-+/**
-+ * try_to_merge_with_stable_page() - when two rmap_items need to be inserted
-+ * into stable tree, the page was found to be identical to a stable ksm page,
-+ * this is the last chance we can merge them into one.
-+ *
-+ * @item1:	the rmap_item holding the page which we wanted to insert
-+ *		into stable tree.
-+ * @item2:	the other rmap_item we found when unstable tree search
-+ * @oldpage:	the page currently mapped by the two rmap_items
-+ * @tree_page:	the page we found identical in stable tree node
-+ * @success1:	return if item1 is successfully merged
-+ * @success2:	return if item2 is successfully merged
-+ */
-+static void try_merge_with_stable(struct rmap_item *item1,
-+				  struct rmap_item *item2,
-+				  struct page **kpage,
-+				  struct page *tree_page,
-+				  int *success1, int *success2)
-+{
-+	struct vm_area_struct *vma1 = item1->slot->vma;
-+	struct vm_area_struct *vma2 = item2->slot->vma;
-+	*success1 = 0;
-+	*success2 = 0;
-+
-+	if (unlikely(*kpage == tree_page)) {
-+		/* I don't think this can really happen */
-+		pr_warn("UKSM: unexpected condition detected in "
-+			"%s -- *kpage == tree_page !\n", __func__);
-+		*success1 = 1;
-+		*success2 = 1;
-+		return;
-+	}
-+
-+	if (!PageAnon(*kpage) || !PageKsm(*kpage))
-+		goto failed;
-+
-+	if (!trylock_page(tree_page))
-+		goto failed;
-+
-+	/* If the oldpage is still ksm and still pointed
-+	 * to in the right place, and still write protected,
-+	 * we are confident it's not changed, no need to
-+	 * memcmp anymore.
-+	 * be ware, we cannot take nested pte locks,
-+	 * deadlock risk.
-+	 */
-+	if (!try_merge_rmap_item(item1, *kpage, tree_page))
-+		goto unlock_failed;
-+
-+	/* ok, then vma2, remind that pte1 already set */
-+	if (!try_merge_rmap_item(item2, *kpage, tree_page))
-+		goto success_1;
-+
-+	*success2 = 1;
-+success_1:
-+	*success1 = 1;
-+
-+
-+	if ((*success1 && vma1->vm_flags & VM_LOCKED) ||
-+	    (*success2 && vma2->vm_flags & VM_LOCKED)) {
-+		munlock_vma_page(*kpage);
-+		if (!PageMlocked(tree_page))
-+			mlock_vma_page(tree_page);
-+	}
-+
-+	/*
-+	 * We do not need oldpage any more in the caller, so can break the lock
-+	 * now.
-+	 */
-+	unlock_page(*kpage);
-+	*kpage = tree_page; /* Get unlocked outside. */
-+	return;
-+
-+unlock_failed:
-+	unlock_page(tree_page);
-+failed:
-+	return;
-+}
-+
-+static inline void stable_node_hash_max(struct stable_node *node,
-+					 struct page *page, u32 hash)
-+{
-+	u32 hash_max = node->hash_max;
-+
-+	if (!hash_max) {
-+		hash_max = page_hash_max(page, hash);
-+		node->hash_max = hash_max;
-+	}
-+}
-+
-+static inline
-+struct stable_node *new_stable_node(struct tree_node *tree_node,
-+				    struct page *kpage, u32 hash_max)
-+{
-+	struct stable_node *new_stable_node;
-+
-+	new_stable_node = alloc_stable_node();
-+	if (!new_stable_node)
-+		return NULL;
-+
-+	new_stable_node->kpfn = page_to_pfn(kpage);
-+	new_stable_node->hash_max = hash_max;
-+	new_stable_node->tree_node = tree_node;
-+	set_page_stable_node(kpage, new_stable_node);
-+
-+	return new_stable_node;
-+}
-+
-+static inline
-+struct stable_node *first_level_insert(struct tree_node *tree_node,
-+				       struct rmap_item *rmap_item,
-+				       struct rmap_item *tree_rmap_item,
-+				       struct page **kpage, u32 hash,
-+				       int *success1, int *success2)
-+{
-+	int cmp;
-+	struct page *tree_page;
-+	u32 hash_max = 0;
-+	struct stable_node *stable_node, *new_snode;
-+	struct rb_node *parent = NULL, **new;
-+
-+	/* this tree node contains no sub-tree yet */
-+	stable_node = rb_entry(tree_node->sub_root.rb_node,
-+			       struct stable_node, node);
-+
-+	tree_page = get_uksm_page(stable_node, 1, 0);
-+	if (tree_page) {
-+		cmp = memcmp_pages_with_cost(*kpage, tree_page, 1);
-+		if (!cmp) {
-+			try_merge_with_stable(rmap_item, tree_rmap_item, kpage,
-+					      tree_page, success1, success2);
-+			put_page(tree_page);
-+			if (!*success1 && !*success2)
-+				goto failed;
-+
-+			return stable_node;
-+
-+		} else {
-+			/*
-+			 * collision in first level try to create a subtree.
-+			 * A new node need to be created.
-+			 */
-+			put_page(tree_page);
-+
-+			stable_node_hash_max(stable_node, tree_page,
-+					     tree_node->hash);
-+			hash_max = rmap_item_hash_max(rmap_item, hash);
-+			cmp = hash_cmp(hash_max, stable_node->hash_max);
-+
-+			parent = &stable_node->node;
-+			if (cmp < 0)
-+				new = &parent->rb_left;
-+			else if (cmp > 0)
-+				new = &parent->rb_right;
-+			else
-+				goto failed;
-+		}
-+
-+	} else {
-+		/* the only stable_node deleted, we reuse its tree_node.
-+		 */
-+		parent = NULL;
-+		new = &tree_node->sub_root.rb_node;
-+	}
-+
-+	new_snode = new_stable_node(tree_node, *kpage, hash_max);
-+	if (!new_snode)
-+		goto failed;
-+
-+	rb_link_node(&new_snode->node, parent, new);
-+	rb_insert_color(&new_snode->node, &tree_node->sub_root);
-+	tree_node->count++;
-+	*success1 = *success2 = 1;
-+
-+	return new_snode;
-+
-+failed:
-+	return NULL;
-+}
-+
-+static inline
-+struct stable_node *stable_subtree_insert(struct tree_node *tree_node,
-+					  struct rmap_item *rmap_item,
-+					  struct rmap_item *tree_rmap_item,
-+					  struct page **kpage, u32 hash,
-+					  int *success1, int *success2)
-+{
-+	struct page *tree_page;
-+	u32 hash_max;
-+	struct stable_node *stable_node, *new_snode;
-+	struct rb_node *parent, **new;
-+
-+research:
-+	parent = NULL;
-+	new = &tree_node->sub_root.rb_node;
-+	BUG_ON(!*new);
-+	hash_max = rmap_item_hash_max(rmap_item, hash);
-+	while (*new) {
-+		int cmp;
-+
-+		stable_node = rb_entry(*new, struct stable_node, node);
-+
-+		cmp = hash_cmp(hash_max, stable_node->hash_max);
-+
-+		if (cmp < 0) {
-+			parent = *new;
-+			new = &parent->rb_left;
-+		} else if (cmp > 0) {
-+			parent = *new;
-+			new = &parent->rb_right;
-+		} else {
-+			tree_page = get_uksm_page(stable_node, 1, 0);
-+			if (tree_page) {
-+				cmp = memcmp_pages_with_cost(*kpage, tree_page, 1);
-+				if (!cmp) {
-+					try_merge_with_stable(rmap_item,
-+						tree_rmap_item, kpage,
-+						tree_page, success1, success2);
-+
-+					put_page(tree_page);
-+					if (!*success1 && !*success2)
-+						goto failed;
-+					/*
-+					 * successfully merged with a stable
-+					 * node
-+					 */
-+					return stable_node;
-+				} else {
-+					put_page(tree_page);
-+					goto failed;
-+				}
-+			} else {
-+				/*
-+				 * stable node may be deleted,
-+				 * and subtree maybe
-+				 * restructed, cannot
-+				 * continue, research it.
-+				 */
-+				if (tree_node->count) {
-+					goto research;
-+				} else {
-+					/* reuse the tree node*/
-+					parent = NULL;
-+					new = &tree_node->sub_root.rb_node;
-+				}
-+			}
-+		}
-+	}
-+
-+	new_snode = new_stable_node(tree_node, *kpage, hash_max);
-+	if (!new_snode)
-+		goto failed;
-+
-+	rb_link_node(&new_snode->node, parent, new);
-+	rb_insert_color(&new_snode->node, &tree_node->sub_root);
-+	tree_node->count++;
-+	*success1 = *success2 = 1;
-+
-+	return new_snode;
-+
-+failed:
-+	return NULL;
-+}
-+
-+
-+/**
-+ * stable_tree_insert() - try to insert a merged page in unstable tree to
-+ * the stable tree
-+ *
-+ * @kpage:		the page need to be inserted
-+ * @hash:		the current hash of this page
-+ * @rmap_item:		the rmap_item being scanned
-+ * @tree_rmap_item:	the rmap_item found on unstable tree
-+ * @success1:		return if rmap_item is merged
-+ * @success2:		return if tree_rmap_item is merged
-+ *
-+ * @return		the stable_node on stable tree if at least one
-+ *			rmap_item is inserted into stable tree, NULL
-+ *			otherwise.
-+ */
-+static struct stable_node *
-+stable_tree_insert(struct page **kpage, u32 hash,
-+		   struct rmap_item *rmap_item,
-+		   struct rmap_item *tree_rmap_item,
-+		   int *success1, int *success2)
-+{
-+	struct rb_node **new = &root_stable_treep->rb_node;
-+	struct rb_node *parent = NULL;
-+	struct stable_node *stable_node;
-+	struct tree_node *tree_node;
-+	u32 hash_max = 0;
-+
-+	*success1 = *success2 = 0;
-+
-+	while (*new) {
-+		int cmp;
-+
-+		tree_node = rb_entry(*new, struct tree_node, node);
-+
-+		cmp = hash_cmp(hash, tree_node->hash);
-+
-+		if (cmp < 0) {
-+			parent = *new;
-+			new = &parent->rb_left;
-+		} else if (cmp > 0) {
-+			parent = *new;
-+			new = &parent->rb_right;
-+		} else
-+			break;
-+	}
-+
-+	if (*new) {
-+		if (tree_node->count == 1) {
-+			stable_node = first_level_insert(tree_node, rmap_item,
-+						tree_rmap_item, kpage,
-+						hash, success1, success2);
-+		} else {
-+			stable_node = stable_subtree_insert(tree_node,
-+					rmap_item, tree_rmap_item, kpage,
-+					hash, success1, success2);
-+		}
-+	} else {
-+
-+		/* no tree node found */
-+		tree_node = alloc_tree_node(stable_tree_node_listp);
-+		if (!tree_node) {
-+			stable_node = NULL;
-+			goto out;
-+		}
-+
-+		stable_node = new_stable_node(tree_node, *kpage, hash_max);
-+		if (!stable_node) {
-+			free_tree_node(tree_node);
-+			goto out;
-+		}
-+
-+		tree_node->hash = hash;
-+		rb_link_node(&tree_node->node, parent, new);
-+		rb_insert_color(&tree_node->node, root_stable_treep);
-+		parent = NULL;
-+		new = &tree_node->sub_root.rb_node;
-+
-+		rb_link_node(&stable_node->node, parent, new);
-+		rb_insert_color(&stable_node->node, &tree_node->sub_root);
-+		tree_node->count++;
-+		*success1 = *success2 = 1;
-+	}
-+
-+out:
-+	return stable_node;
-+}
-+
-+
-+/**
-+ * get_tree_rmap_item_page() - try to get the page and lock the mmap_sem
-+ *
-+ * @return	0 on success, -EBUSY if unable to lock the mmap_sem,
-+ *		-EINVAL if the page mapping has been changed.
-+ */
-+static inline int get_tree_rmap_item_page(struct rmap_item *tree_rmap_item)
-+{
-+	int err;
-+
-+	err = get_mergeable_page_lock_mmap(tree_rmap_item);
-+
-+	if (err == -EINVAL) {
-+		/* its page map has been changed, remove it */
-+		remove_rmap_item_from_tree(tree_rmap_item);
-+	}
-+
-+	/* The page is gotten and mmap_sem is locked now. */
-+	return err;
-+}
-+
-+
-+/**
-+ * unstable_tree_search_insert() - search an unstable tree rmap_item with the
-+ * same hash value. Get its page and trylock the mmap_sem
-+ */
-+static inline
-+struct rmap_item *unstable_tree_search_insert(struct rmap_item *rmap_item,
-+					      u32 hash)
-+
-+{
-+	struct rb_node **new = &root_unstable_tree.rb_node;
-+	struct rb_node *parent = NULL;
-+	struct tree_node *tree_node;
-+	u32 hash_max;
-+	struct rmap_item *tree_rmap_item;
-+
-+	while (*new) {
-+		int cmp;
-+
-+		tree_node = rb_entry(*new, struct tree_node, node);
-+
-+		cmp = hash_cmp(hash, tree_node->hash);
-+
-+		if (cmp < 0) {
-+			parent = *new;
-+			new = &parent->rb_left;
-+		} else if (cmp > 0) {
-+			parent = *new;
-+			new = &parent->rb_right;
-+		} else
-+			break;
-+	}
-+
-+	if (*new) {
-+		/* got the tree_node */
-+		if (tree_node->count == 1) {
-+			tree_rmap_item = rb_entry(tree_node->sub_root.rb_node,
-+						  struct rmap_item, node);
-+			BUG_ON(!tree_rmap_item);
-+
-+			goto get_page_out;
-+		}
-+
-+		/* well, search the collision subtree */
-+		new = &tree_node->sub_root.rb_node;
-+		BUG_ON(!*new);
-+		hash_max = rmap_item_hash_max(rmap_item, hash);
-+
-+		while (*new) {
-+			int cmp;
-+
-+			tree_rmap_item = rb_entry(*new, struct rmap_item,
-+						  node);
-+
-+			cmp = hash_cmp(hash_max, tree_rmap_item->hash_max);
-+			parent = *new;
-+			if (cmp < 0)
-+				new = &parent->rb_left;
-+			else if (cmp > 0)
-+				new = &parent->rb_right;
-+			else
-+				goto get_page_out;
-+		}
-+	} else {
-+		/* alloc a new tree_node */
-+		tree_node = alloc_tree_node(&unstable_tree_node_list);
-+		if (!tree_node)
-+			return NULL;
-+
-+		tree_node->hash = hash;
-+		rb_link_node(&tree_node->node, parent, new);
-+		rb_insert_color(&tree_node->node, &root_unstable_tree);
-+		parent = NULL;
-+		new = &tree_node->sub_root.rb_node;
-+	}
-+
-+	/* did not found even in sub-tree */
-+	rmap_item->tree_node = tree_node;
-+	rmap_item->address |= UNSTABLE_FLAG;
-+	rmap_item->hash_round = uksm_hash_round;
-+	rb_link_node(&rmap_item->node, parent, new);
-+	rb_insert_color(&rmap_item->node, &tree_node->sub_root);
-+
-+	uksm_pages_unshared++;
-+	return NULL;
-+
-+get_page_out:
-+	if (tree_rmap_item->page == rmap_item->page)
-+		return NULL;
-+
-+	if (get_tree_rmap_item_page(tree_rmap_item))
-+		return NULL;
-+
-+	return tree_rmap_item;
-+}
-+
-+static void hold_anon_vma(struct rmap_item *rmap_item,
-+			  struct anon_vma *anon_vma)
-+{
-+	rmap_item->anon_vma = anon_vma;
-+	get_anon_vma(anon_vma);
-+}
-+
-+
-+/**
-+ * stable_tree_append() - append a rmap_item to a stable node. Deduplication
-+ * ratio statistics is done in this function.
-+ *
-+ */
-+static void stable_tree_append(struct rmap_item *rmap_item,
-+			       struct stable_node *stable_node, int logdedup)
-+{
-+	struct node_vma *node_vma = NULL, *new_node_vma, *node_vma_cont = NULL;
-+	unsigned long key = (unsigned long)rmap_item->slot;
-+	unsigned long factor = rmap_item->slot->rung->step;
-+
-+	BUG_ON(!stable_node);
-+	rmap_item->address |= STABLE_FLAG;
-+
-+	if (hlist_empty(&stable_node->hlist)) {
-+		uksm_pages_shared++;
-+		goto node_vma_new;
-+	} else {
-+		uksm_pages_sharing++;
-+	}
-+
-+	hlist_for_each_entry(node_vma, &stable_node->hlist, hlist) {
-+		if (node_vma->key >= key)
-+			break;
-+
-+		if (logdedup) {
-+			node_vma->slot->pages_bemerged += factor;
-+			if (list_empty(&node_vma->slot->dedup_list))
-+				list_add(&node_vma->slot->dedup_list,
-+					 &vma_slot_dedup);
-+		}
-+	}
-+
-+	if (node_vma) {
-+		if (node_vma->key == key) {
-+			node_vma_cont = hlist_entry_safe(node_vma->hlist.next, struct node_vma, hlist);
-+			goto node_vma_ok;
-+		} else if (node_vma->key > key) {
-+			node_vma_cont = node_vma;
-+		}
-+	}
-+
-+node_vma_new:
-+	/* no same vma already in node, alloc a new node_vma */
-+	new_node_vma = alloc_node_vma();
-+	BUG_ON(!new_node_vma);
-+	new_node_vma->head = stable_node;
-+	new_node_vma->slot = rmap_item->slot;
-+
-+	if (!node_vma) {
-+		hlist_add_head(&new_node_vma->hlist, &stable_node->hlist);
-+	} else if (node_vma->key != key) {
-+		if (node_vma->key < key)
-+			hlist_add_behind(&new_node_vma->hlist, &node_vma->hlist);
-+		else {
-+			hlist_add_before(&new_node_vma->hlist,
-+					 &node_vma->hlist);
-+		}
-+
-+	}
-+	node_vma = new_node_vma;
-+
-+node_vma_ok: /* ok, ready to add to the list */
-+	rmap_item->head = node_vma;
-+	hlist_add_head(&rmap_item->hlist, &node_vma->rmap_hlist);
-+	hold_anon_vma(rmap_item, rmap_item->slot->vma->anon_vma);
-+	if (logdedup) {
-+		rmap_item->slot->pages_merged++;
-+		if (node_vma_cont) {
-+			node_vma = node_vma_cont;
-+			hlist_for_each_entry_continue(node_vma, hlist) {
-+				node_vma->slot->pages_bemerged += factor;
-+				if (list_empty(&node_vma->slot->dedup_list))
-+					list_add(&node_vma->slot->dedup_list,
-+						 &vma_slot_dedup);
-+			}
-+		}
-+	}
-+}
-+
-+/*
-+ * We use break_ksm to break COW on a ksm page: it's a stripped down
-+ *
-+ *	if (get_user_pages(addr, 1, 1, 1, &page, NULL) == 1)
-+ *		put_page(page);
-+ *
-+ * but taking great care only to touch a ksm page, in a VM_MERGEABLE vma,
-+ * in case the application has unmapped and remapped mm,addr meanwhile.
-+ * Could a ksm page appear anywhere else?  Actually yes, in a VM_PFNMAP
-+ * mmap of /dev/mem or /dev/kmem, where we would not want to touch it.
-+ */
-+static int break_ksm(struct vm_area_struct *vma, unsigned long addr)
-+{
-+	struct page *page;
-+	int ret = 0;
-+
-+	do {
-+		cond_resched();
-+		page = follow_page(vma, addr, FOLL_GET | FOLL_MIGRATION | FOLL_REMOTE);
-+		if (IS_ERR_OR_NULL(page))
-+			break;
-+		if (PageKsm(page)) {
-+			ret = handle_mm_fault(vma, addr,
-+					      FAULT_FLAG_WRITE | FAULT_FLAG_REMOTE,
-+                                             NULL);
-+		} else
-+			ret = VM_FAULT_WRITE;
-+		put_page(page);
-+	} while (!(ret & (VM_FAULT_WRITE | VM_FAULT_SIGBUS | VM_FAULT_SIGSEGV | VM_FAULT_OOM)));
-+	/*
-+	 * We must loop because handle_mm_fault() may back out if there's
-+	 * any difficulty e.g. if pte accessed bit gets updated concurrently.
-+	 *
-+	 * VM_FAULT_WRITE is what we have been hoping for: it indicates that
-+	 * COW has been broken, even if the vma does not permit VM_WRITE;
-+	 * but note that a concurrent fault might break PageKsm for us.
-+	 *
-+	 * VM_FAULT_SIGBUS could occur if we race with truncation of the
-+	 * backing file, which also invalidates anonymous pages: that's
-+	 * okay, that truncation will have unmapped the PageKsm for us.
-+	 *
-+	 * VM_FAULT_OOM: at the time of writing (late July 2009), setting
-+	 * aside mem_cgroup limits, VM_FAULT_OOM would only be set if the
-+	 * current task has TIF_MEMDIE set, and will be OOM killed on return
-+	 * to user; and ksmd, having no mm, would never be chosen for that.
-+	 *
-+	 * But if the mm is in a limited mem_cgroup, then the fault may fail
-+	 * with VM_FAULT_OOM even if the current task is not TIF_MEMDIE; and
-+	 * even ksmd can fail in this way - though it's usually breaking ksm
-+	 * just to undo a merge it made a moment before, so unlikely to oom.
-+	 *
-+	 * That's a pity: we might therefore have more kernel pages allocated
-+	 * than we're counting as nodes in the stable tree; but uksm_do_scan
-+	 * will retry to break_cow on each pass, so should recover the page
-+	 * in due course.  The important thing is to not let VM_MERGEABLE
-+	 * be cleared while any such pages might remain in the area.
-+	 */
-+	return (ret & VM_FAULT_OOM) ? -ENOMEM : 0;
-+}
-+
-+static void break_cow(struct rmap_item *rmap_item)
-+{
-+	struct vm_area_struct *vma = rmap_item->slot->vma;
-+	struct mm_struct *mm = vma->vm_mm;
-+	unsigned long addr = get_rmap_addr(rmap_item);
-+
-+	if (uksm_test_exit(mm))
-+		goto out;
-+
-+	break_ksm(vma, addr);
-+out:
-+	return;
-+}
-+
-+/*
-+ * Though it's very tempting to unmerge in_stable_tree(rmap_item)s rather
-+ * than check every pte of a given vma, the locking doesn't quite work for
-+ * that - an rmap_item is assigned to the stable tree after inserting ksm
-+ * page and upping mmap_sem.  Nor does it fit with the way we skip dup'ing
-+ * rmap_items from parent to child at fork time (so as not to waste time
-+ * if exit comes before the next scan reaches it).
-+ *
-+ * Similarly, although we'd like to remove rmap_items (so updating counts
-+ * and freeing memory) when unmerging an area, it's easier to leave that
-+ * to the next pass of ksmd - consider, for example, how ksmd might be
-+ * in cmp_and_merge_page on one of the rmap_items we would be removing.
-+ */
-+inline int unmerge_uksm_pages(struct vm_area_struct *vma,
-+		      unsigned long start, unsigned long end)
-+{
-+	unsigned long addr;
-+	int err = 0;
-+
-+	for (addr = start; addr < end && !err; addr += PAGE_SIZE) {
-+		if (uksm_test_exit(vma->vm_mm))
-+			break;
-+		if (signal_pending(current))
-+			err = -ERESTARTSYS;
-+		else
-+			err = break_ksm(vma, addr);
-+	}
-+	return err;
-+}
-+
-+static inline struct stable_node *folio_stable_node(struct folio *folio)
-+{
-+	return folio_test_ksm(folio) ? folio_raw_mapping(folio) : NULL;
-+}
-+
-+static inline void inc_uksm_pages_scanned(void)
-+{
-+	u64 delta;
-+
-+
-+	if (uksm_pages_scanned == U64_MAX) {
-+		encode_benefit();
-+
-+		delta = uksm_pages_scanned >> pages_scanned_base;
-+
-+		if (CAN_OVERFLOW_U64(pages_scanned_stored, delta)) {
-+			pages_scanned_stored >>= 1;
-+			delta >>= 1;
-+			pages_scanned_base++;
-+		}
-+
-+		pages_scanned_stored += delta;
-+
-+		uksm_pages_scanned = uksm_pages_scanned_last = 0;
-+	}
-+
-+	uksm_pages_scanned++;
-+}
-+
-+static inline int find_zero_page_hash(int strength, u32 hash)
-+{
-+	return (zero_hash_table[strength] == hash);
-+}
-+
-+static
-+int cmp_and_merge_zero_page(struct vm_area_struct *vma, struct page *page)
-+{
-+	struct page *zero_page = empty_uksm_zero_page;
-+	struct mm_struct *mm = vma->vm_mm;
-+	pte_t orig_pte = __pte(0);
-+	int err = -EFAULT;
-+
-+	if (uksm_test_exit(mm))
-+		goto out;
-+
-+	if (!trylock_page(page))
-+		goto out;
-+
-+	if (!PageAnon(page))
-+		goto out_unlock;
-+
-+	if (PageTransCompound(page)) {
-+		err = split_huge_page(page);
-+		if (err)
-+			goto out_unlock;
-+	}
-+
-+	if (write_protect_page(vma, page, &orig_pte, 0) == 0) {
-+		if (is_page_full_zero(page))
-+			err = replace_page(vma, page, zero_page, orig_pte);
-+	}
-+
-+out_unlock:
-+	unlock_page(page);
-+out:
-+	return err;
-+}
-+
-+/*
-+ * cmp_and_merge_page() - first see if page can be merged into the stable
-+ * tree; if not, compare hash to previous and if it's the same, see if page
-+ * can be inserted into the unstable tree, or merged with a page already there
-+ * and both transferred to the stable tree.
-+ *
-+ * @page: the page that we are searching identical page to.
-+ * @rmap_item: the reverse mapping into the virtual address of this page
-+ */
-+static void cmp_and_merge_page(struct rmap_item *rmap_item, u32 hash)
-+{
-+	struct rmap_item *tree_rmap_item;
-+	struct page *page;
-+	struct page *kpage = NULL;
-+	u32 hash_max;
-+	int err;
-+	unsigned int success1, success2;
-+	struct stable_node *snode;
-+	int cmp;
-+	struct rb_node *parent = NULL, **new;
-+
-+	remove_rmap_item_from_tree(rmap_item);
-+	page = rmap_item->page;
-+
-+	/* We first start with searching the page inside the stable tree */
-+	kpage = stable_tree_search(rmap_item, hash);
-+	if (kpage) {
-+		err = try_to_merge_with_uksm_page(rmap_item, kpage,
-+						 hash);
-+		if (!err) {
-+			/*
-+			 * The page was successfully merged, add
-+			 * its rmap_item to the stable tree.
-+			 * page lock is needed because it's
-+			 * racing with try_to_unmap_ksm(), etc.
-+			 */
-+			lock_page(kpage);
-+			snode = page_stable_node(kpage);
-+			stable_tree_append(rmap_item, snode, 1);
-+			unlock_page(kpage);
-+			put_page(kpage);
-+			return; /* success */
-+		}
-+		put_page(kpage);
-+
-+		/*
-+		 * if it's a collision and it has been search in sub-rbtree
-+		 * (hash_max != 0), we want to abort, because if it is
-+		 * successfully merged in unstable tree, the collision trends to
-+		 * happen again.
-+		 */
-+		if (err == MERGE_ERR_COLLI && rmap_item->hash_max)
-+			return;
-+	}
-+
-+	tree_rmap_item =
-+		unstable_tree_search_insert(rmap_item, hash);
-+	if (tree_rmap_item) {
-+		err = try_to_merge_two_pages(rmap_item, tree_rmap_item, hash);
-+		/*
-+		 * As soon as we merge this page, we want to remove the
-+		 * rmap_item of the page we have merged with from the unstable
-+		 * tree, and insert it instead as new node in the stable tree.
-+		 */
-+		if (!err) {
-+			kpage = page;
-+			remove_rmap_item_from_tree(tree_rmap_item);
-+			lock_page(kpage);
-+			snode = stable_tree_insert(&kpage, hash,
-+						   rmap_item, tree_rmap_item,
-+						   &success1, &success2);
-+
-+			/*
-+			 * Do not log dedup for tree item, it's not counted as
-+			 * scanned in this round.
-+			 */
-+			if (success2)
-+				stable_tree_append(tree_rmap_item, snode, 0);
-+
-+			/*
-+			 * The order of these two stable append is important:
-+			 * we are scanning rmap_item.
-+			 */
-+			if (success1)
-+				stable_tree_append(rmap_item, snode, 1);
-+
-+			/*
-+			 * The original kpage may be unlocked inside
-+			 * stable_tree_insert() already. This page
-+			 * should be unlocked before doing
-+			 * break_cow().
-+			 */
-+			unlock_page(kpage);
-+
-+			if (!success1)
-+				break_cow(rmap_item);
-+
-+			if (!success2)
-+				break_cow(tree_rmap_item);
-+
-+		} else if (err == MERGE_ERR_COLLI) {
-+			BUG_ON(tree_rmap_item->tree_node->count > 1);
-+
-+			rmap_item_hash_max(tree_rmap_item,
-+					   tree_rmap_item->tree_node->hash);
-+
-+			hash_max = rmap_item_hash_max(rmap_item, hash);
-+			cmp = hash_cmp(hash_max, tree_rmap_item->hash_max);
-+			parent = &tree_rmap_item->node;
-+			if (cmp < 0)
-+				new = &parent->rb_left;
-+			else if (cmp > 0)
-+				new = &parent->rb_right;
-+			else
-+				goto put_up_out;
-+
-+			rmap_item->tree_node = tree_rmap_item->tree_node;
-+			rmap_item->address |= UNSTABLE_FLAG;
-+			rmap_item->hash_round = uksm_hash_round;
-+			rb_link_node(&rmap_item->node, parent, new);
-+			rb_insert_color(&rmap_item->node,
-+					&tree_rmap_item->tree_node->sub_root);
-+			rmap_item->tree_node->count++;
-+		} else {
-+			/*
-+			 * either one of the page has changed or they collide
-+			 * at the max hash, we consider them as ill items.
-+			 */
-+			remove_rmap_item_from_tree(tree_rmap_item);
-+		}
-+put_up_out:
-+		put_page(tree_rmap_item->page);
-+		mmap_read_unlock(tree_rmap_item->slot->vma->vm_mm);
-+	}
-+}
-+
-+
-+
-+
-+static inline unsigned long get_pool_index(struct vma_slot *slot,
-+					   unsigned long index)
-+{
-+	unsigned long pool_index;
-+
-+	pool_index = (sizeof(struct rmap_list_entry *) * index) >> PAGE_SHIFT;
-+	if (pool_index >= slot->pool_size)
-+		BUG();
-+	return pool_index;
-+}
-+
-+static inline unsigned long index_page_offset(unsigned long index)
-+{
-+	return offset_in_page(sizeof(struct rmap_list_entry *) * index);
-+}
-+
-+static inline
-+struct rmap_list_entry *get_rmap_list_entry(struct vma_slot *slot,
-+					    unsigned long index, int need_alloc)
-+{
-+	unsigned long pool_index;
-+	struct page *page;
-+	void *addr;
-+
-+
-+	pool_index = get_pool_index(slot, index);
-+	if (!slot->rmap_list_pool[pool_index]) {
-+		if (!need_alloc)
-+			return NULL;
-+
-+		page = alloc_page(GFP_KERNEL | __GFP_ZERO | __GFP_NOWARN);
-+		if (!page)
-+			return NULL;
-+
-+		slot->rmap_list_pool[pool_index] = page;
-+	}
-+
-+	addr = kmap(slot->rmap_list_pool[pool_index]);
-+	addr += index_page_offset(index);
-+
-+	return addr;
-+}
-+
-+static inline void put_rmap_list_entry(struct vma_slot *slot,
-+				       unsigned long index)
-+{
-+	unsigned long pool_index;
-+
-+	pool_index = get_pool_index(slot, index);
-+	BUG_ON(!slot->rmap_list_pool[pool_index]);
-+	kunmap(slot->rmap_list_pool[pool_index]);
-+}
-+
-+static inline int entry_is_new(struct rmap_list_entry *entry)
-+{
-+	return !entry->item;
-+}
-+
-+static inline unsigned long get_index_orig_addr(struct vma_slot *slot,
-+						unsigned long index)
-+{
-+	return slot->vma->vm_start + (index << PAGE_SHIFT);
-+}
-+
-+static inline unsigned long get_entry_address(struct rmap_list_entry *entry)
-+{
-+	unsigned long addr;
-+
-+	if (is_addr(entry->addr))
-+		addr = get_clean_addr(entry->addr);
-+	else if (entry->item)
-+		addr = get_rmap_addr(entry->item);
-+	else
-+		BUG();
-+
-+	return addr;
-+}
-+
-+static inline struct rmap_item *get_entry_item(struct rmap_list_entry *entry)
-+{
-+	if (is_addr(entry->addr))
-+		return NULL;
-+
-+	return entry->item;
-+}
-+
-+static inline void inc_rmap_list_pool_count(struct vma_slot *slot,
-+					    unsigned long index)
-+{
-+	unsigned long pool_index;
-+
-+	pool_index = get_pool_index(slot, index);
-+	BUG_ON(!slot->rmap_list_pool[pool_index]);
-+	slot->pool_counts[pool_index]++;
-+}
-+
-+static inline void dec_rmap_list_pool_count(struct vma_slot *slot,
-+					    unsigned long index)
-+{
-+	unsigned long pool_index;
-+
-+	pool_index = get_pool_index(slot, index);
-+	BUG_ON(!slot->rmap_list_pool[pool_index]);
-+	BUG_ON(!slot->pool_counts[pool_index]);
-+	slot->pool_counts[pool_index]--;
-+}
-+
-+static inline int entry_has_rmap(struct rmap_list_entry *entry)
-+{
-+	return !is_addr(entry->addr) && entry->item;
-+}
-+
-+static inline void swap_entries(struct rmap_list_entry *entry1,
-+				unsigned long index1,
-+				struct rmap_list_entry *entry2,
-+				unsigned long index2)
-+{
-+	struct rmap_list_entry tmp;
-+
-+	/* swapping two new entries is meaningless */
-+	BUG_ON(entry_is_new(entry1) && entry_is_new(entry2));
-+
-+	tmp = *entry1;
-+	*entry1 = *entry2;
-+	*entry2 = tmp;
-+
-+	if (entry_has_rmap(entry1))
-+		entry1->item->entry_index = index1;
-+
-+	if (entry_has_rmap(entry2))
-+		entry2->item->entry_index = index2;
-+
-+	if (entry_has_rmap(entry1) && !entry_has_rmap(entry2)) {
-+		inc_rmap_list_pool_count(entry1->item->slot, index1);
-+		dec_rmap_list_pool_count(entry1->item->slot, index2);
-+	} else if (!entry_has_rmap(entry1) && entry_has_rmap(entry2)) {
-+		inc_rmap_list_pool_count(entry2->item->slot, index2);
-+		dec_rmap_list_pool_count(entry2->item->slot, index1);
-+	}
-+}
-+
-+static inline void free_entry_item(struct rmap_list_entry *entry)
-+{
-+	unsigned long index;
-+	struct rmap_item *item;
-+
-+	if (!is_addr(entry->addr)) {
-+		BUG_ON(!entry->item);
-+		item = entry->item;
-+		entry->addr = get_rmap_addr(item);
-+		set_is_addr(entry->addr);
-+		index = item->entry_index;
-+		remove_rmap_item_from_tree(item);
-+		dec_rmap_list_pool_count(item->slot, index);
-+		free_rmap_item(item);
-+	}
-+}
-+
-+static inline int pool_entry_boundary(unsigned long index)
-+{
-+	unsigned long linear_addr;
-+
-+	linear_addr = sizeof(struct rmap_list_entry *) * index;
-+	return index && !offset_in_page(linear_addr);
-+}
-+
-+static inline void try_free_last_pool(struct vma_slot *slot,
-+				      unsigned long index)
-+{
-+	unsigned long pool_index;
-+
-+	pool_index = get_pool_index(slot, index);
-+	if (slot->rmap_list_pool[pool_index] &&
-+	    !slot->pool_counts[pool_index]) {
-+		__free_page(slot->rmap_list_pool[pool_index]);
-+		slot->rmap_list_pool[pool_index] = NULL;
-+		slot->flags |= UKSM_SLOT_NEED_SORT;
-+	}
-+
-+}
-+
-+static inline unsigned long vma_item_index(struct vm_area_struct *vma,
-+					   struct rmap_item *item)
-+{
-+	return (get_rmap_addr(item) - vma->vm_start) >> PAGE_SHIFT;
-+}
-+
-+static int within_same_pool(struct vma_slot *slot,
-+			    unsigned long i, unsigned long j)
-+{
-+	unsigned long pool_i, pool_j;
-+
-+	pool_i = get_pool_index(slot, i);
-+	pool_j = get_pool_index(slot, j);
-+
-+	return (pool_i == pool_j);
-+}
-+
-+static void sort_rmap_entry_list(struct vma_slot *slot)
-+{
-+	unsigned long i, j;
-+	struct rmap_list_entry *entry, *swap_entry;
-+
-+	entry = get_rmap_list_entry(slot, 0, 0);
-+	for (i = 0; i < slot->pages; ) {
-+
-+		if (!entry)
-+			goto skip_whole_pool;
-+
-+		if (entry_is_new(entry))
-+			goto next_entry;
-+
-+		if (is_addr(entry->addr)) {
-+			entry->addr = 0;
-+			goto next_entry;
-+		}
-+
-+		j = vma_item_index(slot->vma, entry->item);
-+		if (j == i)
-+			goto next_entry;
-+
-+		if (within_same_pool(slot, i, j))
-+			swap_entry = entry + j - i;
-+		else
-+			swap_entry = get_rmap_list_entry(slot, j, 1);
-+
-+		swap_entries(entry, i, swap_entry, j);
-+		if (!within_same_pool(slot, i, j))
-+			put_rmap_list_entry(slot, j);
-+		continue;
-+
-+skip_whole_pool:
-+		i += PAGE_SIZE / sizeof(*entry);
-+		if (i < slot->pages)
-+			entry = get_rmap_list_entry(slot, i, 0);
-+		continue;
-+
-+next_entry:
-+		if (i >= slot->pages - 1 ||
-+		    !within_same_pool(slot, i, i + 1)) {
-+			put_rmap_list_entry(slot, i);
-+			if (i + 1 < slot->pages)
-+				entry = get_rmap_list_entry(slot, i + 1, 0);
-+		} else
-+			entry++;
-+		i++;
-+		continue;
-+	}
-+
-+	/* free empty pool entries which contain no rmap_item */
-+	/* CAN be simplied to based on only pool_counts when bug freed !!!!! */
-+	for (i = 0; i < slot->pool_size; i++) {
-+		unsigned char has_rmap;
-+		void *addr;
-+
-+		if (!slot->rmap_list_pool[i])
-+			continue;
-+
-+		has_rmap = 0;
-+		addr = kmap(slot->rmap_list_pool[i]);
-+		BUG_ON(!addr);
-+		for (j = 0; j < PAGE_SIZE / sizeof(*entry); j++) {
-+			entry = (struct rmap_list_entry *)addr + j;
-+			if (is_addr(entry->addr))
-+				continue;
-+			if (!entry->item)
-+				continue;
-+			has_rmap = 1;
-+		}
-+		kunmap(slot->rmap_list_pool[i]);
-+		if (!has_rmap) {
-+			BUG_ON(slot->pool_counts[i]);
-+			__free_page(slot->rmap_list_pool[i]);
-+			slot->rmap_list_pool[i] = NULL;
-+		}
-+	}
-+
-+	slot->flags &= ~UKSM_SLOT_NEED_SORT;
-+}
-+
-+/*
-+ * vma_fully_scanned() - if all the pages in this slot have been scanned.
-+ */
-+static inline int vma_fully_scanned(struct vma_slot *slot)
-+{
-+	return slot->pages_scanned == slot->pages;
-+}
-+
-+/**
-+ * get_next_rmap_item() - Get the next rmap_item in a vma_slot according to
-+ * its random permutation. This function is embedded with the random
-+ * permutation index management code.
-+ */
-+static struct rmap_item *get_next_rmap_item(struct vma_slot *slot, u32 *hash)
-+{
-+	unsigned long rand_range, addr, swap_index, scan_index;
-+	struct rmap_item *item = NULL;
-+	struct rmap_list_entry *scan_entry, *swap_entry = NULL;
-+	struct page *page;
-+
-+	scan_index = swap_index = slot->pages_scanned % slot->pages;
-+
-+	if (pool_entry_boundary(scan_index))
-+		try_free_last_pool(slot, scan_index - 1);
-+
-+	if (vma_fully_scanned(slot)) {
-+		if (slot->flags & UKSM_SLOT_NEED_SORT)
-+			slot->flags |= UKSM_SLOT_NEED_RERAND;
-+		else
-+			slot->flags &= ~UKSM_SLOT_NEED_RERAND;
-+		if (slot->flags & UKSM_SLOT_NEED_SORT)
-+			sort_rmap_entry_list(slot);
-+	}
-+
-+	scan_entry = get_rmap_list_entry(slot, scan_index, 1);
-+	if (!scan_entry)
-+		return NULL;
-+
-+	if (entry_is_new(scan_entry)) {
-+		scan_entry->addr = get_index_orig_addr(slot, scan_index);
-+		set_is_addr(scan_entry->addr);
-+	}
-+
-+	if (slot->flags & UKSM_SLOT_NEED_RERAND) {
-+		rand_range = slot->pages - scan_index;
-+		BUG_ON(!rand_range);
-+		swap_index = scan_index + (prandom_u32() % rand_range);
-+	}
-+
-+	if (swap_index != scan_index) {
-+		swap_entry = get_rmap_list_entry(slot, swap_index, 1);
-+
-+		if (!swap_entry)
-+			return NULL;
-+
-+		if (entry_is_new(swap_entry)) {
-+			swap_entry->addr = get_index_orig_addr(slot,
-+							       swap_index);
-+			set_is_addr(swap_entry->addr);
-+		}
-+		swap_entries(scan_entry, scan_index, swap_entry, swap_index);
-+	}
-+
-+	addr = get_entry_address(scan_entry);
-+	item = get_entry_item(scan_entry);
-+	BUG_ON(addr > slot->vma->vm_end || addr < slot->vma->vm_start);
-+
-+	page = follow_page(slot->vma, addr, FOLL_GET);
-+	if (IS_ERR_OR_NULL(page))
-+		goto nopage;
-+
-+	if (!PageAnon(page))
-+		goto putpage;
-+
-+	/*check is zero_page pfn or uksm_zero_page*/
-+	if ((page_to_pfn(page) == zero_pfn)
-+			|| (page_to_pfn(page) == uksm_zero_pfn))
-+		goto putpage;
-+
-+	flush_anon_page(slot->vma, page, addr);
-+	flush_dcache_page(page);
-+
-+
-+	*hash = page_hash(page, hash_strength, 1);
-+	inc_uksm_pages_scanned();
-+	/*if the page content all zero, re-map to zero-page*/
-+	if (find_zero_page_hash(hash_strength, *hash)) {
-+		if (!cmp_and_merge_zero_page(slot->vma, page)) {
-+			slot->pages_merged++;
-+
-+			/* For full-zero pages, no need to create rmap item */
-+			goto putpage;
-+		} else {
-+			inc_rshash_neg(memcmp_cost / 2);
-+		}
-+	}
-+
-+	if (!item) {
-+		item = alloc_rmap_item();
-+		if (item) {
-+			/* It has already been zeroed */
-+			item->slot = slot;
-+			item->address = addr;
-+			item->entry_index = scan_index;
-+			scan_entry->item = item;
-+			inc_rmap_list_pool_count(slot, scan_index);
-+		} else
-+			goto putpage;
-+	}
-+
-+	BUG_ON(item->slot != slot);
-+	/* the page may have changed */
-+	item->page = page;
-+	put_rmap_list_entry(slot, scan_index);
-+	if (swap_entry)
-+		put_rmap_list_entry(slot, swap_index);
-+	return item;
-+
-+putpage:
-+	put_page(page);
-+	page = NULL;
-+nopage:
-+	/* no page, store addr back and free rmap_item if possible */
-+	free_entry_item(scan_entry);
-+	put_rmap_list_entry(slot, scan_index);
-+	if (swap_entry)
-+		put_rmap_list_entry(slot, swap_index);
-+	return NULL;
-+}
-+
-+static inline int in_stable_tree(struct rmap_item *rmap_item)
-+{
-+	return rmap_item->address & STABLE_FLAG;
-+}
-+
-+/**
-+ * scan_vma_one_page() - scan the next page in a vma_slot. Called with
-+ * mmap_sem locked.
-+ */
-+static noinline void scan_vma_one_page(struct vma_slot *slot)
-+{
-+	u32 hash;
-+	struct mm_struct *mm;
-+	struct rmap_item *rmap_item = NULL;
-+	struct vm_area_struct *vma = slot->vma;
-+
-+	mm = vma->vm_mm;
-+	BUG_ON(!mm);
-+	BUG_ON(!slot);
-+
-+	rmap_item = get_next_rmap_item(slot, &hash);
-+	if (!rmap_item)
-+		goto out1;
-+
-+	if (PageKsm(rmap_item->page) && in_stable_tree(rmap_item))
-+		goto out2;
-+
-+	cmp_and_merge_page(rmap_item, hash);
-+out2:
-+	put_page(rmap_item->page);
-+out1:
-+	slot->pages_scanned++;
-+	slot->this_sampled++;
-+	if (slot->fully_scanned_round != fully_scanned_round)
-+		scanned_virtual_pages++;
-+
-+	if (vma_fully_scanned(slot))
-+		slot->fully_scanned_round = fully_scanned_round;
-+}
-+
-+static inline unsigned long rung_get_pages(struct scan_rung *rung)
-+{
-+	struct slot_tree_node *node;
-+
-+	if (!rung->vma_root.rnode)
-+		return 0;
-+
-+	node = container_of(rung->vma_root.rnode, struct slot_tree_node, snode);
-+
-+	return node->size;
-+}
-+
-+#define RUNG_SAMPLED_MIN	3
-+
-+static inline
-+void uksm_calc_rung_step(struct scan_rung *rung,
-+			 unsigned long page_time, unsigned long ratio)
-+{
-+	unsigned long sampled, pages;
-+
-+	/* will be fully scanned ? */
-+	if (!rung->cover_msecs) {
-+		rung->step = 1;
-+		return;
-+	}
-+
-+	sampled = rung->cover_msecs * (NSEC_PER_MSEC / TIME_RATIO_SCALE)
-+		  * ratio / page_time;
-+
-+	/*
-+	 *  Before we finsish a scan round and expensive per-round jobs,
-+	 *  we need to have a chance to estimate the per page time. So
-+	 *  the sampled number can not be too small.
-+	 */
-+	if (sampled < RUNG_SAMPLED_MIN)
-+		sampled = RUNG_SAMPLED_MIN;
-+
-+	pages = rung_get_pages(rung);
-+	if (likely(pages > sampled))
-+		rung->step = pages / sampled;
-+	else
-+		rung->step = 1;
-+}
-+
-+static inline int step_need_recalc(struct scan_rung *rung)
-+{
-+	unsigned long pages, stepmax;
-+
-+	pages = rung_get_pages(rung);
-+	stepmax = pages / RUNG_SAMPLED_MIN;
-+
-+	return pages && (rung->step > pages ||
-+			 (stepmax && rung->step > stepmax));
-+}
-+
-+static inline
-+void reset_current_scan(struct scan_rung *rung, int finished, int step_recalc)
-+{
-+	struct vma_slot *slot;
-+
-+	if (finished)
-+		rung->flags |= UKSM_RUNG_ROUND_FINISHED;
-+
-+	if (step_recalc || step_need_recalc(rung)) {
-+		uksm_calc_rung_step(rung, uksm_ema_page_time, rung->cpu_ratio);
-+		BUG_ON(step_need_recalc(rung));
-+	}
-+
-+	slot_iter_index = prandom_u32() % rung->step;
-+	BUG_ON(!rung->vma_root.rnode);
-+	slot = sradix_tree_next(&rung->vma_root, NULL, 0, slot_iter);
-+	BUG_ON(!slot);
-+
-+	rung->current_scan = slot;
-+	rung->current_offset = slot_iter_index;
-+}
-+
-+static inline struct sradix_tree_root *slot_get_root(struct vma_slot *slot)
-+{
-+	return &slot->rung->vma_root;
-+}
-+
-+/*
-+ * return if resetted.
-+ */
-+static int advance_current_scan(struct scan_rung *rung)
-+{
-+	unsigned short n;
-+	struct vma_slot *slot, *next = NULL;
-+
-+	BUG_ON(!rung->vma_root.num);
-+
-+	slot = rung->current_scan;
-+	n = (slot->pages - rung->current_offset) % rung->step;
-+	slot_iter_index = rung->step - n;
-+	next = sradix_tree_next(&rung->vma_root, slot->snode,
-+				slot->sindex, slot_iter);
-+
-+	if (next) {
-+		rung->current_offset = slot_iter_index;
-+		rung->current_scan = next;
-+		return 0;
-+	} else {
-+		reset_current_scan(rung, 1, 0);
-+		return 1;
-+	}
-+}
-+
-+static inline void rung_rm_slot(struct vma_slot *slot)
-+{
-+	struct scan_rung *rung = slot->rung;
-+	struct sradix_tree_root *root;
-+
-+	if (rung->current_scan == slot)
-+		advance_current_scan(rung);
-+
-+	root = slot_get_root(slot);
-+	sradix_tree_delete_from_leaf(root, slot->snode, slot->sindex);
-+	slot->snode = NULL;
-+	if (step_need_recalc(rung)) {
-+		uksm_calc_rung_step(rung, uksm_ema_page_time, rung->cpu_ratio);
-+		BUG_ON(step_need_recalc(rung));
-+	}
-+
-+	/* In case advance_current_scan loop back to this slot again */
-+	if (rung->vma_root.num && rung->current_scan == slot)
-+		reset_current_scan(slot->rung, 1, 0);
-+}
-+
-+static inline void rung_add_new_slots(struct scan_rung *rung,
-+			struct vma_slot **slots, unsigned long num)
-+{
-+	int err;
-+	struct vma_slot *slot;
-+	unsigned long i;
-+	struct sradix_tree_root *root = &rung->vma_root;
-+
-+	err = sradix_tree_enter(root, (void **)slots, num);
-+	BUG_ON(err);
-+
-+	for (i = 0; i < num; i++) {
-+		slot = slots[i];
-+		slot->rung = rung;
-+		BUG_ON(vma_fully_scanned(slot));
-+	}
-+
-+	if (rung->vma_root.num == num)
-+		reset_current_scan(rung, 0, 1);
-+}
-+
-+static inline int rung_add_one_slot(struct scan_rung *rung,
-+				     struct vma_slot *slot)
-+{
-+	int err;
-+
-+	err = sradix_tree_enter(&rung->vma_root, (void **)&slot, 1);
-+	if (err)
-+		return err;
-+
-+	slot->rung = rung;
-+	if (rung->vma_root.num == 1)
-+		reset_current_scan(rung, 0, 1);
-+
-+	return 0;
-+}
-+
-+/*
-+ * Return true if the slot is deleted from its rung.
-+ */
-+static inline int vma_rung_enter(struct vma_slot *slot, struct scan_rung *rung)
-+{
-+	struct scan_rung *old_rung = slot->rung;
-+	int err;
-+
-+	if (old_rung == rung)
-+		return 0;
-+
-+	rung_rm_slot(slot);
-+	err = rung_add_one_slot(rung, slot);
-+	if (err) {
-+		err = rung_add_one_slot(old_rung, slot);
-+		WARN_ON(err); /* OOPS, badly OOM, we lost this slot */
-+	}
-+
-+	return 1;
-+}
-+
-+static inline int vma_rung_up(struct vma_slot *slot)
-+{
-+	struct scan_rung *rung;
-+
-+	rung = slot->rung;
-+	if (slot->rung != &uksm_scan_ladder[SCAN_LADDER_SIZE-1])
-+		rung++;
-+
-+	return vma_rung_enter(slot, rung);
-+}
-+
-+static inline int vma_rung_down(struct vma_slot *slot)
-+{
-+	struct scan_rung *rung;
-+
-+	rung = slot->rung;
-+	if (slot->rung != &uksm_scan_ladder[0])
-+		rung--;
-+
-+	return vma_rung_enter(slot, rung);
-+}
-+
-+/**
-+ * cal_dedup_ratio() - Calculate the deduplication ratio for this slot.
-+ */
-+static unsigned long cal_dedup_ratio(struct vma_slot *slot)
-+{
-+	unsigned long ret;
-+	unsigned long pages;
-+
-+	pages = slot->this_sampled;
-+	if (!pages)
-+		return 0;
-+
-+	BUG_ON(slot->pages_scanned == slot->last_scanned);
-+
-+	ret = slot->pages_merged;
-+
-+	/* Thrashing area filtering */
-+	if (ret && uksm_thrash_threshold) {
-+		if (slot->pages_cowed * 100 / slot->pages_merged
-+		    > uksm_thrash_threshold) {
-+			ret = 0;
-+		} else {
-+			ret = slot->pages_merged - slot->pages_cowed;
-+		}
-+	}
-+
-+	return ret * 100 / pages;
-+}
-+
-+/**
-+ * cal_dedup_ratio() - Calculate the deduplication ratio for this slot.
-+ */
-+static unsigned long cal_dedup_ratio_old(struct vma_slot *slot)
-+{
-+	unsigned long ret;
-+	unsigned long pages;
-+
-+	pages = slot->pages;
-+	if (!pages)
-+		return 0;
-+
-+	ret = slot->pages_bemerged;
-+
-+	/* Thrashing area filtering */
-+	if (ret && uksm_thrash_threshold) {
-+		if (slot->pages_cowed * 100 / slot->pages_bemerged
-+		    > uksm_thrash_threshold) {
-+			ret = 0;
-+		} else {
-+			ret = slot->pages_bemerged - slot->pages_cowed;
-+		}
-+	}
-+
-+	return ret * 100 / pages;
-+}
-+
-+/**
-+ * stable_node_reinsert() - When the hash_strength has been adjusted, the
-+ * stable tree need to be restructured, this is the function re-inserting the
-+ * stable node.
-+ */
-+static inline void stable_node_reinsert(struct stable_node *new_node,
-+					struct page *page,
-+					struct rb_root *root_treep,
-+					struct list_head *tree_node_listp,
-+					u32 hash)
-+{
-+	struct rb_node **new = &root_treep->rb_node;
-+	struct rb_node *parent = NULL;
-+	struct stable_node *stable_node;
-+	struct tree_node *tree_node;
-+	struct page *tree_page;
-+	int cmp;
-+
-+	while (*new) {
-+		int cmp;
-+
-+		tree_node = rb_entry(*new, struct tree_node, node);
-+
-+		cmp = hash_cmp(hash, tree_node->hash);
-+
-+		if (cmp < 0) {
-+			parent = *new;
-+			new = &parent->rb_left;
-+		} else if (cmp > 0) {
-+			parent = *new;
-+			new = &parent->rb_right;
-+		} else
-+			break;
-+	}
-+
-+	if (*new) {
-+		/* find a stable tree node with same first level hash value */
-+		stable_node_hash_max(new_node, page, hash);
-+		if (tree_node->count == 1) {
-+			stable_node = rb_entry(tree_node->sub_root.rb_node,
-+					       struct stable_node, node);
-+			tree_page = get_uksm_page(stable_node, 1, 0);
-+			if (tree_page) {
-+				stable_node_hash_max(stable_node,
-+						      tree_page, hash);
-+				put_page(tree_page);
-+
-+				/* prepare for stable node insertion */
-+
-+				cmp = hash_cmp(new_node->hash_max,
-+						   stable_node->hash_max);
-+				parent = &stable_node->node;
-+				if (cmp < 0)
-+					new = &parent->rb_left;
-+				else if (cmp > 0)
-+					new = &parent->rb_right;
-+				else
-+					goto failed;
-+
-+				goto add_node;
-+			} else {
-+				/* the only stable_node deleted, the tree node
-+				 * was not deleted.
-+				 */
-+				goto tree_node_reuse;
-+			}
-+		}
-+
-+		/* well, search the collision subtree */
-+		new = &tree_node->sub_root.rb_node;
-+		parent = NULL;
-+		BUG_ON(!*new);
-+		while (*new) {
-+			int cmp;
-+
-+			stable_node = rb_entry(*new, struct stable_node, node);
-+
-+			cmp = hash_cmp(new_node->hash_max,
-+					   stable_node->hash_max);
-+
-+			if (cmp < 0) {
-+				parent = *new;
-+				new = &parent->rb_left;
-+			} else if (cmp > 0) {
-+				parent = *new;
-+				new = &parent->rb_right;
-+			} else {
-+				/* oh, no, still a collision */
-+				goto failed;
-+			}
-+		}
-+
-+		goto add_node;
-+	}
-+
-+	/* no tree node found */
-+	tree_node = alloc_tree_node(tree_node_listp);
-+	if (!tree_node) {
-+		pr_err("UKSM: memory allocation error!\n");
-+		goto failed;
-+	} else {
-+		tree_node->hash = hash;
-+		rb_link_node(&tree_node->node, parent, new);
-+		rb_insert_color(&tree_node->node, root_treep);
-+
-+tree_node_reuse:
-+		/* prepare for stable node insertion */
-+		parent = NULL;
-+		new = &tree_node->sub_root.rb_node;
-+	}
-+
-+add_node:
-+	rb_link_node(&new_node->node, parent, new);
-+	rb_insert_color(&new_node->node, &tree_node->sub_root);
-+	new_node->tree_node = tree_node;
-+	tree_node->count++;
-+	return;
-+
-+failed:
-+	/* This can only happen when two nodes have collided
-+	 * in two levels.
-+	 */
-+	new_node->tree_node = NULL;
-+	return;
-+}
-+
-+static inline void free_all_tree_nodes(struct list_head *list)
-+{
-+	struct tree_node *node, *tmp;
-+
-+	list_for_each_entry_safe(node, tmp, list, all_list) {
-+		free_tree_node(node);
-+	}
-+}
-+
-+/**
-+ * stable_tree_delta_hash() - Delta hash the stable tree from previous hash
-+ * strength to the current hash_strength. It re-structures the hole tree.
-+ */
-+static inline void stable_tree_delta_hash(u32 prev_hash_strength)
-+{
-+	struct stable_node *node, *tmp;
-+	struct rb_root *root_new_treep;
-+	struct list_head *new_tree_node_listp;
-+
-+	stable_tree_index = (stable_tree_index + 1) % 2;
-+	root_new_treep = &root_stable_tree[stable_tree_index];
-+	new_tree_node_listp = &stable_tree_node_list[stable_tree_index];
-+	*root_new_treep = RB_ROOT;
-+	BUG_ON(!list_empty(new_tree_node_listp));
-+
-+	/*
-+	 * we need to be safe, the node could be removed by get_uksm_page()
-+	 */
-+	list_for_each_entry_safe(node, tmp, &stable_node_list, all_list) {
-+		void *addr;
-+		struct page *node_page;
-+		u32 hash;
-+
-+		/*
-+		 * We are completely re-structuring the stable nodes to a new
-+		 * stable tree. We don't want to touch the old tree unlinks and
-+		 * old tree_nodes. The old tree_nodes will be freed at once.
-+		 */
-+		node_page = get_uksm_page(node, 0, 0);
-+		if (!node_page)
-+			continue;
-+
-+		if (node->tree_node) {
-+			hash = node->tree_node->hash;
-+
-+			addr = kmap_atomic(node_page);
-+
-+			hash = delta_hash(addr, prev_hash_strength,
-+					  hash_strength, hash);
-+			kunmap_atomic(addr);
-+		} else {
-+			/*
-+			 *it was not inserted to rbtree due to collision in last
-+			 *round scan.
-+			 */
-+			hash = page_hash(node_page, hash_strength, 0);
-+		}
-+
-+		stable_node_reinsert(node, node_page, root_new_treep,
-+				     new_tree_node_listp, hash);
-+		put_page(node_page);
-+	}
-+
-+	root_stable_treep = root_new_treep;
-+	free_all_tree_nodes(stable_tree_node_listp);
-+	BUG_ON(!list_empty(stable_tree_node_listp));
-+	stable_tree_node_listp = new_tree_node_listp;
-+}
-+
-+static inline void inc_hash_strength(unsigned long delta)
-+{
-+	hash_strength += 1 << delta;
-+	if (hash_strength > HASH_STRENGTH_MAX)
-+		hash_strength = HASH_STRENGTH_MAX;
-+}
-+
-+static inline void dec_hash_strength(unsigned long delta)
-+{
-+	unsigned long change = 1 << delta;
-+
-+	if (hash_strength <= change + 1)
-+		hash_strength = 1;
-+	else
-+		hash_strength -= change;
-+}
-+
-+static inline void inc_hash_strength_delta(void)
-+{
-+	hash_strength_delta++;
-+	if (hash_strength_delta > HASH_STRENGTH_DELTA_MAX)
-+		hash_strength_delta = HASH_STRENGTH_DELTA_MAX;
-+}
-+
-+static inline unsigned long get_current_neg_ratio(void)
-+{
-+	u64 pos = benefit.pos;
-+	u64 neg = benefit.neg;
-+
-+	if (!neg)
-+		return 0;
-+
-+	if (!pos || neg > pos)
-+		return 100;
-+
-+	if (neg > div64_u64(U64_MAX, 100))
-+		pos = div64_u64(pos, 100);
-+	else
-+		neg *= 100;
-+
-+	return div64_u64(neg, pos);
-+}
-+
-+static inline unsigned long get_current_benefit(void)
-+{
-+	u64 pos = benefit.pos;
-+	u64 neg = benefit.neg;
-+	u64 scanned = benefit.scanned;
-+
-+	if (neg > pos)
-+		return 0;
-+
-+	return div64_u64((pos - neg), scanned);
-+}
-+
-+static inline int judge_rshash_direction(void)
-+{
-+	u64 current_neg_ratio, stable_benefit;
-+	u64 current_benefit, delta = 0;
-+	int ret = STILL;
-+
-+	/*
-+	 * Try to probe a value after the boot, and in case the system
-+	 * are still for a long time.
-+	 */
-+	if ((fully_scanned_round & 0xFFULL) == 10) {
-+		ret = OBSCURE;
-+		goto out;
-+	}
-+
-+	current_neg_ratio = get_current_neg_ratio();
-+
-+	if (current_neg_ratio == 0) {
-+		rshash_neg_cont_zero++;
-+		if (rshash_neg_cont_zero > 2)
-+			return GO_DOWN;
-+		else
-+			return STILL;
-+	}
-+	rshash_neg_cont_zero = 0;
-+
-+	if (current_neg_ratio > 90) {
-+		ret = GO_UP;
-+		goto out;
-+	}
-+
-+	current_benefit = get_current_benefit();
-+	stable_benefit = rshash_state.stable_benefit;
-+
-+	if (!stable_benefit) {
-+		ret = OBSCURE;
-+		goto out;
-+	}
-+
-+	if (current_benefit > stable_benefit)
-+		delta = current_benefit - stable_benefit;
-+	else if (current_benefit < stable_benefit)
-+		delta = stable_benefit - current_benefit;
-+
-+	delta = div64_u64(100 * delta, stable_benefit);
-+
-+	if (delta > 50) {
-+		rshash_cont_obscure++;
-+		if (rshash_cont_obscure > 2)
-+			return OBSCURE;
-+		else
-+			return STILL;
-+	}
-+
-+out:
-+	rshash_cont_obscure = 0;
-+	return ret;
-+}
-+
-+/**
-+ * rshash_adjust() - The main function to control the random sampling state
-+ * machine for hash strength adapting.
-+ *
-+ * return true if hash_strength has changed.
-+ */
-+static inline int rshash_adjust(void)
-+{
-+	unsigned long prev_hash_strength = hash_strength;
-+
-+	if (!encode_benefit())
-+		return 0;
-+
-+	switch (rshash_state.state) {
-+	case RSHASH_STILL:
-+		switch (judge_rshash_direction()) {
-+		case GO_UP:
-+			if (rshash_state.pre_direct == GO_DOWN)
-+				hash_strength_delta = 0;
-+
-+			inc_hash_strength(hash_strength_delta);
-+			inc_hash_strength_delta();
-+			rshash_state.stable_benefit = get_current_benefit();
-+			rshash_state.pre_direct = GO_UP;
-+			break;
-+
-+		case GO_DOWN:
-+			if (rshash_state.pre_direct == GO_UP)
-+				hash_strength_delta = 0;
-+
-+			dec_hash_strength(hash_strength_delta);
-+			inc_hash_strength_delta();
-+			rshash_state.stable_benefit = get_current_benefit();
-+			rshash_state.pre_direct = GO_DOWN;
-+			break;
-+
-+		case OBSCURE:
-+			rshash_state.stable_point = hash_strength;
-+			rshash_state.turn_point_down = hash_strength;
-+			rshash_state.turn_point_up = hash_strength;
-+			rshash_state.turn_benefit_down = get_current_benefit();
-+			rshash_state.turn_benefit_up = get_current_benefit();
-+			rshash_state.lookup_window_index = 0;
-+			rshash_state.state = RSHASH_TRYDOWN;
-+			dec_hash_strength(hash_strength_delta);
-+			inc_hash_strength_delta();
-+			break;
-+
-+		case STILL:
-+			break;
-+		default:
-+			BUG();
-+		}
-+		break;
-+
-+	case RSHASH_TRYDOWN:
-+		if (rshash_state.lookup_window_index++ % 5 == 0)
-+			rshash_state.below_count = 0;
-+
-+		if (get_current_benefit() < rshash_state.stable_benefit)
-+			rshash_state.below_count++;
-+		else if (get_current_benefit() >
-+			 rshash_state.turn_benefit_down) {
-+			rshash_state.turn_point_down = hash_strength;
-+			rshash_state.turn_benefit_down = get_current_benefit();
-+		}
-+
-+		if (rshash_state.below_count >= 3 ||
-+		    judge_rshash_direction() == GO_UP ||
-+		    hash_strength == 1) {
-+			hash_strength = rshash_state.stable_point;
-+			hash_strength_delta = 0;
-+			inc_hash_strength(hash_strength_delta);
-+			inc_hash_strength_delta();
-+			rshash_state.lookup_window_index = 0;
-+			rshash_state.state = RSHASH_TRYUP;
-+			hash_strength_delta = 0;
-+		} else {
-+			dec_hash_strength(hash_strength_delta);
-+			inc_hash_strength_delta();
-+		}
-+		break;
-+
-+	case RSHASH_TRYUP:
-+		if (rshash_state.lookup_window_index++ % 5 == 0)
-+			rshash_state.below_count = 0;
-+
-+		if (get_current_benefit() < rshash_state.turn_benefit_down)
-+			rshash_state.below_count++;
-+		else if (get_current_benefit() > rshash_state.turn_benefit_up) {
-+			rshash_state.turn_point_up = hash_strength;
-+			rshash_state.turn_benefit_up = get_current_benefit();
-+		}
-+
-+		if (rshash_state.below_count >= 3 ||
-+		    judge_rshash_direction() == GO_DOWN ||
-+		    hash_strength == HASH_STRENGTH_MAX) {
-+			hash_strength = rshash_state.turn_benefit_up >
-+				rshash_state.turn_benefit_down ?
-+				rshash_state.turn_point_up :
-+				rshash_state.turn_point_down;
-+
-+			rshash_state.state = RSHASH_PRE_STILL;
-+		} else {
-+			inc_hash_strength(hash_strength_delta);
-+			inc_hash_strength_delta();
-+		}
-+
-+		break;
-+
-+	case RSHASH_NEW:
-+	case RSHASH_PRE_STILL:
-+		rshash_state.stable_benefit = get_current_benefit();
-+		rshash_state.state = RSHASH_STILL;
-+		hash_strength_delta = 0;
-+		break;
-+	default:
-+		BUG();
-+	}
-+
-+	/* rshash_neg = rshash_pos = 0; */
-+	reset_benefit();
-+
-+	if (prev_hash_strength != hash_strength)
-+		stable_tree_delta_hash(prev_hash_strength);
-+
-+	return prev_hash_strength != hash_strength;
-+}
-+
-+/**
-+ * round_update_ladder() - The main function to do update of all the
-+ * adjustments whenever a scan round is finished.
-+ */
-+static noinline void round_update_ladder(void)
-+{
-+	int i;
-+	unsigned long dedup;
-+	struct vma_slot *slot, *tmp_slot;
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++)
-+		uksm_scan_ladder[i].flags &= ~UKSM_RUNG_ROUND_FINISHED;
-+
-+	list_for_each_entry_safe(slot, tmp_slot, &vma_slot_dedup, dedup_list) {
-+
-+		/* slot may be rung_rm_slot() when mm exits */
-+		if (slot->snode) {
-+			dedup = cal_dedup_ratio_old(slot);
-+			if (dedup && dedup >= uksm_abundant_threshold)
-+				vma_rung_up(slot);
-+		}
-+
-+		slot->pages_bemerged = 0;
-+		slot->pages_cowed = 0;
-+
-+		list_del_init(&slot->dedup_list);
-+	}
-+}
-+
-+static void uksm_del_vma_slot(struct vma_slot *slot)
-+{
-+	int i, j;
-+	struct rmap_list_entry *entry;
-+
-+	if (slot->snode) {
-+		/*
-+		 * In case it just failed when entering the rung, it's not
-+		 * necessary.
-+		 */
-+		rung_rm_slot(slot);
-+	}
-+
-+	if (!list_empty(&slot->dedup_list))
-+		list_del(&slot->dedup_list);
-+
-+	if (!slot->rmap_list_pool || !slot->pool_counts) {
-+		/* In case it OOMed in uksm_vma_enter() */
-+		goto out;
-+	}
-+
-+	for (i = 0; i < slot->pool_size; i++) {
-+		void *addr;
-+
-+		if (!slot->rmap_list_pool[i])
-+			continue;
-+
-+		addr = kmap(slot->rmap_list_pool[i]);
-+		for (j = 0; j < PAGE_SIZE / sizeof(*entry); j++) {
-+			entry = (struct rmap_list_entry *)addr + j;
-+			if (is_addr(entry->addr))
-+				continue;
-+			if (!entry->item)
-+				continue;
-+
-+			remove_rmap_item_from_tree(entry->item);
-+			free_rmap_item(entry->item);
-+			slot->pool_counts[i]--;
-+		}
-+		BUG_ON(slot->pool_counts[i]);
-+		kunmap(slot->rmap_list_pool[i]);
-+		__free_page(slot->rmap_list_pool[i]);
-+	}
-+	kfree(slot->rmap_list_pool);
-+	kfree(slot->pool_counts);
-+
-+out:
-+	slot->rung = NULL;
-+	if (slot->flags & UKSM_SLOT_IN_UKSM) {
-+		BUG_ON(uksm_pages_total < slot->pages);
-+		uksm_pages_total -= slot->pages;
-+	}
-+
-+	if (slot->fully_scanned_round == fully_scanned_round)
-+		scanned_virtual_pages -= slot->pages;
-+	else
-+		scanned_virtual_pages -= slot->pages_scanned;
-+	free_vma_slot(slot);
-+}
-+
-+
-+#define SPIN_LOCK_PERIOD	32
-+static struct vma_slot *cleanup_slots[SPIN_LOCK_PERIOD];
-+static inline void cleanup_vma_slots(void)
-+{
-+	struct vma_slot *slot;
-+	int i;
-+
-+	i = 0;
-+	spin_lock(&vma_slot_list_lock);
-+	while (!list_empty(&vma_slot_del)) {
-+		slot = list_entry(vma_slot_del.next,
-+				  struct vma_slot, slot_list);
-+		list_del(&slot->slot_list);
-+		cleanup_slots[i++] = slot;
-+		if (i == SPIN_LOCK_PERIOD) {
-+			spin_unlock(&vma_slot_list_lock);
-+			while (--i >= 0)
-+				uksm_del_vma_slot(cleanup_slots[i]);
-+			i = 0;
-+			spin_lock(&vma_slot_list_lock);
-+		}
-+	}
-+	spin_unlock(&vma_slot_list_lock);
-+
-+	while (--i >= 0)
-+		uksm_del_vma_slot(cleanup_slots[i]);
-+}
-+
-+/*
-+ * Expotional moving average formula
-+ */
-+static inline unsigned long ema(unsigned long curr, unsigned long last_ema)
-+{
-+	/*
-+	 * For a very high burst, even the ema cannot work well, a false very
-+	 * high per-page time estimation can result in feedback in very high
-+	 * overhead of context switch and rung update -- this will then lead
-+	 * to higher per-paper time, this may not converge.
-+	 *
-+	 * Instead, we try to approach this value in a binary manner.
-+	 */
-+	if (curr > last_ema * 10)
-+		return last_ema * 2;
-+
-+	return (EMA_ALPHA * curr + (100 - EMA_ALPHA) * last_ema) / 100;
-+}
-+
-+/*
-+ * convert cpu ratio in 1/TIME_RATIO_SCALE configured by user to
-+ * nanoseconds based on current uksm_sleep_jiffies.
-+ */
-+static inline unsigned long cpu_ratio_to_nsec(unsigned int ratio)
-+{
-+	return NSEC_PER_USEC * jiffies_to_usecs(uksm_sleep_jiffies) /
-+		(TIME_RATIO_SCALE - ratio) * ratio;
-+}
-+
-+
-+static inline unsigned long rung_real_ratio(int cpu_time_ratio)
-+{
-+	unsigned long ret;
-+
-+	BUG_ON(!cpu_time_ratio);
-+
-+	if (cpu_time_ratio > 0)
-+		ret = cpu_time_ratio;
-+	else
-+		ret = (unsigned long)(-cpu_time_ratio) *
-+			uksm_max_cpu_percentage / 100UL;
-+
-+	return ret ? ret : 1;
-+}
-+
-+static noinline void uksm_calc_scan_pages(void)
-+{
-+	struct scan_rung *ladder = uksm_scan_ladder;
-+	unsigned long sleep_usecs, nsecs;
-+	unsigned long ratio;
-+	int i;
-+	unsigned long per_page;
-+
-+	if (uksm_ema_page_time > 100000 ||
-+	    (((unsigned long) uksm_eval_round & (256UL - 1)) == 0UL))
-+		uksm_ema_page_time = UKSM_PAGE_TIME_DEFAULT;
-+
-+	per_page = uksm_ema_page_time;
-+	BUG_ON(!per_page);
-+
-+	/*
-+	 * For every 8 eval round, we try to probe a uksm_sleep_jiffies value
-+	 * based on saved user input.
-+	 */
-+	if (((unsigned long) uksm_eval_round & (8UL - 1)) == 0UL)
-+		uksm_sleep_jiffies = uksm_sleep_saved;
-+
-+	/* We require a rung scan at least 1 page in a period. */
-+	nsecs = per_page;
-+	ratio = rung_real_ratio(ladder[0].cpu_ratio);
-+	if (cpu_ratio_to_nsec(ratio) < nsecs) {
-+		sleep_usecs = nsecs * (TIME_RATIO_SCALE - ratio) / ratio
-+				/ NSEC_PER_USEC;
-+		uksm_sleep_jiffies = usecs_to_jiffies(sleep_usecs) + 1;
-+	}
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		ratio = rung_real_ratio(ladder[i].cpu_ratio);
-+		ladder[i].pages_to_scan = cpu_ratio_to_nsec(ratio) /
-+					per_page;
-+		BUG_ON(!ladder[i].pages_to_scan);
-+		uksm_calc_rung_step(&ladder[i], per_page, ratio);
-+	}
-+}
-+
-+/*
-+ * From the scan time of this round (ns) to next expected min sleep time
-+ * (ms), be careful of the possible overflows. ratio is taken from
-+ * rung_real_ratio()
-+ */
-+static inline
-+unsigned int scan_time_to_sleep(unsigned long long scan_time, unsigned long ratio)
-+{
-+	scan_time >>= 20; /* to msec level now */
-+	BUG_ON(scan_time > (ULONG_MAX / TIME_RATIO_SCALE));
-+
-+	return (unsigned int) ((unsigned long) scan_time *
-+			       (TIME_RATIO_SCALE - ratio) / ratio);
-+}
-+
-+#define __round_mask(x, y) ((__typeof__(x))((y)-1))
-+#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1)
-+
-+static void uksm_vma_enter(struct vma_slot **slots, unsigned long num)
-+{
-+	struct scan_rung *rung;
-+
-+	rung = &uksm_scan_ladder[0];
-+	rung_add_new_slots(rung, slots, num);
-+}
-+
-+static struct vma_slot *batch_slots[SLOT_TREE_NODE_STORE_SIZE];
-+
-+static void uksm_enter_all_slots(void)
-+{
-+	struct vma_slot *slot;
-+	unsigned long index;
-+	struct list_head empty_vma_list;
-+	int i;
-+
-+	i = 0;
-+	index = 0;
-+	INIT_LIST_HEAD(&empty_vma_list);
-+
-+	spin_lock(&vma_slot_list_lock);
-+	while (!list_empty(&vma_slot_new)) {
-+		slot = list_entry(vma_slot_new.next,
-+				  struct vma_slot, slot_list);
-+
-+		if (!slot->vma->anon_vma) {
-+			list_move(&slot->slot_list, &empty_vma_list);
-+		} else if (vma_can_enter(slot->vma)) {
-+			batch_slots[index++] = slot;
-+			list_del_init(&slot->slot_list);
-+		} else {
-+			list_move(&slot->slot_list, &vma_slot_noadd);
-+		}
-+
-+		if (++i == SPIN_LOCK_PERIOD ||
-+		    (index && !(index % SLOT_TREE_NODE_STORE_SIZE))) {
-+			spin_unlock(&vma_slot_list_lock);
-+
-+			if (index && !(index % SLOT_TREE_NODE_STORE_SIZE)) {
-+				uksm_vma_enter(batch_slots, index);
-+				index = 0;
-+			}
-+			i = 0;
-+			cond_resched();
-+			spin_lock(&vma_slot_list_lock);
-+		}
-+	}
-+
-+	list_splice(&empty_vma_list, &vma_slot_new);
-+
-+	spin_unlock(&vma_slot_list_lock);
-+
-+	if (index)
-+		uksm_vma_enter(batch_slots, index);
-+
-+}
-+
-+static inline int rung_round_finished(struct scan_rung *rung)
-+{
-+	return rung->flags & UKSM_RUNG_ROUND_FINISHED;
-+}
-+
-+static inline void judge_slot(struct vma_slot *slot)
-+{
-+	struct scan_rung *rung = slot->rung;
-+	unsigned long dedup;
-+	int deleted;
-+
-+	dedup = cal_dedup_ratio(slot);
-+	if (vma_fully_scanned(slot) && uksm_thrash_threshold)
-+		deleted = vma_rung_enter(slot, &uksm_scan_ladder[0]);
-+	else if (dedup && dedup >= uksm_abundant_threshold)
-+		deleted = vma_rung_up(slot);
-+	else
-+		deleted = vma_rung_down(slot);
-+
-+	slot->pages_merged = 0;
-+	slot->pages_cowed = 0;
-+	slot->this_sampled = 0;
-+
-+	if (vma_fully_scanned(slot))
-+		slot->pages_scanned = 0;
-+
-+	slot->last_scanned = slot->pages_scanned;
-+
-+	/* If its deleted in above, then rung was already advanced. */
-+	if (!deleted)
-+		advance_current_scan(rung);
-+}
-+
-+
-+static inline int hash_round_finished(void)
-+{
-+	if (scanned_virtual_pages > (uksm_pages_total >> 2)) {
-+		scanned_virtual_pages = 0;
-+		if (uksm_pages_scanned)
-+			fully_scanned_round++;
-+
-+		return 1;
-+	} else {
-+		return 0;
-+	}
-+}
-+
-+#define UKSM_MMSEM_BATCH	5
-+#define BUSY_RETRY		100
-+
-+/**
-+ * uksm_do_scan()  - the main worker function.
-+ */
-+static noinline void uksm_do_scan(void)
-+{
-+	struct vma_slot *slot, *iter;
-+	struct mm_struct *busy_mm;
-+	unsigned char round_finished, all_rungs_emtpy;
-+	int i, err, mmsem_batch;
-+	unsigned long pcost;
-+	long long delta_exec;
-+	unsigned long vpages, max_cpu_ratio;
-+	unsigned long long start_time, end_time, scan_time;
-+	unsigned int expected_jiffies;
-+
-+	might_sleep();
-+
-+	vpages = 0;
-+
-+	start_time = task_sched_runtime(current);
-+	max_cpu_ratio = 0;
-+	mmsem_batch = 0;
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE;) {
-+		struct scan_rung *rung = &uksm_scan_ladder[i];
-+		unsigned long ratio;
-+		int busy_retry;
-+
-+		if (!rung->pages_to_scan) {
-+			i++;
-+			continue;
-+		}
-+
-+		if (!rung->vma_root.num) {
-+			rung->pages_to_scan = 0;
-+			i++;
-+			continue;
-+		}
-+
-+		ratio = rung_real_ratio(rung->cpu_ratio);
-+		if (ratio > max_cpu_ratio)
-+			max_cpu_ratio = ratio;
-+
-+		busy_retry = BUSY_RETRY;
-+		/*
-+		 * Do not consider rung_round_finished() here, just used up the
-+		 * rung->pages_to_scan quota.
-+		 */
-+		while (rung->pages_to_scan && rung->vma_root.num &&
-+		       likely(!freezing(current))) {
-+			int reset = 0;
-+
-+			slot = rung->current_scan;
-+
-+			BUG_ON(vma_fully_scanned(slot));
-+
-+			if (mmsem_batch)
-+				err = 0;
-+			else
-+				err = try_down_read_slot_mmap_sem(slot);
-+
-+			if (err == -ENOENT) {
-+rm_slot:
-+				rung_rm_slot(slot);
-+				continue;
-+			}
-+
-+			busy_mm = slot->mm;
-+
-+			if (err == -EBUSY) {
-+				/* skip other vmas on the same mm */
-+				do {
-+					reset = advance_current_scan(rung);
-+					iter = rung->current_scan;
-+					busy_retry--;
-+					if (iter->vma->vm_mm != busy_mm ||
-+					    !busy_retry || reset)
-+						break;
-+				} while (1);
-+
-+				if (iter->vma->vm_mm != busy_mm) {
-+					continue;
-+				} else {
-+					/* scan round finsished */
-+					break;
-+				}
-+			}
-+
-+			BUG_ON(!vma_can_enter(slot->vma));
-+			if (uksm_test_exit(slot->vma->vm_mm)) {
-+				mmsem_batch = 0;
-+				mmap_read_unlock(slot->vma->vm_mm);
-+				goto rm_slot;
-+			}
-+
-+			if (mmsem_batch)
-+				mmsem_batch--;
-+			else
-+				mmsem_batch = UKSM_MMSEM_BATCH;
-+
-+			/* Ok, we have take the mmap_sem, ready to scan */
-+			scan_vma_one_page(slot);
-+			rung->pages_to_scan--;
-+			vpages++;
-+
-+			if (rung->current_offset + rung->step > slot->pages - 1
-+			    || vma_fully_scanned(slot)) {
-+				mmap_read_unlock(slot->vma->vm_mm);
-+				judge_slot(slot);
-+				mmsem_batch = 0;
-+			} else {
-+				rung->current_offset += rung->step;
-+				if (!mmsem_batch)
-+					mmap_read_unlock(slot->vma->vm_mm);
-+			}
-+
-+			busy_retry = BUSY_RETRY;
-+			cond_resched();
-+		}
-+
-+		if (mmsem_batch) {
-+			mmap_read_unlock(slot->vma->vm_mm);
-+			mmsem_batch = 0;
-+		}
-+
-+		if (freezing(current))
-+			break;
-+
-+		cond_resched();
-+	}
-+	end_time = task_sched_runtime(current);
-+	delta_exec = end_time - start_time;
-+
-+	if (freezing(current))
-+		return;
-+
-+	cleanup_vma_slots();
-+	uksm_enter_all_slots();
-+
-+	round_finished = 1;
-+	all_rungs_emtpy = 1;
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		struct scan_rung *rung = &uksm_scan_ladder[i];
-+
-+		if (rung->vma_root.num) {
-+			all_rungs_emtpy = 0;
-+			if (!rung_round_finished(rung))
-+				round_finished = 0;
-+		}
-+	}
-+
-+	if (all_rungs_emtpy)
-+		round_finished = 0;
-+
-+	if (round_finished) {
-+		round_update_ladder();
-+		uksm_eval_round++;
-+
-+		if (hash_round_finished() && rshash_adjust()) {
-+			/* Reset the unstable root iff hash strength changed */
-+			uksm_hash_round++;
-+			root_unstable_tree = RB_ROOT;
-+			free_all_tree_nodes(&unstable_tree_node_list);
-+		}
-+
-+		/*
-+		 * A number of pages can hang around indefinitely on per-cpu
-+		 * pagevecs, raised page count preventing write_protect_page
-+		 * from merging them.  Though it doesn't really matter much,
-+		 * it is puzzling to see some stuck in pages_volatile until
-+		 * other activity jostles them out, and they also prevented
-+		 * LTP's KSM test from succeeding deterministically; so drain
-+		 * them here (here rather than on entry to uksm_do_scan(),
-+		 * so we don't IPI too often when pages_to_scan is set low).
-+		 */
-+		lru_add_drain_all();
-+	}
-+
-+
-+	if (vpages && delta_exec > 0) {
-+		pcost = (unsigned long) delta_exec / vpages;
-+		if (likely(uksm_ema_page_time))
-+			uksm_ema_page_time = ema(pcost, uksm_ema_page_time);
-+		else
-+			uksm_ema_page_time = pcost;
-+	}
-+
-+	uksm_calc_scan_pages();
-+	uksm_sleep_real = uksm_sleep_jiffies;
-+	/* in case of radical cpu bursts, apply the upper bound */
-+	end_time = task_sched_runtime(current);
-+	if (max_cpu_ratio && end_time > start_time) {
-+		scan_time = end_time - start_time;
-+		expected_jiffies = msecs_to_jiffies(
-+			scan_time_to_sleep(scan_time, max_cpu_ratio));
-+
-+		if (expected_jiffies > uksm_sleep_real)
-+			uksm_sleep_real = expected_jiffies;
-+
-+		/* We have a 1 second up bound for responsiveness. */
-+		if (jiffies_to_msecs(uksm_sleep_real) > MSEC_PER_SEC)
-+			uksm_sleep_real = msecs_to_jiffies(1000);
-+	}
-+
-+	return;
-+}
-+
-+static int ksmd_should_run(void)
-+{
-+	return uksm_run & UKSM_RUN_MERGE;
-+}
-+
-+static int uksm_scan_thread(void *nothing)
-+{
-+	set_freezable();
-+	set_user_nice(current, 5);
-+
-+	while (!kthread_should_stop()) {
-+		mutex_lock(&uksm_thread_mutex);
-+		if (ksmd_should_run())
-+			uksm_do_scan();
-+		mutex_unlock(&uksm_thread_mutex);
-+
-+		try_to_freeze();
-+
-+		if (ksmd_should_run()) {
-+			schedule_timeout_interruptible(uksm_sleep_real);
-+			uksm_sleep_times++;
-+		} else {
-+			wait_event_freezable(uksm_thread_wait,
-+				ksmd_should_run() || kthread_should_stop());
-+		}
-+	}
-+	return 0;
-+}
-+
-+void rmap_walk_ksm(struct folio *folio, const struct rmap_walk_control *rwc)
-+{
-+	struct stable_node *stable_node;
-+	struct node_vma *node_vma;
-+	struct rmap_item *rmap_item;
-+	int search_new_forks = 0;
-+	unsigned long address;
-+
-+	VM_BUG_ON_FOLIO(!folio_test_ksm(folio), folio);
-+	VM_BUG_ON_FOLIO(!folio_test_locked(folio), folio);
-+
-+	stable_node = folio_stable_node(folio);
-+	if (!stable_node)
-+		return;
-+again:
-+	hlist_for_each_entry(node_vma, &stable_node->hlist, hlist) {
-+		hlist_for_each_entry(rmap_item, &node_vma->rmap_hlist, hlist) {
-+			struct anon_vma *anon_vma = rmap_item->anon_vma;
-+			struct anon_vma_chain *vmac;
-+			struct vm_area_struct *vma;
-+
-+			cond_resched();
-+			anon_vma_lock_read(anon_vma);
-+			anon_vma_interval_tree_foreach(vmac, &anon_vma->rb_root,
-+						       0, ULONG_MAX) {
-+				cond_resched();
-+				vma = vmac->vma;
-+				address = get_rmap_addr(rmap_item);
-+
-+				if (address < vma->vm_start ||
-+				    address >= vma->vm_end)
-+					continue;
-+
-+				if ((rmap_item->slot->vma == vma) ==
-+				    search_new_forks)
-+					continue;
-+
-+				if (rwc->invalid_vma && rwc->invalid_vma(vma, rwc->arg))
-+					continue;
-+
-+				if (!rwc->rmap_one(folio, vma, addr, rwc->arg)) {
-+					anon_vma_unlock_read(anon_vma);
-+					return;
-+				}
-+
-+				if (rwc->done && rwc->done(folio)) {
-+					anon_vma_unlock_read(anon_vma);
-+					return;
-+				}
-+			}
-+			anon_vma_unlock_read(anon_vma);
-+		}
-+	}
-+	if (!search_new_forks++)
-+		goto again;
-+}
-+
-+#ifdef CONFIG_MIGRATION
-+/* Common ksm interface but may be specific to uksm */
-+void folio_migrate_ksm(struct folio *newfolio, struct folio *folio)
-+{
-+	struct stable_node *stable_node;
-+
-+	VM_BUG_ON_FOLIO(!folio_test_locked(folio), folio);
-+	VM_BUG_ON_FOLIO(!folio_test_locked(newfolio), newfolio);
-+	VM_BUG_ON_FOLIO(newfolio->mapping != folio->mapping, newfolio);
-+
-+	stable_node = folio_stable_node(folio);
-+	if (stable_node) {
-+		VM_BUG_ON_FOLIO(stable_node->kpfn != folio_pfn(folio), folio);
-+		stable_node->kpfn = folio_pfn(newfolio);
-+		/*
-+		 newfolio->mapping was set in advance; now we need smp_wmb()
-+		 * to make sure that the new stable_node->kpfn is visible
-+		 * to get_ksm_page() before it can see that folio->mapping
-+		 * has gone stale (or that folio_test_swapcache has been cleared).
-+		 */
-+		smp_wmb();
-+		set_page_stable_node(&folio->page, NULL);
-+	}
-+}
-+#endif /* CONFIG_MIGRATION */
-+
-+#ifdef CONFIG_MEMORY_HOTREMOVE
-+static struct stable_node *uksm_check_stable_tree(unsigned long start_pfn,
-+						 unsigned long end_pfn)
-+{
-+	struct rb_node *node;
-+
-+	for (node = rb_first(root_stable_treep); node; node = rb_next(node)) {
-+		struct stable_node *stable_node;
-+
-+		stable_node = rb_entry(node, struct stable_node, node);
-+		if (stable_node->kpfn >= start_pfn &&
-+		    stable_node->kpfn < end_pfn)
-+			return stable_node;
-+	}
-+	return NULL;
-+}
-+
-+static int uksm_memory_callback(struct notifier_block *self,
-+			       unsigned long action, void *arg)
-+{
-+	struct memory_notify *mn = arg;
-+	struct stable_node *stable_node;
-+
-+	switch (action) {
-+	case MEM_GOING_OFFLINE:
-+		/*
-+		 * Keep it very simple for now: just lock out ksmd and
-+		 * MADV_UNMERGEABLE while any memory is going offline.
-+		 * mutex_lock_nested() is necessary because lockdep was alarmed
-+		 * that here we take uksm_thread_mutex inside notifier chain
-+		 * mutex, and later take notifier chain mutex inside
-+		 * uksm_thread_mutex to unlock it.   But that's safe because both
-+		 * are inside mem_hotplug_mutex.
-+		 */
-+		mutex_lock_nested(&uksm_thread_mutex, SINGLE_DEPTH_NESTING);
-+		break;
-+
-+	case MEM_OFFLINE:
-+		/*
-+		 * Most of the work is done by page migration; but there might
-+		 * be a few stable_nodes left over, still pointing to struct
-+		 * pages which have been offlined: prune those from the tree.
-+		 */
-+		while ((stable_node = uksm_check_stable_tree(mn->start_pfn,
-+					mn->start_pfn + mn->nr_pages)) != NULL)
-+			remove_node_from_stable_tree(stable_node, 1, 1);
-+		fallthrough;
-+
-+	case MEM_CANCEL_OFFLINE:
-+		mutex_unlock(&uksm_thread_mutex);
-+		break;
-+	}
-+	return NOTIFY_OK;
-+}
-+#endif /* CONFIG_MEMORY_HOTREMOVE */
-+
-+#ifdef CONFIG_SYSFS
-+/*
-+ * This all compiles without CONFIG_SYSFS, but is a waste of space.
-+ */
-+
-+#define UKSM_ATTR_RO(_name) \
-+	static struct kobj_attribute _name##_attr = __ATTR_RO(_name)
-+#define UKSM_ATTR(_name) \
-+	static struct kobj_attribute _name##_attr = __ATTR_RW(_name)
-+
-+static ssize_t max_cpu_percentage_show(struct kobject *kobj,
-+				    struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%u\n", uksm_max_cpu_percentage);
-+}
-+
-+static ssize_t max_cpu_percentage_store(struct kobject *kobj,
-+				     struct kobj_attribute *attr,
-+				     const char *buf, size_t count)
-+{
-+	unsigned long max_cpu_percentage;
-+	int err;
-+
-+	err = kstrtoul(buf, 10, &max_cpu_percentage);
-+	if (err || max_cpu_percentage > 100)
-+		return -EINVAL;
-+
-+	if (max_cpu_percentage == 100)
-+		max_cpu_percentage = 99;
-+	else if (max_cpu_percentage < 10)
-+		max_cpu_percentage = 10;
-+
-+	uksm_max_cpu_percentage = max_cpu_percentage;
-+
-+	return count;
-+}
-+UKSM_ATTR(max_cpu_percentage);
-+
-+static ssize_t sleep_millisecs_show(struct kobject *kobj,
-+				    struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%u\n", jiffies_to_msecs(uksm_sleep_jiffies));
-+}
-+
-+static ssize_t sleep_millisecs_store(struct kobject *kobj,
-+				     struct kobj_attribute *attr,
-+				     const char *buf, size_t count)
-+{
-+	unsigned long msecs;
-+	int err;
-+
-+	err = kstrtoul(buf, 10, &msecs);
-+	if (err || msecs > MSEC_PER_SEC)
-+		return -EINVAL;
-+
-+	uksm_sleep_jiffies = msecs_to_jiffies(msecs);
-+	uksm_sleep_saved = uksm_sleep_jiffies;
-+
-+	return count;
-+}
-+UKSM_ATTR(sleep_millisecs);
-+
-+
-+static ssize_t cpu_governor_show(struct kobject *kobj,
-+				  struct kobj_attribute *attr, char *buf)
-+{
-+	int n = sizeof(uksm_cpu_governor_str) / sizeof(char *);
-+	int i;
-+
-+	buf[0] = '\0';
-+	for (i = 0; i < n ; i++) {
-+		if (uksm_cpu_governor == i)
-+			strcat(buf, "[");
-+
-+		strcat(buf, uksm_cpu_governor_str[i]);
-+
-+		if (uksm_cpu_governor == i)
-+			strcat(buf, "]");
-+
-+		strcat(buf, " ");
-+	}
-+	strcat(buf, "\n");
-+
-+	return strlen(buf);
-+}
-+
-+static inline void init_performance_values(void)
-+{
-+	int i;
-+	struct scan_rung *rung;
-+	struct uksm_cpu_preset_s *preset = uksm_cpu_preset + uksm_cpu_governor;
-+
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		rung = uksm_scan_ladder + i;
-+		rung->cpu_ratio = preset->cpu_ratio[i];
-+		rung->cover_msecs = preset->cover_msecs[i];
-+	}
-+
-+	uksm_max_cpu_percentage = preset->max_cpu;
-+}
-+
-+static ssize_t cpu_governor_store(struct kobject *kobj,
-+				   struct kobj_attribute *attr,
-+				   const char *buf, size_t count)
-+{
-+	int n = sizeof(uksm_cpu_governor_str) / sizeof(char *);
-+
-+	for (n--; n >= 0 ; n--) {
-+		if (!strncmp(buf, uksm_cpu_governor_str[n],
-+			     strlen(uksm_cpu_governor_str[n])))
-+			break;
-+	}
-+
-+	if (n < 0)
-+		return -EINVAL;
-+	else
-+		uksm_cpu_governor = n;
-+
-+	init_performance_values();
-+
-+	return count;
-+}
-+UKSM_ATTR(cpu_governor);
-+
-+static ssize_t run_show(struct kobject *kobj, struct kobj_attribute *attr,
-+			char *buf)
-+{
-+	return sprintf(buf, "%u\n", uksm_run);
-+}
-+
-+static ssize_t run_store(struct kobject *kobj, struct kobj_attribute *attr,
-+			 const char *buf, size_t count)
-+{
-+	int err;
-+	unsigned long flags;
-+
-+	err = kstrtoul(buf, 10, &flags);
-+	if (err || flags > UINT_MAX)
-+		return -EINVAL;
-+	if (flags > UKSM_RUN_MERGE)
-+		return -EINVAL;
-+
-+	mutex_lock(&uksm_thread_mutex);
-+	if (uksm_run != flags)
-+		uksm_run = flags;
-+	mutex_unlock(&uksm_thread_mutex);
-+
-+	if (flags & UKSM_RUN_MERGE)
-+		wake_up_interruptible(&uksm_thread_wait);
-+
-+	return count;
-+}
-+UKSM_ATTR(run);
-+
-+static ssize_t abundant_threshold_show(struct kobject *kobj,
-+				     struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%u\n", uksm_abundant_threshold);
-+}
-+
-+static ssize_t abundant_threshold_store(struct kobject *kobj,
-+				      struct kobj_attribute *attr,
-+				      const char *buf, size_t count)
-+{
-+	int err;
-+	unsigned long flags;
-+
-+	err = kstrtoul(buf, 10, &flags);
-+	if (err || flags > 99)
-+		return -EINVAL;
-+
-+	uksm_abundant_threshold = flags;
-+
-+	return count;
-+}
-+UKSM_ATTR(abundant_threshold);
-+
-+static ssize_t thrash_threshold_show(struct kobject *kobj,
-+				     struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%u\n", uksm_thrash_threshold);
-+}
-+
-+static ssize_t thrash_threshold_store(struct kobject *kobj,
-+				      struct kobj_attribute *attr,
-+				      const char *buf, size_t count)
-+{
-+	int err;
-+	unsigned long flags;
-+
-+	err = kstrtoul(buf, 10, &flags);
-+	if (err || flags > 99)
-+		return -EINVAL;
-+
-+	uksm_thrash_threshold = flags;
-+
-+	return count;
-+}
-+UKSM_ATTR(thrash_threshold);
-+
-+static ssize_t cpu_ratios_show(struct kobject *kobj,
-+			       struct kobj_attribute *attr, char *buf)
-+{
-+	int i, size;
-+	struct scan_rung *rung;
-+	char *p = buf;
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		rung = &uksm_scan_ladder[i];
-+
-+		if (rung->cpu_ratio > 0)
-+			size = sprintf(p, "%d ", rung->cpu_ratio);
-+		else
-+			size = sprintf(p, "MAX/%d ",
-+					TIME_RATIO_SCALE / -rung->cpu_ratio);
-+
-+		p += size;
-+	}
-+
-+	*p++ = '\n';
-+	*p = '\0';
-+
-+	return p - buf;
-+}
-+
-+static ssize_t cpu_ratios_store(struct kobject *kobj,
-+				      struct kobj_attribute *attr,
-+				      const char *buf, size_t count)
-+{
-+	int i, cpuratios[SCAN_LADDER_SIZE], err;
-+	unsigned long value;
-+	struct scan_rung *rung;
-+	char *p, *end = NULL;
-+
-+	p = kzalloc(count, GFP_KERNEL);
-+	if (!p)
-+		return -ENOMEM;
-+
-+	memcpy(p, buf, count);
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		if (i != SCAN_LADDER_SIZE - 1) {
-+			end = strchr(p, ' ');
-+			if (!end)
-+				return -EINVAL;
-+
-+			*end = '\0';
-+		}
-+
-+		if (strstr(p, "MAX/")) {
-+			p = strchr(p, '/') + 1;
-+			err = kstrtoul(p, 10, &value);
-+			if (err || value > TIME_RATIO_SCALE || !value)
-+				return -EINVAL;
-+
-+			cpuratios[i] = -(int) (TIME_RATIO_SCALE / value);
-+		} else {
-+			err = kstrtoul(p, 10, &value);
-+			if (err || value > TIME_RATIO_SCALE || !value)
-+				return -EINVAL;
-+
-+			cpuratios[i] = value;
-+		}
-+
-+		p = end + 1;
-+	}
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		rung = &uksm_scan_ladder[i];
-+
-+		rung->cpu_ratio = cpuratios[i];
-+	}
-+
-+	return count;
-+}
-+UKSM_ATTR(cpu_ratios);
-+
-+static ssize_t eval_intervals_show(struct kobject *kobj,
-+			       struct kobj_attribute *attr, char *buf)
-+{
-+	int i, size;
-+	struct scan_rung *rung;
-+	char *p = buf;
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		rung = &uksm_scan_ladder[i];
-+		size = sprintf(p, "%u ", rung->cover_msecs);
-+		p += size;
-+	}
-+
-+	*p++ = '\n';
-+	*p = '\0';
-+
-+	return p - buf;
-+}
-+
-+static ssize_t eval_intervals_store(struct kobject *kobj,
-+				      struct kobj_attribute *attr,
-+				      const char *buf, size_t count)
-+{
-+	int i, err;
-+	unsigned long values[SCAN_LADDER_SIZE];
-+	struct scan_rung *rung;
-+	char *p, *end = NULL;
-+	ssize_t ret = count;
-+
-+	p = kzalloc(count + 2, GFP_KERNEL);
-+	if (!p)
-+		return -ENOMEM;
-+
-+	memcpy(p, buf, count);
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		if (i != SCAN_LADDER_SIZE - 1) {
-+			end = strchr(p, ' ');
-+			if (!end) {
-+				ret = -EINVAL;
-+				goto out;
-+			}
-+
-+			*end = '\0';
-+		}
-+
-+		err = kstrtoul(p, 10, &values[i]);
-+		if (err) {
-+			ret = -EINVAL;
-+			goto out;
-+		}
-+
-+		p = end + 1;
-+	}
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		rung = &uksm_scan_ladder[i];
-+
-+		rung->cover_msecs = values[i];
-+	}
-+
-+out:
-+	kfree(p);
-+	return ret;
-+}
-+UKSM_ATTR(eval_intervals);
-+
-+static ssize_t ema_per_page_time_show(struct kobject *kobj,
-+				 struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%lu\n", uksm_ema_page_time);
-+}
-+UKSM_ATTR_RO(ema_per_page_time);
-+
-+static ssize_t pages_shared_show(struct kobject *kobj,
-+				 struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%lu\n", uksm_pages_shared);
-+}
-+UKSM_ATTR_RO(pages_shared);
-+
-+static ssize_t pages_sharing_show(struct kobject *kobj,
-+				  struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%lu\n", uksm_pages_sharing);
-+}
-+UKSM_ATTR_RO(pages_sharing);
-+
-+static ssize_t pages_unshared_show(struct kobject *kobj,
-+				   struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%lu\n", uksm_pages_unshared);
-+}
-+UKSM_ATTR_RO(pages_unshared);
-+
-+static ssize_t full_scans_show(struct kobject *kobj,
-+			       struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%llu\n", fully_scanned_round);
-+}
-+UKSM_ATTR_RO(full_scans);
-+
-+static ssize_t pages_scanned_show(struct kobject *kobj,
-+				  struct kobj_attribute *attr, char *buf)
-+{
-+	unsigned long base = 0;
-+	u64 delta, ret;
-+
-+	if (pages_scanned_stored) {
-+		base = pages_scanned_base;
-+		ret = pages_scanned_stored;
-+		delta = uksm_pages_scanned >> base;
-+		if (CAN_OVERFLOW_U64(ret, delta)) {
-+			ret >>= 1;
-+			delta >>= 1;
-+			base++;
-+			ret += delta;
-+		}
-+	} else {
-+		ret = uksm_pages_scanned;
-+	}
-+
-+	while (ret > ULONG_MAX) {
-+		ret >>= 1;
-+		base++;
-+	}
-+
-+	if (base)
-+		return sprintf(buf, "%lu * 2^%lu\n", (unsigned long)ret, base);
-+	else
-+		return sprintf(buf, "%lu\n", (unsigned long)ret);
-+}
-+UKSM_ATTR_RO(pages_scanned);
-+
-+static ssize_t hash_strength_show(struct kobject *kobj,
-+				  struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%lu\n", hash_strength);
-+}
-+UKSM_ATTR_RO(hash_strength);
-+
-+static ssize_t sleep_times_show(struct kobject *kobj,
-+				  struct kobj_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%llu\n", uksm_sleep_times);
-+}
-+UKSM_ATTR_RO(sleep_times);
-+
-+
-+static struct attribute *uksm_attrs[] = {
-+	&max_cpu_percentage_attr.attr,
-+	&sleep_millisecs_attr.attr,
-+	&cpu_governor_attr.attr,
-+	&run_attr.attr,
-+	&ema_per_page_time_attr.attr,
-+	&pages_shared_attr.attr,
-+	&pages_sharing_attr.attr,
-+	&pages_unshared_attr.attr,
-+	&full_scans_attr.attr,
-+	&pages_scanned_attr.attr,
-+	&hash_strength_attr.attr,
-+	&sleep_times_attr.attr,
-+	&thrash_threshold_attr.attr,
-+	&abundant_threshold_attr.attr,
-+	&cpu_ratios_attr.attr,
-+	&eval_intervals_attr.attr,
-+	NULL,
-+};
-+
-+static struct attribute_group uksm_attr_group = {
-+	.attrs = uksm_attrs,
-+	.name = "uksm",
-+};
-+#endif /* CONFIG_SYSFS */
-+
-+static inline void init_scan_ladder(void)
-+{
-+	int i;
-+	struct scan_rung *rung;
-+
-+	for (i = 0; i < SCAN_LADDER_SIZE; i++) {
-+		rung = uksm_scan_ladder + i;
-+		slot_tree_init_root(&rung->vma_root);
-+	}
-+
-+	init_performance_values();
-+	uksm_calc_scan_pages();
-+}
-+
-+static inline int cal_positive_negative_costs(void)
-+{
-+	struct page *p1, *p2;
-+	unsigned char *addr1, *addr2;
-+	unsigned long i, time_start, hash_cost;
-+	unsigned long loopnum = 0;
-+
-+	/*IMPORTANT: volatile is needed to prevent over-optimization by gcc. */
-+	volatile u32 hash;
-+	volatile int ret;
-+
-+	p1 = alloc_page(GFP_KERNEL);
-+	if (!p1)
-+		return -ENOMEM;
-+
-+	p2 = alloc_page(GFP_KERNEL);
-+	if (!p2)
-+		return -ENOMEM;
-+
-+	addr1 = kmap_atomic(p1);
-+	addr2 = kmap_atomic(p2);
-+	memset(addr1, prandom_u32(), PAGE_SIZE);
-+	memcpy(addr2, addr1, PAGE_SIZE);
-+
-+	/* make sure that the two pages differ in last byte */
-+	addr2[PAGE_SIZE-1] = ~addr2[PAGE_SIZE-1];
-+	kunmap_atomic(addr2);
-+	kunmap_atomic(addr1);
-+
-+	time_start = jiffies;
-+	while (jiffies - time_start < 100) {
-+		for (i = 0; i < 100; i++)
-+			hash = page_hash(p1, HASH_STRENGTH_FULL, 0);
-+		loopnum += 100;
-+	}
-+	hash_cost = (jiffies - time_start);
-+
-+	time_start = jiffies;
-+	for (i = 0; i < loopnum; i++)
-+		ret = pages_identical_with_cost(p1, p2);
-+	memcmp_cost = HASH_STRENGTH_FULL * (jiffies - time_start);
-+	memcmp_cost /= hash_cost;
-+	pr_info("UKSM: relative memcmp_cost = %lu "
-+		"hash=%u cmp_ret=%d.\n",
-+		memcmp_cost, hash, ret);
-+
-+	__free_page(p1);
-+	__free_page(p2);
-+	return 0;
-+}
-+
-+static int init_zeropage_hash_table(void)
-+{
-+	struct page *page;
-+	char *addr;
-+	int i;
-+
-+	page = alloc_page(GFP_KERNEL);
-+	if (!page)
-+		return -ENOMEM;
-+
-+	addr = kmap_atomic(page);
-+	memset(addr, 0, PAGE_SIZE);
-+	kunmap_atomic(addr);
-+
-+	zero_hash_table = kmalloc_array(HASH_STRENGTH_MAX, sizeof(u32),
-+		GFP_KERNEL);
-+	if (!zero_hash_table)
-+		return -ENOMEM;
-+
-+	for (i = 0; i < HASH_STRENGTH_MAX; i++)
-+		zero_hash_table[i] = page_hash(page, i, 0);
-+
-+	__free_page(page);
-+
-+	return 0;
-+}
-+
-+static inline int init_random_sampling(void)
-+{
-+	unsigned long i;
-+
-+	random_nums = kmalloc(PAGE_SIZE, GFP_KERNEL);
-+	if (!random_nums)
-+		return -ENOMEM;
-+
-+	for (i = 0; i < HASH_STRENGTH_FULL; i++)
-+		random_nums[i] = i;
-+
-+	for (i = 0; i < HASH_STRENGTH_FULL; i++) {
-+		unsigned long rand_range, swap_index, tmp;
-+
-+		rand_range = HASH_STRENGTH_FULL - i;
-+		swap_index = i + prandom_u32() % rand_range;
-+		tmp = random_nums[i];
-+		random_nums[i] =  random_nums[swap_index];
-+		random_nums[swap_index] = tmp;
-+	}
-+
-+	rshash_state.state = RSHASH_NEW;
-+	rshash_state.below_count = 0;
-+	rshash_state.lookup_window_index = 0;
-+
-+	return cal_positive_negative_costs();
-+}
-+
-+static int __init uksm_slab_init(void)
-+{
-+	rmap_item_cache = UKSM_KMEM_CACHE(rmap_item, 0);
-+	if (!rmap_item_cache)
-+		goto out;
-+
-+	stable_node_cache = UKSM_KMEM_CACHE(stable_node, 0);
-+	if (!stable_node_cache)
-+		goto out_free1;
-+
-+	node_vma_cache = UKSM_KMEM_CACHE(node_vma, 0);
-+	if (!node_vma_cache)
-+		goto out_free2;
-+
-+	vma_slot_cache = UKSM_KMEM_CACHE(vma_slot, 0);
-+	if (!vma_slot_cache)
-+		goto out_free3;
-+
-+	tree_node_cache = UKSM_KMEM_CACHE(tree_node, 0);
-+	if (!tree_node_cache)
-+		goto out_free4;
-+
-+	return 0;
-+
-+out_free4:
-+	kmem_cache_destroy(vma_slot_cache);
-+out_free3:
-+	kmem_cache_destroy(node_vma_cache);
-+out_free2:
-+	kmem_cache_destroy(stable_node_cache);
-+out_free1:
-+	kmem_cache_destroy(rmap_item_cache);
-+out:
-+	return -ENOMEM;
-+}
-+
-+static void __init uksm_slab_free(void)
-+{
-+	kmem_cache_destroy(stable_node_cache);
-+	kmem_cache_destroy(rmap_item_cache);
-+	kmem_cache_destroy(node_vma_cache);
-+	kmem_cache_destroy(vma_slot_cache);
-+	kmem_cache_destroy(tree_node_cache);
-+}
-+
-+/* Common interface to ksm, different to it. */
-+int ksm_madvise(struct vm_area_struct *vma, unsigned long start,
-+		unsigned long end, int advice, unsigned long *vm_flags)
-+{
-+	int err;
-+
-+	switch (advice) {
-+	case MADV_MERGEABLE:
-+		return 0;		/* just ignore the advice */
-+
-+	case MADV_UNMERGEABLE:
-+		if (!(*vm_flags & VM_MERGEABLE) || !uksm_flags_can_scan(*vm_flags))
-+			return 0;		/* just ignore the advice */
-+
-+		if (vma->anon_vma) {
-+			err = unmerge_uksm_pages(vma, start, end);
-+			if (err)
-+				return err;
-+		}
-+
-+		uksm_remove_vma(vma);
-+		*vm_flags &= ~VM_MERGEABLE;
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+/* Common interface to ksm, actually the same. */
-+struct page *ksm_might_need_to_copy(struct page *page,
-+			struct vm_area_struct *vma, unsigned long address)
-+{
-+	struct folio *folio = page_folio(page);
-+	struct anon_vma *anon_vma = folio_anon_vma(folio);
-+	struct page *new_page;
-+
-+	if (PageKsm(page)) {
-+		if (page_stable_node(page))
-+			return page;	/* no need to copy it */
-+	} else if (!anon_vma) {
-+		return page;		/* no need to copy it */
-+	} else if (page->index == linear_page_index(vma, address) &&
-+			anon_vma->root == vma->anon_vma->root) {
-+		return page;		/* still no need to copy it */
-+	}
-+	if (!PageUptodate(page))
-+		return page;		/* let do_swap_page report the error */
-+
-+	new_page = alloc_page_vma(GFP_HIGHUSER_MOVABLE, vma, address);
-+	if (new_page) {
-+		copy_user_highpage(new_page, page, address, vma);
-+
-+		SetPageDirty(new_page);
-+		__SetPageUptodate(new_page);
-+		__SetPageLocked(new_page);
-+#ifdef CONFIG_SWAP
-+		count_vm_event(KSM_SWPIN_COPY);
-+#endif
-+	}
-+
-+	return new_page;
-+}
-+
-+/* Copied from mm/ksm.c and required from 5.1 */
-+bool reuse_ksm_page(struct page *page,
-+		    struct vm_area_struct *vma,
-+		    unsigned long address)
-+{
-+#ifdef CONFIG_DEBUG_VM
-+	if (WARN_ON(is_zero_pfn(page_to_pfn(page))) ||
-+			WARN_ON(!page_mapped(page)) ||
-+			WARN_ON(!PageLocked(page))) {
-+		dump_page(page, "reuse_ksm_page");
-+		return false;
-+	}
-+#endif
-+
-+	if (PageSwapCache(page) || !page_stable_node(page))
-+		return false;
-+	/* Prohibit parallel get_ksm_page() */
-+	if (!page_ref_freeze(page, 1))
-+		return false;
-+
-+	page_move_anon_rmap(page, vma);
-+	page->index = linear_page_index(vma, address);
-+	page_ref_unfreeze(page, 1);
-+
-+	return true;
-+}
-+
-+static int __init uksm_init(void)
-+{
-+	struct task_struct *uksm_thread;
-+	int err;
-+
-+	uksm_sleep_jiffies = msecs_to_jiffies(100);
-+	uksm_sleep_saved = uksm_sleep_jiffies;
-+
-+	slot_tree_init();
-+	init_scan_ladder();
-+
-+
-+	err = init_random_sampling();
-+	if (err)
-+		goto out_free2;
-+
-+	err = uksm_slab_init();
-+	if (err)
-+		goto out_free1;
-+
-+	err = init_zeropage_hash_table();
-+	if (err)
-+		goto out_free0;
-+
-+	uksm_thread = kthread_run(uksm_scan_thread, NULL, "uksmd");
-+	if (IS_ERR(uksm_thread)) {
-+		pr_err("uksm: creating kthread failed\n");
-+		err = PTR_ERR(uksm_thread);
-+		goto out_free;
-+	}
-+
-+#ifdef CONFIG_SYSFS
-+	err = sysfs_create_group(mm_kobj, &uksm_attr_group);
-+	if (err) {
-+		pr_err("uksm: register sysfs failed\n");
-+		kthread_stop(uksm_thread);
-+		goto out_free;
-+	}
-+#else
-+	uksm_run = UKSM_RUN_MERGE;	/* no way for user to start it */
-+
-+#endif /* CONFIG_SYSFS */
-+
-+#ifdef CONFIG_MEMORY_HOTREMOVE
-+	/*
-+	 * Choose a high priority since the callback takes uksm_thread_mutex:
-+	 * later callbacks could only be taking locks which nest within that.
-+	 */
-+	hotplug_memory_notifier(uksm_memory_callback, 100);
-+#endif
-+	return 0;
-+
-+out_free:
-+	kfree(zero_hash_table);
-+out_free0:
-+	uksm_slab_free();
-+out_free1:
-+	kfree(random_nums);
-+out_free2:
-+	kfree(uksm_scan_ladder);
-+	return err;
-+}
-+
-+#ifdef MODULE
-+subsys_initcall(ksm_init);
-+#else
-+late_initcall(uksm_init);
-+#endif
-+
-diff --git a/mm/vmstat.c b/mm/vmstat.c
-index b75b1a64b..56b484dbf 100644
---- a/mm/vmstat.c
-+++ b/mm/vmstat.c
-@@ -1247,6 +1247,9 @@ const char * const vmstat_text[] = {
- 	"pgpromote_success",
- #endif
- 
-+#ifdef CONFIG_UKSM
-+	"nr_uksm_zero_pages",
-+#endif
- 	/* enum writeback_stat_item counters */
- 	"nr_dirty_threshold",
- 	"nr_dirty_background_threshold",
--- 
-2.36.1.74.g277cf0bc36
-
diff --git a/0001-arm64-dts-rockchip-Add-back-cdn_dp-to-Pinebook-Pro.patch b/0001-arm64-dts-rockchip-Add-back-cdn_dp-to-Pinebook-Pro.patch
deleted file mode 100644
index 6d87ab0..0000000
--- a/0001-arm64-dts-rockchip-Add-back-cdn_dp-to-Pinebook-Pro.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 7ed9d9ed4276945a2d3615bdf83c1fd64f07a682 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Thu, 4 Nov 2021 17:32:34 +0100
-Subject: [PATCH] arm64: dts: rockchip: Add back cdn_dp to Pinebook Pro CDN_DP
- was removed in commit 2513fa5c25d42f55ca5f0f0ab247af7c9fbfa3b1 ("arm64: dts:
- rockchip: Disable CDN DP on Pinebook Pro") because the Pinebook Pro dts does
- not have the extcon to use it, which results in a black screen if enabled.
-
-But since we (Manjaro ARM) apply patches to enable extcon
-to it, add back the dts node for Pinebook Pro.
-
-Fixes: 2513fa5c25d42f55ca5f0f0ab247af7c9fbfa3b1 ("arm64: dts: rockchip: Disable CDN DP on Pinebook Pro")
-
-Signed-off-by: Dan Johansen <strit@manjaro.org>
----
- arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
-index c2f021a1a18f..229176677fea 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
-@@ -386,6 +386,10 @@ mains_charger: dc-charger {
- 	};
- };
- 
-+&cdn_dp {
-+	status = "okay";
-+};
-+
- &cpu_b0 {
- 	cpu-supply = <&vdd_cpu_b>;
- };
--- 
-2.33.0
-
diff --git a/0001-net-smsc95xx-Allow-mac-address-to-be-set-as-a-parame.patch b/0001-net-smsc95xx-Allow-mac-address-to-be-set-as-a-parame.patch
deleted file mode 100644
index 349c977..0000000
--- a/0001-net-smsc95xx-Allow-mac-address-to-be-set-as-a-parame.patch
+++ /dev/null
@@ -1,90 +0,0 @@
-diff -up linux-5.16/drivers/net/usb/smsc95xx.c.43~ linux-5.16/drivers/net/usb/smsc95xx.c
---- linux-5.16/drivers/net/usb/smsc95xx.c.43~	2022-01-09 23:55:34.000000000 +0100
-+++ linux-5.16/drivers/net/usb/smsc95xx.c	2022-01-10 11:33:33.272235865 +0100
-@@ -50,6 +50,7 @@
- #define SUSPEND_SUSPEND3		(0x08)
- #define SUSPEND_ALLMODES		(SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
- 					 SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
-+#define MAC_ADDR_LEN                    (6)
- 
- struct smsc95xx_priv {
- 	u32 mac_cr;
-@@ -67,6 +68,10 @@ static bool turbo_mode = true;
- module_param(turbo_mode, bool, 0644);
- MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
- 
-+static char *macaddr = ":";
-+module_param(macaddr, charp, 0);
-+MODULE_PARM_DESC(macaddr, "MAC address");
-+
- static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
- 					    u32 *data, int in_pm)
- {
-@@ -753,8 +758,59 @@ static int smsc95xx_ioctl(struct net_dev
- 	return phy_mii_ioctl(netdev->phydev, rq, cmd);
- }
- 
-+/* Check the macaddr module parameter for a MAC address */
-+static int smsc95xx_is_macaddr_param(struct usbnet *dev, u8 *dev_mac)
-+{
-+       int i, j, got_num, num;
-+       u8 mtbl[MAC_ADDR_LEN];
-+
-+       if (macaddr[0] == ':')
-+               return 0;
-+
-+       i = 0;
-+       j = 0;
-+       num = 0;
-+       got_num = 0;
-+       while (j < MAC_ADDR_LEN) {
-+               if (macaddr[i] && macaddr[i] != ':') {
-+                       got_num++;
-+                       if ('0' <= macaddr[i] && macaddr[i] <= '9')
-+                               num = num * 16 + macaddr[i] - '0';
-+                       else if ('A' <= macaddr[i] && macaddr[i] <= 'F')
-+                               num = num * 16 + 10 + macaddr[i] - 'A';
-+                       else if ('a' <= macaddr[i] && macaddr[i] <= 'f')
-+                               num = num * 16 + 10 + macaddr[i] - 'a';
-+                       else
-+                               break;
-+                       i++;
-+               } else if (got_num == 2) {
-+                       mtbl[j++] = (u8) num;
-+                       num = 0;
-+                       got_num = 0;
-+                       i++;
-+               } else {
-+                       break;
-+               }
-+       }
-+
-+       if (j == MAC_ADDR_LEN) {
-+               netif_dbg(dev, ifup, dev->net, "Overriding MAC address with: "
-+               "%02x:%02x:%02x:%02x:%02x:%02x\n", mtbl[0], mtbl[1], mtbl[2],
-+                                               mtbl[3], mtbl[4], mtbl[5]);
-+               for (i = 0; i < MAC_ADDR_LEN; i++)
-+                       dev_mac[i] = mtbl[i];
-+               return 1;
-+       } else {
-+               return 0;
-+       }
-+}
-+
- static void smsc95xx_init_mac_address(struct usbnet *dev)
- {
-+       /* Check module parameters */
-+       if (smsc95xx_is_macaddr_param(dev, dev->net->dev_addr))
-+               return;
-+
- 	u8 addr[ETH_ALEN];
- 
- 	/* maybe the boot loader passed the MAC address in devicetree */
-@@ -781,6 +837,7 @@ static void smsc95xx_init_mac_address(st
- 	netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
- }
- 
-+
- static int smsc95xx_set_mac_address(struct usbnet *dev)
- {
- 	u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
diff --git a/0001-phy-rockchip-typec-Set-extcon-capabilities.patch b/0001-phy-rockchip-typec-Set-extcon-capabilities.patch
deleted file mode 100644
index 0630853..0000000
--- a/0001-phy-rockchip-typec-Set-extcon-capabilities.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From db4e9ffdb985752ae3c3436ff86f8f376ae8fd22 Mon Sep 17 00:00:00 2001
-From: Tobias Schramm <t.schramm@manjaro.org>
-Date: Thu, 28 May 2020 14:25:32 +0200
-Subject: [PATCH] phy: rockchip: typec: Set extcon capabilities
-
-Do not mainline, hack.
-
-Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>
----
- drivers/phy/rockchip/phy-rockchip-typec.c | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
-index 70a31251b202..5385bb4f0bd4 100644
---- a/drivers/phy/rockchip/phy-rockchip-typec.c
-+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
-@@ -40,6 +40,7 @@
- #include <linux/clk-provider.h>
- #include <linux/delay.h>
- #include <linux/extcon.h>
-+#include <linux/extcon-provider.h>
- #include <linux/io.h>
- #include <linux/iopoll.h>
- #include <linux/kernel.h>
-@@ -1160,6 +1161,22 @@ static int rockchip_typec_phy_probe(struct platform_device *pdev)
- 				dev_err(dev, "Invalid or missing extcon\n");
- 			return PTR_ERR(tcphy->extcon);
- 		}
-+	} else {
-+		extcon_set_property_capability(tcphy->extcon, EXTCON_USB,
-+					       EXTCON_PROP_USB_SS);
-+		extcon_set_property_capability(tcphy->extcon, EXTCON_USB_HOST,
-+					       EXTCON_PROP_USB_SS);
-+		extcon_set_property_capability(tcphy->extcon, EXTCON_DISP_DP,
-+					       EXTCON_PROP_USB_SS);
-+		extcon_set_property_capability(tcphy->extcon, EXTCON_USB,
-+					       EXTCON_PROP_USB_TYPEC_POLARITY);
-+		extcon_set_property_capability(tcphy->extcon, EXTCON_USB_HOST,
-+					       EXTCON_PROP_USB_TYPEC_POLARITY);
-+		extcon_set_property_capability(tcphy->extcon, EXTCON_DISP_DP,
-+					       EXTCON_PROP_USB_TYPEC_POLARITY);
-+		extcon_sync(tcphy->extcon, EXTCON_USB);
-+		extcon_sync(tcphy->extcon, EXTCON_USB_HOST);
-+		extcon_sync(tcphy->extcon, EXTCON_DISP_DP);
- 	}
- 
- 	pm_runtime_enable(dev);
--- 
-GitLab 
diff --git a/0001-revert-arm64-dts-allwinner-a64-Add-I2S2-node.patch b/0001-revert-arm64-dts-allwinner-a64-Add-I2S2-node.patch
deleted file mode 100644
index 49083da..0000000
--- a/0001-revert-arm64-dts-allwinner-a64-Add-I2S2-node.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 7adafff1263378f964dbd66ea2ab849fdad5e588 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Mon, 28 Dec 2020 16:14:40 +0100
-Subject: [PATCH] revert: arm64: dts: allwinner: a64: Add I2S2 node
-
----
- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 --------------
- 1 file changed, 14 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-index 51cc30e84e26..dc238814013c 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-@@ -846,20 +846,6 @@ i2s1: i2s@1c22400 {
- 			status = "disabled";
- 		};
- 
--		i2s2: i2s@1c22800 {
--			#sound-dai-cells = <0>;
--			compatible = "allwinner,sun50i-a64-i2s",
--				     "allwinner,sun8i-h3-i2s";
--			reg = <0x01c22800 0x400>;
--			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
--			clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
--			clock-names = "apb", "mod";
--			resets = <&ccu RST_BUS_I2S2>;
--			dma-names = "rx", "tx";
--			dmas = <&dma 27>, <&dma 27>;
--			status = "disabled";
--		};
--
- 		dai: dai@1c22c00 {
- 			#sound-dai-cells = <0>;
- 			compatible = "allwinner,sun50i-a64-codec-i2s";
--- 
-2.29.2
-
diff --git a/0002-Bluetooth-Add-new-quirk-for-broken-local-ext-features.patch b/0002-Bluetooth-Add-new-quirk-for-broken-local-ext-features.patch
deleted file mode 100644
index 4970a4e..0000000
--- a/0002-Bluetooth-Add-new-quirk-for-broken-local-ext-features.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 942e794211fc05943db36212d41c4e8a68b3c922 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Mon, 17 Aug 2020 21:32:16 +0200
-Subject: [PATCH] Bluetooth-Add-new-quirk-for-broken-local-ext-features
-
----
- include/net/bluetooth/hci.h | 7 +++++++
- net/bluetooth/hci_event.c   | 4 +++-
- 2 files changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h
-index c8e67042a3b1..53f7a8518372 100644
---- a/include/net/bluetooth/hci.h
-+++ b/include/net/bluetooth/hci.h
-@@ -228,6 +228,13 @@ enum {
- 	 */
- 	HCI_QUIRK_VALID_LE_STATES,
- 
-+	/* When this quirk is set, max_page for local extended features
-+	 * is set to 1, even if controller reports higher number. Some
-+	 * controllers (e.g. RTL8723CS) report more pages, but they
-+	 * don't actually support features declared there.
-+	 */
-+	HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE,
-+
- 	/* When this quirk is set, then erroneous data reporting
- 	 * is ignored. This is mainly due to the fact that the HCI
- 	 * Read Default Erroneous Data Reporting command is advertised,
-diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
-index 4b7fc430793c..9b165c8f16de 100644
---- a/net/bluetooth/hci_event.c
-+++ b/net/bluetooth/hci_event.c
-@@ -700,7 +700,9 @@ static void hci_cc_read_local_ext_features(struct hci_dev *hdev,
- 	if (rp->status)
- 		return;
- 
--	if (hdev->max_page < rp->max_page)
-+	if (!test_bit(HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE,
-+		      &hdev->quirks) &&
-+	    hdev->max_page < rp->max_page)
- 		hdev->max_page = rp->max_page;
- 
- 	if (rp->page < HCI_MAX_PAGES)
--- 
-2.28.0
-
diff --git a/0002-Bluetooth-btrtl-add-support-for-the-RTL8723CS.patch b/0002-Bluetooth-btrtl-add-support-for-the-RTL8723CS.patch
deleted file mode 100644
index 4588af9..0000000
--- a/0002-Bluetooth-btrtl-add-support-for-the-RTL8723CS.patch
+++ /dev/null
@@ -1,272 +0,0 @@
-From 98780d7a20789dd671c5858546bcc7f9320fb335 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Wed, 17 Nov 2021 00:10:47 +0100
-Subject: [PATCH] Bluetooth: btrtl: add support for the RTL8723CS
-
-Signed-off-by: Dan Johansen <strit@manjaro.org>
----
- drivers/bluetooth/btrtl.c  | 124 +++++++++++++++++++++++++++++++++++--
- drivers/bluetooth/btrtl.h  |   5 ++
- drivers/bluetooth/hci_h5.c |   2 +
- 3 files changed, 127 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c
-index c2bdd1e6060e..e64b6d1ead95 100644
---- a/drivers/bluetooth/btrtl.c
-+++ b/drivers/bluetooth/btrtl.c
-@@ -17,7 +17,12 @@
- 
- #define VERSION "0.1"
- 
-+#define RTL_CHIP_8723CS_CG	3
-+#define RTL_CHIP_8723CS_VF	4
-+#define RTL_CHIP_8723CS_XX	5
- #define RTL_EPATCH_SIGNATURE	"Realtech"
-+#define RTL_ROM_LMP_3499	0x3499
-+#define RTL_ROM_LMP_8703B	0x8703
- #define RTL_ROM_LMP_8723A	0x1200
- #define RTL_ROM_LMP_8723B	0x8723
- #define RTL_ROM_LMP_8821A	0x8821
-@@ -30,6 +35,7 @@
- #define IC_MATCH_FL_HCIREV	(1 << 1)
- #define IC_MATCH_FL_HCIVER	(1 << 2)
- #define IC_MATCH_FL_HCIBUS	(1 << 3)
-+#define IC_MATCH_FL_CHIP_TYPE	(1 << 4)
- #define IC_INFO(lmps, hcir, hciv, bus) \
- 	.match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_HCIREV | \
- 		       IC_MATCH_FL_HCIVER | IC_MATCH_FL_HCIBUS, \
-@@ -57,6 +63,7 @@ struct id_table {
- 	__u16 hci_rev;
- 	__u8 hci_ver;
- 	__u8 hci_bus;
-+	__u8 chip_type;
- 	bool config_needed;
- 	bool has_rom_version;
- 	bool has_msft_ext;
-@@ -97,6 +104,39 @@ static const struct id_table ic_id_table[] = {
- 	  .fw_name  = "rtl_bt/rtl8723b_fw.bin",
- 	  .cfg_name = "rtl_bt/rtl8723b_config" },
- 
-+	/* 8723CS-CG */
-+	{ .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE |
-+			 IC_MATCH_FL_HCIBUS,
-+	  .lmp_subver = RTL_ROM_LMP_8703B,
-+	  .chip_type = RTL_CHIP_8723CS_CG,
-+	  .hci_bus = HCI_UART,
-+	  .config_needed = true,
-+	  .has_rom_version = true,
-+	  .fw_name  = "rtl_bt/rtl8723cs_cg_fw.bin",
-+	  .cfg_name = "rtl_bt/rtl8723cs_cg_config" },
-+
-+	/* 8723CS-VF */
-+	{ .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE |
-+			 IC_MATCH_FL_HCIBUS,
-+	  .lmp_subver = RTL_ROM_LMP_8703B,
-+	  .chip_type = RTL_CHIP_8723CS_VF,
-+	  .hci_bus = HCI_UART,
-+	  .config_needed = true,
-+	  .has_rom_version = true,
-+	  .fw_name  = "rtl_bt/rtl8723cs_vf_fw.bin",
-+	  .cfg_name = "rtl_bt/rtl8723cs_vf_config" },
-+
-+	/* 8723CS-XX */
-+	{ .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE |
-+			 IC_MATCH_FL_HCIBUS,
-+	  .lmp_subver = RTL_ROM_LMP_8703B,
-+	  .chip_type = RTL_CHIP_8723CS_XX,
-+	  .hci_bus = HCI_UART,
-+	  .config_needed = true,
-+	  .has_rom_version = true,
-+	  .fw_name  = "rtl_bt/rtl8723cs_xx_fw.bin",
-+	  .cfg_name = "rtl_bt/rtl8723cs_xx_config" },
-+
- 	/* 8723D */
- 	{ IC_INFO(RTL_ROM_LMP_8723B, 0xd, 0x8, HCI_USB),
- 	  .config_needed = true,
-@@ -182,7 +222,8 @@ static const struct id_table ic_id_table[] = {
- 	};
- 
- static const struct id_table *btrtl_match_ic(u16 lmp_subver, u16 hci_rev,
--					     u8 hci_ver, u8 hci_bus)
-+					     u8 hci_ver, u8 hci_bus,
-+					     u8 chip_type)
- {
- 	int i;
- 
-@@ -199,6 +240,9 @@ static const struct id_table *btrtl_match_ic(u16 lmp_subver, u16 hci_rev,
- 		if ((ic_id_table[i].match_flags & IC_MATCH_FL_HCIBUS) &&
- 		    (ic_id_table[i].hci_bus != hci_bus))
- 			continue;
-+		if ((ic_id_table[i].match_flags & IC_MATCH_FL_CHIP_TYPE) &&
-+		    (ic_id_table[i].chip_type != chip_type))
-+			continue;
- 
- 		break;
- 	}
-@@ -281,6 +325,7 @@ static int rtlbt_parse_firmware(struct hci_dev *hdev,
- 		{ RTL_ROM_LMP_8723B, 1 },
- 		{ RTL_ROM_LMP_8821A, 2 },
- 		{ RTL_ROM_LMP_8761A, 3 },
-+		{ RTL_ROM_LMP_8703B, 7 },
- 		{ RTL_ROM_LMP_8822B, 8 },
- 		{ RTL_ROM_LMP_8723B, 9 },	/* 8723D */
- 		{ RTL_ROM_LMP_8821A, 10 },	/* 8821C */
-@@ -559,6 +604,48 @@ static int btrtl_setup_rtl8723b(struct hci_dev *hdev,
- 	return ret;
- }
- 
-+static bool rtl_has_chip_type(u16 lmp_subver)
-+{
-+	switch (lmp_subver) {
-+	case RTL_ROM_LMP_8703B:
-+		return true;
-+	default:
-+		break;
-+	}
-+
-+	return  false;
-+}
-+
-+static int rtl_read_chip_type(struct hci_dev *hdev, u8 *type)
-+{
-+	struct rtl_chip_type_evt *chip_type;
-+	struct sk_buff *skb;
-+	const unsigned char cmd_buf[] = {0x00, 0x94, 0xa0, 0x00, 0xb0};
-+
-+	/* Read RTL chip type command */
-+	skb = __hci_cmd_sync(hdev, 0xfc61, 5, cmd_buf, HCI_INIT_TIMEOUT);
-+	if (IS_ERR(skb)) {
-+		rtl_dev_err(hdev, "Read chip type failed (%ld)",
-+			    PTR_ERR(skb));
-+		return PTR_ERR(skb);
-+	}
-+
-+	if (skb->len != sizeof(*chip_type)) {
-+		rtl_dev_err(hdev, "RTL chip type event length mismatch");
-+		kfree_skb(skb);
-+		return -EIO;
-+	}
-+
-+	chip_type = (struct rtl_chip_type_evt *)skb->data;
-+	rtl_dev_info(hdev, "chip_type status=%x type=%x",
-+		     chip_type->status, chip_type->type);
-+
-+	*type = chip_type->type & 0x0f;
-+
-+	kfree_skb(skb);
-+	return 0;
-+}
-+
- void btrtl_free(struct btrtl_device_info *btrtl_dev)
- {
- 	kvfree(btrtl_dev->fw_data);
-@@ -575,7 +662,7 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev,
- 	struct hci_rp_read_local_version *resp;
- 	char cfg_name[40];
- 	u16 hci_rev, lmp_subver;
--	u8 hci_ver;
-+	u8 hci_ver, chip_type = 0;
- 	int ret;
- 	u16 opcode;
- 	u8 cmd[2];
-@@ -601,8 +688,17 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev,
- 	hci_rev = le16_to_cpu(resp->hci_rev);
- 	lmp_subver = le16_to_cpu(resp->lmp_subver);
- 
-+	/*
-+	 * We assume drop_fw is not needed for devices that have chip_type.
-+	 */
-+	if (rtl_has_chip_type(lmp_subver)) {
-+		ret = rtl_read_chip_type(hdev, &chip_type);
-+		if (ret)
-+			goto err_free;
-+	}
-+
- 	btrtl_dev->ic_info = btrtl_match_ic(lmp_subver, hci_rev, hci_ver,
--					    hdev->bus);
-+					    hdev->bus, chip_type);
- 
- 	if (!btrtl_dev->ic_info)
- 		btrtl_dev->drop_fw = true;
-@@ -645,7 +741,7 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev,
- 		lmp_subver = le16_to_cpu(resp->lmp_subver);
- 
- 		btrtl_dev->ic_info = btrtl_match_ic(lmp_subver, hci_rev, hci_ver,
--						    hdev->bus);
-+						    hdev->bus, chip_type);
- 	}
- out_free:
- 	kfree_skb(skb);
-@@ -727,6 +823,7 @@ int btrtl_download_firmware(struct hci_dev *hdev,
- 	case RTL_ROM_LMP_8761A:
- 	case RTL_ROM_LMP_8822B:
- 	case RTL_ROM_LMP_8852A:
-+	case RTL_ROM_LMP_8703B:
- 		return btrtl_setup_rtl8723b(hdev, btrtl_dev);
- 	default:
- 		rtl_dev_info(hdev, "assuming no firmware upload needed");
-@@ -758,6 +855,19 @@ void btrtl_set_quirks(struct hci_dev *hdev, struct btrtl_device_info *btrtl_dev)
- 		rtl_dev_dbg(hdev, "WBS supported not enabled.");
- 		break;
- 	}
-+
-+	switch (btrtl_dev->ic_info->lmp_subver) {
-+	case RTL_ROM_LMP_8703B:
-+		/* 8723CS reports two pages for local ext features,
-+		 * but it doesn't support any features from page 2 -
-+		 * it either responds with garbage or with error status
-+		 */
-+		set_bit(HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE,
-+			&hdev->quirks);
-+		break;
-+	default:
-+		break;
-+	}
- }
- EXPORT_SYMBOL_GPL(btrtl_set_quirks);
- 
-@@ -916,6 +1026,12 @@ MODULE_FIRMWARE("rtl_bt/rtl8723b_fw.bin");
- MODULE_FIRMWARE("rtl_bt/rtl8723b_config.bin");
- MODULE_FIRMWARE("rtl_bt/rtl8723bs_fw.bin");
- MODULE_FIRMWARE("rtl_bt/rtl8723bs_config.bin");
-+MODULE_FIRMWARE("rtl_bt/rtl8723cs_cg_fw.bin");
-+MODULE_FIRMWARE("rtl_bt/rtl8723cs_cg_config.bin");
-+MODULE_FIRMWARE("rtl_bt/rtl8723cs_vf_fw.bin");
-+MODULE_FIRMWARE("rtl_bt/rtl8723cs_vf_config.bin");
-+MODULE_FIRMWARE("rtl_bt/rtl8723cs_xx_fw.bin");
-+MODULE_FIRMWARE("rtl_bt/rtl8723cs_xx_config.bin");
- MODULE_FIRMWARE("rtl_bt/rtl8723ds_fw.bin");
- MODULE_FIRMWARE("rtl_bt/rtl8723ds_config.bin");
- MODULE_FIRMWARE("rtl_bt/rtl8761a_fw.bin");
-diff --git a/drivers/bluetooth/btrtl.h b/drivers/bluetooth/btrtl.h
-index 2c441bda390a..1c6282241d2d 100644
---- a/drivers/bluetooth/btrtl.h
-+++ b/drivers/bluetooth/btrtl.h
-@@ -14,6 +14,11 @@
- 
- struct btrtl_device_info;
- 
-+struct rtl_chip_type_evt {
-+	__u8 status;
-+	__u8 type;
-+} __packed;
-+
- struct rtl_download_cmd {
- 	__u8 index;
- 	__u8 data[RTL_FRAG_LEN];
-diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c
-index 34286ffe0568..f963473d6b3f 100644
---- a/drivers/bluetooth/hci_h5.c
-+++ b/drivers/bluetooth/hci_h5.c
-@@ -1095,6 +1095,8 @@ static const struct of_device_id rtl_bluetooth_of_match[] = {
- 	  .data = (const void *)&h5_data_rtl8723bs },
- 	{ .compatible = "realtek,rtl8723ds-bt",
- 	  .data = (const void *)&h5_data_rtl8723bs },
-+	{ .compatible = "realtek,rtl8723cs-bt",
-+	  .data = (const void *)&h5_data_rtl8723bs },
- #endif
- 	{ },
- };
--- 
-2.33.0
-
diff --git a/0002-arm64-dts-allwinner-add-hdmi-sound-to-pine-devices.patch b/0002-arm64-dts-allwinner-add-hdmi-sound-to-pine-devices.patch
deleted file mode 100644
index c7f6cec..0000000
--- a/0002-arm64-dts-allwinner-add-hdmi-sound-to-pine-devices.patch
+++ /dev/null
@@ -1,133 +0,0 @@
-From 28eb6bdff81f3c858826223ef9a91dd95a5becc0 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Mon, 12 Jul 2021 11:17:18 +0200
-Subject: [PATCH] arm64/dts/allwinner: add hdmi sound to pine devices
-
-Signed-off-by: Dan Johansen <strit@manjaro.org>
----
- .../dts/allwinner/sun50i-a64-pine64-lts.dts   |  8 +++++++
- .../boot/dts/allwinner/sun50i-a64-pine64.dts  |  8 +++++++
- .../dts/allwinner/sun50i-a64-pinebook.dts     |  8 +++++++
- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 21 ++++++++++++++++++-
- 4 files changed, 44 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts
-index 596a25907432..d37b17914937 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts
-@@ -20,6 +20,14 @@ led {
- 	};
- };
- 
-+&i2s2 {
-+	status = "okay";
-+};
-+
- &mmc0 {
- 	broken-cd;		/* card detect is broken on *some* boards */
- };
-+
-+&sound_hdmi {
-+	status = "okay";
-+};
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
-index 2accb5ddf783..17886709b6b4 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
-@@ -107,6 +107,10 @@ &i2c1_pins {
- 	bias-pull-up;
- };
- 
-+&i2s2 {
-+	status = "okay";
-+};
-+
- &mdio {
- 	ext_rmii_phy1: ethernet-phy@1 {
- 		compatible = "ethernet-phy-ieee802.3-c22";
-@@ -270,6 +274,10 @@ &sound {
- 	status = "okay";
- };
- 
-+&sound_hdmi {
-+	status = "okay";
-+};
-+
- /* On Euler connector */
- &spdif {
- 	status = "disabled";
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
-index 34e67f5f8297..129d675c1a99 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
-@@ -137,6 +137,10 @@ &mixer0 {
- 	status = "okay";
- };
- 
-+&i2s2 {
-+	status = "okay";
-+};
-+
- &mmc0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&mmc0_pins>;
-@@ -399,6 +403,10 @@ tcon0_out_anx6345: endpoint {
- 	};
- };
- 
-+&sound_hdmi {
-+	status = "okay";
-+};
-+
- &uart0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&uart0_pb_pins>;
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-index 6ddb717f2f98..393350fb20a0 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-@@ -147,7 +147,7 @@ simple-audio-card,dai-link@0 {
- 			format = "i2s";
- 			frame-master = <&link0_cpu>;
- 			bitclock-master = <&link0_cpu>;
--			mclk-fs = <128>;
-+			mclk-fs = <256>;
- 
- 			link0_cpu: cpu {
- 				sound-dai = <&dai>;
-@@ -900,6 +900,24 @@ i2s2: i2s@1c22800 {
- 			status = "disabled";
- 		};
- 
-+		sound_hdmi: sound_hdmi {
-+			compatible = "simple-audio-card";
-+			simple-audio-card,format = "i2s";
-+			simple-audio-card,name = "allwinner-hdmi";
-+			simple-audio-card,mclk-fs = <256>;
-+			status = "disabled";
-+
-+			simple-audio-card,codec {
-+				sound-dai = <&hdmi>;
-+			};
-+
-+			simple-audio-card,cpu {
-+				sound-dai = <&i2s2>;
-+				dai-tdm-slot-num = <2>;
-+				dai-tdm-slot-width = <32>;
-+			};
-+		};
-+
- 		dai: dai@1c22c00 {
- 			#sound-dai-cells = <0>;
- 			compatible = "allwinner,sun50i-a64-codec-i2s";
-@@ -1197,6 +1215,7 @@ deinterlace: deinterlace@1e00000 {
- 		};
- 
- 		hdmi: hdmi@1ee0000 {
-+            #sound-dai-cells = <0>;
- 			compatible = "allwinner,sun50i-a64-dw-hdmi",
- 				     "allwinner,sun8i-a83t-dw-hdmi";
- 			reg = <0x01ee0000 0x10000>;
--- 
-2.32.0
-
diff --git a/0002-arm64-dts-rockchip-add-usb3-node-to-roc-cc-rock64.patch b/0002-arm64-dts-rockchip-add-usb3-node-to-roc-cc-rock64.patch
deleted file mode 100644
index 527f4f3..0000000
--- a/0002-arm64-dts-rockchip-add-usb3-node-to-roc-cc-rock64.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 81547abb93e469951875dde8dcbda39deeaaef15 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Mon, 10 May 2021 17:29:00 +0200
-Subject: [PATCH] arm64: dts: rockchip: add usb3 node to roc-cc/rock64
-
----
- arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 5 +++++
- arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 5 +++++
- 2 files changed, 10 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-index a05732b59f38..6546d32cc7e6 100644
---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-@@ -371,6 +371,11 @@ &usb_host0_ohci {
- 	status = "okay";
- };
- 
-+&usbdrd3 {
-+	dr_mode = "host";
-+	status = "okay";
-+};
-+
- &vop {
- 	status = "okay";
- };
-diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
-index 3bef1f39bc6e..59a192ca3e60 100644
---- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
-@@ -389,6 +389,11 @@ &usb_host0_ohci {
- 	status = "okay";
- };
- 
-+&usbdrd3 {
-+	dr_mode = "host";
-+	status = "okay";
-+};
-+
- &vop {
- 	status = "okay";
- };
--- 
-2.31.1
-
diff --git a/0002-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz64a.patch b/0002-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz64a.patch
deleted file mode 100644
index dd21265..0000000
--- a/0002-arm64-dts-rockchip-enable-vop2-and-hdmi-tx-on-quartz64a.patch
+++ /dev/null
@@ -1,189 +0,0 @@
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-List-Id: Upstream kernel work for Rockchip platforms
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- linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org
-
-Enable the RK356x Video Output Processor (VOP) 2 on the Pine64
-Quartz64 Model A.
-
-Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
----
- .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 24 +++++++++++++++++++
- 1 file changed, 24 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
-index 4d4b2a301b1a..9fba790c6af4 100644
---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
-@@ -205,6 +205,16 @@ &gmac1m0_clkinout
- 	status = "okay";
- };
- 
-+&hdmi {
-+	status = "okay";
-+	avdd-0v9-supply = <&vdda_0v9>;
-+	avdd-1v8-supply = <&vcc_1v8>;
-+};
-+
-+&hdmi_in_vp0 {
-+	status = "okay";
-+};
-+
- &i2c0 {
- 	status = "okay";
- 
-@@ -546,3 +556,17 @@ bluetooth {
- &uart2 {
- 	status = "okay";
- };
-+
-+&vop {
-+	status = "okay";
-+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+};
-+
-+&vop_mmu {
-+	status = "okay";
-+};
-+
-+&vp0_out_hdmi {
-+	status = "okay";
-+};
diff --git a/0002-usb-typec-altmodes-displayport-Add-hacky-generic-altmode.patch b/0002-usb-typec-altmodes-displayport-Add-hacky-generic-altmode.patch
deleted file mode 100644
index b84fa3f..0000000
--- a/0002-usb-typec-altmodes-displayport-Add-hacky-generic-altmode.patch
+++ /dev/null
@@ -1,120 +0,0 @@
-From fd739ae47f9ea780a1e161a478e241df06eaff7e Mon Sep 17 00:00:00 2001
-From: Tobias Schramm <t.schramm@manjaro.org>
-Date: Thu, 28 May 2020 14:26:27 +0200
-Subject: [PATCH] usb: typec: altmodes: displayport: Add hacky, generic altmode
- detection
-
-Do not mainline, hack.
-
-Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>
----
- drivers/usb/typec/altmodes/displayport.c | 55 ++++++++++++++++++++++--
- 1 file changed, 52 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/usb/typec/altmodes/displayport.c b/drivers/usb/typec/altmodes/displayport.c
-index e62e5e3da01e..a3d03db476aa 100644
---- a/drivers/usb/typec/altmodes/displayport.c
-+++ b/drivers/usb/typec/altmodes/displayport.c
-@@ -9,6 +9,8 @@
-  */
- 
- #include <linux/delay.h>
-+#include <linux/extcon.h>
-+#include <linux/extcon-provider.h>
- #include <linux/mutex.h>
- #include <linux/module.h>
- #include <linux/usb/pd_vdo.h>
-@@ -135,15 +137,53 @@ static int dp_altmode_status_update(struct dp_altmode *dp)
- 	return ret;
- }
- 
-+static void dp_altmode_update_extcon(struct dp_altmode *dp, bool disconnect) {
-+	const struct device *dev = &dp->port->dev;
-+	struct extcon_dev* edev = NULL;
-+
-+	while (dev) {
-+		edev = extcon_find_edev_by_node(dev->of_node);
-+		if(!IS_ERR(edev)) {
-+			break;
-+		}
-+		dev = dev->parent;
-+	}
-+
-+	if (IS_ERR_OR_NULL(edev)) {
-+		return;
-+	}
-+
-+	if (disconnect || !dp->data.conf) {
-+		extcon_set_state_sync(edev, EXTCON_DISP_DP, false);
-+	} else {
-+		union extcon_property_value extcon_true = { .intval = true };
-+		extcon_set_state(edev, EXTCON_DISP_DP, true);
-+		if (DP_CONF_GET_PIN_ASSIGN(dp->data.conf) & DP_PIN_ASSIGN_MULTI_FUNC_MASK) {
-+			extcon_set_state_sync(edev, EXTCON_USB_HOST, true);
-+			extcon_set_property(edev, EXTCON_DISP_DP, EXTCON_PROP_USB_SS,
-+						 extcon_true);
-+		} else {
-+			extcon_set_state_sync(edev, EXTCON_USB_HOST, false);
-+		}
-+		extcon_sync(edev, EXTCON_DISP_DP);
-+		extcon_set_state_sync(edev, EXTCON_USB, false);
-+	}
-+
-+}
-+
- static int dp_altmode_configured(struct dp_altmode *dp)
- {
- 	int ret;
- 
- 	sysfs_notify(&dp->alt->dev.kobj, "displayport", "configuration");
- 
--	if (!dp->data.conf)
-+	if (!dp->data.conf) {
-+		dp_altmode_update_extcon(dp, true);
- 		return typec_altmode_notify(dp->alt, TYPEC_STATE_USB,
- 					    &dp->data);
-+	}
-+
-+	dp_altmode_update_extcon(dp, false);
- 
- 	ret = dp_altmode_notify(dp);
- 	if (ret)
-@@ -170,9 +210,11 @@ static int dp_altmode_configure_vdm(struct dp_altmode *dp, u32 conf)
- 	if (ret) {
- 		if (DP_CONF_GET_PIN_ASSIGN(dp->data.conf))
- 			dp_altmode_notify(dp);
--		else
-+		else {
-+			dp_altmode_update_extcon(dp, true);
- 			typec_altmode_notify(dp->alt, TYPEC_STATE_USB,
- 					     &dp->data);
-+		}
- 	}
- 
- 	return ret;
-@@ -211,6 +253,8 @@ static void dp_altmode_work(struct work_struct *work)
- 	case DP_STATE_EXIT:
- 		if (typec_altmode_exit(dp->alt))
- 			dev_err(&dp->alt->dev, "Exit Mode Failed!\n");
-+		else
-+			dp_altmode_update_extcon(dp, true);
- 		break;
- 	default:
- 		break;
-@@ -521,8 +565,13 @@ int dp_altmode_probe(struct typec_altmode *alt)
- 	if (!(DP_CAP_DFP_D_PIN_ASSIGN(port->vdo) &
- 	      DP_CAP_UFP_D_PIN_ASSIGN(alt->vdo)) &&
- 	    !(DP_CAP_UFP_D_PIN_ASSIGN(port->vdo) &
--	      DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo)))
-+	      DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo))) {
-+		dev_err(&alt->dev, "No compatible pin configuration found:"\
-+			"%04lx -> %04lx, %04lx <- %04lx",
-+			DP_CAP_DFP_D_PIN_ASSIGN(port->vdo), DP_CAP_UFP_D_PIN_ASSIGN(alt->vdo),
-+			DP_CAP_UFP_D_PIN_ASSIGN(port->vdo), DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo));
- 		return -ENODEV;
-+	}
- 
- 	ret = sysfs_create_group(&alt->dev.kobj, &dp_altmode_group);
- 	if (ret)
--- 
-GitLab 
diff --git a/0003-Bluetooth-btrtl-add-support-for-the-RTL8723CS.patch b/0003-Bluetooth-btrtl-add-support-for-the-RTL8723CS.patch
deleted file mode 100644
index 9abb2b2..0000000
--- a/0003-Bluetooth-btrtl-add-support-for-the-RTL8723CS.patch
+++ /dev/null
@@ -1,308 +0,0 @@
-From 1c13fd1ec688ee957b815a2641b9fa91126f7847 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Mon, 1 Mar 2021 09:47:32 +0100
-Subject: [PATCH] Bluetooth-btrtl-add-support-for-the-RTL8723CS
-
----
- drivers/bluetooth/btrtl.c  | 129 ++++++++++++++++++++++++++++++++++++-
- drivers/bluetooth/btrtl.h  |  12 ++++
- drivers/bluetooth/hci_h5.c |   6 ++
- 3 files changed, 144 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c
-index e7fe5fb22753..39ec254f33ac 100644
---- a/drivers/bluetooth/btrtl.c
-+++ b/drivers/bluetooth/btrtl.c
-@@ -17,7 +17,11 @@
- 
- #define VERSION "0.1"
- 
-+#define RTL_CHIP_8723CS_CG	3
-+#define RTL_CHIP_8723CS_VF	4
-+#define RTL_CHIP_8723CS_XX	5
- #define RTL_EPATCH_SIGNATURE	"Realtech"
-+#define RTL_ROM_LMP_8703B	0x8703
- #define RTL_ROM_LMP_8723A	0x1200
- #define RTL_ROM_LMP_8723B	0x8723
- #define RTL_ROM_LMP_8821A	0x8821
-@@ -30,6 +34,7 @@
- #define IC_MATCH_FL_HCIREV	(1 << 1)
- #define IC_MATCH_FL_HCIVER	(1 << 2)
- #define IC_MATCH_FL_HCIBUS	(1 << 3)
-+#define IC_MATCH_FL_CHIP_TYPE	(1 << 4)
- #define IC_INFO(lmps, hcir, hciv, bus) \
- 	.match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_HCIREV | \
- 		       IC_MATCH_FL_HCIVER | IC_MATCH_FL_HCIBUS, \
-@@ -57,6 +62,7 @@ struct id_table {
- 	__u16 hci_rev;
- 	__u8 hci_ver;
- 	__u8 hci_bus;
-+    __u8 chip_type;
- 	bool config_needed;
- 	bool has_rom_version;
- 	char *fw_name;
-@@ -96,6 +102,39 @@ static const struct id_table ic_id_table[] = {
- 	  .fw_name  = "rtl_bt/rtl8723b_fw.bin",
- 	  .cfg_name = "rtl_bt/rtl8723b_config" },
- 
-+	/* 8723CS-CG */
-+	{ .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE |
-+			 IC_MATCH_FL_HCIBUS,
-+	  .lmp_subver = RTL_ROM_LMP_8703B,
-+	  .chip_type = RTL_CHIP_8723CS_CG,
-+	  .hci_bus = HCI_UART,
-+	  .config_needed = true,
-+	  .has_rom_version = true,
-+	  .fw_name  = "rtl_bt/rtl8723cs_cg_fw.bin",
-+	  .cfg_name = "rtl_bt/rtl8723cs_cg_config" },
-+
-+	/* 8723CS-VF */
-+	{ .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE |
-+			 IC_MATCH_FL_HCIBUS,
-+	  .lmp_subver = RTL_ROM_LMP_8703B,
-+	  .chip_type = RTL_CHIP_8723CS_VF,
-+	  .hci_bus = HCI_UART,
-+	  .config_needed = true,
-+	  .has_rom_version = true,
-+	  .fw_name  = "rtl_bt/rtl8723cs_vf_fw.bin",
-+	  .cfg_name = "rtl_bt/rtl8723cs_vf_config" },
-+
-+	/* 8723CS-XX */
-+	{ .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE |
-+			 IC_MATCH_FL_HCIBUS,
-+	  .lmp_subver = RTL_ROM_LMP_8703B,
-+	  .chip_type = RTL_CHIP_8723CS_XX,
-+	  .hci_bus = HCI_UART,
-+	  .config_needed = true,
-+	  .has_rom_version = true,
-+	  .fw_name  = "rtl_bt/rtl8723cs_xx_fw.bin",
-+	  .cfg_name = "rtl_bt/rtl8723cs_xx_config" },
-+
- 	/* 8723D */
- 	{ IC_INFO(RTL_ROM_LMP_8723B, 0xd, 0x8, HCI_USB),
- 	  .config_needed = true,
-@@ -168,7 +207,8 @@ static const struct id_table ic_id_table[] = {
- 	};
- 
- static const struct id_table *btrtl_match_ic(u16 lmp_subver, u16 hci_rev,
--					     u8 hci_ver, u8 hci_bus)
-+					     u8 hci_ver, u8 hci_bus,
-+					     u8 chip_type)
- {
- 	int i;
- 
-@@ -185,6 +225,9 @@ static const struct id_table *btrtl_match_ic(u16 lmp_subver, u16 hci_rev,
- 		if ((ic_id_table[i].match_flags & IC_MATCH_FL_HCIBUS) &&
- 		    (ic_id_table[i].hci_bus != hci_bus))
- 			continue;
-+		if ((ic_id_table[i].match_flags & IC_MATCH_FL_CHIP_TYPE) &&
-+		    (ic_id_table[i].chip_type != chip_type))
-+			continue;
- 
- 		break;
- 	}
-@@ -267,6 +310,7 @@ static int rtlbt_parse_firmware(struct hci_dev *hdev,
- 		{ RTL_ROM_LMP_8723B, 1 },
- 		{ RTL_ROM_LMP_8821A, 2 },
- 		{ RTL_ROM_LMP_8761A, 3 },
-+		{ RTL_ROM_LMP_8703B, 7 },
- 		{ RTL_ROM_LMP_8822B, 8 },
- 		{ RTL_ROM_LMP_8723B, 9 },	/* 8723D */
- 		{ RTL_ROM_LMP_8821A, 10 },	/* 8821C */
-@@ -545,6 +589,48 @@ static int btrtl_setup_rtl8723b(struct hci_dev *hdev,
- 	return ret;
- }
- 
-+static bool rtl_has_chip_type(u16 lmp_subver)
-+{
-+	switch (lmp_subver) {
-+	case RTL_ROM_LMP_8703B:
-+		return true;
-+	default:
-+		break;
-+	}
-+
-+	return  false;
-+}
-+
-+static int rtl_read_chip_type(struct hci_dev *hdev, u8 *type)
-+{
-+	struct rtl_chip_type_evt *chip_type;
-+	struct sk_buff *skb;
-+	const unsigned char cmd_buf[] = {0x00, 0x94, 0xa0, 0x00, 0xb0};
-+
-+	/* Read RTL chip type command */
-+	skb = __hci_cmd_sync(hdev, 0xfc61, 5, cmd_buf, HCI_INIT_TIMEOUT);
-+	if (IS_ERR(skb)) {
-+		rtl_dev_err(hdev, "Read chip type failed (%ld)",
-+			    PTR_ERR(skb));
-+		return PTR_ERR(skb);
-+	}
-+
-+	if (skb->len != sizeof(*chip_type)) {
-+		rtl_dev_err(hdev, "RTL chip type event length mismatch");
-+		kfree_skb(skb);
-+		return -EIO;
-+	}
-+
-+	chip_type = (struct rtl_chip_type_evt *)skb->data;
-+	rtl_dev_info(hdev, "chip_type status=%x type=%x",
-+		     chip_type->status, chip_type->type);
-+
-+	*type = chip_type->type & 0x0f;
-+
-+	kfree_skb(skb);
-+	return 0;
-+}
-+
- void btrtl_free(struct btrtl_device_info *btrtl_dev)
- {
- 	kvfree(btrtl_dev->fw_data);
-@@ -561,7 +647,7 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev,
- 	struct hci_rp_read_local_version *resp;
- 	char cfg_name[40];
- 	u16 hci_rev, lmp_subver;
--	u8 hci_ver;
-+	u8 hci_ver, chip_type = 0;
- 	int ret;
- 	u16 opcode;
- 	u8 cmd[2];
-@@ -631,8 +717,14 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev,
- out_free:
- 	kfree_skb(skb);
- 
-+	if (rtl_has_chip_type(lmp_subver)) {
-+		ret = rtl_read_chip_type(hdev, &chip_type);
-+		if (ret)
-+			goto err_free;
-+	}
-+
- 	btrtl_dev->ic_info = btrtl_match_ic(lmp_subver, hci_rev, hci_ver,
--					    hdev->bus);
-+					    hdev->bus, chip_type);
- 
- 	if (!btrtl_dev->ic_info) {
- 		rtl_dev_info(hdev, "unknown IC info, lmp subver %04x, hci rev %04x, hci ver %04x",
-@@ -711,6 +803,7 @@ int btrtl_download_firmware(struct hci_dev *hdev,
- 	case RTL_ROM_LMP_8761A:
- 	case RTL_ROM_LMP_8822B:
- 	case RTL_ROM_LMP_8852A:
-+	case RTL_ROM_LMP_8703B:
- 		return btrtl_setup_rtl8723b(hdev, btrtl_dev);
- 	default:
- 		rtl_dev_info(hdev, "assuming no firmware upload needed");
-@@ -751,6 +844,12 @@ int btrtl_setup_realtek(struct hci_dev *hdev)
- 		break;
- 	}
- 
-+	if (ret)
-+		goto out_free;
-+ 
-+	btrtl_apply_quirks(hdev, btrtl_dev);
-+
-+out_free:
- 	btrtl_free(btrtl_dev);
- 	return ret;
- }
-@@ -884,6 +983,24 @@ int btrtl_get_uart_settings(struct hci_dev *hdev,
- }
- EXPORT_SYMBOL_GPL(btrtl_get_uart_settings);
- 
-+void btrtl_apply_quirks(struct hci_dev *hdev,
-+			struct btrtl_device_info *btrtl_dev)
-+{
-+	switch (btrtl_dev->ic_info->lmp_subver) {
-+	case RTL_ROM_LMP_8703B:
-+		/* 8723CS reports two pages for local ext features,
-+		 * but it doesn't support any features from page 2 -
-+		 * it either responds with garbage or with error status
-+		 */
-+		set_bit(HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE,
-+			&hdev->quirks);
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+EXPORT_SYMBOL_GPL(btrtl_apply_quirks);
-+
- MODULE_AUTHOR("Daniel Drake <drake@endlessm.com>");
- MODULE_DESCRIPTION("Bluetooth support for Realtek devices ver " VERSION);
- MODULE_VERSION(VERSION);
-@@ -893,6 +1010,12 @@ MODULE_FIRMWARE("rtl_bt/rtl8723b_fw.bin");
- MODULE_FIRMWARE("rtl_bt/rtl8723b_config.bin");
- MODULE_FIRMWARE("rtl_bt/rtl8723bs_fw.bin");
- MODULE_FIRMWARE("rtl_bt/rtl8723bs_config.bin");
-+MODULE_FIRMWARE("rtl_bt/rtl8723cs_cg_fw.bin");
-+MODULE_FIRMWARE("rtl_bt/rtl8723cs_cg_config.bin");
-+MODULE_FIRMWARE("rtl_bt/rtl8723cs_vf_fw.bin");
-+MODULE_FIRMWARE("rtl_bt/rtl8723cs_vf_config.bin");
-+MODULE_FIRMWARE("rtl_bt/rtl8723cs_xx_fw.bin");
-+MODULE_FIRMWARE("rtl_bt/rtl8723cs_xx_config.bin");
- MODULE_FIRMWARE("rtl_bt/rtl8723ds_fw.bin");
- MODULE_FIRMWARE("rtl_bt/rtl8723ds_config.bin");
- MODULE_FIRMWARE("rtl_bt/rtl8761a_fw.bin");
-diff --git a/drivers/bluetooth/btrtl.h b/drivers/bluetooth/btrtl.h
-index 2a582682136d..152ed2ece4c2 100644
---- a/drivers/bluetooth/btrtl.h
-+++ b/drivers/bluetooth/btrtl.h
-@@ -14,6 +14,11 @@
- 
- struct btrtl_device_info;
- 
-+struct rtl_chip_type_evt {
-+	__u8 status;
-+	__u8 type;
-+} __packed;
-+
- struct rtl_download_cmd {
- 	__u8 index;
- 	__u8 data[RTL_FRAG_LEN];
-@@ -60,6 +65,8 @@ int btrtl_get_uart_settings(struct hci_dev *hdev,
- 			    struct btrtl_device_info *btrtl_dev,
- 			    unsigned int *controller_baudrate,
- 			    u32 *device_baudrate, bool *flow_control);
-+void btrtl_apply_quirks(struct hci_dev *hdev,
-+			struct btrtl_device_info *btrtl_dev);
- 
- #else
- 
-@@ -96,6 +103,11 @@ static inline int btrtl_get_uart_settings(struct hci_dev *hdev,
- 					  bool *flow_control)
- {
- 	return -ENOENT;
-+
-+static inline void btrtl_apply_quirks(struct hci_dev *hdev,
-+			struct btrtl_device_info *btrtl_dev)
-+{
-+}
- }
- 
- #endif
-diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c
-index 27e96681d583..35de379cebcd 100644
---- a/drivers/bluetooth/hci_h5.c
-+++ b/drivers/bluetooth/hci_h5.c
-@@ -898,6 +898,10 @@ static int h5_btrtl_setup(struct h5 *h5)
- 	}
- 	/* Give the device some time to set up the new baudrate. */
- 	usleep_range(10000, 20000);
-+	if (err)
-+		goto out_free;
-+
-+	btrtl_apply_quirks(h5->hu->hdev, btrtl_dev);
- 
- 	serdev_device_set_baudrate(h5->hu->serdev, controller_baudrate);
- 	serdev_device_set_flow_control(h5->hu->serdev, flow_control);
-@@ -1029,6 +1033,8 @@ static const struct of_device_id rtl_bluetooth_of_match[] = {
- 	  .data = (const void *)&rtl_vnd },
- 	{ .compatible = "realtek,rtl8723ds-bt",
- 	  .data = (const void *)&rtl_vnd },
-+	{ .compatible = "realtek,rtl8723cs-bt",
-+	  .data = (const void *)&rtl_vnd },
- #endif
- 	{ },
- };
--- 
-2.30.1
-
diff --git a/0003-add-GPU-for-RK356x-SoCs.patch b/0003-add-GPU-for-RK356x-SoCs.patch
deleted file mode 100644
index fe11de9..0000000
--- a/0003-add-GPU-for-RK356x-SoCs.patch
+++ /dev/null
@@ -1,629 +0,0 @@
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- Fri, 26 Nov 2021 07:17:38 -0800 (PST)
-From: Alex Bee <knaerzche@gmail.com>
-To: Heiko Stuebner <heiko@sntech.de>,
-	Rob Herring <robh+dt@kernel.org>
-Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>,
- linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
- linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
- Alex Bee <knaerzche@gmail.com>
-Subject: [PATCH 1/4] dt-bindings: gpu: mali-bifrost: Allow up to two clocks
-Date: Fri, 26 Nov 2021 16:17:26 +0100
-Message-Id: <20211126151729.1026566-2-knaerzche@gmail.com>
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-
-Commit b681af0bc1cc ("drm: panfrost: add optional bus_clock")
-added an optional bus_clock to support Allwinner H6 T-720 GPU.
-Increase the max clock items in the dt-binding to reflect this.
-
-Bifrost GPU in Rockchip RK3568 SoCs also has a core and a bus clock
-and it gets added here in a (very) similar way it was done for
-allwinner,sun50i-h6-mali compatible in arm,mali-midgard binding.
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- .../bindings/gpu/arm,mali-bifrost.yaml        | 20 ++++++++++++++++++-
- 1 file changed, 19 insertions(+), 1 deletion(-)
-
-diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
-index 6f98dd55fb4c..2849a7a97d73 100644
---- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
-+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
-@@ -39,7 +39,14 @@ properties:
-       - const: gpu
- 
-   clocks:
--    maxItems: 1
-+    minItems: 1
-+    maxItems: 2
-+
-+  clock-names:
-+    minItems: 1
-+    items:
-+      - const: core
-+      - const: bus
- 
-   mali-supply: true
- 
-@@ -118,6 +125,17 @@ allOf:
-         power-domains:
-           maxItems: 1
-         sram-supply: false
-+  - if:
-+      properties:
-+        compatible:
-+          contains:
-+            const: rockchip,rk3568-mali
-+    then:
-+      properties:
-+        clocks:
-+          minItems: 2
-+      required:
-+        - clock-names
- 
- examples:
-   - |
-
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-
-From: Ezequiel Garcia <ezequiel@collabora.com>
-
-Rockchip SoCs RK3566 and RK3568 have a Mali Gondul core
-which is based on the Bifrost architecture. It has
-one shader core and two execution engines.
-
-Quoting the datasheet:
-
-Mali-G52 1-Core-2EE
-* Support 1600Mpix/s fill rate when 800MHz clock frequency
-* Support 38.4GLOPs when 800MHz clock frequency
-
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 50 ++++++++++++++++++++++++
- 1 file changed, 50 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-index 46d9552f6028..3b314ccd6c94 100644
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -125,6 +125,40 @@ opp-1800000000 {
- 		};
- 	};
- 
-+	gpu_opp_table: opp-table-1 {
-+		compatible = "operating-points-v2";
-+
-+		opp-200000000 {
-+			opp-hz = /bits/ 64 <200000000>;
-+			opp-microvolt = <825000>;
-+		};
-+
-+		opp-300000000 {
-+			opp-hz = /bits/ 64 <300000000>;
-+			opp-microvolt = <825000>;
-+		};
-+
-+		opp-400000000 {
-+			opp-hz = /bits/ 64 <400000000>;
-+			opp-microvolt = <825000>;
-+		};
-+
-+		opp-600000000 {
-+			opp-hz = /bits/ 64 <600000000>;
-+			opp-microvolt = <825000>;
-+		};
-+
-+		opp-700000000 {
-+			opp-hz = /bits/ 64 <700000000>;
-+			opp-microvolt = <900000>;
-+		};
-+
-+		opp-800000000 {
-+			opp-hz = /bits/ 64 <800000000>;
-+			opp-microvolt = <1000000>;
-+		};
-+	};
-+
- 	firmware {
- 		scmi: scmi {
- 			compatible = "arm,scmi-smc";
-@@ -386,6 +420,22 @@ power-domain@RK3568_PD_RKVENC {
- 		};
- 	};
- 
-+	gpu: gpu@fde60000 {
-+		compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
-+		reg = <0x0 0xfde60000 0x0 0x4000>;
-+
-+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
-+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
-+			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-names = "job", "mmu", "gpu";
-+		clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
-+		clock-names = "core", "bus";
-+		operating-points-v2 = <&gpu_opp_table>;
-+		#cooling-cells = <2>;
-+		power-domains = <&power RK3568_PD_GPU>;
-+		status = "disabled";
-+	};
-+
- 	sdmmc2: mmc@fe000000 {
- 		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
- 		reg = <0x0 0xfe000000 0x0 0x4000>;
-
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- Fri, 26 Nov 2021 07:17:40 -0800 (PST)
-From: Alex Bee <knaerzche@gmail.com>
-To: Heiko Stuebner <heiko@sntech.de>,
-	Rob Herring <robh+dt@kernel.org>
-Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>,
- linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
- linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
- Alex Bee <knaerzche@gmail.com>
-Subject: [PATCH 3/4] arm64: dts: rockchip: Add cooling map / trip points for
- RK356x' GPU
-Date: Fri, 26 Nov 2021 16:17:28 +0100
-Message-Id: <20211126151729.1026566-4-knaerzche@gmail.com>
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- <linux-rockchip.lists.infradead.org>
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-
-RK356x SoCs have a second thermal sensor for the GPU:
-This adds the cooling map / trip points for it to make use of it's
-contribution as a cooling device.
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 27 ++++++++++++++++++++++++
- 1 file changed, 27 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-index 3b314ccd6c94..a67c279c164d 100644
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -960,6 +960,33 @@ gpu_thermal: gpu-thermal {
- 			polling-delay = <1000>; /* milliseconds */
- 
- 			thermal-sensors = <&tsadc 1>;
-+
-+			trips {
-+				gpu_threshold: gpu-threshold {
-+					temperature = <70000>;
-+					hysteresis = <2000>;
-+					type = "passive";
-+				};
-+				gpu_target: gpu-target {
-+					temperature = <75000>;
-+					hysteresis = <2000>;
-+					type = "passive";
-+				};
-+				gpu_crit: gpu-crit {
-+					temperature = <95000>;
-+					hysteresis = <2000>;
-+					type = "critical";
-+				};
-+			};
-+
-+			cooling-maps {
-+				map0 {
-+					trip = <&gpu_target>;
-+					cooling-device =
-+						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+				};
-+			};
-+
- 		};
- 	};
- 
-
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- Fri, 26 Nov 2021 07:17:41 -0800 (PST)
-From: Alex Bee <knaerzche@gmail.com>
-To: Heiko Stuebner <heiko@sntech.de>,
-	Rob Herring <robh+dt@kernel.org>
-Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>,
- linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
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-Subject: [PATCH 4/4] arm64: dts: rockchip: Enable the GPU on Quartz64 Model A
-Date: Fri, 26 Nov 2021 16:17:29 +0100
-Message-Id: <20211126151729.1026566-5-knaerzche@gmail.com>
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-From: Ezequiel Garcia <ezequiel@collabora.com>
-
-Enable the GPU core on the Pine64 Quartz64 Model A.
-
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
-index 4d4b2a301b1a..625489c60622 100644
---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
-@@ -205,6 +205,11 @@ &gmac1m0_clkinout
- 	status = "okay";
- };
- 
-+&gpu {
-+	mali-supply = <&vdd_gpu>;
-+	status = "okay";
-+};
-+
- &i2c0 {
- 	status = "okay";
- 
diff --git a/0003-arm64-allwinner-a64-enable-Bluetooth-On-Pinebook.patch b/0003-arm64-allwinner-a64-enable-Bluetooth-On-Pinebook.patch
deleted file mode 100644
index fdb1487..0000000
--- a/0003-arm64-allwinner-a64-enable-Bluetooth-On-Pinebook.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 3704655d8113ccaae2fb52287fcca5d2900e941b Mon Sep 17 00:00:00 2001
-From: Vasily Khoruzhick <anarsoul@gmail.com>
-Date: Wed, 31 Oct 2018 20:43:26 -0700
-Subject: [PATCH] arm64: allwinner: a64: enable Bluetooth On Pinebook
-
-Pinebook has an RTL8723CS WiFi + BT chip, BT is connected to UART1
-and uses PL5 as device wake GPIO, PL6 as host wake GPIO the I2C
-controlling signals are connected to R_I2C bus.
-
-Enable it in the device tree.
-
-Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
----
- .../arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
-index 64b1c54f87c0a..e63ff271be4e6 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
-@@ -408,6 +408,18 @@
- 	status = "okay";
- };
- 
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
-+	status = "okay";
-+
-+	bluetooth {
-+		compatible = "realtek,rtl8723cs-bt";
-+		device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
-+		host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
-+	};
-+};
-+
- &usb_otg {
- 	dr_mode = "host";
- };
- 
diff --git a/0003-arm64-dts-allwinner-add-ohci-ehci-to-h5-nanopi.patch b/0003-arm64-dts-allwinner-add-ohci-ehci-to-h5-nanopi.patch
deleted file mode 100644
index 72d94f5..0000000
--- a/0003-arm64-dts-allwinner-add-ohci-ehci-to-h5-nanopi.patch
+++ /dev/null
@@ -1,32 +0,0 @@
---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts	2020-06-22 02:12:27.186651478 +0300
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts	2020-06-22 02:43:34.362938364 +0300
-@@ -87,6 +87,14 @@
- 	status = "okay";
- };
- 
-+&ehci1 {
-+	status = "okay";
-+};
-+
-+&ehci2 {
-+	status = "okay";
-+};
-+
- &ehci3 {
- 	status = "okay";
- };
-@@ -142,6 +150,14 @@
- 	status = "okay";
- };
- 
-+&ohci1 {
-+	status = "okay";
-+};
-+
-+&ohci2 {
-+	status = "okay";
-+};
-+
- &ohci3 {
- 	status = "okay";
- };
diff --git a/0003-arm64-dts-rockchip-add-typec-extcon-hack.patch b/0003-arm64-dts-rockchip-add-typec-extcon-hack.patch
deleted file mode 100644
index 42907ad..0000000
--- a/0003-arm64-dts-rockchip-add-typec-extcon-hack.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-diff -up linux-5.15/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts.60~ linux-5.15/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
---- linux-5.15/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts.60~	2021-11-25 20:12:02.649659672 +0100
-+++ linux-5.15/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts	2021-11-25 20:13:10.705935209 +0100
-@@ -385,6 +385,11 @@
- 	};
- };
- 
-+&cdn_dp {
-+	status = "okay";
-+	extcon = <&fusb0>;
-+};
-+
- &cpu_b0 {
- 	cpu-supply = <&vdd_cpu_b>;
- };
-@@ -717,6 +722,9 @@
- 				<PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
- 			try-power-role = "sink";
- 
-+			extcon-cables = <1 2 5 6 9 10 12 44>;
-+			typec-altmodes = <0xff01 1 0x001c0000 1>;
-+
- 			ports {
- 				#address-cells = <1>;
- 				#size-cells = <0>;
-@@ -983,6 +991,7 @@
- };
- 
- &tcphy0 {
-+	extcon = <&fusb0>;
- 	status = "okay";
- };
- 
diff --git a/0004-arm64-allwinner-a64-enable-Bluetooth-On-Pinebook.patch b/0004-arm64-allwinner-a64-enable-Bluetooth-On-Pinebook.patch
deleted file mode 100644
index fdb1487..0000000
--- a/0004-arm64-allwinner-a64-enable-Bluetooth-On-Pinebook.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 3704655d8113ccaae2fb52287fcca5d2900e941b Mon Sep 17 00:00:00 2001
-From: Vasily Khoruzhick <anarsoul@gmail.com>
-Date: Wed, 31 Oct 2018 20:43:26 -0700
-Subject: [PATCH] arm64: allwinner: a64: enable Bluetooth On Pinebook
-
-Pinebook has an RTL8723CS WiFi + BT chip, BT is connected to UART1
-and uses PL5 as device wake GPIO, PL6 as host wake GPIO the I2C
-controlling signals are connected to R_I2C bus.
-
-Enable it in the device tree.
-
-Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
----
- .../arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
-index 64b1c54f87c0a..e63ff271be4e6 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
-@@ -408,6 +408,18 @@
- 	status = "okay";
- };
- 
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
-+	status = "okay";
-+
-+	bluetooth {
-+		compatible = "realtek,rtl8723cs-bt";
-+		device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
-+		host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
-+	};
-+};
-+
- &usb_otg {
- 	dr_mode = "host";
- };
- 
diff --git a/0004-arm64-dts-allwinner-add-ohci-ehci-to-h5-nanopi.patch b/0004-arm64-dts-allwinner-add-ohci-ehci-to-h5-nanopi.patch
deleted file mode 100644
index 72d94f5..0000000
--- a/0004-arm64-dts-allwinner-add-ohci-ehci-to-h5-nanopi.patch
+++ /dev/null
@@ -1,32 +0,0 @@
---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts	2020-06-22 02:12:27.186651478 +0300
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts	2020-06-22 02:43:34.362938364 +0300
-@@ -87,6 +87,14 @@
- 	status = "okay";
- };
- 
-+&ehci1 {
-+	status = "okay";
-+};
-+
-+&ehci2 {
-+	status = "okay";
-+};
-+
- &ehci3 {
- 	status = "okay";
- };
-@@ -142,6 +150,14 @@
- 	status = "okay";
- };
- 
-+&ohci1 {
-+	status = "okay";
-+};
-+
-+&ohci2 {
-+	status = "okay";
-+};
-+
- &ohci3 {
- 	status = "okay";
- };
diff --git a/0004-arm64-dts-allwinner-enable-bluetooth-pinetab-pinepho.patch b/0004-arm64-dts-allwinner-enable-bluetooth-pinetab-pinepho.patch
deleted file mode 100644
index a21861e..0000000
--- a/0004-arm64-dts-allwinner-enable-bluetooth-pinetab-pinepho.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 11b68020edeac7889dd229d3f03191cd0e63f2b2 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Fri, 29 May 2020 18:12:53 +0200
-Subject: [PATCH] arm64-dts-allwinner-enable-bluetooth-pinetab-pinephone
-
----
- .../boot/dts/allwinner/sun50i-a64-pinephone.dtsi   | 14 ++++++++++++++
- .../boot/dts/allwinner/sun50i-a64-pinetab.dts      | 14 ++++++++++++++
- 2 files changed, 28 insertions(+)
-
-diff -up linux-5.16/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi.70~ linux-5.16/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
---- linux-5.16/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi.70~	2022-01-10 12:15:06.241280207 +0100
-+++ linux-5.16/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi	2022-01-10 12:16:19.055587850 +0100
-@@ -490,6 +490,7 @@
- 		device-wake-gpios = <&pio 7 6 GPIO_ACTIVE_LOW>; /* PH6 */
- 		enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
- 		host-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
-+		firmware-postfix = "pinebook";
- 	};
- };
- 
-diff -up linux-5.16/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts.70~ linux-5.16/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
---- linux-5.16/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts.70~	2022-01-09 23:55:34.000000000 +0100
-+++ linux-5.16/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts	2022-01-10 12:15:06.241280207 +0100
-@@ -465,6 +465,20 @@
- 	status = "okay";
- };
- 
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
-+	status = "okay";
-+
-+	bluetooth {
-+		compatible = "realtek,rtl8723cs-bt";
-+		reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
-+		device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
-+		host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
-+		firmware-postfix = "pinebook";
-+	};
-+};
-+
- &usb_otg {
- 	dr_mode = "otg";
- 	status = "okay";
diff --git a/0004-arm64-dts-rockchip-setup-USB-type-c-port-as-dual-data-role.patch b/0004-arm64-dts-rockchip-setup-USB-type-c-port-as-dual-data-role.patch
deleted file mode 100644
index ae406ce..0000000
--- a/0004-arm64-dts-rockchip-setup-USB-type-c-port-as-dual-data-role.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From a8f3e4ffe533f952a468cb8f3d067865bd58144f Mon Sep 17 00:00:00 2001
-From: Tobias Schramm <t.schramm@manjaro.org>
-Date: Sat, 6 Jun 2020 23:45:10 +0200
-Subject: [PATCH] arm64: dts: rockchip: setup USB type c port as dual data role
-
-Some chargers try to put the charged device into device data role.
-Before this commit this condition caused the tcpm state machine to
-issue a hard reset due to a capability missmatch.
-
-Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>
----
- arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
-index c505c88b5d9b..d77dca5524ff 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
-@@ -726,7 +726,7 @@ fusb0: fusb30x@22 {
- 
- 		connector {
- 			compatible = "usb-c-connector";
--			data-role = "host";
-+			data-role = "dual";
- 			label = "USB-C";
- 			op-sink-microwatt = <1000000>;
- 			power-role = "dual";
--- 
-GitLab 
diff --git a/0004-drm-bridge-analogix_dp-Add-enable_psr-param.patch b/0004-drm-bridge-analogix_dp-Add-enable_psr-param.patch
deleted file mode 100644
index f32cea9..0000000
--- a/0004-drm-bridge-analogix_dp-Add-enable_psr-param.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
-index 76736fb8ed94..9735ab71fca7 100644
---- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
-+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
-@@ -35,6 +35,10 @@
- 
- static const bool verify_fast_training;
- 
-+static bool enable_psr = true;
-+module_param(enable_psr, bool, 0644);
-+MODULE_PARM_DESC(enable_psr, "PSR support (1 = enabled (default), 0 = disabled)");
-+
- struct bridge_init {
- 	struct i2c_client *client;
- 	struct device_node *node;
-@@ -979,7 +983,7 @@ static int analogix_dp_commit(struct analogix_dp_device *dp)
- 	if (ret)
- 		return ret;
- 
--	if (analogix_dp_detect_sink_psr(dp)) {
-+	if (enable_psr && analogix_dp_detect_sink_psr(dp)) {
- 		ret = analogix_dp_enable_sink_psr(dp);
- 		if (ret)
- 			return ret;
diff --git a/0004-power-supply-Add-Support-for-RK817-Charger.patch b/0004-power-supply-Add-Support-for-RK817-Charger.patch
deleted file mode 100644
index 94d2ef8..0000000
--- a/0004-power-supply-Add-Support-for-RK817-Charger.patch
+++ /dev/null
@@ -1,1782 +0,0 @@
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-From: Chris Morgan <macroalpha82@gmail.com>
-To: linux-rockchip@lists.infradead.org
-Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
- lee.jones@linaro.org, robh+dt@kernel.org, heiko@sntech.de, sre@kernel.org,
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- Chris Morgan <macromorgan@hotmail.com>
-Subject: [PATCH v4 1/4] dt-bindings: Add Rockchip rk817 battery charger
- support
-Date: Mon, 23 Aug 2021 23:09:52 -0500
-Message-Id: <20210824040955.29112-2-macroalpha82@gmail.com>
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-From: Chris Morgan <macromorgan@hotmail.com>
-
-Create dt-binding documentation to document rk817 battery and charger
-usage. New device-tree properties have been added.
-
-- rockchip,resistor-sense-micro-ohms: The value in microohms of the
-                                      sample resistor.
-- rockchip,sleep-enter-current-microamp: The value in microamps of the
-                                         sleep enter current.
-- rockchip,sleep-filter-current: The value in microamps of the sleep
-                                 filter current.
-
-Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
-Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
----
- .../devicetree/bindings/mfd/rk808.txt         | 38 +++++++++++++++++++
- 1 file changed, 38 insertions(+)
-
-diff --git a/Documentation/devicetree/bindings/mfd/rk808.txt b/Documentation/devicetree/bindings/mfd/rk808.txt
-index 23a17a6663ec..6e1b9fb1f64a 100644
---- a/Documentation/devicetree/bindings/mfd/rk808.txt
-+++ b/Documentation/devicetree/bindings/mfd/rk808.txt
-@@ -77,6 +77,37 @@ Optional RK817 properties:
- - rockchip,mic-in-differential: Telling if the microphone uses differential
- 				mode. Should be under the codec child node.
- 
-+- battery:	The child node for the charger to hold additional properties.
-+		If a battery is not in use, this node can be omitted. If a
-+		battery node is used, the following values are required in the
-+		battery node itself:
-+		rockchip,resistor-sense-micro-ohms,
-+		rockchip,sleep-enter-current-microamp,
-+		rockchip,sleep-filter-current-microamp,
-+		Additionally, a phandle to a monitored-battery node that
-+		contains the following is also required:
-+		charge-full-design-microamp-hours,
-+		charge-term-current-microamp,
-+		constant-charge-current-max-microamp,
-+		constant-charge-voltage-max-microvolt,
-+		voltage-max-design-microvolt,
-+		voltage-min-design-microvolt,
-+		and a valid ocv-capacity table.
-+- rockchip,resistor-sense-micro-ohms: Value in microohms of the battery sense
-+				      resistor. The PMIC only supports values
-+				      of either 10000 or 20000. This value is
-+				      used by the driver to set the correct
-+				      divisor value to translate ADC readings
-+				      into the proper units of measure.
-+- rockchip,sleep-enter-current-microamp: Value in microamps of the sleep enter
-+					 current for the charger. Value is used
-+					 by the driver to calibrate the relax
-+					 threshold.
-+- rockchip,sleep-filter-current-microamp: Value in microamps of the sleep
-+					  filter current for the charger.
-+					  Value is used by the driver to derive
-+					  the sleep sample current.
-+
- Optional RK818 properties:
- - vcc1-supply:  The input supply for DCDC_REG1
- - vcc2-supply:  The input supply for DCDC_REG2
-@@ -459,6 +490,13 @@ Example:
- 			};
- 		};
- 
-+		rk817_battery: battery {
-+			monitored-battery = <&battery_cell>;
-+			rockchip,resistor-sense-micro-ohms = <10000>;
-+			rockchip,sleep-enter-current-microamp = <300000>;
-+			rockchip,sleep-filter-current-microamp = <100000>;
-+		};
-+
- 		rk817_codec: codec {
- 			rockchip,mic-in-differential;
- 		};
-
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-From: Chris Morgan <macroalpha82@gmail.com>
-To: linux-rockchip@lists.infradead.org
-Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
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-Subject: [PATCH v4 2/4] mfd: Add Rockchip rk817 battery charger support
-Date: Mon, 23 Aug 2021 23:09:53 -0500
-Message-Id: <20210824040955.29112-3-macroalpha82@gmail.com>
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-From: Chris Morgan <macromorgan@hotmail.com>
-
-Add rk817 charger support cell to rk808 mfd driver.
-
-Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
-Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
-Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
----
- drivers/mfd/rk808.c       | 16 ++++++-
- include/linux/mfd/rk808.h | 87 +++++++++++++++++++++++++++++++++++++++
- 2 files changed, 102 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c
-index 77ccd31ca1d9..edc779aee667 100644
---- a/drivers/mfd/rk808.c
-+++ b/drivers/mfd/rk808.c
-@@ -66,6 +66,10 @@ static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg)
- 	case RK817_SECONDS_REG ... RK817_WEEKS_REG:
- 	case RK817_RTC_STATUS_REG:
- 	case RK817_CODEC_DTOP_LPT_SRST:
-+	case RK817_GAS_GAUGE_ADC_CONFIG0 ... RK817_GAS_GAUGE_CUR_ADC_K0:
-+	case RK817_PMIC_CHRG_STS:
-+	case RK817_PMIC_CHRG_OUT:
-+	case RK817_PMIC_CHRG_IN:
- 	case RK817_INT_STS_REG0:
- 	case RK817_INT_STS_REG1:
- 	case RK817_INT_STS_REG2:
-@@ -73,7 +77,7 @@ static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg)
- 		return true;
- 	}
- 
--	return true;
-+	return false;
- }
- 
- static const struct regmap_config rk818_regmap_config = {
-@@ -126,6 +130,11 @@ static const struct resource rk817_pwrkey_resources[] = {
- 	DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL),
- };
- 
-+static const struct resource rk817_charger_resources[] = {
-+	DEFINE_RES_IRQ(RK817_IRQ_PLUG_IN),
-+	DEFINE_RES_IRQ(RK817_IRQ_PLUG_OUT),
-+};
-+
- static const struct mfd_cell rk805s[] = {
- 	{ .name = "rk808-clkout", },
- 	{ .name = "rk808-regulator", },
-@@ -165,6 +174,11 @@ static const struct mfd_cell rk817s[] = {
- 		.resources = &rk817_rtc_resources[0],
- 	},
- 	{ .name = "rk817-codec",},
-+	{
-+		.name = "rk817-charger",
-+		.num_resources = ARRAY_SIZE(rk817_charger_resources),
-+		.resources = &rk817_charger_resources[0],
-+	},
- };
- 
- static const struct mfd_cell rk818s[] = {
-diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h
-index a96e6d43ca06..1390432c0222 100644
---- a/include/linux/mfd/rk808.h
-+++ b/include/linux/mfd/rk808.h
-@@ -518,6 +518,74 @@ enum rk809_reg_id {
- #define MIC_DIFF_DIS			(0x0 << 7)
- #define MIC_DIFF_EN			(0x1 << 7)
- 
-+/* RK817 Battery Registers */
-+#define RK817_GAS_GAUGE_ADC_CONFIG0	0x50
-+#define RK817_GG_EN			(0x1 << 7)
-+#define RK817_SYS_VOL_ADC_EN		(0x1 << 6)
-+#define RK817_TS_ADC_EN			(0x1 << 5)
-+#define RK817_USB_VOL_ADC_EN		(0x1 << 4)
-+#define RK817_BAT_VOL_ADC_EN		(0x1 << 3)
-+#define RK817_BAT_CUR_ADC_EN		(0x1 << 2)
-+
-+#define RK817_GAS_GAUGE_ADC_CONFIG1	0x55
-+
-+#define RK817_CUR_CALIB_UPD		(0x1 << 7)
-+#define RK817_VOL_CALIB_UPD		(0x1 << 6)
-+
-+#define RK817_GAS_GAUGE_GG_CON		0x56
-+#define RK817_GAS_GAUGE_GG_STS		0x57
-+
-+#define RK817_RELAX_VOL_UPD		(0x3 << 2)
-+#define RK817_RELAX_STS			(0x1 << 1)
-+
-+#define RK817_GAS_GAUGE_RELAX_THRE_H	0x58
-+#define RK817_GAS_GAUGE_RELAX_THRE_L	0x59
-+#define RK817_GAS_GAUGE_OCV_THRE_VOL	0x62
-+#define RK817_GAS_GAUGE_OCV_VOL_H	0x63
-+#define RK817_GAS_GAUGE_OCV_VOL_L	0x64
-+#define RK817_GAS_GAUGE_PWRON_VOL_H	0x6b
-+#define RK817_GAS_GAUGE_PWRON_VOL_L	0x6c
-+#define RK817_GAS_GAUGE_PWRON_CUR_H	0x6d
-+#define RK817_GAS_GAUGE_PWRON_CUR_L	0x6e
-+#define RK817_GAS_GAUGE_OFF_CNT		0x6f
-+#define RK817_GAS_GAUGE_Q_INIT_H3	0x70
-+#define RK817_GAS_GAUGE_Q_INIT_H2	0x71
-+#define RK817_GAS_GAUGE_Q_INIT_L1	0x72
-+#define RK817_GAS_GAUGE_Q_INIT_L0	0x73
-+#define RK817_GAS_GAUGE_Q_PRES_H3	0x74
-+#define RK817_GAS_GAUGE_Q_PRES_H2	0x75
-+#define RK817_GAS_GAUGE_Q_PRES_L1	0x76
-+#define RK817_GAS_GAUGE_Q_PRES_L0	0x77
-+#define RK817_GAS_GAUGE_BAT_VOL_H	0x78
-+#define RK817_GAS_GAUGE_BAT_VOL_L	0x79
-+#define RK817_GAS_GAUGE_BAT_CUR_H	0x7a
-+#define RK817_GAS_GAUGE_BAT_CUR_L	0x7b
-+#define RK817_GAS_GAUGE_USB_VOL_H	0x7e
-+#define RK817_GAS_GAUGE_USB_VOL_L	0x7f
-+#define RK817_GAS_GAUGE_SYS_VOL_H	0x80
-+#define RK817_GAS_GAUGE_SYS_VOL_L	0x81
-+#define RK817_GAS_GAUGE_Q_MAX_H3	0x82
-+#define RK817_GAS_GAUGE_Q_MAX_H2	0x83
-+#define RK817_GAS_GAUGE_Q_MAX_L1	0x84
-+#define RK817_GAS_GAUGE_Q_MAX_L0	0x85
-+#define RK817_GAS_GAUGE_SLEEP_CON_SAMP_CUR_H	0x8f
-+#define RK817_GAS_GAUGE_SLEEP_CON_SAMP_CUR_L	0x90
-+#define RK817_GAS_GAUGE_CAL_OFFSET_H	0x91
-+#define RK817_GAS_GAUGE_CAL_OFFSET_L	0x92
-+#define RK817_GAS_GAUGE_VCALIB0_H	0x93
-+#define RK817_GAS_GAUGE_VCALIB0_L	0x94
-+#define RK817_GAS_GAUGE_VCALIB1_H	0x95
-+#define RK817_GAS_GAUGE_VCALIB1_L	0x96
-+#define RK817_GAS_GAUGE_IOFFSET_H	0x97
-+#define RK817_GAS_GAUGE_IOFFSET_L	0x98
-+#define RK817_GAS_GAUGE_BAT_R1		0x9a
-+#define RK817_GAS_GAUGE_BAT_R2		0x9b
-+#define RK817_GAS_GAUGE_BAT_R3		0x9c
-+#define RK817_GAS_GAUGE_DATA3		0xa0
-+#define RK817_GAS_GAUGE_DATA4		0xa1
-+#define RK817_GAS_GAUGE_DATA5		0xa2
-+#define RK817_GAS_GAUGE_CUR_ADC_K0	0xb0
-+
- #define RK817_POWER_EN_REG(i)		(0xb1 + (i))
- #define RK817_POWER_SLP_EN_REG(i)	(0xb5 + (i))
- 
-@@ -543,10 +611,29 @@ enum rk809_reg_id {
- #define RK817_LDO_ON_VSEL_REG(idx)	(0xcc + (idx) * 2)
- #define RK817_BOOST_OTG_CFG		(0xde)
- 
-+#define RK817_PMIC_CHRG_OUT		0xe4
-+#define RK817_CHRG_VOL_SEL		(0x07 << 4)
-+#define RK817_CHRG_CUR_SEL		(0x07 << 0)
-+
-+#define RK817_PMIC_CHRG_IN		0xe5
-+#define RK817_USB_VLIM_EN		(0x01 << 7)
-+#define RK817_USB_VLIM_SEL		(0x07 << 4)
-+#define RK817_USB_ILIM_EN		(0x01 << 3)
-+#define RK817_USB_ILIM_SEL		(0x07 << 0)
-+#define RK817_PMIC_CHRG_TERM		0xe6
-+#define RK817_CHRG_TERM_ANA_DIG		(0x01 << 2)
-+#define RK817_CHRG_TERM_ANA_SEL		(0x03 << 0)
-+#define RK817_CHRG_EN			(0x01 << 6)
-+
-+#define RK817_PMIC_CHRG_STS		0xeb
-+#define RK817_CHG_STS			(0x07 << 4)
-+
- #define RK817_ID_MSB			0xed
- #define RK817_ID_LSB			0xee
- 
- #define RK817_SYS_STS			0xf0
-+#define RK817_PLUG_IN_STS		(0x1 << 6)
-+
- #define RK817_SYS_CFG(i)		(0xf1 + (i))
- 
- #define RK817_ON_SOURCE_REG		0xf5
-
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-From: Chris Morgan <macroalpha82@gmail.com>
-To: linux-rockchip@lists.infradead.org
-Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
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-Subject: [PATCH v4 3/4] power: supply: Add charger driver for Rockchip RK817
-Date: Mon, 23 Aug 2021 23:09:54 -0500
-Message-Id: <20210824040955.29112-4-macroalpha82@gmail.com>
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-From: Chris Morgan <macromorgan@hotmail.com>
-
-Add support for the Rockchip rk817 battery charger integrated into the
-rk817 PMIC.
-
-Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
-Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
----
- drivers/power/supply/Kconfig         |   6 +
- drivers/power/supply/Makefile        |   1 +
- drivers/power/supply/rk817_charger.c | 959 +++++++++++++++++++++++++++
- 3 files changed, 966 insertions(+)
- create mode 100644 drivers/power/supply/rk817_charger.c
-
-diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig
-index 11f5368e810e..311130da36ff 100644
---- a/drivers/power/supply/Kconfig
-+++ b/drivers/power/supply/Kconfig
-@@ -666,6 +666,12 @@ config CHARGER_BQ256XX
- 	  charge management and system power path management devices for single
- 	  cell Li-ion and Li-polymer batteries.
- 
-+config CHARGER_RK817
-+	tristate "Rockchip RK817 PMIC Battery Charger"
-+	depends on MFD_RK808
-+	help
-+	  Say Y to include support for Rockchip RK817 Battery Charger.
-+
- config CHARGER_SMB347
- 	tristate "Summit Microelectronics SMB3XX Battery Charger"
- 	depends on I2C
-diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile
-index 33059a91f60c..9497d2105712 100644
---- a/drivers/power/supply/Makefile
-+++ b/drivers/power/supply/Makefile
-@@ -87,6 +87,7 @@ obj-$(CONFIG_CHARGER_BQ2515X)	+= bq2515x_charger.o
- obj-$(CONFIG_CHARGER_BQ25890)	+= bq25890_charger.o
- obj-$(CONFIG_CHARGER_BQ25980)	+= bq25980_charger.o
- obj-$(CONFIG_CHARGER_BQ256XX)	+= bq256xx_charger.o
-+obj-$(CONFIG_CHARGER_RK817)	+= rk817_charger.o
- obj-$(CONFIG_CHARGER_SMB347)	+= smb347-charger.o
- obj-$(CONFIG_CHARGER_TPS65090)	+= tps65090-charger.o
- obj-$(CONFIG_CHARGER_TPS65217)	+= tps65217_charger.o
-diff --git a/drivers/power/supply/rk817_charger.c b/drivers/power/supply/rk817_charger.c
-new file mode 100644
-index 000000000000..34338aebe269
---- /dev/null
-+++ b/drivers/power/supply/rk817_charger.c
-@@ -0,0 +1,959 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Charger Driver for Rockchip rk817
-+ *
-+ * Copyright (c) 2021
-+ *
-+ * Authors: Maya Matuszczyk <maccraft123mc@gmail.com>
-+ *	    Chris Morgan <macromorgan@hotmail.com>
-+ */
-+
-+#include <linux/mfd/rk808.h>
-+#include <linux/irq.h>
-+#include <linux/of_gpio.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+#include <linux/power_supply.h>
-+#include <asm/unaligned.h>
-+
-+/* Charging statuses reported by hardware register */
-+enum rk817_charge_status {
-+	CHRG_OFF,
-+	DEAD_CHRG,
-+	TRICKLE_CHRG,
-+	CC_OR_CV_CHRG,
-+	CHARGE_FINISH,
-+	USB_OVER_VOL,
-+	BAT_TMP_ERR,
-+	BAT_TIM_ERR,
-+};
-+
-+/* Max charging current read to/written from hardware register.
-+ * Note how highest value corresponding to 0x7 is the lowest
-+ * current, this is per the datasheet.
-+ */
-+enum rk817_chg_cur {
-+	CHG_1A,
-+	CHG_1_5A,
-+	CHG_2A,
-+	CHG_2_5A,
-+	CHG_2_75A,
-+	CHG_3A,
-+	CHG_3_5A,
-+	CHG_0_5A,
-+};
-+
-+struct rk817_charger {
-+	struct device *dev;
-+	struct rk808 *rk808;
-+
-+	struct power_supply *bat_ps;
-+	struct power_supply *chg_ps;
-+	bool plugged_in;
-+
-+	/* The voltage_k and voltage_b values are used to calibrate the ADC
-+	 * voltage readings. While they are documented in the BSP kernel and
-+	 * datasheet as voltage_k and voltage_b, there is no further
-+	 * information explaining them in more detail.
-+	 */
-+
-+	uint32_t voltage_k;
-+	uint32_t voltage_b;
-+
-+	/* Storing immutable values of battery here so we can release
-+	 * get_battery_info after the probe and use these values.
-+	 */
-+	int bat_charge_full_design_uah;
-+	int bat_voltage_min_design_uv;
-+	int bat_voltage_max_design_uv;
-+
-+	/* dsoc seems to be difference between full charge and actual charge in
-+	 * BSP stored as a percentage, to the thousandth.
-+	 */
-+	int dsoc;
-+
-+	/* Calibrate the DSOC on a fully charged battery, this way we can use
-+	 * the calibrated DSOC value to correct for columb counter drift.
-+	 */
-+	bool dsoc_cal;
-+
-+	/* Implementation specific properties from device tree */
-+	int res_div;
-+	int sleep_enter_current;
-+	int sleep_filter_current;
-+};
-+
-+/* ADC coefficients extracted from BSP kernel */
-+#define ADC_TO_CURRENT(adc_value, res_div)	\
-+	(adc_value * 172 / res_div)
-+
-+#define CURRENT_TO_ADC(current, samp_res)	\
-+	(current * samp_res / 172)
-+
-+#define CHARGE_TO_ADC(capacity, res_div)	\
-+	(capacity * res_div * 3600 / 172 * 1000)
-+
-+#define ADC_TO_CHARGE_UAH(adc_value, res_div)	\
-+	(adc_value / 3600 * 172 / res_div)
-+
-+#define ADC_TO_CAPACITY(adc_value, res_div)	\
-+	(adc_value / 1000 * 172 / 3600 / res_div)
-+
-+static u8 rk817_chg_cur_to_reg(u32 chg_cur_ma)
-+{
-+	if (chg_cur_ma > 3500)
-+		return CHG_3_5A;
-+	else if (chg_cur_ma > 3000)
-+		return CHG_3A;
-+	else if (chg_cur_ma > 2750)
-+		return CHG_2_75A;
-+	else if (chg_cur_ma > 2500)
-+		return CHG_2_5A;
-+	else if (chg_cur_ma > 2000)
-+		return CHG_2A;
-+	else if (chg_cur_ma > 1500)
-+		return CHG_1_5A;
-+	else if (chg_cur_ma > 1000)
-+		return CHG_1A;
-+	else if (chg_cur_ma > 500)
-+		return CHG_0_5A;
-+	else
-+		return -EINVAL;
-+}
-+
-+static int rk817_chg_cur_from_reg(u8 reg)
-+{
-+	switch (reg) {
-+	case CHG_0_5A:
-+		return 500000;
-+	case CHG_1A:
-+		return 1000000;
-+	case CHG_1_5A:
-+		return 1500000;
-+	case CHG_2A:
-+		return 2000000;
-+	case CHG_2_5A:
-+		return 2500000;
-+	case CHG_2_75A:
-+		return 2750000;
-+	case CHG_3A:
-+		return 3000000;
-+	case CHG_3_5A:
-+		return 3500000;
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
-+static void rk817_bat_calib_vol(struct rk817_charger *charger)
-+{
-+	uint32_t vcalib0 = 0;
-+	uint32_t vcalib1 = 0;
-+	u8 bulk_reg[2];
-+
-+	/* calibrate voltage */
-+	regmap_bulk_read(charger->rk808->regmap, RK817_GAS_GAUGE_VCALIB0_H,
-+			 bulk_reg, 2);
-+	vcalib0 = get_unaligned_be16(bulk_reg);
-+
-+	regmap_bulk_read(charger->rk808->regmap, RK817_GAS_GAUGE_VCALIB1_H,
-+			 bulk_reg, 2);
-+	vcalib1 = get_unaligned_be16(bulk_reg);
-+
-+	/* values were taken from BSP kernel */
-+	charger->voltage_k = (4025 - 2300) * 1000 /
-+			     ((vcalib1 - vcalib0) ? (vcalib1 - vcalib0) : 1);
-+	charger->voltage_b = 4025 - (charger->voltage_k * vcalib1) / 1000;
-+}
-+
-+static void rk817_bat_calib_cur(struct rk817_charger *charger)
-+{
-+	u8 bulk_reg[2];
-+
-+	/* calibrate current */
-+	regmap_bulk_read(charger->rk808->regmap, RK817_GAS_GAUGE_IOFFSET_H,
-+			 bulk_reg, 2);
-+	regmap_bulk_write(charger->rk808->regmap, RK817_GAS_GAUGE_CAL_OFFSET_H,
-+			  bulk_reg, 2);
-+}
-+
-+static int rk817_bat_calib_cap(struct rk817_charger *charger)
-+{
-+	struct rk808 *rk808 = charger->rk808;
-+	int reg, tmp, charge_now, charge_now_adc, dsoc_value;
-+	u8 bulk_reg[4];
-+
-+	/* Calibrate the dsoc on a fully charged battery */
-+
-+	regmap_read(rk808->regmap, RK817_PMIC_CHRG_STS, &reg);
-+	tmp = (reg >> 4) & 0x07;
-+	if (tmp == CHARGE_FINISH) {
-+		/* Read the columb counter */
-+		regmap_bulk_read(rk808->regmap, RK817_GAS_GAUGE_Q_PRES_H3,
-+				 bulk_reg, 4);
-+		charge_now_adc = get_unaligned_be32(bulk_reg);
-+		if (charge_now_adc < 0)
-+			charge_now_adc = 0;
-+		charge_now = ADC_TO_CHARGE_UAH(charge_now_adc, charger->res_div);
-+
-+		/* Get and set our DSOC value with a full charge */
-+
-+		dsoc_value = ((charge_now * 100) /
-+			      (charger->bat_charge_full_design_uah / 1000));
-+
-+		if (!charger->dsoc_cal) {
-+			if (dsoc_value > 100000)
-+				charger->dsoc = 100000;
-+			if (dsoc_value != charger->dsoc) {
-+				charger->dsoc = dsoc_value;
-+				put_unaligned_le24(dsoc_value, bulk_reg);
-+				regmap_bulk_write(rk808->regmap,
-+						  RK817_GAS_GAUGE_BAT_R1,
-+						  bulk_reg, 3);
-+			}
-+			/* Mark our dsoc as calibrated. */
-+			charger->dsoc_cal = 1;
-+		}
-+
-+		/* In the event our columb counter has drifted over the
-+		 * calibrated dsoc of the battery, adjust the columb counter
-+		 * to correct the drift. Don't do this unless we already
-+		 * calibrated our dsoc at a fully charged state.
-+		 */
-+
-+		if (dsoc_value > charger->dsoc && charger->dsoc_cal) {
-+			/* Order of operations matters here to ensure we keep
-+			 * enough precision until the last step to keep from
-+			 * making needless updates to columb counter.
-+			 */
-+			charge_now = charger->dsoc *
-+				     (charger->bat_charge_full_design_uah
-+				     / 1000) / 100;
-+			charge_now_adc = CHARGE_TO_ADC((charge_now / 1000),
-+					 charger->res_div);
-+
-+			put_unaligned_be32(charge_now_adc, bulk_reg);
-+			regmap_bulk_write(rk808->regmap,
-+					  RK817_GAS_GAUGE_Q_INIT_H3,
-+					  bulk_reg, 4);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int rk817_bat_get_prop(struct power_supply *ps,
-+		enum power_supply_property prop,
-+		union power_supply_propval *val)
-+{
-+	struct rk817_charger *charger = power_supply_get_drvdata(ps);
-+	uint32_t tmp = 0;
-+	/* Registers for current is a signed 16bit int */
-+	short int cur = 0;
-+	/* Registers for capacity-now is a signed 32bit int */
-+	int32_t charge_now = 0;
-+	int ret = 0;
-+	int reg = 0;
-+	u8 bulk_reg[4];
-+	struct rk808 *rk808 = charger->rk808;
-+
-+	/* Recalibrate voltage and current readings if we need to BSP does both
-+	 * on CUR_CALIB_UPD, ignoring VOL_CALIB_UPD. Curiously enough, both
-+	 * documentation and the BSP show that you perform an update if bit 7
-+	 * is 1, but you clear the status by writing a 1 to bit 7.
-+	 */
-+	regmap_read(rk808->regmap, RK817_GAS_GAUGE_ADC_CONFIG1, &reg);
-+	tmp = (reg >> 7) & 0x01;
-+	if (tmp) {
-+		rk817_bat_calib_cur(charger);
-+		rk817_bat_calib_vol(charger);
-+		regmap_write_bits(rk808->regmap, RK817_GAS_GAUGE_ADC_CONFIG1,
-+				   RK817_CUR_CALIB_UPD, (1 << 7));
-+	}
-+
-+	rk817_bat_calib_cap(charger);
-+
-+	switch (prop) {
-+	case POWER_SUPPLY_PROP_PRESENT:
-+		regmap_read(rk808->regmap, RK817_PMIC_CHRG_STS, &reg);
-+		val->intval = (reg >> 7);
-+		break;
-+	case POWER_SUPPLY_PROP_STATUS:
-+		if (!charger->plugged_in) {
-+			val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
-+			break;
-+		}
-+		ret = regmap_read(rk808->regmap, RK817_PMIC_CHRG_STS, &reg);
-+		if (ret)
-+			return ret;
-+		tmp = (reg >> 4) & 0x07;
-+		switch (tmp) {
-+		case CHRG_OFF:
-+			val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
-+			break;
-+		/* Dead charge is documented, but not explained. I never
-+		 * observed it but assume it's a pre-charge for a dead
-+		 * battery.
-+		 */
-+		case DEAD_CHRG:
-+		case TRICKLE_CHRG:
-+		case CC_OR_CV_CHRG:
-+			val->intval = POWER_SUPPLY_STATUS_CHARGING;
-+			break;
-+		case CHARGE_FINISH:
-+			val->intval = POWER_SUPPLY_STATUS_FULL;
-+			break;
-+		default:
-+			val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
-+			return -EINVAL;
-+
-+		}
-+		break;
-+	case POWER_SUPPLY_PROP_CHARGE_TYPE:
-+		ret = regmap_read(rk808->regmap, RK817_PMIC_CHRG_STS, &reg);
-+		if (ret)
-+			return ret;
-+		tmp = (reg >> 4) & 0x07;
-+		switch (tmp) {
-+		case CHRG_OFF:
-+		case CHARGE_FINISH:
-+			val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE;
-+			break;
-+		case TRICKLE_CHRG:
-+			val->intval = POWER_SUPPLY_CHARGE_TYPE_TRICKLE;
-+			break;
-+		case DEAD_CHRG:
-+		case CC_OR_CV_CHRG:
-+			val->intval = POWER_SUPPLY_CHARGE_TYPE_STANDARD;
-+			break;
-+		default:
-+			val->intval = POWER_SUPPLY_CHARGE_TYPE_UNKNOWN;
-+			break;
-+		}
-+		break;
-+	case POWER_SUPPLY_PROP_CHARGE_FULL:
-+		val->intval = ((charger->bat_charge_full_design_uah /
-+			       1000) * charger->dsoc) / 100;
-+		break;
-+	case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
-+		val->intval = charger->bat_charge_full_design_uah;
-+		break;
-+	case POWER_SUPPLY_PROP_CHARGE_EMPTY_DESIGN:
-+		val->intval = 0;
-+		break;
-+	case POWER_SUPPLY_PROP_CHARGE_NOW:
-+		regmap_bulk_read(rk808->regmap, RK817_GAS_GAUGE_Q_PRES_H3,
-+				 bulk_reg, 4);
-+		charge_now = get_unaligned_be32(bulk_reg);
-+		if (charge_now < 0)
-+			charge_now = 0;
-+		val->intval = ADC_TO_CHARGE_UAH(charge_now, charger->res_div);
-+		break;
-+	case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
-+		val->intval = charger->bat_voltage_min_design_uv;
-+		break;
-+	case POWER_SUPPLY_PROP_VOLTAGE_BOOT:
-+		regmap_bulk_read(rk808->regmap, RK817_GAS_GAUGE_PWRON_VOL_H,
-+				 bulk_reg, 2);
-+		tmp = get_unaligned_be16(bulk_reg);
-+		val->intval = (charger->voltage_k * tmp) +
-+			       1000 * charger->voltage_b;
-+		break;
-+	case POWER_SUPPLY_PROP_VOLTAGE_AVG:
-+		regmap_bulk_read(rk808->regmap, RK817_GAS_GAUGE_BAT_VOL_H,
-+				 bulk_reg, 2);
-+		tmp = get_unaligned_be16(bulk_reg);
-+		val->intval = (charger->voltage_k * tmp) +
-+			       1000 * charger->voltage_b;
-+		break;
-+	case POWER_SUPPLY_PROP_VOLTAGE_OCV:
-+		regmap_bulk_read(rk808->regmap, RK817_GAS_GAUGE_OCV_VOL_H,
-+				 bulk_reg, 2);
-+		tmp = get_unaligned_be16(bulk_reg);
-+		val->intval = (charger->voltage_k * tmp) +
-+			       1000 * charger->voltage_b;
-+		break;
-+	case POWER_SUPPLY_PROP_CURRENT_BOOT:
-+		regmap_bulk_read(rk808->regmap, RK817_GAS_GAUGE_PWRON_CUR_H,
-+				 bulk_reg, 2);
-+		cur = get_unaligned_be16(bulk_reg);
-+		val->intval = ADC_TO_CURRENT(cur, charger->res_div);
-+		break;
-+	case POWER_SUPPLY_PROP_CURRENT_AVG:
-+		regmap_bulk_read(rk808->regmap, RK817_GAS_GAUGE_BAT_CUR_H,
-+				 bulk_reg, 2);
-+		cur = get_unaligned_be16(bulk_reg);
-+		val->intval = ADC_TO_CURRENT(cur, charger->res_div);
-+		break;
-+	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX:
-+		regmap_read(rk808->regmap, RK817_PMIC_CHRG_OUT, &tmp);
-+		val->intval = rk817_chg_cur_from_reg(tmp & RK817_CHRG_CUR_SEL);
-+		break;
-+	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX:
-+		regmap_read(rk808->regmap, RK817_PMIC_CHRG_OUT, &tmp);
-+		val->intval = ((((tmp & RK817_CHRG_VOL_SEL) >> 4) * 50000) +
-+			       4100000);
-+		break;
-+	case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
-+		val->intval = charger->bat_voltage_max_design_uv;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+	return 0;
-+}
-+
-+static int rk817_chg_get_prop(struct power_supply *ps,
-+			      enum power_supply_property prop,
-+			      union power_supply_propval *val)
-+{
-+	struct rk817_charger *charger = power_supply_get_drvdata(ps);
-+	int vol, tmp = 0;
-+	u8 bulk_reg[2];
-+
-+	switch (prop) {
-+	case POWER_SUPPLY_PROP_ONLINE:
-+		val->intval = charger->plugged_in;
-+		break;
-+	case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
-+		/* max voltage from datasheet at 5.5v (default 5.0v) */
-+		val->intval = 5500000;
-+		break;
-+	case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
-+		/* min voltage from datasheet at 3.8v (default 5.0v) */
-+		val->intval = 3800000;
-+		break;
-+	case POWER_SUPPLY_PROP_VOLTAGE_AVG:
-+		/* Note that on my example hardware (an Odroid Go Advance) the
-+		 * voltage of the power connector is measured on the register
-+		 * labelled USB in the datasheet; I don't know if this is how
-+		 * it is designed or just a quirk of the implementation. I
-+		 * believe this will also measure the voltage of the USB output
-+		 * when in OTG mode, if that is the case we may need to change
-+		 * this in the future to return 0 if the power supply status
-+		 * is offline.
-+		 */
-+		regmap_bulk_read(charger->rk808->regmap,
-+				 RK817_GAS_GAUGE_USB_VOL_H,
-+				 bulk_reg, 2);
-+		tmp = get_unaligned_be16(bulk_reg);
-+		vol = ((charger->voltage_k * tmp / 1000 + charger->voltage_b) *
-+		       60 / 46);
-+		val->intval = vol * 1000;
-+		break;
-+	/* While it's possible that other implementations could use different
-+	 * USB types, the current implementation for this PMIC (the Odroid Go
-+	 * Advance) only uses a dedicated charging port with no rx/tx lines.
-+	 */
-+	case POWER_SUPPLY_PROP_USB_TYPE:
-+		val->intval = POWER_SUPPLY_USB_TYPE_DCP;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+	return 0;
-+
-+}
-+
-+static irqreturn_t rk817_plug_in_isr(int irq, void *cg)
-+{
-+	struct rk817_charger *charger;
-+
-+	charger = (struct rk817_charger *)cg;
-+	charger->plugged_in = 1;
-+	power_supply_changed(charger->chg_ps);
-+	power_supply_changed(charger->bat_ps);
-+	dev_dbg(charger->dev, "Power Cord Inserted\n");
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static irqreturn_t rk817_plug_out_isr(int irq, void *cg)
-+{
-+	struct rk817_charger *charger;
-+	struct rk808 *rk808;
-+
-+	charger = (struct rk817_charger *)cg;
-+	rk808 = charger->rk808;
-+	charger->plugged_in = 0;
-+	power_supply_changed(charger->bat_ps);
-+	power_supply_changed(charger->chg_ps);
-+
-+	/* For some reason the bits of RK817_PMIC_CHRG_IN reset whenever the
-+	 * power cord is unplugged. This was not documented in the BSP kernel
-+	 * or the datasheet and only discovered by trial and error. Set minimum
-+	 * USB input voltage to 4.5v and enable USB voltage input limit.
-+	 */
-+	regmap_write_bits(rk808->regmap, RK817_PMIC_CHRG_IN,
-+			  RK817_USB_VLIM_SEL, (0x05 << 4));
-+	regmap_write_bits(rk808->regmap, RK817_PMIC_CHRG_IN, RK817_USB_VLIM_EN,
-+			  (0x01 << 7));
-+
-+	/* Set average USB input current limit to 1.5A and enable USB current
-+	 * input limit.
-+	 */
-+	regmap_write_bits(rk808->regmap, RK817_PMIC_CHRG_IN,
-+			  RK817_USB_ILIM_SEL, 0x03);
-+	regmap_write_bits(rk808->regmap, RK817_PMIC_CHRG_IN, RK817_USB_ILIM_EN,
-+			  (0x01 << 3));
-+
-+	dev_dbg(charger->dev, "Power Cord Removed\n");
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static enum power_supply_property rk817_bat_props[] = {
-+	POWER_SUPPLY_PROP_PRESENT,
-+	POWER_SUPPLY_PROP_STATUS,
-+	POWER_SUPPLY_PROP_CHARGE_TYPE,
-+	POWER_SUPPLY_PROP_CHARGE_FULL,
-+	POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
-+	POWER_SUPPLY_PROP_CHARGE_EMPTY_DESIGN,
-+	POWER_SUPPLY_PROP_CHARGE_NOW,
-+	POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX,
-+	POWER_SUPPLY_PROP_VOLTAGE_BOOT,
-+	POWER_SUPPLY_PROP_VOLTAGE_AVG,
-+	POWER_SUPPLY_PROP_VOLTAGE_OCV,
-+	POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX,
-+	POWER_SUPPLY_PROP_CURRENT_BOOT,
-+	POWER_SUPPLY_PROP_CURRENT_AVG,
-+	POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
-+	POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
-+};
-+
-+static enum power_supply_property rk817_chg_props[] = {
-+	POWER_SUPPLY_PROP_ONLINE,
-+	POWER_SUPPLY_PROP_USB_TYPE,
-+	POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
-+	POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
-+	POWER_SUPPLY_PROP_VOLTAGE_AVG,
-+};
-+
-+static enum power_supply_usb_type rk817_usb_type[] = {
-+	POWER_SUPPLY_USB_TYPE_DCP,
-+	POWER_SUPPLY_USB_TYPE_UNKNOWN,
-+};
-+
-+static const struct power_supply_desc rk817_bat_desc = {
-+	.name = "rk817-battery",
-+	.type = POWER_SUPPLY_TYPE_BATTERY,
-+	.properties = rk817_bat_props,
-+	.num_properties = ARRAY_SIZE(rk817_bat_props),
-+	.get_property = rk817_bat_get_prop,
-+};
-+
-+static const struct power_supply_desc rk817_chg_desc = {
-+	.name = "rk817-charger",
-+	.type = POWER_SUPPLY_TYPE_USB,
-+	.usb_types = rk817_usb_type,
-+	.num_usb_types = ARRAY_SIZE(rk817_usb_type),
-+	.properties = rk817_chg_props,
-+	.num_properties = ARRAY_SIZE(rk817_chg_props),
-+	.get_property = rk817_chg_get_prop,
-+};
-+
-+static int
-+rk817_read_or_set_full_charge_on_boot(struct rk817_charger *charger,
-+				      struct power_supply_battery_info *bat_info)
-+{
-+	struct rk808 *rk808 = charger->rk808;
-+	u8 bulk_reg[4];
-+	u32 design_charge_mah = (charger->bat_charge_full_design_uah / 1000);
-+	u32 boot_voltage, boot_charge, tmp, full_charge_cap;
-+	int ret, boot_capacity;
-+
-+	/* Read DSOC value if pre-existing. If not, initialize at 100%.
-+	 * Note endianness, also register says it's for resistance,
-+	 * however BSP kernel treats this as an nvram field for the DSOC
-+	 * as best I can tell. Doing the same for backwards compatibility.
-+	 */
-+	ret = regmap_bulk_read(rk808->regmap, RK817_GAS_GAUGE_BAT_R1, bulk_reg, 3);
-+	if (ret < 0)
-+		return ret;
-+	charger->dsoc = get_unaligned_le24(bulk_reg);
-+	/* If we have an invalid DSOC, write 100 (100000) as default. */
-+	if (charger->dsoc < 1000 || charger->dsoc > 100000) {
-+		charger->dsoc = 100000;
-+		put_unaligned_le24(charger->dsoc, bulk_reg);
-+		regmap_bulk_write(rk808->regmap, RK817_GAS_GAUGE_BAT_R1,
-+				  bulk_reg, 3);
-+	}
-+
-+	/* Register appears to be nvram that stores capacity in mAH. Note
-+	 * endianness, keeping consistent with BSP kernel, however it looks
-+	 * like we can use any arbitrary method to store value if we don't care
-+	 * about compatibility. Additionally, it doesn't appear that this value
-+	 * is used for anything, so realistically getting it and setting it is
-+	 * to ensure backward compatibility with BSP and serves no purpose with
-+	 * this driver, and I'm not sure if the BSP driver does anything with
-+	 * this value either.
-+	 */
-+
-+	ret = regmap_bulk_read(rk808->regmap, RK817_GAS_GAUGE_DATA3, bulk_reg, 3);
-+	if (ret < 0)
-+		return ret;
-+
-+	full_charge_cap = get_unaligned_le24(bulk_reg);
-+
-+	/* Sanity checking for values equal to zero or less than would be
-+	 * practical for this device (BSP Kernel assumes 500mAH or less) for
-+	 * practicality purposes.
-+	 */
-+	if (full_charge_cap < 500) {
-+		put_unaligned_le24(design_charge_mah, bulk_reg);
-+		ret = regmap_bulk_write(rk808->regmap, RK817_GAS_GAUGE_DATA3, bulk_reg, 3);
-+		if (ret < 0)
-+			return ret;
-+		dev_info(charger->dev,
-+			 "Invalid NVRAM Data for max charge, setting to design capacity %u uAH\n",
-+			 design_charge_mah*1000);
-+	}
-+
-+	/* Capture boot voltage and look up boot capacity from OCV tables. */
-+
-+	regmap_bulk_read(rk808->regmap, RK817_GAS_GAUGE_PWRON_VOL_H,
-+			 bulk_reg, 2);
-+	tmp = get_unaligned_be16(bulk_reg);
-+	boot_voltage = (charger->voltage_k * tmp) + 1000 * charger->voltage_b;
-+	/* Since only implementation has no working thermistor, assume 20C for
-+	 * OCV lookup. If lookup fails, report error with OCV table.
-+	 */
-+	boot_capacity = power_supply_batinfo_ocv2cap(bat_info, boot_voltage, 20);
-+	if (boot_capacity < 0) {
-+		return dev_err_probe(charger->dev,
-+				     boot_capacity,
-+				     "Unable to read boot charge from OCV table: %i\n",
-+				     boot_capacity);
-+	}
-+
-+	/* Write boot charge to registers, estimate boot charge based on
-+	 * capacity and max charge of battery.
-+	 */
-+	boot_charge = (boot_capacity * charger->bat_charge_full_design_uah) / 100;
-+	tmp = CHARGE_TO_ADC((boot_charge / 1000), charger->res_div);
-+	put_unaligned_be32(tmp, bulk_reg);
-+	regmap_bulk_write(rk808->regmap, RK817_GAS_GAUGE_Q_INIT_H3,
-+			  bulk_reg, 4);
-+
-+	/* Set QMAX value to max design capacity. */
-+	tmp = CHARGE_TO_ADC((charger->bat_charge_full_design_uah / 1000),
-+			    charger->res_div);
-+	put_unaligned_be32(tmp, bulk_reg);
-+	ret = regmap_bulk_write(rk808->regmap, RK817_GAS_GAUGE_Q_MAX_H3,
-+				bulk_reg, 4);
-+	if (ret < 0)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static int rk817_battery_init(struct rk817_charger *charger,
-+			      struct power_supply_battery_info *bat_info)
-+{
-+	struct rk808 *rk808 = charger->rk808;
-+	u32 tmp, max_chg_vol_mv, max_chg_cur_ma;
-+	u8 max_chg_vol_reg, chg_term_i_reg, max_chg_cur_reg;
-+	int ret, chg_term_ma;
-+	u8 bulk_reg[2];
-+
-+	/* Get initial plug state */
-+	regmap_read(rk808->regmap, RK817_SYS_STS, &tmp);
-+	charger->plugged_in = (tmp & RK817_PLUG_IN_STS);
-+
-+	/* Turn on all ADC functions to measure battery, USB, and sys voltage,
-+	 * as well as batt temp. Note only tested implementation so far does
-+	 * not use a battery with a thermistor.
-+	 */
-+	regmap_write(rk808->regmap, RK817_GAS_GAUGE_ADC_CONFIG0, 0xfc);
-+
-+	/* Set relax mode voltage sampling interval and ADC offset calibration
-+	 * interval to 8 minutes to mirror BSP kernel. Set voltage and current
-+	 * modes to average to mirror BSP kernel.
-+	 */
-+	regmap_write(rk808->regmap, RK817_GAS_GAUGE_GG_CON, 0x04);
-+
-+	/* Write relax threshold, derived from sleep enter current. */
-+	tmp = CURRENT_TO_ADC(charger->sleep_enter_current, charger->res_div);
-+	put_unaligned_be16(tmp, bulk_reg);
-+	regmap_bulk_write(rk808->regmap, RK817_GAS_GAUGE_RELAX_THRE_H,
-+			  bulk_reg, 2);
-+
-+	/* Write sleep sample current, derived from sleep filter current. */
-+	tmp = CURRENT_TO_ADC(charger->sleep_filter_current, charger->res_div);
-+	put_unaligned_be16(tmp, bulk_reg);
-+	regmap_bulk_write(rk808->regmap, RK817_GAS_GAUGE_SLEEP_CON_SAMP_CUR_H,
-+			  bulk_reg, 2);
-+
-+	/* Restart battery relax voltage */
-+	regmap_write_bits(rk808->regmap, RK817_GAS_GAUGE_GG_STS,
-+			  RK817_RELAX_VOL_UPD, (0x0 << 2));
-+
-+	/* Set OCV Threshold Voltage to 127.5mV. This was hard coded like this
-+	 * in the BSP.
-+	 */
-+	regmap_write(rk808->regmap, RK817_GAS_GAUGE_OCV_THRE_VOL, 0xff);
-+
-+	/* Set maximum charging voltage to battery max voltage. Trying to be
-+	 * incredibly safe with these value, as setting them wrong could
-+	 * overcharge the battery, which would be very bad.
-+	 */
-+	max_chg_vol_mv = bat_info->constant_charge_voltage_max_uv / 1000;
-+	max_chg_cur_ma = bat_info->constant_charge_current_max_ua / 1000;
-+
-+	if (max_chg_vol_mv < 4100) {
-+		return dev_err_probe(charger->dev, -EINVAL,
-+		       "invalid max charger voltage, value %u unsupported\n",
-+			max_chg_vol_mv * 1000);
-+	}
-+	if (max_chg_vol_mv > 4450) {
-+		dev_info(charger->dev,
-+			 "Setting max charge voltage to 4450000uv\n");
-+		max_chg_vol_mv = 4450;
-+	}
-+
-+	if (max_chg_cur_ma < 500) {
-+		return dev_err_probe(charger->dev, -EINVAL,
-+		       "invalid max charger current, value %u unsupported\n",
-+		       max_chg_cur_ma * 1000);
-+	}
-+	if (max_chg_cur_ma > 3500)
-+		dev_info(charger->dev,
-+			 "Setting max charge current to 3500000ua\n");
-+
-+	/* Now that the values are sanity checked, if we subtract 4100 from the
-+	 * max voltage and divide by 50, we conviently get the exact value for
-+	 * the registers, which are 4.1v, 4.15v, 4.2v, 4.25v, 4.3v, 4.35v,
-+	 * 4.4v, and 4.45v; these correspond to values 0x00 through 0x07.
-+	 */
-+	max_chg_vol_reg = (max_chg_vol_mv - 4100) / 50;
-+
-+	max_chg_cur_reg = rk817_chg_cur_to_reg(max_chg_cur_ma);
-+
-+	if (max_chg_vol_reg < 0 || max_chg_vol_reg > 7) {
-+		return dev_err_probe(charger->dev, -EINVAL,
-+		       "invalid max charger voltage, value %u unsupported\n",
-+		       max_chg_vol_mv * 1000);
-+	}
-+	if (max_chg_cur_reg < 0 || max_chg_cur_reg > 7) {
-+		return dev_err_probe(charger->dev, -EINVAL,
-+		       "invalid max charger current, value %u unsupported\n",
-+		       max_chg_cur_ma * 1000);
-+	}
-+
-+	/* Write the values to the registers, and deliver an emergency warning
-+	 * in the event they are not written correctly.
-+	 */
-+	ret = regmap_write_bits(rk808->regmap, RK817_PMIC_CHRG_OUT,
-+				RK817_CHRG_VOL_SEL, (max_chg_vol_reg << 4));
-+	if (ret) {
-+		dev_emerg(charger->dev,
-+			  "Danger, unable to set max charger voltage: %u\n",
-+			  ret);
-+	}
-+
-+	ret = regmap_write_bits(rk808->regmap, RK817_PMIC_CHRG_OUT,
-+				RK817_CHRG_CUR_SEL, max_chg_cur_reg);
-+	if (ret) {
-+		dev_emerg(charger->dev,
-+			  "Danger, unable to set max charger current: %u\n",
-+			  ret);
-+	}
-+
-+	/* Set charge finishing mode to analog */
-+	regmap_write_bits(rk808->regmap, RK817_PMIC_CHRG_TERM,
-+			  RK817_CHRG_TERM_ANA_DIG, (0x0 << 2));
-+
-+	/* Set charge finish current, warn if value not in range and keep
-+	 * default.
-+	 */
-+	chg_term_ma = bat_info->charge_term_current_ua / 1000;
-+	if (chg_term_ma < 150 || chg_term_ma > 400) {
-+		dev_warn(charger->dev,
-+			 "Invalid charge termination value %u, keeping default\n",
-+			 chg_term_ma * 1000);
-+		chg_term_ma = 200;
-+	}
-+
-+	/* Values of 150ma, 200ma, 300ma, and 400ma correspond to 00, 01, 10,
-+	 * and 11.
-+	 */
-+	chg_term_i_reg = (chg_term_ma - 100) / 100;
-+	regmap_write_bits(rk808->regmap, RK817_PMIC_CHRG_TERM,
-+			  RK817_CHRG_TERM_ANA_SEL, chg_term_i_reg);
-+
-+	ret = rk817_read_or_set_full_charge_on_boot(charger, bat_info);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* Set minimum USB input voltage to 4.5v and enable USB voltage input
-+	 * limit.
-+	 */
-+	regmap_write_bits(rk808->regmap, RK817_PMIC_CHRG_IN,
-+			  RK817_USB_VLIM_SEL, (0x05 << 4));
-+	regmap_write_bits(rk808->regmap, RK817_PMIC_CHRG_IN, RK817_USB_VLIM_EN,
-+			  (0x01 << 7));
-+
-+	/* Set average USB input current limit to 1.5A and enable USB current
-+	 * input limit.
-+	 */
-+	regmap_write_bits(rk808->regmap, RK817_PMIC_CHRG_IN,
-+			  RK817_USB_ILIM_SEL, 0x03);
-+	regmap_write_bits(rk808->regmap, RK817_PMIC_CHRG_IN, RK817_USB_ILIM_EN,
-+			  (0x01 << 3));
-+
-+	return 0;
-+}
-+
-+static int rk817_charger_probe(struct platform_device *pdev)
-+{
-+	struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent);
-+	struct rk817_charger *charger;
-+	struct device_node *node;
-+	struct power_supply_battery_info bat_info = { };
-+	struct device *dev = &pdev->dev;
-+	struct power_supply_config pscfg = {};
-+	int plugin_irq, plugout_irq;
-+	int of_value;
-+	int ret;
-+
-+	node = of_get_child_by_name(dev->parent->of_node, "battery");
-+	if (!node)
-+		return -ENODEV;
-+
-+	charger = devm_kzalloc(&pdev->dev, sizeof(*charger), GFP_KERNEL);
-+	if (!charger)
-+		return -ENOMEM;
-+
-+	charger->rk808 = rk808;
-+
-+	charger->dev = &pdev->dev;
-+	platform_set_drvdata(pdev, charger);
-+
-+	rk817_bat_calib_vol(charger);
-+
-+	pscfg.drv_data = charger;
-+	pscfg.of_node = node;
-+
-+	/* Get sample resistor value. Note only values of 10000 or 20000
-+	 * microohms are allowed. Schematic for my test implementation (an
-+	 * Odroid Go Advance) shows a 10 milliohm resistor for reference.
-+	 */
-+	ret = of_property_read_u32(node, "rockchip,resistor-sense-micro-ohms",
-+				   &of_value);
-+	if (ret < 0) {
-+		return dev_err_probe(dev, ret,
-+				     "Error reading sample resistor value\n");
-+	}
-+	/* Store as a 1 or a 2, since all we really use the value for is as a
-+	 * divisor in some calculations.
-+	 */
-+	charger->res_div = (of_value == 20000) ? 2 : 1;
-+
-+	/* Get sleep enter current value. Not sure what this value is for
-+	 * other than to help calibrate the relax threshold.
-+	 */
-+	ret = of_property_read_u32(node,
-+				   "rockchip,sleep-enter-current-microamp",
-+				   &of_value);
-+	if (ret < 0) {
-+		return dev_err_probe(dev, ret,
-+				     "Error reading sleep enter cur value\n");
-+	}
-+	charger->sleep_enter_current = of_value;
-+
-+	/* Get sleep filter current value */
-+	ret = of_property_read_u32(node,
-+				   "rockchip,sleep-filter-current-microamp",
-+				   &of_value);
-+	if (ret < 0) {
-+		return dev_err_probe(dev, ret,
-+				     "Error reading sleep filter cur value\n");
-+	}
-+
-+	charger->sleep_filter_current = of_value;
-+
-+	charger->bat_ps = devm_power_supply_register(&pdev->dev,
-+						     &rk817_bat_desc, &pscfg);
-+
-+	charger->chg_ps = devm_power_supply_register(&pdev->dev,
-+						     &rk817_chg_desc, &pscfg);
-+
-+	if (IS_ERR(charger->chg_ps))
-+		return dev_err_probe(dev, -EINVAL,
-+				     "Battery failed to probe\n");
-+
-+	if (IS_ERR(charger->chg_ps))
-+		return dev_err_probe(dev, -EINVAL,
-+				     "Charger failed to probe\n");
-+
-+	ret = power_supply_get_battery_info(charger->bat_ps,
-+					    &bat_info);
-+	if (ret) {
-+		return dev_err_probe(dev, ret,
-+				     "Unable to get battery info: %d\n", ret);
-+	}
-+
-+	if ((!bat_info.charge_full_design_uah) ||
-+	    (!bat_info.voltage_min_design_uv) ||
-+	    (!bat_info.voltage_max_design_uv) ||
-+	    (!bat_info.constant_charge_voltage_max_uv) ||
-+	    (!bat_info.constant_charge_current_max_ua) ||
-+	    (!bat_info.charge_term_current_ua)) {
-+		return dev_err_probe(dev, -EINVAL,
-+				     "Required battery info missing.\n");
-+	}
-+
-+	charger->bat_charge_full_design_uah = bat_info.charge_full_design_uah;
-+	charger->bat_voltage_min_design_uv = bat_info.voltage_min_design_uv;
-+	charger->bat_voltage_max_design_uv = bat_info.voltage_max_design_uv;
-+
-+	/* Has to run after power_supply_get_battery_info as it depends on some
-+	 * values discovered from that routine.
-+	 */
-+	ret = rk817_battery_init(charger, &bat_info);
-+	if (ret)
-+		return ret;
-+
-+	power_supply_put_battery_info(charger->bat_ps, &bat_info);
-+
-+	plugin_irq = platform_get_irq(pdev, 0);
-+	if (plugin_irq < 0)
-+		return plugin_irq;
-+
-+	plugout_irq = platform_get_irq(pdev, 1);
-+	if (plugout_irq < 0)
-+		return plugout_irq;
-+
-+	ret = devm_request_threaded_irq(charger->dev, plugin_irq, NULL,
-+					rk817_plug_in_isr,
-+					IRQF_TRIGGER_RISING | IRQF_ONESHOT,
-+					"rk817_plug_in", charger);
-+	if (ret) {
-+		return dev_err_probe(&pdev->dev, ret,
-+				      "plug_in_irq request failed!\n");
-+	}
-+
-+	ret = devm_request_threaded_irq(charger->dev, plugout_irq, NULL,
-+					rk817_plug_out_isr,
-+					IRQF_TRIGGER_RISING | IRQF_ONESHOT,
-+					"rk817_plug_out", charger);
-+	if (ret) {
-+		return dev_err_probe(&pdev->dev, ret,
-+				     "plug_out_irq request failed!\n");
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static struct platform_driver rk817_charger_driver = {
-+	.probe    = rk817_charger_probe,
-+	.driver   = {
-+		.name  = "rk817-charger",
-+	},
-+};
-+module_platform_driver(rk817_charger_driver);
-+
-+MODULE_DESCRIPTION("Battery power supply driver for RK817 PMIC");
-+MODULE_AUTHOR("Maya Matuszczyk <maccraft123mc@gmail.com>");
-+MODULE_LICENSE("GPL");
-
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-From: Chris Morgan <macroalpha82@gmail.com>
-To: linux-rockchip@lists.infradead.org
-Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
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- Chris Morgan <macromorgan@hotmail.com>
-Subject: [PATCH v4 4/4] arm64: dts: rockchip: add rk817 charger to Odroid Go
- Advance
-Date: Mon, 23 Aug 2021 23:09:55 -0500
-Message-Id: <20210824040955.29112-5-macroalpha82@gmail.com>
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-From: Chris Morgan <macromorgan@hotmail.com>
-
-Add the new rk817 charger driver to the Odroid Go Advance. Create a
-monitored battery node as well for the charger to use. All values
-from monitored battery are gathered from the BSP kernel for the
-Odroid Go Advance provided by HardKernel.
-
-Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
-Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
----
- .../boot/dts/rockchip/rk3326-odroid-go2.dts   | 26 +++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
-index 7fc674a99a6c..aff8d0768c5a 100644
---- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
-@@ -52,6 +52,25 @@ backlight: backlight {
- 		pwms = <&pwm1 0 25000 0>;
- 	};
- 
-+	battery_cell: battery-cell {
-+		compatible = "simple-battery";
-+		charge-full-design-microamp-hours = <3000000>;
-+		charge-term-current-microamp = <300000>;
-+		constant-charge-current-max-microamp = <2000000>;
-+		constant-charge-voltage-max-microvolt = <4200000>;
-+		factory-internal-resistance-micro-ohms = <180000>;
-+		voltage-max-design-microvolt = <4100000>;
-+		voltage-min-design-microvolt = <3500000>;
-+
-+		ocv-capacity-celsius = <20>;
-+		ocv-capacity-table-0 =	<4106000 100>, <4071000 95>, <4018000 90>, <3975000 85>,
-+					<3946000 80>, <3908000 75>, <3877000 70>, <3853000 65>,
-+					<3834000 60>, <3816000 55>, <3802000 50>, <3788000 45>,
-+					<3774000 40>, <3760000 35>, <3748000 30>, <3735000 25>,
-+					<3718000 20>, <3697000 15>, <3685000 10>, <3625000 5>,
-+					<3500000 0>;
-+	};
-+
- 	gpio-keys {
- 		compatible = "gpio-keys";
- 		pinctrl-names = "default";
-@@ -462,6 +481,13 @@ regulator-state-mem {
- 			};
- 		};
- 
-+		rk817_battery: battery {
-+			monitored-battery = <&battery_cell>;
-+			rockchip,resistor-sense-micro-ohms = <10000>;
-+			rockchip,sleep-enter-current-microamp = <300000>;
-+			rockchip,sleep-filter-current-microamp = <100000>;
-+		};
-+
- 		rk817_codec: codec {
- 			rockchip,mic-in-differential;
- 		};
diff --git a/0005-drm-bridge-analogix_dp-Add-enable_psr-param.patch b/0005-drm-bridge-analogix_dp-Add-enable_psr-param.patch
deleted file mode 100644
index f32cea9..0000000
--- a/0005-drm-bridge-analogix_dp-Add-enable_psr-param.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
-index 76736fb8ed94..9735ab71fca7 100644
---- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
-+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
-@@ -35,6 +35,10 @@
- 
- static const bool verify_fast_training;
- 
-+static bool enable_psr = true;
-+module_param(enable_psr, bool, 0644);
-+MODULE_PARM_DESC(enable_psr, "PSR support (1 = enabled (default), 0 = disabled)");
-+
- struct bridge_init {
- 	struct i2c_client *client;
- 	struct device_node *node;
-@@ -979,7 +983,7 @@ static int analogix_dp_commit(struct analogix_dp_device *dp)
- 	if (ret)
- 		return ret;
- 
--	if (analogix_dp_detect_sink_psr(dp)) {
-+	if (enable_psr && analogix_dp_detect_sink_psr(dp)) {
- 		ret = analogix_dp_enable_sink_psr(dp);
- 		if (ret)
- 			return ret;
diff --git a/0005-gpu-drm-add-new-display-resolution-2560x1440.patch b/0005-gpu-drm-add-new-display-resolution-2560x1440.patch
deleted file mode 100644
index 514f0ad..0000000
--- a/0005-gpu-drm-add-new-display-resolution-2560x1440.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From ce9ad5ce77cb92963b1ce2cc85d2c024ccec7dae Mon Sep 17 00:00:00 2001
-From: Dongjin Kim <tobetter@gmail.com>
-Date: Thu, 10 Sep 2020 11:01:33 +0900
-Subject: [PATCH] ODROID-COMMON: gpu/drm: add new display resolution 2560x1440
-
-Signed-off-by: Joy Cho <joy.cho@hardkernel.com>
-Signed-off-by: Dongjin Kim <tobetter@gmail.com>
----
- drivers/gpu/drm/meson/meson_vclk.c | 18 ++++++++++++++++++
- drivers/gpu/drm/meson/meson_venc.c |  5 +++--
- 2 files changed, 21 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
-index 0eb86943a3588..e734d1be553d2 100644
---- a/drivers/gpu/drm/meson/meson_vclk.c
-+++ b/drivers/gpu/drm/meson/meson_vclk.c
-@@ -357,6 +357,8 @@ enum {
- 	MESON_VCLK_HDMI_594000,
- /* 2970 /1 /1 /1 /5 /1  => /1 /2 */
- 	MESON_VCLK_HDMI_594000_YUV420,
-+/* 4830 /2 /1 /2 /5 /1  => /1 /1 */
-+	MESON_VCLK_HDMI_241500,
- };
- 
- struct meson_vclk_params {
-@@ -467,6 +469,18 @@ struct meson_vclk_params {
- 		.vid_pll_div = VID_PLL_DIV_5,
- 		.vclk_div = 1,
- 	},
-+	[MESON_VCLK_HDMI_241500] = {
-+		.pll_freq = 4830000,
-+		.phy_freq = 2415000,
-+		.venc_freq = 241500,
-+		.vclk_freq = 241500,
-+		.pixel_freq = 241500,
-+		.pll_od1 = 2,
-+		.pll_od2 = 1,
-+		.pll_od3 = 2,
-+		.vid_pll_div = VID_PLL_DIV_5,
-+		.vclk_div = 1,
-+	},
- 	{ /* sentinel */ },
- };
- 
-@@ -873,6 +887,10 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
- 			m = 0xf7;
- 			frac = vic_alternate_clock ? 0x8148 : 0x10000;
- 			break;
-+		case 4830000:
-+			m = 0xc9;
-+			frac = 0xd560;
-+			break;
- 		}
- 
- 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
-diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
-index f93c725b6f02d..ebe4f2a92fe06 100644
---- a/drivers/gpu/drm/meson/meson_venc.c
-+++ b/drivers/gpu/drm/meson/meson_venc.c
-@@ -866,10 +866,11 @@ meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode)
- 			    DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))
- 		return MODE_BAD;
- 
--	if (mode->hdisplay < 640 || mode->hdisplay > 1920)
-+	/* support higher resolution than 1920x1080 */
-+	if (mode->hdisplay < 640 || mode->hdisplay > 2560)
- 		return MODE_BAD_HVALUE;
- 
--	if (mode->vdisplay < 480 || mode->vdisplay > 1200)
-+	if (mode->vdisplay < 480 || mode->vdisplay > 1600)
- 		return MODE_BAD_VVALUE;
- 
- 	return MODE_OK;
diff --git a/0005-phy-rockchip-inno-usb2-support-rk356x-usb2phy.patch b/0005-phy-rockchip-inno-usb2-support-rk356x-usb2phy.patch
deleted file mode 100644
index d7ca43f..0000000
--- a/0005-phy-rockchip-inno-usb2-support-rk356x-usb2phy.patch
+++ /dev/null
@@ -1,538 +0,0 @@
-diff -up linux-5.16/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts.78~ linux-5.16/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
---- linux-5.16/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts.78~	2022-01-10 12:17:10.631799557 +0100
-+++ linux-5.16/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts	2022-01-10 12:19:17.643302263 +0100
-@@ -124,6 +124,22 @@
- 		vin-supply = <&vcc12v_dcin>;
- 	};
- 
-+	/* all four ports are controlled by one gpio
-+	 * the host ports are sourced from vcc5v0_usb
-+	 * the otg port is sourced from vcc5v0_midu
-+	 */
-+	vcc5v0_usb20_host: vcc5v0_usb20_host {
-+		compatible = "regulator-fixed";
-+		enable-active-high;
-+		gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&vcc5v0_usb20_host_en>;
-+		regulator-name = "vcc5v0_usb20_host";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vcc5v0_usb>;
-+	};
-+
- 	vcc3v3_sd: vcc3v3_sd {
- 		compatible = "regulator-fixed";
- 		enable-active-low;
-@@ -492,6 +508,12 @@
- 		};
- 	};
- 
-+	usb2 {
-+		vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
-+			rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
- 	vcc_sd {
- 		vcc_sd_h: vcc-sd-h {
- 			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-@@ -575,3 +597,33 @@
- &vp0_out_hdmi {
- 	status = "okay";
- };
-+
-+&u2phy1_host {
-+	phy-supply = <&vcc5v0_usb20_host>;
-+	status = "okay";
-+};
-+
-+&u2phy1_otg {
-+	phy-supply = <&vcc5v0_usb20_host>;
-+	status = "okay";
-+};
-+
-+&u2phy1 {
-+	status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+	status = "okay";
-+};
-diff -up linux-5.16/arch/arm64/boot/dts/rockchip/rk356x.dtsi.78~ linux-5.16/arch/arm64/boot/dts/rockchip/rk356x.dtsi
---- linux-5.16/arch/arm64/boot/dts/rockchip/rk356x.dtsi.78~	2022-01-10 12:17:10.631799557 +0100
-+++ linux-5.16/arch/arm64/boot/dts/rockchip/rk356x.dtsi	2022-01-10 12:17:10.634799569 +0100
-@@ -238,6 +238,50 @@
- 		msi-controller;
- 	};
- 
-+	usb_host0_ehci: usb@fd800000 {
-+		compatible = "generic-ehci";
-+		reg = <0x0 0xfd800000 0x0 0x40000>;
-+		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
-+			 <&cru PCLK_USB>;
-+		phys = <&u2phy1_otg>;
-+		phy-names = "usb";
-+		status = "disabled";
-+	};
-+
-+	usb_host0_ohci: usb@fd840000 {
-+		compatible = "generic-ohci";
-+		reg = <0x0 0xfd840000 0x0 0x40000>;
-+		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
-+			 <&cru PCLK_USB>;
-+		phys = <&u2phy1_otg>;
-+		phy-names = "usb";
-+		status = "disabled";
-+	};
-+
-+	usb_host1_ehci: usb@fd880000 {
-+		compatible = "generic-ehci";
-+		reg = <0x0 0xfd880000 0x0 0x40000>;
-+		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
-+			 <&cru PCLK_USB>;
-+		phys = <&u2phy1_host>;
-+		phy-names = "usb";
-+		status = "disabled";
-+	};
-+
-+	usb_host1_ohci: usb@fd8c0000 {
-+		compatible = "generic-ohci";
-+		reg = <0x0 0xfd8c0000 0x0 0x40000>;
-+		interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
-+		clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
-+			 <&cru PCLK_USB>;
-+		phys = <&u2phy1_host>;
-+		phy-names = "usb";
-+		status = "disabled";
-+	};
-+
- 	pmugrf: syscon@fdc20000 {
- 		compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
- 		reg = <0x0 0xfdc20000 0x0 0x10000>;
-@@ -253,6 +297,16 @@
- 		reg = <0x0 0xfdc60000 0x0 0x10000>;
- 	};
- 
-+	usb2phy0_grf: syscon@fdca0000 {
-+		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
-+		reg = <0x0 0xfdca0000 0x0 0x8000>;
-+	};
-+
-+	usb2phy1_grf: syscon@fdca8000 {
-+		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
-+		reg = <0x0 0xfdca8000 0x0 0x8000>;
-+	};
-+
- 	pmucru: clock-controller@fdd00000 {
- 		compatible = "rockchip,rk3568-pmucru";
- 		reg = <0x0 0xfdd00000 0x0 0x1000>;
-@@ -1271,6 +1325,50 @@
- 		status = "disabled";
- 	};
- 
-+	u2phy0: usb2phy@fe8a0000 {
-+		compatible = "rockchip,rk3568-usb2phy";
-+		reg = <0x0 0xfe8a0000 0x0 0x10000>;
-+		clocks = <&pmucru CLK_USBPHY0_REF>;
-+		clock-names = "phyclk";
-+		clock-output-names = "clk_usbphy0_480m";
-+		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
-+		rockchip,usbgrf = <&usb2phy0_grf>;
-+		#clock-cells = <0>;
-+		status = "disabled";
-+
-+		u2phy0_host: host-port {
-+			#phy-cells = <0>;
-+			status = "disabled";
-+		};
-+
-+		u2phy0_otg: otg-port {
-+			#phy-cells = <0>;
-+			status = "disabled";
-+		};
-+	};
-+
-+	u2phy1: usb2phy@fe8b0000 {
-+		compatible = "rockchip,rk3568-usb2phy";
-+		reg = <0x0 0xfe8b0000 0x0 0x10000>;
-+		clocks = <&pmucru CLK_USBPHY1_REF>;
-+		clock-names = "phyclk";
-+		clock-output-names = "clk_usbphy1_480m";
-+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-+		rockchip,usbgrf = <&usb2phy1_grf>;
-+		#clock-cells = <0>;
-+		status = "disabled";
-+
-+		u2phy1_host: host-port {
-+			#phy-cells = <0>;
-+			status = "disabled";
-+		};
-+
-+		u2phy1_otg: otg-port {
-+			#phy-cells = <0>;
-+			status = "disabled";
-+		};
-+	};
-+
- 	pinctrl: pinctrl {
- 		compatible = "rockchip,rk3568-pinctrl";
- 		rockchip,grf = <&grf>;
-diff -up linux-5.16/drivers/phy/rockchip/phy-rockchip-inno-usb2.c.78~ linux-5.16/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
---- linux-5.16/drivers/phy/rockchip/phy-rockchip-inno-usb2.c.78~	2022-01-09 23:55:34.000000000 +0100
-+++ linux-5.16/drivers/phy/rockchip/phy-rockchip-inno-usb2.c	2022-01-10 12:17:10.634799569 +0100
-@@ -204,6 +204,7 @@ struct rockchip_usb2phy_port {
-  * @dcd_retries: The retry count used to track Data contact
-  *		 detection process.
-  * @edev: extcon device for notification registration
-+ * @irq: muxed interrupt for single irq configuration
-  * @phy_cfg: phy register configuration, assigned by driver data.
-  * @ports: phy port instance.
-  */
-@@ -218,6 +219,7 @@ struct rockchip_usb2phy {
- 	enum power_supply_type	chg_type;
- 	u8			dcd_retries;
- 	struct extcon_dev	*edev;
-+	int			irq;
- 	const struct rockchip_usb2phy_cfg	*phy_cfg;
- 	struct rockchip_usb2phy_port	ports[USB2PHY_NUM_PORTS];
- };
-@@ -927,6 +929,102 @@ static irqreturn_t rockchip_usb2phy_otg_
- 		return IRQ_NONE;
- }
- 
-+static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
-+{
-+	struct rockchip_usb2phy *rphy = data;
-+	struct rockchip_usb2phy_port *rport;
-+	irqreturn_t ret = IRQ_NONE;
-+	unsigned int index;
-+
-+	for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
-+		rport = &rphy->ports[index];
-+		if (!rport->phy)
-+			continue;
-+
-+		/* Handle linestate irq for both otg port and host port */
-+		ret = rockchip_usb2phy_linestate_irq(irq, rport);
-+	}
-+
-+	return ret;
-+}
-+
-+static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy,
-+					  struct rockchip_usb2phy_port *rport,
-+					  struct device_node *child_np)
-+{
-+	int ret;
-+
-+	/*
-+	 * If the usb2 phy used combined irq for otg and host port,
-+	 * don't need to init otg and host port irq separately.
-+	 */
-+	if (rphy->irq > 0)
-+		return 0;
-+
-+	switch (rport->port_id) {
-+	case USB2PHY_PORT_HOST:
-+		rport->ls_irq = of_irq_get_byname(child_np, "linestate");
-+		if (rport->ls_irq < 0) {
-+			dev_err(rphy->dev, "no linestate irq provided\n");
-+			return rport->ls_irq;
-+		}
-+
-+		ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
-+						rockchip_usb2phy_linestate_irq,
-+						IRQF_ONESHOT,
-+						"rockchip_usb2phy", rport);
-+		if (ret) {
-+			dev_err(rphy->dev, "failed to request linestate irq handle\n");
-+			return ret;
-+		}
-+		break;
-+	case USB2PHY_PORT_OTG:
-+		/*
-+		 * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
-+		 * interrupts muxed together, so probe the otg-mux interrupt first,
-+		 * if not found, then look for the regular interrupts one by one.
-+		 */
-+		rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
-+		if (rport->otg_mux_irq > 0) {
-+			ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
-+							NULL,
-+							rockchip_usb2phy_otg_mux_irq,
-+							IRQF_ONESHOT,
-+							"rockchip_usb2phy_otg",
-+							rport);
-+			if (ret) {
-+				dev_err(rphy->dev,
-+					"failed to request otg-mux irq handle\n");
-+				return ret;
-+			}
-+		} else {
-+			rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
-+			if (rport->bvalid_irq < 0) {
-+				dev_err(rphy->dev, "no vbus valid irq provided\n");
-+				ret = rport->bvalid_irq;
-+				return ret;
-+			}
-+
-+			ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
-+							NULL,
-+							rockchip_usb2phy_bvalid_irq,
-+							IRQF_ONESHOT,
-+							"rockchip_usb2phy_bvalid",
-+							rport);
-+			if (ret) {
-+				dev_err(rphy->dev,
-+					"failed to request otg-bvalid irq handle\n");
-+				return ret;
-+			}
-+		}
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
- static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
- 					   struct rockchip_usb2phy_port *rport,
- 					   struct device_node *child_np)
-@@ -940,18 +1038,9 @@ static int rockchip_usb2phy_host_port_in
- 	mutex_init(&rport->mutex);
- 	INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
- 
--	rport->ls_irq = of_irq_get_byname(child_np, "linestate");
--	if (rport->ls_irq < 0) {
--		dev_err(rphy->dev, "no linestate irq provided\n");
--		return rport->ls_irq;
--	}
--
--	ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
--					rockchip_usb2phy_linestate_irq,
--					IRQF_ONESHOT,
--					"rockchip_usb2phy", rport);
-+	ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
- 	if (ret) {
--		dev_err(rphy->dev, "failed to request linestate irq handle\n");
-+		dev_err(rphy->dev, "failed to setup host irq\n");
- 		return ret;
- 	}
- 
-@@ -1000,43 +1089,10 @@ static int rockchip_usb2phy_otg_port_ini
- 	INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
- 	INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
- 
--	/*
--	 * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
--	 * interrupts muxed together, so probe the otg-mux interrupt first,
--	 * if not found, then look for the regular interrupts one by one.
--	 */
--	rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
--	if (rport->otg_mux_irq > 0) {
--		ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
--						NULL,
--						rockchip_usb2phy_otg_mux_irq,
--						IRQF_ONESHOT,
--						"rockchip_usb2phy_otg",
--						rport);
--		if (ret) {
--			dev_err(rphy->dev,
--				"failed to request otg-mux irq handle\n");
--			goto out;
--		}
--	} else {
--		rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
--		if (rport->bvalid_irq < 0) {
--			dev_err(rphy->dev, "no vbus valid irq provided\n");
--			ret = rport->bvalid_irq;
--			goto out;
--		}
--
--		ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
--						NULL,
--						rockchip_usb2phy_bvalid_irq,
--						IRQF_ONESHOT,
--						"rockchip_usb2phy_bvalid",
--						rport);
--		if (ret) {
--			dev_err(rphy->dev,
--				"failed to request otg-bvalid irq handle\n");
--			goto out;
--		}
-+	ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
-+	if (ret) {
-+		dev_err(rphy->dev, "failed to init irq for host port\n");
-+		goto out;
- 	}
- 
- 	if (!IS_ERR(rphy->edev)) {
-@@ -1074,12 +1130,19 @@ static int rockchip_usb2phy_probe(struct
- 		return -EINVAL;
- 	}
- 
--	if (!dev->parent || !dev->parent->of_node)
--		return -EINVAL;
-+	if (!dev->parent || !dev->parent->of_node) {
-+		rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
-+		if (IS_ERR(rphy->grf)) {
-+			dev_err(dev, "failed to locate usbgrf\n");
-+			return PTR_ERR(rphy->grf);
-+		}
-+	}
- 
--	rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
--	if (IS_ERR(rphy->grf))
--		return PTR_ERR(rphy->grf);
-+	else {
-+		rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
-+			if (IS_ERR(rphy->grf))
-+				return PTR_ERR(rphy->grf);
-+	}
- 
- 	if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
- 		rphy->usbgrf =
-@@ -1091,16 +1154,26 @@ static int rockchip_usb2phy_probe(struct
- 		rphy->usbgrf = NULL;
- 	}
- 
--	if (of_property_read_u32(np, "reg", &reg)) {
-+	if (of_property_read_u32_index(np, "reg", 0, &reg)) {
- 		dev_err(dev, "the reg property is not assigned in %pOFn node\n",
- 			np);
- 		return -EINVAL;
- 	}
- 
-+	/* support address_cells=2 */
-+	if (reg == 0) {
-+		if (of_property_read_u32_index(np, "reg", 1, &reg)) {
-+			dev_err(dev, "the reg property is not assigned in %pOFn node\n",
-+				np);
-+			return -EINVAL;
-+		}
-+	}
-+
- 	rphy->dev = dev;
- 	phy_cfgs = match->data;
- 	rphy->chg_state = USB_CHG_STATE_UNDEFINED;
- 	rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
-+	rphy->irq = platform_get_irq_optional(pdev, 0);
- 	platform_set_drvdata(pdev, rphy);
- 
- 	ret = rockchip_usb2phy_extcon_register(rphy);
-@@ -1180,6 +1253,20 @@ next_child:
- 	}
- 
- 	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+
-+	if (rphy->irq > 0) {
-+		ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL,
-+						rockchip_usb2phy_irq,
-+						IRQF_ONESHOT,
-+						"rockchip_usb2phy",
-+						rphy);
-+		if (ret) {
-+			dev_err(rphy->dev,
-+				"failed to request usb2phy irq handle\n");
-+			goto put_child;
-+		}
-+	}
-+
- 	return PTR_ERR_OR_ZERO(provider);
- 
- put_child:
-@@ -1418,6 +1505,69 @@ static const struct rockchip_usb2phy_cfg
- 	{ /* sentinel */ }
- };
- 
-+static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
-+	{
-+		.reg = 0xfe8a0000,
-+		.num_ports	= 2,
-+		.clkout_ctl	= { 0x0008, 4, 4, 1, 0 },
-+		.port_cfgs	= {
-+			[USB2PHY_PORT_OTG] = {
-+				.phy_sus	= { 0x0000, 8, 0, 0, 0x1d1 },
-+				.bvalid_det_en	= { 0x0080, 2, 2, 0, 1 },
-+				.bvalid_det_st	= { 0x0084, 2, 2, 0, 1 },
-+				.bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
-+				.utmi_avalid	= { 0x00c0, 10, 10, 0, 1 },
-+				.utmi_bvalid	= { 0x00c0, 9, 9, 0, 1 },
-+			},
-+			[USB2PHY_PORT_HOST] = {
-+				/* Select suspend control from controller */
-+				.phy_sus	= { 0x0004, 8, 0, 0x1d2, 0x1d2 },
-+				.ls_det_en	= { 0x0080, 1, 1, 0, 1 },
-+				.ls_det_st	= { 0x0084, 1, 1, 0, 1 },
-+				.ls_det_clr	= { 0x0088, 1, 1, 0, 1 },
-+				.utmi_ls	= { 0x00c0, 17, 16, 0, 1 },
-+				.utmi_hstdet	= { 0x00c0, 19, 19, 0, 1 }
-+			}
-+		},
-+		.chg_det = {
-+			.opmode		= { 0x0000, 3, 0, 5, 1 },
-+			.cp_det		= { 0x00c0, 24, 24, 0, 1 },
-+			.dcp_det	= { 0x00c0, 23, 23, 0, 1 },
-+			.dp_det		= { 0x00c0, 25, 25, 0, 1 },
-+			.idm_sink_en	= { 0x0008, 8, 8, 0, 1 },
-+			.idp_sink_en	= { 0x0008, 7, 7, 0, 1 },
-+			.idp_src_en	= { 0x0008, 9, 9, 0, 1 },
-+			.rdm_pdwn_en	= { 0x0008, 10, 10, 0, 1 },
-+			.vdm_src_en	= { 0x0008, 12, 12, 0, 1 },
-+			.vdp_src_en	= { 0x0008, 11, 11, 0, 1 },
-+		},
-+	},
-+	{
-+		.reg = 0xfe8b0000,
-+		.num_ports	= 2,
-+		.clkout_ctl	= { 0x0008, 4, 4, 1, 0 },
-+		.port_cfgs	= {
-+			[USB2PHY_PORT_OTG] = {
-+				.phy_sus	= { 0x0000, 8, 0, 0x1d2, 0x1d1 },
-+				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
-+				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
-+				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
-+				.utmi_ls	= { 0x00c0, 5, 4, 0, 1 },
-+				.utmi_hstdet	= { 0x00c0, 7, 7, 0, 1 }
-+			},
-+			[USB2PHY_PORT_HOST] = {
-+				.phy_sus	= { 0x0004, 8, 0, 0x1d2, 0x1d1 },
-+				.ls_det_en	= { 0x0080, 1, 1, 0, 1 },
-+				.ls_det_st	= { 0x0084, 1, 1, 0, 1 },
-+				.ls_det_clr	= { 0x0088, 1, 1, 0, 1 },
-+				.utmi_ls	= { 0x00c0, 17, 16, 0, 1 },
-+				.utmi_hstdet	= { 0x00c0, 19, 19, 0, 1 }
-+			}
-+		},
-+	},
-+	{ /* sentinel */ }
-+};
-+
- static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
- 	{
- 		.reg = 0x100,
-@@ -1467,6 +1617,7 @@ static const struct of_device_id rockchi
- 	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
- 	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
- 	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
-+	{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
- 	{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
- 	{}
- };
diff --git a/0005-staging-add-rtl8723cs-driver.patch b/0005-staging-add-rtl8723cs-driver.patch
deleted file mode 100644
index 98fb40c..0000000
--- a/0005-staging-add-rtl8723cs-driver.patch
+++ /dev/null
@@ -1,446905 +0,0 @@
-From 415584383fd80577852ff63c905b8ccb64feb009 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Mon, 13 Sep 2021 15:06:35 +0200
-Subject: [PATCH] staging: add rtl8723cs driver
-
-Signed-off-by: Dan Johansen <strit@manjaro.org>
----
- drivers/staging/Kconfig                       |     2 +
- drivers/staging/Makefile                      |     1 +
- drivers/staging/rtl8723cs/Kconfig             |     8 +
- drivers/staging/rtl8723cs/Makefile            |  2522 +++
- drivers/staging/rtl8723cs/clean               |     5 +
- .../staging/rtl8723cs/core/crypto/aes-ccm.c   |   211 +
- .../staging/rtl8723cs/core/crypto/aes-ctr.c   |    70 +
- .../staging/rtl8723cs/core/crypto/aes-gcm.c   |   326 +
- .../rtl8723cs/core/crypto/aes-internal-enc.c  |   129 +
- .../rtl8723cs/core/crypto/aes-internal.c      |   843 +
- .../staging/rtl8723cs/core/crypto/aes-omac1.c |   172 +
- .../staging/rtl8723cs/core/crypto/aes-siv.c   |   207 +
- drivers/staging/rtl8723cs/core/crypto/aes.h   |    21 +
- drivers/staging/rtl8723cs/core/crypto/aes_i.h |   125 +
- .../staging/rtl8723cs/core/crypto/aes_siv.h   |    21 +
- .../staging/rtl8723cs/core/crypto/aes_wrap.h  |    73 +
- drivers/staging/rtl8723cs/core/crypto/ccmp.c  |   384 +
- drivers/staging/rtl8723cs/core/crypto/gcmp.c  |   193 +
- .../rtl8723cs/core/crypto/rtw_crypto_wrap.c   |    85 +
- .../rtl8723cs/core/crypto/rtw_crypto_wrap.h   |    64 +
- .../rtl8723cs/core/crypto/sha256-internal.c   |   230 +
- .../rtl8723cs/core/crypto/sha256-prf.c        |   109 +
- .../staging/rtl8723cs/core/crypto/sha256.c    |   104 +
- .../staging/rtl8723cs/core/crypto/sha256.h    |    30 +
- .../staging/rtl8723cs/core/crypto/sha256_i.h  |    25 +
- .../rtl8723cs/core/crypto/wlancrypto_wrap.h   |    34 +
- .../staging/rtl8723cs/core/efuse/rtw_efuse.c  |  3575 ++++
- .../staging/rtl8723cs/core/mesh/rtw_mesh.c    |  4392 ++++
- .../staging/rtl8723cs/core/mesh/rtw_mesh.h    |   537 +
- .../rtl8723cs/core/mesh/rtw_mesh_hwmp.c       |  1518 ++
- .../rtl8723cs/core/mesh/rtw_mesh_hwmp.h       |    60 +
- .../rtl8723cs/core/mesh/rtw_mesh_pathtbl.c    |  1242 ++
- .../rtl8723cs/core/mesh/rtw_mesh_pathtbl.h    |   211 +
- .../rtl8723cs/core/monitor/rtw_radiotap.c     |   615 +
- .../rtl8723cs/core/monitor/rtw_radiotap.h     |    63 +
- drivers/staging/rtl8723cs/core/rtw_ap.c       |  5992 ++++++
- .../staging/rtl8723cs/core/rtw_beamforming.c  |  2194 ++
- drivers/staging/rtl8723cs/core/rtw_br_ext.c   |  1308 ++
- drivers/staging/rtl8723cs/core/rtw_bt_mp.c    |  1575 ++
- drivers/staging/rtl8723cs/core/rtw_btcoex.c   |  1817 ++
- .../rtl8723cs/core/rtw_btcoex_wifionly.c      |    47 +
- drivers/staging/rtl8723cs/core/rtw_chplan.c   |  2516 +++
- drivers/staging/rtl8723cs/core/rtw_chplan.h   |    95 +
- drivers/staging/rtl8723cs/core/rtw_cmd.c      |  5675 ++++++
- drivers/staging/rtl8723cs/core/rtw_debug.c    |  8306 ++++++++
- drivers/staging/rtl8723cs/core/rtw_eeprom.c   |   329 +
- drivers/staging/rtl8723cs/core/rtw_ft.c       |   668 +
- .../staging/rtl8723cs/core/rtw_ieee80211.c    |  3166 +++
- drivers/staging/rtl8723cs/core/rtw_io.c       |   952 +
- .../staging/rtl8723cs/core/rtw_ioctl_query.c  |    19 +
- .../staging/rtl8723cs/core/rtw_ioctl_set.c    |   929 +
- drivers/staging/rtl8723cs/core/rtw_iol.c      |   388 +
- drivers/staging/rtl8723cs/core/rtw_mbo.c      |   803 +
- drivers/staging/rtl8723cs/core/rtw_mem.c      |   171 +
- drivers/staging/rtl8723cs/core/rtw_mi.c       |  1546 ++
- drivers/staging/rtl8723cs/core/rtw_mlme.c     |  5955 ++++++
- drivers/staging/rtl8723cs/core/rtw_mlme_ext.c | 16603 ++++++++++++++++
- drivers/staging/rtl8723cs/core/rtw_mp.c       |  3991 ++++
- drivers/staging/rtl8723cs/core/rtw_odm.c      |   600 +
- drivers/staging/rtl8723cs/core/rtw_p2p.c      |  5017 +++++
- drivers/staging/rtl8723cs/core/rtw_pwrctrl.c  |  2958 +++
- drivers/staging/rtl8723cs/core/rtw_recv.c     |  4763 +++++
- drivers/staging/rtl8723cs/core/rtw_rf.c       |  2437 +++
- drivers/staging/rtl8723cs/core/rtw_rm.c       |  2825 +++
- drivers/staging/rtl8723cs/core/rtw_rm_fsm.c   |  1017 +
- drivers/staging/rtl8723cs/core/rtw_rm_util.c  |   501 +
- drivers/staging/rtl8723cs/core/rtw_roch.c     |   591 +
- drivers/staging/rtl8723cs/core/rtw_rson.c     |   592 +
- drivers/staging/rtl8723cs/core/rtw_sdio.c     |   157 +
- drivers/staging/rtl8723cs/core/rtw_security.c |  2872 +++
- drivers/staging/rtl8723cs/core/rtw_sreset.c   |   320 +
- drivers/staging/rtl8723cs/core/rtw_sta_mgt.c  |  1369 ++
- drivers/staging/rtl8723cs/core/rtw_swcrypto.c |   296 +
- drivers/staging/rtl8723cs/core/rtw_tdls.c     |  3516 ++++
- drivers/staging/rtl8723cs/core/rtw_vht.c      |  1141 ++
- drivers/staging/rtl8723cs/core/rtw_wapi.c     |  1320 ++
- .../staging/rtl8723cs/core/rtw_wapi_sms4.c    |   922 +
- .../staging/rtl8723cs/core/rtw_wlan_util.c    |  5662 ++++++
- drivers/staging/rtl8723cs/core/rtw_wnm.c      |  1098 +
- drivers/staging/rtl8723cs/core/rtw_xmit.c     |  6638 ++++++
- drivers/staging/rtl8723cs/core/wds/rtw_wds.c  |   786 +
- drivers/staging/rtl8723cs/core/wds/rtw_wds.h  |    65 +
- drivers/staging/rtl8723cs/hal/HalPwrSeqCmd.c  |   185 +
- .../rtl8723cs/hal/btc/btc_basic_types.h       |    53 +
- .../rtl8723cs/hal/btc/halbtc8703b1ant.c       |  4622 +++++
- .../rtl8723cs/hal/btc/halbtc8703b1ant.h       |   445 +
- .../staging/rtl8723cs/hal/btc/halbtcoutsrc.h  |  2164 ++
- .../staging/rtl8723cs/hal/btc/mp_precomp.h    |   168 +
- .../staging/rtl8723cs/hal/efuse/efuse_mask.h  |   188 +
- .../efuse/rtl8703b/HalEfuseMask8703B_PCIE.c   |    94 +
- .../efuse/rtl8703b/HalEfuseMask8703B_PCIE.h   |    33 +
- .../efuse/rtl8703b/HalEfuseMask8703B_SDIO.c   |    95 +
- .../efuse/rtl8703b/HalEfuseMask8703B_SDIO.h   |    34 +
- .../efuse/rtl8703b/HalEfuseMask8703B_USB.c    |    92 +
- .../efuse/rtl8703b/HalEfuseMask8703B_USB.h    |    34 +
- drivers/staging/rtl8723cs/hal/hal_btcoex.c    |  6651 +++++++
- .../rtl8723cs/hal/hal_btcoex_wifionly.c       |   279 +
- drivers/staging/rtl8723cs/hal/hal_com.c       | 16525 +++++++++++++++
- drivers/staging/rtl8723cs/hal/hal_com_c2h.h   |   142 +
- .../staging/rtl8723cs/hal/hal_com_phycfg.c    |  6275 ++++++
- drivers/staging/rtl8723cs/hal/hal_dm.c        |  1937 ++
- drivers/staging/rtl8723cs/hal/hal_dm.h        |   121 +
- drivers/staging/rtl8723cs/hal/hal_dm_acs.c    |   577 +
- drivers/staging/rtl8723cs/hal/hal_dm_acs.h    |   173 +
- drivers/staging/rtl8723cs/hal/hal_halmac.c    |  5927 ++++++
- drivers/staging/rtl8723cs/hal/hal_halmac.h    |   252 +
- .../staging/rtl8723cs/hal/hal_hci/hal_sdio.c  |   885 +
- .../rtl8723cs/hal/hal_hci/hal_sdio_coex.c     |    35 +
- drivers/staging/rtl8723cs/hal/hal_intf.c      |  2350 +++
- drivers/staging/rtl8723cs/hal/hal_mcc.c       |  4078 ++++
- drivers/staging/rtl8723cs/hal/hal_mp.c        |  2642 +++
- drivers/staging/rtl8723cs/hal/hal_phy.c       |   257 +
- drivers/staging/rtl8723cs/hal/led/hal_led.c   |   254 +
- .../staging/rtl8723cs/hal/led/hal_sdio_led.c  |  2014 ++
- .../rtl8723cs/hal/phydm/ap_makefile.mk        |   237 +
- .../staging/rtl8723cs/hal/phydm/halhwimg.h    |   137 +
- .../rtl8723cs/hal/phydm/halrf/halphyrf_ap.c   |  1674 ++
- .../rtl8723cs/hal/phydm/halrf/halphyrf_ap.h   |   170 +
- .../rtl8723cs/hal/phydm/halrf/halphyrf_ce.c   |  1180 ++
- .../rtl8723cs/hal/phydm/halrf/halphyrf_ce.h   |   123 +
- .../rtl8723cs/hal/phydm/halrf/halphyrf_iot.c  |   664 +
- .../rtl8723cs/hal/phydm/halrf/halphyrf_iot.h  |   137 +
- .../rtl8723cs/hal/phydm/halrf/halphyrf_win.c  |  1108 ++
- .../rtl8723cs/hal/phydm/halrf/halphyrf_win.h  |   132 +
- .../staging/rtl8723cs/hal/phydm/halrf/halrf.c |  4230 ++++
- .../staging/rtl8723cs/hal/phydm/halrf/halrf.h |   802 +
- .../rtl8723cs/hal/phydm/halrf/halrf_debug.c   |   395 +
- .../rtl8723cs/hal/phydm/halrf/halrf_debug.h   |   140 +
- .../rtl8723cs/hal/phydm/halrf/halrf_dpk.h     |   150 +
- .../hal/phydm/halrf/halrf_features.h          |    43 +
- .../rtl8723cs/hal/phydm/halrf/halrf_iqk.h     |   151 +
- .../rtl8723cs/hal/phydm/halrf/halrf_kfree.c   |  3705 ++++
- .../rtl8723cs/hal/phydm/halrf/halrf_kfree.h   |   296 +
- .../hal/phydm/halrf/halrf_powertracking.c     |   186 +
- .../hal/phydm/halrf/halrf_powertracking.h     |    43 +
- .../hal/phydm/halrf/halrf_powertracking_ap.c  |  1290 ++
- .../hal/phydm/halrf/halrf_powertracking_ap.h  |   407 +
- .../hal/phydm/halrf/halrf_powertracking_ce.c  |   955 +
- .../hal/phydm/halrf/halrf_powertracking_ce.h  |   331 +
- .../hal/phydm/halrf/halrf_powertracking_iot.c |  1004 +
- .../hal/phydm/halrf/halrf_powertracking_iot.h |   372 +
- .../hal/phydm/halrf/halrf_powertracking_win.c |   924 +
- .../hal/phydm/halrf/halrf_powertracking_win.h |   306 +
- .../rtl8723cs/hal/phydm/halrf/halrf_psd.c     |   531 +
- .../rtl8723cs/hal/phydm/halrf/halrf_psd.h     |    50 +
- .../hal/phydm/halrf/halrf_txgapcal.c          |   300 +
- .../hal/phydm/halrf/halrf_txgapcal.h          |    31 +
- .../hal/phydm/halrf/rtl8703b/halrf_8703b.c    |  1857 ++
- .../hal/phydm/halrf/rtl8703b/halrf_8703b.h    |    89 +
- .../staging/rtl8723cs/hal/phydm/mp_precomp.h  |    24 +
- drivers/staging/rtl8723cs/hal/phydm/phydm.c   |  3820 ++++
- drivers/staging/rtl8723cs/hal/phydm/phydm.h   |  1566 ++
- drivers/staging/rtl8723cs/hal/phydm/phydm.mk  |   248 +
- .../rtl8723cs/hal/phydm/phydm_adaptivity.c    |   845 +
- .../rtl8723cs/hal/phydm/phydm_adaptivity.h    |   126 +
- .../rtl8723cs/hal/phydm/phydm_adc_sampling.c  |  1647 ++
- .../rtl8723cs/hal/phydm/phydm_adc_sampling.h  |   172 +
- .../rtl8723cs/hal/phydm/phydm_antdect.c       |   888 +
- .../rtl8723cs/hal/phydm/phydm_antdect.h       |    78 +
- .../rtl8723cs/hal/phydm/phydm_antdiv.c        |  6552 ++++++
- .../rtl8723cs/hal/phydm/phydm_antdiv.h        |   547 +
- .../staging/rtl8723cs/hal/phydm/phydm_api.c   |  3763 ++++
- .../staging/rtl8723cs/hal/phydm/phydm_api.h   |   228 +
- .../rtl8723cs/hal/phydm/phydm_auto_dbg.c      |   725 +
- .../rtl8723cs/hal/phydm/phydm_auto_dbg.h      |   115 +
- .../rtl8723cs/hal/phydm/phydm_beamforming.c   |  1989 ++
- .../rtl8723cs/hal/phydm/phydm_beamforming.h   |   363 +
- .../rtl8723cs/hal/phydm/phydm_cck_pd.c        |  1906 ++
- .../rtl8723cs/hal/phydm/phydm_cck_pd.h        |   201 +
- .../hal/phydm/phydm_cck_rx_pathdiv.c          |   163 +
- .../hal/phydm/phydm_cck_rx_pathdiv.h          |    67 +
- .../staging/rtl8723cs/hal/phydm/phydm_ccx.c   |  3290 +++
- .../staging/rtl8723cs/hal/phydm/phydm_ccx.h   |   428 +
- .../rtl8723cs/hal/phydm/phydm_cfotracking.c   |   623 +
- .../rtl8723cs/hal/phydm/phydm_cfotracking.h   |    74 +
- .../staging/rtl8723cs/hal/phydm/phydm_debug.c |  6156 ++++++
- .../staging/rtl8723cs/hal/phydm/phydm_debug.h |   484 +
- .../staging/rtl8723cs/hal/phydm/phydm_dfs.c   |  2193 ++
- .../staging/rtl8723cs/hal/phydm/phydm_dfs.h   |   191 +
- .../staging/rtl8723cs/hal/phydm/phydm_dig.c   |  3516 ++++
- .../staging/rtl8723cs/hal/phydm/phydm_dig.h   |   380 +
- .../rtl8723cs/hal/phydm/phydm_direct_bf.c     |   366 +
- .../rtl8723cs/hal/phydm/phydm_direct_bf.h     |    44 +
- .../hal/phydm/phydm_dynamictxpower.c          |   795 +
- .../hal/phydm/phydm_dynamictxpower.h          |   142 +
- .../rtl8723cs/hal/phydm/phydm_features.h      |    82 +
- .../rtl8723cs/hal/phydm/phydm_features_ap.h   |   227 +
- .../rtl8723cs/hal/phydm/phydm_features_ce.h   |   245 +
- .../hal/phydm/phydm_features_ce2_kernel.h     |    84 +
- .../rtl8723cs/hal/phydm/phydm_features_iot.h  |   177 +
- .../rtl8723cs/hal/phydm/phydm_features_win.h  |   215 +
- .../rtl8723cs/hal/phydm/phydm_hwconfig.c      |  1674 ++
- .../rtl8723cs/hal/phydm/phydm_hwconfig.h      |    79 +
- .../rtl8723cs/hal/phydm/phydm_interface.c     |  1480 ++
- .../rtl8723cs/hal/phydm/phydm_interface.h     |   328 +
- .../rtl8723cs/hal/phydm/phydm_lna_sat.c       |  1688 ++
- .../rtl8723cs/hal/phydm/phydm_lna_sat.h       |   196 +
- .../rtl8723cs/hal/phydm/phydm_math_lib.c      |   290 +
- .../rtl8723cs/hal/phydm/phydm_math_lib.h      |   120 +
- .../staging/rtl8723cs/hal/phydm/phydm_mp.c    |   408 +
- .../staging/rtl8723cs/hal/phydm/phydm_mp.h    |    83 +
- .../rtl8723cs/hal/phydm/phydm_noisemonitor.c  |   467 +
- .../rtl8723cs/hal/phydm/phydm_noisemonitor.h  |    48 +
- .../rtl8723cs/hal/phydm/phydm_pathdiv.c       |  1113 ++
- .../rtl8723cs/hal/phydm/phydm_pathdiv.h       |   145 +
- .../rtl8723cs/hal/phydm/phydm_phystatus.c     |  3245 +++
- .../rtl8723cs/hal/phydm/phydm_phystatus.h     |  1250 ++
- .../hal/phydm/phydm_pmac_tx_setting.c         |   584 +
- .../hal/phydm/phydm_pmac_tx_setting.h         |   111 +
- .../rtl8723cs/hal/phydm/phydm_pow_train.c     |   171 +
- .../rtl8723cs/hal/phydm/phydm_pow_train.h     |    84 +
- .../rtl8723cs/hal/phydm/phydm_pre_define.h    |  1020 +
- .../rtl8723cs/hal/phydm/phydm_precomp.h       |   651 +
- .../rtl8723cs/hal/phydm/phydm_primary_cca.c   |   173 +
- .../rtl8723cs/hal/phydm/phydm_primary_cca.h   |    76 +
- .../staging/rtl8723cs/hal/phydm/phydm_psd.c   |   564 +
- .../staging/rtl8723cs/hal/phydm/phydm_psd.h   |    68 +
- .../rtl8723cs/hal/phydm/phydm_rainfo.c        |  2431 +++
- .../rtl8723cs/hal/phydm/phydm_rainfo.h        |   333 +
- .../staging/rtl8723cs/hal/phydm/phydm_reg.h   |   243 +
- .../rtl8723cs/hal/phydm/phydm_regdefine11ac.h |   109 +
- .../rtl8723cs/hal/phydm/phydm_regdefine11n.h  |   220 +
- .../rtl8723cs/hal/phydm/phydm_regtable.h      |  1109 ++
- .../rtl8723cs/hal/phydm/phydm_rssi_monitor.c  |   189 +
- .../rtl8723cs/hal/phydm/phydm_rssi_monitor.h  |    58 +
- .../rtl8723cs/hal/phydm/phydm_smt_ant.c       |  2277 +++
- .../rtl8723cs/hal/phydm/phydm_smt_ant.h       |   210 +
- .../staging/rtl8723cs/hal/phydm/phydm_soml.c  |  1451 ++
- .../staging/rtl8723cs/hal/phydm/phydm_soml.h  |   199 +
- .../staging/rtl8723cs/hal/phydm/phydm_types.h |   413 +
- .../hal/phydm/rtl8703b/halhwimg8703b_bb.c     |   823 +
- .../hal/phydm/rtl8703b/halhwimg8703b_bb.h     |    51 +
- .../hal/phydm/rtl8703b/halhwimg8703b_mac.c    |   288 +
- .../hal/phydm/rtl8703b/halhwimg8703b_mac.h    |    33 +
- .../hal/phydm/rtl8703b/halhwimg8703b_rf.c     |   997 +
- .../hal/phydm/rtl8703b/halhwimg8703b_rf.h     |    69 +
- .../hal/phydm/rtl8703b/phydm_regconfig8703b.c |   167 +
- .../hal/phydm/rtl8703b/phydm_regconfig8703b.h |    47 +
- .../hal/phydm/rtl8703b/phydm_rtl8703b.c       |    53 +
- .../hal/phydm/rtl8703b/phydm_rtl8703b.h       |    21 +
- .../hal/phydm/rtl8703b/version_rtl8703b.h     |    24 +
- .../rtl8723cs/hal/phydm/sd4_phydm_2_kernel.mk |   188 +
- .../rtl8723cs/hal/phydm/txbf/halcomtxbf.c     |   520 +
- .../rtl8723cs/hal/phydm/txbf/halcomtxbf.h     |   183 +
- .../rtl8723cs/hal/phydm/txbf/haltxbf8192e.c   |   384 +
- .../rtl8723cs/hal/phydm/txbf/haltxbf8192e.h   |    71 +
- .../rtl8723cs/hal/phydm/txbf/haltxbf8814a.c   |   675 +
- .../rtl8723cs/hal/phydm/txbf/haltxbf8814a.h   |    77 +
- .../rtl8723cs/hal/phydm/txbf/haltxbf8822b.c   |  1088 +
- .../rtl8723cs/hal/phydm/txbf/haltxbf8822b.h   |    78 +
- .../hal/phydm/txbf/haltxbfinterface.c         |  1484 ++
- .../hal/phydm/txbf/haltxbfinterface.h         |   167 +
- .../rtl8723cs/hal/phydm/txbf/haltxbfjaguar.c  |   509 +
- .../rtl8723cs/hal/phydm/txbf/haltxbfjaguar.h  |    78 +
- .../hal/phydm/txbf/phydm_hal_txbf_api.c       |   759 +
- .../hal/phydm/txbf/phydm_hal_txbf_api.h       |    89 +
- .../rtl8723cs/hal/rtl8703b/Hal8703BPwrSeq.c   |    84 +
- .../rtl8723cs/hal/rtl8703b/hal8703b_fw.c      |  7973 ++++++++
- .../rtl8723cs/hal/rtl8703b/hal8703b_fw.h      |    40 +
- .../rtl8723cs/hal/rtl8703b/rtl8703b_cmd.c     |   507 +
- .../rtl8723cs/hal/rtl8703b/rtl8703b_dm.c      |   307 +
- .../hal/rtl8703b/rtl8703b_hal_init.c          |  5565 ++++++
- .../rtl8723cs/hal/rtl8703b/rtl8703b_phycfg.c  |  1282 ++
- .../rtl8723cs/hal/rtl8703b/rtl8703b_rf6052.c  |   232 +
- .../rtl8723cs/hal/rtl8703b/rtl8703b_rxdesc.c  |    63 +
- .../rtl8723cs/hal/rtl8703b/rtl8703b_sreset.c  |   100 +
- .../hal/rtl8703b/sdio/rtl8703bs_led.c         |   123 +
- .../hal/rtl8703b/sdio/rtl8703bs_recv.c        |   476 +
- .../hal/rtl8703b/sdio/rtl8703bs_xmit.c        |   739 +
- .../hal/rtl8703b/sdio/sdio_halinit.c          |  1668 ++
- .../rtl8723cs/hal/rtl8703b/sdio/sdio_ops.c    |  1669 ++
- drivers/staging/rtl8723cs/ifcfg-wlan0         |     4 +
- .../rtl8723cs/include/Hal8188EPhyCfg.h        |   249 +
- .../rtl8723cs/include/Hal8188EPhyReg.h        |  1100 +
- .../rtl8723cs/include/Hal8188EPwrSeq.h        |   170 +
- .../rtl8723cs/include/Hal8188FPhyCfg.h        |   120 +
- .../rtl8723cs/include/Hal8188FPhyReg.h        |  1165 ++
- .../rtl8723cs/include/Hal8188FPwrSeq.h        |   212 +
- .../rtl8723cs/include/Hal8192EPhyCfg.h        |   136 +
- .../rtl8723cs/include/Hal8192EPhyReg.h        |  1146 ++
- .../rtl8723cs/include/Hal8192EPwrSeq.h        |   169 +
- .../rtl8723cs/include/Hal8192FPhyCfg.h        |   115 +
- .../rtl8723cs/include/Hal8192FPhyReg.h        |  1134 ++
- .../rtl8723cs/include/Hal8192FPwrSeq.h        |   220 +
- .../rtl8723cs/include/Hal8703BPhyCfg.h        |   116 +
- .../rtl8723cs/include/Hal8703BPhyReg.h        |  1133 ++
- .../rtl8723cs/include/Hal8703BPwrSeq.h        |   198 +
- .../rtl8723cs/include/Hal8710BPhyCfg.h        |   111 +
- .../rtl8723cs/include/Hal8710BPhyReg.h        |  1134 ++
- .../rtl8723cs/include/Hal8710BPwrSeq.h        |   167 +
- .../rtl8723cs/include/Hal8723BPhyCfg.h        |   116 +
- .../rtl8723cs/include/Hal8723BPhyReg.h        |  1131 ++
- .../rtl8723cs/include/Hal8723BPwrSeq.h        |   246 +
- .../rtl8723cs/include/Hal8723DPhyCfg.h        |   115 +
- .../rtl8723cs/include/Hal8723DPhyReg.h        |  1134 ++
- .../rtl8723cs/include/Hal8723DPwrSeq.h        |   206 +
- .../staging/rtl8723cs/include/Hal8723PwrSeq.h |   183 +
- .../staging/rtl8723cs/include/Hal8812PhyCfg.h |   134 +
- .../staging/rtl8723cs/include/Hal8812PhyReg.h |   735 +
- .../staging/rtl8723cs/include/Hal8812PwrSeq.h |   208 +
- .../staging/rtl8723cs/include/Hal8814PhyCfg.h |   236 +
- .../staging/rtl8723cs/include/Hal8814PhyReg.h |   863 +
- .../staging/rtl8723cs/include/Hal8814PwrSeq.h |   231 +
- .../rtl8723cs/include/Hal8821APwrSeq.h        |   200 +
- .../staging/rtl8723cs/include/HalPwrSeqCmd.h  |   130 +
- drivers/staging/rtl8723cs/include/HalVerDef.h |   209 +
- drivers/staging/rtl8723cs/include/autoconf.h  |   290 +
- .../staging/rtl8723cs/include/basic_types.h   |   357 +
- .../rtl8723cs/include/byteorder/big_endian.h  |    82 +
- .../rtl8723cs/include/byteorder/generic.h     |   207 +
- .../include/byteorder/little_endian.h         |    84 +
- .../rtl8723cs/include/byteorder/swab.h        |   136 +
- .../rtl8723cs/include/byteorder/swabb.h       |   151 +
- drivers/staging/rtl8723cs/include/circ_buf.h  |    23 +
- drivers/staging/rtl8723cs/include/cmd_osdep.h |    26 +
- .../rtl8723cs/include/cmn_info/rtw_sta_info.h |   279 +
- .../staging/rtl8723cs/include/custom_gpio.h   |    34 +
- drivers/staging/rtl8723cs/include/drv_conf.h  |   793 +
- drivers/staging/rtl8723cs/include/drv_types.h |  2036 ++
- .../staging/rtl8723cs/include/drv_types_ce.h  |    86 +
- .../rtl8723cs/include/drv_types_gspi.h        |    49 +
- .../rtl8723cs/include/drv_types_linux.h       |    19 +
- .../staging/rtl8723cs/include/drv_types_pci.h |    60 +
- .../rtl8723cs/include/drv_types_sdio.h        |    94 +
- .../staging/rtl8723cs/include/drv_types_xp.h  |    88 +
- drivers/staging/rtl8723cs/include/ethernet.h  |    36 +
- drivers/staging/rtl8723cs/include/gspi_hal.h  |    30 +
- drivers/staging/rtl8723cs/include/gspi_ops.h  |   180 +
- .../rtl8723cs/include/gspi_ops_linux.h        |    18 +
- .../staging/rtl8723cs/include/gspi_osintf.h   |    19 +
- drivers/staging/rtl8723cs/include/h2clbk.h    |    26 +
- .../staging/rtl8723cs/include/hal_btcoex.h    |   108 +
- .../rtl8723cs/include/hal_btcoex_wifionly.h   |    89 +
- drivers/staging/rtl8723cs/include/hal_com.h   |   736 +
- .../staging/rtl8723cs/include/hal_com_h2c.h   |   817 +
- .../staging/rtl8723cs/include/hal_com_led.h   |   437 +
- .../rtl8723cs/include/hal_com_phycfg.h        |   341 +
- .../staging/rtl8723cs/include/hal_com_reg.h   |  1890 ++
- drivers/staging/rtl8723cs/include/hal_data.h  |   881 +
- drivers/staging/rtl8723cs/include/hal_gspi.h  |    26 +
- .../staging/rtl8723cs/include/hal_ic_cfg.h    |   710 +
- drivers/staging/rtl8723cs/include/hal_intf.h  |   909 +
- drivers/staging/rtl8723cs/include/hal_pg.h    |   997 +
- drivers/staging/rtl8723cs/include/hal_phy.h   |   234 +
- .../staging/rtl8723cs/include/hal_phy_reg.h   |   270 +
- drivers/staging/rtl8723cs/include/hal_sdio.h  |    95 +
- .../staging/rtl8723cs/include/hal_sdio_coex.h |    41 +
- drivers/staging/rtl8723cs/include/ieee80211.h |  2000 ++
- .../staging/rtl8723cs/include/ieee80211_ext.h |   312 +
- drivers/staging/rtl8723cs/include/if_ether.h  |   106 +
- drivers/staging/rtl8723cs/include/ip.h        |   135 +
- .../rtl8723cs/include/linux/wireless.h        |    87 +
- .../staging/rtl8723cs/include/mlme_osdep.h    |    25 +
- drivers/staging/rtl8723cs/include/nic_spec.h  |    41 +
- .../staging/rtl8723cs/include/osdep_intf.h    |   143 +
- .../staging/rtl8723cs/include/osdep_service.h |   887 +
- .../rtl8723cs/include/osdep_service_bsd.h     |   757 +
- .../rtl8723cs/include/osdep_service_ce.h      |   200 +
- .../rtl8723cs/include/osdep_service_linux.h   |   564 +
- .../rtl8723cs/include/osdep_service_xp.h      |   210 +
- drivers/staging/rtl8723cs/include/pci_hal.h   |    60 +
- drivers/staging/rtl8723cs/include/pci_ops.h   |   116 +
- .../staging/rtl8723cs/include/pci_osintf.h    |    66 +
- .../staging/rtl8723cs/include/recv_osdep.h    |    70 +
- .../staging/rtl8723cs/include/rtl8188e_cmd.h  |   165 +
- .../staging/rtl8723cs/include/rtl8188e_dm.h   |    27 +
- .../staging/rtl8723cs/include/rtl8188e_hal.h  |   321 +
- .../staging/rtl8723cs/include/rtl8188e_led.h  |    37 +
- .../staging/rtl8723cs/include/rtl8188e_recv.h |   156 +
- .../staging/rtl8723cs/include/rtl8188e_rf.h   |    27 +
- .../staging/rtl8723cs/include/rtl8188e_spec.h |   159 +
- .../rtl8723cs/include/rtl8188e_sreset.h       |    24 +
- .../staging/rtl8723cs/include/rtl8188e_xmit.h |   302 +
- .../staging/rtl8723cs/include/rtl8188f_cmd.h  |   200 +
- .../staging/rtl8723cs/include/rtl8188f_dm.h   |    39 +
- .../staging/rtl8723cs/include/rtl8188f_hal.h  |   260 +
- .../staging/rtl8723cs/include/rtl8188f_led.h  |    45 +
- .../staging/rtl8723cs/include/rtl8188f_recv.h |    64 +
- .../staging/rtl8723cs/include/rtl8188f_rf.h   |    25 +
- .../staging/rtl8723cs/include/rtl8188f_spec.h |   275 +
- .../rtl8723cs/include/rtl8188f_sreset.h       |    24 +
- .../staging/rtl8723cs/include/rtl8188f_xmit.h |   340 +
- .../staging/rtl8723cs/include/rtl8192e_cmd.h  |   141 +
- .../staging/rtl8723cs/include/rtl8192e_dm.h   |    28 +
- .../staging/rtl8723cs/include/rtl8192e_hal.h  |   330 +
- .../staging/rtl8723cs/include/rtl8192e_led.h  |    36 +
- .../staging/rtl8723cs/include/rtl8192e_recv.h |   175 +
- .../staging/rtl8723cs/include/rtl8192e_rf.h   |    28 +
- .../staging/rtl8723cs/include/rtl8192e_spec.h |   313 +
- .../rtl8723cs/include/rtl8192e_sreset.h       |    24 +
- .../staging/rtl8723cs/include/rtl8192e_xmit.h |   457 +
- .../staging/rtl8723cs/include/rtl8192f_cmd.h  |   213 +
- .../staging/rtl8723cs/include/rtl8192f_dm.h   |    27 +
- .../staging/rtl8723cs/include/rtl8192f_hal.h  |   321 +
- .../staging/rtl8723cs/include/rtl8192f_led.h  |    59 +
- .../staging/rtl8723cs/include/rtl8192f_recv.h |   107 +
- .../staging/rtl8723cs/include/rtl8192f_rf.h   |    91 +
- .../staging/rtl8723cs/include/rtl8192f_spec.h |   541 +
- .../rtl8723cs/include/rtl8192f_sreset.h       |    24 +
- .../staging/rtl8723cs/include/rtl8192f_xmit.h |   538 +
- .../staging/rtl8723cs/include/rtl8703b_cmd.h  |   199 +
- .../staging/rtl8723cs/include/rtl8703b_dm.h   |    39 +
- .../staging/rtl8723cs/include/rtl8703b_hal.h  |   266 +
- .../staging/rtl8723cs/include/rtl8703b_led.h  |    44 +
- .../staging/rtl8723cs/include/rtl8703b_recv.h |    83 +
- .../staging/rtl8723cs/include/rtl8703b_rf.h   |    25 +
- .../staging/rtl8723cs/include/rtl8703b_spec.h |   464 +
- .../rtl8723cs/include/rtl8703b_sreset.h       |    24 +
- .../staging/rtl8723cs/include/rtl8703b_xmit.h |   342 +
- .../staging/rtl8723cs/include/rtl8710b_cmd.h  |   169 +
- .../staging/rtl8723cs/include/rtl8710b_dm.h   |    39 +
- .../staging/rtl8723cs/include/rtl8710b_hal.h  |   277 +
- .../staging/rtl8723cs/include/rtl8710b_led.h  |    44 +
- .../rtl8723cs/include/rtl8710b_lps_poff.h     |    56 +
- .../staging/rtl8723cs/include/rtl8710b_recv.h |    81 +
- .../staging/rtl8723cs/include/rtl8710b_rf.h   |    20 +
- .../staging/rtl8723cs/include/rtl8710b_spec.h |   481 +
- .../rtl8723cs/include/rtl8710b_sreset.h       |    24 +
- .../staging/rtl8723cs/include/rtl8710b_xmit.h |   523 +
- .../staging/rtl8723cs/include/rtl8723b_cmd.h  |   199 +
- .../staging/rtl8723cs/include/rtl8723b_dm.h   |    38 +
- .../staging/rtl8723cs/include/rtl8723b_hal.h  |   274 +
- .../staging/rtl8723cs/include/rtl8723b_led.h  |    44 +
- .../staging/rtl8723cs/include/rtl8723b_recv.h |    82 +
- .../staging/rtl8723cs/include/rtl8723b_rf.h   |    25 +
- .../staging/rtl8723cs/include/rtl8723b_spec.h |   280 +
- .../rtl8723cs/include/rtl8723b_sreset.h       |    24 +
- .../staging/rtl8723cs/include/rtl8723b_xmit.h |   342 +
- .../staging/rtl8723cs/include/rtl8723d_cmd.h  |   183 +
- .../staging/rtl8723cs/include/rtl8723d_dm.h   |    39 +
- .../staging/rtl8723cs/include/rtl8723d_hal.h  |   303 +
- .../staging/rtl8723cs/include/rtl8723d_led.h  |    44 +
- .../rtl8723cs/include/rtl8723d_lps_poff.h     |    56 +
- .../staging/rtl8723cs/include/rtl8723d_recv.h |   112 +
- .../staging/rtl8723cs/include/rtl8723d_rf.h   |    21 +
- .../staging/rtl8723cs/include/rtl8723d_spec.h |   447 +
- .../rtl8723cs/include/rtl8723d_sreset.h       |    24 +
- .../staging/rtl8723cs/include/rtl8723d_xmit.h |   530 +
- .../staging/rtl8723cs/include/rtl8723f_hal.h  |   262 +
- .../staging/rtl8723cs/include/rtl8723fs_hal.h |    31 +
- .../staging/rtl8723cs/include/rtl8723fu_hal.h |    61 +
- .../staging/rtl8723cs/include/rtl8812a_cmd.h  |   152 +
- .../staging/rtl8723cs/include/rtl8812a_dm.h   |    27 +
- .../staging/rtl8723cs/include/rtl8812a_hal.h  |   369 +
- .../staging/rtl8723cs/include/rtl8812a_led.h  |    41 +
- .../staging/rtl8723cs/include/rtl8812a_recv.h |   149 +
- .../staging/rtl8723cs/include/rtl8812a_rf.h   |    28 +
- .../staging/rtl8723cs/include/rtl8812a_spec.h |   263 +
- .../rtl8723cs/include/rtl8812a_sreset.h       |    24 +
- .../staging/rtl8723cs/include/rtl8812a_xmit.h |   371 +
- .../staging/rtl8723cs/include/rtl8814a_cmd.h  |   161 +
- .../staging/rtl8723cs/include/rtl8814a_dm.h   |    23 +
- .../staging/rtl8723cs/include/rtl8814a_hal.h  |   329 +
- .../staging/rtl8723cs/include/rtl8814a_led.h  |    36 +
- .../staging/rtl8723cs/include/rtl8814a_recv.h |   182 +
- .../staging/rtl8723cs/include/rtl8814a_rf.h   |    28 +
- .../staging/rtl8723cs/include/rtl8814a_spec.h |   653 +
- .../rtl8723cs/include/rtl8814a_sreset.h       |    24 +
- .../staging/rtl8723cs/include/rtl8814a_xmit.h |   315 +
- .../staging/rtl8723cs/include/rtl8814b_hal.h  |   239 +
- .../staging/rtl8723cs/include/rtl8814be_hal.h |    30 +
- .../staging/rtl8723cs/include/rtl8814bu_hal.h |    61 +
- .../staging/rtl8723cs/include/rtl8821a_spec.h |    90 +
- .../staging/rtl8723cs/include/rtl8821a_xmit.h |   176 +
- .../staging/rtl8723cs/include/rtl8821c_dm.h   |    23 +
- .../staging/rtl8723cs/include/rtl8821c_hal.h  |    84 +
- .../staging/rtl8723cs/include/rtl8821c_spec.h |   202 +
- .../staging/rtl8723cs/include/rtl8821ce_hal.h |    23 +
- .../staging/rtl8723cs/include/rtl8821cs_hal.h |    23 +
- .../staging/rtl8723cs/include/rtl8821cu_hal.h |    24 +
- .../staging/rtl8723cs/include/rtl8822b_hal.h  |   234 +
- .../staging/rtl8723cs/include/rtl8822be_hal.h |    27 +
- .../staging/rtl8723cs/include/rtl8822bs_hal.h |    31 +
- .../staging/rtl8723cs/include/rtl8822bu_hal.h |    61 +
- .../staging/rtl8723cs/include/rtl8822c_hal.h  |   246 +
- .../staging/rtl8723cs/include/rtl8822ce_hal.h |    27 +
- .../staging/rtl8723cs/include/rtl8822cs_hal.h |    31 +
- .../staging/rtl8723cs/include/rtl8822cu_hal.h |    61 +
- .../staging/rtl8723cs/include/rtw_android.h   |   117 +
- drivers/staging/rtl8723cs/include/rtw_ap.h    |   143 +
- .../rtl8723cs/include/rtw_beamforming.h       |   297 +
- .../staging/rtl8723cs/include/rtw_br_ext.h    |    69 +
- drivers/staging/rtl8723cs/include/rtw_bt_mp.h |   288 +
- .../staging/rtl8723cs/include/rtw_btcoex.h    |   468 +
- .../rtl8723cs/include/rtw_btcoex_wifionly.h   |    24 +
- .../staging/rtl8723cs/include/rtw_byteorder.h |    33 +
- drivers/staging/rtl8723cs/include/rtw_cmd.h   |   790 +
- drivers/staging/rtl8723cs/include/rtw_debug.h |   727 +
- .../staging/rtl8723cs/include/rtw_eeprom.h    |   116 +
- drivers/staging/rtl8723cs/include/rtw_efuse.h |   285 +
- drivers/staging/rtl8723cs/include/rtw_event.h |    95 +
- drivers/staging/rtl8723cs/include/rtw_ft.h    |   183 +
- drivers/staging/rtl8723cs/include/rtw_ht.h    |   217 +
- drivers/staging/rtl8723cs/include/rtw_io.h    |   526 +
- drivers/staging/rtl8723cs/include/rtw_ioctl.h |    47 +
- .../rtl8723cs/include/rtw_ioctl_query.h       |    19 +
- .../staging/rtl8723cs/include/rtw_ioctl_set.h |    40 +
- drivers/staging/rtl8723cs/include/rtw_iol.h   |   131 +
- drivers/staging/rtl8723cs/include/rtw_mbo.h   |   114 +
- drivers/staging/rtl8723cs/include/rtw_mcc.h   |   315 +
- drivers/staging/rtl8723cs/include/rtw_mem.h   |    29 +
- drivers/staging/rtl8723cs/include/rtw_mi.h    |   305 +
- drivers/staging/rtl8723cs/include/rtw_mlme.h  |  1238 ++
- .../staging/rtl8723cs/include/rtw_mlme_ext.h  |  1239 ++
- drivers/staging/rtl8723cs/include/rtw_mp.h    |   943 +
- .../rtl8723cs/include/rtw_mp_phy_regdef.h     |  1094 +
- drivers/staging/rtl8723cs/include/rtw_odm.h   |   103 +
- drivers/staging/rtl8723cs/include/rtw_p2p.h   |   167 +
- .../staging/rtl8723cs/include/rtw_pwrctrl.h   |   772 +
- drivers/staging/rtl8723cs/include/rtw_qos.h   |    66 +
- drivers/staging/rtl8723cs/include/rtw_recv.h  |   868 +
- drivers/staging/rtl8723cs/include/rtw_rf.h    |   326 +
- drivers/staging/rtl8723cs/include/rtw_rm.h    |   105 +
- .../staging/rtl8723cs/include/rtw_rm_fsm.h    |   397 +
- .../staging/rtl8723cs/include/rtw_rm_util.h   |    47 +
- drivers/staging/rtl8723cs/include/rtw_roch.h  |    61 +
- drivers/staging/rtl8723cs/include/rtw_rson.h  |    61 +
- drivers/staging/rtl8723cs/include/rtw_sdio.h  |    26 +
- .../staging/rtl8723cs/include/rtw_security.h  |   421 +
- .../staging/rtl8723cs/include/rtw_sreset.h    |    66 +
- .../staging/rtl8723cs/include/rtw_swcrypto.h  |    49 +
- drivers/staging/rtl8723cs/include/rtw_tdls.h  |   185 +
- .../staging/rtl8723cs/include/rtw_version.h   |     3 +
- drivers/staging/rtl8723cs/include/rtw_vht.h   |   184 +
- drivers/staging/rtl8723cs/include/rtw_wapi.h  |   230 +
- drivers/staging/rtl8723cs/include/rtw_wnm.h   |   209 +
- drivers/staging/rtl8723cs/include/rtw_xmit.h  |  1071 +
- drivers/staging/rtl8723cs/include/sdio_hal.h  |    57 +
- drivers/staging/rtl8723cs/include/sdio_ops.h  |   207 +
- .../staging/rtl8723cs/include/sdio_ops_ce.h   |    49 +
- .../rtl8723cs/include/sdio_ops_linux.h        |    58 +
- .../staging/rtl8723cs/include/sdio_ops_xp.h   |    49 +
- .../staging/rtl8723cs/include/sdio_osintf.h   |    19 +
- drivers/staging/rtl8723cs/include/sta_info.h  |   782 +
- drivers/staging/rtl8723cs/include/usb_hal.h   |    71 +
- drivers/staging/rtl8723cs/include/usb_ops.h   |   153 +
- .../staging/rtl8723cs/include/usb_ops_linux.h |    98 +
- .../staging/rtl8723cs/include/usb_osintf.h    |    26 +
- .../rtl8723cs/include/usb_vendor_req.h        |    56 +
- drivers/staging/rtl8723cs/include/wifi.h      |  1369 ++
- .../staging/rtl8723cs/include/wlan_bssdef.h   |   327 +
- .../staging/rtl8723cs/include/xmit_osdep.h    |    96 +
- .../os_dep/linux/custom_gpio_linux.c          |   340 +
- .../rtl8723cs/os_dep/linux/ioctl_cfg80211.c   | 10852 ++++++++++
- .../rtl8723cs/os_dep/linux/ioctl_cfg80211.h   |   454 +
- .../rtl8723cs/os_dep/linux/ioctl_linux.c      | 13049 ++++++++++++
- .../staging/rtl8723cs/os_dep/linux/ioctl_mp.c |  3531 ++++
- .../rtl8723cs/os_dep/linux/mlme_linux.c       |   444 +
- .../staging/rtl8723cs/os_dep/linux/nlrtw.c    |   583 +
- .../staging/rtl8723cs/os_dep/linux/nlrtw.h    |    48 +
- .../staging/rtl8723cs/os_dep/linux/os_intfs.c |  5744 ++++++
- .../rtl8723cs/os_dep/linux/recv_linux.c       |   734 +
- .../rtl8723cs/os_dep/linux/rhashtable.c       |   844 +
- .../rtl8723cs/os_dep/linux/rhashtable.h       |   827 +
- .../rtl8723cs/os_dep/linux/rtw_android.c      |  1346 ++
- .../rtl8723cs/os_dep/linux/rtw_cfgvendor.c    |  2170 ++
- .../rtl8723cs/os_dep/linux/rtw_cfgvendor.h    |   636 +
- .../staging/rtl8723cs/os_dep/linux/rtw_proc.c |  6233 ++++++
- .../staging/rtl8723cs/os_dep/linux/rtw_proc.h |    72 +
- .../rtl8723cs/os_dep/linux/rtw_rhashtable.c   |    77 +
- .../rtl8723cs/os_dep/linux/rtw_rhashtable.h   |    67 +
- .../rtl8723cs/os_dep/linux/sdio_intf.c        |  1424 ++
- .../rtl8723cs/os_dep/linux/sdio_ops_linux.c   |  1347 ++
- .../rtl8723cs/os_dep/linux/wifi_regd.c        |   410 +
- .../rtl8723cs/os_dep/linux/wifi_regd.h        |    27 +
- .../rtl8723cs/os_dep/linux/xmit_linux.c       |   538 +
- .../staging/rtl8723cs/os_dep/osdep_service.c  |  3430 ++++
- .../platform/custom_country_chplan.h          |    22 +
- .../platform/platform_ARM_SUN50IW1P1_sdio.c   |    86 +
- .../platform/platform_ARM_SUNnI_sdio.c        |   130 +
- .../platform/platform_ARM_SUNxI_sdio.c        |    90 +
- .../platform/platform_ARM_SUNxI_usb.c         |   136 +
- .../platform/platform_ARM_WMT_sdio.c          |    46 +
- .../rtl8723cs/platform/platform_RTK_DMP_usb.c |    30 +
- .../platform/platform_aml_s905_sdio.c         |    54 +
- .../platform/platform_aml_s905_sdio.h         |    28 +
- .../platform/platform_arm_act_sdio.c          |    53 +
- .../platform/platform_hisilicon_hi3798_sdio.c |   110 +
- .../platform/platform_hisilicon_hi3798_sdio.h |    28 +
- .../staging/rtl8723cs/platform/platform_ops.c |    34 +
- .../staging/rtl8723cs/platform/platform_ops.h |    26 +
- .../rtl8723cs/platform/platform_sprd_sdio.c   |    84 +
- .../platform/platform_zte_zx296716_sdio.c     |    53 +
- .../platform/platform_zte_zx296716_sdio.h     |    25 +
- drivers/staging/rtl8723cs/runwpa              |    20 +
- drivers/staging/rtl8723cs/wlan0dhcp           |    16 +
- 586 files changed, 442195 insertions(+)
- create mode 100644 drivers/staging/rtl8723cs/Kconfig
- create mode 100644 drivers/staging/rtl8723cs/Makefile
- create mode 100644 drivers/staging/rtl8723cs/clean
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/aes-ccm.c
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/aes-ctr.c
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/aes-gcm.c
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/aes-internal-enc.c
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/aes-internal.c
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/aes-omac1.c
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/aes-siv.c
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/aes.h
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/aes_i.h
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/aes_siv.h
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/aes_wrap.h
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/ccmp.c
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/gcmp.c
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/rtw_crypto_wrap.c
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/rtw_crypto_wrap.h
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/sha256-internal.c
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/sha256-prf.c
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/sha256.c
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/sha256.h
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/sha256_i.h
- create mode 100644 drivers/staging/rtl8723cs/core/crypto/wlancrypto_wrap.h
- create mode 100644 drivers/staging/rtl8723cs/core/efuse/rtw_efuse.c
- create mode 100644 drivers/staging/rtl8723cs/core/mesh/rtw_mesh.c
- create mode 100644 drivers/staging/rtl8723cs/core/mesh/rtw_mesh.h
- create mode 100644 drivers/staging/rtl8723cs/core/mesh/rtw_mesh_hwmp.c
- create mode 100644 drivers/staging/rtl8723cs/core/mesh/rtw_mesh_hwmp.h
- create mode 100644 drivers/staging/rtl8723cs/core/mesh/rtw_mesh_pathtbl.c
- create mode 100644 drivers/staging/rtl8723cs/core/mesh/rtw_mesh_pathtbl.h
- create mode 100644 drivers/staging/rtl8723cs/core/monitor/rtw_radiotap.c
- create mode 100644 drivers/staging/rtl8723cs/core/monitor/rtw_radiotap.h
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_ap.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_beamforming.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_br_ext.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_bt_mp.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_btcoex.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_btcoex_wifionly.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_chplan.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_chplan.h
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_cmd.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_debug.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_eeprom.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_ft.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_ieee80211.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_io.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_ioctl_query.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_ioctl_set.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_iol.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_mbo.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_mem.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_mi.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_mlme.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_mlme_ext.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_mp.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_odm.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_p2p.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_pwrctrl.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_recv.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_rf.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_rm.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_rm_fsm.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_rm_util.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_roch.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_rson.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_sdio.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_security.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_sreset.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_sta_mgt.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_swcrypto.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_tdls.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_vht.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_wapi.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_wapi_sms4.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_wlan_util.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_wnm.c
- create mode 100644 drivers/staging/rtl8723cs/core/rtw_xmit.c
- create mode 100644 drivers/staging/rtl8723cs/core/wds/rtw_wds.c
- create mode 100644 drivers/staging/rtl8723cs/core/wds/rtw_wds.h
- create mode 100644 drivers/staging/rtl8723cs/hal/HalPwrSeqCmd.c
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- create mode 100644 drivers/staging/rtl8723cs/hal/btc/halbtc8703b1ant.h
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- create mode 100644 drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_PCIE.h
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- create mode 100644 drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_SDIO.h
- create mode 100644 drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_USB.c
- create mode 100644 drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_USB.h
- create mode 100644 drivers/staging/rtl8723cs/hal/hal_btcoex.c
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- create mode 100644 drivers/staging/rtl8723cs/hal/hal_com_c2h.h
- create mode 100644 drivers/staging/rtl8723cs/hal/hal_com_phycfg.c
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- create mode 100644 drivers/staging/rtl8723cs/hal/hal_dm.h
- create mode 100644 drivers/staging/rtl8723cs/hal/hal_dm_acs.c
- create mode 100644 drivers/staging/rtl8723cs/hal/hal_dm_acs.h
- create mode 100644 drivers/staging/rtl8723cs/hal/hal_halmac.c
- create mode 100644 drivers/staging/rtl8723cs/hal/hal_halmac.h
- create mode 100644 drivers/staging/rtl8723cs/hal/hal_hci/hal_sdio.c
- create mode 100644 drivers/staging/rtl8723cs/hal/hal_hci/hal_sdio_coex.c
- create mode 100644 drivers/staging/rtl8723cs/hal/hal_intf.c
- create mode 100644 drivers/staging/rtl8723cs/hal/hal_mcc.c
- create mode 100644 drivers/staging/rtl8723cs/hal/hal_mp.c
- create mode 100644 drivers/staging/rtl8723cs/hal/hal_phy.c
- create mode 100644 drivers/staging/rtl8723cs/hal/led/hal_led.c
- create mode 100644 drivers/staging/rtl8723cs/hal/led/hal_sdio_led.c
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/ap_makefile.mk
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halhwimg.h
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- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_ap.h
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- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_ce.h
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- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_debug.h
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_dpk.h
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_features.h
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_iqk.h
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_kfree.c
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_kfree.h
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking.c
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking.h
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- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_ap.h
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- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_ce.h
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_iot.c
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_iot.h
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_win.c
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_win.h
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_psd.c
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_psd.h
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_txgapcal.c
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_txgapcal.h
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/rtl8703b/halrf_8703b.c
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/halrf/rtl8703b/halrf_8703b.h
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/mp_precomp.h
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- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/phydm.h
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/phydm.mk
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- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/phydm_adaptivity.h
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/phydm_adc_sampling.c
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/phydm_adc_sampling.h
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- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/phydm_dig.c
- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/phydm_dig.h
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- create mode 100644 drivers/staging/rtl8723cs/hal/phydm/phydm_direct_bf.h
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- create mode 100644 drivers/staging/rtl8723cs/include/rtl8821c_spec.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtl8821ce_hal.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtl8821cs_hal.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtl8821cu_hal.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtl8822b_hal.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtl8822be_hal.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtl8822bs_hal.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtl8822bu_hal.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtl8822c_hal.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtl8822ce_hal.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtl8822cs_hal.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtl8822cu_hal.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_android.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_ap.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_beamforming.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_br_ext.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_bt_mp.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_btcoex.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_btcoex_wifionly.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_byteorder.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_cmd.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_debug.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_eeprom.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_efuse.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_event.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_ft.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_ht.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_io.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_ioctl.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_ioctl_query.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_ioctl_set.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_iol.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_mbo.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_mcc.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_mem.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_mi.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_mlme.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_mlme_ext.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_mp.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_mp_phy_regdef.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_odm.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_p2p.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_pwrctrl.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_qos.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_recv.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_rf.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_rm.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_rm_fsm.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_rm_util.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_roch.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_rson.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_sdio.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_security.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_sreset.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_swcrypto.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_tdls.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_version.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_vht.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_wapi.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_wnm.h
- create mode 100644 drivers/staging/rtl8723cs/include/rtw_xmit.h
- create mode 100644 drivers/staging/rtl8723cs/include/sdio_hal.h
- create mode 100644 drivers/staging/rtl8723cs/include/sdio_ops.h
- create mode 100644 drivers/staging/rtl8723cs/include/sdio_ops_ce.h
- create mode 100644 drivers/staging/rtl8723cs/include/sdio_ops_linux.h
- create mode 100644 drivers/staging/rtl8723cs/include/sdio_ops_xp.h
- create mode 100644 drivers/staging/rtl8723cs/include/sdio_osintf.h
- create mode 100644 drivers/staging/rtl8723cs/include/sta_info.h
- create mode 100644 drivers/staging/rtl8723cs/include/usb_hal.h
- create mode 100644 drivers/staging/rtl8723cs/include/usb_ops.h
- create mode 100644 drivers/staging/rtl8723cs/include/usb_ops_linux.h
- create mode 100644 drivers/staging/rtl8723cs/include/usb_osintf.h
- create mode 100644 drivers/staging/rtl8723cs/include/usb_vendor_req.h
- create mode 100644 drivers/staging/rtl8723cs/include/wifi.h
- create mode 100644 drivers/staging/rtl8723cs/include/wlan_bssdef.h
- create mode 100644 drivers/staging/rtl8723cs/include/xmit_osdep.h
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/custom_gpio_linux.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/ioctl_cfg80211.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/ioctl_cfg80211.h
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/ioctl_linux.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/ioctl_mp.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/mlme_linux.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/nlrtw.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/nlrtw.h
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/os_intfs.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/recv_linux.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/rhashtable.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/rhashtable.h
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/rtw_android.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/rtw_cfgvendor.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/rtw_cfgvendor.h
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/rtw_proc.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/rtw_proc.h
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/rtw_rhashtable.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/rtw_rhashtable.h
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/sdio_intf.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/sdio_ops_linux.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/wifi_regd.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/wifi_regd.h
- create mode 100644 drivers/staging/rtl8723cs/os_dep/linux/xmit_linux.c
- create mode 100644 drivers/staging/rtl8723cs/os_dep/osdep_service.c
- create mode 100644 drivers/staging/rtl8723cs/platform/custom_country_chplan.h
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_ARM_SUN50IW1P1_sdio.c
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_ARM_SUNnI_sdio.c
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_ARM_SUNxI_sdio.c
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_ARM_SUNxI_usb.c
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_ARM_WMT_sdio.c
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_RTK_DMP_usb.c
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_aml_s905_sdio.c
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_aml_s905_sdio.h
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_arm_act_sdio.c
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_hisilicon_hi3798_sdio.c
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_hisilicon_hi3798_sdio.h
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_ops.c
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_ops.h
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_sprd_sdio.c
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_zte_zx296716_sdio.c
- create mode 100644 drivers/staging/rtl8723cs/platform/platform_zte_zx296716_sdio.h
- create mode 100644 drivers/staging/rtl8723cs/runwpa
- create mode 100644 drivers/staging/rtl8723cs/wlan0dhcp
-
-diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
-index e03627ad4460..5f9ec2b1a335 100644
---- a/drivers/staging/Kconfig
-+++ b/drivers/staging/Kconfig
-@@ -102,4 +102,6 @@ source "drivers/staging/qlge/Kconfig"
- 
- source "drivers/staging/wfx/Kconfig"
- 
-+source "drivers/staging/rtl8723cs/Kconfig"
-+
- endif # STAGING
-diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
-index c7f8d8d8dd11..81a362f79845 100644
---- a/drivers/staging/Makefile
-+++ b/drivers/staging/Makefile
-@@ -41,3 +41,4 @@ obj-$(CONFIG_XIL_AXIS_FIFO)	+= axis-fifo/
- obj-$(CONFIG_FIELDBUS_DEV)     += fieldbus/
- obj-$(CONFIG_QLGE)		+= qlge/
- obj-$(CONFIG_WFX)		+= wfx/
-+obj-$(CONFIG_RTL8723CS)		+= rtl8723cs/
-diff --git a/drivers/staging/rtl8723cs/Kconfig b/drivers/staging/rtl8723cs/Kconfig
-new file mode 100644
-index 000000000000..9b2e6ad9dbbc
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/Kconfig
-@@ -0,0 +1,8 @@
-+# SPDX-License-Identifier: GPL-2.0
-+config RTL8723CS
-+	tristate "Realtek RTL8723CS SDIO or SPI WiFi driver (2020)"
-+	depends on WLAN && MMC && CFG80211
-+	select WIRELESS_EXT
-+	select WEXT_PRIV
-+	help
-+	  Help message of RTL8723CS
-diff --git a/drivers/staging/rtl8723cs/Makefile b/drivers/staging/rtl8723cs/Makefile
-new file mode 100644
-index 000000000000..a709256357f9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/Makefile
-@@ -0,0 +1,2522 @@
-+# SPDX-License-Identifier: GPL-2.0
-+EXTRA_CFLAGS += $(USER_EXTRA_CFLAGS)
-+EXTRA_CFLAGS += -O2
-+#EXTRA_CFLAGS += -O3
-+#EXTRA_CFLAGS += -Wall
-+#EXTRA_CFLAGS += -Wextra
-+#EXTRA_CFLAGS += -Werror
-+#EXTRA_CFLAGS += -pedantic
-+#EXTRA_CFLAGS += -Wshadow -Wpointer-arith -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes
-+
-+EXTRA_CFLAGS += -Wno-unused-variable
-+#EXTRA_CFLAGS += -Wno-unused-value
-+#EXTRA_CFLAGS += -Wno-unused-label
-+#EXTRA_CFLAGS += -Wno-unused-parameter
-+#EXTRA_CFLAGS += -Wno-unused-function
-+#EXTRA_CFLAGS += -Wno-unused
-+#EXTRA_CFLAGS += -Wno-uninitialized
-+
-+GCC_VER_49 := $(shell echo `$(CC) -dumpversion | cut -f1-2 -d.` \>= 4.9 | bc )
-+ifeq ($(GCC_VER_49),1)
-+EXTRA_CFLAGS += -Wno-date-time	# Fix compile error && warning on gcc 4.9 and later
-+endif
-+
-+EXTRA_CFLAGS += -I$(srctree)/$(src)/include
-+
-+EXTRA_LDFLAGS += --strip-debug
-+
-+CONFIG_AUTOCFG_CP = n
-+
-+########################## WIFI IC ############################
-+CONFIG_MULTIDRV = n
-+CONFIG_RTL8188E = n
-+CONFIG_RTL8812A = n
-+CONFIG_RTL8821A = n
-+CONFIG_RTL8192E = n
-+CONFIG_RTL8723B = n
-+CONFIG_RTL8814A = n
-+CONFIG_RTL8723C = y
-+CONFIG_RTL8188F = n
-+CONFIG_RTL8188GTV = n
-+CONFIG_RTL8822B = n
-+CONFIG_RTL8723D = n
-+CONFIG_RTL8821C = n
-+CONFIG_RTL8710B = n
-+CONFIG_RTL8192F = n
-+CONFIG_RTL8822C = n
-+CONFIG_RTL8814B = n
-+CONFIG_RTL8723F = n
-+######################### Interface ###########################
-+CONFIG_USB_HCI = n
-+CONFIG_PCI_HCI = n
-+CONFIG_SDIO_HCI = y
-+CONFIG_GSPI_HCI = n
-+########################## Features ###########################
-+CONFIG_AP_MODE = y
-+CONFIG_P2P = y
-+CONFIG_MP_INCLUDED = n
-+CONFIG_POWER_SAVING = y
-+CONFIG_IPS_MODE = 0
-+CONFIG_LPS_MODE = 1
-+CONFIG_USB_AUTOSUSPEND = n
-+CONFIG_HW_PWRP_DETECTION = n
-+CONFIG_BT_COEXIST = y
-+CONFIG_WAPI_SUPPORT = n
-+CONFIG_EFUSE_CONFIG_FILE = n
-+CONFIG_EXT_CLK = n
-+CONFIG_TRAFFIC_PROTECT = n
-+CONFIG_LOAD_PHY_PARA_FROM_FILE = n
-+CONFIG_TXPWR_BY_RATE = y
-+CONFIG_TXPWR_BY_RATE_EN = y
-+CONFIG_TXPWR_LIMIT = y
-+CONFIG_TXPWR_LIMIT_EN = n
-+CONFIG_RTW_CHPLAN = 0xFF
-+CONFIG_RTW_ADAPTIVITY_EN = disable
-+CONFIG_RTW_ADAPTIVITY_MODE = normal
-+CONFIG_SIGNAL_SCALE_MAPPING = n
-+CONFIG_80211W = y
-+CONFIG_REDUCE_TX_CPU_LOADING = n
-+CONFIG_BR_EXT = y
-+CONFIG_TDLS = y
-+CONFIG_WIFI_MONITOR = y
-+CONFIG_MCC_MODE = n
-+CONFIG_APPEND_VENDOR_IE_ENABLE = n
-+CONFIG_RTW_NAPI = n
-+CONFIG_RTW_GRO = n
-+CONFIG_RTW_NETIF_SG = y
-+CONFIG_RTW_IPCAM_APPLICATION = n
-+CONFIG_RTW_REPEATER_SON = n
-+CONFIG_ICMP_VOQ = n
-+CONFIG_IP_R_MONITOR = n #arp VOQ and high rate
-+# user priority mapping rule : tos, dscp
-+CONFIG_RTW_UP_MAPPING_RULE = tos
-+CONFIG_RTW_MBO = n
-+########################## Android ###########################
-+# CONFIG_RTW_ANDROID - 0: no Android, 4/5/6/7/8/9/10 : Android version
-+CONFIG_RTW_ANDROID = 0
-+
-+ifeq ($(shell test $(CONFIG_RTW_ANDROID) -gt 0; echo $$?), 0)
-+EXTRA_CFLAGS += -DCONFIG_RTW_ANDROID=$(CONFIG_RTW_ANDROID)
-+endif
-+########################## Debug ###########################
-+CONFIG_RTW_DEBUG = n
-+# default log level is _DRV_INFO_ = 4,
-+# please refer to "How_to_set_driver_debug_log_level.doc" to set the available level.
-+CONFIG_RTW_LOG_LEVEL = 6
-+
-+# enable /proc/net/rtlxxxx/ debug interfaces
-+CONFIG_PROC_DEBUG = y
-+
-+######################## Wake On Lan ##########################
-+CONFIG_WOWLAN = y
-+#bit3: ARP enable, bit2: deauth, bit1: unicast, bit0: magic pkt.
-+CONFIG_WAKEUP_TYPE = 0xf
-+CONFIG_WOW_LPS_MODE = default
-+#bit0: disBBRF off, #bit1: Wireless remote controller (WRC)
-+CONFIG_SUSPEND_TYPE = 0
-+CONFIG_WOW_STA_MIX = n
-+CONFIG_GPIO_WAKEUP = y
-+# Please contact with RTK support team first. After getting the agreement from RTK support team, 
-+# you are just able to modify the CONFIG_WAKEUP_GPIO_IDX with customized requirement.
-+CONFIG_WAKEUP_GPIO_IDX = default
-+CONFIG_HIGH_ACTIVE_DEV2HST = n
-+######### only for USB #########
-+CONFIG_ONE_PIN_GPIO = n
-+CONFIG_HIGH_ACTIVE_HST2DEV = n
-+CONFIG_PNO_SUPPORT = n
-+CONFIG_PNO_SET_DEBUG = n
-+CONFIG_AP_WOWLAN = n
-+######### Notify SDIO Host Keep Power During Syspend ##########
-+CONFIG_RTW_SDIO_PM_KEEP_POWER = y
-+###################### MP HW TX MODE FOR VHT #######################
-+CONFIG_MP_VHT_HW_TX_MODE = n
-+###################### ROAMING #####################################
-+CONFIG_LAYER2_ROAMING = y
-+#bit0: ROAM_ON_EXPIRED, #bit1: ROAM_ON_RESUME, #bit2: ROAM_ACTIVE
-+CONFIG_ROAMING_FLAG = 0x3
-+###################### Platform Related #######################
-+CONFIG_PLATFORM_I386_PC = y
-+CONFIG_PLATFORM_ANDROID_X86 = n
-+CONFIG_PLATFORM_ANDROID_INTEL_X86 = n
-+CONFIG_PLATFORM_JB_X86 = n
-+CONFIG_PLATFORM_ARM_S3C2K4 = n
-+CONFIG_PLATFORM_ARM_PXA2XX = n
-+CONFIG_PLATFORM_ARM_S3C6K4 = n
-+CONFIG_PLATFORM_MIPS_RMI = n
-+CONFIG_PLATFORM_RTD2880B = n
-+CONFIG_PLATFORM_MIPS_AR9132 = n
-+CONFIG_PLATFORM_RTK_DMP = n
-+CONFIG_PLATFORM_MIPS_PLM = n
-+CONFIG_PLATFORM_MSTAR389 = n
-+CONFIG_PLATFORM_MT53XX = n
-+CONFIG_PLATFORM_ARM_MX51_241H = n
-+CONFIG_PLATFORM_FS_MX61 = n
-+CONFIG_PLATFORM_ACTIONS_ATJ227X = n
-+CONFIG_PLATFORM_TEGRA3_CARDHU = n
-+CONFIG_PLATFORM_TEGRA4_DALMORE = n
-+CONFIG_PLATFORM_ARM_TCC8900 = n
-+CONFIG_PLATFORM_ARM_TCC8920 = n
-+CONFIG_PLATFORM_ARM_TCC8920_JB42 = n
-+CONFIG_PLATFORM_ARM_TCC8930_JB42 = n
-+CONFIG_PLATFORM_ARM_RK2818 = n
-+CONFIG_PLATFORM_ARM_RK3066 = n
-+CONFIG_PLATFORM_ARM_RK3188 = n
-+CONFIG_PLATFORM_ARM_URBETTER = n
-+CONFIG_PLATFORM_ARM_TI_PANDA = n
-+CONFIG_PLATFORM_MIPS_JZ4760 = n
-+CONFIG_PLATFORM_DMP_PHILIPS = n
-+CONFIG_PLATFORM_MSTAR_TITANIA12 = n
-+CONFIG_PLATFORM_MSTAR = n
-+CONFIG_PLATFORM_SZEBOOK = n
-+CONFIG_PLATFORM_ARM_SUNxI = n
-+CONFIG_PLATFORM_ARM_SUN6I = n
-+CONFIG_PLATFORM_ARM_SUN7I = n
-+CONFIG_PLATFORM_ARM_SUN8I_W3P1 = n
-+CONFIG_PLATFORM_ARM_SUN8I_W5P1 = n
-+CONFIG_PLATFORM_ACTIONS_ATM702X = n
-+CONFIG_PLATFORM_ACTIONS_ATV5201 = n
-+CONFIG_PLATFORM_ACTIONS_ATM705X = n
-+CONFIG_PLATFORM_ARM_SUN50IW1P1 = n
-+CONFIG_PLATFORM_ARM_RTD299X = n
-+CONFIG_PLATFORM_ARM_LGE = n
-+CONFIG_PLATFORM_ARM_SPREADTRUM_6820 = n
-+CONFIG_PLATFORM_ARM_SPREADTRUM_8810 = n
-+CONFIG_PLATFORM_ARM_WMT = n
-+CONFIG_PLATFORM_TI_DM365 = n
-+CONFIG_PLATFORM_MOZART = n
-+CONFIG_PLATFORM_RTK119X = n
-+CONFIG_PLATFORM_RTK119X_AM = n
-+CONFIG_PLATFORM_RTK129X = n
-+CONFIG_PLATFORM_RTK1319 = n
-+CONFIG_PLATFORM_RTK390X = n
-+CONFIG_PLATFORM_NOVATEK_NT72668 = n
-+CONFIG_PLATFORM_HISILICON = n
-+CONFIG_PLATFORM_HISILICON_HI3798 = n
-+CONFIG_PLATFORM_NV_TK1 = n
-+CONFIG_PLATFORM_NV_TK1_UBUNTU = n
-+CONFIG_PLATFORM_RTL8197D = n
-+CONFIG_PLATFORM_AML_S905 = n
-+CONFIG_PLATFORM_ZTE_ZX296716 = n
-+########### CUSTOMER ################################
-+CONFIG_CUSTOMER_HUAWEI_GENERAL = n
-+
-+CONFIG_DRVEXT_MODULE = n
-+
-+export TopDIR ?= $(srctree)/$(src)
-+
-+########### COMMON  #################################
-+ifeq ($(CONFIG_GSPI_HCI), y)
-+HCI_NAME = gspi
-+endif
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+HCI_NAME = sdio
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+HCI_NAME = usb
-+endif
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+HCI_NAME = pci
-+endif
-+
-+
-+_OS_INTFS_FILES :=	os_dep/osdep_service.o \
-+			os_dep/linux/os_intfs.o \
-+			os_dep/linux/$(HCI_NAME)_intf.o \
-+			os_dep/linux/$(HCI_NAME)_ops_linux.o \
-+			os_dep/linux/ioctl_linux.o \
-+			os_dep/linux/xmit_linux.o \
-+			os_dep/linux/mlme_linux.o \
-+			os_dep/linux/recv_linux.o \
-+			os_dep/linux/ioctl_cfg80211.o \
-+			os_dep/linux/rtw_cfgvendor.o \
-+			os_dep/linux/wifi_regd.o \
-+			os_dep/linux/rtw_android.o \
-+			os_dep/linux/rtw_proc.o \
-+			os_dep/linux/nlrtw.o \
-+			os_dep/linux/rtw_rhashtable.o
-+
-+ifeq ($(CONFIG_MP_INCLUDED), y)
-+_OS_INTFS_FILES += os_dep/linux/ioctl_mp.o
-+endif
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_OS_INTFS_FILES += os_dep/linux/custom_gpio_linux.o
-+_OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_ops_linux.o
-+endif
-+
-+ifeq ($(CONFIG_GSPI_HCI), y)
-+_OS_INTFS_FILES += os_dep/linux/custom_gpio_linux.o
-+_OS_INTFS_FILES += os_dep/linux/$(HCI_NAME)_ops_linux.o
-+endif
-+
-+
-+_HAL_INTFS_FILES :=	hal/hal_intf.o \
-+			hal/hal_com.o \
-+			hal/hal_com_phycfg.o \
-+			hal/hal_phy.o \
-+			hal/hal_dm.o \
-+			hal/hal_dm_acs.o \
-+			hal/hal_btcoex_wifionly.o \
-+			hal/hal_btcoex.o \
-+			hal/hal_mp.o \
-+			hal/hal_mcc.o \
-+			hal/hal_hci/hal_$(HCI_NAME).o \
-+			hal/led/hal_led.o \
-+			hal/led/hal_$(HCI_NAME)_led.o
-+
-+
-+EXTRA_CFLAGS += -I$(srctree)/$(src)/platform
-+_PLATFORM_FILES := platform/platform_ops.o
-+
-+EXTRA_CFLAGS += -I$(srctree)/$(src)/hal/btc
-+
-+########### HAL_RTL8188E #################################
-+ifeq ($(CONFIG_RTL8188E), y)
-+
-+RTL871X = rtl8188e
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8189es
-+endif
-+
-+ifeq ($(CONFIG_GSPI_HCI), y)
-+MODULE_NAME = 8189es
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8188eu
-+endif
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8188ee
-+endif
-+EXTRA_CFLAGS += -DCONFIG_RTL8188E
-+
-+_HAL_INTFS_FILES +=	hal/HalPwrSeqCmd.o \
-+					hal/$(RTL871X)/Hal8188EPwrSeq.o\
-+ 					hal/$(RTL871X)/$(RTL871X)_xmit.o\
-+					hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+			hal/$(RTL871X)/$(RTL871X)_dm.o \
-+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+			hal/$(RTL871X)/hal8188e_s_fw.o \
-+			hal/$(RTL871X)/hal8188e_t_fw.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+else
-+ifeq ($(CONFIG_GSPI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+endif
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_PCIE.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_SDIO.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8192E #################################
-+ifeq ($(CONFIG_RTL8192E), y)
-+
-+RTL871X = rtl8192e
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8192es
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8192eu
-+endif
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8192ee
-+endif
-+EXTRA_CFLAGS += -DCONFIG_RTL8192E
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+					hal/$(RTL871X)/Hal8192EPwrSeq.o\
-+					hal/$(RTL871X)/$(RTL871X)_xmit.o\
-+					hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+			hal/$(RTL871X)/$(RTL871X)_dm.o \
-+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+			hal/$(RTL871X)/hal8192e_fw.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+else
-+ifeq ($(CONFIG_GSPI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+endif
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_PCIE.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_SDIO.o
-+endif
-+
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+_BTC_FILES += hal/btc/halbtc8192e1ant.o \
-+				hal/btc/halbtc8192e2ant.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8812A_RTL8821A #################################
-+
-+ifneq ($(CONFIG_RTL8812A)_$(CONFIG_RTL8821A), n_n)
-+
-+RTL871X = rtl8812a
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8812au
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8812ae
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8812as
-+endif
-+
-+_HAL_INTFS_FILES +=  hal/HalPwrSeqCmd.o \
-+					hal/$(RTL871X)/Hal8812PwrSeq.o \
-+					hal/$(RTL871X)/Hal8821APwrSeq.o\
-+					hal/$(RTL871X)/$(RTL871X)_xmit.o\
-+					hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+			hal/$(RTL871X)/$(RTL871X)_dm.o \
-+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+else
-+ifeq ($(CONFIG_GSPI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+endif
-+endif
-+
-+ifeq ($(CONFIG_RTL8812A), y)
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8812A_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8812A_PCIE.o
-+endif
-+endif
-+ifeq ($(CONFIG_RTL8821A), y)
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_PCIE.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_SDIO.o
-+endif
-+endif
-+
-+ifeq ($(CONFIG_RTL8812A), y)
-+EXTRA_CFLAGS += -DCONFIG_RTL8812A
-+_HAL_INTFS_FILES +=	hal/rtl8812a/hal8812a_fw.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8821A), y)
-+
-+ifeq ($(CONFIG_RTL8812A), n)
-+
-+RTL871X = rtl8821a
-+ifeq ($(CONFIG_USB_HCI), y)
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+MODULE_NAME := 8821au
-+else
-+MODULE_NAME := 8811au
-+endif
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME := 8821ae
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME := 8821as
-+endif
-+
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8821A
-+
-+_HAL_INTFS_FILES +=	hal/rtl8812a/hal8821a_fw.o
-+		
-+endif
-+
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+ifeq ($(CONFIG_RTL8812A), y)
-+_BTC_FILES += hal/btc/halbtc8812a1ant.o \
-+				hal/btc/halbtc8812a2ant.o
-+endif
-+ifeq ($(CONFIG_RTL8821A), y)
-+_BTC_FILES += hal/btc/halbtc8821a1ant.o \
-+				hal/btc/halbtc8821a2ant.o
-+endif
-+endif
-+
-+endif
-+
-+########### HAL_RTL8723B #################################
-+ifeq ($(CONFIG_RTL8723B), y)
-+
-+RTL871X = rtl8723b
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8723bu
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8723be
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8723bs
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8723B
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+					hal/$(RTL871X)/Hal8723BPwrSeq.o\
-+					hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+			hal/$(RTL871X)/$(RTL871X)_dm.o \
-+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+			hal/$(RTL871X)/hal8723b_fw.o
-+
-+_HAL_INTFS_FILES +=	\
-+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_PCIE.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_SDIO.o
-+endif
-+
-+_BTC_FILES += hal/btc/halbtc8723bwifionly.o
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+_BTC_FILES += hal/btc/halbtc8723b1ant.o \
-+				hal/btc/halbtc8723b2ant.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8814A #################################
-+ifeq ($(CONFIG_RTL8814A), y)
-+## ADD NEW VHT MP HW TX MODE ##
-+#EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE
-+#CONFIG_MP_VHT_HW_TX_MODE = y
-+##########################################
-+RTL871X = rtl8814a
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8814au
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8814ae
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8814as
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8814A
-+
-+_HAL_INTFS_FILES +=  hal/HalPwrSeqCmd.o \
-+					hal/$(RTL871X)/Hal8814PwrSeq.o \
-+					hal/$(RTL871X)/$(RTL871X)_xmit.o\
-+					hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+			hal/$(RTL871X)/$(RTL871X)_dm.o \
-+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+			hal/$(RTL871X)/hal8814a_fw.o
-+
-+
-+_HAL_INTFS_FILES +=	\
-+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+else
-+ifeq ($(CONFIG_GSPI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+endif
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8814A_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8814A_PCIE.o
-+endif
-+
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+_BTC_FILES += hal/btc/halbtc8814a2ant.o
-+endif
-+endif
-+
-+########### HAL_RTL8723C #################################
-+ifeq ($(CONFIG_RTL8723C), y)
-+
-+RTL871X = rtl8703b
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8723cu
-+MODULE_SUB_NAME = 8703bu
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8723ce
-+MODULE_SUB_NAME = 8703be
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8723cs
-+MODULE_SUB_NAME = 8703bs
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8703B
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+					hal/$(RTL871X)/Hal8703BPwrSeq.o\
-+					hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+			hal/$(RTL871X)/$(RTL871X)_dm.o \
-+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+			hal/$(RTL871X)/hal8703b_fw.o
-+
-+_HAL_INTFS_FILES +=	\
-+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8703B_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8703B_PCIE.o
-+endif
-+
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+_BTC_FILES += hal/btc/halbtc8703b1ant.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8723D #################################
-+ifeq ($(CONFIG_RTL8723D), y)
-+
-+RTL871X = rtl8723d
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8723du
-+MODULE_SUB_NAME = 8723du
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8723de
-+MODULE_SUB_NAME = 8723de
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8723ds
-+MODULE_SUB_NAME = 8723ds
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8723D
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+					hal/$(RTL871X)/Hal8723DPwrSeq.o\
-+					hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+			hal/$(RTL871X)/$(RTL871X)_dm.o \
-+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+			hal/$(RTL871X)/hal8723d_fw.o \
-+			hal/$(RTL871X)/$(RTL871X)_lps_poff.o
-+
-+
-+_HAL_INTFS_FILES +=	\
-+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723D_USB.o
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723D_PCIE.o
-+endif
-+
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+_BTC_FILES += hal/btc/halbtc8723d1ant.o \
-+				hal/btc/halbtc8723d2ant.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8723F #################################
-+ifeq ($(CONFIG_RTL8723F), y)
-+RTL871X := rtl8723f
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8723fu
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8723fs
-+endif
-+
-+endif
-+
-+########### HAL_RTL8188F #################################
-+ifeq ($(CONFIG_RTL8188F), y)
-+
-+RTL871X = rtl8188f
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8188fu
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8188fe
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8189fs
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8188F
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+					hal/$(RTL871X)/Hal8188FPwrSeq.o\
-+					hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+			hal/$(RTL871X)/$(RTL871X)_dm.o \
-+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+			hal/$(RTL871X)/hal8188f_fw.o
-+
-+_HAL_INTFS_FILES +=	\
-+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188F_USB.o
-+endif
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188F_SDIO.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8188GTV #################################
-+ifeq ($(CONFIG_RTL8188GTV), y)
-+
-+RTL871X = rtl8188gtv
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8188gtvu
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8189gtvs
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8188GTV
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+					hal/$(RTL871X)/Hal8188GTVPwrSeq.o\
-+					hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+			hal/$(RTL871X)/$(RTL871X)_dm.o \
-+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+			hal/$(RTL871X)/hal8188gtv_fw.o
-+
-+_HAL_INTFS_FILES +=	\
-+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188GTV_USB.o
-+endif
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188GTV_SDIO.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8822B #################################
-+ifeq ($(CONFIG_RTL8822B), y)
-+RTL871X := rtl8822b
-+ifeq ($(CONFIG_USB_HCI), y)
-+ifeq ($(CONFIG_BT_COEXIST), n)
-+MODULE_NAME = 8812bu
-+else
-+MODULE_NAME = 88x2bu
-+endif
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 88x2be
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 88x2bs
-+endif
-+
-+endif
-+########### HAL_RTL8821C #################################
-+ifeq ($(CONFIG_RTL8821C), y)
-+RTL871X := rtl8821c
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8821cu
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8821ce
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8821cs
-+endif
-+
-+endif
-+
-+########### HAL_RTL8710B #################################
-+ifeq ($(CONFIG_RTL8710B), y)
-+
-+RTL871X = rtl8710b
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8710bu
-+MODULE_SUB_NAME = 8710bu
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8710B
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+					hal/$(RTL871X)/Hal8710BPwrSeq.o\
-+					hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+			hal/$(RTL871X)/$(RTL871X)_dm.o \
-+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+			hal/$(RTL871X)/hal8710b_fw.o \
-+			hal/$(RTL871X)/$(RTL871X)_lps_poff.o
-+
-+
-+_HAL_INTFS_FILES +=	\
-+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
-+
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8710B_USB.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8192F #################################
-+ifeq ($(CONFIG_RTL8192F), y)
-+
-+RTL871X = rtl8192f
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8192fu
-+MODULE_SUB_NAME = 8192fu
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8192fe
-+MODULE_SUB_NAME = 8192fe
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 8192fs
-+MODULE_SUB_NAME = 8192fs
-+endif
-+
-+EXTRA_CFLAGS += -DCONFIG_RTL8192F
-+
-+_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
-+					hal/$(RTL871X)/Hal8192FPwrSeq.o\
-+					hal/$(RTL871X)/$(RTL871X)_sreset.o
-+
-+_HAL_INTFS_FILES +=	hal/$(RTL871X)/$(RTL871X)_hal_init.o \
-+			hal/$(RTL871X)/$(RTL871X)_phycfg.o \
-+			hal/$(RTL871X)/$(RTL871X)_rf6052.o \
-+			hal/$(RTL871X)/$(RTL871X)_dm.o \
-+			hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
-+			hal/$(RTL871X)/$(RTL871X)_cmd.o \
-+			hal/$(RTL871X)/hal8192f_fw.o \
-+			hal/$(RTL871X)/$(RTL871X)_lps_poff.o
-+
-+
-+_HAL_INTFS_FILES +=	\
-+			hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \
-+			hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o
-+			
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o
-+else
-+_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o
-+endif
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_SDIO.o
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_USB.o
-+endif
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_PCIE.o
-+endif
-+
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+_BTC_FILES += hal/btc/halbtccommon.o \
-+				hal/btc/halbtc8192f.o
-+endif
-+
-+endif
-+
-+########### HAL_RTL8822C #################################
-+ifeq ($(CONFIG_RTL8822C), y)
-+RTL871X := rtl8822c
-+ifeq ($(CONFIG_USB_HCI), y)
-+ifeq ($(CONFIG_BT_COEXIST), n)
-+MODULE_NAME = 8812cu
-+else
-+MODULE_NAME = 88x2cu
-+endif
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 88x2ce
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME = 88x2cs
-+endif
-+
-+endif
-+
-+########### HAL_RTL8814B #################################
-+ifeq ($(CONFIG_RTL8814B), y)
-+RTL871X := rtl8814b
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME = 8814bu
-+endif
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME = 8814be
-+endif
-+
-+endif
-+
-+########### AUTO_CFG  #################################
-+
-+ifeq ($(CONFIG_AUTOCFG_CP), y)
-+
-+ifeq ($(CONFIG_MULTIDRV), y)
-+$(shell cp $(TopDIR)/autoconf_multidrv_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
-+else
-+ifeq ($(CONFIG_RTL8188E)$(CONFIG_SDIO_HCI),yy)
-+$(shell cp $(TopDIR)/autoconf_rtl8189e_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
-+else ifeq ($(CONFIG_RTL8188F)$(CONFIG_SDIO_HCI),yy)
-+$(shell cp $(TopDIR)/autoconf_rtl8189f_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
-+else ifeq ($(CONFIG_RTL8723C),y)
-+$(shell cp $(TopDIR)/autoconf_rtl8723c_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
-+else
-+$(shell cp $(TopDIR)/autoconf_$(RTL871X)_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h)
-+endif
-+endif
-+
-+endif
-+
-+########### END OF PATH  #################################
-+
-+ifeq ($(CONFIG_AP_MODE), y)
-+EXTRA_CFLAGS += -DCONFIG_AP_MODE
-+endif
-+
-+ifeq ($(CONFIG_P2P), y)
-+EXTRA_CFLAGS += -DCONFIG_P2P
-+ifneq ($(CONFIG_AP_MODE), y)
-+$(error "CONFIG_AP_MODE is required for CONFIG_P2P")
-+endif
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+ifeq ($(CONFIG_USB_AUTOSUSPEND), y)
-+EXTRA_CFLAGS += -DCONFIG_USB_AUTOSUSPEND
-+endif
-+endif
-+
-+ifeq ($(CONFIG_MP_INCLUDED), y)
-+#MODULE_NAME := $(MODULE_NAME)_mp
-+EXTRA_CFLAGS += -DCONFIG_MP_INCLUDED
-+endif
-+
-+ifeq ($(CONFIG_POWER_SAVING), y)
-+ifneq ($(CONFIG_IPS_MODE), default)
-+EXTRA_CFLAGS += -DRTW_IPS_MODE=$(CONFIG_IPS_MODE)
-+endif
-+ifneq ($(CONFIG_LPS_MODE), default)
-+EXTRA_CFLAGS += -DRTW_LPS_MODE=$(CONFIG_LPS_MODE)
-+endif
-+ifneq ($(CONFIG_WOW_LPS_MODE), default)
-+EXTRA_CFLAGS += -DRTW_WOW_LPS_MODE=$(CONFIG_WOW_LPS_MODE)
-+endif
-+EXTRA_CFLAGS += -DCONFIG_POWER_SAVING
-+endif
-+
-+ifeq ($(CONFIG_HW_PWRP_DETECTION), y)
-+EXTRA_CFLAGS += -DCONFIG_HW_PWRP_DETECTION
-+endif
-+
-+ifeq ($(CONFIG_BT_COEXIST), y)
-+EXTRA_CFLAGS += -DCONFIG_BT_COEXIST
-+endif
-+
-+ifeq ($(CONFIG_WAPI_SUPPORT), y)
-+EXTRA_CFLAGS += -DCONFIG_WAPI_SUPPORT
-+endif
-+
-+
-+ifeq ($(CONFIG_EFUSE_CONFIG_FILE), y)
-+EXTRA_CFLAGS += -DCONFIG_EFUSE_CONFIG_FILE
-+
-+#EFUSE_MAP_PATH
-+USER_EFUSE_MAP_PATH ?=
-+ifneq ($(USER_EFUSE_MAP_PATH),)
-+EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"$(USER_EFUSE_MAP_PATH)\"
-+else ifeq ($(MODULE_NAME), 8189es)
-+EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/system/etc/wifi/wifi_efuse_8189e.map\"
-+else ifeq ($(MODULE_NAME), 8723bs)
-+EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/system/etc/wifi/wifi_efuse_8723bs.map\"
-+else
-+EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/vendor/etc/firmware/wifi_efuse_$(MODULE_NAME).map\"
-+endif
-+
-+#WIFIMAC_PATH
-+USER_WIFIMAC_PATH ?=
-+ifneq ($(USER_WIFIMAC_PATH),)
-+EXTRA_CFLAGS += -DWIFIMAC_PATH=\"$(USER_WIFIMAC_PATH)\"
-+else
-+EXTRA_CFLAGS += -DWIFIMAC_PATH=\"/data/wifimac.txt\"
-+endif
-+
-+endif
-+
-+ifeq ($(CONFIG_EXT_CLK), y)
-+EXTRA_CFLAGS += -DCONFIG_EXT_CLK
-+endif
-+
-+ifeq ($(CONFIG_TRAFFIC_PROTECT), y)
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+endif
-+
-+ifeq ($(CONFIG_LOAD_PHY_PARA_FROM_FILE), y)
-+EXTRA_CFLAGS += -DCONFIG_LOAD_PHY_PARA_FROM_FILE
-+#EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER
-+EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"/lib/firmware/\"
-+endif
-+
-+ifeq ($(CONFIG_TXPWR_BY_RATE), n)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE=0
-+else ifeq ($(CONFIG_TXPWR_BY_RATE), y)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE=1
-+endif
-+ifeq ($(CONFIG_TXPWR_BY_RATE_EN), n)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=0
-+else ifeq ($(CONFIG_TXPWR_BY_RATE_EN), y)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=1
-+else ifeq ($(CONFIG_TXPWR_BY_RATE_EN), auto)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=2
-+endif
-+
-+ifeq ($(CONFIG_TXPWR_LIMIT), n)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT=0
-+else ifeq ($(CONFIG_TXPWR_LIMIT), y)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT=1
-+endif
-+ifeq ($(CONFIG_TXPWR_LIMIT_EN), n)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=0
-+else ifeq ($(CONFIG_TXPWR_LIMIT_EN), y)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=1
-+else ifeq ($(CONFIG_TXPWR_LIMIT_EN), auto)
-+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=2
-+endif
-+
-+ifneq ($(CONFIG_RTW_CHPLAN), 0xFF)
-+EXTRA_CFLAGS += -DCONFIG_RTW_CHPLAN=$(CONFIG_RTW_CHPLAN)
-+endif
-+
-+ifeq ($(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY), y)
-+EXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_BY_REGULATORY
-+endif
-+
-+ifeq ($(CONFIG_CALIBRATE_TX_POWER_TO_MAX), y)
-+EXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_TO_MAX
-+endif
-+
-+ifeq ($(CONFIG_RTW_ADAPTIVITY_EN), disable)
-+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_EN=0
-+else ifeq ($(CONFIG_RTW_ADAPTIVITY_EN), enable)
-+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_EN=1
-+endif
-+
-+ifeq ($(CONFIG_RTW_ADAPTIVITY_MODE), normal)
-+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_MODE=0
-+else ifeq ($(CONFIG_RTW_ADAPTIVITY_MODE), carrier_sense)
-+EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_MODE=1
-+endif
-+
-+ifeq ($(CONFIG_SIGNAL_SCALE_MAPPING), y)
-+EXTRA_CFLAGS += -DCONFIG_SIGNAL_SCALE_MAPPING
-+endif
-+
-+ifeq ($(CONFIG_80211W), y)
-+EXTRA_CFLAGS += -DCONFIG_IEEE80211W
-+endif
-+
-+ifeq ($(CONFIG_WOWLAN), y)
-+EXTRA_CFLAGS += -DCONFIG_WOWLAN -DRTW_WAKEUP_EVENT=$(CONFIG_WAKEUP_TYPE)
-+EXTRA_CFLAGS += -DRTW_SUSPEND_TYPE=$(CONFIG_SUSPEND_TYPE)
-+ifeq ($(CONFIG_WOW_STA_MIX), y)
-+EXTRA_CFLAGS += -DRTW_WOW_STA_MIX
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER
-+endif
-+endif
-+
-+ifeq ($(CONFIG_AP_WOWLAN), y)
-+EXTRA_CFLAGS += -DCONFIG_AP_WOWLAN
-+ifeq ($(CONFIG_AP_MODE), n)
-+EXTRA_CFLAGS += -DCONFIG_AP_MODE
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER
-+endif
-+endif
-+
-+ifeq ($(CONFIG_LAYER2_ROAMING), y)
-+EXTRA_CFLAGS += -DCONFIG_LAYER2_ROAMING -DCONFIG_ROAMING_FLAG=$(CONFIG_ROAMING_FLAG)
-+endif
-+
-+ifeq ($(CONFIG_PNO_SUPPORT), y)
-+EXTRA_CFLAGS += -DCONFIG_PNO_SUPPORT
-+ifeq ($(CONFIG_PNO_SET_DEBUG), y)
-+EXTRA_CFLAGS += -DCONFIG_PNO_SET_DEBUG
-+endif
-+endif
-+
-+ifeq ($(CONFIG_GPIO_WAKEUP), y)
-+EXTRA_CFLAGS += -DCONFIG_GPIO_WAKEUP
-+ifeq ($(CONFIG_ONE_PIN_GPIO), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_ONE_PIN_GPIO
-+endif
-+ifeq ($(CONFIG_HIGH_ACTIVE_DEV2HST), y)
-+EXTRA_CFLAGS += -DHIGH_ACTIVE_DEV2HST=1
-+else
-+EXTRA_CFLAGS += -DHIGH_ACTIVE_DEV2HST=0
-+endif
-+endif
-+
-+ifeq ($(CONFIG_HIGH_ACTIVE_HST2DEV), y)
-+EXTRA_CFLAGS += -DHIGH_ACTIVE_HST2DEV=1
-+else
-+EXTRA_CFLAGS += -DHIGH_ACTIVE_HST2DEV=0
-+endif
-+
-+ifneq ($(CONFIG_WAKEUP_GPIO_IDX), default)
-+EXTRA_CFLAGS += -DWAKEUP_GPIO_IDX=$(CONFIG_WAKEUP_GPIO_IDX)
-+endif
-+
-+ifeq ($(CONFIG_RTW_SDIO_PM_KEEP_POWER), y)
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER
-+endif
-+endif
-+
-+ifeq ($(CONFIG_REDUCE_TX_CPU_LOADING), y)
-+EXTRA_CFLAGS += -DCONFIG_REDUCE_TX_CPU_LOADING
-+endif
-+
-+ifeq ($(CONFIG_BR_EXT), y)
-+BR_NAME = br0
-+EXTRA_CFLAGS += -DCONFIG_BR_EXT
-+EXTRA_CFLAGS += '-DCONFIG_BR_EXT_BRNAME="'$(BR_NAME)'"'
-+endif
-+
-+
-+ifeq ($(CONFIG_TDLS), y)
-+EXTRA_CFLAGS += -DCONFIG_TDLS
-+endif
-+
-+ifeq ($(CONFIG_WIFI_MONITOR), y)
-+EXTRA_CFLAGS += -DCONFIG_WIFI_MONITOR
-+endif
-+
-+ifeq ($(CONFIG_MCC_MODE), y)
-+EXTRA_CFLAGS += -DCONFIG_MCC_MODE
-+endif
-+
-+ifeq ($(CONFIG_RTW_NAPI), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_NAPI
-+endif
-+
-+ifeq ($(CONFIG_RTW_GRO), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_GRO
-+endif
-+
-+ifeq ($(CONFIG_RTW_REPEATER_SON), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_REPEATER_SON
-+endif
-+
-+ifeq ($(CONFIG_RTW_IPCAM_APPLICATION), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_IPCAM_APPLICATION
-+ifeq ($(CONFIG_WIFI_MONITOR), n)
-+EXTRA_CFLAGS += -DCONFIG_WIFI_MONITOR
-+endif
-+endif
-+
-+ifeq ($(CONFIG_RTW_NETIF_SG), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_NETIF_SG
-+endif
-+
-+ifeq ($(CONFIG_ICMP_VOQ), y)
-+EXTRA_CFLAGS += -DCONFIG_ICMP_VOQ
-+endif
-+
-+ifeq ($(CONFIG_IP_R_MONITOR), y)
-+EXTRA_CFLAGS += -DCONFIG_IP_R_MONITOR
-+endif
-+
-+ifeq ($(CONFIG_MP_VHT_HW_TX_MODE), y)
-+EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE
-+ifeq ($(CONFIG_PLATFORM_I386_PC), y)
-+## For I386 X86 ToolChain use Hardware FLOATING
-+EXTRA_CFLAGS += -mhard-float
-+else
-+## For ARM ToolChain use Hardware FLOATING
-+EXTRA_CFLAGS += -mfloat-abi=hard
-+endif
-+endif
-+
-+ifeq ($(CONFIG_APPEND_VENDOR_IE_ENABLE), y)
-+EXTRA_CFLAGS += -DCONFIG_APPEND_VENDOR_IE_ENABLE
-+endif
-+
-+ifeq ($(CONFIG_RTW_DEBUG), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_DEBUG
-+EXTRA_CFLAGS += -DRTW_LOG_LEVEL=$(CONFIG_RTW_LOG_LEVEL)
-+endif
-+
-+ifeq ($(CONFIG_PROC_DEBUG), y)
-+EXTRA_CFLAGS += -DCONFIG_PROC_DEBUG
-+endif
-+
-+ifeq ($(CONFIG_RTW_UP_MAPPING_RULE), dscp)
-+EXTRA_CFLAGS += -DCONFIG_RTW_UP_MAPPING_RULE=1
-+else
-+EXTRA_CFLAGS += -DCONFIG_RTW_UP_MAPPING_RULE=0
-+endif
-+
-+EXTRA_CFLAGS += -DDM_ODM_SUPPORT_TYPE=0x04
-+
-+ifeq ($(CONFIG_RTW_MBO), y)
-+EXTRA_CFLAGS += -DCONFIG_RTW_MBO -DCONFIG_RTW_80211K -DCONFIG_RTW_WNM -DCONFIG_RTW_BTM_ROAM
-+EXTRA_CFLAGS += -DCONFIG_RTW_80211R
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_I386_PC), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_RTW_80211R
-+EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE
-+
-+SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
-+ARCH ?= $(SUBARCH)
-+CROSS_COMPILE ?=
-+KVER  := $(shell uname -r)
-+KSRC := /lib/modules/$(KVER)/build
-+MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
-+INSTALL_PREFIX :=
-+STAGINGMODDIR := /lib/modules/$(KVER)/kernel/drivers/staging
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_NV_TK1), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_PLATFORM_ANDROID
-+# Enable this for Android 5.0
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+EXTRA_CFLAGS += -DRTW_VENDOR_EXT_SUPPORT
-+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
-+ARCH ?= arm
-+
-+CROSS_COMPILE := /mnt/newdisk/android_sdk/nvidia_tk1/android_L/prebuilts/gcc/linux-x86/arm/arm-eabi-4.8/bin/arm-eabi-
-+KSRC :=/mnt/newdisk/android_sdk/nvidia_tk1/android_L/out/target/product/shieldtablet/obj/KERNEL/
-+MODULE_NAME = wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_NV_TK1_UBUNTU), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+
-+ARCH ?= arm
-+
-+CROSS_COMPILE ?=
-+KVER := $(shell uname -r)
-+KSRC := /lib/modules/$(KVER)/build
-+MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
-+INSTALL_PREFIX :=
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATM702X), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ACTIONS_ATM702X
-+#ARCH := arm
-+ARCH := $(R_ARCH)
-+#CROSS_COMPILE := arm-none-linux-gnueabi-
-+CROSS_COMPILE := $(R_CROSS_COMPILE)
-+KVER:= 3.4.0
-+#KSRC := ../../../../build/out/kernel
-+KSRC := $(KERNEL_BUILD_PATH)
-+MODULE_NAME :=wlan
-+endif
-+
-+
-+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATM705X), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+#EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
-+# default setting for Android 4.1, 4.2, 4.3, 4.4
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ACTIONS_ATM705X
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+
-+# Enable this for Android 5.0
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+_PLATFORM_FILES += platform/platform_arm_act_sdio.o
-+endif
-+
-+ARCH := arm
-+CROSS_COMPILE := /opt/arm-2011.09/bin/arm-none-linux-gnueabi-
-+KSRC := /home/android_sdk/Action-semi/705a_android_L/android/kernel
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_SUN50IW1P1), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN50IW1P1
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+
-+# Enable this for Android 5.0
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_PLATFORM_FILES += platform/platform_ARM_SUN50IW1P1_sdio.o
-+endif
-+
-+ARCH := arm64
-+# ===Cross compile setting for Android 5.1(64) SDK ===
-+CROSS_COMPILE := /home/android_sdk/Allwinner/a64/android-51/lichee/out/sun50iw1p1/android/common/buildroot/external-toolchain/bin/aarch64-linux-gnu-
-+KSRC :=/home/android_sdk/Allwinner/a64/android-51/lichee/linux-3.10/
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_TI_AM3517), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_SHUTTLE
-+CROSS_COMPILE := arm-eabi-
-+KSRC := $(shell pwd)/../../../Android/kernel
-+ARCH := arm
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MSTAR_TITANIA12), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR -DCONFIG_PLATFORM_MSTAR_TITANIA12
-+ARCH:=mips
-+CROSS_COMPILE:= /usr/src/Mstar_kernel/mips-4.3/bin/mips-linux-gnu-
-+KVER:= 2.6.28.9
-+KSRC:= /usr/src/Mstar_kernel/2.6.28.9/
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MSTAR), y)
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR_HIGH
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX -DCONFIG_FIX_NR_BULKIN_BUFFER
-+endif
-+ARCH:=arm
-+CROSS_COMPILE:= /usr/src/bin/arm-none-linux-gnueabi-
-+KVER:= 3.1.10
-+KSRC:= /usr/src/Mstar_kernel/3.1.10/
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ANDROID_X86), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
-+ARCH := $(SUBARCH)
-+CROSS_COMPILE := /media/DATA-2/android-x86/ics-x86_20120130/prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/bin/i686-unknown-linux-gnu-
-+KSRC := /media/DATA-2/android-x86/ics-x86_20120130/out/target/product/generic_x86/obj/kernel
-+MODULE_NAME :=wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ANDROID_INTEL_X86), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ANDROID_INTEL_X86
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_INTEL_BYT
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_SKIP_SIGNAL_SCALE_MAPPING
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE
-+endif
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_JB_X86), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
-+ARCH := $(SUBARCH)
-+CROSS_COMPILE := /home/android_sdk/android-x86_JB/prebuilts/gcc/linux-x86/x86/i686-linux-android-4.7/bin/i686-linux-android-
-+KSRC := /home/android_sdk/android-x86_JB/out/target/product/x86/obj/kernel/
-+MODULE_NAME :=wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_PXA2XX), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ARCH := arm
-+CROSS_COMPILE := arm-none-linux-gnueabi-
-+KVER  := 2.6.34.1
-+KSRC ?= /usr/src/linux-2.6.34.1
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_S3C2K4), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ARCH := arm
-+CROSS_COMPILE := arm-linux-
-+KVER  := 2.6.24.7_$(ARCH)
-+KSRC := /usr/src/kernels/linux-$(KVER)
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_S3C6K4), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ARCH := arm
-+CROSS_COMPILE := arm-none-linux-gnueabi-
-+KVER  := 2.6.34.1
-+KSRC ?= /usr/src/linux-2.6.34.1
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_RTD2880B), y)
-+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTD2880B
-+ARCH:=
-+CROSS_COMPILE:=
-+KVER:=
-+KSRC:=
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MIPS_RMI), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ARCH:=mips
-+CROSS_COMPILE:=mipsisa32r2-uclibc-
-+KVER:=
-+KSRC:= /root/work/kernel_realtek
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MIPS_PLM), y)
-+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
-+ARCH:=mips
-+CROSS_COMPILE:=mipsisa32r2-uclibc-
-+KVER:=
-+KSRC:= /root/work/kernel_realtek
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MSTAR389), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR389
-+ARCH:=mips
-+CROSS_COMPILE:= mips-linux-gnu-
-+KVER:= 2.6.28.10
-+KSRC:= /home/mstar/mstar_linux/2.6.28.9/
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MIPS_AR9132), y)
-+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
-+ARCH := mips
-+CROSS_COMPILE := mips-openwrt-linux-
-+KSRC := /home/alex/test_openwrt/tmp/linux-2.6.30.9
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_DMP_PHILIPS), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM
-+ARCH := mips
-+#CROSS_COMPILE:=/usr/local/msdk-4.3.6-mips-EL-2.6.12.6-0.9.30.3/bin/mipsel-linux-
-+CROSS_COMPILE:=/usr/local/toolchain_mipsel/bin/mipsel-linux-
-+KSRC ?=/usr/local/Jupiter/linux-2.6.12
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_RTK_DMP), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM  -DCONFIG_WIRELESS_EXT
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+_PLATFORM_FILES += platform/platform_RTK_DMP_usb.o
-+endif
-+ARCH:=mips
-+CROSS_COMPILE:=mipsel-linux-
-+KVER:=
-+KSRC ?= /usr/src/DMP_Kernel/jupiter/linux-2.6.12
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MT53XX), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MT53XX
-+ARCH:= arm
-+CROSS_COMPILE:= arm11_mtk_le-
-+KVER:= 2.6.27
-+KSRC?= /proj/mtk00802/BD_Compare/BDP/Dev/BDP_V301/BDP_Linux/linux-2.6.27
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_MX51_241H), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_WISTRON_PLATFORM
-+ARCH := arm
-+CROSS_COMPILE := /opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-
-+KVER  := 2.6.31
-+KSRC ?= /lib/modules/2.6.31-770-g0e46b52/source
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_FS_MX61), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ARCH := arm
-+CROSS_COMPILE := /home/share/CusEnv/FreeScale/arm-eabi-4.4.3/bin/arm-eabi-
-+KSRC ?= /home/share/CusEnv/FreeScale/FS_kernel_env
-+endif
-+
-+
-+
-+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATJ227X), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATJ227X
-+ARCH := mips
-+CROSS_COMPILE := /home/cnsd4/project/actions/tools-2.6.27/bin/mipsel-linux-gnu-
-+KVER  := 2.6.27
-+KSRC := /home/cnsd4/project/actions/linux-2.6.27.28
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_TI_DM365), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_TI_DM365
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX
-+EXTRA_CFLAGS += -DCONFIG_SINGLE_XMIT_BUF -DCONFIG_SINGLE_RECV_BUF
-+ARCH := arm
-+#CROSS_COMPILE := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/arm/v5t_le/bin/arm_v5t_le-
-+#KSRC := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/lsp/ti-davinci/linux-dm365
-+CROSS_COMPILE := /opt/montavista/pro5.0/devkit/arm/v5t_le/bin/arm-linux-
-+KSRC:= /home/vivotek/lsp/DM365/kernel_platform/kernel/linux-2.6.18
-+KERNELOUTPUT := ${PRODUCTDIR}/tmp
-+KVER  := 2.6.18
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MOZART), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MOZART
-+ARCH := arm
-+CROSS_COMPILE := /home/vivotek/lsp/mozart3v2/Mozart3e_Toolchain/build_arm_nofpu/usr/bin/arm-linux-
-+KVER  := $(shell uname -r)
-+KSRC:= /opt/Vivotek/lsp/mozart3v2/kernel_platform/kernel/mozart_kernel-1.17
-+KERNELOUTPUT := /home/pink/sample/ODM/IP8136W-VINT/tmp/kernel
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_TEGRA3_CARDHU), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
-+KSRC := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/out/target/product/cardhu/obj/KERNEL
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_TEGRA4_DALMORE), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
-+KSRC := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/out/target/product/dalmore/obj/KERNEL
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_TCC8900), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/Telechips/SDK_2304_20110613/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
-+KSRC := /home/android_sdk/Telechips/SDK_2304_20110613/kernel
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_TCC8920), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
-+KSRC := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/kernel
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_TCC8920_JB42), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
-+KSRC := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/kernel
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_RK2818), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS
-+ARCH := arm
-+CROSS_COMPILE := /usr/src/release_fae_version/toolchain/arm-eabi-4.4.0/bin/arm-eabi-
-+KSRC := /usr/src/release_fae_version/kernel25_A7_281x
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_RK3188), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS
-+# default setting for Android 4.1, 4.2, 4.3, 4.4
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_RTW_80211R
-+# default setting for Power control
-+#EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN
-+endif
-+EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE
-+# default setting for Special function
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3188/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
-+KSRC := /home/android_sdk/Rockchip/Rk3188/kernel
-+MODULE_NAME := 8723cs
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_RK3066), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_RK3066
-+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN
-+endif
-+EXTRA_CFLAGS += -fno-pic
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/Rockchip/rk3066_20130607/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi-
-+#CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3066sdk/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi-
-+KSRC := /home/android_sdk/Rockchip/Rk3066sdk/kernel
-+MODULE_NAME :=wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_URBETTER), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE
-+ARCH := arm
-+CROSS_COMPILE := /media/DATA-1/urbetter/arm-2009q3/bin/arm-none-linux-gnueabi-
-+KSRC := /media/DATA-1/urbetter/ics-urbetter/kernel
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_TI_PANDA), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE
-+ARCH := arm
-+#CROSS_COMPILE := /media/DATA-1/aosp/ics-aosp_20111227/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
-+#KSRC := /media/DATA-1/aosp/android-omap-panda-3.0_20120104
-+CROSS_COMPILE := /media/DATA-1/android-4.0/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
-+KSRC := /media/DATA-1/android-4.0/panda_kernel/omap
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_MIPS_JZ4760), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_MINIMAL_MEMORY_USAGE
-+ARCH ?= mips
-+CROSS_COMPILE ?= /mnt/sdb5/Ingenic/Umido/mips-4.3/bin/mips-linux-gnu-
-+KSRC ?= /mnt/sdb5/Ingenic/Umido/kernel
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_SZEBOOK), y)
-+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
-+ARCH:=arm
-+CROSS_COMPILE:=/opt/crosstool2/bin/armeb-unknown-linux-gnueabi-
-+KVER:= 2.6.31.6
-+KSRC:= ../code/linux-2.6.31.6-2020/
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_SUNxI), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUNxI
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+# default setting for A10-EVB mmc0
-+#EXTRA_CFLAGS += -DCONFIG_WITS_EVB_V13
-+_PLATFORM_FILES += platform/platform_ARM_SUNxI_sdio.o
-+endif
-+
-+ARCH := arm
-+#CROSS_COMPILE := arm-none-linux-gnueabi-
-+CROSS_COMPILE=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/buildroot/output/external-toolchain/bin/arm-none-linux-gnueabi-
-+KVER  := 3.0.8
-+#KSRC:= ../lichee/linux-3.0/
-+KSRC=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/linux-3.0
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_SUN6I), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN6I
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2, 4.3, 4.4
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS +=  -DCONFIG_QOS_OPTIMIZATION
-+
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+# default setting for A31-EVB mmc0
-+EXTRA_CFLAGS += -DCONFIG_A31_EVB
-+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
-+endif
-+
-+ARCH := arm
-+#Android-JB42
-+#CROSS_COMPILE := /home/android_sdk/Allwinner/a31/android-jb42/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi-
-+#KSRC :=/home/android_sdk/Allwinner/a31/android-jb42/lichee/linux-3.3
-+#ifeq ($(CONFIG_USB_HCI), y)
-+#MODULE_NAME := 8188eu_sw
-+#endif
-+# ==== Cross compile setting for kitkat-a3x_v4.5 =====
-+CROSS_COMPILE := /home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi-
-+KSRC :=/home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/linux-3.3
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_SUN7I), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2, 4.3, 4.4
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS +=  -DCONFIG_QOS_OPTIMIZATION
-+
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
-+endif
-+
-+ARCH := arm
-+# ===Cross compile setting for Android 4.2 SDK ===
-+#CROSS_COMPILE := /home/android_sdk/Allwinner/a20_evb/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
-+#KSRC := /home/android_sdk/Allwinner/a20_evb/lichee/linux-3.3
-+# ==== Cross compile setting for Android 4.3 SDK =====
-+#CROSS_COMPILE := /home/android_sdk/Allwinner/a20/android-jb43/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
-+#KSRC := /home/android_sdk/Allwinner/a20/android-jb43/lichee/linux-3.4
-+# ==== Cross compile setting for kitkat-a20_v4.4 =====
-+CROSS_COMPILE := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
-+KSRC := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/linux-3.4
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W3P1), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I_W3P1
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
-+endif
-+
-+ARCH := arm
-+# ===Cross compile setting for Android 4.2 SDK ===
-+#CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-jb42/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
-+#KSRC :=/home/android_sdk/Allwinner/a23/android-jb42/lichee/linux-3.4
-+# ===Cross compile setting for Android 4.4 SDK ===
-+CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-kk44/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
-+KSRC :=/home/android_sdk/Allwinner/a23/android-kk44/lichee/linux-3.4
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W5P1), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I_W5P1
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+
-+# Enable this for Android 5.0
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
-+endif
-+
-+ARCH := arm
-+# ===Cross compile setting for Android L SDK ===
-+CROSS_COMPILE := /home/android_sdk/Allwinner/a33/android-L/lichee/out/sun8iw5p1/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
-+KSRC :=/home/android_sdk/Allwinner/a33/android-L/lichee/linux-3.4
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATV5201), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATV5201
-+EXTRA_CFLAGS += -DCONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP
-+ARCH := mips
-+CROSS_COMPILE := mipsel-linux-gnu-
-+KVER  := $(KERNEL_VER)
-+KSRC:= $(CFGDIR)/../../kernel/linux-$(KERNEL_VER)
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_RTD299X), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ifeq ($(CONFIG_ANDROID), y)
-+# Enable this for Android 5.0
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+endif
-+#ARCH, CROSS_COMPILE, KSRC,and  MODDESTDIR are provided by external makefile
-+INSTALL_PREFIX :=
-+MODULE_NAME := wlan
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_RTD299X_LG), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DRTW_P2P_GROUP_INTERFACE=1
-+EXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3
-+#EXTRA_CFLAGS += -DCONFIG_FIX_HWPORT
-+EXTRA_CFLAGS += -DLGE_PRIVATE
-+EXTRA_CFLAGS += -DPURE_SUPPLICANT
-+EXTRA_CFLAGS += -DCONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP -DCONFIG_RTW_IOCTL_SET_COUNTRY
-+EXTRA_CFLAGS += -DDBG_RX_DFRAME_RAW_DATA
-+EXTRA_CFLAGS += -DRTW_REDUCE_SCAN_SWITCH_CH_TIME
-+ARCH ?= arm
-+KVER ?=
-+
-+ifneq ($(PLATFORM), WEBOS)
-+$(info PLATFORM is empty)
-+CROSS_COMPILE ?= /mnt/newdisk/LGE/arm-lg115x-linux-gnueabi-4.8-2016.03-x86_64/bin/arm-lg115x-linux-gnueabi-
-+KSRC ?= /mnt/newdisk/LGE/linux-rockhopper_k3lp_drd4tv_423
-+endif
-+
-+CROSS_COMPILE ?=
-+KSRC ?= $(LINUX_SRC)
-+INSTALL_PREFIX ?=
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_HISILICON), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_HISILICON
-+ifeq ($(SUPPORT_CONCURRENT),y)
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+endif
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH := arm
-+ifeq ($(CROSS_COMPILE),)
-+       CROSS_COMPILE = arm-hisiv200-linux-
-+endif
-+MODULE_NAME := rtl8192eu
-+ifeq ($(KSRC),)
-+       KSRC := ../../../../../../kernel/linux-3.4.y
-+endif
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_HISILICON_HI3798), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON_HI3798
-+#EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON_HI3798_MV200_HDMI_DONGLE
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+# default setting for Android
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
-+EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
-+# default setting for Android 5.x and later
-+#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+
-+# If system could power on and recognize Wi-Fi SDIO automatically,
-+# platfrom operations are not necessary.
-+#ifeq ($(CONFIG_SDIO_HCI), y)
-+#EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+#_PLATFORM_FILES += platform/platform_hisilicon_hi3798_sdio.o
-+#EXTRA_CFLAGS += -DCONFIG_HISI_SDIO_ID=1
-+#endif
-+
-+ARCH ?= arm
-+CROSS_COMPILE ?= /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/tools/linux/toolchains/arm-histbv310-linux/bin/arm-histbv310-linux-
-+ifndef KSRC
-+KSRC := /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/source/kernel/linux-3.18.y
-+KSRC += O=/HiSTBAndroidV600R003C00SPC021_git_0512/out/target/product/Hi3798MV200/obj/KERNEL_OBJ
-+endif
-+
-+ifeq ($(CONFIG_RTL8822B), y)
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+CONFIG_RTL8822BS ?= m
-+USER_MODULE_NAME := rtl8822bs
-+endif
-+endif
-+
-+endif
-+
-+# Platform setting
-+ifeq ($(CONFIG_PLATFORM_ARM_SPREADTRUM_6820), y)
-+ifeq ($(CONFIG_ANDROID_2X), y)
-+EXTRA_CFLAGS += -DANDROID_2X
-+endif
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_SPRD
-+EXTRA_CFLAGS += -DPLATFORM_SPREADTRUM_6820
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ifeq ($(RTL871X), rtl8188e)
-+EXTRA_CFLAGS += -DSOFTAP_PS_DURATION=50
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+_PLATFORM_FILES += platform/platform_sprd_sdio.o
-+endif
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_SPREADTRUM_8810), y)
-+ifeq ($(CONFIG_ANDROID_2X), y)
-+EXTRA_CFLAGS += -DANDROID_2X
-+endif
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_SPRD
-+EXTRA_CFLAGS += -DPLATFORM_SPREADTRUM_8810
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+ifeq ($(RTL871X), rtl8188e)
-+EXTRA_CFLAGS += -DSOFTAP_PS_DURATION=50
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+_PLATFORM_FILES += platform/platform_sprd_sdio.o
-+endif
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_WMT), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_PLATFORM_FILES += platform/platform_ARM_WMT_sdio.o
-+endif
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/WonderMedia/wm8880-android4.4/toolchain/arm_201103_gcc4.5.2/mybin/arm_1103_le-
-+KSRC := /home/android_sdk/WonderMedia/wm8880-android4.4/kernel4.4/
-+MODULE_NAME :=8189es_kk
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_RTK119X), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+#EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+#EXTRA_CFLAGS +=  -DCONFIG_QOS_OPTIMIZATION
-+EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
-+
-+#EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+#_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
-+endif
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
-+endif
-+
-+ARCH := arm
-+
-+# ==== Cross compile setting for Android 4.4 SDK =====
-+#CROSS_COMPILE := arm-linux-gnueabihf-
-+KVER  := 3.10.24
-+#KSRC :=/home/android_sdk/Allwinner/a20/android-kitkat44/lichee/linux-3.4
-+CROSS_COMPILE := /home/realtek/software_phoenix/phoenix/toolchain/usr/local/arm-2013.11/bin/arm-linux-gnueabihf-
-+KSRC := /home/realtek/software_phoenix/linux-kernel
-+MODULE_NAME := 8192eu
-+
-+endif
-+
-+# Actions-Micro use this flag for DHC 1195 and DHC 1395
-+ifeq ($(CONFIG_PLATFORM_RTK119X_AM), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_RTK119X_AM
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_FULL_CH_IN_P2P_HANDSHAKE
-+EXTRA_CFLAGS += -DCONFIG_SEL_P2P_IFACE=2
-+EXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+endif
-+
-+ARCH := arm
-+
-+#CROSS_COMPILE := arm-linux-gnueabihf-
-+KVER  := 3.10.24
-+#KSRC :=
-+CROSS_COMPILE :=
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_RTK129X), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_RTK129X
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+#EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_QOS_OPTIMIZATION
-+EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
-+# Enable this for Android 5.0
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+ifeq ($(CONFIG_RTL8821C)$(CONFIG_SDIO_HCI),yy)
-+EXTRA_CFLAGS += -DCONFIG_WAKEUP_GPIO_INPUT_MODE
-+EXTRA_CFLAGS += -DCONFIG_BT_WAKE_HST_OPEN_DRAIN
-+endif
-+EXTRA_CFLAGS += -Wno-error=date-time
-+# default setting for Android 7.0
-+ifeq ($(RTK_ANDROID_VERSION), nougat)
-+EXTRA_CFLAGS += -DRTW_P2P_GROUP_INTERFACE=1
-+endif
-+#EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+endif
-+
-+ARCH := arm64
-+
-+# ==== Cross compile setting for Android 4.4 SDK =====
-+#CROSS_COMPILE := arm-linux-gnueabihf-
-+#KVER  := 4.1.10
-+#CROSS_COMPILE := $(CROSS)
-+#KSRC := $(LINUX_KERNEL_PATH)
-+CROSS_COMPILE := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/phoenix/toolchain/asdk64-4.9.4-a53-EL-3.10-g2.19-a64nt-160307/bin/asdk64-linux-
-+KSRC := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/linux-kernel
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_RTK1319), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_RTK1319
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+#EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_QOS_OPTIMIZATION
-+EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
-+# Enable this for Android 5.0
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+ifeq ($(CONFIG_RTL8821C)$(CONFIG_SDIO_HCI),yy)
-+EXTRA_CFLAGS += -DCONFIG_WAKEUP_GPIO_INPUT_MODE
-+EXTRA_CFLAGS += -DCONFIG_BT_WAKE_HST_OPEN_DRAIN
-+endif
-+EXTRA_CFLAGS += -Wno-error=date-time
-+# default setting for Android 7.0
-+ifeq ($(RTK_ANDROID_VERSION), nougat)
-+EXTRA_CFLAGS += -DRTW_P2P_GROUP_INTERFACE=1
-+endif
-+#EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+endif
-+
-+ARCH := arm64
-+
-+# ==== Cross compile setting for Android 4.4 SDK =====
-+#CROSS_COMPILE := arm-linux-gnueabihf-
-+#KVER  := 4.1.10
-+#CROSS_COMPILE := $(CROSS)
-+#KSRC := $(LINUX_KERNEL_PATH)
-+CROSS_COMPILE := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/phoenix/toolchain/asdk64-4.9.4-a53-EL-3.10-g2.19-a64nt-160307/bin/asdk64-linux-
-+KSRC := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/linux-kernel
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_RTK390X), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_RTK390X
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_RTW_NETIF_SG
-+ifeq ($(CONFIG_USB_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+endif
-+
-+ARCH:=rlx
-+
-+CROSS_COMPILE:=mips-linux-
-+KSRC:= /home/realtek/share/Develop/IPCAM_SDK/RealSil/rts3901_sdk_v1.2_vanilla/linux-3.10
-+
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_NOVATEK_NT72668), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_NOVATEK_NT72668
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX
-+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
-+ARCH ?= arm
-+CROSS_COMPILE := arm-linux-gnueabihf-
-+KVER := 3.8.0
-+KSRC := /Custom/Novatek/TCL/linux-3.8_header
-+#KSRC := $(KERNELDIR)
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ARM_TCC8930_JB42), y)
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+# default setting for Android 4.1, 4.2
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-+ARCH := arm
-+CROSS_COMPILE := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
-+KSRC := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/kernel
-+MODULE_NAME := wlan
-+endif 
-+
-+ifeq ($(CONFIG_PLATFORM_RTL8197D), y)
-+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTL8197D
-+export DIR_LINUX=$(shell pwd)/../SDK/rlxlinux-sdk321-v50/linux-2.6.30
-+ARCH ?= rlx
-+CROSS_COMPILE:= $(DIR_LINUX)/../toolchain/rsdk-1.5.5-5281-EB-2.6.30-0.9.30.3-110714/bin/rsdk-linux-
-+KSRC := $(DIR_LINUX)
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_AML_S905), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_AML_S905
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -fno-pic
-+# default setting for Android
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
-+EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
-+# default setting for Android 5.x and later
-+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+_PLATFORM_FILES += platform/platform_aml_s905_sdio.o
-+endif
-+
-+ARCH ?= arm64
-+CROSS_COMPILE ?= /4.4_S905L_8822bs_compile/gcc-linaro-aarch64-linux-gnu-4.9-2014.09_linux/bin/aarch64-linux-gnu-
-+ifndef KSRC
-+KSRC := /4.4_S905L_8822bs_compile/common
-+# To locate output files in a separate directory.
-+KSRC += O=/4.4_S905L_8822bs_compile/KERNEL_OBJ
-+endif
-+
-+ifeq ($(CONFIG_RTL8822B), y)
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+CONFIG_RTL8822BS ?= m
-+USER_MODULE_NAME := 8822bs
-+endif
-+endif
-+
-+endif
-+
-+ifeq ($(CONFIG_PLATFORM_ZTE_ZX296716), y)
-+EXTRA_CFLAGS += -Wno-error=date-time
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ZTE_ZX296716
-+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-+# default setting for Android
-+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
-+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
-+EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
-+# default setting for Android 5.x and later
-+#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+# mark this temporarily
-+#EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
-+#_PLATFORM_FILES += platform/platform_zte_zx296716_sdio.o
-+endif
-+
-+ARCH ?= arm64
-+CROSS_COMPILE ?=
-+KSRC ?=
-+
-+ifeq ($(CONFIG_RTL8822B), y)
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+CONFIG_RTL8822BS ?= m
-+USER_MODULE_NAME := 8822bs
-+endif
-+endif
-+
-+endif
-+
-+########### CUSTOMER ################################
-+ifeq ($(CONFIG_CUSTOMER_HUAWEI_GENERAL), y)
-+CONFIG_CUSTOMER_HUAWEI = y
-+endif
-+
-+ifeq ($(CONFIG_CUSTOMER_HUAWEI), y)
-+EXTRA_CFLAGS += -DCONFIG_HUAWEI_PROC
-+endif
-+
-+CONFIG_PLATFORM_CMAP_INTFS = n
-+ifeq ($(CONFIG_PLATFORM_CMAP_INTFS), y)
-+PLATFORM_CMAP_INTFS_TYPE = 00
-+EXTRA_CFLAGS += -DCONFIG_PLATFORM_CMAP_INTFS -DCMAP_UNASSOC_METRICS_STA_MAX=32
-+_OS_INTFS_FILES += os_dep/linux/custom_multiap_intfs/custom_multiap_intfs.o
-+_PLATFORM_FILES += platform/custom_multiap_intfs_$(PLATFORM_CMAP_INTFS_TYPE).o
-+endif
-+
-+ifeq ($(CONFIG_MULTIDRV), y)
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+MODULE_NAME := rtw_sdio
-+endif
-+
-+ifeq ($(CONFIG_USB_HCI), y)
-+MODULE_NAME := rtw_usb
-+endif
-+
-+ifeq ($(CONFIG_PCI_HCI), y)
-+MODULE_NAME := rtw_pci
-+endif
-+
-+
-+endif
-+
-+USER_MODULE_NAME ?=
-+ifneq ($(USER_MODULE_NAME),)
-+MODULE_NAME := $(USER_MODULE_NAME)
-+endif
-+
-+ifneq ($(KERNELRELEASE),)
-+
-+########### this part for *.mk ############################
-+include $(srctree)/$(src)/hal/phydm/phydm.mk
-+
-+########### HAL_RTL8822B #################################
-+ifeq ($(CONFIG_RTL8822B), y)
-+include $(srctree)/$(src)/rtl8822b.mk
-+endif
-+
-+########### HAL_RTL8821C #################################
-+ifeq ($(CONFIG_RTL8821C), y)
-+include $(srctree)/$(src)/rtl8821c.mk
-+endif
-+
-+########### HAL_RTL8822C #################################
-+ifeq ($(CONFIG_RTL8822C), y)
-+include $(srctree)/$(src)/rtl8822c.mk
-+endif
-+
-+########### HAL_RTL8814B #################################
-+ifeq ($(CONFIG_RTL8814B), y)
-+include $(srctree)/$(src)/rtl8814b.mk
-+endif
-+
-+########### HAL_RTL8723F #################################
-+ifeq ($(CONFIG_RTL8723F), y)
-+include $(srctree)/$(src)/rtl8723f.mk
-+endif
-+
-+rtk_core :=	core/rtw_cmd.o \
-+		core/rtw_security.o \
-+		core/rtw_debug.o \
-+		core/rtw_io.o \
-+		core/rtw_ioctl_query.o \
-+		core/rtw_ioctl_set.o \
-+		core/rtw_ieee80211.o \
-+		core/rtw_mlme.o \
-+		core/rtw_mlme_ext.o \
-+		core/rtw_mi.o \
-+		core/rtw_wlan_util.o \
-+		core/rtw_vht.o \
-+		core/rtw_pwrctrl.o \
-+		core/rtw_rf.o \
-+		core/rtw_chplan.o \
-+		core/monitor/rtw_radiotap.o \
-+		core/rtw_recv.o \
-+		core/rtw_sta_mgt.o \
-+		core/rtw_ap.o \
-+		core/wds/rtw_wds.o \
-+		core/mesh/rtw_mesh.o \
-+		core/mesh/rtw_mesh_pathtbl.o \
-+		core/mesh/rtw_mesh_hwmp.o \
-+		core/rtw_xmit.o	\
-+		core/rtw_p2p.o \
-+		core/rtw_rson.o \
-+		core/rtw_tdls.o \
-+		core/rtw_br_ext.o \
-+		core/rtw_iol.o \
-+		core/rtw_sreset.o \
-+		core/rtw_btcoex_wifionly.o \
-+		core/rtw_btcoex.o \
-+		core/rtw_beamforming.o \
-+		core/rtw_odm.o \
-+		core/rtw_rm.o \
-+		core/rtw_rm_fsm.o \
-+		core/rtw_ft.o \
-+		core/rtw_wnm.o \
-+		core/rtw_mbo.o \
-+		core/rtw_rm_util.o \
-+		core/efuse/rtw_efuse.o \
-+		core/rtw_roch.o
-+
-+ifeq ($(CONFIG_SDIO_HCI), y)
-+rtk_core += core/rtw_sdio.o
-+endif
-+
-+EXTRA_CFLAGS += -I$(srctree)/$(src)/core/crypto
-+rtk_core += \
-+		core/crypto/aes-internal.o \
-+		core/crypto/aes-internal-enc.o \
-+		core/crypto/aes-gcm.o \
-+		core/crypto/aes-ccm.o \
-+		core/crypto/aes-omac1.o \
-+		core/crypto/ccmp.o \
-+		core/crypto/gcmp.o \
-+		core/crypto/aes-siv.o \
-+		core/crypto/aes-ctr.o \
-+		core/crypto/sha256-internal.o \
-+		core/crypto/sha256.o \
-+		core/crypto/sha256-prf.o \
-+		core/crypto/rtw_crypto_wrap.o \
-+		core/rtw_swcrypto.o
-+
-+$(MODULE_NAME)-y += $(rtk_core)
-+
-+$(MODULE_NAME)-$(CONFIG_WAPI_SUPPORT) += core/rtw_wapi.o	\
-+					core/rtw_wapi_sms4.o
-+
-+$(MODULE_NAME)-y += $(_OS_INTFS_FILES)
-+$(MODULE_NAME)-y += $(_HAL_INTFS_FILES)
-+$(MODULE_NAME)-y += $(_PHYDM_FILES)
-+$(MODULE_NAME)-y += $(_BTC_FILES)
-+$(MODULE_NAME)-y += $(_PLATFORM_FILES)
-+
-+$(MODULE_NAME)-$(CONFIG_MP_INCLUDED) += core/rtw_mp.o
-+
-+ifeq ($(CONFIG_RTL8723B), y)
-+$(MODULE_NAME)-$(CONFIG_MP_INCLUDED)+= core/rtw_bt_mp.o
-+endif
-+
-+obj-$(CONFIG_RTL8723CS) := $(MODULE_NAME).o
-+
-+else
-+
-+export CONFIG_RTL8723CS = m
-+
-+all: modules
-+
-+modules:
-+	$(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd)  modules
-+
-+strip:
-+	$(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded
-+
-+install:
-+	install -p -m 644 $(MODULE_NAME).ko  $(MODDESTDIR)
-+	/sbin/depmod -a ${KVER}
-+
-+uninstall:
-+	rm -f $(MODDESTDIR)/$(MODULE_NAME).ko
-+	/sbin/depmod -a ${KVER}
-+
-+backup_rtlwifi:
-+	@echo "Making backup rtlwifi drivers"
-+ifneq (,$(wildcard $(STAGINGMODDIR)/rtl*))
-+	@tar cPf $(wildcard $(STAGINGMODDIR))/backup_rtlwifi_driver.tar $(wildcard $(STAGINGMODDIR)/rtl*)
-+	@rm -rf $(wildcard $(STAGINGMODDIR)/rtl*)
-+endif
-+ifneq (,$(wildcard $(MODDESTDIR)realtek))
-+	@tar cPf $(MODDESTDIR)backup_rtlwifi_driver.tar $(MODDESTDIR)realtek
-+	@rm -fr $(MODDESTDIR)realtek
-+endif
-+ifneq (,$(wildcard $(MODDESTDIR)rtl*))
-+	@tar cPf $(MODDESTDIR)../backup_rtlwifi_driver.tar $(wildcard $(MODDESTDIR)rtl*)
-+	@rm -fr $(wildcard $(MODDESTDIR)rtl*)
-+endif
-+	@/sbin/depmod -a ${KVER}
-+	@echo "Please reboot your system"
-+
-+restore_rtlwifi:
-+	@echo "Restoring backups"
-+ifneq (,$(wildcard $(STAGINGMODDIR)/backup_rtlwifi_driver.tar))
-+	@tar xPf $(STAGINGMODDIR)/backup_rtlwifi_driver.tar
-+	@rm $(STAGINGMODDIR)/backup_rtlwifi_driver.tar
-+endif
-+ifneq (,$(wildcard $(MODDESTDIR)backup_rtlwifi_driver.tar))
-+	@tar xPf $(MODDESTDIR)backup_rtlwifi_driver.tar
-+	@rm $(MODDESTDIR)backup_rtlwifi_driver.tar
-+endif
-+ifneq (,$(wildcard $(MODDESTDIR)../backup_rtlwifi_driver.tar))
-+	@tar xPf $(MODDESTDIR)../backup_rtlwifi_driver.tar
-+	@rm $(MODDESTDIR)../backup_rtlwifi_driver.tar
-+endif
-+	@/sbin/depmod -a ${KVER}
-+	@echo "Please reboot your system"
-+
-+config_r:
-+	@echo "make config"
-+	/bin/bash script/Configure script/config.in
-+
-+
-+.PHONY: modules clean
-+
-+clean:
-+	#$(MAKE) -C $(KSRC) M=$(shell pwd) clean
-+	cd hal ; rm -fr */*/*/*.mod.c */*/*/*.mod */*/*/*.o */*/*/.*.cmd */*/*/*.ko
-+	cd hal ; rm -fr */*/*.mod.c */*/*.mod */*/*.o */*/.*.cmd */*/*.ko
-+	cd hal ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko
-+	cd hal ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
-+	cd core ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko
-+	cd core ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
-+	cd os_dep/linux ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
-+	cd os_dep ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
-+	cd platform ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
-+	rm -fr Module.symvers ; rm -fr Module.markers ; rm -fr modules.order
-+	rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~
-+	rm -fr .tmp_versions
-+endif
-+
-diff --git a/drivers/staging/rtl8723cs/clean b/drivers/staging/rtl8723cs/clean
-new file mode 100644
-index 000000000000..87664218b889
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/clean
-@@ -0,0 +1,5 @@
-+#!/bin/bash
-+rmmod 8192cu
-+rmmod 8192ce
-+rmmod 8192du
-+rmmod 8192de
-diff --git a/drivers/staging/rtl8723cs/core/crypto/aes-ccm.c b/drivers/staging/rtl8723cs/core/crypto/aes-ccm.c
-new file mode 100644
-index 000000000000..a2309b5f14f5
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/aes-ccm.c
-@@ -0,0 +1,211 @@
-+/*
-+ * Counter with CBC-MAC (CCM) with AES
-+ *
-+ * Copyright (c) 2010-2012, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#include "rtw_crypto_wrap.h"
-+
-+#include "aes.h"
-+#include "aes_wrap.h"
-+
-+
-+static void xor_aes_block(u8 *dst, const u8 *src)
-+{
-+	u32 *d = (u32 *) dst;
-+	u32 *s = (u32 *) src;
-+	*d++ ^= *s++;
-+	*d++ ^= *s++;
-+	*d++ ^= *s++;
-+	*d++ ^= *s++;
-+}
-+
-+
-+static void aes_ccm_auth_start(void *aes, size_t M, size_t L, const u8 *nonce,
-+			       const u8 *aad, size_t aad_len, size_t plain_len,
-+			       u8 *x)
-+{
-+	u8 aad_buf[2 * AES_BLOCK_SIZE];
-+	u8 b[AES_BLOCK_SIZE];
-+
-+	/* Authentication */
-+	/* B_0: Flags | Nonce N | l(m) */
-+	b[0] = aad_len ? 0x40 : 0 /* Adata */;
-+	b[0] |= (((M - 2) / 2) /* M' */ << 3);
-+	b[0] |= (L - 1) /* L' */;
-+	os_memcpy(&b[1], nonce, 15 - L);
-+	WPA_PUT_BE16(&b[AES_BLOCK_SIZE - L], plain_len);
-+
-+	wpa_hexdump_key(_MSG_EXCESSIVE_, "CCM B_0", b, AES_BLOCK_SIZE);
-+	aes_encrypt_128(aes, b, x); /* X_1 = E(K, B_0) */
-+
-+	if (!aad_len)
-+		return;
-+
-+	WPA_PUT_BE16(aad_buf, aad_len);
-+	os_memcpy(aad_buf + 2, aad, aad_len);
-+	os_memset(aad_buf + 2 + aad_len, 0, sizeof(aad_buf) - 2 - aad_len);
-+
-+	xor_aes_block(aad_buf, x);
-+	aes_encrypt_128(aes, aad_buf, x); /* X_2 = E(K, X_1 XOR B_1) */
-+
-+	if (aad_len > AES_BLOCK_SIZE - 2) {
-+		xor_aes_block(&aad_buf[AES_BLOCK_SIZE], x);
-+		/* X_3 = E(K, X_2 XOR B_2) */
-+		aes_encrypt_128(aes, &aad_buf[AES_BLOCK_SIZE], x);
-+	}
-+}
-+
-+
-+static void aes_ccm_auth(void *aes, const u8 *data, size_t len, u8 *x)
-+{
-+	size_t last = len % AES_BLOCK_SIZE;
-+	size_t i;
-+
-+	for (i = 0; i < len / AES_BLOCK_SIZE; i++) {
-+		/* X_i+1 = E(K, X_i XOR B_i) */
-+		xor_aes_block(x, data);
-+		data += AES_BLOCK_SIZE;
-+		aes_encrypt_128(aes, x, x);
-+	}
-+	if (last) {
-+		/* XOR zero-padded last block */
-+		for (i = 0; i < last; i++)
-+			x[i] ^= *data++;
-+		aes_encrypt_128(aes, x, x);
-+	}
-+}
-+
-+
-+static void aes_ccm_encr_start(size_t L, const u8 *nonce, u8 *a)
-+{
-+	/* A_i = Flags | Nonce N | Counter i */
-+	a[0] = L - 1; /* Flags = L' */
-+	os_memcpy(&a[1], nonce, 15 - L);
-+}
-+
-+
-+static void aes_ccm_encr(void *aes, size_t L, const u8 *in, size_t len, u8 *out,
-+			 u8 *a)
-+{
-+	size_t last = len % AES_BLOCK_SIZE;
-+	size_t i;
-+
-+	/* crypt = msg XOR (S_1 | S_2 | ... | S_n) */
-+	for (i = 1; i <= len / AES_BLOCK_SIZE; i++) {
-+		WPA_PUT_BE16(&a[AES_BLOCK_SIZE - 2], i);
-+		/* S_i = E(K, A_i) */
-+		aes_encrypt_128(aes, a, out);
-+		xor_aes_block(out, in);
-+		out += AES_BLOCK_SIZE;
-+		in += AES_BLOCK_SIZE;
-+	}
-+	if (last) {
-+		WPA_PUT_BE16(&a[AES_BLOCK_SIZE - 2], i);
-+		aes_encrypt_128(aes, a, out);
-+		/* XOR zero-padded last block */
-+		for (i = 0; i < last; i++)
-+			*out++ ^= *in++;
-+	}
-+}
-+
-+
-+static void aes_ccm_encr_auth(void *aes, size_t M, u8 *x, u8 *a, u8 *auth)
-+{
-+	size_t i;
-+	u8 tmp[AES_BLOCK_SIZE];
-+
-+	wpa_hexdump_key(_MSG_EXCESSIVE_, "CCM T", x, M);
-+	/* U = T XOR S_0; S_0 = E(K, A_0) */
-+	WPA_PUT_BE16(&a[AES_BLOCK_SIZE - 2], 0);
-+	aes_encrypt_128(aes, a, tmp);
-+	for (i = 0; i < M; i++)
-+		auth[i] = x[i] ^ tmp[i];
-+	wpa_hexdump_key(_MSG_EXCESSIVE_, "CCM U", auth, M);
-+}
-+
-+
-+static void aes_ccm_decr_auth(void *aes, size_t M, u8 *a, const u8 *auth, u8 *t)
-+{
-+	size_t i;
-+	u8 tmp[AES_BLOCK_SIZE];
-+
-+	wpa_hexdump_key(_MSG_EXCESSIVE_, "CCM U", auth, M);
-+	/* U = T XOR S_0; S_0 = E(K, A_0) */
-+	WPA_PUT_BE16(&a[AES_BLOCK_SIZE - 2], 0);
-+	aes_encrypt_128(aes, a, tmp);
-+	for (i = 0; i < M; i++)
-+		t[i] = auth[i] ^ tmp[i];
-+	wpa_hexdump_key(_MSG_EXCESSIVE_, "CCM T", t, M);
-+}
-+
-+
-+/* AES-CCM with fixed L=2 and aad_len <= 30 assumption */
-+int aes_ccm_ae(const u8 *key, size_t key_len, const u8 *nonce,
-+	       size_t M, const u8 *plain, size_t plain_len,
-+	       const u8 *aad, size_t aad_len, u8 *crypt, u8 *auth)
-+{
-+	const size_t L = 2;
-+	void *aes;
-+	u8 x[AES_BLOCK_SIZE], a[AES_BLOCK_SIZE];
-+
-+	if (aad_len > 30 || M > AES_BLOCK_SIZE)
-+		return -1;
-+
-+	aes = aes_encrypt_init(key, key_len);
-+	if (aes == NULL)
-+		return -1;
-+
-+	aes_ccm_auth_start(aes, M, L, nonce, aad, aad_len, plain_len, x);
-+	aes_ccm_auth(aes, plain, plain_len, x);
-+
-+	/* Encryption */
-+	aes_ccm_encr_start(L, nonce, a);
-+	aes_ccm_encr(aes, L, plain, plain_len, crypt, a);
-+	aes_ccm_encr_auth(aes, M, x, a, auth);
-+
-+	aes_encrypt_deinit(aes);
-+
-+	return 0;
-+}
-+
-+
-+/* AES-CCM with fixed L=2 and aad_len <= 30 assumption */
-+int aes_ccm_ad(const u8 *key, size_t key_len, const u8 *nonce,
-+	       size_t M, const u8 *crypt, size_t crypt_len,
-+	       const u8 *aad, size_t aad_len, const u8 *auth, u8 *plain)
-+{
-+	const size_t L = 2;
-+	void *aes;
-+	u8 x[AES_BLOCK_SIZE], a[AES_BLOCK_SIZE];
-+	u8 t[AES_BLOCK_SIZE];
-+
-+	if (aad_len > 30 || M > AES_BLOCK_SIZE)
-+		return -1;
-+
-+	aes = aes_encrypt_init(key, key_len);
-+	if (aes == NULL)
-+		return -1;
-+
-+	/* Decryption */
-+	aes_ccm_encr_start(L, nonce, a);
-+	aes_ccm_decr_auth(aes, M, a, auth, t);
-+
-+	/* plaintext = msg XOR (S_1 | S_2 | ... | S_n) */
-+	aes_ccm_encr(aes, L, crypt, crypt_len, plain, a);
-+
-+	aes_ccm_auth_start(aes, M, L, nonce, aad, aad_len, crypt_len, x);
-+	aes_ccm_auth(aes, plain, crypt_len, x);
-+
-+	aes_encrypt_deinit(aes);
-+
-+	if (os_memcmp_const(x, t, M) != 0) {
-+		wpa_printf(_MSG_EXCESSIVE_, "CCM: Auth mismatch");
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-diff --git a/drivers/staging/rtl8723cs/core/crypto/aes-ctr.c b/drivers/staging/rtl8723cs/core/crypto/aes-ctr.c
-new file mode 100644
-index 000000000000..9533709b7485
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/aes-ctr.c
-@@ -0,0 +1,70 @@
-+/*
-+ * AES-128/192/256 CTR
-+ *
-+ * Copyright (c) 2003-2007, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#include "rtw_crypto_wrap.h"
-+
-+#include "aes.h"
-+#include "aes_wrap.h"
-+
-+/**
-+ * aes_ctr_encrypt - AES-128/192/256 CTR mode encryption
-+ * @key: Key for encryption (key_len bytes)
-+ * @key_len: Length of the key (16, 24, or 32 bytes)
-+ * @nonce: Nonce for counter mode (16 bytes)
-+ * @data: Data to encrypt in-place
-+ * @data_len: Length of data in bytes
-+ * Returns: 0 on success, -1 on failure
-+ */
-+int aes_ctr_encrypt(const u8 *key, size_t key_len, const u8 *nonce,
-+		    u8 *data, size_t data_len)
-+{
-+	void *ctx;
-+	size_t j, len, left = data_len;
-+	int i;
-+	u8 *pos = data;
-+	u8 counter[AES_BLOCK_SIZE], buf[AES_BLOCK_SIZE];
-+
-+	ctx = aes_encrypt_init(key, key_len);
-+	if (ctx == NULL)
-+		return -1;
-+	os_memcpy(counter, nonce, AES_BLOCK_SIZE);
-+
-+	while (left > 0) {
-+		aes_encrypt_128(ctx, counter, buf);
-+
-+		len = (left < AES_BLOCK_SIZE) ? left : AES_BLOCK_SIZE;
-+		for (j = 0; j < len; j++)
-+			pos[j] ^= buf[j];
-+		pos += len;
-+		left -= len;
-+
-+		for (i = AES_BLOCK_SIZE - 1; i >= 0; i--) {
-+			counter[i]++;
-+			if (counter[i])
-+				break;
-+		}
-+	}
-+	aes_encrypt_deinit(ctx);
-+	return 0;
-+}
-+
-+
-+/**
-+ * aes_128_ctr_encrypt - AES-128 CTR mode encryption
-+ * @key: Key for encryption (key_len bytes)
-+ * @nonce: Nonce for counter mode (16 bytes)
-+ * @data: Data to encrypt in-place
-+ * @data_len: Length of data in bytes
-+ * Returns: 0 on success, -1 on failure
-+ */
-+int aes_128_ctr_encrypt(const u8 *key, const u8 *nonce,
-+			u8 *data, size_t data_len)
-+{
-+	return aes_ctr_encrypt(key, 16, nonce, data, data_len);
-+}
-diff --git a/drivers/staging/rtl8723cs/core/crypto/aes-gcm.c b/drivers/staging/rtl8723cs/core/crypto/aes-gcm.c
-new file mode 100644
-index 000000000000..76061f53db24
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/aes-gcm.c
-@@ -0,0 +1,326 @@
-+/*
-+ * Galois/Counter Mode (GCM) and GMAC with AES
-+ *
-+ * Copyright (c) 2012, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#include "rtw_crypto_wrap.h"
-+
-+#include "aes.h"
-+#include "aes_wrap.h"
-+
-+static void inc32(u8 *block)
-+{
-+	u32 val;
-+	val = WPA_GET_BE32(block + AES_BLOCK_SIZE - 4);
-+	val++;
-+	WPA_PUT_BE32(block + AES_BLOCK_SIZE - 4, val);
-+}
-+
-+
-+static void xor_block(u8 *dst, const u8 *src)
-+{
-+	u32 *d = (u32 *) dst;
-+	u32 *s = (u32 *) src;
-+	*d++ ^= *s++;
-+	*d++ ^= *s++;
-+	*d++ ^= *s++;
-+	*d++ ^= *s++;
-+}
-+
-+
-+static void shift_right_block(u8 *v)
-+{
-+	u32 val;
-+
-+	val = WPA_GET_BE32(v + 12);
-+	val >>= 1;
-+	if (v[11] & 0x01)
-+		val |= 0x80000000;
-+	WPA_PUT_BE32(v + 12, val);
-+
-+	val = WPA_GET_BE32(v + 8);
-+	val >>= 1;
-+	if (v[7] & 0x01)
-+		val |= 0x80000000;
-+	WPA_PUT_BE32(v + 8, val);
-+
-+	val = WPA_GET_BE32(v + 4);
-+	val >>= 1;
-+	if (v[3] & 0x01)
-+		val |= 0x80000000;
-+	WPA_PUT_BE32(v + 4, val);
-+
-+	val = WPA_GET_BE32(v);
-+	val >>= 1;
-+	WPA_PUT_BE32(v, val);
-+}
-+
-+
-+/* Multiplication in GF(2^128) */
-+static void gf_mult(const u8 *x, const u8 *y, u8 *z)
-+{
-+	u8 v[16];
-+	int i, j;
-+
-+	os_memset(z, 0, 16); /* Z_0 = 0^128 */
-+	os_memcpy(v, y, 16); /* V_0 = Y */
-+
-+	for (i = 0; i < 16; i++) {
-+		for (j = 0; j < 8; j++) {
-+			if (x[i] & BIT(7 - j)) {
-+				/* Z_(i + 1) = Z_i XOR V_i */
-+				xor_block(z, v);
-+			} else {
-+				/* Z_(i + 1) = Z_i */
-+			}
-+
-+			if (v[15] & 0x01) {
-+				/* V_(i + 1) = (V_i >> 1) XOR R */
-+				shift_right_block(v);
-+				/* R = 11100001 || 0^120 */
-+				v[0] ^= 0xe1;
-+			} else {
-+				/* V_(i + 1) = V_i >> 1 */
-+				shift_right_block(v);
-+			}
-+		}
-+	}
-+}
-+
-+
-+static void ghash_start(u8 *y)
-+{
-+	/* Y_0 = 0^128 */
-+	os_memset(y, 0, 16);
-+}
-+
-+
-+static void ghash(const u8 *h, const u8 *x, size_t xlen, u8 *y)
-+{
-+	size_t m, i;
-+	const u8 *xpos = x;
-+	u8 tmp[16];
-+
-+	m = xlen / 16;
-+
-+	for (i = 0; i < m; i++) {
-+		/* Y_i = (Y^(i-1) XOR X_i) dot H */
-+		xor_block(y, xpos);
-+		xpos += 16;
-+
-+		/* dot operation:
-+		 * multiplication operation for binary Galois (finite) field of
-+		 * 2^128 elements */
-+		gf_mult(y, h, tmp);
-+		os_memcpy(y, tmp, 16);
-+	}
-+
-+	if (x + xlen > xpos) {
-+		/* Add zero padded last block */
-+		size_t last = x + xlen - xpos;
-+		os_memcpy(tmp, xpos, last);
-+		os_memset(tmp + last, 0, sizeof(tmp) - last);
-+
-+		/* Y_i = (Y^(i-1) XOR X_i) dot H */
-+		xor_block(y, tmp);
-+
-+		/* dot operation:
-+		 * multiplication operation for binary Galois (finite) field of
-+		 * 2^128 elements */
-+		gf_mult(y, h, tmp);
-+		os_memcpy(y, tmp, 16);
-+	}
-+
-+	/* Return Y_m */
-+}
-+
-+
-+static void aes_gctr(void *aes, const u8 *icb, const u8 *x, size_t xlen, u8 *y)
-+{
-+	size_t i, n, last;
-+	u8 cb[AES_BLOCK_SIZE], tmp[AES_BLOCK_SIZE];
-+	const u8 *xpos = x;
-+	u8 *ypos = y;
-+
-+	if (xlen == 0)
-+		return;
-+
-+	n = xlen / 16;
-+
-+	os_memcpy(cb, icb, AES_BLOCK_SIZE);
-+	/* Full blocks */
-+	for (i = 0; i < n; i++) {
-+		aes_encrypt_128(aes, cb, ypos);
-+		xor_block(ypos, xpos);
-+		xpos += AES_BLOCK_SIZE;
-+		ypos += AES_BLOCK_SIZE;
-+		inc32(cb);
-+	}
-+
-+	last = x + xlen - xpos;
-+	if (last) {
-+		/* Last, partial block */
-+		aes_encrypt_128(aes, cb, tmp);
-+		for (i = 0; i < last; i++)
-+			*ypos++ = *xpos++ ^ tmp[i];
-+	}
-+}
-+
-+
-+static void * aes_gcm_init_hash_subkey(const u8 *key, size_t key_len, u8 *H)
-+{
-+	void *aes;
-+
-+	aes = aes_encrypt_init(key, key_len);
-+	if (aes == NULL)
-+		return NULL;
-+
-+	/* Generate hash subkey H = AES_K(0^128) */
-+	os_memset(H, 0, AES_BLOCK_SIZE);
-+	aes_encrypt_128(aes, H, H);
-+	wpa_hexdump_key(_MSG_EXCESSIVE_, "Hash subkey H for GHASH",
-+			H, AES_BLOCK_SIZE);
-+	return aes;
-+}
-+
-+
-+static void aes_gcm_prepare_j0(const u8 *iv, size_t iv_len, const u8 *H, u8 *J0)
-+{
-+	u8 len_buf[16];
-+
-+	if (iv_len == 12) {
-+		/* Prepare block J_0 = IV || 0^31 || 1 [len(IV) = 96] */
-+		os_memcpy(J0, iv, iv_len);
-+		os_memset(J0 + iv_len, 0, AES_BLOCK_SIZE - iv_len);
-+		J0[AES_BLOCK_SIZE - 1] = 0x01;
-+	} else {
-+		/*
-+		 * s = 128 * ceil(len(IV)/128) - len(IV)
-+		 * J_0 = GHASH_H(IV || 0^(s+64) || [len(IV)]_64)
-+		 */
-+		ghash_start(J0);
-+		ghash(H, iv, iv_len, J0);
-+		WPA_PUT_BE64(len_buf, 0);
-+		WPA_PUT_BE64(len_buf + 8, iv_len * 8);
-+		ghash(H, len_buf, sizeof(len_buf), J0);
-+	}
-+}
-+
-+
-+static void aes_gcm_gctr(void *aes, const u8 *J0, const u8 *in, size_t len,
-+			 u8 *out)
-+{
-+	u8 J0inc[AES_BLOCK_SIZE];
-+
-+	if (len == 0)
-+		return;
-+
-+	os_memcpy(J0inc, J0, AES_BLOCK_SIZE);
-+	inc32(J0inc);
-+	aes_gctr(aes, J0inc, in, len, out);
-+}
-+
-+
-+static void aes_gcm_ghash(const u8 *H, const u8 *aad, size_t aad_len,
-+			  const u8 *crypt, size_t crypt_len, u8 *S)
-+{
-+	u8 len_buf[16];
-+
-+	/*
-+	 * u = 128 * ceil[len(C)/128] - len(C)
-+	 * v = 128 * ceil[len(A)/128] - len(A)
-+	 * S = GHASH_H(A || 0^v || C || 0^u || [len(A)]64 || [len(C)]64)
-+	 * (i.e., zero padded to block size A || C and lengths of each in bits)
-+	 */
-+	ghash_start(S);
-+	ghash(H, aad, aad_len, S);
-+	ghash(H, crypt, crypt_len, S);
-+	WPA_PUT_BE64(len_buf, aad_len * 8);
-+	WPA_PUT_BE64(len_buf + 8, crypt_len * 8);
-+	ghash(H, len_buf, sizeof(len_buf), S);
-+
-+	wpa_hexdump_key(_MSG_EXCESSIVE_, "S = GHASH_H(...)", S, 16);
-+}
-+
-+
-+/**
-+ * aes_gcm_ae - GCM-AE_K(IV, P, A)
-+ */
-+int aes_gcm_ae(const u8 *key, size_t key_len, const u8 *iv, size_t iv_len,
-+	       const u8 *plain, size_t plain_len,
-+	       const u8 *aad, size_t aad_len, u8 *crypt, u8 *tag)
-+{
-+	u8 H[AES_BLOCK_SIZE];
-+	u8 J0[AES_BLOCK_SIZE];
-+	u8 S[16];
-+	void *aes;
-+
-+	aes = aes_gcm_init_hash_subkey(key, key_len, H);
-+	if (aes == NULL)
-+		return -1;
-+
-+	aes_gcm_prepare_j0(iv, iv_len, H, J0);
-+
-+	/* C = GCTR_K(inc_32(J_0), P) */
-+	aes_gcm_gctr(aes, J0, plain, plain_len, crypt);
-+
-+	aes_gcm_ghash(H, aad, aad_len, crypt, plain_len, S);
-+
-+	/* T = MSB_t(GCTR_K(J_0, S)) */
-+	aes_gctr(aes, J0, S, sizeof(S), tag);
-+
-+	/* Return (C, T) */
-+
-+	aes_encrypt_deinit(aes);
-+
-+	return 0;
-+}
-+
-+
-+/**
-+ * aes_gcm_ad - GCM-AD_K(IV, C, A, T)
-+ */
-+int aes_gcm_ad(const u8 *key, size_t key_len, const u8 *iv, size_t iv_len,
-+	       const u8 *crypt, size_t crypt_len,
-+	       const u8 *aad, size_t aad_len, const u8 *tag, u8 *plain)
-+{
-+	u8 H[AES_BLOCK_SIZE];
-+	u8 J0[AES_BLOCK_SIZE];
-+	u8 S[16], T[16];
-+	void *aes;
-+
-+	aes = aes_gcm_init_hash_subkey(key, key_len, H);
-+	if (aes == NULL)
-+		return -1;
-+
-+	aes_gcm_prepare_j0(iv, iv_len, H, J0);
-+
-+	/* P = GCTR_K(inc_32(J_0), C) */
-+	aes_gcm_gctr(aes, J0, crypt, crypt_len, plain);
-+
-+	aes_gcm_ghash(H, aad, aad_len, crypt, crypt_len, S);
-+
-+	/* T' = MSB_t(GCTR_K(J_0, S)) */
-+	aes_gctr(aes, J0, S, sizeof(S), T);
-+
-+	aes_encrypt_deinit(aes);
-+
-+	if (os_memcmp_const(tag, T, 16) != 0) {
-+		wpa_printf(_MSG_EXCESSIVE_, "GCM: Tag mismatch");
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+
-+int aes_gmac(const u8 *key, size_t key_len, const u8 *iv, size_t iv_len,
-+	     const u8 *aad, size_t aad_len, u8 *tag)
-+{
-+	return aes_gcm_ae(key, key_len, iv, iv_len, NULL, 0, aad, aad_len, NULL,
-+			  tag);
-+}
-diff --git a/drivers/staging/rtl8723cs/core/crypto/aes-internal-enc.c b/drivers/staging/rtl8723cs/core/crypto/aes-internal-enc.c
-new file mode 100644
-index 000000000000..6728363b6bf2
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/aes-internal-enc.c
-@@ -0,0 +1,129 @@
-+/*
-+ * AES (Rijndael) cipher - encrypt
-+ *
-+ * Modifications to public domain implementation:
-+ * - cleanup
-+ * - use C pre-processor to make it easier to change S table access
-+ * - added option (AES_SMALL_TABLES) for reducing code size by about 8 kB at
-+ *   cost of reduced throughput (quite small difference on Pentium 4,
-+ *   10-25% when using -O1 or -O2 optimization)
-+ *
-+ * Copyright (c) 2003-2012, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#include "rtw_crypto_wrap.h"
-+
-+#include "aes_i.h"
-+
-+static void rijndaelEncrypt(const u32 rk[], int Nr, const u8 pt[16], u8 ct[16])
-+{
-+	u32 s0, s1, s2, s3, t0, t1, t2, t3;
-+#ifndef FULL_UNROLL
-+	int r;
-+#endif /* ?FULL_UNROLL */
-+
-+	/*
-+	 * map byte array block to cipher state
-+	 * and add initial round key:
-+	 */
-+	s0 = GETU32(pt     ) ^ rk[0];
-+	s1 = GETU32(pt +  4) ^ rk[1];
-+	s2 = GETU32(pt +  8) ^ rk[2];
-+	s3 = GETU32(pt + 12) ^ rk[3];
-+
-+#define ROUND(i,d,s) \
-+d##0 = TE0(s##0) ^ TE1(s##1) ^ TE2(s##2) ^ TE3(s##3) ^ rk[4 * i]; \
-+d##1 = TE0(s##1) ^ TE1(s##2) ^ TE2(s##3) ^ TE3(s##0) ^ rk[4 * i + 1]; \
-+d##2 = TE0(s##2) ^ TE1(s##3) ^ TE2(s##0) ^ TE3(s##1) ^ rk[4 * i + 2]; \
-+d##3 = TE0(s##3) ^ TE1(s##0) ^ TE2(s##1) ^ TE3(s##2) ^ rk[4 * i + 3]
-+
-+#ifdef FULL_UNROLL
-+
-+	ROUND(1,t,s);
-+	ROUND(2,s,t);
-+	ROUND(3,t,s);
-+	ROUND(4,s,t);
-+	ROUND(5,t,s);
-+	ROUND(6,s,t);
-+	ROUND(7,t,s);
-+	ROUND(8,s,t);
-+	ROUND(9,t,s);
-+	if (Nr > 10) {
-+		ROUND(10,s,t);
-+		ROUND(11,t,s);
-+		if (Nr > 12) {
-+			ROUND(12,s,t);
-+			ROUND(13,t,s);
-+		}
-+	}
-+
-+	rk += Nr << 2;
-+
-+#else  /* !FULL_UNROLL */
-+
-+	/* Nr - 1 full rounds: */
-+	r = Nr >> 1;
-+	for (;;) {
-+		ROUND(1,t,s);
-+		rk += 8;
-+		if (--r == 0)
-+			break;
-+		ROUND(0,s,t);
-+	}
-+
-+#endif /* ?FULL_UNROLL */
-+
-+#undef ROUND
-+
-+	/*
-+	 * apply last round and
-+	 * map cipher state to byte array block:
-+	 */
-+	s0 = TE41(t0) ^ TE42(t1) ^ TE43(t2) ^ TE44(t3) ^ rk[0];
-+	PUTU32(ct     , s0);
-+	s1 = TE41(t1) ^ TE42(t2) ^ TE43(t3) ^ TE44(t0) ^ rk[1];
-+	PUTU32(ct +  4, s1);
-+	s2 = TE41(t2) ^ TE42(t3) ^ TE43(t0) ^ TE44(t1) ^ rk[2];
-+	PUTU32(ct +  8, s2);
-+	s3 = TE41(t3) ^ TE42(t0) ^ TE43(t1) ^ TE44(t2) ^ rk[3];
-+	PUTU32(ct + 12, s3);
-+}
-+
-+
-+void * aes_encrypt_init(const u8 *key, size_t len)
-+{
-+	u32 *rk;
-+	int res;
-+
-+	if (TEST_FAIL())
-+		return NULL;
-+
-+	rk = os_malloc(AES_PRIV_SIZE);
-+	if (rk == NULL)
-+		return NULL;
-+	res = rijndaelKeySetupEnc(rk, key, len * 8);
-+	if (res < 0) {
-+		rtw_mfree(rk, AES_PRIV_SIZE);
-+		return NULL;
-+	}
-+	rk[AES_PRIV_NR_POS] = res;
-+	return rk;
-+}
-+
-+
-+int aes_encrypt_128(void *ctx, const u8 *plain, u8 *crypt)
-+{
-+	u32 *rk = ctx;
-+	rijndaelEncrypt(ctx, rk[AES_PRIV_NR_POS], plain, crypt);
-+	return 0;
-+}
-+
-+
-+void aes_encrypt_deinit(void *ctx)
-+{
-+	os_memset(ctx, 0, AES_PRIV_SIZE);
-+	rtw_mfree(ctx, AES_PRIV_SIZE);
-+}
-diff --git a/drivers/staging/rtl8723cs/core/crypto/aes-internal.c b/drivers/staging/rtl8723cs/core/crypto/aes-internal.c
-new file mode 100644
-index 000000000000..57d653949991
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/aes-internal.c
-@@ -0,0 +1,843 @@
-+/*
-+ * AES (Rijndael) cipher
-+ *
-+ * Modifications to public domain implementation:
-+ * - cleanup
-+ * - use C pre-processor to make it easier to change S table access
-+ * - added option (AES_SMALL_TABLES) for reducing code size by about 8 kB at
-+ *   cost of reduced throughput (quite small difference on Pentium 4,
-+ *   10-25% when using -O1 or -O2 optimization)
-+ *
-+ * Copyright (c) 2003-2012, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#include "rtw_crypto_wrap.h"
-+
-+#include "aes_i.h"
-+
-+/*
-+ * rijndael-alg-fst.c
-+ *
-+ * @version 3.0 (December 2000)
-+ *
-+ * Optimised ANSI C code for the Rijndael cipher (now AES)
-+ *
-+ * @author Vincent Rijmen <vincent.rijmen@esat.kuleuven.ac.be>
-+ * @author Antoon Bosselaers <antoon.bosselaers@esat.kuleuven.ac.be>
-+ * @author Paulo Barreto <paulo.barreto@terra.com.br>
-+ *
-+ * This code is hereby placed in the public domain.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ''AS IS'' AND ANY EXPRESS
-+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+
-+/*
-+Te0[x] = S [x].[02, 01, 01, 03];
-+Te1[x] = S [x].[03, 02, 01, 01];
-+Te2[x] = S [x].[01, 03, 02, 01];
-+Te3[x] = S [x].[01, 01, 03, 02];
-+Te4[x] = S [x].[01, 01, 01, 01];
-+
-+Td0[x] = Si[x].[0e, 09, 0d, 0b];
-+Td1[x] = Si[x].[0b, 0e, 09, 0d];
-+Td2[x] = Si[x].[0d, 0b, 0e, 09];
-+Td3[x] = Si[x].[09, 0d, 0b, 0e];
-+Td4[x] = Si[x].[01, 01, 01, 01];
-+*/
-+
-+const u32 Te0[256] = {
-+    0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU,
-+    0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U,
-+    0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU,
-+    0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U, 0xec76769aU,
-+    0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U,
-+    0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU,
-+    0x41adadecU, 0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU,
-+    0x239c9cbfU, 0x53a4a4f7U, 0xe4727296U, 0x9bc0c05bU,
-+    0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU, 0x4c26266aU,
-+    0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU,
-+    0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U,
-+    0xe2717193U, 0xabd8d873U, 0x62313153U, 0x2a15153fU,
-+    0x0804040cU, 0x95c7c752U, 0x46232365U, 0x9dc3c35eU,
-+    0x30181828U, 0x379696a1U, 0x0a05050fU, 0x2f9a9ab5U,
-+    0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU,
-+    0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU,
-+    0x1209091bU, 0x1d83839eU, 0x582c2c74U, 0x341a1a2eU,
-+    0x361b1b2dU, 0xdc6e6eb2U, 0xb45a5aeeU, 0x5ba0a0fbU,
-+    0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U, 0x7db3b3ceU,
-+    0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U,
-+    0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU,
-+    0x40202060U, 0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU,
-+    0xd46a6abeU, 0x8dcbcb46U, 0x67bebed9U, 0x7239394bU,
-+    0x944a4adeU, 0x984c4cd4U, 0xb05858e8U, 0x85cfcf4aU,
-+    0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U,
-+    0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U,
-+    0x8a4545cfU, 0xe9f9f910U, 0x04020206U, 0xfe7f7f81U,
-+    0xa05050f0U, 0x783c3c44U, 0x259f9fbaU, 0x4ba8a8e3U,
-+    0xa25151f3U, 0x5da3a3feU, 0x804040c0U, 0x058f8f8aU,
-+    0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U,
-+    0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U,
-+    0x20101030U, 0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU,
-+    0x81cdcd4cU, 0x180c0c14U, 0x26131335U, 0xc3ecec2fU,
-+    0xbe5f5fe1U, 0x359797a2U, 0x884444ccU, 0x2e171739U,
-+    0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U,
-+    0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U,
-+    0xc06060a0U, 0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU,
-+    0x44222266U, 0x542a2a7eU, 0x3b9090abU, 0x0b888883U,
-+    0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U, 0x2814143cU,
-+    0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U,
-+    0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU,
-+    0x924949dbU, 0x0c06060aU, 0x4824246cU, 0xb85c5ce4U,
-+    0x9fc2c25dU, 0xbdd3d36eU, 0x43acacefU, 0xc46262a6U,
-+    0x399191a8U, 0x319595a4U, 0xd3e4e437U, 0xf279798bU,
-+    0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U,
-+    0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U,
-+    0xd86c6cb4U, 0xac5656faU, 0xf3f4f407U, 0xcfeaea25U,
-+    0xca6565afU, 0xf47a7a8eU, 0x47aeaee9U, 0x10080818U,
-+    0x6fbabad5U, 0xf0787888U, 0x4a25256fU, 0x5c2e2e72U,
-+    0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U,
-+    0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U,
-+    0x964b4bddU, 0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U,
-+    0xe0707090U, 0x7c3e3e42U, 0x71b5b5c4U, 0xcc6666aaU,
-+    0x904848d8U, 0x06030305U, 0xf7f6f601U, 0x1c0e0e12U,
-+    0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U,
-+    0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U,
-+    0xd9e1e138U, 0xebf8f813U, 0x2b9898b3U, 0x22111133U,
-+    0xd26969bbU, 0xa9d9d970U, 0x078e8e89U, 0x339494a7U,
-+    0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U, 0xc9e9e920U,
-+    0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU,
-+    0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U,
-+    0x65bfbfdaU, 0xd7e6e631U, 0x844242c6U, 0xd06868b8U,
-+    0x824141c3U, 0x299999b0U, 0x5a2d2d77U, 0x1e0f0f11U,
-+    0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U, 0x2c16163aU,
-+};
-+#ifndef AES_SMALL_TABLES
-+const u32 Te1[256] = {
-+    0xa5c66363U, 0x84f87c7cU, 0x99ee7777U, 0x8df67b7bU,
-+    0x0dfff2f2U, 0xbdd66b6bU, 0xb1de6f6fU, 0x5491c5c5U,
-+    0x50603030U, 0x03020101U, 0xa9ce6767U, 0x7d562b2bU,
-+    0x19e7fefeU, 0x62b5d7d7U, 0xe64dababU, 0x9aec7676U,
-+    0x458fcacaU, 0x9d1f8282U, 0x4089c9c9U, 0x87fa7d7dU,
-+    0x15effafaU, 0xebb25959U, 0xc98e4747U, 0x0bfbf0f0U,
-+    0xec41adadU, 0x67b3d4d4U, 0xfd5fa2a2U, 0xea45afafU,
-+    0xbf239c9cU, 0xf753a4a4U, 0x96e47272U, 0x5b9bc0c0U,
-+    0xc275b7b7U, 0x1ce1fdfdU, 0xae3d9393U, 0x6a4c2626U,
-+    0x5a6c3636U, 0x417e3f3fU, 0x02f5f7f7U, 0x4f83ccccU,
-+    0x5c683434U, 0xf451a5a5U, 0x34d1e5e5U, 0x08f9f1f1U,
-+    0x93e27171U, 0x73abd8d8U, 0x53623131U, 0x3f2a1515U,
-+    0x0c080404U, 0x5295c7c7U, 0x65462323U, 0x5e9dc3c3U,
-+    0x28301818U, 0xa1379696U, 0x0f0a0505U, 0xb52f9a9aU,
-+    0x090e0707U, 0x36241212U, 0x9b1b8080U, 0x3ddfe2e2U,
-+    0x26cdebebU, 0x694e2727U, 0xcd7fb2b2U, 0x9fea7575U,
-+    0x1b120909U, 0x9e1d8383U, 0x74582c2cU, 0x2e341a1aU,
-+    0x2d361b1bU, 0xb2dc6e6eU, 0xeeb45a5aU, 0xfb5ba0a0U,
-+    0xf6a45252U, 0x4d763b3bU, 0x61b7d6d6U, 0xce7db3b3U,
-+    0x7b522929U, 0x3edde3e3U, 0x715e2f2fU, 0x97138484U,
-+    0xf5a65353U, 0x68b9d1d1U, 0x00000000U, 0x2cc1ededU,
-+    0x60402020U, 0x1fe3fcfcU, 0xc879b1b1U, 0xedb65b5bU,
-+    0xbed46a6aU, 0x468dcbcbU, 0xd967bebeU, 0x4b723939U,
-+    0xde944a4aU, 0xd4984c4cU, 0xe8b05858U, 0x4a85cfcfU,
-+    0x6bbbd0d0U, 0x2ac5efefU, 0xe54faaaaU, 0x16edfbfbU,
-+    0xc5864343U, 0xd79a4d4dU, 0x55663333U, 0x94118585U,
-+    0xcf8a4545U, 0x10e9f9f9U, 0x06040202U, 0x81fe7f7fU,
-+    0xf0a05050U, 0x44783c3cU, 0xba259f9fU, 0xe34ba8a8U,
-+    0xf3a25151U, 0xfe5da3a3U, 0xc0804040U, 0x8a058f8fU,
-+    0xad3f9292U, 0xbc219d9dU, 0x48703838U, 0x04f1f5f5U,
-+    0xdf63bcbcU, 0xc177b6b6U, 0x75afdadaU, 0x63422121U,
-+    0x30201010U, 0x1ae5ffffU, 0x0efdf3f3U, 0x6dbfd2d2U,
-+    0x4c81cdcdU, 0x14180c0cU, 0x35261313U, 0x2fc3ececU,
-+    0xe1be5f5fU, 0xa2359797U, 0xcc884444U, 0x392e1717U,
-+    0x5793c4c4U, 0xf255a7a7U, 0x82fc7e7eU, 0x477a3d3dU,
-+    0xacc86464U, 0xe7ba5d5dU, 0x2b321919U, 0x95e67373U,
-+    0xa0c06060U, 0x98198181U, 0xd19e4f4fU, 0x7fa3dcdcU,
-+    0x66442222U, 0x7e542a2aU, 0xab3b9090U, 0x830b8888U,
-+    0xca8c4646U, 0x29c7eeeeU, 0xd36bb8b8U, 0x3c281414U,
-+    0x79a7dedeU, 0xe2bc5e5eU, 0x1d160b0bU, 0x76addbdbU,
-+    0x3bdbe0e0U, 0x56643232U, 0x4e743a3aU, 0x1e140a0aU,
-+    0xdb924949U, 0x0a0c0606U, 0x6c482424U, 0xe4b85c5cU,
-+    0x5d9fc2c2U, 0x6ebdd3d3U, 0xef43acacU, 0xa6c46262U,
-+    0xa8399191U, 0xa4319595U, 0x37d3e4e4U, 0x8bf27979U,
-+    0x32d5e7e7U, 0x438bc8c8U, 0x596e3737U, 0xb7da6d6dU,
-+    0x8c018d8dU, 0x64b1d5d5U, 0xd29c4e4eU, 0xe049a9a9U,
-+    0xb4d86c6cU, 0xfaac5656U, 0x07f3f4f4U, 0x25cfeaeaU,
-+    0xafca6565U, 0x8ef47a7aU, 0xe947aeaeU, 0x18100808U,
-+    0xd56fbabaU, 0x88f07878U, 0x6f4a2525U, 0x725c2e2eU,
-+    0x24381c1cU, 0xf157a6a6U, 0xc773b4b4U, 0x5197c6c6U,
-+    0x23cbe8e8U, 0x7ca1ddddU, 0x9ce87474U, 0x213e1f1fU,
-+    0xdd964b4bU, 0xdc61bdbdU, 0x860d8b8bU, 0x850f8a8aU,
-+    0x90e07070U, 0x427c3e3eU, 0xc471b5b5U, 0xaacc6666U,
-+    0xd8904848U, 0x05060303U, 0x01f7f6f6U, 0x121c0e0eU,
-+    0xa3c26161U, 0x5f6a3535U, 0xf9ae5757U, 0xd069b9b9U,
-+    0x91178686U, 0x5899c1c1U, 0x273a1d1dU, 0xb9279e9eU,
-+    0x38d9e1e1U, 0x13ebf8f8U, 0xb32b9898U, 0x33221111U,
-+    0xbbd26969U, 0x70a9d9d9U, 0x89078e8eU, 0xa7339494U,
-+    0xb62d9b9bU, 0x223c1e1eU, 0x92158787U, 0x20c9e9e9U,
-+    0x4987ceceU, 0xffaa5555U, 0x78502828U, 0x7aa5dfdfU,
-+    0x8f038c8cU, 0xf859a1a1U, 0x80098989U, 0x171a0d0dU,
-+    0xda65bfbfU, 0x31d7e6e6U, 0xc6844242U, 0xb8d06868U,
-+    0xc3824141U, 0xb0299999U, 0x775a2d2dU, 0x111e0f0fU,
-+    0xcb7bb0b0U, 0xfca85454U, 0xd66dbbbbU, 0x3a2c1616U,
-+};
-+const u32 Te2[256] = {
-+    0x63a5c663U, 0x7c84f87cU, 0x7799ee77U, 0x7b8df67bU,
-+    0xf20dfff2U, 0x6bbdd66bU, 0x6fb1de6fU, 0xc55491c5U,
-+    0x30506030U, 0x01030201U, 0x67a9ce67U, 0x2b7d562bU,
-+    0xfe19e7feU, 0xd762b5d7U, 0xabe64dabU, 0x769aec76U,
-+    0xca458fcaU, 0x829d1f82U, 0xc94089c9U, 0x7d87fa7dU,
-+    0xfa15effaU, 0x59ebb259U, 0x47c98e47U, 0xf00bfbf0U,
-+    0xadec41adU, 0xd467b3d4U, 0xa2fd5fa2U, 0xafea45afU,
-+    0x9cbf239cU, 0xa4f753a4U, 0x7296e472U, 0xc05b9bc0U,
-+    0xb7c275b7U, 0xfd1ce1fdU, 0x93ae3d93U, 0x266a4c26U,
-+    0x365a6c36U, 0x3f417e3fU, 0xf702f5f7U, 0xcc4f83ccU,
-+    0x345c6834U, 0xa5f451a5U, 0xe534d1e5U, 0xf108f9f1U,
-+    0x7193e271U, 0xd873abd8U, 0x31536231U, 0x153f2a15U,
-+    0x040c0804U, 0xc75295c7U, 0x23654623U, 0xc35e9dc3U,
-+    0x18283018U, 0x96a13796U, 0x050f0a05U, 0x9ab52f9aU,
-+    0x07090e07U, 0x12362412U, 0x809b1b80U, 0xe23ddfe2U,
-+    0xeb26cdebU, 0x27694e27U, 0xb2cd7fb2U, 0x759fea75U,
-+    0x091b1209U, 0x839e1d83U, 0x2c74582cU, 0x1a2e341aU,
-+    0x1b2d361bU, 0x6eb2dc6eU, 0x5aeeb45aU, 0xa0fb5ba0U,
-+    0x52f6a452U, 0x3b4d763bU, 0xd661b7d6U, 0xb3ce7db3U,
-+    0x297b5229U, 0xe33edde3U, 0x2f715e2fU, 0x84971384U,
-+    0x53f5a653U, 0xd168b9d1U, 0x00000000U, 0xed2cc1edU,
-+    0x20604020U, 0xfc1fe3fcU, 0xb1c879b1U, 0x5bedb65bU,
-+    0x6abed46aU, 0xcb468dcbU, 0xbed967beU, 0x394b7239U,
-+    0x4ade944aU, 0x4cd4984cU, 0x58e8b058U, 0xcf4a85cfU,
-+    0xd06bbbd0U, 0xef2ac5efU, 0xaae54faaU, 0xfb16edfbU,
-+    0x43c58643U, 0x4dd79a4dU, 0x33556633U, 0x85941185U,
-+    0x45cf8a45U, 0xf910e9f9U, 0x02060402U, 0x7f81fe7fU,
-+    0x50f0a050U, 0x3c44783cU, 0x9fba259fU, 0xa8e34ba8U,
-+    0x51f3a251U, 0xa3fe5da3U, 0x40c08040U, 0x8f8a058fU,
-+    0x92ad3f92U, 0x9dbc219dU, 0x38487038U, 0xf504f1f5U,
-+    0xbcdf63bcU, 0xb6c177b6U, 0xda75afdaU, 0x21634221U,
-+    0x10302010U, 0xff1ae5ffU, 0xf30efdf3U, 0xd26dbfd2U,
-+    0xcd4c81cdU, 0x0c14180cU, 0x13352613U, 0xec2fc3ecU,
-+    0x5fe1be5fU, 0x97a23597U, 0x44cc8844U, 0x17392e17U,
-+    0xc45793c4U, 0xa7f255a7U, 0x7e82fc7eU, 0x3d477a3dU,
-+    0x64acc864U, 0x5de7ba5dU, 0x192b3219U, 0x7395e673U,
-+    0x60a0c060U, 0x81981981U, 0x4fd19e4fU, 0xdc7fa3dcU,
-+    0x22664422U, 0x2a7e542aU, 0x90ab3b90U, 0x88830b88U,
-+    0x46ca8c46U, 0xee29c7eeU, 0xb8d36bb8U, 0x143c2814U,
-+    0xde79a7deU, 0x5ee2bc5eU, 0x0b1d160bU, 0xdb76addbU,
-+    0xe03bdbe0U, 0x32566432U, 0x3a4e743aU, 0x0a1e140aU,
-+    0x49db9249U, 0x060a0c06U, 0x246c4824U, 0x5ce4b85cU,
-+    0xc25d9fc2U, 0xd36ebdd3U, 0xacef43acU, 0x62a6c462U,
-+    0x91a83991U, 0x95a43195U, 0xe437d3e4U, 0x798bf279U,
-+    0xe732d5e7U, 0xc8438bc8U, 0x37596e37U, 0x6db7da6dU,
-+    0x8d8c018dU, 0xd564b1d5U, 0x4ed29c4eU, 0xa9e049a9U,
-+    0x6cb4d86cU, 0x56faac56U, 0xf407f3f4U, 0xea25cfeaU,
-+    0x65afca65U, 0x7a8ef47aU, 0xaee947aeU, 0x08181008U,
-+    0xbad56fbaU, 0x7888f078U, 0x256f4a25U, 0x2e725c2eU,
-+    0x1c24381cU, 0xa6f157a6U, 0xb4c773b4U, 0xc65197c6U,
-+    0xe823cbe8U, 0xdd7ca1ddU, 0x749ce874U, 0x1f213e1fU,
-+    0x4bdd964bU, 0xbddc61bdU, 0x8b860d8bU, 0x8a850f8aU,
-+    0x7090e070U, 0x3e427c3eU, 0xb5c471b5U, 0x66aacc66U,
-+    0x48d89048U, 0x03050603U, 0xf601f7f6U, 0x0e121c0eU,
-+    0x61a3c261U, 0x355f6a35U, 0x57f9ae57U, 0xb9d069b9U,
-+    0x86911786U, 0xc15899c1U, 0x1d273a1dU, 0x9eb9279eU,
-+    0xe138d9e1U, 0xf813ebf8U, 0x98b32b98U, 0x11332211U,
-+    0x69bbd269U, 0xd970a9d9U, 0x8e89078eU, 0x94a73394U,
-+    0x9bb62d9bU, 0x1e223c1eU, 0x87921587U, 0xe920c9e9U,
-+    0xce4987ceU, 0x55ffaa55U, 0x28785028U, 0xdf7aa5dfU,
-+    0x8c8f038cU, 0xa1f859a1U, 0x89800989U, 0x0d171a0dU,
-+    0xbfda65bfU, 0xe631d7e6U, 0x42c68442U, 0x68b8d068U,
-+    0x41c38241U, 0x99b02999U, 0x2d775a2dU, 0x0f111e0fU,
-+    0xb0cb7bb0U, 0x54fca854U, 0xbbd66dbbU, 0x163a2c16U,
-+};
-+const u32 Te3[256] = {
-+
-+    0x6363a5c6U, 0x7c7c84f8U, 0x777799eeU, 0x7b7b8df6U,
-+    0xf2f20dffU, 0x6b6bbdd6U, 0x6f6fb1deU, 0xc5c55491U,
-+    0x30305060U, 0x01010302U, 0x6767a9ceU, 0x2b2b7d56U,
-+    0xfefe19e7U, 0xd7d762b5U, 0xababe64dU, 0x76769aecU,
-+    0xcaca458fU, 0x82829d1fU, 0xc9c94089U, 0x7d7d87faU,
-+    0xfafa15efU, 0x5959ebb2U, 0x4747c98eU, 0xf0f00bfbU,
-+    0xadadec41U, 0xd4d467b3U, 0xa2a2fd5fU, 0xafafea45U,
-+    0x9c9cbf23U, 0xa4a4f753U, 0x727296e4U, 0xc0c05b9bU,
-+    0xb7b7c275U, 0xfdfd1ce1U, 0x9393ae3dU, 0x26266a4cU,
-+    0x36365a6cU, 0x3f3f417eU, 0xf7f702f5U, 0xcccc4f83U,
-+    0x34345c68U, 0xa5a5f451U, 0xe5e534d1U, 0xf1f108f9U,
-+    0x717193e2U, 0xd8d873abU, 0x31315362U, 0x15153f2aU,
-+    0x04040c08U, 0xc7c75295U, 0x23236546U, 0xc3c35e9dU,
-+    0x18182830U, 0x9696a137U, 0x05050f0aU, 0x9a9ab52fU,
-+    0x0707090eU, 0x12123624U, 0x80809b1bU, 0xe2e23ddfU,
-+    0xebeb26cdU, 0x2727694eU, 0xb2b2cd7fU, 0x75759feaU,
-+    0x09091b12U, 0x83839e1dU, 0x2c2c7458U, 0x1a1a2e34U,
-+    0x1b1b2d36U, 0x6e6eb2dcU, 0x5a5aeeb4U, 0xa0a0fb5bU,
-+    0x5252f6a4U, 0x3b3b4d76U, 0xd6d661b7U, 0xb3b3ce7dU,
-+    0x29297b52U, 0xe3e33eddU, 0x2f2f715eU, 0x84849713U,
-+    0x5353f5a6U, 0xd1d168b9U, 0x00000000U, 0xeded2cc1U,
-+    0x20206040U, 0xfcfc1fe3U, 0xb1b1c879U, 0x5b5bedb6U,
-+    0x6a6abed4U, 0xcbcb468dU, 0xbebed967U, 0x39394b72U,
-+    0x4a4ade94U, 0x4c4cd498U, 0x5858e8b0U, 0xcfcf4a85U,
-+    0xd0d06bbbU, 0xefef2ac5U, 0xaaaae54fU, 0xfbfb16edU,
-+    0x4343c586U, 0x4d4dd79aU, 0x33335566U, 0x85859411U,
-+    0x4545cf8aU, 0xf9f910e9U, 0x02020604U, 0x7f7f81feU,
-+    0x5050f0a0U, 0x3c3c4478U, 0x9f9fba25U, 0xa8a8e34bU,
-+    0x5151f3a2U, 0xa3a3fe5dU, 0x4040c080U, 0x8f8f8a05U,
-+    0x9292ad3fU, 0x9d9dbc21U, 0x38384870U, 0xf5f504f1U,
-+    0xbcbcdf63U, 0xb6b6c177U, 0xdada75afU, 0x21216342U,
-+    0x10103020U, 0xffff1ae5U, 0xf3f30efdU, 0xd2d26dbfU,
-+    0xcdcd4c81U, 0x0c0c1418U, 0x13133526U, 0xecec2fc3U,
-+    0x5f5fe1beU, 0x9797a235U, 0x4444cc88U, 0x1717392eU,
-+    0xc4c45793U, 0xa7a7f255U, 0x7e7e82fcU, 0x3d3d477aU,
-+    0x6464acc8U, 0x5d5de7baU, 0x19192b32U, 0x737395e6U,
-+    0x6060a0c0U, 0x81819819U, 0x4f4fd19eU, 0xdcdc7fa3U,
-+    0x22226644U, 0x2a2a7e54U, 0x9090ab3bU, 0x8888830bU,
-+    0x4646ca8cU, 0xeeee29c7U, 0xb8b8d36bU, 0x14143c28U,
-+    0xdede79a7U, 0x5e5ee2bcU, 0x0b0b1d16U, 0xdbdb76adU,
-+    0xe0e03bdbU, 0x32325664U, 0x3a3a4e74U, 0x0a0a1e14U,
-+    0x4949db92U, 0x06060a0cU, 0x24246c48U, 0x5c5ce4b8U,
-+    0xc2c25d9fU, 0xd3d36ebdU, 0xacacef43U, 0x6262a6c4U,
-+    0x9191a839U, 0x9595a431U, 0xe4e437d3U, 0x79798bf2U,
-+    0xe7e732d5U, 0xc8c8438bU, 0x3737596eU, 0x6d6db7daU,
-+    0x8d8d8c01U, 0xd5d564b1U, 0x4e4ed29cU, 0xa9a9e049U,
-+    0x6c6cb4d8U, 0x5656faacU, 0xf4f407f3U, 0xeaea25cfU,
-+    0x6565afcaU, 0x7a7a8ef4U, 0xaeaee947U, 0x08081810U,
-+    0xbabad56fU, 0x787888f0U, 0x25256f4aU, 0x2e2e725cU,
-+    0x1c1c2438U, 0xa6a6f157U, 0xb4b4c773U, 0xc6c65197U,
-+    0xe8e823cbU, 0xdddd7ca1U, 0x74749ce8U, 0x1f1f213eU,
-+    0x4b4bdd96U, 0xbdbddc61U, 0x8b8b860dU, 0x8a8a850fU,
-+    0x707090e0U, 0x3e3e427cU, 0xb5b5c471U, 0x6666aaccU,
-+    0x4848d890U, 0x03030506U, 0xf6f601f7U, 0x0e0e121cU,
-+    0x6161a3c2U, 0x35355f6aU, 0x5757f9aeU, 0xb9b9d069U,
-+    0x86869117U, 0xc1c15899U, 0x1d1d273aU, 0x9e9eb927U,
-+    0xe1e138d9U, 0xf8f813ebU, 0x9898b32bU, 0x11113322U,
-+    0x6969bbd2U, 0xd9d970a9U, 0x8e8e8907U, 0x9494a733U,
-+    0x9b9bb62dU, 0x1e1e223cU, 0x87879215U, 0xe9e920c9U,
-+    0xcece4987U, 0x5555ffaaU, 0x28287850U, 0xdfdf7aa5U,
-+    0x8c8c8f03U, 0xa1a1f859U, 0x89898009U, 0x0d0d171aU,
-+    0xbfbfda65U, 0xe6e631d7U, 0x4242c684U, 0x6868b8d0U,
-+    0x4141c382U, 0x9999b029U, 0x2d2d775aU, 0x0f0f111eU,
-+    0xb0b0cb7bU, 0x5454fca8U, 0xbbbbd66dU, 0x16163a2cU,
-+};
-+const u32 Te4[256] = {
-+    0x63636363U, 0x7c7c7c7cU, 0x77777777U, 0x7b7b7b7bU,
-+    0xf2f2f2f2U, 0x6b6b6b6bU, 0x6f6f6f6fU, 0xc5c5c5c5U,
-+    0x30303030U, 0x01010101U, 0x67676767U, 0x2b2b2b2bU,
-+    0xfefefefeU, 0xd7d7d7d7U, 0xababababU, 0x76767676U,
-+    0xcacacacaU, 0x82828282U, 0xc9c9c9c9U, 0x7d7d7d7dU,
-+    0xfafafafaU, 0x59595959U, 0x47474747U, 0xf0f0f0f0U,
-+    0xadadadadU, 0xd4d4d4d4U, 0xa2a2a2a2U, 0xafafafafU,
-+    0x9c9c9c9cU, 0xa4a4a4a4U, 0x72727272U, 0xc0c0c0c0U,
-+    0xb7b7b7b7U, 0xfdfdfdfdU, 0x93939393U, 0x26262626U,
-+    0x36363636U, 0x3f3f3f3fU, 0xf7f7f7f7U, 0xccccccccU,
-+    0x34343434U, 0xa5a5a5a5U, 0xe5e5e5e5U, 0xf1f1f1f1U,
-+    0x71717171U, 0xd8d8d8d8U, 0x31313131U, 0x15151515U,
-+    0x04040404U, 0xc7c7c7c7U, 0x23232323U, 0xc3c3c3c3U,
-+    0x18181818U, 0x96969696U, 0x05050505U, 0x9a9a9a9aU,
-+    0x07070707U, 0x12121212U, 0x80808080U, 0xe2e2e2e2U,
-+    0xebebebebU, 0x27272727U, 0xb2b2b2b2U, 0x75757575U,
-+    0x09090909U, 0x83838383U, 0x2c2c2c2cU, 0x1a1a1a1aU,
-+    0x1b1b1b1bU, 0x6e6e6e6eU, 0x5a5a5a5aU, 0xa0a0a0a0U,
-+    0x52525252U, 0x3b3b3b3bU, 0xd6d6d6d6U, 0xb3b3b3b3U,
-+    0x29292929U, 0xe3e3e3e3U, 0x2f2f2f2fU, 0x84848484U,
-+    0x53535353U, 0xd1d1d1d1U, 0x00000000U, 0xededededU,
-+    0x20202020U, 0xfcfcfcfcU, 0xb1b1b1b1U, 0x5b5b5b5bU,
-+    0x6a6a6a6aU, 0xcbcbcbcbU, 0xbebebebeU, 0x39393939U,
-+    0x4a4a4a4aU, 0x4c4c4c4cU, 0x58585858U, 0xcfcfcfcfU,
-+    0xd0d0d0d0U, 0xefefefefU, 0xaaaaaaaaU, 0xfbfbfbfbU,
-+    0x43434343U, 0x4d4d4d4dU, 0x33333333U, 0x85858585U,
-+    0x45454545U, 0xf9f9f9f9U, 0x02020202U, 0x7f7f7f7fU,
-+    0x50505050U, 0x3c3c3c3cU, 0x9f9f9f9fU, 0xa8a8a8a8U,
-+    0x51515151U, 0xa3a3a3a3U, 0x40404040U, 0x8f8f8f8fU,
-+    0x92929292U, 0x9d9d9d9dU, 0x38383838U, 0xf5f5f5f5U,
-+    0xbcbcbcbcU, 0xb6b6b6b6U, 0xdadadadaU, 0x21212121U,
-+    0x10101010U, 0xffffffffU, 0xf3f3f3f3U, 0xd2d2d2d2U,
-+    0xcdcdcdcdU, 0x0c0c0c0cU, 0x13131313U, 0xececececU,
-+    0x5f5f5f5fU, 0x97979797U, 0x44444444U, 0x17171717U,
-+    0xc4c4c4c4U, 0xa7a7a7a7U, 0x7e7e7e7eU, 0x3d3d3d3dU,
-+    0x64646464U, 0x5d5d5d5dU, 0x19191919U, 0x73737373U,
-+    0x60606060U, 0x81818181U, 0x4f4f4f4fU, 0xdcdcdcdcU,
-+    0x22222222U, 0x2a2a2a2aU, 0x90909090U, 0x88888888U,
-+    0x46464646U, 0xeeeeeeeeU, 0xb8b8b8b8U, 0x14141414U,
-+    0xdedededeU, 0x5e5e5e5eU, 0x0b0b0b0bU, 0xdbdbdbdbU,
-+    0xe0e0e0e0U, 0x32323232U, 0x3a3a3a3aU, 0x0a0a0a0aU,
-+    0x49494949U, 0x06060606U, 0x24242424U, 0x5c5c5c5cU,
-+    0xc2c2c2c2U, 0xd3d3d3d3U, 0xacacacacU, 0x62626262U,
-+    0x91919191U, 0x95959595U, 0xe4e4e4e4U, 0x79797979U,
-+    0xe7e7e7e7U, 0xc8c8c8c8U, 0x37373737U, 0x6d6d6d6dU,
-+    0x8d8d8d8dU, 0xd5d5d5d5U, 0x4e4e4e4eU, 0xa9a9a9a9U,
-+    0x6c6c6c6cU, 0x56565656U, 0xf4f4f4f4U, 0xeaeaeaeaU,
-+    0x65656565U, 0x7a7a7a7aU, 0xaeaeaeaeU, 0x08080808U,
-+    0xbabababaU, 0x78787878U, 0x25252525U, 0x2e2e2e2eU,
-+    0x1c1c1c1cU, 0xa6a6a6a6U, 0xb4b4b4b4U, 0xc6c6c6c6U,
-+    0xe8e8e8e8U, 0xddddddddU, 0x74747474U, 0x1f1f1f1fU,
-+    0x4b4b4b4bU, 0xbdbdbdbdU, 0x8b8b8b8bU, 0x8a8a8a8aU,
-+    0x70707070U, 0x3e3e3e3eU, 0xb5b5b5b5U, 0x66666666U,
-+    0x48484848U, 0x03030303U, 0xf6f6f6f6U, 0x0e0e0e0eU,
-+    0x61616161U, 0x35353535U, 0x57575757U, 0xb9b9b9b9U,
-+    0x86868686U, 0xc1c1c1c1U, 0x1d1d1d1dU, 0x9e9e9e9eU,
-+    0xe1e1e1e1U, 0xf8f8f8f8U, 0x98989898U, 0x11111111U,
-+    0x69696969U, 0xd9d9d9d9U, 0x8e8e8e8eU, 0x94949494U,
-+    0x9b9b9b9bU, 0x1e1e1e1eU, 0x87878787U, 0xe9e9e9e9U,
-+    0xcecececeU, 0x55555555U, 0x28282828U, 0xdfdfdfdfU,
-+    0x8c8c8c8cU, 0xa1a1a1a1U, 0x89898989U, 0x0d0d0d0dU,
-+    0xbfbfbfbfU, 0xe6e6e6e6U, 0x42424242U, 0x68686868U,
-+    0x41414141U, 0x99999999U, 0x2d2d2d2dU, 0x0f0f0f0fU,
-+    0xb0b0b0b0U, 0x54545454U, 0xbbbbbbbbU, 0x16161616U,
-+};
-+#endif /* AES_SMALL_TABLES */
-+const u32 Td0[256] = {
-+    0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U,
-+    0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U,
-+    0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U,
-+    0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U, 0xb562a38fU,
-+    0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U,
-+    0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U,
-+    0x038f5fe7U, 0x15929c95U, 0xbf6d7aebU, 0x955259daU,
-+    0xd4be832dU, 0x587421d3U, 0x49e06929U, 0x8ec9c844U,
-+    0x75c2896aU, 0xf48e7978U, 0x99583e6bU, 0x27b971ddU,
-+    0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U,
-+    0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U,
-+    0xb16477e0U, 0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U,
-+    0x70486858U, 0x8f45fd19U, 0x94de6c87U, 0x527bf8b7U,
-+    0xab73d323U, 0x724b02e2U, 0xe31f8f57U, 0x6655ab2aU,
-+    0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U,
-+    0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU,
-+    0x8acf1c2bU, 0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U,
-+    0x65daf4cdU, 0x0605bed5U, 0xd134621fU, 0xc4a6fe8aU,
-+    0x342e539dU, 0xa2f355a0U, 0x058ae132U, 0xa4f6eb75U,
-+    0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U,
-+    0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U,
-+    0x91548db5U, 0x71c45d05U, 0x0406d46fU, 0x605015ffU,
-+    0x1998fb24U, 0xd6bde997U, 0x894043ccU, 0x67d99e77U,
-+    0xb0e842bdU, 0x07898b88U, 0xe7195b38U, 0x79c8eedbU,
-+    0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U,
-+    0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU,
-+    0xfd0efffbU, 0x0f853856U, 0x3daed51eU, 0x362d3927U,
-+    0x0a0fd964U, 0x685ca621U, 0x9b5b54d1U, 0x24362e3aU,
-+    0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U, 0x1b9b919eU,
-+    0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U,
-+    0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU,
-+    0x0e090d0bU, 0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U,
-+    0x57f11985U, 0xaf75074cU, 0xee99ddbbU, 0xa37f60fdU,
-+    0xf701269fU, 0x5c72f5bcU, 0x44663bc5U, 0x5bfb7e34U,
-+    0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U,
-+    0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U,
-+    0x854a247dU, 0xd2bb3df8U, 0xaef93211U, 0xc729a16dU,
-+    0x1d9e2f4bU, 0xdcb230f3U, 0x0d8652ecU, 0x77c1e3d0U,
-+    0x2bb3166cU, 0xa970b999U, 0x119448faU, 0x47e96422U,
-+    0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU,
-+    0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U,
-+    0xa6f581cfU, 0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U,
-+    0x2c3a9de4U, 0x5078920dU, 0x6a5fcc9bU, 0x547e4662U,
-+    0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU, 0x82c3aff5U,
-+    0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U,
-+    0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU,
-+    0xcd267809U, 0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U,
-+    0xe6956e65U, 0xaaffe67eU, 0x21bccf08U, 0xef15e8e6U,
-+    0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U, 0x29b07cd6U,
-+    0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U,
-+    0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U,
-+    0xf104984aU, 0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU,
-+    0x764dd68dU, 0x43efb04dU, 0xccaa4d54U, 0xe49604dfU,
-+    0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U, 0x4665517fU,
-+    0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU,
-+    0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U,
-+    0x9ad7618cU, 0x37a10c7aU, 0x59f8148eU, 0xeb133c89U,
-+    0xcea927eeU, 0xb761c935U, 0xe11ce5edU, 0x7a47b13cU,
-+    0x9cd2df59U, 0x55f2733fU, 0x1814ce79U, 0x73c737bfU,
-+    0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U,
-+    0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU,
-+    0x161dc372U, 0xbce2250cU, 0x283c498bU, 0xff0d9541U,
-+    0x39a80171U, 0x080cb3deU, 0xd8b4e49cU, 0x6456c190U,
-+    0x7bcb8461U, 0xd532b670U, 0x486c5c74U, 0xd0b85742U,
-+};
-+#ifndef AES_SMALL_TABLES
-+const u32 Td1[256] = {
-+    0x5051f4a7U, 0x537e4165U, 0xc31a17a4U, 0x963a275eU,
-+    0xcb3bab6bU, 0xf11f9d45U, 0xabacfa58U, 0x934be303U,
-+    0x552030faU, 0xf6ad766dU, 0x9188cc76U, 0x25f5024cU,
-+    0xfc4fe5d7U, 0xd7c52acbU, 0x80263544U, 0x8fb562a3U,
-+    0x49deb15aU, 0x6725ba1bU, 0x9845ea0eU, 0xe15dfec0U,
-+    0x02c32f75U, 0x12814cf0U, 0xa38d4697U, 0xc66bd3f9U,
-+    0xe7038f5fU, 0x9515929cU, 0xebbf6d7aU, 0xda955259U,
-+    0x2dd4be83U, 0xd3587421U, 0x2949e069U, 0x448ec9c8U,
-+    0x6a75c289U, 0x78f48e79U, 0x6b99583eU, 0xdd27b971U,
-+    0xb6bee14fU, 0x17f088adU, 0x66c920acU, 0xb47dce3aU,
-+    0x1863df4aU, 0x82e51a31U, 0x60975133U, 0x4562537fU,
-+    0xe0b16477U, 0x84bb6baeU, 0x1cfe81a0U, 0x94f9082bU,
-+    0x58704868U, 0x198f45fdU, 0x8794de6cU, 0xb7527bf8U,
-+    0x23ab73d3U, 0xe2724b02U, 0x57e31f8fU, 0x2a6655abU,
-+    0x07b2eb28U, 0x032fb5c2U, 0x9a86c57bU, 0xa5d33708U,
-+    0xf2302887U, 0xb223bfa5U, 0xba02036aU, 0x5ced1682U,
-+    0x2b8acf1cU, 0x92a779b4U, 0xf0f307f2U, 0xa14e69e2U,
-+    0xcd65daf4U, 0xd50605beU, 0x1fd13462U, 0x8ac4a6feU,
-+    0x9d342e53U, 0xa0a2f355U, 0x32058ae1U, 0x75a4f6ebU,
-+    0x390b83ecU, 0xaa4060efU, 0x065e719fU, 0x51bd6e10U,
-+    0xf93e218aU, 0x3d96dd06U, 0xaedd3e05U, 0x464de6bdU,
-+    0xb591548dU, 0x0571c45dU, 0x6f0406d4U, 0xff605015U,
-+    0x241998fbU, 0x97d6bde9U, 0xcc894043U, 0x7767d99eU,
-+    0xbdb0e842U, 0x8807898bU, 0x38e7195bU, 0xdb79c8eeU,
-+    0x47a17c0aU, 0xe97c420fU, 0xc9f8841eU, 0x00000000U,
-+    0x83098086U, 0x48322bedU, 0xac1e1170U, 0x4e6c5a72U,
-+    0xfbfd0effU, 0x560f8538U, 0x1e3daed5U, 0x27362d39U,
-+    0x640a0fd9U, 0x21685ca6U, 0xd19b5b54U, 0x3a24362eU,
-+    0xb10c0a67U, 0x0f9357e7U, 0xd2b4ee96U, 0x9e1b9b91U,
-+    0x4f80c0c5U, 0xa261dc20U, 0x695a774bU, 0x161c121aU,
-+    0x0ae293baU, 0xe5c0a02aU, 0x433c22e0U, 0x1d121b17U,
-+    0x0b0e090dU, 0xadf28bc7U, 0xb92db6a8U, 0xc8141ea9U,
-+    0x8557f119U, 0x4caf7507U, 0xbbee99ddU, 0xfda37f60U,
-+    0x9ff70126U, 0xbc5c72f5U, 0xc544663bU, 0x345bfb7eU,
-+    0x768b4329U, 0xdccb23c6U, 0x68b6edfcU, 0x63b8e4f1U,
-+    0xcad731dcU, 0x10426385U, 0x40139722U, 0x2084c611U,
-+    0x7d854a24U, 0xf8d2bb3dU, 0x11aef932U, 0x6dc729a1U,
-+    0x4b1d9e2fU, 0xf3dcb230U, 0xec0d8652U, 0xd077c1e3U,
-+    0x6c2bb316U, 0x99a970b9U, 0xfa119448U, 0x2247e964U,
-+    0xc4a8fc8cU, 0x1aa0f03fU, 0xd8567d2cU, 0xef223390U,
-+    0xc787494eU, 0xc1d938d1U, 0xfe8ccaa2U, 0x3698d40bU,
-+    0xcfa6f581U, 0x28a57adeU, 0x26dab78eU, 0xa43fadbfU,
-+    0xe42c3a9dU, 0x0d507892U, 0x9b6a5fccU, 0x62547e46U,
-+    0xc2f68d13U, 0xe890d8b8U, 0x5e2e39f7U, 0xf582c3afU,
-+    0xbe9f5d80U, 0x7c69d093U, 0xa96fd52dU, 0xb3cf2512U,
-+    0x3bc8ac99U, 0xa710187dU, 0x6ee89c63U, 0x7bdb3bbbU,
-+    0x09cd2678U, 0xf46e5918U, 0x01ec9ab7U, 0xa8834f9aU,
-+    0x65e6956eU, 0x7eaaffe6U, 0x0821bccfU, 0xe6ef15e8U,
-+    0xd9bae79bU, 0xce4a6f36U, 0xd4ea9f09U, 0xd629b07cU,
-+    0xaf31a4b2U, 0x312a3f23U, 0x30c6a594U, 0xc035a266U,
-+    0x37744ebcU, 0xa6fc82caU, 0xb0e090d0U, 0x1533a7d8U,
-+    0x4af10498U, 0xf741ecdaU, 0x0e7fcd50U, 0x2f1791f6U,
-+    0x8d764dd6U, 0x4d43efb0U, 0x54ccaa4dU, 0xdfe49604U,
-+    0xe39ed1b5U, 0x1b4c6a88U, 0xb8c12c1fU, 0x7f466551U,
-+    0x049d5eeaU, 0x5d018c35U, 0x73fa8774U, 0x2efb0b41U,
-+    0x5ab3671dU, 0x5292dbd2U, 0x33e91056U, 0x136dd647U,
-+    0x8c9ad761U, 0x7a37a10cU, 0x8e59f814U, 0x89eb133cU,
-+    0xeecea927U, 0x35b761c9U, 0xede11ce5U, 0x3c7a47b1U,
-+    0x599cd2dfU, 0x3f55f273U, 0x791814ceU, 0xbf73c737U,
-+    0xea53f7cdU, 0x5b5ffdaaU, 0x14df3d6fU, 0x867844dbU,
-+    0x81caaff3U, 0x3eb968c4U, 0x2c382434U, 0x5fc2a340U,
-+    0x72161dc3U, 0x0cbce225U, 0x8b283c49U, 0x41ff0d95U,
-+    0x7139a801U, 0xde080cb3U, 0x9cd8b4e4U, 0x906456c1U,
-+    0x617bcb84U, 0x70d532b6U, 0x74486c5cU, 0x42d0b857U,
-+};
-+const u32 Td2[256] = {
-+    0xa75051f4U, 0x65537e41U, 0xa4c31a17U, 0x5e963a27U,
-+    0x6bcb3babU, 0x45f11f9dU, 0x58abacfaU, 0x03934be3U,
-+    0xfa552030U, 0x6df6ad76U, 0x769188ccU, 0x4c25f502U,
-+    0xd7fc4fe5U, 0xcbd7c52aU, 0x44802635U, 0xa38fb562U,
-+    0x5a49deb1U, 0x1b6725baU, 0x0e9845eaU, 0xc0e15dfeU,
-+    0x7502c32fU, 0xf012814cU, 0x97a38d46U, 0xf9c66bd3U,
-+    0x5fe7038fU, 0x9c951592U, 0x7aebbf6dU, 0x59da9552U,
-+    0x832dd4beU, 0x21d35874U, 0x692949e0U, 0xc8448ec9U,
-+    0x896a75c2U, 0x7978f48eU, 0x3e6b9958U, 0x71dd27b9U,
-+    0x4fb6bee1U, 0xad17f088U, 0xac66c920U, 0x3ab47dceU,
-+    0x4a1863dfU, 0x3182e51aU, 0x33609751U, 0x7f456253U,
-+    0x77e0b164U, 0xae84bb6bU, 0xa01cfe81U, 0x2b94f908U,
-+    0x68587048U, 0xfd198f45U, 0x6c8794deU, 0xf8b7527bU,
-+    0xd323ab73U, 0x02e2724bU, 0x8f57e31fU, 0xab2a6655U,
-+    0x2807b2ebU, 0xc2032fb5U, 0x7b9a86c5U, 0x08a5d337U,
-+    0x87f23028U, 0xa5b223bfU, 0x6aba0203U, 0x825ced16U,
-+    0x1c2b8acfU, 0xb492a779U, 0xf2f0f307U, 0xe2a14e69U,
-+    0xf4cd65daU, 0xbed50605U, 0x621fd134U, 0xfe8ac4a6U,
-+    0x539d342eU, 0x55a0a2f3U, 0xe132058aU, 0xeb75a4f6U,
-+    0xec390b83U, 0xefaa4060U, 0x9f065e71U, 0x1051bd6eU,
-+
-+    0x8af93e21U, 0x063d96ddU, 0x05aedd3eU, 0xbd464de6U,
-+    0x8db59154U, 0x5d0571c4U, 0xd46f0406U, 0x15ff6050U,
-+    0xfb241998U, 0xe997d6bdU, 0x43cc8940U, 0x9e7767d9U,
-+    0x42bdb0e8U, 0x8b880789U, 0x5b38e719U, 0xeedb79c8U,
-+    0x0a47a17cU, 0x0fe97c42U, 0x1ec9f884U, 0x00000000U,
-+    0x86830980U, 0xed48322bU, 0x70ac1e11U, 0x724e6c5aU,
-+    0xfffbfd0eU, 0x38560f85U, 0xd51e3daeU, 0x3927362dU,
-+    0xd9640a0fU, 0xa621685cU, 0x54d19b5bU, 0x2e3a2436U,
-+    0x67b10c0aU, 0xe70f9357U, 0x96d2b4eeU, 0x919e1b9bU,
-+    0xc54f80c0U, 0x20a261dcU, 0x4b695a77U, 0x1a161c12U,
-+    0xba0ae293U, 0x2ae5c0a0U, 0xe0433c22U, 0x171d121bU,
-+    0x0d0b0e09U, 0xc7adf28bU, 0xa8b92db6U, 0xa9c8141eU,
-+    0x198557f1U, 0x074caf75U, 0xddbbee99U, 0x60fda37fU,
-+    0x269ff701U, 0xf5bc5c72U, 0x3bc54466U, 0x7e345bfbU,
-+    0x29768b43U, 0xc6dccb23U, 0xfc68b6edU, 0xf163b8e4U,
-+    0xdccad731U, 0x85104263U, 0x22401397U, 0x112084c6U,
-+    0x247d854aU, 0x3df8d2bbU, 0x3211aef9U, 0xa16dc729U,
-+    0x2f4b1d9eU, 0x30f3dcb2U, 0x52ec0d86U, 0xe3d077c1U,
-+    0x166c2bb3U, 0xb999a970U, 0x48fa1194U, 0x642247e9U,
-+    0x8cc4a8fcU, 0x3f1aa0f0U, 0x2cd8567dU, 0x90ef2233U,
-+    0x4ec78749U, 0xd1c1d938U, 0xa2fe8ccaU, 0x0b3698d4U,
-+    0x81cfa6f5U, 0xde28a57aU, 0x8e26dab7U, 0xbfa43fadU,
-+    0x9de42c3aU, 0x920d5078U, 0xcc9b6a5fU, 0x4662547eU,
-+    0x13c2f68dU, 0xb8e890d8U, 0xf75e2e39U, 0xaff582c3U,
-+    0x80be9f5dU, 0x937c69d0U, 0x2da96fd5U, 0x12b3cf25U,
-+    0x993bc8acU, 0x7da71018U, 0x636ee89cU, 0xbb7bdb3bU,
-+    0x7809cd26U, 0x18f46e59U, 0xb701ec9aU, 0x9aa8834fU,
-+    0x6e65e695U, 0xe67eaaffU, 0xcf0821bcU, 0xe8e6ef15U,
-+    0x9bd9bae7U, 0x36ce4a6fU, 0x09d4ea9fU, 0x7cd629b0U,
-+    0xb2af31a4U, 0x23312a3fU, 0x9430c6a5U, 0x66c035a2U,
-+    0xbc37744eU, 0xcaa6fc82U, 0xd0b0e090U, 0xd81533a7U,
-+    0x984af104U, 0xdaf741ecU, 0x500e7fcdU, 0xf62f1791U,
-+    0xd68d764dU, 0xb04d43efU, 0x4d54ccaaU, 0x04dfe496U,
-+    0xb5e39ed1U, 0x881b4c6aU, 0x1fb8c12cU, 0x517f4665U,
-+    0xea049d5eU, 0x355d018cU, 0x7473fa87U, 0x412efb0bU,
-+    0x1d5ab367U, 0xd25292dbU, 0x5633e910U, 0x47136dd6U,
-+    0x618c9ad7U, 0x0c7a37a1U, 0x148e59f8U, 0x3c89eb13U,
-+    0x27eecea9U, 0xc935b761U, 0xe5ede11cU, 0xb13c7a47U,
-+    0xdf599cd2U, 0x733f55f2U, 0xce791814U, 0x37bf73c7U,
-+    0xcdea53f7U, 0xaa5b5ffdU, 0x6f14df3dU, 0xdb867844U,
-+    0xf381caafU, 0xc43eb968U, 0x342c3824U, 0x405fc2a3U,
-+    0xc372161dU, 0x250cbce2U, 0x498b283cU, 0x9541ff0dU,
-+    0x017139a8U, 0xb3de080cU, 0xe49cd8b4U, 0xc1906456U,
-+    0x84617bcbU, 0xb670d532U, 0x5c74486cU, 0x5742d0b8U,
-+};
-+const u32 Td3[256] = {
-+    0xf4a75051U, 0x4165537eU, 0x17a4c31aU, 0x275e963aU,
-+    0xab6bcb3bU, 0x9d45f11fU, 0xfa58abacU, 0xe303934bU,
-+    0x30fa5520U, 0x766df6adU, 0xcc769188U, 0x024c25f5U,
-+    0xe5d7fc4fU, 0x2acbd7c5U, 0x35448026U, 0x62a38fb5U,
-+    0xb15a49deU, 0xba1b6725U, 0xea0e9845U, 0xfec0e15dU,
-+    0x2f7502c3U, 0x4cf01281U, 0x4697a38dU, 0xd3f9c66bU,
-+    0x8f5fe703U, 0x929c9515U, 0x6d7aebbfU, 0x5259da95U,
-+    0xbe832dd4U, 0x7421d358U, 0xe0692949U, 0xc9c8448eU,
-+    0xc2896a75U, 0x8e7978f4U, 0x583e6b99U, 0xb971dd27U,
-+    0xe14fb6beU, 0x88ad17f0U, 0x20ac66c9U, 0xce3ab47dU,
-+    0xdf4a1863U, 0x1a3182e5U, 0x51336097U, 0x537f4562U,
-+    0x6477e0b1U, 0x6bae84bbU, 0x81a01cfeU, 0x082b94f9U,
-+    0x48685870U, 0x45fd198fU, 0xde6c8794U, 0x7bf8b752U,
-+    0x73d323abU, 0x4b02e272U, 0x1f8f57e3U, 0x55ab2a66U,
-+    0xeb2807b2U, 0xb5c2032fU, 0xc57b9a86U, 0x3708a5d3U,
-+    0x2887f230U, 0xbfa5b223U, 0x036aba02U, 0x16825cedU,
-+    0xcf1c2b8aU, 0x79b492a7U, 0x07f2f0f3U, 0x69e2a14eU,
-+    0xdaf4cd65U, 0x05bed506U, 0x34621fd1U, 0xa6fe8ac4U,
-+    0x2e539d34U, 0xf355a0a2U, 0x8ae13205U, 0xf6eb75a4U,
-+    0x83ec390bU, 0x60efaa40U, 0x719f065eU, 0x6e1051bdU,
-+    0x218af93eU, 0xdd063d96U, 0x3e05aeddU, 0xe6bd464dU,
-+    0x548db591U, 0xc45d0571U, 0x06d46f04U, 0x5015ff60U,
-+    0x98fb2419U, 0xbde997d6U, 0x4043cc89U, 0xd99e7767U,
-+    0xe842bdb0U, 0x898b8807U, 0x195b38e7U, 0xc8eedb79U,
-+    0x7c0a47a1U, 0x420fe97cU, 0x841ec9f8U, 0x00000000U,
-+    0x80868309U, 0x2bed4832U, 0x1170ac1eU, 0x5a724e6cU,
-+    0x0efffbfdU, 0x8538560fU, 0xaed51e3dU, 0x2d392736U,
-+    0x0fd9640aU, 0x5ca62168U, 0x5b54d19bU, 0x362e3a24U,
-+    0x0a67b10cU, 0x57e70f93U, 0xee96d2b4U, 0x9b919e1bU,
-+    0xc0c54f80U, 0xdc20a261U, 0x774b695aU, 0x121a161cU,
-+    0x93ba0ae2U, 0xa02ae5c0U, 0x22e0433cU, 0x1b171d12U,
-+    0x090d0b0eU, 0x8bc7adf2U, 0xb6a8b92dU, 0x1ea9c814U,
-+    0xf1198557U, 0x75074cafU, 0x99ddbbeeU, 0x7f60fda3U,
-+    0x01269ff7U, 0x72f5bc5cU, 0x663bc544U, 0xfb7e345bU,
-+    0x4329768bU, 0x23c6dccbU, 0xedfc68b6U, 0xe4f163b8U,
-+    0x31dccad7U, 0x63851042U, 0x97224013U, 0xc6112084U,
-+    0x4a247d85U, 0xbb3df8d2U, 0xf93211aeU, 0x29a16dc7U,
-+    0x9e2f4b1dU, 0xb230f3dcU, 0x8652ec0dU, 0xc1e3d077U,
-+    0xb3166c2bU, 0x70b999a9U, 0x9448fa11U, 0xe9642247U,
-+    0xfc8cc4a8U, 0xf03f1aa0U, 0x7d2cd856U, 0x3390ef22U,
-+    0x494ec787U, 0x38d1c1d9U, 0xcaa2fe8cU, 0xd40b3698U,
-+    0xf581cfa6U, 0x7ade28a5U, 0xb78e26daU, 0xadbfa43fU,
-+    0x3a9de42cU, 0x78920d50U, 0x5fcc9b6aU, 0x7e466254U,
-+    0x8d13c2f6U, 0xd8b8e890U, 0x39f75e2eU, 0xc3aff582U,
-+    0x5d80be9fU, 0xd0937c69U, 0xd52da96fU, 0x2512b3cfU,
-+    0xac993bc8U, 0x187da710U, 0x9c636ee8U, 0x3bbb7bdbU,
-+    0x267809cdU, 0x5918f46eU, 0x9ab701ecU, 0x4f9aa883U,
-+    0x956e65e6U, 0xffe67eaaU, 0xbccf0821U, 0x15e8e6efU,
-+    0xe79bd9baU, 0x6f36ce4aU, 0x9f09d4eaU, 0xb07cd629U,
-+    0xa4b2af31U, 0x3f23312aU, 0xa59430c6U, 0xa266c035U,
-+    0x4ebc3774U, 0x82caa6fcU, 0x90d0b0e0U, 0xa7d81533U,
-+    0x04984af1U, 0xecdaf741U, 0xcd500e7fU, 0x91f62f17U,
-+    0x4dd68d76U, 0xefb04d43U, 0xaa4d54ccU, 0x9604dfe4U,
-+    0xd1b5e39eU, 0x6a881b4cU, 0x2c1fb8c1U, 0x65517f46U,
-+    0x5eea049dU, 0x8c355d01U, 0x877473faU, 0x0b412efbU,
-+    0x671d5ab3U, 0xdbd25292U, 0x105633e9U, 0xd647136dU,
-+    0xd7618c9aU, 0xa10c7a37U, 0xf8148e59U, 0x133c89ebU,
-+    0xa927eeceU, 0x61c935b7U, 0x1ce5ede1U, 0x47b13c7aU,
-+    0xd2df599cU, 0xf2733f55U, 0x14ce7918U, 0xc737bf73U,
-+    0xf7cdea53U, 0xfdaa5b5fU, 0x3d6f14dfU, 0x44db8678U,
-+    0xaff381caU, 0x68c43eb9U, 0x24342c38U, 0xa3405fc2U,
-+    0x1dc37216U, 0xe2250cbcU, 0x3c498b28U, 0x0d9541ffU,
-+    0xa8017139U, 0x0cb3de08U, 0xb4e49cd8U, 0x56c19064U,
-+    0xcb84617bU, 0x32b670d5U, 0x6c5c7448U, 0xb85742d0U,
-+};
-+const u32 Td4[256] = {
-+    0x52525252U, 0x09090909U, 0x6a6a6a6aU, 0xd5d5d5d5U,
-+    0x30303030U, 0x36363636U, 0xa5a5a5a5U, 0x38383838U,
-+    0xbfbfbfbfU, 0x40404040U, 0xa3a3a3a3U, 0x9e9e9e9eU,
-+    0x81818181U, 0xf3f3f3f3U, 0xd7d7d7d7U, 0xfbfbfbfbU,
-+    0x7c7c7c7cU, 0xe3e3e3e3U, 0x39393939U, 0x82828282U,
-+    0x9b9b9b9bU, 0x2f2f2f2fU, 0xffffffffU, 0x87878787U,
-+    0x34343434U, 0x8e8e8e8eU, 0x43434343U, 0x44444444U,
-+    0xc4c4c4c4U, 0xdedededeU, 0xe9e9e9e9U, 0xcbcbcbcbU,
-+    0x54545454U, 0x7b7b7b7bU, 0x94949494U, 0x32323232U,
-+    0xa6a6a6a6U, 0xc2c2c2c2U, 0x23232323U, 0x3d3d3d3dU,
-+    0xeeeeeeeeU, 0x4c4c4c4cU, 0x95959595U, 0x0b0b0b0bU,
-+    0x42424242U, 0xfafafafaU, 0xc3c3c3c3U, 0x4e4e4e4eU,
-+    0x08080808U, 0x2e2e2e2eU, 0xa1a1a1a1U, 0x66666666U,
-+    0x28282828U, 0xd9d9d9d9U, 0x24242424U, 0xb2b2b2b2U,
-+    0x76767676U, 0x5b5b5b5bU, 0xa2a2a2a2U, 0x49494949U,
-+    0x6d6d6d6dU, 0x8b8b8b8bU, 0xd1d1d1d1U, 0x25252525U,
-+    0x72727272U, 0xf8f8f8f8U, 0xf6f6f6f6U, 0x64646464U,
-+    0x86868686U, 0x68686868U, 0x98989898U, 0x16161616U,
-+    0xd4d4d4d4U, 0xa4a4a4a4U, 0x5c5c5c5cU, 0xccccccccU,
-+    0x5d5d5d5dU, 0x65656565U, 0xb6b6b6b6U, 0x92929292U,
-+    0x6c6c6c6cU, 0x70707070U, 0x48484848U, 0x50505050U,
-+    0xfdfdfdfdU, 0xededededU, 0xb9b9b9b9U, 0xdadadadaU,
-+    0x5e5e5e5eU, 0x15151515U, 0x46464646U, 0x57575757U,
-+    0xa7a7a7a7U, 0x8d8d8d8dU, 0x9d9d9d9dU, 0x84848484U,
-+    0x90909090U, 0xd8d8d8d8U, 0xababababU, 0x00000000U,
-+    0x8c8c8c8cU, 0xbcbcbcbcU, 0xd3d3d3d3U, 0x0a0a0a0aU,
-+    0xf7f7f7f7U, 0xe4e4e4e4U, 0x58585858U, 0x05050505U,
-+    0xb8b8b8b8U, 0xb3b3b3b3U, 0x45454545U, 0x06060606U,
-+    0xd0d0d0d0U, 0x2c2c2c2cU, 0x1e1e1e1eU, 0x8f8f8f8fU,
-+    0xcacacacaU, 0x3f3f3f3fU, 0x0f0f0f0fU, 0x02020202U,
-+    0xc1c1c1c1U, 0xafafafafU, 0xbdbdbdbdU, 0x03030303U,
-+    0x01010101U, 0x13131313U, 0x8a8a8a8aU, 0x6b6b6b6bU,
-+    0x3a3a3a3aU, 0x91919191U, 0x11111111U, 0x41414141U,
-+    0x4f4f4f4fU, 0x67676767U, 0xdcdcdcdcU, 0xeaeaeaeaU,
-+    0x97979797U, 0xf2f2f2f2U, 0xcfcfcfcfU, 0xcecececeU,
-+    0xf0f0f0f0U, 0xb4b4b4b4U, 0xe6e6e6e6U, 0x73737373U,
-+    0x96969696U, 0xacacacacU, 0x74747474U, 0x22222222U,
-+    0xe7e7e7e7U, 0xadadadadU, 0x35353535U, 0x85858585U,
-+    0xe2e2e2e2U, 0xf9f9f9f9U, 0x37373737U, 0xe8e8e8e8U,
-+    0x1c1c1c1cU, 0x75757575U, 0xdfdfdfdfU, 0x6e6e6e6eU,
-+    0x47474747U, 0xf1f1f1f1U, 0x1a1a1a1aU, 0x71717171U,
-+    0x1d1d1d1dU, 0x29292929U, 0xc5c5c5c5U, 0x89898989U,
-+    0x6f6f6f6fU, 0xb7b7b7b7U, 0x62626262U, 0x0e0e0e0eU,
-+    0xaaaaaaaaU, 0x18181818U, 0xbebebebeU, 0x1b1b1b1bU,
-+    0xfcfcfcfcU, 0x56565656U, 0x3e3e3e3eU, 0x4b4b4b4bU,
-+    0xc6c6c6c6U, 0xd2d2d2d2U, 0x79797979U, 0x20202020U,
-+    0x9a9a9a9aU, 0xdbdbdbdbU, 0xc0c0c0c0U, 0xfefefefeU,
-+    0x78787878U, 0xcdcdcdcdU, 0x5a5a5a5aU, 0xf4f4f4f4U,
-+    0x1f1f1f1fU, 0xddddddddU, 0xa8a8a8a8U, 0x33333333U,
-+    0x88888888U, 0x07070707U, 0xc7c7c7c7U, 0x31313131U,
-+    0xb1b1b1b1U, 0x12121212U, 0x10101010U, 0x59595959U,
-+    0x27272727U, 0x80808080U, 0xececececU, 0x5f5f5f5fU,
-+    0x60606060U, 0x51515151U, 0x7f7f7f7fU, 0xa9a9a9a9U,
-+    0x19191919U, 0xb5b5b5b5U, 0x4a4a4a4aU, 0x0d0d0d0dU,
-+    0x2d2d2d2dU, 0xe5e5e5e5U, 0x7a7a7a7aU, 0x9f9f9f9fU,
-+    0x93939393U, 0xc9c9c9c9U, 0x9c9c9c9cU, 0xefefefefU,
-+    0xa0a0a0a0U, 0xe0e0e0e0U, 0x3b3b3b3bU, 0x4d4d4d4dU,
-+    0xaeaeaeaeU, 0x2a2a2a2aU, 0xf5f5f5f5U, 0xb0b0b0b0U,
-+    0xc8c8c8c8U, 0xebebebebU, 0xbbbbbbbbU, 0x3c3c3c3cU,
-+    0x83838383U, 0x53535353U, 0x99999999U, 0x61616161U,
-+    0x17171717U, 0x2b2b2b2bU, 0x04040404U, 0x7e7e7e7eU,
-+    0xbabababaU, 0x77777777U, 0xd6d6d6d6U, 0x26262626U,
-+    0xe1e1e1e1U, 0x69696969U, 0x14141414U, 0x63636363U,
-+    0x55555555U, 0x21212121U, 0x0c0c0c0cU, 0x7d7d7d7dU,
-+};
-+const u32 rcon[] = {
-+	0x01000000, 0x02000000, 0x04000000, 0x08000000,
-+	0x10000000, 0x20000000, 0x40000000, 0x80000000,
-+	0x1B000000, 0x36000000, /* for 128-bit blocks, Rijndael never uses more than 10 rcon values */
-+};
-+#else /* AES_SMALL_TABLES */
-+const u8 Td4s[256] = {
-+    0x52U, 0x09U, 0x6aU, 0xd5U, 0x30U, 0x36U, 0xa5U, 0x38U,
-+    0xbfU, 0x40U, 0xa3U, 0x9eU, 0x81U, 0xf3U, 0xd7U, 0xfbU,
-+    0x7cU, 0xe3U, 0x39U, 0x82U, 0x9bU, 0x2fU, 0xffU, 0x87U,
-+    0x34U, 0x8eU, 0x43U, 0x44U, 0xc4U, 0xdeU, 0xe9U, 0xcbU,
-+    0x54U, 0x7bU, 0x94U, 0x32U, 0xa6U, 0xc2U, 0x23U, 0x3dU,
-+    0xeeU, 0x4cU, 0x95U, 0x0bU, 0x42U, 0xfaU, 0xc3U, 0x4eU,
-+    0x08U, 0x2eU, 0xa1U, 0x66U, 0x28U, 0xd9U, 0x24U, 0xb2U,
-+    0x76U, 0x5bU, 0xa2U, 0x49U, 0x6dU, 0x8bU, 0xd1U, 0x25U,
-+    0x72U, 0xf8U, 0xf6U, 0x64U, 0x86U, 0x68U, 0x98U, 0x16U,
-+    0xd4U, 0xa4U, 0x5cU, 0xccU, 0x5dU, 0x65U, 0xb6U, 0x92U,
-+    0x6cU, 0x70U, 0x48U, 0x50U, 0xfdU, 0xedU, 0xb9U, 0xdaU,
-+    0x5eU, 0x15U, 0x46U, 0x57U, 0xa7U, 0x8dU, 0x9dU, 0x84U,
-+    0x90U, 0xd8U, 0xabU, 0x00U, 0x8cU, 0xbcU, 0xd3U, 0x0aU,
-+    0xf7U, 0xe4U, 0x58U, 0x05U, 0xb8U, 0xb3U, 0x45U, 0x06U,
-+    0xd0U, 0x2cU, 0x1eU, 0x8fU, 0xcaU, 0x3fU, 0x0fU, 0x02U,
-+    0xc1U, 0xafU, 0xbdU, 0x03U, 0x01U, 0x13U, 0x8aU, 0x6bU,
-+    0x3aU, 0x91U, 0x11U, 0x41U, 0x4fU, 0x67U, 0xdcU, 0xeaU,
-+    0x97U, 0xf2U, 0xcfU, 0xceU, 0xf0U, 0xb4U, 0xe6U, 0x73U,
-+    0x96U, 0xacU, 0x74U, 0x22U, 0xe7U, 0xadU, 0x35U, 0x85U,
-+    0xe2U, 0xf9U, 0x37U, 0xe8U, 0x1cU, 0x75U, 0xdfU, 0x6eU,
-+    0x47U, 0xf1U, 0x1aU, 0x71U, 0x1dU, 0x29U, 0xc5U, 0x89U,
-+    0x6fU, 0xb7U, 0x62U, 0x0eU, 0xaaU, 0x18U, 0xbeU, 0x1bU,
-+    0xfcU, 0x56U, 0x3eU, 0x4bU, 0xc6U, 0xd2U, 0x79U, 0x20U,
-+    0x9aU, 0xdbU, 0xc0U, 0xfeU, 0x78U, 0xcdU, 0x5aU, 0xf4U,
-+    0x1fU, 0xddU, 0xa8U, 0x33U, 0x88U, 0x07U, 0xc7U, 0x31U,
-+    0xb1U, 0x12U, 0x10U, 0x59U, 0x27U, 0x80U, 0xecU, 0x5fU,
-+    0x60U, 0x51U, 0x7fU, 0xa9U, 0x19U, 0xb5U, 0x4aU, 0x0dU,
-+    0x2dU, 0xe5U, 0x7aU, 0x9fU, 0x93U, 0xc9U, 0x9cU, 0xefU,
-+    0xa0U, 0xe0U, 0x3bU, 0x4dU, 0xaeU, 0x2aU, 0xf5U, 0xb0U,
-+    0xc8U, 0xebU, 0xbbU, 0x3cU, 0x83U, 0x53U, 0x99U, 0x61U,
-+    0x17U, 0x2bU, 0x04U, 0x7eU, 0xbaU, 0x77U, 0xd6U, 0x26U,
-+    0xe1U, 0x69U, 0x14U, 0x63U, 0x55U, 0x21U, 0x0cU, 0x7dU,
-+};
-+const u8 rcons[] = {
-+	0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1B, 0x36
-+	/* for 128-bit blocks, Rijndael never uses more than 10 rcon values */
-+};
-+#endif /* AES_SMALL_TABLES */
-+/**
-+ * Expand the cipher key into the encryption key schedule.
-+ *
-+ * @return	the number of rounds for the given cipher key size.
-+ */
-+int rijndaelKeySetupEnc(u32 rk[], const u8 cipherKey[], int keyBits)
-+{
-+	int i;
-+	u32 temp;
-+
-+	rk[0] = GETU32(cipherKey     );
-+	rk[1] = GETU32(cipherKey +  4);
-+	rk[2] = GETU32(cipherKey +  8);
-+	rk[3] = GETU32(cipherKey + 12);
-+
-+	if (keyBits == 128) {
-+		for (i = 0; i < 10; i++) {
-+			temp  = rk[3];
-+			rk[4] = rk[0] ^ TE421(temp) ^ TE432(temp) ^
-+				TE443(temp) ^ TE414(temp) ^ RCON(i);
-+			rk[5] = rk[1] ^ rk[4];
-+			rk[6] = rk[2] ^ rk[5];
-+			rk[7] = rk[3] ^ rk[6];
-+			rk += 4;
-+		}
-+		return 10;
-+	}
-+
-+	rk[4] = GETU32(cipherKey + 16);
-+	rk[5] = GETU32(cipherKey + 20);
-+
-+	if (keyBits == 192) {
-+		for (i = 0; i < 8; i++) {
-+			temp  = rk[5];
-+			rk[6] = rk[0] ^ TE421(temp) ^ TE432(temp) ^
-+				TE443(temp) ^ TE414(temp) ^ RCON(i);
-+			rk[7] = rk[1] ^ rk[6];
-+			rk[8] = rk[2] ^ rk[7];
-+			rk[9] = rk[3] ^ rk[8];
-+			if (i == 7)
-+				return 12;
-+			rk[10] = rk[4] ^ rk[9];
-+			rk[11] = rk[5] ^ rk[10];
-+			rk += 6;
-+		}
-+	}
-+
-+	rk[6] = GETU32(cipherKey + 24);
-+	rk[7] = GETU32(cipherKey + 28);
-+
-+	if (keyBits == 256) {
-+		for (i = 0; i < 7; i++) {
-+			temp  = rk[7];
-+			rk[8] = rk[0] ^ TE421(temp) ^ TE432(temp) ^
-+				TE443(temp) ^ TE414(temp) ^ RCON(i);
-+			rk[9] = rk[1] ^ rk[8];
-+			rk[10] = rk[2] ^ rk[9];
-+			rk[11] = rk[3] ^ rk[10];
-+			if (i == 6)
-+				return 14;
-+			temp  = rk[11];
-+			rk[12] = rk[4] ^ TE411(temp) ^ TE422(temp) ^
-+				TE433(temp) ^ TE444(temp);
-+			rk[13] = rk[5] ^ rk[12];
-+			rk[14] = rk[6] ^ rk[13];
-+			rk[15] = rk[7] ^ rk[14];
-+			rk += 8;
-+		}
-+	}
-+
-+	return -1;
-+}
-diff --git a/drivers/staging/rtl8723cs/core/crypto/aes-omac1.c b/drivers/staging/rtl8723cs/core/crypto/aes-omac1.c
-new file mode 100644
-index 000000000000..2d20aed87046
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/aes-omac1.c
-@@ -0,0 +1,172 @@
-+/*
-+ * One-key CBC MAC (OMAC1) hash with AES
-+ *
-+ * Copyright (c) 2003-2007, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#include "rtw_crypto_wrap.h"
-+
-+#include "aes.h"
-+#include "aes_wrap.h"
-+
-+static void gf_mulx(u8 *pad)
-+{
-+	int i, carry;
-+
-+	carry = pad[0] & 0x80;
-+	for (i = 0; i < AES_BLOCK_SIZE - 1; i++)
-+		pad[i] = (pad[i] << 1) | (pad[i + 1] >> 7);
-+	pad[AES_BLOCK_SIZE - 1] <<= 1;
-+	if (carry)
-+		pad[AES_BLOCK_SIZE - 1] ^= 0x87;
-+}
-+
-+
-+/**
-+ * omac1_aes_vector - One-Key CBC MAC (OMAC1) hash with AES
-+ * @key: Key for the hash operation
-+ * @key_len: Key length in octets
-+ * @num_elem: Number of elements in the data vector
-+ * @addr: Pointers to the data areas
-+ * @len: Lengths of the data blocks
-+ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes)
-+ * Returns: 0 on success, -1 on failure
-+ *
-+ * This is a mode for using block cipher (AES in this case) for authentication.
-+ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication
-+ * (SP) 800-38B.
-+ */
-+int omac1_aes_vector(const u8 *key, size_t key_len, size_t num_elem,
-+		     const u8 *addr[], const size_t *len, u8 *mac)
-+{
-+	void *ctx;
-+	u8 cbc[AES_BLOCK_SIZE], pad[AES_BLOCK_SIZE];
-+	const u8 *pos, *end;
-+	size_t i, e, left, total_len;
-+
-+	if (TEST_FAIL())
-+		return -1;
-+
-+	ctx = aes_encrypt_init(key, key_len);
-+	if (ctx == NULL)
-+		return -1;
-+	os_memset(cbc, 0, AES_BLOCK_SIZE);
-+
-+	total_len = 0;
-+	for (e = 0; e < num_elem; e++)
-+		total_len += len[e];
-+	left = total_len;
-+
-+	e = 0;
-+	pos = addr[0];
-+	end = pos + len[0];
-+
-+	while (left >= AES_BLOCK_SIZE) {
-+		for (i = 0; i < AES_BLOCK_SIZE; i++) {
-+			cbc[i] ^= *pos++;
-+			if (pos >= end) {
-+				/*
-+				 * Stop if there are no more bytes to process
-+				 * since there are no more entries in the array.
-+				 */
-+				if (i + 1 == AES_BLOCK_SIZE &&
-+				    left == AES_BLOCK_SIZE)
-+					break;
-+				e++;
-+				pos = addr[e];
-+				end = pos + len[e];
-+			}
-+		}
-+		if (left > AES_BLOCK_SIZE)
-+			aes_encrypt_128(ctx, cbc, cbc);
-+		left -= AES_BLOCK_SIZE;
-+	}
-+
-+	os_memset(pad, 0, AES_BLOCK_SIZE);
-+	aes_encrypt_128(ctx, pad, pad);
-+	gf_mulx(pad);
-+
-+	if (left || total_len == 0) {
-+		for (i = 0; i < left; i++) {
-+			cbc[i] ^= *pos++;
-+			if (pos >= end) {
-+				/*
-+				 * Stop if there are no more bytes to process
-+				 * since there are no more entries in the array.
-+				 */
-+				if (i + 1 == left)
-+					break;
-+				e++;
-+				pos = addr[e];
-+				end = pos + len[e];
-+			}
-+		}
-+		cbc[left] ^= 0x80;
-+		gf_mulx(pad);
-+	}
-+
-+	for (i = 0; i < AES_BLOCK_SIZE; i++)
-+		pad[i] ^= cbc[i];
-+	aes_encrypt_128(ctx, pad, mac);
-+	aes_encrypt_deinit(ctx);
-+	return 0;
-+}
-+
-+
-+/**
-+ * omac1_aes_128_vector - One-Key CBC MAC (OMAC1) hash with AES-128
-+ * @key: 128-bit key for the hash operation
-+ * @num_elem: Number of elements in the data vector
-+ * @addr: Pointers to the data areas
-+ * @len: Lengths of the data blocks
-+ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes)
-+ * Returns: 0 on success, -1 on failure
-+ *
-+ * This is a mode for using block cipher (AES in this case) for authentication.
-+ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication
-+ * (SP) 800-38B.
-+ */
-+int omac1_aes_128_vector(const u8 *key, size_t num_elem,
-+			 const u8 *addr[], const size_t *len, u8 *mac)
-+{
-+	return omac1_aes_vector(key, 16, num_elem, addr, len, mac);
-+}
-+
-+
-+/**
-+ * omac1_aes_128 - One-Key CBC MAC (OMAC1) hash with AES-128 (aka AES-CMAC)
-+ * @key: 128-bit key for the hash operation
-+ * @data: Data buffer for which a MAC is determined
-+ * @data_len: Length of data buffer in bytes
-+ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes)
-+ * Returns: 0 on success, -1 on failure
-+ *
-+ * This is a mode for using block cipher (AES in this case) for authentication.
-+ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication
-+ * (SP) 800-38B.
-+ */
-+int omac1_aes_128(const u8 *key, const u8 *data, size_t data_len, u8 *mac)
-+{
-+	return omac1_aes_128_vector(key, 1, &data, &data_len, mac);
-+}
-+
-+
-+/**
-+ * omac1_aes_256 - One-Key CBC MAC (OMAC1) hash with AES-256 (aka AES-CMAC)
-+ * @key: 256-bit key for the hash operation
-+ * @data: Data buffer for which a MAC is determined
-+ * @data_len: Length of data buffer in bytes
-+ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes)
-+ * Returns: 0 on success, -1 on failure
-+ *
-+ * This is a mode for using block cipher (AES in this case) for authentication.
-+ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication
-+ * (SP) 800-38B.
-+ */
-+int omac1_aes_256(const u8 *key, const u8 *data, size_t data_len, u8 *mac)
-+{
-+	return omac1_aes_vector(key, 32, 1, &data, &data_len, mac);
-+}
-diff --git a/drivers/staging/rtl8723cs/core/crypto/aes-siv.c b/drivers/staging/rtl8723cs/core/crypto/aes-siv.c
-new file mode 100644
-index 000000000000..58656f2b5de4
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/aes-siv.c
-@@ -0,0 +1,207 @@
-+/*
-+ * AES SIV (RFC 5297)
-+ * Copyright (c) 2013 Cozybit, Inc.
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#include "rtw_crypto_wrap.h"
-+
-+#include "aes.h"
-+#include "aes_wrap.h"
-+#include "aes_siv.h"
-+
-+
-+static const u8 zero[AES_BLOCK_SIZE];
-+
-+
-+static void dbl(u8 *pad)
-+{
-+	int i, carry;
-+
-+	carry = pad[0] & 0x80;
-+	for (i = 0; i < AES_BLOCK_SIZE - 1; i++)
-+		pad[i] = (pad[i] << 1) | (pad[i + 1] >> 7);
-+	pad[AES_BLOCK_SIZE - 1] <<= 1;
-+	if (carry)
-+		pad[AES_BLOCK_SIZE - 1] ^= 0x87;
-+}
-+
-+
-+static void xor(u8 *a, const u8 *b)
-+{
-+	int i;
-+
-+	for (i = 0; i < AES_BLOCK_SIZE; i++)
-+		*a++ ^= *b++;
-+}
-+
-+
-+static void xorend(u8 *a, int alen, const u8 *b, int blen)
-+{
-+	int i;
-+
-+	if (alen < blen)
-+		return;
-+
-+	for (i = 0; i < blen; i++)
-+		a[alen - blen + i] ^= b[i];
-+}
-+
-+
-+static void pad_block(u8 *pad, const u8 *addr, size_t len)
-+{
-+	os_memset(pad, 0, AES_BLOCK_SIZE);
-+	os_memcpy(pad, addr, len);
-+
-+	if (len < AES_BLOCK_SIZE)
-+		pad[len] = 0x80;
-+}
-+
-+
-+static int aes_s2v(const u8 *key, size_t key_len,
-+		   size_t num_elem, const u8 *addr[], size_t *len, u8 *mac)
-+{
-+	u8 tmp[AES_BLOCK_SIZE], tmp2[AES_BLOCK_SIZE];
-+	u8 *buf = NULL;
-+	int ret;
-+	size_t i;
-+	const u8 *data[1];
-+	size_t data_len[1];
-+
-+	if (!num_elem) {
-+		os_memcpy(tmp, zero, sizeof(zero));
-+		tmp[AES_BLOCK_SIZE - 1] = 1;
-+		data[0] = tmp;
-+		data_len[0] = sizeof(tmp);
-+		return omac1_aes_vector(key, key_len, 1, data, data_len, mac);
-+	}
-+
-+	data[0] = zero;
-+	data_len[0] = sizeof(zero);
-+	ret = omac1_aes_vector(key, key_len, 1, data, data_len, tmp);
-+	if (ret)
-+		return ret;
-+
-+	for (i = 0; i < num_elem - 1; i++) {
-+		ret = omac1_aes_vector(key, key_len, 1, &addr[i], &len[i],
-+				       tmp2);
-+		if (ret)
-+			return ret;
-+
-+		dbl(tmp);
-+		xor(tmp, tmp2);
-+	}
-+	if (len[i] >= AES_BLOCK_SIZE) {
-+		buf = os_memdup(addr[i], len[i]);
-+		if (!buf)
-+			return -ENOMEM;
-+
-+		xorend(buf, len[i], tmp, AES_BLOCK_SIZE);
-+		data[0] = buf;
-+		ret = omac1_aes_vector(key, key_len, 1, data, &len[i], mac);
-+		bin_clear_free(buf, len[i]);
-+		return ret;
-+	}
-+
-+	dbl(tmp);
-+	pad_block(tmp2, addr[i], len[i]);
-+	xor(tmp, tmp2);
-+
-+	data[0] = tmp;
-+	data_len[0] = sizeof(tmp);
-+	return omac1_aes_vector(key, key_len, 1, data, data_len, mac);
-+}
-+
-+
-+int aes_siv_encrypt(const u8 *key, size_t key_len,
-+		    const u8 *pw, size_t pwlen,
-+		    size_t num_elem, const u8 *addr[], const size_t *len,
-+		    u8 *out)
-+{
-+	const u8 *_addr[6];
-+	size_t _len[6];
-+	const u8 *k1, *k2;
-+	u8 v[AES_BLOCK_SIZE];
-+	size_t i;
-+	u8 *iv, *crypt_pw;
-+
-+	if (num_elem > ARRAY_SIZE(_addr) - 1 ||
-+	    (key_len != 32 && key_len != 48 && key_len != 64))
-+		return -1;
-+
-+	key_len /= 2;
-+	k1 = key;
-+	k2 = key + key_len;
-+
-+	for (i = 0; i < num_elem; i++) {
-+		_addr[i] = addr[i];
-+		_len[i] = len[i];
-+	}
-+	_addr[num_elem] = pw;
-+	_len[num_elem] = pwlen;
-+
-+	if (aes_s2v(k1, key_len, num_elem + 1, _addr, _len, v))
-+		return -1;
-+
-+	iv = out;
-+	crypt_pw = out + AES_BLOCK_SIZE;
-+
-+	os_memcpy(iv, v, AES_BLOCK_SIZE);
-+	os_memcpy(crypt_pw, pw, pwlen);
-+
-+	/* zero out 63rd and 31st bits of ctr (from right) */
-+	v[8] &= 0x7f;
-+	v[12] &= 0x7f;
-+	return aes_ctr_encrypt(k2, key_len, v, crypt_pw, pwlen);
-+}
-+
-+
-+int aes_siv_decrypt(const u8 *key, size_t key_len,
-+		    const u8 *iv_crypt, size_t iv_c_len,
-+		    size_t num_elem, const u8 *addr[], const size_t *len,
-+		    u8 *out)
-+{
-+	const u8 *_addr[6];
-+	size_t _len[6];
-+	const u8 *k1, *k2;
-+	size_t crypt_len;
-+	size_t i;
-+	int ret;
-+	u8 iv[AES_BLOCK_SIZE];
-+	u8 check[AES_BLOCK_SIZE];
-+
-+	if (iv_c_len < AES_BLOCK_SIZE || num_elem > ARRAY_SIZE(_addr) - 1 ||
-+	    (key_len != 32 && key_len != 48 && key_len != 64))
-+		return -1;
-+	crypt_len = iv_c_len - AES_BLOCK_SIZE;
-+	key_len /= 2;
-+	k1 = key;
-+	k2 = key + key_len;
-+
-+	for (i = 0; i < num_elem; i++) {
-+		_addr[i] = addr[i];
-+		_len[i] = len[i];
-+	}
-+	_addr[num_elem] = out;
-+	_len[num_elem] = crypt_len;
-+
-+	os_memcpy(iv, iv_crypt, AES_BLOCK_SIZE);
-+	os_memcpy(out, iv_crypt + AES_BLOCK_SIZE, crypt_len);
-+
-+	iv[8] &= 0x7f;
-+	iv[12] &= 0x7f;
-+
-+	ret = aes_ctr_encrypt(k2, key_len, iv, out, crypt_len);
-+	if (ret)
-+		return ret;
-+
-+	ret = aes_s2v(k1, key_len, num_elem + 1, _addr, _len, check);
-+	if (ret)
-+		return ret;
-+	if (os_memcmp(check, iv_crypt, AES_BLOCK_SIZE) == 0)
-+		return 0;
-+
-+	return -1;
-+}
-diff --git a/drivers/staging/rtl8723cs/core/crypto/aes.h b/drivers/staging/rtl8723cs/core/crypto/aes.h
-new file mode 100644
-index 000000000000..1aafe3b4e52f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/aes.h
-@@ -0,0 +1,21 @@
-+/*
-+ * AES functions
-+ * Copyright (c) 2003-2006, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#ifndef AES_H
-+#define AES_H
-+
-+#define AES_BLOCK_SIZE 16
-+
-+void * aes_encrypt_init(const u8 *key, size_t len);
-+int aes_encrypt_128(void *ctx, const u8 *plain, u8 *crypt);
-+void aes_encrypt_deinit(void *ctx);
-+void * aes_decrypt_init(const u8 *key, size_t len);
-+int aes_decrypt(void *ctx, const u8 *crypt, u8 *plain);
-+void aes_decrypt_deinit(void *ctx);
-+
-+#endif /* AES_H */
-diff --git a/drivers/staging/rtl8723cs/core/crypto/aes_i.h b/drivers/staging/rtl8723cs/core/crypto/aes_i.h
-new file mode 100644
-index 000000000000..54375cf35583
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/aes_i.h
-@@ -0,0 +1,125 @@
-+/*
-+ * AES (Rijndael) cipher
-+ * Copyright (c) 2003-2012, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#ifndef AES_I_H
-+#define AES_I_H
-+
-+#include "aes.h"
-+
-+/* #define FULL_UNROLL */
-+#define AES_SMALL_TABLES
-+
-+extern const u32 Te0[256];
-+extern const u32 Te1[256];
-+extern const u32 Te2[256];
-+extern const u32 Te3[256];
-+extern const u32 Te4[256];
-+extern const u32 Td0[256];
-+extern const u32 Td1[256];
-+extern const u32 Td2[256];
-+extern const u32 Td3[256];
-+extern const u32 Td4[256];
-+extern const u32 rcon[10];
-+extern const u8 Td4s[256];
-+extern const u8 rcons[10];
-+
-+#ifndef AES_SMALL_TABLES
-+
-+#define RCON(i) rcon[(i)]
-+
-+#define TE0(i) Te0[((i) >> 24) & 0xff]
-+#define TE1(i) Te1[((i) >> 16) & 0xff]
-+#define TE2(i) Te2[((i) >> 8) & 0xff]
-+#define TE3(i) Te3[(i) & 0xff]
-+#define TE41(i) (Te4[((i) >> 24) & 0xff] & 0xff000000)
-+#define TE42(i) (Te4[((i) >> 16) & 0xff] & 0x00ff0000)
-+#define TE43(i) (Te4[((i) >> 8) & 0xff] & 0x0000ff00)
-+#define TE44(i) (Te4[(i) & 0xff] & 0x000000ff)
-+#define TE421(i) (Te4[((i) >> 16) & 0xff] & 0xff000000)
-+#define TE432(i) (Te4[((i) >> 8) & 0xff] & 0x00ff0000)
-+#define TE443(i) (Te4[(i) & 0xff] & 0x0000ff00)
-+#define TE414(i) (Te4[((i) >> 24) & 0xff] & 0x000000ff)
-+#define TE411(i) (Te4[((i) >> 24) & 0xff] & 0xff000000)
-+#define TE422(i) (Te4[((i) >> 16) & 0xff] & 0x00ff0000)
-+#define TE433(i) (Te4[((i) >> 8) & 0xff] & 0x0000ff00)
-+#define TE444(i) (Te4[(i) & 0xff] & 0x000000ff)
-+#define TE4(i) (Te4[(i)] & 0x000000ff)
-+
-+#define TD0(i) Td0[((i) >> 24) & 0xff]
-+#define TD1(i) Td1[((i) >> 16) & 0xff]
-+#define TD2(i) Td2[((i) >> 8) & 0xff]
-+#define TD3(i) Td3[(i) & 0xff]
-+#define TD41(i) (Td4[((i) >> 24) & 0xff] & 0xff000000)
-+#define TD42(i) (Td4[((i) >> 16) & 0xff] & 0x00ff0000)
-+#define TD43(i) (Td4[((i) >> 8) & 0xff] & 0x0000ff00)
-+#define TD44(i) (Td4[(i) & 0xff] & 0x000000ff)
-+#define TD0_(i) Td0[(i) & 0xff]
-+#define TD1_(i) Td1[(i) & 0xff]
-+#define TD2_(i) Td2[(i) & 0xff]
-+#define TD3_(i) Td3[(i) & 0xff]
-+
-+#else /* AES_SMALL_TABLES */
-+
-+#define RCON(i) (rcons[(i)] << 24)
-+
-+static inline u32 rotr(u32 val, int bits)
-+{
-+	return (val >> bits) | (val << (32 - bits));
-+}
-+
-+#define TE0(i) Te0[((i) >> 24) & 0xff]
-+#define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8)
-+#define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16)
-+#define TE3(i) rotr(Te0[(i) & 0xff], 24)
-+#define TE41(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000)
-+#define TE42(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000)
-+#define TE43(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00)
-+#define TE44(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff)
-+#define TE421(i) ((Te0[((i) >> 16) & 0xff] << 8) & 0xff000000)
-+#define TE432(i) (Te0[((i) >> 8) & 0xff] & 0x00ff0000)
-+#define TE443(i) (Te0[(i) & 0xff] & 0x0000ff00)
-+#define TE414(i) ((Te0[((i) >> 24) & 0xff] >> 8) & 0x000000ff)
-+#define TE411(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000)
-+#define TE422(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000)
-+#define TE433(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00)
-+#define TE444(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff)
-+#define TE4(i) ((Te0[(i)] >> 8) & 0x000000ff)
-+
-+#define TD0(i) Td0[((i) >> 24) & 0xff]
-+#define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8)
-+#define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16)
-+#define TD3(i) rotr(Td0[(i) & 0xff], 24)
-+#define TD41(i) (Td4s[((i) >> 24) & 0xff] << 24)
-+#define TD42(i) (Td4s[((i) >> 16) & 0xff] << 16)
-+#define TD43(i) (Td4s[((i) >> 8) & 0xff] << 8)
-+#define TD44(i) (Td4s[(i) & 0xff])
-+#define TD0_(i) Td0[(i) & 0xff]
-+#define TD1_(i) rotr(Td0[(i) & 0xff], 8)
-+#define TD2_(i) rotr(Td0[(i) & 0xff], 16)
-+#define TD3_(i) rotr(Td0[(i) & 0xff], 24)
-+
-+#endif /* AES_SMALL_TABLES */
-+
-+#ifdef _MSC_VER
-+#define SWAP(x) (_lrotl(x, 8) & 0x00ff00ff | _lrotr(x, 8) & 0xff00ff00)
-+#define GETU32(p) SWAP(*((u32 *)(p)))
-+#define PUTU32(ct, st) { *((u32 *)(ct)) = SWAP((st)); }
-+#else
-+#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \
-+((u32)(pt)[2] <<  8) ^ ((u32)(pt)[3]))
-+#define PUTU32(ct, st) { \
-+(ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \
-+(ct)[2] = (u8)((st) >>  8); (ct)[3] = (u8)(st); }
-+#endif
-+
-+#define AES_PRIV_SIZE (4 * 4 * 15 + 4)
-+#define AES_PRIV_NR_POS (4 * 15)
-+
-+int rijndaelKeySetupEnc(u32 rk[], const u8 cipherKey[], int keyBits);
-+
-+#endif /* AES_I_H */
-diff --git a/drivers/staging/rtl8723cs/core/crypto/aes_siv.h b/drivers/staging/rtl8723cs/core/crypto/aes_siv.h
-new file mode 100644
-index 000000000000..fb05d80c1f12
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/aes_siv.h
-@@ -0,0 +1,21 @@
-+/*
-+ * AES SIV (RFC 5297)
-+ * Copyright (c) 2013 Cozybit, Inc.
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#ifndef AES_SIV_H
-+#define AES_SIV_H
-+
-+int aes_siv_encrypt(const u8 *key, size_t key_len,
-+		    const u8 *pw, size_t pwlen,
-+		    size_t num_elem, const u8 *addr[], const size_t *len,
-+		    u8 *out);
-+int aes_siv_decrypt(const u8 *key, size_t key_len,
-+		    const u8 *iv_crypt, size_t iv_c_len,
-+		    size_t num_elem, const u8 *addr[], const size_t *len,
-+		    u8 *out);
-+
-+#endif /* AES_SIV_H */
-diff --git a/drivers/staging/rtl8723cs/core/crypto/aes_wrap.h b/drivers/staging/rtl8723cs/core/crypto/aes_wrap.h
-new file mode 100644
-index 000000000000..b70b1d26e550
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/aes_wrap.h
-@@ -0,0 +1,73 @@
-+/*
-+ * AES-based functions
-+ *
-+ * - AES Key Wrap Algorithm (RFC3394)
-+ * - One-Key CBC MAC (OMAC1) hash with AES-128 and AES-256
-+ * - AES-128/192/256 CTR mode encryption
-+ * - AES-128 EAX mode encryption/decryption
-+ * - AES-128 CBC
-+ * - AES-GCM
-+ * - AES-CCM
-+ *
-+ * Copyright (c) 2003-2012, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#ifndef AES_WRAP_H
-+#define AES_WRAP_H
-+
-+int __must_check aes_wrap(const u8 *kek, size_t kek_len, int n, const u8 *plain,
-+			  u8 *cipher);
-+int __must_check aes_unwrap(const u8 *kek, size_t kek_len, int n,
-+			    const u8 *cipher, u8 *plain);
-+int __must_check omac1_aes_vector(const u8 *key, size_t key_len,
-+				  size_t num_elem, const u8 *addr[],
-+				  const size_t *len, u8 *mac);
-+int __must_check omac1_aes_128_vector(const u8 *key, size_t num_elem,
-+				      const u8 *addr[], const size_t *len,
-+				      u8 *mac);
-+int __must_check omac1_aes_128(const u8 *key, const u8 *data, size_t data_len,
-+			       u8 *mac);
-+int __must_check omac1_aes_256(const u8 *key, const u8 *data, size_t data_len,
-+			       u8 *mac);
-+int __must_check aes_128_encrypt_block(const u8 *key, const u8 *in, u8 *out);
-+int __must_check aes_ctr_encrypt(const u8 *key, size_t key_len, const u8 *nonce,
-+				 u8 *data, size_t data_len);
-+int __must_check aes_128_ctr_encrypt(const u8 *key, const u8 *nonce,
-+				     u8 *data, size_t data_len);
-+int __must_check aes_128_eax_encrypt(const u8 *key,
-+				     const u8 *nonce, size_t nonce_len,
-+				     const u8 *hdr, size_t hdr_len,
-+				     u8 *data, size_t data_len, u8 *tag);
-+int __must_check aes_128_eax_decrypt(const u8 *key,
-+				     const u8 *nonce, size_t nonce_len,
-+				     const u8 *hdr, size_t hdr_len,
-+				     u8 *data, size_t data_len, const u8 *tag);
-+int __must_check aes_128_cbc_encrypt(const u8 *key, const u8 *iv, u8 *data,
-+				     size_t data_len);
-+int __must_check aes_128_cbc_decrypt(const u8 *key, const u8 *iv, u8 *data,
-+				     size_t data_len);
-+int __must_check aes_gcm_ae(const u8 *key, size_t key_len,
-+			    const u8 *iv, size_t iv_len,
-+			    const u8 *plain, size_t plain_len,
-+			    const u8 *aad, size_t aad_len,
-+			    u8 *crypt, u8 *tag);
-+int __must_check aes_gcm_ad(const u8 *key, size_t key_len,
-+			    const u8 *iv, size_t iv_len,
-+			    const u8 *crypt, size_t crypt_len,
-+			    const u8 *aad, size_t aad_len, const u8 *tag,
-+			    u8 *plain);
-+int __must_check aes_gmac(const u8 *key, size_t key_len,
-+			  const u8 *iv, size_t iv_len,
-+			  const u8 *aad, size_t aad_len, u8 *tag);
-+int __must_check aes_ccm_ae(const u8 *key, size_t key_len, const u8 *nonce,
-+			    size_t M, const u8 *plain, size_t plain_len,
-+			    const u8 *aad, size_t aad_len, u8 *crypt, u8 *auth);
-+int __must_check aes_ccm_ad(const u8 *key, size_t key_len, const u8 *nonce,
-+			    size_t M, const u8 *crypt, size_t crypt_len,
-+			    const u8 *aad, size_t aad_len, const u8 *auth,
-+			    u8 *plain);
-+
-+#endif /* AES_WRAP_H */
-diff --git a/drivers/staging/rtl8723cs/core/crypto/ccmp.c b/drivers/staging/rtl8723cs/core/crypto/ccmp.c
-new file mode 100644
-index 000000000000..10390ac42d32
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/ccmp.c
-@@ -0,0 +1,384 @@
-+/*
-+ * CTR with CBC-MAC Protocol (CCMP)
-+ * Copyright (c) 2010-2012, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#include "rtw_crypto_wrap.h"
-+
-+#include "aes.h"
-+#include "aes_wrap.h"
-+#include "wlancrypto_wrap.h"
-+
-+
-+
-+static void ccmp_aad_nonce(const struct ieee80211_hdr *hdr, const u8 *data,
-+			   u8 *aad, size_t *aad_len, u8 *nonce)
-+{
-+	u16 fc, stype, seq;
-+	int qos = 0, addr4 = 0;
-+	u8 *pos;
-+
-+	nonce[0] = 0;
-+
-+	fc = le_to_host16(hdr->frame_control);
-+	stype = WLAN_FC_GET_STYPE(fc);
-+	if ((fc & (WLAN_FC_TODS | WLAN_FC_FROMDS)) ==
-+	    (WLAN_FC_TODS | WLAN_FC_FROMDS))
-+		addr4 = 1;
-+
-+	if (WLAN_FC_GET_TYPE(fc) == WLAN_FC_TYPE_DATA) {
-+		fc &= ~0x0070; /* Mask subtype bits */
-+		if (stype & WLAN_FC_STYPE_QOS_DATA) {
-+			const u8 *qc;
-+			qos = 1;
-+			fc &= ~WLAN_FC_ORDER;
-+			qc = (const u8 *)hdr + 24;
-+			if (addr4)
-+				qc += ETH_ALEN;
-+			nonce[0] = qc[0] & 0x0f;
-+		}
-+	} else if (WLAN_FC_GET_TYPE(fc) == WLAN_FC_TYPE_MGMT)
-+		nonce[0] |= 0x10; /* Management */
-+
-+	fc &= ~(WLAN_FC_RETRY | WLAN_FC_PWRMGT | WLAN_FC_MOREDATA);
-+	fc |= WLAN_FC_ISWEP;
-+	WPA_PUT_LE16(aad, fc);
-+	pos = aad + 2;
-+	os_memcpy(pos, GetAddr1Ptr((u8 *)hdr), 3 * ETH_ALEN);
-+	pos += 3 * ETH_ALEN;
-+	seq = le_to_host16(hdr->seq_ctrl);
-+	seq &= ~0xfff0; /* Mask Seq#; do not modify Frag# */
-+	WPA_PUT_LE16(pos, seq);
-+	pos += 2;
-+
-+	os_memcpy(pos, (u8 *)hdr + 24, addr4 * ETH_ALEN + qos * 2);
-+	pos += addr4 * ETH_ALEN;
-+	if (qos) {
-+		pos[0] &= ~0x70;
-+		if (1 /* FIX: either device has SPP A-MSDU Capab = 0 */)
-+			pos[0] &= ~0x80;
-+		pos++;
-+		*pos++ = 0x00;
-+	}
-+
-+	*aad_len = pos - aad;
-+
-+	os_memcpy(nonce + 1, hdr->addr2, ETH_ALEN);
-+	nonce[7] = data[7]; /* PN5 */
-+	nonce[8] = data[6]; /* PN4 */
-+	nonce[9] = data[5]; /* PN3 */
-+	nonce[10] = data[4]; /* PN2 */
-+	nonce[11] = data[1]; /* PN1 */
-+	nonce[12] = data[0]; /* PN0 */
-+}
-+
-+
-+static void ccmp_aad_nonce_pv1(const u8 *hdr, const u8 *a1, const u8 *a2,
-+			       const u8 *a3, const u8 *pn,
-+			       u8 *aad, size_t *aad_len, u8 *nonce)
-+{
-+	u16 fc, type;
-+	u8 *pos;
-+
-+	nonce[0] = BIT(5); /* PV1 */
-+	/* TODO: Priority for QMF; 0 is used for Data frames */
-+
-+	fc = WPA_GET_LE16(hdr);
-+	type = (fc & (BIT(2) | BIT(3) | BIT(4))) >> 2;
-+
-+	if (type == 1)
-+		nonce[0] |= 0x10; /* Management */
-+
-+	fc &= ~(BIT(10) | BIT(11) | BIT(13) | BIT(14) | BIT(15));
-+	fc |= BIT(12);
-+	WPA_PUT_LE16(aad, fc);
-+	pos = aad + 2;
-+	if (type == 0 || type == 3) {
-+		const u8 *sc;
-+
-+		os_memcpy(pos, a1, ETH_ALEN);
-+		pos += ETH_ALEN;
-+		os_memcpy(pos, a2, ETH_ALEN);
-+		pos += ETH_ALEN;
-+
-+		if (type == 0) {
-+			/* Either A1 or A2 contains SID */
-+			sc = hdr + 2 + 2 + ETH_ALEN;
-+		} else {
-+			/* Both A1 and A2 contain full addresses */
-+			sc = hdr + 2 + 2 * ETH_ALEN;
-+		}
-+		/* SC with Sequence Number subfield (bits 4-15 of the Sequence
-+		 * Control field) masked to 0. */
-+		*pos++ = *sc & 0x0f;
-+		*pos++ = 0;
-+
-+		if (a3) {
-+			os_memcpy(pos, a3, ETH_ALEN);
-+			pos += ETH_ALEN;
-+		}
-+	}
-+
-+	*aad_len = pos - aad;
-+
-+	os_memcpy(nonce + 1, a2, ETH_ALEN);
-+	nonce[7] = pn[5]; /* PN5 */
-+	nonce[8] = pn[4]; /* PN4 */
-+	nonce[9] = pn[3]; /* PN3 */
-+	nonce[10] = pn[2]; /* PN2 */
-+	nonce[11] = pn[1]; /* PN1 */
-+	nonce[12] = pn[0]; /* PN0 */
-+}
-+
-+
-+u8 * ccmp_decrypt(const u8 *tk, const struct ieee80211_hdr *hdr,
-+		  const u8 *data, size_t data_len, size_t *decrypted_len)
-+{
-+	u8 aad[30], nonce[13];
-+	size_t aad_len;
-+	size_t mlen;
-+	u8 *plain;
-+
-+	if (data_len < 8 + 8)
-+		return NULL;
-+
-+	plain = os_malloc(data_len + AES_BLOCK_SIZE);
-+	if (plain == NULL)
-+		return NULL;
-+
-+	mlen = data_len - 8 - 8;
-+
-+	os_memset(aad, 0, sizeof(aad));
-+	ccmp_aad_nonce(hdr, data, aad, &aad_len, nonce);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP AAD", aad, aad_len);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP nonce", nonce, 13);
-+
-+	if (aes_ccm_ad(tk, 16, nonce, 8, data + 8, mlen, aad, aad_len,
-+		       data + 8 + mlen, plain) < 0) {
-+		u16 seq_ctrl = le_to_host16(hdr->seq_ctrl);
-+		wpa_printf(_MSG_INFO_, "Invalid CCMP MIC in frame: A1=" MACSTR
-+			   " A2=" MACSTR " A3=" MACSTR " seq=%u frag=%u",
-+			   MAC2STR(hdr->addr1), MAC2STR(hdr->addr2),
-+			   MAC2STR(hdr->addr3),
-+			   WLAN_GET_SEQ_SEQ(seq_ctrl),
-+			   WLAN_GET_SEQ_FRAG(seq_ctrl));
-+		rtw_mfree(plain, data_len + AES_BLOCK_SIZE);
-+		return NULL;
-+	}
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP decrypted", plain, mlen);
-+
-+	*decrypted_len = mlen;
-+	return plain;
-+}
-+
-+
-+void ccmp_get_pn(u8 *pn, const u8 *data)
-+{
-+	pn[0] = data[7]; /* PN5 */
-+	pn[1] = data[6]; /* PN4 */
-+	pn[2] = data[5]; /* PN3 */
-+	pn[3] = data[4]; /* PN2 */
-+	pn[4] = data[1]; /* PN1 */
-+	pn[5] = data[0]; /* PN0 */
-+}
-+
-+
-+u8 * ccmp_encrypt(const u8 *tk, u8 *frame, size_t len, size_t hdrlen, u8 *qos,
-+		  u8 *pn, int keyid, size_t *encrypted_len)
-+{
-+	u8 aad[30], nonce[13];
-+	size_t aad_len, plen;
-+	u8 *crypt, *pos, *pdata;
-+	struct ieee80211_hdr *hdr;
-+
-+	if (len < hdrlen || hdrlen < 24)
-+		return NULL;
-+	plen = len - hdrlen;
-+
-+	crypt = os_malloc(hdrlen + 8 + plen + 8 + AES_BLOCK_SIZE);
-+	if (crypt == NULL)
-+		return NULL;
-+
-+	if (pn == NULL) {
-+		os_memcpy(crypt, frame, hdrlen + 8);
-+		hdr = (struct ieee80211_hdr *) crypt;
-+		hdr->frame_control |= host_to_le16(WLAN_FC_ISWEP);
-+		pos = crypt + hdrlen + 8;
-+		pdata = frame + hdrlen + 8;
-+	} else {
-+		os_memcpy(crypt, frame, hdrlen);
-+		hdr = (struct ieee80211_hdr *) crypt;
-+		hdr->frame_control |= host_to_le16(WLAN_FC_ISWEP);
-+		pos = crypt + hdrlen;
-+		*pos++ = pn[5]; /* PN0 */
-+		*pos++ = pn[4]; /* PN1 */
-+		*pos++ = 0x00; /* Rsvd */
-+		*pos++ = 0x20 | (keyid << 6);
-+		*pos++ = pn[3]; /* PN2 */
-+		*pos++ = pn[2]; /* PN3 */
-+		*pos++ = pn[1]; /* PN4 */
-+		*pos++ = pn[0]; /* PN5 */
-+		pdata = frame + hdrlen;
-+	}
-+
-+	os_memset(aad, 0, sizeof(aad));
-+	ccmp_aad_nonce(hdr, crypt + hdrlen, aad, &aad_len, nonce);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP AAD", aad, aad_len);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP nonce", nonce, 13);
-+
-+	if (aes_ccm_ae(tk, 16, nonce, 8, pdata, plen, aad, aad_len,
-+		       pos, pos + plen) < 0) {
-+		rtw_mfree(crypt, hdrlen + 8 + plen + 8 + AES_BLOCK_SIZE);
-+		return NULL;
-+	}
-+
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP encrypted", crypt + hdrlen + 8, plen);
-+
-+	*encrypted_len = hdrlen + 8 + plen + 8;
-+
-+	return crypt;
-+}
-+
-+
-+u8 * ccmp_encrypt_pv1(const u8 *tk, const u8 *a1, const u8 *a2, const u8 *a3,
-+		      const u8 *frame, size_t len,
-+		      size_t hdrlen, const u8 *pn, int keyid,
-+		      size_t *encrypted_len)
-+{
-+	u8 aad[24], nonce[13];
-+	size_t aad_len, plen;
-+	u8 *crypt, *pos;
-+	struct ieee80211_hdr *hdr;
-+
-+	if (len < hdrlen || hdrlen < 12)
-+		return NULL;
-+	plen = len - hdrlen;
-+
-+	crypt = os_malloc(hdrlen + plen + 8 + AES_BLOCK_SIZE);
-+	if (crypt == NULL)
-+		return NULL;
-+
-+	os_memcpy(crypt, frame, hdrlen);
-+	hdr = (struct ieee80211_hdr *) crypt;
-+	hdr->frame_control |= host_to_le16(BIT(12)); /* Protected Frame */
-+	pos = crypt + hdrlen;
-+
-+	os_memset(aad, 0, sizeof(aad));
-+	ccmp_aad_nonce_pv1(crypt, a1, a2, a3, pn, aad, &aad_len, nonce);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP AAD", aad, aad_len);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP nonce", nonce, sizeof(nonce));
-+
-+	if (aes_ccm_ae(tk, 16, nonce, 8, frame + hdrlen, plen, aad, aad_len,
-+		       pos, pos + plen) < 0) {
-+		rtw_mfree(crypt, hdrlen + plen + 8 + AES_BLOCK_SIZE);
-+		return NULL;
-+	}
-+
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP encrypted", crypt + hdrlen, plen);
-+
-+	*encrypted_len = hdrlen + plen + 8;
-+
-+	return crypt;
-+}
-+
-+
-+u8 * ccmp_256_decrypt(const u8 *tk, const struct ieee80211_hdr *hdr,
-+		      const u8 *data, size_t data_len, size_t *decrypted_len)
-+{
-+	u8 aad[30], nonce[13];
-+	size_t aad_len;
-+	size_t mlen;
-+	u8 *plain;
-+
-+	if (data_len < 8 + 16)
-+		return NULL;
-+
-+	plain = os_malloc(data_len + AES_BLOCK_SIZE);
-+	if (plain == NULL)
-+		return NULL;
-+
-+	mlen = data_len - 8 - 16;
-+
-+	os_memset(aad, 0, sizeof(aad));
-+	ccmp_aad_nonce(hdr, data, aad, &aad_len, nonce);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 AAD", aad, aad_len);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 nonce", nonce, 13);
-+
-+	if (aes_ccm_ad(tk, 32, nonce, 16, data + 8, mlen, aad, aad_len,
-+		       data + 8 + mlen, plain) < 0) {
-+		u16 seq_ctrl = le_to_host16(hdr->seq_ctrl);
-+		wpa_printf(_MSG_INFO_, "Invalid CCMP-256 MIC in frame: A1=" MACSTR
-+			   " A2=" MACSTR " A3=" MACSTR " seq=%u frag=%u",
-+			   MAC2STR(hdr->addr1), MAC2STR(hdr->addr2),
-+			   MAC2STR(hdr->addr3),
-+			   WLAN_GET_SEQ_SEQ(seq_ctrl),
-+			   WLAN_GET_SEQ_FRAG(seq_ctrl));
-+		rtw_mfree(plain, data_len + AES_BLOCK_SIZE);
-+		return NULL;
-+	}
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 decrypted", plain, mlen);
-+
-+	*decrypted_len = mlen;
-+	return plain;
-+}
-+
-+
-+u8 * ccmp_256_encrypt(const u8 *tk, u8 *frame, size_t len, size_t hdrlen,
-+		      u8 *qos, u8 *pn, int keyid, size_t *encrypted_len)
-+{
-+	u8 aad[30], nonce[13];
-+	size_t aad_len, plen;
-+	u8 *crypt, *pos, *pdata;
-+	struct ieee80211_hdr *hdr;
-+
-+	if (len < hdrlen || hdrlen < 24)
-+		return NULL;
-+	plen = len - hdrlen;
-+
-+	crypt = os_malloc(hdrlen + 8 + plen + 16 + AES_BLOCK_SIZE);
-+	if (crypt == NULL)
-+		return NULL;
-+
-+	if (pn == NULL) {
-+		os_memcpy(crypt, frame, hdrlen + 8);
-+		hdr = (struct ieee80211_hdr *) crypt;
-+		hdr->frame_control |= host_to_le16(WLAN_FC_ISWEP);
-+		pos = crypt + hdrlen + 8;
-+		pdata = frame + hdrlen + 8;
-+	} else {
-+		os_memcpy(crypt, frame, hdrlen);
-+		hdr = (struct ieee80211_hdr *) crypt;
-+		hdr->frame_control |= host_to_le16(WLAN_FC_ISWEP);
-+		pos = crypt + hdrlen;
-+		*pos++ = pn[5]; /* PN0 */
-+		*pos++ = pn[4]; /* PN1 */
-+		*pos++ = 0x00; /* Rsvd */
-+		*pos++ = 0x20 | (keyid << 6);
-+		*pos++ = pn[3]; /* PN2 */
-+		*pos++ = pn[2]; /* PN3 */
-+		*pos++ = pn[1]; /* PN4 */
-+		*pos++ = pn[0]; /* PN5 */
-+		pdata = frame + hdrlen;
-+	}
-+
-+	os_memset(aad, 0, sizeof(aad));
-+	ccmp_aad_nonce(hdr, crypt + hdrlen, aad, &aad_len, nonce);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 AAD", aad, aad_len);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 nonce", nonce, 13);
-+
-+	if (aes_ccm_ae(tk, 32, nonce, 16, pdata, plen, aad, aad_len,
-+		       pos, pos + plen) < 0) {
-+		rtw_mfree(crypt, hdrlen + 8 + plen + 16 + AES_BLOCK_SIZE);
-+		return NULL;
-+	}
-+
-+	wpa_hexdump(_MSG_EXCESSIVE_, "CCMP-256 encrypted", crypt + hdrlen + 8,
-+		    plen);
-+
-+	*encrypted_len = hdrlen + 8 + plen + 16;
-+
-+	return crypt;
-+}
-diff --git a/drivers/staging/rtl8723cs/core/crypto/gcmp.c b/drivers/staging/rtl8723cs/core/crypto/gcmp.c
-new file mode 100644
-index 000000000000..2d70a2192fed
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/gcmp.c
-@@ -0,0 +1,193 @@
-+/*
-+ * GCM with GMAC Protocol (GCMP)
-+ * Copyright (c) 2012, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#include "rtw_crypto_wrap.h"
-+
-+#include "aes.h"
-+#include "aes_wrap.h"
-+#include "wlancrypto_wrap.h"
-+
-+
-+static void gcmp_aad_nonce(const struct ieee80211_hdr *hdr, const u8 *data,
-+			   u8 *aad, size_t *aad_len, u8 *nonce)
-+{
-+	u16 fc, stype, seq;
-+	int qos = 0, addr4 = 0;
-+	u8 *pos;
-+
-+	fc = le_to_host16(hdr->frame_control);
-+	stype = WLAN_FC_GET_STYPE(fc);
-+	if ((fc & (WLAN_FC_TODS | WLAN_FC_FROMDS)) ==
-+	    (WLAN_FC_TODS | WLAN_FC_FROMDS))
-+		addr4 = 1;
-+
-+	if (WLAN_FC_GET_TYPE(fc) == WLAN_FC_TYPE_DATA) {
-+		fc &= ~0x0070; /* Mask subtype bits */
-+		if (stype & WLAN_FC_STYPE_QOS_DATA) {
-+			const u8 *qc;
-+			qos = 1;
-+			fc &= ~WLAN_FC_ORDER;
-+			qc = (const u8 *)hdr + 24;
-+			if (addr4)
-+				qc += ETH_ALEN;
-+		}
-+	}
-+
-+	fc &= ~(WLAN_FC_RETRY | WLAN_FC_PWRMGT | WLAN_FC_MOREDATA);
-+	WPA_PUT_LE16(aad, fc);
-+	pos = aad + 2;
-+	os_memcpy(pos, GetAddr1Ptr((u8 *)hdr), 3 * ETH_ALEN);
-+	pos += 3 * ETH_ALEN;
-+	seq = le_to_host16(hdr->seq_ctrl);
-+	seq &= ~0xfff0; /* Mask Seq#; do not modify Frag# */
-+	WPA_PUT_LE16(pos, seq);
-+	pos += 2;
-+
-+	wpa_printf(_MSG_INFO_, "pos - aad = %u, qos(%d)\n", (pos - aad), qos);
-+
-+	os_memcpy(pos, (u8 *)hdr + 24, addr4 * ETH_ALEN + qos * 2);
-+	pos += addr4 * ETH_ALEN;
-+	if (qos) {
-+		pos[0] &= ~0x70;
-+		if (1 /* FIX: either device has SPP A-MSDU Capab = 0 */)
-+			pos[0] &= ~0x80;
-+		pos++;
-+		*pos++ = 0x00;
-+	}
-+
-+	wpa_printf(_MSG_INFO_, "pos - aad = %u\n", (pos - aad));
-+	*aad_len = pos - aad;
-+
-+	os_memcpy(nonce, hdr->addr2, ETH_ALEN);
-+	nonce[6] = data[7]; /* PN5 */
-+	nonce[7] = data[6]; /* PN4 */
-+	nonce[8] = data[5]; /* PN3 */
-+	nonce[9] = data[4]; /* PN2 */
-+	nonce[10] = data[1]; /* PN1 */
-+	nonce[11] = data[0]; /* PN0 */
-+}
-+
-+/**
-+ * gcmp_decrypt -
-+ * @tk: the temporal key
-+ * @tk_len: length of @tk
-+ * @hdr: the mac header
-+ * @data: payload after mac header (PN + enc_data + MIC)
-+ * @data_len: length of @data (PN + enc_data + MIC)
-+ * @decrypted_len: length of the data decrypted
-+ */
-+u8 * gcmp_decrypt(const u8 *tk, size_t tk_len, const struct ieee80211_hdr *hdr,
-+		  const u8 *data, size_t data_len, size_t *decrypted_len)
-+{
-+	u8 aad[30], nonce[12], *plain;
-+	size_t aad_len, mlen;
-+	const u8 *m;
-+
-+	if (data_len < 8 + 16)
-+		return NULL;
-+
-+	plain = os_malloc(data_len + AES_BLOCK_SIZE);
-+	if (plain == NULL)
-+		return NULL;
-+
-+	m = data + 8;
-+	mlen = data_len - 8 - 16;
-+
-+	os_memset(aad, 0, sizeof(aad));
-+	gcmp_aad_nonce(hdr, data, aad, &aad_len, nonce);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "GCMP AAD", aad, aad_len);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "GCMP nonce", nonce, sizeof(nonce));
-+
-+	if (aes_gcm_ad(tk, tk_len, nonce, sizeof(nonce), m, mlen, aad, aad_len,
-+		       m + mlen, plain) < 0) {
-+		u16 seq_ctrl = le_to_host16(hdr->seq_ctrl);
-+		wpa_printf(_MSG_INFO_, "Invalid GCMP frame: A1=" MACSTR
-+			   " A2=" MACSTR " A3=" MACSTR " seq=%u frag=%u",
-+			   MAC2STR(hdr->addr1), MAC2STR(hdr->addr2),
-+			   MAC2STR(hdr->addr3),
-+			   WLAN_GET_SEQ_SEQ(seq_ctrl),
-+			   WLAN_GET_SEQ_FRAG(seq_ctrl));
-+		rtw_mfree(plain, data_len + AES_BLOCK_SIZE);
-+		return NULL;
-+	}
-+
-+	*decrypted_len = mlen;
-+	return plain;
-+}
-+
-+/**
-+ * gcmp_encrypt - 
-+ * @tk: the temporal key
-+ * @tk_len: length of @tk
-+ * @frame: the point to mac header, the frame including mac header and payload, 
-+ *         if @pn is NULL, then the frame including pn
-+ * @len: length of @frame 
-+ *         length = mac header + payload
-+ * @hdrlen: length of the mac header
-+ * @qos: pointer to the QOS field of the frame
-+ * @pn: packet number
-+ * @keyid: key id
-+ * @encrypted_len: length of the encrypted frame 
-+ *                 including mac header, pn, payload and MIC
-+ */
-+u8 * gcmp_encrypt(const u8 *tk, size_t tk_len, const u8 *frame, size_t len,
-+		  size_t hdrlen, const u8 *qos,
-+		  const u8 *pn, int keyid, size_t *encrypted_len)
-+{
-+	u8 aad[30], nonce[12], *crypt, *pos;
-+	const u8 *pdata;
-+	size_t aad_len, plen;
-+	struct ieee80211_hdr *hdr;
-+
-+	if (len < hdrlen || hdrlen < 24)
-+		return NULL;
-+	plen = len - hdrlen;
-+
-+	crypt = os_malloc(hdrlen + 8 + plen + 16 + AES_BLOCK_SIZE);
-+	if (crypt == NULL)
-+		return NULL;
-+
-+	if (pn == NULL) {
-+		os_memcpy(crypt, frame, hdrlen + 8);
-+		hdr = (struct ieee80211_hdr *)crypt;
-+		pos = crypt + hdrlen + 8;
-+		pdata = frame + hdrlen + 8;
-+	} else {
-+		os_memcpy(crypt, frame, hdrlen);
-+		hdr = (struct ieee80211_hdr *)crypt;
-+		pos = crypt + hdrlen;
-+
-+		*pos++ = pn[5]; /* PN0 */
-+		*pos++ = pn[4]; /* PN1 */
-+		*pos++ = 0x00; /* Rsvd */
-+		*pos++ = 0x20 | (keyid << 6);
-+		*pos++ = pn[3]; /* PN2 */
-+		*pos++ = pn[2]; /* PN3 */
-+		*pos++ = pn[1]; /* PN4 */
-+		*pos++ = pn[0]; /* PN5 */
-+		pdata = frame + hdrlen;
-+	}
-+
-+	os_memset(aad, 0, sizeof(aad));
-+	gcmp_aad_nonce(hdr, crypt + hdrlen, aad, &aad_len, nonce);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "GCMP AAD", aad, aad_len);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "GCMP nonce", nonce, sizeof(nonce));
-+
-+	if (aes_gcm_ae(tk, tk_len, nonce, sizeof(nonce), pdata, plen,
-+			aad, aad_len, pos, pos + plen) < 0) {
-+		rtw_mfree(crypt, hdrlen + 8 + plen + 16 + AES_BLOCK_SIZE);
-+		return NULL;
-+	}
-+
-+	wpa_hexdump(_MSG_EXCESSIVE_, "GCMP MIC", pos + plen, 16);
-+	wpa_hexdump(_MSG_EXCESSIVE_, "GCMP encrypted", pos, plen);
-+
-+	*encrypted_len = hdrlen + 8 + plen + 16;
-+
-+	return crypt;
-+}
-diff --git a/drivers/staging/rtl8723cs/core/crypto/rtw_crypto_wrap.c b/drivers/staging/rtl8723cs/core/crypto/rtw_crypto_wrap.c
-new file mode 100644
-index 000000000000..8fdb3c903bb7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/rtw_crypto_wrap.c
-@@ -0,0 +1,85 @@
-+#include "rtw_crypto_wrap.h"
-+
-+#ifndef DEBUG_CRYPTO
-+#define DEBUG_CRYPTO 0
-+#endif /* DEBUG_CRYTO */
-+
-+int os_memcmp(const void *s1, const void *s2, size_t n)
-+{
-+	return _rtw_memcmp2(s1, s2, n);
-+}
-+
-+int os_memcmp_const(const void *a, const void *b, size_t len)
-+{
-+	const u8 *aa = a;
-+	const u8 *bb = b;
-+	size_t i;
-+	u8 res;
-+
-+	for (res = 0, i = 0; i < len; i++)
-+		res |= aa[i] ^ bb[i];
-+
-+	return res;
-+}
-+
-+void* os_memdup(const void *src, u32 sz)
-+{
-+	void *r = rtw_malloc(sz);
-+
-+	if (r && src)
-+		_rtw_memcpy(r, src, sz);
-+	return r;
-+}
-+
-+size_t os_strlen(const char *s)
-+{
-+	const char *p = s;
-+	while (*p)
-+		p++;
-+	return p - s;
-+}
-+
-+
-+void forced_memzero(void *ptr, size_t len)
-+{
-+	_rtw_memset(ptr, 0, len);
-+}
-+
-+void bin_clear_free(void *bin, size_t len)
-+{
-+	if (bin) {
-+		forced_memzero(bin, len);
-+		rtw_mfree(bin, len);
-+	}
-+}
-+
-+void wpa_printf(int level, const char *fmt, ...)
-+{
-+#if DEBUG_CRYPTO
-+#define MSG_LEN 100
-+	va_list args;
-+	u8 buf[MSG_LEN] = { 0 };
-+	int err;
-+
-+	va_start(args, fmt);
-+	err = vsnprintf(buf, MSG_LEN, fmt, args);
-+	va_end(args);
-+
-+	RTW_INFO("%s", buf);
-+#undef MSG_LEN
-+#endif /* DEBUG_CRYPTO */
-+}
-+
-+void wpa_hexdump(int level, const char *title, const void *buf, size_t len)
-+{
-+#if DEBUG_CRYPTO
-+	RTW_INFO_DUMP((u8 *)title, buf, len);
-+#endif /* DEBUG_CRYPTO */
-+}
-+
-+void wpa_hexdump_key(int level, const char *title, const void *buf, size_t len)
-+{
-+#if DEBUG_CRYPTO
-+	RTW_INFO_DUMP((u8 *)title, buf, len);
-+#endif /* DEBUG_CRYPTO */
-+}
-diff --git a/drivers/staging/rtl8723cs/core/crypto/rtw_crypto_wrap.h b/drivers/staging/rtl8723cs/core/crypto/rtw_crypto_wrap.h
-new file mode 100644
-index 000000000000..9b64a14194ef
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/rtw_crypto_wrap.h
-@@ -0,0 +1,64 @@
-+#ifndef RTW_CRYTO_WRAP_H
-+#define RTW_CRYTO_WRAP_H
-+
-+#include <drv_types.h>
-+
-+#define TEST_FAIL() 0
-+
-+#define os_memset _rtw_memset
-+#define os_memcpy _rtw_memcpy
-+#define os_malloc rtw_malloc
-+
-+#define le_to_host16 le16_to_cpu
-+#define host_to_le16 cpu_to_le16
-+
-+#define WPA_PUT_LE16 RTW_PUT_LE16
-+#define WPA_GET_LE16 RTW_GET_LE16
-+#define WPA_PUT_LE32 RTW_PUT_LE32
-+#define WPA_GET_LE32 RTW_GET_LE32
-+#define WPA_PUT_LE64 RTW_PUT_LE64
-+#define WPA_GET_LE64 RTW_GET_LE64
-+#define WPA_PUT_BE16 RTW_PUT_BE16
-+#define WPA_GET_BE16 RTW_GET_BE16
-+#define WPA_PUT_BE32 RTW_PUT_BE32
-+#define WPA_GET_BE32 RTW_GET_BE32
-+#define WPA_PUT_BE64 RTW_PUT_BE64
-+#define WPA_GET_BE64 RTW_GET_BE64
-+
-+#ifndef MAC2STR
-+#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
-+#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
-+#endif
-+
-+#define WLAN_FC_PVER		0x0003
-+#define WLAN_FC_TODS		0x0100
-+#define WLAN_FC_FROMDS		0x0200
-+#define WLAN_FC_MOREFRAG	0x0400
-+#define WLAN_FC_RETRY		0x0800
-+#define WLAN_FC_PWRMGT		0x1000
-+#define WLAN_FC_MOREDATA	0x2000
-+#define WLAN_FC_ISWEP		0x4000
-+#define WLAN_FC_ORDER		0x8000
-+
-+#define WLAN_FC_TYPE_DATA RTW_IEEE80211_FTYPE_DATA
-+#define WLAN_FC_TYPE_MGMT RTW_IEEE80211_FTYPE_MGMT
-+
-+#define WLAN_FC_STYPE_QOS_DATA RTW_IEEE80211_STYPE_QOS_DATA
-+
-+enum {
-+	_MSG_EXCESSIVE_, _MSG_MSGDUMP_, _MSG_DEBUG_, _MSG_INFO_, _MSG_WARNING_, _MSG_ERROR_
-+};
-+
-+int os_memcmp(const void *s1, const void *s2, size_t n);
-+int os_memcmp_const(const void *a, const void *b, size_t len);
-+void* os_memdup(const void *src, u32 sz);
-+size_t os_strlen(const char *s);
-+
-+void forced_memzero(void *ptr, size_t len);
-+void bin_clear_free(void *bin, size_t len);
-+
-+void wpa_printf(int level, const char *fmt, ...);
-+void wpa_hexdump(int level, const char *title, const void *buf, size_t len);
-+void wpa_hexdump_key(int level, const char *title, const void *buf, size_t len);
-+
-+#endif /* RTW_CRYTO_WRAP_H */
-diff --git a/drivers/staging/rtl8723cs/core/crypto/sha256-internal.c b/drivers/staging/rtl8723cs/core/crypto/sha256-internal.c
-new file mode 100644
-index 000000000000..98228ea3378c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/sha256-internal.c
-@@ -0,0 +1,230 @@
-+/*
-+ * SHA-256 hash implementation and interface functions
-+ * Copyright (c) 2003-2011, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#include "rtw_crypto_wrap.h"
-+
-+//#include "common.h"
-+#include "sha256.h"
-+#include "sha256_i.h"
-+//#include "crypto.h"
-+#include "wlancrypto_wrap.h"
-+
-+
-+/**
-+ * sha256_vector - SHA256 hash for data vector
-+ * @num_elem: Number of elements in the data vector
-+ * @addr: Pointers to the data areas
-+ * @len: Lengths of the data blocks
-+ * @mac: Buffer for the hash
-+ * Returns: 0 on success, -1 of failure
-+ */
-+int sha256_vector(size_t num_elem, const u8 *addr[], const size_t *len,
-+		  u8 *mac)
-+{
-+	struct _sha256_state ctx;
-+	size_t i;
-+
-+	if (TEST_FAIL())
-+		return -1;
-+
-+	_sha256_init(&ctx);
-+	for (i = 0; i < num_elem; i++)
-+		if (sha256_process(&ctx, addr[i], len[i]))
-+			return -1;
-+	if (sha256_done(&ctx, mac))
-+		return -1;
-+	return 0;
-+}
-+
-+
-+/* ===== start - public domain SHA256 implementation ===== */
-+
-+/* This is based on SHA256 implementation in LibTomCrypt that was released into
-+ * public domain by Tom St Denis. */
-+
-+/* the K array */
-+static const unsigned long K[64] = {
-+	0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL,
-+	0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL,
-+	0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL,
-+	0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL,
-+	0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL,
-+	0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL,
-+	0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL,
-+	0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL,
-+	0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL,
-+	0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL,
-+	0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL,
-+	0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL,
-+	0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL
-+};
-+
-+
-+/* Various logical functions */
-+#define RORc(x, y) \
-+( ((((unsigned long) (x) & 0xFFFFFFFFUL) >> (unsigned long) ((y) & 31)) | \
-+   ((unsigned long) (x) << (unsigned long) (32 - ((y) & 31)))) & 0xFFFFFFFFUL)
-+#define Ch(x,y,z)       (z ^ (x & (y ^ z)))
-+#define Maj(x,y,z)      (((x | y) & z) | (x & y))
-+#define S(x, n)         RORc((x), (n))
-+#define R(x, n)         (((x)&0xFFFFFFFFUL)>>(n))
-+#define Sigma0(x)       (S(x, 2) ^ S(x, 13) ^ S(x, 22))
-+#define Sigma1(x)       (S(x, 6) ^ S(x, 11) ^ S(x, 25))
-+#define Gamma0(x)       (S(x, 7) ^ S(x, 18) ^ R(x, 3))
-+#define Gamma1(x)       (S(x, 17) ^ S(x, 19) ^ R(x, 10))
-+#ifndef MIN
-+#define MIN(x, y) (((x) < (y)) ? (x) : (y))
-+#endif
-+
-+/* compress 512-bits */
-+static int sha256_compress(struct _sha256_state *md, unsigned char *buf)
-+{
-+	u32 S[8], W[64], t0, t1;
-+	u32 t;
-+	int i;
-+
-+	/* copy state into S */
-+	for (i = 0; i < 8; i++) {
-+		S[i] = md->state[i];
-+	}
-+
-+	/* copy the state into 512-bits into W[0..15] */
-+	for (i = 0; i < 16; i++)
-+		W[i] = WPA_GET_BE32(buf + (4 * i));
-+
-+	/* fill W[16..63] */
-+	for (i = 16; i < 64; i++) {
-+		W[i] = Gamma1(W[i - 2]) + W[i - 7] + Gamma0(W[i - 15]) +
-+			W[i - 16];
-+	}
-+
-+	/* Compress */
-+#define RND(a,b,c,d,e,f,g,h,i)                          \
-+	t0 = h + Sigma1(e) + Ch(e, f, g) + K[i] + W[i];	\
-+	t1 = Sigma0(a) + Maj(a, b, c);			\
-+	d += t0;					\
-+	h  = t0 + t1;
-+
-+	for (i = 0; i < 64; ++i) {
-+		RND(S[0], S[1], S[2], S[3], S[4], S[5], S[6], S[7], i);
-+		t = S[7]; S[7] = S[6]; S[6] = S[5]; S[5] = S[4];
-+		S[4] = S[3]; S[3] = S[2]; S[2] = S[1]; S[1] = S[0]; S[0] = t;
-+	}
-+
-+	/* feedback */
-+	for (i = 0; i < 8; i++) {
-+		md->state[i] = md->state[i] + S[i];
-+	}
-+	return 0;
-+}
-+
-+
-+/* Initialize the hash state */
-+void _sha256_init(struct _sha256_state *md)
-+{
-+	md->curlen = 0;
-+	md->length = 0;
-+	md->state[0] = 0x6A09E667UL;
-+	md->state[1] = 0xBB67AE85UL;
-+	md->state[2] = 0x3C6EF372UL;
-+	md->state[3] = 0xA54FF53AUL;
-+	md->state[4] = 0x510E527FUL;
-+	md->state[5] = 0x9B05688CUL;
-+	md->state[6] = 0x1F83D9ABUL;
-+	md->state[7] = 0x5BE0CD19UL;
-+}
-+
-+/**
-+   Process a block of memory though the hash
-+   @param md     The hash state
-+   @param in     The data to hash
-+   @param inlen  The length of the data (octets)
-+   @return CRYPT_OK if successful
-+*/
-+int sha256_process(struct _sha256_state *md, const unsigned char *in,
-+		   unsigned long inlen)
-+{
-+	unsigned long n;
-+
-+	if (md->curlen >= sizeof(md->buf))
-+		return -1;
-+
-+	while (inlen > 0) {
-+		if (md->curlen == 0 && inlen >= SHA256_BLOCK_SIZE) {
-+			if (sha256_compress(md, (unsigned char *) in) < 0)
-+				return -1;
-+			md->length += SHA256_BLOCK_SIZE * 8;
-+			in += SHA256_BLOCK_SIZE;
-+			inlen -= SHA256_BLOCK_SIZE;
-+		} else {
-+			n = MIN(inlen, (SHA256_BLOCK_SIZE - md->curlen));
-+			os_memcpy(md->buf + md->curlen, in, n);
-+			md->curlen += n;
-+			in += n;
-+			inlen -= n;
-+			if (md->curlen == SHA256_BLOCK_SIZE) {
-+				if (sha256_compress(md, md->buf) < 0)
-+					return -1;
-+				md->length += 8 * SHA256_BLOCK_SIZE;
-+				md->curlen = 0;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+
-+/**
-+   Terminate the hash to get the digest
-+   @param md  The hash state
-+   @param out [out] The destination of the hash (32 bytes)
-+   @return CRYPT_OK if successful
-+*/
-+int sha256_done(struct _sha256_state *md, unsigned char *out)
-+{
-+	int i;
-+
-+	if (md->curlen >= sizeof(md->buf))
-+		return -1;
-+
-+	/* increase the length of the message */
-+	md->length += md->curlen * 8;
-+
-+	/* append the '1' bit */
-+	md->buf[md->curlen++] = (unsigned char) 0x80;
-+
-+	/* if the length is currently above 56 bytes we append zeros
-+	 * then compress.  Then we can fall back to padding zeros and length
-+	 * encoding like normal.
-+	 */
-+	if (md->curlen > 56) {
-+		while (md->curlen < SHA256_BLOCK_SIZE) {
-+			md->buf[md->curlen++] = (unsigned char) 0;
-+		}
-+		sha256_compress(md, md->buf);
-+		md->curlen = 0;
-+	}
-+
-+	/* pad up to 56 bytes of zeroes */
-+	while (md->curlen < 56) {
-+		md->buf[md->curlen++] = (unsigned char) 0;
-+	}
-+
-+	/* store length */
-+	WPA_PUT_BE64(md->buf + 56, md->length);
-+	sha256_compress(md, md->buf);
-+
-+	/* copy output */
-+	for (i = 0; i < 8; i++)
-+		WPA_PUT_BE32(out + (4 * i), md->state[i]);
-+
-+	return 0;
-+}
-+
-+/* ===== end - public domain SHA256 implementation ===== */
-diff --git a/drivers/staging/rtl8723cs/core/crypto/sha256-prf.c b/drivers/staging/rtl8723cs/core/crypto/sha256-prf.c
-new file mode 100644
-index 000000000000..642b38ff618c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/sha256-prf.c
-@@ -0,0 +1,109 @@
-+/*
-+ * SHA256-based PRF (IEEE 802.11r)
-+ * Copyright (c) 2003-2016, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#include "rtw_crypto_wrap.h"
-+
-+//#include "common.h"
-+#include "sha256.h"
-+//#include "crypto.h"
-+#include "wlancrypto_wrap.h"
-+
-+
-+/**
-+ * sha256_prf - SHA256-based Pseudo-Random Function (IEEE 802.11r, 8.5.1.5.2)
-+ * @key: Key for PRF
-+ * @key_len: Length of the key in bytes
-+ * @label: A unique label for each purpose of the PRF
-+ * @data: Extra data to bind into the key
-+ * @data_len: Length of the data
-+ * @buf: Buffer for the generated pseudo-random key
-+ * @buf_len: Number of bytes of key to generate
-+ * Returns: 0 on success, -1 on failure
-+ *
-+ * This function is used to derive new, cryptographically separate keys from a
-+ * given key.
-+ */
-+int sha256_prf(const u8 *key, size_t key_len, const char *label,
-+		const u8 *data, size_t data_len, u8 *buf, size_t buf_len)
-+{
-+	return sha256_prf_bits(key, key_len, label, data, data_len, buf,
-+			       buf_len * 8);
-+}
-+
-+
-+/**
-+ * sha256_prf_bits - IEEE Std 802.11-2012, 11.6.1.7.2 Key derivation function
-+ * @key: Key for KDF
-+ * @key_len: Length of the key in bytes
-+ * @label: A unique label for each purpose of the PRF
-+ * @data: Extra data to bind into the key
-+ * @data_len: Length of the data
-+ * @buf: Buffer for the generated pseudo-random key
-+ * @buf_len: Number of bits of key to generate
-+ * Returns: 0 on success, -1 on failure
-+ *
-+ * This function is used to derive new, cryptographically separate keys from a
-+ * given key. If the requested buf_len is not divisible by eight, the least
-+ * significant 1-7 bits of the last octet in the output are not part of the
-+ * requested output.
-+ */
-+int sha256_prf_bits(const u8 *key, size_t key_len, const char *label,
-+		    const u8 *data, size_t data_len, u8 *buf,
-+		    size_t buf_len_bits)
-+{
-+	u16 counter = 1;
-+	size_t pos, plen;
-+	u8 hash[SHA256_MAC_LEN];
-+	const u8 *addr[4];
-+	size_t len[4];
-+	u8 counter_le[2], length_le[2];
-+	size_t buf_len = (buf_len_bits + 7) / 8;
-+
-+	addr[0] = counter_le;
-+	len[0] = 2;
-+	addr[1] = (u8 *) label;
-+	len[1] = os_strlen(label);
-+	addr[2] = data;
-+	len[2] = data_len;
-+	addr[3] = length_le;
-+	len[3] = sizeof(length_le);
-+
-+	WPA_PUT_LE16(length_le, buf_len_bits);
-+	pos = 0;
-+	while (pos < buf_len) {
-+		plen = buf_len - pos;
-+		WPA_PUT_LE16(counter_le, counter);
-+		if (plen >= SHA256_MAC_LEN) {
-+			if (hmac_sha256_vector(key, key_len, 4, addr, len,
-+					       &buf[pos]) < 0)
-+				return -1;
-+			pos += SHA256_MAC_LEN;
-+		} else {
-+			if (hmac_sha256_vector(key, key_len, 4, addr, len,
-+					       hash) < 0)
-+				return -1;
-+			os_memcpy(&buf[pos], hash, plen);
-+			pos += plen;
-+			break;
-+		}
-+		counter++;
-+	}
-+
-+	/*
-+	 * Mask out unused bits in the last octet if it does not use all the
-+	 * bits.
-+	 */
-+	if (buf_len_bits % 8) {
-+		u8 mask = 0xff << (8 - buf_len_bits % 8);
-+		buf[pos - 1] &= mask;
-+	}
-+
-+	forced_memzero(hash, sizeof(hash));
-+
-+	return 0;
-+}
-diff --git a/drivers/staging/rtl8723cs/core/crypto/sha256.c b/drivers/staging/rtl8723cs/core/crypto/sha256.c
-new file mode 100644
-index 000000000000..ea5d9e3f2dd6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/sha256.c
-@@ -0,0 +1,104 @@
-+/*
-+ * SHA-256 hash implementation and interface functions
-+ * Copyright (c) 2003-2012, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#include "rtw_crypto_wrap.h"
-+
-+#include "sha256.h"
-+//#include "crypto.h"
-+#include "wlancrypto_wrap.h"
-+
-+
-+/**
-+ * hmac_sha256_vector - HMAC-SHA256 over data vector (RFC 2104)
-+ * @key: Key for HMAC operations
-+ * @key_len: Length of the key in bytes
-+ * @num_elem: Number of elements in the data vector
-+ * @addr: Pointers to the data areas
-+ * @len: Lengths of the data blocks
-+ * @mac: Buffer for the hash (32 bytes)
-+ * Returns: 0 on success, -1 on failure
-+ */
-+int hmac_sha256_vector(const u8 *key, size_t key_len, size_t num_elem,
-+		       const u8 *addr[], const size_t *len, u8 *mac)
-+{
-+	unsigned char k_pad[64]; /* padding - key XORd with ipad/opad */
-+	unsigned char tk[32];
-+	const u8 *_addr[6];
-+	size_t _len[6], i;
-+
-+	if (num_elem > 5) {
-+		/*
-+		 * Fixed limit on the number of fragments to avoid having to
-+		 * allocate memory (which could fail).
-+		 */
-+		return -1;
-+	}
-+
-+        /* if key is longer than 64 bytes reset it to key = SHA256(key) */
-+        if (key_len > 64) {
-+		if (sha256_vector(1, &key, &key_len, tk) < 0)
-+			return -1;
-+		key = tk;
-+		key_len = 32;
-+        }
-+
-+	/* the HMAC_SHA256 transform looks like:
-+	 *
-+	 * SHA256(K XOR opad, SHA256(K XOR ipad, text))
-+	 *
-+	 * where K is an n byte key
-+	 * ipad is the byte 0x36 repeated 64 times
-+	 * opad is the byte 0x5c repeated 64 times
-+	 * and text is the data being protected */
-+
-+	/* start out by storing key in ipad */
-+	os_memset(k_pad, 0, sizeof(k_pad));
-+	os_memcpy(k_pad, key, key_len);
-+	/* XOR key with ipad values */
-+	for (i = 0; i < 64; i++)
-+		k_pad[i] ^= 0x36;
-+
-+	/* perform inner SHA256 */
-+	_addr[0] = k_pad;
-+	_len[0] = 64;
-+	for (i = 0; i < num_elem; i++) {
-+		_addr[i + 1] = addr[i];
-+		_len[i + 1] = len[i];
-+	}
-+	if (sha256_vector(1 + num_elem, _addr, _len, mac) < 0)
-+		return -1;
-+
-+	os_memset(k_pad, 0, sizeof(k_pad));
-+	os_memcpy(k_pad, key, key_len);
-+	/* XOR key with opad values */
-+	for (i = 0; i < 64; i++)
-+		k_pad[i] ^= 0x5c;
-+
-+	/* perform outer SHA256 */
-+	_addr[0] = k_pad;
-+	_len[0] = 64;
-+	_addr[1] = mac;
-+	_len[1] = SHA256_MAC_LEN;
-+	return sha256_vector(2, _addr, _len, mac);
-+}
-+
-+
-+/**
-+ * hmac_sha256 - HMAC-SHA256 over data buffer (RFC 2104)
-+ * @key: Key for HMAC operations
-+ * @key_len: Length of the key in bytes
-+ * @data: Pointers to the data area
-+ * @data_len: Length of the data area
-+ * @mac: Buffer for the hash (32 bytes)
-+ * Returns: 0 on success, -1 on failure
-+ */
-+int hmac_sha256(const u8 *key, size_t key_len, const u8 *data,
-+		size_t data_len, u8 *mac)
-+{
-+	return hmac_sha256_vector(key, key_len, 1, &data, &data_len, mac);
-+}
-diff --git a/drivers/staging/rtl8723cs/core/crypto/sha256.h b/drivers/staging/rtl8723cs/core/crypto/sha256.h
-new file mode 100644
-index 000000000000..5219022edd7d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/sha256.h
-@@ -0,0 +1,30 @@
-+/*
-+ * SHA256 hash implementation and interface functions
-+ * Copyright (c) 2003-2016, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#ifndef SHA256_H
-+#define SHA256_H
-+
-+#define SHA256_MAC_LEN 32
-+
-+int hmac_sha256_vector(const u8 *key, size_t key_len, size_t num_elem,
-+		       const u8 *addr[], const size_t *len, u8 *mac);
-+int hmac_sha256(const u8 *key, size_t key_len, const u8 *data,
-+		size_t data_len, u8 *mac);
-+int sha256_prf(const u8 *key, size_t key_len, const char *label,
-+	       const u8 *data, size_t data_len, u8 *buf, size_t buf_len);
-+int sha256_prf_bits(const u8 *key, size_t key_len, const char *label,
-+		    const u8 *data, size_t data_len, u8 *buf,
-+		    size_t buf_len_bits);
-+void tls_prf_sha256(const u8 *secret, size_t secret_len,
-+		    const char *label, const u8 *seed, size_t seed_len,
-+		    u8 *out, size_t outlen);
-+int hmac_sha256_kdf(const u8 *secret, size_t secret_len,
-+		    const char *label, const u8 *seed, size_t seed_len,
-+		    u8 *out, size_t outlen);
-+
-+#endif /* SHA256_H */
-diff --git a/drivers/staging/rtl8723cs/core/crypto/sha256_i.h b/drivers/staging/rtl8723cs/core/crypto/sha256_i.h
-new file mode 100644
-index 000000000000..11ddd6b14716
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/sha256_i.h
-@@ -0,0 +1,25 @@
-+/*
-+ * SHA-256 internal definitions
-+ * Copyright (c) 2003-2011, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#ifndef SHA256_I_H
-+#define SHA256_I_H
-+
-+#define SHA256_BLOCK_SIZE 64
-+
-+struct _sha256_state {
-+	u64 length;
-+	u32 state[8], curlen;
-+	u8 buf[SHA256_BLOCK_SIZE];
-+};
-+
-+void _sha256_init(struct _sha256_state *md);
-+int sha256_process(struct _sha256_state *md, const unsigned char *in,
-+		   unsigned long inlen);
-+int sha256_done(struct _sha256_state *md, unsigned char *out);
-+
-+#endif /* SHA256_I_H */
-diff --git a/drivers/staging/rtl8723cs/core/crypto/wlancrypto_wrap.h b/drivers/staging/rtl8723cs/core/crypto/wlancrypto_wrap.h
-new file mode 100644
-index 000000000000..e331d036bb49
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/crypto/wlancrypto_wrap.h
-@@ -0,0 +1,34 @@
-+/*
-+ * wlantest - IEEE 802.11 protocol monitoring and testing tool
-+ * Copyright (c) 2010-2013, Jouni Malinen <j@w1.fi>
-+ *
-+ * This software may be distributed under the terms of the BSD license.
-+ * See README for more details.
-+ */
-+
-+#ifndef WLANCRYPTO_WRAP_H
-+#define WLANCRYPTO_WRAP_H
-+
-+int sha256_vector(size_t num_elem, const u8 *addr[], const size_t *len,
-+	u8 *mac);
-+
-+u8* ccmp_decrypt(const u8 *tk, const struct ieee80211_hdr *hdr,
-+	const u8 *data, size_t data_len, size_t *decrypted_len);
-+u8* ccmp_encrypt(const u8 *tk, u8 *frame, size_t len, size_t hdrlen, u8 *qos,
-+	u8 *pn, int keyid, size_t *encrypted_len);
-+u8* ccmp_encrypt_pv1(const u8 *tk, const u8 *a1, const u8 *a2, const u8 *a3,
-+	const u8 *frame, size_t len,
-+	size_t hdrlen, const u8 *pn, int keyid,
-+	size_t *encrypted_len);
-+u8* ccmp_256_decrypt(const u8 *tk, const struct ieee80211_hdr *hdr,
-+	const u8 *data, size_t data_len, size_t *decrypted_len);
-+u8* ccmp_256_encrypt(const u8 *tk, u8 *frame, size_t len, size_t hdrlen,
-+	u8 *qos, u8 *pn, int keyid, size_t *encrypted_len);
-+
-+u8* gcmp_decrypt(const u8 *tk, size_t tk_len, const struct ieee80211_hdr *hdr,
-+	const u8 *data, size_t data_len, size_t *decrypted_len);
-+u8* gcmp_encrypt(const u8 *tk, size_t tk_len, const u8 *frame, size_t len,
-+	size_t hdrlen, const u8 *qos,
-+	const u8 *pn, int keyid, size_t *encrypted_len);
-+
-+#endif /* WLANCRYPTO_WRAP_H */
-diff --git a/drivers/staging/rtl8723cs/core/efuse/rtw_efuse.c b/drivers/staging/rtl8723cs/core/efuse/rtw_efuse.c
-new file mode 100644
-index 000000000000..fe414c6766a7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/efuse/rtw_efuse.c
-@@ -0,0 +1,3575 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_EFUSE_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#include "../hal/efuse/efuse_mask.h"
-+
-+/*------------------------Define local variable------------------------------*/
-+u8	fakeEfuseBank = {0};
-+u32	fakeEfuseUsedBytes = {0};
-+u8	fakeEfuseContent[EFUSE_MAX_HW_SIZE] = {0};
-+u8	fakeEfuseInitMap[EFUSE_MAX_MAP_LEN] = {0};
-+u8	fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN] = {0};
-+
-+u32	BTEfuseUsedBytes = {0};
-+u8	BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
-+u8	BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN] = {0};
-+u8	BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN] = {0};
-+
-+u32	fakeBTEfuseUsedBytes = {0};
-+u8	fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
-+u8	fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN] = {0};
-+u8	fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN] = {0};
-+
-+u8	maskfileBuffer[64];
-+u8	btmaskfileBuffer[64];
-+
-+/*------------------------Define local variable------------------------------*/
-+BOOLEAN rtw_file_efuse_IsMasked(PADAPTER pAdapter, u16 Offset, u8 *maskbuf)
-+{
-+	int r = Offset / 16;
-+	int c = (Offset % 16) / 2;
-+	int result = 0;
-+
-+	if (pAdapter->registrypriv.boffefusemask)
-+		return FALSE;
-+
-+	if (c < 4) /* Upper double word */
-+		result = (maskbuf[r] & (0x10 << c));
-+	else
-+		result = (maskbuf[r] & (0x01 << (c - 4)));
-+
-+	return (result > 0) ? 0 : 1;
-+}
-+
-+BOOLEAN efuse_IsBT_Masked(PADAPTER pAdapter, u16 Offset)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
-+
-+	if (pAdapter->registrypriv.boffefusemask)
-+		return FALSE;
-+
-+#ifdef CONFIG_BT_EFUSE_MASK
-+#ifdef CONFIG_RTL8822C
-+#ifdef CONFIG_USB_HCI
-+	if (IS_HARDWARE_TYPE_8822C(pAdapter))
-+		return (IS_BT_MASKED(8822C, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+	if (IS_HARDWARE_TYPE_8822C(pAdapter))
-+		return (IS_BT_MASKED(8822C, _MPCIE, Offset)) ? TRUE : FALSE;
-+#endif
-+#ifdef CONFIG_SDIO_HCI
-+	if (IS_HARDWARE_TYPE_8822C(pAdapter))
-+		return (IS_BT_MASKED(8822C, _MSDIO, Offset)) ? TRUE : FALSE;
-+#endif
-+#endif /*#ifdef CONFIG_RTL8822C*/
-+#endif /* CONFIG_BT_EFUSE_MASK */
-+	return FALSE;
-+}
-+
-+void rtw_bt_efuse_mask_array(PADAPTER pAdapter, u8 *pArray)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
-+
-+#ifdef CONFIG_BT_EFUSE_MASK
-+#ifdef CONFIG_RTL8822C
-+#ifdef CONFIG_USB_HCI
-+if (IS_HARDWARE_TYPE_8822CU(pAdapter))
-+		GET_BT_MASK_ARRAY(8822C, _MUSB, pArray);
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+	if (IS_HARDWARE_TYPE_8822CE(pAdapter))
-+		GET_BT_MASK_ARRAY(8822C, _MPCIE, pArray);
-+#endif
-+#ifdef CONFIG_SDIO_HCI
-+	if (IS_HARDWARE_TYPE_8822CS(pAdapter))
-+		GET_BT_MASK_ARRAY(8822C, _MSDIO, pArray);
-+#endif
-+#endif /*#ifdef CONFIG_RTL8822C*/
-+#endif /* CONFIG_BT_EFUSE_MASK */
-+
-+}
-+
-+u16 rtw_get_bt_efuse_mask_arraylen(PADAPTER pAdapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+
-+#ifdef CONFIG_BT_EFUSE_MASK
-+#ifdef CONFIG_RTL8822C
-+#ifdef CONFIG_USB_HCI
-+	if (IS_HARDWARE_TYPE_8822CU(pAdapter))
-+		return GET_BT_MASK_ARRAY_LEN(8822C, _MUSB);
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+	if (IS_HARDWARE_TYPE_8822CE(pAdapter))
-+		return GET_BT_MASK_ARRAY_LEN(8822C, _MPCIE);
-+#endif
-+#ifdef CONFIG_SDIO_HCI
-+	if (IS_HARDWARE_TYPE_8822CS(pAdapter))
-+		return GET_BT_MASK_ARRAY_LEN(8822C, _MSDIO);
-+#endif
-+#endif /*#ifdef CONFIG_RTL8822C*/
-+#endif /* CONFIG_BT_EFUSE_MASK */
-+
-+	return 0;
-+}
-+
-+BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset)
-+{
-+
-+	if (pAdapter->registrypriv.boffefusemask)
-+		return FALSE;
-+
-+#ifdef CONFIG_USB_HCI
-+#if defined(CONFIG_RTL8188E)
-+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
-+		return (IS_MASKED(8188E, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8812A)
-+	if (IS_HARDWARE_TYPE_8812(pAdapter))
-+		return (IS_MASKED(8812A, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8821A)
-+#if 0
-+	if (IS_HARDWARE_TYPE_8811AU(pAdapter))
-+		return (IS_MASKED(8811A, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+	if (IS_HARDWARE_TYPE_8821(pAdapter))
-+		return (IS_MASKED(8821A, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8192E)
-+	if (IS_HARDWARE_TYPE_8192E(pAdapter))
-+		return (IS_MASKED(8192E, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8723B)
-+	if (IS_HARDWARE_TYPE_8723B(pAdapter))
-+		return (IS_MASKED(8723B, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8703B)
-+	if (IS_HARDWARE_TYPE_8703B(pAdapter))
-+		return (IS_MASKED(8703B, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8814A)
-+	if (IS_HARDWARE_TYPE_8814A(pAdapter))
-+		return (IS_MASKED(8814A, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8188F)
-+	if (IS_HARDWARE_TYPE_8188F(pAdapter))
-+		return (IS_MASKED(8188F, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8188GTV)
-+	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
-+		return (IS_MASKED(8188GTV, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8822B)
-+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
-+		return (IS_MASKED(8822B, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8723D)
-+	if (IS_HARDWARE_TYPE_8723D(pAdapter))
-+		return (IS_MASKED(8723D, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8710B)
-+	if (IS_HARDWARE_TYPE_8710B(pAdapter))
-+		return (IS_MASKED(8710B, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8821C)
-+	if (IS_HARDWARE_TYPE_8821CU(pAdapter))
-+		return (IS_MASKED(8821C, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+
-+#if defined(CONFIG_RTL8192F)
-+	if (IS_HARDWARE_TYPE_8192FU(pAdapter))
-+		return (IS_MASKED(8192F, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8822C)
-+	if (IS_HARDWARE_TYPE_8822C(pAdapter))
-+		return (IS_MASKED(8822C, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8814B)
-+	if (IS_HARDWARE_TYPE_8814B(pAdapter))
-+		return (IS_MASKED(8814B, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8723F)
-+	if (IS_HARDWARE_TYPE_8723F(pAdapter))
-+		return (IS_MASKED(8723F, _MUSB, Offset)) ? TRUE : FALSE;
-+#endif
-+#endif /*CONFIG_USB_HCI*/
-+
-+#ifdef CONFIG_PCI_HCI
-+#if defined(CONFIG_RTL8188E)
-+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
-+		return (IS_MASKED(8188E, _MPCIE, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8192E)
-+	if (IS_HARDWARE_TYPE_8192E(pAdapter))
-+		return (IS_MASKED(8192E, _MPCIE, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8812A)
-+	if (IS_HARDWARE_TYPE_8812(pAdapter))
-+		return (IS_MASKED(8812A, _MPCIE, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8821A)
-+	if (IS_HARDWARE_TYPE_8821(pAdapter))
-+		return (IS_MASKED(8821A, _MPCIE, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8723B)
-+	if (IS_HARDWARE_TYPE_8723B(pAdapter))
-+		return (IS_MASKED(8723B, _MPCIE, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8814A)
-+	if (IS_HARDWARE_TYPE_8814A(pAdapter))
-+		return (IS_MASKED(8814A, _MPCIE, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8822B)
-+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
-+		return (IS_MASKED(8822B, _MPCIE, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8821C)
-+	if (IS_HARDWARE_TYPE_8821CE(pAdapter))
-+		return (IS_MASKED(8821C, _MPCIE, Offset)) ? TRUE : FALSE;
-+#endif
-+
-+#if defined(CONFIG_RTL8192F)
-+	if (IS_HARDWARE_TYPE_8192FE(pAdapter))
-+		return (IS_MASKED(8192F, _MPCIE, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8822C)
-+	if (IS_HARDWARE_TYPE_8822C(pAdapter))
-+		return (IS_MASKED(8822C, _MPCIE, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8814B)
-+	if (IS_HARDWARE_TYPE_8814B(pAdapter))
-+		return (IS_MASKED(8814B, _MPCIE, Offset)) ? TRUE : FALSE;
-+#endif
-+#endif /*CONFIG_PCI_HCI*/
-+
-+#ifdef CONFIG_SDIO_HCI
-+#ifdef CONFIG_RTL8188E_SDIO
-+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
-+		return (IS_MASKED(8188E, _MSDIO, Offset)) ? TRUE : FALSE;
-+#endif
-+#ifdef CONFIG_RTL8723B
-+	if (IS_HARDWARE_TYPE_8723BS(pAdapter))
-+		return (IS_MASKED(8723B, _MSDIO, Offset)) ? TRUE : FALSE;
-+#endif
-+#ifdef CONFIG_RTL8188F
-+	if (IS_HARDWARE_TYPE_8188F(pAdapter))
-+		return (IS_MASKED(8188F, _MSDIO, Offset)) ? TRUE : FALSE;
-+#endif
-+#ifdef CONFIG_RTL8188GTV
-+	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
-+		return (IS_MASKED(8188GTV, _MSDIO, Offset)) ? TRUE : FALSE;
-+#endif
-+#ifdef CONFIG_RTL8192E
-+	if (IS_HARDWARE_TYPE_8192ES(pAdapter))
-+		return (IS_MASKED(8192E, _MSDIO, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8821A)
-+	if (IS_HARDWARE_TYPE_8821S(pAdapter))
-+		return (IS_MASKED(8821A, _MSDIO, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8821C)
-+	if (IS_HARDWARE_TYPE_8821CS(pAdapter))
-+		return (IS_MASKED(8821C, _MSDIO, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8822B)
-+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
-+		return (IS_MASKED(8822B, _MSDIO, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8192F)
-+	if (IS_HARDWARE_TYPE_8192FS(pAdapter))
-+		return (IS_MASKED(8192F, _MSDIO, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8822C)
-+	if (IS_HARDWARE_TYPE_8822C(pAdapter))
-+		return (IS_MASKED(8822C, _MSDIO, Offset)) ? TRUE : FALSE;
-+#endif
-+#if defined(CONFIG_RTL8723F)
-+	if (IS_HARDWARE_TYPE_8723F(pAdapter))
-+		return (IS_MASKED(8723F, _MSDIO, Offset)) ? TRUE : FALSE;
-+#endif
-+#endif /*CONFIG_SDIO_HCI*/
-+
-+	return FALSE;
-+}
-+
-+void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray)
-+{
-+
-+#ifdef CONFIG_USB_HCI
-+#if defined(CONFIG_RTL8188E)
-+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
-+		GET_MASK_ARRAY(8188E, _MUSB, pArray);
-+#endif
-+#if defined(CONFIG_RTL8812A)
-+	if (IS_HARDWARE_TYPE_8812(pAdapter))
-+		GET_MASK_ARRAY(8812A, _MUSB, pArray);
-+#endif
-+#if defined(CONFIG_RTL8821A)
-+	if (IS_HARDWARE_TYPE_8821(pAdapter))
-+		GET_MASK_ARRAY(8821A, _MUSB, pArray);
-+#endif
-+#if defined(CONFIG_RTL8192E)
-+	if (IS_HARDWARE_TYPE_8192E(pAdapter))
-+		GET_MASK_ARRAY(8192E, _MUSB, pArray);
-+#endif
-+#if defined(CONFIG_RTL8723B)
-+	if (IS_HARDWARE_TYPE_8723B(pAdapter))
-+		GET_MASK_ARRAY(8723B, _MUSB, pArray);
-+#endif
-+#if defined(CONFIG_RTL8703B)
-+	if (IS_HARDWARE_TYPE_8703B(pAdapter))
-+		GET_MASK_ARRAY(8703B, _MUSB, pArray);
-+#endif
-+#if defined(CONFIG_RTL8188F)
-+	if (IS_HARDWARE_TYPE_8188F(pAdapter))
-+		GET_MASK_ARRAY(8188F, _MUSB, pArray);
-+#endif
-+#if defined(CONFIG_RTL8188GTV)
-+	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
-+		GET_MASK_ARRAY(8188GTV, _MUSB, pArray);
-+#endif
-+#if defined(CONFIG_RTL8814A)
-+	if (IS_HARDWARE_TYPE_8814A(pAdapter))
-+		GET_MASK_ARRAY(8814A, _MUSB, pArray);
-+#endif
-+#if defined(CONFIG_RTL8822B)
-+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
-+		GET_MASK_ARRAY(8822B, _MUSB, pArray);
-+#endif
-+#if defined(CONFIG_RTL8821C)
-+	if (IS_HARDWARE_TYPE_8821CU(pAdapter))
-+		GET_MASK_ARRAY(8821C, _MUSB, pArray);
-+#endif
-+#if defined(CONFIG_RTL8192F)
-+	if (IS_HARDWARE_TYPE_8192FU(pAdapter))
-+		GET_MASK_ARRAY(8192F, _MUSB, pArray);
-+#endif
-+#if defined(CONFIG_RTL8822C)
-+	if (IS_HARDWARE_TYPE_8822C(pAdapter))
-+		GET_MASK_ARRAY(8822C, _MUSB, pArray);
-+#endif
-+#if defined(CONFIG_RTL8814B)
-+	if (IS_HARDWARE_TYPE_8814B(pAdapter))
-+		GET_MASK_ARRAY(8814B, _MUSB, pArray);
-+#endif
-+#if defined(CONFIG_RTL8723F)
-+	if (IS_HARDWARE_TYPE_8723F(pAdapter))
-+		GET_MASK_ARRAY(8723F, _MUSB, pArray);
-+#endif
-+#endif /*CONFIG_USB_HCI*/
-+
-+#ifdef CONFIG_PCI_HCI
-+#if defined(CONFIG_RTL8188E)
-+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
-+		GET_MASK_ARRAY(8188E, _MPCIE, pArray);
-+#endif
-+#if defined(CONFIG_RTL8192E)
-+	if (IS_HARDWARE_TYPE_8192E(pAdapter))
-+		GET_MASK_ARRAY(8192E, _MPCIE, pArray);
-+#endif
-+#if defined(CONFIG_RTL8812A)
-+	if (IS_HARDWARE_TYPE_8812(pAdapter))
-+		GET_MASK_ARRAY(8812A, _MPCIE, pArray);
-+#endif
-+#if defined(CONFIG_RTL8821A)
-+	if (IS_HARDWARE_TYPE_8821(pAdapter))
-+		GET_MASK_ARRAY(8821A, _MPCIE, pArray);
-+#endif
-+#if defined(CONFIG_RTL8723B)
-+	if (IS_HARDWARE_TYPE_8723B(pAdapter))
-+		GET_MASK_ARRAY(8723B, _MPCIE, pArray);
-+#endif
-+#if defined(CONFIG_RTL8814A)
-+	if (IS_HARDWARE_TYPE_8814A(pAdapter))
-+		GET_MASK_ARRAY(8814A, _MPCIE, pArray);
-+#endif
-+#if defined(CONFIG_RTL8822B)
-+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
-+		GET_MASK_ARRAY(8822B, _MPCIE, pArray);
-+#endif
-+#if defined(CONFIG_RTL8821C)
-+	if (IS_HARDWARE_TYPE_8821CE(pAdapter))
-+		GET_MASK_ARRAY(8821C, _MPCIE, pArray);
-+#endif
-+#if defined(CONFIG_RTL8192F)
-+	if (IS_HARDWARE_TYPE_8192FE(pAdapter))
-+		GET_MASK_ARRAY(8192F, _MPCIE, pArray);
-+#endif
-+#if defined(CONFIG_RTL8822C)
-+	if (IS_HARDWARE_TYPE_8822C(pAdapter))
-+		GET_MASK_ARRAY(8822C, _MPCIE, pArray);
-+#endif
-+#if defined(CONFIG_RTL8814B)
-+	if (IS_HARDWARE_TYPE_8814B(pAdapter))
-+		GET_MASK_ARRAY(8814B, _MPCIE, pArray);
-+#endif
-+#endif /*CONFIG_PCI_HCI*/
-+
-+#ifdef CONFIG_SDIO_HCI
-+#if defined(CONFIG_RTL8188E)
-+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
-+		GET_MASK_ARRAY(8188E, _MSDIO, pArray);
-+#endif
-+#if defined(CONFIG_RTL8723B)
-+	if (IS_HARDWARE_TYPE_8723BS(pAdapter))
-+		GET_MASK_ARRAY(8723B, _MSDIO, pArray);
-+#endif
-+#if defined(CONFIG_RTL8188F)
-+	if (IS_HARDWARE_TYPE_8188F(pAdapter))
-+		GET_MASK_ARRAY(8188F, _MSDIO, pArray);
-+#endif
-+#if defined(CONFIG_RTL8188GTV)
-+	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
-+		GET_MASK_ARRAY(8188GTV, _MSDIO, pArray);
-+#endif
-+#if defined(CONFIG_RTL8192E)
-+	if (IS_HARDWARE_TYPE_8192ES(pAdapter))
-+		GET_MASK_ARRAY(8192E, _MSDIO, pArray);
-+#endif
-+#if defined(CONFIG_RTL8821A)
-+	if (IS_HARDWARE_TYPE_8821S(pAdapter))
-+		GET_MASK_ARRAY(8821A, _MSDIO, pArray);
-+#endif
-+#if defined(CONFIG_RTL8821C)
-+	if (IS_HARDWARE_TYPE_8821CS(pAdapter))
-+		GET_MASK_ARRAY(8821C , _MSDIO, pArray);
-+#endif
-+#if defined(CONFIG_RTL8822B)
-+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
-+		GET_MASK_ARRAY(8822B , _MSDIO, pArray);
-+#endif
-+#if defined(CONFIG_RTL8192F)
-+	if (IS_HARDWARE_TYPE_8192FS(pAdapter))
-+		GET_MASK_ARRAY(8192F, _MSDIO, pArray);
-+#endif
-+#if defined(CONFIG_RTL8822C)
-+	if (IS_HARDWARE_TYPE_8822C(pAdapter))
-+		GET_MASK_ARRAY(8822C , _MSDIO, pArray);
-+#endif
-+#if defined(CONFIG_RTL8723F)
-+	if (IS_HARDWARE_TYPE_8723F(pAdapter))
-+		GET_MASK_ARRAY(8723F, _MSDIO, pArray);
-+#endif
-+#endif /*CONFIG_SDIO_HCI*/
-+}
-+
-+u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter)
-+{
-+
-+#ifdef CONFIG_USB_HCI
-+#if defined(CONFIG_RTL8188E)
-+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8188E, _MUSB);
-+#endif
-+#if defined(CONFIG_RTL8812A)
-+	if (IS_HARDWARE_TYPE_8812(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8812A, _MUSB);
-+#endif
-+#if defined(CONFIG_RTL8821A)
-+	if (IS_HARDWARE_TYPE_8821(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8821A, _MUSB);
-+#endif
-+#if defined(CONFIG_RTL8192E)
-+	if (IS_HARDWARE_TYPE_8192E(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8192E, _MUSB);
-+#endif
-+#if defined(CONFIG_RTL8723B)
-+	if (IS_HARDWARE_TYPE_8723B(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8723B, _MUSB);
-+#endif
-+#if defined(CONFIG_RTL8703B)
-+	if (IS_HARDWARE_TYPE_8703B(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8703B, _MUSB);
-+#endif
-+#if defined(CONFIG_RTL8188F)
-+	if (IS_HARDWARE_TYPE_8188F(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8188F, _MUSB);
-+#endif
-+#if defined(CONFIG_RTL8188GTV)
-+	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8188GTV, _MUSB);
-+#endif
-+#if defined(CONFIG_RTL8814A)
-+	if (IS_HARDWARE_TYPE_8814A(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8814A, _MUSB);
-+#endif
-+#if defined(CONFIG_RTL8822B)
-+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8822B, _MUSB);
-+#endif
-+#if defined(CONFIG_RTL8821C)
-+	if (IS_HARDWARE_TYPE_8821CU(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8821C, _MUSB);
-+#endif
-+#if defined(CONFIG_RTL8192F)
-+	if (IS_HARDWARE_TYPE_8192FU(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8192F, _MUSB);
-+#endif
-+#if defined(CONFIG_RTL8822C)
-+	if (IS_HARDWARE_TYPE_8822C(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8822C, _MUSB);
-+#endif
-+#if defined(CONFIG_RTL8814B)
-+	if (IS_HARDWARE_TYPE_8814B(pAdapter)) {
-+		return GET_MASK_ARRAY_LEN(8814B, _MUSB);
-+	}
-+#endif
-+#if defined(CONFIG_RTL8723F)
-+	if (IS_HARDWARE_TYPE_8723F(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8723F, _MUSB);
-+#endif
-+#endif /*CONFIG_USB_HCI*/
-+
-+#ifdef CONFIG_PCI_HCI
-+#if defined(CONFIG_RTL8188E)
-+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8188E, _MPCIE);
-+#endif
-+#if defined(CONFIG_RTL8192E)
-+	if (IS_HARDWARE_TYPE_8192E(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8192E, _MPCIE);
-+#endif
-+#if defined(CONFIG_RTL8812A)
-+	if (IS_HARDWARE_TYPE_8812(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8812A, _MPCIE);
-+#endif
-+#if defined(CONFIG_RTL8821A)
-+	if (IS_HARDWARE_TYPE_8821(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8821A, _MPCIE);
-+#endif
-+#if defined(CONFIG_RTL8723B)
-+	if (IS_HARDWARE_TYPE_8723B(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8723B, _MPCIE);
-+#endif
-+#if defined(CONFIG_RTL8814A)
-+	if (IS_HARDWARE_TYPE_8814A(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8814A, _MPCIE);
-+#endif
-+#if defined(CONFIG_RTL8822B)
-+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8822B, _MPCIE);
-+#endif
-+#if defined(CONFIG_RTL8821C)
-+	if (IS_HARDWARE_TYPE_8821CE(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8821C, _MPCIE);
-+#endif
-+#if defined(CONFIG_RTL8192F)
-+	if (IS_HARDWARE_TYPE_8192FE(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8192F, _MPCIE);
-+#endif
-+#if defined(CONFIG_RTL8822C)
-+	if (IS_HARDWARE_TYPE_8822C(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8822C, _MPCIE);
-+#endif
-+#if defined(CONFIG_RTL8814B)
-+	if (IS_HARDWARE_TYPE_8814B(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8814B, _MPCIE);
-+#endif
-+#endif /*CONFIG_PCI_HCI*/
-+
-+#ifdef CONFIG_SDIO_HCI
-+#if defined(CONFIG_RTL8188E)
-+	if (IS_HARDWARE_TYPE_8188E(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8188E, _MSDIO);
-+#endif
-+#if defined(CONFIG_RTL8723B)
-+	if (IS_HARDWARE_TYPE_8723BS(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8723B, _MSDIO);
-+#endif
-+#if defined(CONFIG_RTL8188F)
-+	if (IS_HARDWARE_TYPE_8188F(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8188F, _MSDIO);
-+#endif
-+#if defined(CONFIG_RTL8188GTV)
-+	if (IS_HARDWARE_TYPE_8188GTV(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8188GTV, _MSDIO);
-+#endif
-+#if defined(CONFIG_RTL8192E)
-+	if (IS_HARDWARE_TYPE_8192ES(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8192E, _MSDIO);
-+#endif
-+#if defined(CONFIG_RTL8821A)
-+	if (IS_HARDWARE_TYPE_8821S(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8821A, _MSDIO);
-+#endif
-+#if defined(CONFIG_RTL8821C)
-+	if (IS_HARDWARE_TYPE_8821CS(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8821C, _MSDIO);
-+#endif
-+#if defined(CONFIG_RTL8822B)
-+	if (IS_HARDWARE_TYPE_8822B(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8822B, _MSDIO);
-+#endif
-+#if defined(CONFIG_RTL8192F)
-+	if (IS_HARDWARE_TYPE_8192FS(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8192F, _MSDIO);
-+#endif
-+#if defined(CONFIG_RTL8822C)
-+	if (IS_HARDWARE_TYPE_8822C(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8822C, _MSDIO);
-+#endif
-+#if defined(CONFIG_RTL8723F)
-+	if (IS_HARDWARE_TYPE_8723F(pAdapter))
-+		return GET_MASK_ARRAY_LEN(8723F, _MSDIO);
-+#endif
-+#endif/*CONFIG_SDIO_HCI*/
-+	return 0;
-+}
-+
-+static void rtw_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
-+{
-+	u16 i = 0;
-+
-+	if (padapter->registrypriv.boffefusemask == 0) {
-+		for (i = 0; i < cnts; i++) {
-+			if (padapter->registrypriv.bFileMaskEfuse == _TRUE) {
-+					if (rtw_file_efuse_IsMasked(padapter, addr + i, maskfileBuffer)) /*use file efuse mask.*/
-+						data[i] = 0xff;
-+					else
-+						RTW_DBG("data[%x] = %x\n", i, data[i]);
-+			} else {
-+					if (efuse_IsMasked(padapter, addr + i))
-+						data[i] = 0xff;
-+					else
-+						RTW_DBG("data[%x] = %x\n", i, data[i]);
-+			}
-+		}
-+	}
-+}
-+
-+u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
-+{
-+	u8	ret = _SUCCESS;
-+	u16	mapLen = 0;
-+
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
-+
-+	ret = rtw_efuse_map_read(padapter, addr, cnts , data);
-+
-+	rtw_mask_map_read(padapter, addr, cnts , data);
-+
-+	return ret;
-+
-+}
-+
-+/* ***********************************************************
-+ *				Efuse related code
-+ * *********************************************************** */
-+static u8 hal_EfuseSwitchToBank(
-+	PADAPTER	padapter,
-+	u8			bank,
-+	u8			bPseudoTest)
-+{
-+	u8 bRet = _FALSE;
-+	u32 value32 = 0;
-+#ifdef HAL_EFUSE_MEMORY
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+	PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
-+#endif
-+
-+
-+	RTW_INFO("%s: Efuse switch bank to %d\n", __FUNCTION__, bank);
-+	if (bPseudoTest) {
-+#ifdef HAL_EFUSE_MEMORY
-+		pEfuseHal->fakeEfuseBank = bank;
-+#else
-+		fakeEfuseBank = bank;
-+#endif
-+		bRet = _TRUE;
-+	} else {
-+		value32 = rtw_read32(padapter, 0x34);
-+		bRet = _TRUE;
-+		switch (bank) {
-+		case 0:
-+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
-+			break;
-+		case 1:
-+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);
-+			break;
-+		case 2:
-+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);
-+			break;
-+		case 3:
-+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);
-+			break;
-+		default:
-+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
-+			bRet = _FALSE;
-+			break;
-+		}
-+		rtw_write32(padapter, 0x34, value32);
-+	}
-+
-+	return bRet;
-+}
-+
-+void rtw_efuse_analyze(PADAPTER	padapter, u8 Type, u8 Fake)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	PEFUSE_HAL		pEfuseHal = &(pHalData->EfuseHal);
-+	u16	eFuse_Addr = 0;
-+	u8 offset, wden;
-+	u16	 i, j;
-+	u8	efuseHeader = 0, efuseExtHdr = 0, efuseData[EFUSE_MAX_WORD_UNIT*2] = {0}, dataCnt = 0;
-+	u16	efuseHeader2Byte = 0;
-+	u8	*eFuseWord = NULL;// [EFUSE_MAX_SECTION_NUM][EFUSE_MAX_WORD_UNIT];
-+	u8	offset_2_0 = 0;
-+	u8	pgSectionCnt = 0;
-+	u8	wd_cnt = 0;
-+	u8	max_section = 64;
-+	u16	mapLen = 0, maprawlen = 0;
-+	boolean	bExtHeader = _FALSE;
-+	u8	efuseType = EFUSE_WIFI;
-+	boolean	bPseudoTest = _FALSE;
-+	u8	bank = 0, startBank = 0, endBank = 1-1;
-+	boolean	bCheckNextBank = FALSE;
-+	u8	protectBytesBank = 0;
-+	u16	efuse_max = 0;
-+	u8	ParseEfuseExtHdr, ParseEfuseHeader, ParseOffset, ParseWDEN, ParseOffset2_0;
-+
-+	eFuseWord = rtw_zmalloc(EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));
-+
-+	if (eFuseWord == NULL) {
-+		RTW_INFO("%s:rtw_zmalloc eFuseWord = NULL !!\n", __func__);
-+		return;
-+	}
-+
-+	RTW_INFO("\n");
-+	if (Type == 0) {
-+		if (Fake == 0) {
-+			RTW_INFO("\n\tEFUSE_Analyze Wifi Content\n");
-+			efuseType = EFUSE_WIFI;
-+			bPseudoTest = FALSE;
-+			startBank = 0;
-+			endBank = 0;
-+		} else {
-+			RTW_INFO("\n\tEFUSE_Analyze Wifi Pseudo Content\n");
-+			efuseType = EFUSE_WIFI;
-+			bPseudoTest = TRUE;
-+			startBank = 0;
-+			endBank = 0;
-+		}
-+	} else {
-+		if (Fake == 0) {
-+			RTW_INFO("\n\tEFUSE_Analyze BT Content\n");
-+			efuseType = EFUSE_BT;
-+			bPseudoTest = FALSE;
-+			startBank = 1;
-+			endBank = EFUSE_MAX_BANK - 1;
-+		} else {
-+			RTW_INFO("\n\tEFUSE_Analyze BT Pseudo Content\n");
-+			efuseType = EFUSE_BT;
-+			bPseudoTest = TRUE;
-+			startBank = 1;
-+			endBank = EFUSE_MAX_BANK - 1;
-+			if (IS_HARDWARE_TYPE_8821(padapter))
-+				endBank = 3 - 1;/*EFUSE_MAX_BANK_8821A - 1;*/
-+		}
-+	}
-+
-+	RTW_INFO("\n\r 1Byte header, [7:4]=offset, [3:0]=word enable\n");
-+	RTW_INFO("\n\r 2Byte header, header[7:5]=offset[2:0], header[4:0]=0x0F\n");
-+	RTW_INFO("\n\r 2Byte header, extHeader[7:4]=offset[6:3], extHeader[3:0]=word enable\n");
-+
-+	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, bPseudoTest);
-+	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAX_SECTION, (void *)&max_section, bPseudoTest);
-+	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_PROTECT_BYTES_BANK, (void *)&protectBytesBank, bPseudoTest);
-+	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, (void *)&efuse_max, bPseudoTest);
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (void *)&maprawlen, _FALSE);
-+
-+	_rtw_memset(eFuseWord, 0xff, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));
-+	_rtw_memset(pEfuseHal->fakeEfuseInitMap, 0xff, EFUSE_MAX_MAP_LEN);
-+
-+	if (IS_HARDWARE_TYPE_8821(padapter))
-+		endBank = 3 - 1;/*EFUSE_MAX_BANK_8821A - 1;*/
-+
-+	for (bank = startBank; bank <= endBank; bank++) {
-+		if (!hal_EfuseSwitchToBank(padapter, bank, bPseudoTest)) {
-+			RTW_INFO("EFUSE_SwitchToBank() Fail!!\n");
-+			goto out_free_buffer;
-+		}
-+
-+		eFuse_Addr = bank * EFUSE_MAX_BANK_SIZE;
-+
-+		efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
-+
-+		if (efuseHeader == 0xFF && bank == startBank && Fake != TRUE) {
-+			RTW_INFO("Non-PGed Efuse\n");
-+			goto out_free_buffer;
-+		}
-+		RTW_INFO("EFUSE_REAL_CONTENT_LEN = %d\n", maprawlen);
-+
-+		while ((efuseHeader != 0xFF) && ((efuseType == EFUSE_WIFI && (eFuse_Addr < maprawlen)) || (efuseType == EFUSE_BT && (eFuse_Addr < (endBank + 1) * EFUSE_MAX_BANK_SIZE)))) {
-+
-+			RTW_INFO("Analyzing: Offset: 0x%X\n", eFuse_Addr);
-+
-+			/* Check PG header for section num.*/
-+			if (EXT_HEADER(efuseHeader)) {
-+				bExtHeader = TRUE;
-+				offset_2_0 = GET_HDR_OFFSET_2_0(efuseHeader);
-+				efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
-+
-+				if (efuseExtHdr != 0xff) {
-+					if (ALL_WORDS_DISABLED(efuseExtHdr)) {
-+						/* Read next pg header*/
-+						efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
-+						continue;
-+					} else {
-+						offset = ((efuseExtHdr & 0xF0) >> 1) | offset_2_0;
-+						wden = (efuseExtHdr & 0x0F);
-+						efuseHeader2Byte = (efuseExtHdr<<8)|efuseHeader;
-+						RTW_INFO("Find efuseHeader2Byte = 0x%04X, offset=%d, wden=0x%x\n",
-+										efuseHeader2Byte, offset, wden);
-+					}
-+				} else {
-+					RTW_INFO("Error, efuse[%d]=0xff, efuseExtHdr=0xff\n", eFuse_Addr-1);
-+					break;
-+				}
-+			} else {
-+				offset = ((efuseHeader >> 4) & 0x0f);
-+				wden = (efuseHeader & 0x0f);
-+			}
-+
-+			_rtw_memset(efuseData, '\0', EFUSE_MAX_WORD_UNIT * 2);
-+			dataCnt = 0;
-+
-+			if (offset < max_section) {
-+				for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
-+					/* Check word enable condition in the section	*/
-+					if (!(wden & (0x01<<i))) {
-+						if (!((efuseType == EFUSE_WIFI && (eFuse_Addr + 2 < maprawlen)) ||
-+								(efuseType == EFUSE_BT && (eFuse_Addr + 2 < (endBank + 1) * EFUSE_MAX_BANK_SIZE)))) {
-+							RTW_INFO("eFuse_Addr exceeds, break\n");
-+							break;
-+						}
-+						efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData[dataCnt++], bPseudoTest);
-+						eFuseWord[(offset * 8) + (i * 2)] = (efuseData[dataCnt - 1]);
-+						efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData[dataCnt++], bPseudoTest);
-+						eFuseWord[(offset * 8) + (i * 2 + 1)] = (efuseData[dataCnt - 1]);
-+					}
-+				}
-+			}
-+
-+			if (bExtHeader) {
-+				RTW_INFO("Efuse PG Section (%d) = ", pgSectionCnt);
-+				RTW_INFO("[ %04X ], [", efuseHeader2Byte);
-+
-+			} else {
-+				RTW_INFO("Efuse PG Section (%d) = ", pgSectionCnt);
-+				RTW_INFO("[ %02X ], [", efuseHeader);
-+			}
-+
-+			for (j = 0; j < dataCnt; j++)
-+				RTW_INFO(" %02X ", efuseData[j]);
-+
-+			RTW_INFO("]\n");
-+
-+
-+			if (bExtHeader) {
-+				ParseEfuseExtHdr = (efuseHeader2Byte & 0xff00) >> 8;
-+				ParseEfuseHeader = (efuseHeader2Byte & 0xff);
-+				ParseOffset2_0 = GET_HDR_OFFSET_2_0(ParseEfuseHeader);
-+				ParseOffset = ((ParseEfuseExtHdr & 0xF0) >> 1) | ParseOffset2_0;
-+				ParseWDEN = (ParseEfuseExtHdr & 0x0F);
-+				RTW_INFO("Header=0x%x, ExtHeader=0x%x, ", ParseEfuseHeader, ParseEfuseExtHdr);
-+			} else {
-+				ParseEfuseHeader = efuseHeader;
-+				ParseOffset = ((ParseEfuseHeader >> 4) & 0x0f);
-+				ParseWDEN = (ParseEfuseHeader & 0x0f);
-+				RTW_INFO("Header=0x%x, ", ParseEfuseHeader);
-+			}
-+			RTW_INFO("offset=0x%x(%d), word enable=0x%x\n", ParseOffset, ParseOffset, ParseWDEN);
-+
-+			wd_cnt = 0;
-+			for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
-+				if (!(wden & (0x01 << i))) {
-+					RTW_INFO("Map[ %02X ] = %02X %02X\n", ((offset * EFUSE_MAX_WORD_UNIT * 2) + (i * 2)), efuseData[wd_cnt * 2 + 0], efuseData[wd_cnt * 2 + 1]);
-+					wd_cnt++;
-+				}
-+			}
-+
-+			pgSectionCnt++;
-+			bExtHeader = FALSE;
-+			efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
-+			if (efuseHeader == 0xFF) {
-+				if ((eFuse_Addr + protectBytesBank) >= efuse_max)
-+					bCheckNextBank = TRUE;
-+				else
-+					bCheckNextBank = FALSE;
-+			}
-+		}
-+		if (!bCheckNextBank) {
-+			RTW_INFO("Not need to check next bank, eFuse_Addr=%d, protectBytesBank=%d, efuse_max=%d\n",
-+				eFuse_Addr, protectBytesBank, efuse_max);
-+			break;
-+		}
-+	}
-+	/* switch bank back to 0 for BT/wifi later use*/
-+	hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
-+
-+	/* 3. Collect 16 sections and 4 word unit into Efuse map.*/
-+	for (i = 0; i < max_section; i++) {
-+		for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) {
-+			pEfuseHal->fakeEfuseInitMap[(i*8)+(j*2)] = (eFuseWord[(i*8)+(j*2)]);
-+			pEfuseHal->fakeEfuseInitMap[(i*8)+((j*2)+1)] =  (eFuseWord[(i*8)+((j*2)+1)]);
-+		}
-+	}
-+
-+	RTW_INFO("\n\tEFUSE Analyze Map\n");
-+	i = 0;
-+	j = 0;
-+
-+	for (i = 0; i < mapLen; i++) {
-+		if (i % 16 == 0)
-+			RTW_PRINT_SEL(RTW_DBGDUMP, "0x%03x: ", i);
-+
-+		_RTW_PRINT_SEL(RTW_DBGDUMP, "%02X%s"
-+			, pEfuseHal->fakeEfuseInitMap[i]
-+			, ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? "	  " : " ")
-+		);
-+	}
-+	_RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
-+
-+out_free_buffer:
-+	if (eFuseWord)
-+		rtw_mfree((u8 *)eFuseWord, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));
-+}
-+
-+void efuse_PreUpdateAction(
-+	PADAPTER	pAdapter,
-+	u32			*BackupRegs)
-+{
-+	if (IS_HARDWARE_TYPE_8812AU(pAdapter) || IS_HARDWARE_TYPE_8822BU(pAdapter)) {
-+		/* <20131115, Kordan> Turn off Rx to prevent from being busy when writing the EFUSE. (Asked by Chunchu.)*/
-+		BackupRegs[0] = phy_query_mac_reg(pAdapter, REG_RCR, bMaskDWord);
-+		BackupRegs[1] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord);
-+		BackupRegs[2] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord);
-+#ifdef CONFIG_RTL8812A
-+		BackupRegs[3] = phy_query_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord);
-+#endif
-+		PlatformEFIOWrite4Byte(pAdapter, REG_RCR, 0x1);
-+		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0, 0);
-+		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+1, 0);
-+		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+2, 0);
-+		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+3, 0);
-+		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+4, 0);
-+		PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+5, 0);
-+#ifdef CONFIG_RTL8812A
-+		/* <20140410, Kordan> 0x11 = 0x4E, lower down LX_SPS0 voltage. (Asked by Chunchu)*/
-+		phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskByte1, 0x4E);
-+#endif
-+		RTW_INFO(" %s , done\n", __func__);
-+
-+		}
-+}
-+
-+
-+void efuse_PostUpdateAction(
-+	PADAPTER	pAdapter,
-+	u32			*BackupRegs)
-+{
-+	if (IS_HARDWARE_TYPE_8812AU(pAdapter) || IS_HARDWARE_TYPE_8822BU(pAdapter)) {
-+		/* <20131115, Kordan> Turn on Rx and restore the registers. (Asked by Chunchu.)*/
-+		phy_set_mac_reg(pAdapter, REG_RCR, bMaskDWord, BackupRegs[0]);
-+		phy_set_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord, BackupRegs[1]);
-+		phy_set_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord, BackupRegs[2]);
-+#ifdef CONFIG_RTL8812A
-+		phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord, BackupRegs[3]);
-+#endif
-+	RTW_INFO(" %s , done\n", __func__);
-+	}
-+}
-+
-+
-+#ifdef RTW_HALMAC
-+#include "../../hal/hal_halmac.h"
-+
-+void Efuse_PowerSwitch(PADAPTER adapter, u8 write, u8 pwrstate)
-+{
-+}
-+
-+void BTEfuse_PowerSwitch(PADAPTER adapter, u8 write, u8 pwrstate)
-+{
-+}
-+
-+u8 efuse_GetCurrentSize(PADAPTER adapter, u16 *size)
-+{
-+	*size = 0;
-+
-+	return _FAIL;
-+}
-+
-+u16 efuse_GetMaxSize(PADAPTER adapter)
-+{
-+	struct dvobj_priv *d;
-+	u32 size = 0;
-+	int err;
-+
-+	d = adapter_to_dvobj(adapter);
-+	err = rtw_halmac_get_physical_efuse_size(d, &size);
-+	if (err)
-+		return 0;
-+
-+	return size;
-+}
-+
-+u16 efuse_GetavailableSize(PADAPTER adapter)
-+{
-+	struct dvobj_priv *d;
-+	u32 size = 0;
-+	int err;
-+
-+	d = adapter_to_dvobj(adapter);
-+	err = rtw_halmac_get_available_efuse_size(d, &size);
-+	if (err)
-+		return 0;
-+
-+	return size;
-+}
-+
-+
-+u8 efuse_bt_GetCurrentSize(PADAPTER adapter, u16 *usesize)
-+{
-+	u8 *efuse_map;
-+
-+	*usesize = 0;
-+	efuse_map = rtw_malloc(EFUSE_BT_MAP_LEN);
-+	if (efuse_map == NULL) {
-+		RTW_DBG("%s: malloc FAIL\n", __FUNCTION__);
-+		return _FAIL;
-+	}
-+
-+	/* for get bt phy efuse last use byte */
-+	hal_ReadEFuse_BT_logic_map(adapter, 0x00, EFUSE_BT_MAP_LEN, efuse_map);
-+	*usesize = fakeBTEfuseUsedBytes;
-+
-+	if (efuse_map)
-+		rtw_mfree(efuse_map, EFUSE_BT_MAP_LEN);
-+
-+	return _SUCCESS;
-+}
-+
-+u16 efuse_bt_GetMaxSize(PADAPTER adapter)
-+{
-+	return EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK;
-+}
-+
-+void EFUSE_GetEfuseDefinition(PADAPTER adapter, u8 efusetype, u8 type, void *out, BOOLEAN test)
-+{
-+	struct dvobj_priv *d;
-+	u32 v32 = 0;
-+
-+
-+	d = adapter_to_dvobj(adapter);
-+
-+	if (adapter->hal_func.EFUSEGetEfuseDefinition) {
-+		adapter->hal_func.EFUSEGetEfuseDefinition(adapter, efusetype, type, out, test);
-+		return;
-+	}
-+
-+	if (EFUSE_WIFI == efusetype) {
-+		switch (type) {
-+		case TYPE_EFUSE_MAP_LEN:
-+			rtw_halmac_get_logical_efuse_size(d, &v32);
-+			*(u16 *)out = (u16)v32;
-+			return;
-+
-+		case TYPE_EFUSE_REAL_CONTENT_LEN:
-+			rtw_halmac_get_physical_efuse_size(d, &v32);
-+			*(u16 *)out = (u16)v32;
-+			return;
-+		}
-+	} else if (EFUSE_BT == efusetype) {
-+		switch (type) {
-+		case TYPE_EFUSE_MAP_LEN:
-+			*(u16 *)out = EFUSE_BT_MAP_LEN;
-+			return;
-+
-+		case TYPE_EFUSE_REAL_CONTENT_LEN:
-+			*(u16 *)out = EFUSE_BT_REAL_CONTENT_LEN;
-+			return;
-+		}
-+	}
-+}
-+
-+/*
-+ * read/write raw efuse data
-+ */
-+u8 rtw_efuse_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data)
-+{
-+	struct dvobj_priv *d;
-+	u8 *efuse = NULL;
-+	u32 size;
-+	int err;
-+
-+
-+	d = adapter_to_dvobj(adapter);
-+	err = rtw_halmac_get_physical_efuse_size(d, &size);
-+	if (err){
-+		size = EFUSE_MAX_SIZE;
-+		RTW_INFO(" physical_efuse_size err size %d\n", size);
-+	}
-+
-+	if ((addr + cnts) > size)
-+		return _FAIL;
-+
-+	if (_TRUE == write) {
-+		err = rtw_halmac_write_physical_efuse(d, addr, cnts, data);
-+		if (err)
-+			return _FAIL;
-+	} else {
-+		if (cnts > 16)
-+			efuse = rtw_zmalloc(size);
-+
-+		if (efuse) {
-+			err = rtw_halmac_read_physical_efuse_map(d, efuse, size);
-+			if (err) {
-+				rtw_mfree(efuse, size);
-+				return _FAIL;
-+			}
-+
-+			_rtw_memcpy(data, efuse + addr, cnts);
-+			rtw_mfree(efuse, size);
-+		} else {
-+			err = rtw_halmac_read_physical_efuse(d, addr, cnts, data);
-+			if (err)
-+				return _FAIL;
-+		}
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+static inline void dump_buf(u8 *buf, u32 len)
-+{
-+	u32 i;
-+
-+	RTW_INFO("-----------------Len %d----------------\n", len);
-+	for (i = 0; i < len; i++)
-+		printk("%2.2x-", *(buf + i));
-+	printk("\n");
-+}
-+
-+/*
-+ * read/write raw efuse data
-+ */
-+u8 rtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data)
-+{
-+	struct dvobj_priv *d;
-+	u8 *efuse = NULL;
-+	u32 size;
-+	int err = _FAIL;
-+
-+
-+	d = adapter_to_dvobj(adapter);
-+
-+	size = EFUSE_BT_REAL_CONTENT_LEN;
-+
-+	if ((addr + cnts) > size)
-+		return _FAIL;
-+
-+	if (_TRUE == write) {
-+		err = rtw_halmac_write_bt_physical_efuse(d, addr, cnts, data);
-+		if (err == -1) {
-+			RTW_ERR("%s: rtw_halmac_write_bt_physical_efuse fail!\n", __FUNCTION__);
-+			return _FAIL;
-+		}
-+		RTW_INFO("%s: rtw_halmac_write_bt_physical_efuse OK! data 0x%x\n", __FUNCTION__, *data);
-+	} else {
-+		efuse = rtw_zmalloc(size);
-+
-+		if (efuse) {
-+			err = rtw_halmac_read_bt_physical_efuse_map(d, efuse, size);
-+
-+			if (err == -1) {
-+				RTW_ERR("%s: rtw_halmac_read_bt_physical_efuse_map fail!\n", __FUNCTION__);
-+				rtw_mfree(efuse, size);
-+				return _FAIL;
-+			}
-+			dump_buf(efuse + addr, cnts);
-+
-+			_rtw_memcpy(data, efuse + addr, cnts);
-+
-+			RTW_INFO("%s: rtw_halmac_read_bt_physical_efuse_map ok! data 0x%x\n", __FUNCTION__, *data);
-+			rtw_mfree(efuse, size);
-+		}
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+u8 rtw_efuse_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
-+{
-+	struct dvobj_priv *d;
-+	u8 *efuse = NULL;
-+	u32 size, i;
-+	int err;
-+	u32	backupRegs[4] = {0};
-+	u8 status = _SUCCESS;
-+
-+	efuse_PreUpdateAction(adapter, backupRegs);
-+
-+	d = adapter_to_dvobj(adapter);
-+	err = rtw_halmac_get_logical_efuse_size(d, &size);
-+	if (err) {
-+		status = _FAIL;
-+		RTW_DBG("halmac_get_logical_efuse_size fail\n");
-+		goto exit;
-+	}
-+	/* size error handle */
-+	if ((addr + cnts) > size) {
-+		if (addr < size)
-+			cnts = size - addr;
-+		else {
-+			status = _FAIL;
-+			RTW_DBG(" %s() ,addr + cnts) > size fail\n", __func__);
-+			goto exit;
-+		}
-+	}
-+
-+	if (cnts > 16)
-+		efuse = rtw_zmalloc(size);
-+
-+	if (efuse) {
-+		err = rtw_halmac_read_logical_efuse_map(d, efuse, size, NULL, 0);
-+		if (err) {
-+			rtw_mfree(efuse, size);
-+			status = _FAIL;
-+			RTW_DBG(" %s() ,halmac_read_logical_efus map fail\n", __func__);
-+			goto exit;
-+		}
-+
-+		_rtw_memcpy(data, efuse + addr, cnts);
-+		rtw_mfree(efuse, size);
-+	} else {
-+		err = rtw_halmac_read_logical_efuse(d, addr, cnts, data);
-+		if (err) {
-+			status = _FAIL;
-+			RTW_DBG(" %s() ,halmac_read_logical_efus data fail\n", __func__);
-+			goto exit;
-+		}
-+	}
-+	status = _SUCCESS;
-+exit:
-+	efuse_PostUpdateAction(adapter, backupRegs);
-+
-+	return status;
-+}
-+
-+
-+u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
-+{
-+	struct dvobj_priv *d;
-+	u8 *efuse = NULL;
-+	u32 size;
-+	int err;
-+	u8 mask_buf[64] = "";
-+	u16 mask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(adapter);
-+	u32 backupRegs[4] = {0};
-+	u8 status = _SUCCESS;;
-+
-+	efuse_PreUpdateAction(adapter, backupRegs);
-+
-+	d = adapter_to_dvobj(adapter);
-+	err = rtw_halmac_get_logical_efuse_size(d, &size);
-+	if (err) {
-+		status = _FAIL;
-+		goto exit;
-+	}
-+
-+	if ((addr + cnts) > size) {
-+		status = _FAIL;
-+		goto exit;
-+	}
-+
-+	efuse = rtw_zmalloc(size);
-+	if (!efuse) {
-+		status = _FAIL;
-+		goto exit;
-+	}
-+
-+	err = rtw_halmac_read_logical_efuse_map(d, efuse, size, NULL, 0);
-+	if (err) {
-+		rtw_mfree(efuse, size);
-+		status = _FAIL;
-+		goto exit;
-+	}
-+
-+	_rtw_memcpy(efuse + addr, data, cnts);
-+
-+	if (adapter->registrypriv.boffefusemask == 0) {
-+		RTW_INFO("Use mask Array Len: %d\n", mask_len);
-+
-+		if (mask_len != 0) {
-+			if (adapter->registrypriv.bFileMaskEfuse == _TRUE)
-+				_rtw_memcpy(mask_buf, maskfileBuffer, mask_len);
-+			else
-+				rtw_efuse_mask_array(adapter, mask_buf);
-+
-+			err = rtw_halmac_write_logical_efuse_map(d, efuse, size, mask_buf, mask_len);
-+		} else
-+			err = rtw_halmac_write_logical_efuse_map(d, efuse, size, NULL, 0);
-+	} else {
-+		_rtw_memset(mask_buf, 0xFF, sizeof(mask_buf));
-+		RTW_INFO("Efuse mask off\n");
-+		err = rtw_halmac_write_logical_efuse_map(d, efuse, size, mask_buf, size/16);
-+	}
-+
-+	if (err) {
-+		rtw_mfree(efuse, size);
-+		status = _FAIL;
-+		goto exit;
-+	}
-+
-+	rtw_mfree(efuse, size);
-+	status = _SUCCESS;
-+exit :
-+	efuse_PostUpdateAction(adapter, backupRegs);
-+
-+	return status;
-+}
-+
-+int Efuse_PgPacketRead(PADAPTER adapter, u8 offset, u8 *data, BOOLEAN test)
-+{
-+	return _FALSE;
-+}
-+
-+int Efuse_PgPacketWrite(PADAPTER adapter, u8 offset, u8 word_en, u8 *data, BOOLEAN test)
-+{
-+	return _FALSE;
-+}
-+
-+static void rtw_bt_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
-+{
-+	u16 i = 0;
-+
-+#ifdef CONFIG_BT_EFUSE_MASK
-+	if (padapter->registrypriv.boffefusemask == 0) {
-+			for (i = 0; i < cnts; i++) {
-+				if (padapter->registrypriv.bBTFileMaskEfuse == _TRUE) {
-+						if (rtw_file_efuse_IsMasked(padapter, addr + i, btmaskfileBuffer)) /*use BT file efuse mask.*/
-+							data[i] = 0xff;
-+						else
-+							RTW_INFO("data[%x] = %x\n", i, data[i]);
-+				} else {
-+						if (efuse_IsBT_Masked(padapter, addr + i)) /*use drv internal efuse mask.*/
-+							data[i] = 0xff;
-+						else
-+							RTW_INFO("data[%x] = %x\n", i, data[i]);
-+					}
-+			}
-+	}
-+#endif /*CONFIG_BT_EFUSE_MASK*/
-+}
-+
-+u8 rtw_BT_efuse_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
-+{
-+	hal_ReadEFuse_BT_logic_map(adapter, addr, cnts, data);
-+
-+	rtw_bt_mask_map_read(adapter, addr, cnts, data);
-+
-+	return _SUCCESS;
-+}
-+
-+
-+static u16
-+hal_EfuseGetCurrentSize_BT(
-+	PADAPTER	padapter,
-+	u8			bPseudoTest)
-+{
-+#ifdef HAL_EFUSE_MEMORY
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
-+#endif
-+	u16 btusedbytes;
-+	u16	efuse_addr;
-+	u8	bank, startBank;
-+	u8	hoffset = 0, hworden = 0;
-+	u8	efuse_data, word_cnts = 0;
-+	u16	retU2 = 0;
-+
-+
-+	btusedbytes = fakeBTEfuseUsedBytes;
-+
-+	efuse_addr = (u16)((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN));
-+	startBank = (u8)(1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN));
-+
-+	RTW_INFO("%s: start from bank=%d addr=0x%X\n", __FUNCTION__, startBank, efuse_addr);
-+	retU2 = EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK;
-+
-+	for (bank = startBank; bank < 3; bank++) {
-+		if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) {
-+			RTW_ERR("%s: switch bank(%d) Fail!!\n", __FUNCTION__, bank);
-+			/* bank = EFUSE_MAX_BANK; */
-+			break;
-+		}
-+
-+		/* only when bank is switched we have to reset the efuse_addr. */
-+		if (bank != startBank)
-+			efuse_addr = 0;
-+
-+
-+		while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
-+			if (rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &efuse_data) == _FALSE) {
-+				RTW_ERR("%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __FUNCTION__, efuse_addr);
-+				/* bank = EFUSE_MAX_BANK; */
-+				break;
-+			}
-+			RTW_INFO("%s: efuse_OneByteRead ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank);
-+
-+			if (efuse_data == 0xFF)
-+				break;
-+
-+			if (EXT_HEADER(efuse_data)) {
-+				hoffset = GET_HDR_OFFSET_2_0(efuse_data);
-+				efuse_addr++;
-+				rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &efuse_data);
-+				RTW_INFO("%s: efuse_OneByteRead EXT_HEADER ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank);
-+
-+				if (ALL_WORDS_DISABLED(efuse_data)) {
-+					efuse_addr++;
-+					continue;
-+				}
-+
-+				/*				hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); */
-+				hoffset |= ((efuse_data & 0xF0) >> 1);
-+				hworden = efuse_data & 0x0F;
-+			} else {
-+				hoffset = (efuse_data >> 4) & 0x0F;
-+				hworden =  efuse_data & 0x0F;
-+			}
-+
-+			RTW_INFO(FUNC_ADPT_FMT": Offset=%d Worden=%#X\n",
-+				 FUNC_ADPT_ARG(padapter), hoffset, hworden);
-+
-+			word_cnts = Efuse_CalculateWordCnts(hworden);
-+			/* read next header */
-+			efuse_addr += (word_cnts * 2) + 1;
-+		}
-+		/* Check if we need to check next bank efuse */
-+		if (efuse_addr < retU2)
-+			break;/* don't need to check next bank. */
-+	}
-+	retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
-+
-+	fakeBTEfuseUsedBytes = retU2;
-+	RTW_INFO("%s: CurrentSize=%d\n", __FUNCTION__, retU2);
-+	return retU2;
-+}
-+
-+#ifdef CONFIG_RTL8822C
-+void rtw_pre_bt_efuse(PADAPTER padapter)
-+{
-+	char pgdata[4] = {0x72, 0x80, 0x14, 0x90}; /*BT 5M PLL*/
-+	u8 status = 1;
-+	u8 bkmask;
-+	BOOLEAN bt_en;
-+
-+	bkmask = padapter->registrypriv.boffefusemask;
-+	padapter->registrypriv.boffefusemask = 1;
-+
-+	bt_en = rtw_read8(padapter, 0x6A) & BIT2 ? _TRUE : _FALSE;
-+	if (IS_HARDWARE_TYPE_8822C(padapter) && bt_en == _TRUE) {
-+			status = rtw_BT_efuse_map_write(padapter, 0x1f8, 4, pgdata);
-+			RTW_INFO("%s done!!!\n", __FUNCTION__);
-+	}
-+	if (status == _FAIL)
-+		RTW_INFO("%s: fail\n", __FUNCTION__);
-+	padapter->registrypriv.boffefusemask = bkmask;
-+}
-+#endif
-+
-+u8 rtw_BT_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
-+{
-+#define RT_ASSERT_RET(expr)									\
-+	if (!(expr)) {										\
-+		printk("Assertion failed! %s at ......\n", #expr);				\
-+		printk("	  ......%s,%s, line=%d\n",__FILE__, __FUNCTION__, __LINE__);	\
-+		return _FAIL;	\
-+	}
-+
-+	u8	offset, word_en;
-+	u8 *efuse = NULL;
-+	u8	*map;
-+	u8	newdata[PGPKT_DATA_SIZE];
-+	s32 i = 0, j = 0, idx = 0, chk_total_byte = 0;
-+	u8	ret = _SUCCESS;
-+	u16 mapLen = 1024;
-+	u16 startAddr = 0;
-+
-+	if ((addr + cnts) > mapLen)
-+		return _FAIL;
-+
-+	RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */
-+	RT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */
-+
-+	efuse = rtw_zmalloc(mapLen);
-+	if (!efuse)
-+		return _FAIL;
-+
-+	map = rtw_zmalloc(mapLen);
-+	if (map == NULL) {
-+		rtw_mfree(efuse, mapLen);
-+		return _FAIL;
-+	}
-+
-+	_rtw_memset(map, 0xFF, mapLen);
-+
-+	ret = rtw_BT_efuse_map_read(adapter, 0, mapLen, map);
-+	if (ret == _FAIL)
-+		goto exit;
-+
-+	_rtw_memcpy(efuse , map, mapLen);
-+	_rtw_memcpy(efuse + addr, data, cnts);
-+#ifdef CONFIG_BT_EFUSE_MASK
-+	if (adapter->registrypriv.boffefusemask == 0) {
-+		for (i = 0; i < cnts; i++) {
-+			if (adapter->registrypriv.bBTFileMaskEfuse == _TRUE) {
-+				if (rtw_file_efuse_IsMasked(adapter, addr + i, btmaskfileBuffer)) /*use file efuse mask. */
-+					efuse[addr + i] = map[addr + i];
-+			} else {
-+				if (efuse_IsBT_Masked(adapter, addr + i))
-+					efuse[addr + i] = map[addr + i];
-+			}
-+			RTW_INFO("%s , efuse[%x] = %x, map = %x\n", __func__, addr + i, efuse[ addr + i], map[addr + i]);
-+		}
-+	}
-+#endif /*CONFIG_BT_EFUSE_MASK*/
-+	/* precheck pg efuse data byte*/
-+	chk_total_byte = 0;
-+	idx = 0;
-+	offset = (addr >> 3);
-+
-+	while (idx < cnts) {
-+		word_en = 0xF;
-+		j = (addr + idx) & 0x7;
-+		for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
-+			if (efuse[addr + idx] != map[addr + idx])
-+				word_en &= ~BIT(i >> 1);
-+		}
-+
-+		if (word_en != 0xF) {
-+			chk_total_byte += Efuse_CalculateWordCnts(word_en) * 2;
-+
-+			if (offset >= EFUSE_MAX_SECTION_BASE) /* Over EFUSE_MAX_SECTION 16 for 2 ByteHeader */
-+				chk_total_byte += 2;
-+			else
-+				chk_total_byte += 1;
-+		}
-+
-+		offset++;
-+	}
-+
-+	RTW_INFO("Total PG bytes Count = %d\n", chk_total_byte);
-+	startAddr = hal_EfuseGetCurrentSize_BT(adapter, _FALSE);
-+	RTW_INFO("%s: startAddr=%#X\n", __func__, startAddr);
-+
-+	if (!AVAILABLE_EFUSE_ADDR(startAddr + chk_total_byte)) {
-+		RTW_INFO("%s: startAddr(0x%X) + PG data len %d >= efuse BT available offset (0x%X)\n",
-+			 __func__, startAddr, chk_total_byte, EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK);
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	idx = 0;
-+	offset = (addr >> 3);
-+	while (idx < cnts) {
-+		word_en = 0xF;
-+		j = (addr + idx) & 0x7;
-+		_rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE);
-+		for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
-+			if (efuse[addr + idx] != map[addr + idx]) {
-+				word_en &= ~BIT(i >> 1);
-+				newdata[i] = efuse[addr + idx];
-+			}
-+		}
-+
-+		if (word_en != 0xF) {
-+			ret = EfusePgPacketWrite_BT(adapter, offset, word_en, newdata, _FALSE);
-+			RTW_INFO("offset=%x\n", offset);
-+			RTW_INFO("word_en=%x\n", word_en);
-+			RTW_INFO("%s: data=", __FUNCTION__);
-+			for (i = 0; i < PGPKT_DATA_SIZE; i++)
-+				RTW_INFO("0x%02X ", newdata[i]);
-+			RTW_INFO("\n");
-+			if (ret == _FAIL)
-+				break;
-+		}
-+		offset++;
-+	}
-+exit:
-+	if (efuse)
-+		rtw_mfree(efuse, mapLen);
-+	if (map)
-+		rtw_mfree(map, mapLen);
-+	return ret;
-+}
-+
-+void hal_ReadEFuse_BT_logic_map(
-+	PADAPTER	padapter,
-+	u16			_offset,
-+	u16			_size_byte,
-+	u8			*pbuf
-+)
-+{
-+
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+
-+	u8	*efuseTbl, *phyefuse;
-+	u8	bank;
-+	u16	eFuse_Addr = 0;
-+	u8	efuseHeader, efuseExtHdr, efuseData;
-+	u8	offset, wden;
-+	u16	i, total, used;
-+	u8	efuse_usage;
-+
-+
-+	/* */
-+	/* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
-+	/* */
-+	if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) {
-+		RTW_INFO("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __FUNCTION__, _offset, _size_byte);
-+		return;
-+	}
-+
-+	efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN);
-+	phyefuse = rtw_malloc(EFUSE_BT_REAL_CONTENT_LEN);
-+	if (efuseTbl == NULL || phyefuse == NULL) {
-+		RTW_INFO("%s: efuseTbl or phyefuse malloc fail!\n", __FUNCTION__);
-+		goto exit;
-+	}
-+
-+	/* 0xff will be efuse default value instead of 0x00. */
-+	_rtw_memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
-+	_rtw_memset(phyefuse, 0xFF, EFUSE_BT_REAL_CONTENT_LEN);
-+
-+	if (rtw_efuse_bt_access(padapter, _FALSE, 0, EFUSE_BT_REAL_CONTENT_LEN, phyefuse))
-+		dump_buf(phyefuse, EFUSE_BT_REAL_BANK_CONTENT_LEN);
-+
-+	total = BANK_NUM;
-+	for (bank = 1; bank <= total; bank++) { /* 8723d Max bake 0~2 */
-+		eFuse_Addr = 0;
-+
-+		while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
-+			/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */
-+			efuseHeader = phyefuse[eFuse_Addr++];
-+
-+			if (efuseHeader == 0xFF)
-+				break;
-+			RTW_INFO("%s: efuse[%#X]=0x%02x (header)\n", __FUNCTION__, (((bank - 1) * EFUSE_BT_REAL_CONTENT_LEN) + eFuse_Addr - 1), efuseHeader);
-+
-+			/* Check PG header for section num. */
-+			if (EXT_HEADER(efuseHeader)) {	/* extended header */
-+				offset = GET_HDR_OFFSET_2_0(efuseHeader);
-+				RTW_INFO("%s: extended header offset_2_0=0x%X\n", __FUNCTION__, offset);
-+
-+				/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */
-+				efuseExtHdr = phyefuse[eFuse_Addr++];
-+
-+				RTW_INFO("%s: efuse[%#X]=0x%02x (ext header)\n", __FUNCTION__, (((bank - 1) * EFUSE_BT_REAL_CONTENT_LEN) + eFuse_Addr - 1), efuseExtHdr);
-+				if (ALL_WORDS_DISABLED(efuseExtHdr))
-+					continue;
-+
-+				offset |= ((efuseExtHdr & 0xF0) >> 1);
-+				wden = (efuseExtHdr & 0x0F);
-+			} else {
-+				offset = ((efuseHeader >> 4) & 0x0f);
-+				wden = (efuseHeader & 0x0f);
-+			}
-+
-+			if (offset < EFUSE_BT_MAX_SECTION) {
-+				u16 addr;
-+
-+				/* Get word enable value from PG header */
-+				RTW_INFO("%s: Offset=%d Worden=%#X\n", __FUNCTION__, offset, wden);
-+
-+				addr = offset * PGPKT_DATA_SIZE;
-+				for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
-+					/* Check word enable condition in the section */
-+					if (!(wden & (0x01 << i))) {
-+						efuseData = 0;
-+						/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
-+						efuseData = phyefuse[eFuse_Addr++];
-+
-+						RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr - 1, efuseData);
-+						efuseTbl[addr] = efuseData;
-+
-+						efuseData = 0;
-+						/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
-+						efuseData = phyefuse[eFuse_Addr++];
-+
-+						RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr - 1, efuseData);
-+						efuseTbl[addr + 1] = efuseData;
-+					}
-+					addr += 2;
-+				}
-+			} else {
-+				RTW_INFO("%s: offset(%d) is illegal!!\n", __FUNCTION__, offset);
-+				eFuse_Addr += Efuse_CalculateWordCnts(wden) * 2;
-+			}
-+		}
-+
-+		if ((eFuse_Addr - 1) < total) {
-+			RTW_INFO("%s: bank(%d) data end at %#x\n", __FUNCTION__, bank, eFuse_Addr - 1);
-+			break;
-+		}
-+	}
-+
-+	/* switch bank back to bank 0 for later BT and wifi use. */
-+	//hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
-+
-+	/* Copy from Efuse map to output pointer memory!!! */
-+	for (i = 0; i < _size_byte; i++)
-+		pbuf[i] = efuseTbl[_offset + i];
-+	/* Calculate Efuse utilization */
-+	total = EFUSE_BT_REAL_BANK_CONTENT_LEN;
-+
-+	used = eFuse_Addr - 1;
-+
-+	if (total)
-+		efuse_usage = (u8)((used * 100) / total);
-+	else
-+		efuse_usage = 100;
-+
-+	fakeBTEfuseUsedBytes = used;
-+	RTW_INFO("%s: BTEfuseUsed last Bytes = %#x\n", __FUNCTION__, fakeBTEfuseUsedBytes);
-+
-+exit:
-+	if (efuseTbl)
-+		rtw_mfree(efuseTbl, EFUSE_BT_MAP_LEN);
-+	if (phyefuse)
-+		rtw_mfree(phyefuse, EFUSE_BT_REAL_BANK_CONTENT_LEN);
-+}
-+
-+
-+static u8 hal_EfusePartialWriteCheck(
-+	PADAPTER		padapter,
-+	u8				efuseType,
-+	u16				*pAddr,
-+	PPGPKT_STRUCT	pTargetPkt,
-+	u8				bPseudoTest)
-+{
-+	u8	bRet = _FALSE;
-+	u16	startAddr = 0, efuse_max_available_len = EFUSE_BT_REAL_BANK_CONTENT_LEN, efuse_max = EFUSE_BT_REAL_BANK_CONTENT_LEN;
-+	u8	efuse_data = 0;
-+
-+	startAddr = (u16)fakeBTEfuseUsedBytes;
-+
-+	startAddr %= efuse_max;
-+	RTW_INFO("%s: startAddr=%#X\n", __FUNCTION__, startAddr);
-+
-+	while (1) {
-+		if (startAddr >= efuse_max_available_len) {
-+			bRet = _FALSE;
-+			RTW_INFO("%s: startAddr(%d) >= efuse_max_available_len(%d)\n",
-+				__FUNCTION__, startAddr, efuse_max_available_len);
-+			break;
-+		}
-+		if (rtw_efuse_bt_access(padapter, _FALSE, startAddr, 1, &efuse_data)&& (efuse_data != 0xFF)) {
-+			bRet = _FALSE;
-+			RTW_INFO("%s: Something Wrong! last bytes(%#X=0x%02X) is not 0xFF\n",
-+				 __FUNCTION__, startAddr, efuse_data);
-+			break;
-+		} else {
-+			/* not used header, 0xff */
-+			*pAddr = startAddr;
-+			/*			RTW_INFO("%s: Started from unused header offset=%d\n", __FUNCTION__, startAddr)); */
-+			bRet = _TRUE;
-+			break;
-+		}
-+	}
-+
-+	return bRet;
-+}
-+
-+
-+static u8 hal_EfusePgPacketWrite2ByteHeader(
-+	PADAPTER		padapter,
-+	u8				efuseType,
-+	u16				*pAddr,
-+	PPGPKT_STRUCT	pTargetPkt,
-+	u8				bPseudoTest)
-+{
-+	u16	efuse_addr, efuse_max_available_len = EFUSE_BT_REAL_BANK_CONTENT_LEN;
-+	u8	pg_header = 0, tmp_header = 0;
-+	u8	repeatcnt = 0;
-+
-+	/*	RTW_INFO("%s\n", __FUNCTION__); */
-+
-+	efuse_addr = *pAddr;
-+	if (efuse_addr >= efuse_max_available_len) {
-+		RTW_INFO("%s: addr(%d) over avaliable(%d)!!\n", __FUNCTION__, efuse_addr, efuse_max_available_len);
-+		return _FALSE;
-+	}
-+
-+	pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
-+	/*	RTW_INFO("%s: pg_header=0x%x\n", __FUNCTION__, pg_header); */
-+
-+	do {
-+
-+		rtw_efuse_bt_access(padapter, _TRUE, efuse_addr, 1, &pg_header);
-+		rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &tmp_header);
-+
-+		if (tmp_header != 0xFF)
-+			break;
-+		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
-+			RTW_INFO("%s: Repeat over limit for pg_header!!\n", __FUNCTION__);
-+			return _FALSE;
-+		}
-+	} while (1);
-+
-+	if (tmp_header != pg_header) {
-+		RTW_ERR("%s: PG Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header);
-+		return _FALSE;
-+	}
-+
-+	/* to write ext_header */
-+	efuse_addr++;
-+	pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
-+
-+	do {
-+		rtw_efuse_bt_access(padapter, _TRUE, efuse_addr, 1, &pg_header);
-+		rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &tmp_header);
-+
-+		if (tmp_header != 0xFF)
-+			break;
-+		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
-+			RTW_INFO("%s: Repeat over limit for ext_header!!\n", __FUNCTION__);
-+			return _FALSE;
-+		}
-+	} while (1);
-+
-+	if (tmp_header != pg_header) {	/* offset PG fail */
-+		RTW_ERR("%s: PG EXT Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header);
-+		return _FALSE;
-+	}
-+
-+	*pAddr = efuse_addr;
-+
-+	return _TRUE;
-+}
-+
-+
-+static u8 hal_EfusePgPacketWrite1ByteHeader(
-+	PADAPTER		pAdapter,
-+	u8				efuseType,
-+	u16				*pAddr,
-+	PPGPKT_STRUCT	pTargetPkt,
-+	u8				bPseudoTest)
-+{
-+	u8	pg_header = 0, tmp_header = 0;
-+	u16	efuse_addr = *pAddr;
-+	u8	repeatcnt = 0;
-+
-+
-+	/*	RTW_INFO("%s\n", __FUNCTION__); */
-+	pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en;
-+
-+	do {
-+		rtw_efuse_bt_access(pAdapter, _TRUE, efuse_addr, 1, &pg_header);
-+		rtw_efuse_bt_access(pAdapter, _FALSE, efuse_addr, 1, &tmp_header);
-+
-+		if (tmp_header != 0xFF)
-+			break;
-+		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
-+			RTW_INFO("%s: Repeat over limit for pg_header!!\n", __FUNCTION__);
-+			return _FALSE;
-+		}
-+	} while (1);
-+
-+	if (tmp_header != pg_header) {
-+		RTW_ERR("%s: PG Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header);
-+		return _FALSE;
-+	}
-+
-+	*pAddr = efuse_addr;
-+
-+	return _TRUE;
-+}
-+
-+static u8 hal_EfusePgPacketWriteHeader(
-+	PADAPTER		padapter,
-+	u8				efuseType,
-+	u16				*pAddr,
-+	PPGPKT_STRUCT	pTargetPkt,
-+	u8				bPseudoTest)
-+{
-+	u8 bRet = _FALSE;
-+
-+	if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
-+		bRet = hal_EfusePgPacketWrite2ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
-+	else
-+		bRet = hal_EfusePgPacketWrite1ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
-+
-+	return bRet;
-+}
-+
-+
-+static u8
-+Hal_EfuseWordEnableDataWrite(
-+	PADAPTER	padapter,
-+	u16			efuse_addr,
-+	u8			word_en,
-+	u8			*data,
-+	u8			bPseudoTest)
-+{
-+	u16	tmpaddr = 0;
-+	u16	start_addr = efuse_addr;
-+	u8	badworden = 0x0F;
-+	u8	tmpdata[PGPKT_DATA_SIZE];
-+
-+
-+	/*	RTW_INFO("%s: efuse_addr=%#x word_en=%#x\n", __FUNCTION__, efuse_addr, word_en); */
-+	_rtw_memset(tmpdata, 0xFF, PGPKT_DATA_SIZE);
-+
-+	if (!(word_en & BIT(0))) {
-+		tmpaddr = start_addr;
-+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[0]);
-+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[1]);
-+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[0]);
-+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[1]);
-+		if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))
-+			badworden &= (~BIT(0));
-+	}
-+	if (!(word_en & BIT(1))) {
-+		tmpaddr = start_addr;
-+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[2]);
-+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[3]);
-+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[2]);
-+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[3]);
-+		if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))
-+			badworden &= (~BIT(1));
-+	}
-+	if (!(word_en & BIT(2))) {
-+		tmpaddr = start_addr;
-+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[4]);
-+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[5]);
-+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[4]);
-+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[5]);
-+		if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))
-+			badworden &= (~BIT(2));
-+	}
-+	if (!(word_en & BIT(3))) {
-+		tmpaddr = start_addr;
-+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[6]);
-+		rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[7]);
-+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[6]);
-+		rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[7]);
-+
-+		if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))
-+			badworden &= (~BIT(3));
-+	}
-+
-+	return badworden;
-+}
-+
-+static void
-+hal_EfuseConstructPGPkt(
-+	u8				offset,
-+	u8				word_en,
-+	u8				*pData,
-+	PPGPKT_STRUCT	pTargetPkt)
-+{
-+	_rtw_memset(pTargetPkt->data, 0xFF, PGPKT_DATA_SIZE);
-+	pTargetPkt->offset = offset;
-+	pTargetPkt->word_en = word_en;
-+	efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
-+	pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
-+}
-+
-+static u8
-+hal_EfusePgPacketWriteData(
-+	PADAPTER		pAdapter,
-+	u8				efuseType,
-+	u16				*pAddr,
-+	PPGPKT_STRUCT	pTargetPkt,
-+	u8				bPseudoTest)
-+{
-+	u16	efuse_addr;
-+	u8	badworden;
-+
-+	efuse_addr = *pAddr;
-+	badworden = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr + 1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
-+	if (badworden != 0x0F) {
-+		RTW_INFO("%s: Fail!!\n", __FUNCTION__);
-+		return _FALSE;
-+	} else
-+		RTW_INFO("%s: OK!!\n", __FUNCTION__);
-+
-+	return _TRUE;
-+}
-+
-+u8 efuse_OneByteRead(struct _ADAPTER *a, u16 addr, u8 *data, u8 bPseudoTest)
-+{
-+		struct dvobj_priv *d;
-+		int err;
-+		u8 ret = _TRUE;
-+
-+		d = adapter_to_dvobj(a);
-+		err = rtw_halmac_read_physical_efuse(d, addr, 1, data);
-+		if (err) {
-+			RTW_ERR("%s: addr=0x%x FAIL!!!\n", __FUNCTION__, addr);
-+			ret = _FALSE;
-+		}
-+
-+		return ret;
-+
-+}
-+
-+
-+static u8
-+hal_BT_EfusePgCheckAvailableAddr(
-+	PADAPTER	pAdapter,
-+	u8		bPseudoTest)
-+{
-+	u16	max_available = EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK;
-+	u16	current_size = 0;
-+
-+	 RTW_INFO("%s: max_available=%d\n", __FUNCTION__, max_available);
-+	current_size = hal_EfuseGetCurrentSize_BT(pAdapter, bPseudoTest);
-+	if (current_size >= max_available) {
-+		RTW_INFO("%s: Error!! current_size(%d)>max_available(%d)\n", __FUNCTION__, current_size, max_available);
-+		return _FALSE;
-+	}
-+	return _TRUE;
-+}
-+
-+u8 EfusePgPacketWrite_BT(
-+	PADAPTER	pAdapter,
-+	u8			offset,
-+	u8			word_en,
-+	u8			*pData,
-+	u8			bPseudoTest)
-+{
-+	PGPKT_STRUCT targetPkt;
-+	u16 startAddr = 0;
-+	u8 efuseType = EFUSE_BT;
-+
-+	if (!hal_BT_EfusePgCheckAvailableAddr(pAdapter, bPseudoTest))
-+		return _FALSE;
-+
-+	hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
-+
-+	if (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
-+		return _FALSE;
-+
-+	if (!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
-+		return _FALSE;
-+
-+	if (!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
-+		return _FALSE;
-+
-+	return _TRUE;
-+}
-+
-+
-+#else /* !RTW_HALMAC */
-+/* ------------------------------------------------------------------------------ */
-+#define REG_EFUSE_CTRL		0x0030
-+#define EFUSE_CTRL			REG_EFUSE_CTRL		/* E-Fuse Control. */
-+/* ------------------------------------------------------------------------------ */
-+
-+
-+BOOLEAN
-+Efuse_Read1ByteFromFakeContent(
-+		PADAPTER	pAdapter,
-+		u16		Offset,
-+		u8		*Value);
-+BOOLEAN
-+Efuse_Read1ByteFromFakeContent(
-+		PADAPTER	pAdapter,
-+		u16		Offset,
-+		u8		*Value)
-+{
-+	if (Offset >= EFUSE_MAX_HW_SIZE)
-+		return _FALSE;
-+	/* DbgPrint("Read fake content, offset = %d\n", Offset); */
-+	if (fakeEfuseBank == 0)
-+		*Value = fakeEfuseContent[Offset];
-+	else
-+		*Value = fakeBTEfuseContent[fakeEfuseBank - 1][Offset];
-+	return _TRUE;
-+}
-+
-+BOOLEAN
-+Efuse_Write1ByteToFakeContent(
-+			PADAPTER	pAdapter,
-+			u16		Offset,
-+			u8		Value);
-+BOOLEAN
-+Efuse_Write1ByteToFakeContent(
-+			PADAPTER	pAdapter,
-+			u16		Offset,
-+			u8		Value)
-+{
-+	if (Offset >= EFUSE_MAX_HW_SIZE)
-+		return _FALSE;
-+	if (fakeEfuseBank == 0)
-+		fakeEfuseContent[Offset] = Value;
-+	else
-+		fakeBTEfuseContent[fakeEfuseBank - 1][Offset] = Value;
-+	return _TRUE;
-+}
-+
-+/*-----------------------------------------------------------------------------
-+ * Function:	Efuse_PowerSwitch
-+ *
-+ * Overview:	When we want to enable write operation, we should change to
-+ *				pwr on state. When we stop write, we should switch to 500k mode
-+ *				and disable LDO 2.5V.
-+ *
-+ * Input:       NONE
-+ *
-+ * Output:      NONE
-+ *
-+ * Return:      NONE
-+ *
-+ * Revised History:
-+ * When			Who		Remark
-+ * 11/17/2008	MHC		Create Version 0.
-+ *
-+ *---------------------------------------------------------------------------*/
-+void
-+Efuse_PowerSwitch(
-+		PADAPTER	pAdapter,
-+		u8		bWrite,
-+		u8		PwrState)
-+{
-+	pAdapter->hal_func.EfusePowerSwitch(pAdapter, bWrite, PwrState);
-+}
-+
-+void
-+BTEfuse_PowerSwitch(
-+		PADAPTER	pAdapter,
-+		u8		bWrite,
-+		u8		PwrState)
-+{
-+	if (pAdapter->hal_func.BTEfusePowerSwitch)
-+		pAdapter->hal_func.BTEfusePowerSwitch(pAdapter, bWrite, PwrState);
-+}
-+
-+/*-----------------------------------------------------------------------------
-+ * Function:	efuse_GetCurrentSize
-+ *
-+ * Overview:	Get current efuse size!!!
-+ *
-+ * Input:       NONE
-+ *
-+ * Output:      NONE
-+ *
-+ * Return:      NONE
-+ *
-+ * Revised History:
-+ * When			Who		Remark
-+ * 11/16/2008	MHC		Create Version 0.
-+ *
-+ *---------------------------------------------------------------------------*/
-+u16
-+Efuse_GetCurrentSize(
-+	PADAPTER		pAdapter,
-+	u8			efuseType,
-+	BOOLEAN		bPseudoTest)
-+{
-+	u16 ret = 0;
-+
-+	ret = pAdapter->hal_func.EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest);
-+
-+	return ret;
-+}
-+
-+/*
-+ *	Description:
-+ *		Execute E-Fuse read byte operation.
-+ *		Refered from SD1 Richard.
-+ *
-+ *	Assumption:
-+ *		1. Boot from E-Fuse and successfully auto-load.
-+ *		2. PASSIVE_LEVEL (USB interface)
-+ *
-+ *	Created by Roger, 2008.10.21.
-+ *   */
-+void
-+ReadEFuseByte(
-+	PADAPTER	Adapter,
-+	u16			_offset,
-+	u8			*pbuf,
-+	BOOLEAN	bPseudoTest)
-+{
-+	u32	value32;
-+	u8	readbyte;
-+	u16	retry;
-+	/* systime start=rtw_get_current_time(); */
-+
-+	if (bPseudoTest) {
-+		Efuse_Read1ByteFromFakeContent(Adapter, _offset, pbuf);
-+		return;
-+	}
-+	if (IS_HARDWARE_TYPE_8723B(Adapter)) {
-+		/* <20130121, Kordan> For SMIC S55 EFUSE specificatoin. */
-+		/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
-+		phy_set_mac_reg(Adapter, EFUSE_TEST, BIT11, 0);
-+	}
-+	/* Write Address */
-+	rtw_write8(Adapter, EFUSE_CTRL + 1, (_offset & 0xff));
-+	readbyte = rtw_read8(Adapter, EFUSE_CTRL + 2);
-+	rtw_write8(Adapter, EFUSE_CTRL + 2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc));
-+
-+	/* Write bit 32 0 */
-+	readbyte = rtw_read8(Adapter, EFUSE_CTRL + 3);
-+	rtw_write8(Adapter, EFUSE_CTRL + 3, (readbyte & 0x7f));
-+
-+	/* Check bit 32 read-ready */
-+	retry = 0;
-+	value32 = rtw_read32(Adapter, EFUSE_CTRL);
-+	/* while(!(((value32 >> 24) & 0xff) & 0x80)  && (retry<10)) */
-+	while (!(((value32 >> 24) & 0xff) & 0x80)  && (retry < 10000)) {
-+		value32 = rtw_read32(Adapter, EFUSE_CTRL);
-+		retry++;
-+	}
-+
-+	/* 20100205 Joseph: Add delay suggested by SD1 Victor. */
-+	/* This fix the problem that Efuse read error in high temperature condition. */
-+	/* Designer says that there shall be some delay after ready bit is set, or the */
-+	/* result will always stay on last data we read. */
-+	rtw_udelay_os(50);
-+	value32 = rtw_read32(Adapter, EFUSE_CTRL);
-+
-+	*pbuf = (u8)(value32 & 0xff);
-+	/* RTW_INFO("ReadEFuseByte _offset:%08u, in %d ms\n",_offset ,rtw_get_passing_time_ms(start)); */
-+
-+}
-+
-+/*
-+ *	Description:
-+ *		1. Execute E-Fuse read byte operation according as map offset and
-+ *		    save to E-Fuse table.
-+ *		2. Refered from SD1 Richard.
-+ *
-+ *	Assumption:
-+ *		1. Boot from E-Fuse and successfully auto-load.
-+ *		2. PASSIVE_LEVEL (USB interface)
-+ *
-+ *	Created by Roger, 2008.10.21.
-+ *
-+ *	2008/12/12 MH	1. Reorganize code flow and reserve bytes. and add description.
-+ *					2. Add efuse utilization collect.
-+ *	2008/12/22 MH	Read Efuse must check if we write section 1 data again!!! Sec1
-+ *					write addr must be after sec5.
-+ *   */
-+
-+void
-+efuse_ReadEFuse(
-+	PADAPTER	Adapter,
-+	u8		efuseType,
-+	u16		_offset,
-+	u16		_size_byte,
-+	u8	*pbuf,
-+	BOOLEAN	bPseudoTest
-+);
-+void
-+efuse_ReadEFuse(
-+	PADAPTER	Adapter,
-+	u8		efuseType,
-+	u16		_offset,
-+	u16		_size_byte,
-+	u8	*pbuf,
-+	BOOLEAN	bPseudoTest
-+)
-+{
-+	Adapter->hal_func.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
-+}
-+
-+void
-+EFUSE_GetEfuseDefinition(
-+			PADAPTER	pAdapter,
-+			u8		efuseType,
-+			u8		type,
-+			void		*pOut,
-+			BOOLEAN		bPseudoTest
-+)
-+{
-+	pAdapter->hal_func.EFUSEGetEfuseDefinition(pAdapter, efuseType, type, pOut, bPseudoTest);
-+}
-+
-+
-+/*  11/16/2008 MH Read one byte from real Efuse. */
-+u8
-+efuse_OneByteRead(
-+		PADAPTER	pAdapter,
-+		u16			addr,
-+		u8			*data,
-+		BOOLEAN		bPseudoTest)
-+{
-+	u32	tmpidx = 0;
-+	u8	bResult;
-+	u8	readbyte;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+
-+	/* RTW_INFO("===> EFUSE_OneByteRead(), addr = %x\n", addr); */
-+	/* RTW_INFO("===> EFUSE_OneByteRead() start, 0x34 = 0x%X\n", rtw_read32(pAdapter, EFUSE_TEST)); */
-+
-+	if (bPseudoTest) {
-+		bResult = Efuse_Read1ByteFromFakeContent(pAdapter, addr, data);
-+		return bResult;
-+	}
-+
-+#ifdef CONFIG_RTL8710B
-+	/* <20171208, Peter>, Dont do the following write16(0x34) */
-+	if (IS_HARDWARE_TYPE_8710B(pAdapter)) {
-+		bResult = pAdapter->hal_func.efuse_indirect_read4(pAdapter, addr, data);
-+		return bResult;
-+	}
-+#endif
-+
-+	if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
-+	    (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
-+	    (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
-+	   ) {
-+		/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
-+		/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8])	 */
-+		/* phy_set_mac_reg(pAdapter, 0x34, BIT11, 0); */
-+		rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) & (~BIT11));
-+	}
-+
-+	/* -----------------e-fuse reg ctrl --------------------------------- */
-+	/* address			 */
-+	rtw_write8(pAdapter, EFUSE_CTRL + 1, (u8)(addr & 0xff));
-+	rtw_write8(pAdapter, EFUSE_CTRL + 2, ((u8)((addr >> 8) & 0x03)) |
-+		   (rtw_read8(pAdapter, EFUSE_CTRL + 2) & 0xFC));
-+
-+	/* rtw_write8(pAdapter, EFUSE_CTRL+3,  0x72); */ /* read cmd	 */
-+	/* Write bit 32 0 */
-+	readbyte = rtw_read8(pAdapter, EFUSE_CTRL + 3);
-+	rtw_write8(pAdapter, EFUSE_CTRL + 3, (readbyte & 0x7f));
-+
-+	while (!(0x80 & rtw_read8(pAdapter, EFUSE_CTRL + 3)) && (tmpidx < 1000)) {
-+		rtw_mdelay_os(1);
-+		tmpidx++;
-+	}
-+	if (tmpidx < 100) {
-+		*data = rtw_read8(pAdapter, EFUSE_CTRL);
-+		bResult = _TRUE;
-+	} else {
-+		*data = 0xff;
-+		bResult = _FALSE;
-+		RTW_INFO("%s: [ERROR] addr=0x%x bResult=%d time out 1s !!!\n", __FUNCTION__, addr, bResult);
-+		RTW_INFO("%s: [ERROR] EFUSE_CTRL =0x%08x !!!\n", __FUNCTION__, rtw_read32(pAdapter, EFUSE_CTRL));
-+	}
-+
-+	return bResult;
-+}
-+
-+/*  11/16/2008 MH Write one byte to reald Efuse. */
-+u8
-+efuse_OneByteWrite(
-+		PADAPTER	pAdapter,
-+		u16			addr,
-+		u8			data,
-+		BOOLEAN		bPseudoTest)
-+{
-+	u8	tmpidx = 0;
-+	u8	bResult = _FALSE;
-+	u32 efuseValue = 0;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+
-+	/* RTW_INFO("===> EFUSE_OneByteWrite(), addr = %x data=%x\n", addr, data); */
-+	/* RTW_INFO("===> EFUSE_OneByteWrite() start, 0x34 = 0x%X\n", rtw_read32(pAdapter, EFUSE_TEST)); */
-+
-+	if (bPseudoTest) {
-+		bResult = Efuse_Write1ByteToFakeContent(pAdapter, addr, data);
-+		return bResult;
-+	}
-+
-+	Efuse_PowerSwitch(pAdapter, _TRUE, _TRUE);
-+
-+	/* -----------------e-fuse reg ctrl ---------------------------------	 */
-+	/* address			 */
-+
-+
-+	efuseValue = rtw_read32(pAdapter, EFUSE_CTRL);
-+	efuseValue |= (BIT21 | BIT31);
-+	efuseValue &= ~(0x3FFFF);
-+	efuseValue |= ((addr << 8 | data) & 0x3FFFF);
-+
-+	/* <20130227, Kordan> 8192E MP chip A-cut had better not set 0x34[11] until B-Cut. */
-+	if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
-+	    (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
-+	    (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
-+	   ) {
-+		/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
-+		/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
-+		/* phy_set_mac_reg(pAdapter, 0x34, BIT11, 1); */
-+		rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) | (BIT11));
-+		rtw_write32(pAdapter, EFUSE_CTRL, 0x90600000 | ((addr << 8 | data)));
-+	} else
-+		rtw_write32(pAdapter, EFUSE_CTRL, efuseValue);
-+
-+	rtw_mdelay_os(1);
-+
-+	while ((0x80 &  rtw_read8(pAdapter, EFUSE_CTRL + 3)) && (tmpidx < 100)) {
-+		rtw_mdelay_os(1);
-+		tmpidx++;
-+	}
-+
-+	if (tmpidx < 100)
-+		bResult = _TRUE;
-+	else {
-+		bResult = _FALSE;
-+		RTW_INFO("%s: [ERROR] addr=0x%x ,efuseValue=0x%x ,bResult=%d time out 1s !!!\n",
-+			 __FUNCTION__, addr, efuseValue, bResult);
-+		RTW_INFO("%s: [ERROR] EFUSE_CTRL =0x%08x !!!\n", __FUNCTION__, rtw_read32(pAdapter, EFUSE_CTRL));
-+	}
-+
-+	/* disable Efuse program enable */
-+	if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
-+	    (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
-+	    (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
-+	   )
-+		phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT(11), 0);
-+
-+	Efuse_PowerSwitch(pAdapter, _TRUE, _FALSE);
-+
-+	return bResult;
-+}
-+
-+int
-+Efuse_PgPacketRead(PADAPTER	pAdapter,
-+			u8			offset,
-+			u8			*data,
-+			BOOLEAN		bPseudoTest)
-+{
-+	int	ret = 0;
-+
-+	ret =  pAdapter->hal_func.Efuse_PgPacketRead(pAdapter, offset, data, bPseudoTest);
-+
-+	return ret;
-+}
-+
-+int
-+Efuse_PgPacketWrite(PADAPTER	pAdapter,
-+			u8			offset,
-+			u8			word_en,
-+			u8			*data,
-+			BOOLEAN		bPseudoTest)
-+{
-+	int ret;
-+
-+	ret =  pAdapter->hal_func.Efuse_PgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest);
-+
-+	return ret;
-+}
-+
-+
-+int
-+Efuse_PgPacketWrite_BT(PADAPTER	pAdapter,
-+			u8			offset,
-+			u8			word_en,
-+			u8			*data,
-+			BOOLEAN		bPseudoTest)
-+{
-+	int ret;
-+
-+	ret =  pAdapter->hal_func.Efuse_PgPacketWrite_BT(pAdapter, offset, word_en, data, bPseudoTest);
-+
-+	return ret;
-+}
-+
-+
-+u8
-+Efuse_WordEnableDataWrite(PADAPTER	pAdapter,
-+				u16		efuse_addr,
-+				u8		word_en,
-+				u8		*data,
-+				BOOLEAN		bPseudoTest)
-+{
-+	u8	ret = 0;
-+
-+	ret =  pAdapter->hal_func.Efuse_WordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
-+
-+	return ret;
-+}
-+
-+static u8 efuse_read8(PADAPTER padapter, u16 address, u8 *value)
-+{
-+	return efuse_OneByteRead(padapter, address, value, _FALSE);
-+}
-+
-+static u8 efuse_write8(PADAPTER padapter, u16 address, u8 *value)
-+{
-+	return efuse_OneByteWrite(padapter, address, *value, _FALSE);
-+}
-+
-+/*
-+ * read/wirte raw efuse data
-+ */
-+u8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 *data)
-+{
-+	int i = 0;
-+	u16	real_content_len = 0, max_available_size = 0;
-+	u8 res = _FAIL ;
-+	u8(*rw8)(PADAPTER, u16, u8 *);
-+	u32	backupRegs[4] = {0};
-+
-+
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (void *)&real_content_len, _FALSE);
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (void *)&max_available_size, _FALSE);
-+
-+	if (start_addr > real_content_len)
-+		return _FAIL;
-+
-+	if (_TRUE == bWrite) {
-+		if ((start_addr + cnts) > max_available_size)
-+			return _FAIL;
-+		rw8 = &efuse_write8;
-+	} else
-+		rw8 = &efuse_read8;
-+
-+	efuse_PreUpdateAction(padapter, backupRegs);
-+
-+	Efuse_PowerSwitch(padapter, bWrite, _TRUE);
-+
-+	/* e-fuse one byte read / write */
-+	for (i = 0; i < cnts; i++) {
-+		if (start_addr >= real_content_len) {
-+			res = _FAIL;
-+			break;
-+		}
-+
-+		res = rw8(padapter, start_addr++, data++);
-+		if (_FAIL == res)
-+			break;
-+	}
-+
-+	Efuse_PowerSwitch(padapter, bWrite, _FALSE);
-+
-+	efuse_PostUpdateAction(padapter, backupRegs);
-+
-+	return res;
-+}
-+/* ------------------------------------------------------------------------------ */
-+u16 efuse_GetMaxSize(PADAPTER padapter)
-+{
-+	u16	max_size;
-+
-+	max_size = 0;
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (void *)&max_size, _FALSE);
-+	return max_size;
-+}
-+/* ------------------------------------------------------------------------------ */
-+u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size)
-+{
-+	Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
-+	*size = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE);
-+	Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
-+
-+	return _SUCCESS;
-+}
-+/* ------------------------------------------------------------------------------ */
-+u16 efuse_bt_GetMaxSize(PADAPTER padapter)
-+{
-+	u16	max_size;
-+
-+	max_size = 0;
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (void *)&max_size, _FALSE);
-+	return max_size;
-+}
-+
-+u8 efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size)
-+{
-+	Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
-+	*size = Efuse_GetCurrentSize(padapter, EFUSE_BT, _FALSE);
-+	Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
-+
-+	return _SUCCESS;
-+}
-+
-+u8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
-+{
-+	u16	mapLen = 0;
-+
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
-+
-+	if ((addr + cnts) > mapLen)
-+		return _FAIL;
-+
-+	Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
-+
-+	efuse_ReadEFuse(padapter, EFUSE_WIFI, addr, cnts, data, _FALSE);
-+
-+	Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
-+
-+	return _SUCCESS;
-+}
-+
-+u8 rtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
-+{
-+	u16	mapLen = 0;
-+
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
-+
-+	if ((addr + cnts) > mapLen)
-+		return _FAIL;
-+
-+	Efuse_PowerSwitch(padapter, _FALSE, _TRUE);
-+
-+	efuse_ReadEFuse(padapter, EFUSE_BT, addr, cnts, data, _FALSE);
-+
-+	Efuse_PowerSwitch(padapter, _FALSE, _FALSE);
-+
-+	return _SUCCESS;
-+}
-+
-+/* ------------------------------------------------------------------------------ */
-+u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
-+{
-+#define RT_ASSERT_RET(expr)												\
-+	if (!(expr)) {															\
-+		printk("Assertion failed! %s at ......\n", #expr);							\
-+		printk("      ......%s,%s, line=%d\n",__FILE__, __FUNCTION__, __LINE__);	\
-+		return _FAIL;	\
-+	}
-+
-+	u8 *efuse = NULL;
-+	u8	offset, word_en;
-+	u8	*map = NULL;
-+	u8	newdata[PGPKT_DATA_SIZE];
-+	s32	i, j, idx, chk_total_byte;
-+	u8	ret = _SUCCESS;
-+	u16	mapLen = 0, startAddr = 0, efuse_max_available_len = 0;
-+	u32	backupRegs[4] = {0};
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	PEFUSE_HAL	pEfuseHal = &pHalData->EfuseHal;
-+
-+
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, _FALSE);
-+
-+	if ((addr + cnts) > mapLen)
-+		return _FAIL;
-+
-+	RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */
-+	RT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */
-+
-+	efuse = rtw_zmalloc(mapLen);
-+	if (!efuse)
-+		return _FAIL;
-+
-+	map = rtw_zmalloc(mapLen);
-+	if (map == NULL) {
-+		rtw_mfree(efuse, mapLen);
-+		return _FAIL;
-+	}
-+
-+	_rtw_memset(map, 0xFF, mapLen);
-+
-+	ret = rtw_efuse_map_read(padapter, 0, mapLen, map);
-+	if (ret == _FAIL)
-+		goto exit;
-+
-+	_rtw_memcpy(efuse , map, mapLen);
-+	_rtw_memcpy(efuse + addr, data, cnts);
-+
-+	if (padapter->registrypriv.boffefusemask == 0) {
-+		for (i = 0; i < cnts; i++) {
-+			if (padapter->registrypriv.bFileMaskEfuse == _TRUE) {
-+				if (rtw_file_efuse_IsMasked(padapter, addr + i, maskfileBuffer)) /*use file efuse mask. */
-+					efuse[addr + i] = map[addr + i];
-+			} else {
-+				if (efuse_IsMasked(padapter, addr + i))
-+					efuse[addr + i] = map[addr + i];
-+			}
-+			RTW_INFO("%s , data[%d] = %x, map[addr+i]= %x\n", __func__, addr + i, efuse[ addr + i], map[addr + i]);
-+		}
-+	}
-+	/*Efuse_PowerSwitch(padapter, _TRUE, _TRUE);*/
-+
-+	chk_total_byte = 0;
-+	idx = 0;
-+	offset = (addr >> 3);
-+
-+	while (idx < cnts) {
-+		word_en = 0xF;
-+		j = (addr + idx) & 0x7;
-+		for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
-+			if (efuse[addr + idx] != map[addr + idx])
-+				word_en &= ~BIT(i >> 1);
-+		}
-+
-+		if (word_en != 0xF) {
-+			chk_total_byte += Efuse_CalculateWordCnts(word_en) * 2;
-+
-+			if (offset >= EFUSE_MAX_SECTION_BASE) /* Over EFUSE_MAX_SECTION 16 for 2 ByteHeader */
-+				chk_total_byte += 2;
-+			else
-+				chk_total_byte += 1;
-+		}
-+
-+		offset++;
-+	}
-+
-+	RTW_INFO("Total PG bytes Count = %d\n", chk_total_byte);
-+	rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
-+
-+	if (startAddr == 0) {
-+		startAddr = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE);
-+		RTW_INFO("%s: Efuse_GetCurrentSize startAddr=%#X\n", __func__, startAddr);
-+	}
-+	RTW_DBG("%s: startAddr=%#X\n", __func__, startAddr);
-+
-+	if ((startAddr + chk_total_byte) >= efuse_max_available_len) {
-+		RTW_INFO("%s: startAddr(0x%X) + PG data len %d >= efuse_max_available_len(0x%X)\n",
-+			 __func__, startAddr, chk_total_byte, efuse_max_available_len);
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	efuse_PreUpdateAction(padapter, backupRegs);
-+
-+	idx = 0;
-+	offset = (addr >> 3);
-+	while (idx < cnts) {
-+		word_en = 0xF;
-+		j = (addr + idx) & 0x7;
-+		_rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE);
-+		for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
-+			if (efuse[addr + idx] != map[addr + idx]) {
-+				word_en &= ~BIT(i >> 1);
-+				newdata[i] = efuse[addr + idx];
-+#ifdef CONFIG_RTL8723B
-+				if (addr + idx == 0x8) {
-+					if (IS_C_CUT(pHalData->version_id) || IS_B_CUT(pHalData->version_id)) {
-+						if (pHalData->adjuseVoltageVal == 6) {
-+							newdata[i] = map[addr + idx];
-+							RTW_INFO(" %s ,\n adjuseVoltageVal = %d ,newdata[%d] = %x\n", __func__, pHalData->adjuseVoltageVal, i, newdata[i]);
-+						}
-+					}
-+				}
-+#endif
-+			}
-+		}
-+
-+		if (word_en != 0xF) {
-+			ret = Efuse_PgPacketWrite(padapter, offset, word_en, newdata, _FALSE);
-+			RTW_INFO("offset=%x\n", offset);
-+			RTW_INFO("word_en=%x\n", word_en);
-+
-+			for (i = 0; i < PGPKT_DATA_SIZE; i++)
-+				RTW_INFO("data=%x \t", newdata[i]);
-+			if (ret == _FAIL)
-+				break;
-+		}
-+
-+		offset++;
-+	}
-+
-+	/*Efuse_PowerSwitch(padapter, _TRUE, _FALSE);*/
-+
-+	efuse_PostUpdateAction(padapter, backupRegs);
-+
-+exit:
-+
-+	rtw_mfree(map, mapLen);
-+	rtw_mfree(efuse, mapLen);
-+
-+	return ret;
-+}
-+
-+
-+u8 rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
-+{
-+#define RT_ASSERT_RET(expr)												\
-+	if (!(expr)) {															\
-+		printk("Assertion failed! %s at ......\n", #expr);							\
-+		printk("      ......%s,%s, line=%d\n",__FILE__, __FUNCTION__, __LINE__);	\
-+		return _FAIL;	\
-+	}
-+
-+	u8	offset, word_en;
-+	u8	*map;
-+	u8	newdata[PGPKT_DATA_SIZE];
-+	s32	i = 0, j = 0, idx;
-+	u8	ret = _SUCCESS;
-+	u16	mapLen = 0;
-+
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
-+
-+	if ((addr + cnts) > mapLen)
-+		return _FAIL;
-+
-+	RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */
-+	RT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */
-+
-+	map = rtw_zmalloc(mapLen);
-+	if (map == NULL)
-+		return _FAIL;
-+
-+	ret = rtw_BT_efuse_map_read(padapter, 0, mapLen, map);
-+	if (ret == _FAIL)
-+		goto exit;
-+	RTW_INFO("OFFSET\tVALUE(hex)\n");
-+	for (i = 0; i < 1024; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */
-+		RTW_INFO("0x%03x\t", i);
-+		for (j = 0; j < 8; j++)
-+			RTW_INFO("%02X ", map[i + j]);
-+		RTW_INFO("\t");
-+		for (; j < 16; j++)
-+			RTW_INFO("%02X ", map[i + j]);
-+		RTW_INFO("\n");
-+	}
-+	RTW_INFO("\n");
-+	Efuse_PowerSwitch(padapter, _TRUE, _TRUE);
-+
-+	idx = 0;
-+	offset = (addr >> 3);
-+	while (idx < cnts) {
-+		word_en = 0xF;
-+		j = (addr + idx) & 0x7;
-+		_rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE);
-+		for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
-+			if (data[idx] != map[addr + idx]) {
-+				word_en &= ~BIT(i >> 1);
-+				newdata[i] = data[idx];
-+			}
-+		}
-+
-+		if (word_en != 0xF) {
-+			RTW_INFO("offset=%x\n", offset);
-+			RTW_INFO("word_en=%x\n", word_en);
-+			RTW_INFO("%s: data=", __FUNCTION__);
-+			for (i = 0; i < PGPKT_DATA_SIZE; i++)
-+				RTW_INFO("0x%02X ", newdata[i]);
-+			RTW_INFO("\n");
-+			ret = Efuse_PgPacketWrite_BT(padapter, offset, word_en, newdata, _FALSE);
-+			if (ret == _FAIL)
-+				break;
-+		}
-+
-+		offset++;
-+	}
-+
-+	Efuse_PowerSwitch(padapter, _TRUE, _FALSE);
-+
-+exit:
-+
-+	rtw_mfree(map, mapLen);
-+
-+	return ret;
-+}
-+
-+/*-----------------------------------------------------------------------------
-+ * Function:	Efuse_ReadAllMap
-+ *
-+ * Overview:	Read All Efuse content
-+ *
-+ * Input:       NONE
-+ *
-+ * Output:      NONE
-+ *
-+ * Return:      NONE
-+ *
-+ * Revised History:
-+ * When			Who		Remark
-+ * 11/11/2008	MHC		Create Version 0.
-+ *
-+ *---------------------------------------------------------------------------*/
-+void
-+Efuse_ReadAllMap(
-+			PADAPTER	pAdapter,
-+			u8		efuseType,
-+			u8		*Efuse,
-+			BOOLEAN		bPseudoTest);
-+void
-+Efuse_ReadAllMap(
-+			PADAPTER	pAdapter,
-+			u8		efuseType,
-+			u8		*Efuse,
-+			BOOLEAN		bPseudoTest)
-+{
-+	u16	mapLen = 0;
-+
-+	Efuse_PowerSwitch(pAdapter, _FALSE, _TRUE);
-+
-+	EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, bPseudoTest);
-+
-+	efuse_ReadEFuse(pAdapter, efuseType, 0, mapLen, Efuse, bPseudoTest);
-+
-+	Efuse_PowerSwitch(pAdapter, _FALSE, _FALSE);
-+}
-+
-+/*-----------------------------------------------------------------------------
-+ * Function:	efuse_ShadowWrite1Byte
-+ *			efuse_ShadowWrite2Byte
-+ *			efuse_ShadowWrite4Byte
-+ *
-+ * Overview:	Write efuse modify map by one/two/four byte.
-+ *
-+ * Input:       NONE
-+ *
-+ * Output:      NONE
-+ *
-+ * Return:      NONE
-+ *
-+ * Revised History:
-+ * When			Who		Remark
-+ * 11/12/2008	MHC		Create Version 0.
-+ *
-+ *---------------------------------------------------------------------------*/
-+#ifdef PLATFORM
-+static void
-+efuse_ShadowWrite1Byte(
-+		PADAPTER	pAdapter,
-+		u16		Offset,
-+		u8		Value);
-+#endif /* PLATFORM */
-+static void
-+efuse_ShadowWrite1Byte(
-+		PADAPTER	pAdapter,
-+		u16		Offset,
-+		u8		Value)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
-+
-+	pHalData->efuse_eeprom_data[Offset] = Value;
-+
-+}	/* efuse_ShadowWrite1Byte */
-+
-+/* ---------------Write Two Bytes */
-+static void
-+efuse_ShadowWrite2Byte(
-+		PADAPTER	pAdapter,
-+		u16		Offset,
-+		u16		Value)
-+{
-+
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
-+
-+
-+	pHalData->efuse_eeprom_data[Offset] = Value & 0x00FF;
-+	pHalData->efuse_eeprom_data[Offset + 1] = Value >> 8;
-+
-+}	/* efuse_ShadowWrite1Byte */
-+
-+/* ---------------Write Four Bytes */
-+static void
-+efuse_ShadowWrite4Byte(
-+		PADAPTER	pAdapter,
-+		u16		Offset,
-+		u32		Value)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
-+
-+	pHalData->efuse_eeprom_data[Offset] = (u8)(Value & 0x000000FF);
-+	pHalData->efuse_eeprom_data[Offset + 1] = (u8)((Value >> 8) & 0x0000FF);
-+	pHalData->efuse_eeprom_data[Offset + 2] = (u8)((Value >> 16) & 0x00FF);
-+	pHalData->efuse_eeprom_data[Offset + 3] = (u8)((Value >> 24) & 0xFF);
-+
-+}	/* efuse_ShadowWrite1Byte */
-+
-+
-+/*-----------------------------------------------------------------------------
-+ * Function:	EFUSE_ShadowWrite
-+ *
-+ * Overview:	Write efuse modify map for later update operation to use!!!!!
-+ *
-+ * Input:       NONE
-+ *
-+ * Output:      NONE
-+ *
-+ * Return:      NONE
-+ *
-+ * Revised History:
-+ * When			Who		Remark
-+ * 11/12/2008	MHC		Create Version 0.
-+ *
-+ *---------------------------------------------------------------------------*/
-+void
-+EFUSE_ShadowWrite(
-+		PADAPTER	pAdapter,
-+		u8		Type,
-+		u16		Offset,
-+		u32		Value);
-+void
-+EFUSE_ShadowWrite(
-+		PADAPTER	pAdapter,
-+		u8		Type,
-+		u16		Offset,
-+		u32		Value)
-+{
-+#if (MP_DRIVER == 0)
-+	return;
-+#endif
-+	if (pAdapter->registrypriv.mp_mode == 0)
-+		return;
-+
-+
-+	if (Type == 1)
-+		efuse_ShadowWrite1Byte(pAdapter, Offset, (u8)Value);
-+	else if (Type == 2)
-+		efuse_ShadowWrite2Byte(pAdapter, Offset, (u16)Value);
-+	else if (Type == 4)
-+		efuse_ShadowWrite4Byte(pAdapter, Offset, (u32)Value);
-+
-+}	/* EFUSE_ShadowWrite */
-+
-+#endif /* !RTW_HALMAC */
-+/*-----------------------------------------------------------------------------
-+ * Function:	efuse_ShadowRead1Byte
-+ *			efuse_ShadowRead2Byte
-+ *			efuse_ShadowRead4Byte
-+ *
-+ * Overview:	Read from efuse init map by one/two/four bytes !!!!!
-+ *
-+ * Input:       NONE
-+ *
-+ * Output:      NONE
-+ *
-+ * Return:      NONE
-+ *
-+ * Revised History:
-+ * When			Who		Remark
-+ * 11/12/2008	MHC		Create Version 0.
-+ *
-+ *---------------------------------------------------------------------------*/
-+static void
-+efuse_ShadowRead1Byte(
-+		PADAPTER	pAdapter,
-+		u16		Offset,
-+		u8		*Value)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
-+
-+	*Value = pHalData->efuse_eeprom_data[Offset];
-+
-+}	/* EFUSE_ShadowRead1Byte */
-+
-+/* ---------------Read Two Bytes */
-+static void
-+efuse_ShadowRead2Byte(
-+		PADAPTER	pAdapter,
-+		u16		Offset,
-+		u16		*Value)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
-+
-+	*Value = pHalData->efuse_eeprom_data[Offset];
-+	*Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8;
-+
-+}	/* EFUSE_ShadowRead2Byte */
-+
-+/* ---------------Read Four Bytes */
-+static void
-+efuse_ShadowRead4Byte(
-+		PADAPTER	pAdapter,
-+		u16		Offset,
-+		u32		*Value)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
-+
-+	*Value = pHalData->efuse_eeprom_data[Offset];
-+	*Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8;
-+	*Value |= pHalData->efuse_eeprom_data[Offset + 2] << 16;
-+	*Value |= pHalData->efuse_eeprom_data[Offset + 3] << 24;
-+
-+}	/* efuse_ShadowRead4Byte */
-+
-+/*-----------------------------------------------------------------------------
-+ * Function:	EFUSE_ShadowRead
-+ *
-+ * Overview:	Read from pHalData->efuse_eeprom_data
-+ *---------------------------------------------------------------------------*/
-+void
-+EFUSE_ShadowRead(
-+			PADAPTER	pAdapter,
-+			u8		Type,
-+			u16		Offset,
-+			u32		*Value)
-+{
-+	if (Type == 1)
-+		efuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value);
-+	else if (Type == 2)
-+		efuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value);
-+	else if (Type == 4)
-+		efuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value);
-+
-+}	/* EFUSE_ShadowRead */
-+
-+/*  11/16/2008 MH Add description. Get current efuse area enabled word!!. */
-+u8
-+Efuse_CalculateWordCnts(u8	word_en)
-+{
-+	u8 word_cnts = 0;
-+	if (!(word_en & BIT(0)))
-+		word_cnts++; /* 0 : write enable */
-+	if (!(word_en & BIT(1)))
-+		word_cnts++;
-+	if (!(word_en & BIT(2)))
-+		word_cnts++;
-+	if (!(word_en & BIT(3)))
-+		word_cnts++;
-+	return word_cnts;
-+}
-+
-+/*-----------------------------------------------------------------------------
-+ * Function:	efuse_WordEnableDataRead
-+ *
-+ * Overview:	Read allowed word in current efuse section data.
-+ *
-+ * Input:       NONE
-+ *
-+ * Output:      NONE
-+ *
-+ * Return:      NONE
-+ *
-+ * Revised History:
-+ * When			Who		Remark
-+ * 11/16/2008	MHC		Create Version 0.
-+ * 11/21/2008	MHC		Fix Write bug when we only enable late word.
-+ *
-+ *---------------------------------------------------------------------------*/
-+void
-+efuse_WordEnableDataRead(u8	word_en,
-+				u8	*sourdata,
-+				u8	*targetdata)
-+{
-+	if (!(word_en & BIT(0))) {
-+		targetdata[0] = sourdata[0];
-+		targetdata[1] = sourdata[1];
-+	}
-+	if (!(word_en & BIT(1))) {
-+		targetdata[2] = sourdata[2];
-+		targetdata[3] = sourdata[3];
-+	}
-+	if (!(word_en & BIT(2))) {
-+		targetdata[4] = sourdata[4];
-+		targetdata[5] = sourdata[5];
-+	}
-+	if (!(word_en & BIT(3))) {
-+		targetdata[6] = sourdata[6];
-+		targetdata[7] = sourdata[7];
-+	}
-+}
-+
-+/*-----------------------------------------------------------------------------
-+ * Function:	EFUSE_ShadowMapUpdate
-+ *
-+ * Overview:	Transfer current EFUSE content to shadow init and modify map.
-+ *
-+ * Input:       NONE
-+ *
-+ * Output:      NONE
-+ *
-+ * Return:      NONE
-+ *
-+ * Revised History:
-+ * When			Who		Remark
-+ * 11/13/2008	MHC		Create Version 0.
-+ *
-+ *---------------------------------------------------------------------------*/
-+void EFUSE_ShadowMapUpdate(
-+	PADAPTER	pAdapter,
-+	u8		efuseType,
-+	BOOLEAN	bPseudoTest)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
-+	u16	mapLen = 0;
-+#ifdef RTW_HALMAC
-+	u8 *efuse_map = NULL;
-+	int err;
-+
-+
-+	mapLen = EEPROM_MAX_SIZE;
-+	efuse_map = pHalData->efuse_eeprom_data;
-+	/* efuse default content is 0xFF */
-+	_rtw_memset(efuse_map, 0xFF, EEPROM_MAX_SIZE);
-+
-+	EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, bPseudoTest);
-+	if (!mapLen) {
-+		RTW_WARN("%s: <ERROR> fail to get efuse size!\n", __FUNCTION__);
-+		mapLen = EEPROM_MAX_SIZE;
-+	}
-+	if (mapLen > EEPROM_MAX_SIZE) {
-+		RTW_WARN("%s: <ERROR> size of efuse data(%d) is large than expected(%d)!\n",
-+			 __FUNCTION__, mapLen, EEPROM_MAX_SIZE);
-+		mapLen = EEPROM_MAX_SIZE;
-+	}
-+
-+	if (pHalData->bautoload_fail_flag == _FALSE) {
-+		err = rtw_halmac_read_logical_efuse_map(adapter_to_dvobj(pAdapter), efuse_map, mapLen, NULL, 0);
-+		if (err)
-+			RTW_ERR("%s: <ERROR> fail to get efuse map!\n", __FUNCTION__);
-+	}
-+#else /* !RTW_HALMAC */
-+	EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, bPseudoTest);
-+
-+	if (pHalData->bautoload_fail_flag == _TRUE)
-+		_rtw_memset(pHalData->efuse_eeprom_data, 0xFF, mapLen);
-+	else {
-+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
-+		if (_SUCCESS != retriveAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pHalData->efuse_eeprom_data)) {
-+#endif
-+
-+			Efuse_ReadAllMap(pAdapter, efuseType, pHalData->efuse_eeprom_data, bPseudoTest);
-+
-+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
-+			storeAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pHalData->efuse_eeprom_data);
-+		}
-+#endif
-+	}
-+
-+	/* PlatformMoveMemory((void *)&pHalData->EfuseMap[EFUSE_MODIFY_MAP][0], */
-+	/* (void *)&pHalData->EfuseMap[EFUSE_INIT_MAP][0], mapLen); */
-+#endif /* !RTW_HALMAC */
-+
-+	rtw_mask_map_read(pAdapter, 0x00, mapLen, pHalData->efuse_eeprom_data);
-+
-+	rtw_dump_cur_efuse(pAdapter);
-+} /* EFUSE_ShadowMapUpdate */
-+
-+const u8 _mac_hidden_max_bw_to_hal_bw_cap[MAC_HIDDEN_MAX_BW_NUM] = {
-+	0,
-+	0,
-+	(BW_CAP_160M | BW_CAP_80M | BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),
-+	(BW_CAP_5M),
-+	(BW_CAP_10M | BW_CAP_5M),
-+	(BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),
-+	(BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),
-+	(BW_CAP_80M | BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M),
-+};
-+
-+const u8 _mac_hidden_proto_to_hal_proto_cap[MAC_HIDDEN_PROTOCOL_NUM] = {
-+	0,
-+	0,
-+	(PROTO_CAP_11N | PROTO_CAP_11G | PROTO_CAP_11B),
-+	(PROTO_CAP_11AC | PROTO_CAP_11N | PROTO_CAP_11G | PROTO_CAP_11B),
-+};
-+
-+u8 mac_hidden_wl_func_to_hal_wl_func(u8 func)
-+{
-+	u8 wl_func = 0;
-+
-+	if (func & BIT0)
-+		wl_func |= WL_FUNC_MIRACAST;
-+	if (func & BIT1)
-+		wl_func |= WL_FUNC_P2P;
-+	if (func & BIT2)
-+		wl_func |= WL_FUNC_TDLS;
-+	if (func & BIT3)
-+		wl_func |= WL_FUNC_FTM;
-+
-+	return wl_func;
-+}
-+
-+#ifdef PLATFORM_LINUX
-+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
-+/* #include <rtw_eeprom.h> */
-+
-+int isAdaptorInfoFileValid(void)
-+{
-+	return _TRUE;
-+}
-+
-+int storeAdaptorInfoFile(char *path, u8 *efuse_data)
-+{
-+	int ret = _SUCCESS;
-+
-+	if (path && efuse_data) {
-+		ret = rtw_store_to_file(path, efuse_data, EEPROM_MAX_SIZE_512);
-+		if (ret == EEPROM_MAX_SIZE)
-+			ret = _SUCCESS;
-+		else
-+			ret = _FAIL;
-+	} else {
-+		RTW_INFO("%s NULL pointer\n", __FUNCTION__);
-+		ret =  _FAIL;
-+	}
-+	return ret;
-+}
-+
-+int retriveAdaptorInfoFile(char *path, u8 *efuse_data)
-+{
-+	int ret = _SUCCESS;
-+	mm_segment_t oldfs;
-+	struct file *fp;
-+
-+	if (path && efuse_data) {
-+
-+		ret = rtw_retrieve_from_file(path, efuse_data, EEPROM_MAX_SIZE);
-+
-+		if (ret == EEPROM_MAX_SIZE)
-+			ret = _SUCCESS;
-+		else
-+			ret = _FAIL;
-+
-+#if 0
-+		if (isAdaptorInfoFileValid())
-+			return 0;
-+		else
-+			return _FAIL;
-+#endif
-+
-+	} else {
-+		RTW_INFO("%s NULL pointer\n", __FUNCTION__);
-+		ret = _FAIL;
-+	}
-+	return ret;
-+}
-+#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */
-+
-+u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepath, u8 *buf, u32 len)
-+{
-+	char *ptmpbuf = NULL, *ptr;
-+	u8 val8;
-+	u32 count, i, j;
-+	int err;
-+	u32 bufsize = 4096;
-+
-+	ptmpbuf = rtw_zmalloc(bufsize);
-+	if (ptmpbuf == NULL)
-+		return _FALSE;
-+
-+	count = rtw_retrieve_from_file(filepath, ptmpbuf, bufsize);
-+	if (count <= 90) {
-+		rtw_mfree(ptmpbuf, bufsize);
-+		RTW_ERR("%s, filepatch %s, size=%d, FAIL!!\n", __FUNCTION__, filepath, count);
-+		return _FALSE;
-+	}
-+	i = 0;
-+	j = 0;
-+	ptr = ptmpbuf;
-+	while ((j < len) && (i < count)) {
-+		if (ptmpbuf[i] == '\0')
-+			break;
-+		ptr = strpbrk(&ptmpbuf[i], " \t\n\r");
-+		if (ptr) {
-+			if (ptr == &ptmpbuf[i]) {
-+				i++;
-+				continue;
-+			}
-+			/* Add string terminating null */
-+			*ptr = 0;
-+		} else {
-+			ptr = &ptmpbuf[count-1];
-+		}
-+
-+		err = sscanf(&ptmpbuf[i], "%hhx", &val8);
-+		if (err != 1) {
-+			RTW_WARN("Something wrong to parse efuse file, string=%s\n", &ptmpbuf[i]);
-+		} else {
-+			buf[j] = val8;
-+			RTW_DBG("i=%d, j=%d, 0x%02x\n", i, j, buf[j]);
-+			j++;
-+		}
-+		i = ptr - ptmpbuf + 1;
-+	}
-+	rtw_mfree(ptmpbuf, bufsize);
-+	RTW_INFO("%s, filepatch %s, size=%d, done\n", __FUNCTION__, filepath, count);
-+	return _TRUE;
-+}
-+
-+
-+u8 rtw_efuse_file_store(PADAPTER padapter, u8 *filepath, u8 *buf, u32 len)
-+{
-+	int err = 0, i = 0, j = 0, mapLen = 0 ;
-+	char *cbuf, *pchr;
-+
-+	cbuf = rtw_zmalloc(len * 3);
-+	pchr = cbuf;
-+
-+	if (filepath && buf) {
-+		if (cbuf == NULL) {
-+			RTW_INFO("%s, malloc cbuf _FAIL\n", __FUNCTION__);
-+			err = _FAIL;
-+		} else {
-+			for (i = 0; i <= len; i += 16) {
-+				for (j = 0; j < 16; j++)
-+					pchr += sprintf(pchr, "%02X ", buf[i + j]);
-+				pchr += sprintf(pchr, "\n");
-+			}
-+
-+			err = rtw_store_to_file(filepath, cbuf, strlen(cbuf));
-+			RTW_INFO("%s, rtw_store_to_file len=%d,err =%d, len(cbuf)=%zd\n", __FUNCTION__, len, err, strlen(cbuf));
-+			if (err == strlen(cbuf)) {
-+				err = _SUCCESS;
-+				RTW_INFO("%s, filepatch %s, len=%d, done\n", __FUNCTION__, filepath, len);
-+			} else {
-+				err = _FAIL;
-+				RTW_INFO("%s, filepatch %s, len=%d,err =%d, _FAIL\n", __FUNCTION__, filepath, len, err);
-+			}
-+		}
-+	}
-+	if (cbuf)
-+		rtw_mfree(cbuf, len * 3);
-+
-+	return err;
-+}
-+
-+#ifdef CONFIG_EFUSE_CONFIG_FILE
-+u32 rtw_read_efuse_from_file(const char *path, u8 *buf, int map_size)
-+{
-+	u32 i;
-+	u8 c;
-+	u8 temp[3];
-+	u8 temp_i;
-+	u8 end = _FALSE;
-+	u32 ret = _FAIL;
-+
-+	u8 *file_data = NULL;
-+	u32 file_size, read_size, pos = 0;
-+	u8 *map = NULL;
-+
-+	if (rtw_is_file_readable_with_size(path, &file_size) != _TRUE) {
-+		RTW_PRINT("%s %s is not readable\n", __func__, path);
-+		goto exit;
-+	}
-+
-+	file_data = rtw_vmalloc(file_size);
-+	if (!file_data) {
-+		RTW_ERR("%s rtw_vmalloc(%d) fail\n", __func__, file_size);
-+		goto exit;
-+	}
-+
-+	read_size = rtw_retrieve_from_file(path, file_data, file_size);
-+	if (read_size == 0) {
-+		RTW_ERR("%s read from %s fail\n", __func__, path);
-+		goto exit;
-+	}
-+
-+	map = rtw_vmalloc(map_size);
-+	if (!map) {
-+		RTW_ERR("%s rtw_vmalloc(%d) fail\n", __func__, map_size);
-+		goto exit;
-+	}
-+	_rtw_memset(map, 0xff, map_size);
-+
-+	temp[2] = 0; /* end of string '\0' */
-+
-+	for (i = 0 ; i < map_size ; i++) {
-+		temp_i = 0;
-+
-+		while (1) {
-+			if (pos >= read_size) {
-+				end = _TRUE;
-+				break;
-+			}
-+			c = file_data[pos++];
-+
-+			/* bypass spece or eol or null before first hex digit */
-+			if (temp_i == 0 && (is_eol(c) == _TRUE || is_space(c) == _TRUE || is_null(c) == _TRUE))
-+				continue;
-+
-+			if (IsHexDigit(c) == _FALSE) {
-+				RTW_ERR("%s invalid 8-bit hex format for offset:0x%03x\n", __func__, i);
-+				goto exit;
-+			}
-+
-+			temp[temp_i++] = c;
-+
-+			if (temp_i == 2) {
-+				/* parse value */
-+				if (sscanf(temp, "%hhx", &map[i]) != 1) {
-+					RTW_ERR("%s sscanf fail for offset:0x%03x\n", __func__, i);
-+					goto exit;
-+				}
-+				break;
-+			}
-+		}
-+
-+		if (end == _TRUE) {
-+			if (temp_i != 0) {
-+				RTW_ERR("%s incomplete 8-bit hex format for offset:0x%03x\n", __func__, i);
-+				goto exit;
-+			}
-+			break;
-+		}
-+	}
-+
-+	RTW_PRINT("efuse file:%s, 0x%03x byte content read\n", path, i);
-+
-+	_rtw_memcpy(buf, map, map_size);
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	if (file_data)
-+		rtw_vmfree(file_data, file_size);
-+	if (map)
-+		rtw_vmfree(map, map_size);
-+
-+	return ret;
-+}
-+
-+u32 rtw_read_macaddr_from_file(const char *path, u8 *buf)
-+{
-+	u32 i;
-+	u8 temp[3];
-+	u32 ret = _FAIL;
-+
-+	u8 file_data[17];
-+	u32 read_size;
-+	u8 addr[ETH_ALEN];
-+
-+	if (rtw_is_file_readable(path) != _TRUE) {
-+		RTW_PRINT("%s %s is not readable\n", __func__, path);
-+		goto exit;
-+	}
-+
-+	read_size = rtw_retrieve_from_file(path, file_data, 17);
-+	if (read_size != 17) {
-+		RTW_ERR("%s read from %s fail\n", __func__, path);
-+		goto exit;
-+	}
-+
-+	temp[2] = 0; /* end of string '\0' */
-+
-+	for (i = 0 ; i < ETH_ALEN ; i++) {
-+		if (IsHexDigit(file_data[i * 3]) == _FALSE || IsHexDigit(file_data[i * 3 + 1]) == _FALSE) {
-+			RTW_ERR("%s invalid 8-bit hex format for address offset:%u\n", __func__, i);
-+			goto exit;
-+		}
-+
-+		if (i < ETH_ALEN - 1 && file_data[i * 3 + 2] != ':') {
-+			RTW_ERR("%s invalid separator after address offset:%u\n", __func__, i);
-+			goto exit;
-+		}
-+
-+		temp[0] = file_data[i * 3];
-+		temp[1] = file_data[i * 3 + 1];
-+		if (sscanf(temp, "%hhx", &addr[i]) != 1) {
-+			RTW_ERR("%s sscanf fail for address offset:0x%03x\n", __func__, i);
-+			goto exit;
-+		}
-+	}
-+
-+	_rtw_memcpy(buf, addr, ETH_ALEN);
-+
-+	RTW_PRINT("wifi_mac file: %s\n", path);
-+#ifdef CONFIG_RTW_DEBUG
-+	RTW_INFO(MAC_FMT"\n", MAC_ARG(buf));
-+#endif
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_EFUSE_CONFIG_FILE */
-+
-+#endif /* PLATFORM_LINUX */
-diff --git a/drivers/staging/rtl8723cs/core/mesh/rtw_mesh.c b/drivers/staging/rtl8723cs/core/mesh/rtw_mesh.c
-new file mode 100644
-index 000000000000..41a311128935
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/mesh/rtw_mesh.c
-@@ -0,0 +1,4392 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_MESH_C_
-+
-+#ifdef CONFIG_RTW_MESH
-+#include <drv_types.h>
-+
-+const char *_rtw_mesh_plink_str[] = {
-+	"UNKNOWN",
-+	"LISTEN",
-+	"OPN_SNT",
-+	"OPN_RCVD",
-+	"CNF_RCVD",
-+	"ESTAB",
-+	"HOLDING",
-+	"BLOCKED",
-+};
-+
-+const char *_rtw_mesh_ps_str[] = {
-+	"UNKNOWN",
-+	"ACTIVE",
-+	"LSLEEP",
-+	"DSLEEP",
-+};
-+
-+const char *_action_self_protected_str[] = {
-+	"ACT_SELF_PROTECTED_RSVD",
-+	"MESH_OPEN",
-+	"MESH_CONF",
-+	"MESH_CLOSE",
-+	"MESH_GK_INFORM",
-+	"MESH_GK_ACK",
-+};
-+
-+inline u8 *rtw_set_ie_mesh_id(u8 *buf, u32 *buf_len, const char *mesh_id, u8 id_len)
-+{
-+	return rtw_set_ie(buf, WLAN_EID_MESH_ID, id_len, mesh_id, buf_len);
-+}
-+
-+inline u8 *rtw_set_ie_mesh_config(u8 *buf, u32 *buf_len
-+	, u8 path_sel_proto, u8 path_sel_metric, u8 congest_ctl_mode, u8 sync_method, u8 auth_proto
-+	, u8 num_of_peerings, bool cto_mgate, bool cto_as
-+	, bool accept_peerings, bool mcca_sup, bool mcca_en, bool forwarding
-+	, bool mbca_en, bool tbtt_adj, bool ps_level)
-+{
-+
-+	u8 conf[7] = {0};
-+
-+	SET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(conf, path_sel_proto);
-+	SET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(conf, path_sel_metric);
-+	SET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(conf, congest_ctl_mode);
-+	SET_MESH_CONF_ELE_SYNC_METHOD_ID(conf, sync_method);
-+	SET_MESH_CONF_ELE_AUTH_PROTO_ID(conf, auth_proto);
-+
-+	SET_MESH_CONF_ELE_CTO_MGATE(conf, cto_mgate);
-+	SET_MESH_CONF_ELE_NUM_OF_PEERINGS(conf, num_of_peerings);
-+	SET_MESH_CONF_ELE_CTO_AS(conf, cto_as);
-+
-+	SET_MESH_CONF_ELE_ACCEPT_PEERINGS(conf, accept_peerings);
-+	SET_MESH_CONF_ELE_MCCA_SUP(conf, mcca_sup);
-+	SET_MESH_CONF_ELE_MCCA_EN(conf, mcca_en);
-+	SET_MESH_CONF_ELE_FORWARDING(conf, forwarding);
-+	SET_MESH_CONF_ELE_MBCA_EN(conf, mbca_en);
-+	SET_MESH_CONF_ELE_TBTT_ADJ(conf, tbtt_adj);
-+	SET_MESH_CONF_ELE_PS_LEVEL(conf, ps_level);
-+
-+	return rtw_set_ie(buf, WLAN_EID_MESH_CONFIG, 7, conf, buf_len);
-+}
-+
-+inline u8 *rtw_set_ie_mpm(u8 *buf, u32 *buf_len
-+	, u8 proto_id, u16 llid, u16 *plid, u16 *reason, u8 *chosen_pmk)
-+{
-+	u8 data[24] = {0};
-+	u8 *pos = data;
-+
-+	RTW_PUT_LE16(pos, proto_id);
-+	pos += 2;
-+
-+	RTW_PUT_LE16(pos, llid);
-+	pos += 2;
-+
-+	if (plid) {
-+		RTW_PUT_LE16(pos, *plid);
-+		pos += 2;
-+	}
-+
-+	if (reason) {
-+		RTW_PUT_LE16(pos, *reason);
-+		pos += 2;
-+	}
-+
-+	if (chosen_pmk) {
-+		_rtw_memcpy(pos, chosen_pmk, 16);
-+		pos += 16;
-+	}
-+
-+	return rtw_set_ie(buf, WLAN_EID_MPM, pos - data, data, buf_len);
-+}
-+
-+bool rtw_bss_is_forwarding(WLAN_BSSID_EX *bss)
-+{
-+	u8 *ie;
-+	int ie_len;
-+	bool ret = 0;
-+
-+	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
-+			BSS_EX_TLV_IES_LEN(bss));
-+	if (!ie || ie_len != 7)
-+		goto exit;
-+
-+	ret = GET_MESH_CONF_ELE_FORWARDING(ie + 2);
-+
-+exit:
-+	return ret;
-+}
-+
-+bool rtw_bss_is_cto_mgate(WLAN_BSSID_EX *bss)
-+{
-+	u8 *ie;
-+	int ie_len;
-+	bool ret = 0;
-+
-+	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
-+			BSS_EX_TLV_IES_LEN(bss));
-+	if (!ie || ie_len != 7)
-+		goto exit;
-+
-+	ret = GET_MESH_CONF_ELE_CTO_MGATE(ie + 2);
-+
-+exit:
-+	return ret;
-+}
-+
-+int _rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b, u8 **a_mconf_ie_r, u8 **b_mconf_ie_r)
-+{
-+	int ret = 0;
-+	u8 *a_mconf_ie, *b_mconf_ie;
-+	sint a_mconf_ie_len, b_mconf_ie_len;
-+
-+	if (a->InfrastructureMode != Ndis802_11_mesh)
-+		goto exit;
-+	a_mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(a), WLAN_EID_MESH_CONFIG, &a_mconf_ie_len, BSS_EX_TLV_IES_LEN(a));
-+	if (!a_mconf_ie || a_mconf_ie_len != 7)
-+		goto exit;
-+	if (a_mconf_ie_r)
-+		*a_mconf_ie_r = a_mconf_ie;
-+
-+	if (b->InfrastructureMode != Ndis802_11_mesh)
-+		goto exit;
-+	b_mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(b), WLAN_EID_MESH_CONFIG, &b_mconf_ie_len, BSS_EX_TLV_IES_LEN(b));
-+	if (!b_mconf_ie || b_mconf_ie_len != 7)
-+		goto exit;
-+	if (b_mconf_ie_r)
-+		*b_mconf_ie_r = b_mconf_ie;
-+
-+	if (a->mesh_id.SsidLength != b->mesh_id.SsidLength
-+		|| _rtw_memcmp(a->mesh_id.Ssid, b->mesh_id.Ssid, a->mesh_id.SsidLength) == _FALSE)
-+		goto exit;
-+
-+	if (_rtw_memcmp(a_mconf_ie + 2, b_mconf_ie + 2, 5) == _FALSE)
-+		goto exit;
-+
-+	ret = 1;
-+
-+exit:
-+	return ret;
-+}
-+
-+int rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b)
-+{
-+	return _rtw_bss_is_same_mbss(a, b, NULL, NULL);
-+}
-+
-+int rtw_bss_is_candidate_mesh_peer(_adapter *adapter, WLAN_BSSID_EX *target, u8 ch, u8 add_peer)
-+{
-+	int ret = 0;
-+	WLAN_BSSID_EX *self = &adapter->mlmepriv.cur_network.network;
-+	u8 *s_mconf_ie, *t_mconf_ie;
-+	u8 auth_pid;
-+	int i, j;
-+
-+	if (ch && self->Configuration.DSConfig != target->Configuration.DSConfig)
-+		goto exit;
-+
-+	if (!_rtw_bss_is_same_mbss(self, target, &s_mconf_ie, &t_mconf_ie))
-+		goto exit;
-+
-+	if (add_peer) {
-+		/* Accept additional mesh peerings */
-+		if (GET_MESH_CONF_ELE_ACCEPT_PEERINGS(t_mconf_ie + 2) == 0)
-+			goto exit;
-+	}
-+
-+	/* BSSBasicRateSet */
-+	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
-+		if (target->SupportedRates[i] == 0)
-+			break;	
-+		if (target->SupportedRates[i] & 0x80) {
-+			u8 match = 0;
-+
-+			if (!ch) {
-+				/* off-channel, check target with our hardcode capability */
-+				if (target->Configuration.DSConfig > 14)
-+					match = rtw_is_basic_rate_ofdm(target->SupportedRates[i]);
-+				else
-+					match = rtw_is_basic_rate_mix(target->SupportedRates[i]);
-+			} else { 
-+				for (j = 0; j < NDIS_802_11_LENGTH_RATES_EX; j++) {
-+					if (self->SupportedRates[j] == 0)
-+						break;
-+					if (self->SupportedRates[j] == target->SupportedRates[i]) {
-+						match = 1;
-+						break;
-+					}
-+				}
-+			}
-+			if (!match)
-+				goto exit;
-+		}
-+	}
-+
-+	/* BSSBasicMCSSet */
-+
-+
-+	auth_pid = GET_MESH_CONF_ELE_AUTH_PROTO_ID(s_mconf_ie + 2);
-+	if (auth_pid && auth_pid <= 2) {
-+		struct security_priv *sec = &adapter->securitypriv;
-+		u8 *rsn_ie;
-+		int rsn_ie_len;
-+		int group_cipher = 0, pairwise_cipher = 0, gmcs = 0;
-+		u8 mfp_opt = MFP_NO;
-+
-+		/* 802.1X connected to AS ? */
-+
-+		/* RSN */
-+		rsn_ie = rtw_get_wpa2_ie(BSS_EX_TLV_IES(target), &rsn_ie_len, BSS_EX_TLV_IES_LEN(target));
-+		if (!rsn_ie || rsn_ie_len == 0)
-+			goto exit;
-+		if (rtw_parse_wpa2_ie(rsn_ie, rsn_ie_len + 2, &group_cipher, &pairwise_cipher, &gmcs, NULL, &mfp_opt) != _SUCCESS)
-+			goto exit;
-+		if ((sec->mfp_opt == MFP_REQUIRED && mfp_opt < MFP_OPTIONAL)
-+			|| (mfp_opt == MFP_REQUIRED && sec->mfp_opt < MFP_OPTIONAL))
-+			goto exit;
-+		if (!(sec->wpa2_group_cipher & group_cipher))
-+			goto exit;
-+		if (!(sec->wpa2_pairwise_cipher & pairwise_cipher))
-+			goto exit;
-+		#ifdef CONFIG_IEEE80211W
-+		if ((sec->mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL)
-+			&& security_type_bip_to_gmcs(sec->dot11wCipher) != gmcs)
-+			goto exit;
-+		#endif
-+	}
-+
-+	ret = 1;
-+
-+exit:
-+	return ret;
-+}
-+
-+void rtw_mesh_bss_peering_status(WLAN_BSSID_EX *bss, u8 *nop, u8 *accept)
-+{
-+	u8 *ie;
-+	int ie_len;
-+
-+	if (nop)
-+		*nop = 0;
-+	if (accept)
-+		*accept = 0;
-+
-+	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
-+			BSS_EX_TLV_IES_LEN(bss));
-+	if (!ie || ie_len != 7)
-+		goto exit;
-+
-+	if (nop)
-+		*nop = GET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2);
-+	if (accept)
-+		*accept = GET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2);
-+
-+exit:
-+	return;
-+}
-+
-+#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+void rtw_mesh_update_scanned_acnode_status(_adapter *adapter, struct wlan_network *scanned)
-+{
-+	bool acnode;
-+	u8 nop, accept;
-+
-+	rtw_mesh_bss_peering_status(&scanned->network, &nop, &accept);
-+
-+	acnode = !nop && accept;
-+
-+	if (acnode && scanned->acnode_stime == 0) {
-+		scanned->acnode_stime = rtw_get_current_time();
-+		if (scanned->acnode_stime == 0)
-+			scanned->acnode_stime++;
-+	} else if (!acnode) {
-+		scanned->acnode_stime = 0;
-+		scanned->acnode_notify_etime = 0;
-+	}
-+}
-+
-+bool rtw_mesh_scanned_is_acnode_confirmed(_adapter *adapter, struct wlan_network *scanned)
-+{
-+	return scanned->acnode_stime
-+			&& rtw_get_passing_time_ms(scanned->acnode_stime)
-+				> adapter->mesh_cfg.peer_sel_policy.acnode_conf_timeout_ms;
-+}
-+
-+static bool rtw_mesh_scanned_is_acnode_allow_notify(_adapter *adapter, struct wlan_network *scanned)
-+{
-+	return scanned->acnode_notify_etime
-+			&& rtw_time_after(scanned->acnode_notify_etime, rtw_get_current_time());
-+}
-+
-+bool rtw_mesh_acnode_prevent_allow_sacrifice(_adapter *adapter)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	bool allow = 0;
-+
-+	if (!mcfg->peer_sel_policy.acnode_prevent
-+		|| mcfg->max_peer_links <= 1
-+		|| stapriv->asoc_list_cnt < mcfg->max_peer_links)
-+		goto exit;
-+
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	if (rtw_mesh_cto_mgate_required(adapter))
-+		goto exit;
-+#endif
-+
-+	allow = 1;
-+
-+exit:
-+	return allow;
-+}
-+
-+static bool rtw_mesh_acnode_candidate_exist(_adapter *adapter)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+	_queue *queue = &(mlme->scanned_queue);
-+	_list *head, *list;
-+	_irqL irqL;
-+	struct wlan_network *scanned = NULL;
-+	struct sta_info *sta = NULL;
-+	bool need = 0;
-+
-+	_enter_critical_bh(&(mlme->scanned_queue.lock), &irqL);
-+
-+	head = get_list_head(queue);
-+	list = get_next(head);
-+	while (!rtw_end_of_queue_search(head, list)) {
-+		scanned = LIST_CONTAINOR(list, struct wlan_network, list);
-+		list = get_next(list);
-+
-+		if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms
-+			&& rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned)
-+			&& (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi)
-+			#if CONFIG_RTW_MACADDR_ACL
-+			&& rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE
-+			#endif
-+			&& rtw_bss_is_candidate_mesh_peer(adapter, &scanned->network, 1, 1)
-+			#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+			&& !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
-+			#endif
-+			#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+			&& rtw_mesh_cto_mgate_network_filter(adapter, scanned)
-+			#endif
-+		) {
-+			need = 1;
-+			break;
-+		}
-+	}
-+
-+	_exit_critical_bh(&(mlme->scanned_queue.lock), &irqL);
-+
-+	return need;
-+}
-+
-+static int rtw_mesh_acnode_prevent_sacrifice_chk(_adapter *adapter, struct sta_info **sac, struct sta_info *com)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	int updated = 0;
-+
-+	/*
-+	* TODO: compare next_hop reference cnt of forwarding info
-+	* don't sacrifice working next_hop or choose sta with least cnt
-+	*/
-+
-+	if (*sac == NULL) {
-+		updated = 1;
-+		goto exit;
-+	}
-+
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	if (mcfg->peer_sel_policy.cto_mgate_require
-+		&& !mcfg->dot11MeshGateAnnouncementProtocol
-+	) {
-+		if (IS_CTO_MGATE_CONF_TIMEOUT(com->plink)) {
-+			if (!IS_CTO_MGATE_CONF_TIMEOUT((*sac)->plink)) {
-+				/* blacklist > not blacklist */
-+				updated = 1;
-+				goto exit;
-+			}
-+		} else if (!IS_CTO_MGATE_CONF_DISABLED(com->plink)) {
-+			if (IS_CTO_MGATE_CONF_DISABLED((*sac)->plink)) {
-+				/* confirming > disabled */
-+				updated = 1;
-+				goto exit;
-+			}
-+		}
-+	}
-+#endif
-+
-+exit:
-+	if (updated)
-+		*sac = com;
-+
-+	return updated;
-+}
-+
-+struct sta_info *_rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	_list *head, *list;
-+	struct sta_info *sta, *sacrifice = NULL;
-+	u8 nop;
-+
-+	head = &stapriv->asoc_list;
-+	list = get_next(head);
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
-+		list = get_next(list);
-+
-+		if (!sta->plink || !sta->plink->scanned) {
-+			rtw_warn_on(1);
-+			continue;
-+		}
-+
-+		rtw_mesh_bss_peering_status(&sta->plink->scanned->network, &nop, NULL);
-+		if (nop < 2)
-+			continue;
-+
-+		rtw_mesh_acnode_prevent_sacrifice_chk(adapter, &sacrifice, sta);
-+	}
-+
-+	return sacrifice;
-+}
-+
-+struct sta_info *rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct sta_info *sacrifice = NULL;
-+
-+	enter_critical_bh(&stapriv->asoc_list_lock);
-+
-+	sacrifice = _rtw_mesh_acnode_prevent_pick_sacrifice(adapter);
-+
-+	exit_critical_bh(&stapriv->asoc_list_lock);
-+
-+	return sacrifice;
-+}
-+
-+static void rtw_mesh_acnode_rsvd_chk(_adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	u8 acnode_rsvd = 0;
-+
-+	if (rtw_mesh_acnode_prevent_allow_sacrifice(adapter)
-+		&& rtw_mesh_acnode_prevent_pick_sacrifice(adapter)
-+		&& rtw_mesh_acnode_candidate_exist(adapter))
-+		acnode_rsvd = 1;
-+
-+	if (plink_ctl->acnode_rsvd != acnode_rsvd) {
-+		plink_ctl->acnode_rsvd = acnode_rsvd;
-+		RTW_INFO(FUNC_ADPT_FMT" acnode_rsvd = %d\n", FUNC_ADPT_ARG(adapter), plink_ctl->acnode_rsvd);
-+		update_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, 1, 0);
-+	}
-+}
-+
-+static void rtw_mesh_acnode_set_notify_etime(_adapter *adapter, u8 *rframe_whdr)
-+{
-+	if (adapter->mesh_info.plink_ctl.acnode_rsvd) {
-+		struct wlan_network *scanned = rtw_find_network(&adapter->mlmepriv.scanned_queue, get_addr2_ptr(rframe_whdr));
-+
-+		if (rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned)) {
-+			scanned->acnode_notify_etime = rtw_get_current_time()
-+				+ rtw_ms_to_systime(adapter->mesh_cfg.peer_sel_policy.acnode_notify_timeout_ms);
-+			if (scanned->acnode_notify_etime == 0)
-+				scanned->acnode_notify_etime++;
-+		}
-+	}
-+}
-+
-+void dump_mesh_acnode_prevent_settings(void *sel, _adapter *adapter)
-+{
-+	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
-+
-+	RTW_PRINT_SEL(sel, "%-6s %-12s %-14s\n"
-+		, "enable", "conf_timeout", "nofity_timeout");
-+	RTW_PRINT_SEL(sel, "%6u %12u %14u\n"
-+		, peer_sel_policy->acnode_prevent
-+		, peer_sel_policy->acnode_conf_timeout_ms
-+		, peer_sel_policy->acnode_notify_timeout_ms);
-+}
-+#endif /* CONFIG_RTW_MESH_ACNODE_PREVENT */
-+
-+#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+int rtw_mesh_peer_blacklist_add(_adapter *adapter, const u8 *addr)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+
-+	return rtw_blacklist_add(&plink_ctl->peer_blacklist, addr
-+		, mcfg->peer_sel_policy.peer_blacklist_timeout_ms);
-+}
-+
-+int rtw_mesh_peer_blacklist_del(_adapter *adapter, const u8 *addr)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+
-+	return rtw_blacklist_del(&plink_ctl->peer_blacklist, addr);
-+}
-+
-+int rtw_mesh_peer_blacklist_search(_adapter *adapter, const u8 *addr)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+
-+	return rtw_blacklist_search(&plink_ctl->peer_blacklist, addr);
-+}
-+
-+void rtw_mesh_peer_blacklist_flush(_adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+
-+	rtw_blacklist_flush(&plink_ctl->peer_blacklist);
-+}
-+
-+void dump_mesh_peer_blacklist(void *sel, _adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+
-+	dump_blacklist(sel, &plink_ctl->peer_blacklist, "blacklist");
-+}
-+
-+void dump_mesh_peer_blacklist_settings(void *sel, _adapter *adapter)
-+{
-+	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
-+
-+	RTW_PRINT_SEL(sel, "%-12s %-17s\n"
-+		, "conf_timeout", "blacklist_timeout");
-+	RTW_PRINT_SEL(sel, "%12u %17u\n"
-+		, peer_sel_policy->peer_conf_timeout_ms
-+		, peer_sel_policy->peer_blacklist_timeout_ms);
-+}
-+#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */
-+
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+u8 rtw_mesh_cto_mgate_required(_adapter *adapter)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+
-+	return mcfg->peer_sel_policy.cto_mgate_require
-+		&& !rtw_bss_is_cto_mgate(&(mlmeext->mlmext_info.network));
-+}
-+
-+u8 rtw_mesh_cto_mgate_network_filter(_adapter *adapter, struct wlan_network *scanned)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+
-+	return !rtw_mesh_cto_mgate_required(adapter)
-+			|| (rtw_bss_is_cto_mgate(&scanned->network)
-+				&& !rtw_mesh_cto_mgate_blacklist_search(adapter, scanned->network.MacAddress));
-+}
-+
-+int rtw_mesh_cto_mgate_blacklist_add(_adapter *adapter, const u8 *addr)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+
-+	return rtw_blacklist_add(&plink_ctl->cto_mgate_blacklist, addr
-+		, mcfg->peer_sel_policy.cto_mgate_blacklist_timeout_ms);
-+}
-+
-+int rtw_mesh_cto_mgate_blacklist_del(_adapter *adapter, const u8 *addr)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+
-+	return rtw_blacklist_del(&plink_ctl->cto_mgate_blacklist, addr);
-+}
-+
-+int rtw_mesh_cto_mgate_blacklist_search(_adapter *adapter, const u8 *addr)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+
-+	return rtw_blacklist_search(&plink_ctl->cto_mgate_blacklist, addr);
-+}
-+
-+void rtw_mesh_cto_mgate_blacklist_flush(_adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+
-+	rtw_blacklist_flush(&plink_ctl->cto_mgate_blacklist);
-+}
-+
-+void dump_mesh_cto_mgate_blacklist(void *sel, _adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+
-+	dump_blacklist(sel, &plink_ctl->cto_mgate_blacklist, "blacklist");
-+}
-+
-+void dump_mesh_cto_mgate_blacklist_settings(void *sel, _adapter *adapter)
-+{
-+	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
-+
-+	RTW_PRINT_SEL(sel, "%-12s %-17s\n"
-+		, "conf_timeout", "blacklist_timeout");
-+	RTW_PRINT_SEL(sel, "%12u %17u\n"
-+		, peer_sel_policy->cto_mgate_conf_timeout_ms
-+		, peer_sel_policy->cto_mgate_blacklist_timeout_ms);
-+}
-+
-+static void rtw_mesh_cto_mgate_blacklist_chk(_adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	_queue *blist = &plink_ctl->cto_mgate_blacklist;
-+	_list *list, *head;
-+	struct blacklist_ent *ent = NULL;
-+	struct wlan_network *scanned = NULL;
-+
-+	enter_critical_bh(&blist->lock);
-+	head = &blist->queue;
-+	list = get_next(head);
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
-+		list = get_next(list);
-+
-+		if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
-+			rtw_list_delete(&ent->list);
-+			rtw_mfree(ent, sizeof(struct blacklist_ent));
-+			continue;
-+		}
-+
-+		scanned = rtw_find_network(&adapter->mlmepriv.scanned_queue, ent->addr);
-+		if (!scanned)
-+			continue;
-+
-+		if (rtw_bss_is_forwarding(&scanned->network)) {
-+			rtw_list_delete(&ent->list);
-+			rtw_mfree(ent, sizeof(struct blacklist_ent));
-+		}
-+	}
-+
-+	exit_critical_bh(&blist->lock);
-+}
-+#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
-+
-+void rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scanned)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	bool acnode = 0;
-+
-+	if (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl))
-+		goto exit;
-+
-+	if (plink_ctl->num >= RTW_MESH_MAX_PEER_CANDIDATES)
-+		goto exit;
-+
-+#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+	if (plink_ctl->acnode_rsvd) {
-+		acnode = rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned);
-+		if (acnode && !rtw_mesh_scanned_is_acnode_allow_notify(adapter, scanned))
-+			goto exit;
-+	}
-+#endif
-+
-+	/* wpa_supplicant's auto peer will initiate peering when candidate peer is reported without max_peer_links consideration */
-+	if (plink_ctl->num >= mcfg->max_peer_links + acnode ? 1 : 0)
-+		goto exit;
-+
-+	if (rtw_get_passing_time_ms(scanned->last_scanned) >= mcfg->peer_sel_policy.scanr_exp_ms
-+		|| (mcfg->rssi_threshold && mcfg->rssi_threshold > scanned->network.Rssi)
-+		|| !rtw_bss_is_candidate_mesh_peer(adapter, &scanned->network, 1, 1)
-+		#if CONFIG_RTW_MACADDR_ACL
-+		|| rtw_access_ctrl(adapter, scanned->network.MacAddress) == _FALSE
-+		#endif
-+		|| rtw_mesh_plink_get(adapter, scanned->network.MacAddress)
-+		#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+		|| rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
-+		#endif
-+		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+		|| !rtw_mesh_cto_mgate_network_filter(adapter, scanned)
-+		#endif
-+	)
-+		goto exit;
-+
-+#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+	if (acnode) {
-+		scanned->acnode_notify_etime = 0;
-+		RTW_INFO(FUNC_ADPT_FMT" acnode "MAC_FMT"\n"
-+			, FUNC_ADPT_ARG(adapter), MAC_ARG(scanned->network.MacAddress));
-+	}
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	rtw_cfg80211_notify_new_peer_candidate(adapter->rtw_wdev
-+		, scanned->network.MacAddress
-+		, BSS_EX_TLV_IES(&scanned->network)
-+		, BSS_EX_TLV_IES_LEN(&scanned->network)
-+		, scanned->network.Rssi
-+		, GFP_ATOMIC
-+	);
-+#endif
-+
-+exit:
-+	return;
-+}
-+
-+void rtw_mesh_peer_status_chk(_adapter *adapter)
-+{
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	struct mesh_plink_ent *plink;
-+	_list *head, *list;
-+	struct sta_info *sta = NULL;
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	int stainfo_offset;
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	u8 cto_mgate, forwarding, mgate;
-+#endif
-+	u8 flush;
-+	s8 flush_list[NUM_STA];
-+	u8 flush_num = 0;
-+	int i;
-+
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	if (rtw_mesh_cto_mgate_required(adapter)) {
-+		/* active scan on operating channel */
-+		issue_probereq_ex(adapter, &adapter->mlmepriv.cur_network.network.mesh_id, NULL, 0, 0, 0, 0);
-+	}
-+#endif
-+
-+	enter_critical_bh(&(plink_ctl->lock));
-+
-+	/* check established peers */
-+	enter_critical_bh(&stapriv->asoc_list_lock);
-+
-+	head = &stapriv->asoc_list;
-+	list = get_next(head);
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
-+		list = get_next(list);
-+
-+		if (!sta->plink || !sta->plink->scanned) {
-+			rtw_warn_on(1);
-+			continue;
-+		}
-+		plink = sta->plink;
-+		flush = 0;
-+
-+		/* remove unsuitable peer */
-+		if (!rtw_bss_is_candidate_mesh_peer(adapter, &plink->scanned->network, 1, 0)
-+			#if CONFIG_RTW_MACADDR_ACL
-+			|| rtw_access_ctrl(adapter, plink->addr) == _FALSE
-+			#endif
-+		) {
-+			flush = 1;
-+			goto flush_add;
-+		}
-+
-+		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+		cto_mgate = rtw_bss_is_cto_mgate(&(plink->scanned->network));
-+		forwarding = rtw_bss_is_forwarding(&(plink->scanned->network));
-+		mgate = rtw_mesh_gate_search(minfo->mesh_paths, sta->cmn.mac_addr);
-+
-+		/* CTO_MGATE required, remove peer without CTO_MGATE */
-+		if (rtw_mesh_cto_mgate_required(adapter) && !cto_mgate) {
-+			flush = 1;
-+			goto flush_add;
-+		}
-+
-+		/* cto_mgate_conf status update */
-+		if (IS_CTO_MGATE_CONF_DISABLED(plink)) {
-+			if (cto_mgate && !forwarding && !mgate)
-+				SET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms);
-+			else
-+				rtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr);
-+		} else {
-+			/* cto_mgate_conf ongoing */
-+			if (cto_mgate && !forwarding && !mgate) {
-+				if (IS_CTO_MGATE_CONF_TIMEOUT(plink)) {
-+					rtw_mesh_cto_mgate_blacklist_add(adapter, sta->cmn.mac_addr);
-+
-+					/* CTO_MGATE required, remove peering can't achieve CTO_MGATE */
-+					if (rtw_mesh_cto_mgate_required(adapter)) {
-+						flush = 1;
-+						goto flush_add;
-+					}	
-+				}
-+			} else {
-+				SET_CTO_MGATE_CONF_DISABLED(plink);
-+				rtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr);
-+			}
-+		}
-+		#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
-+
-+flush_add:
-+		if (flush) {
-+			rtw_list_delete(&sta->asoc_list);
-+			stapriv->asoc_list_cnt--;
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+			if (sta->tbtx_enable)
-+				stapriv->tbtx_asoc_list_cnt--;
-+#endif
-+			STA_SET_MESH_PLINK(sta, NULL);
-+
-+			stainfo_offset = rtw_stainfo_offset(stapriv, sta);
-+			if (stainfo_offset_valid(stainfo_offset))
-+				flush_list[flush_num++] = stainfo_offset;
-+			else
-+				rtw_warn_on(1);
-+		}
-+	}
-+
-+	exit_critical_bh(&stapriv->asoc_list_lock);
-+
-+	/* check non-established peers */
-+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
-+		plink = &plink_ctl->ent[i];
-+		if (plink->valid != _TRUE || plink->plink_state == RTW_MESH_PLINK_ESTAB)
-+			continue;
-+
-+		/* remove unsuitable peer */
-+		if (!rtw_bss_is_candidate_mesh_peer(adapter, &plink->scanned->network, 1, 1)
-+			#if CONFIG_RTW_MACADDR_ACL
-+			|| rtw_access_ctrl(adapter, plink->addr) == _FALSE
-+			#endif
-+		) {
-+			_rtw_mesh_expire_peer_ent(adapter, plink);
-+			continue;
-+		}
-+
-+		#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+		/* peer confirm check timeout, add to black list */
-+		if (IS_PEER_CONF_TIMEOUT(plink)) {
-+			rtw_mesh_peer_blacklist_add(adapter, plink->addr);
-+			_rtw_mesh_expire_peer_ent(adapter, plink);
-+		}
-+		#endif
-+	}
-+
-+	exit_critical_bh(&(plink_ctl->lock));
-+
-+	if (flush_num) {
-+		u8 sta_addr[ETH_ALEN];
-+		u8 updated = _FALSE;
-+
-+		for (i = 0; i < flush_num; i++) {
-+			sta = rtw_get_stainfo_by_offset(stapriv, flush_list[i]);
-+			_rtw_memcpy(sta_addr, sta->cmn.mac_addr, ETH_ALEN);
-+
-+			updated |= ap_free_sta(adapter, sta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _FALSE);
-+			rtw_mesh_expire_peer(adapter, sta_addr);
-+		}
-+
-+		associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);
-+	}
-+
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	/* loop cto_mgate_blacklist to remove ent according to scan_r */
-+	rtw_mesh_cto_mgate_blacklist_chk(adapter);
-+#endif
-+
-+#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+	rtw_mesh_acnode_rsvd_chk(adapter);
-+#endif
-+
-+	return;
-+}
-+
-+#if CONFIG_RTW_MESH_OFFCH_CAND
-+static u8 rtw_mesh_offch_cto_mgate_required(_adapter *adapter)
-+{
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+	_queue *queue = &(mlme->scanned_queue);
-+	_list *head, *pos;
-+	struct wlan_network *scanned = NULL;
-+	u8 ret = 0;
-+
-+	if (!rtw_mesh_cto_mgate_required(adapter))
-+		goto exit;
-+
-+	enter_critical_bh(&(mlme->scanned_queue.lock));
-+
-+	head = get_list_head(queue);
-+	pos = get_next(head);
-+	while (!rtw_end_of_queue_search(head, pos)) {
-+		scanned = LIST_CONTAINOR(pos, struct wlan_network, list);
-+
-+		if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms
-+			&& (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi)
-+			#if CONFIG_RTW_MACADDR_ACL
-+			&& rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE
-+			#endif
-+			&& rtw_bss_is_candidate_mesh_peer(adapter, &scanned->network, 1, 1)
-+			&& rtw_bss_is_cto_mgate(&scanned->network)
-+			#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+			&& !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
-+			#endif
-+			&& !rtw_mesh_cto_mgate_blacklist_search(adapter, scanned->network.MacAddress)
-+		)
-+			break;
-+
-+		pos = get_next(pos);
-+	}
-+
-+	if (rtw_end_of_queue_search(head, pos))
-+		ret = 1;
-+
-+	exit_critical_bh(&(mlme->scanned_queue.lock));
-+
-+exit:
-+	return ret;
-+#else
-+	return 0;
-+#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
-+}
-+
-+u8 rtw_mesh_offch_candidate_accepted(_adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	u8 ret = 0;
-+
-+	if (!adapter->mesh_cfg.peer_sel_policy.offch_cand)
-+		goto exit;
-+
-+	ret = MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)
-+		&& (!plink_ctl->num || rtw_mesh_offch_cto_mgate_required(adapter))
-+		;
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (ret) {
-+		struct mi_state mstate_no_self;
-+
-+		rtw_mi_status_no_self(adapter, &mstate_no_self);
-+		if (MSTATE_STA_LD_NUM(&mstate_no_self))
-+			ret = 0;
-+	}
-+#endif
-+
-+exit:
-+	return ret;
-+}
-+
-+/*
-+ * this function is called under off channel candidate is required 
-+ * the channel with maximum candidate count is selected
-+*/
-+u8 rtw_mesh_select_operating_ch(_adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+	_queue *queue = &(mlme->scanned_queue);
-+	_list *head, *pos;
-+	_irqL irqL;
-+	struct wlan_network *scanned = NULL;
-+	int i;
-+	/* statistics for candidate accept peering */
-+	u8 cand_ap_cnt[MAX_CHANNEL_NUM] = {0};
-+	u8 max_cand_ap_ch = 0;
-+	u8 max_cand_ap_cnt = 0;
-+	/* statistics for candidate including not accept peering */
-+	u8 cand_cnt[MAX_CHANNEL_NUM] = {0};
-+	u8 max_cand_ch = 0;
-+	u8 max_cand_cnt = 0;
-+
-+	_enter_critical_bh(&(mlme->scanned_queue.lock), &irqL);
-+
-+	head = get_list_head(queue);
-+	pos = get_next(head);
-+	while (!rtw_end_of_queue_search(head, pos)) {
-+		scanned = LIST_CONTAINOR(pos, struct wlan_network, list);
-+		pos = get_next(pos);
-+
-+		if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms
-+			&& (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi)
-+			#if CONFIG_RTW_MACADDR_ACL
-+			&& rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE
-+			#endif
-+			&& rtw_bss_is_candidate_mesh_peer(adapter, &scanned->network, 0, 0)
-+			#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+			&& !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
-+			#endif
-+			#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+			&& rtw_mesh_cto_mgate_network_filter(adapter, scanned)
-+			#endif
-+		) {
-+			int ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scanned->network.Configuration.DSConfig);
-+
-+			if (ch_set_idx >= 0
-+				&& !(rfctl->channel_set[ch_set_idx].flags & RTW_CHF_NO_IR)
-+				&& !CH_IS_NON_OCP(&rfctl->channel_set[ch_set_idx])
-+			) {
-+				u8 nop, accept;
-+
-+				rtw_mesh_bss_peering_status(&scanned->network, &nop, &accept);
-+				cand_cnt[ch_set_idx]++;
-+				if (max_cand_cnt < cand_cnt[ch_set_idx]) {
-+					max_cand_cnt = cand_cnt[ch_set_idx];
-+					max_cand_ch = rfctl->channel_set[ch_set_idx].ChannelNum;
-+				}
-+				if (accept) {
-+					cand_ap_cnt[ch_set_idx]++;
-+					if (max_cand_ap_cnt < cand_ap_cnt[ch_set_idx]) {
-+						max_cand_ap_cnt = cand_ap_cnt[ch_set_idx];
-+						max_cand_ap_ch = rfctl->channel_set[ch_set_idx].ChannelNum;
-+					}
-+				}
-+			}
-+		}
-+	}
-+
-+	_exit_critical_bh(&(mlme->scanned_queue.lock), &irqL);
-+
-+	return max_cand_ap_ch ? max_cand_ap_ch : max_cand_ch;
-+}
-+
-+void dump_mesh_offch_cand_settings(void *sel, _adapter *adapter)
-+{
-+	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
-+
-+	RTW_PRINT_SEL(sel, "%-6s %-11s\n"
-+		, "enable", "find_int_ms");
-+	RTW_PRINT_SEL(sel, "%6u %11u\n"
-+		, peer_sel_policy->offch_cand, peer_sel_policy->offch_find_int_ms);
-+}
-+#endif /* CONFIG_RTW_MESH_OFFCH_CAND */
-+
-+void dump_mesh_peer_sel_policy(void *sel, _adapter *adapter)
-+{
-+	struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
-+
-+	RTW_PRINT_SEL(sel, "%-12s\n", "scanr_exp_ms");
-+	RTW_PRINT_SEL(sel, "%12u\n", peer_sel_policy->scanr_exp_ms);
-+}
-+
-+void dump_mesh_networks(void *sel, _adapter *adapter)
-+{
-+#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+#define NSTATE_TITLE_FMT_ACN " %-5s"
-+#define NSTATE_VALUE_FMT_ACN " %5d"
-+#define NSTATE_TITLE_ARG_ACN , "acn"
-+#define NSTATE_VALUE_ARG_ACN , (acn_ms < 99999 ? acn_ms : 99999)
-+#else
-+#define NSTATE_TITLE_FMT_ACN ""
-+#define NSTATE_VALUE_FMT_ACN ""
-+#define NSTATE_TITLE_ARG_ACN
-+#define NSTATE_VALUE_ARG_ACN
-+#endif
-+
-+	struct mlme_priv *mlme = &(adapter->mlmepriv);
-+	_queue *queue = &(mlme->scanned_queue);
-+	struct wlan_network	*network;
-+	_list *list, *head;
-+	u8 same_mbss;
-+	u8 candidate;
-+	struct mesh_plink_ent *plink;
-+	u8 blocked;
-+	u8 established;
-+	s32 age_ms;
-+#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+	s32 acn_ms;
-+#endif
-+	u8 *mesh_conf_ie;
-+	sint mesh_conf_ie_len;
-+	u8 auth_pid;
-+	u8 *rsn_ie;
-+	int rsn_ie_len;
-+	int gcs, pcs, gmcs;
-+	u8 mfp_opt;
-+	struct wlan_network **mesh_networks;
-+	u8 mesh_network_cnt = 0;
-+	int i;
-+
-+	mesh_networks = rtw_zvmalloc(mlme->max_bss_cnt * sizeof(struct wlan_network *));
-+	if (!mesh_networks)
-+		return;
-+
-+	enter_critical_bh(&queue->lock);
-+	head = get_list_head(queue);
-+	list = get_next(head);
-+
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		network = LIST_CONTAINOR(list, struct wlan_network, list);
-+		list = get_next(list);
-+
-+		if (network->network.InfrastructureMode != Ndis802_11_mesh)
-+			continue;
-+
-+		mesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG
-+			, &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network));
-+		if (!mesh_conf_ie || mesh_conf_ie_len != 7)
-+			continue;
-+
-+		mesh_networks[mesh_network_cnt++] = network;
-+	}
-+
-+	exit_critical_bh(&queue->lock);
-+
-+	RTW_PRINT_SEL(sel, "  %-17s %-3s %-4s %-5s %-32s %-10s"
-+		" %-3s %-3s %-4s"
-+		" %-3s %-3s %-3s"
-+		NSTATE_TITLE_FMT_ACN
-+		"\n"
-+		, "bssid", "ch", "rssi", "age", "mesh_id", "P M C S A "
-+		, "pcs", "gcs", "gmcs"
-+		, "nop", "fwd", "cto"
-+		NSTATE_TITLE_ARG_ACN
-+	);
-+
-+	if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)) {
-+		network = &mlme->cur_network;
-+		mesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG
-+			, &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network));
-+		if (mesh_conf_ie && mesh_conf_ie_len == 7) {
-+			gcs = pcs = gmcs = 0;
-+			mfp_opt = MFP_NO;
-+			auth_pid = GET_MESH_CONF_ELE_AUTH_PROTO_ID(mesh_conf_ie + 2);
-+			if (auth_pid && auth_pid <= 2) {
-+				rsn_ie = rtw_get_wpa2_ie(BSS_EX_TLV_IES(&network->network)
-+							, &rsn_ie_len, BSS_EX_TLV_IES_LEN(&network->network));
-+				if (rsn_ie && rsn_ie_len)
-+					rtw_parse_wpa2_ie(rsn_ie, rsn_ie_len + 2, &gcs, &pcs, &gmcs, NULL, &mfp_opt);
-+			}
-+			RTW_PRINT_SEL(sel, "* "MAC_FMT" %3d            %-32s %2x%2x%2x%2x%2x"
-+				" %03x %03x %c%03x"
-+				" %c%2u %3u %c%c "
-+				"\n"
-+				, MAC_ARG(network->network.MacAddress)
-+				, network->network.Configuration.DSConfig
-+				, network->network.mesh_id.Ssid
-+				, GET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(mesh_conf_ie + 2)
-+				, GET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(mesh_conf_ie + 2)
-+				, GET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(mesh_conf_ie + 2)
-+				, GET_MESH_CONF_ELE_SYNC_METHOD_ID(mesh_conf_ie + 2)
-+				, auth_pid
-+				, pcs, gcs, mfp_opt == MFP_REQUIRED ? 'R' : (mfp_opt == MFP_OPTIONAL ? 'C' : ' ')
-+				, mfp_opt >= MFP_OPTIONAL ? gmcs : 0
-+				, GET_MESH_CONF_ELE_ACCEPT_PEERINGS(mesh_conf_ie + 2) ? '+' : ' '
-+				, GET_MESH_CONF_ELE_NUM_OF_PEERINGS(mesh_conf_ie + 2)
-+				, GET_MESH_CONF_ELE_FORWARDING(mesh_conf_ie + 2)
-+				, GET_MESH_CONF_ELE_CTO_MGATE(mesh_conf_ie + 2) ? 'G' : ' '
-+				, GET_MESH_CONF_ELE_CTO_AS(mesh_conf_ie + 2) ? 'A' : ' '
-+			);
-+		}
-+	}
-+
-+	for (i = 0; i < mesh_network_cnt; i++) {
-+		network = mesh_networks[i];
-+
-+		if (network->network.InfrastructureMode != Ndis802_11_mesh)
-+			continue;
-+
-+		mesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG
-+			, &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network));
-+		if (!mesh_conf_ie || mesh_conf_ie_len != 7)
-+			continue;
-+
-+		gcs = pcs = gmcs = 0;
-+		mfp_opt = MFP_NO;
-+		auth_pid = GET_MESH_CONF_ELE_AUTH_PROTO_ID(mesh_conf_ie + 2);
-+		if (auth_pid && auth_pid <= 2) {
-+			rsn_ie = rtw_get_wpa2_ie(BSS_EX_TLV_IES(&network->network), &rsn_ie_len, BSS_EX_TLV_IES_LEN(&network->network));
-+			if (rsn_ie && rsn_ie_len)
-+				rtw_parse_wpa2_ie(rsn_ie, rsn_ie_len + 2, &gcs, &pcs, &gmcs, NULL, &mfp_opt);
-+		}
-+		age_ms = rtw_get_passing_time_ms(network->last_scanned);
-+		#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+		if (network->acnode_stime == 0)
-+			acn_ms = 0;
-+		else
-+			acn_ms = rtw_get_passing_time_ms(network->acnode_stime);
-+		#endif
-+		same_mbss = 0;
-+		candidate = 0;
-+		plink = NULL;
-+		blocked = 0;
-+		established = 0;
-+
-+		if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)) {
-+			plink = rtw_mesh_plink_get(adapter, network->network.MacAddress);
-+			if (plink && plink->plink_state == RTW_MESH_PLINK_ESTAB)
-+				established = 1;
-+			else if (plink && plink->plink_state == RTW_MESH_PLINK_BLOCKED)
-+				blocked = 1;
-+			else if (plink)
-+				;
-+			else if (rtw_bss_is_candidate_mesh_peer(adapter, &network->network, 0, 1))
-+				candidate = 1;
-+			else if (rtw_bss_is_same_mbss(&mlme->cur_network.network, &network->network))
-+				same_mbss = 1;
-+		}
-+
-+		RTW_PRINT_SEL(sel, "%c "MAC_FMT" %3d %4ld %5d %-32s %2x%2x%2x%2x%2x"
-+			" %03x %03x %c%03x"
-+			" %c%2u %3u %c%c "
-+			NSTATE_VALUE_FMT_ACN
-+			"\n"
-+			, established ? 'E' : (blocked ? 'B' : (plink ? 'N' : (candidate ? 'C' : (same_mbss ? 'S' : ' '))))
-+			, MAC_ARG(network->network.MacAddress)
-+			, network->network.Configuration.DSConfig
-+			, network->network.Rssi
-+			, age_ms < 99999 ? age_ms : 99999
-+			, network->network.mesh_id.Ssid
-+			, GET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(mesh_conf_ie + 2)
-+			, GET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(mesh_conf_ie + 2)
-+			, GET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(mesh_conf_ie + 2)
-+			, GET_MESH_CONF_ELE_SYNC_METHOD_ID(mesh_conf_ie + 2)
-+			, auth_pid
-+			, pcs, gcs, mfp_opt == MFP_REQUIRED ? 'R' : (mfp_opt == MFP_OPTIONAL ? 'C' : ' ')
-+			, mfp_opt >= MFP_OPTIONAL ? gmcs : 0
-+			, GET_MESH_CONF_ELE_ACCEPT_PEERINGS(mesh_conf_ie + 2) ? '+' : ' '
-+			, GET_MESH_CONF_ELE_NUM_OF_PEERINGS(mesh_conf_ie + 2)
-+			, GET_MESH_CONF_ELE_FORWARDING(mesh_conf_ie + 2)
-+			, GET_MESH_CONF_ELE_CTO_MGATE(mesh_conf_ie + 2) ? 'G' : ' '
-+			, GET_MESH_CONF_ELE_CTO_AS(mesh_conf_ie + 2) ? 'A' : ' '
-+			NSTATE_VALUE_ARG_ACN
-+		);
-+	}
-+
-+	rtw_vmfree(mesh_networks, mlme->max_bss_cnt * sizeof(struct wlan_network *));
-+}
-+
-+void rtw_mesh_adjust_chbw(u8 req_ch, u8 *req_bw, u8 *req_offset)
-+{
-+	if (req_ch >= 5 && req_ch <= 9) {
-+		/* prevent secondary channel offset mismatch */
-+		if (*req_bw > CHANNEL_WIDTH_20) {
-+			*req_bw = CHANNEL_WIDTH_20;
-+			*req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		}
-+	}
-+}
-+
-+void rtw_mesh_sae_check_frames(_adapter *adapter, const u8 *buf, u32 len, u8 tx, u16 alg, u16 seq, u16 status)
-+{
-+#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+	if (tx && seq == 1)
-+		rtw_mesh_plink_set_peer_conf_timeout(adapter, GetAddr1Ptr(buf));
-+#endif
-+}
-+
-+#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS
-+#ifdef CONFIG_RTW_MESH_AEK
-+static int rtw_mpm_ampe_dec(_adapter *adapter, struct mesh_plink_ent *plink
-+	, u8 *fhead, size_t flen, u8* fbody, u8 *mic_ie, u8 *ampe_buf)
-+{	
-+	int ret = _FAIL, verify_ret;
-+	const u8 *aad[] = {adapter_mac_addr(adapter), plink->addr, fbody};
-+	const size_t aad_len[] = {ETH_ALEN, ETH_ALEN, mic_ie - fbody};
-+	u8 *iv_crypt;
-+	size_t iv_crypt_len = flen - (mic_ie + 2 - fhead);
-+
-+	iv_crypt = rtw_malloc(iv_crypt_len);
-+	if (!iv_crypt)
-+		goto exit;
-+
-+	_rtw_memcpy(iv_crypt, mic_ie + 2, iv_crypt_len);
-+
-+	verify_ret = rtw_aes_siv_decrypt(plink->aek, 32, iv_crypt, iv_crypt_len
-+		, 3, aad, aad_len, ampe_buf);
-+
-+	rtw_mfree(iv_crypt, iv_crypt_len);
-+
-+	if (verify_ret) {
-+		RTW_WARN("verify error, aek_valid=%u\n", plink->aek_valid);
-+		goto exit;
-+	} else if (*ampe_buf != WLAN_EID_AMPE) {
-+		RTW_WARN("plaintext is not AMPE IE\n");
-+		goto exit;
-+	} else if ( 16 /* AES_BLOCK_SIZE*/ + 2 + *(ampe_buf + 1) > iv_crypt_len) {
-+		RTW_WARN("plaintext AMPE IE length is not valid\n");
-+		goto exit;
-+	}
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+static int rtw_mpm_ampe_enc(_adapter *adapter, struct mesh_plink_ent *plink
-+	, u8* fbody, u8 *mic_ie, u8 *ampe_buf, bool inverse)
-+{
-+	int ret = _FAIL, protect_ret;
-+	const u8 *aad[3];
-+	const size_t aad_len[3] = {ETH_ALEN, ETH_ALEN, mic_ie - fbody};
-+	u8 *ampe_ie;
-+	size_t ampe_ie_len = *(ampe_buf + 1) + 2; /* including id & len */
-+
-+	if (inverse) {
-+		aad[0] = plink->addr;
-+		aad[1] = adapter_mac_addr(adapter);
-+	} else {
-+		aad[0] = adapter_mac_addr(adapter);
-+		aad[1] = plink->addr;
-+	}
-+	aad[2] = fbody;
-+
-+	ampe_ie = rtw_malloc(ampe_ie_len);
-+	if (!ampe_ie)
-+		goto exit;
-+
-+	_rtw_memcpy(ampe_ie, ampe_buf, ampe_ie_len);
-+
-+	protect_ret = rtw_aes_siv_encrypt(plink->aek, 32, ampe_ie, ampe_ie_len
-+		, 3, aad, aad_len, mic_ie + 2);
-+
-+	rtw_mfree(ampe_ie, ampe_ie_len);
-+
-+	if (protect_ret) {
-+		RTW_WARN("protect error, aek_valid=%u\n", plink->aek_valid);
-+		goto exit;
-+	}
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_RTW_MESH_AEK */
-+
-+static int rtw_mpm_tx_ies_sync_bss(_adapter *adapter, struct mesh_plink_ent *plink
-+	, u8 *fhead, size_t flen, u8* fbody, u8 tlv_ies_offset, u8 *mpm_ie, u8 *mic_ie
-+	, u8 **nbuf, size_t *nlen)
-+{
-+	int ret = _FAIL;
-+	struct mlme_priv *mlme = &(adapter->mlmepriv);
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);
-+	WLAN_BSSID_EX *network = &(mlmeinfo->network);
-+	uint left;
-+	u8 *pos;
-+
-+	uint mpm_ielen = *(mpm_ie + 1);
-+	u8 *fpos;
-+	u8 *new_buf = NULL;
-+	size_t new_len = 0;
-+
-+	u8 *new_fhead;
-+	size_t new_flen;
-+	u8 *new_fbody;
-+	u8 *new_mic_ie;
-+
-+#ifdef CONFIG_RTW_MESH_AEK
-+	u8 *ampe_buf = NULL;
-+	size_t ampe_buf_len = 0;
-+
-+	/* decode */
-+	if (mic_ie) {
-+		ampe_buf_len = flen - (mic_ie + 2 + 16 /* AES_BLOCK_SIZE */ - fhead);
-+		ampe_buf = rtw_malloc(ampe_buf_len);
-+		if (!ampe_buf)
-+			goto exit;
-+
-+		if (rtw_mpm_ampe_dec(adapter, plink, fhead, flen, fbody, mic_ie, ampe_buf) != _SUCCESS)
-+			goto exit;
-+
-+		if (*(ampe_buf + 1) >= 68) {
-+			_rtw_memcpy(plink->sel_pcs, ampe_buf + 2, 4);
-+			_rtw_memcpy(plink->l_nonce, ampe_buf + 6, 32);
-+			_rtw_memcpy(plink->p_nonce, ampe_buf + 38, 32);
-+		}
-+	}
-+#endif
-+
-+	/* count for new frame length  */
-+	new_len = sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset;
-+	left = BSS_EX_TLV_IES_LEN(network);
-+	pos = BSS_EX_TLV_IES(network);
-+	while (left >= 2) {
-+		u8 id, elen;
-+	
-+		id = *pos++;
-+		elen = *pos++;
-+		left -= 2;
-+
-+		if (elen > left)
-+			break;
-+
-+		switch (id) {
-+		case WLAN_EID_SSID:
-+		case WLAN_EID_DS_PARAMS:
-+		case WLAN_EID_TIM:
-+			break;
-+		default:
-+			new_len += 2 + elen;
-+		}
-+
-+		left -= elen;
-+		pos += elen;
-+	}
-+	new_len += mpm_ielen + 2;
-+	if (mic_ie)
-+		new_len += 16 /* AES_BLOCK_SIZE*/ + 2 + ampe_buf_len;
-+
-+	/* alloc new frame */
-+	new_buf = rtw_malloc(new_len);
-+	if (!new_buf) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	/* build new frame  */
-+	_rtw_memcpy(new_buf, fhead, sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset);
-+	new_fhead = new_buf;
-+	new_flen = new_len;
-+	new_fbody = new_fhead + sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	fpos = new_fbody + tlv_ies_offset;
-+	left = BSS_EX_TLV_IES_LEN(network);
-+	pos = BSS_EX_TLV_IES(network);
-+	while (left >= 2) {
-+		u8 id, elen;
-+	
-+		id = *pos++;
-+		elen = *pos++;
-+		left -= 2;
-+
-+		if (elen > left)
-+			break;
-+
-+		switch (id) {
-+		case WLAN_EID_SSID:
-+		case WLAN_EID_DS_PARAMS:
-+		case WLAN_EID_TIM:
-+			break;
-+		default:
-+			fpos = rtw_set_ie(fpos, id, elen, pos, NULL);
-+			if (id == WLAN_EID_MESH_CONFIG)
-+				fpos = rtw_set_ie(fpos, WLAN_EID_MPM, mpm_ielen, mpm_ie + 2, NULL);
-+		}
-+
-+		left -= elen;
-+		pos += elen;
-+	}
-+	if (mic_ie) {
-+		new_mic_ie = fpos;
-+		*fpos++ = WLAN_EID_MIC;
-+		*fpos++ = 16 /* AES_BLOCK_SIZE */;
-+	}
-+
-+#ifdef CONFIG_RTW_MESH_AEK
-+	/* encode */
-+	if (mic_ie) {
-+		int enc_ret = rtw_mpm_ampe_enc(adapter, plink, new_fbody, new_mic_ie, ampe_buf, 0);
-+		if (enc_ret != _SUCCESS)
-+			goto exit;
-+	}
-+#endif
-+
-+	*nlen = new_len;
-+	*nbuf = new_buf;
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	if (ret != _SUCCESS && new_buf)
-+		rtw_mfree(new_buf, new_len);
-+
-+#ifdef CONFIG_RTW_MESH_AEK
-+	if (ampe_buf)
-+		rtw_mfree(ampe_buf, ampe_buf_len);
-+#endif
-+
-+	return ret;
-+}
-+#endif /* CONFIG_RTW_MPM_TX_IES_SYNC_BSS */
-+
-+struct mpm_frame_info {
-+	u8 *aid;
-+	u16 aid_v;
-+	u8 *pid;
-+	u16 pid_v;
-+	u8 *llid;
-+	u16 llid_v;
-+	u8 *plid;
-+	u16 plid_v;
-+	u8 *reason;
-+	u16 reason_v;
-+	u8 *chosen_pmk;
-+};
-+
-+/*
-+* pid:00000 llid:00000 chosen_pmk:0x00000000000000000000000000000000
-+* aid:00000 pid:00000 llid:00000 plid:00000 chosen_pmk:0x00000000000000000000000000000000
-+* pid:00000 llid:00000 plid:00000 reason:00000 chosen_pmk:0x00000000000000000000000000000000
-+*/
-+#define MPM_LOG_BUF_LEN 92 /* this length is limited for legal combination */
-+static void rtw_mpm_info_msg(struct mpm_frame_info *mpm_info, u8 *mpm_log_buf)
-+{
-+	int cnt = 0;
-+
-+	if (mpm_info->aid) {
-+		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "aid:%u ", mpm_info->aid_v);
-+		if (cnt >= MPM_LOG_BUF_LEN - 1)
-+			goto exit;
-+	}
-+	if (mpm_info->pid) {
-+		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "pid:%u ", mpm_info->pid_v);
-+		if (cnt >= MPM_LOG_BUF_LEN - 1)
-+			goto exit;
-+	}
-+	if (mpm_info->llid) {
-+		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "llid:%u ", mpm_info->llid_v);
-+		if (cnt >= MPM_LOG_BUF_LEN - 1)
-+			goto exit;
-+	}
-+	if (mpm_info->plid) {
-+		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "plid:%u ", mpm_info->plid_v);
-+		if (cnt >= MPM_LOG_BUF_LEN - 1)
-+			goto exit;
-+	}
-+	if (mpm_info->reason) {
-+		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "reason:%u ", mpm_info->reason_v);
-+		if (cnt >= MPM_LOG_BUF_LEN - 1)
-+			goto exit;
-+	}
-+	if (mpm_info->chosen_pmk) {
-+		cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "chosen_pmk:0x"KEY_FMT, KEY_ARG(mpm_info->chosen_pmk));
-+		if (cnt >= MPM_LOG_BUF_LEN - 1)
-+			goto exit;
-+	}
-+
-+exit:
-+	return;
-+}
-+
-+static int rtw_mpm_check_frames(_adapter *adapter, u8 action, const u8 **buf, size_t *len, u8 tx)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	struct mesh_plink_ent *plink = NULL;
-+	u8 *nbuf = NULL;
-+	size_t nlen = 0;
-+	u8 *fhead = (u8 *)*buf;
-+	size_t flen = *len;
-+	u8 *peer_addr = tx ? GetAddr1Ptr(fhead) : get_addr2_ptr(fhead);
-+	u8 *frame_body = fhead + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	struct mpm_frame_info mpm_info;
-+	u8 tlv_ies_offset;
-+	u8 *mpm_ie = NULL;
-+	uint mpm_ielen = 0;
-+	u8 *mic_ie = NULL;
-+	uint mic_ielen = 0;
-+	int ret = 0;
-+	u8 mpm_log_buf[MPM_LOG_BUF_LEN] = {0};
-+
-+	if (action == RTW_ACT_SELF_PROTECTED_MESH_OPEN)
-+		tlv_ies_offset = 4;
-+	else if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF)
-+		tlv_ies_offset = 6;
-+	else if (action == RTW_ACT_SELF_PROTECTED_MESH_CLOSE)
-+		tlv_ies_offset = 2;
-+	else {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	plink = rtw_mesh_plink_get(adapter, peer_addr);
-+	if (!plink && (tx == _TRUE || action == RTW_ACT_SELF_PROTECTED_MESH_CONF)) {
-+		/* warning message if no plink when: 1.TX all MPM or 2.RX CONF */
-+		RTW_WARN("RTW_%s:%s without plink of "MAC_FMT"\n"
-+			, (tx == _TRUE) ? "Tx" : "Rx", action_self_protected_str(action), MAC_ARG(peer_addr));
-+		goto exit;
-+	}
-+
-+	_rtw_memset(&mpm_info, 0, sizeof(struct mpm_frame_info));
-+
-+	if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) {
-+		mpm_info.aid = (u8 *)frame_body + 4;
-+		mpm_info.aid_v = RTW_GET_LE16(mpm_info.aid);
-+	}
-+
-+	mpm_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
-+		, WLAN_EID_MPM, &mpm_ielen
-+		, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
-+	if (!mpm_ie || mpm_ielen < 2 + 2)
-+		goto exit;
-+
-+	mpm_info.pid = mpm_ie + 2;
-+	mpm_info.pid_v = RTW_GET_LE16(mpm_info.pid);
-+	mpm_info.llid = mpm_info.pid + 2;
-+	mpm_info.llid_v = RTW_GET_LE16(mpm_info.llid);
-+
-+	switch (action) {
-+	case RTW_ACT_SELF_PROTECTED_MESH_OPEN:
-+		/* pid:2, llid:2, (chosen_pmk:16) */
-+		if (mpm_info.pid_v == 0 && mpm_ielen == 4)
-+			;
-+		else if (mpm_info.pid_v == 1 && mpm_ielen == 20)
-+			mpm_info.chosen_pmk = mpm_info.llid + 2;
-+		else
-+			goto exit;
-+		break;
-+	case RTW_ACT_SELF_PROTECTED_MESH_CONF:
-+		/* pid:2, llid:2, plid:2, (chosen_pmk:16) */
-+		mpm_info.plid = mpm_info.llid + 2;
-+		mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);
-+		if (mpm_info.pid_v == 0 && mpm_ielen == 6)
-+			;
-+		else if (mpm_info.pid_v == 1 && mpm_ielen == 22)
-+			mpm_info.chosen_pmk = mpm_info.plid + 2;
-+		else
-+			goto exit;
-+		break;
-+	case RTW_ACT_SELF_PROTECTED_MESH_CLOSE:
-+		/* pid:2, llid:2, (plid:2), reason:2, (chosen_pmk:16) */
-+		if (mpm_info.pid_v == 0 && mpm_ielen == 6) {
-+			/* MPM, without plid */
-+			mpm_info.reason = mpm_info.llid + 2;
-+			mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
-+		} else if (mpm_info.pid_v == 0 && mpm_ielen == 8) {
-+			/* MPM, with plid */
-+			mpm_info.plid = mpm_info.llid + 2;
-+			mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);
-+			mpm_info.reason = mpm_info.plid + 2;
-+			mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
-+		} else if (mpm_info.pid_v == 1 && mpm_ielen == 22) {
-+			/* AMPE, without plid */
-+			mpm_info.reason = mpm_info.llid + 2;
-+			mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
-+			mpm_info.chosen_pmk = mpm_info.reason + 2;
-+		} else if (mpm_info.pid_v == 1 && mpm_ielen == 24) {
-+			/* AMPE, with plid */
-+			mpm_info.plid = mpm_info.llid + 2;
-+			mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);
-+			mpm_info.reason = mpm_info.plid + 2;
-+			mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
-+			mpm_info.chosen_pmk = mpm_info.reason + 2;
-+		} else
-+			goto exit;
-+		break;
-+	};
-+
-+	if (mpm_info.pid_v == 1) {
-+		mic_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
-+			, WLAN_EID_MIC, &mic_ielen
-+			, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
-+		if (!mic_ie || mic_ielen != 16 /* AES_BLOCK_SIZE */)
-+			goto exit;
-+	}
-+
-+#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS
-+	if ((action == RTW_ACT_SELF_PROTECTED_MESH_OPEN || action == RTW_ACT_SELF_PROTECTED_MESH_CONF)
-+		&& tx == _TRUE
-+	) {
-+#define DBG_RTW_MPM_TX_IES_SYNC_BSS 0
-+
-+		if (mpm_info.pid_v == 1 && (!plink || !MESH_PLINK_AEK_VALID(plink))) {
-+			RTW_WARN("AEK not ready, IEs can't sync with BSS\n");
-+			goto bypass_sync_bss;
-+		}
-+
-+		if (DBG_RTW_MPM_TX_IES_SYNC_BSS) {
-+			RTW_INFO(FUNC_ADPT_FMT" before:\n", FUNC_ADPT_ARG(adapter));
-+			dump_ies(RTW_DBGDUMP
-+				, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
-+				, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
-+		}
-+
-+		rtw_mpm_tx_ies_sync_bss(adapter, plink
-+			, fhead, flen, frame_body, tlv_ies_offset, mpm_ie, mic_ie
-+			, &nbuf, &nlen);
-+		if (!nbuf)
-+			goto exit;
-+
-+		/* update pointer & len for new frame */
-+		fhead = nbuf;
-+		flen = nlen;
-+		frame_body = fhead + sizeof(struct rtw_ieee80211_hdr_3addr);
-+		if (mpm_info.pid_v == 1) {
-+			mic_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
-+				, WLAN_EID_MIC, &mic_ielen
-+				, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
-+		}
-+
-+		if (DBG_RTW_MPM_TX_IES_SYNC_BSS) {
-+			RTW_INFO(FUNC_ADPT_FMT" after:\n", FUNC_ADPT_ARG(adapter));
-+			dump_ies(RTW_DBGDUMP
-+				, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
-+				, flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
-+		}
-+	}
-+bypass_sync_bss:
-+#endif /* CONFIG_RTW_MPM_TX_IES_SYNC_BSS */
-+
-+	if (!plink)
-+		goto mpm_log;
-+
-+#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+	if (action == RTW_ACT_SELF_PROTECTED_MESH_OPEN) {
-+		if (tx)
-+			rtw_mesh_plink_set_peer_conf_timeout(adapter, peer_addr);
-+
-+	} else
-+#endif
-+#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+	if (action == RTW_ACT_SELF_PROTECTED_MESH_CLOSE) {
-+		if (tx && mpm_info.reason && mpm_info.reason_v == WLAN_REASON_MESH_MAX_PEERS) {
-+			if (rtw_mesh_scanned_is_acnode_confirmed(adapter, plink->scanned)
-+				&& rtw_mesh_acnode_prevent_allow_sacrifice(adapter)
-+			) {
-+				struct sta_info *sac = rtw_mesh_acnode_prevent_pick_sacrifice(adapter);
-+
-+				if (sac) {
-+					struct sta_priv *stapriv = &adapter->stapriv;
-+					_irqL irqL;
-+					u8 sta_addr[ETH_ALEN];
-+					u8 updated = _FALSE;
-+
-+					_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+					if (!rtw_is_list_empty(&sac->asoc_list)) {
-+						rtw_list_delete(&sac->asoc_list);
-+						stapriv->asoc_list_cnt--;
-+						#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+						if (sac->tbtx_enable)
-+							stapriv->tbtx_asoc_list_cnt--;
-+						#endif			
-+						STA_SET_MESH_PLINK(sac, NULL);
-+					}
-+					_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+					RTW_INFO(FUNC_ADPT_FMT" sacrifice "MAC_FMT" for acnode\n"
-+						, FUNC_ADPT_ARG(adapter), MAC_ARG(sac->cmn.mac_addr));
-+
-+					_rtw_memcpy(sta_addr, sac->cmn.mac_addr, ETH_ALEN);
-+					updated = ap_free_sta(adapter, sac, 0, 0, 1);
-+					rtw_mesh_expire_peer(stapriv->padapter, sta_addr);
-+
-+					associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);
-+				}
-+			}
-+		}
-+	} else
-+#endif
-+	if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) {
-+		_irqL irqL;
-+		u8 *ies = NULL;
-+		u16 ies_len = 0;
-+
-+		_enter_critical_bh(&(plink_ctl->lock), &irqL);
-+
-+		plink = _rtw_mesh_plink_get(adapter, peer_addr);
-+		if (!plink)
-+			goto release_plink_ctl;
-+
-+		if (tx == _FALSE) {
-+			ies = plink->rx_conf_ies;
-+			ies_len = plink->rx_conf_ies_len;
-+			plink->rx_conf_ies = NULL;
-+			plink->rx_conf_ies_len = 0;
-+
-+			plink->llid = mpm_info.plid_v;
-+			plink->plid = mpm_info.llid_v;
-+			plink->peer_aid = mpm_info.aid_v;
-+			if (mpm_info.pid_v == 1)
-+				_rtw_memcpy(plink->chosen_pmk, mpm_info.chosen_pmk, 16);
-+		}
-+		#ifdef CONFIG_RTW_MESH_DRIVER_AID
-+		else {
-+			ies = plink->tx_conf_ies;
-+			ies_len = plink->tx_conf_ies_len;
-+			plink->tx_conf_ies = NULL;
-+			plink->tx_conf_ies_len = 0;
-+		}
-+		#endif
-+
-+		if (ies && ies_len)
-+			rtw_mfree(ies, ies_len);
-+
-+		#ifndef CONFIG_RTW_MESH_DRIVER_AID
-+		if (tx == _TRUE)
-+			goto release_plink_ctl; /* no need to copy tx conf ies */
-+		#endif
-+
-+		/* copy mesh confirm IEs */
-+		if (mpm_info.pid_v == 1) /* not include MIC & encrypted AMPE */
-+			ies_len = (mic_ie - fhead) - sizeof(struct rtw_ieee80211_hdr_3addr) - 2;
-+		else
-+			ies_len = flen - sizeof(struct rtw_ieee80211_hdr_3addr) - 2;
-+
-+		ies = rtw_zmalloc(ies_len);
-+		if (ies) {
-+			_rtw_memcpy(ies, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + 2, ies_len);
-+			if (tx == _FALSE) {
-+				plink->rx_conf_ies = ies;
-+				plink->rx_conf_ies_len = ies_len;
-+			}
-+			#ifdef CONFIG_RTW_MESH_DRIVER_AID	
-+			else {
-+				plink->tx_conf_ies = ies;
-+				plink->tx_conf_ies_len = ies_len;
-+			}
-+			#endif
-+		}
-+
-+release_plink_ctl:
-+		_exit_critical_bh(&(plink_ctl->lock), &irqL);
-+	}
-+
-+mpm_log:
-+	rtw_mpm_info_msg(&mpm_info, mpm_log_buf);
-+	RTW_INFO("RTW_%s:%s %s\n"
-+		, (tx == _TRUE) ? "Tx" : "Rx"
-+		, action_self_protected_str(action)
-+		, mpm_log_buf
-+	);
-+
-+	ret = 1;
-+
-+exit:
-+	if (nbuf) {
-+		if (ret == 1) {
-+			*buf = nbuf;
-+			*len = nlen;
-+		} else
-+			rtw_mfree(nbuf, nlen);
-+	}
-+
-+	return ret;
-+}
-+
-+static int rtw_mesh_check_frames(_adapter *adapter, const u8 **buf, size_t *len, u8 tx)
-+{
-+	int is_mesh_frame = -1;
-+	const u8 *frame_body;
-+	u8 category, action;
-+
-+	frame_body = *buf + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	category = frame_body[0];
-+
-+	if (category == RTW_WLAN_CATEGORY_SELF_PROTECTED) {
-+		action = frame_body[1];
-+		switch (action) {
-+		case RTW_ACT_SELF_PROTECTED_MESH_OPEN:
-+		case RTW_ACT_SELF_PROTECTED_MESH_CONF:
-+		case RTW_ACT_SELF_PROTECTED_MESH_CLOSE:
-+			rtw_mpm_check_frames(adapter, action, buf, len, tx);
-+			is_mesh_frame = action;
-+			break;
-+		case RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM:
-+		case RTW_ACT_SELF_PROTECTED_MESH_GK_ACK:
-+			RTW_INFO("RTW_%s:%s\n", (tx == _TRUE) ? "Tx" : "Rx", action_self_protected_str(action));
-+			is_mesh_frame = action;
-+			break;
-+		default:
-+			break;
-+		};
-+	}
-+
-+	return is_mesh_frame;
-+}
-+
-+int rtw_mesh_check_frames_tx(_adapter *adapter, const u8 **buf, size_t *len)
-+{
-+	return rtw_mesh_check_frames(adapter, buf, len, _TRUE);
-+}
-+
-+int rtw_mesh_check_frames_rx(_adapter *adapter, const u8 *buf, size_t len)
-+{
-+	return rtw_mesh_check_frames(adapter, &buf, &len, _FALSE);
-+}
-+
-+int rtw_mesh_on_auth(_adapter *adapter, union recv_frame *rframe)
-+{
-+	u8 *whdr = rframe->u.hdr.rx_data;
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+	if (rtw_access_ctrl(adapter, get_addr2_ptr(whdr)) == _FALSE)
-+		return _SUCCESS;
-+#endif
-+
-+	if (!rtw_mesh_plink_get(adapter, get_addr2_ptr(whdr))) {
-+		#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+		rtw_mesh_acnode_set_notify_etime(adapter, whdr);
-+		#endif
-+
-+		if (adapter_to_rfctl(adapter)->offch_state == OFFCHS_NONE)
-+			issue_probereq(adapter, &adapter->mlmepriv.cur_network.network.mesh_id, get_addr2_ptr(whdr));
-+
-+		/* only peer being added (checked by notify conditions) is allowed */
-+		return _SUCCESS;
-+	}
-+
-+	rtw_cfg80211_rx_mframe(adapter, rframe, NULL);
-+	return _SUCCESS;
-+}
-+
-+unsigned int on_action_self_protected(_adapter *adapter, union recv_frame *rframe)
-+{
-+	unsigned int ret = _FAIL;
-+	struct sta_info *sta = NULL;
-+	u8 *pframe = rframe->u.hdr.rx_data;
-+	uint frame_len = rframe->u.hdr.len;
-+	u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
-+	u8 category;
-+	u8 action;
-+
-+	/* check RA matches or not */
-+	if (!_rtw_memcmp(adapter_mac_addr(adapter), GetAddr1Ptr(pframe), ETH_ALEN))
-+		goto exit;
-+
-+	category = frame_body[0];
-+	if (category != RTW_WLAN_CATEGORY_SELF_PROTECTED)
-+		goto exit;
-+
-+	action = frame_body[1];
-+	switch (action) {
-+	case RTW_ACT_SELF_PROTECTED_MESH_OPEN:
-+	case RTW_ACT_SELF_PROTECTED_MESH_CONF:
-+	case RTW_ACT_SELF_PROTECTED_MESH_CLOSE:
-+	case RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM:
-+	case RTW_ACT_SELF_PROTECTED_MESH_GK_ACK:
-+		if (!(MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)))
-+			goto exit;
-+#ifdef CONFIG_IOCTL_CFG80211
-+		#if CONFIG_RTW_MACADDR_ACL
-+		if (rtw_access_ctrl(adapter, get_addr2_ptr(pframe)) == _FALSE)
-+			goto exit;
-+		#endif
-+		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+		if (rtw_mesh_cto_mgate_required(adapter)
-+			/* only peer being added (checked by notify conditions) is allowed */
-+			&& !rtw_mesh_plink_get(adapter, get_addr2_ptr(pframe)))
-+			goto exit;
-+		#endif
-+		rtw_cfg80211_rx_action(adapter, rframe, NULL);
-+		ret = _SUCCESS;
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+		break;
-+	default:
-+		break;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+const u8 ae_to_mesh_ctrl_len[] = {
-+	6,
-+	12, /* MESH_FLAGS_AE_A4 */
-+	18, /* MESH_FLAGS_AE_A5_A6 */
-+	0,
-+};
-+
-+unsigned int on_action_mesh(_adapter *adapter, union recv_frame *rframe)
-+{
-+	unsigned int ret = _FAIL;
-+	struct sta_info *sta = NULL;
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	u8 *pframe = rframe->u.hdr.rx_data;
-+	uint frame_len = rframe->u.hdr.len;
-+	u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
-+	u8 category;
-+	u8 action;
-+
-+	if (!MLME_IS_MESH(adapter))
-+		goto exit;
-+
-+	/* check stainfo exist? */
-+
-+	category = frame_body[0];
-+	if (category != RTW_WLAN_CATEGORY_MESH)
-+		goto exit;
-+
-+	action = frame_body[1];
-+	switch (action) {
-+	case RTW_ACT_MESH_HWMP_PATH_SELECTION:
-+		rtw_mesh_rx_path_sel_frame(adapter, rframe);
-+		ret = _SUCCESS;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+bool rtw_mesh_update_bss_peering_status(_adapter *adapter, WLAN_BSSID_EX *bss)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	u8 num_of_peerings = stapriv->asoc_list_cnt;
-+	bool accept_peerings = stapriv->asoc_list_cnt < mcfg->max_peer_links;
-+	u8 *ie;
-+	int ie_len;
-+	bool updated = 0;
-+
-+#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+	accept_peerings |= plink_ctl->acnode_rsvd;
-+#endif
-+
-+	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, BSS_EX_TLV_IES_LEN(bss));
-+	if (!ie || ie_len != 7) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (GET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2) != num_of_peerings) {
-+		SET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2, num_of_peerings);
-+		updated = 1;
-+	}
-+
-+	if (GET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2) != accept_peerings) {
-+		SET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2, accept_peerings);
-+		updated = 1;
-+	}
-+
-+exit:
-+	return updated;
-+}
-+
-+bool rtw_mesh_update_bss_formation_info(_adapter *adapter, WLAN_BSSID_EX *bss)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	u8 cto_mgate = (minfo->num_gates || mcfg->dot11MeshGateAnnouncementProtocol);
-+	u8 cto_as = 0;
-+	u8 *ie;
-+	int ie_len;
-+	bool updated = 0;
-+
-+	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
-+			BSS_EX_TLV_IES_LEN(bss));
-+	if (!ie || ie_len != 7) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (GET_MESH_CONF_ELE_CTO_MGATE(ie + 2) != cto_mgate) {
-+		SET_MESH_CONF_ELE_CTO_MGATE(ie + 2, cto_mgate);
-+		updated = 1;
-+	}
-+
-+	if (GET_MESH_CONF_ELE_CTO_AS(ie + 2) != cto_as) {
-+		SET_MESH_CONF_ELE_CTO_AS(ie + 2, cto_as);
-+		updated = 1;
-+	}
-+
-+exit:
-+	return updated;
-+}
-+
-+bool rtw_mesh_update_bss_forwarding_state(_adapter *adapter, WLAN_BSSID_EX *bss)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	u8 forward = mcfg->dot11MeshForwarding;
-+	u8 *ie;
-+	int ie_len;
-+	bool updated = 0;
-+
-+	ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
-+			BSS_EX_TLV_IES_LEN(bss));
-+	if (!ie || ie_len != 7) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (GET_MESH_CONF_ELE_FORWARDING(ie + 2) != forward) {
-+		SET_MESH_CONF_ELE_FORWARDING(ie + 2, forward);
-+		updated = 1;
-+	}
-+
-+exit:
-+	return updated;
-+}
-+
-+struct mesh_plink_ent *_rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	struct mesh_plink_ent *ent = NULL;
-+	int i;
-+
-+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
-+		if (plink_ctl->ent[i].valid == _TRUE
-+			&& _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE
-+		) {
-+			ent = &plink_ctl->ent[i];
-+			break;
-+		}
-+	}
-+
-+	return ent;
-+}
-+
-+struct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	struct mesh_plink_ent *ent = NULL;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
-+	ent = _rtw_mesh_plink_get(adapter, hwaddr);
-+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
-+
-+	return ent;
-+}
-+
-+struct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 idx)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	struct mesh_plink_ent *ent = NULL;
-+	int i, j = 0;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
-+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
-+		if (plink_ctl->ent[i].valid == _TRUE
-+			&& plink_ctl->ent[i].plink_state != RTW_MESH_PLINK_ESTAB
-+		) {
-+			if (j == idx) {
-+				ent = &plink_ctl->ent[i];
-+				break;
-+			}
-+			j++;
-+		}
-+	}
-+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
-+
-+	return ent;
-+}
-+
-+int _rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	struct mesh_plink_ent *ent = NULL;
-+	u8 exist = _FALSE;
-+	int i;
-+
-+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
-+		if (plink_ctl->ent[i].valid == _TRUE
-+			&& _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE
-+		) {
-+			ent = &plink_ctl->ent[i];
-+			exist = _TRUE;
-+			break;
-+		}
-+
-+		if (ent == NULL && plink_ctl->ent[i].valid == _FALSE)
-+			ent = &plink_ctl->ent[i];
-+	}
-+
-+	if (exist == _FALSE && ent) {
-+		_rtw_memcpy(ent->addr, hwaddr, ETH_ALEN);
-+		ent->valid = _TRUE;
-+		#ifdef CONFIG_RTW_MESH_AEK
-+		ent->aek_valid = 0;
-+		#endif
-+		ent->llid = 0;
-+		ent->plid = 0;
-+		_rtw_memset(ent->chosen_pmk, 0, 16);
-+		#ifdef CONFIG_RTW_MESH_AEK
-+		_rtw_memset(ent->sel_pcs, 0, 4);
-+		_rtw_memset(ent->l_nonce, 0, 32);
-+		_rtw_memset(ent->p_nonce, 0, 32);
-+		#endif
-+		ent->plink_state = RTW_MESH_PLINK_LISTEN;
-+		#ifndef CONFIG_RTW_MESH_DRIVER_AID
-+		ent->aid = 0;
-+		#endif
-+		ent->peer_aid = 0;
-+		SET_PEER_CONF_DISABLED(ent);
-+		SET_CTO_MGATE_CONF_DISABLED(ent);
-+		plink_ctl->num++;
-+	}
-+
-+	return exist == _TRUE ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL);
-+}
-+
-+int rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	_irqL irqL;
-+	int ret;
-+
-+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
-+	ret = _rtw_mesh_plink_add(adapter, hwaddr);
-+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
-+
-+	return ret;
-+}
-+
-+int rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	struct mesh_plink_ent *ent = NULL;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
-+	ent = _rtw_mesh_plink_get(adapter, hwaddr);
-+	if (ent)
-+		ent->plink_state = state;
-+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
-+
-+	return ent ? _SUCCESS : _FAIL;
-+}
-+
-+#ifdef CONFIG_RTW_MESH_AEK
-+int rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	struct mesh_plink_ent *ent = NULL;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
-+	ent = _rtw_mesh_plink_get(adapter, hwaddr);
-+	if (ent) {
-+		_rtw_memcpy(ent->aek, aek, 32);
-+		ent->aek_valid = 1;
-+	}
-+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
-+
-+	return ent ? _SUCCESS : _FAIL;
-+}
-+#endif
-+
-+#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+int rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	struct mesh_plink_ent *ent = NULL;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
-+	ent = _rtw_mesh_plink_get(adapter, hwaddr);
-+	if (ent) {
-+		if (IS_PEER_CONF_DISABLED(ent))
-+			SET_PEER_CONF_END_TIME(ent, mcfg->peer_sel_policy.peer_conf_timeout_ms);
-+	}
-+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
-+
-+	return ent ? _SUCCESS : _FAIL;
-+}
-+#endif
-+
-+void _rtw_mesh_plink_del_ent(_adapter *adapter, struct mesh_plink_ent *ent)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+
-+	ent->valid = _FALSE;
-+	#ifdef CONFIG_RTW_MESH_DRIVER_AID
-+	if (ent->tx_conf_ies && ent->tx_conf_ies_len)
-+		rtw_mfree(ent->tx_conf_ies, ent->tx_conf_ies_len);
-+	ent->tx_conf_ies = NULL;
-+	ent->tx_conf_ies_len = 0;
-+	#endif
-+	if (ent->rx_conf_ies && ent->rx_conf_ies_len)
-+		rtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len);
-+	ent->rx_conf_ies = NULL;
-+	ent->rx_conf_ies_len = 0;
-+	if (ent->scanned)
-+		ent->scanned = NULL;
-+	plink_ctl->num--;
-+}
-+
-+int rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	struct mesh_plink_ent *ent = NULL;
-+	u8 exist = _FALSE;
-+	int i;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
-+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
-+		if (plink_ctl->ent[i].valid == _TRUE
-+			&& _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE
-+		) {
-+			ent = &plink_ctl->ent[i];
-+			exist = _TRUE;
-+			break;
-+		}
-+	}
-+
-+	if (exist == _TRUE)
-+		_rtw_mesh_plink_del_ent(adapter, ent);
-+
-+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
-+
-+	return exist == _TRUE ? _SUCCESS : RTW_ALREADY;
-+}
-+
-+void rtw_mesh_plink_ctl_init(_adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	int i;
-+
-+	_rtw_spinlock_init(&plink_ctl->lock);
-+	plink_ctl->num = 0;
-+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++)
-+		plink_ctl->ent[i].valid = _FALSE;
-+
-+#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+	_rtw_init_queue(&plink_ctl->peer_blacklist);
-+#endif
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	_rtw_init_queue(&plink_ctl->cto_mgate_blacklist);
-+#endif
-+}
-+
-+void rtw_mesh_plink_ctl_deinit(_adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	struct mesh_plink_ent *ent;
-+	int i;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
-+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
-+		ent = &plink_ctl->ent[i];
-+		#ifdef CONFIG_RTW_MESH_DRIVER_AID
-+		if (ent->tx_conf_ies && ent->tx_conf_ies_len)
-+			rtw_mfree(ent->tx_conf_ies, ent->tx_conf_ies_len);
-+		#endif
-+		if (ent->rx_conf_ies && ent->rx_conf_ies_len)
-+			rtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len);
-+	}
-+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
-+
-+	_rtw_spinlock_free(&plink_ctl->lock);
-+
-+#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+	rtw_mesh_peer_blacklist_flush(adapter);
-+	_rtw_deinit_queue(&plink_ctl->peer_blacklist);
-+#endif
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	rtw_mesh_cto_mgate_blacklist_flush(adapter);
-+	_rtw_deinit_queue(&plink_ctl->cto_mgate_blacklist);
-+#endif
-+}
-+
-+void dump_mesh_plink_ctl(void *sel, _adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	struct mesh_plink_ent *ent;
-+	int i;
-+
-+	RTW_PRINT_SEL(sel, "num:%u\n", plink_ctl->num);
-+	#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+	RTW_PRINT_SEL(sel, "acnode_rsvd:%u\n", plink_ctl->acnode_rsvd);
-+	#endif
-+
-+	for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++)  {
-+		ent = &plink_ctl->ent[i];
-+		if (!ent->valid)
-+			continue;
-+
-+		RTW_PRINT_SEL(sel, "\n");
-+		RTW_PRINT_SEL(sel, "peer:"MAC_FMT"\n", MAC_ARG(ent->addr));
-+		RTW_PRINT_SEL(sel, "plink_state:%s\n", rtw_mesh_plink_str(ent->plink_state));
-+
-+		#ifdef CONFIG_RTW_MESH_AEK
-+		if (ent->aek_valid)
-+			RTW_PRINT_SEL(sel, "aek:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->aek), KEY_ARG(ent->aek + 16));
-+		#endif
-+
-+		RTW_PRINT_SEL(sel, "llid:%u, plid:%u\n", ent->llid, ent->plid);
-+		#ifndef CONFIG_RTW_MESH_DRIVER_AID
-+		RTW_PRINT_SEL(sel, "aid:%u\n", ent->aid);
-+		#endif
-+		RTW_PRINT_SEL(sel, "peer_aid:%u\n", ent->peer_aid);
-+
-+		RTW_PRINT_SEL(sel, "chosen_pmk:"KEY_FMT"\n", KEY_ARG(ent->chosen_pmk));
-+
-+		#ifdef CONFIG_RTW_MESH_AEK
-+		RTW_PRINT_SEL(sel, "sel_pcs:%02x%02x%02x%02x\n"
-+			, ent->sel_pcs[0], ent->sel_pcs[1], ent->sel_pcs[2], ent->sel_pcs[3]);
-+		RTW_PRINT_SEL(sel, "l_nonce:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->l_nonce), KEY_ARG(ent->l_nonce + 16));
-+		RTW_PRINT_SEL(sel, "p_nonce:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->p_nonce), KEY_ARG(ent->p_nonce + 16));
-+		#endif
-+
-+		#ifdef CONFIG_RTW_MESH_DRIVER_AID
-+		RTW_PRINT_SEL(sel, "tx_conf_ies:%p, len:%u\n", ent->tx_conf_ies, ent->tx_conf_ies_len);
-+		#endif
-+		RTW_PRINT_SEL(sel, "rx_conf_ies:%p, len:%u\n", ent->rx_conf_ies, ent->rx_conf_ies_len);
-+		RTW_PRINT_SEL(sel, "scanned:%p\n", ent->scanned);
-+
-+		#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+		if (!IS_PEER_CONF_DISABLED(ent)) {
-+			if (!IS_PEER_CONF_TIMEOUT(ent))
-+				RTW_PRINT_SEL(sel, "peer_conf:%d\n", rtw_systime_to_ms(ent->peer_conf_end_time - rtw_get_current_time()));
-+			else
-+				RTW_PRINT_SEL(sel, "peer_conf:TIMEOUT\n");
-+		}
-+		#endif
-+
-+		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+		if (!IS_CTO_MGATE_CONF_DISABLED(ent)) {
-+			if (!IS_CTO_MGATE_CONF_TIMEOUT(ent))
-+				RTW_PRINT_SEL(sel, "cto_mgate_conf:%d\n", rtw_systime_to_ms(ent->cto_mgate_conf_end_time - rtw_get_current_time()));
-+			else
-+				RTW_PRINT_SEL(sel, "cto_mgate_conf:TIMEOUT\n");
-+		}
-+		#endif
-+	}
-+}
-+
-+/* this function is called with plink_ctl being locked */
-+static int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *plink, struct sta_info *sta)
-+{
-+#ifndef DBG_RTW_MESH_PEER_ESTABLISH
-+#define DBG_RTW_MESH_PEER_ESTABLISH 0
-+#endif
-+
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	u8 *tlv_ies;
-+	u16 tlv_ieslen;
-+	struct rtw_ieee802_11_elems elems;
-+	_irqL irqL;
-+	int i;
-+	u16 status = 0;
-+	int ret = _FAIL;
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	u8 sta_tbtx_enable = _FALSE;
-+#endif
-+
-+	if (!plink->rx_conf_ies || !plink->rx_conf_ies_len) {
-+		RTW_INFO(FUNC_ADPT_FMT" no rx confirm from sta "MAC_FMT"\n"
-+			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
-+		goto exit;
-+	}
-+
-+	if (plink->rx_conf_ies_len < 4) {
-+		RTW_INFO(FUNC_ADPT_FMT" confirm from sta "MAC_FMT" too short\n"
-+			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_RTW_MESH_DRIVER_AID
-+	if (!plink->tx_conf_ies || !plink->tx_conf_ies_len) {
-+		RTW_INFO(FUNC_ADPT_FMT" no tx confirm to sta "MAC_FMT"\n"
-+			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
-+		goto exit;
-+	}
-+
-+	if (plink->tx_conf_ies_len < 4) {
-+		RTW_INFO(FUNC_ADPT_FMT" confirm to sta "MAC_FMT" too short\n"
-+			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
-+		goto exit;
-+	}
-+#endif
-+
-+	tlv_ies = plink->rx_conf_ies + 4;
-+	tlv_ieslen = plink->rx_conf_ies_len - 4;
-+
-+	if (DBG_RTW_MESH_PEER_ESTABLISH)
-+		dump_ies(RTW_DBGDUMP, tlv_ies, tlv_ieslen);
-+
-+	if (rtw_ieee802_11_parse_elems(tlv_ies, tlv_ieslen, &elems, 1) == ParseFailed) {
-+		RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" sent invalid confirm\n"
-+			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
-+		goto exit;
-+	}
-+
-+	SET_PEER_CONF_DISABLED(plink);
-+	if (rtw_bss_is_cto_mgate(&plink->scanned->network)
-+		&& !rtw_bss_is_forwarding(&plink->scanned->network))
-+		SET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms);
-+	else
-+		SET_CTO_MGATE_CONF_DISABLED(plink);
-+
-+	sta->state &= (~WIFI_FW_AUTH_SUCCESS);
-+	sta->state |= WIFI_FW_ASSOC_STATE;
-+
-+	rtw_ap_parse_sta_capability(adapter, sta, plink->rx_conf_ies);
-+
-+	status = rtw_ap_parse_sta_supported_rates(adapter, sta, tlv_ies, tlv_ieslen);
-+	if (status != _STATS_SUCCESSFUL_)
-+		goto exit;
-+
-+	status = rtw_ap_parse_sta_security_ie(adapter, sta, &elems);
-+	if (status != _STATS_SUCCESSFUL_) {
-+		RTW_INFO(FUNC_ADPT_FMT" security check fail, status=%u\n", FUNC_ADPT_ARG(adapter), status);
-+		goto exit;
-+	}
-+
-+	rtw_ap_parse_sta_wmm_ie(adapter, sta, tlv_ies, tlv_ieslen);
-+#ifdef CONFIG_RTS_FULL_BW
-+	/*check vendor IE*/
-+	rtw_parse_sta_vendor_ie_8812(adapter, sta, tlv_ies, tlv_ieslen);
-+#endif/*CONFIG_RTS_FULL_BW*/
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	if (elems.tbtx_cap && elems.tbtx_cap_len != 0) {
-+		if(rtw_is_tbtx_capabilty(elems.tbtx_cap, elems.tbtx_cap_len)) {
-+			sta_tbtx_enable = _TRUE;
-+		}
-+	}
-+#endif
-+
-+	rtw_ap_parse_sta_ht_ie(adapter, sta, &elems);
-+	rtw_ap_parse_sta_vht_ie(adapter, sta, &elems);
-+
-+	/* AID */
-+#ifdef CONFIG_RTW_MESH_DRIVER_AID
-+	sta->cmn.aid = RTW_GET_LE16(plink->tx_conf_ies + 2);
-+#else
-+	sta->cmn.aid = plink->aid;
-+#endif
-+	stapriv->sta_aid[sta->cmn.aid - 1] = sta;
-+	RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" aid:%u\n"
-+		, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr), sta->cmn.aid);
-+
-+	sta->state &= (~WIFI_FW_ASSOC_STATE);
-+	sta->state |= WIFI_FW_ASSOC_SUCCESS;
-+
-+	sta->local_mps = RTW_MESH_PS_ACTIVE;
-+
-+	rtw_ewma_err_rate_init(&sta->metrics.err_rate);
-+	rtw_ewma_err_rate_add(&sta->metrics.err_rate, 1);
-+	/* init data_rate to 1M */
-+	sta->metrics.data_rate = 10;
-+	sta->alive = _TRUE;
-+
-+	_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+	if (rtw_is_list_empty(&sta->asoc_list)) {
-+		STA_SET_MESH_PLINK(sta, plink);
-+		/* TBD: up layer timeout mechanism */
-+		/* sta->expire_to = mcfg->plink_timeout / 2; */
-+		rtw_list_insert_tail(&sta->asoc_list, &stapriv->asoc_list);
-+		stapriv->asoc_list_cnt++;
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+		if (sta_tbtx_enable) {
-+			sta->tbtx_enable = _TRUE;
-+			stapriv->tbtx_asoc_list_cnt++;
-+		}
-+#endif
-+	}
-+	_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+
-+	bss_cap_update_on_sta_join(adapter, sta);
-+	sta_info_update(adapter, sta);
-+	report_add_sta_event(adapter, sta->cmn.mac_addr);
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+int rtw_mesh_set_plink_state(_adapter *adapter, const u8 *mac, u8 plink_state)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	struct mesh_plink_ent *plink = NULL;
-+	_irqL irqL2;
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct sta_info *sta = NULL;
-+	_irqL irqL;
-+	struct sta_info *del_sta = NULL;
-+	int ret = _SUCCESS;
-+
-+	_enter_critical_bh(&(plink_ctl->lock), &irqL2);
-+
-+	plink = _rtw_mesh_plink_get(adapter, mac);
-+	if (!plink) {
-+		ret = _FAIL;
-+		goto release_plink_ctl;
-+	}
-+
-+	plink->plink_state = plink_state;
-+
-+	#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+	if (plink_state == RTW_MESH_PLINK_OPN_SNT) {
-+		if (rtw_mesh_scanned_is_acnode_confirmed(adapter, plink->scanned)
-+			&& rtw_mesh_acnode_prevent_allow_sacrifice(adapter)
-+		) {
-+			struct sta_info *sac = rtw_mesh_acnode_prevent_pick_sacrifice(adapter);
-+
-+			if (sac) {
-+				del_sta = sac;
-+				_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+				if (!rtw_is_list_empty(&del_sta->asoc_list)) {
-+					rtw_list_delete(&del_sta->asoc_list);
-+					stapriv->asoc_list_cnt--;
-+					#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+					if (del_sta->tbtx_enable)
-+						stapriv->tbtx_asoc_list_cnt--;
-+					#endif
-+					STA_SET_MESH_PLINK(del_sta, NULL);
-+				}
-+				_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+				RTW_INFO(FUNC_ADPT_FMT" sacrifice "MAC_FMT" for acnode\n"
-+					, FUNC_ADPT_ARG(adapter), MAC_ARG(del_sta->cmn.mac_addr));
-+			}
-+		}
-+	} else
-+	#endif
-+	if (plink_state == RTW_MESH_PLINK_OPN_RCVD
-+		|| plink_state == RTW_MESH_PLINK_CNF_RCVD
-+		|| plink_state == RTW_MESH_PLINK_ESTAB
-+	) {
-+		sta = rtw_get_stainfo(stapriv, mac);
-+		if (!sta) {
-+			sta = rtw_alloc_stainfo(stapriv, mac);
-+			if (!sta)
-+				goto release_plink_ctl;
-+		}
-+
-+		if (plink_state == RTW_MESH_PLINK_ESTAB) {
-+			if (rtw_mesh_peer_establish(adapter, plink, sta) != _SUCCESS) {
-+				del_sta = sta;
-+				ret = _FAIL;
-+				goto release_plink_ctl;
-+			}
-+		}
-+	}
-+	else if (plink_state == RTW_MESH_PLINK_HOLDING) {
-+		del_sta = rtw_get_stainfo(stapriv, mac);
-+		if (!del_sta)
-+			goto release_plink_ctl;
-+
-+		_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+		if (!rtw_is_list_empty(&del_sta->asoc_list)) {
-+			rtw_list_delete(&del_sta->asoc_list);
-+			stapriv->asoc_list_cnt--;
-+			#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+			if (del_sta->tbtx_enable)
-+				stapriv->tbtx_asoc_list_cnt--;
-+			#endif
-+			STA_SET_MESH_PLINK(del_sta, NULL);
-+		}
-+		_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+	}
-+
-+release_plink_ctl:
-+	_exit_critical_bh(&(plink_ctl->lock), &irqL2);
-+
-+	if (del_sta) {
-+		u8 sta_addr[ETH_ALEN];
-+		u8 updated = _FALSE;
-+
-+		_rtw_memcpy(sta_addr, del_sta->cmn.mac_addr, ETH_ALEN);
-+		updated = ap_free_sta(adapter, del_sta, 0, 0, 1);
-+		rtw_mesh_expire_peer(stapriv->padapter, sta_addr);
-+
-+		associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);
-+	}
-+
-+	return ret;
-+}
-+
-+struct mesh_set_plink_cmd_parm {
-+	const u8 *mac;
-+	u8 plink_state;
-+};
-+
-+u8 rtw_mesh_set_plink_state_cmd_hdl(_adapter *adapter, u8 *parmbuf)
-+{
-+	struct mesh_set_plink_cmd_parm *parm = (struct mesh_set_plink_cmd_parm *)parmbuf;
-+
-+	if (rtw_mesh_set_plink_state(adapter, parm->mac, parm->plink_state) == _SUCCESS)
-+		return	H2C_SUCCESS;
-+
-+	return H2C_CMD_FAIL;
-+}
-+
-+u8 rtw_mesh_set_plink_state_cmd(_adapter *adapter, const u8 *mac, u8 plink_state)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct mesh_set_plink_cmd_parm *parm;
-+	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8 res = _SUCCESS;
-+
-+	/* prepare cmd parameter */
-+	parm = rtw_zmalloc(sizeof(*parm));
-+	if (parm == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	parm->mac = mac;
-+	parm->plink_state = plink_state;
-+
-+	/* need enqueue, prepare cmd_obj and enqueue */
-+	cmdobj = rtw_zmalloc(sizeof(*cmdobj));
-+	if (cmdobj == NULL) {
-+		res = _FAIL;
-+		rtw_mfree(parm, sizeof(*parm));
-+		goto exit;
-+	}
-+
-+	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_MESH_PLINK_STATE);
-+	cmdobj->sctx = &sctx;
-+	rtw_sctx_init(&sctx, 2000);
-+
-+	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
-+	if (res == _SUCCESS) {
-+		rtw_sctx_wait(&sctx, __func__);
-+		_enter_critical_mutex(&cmdpriv->sctx_mutex, NULL);
-+		if (sctx.status == RTW_SCTX_SUBMITTED)
-+			cmdobj->sctx = NULL;
-+		_exit_critical_mutex(&cmdpriv->sctx_mutex, NULL);
-+		if (sctx.status != RTW_SCTX_DONE_SUCCESS)
-+			res = _FAIL;
-+	}
-+
-+exit:
-+	return res;
-+}
-+
-+void rtw_mesh_expire_peer_notify(_adapter *adapter, const u8 *peer_addr)
-+{
-+	u8 null_ssid[2] = {0, 0};
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	rtw_cfg80211_notify_new_peer_candidate(adapter->rtw_wdev
-+		, peer_addr
-+		, null_ssid
-+		, 2
-+		, 0
-+		, GFP_ATOMIC
-+	);
-+#endif
-+
-+	return;
-+}
-+
-+static u8 *rtw_mesh_construct_peer_mesh_close(_adapter *adapter, struct mesh_plink_ent *plink, u16 reason, u32 *len)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	u8 *frame = NULL, *pos;
-+	u32 flen;
-+	struct rtw_ieee80211_hdr *whdr;
-+
-+	if (minfo->mesh_auth_id && !MESH_PLINK_AEK_VALID(plink))
-+		goto exit;
-+
-+	flen = sizeof(struct rtw_ieee80211_hdr_3addr)
-+		+ 2 /* category, action */
-+		+ 2 + minfo->mesh_id_len /* mesh id */
-+		+ 2 + 8 + (minfo->mesh_auth_id ? 16 : 0) /* mpm */
-+		+ (minfo->mesh_auth_id ? 2 + 16 /* AES_BLOCK_SIZE */ : 0) /* mic */
-+		+ (minfo->mesh_auth_id ? 70 : 0) /* ampe */
-+		;
-+
-+	pos = frame = rtw_zmalloc(flen);
-+	if (!frame)
-+		goto exit;
-+
-+	whdr = (struct rtw_ieee80211_hdr *)frame;
-+	_rtw_memcpy(whdr->addr1, adapter_mac_addr(adapter), ETH_ALEN);
-+	_rtw_memcpy(whdr->addr2, plink->addr, ETH_ALEN);
-+	_rtw_memcpy(whdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);
-+
-+	set_frame_sub_type(frame, WIFI_ACTION);
-+
-+	pos += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	*(pos++) = RTW_WLAN_CATEGORY_SELF_PROTECTED;
-+	*(pos++) = RTW_ACT_SELF_PROTECTED_MESH_CLOSE;
-+
-+	pos = rtw_set_ie_mesh_id(pos, NULL, minfo->mesh_id, minfo->mesh_id_len);
-+
-+	pos = rtw_set_ie_mpm(pos, NULL
-+		, minfo->mesh_auth_id ? 1 : 0
-+		, plink->plid
-+		, &plink->llid
-+		, &reason
-+		, minfo->mesh_auth_id ? plink->chosen_pmk : NULL);
-+
-+#ifdef CONFIG_RTW_MESH_AEK
-+	if (minfo->mesh_auth_id) {
-+		u8 ampe_buf[70];
-+		int enc_ret;
-+
-+		*pos = WLAN_EID_MIC;
-+		*(pos + 1) = 16 /* AES_BLOCK_SIZE */;
-+
-+		ampe_buf[0] = WLAN_EID_AMPE;
-+		ampe_buf[1] = 68;
-+		_rtw_memcpy(ampe_buf + 2, plink->sel_pcs, 4);
-+		_rtw_memcpy(ampe_buf + 6, plink->p_nonce, 32);
-+		_rtw_memcpy(ampe_buf + 38, plink->l_nonce, 32);
-+
-+		enc_ret = rtw_mpm_ampe_enc(adapter, plink
-+			, frame + sizeof(struct rtw_ieee80211_hdr_3addr)
-+			, pos, ampe_buf, 1);
-+		if (enc_ret != _SUCCESS) {
-+			rtw_mfree(frame, flen);
-+			frame = NULL;
-+			goto exit;
-+		}
-+	}
-+#endif
-+
-+	*len = flen;
-+
-+exit:
-+	return frame;
-+}
-+
-+void _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink)
-+{
-+#if defined(CONFIG_RTW_MESH_STA_DEL_DISASOC)
-+	_rtw_mesh_plink_del_ent(adapter, plink);
-+	rtw_cfg80211_indicate_sta_disassoc(adapter, plink->addr, 0);
-+#else
-+	u8 *frame = NULL;
-+	u32 flen;
-+
-+	if (plink->plink_state == RTW_MESH_PLINK_ESTAB)
-+		frame = rtw_mesh_construct_peer_mesh_close(adapter, plink, WLAN_REASON_MESH_CLOSE, &flen);
-+
-+	if (frame) {
-+		struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+		struct wireless_dev *wdev = adapter->rtw_wdev;
-+		s32 freq = rtw_ch2freq(mlmeext->cur_channel);
-+
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+		rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, flen, GFP_ATOMIC);
-+		#else
-+		cfg80211_rx_action(adapter->pnetdev, freq, frame, flen, GFP_ATOMIC);
-+		#endif
-+
-+		rtw_mfree(frame, flen);
-+	} else {
-+		rtw_mesh_expire_peer_notify(adapter, plink->addr);
-+		RTW_INFO(FUNC_ADPT_FMT" set "MAC_FMT" plink unknown\n"
-+			, FUNC_ADPT_ARG(adapter), MAC_ARG(plink->addr));
-+		plink->plink_state = RTW_MESH_PLINK_UNKNOWN;
-+	}
-+#endif
-+}
-+
-+void rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+	struct mesh_plink_ent *plink;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&(plink_ctl->lock), &irqL);
-+
-+	plink = _rtw_mesh_plink_get(adapter, peer_addr);
-+	if (!plink)
-+		goto exit;
-+
-+	_rtw_mesh_expire_peer_ent(adapter, plink);
-+
-+exit:
-+	_exit_critical_bh(&(plink_ctl->lock), &irqL);
-+}
-+
-+u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps)
-+{
-+	_irqL irqL;
-+	_list *head, *list;
-+	struct sta_info *sta;
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	u8 sta_alive_num = 0, i;
-+	char sta_alive_list[NUM_STA];
-+	u8 annc_cnt = 0;
-+
-+	if (rtw_linked_check(adapter) == _FALSE)
-+		goto exit;
-+
-+	_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+
-+	head = &stapriv->asoc_list;
-+	list = get_next(head);
-+	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
-+		int stainfo_offset;
-+
-+		sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
-+		list = get_next(list);
-+
-+		stainfo_offset = rtw_stainfo_offset(stapriv, sta);
-+		if (stainfo_offset_valid(stainfo_offset))
-+			sta_alive_list[sta_alive_num++] = stainfo_offset;
-+	}
-+	_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+
-+	for (i = 0; i < sta_alive_num; i++) {
-+		sta = rtw_get_stainfo_by_offset(stapriv, sta_alive_list[i]);
-+		if (!sta)
-+			continue;
-+
-+		issue_qos_nulldata(adapter, sta->cmn.mac_addr, 7, ps, 3, 500);
-+		annc_cnt++;
-+	}
-+
-+exit:
-+	return annc_cnt;
-+}
-+
-+static void mpath_tx_tasklet_hdl(void *priv)
-+{
-+	_adapter *adapter = (_adapter *)priv;
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct xmit_frame *xframe;
-+	_list *list, *head;
-+	_list tmp;
-+	u32 tmp_len;
-+	s32 res;
-+
-+	_rtw_init_listhead(&tmp);
-+
-+	while (1) {
-+		tmp_len = 0;
-+		enter_critical_bh(&minfo->mpath_tx_queue.lock);
-+		if (minfo->mpath_tx_queue_len) {
-+			rtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp);
-+			tmp_len = minfo->mpath_tx_queue_len;
-+			minfo->mpath_tx_queue_len = 0;
-+		}
-+		exit_critical_bh(&minfo->mpath_tx_queue.lock);
-+
-+		if (!tmp_len)
-+			break;
-+
-+		head = &tmp;
-+		list = get_next(head);
-+		while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+			xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
-+			list = get_next(list);
-+			rtw_list_delete(&xframe->list);
-+			res = rtw_xmit_posthandle(adapter, xframe, xframe->pkt);
-+			if (res < 0) {
-+				#ifdef DBG_TX_DROP_FRAME
-+				RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__);
-+				#endif
-+				adapter->xmitpriv.tx_drop++;
-+			}
-+		}
-+	}
-+}
-+
-+static void rtw_mpath_tx_queue_flush(_adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct xmit_frame *xframe;
-+	_list *list, *head;
-+	_list tmp;
-+
-+	_rtw_init_listhead(&tmp);
-+
-+	enter_critical_bh(&minfo->mpath_tx_queue.lock);
-+	rtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp);
-+	minfo->mpath_tx_queue_len = 0;
-+	exit_critical_bh(&minfo->mpath_tx_queue.lock);
-+
-+	head = &tmp;
-+	list = get_next(head);
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
-+		list = get_next(list);
-+		rtw_list_delete(&xframe->list);
-+		rtw_free_xmitframe(&adapter->xmitpriv, xframe);
-+	}
-+}
-+
-+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
-+#if defined(CONFIG_SLUB)
-+#include <linux/slub_def.h>
-+#elif defined(CONFIG_SLAB)
-+#include <linux/slab_def.h>
-+#endif
-+typedef struct kmem_cache rtw_mcache;
-+#endif
-+
-+rtw_mcache *rtw_mcache_create(const char *name, size_t size)
-+{
-+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
-+	return kmem_cache_create(name, size, 0, 0, NULL);
-+#else
-+	#error "TBD\n";
-+#endif
-+}
-+
-+void rtw_mcache_destroy(rtw_mcache *s)
-+{
-+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
-+	kmem_cache_destroy(s);
-+#else
-+	#error "TBD\n";
-+#endif
-+}
-+
-+void *_rtw_mcache_alloc(rtw_mcache *cachep)
-+{
-+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
-+	return kmem_cache_alloc(cachep, GFP_ATOMIC);
-+#else
-+	#error "TBD\n";
-+#endif
-+}
-+
-+void _rtw_mcache_free(rtw_mcache *cachep, void *objp)
-+{
-+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
-+	kmem_cache_free(cachep, objp);
-+#else
-+	#error "TBD\n";
-+#endif
-+}
-+
-+#ifdef DBG_MEM_ALLOC
-+inline void *dbg_rtw_mcache_alloc(rtw_mcache *cachep, const enum mstat_f flags, const char *func, const int line)
-+{
-+	void *p;
-+	u32 sz = cachep->size;
-+
-+	if (match_mstat_sniff_rules(flags, sz))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u)\n", func, line, __func__, sz);
-+
-+	p = _rtw_mcache_alloc(cachep);
-+
-+	rtw_mstat_update(
-+		flags
-+		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
-+		, sz
-+	);
-+
-+	return p;
-+}
-+
-+inline void dbg_rtw_mcache_free(rtw_mcache *cachep, void *pbuf, const enum mstat_f flags, const char *func, const int line)
-+{
-+	u32 sz = cachep->size;
-+
-+	if (match_mstat_sniff_rules(flags, sz))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u)\n", func, line, __func__, sz);
-+
-+	_rtw_mcache_free(cachep, pbuf);
-+
-+	rtw_mstat_update(
-+		flags
-+		, MSTAT_FREE
-+		, sz
-+	);
-+}
-+
-+#define rtw_mcache_alloc(cachep) dbg_rtw_mcache_alloc(cachep, MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
-+#define rtw_mcache_free(cachep, objp) dbg_rtw_mcache_free(cachep, objp, MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
-+#else
-+#define rtw_mcache_alloc(cachep) _rtw_mcache_alloc(cachep)
-+#define rtw_mcache_free(cachep, objp) _rtw_mcache_free(cachep, objp)
-+#endif /* DBG_MEM_ALLOC */
-+
-+/* Mesh Received Cache */
-+#define RTW_MRC_BUCKETS			256 /* must be a power of 2 */
-+#define RTW_MRC_QUEUE_MAX_LEN	4
-+#define RTW_MRC_TIMEOUT_MS		(3 * 1000)
-+
-+/**
-+ * struct rtw_mrc_entry - entry in the Mesh Received Cache
-+ *
-+ * @seqnum: mesh sequence number of the frame
-+ * @exp_time: expiration time of the entry
-+ * @msa: mesh source address of the frame
-+ * @list: hashtable list pointer
-+ *
-+ * The Mesh Received Cache keeps track of the latest received frames that
-+ * have been received by a mesh interface and discards received frames
-+ * that are found in the cache.
-+ */
-+struct rtw_mrc_entry {
-+	rtw_hlist_node list;
-+	systime exp_time;
-+	u32 seqnum;
-+	u8 msa[ETH_ALEN];
-+};
-+
-+struct rtw_mrc {
-+	rtw_hlist_head bucket[RTW_MRC_BUCKETS];
-+	u32 idx_mask;
-+	rtw_mcache *cache;
-+};
-+
-+static int rtw_mrc_init(_adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	char cache_name[IFNAMSIZ + 8 + 1];
-+	int i;
-+
-+	minfo->mrc = rtw_malloc(sizeof(struct rtw_mrc));
-+	if (!minfo->mrc)
-+		return -ENOMEM;
-+	minfo->mrc->idx_mask = RTW_MRC_BUCKETS - 1;
-+	for (i = 0; i < RTW_MRC_BUCKETS; i++)
-+		rtw_hlist_head_init(&minfo->mrc->bucket[i]);
-+
-+	sprintf(cache_name, "rtw_mrc_%s", ADPT_ARG(adapter));
-+	minfo->mrc->cache = rtw_mcache_create(cache_name, sizeof(struct rtw_mrc_entry));
-+
-+	return 0;
-+}
-+
-+static void rtw_mrc_free(_adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct rtw_mrc *mrc = minfo->mrc;
-+	struct rtw_mrc_entry *p;
-+	rtw_hlist_node *np, *n;
-+	int i;
-+
-+	if (!mrc)
-+		return;
-+
-+	for (i = 0; i < RTW_MRC_BUCKETS; i++) {
-+		rtw_hlist_for_each_entry_safe(p, np, n, &mrc->bucket[i], list) {
-+			rtw_hlist_del(&p->list);
-+			rtw_mcache_free(mrc->cache, p);
-+		}
-+	}
-+
-+	rtw_mcache_destroy(mrc->cache);
-+
-+	rtw_mfree(mrc, sizeof(struct rtw_mrc));
-+	minfo->mrc = NULL;
-+}
-+
-+/**
-+ * rtw_mrc_check - Check frame in mesh received cache and add if absent.
-+ *
-+ * @adapter:	interface
-+ * @msa:		mesh source address
-+ * @seq:		mesh seq number
-+ *
-+ * Returns: 0 if the frame is not in the cache, nonzero otherwise.
-+ *
-+ * Checks using the mesh source address and the mesh sequence number if we have
-+ * received this frame lately. If the frame is not in the cache, it is added to
-+ * it.
-+ */
-+static int rtw_mrc_check(_adapter *adapter, const u8 *msa, u32 seq)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct rtw_mrc *mrc = minfo->mrc;
-+	int entries = 0;
-+	u8 idx;
-+	struct rtw_mrc_entry *p;
-+	rtw_hlist_node *np, *n;
-+	u8 timeout;
-+
-+	if (!mrc)
-+		return -1;
-+
-+	idx = seq & mrc->idx_mask;
-+	rtw_hlist_for_each_entry_safe(p, np, n, &mrc->bucket[idx], list) {
-+		++entries;
-+		timeout = rtw_time_after(rtw_get_current_time(), p->exp_time);
-+		if (timeout || entries == RTW_MRC_QUEUE_MAX_LEN) {
-+			if (!timeout)
-+				minfo->mshstats.mrc_del_qlen++;
-+
-+			rtw_hlist_del(&p->list);
-+			rtw_mcache_free(mrc->cache, p);
-+			--entries;
-+		} else if ((seq == p->seqnum) && _rtw_memcmp(msa, p->msa, ETH_ALEN) == _TRUE)
-+			return -1;
-+	}
-+
-+	p = rtw_mcache_alloc(mrc->cache);
-+	if (!p)
-+		return 0;
-+
-+	p->seqnum = seq;
-+	p->exp_time = rtw_get_current_time() + rtw_ms_to_systime(RTW_MRC_TIMEOUT_MS);
-+	_rtw_memcpy(p->msa, msa, ETH_ALEN);
-+	rtw_hlist_add_head(&p->list, &mrc->bucket[idx]);
-+	return 0;
-+}
-+
-+static int rtw_mesh_decache(_adapter *adapter, const u8 *msa, u32 seq)
-+{
-+	return rtw_mrc_check(adapter, msa, seq);
-+}
-+
-+#ifndef RTW_MESH_SCAN_RESULT_EXP_MS
-+#define RTW_MESH_SCAN_RESULT_EXP_MS (10 * 1000)
-+#endif
-+
-+#ifndef RTW_MESH_ACNODE_PREVENT
-+#define RTW_MESH_ACNODE_PREVENT 0
-+#endif
-+#ifndef RTW_MESH_ACNODE_CONF_TIMEOUT_MS
-+#define RTW_MESH_ACNODE_CONF_TIMEOUT_MS (20 * 1000)
-+#endif
-+#ifndef RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS
-+#define RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS (2 * 1000)
-+#endif
-+
-+#ifndef RTW_MESH_OFFCH_CAND
-+#define RTW_MESH_OFFCH_CAND 1
-+#endif
-+#ifndef RTW_MESH_OFFCH_CAND_FIND_INT_MS
-+#define RTW_MESH_OFFCH_CAND_FIND_INT_MS (10 * 1000)
-+#endif
-+
-+#ifndef RTW_MESH_PEER_CONF_TIMEOUT_MS
-+#define RTW_MESH_PEER_CONF_TIMEOUT_MS (20 * 1000)
-+#endif
-+#ifndef RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS
-+#define RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS (20 * 1000)
-+#endif
-+
-+#ifndef RTW_MESH_CTO_MGATE_REQUIRE
-+#define RTW_MESH_CTO_MGATE_REQUIRE 0
-+#endif
-+#ifndef RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS
-+#define RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS (20 * 1000)
-+#endif
-+#ifndef RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS
-+#define RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS (20 * 1000)
-+#endif
-+
-+void rtw_mesh_cfg_init_peer_sel_policy(struct rtw_mesh_cfg *mcfg)
-+{
-+	struct mesh_peer_sel_policy *sel_policy = &mcfg->peer_sel_policy;
-+
-+	sel_policy->scanr_exp_ms = RTW_MESH_SCAN_RESULT_EXP_MS;
-+
-+#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+	sel_policy->acnode_prevent = RTW_MESH_ACNODE_PREVENT;
-+	sel_policy->acnode_conf_timeout_ms = RTW_MESH_ACNODE_CONF_TIMEOUT_MS;
-+	sel_policy->acnode_notify_timeout_ms = RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS;
-+#endif
-+
-+#if CONFIG_RTW_MESH_OFFCH_CAND
-+	sel_policy->offch_cand = RTW_MESH_OFFCH_CAND;
-+	sel_policy->offch_find_int_ms = RTW_MESH_OFFCH_CAND_FIND_INT_MS;
-+#endif
-+
-+#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+	sel_policy->peer_conf_timeout_ms = RTW_MESH_PEER_CONF_TIMEOUT_MS;
-+	sel_policy->peer_blacklist_timeout_ms = RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS;
-+#endif
-+
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	sel_policy->cto_mgate_require = RTW_MESH_CTO_MGATE_REQUIRE;
-+	sel_policy->cto_mgate_conf_timeout_ms = RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS;
-+	sel_policy->cto_mgate_blacklist_timeout_ms = RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS;
-+#endif
-+}
-+
-+void rtw_mesh_cfg_init(_adapter *adapter)
-+{
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+
-+	mcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS;
-+	mcfg->plink_timeout = RTW_MESH_PEER_LINK_TIMEOUT;
-+
-+	mcfg->dot11MeshTTL = RTW_MESH_TTL;
-+	mcfg->element_ttl = RTW_MESH_DEFAULT_ELEMENT_TTL;
-+	mcfg->dot11MeshHWMPmaxPREQretries = RTW_MESH_MAX_PREQ_RETRIES;
-+	mcfg->path_refresh_time = RTW_MESH_PATH_REFRESH_TIME;
-+	mcfg->min_discovery_timeout = RTW_MESH_MIN_DISCOVERY_TIMEOUT;
-+	mcfg->dot11MeshHWMPactivePathTimeout = RTW_MESH_PATH_TIMEOUT;
-+	mcfg->dot11MeshHWMPpreqMinInterval = RTW_MESH_PREQ_MIN_INT;
-+	mcfg->dot11MeshHWMPperrMinInterval = RTW_MESH_PERR_MIN_INT;
-+	mcfg->dot11MeshHWMPnetDiameterTraversalTime = RTW_MESH_DIAM_TRAVERSAL_TIME;
-+	mcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_ROOTMODE_NO_ROOT;
-+	mcfg->dot11MeshHWMPRannInterval = RTW_MESH_RANN_INTERVAL;
-+	mcfg->dot11MeshGateAnnouncementProtocol = _FALSE;
-+	mcfg->dot11MeshForwarding = _TRUE;
-+	mcfg->rssi_threshold = 0;
-+	mcfg->dot11MeshHWMPactivePathToRootTimeout = RTW_MESH_PATH_TO_ROOT_TIMEOUT;
-+	mcfg->dot11MeshHWMProotInterval = RTW_MESH_ROOT_INTERVAL;
-+	mcfg->dot11MeshHWMPconfirmationInterval = RTW_MESH_ROOT_CONFIRMATION_INTERVAL;
-+	mcfg->path_gate_timeout_factor = 3;
-+	rtw_mesh_cfg_init_peer_sel_policy(mcfg);
-+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
-+	mcfg->sane_metric_delta = RTW_MESH_SANE_METRIC_DELTA;
-+	mcfg->max_root_add_chk_cnt = RTW_MESH_MAX_ROOT_ADD_CHK_CNT;
-+#endif
-+
-+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+	mcfg->b2u_flags_msrc = regsty->msrc_b2u_flags;
-+	mcfg->b2u_flags_mfwd = regsty->mfwd_b2u_flags;
-+#endif
-+}
-+
-+void rtw_mesh_cfg_init_max_peer_links(_adapter *adapter, u8 stack_conf)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+
-+	mcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS;
-+
-+	if (mcfg->max_peer_links > stack_conf)
-+		mcfg->max_peer_links = stack_conf;
-+}
-+
-+void rtw_mesh_cfg_init_plink_timeout(_adapter *adapter, u32 stack_conf)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+
-+	mcfg->plink_timeout = stack_conf;
-+}
-+
-+void rtw_mesh_init_mesh_info(_adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+
-+	_rtw_memset(minfo, 0, sizeof(struct rtw_mesh_info));
-+
-+	rtw_mesh_plink_ctl_init(adapter);
-+	
-+	minfo->last_preq = rtw_get_current_time();
-+	/* minfo->last_sn_update = rtw_get_current_time(); */
-+	minfo->next_perr = rtw_get_current_time();
-+	
-+	ATOMIC_SET(&minfo->mpaths, 0);
-+	rtw_mesh_pathtbl_init(adapter);
-+
-+	_rtw_init_queue(&minfo->mpath_tx_queue);
-+	tasklet_init(&minfo->mpath_tx_tasklet
-+		, (void(*)(unsigned long))mpath_tx_tasklet_hdl
-+		, (unsigned long)adapter);
-+
-+	rtw_mrc_init(adapter);
-+
-+	_rtw_init_listhead(&minfo->preq_queue.list);
-+	_rtw_spinlock_init(&minfo->mesh_preq_queue_lock);
-+	
-+	rtw_init_timer(&adapter->mesh_path_timer, adapter, rtw_ieee80211_mesh_path_timer, adapter);
-+	rtw_init_timer(&adapter->mesh_path_root_timer, adapter, rtw_ieee80211_mesh_path_root_timer, adapter);
-+	rtw_init_timer(&adapter->mesh_atlm_param_req_timer, adapter, rtw_mesh_atlm_param_req_timer, adapter);
-+	_init_workitem(&adapter->mesh_work, rtw_mesh_work_hdl, NULL);
-+}
-+
-+void rtw_mesh_deinit_mesh_info(_adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+
-+	tasklet_kill(&minfo->mpath_tx_tasklet);
-+	rtw_mpath_tx_queue_flush(adapter);
-+	_rtw_deinit_queue(&adapter->mesh_info.mpath_tx_queue);
-+
-+	rtw_mrc_free(adapter);
-+
-+	rtw_mesh_pathtbl_unregister(adapter);
-+
-+	rtw_mesh_plink_ctl_deinit(adapter);
-+
-+	_cancel_workitem_sync(&adapter->mesh_work);
-+	_cancel_timer_ex(&adapter->mesh_path_timer);
-+	_cancel_timer_ex(&adapter->mesh_path_root_timer);
-+	_cancel_timer_ex(&adapter->mesh_atlm_param_req_timer);
-+}
-+
-+/**
-+ * rtw_mesh_nexthop_resolve - lookup next hop; conditionally start path discovery
-+ *
-+ * @skb: 802.11 frame to be sent
-+ * @sdata: network subif the frame will be sent through
-+ *
-+ * Lookup next hop for given skb and start path discovery if no
-+ * forwarding information is found.
-+ *
-+ * Returns: 0 if the next hop was found and -ENOENT if the frame was queued.
-+ * skb is freeed here if no mpath could be allocated.
-+ */
-+int rtw_mesh_nexthop_resolve(_adapter *adapter,
-+			struct xmit_frame *xframe)
-+{
-+	struct pkt_attrib *attrib = &xframe->attrib;
-+	struct rtw_mesh_path *mpath;
-+	struct xmit_frame *xframe_to_free = NULL;
-+	u8 *target_addr = attrib->mda;
-+	int err = 0;
-+	int ret = _SUCCESS;
-+
-+	rtw_rcu_read_lock();
-+	err = rtw_mesh_nexthop_lookup(adapter, target_addr, attrib->msa, attrib->ra);
-+	if (!err)
-+		goto endlookup;
-+
-+	/* no nexthop found, start resolving */
-+	mpath = rtw_mesh_path_lookup(adapter, target_addr);
-+	if (!mpath) {
-+		mpath = rtw_mesh_path_add(adapter, target_addr);
-+		if (IS_ERR(mpath)) {
-+			xframe->pkt = NULL; /* free pkt outside */
-+			rtw_mesh_path_discard_frame(adapter, xframe);
-+			err = PTR_ERR(mpath);
-+			ret = _FAIL;
-+			goto endlookup;
-+		}
-+	}
-+
-+	if (!(mpath->flags & RTW_MESH_PATH_RESOLVING))
-+		rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START);
-+
-+	enter_critical_bh(&mpath->frame_queue.lock);
-+
-+	if (mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) {
-+		xframe_to_free = LIST_CONTAINOR(get_next(get_list_head(&mpath->frame_queue)), struct xmit_frame, list);
-+		rtw_list_delete(&(xframe_to_free->list));
-+		mpath->frame_queue_len--;
-+	}
-+
-+	rtw_list_insert_tail(&xframe->list, get_list_head(&mpath->frame_queue));
-+	mpath->frame_queue_len++;
-+
-+	exit_critical_bh(&mpath->frame_queue.lock);
-+
-+	ret = RTW_RA_RESOLVING;
-+	if (xframe_to_free)
-+		rtw_mesh_path_discard_frame(adapter, xframe_to_free);
-+
-+endlookup:
-+	rtw_rcu_read_unlock();
-+	return ret;
-+}
-+
-+/**
-+ * rtw_mesh_nexthop_lookup - put the appropriate next hop on a mesh frame. Calling
-+ * this function is considered "using" the associated mpath, so preempt a path
-+ * refresh if this mpath expires soon.
-+ *
-+ * @skb: 802.11 frame to be sent
-+ * @sdata: network subif the frame will be sent through
-+ *
-+ * Returns: 0 if the next hop was found. Nonzero otherwise.
-+ */
-+int rtw_mesh_nexthop_lookup(_adapter *adapter,
-+	const u8 *mda, const u8 *msa, u8 *ra)
-+{
-+	struct rtw_mesh_path *mpath;
-+	struct sta_info *next_hop;
-+	const u8 *target_addr = mda;
-+	int err = -ENOENT;
-+	struct registry_priv  *registry_par = &adapter->registrypriv;
-+	u8 peer_alive_based_preq = registry_par->peer_alive_based_preq;
-+	BOOLEAN nexthop_alive = _TRUE;
-+
-+	rtw_rcu_read_lock();
-+	mpath = rtw_mesh_path_lookup(adapter, target_addr);
-+
-+	if (!mpath || !(mpath->flags & RTW_MESH_PATH_ACTIVE))
-+		goto endlookup;
-+
-+	next_hop = rtw_rcu_dereference(mpath->next_hop);
-+	if (next_hop) {
-+		_rtw_memcpy(ra, next_hop->cmn.mac_addr, ETH_ALEN);
-+		err = 0;
-+	}
-+
-+	if (peer_alive_based_preq && next_hop)
-+		nexthop_alive = next_hop->alive;
-+
-+	if (_rtw_memcmp(adapter_mac_addr(adapter), msa, ETH_ALEN) == _TRUE &&
-+	    !(mpath->flags & RTW_MESH_PATH_RESOLVING) &&
-+	    !(mpath->flags & RTW_MESH_PATH_FIXED)) {
-+		u8 flags = RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH;
-+
-+		if (peer_alive_based_preq && nexthop_alive == _FALSE) {
-+			flags |= RTW_PREQ_Q_F_BCAST_PREQ;
-+			rtw_mesh_queue_preq(mpath, flags);
-+		} else if (rtw_time_after(rtw_get_current_time(),
-+			mpath->exp_time -
-+			rtw_ms_to_systime(adapter->mesh_cfg.path_refresh_time))) {
-+			rtw_mesh_queue_preq(mpath, flags);
-+		}
-+	/* Avoid keeping trying unicast PREQ toward root,
-+	   when next_hop leaves */
-+	} else if (peer_alive_based_preq &&
-+		   _rtw_memcmp(adapter_mac_addr(adapter), msa, ETH_ALEN) == _TRUE &&
-+		   (mpath->flags & RTW_MESH_PATH_RESOLVING) &&
-+		   !(mpath->flags & RTW_MESH_PATH_FIXED) &&
-+		   !(mpath->flags & RTW_MESH_PATH_BCAST_PREQ) &&
-+		   mpath->is_root && nexthop_alive == _FALSE) {
-+		enter_critical_bh(&mpath->state_lock);
-+		mpath->flags |= RTW_MESH_PATH_BCAST_PREQ;
-+		exit_critical_bh(&mpath->state_lock);
-+	}
-+
-+endlookup:
-+	rtw_rcu_read_unlock();
-+	return err;
-+}
-+
-+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+static bool rtw_mesh_data_bmc_to_uc(_adapter *adapter
-+	, const u8 *da, const u8 *sa, const u8 *mda, const u8 *msa
-+	, u8 ae_need, const u8 *ori_ta, u8 mfwd_ttl
-+	, u16 os_qid, _list *b2u_list, u8 *b2u_num, u32 *b2u_mseq)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct xmit_priv *xmitpriv = &adapter->xmitpriv;
-+	_irqL irqL;
-+	_list *head, *list;
-+	struct sta_info *sta;
-+	char b2u_sta_id[NUM_STA];
-+	u8 b2u_sta_num = 0;
-+	bool bmc_need = _FALSE;
-+	int i;
-+
-+	_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+	head = &stapriv->asoc_list;
-+	list = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
-+		int stainfo_offset;
-+
-+		sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
-+		list = get_next(list);
-+	
-+		stainfo_offset = rtw_stainfo_offset(stapriv, sta);
-+		if (stainfo_offset_valid(stainfo_offset))
-+			b2u_sta_id[b2u_sta_num++] = stainfo_offset;
-+	}
-+	_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+
-+	if (!b2u_sta_num)
-+		goto exit;
-+
-+	for (i = 0; i < b2u_sta_num; i++) {
-+		struct xmit_frame *b2uframe;
-+		struct pkt_attrib *attrib;
-+
-+		sta = rtw_get_stainfo_by_offset(stapriv, b2u_sta_id[i]);
-+		if (!(sta->state & WIFI_ASOC_STATE)
-+			|| _rtw_memcmp(sta->cmn.mac_addr, msa, ETH_ALEN) == _TRUE
-+			|| (ori_ta && _rtw_memcmp(sta->cmn.mac_addr, ori_ta, ETH_ALEN) == _TRUE)
-+			|| is_broadcast_mac_addr(sta->cmn.mac_addr)
-+			|| is_zero_mac_addr(sta->cmn.mac_addr))
-+			continue;
-+
-+		b2uframe = rtw_alloc_xmitframe(xmitpriv, os_qid);
-+		if (!b2uframe) {
-+			bmc_need = _TRUE;
-+			break;
-+		}
-+
-+		if ((*b2u_num)++ == 0 && !ori_ta) {
-+			*b2u_mseq = (cpu_to_le32(adapter->mesh_info.mesh_seqnum));
-+			adapter->mesh_info.mesh_seqnum++;
-+		}
-+
-+		attrib = &b2uframe->attrib;
-+
-+		attrib->mb2u = 1;
-+		attrib->mseq = *b2u_mseq;
-+		attrib->mfwd_ttl = ori_ta ? mfwd_ttl : 0;
-+		_rtw_memcpy(attrib->ra, sta->cmn.mac_addr, ETH_ALEN);
-+		_rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
-+		_rtw_memcpy(attrib->mda, mda, ETH_ALEN);
-+		_rtw_memcpy(attrib->msa, msa, ETH_ALEN);
-+		_rtw_memcpy(attrib->dst, da, ETH_ALEN);
-+		_rtw_memcpy(attrib->src, sa, ETH_ALEN);
-+		attrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;
-+
-+		rtw_list_insert_tail(&b2uframe->list, b2u_list);
-+	}
-+
-+exit:
-+	return bmc_need;
-+}
-+
-+void dump_mesh_b2u_flags(void *sel, _adapter *adapter)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+
-+	RTW_PRINT_SEL(sel, "%4s %4s\n", "msrc", "mfwd");
-+	RTW_PRINT_SEL(sel, "0x%02x 0x%02x\n", mcfg->b2u_flags_msrc, mcfg->b2u_flags_mfwd);
-+}
-+#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */
-+
-+int rtw_mesh_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list)
-+{
-+	struct pkt_file pktfile;
-+	struct ethhdr etherhdr;
-+	struct pkt_attrib *attrib;
-+	struct rtw_mesh_path *mpath = NULL, *mppath = NULL;
-+	u8 is_da_mcast;
-+	u8 ae_need;
-+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+	bool bmc_need = _TRUE;
-+	u8 b2u_num = 0;
-+	u32 b2u_mseq = 0;
-+#endif
-+	int res = _SUCCESS;
-+
-+	_rtw_open_pktfile(pkt, &pktfile);
-+	if (_rtw_pktfile_read(&pktfile, (u8 *)&etherhdr, ETH_HLEN) != ETH_HLEN) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	
-+	xframe->pkt = pkt;
-+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+	_rtw_init_listhead(b2u_list);
-+#endif
-+
-+	is_da_mcast = IS_MCAST(etherhdr.h_dest);
-+	if (!is_da_mcast) {
-+		struct sta_info *next_hop; 
-+		bool mpp_lookup = 1;
-+	
-+		mpath = rtw_mesh_path_lookup(adapter, etherhdr.h_dest);
-+		if (mpath) {
-+			mpp_lookup = 0;
-+			next_hop = rtw_rcu_dereference(mpath->next_hop);
-+			if (!next_hop
-+				|| !(mpath->flags & (RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVING))
-+			) {
-+				/* mpath is not valid, search mppath */
-+				mpp_lookup = 1;
-+			}
-+		}
-+
-+		if (mpp_lookup) {
-+			mppath = rtw_mpp_path_lookup(adapter, etherhdr.h_dest);
-+			if (mppath)
-+				mppath->exp_time = rtw_get_current_time();
-+		}
-+
-+		if (mppath && mpath)
-+			rtw_mesh_path_del(adapter, mpath->dst);
-+
-+		ae_need = _rtw_memcmp(adapter_mac_addr(adapter), etherhdr.h_source, ETH_ALEN) == _FALSE
-+			|| (mppath && _rtw_memcmp(mppath->mpp, etherhdr.h_dest, ETH_ALEN) == _FALSE);
-+	} else {
-+		ae_need = _rtw_memcmp(adapter_mac_addr(adapter), etherhdr.h_source, ETH_ALEN) == _FALSE;
-+
-+		#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+		if (rtw_msrc_b2u_policy_chk(adapter->mesh_cfg.b2u_flags_msrc, etherhdr.h_dest)) {
-+			bmc_need = rtw_mesh_data_bmc_to_uc(adapter
-+				, etherhdr.h_dest, etherhdr.h_source
-+				, etherhdr.h_dest, adapter_mac_addr(adapter), ae_need, NULL, 0
-+				, os_qid, b2u_list, &b2u_num, &b2u_mseq);
-+			if (bmc_need == _FALSE) {
-+				res = RTW_BMC_NO_NEED;
-+				goto exit;
-+			}
-+		}
-+		#endif
-+	}
-+
-+	attrib = &xframe->attrib;
-+
-+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+	if (b2u_num) {
-+		attrib->mb2u = 1;
-+		attrib->mseq = b2u_mseq;
-+	} else
-+		attrib->mb2u = 0;
-+#endif
-+
-+	attrib->mfwd_ttl = 0;
-+	_rtw_memcpy(attrib->dst, etherhdr.h_dest, ETH_ALEN);
-+	_rtw_memcpy(attrib->src, etherhdr.h_source, ETH_ALEN);
-+	_rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
-+
-+	if (is_da_mcast) {
-+		attrib->mesh_frame_mode = ae_need ? MESH_BMCAST_PX_DATA : MESH_BMCAST_DATA;
-+		_rtw_memcpy(attrib->ra, attrib->dst, ETH_ALEN);
-+		_rtw_memcpy(attrib->msa, adapter_mac_addr(adapter), ETH_ALEN);
-+	} else {
-+		attrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;
-+		_rtw_memcpy(attrib->mda, (mppath && ae_need) ? mppath->mpp : attrib->dst, ETH_ALEN);
-+		_rtw_memcpy(attrib->msa, adapter_mac_addr(adapter), ETH_ALEN);
-+		/* RA needs to be resolved */
-+		res = rtw_mesh_nexthop_resolve(adapter, xframe);
-+	}
-+
-+exit:
-+	return res;
-+}
-+
-+s8 rtw_mesh_tx_set_whdr_mctrl_len(u8 mesh_frame_mode, struct pkt_attrib *attrib)
-+{
-+	u8 ret = 0;
-+	switch (mesh_frame_mode) {
-+	case MESH_UCAST_DATA:
-+		attrib->hdrlen = WLAN_HDR_A4_QOS_LEN;
-+		/* mesh flag + mesh TTL + Mesh SN. no ext addr. */
-+		attrib->meshctrl_len = 6;
-+		break;
-+	case MESH_BMCAST_DATA:
-+		attrib->hdrlen = WLAN_HDR_A3_QOS_LEN;
-+		/* mesh flag + mesh TTL + Mesh SN. no ext addr. */
-+		attrib->meshctrl_len = 6;
-+		break;
-+	case MESH_UCAST_PX_DATA:
-+		attrib->hdrlen = WLAN_HDR_A4_QOS_LEN;
-+		/* mesh flag + mesh TTL + Mesh SN + extaddr1 + extaddr2. */
-+		attrib->meshctrl_len = 18;
-+		break;
-+	case MESH_BMCAST_PX_DATA:
-+		attrib->hdrlen = WLAN_HDR_A3_QOS_LEN;
-+		/* mesh flag + mesh TTL + Mesh SN + extaddr1 */
-+		attrib->meshctrl_len = 12;
-+		break;
-+	default:
-+		RTW_WARN("Invalid mesh frame mode:%u\n", mesh_frame_mode);
-+		ret = -1;
-+		break;
-+	}				
-+
-+	return ret;
-+}
-+
-+void rtw_mesh_tx_build_mctrl(_adapter *adapter, struct pkt_attrib *attrib, u8 *buf)
-+{
-+	struct rtw_ieee80211s_hdr *mctrl = (struct rtw_ieee80211s_hdr *)buf;
-+
-+	_rtw_memset(mctrl, 0, XATTRIB_GET_MCTRL_LEN(attrib));
-+
-+	if (attrib->mfwd_ttl
-+		#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+		|| attrib->mb2u
-+		#endif
-+	) {
-+		#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+		if (!attrib->mfwd_ttl)
-+			mctrl->ttl = adapter->mesh_cfg.dot11MeshTTL;
-+		else
-+		#endif
-+			mctrl->ttl = attrib->mfwd_ttl;
-+
-+		mctrl->seqnum = (cpu_to_le32(attrib->mseq));
-+	} else {
-+		mctrl->ttl = adapter->mesh_cfg.dot11MeshTTL;
-+		mctrl->seqnum = (cpu_to_le32(adapter->mesh_info.mesh_seqnum));
-+		adapter->mesh_info.mesh_seqnum++;
-+	}
-+
-+	switch (attrib->mesh_frame_mode){
-+	case MESH_UCAST_DATA:
-+	case MESH_BMCAST_DATA:
-+		break;
-+	case MESH_UCAST_PX_DATA:
-+		mctrl->flags |= MESH_FLAGS_AE_A5_A6;
-+		_rtw_memcpy(mctrl->eaddr1, attrib->dst, ETH_ALEN);
-+		_rtw_memcpy(mctrl->eaddr2, attrib->src, ETH_ALEN);
-+		break;
-+	case MESH_BMCAST_PX_DATA:
-+		mctrl->flags |= MESH_FLAGS_AE_A4;
-+		_rtw_memcpy(mctrl->eaddr1, attrib->src, ETH_ALEN);
-+		break;
-+	case MESH_MHOP_UCAST_ACT:
-+		/* TBD */
-+		break;
-+	case MESH_MHOP_BMCAST_ACT:
-+		/* TBD */
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+u8 rtw_mesh_tx_build_whdr(_adapter *adapter, struct pkt_attrib *attrib
-+	, u16 *fctrl, struct rtw_ieee80211_hdr *whdr)
-+{
-+	switch (attrib->mesh_frame_mode) {
-+	case MESH_UCAST_DATA:		/* 1, 1, RA, TA, mDA(=DA),	mSA(=SA) */
-+	case MESH_UCAST_PX_DATA:	/* 1, 1, RA, TA, mDA,		mSA,		[DA, SA] */
-+		SetToDs(fctrl);
-+		SetFrDs(fctrl);
-+		_rtw_memcpy(whdr->addr1, attrib->ra, ETH_ALEN);
-+		_rtw_memcpy(whdr->addr2, attrib->ta, ETH_ALEN);
-+		_rtw_memcpy(whdr->addr3, attrib->mda, ETH_ALEN);
-+		_rtw_memcpy(whdr->addr4, attrib->msa, ETH_ALEN);
-+		break;
-+	case MESH_BMCAST_DATA:		/* 0, 1, RA(DA), TA, mSA(SA) */
-+	case MESH_BMCAST_PX_DATA:	/* 0, 1, RA(DA), TA, mSA,		[SA] */
-+		SetFrDs(fctrl);
-+		_rtw_memcpy(whdr->addr1, attrib->ra, ETH_ALEN);
-+		_rtw_memcpy(whdr->addr2, attrib->ta, ETH_ALEN);
-+		_rtw_memcpy(whdr->addr3, attrib->msa, ETH_ALEN);
-+		break;
-+	case MESH_MHOP_UCAST_ACT:
-+		/* TBD */
-+		RTW_INFO("MESH_MHOP_UCAST_ACT\n");
-+		break;
-+	case MESH_MHOP_BMCAST_ACT:
-+		/* TBD */
-+		RTW_INFO("MESH_MHOP_BMCAST_ACT\n");
-+		break;
-+	default:
-+		RTW_WARN("Invalid mesh frame mode\n");
-+		break;
-+	}
-+	
-+	return 0;
-+}
-+
-+int rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
-+	u8 *whdr = get_recvframe_data(rframe);
-+	u8 is_ra_bmc = 0;
-+	u8 a4_shift = 0;
-+	u8 ps;
-+	u8 *qc;
-+	u8 mps_mode = RTW_MESH_PS_UNKNOWN;
-+	sint ret = _FAIL;
-+
-+	if (!(MLME_STATE(adapter) & WIFI_ASOC_STATE))
-+		goto exit;
-+
-+	if (!rattrib->qos)
-+		goto exit;
-+
-+	switch (rattrib->to_fr_ds) {
-+	case 2:
-+		if (!IS_MCAST(GetAddr1Ptr(whdr)))
-+			goto exit;
-+		*sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr));
-+		if (*sta == NULL) {
-+			ret = _SUCCESS; /* return _SUCCESS to drop at sta checking */
-+			goto exit;
-+		}
-+		_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->mda, GetAddr1Ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->msa, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
-+		_rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->src, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */
-+		_rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN);
-+		is_ra_bmc = 1;
-+		break;
-+	case 3:
-+		if (IS_MCAST(GetAddr1Ptr(whdr)))
-+			goto exit;
-+		*sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr));
-+		if (*sta == NULL) {
-+			ret = _SUCCESS; /* return _SUCCESS to drop at sta checking */
-+			goto exit;
-+		}
-+		_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->mda, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
-+		_rtw_memcpy(rattrib->msa, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
-+		_rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */
-+		_rtw_memcpy(rattrib->src, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */
-+		_rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN);
-+		a4_shift = ETH_ALEN;
-+		break;
-+	default:
-+		goto exit;
-+	}
-+
-+	qc = whdr + WLAN_HDR_A3_LEN + a4_shift;
-+	ps = GetPwrMgt(whdr);
-+	mps_mode = ps ? (is_ra_bmc || (get_mps_lv(qc)) ? RTW_MESH_PS_DSLEEP : RTW_MESH_PS_LSLEEP) : RTW_MESH_PS_ACTIVE;
-+
-+	if (ps) {
-+		if (!((*sta)->state & WIFI_SLEEP_STATE))
-+			stop_sta_xmit(adapter, *sta);
-+	} else {
-+		if ((*sta)->state & WIFI_SLEEP_STATE)
-+			wakeup_sta_to_xmit(adapter, *sta);
-+	}
-+
-+	if (is_ra_bmc)
-+		(*sta)->nonpeer_mps = mps_mode;
-+	else {
-+		(*sta)->peer_mps = mps_mode;
-+		if (mps_mode != RTW_MESH_PS_ACTIVE && (*sta)->nonpeer_mps == RTW_MESH_PS_ACTIVE)
-+			(*sta)->nonpeer_mps = RTW_MESH_PS_DSLEEP;
-+	}
-+
-+	if (get_frame_sub_type(whdr) & BIT(6)) {
-+		/* No data, will not indicate to upper layer, temporily count it here */
-+		count_rx_stats(adapter, rframe, *sta);
-+		ret = RTW_RX_HANDLED;
-+		goto exit;
-+	}
-+
-+	rattrib->mesh_ctrl_present = get_mctrl_present(qc) ? 1 : 0;
-+	if (!rattrib->mesh_ctrl_present)
-+		goto exit;
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+int rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe
-+	, const struct rtw_ieee80211s_hdr *mctrl, const u8 *mda, const u8 *msa
-+	, u8 *mctrl_len
-+	, const u8 **da, const u8 **sa)
-+{
-+	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
-+	u8 mlen;
-+	u8 ae;
-+	int ret = _SUCCESS;
-+
-+	ae = mctrl->flags & MESH_FLAGS_AE;
-+	mlen = ae_to_mesh_ctrl_len[ae];
-+	switch (rattrib->to_fr_ds) {
-+	case 2:
-+		*da = mda;
-+		if (ae == MESH_FLAGS_AE_A4)
-+			*sa = mctrl->eaddr1;
-+		else if (ae == 0)
-+			*sa = msa;
-+		else
-+			ret = _FAIL;
-+		break;
-+	case 3:
-+		if (ae == MESH_FLAGS_AE_A5_A6) {
-+			*da = mctrl->eaddr1;
-+			*sa = mctrl->eaddr2;
-+		} else if (ae == 0) {
-+			*da = mda;
-+			*sa = msa;
-+		} else
-+			ret = _FAIL;
-+		break;
-+	default:
-+		ret = _FAIL;
-+	}
-+
-+	if (ret == _FAIL) {
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" invalid tfDS:%u AE:%u combination ra="MAC_FMT" ta="MAC_FMT"\n"
-+			, FUNC_ADPT_ARG(adapter), rattrib->to_fr_ds, ae, MAC_ARG(rattrib->ra), MAC_ARG(rattrib->ta));
-+		#endif
-+		*mctrl_len = 0;
-+	} else
-+		*mctrl_len = mlen;
-+
-+	return ret;	
-+}
-+
-+inline int rtw_mesh_rx_validate_mctrl_non_amsdu(_adapter *adapter, union recv_frame *rframe)
-+{
-+	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
-+	const u8 *da, *sa;
-+	int ret;
-+
-+	ret = rtw_mesh_rx_data_validate_mctrl(adapter, rframe
-+			, (struct rtw_ieee80211s_hdr *)(get_recvframe_data(rframe) + rattrib->hdrlen + rattrib->iv_len)
-+			, rattrib->mda, rattrib->msa
-+			, &rattrib->mesh_ctrl_len
-+			, &da, &sa);
-+
-+	if (ret == _SUCCESS) {
-+		_rtw_memcpy(rattrib->dst, da, ETH_ALEN);
-+		_rtw_memcpy(rattrib->src, sa, ETH_ALEN);
-+	}
-+
-+	return ret;
-+}
-+
-+/**
-+ * rtw_mesh_rx_nexthop_resolve - lookup next hop; conditionally start path discovery
-+ *
-+ * @skb: 802.11 frame to be sent
-+ * @sdata: network subif the frame will be sent through
-+ *
-+ * Lookup next hop for given skb and start path discovery if no
-+ * forwarding information is found.
-+ *
-+ * Returns: 0 if the next hop was found and -ENOENT if the frame was queued.
-+ * skb is freeed here if no mpath could be allocated.
-+ */
-+static int rtw_mesh_rx_nexthop_resolve(_adapter *adapter,
-+	const u8 *mda, const u8 *msa, u8 *ra)
-+{
-+	struct rtw_mesh_path *mpath;
-+	struct xmit_frame *xframe_to_free = NULL;
-+	int err = 0;
-+	int ret = _SUCCESS;
-+
-+	rtw_rcu_read_lock();
-+	err = rtw_mesh_nexthop_lookup(adapter, mda, msa, ra);
-+	if (!err)
-+		goto endlookup;
-+
-+	/* no nexthop found, start resolving */
-+	mpath = rtw_mesh_path_lookup(adapter, mda);
-+	if (!mpath) {
-+		mpath = rtw_mesh_path_add(adapter, mda);
-+		if (IS_ERR(mpath)) {
-+			err = PTR_ERR(mpath);
-+			ret = _FAIL;
-+			goto endlookup;
-+		}
-+	}
-+
-+	if (!(mpath->flags & RTW_MESH_PATH_RESOLVING))
-+		rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START);
-+
-+	ret = _FAIL;
-+
-+endlookup:
-+	rtw_rcu_read_unlock();
-+	return ret;
-+}
-+
-+#define RTW_MESH_DECACHE_BMC 1
-+#define RTW_MESH_DECACHE_UC 0
-+
-+#define RTW_MESH_FORWARD_MDA_SELF_COND 0
-+#define DBG_RTW_MESH_FORWARD_MDA_SELF_COND 0
-+int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe
-+	, const u8 *mda, const u8 *msa
-+	, const u8 *da, const u8 *sa
-+	, struct rtw_ieee80211s_hdr *mctrl
-+	, u8 *msdu, enum rtw_rx_llc_hdl llc_hdl
-+	, struct xmit_frame **fwd_frame, _list *b2u_list)
-+{
-+	_adapter *adapter = rframe->u.hdr.adapter;
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
-+	struct rtw_mesh_path *mppath;
-+	u8 is_mda_bmc = IS_MCAST(mda); 
-+	u8 is_mda_self = !is_mda_bmc && _rtw_memcmp(mda, adapter_mac_addr(adapter), ETH_ALEN);
-+	u16 os_qid;
-+	struct xmit_frame *xframe;
-+	struct pkt_attrib *xattrib;
-+	u8 fwd_ra[ETH_ALEN] = {0};
-+	u8 fwd_mpp[ETH_ALEN] = {0}; /* forward to other gate */
-+	u32 fwd_mseq;
-+	int act = 0;
-+	u8 ae_need;
-+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+	bool bmc_need = _TRUE;
-+	u8 b2u_num = 0;
-+#endif
-+
-+	/* fwd info lifetime update */
-+	#if 0
-+	if (!is_mda_self)
-+		mDA(A3) fwinfo.lifetime
-+	mSA(A4) fwinfo.lifetime
-+	Precursor-to-mDA(A2) fwinfo.lifetime
-+	#endif
-+
-+	/* update/create pxoxy info for SA, mSA */
-+	if ((mctrl->flags & MESH_FLAGS_AE)
-+		&& sa != msa && _rtw_memcmp(sa, msa, ETH_ALEN) == _FALSE
-+	) {
-+		const u8 *proxied_addr = sa;
-+		const u8 *mpp_addr = msa;
-+
-+		rtw_rcu_read_lock();
-+		mppath = rtw_mpp_path_lookup(adapter, proxied_addr);
-+		if (!mppath)
-+			rtw_mpp_path_add(adapter, proxied_addr, mpp_addr);
-+		else {
-+			enter_critical_bh(&mppath->state_lock);
-+			if (_rtw_memcmp(mppath->mpp, mpp_addr, ETH_ALEN) == _FALSE)
-+				_rtw_memcpy(mppath->mpp, mpp_addr, ETH_ALEN);
-+			mppath->exp_time = rtw_get_current_time();
-+			exit_critical_bh(&mppath->state_lock);
-+		}
-+		rtw_rcu_read_unlock();
-+	}
-+
-+	/* mSA is self, need no further process */
-+	if (_rtw_memcmp(msa, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
-+		goto exit;
-+
-+	fwd_mseq = le32_to_cpu(mctrl->seqnum);
-+
-+	/* check duplicate MSDU from mSA */
-+	if (((RTW_MESH_DECACHE_BMC && is_mda_bmc)
-+			|| (RTW_MESH_DECACHE_UC && !is_mda_bmc))
-+		&& rtw_mesh_decache(adapter, msa, fwd_mseq)
-+	) {
-+		minfo->mshstats.dropped_frames_duplicate++;
-+		goto exit;
-+	}
-+
-+	if (is_mda_bmc) {
-+		/* mDA is bmc addr */
-+		act |= RTW_RX_MSDU_ACT_INDICATE;
-+		if (!mcfg->dot11MeshForwarding)
-+			goto exit;
-+		goto fwd_chk;
-+
-+	} else if (!is_mda_self) {
-+		/* mDA is unicast but not self */
-+		if (!mcfg->dot11MeshForwarding) {
-+			rtw_mesh_path_error_tx(adapter
-+				, adapter->mesh_cfg.element_ttl
-+				, mda, 0
-+				, WLAN_REASON_MESH_PATH_NOFORWARD
-+				, rattrib->ta
-+			);
-+			#ifdef DBG_RX_DROP_FRAME
-+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" mDA("MAC_FMT") not self, !dot11MeshForwarding\n"
-+				, FUNC_ADPT_ARG(adapter), MAC_ARG(mda));
-+			#endif
-+			goto exit;
-+		}
-+
-+		if (rtw_mesh_rx_nexthop_resolve(adapter, mda, msa, fwd_ra) != _SUCCESS) {
-+			/* mDA is unknown */
-+			rtw_mesh_path_error_tx(adapter
-+				, adapter->mesh_cfg.element_ttl
-+				, mda, 0
-+				, WLAN_REASON_MESH_PATH_NOFORWARD
-+				, rattrib->ta
-+			);
-+			#ifdef DBG_RX_DROP_FRAME
-+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" mDA("MAC_FMT") unknown\n"
-+				, FUNC_ADPT_ARG(adapter), MAC_ARG(mda));
-+			#endif
-+			minfo->mshstats.dropped_frames_no_route++;
-+			goto exit;
-+
-+		} else {
-+			/* mDA is known in fwd info */
-+			#if 0
-+			if	(TA is not in precursors)
-+				goto exit;
-+			#endif
-+			goto fwd_chk;
-+		}
-+
-+	} else {
-+		/* mDA is self */
-+		#if RTW_MESH_FORWARD_MDA_SELF_COND
-+		if (da == mda
-+			|| _rtw_memcmp(da, adapter_mac_addr(adapter), ETH_ALEN)
-+		) {
-+			/* DA is self, indicate */
-+			act |= RTW_RX_MSDU_ACT_INDICATE;
-+			goto exit;
-+		}
-+
-+		if (rtw_get_iface_by_macddr(adapter, da)) {
-+			/* DA is buddy, indicate */
-+			act |= RTW_RX_MSDU_ACT_INDICATE;
-+			#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
-+			RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") is buddy("ADPT_FMT")\n"
-+				, FUNC_ADPT_ARG(adapter), MAC_ARG(da), ADPT_ARG(rtw_get_iface_by_macddr(adapter, da)));
-+			#endif
-+			goto exit;
-+		}
-+
-+		/* DA is not self or buddy */
-+		if (rtw_mesh_nexthop_lookup(adapter, da, msa, fwd_ra) == 0) {
-+			/* DA is known in fwd info */
-+			if (!mcfg->dot11MeshForwarding) {
-+				/* path error to? */
-+				#if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND
-+				RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") not self, !dot11MeshForwarding\n"
-+					, FUNC_ADPT_ARG(adapter), MAC_ARG(da));
-+				#endif
-+				goto exit;
-+			}
-+			mda = da;
-+			#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
-+			RTW_INFO(FUNC_ADPT_FMT" fwd to DA("MAC_FMT"), fwd_RA("MAC_FMT")\n"
-+				, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(fwd_ra));
-+			#endif
-+			goto fwd_chk;
-+		}
-+
-+		rtw_rcu_read_lock();
-+		mppath = rtw_mpp_path_lookup(adapter, da);
-+		if (mppath) {
-+			if (_rtw_memcmp(mppath->mpp, adapter_mac_addr(adapter), ETH_ALEN) == _FALSE) {
-+				/* DA is proxied by others */
-+				if (!mcfg->dot11MeshForwarding) {
-+					/* path error to? */
-+					#if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND
-+					RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by ("MAC_FMT"), !dot11MeshForwarding\n"
-+						, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp));
-+					#endif
-+					rtw_rcu_read_unlock();
-+					goto exit;
-+				}
-+				_rtw_memcpy(fwd_mpp, mppath->mpp, ETH_ALEN);
-+				mda = fwd_mpp;
-+				msa = adapter_mac_addr(adapter);
-+				rtw_rcu_read_unlock();
-+
-+				/* resolve RA */
-+				if (rtw_mesh_nexthop_lookup(adapter, mda, msa, fwd_ra) != 0) {
-+					minfo->mshstats.dropped_frames_no_route++;
-+					#if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND
-+					RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by ("MAC_FMT"), RA resolve fail\n"
-+						, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp));
-+					#endif
-+					goto exit;
-+				}
-+				#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
-+				RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by ("MAC_FMT"), fwd_RA("MAC_FMT")\n"
-+					, FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp), MAC_ARG(fwd_ra));
-+				#endif
-+				goto fwd_chk; /*  forward to other gate */
-+			} else {
-+				#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
-+				RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by self\n"
-+					, FUNC_ADPT_ARG(adapter), MAC_ARG(da));
-+				#endif
-+			}
-+		}
-+		rtw_rcu_read_unlock();
-+
-+		if (!mppath) {
-+			#if DBG_RTW_MESH_FORWARD_MDA_SELF_COND
-+			RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") unknown\n"
-+				, FUNC_ADPT_ARG(adapter), MAC_ARG(da));
-+			#endif
-+			/* DA is unknown */
-+			#if 0 /* TODO: flags with AE bit */
-+			rtw_mesh_path_error_tx(adapter
-+				, adapter->mesh_cfg.element_ttl
-+				, mda, adapter->mesh_info.last_sn_update
-+				, WLAN_REASON_MESH_PATH_NOPROXY
-+				, msa
-+			);
-+			#endif
-+		}
-+
-+		/*
-+		* indicate to DS for both cases:
-+		* 1.) DA is proxied by self
-+		* 2.) DA is unknown
-+		*/
-+		#endif /* RTW_MESH_FORWARD_MDA_SELF_COND */
-+		act |= RTW_RX_MSDU_ACT_INDICATE;
-+		goto exit;
-+	}
-+
-+fwd_chk:
-+
-+	if (adapter->stapriv.asoc_list_cnt <= 1)
-+		goto exit;
-+
-+	if (mctrl->ttl == 1) {
-+		minfo->mshstats.dropped_frames_ttl++;
-+		if (!act) {
-+			#ifdef DBG_RX_DROP_FRAME
-+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" ttl reaches 0, not forwarding\n"
-+				, FUNC_ADPT_ARG(adapter));
-+			#endif
-+		}
-+		goto exit;
-+	}
-+
-+	os_qid = rtw_os_recv_select_queue(msdu, llc_hdl);
-+
-+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+	_rtw_init_listhead(b2u_list);
-+#endif
-+
-+	ae_need = _rtw_memcmp(da , mda, ETH_ALEN) == _FALSE
-+		|| _rtw_memcmp(sa , msa, ETH_ALEN) == _FALSE;
-+
-+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+	if (is_mda_bmc
-+		&& rtw_mfwd_b2u_policy_chk(mcfg->b2u_flags_mfwd, mda, rattrib->to_fr_ds == 3)
-+	) {
-+		bmc_need = rtw_mesh_data_bmc_to_uc(adapter
-+			, da, sa, mda, msa, ae_need, rframe->u.hdr.psta->cmn.mac_addr, mctrl->ttl - 1
-+			, os_qid, b2u_list, &b2u_num, &fwd_mseq);
-+	}
-+
-+	if (bmc_need == _TRUE)
-+#endif
-+	{
-+		xframe = rtw_alloc_xmitframe(&adapter->xmitpriv, os_qid);
-+		if (!xframe) {
-+			#ifdef DBG_TX_DROP_FRAME
-+			RTW_INFO("DBG_TX_DROP_FRAME "FUNC_ADPT_FMT" rtw_alloc_xmitframe fail\n"
-+				, FUNC_ADPT_ARG(adapter));
-+			#endif
-+			goto exit;
-+		}
-+
-+		xattrib = &xframe->attrib;
-+
-+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+		if (b2u_num)
-+			xattrib->mb2u = 1;
-+		else
-+			xattrib->mb2u = 0;
-+#endif
-+		xattrib->mfwd_ttl = mctrl->ttl - 1;
-+		xattrib->mseq = fwd_mseq;
-+		_rtw_memcpy(xattrib->dst, da, ETH_ALEN);
-+		_rtw_memcpy(xattrib->src, sa, ETH_ALEN);
-+		_rtw_memcpy(xattrib->mda, mda, ETH_ALEN);
-+		_rtw_memcpy(xattrib->msa, msa, ETH_ALEN);
-+		_rtw_memcpy(xattrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
-+
-+		if (is_mda_bmc) {
-+			xattrib->mesh_frame_mode = ae_need ? MESH_BMCAST_PX_DATA : MESH_BMCAST_DATA;
-+			_rtw_memcpy(xattrib->ra, mda, ETH_ALEN);
-+		} else {
-+			xattrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;
-+			_rtw_memcpy(xattrib->ra, fwd_ra, ETH_ALEN);
-+		}
-+
-+		*fwd_frame = xframe;
-+	}
-+
-+	act |= RTW_RX_MSDU_ACT_FORWARD;
-+	if (is_mda_bmc)
-+		minfo->mshstats.fwded_mcast++;
-+	else
-+		minfo->mshstats.fwded_unicast++;
-+	minfo->mshstats.fwded_frames++;
-+
-+exit:
-+	return act;
-+}
-+
-+void dump_mesh_stats(void *sel, _adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct rtw_mesh_stats *stats = &minfo->mshstats;
-+
-+	RTW_PRINT_SEL(sel, "fwd_bmc:%u\n", stats->fwded_mcast);
-+	RTW_PRINT_SEL(sel, "fwd_uc:%u\n", stats->fwded_unicast);
-+
-+	RTW_PRINT_SEL(sel, "drop_ttl:%u\n", stats->dropped_frames_ttl);
-+	RTW_PRINT_SEL(sel, "drop_no_route:%u\n", stats->dropped_frames_no_route);
-+	RTW_PRINT_SEL(sel, "drop_congestion:%u\n", stats->dropped_frames_congestion);
-+	RTW_PRINT_SEL(sel, "drop_dup:%u\n", stats->dropped_frames_duplicate);
-+
-+	RTW_PRINT_SEL(sel, "mrc_del_qlen:%u\n", stats->mrc_del_qlen);
-+}
-+#endif /* CONFIG_RTW_MESH */
-+
-diff --git a/drivers/staging/rtl8723cs/core/mesh/rtw_mesh.h b/drivers/staging/rtl8723cs/core/mesh/rtw_mesh.h
-new file mode 100644
-index 000000000000..5410ba404468
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/mesh/rtw_mesh.h
-@@ -0,0 +1,537 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_MESH_H_
-+#define __RTW_MESH_H_
-+
-+#ifndef CONFIG_AP_MODE
-+	#error "CONFIG_RTW_MESH can't be enabled when CONFIG_AP_MODE is not defined\n"
-+#endif
-+
-+#define RTW_MESH_TTL				31
-+#define RTW_MESH_PERR_MIN_INT			100
-+#define RTW_MESH_DEFAULT_ELEMENT_TTL		31
-+#define RTW_MESH_RANN_INTERVAL			5000
-+#define RTW_MESH_PATH_TO_ROOT_TIMEOUT		6000
-+#define RTW_MESH_DIAM_TRAVERSAL_TIME		50
-+#define RTW_MESH_PATH_TIMEOUT			5000
-+#define RTW_MESH_PREQ_MIN_INT			10
-+#define RTW_MESH_MAX_PREQ_RETRIES		4
-+#define RTW_MESH_MIN_DISCOVERY_TIMEOUT 		(2 * RTW_MESH_DIAM_TRAVERSAL_TIME)
-+#define RTW_MESH_ROOT_CONFIRMATION_INTERVAL	2000
-+#define RTW_MESH_PATH_REFRESH_TIME		1000
-+#define RTW_MESH_ROOT_INTERVAL			5000
-+
-+#define RTW_MESH_SANE_METRIC_DELTA		100
-+#define RTW_MESH_MAX_ROOT_ADD_CHK_CNT		2
-+
-+#define RTW_MESH_PLINK_UNKNOWN	0
-+#define RTW_MESH_PLINK_LISTEN	1
-+#define RTW_MESH_PLINK_OPN_SNT	2
-+#define RTW_MESH_PLINK_OPN_RCVD 3
-+#define RTW_MESH_PLINK_CNF_RCVD 4
-+#define RTW_MESH_PLINK_ESTAB	5
-+#define RTW_MESH_PLINK_HOLDING	6
-+#define RTW_MESH_PLINK_BLOCKED	7
-+
-+extern const char *_rtw_mesh_plink_str[];
-+#define rtw_mesh_plink_str(s) ((s <= RTW_MESH_PLINK_BLOCKED) ? _rtw_mesh_plink_str[s] : _rtw_mesh_plink_str[RTW_MESH_PLINK_UNKNOWN])
-+
-+#define RTW_MESH_PS_UNKNOWN 0
-+#define RTW_MESH_PS_ACTIVE 1
-+#define RTW_MESH_PS_LSLEEP 2
-+#define RTW_MESH_PS_DSLEEP 3
-+
-+extern const char *_rtw_mesh_ps_str[];
-+#define rtw_mesh_ps_str(mps) ((mps <= RTW_MESH_PS_DSLEEP) ? _rtw_mesh_ps_str[mps] : _rtw_mesh_ps_str[RTW_MESH_PS_UNKNOWN])
-+
-+#define GET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(_iec)		LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 0, 0, 8)
-+#define GET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(_iec)		LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 1, 0, 8)
-+#define GET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(_iec)	LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 2, 0, 8)
-+#define GET_MESH_CONF_ELE_SYNC_METHOD_ID(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 3, 0, 8)
-+#define GET_MESH_CONF_ELE_AUTH_PROTO_ID(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 4, 0, 8)
-+
-+#define GET_MESH_CONF_ELE_MESH_FORMATION(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 0, 8)
-+#define GET_MESH_CONF_ELE_CTO_MGATE(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 0, 1)
-+#define GET_MESH_CONF_ELE_NUM_OF_PEERINGS(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 1, 6)
-+#define GET_MESH_CONF_ELE_CTO_AS(_iec)					LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 7, 1)
-+
-+#define GET_MESH_CONF_ELE_MESH_CAP(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 0, 8)
-+#define GET_MESH_CONF_ELE_ACCEPT_PEERINGS(_iec)			LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 0, 1)
-+#define GET_MESH_CONF_ELE_MCCA_SUP(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 1, 1)
-+#define GET_MESH_CONF_ELE_MCCA_EN(_iec)					LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 2, 1)
-+#define GET_MESH_CONF_ELE_FORWARDING(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 3, 1)
-+#define GET_MESH_CONF_ELE_MBCA_EN(_iec)					LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 4, 1)
-+#define GET_MESH_CONF_ELE_TBTT_ADJ(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 5, 1)
-+#define GET_MESH_CONF_ELE_PS_LEVEL(_iec)				LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 6, 1)
-+
-+#define SET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(_iec, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 0, 0, 8, _val)
-+#define SET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(_iec, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 1, 0, 8, _val)
-+#define SET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(_iec, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 2, 0, 8, _val)
-+#define SET_MESH_CONF_ELE_SYNC_METHOD_ID(_iec, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 3, 0, 8, _val)
-+#define SET_MESH_CONF_ELE_AUTH_PROTO_ID(_iec, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 4, 0, 8, _val)
-+
-+#define SET_MESH_CONF_ELE_CTO_MGATE(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 0, 1, _val)
-+#define SET_MESH_CONF_ELE_NUM_OF_PEERINGS(_iec, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 1, 6, _val)
-+#define SET_MESH_CONF_ELE_CTO_AS(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 7, 1, _val)
-+
-+#define SET_MESH_CONF_ELE_ACCEPT_PEERINGS(_iec, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 0, 1, _val)
-+#define SET_MESH_CONF_ELE_MCCA_SUP(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 1, 1, _val)
-+#define SET_MESH_CONF_ELE_MCCA_EN(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 2, 1, _val)
-+#define SET_MESH_CONF_ELE_FORWARDING(_iec, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 3, 1, _val)
-+#define SET_MESH_CONF_ELE_MBCA_EN(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 4, 1, _val)
-+#define SET_MESH_CONF_ELE_TBTT_ADJ(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 5, 1, _val)
-+#define SET_MESH_CONF_ELE_PS_LEVEL(_iec, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 6, 1, _val)
-+
-+/* Mesh flags */
-+#define MESH_FLAGS_AE		0x3 /* mask */
-+#define MESH_FLAGS_AE_A4 	0x1
-+#define MESH_FLAGS_AE_A5_A6	0x2
-+
-+/* Max number of paths */
-+#define RTW_MESH_MAX_PATHS 1024
-+
-+#define RTW_PREQ_Q_F_START	0x1
-+#define RTW_PREQ_Q_F_REFRESH	0x2
-+#define RTW_PREQ_Q_F_CHK	0x4
-+#define RTW_PREQ_Q_F_PEER_AKA	0x8
-+#define RTW_PREQ_Q_F_BCAST_PREQ	0x10 /* force path_dicover using broadcast */
-+struct rtw_mesh_preq_queue {
-+	_list list;
-+	u8 dst[ETH_ALEN];
-+	u8 flags;
-+};
-+
-+extern const u8 ae_to_mesh_ctrl_len[];
-+
-+enum mesh_frame_type {
-+	MESH_UCAST_DATA		= 0x0,
-+	MESH_BMCAST_DATA	= 0x1,
-+	MESH_UCAST_PX_DATA	= 0x2,
-+	MESH_BMCAST_PX_DATA	= 0x3,
-+	MESH_MHOP_UCAST_ACT	= 0x4,
-+	MESH_MHOP_BMCAST_ACT	= 0x5,
-+};
-+
-+enum mpath_sel_frame_type {
-+	MPATH_PREQ = 0,
-+	MPATH_PREP,
-+	MPATH_PERR,
-+	MPATH_RANN
-+};
-+
-+/**
-+ * enum rtw_mesh_deferred_task_flags - mesh deferred tasks
-+ *
-+ *
-+ *
-+ * @RTW_MESH_WORK_HOUSEKEEPING: run the periodic mesh housekeeping tasks
-+ * @RTW_MESH_WORK_ROOT: the mesh root station needs to send a frame
-+ * @RTW_MESH_WORK_DRIFT_ADJUST: time to compensate for clock drift relative to other
-+ * mesh nodes
-+ * @RTW_MESH_WORK_MBSS_CHANGED: rebuild beacon and notify driver of BSS changes
-+ */
-+enum rtw_mesh_deferred_task_flags {
-+	RTW_MESH_WORK_HOUSEKEEPING,
-+	RTW_MESH_WORK_ROOT,
-+	RTW_MESH_WORK_DRIFT_ADJUST,
-+	RTW_MESH_WORK_MBSS_CHANGED,
-+};
-+
-+#define RTW_MESH_MAX_PEER_CANDIDATES 15 /* aid consideration */
-+#define RTW_MESH_MAX_PEER_LINKS 8
-+#define RTW_MESH_PEER_LINK_TIMEOUT 20
-+
-+#define RTW_MESH_PEER_CONF_DISABLED 0 /* special time value means no confirmation ongoing */
-+#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+#define IS_PEER_CONF_DISABLED(plink) ((plink)->peer_conf_end_time == RTW_MESH_PEER_CONF_DISABLED)
-+#define IS_PEER_CONF_TIMEOUT(plink)(!IS_PEER_CONF_DISABLED(plink) && rtw_time_after(rtw_get_current_time(), (plink)->peer_conf_end_time))
-+#define SET_PEER_CONF_DISABLED(plink) (plink)->peer_conf_end_time = RTW_MESH_PEER_CONF_DISABLED
-+#define SET_PEER_CONF_END_TIME(plink, timeout_ms) \
-+	do { \
-+		(plink)->peer_conf_end_time = rtw_get_current_time() + rtw_ms_to_systime(timeout_ms); \
-+		if ((plink)->peer_conf_end_time == RTW_MESH_PEER_CONF_DISABLED) \
-+			(plink)->peer_conf_end_time++; \
-+	} while (0)
-+#else
-+#define IS_PEER_CONF_DISABLED(plink) 1
-+#define IS_PEER_CONF_TIMEOUT(plink) 0
-+#define SET_PEER_CONF_DISABLED(plink) do {} while (0)
-+#define SET_PEER_CONF_END_TIME(plink, timeout_ms) do {} while (0)
-+#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */
-+
-+#define RTW_MESH_CTO_MGATE_CONF_DISABLED 0 /* special time value means no confirmation ongoing */
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+#define IS_CTO_MGATE_CONF_DISABLED(plink) ((plink)->cto_mgate_conf_end_time == RTW_MESH_CTO_MGATE_CONF_DISABLED)
-+#define IS_CTO_MGATE_CONF_TIMEOUT(plink)(!IS_CTO_MGATE_CONF_DISABLED(plink) && rtw_time_after(rtw_get_current_time(), (plink)->cto_mgate_conf_end_time))
-+#define SET_CTO_MGATE_CONF_DISABLED(plink) (plink)->cto_mgate_conf_end_time = RTW_MESH_CTO_MGATE_CONF_DISABLED
-+#define SET_CTO_MGATE_CONF_END_TIME(plink, timeout_ms) \
-+	do { \
-+		(plink)->cto_mgate_conf_end_time = rtw_get_current_time() + rtw_ms_to_systime(timeout_ms); \
-+		if ((plink)->cto_mgate_conf_end_time == RTW_MESH_CTO_MGATE_CONF_DISABLED) \
-+			(plink)->cto_mgate_conf_end_time++; \
-+	} while (0)
-+#else
-+#define IS_CTO_MGATE_CONF_DISABLED(plink) 1
-+#define IS_CTO_MGATE_CONF_TIMEOUT(plink) 0
-+#define SET_CTO_MGATE_CONF_DISABLED(plink) do {} while (0)
-+#define SET_CTO_MGATE_CONF_END_TIME(plink, timeout_ms) do {} while (0)
-+#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
-+
-+struct mesh_plink_ent {
-+	u8 valid;
-+	u8 addr[ETH_ALEN];
-+	u8 plink_state;
-+
-+#ifdef CONFIG_RTW_MESH_AEK
-+	u8 aek_valid;
-+	u8 aek[32];
-+#endif
-+
-+	u16 llid;
-+	u16 plid;
-+#ifndef CONFIG_RTW_MESH_DRIVER_AID
-+	u16 aid; /* aid assigned from upper layer */
-+#endif
-+	u16 peer_aid; /* aid assigned from peer */
-+
-+	u8 chosen_pmk[16];
-+
-+#ifdef CONFIG_RTW_MESH_AEK
-+	u8 sel_pcs[4];
-+	u8 l_nonce[32];
-+	u8 p_nonce[32];
-+#endif
-+
-+#ifdef CONFIG_RTW_MESH_DRIVER_AID
-+	u8 *tx_conf_ies;
-+	u16 tx_conf_ies_len;
-+#endif
-+	u8 *rx_conf_ies;
-+	u16 rx_conf_ies_len;
-+
-+	struct wlan_network *scanned;
-+
-+#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+	systime peer_conf_end_time;
-+#endif
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	systime cto_mgate_conf_end_time;
-+#endif
-+};
-+
-+#ifdef CONFIG_RTW_MESH_AEK
-+#define MESH_PLINK_AEK_VALID(ent) ent->aek_valid
-+#else
-+#define MESH_PLINK_AEK_VALID(ent) 0
-+#endif
-+
-+struct mesh_plink_pool {
-+	_lock lock;
-+	u8 num; /* current ent being used */
-+	struct mesh_plink_ent ent[RTW_MESH_MAX_PEER_CANDIDATES];
-+
-+#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+	u8 acnode_rsvd;
-+#endif
-+
-+#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+	_queue peer_blacklist;
-+#endif
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	_queue cto_mgate_blacklist;
-+#endif
-+};
-+
-+struct mesh_peer_sel_policy {
-+	u32 scanr_exp_ms;
-+
-+#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+	u8 acnode_prevent;
-+	u32 acnode_conf_timeout_ms;
-+	u32 acnode_notify_timeout_ms;
-+#endif
-+
-+#if CONFIG_RTW_MESH_OFFCH_CAND
-+	u8 offch_cand;
-+	u32 offch_find_int_ms; /* 0 means no offch find triggerred by driver self*/
-+#endif
-+
-+#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+	u32 peer_conf_timeout_ms;
-+	u32 peer_blacklist_timeout_ms;
-+#endif
-+
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	u8 cto_mgate_require;
-+	u32 cto_mgate_conf_timeout_ms;
-+	u32 cto_mgate_blacklist_timeout_ms;
-+#endif
-+};
-+
-+/* b2u flags */
-+#define RTW_MESH_B2U_ALL		BIT0
-+#define RTW_MESH_B2U_GA_UCAST	BIT1 /* Group addressed unicast frame, forward only */
-+#define RTW_MESH_B2U_BCAST		BIT2
-+#define RTW_MESH_B2U_IP_MCAST	BIT3
-+
-+#define rtw_msrc_b2u_policy_chk(flags, mda) ( \
-+	(flags & RTW_MESH_B2U_ALL) \
-+	|| ((flags & RTW_MESH_B2U_BCAST) && is_broadcast_mac_addr(mda)) \
-+	|| ((flags & RTW_MESH_B2U_IP_MCAST) && (IP_MCAST_MAC(mda) || ICMPV6_MCAST_MAC(mda))) \
-+	)
-+
-+#define rtw_mfwd_b2u_policy_chk(flags, mda, ucst) ( \
-+	(flags & RTW_MESH_B2U_ALL) \
-+	|| ((flags & RTW_MESH_B2U_GA_UCAST) && ucst) \
-+	|| ((flags & RTW_MESH_B2U_BCAST) && is_broadcast_mac_addr(mda)) \
-+	|| ((flags & RTW_MESH_B2U_IP_MCAST) && (IP_MCAST_MAC(mda) || ICMPV6_MCAST_MAC(mda))) \
-+	)
-+
-+/**
-+ * @sane_metric_delta: Controlling if trigger additional path check mechanism
-+ * @max_root_add_chk_cnt: The retry cnt to send additional root confirmation
-+ *	PREQ through old(last) path
-+ */
-+struct rtw_mesh_cfg {
-+	u8 max_peer_links; /* peering limit */
-+	u32 plink_timeout; /* seconds */
-+
-+	u8 dot11MeshTTL;
-+	u8 element_ttl;
-+	u32 path_refresh_time;
-+	u16 dot11MeshHWMPpreqMinInterval;
-+	u16 dot11MeshHWMPnetDiameterTraversalTime;
-+	u32 dot11MeshHWMPactivePathTimeout;
-+	u8 dot11MeshHWMPmaxPREQretries;
-+	u16 min_discovery_timeout;
-+	u16 dot11MeshHWMPconfirmationInterval;
-+	u16 dot11MeshHWMPperrMinInterval;
-+	u8 dot11MeshHWMPRootMode;
-+	BOOLEAN dot11MeshForwarding;
-+	s32 rssi_threshold; /* in dBm, 0: no specified */
-+	u16 dot11MeshHWMPRannInterval;
-+	BOOLEAN dot11MeshGateAnnouncementProtocol;
-+	u32 dot11MeshHWMPactivePathToRootTimeout;
-+	u16 dot11MeshHWMProotInterval;
-+	u8 path_gate_timeout_factor;
-+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
-+	u16 sane_metric_delta;
-+	u8 max_root_add_chk_cnt;
-+#endif
-+
-+	struct mesh_peer_sel_policy peer_sel_policy;
-+
-+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+	u8 b2u_flags_msrc;
-+	u8 b2u_flags_mfwd;
-+#endif
-+};
-+
-+struct rtw_mesh_stats {
-+	u32 fwded_mcast;		/* Mesh forwarded multicast frames */
-+	u32 fwded_unicast;		/* Mesh forwarded unicast frames */
-+	u32 fwded_frames;		/* Mesh total forwarded frames */
-+	u32 dropped_frames_ttl;	/* Not transmitted since mesh_ttl == 0*/
-+	u32 dropped_frames_no_route;	/* Not transmitted, no route found */
-+	u32 dropped_frames_congestion;/* Not forwarded due to congestion */
-+	u32 dropped_frames_duplicate;
-+
-+	u32 mrc_del_qlen; /* MRC entry deleted cause by queue length limit */
-+};
-+
-+struct rtw_mrc;
-+
-+struct rtw_mesh_info {
-+	u8 mesh_id[NDIS_802_11_LENGTH_SSID];
-+	size_t mesh_id_len;
-+	/* Active Path Selection Protocol Identifier */
-+	u8 mesh_pp_id;
-+	/* Active Path Selection Metric Identifier */
-+	u8 mesh_pm_id;
-+	/* Congestion Control Mode Identifier */
-+	u8 mesh_cc_id;
-+	/* Synchronization Protocol Identifier */
-+	u8 mesh_sp_id;
-+	/* Authentication Protocol Identifier */
-+	u8 mesh_auth_id;
-+
-+	struct mesh_plink_pool plink_ctl;
-+
-+	u32 mesh_seqnum;
-+	/* MSTA's own hwmp sequence number */
-+	u32 sn;
-+	systime last_preq;
-+	systime last_sn_update;
-+	systime next_perr;
-+	/* Last used Path Discovery ID */
-+	u32 preq_id;
-+	
-+	ATOMIC_T mpaths;
-+	struct rtw_mesh_table *mesh_paths;
-+	struct rtw_mesh_table *mpp_paths;
-+	int mesh_paths_generation;
-+	int mpp_paths_generation;
-+
-+	int num_gates;
-+	struct rtw_mesh_path *max_addr_gate;
-+	bool max_addr_gate_is_larger_than_self;
-+
-+	struct rtw_mesh_stats mshstats;
-+
-+	_queue mpath_tx_queue;
-+	u32 mpath_tx_queue_len;
-+	_tasklet mpath_tx_tasklet;
-+
-+	struct rtw_mrc *mrc;
-+
-+	_lock mesh_preq_queue_lock;
-+	struct rtw_mesh_preq_queue preq_queue;
-+	int preq_queue_len;
-+};
-+
-+extern const char *_action_self_protected_str[];
-+#define action_self_protected_str(action) ((action < RTW_ACT_SELF_PROTECTED_NUM) ? _action_self_protected_str[action] : _action_self_protected_str[0])
-+
-+u8 *rtw_set_ie_mesh_id(u8 *buf, u32 *buf_len, const char *mesh_id, u8 id_len);
-+u8 *rtw_set_ie_mesh_config(u8 *buf, u32 *buf_len
-+	, u8 path_sel_proto, u8 path_sel_metric, u8 congest_ctl_mode, u8 sync_method, u8 auth_proto
-+	, u8 num_of_peerings, bool cto_mgate, bool cto_as
-+	, bool accept_peerings, bool mcca_sup, bool mcca_en, bool forwarding
-+	, bool mbca_en, bool tbtt_adj, bool ps_level);
-+
-+int rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b);
-+int rtw_bss_is_candidate_mesh_peer(_adapter *adapter, WLAN_BSSID_EX *target, u8 ch, u8 add_peer);
-+
-+void rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scanned);
-+
-+void rtw_mesh_peer_status_chk(_adapter *adapter);
-+
-+#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+void rtw_mesh_update_scanned_acnode_status(_adapter *adapter, struct wlan_network *scanned);
-+bool rtw_mesh_scanned_is_acnode_confirmed(_adapter *adapter, struct wlan_network *scanned);
-+bool rtw_mesh_acnode_prevent_allow_sacrifice(_adapter *adapter);
-+struct sta_info *rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter);
-+void dump_mesh_acnode_prevent_settings(void *sel, _adapter *adapter);
-+#endif
-+
-+#if CONFIG_RTW_MESH_OFFCH_CAND
-+u8 rtw_mesh_offch_candidate_accepted(_adapter *adapter);
-+u8 rtw_mesh_select_operating_ch(_adapter *adapter);
-+void dump_mesh_offch_cand_settings(void *sel, _adapter *adapter);
-+#endif
-+
-+#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+int rtw_mesh_peer_blacklist_add(_adapter *adapter, const u8 *addr);
-+int rtw_mesh_peer_blacklist_del(_adapter *adapter, const u8 *addr);
-+int rtw_mesh_peer_blacklist_search(_adapter *adapter, const u8 *addr);
-+void rtw_mesh_peer_blacklist_flush(_adapter *adapter);
-+void dump_mesh_peer_blacklist(void *sel, _adapter *adapter);
-+void dump_mesh_peer_blacklist_settings(void *sel, _adapter *adapter);
-+#endif
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+u8 rtw_mesh_cto_mgate_required(_adapter *adapter);
-+u8 rtw_mesh_cto_mgate_network_filter(_adapter *adapter, struct wlan_network *scanned);
-+int rtw_mesh_cto_mgate_blacklist_add(_adapter *adapter, const u8 *addr);
-+int rtw_mesh_cto_mgate_blacklist_del(_adapter *adapter, const u8 *addr);
-+int rtw_mesh_cto_mgate_blacklist_search(_adapter *adapter, const u8 *addr);
-+void rtw_mesh_cto_mgate_blacklist_flush(_adapter *adapter);
-+void dump_mesh_cto_mgate_blacklist(void *sel, _adapter *adapter);
-+void dump_mesh_cto_mgate_blacklist_settings(void *sel, _adapter *adapter);
-+#endif
-+void dump_mesh_peer_sel_policy(void *sel, _adapter *adapter);
-+void dump_mesh_networks(void *sel, _adapter *adapter);
-+
-+void rtw_mesh_adjust_chbw(u8 req_ch, u8 *req_bw, u8 *req_offset);
-+
-+void rtw_mesh_sae_check_frames(_adapter *adapter, const u8 *buf, u32 len, u8 tx, u16 alg, u16 seq, u16 status);
-+int rtw_mesh_check_frames_tx(_adapter *adapter, const u8 **buf, size_t *len);
-+int rtw_mesh_check_frames_rx(_adapter *adapter, const u8 *buf, size_t len);
-+
-+int rtw_mesh_on_auth(_adapter *adapter, union recv_frame *rframe);
-+unsigned int on_action_self_protected(_adapter *adapter, union recv_frame *rframe);
-+
-+bool rtw_mesh_update_bss_peering_status(_adapter *adapter, WLAN_BSSID_EX *bss);
-+bool rtw_mesh_update_bss_formation_info(_adapter *adapter, WLAN_BSSID_EX *bss);
-+bool rtw_mesh_update_bss_forwarding_state(_adapter *adapter, WLAN_BSSID_EX *bss);
-+
-+struct mesh_plink_ent *_rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr);
-+struct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr);
-+struct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 idx);
-+int _rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr);
-+int rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr);
-+int rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state);
-+#ifdef CONFIG_RTW_MESH_AEK
-+int rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek);
-+#endif
-+#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+int rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr);
-+#endif
-+void _rtw_mesh_plink_del_ent(_adapter *adapter, struct mesh_plink_ent *ent);
-+int rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr);
-+void rtw_mesh_plink_ctl_init(_adapter *adapter);
-+void rtw_mesh_plink_ctl_deinit(_adapter *adapter);
-+void dump_mesh_plink_ctl(void *sel, _adapter *adapter);
-+
-+u8 rtw_mesh_set_plink_state_cmd(_adapter *adapter, const u8 *mac, u8 plink_state);
-+
-+void _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink);
-+void rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr);
-+u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps);
-+
-+unsigned int on_action_mesh(_adapter *adapter, union recv_frame *rframe);
-+
-+void rtw_mesh_cfg_init(_adapter *adapter);
-+void rtw_mesh_cfg_init_max_peer_links(_adapter *adapter, u8 stack_conf);
-+void rtw_mesh_cfg_init_plink_timeout(_adapter *adapter, u32 stack_conf);
-+void rtw_mesh_init_mesh_info(_adapter *adapter);
-+void rtw_mesh_deinit_mesh_info(_adapter *adapter);
-+
-+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+void dump_mesh_b2u_flags(void *sel, _adapter *adapter);
-+#endif
-+
-+int rtw_mesh_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list);
-+
-+s8 rtw_mesh_tx_set_whdr_mctrl_len(u8 mesh_frame_mode, struct pkt_attrib *attrib);
-+void rtw_mesh_tx_build_mctrl(_adapter *adapter, struct pkt_attrib *attrib, u8 *buf);
-+u8 rtw_mesh_tx_build_whdr(_adapter *adapter, struct pkt_attrib *attrib
-+	, u16 *fctrl, struct rtw_ieee80211_hdr *whdr);
-+
-+int rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta);
-+int rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe
-+	, const struct rtw_ieee80211s_hdr *mctrl, const u8 *mda, const u8 *msa
-+	, u8 *mctrl_len, const u8 **da, const u8 **sa);
-+int rtw_mesh_rx_validate_mctrl_non_amsdu(_adapter *adapter, union recv_frame *rframe);
-+
-+int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe
-+	, const u8 *mda, const u8 *msa
-+	, const u8 *da, const u8 *sa
-+	, struct rtw_ieee80211s_hdr *mctrl
-+	, u8 *msdu, enum rtw_rx_llc_hdl llc_hdl
-+	, struct xmit_frame **fwd_frame, _list *b2u_list);
-+
-+void dump_mesh_stats(void *sel, _adapter *adapter);
-+
-+#if defined(PLATFORM_LINUX) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32))
-+#define rtw_lockdep_assert_held(l) lockdep_assert_held(l)
-+#define rtw_lockdep_is_held(l) lockdep_is_held(l)
-+#else
-+#error "TBD\n"
-+#endif
-+
-+#include "rtw_mesh_pathtbl.h"
-+#include "rtw_mesh_hwmp.h"
-+#endif /* __RTW_MESH_H_ */
-+
-diff --git a/drivers/staging/rtl8723cs/core/mesh/rtw_mesh_hwmp.c b/drivers/staging/rtl8723cs/core/mesh/rtw_mesh_hwmp.c
-new file mode 100644
-index 000000000000..04be425b2140
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/mesh/rtw_mesh_hwmp.c
-@@ -0,0 +1,1518 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_HWMP_C_
-+
-+#ifdef CONFIG_RTW_MESH
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#define RTW_TEST_FRAME_LEN	8192
-+#define RTW_MAX_METRIC	0xffffffff
-+#define RTW_ARITH_SHIFT	8
-+#define RTW_LINK_FAIL_THRESH 95
-+#define RTW_MAX_PREQ_QUEUE_LEN	64
-+#define RTW_ATLM_REQ_CYCLE 1000
-+
-+#define rtw_ilog2(n)			\
-+(					\
-+	(n) < 2 ? 0 :			\
-+	(n) & (1ULL << 63) ? 63 :	\
-+	(n) & (1ULL << 62) ? 62 :	\
-+	(n) & (1ULL << 61) ? 61 :	\
-+	(n) & (1ULL << 60) ? 60 :	\
-+	(n) & (1ULL << 59) ? 59 :	\
-+	(n) & (1ULL << 58) ? 58 :	\
-+	(n) & (1ULL << 57) ? 57 :	\
-+	(n) & (1ULL << 56) ? 56 :	\
-+	(n) & (1ULL << 55) ? 55 :	\
-+	(n) & (1ULL << 54) ? 54 :	\
-+	(n) & (1ULL << 53) ? 53 :	\
-+	(n) & (1ULL << 52) ? 52 :	\
-+	(n) & (1ULL << 51) ? 51 :	\
-+	(n) & (1ULL << 50) ? 50 :	\
-+	(n) & (1ULL << 49) ? 49 :	\
-+	(n) & (1ULL << 48) ? 48 :	\
-+	(n) & (1ULL << 47) ? 47 :	\
-+	(n) & (1ULL << 46) ? 46 :	\
-+	(n) & (1ULL << 45) ? 45 :	\
-+	(n) & (1ULL << 44) ? 44 :	\
-+	(n) & (1ULL << 43) ? 43 :	\
-+	(n) & (1ULL << 42) ? 42 :	\
-+	(n) & (1ULL << 41) ? 41 :	\
-+	(n) & (1ULL << 40) ? 40 :	\
-+	(n) & (1ULL << 39) ? 39 :	\
-+	(n) & (1ULL << 38) ? 38 :	\
-+	(n) & (1ULL << 37) ? 37 :	\
-+	(n) & (1ULL << 36) ? 36 :	\
-+	(n) & (1ULL << 35) ? 35 :	\
-+	(n) & (1ULL << 34) ? 34 :	\
-+	(n) & (1ULL << 33) ? 33 :	\
-+	(n) & (1ULL << 32) ? 32 :	\
-+	(n) & (1ULL << 31) ? 31 :	\
-+	(n) & (1ULL << 30) ? 30 :	\
-+	(n) & (1ULL << 29) ? 29 :	\
-+	(n) & (1ULL << 28) ? 28 :	\
-+	(n) & (1ULL << 27) ? 27 :	\
-+	(n) & (1ULL << 26) ? 26 :	\
-+	(n) & (1ULL << 25) ? 25 :	\
-+	(n) & (1ULL << 24) ? 24 :	\
-+	(n) & (1ULL << 23) ? 23 :	\
-+	(n) & (1ULL << 22) ? 22 :	\
-+	(n) & (1ULL << 21) ? 21 :	\
-+	(n) & (1ULL << 20) ? 20 :	\
-+	(n) & (1ULL << 19) ? 19 :	\
-+	(n) & (1ULL << 18) ? 18 :	\
-+	(n) & (1ULL << 17) ? 17 :	\
-+	(n) & (1ULL << 16) ? 16 :	\
-+	(n) & (1ULL << 15) ? 15 :	\
-+	(n) & (1ULL << 14) ? 14 :	\
-+	(n) & (1ULL << 13) ? 13 :	\
-+	(n) & (1ULL << 12) ? 12 :	\
-+	(n) & (1ULL << 11) ? 11 :	\
-+	(n) & (1ULL << 10) ? 10 :	\
-+	(n) & (1ULL <<  9) ?  9 :	\
-+	(n) & (1ULL <<  8) ?  8 :	\
-+	(n) & (1ULL <<  7) ?  7 :	\
-+	(n) & (1ULL <<  6) ?  6 :	\
-+	(n) & (1ULL <<  5) ?  5 :	\
-+	(n) & (1ULL <<  4) ?  4 :	\
-+	(n) & (1ULL <<  3) ?  3 :	\
-+	(n) & (1ULL <<  2) ?  2 :	\
-+	1				\
-+)
-+
-+enum rtw_mpath_frame_type {
-+	RTW_MPATH_PREQ = 0,
-+	RTW_MPATH_PREP,
-+	RTW_MPATH_PERR,
-+	RTW_MPATH_RANN
-+};
-+
-+static inline u32 rtw_u32_field_get(const u8 *preq_elem, int shift, BOOLEAN ae)
-+{
-+	if (ae)
-+		shift += 6;
-+	return LE_BITS_TO_4BYTE(preq_elem + shift, 0, 32);
-+}
-+
-+static inline u16 rtw_u16_field_get(const u8 *preq_elem, int shift, BOOLEAN ae)
-+{
-+	if (ae)
-+		shift += 6;
-+	return LE_BITS_TO_2BYTE(preq_elem + shift, 0, 16);
-+}
-+
-+/* HWMP IE processing macros */
-+#define RTW_AE_F			(1<<6)
-+#define RTW_AE_F_SET(x)			(*x & RTW_AE_F)
-+#define RTW_PREQ_IE_FLAGS(x)		(*(x))
-+#define RTW_PREQ_IE_HOPCOUNT(x)		(*(x + 1))
-+#define RTW_PREQ_IE_TTL(x)		(*(x + 2))
-+#define RTW_PREQ_IE_PREQ_ID(x)		rtw_u32_field_get(x, 3, 0)
-+#define RTW_PREQ_IE_ORIG_ADDR(x)	(x + 7)
-+#define RTW_PREQ_IE_ORIG_SN(x)		rtw_u32_field_get(x, 13, 0)
-+#define RTW_PREQ_IE_LIFETIME(x)		rtw_u32_field_get(x, 17, RTW_AE_F_SET(x))
-+#define RTW_PREQ_IE_METRIC(x) 		rtw_u32_field_get(x, 21, RTW_AE_F_SET(x))
-+#define RTW_PREQ_IE_TARGET_F(x)		(*(RTW_AE_F_SET(x) ? x + 32 : x + 26))
-+#define RTW_PREQ_IE_TARGET_ADDR(x) 	(RTW_AE_F_SET(x) ? x + 33 : x + 27)
-+#define RTW_PREQ_IE_TARGET_SN(x) 	rtw_u32_field_get(x, 33, RTW_AE_F_SET(x))
-+
-+#define RTW_PREP_IE_FLAGS(x)		RTW_PREQ_IE_FLAGS(x)
-+#define RTW_PREP_IE_HOPCOUNT(x)		RTW_PREQ_IE_HOPCOUNT(x)
-+#define RTW_PREP_IE_TTL(x)		RTW_PREQ_IE_TTL(x)
-+#define RTW_PREP_IE_ORIG_ADDR(x)	(RTW_AE_F_SET(x) ? x + 27 : x + 21)
-+#define RTW_PREP_IE_ORIG_SN(x)		rtw_u32_field_get(x, 27, RTW_AE_F_SET(x))
-+#define RTW_PREP_IE_LIFETIME(x)		rtw_u32_field_get(x, 13, RTW_AE_F_SET(x))
-+#define RTW_PREP_IE_METRIC(x)		rtw_u32_field_get(x, 17, RTW_AE_F_SET(x))
-+#define RTW_PREP_IE_TARGET_ADDR(x)	(x + 3)
-+#define RTW_PREP_IE_TARGET_SN(x)	rtw_u32_field_get(x, 9, 0)
-+
-+#define RTW_PERR_IE_TTL(x)		(*(x))
-+#define RTW_PERR_IE_TARGET_FLAGS(x)	(*(x + 2))
-+#define RTW_PERR_IE_TARGET_ADDR(x)	(x + 3)
-+#define RTW_PERR_IE_TARGET_SN(x)	rtw_u32_field_get(x, 9, 0)
-+#define RTW_PERR_IE_TARGET_RCODE(x)	rtw_u16_field_get(x, 13, 0)
-+
-+#define RTW_TU_TO_SYSTIME(x)	(rtw_us_to_systime((x) * 1024))
-+#define RTW_TU_TO_EXP_TIME(x)	(rtw_get_current_time() + RTW_TU_TO_SYSTIME(x))
-+#define RTW_MSEC_TO_TU(x) (x*1000/1024)
-+#define RTW_SN_GT(x, y) ((s32)(y - x) < 0)
-+#define RTW_SN_LT(x, y) ((s32)(x - y) < 0)
-+#define RTW_MAX_SANE_SN_DELTA 32
-+
-+static inline u32 RTW_SN_DELTA(u32 x, u32 y)
-+{
-+	return x >= y ? x - y : y - x;
-+}
-+
-+#define rtw_net_traversal_jiffies(adapter) \
-+	rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPnetDiameterTraversalTime)
-+#define rtw_default_lifetime(adapter) \
-+	RTW_MSEC_TO_TU(adapter->mesh_cfg.dot11MeshHWMPactivePathTimeout)
-+#define rtw_min_preq_int_jiff(adapter) \
-+	(rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPpreqMinInterval))
-+#define rtw_max_preq_retries(adapter) (adapter->mesh_cfg.dot11MeshHWMPmaxPREQretries)
-+#define rtw_disc_timeout_jiff(adapter) \
-+	rtw_ms_to_systime(adapter->mesh_cfg.min_discovery_timeout)
-+#define rtw_root_path_confirmation_jiffies(adapter) \
-+	rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPconfirmationInterval)
-+
-+static inline BOOLEAN rtw_ether_addr_equal(const u8 *addr1, const u8 *addr2)
-+{
-+	return _rtw_memcmp(addr1, addr2, ETH_ALEN);
-+}
-+
-+#ifdef PLATFORM_LINUX
-+#define rtw_print_ratelimit()	printk_ratelimit()
-+#define rtw_mod_timer(ptimer, expires) mod_timer(&(ptimer)->timer, expires)
-+#else
-+
-+#endif
-+
-+#define RTW_MESH_EWMA_PRECISION 20
-+#define RTW_MESH_EWMA_WEIGHT_RCP 8
-+#define RTW_TOTAL_PKT_MIN_THRESHOLD 1
-+inline void rtw_ewma_err_rate_init(struct rtw_ewma_err_rate *e)
-+{
-+	e->internal = 0;
-+}
-+inline unsigned long rtw_ewma_err_rate_read(struct rtw_ewma_err_rate *e)
-+{
-+	return e->internal >> (RTW_MESH_EWMA_PRECISION);
-+}
-+inline void rtw_ewma_err_rate_add(struct rtw_ewma_err_rate *e,
-+				  unsigned long val)
-+{
-+	unsigned long internal = e->internal;
-+	unsigned long weight_rcp = rtw_ilog2(RTW_MESH_EWMA_WEIGHT_RCP);
-+	unsigned long precision = RTW_MESH_EWMA_PRECISION;
-+
-+	(e->internal) = internal ? (((internal << weight_rcp) - internal) +
-+			(val << precision)) >> weight_rcp :
-+			(val << precision);
-+}
-+
-+static const u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+
-+static int rtw_mesh_path_sel_frame_tx(enum rtw_mpath_frame_type mpath_action, u8 flags,
-+				      const u8 *originator_addr, u32 originator_sn,
-+				      u8 target_flags, const u8 *target,
-+				      u32 target_sn, const u8 *da, u8 hopcount, u8 ttl,
-+				      u32 lifetime, u32 metric, u32 preq_id, 
-+				      _adapter *adapter)
-+{
-+	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+	struct xmit_frame *pmgntframe = NULL;
-+	struct rtw_ieee80211_hdr *pwlanhdr = NULL;
-+	struct pkt_attrib *pattrib = NULL;
-+	u8 category = RTW_WLAN_CATEGORY_MESH;
-+	u8 action = RTW_ACT_MESH_HWMP_PATH_SELECTION;
-+	u16 *fctrl = NULL;
-+	u8 *pos, ie_len;
-+
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return -1;
-+
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(adapter, pattrib);
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pos = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pos;
-+
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pos, WIFI_ACTION);
-+
-+	pos += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pos = rtw_set_fixed_ie(pos, 1, &(category), &(pattrib->pktlen));
-+	pos = rtw_set_fixed_ie(pos, 1, &(action), &(pattrib->pktlen));
-+
-+	switch (mpath_action) {
-+	case RTW_MPATH_PREQ:
-+		RTW_HWMP_DBG("sending PREQ to "MAC_FMT"\n", MAC_ARG(target));
-+		ie_len = 37;
-+		pattrib->pktlen += (ie_len + 2);
-+		*pos++ = WLAN_EID_PREQ;
-+		break;
-+	case RTW_MPATH_PREP:
-+		RTW_HWMP_DBG("sending PREP to "MAC_FMT"\n", MAC_ARG(originator_addr));
-+		ie_len = 31;
-+		pattrib->pktlen += (ie_len + 2);
-+		*pos++ = WLAN_EID_PREP;
-+		break;
-+	case RTW_MPATH_RANN:
-+		RTW_HWMP_DBG("sending RANN from "MAC_FMT"\n", MAC_ARG(originator_addr));
-+		ie_len = sizeof(struct rtw_ieee80211_rann_ie);
-+		pattrib->pktlen += (ie_len + 2);
-+		*pos++ = WLAN_EID_RANN;
-+		break;
-+	default:
-+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+		return _FAIL;
-+	}
-+	*pos++ = ie_len;
-+	*pos++ = flags;
-+	*pos++ = hopcount;
-+	*pos++ = ttl;
-+	if (mpath_action == RTW_MPATH_PREP) {
-+		_rtw_memcpy(pos, target, ETH_ALEN);
-+		pos += ETH_ALEN;
-+		*(u32 *)pos = cpu_to_le32(target_sn);
-+		pos += 4;
-+	} else {
-+		if (mpath_action == RTW_MPATH_PREQ) {
-+			*(u32 *)pos = cpu_to_le32(preq_id);
-+			pos += 4;
-+		}
-+		_rtw_memcpy(pos, originator_addr, ETH_ALEN);
-+		pos += ETH_ALEN;
-+		*(u32 *)pos = cpu_to_le32(originator_sn);
-+		pos += 4;
-+	}
-+	*(u32 *)pos = cpu_to_le32(lifetime);
-+	pos += 4;
-+	*(u32 *)pos = cpu_to_le32(metric);
-+	pos += 4;
-+	if (mpath_action == RTW_MPATH_PREQ) {
-+		*pos++ = 1; /* support only 1 destination now */
-+		*pos++ = target_flags;
-+		_rtw_memcpy(pos, target, ETH_ALEN);
-+		pos += ETH_ALEN;
-+		*(u32 *)pos = cpu_to_le32(target_sn);
-+		pos += 4;
-+	} else if (mpath_action == RTW_MPATH_PREP) {
-+		_rtw_memcpy(pos, originator_addr, ETH_ALEN);
-+		pos += ETH_ALEN;
-+		*(u32 *)pos = cpu_to_le32(originator_sn);
-+		pos += 4;
-+	}
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+	dump_mgntframe(adapter, pmgntframe);
-+	return 0;
-+}
-+
-+int rtw_mesh_path_error_tx(_adapter *adapter,
-+			   u8 ttl, const u8 *target, u32 target_sn,
-+			   u16 perr_reason_code, const u8 *ra)
-+{
-+
-+	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+	struct xmit_frame *pmgntframe = NULL;
-+	struct rtw_ieee80211_hdr *pwlanhdr = NULL;
-+	struct pkt_attrib *pattrib = NULL;
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	u8 category = RTW_WLAN_CATEGORY_MESH;
-+	u8 action = RTW_ACT_MESH_HWMP_PATH_SELECTION;
-+	u8 *pos, ie_len;
-+	u16 *fctrl = NULL;
-+
-+	if (rtw_time_before(rtw_get_current_time(), minfo->next_perr))
-+		return -1;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return -1;
-+
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(adapter, pattrib);
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pos = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pos;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pos, WIFI_ACTION);
-+
-+	pos += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pos = rtw_set_fixed_ie(pos, 1, &(category), &(pattrib->pktlen));
-+	pos = rtw_set_fixed_ie(pos, 1, &(action), &(pattrib->pktlen));
-+
-+	ie_len = 15;
-+	pattrib->pktlen += (2 + ie_len);
-+	*pos++ = WLAN_EID_PERR;
-+	*pos++ = ie_len;
-+	/* ttl */
-+	*pos++ = ttl;
-+	/* The Number of Destinations N */
-+	*pos++ = 1;
-+	/* Flags format | B7 | B6 | B5:B0 | = | rsvd | AE | rsvd | */
-+	*pos = 0;
-+	pos++;
-+	_rtw_memcpy(pos, target, ETH_ALEN);
-+	pos += ETH_ALEN;
-+	*(u32 *)pos = cpu_to_le32(target_sn);
-+	pos += 4;
-+	*(u16 *)pos = cpu_to_le16(perr_reason_code);
-+
-+	adapter->mesh_info.next_perr = RTW_TU_TO_EXP_TIME(
-+				adapter->mesh_cfg.dot11MeshHWMPperrMinInterval);
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+	/* Send directly. Rewrite it if deferred tx is needed */
-+	dump_mgntframe(adapter, pmgntframe);
-+
-+	RTW_HWMP_DBG("TX PERR toward "MAC_FMT", ra = "MAC_FMT"\n", MAC_ARG(target), MAC_ARG(ra));
-+	
-+	return 0;
-+}
-+
-+static u32 rtw_airtime_link_metric_get(_adapter *adapter, struct sta_info *sta)
-+{
-+	struct dm_struct *dm = adapter_to_phydm(adapter);
-+	int device_constant = phydm_get_plcp(dm, sta->cmn.mac_id) << RTW_ARITH_SHIFT;
-+	u32 test_frame_len = RTW_TEST_FRAME_LEN << RTW_ARITH_SHIFT;
-+	u32 s_unit = 1 << RTW_ARITH_SHIFT;
-+	u32 err;
-+	u16 rate;
-+	u32 tx_time, estimated_retx;
-+	u64 result;
-+	/* The fail_avg should <= 100 here */
-+	u32 fail_avg = (u32)rtw_ewma_err_rate_read(&sta->metrics.err_rate);
-+
-+	if (fail_avg > RTW_LINK_FAIL_THRESH)
-+		return RTW_MAX_METRIC;
-+
-+	rate = sta->metrics.data_rate;
-+	/* rate unit is 100Kbps, min rate = 10 */
-+	if (rate < 10) {
-+		RTW_HWMP_INFO("rate = %d\n", rate);
-+		return RTW_MAX_METRIC;
-+	}
-+
-+	err = (fail_avg << RTW_ARITH_SHIFT) / 100;
-+
-+	/* test_frame_len*10 to adjust the unit of rate(100kbps/unit) */
-+	tx_time = (device_constant + 10 * test_frame_len / rate);
-+	estimated_retx = ((1 << (2 * RTW_ARITH_SHIFT)) / (s_unit - err));
-+	result = (tx_time * estimated_retx) >> (2 * RTW_ARITH_SHIFT);
-+	/* Convert us to 0.01 TU(10.24us). x/10.24 = x*100/1024 */
-+	result = (result * 100) >> 10;
-+
-+	return (u32)result;
-+}
-+
-+void rtw_ieee80211s_update_metric(_adapter *adapter, u8 mac_id,
-+				  u8 per, u8 rate,
-+				  u8 bw, u8 total_pkt)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	struct sta_info *sta;
-+	u8 rate_idx;
-+	u8 sgi;
-+
-+	sta = macid_ctl->sta[mac_id];
-+	if (!sta)
-+		return;
-+
-+	/* if RA, use reported rate */
-+	if (adapter->fix_rate == 0xff) {
-+		rate_idx = rate & 0x7f;
-+		sgi = rate >> 7;
-+	} else {
-+		rate_idx = adapter->fix_rate & 0x7f;
-+		sgi = adapter->fix_rate >> 7;
-+	}
-+	sta->metrics.data_rate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi);
-+
-+	if (total_pkt < RTW_TOTAL_PKT_MIN_THRESHOLD)
-+		return;
-+
-+	/* TBD: sta->metrics.overhead = phydm_get_plcp(void *dm_void, u16 macid); */
-+	sta->metrics.total_pkt = total_pkt;
-+
-+	rtw_ewma_err_rate_add(&sta->metrics.err_rate, per);
-+	if (rtw_ewma_err_rate_read(&sta->metrics.err_rate) > 
-+			RTW_LINK_FAIL_THRESH)
-+		rtw_mesh_plink_broken(sta);
-+}
-+
-+static void rtw_hwmp_preq_frame_process(_adapter *adapter,
-+					struct rtw_ieee80211_hdr_3addr *mgmt,
-+					const u8 *preq_elem, u32 originator_metric)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_path *path = NULL;
-+	const u8 *target_addr, *originator_addr;
-+	const u8 *da;
-+	u8 target_flags, ttl, flags, to_gate_ask = 0;
-+	u32 originator_sn, target_sn, lifetime, target_metric = 0;
-+	BOOLEAN reply = _FALSE;
-+	BOOLEAN forward = _TRUE;
-+	BOOLEAN preq_is_gate;
-+
-+	/* Update target SN, if present */
-+	target_addr = RTW_PREQ_IE_TARGET_ADDR(preq_elem);
-+	originator_addr = RTW_PREQ_IE_ORIG_ADDR(preq_elem);
-+	target_sn = RTW_PREQ_IE_TARGET_SN(preq_elem);
-+	originator_sn = RTW_PREQ_IE_ORIG_SN(preq_elem);
-+	target_flags = RTW_PREQ_IE_TARGET_F(preq_elem);
-+	/* PREQ gate announcements */
-+	flags = RTW_PREQ_IE_FLAGS(preq_elem);
-+	preq_is_gate = !!(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG);
-+
-+	RTW_HWMP_DBG("received PREQ from "MAC_FMT"\n", MAC_ARG(originator_addr));
-+
-+	if (rtw_ether_addr_equal(target_addr, adapter_mac_addr(adapter))) {
-+		RTW_HWMP_DBG("PREQ is for us\n");
-+#ifdef CONFIG_RTW_MESH_ON_DMD_GANN
-+		rtw_rcu_read_lock();
-+		path = rtw_mesh_path_lookup(adapter, originator_addr);
-+		if (path) {
-+			if (preq_is_gate)
-+				rtw_mesh_path_add_gate(path);
-+			else if (path->is_gate) {
-+				enter_critical_bh(&path->state_lock);
-+				rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
-+				exit_critical_bh(&path->state_lock);
-+			}
-+		}
-+		path = NULL;
-+		rtw_rcu_read_unlock();
-+#endif
-+		forward = _FALSE;
-+		reply = _TRUE;
-+		to_gate_ask = 1;
-+		target_metric = 0;
-+		if (rtw_time_after(rtw_get_current_time(), minfo->last_sn_update +
-+					rtw_net_traversal_jiffies(adapter)) ||
-+		    rtw_time_before(rtw_get_current_time(), minfo->last_sn_update)) {
-+			++minfo->sn;
-+			minfo->last_sn_update = rtw_get_current_time();
-+		}
-+		target_sn = minfo->sn;
-+	} else if (is_broadcast_mac_addr(target_addr) &&
-+		   (target_flags & RTW_IEEE80211_PREQ_TO_FLAG)) {
-+		rtw_rcu_read_lock();
-+		path = rtw_mesh_path_lookup(adapter, originator_addr);
-+		if (path) {
-+			if (flags & RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG) {
-+				reply = _TRUE;
-+				target_addr = adapter_mac_addr(adapter);
-+				target_sn = ++minfo->sn;
-+				target_metric = 0;
-+				minfo->last_sn_update = rtw_get_current_time();
-+			}
-+
-+			if (preq_is_gate) {
-+				lifetime = RTW_PREQ_IE_LIFETIME(preq_elem);
-+				path->gate_ann_int = lifetime;
-+				path->gate_asked = false;
-+				rtw_mesh_path_add_gate(path);
-+			} else if (path->is_gate) {
-+				enter_critical_bh(&path->state_lock);
-+				rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
-+				exit_critical_bh(&path->state_lock);
-+			}
-+		}
-+		rtw_rcu_read_unlock();
-+	} else {
-+		rtw_rcu_read_lock();
-+#ifdef CONFIG_RTW_MESH_ON_DMD_GANN
-+		path = rtw_mesh_path_lookup(adapter, originator_addr);
-+		if (path) {
-+			if (preq_is_gate)
-+				rtw_mesh_path_add_gate(path);
-+			else if (path->is_gate) {
-+				enter_critical_bh(&path->state_lock);
-+				rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
-+				exit_critical_bh(&path->state_lock);
-+			}
-+		}
-+		path = NULL;
-+#endif
-+		path = rtw_mesh_path_lookup(adapter, target_addr);
-+		if (path) {
-+			if ((!(path->flags & RTW_MESH_PATH_SN_VALID)) ||
-+					RTW_SN_LT(path->sn, target_sn)) {
-+				path->sn = target_sn;
-+				path->flags |= RTW_MESH_PATH_SN_VALID;
-+			} else if ((!(target_flags & RTW_IEEE80211_PREQ_TO_FLAG)) &&
-+					(path->flags & RTW_MESH_PATH_ACTIVE)) {
-+				reply = _TRUE;
-+				target_metric = path->metric;
-+				target_sn = path->sn;
-+				/* Case E2 of sec 13.10.9.3 IEEE 802.11-2012*/
-+				target_flags |= RTW_IEEE80211_PREQ_TO_FLAG;
-+			}
-+		}
-+		rtw_rcu_read_unlock();
-+	}
-+
-+	if (reply) {
-+		lifetime = RTW_PREQ_IE_LIFETIME(preq_elem);
-+		ttl = mshcfg->element_ttl;
-+		if (ttl != 0 && !to_gate_ask) {
-+			RTW_HWMP_DBG("replying to the PREQ\n");
-+			rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, 0, originator_addr,
-+						   originator_sn, 0, target_addr,
-+						   target_sn, mgmt->addr2, 0, ttl,
-+						   lifetime, target_metric, 0,
-+						   adapter);
-+		} else if (ttl != 0 && to_gate_ask) {
-+			RTW_HWMP_DBG("replying to the PREQ (PREQ for us)\n");
-+			if (mshcfg->dot11MeshGateAnnouncementProtocol) {
-+				/* BIT 7 is used to identify the prep is from mesh gate */
-+				to_gate_ask = RTW_IEEE80211_PREQ_IS_GATE_FLAG | BIT(7);
-+			} else {
-+				to_gate_ask = 0;
-+			}
-+
-+			rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, to_gate_ask, originator_addr,
-+						   originator_sn, 0, target_addr,
-+						   target_sn, mgmt->addr2, 0, ttl,
-+						   lifetime, target_metric, 0,
-+						   adapter);
-+		} else {
-+			minfo->mshstats.dropped_frames_ttl++;
-+		}
-+	}
-+
-+	if (forward && mshcfg->dot11MeshForwarding) {
-+		u32 preq_id;
-+		u8 hopcount;
-+
-+		ttl = RTW_PREQ_IE_TTL(preq_elem);
-+		lifetime = RTW_PREQ_IE_LIFETIME(preq_elem);
-+		if (ttl <= 1) {
-+			minfo->mshstats.dropped_frames_ttl++;
-+			return;
-+		}
-+		RTW_HWMP_DBG("forwarding the PREQ from "MAC_FMT"\n", MAC_ARG(originator_addr));
-+		--ttl;
-+		preq_id = RTW_PREQ_IE_PREQ_ID(preq_elem);
-+		hopcount = RTW_PREQ_IE_HOPCOUNT(preq_elem) + 1;
-+		da = (path && path->is_root) ?
-+			path->rann_snd_addr : bcast_addr;
-+
-+		if (flags & RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG) {
-+			target_addr = RTW_PREQ_IE_TARGET_ADDR(preq_elem);
-+			target_sn = RTW_PREQ_IE_TARGET_SN(preq_elem);
-+		}
-+
-+		rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, originator_addr,
-+					   originator_sn, target_flags, target_addr,
-+					   target_sn, da, hopcount, ttl, lifetime,
-+					   originator_metric, preq_id, adapter);
-+		if (!is_multicast_mac_addr(da))
-+			minfo->mshstats.fwded_unicast++;
-+		else
-+			minfo->mshstats.fwded_mcast++;
-+		minfo->mshstats.fwded_frames++;
-+	}
-+}
-+
-+static inline struct sta_info *
-+rtw_next_hop_deref_protected(struct rtw_mesh_path *path)
-+{
-+	return rtw_rcu_dereference_protected(path->next_hop,
-+					 rtw_lockdep_is_held(&path->state_lock));
-+}
-+
-+static void rtw_hwmp_prep_frame_process(_adapter *adapter,
-+					struct rtw_ieee80211_hdr_3addr *mgmt,
-+					const u8 *prep_elem, u32 metric)
-+{
-+	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;
-+	struct rtw_mesh_path *path;
-+	const u8 *target_addr, *originator_addr;
-+	u8 ttl, hopcount, flags;
-+	u8 next_hop[ETH_ALEN];
-+	u32 target_sn, originator_sn, lifetime;
-+
-+	RTW_HWMP_DBG("received PREP from "MAC_FMT"\n",
-+		  MAC_ARG(RTW_PREP_IE_TARGET_ADDR(prep_elem)));
-+
-+	originator_addr = RTW_PREP_IE_ORIG_ADDR(prep_elem);
-+	if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) {
-+		/* destination, no forwarding required */
-+		rtw_rcu_read_lock();
-+		target_addr = RTW_PREP_IE_TARGET_ADDR(prep_elem);
-+		path = rtw_mesh_path_lookup(adapter, target_addr);
-+		if (path && path->gate_asked) {
-+			flags = RTW_PREP_IE_FLAGS(prep_elem);
-+			if (flags & BIT(7)) {
-+				enter_critical_bh(&path->state_lock);
-+				path->gate_asked = false;
-+				exit_critical_bh(&path->state_lock);
-+				if (!(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG)) {
-+					enter_critical_bh(&path->state_lock);
-+					rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
-+					exit_critical_bh(&path->state_lock);
-+				}
-+			}
-+		}
-+
-+		rtw_rcu_read_unlock();
-+		return;
-+	}
-+
-+	if (!mshcfg->dot11MeshForwarding)
-+		return;
-+
-+	ttl = RTW_PREP_IE_TTL(prep_elem);
-+	if (ttl <= 1) {
-+		mshstats->dropped_frames_ttl++;
-+		return;
-+	}
-+
-+	rtw_rcu_read_lock();
-+	path = rtw_mesh_path_lookup(adapter, originator_addr);
-+	if (path)
-+		enter_critical_bh(&path->state_lock);
-+	else
-+		goto fail;
-+	if (!(path->flags & RTW_MESH_PATH_ACTIVE)) {
-+		exit_critical_bh(&path->state_lock);
-+		goto fail;
-+	}
-+	_rtw_memcpy(next_hop, rtw_next_hop_deref_protected(path)->cmn.mac_addr, ETH_ALEN);
-+	exit_critical_bh(&path->state_lock);
-+	--ttl;
-+	flags = RTW_PREP_IE_FLAGS(prep_elem);
-+	lifetime = RTW_PREP_IE_LIFETIME(prep_elem);
-+	hopcount = RTW_PREP_IE_HOPCOUNT(prep_elem) + 1;
-+	target_addr = RTW_PREP_IE_TARGET_ADDR(prep_elem);
-+	target_sn = RTW_PREP_IE_TARGET_SN(prep_elem);
-+	originator_sn = RTW_PREP_IE_ORIG_SN(prep_elem);
-+
-+	rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, flags, originator_addr, originator_sn, 0,
-+				   target_addr, target_sn, next_hop, hopcount,
-+				   ttl, lifetime, metric, 0, adapter);
-+	rtw_rcu_read_unlock();
-+
-+	mshstats->fwded_unicast++;
-+	mshstats->fwded_frames++;
-+	return;
-+
-+fail:
-+	rtw_rcu_read_unlock();
-+	mshstats->dropped_frames_no_route++;
-+}
-+
-+static void rtw_hwmp_perr_frame_process(_adapter *adapter,
-+					struct rtw_ieee80211_hdr_3addr *mgmt,
-+					const u8 *perr_elem)
-+{
-+	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;
-+	struct rtw_mesh_path *path;
-+	u8 ttl;
-+	const u8 *ta, *target_addr;
-+	u32 target_sn;
-+	u16 perr_reason_code;
-+
-+	ta = mgmt->addr2;
-+	ttl = RTW_PERR_IE_TTL(perr_elem);
-+	if (ttl <= 1) {
-+		mshstats->dropped_frames_ttl++;
-+		return;
-+	}
-+	ttl--;
-+	target_addr = RTW_PERR_IE_TARGET_ADDR(perr_elem);
-+	target_sn = RTW_PERR_IE_TARGET_SN(perr_elem);
-+	perr_reason_code = RTW_PERR_IE_TARGET_RCODE(perr_elem);
-+
-+	RTW_HWMP_DBG("received PERR toward target "MAC_FMT"\n", MAC_ARG(target_addr));
-+
-+	rtw_rcu_read_lock();
-+	path = rtw_mesh_path_lookup(adapter, target_addr);
-+	if (path) {
-+		struct sta_info *sta;
-+
-+		enter_critical_bh(&path->state_lock);
-+		sta = rtw_next_hop_deref_protected(path);
-+		if (path->flags & RTW_MESH_PATH_ACTIVE &&
-+		    rtw_ether_addr_equal(ta, sta->cmn.mac_addr) &&
-+		    !(path->flags & RTW_MESH_PATH_FIXED) &&
-+		    (!(path->flags & RTW_MESH_PATH_SN_VALID) ||
-+		    RTW_SN_GT(target_sn, path->sn)  || target_sn == 0)) {
-+			path->flags &= ~RTW_MESH_PATH_ACTIVE;
-+			if (target_sn != 0)
-+				path->sn = target_sn;
-+			else
-+				path->sn += 1;
-+			exit_critical_bh(&path->state_lock);
-+			if (!mshcfg->dot11MeshForwarding)
-+				goto endperr;
-+			rtw_mesh_path_error_tx(adapter, ttl, target_addr,
-+					       target_sn, perr_reason_code,
-+					       bcast_addr);
-+		} else
-+			exit_critical_bh(&path->state_lock);
-+	}
-+endperr:
-+	rtw_rcu_read_unlock();
-+}
-+
-+static void rtw_hwmp_rann_frame_process(_adapter *adapter,
-+					struct rtw_ieee80211_hdr_3addr *mgmt,
-+					const struct rtw_ieee80211_rann_ie *rann)
-+{
-+	struct sta_info *sta;
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;
-+	struct rtw_mesh_path *path;
-+	u8 ttl, flags, hopcount;
-+	const u8 *originator_addr;
-+	u32 originator_sn, metric, metric_txsta, interval;
-+	BOOLEAN root_is_gate;
-+
-+	ttl = rann->rann_ttl;
-+	flags = rann->rann_flags;
-+	root_is_gate = !!(flags & RTW_RANN_FLAG_IS_GATE);
-+	originator_addr = rann->rann_addr;
-+	originator_sn = le32_to_cpu(rann->rann_seq);
-+	interval = le32_to_cpu(rann->rann_interval);
-+	hopcount = rann->rann_hopcount;
-+	hopcount++;
-+	metric = le32_to_cpu(rann->rann_metric);
-+
-+	/*  Ignore our own RANNs */
-+	if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter)))
-+		return;
-+
-+	RTW_HWMP_DBG("received RANN from "MAC_FMT" via neighbour "MAC_FMT" (is_gate=%d)\n",
-+		  MAC_ARG(originator_addr), MAC_ARG(mgmt->addr2), root_is_gate);
-+
-+	rtw_rcu_read_lock();
-+	sta = rtw_get_stainfo(pstapriv, mgmt->addr2);
-+	if (!sta) {
-+		rtw_rcu_read_unlock();
-+		return;
-+	}
-+
-+	metric_txsta = rtw_airtime_link_metric_get(adapter, sta);
-+
-+	path = rtw_mesh_path_lookup(adapter, originator_addr);
-+	if (!path) {
-+		path = rtw_mesh_path_add(adapter, originator_addr);
-+		if (IS_ERR(path)) {
-+			rtw_rcu_read_unlock();
-+			mshstats->dropped_frames_no_route++;
-+			return;
-+		}
-+	}
-+
-+	if (!(RTW_SN_LT(path->sn, originator_sn)) &&
-+	    !(path->sn == originator_sn && metric < path->rann_metric)) {
-+		rtw_rcu_read_unlock();
-+		return;
-+	}
-+
-+	if ((!(path->flags & (RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVING)) ||
-+	     (rtw_time_after(rtw_get_current_time(), path->last_preq_to_root +
-+				  rtw_root_path_confirmation_jiffies(adapter)) ||
-+	     rtw_time_before(rtw_get_current_time(), path->last_preq_to_root))) &&
-+	     !(path->flags & RTW_MESH_PATH_FIXED) && (ttl != 0)) {
-+		u8 preq_node_flag = RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH;
-+
-+		RTW_HWMP_DBG("time to refresh root path "MAC_FMT"\n",
-+			  MAC_ARG(originator_addr));
-+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
-+		if (RTW_SN_LT(path->sn, originator_sn) &&
-+		    (path->rann_metric + mshcfg->sane_metric_delta < metric) &&
-+		    _rtw_memcmp(bcast_addr, path->rann_snd_addr, ETH_ALEN) == _FALSE) {
-+			RTW_HWMP_DBG("Trigger additional check for root "
-+				     "confirm PREQ. rann_snd_addr = "MAC_FMT
-+				     "add_chk_rann_snd_addr= "MAC_FMT"\n",
-+					MAC_ARG(mgmt->addr2),
-+					MAC_ARG(path->rann_snd_addr));
-+			_rtw_memcpy(path->add_chk_rann_snd_addr,
-+				    path->rann_snd_addr, ETH_ALEN);
-+			preq_node_flag |= RTW_PREQ_Q_F_CHK;
-+			
-+		}
-+#endif
-+		rtw_mesh_queue_preq(path, preq_node_flag);
-+		path->last_preq_to_root = rtw_get_current_time();
-+	}
-+
-+	path->sn = originator_sn;
-+	path->rann_metric = metric + metric_txsta;
-+	path->is_root = _TRUE;
-+	/* Recording RANNs sender address to send individually
-+	 * addressed PREQs destined for root mesh STA */
-+	_rtw_memcpy(path->rann_snd_addr, mgmt->addr2, ETH_ALEN);
-+
-+	if (root_is_gate) {
-+		path->gate_ann_int = interval;
-+		path->gate_asked = false;
-+		rtw_mesh_path_add_gate(path);
-+	} else if (path->is_gate) {
-+		enter_critical_bh(&path->state_lock);
-+		rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
-+		exit_critical_bh(&path->state_lock);
-+	}
-+
-+	if (ttl <= 1) {
-+		mshstats->dropped_frames_ttl++;
-+		rtw_rcu_read_unlock();
-+		return;
-+	}
-+	ttl--;
-+
-+	if (mshcfg->dot11MeshForwarding) {
-+		rtw_mesh_path_sel_frame_tx(RTW_MPATH_RANN, flags, originator_addr,
-+					   originator_sn, 0, NULL, 0, bcast_addr,
-+					   hopcount, ttl, interval,
-+					   metric + metric_txsta, 0, adapter);
-+	}
-+
-+	rtw_rcu_read_unlock();
-+}
-+
-+static u32 rtw_hwmp_route_info_get(_adapter *adapter,
-+				   struct rtw_ieee80211_hdr_3addr *mgmt,
-+				   const u8 *hwmp_ie, enum rtw_mpath_frame_type action)
-+{
-+	struct rtw_mesh_path *path;
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+	struct sta_info *sta;
-+	BOOLEAN fresh_info;
-+	const u8 *originator_addr, *ta;
-+	u32 originator_sn, originator_metric;
-+	unsigned long originator_lifetime, exp_time;
-+	u32 last_hop_metric, new_metric;
-+	BOOLEAN process = _TRUE;
-+
-+	rtw_rcu_read_lock();
-+	sta = rtw_get_stainfo(pstapriv, mgmt->addr2);
-+	if (!sta) {
-+		rtw_rcu_read_unlock();
-+		return 0;
-+	}
-+
-+	last_hop_metric = rtw_airtime_link_metric_get(adapter, sta);
-+	/* Update and check originator routing info */
-+	fresh_info = _TRUE;
-+
-+	switch (action) {
-+	case RTW_MPATH_PREQ:
-+		originator_addr = RTW_PREQ_IE_ORIG_ADDR(hwmp_ie);
-+		originator_sn = RTW_PREQ_IE_ORIG_SN(hwmp_ie);
-+		originator_lifetime = RTW_PREQ_IE_LIFETIME(hwmp_ie);
-+		originator_metric = RTW_PREQ_IE_METRIC(hwmp_ie);
-+		break;
-+	case RTW_MPATH_PREP:
-+		/* Note: For coding, the naming is not consist with spec */
-+		originator_addr = RTW_PREP_IE_TARGET_ADDR(hwmp_ie);
-+		originator_sn = RTW_PREP_IE_TARGET_SN(hwmp_ie);
-+		originator_lifetime = RTW_PREP_IE_LIFETIME(hwmp_ie);
-+		originator_metric = RTW_PREP_IE_METRIC(hwmp_ie);
-+		break;
-+	default:
-+		rtw_rcu_read_unlock();
-+		return 0;
-+	}
-+	new_metric = originator_metric + last_hop_metric;
-+	if (new_metric < originator_metric)
-+		new_metric = RTW_MAX_METRIC;
-+	exp_time = RTW_TU_TO_EXP_TIME(originator_lifetime);
-+
-+	if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) {
-+		process = _FALSE;
-+		fresh_info = _FALSE;
-+	} else {
-+		path = rtw_mesh_path_lookup(adapter, originator_addr);
-+		if (path) {
-+			enter_critical_bh(&path->state_lock);
-+			if (path->flags & RTW_MESH_PATH_FIXED)
-+				fresh_info = _FALSE;
-+			else if ((path->flags & RTW_MESH_PATH_ACTIVE) &&
-+			    (path->flags & RTW_MESH_PATH_SN_VALID)) {
-+				if (RTW_SN_GT(path->sn, originator_sn) ||
-+				    (path->sn == originator_sn &&
-+				     new_metric >= path->metric)) {
-+					process = _FALSE;
-+					fresh_info = _FALSE;
-+				}
-+			} else if (!(path->flags & RTW_MESH_PATH_ACTIVE)) {
-+				BOOLEAN have_sn, newer_sn, bounced;
-+
-+				have_sn = path->flags & RTW_MESH_PATH_SN_VALID;
-+				newer_sn = have_sn && RTW_SN_GT(originator_sn, path->sn);
-+				bounced = have_sn &&
-+					  (RTW_SN_DELTA(originator_sn, path->sn) >
-+							RTW_MAX_SANE_SN_DELTA);
-+
-+				if (!have_sn || newer_sn) {
-+				} else if (bounced) {
-+				} else {
-+					process = _FALSE;
-+					fresh_info = _FALSE;
-+				}
-+			}
-+		} else {
-+			path = rtw_mesh_path_add(adapter, originator_addr);
-+			if (IS_ERR(path)) {
-+				rtw_rcu_read_unlock();
-+				return 0;
-+			}
-+			enter_critical_bh(&path->state_lock);
-+		}
-+
-+		if (fresh_info) {
-+			rtw_mesh_path_assign_nexthop(path, sta);
-+			path->flags |= RTW_MESH_PATH_SN_VALID;
-+			path->metric = new_metric;
-+			path->sn = originator_sn;
-+			path->exp_time = rtw_time_after(path->exp_time, exp_time)
-+					  ?  path->exp_time : exp_time;
-+			rtw_mesh_path_activate(path);
-+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
-+			if (path->is_root && (action == RTW_MPATH_PREP)) {
-+				_rtw_memcpy(path->rann_snd_addr, 
-+				mgmt->addr2, ETH_ALEN);
-+				path->rann_metric = new_metric;
-+			}
-+#endif
-+			exit_critical_bh(&path->state_lock);
-+			rtw_mesh_path_tx_pending(path);
-+		} else
-+			exit_critical_bh(&path->state_lock);
-+	}
-+
-+	/* Update and check transmitter routing info */
-+	ta = mgmt->addr2;
-+	if (rtw_ether_addr_equal(originator_addr, ta))
-+		fresh_info = _FALSE;
-+	else {
-+		fresh_info = _TRUE;
-+
-+		path = rtw_mesh_path_lookup(adapter, ta);
-+		if (path) {
-+			enter_critical_bh(&path->state_lock);
-+			if ((path->flags & RTW_MESH_PATH_FIXED) ||
-+				((path->flags & RTW_MESH_PATH_ACTIVE) &&
-+					(last_hop_metric > path->metric)))
-+				fresh_info = _FALSE;
-+		} else {
-+			path = rtw_mesh_path_add(adapter, ta);
-+			if (IS_ERR(path)) {
-+				rtw_rcu_read_unlock();
-+				return 0;
-+			}
-+			enter_critical_bh(&path->state_lock);
-+		}
-+
-+		if (fresh_info) {
-+			rtw_mesh_path_assign_nexthop(path, sta);
-+			path->metric = last_hop_metric;
-+			path->exp_time = rtw_time_after(path->exp_time, exp_time)
-+					  ?  path->exp_time : exp_time;
-+			rtw_mesh_path_activate(path);
-+			exit_critical_bh(&path->state_lock);
-+			rtw_mesh_path_tx_pending(path);
-+		} else
-+			exit_critical_bh(&path->state_lock);
-+	}
-+
-+	rtw_rcu_read_unlock();
-+
-+	return process ? new_metric : 0;
-+}
-+
-+static void rtw_mesh_rx_hwmp_frame_cnts(_adapter *adapter, u8 *addr)
-+{
-+	struct sta_info *sta;
-+
-+	sta = rtw_get_stainfo(&adapter->stapriv, addr);
-+	if (sta)
-+		sta->sta_stats.rx_hwmp_pkts++;
-+}
-+
-+void rtw_mesh_rx_path_sel_frame(_adapter *adapter, union recv_frame *rframe)
-+{
-+	struct mesh_plink_ent *plink = NULL;
-+	struct rtw_ieee802_11_elems elems;
-+	u32 path_metric;
-+	struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;
-+	u8 *pframe = rframe->u.hdr.rx_data, *start;
-+	uint frame_len = rframe->u.hdr.len, left;
-+	struct rtw_ieee80211_hdr_3addr *frame_hdr = (struct rtw_ieee80211_hdr_3addr *)pframe;
-+	u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
-+	ParseRes parse_res;
-+
-+	plink = rtw_mesh_plink_get(adapter, get_addr2_ptr(pframe));
-+	if (!plink || plink->plink_state != RTW_MESH_PLINK_ESTAB)
-+		return;
-+
-+	rtw_mesh_rx_hwmp_frame_cnts(adapter, get_addr2_ptr(pframe));
-+
-+	/* Mesh action frame IE offset = 2 */
-+	attrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+	left = frame_len - attrib->hdrlen - attrib->iv_len - attrib->icv_len - 2;
-+	start = pframe + attrib->hdrlen + 2;
-+
-+	parse_res = rtw_ieee802_11_parse_elems(start, left, &elems, 1);
-+	if (parse_res == ParseFailed)
-+		RTW_HWMP_INFO(FUNC_ADPT_FMT" Path Select Frame ParseFailed\n"
-+			, FUNC_ADPT_ARG(adapter));
-+	else if (parse_res == ParseUnknown)
-+		RTW_HWMP_INFO(FUNC_ADPT_FMT" Path Select Frame ParseUnknown\n"
-+			, FUNC_ADPT_ARG(adapter));
-+
-+	if (elems.preq) {
-+		if (elems.preq_len != 37)
-+			/* Right now we support just 1 destination and no AE */
-+			return;
-+		path_metric = rtw_hwmp_route_info_get(adapter, frame_hdr, elems.preq,
-+						  MPATH_PREQ);
-+		if (path_metric)
-+			rtw_hwmp_preq_frame_process(adapter, frame_hdr, elems.preq,
-+						path_metric);
-+	}
-+	if (elems.prep) {
-+		if (elems.prep_len != 31)
-+			/* Right now we support no AE */
-+			return;
-+		path_metric = rtw_hwmp_route_info_get(adapter, frame_hdr, elems.prep,
-+						  MPATH_PREP);
-+		if (path_metric)
-+			rtw_hwmp_prep_frame_process(adapter, frame_hdr, elems.prep,
-+						path_metric);
-+	}
-+	if (elems.perr) {
-+		if (elems.perr_len != 15)
-+			/* Right now we support only one destination per PERR */
-+			return;
-+		rtw_hwmp_perr_frame_process(adapter, frame_hdr, elems.perr);
-+	}
-+	if (elems.rann)
-+		rtw_hwmp_rann_frame_process(adapter, frame_hdr, (struct rtw_ieee80211_rann_ie *)elems.rann);
-+}
-+
-+void rtw_mesh_queue_preq(struct rtw_mesh_path *path, u8 flags)
-+{
-+	_adapter *adapter = path->adapter;
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct rtw_mesh_preq_queue *preq_node;
-+
-+	preq_node = rtw_malloc(sizeof(struct rtw_mesh_preq_queue));
-+	if (!preq_node) {
-+		RTW_HWMP_INFO("could not allocate PREQ node\n");
-+		return;
-+	}
-+
-+	enter_critical_bh(&minfo->mesh_preq_queue_lock);
-+	if (minfo->preq_queue_len == RTW_MAX_PREQ_QUEUE_LEN) {
-+		exit_critical_bh(&minfo->mesh_preq_queue_lock);
-+		rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));
-+		if (rtw_print_ratelimit())
-+			RTW_HWMP_INFO("PREQ node queue full\n");
-+		return;
-+	}
-+
-+	_rtw_spinlock(&path->state_lock);
-+	if (path->flags & RTW_MESH_PATH_REQ_QUEUED) {
-+		_rtw_spinunlock(&path->state_lock);
-+		exit_critical_bh(&minfo->mesh_preq_queue_lock);
-+		rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));
-+		return;
-+	}
-+
-+	_rtw_memcpy(preq_node->dst, path->dst, ETH_ALEN);
-+	preq_node->flags = flags;
-+
-+	path->flags |= RTW_MESH_PATH_REQ_QUEUED;
-+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
-+	if (flags & RTW_PREQ_Q_F_CHK)
-+		path->flags |= RTW_MESH_PATH_ROOT_ADD_CHK;
-+#endif
-+	if (flags & RTW_PREQ_Q_F_PEER_AKA)
-+		path->flags |= RTW_MESH_PATH_PEER_AKA;
-+	if (flags & RTW_PREQ_Q_F_BCAST_PREQ)
-+		path->flags |= RTW_MESH_PATH_BCAST_PREQ;
-+	_rtw_spinunlock(&path->state_lock);
-+
-+	rtw_list_insert_tail(&preq_node->list, &minfo->preq_queue.list);
-+	++minfo->preq_queue_len;
-+	exit_critical_bh(&minfo->mesh_preq_queue_lock);
-+
-+	if (rtw_time_after(rtw_get_current_time(), minfo->last_preq + rtw_min_preq_int_jiff(adapter)))
-+		rtw_mesh_work(&adapter->mesh_work);
-+
-+	else if (rtw_time_before(rtw_get_current_time(), minfo->last_preq)) {
-+		/* systime wrapped around issue */
-+		minfo->last_preq = rtw_get_current_time() - rtw_min_preq_int_jiff(adapter) - 1;
-+		rtw_mesh_work(&adapter->mesh_work);
-+	} else
-+		rtw_mod_timer(&adapter->mesh_path_timer, minfo->last_preq +
-+					rtw_min_preq_int_jiff(adapter) + 1);
-+}
-+
-+static const u8 *rtw_hwmp_preq_da(struct rtw_mesh_path *path,
-+			    BOOLEAN is_root_add_chk, BOOLEAN da_is_peer,
-+			    BOOLEAN force_preq_bcast)
-+{
-+	const u8 *da;
-+
-+	if (da_is_peer)
-+		da = path->dst;
-+	else if (force_preq_bcast)
-+		da = bcast_addr;
-+	else if (path->is_root)
-+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
-+		da = is_root_add_chk ? path->add_chk_rann_snd_addr:
-+				       path->rann_snd_addr;
-+#else
-+		da = path->rann_snd_addr;
-+#endif
-+	else
-+		da = bcast_addr;
-+
-+	return da;
-+}
-+
-+void rtw_mesh_path_start_discovery(_adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_preq_queue *preq_node;
-+	struct rtw_mesh_path *path;
-+	u8 ttl, target_flags = 0;
-+	const u8 *da;
-+	u32 lifetime;
-+	u8 flags = 0;
-+	BOOLEAN is_root_add_chk = _FALSE;
-+	BOOLEAN da_is_peer, force_preq_bcast;
-+
-+	enter_critical_bh(&minfo->mesh_preq_queue_lock);
-+	if (!minfo->preq_queue_len ||
-+		rtw_time_before(rtw_get_current_time(), minfo->last_preq +
-+				rtw_min_preq_int_jiff(adapter))) {
-+		exit_critical_bh(&minfo->mesh_preq_queue_lock);
-+		return;
-+	}
-+
-+	preq_node = rtw_list_first_entry(&minfo->preq_queue.list,
-+			struct rtw_mesh_preq_queue, list);
-+	rtw_list_delete(&preq_node->list); /* list_del_init(&preq_node->list); */
-+	--minfo->preq_queue_len;
-+	exit_critical_bh(&minfo->mesh_preq_queue_lock);
-+
-+	rtw_rcu_read_lock();
-+	path = rtw_mesh_path_lookup(adapter, preq_node->dst);
-+	if (!path)
-+		goto enddiscovery;
-+
-+	enter_critical_bh(&path->state_lock);
-+	if (path->flags & (RTW_MESH_PATH_DELETED | RTW_MESH_PATH_FIXED)) {
-+		exit_critical_bh(&path->state_lock);
-+		goto enddiscovery;
-+	}
-+	path->flags &= ~RTW_MESH_PATH_REQ_QUEUED;
-+	if (preq_node->flags & RTW_PREQ_Q_F_START) {
-+		if (path->flags & RTW_MESH_PATH_RESOLVING) {
-+			exit_critical_bh(&path->state_lock);
-+			goto enddiscovery;
-+		} else {
-+			path->flags &= ~RTW_MESH_PATH_RESOLVED;
-+			path->flags |= RTW_MESH_PATH_RESOLVING;
-+			path->discovery_retries = 0;
-+			path->discovery_timeout = rtw_disc_timeout_jiff(adapter);
-+		}
-+	} else if (!(path->flags & RTW_MESH_PATH_RESOLVING) ||
-+			path->flags & RTW_MESH_PATH_RESOLVED) {
-+		path->flags &= ~RTW_MESH_PATH_RESOLVING;
-+		exit_critical_bh(&path->state_lock);
-+		goto enddiscovery;
-+	}
-+
-+	minfo->last_preq = rtw_get_current_time();
-+
-+	if (rtw_time_after(rtw_get_current_time(), minfo->last_sn_update +
-+				rtw_net_traversal_jiffies(adapter)) ||
-+	    rtw_time_before(rtw_get_current_time(), minfo->last_sn_update)) {
-+		++minfo->sn;
-+		minfo->last_sn_update = rtw_get_current_time();
-+	}
-+	lifetime = rtw_default_lifetime(adapter);
-+	ttl = mshcfg->element_ttl;
-+	if (ttl == 0) {
-+		minfo->mshstats.dropped_frames_ttl++;
-+		exit_critical_bh(&path->state_lock);
-+		goto enddiscovery;
-+	}
-+
-+	if (preq_node->flags & RTW_PREQ_Q_F_REFRESH)
-+		target_flags |= RTW_IEEE80211_PREQ_TO_FLAG;
-+	else
-+		target_flags &= ~RTW_IEEE80211_PREQ_TO_FLAG;
-+
-+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
-+	is_root_add_chk = !!(path->flags & RTW_MESH_PATH_ROOT_ADD_CHK);
-+#endif
-+	da_is_peer = !!(path->flags & RTW_MESH_PATH_PEER_AKA);
-+	force_preq_bcast = !!(path->flags & RTW_MESH_PATH_BCAST_PREQ);
-+	exit_critical_bh(&path->state_lock);
-+
-+	da = rtw_hwmp_preq_da(path, is_root_add_chk,
-+			      da_is_peer, force_preq_bcast);
-+
-+#ifdef CONFIG_RTW_MESH_ON_DMD_GANN
-+	flags = (mshcfg->dot11MeshGateAnnouncementProtocol)
-+		? RTW_IEEE80211_PREQ_IS_GATE_FLAG : 0;
-+#endif
-+	rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, adapter_mac_addr(adapter), minfo->sn,
-+				   target_flags, path->dst, path->sn, da, 0,
-+				   ttl, lifetime, 0, minfo->preq_id++, adapter);
-+	rtw_mod_timer(&path->timer, rtw_get_current_time() + path->discovery_timeout);
-+
-+enddiscovery:
-+	rtw_rcu_read_unlock();
-+	rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));
-+}
-+
-+void rtw_mesh_path_timer(void *ctx)
-+{
-+	struct rtw_mesh_path *path = (void *) ctx;
-+	_adapter *adapter = path->adapter;
-+	int ret;
-+	u8 retry = 0;
-+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
-+	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
-+#endif
-+	/* TBD: Proctect for suspend */
-+#if 0
-+	if (suspending)
-+		return;
-+#endif
-+	enter_critical_bh(&path->state_lock);
-+	if (path->flags & RTW_MESH_PATH_RESOLVED ||
-+			(!(path->flags & RTW_MESH_PATH_RESOLVING))) {
-+		path->flags &= ~(RTW_MESH_PATH_RESOLVING |
-+				 RTW_MESH_PATH_RESOLVED |
-+				 RTW_MESH_PATH_ROOT_ADD_CHK |
-+				 RTW_MESH_PATH_PEER_AKA |
-+				 RTW_MESH_PATH_BCAST_PREQ);
-+		exit_critical_bh(&path->state_lock);
-+	} else if (path->discovery_retries < rtw_max_preq_retries(adapter)) {
-+		++path->discovery_retries;
-+		path->discovery_timeout *= 2;
-+		path->flags &= ~RTW_MESH_PATH_REQ_QUEUED;
-+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
-+		if (path->discovery_retries > mshcfg->max_root_add_chk_cnt)
-+			path->flags &= ~RTW_MESH_PATH_ROOT_ADD_CHK;
-+#endif
-+		if (path->gate_asked)
-+			retry |= RTW_PREQ_Q_F_REFRESH;
-+
-+		exit_critical_bh(&path->state_lock);
-+		rtw_mesh_queue_preq(path, retry);
-+	} else {
-+		path->flags &= ~(RTW_MESH_PATH_RESOLVING |
-+				  RTW_MESH_PATH_RESOLVED |
-+				  RTW_MESH_PATH_REQ_QUEUED |
-+				  RTW_MESH_PATH_ROOT_ADD_CHK |
-+				  RTW_MESH_PATH_PEER_AKA |
-+				  RTW_MESH_PATH_BCAST_PREQ);
-+		path->exp_time = rtw_get_current_time();
-+		exit_critical_bh(&path->state_lock);
-+		if (!path->is_gate && rtw_mesh_gate_num(adapter) > 0) {
-+			ret = rtw_mesh_path_send_to_gates(path);
-+			if (ret)
-+				RTW_HWMP_DBG("no gate was reachable\n");
-+		} else
-+			rtw_mesh_path_flush_pending(path);
-+	}
-+}
-+
-+
-+void rtw_mesh_path_tx_root_frame(_adapter *adapter)
-+{
-+	struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	u32 interval = mshcfg->dot11MeshHWMPRannInterval;
-+	u8 flags, target_flags = 0;
-+
-+	flags = (mshcfg->dot11MeshGateAnnouncementProtocol)
-+			? RTW_RANN_FLAG_IS_GATE : 0;
-+
-+	switch (mshcfg->dot11MeshHWMPRootMode) {
-+	case RTW_IEEE80211_PROACTIVE_RANN:
-+		rtw_mesh_path_sel_frame_tx(RTW_MPATH_RANN, flags, adapter_mac_addr(adapter),
-+					   ++minfo->sn, 0, NULL, 0, bcast_addr,
-+					   0, mshcfg->element_ttl,
-+					   interval, 0, 0, adapter);
-+		break;
-+	case RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP:
-+		flags |= RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG;
-+	case RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP:
-+		interval = mshcfg->dot11MeshHWMPactivePathToRootTimeout;
-+		target_flags |= RTW_IEEE80211_PREQ_TO_FLAG |
-+				RTW_IEEE80211_PREQ_USN_FLAG;
-+		rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, adapter_mac_addr(adapter),
-+					   ++minfo->sn, target_flags,
-+					   (u8 *) bcast_addr, 0, bcast_addr,
-+					   0, mshcfg->element_ttl, interval,
-+					   0, minfo->preq_id++, adapter);
-+		break;
-+	default:
-+		RTW_HWMP_INFO("Proactive mechanism not supported\n");
-+		return;
-+	}
-+}
-+
-+void rtw_mesh_work(_workitem *work)
-+{
-+	/* use kernel global workqueue */
-+	_set_workitem(work);
-+}
-+
-+void rtw_ieee80211_mesh_path_timer(void *ctx)
-+{
-+	_adapter *adapter = (_adapter *)ctx;
-+	rtw_mesh_work(&adapter->mesh_work);
-+}
-+
-+void rtw_ieee80211_mesh_path_root_timer(void *ctx)
-+{
-+	_adapter *adapter = (_adapter *)ctx;
-+
-+	rtw_set_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);
-+
-+	rtw_mesh_work(&adapter->mesh_work);
-+}
-+
-+static void rtw_ieee80211_mesh_rootpath(_adapter *adapter)
-+{
-+	u32 interval;
-+
-+	rtw_mesh_path_tx_root_frame(adapter);
-+
-+	if (adapter->mesh_cfg.dot11MeshHWMPRootMode == RTW_IEEE80211_PROACTIVE_RANN)
-+		interval = adapter->mesh_cfg.dot11MeshHWMPRannInterval;
-+	else
-+		interval = adapter->mesh_cfg.dot11MeshHWMProotInterval;
-+
-+	rtw_mod_timer(&adapter->mesh_path_root_timer,
-+		  RTW_TU_TO_EXP_TIME(interval));
-+}
-+
-+BOOLEAN rtw_ieee80211_mesh_root_setup(_adapter *adapter)
-+{
-+	BOOLEAN root_enabled = _FALSE;
-+
-+	if (adapter->mesh_cfg.dot11MeshHWMPRootMode > RTW_IEEE80211_ROOTMODE_ROOT) {
-+		rtw_set_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);
-+		root_enabled = _TRUE;
-+	}
-+	else {
-+		rtw_clear_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);
-+		/* stop running timer */
-+		_cancel_timer_ex(&adapter->mesh_path_root_timer);
-+		root_enabled = _FALSE;
-+	}
-+
-+	return root_enabled;
-+}
-+
-+void rtw_mesh_work_hdl(_workitem *work)
-+{
-+	_adapter *adapter = container_of(work, _adapter, mesh_work);
-+
-+	while(adapter->mesh_info.preq_queue_len) {
-+		if (rtw_time_after(rtw_get_current_time(),
-+		       adapter->mesh_info.last_preq + rtw_min_preq_int_jiff(adapter)))
-+		       /* It will consume preq_queue_len */
-+		       rtw_mesh_path_start_discovery(adapter);
-+		else {
-+			struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+
-+			rtw_mod_timer(&adapter->mesh_path_timer,
-+				minfo->last_preq + rtw_min_preq_int_jiff(adapter) + 1);
-+			break;
-+		}
-+	}
-+
-+	if (rtw_test_and_clear_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags))
-+		rtw_ieee80211_mesh_rootpath(adapter);
-+}
-+
-+#ifndef RTW_PER_CMD_SUPPORT_FW
-+static void rtw_update_metric_directly(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	u8 i;
-+
-+	for (i = 0; i < macid_ctl->num; i++) {
-+		u8 role;
-+		role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]);
-+		if (role == H2C_MSR_ROLE_MESH) {
-+			struct sta_info *sta = macid_ctl->sta[i];
-+			u8 rate_idx, sgi, bw;
-+			u32 rate;
-+
-+			if (!sta)
-+				continue;
-+			rate_idx = rtw_get_current_tx_rate(adapter, sta);
-+			sgi = rtw_get_current_tx_sgi(adapter, sta);
-+			bw = sta->cmn.bw_mode;
-+			rate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi);
-+			sta->metrics.data_rate = rate;
-+		}
-+	}
-+}
-+#endif
-+
-+void rtw_mesh_atlm_param_req_timer(void *ctx)
-+{
-+	_adapter *adapter = (_adapter *)ctx;
-+	u8 ret = _FAIL;
-+
-+#ifdef RTW_PER_CMD_SUPPORT_FW
-+	ret = rtw_req_per_cmd(adapter);
-+	if (ret == _FAIL)
-+		RTW_HWMP_INFO("rtw_req_per_cmd fail\n");
-+#else
-+	rtw_update_metric_directly(adapter);
-+#endif
-+	_set_timer(&adapter->mesh_atlm_param_req_timer, RTW_ATLM_REQ_CYCLE);
-+}
-+
-+#endif /* CONFIG_RTW_MESH */
-+
-diff --git a/drivers/staging/rtl8723cs/core/mesh/rtw_mesh_hwmp.h b/drivers/staging/rtl8723cs/core/mesh/rtw_mesh_hwmp.h
-new file mode 100644
-index 000000000000..943341781602
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/mesh/rtw_mesh_hwmp.h
-@@ -0,0 +1,60 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_MESH_HWMP_H_
-+#define __RTW_MESH_HWMP_H_
-+
-+#ifndef DBG_RTW_HWMP
-+#define DBG_RTW_HWMP 0
-+#endif
-+#if DBG_RTW_HWMP
-+#define RTW_HWMP_DBG(fmt, arg...) RTW_PRINT(fmt, ##arg)
-+#else
-+#define RTW_HWMP_DBG(fmt, arg...) RTW_DBG(fmt, ##arg)
-+#endif
-+
-+#ifndef INFO_RTW_HWMP
-+#define INFO_RTW_HWMP 0
-+#endif
-+#if INFO_RTW_HWMP
-+#define RTW_HWMP_INFO(fmt, arg...) RTW_PRINT(fmt, ##arg)
-+#else
-+#define RTW_HWMP_INFO(fmt, arg...) RTW_INFO(fmt, ##arg)
-+#endif
-+
-+
-+void rtw_ewma_err_rate_init(struct rtw_ewma_err_rate *e);
-+unsigned long rtw_ewma_err_rate_read(struct rtw_ewma_err_rate *e);
-+void rtw_ewma_err_rate_add(struct rtw_ewma_err_rate *e, unsigned long val);
-+int rtw_mesh_path_error_tx(_adapter *adapter,
-+			   u8 ttl, const u8 *target, u32 target_sn,
-+			   u16 target_rcode, const u8 *ra);
-+void rtw_ieee80211s_update_metric(_adapter *adapter, u8 mac_id,
-+				  u8 per, u8 rate,
-+				  u8 bw, u8 total_pkt);
-+void rtw_mesh_rx_path_sel_frame(_adapter *adapter, union recv_frame *rframe);
-+void rtw_mesh_queue_preq(struct rtw_mesh_path *mpath, u8 flags);
-+void rtw_mesh_path_start_discovery(_adapter *adapter);
-+void rtw_mesh_path_timer(void *ctx);
-+void rtw_mesh_path_tx_root_frame(_adapter *adapter);
-+void rtw_mesh_work_hdl(_workitem *work);
-+void rtw_ieee80211_mesh_path_timer(void *ctx);
-+void rtw_ieee80211_mesh_path_root_timer(void *ctx);
-+BOOLEAN rtw_ieee80211_mesh_root_setup(_adapter *adapter);
-+void rtw_mesh_work(_workitem *work);
-+void rtw_mesh_atlm_param_req_timer(void *ctx);
-+
-+#endif /* __RTW_MESH_HWMP_H_ */
-+
-+
-diff --git a/drivers/staging/rtl8723cs/core/mesh/rtw_mesh_pathtbl.c b/drivers/staging/rtl8723cs/core/mesh/rtw_mesh_pathtbl.c
-new file mode 100644
-index 000000000000..b74b56792d75
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/mesh/rtw_mesh_pathtbl.c
-@@ -0,0 +1,1242 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_MESH_PATHTBL_C_
-+
-+#ifdef CONFIG_RTW_MESH
-+#include <drv_types.h>
-+#include <linux/jhash.h>
-+
-+#ifdef PLATFORM_LINUX
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+static void rtw_mpath_free_rcu(struct rtw_mesh_path *mpath)
-+{
-+	kfree_rcu(mpath, rcu);
-+	rtw_mstat_update(MSTAT_TYPE_PHY, MSTAT_FREE, sizeof(struct rtw_mesh_path));
-+}
-+#else
-+static void rtw_mpath_free_rcu_callback(rtw_rcu_head *head)
-+{
-+	struct rtw_mesh_path *mpath;
-+
-+	mpath = container_of(head, struct rtw_mesh_path, rcu);
-+	rtw_mfree(mpath, sizeof(struct rtw_mesh_path));
-+}
-+
-+static void rtw_mpath_free_rcu(struct rtw_mesh_path *mpath)
-+{
-+	call_rcu(&mpath->rcu, rtw_mpath_free_rcu_callback);
-+}
-+#endif
-+#endif /* PLATFORM_LINUX */
-+
-+static void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath);
-+
-+static u32 rtw_mesh_table_hash(const void *addr, u32 len, u32 seed)
-+{
-+	/* Use last four bytes of hw addr as hash index */
-+	return jhash_1word(*(u32 *)(addr+2), seed);
-+}
-+
-+static const rtw_rhashtable_params rtw_mesh_rht_params = {
-+	.nelem_hint = 2,
-+	.automatic_shrinking = true,
-+	.key_len = ETH_ALEN,
-+	.key_offset = offsetof(struct rtw_mesh_path, dst),
-+	.head_offset = offsetof(struct rtw_mesh_path, rhash),
-+	.hashfn = rtw_mesh_table_hash,
-+};
-+
-+static inline bool rtw_mpath_expired(struct rtw_mesh_path *mpath)
-+{
-+	return (mpath->flags & RTW_MESH_PATH_ACTIVE) &&
-+	       rtw_time_after(rtw_get_current_time(), mpath->exp_time) &&
-+	       !(mpath->flags & RTW_MESH_PATH_FIXED);
-+}
-+
-+static void rtw_mesh_path_rht_free(void *ptr, void *tblptr)
-+{
-+	struct rtw_mesh_path *mpath = ptr;
-+	struct rtw_mesh_table *tbl = tblptr;
-+
-+	rtw_mesh_path_free_rcu(tbl, mpath);
-+}
-+
-+static struct rtw_mesh_table *rtw_mesh_table_alloc(void)
-+{
-+	struct rtw_mesh_table *newtbl;
-+
-+	newtbl = rtw_malloc(sizeof(struct rtw_mesh_table));
-+	if (!newtbl)
-+		return NULL;
-+
-+	rtw_hlist_head_init(&newtbl->known_gates);
-+	ATOMIC_SET(&newtbl->entries,  0);
-+	_rtw_spinlock_init(&newtbl->gates_lock);
-+
-+	return newtbl;
-+}
-+
-+static void rtw_mesh_table_free(struct rtw_mesh_table *tbl)
-+{
-+	rtw_rhashtable_free_and_destroy(&tbl->rhead,
-+				    rtw_mesh_path_rht_free, tbl);
-+	rtw_mfree(tbl, sizeof(struct rtw_mesh_table));
-+}
-+
-+/**
-+ *
-+ * rtw_mesh_path_assign_nexthop - update mesh path next hop
-+ *
-+ * @mpath: mesh path to update
-+ * @sta: next hop to assign
-+ *
-+ * Locking: mpath->state_lock must be held when calling this function
-+ */
-+void rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info *sta)
-+{
-+	struct xmit_frame *xframe;
-+	_list *list, *head;
-+
-+	rtw_rcu_assign_pointer(mpath->next_hop, sta);
-+
-+	enter_critical_bh(&mpath->frame_queue.lock);
-+	head = &mpath->frame_queue.queue;
-+	list = get_next(head);
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
-+		list = get_next(list);
-+		_rtw_memcpy(xframe->attrib.ra, sta->cmn.mac_addr, ETH_ALEN);
-+	}
-+
-+	exit_critical_bh(&mpath->frame_queue.lock);
-+}
-+
-+static void rtw_prepare_for_gate(struct xmit_frame *xframe, char *dst_addr,
-+			     struct rtw_mesh_path *gate_mpath)
-+{
-+	struct pkt_attrib *attrib = &xframe->attrib;
-+	char *next_hop;
-+
-+	if (attrib->mesh_frame_mode == MESH_UCAST_DATA)
-+		attrib->mesh_frame_mode = MESH_UCAST_PX_DATA;
-+
-+	/* update next hop */
-+	rtw_rcu_read_lock();
-+	next_hop = rtw_rcu_dereference(gate_mpath->next_hop)->cmn.mac_addr;
-+	_rtw_memcpy(attrib->ra, next_hop, ETH_ALEN);
-+	rtw_rcu_read_unlock();
-+	_rtw_memcpy(attrib->mda, dst_addr, ETH_ALEN);
-+}
-+
-+/**
-+ *
-+ * rtw_mesh_path_move_to_queue - Move or copy frames from one mpath queue to another
-+ *
-+ * This function is used to transfer or copy frames from an unresolved mpath to
-+ * a gate mpath.  The function also adds the Address Extension field and
-+ * updates the next hop.
-+ *
-+ * If a frame already has an Address Extension field, only the next hop and
-+ * destination addresses are updated.
-+ *
-+ * The gate mpath must be an active mpath with a valid mpath->next_hop.
-+ *
-+ * @mpath: An active mpath the frames will be sent to (i.e. the gate)
-+ * @from_mpath: The failed mpath
-+ * @copy: When true, copy all the frames to the new mpath queue.  When false,
-+ * move them.
-+ */
-+static void rtw_mesh_path_move_to_queue(struct rtw_mesh_path *gate_mpath,
-+				    struct rtw_mesh_path *from_mpath,
-+				    bool copy)
-+{
-+	struct xmit_frame *fskb;
-+	_list *list, *head;
-+	_list failq;
-+	u32 failq_len;
-+	_irqL flags;
-+
-+	if (rtw_warn_on(gate_mpath == from_mpath))
-+		return;
-+	if (rtw_warn_on(!gate_mpath->next_hop))
-+		return;
-+
-+	_rtw_init_listhead(&failq);
-+
-+	_enter_critical_bh(&from_mpath->frame_queue.lock, &flags);
-+	rtw_list_splice_init(&from_mpath->frame_queue.queue, &failq);
-+	failq_len = from_mpath->frame_queue_len;
-+	from_mpath->frame_queue_len = 0;
-+	_exit_critical_bh(&from_mpath->frame_queue.lock, &flags);
-+
-+	head = &failq;
-+	list = get_next(head);
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		if (gate_mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) {
-+			RTW_MPATH_DBG(FUNC_ADPT_FMT" mpath queue for gate %pM is full!\n"
-+				, FUNC_ADPT_ARG(gate_mpath->adapter), gate_mpath->dst);
-+			break;
-+		}
-+
-+		fskb = LIST_CONTAINOR(list, struct xmit_frame, list);
-+		list = get_next(list);
-+
-+		rtw_list_delete(&fskb->list);
-+		failq_len--;
-+		rtw_prepare_for_gate(fskb, gate_mpath->dst, gate_mpath);
-+		_enter_critical_bh(&gate_mpath->frame_queue.lock, &flags);
-+		rtw_list_insert_tail(&fskb->list, get_list_head(&gate_mpath->frame_queue));
-+		gate_mpath->frame_queue_len++;
-+		_exit_critical_bh(&gate_mpath->frame_queue.lock, &flags);
-+
-+		#if 0 /* TODO: copy */
-+		skb = rtw_skb_copy(fskb);
-+		if (rtw_warn_on(!skb))
-+			break;
-+
-+		rtw_prepare_for_gate(skb, gate_mpath->dst, gate_mpath);
-+		skb_queue_tail(&gate_mpath->frame_queue, skb);
-+
-+		if (copy)
-+			continue;
-+
-+		__skb_unlink(fskb, &failq);
-+		rtw_skb_free(fskb);
-+		#endif
-+	}
-+
-+	RTW_MPATH_DBG(FUNC_ADPT_FMT" mpath queue for gate %pM has %d frames\n"
-+		, FUNC_ADPT_ARG(gate_mpath->adapter), gate_mpath->dst, gate_mpath->frame_queue_len);
-+
-+	if (!copy)
-+		return;
-+
-+	_enter_critical_bh(&from_mpath->frame_queue.lock, &flags);
-+	rtw_list_splice(&failq, &from_mpath->frame_queue.queue);
-+	from_mpath->frame_queue_len += failq_len;
-+	_exit_critical_bh(&from_mpath->frame_queue.lock, &flags);
-+}
-+
-+
-+static struct rtw_mesh_path *rtw_mpath_lookup(struct rtw_mesh_table *tbl, const u8 *dst)
-+{
-+	struct rtw_mesh_path *mpath;
-+
-+	if (!tbl)
-+		return NULL;
-+
-+	mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, dst, rtw_mesh_rht_params);
-+
-+	if (mpath && rtw_mpath_expired(mpath)) {
-+		enter_critical_bh(&mpath->state_lock);
-+		mpath->flags &= ~RTW_MESH_PATH_ACTIVE;
-+		exit_critical_bh(&mpath->state_lock);
-+	}
-+	return mpath;
-+}
-+
-+/**
-+ * rtw_mesh_path_lookup - look up a path in the mesh path table
-+ * @sdata: local subif
-+ * @dst: hardware address (ETH_ALEN length) of destination
-+ *
-+ * Returns: pointer to the mesh path structure, or NULL if not found
-+ *
-+ * Locking: must be called within a read rcu section.
-+ */
-+struct rtw_mesh_path *
-+rtw_mesh_path_lookup(_adapter *adapter, const u8 *dst)
-+{
-+	return rtw_mpath_lookup(adapter->mesh_info.mesh_paths, dst);
-+}
-+
-+struct rtw_mesh_path *
-+rtw_mpp_path_lookup(_adapter *adapter, const u8 *dst)
-+{
-+	return rtw_mpath_lookup(adapter->mesh_info.mpp_paths, dst);
-+}
-+
-+static struct rtw_mesh_path *
-+__rtw_mesh_path_lookup_by_idx(struct rtw_mesh_table *tbl, int idx)
-+{
-+	int i = 0, ret;
-+	struct rtw_mesh_path *mpath = NULL;
-+	rtw_rhashtable_iter iter;
-+
-+	if (!tbl)
-+		return NULL;
-+
-+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
-+	if (ret)
-+		return NULL;
-+
-+	ret = rtw_rhashtable_walk_start(&iter);
-+	if (ret && ret != -EAGAIN)
-+		goto err;
-+
-+	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
-+		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
-+			continue;
-+		if (IS_ERR(mpath))
-+			break;
-+		if (i++ == idx)
-+			break;
-+	}
-+err:
-+	rtw_rhashtable_walk_stop(&iter);
-+	rtw_rhashtable_walk_exit(&iter);
-+
-+	if (IS_ERR(mpath) || !mpath)
-+		return NULL;
-+
-+	if (rtw_mpath_expired(mpath)) {
-+		enter_critical_bh(&mpath->state_lock);
-+		mpath->flags &= ~RTW_MESH_PATH_ACTIVE;
-+		exit_critical_bh(&mpath->state_lock);
-+	}
-+	return mpath;
-+}
-+
-+/**
-+ * rtw_mesh_path_lookup_by_idx - look up a path in the mesh path table by its index
-+ * @idx: index
-+ * @sdata: local subif, or NULL for all entries
-+ *
-+ * Returns: pointer to the mesh path structure, or NULL if not found.
-+ *
-+ * Locking: must be called within a read rcu section.
-+ */
-+struct rtw_mesh_path *
-+rtw_mesh_path_lookup_by_idx(_adapter *adapter, int idx)
-+{
-+	return __rtw_mesh_path_lookup_by_idx(adapter->mesh_info.mesh_paths, idx);
-+}
-+
-+void dump_mpath(void *sel, _adapter *adapter)
-+{
-+	struct rtw_mesh_path *mpath;
-+	int idx = 0;
-+	char dst[ETH_ALEN];
-+	char next_hop[ETH_ALEN];
-+	u32 sn, metric, qlen;
-+	u32 exp_ms = 0, dto_ms;
-+	u8 drty;
-+	enum rtw_mesh_path_flags flags;
-+
-+	RTW_PRINT_SEL(sel, "%-17s %-17s %-10s %-10s %-4s %-6s %-6s %-4s flags\n"
-+		, "dst", "next_hop", "sn", "metric", "qlen", "exp_ms", "dto_ms", "drty"
-+	);
-+
-+	do {
-+		rtw_rcu_read_lock();
-+
-+		mpath = rtw_mesh_path_lookup_by_idx(adapter, idx);
-+		if (mpath) {
-+			_rtw_memcpy(dst, mpath->dst, ETH_ALEN);
-+			_rtw_memcpy(next_hop, mpath->next_hop->cmn.mac_addr, ETH_ALEN);
-+			sn = mpath->sn;
-+			metric = mpath->metric;
-+			qlen = mpath->frame_queue_len;
-+			if (rtw_time_after(mpath->exp_time, rtw_get_current_time()))
-+				exp_ms = rtw_get_remaining_time_ms(mpath->exp_time);
-+			dto_ms = rtw_systime_to_ms(mpath->discovery_timeout);
-+			drty = mpath->discovery_retries;
-+			flags = mpath->flags;
-+		}
-+
-+		rtw_rcu_read_unlock();
-+
-+		if (mpath) {
-+			RTW_PRINT_SEL(sel, MAC_FMT" "MAC_FMT" %10u %10u %4u %6u %6u %4u%s%s%s%s%s%s%s%s%s%s\n"
-+				, MAC_ARG(dst), MAC_ARG(next_hop), sn, metric, qlen
-+				, exp_ms < 999999 ? exp_ms : 999999
-+				, dto_ms < 999999 ? dto_ms : 999999
-+				, drty
-+				, (flags & RTW_MESH_PATH_ACTIVE) ? " ACT" : ""
-+				, (flags & RTW_MESH_PATH_RESOLVING) ? " RSVING" : ""
-+				, (flags & RTW_MESH_PATH_SN_VALID) ? " SN_VALID" : ""
-+				, (flags & RTW_MESH_PATH_FIXED) ?  " FIXED" : ""
-+				, (flags & RTW_MESH_PATH_RESOLVED) ? " RSVED" : ""
-+				, (flags & RTW_MESH_PATH_REQ_QUEUED) ? " REQ_IN_Q" : ""
-+				, (flags & RTW_MESH_PATH_DELETED) ? " DELETED" : ""
-+				, (flags & RTW_MESH_PATH_ROOT_ADD_CHK) ? " R_ADD_CHK" : ""
-+				, (flags & RTW_MESH_PATH_PEER_AKA) ? " PEER_AKA" : ""
-+				, (flags & RTW_MESH_PATH_BCAST_PREQ) ? " BC_PREQ" : ""
-+			);
-+		}
-+
-+		idx++;
-+	} while (mpath);
-+}
-+
-+/**
-+ * rtw_mpp_path_lookup_by_idx - look up a path in the proxy path table by its index
-+ * @idx: index
-+ * @sdata: local subif, or NULL for all entries
-+ *
-+ * Returns: pointer to the proxy path structure, or NULL if not found.
-+ *
-+ * Locking: must be called within a read rcu section.
-+ */
-+struct rtw_mesh_path *
-+rtw_mpp_path_lookup_by_idx(_adapter *adapter, int idx)
-+{
-+	return __rtw_mesh_path_lookup_by_idx(adapter->mesh_info.mpp_paths, idx);
-+}
-+
-+/**
-+ * rtw_mesh_path_add_gate - add the given mpath to a mesh gate to our path table
-+ * @mpath: gate path to add to table
-+ */
-+int rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath)
-+{
-+	struct rtw_mesh_cfg *mcfg;
-+	struct rtw_mesh_info *minfo;
-+	struct rtw_mesh_table *tbl;
-+	int err, ori_num_gates;
-+
-+	rtw_rcu_read_lock();
-+	tbl = mpath->adapter->mesh_info.mesh_paths;
-+	if (!tbl) {
-+		err = -ENOENT;
-+		goto err_rcu;
-+	}
-+
-+	enter_critical_bh(&mpath->state_lock);
-+	mcfg = &mpath->adapter->mesh_cfg;
-+	mpath->gate_timeout = rtw_get_current_time() +
-+			      rtw_ms_to_systime(mcfg->path_gate_timeout_factor *
-+					        mpath->gate_ann_int);
-+	if (mpath->is_gate) {
-+		err = -EEXIST;
-+		exit_critical_bh(&mpath->state_lock);
-+		goto err_rcu;
-+	}
-+
-+	minfo = &mpath->adapter->mesh_info;
-+	mpath->is_gate = true;
-+	_rtw_spinlock(&tbl->gates_lock);
-+	ori_num_gates = minfo->num_gates;
-+	minfo->num_gates++;
-+	rtw_hlist_add_head_rcu(&mpath->gate_list, &tbl->known_gates);
-+
-+	if (ori_num_gates == 0
-+		|| rtw_macaddr_is_larger(mpath->dst, minfo->max_addr_gate->dst)
-+	) {
-+		minfo->max_addr_gate = mpath;
-+		minfo->max_addr_gate_is_larger_than_self =
-+			rtw_macaddr_is_larger(mpath->dst, adapter_mac_addr(mpath->adapter));
-+	}
-+
-+	_rtw_spinunlock(&tbl->gates_lock);
-+
-+	exit_critical_bh(&mpath->state_lock);
-+
-+	if (ori_num_gates == 0) {
-+		update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0);
-+		#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
-+		if (!rtw_mesh_cto_mgate_required(mpath->adapter))
-+			rtw_netif_carrier_on(mpath->adapter->pnetdev);
-+		#endif
-+	}
-+
-+	RTW_MPATH_DBG(
-+		  FUNC_ADPT_FMT" Mesh path: Recorded new gate: %pM. %d known gates\n",
-+		  FUNC_ADPT_ARG(mpath->adapter),
-+		  mpath->dst, mpath->adapter->mesh_info.num_gates);
-+	err = 0;
-+err_rcu:
-+	rtw_rcu_read_unlock();
-+	return err;
-+}
-+
-+/**
-+ * rtw_mesh_gate_del - remove a mesh gate from the list of known gates
-+ * @tbl: table which holds our list of known gates
-+ * @mpath: gate mpath
-+ */
-+void rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath)
-+{
-+	struct rtw_mesh_cfg *mcfg;
-+	struct rtw_mesh_info *minfo;
-+	int ori_num_gates;
-+
-+	rtw_lockdep_assert_held(&mpath->state_lock);
-+	if (!mpath->is_gate)
-+		return;
-+
-+	mcfg = &mpath->adapter->mesh_cfg;
-+	minfo = &mpath->adapter->mesh_info;
-+
-+	mpath->is_gate = false;
-+	enter_critical_bh(&tbl->gates_lock);
-+	rtw_hlist_del_rcu(&mpath->gate_list);
-+	ori_num_gates = minfo->num_gates;
-+	minfo->num_gates--;
-+
-+	if (ori_num_gates == 1) {
-+		minfo->max_addr_gate = NULL;
-+		minfo->max_addr_gate_is_larger_than_self = 0;
-+	} else if (minfo->max_addr_gate == mpath) {
-+		struct rtw_mesh_path *gate, *max_addr_gate = NULL;
-+		rtw_hlist_node *node;
-+
-+		rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
-+			if (!max_addr_gate || rtw_macaddr_is_larger(gate->dst, max_addr_gate->dst))
-+				max_addr_gate = gate;
-+		}
-+		minfo->max_addr_gate = max_addr_gate;
-+		minfo->max_addr_gate_is_larger_than_self =
-+			rtw_macaddr_is_larger(max_addr_gate->dst, adapter_mac_addr(mpath->adapter));
-+	}
-+
-+	exit_critical_bh(&tbl->gates_lock);
-+
-+	if (ori_num_gates == 1) {
-+		update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0);
-+		#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
-+		if (rtw_mesh_cto_mgate_required(mpath->adapter))
-+			rtw_netif_carrier_off(mpath->adapter->pnetdev);
-+		#endif
-+	}
-+
-+	RTW_MPATH_DBG(
-+		  FUNC_ADPT_FMT" Mesh path: Deleted gate: %pM. %d known gates\n",
-+		  FUNC_ADPT_ARG(mpath->adapter),
-+		  mpath->dst, mpath->adapter->mesh_info.num_gates);
-+}
-+
-+/**
-+ * rtw_mesh_gate_search - search a mesh gate from the list of known gates
-+ * @tbl: table which holds our list of known gates
-+ * @addr: address of gate
-+ */
-+bool rtw_mesh_gate_search(struct rtw_mesh_table *tbl, const u8 *addr)
-+{
-+	struct rtw_mesh_path *gate;
-+	rtw_hlist_node *node;
-+	bool exist = 0;
-+
-+	rtw_rcu_read_lock();
-+	rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
-+		if (_rtw_memcmp(gate->dst, addr, ETH_ALEN) == _TRUE) {
-+			exist = 1;
-+			break;
-+		}
-+	}
-+
-+	rtw_rcu_read_unlock();
-+
-+	return exist;
-+}
-+
-+/**
-+ * rtw_mesh_gate_num - number of gates known to this interface
-+ * @sdata: subif data
-+ */
-+int rtw_mesh_gate_num(_adapter *adapter)
-+{
-+	return adapter->mesh_info.num_gates;
-+}
-+
-+bool rtw_mesh_is_primary_gate(_adapter *adapter)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+
-+	return mcfg->dot11MeshGateAnnouncementProtocol
-+		&& !minfo->max_addr_gate_is_larger_than_self;
-+}
-+
-+void dump_known_gates(void *sel, _adapter *adapter)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct rtw_mesh_table *tbl;
-+	struct rtw_mesh_path *gate;
-+	rtw_hlist_node *node;
-+
-+	if (!rtw_mesh_gate_num(adapter))
-+		goto exit;
-+
-+	rtw_rcu_read_lock();
-+
-+	tbl = minfo->mesh_paths;
-+	if (!tbl)
-+		goto unlock;
-+
-+	RTW_PRINT_SEL(sel, "num:%d\n", rtw_mesh_gate_num(adapter));
-+
-+	rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
-+		RTW_PRINT_SEL(sel, "%c"MAC_FMT"\n"
-+			, gate == minfo->max_addr_gate ? '*' : ' '
-+			, MAC_ARG(gate->dst));
-+	}
-+
-+unlock:
-+	rtw_rcu_read_unlock();
-+exit:
-+	return;
-+}
-+
-+static
-+struct rtw_mesh_path *rtw_mesh_path_new(_adapter *adapter,
-+				const u8 *dst)
-+{
-+	struct rtw_mesh_path *new_mpath;
-+
-+	new_mpath = rtw_zmalloc(sizeof(struct rtw_mesh_path));
-+	if (!new_mpath)
-+		return NULL;
-+
-+	_rtw_memcpy(new_mpath->dst, dst, ETH_ALEN);
-+	_rtw_memset(new_mpath->rann_snd_addr, 0xFF, ETH_ALEN);
-+	new_mpath->is_root = false;
-+	new_mpath->adapter = adapter;
-+	new_mpath->flags = 0;
-+	new_mpath->gate_asked = false;
-+	_rtw_init_queue(&new_mpath->frame_queue);
-+	new_mpath->frame_queue_len = 0;
-+	new_mpath->exp_time = rtw_get_current_time();
-+	_rtw_spinlock_init(&new_mpath->state_lock);
-+	rtw_init_timer(&new_mpath->timer, adapter, rtw_mesh_path_timer, new_mpath);
-+
-+	return new_mpath;
-+}
-+
-+/**
-+ * rtw_mesh_path_add - allocate and add a new path to the mesh path table
-+ * @dst: destination address of the path (ETH_ALEN length)
-+ * @sdata: local subif
-+ *
-+ * Returns: 0 on success
-+ *
-+ * State: the initial state of the new path is set to 0
-+ */
-+struct rtw_mesh_path *rtw_mesh_path_add(_adapter *adapter,
-+				const u8 *dst)
-+{
-+	struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;
-+	struct rtw_mesh_path *mpath, *new_mpath;
-+	int ret;
-+
-+	if (!tbl)
-+		return ERR_PTR(-ENOTSUPP);
-+
-+	if (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
-+		/* never add ourselves as neighbours */
-+		return ERR_PTR(-ENOTSUPP);
-+
-+	if (is_multicast_mac_addr(dst))
-+		return ERR_PTR(-ENOTSUPP);
-+
-+	if (ATOMIC_INC_UNLESS(&adapter->mesh_info.mpaths, RTW_MESH_MAX_MPATHS) == 0)
-+		return ERR_PTR(-ENOSPC);
-+
-+	new_mpath = rtw_mesh_path_new(adapter, dst);
-+	if (!new_mpath)
-+		return ERR_PTR(-ENOMEM);
-+
-+	do {
-+		ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead,
-+						    &new_mpath->rhash,
-+						    rtw_mesh_rht_params);
-+
-+		if (ret == -EEXIST)
-+			mpath = rtw_rhashtable_lookup_fast(&tbl->rhead,
-+						       dst,
-+						       rtw_mesh_rht_params);
-+
-+	} while (unlikely(ret == -EEXIST && !mpath));
-+
-+	if (ret && ret != -EEXIST)
-+		return ERR_PTR(ret);
-+
-+	/* At this point either new_mpath was added, or we found a
-+	 * matching entry already in the table; in the latter case
-+	 * free the unnecessary new entry.
-+	 */
-+	if (ret == -EEXIST) {
-+		rtw_mfree(new_mpath, sizeof(struct rtw_mesh_path));
-+		new_mpath = mpath;
-+	}
-+	adapter->mesh_info.mesh_paths_generation++;
-+	return new_mpath;
-+}
-+
-+int rtw_mpp_path_add(_adapter *adapter,
-+		 const u8 *dst, const u8 *mpp)
-+{
-+	struct rtw_mesh_table *tbl = adapter->mesh_info.mpp_paths;
-+	struct rtw_mesh_path *new_mpath;
-+	int ret;
-+
-+	if (!tbl)
-+		return -ENOTSUPP;
-+
-+	if (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
-+		/* never add ourselves as neighbours */
-+		return -ENOTSUPP;
-+
-+	if (is_multicast_mac_addr(dst))
-+		return -ENOTSUPP;
-+
-+	new_mpath = rtw_mesh_path_new(adapter, dst);
-+
-+	if (!new_mpath)
-+		return -ENOMEM;
-+
-+	_rtw_memcpy(new_mpath->mpp, mpp, ETH_ALEN);
-+	ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead,
-+					    &new_mpath->rhash,
-+					    rtw_mesh_rht_params);
-+
-+	adapter->mesh_info.mpp_paths_generation++;
-+	return ret;
-+}
-+
-+void dump_mpp(void *sel, _adapter *adapter)
-+{
-+	struct rtw_mesh_path *mpath;
-+	int idx = 0;
-+	char dst[ETH_ALEN];
-+	char mpp[ETH_ALEN];
-+
-+	RTW_PRINT_SEL(sel, "%-17s %-17s\n", "dst", "mpp");
-+
-+	do {
-+		rtw_rcu_read_lock();
-+
-+		mpath = rtw_mpp_path_lookup_by_idx(adapter, idx);
-+		if (mpath) {
-+			_rtw_memcpy(dst, mpath->dst, ETH_ALEN);
-+			_rtw_memcpy(mpp, mpath->mpp, ETH_ALEN);
-+		}
-+
-+		rtw_rcu_read_unlock();
-+
-+		if (mpath) {
-+			RTW_PRINT_SEL(sel, MAC_FMT" "MAC_FMT"\n"
-+				, MAC_ARG(dst), MAC_ARG(mpp));
-+		}
-+
-+		idx++;
-+	} while (mpath);
-+}
-+
-+/**
-+ * rtw_mesh_plink_broken - deactivates paths and sends perr when a link breaks
-+ *
-+ * @sta: broken peer link
-+ *
-+ * This function must be called from the rate control algorithm if enough
-+ * delivery errors suggest that a peer link is no longer usable.
-+ */
-+void rtw_mesh_plink_broken(struct sta_info *sta)
-+{
-+	_adapter *adapter = sta->padapter;
-+	struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;
-+	static const u8 bcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	struct rtw_mesh_path *mpath;
-+	rtw_rhashtable_iter iter;
-+	int ret;
-+
-+	if (!tbl)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
-+	if (ret)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_start(&iter);
-+	if (ret && ret != -EAGAIN)
-+		goto out;
-+
-+	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
-+		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
-+			continue;
-+		if (IS_ERR(mpath))
-+			break;
-+		if (rtw_rcu_access_pointer(mpath->next_hop) == sta &&
-+		    mpath->flags & RTW_MESH_PATH_ACTIVE &&
-+		    !(mpath->flags & RTW_MESH_PATH_FIXED)) {
-+			enter_critical_bh(&mpath->state_lock);
-+			mpath->flags &= ~RTW_MESH_PATH_ACTIVE;
-+			++mpath->sn;
-+			exit_critical_bh(&mpath->state_lock);
-+			rtw_mesh_path_error_tx(adapter,
-+				adapter->mesh_cfg.element_ttl,
-+				mpath->dst, mpath->sn,
-+				WLAN_REASON_MESH_PATH_DEST_UNREACHABLE, bcast);
-+		}
-+	}
-+out:
-+	rtw_rhashtable_walk_stop(&iter);
-+	rtw_rhashtable_walk_exit(&iter);
-+}
-+
-+static void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl,
-+			       struct rtw_mesh_path *mpath)
-+{
-+	_adapter *adapter = mpath->adapter;
-+
-+	enter_critical_bh(&mpath->state_lock);
-+	mpath->flags |= RTW_MESH_PATH_RESOLVING | RTW_MESH_PATH_DELETED;
-+	rtw_mesh_gate_del(tbl, mpath);
-+	exit_critical_bh(&mpath->state_lock);
-+	_cancel_timer_ex(&mpath->timer);
-+	ATOMIC_DEC(&adapter->mesh_info.mpaths);
-+	ATOMIC_DEC(&tbl->entries);
-+	_rtw_spinlock_free(&mpath->state_lock);
-+
-+	rtw_mesh_path_flush_pending(mpath);
-+
-+	rtw_mpath_free_rcu(mpath);
-+}
-+
-+static void __rtw_mesh_path_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath)
-+{
-+	rtw_rhashtable_remove_fast(&tbl->rhead, &mpath->rhash, rtw_mesh_rht_params);
-+	rtw_mesh_path_free_rcu(tbl, mpath);
-+}
-+
-+/**
-+ * rtw_mesh_path_flush_by_nexthop - Deletes mesh paths if their next hop matches
-+ *
-+ * @sta: mesh peer to match
-+ *
-+ * RCU notes: this function is called when a mesh plink transitions from
-+ * PLINK_ESTAB to any other state, since PLINK_ESTAB state is the only one that
-+ * allows path creation. This will happen before the sta can be freed (because
-+ * sta_info_destroy() calls this) so any reader in a rcu read block will be
-+ * protected against the plink disappearing.
-+ */
-+void rtw_mesh_path_flush_by_nexthop(struct sta_info *sta)
-+{
-+	_adapter *adapter = sta->padapter;
-+	struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;
-+	struct rtw_mesh_path *mpath;
-+	rtw_rhashtable_iter iter;
-+	int ret;
-+
-+	if (!tbl)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
-+	if (ret)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_start(&iter);
-+	if (ret && ret != -EAGAIN)
-+		goto out;
-+
-+	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
-+		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
-+			continue;
-+		if (IS_ERR(mpath))
-+			break;
-+
-+		if (rtw_rcu_access_pointer(mpath->next_hop) == sta)
-+			__rtw_mesh_path_del(tbl, mpath);
-+	}
-+out:
-+	rtw_rhashtable_walk_stop(&iter);
-+	rtw_rhashtable_walk_exit(&iter);
-+}
-+
-+static void rtw_mpp_flush_by_proxy(_adapter *adapter,
-+			       const u8 *proxy)
-+{
-+	struct rtw_mesh_table *tbl = adapter->mesh_info.mpp_paths;
-+	struct rtw_mesh_path *mpath;
-+	rtw_rhashtable_iter iter;
-+	int ret;
-+
-+	if (!tbl)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
-+	if (ret)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_start(&iter);
-+	if (ret && ret != -EAGAIN)
-+		goto out;
-+
-+	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
-+		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
-+			continue;
-+		if (IS_ERR(mpath))
-+			break;
-+
-+		if (_rtw_memcmp(mpath->mpp, proxy, ETH_ALEN) == _TRUE)
-+			__rtw_mesh_path_del(tbl, mpath);
-+	}
-+out:
-+	rtw_rhashtable_walk_stop(&iter);
-+	rtw_rhashtable_walk_exit(&iter);
-+}
-+
-+static void rtw_table_flush_by_iface(struct rtw_mesh_table *tbl)
-+{
-+	struct rtw_mesh_path *mpath;
-+	rtw_rhashtable_iter iter;
-+	int ret;
-+
-+	if (!tbl)
-+		return;
-+	
-+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
-+	if (ret)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_start(&iter);
-+	if (ret && ret != -EAGAIN)
-+		goto out;
-+
-+	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
-+		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
-+			continue;
-+		if (IS_ERR(mpath))
-+			break;
-+		__rtw_mesh_path_del(tbl, mpath);
-+	}
-+out:
-+	rtw_rhashtable_walk_stop(&iter);
-+	rtw_rhashtable_walk_exit(&iter);
-+}
-+
-+/**
-+ * rtw_mesh_path_flush_by_iface - Deletes all mesh paths associated with a given iface
-+ *
-+ * This function deletes both mesh paths as well as mesh portal paths.
-+ *
-+ * @sdata: interface data to match
-+ *
-+ */
-+void rtw_mesh_path_flush_by_iface(_adapter *adapter)
-+{
-+	rtw_table_flush_by_iface(adapter->mesh_info.mesh_paths);
-+	rtw_table_flush_by_iface(adapter->mesh_info.mpp_paths);
-+}
-+
-+/**
-+ * rtw_table_path_del - delete a path from the mesh or mpp table
-+ *
-+ * @tbl: mesh or mpp path table
-+ * @sdata: local subif
-+ * @addr: dst address (ETH_ALEN length)
-+ *
-+ * Returns: 0 if successful
-+ */
-+static int rtw_table_path_del(struct rtw_mesh_table *tbl,
-+			  const u8 *addr)
-+{
-+	struct rtw_mesh_path *mpath;
-+
-+	if (!tbl)
-+		return -ENXIO;
-+
-+	rtw_rcu_read_lock();
-+	mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, addr, rtw_mesh_rht_params);
-+	if (!mpath) {
-+		rtw_rcu_read_unlock();
-+		return -ENXIO;
-+	}
-+
-+	__rtw_mesh_path_del(tbl, mpath);
-+	rtw_rcu_read_unlock();
-+	return 0;
-+}
-+
-+
-+/**
-+ * rtw_mesh_path_del - delete a mesh path from the table
-+ *
-+ * @addr: dst address (ETH_ALEN length)
-+ * @sdata: local subif
-+ *
-+ * Returns: 0 if successful
-+ */
-+int rtw_mesh_path_del(_adapter *adapter, const u8 *addr)
-+{
-+	int err;
-+
-+	/* flush relevant mpp entries first */
-+	rtw_mpp_flush_by_proxy(adapter, addr);
-+
-+	err = rtw_table_path_del(adapter->mesh_info.mesh_paths, addr);
-+	adapter->mesh_info.mesh_paths_generation++;
-+	return err;
-+}
-+
-+/**
-+ * rtw_mesh_path_tx_pending - sends pending frames in a mesh path queue
-+ *
-+ * @mpath: mesh path to activate
-+ *
-+ * Locking: the state_lock of the mpath structure must NOT be held when calling
-+ * this function.
-+ */
-+void rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath)
-+{
-+	if (mpath->flags & RTW_MESH_PATH_ACTIVE) {
-+		struct rtw_mesh_info *minfo = &mpath->adapter->mesh_info;
-+		_list q;
-+		u32 q_len = 0;
-+
-+		_rtw_init_listhead(&q);
-+
-+		/* move to local queue */
-+		enter_critical_bh(&mpath->frame_queue.lock);
-+		if (mpath->frame_queue_len) {
-+			rtw_list_splice_init(&mpath->frame_queue.queue, &q);
-+			q_len = mpath->frame_queue_len;
-+			mpath->frame_queue_len = 0;
-+		}
-+		exit_critical_bh(&mpath->frame_queue.lock);
-+
-+		if (q_len) {
-+			/* move to mpath_tx_queue */
-+			enter_critical_bh(&minfo->mpath_tx_queue.lock);
-+			rtw_list_splice_tail(&q, &minfo->mpath_tx_queue.queue);
-+			minfo->mpath_tx_queue_len += q_len;
-+			exit_critical_bh(&minfo->mpath_tx_queue.lock);
-+
-+			/* schedule mpath_tx_tasklet */
-+			tasklet_hi_schedule(&minfo->mpath_tx_tasklet);
-+		}
-+	}
-+}
-+
-+/**
-+ * rtw_mesh_path_send_to_gates - sends pending frames to all known mesh gates
-+ *
-+ * @mpath: mesh path whose queue will be emptied
-+ *
-+ * If there is only one gate, the frames are transferred from the failed mpath
-+ * queue to that gate's queue.  If there are more than one gates, the frames
-+ * are copied from each gate to the next.  After frames are copied, the
-+ * mpath queues are emptied onto the transmission queue.
-+ */
-+int rtw_mesh_path_send_to_gates(struct rtw_mesh_path *mpath)
-+{
-+	_adapter *adapter = mpath->adapter;
-+	struct rtw_mesh_table *tbl;
-+	struct rtw_mesh_path *from_mpath = mpath;
-+	struct rtw_mesh_path *gate;
-+	bool copy = false;
-+	rtw_hlist_node *node;
-+
-+	tbl = adapter->mesh_info.mesh_paths;
-+	if (!tbl)
-+		return 0;
-+
-+	rtw_rcu_read_lock();
-+	rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
-+		if (gate->flags & RTW_MESH_PATH_ACTIVE) {
-+			RTW_MPATH_DBG(FUNC_ADPT_FMT" Forwarding to %pM\n",
-+				FUNC_ADPT_ARG(adapter), gate->dst);
-+			rtw_mesh_path_move_to_queue(gate, from_mpath, copy);
-+			from_mpath = gate;
-+			copy = true;
-+		} else {
-+			RTW_MPATH_DBG(
-+				  FUNC_ADPT_FMT" Not forwarding to %pM (flags %#x)\n",
-+				  FUNC_ADPT_ARG(adapter), gate->dst, gate->flags);
-+		}
-+	}
-+
-+	rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
-+		RTW_MPATH_DBG(FUNC_ADPT_FMT" Sending to %pM\n",
-+			FUNC_ADPT_ARG(adapter), gate->dst);
-+		rtw_mesh_path_tx_pending(gate);
-+	}
-+	rtw_rcu_read_unlock();
-+
-+	return (from_mpath == mpath) ? -EHOSTUNREACH : 0;
-+}
-+
-+/**
-+ * rtw_mesh_path_discard_frame - discard a frame whose path could not be resolved
-+ *
-+ * @skb: frame to discard
-+ * @sdata: network subif the frame was to be sent through
-+ *
-+ * Locking: the function must me called within a rcu_read_lock region
-+ */
-+void rtw_mesh_path_discard_frame(_adapter *adapter,
-+			     struct xmit_frame *xframe)
-+{
-+	rtw_free_xmitframe(&adapter->xmitpriv, xframe);
-+	adapter->mesh_info.mshstats.dropped_frames_no_route++;
-+}
-+
-+/**
-+ * rtw_mesh_path_flush_pending - free the pending queue of a mesh path
-+ *
-+ * @mpath: mesh path whose queue has to be freed
-+ *
-+ * Locking: the function must me called within a rcu_read_lock region
-+ */
-+void rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath)
-+{
-+	struct xmit_frame *xframe;
-+	_list *list, *head;
-+	_list tmp;
-+
-+	_rtw_init_listhead(&tmp);
-+
-+	enter_critical_bh(&mpath->frame_queue.lock);
-+	rtw_list_splice_init(&mpath->frame_queue.queue, &tmp);
-+	mpath->frame_queue_len = 0;
-+	exit_critical_bh(&mpath->frame_queue.lock);
-+
-+	head = &tmp;
-+	list = get_next(head);
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
-+		list = get_next(list);
-+		rtw_list_delete(&xframe->list);
-+		rtw_mesh_path_discard_frame(mpath->adapter, xframe);
-+	}
-+}
-+
-+/**
-+ * rtw_mesh_path_fix_nexthop - force a specific next hop for a mesh path
-+ *
-+ * @mpath: the mesh path to modify
-+ * @next_hop: the next hop to force
-+ *
-+ * Locking: this function must be called holding mpath->state_lock
-+ */
-+void rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop)
-+{
-+	enter_critical_bh(&mpath->state_lock);
-+	rtw_mesh_path_assign_nexthop(mpath, next_hop);
-+	mpath->sn = 0xffff;
-+	mpath->metric = 0;
-+	mpath->hop_count = 0;
-+	mpath->exp_time = 0;
-+	mpath->flags = RTW_MESH_PATH_FIXED | RTW_MESH_PATH_SN_VALID;
-+	rtw_mesh_path_activate(mpath);
-+	exit_critical_bh(&mpath->state_lock);
-+	rtw_ewma_err_rate_init(&next_hop->metrics.err_rate);
-+	/* init it at a low value - 0 start is tricky */
-+	rtw_ewma_err_rate_add(&next_hop->metrics.err_rate, 1);
-+	rtw_mesh_path_tx_pending(mpath);
-+}
-+
-+int rtw_mesh_pathtbl_init(_adapter *adapter)
-+{
-+	struct rtw_mesh_table *tbl_path, *tbl_mpp;
-+	int ret;
-+
-+	tbl_path = rtw_mesh_table_alloc();
-+	if (!tbl_path)
-+		return -ENOMEM;
-+
-+	tbl_mpp = rtw_mesh_table_alloc();
-+	if (!tbl_mpp) {
-+		ret = -ENOMEM;
-+		goto free_path;
-+	}
-+
-+	rtw_rhashtable_init(&tbl_path->rhead, &rtw_mesh_rht_params);
-+	rtw_rhashtable_init(&tbl_mpp->rhead, &rtw_mesh_rht_params);
-+
-+	adapter->mesh_info.mesh_paths = tbl_path;
-+	adapter->mesh_info.mpp_paths = tbl_mpp;
-+
-+	return 0;
-+
-+free_path:
-+	rtw_mesh_table_free(tbl_path);
-+	return ret;
-+}
-+
-+static
-+void rtw_mesh_path_tbl_expire(_adapter *adapter,
-+			  struct rtw_mesh_table *tbl)
-+{
-+	struct rtw_mesh_path *mpath;
-+	rtw_rhashtable_iter iter;
-+	int ret;
-+
-+	if (!tbl)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
-+	if (ret)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_start(&iter);
-+	if (ret && ret != -EAGAIN)
-+		goto out;
-+
-+	while ((mpath = rtw_rhashtable_walk_next(&iter))) {
-+		if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
-+			continue;
-+		if (IS_ERR(mpath))
-+			break;
-+		if ((!(mpath->flags & RTW_MESH_PATH_RESOLVING)) &&
-+		    (!(mpath->flags & RTW_MESH_PATH_FIXED)) &&
-+		     rtw_time_after(rtw_get_current_time(), mpath->exp_time + RTW_MESH_PATH_EXPIRE))
-+			__rtw_mesh_path_del(tbl, mpath);
-+
-+		if (mpath->is_gate &&  /* need not to deal with non-gate case */
-+		    rtw_time_after(rtw_get_current_time(), mpath->gate_timeout)) {
-+			RTW_MPATH_DBG(FUNC_ADPT_FMT"mpath [%pM] expired systime is %lu systime is %lu\n",
-+				      FUNC_ADPT_ARG(adapter), mpath->dst,
-+				      mpath->gate_timeout, rtw_get_current_time());
-+			enter_critical_bh(&mpath->state_lock);
-+			if (mpath->gate_asked) { /* asked gate before */
-+				rtw_mesh_gate_del(tbl, mpath);
-+				exit_critical_bh(&mpath->state_lock);
-+			} else {
-+				mpath->gate_asked = true;
-+				mpath->gate_timeout = rtw_get_current_time() + rtw_ms_to_systime(mpath->gate_ann_int);
-+				exit_critical_bh(&mpath->state_lock);
-+				rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH);
-+				RTW_MPATH_DBG(FUNC_ADPT_FMT"mpath [%pM] ask mesh gate existence (is_root=%d)\n",
-+				      FUNC_ADPT_ARG(adapter), mpath->dst, mpath->is_root);
-+			}
-+		}
-+	}
-+
-+out:
-+	rtw_rhashtable_walk_stop(&iter);
-+	rtw_rhashtable_walk_exit(&iter);
-+}
-+
-+void rtw_mesh_path_expire(_adapter *adapter)
-+{
-+	rtw_mesh_path_tbl_expire(adapter, adapter->mesh_info.mesh_paths);
-+	rtw_mesh_path_tbl_expire(adapter, adapter->mesh_info.mpp_paths);
-+}
-+
-+void rtw_mesh_pathtbl_unregister(_adapter *adapter)
-+{
-+	if (adapter->mesh_info.mesh_paths) {
-+		rtw_mesh_table_free(adapter->mesh_info.mesh_paths);
-+		adapter->mesh_info.mesh_paths = NULL;
-+	}
-+
-+	if (adapter->mesh_info.mpp_paths) {
-+		rtw_mesh_table_free(adapter->mesh_info.mpp_paths);
-+		adapter->mesh_info.mpp_paths = NULL;
-+	}
-+}
-+#endif /* CONFIG_RTW_MESH */
-+
-diff --git a/drivers/staging/rtl8723cs/core/mesh/rtw_mesh_pathtbl.h b/drivers/staging/rtl8723cs/core/mesh/rtw_mesh_pathtbl.h
-new file mode 100644
-index 000000000000..be0c40980c9e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/mesh/rtw_mesh_pathtbl.h
-@@ -0,0 +1,211 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_MESH_PATHTBL_H_
-+#define __RTW_MESH_PATHTBL_H_
-+
-+#ifndef DBG_RTW_MPATH
-+#define DBG_RTW_MPATH 1
-+#endif
-+#if DBG_RTW_MPATH
-+#define RTW_MPATH_DBG(fmt, arg...) RTW_PRINT(fmt, ##arg)
-+#else
-+#define RTW_MPATH_DBG(fmt, arg...) do {} while (0)
-+#endif
-+
-+/**
-+ * enum rtw_mesh_path_flags - mesh path flags
-+ *
-+ * @RTW_MESH_PATH_ACTIVE: the mesh path can be used for forwarding
-+ * @RTW_MESH_PATH_RESOLVING: the discovery process is running for this mesh path
-+ * @RTW_MESH_PATH_SN_VALID: the mesh path contains a valid destination sequence
-+ *	number
-+ * @RTW_MESH_PATH_FIXED: the mesh path has been manually set and should not be
-+ *	modified
-+ * @RTW_MESH_PATH_RESOLVED: the mesh path can has been resolved
-+ * @RTW_MESH_PATH_REQ_QUEUED: there is an unsent path request for this destination
-+ *	already queued up, waiting for the discovery process to start.
-+ * @RTW_MESH_PATH_DELETED: the mesh path has been deleted and should no longer
-+ *	be used
-+ * @RTW_MESH_PATH_ROOT_ADD_CHK: root additional check in root mode.
-+ *	With this flag, It will try the last used rann_snd_addr
-+ * @RTW_MESH_PATH_PEER_AKA: only used toward a peer, only used in active keep
-+ *	alive mechanism. PREQ's da = path dst
-+ * @RTW_MESH_PATH_BCAST_PREQ: for re-checking next hop resolve toward root.
-+ *	Use it to force path_discover sending broadcast PREQ for root.
-+ * 
-+ * RTW_MESH_PATH_RESOLVED is used by the mesh path timer to
-+ * decide when to stop or cancel the mesh path discovery.
-+ */
-+enum rtw_mesh_path_flags {
-+	RTW_MESH_PATH_ACTIVE =		BIT(0),
-+	RTW_MESH_PATH_RESOLVING =	BIT(1),
-+	RTW_MESH_PATH_SN_VALID =	BIT(2),
-+	RTW_MESH_PATH_FIXED	=	BIT(3),
-+	RTW_MESH_PATH_RESOLVED =	BIT(4),
-+	RTW_MESH_PATH_REQ_QUEUED =	BIT(5),
-+	RTW_MESH_PATH_DELETED =		BIT(6),
-+	RTW_MESH_PATH_ROOT_ADD_CHK =	BIT(7),
-+	RTW_MESH_PATH_PEER_AKA =	BIT(8),
-+	RTW_MESH_PATH_BCAST_PREQ =	BIT(9),	
-+};
-+
-+/**
-+ * struct rtw_mesh_path - mesh path structure
-+ *
-+ * @dst: mesh path destination mac address
-+ * @mpp: mesh proxy mac address
-+ * @rhash: rhashtable list pointer
-+ * @gate_list: list pointer for known gates list
-+ * @sdata: mesh subif
-+ * @next_hop: mesh neighbor to which frames for this destination will be
-+ *	forwarded
-+ * @timer: mesh path discovery timer
-+ * @frame_queue: pending queue for frames sent to this destination while the
-+ *	path is unresolved
-+ * @rcu: rcu head for freeing mesh path
-+ * @sn: target sequence number
-+ * @metric: current metric to this destination
-+ * @hop_count: hops to destination
-+ * @exp_time: in jiffies, when the path will expire or when it expired
-+ * @discovery_timeout: timeout (lapse in jiffies) used for the last discovery
-+ *	retry
-+ * @discovery_retries: number of discovery retries
-+ * @flags: mesh path flags, as specified on &enum rtw_mesh_path_flags
-+ * @state_lock: mesh path state lock used to protect changes to the
-+ * mpath itself.  No need to take this lock when adding or removing
-+ * an mpath to a hash bucket on a path table.
-+ * @rann_snd_addr: the RANN sender address
-+ * @rann_metric: the aggregated path metric towards the root node
-+ * @last_preq_to_root: Timestamp of last PREQ sent to root
-+ * @is_root: the destination station of this path is a root node
-+ * @is_gate: the destination station of this path is a mesh gate
-+ *
-+ *
-+ * The dst address is unique in the mesh path table. Since the mesh_path is
-+ * protected by RCU, deleting the next_hop STA must remove / substitute the
-+ * mesh_path structure and wait until that is no longer reachable before
-+ * destroying the STA completely.
-+ */
-+struct rtw_mesh_path {
-+	u8 dst[ETH_ALEN];
-+	u8 mpp[ETH_ALEN];	/* used for MPP or MAP */
-+	rtw_rhash_head rhash;
-+	rtw_hlist_node gate_list;
-+	_adapter *adapter;
-+	struct sta_info __rcu *next_hop;
-+	_timer timer;
-+	_queue frame_queue;
-+	u32 frame_queue_len;
-+	rtw_rcu_head rcu;
-+	u32 sn;
-+	u32 metric;
-+	u8 hop_count;
-+	systime exp_time;
-+	systime discovery_timeout;
-+	systime gate_timeout;
-+	u32 gate_ann_int;    /* gate announce interval */
-+	u8 discovery_retries;
-+	enum rtw_mesh_path_flags flags;
-+	_lock state_lock;
-+	u8 rann_snd_addr[ETH_ALEN];
-+#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK
-+	u8 add_chk_rann_snd_addr[ETH_ALEN];
-+#endif
-+	u32 rann_metric;
-+	unsigned long last_preq_to_root;
-+	bool is_root;
-+	bool is_gate;
-+	bool gate_asked;
-+};
-+
-+/**
-+ * struct rtw_mesh_table
-+ *
-+ * @known_gates: list of known mesh gates and their mpaths by the station. The
-+ * gate's mpath may or may not be resolved and active.
-+ * @gates_lock: protects updates to known_gates
-+ * @rhead: the rhashtable containing struct mesh_paths, keyed by dest addr
-+ * @entries: number of entries in the table
-+ */
-+struct rtw_mesh_table {
-+	rtw_hlist_head known_gates;
-+	_lock gates_lock;
-+	rtw_rhashtable rhead;
-+	ATOMIC_T entries;
-+};
-+
-+#define RTW_MESH_PATH_EXPIRE (600 * HZ)
-+
-+/* Maximum number of paths per interface */
-+#define RTW_MESH_MAX_MPATHS		1024
-+
-+/* Number of frames buffered per destination for unresolved destinations */
-+#define RTW_MESH_FRAME_QUEUE_LEN	10
-+
-+int rtw_mesh_nexthop_lookup(_adapter *adapter,
-+	const u8 *mda, const u8 *msa, u8 *ra);
-+int rtw_mesh_nexthop_resolve(_adapter *adapter,
-+			 struct xmit_frame *xframe);
-+
-+struct rtw_mesh_path *rtw_mesh_path_lookup(_adapter *adapter,
-+				   const u8 *dst);
-+struct rtw_mesh_path *rtw_mpp_path_lookup(_adapter *adapter,
-+				  const u8 *dst);
-+int rtw_mpp_path_add(_adapter *adapter,
-+		 const u8 *dst, const u8 *mpp);
-+void dump_mpp(void *sel, _adapter *adapter);
-+
-+struct rtw_mesh_path *
-+rtw_mesh_path_lookup_by_idx(_adapter *adapter, int idx);
-+void dump_mpath(void *sel, _adapter *adapter);
-+
-+struct rtw_mesh_path *
-+rtw_mpp_path_lookup_by_idx(_adapter *adapter, int idx);
-+void rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop);
-+void rtw_mesh_path_expire(_adapter *adapter);
-+
-+struct rtw_mesh_path *
-+rtw_mesh_path_add(_adapter *adapter, const u8 *dst);
-+
-+int rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath);
-+void rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath);
-+bool rtw_mesh_gate_search(struct rtw_mesh_table *tbl, const u8 *addr);
-+int rtw_mesh_path_send_to_gates(struct rtw_mesh_path *mpath);
-+int rtw_mesh_gate_num(_adapter *adapter);
-+bool rtw_mesh_is_primary_gate(_adapter *adapter);
-+void dump_known_gates(void *sel, _adapter *adapter);
-+
-+void rtw_mesh_plink_broken(struct sta_info *sta);
-+
-+void rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info *sta);
-+void rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath);
-+void rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath);
-+int rtw_mesh_pathtbl_init(_adapter *adapter);
-+void rtw_mesh_pathtbl_unregister(_adapter *adapter);
-+int rtw_mesh_path_del(_adapter *adapter, const u8 *addr);
-+
-+void rtw_mesh_path_flush_by_nexthop(struct sta_info *sta);
-+void rtw_mesh_path_discard_frame(_adapter *adapter,
-+			     struct xmit_frame *xframe);
-+
-+static inline void rtw_mesh_path_activate(struct rtw_mesh_path *mpath)
-+{
-+	mpath->flags |= RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVED;
-+}
-+
-+void rtw_mesh_path_flush_by_iface(_adapter *adapter);
-+
-+#endif /* __RTW_MESH_PATHTBL_H_ */
-+
-diff --git a/drivers/staging/rtl8723cs/core/monitor/rtw_radiotap.c b/drivers/staging/rtl8723cs/core/monitor/rtw_radiotap.c
-new file mode 100644
-index 000000000000..e9ebc7d7ace7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/monitor/rtw_radiotap.c
-@@ -0,0 +1,615 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_RADIOTAP_C_
-+
-+#ifdef CONFIG_WIFI_MONITOR
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#define CHAN2FREQ(a) ((a < 14) ? (2407+5*a) : (5000+5*a))
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0))
-+#define IEEE80211_RADIOTAP_ZERO_LEN_PSDU 26
-+#define IEEE80211_RADIOTAP_LSIG 27
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0))
-+#define IEEE80211_RADIOTAP_TIMESTAMP 22
-+/* For IEEE80211_RADIOTAP_TIMESTAMP */
-+#define IEEE80211_RADIOTAP_TIMESTAMP_UNIT_MASK			0x000F
-+#define IEEE80211_RADIOTAP_TIMESTAMP_UNIT_MS			0x0000
-+#define IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US			0x0001
-+#define IEEE80211_RADIOTAP_TIMESTAMP_UNIT_NS			0x0003
-+#define IEEE80211_RADIOTAP_TIMESTAMP_SPOS_MASK			0x00F0
-+#define IEEE80211_RADIOTAP_TIMESTAMP_SPOS_BEGIN_MDPU		0x0000
-+#define IEEE80211_RADIOTAP_TIMESTAMP_SPOS_EO_MPDU		0x0010
-+#define IEEE80211_RADIOTAP_TIMESTAMP_SPOS_EO_PPDU		0x0020
-+#define IEEE80211_RADIOTAP_TIMESTAMP_SPOS_PLCP_SIG_ACQ		0x0030
-+#define IEEE80211_RADIOTAP_TIMESTAMP_SPOS_UNKNOWN		0x00F0
-+
-+#define IEEE80211_RADIOTAP_TIMESTAMP_FLAG_64BIT			0x00
-+#define IEEE80211_RADIOTAP_TIMESTAMP_FLAG_32BIT			0x01
-+#define IEEE80211_RADIOTAP_TIMESTAMP_FLAG_ACCURACY		0x02
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 12, 0))
-+/* for IEEE80211_RADIOTAP_CHANNEL */
-+#define	IEEE80211_CHAN_GSM	0x1000	/* GSM (900 MHz) */
-+#define	IEEE80211_CHAN_STURBO	0x2000	/* Static Turbo */
-+#define	IEEE80211_CHAN_HALF	0x4000	/* Half channel (10 MHz wide) */
-+#define	IEEE80211_CHAN_QUARTER	0x8000	/* Quarter channel (5 MHz wide) */
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
-+#define IEEE80211_RADIOTAP_VHT 21
-+/* For IEEE80211_RADIOTAP_VHT */
-+#define IEEE80211_RADIOTAP_VHT_KNOWN_STBC			0x0001
-+#define IEEE80211_RADIOTAP_VHT_KNOWN_TXOP_PS_NA			0x0002
-+#define IEEE80211_RADIOTAP_VHT_KNOWN_GI				0x0004
-+#define IEEE80211_RADIOTAP_VHT_KNOWN_SGI_NSYM_DIS		0x0008
-+#define IEEE80211_RADIOTAP_VHT_KNOWN_LDPC_EXTRA_OFDM_SYM	0x0010
-+#define IEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED			0x0020
-+#define IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH			0x0040
-+#define IEEE80211_RADIOTAP_VHT_KNOWN_GROUP_ID			0x0080
-+#define IEEE80211_RADIOTAP_VHT_KNOWN_PARTIAL_AID		0x0100
-+
-+#define IEEE80211_RADIOTAP_VHT_FLAG_STBC			0x01
-+#define IEEE80211_RADIOTAP_VHT_FLAG_TXOP_PS_NA			0x02
-+#define IEEE80211_RADIOTAP_VHT_FLAG_SGI				0x04
-+#define IEEE80211_RADIOTAP_VHT_FLAG_SGI_NSYM_M10_9		0x08
-+#define IEEE80211_RADIOTAP_VHT_FLAG_LDPC_EXTRA_OFDM_SYM		0x10
-+#define IEEE80211_RADIOTAP_VHT_FLAG_BEAMFORMED			0x20
-+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))
-+#define IEEE80211_RADIOTAP_CODING_LDPC_USER0			0x01
-+#define IEEE80211_RADIOTAP_CODING_LDPC_USER1			0x02
-+#define IEEE80211_RADIOTAP_CODING_LDPC_USER2			0x04
-+#define IEEE80211_RADIOTAP_CODING_LDPC_USER3			0x08
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0))
-+#define IEEE80211_RADIOTAP_AMPDU_STATUS 20
-+/* For IEEE80211_RADIOTAP_AMPDU_STATUS */
-+#define IEEE80211_RADIOTAP_AMPDU_REPORT_ZEROLEN		0x0001
-+#define IEEE80211_RADIOTAP_AMPDU_IS_ZEROLEN		0x0002
-+#define IEEE80211_RADIOTAP_AMPDU_LAST_KNOWN		0x0004
-+#define IEEE80211_RADIOTAP_AMPDU_IS_LAST		0x0008
-+#define IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_ERR		0x0010
-+#define IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN	0x0020
-+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0))
-+#define IEEE80211_RADIOTAP_AMPDU_EOF			0x0040
-+#define IEEE80211_RADIOTAP_AMPDU_EOF_KNOWN		0x0080
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39))
-+#define IEEE80211_RADIOTAP_MCS 19
-+/* For IEEE80211_RADIOTAP_MCS */
-+#define IEEE80211_RADIOTAP_MCS_HAVE_BW		0x01
-+#define IEEE80211_RADIOTAP_MCS_HAVE_MCS		0x02
-+#define IEEE80211_RADIOTAP_MCS_HAVE_GI		0x04
-+#define IEEE80211_RADIOTAP_MCS_HAVE_FMT		0x08
-+#define IEEE80211_RADIOTAP_MCS_HAVE_FEC		0x10
-+
-+#define IEEE80211_RADIOTAP_MCS_BW_MASK		0x03
-+#define		IEEE80211_RADIOTAP_MCS_BW_20		0
-+#define		IEEE80211_RADIOTAP_MCS_BW_40		1
-+#define		IEEE80211_RADIOTAP_MCS_BW_20L		2
-+#define		IEEE80211_RADIOTAP_MCS_BW_20U		3
-+#define IEEE80211_RADIOTAP_MCS_SGI		0x04
-+#define IEEE80211_RADIOTAP_MCS_FMT_GF		0x08
-+#define IEEE80211_RADIOTAP_MCS_FEC_LDPC		0x10
-+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0))
-+#define IEEE80211_RADIOTAP_MCS_HAVE_STBC	0x20
-+
-+#define IEEE80211_RADIOTAP_MCS_STBC_MASK	0x60
-+#define		IEEE80211_RADIOTAP_MCS_STBC_1	1
-+#define		IEEE80211_RADIOTAP_MCS_STBC_2	2
-+#define		IEEE80211_RADIOTAP_MCS_STBC_3	3
-+#define IEEE80211_RADIOTAP_MCS_STBC_SHIFT	5
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 34))
-+#define IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE 29
-+#define IEEE80211_RADIOTAP_VENDOR_NAMESPACE 30
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 30))
-+#define IEEE80211_RADIOTAP_F_BADFCS 0x40
-+#endif
-+
-+static inline void _rtw_radiotap_fill_flags(struct rx_pkt_attrib *a, u8 *flags)
-+{
-+	struct moinfo *moif = (struct moinfo *)&a->moif;
-+
-+	if (0)
-+		*flags |= IEEE80211_RADIOTAP_F_CFP;
-+
-+	if (0)
-+		*flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
-+
-+	if ((a->encrypt == 1) || (a->encrypt == 5))
-+		*flags |= IEEE80211_RADIOTAP_F_WEP;
-+
-+	if (a->mfrag)
-+		*flags |= IEEE80211_RADIOTAP_F_FRAG;
-+
-+	if (1)
-+		*flags |= IEEE80211_RADIOTAP_F_FCS;
-+
-+	if (0)
-+		*flags |= IEEE80211_RADIOTAP_F_DATAPAD;
-+
-+	if (a->crc_err)
-+		*flags |= IEEE80211_RADIOTAP_F_BADFCS;
-+
-+	/* Currently unspecified but used
-+	   for short guard interval (HT) */
-+	if (moif->u.snif_info.sgi || a->sgi)
-+		*flags |= 0x80;
-+
-+}
-+
-+sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf)
-+{
-+#define RTAP_HDR_MAX 64
-+
-+	sint ret = _SUCCESS;
-+	struct moinfo *moif = (struct moinfo *)&a->moif;
-+
-+	u8 rx_cnt = 0;
-+
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+
-+	int i = 0;
-+	u8 tmp_8bit = 0;
-+	u16 tmp_16bit = 0;
-+	u32 tmp_32bit = 0;
-+	u64 tmp_64bit = 0;
-+
-+	_pkt *pskb = NULL;
-+
-+	struct ieee80211_radiotap_header *rtap_hdr = NULL;
-+	u8 *ptr = NULL;
-+
-+	/* 
-+	  radiotap length (include header 8)
-+	  11G length: 36 (0x0040002f)
-+	  11N length:
-+	  11AC length: 60 (0x0070002b)
-+	 */
-+	u8 hdr_buf[RTAP_HDR_MAX] = { 0 };
-+	u16 rt_len = 8;
-+
-+	/* create header */
-+	rtap_hdr = (struct ieee80211_radiotap_header *)&hdr_buf[0];
-+	rtap_hdr->it_version = PKTHDR_RADIOTAP_VERSION;
-+
-+	/* each antenna information */
-+	rx_cnt = rf_type_to_rf_rx_cnt(pHalData->rf_type);
-+#if 0
-+	if (rx_cnt > 1) {
-+		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE) |
-+		BIT(IEEE80211_RADIOTAP_EXT);
-+
-+		for (i = 1; i < rx_cnt; i++) {
-+			tmp_32bit = (BIT(IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
-+				     BIT(IEEE80211_RADIOTAP_LOCK_QUALITY) |
-+				     BIT(IEEE80211_RADIOTAP_ANTENNA) |
-+				     BIT(IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE) |
-+				     BIT(IEEE80211_RADIOTAP_EXT));
-+			_rtw_memcpy(&hdr_buf[rt_len], &tmp_32bit, 4);
-+			rt_len += 4;
-+		}
-+
-+		tmp_32bit = (BIT(IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
-+			     BIT(IEEE80211_RADIOTAP_LOCK_QUALITY) |
-+			     BIT(IEEE80211_RADIOTAP_ANTENNA));
-+		_rtw_memcpy(&hdr_buf[rt_len], &tmp_32bit, 4);
-+		rt_len += 4;
-+	}
-+#endif
-+
-+	/* tsft, Required Alignment: 8 bytes */
-+	if (0) { //(a->free_cnt) {
-+		/* TSFT + free_cnt */
-+		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_TSFT);
-+		if (!IS_ALIGNED(rt_len, 8))
-+			rt_len = ((rt_len + 7) & 0xFFF8); /* Alignment */
-+
-+		tmp_64bit = cpu_to_le64(a->free_cnt);
-+		_rtw_memcpy(&hdr_buf[rt_len], &tmp_64bit, 8);
-+		rt_len += 8;
-+	}
-+
-+	/* flags */
-+	rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_FLAGS);
-+	_rtw_radiotap_fill_flags(a, &hdr_buf[rt_len]);
-+	rt_len += 1;
-+
-+	/* rate */
-+	if (a->data_rate <= DESC_RATE54M) {
-+		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_RATE);
-+		hdr_buf[rt_len] = hw_rate_to_m_rate(a->data_rate);
-+		rt_len += 1;
-+	}
-+
-+	/* channel & flags, Required Alignment: 2 bytes */
-+	if (1) {
-+		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_CHANNEL);
-+		rt_len += (rt_len % 2); /* Alignment */
-+
-+		tmp_16bit = CHAN2FREQ(rtw_get_oper_ch(padapter));
-+		_rtw_memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
-+		rt_len += 2;
-+
-+		/* channel flags */
-+		tmp_16bit = 0;
-+		if (pHalData->current_band_type == 0)
-+			tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_2GHZ);
-+		else
-+			tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_5GHZ);
-+
-+		if (a->data_rate <= DESC_RATE11M) {
-+			/* CCK */
-+			tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_CCK);
-+		} else {
-+			/* OFDM */
-+			tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_OFDM);
-+		}
-+
-+		if (rtw_get_oper_bw(padapter) == CHANNEL_WIDTH_10) {
-+			/* 10Mhz Channel Width */
-+			tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_HALF);
-+		}
-+
-+		if (rtw_get_oper_bw(padapter) == CHANNEL_WIDTH_5) {
-+			/* 5Mhz Channel Width */
-+			tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_QUARTER);
-+		}
-+		_rtw_memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
-+		rt_len += 2;
-+	}
-+
-+	/* dBm Antenna Signal */
-+	rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_DBM_ANTSIGNAL);
-+	hdr_buf[rt_len] = a->phy_info.recv_signal_power;
-+	rt_len += 1;
-+
-+#if 0
-+	/* dBm Antenna Noise */
-+	rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_DBM_ANTNOISE);
-+	hdr_buf[rt_len] = 0;
-+	rt_len += 1;
-+#endif
-+#if 0
-+	/* Signal Quality, Required Alignment: 2 bytes */
-+	rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_LOCK_QUALITY);
-+	if (!IS_ALIGNED(rt_len, 2))
-+	rt_len++;
-+	hdr_buf[rt_len] = a->phy_info.signal_quality;
-+	rt_len += 2;
-+
-+#endif
-+
-+#if 0
-+	/* Antenna */
-+	rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_ANTENNA);
-+	hdr_buf[rt_len] = 0; /* pHalData->rf_type; */
-+	rt_len += 1;
-+#endif
-+#if 0
-+	/* RX flags, Required Alignment: 2 bytes */
-+	rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_RX_FLAGS);
-+	tmp_16bit = 0;
-+	_rtw_memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
-+	rt_len += 2;
-+#endif
-+
-+	/* MCS information, Required Alignment: 1 bytes */
-+	if (a->data_rate >= DESC_RATEMCS0 && a->data_rate <= DESC_RATEMCS31) {
-+		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_MCS);
-+		/* Structure u8 known, u8 flags, u8 mcs */
-+
-+		/* known.bandwidth */
-+		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_MCS_HAVE_BW;
-+		if (moif->u.snif_info.ofdm_bw)
-+			hdr_buf[rt_len + 1] |= IEEE80211_RADIOTAP_MCS_BW_40;
-+		if (a->bw == CHANNEL_WIDTH_40)
-+			hdr_buf[rt_len + 1] |= IEEE80211_RADIOTAP_MCS_BW_40;
-+		else
-+			hdr_buf[rt_len + 1] |= IEEE80211_RADIOTAP_MCS_BW_20;
-+
-+
-+		/* known.guard interval */
-+		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_MCS_HAVE_GI;
-+		if (moif->u.snif_info.sgi) {
-+			hdr_buf[rt_len + 1] |= IEEE80211_RADIOTAP_MCS_SGI;
-+		} else {
-+			hdr_buf[rt_len + 1] |= ((a->sgi & 0x01) << 2);
-+		}
-+
-+		/* FEC Type */
-+		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_MCS_HAVE_FEC;
-+		if (moif->u.snif_info.ldpc) {
-+			hdr_buf[rt_len + 1] |= ((moif->u.snif_info.ldpc & 0x01) << 4);
-+		} else {
-+			hdr_buf[rt_len + 1] |= ((a->ldpc & 0x01) << 4);
-+		}
-+
-+		/* STBC */
-+		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_MCS_HAVE_STBC;
-+		if (moif->u.snif_info.stbc) {
-+			hdr_buf[rt_len + 1] |= ((moif->u.snif_info.stbc & 0x03) << 5);
-+		} else {
-+			hdr_buf[rt_len + 1] |= ((a->stbc & 0x03) << 5);
-+		}
-+
-+		/* known.MCS index */
-+		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_MCS_HAVE_MCS;
-+
-+		/* u8 mcs */
-+		hdr_buf[rt_len + 2] = a->data_rate - DESC_RATEMCS0;
-+
-+		rt_len += 3;
-+	}
-+
-+	/* AMPDU, Required Alignment: 4 bytes */
-+	if (a->ampdu) {
-+		static u32 ref_num = 0x10000000;
-+		static u8 ppdu_cnt = 0;
-+
-+		/* Structure u32 reference number, u16 flags, u8 delimiter CRC value, u8 reserved */
-+		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_AMPDU_STATUS);
-+		if (!IS_ALIGNED(rt_len, 4))
-+			rt_len = ((rt_len + 3) & 0xFFFC); /* Alignment */
-+
-+		/* u32 reference number */
-+		if (a->ppdu_cnt != ppdu_cnt) {
-+			ppdu_cnt = a->ppdu_cnt;
-+			ref_num += 1;
-+		}
-+		tmp_32bit = cpu_to_le32(ref_num);
-+		_rtw_memcpy(&hdr_buf[rt_len], &tmp_32bit, 4);
-+		rt_len += 4;
-+
-+		/* u16 flags */
-+		tmp_16bit = 0;
-+		if (0) {
-+			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_REPORT_ZEROLEN);
-+			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_IS_ZEROLEN);
-+		}
-+
-+		if (0) {
-+			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_IS_LAST);
-+			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_LAST_KNOWN);
-+		}
-+
-+		if (0) {
-+			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_ERR);
-+			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN);
-+		}
-+
-+		if (a->ampdu_eof) {
-+			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_EOF_KNOWN);
-+			tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_AMPDU_EOF);
-+		}
-+
-+		_rtw_memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
-+		rt_len += 2;
-+
-+		/* u8 delimiter CRC value, u8 reserved */
-+		rt_len += 2;
-+	}
-+
-+	/* VHT, Required Alignment: 2 bytes */
-+	if (a->data_rate >= DESC_RATEVHTSS1MCS0 && a->data_rate <= DESC_RATEVHTSS4MCS9) {
-+		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_VHT);
-+
-+		rt_len += (rt_len % 2); /* Alignment */
-+
-+		/* Structure
-+		   u16 known, u8 flags, u8 bandwidth, u8 mcs_nss[4],
-+		   u8 coding, u8 group_id, u16 partial_aid */
-+
-+		tmp_16bit = 0;
-+
-+		/* STBC */
-+		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_STBC);
-+		if (moif->u.snif_info.stbc) {
-+			hdr_buf[rt_len + 2] |= IEEE80211_RADIOTAP_VHT_FLAG_STBC;
-+		} else {
-+			hdr_buf[rt_len + 2] |= (a->stbc & 0x01);
-+		}
-+
-+		/* TXOP_PS_NOT_ALLOWED */
-+		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_TXOP_PS_NA);
-+		if (moif->u.snif_info.vht_txop_not_allow) {
-+			hdr_buf[rt_len + 2] |= IEEE80211_RADIOTAP_VHT_FLAG_TXOP_PS_NA;
-+		}
-+
-+
-+		/* Guard interval */
-+		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_GI);
-+		if (moif->u.snif_info.sgi) {
-+			hdr_buf[rt_len + 2] |= IEEE80211_RADIOTAP_VHT_FLAG_SGI;
-+		} else {
-+			hdr_buf[rt_len + 2] |= ((a->sgi & 0x01) << 2);
-+		}
-+
-+		/* Short GI NSYM */
-+		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_SGI_NSYM_DIS);
-+		if (moif->u.snif_info.vht_nsym_dis) {
-+			hdr_buf[rt_len + 2] |= IEEE80211_RADIOTAP_VHT_FLAG_SGI_NSYM_M10_9;
-+		}
-+
-+		/* LDPC extra OFDM symbol */
-+		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_LDPC_EXTRA_OFDM_SYM);
-+		if (moif->u.snif_info.vht_ldpc_extra) {
-+			hdr_buf[rt_len + 2] |= IEEE80211_RADIOTAP_VHT_FLAG_LDPC_EXTRA_OFDM_SYM;
-+		} else {
-+			hdr_buf[rt_len + 2] |= ((a->ldpc & 0x01) << 4);
-+		}
-+
-+		/* Short GI NSYM */
-+		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED);
-+		if (moif->u.snif_info.vht_beamformed) {
-+			hdr_buf[rt_len + 2] |= IEEE80211_RADIOTAP_VHT_FLAG_BEAMFORMED;
-+		}
-+
-+		/* know.Bandwidth */
-+		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH);
-+
-+		/* Group ID */
-+		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_GROUP_ID);
-+
-+		/* Partial AID */
-+		tmp_16bit |= cpu_to_le16(IEEE80211_RADIOTAP_VHT_KNOWN_PARTIAL_AID);
-+
-+		_rtw_memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
-+		rt_len += 3;
-+
-+		/* u8 bandwidth */
-+		if (moif->u.snif_info.ofdm_bw)
-+			tmp_8bit = moif->u.snif_info.ofdm_bw;
-+		else
-+			tmp_8bit = a->bw;
-+
-+		switch (tmp_8bit) {
-+		case CHANNEL_WIDTH_20:
-+			hdr_buf[rt_len] |= 0;
-+			break;
-+		case CHANNEL_WIDTH_40:
-+			hdr_buf[rt_len] |= 1;
-+			break;
-+		case CHANNEL_WIDTH_80:
-+			hdr_buf[rt_len] |= 4;
-+			break;
-+		case CHANNEL_WIDTH_160:
-+			hdr_buf[rt_len] |= 11;
-+			break;
-+		default:
-+			hdr_buf[rt_len] |= 0;
-+		}
-+		rt_len += 1;
-+
-+		/* u8 mcs_nss[4] */
-+		if ((DESC_RATEVHTSS1MCS0 <= a->data_rate) &&
-+			(a->data_rate <= DESC_RATEVHTSS4MCS9)) {
-+			/* User 0 */
-+			/* MCS */
-+			hdr_buf[rt_len] = ((a->data_rate - DESC_RATEVHTSS1MCS0) % 10) << 4;
-+			/* NSS */
-+			hdr_buf[rt_len] |= (((a->data_rate - DESC_RATEVHTSS1MCS0) / 10) + 1);
-+		}
-+		rt_len += 4;
-+
-+		/* u8 coding, phystat? */
-+		hdr_buf[rt_len] = 0;
-+		rt_len += 1;
-+
-+		/* u8 group_id */
-+		hdr_buf[rt_len] = moif->u.snif_info.vht_group_id;
-+		rt_len += 1;
-+
-+		/* u16 partial_aid */
-+		tmp_16bit = cpu_to_le16(moif->u.snif_info.vht_nsts_aid);
-+		_rtw_memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
-+		rt_len += 2;
-+	}
-+
-+	/* frame timestamp, Required Alignment: 8 bytes */
-+	if (0) { //(a->free_cnt) {
-+		rtap_hdr->it_present |= BIT(IEEE80211_RADIOTAP_TIMESTAMP);
-+		if (!IS_ALIGNED(rt_len, 8))
-+			rt_len = ((rt_len + 7) & 0xFFF8); /* Alignment */
-+
-+		/* u64 timestamp */
-+		tmp_64bit = cpu_to_le64(a->free_cnt);
-+		_rtw_memcpy(&hdr_buf[rt_len], &tmp_64bit, 8);
-+		rt_len += 8;
-+
-+		/* u16 accuracy */
-+		tmp_16bit = cpu_to_le16(22);
-+		_rtw_memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
-+		rt_len += 2;
-+
-+		/* u8 unit/position */
-+		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US;
-+		rt_len += 1;
-+
-+		/* u8 flags */
-+		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_TIMESTAMP_FLAG_32BIT;
-+		hdr_buf[rt_len] |= IEEE80211_RADIOTAP_TIMESTAMP_FLAG_ACCURACY;
-+		rt_len += 1;
-+	}
-+
-+	/* each antenna information */
-+#if 0
-+	if (rx_cnt > 1) {
-+		for (i = 0; i <= rx_cnt; i++) {
-+			/* dBm Antenna Signal */
-+			hdr_buf[rt_len] = a->phy_info.rx_mimo_signal_strength[i];
-+			rt_len += 1;
-+
-+			/* Signal Quality */
-+			if (!IS_ALIGNED(rt_len, 2))
-+				rt_len++;
-+			hdr_buf[rt_len] = cpu_to_le16(a->phy_info.rx_mimo_signal_quality[i]);
-+			rt_len += 2;
-+
-+			/* Antenna */
-+			hdr_buf[rt_len] = i; /* pHalData->rf_type; */
-+			rt_len += 1;
-+		}
-+	}
-+#endif
-+
-+	/* push to skb */
-+	pskb = (_pkt *)buf;
-+	if (skb_headroom(pskb) < rt_len) {
-+		RTW_INFO("%s:%d %s headroom is too small.\n", __FILE__, __LINE__, __func__);
-+		ret = _FAIL;
-+		return ret;
-+	}
-+
-+	ptr = skb_push(pskb, rt_len);
-+	if (ptr) {
-+		rtap_hdr->it_len = cpu_to_le16(rt_len);
-+		rtap_hdr->it_present = cpu_to_le32(rtap_hdr->it_present);
-+		memcpy(ptr, rtap_hdr, rt_len);
-+	} else
-+		ret = _FAIL;
-+
-+	return ret;
-+
-+}
-+
-+void rx_query_moinfo(struct rx_pkt_attrib *a, u8 *desc)
-+{
-+	switch (a->drvinfo_sz) {
-+	case 40:
-+		_rtw_memcpy(a->moif, &desc[32], 8);
-+		break;
-+	case 48:
-+		_rtw_memcpy(a->moif, &desc[32], 12);
-+		break;
-+	case 32:
-+		/* passthrough */
-+	default:
-+		break;
-+	}
-+}
-+
-+#endif /* CONFIG_WIFI_MONITOR */
-diff --git a/drivers/staging/rtl8723cs/core/monitor/rtw_radiotap.h b/drivers/staging/rtl8723cs/core/monitor/rtw_radiotap.h
-new file mode 100644
-index 000000000000..affacd1855b4
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/monitor/rtw_radiotap.h
-@@ -0,0 +1,63 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_RADIOTAP_H_
-+#define __RTW_RADIOTAP_H_
-+
-+struct mon_reg_backup {
-+	/* flags */
-+	u8	known_rcr:1;
-+	u8	known_drvinfo:1;
-+	u8	known_rxfilter:1;
-+	u8	known_misc0:1;
-+	/* data */
-+	u8	drvinfo;
-+	u16	rxfilter0;
-+	u16	rxfilter1;
-+	u16	rxfilter2;
-+	u32	rcr;
-+	u32	misc0;
-+};
-+
-+struct moinfo {
-+	union {
-+		struct  {
-+			u32	sgi:1;
-+			u32	ldpc:1;
-+			u32	stbc:2;
-+			u32	not_sounding:1;
-+			u32	ofdm_bw:2;
-+			u32	vht_group_id:2;
-+			u32	vht_nsts_aid:12;
-+			u32	vht_txop_not_allow:1;
-+			u32	vht_nsym_dis:1;
-+			u32	vht_ldpc_extra:1;
-+			u32	vht_su_mcs:12;
-+			u32	vht_beamformed:1;
-+		}snif_info;
-+
-+		struct  {
-+			u32	A;
-+			u32	B;
-+			u32	C;
-+		}plcp_info;
-+	}u;
-+};
-+
-+sint rtw_fill_radiotap_hdr(_adapter *padapter, struct rx_pkt_attrib *a, u8 *buf);
-+
-+void rx_query_moinfo(struct rx_pkt_attrib *a, u8 *desc);
-+
-+#endif /* __RTW_RADIOTAP_H_ */
-+
-diff --git a/drivers/staging/rtl8723cs/core/rtw_ap.c b/drivers/staging/rtl8723cs/core/rtw_ap.c
-new file mode 100644
-index 000000000000..bd4632e4516c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_ap.c
-@@ -0,0 +1,5992 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_AP_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#ifdef CONFIG_AP_MODE
-+
-+extern unsigned char	RTW_WPA_OUI[];
-+extern unsigned char	WMM_OUI[];
-+extern unsigned char	WPS_OUI[];
-+extern unsigned char	P2P_OUI[];
-+extern unsigned char	WFD_OUI[];
-+
-+void init_mlme_ap_info(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	_rtw_spinlock_init(&pmlmepriv->bcn_update_lock);
-+	/* pmlmeext->bstart_bss = _FALSE; */
-+}
-+
-+void free_mlme_ap_info(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	stop_ap_mode(padapter);
-+	_rtw_spinlock_free(&pmlmepriv->bcn_update_lock);
-+
-+}
-+
-+/*
-+* Set TIM IE
-+* return length of total TIM IE
-+*/
-+u8 rtw_set_tim_ie(u8 dtim_cnt, u8 dtim_period
-+	, const u8 *tim_bmp, u8 tim_bmp_len, u8 *tim_ie)
-+{
-+	u8 *p = tim_ie;
-+	u8 i, n1, n2;
-+	u8 bmp_len;
-+
-+	if (rtw_bmp_not_empty(tim_bmp, tim_bmp_len)) {
-+		/* find the first nonzero octet in tim_bitmap */
-+		for (i = 0; i < tim_bmp_len; i++)
-+			if (tim_bmp[i])
-+				break;
-+		n1 = i & 0xFE;
-+	
-+		/* find the last nonzero octet in tim_bitmap, except octet 0 */
-+		for (i = tim_bmp_len - 1; i > 0; i--)
-+			if (tim_bmp[i])
-+				break;
-+		n2 = i;
-+		bmp_len = n2 - n1 + 1;
-+	} else {
-+		n1 = n2 = 0;
-+		bmp_len = 1;
-+	}
-+
-+	*p++ = WLAN_EID_TIM;
-+	*p++ = 2 + 1 + bmp_len;
-+	*p++ = dtim_cnt;
-+	*p++ = dtim_period;
-+	*p++ = (rtw_bmp_is_set(tim_bmp, tim_bmp_len, 0) ? BIT0 : 0) | n1;
-+	_rtw_memcpy(p, tim_bmp + n1, bmp_len);
-+
-+#if 0
-+	RTW_INFO("n1:%u, n2:%u, bmp_offset:%u, bmp_len:%u\n", n1, n2, n1 / 2, bmp_len);
-+	RTW_INFO_DUMP("tim_ie: ", tim_ie + 2, 2 + 1 + bmp_len);
-+#endif
-+	return 2 + 2 + 1 + bmp_len;
-+}
-+
-+static void update_BCNTIM(_adapter *padapter)
-+{
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network);
-+	unsigned char *pie = pnetwork_mlmeext->IEs;
-+
-+#if 0
-+
-+
-+	/* update TIM IE */
-+	/* if(rtw_tim_map_anyone_be_set(padapter, pstapriv->tim_bitmap)) */
-+#endif
-+	if (_TRUE) {
-+		u8 *p, *dst_ie, *premainder_ie = NULL, *pbackup_remainder_ie = NULL;
-+		uint offset, tmp_len, tim_ielen, tim_ie_offset, remainder_ielen;
-+
-+		p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, _TIM_IE_, &tim_ielen, pnetwork_mlmeext->IELength - _FIXED_IE_LENGTH_);
-+		if (p != NULL && tim_ielen > 0) {
-+			tim_ielen += 2;
-+
-+			premainder_ie = p + tim_ielen;
-+
-+			tim_ie_offset = (sint)(p - pie);
-+
-+			remainder_ielen = pnetwork_mlmeext->IELength - tim_ie_offset - tim_ielen;
-+
-+			/*append TIM IE from dst_ie offset*/
-+			dst_ie = p;
-+		} else {
-+			tim_ielen = 0;
-+
-+			/*calculate head_len*/
-+			offset = _FIXED_IE_LENGTH_;
-+
-+			/* get ssid_ie len */
-+			p = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SSID_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_));
-+			if (p != NULL)
-+				offset += tmp_len + 2;
-+
-+			/*get supported rates len*/
-+			p = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_));
-+			if (p !=  NULL)
-+				offset += tmp_len + 2;
-+
-+			/*DS Parameter Set IE, len=3*/
-+			offset += 3;
-+
-+			premainder_ie = pie + offset;
-+
-+			remainder_ielen = pnetwork_mlmeext->IELength - offset - tim_ielen;
-+
-+			/*append TIM IE from offset*/
-+			dst_ie = pie + offset;
-+
-+		}
-+
-+		if (remainder_ielen > 0) {
-+			pbackup_remainder_ie = rtw_malloc(remainder_ielen);
-+			if (pbackup_remainder_ie && premainder_ie)
-+				_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
-+		}
-+
-+		/* append TIM IE */
-+		dst_ie += rtw_set_tim_ie(0, 1, pstapriv->tim_bitmap, pstapriv->aid_bmp_len, dst_ie);
-+
-+		/*copy remainder IE*/
-+		if (pbackup_remainder_ie) {
-+			_rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);
-+
-+			rtw_mfree(pbackup_remainder_ie, remainder_ielen);
-+		}
-+
-+		offset = (uint)(dst_ie - pie);
-+		pnetwork_mlmeext->IELength = offset + remainder_ielen;
-+
-+	}
-+}
-+
-+void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len)
-+{
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	u8	bmatch = _FALSE;
-+	u8	*pie = pnetwork->IEs;
-+	u8	*p = NULL, *dst_ie = NULL, *premainder_ie = NULL, *pbackup_remainder_ie = NULL;
-+	u32	i, offset, ielen = 0, ie_offset, remainder_ielen = 0;
-+
-+	for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pnetwork->IELength;) {
-+		pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i);
-+
-+		if (pIE->ElementID > index)
-+			break;
-+		else if (pIE->ElementID == index) { /* already exist the same IE */
-+			p = (u8 *)pIE;
-+			ielen = pIE->Length;
-+			bmatch = _TRUE;
-+			break;
-+		}
-+
-+		p = (u8 *)pIE;
-+		ielen = pIE->Length;
-+		i += (pIE->Length + 2);
-+	}
-+
-+	if (p != NULL && ielen > 0) {
-+		ielen += 2;
-+
-+		premainder_ie = p + ielen;
-+
-+		ie_offset = (sint)(p - pie);
-+
-+		remainder_ielen = pnetwork->IELength - ie_offset - ielen;
-+
-+		if (bmatch)
-+			dst_ie = p;
-+		else
-+			dst_ie = (p + ielen);
-+	}
-+
-+	if (dst_ie == NULL)
-+		return;
-+
-+	if (remainder_ielen > 0) {
-+		pbackup_remainder_ie = rtw_malloc(remainder_ielen);
-+		if (pbackup_remainder_ie && premainder_ie)
-+			_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
-+	}
-+
-+	*dst_ie++ = index;
-+	*dst_ie++ = len;
-+
-+	_rtw_memcpy(dst_ie, data, len);
-+	dst_ie += len;
-+
-+	/* copy remainder IE */
-+	if (pbackup_remainder_ie) {
-+		_rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);
-+
-+		rtw_mfree(pbackup_remainder_ie, remainder_ielen);
-+	}
-+
-+	offset = (uint)(dst_ie - pie);
-+	pnetwork->IELength = offset + remainder_ielen;
-+}
-+
-+void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index)
-+{
-+	u8 *p, *dst_ie = NULL, *premainder_ie = NULL, *pbackup_remainder_ie = NULL;
-+	uint offset, ielen, ie_offset, remainder_ielen = 0;
-+	u8	*pie = pnetwork->IEs;
-+
-+	p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, index, &ielen, pnetwork->IELength - _FIXED_IE_LENGTH_);
-+	if (p != NULL && ielen > 0) {
-+		ielen += 2;
-+
-+		premainder_ie = p + ielen;
-+
-+		ie_offset = (sint)(p - pie);
-+
-+		remainder_ielen = pnetwork->IELength - ie_offset - ielen;
-+
-+		dst_ie = p;
-+	} else
-+		return;
-+
-+	if (remainder_ielen > 0) {
-+		pbackup_remainder_ie = rtw_malloc(remainder_ielen);
-+		if (pbackup_remainder_ie && premainder_ie)
-+			_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
-+	}
-+
-+	/* copy remainder IE */
-+	if (pbackup_remainder_ie) {
-+		_rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen);
-+
-+		rtw_mfree(pbackup_remainder_ie, remainder_ielen);
-+	}
-+
-+	offset = (uint)(dst_ie - pie);
-+	pnetwork->IELength = offset + remainder_ielen;
-+}
-+
-+
-+u8 chk_sta_is_alive(struct sta_info *psta);
-+u8 chk_sta_is_alive(struct sta_info *psta)
-+{
-+	u8 ret = _FALSE;
-+#ifdef DBG_EXPIRATION_CHK
-+	RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", expire_to:%u, %s%ssq_len:%u\n"
-+		 , MAC_ARG(psta->cmn.mac_addr)
-+		 , psta->cmn.rssi_stat.rssi
-+		 /* , STA_RX_PKTS_ARG(psta) */
-+		 , STA_RX_PKTS_DIFF_ARG(psta)
-+		 , psta->expire_to
-+		 , psta->state & WIFI_SLEEP_STATE ? "PS, " : ""
-+		 , psta->state & WIFI_STA_ALIVE_CHK_STATE ? "SAC, " : ""
-+		 , psta->sleepq_len
-+		);
-+#endif
-+
-+	/* if(sta_last_rx_pkts(psta) == sta_rx_pkts(psta)) */
-+	if ((psta->sta_stats.last_rx_data_pkts + psta->sta_stats.last_rx_ctrl_pkts) == (psta->sta_stats.rx_data_pkts + psta->sta_stats.rx_ctrl_pkts)) {
-+#if 0
-+		if (psta->state & WIFI_SLEEP_STATE)
-+			ret = _TRUE;
-+#endif
-+	} else
-+		ret = _TRUE;
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(psta->padapter)) {
-+		u8 bcn_alive, hwmp_alive;
-+
-+		hwmp_alive = (psta->sta_stats.rx_hwmp_pkts !=
-+			      psta->sta_stats.last_rx_hwmp_pkts);
-+		bcn_alive = (psta->sta_stats.rx_beacon_pkts != 
-+			     psta->sta_stats.last_rx_beacon_pkts);
-+		/* The reference for nexthop_lookup */
-+		psta->alive = ret || hwmp_alive || bcn_alive;
-+		/* The reference for expire_timeout_chk */
-+		/* Exclude bcn_alive to avoid a misjudge condition
-+		   that a peer unexpectedly leave and restart quickly*/
-+		ret = ret || hwmp_alive;
-+	}
-+#endif
-+
-+	sta_update_last_rx_pkts(psta);
-+
-+	return ret;
-+}
-+
-+/**
-+ * issue_aka_chk_frame - issue active keep alive check frame
-+ *	aka = active keep alive
-+ */
-+#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-+static int issue_aka_chk_frame(_adapter *adapter, struct sta_info *psta)
-+{
-+	int ret = _FAIL;
-+	u8 *target_addr = psta->cmn.mac_addr;
-+
-+	if (MLME_IS_AP(adapter)) {
-+		/* issue null data to check sta alive */
-+		if (psta->state & WIFI_SLEEP_STATE)
-+			ret = issue_nulldata(adapter, target_addr, 0, 1, 50);
-+		else
-+			ret = issue_nulldata(adapter, target_addr, 0, 3, 50);
-+	}
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(adapter)) {
-+		struct rtw_mesh_path *mpath;
-+
-+		rtw_rcu_read_lock();
-+		mpath = rtw_mesh_path_lookup(adapter, target_addr);
-+		if (!mpath) {
-+			mpath = rtw_mesh_path_add(adapter, target_addr);
-+			if (IS_ERR(mpath)) {
-+				rtw_rcu_read_unlock();
-+				RTW_ERR(FUNC_ADPT_FMT" rtw_mesh_path_add for "MAC_FMT" fail.\n",
-+					FUNC_ADPT_ARG(adapter), MAC_ARG(target_addr));
-+				return _FAIL;
-+			}
-+		}
-+		if (mpath->flags & RTW_MESH_PATH_ACTIVE)
-+			ret = _SUCCESS;
-+		else {
-+			u8 flags = RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_PEER_AKA;
-+			/* issue PREQ to check peer alive */
-+			rtw_mesh_queue_preq(mpath, flags);
-+			ret = _FALSE;
-+		}
-+		rtw_rcu_read_unlock();
-+	}
-+#endif
-+	return ret;
-+}
-+#endif
-+
-+#ifdef RTW_CONFIG_RFREG18_WA
-+static void rtw_check_restore_rf18(_adapter *padapter)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+	u32 reg;
-+	u8 union_ch = 0, union_bw = 0, union_offset = 0, setchbw = _FALSE;
-+		
-+	reg = rtw_hal_read_rfreg(padapter, 0, 0x18, 0x3FF);
-+	if ((reg & 0xFF) == 0)
-+			setchbw = _TRUE;
-+	reg = rtw_hal_read_rfreg(padapter, 1, 0x18, 0x3FF);
-+	if ((reg & 0xFF) == 0)
-+			setchbw = _TRUE;
-+
-+	if (setchbw) {
-+		if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset)) {
-+			RTW_INFO("Hit RF(0x18)=0!! restore original channel setting.\n");
-+			union_ch =  pmlmeext->cur_channel;
-+			union_offset = pmlmeext->cur_ch_offset ;
-+			union_bw = pmlmeext->cur_bwmode;
-+		} else {
-+			RTW_INFO("Hit RF(0x18)=0!! set ch(%x) offset(%x) bwmode(%x)\n", union_ch, union_offset, union_bw);
-+		}
-+		/*	Initial the channel_bw setting procedure.	*/
-+		pHalData->current_channel = 0;
-+		set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
-+	}
-+}
-+#endif
-+
-+void	expire_timeout_chk(_adapter *padapter)
-+{
-+	_irqL irqL;
-+	_list	*phead, *plist;
-+	u8 updated = _FALSE;
-+	struct sta_info *psta = NULL;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	u8 chk_alive_num = 0;
-+	char chk_alive_list[NUM_STA];
-+	int i;
-+	int stainfo_offset;
-+	u8 flush_num = 0;
-+	char flush_list[NUM_STA]={0};
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(padapter)
-+		&& check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)
-+	) {
-+		struct rtw_mesh_cfg *mcfg = &padapter->mesh_cfg;
-+
-+		rtw_mesh_path_expire(padapter);
-+
-+		/* TBD: up layer timeout mechanism */
-+		/* if (!mcfg->plink_timeout)
-+			return; */
-+#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-+		return;
-+#endif
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTW_WDS
-+	rtw_wds_path_expire(padapter);
-+#endif
-+
-+#ifdef CONFIG_MCC_MODE
-+	/*	then driver may check fail due to not recv client's frame under sitesurvey,
-+	 *	don't expire timeout chk under MCC under sitesurvey */
-+
-+	if (rtw_hal_mcc_link_status_chk(padapter, __func__) == _FALSE)
-+		return;
-+#endif
-+
-+	_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);
-+
-+	phead = &pstapriv->auth_list;
-+	plist = get_next(phead);
-+
-+	/* check auth_queue */
-+#ifdef DBG_EXPIRATION_CHK
-+	if (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+		RTW_INFO(FUNC_ADPT_FMT" auth_list, cnt:%u\n"
-+			, FUNC_ADPT_ARG(padapter), pstapriv->auth_list_cnt);
-+	}
-+#endif
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+		psta = LIST_CONTAINOR(plist, struct sta_info, auth_list);
-+
-+		plist = get_next(plist);
-+
-+
-+#ifdef CONFIG_ATMEL_RC_PATCH
-+		if (_rtw_memcmp((void *)(pstapriv->atmel_rc_pattern), (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE)
-+			continue;
-+		if (psta->flag_atmel_rc)
-+			continue;
-+#endif
-+		if (psta->expire_to > 0) {
-+			psta->expire_to--;
-+			if (psta->expire_to == 0) {
-+				stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
-+				if (stainfo_offset_valid(stainfo_offset))
-+					flush_list[flush_num++] = stainfo_offset;
-+				else
-+					rtw_warn_on(1);
-+			}
-+		}
-+
-+	}
-+
-+	_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
-+	for (i = 0; i < flush_num; i++) {
-+		psta = rtw_get_stainfo_by_offset(pstapriv, flush_list[i]);
-+		RTW_INFO(FUNC_ADPT_FMT" auth expire "MAC_FMT"\n"
-+			, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
-+		rtw_free_stainfo(padapter, psta);
-+		psta = NULL;
-+	}
-+
-+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+	phead = &pstapriv->asoc_list;
-+	plist = get_next(phead);
-+
-+	/* check asoc_queue */
-+#ifdef DBG_EXPIRATION_CHK
-+	if (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+		RTW_INFO(FUNC_ADPT_FMT" asoc_list, cnt:%u\n"
-+			, FUNC_ADPT_ARG(padapter), pstapriv->asoc_list_cnt);
-+	}
-+#endif
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+		plist = get_next(plist);
-+#ifdef CONFIG_ATMEL_RC_PATCH
-+		RTW_INFO("%s:%d  psta=%p, %02x,%02x||%02x,%02x  \n\n", __func__,  __LINE__,
-+			psta, pstapriv->atmel_rc_pattern[0], pstapriv->atmel_rc_pattern[5], psta->cmn.mac_addr[0], psta->cmn.mac_addr[5]);
-+		if (_rtw_memcmp((void *)pstapriv->atmel_rc_pattern, (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE)
-+			continue;
-+		if (psta->flag_atmel_rc)
-+			continue;
-+		RTW_INFO("%s: debug line:%d\n", __func__, __LINE__);
-+#endif
-+#ifdef CONFIG_AUTO_AP_MODE
-+		if (psta->isrc)
-+			continue;
-+#endif
-+		if (chk_sta_is_alive(psta) || !psta->expire_to) {
-+			psta->expire_to = pstapriv->expire_to;
-+			psta->keep_alive_trycnt = 0;
-+			#if !defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && defined(CONFIG_80211N_HT)
-+			psta->under_exist_checking = 0;
-+			#endif
-+		} else
-+			psta->expire_to--;
-+
-+#if !defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && defined(CONFIG_80211N_HT)
-+		if ((psta->flags & WLAN_STA_HT) && (psta->htpriv.agg_enable_bitmap || psta->under_exist_checking)) {
-+			/* check sta by delba(addba) for 11n STA */
-+			/* ToDo: use CCX report to check for all STAs */
-+			/* RTW_INFO("asoc check by DELBA/ADDBA! (pstapriv->expire_to=%d s)(psta->expire_to=%d s), [%02x, %d]\n", pstapriv->expire_to*2, psta->expire_to*2, psta->htpriv.agg_enable_bitmap, psta->under_exist_checking); */
-+			if (psta->expire_to <= (pstapriv->expire_to - 50)) {
-+				RTW_INFO("asoc expire by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to - psta->expire_to) * 2);
-+				psta->under_exist_checking = 0;
-+				psta->expire_to = 0;
-+			} else if (psta->expire_to <= (pstapriv->expire_to - 3) && (psta->under_exist_checking == 0)) {
-+				RTW_INFO("asoc check by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to - psta->expire_to) * 2);
-+				psta->under_exist_checking = 1;
-+				/* tear down TX AMPDU */
-+				send_delba(padapter, 1, psta->cmn.mac_addr);/*  */ /* originator */
-+				psta->htpriv.agg_enable_bitmap = 0x0;/* reset */
-+				psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */
-+			}
-+		}
-+#endif /* !defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && defined(CONFIG_80211N_HT) */
-+
-+		if (psta->expire_to <= 0) {
-+			struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+
-+			if (padapter->registrypriv.wifi_spec == 1) {
-+				psta->expire_to = pstapriv->expire_to;
-+				continue;
-+			}
-+
-+#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-+#ifdef CONFIG_80211N_HT
-+
-+#define KEEP_ALIVE_TRYCNT (3)
-+
-+			if (psta->keep_alive_trycnt > 0 && psta->keep_alive_trycnt <= KEEP_ALIVE_TRYCNT) {
-+				if (psta->state & WIFI_STA_ALIVE_CHK_STATE)
-+					psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
-+				else
-+					psta->keep_alive_trycnt = 0;
-+
-+			} else if ((psta->keep_alive_trycnt > KEEP_ALIVE_TRYCNT) && !(psta->state & WIFI_STA_ALIVE_CHK_STATE))
-+				psta->keep_alive_trycnt = 0;
-+			if ((psta->htpriv.ht_option == _TRUE) && (psta->htpriv.ampdu_enable == _TRUE)) {
-+				uint priority = 1; /* test using BK */
-+				u8 issued = 0;
-+
-+				/* issued = (psta->htpriv.agg_enable_bitmap>>priority)&0x1; */
-+				issued |= (psta->htpriv.candidate_tid_bitmap >> priority) & 0x1;
-+
-+				if (0 == issued) {
-+					if (!(psta->state & WIFI_STA_ALIVE_CHK_STATE)) {
-+						psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority);
-+
-+						if (psta->state & WIFI_SLEEP_STATE)
-+							psta->expire_to = 2; /* 2x2=4 sec */
-+						else
-+							psta->expire_to = 1; /* 2 sec */
-+
-+						psta->state |= WIFI_STA_ALIVE_CHK_STATE;
-+
-+						/* add_ba_hdl(padapter, (u8*)paddbareq_parm); */
-+
-+						RTW_INFO("issue addba_req to check if sta alive, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt);
-+
-+						issue_addba_req(padapter, psta->cmn.mac_addr, (u8)priority);
-+
-+						_set_timer(&psta->addba_retry_timer, ADDBA_TO);
-+
-+						psta->keep_alive_trycnt++;
-+
-+						continue;
-+					}
-+				}
-+			}
-+			if (psta->keep_alive_trycnt > 0 && psta->state & WIFI_STA_ALIVE_CHK_STATE) {
-+				psta->keep_alive_trycnt = 0;
-+				psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
-+				RTW_INFO("change to another methods to check alive if staion is at ps mode\n");
-+			}
-+
-+#endif /* CONFIG_80211N_HT */
-+#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK	 */
-+			if (psta->state & WIFI_SLEEP_STATE) {
-+				if (!(psta->state & WIFI_STA_ALIVE_CHK_STATE)) {
-+					/* to check if alive by another methods if staion is at ps mode.					 */
-+					psta->expire_to = pstapriv->expire_to;
-+					psta->state |= WIFI_STA_ALIVE_CHK_STATE;
-+
-+					/* RTW_INFO("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->cmn.mac_addr)); */
-+
-+					/* to update bcn with tim_bitmap for this station */
-+					rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
-+					update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0);
-+
-+					if (!pmlmeext->active_keep_alive_check)
-+						continue;
-+				}
-+			}
-+
-+			{
-+				int stainfo_offset;
-+
-+				stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
-+				if (stainfo_offset_valid(stainfo_offset))
-+					chk_alive_list[chk_alive_num++] = stainfo_offset;
-+				continue;
-+			}
-+		} else {
-+			/* TODO: Aging mechanism to digest frames in sleep_q to avoid running out of xmitframe */
-+			if (psta->sleepq_len > (NR_XMITFRAME / pstapriv->asoc_list_cnt)
-+			    && padapter->xmitpriv.free_xmitframe_cnt < ((NR_XMITFRAME / pstapriv->asoc_list_cnt) / 2)
-+			   ) {
-+				RTW_INFO(FUNC_ADPT_FMT" sta:"MAC_FMT", sleepq_len:%u, free_xmitframe_cnt:%u, asoc_list_cnt:%u, clear sleep_q\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, psta->sleepq_len, padapter->xmitpriv.free_xmitframe_cnt, pstapriv->asoc_list_cnt);
-+				wakeup_sta_to_xmit(padapter, psta);
-+			}
-+		}
-+	}
-+
-+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+	if (chk_alive_num) {
-+#if defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK)
-+		u8 backup_ch = 0, backup_bw = 0, backup_offset = 0;
-+		u8 union_ch = 0, union_bw = 0, union_offset = 0;
-+		u8 switch_channel_by_drv = _TRUE;
-+		struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+#endif
-+		char del_asoc_list[NUM_STA];
-+
-+		_rtw_memset(del_asoc_list, NUM_STA, NUM_STA);
-+
-+		#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-+		if (pmlmeext->active_keep_alive_check) {
-+			#ifdef CONFIG_MCC_MODE
-+			if (MCC_EN(padapter)) {
-+				/* driver doesn't switch channel under MCC */
-+				if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
-+					switch_channel_by_drv = _FALSE;
-+			}
-+			#endif
-+
-+			if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset)
-+				|| pmlmeext->cur_channel != union_ch)
-+				switch_channel_by_drv = _FALSE;
-+
-+			/* switch to correct channel of current network  before issue keep-alive frames */
-+			if (switch_channel_by_drv == _TRUE && rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) {
-+				backup_ch = rtw_get_oper_ch(padapter);
-+				backup_bw = rtw_get_oper_bw(padapter);
-+				backup_offset = rtw_get_oper_choffset(padapter);
-+				set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
-+			}
-+		}
-+		#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
-+
-+		/* check loop */
-+		for (i = 0; i < chk_alive_num; i++) {
-+			#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-+			int ret = _FAIL;
-+			#endif
-+
-+			psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);
-+
-+			#ifdef CONFIG_ATMEL_RC_PATCH
-+			if (_rtw_memcmp(pstapriv->atmel_rc_pattern, psta->cmn.mac_addr, ETH_ALEN) == _TRUE)
-+				continue;
-+			if (psta->flag_atmel_rc)
-+				continue;
-+			#endif
-+
-+			if (!(psta->state & WIFI_ASOC_STATE))
-+				continue;
-+
-+			#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-+			if (pmlmeext->active_keep_alive_check) {
-+				/* issue active keep alive frame to check */
-+				ret = issue_aka_chk_frame(padapter, psta);
-+
-+				psta->keep_alive_trycnt++;
-+				if (ret == _SUCCESS) {
-+					RTW_INFO(FUNC_ADPT_FMT" asoc check, "MAC_FMT" is alive\n"
-+						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
-+					psta->expire_to = pstapriv->expire_to;
-+					psta->keep_alive_trycnt = 0;
-+					continue;
-+				} else if (psta->keep_alive_trycnt <= 3) {
-+					RTW_INFO(FUNC_ADPT_FMT" asoc check, "MAC_FMT" keep_alive_trycnt=%d\n"
-+						, FUNC_ADPT_ARG(padapter) , MAC_ARG(psta->cmn.mac_addr), psta->keep_alive_trycnt);
-+					psta->expire_to = 1;
-+					continue;
-+				}
-+			}
-+			#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
-+
-+			psta->keep_alive_trycnt = 0;
-+			del_asoc_list[i] = chk_alive_list[i];
-+			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+			if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
-+				rtw_list_delete(&psta->asoc_list);
-+				pstapriv->asoc_list_cnt--;
-+				#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+				if (psta->tbtx_enable)
-+					pstapriv->tbtx_asoc_list_cnt--;
-+				#endif				
-+				STA_SET_MESH_PLINK(psta, NULL);
-+			}
-+			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+		}
-+
-+		/* delete loop */
-+		for (i = 0; i < chk_alive_num; i++) {
-+			u8 sta_addr[ETH_ALEN];
-+
-+			if (del_asoc_list[i] >= NUM_STA)
-+				continue;
-+
-+			psta = rtw_get_stainfo_by_offset(pstapriv, del_asoc_list[i]);
-+			_rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN);
-+
-+			RTW_INFO(FUNC_ADPT_FMT" asoc expire "MAC_FMT", state=0x%x\n"
-+				, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr), psta->state);
-+			updated |= ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _FALSE);
-+			#ifdef CONFIG_RTW_MESH
-+			if (MLME_IS_MESH(padapter))
-+				rtw_mesh_expire_peer(padapter, sta_addr);
-+			#endif
-+		}
-+
-+		#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-+		if (pmlmeext->active_keep_alive_check) {
-+			/* back to the original operation channel */
-+			if (switch_channel_by_drv == _TRUE && backup_ch > 0)
-+				set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw);
-+		}
-+		#endif
-+	}
-+
-+#ifdef RTW_CONFIG_RFREG18_WA
-+	rtw_check_restore_rf18(padapter);
-+#endif
-+	associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
-+}
-+
-+void rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta)
-+{
-+	unsigned char sta_band = 0;
-+	u64 tx_ra_bitmap = 0;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
-+
-+	if (!psta)
-+		return;
-+
-+	if (!(psta->state & WIFI_ASOC_STATE))
-+		return;
-+
-+	rtw_hal_update_sta_ra_info(padapter, psta);
-+	tx_ra_bitmap = psta->cmn.ra_info.ramask;
-+
-+	if (pcur_network->Configuration.DSConfig > 14) {
-+
-+		if (tx_ra_bitmap & 0xffff000)
-+			sta_band |= WIRELESS_11_5N;
-+
-+		if (tx_ra_bitmap & 0xff0)
-+			sta_band |= WIRELESS_11A;
-+
-+		/* 5G band */
-+#ifdef CONFIG_80211AC_VHT
-+		if (psta->vhtpriv.vht_option)
-+			sta_band = WIRELESS_11_5AC;
-+#endif
-+	} else {
-+		if (tx_ra_bitmap & 0xffff000)
-+			sta_band |= WIRELESS_11_24N;
-+
-+		if (tx_ra_bitmap & 0xff0)
-+			sta_band |= WIRELESS_11G;
-+
-+		if (tx_ra_bitmap & 0x0f)
-+			sta_band |= WIRELESS_11B;
-+	}
-+
-+	psta->wireless_mode = sta_band;
-+	rtw_hal_update_sta_wset(padapter, psta);
-+	RTW_INFO("%s=> mac_id:%d , tx_ra_bitmap:0x%016llx, networkType:0x%02x\n",
-+			__FUNCTION__, psta->cmn.mac_id, tx_ra_bitmap, psta->wireless_mode);
-+}
-+
-+#ifdef CONFIG_BMC_TX_RATE_SELECT
-+u8 rtw_ap_find_mini_tx_rate(_adapter *adapter)
-+{
-+	_irqL irqL;
-+	_list	*phead, *plist;
-+	u8 miini_tx_rate = ODM_RATEVHTSS4MCS9, sta_tx_rate;
-+	struct sta_info *psta = NULL;
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+
-+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+	phead = &pstapriv->asoc_list;
-+	plist = get_next(phead);
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+		plist = get_next(plist);
-+
-+		sta_tx_rate = psta->cmn.ra_info.curr_tx_rate & 0x7F;
-+		if (sta_tx_rate < miini_tx_rate)
-+			miini_tx_rate = sta_tx_rate;
-+	}
-+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+	return miini_tx_rate;
-+}
-+
-+u8 rtw_ap_find_bmc_rate(_adapter *adapter, u8 tx_rate)
-+{
-+	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA(adapter);
-+	u8 tx_ini_rate = ODM_RATE6M;
-+
-+	switch (tx_rate) {
-+	case ODM_RATEVHTSS3MCS9:
-+	case ODM_RATEVHTSS3MCS8:
-+	case ODM_RATEVHTSS3MCS7:
-+	case ODM_RATEVHTSS3MCS6:
-+	case ODM_RATEVHTSS3MCS5:
-+	case ODM_RATEVHTSS3MCS4:
-+	case ODM_RATEVHTSS3MCS3:
-+	case ODM_RATEVHTSS2MCS9:
-+	case ODM_RATEVHTSS2MCS8:
-+	case ODM_RATEVHTSS2MCS7:
-+	case ODM_RATEVHTSS2MCS6:
-+	case ODM_RATEVHTSS2MCS5:
-+	case ODM_RATEVHTSS2MCS4:
-+	case ODM_RATEVHTSS2MCS3:
-+	case ODM_RATEVHTSS1MCS9:
-+	case ODM_RATEVHTSS1MCS8:
-+	case ODM_RATEVHTSS1MCS7:
-+	case ODM_RATEVHTSS1MCS6:
-+	case ODM_RATEVHTSS1MCS5:
-+	case ODM_RATEVHTSS1MCS4:
-+	case ODM_RATEVHTSS1MCS3:
-+	case ODM_RATEMCS15:
-+	case ODM_RATEMCS14:
-+	case ODM_RATEMCS13:
-+	case ODM_RATEMCS12:
-+	case ODM_RATEMCS11:
-+	case ODM_RATEMCS7:
-+	case ODM_RATEMCS6:
-+	case ODM_RATEMCS5:
-+	case ODM_RATEMCS4:
-+	case ODM_RATEMCS3:
-+	case ODM_RATE54M:
-+	case ODM_RATE48M:
-+	case ODM_RATE36M:
-+	case ODM_RATE24M:
-+		tx_ini_rate = ODM_RATE24M;
-+		break;
-+	case ODM_RATEVHTSS3MCS2:
-+	case ODM_RATEVHTSS3MCS1:
-+	case ODM_RATEVHTSS2MCS2:
-+	case ODM_RATEVHTSS2MCS1:
-+	case ODM_RATEVHTSS1MCS2:
-+	case ODM_RATEVHTSS1MCS1:
-+	case ODM_RATEMCS10:
-+	case ODM_RATEMCS9:
-+	case ODM_RATEMCS2:
-+	case ODM_RATEMCS1:
-+	case ODM_RATE18M:
-+	case ODM_RATE12M:
-+		tx_ini_rate = ODM_RATE12M;
-+		break;
-+	case ODM_RATEVHTSS3MCS0:
-+	case ODM_RATEVHTSS2MCS0:
-+	case ODM_RATEVHTSS1MCS0:
-+	case ODM_RATEMCS8:
-+	case ODM_RATEMCS0:
-+	case ODM_RATE9M:
-+	case ODM_RATE6M:
-+		tx_ini_rate = ODM_RATE6M;
-+		break;
-+	case ODM_RATE11M:
-+	case ODM_RATE5_5M:
-+	case ODM_RATE2M:
-+	case ODM_RATE1M:
-+		tx_ini_rate = ODM_RATE1M;
-+		break;
-+	default:
-+		tx_ini_rate = ODM_RATE6M;
-+		break;
-+	}
-+
-+	if (hal_data->current_band_type == BAND_ON_5G)
-+		if (tx_ini_rate < ODM_RATE6M)
-+			tx_ini_rate = ODM_RATE6M;
-+
-+	return tx_ini_rate;
-+}
-+
-+void rtw_update_bmc_sta_tx_rate(_adapter *adapter)
-+{
-+	struct sta_info *psta = NULL;
-+	u8 tx_rate;
-+
-+	psta = rtw_get_bcmc_stainfo(adapter);
-+	if (psta == NULL) {
-+		RTW_ERR(ADPT_FMT "could not get bmc_sta !!\n", ADPT_ARG(adapter));
-+		return;
-+	}
-+
-+	if (adapter->bmc_tx_rate != MGN_UNKNOWN) {
-+		psta->init_rate = adapter->bmc_tx_rate;
-+		goto _exit;
-+	}
-+
-+	if (adapter->stapriv.asoc_sta_count <= 2)
-+		goto _exit;
-+
-+	tx_rate = rtw_ap_find_mini_tx_rate(adapter);
-+	#ifdef CONFIG_BMC_TX_LOW_RATE
-+	tx_rate = rtw_ap_find_bmc_rate(adapter, tx_rate);
-+	#endif
-+
-+	psta->init_rate = hw_rate_to_m_rate(tx_rate);
-+
-+_exit:
-+	RTW_INFO(ADPT_FMT" BMC Tx rate - %s\n", ADPT_ARG(adapter), MGN_RATE_STR(psta->init_rate));
-+}
-+#endif
-+
-+void rtw_init_bmc_sta_tx_rate(_adapter *padapter, struct sta_info *psta)
-+{
-+#ifdef CONFIG_BMC_TX_LOW_RATE
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+#endif
-+	u8 rate_idx = 0;
-+	u8 brate_table[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M,
-+		MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};
-+
-+	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
-+		return;
-+
-+	if (padapter->bmc_tx_rate != MGN_UNKNOWN)
-+		psta->init_rate = padapter->bmc_tx_rate;
-+	else {
-+		#ifdef CONFIG_BMC_TX_LOW_RATE
-+		if (IsEnableHWOFDM(pmlmeext->cur_wireless_mode) && (psta->cmn.ra_info.ramask && 0xFF0))
-+			rate_idx = get_lowest_rate_idx_ex(psta->cmn.ra_info.ramask, 4); /*from basic rate*/
-+		else
-+			rate_idx = get_lowest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/
-+		#else
-+		rate_idx = get_highest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/
-+		#endif
-+		if (rate_idx < 12)
-+			psta->init_rate = brate_table[rate_idx];
-+		else
-+			psta->init_rate = MGN_1M;
-+	}
-+
-+	RTW_INFO(ADPT_FMT" BMC Init Tx rate - %s\n", ADPT_ARG(padapter), MGN_RATE_STR(psta->init_rate));
-+}
-+
-+void update_bmc_sta(_adapter *padapter)
-+{
-+	_irqL	irqL;
-+	unsigned char	network_type;
-+	int supportRateNum = 0;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
-+	struct sta_info *psta = rtw_get_bcmc_stainfo(padapter);
-+
-+	if (psta) {
-+		psta->cmn.aid = 0;/* default set to 0 */
-+#ifdef CONFIG_RTW_MESH
-+		if (MLME_IS_MESH(padapter))
-+			psta->qos_option = 1;
-+		else
-+#endif
-+			psta->qos_option = 0;
-+#ifdef CONFIG_80211N_HT
-+		psta->htpriv.ht_option = _FALSE;
-+#endif /* CONFIG_80211N_HT */
-+
-+		psta->ieee8021x_blocked = 0;
-+
-+		_rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats));
-+
-+		/* psta->dot118021XPrivacy = _NO_PRIVACY_; */ /* !!! remove it, because it has been set before this. */
-+
-+		supportRateNum = rtw_get_rateset_len((u8 *)&pcur_network->SupportedRates);
-+		network_type = rtw_check_network_type((u8 *)&pcur_network->SupportedRates, supportRateNum, pcur_network->Configuration.DSConfig);
-+		if (IsSupportedTxCCK(network_type))
-+			network_type = WIRELESS_11B;
-+		else if (network_type == WIRELESS_INVALID) { /* error handling */
-+			if (pcur_network->Configuration.DSConfig > 14)
-+				network_type = WIRELESS_11A;
-+			else
-+				network_type = WIRELESS_11B;
-+		}
-+		update_sta_basic_rate(psta, network_type);
-+		psta->wireless_mode = network_type;
-+
-+		rtw_hal_update_sta_ra_info(padapter, psta);
-+
-+		_enter_critical_bh(&psta->lock, &irqL);
-+		psta->state = WIFI_ASOC_STATE;
-+		_exit_critical_bh(&psta->lock, &irqL);
-+
-+		rtw_sta_media_status_rpt(padapter, psta, 1);
-+		rtw_init_bmc_sta_tx_rate(padapter, psta);
-+
-+	} else
-+		RTW_INFO("add_RATid_bmc_sta error!\n");
-+
-+}
-+
-+#if defined(CONFIG_80211N_HT) && defined(CONFIG_BEAMFORMING)
-+void update_sta_info_apmode_ht_bf_cap(_adapter *padapter, struct sta_info *psta)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct ht_priv	*phtpriv_ap = &pmlmepriv->htpriv;
-+	struct ht_priv	*phtpriv_sta = &psta->htpriv;
-+
-+	u8 cur_beamform_cap = 0;
-+
-+	/*Config Tx beamforming setting*/
-+	if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
-+		GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP((u8 *)(&phtpriv_sta->ht_cap))) {
-+		SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
-+		/*Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
-+		SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 6);
-+	}
-+
-+	if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
-+		GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP((u8 *)(&phtpriv_sta->ht_cap))) {
-+		SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
-+		/*Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
-+		SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 4);
-+	}
-+	if (cur_beamform_cap)
-+		RTW_INFO("Client STA(%d) HT Beamforming Cap = 0x%02X\n", psta->cmn.aid, cur_beamform_cap);
-+
-+	phtpriv_sta->beamform_cap = cur_beamform_cap;
-+	psta->cmn.bf_info.ht_beamform_cap = cur_beamform_cap;
-+
-+}
-+#endif /*CONFIG_80211N_HT && CONFIG_BEAMFORMING*/
-+
-+/* notes:
-+ * AID: 1~MAX for sta and 0 for bc/mc in ap/adhoc mode  */
-+void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta)
-+{
-+	_irqL	irqL;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+#ifdef CONFIG_80211N_HT
-+	struct ht_priv	*phtpriv_ap = &pmlmepriv->htpriv;
-+	struct ht_priv	*phtpriv_sta = &psta->htpriv;
-+#endif /* CONFIG_80211N_HT */
-+	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0;
-+	/* set intf_tag to if1 */
-+	/* psta->intf_tag = 0; */
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	/*alloc macid when call rtw_alloc_stainfo(),release macid when call rtw_free_stainfo()*/
-+
-+	if (!MLME_IS_MESH(padapter) && psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
-+		psta->ieee8021x_blocked = _TRUE;
-+	else
-+		psta->ieee8021x_blocked = _FALSE;
-+
-+
-+	/* update sta's cap */
-+
-+	/* ERP */
-+	VCS_update(padapter, psta);
-+#ifdef CONFIG_80211N_HT
-+	/* HT related cap */
-+	if (phtpriv_sta->ht_option) {
-+		/* check if sta supports rx ampdu */
-+		phtpriv_sta->ampdu_enable = phtpriv_ap->ampdu_enable;
-+
-+		phtpriv_sta->rx_ampdu_min_spacing = (phtpriv_sta->ht_cap.ampdu_params_info & IEEE80211_HT_CAP_AMPDU_DENSITY) >> 2;
-+
-+		/* bwmode */
-+		if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH))
-+			psta->cmn.bw_mode = CHANNEL_WIDTH_40;
-+		else
-+			psta->cmn.bw_mode = CHANNEL_WIDTH_20;
-+
-+		if (phtpriv_sta->op_present
-+			&& !GET_HT_OP_ELE_STA_CHL_WIDTH(phtpriv_sta->ht_op))
-+			psta->cmn.bw_mode = CHANNEL_WIDTH_20;
-+
-+		if (psta->ht_40mhz_intolerant)
-+			psta->cmn.bw_mode = CHANNEL_WIDTH_20;
-+
-+		if (pmlmeext->cur_bwmode < psta->cmn.bw_mode)
-+			psta->cmn.bw_mode = pmlmeext->cur_bwmode;
-+
-+		phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset;
-+
-+
-+		/* check if sta support s Short GI 20M */
-+		if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20))
-+			phtpriv_sta->sgi_20m = _TRUE;
-+
-+		/* check if sta support s Short GI 40M */
-+		if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) {
-+			if (psta->cmn.bw_mode == CHANNEL_WIDTH_40) /* according to psta->bw_mode */
-+				phtpriv_sta->sgi_40m = _TRUE;
-+			else
-+				phtpriv_sta->sgi_40m = _FALSE;
-+		}
-+
-+		psta->qos_option = _TRUE;
-+
-+		/* B0 Config LDPC Coding Capability */
-+		if (TEST_FLAG(phtpriv_ap->ldpc_cap, LDPC_HT_ENABLE_TX) &&
-+		    GET_HT_CAP_ELE_LDPC_CAP((u8 *)(&phtpriv_sta->ht_cap))) {
-+			SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX));
-+			RTW_INFO("Enable HT Tx LDPC for STA(%d)\n", psta->cmn.aid);
-+		}
-+
-+		/* B7 B8 B9 Config STBC setting */
-+		if (TEST_FLAG(phtpriv_ap->stbc_cap, STBC_HT_ENABLE_TX) &&
-+		    GET_HT_CAP_ELE_RX_STBC((u8 *)(&phtpriv_sta->ht_cap))) {
-+			SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX));
-+			RTW_INFO("Enable HT Tx STBC for STA(%d)\n", psta->cmn.aid);
-+		}
-+
-+		#ifdef CONFIG_BEAMFORMING
-+		update_sta_info_apmode_ht_bf_cap(padapter, psta);
-+		#endif
-+	} else {
-+		phtpriv_sta->ampdu_enable = _FALSE;
-+
-+		phtpriv_sta->sgi_20m = _FALSE;
-+		phtpriv_sta->sgi_40m = _FALSE;
-+		psta->cmn.bw_mode = CHANNEL_WIDTH_20;
-+		phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	}
-+
-+	phtpriv_sta->ldpc_cap = cur_ldpc_cap;
-+	phtpriv_sta->stbc_cap = cur_stbc_cap;
-+
-+	/* Rx AMPDU */
-+	send_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */
-+
-+	/* TX AMPDU */
-+	send_delba(padapter, 1, psta->cmn.mac_addr);/*  */ /* originator */
-+	phtpriv_sta->agg_enable_bitmap = 0x0;/* reset */
-+	phtpriv_sta->candidate_tid_bitmap = 0x0;/* reset */
-+#endif /* CONFIG_80211N_HT */
-+
-+#ifdef CONFIG_80211AC_VHT
-+	update_sta_vht_info_apmode(padapter, psta);
-+#endif
-+	psta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta));
-+	update_ldpc_stbc_cap(psta);
-+
-+	/* todo: init other variables */
-+
-+	_rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats));
-+
-+
-+	/* add ratid */
-+	/* add_RATid(padapter, psta); */ /* move to ap_sta_info_defer_update() */
-+
-+	/* ap mode */
-+	rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
-+
-+	_enter_critical_bh(&psta->lock, &irqL);
-+
-+	/* Check encryption */
-+	if (!MLME_IS_MESH(padapter) && psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
-+		psta->state |= WIFI_UNDER_KEY_HANDSHAKE;
-+
-+	psta->state |= WIFI_ASOC_STATE;
-+
-+	_exit_critical_bh(&psta->lock, &irqL);
-+}
-+
-+#ifdef CONFIG_RTW_80211K
-+static void update_rm_cap(u8 *frame_head, _adapter *pa, u32 pktlen, int offset)
-+{
-+	u8 *res;
-+	sint len;
-+
-+	res = rtw_get_ie(frame_head + offset, _EID_RRM_EN_CAP_IE_, &len,
-+			 pktlen - offset);
-+	if (res != NULL)
-+		_rtw_memcpy((void *)pa->rmpriv.rm_en_cap_def, (res + 2), len);
-+}
-+#endif
-+
-+static void update_ap_info(_adapter *padapter, struct sta_info *psta)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+#ifdef CONFIG_80211N_HT
-+	struct ht_priv	*phtpriv_ap = &pmlmepriv->htpriv;
-+#endif /* CONFIG_80211N_HT */
-+
-+	psta->wireless_mode = pmlmeext->cur_wireless_mode;
-+
-+	psta->bssratelen = rtw_get_rateset_len(pnetwork->SupportedRates);
-+	_rtw_memcpy(psta->bssrateset, pnetwork->SupportedRates, psta->bssratelen);
-+
-+#ifdef CONFIG_80211N_HT
-+	/* HT related cap */
-+	if (phtpriv_ap->ht_option) {
-+		/* check if sta supports rx ampdu */
-+		/* phtpriv_ap->ampdu_enable = phtpriv_ap->ampdu_enable; */
-+
-+		/* check if sta support s Short GI 20M */
-+		if ((phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20))
-+			phtpriv_ap->sgi_20m = _TRUE;
-+		/* check if sta support s Short GI 40M */
-+		if ((phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40))
-+			phtpriv_ap->sgi_40m = _TRUE;
-+
-+		psta->qos_option = _TRUE;
-+	} else {
-+		phtpriv_ap->ampdu_enable = _FALSE;
-+
-+		phtpriv_ap->sgi_20m = _FALSE;
-+		phtpriv_ap->sgi_40m = _FALSE;
-+	}
-+
-+	psta->cmn.bw_mode = pmlmeext->cur_bwmode;
-+	phtpriv_ap->ch_offset = pmlmeext->cur_ch_offset;
-+
-+	phtpriv_ap->agg_enable_bitmap = 0x0;/* reset */
-+	phtpriv_ap->candidate_tid_bitmap = 0x0;/* reset */
-+
-+	_rtw_memcpy(&psta->htpriv, &pmlmepriv->htpriv, sizeof(struct ht_priv));
-+
-+#ifdef CONFIG_80211AC_VHT
-+	_rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv));
-+#endif /* CONFIG_80211AC_VHT */
-+
-+#endif /* CONFIG_80211N_HT */
-+
-+	psta->state |= WIFI_AP_STATE; /* Aries, add,fix bug of flush_cam_entry at STOP AP mode , 0724 */
-+}
-+
-+static void rtw_set_hw_wmm_param(_adapter *padapter)
-+{
-+	u8	AIFS, ECWMin, ECWMax, aSifsTime;
-+	u8	acm_mask;
-+	u16	TXOP;
-+	u32	acParm, i;
-+	u32	edca[4], inx[4];
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+
-+	acm_mask = 0;
-+#ifdef CONFIG_80211N_HT
-+	if (pregpriv->ht_enable &&
-+		(is_supported_5g(pmlmeext->cur_wireless_mode) ||
-+	    (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)))
-+		aSifsTime = 16;
-+	else
-+#endif /* CONFIG_80211N_HT */
-+		aSifsTime = 10;
-+
-+	if (pmlmeinfo->WMM_enable == 0) {
-+		padapter->mlmepriv.acm_mask = 0;
-+
-+		AIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
-+
-+		if (pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11A)) {
-+			ECWMin = 4;
-+			ECWMax = 10;
-+		} else if (pmlmeext->cur_wireless_mode & WIRELESS_11B) {
-+			ECWMin = 5;
-+			ECWMax = 10;
-+		} else {
-+			ECWMin = 4;
-+			ECWMax = 10;
-+		}
-+
-+		TXOP = 0;
-+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));
-+
-+		ECWMin = 2;
-+		ECWMax = 3;
-+		TXOP = 0x2f;
-+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));
-+
-+	} else {
-+		edca[0] = edca[1] = edca[2] = edca[3] = 0;
-+
-+		/*TODO:*/
-+		acm_mask = 0;
-+		padapter->mlmepriv.acm_mask = acm_mask;
-+
-+#if 0
-+		/* BK */
-+		/* AIFS = AIFSN * slot time + SIFS - r2t phy delay */
-+#endif
-+		AIFS = (7 * pmlmeinfo->slotTime) + aSifsTime;
-+		ECWMin = 4;
-+		ECWMax = 10;
-+		TXOP = 0;
-+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));
-+		edca[XMIT_BK_QUEUE] = acParm;
-+		RTW_INFO("WMM(BK): %x\n", acParm);
-+
-+		/* BE */
-+		AIFS = (3 * pmlmeinfo->slotTime) + aSifsTime;
-+		ECWMin = 4;
-+		ECWMax = 6;
-+		TXOP = 0;
-+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));
-+		edca[XMIT_BE_QUEUE] = acParm;
-+		RTW_INFO("WMM(BE): %x\n", acParm);
-+
-+		/* VI */
-+		AIFS = (1 * pmlmeinfo->slotTime) + aSifsTime;
-+		ECWMin = 3;
-+		ECWMax = 4;
-+		TXOP = 94;
-+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));
-+		edca[XMIT_VI_QUEUE] = acParm;
-+		RTW_INFO("WMM(VI): %x\n", acParm);
-+
-+		/* VO */
-+		AIFS = (1 * pmlmeinfo->slotTime) + aSifsTime;
-+		ECWMin = 2;
-+		ECWMax = 3;
-+		TXOP = 47;
-+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));
-+		edca[XMIT_VO_QUEUE] = acParm;
-+		RTW_INFO("WMM(VO): %x\n", acParm);
-+
-+
-+		if (padapter->registrypriv.acm_method == 1)
-+			rtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask));
-+		else
-+			padapter->mlmepriv.acm_mask = acm_mask;
-+
-+		inx[0] = 0;
-+		inx[1] = 1;
-+		inx[2] = 2;
-+		inx[3] = 3;
-+
-+		if (pregpriv->wifi_spec == 1) {
-+			u32	j, tmp, change_inx = _FALSE;
-+
-+			/* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */
-+			for (i = 0 ; i < 4 ; i++) {
-+				for (j = i + 1 ; j < 4 ; j++) {
-+					/* compare CW and AIFS */
-+					if ((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF))
-+						change_inx = _TRUE;
-+					else if ((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) {
-+						/* compare TXOP */
-+						if ((edca[j] >> 16) > (edca[i] >> 16))
-+							change_inx = _TRUE;
-+					}
-+
-+					if (change_inx) {
-+						tmp = edca[i];
-+						edca[i] = edca[j];
-+						edca[j] = tmp;
-+
-+						tmp = inx[i];
-+						inx[i] = inx[j];
-+						inx[j] = tmp;
-+
-+						change_inx = _FALSE;
-+					}
-+				}
-+			}
-+		}
-+
-+		for (i = 0 ; i < 4 ; i++) {
-+			pxmitpriv->wmm_para_seq[i] = inx[i];
-+			RTW_INFO("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]);
-+		}
-+
-+	}
-+
-+}
-+#ifdef CONFIG_80211N_HT
-+static void update_hw_ht_param(_adapter *padapter)
-+{
-+	unsigned char		max_AMPDU_len;
-+	unsigned char		min_MPDU_spacing;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+
-+	/* handle A-MPDU parameter field */
-+	/*
-+		AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k
-+		AMPDU_para [4:2]:Min MPDU Start Spacing
-+	*/
-+	max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
-+
-+	min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2;
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing));
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len));
-+
-+	/*  */
-+	/* Config SM Power Save setting */
-+	/*  */
-+	pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;
-+	if (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) {
-+#if 0
-+		u8 i;
-+		/* update the MCS rates */
-+		for (i = 0; i < 16; i++)
-+			pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
-+#endif
-+		RTW_INFO("%s(): WLAN_HT_CAP_SM_PS_STATIC\n", __FUNCTION__);
-+	}
-+
-+	/*  */
-+	/* Config current HT Protection mode. */
-+	/*  */
-+	/* pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; */
-+
-+}
-+#endif /* CONFIG_80211N_HT */
-+static void rtw_ap_check_scan(_adapter *padapter)
-+{
-+	_irqL	irqL;
-+	_list		*plist, *phead;
-+	u32	delta_time, lifetime;
-+	struct	wlan_network	*pnetwork = NULL;
-+	WLAN_BSSID_EX *pbss = NULL;
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	_queue	*queue	= &(pmlmepriv->scanned_queue);
-+	u8 do_scan = _FALSE;
-+	u8 reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED;
-+
-+	lifetime = SCANQUEUE_LIFETIME; /* 20 sec */
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+	phead = get_list_head(queue);
-+	if (rtw_end_of_queue_search(phead, get_next(phead)) == _TRUE)
-+		if (padapter->registrypriv.wifi_spec) {
-+			do_scan = _TRUE;
-+			reason |= RTW_AUTO_SCAN_REASON_2040_BSS;
-+		}
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+#ifdef CONFIG_RTW_ACS
-+	if (padapter->registrypriv.acs_auto_scan) {
-+		do_scan = _TRUE;
-+		reason |= RTW_AUTO_SCAN_REASON_ACS;
-+		rtw_acs_start(padapter);
-+	}
-+#endif/*CONFIG_RTW_ACS*/
-+
-+	if (_TRUE == do_scan) {
-+		RTW_INFO("%s : drv scans by itself and wait_completed\n", __func__);
-+		rtw_drv_scan_by_self(padapter, reason);
-+		rtw_scan_wait_completed(padapter);
-+	}
-+
-+#ifdef CONFIG_RTW_ACS
-+	if (padapter->registrypriv.acs_auto_scan)
-+		rtw_acs_stop(padapter);
-+#endif
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+	while (1) {
-+
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+
-+		if (rtw_chset_search_ch(adapter_to_chset(padapter), pnetwork->network.Configuration.DSConfig) >= 0
-+		    && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE
-+		    && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))) {
-+			delta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned);
-+
-+			if (delta_time < lifetime) {
-+
-+				uint ie_len = 0;
-+				u8 *pbuf = NULL;
-+				u8 *ie = NULL;
-+
-+				pbss = &pnetwork->network;
-+				ie = pbss->IEs;
-+
-+				/*check if HT CAP INFO IE exists or not*/
-+				pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss->IELength - _BEACON_IE_OFFSET_));
-+				if (pbuf == NULL) {
-+					/* HT CAP INFO IE don't exist, it is b/g mode bss.*/
-+
-+					if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc))
-+						ATOMIC_SET(&pmlmepriv->olbc, _TRUE);
-+
-+					if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht))
-+						ATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE);
-+					
-+					if (padapter->registrypriv.wifi_spec)
-+						RTW_INFO("%s: %s is a/b/g ap\n", __func__, pnetwork->network.Ssid.Ssid);
-+				}
-+			}
-+		}
-+
-+		plist = get_next(plist);
-+
-+	}
-+
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+#ifdef CONFIG_80211N_HT
-+	pmlmepriv->num_sta_no_ht = 0; /* reset to 0 after ap do scanning*/
-+#endif
-+}
-+
-+void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter)
-+{
-+	WLAN_BSSID_EX *pnetwork = &(adapter->mlmepriv.cur_network.network);
-+	struct sta_info *sta = NULL;
-+
-+	/* update cur_wireless_mode */
-+	update_wireless_mode(adapter);
-+
-+	/* update RRSR and RTS_INIT_RATE register after set channel and bandwidth */
-+	UpdateBrateTbl(adapter, pnetwork->SupportedRates);
-+	rtw_hal_set_hwreg(adapter, HW_VAR_BASIC_RATE, pnetwork->SupportedRates);
-+
-+	/* update capability after cur_wireless_mode updated */
-+	update_capinfo(adapter, rtw_get_capability(pnetwork));
-+
-+	/* update bc/mc sta_info */
-+	update_bmc_sta(adapter);
-+
-+	/* update AP's sta info */
-+	sta = rtw_get_stainfo(&adapter->stapriv, pnetwork->MacAddress);
-+	if (!sta) {
-+		RTW_INFO(FUNC_ADPT_FMT" !sta for macaddr="MAC_FMT"\n", FUNC_ADPT_ARG(adapter), MAC_ARG(pnetwork->MacAddress));
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	update_ap_info(adapter, sta);
-+}
-+
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+bool rtw_ap_nums_check(_adapter *adapter)
-+{
-+	if (rtw_ap_get_nums(adapter) < CONFIG_LIMITED_AP_NUM)
-+		return _TRUE;
-+	return _FALSE;
-+}
-+u8 rtw_ap_allocate_vapid(struct dvobj_priv *dvobj)
-+{
-+	u8 vap_id;
-+
-+	for (vap_id = 0; vap_id < CONFIG_LIMITED_AP_NUM; vap_id++) {
-+		if (!(dvobj->vap_map & BIT(vap_id)))
-+			break;
-+	}
-+
-+	if (vap_id < CONFIG_LIMITED_AP_NUM)
-+		dvobj->vap_map |= BIT(vap_id);
-+
-+	return vap_id;
-+}
-+u8 rtw_ap_release_vapid(struct dvobj_priv *dvobj, u8 vap_id)
-+{
-+	if (vap_id >= CONFIG_LIMITED_AP_NUM) {
-+		RTW_ERR("%s - vapid(%d) failed\n", __func__, vap_id);
-+		rtw_warn_on(1);
-+		return _FAIL;
-+	}
-+	dvobj->vap_map &= ~ BIT(vap_id);
-+	return _SUCCESS;
-+}
-+#endif
-+static void _rtw_iface_undersurvey_chk(const char *func, _adapter *adapter)
-+{
-+	int i;
-+	_adapter *iface;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mlme_priv *pmlmepriv;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if ((iface) && rtw_is_adapter_up(iface)) {
-+			pmlmepriv = &iface->mlmepriv;
-+			if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY))
-+				RTW_ERR("%s ("ADPT_FMT") under survey\n", func, ADPT_ARG(iface));
-+		}
-+	}
-+}
-+void start_bss_network(_adapter *padapter, struct createbss_parm *parm)
-+{
-+#define DUMP_ADAPTERS_STATUS 0
-+	u8 mlme_act = MLME_ACTION_UNKNOWN;
-+	u8 val8;
-+	u16 bcn_interval;
-+	u32	acparm;
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
-+	WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; /* used as input */
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network);
-+	struct dvobj_priv *pdvobj = padapter->dvobj;
-+	s16 req_ch = REQ_CH_NONE, req_bw = REQ_BW_NONE, req_offset = REQ_OFFSET_NONE;
-+	u8 u_ch = 0, u_bw, u_offset;
-+	bool set_u_ch;
-+	u8 doiqk = _FALSE;
-+	/* use for check ch bw offset can be allowed or not */
-+	u8 chbw_allow = _TRUE;
-+	int i;
-+	u8 ifbmp_ch_changed = 0;
-+
-+	if (parm->req_ch != 0) {
-+		/* bypass other setting, go checking ch, bw, offset */
-+		mlme_act = MLME_OPCH_SWITCH;
-+		req_ch = parm->req_ch;
-+		req_bw = parm->req_bw;
-+		req_offset = parm->req_offset;
-+		goto chbw_decision;
-+	} else {
-+		/* request comes from upper layer */
-+		if (MLME_IS_AP(padapter))
-+			mlme_act = MLME_AP_STARTED;
-+		else if (MLME_IS_MESH(padapter))
-+			mlme_act = MLME_MESH_STARTED;
-+		else
-+			rtw_warn_on(1);
-+		req_ch = 0;
-+		_rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length);
-+	}
-+
-+	bcn_interval = (u16)pnetwork->Configuration.BeaconPeriod;
-+
-+	/* check if there is wps ie, */
-+	/* if there is wpsie in beacon, the hostapd will update beacon twice when stating hostapd, */
-+	/* and at first time the security ie ( RSN/WPA IE) will not include in beacon. */
-+	if (NULL == rtw_get_wps_ie(pnetwork->IEs + _FIXED_IE_LENGTH_, pnetwork->IELength - _FIXED_IE_LENGTH_, NULL, NULL))
-+		pmlmeext->bstart_bss = _TRUE;
-+
-+	/* todo: update wmm, ht cap */
-+	/* pmlmeinfo->WMM_enable; */
-+	/* pmlmeinfo->HT_enable; */
-+	if (pmlmepriv->qospriv.qos_option)
-+		pmlmeinfo->WMM_enable = _TRUE;
-+#ifdef CONFIG_80211N_HT
-+	if (pmlmepriv->htpriv.ht_option) {
-+		pmlmeinfo->WMM_enable = _TRUE;
-+		pmlmeinfo->HT_enable = _TRUE;
-+		/* pmlmeinfo->HT_info_enable = _TRUE; */
-+		/* pmlmeinfo->HT_caps_enable = _TRUE; */
-+
-+		update_hw_ht_param(padapter);
-+	}
-+#endif /* #CONFIG_80211N_HT */
-+
-+#ifdef CONFIG_80211AC_VHT
-+	if (pmlmepriv->vhtpriv.vht_option) {
-+		pmlmeinfo->VHT_enable = _TRUE;
-+		update_hw_vht_param(padapter);
-+	}
-+#endif /* CONFIG_80211AC_VHT */
-+
-+	if (pmlmepriv->cur_network.join_res != _TRUE) { /* setting only at  first time */
-+		/* WEP Key will be set before this function, do not clear CAM. */
-+		if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_)
-+			&& !MLME_IS_MESH(padapter) /* mesh group key is set before this function */
-+		)
-+			flush_all_cam_entry(padapter);	/* clear CAM */
-+	}
-+
-+	/* set MSR to AP_Mode		 */
-+	Set_MSR(padapter, _HW_STATE_AP_);
-+
-+	/* Set BSSID REG */
-+	rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pnetwork->MacAddress);
-+
-+	/* Set Security */
-+	val8 = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) ? 0xcc : 0xcf;
-+	rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
-+
-+	/* Beacon Control related register */
-+	rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&bcn_interval));
-+
-+	rtw_hal_rcr_set_chk_bssid(padapter, mlme_act);
-+
-+chbw_decision:
-+	ifbmp_ch_changed = rtw_ap_chbw_decision(padapter, parm->ifbmp, parm->excl_ifbmp
-+						, req_ch, req_bw, req_offset
-+						, &u_ch, &u_bw, &u_offset, &chbw_allow, &set_u_ch);
-+
-+	for (i = 0; i < pdvobj->iface_nums; i++) {
-+		if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i])
-+			continue;
-+
-+		/* let pnetwork_mlme == pnetwork_mlmeext */
-+		_rtw_memcpy(&(pdvobj->padapters[i]->mlmepriv.cur_network.network)
-+			, &(pdvobj->padapters[i]->mlmeextpriv.mlmext_info.network)
-+			, pdvobj->padapters[i]->mlmeextpriv.mlmext_info.network.Length);
-+
-+		rtw_start_bss_hdl_after_chbw_decided(pdvobj->padapters[i]);
-+
-+		/* Set EDCA param reg after update cur_wireless_mode & update_capinfo */
-+		if (pregpriv->wifi_spec == 1)
-+			rtw_set_hw_wmm_param(pdvobj->padapters[i]);
-+	}
-+
-+#if defined(CONFIG_DFS_MASTER)
-+	rtw_dfs_rd_en_decision(padapter, mlme_act, parm->excl_ifbmp);
-+#endif
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(padapter)) {
-+		/* 
-+		* due to check under rtw_ap_chbw_decision
-+		* if under MCC mode, means req channel setting is the same as current channel setting
-+		* if not under MCC mode, mean req channel setting is not the same as current channel setting
-+		*/
-+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
-+				RTW_INFO(FUNC_ADPT_FMT": req channel setting is the same as current channel setting, go to update BCN\n"
-+				, FUNC_ADPT_ARG(padapter));
-+
-+				goto update_beacon;
-+
-+		}
-+	}
-+
-+	/* issue null data to AP for all interface connecting to AP before switch channel setting for softap */
-+	rtw_hal_mcc_issue_null_data(padapter, chbw_allow, 1);
-+#endif /* CONFIG_MCC_MODE */
-+
-+	if (!IS_CH_WAITING(adapter_to_rfctl(padapter))) {
-+		doiqk = _TRUE;
-+		rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
-+	}
-+
-+	if (set_u_ch)
-+		set_channel_bwmode(padapter, u_ch, u_offset, u_bw);
-+
-+	doiqk = _FALSE;
-+	rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
-+
-+#ifdef CONFIG_MCC_MODE
-+	/* after set_channel_bwmode for backup IQK */
-+	if (rtw_hal_set_mcc_setting_start_bss_network(padapter, chbw_allow) == _FAIL) {
-+		/* MCC setting fail, update to buddy's channel */
-+		rtw_mi_get_ch_setting_union_no_self(padapter, &u_ch, &u_bw, &u_offset);
-+		pnetwork->Configuration.DSConfig = u_ch;
-+		padapter->mlmeextpriv.cur_channel = u_ch;
-+		padapter->mlmeextpriv.cur_bwmode = u_bw;
-+		padapter->mlmeextpriv.cur_ch_offset = u_offset;
-+
-+		if (ifbmp_ch_changed == 0) {
-+			u8 ht_option = 0;
-+
-+#ifdef CONFIG_80211N_HT
-+			ht_option = padapter->mlmepriv.htpriv.ht_option;
-+#endif
-+
-+			rtw_cfg80211_ch_switch_notify(padapter
-+				, padapter->mlmeextpriv.cur_channel
-+				, padapter->mlmeextpriv.cur_bwmode
-+				, padapter->mlmeextpriv.cur_ch_offset
-+				, ht_option, 0);
-+		}
-+	}
-+#endif
-+
-+#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
-+	for (i = 0; i < pdvobj->iface_nums; i++) {
-+		if (!(ifbmp_ch_changed & BIT(i)) || !pdvobj->padapters[i])
-+			continue;
-+
-+		{
-+			u8 ht_option = 0;
-+
-+			#ifdef CONFIG_80211N_HT
-+			ht_option = pdvobj->padapters[i]->mlmepriv.htpriv.ht_option;
-+			#endif
-+
-+			rtw_cfg80211_ch_switch_notify(pdvobj->padapters[i]
-+				, pdvobj->padapters[i]->mlmeextpriv.cur_channel
-+				, pdvobj->padapters[i]->mlmeextpriv.cur_bwmode
-+				, pdvobj->padapters[i]->mlmeextpriv.cur_ch_offset
-+				, ht_option, 0);
-+		}
-+	}
-+#endif /* defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */
-+
-+	rtw_rfctl_update_op_mode(adapter_to_rfctl(padapter), parm->ifbmp, 1);
-+
-+	if (DUMP_ADAPTERS_STATUS) {
-+		RTW_INFO(FUNC_ADPT_FMT" done\n", FUNC_ADPT_ARG(padapter));
-+		dump_adapters_status(RTW_DBGDUMP , adapter_to_dvobj(padapter));
-+	}
-+
-+#ifdef CONFIG_MCC_MODE
-+update_beacon:
-+#endif
-+
-+	for (i = 0; i < pdvobj->iface_nums; i++) {
-+		struct mlme_priv *mlme;
-+
-+		if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i])
-+			continue;
-+
-+		/* update beacon content only if bstart_bss is _TRUE */
-+		if (pdvobj->padapters[i]->mlmeextpriv.bstart_bss != _TRUE)
-+			continue;
-+
-+		mlme = &(pdvobj->padapters[i]->mlmepriv);
-+
-+		#ifdef CONFIG_80211N_HT
-+		if ((ATOMIC_READ(&mlme->olbc) == _TRUE) || (ATOMIC_READ(&mlme->olbc_ht) == _TRUE)) {
-+			/* AP is not starting a 40 MHz BSS in presence of an 802.11g BSS. */
-+			mlme->ht_op_mode &= (~HT_INFO_OPERATION_MODE_OP_MODE_MASK);
-+			mlme->ht_op_mode |= OP_MODE_MAY_BE_LEGACY_STAS;
-+			update_beacon(pdvobj->padapters[i], _HT_ADD_INFO_IE_, NULL, _FALSE, 0);
-+		}
-+		#endif
-+
-+		update_beacon(pdvobj->padapters[i], _TIM_IE_, NULL, _FALSE, 0);
-+	}
-+
-+	if (mlme_act != MLME_OPCH_SWITCH
-+		&& pmlmeext->bstart_bss == _TRUE
-+	) {
-+#ifdef CONFIG_SUPPORT_MULTI_BCN
-+		_irqL irqL;
-+
-+		_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
-+		if (rtw_is_list_empty(&padapter->list)) {
-+			#ifdef CONFIG_FW_HANDLE_TXBCN
-+			padapter->vap_id = rtw_ap_allocate_vapid(pdvobj);
-+			#endif
-+			rtw_list_insert_tail(&padapter->list, get_list_head(&pdvobj->ap_if_q));
-+			pdvobj->nr_ap_if++;
-+			pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL / pdvobj->nr_ap_if;
-+		}
-+		_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
-+
-+		#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+		rtw_ap_set_mbid_num(padapter, pdvobj->nr_ap_if);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pdvobj->inter_bcn_space));
-+		#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
-+
-+#endif /*CONFIG_SUPPORT_MULTI_BCN*/
-+
-+		#ifdef CONFIG_HW_P0_TSF_SYNC
-+		correct_TSF(padapter, mlme_act);
-+		#endif
-+	}
-+
-+	rtw_scan_wait_completed(padapter);
-+
-+	_rtw_iface_undersurvey_chk(__func__, padapter);
-+	/* send beacon */
-+	ResumeTxBeacon(padapter);
-+	{
-+#if !defined(CONFIG_INTERRUPT_BASED_TXBCN)
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_PCI_BCN_POLLING)
-+#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+		if (pdvobj->nr_ap_if == 1
-+			&& mlme_act != MLME_OPCH_SWITCH
-+		) {
-+			RTW_INFO("start SW BCN TIMER!\n");
-+			_set_timer(&pdvobj->txbcn_timer, bcn_interval);
-+		}
-+#else
-+		for (i = 0; i < pdvobj->iface_nums; i++) {
-+			if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i])
-+				continue;
-+
-+			if (send_beacon(pdvobj->padapters[i]) == _FAIL)
-+				RTW_INFO(ADPT_FMT" issue_beacon, fail!\n", ADPT_ARG(pdvobj->padapters[i]));
-+		}
-+#endif
-+#endif
-+#endif /* !defined(CONFIG_INTERRUPT_BASED_TXBCN) */
-+
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+		if (mlme_act != MLME_OPCH_SWITCH
-+			&& pmlmeext->bstart_bss == _TRUE)
-+			rtw_ap_mbid_bcn_en(padapter, padapter->vap_id);
-+#endif
-+	}
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	if (MLME_IS_AP(padapter) && padapter->tbtx_capability == _TRUE) {
-+		_set_timer(&pmlmeext->tbtx_token_dispatch_timer, 1);
-+		RTW_INFO("Start token dispatch\n");
-+	}
-+#endif
-+}
-+
-+int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf,  int len)
-+{
-+	int ret = _SUCCESS;
-+	u8 *p;
-+	u8 *pHT_caps_ie = NULL;
-+	u8 *pHT_info_ie = NULL;
-+	u16 cap, ht_cap = _FALSE;
-+	uint ie_len = 0;
-+	int group_cipher, pairwise_cipher, gmcs;
-+	u32 akm;
-+	u8 mfp_opt = MFP_NO;
-+	u8	channel, network_type;
-+	u8 OUI1[] = {0x00, 0x50, 0xf2, 0x01};
-+	u8 WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};
-+	HT_CAP_AMPDU_DENSITY best_ampdu_density;
-+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	WLAN_BSSID_EX *pbss_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
-+	u8 *ie = pbss_network->IEs;
-+	u8 vht_cap = _FALSE;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	u8 rf_num = 0;
-+	int ret_rm;
-+	/* SSID */
-+	/* Supported rates */
-+	/* DS Params */
-+	/* WLAN_EID_COUNTRY */
-+	/* ERP Information element */
-+	/* Extended supported rates */
-+	/* WPA/WPA2 */
-+	/* Radio Resource Management */
-+	/* Wi-Fi Wireless Multimedia Extensions */
-+	/* ht_capab, ht_oper */
-+	/* WPS IE */
-+
-+	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
-+
-+	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
-+		return _FAIL;
-+
-+
-+	if (len > MAX_IE_SZ)
-+		return _FAIL;
-+
-+	pbss_network->IELength = len;
-+
-+	_rtw_memset(ie, 0, MAX_IE_SZ);
-+
-+	_rtw_memcpy(ie, pbuf, pbss_network->IELength);
-+
-+
-+	if (pbss_network->InfrastructureMode != Ndis802_11APMode
-+		&& pbss_network->InfrastructureMode != Ndis802_11_mesh
-+	) {
-+		rtw_warn_on(1);
-+		return _FAIL;
-+	}
-+
-+
-+	rtw_ap_check_scan(padapter);
-+
-+
-+	pbss_network->Rssi = 0;
-+
-+	_rtw_memcpy(pbss_network->MacAddress, adapter_mac_addr(padapter), ETH_ALEN);
-+
-+	/* beacon interval */
-+	p = rtw_get_beacon_interval_from_ie(ie);/* ie + 8;	 */ /* 8: TimeStamp, 2: Beacon Interval 2:Capability */
-+	/* pbss_network->Configuration.BeaconPeriod = le16_to_cpu(*(unsigned short*)p); */
-+	pbss_network->Configuration.BeaconPeriod = RTW_GET_LE16(p);
-+
-+	/* capability */
-+	/* cap = *(unsigned short *)rtw_get_capability_from_ie(ie); */
-+	/* cap = le16_to_cpu(cap); */
-+	cap = RTW_GET_LE16(ie);
-+
-+	/* SSID */
-+	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SSID_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
-+	if (p && ie_len > 0) {
-+		_rtw_memset(&pbss_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
-+		_rtw_memcpy(pbss_network->Ssid.Ssid, (p + 2), ie_len);
-+		pbss_network->Ssid.SsidLength = ie_len;
-+#ifdef CONFIG_P2P
-+		_rtw_memcpy(padapter->wdinfo.p2p_group_ssid, pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength);
-+		padapter->wdinfo.p2p_group_ssid_len = pbss_network->Ssid.SsidLength;
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTW_MESH
-+	/* Mesh ID */
-+	if (MLME_IS_MESH(padapter)) {
-+		p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, WLAN_EID_MESH_ID, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
-+		if (p && ie_len > 0) {
-+			_rtw_memset(&pbss_network->mesh_id, 0, sizeof(NDIS_802_11_SSID));
-+			_rtw_memcpy(pbss_network->mesh_id.Ssid, (p + 2), ie_len);
-+			pbss_network->mesh_id.SsidLength = ie_len;
-+		}
-+	}
-+#endif
-+
-+	/* chnnel */
-+	channel = 0;
-+	pbss_network->Configuration.Length = 0;
-+	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _DSSET_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
-+	if (p && ie_len > 0)
-+		channel = *(p + 2);
-+
-+	pbss_network->Configuration.DSConfig = channel;
-+
-+	/*	support rate ie & ext support ie & IElen & SupportedRates	*/
-+	network_type = rtw_update_rate_bymode(pbss_network, pregistrypriv->wireless_mode);
-+
-+	/* parsing ERP_IE */
-+	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
-+	if (p && ie_len > 0)  {
-+		if(padapter->registrypriv.wireless_mode == WIRELESS_11B ) {
-+
-+			pbss_network->IELength = pbss_network->IELength - *(p+1) - 2;
-+			ret_rm = rtw_ies_remove_ie(ie , &len, _BEACON_IE_OFFSET_, _ERPINFO_IE_,NULL,0);
-+			RTW_DBG("%s, remove_ie of ERP_IE=%d\n", __FUNCTION__, ret_rm);
-+		} else 
-+			ERP_IE_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p);
-+
-+	}
-+
-+	/* update privacy/security */
-+	if (cap & BIT(4))
-+		pbss_network->Privacy = 1;
-+	else
-+		pbss_network->Privacy = 0;
-+
-+	psecuritypriv->wpa_psk = 0;
-+
-+	/* wpa2 */
-+	akm = 0;
-+	gmcs = 0;
-+	group_cipher = 0;
-+	pairwise_cipher = 0;
-+	psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_;
-+	psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_;
-+	psecuritypriv->akmp = 0;
-+	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
-+	if (p && ie_len > 0) {
-+		if (rtw_parse_wpa2_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, &gmcs, &akm, &mfp_opt) == _SUCCESS) {
-+			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
-+			psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK;
-+			psecuritypriv->dot8021xalg = 1;/* psk,  todo:802.1x */
-+			psecuritypriv->wpa_psk |= BIT(1);
-+
-+			psecuritypriv->wpa2_group_cipher = group_cipher;
-+			psecuritypriv->wpa2_pairwise_cipher = pairwise_cipher;
-+			psecuritypriv->akmp = akm;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+			/**
-+			 * Kernel < v5.x, the auth_type set as
-+			 * NL80211_AUTHTYPE_AUTOMATIC in
-+			 * cfg80211_rtw_start_ap(). if the AKM SAE in the RSN
-+			 * IE, we have to update the auth_type for SAE in
-+			 * rtw_check_beacon_data()
-+			 */
-+			if (CHECK_BIT(WLAN_AKM_TYPE_SAE, akm)) {
-+				RTW_INFO("%s: Auth type as SAE\n", __func__);
-+				psecuritypriv->auth_type = MLME_AUTHTYPE_SAE;
-+				psecuritypriv->auth_alg = WLAN_AUTH_SAE;
-+			}
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+#if 0
-+			switch (group_cipher) {
-+			case WPA_CIPHER_NONE:
-+				psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_;
-+				break;
-+			case WPA_CIPHER_WEP40:
-+				psecuritypriv->wpa2_group_cipher = _WEP40_;
-+				break;
-+			case WPA_CIPHER_TKIP:
-+				psecuritypriv->wpa2_group_cipher = _TKIP_;
-+				break;
-+			case WPA_CIPHER_CCMP:
-+				psecuritypriv->wpa2_group_cipher = _AES_;
-+				break;
-+			case WPA_CIPHER_WEP104:
-+				psecuritypriv->wpa2_group_cipher = _WEP104_;
-+				break;
-+			}
-+
-+			switch (pairwise_cipher) {
-+			case WPA_CIPHER_NONE:
-+				psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_;
-+				break;
-+			case WPA_CIPHER_WEP40:
-+				psecuritypriv->wpa2_pairwise_cipher = _WEP40_;
-+				break;
-+			case WPA_CIPHER_TKIP:
-+				psecuritypriv->wpa2_pairwise_cipher = _TKIP_;
-+				break;
-+			case WPA_CIPHER_CCMP:
-+				psecuritypriv->wpa2_pairwise_cipher = _AES_;
-+				break;
-+			case WPA_CIPHER_WEP104:
-+				psecuritypriv->wpa2_pairwise_cipher = _WEP104_;
-+				break;
-+			}
-+#endif
-+		}
-+
-+	}
-+
-+	/* wpa */
-+	ie_len = 0;
-+	group_cipher = 0;
-+	pairwise_cipher = 0;
-+	psecuritypriv->wpa_group_cipher = _NO_PRIVACY_;
-+	psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_;
-+	for (p = ie + _BEACON_IE_OFFSET_; ; p += (ie_len + 2)) {
-+		p = rtw_get_ie(p, _SSN_IE_1_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));
-+		if ((p) && (_rtw_memcmp(p + 2, OUI1, 4))) {
-+			if (rtw_parse_wpa_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
-+				psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
-+				psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK;
-+				psecuritypriv->dot8021xalg = 1;/* psk,  todo:802.1x */
-+
-+				psecuritypriv->wpa_psk |= BIT(0);
-+
-+				psecuritypriv->wpa_group_cipher = group_cipher;
-+				psecuritypriv->wpa_pairwise_cipher = pairwise_cipher;
-+
-+#if 0
-+				switch (group_cipher) {
-+				case WPA_CIPHER_NONE:
-+					psecuritypriv->wpa_group_cipher = _NO_PRIVACY_;
-+					break;
-+				case WPA_CIPHER_WEP40:
-+					psecuritypriv->wpa_group_cipher = _WEP40_;
-+					break;
-+				case WPA_CIPHER_TKIP:
-+					psecuritypriv->wpa_group_cipher = _TKIP_;
-+					break;
-+				case WPA_CIPHER_CCMP:
-+					psecuritypriv->wpa_group_cipher = _AES_;
-+					break;
-+				case WPA_CIPHER_WEP104:
-+					psecuritypriv->wpa_group_cipher = _WEP104_;
-+					break;
-+				}
-+
-+				switch (pairwise_cipher) {
-+				case WPA_CIPHER_NONE:
-+					psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_;
-+					break;
-+				case WPA_CIPHER_WEP40:
-+					psecuritypriv->wpa_pairwise_cipher = _WEP40_;
-+					break;
-+				case WPA_CIPHER_TKIP:
-+					psecuritypriv->wpa_pairwise_cipher = _TKIP_;
-+					break;
-+				case WPA_CIPHER_CCMP:
-+					psecuritypriv->wpa_pairwise_cipher = _AES_;
-+					break;
-+				case WPA_CIPHER_WEP104:
-+					psecuritypriv->wpa_pairwise_cipher = _WEP104_;
-+					break;
-+				}
-+#endif
-+			}
-+
-+			break;
-+
-+		}
-+
-+		if ((p == NULL) || (ie_len == 0))
-+			break;
-+
-+	}
-+
-+	if (mfp_opt == MFP_INVALID) {
-+		RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter));
-+		return _FAIL;
-+	}
-+	psecuritypriv->mfp_opt = mfp_opt;
-+
-+#ifdef CONFIG_RTW_80211K
-+	/* RRM */
-+	update_rm_cap(pbuf, padapter, len, _BEACON_IE_OFFSET_);
-+
-+#endif /* CONFIG_RTW_80211K */
-+
-+	/* wmm */
-+	ie_len = 0;
-+	pmlmepriv->qospriv.qos_option = 0;
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(padapter))
-+		pmlmepriv->qospriv.qos_option = 1;
-+#endif
-+	if (pregistrypriv->wmm_enable) {
-+		for (p = ie + _BEACON_IE_OFFSET_; ; p += (ie_len + 2)) {
-+			p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));
-+			if ((p) && _rtw_memcmp(p + 2, WMM_PARA_IE, 6)) {
-+				pmlmepriv->qospriv.qos_option = 1;
-+
-+				*(p + 8) |= BIT(7); /* QoS Info, support U-APSD */
-+
-+				/* disable all ACM bits since the WMM admission control is not supported */
-+				*(p + 10) &= ~BIT(4); /* BE */
-+				*(p + 14) &= ~BIT(4); /* BK */
-+				*(p + 18) &= ~BIT(4); /* VI */
-+				*(p + 22) &= ~BIT(4); /* VO */
-+
-+				WMM_param_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p);
-+
-+				break;
-+			}
-+
-+			if ((p == NULL) || (ie_len == 0))
-+				break;
-+		}
-+	}
-+#ifdef CONFIG_80211N_HT
-+	if(padapter->registrypriv.ht_enable &&
-+		is_supported_ht(padapter->registrypriv.wireless_mode)) {
-+		/* parsing HT_CAP_IE */
-+		p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
-+		if (p && ie_len > 0) {
-+			HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor = MAX_AMPDU_FACTOR_64K;
-+			struct rtw_ieee80211_ht_cap *pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2);
-+
-+#ifdef CONFIG_RTW_DEBUG
-+			if (0) {
-+				RTW_INFO(FUNC_ADPT_FMT" HT_CAP_IE from upper layer:\n", FUNC_ADPT_ARG(padapter));
-+				dump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len);
-+			}
-+#endif	/*	CONFIG_RTW_DEBUG	*/
-+			pHT_caps_ie = p;
-+
-+			ht_cap = _TRUE;
-+			network_type |= WIRELESS_11_24N;
-+
-+			rtw_ht_use_default_setting(padapter);
-+
-+			/* Update HT Capabilities Info field */
-+			if (pmlmepriv->htpriv.sgi_20m == _FALSE)
-+				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_20);
-+
-+			if (pmlmepriv->htpriv.sgi_40m == _FALSE)
-+				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_40);
-+
-+			if (!TEST_FLAG(pmlmepriv->htpriv.ldpc_cap, LDPC_HT_ENABLE_RX))
-+				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_LDPC_CODING);
-+
-+			if (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_TX))
-+				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_TX_STBC);
-+
-+			if (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_RX))
-+				pht_cap->cap_info &= ~(IEEE80211_HT_CAP_RX_STBC_3R);
-+
-+			/* Update A-MPDU Parameters field */
-+			pht_cap->ampdu_params_info &= ~(IEEE80211_HT_CAP_AMPDU_FACTOR | IEEE80211_HT_CAP_AMPDU_DENSITY);
-+
-+			if ((psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_CCMP) ||
-+				(psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP)) {
-+				rtw_hal_get_def_var(padapter, HW_VAR_BEST_AMPDU_DENSITY, &best_ampdu_density);
-+				pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (best_ampdu_density << 2));
-+			} else
-+				pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & 0x00);
-+
-+			rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor);
-+			pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_FACTOR & max_rx_ampdu_factor); /* set  Max Rx AMPDU size  to 64K */
-+
-+			_rtw_memcpy(&(pmlmeinfo->HT_caps), pht_cap, sizeof(struct HT_caps_element));
-+
-+			/* Update Supported MCS Set field */
-+			{
-+				u8 rx_nss = 0;
-+				int i;
-+
-+				rx_nss = GET_HAL_RX_NSS(padapter);
-+
-+				/* RX MCS Bitmask */
-+				switch (rx_nss) {
-+				case 1:
-+					set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_1R);
-+					break;
-+				case 2:
-+					set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_2R);
-+					break;
-+				case 3:
-+					set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_3R);
-+					break;
-+				case 4:
-+					set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_4R);
-+					break;
-+				default:
-+					RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", GET_HAL_RFPATH(padapter), rx_nss);
-+				}
-+				for (i = 0; i < 10; i++)
-+					*(HT_CAP_ELE_RX_MCS_MAP(pht_cap) + i) &= padapter->mlmeextpriv.default_supported_mcs_set[i];
-+			}
-+
-+#ifdef CONFIG_BEAMFORMING
-+			/* Use registry value to enable HT Beamforming. */
-+			/* ToDo: use configure file to set these capability. */
-+			pht_cap->tx_BF_cap_info = 0;
-+
-+			/* HT Beamformer */
-+			if (TEST_FLAG(pmlmepriv->htpriv.beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {
-+				/* Transmit NDP Capable */
-+				SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(pht_cap, 1);
-+				/* Explicit Compressed Steering Capable */
-+				SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pht_cap, 1);
-+				/* Compressed Steering Number Antennas */
-+				SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, 1);
-+				rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);
-+				SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pht_cap, rf_num);
-+			}
-+
-+			/* HT Beamformee */
-+			if (TEST_FLAG(pmlmepriv->htpriv.beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {
-+				/* Receive NDP Capable */
-+				SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(pht_cap, 1);
-+				/* Explicit Compressed Beamforming Feedback Capable */
-+				SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pht_cap, 2);
-+				rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
-+				SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, rf_num);
-+			}
-+#endif /* CONFIG_BEAMFORMING */
-+
-+			_rtw_memcpy(&pmlmepriv->htpriv.ht_cap, p + 2, ie_len);
-+#ifdef CONFIG_RTW_DEBUG
-+			if (0) {
-+				RTW_INFO(FUNC_ADPT_FMT" HT_CAP_IE driver masked:\n", FUNC_ADPT_ARG(padapter));
-+				dump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len);
-+			}
-+#endif	/*	CONFIG_RTW_DEBUG	*/
-+		}
-+
-+		/* parsing HT_INFO_IE */
-+		p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
-+		if (p && ie_len > 0) {
-+			pHT_info_ie = p;
-+			if (channel == 0)
-+				pbss_network->Configuration.DSConfig = GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2);
-+			else if (channel != GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2)) {
-+				RTW_INFO(FUNC_ADPT_FMT" ch inconsistent, DSSS:%u, HT primary:%u\n"
-+					, FUNC_ADPT_ARG(padapter), channel, GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2));
-+			}
-+		}
-+	}
-+#endif /* CONFIG_80211N_HT */
-+	pmlmepriv->cur_network.network_type = network_type;
-+
-+#ifdef CONFIG_80211N_HT
-+	pmlmepriv->htpriv.ht_option = _FALSE;
-+
-+	if ((psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) ||
-+	    (psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_TKIP)) {
-+		/* todo: */
-+		/* ht_cap = _FALSE; */
-+	}
-+
-+	/* ht_cap	 */
-+	if (padapter->registrypriv.ht_enable &&
-+		is_supported_ht(padapter->registrypriv.wireless_mode) && ht_cap == _TRUE) {
-+
-+		pmlmepriv->htpriv.ht_option = _TRUE;
-+		pmlmepriv->qospriv.qos_option = 1;
-+
-+		pmlmepriv->htpriv.ampdu_enable = pregistrypriv->ampdu_enable ? _TRUE : _FALSE;
-+
-+		HT_caps_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_caps_ie);
-+
-+		HT_info_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_info_ie);
-+	}
-+#endif
-+
-+#ifdef CONFIG_80211AC_VHT
-+	pmlmepriv->ori_vht_en = 0;
-+	pmlmepriv->vhtpriv.vht_option = _FALSE;
-+
-+	if (pmlmepriv->htpriv.ht_option == _TRUE
-+		&& pbss_network->Configuration.DSConfig > 14
-+		&& REGSTY_IS_11AC_ENABLE(pregistrypriv)
-+		&& is_supported_vht(pregistrypriv->wireless_mode)
-+		&& (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
-+	) {
-+		/* Parsing VHT CAP IE */
-+		p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
-+		if (p && ie_len > 0)
-+			vht_cap = _TRUE;
-+
-+		/* Parsing VHT OPERATION IE */
-+
-+		if (vht_cap == _TRUE
-+			&& MLME_IS_MESH(padapter) /* allow only mesh temporarily before VHT IE checking is ready */
-+		) {
-+			rtw_check_for_vht20(padapter, ie + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_);
-+			pmlmepriv->ori_vht_en = 1;
-+			pmlmepriv->vhtpriv.vht_option = _TRUE;
-+		} else if (REGSTY_IS_11AC_AUTO(pregistrypriv)) {
-+			rtw_vht_ies_detach(padapter, pbss_network);
-+			rtw_vht_ies_attach(padapter, pbss_network);
-+		}
-+	}
-+
-+	if (pmlmepriv->vhtpriv.vht_option == _FALSE)
-+		rtw_vht_ies_detach(padapter, pbss_network);
-+#endif /* CONFIG_80211AC_VHT */
-+
-+#ifdef CONFIG_80211N_HT
-+	if(padapter->registrypriv.ht_enable &&
-+					is_supported_ht(padapter->registrypriv.wireless_mode) &&
-+		pbss_network->Configuration.DSConfig <= 14 && padapter->registrypriv.wifi_spec == 1 &&
-+		pbss_network->IELength + 10 <= MAX_IE_SZ) {
-+		uint len = 0;
-+
-+		SET_EXT_CAPABILITY_ELE_BSS_COEXIST(pmlmepriv->ext_capab_ie_data, 1);
-+		pmlmepriv->ext_capab_ie_len = 10;
-+		rtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len);
-+		pbss_network->IELength += pmlmepriv->ext_capab_ie_len;
-+	}
-+#endif /* CONFIG_80211N_HT */
-+
-+	pbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network);
-+
-+	rtw_ies_get_chbw(pbss_network->IEs + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_
-+		, &pmlmepriv->ori_ch, &pmlmepriv->ori_bw, &pmlmepriv->ori_offset, 1, 1);
-+	rtw_warn_on(pmlmepriv->ori_ch == 0);
-+
-+	{
-+		/* alloc sta_info for ap itself */
-+
-+		struct sta_info *sta;
-+
-+		sta = rtw_get_stainfo(&padapter->stapriv, pbss_network->MacAddress);
-+		if (!sta) {
-+			sta = rtw_alloc_stainfo(&padapter->stapriv, pbss_network->MacAddress);
-+			if (sta == NULL)
-+				return _FAIL;
-+		}
-+	}
-+
-+	rtw_startbss_cmd(padapter, RTW_CMDF_WAIT_ACK);
-+	{
-+		int sk_band = RTW_GET_SCAN_BAND_SKIP(padapter);
-+
-+		if (sk_band)
-+			RTW_CLR_SCAN_BAND_SKIP(padapter, sk_band);
-+	}
-+
-+	rtw_indicate_connect(padapter);
-+
-+	pmlmepriv->cur_network.join_res = _TRUE;/* for check if already set beacon */
-+
-+	/* update bc/mc sta_info */
-+	/* update_bmc_sta(padapter); */
-+
-+	return ret;
-+
-+}
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+void rtw_macaddr_acl_init(_adapter *adapter, u8 period)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct wlan_acl_pool *acl;
-+	_queue *acl_node_q;
-+	int i;
-+	_irqL irqL;
-+
-+	if (period >= RTW_ACL_PERIOD_NUM) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	acl = &stapriv->acl_list[period];
-+	acl_node_q = &acl->acl_node_q;
-+
-+	_rtw_spinlock_init(&(acl_node_q->lock));
-+
-+	_enter_critical_bh(&(acl_node_q->lock), &irqL);
-+	_rtw_init_listhead(&(acl_node_q->queue));
-+	acl->num = 0;
-+	acl->mode = RTW_ACL_MODE_DISABLED;
-+	for (i = 0; i < NUM_ACL; i++) {
-+		_rtw_init_listhead(&acl->aclnode[i].list);
-+		acl->aclnode[i].valid = _FALSE;
-+	}
-+	_exit_critical_bh(&(acl_node_q->lock), &irqL);
-+}
-+
-+static void _rtw_macaddr_acl_deinit(_adapter *adapter, u8 period, bool clear_only)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct wlan_acl_pool *acl;
-+	_queue *acl_node_q;
-+	_irqL irqL;
-+	_list *head, *list;
-+	struct rtw_wlan_acl_node *acl_node;
-+
-+	if (period >= RTW_ACL_PERIOD_NUM) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	acl = &stapriv->acl_list[period];
-+	acl_node_q = &acl->acl_node_q;
-+
-+	_enter_critical_bh(&(acl_node_q->lock), &irqL);
-+	head = get_list_head(acl_node_q);
-+	list = get_next(head);
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);
-+		list = get_next(list);
-+
-+		if (acl_node->valid == _TRUE) {
-+			acl_node->valid = _FALSE;
-+			rtw_list_delete(&acl_node->list);
-+			acl->num--;
-+		}
-+	}
-+	_exit_critical_bh(&(acl_node_q->lock), &irqL);
-+
-+	if (!clear_only)
-+		_rtw_spinlock_free(&(acl_node_q->lock));
-+
-+	rtw_warn_on(acl->num);
-+	acl->mode = RTW_ACL_MODE_DISABLED;
-+}
-+
-+void rtw_macaddr_acl_deinit(_adapter *adapter, u8 period)
-+{
-+	_rtw_macaddr_acl_deinit(adapter, period, 0);
-+}
-+
-+void rtw_macaddr_acl_clear(_adapter *adapter, u8 period)
-+{
-+	_rtw_macaddr_acl_deinit(adapter, period, 1);
-+}
-+
-+void rtw_set_macaddr_acl(_adapter *adapter, u8 period, int mode)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct wlan_acl_pool *acl;
-+
-+	if (period >= RTW_ACL_PERIOD_NUM) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	acl = &stapriv->acl_list[period];
-+
-+	RTW_INFO(FUNC_ADPT_FMT" p=%u, mode=%d\n"
-+		, FUNC_ADPT_ARG(adapter), period, mode);
-+
-+	acl->mode = mode;
-+}
-+
-+int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr)
-+{
-+	_irqL irqL;
-+	_list *list, *head;
-+	u8 existed = 0;
-+	int i = -1, ret = 0;
-+	struct rtw_wlan_acl_node *acl_node;
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct wlan_acl_pool *acl;
-+	_queue *acl_node_q;
-+
-+	if (period >= RTW_ACL_PERIOD_NUM) {
-+		rtw_warn_on(1);
-+		ret = -1;
-+		goto exit;
-+	}
-+
-+	acl = &stapriv->acl_list[period];
-+	acl_node_q = &acl->acl_node_q;
-+
-+	_enter_critical_bh(&(acl_node_q->lock), &irqL);
-+
-+	head = get_list_head(acl_node_q);
-+	list = get_next(head);
-+
-+	/* search for existed entry */
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);
-+		list = get_next(list);
-+
-+		if (_rtw_memcmp(acl_node->addr, addr, ETH_ALEN)) {
-+			if (acl_node->valid == _TRUE) {
-+				existed = 1;
-+				break;
-+			}
-+		}
-+	}
-+	if (existed)
-+		goto release_lock;
-+
-+	if (acl->num >= NUM_ACL)
-+		goto release_lock;
-+
-+	/* find empty one and use */
-+	for (i = 0; i < NUM_ACL; i++) {
-+
-+		acl_node = &acl->aclnode[i];
-+		if (acl_node->valid == _FALSE) {
-+
-+			_rtw_init_listhead(&acl_node->list);
-+			_rtw_memcpy(acl_node->addr, addr, ETH_ALEN);
-+			acl_node->valid = _TRUE;
-+
-+			rtw_list_insert_tail(&acl_node->list, get_list_head(acl_node_q));
-+			acl->num++;
-+			break;
-+		}
-+	}
-+
-+release_lock:
-+	_exit_critical_bh(&(acl_node_q->lock), &irqL);
-+
-+	if (!existed && (i < 0 || i >= NUM_ACL))
-+		ret = -1;
-+
-+	RTW_INFO(FUNC_ADPT_FMT" p=%u "MAC_FMT" %s (acl_num=%d)\n"
-+		 , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr)
-+		, (existed ? "existed" : ((i < 0 || i >= NUM_ACL) ? "no room" : "added"))
-+		 , acl->num);
-+exit:
-+	return ret;
-+}
-+
-+int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr)
-+{
-+	_irqL irqL;
-+	_list *list, *head;
-+	int ret = 0;
-+	struct rtw_wlan_acl_node *acl_node;
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct wlan_acl_pool *acl;
-+	_queue	*acl_node_q;
-+	u8 is_baddr = is_broadcast_mac_addr(addr);
-+	u8 match = 0;
-+
-+	if (period >= RTW_ACL_PERIOD_NUM) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	acl = &stapriv->acl_list[period];
-+	acl_node_q = &acl->acl_node_q;
-+
-+	_enter_critical_bh(&(acl_node_q->lock), &irqL);
-+
-+	head = get_list_head(acl_node_q);
-+	list = get_next(head);
-+
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);
-+		list = get_next(list);
-+
-+		if (is_baddr || _rtw_memcmp(acl_node->addr, addr, ETH_ALEN)) {
-+			if (acl_node->valid == _TRUE) {
-+				acl_node->valid = _FALSE;
-+				rtw_list_delete(&acl_node->list);
-+				acl->num--;
-+				match = 1;
-+			}
-+		}
-+	}
-+
-+	_exit_critical_bh(&(acl_node_q->lock), &irqL);
-+
-+	RTW_INFO(FUNC_ADPT_FMT" p=%u "MAC_FMT" %s (acl_num=%d)\n"
-+		 , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr)
-+		 , is_baddr ? "clear all" : (match ? "match" : "no found")
-+		 , acl->num);
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_RTW_MACADDR_ACL */
-+
-+u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk)
-+{
-+	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
-+	struct cmd_obj *cmd;
-+	struct set_stakey_parm *param;
-+	u8	res = _SUCCESS;
-+
-+	cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (cmd == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	param = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));
-+	if (param == NULL) {
-+		rtw_mfree((u8 *) cmd, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	init_h2fwcmd_w_parm_no_rsp(cmd, param, CMD_SET_STAKEY);
-+
-+	_rtw_memcpy(param->addr, addr, ETH_ALEN);
-+	param->algorithm = alg;
-+	param->keyid = keyid;
-+	if (!!(alg & _SEC_TYPE_256_))
-+		_rtw_memcpy(param->key, key, 32);
-+	else
-+		_rtw_memcpy(param->key, key, 16);
-+	param->gk = gk;
-+
-+	res = rtw_enqueue_cmd(cmdpriv, cmd);
-+
-+exit:
-+	return res;
-+}
-+
-+u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta)
-+{
-+	return rtw_ap_set_sta_key(padapter
-+		, psta->cmn.mac_addr
-+		, psta->dot118021XPrivacy
-+		, psta->dot118021x_UncstKey.skey
-+		, 0
-+		, 0
-+	);
-+}
-+
-+static int rtw_ap_set_key(_adapter *padapter, u8 *key, u8 alg, int keyid, u8 set_tx)
-+{
-+	u8 keylen;
-+	struct cmd_obj *pcmd;
-+	struct setkey_parm *psetkeyparm;
-+	struct cmd_priv	*pcmdpriv = &(padapter->cmdpriv);
-+	int res = _SUCCESS;
-+
-+	/* RTW_INFO("%s\n", __FUNCTION__); */
-+
-+	pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (pcmd == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	psetkeyparm = (struct setkey_parm *)rtw_zmalloc(sizeof(struct setkey_parm));
-+	if (psetkeyparm == NULL) {
-+		rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	_rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm));
-+
-+	psetkeyparm->keyid = (u8)keyid;
-+	if (is_wep_enc(alg))
-+		padapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid);
-+
-+	psetkeyparm->algorithm = alg;
-+
-+	psetkeyparm->set_tx = set_tx;
-+
-+	switch (alg) {
-+	case _WEP40_:
-+		keylen = 5;
-+		break;
-+	case _WEP104_:
-+		keylen = 13;
-+		break;
-+	case _GCMP_256_:
-+	case _CCMP_256_:
-+		keylen = 32;
-+		break;
-+	case _TKIP_:
-+	case _TKIP_WTMIC_:
-+	case _AES_:
-+	case _GCMP_:
-+	default:
-+		keylen = 16;
-+	}
-+
-+	_rtw_memcpy(&(psetkeyparm->key[0]), key, keylen);
-+
-+	pcmd->cmdcode = CMD_SET_KEY; /*_SetKey_CMD_;*/
-+	pcmd->parmbuf = (u8 *)psetkeyparm;
-+	pcmd->cmdsz = (sizeof(struct setkey_parm));
-+	pcmd->rsp = NULL;
-+	pcmd->rspsz = 0;
-+
-+
-+	_rtw_init_listhead(&pcmd->list);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, pcmd);
-+
-+exit:
-+
-+	return res;
-+}
-+
-+int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid)
-+{
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	return rtw_ap_set_key(padapter, key, alg, keyid, 1);
-+}
-+
-+int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx)
-+{
-+	u8 alg;
-+
-+	switch (keylen) {
-+	case 5:
-+		alg = _WEP40_;
-+		break;
-+	case 13:
-+		alg = _WEP104_;
-+		break;
-+	default:
-+		alg = _NO_PRIVACY_;
-+	}
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	return rtw_ap_set_key(padapter, key, alg, keyid, set_tx);
-+}
-+
-+u8 rtw_ap_bmc_frames_hdl(_adapter *padapter)
-+{
-+#define HIQ_XMIT_COUNTS (6)
-+	_irqL irqL;
-+	struct sta_info *psta_bmc;
-+	_list	*xmitframe_plist, *xmitframe_phead;
-+	struct xmit_frame *pxmitframe = NULL;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	struct sta_priv  *pstapriv = &padapter->stapriv;
-+	bool update_tim = _FALSE;
-+
-+
-+	if (padapter->registrypriv.wifi_spec != 1)
-+		return H2C_SUCCESS;
-+
-+
-+	psta_bmc = rtw_get_bcmc_stainfo(padapter);
-+	if (!psta_bmc)
-+		return H2C_SUCCESS;
-+
-+
-+	_enter_critical_bh(&pxmitpriv->lock, &irqL);
-+
-+	if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) {
-+		int tx_counts = 0;
-+
-+		_update_beacon(padapter, _TIM_IE_, NULL, _FALSE, 0, "update TIM with TIB=1");
-+
-+		RTW_INFO("sleepq_len of bmc_sta = %d\n", psta_bmc->sleepq_len);
-+
-+		xmitframe_phead = get_list_head(&psta_bmc->sleep_q);
-+		xmitframe_plist = get_next(xmitframe_phead);
-+
-+		while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
-+			pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
-+
-+			xmitframe_plist = get_next(xmitframe_plist);
-+
-+			rtw_list_delete(&pxmitframe->list);
-+
-+			psta_bmc->sleepq_len--;
-+			tx_counts++;
-+
-+			if (psta_bmc->sleepq_len > 0)
-+				pxmitframe->attrib.mdata = 1;
-+			else
-+				pxmitframe->attrib.mdata = 0;
-+
-+			if (tx_counts == HIQ_XMIT_COUNTS)
-+				pxmitframe->attrib.mdata = 0;
-+
-+			pxmitframe->attrib.triggered = 1;
-+
-+			if (xmitframe_hiq_filter(pxmitframe) == _TRUE)
-+				pxmitframe->attrib.qsel = QSLT_HIGH;/*HIQ*/
-+
-+			rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
-+
-+			if (tx_counts == HIQ_XMIT_COUNTS)
-+				break;
-+
-+		}
-+
-+	} else {
-+		if (psta_bmc->sleepq_len == 0) {
-+
-+			/*RTW_INFO("sleepq_len of bmc_sta = %d\n", psta_bmc->sleepq_len);*/
-+
-+			if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0))
-+				update_tim = _TRUE;
-+
-+			rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);
-+			rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);
-+
-+			if (update_tim == _TRUE) {
-+				RTW_INFO("clear TIB\n");
-+				_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "bmc sleepq and HIQ empty");
-+			}
-+		}
-+	}
-+
-+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
-+
-+#if 0
-+	/* HIQ Check */
-+	rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);
-+
-+	while (_FALSE == empty && rtw_get_passing_time_ms(start) < 3000) {
-+		rtw_msleep_os(100);
-+		rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);
-+	}
-+
-+
-+	printk("check if hiq empty=%d\n", empty);
-+#endif
-+
-+	return H2C_SUCCESS;
-+}
-+
-+#ifdef CONFIG_NATIVEAP_MLME
-+
-+static void associated_stainfo_update(_adapter *padapter, struct sta_info *psta, u32 sta_info_type)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	RTW_INFO("%s: "MAC_FMT", updated_type=0x%x\n", __func__, MAC_ARG(psta->cmn.mac_addr), sta_info_type);
-+#ifdef CONFIG_80211N_HT
-+	if (sta_info_type & STA_INFO_UPDATE_BW) {
-+
-+		if ((psta->flags & WLAN_STA_HT) && !psta->ht_20mhz_set) {
-+			if (pmlmepriv->sw_to_20mhz) {
-+				psta->cmn.bw_mode = CHANNEL_WIDTH_20;
-+				/*psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;*/
-+				psta->htpriv.sgi_40m = _FALSE;
-+			} else {
-+				/*TODO: Switch back to 40MHZ?80MHZ*/
-+			}
-+		}
-+	}
-+#endif /* CONFIG_80211N_HT */
-+	/*
-+		if (sta_info_type & STA_INFO_UPDATE_RATE) {
-+
-+		}
-+	*/
-+
-+	if (sta_info_type & STA_INFO_UPDATE_PROTECTION_MODE)
-+		VCS_update(padapter, psta);
-+
-+	/*
-+		if (sta_info_type & STA_INFO_UPDATE_CAP) {
-+
-+		}
-+
-+		if (sta_info_type & STA_INFO_UPDATE_HT_CAP) {
-+
-+		}
-+
-+		if (sta_info_type & STA_INFO_UPDATE_VHT_CAP) {
-+
-+		}
-+	*/
-+
-+}
-+
-+static void update_bcn_ext_capab_ie(_adapter *padapter)
-+{
-+	sint ie_len = 0;
-+	unsigned char	*pbuf;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
-+	u8 *ie = pnetwork->IEs;
-+	u8 null_extcap_data[8] = {0};
-+
-+	pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
-+	if (pbuf && ie_len > 0)
-+		rtw_remove_bcn_ie(padapter, pnetwork, _EXT_CAP_IE_);
-+
-+	if ((pmlmepriv->ext_capab_ie_len > 0) &&
-+	    (_rtw_memcmp(pmlmepriv->ext_capab_ie_data, null_extcap_data, sizeof(null_extcap_data)) == _FALSE))
-+		rtw_add_bcn_ie(padapter, pnetwork, _EXT_CAP_IE_, pmlmepriv->ext_capab_ie_data, pmlmepriv->ext_capab_ie_len);
-+
-+}
-+
-+static void update_bcn_erpinfo_ie(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
-+	unsigned char *p, *ie = pnetwork->IEs;
-+	u32 len = 0;
-+
-+	RTW_INFO("%s, ERP_enable=%d\n", __FUNCTION__, pmlmeinfo->ERP_enable);
-+
-+	if (!pmlmeinfo->ERP_enable)
-+		return;
-+
-+	/* parsing ERP_IE */
-+	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
-+	if (p && len > 0) {
-+		PNDIS_802_11_VARIABLE_IEs pIE = (PNDIS_802_11_VARIABLE_IEs)p;
-+
-+		if (pmlmepriv->num_sta_non_erp == 1)
-+			pIE->data[0] |= RTW_ERP_INFO_NON_ERP_PRESENT | RTW_ERP_INFO_USE_PROTECTION;
-+		else
-+			pIE->data[0] &= ~(RTW_ERP_INFO_NON_ERP_PRESENT | RTW_ERP_INFO_USE_PROTECTION);
-+
-+		if (pmlmepriv->num_sta_no_short_preamble > 0)
-+			pIE->data[0] |= RTW_ERP_INFO_BARKER_PREAMBLE_MODE;
-+		else
-+			pIE->data[0] &= ~(RTW_ERP_INFO_BARKER_PREAMBLE_MODE);
-+
-+		ERP_IE_handler(padapter, pIE);
-+	}
-+
-+}
-+
-+static void update_bcn_htcap_ie(_adapter *padapter)
-+{
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+}
-+
-+static void update_bcn_htinfo_ie(_adapter *padapter)
-+{
-+#ifdef CONFIG_80211N_HT
-+	/*
-+	u8 beacon_updated = _FALSE;
-+	u32 sta_info_update_type = STA_INFO_UPDATE_NONE;
-+	*/
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
-+	unsigned char *p, *ie = pnetwork->IEs;
-+	u32 len = 0;
-+
-+	if (pmlmepriv->htpriv.ht_option == _FALSE)
-+		return;
-+
-+	if (pmlmeinfo->HT_info_enable != 1)
-+		return;
-+
-+
-+	RTW_INFO("%s current operation mode=0x%X\n",
-+		 __FUNCTION__, pmlmepriv->ht_op_mode);
-+
-+	RTW_INFO("num_sta_40mhz_intolerant(%d), 20mhz_width_req(%d), intolerant_ch_rpt(%d), olbc(%d)\n",
-+		pmlmepriv->num_sta_40mhz_intolerant, pmlmepriv->ht_20mhz_width_req, pmlmepriv->ht_intolerant_ch_reported, ATOMIC_READ(&pmlmepriv->olbc));
-+
-+	/*parsing HT_INFO_IE, currently only update ht_op_mode - pht_info->infos[1] & pht_info->infos[2] for wifi logo test*/
-+	p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
-+	if (p && len > 0) {
-+		struct HT_info_element *pht_info = NULL;
-+
-+		pht_info = (struct HT_info_element *)(p + 2);
-+
-+		/* for STA Channel Width/Secondary Channel Offset*/
-+		if ((pmlmepriv->sw_to_20mhz == 0) && (pmlmeext->cur_channel <= 14)) {
-+			if ((pmlmepriv->num_sta_40mhz_intolerant > 0) || (pmlmepriv->ht_20mhz_width_req == _TRUE)
-+			    || (pmlmepriv->ht_intolerant_ch_reported == _TRUE) || (ATOMIC_READ(&pmlmepriv->olbc) == _TRUE)) {
-+				SET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info, 0);
-+				SET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 0);
-+
-+				pmlmepriv->sw_to_20mhz = 1;
-+				/*
-+				sta_info_update_type |= STA_INFO_UPDATE_BW;
-+				beacon_updated = _TRUE;
-+				*/
-+
-+				RTW_INFO("%s:switching to 20Mhz\n", __FUNCTION__);
-+
-+				/*TODO : cur_bwmode/cur_ch_offset switches to 20Mhz*/
-+			}
-+		} else {
-+
-+			if ((pmlmepriv->num_sta_40mhz_intolerant == 0) && (pmlmepriv->ht_20mhz_width_req == _FALSE)
-+			    && (pmlmepriv->ht_intolerant_ch_reported == _FALSE) && (ATOMIC_READ(&pmlmepriv->olbc) == _FALSE)) {
-+
-+				if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_40) {
-+
-+					SET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 1);
-+
-+					SET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info,
-+						(pmlmeext->cur_ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) ?
-+						HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE : HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW);
-+
-+					pmlmepriv->sw_to_20mhz = 0;
-+					/*
-+					sta_info_update_type |= STA_INFO_UPDATE_BW;
-+					beacon_updated = _TRUE;
-+					*/
-+
-+					RTW_INFO("%s:switching back to 40Mhz\n", __FUNCTION__);
-+				}
-+			}
-+		}
-+
-+		/* to update  ht_op_mode*/
-+		*(u16 *)(pht_info->infos + 1) = cpu_to_le16(pmlmepriv->ht_op_mode);
-+
-+	}
-+
-+	/*associated_clients_update(padapter, beacon_updated, sta_info_update_type);*/
-+#endif /* CONFIG_80211N_HT */
-+}
-+
-+static void update_bcn_rsn_ie(_adapter *padapter)
-+{
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+}
-+
-+static void update_bcn_wpa_ie(_adapter *padapter)
-+{
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+}
-+
-+static void update_bcn_wmm_ie(_adapter *padapter)
-+{
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+}
-+
-+static void update_bcn_wps_ie(_adapter *padapter)
-+{
-+	u8 *pwps_ie = NULL, *pwps_ie_src, *premainder_ie, *pbackup_remainder_ie = NULL;
-+	uint wps_ielen = 0, wps_offset, remainder_ielen;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
-+	unsigned char *ie = pnetwork->IEs;
-+	u32 ielen = pnetwork->IELength;
-+
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	pwps_ie = rtw_get_wps_ie(ie + _FIXED_IE_LENGTH_, ielen - _FIXED_IE_LENGTH_, NULL, &wps_ielen);
-+
-+	if (pwps_ie == NULL || wps_ielen == 0)
-+		return;
-+
-+	pwps_ie_src = pmlmepriv->wps_beacon_ie;
-+	if (pwps_ie_src == NULL)
-+		return;
-+
-+	wps_offset = (uint)(pwps_ie - ie);
-+
-+	premainder_ie = pwps_ie + wps_ielen;
-+
-+	remainder_ielen = ielen - wps_offset - wps_ielen;
-+
-+	if (remainder_ielen > 0) {
-+		pbackup_remainder_ie = rtw_malloc(remainder_ielen);
-+		if (pbackup_remainder_ie)
-+			_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
-+	}
-+
-+	wps_ielen = (uint)pwps_ie_src[1];/* to get ie data len */
-+	if ((wps_offset + wps_ielen + 2 + remainder_ielen) <= MAX_IE_SZ) {
-+		_rtw_memcpy(pwps_ie, pwps_ie_src, wps_ielen + 2);
-+		pwps_ie += (wps_ielen + 2);
-+
-+		if (pbackup_remainder_ie)
-+			_rtw_memcpy(pwps_ie, pbackup_remainder_ie, remainder_ielen);
-+
-+		/* update IELength */
-+		pnetwork->IELength = wps_offset + (wps_ielen + 2) + remainder_ielen;
-+	}
-+
-+	if (pbackup_remainder_ie)
-+		rtw_mfree(pbackup_remainder_ie, remainder_ielen);
-+
-+	/* deal with the case without set_tx_beacon_cmd() in update_beacon() */
-+#if defined(CONFIG_INTERRUPT_BASED_TXBCN) || defined(CONFIG_PCI_HCI)
-+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
-+		u8 sr = 0;
-+		rtw_get_wps_attr_content(pwps_ie_src,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);
-+
-+		if (sr) {
-+			set_fwstate(pmlmepriv, WIFI_UNDER_WPS);
-+			RTW_INFO("%s, set WIFI_UNDER_WPS\n", __func__);
-+		} else {
-+			clr_fwstate(pmlmepriv, WIFI_UNDER_WPS);
-+			RTW_INFO("%s, clr WIFI_UNDER_WPS\n", __func__);
-+		}
-+	}
-+#endif
-+}
-+
-+static void update_bcn_p2p_ie(_adapter *padapter)
-+{
-+
-+}
-+
-+static void update_bcn_vendor_spec_ie(_adapter *padapter, u8 *oui)
-+{
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	if (_rtw_memcmp(RTW_WPA_OUI, oui, 4))
-+		update_bcn_wpa_ie(padapter);
-+	else if (_rtw_memcmp(WMM_OUI, oui, 4))
-+		update_bcn_wmm_ie(padapter);
-+	else if (_rtw_memcmp(WPS_OUI, oui, 4))
-+		update_bcn_wps_ie(padapter);
-+	else if (_rtw_memcmp(P2P_OUI, oui, 4))
-+		update_bcn_p2p_ie(padapter);
-+	else
-+		RTW_INFO("unknown OUI type!\n");
-+
-+
-+}
-+
-+void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, u8 flags, const char *tag)
-+{
-+	_irqL irqL;
-+	struct mlme_priv *pmlmepriv;
-+	struct mlme_ext_priv *pmlmeext;
-+	bool updated = 1; /* treat as upadated by default */
-+
-+	if (!padapter)
-+		return;
-+
-+	pmlmepriv = &(padapter->mlmepriv);
-+	pmlmeext = &(padapter->mlmeextpriv);
-+
-+	if (pmlmeext->bstart_bss == _FALSE)
-+		return;
-+
-+	_enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
-+
-+	switch (ie_id) {
-+	case _TIM_IE_:
-+		update_BCNTIM(padapter);
-+		break;
-+
-+	case _ERPINFO_IE_:
-+		update_bcn_erpinfo_ie(padapter);
-+		break;
-+
-+	case _HT_CAPABILITY_IE_:
-+		update_bcn_htcap_ie(padapter);
-+		break;
-+
-+	case _RSN_IE_2_:
-+		update_bcn_rsn_ie(padapter);
-+		break;
-+
-+	case _HT_ADD_INFO_IE_:
-+		update_bcn_htinfo_ie(padapter);
-+		break;
-+
-+	case _EXT_CAP_IE_:
-+		update_bcn_ext_capab_ie(padapter);
-+		break;
-+
-+#ifdef CONFIG_RTW_MESH
-+	case WLAN_EID_MESH_CONFIG:
-+		updated = rtw_mesh_update_bss_peering_status(padapter, &(pmlmeext->mlmext_info.network));
-+		updated |= rtw_mesh_update_bss_formation_info(padapter, &(pmlmeext->mlmext_info.network));
-+		updated |= rtw_mesh_update_bss_forwarding_state(padapter, &(pmlmeext->mlmext_info.network));
-+		break;
-+#endif
-+
-+	case _VENDOR_SPECIFIC_IE_:
-+		update_bcn_vendor_spec_ie(padapter, oui);
-+		break;
-+
-+	case 0xFF:
-+	default:
-+		break;
-+	}
-+
-+	if (updated)
-+		pmlmepriv->update_bcn = _TRUE;
-+
-+	_exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
-+
-+#ifndef CONFIG_INTERRUPT_BASED_TXBCN
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_PCI_BCN_POLLING)
-+	if (tx && updated) {
-+		/* send_beacon(padapter); */ /* send_beacon must execute on TSR level */
-+		if (0)
-+			RTW_INFO(FUNC_ADPT_FMT" ie_id:%u - %s\n", FUNC_ADPT_ARG(padapter), ie_id, tag);
-+		if(flags == RTW_CMDF_WAIT_ACK)
-+			set_tx_beacon_cmd(padapter, RTW_CMDF_WAIT_ACK);
-+		else
-+			set_tx_beacon_cmd(padapter, 0);
-+	}
-+#else
-+	{
-+		/* PCI will issue beacon when BCN interrupt occurs.		 */
-+	}
-+#endif
-+#endif /* !CONFIG_INTERRUPT_BASED_TXBCN */
-+}
-+
-+#ifdef CONFIG_80211N_HT
-+
-+void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len)
-+{
-+	struct sta_info *psta;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	u8 beacon_updated = _FALSE;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	uint frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr);
-+	u8 category, action;
-+
-+	psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
-+	if (psta == NULL)
-+		return;
-+
-+
-+	category = frame_body[0];
-+	action = frame_body[1];
-+
-+	if (frame_body_len > 0) {
-+		if ((frame_body[2] == EID_BSSCoexistence) && (frame_body[3] > 0)) {
-+			u8 ie_data = frame_body[4];
-+
-+			if (ie_data & RTW_WLAN_20_40_BSS_COEX_40MHZ_INTOL) {
-+				if (psta->ht_40mhz_intolerant == 0) {
-+					psta->ht_40mhz_intolerant = 1;
-+					pmlmepriv->num_sta_40mhz_intolerant++;
-+					beacon_updated = _TRUE;
-+				}
-+			} else if (ie_data & RTW_WLAN_20_40_BSS_COEX_20MHZ_WIDTH_REQ)	{
-+				if (pmlmepriv->ht_20mhz_width_req == _FALSE) {
-+					pmlmepriv->ht_20mhz_width_req = _TRUE;
-+					beacon_updated = _TRUE;
-+				}
-+			} else
-+				beacon_updated = _FALSE;
-+		}
-+	}
-+
-+	if (frame_body_len > 8) {
-+		/* if EID_BSSIntolerantChlReport ie exists */
-+		if ((frame_body[5] == EID_BSSIntolerantChlReport) && (frame_body[6] > 0)) {
-+			/*todo:*/
-+			if (pmlmepriv->ht_intolerant_ch_reported == _FALSE) {
-+				pmlmepriv->ht_intolerant_ch_reported = _TRUE;
-+				beacon_updated = _TRUE;
-+			}
-+		}
-+	}
-+
-+	if (beacon_updated) {
-+
-+		update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0);
-+
-+		associated_stainfo_update(padapter, psta, STA_INFO_UPDATE_BW);
-+	}
-+
-+
-+
-+}
-+
-+void rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field)
-+{
-+	u8 e_field, m_field;
-+	struct sta_info *psta;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+	psta = rtw_get_stainfo(pstapriv, ta);
-+	if (psta == NULL)
-+		return;
-+
-+	e_field = (ctrl_field & BIT(0)) ? 1 : 0; /*SM Power Save Enabled*/
-+	m_field = (ctrl_field & BIT(1)) ? 1 : 0; /*SM Mode, 0:static SMPS, 1:dynamic SMPS*/
-+
-+	if (e_field) {
-+		if (m_field) { /*mode*/
-+			psta->htpriv.smps_cap = WLAN_HT_CAP_SM_PS_DYNAMIC;
-+			RTW_ERR("Don't support dynamic SMPS\n");
-+		}
-+		else
-+			psta->htpriv.smps_cap = WLAN_HT_CAP_SM_PS_STATIC;
-+	} else {
-+		/*disable*/
-+		psta->htpriv.smps_cap = WLAN_HT_CAP_SM_PS_DISABLED;
-+	}
-+
-+	if (psta->htpriv.smps_cap != WLAN_HT_CAP_SM_PS_DYNAMIC)
-+		rtw_ssmps_wk_cmd(padapter, psta, e_field, 1);
-+}
-+
-+/*
-+op_mode
-+Set to 0 (HT pure) under the followign conditions
-+	- all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or
-+	- all STAs in the BSS are 20 MHz HT in 20 MHz BSS
-+Set to 1 (HT non-member protection) if there may be non-HT STAs
-+	in both the primary and the secondary channel
-+Set to 2 if only HT STAs are associated in BSS,
-+	however and at least one 20 MHz HT STA is associated
-+Set to 3 (HT mixed mode) when one or more non-HT STAs are associated
-+	(currently non-GF HT station is considered as non-HT STA also)
-+*/
-+int rtw_ht_operation_update(_adapter *padapter)
-+{
-+	u16 cur_op_mode, new_op_mode;
-+	int op_mode_changes = 0;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct ht_priv	*phtpriv_ap = &pmlmepriv->htpriv;
-+
-+	if (pmlmepriv->htpriv.ht_option == _FALSE)
-+		return 0;
-+
-+	/*if (!iface->conf->ieee80211n || iface->conf->ht_op_mode_fixed)
-+		return 0;*/
-+
-+	RTW_INFO("%s current operation mode=0x%X\n",
-+		 __FUNCTION__, pmlmepriv->ht_op_mode);
-+
-+	if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)
-+	    && pmlmepriv->num_sta_ht_no_gf) {
-+		pmlmepriv->ht_op_mode |=
-+			HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT;
-+		op_mode_changes++;
-+	} else if ((pmlmepriv->ht_op_mode &
-+		    HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT) &&
-+		   pmlmepriv->num_sta_ht_no_gf == 0) {
-+		pmlmepriv->ht_op_mode &=
-+			~HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT;
-+		op_mode_changes++;
-+	}
-+
-+	if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) &&
-+	    (pmlmepriv->num_sta_no_ht || ATOMIC_READ(&pmlmepriv->olbc_ht))) {
-+		pmlmepriv->ht_op_mode |= HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT;
-+		op_mode_changes++;
-+	} else if ((pmlmepriv->ht_op_mode &
-+		    HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) &&
-+		   (pmlmepriv->num_sta_no_ht == 0 && !ATOMIC_READ(&pmlmepriv->olbc_ht))) {
-+		pmlmepriv->ht_op_mode &=
-+			~HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT;
-+		op_mode_changes++;
-+	}
-+
-+	/* Note: currently we switch to the MIXED op mode if HT non-greenfield
-+	 * station is associated. Probably it's a theoretical case, since
-+	 * it looks like all known HT STAs support greenfield.
-+	 */
-+	new_op_mode = 0;
-+	if (pmlmepriv->num_sta_no_ht /*||
-+	    (pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/)
-+		new_op_mode = OP_MODE_MIXED;
-+	else if ((phtpriv_ap->ht_cap.cap_info & IEEE80211_HT_CAP_SUP_WIDTH)
-+		 && pmlmepriv->num_sta_ht_20mhz)
-+		new_op_mode = OP_MODE_20MHZ_HT_STA_ASSOCED;
-+	else if (ATOMIC_READ(&pmlmepriv->olbc_ht))
-+		new_op_mode = OP_MODE_MAY_BE_LEGACY_STAS;
-+	else
-+		new_op_mode = OP_MODE_PURE;
-+
-+	cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK;
-+	if (cur_op_mode != new_op_mode) {
-+		pmlmepriv->ht_op_mode &= ~HT_INFO_OPERATION_MODE_OP_MODE_MASK;
-+		pmlmepriv->ht_op_mode |= new_op_mode;
-+		op_mode_changes++;
-+	}
-+
-+	RTW_INFO("%s new operation mode=0x%X changes=%d\n",
-+		 __FUNCTION__, pmlmepriv->ht_op_mode, op_mode_changes);
-+
-+	return op_mode_changes;
-+
-+}
-+
-+#endif /* CONFIG_80211N_HT */
-+
-+void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type)
-+{
-+	/* update associcated stations cap. */
-+	if (updated == _TRUE) {
-+		_irqL irqL;
-+		_list	*phead, *plist;
-+		struct sta_info *psta = NULL;
-+		struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+		phead = &pstapriv->asoc_list;
-+		plist = get_next(phead);
-+
-+		/* check asoc_queue */
-+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+			psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+
-+			plist = get_next(plist);
-+
-+			associated_stainfo_update(padapter, psta, sta_info_type);
-+		}
-+
-+		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+	}
-+
-+}
-+
-+/* called > TSR LEVEL for USB or SDIO Interface*/
-+void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
-+{
-+	u8 beacon_updated = _FALSE;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+
-+
-+#if 0
-+	if (!(psta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) &&
-+	    !psta->no_short_preamble_set) {
-+		psta->no_short_preamble_set = 1;
-+		pmlmepriv->num_sta_no_short_preamble++;
-+		if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
-+		    (pmlmepriv->num_sta_no_short_preamble == 1))
-+			ieee802_11_set_beacons(hapd->iface);
-+	}
-+#endif
-+
-+
-+	if (!(psta->flags & WLAN_STA_SHORT_PREAMBLE)) {
-+		if (!psta->no_short_preamble_set) {
-+			psta->no_short_preamble_set = 1;
-+
-+			pmlmepriv->num_sta_no_short_preamble++;
-+
-+			if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
-+			    (pmlmepriv->num_sta_no_short_preamble == 1))
-+				beacon_updated = _TRUE;
-+		}
-+	} else {
-+		if (psta->no_short_preamble_set) {
-+			psta->no_short_preamble_set = 0;
-+
-+			pmlmepriv->num_sta_no_short_preamble--;
-+
-+			if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
-+			    (pmlmepriv->num_sta_no_short_preamble == 0))
-+				beacon_updated = _TRUE;
-+		}
-+	}
-+
-+#if 0
-+	if (psta->flags & WLAN_STA_NONERP && !psta->nonerp_set) {
-+		psta->nonerp_set = 1;
-+		pmlmepriv->num_sta_non_erp++;
-+		if (pmlmepriv->num_sta_non_erp == 1)
-+			ieee802_11_set_beacons(hapd->iface);
-+	}
-+#endif
-+
-+	if (psta->flags & WLAN_STA_NONERP) {
-+		if (!psta->nonerp_set) {
-+			psta->nonerp_set = 1;
-+
-+			pmlmepriv->num_sta_non_erp++;
-+
-+			if (pmlmepriv->num_sta_non_erp == 1) {
-+				beacon_updated = _TRUE;
-+				update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0);
-+			}
-+		}
-+
-+	} else {
-+		if (psta->nonerp_set) {
-+			psta->nonerp_set = 0;
-+
-+			pmlmepriv->num_sta_non_erp--;
-+
-+			if (pmlmepriv->num_sta_non_erp == 0) {
-+				beacon_updated = _TRUE;
-+				update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0);
-+			}
-+		}
-+
-+	}
-+
-+
-+#if 0
-+	if (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT) &&
-+	    !psta->no_short_slot_time_set) {
-+		psta->no_short_slot_time_set = 1;
-+		pmlmepriv->num_sta_no_short_slot_time++;
-+		if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
-+		    (pmlmepriv->num_sta_no_short_slot_time == 1))
-+			ieee802_11_set_beacons(hapd->iface);
-+	}
-+#endif
-+
-+	if (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT)) {
-+		if (!psta->no_short_slot_time_set) {
-+			psta->no_short_slot_time_set = 1;
-+
-+			pmlmepriv->num_sta_no_short_slot_time++;
-+
-+			if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
-+			    (pmlmepriv->num_sta_no_short_slot_time == 1))
-+				beacon_updated = _TRUE;
-+		}
-+	} else {
-+		if (psta->no_short_slot_time_set) {
-+			psta->no_short_slot_time_set = 0;
-+
-+			pmlmepriv->num_sta_no_short_slot_time--;
-+
-+			if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
-+			    (pmlmepriv->num_sta_no_short_slot_time == 0))
-+				beacon_updated = _TRUE;
-+		}
-+	}
-+
-+#ifdef CONFIG_80211N_HT
-+	if(padapter->registrypriv.ht_enable &&
-+		is_supported_ht(padapter->registrypriv.wireless_mode)) {
-+		if (psta->flags & WLAN_STA_HT) {
-+			u16 ht_capab = le16_to_cpu(psta->htpriv.ht_cap.cap_info);
-+
-+			RTW_INFO("HT: STA " MAC_FMT " HT Capabilities Info: 0x%04x\n",
-+				MAC_ARG(psta->cmn.mac_addr), ht_capab);
-+
-+			if (psta->no_ht_set) {
-+				psta->no_ht_set = 0;
-+				pmlmepriv->num_sta_no_ht--;
-+			}
-+
-+			if ((ht_capab & IEEE80211_HT_CAP_GRN_FLD) == 0) {
-+				if (!psta->no_ht_gf_set) {
-+					psta->no_ht_gf_set = 1;
-+					pmlmepriv->num_sta_ht_no_gf++;
-+				}
-+				RTW_INFO("%s STA " MAC_FMT " - no "
-+					 "greenfield, num of non-gf stations %d\n",
-+					 __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),
-+					 pmlmepriv->num_sta_ht_no_gf);
-+			}
-+
-+			if ((ht_capab & IEEE80211_HT_CAP_SUP_WIDTH) == 0) {
-+				if (!psta->ht_20mhz_set) {
-+					psta->ht_20mhz_set = 1;
-+					pmlmepriv->num_sta_ht_20mhz++;
-+				}
-+				RTW_INFO("%s STA " MAC_FMT " - 20 MHz HT, "
-+					 "num of 20MHz HT STAs %d\n",
-+					 __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),
-+					 pmlmepriv->num_sta_ht_20mhz);
-+			}
-+
-+			if (((ht_capab & RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT) != 0) &&
-+				(psta->ht_40mhz_intolerant == 0)) {
-+				psta->ht_40mhz_intolerant = 1;
-+				pmlmepriv->num_sta_40mhz_intolerant++;
-+				RTW_INFO("%s STA " MAC_FMT " - 40MHZ_INTOLERANT, ",
-+					   __FUNCTION__, MAC_ARG(psta->cmn.mac_addr));
-+			}
-+
-+		} else {
-+			if (!psta->no_ht_set) {
-+				psta->no_ht_set = 1;
-+				pmlmepriv->num_sta_no_ht++;
-+			}
-+			if (pmlmepriv->htpriv.ht_option == _TRUE) {
-+				RTW_INFO("%s STA " MAC_FMT
-+					 " - no HT, num of non-HT stations %d\n",
-+					 __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),
-+					 pmlmepriv->num_sta_no_ht);
-+			}
-+		}
-+
-+		if (rtw_ht_operation_update(padapter) > 0) {
-+			update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0);
-+			update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE, 0);
-+			beacon_updated = _TRUE;
-+		}
-+	}
-+#endif /* CONFIG_80211N_HT */
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(padapter)) {
-+		struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+		update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE, 0);
-+		if (pstapriv->asoc_list_cnt == 1)
-+			_set_timer(&padapter->mesh_atlm_param_req_timer, 0);
-+		beacon_updated = _TRUE;
-+	}
-+#endif
-+
-+	if (beacon_updated)
-+		update_beacon(padapter, 0xFF, NULL, _TRUE, 0);
-+
-+	/* update associcated stations cap. */
-+	associated_clients_update(padapter,  beacon_updated, STA_INFO_UPDATE_ALL);
-+
-+	RTW_INFO("%s, updated=%d\n", __func__, beacon_updated);
-+
-+}
-+
-+u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta)
-+{
-+	u8 beacon_updated = _FALSE;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+
-+	if (!psta)
-+		return beacon_updated;
-+
-+	if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {
-+		rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
-+		beacon_updated = _TRUE;
-+		update_beacon(padapter, _TIM_IE_, NULL, _FALSE, 0);
-+	}
-+
-+	if (psta->no_short_preamble_set) {
-+		psta->no_short_preamble_set = 0;
-+		pmlmepriv->num_sta_no_short_preamble--;
-+		if (pmlmeext->cur_wireless_mode > WIRELESS_11B
-+		    && pmlmepriv->num_sta_no_short_preamble == 0)
-+			beacon_updated = _TRUE;
-+	}
-+
-+	if (psta->nonerp_set) {
-+		psta->nonerp_set = 0;
-+		pmlmepriv->num_sta_non_erp--;
-+		if (pmlmepriv->num_sta_non_erp == 0) {
-+			beacon_updated = _TRUE;
-+			update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE, 0);
-+		}
-+	}
-+
-+	if (psta->no_short_slot_time_set) {
-+		psta->no_short_slot_time_set = 0;
-+		pmlmepriv->num_sta_no_short_slot_time--;
-+		if (pmlmeext->cur_wireless_mode > WIRELESS_11B
-+		    && pmlmepriv->num_sta_no_short_slot_time == 0)
-+			beacon_updated = _TRUE;
-+	}
-+
-+#ifdef CONFIG_80211N_HT
-+	if (psta->no_ht_gf_set) {
-+		psta->no_ht_gf_set = 0;
-+		pmlmepriv->num_sta_ht_no_gf--;
-+	}
-+
-+	if (psta->no_ht_set) {
-+		psta->no_ht_set = 0;
-+		pmlmepriv->num_sta_no_ht--;
-+	}
-+
-+	if (psta->ht_20mhz_set) {
-+		psta->ht_20mhz_set = 0;
-+		pmlmepriv->num_sta_ht_20mhz--;
-+	}
-+
-+	if (psta->ht_40mhz_intolerant) {
-+		psta->ht_40mhz_intolerant = 0;
-+		if (pmlmepriv->num_sta_40mhz_intolerant > 0)
-+			pmlmepriv->num_sta_40mhz_intolerant--;
-+		else
-+			rtw_warn_on(1);
-+	}
-+
-+	if (rtw_ht_operation_update(padapter) > 0) {
-+		update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0);
-+		update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE, 0);
-+	}
-+#endif /* CONFIG_80211N_HT */
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(padapter)) {
-+		update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE, 0);
-+		if (pstapriv->asoc_list_cnt == 0)
-+			_cancel_timer_ex(&padapter->mesh_atlm_param_req_timer);
-+		beacon_updated = _TRUE;
-+	}
-+#endif
-+
-+	if (beacon_updated == _TRUE)
-+		update_beacon(padapter, 0xFF, NULL, _TRUE, 0);
-+
-+#if 0
-+	/* update associated stations cap. */
-+	associated_clients_update(padapter,  beacon_updated, STA_INFO_UPDATE_ALL); /* move it to avoid deadlock */
-+#endif
-+
-+	RTW_INFO("%s, updated=%d\n", __func__, beacon_updated);
-+
-+	return beacon_updated;
-+
-+}
-+
-+u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue)
-+{
-+	_irqL irqL;
-+	u8 beacon_updated = _FALSE;
-+
-+	if (!psta)
-+		return beacon_updated;
-+
-+	if (active == _TRUE) {
-+#ifdef CONFIG_80211N_HT
-+		/* tear down Rx AMPDU */
-+		send_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */
-+
-+		/* tear down TX AMPDU */
-+		send_delba(padapter, 1, psta->cmn.mac_addr);/*  */ /* originator */
-+
-+#endif /* CONFIG_80211N_HT */
-+
-+		if (!MLME_IS_MESH(padapter))
-+			issue_deauth(padapter, psta->cmn.mac_addr, reason);
-+	}
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(padapter))
-+		rtw_mesh_path_flush_by_nexthop(psta);
-+#endif
-+
-+#ifdef CONFIG_BEAMFORMING
-+	beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, psta->cmn.mac_addr, ETH_ALEN, 1);
-+#endif
-+
-+#ifdef CONFIG_80211N_HT
-+	psta->htpriv.agg_enable_bitmap = 0x0;/* reset */
-+	psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */
-+#endif
-+
-+
-+
-+	_enter_critical_bh(&psta->lock, &irqL);
-+	psta->state &= ~(WIFI_ASOC_STATE | WIFI_UNDER_KEY_HANDSHAKE);
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if ((psta->auth_len != 0) && (psta->pauth_frame != NULL)) {
-+		rtw_mfree(psta->pauth_frame, psta->auth_len);
-+		psta->pauth_frame = NULL;
-+		psta->auth_len = 0;
-+	}
-+	if (psta->passoc_req && psta->assoc_req_len > 0) {
-+		rtw_mfree(psta->passoc_req , psta->assoc_req_len);
-+		psta->passoc_req = NULL;
-+		psta->assoc_req_len = 0;
-+	}
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+	_exit_critical_bh(&psta->lock, &irqL);
-+
-+	if (!MLME_IS_MESH(padapter)) {
-+		#ifdef CONFIG_RTW_WDS
-+		rtw_wds_path_flush_by_nexthop(psta);
-+		#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+		#ifdef COMPAT_KERNEL_RELEASE
-+		rtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason);
-+		#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
-+		rtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason);
-+		#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */
-+		/* will call rtw_cfg80211_indicate_sta_disassoc() in cmd_thread for old API context */
-+		#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */
-+#else
-+		rtw_indicate_sta_disassoc_event(padapter, psta);
-+#endif
-+	}
-+
-+	beacon_updated = bss_cap_update_on_sta_leave(padapter, psta);
-+
-+	report_del_sta_event(padapter, psta->cmn.mac_addr, reason, enqueue, _FALSE);
-+	
-+	/* clear cam entry / key */
-+	rtw_clearstakey_cmd(padapter, psta, enqueue);
-+	
-+	return beacon_updated;
-+
-+}
-+
-+int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset)
-+{
-+	_irqL irqL;
-+	_list	*phead, *plist;
-+	int ret = 0;
-+	struct sta_info *psta = NULL;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+
-+	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
-+		return ret;
-+
-+	RTW_INFO(FUNC_NDEV_FMT" with ch:%u, offset:%u\n",
-+		 FUNC_NDEV_ARG(padapter->pnetdev), new_ch, ch_offset);
-+
-+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+	phead = &pstapriv->asoc_list;
-+	plist = get_next(phead);
-+
-+	/* for each sta in asoc_queue */
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+		plist = get_next(plist);
-+
-+		issue_action_spct_ch_switch(padapter, psta->cmn.mac_addr, new_ch, ch_offset);
-+		psta->expire_to = ((pstapriv->expire_to * 2) > 5) ? 5 : (pstapriv->expire_to * 2);
-+	}
-+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+	issue_action_spct_ch_switch(padapter, bc_addr, new_ch, ch_offset);
-+
-+	return ret;
-+}
-+
-+int rtw_sta_flush(_adapter *padapter, bool enqueue)
-+{
-+	_irqL irqL;
-+	_list	*phead, *plist;
-+	int ret = 0;
-+	struct sta_info *psta = NULL;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	u8 flush_num = 0;
-+	char flush_list[NUM_STA];
-+	int i;
-+
-+	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
-+		return ret;
-+
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev));
-+
-+	/* pick sta from sta asoc_queue */
-+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+	phead = &pstapriv->asoc_list;
-+	plist = get_next(phead);
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+		int stainfo_offset;
-+
-+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+		plist = get_next(plist);
-+
-+		rtw_list_delete(&psta->asoc_list);
-+		pstapriv->asoc_list_cnt--;
-+		#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+		if (psta->tbtx_enable)
-+			pstapriv->tbtx_asoc_list_cnt--;
-+		#endif
-+		STA_SET_MESH_PLINK(psta, NULL);
-+
-+		stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
-+		if (stainfo_offset_valid(stainfo_offset))
-+			flush_list[flush_num++] = stainfo_offset;
-+		else
-+			rtw_warn_on(1);
-+	}
-+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+	/* call ap_free_sta() for each sta picked */
-+	for (i = 0; i < flush_num; i++) {
-+		u8 sta_addr[ETH_ALEN];
-+
-+		psta = rtw_get_stainfo_by_offset(pstapriv, flush_list[i]);
-+		_rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN);
-+
-+		ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, enqueue);
-+		#ifdef CONFIG_RTW_MESH
-+		if (MLME_IS_MESH(padapter))
-+			rtw_mesh_expire_peer(padapter, sta_addr);
-+		#endif
-+	}
-+
-+	if (!MLME_IS_MESH(padapter))
-+		issue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING);
-+
-+	associated_clients_update(padapter, _TRUE, STA_INFO_UPDATE_ALL);
-+
-+	return ret;
-+}
-+
-+/* called > TSR LEVEL for USB or SDIO Interface*/
-+void sta_info_update(_adapter *padapter, struct sta_info *psta)
-+{
-+	int flags = psta->flags;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+
-+	/* update wmm cap. */
-+	if (WLAN_STA_WME & flags)
-+		psta->qos_option = 1;
-+	else
-+		psta->qos_option = 0;
-+
-+	if (pmlmepriv->qospriv.qos_option == 0)
-+		psta->qos_option = 0;
-+
-+
-+#ifdef CONFIG_80211N_HT
-+	/* update 802.11n ht cap. */
-+	if (WLAN_STA_HT & flags) {
-+		psta->htpriv.ht_option = _TRUE;
-+		psta->qos_option = 1;
-+
-+		psta->htpriv.smps_cap = (psta->htpriv.ht_cap.cap_info & IEEE80211_HT_CAP_SM_PS) >> 2;
-+	} else
-+		psta->htpriv.ht_option = _FALSE;
-+
-+	if (pmlmepriv->htpriv.ht_option == _FALSE)
-+		psta->htpriv.ht_option = _FALSE;
-+#endif
-+
-+#ifdef CONFIG_80211AC_VHT
-+	/* update 802.11AC vht cap. */
-+	if (WLAN_STA_VHT & flags)
-+		psta->vhtpriv.vht_option = _TRUE;
-+	else
-+		psta->vhtpriv.vht_option = _FALSE;
-+
-+	if (pmlmepriv->vhtpriv.vht_option == _FALSE)
-+		psta->vhtpriv.vht_option = _FALSE;
-+#endif
-+
-+	update_sta_info_apmode(padapter, psta);
-+}
-+
-+/* called >= TSR LEVEL for USB or SDIO Interface*/
-+void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta)
-+{
-+	if (psta->state & WIFI_ASOC_STATE)
-+		rtw_hal_update_ra_mask(psta); /* DM_RATR_STA_INIT */
-+}
-+/* restore hw setting from sw data structures */
-+void rtw_ap_restore_network(_adapter *padapter)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *psta;
-+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
-+	_irqL irqL;
-+	_list	*phead, *plist;
-+	u8 chk_alive_num = 0;
-+	char chk_alive_list[NUM_STA];
-+	int i;
-+
-+	rtw_setopmode_cmd(padapter
-+		, MLME_IS_AP(padapter) ? Ndis802_11APMode : Ndis802_11_mesh
-+		, RTW_CMDF_DIRECTLY
-+	);
-+
-+	set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
-+
-+	rtw_startbss_cmd(padapter, RTW_CMDF_DIRECTLY);
-+
-+	if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
-+	    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {
-+		/* restore group key, WEP keys is restored in ips_leave() */
-+		rtw_set_key(padapter, psecuritypriv, psecuritypriv->dot118021XGrpKeyid, 0, _FALSE);
-+	}
-+
-+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+	phead = &pstapriv->asoc_list;
-+	plist = get_next(phead);
-+
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+		int stainfo_offset;
-+
-+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+		plist = get_next(plist);
-+
-+		stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
-+		if (stainfo_offset_valid(stainfo_offset))
-+			chk_alive_list[chk_alive_num++] = stainfo_offset;
-+	}
-+
-+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+	for (i = 0; i < chk_alive_num; i++) {
-+		psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);
-+
-+		if (psta == NULL)
-+			RTW_INFO(FUNC_ADPT_FMT" sta_info is null\n", FUNC_ADPT_ARG(padapter));
-+		else if (psta->state & WIFI_ASOC_STATE) {
-+			rtw_sta_media_status_rpt(padapter, psta, 1);
-+			Update_RA_Entry(padapter, psta);
-+			/* pairwise key */
-+			/* per sta pairwise key and settings */
-+			if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
-+			    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_))
-+				rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE);
-+		}
-+	}
-+
-+}
-+
-+void start_ap_mode(_adapter *padapter)
-+{
-+	int i;
-+	struct sta_info *psta = NULL;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+
-+	pmlmepriv->update_bcn = _FALSE;
-+
-+	/*init_mlme_ap_info(padapter);*/
-+
-+	pmlmeext->bstart_bss = _FALSE;
-+
-+	pmlmepriv->num_sta_non_erp = 0;
-+
-+	pmlmepriv->num_sta_no_short_slot_time = 0;
-+
-+	pmlmepriv->num_sta_no_short_preamble = 0;
-+
-+	pmlmepriv->num_sta_ht_no_gf = 0;
-+#ifdef CONFIG_80211N_HT
-+	pmlmepriv->num_sta_no_ht = 0;
-+#endif /* CONFIG_80211N_HT */
-+	pmlmeinfo->HT_info_enable = 0;
-+	pmlmeinfo->HT_caps_enable = 0;
-+	pmlmeinfo->HT_enable = 0;
-+
-+	pmlmepriv->num_sta_ht_20mhz = 0;
-+	pmlmepriv->num_sta_40mhz_intolerant = 0;
-+	ATOMIC_SET(&pmlmepriv->olbc, _FALSE);
-+	ATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE);
-+
-+#ifdef CONFIG_80211N_HT
-+	pmlmepriv->ht_20mhz_width_req = _FALSE;
-+	pmlmepriv->ht_intolerant_ch_reported = _FALSE;
-+	pmlmepriv->ht_op_mode = 0;
-+	pmlmepriv->sw_to_20mhz = 0;
-+#endif
-+
-+	_rtw_memset(pmlmepriv->ext_capab_ie_data, 0, sizeof(pmlmepriv->ext_capab_ie_data));
-+	pmlmepriv->ext_capab_ie_len = 0;
-+
-+	psecuritypriv->dot118021x_bmc_cam_id = INVALID_SEC_MAC_CAM_ID;
-+
-+	for (i = 0 ;  i < pstapriv->max_aid; i++)
-+		pstapriv->sta_aid[i] = NULL;
-+
-+#ifdef CONFIG_RTW_WDS
-+	if (MLME_IS_AP(padapter))
-+		rtw_wds_pathtbl_init(padapter);
-+#endif
-+
-+	psta = rtw_get_bcmc_stainfo(padapter);
-+	/*_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/
-+	if (psta)
-+		rtw_free_stainfo(padapter, psta);
-+	/*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/
-+
-+	rtw_init_bcmc_stainfo(padapter);
-+
-+	if (rtw_mi_get_ap_num(padapter))
-+		RTW_SET_SCAN_BAND_SKIP(padapter, BAND_5G);
-+
-+}
-+
-+void stop_ap_mode(_adapter *padapter)
-+{
-+	u8 self_action = MLME_ACTION_UNKNOWN;
-+	struct sta_info *psta = NULL;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+#ifdef CONFIG_SUPPORT_MULTI_BCN
-+	struct dvobj_priv *pdvobj = padapter->dvobj;
-+	_irqL irqL;
-+#endif
-+
-+	RTW_INFO("%s -"ADPT_FMT"\n", __func__, ADPT_ARG(padapter));
-+
-+	if (MLME_IS_AP(padapter))
-+		self_action = MLME_AP_STOPPED;
-+	else if (MLME_IS_MESH(padapter))
-+		self_action = MLME_MESH_STOPPED;
-+	else
-+		rtw_warn_on(1);
-+
-+	pmlmepriv->update_bcn = _FALSE;
-+	/*pmlmeext->bstart_bss = _FALSE;*/
-+	padapter->netif_up = _FALSE;
-+	/* _rtw_spinlock_free(&pmlmepriv->bcn_update_lock); */
-+
-+	/* reset and init security priv , this can refine with rtw_reset_securitypriv */
-+	_rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof(struct security_priv));
-+	padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
-+	padapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled;
-+
-+#ifdef CONFIG_DFS_MASTER
-+	rtw_dfs_rd_en_decision(padapter, self_action, 0);
-+#endif
-+
-+	rtw_rfctl_update_op_mode(adapter_to_rfctl(padapter), BIT(padapter->iface_id), 0);
-+
-+	/* free scan queue */
-+	rtw_free_network_queue(padapter, _TRUE);
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+	rtw_macaddr_acl_clear(padapter, RTW_ACL_PERIOD_BSS);
-+#endif
-+
-+	rtw_sta_flush(padapter, _TRUE);
-+
-+	/* free_assoc_sta_resources	 */
-+	rtw_free_all_stainfo(padapter);
-+
-+	psta = rtw_get_bcmc_stainfo(padapter);
-+	if (psta) {
-+		rtw_sta_mstatus_disc_rpt(padapter, psta->cmn.mac_id);
-+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
-+		rtw_free_stainfo(padapter, psta);
-+		/*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/
-+	}
-+
-+	pmlmepriv->ap_isolate = 0;
-+#ifdef CONFIG_RTW_WDS
-+	adapter_set_use_wds(padapter, 0);
-+#endif
-+#ifdef CONFIG_RTW_MULTI_AP
-+	padapter->multi_ap = 0;
-+#endif
-+	rtw_free_mlme_priv_ie_data(pmlmepriv);
-+
-+#ifdef CONFIG_SUPPORT_MULTI_BCN
-+	if (pmlmeext->bstart_bss == _TRUE) {
-+		#ifdef CONFIG_FW_HANDLE_TXBCN
-+		u8 free_apid = CONFIG_LIMITED_AP_NUM;
-+		#endif
-+
-+		_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
-+		pdvobj->nr_ap_if--;
-+		if (pdvobj->nr_ap_if > 0)
-+			pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL / pdvobj->nr_ap_if;
-+		else
-+			pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL;
-+		#ifdef CONFIG_FW_HANDLE_TXBCN
-+		rtw_ap_release_vapid(pdvobj, padapter->vap_id);
-+		free_apid = padapter->vap_id;
-+		padapter->vap_id = CONFIG_LIMITED_AP_NUM;
-+		#endif
-+		rtw_list_delete(&padapter->list);
-+		_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
-+		#ifdef CONFIG_FW_HANDLE_TXBCN
-+		rtw_ap_mbid_bcn_dis(padapter, free_apid);
-+		#endif
-+
-+		#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+		rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pdvobj->inter_bcn_space));
-+
-+		if (pdvobj->nr_ap_if == 0)
-+			_cancel_timer_ex(&pdvobj->txbcn_timer);
-+		#endif
-+	}
-+#endif
-+
-+	pmlmeext->bstart_bss = _FALSE;
-+
-+	rtw_hal_rcr_set_chk_bssid(padapter, self_action);
-+
-+#ifdef CONFIG_HW_P0_TSF_SYNC
-+	correct_TSF(padapter, self_action);
-+#endif
-+
-+#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_MediaStatusNotify(padapter, 0); /* disconnect */
-+#endif
-+
-+#ifdef CONFIG_RTW_WDS
-+	if (MLME_IS_AP(padapter))
-+		rtw_wds_pathtbl_unregister(padapter);
-+#endif
-+}
-+
-+#endif /* CONFIG_NATIVEAP_MLME */
-+
-+void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset)
-+{
-+#define UPDATE_VHT_CAP 1
-+#define UPDATE_HT_CAP 1
-+#ifdef CONFIG_80211AC_VHT
-+	struct vht_priv *vhtpriv = &adapter->mlmepriv.vhtpriv;
-+#endif
-+	{
-+		u8 *p;
-+		int ie_len;
-+		u8 old_ch = bss->Configuration.DSConfig;
-+		bool change_band = _FALSE;
-+
-+		if ((ch <= 14 && old_ch >= 36) || (ch >= 36 && old_ch <= 14))
-+			change_band = _TRUE;
-+
-+		/* update channel in IE */
-+		p = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
-+		if (p && ie_len > 0)
-+			*(p + 2) = ch;
-+
-+		bss->Configuration.DSConfig = ch;
-+
-+		/* band is changed, update ERP, support rate, ext support rate IE */
-+		if (change_band == _TRUE)
-+			change_band_update_ie(adapter, bss, ch);
-+	}
-+
-+#ifdef CONFIG_80211AC_VHT
-+	if (vhtpriv->vht_option == _TRUE) {
-+		u8 *vht_cap_ie, *vht_op_ie;
-+		int vht_cap_ielen, vht_op_ielen;
-+		u8	center_freq;
-+
-+		vht_cap_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_VHTCapability, &vht_cap_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
-+		vht_op_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_VHTOperation, &vht_op_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
-+		center_freq = rtw_get_center_ch(ch, bw, offset);
-+
-+		/* update vht cap ie */
-+		if (vht_cap_ie && vht_cap_ielen) {
-+			#if UPDATE_VHT_CAP
-+			/* if ((bw == CHANNEL_WIDTH_160 || bw == CHANNEL_WIDTH_80_80) && pvhtpriv->sgi_160m)
-+				SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvht_cap_ie + 2, 1);
-+			else */
-+				SET_VHT_CAPABILITY_ELE_SHORT_GI160M(vht_cap_ie + 2, 0);
-+
-+			if (bw >= CHANNEL_WIDTH_80 && vhtpriv->sgi_80m)
-+				SET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 1);
-+			else
-+				SET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 0);
-+			#endif
-+		}
-+
-+		/* update vht op ie */
-+		if (vht_op_ie && vht_op_ielen) {
-+			if (bw < CHANNEL_WIDTH_80) {
-+				SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0);
-+				SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0);
-+				SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);
-+			} else if (bw == CHANNEL_WIDTH_80) {
-+				SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 1);
-+				SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, center_freq);
-+				SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);
-+			} else {
-+				RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(adapter), bw);
-+				rtw_warn_on(1);
-+			}
-+		}
-+	}
-+#endif /* CONFIG_80211AC_VHT */
-+#ifdef CONFIG_80211N_HT
-+	{
-+		struct ht_priv	*htpriv = &adapter->mlmepriv.htpriv;
-+		u8 *ht_cap_ie, *ht_op_ie;
-+		int ht_cap_ielen, ht_op_ielen;
-+
-+		ht_cap_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_HTCapability, &ht_cap_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
-+		ht_op_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_HTInfo, &ht_op_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
-+
-+		/* update ht cap ie */
-+		if (ht_cap_ie && ht_cap_ielen) {
-+			#if UPDATE_HT_CAP
-+			if (bw >= CHANNEL_WIDTH_40)
-+				SET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2, 1);
-+			else
-+				SET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2, 0);
-+
-+			if (bw >= CHANNEL_WIDTH_40 && htpriv->sgi_40m)
-+				SET_HT_CAP_ELE_SHORT_GI40M(ht_cap_ie + 2, 1);
-+			else
-+				SET_HT_CAP_ELE_SHORT_GI40M(ht_cap_ie + 2, 0);
-+
-+			if (htpriv->sgi_20m)
-+				SET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 1);
-+			else
-+				SET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 0);
-+			#endif
-+		}
-+
-+		/* update ht op ie */
-+		if (ht_op_ie && ht_op_ielen) {
-+			SET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2, ch);
-+			switch (offset) {
-+			case HAL_PRIME_CHNL_OFFSET_LOWER:
-+				SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCA);
-+				break;
-+			case HAL_PRIME_CHNL_OFFSET_UPPER:
-+				SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCB);
-+				break;
-+			case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
-+			default:
-+				SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCN);
-+				break;
-+			}
-+
-+			if (bw >= CHANNEL_WIDTH_40)
-+				SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2, 1);
-+			else
-+				SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2, 0);
-+		}
-+	}
-+#endif /* CONFIG_80211N_HT */
-+}
-+
-+static u8 rtw_ap_update_chbw_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp
-+	, u8 cur_ie_ch[], u8 cur_ie_bw[], u8 cur_ie_offset[]
-+	, u8 dec_ch[], u8 dec_bw[], u8 dec_offset[]
-+	, const char *caller)
-+{
-+	_adapter *iface;
-+	struct mlme_ext_priv *mlmeext;
-+	WLAN_BSSID_EX *network;
-+	u8 ifbmp_ch_changed = 0;
-+	int i;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
-+			continue;
-+
-+		iface = dvobj->padapters[i];
-+		mlmeext = &(iface->mlmeextpriv);
-+
-+		if (MLME_IS_ASOC(iface)) {
-+			RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u%s\n", caller, ADPT_ARG(iface)
-+				, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset
-+				, dec_ch[i], dec_bw[i], dec_offset[i]
-+				, MLME_IS_OPCH_SW(iface) ? " OPCH_SW" : "");
-+		} else {
-+			RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u%s\n", caller, ADPT_ARG(iface)
-+				, cur_ie_ch[i], cur_ie_bw[i], cur_ie_offset[i]
-+				, dec_ch[i], dec_bw[i], dec_offset[i]
-+				, MLME_IS_OPCH_SW(iface) ? " OPCH_SW" : "");
-+		}
-+	}
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
-+			continue;
-+
-+		iface = dvobj->padapters[i];
-+		mlmeext = &(iface->mlmeextpriv);
-+		network = &(mlmeext->mlmext_info.network);
-+
-+		/* ch setting differs from mlmeext.network IE */
-+		if (cur_ie_ch[i] != dec_ch[i]
-+			|| cur_ie_bw[i] != dec_bw[i]
-+			|| cur_ie_offset[i] != dec_offset[i])
-+			ifbmp_ch_changed |= BIT(i);
-+
-+		/* ch setting differs from existing one */
-+		if (MLME_IS_ASOC(iface)
-+			&& (mlmeext->cur_channel != dec_ch[i]
-+				|| mlmeext->cur_bwmode != dec_bw[i]
-+				|| mlmeext->cur_ch_offset != dec_offset[i])
-+		) {
-+			if (rtw_linked_check(iface) == _TRUE) {
-+				#ifdef CONFIG_SPCT_CH_SWITCH
-+				if (1)
-+					rtw_ap_inform_ch_switch(iface, dec_ch[i], dec_offset[i]);
-+				else
-+				#endif
-+					rtw_sta_flush(iface, _FALSE);
-+			}
-+		}
-+
-+		mlmeext->cur_channel = dec_ch[i];
-+		mlmeext->cur_bwmode = dec_bw[i];
-+		mlmeext->cur_ch_offset = dec_offset[i];
-+
-+		rtw_ap_update_bss_chbw(iface, network, dec_ch[i], dec_bw[i], dec_offset[i]);
-+	}
-+
-+	return ifbmp_ch_changed;
-+}
-+
-+static u8 rtw_ap_ch_specific_chk(_adapter *adapter, u8 ch, u8 *bw, u8 *offset, const char *caller)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	RT_CHANNEL_INFO *chset = rfctl->channel_set;
-+	int ch_idx;
-+	u8 ret = _SUCCESS;
-+
-+	ch_idx = rtw_chset_search_ch(chset, ch);
-+	if (ch_idx < 0) {
-+		RTW_WARN("%s ch:%u doesn't fit in chplan\n", caller, ch);
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+	if (chset[ch_idx].flags & RTW_CHF_NO_IR) {
-+		RTW_WARN("%s ch:%u is passive\n", caller, ch);
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	rtw_adjust_chbw(adapter, ch, bw, offset);
-+
-+	if (!rtw_get_offset_by_chbw(ch, *bw, offset)) {
-+		RTW_WARN("%s %u,%u has no valid offset\n", caller, ch, *bw);
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	while (!rtw_chset_is_chbw_valid(chset, ch, *bw, *offset, 0, 0)
-+		|| (rtw_rfctl_dfs_domain_unknown(rfctl) && rtw_chset_is_dfs_chbw(chset, ch, *bw, *offset))
-+	) {
-+		if (*bw > CHANNEL_WIDTH_20)
-+			(*bw)--;
-+		if (*bw == CHANNEL_WIDTH_20) {
-+			*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+			break;
-+		}
-+	}
-+
-+	if (rtw_rfctl_dfs_domain_unknown(rfctl) && rtw_chset_is_dfs_chbw(chset, ch, *bw, *offset)) {
-+		RTW_WARN("%s DFS channel %u can't be used\n", caller, ch);
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+static bool rtw_ap_choose_chbw(_adapter *adapter, u8 sel_ch, u8 max_bw, u8 cur_ch
-+	, u8 *ch, u8 *bw, u8 *offset, bool by_int_info, u8 mesh_only, const char *caller)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	bool ch_avail = _FALSE;
-+
-+#if defined(CONFIG_DFS_MASTER)
-+	if (!rtw_rfctl_dfs_domain_unknown(rfctl)) {
-+		if (rfctl->radar_detected
-+			&& rfctl->dbg_dfs_choose_dfs_ch_first
-+		) {
-+			ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw
-+						, ch, bw, offset
-+						, RTW_CHF_DFS, 0
-+						, cur_ch, by_int_info, mesh_only);
-+			if (ch_avail == _TRUE) {
-+				RTW_INFO("%s choose 5G DFS channel for debug\n", caller);
-+				goto exit;
-+			}
-+		}
-+
-+		if (rfctl->radar_detected
-+			&& (rfctl->dfs_ch_sel_e_flags || rfctl->dfs_ch_sel_d_flags)
-+		) {
-+			ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw
-+						, ch, bw, offset
-+						, rfctl->dfs_ch_sel_e_flags, rfctl->dfs_ch_sel_d_flags
-+						, cur_ch, by_int_info, mesh_only);
-+			if (ch_avail == _TRUE) {
-+				RTW_INFO("%s choose with dfs_ch_sel_ e_flags:0x%02x d_flags:0x%02x for debug\n"
-+					, caller, rfctl->dfs_ch_sel_e_flags, rfctl->dfs_ch_sel_d_flags);
-+				goto exit;
-+			}
-+		}
-+
-+		ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw
-+					, ch, bw, offset
-+					, 0, 0
-+					, cur_ch, by_int_info, mesh_only);
-+	} else
-+#endif /* defined(CONFIG_DFS_MASTER) */
-+	{
-+		ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw
-+					, ch, bw, offset
-+					, 0, RTW_CHF_DFS
-+					, cur_ch, by_int_info, mesh_only);
-+	}
-+#if defined(CONFIG_DFS_MASTER)
-+exit:
-+#endif
-+	if (ch_avail == _FALSE)
-+		RTW_WARN("%s no available channel\n", caller);
-+
-+	return ch_avail;
-+}
-+
-+u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp
-+	, s16 req_ch, s8 req_bw, s8 req_offset
-+	, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow, bool *set_u_ch)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	RT_CHANNEL_INFO *chset = adapter_to_chset(adapter);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	bool ch_avail = _FALSE;
-+	u8 cur_ie_ch[CONFIG_IFACE_NUMBER] = {0};
-+	u8 cur_ie_bw[CONFIG_IFACE_NUMBER] = {0};
-+	u8 cur_ie_offset[CONFIG_IFACE_NUMBER] = {0};
-+	u8 dec_ch[CONFIG_IFACE_NUMBER] = {0};
-+	u8 dec_bw[CONFIG_IFACE_NUMBER] = {0};
-+	u8 dec_offset[CONFIG_IFACE_NUMBER] = {0};
-+	u8 u_ch = 0, u_bw = 0, u_offset = 0;
-+	struct mlme_ext_priv *mlmeext;
-+	WLAN_BSSID_EX *network;
-+	struct mi_state mstate;
-+	struct mi_state mstate_others;
-+	u8 ifbmp_others = 0xFF & ~ifbmp & ~excl_ifbmp;
-+	u8 ifbmp_ch_changed = 0;
-+	bool ifbmp_all_mesh = 0;
-+	_adapter *iface;
-+	int i;
-+
-+	*set_u_ch = _FALSE;
-+
-+#ifdef CONFIG_RTW_MESH
-+	for (i = 0; i < dvobj->iface_nums; i++)
-+		if ((ifbmp & BIT(i)) && dvobj->padapters)
-+			if (!MLME_IS_MESH(dvobj->padapters[i]))
-+				break;
-+	ifbmp_all_mesh = i >= dvobj->iface_nums ? 1 : 0;
-+#endif
-+
-+	RTW_INFO("%s ifbmp:0x%02x excl_ifbmp:0x%02x req:%d,%d,%d\n", __func__
-+		, ifbmp, excl_ifbmp, req_ch, req_bw, req_offset);
-+	rtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate);
-+	rtw_mi_status_by_ifbmp(dvobj, ifbmp_others, &mstate_others);
-+	RTW_INFO("%s others ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, mesh_num:%u\n"
-+		, __func__, MSTATE_STA_LD_NUM(&mstate_others), MSTATE_STA_LG_NUM(&mstate_others)
-+		, MSTATE_AP_NUM(&mstate_others), MSTATE_MESH_NUM(&mstate_others));
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
-+			continue;
-+		iface = dvobj->padapters[i];
-+		mlmeext = &(iface->mlmeextpriv);
-+		network = &(mlmeext->mlmext_info.network);
-+
-+		/* get current IE channel settings */
-+		rtw_ies_get_chbw(BSS_EX_TLV_IES(network), BSS_EX_TLV_IES_LEN(network)
-+			, &cur_ie_ch[i], &cur_ie_bw[i], &cur_ie_offset[i], 1, 1);
-+
-+		/* prepare temporary channel setting decision */
-+		if (req_ch == 0) {
-+			/* request comes from upper layer, use cur_ie values */
-+			dec_ch[i] = cur_ie_ch[i];
-+			dec_bw[i] = cur_ie_bw[i];
-+			dec_offset[i] = cur_ie_offset[i];
-+		} else {
-+			/* use chbw of cur_ie updated with specifying req as temporary decision */
-+			dec_ch[i] = (req_ch <= REQ_CH_NONE) ? cur_ie_ch[i] : req_ch;
-+			if (req_bw <= REQ_BW_NONE) {
-+				if (req_bw == REQ_BW_ORI)
-+					dec_bw[i] = iface->mlmepriv.ori_bw;
-+				else
-+					dec_bw[i] = cur_ie_bw[i];
-+			} else
-+				dec_bw[i] = req_bw;
-+			dec_offset[i] = (req_offset <= REQ_OFFSET_NONE) ? cur_ie_offset[i] : req_offset;
-+		}
-+	}
-+
-+	if (MSTATE_STA_LD_NUM(&mstate_others) || MSTATE_STA_LG_NUM(&mstate_others)
-+		|| MSTATE_AP_NUM(&mstate_others) || MSTATE_MESH_NUM(&mstate_others)
-+	) {
-+		/* has linked/linking STA or has AP/Mesh mode */
-+		rtw_warn_on(!rtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp_others, &u_ch, &u_bw, &u_offset));
-+		RTW_INFO("%s others union:%u,%u,%u\n", __func__, u_ch, u_bw, u_offset);
-+	}
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(adapter) && req_ch == 0) {
-+		if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
-+			u8 if_id = adapter->iface_id;
-+
-+			mlmeext = &(adapter->mlmeextpriv);
-+
-+			/* check channel settings are the same */
-+			if (cur_ie_ch[if_id] == mlmeext->cur_channel
-+				&& cur_ie_bw[if_id] == mlmeext->cur_bwmode
-+				&& cur_ie_offset[if_id] == mlmeext->cur_ch_offset) {
-+
-+				RTW_INFO(FUNC_ADPT_FMT"req ch settings are the same as current ch setting, go to exit\n"
-+					, FUNC_ADPT_ARG(adapter));
-+
-+				*chbw_allow = _FALSE;
-+				goto exit;
-+			} else {
-+				RTW_INFO(FUNC_ADPT_FMT"request channel settings are not the same as current channel setting(%d,%d,%d,%d,%d,%d), restart MCC\n"
-+					, FUNC_ADPT_ARG(adapter)
-+					, cur_ie_ch[if_id], cur_ie_bw[if_id], cur_ie_offset[if_id]
-+					, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
-+
-+				rtw_hal_set_mcc_setting_disconnect(adapter);
-+			}
-+		}	
-+	}
-+#endif /* CONFIG_MCC_MODE */
-+
-+	if (MSTATE_STA_LG_NUM(&mstate_others) && !MSTATE_STA_LD_NUM(&mstate_others)) {
-+		/* has linking STA but no linked STA */
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
-+				continue;
-+			iface = dvobj->padapters[i];
-+
-+			rtw_adjust_chbw(iface, dec_ch[i], &dec_bw[i], &dec_offset[i]);
-+			#ifdef CONFIG_RTW_MESH
-+			if (MLME_IS_MESH(iface))
-+				rtw_mesh_adjust_chbw(dec_ch[i], &dec_bw[i], &dec_offset[i]);
-+			#endif
-+
-+			if (rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch[i], dec_bw[i], dec_offset[i])) {
-+				rtw_chset_sync_chbw(chset
-+					, &dec_ch[i], &dec_bw[i], &dec_offset[i]
-+					, &u_ch, &u_bw, &u_offset, 1, 0);
-+				*set_u_ch = _TRUE;
-+
-+				/* channel bw offset can be allowed, not need MCC */
-+				*chbw_allow = _TRUE;
-+			} else {
-+				#ifdef CONFIG_MCC_MODE
-+				if (MCC_EN(iface)) {
-+					mlmeext = &(iface->mlmeextpriv);
-+					mlmeext->cur_channel = *ch = dec_ch[i];
-+					mlmeext->cur_bwmode = *bw = dec_bw[i];
-+					mlmeext->cur_ch_offset = *offset = dec_offset[i];
-+
-+					/* channel bw offset can not be allowed, need MCC */
-+					*chbw_allow = _FALSE;
-+					RTW_INFO(FUNC_ADPT_FMT" enable mcc: %u,%u,%u\n", FUNC_ADPT_ARG(iface)
-+						 , *ch, *bw, *offset);
-+					goto exit;
-+				}
-+				#endif /* CONFIG_MCC_MODE */
-+
-+				/* set this for possible ch change when join down*/
-+				set_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING);
-+			}
-+		}
-+
-+	} else if (MSTATE_STA_LD_NUM(&mstate_others)
-+		|| MSTATE_AP_NUM(&mstate_others) || MSTATE_MESH_NUM(&mstate_others)
-+	) {
-+		/* has linked STA mode or AP/Mesh mode */
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
-+				continue;
-+			iface = dvobj->padapters[i];
-+
-+			rtw_adjust_chbw(iface, u_ch, &dec_bw[i], &dec_offset[i]);
-+			#ifdef CONFIG_RTW_MESH
-+			if (MLME_IS_MESH(iface))
-+				rtw_mesh_adjust_chbw(u_ch, &dec_bw[i], &dec_offset[i]);
-+			#endif
-+
-+			#ifdef CONFIG_MCC_MODE
-+			if (MCC_EN(iface)) {
-+				if (!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch[i], dec_bw[i], dec_offset[i])) {
-+					mlmeext = &(iface->mlmeextpriv);
-+					mlmeext->cur_channel = *ch = dec_ch[i] = cur_ie_ch[i];
-+					mlmeext->cur_bwmode = *bw = dec_bw[i] = cur_ie_bw[i];
-+					mlmeext->cur_ch_offset = *offset = dec_offset[i] = cur_ie_offset[i];
-+					/* channel bw offset can not be allowed, need MCC */
-+					*chbw_allow = _FALSE;
-+					RTW_INFO(FUNC_ADPT_FMT" enable mcc: %u,%u,%u\n", FUNC_ADPT_ARG(iface)
-+						 , *ch, *bw, *offset);
-+					goto exit;
-+				} else
-+					/* channel bw offset can be allowed, not need MCC */
-+					*chbw_allow = _TRUE;
-+			}
-+			#endif /* CONFIG_MCC_MODE */
-+
-+			if (req_ch == 0 && dec_bw[i] > u_bw
-+				&& rtw_chset_is_dfs_chbw(chset, u_ch, u_bw, u_offset)
-+			) {
-+				/* request comes from upper layer, prevent from additional channel waiting */
-+				dec_bw[i] = u_bw;
-+				if (dec_bw[i] == CHANNEL_WIDTH_20)
-+					dec_offset[i] = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+			}
-+
-+			/* follow */
-+			rtw_chset_sync_chbw(chset
-+				, &dec_ch[i], &dec_bw[i], &dec_offset[i]
-+				, &u_ch, &u_bw, &u_offset, 1, 0);
-+		}
-+
-+		*set_u_ch = _TRUE;
-+
-+	} else {
-+		/* autonomous decision */
-+		u8 ori_ch = 0;
-+		u8 max_bw;
-+		bool by_int_info;
-+
-+		/* autonomous decision, not need MCC */
-+		*chbw_allow = _TRUE;
-+
-+		if (req_ch <= REQ_CH_NONE) /* channel is not specified */
-+			goto choose_chbw;
-+
-+		/* get tmp dec union of ifbmp */
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
-+				continue;
-+			if (u_ch == 0) {
-+				u_ch = dec_ch[i];
-+				u_bw = dec_bw[i];
-+				u_offset = dec_offset[i];
-+				rtw_adjust_chbw(adapter, u_ch, &u_bw, &u_offset);
-+				rtw_get_offset_by_chbw(u_ch, u_bw, &u_offset);
-+			} else {
-+				u8 tmp_ch = dec_ch[i];
-+				u8 tmp_bw = dec_bw[i];
-+				u8 tmp_offset = dec_offset[i];
-+				
-+				rtw_adjust_chbw(adapter, tmp_ch, &tmp_bw, &tmp_offset);
-+				rtw_get_offset_by_chbw(tmp_ch, tmp_bw, &tmp_offset);
-+
-+				rtw_warn_on(!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, tmp_ch, tmp_bw, tmp_offset));
-+				rtw_sync_chbw(&tmp_ch, &tmp_bw, &tmp_offset, &u_ch, &u_bw, &u_offset);
-+			}
-+		}
-+
-+		#ifdef CONFIG_RTW_MESH
-+		/* if ifbmp are all mesh, apply bw restriction */
-+		if (ifbmp_all_mesh)
-+			rtw_mesh_adjust_chbw(u_ch, &u_bw, &u_offset);
-+		#endif
-+
-+		RTW_INFO("%s ifbmp:0x%02x tmp union:%u,%u,%u\n", __func__, ifbmp, u_ch, u_bw, u_offset);
-+
-+		/* check if tmp dec union is usable */
-+		if (rtw_ap_ch_specific_chk(adapter, u_ch, &u_bw, &u_offset, __func__) == _FAIL) {
-+			/* channel can't be used */
-+			if (req_ch > 0) {
-+				/* specific channel and not from IE => don't change channel setting */
-+				goto exit;
-+			}
-+			goto choose_chbw;
-+		} else if (rtw_chset_is_chbw_non_ocp(chset, u_ch, u_bw, u_offset)) {
-+			RTW_WARN("%s DFS channel %u,%u under non ocp\n", __func__, u_ch, u_bw);
-+			if (req_ch > 0 && req_bw > REQ_BW_NONE) {
-+				/* change_chbw with specific channel and specific bw, goto update_bss_chbw directly */
-+				goto update_bss_chbw;
-+			}
-+		} else
-+			goto update_bss_chbw;
-+
-+choose_chbw:
-+		by_int_info = req_ch == REQ_CH_INT_INFO ? 1 : 0;
-+		req_ch = req_ch > 0 ? req_ch : 0;
-+		max_bw = req_bw > REQ_BW_NONE ? req_bw : CHANNEL_WIDTH_20;
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
-+				continue;
-+			iface = dvobj->padapters[i];
-+			mlmeext = &(iface->mlmeextpriv);
-+
-+			if (req_bw <= REQ_BW_NONE) {
-+				if (req_bw == REQ_BW_ORI) {
-+					if (max_bw < iface->mlmepriv.ori_bw)
-+						max_bw = iface->mlmepriv.ori_bw;
-+				} else {
-+					if (max_bw < cur_ie_bw[i])
-+						max_bw = cur_ie_bw[i];
-+				}
-+			}
-+
-+			if (MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate)) {
-+				if (ori_ch == 0)
-+					ori_ch = mlmeext->cur_channel;
-+				else if (ori_ch != mlmeext->cur_channel)
-+					rtw_warn_on(1);
-+			} else {
-+				if (ori_ch == 0)
-+					ori_ch = cur_ie_ch[i];
-+				else if (ori_ch != cur_ie_ch[i])
-+					rtw_warn_on(1);
-+			}
-+		}
-+
-+		ch_avail = rtw_ap_choose_chbw(adapter, req_ch, max_bw
-+			, ori_ch, &u_ch, &u_bw, &u_offset, by_int_info, ifbmp_all_mesh, __func__);
-+		if (ch_avail == _FALSE)
-+			goto exit;
-+
-+update_bss_chbw:
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
-+				continue;
-+			iface = dvobj->padapters[i];
-+
-+			dec_ch[i] = u_ch;
-+			if (dec_bw[i] > u_bw)
-+				dec_bw[i] = u_bw;
-+			if (dec_bw[i] == CHANNEL_WIDTH_20)
-+				dec_offset[i] = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+			else
-+				dec_offset[i] = u_offset;
-+
-+			#ifdef CONFIG_RTW_MESH
-+			if (MLME_IS_MESH(iface))
-+				rtw_mesh_adjust_chbw(dec_ch[i], &dec_bw[i], &dec_offset[i]);
-+			#endif
-+		}
-+
-+		*set_u_ch = _TRUE;
-+	}
-+
-+	ifbmp_ch_changed = rtw_ap_update_chbw_by_ifbmp(dvobj, ifbmp
-+							, cur_ie_ch, cur_ie_bw, cur_ie_offset
-+							, dec_ch, dec_bw, dec_offset
-+							, __func__);
-+
-+	if (u_ch != 0)
-+		RTW_INFO("%s union:%u,%u,%u\n", __func__, u_ch, u_bw, u_offset);
-+
-+	if (*set_u_ch == _TRUE) {
-+		rtw_mi_update_union_chan_inf(adapter, u_ch, u_offset, u_bw);
-+		*ch = u_ch;
-+		*bw = u_bw;
-+		*offset = u_offset;
-+	}
-+
-+	if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_SURVEY)) {
-+		/* scanning, leave ch setting to scan state machine */
-+		*set_u_ch = _FALSE;
-+	}
-+
-+exit:
-+	return ifbmp_ch_changed;
-+}
-+
-+u8 rtw_ap_sta_states_check(_adapter *adapter)
-+{
-+	struct sta_info *psta;
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+	_list *plist, *phead;
-+	_irqL irqL;
-+	u8 rst = _FALSE;
-+
-+	if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter))
-+		return _FALSE;
-+
-+	if (pstapriv->auth_list_cnt !=0)
-+		return _TRUE;
-+
-+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+	phead = &pstapriv->asoc_list;
-+	plist = get_next(phead);
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+
-+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+		plist = get_next(plist);
-+
-+		if (!(psta->state & WIFI_ASOC_STATE)) {
-+			RTW_INFO(ADPT_FMT"- SoftAP/Mesh - sta under linking, its state = 0x%x\n", ADPT_ARG(adapter), psta->state);
-+			rst = _TRUE;
-+			break;
-+		} else if (psta->state & WIFI_UNDER_KEY_HANDSHAKE) {
-+			RTW_INFO(ADPT_FMT"- SoftAP/Mesh - sta under key handshaking, its state = 0x%x\n", ADPT_ARG(adapter), psta->state);
-+			rst = _TRUE;
-+			break;
-+		}
-+	}
-+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+	return rst;
-+}
-+
-+/*#define DBG_SWTIMER_BASED_TXBCN*/
-+#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+void tx_beacon_handlder(struct dvobj_priv *pdvobj)
-+{
-+#define BEACON_EARLY_TIME		20	/* unit:TU*/
-+	_irqL irqL;
-+	_list	*plist, *phead;
-+	u32 timestamp[2];
-+	u32 bcn_interval_us; /* unit : usec */
-+	u64 time;
-+	u32 cur_tick, time_offset; /* unit : usec */
-+	u32 inter_bcn_space_us; /* unit : usec */
-+	u32 txbcn_timer_ms; /* unit : ms */
-+	int nr_vap, idx, bcn_idx;
-+	int i;
-+	u8 val8, late = 0;
-+	_adapter *padapter = NULL;
-+
-+	i = 0;
-+
-+	/* get first ap mode interface */
-+	_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
-+	if (rtw_is_list_empty(&pdvobj->ap_if_q.queue) || (pdvobj->nr_ap_if == 0)) {
-+		RTW_INFO("[%s] ERROR: ap_if_q is empty!or nr_ap = %d\n", __func__, pdvobj->nr_ap_if);
-+		_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
-+		return;
-+	} else
-+		padapter = LIST_CONTAINOR(get_next(&(pdvobj->ap_if_q.queue)), struct _ADAPTER, list);
-+	_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
-+
-+	if (NULL == padapter) {
-+		RTW_INFO("[%s] ERROR: no any ap interface!\n", __func__);
-+		return;
-+	}
-+
-+
-+	bcn_interval_us = DEFAULT_BCN_INTERVAL * NET80211_TU_TO_US;
-+	if (0 == bcn_interval_us) {
-+		RTW_INFO("[%s] ERROR: beacon interval = 0\n", __func__);
-+		return;
-+	}
-+
-+	/* read TSF */
-+	timestamp[1] = rtw_read32(padapter, 0x560 + 4);
-+	timestamp[0] = rtw_read32(padapter, 0x560);
-+	while (timestamp[1]) {
-+		time = (0xFFFFFFFF % bcn_interval_us + 1) * timestamp[1] + timestamp[0];
-+		timestamp[0] = (u32)time;
-+		timestamp[1] = (u32)(time >> 32);
-+	}
-+	cur_tick = timestamp[0] % bcn_interval_us;
-+
-+
-+	_enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
-+
-+	nr_vap = (pdvobj->nr_ap_if - 1);
-+	if (nr_vap > 0) {
-+		inter_bcn_space_us = pdvobj->inter_bcn_space * NET80211_TU_TO_US; /* beacon_interval / (nr_vap+1); */
-+		idx = cur_tick / inter_bcn_space_us;
-+		if (idx < nr_vap)	/* if (idx < (nr_vap+1))*/
-+			bcn_idx = idx + 1;	/* bcn_idx = (idx + 1) % (nr_vap+1);*/
-+		else
-+			bcn_idx = 0;
-+
-+		/* to get padapter based on bcn_idx */
-+		padapter = NULL;
-+		phead = get_list_head(&pdvobj->ap_if_q);
-+		plist = get_next(phead);
-+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+			padapter = LIST_CONTAINOR(plist, struct _ADAPTER, list);
-+
-+			plist = get_next(plist);
-+
-+			if (i == bcn_idx)
-+				break;
-+
-+			i++;
-+		}
-+		if ((NULL == padapter) || (i > pdvobj->nr_ap_if)) {
-+			RTW_INFO("[%s] ERROR: nr_ap_if = %d, padapter=%p, bcn_idx=%d, index=%d\n",
-+				__func__, pdvobj->nr_ap_if, padapter, bcn_idx, i);
-+			_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
-+			return;
-+		}
-+#ifdef DBG_SWTIMER_BASED_TXBCN
-+		RTW_INFO("BCN_IDX=%d, cur_tick=%d, padapter=%p\n", bcn_idx, cur_tick, padapter);
-+#endif
-+		if (((idx + 2 == nr_vap + 1) && (idx < nr_vap + 1)) || (0 == bcn_idx)) {
-+			time_offset = bcn_interval_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US;
-+			if ((s32)time_offset < 0)
-+				time_offset += inter_bcn_space_us;
-+
-+		} else {
-+			time_offset = (idx + 2) * inter_bcn_space_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US;
-+			if (time_offset > (inter_bcn_space_us + (inter_bcn_space_us >> 1))) {
-+				time_offset -= inter_bcn_space_us;
-+				late = 1;
-+			}
-+		}
-+	} else
-+		/*#endif*/ { /* MBSSID */
-+		time_offset = 2 * bcn_interval_us - cur_tick - BEACON_EARLY_TIME * NET80211_TU_TO_US;
-+		if (time_offset > (bcn_interval_us + (bcn_interval_us >> 1))) {
-+			time_offset -= bcn_interval_us;
-+			late = 1;
-+		}
-+	}
-+	_exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL);
-+
-+#ifdef DBG_SWTIMER_BASED_TXBCN
-+	RTW_INFO("set sw bcn timer %d us\n", time_offset);
-+#endif
-+	txbcn_timer_ms = time_offset / NET80211_TU_TO_US;
-+	_set_timer(&pdvobj->txbcn_timer, txbcn_timer_ms);
-+
-+	if (padapter) {
-+#ifdef CONFIG_BCN_RECOVERY
-+		rtw_ap_bcn_recovery(padapter);
-+#endif /*CONFIG_BCN_RECOVERY*/
-+
-+#ifdef CONFIG_BCN_XMIT_PROTECT
-+		rtw_ap_bcn_queue_empty_check(padapter, txbcn_timer_ms);
-+#endif /*CONFIG_BCN_XMIT_PROTECT*/
-+
-+#ifdef DBG_SWTIMER_BASED_TXBCN
-+		RTW_INFO("padapter=%p, PORT=%d\n", padapter, padapter->hw_port);
-+#endif
-+		/* bypass TX BCN queue if op ch is switching/waiting */
-+		if (!check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)
-+			&& !IS_CH_WAITING(adapter_to_rfctl(padapter))
-+		) {
-+			/*update_beacon(padapter, _TIM_IE_, NULL, _FALSE, 0);*/
-+			/*issue_beacon(padapter, 0);*/
-+			send_beacon(padapter);
-+		}
-+	}
-+
-+#if 0
-+	/* handle any buffered BC/MC frames*/
-+	/* Don't dynamically change DIS_ATIM due to HW will auto send ACQ after HIQ empty.*/
-+	val8 = *((unsigned char *)priv->beaconbuf + priv->timoffset + 4);
-+	if (val8 & 0x01) {
-+		process_mcast_dzqueue(priv);
-+		priv->pkt_in_dtimQ = 0;
-+	}
-+#endif
-+
-+}
-+
-+void tx_beacon_timer_handlder(void *ctx)
-+{
-+	struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx;
-+	_adapter *padapter = pdvobj->padapters[0];
-+
-+	if (padapter)
-+		set_tx_beacon_cmd(padapter, 0);
-+}
-+#endif
-+
-+void rtw_ap_parse_sta_capability(_adapter *adapter, struct sta_info *sta, u8 *cap)
-+{
-+	sta->capability = RTW_GET_LE16(cap);
-+	if (sta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
-+		sta->flags |= WLAN_STA_SHORT_PREAMBLE;
-+	else
-+		sta->flags &= ~WLAN_STA_SHORT_PREAMBLE;
-+}
-+
-+u16 rtw_ap_parse_sta_supported_rates(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len)
-+{
-+	u8 rate_set[12];
-+	u8 rate_num;
-+	int i;
-+	u16 status = _STATS_SUCCESSFUL_;
-+
-+	rtw_ies_get_supported_rate(tlv_ies, tlv_ies_len, rate_set, &rate_num);
-+	if (rate_num == 0) {
-+		RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" with no supported rate\n"
-+			, FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
-+		status = _STATS_FAILURE_;
-+		goto exit;
-+	}
-+
-+	_rtw_memcpy(sta->bssrateset, rate_set, rate_num);
-+	sta->bssratelen = rate_num;
-+
-+	if (MLME_IS_AP(adapter)) {
-+		/* this function force only CCK rates to be bassic rate... */
-+		UpdateBrateTblForSoftAP(sta->bssrateset, sta->bssratelen);
-+	}
-+
-+	/* if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G) */ /* ? */
-+	sta->flags |= WLAN_STA_NONERP;
-+	for (i = 0; i < sta->bssratelen; i++) {
-+		if ((sta->bssrateset[i] & 0x7f) > 22) {
-+			sta->flags &= ~WLAN_STA_NONERP;
-+			break;
-+		}
-+	}
-+
-+exit:
-+	return status;
-+}
-+
-+u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)
-+{
-+	struct security_priv *sec = &adapter->securitypriv;
-+	u8 *wpa_ie;
-+	int wpa_ie_len;
-+	int group_cipher = 0, pairwise_cipher = 0, gmcs = 0;
-+	u32 akm = 0;
-+	u8 mfp_opt = MFP_NO;
-+	u16 status = _STATS_SUCCESSFUL_;
-+
-+	sta->dot8021xalg = 0;
-+	sta->wpa_psk = 0;
-+	sta->wpa_group_cipher = 0;
-+	sta->wpa2_group_cipher = 0;
-+	sta->wpa_pairwise_cipher = 0;
-+	sta->wpa2_pairwise_cipher = 0;
-+	_rtw_memset(sta->wpa_ie, 0, sizeof(sta->wpa_ie));
-+
-+	if ((sec->wpa_psk & BIT(1)) && elems->rsn_ie) {
-+		wpa_ie = elems->rsn_ie;
-+		wpa_ie_len = elems->rsn_ie_len;
-+
-+		if (rtw_parse_wpa2_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, &gmcs, &akm, &mfp_opt) == _SUCCESS) {
-+			sta->dot8021xalg = 1;/* psk, todo:802.1x */
-+			sta->wpa_psk |= BIT(1);
-+
-+			sta->wpa2_group_cipher = group_cipher & sec->wpa2_group_cipher;
-+			sta->wpa2_pairwise_cipher = pairwise_cipher & sec->wpa2_pairwise_cipher;
-+
-+			sta->akm_suite_type = akm;
-+			if (MLME_IS_AP(adapter) && (CHECK_BIT(WLAN_AKM_TYPE_SAE, akm)) && (MFP_NO == mfp_opt)) {
-+				status = WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION;
-+				goto exit;
-+			}
-+
-+			if (MLME_IS_AP(adapter) && (!CHECK_BIT(sec->akmp, akm))) {
-+				status = WLAN_STATUS_AKMP_NOT_VALID;
-+				goto exit;
-+			}
-+
-+			if (!sta->wpa2_group_cipher) {
-+				status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID;
-+				goto exit;
-+			}
-+
-+			if (!sta->wpa2_pairwise_cipher) {
-+				status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID;
-+				goto exit;
-+			}
-+
-+		} else {
-+			status = WLAN_STATUS_INVALID_IE;
-+			goto exit;
-+		}
-+
-+	}
-+	else if ((sec->wpa_psk & BIT(0)) && elems->wpa_ie) {
-+		wpa_ie = elems->wpa_ie;
-+		wpa_ie_len = elems->wpa_ie_len;
-+
-+		if (rtw_parse_wpa_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
-+			sta->dot8021xalg = 1;/* psk, todo:802.1x */
-+			sta->wpa_psk |= BIT(0);
-+
-+			sta->wpa_group_cipher = group_cipher & sec->wpa_group_cipher;
-+			sta->wpa_pairwise_cipher = pairwise_cipher & sec->wpa_pairwise_cipher;
-+
-+			if (!sta->wpa_group_cipher) {
-+				status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID;
-+				goto exit;
-+			}
-+
-+			if (!sta->wpa_pairwise_cipher) {
-+				status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID;
-+				goto exit;
-+			}
-+		} else {
-+			status = WLAN_STATUS_INVALID_IE;
-+			goto exit;
-+		}
-+
-+	} else {
-+		wpa_ie = NULL;
-+		wpa_ie_len = 0;
-+	}
-+
-+	if ((sec->mfp_opt == MFP_REQUIRED && mfp_opt < MFP_OPTIONAL)
-+		|| (mfp_opt == MFP_REQUIRED && sec->mfp_opt < MFP_OPTIONAL)
-+	) {
-+		status = WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION;
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(adapter)) {
-+		/* MFP is mandatory for secure mesh */
-+		if (adapter->mesh_info.mesh_auth_id)
-+			sta->flags |= WLAN_STA_MFP;
-+	} else
-+#endif
-+	if (sec->mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL)
-+		sta->flags |= WLAN_STA_MFP;
-+
-+#ifdef CONFIG_IEEE80211W
-+	if ((sta->flags & WLAN_STA_MFP)
-+		&& (sec->mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL)
-+		&& security_type_bip_to_gmcs(sec->dot11wCipher) != gmcs
-+	) {
-+		status = WLAN_STATUS_CIPHER_REJECTED_PER_POLICY;
-+		goto exit;
-+	}
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (MLME_IS_AP(adapter) &&
-+		(sec->auth_type == MLME_AUTHTYPE_SAE) &&
-+		(CHECK_BIT(WLAN_AKM_TYPE_SAE, sta->akm_suite_type)) &&
-+		(WLAN_AUTH_OPEN == sta->authalg)) {
-+		/* WPA3-SAE, PMK caching */
-+		if (rtw_cached_pmkid(adapter, sta->cmn.mac_addr) == -1) {
-+			RTW_INFO("SAE: No PMKSA cache entry found\n");
-+			status = WLAN_STATUS_INVALID_PMKID;
-+			goto exit;
-+		} else {
-+			RTW_INFO("SAE: PMKSA cache entry found\n");
-+		}
-+	}
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+	if (!MLME_IS_AP(adapter))
-+		goto exit;
-+
-+	sta->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS);
-+	/* if (hapd->conf->wps_state && wpa_ie == NULL) { */ /* todo: to check ap if supporting WPS */
-+	if (wpa_ie == NULL) {
-+		if (elems->wps_ie) {
-+			RTW_INFO("STA included WPS IE in "
-+				 "(Re)Association Request - assume WPS is "
-+				 "used\n");
-+			sta->flags |= WLAN_STA_WPS;
-+			/* wpabuf_free(sta->wps_ie); */
-+			/* sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4, */
-+			/*				elems.wps_ie_len - 4); */
-+		} else {
-+			RTW_INFO("STA did not include WPA/RSN IE "
-+				 "in (Re)Association Request - possible WPS "
-+				 "use\n");
-+			sta->flags |= WLAN_STA_MAYBE_WPS;
-+		}
-+
-+		/* AP support WPA/RSN, and sta is going to do WPS, but AP is not ready */
-+		/* that the selected registrar of AP is _FLASE */
-+		if ((sec->wpa_psk > 0)
-+			&& (sta->flags & (WLAN_STA_WPS | WLAN_STA_MAYBE_WPS))
-+		) {
-+			struct mlme_priv *mlme = &adapter->mlmepriv;
-+
-+			if (mlme->wps_beacon_ie) {
-+				u8 selected_registrar = 0;
-+
-+				rtw_get_wps_attr_content(mlme->wps_beacon_ie, mlme->wps_beacon_ie_len, WPS_ATTR_SELECTED_REGISTRAR, &selected_registrar, NULL);
-+
-+				if (!selected_registrar) {
-+					RTW_INFO("selected_registrar is _FALSE , or AP is not ready to do WPS\n");
-+					status = _STATS_UNABLE_HANDLE_STA_;
-+					goto exit;
-+				}
-+			}
-+		}
-+
-+	} else {
-+		int copy_len;
-+
-+		if (sec->wpa_psk == 0) {
-+			RTW_INFO("STA " MAC_FMT
-+				": WPA/RSN IE in association request, but AP don't support WPA/RSN\n",
-+				MAC_ARG(sta->cmn.mac_addr));
-+			status = WLAN_STATUS_INVALID_IE;
-+			goto exit;
-+		}
-+
-+		if (elems->wps_ie) {
-+			RTW_INFO("STA included WPS IE in "
-+				 "(Re)Association Request - WPS is "
-+				 "used\n");
-+			sta->flags |= WLAN_STA_WPS;
-+			copy_len = 0;
-+		} else
-+			copy_len = ((wpa_ie_len + 2) > sizeof(sta->wpa_ie)) ? (sizeof(sta->wpa_ie)) : (wpa_ie_len + 2);
-+
-+		if (copy_len > 0)
-+			_rtw_memcpy(sta->wpa_ie, wpa_ie - 2, copy_len);
-+	}
-+
-+exit:
-+	return status;
-+}
-+
-+void rtw_ap_parse_sta_wmm_ie(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len)
-+{
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+	unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01};
-+	u8 *p;
-+
-+	sta->flags &= ~WLAN_STA_WME;
-+	sta->qos_option = 0;
-+	sta->qos_info = 0;
-+	sta->has_legacy_ac = _TRUE;
-+	sta->uapsd_vo = 0;
-+	sta->uapsd_vi = 0;
-+	sta->uapsd_be = 0;
-+	sta->uapsd_bk = 0;
-+
-+	if (!mlme->qospriv.qos_option)
-+		goto exit;
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(adapter)) {
-+		/* QoS is mandatory in mesh */
-+		sta->flags |= WLAN_STA_WME;
-+	}
-+#endif
-+
-+	p = rtw_get_ie_ex(tlv_ies, tlv_ies_len, WLAN_EID_VENDOR_SPECIFIC, WMM_IE, 6, NULL, NULL);
-+	if (!p)
-+		goto exit;
-+
-+	sta->flags |= WLAN_STA_WME;
-+	sta->qos_option = 1;
-+	sta->qos_info = *(p + 8);
-+	sta->max_sp_len = (sta->qos_info >> 5) & 0x3;
-+
-+	if ((sta->qos_info & 0xf) != 0xf)
-+		sta->has_legacy_ac = _TRUE;
-+	else
-+		sta->has_legacy_ac = _FALSE;
-+
-+	if (sta->qos_info & 0xf) {
-+		if (sta->qos_info & BIT(0))
-+			sta->uapsd_vo = BIT(0) | BIT(1);
-+		else
-+			sta->uapsd_vo = 0;
-+
-+		if (sta->qos_info & BIT(1))
-+			sta->uapsd_vi = BIT(0) | BIT(1);
-+		else
-+			sta->uapsd_vi = 0;
-+
-+		if (sta->qos_info & BIT(2))
-+			sta->uapsd_bk = BIT(0) | BIT(1);
-+		else
-+			sta->uapsd_bk = 0;
-+
-+		if (sta->qos_info & BIT(3))
-+			sta->uapsd_be = BIT(0) | BIT(1);
-+		else
-+			sta->uapsd_be = 0;
-+	}
-+
-+exit:
-+	return;
-+}
-+
-+void rtw_ap_parse_sta_ht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)
-+{
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+
-+	sta->flags &= ~WLAN_STA_HT;
-+
-+#ifdef CONFIG_80211N_HT
-+	if (mlme->htpriv.ht_option == _FALSE)
-+		goto exit;
-+
-+	/* save HT capabilities in the sta object */
-+	_rtw_memset(&sta->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap));
-+	if (elems->ht_capabilities && elems->ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap)) {
-+		sta->flags |= WLAN_STA_HT;
-+		sta->flags |= WLAN_STA_WME;
-+		_rtw_memcpy(&sta->htpriv.ht_cap, elems->ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap));
-+
-+		if (elems->ht_operation && elems->ht_operation_len == HT_OP_IE_LEN) {
-+			_rtw_memcpy(sta->htpriv.ht_op, elems->ht_operation, HT_OP_IE_LEN);
-+			sta->htpriv.op_present = 1;
-+		}
-+	}
-+exit:
-+#endif
-+
-+	return;
-+}
-+
-+void rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)
-+{
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+
-+	sta->flags &= ~WLAN_STA_VHT;
-+
-+#ifdef CONFIG_80211AC_VHT
-+	if (mlme->vhtpriv.vht_option == _FALSE)
-+		goto exit;
-+
-+	_rtw_memset(&sta->vhtpriv, 0, sizeof(struct vht_priv));
-+	if (elems->vht_capabilities && elems->vht_capabilities_len == VHT_CAP_IE_LEN) {
-+		sta->flags |= WLAN_STA_VHT;
-+		_rtw_memcpy(sta->vhtpriv.vht_cap, elems->vht_capabilities, VHT_CAP_IE_LEN);
-+
-+		if (elems->vht_operation && elems->vht_operation_len== VHT_OP_IE_LEN) {
-+			_rtw_memcpy(sta->vhtpriv.vht_op, elems->vht_operation, VHT_OP_IE_LEN);
-+			sta->vhtpriv.op_present = 1;
-+		}
-+
-+		if (elems->vht_op_mode_notify && elems->vht_op_mode_notify_len == 1) {
-+			_rtw_memcpy(&sta->vhtpriv.vht_op_mode_notify, elems->vht_op_mode_notify, 1);
-+			sta->vhtpriv.notify_present = 1;
-+		}
-+	}
-+exit:
-+#endif
-+
-+	return;
-+}
-+
-+void rtw_ap_parse_sta_multi_ap_ie(_adapter *adapter, struct sta_info *sta, u8 *ies, int ies_len)
-+{
-+	sta->flags &= ~WLAN_STA_MULTI_AP;
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+	if (adapter->multi_ap
-+		&& (rtw_get_multi_ap_ie_ext(ies, ies_len) & MULTI_AP_BACKHAUL_STA)
-+	) {
-+		if (adapter->multi_ap & MULTI_AP_BACKHAUL_BSS) /* with backhaul bss, enable WDS */
-+			sta->flags |= WLAN_STA_MULTI_AP | WLAN_STA_WDS;
-+		else if (adapter->multi_ap & MULTI_AP_FRONTHAUL_BSS) /* fronthaul bss only */
-+			sta->flags |= WLAN_STA_MULTI_AP;
-+	}
-+#endif
-+}
-+
-+#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+static bool rtw_ap_data_bmc_to_uc(_adapter *adapter
-+	, const u8 *da, const u8 *sa, const u8 *ori_ta
-+	, u16 os_qid, _list *b2u_list)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct xmit_priv *xmitpriv = &adapter->xmitpriv;
-+	_irqL irqL;
-+	_list *head, *list;
-+	struct sta_info *sta;
-+	char b2u_sta_id[NUM_STA];
-+	u8 b2u_sta_num = 0;
-+	bool bmc_need = _FALSE;
-+	int i;
-+
-+	_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+	head = &stapriv->asoc_list;
-+	list = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
-+		int stainfo_offset;
-+
-+		sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
-+		list = get_next(list);
-+	
-+		stainfo_offset = rtw_stainfo_offset(stapriv, sta);
-+		if (stainfo_offset_valid(stainfo_offset))
-+			b2u_sta_id[b2u_sta_num++] = stainfo_offset;
-+	}
-+	_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+
-+	if (!b2u_sta_num)
-+		goto exit;
-+
-+	for (i = 0; i < b2u_sta_num; i++) {
-+		struct xmit_frame *b2uframe;
-+		struct pkt_attrib *attrib;
-+
-+		sta = rtw_get_stainfo_by_offset(stapriv, b2u_sta_id[i]);
-+		if (!(sta->state & WIFI_ASOC_STATE)
-+			|| _rtw_memcmp(sta->cmn.mac_addr, sa, ETH_ALEN) == _TRUE
-+			|| (ori_ta && _rtw_memcmp(sta->cmn.mac_addr, ori_ta, ETH_ALEN) == _TRUE)
-+			|| is_broadcast_mac_addr(sta->cmn.mac_addr)
-+			|| is_zero_mac_addr(sta->cmn.mac_addr))
-+			continue;
-+
-+		b2uframe = rtw_alloc_xmitframe(xmitpriv, os_qid);
-+		if (!b2uframe) {
-+			bmc_need = _TRUE;
-+			break;
-+		}
-+
-+		attrib = &b2uframe->attrib;
-+
-+		_rtw_memcpy(attrib->ra, sta->cmn.mac_addr, ETH_ALEN);
-+		_rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
-+		#ifdef CONFIG_RTW_WDS
-+		if (adapter_use_wds(adapter) && (sta->flags & WLAN_STA_WDS)) {
-+			_rtw_memcpy(attrib->dst, da, ETH_ALEN);
-+			attrib->wds = 1;
-+		} else
-+		#endif
-+			_rtw_memcpy(attrib->dst, attrib->ra, ETH_ALEN);
-+		_rtw_memcpy(attrib->src, sa, ETH_ALEN);
-+
-+		rtw_list_insert_tail(&b2uframe->list, b2u_list);
-+	}
-+
-+exit:
-+	return bmc_need;
-+}
-+
-+void dump_ap_b2u_flags(void *sel, _adapter *adapter)
-+{
-+	RTW_PRINT_SEL(sel, "%4s %4s\n", "src", "fwd");
-+	RTW_PRINT_SEL(sel, "0x%02x 0x%02x\n", adapter->b2u_flags_ap_src, adapter->b2u_flags_ap_fwd);
-+}
-+#endif /* CONFIG_RTW_AP_DATA_BMC_TO_UC */
-+
-+static int rtw_ap_nexthop_resolve(_adapter *adapter, struct xmit_frame *xframe)
-+{
-+	struct pkt_attrib *attrib = &xframe->attrib;
-+	int ret = _SUCCESS;
-+
-+#ifdef CONFIG_RTW_WDS
-+	if (adapter_use_wds(adapter)
-+		&& rtw_wds_nexthop_lookup(adapter, attrib->dst, attrib->ra) == 0
-+	) {
-+		if (_rtw_memcmp(attrib->dst, attrib->ra, ETH_ALEN) == _FALSE)
-+			attrib->wds = 1;
-+	} else
-+#endif
-+		_rtw_memcpy(attrib->ra, attrib->dst, ETH_ALEN);
-+
-+	return ret;
-+}
-+
-+int rtw_ap_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list)
-+{
-+	struct pkt_file pktfile;
-+	struct ethhdr etherhdr;
-+	struct pkt_attrib *attrib;
-+	struct rtw_mesh_path *mpath = NULL, *mppath = NULL;
-+	u8 is_da_mcast;
-+	u8 addr4_need;
-+#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+	bool bmc_need = _TRUE;
-+#endif
-+	int res = _SUCCESS;
-+
-+	_rtw_open_pktfile(pkt, &pktfile);
-+	if (_rtw_pktfile_read(&pktfile, (u8 *)&etherhdr, ETH_HLEN) != ETH_HLEN) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	
-+	xframe->pkt = pkt;
-+#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+	_rtw_init_listhead(b2u_list);
-+#endif
-+
-+	is_da_mcast = IS_MCAST(etherhdr.h_dest);
-+	if (is_da_mcast) {
-+		#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+		if (rtw_ap_src_b2u_policy_chk(adapter->b2u_flags_ap_src, etherhdr.h_dest)
-+			&& adapter->registrypriv.wifi_spec == 0
-+			&& adapter->xmitpriv.free_xmitframe_cnt > (NR_XMITFRAME / 4)
-+		) {
-+			bmc_need = rtw_ap_data_bmc_to_uc(adapter
-+				, etherhdr.h_dest, etherhdr.h_source, NULL, os_qid, b2u_list);
-+			if (bmc_need == _FALSE) {
-+				res = RTW_BMC_NO_NEED;
-+				goto exit;
-+			}
-+		}
-+		#endif
-+	}
-+
-+	attrib = &xframe->attrib;
-+
-+	_rtw_memcpy(attrib->dst, etherhdr.h_dest, ETH_ALEN);
-+	_rtw_memcpy(attrib->src, etherhdr.h_source, ETH_ALEN);
-+	_rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
-+
-+	if (is_da_mcast)
-+		_rtw_memcpy(attrib->ra, attrib->dst, ETH_ALEN);
-+	else
-+		res = rtw_ap_nexthop_resolve(adapter, xframe);
-+
-+exit:
-+	return res;
-+}
-+
-+int rtw_ap_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
-+	u8 *whdr = get_recvframe_data(rframe);
-+	u8 is_ra_bmc = 0;
-+	sint ret = _FAIL;
-+
-+	if (!(MLME_STATE(adapter) & WIFI_ASOC_STATE))
-+		goto exit;
-+
-+	switch (rattrib->to_fr_ds) {
-+	case 1:
-+		if (IS_MCAST(GetAddr1Ptr(whdr)))
-+			goto exit;
-+		_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
-+		_rtw_memcpy(rattrib->src, get_addr2_ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->bssid, GetAddr1Ptr(whdr), ETH_ALEN);
-+		break;
-+	case 3:
-+		is_ra_bmc = IS_MCAST(GetAddr1Ptr(whdr)) ? 1 : 0;
-+		_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
-+		_rtw_memcpy(rattrib->src, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
-+		if (!is_ra_bmc)
-+			_rtw_memcpy(rattrib->bssid, GetAddr1Ptr(whdr), ETH_ALEN);
-+		break;
-+	default:
-+		ret = RTW_RX_HANDLED; /* don't count for drop */
-+		goto exit;
-+	}
-+
-+	*sta = rtw_get_stainfo(stapriv, rattrib->ta);
-+	if (*sta == NULL) {
-+		if (!is_ra_bmc && !IS_RADAR_DETECTED(adapter_to_rfctl(adapter))) {
-+			#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL
-+			RTW_INFO(FUNC_ADPT_FMT" issue_deauth to "MAC_FMT" with reason(7), unknown TA\n"
-+				, FUNC_ADPT_ARG(adapter), MAC_ARG(rattrib->ta));
-+			issue_deauth(adapter, rattrib->ta, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
-+			#endif
-+		}
-+		ret = RTW_RX_HANDLED;
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_RTW_WDS_AUTO_EN
-+	if (rattrib->to_fr_ds == 3 && !(sta->flags & WLAN_STA_WDS))
-+		sta->flags |= WLAN_STA_WDS;
-+#endif
-+
-+	process_pwrbit_data(adapter, rframe, *sta);
-+	
-+	if ((get_frame_sub_type(whdr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE)
-+		process_wmmps_data(adapter, rframe, *sta);
-+	
-+	if (get_frame_sub_type(whdr) & BIT(6)) {
-+		/* No data, will not indicate to upper layer, temporily count it here */
-+		count_rx_stats(adapter, rframe, *sta);
-+		ret = RTW_RX_HANDLED;
-+		goto exit;
-+	}
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+int rtw_ap_rx_msdu_act_check(union recv_frame *rframe
-+	, const u8 *da, const u8 *sa
-+	, u8 *msdu, enum rtw_rx_llc_hdl llc_hdl
-+	, struct xmit_frame **fwd_frame, _list *b2u_list)
-+{
-+	_adapter *adapter = rframe->u.hdr.adapter;
-+	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
-+	struct rtw_wds_path *wpath;
-+	u8 is_da_bmc = IS_MCAST(da); 
-+	u8 is_da_self = !is_da_bmc && _rtw_memcmp(da, adapter_mac_addr(adapter), ETH_ALEN);
-+	u8 is_da_peer = 0;
-+	int in_wds_tbl = 0;
-+	u16 os_qid;
-+	struct xmit_frame *xframe;
-+	struct pkt_attrib *xattrib;
-+	u8 fwd_ra[ETH_ALEN] = {0};
-+	int act = 0;
-+#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+	bool bmc_need = _TRUE;
-+#endif
-+
-+#ifdef CONFIG_RTW_WDS
-+	/* update/create wds info for SA, RA */
-+	if (adapter_use_wds(adapter)
-+		&& (rframe->u.hdr.psta->state & WIFI_ASOC_STATE)
-+		&& _rtw_memcmp(sa, rframe->u.hdr.psta->cmn.mac_addr, ETH_ALEN) == _FALSE
-+	) {
-+		rtw_rcu_read_lock();
-+		wpath = rtw_wds_path_lookup(adapter, sa);
-+		if (!wpath)
-+			rtw_wds_path_add(adapter, sa, rframe->u.hdr.psta);
-+		else {
-+			rtw_wds_path_assign_nexthop(wpath, rframe->u.hdr.psta);
-+			wpath->last_update = rtw_get_current_time();
-+		}
-+		rtw_rcu_read_unlock();
-+	}
-+#endif
-+
-+	/* SA is self, need no further process */
-+	if (_rtw_memcmp(sa, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
-+		goto exit;
-+
-+	if (is_da_bmc) {
-+		/* DA is bmc addr */
-+		act |= RTW_RX_MSDU_ACT_INDICATE;
-+		if (adapter->mlmepriv.ap_isolate)
-+			goto exit;
-+		goto fwd_chk;
-+
-+	}
-+	
-+	if (is_da_self) {
-+		/* DA is self, indicate */
-+		act |= RTW_RX_MSDU_ACT_INDICATE;
-+		goto exit;
-+	}
-+
-+	/* DA is not self */
-+#ifdef CONFIG_RTW_WDS
-+	if (adapter_use_wds(adapter))
-+		in_wds_tbl = rtw_wds_nexthop_lookup(adapter, da, fwd_ra) == 0;
-+#endif
-+	if (!in_wds_tbl)
-+		is_da_peer = rtw_get_stainfo(&adapter->stapriv, da) ? 1 : 0;
-+
-+	if (in_wds_tbl || is_da_peer) {
-+		/* DA is known (peer or can be forwarded by peer) */
-+		if (adapter->mlmepriv.ap_isolate) {
-+			#if defined(DBG_RX_DROP_FRAME)
-+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") through peer, ap_isolate\n"
-+				, FUNC_ADPT_ARG(adapter), MAC_ARG(da));
-+			#endif
-+			goto exit;
-+		}
-+		goto fwd_chk;
-+	}
-+
-+	/* DA is unknown*/
-+	act |= RTW_RX_MSDU_ACT_INDICATE;
-+	goto exit;
-+
-+fwd_chk:
-+
-+	if (adapter->stapriv.asoc_list_cnt <= 1)
-+		goto exit;
-+
-+	os_qid = rtw_os_recv_select_queue(msdu, llc_hdl);
-+
-+#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+	_rtw_init_listhead(b2u_list);
-+
-+	if (is_da_bmc
-+		&& rtw_ap_fwd_b2u_policy_chk(adapter->b2u_flags_ap_fwd, da, rattrib->to_fr_ds == 3 && !IS_MCAST(rattrib->ra))
-+		&& adapter->registrypriv.wifi_spec == 0
-+		&& adapter->xmitpriv.free_xmitframe_cnt > (NR_XMITFRAME / 4)
-+	) {
-+		bmc_need = rtw_ap_data_bmc_to_uc(adapter
-+			, da, sa, rframe->u.hdr.psta->cmn.mac_addr
-+			, os_qid, b2u_list);
-+	}
-+
-+	if (bmc_need == _TRUE)
-+#endif
-+	{
-+		xframe = rtw_alloc_xmitframe(&adapter->xmitpriv, os_qid);
-+		if (!xframe) {
-+			#ifdef DBG_TX_DROP_FRAME
-+			RTW_INFO("DBG_TX_DROP_FRAME "FUNC_ADPT_FMT" rtw_alloc_xmitframe fail\n"
-+				, FUNC_ADPT_ARG(adapter));
-+			#endif
-+			goto exit;
-+		}
-+
-+		xattrib = &xframe->attrib;
-+
-+		_rtw_memcpy(xattrib->dst, da, ETH_ALEN);
-+		_rtw_memcpy(xattrib->src, sa, ETH_ALEN);
-+		_rtw_memcpy(xattrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
-+
-+		#ifdef CONFIG_RTW_WDS
-+		if (in_wds_tbl && _rtw_memcmp(da, fwd_ra, ETH_ALEN) == _FALSE) {
-+			_rtw_memcpy(xattrib->ra, fwd_ra, ETH_ALEN);
-+			xattrib->wds = 1;			
-+		} else
-+		#endif
-+			_rtw_memcpy(xattrib->ra, da, ETH_ALEN);
-+
-+		*fwd_frame = xframe;
-+	}
-+
-+	act |= RTW_RX_MSDU_ACT_FORWARD;
-+
-+exit:
-+	return act;
-+}
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+void rtw_issue_action_token_req(_adapter *padapter, struct sta_info *pstat)
-+{
-+	/* Token Request Format
-+	 	Category code :		1 Byte
-+		Action code : 		1 Byte
-+		Element field: 		4 Bytes, the duration of data transmission requested for the station.
-+	*/
-+
-+	u8 val = 0x0;
-+	u8 category = RTW_WLAN_CATEGORY_TBTX;
-+	u32 tbtx_duration = TBTX_TX_DURATION*1000;
-+	u8 *pframe;
-+	unsigned short *fctrl;
-+	struct xmit_frame		*pmgntframe;
-+	struct pkt_attrib		*pattrib;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
-+
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		return;
-+
-+	RTW_DBG("%s: %6ph\n", __FUNCTION__, pstat->cmn.mac_addr);
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+	pattrib->rate = MGN_24M; /* issue action request using OFDM rate? 20190716 Bruce add */ 
-+	
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->cmn.mac_addr, ETH_ALEN);
-+	_rtw_memcpy((void *)get_addr2_ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+	
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(val), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *)&(tbtx_duration), &(pattrib->pktlen));
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+	padapter->stapriv.last_token_holder = pstat;
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+}
-+#endif	/* CONFIG_RTW_TOKEN_BASED_XMIT */
-+#endif	/* CONFIG_AP_MODE */
-+
-diff --git a/drivers/staging/rtl8723cs/core/rtw_beamforming.c b/drivers/staging/rtl8723cs/core/rtw_beamforming.c
-new file mode 100644
-index 000000000000..8eda985da204
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_beamforming.c
-@@ -0,0 +1,2194 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_BEAMFORMING_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#ifdef CONFIG_BEAMFORMING
-+
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+
-+struct ndpa_sta_info {
-+	u16 aid:12;
-+	u16 feedback_type:1;
-+	u16 nc_index:3;
-+};
-+
-+static void _get_txvector_parameter(PADAPTER adapter, struct sta_info *sta, u8 *g_id, u16 *p_aid)
-+{
-+	struct mlme_priv *mlme;
-+	u16 aid;
-+	u8 *bssid;
-+	u16 val16;
-+	u8 i;
-+
-+
-+	mlme = &adapter->mlmepriv;
-+
-+	if (check_fwstate(mlme, WIFI_AP_STATE)) {
-+		/*
-+		 * Sent by an AP and addressed to a STA associated with that AP
-+		 * or sent by a DLS or TDLS STA in a direct path to
-+		 * a DLS or TDLS peer STA
-+		 */
-+
-+		aid = sta->cmn.aid;
-+		bssid = adapter_mac_addr(adapter);
-+		RTW_INFO("%s: AID=0x%x BSSID=" MAC_FMT "\n",
-+			 __FUNCTION__, sta->cmn.aid, MAC_ARG(bssid));
-+
-+		/* AID[0:8] */
-+		aid &= 0x1FF;
-+		/* BSSID[44:47] xor BSSID[40:43] */
-+		val16 = ((bssid[5] & 0xF0) >> 4) ^ (bssid[5] & 0xF);
-+		/* (dec(AID[0:8]) + dec(BSSID)*2^5) mod 2^9 */
-+		*p_aid = (aid + (val16 << 5)) & 0x1FF;
-+		*g_id = 63;
-+	} else if ((check_fwstate(mlme, WIFI_ADHOC_STATE) == _TRUE)
-+		   || (check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
-+		/*
-+		 * Otherwise, includes
-+		 * 1. Sent to an IBSS STA
-+		 * 2. Sent by an AP to a non associated STA
-+		 * 3. Sent to a STA for which it is not known
-+		 *    which condition is applicable
-+		 */
-+		*p_aid = 0;
-+		*g_id = 63;
-+	} else {
-+		/* Addressed to AP */
-+		bssid = sta->cmn.mac_addr;
-+		RTW_INFO("%s: BSSID=" MAC_FMT "\n", __FUNCTION__, MAC_ARG(bssid));
-+
-+		/* BSSID[39:47] */
-+		*p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
-+		*g_id = 0;
-+	}
-+
-+	RTW_INFO("%s: GROUP_ID=0x%02x PARTIAL_AID=0x%04x\n",
-+		 __FUNCTION__, *g_id, *p_aid);
-+}
-+
-+/*
-+ * Parameters
-+ *	adapter		struct _adapter*
-+ *	sta		struct sta_info*
-+ *	sta_bf_cap	beamforming capabe of sta
-+ *	sounding_dim	Number of Sounding Dimensions
-+ *	comp_steering	Compressed Steering Number of Beamformer Antennas Supported
-+ */
-+static void _get_sta_beamform_cap(PADAPTER adapter, struct sta_info *sta,
-+	u8 *sta_bf_cap, u8 *sounding_dim, u8 *comp_steering)
-+{
-+	struct beamforming_info *info;
-+	struct mlme_priv *mlme;
-+	struct ht_priv *ht;
-+	u16 ht_bf_cap;
-+#ifdef CONFIG_80211AC_VHT
-+	struct vht_priv *vht;
-+	u16 vht_bf_cap;
-+#endif /* CONFIG_80211AC_VHT */
-+
-+
-+	*sta_bf_cap = 0;
-+	*sounding_dim = 0;
-+	*comp_steering = 0;
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+	ht = &adapter->mlmepriv.htpriv;
-+#ifdef CONFIG_80211AC_VHT
-+	vht = &adapter->mlmepriv.vhtpriv;
-+#endif /* CONFIG_80211AC_VHT */
-+	mlme = &adapter->mlmepriv;
-+
-+	if (is_supported_ht(sta->wireless_mode) == _FALSE)
-+		return;
-+
-+	/* HT */
-+	if (check_fwstate(mlme, WIFI_AP_STATE)) {
-+		/* Get peer clinet's BF cap: the cap. is intersected with associated AP.*/
-+		ht_bf_cap = sta->htpriv.beamform_cap;
-+		RTW_INFO("At AP state, peer sta's ht_bf_cap=0x%x\n", ht_bf_cap);
-+
-+		if (TEST_FLAG(ht_bf_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {
-+			info->beamforming_cap |= BEAMFORMER_CAP_HT_EXPLICIT;
-+			*sta_bf_cap |= BEAMFORMEE_CAP_HT_EXPLICIT;
-+			*comp_steering = (ht_bf_cap & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4;
-+			RTW_INFO("%s: we support BEAMFORMER_CAP_HT_EXPLICIT\n", __func__);
-+		}
-+		if (TEST_FLAG(ht_bf_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {
-+			info->beamforming_cap |= BEAMFORMEE_CAP_HT_EXPLICIT;
-+			*sta_bf_cap |= BEAMFORMER_CAP_HT_EXPLICIT;
-+			*sounding_dim = (ht_bf_cap & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6;
-+			RTW_INFO("%s: we support BEAMFORMEE_CAP_HT_EXPLICIT\n", __func__);
-+		}
-+	} else {
-+		/* Get adapter's BF Cap: the cap. is intersected with associated AP.*/
-+		ht_bf_cap = ht->beamform_cap;
-+		RTW_INFO("At non-AP state, adapter's ht_bf_cap=0x%x\n", ht_bf_cap);
-+
-+		if (TEST_FLAG(ht_bf_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {
-+			info->beamforming_cap |= BEAMFORMEE_CAP_HT_EXPLICIT;
-+			*sta_bf_cap |= BEAMFORMER_CAP_HT_EXPLICIT;
-+			*sounding_dim = (ht_bf_cap & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6;
-+			RTW_INFO("%s: we support BEAMFORMEE_CAP_HT_EXPLICIT\n", __func__);
-+		}
-+		if (TEST_FLAG(ht_bf_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {
-+			info->beamforming_cap |= BEAMFORMER_CAP_HT_EXPLICIT;
-+			*sta_bf_cap |= BEAMFORMEE_CAP_HT_EXPLICIT;
-+			*comp_steering = (ht_bf_cap & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4;
-+			RTW_INFO("%s: we support BEAMFORMER_CAP_HT_EXPLICIT\n", __func__);
-+		}
-+	}
-+
-+#ifdef CONFIG_80211AC_VHT
-+
-+	if (is_supported_vht(sta->wireless_mode) == _FALSE)
-+		return;
-+
-+	/* VHT */
-+	if (check_fwstate(mlme, WIFI_AP_STATE)) {
-+		/* Get peer clinet's BF cap: the cap. is intersected with associated AP.*/
-+		vht_bf_cap = sta->vhtpriv.beamform_cap;
-+		RTW_INFO("At AP state, peer sta's vht_bf_cap=0x%x\n", vht_bf_cap);
-+
-+		/* We are SU Beamformer because the STA is SU Beamformee */
-+		if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
-+			info->beamforming_cap |= BEAMFORMER_CAP_VHT_SU;
-+			*sta_bf_cap |= BEAMFORMEE_CAP_VHT_SU;
-+			RTW_INFO("%s: we support BEAMFORMER_CAP_VHT_SU\n", __func__);
-+
-+			/* We are MU Beamformer because the STA is MU Beamformee */
-+			if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) {
-+				info->beamforming_cap |= BEAMFORMER_CAP_VHT_MU;
-+				*sta_bf_cap |= BEAMFORMEE_CAP_VHT_MU;
-+				RTW_INFO("%s: we support BEAMFORMER_CAP_VHT_MU\n", __func__);
-+			}
-+
-+			*comp_steering = (vht_bf_cap & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;
-+		}
-+		/* We are SU Beamformee because the STA is SU Beamformer */
-+		if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
-+			info->beamforming_cap |= BEAMFORMEE_CAP_VHT_SU;
-+			*sta_bf_cap |= BEAMFORMER_CAP_VHT_SU;
-+			RTW_INFO("%s: we support BEAMFORMEE_CAP_VHT_SU\n", __func__);
-+
-+			/* The STA is MU Beamformer, but we(AP) should not be MU Beamformee */
-+			if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {
-+				RTW_WARN("%s: Associated STA should not be a MU BFer.\n", __func__);
-+			}
-+
-+			*sounding_dim = (vht_bf_cap & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;
-+		}
-+	} else {
-+		/* Get adapter's BF Cap: the cap. is intersected with associated AP.*/
-+		vht_bf_cap = vht->beamform_cap;
-+		RTW_INFO("At non-AP state, adapter's vht_bf_cap=0x%x\n", vht_bf_cap);
-+
-+		/* We are SU Beamformee */
-+		if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
-+			info->beamforming_cap |= BEAMFORMEE_CAP_VHT_SU;
-+			*sta_bf_cap |= BEAMFORMER_CAP_VHT_SU;
-+			RTW_INFO("%s: we support BEAMFORMEE_CAP_VHT_SU\n", __func__);
-+
-+			/* We are MU Beamformee */
-+			if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) {
-+				info->beamforming_cap |= BEAMFORMEE_CAP_VHT_MU;
-+				*sta_bf_cap |= BEAMFORMER_CAP_VHT_MU;
-+				RTW_INFO("%s: we support BEAMFORMEE_CAP_VHT_MU\n", __func__);
-+			}
-+
-+			*sounding_dim = (vht_bf_cap & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;
-+		}
-+		/* We are SU Beamformer */
-+		if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
-+			info->beamforming_cap |= BEAMFORMER_CAP_VHT_SU;
-+			*sta_bf_cap |= BEAMFORMEE_CAP_VHT_SU;
-+			RTW_INFO("%s: we support BEAMFORMER_CAP_VHT_SU\n", __func__);
-+
-+			/* We are MU Beamformer, but client should not be a MU Beamformer */
-+			if (TEST_FLAG(vht_bf_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {
-+				RTW_WARN("%s: non-AP state should not support MU BFer.\n", __func__);
-+			}
-+
-+			*comp_steering = (vht_bf_cap & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;
-+		}
-+	}
-+#endif /* CONFIG_80211AC_VHT */
-+
-+}
-+
-+static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, enum channel_width bw)
-+{
-+	/* General */
-+	struct xmit_priv		*pxmitpriv;
-+	struct mlme_ext_priv		*pmlmeext;
-+	struct mlme_ext_info		*pmlmeinfo;
-+	struct xmit_frame		*pmgntframe;
-+	/* Beamforming */
-+	struct beamforming_info		*info;
-+	struct beamformee_entry		*bfee;
-+	struct ndpa_sta_info		sta_info;
-+	u8 ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xE0, 0x4C};
-+	/* MISC */
-+	struct pkt_attrib		*attrib;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	enum MGN_RATE txrate;
-+	u8 *pframe;
-+	u16 duration = 0;
-+	u8 aSifsTime = 0;
-+
-+
-+	RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra));
-+
-+	pxmitpriv = &adapter->xmitpriv;
-+	pmlmeext = &adapter->mlmeextpriv;
-+	pmlmeinfo = &pmlmeext->mlmext_info;
-+	bfee = rtw_bf_bfee_get_entry_by_addr(adapter, ra);
-+	if (!bfee) {
-+		RTW_ERR("%s: Cann't find beamformee entry!\n", __FUNCTION__);
-+		return _FALSE;
-+	}
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (!pmgntframe) {
-+		RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
-+		return _FALSE;
-+	}
-+
-+	txrate = beamforming_get_htndp_tx_rate(GET_PDM_ODM(adapter), bfee->comp_steering_num_of_bfer);
-+
-+	/* update attribute */
-+	attrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(adapter, attrib);
-+	/*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
-+	attrib->subtype = WIFI_ACTION_NOACK;
-+	attrib->bwmode = bw;
-+	/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
-+	attrib->order = 1;
-+	attrib->rate = (u8)txrate;
-+	attrib->bf_pkt_type = 0;
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	/* Frame control */
-+	pwlanhdr->frame_ctl = 0;
-+	set_frame_sub_type(pframe, attrib->subtype);
-+	set_order_bit(pframe);
-+
-+	/* Duration */
-+	if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
-+		aSifsTime = 10;
-+	else
-+		aSifsTime = 16;
-+	duration = 2 * aSifsTime + 40;
-+	if (bw == CHANNEL_WIDTH_40)
-+		duration += 87;
-+	else
-+		duration += 180;
-+	set_duration(pframe, duration);
-+
-+	/* DA */
-+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
-+	/* SA */
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
-+	/* BSSID */
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
-+
-+	/* HT control field */
-+	SET_HT_CTRL_CSI_STEERING(pframe + 24, 3);
-+	SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);
-+
-+	/*
-+	 * Frame Body
-+	 * Category field: vender-specific value, 0x7F
-+	 * OUI: 0x00E04C
-+	 */
-+	_rtw_memcpy(pframe + 28, ActionHdr, 4);
-+
-+	attrib->pktlen = 32;
-+	attrib->last_txcmdsz = attrib->pktlen;
-+
-+	dump_mgntframe(adapter, pmgntframe);
-+
-+	return _TRUE;
-+}
-+
-+static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, enum channel_width bw)
-+{
-+	/* General */
-+	struct xmit_priv		*pxmitpriv;
-+	struct mlme_ext_priv		*pmlmeext;
-+	struct xmit_frame		*pmgntframe;
-+	/* Beamforming */
-+	struct beamforming_info		*info;
-+	struct beamformee_entry		*bfee;
-+	struct ndpa_sta_info		sta_info;
-+	/* MISC */
-+	struct pkt_attrib		*attrib;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	u8 *pframe;
-+	enum MGN_RATE txrate;
-+	u16 duration = 0;
-+	u8 sequence = 0, aSifsTime = 0;
-+
-+
-+	RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra));
-+
-+	pxmitpriv = &adapter->xmitpriv;
-+	pmlmeext = &adapter->mlmeextpriv;
-+	info = GET_BEAMFORM_INFO(adapter);
-+	bfee = rtw_bf_bfee_get_entry_by_addr(adapter, ra);
-+	if (!bfee) {
-+		RTW_ERR("%s: Cann't find beamformee entry!\n", __FUNCTION__);
-+		return _FALSE;
-+	}
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (!pmgntframe) {
-+		RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
-+		return _FALSE;
-+	}
-+
-+	txrate = beamforming_get_vht_ndp_tx_rate(GET_PDM_ODM(adapter), bfee->comp_steering_num_of_bfer);
-+
-+	/* update attribute */
-+	attrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(adapter, attrib);
-+	/*pattrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
-+	attrib->subtype = WIFI_NDPA;
-+	attrib->bwmode = bw;
-+	/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
-+	attrib->rate = (u8)txrate;
-+	attrib->bf_pkt_type = 0;
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);
-+	pframe = pmgntframe->buf_addr + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	/* Frame control */
-+	pwlanhdr->frame_ctl = 0;
-+	set_frame_sub_type(pframe, attrib->subtype);
-+
-+	/* Duration */
-+	if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
-+		aSifsTime = 16;
-+	else
-+		aSifsTime = 10;
-+	duration = 2 * aSifsTime + 44;
-+	if (bw == CHANNEL_WIDTH_80)
-+		duration += 40;
-+	else if (bw == CHANNEL_WIDTH_40)
-+		duration += 87;
-+	else
-+		duration += 180;
-+	set_duration(pframe, duration);
-+
-+	/* RA */
-+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
-+
-+	/* TA */
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
-+
-+	/* Sounding Sequence, bit0~1 is reserved */
-+	sequence = info->sounding_sequence << 2;
-+	if (info->sounding_sequence >= 0x3f)
-+		info->sounding_sequence = 0;
-+	else
-+		info->sounding_sequence++;
-+	_rtw_memcpy(pframe + 16, &sequence, 1);
-+
-+	/* STA Info */
-+	/*
-+	 * "AID12" Equal to 0 if the STA is an AP, mesh STA or
-+	 * STA that is a member of an IBSS
-+	 */
-+	if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _FALSE)
-+		aid = 0;
-+	sta_info.aid = aid;
-+	/* "Feedback Type" set to 0 for SU */
-+	sta_info.feedback_type = 0;
-+	/* "Nc Index" reserved if the Feedback Type field indicates SU */
-+	sta_info.nc_index = 0;
-+	_rtw_memcpy(pframe + 17, (u8 *)&sta_info, 2);
-+
-+	attrib->pktlen = 19;
-+	attrib->last_txcmdsz = attrib->pktlen;
-+
-+	dump_mgntframe(adapter, pmgntframe);
-+
-+	return _TRUE;
-+}
-+
-+static u8 _send_vht_mu_ndpa_packet(PADAPTER adapter, enum channel_width bw)
-+{
-+	/* General */
-+	struct xmit_priv		*pxmitpriv;
-+	struct mlme_ext_priv		*pmlmeext;
-+	struct xmit_frame		*pmgntframe;
-+	/* Beamforming */
-+	struct beamforming_info		*info;
-+	struct sounding_info		*sounding;
-+	struct beamformee_entry		*bfee;
-+	struct ndpa_sta_info		sta_info;
-+	/* MISC */
-+	struct pkt_attrib		*attrib;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	enum MGN_RATE txrate;
-+	u8 *pframe;
-+	u8 *ra = NULL;
-+	u16 duration = 0;
-+	u8 sequence = 0, aSifsTime = 0;
-+	u8 i;
-+
-+
-+	RTW_INFO("+%s\n", __FUNCTION__);
-+
-+	pxmitpriv = &adapter->xmitpriv;
-+	pmlmeext = &adapter->mlmeextpriv;
-+	info = GET_BEAMFORM_INFO(adapter);
-+	sounding = &info->sounding_info;
-+
-+	txrate = MGN_VHT2SS_MCS0;
-+
-+	/*
-+	 * Fill the first MU BFee entry (STA1) MAC addr to destination address then
-+	 * HW will change A1 to broadcast addr.
-+	 * 2015.05.28. Suggested by SD1 Chunchu.
-+	 */
-+	bfee = &info->bfee_entry[sounding->mu_sounding_list[0]];
-+	ra = bfee->mac_addr;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (!pmgntframe) {
-+		RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
-+		return _FALSE;
-+	}
-+
-+	/* update attribute */
-+	attrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(adapter, attrib);
-+	/*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
-+	attrib->subtype = WIFI_NDPA;
-+	attrib->bwmode = bw;
-+	/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
-+	attrib->rate = (u8)txrate;
-+	/* Set TxBFPktType of Tx desc to unicast type if there is only one MU STA for HW design */
-+	if (info->sounding_info.candidate_mu_bfee_cnt > 1)
-+		attrib->bf_pkt_type = 1;
-+	else
-+		attrib->bf_pkt_type = 0;
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);
-+	pframe = pmgntframe->buf_addr + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	/* Frame control */
-+	pwlanhdr->frame_ctl = 0;
-+	set_frame_sub_type(pframe, attrib->subtype);
-+
-+	/* Duration */
-+	if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
-+		aSifsTime = 16;
-+	else
-+		aSifsTime = 10;
-+	duration = 2 * aSifsTime + 44;
-+	if (bw == CHANNEL_WIDTH_80)
-+		duration += 40;
-+	else if (bw == CHANNEL_WIDTH_40)
-+		duration += 87;
-+	else
-+		duration += 180;
-+	set_duration(pframe, duration);
-+
-+	/* RA */
-+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
-+
-+	/* TA */
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
-+
-+	/* Sounding Sequence, bit0~1 is reserved */
-+	sequence = info->sounding_sequence << 2;
-+	if (info->sounding_sequence >= 0x3f)
-+		info->sounding_sequence = 0;
-+	else
-+		info->sounding_sequence++;
-+	_rtw_memcpy(pframe + 16, &sequence, 1);
-+
-+	attrib->pktlen = 17;
-+
-+	/*
-+	 * Construct STA info. for multiple STAs
-+	 * STA Info1, ..., STA Info n
-+	 */
-+	for (i = 0; i < sounding->candidate_mu_bfee_cnt; i++) {
-+		bfee = &info->bfee_entry[sounding->mu_sounding_list[i]];
-+		sta_info.aid = bfee->aid;
-+		sta_info.feedback_type = 1; /* 1'b1: MU */
-+		sta_info.nc_index = 0;
-+		_rtw_memcpy(pframe + attrib->pktlen, (u8 *)&sta_info, 2);
-+		attrib->pktlen += 2;
-+	}
-+
-+	attrib->last_txcmdsz = attrib->pktlen;
-+
-+	dump_mgntframe(adapter, pmgntframe);
-+
-+	return _TRUE;
-+}
-+
-+static u8 _send_bf_report_poll(PADAPTER adapter, u8 *ra, u8 bFinalPoll)
-+{
-+	/* General */
-+	struct xmit_priv *pxmitpriv;
-+	struct xmit_frame *pmgntframe;
-+	/* MISC */
-+	struct pkt_attrib *attrib;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	u8 *pframe;
-+
-+
-+	RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra));
-+
-+	pxmitpriv = &adapter->xmitpriv;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (!pmgntframe) {
-+		RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
-+		return _FALSE;
-+	}
-+
-+	/* update attribute */
-+	attrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(adapter, attrib);
-+	/*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
-+	attrib->subtype = WIFI_BF_REPORT_POLL;
-+	attrib->bwmode = CHANNEL_WIDTH_20;
-+	/*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
-+	attrib->rate = MGN_6M;
-+	if (bFinalPoll)
-+		attrib->bf_pkt_type = 3;
-+	else
-+		attrib->bf_pkt_type = 2;
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);
-+	pframe = pmgntframe->buf_addr + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	/* Frame control */
-+	pwlanhdr->frame_ctl = 0;
-+	set_frame_sub_type(pframe, attrib->subtype);
-+
-+	/* Duration */
-+	set_duration(pframe, 100);
-+
-+	/* RA */
-+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
-+
-+	/* TA */
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
-+
-+	/* Feedback Segment Retransmission Bitmap */
-+	pframe[16] = 0xFF;
-+
-+	attrib->pktlen = 17;
-+	attrib->last_txcmdsz = attrib->pktlen;
-+
-+	dump_mgntframe(adapter, pmgntframe);
-+
-+	return _TRUE;
-+}
-+
-+static void _sounding_update_min_period(PADAPTER adapter, u16 period, u8 leave)
-+{
-+	struct beamforming_info *info;
-+	struct beamformee_entry *bfee;
-+	u8 i = 0;
-+	u16 min_val = 0xFFFF;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+
-+	if (_TRUE == leave) {
-+		/*
-+		 * When a BFee left,
-+		 * we need to find the latest min sounding period
-+		 * from the remaining BFees
-+		 */
-+		for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
-+			bfee = &info->bfee_entry[i];
-+			if ((bfee->used == _TRUE)
-+			    && (bfee->sound_period < min_val))
-+				min_val = bfee->sound_period;
-+		}
-+
-+		if (min_val == 0xFFFF)
-+			info->sounding_info.min_sounding_period = 0;
-+		else
-+			info->sounding_info.min_sounding_period = min_val;
-+	} else {
-+		if ((info->sounding_info.min_sounding_period == 0)
-+		    || (period < info->sounding_info.min_sounding_period))
-+			info->sounding_info.min_sounding_period = period;
-+	}
-+}
-+
-+static void _sounding_init(struct sounding_info *sounding)
-+{
-+	_rtw_memset(sounding->su_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_SU);
-+	_rtw_memset(sounding->mu_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_MU);
-+	sounding->state = SOUNDING_STATE_NONE;
-+	sounding->su_bfee_curidx = 0xFF;
-+	sounding->candidate_mu_bfee_cnt = 0;
-+	sounding->min_sounding_period = 0;
-+	sounding->sound_remain_cnt_per_period = 0;
-+}
-+
-+static void _sounding_reset_vars(PADAPTER adapter)
-+{
-+	struct beamforming_info	*info;
-+	struct sounding_info *sounding;
-+	u8 idx;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+	sounding = &info->sounding_info;
-+
-+	_rtw_memset(sounding->su_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_SU);
-+	_rtw_memset(sounding->mu_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_MU);
-+	sounding->su_bfee_curidx = 0xFF;
-+	sounding->candidate_mu_bfee_cnt = 0;
-+
-+	/* Clear bSound flag for the new period */
-+	for (idx = 0; idx < MAX_BEAMFORMEE_ENTRY_NUM; idx++) {
-+		if ((info->bfee_entry[idx].used == _TRUE)
-+		    && (info->bfee_entry[idx].sounding == _TRUE)) {
-+			info->bfee_entry[idx].sounding = _FALSE;
-+			info->bfee_entry[idx].bCandidateSoundingPeer = _FALSE;
-+		}
-+	}
-+}
-+
-+/*
-+ * Return
-+ *	0	Prepare sounding list OK
-+ *	-1	Fail to prepare sounding list, because no beamformee need to souding
-+ *	-2	Fail to prepare sounding list, because beamformee state not ready
-+ *
-+ */
-+static int _sounding_get_list(PADAPTER adapter)
-+{
-+	struct beamforming_info	*info;
-+	struct sounding_info *sounding;
-+	struct beamformee_entry *bfee;
-+	u8 i, mu_idx = 0, su_idx = 0, not_ready = 0;
-+	int ret = 0;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+	sounding = &info->sounding_info;
-+
-+	/* Add MU BFee list first because MU priority is higher than SU */
-+	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
-+		bfee = &info->bfee_entry[i];
-+		if (bfee->used == _FALSE)
-+			continue;
-+
-+		if (bfee->state != BEAMFORM_ENTRY_HW_STATE_ADDED) {
-+			RTW_ERR("%s: Invalid BFee idx(%d) Hw state=%d\n", __FUNCTION__, i, bfee->state);
-+			not_ready++;
-+			continue;
-+		}
-+
-+		/*
-+		 * Decrease BFee's SoundCnt per period
-+		 * If the remain count is 0,
-+		 * then it can be sounded at this time
-+		 */
-+		if (bfee->SoundCnt) {
-+			bfee->SoundCnt--;
-+			if (bfee->SoundCnt)
-+				continue;
-+		}
-+
-+		/*
-+		 * <tynli_Note>
-+		 *	If the STA supports MU BFee capability then we add it to MUSoundingList directly
-+		 *	because we can only sound one STA by unicast NDPA with MU cap enabled to get correct channel info.
-+		 *	Suggested by BB team Luke Lee. 2015.11.25.
-+		 */
-+		if (bfee->cap & BEAMFORMEE_CAP_VHT_MU) {
-+			/* MU BFee */
-+			if (mu_idx >= MAX_NUM_BEAMFORMEE_MU) {
-+				RTW_ERR("%s: Too much MU bfee entry(Limit:%d)\n", __FUNCTION__, MAX_NUM_BEAMFORMEE_MU);
-+				continue;
-+			}
-+
-+			if (bfee->bApplySounding == _TRUE) {
-+				bfee->bCandidateSoundingPeer = _TRUE;
-+				bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, sounding->min_sounding_period);
-+				sounding->mu_sounding_list[mu_idx] = i;
-+				mu_idx++;
-+			}
-+		} else if (bfee->cap & (BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {
-+			/* SU BFee (HT/VHT) */
-+			if (su_idx >= MAX_NUM_BEAMFORMEE_SU) {
-+				RTW_ERR("%s: Too much SU bfee entry(Limit:%d)\n", __FUNCTION__, MAX_NUM_BEAMFORMEE_SU);
-+				continue;
-+			}
-+
-+			if (bfee->bDeleteSounding == _TRUE) {
-+				sounding->su_sounding_list[su_idx] = i;
-+				su_idx++;
-+			} else if ((bfee->bApplySounding == _TRUE)
-+			    && (bfee->bSuspendSUCap == _FALSE)) {
-+				bfee->bCandidateSoundingPeer = _TRUE;
-+				bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, sounding->min_sounding_period);
-+				sounding->su_sounding_list[su_idx] = i;
-+				su_idx++;
-+			}
-+		}
-+	}
-+
-+	sounding->candidate_mu_bfee_cnt = mu_idx;
-+
-+	if (su_idx + mu_idx == 0) {
-+		ret = -1;
-+		if (not_ready)
-+			ret = -2;
-+	}
-+
-+	RTW_INFO("-%s: There are %d SU and %d MU BFees in this sounding period\n", __FUNCTION__, su_idx, mu_idx);
-+
-+	return ret;
-+}
-+
-+static void _sounding_handler(PADAPTER adapter)
-+{
-+	struct beamforming_info	*info;
-+	struct sounding_info *sounding;
-+	struct beamformee_entry *bfee;
-+	u8 su_idx, i;
-+	u32 timeout_period = 0;
-+	u8 set_timer = _FALSE;
-+	int ret = 0;
-+	static u16 wait_cnt = 0;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+	sounding = &info->sounding_info;
-+
-+	RTW_DBG("+%s: state=%d\n", __FUNCTION__, sounding->state);
-+	if ((sounding->state != SOUNDING_STATE_INIT)
-+	    && (sounding->state != SOUNDING_STATE_SU_SOUNDDOWN)
-+	    && (sounding->state != SOUNDING_STATE_MU_SOUNDDOWN)
-+	    && (sounding->state != SOUNDING_STATE_SOUNDING_TIMEOUT)) {
-+		RTW_WARN("%s: Invalid State(%d) and return!\n", __FUNCTION__, sounding->state);
-+		return;
-+	}
-+
-+	if (sounding->state == SOUNDING_STATE_INIT) {
-+		RTW_INFO("%s: Sounding start\n", __FUNCTION__);
-+
-+		/* Init Var */
-+		_sounding_reset_vars(adapter);
-+
-+		/* Get the sounding list of this sounding period */
-+		ret = _sounding_get_list(adapter);
-+		if (ret == -1) {
-+			wait_cnt = 0;
-+			sounding->state = SOUNDING_STATE_NONE;
-+			RTW_ERR("%s: No BFees found, set to SOUNDING_STATE_NONE\n", __FUNCTION__);
-+			info->sounding_running--;
-+			return;
-+		}
-+		if (ret == -2) {
-+			RTW_WARN("%s: Temporarily cann't find BFee to sounding\n", __FUNCTION__);
-+			if (wait_cnt < 5) {
-+				wait_cnt++;
-+			} else {
-+				wait_cnt = 0;
-+				sounding->state = SOUNDING_STATE_NONE;
-+				RTW_ERR("%s: Wait changing state timeout!! Set to SOUNDING_STATE_NONE\n", __FUNCTION__);
-+			}
-+			info->sounding_running--;
-+			return;
-+		}
-+		if (ret != 0) {
-+			wait_cnt = 0;
-+			RTW_ERR("%s: Unkown state(%d)!\n", __FUNCTION__, ret);
-+			info->sounding_running--;
-+			return;
-+
-+		}
-+
-+		wait_cnt = 0;
-+
-+		if (check_fwstate(&adapter->mlmepriv, WIFI_UNDER_SURVEY) == _TRUE) {
-+			RTW_INFO("%s: Sounding abort! scanning APs...\n", __FUNCTION__);
-+			info->sounding_running--;
-+			return;
-+		}
-+
-+		rtw_ps_deny(adapter, PS_DENY_BEAMFORMING);
-+		LeaveAllPowerSaveModeDirect(adapter);
-+	}
-+
-+	/* Get non-sound SU BFee index */
-+	for (i = 0; i < MAX_NUM_BEAMFORMEE_SU; i++) {
-+		su_idx = sounding->su_sounding_list[i];
-+		if (su_idx >= MAX_BEAMFORMEE_ENTRY_NUM)
-+			continue;
-+		bfee = &info->bfee_entry[su_idx];
-+		if (_FALSE == bfee->sounding)
-+			break;
-+	}
-+	if (i < MAX_NUM_BEAMFORMEE_SU) {
-+		sounding->su_bfee_curidx = su_idx;
-+		/* Set to sounding start state */
-+		sounding->state = SOUNDING_STATE_SU_START;
-+		RTW_DBG("%s: Set to SOUNDING_STATE_SU_START\n", __FUNCTION__);
-+
-+		bfee->sounding = _TRUE;
-+		/* Reset sounding timeout flag for the new sounding */
-+		bfee->bSoundingTimeout = _FALSE;
-+
-+		if (_TRUE == bfee->bDeleteSounding) {
-+			u8 res = _FALSE;
-+			rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 0);
-+			return;
-+		}
-+
-+		/* Start SU sounding */
-+		if (bfee->cap & BEAMFORMEE_CAP_VHT_SU)
-+			_send_vht_ndpa_packet(adapter, bfee->mac_addr, bfee->aid, bfee->sound_bw);
-+		else if (bfee->cap & BEAMFORMEE_CAP_HT_EXPLICIT)
-+			_send_ht_ndpa_packet(adapter, bfee->mac_addr, bfee->sound_bw);
-+
-+		/* Set sounding timeout timer */
-+		_set_timer(&info->sounding_timeout_timer, SU_SOUNDING_TIMEOUT);
-+		return;
-+	}
-+
-+	if (sounding->candidate_mu_bfee_cnt > 0) {
-+		/*
-+		 * If there is no SU BFee then find MU BFee and perform MU sounding
-+		 *
-+		 * <tynli_note> Need to check the MU starting condition. 2015.12.15.
-+		 */
-+		sounding->state = SOUNDING_STATE_MU_START;
-+		RTW_DBG("%s: Set to SOUNDING_STATE_MU_START\n", __FUNCTION__);
-+
-+		/* Update MU BFee info */
-+		for (i = 0; i < sounding->candidate_mu_bfee_cnt; i++) {
-+			bfee = &info->bfee_entry[sounding->mu_sounding_list[i]];
-+			bfee->sounding = _TRUE;
-+		}
-+
-+		/* Send MU NDPA */
-+		bfee = &info->bfee_entry[sounding->mu_sounding_list[0]];
-+		_send_vht_mu_ndpa_packet(adapter, bfee->sound_bw);
-+
-+		/* Send BF report poll if more than 1 MU STA */
-+		for (i = 1; i < sounding->candidate_mu_bfee_cnt; i++) {
-+			bfee = &info->bfee_entry[sounding->mu_sounding_list[i]];
-+
-+			if (i == (sounding->candidate_mu_bfee_cnt - 1))/* The last STA*/
-+				_send_bf_report_poll(adapter, bfee->mac_addr, _TRUE);
-+			else
-+				_send_bf_report_poll(adapter, bfee->mac_addr, _FALSE);
-+		}
-+
-+		sounding->candidate_mu_bfee_cnt = 0;
-+
-+		/* Set sounding timeout timer */
-+		_set_timer(&info->sounding_timeout_timer, MU_SOUNDING_TIMEOUT);
-+		return;
-+	}
-+
-+	info->sounding_running--;
-+	sounding->state = SOUNDING_STATE_INIT;
-+	RTW_INFO("%s: Sounding finished!\n", __FUNCTION__);
-+	rtw_ps_deny_cancel(adapter, PS_DENY_BEAMFORMING);
-+}
-+
-+static void _sounding_force_stop(PADAPTER adapter)
-+{
-+	struct beamforming_info	*info;
-+	struct sounding_info *sounding;
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+	sounding = &info->sounding_info;
-+
-+	if ((sounding->state == SOUNDING_STATE_SU_START)
-+	    || (sounding->state == SOUNDING_STATE_MU_START)) {
-+		u8 res = _FALSE;
-+		_cancel_timer_ex(&info->sounding_timeout_timer);
-+		rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 1);
-+		return;
-+	}
-+
-+	info->sounding_running--;
-+	sounding->state = SOUNDING_STATE_INIT;
-+	RTW_INFO("%s: Sounding finished!\n", __FUNCTION__);
-+	rtw_ps_deny_cancel(adapter, PS_DENY_BEAMFORMING);
-+}
-+
-+static void _sounding_timer_handler(void *FunctionContext)
-+{
-+	PADAPTER adapter;
-+	struct beamforming_info	*info;
-+	struct sounding_info *sounding;
-+	static u8 delay = 0;
-+
-+
-+	RTW_DBG("+%s\n", __FUNCTION__);
-+
-+	adapter = (PADAPTER)FunctionContext;
-+	info = GET_BEAMFORM_INFO(adapter);
-+	sounding = &info->sounding_info;
-+
-+	if (SOUNDING_STATE_NONE == sounding->state) {
-+		RTW_INFO("%s: Stop!\n", __FUNCTION__);
-+		if (info->sounding_running)
-+			RTW_WARN("%s: souding_running=%d when thread stop!\n",
-+				 __FUNCTION__, info->sounding_running);
-+		return;
-+	}
-+
-+	_set_timer(&info->sounding_timer, sounding->min_sounding_period);
-+
-+	if (!info->sounding_running) {
-+		if (SOUNDING_STATE_INIT != sounding->state) {
-+			RTW_WARN("%s: state(%d) != SOUNDING_STATE_INIT!!\n", __FUNCTION__, sounding->state);
-+			sounding->state = SOUNDING_STATE_INIT;
-+		}
-+		delay = 0;
-+		info->sounding_running++;
-+		rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 1);
-+	} else {
-+		if (delay != 0xFF)
-+			delay++;
-+		RTW_WARN("%s: souding is still processing...(state:%d, running:%d, delay:%d)\n",
-+			 __FUNCTION__, sounding->state, info->sounding_running, delay);
-+		if (delay > 3) {
-+			RTW_WARN("%s: Stop sounding!!\n", __FUNCTION__);
-+			_sounding_force_stop(adapter);
-+		}
-+	}
-+}
-+
-+static void _sounding_timeout_timer_handler(void *FunctionContext)
-+{
-+	PADAPTER adapter;
-+	struct beamforming_info	*info;
-+	struct sounding_info *sounding;
-+	struct beamformee_entry *bfee;
-+
-+
-+	RTW_WARN("+%s\n", __FUNCTION__);
-+
-+	adapter = (PADAPTER)FunctionContext;
-+	info = GET_BEAMFORM_INFO(adapter);
-+	sounding = &info->sounding_info;
-+
-+	if (SOUNDING_STATE_SU_START == sounding->state) {
-+		sounding->state = SOUNDING_STATE_SOUNDING_TIMEOUT;
-+		RTW_ERR("%s: Set to SU SOUNDING_STATE_SOUNDING_TIMEOUT\n", __FUNCTION__);
-+		/* SU BFee */
-+		bfee = &info->bfee_entry[sounding->su_bfee_curidx];
-+		bfee->bSoundingTimeout = _TRUE;
-+		RTW_WARN("%s: The BFee entry[%d] is Sounding Timeout!\n", __FUNCTION__, sounding->su_bfee_curidx);
-+	} else if (SOUNDING_STATE_MU_START == sounding->state) {
-+		sounding->state = SOUNDING_STATE_SOUNDING_TIMEOUT;
-+		RTW_ERR("%s: Set to MU SOUNDING_STATE_SOUNDING_TIMEOUT\n", __FUNCTION__);
-+	} else {
-+		RTW_WARN("%s: unexpected sounding state:0x%02x\n", __FUNCTION__, sounding->state);
-+		return;
-+	}
-+
-+	rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 1);
-+}
-+
-+static struct beamformer_entry *_bfer_get_free_entry(PADAPTER adapter)
-+{
-+	u8 i = 0;
-+	struct beamforming_info *info;
-+	struct beamformer_entry *bfer;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+
-+	for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {
-+		bfer = &info->bfer_entry[i];
-+		if (bfer->used == _FALSE)
-+			return bfer;
-+	}
-+
-+	return NULL;
-+}
-+
-+static struct beamformer_entry *_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra)
-+{
-+	u8 i = 0;
-+	struct beamforming_info *info;
-+	struct beamformer_entry *bfer;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+
-+	for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {
-+		bfer = &info->bfer_entry[i];
-+		if (bfer->used == _FALSE)
-+			continue;
-+		if (_rtw_memcmp(ra, bfer->mac_addr, ETH_ALEN) == _TRUE)
-+			return bfer;
-+	}
-+
-+	return NULL;
-+}
-+
-+static struct beamformer_entry *_bfer_add_entry(PADAPTER adapter,
-+	struct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering)
-+{
-+	struct mlme_priv *mlme;
-+	struct beamforming_info *info;
-+	struct beamformer_entry *bfer;
-+	u8 *bssid;
-+	u16 val16;
-+	u8 i;
-+
-+
-+	mlme = &adapter->mlmepriv;
-+	info = GET_BEAMFORM_INFO(adapter);
-+
-+	bfer = _bfer_get_entry_by_addr(adapter, sta->cmn.mac_addr);
-+	if (!bfer) {
-+		bfer = _bfer_get_free_entry(adapter);
-+		if (!bfer)
-+			return NULL;
-+	}
-+
-+	bfer->used = _TRUE;
-+	_get_txvector_parameter(adapter, sta, &bfer->g_id, &bfer->p_aid);
-+	_rtw_memcpy(bfer->mac_addr, sta->cmn.mac_addr, ETH_ALEN);
-+	bfer->cap = bf_cap;
-+	bfer->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT;
-+	bfer->NumofSoundingDim = sounding_dim;
-+
-+	if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_MU)) {
-+		info->beamformer_mu_cnt += 1;
-+		bfer->aid = sta->cmn.aid;
-+	} else if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) {
-+		info->beamformer_su_cnt += 1;
-+
-+		/* Record HW idx info */
-+		for (i = 0; i < MAX_NUM_BEAMFORMER_SU; i++) {
-+			if ((info->beamformer_su_reg_maping & BIT(i)) == 0) {
-+				info->beamformer_su_reg_maping |= BIT(i);
-+				bfer->su_reg_index = i;
-+				break;
-+			}
-+		}
-+		RTW_INFO("%s: Add BFer entry beamformer_su_reg_maping=%#x, su_reg_index=%d\n",
-+			 __FUNCTION__, info->beamformer_su_reg_maping, bfer->su_reg_index);
-+	}
-+
-+	return bfer;
-+}
-+
-+static void _bfer_remove_entry(PADAPTER adapter, struct beamformer_entry *entry)
-+{
-+	struct beamforming_info *info;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+
-+	entry->state = BEAMFORM_ENTRY_HW_STATE_DELETE_INIT;
-+
-+	if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_MU)) {
-+		info->beamformer_mu_cnt -= 1;
-+		_rtw_memset(entry->gid_valid, 0, 8);
-+		_rtw_memset(entry->user_position, 0, 16);
-+	} else if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) {
-+		info->beamformer_su_cnt -= 1;
-+	}
-+
-+	if (info->beamformer_mu_cnt == 0)
-+		info->beamforming_cap &= ~BEAMFORMEE_CAP_VHT_MU;
-+	if (info->beamformer_su_cnt == 0)
-+		info->beamforming_cap &= ~(BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT);
-+}
-+
-+static u8 _bfer_set_entry_gid(PADAPTER adapter, u8 *addr, u8 *gid, u8 *position)
-+{
-+	struct beamformer_entry bfer;
-+
-+	memset(&bfer, 0, sizeof(bfer));
-+	memcpy(bfer.mac_addr, addr, ETH_ALEN);
-+
-+	/* Parsing Membership Status Array */
-+	memcpy(bfer.gid_valid, gid, 8);
-+
-+	/* Parsing User Position Array */
-+	memcpy(bfer.user_position, position, 16);
-+
-+	/* Config HW GID table */
-+	rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_GID_TABLE, (u8 *) &bfer,
-+			sizeof(bfer), 1);
-+
-+	return _SUCCESS;
-+}
-+
-+static struct beamformee_entry *_bfee_get_free_entry(PADAPTER adapter)
-+{
-+	u8 i = 0;
-+	struct beamforming_info *info;
-+	struct beamformee_entry *bfee;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+
-+	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
-+		bfee = &info->bfee_entry[i];
-+		if (bfee->used == _FALSE)
-+			return bfee;
-+	}
-+
-+	return NULL;
-+}
-+
-+static struct beamformee_entry *_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra)
-+{
-+	u8 i = 0;
-+	struct beamforming_info *info;
-+	struct beamformee_entry *bfee;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+
-+	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
-+		bfee = &info->bfee_entry[i];
-+		if (bfee->used == _FALSE)
-+			continue;
-+		if (_rtw_memcmp(ra, bfee->mac_addr, ETH_ALEN) == _TRUE)
-+			return bfee;
-+	}
-+
-+	return NULL;
-+}
-+
-+static u8 _bfee_get_first_su_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore)
-+{
-+	struct beamforming_info *info;
-+	struct beamformee_entry *bfee;
-+	u8 i;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+
-+	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
-+		bfee = &info->bfee_entry[i];
-+		if (ignore && (bfee == ignore))
-+			continue;
-+		if (bfee->used == _FALSE)
-+			continue;
-+		if ((!TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU))
-+		    && TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT))
-+			return i;
-+	}
-+
-+	return 0xFF;
-+}
-+
-+/*
-+ * Description:
-+ *	Get the first entry index of MU Beamformee.
-+ *
-+ * Return Value:
-+ *	Index of the first MU sta, or 0xFF for invalid index.
-+ *
-+ * 2015.05.25. Created by tynli.
-+ *
-+ */
-+static u8 _bfee_get_first_mu_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore)
-+{
-+	struct beamforming_info *info;
-+	struct beamformee_entry *bfee;
-+	u8 i;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+
-+	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
-+		bfee = &info->bfee_entry[i];
-+		if (ignore && (bfee == ignore))
-+			continue;
-+		if (bfee->used == _FALSE)
-+			continue;
-+		if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU))
-+			return i;
-+	}
-+
-+	return 0xFF;
-+}
-+
-+static struct beamformee_entry *_bfee_add_entry(PADAPTER adapter,
-+	struct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering)
-+{
-+	struct mlme_priv *mlme;
-+	struct beamforming_info *info;
-+	struct beamformee_entry *bfee;
-+	u8 *bssid;
-+	u16 val16;
-+	u8 i;
-+
-+
-+	mlme = &adapter->mlmepriv;
-+	info = GET_BEAMFORM_INFO(adapter);
-+
-+	bfee = _bfee_get_entry_by_addr(adapter, sta->cmn.mac_addr);
-+	if (!bfee) {
-+		bfee = _bfee_get_free_entry(adapter);
-+		if (!bfee)
-+			return NULL;
-+	}
-+
-+	bfee->used = _TRUE;
-+	bfee->aid = sta->cmn.aid;
-+	bfee->mac_id = sta->cmn.mac_id;
-+	bfee->sound_bw = sta->cmn.bw_mode;
-+
-+	_get_txvector_parameter(adapter, sta, &bfee->g_id, &bfee->p_aid);
-+	sta->cmn.bf_info.g_id = bfee->g_id;
-+	sta->cmn.bf_info.p_aid = bfee->p_aid;
-+
-+	_rtw_memcpy(bfee->mac_addr, sta->cmn.mac_addr, ETH_ALEN);
-+	bfee->txbf = _FALSE;
-+	bfee->sounding = _FALSE;
-+	bfee->sound_period = 40;
-+	_sounding_update_min_period(adapter, bfee->sound_period, _FALSE);
-+	bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, info->sounding_info.min_sounding_period);
-+	bfee->cap = bf_cap;
-+	bfee->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT;
-+
-+	bfee->bCandidateSoundingPeer = _FALSE;
-+	bfee->bSoundingTimeout = _FALSE;
-+	bfee->bDeleteSounding = _FALSE;
-+	bfee->bApplySounding = _TRUE;
-+
-+	bfee->tx_timestamp = 0;
-+	bfee->tx_bytes = 0;
-+
-+	bfee->LogStatusFailCnt = 0;
-+	bfee->NumofSoundingDim = sounding_dim;
-+	bfee->comp_steering_num_of_bfer = comp_steering;
-+	bfee->bSuspendSUCap = _FALSE;
-+
-+	if (TEST_FLAG(bf_cap, BEAMFORMEE_CAP_VHT_MU)) {
-+		info->beamformee_mu_cnt += 1;
-+		info->first_mu_bfee_index = _bfee_get_first_mu_entry_idx(adapter, NULL);
-+
-+		if (_TRUE == info->bEnableSUTxBFWorkAround) {
-+			/* When the first MU BFee added, discard SU BFee bfee's capability */
-+			if ((info->beamformee_mu_cnt == 1) && (info->beamformee_su_cnt > 0)) {
-+				if (info->TargetSUBFee) {
-+					info->TargetSUBFee->bSuspendSUCap = _TRUE;
-+					info->TargetSUBFee->bDeleteSounding = _TRUE;
-+				} else {
-+					RTW_ERR("%s: UNEXPECTED!! info->TargetSUBFee is NULL!", __FUNCTION__);
-+				}
-+				info->TargetSUBFee = NULL;
-+				_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
-+				rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 0);
-+			}
-+		}
-+
-+		/* Record HW idx info */
-+		for (i = 0; i < MAX_NUM_BEAMFORMEE_MU; i++) {
-+			if ((info->beamformee_mu_reg_maping & BIT(i)) == 0) {
-+				info->beamformee_mu_reg_maping |= BIT(i);
-+				bfee->mu_reg_index = i;
-+				break;
-+			}
-+		}
-+		RTW_INFO("%s: Add BFee entry beamformee_mu_reg_maping=%#x, mu_reg_index=%d\n",
-+			 __FUNCTION__, info->beamformee_mu_reg_maping, bfee->mu_reg_index);
-+
-+	} else if (TEST_FLAG(bf_cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {
-+		info->beamformee_su_cnt += 1;
-+
-+		if (_TRUE == info->bEnableSUTxBFWorkAround) {
-+			/* Record the first SU BFee index. We only allow the first SU BFee to be sound */
-+			if ((info->beamformee_su_cnt == 1) && (info->beamformee_mu_cnt == 0)) {
-+				info->TargetSUBFee = bfee;
-+				_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
-+				bfee->bSuspendSUCap = _FALSE;
-+			} else {
-+				bfee->bSuspendSUCap = _TRUE;
-+			}
-+		}
-+
-+		/* Record HW idx info */
-+		for (i = 0; i < MAX_NUM_BEAMFORMEE_SU; i++) {
-+			if ((info->beamformee_su_reg_maping & BIT(i)) == 0) {
-+				info->beamformee_su_reg_maping |= BIT(i);
-+				bfee->su_reg_index = i;
-+				break;
-+			}
-+		}
-+		RTW_INFO("%s: Add BFee entry beamformee_su_reg_maping=%#x, su_reg_index=%d\n",
-+			 __FUNCTION__, info->beamformee_su_reg_maping, bfee->su_reg_index);
-+	}
-+
-+	return bfee;
-+}
-+
-+static void _bfee_remove_entry(PADAPTER adapter, struct beamformee_entry *entry)
-+{
-+	struct beamforming_info *info;
-+	u8 idx;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+
-+	entry->state = BEAMFORM_ENTRY_HW_STATE_DELETE_INIT;
-+
-+	if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_MU)) {
-+		info->beamformee_mu_cnt -= 1;
-+		info->first_mu_bfee_index = _bfee_get_first_mu_entry_idx(adapter, entry);
-+
-+		if (_TRUE == info->bEnableSUTxBFWorkAround) {
-+			if ((info->beamformee_mu_cnt == 0) && (info->beamformee_su_cnt > 0)) {
-+				idx = _bfee_get_first_su_entry_idx(adapter, NULL);
-+				info->TargetSUBFee = &info->bfee_entry[idx];
-+				_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
-+				info->TargetSUBFee->bSuspendSUCap = _FALSE;
-+			}
-+		}
-+	} else if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {
-+		info->beamformee_su_cnt -= 1;
-+
-+		/* When the target SU BFee leaves, disable workaround */
-+		if ((_TRUE == info->bEnableSUTxBFWorkAround)
-+		    && (entry == info->TargetSUBFee)) {
-+			entry->bSuspendSUCap = _TRUE;
-+			info->TargetSUBFee = NULL;
-+			_rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
-+			rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 0);
-+		}
-+	}
-+
-+	if (info->beamformee_mu_cnt == 0)
-+		info->beamforming_cap &= ~BEAMFORMER_CAP_VHT_MU;
-+	if (info->beamformee_su_cnt == 0)
-+		info->beamforming_cap &= ~(BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT);
-+
-+	_sounding_update_min_period(adapter, 0, _TRUE);
-+}
-+
-+static enum beamforming_cap _bfee_get_entry_cap_by_macid(PADAPTER adapter, u8 macid)
-+{
-+	struct beamforming_info *info;
-+	struct beamformee_entry *bfee;
-+	u8 i;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+
-+	for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {
-+		bfee = &info->bfee_entry[i];
-+		if (bfee->used == _FALSE)
-+			continue;
-+		if (bfee->mac_id == macid)
-+			return bfee->cap;
-+	}
-+
-+	return BEAMFORMING_CAP_NONE;
-+}
-+
-+static void _beamforming_enter(PADAPTER adapter, void *p)
-+{
-+	struct mlme_priv *mlme;
-+	struct ht_priv *htpriv;
-+#ifdef CONFIG_80211AC_VHT
-+	struct vht_priv *vhtpriv;
-+#endif
-+	struct mlme_ext_priv *mlme_ext;
-+	struct sta_info *sta, *sta_copy;
-+	struct beamforming_info *info;
-+	struct beamformer_entry *bfer = NULL;
-+	struct beamformee_entry *bfee = NULL;
-+	u8 wireless_mode;
-+	u8 sta_bf_cap;
-+	u8 sounding_dim = 0; /* number of sounding dimensions */
-+	u8 comp_steering_num = 0; /* compressed steering number */
-+
-+
-+	mlme = &adapter->mlmepriv;
-+	htpriv = &mlme->htpriv;
-+#ifdef CONFIG_80211AC_VHT
-+	vhtpriv = &mlme->vhtpriv;
-+#endif
-+	mlme_ext = &adapter->mlmeextpriv;
-+	info = GET_BEAMFORM_INFO(adapter);
-+
-+	sta_copy = (struct sta_info *)p;
-+	sta = rtw_get_stainfo(&adapter->stapriv, sta_copy->cmn.mac_addr);
-+	if (!sta) {
-+		RTW_ERR("%s: Cann't find STA info for " MAC_FMT "\n",
-+			__FUNCTION__, MAC_ARG(sta_copy->cmn.mac_addr));
-+		return;
-+	}
-+
-+	RTW_INFO("%s: find STA info for " MAC_FMT "\n",
-+		__FUNCTION__, MAC_ARG(sta_copy->cmn.mac_addr));
-+
-+	if (sta != sta_copy) {
-+		RTW_WARN("%s: Origin sta(fake)=%p realsta=%p for " MAC_FMT "\n",
-+		__FUNCTION__, sta_copy, sta, MAC_ARG(sta_copy->cmn.mac_addr));
-+	}
-+
-+	/* The current setting does not support Beaforming */
-+	wireless_mode = sta->wireless_mode;
-+	if ((is_supported_ht(wireless_mode) == _FALSE)
-+	    && (is_supported_vht(wireless_mode) == _FALSE)) {
-+		RTW_WARN("%s: Not support HT or VHT mode\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	if ((0 == htpriv->beamform_cap)
-+#ifdef CONFIG_80211AC_VHT
-+	    && (0 == vhtpriv->beamform_cap)
-+#endif
-+	   ) {
-+		RTW_INFO("The configuration disabled Beamforming! Skip...\n");
-+		return;
-+	}
-+
-+	_get_sta_beamform_cap(adapter, sta,
-+			      &sta_bf_cap, &sounding_dim, &comp_steering_num);
-+	RTW_INFO("STA Beamforming Capability=0x%02X\n", sta_bf_cap);
-+	if (sta_bf_cap == BEAMFORMING_CAP_NONE)
-+		return;
-+	if ((sta_bf_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
-+	    || (sta_bf_cap & BEAMFORMEE_CAP_VHT_SU)
-+	    || (sta_bf_cap & BEAMFORMEE_CAP_VHT_MU))
-+		sta_bf_cap |= BEAMFORMEE_CAP;
-+	if ((sta_bf_cap & BEAMFORMER_CAP_HT_EXPLICIT)
-+	    || (sta_bf_cap & BEAMFORMER_CAP_VHT_SU)
-+	    || (sta_bf_cap & BEAMFORMER_CAP_VHT_MU))
-+		sta_bf_cap |= BEAMFORMER_CAP;
-+
-+	if (sta_bf_cap & BEAMFORMER_CAP) {
-+		/* The other side is beamformer */
-+		bfer = _bfer_add_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num);
-+		if (!bfer)
-+			RTW_ERR("%s: Fail to allocate bfer entry!\n", __FUNCTION__);
-+	}
-+	if (sta_bf_cap & BEAMFORMEE_CAP) {
-+		/* The other side is beamformee */
-+		bfee = _bfee_add_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num);
-+		if (!bfee)
-+			RTW_ERR("%s: Fail to allocate bfee entry!\n", __FUNCTION__);
-+	}
-+	if (!bfer && !bfee)
-+		return;
-+
-+	rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_ENTER, (u8*)sta);
-+
-+	/* Perform sounding if there is BFee */
-+	if ((info->beamformee_su_cnt != 0)
-+	    || (info->beamformee_mu_cnt != 0)) {
-+		if (SOUNDING_STATE_NONE == info->sounding_info.state) {
-+			info->sounding_info.state = SOUNDING_STATE_INIT;
-+			/* Start sounding after 2 sec */
-+			_set_timer(&info->sounding_timer, 2000);
-+		}
-+	}
-+}
-+
-+static void _beamforming_reset(PADAPTER adapter)
-+{
-+	RTW_ERR("%s: Not ready!!\n", __FUNCTION__);
-+}
-+
-+static void _beamforming_leave(PADAPTER adapter, u8 *ra)
-+{
-+	struct beamforming_info *info;
-+	struct beamformer_entry *bfer = NULL;
-+	struct beamformee_entry *bfee = NULL;
-+	u8 bHwStateAddInit = _FALSE;
-+
-+
-+	RTW_INFO("+%s\n", __FUNCTION__);
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+	bfer = _bfer_get_entry_by_addr(adapter, ra);
-+	bfee = _bfee_get_entry_by_addr(adapter, ra);
-+
-+	if (!bfer && !bfee) {
-+		RTW_WARN("%s: " MAC_FMT " is neither beamforming ee or er!!\n",
-+			__FUNCTION__, MAC_ARG(ra));
-+		return;
-+	}
-+
-+	if (bfer)
-+		_bfer_remove_entry(adapter, bfer);
-+
-+	if (bfee)
-+		_bfee_remove_entry(adapter, bfee);
-+
-+	rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_LEAVE, ra);
-+
-+	/* Stop sounding if there is no any BFee */
-+	if ((info->beamformee_su_cnt == 0)
-+	    && (info->beamformee_mu_cnt == 0)) {
-+		_cancel_timer_ex(&info->sounding_timer);
-+		_sounding_init(&info->sounding_info);
-+	}
-+
-+	RTW_INFO("-%s\n", __FUNCTION__);
-+}
-+
-+static void _beamforming_sounding_down(PADAPTER adapter, u8 status)
-+{
-+	struct beamforming_info	*info;
-+	struct sounding_info *sounding;
-+	struct beamformee_entry *bfee;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+	sounding = &info->sounding_info;
-+
-+	RTW_INFO("+%s: sounding=%d, status=0x%02x\n", __FUNCTION__, sounding->state, status);
-+
-+	if (sounding->state == SOUNDING_STATE_MU_START) {
-+		RTW_INFO("%s: MU sounding done\n", __FUNCTION__);
-+		sounding->state = SOUNDING_STATE_MU_SOUNDDOWN;
-+		RTW_INFO("%s: Set to SOUNDING_STATE_MU_SOUNDDOWN\n", __FUNCTION__);
-+		info->SetHalSoundownOnDemandCnt++;
-+		rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);
-+	} else if (sounding->state == SOUNDING_STATE_SU_START) {
-+		RTW_INFO("%s: SU entry[%d] sounding down\n", __FUNCTION__, sounding->su_bfee_curidx);
-+		bfee = &info->bfee_entry[sounding->su_bfee_curidx];
-+		sounding->state = SOUNDING_STATE_SU_SOUNDDOWN;
-+		RTW_INFO("%s: Set to SOUNDING_STATE_SU_SOUNDDOWN\n", __FUNCTION__);
-+
-+		/*
-+		 * <tynli_note>
-+		 *	bfee->bSoundingTimeout this flag still cannot avoid
-+		 *	old sound down event happens in the new sounding period.
-+		 *	2015.12.10
-+		 */
-+		if (_TRUE == bfee->bSoundingTimeout) {
-+			RTW_WARN("%s: The entry[%d] is bSoundingTimeout!\n", __FUNCTION__, sounding->su_bfee_curidx);
-+			bfee->bSoundingTimeout = _FALSE;
-+			return;
-+		}
-+
-+		if (_TRUE == status) {
-+			/* success */
-+			bfee->LogStatusFailCnt = 0;
-+			info->SetHalSoundownOnDemandCnt++;
-+			rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);
-+		} else if (_TRUE == bfee->bDeleteSounding) {
-+			RTW_WARN("%s: Delete entry[%d] sounding info!\n", __FUNCTION__, sounding->su_bfee_curidx);
-+			rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);
-+			bfee->bDeleteSounding = _FALSE;
-+		} else {
-+			bfee->LogStatusFailCnt++;
-+			RTW_WARN("%s: LogStatusFailCnt=%d\n", __FUNCTION__, bfee->LogStatusFailCnt);
-+			if (bfee->LogStatusFailCnt > 30) {
-+				RTW_ERR("%s: LogStatusFailCnt > 30, Stop SOUNDING!!\n", __FUNCTION__);
-+				rtw_bf_cmd(adapter, BEAMFORMING_CTRL_LEAVE, bfee->mac_addr, ETH_ALEN, 1);
-+			}
-+		}
-+	} else {
-+		RTW_WARN("%s: unexpected sounding state:0x%02x\n", __FUNCTION__, sounding->state);
-+		return;
-+	}
-+
-+	rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 0);
-+}
-+
-+static void _c2h_snd_txbf(PADAPTER adapter, u8 *buf, u8 buf_len)
-+{
-+	struct beamforming_info	*info;
-+	u8 res;
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+
-+	_cancel_timer_ex(&info->sounding_timeout_timer);
-+
-+	res = C2H_SND_TXBF_GET_SND_RESULT(buf) ? _TRUE : _FALSE;
-+	RTW_INFO("+%s: %s\n", __FUNCTION__, res==_TRUE?"Success":"Fail!");
-+
-+	rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 1);
-+}
-+
-+/*
-+ * Description:
-+ *	This function is for phydm only
-+ */
-+enum beamforming_cap rtw_bf_bfee_get_entry_cap_by_macid(void *mlme, u8 macid)
-+{
-+	PADAPTER adapter;
-+	enum beamforming_cap cap = BEAMFORMING_CAP_NONE;
-+
-+
-+	adapter = mlme_to_adapter((struct mlme_priv *)mlme);
-+	cap = _bfee_get_entry_cap_by_macid(adapter, macid);
-+
-+	return cap;
-+}
-+
-+struct beamformer_entry *rtw_bf_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra)
-+{
-+	return _bfer_get_entry_by_addr(adapter, ra);
-+}
-+
-+struct beamformee_entry *rtw_bf_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra)
-+{
-+	return _bfee_get_entry_by_addr(adapter, ra);
-+}
-+
-+void rtw_bf_get_ndpa_packet(PADAPTER adapter, union recv_frame *precv_frame)
-+{
-+	RTW_DBG("+%s\n", __FUNCTION__);
-+}
-+
-+u32 rtw_bf_get_report_packet(PADAPTER adapter, union recv_frame *precv_frame)
-+{
-+	u32 ret = _SUCCESS;
-+	struct beamforming_info *info;
-+	struct beamformee_entry *bfee = NULL;
-+	u8 *pframe;
-+	u32 frame_len;
-+	u8 *ta;
-+	u8 *frame_body;
-+	u8 category, action;
-+	u8 *pMIMOCtrlField, *pCSIMatrix;
-+	u8 Nc = 0, Nr = 0, CH_W = 0, Ng = 0, CodeBook = 0;
-+	u16 CSIMatrixLen = 0;
-+
-+
-+	RTW_INFO("+%s\n", __FUNCTION__);
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+	pframe = precv_frame->u.hdr.rx_data;
-+	frame_len = precv_frame->u.hdr.len;
-+
-+	/* Memory comparison to see if CSI report is the same with previous one */
-+	ta = get_addr2_ptr(pframe);
-+	bfee = _bfee_get_entry_by_addr(adapter, ta);
-+	if (!bfee)
-+		return _FAIL;
-+
-+	frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	category = frame_body[0];
-+	action = frame_body[1];
-+
-+	if ((category == RTW_WLAN_CATEGORY_VHT)
-+	    && (action == RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING)) {
-+		pMIMOCtrlField = pframe + 26;
-+		Nc = (*pMIMOCtrlField) & 0x7;
-+		Nr = ((*pMIMOCtrlField) & 0x38) >> 3;
-+		CH_W =  (((*pMIMOCtrlField) & 0xC0) >> 6);
-+		Ng = (*(pMIMOCtrlField+1)) & 0x3;
-+		CodeBook = ((*(pMIMOCtrlField+1)) & 0x4) >> 2;
-+		/*
-+		 * 24+(1+1+3)+2
-+		 * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)
-+		 */
-+		pCSIMatrix = pMIMOCtrlField + 3 + Nc;
-+		CSIMatrixLen = frame_len - 26 - 3 - Nc;
-+		info->TargetCSIInfo.bVHT = _TRUE;
-+	} else if ((category == RTW_WLAN_CATEGORY_HT)
-+		   && (action == RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING)) {
-+		pMIMOCtrlField = pframe + 26;
-+		Nc = (*pMIMOCtrlField) & 0x3;
-+		Nr = ((*pMIMOCtrlField) & 0xC) >> 2;
-+		CH_W = ((*pMIMOCtrlField) & 0x10) >> 4;
-+		Ng = ((*pMIMOCtrlField) & 0x60) >> 5;
-+		CodeBook = ((*(pMIMOCtrlField+1)) & 0x6) >> 1;
-+		/*
-+		 * 24+(1+1+6)+2
-+		 * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)
-+		 */
-+		pCSIMatrix = pMIMOCtrlField + 6 + Nr;
-+		CSIMatrixLen = frame_len  - 26 - 6 - Nr;
-+		info->TargetCSIInfo.bVHT = _FALSE;
-+	}
-+
-+	/* Update current CSI report info */
-+	if ((_TRUE == info->bEnableSUTxBFWorkAround)
-+	    && (info->TargetSUBFee == bfee)) {
-+		if ((info->TargetCSIInfo.Nc != Nc) || (info->TargetCSIInfo.Nr != Nr) ||
-+			(info->TargetCSIInfo.ChnlWidth != CH_W) || (info->TargetCSIInfo.Ng != Ng) ||
-+			(info->TargetCSIInfo.CodeBook != CodeBook)) {
-+			info->TargetCSIInfo.Nc = Nc;
-+			info->TargetCSIInfo.Nr = Nr;
-+			info->TargetCSIInfo.ChnlWidth = CH_W;
-+			info->TargetCSIInfo.Ng = Ng;
-+			info->TargetCSIInfo.CodeBook = CodeBook;
-+
-+			rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 1);
-+		}
-+	}
-+
-+	RTW_INFO("%s: pkt type=%d-%d, Nc=%d, Nr=%d, CH_W=%d, Ng=%d, CodeBook=%d\n",
-+		 __FUNCTION__, category, action, Nc, Nr, CH_W, Ng, CodeBook);
-+
-+	return ret;
-+}
-+
-+u8 rtw_bf_send_vht_gid_mgnt_packet(PADAPTER adapter, u8 *ra, u8 *gid, u8 *position)
-+{
-+	/* General */
-+	struct xmit_priv *xmitpriv;
-+	struct mlme_priv *mlmepriv;
-+	struct xmit_frame *pmgntframe;
-+	/* MISC */
-+	struct pkt_attrib *attrib;
-+	struct rtw_ieee80211_hdr *wlanhdr;
-+	u8 *pframe, *ptr;
-+
-+
-+	xmitpriv = &adapter->xmitpriv;
-+	mlmepriv = &adapter->mlmepriv;
-+
-+	pmgntframe = alloc_mgtxmitframe(xmitpriv);
-+	if (!pmgntframe)
-+		return _FALSE;
-+
-+	/* update attribute */
-+	attrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(adapter, attrib);
-+	attrib->rate = MGN_6M;
-+	attrib->bwmode = CHANNEL_WIDTH_20;
-+	attrib->subtype = WIFI_ACTION;
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)pmgntframe->buf_addr + TXDESC_OFFSET;
-+	wlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	wlanhdr->frame_ctl = 0;
-+	set_frame_sub_type(pframe, attrib->subtype);
-+	set_duration(pframe, 0);
-+	SetFragNum(pframe, 0);
-+	SetSeqNum(pframe, 0);
-+
-+	_rtw_memcpy(wlanhdr->addr1, ra, ETH_ALEN);
-+	_rtw_memcpy(wlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
-+	_rtw_memcpy(wlanhdr->addr3, get_bssid(mlmepriv), ETH_ALEN);
-+
-+	pframe[24] = RTW_WLAN_CATEGORY_VHT;
-+	pframe[25] = RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT;
-+	/* Set Membership Status Array */
-+	ptr = pframe + 26;
-+	_rtw_memcpy(ptr, gid, 8);
-+	/* Set User Position Array */
-+	ptr = pframe + 34;
-+	_rtw_memcpy(ptr, position, 16);
-+
-+	attrib->pktlen = 54;
-+	attrib->last_txcmdsz = attrib->pktlen;
-+
-+	dump_mgntframe(adapter, pmgntframe);
-+
-+	return _TRUE;
-+}
-+
-+/*
-+ * Description:
-+ *	On VHT GID management frame by an MU beamformee.
-+ */
-+void rtw_bf_get_vht_gid_mgnt_packet(PADAPTER adapter, union recv_frame *precv_frame)
-+{
-+	u8 *pframe;
-+	u8 *ta, *gid, *position;
-+
-+
-+	RTW_DBG("+%s\n", __FUNCTION__);
-+
-+	pframe = precv_frame->u.hdr.rx_data;
-+
-+	/* Get address by Addr2 */
-+	ta = get_addr2_ptr(pframe);
-+	/* Remove signaling TA */
-+	ta[0] &= 0xFE;
-+
-+	/* Membership Status Array */
-+	gid = pframe + 26;
-+	/* User Position Array */
-+	position= pframe + 34;
-+
-+	_bfer_set_entry_gid(adapter, ta, gid, position);
-+}
-+
-+void rtw_bf_init(PADAPTER adapter)
-+{
-+	struct beamforming_info	*info;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+	info->beamforming_cap = BEAMFORMING_CAP_NONE;
-+	info->beamforming_state = BEAMFORMING_STATE_IDLE;
-+/*
-+	info->bfee_entry[MAX_BEAMFORMEE_ENTRY_NUM];
-+	info->bfer_entry[MAX_BEAMFORMER_ENTRY_NUM];
-+*/
-+	info->sounding_sequence = 0;
-+	info->beamformee_su_cnt = 0;
-+	info->beamformer_su_cnt = 0;
-+	info->beamformee_su_reg_maping = 0;
-+	info->beamformer_su_reg_maping = 0;
-+	info->beamformee_mu_cnt = 0;
-+	info->beamformer_mu_cnt = 0;
-+	info->beamformee_mu_reg_maping = 0;
-+	info->first_mu_bfee_index = 0xFF;
-+	info->mu_bfer_curidx = 0xFF;
-+	info->cur_csi_rpt_rate = HALMAC_OFDM24;
-+
-+	_sounding_init(&info->sounding_info);
-+	rtw_init_timer(&info->sounding_timer, adapter, _sounding_timer_handler, adapter);
-+	rtw_init_timer(&info->sounding_timeout_timer, adapter, _sounding_timeout_timer_handler, adapter);
-+
-+	info->SetHalBFEnterOnDemandCnt = 0;
-+	info->SetHalBFLeaveOnDemandCnt = 0;
-+	info->SetHalSoundownOnDemandCnt = 0;
-+
-+	info->bEnableSUTxBFWorkAround = _TRUE;
-+	info->TargetSUBFee = NULL;
-+
-+	info->sounding_running = 0;
-+}
-+
-+void rtw_bf_cmd_hdl(PADAPTER adapter, u8 type, u8 *pbuf)
-+{
-+	switch (type) {
-+	case BEAMFORMING_CTRL_ENTER:
-+		_beamforming_enter(adapter, pbuf);
-+		break;
-+
-+	case BEAMFORMING_CTRL_LEAVE:
-+		if (pbuf == NULL)
-+			_beamforming_reset(adapter);
-+		else
-+			_beamforming_leave(adapter, pbuf);
-+		break;
-+
-+	case BEAMFORMING_CTRL_START_PERIOD:
-+		_sounding_handler(adapter);
-+		break;
-+
-+	case BEAMFORMING_CTRL_END_PERIOD:
-+		_beamforming_sounding_down(adapter, *pbuf);
-+		break;
-+
-+	case BEAMFORMING_CTRL_SET_GID_TABLE:
-+		rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_SET_GID_TABLE, pbuf);
-+		break;
-+
-+	case BEAMFORMING_CTRL_SET_CSI_REPORT:
-+		rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_CSI_REPORT, pbuf);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+u8 rtw_bf_cmd(PADAPTER adapter, s32 type, u8 *pbuf, s32 size, u8 enqueue)
-+{
-+	struct cmd_obj *ph2c;
-+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
-+	struct cmd_priv	*pcmdpriv = &adapter->cmdpriv;
-+	u8 *wk_buf;
-+	u8 res = _SUCCESS;
-+
-+
-+	if (!enqueue) {
-+		rtw_bf_cmd_hdl(adapter, type, pbuf);
-+		goto exit;
-+	}
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	if (pbuf != NULL) {
-+		wk_buf = rtw_zmalloc(size);
-+		if (wk_buf == NULL) {
-+			rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
-+			rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		_rtw_memcpy(wk_buf, pbuf, size);
-+	} else {
-+		wk_buf = NULL;
-+		size = 0;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = BEAMFORMING_WK_CID;
-+	pdrvextra_cmd_parm->type = type;
-+	pdrvextra_cmd_parm->size = size;
-+	pdrvextra_cmd_parm->pbuf = wk_buf;
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+	return res;
-+}
-+
-+void rtw_bf_update_attrib(PADAPTER adapter, struct pkt_attrib *attrib, struct sta_info *sta)
-+{
-+	if (sta) {
-+		attrib->txbf_g_id = sta->cmn.bf_info.g_id;
-+		attrib->txbf_p_aid = sta->cmn.bf_info.p_aid;
-+	}
-+}
-+
-+void rtw_bf_c2h_handler(PADAPTER adapter, u8 id, u8 *buf, u8 buf_len)
-+{
-+	switch (id) {
-+	case CMD_ID_C2H_SND_TXBF:
-+		_c2h_snd_txbf(adapter, buf, buf_len);
-+		break;
-+	}
-+}
-+
-+#define toMbps(bytes, secs)	(rtw_division64(bytes >> 17, secs))
-+void rtw_bf_update_traffic(PADAPTER adapter)
-+{
-+	struct beamforming_info	*info;
-+	struct sounding_info *sounding;
-+	struct beamformee_entry *bfee;
-+	struct sta_info *sta;
-+	u8 bfee_cnt, sounding_idx, i;
-+	u16 tp[MAX_BEAMFORMEE_ENTRY_NUM] = {0};
-+	u8 tx_rate[MAX_BEAMFORMEE_ENTRY_NUM] = {0};
-+	u64 tx_bytes, last_bytes;
-+	u32 time;
-+	systime last_timestamp;
-+	u8 set_timer = _FALSE;
-+
-+
-+	info = GET_BEAMFORM_INFO(adapter);
-+	sounding = &info->sounding_info;
-+
-+	/* Check any bfee exist? */
-+	bfee_cnt = info->beamformee_su_cnt + info->beamformee_mu_cnt;
-+	if (bfee_cnt == 0)
-+		return;
-+
-+	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
-+		bfee = &info->bfee_entry[i];
-+		if (_FALSE == bfee->used)
-+			continue;
-+
-+		sta = rtw_get_stainfo(&adapter->stapriv, bfee->mac_addr);
-+		if (!sta) {
-+			RTW_ERR("%s: Cann't find sta_info for " MAC_FMT "!\n", __FUNCTION__, MAC_ARG(bfee->mac_addr));
-+			continue;
-+		}
-+
-+		last_timestamp = bfee->tx_timestamp;
-+		last_bytes = bfee->tx_bytes;
-+		bfee->tx_timestamp = rtw_get_current_time();
-+		bfee->tx_bytes = sta->sta_stats.tx_bytes;
-+		if (last_timestamp) {
-+			if (bfee->tx_bytes >= last_bytes)
-+				tx_bytes = bfee->tx_bytes - last_bytes;
-+			else
-+				tx_bytes = bfee->tx_bytes + (~last_bytes);
-+			time = rtw_get_time_interval_ms(last_timestamp, bfee->tx_timestamp);
-+			time = (time > 1000) ? time/1000 : 1;
-+			tp[i] = toMbps(tx_bytes, time);
-+			tx_rate[i] = rtw_get_current_tx_rate(adapter, sta);
-+			RTW_INFO("%s: BFee idx(%d), MadId(%d), TxTP=%lld bytes (%d Mbps), txrate=%d\n",
-+				 __FUNCTION__, i, bfee->mac_id, tx_bytes, tp[i], tx_rate[i]);
-+		}
-+	}
-+
-+	sounding_idx = phydm_get_beamforming_sounding_info(GET_PDM_ODM(adapter), tp, MAX_BEAMFORMEE_ENTRY_NUM, tx_rate);
-+
-+	for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
-+		bfee = &info->bfee_entry[i];
-+		if (_FALSE == bfee->used) {
-+			if (sounding_idx & BIT(i))
-+				RTW_WARN("%s: bfee(%d) not in used but need sounding?!\n", __FUNCTION__, i);
-+			continue;
-+		}
-+
-+		if (sounding_idx & BIT(i)) {
-+			if (_FALSE == bfee->bApplySounding) {
-+				bfee->bApplySounding = _TRUE;
-+				bfee->SoundCnt = 0;
-+				set_timer = _TRUE;
-+			}
-+		} else {
-+			if (_TRUE == bfee->bApplySounding) {
-+				bfee->bApplySounding = _FALSE;
-+				bfee->bDeleteSounding = _TRUE;
-+				bfee->SoundCnt = 0;
-+				set_timer = _TRUE;
-+			}
-+		}
-+	}
-+
-+	if (_TRUE == set_timer) {
-+		if (SOUNDING_STATE_NONE == info->sounding_info.state) {
-+			info->sounding_info.state = SOUNDING_STATE_INIT;
-+			_set_timer(&info->sounding_timer, 0);
-+		}
-+	}
-+}
-+
-+#else /* !RTW_BEAMFORMING_VERSION_2 */
-+
-+/*PHYDM_BF - (BEAMFORMING_SUPPORT == 1)*/
-+u32	rtw_beamforming_get_report_frame(PADAPTER	 Adapter, union recv_frame *precv_frame)
-+{
-+	u32	ret = _SUCCESS;
-+
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
-+
-+	ret = beamforming_get_report_frame(pDM_Odm, precv_frame);
-+	return ret;
-+}
-+
-+void	rtw_beamforming_get_ndpa_frame(PADAPTER	 Adapter, union recv_frame *precv_frame)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
-+
-+	beamforming_get_ndpa_frame(pDM_Odm, precv_frame);
-+}
-+
-+void	beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
-+
-+	/*(BEAMFORMING_SUPPORT == 1)- for PHYDM beamfoming*/
-+	switch (type) {
-+	case BEAMFORMING_CTRL_ENTER: {
-+		struct sta_info	*psta = (void *)pbuf;
-+		u16			staIdx = psta->cmn.mac_id;
-+
-+		beamforming_enter(pDM_Odm, staIdx, adapter_mac_addr(psta->padapter));
-+		break;
-+	}
-+	case BEAMFORMING_CTRL_LEAVE:
-+		beamforming_leave(pDM_Odm, pbuf);
-+		break;
-+	default:
-+		break;
-+
-+	}
-+}
-+
-+u8	beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue)
-+{
-+	struct cmd_obj	*ph2c;
-+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8	res = _SUCCESS;
-+
-+	/*20170214 ad_hoc mode and mp_mode not support BF*/
-+	if ((padapter->registrypriv.mp_mode == 1)
-+		|| (pmlmeinfo->state == WIFI_FW_ADHOC_STATE))
-+		return res;
-+
-+	if (enqueue) {
-+		u8	*wk_buf;
-+
-+		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+		if (ph2c == NULL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+		if (pdrvextra_cmd_parm == NULL) {
-+			rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		if (pbuf != NULL) {
-+			wk_buf = rtw_zmalloc(size);
-+			if (wk_buf == NULL) {
-+				rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
-+				rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
-+				res = _FAIL;
-+				goto exit;
-+			}
-+
-+			_rtw_memcpy(wk_buf, pbuf, size);
-+		} else {
-+			wk_buf = NULL;
-+			size = 0;
-+		}
-+
-+		pdrvextra_cmd_parm->ec_id = BEAMFORMING_WK_CID;
-+		pdrvextra_cmd_parm->type = type;
-+		pdrvextra_cmd_parm->size = size;
-+		pdrvextra_cmd_parm->pbuf = wk_buf;
-+
-+		init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+	} else
-+		beamforming_wk_hdl(padapter, type, pbuf);
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta)
-+{
-+	if (psta) {
-+		pattrib->txbf_g_id = psta->cmn.bf_info.g_id;
-+		pattrib->txbf_p_aid = psta->cmn.bf_info.p_aid;
-+	}
-+}
-+#endif /* !RTW_BEAMFORMING_VERSION_2 */
-+
-+#endif /* CONFIG_BEAMFORMING */
-diff --git a/drivers/staging/rtl8723cs/core/rtw_br_ext.c b/drivers/staging/rtl8723cs/core/rtw_br_ext.c
-new file mode 100644
-index 000000000000..4251b825c8ae
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_br_ext.c
-@@ -0,0 +1,1308 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_BR_EXT_C_
-+
-+#ifdef __KERNEL__
-+	#include <linux/if_arp.h>
-+	#include <net/ip.h>
-+	#include <linux/udp.h>
-+	#include <linux/if_pppox.h>
-+#endif
-+
-+#if 1	/* rtw_wifi_driver */
-+	#include <drv_types.h>
-+#else	/* rtw_wifi_driver */
-+	#include "./8192cd_cfg.h"
-+
-+	#ifndef __KERNEL__
-+		#include "./sys-support.h"
-+	#endif
-+
-+	#include "./8192cd.h"
-+	#include "./8192cd_headers.h"
-+	#include "./8192cd_br_ext.h"
-+	#include "./8192cd_debug.h"
-+#endif /* rtw_wifi_driver */
-+
-+#ifdef CL_IPV6_PASS
-+	#ifdef __KERNEL__
-+		#include <linux/ipv6.h>
-+		#include <linux/icmpv6.h>
-+		#include <net/ndisc.h>
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
-+			#include <net/ip6_checksum.h>
-+		#else
-+			#include <net/checksum.h>
-+		#endif
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_BR_EXT
-+
-+/* #define BR_EXT_DEBUG */
-+
-+#define NAT25_IPV4		01
-+#define NAT25_IPV6		02
-+#define NAT25_PPPOE		05
-+
-+#define RTL_RELAY_TAG_LEN (ETH_ALEN)
-+#define TAG_HDR_LEN		4
-+
-+#define MAGIC_CODE		0x8186
-+#define MAGIC_CODE_LEN	2
-+#define WAIT_TIME_PPPOE	5	/* waiting time for pppoe server in sec */
-+
-+/*-----------------------------------------------------------------
-+  How database records network address:
-+           0    1    2    3    4    5    6    7    8    9   10
-+        |----|----|----|----|----|----|----|----|----|----|----|
-+  IPv4  |type|                             |      IP addr      |
-+  Apple |type| Network |node|
-+  PPPoE |type|   SID   |           AC MAC            |
-+-----------------------------------------------------------------*/
-+
-+
-+/* Find a tag in pppoe frame and return the pointer */
-+static __inline__ unsigned char *__nat25_find_pppoe_tag(struct pppoe_hdr *ph, unsigned short type)
-+{
-+	unsigned char *cur_ptr, *start_ptr;
-+	unsigned short tagLen, tagType;
-+
-+	start_ptr = cur_ptr = (unsigned char *)ph->tag;
-+	while ((cur_ptr - start_ptr) < ntohs(ph->length)) {
-+		/* prevent un-alignment access */
-+		tagType = (unsigned short)((cur_ptr[0] << 8) + cur_ptr[1]);
-+		tagLen  = (unsigned short)((cur_ptr[2] << 8) + cur_ptr[3]);
-+		if (tagType == type)
-+			return cur_ptr;
-+		cur_ptr = cur_ptr + TAG_HDR_LEN + tagLen;
-+	}
-+	return 0;
-+}
-+
-+
-+static __inline__ int __nat25_add_pppoe_tag(struct sk_buff *skb, struct pppoe_tag *tag)
-+{
-+	struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN);
-+	int data_len;
-+
-+	data_len = tag->tag_len + TAG_HDR_LEN;
-+	if (skb_tailroom(skb) < data_len) {
-+		_DEBUG_ERR("skb_tailroom() failed in add SID tag!\n");
-+		return -1;
-+	}
-+
-+	skb_put(skb, data_len);
-+	/* have a room for new tag */
-+	memmove(((unsigned char *)ph->tag + data_len), (unsigned char *)ph->tag, ntohs(ph->length));
-+	ph->length = htons(ntohs(ph->length) + data_len);
-+	memcpy((unsigned char *)ph->tag, tag, data_len);
-+	return data_len;
-+}
-+
-+static int skb_pull_and_merge(struct sk_buff *skb, unsigned char *src, int len)
-+{
-+	int tail_len;
-+	unsigned long end, tail;
-+
-+	if ((src + len) > skb_tail_pointer(skb) || skb->len < len)
-+		return -1;
-+
-+	tail = (unsigned long)skb_tail_pointer(skb);
-+	end = (unsigned long)src + len;
-+	if (tail < end)
-+		return -1;
-+
-+	tail_len = (int)(tail - end);
-+	if (tail_len > 0)
-+		memmove(src, src + len, tail_len);
-+
-+	skb_trim(skb, skb->len - len);
-+	return 0;
-+}
-+
-+static __inline__ unsigned long __nat25_timeout(_adapter *priv)
-+{
-+	unsigned long timeout;
-+
-+	timeout = jiffies - NAT25_AGEING_TIME * HZ;
-+
-+	return timeout;
-+}
-+
-+
-+static __inline__ int  __nat25_has_expired(_adapter *priv,
-+		struct nat25_network_db_entry *fdb)
-+{
-+	if (time_before_eq(fdb->ageing_timer, __nat25_timeout(priv)))
-+		return 1;
-+
-+	return 0;
-+}
-+
-+
-+static __inline__ void __nat25_generate_ipv4_network_addr(unsigned char *networkAddr,
-+		unsigned int *ipAddr)
-+{
-+	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
-+
-+	networkAddr[0] = NAT25_IPV4;
-+	memcpy(networkAddr + 7, (unsigned char *)ipAddr, 4);
-+}
-+
-+
-+static __inline__ void __nat25_generate_pppoe_network_addr(unsigned char *networkAddr,
-+		unsigned char *ac_mac, unsigned short *sid)
-+{
-+	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
-+
-+	networkAddr[0] = NAT25_PPPOE;
-+	memcpy(networkAddr + 1, (unsigned char *)sid, 2);
-+	memcpy(networkAddr + 3, (unsigned char *)ac_mac, 6);
-+}
-+
-+
-+#ifdef CL_IPV6_PASS
-+static  void __nat25_generate_ipv6_network_addr(unsigned char *networkAddr,
-+		unsigned int *ipAddr)
-+{
-+	memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN);
-+
-+	networkAddr[0] = NAT25_IPV6;
-+	memcpy(networkAddr + 1, (unsigned char *)ipAddr, 16);
-+}
-+
-+
-+static unsigned char *scan_tlv(unsigned char *data, int len, unsigned char tag, unsigned char len8b)
-+{
-+	while (len > 0) {
-+		if (*data == tag && *(data + 1) == len8b && len >= len8b * 8)
-+			return data + 2;
-+
-+		len -= (*(data + 1)) * 8;
-+		data += (*(data + 1)) * 8;
-+	}
-+	return NULL;
-+}
-+
-+
-+static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char *replace_mac)
-+{
-+	struct icmp6hdr *icmphdr = (struct icmp6hdr *)data;
-+	unsigned char *mac;
-+
-+	if (icmphdr->icmp6_type == NDISC_ROUTER_SOLICITATION) {
-+		if (len >= 8) {
-+			mac = scan_tlv(&data[8], len - 8, 1, 1);
-+			if (mac) {
-+				RTW_INFO("Router Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
-+					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
-+					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
-+				memcpy(mac, replace_mac, 6);
-+				return 1;
-+			}
-+		}
-+	} else if (icmphdr->icmp6_type == NDISC_ROUTER_ADVERTISEMENT) {
-+		if (len >= 16) {
-+			mac = scan_tlv(&data[16], len - 16, 1, 1);
-+			if (mac) {
-+				RTW_INFO("Router Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
-+					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
-+					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
-+				memcpy(mac, replace_mac, 6);
-+				return 1;
-+			}
-+		}
-+	} else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_SOLICITATION) {
-+		if (len >= 24) {
-+			mac = scan_tlv(&data[24], len - 24, 1, 1);
-+			if (mac) {
-+				RTW_INFO("Neighbor Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
-+					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
-+					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
-+				memcpy(mac, replace_mac, 6);
-+				return 1;
-+			}
-+		}
-+	} else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_ADVERTISEMENT) {
-+		if (len >= 24) {
-+			mac = scan_tlv(&data[24], len - 24, 2, 1);
-+			if (mac) {
-+				RTW_INFO("Neighbor Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
-+					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
-+					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
-+				memcpy(mac, replace_mac, 6);
-+				return 1;
-+			}
-+		}
-+	} else if (icmphdr->icmp6_type == NDISC_REDIRECT) {
-+		if (len >= 40) {
-+			mac = scan_tlv(&data[40], len - 40, 2, 1);
-+			if (mac) {
-+				RTW_INFO("Redirect,  replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n",
-+					mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
-+					replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]);
-+				memcpy(mac, replace_mac, 6);
-+				return 1;
-+			}
-+		}
-+	}
-+	return 0;
-+}
-+
-+#ifdef SUPPORT_RX_UNI2MCAST
-+static void convert_ipv6_mac_to_mc(struct sk_buff *skb)
-+{
-+	struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN);
-+	unsigned char *dst_mac = skb->data;
-+
-+	/* dst_mac[0] = 0xff; */
-+	/* dst_mac[1] = 0xff; */
-+	/*modified by qinjunjie,ipv6 multicast address ix 0x33-33-xx-xx-xx-xx*/
-+	dst_mac[0] = 0x33;
-+	dst_mac[1] = 0x33;
-+	memcpy(&dst_mac[2], &iph->daddr.s6_addr32[3], 4);
-+#if defined(__LINUX_2_6__)
-+	/*modified by qinjunjie,warning:should not remove next line*/
-+	skb->pkt_type = PACKET_MULTICAST;
-+#endif
-+}
-+#endif /* CL_IPV6_PASS */
-+#endif /* SUPPORT_RX_UNI2MCAST */
-+
-+
-+static __inline__ int __nat25_network_hash(unsigned char *networkAddr)
-+{
-+	if (networkAddr[0] == NAT25_IPV4) {
-+		unsigned long x;
-+
-+		x = networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10];
-+
-+		return x & (NAT25_HASH_SIZE - 1);
-+	} else if (networkAddr[0] == NAT25_PPPOE) {
-+		unsigned long x;
-+
-+		x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8];
-+
-+		return x & (NAT25_HASH_SIZE - 1);
-+	}
-+#ifdef CL_IPV6_PASS
-+	else if (networkAddr[0] == NAT25_IPV6) {
-+		unsigned long x;
-+
-+		x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^
-+		    networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10] ^
-+		    networkAddr[11] ^ networkAddr[12] ^ networkAddr[13] ^ networkAddr[14] ^ networkAddr[15] ^
-+		    networkAddr[16];
-+
-+		return x & (NAT25_HASH_SIZE - 1);
-+	}
-+#endif
-+	else {
-+		unsigned long x = 0;
-+		int i;
-+
-+		for (i = 0; i < MAX_NETWORK_ADDR_LEN; i++)
-+			x ^= networkAddr[i];
-+
-+		return x & (NAT25_HASH_SIZE - 1);
-+	}
-+}
-+
-+
-+static __inline__ void __network_hash_link(_adapter *priv,
-+		struct nat25_network_db_entry *ent, int hash)
-+{
-+	/* Caller must _enter_critical_bh already! */
-+	/* _irqL irqL; */
-+	/* _enter_critical_bh(&priv->br_ext_lock, &irqL); */
-+
-+	ent->next_hash = priv->nethash[hash];
-+	if (ent->next_hash != NULL)
-+		ent->next_hash->pprev_hash = &ent->next_hash;
-+	priv->nethash[hash] = ent;
-+	ent->pprev_hash = &priv->nethash[hash];
-+
-+	/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */
-+}
-+
-+
-+static __inline__ void __network_hash_unlink(struct nat25_network_db_entry *ent)
-+{
-+	/* Caller must _enter_critical_bh already! */
-+	/* _irqL irqL; */
-+	/* _enter_critical_bh(&priv->br_ext_lock, &irqL); */
-+
-+	*(ent->pprev_hash) = ent->next_hash;
-+	if (ent->next_hash != NULL)
-+		ent->next_hash->pprev_hash = ent->pprev_hash;
-+	ent->next_hash = NULL;
-+	ent->pprev_hash = NULL;
-+
-+	/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */
-+}
-+
-+
-+static int __nat25_db_network_lookup_and_replace(_adapter *priv,
-+		struct sk_buff *skb, unsigned char *networkAddr)
-+{
-+	struct nat25_network_db_entry *db;
-+	_irqL irqL;
-+	_enter_critical_bh(&priv->br_ext_lock, &irqL);
-+
-+	db = priv->nethash[__nat25_network_hash(networkAddr)];
-+	while (db != NULL) {
-+		if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) {
-+			if (!__nat25_has_expired(priv, db)) {
-+				/* replace the destination mac address */
-+				memcpy(skb->data, db->macAddr, ETH_ALEN);
-+				atomic_inc(&db->use_count);
-+
-+#ifdef CL_IPV6_PASS
-+				RTW_INFO("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
-+					 "%02x%02x%02x%02x%02x%02x\n",
-+					 db->macAddr[0],
-+					 db->macAddr[1],
-+					 db->macAddr[2],
-+					 db->macAddr[3],
-+					 db->macAddr[4],
-+					 db->macAddr[5],
-+					 db->networkAddr[0],
-+					 db->networkAddr[1],
-+					 db->networkAddr[2],
-+					 db->networkAddr[3],
-+					 db->networkAddr[4],
-+					 db->networkAddr[5],
-+					 db->networkAddr[6],
-+					 db->networkAddr[7],
-+					 db->networkAddr[8],
-+					 db->networkAddr[9],
-+					 db->networkAddr[10],
-+					 db->networkAddr[11],
-+					 db->networkAddr[12],
-+					 db->networkAddr[13],
-+					 db->networkAddr[14],
-+					 db->networkAddr[15],
-+					 db->networkAddr[16]);
-+#else
-+				RTW_INFO("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
-+					 db->macAddr[0],
-+					 db->macAddr[1],
-+					 db->macAddr[2],
-+					 db->macAddr[3],
-+					 db->macAddr[4],
-+					 db->macAddr[5],
-+					 db->networkAddr[0],
-+					 db->networkAddr[1],
-+					 db->networkAddr[2],
-+					 db->networkAddr[3],
-+					 db->networkAddr[4],
-+					 db->networkAddr[5],
-+					 db->networkAddr[6],
-+					 db->networkAddr[7],
-+					 db->networkAddr[8],
-+					 db->networkAddr[9],
-+					 db->networkAddr[10]);
-+#endif
-+			}
-+			_exit_critical_bh(&priv->br_ext_lock, &irqL);
-+			return 1;
-+		}
-+
-+		db = db->next_hash;
-+	}
-+
-+	_exit_critical_bh(&priv->br_ext_lock, &irqL);
-+	return 0;
-+}
-+
-+
-+static void __nat25_db_network_insert(_adapter *priv,
-+		      unsigned char *macAddr, unsigned char *networkAddr)
-+{
-+	struct nat25_network_db_entry *db;
-+	int hash;
-+	_irqL irqL;
-+	_enter_critical_bh(&priv->br_ext_lock, &irqL);
-+
-+	hash = __nat25_network_hash(networkAddr);
-+	db = priv->nethash[hash];
-+	while (db != NULL) {
-+		if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) {
-+			memcpy(db->macAddr, macAddr, ETH_ALEN);
-+			db->ageing_timer = jiffies;
-+			_exit_critical_bh(&priv->br_ext_lock, &irqL);
-+			return;
-+		}
-+
-+		db = db->next_hash;
-+	}
-+
-+	db = (struct nat25_network_db_entry *) rtw_malloc(sizeof(*db));
-+	if (db == NULL) {
-+		_exit_critical_bh(&priv->br_ext_lock, &irqL);
-+		return;
-+	}
-+
-+	memcpy(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN);
-+	memcpy(db->macAddr, macAddr, ETH_ALEN);
-+	atomic_set(&db->use_count, 1);
-+	db->ageing_timer = jiffies;
-+
-+	__network_hash_link(priv, db, hash);
-+
-+	_exit_critical_bh(&priv->br_ext_lock, &irqL);
-+}
-+
-+
-+static void __nat25_db_print(_adapter *priv)
-+{
-+	_irqL irqL;
-+	_enter_critical_bh(&priv->br_ext_lock, &irqL);
-+
-+#ifdef BR_EXT_DEBUG
-+	static int counter = 0;
-+	int i, j;
-+	struct nat25_network_db_entry *db;
-+
-+	counter++;
-+	if ((counter % 16) != 0)
-+		return;
-+
-+	for (i = 0, j = 0; i < NAT25_HASH_SIZE; i++) {
-+		db = priv->nethash[i];
-+
-+		while (db != NULL) {
-+#ifdef CL_IPV6_PASS
-+			panic_printk("NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
-+				     "%02x%02x%02x%02x%02x%02x\n",
-+				     j,
-+				     i,
-+				     atomic_read(&db->use_count),
-+				     db->macAddr[0],
-+				     db->macAddr[1],
-+				     db->macAddr[2],
-+				     db->macAddr[3],
-+				     db->macAddr[4],
-+				     db->macAddr[5],
-+				     db->networkAddr[0],
-+				     db->networkAddr[1],
-+				     db->networkAddr[2],
-+				     db->networkAddr[3],
-+				     db->networkAddr[4],
-+				     db->networkAddr[5],
-+				     db->networkAddr[6],
-+				     db->networkAddr[7],
-+				     db->networkAddr[8],
-+				     db->networkAddr[9],
-+				     db->networkAddr[10],
-+				     db->networkAddr[11],
-+				     db->networkAddr[12],
-+				     db->networkAddr[13],
-+				     db->networkAddr[14],
-+				     db->networkAddr[15],
-+				     db->networkAddr[16]);
-+#else
-+			panic_printk("NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
-+				     j,
-+				     i,
-+				     atomic_read(&db->use_count),
-+				     db->macAddr[0],
-+				     db->macAddr[1],
-+				     db->macAddr[2],
-+				     db->macAddr[3],
-+				     db->macAddr[4],
-+				     db->macAddr[5],
-+				     db->networkAddr[0],
-+				     db->networkAddr[1],
-+				     db->networkAddr[2],
-+				     db->networkAddr[3],
-+				     db->networkAddr[4],
-+				     db->networkAddr[5],
-+				     db->networkAddr[6],
-+				     db->networkAddr[7],
-+				     db->networkAddr[8],
-+				     db->networkAddr[9],
-+				     db->networkAddr[10]);
-+#endif
-+			j++;
-+
-+			db = db->next_hash;
-+		}
-+	}
-+#endif
-+
-+	_exit_critical_bh(&priv->br_ext_lock, &irqL);
-+}
-+
-+
-+
-+
-+/*
-+ *	NAT2.5 interface
-+ */
-+
-+void nat25_db_cleanup(_adapter *priv)
-+{
-+	int i;
-+	_irqL irqL;
-+	_enter_critical_bh(&priv->br_ext_lock, &irqL);
-+
-+	for (i = 0; i < NAT25_HASH_SIZE; i++) {
-+		struct nat25_network_db_entry *f;
-+		f = priv->nethash[i];
-+		while (f != NULL) {
-+			struct nat25_network_db_entry *g;
-+
-+			g = f->next_hash;
-+			if (priv->scdb_entry == f) {
-+				memset(priv->scdb_mac, 0, ETH_ALEN);
-+				memset(priv->scdb_ip, 0, 4);
-+				priv->scdb_entry = NULL;
-+			}
-+			__network_hash_unlink(f);
-+			rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry));
-+
-+			f = g;
-+		}
-+	}
-+
-+	_exit_critical_bh(&priv->br_ext_lock, &irqL);
-+}
-+
-+
-+void nat25_db_expire(_adapter *priv)
-+{
-+	int i;
-+	_irqL irqL;
-+	_enter_critical_bh(&priv->br_ext_lock, &irqL);
-+
-+	/* if(!priv->ethBrExtInfo.nat25_disable) */
-+	{
-+		for (i = 0; i < NAT25_HASH_SIZE; i++) {
-+			struct nat25_network_db_entry *f;
-+			f = priv->nethash[i];
-+
-+			while (f != NULL) {
-+				struct nat25_network_db_entry *g;
-+				g = f->next_hash;
-+
-+				if (__nat25_has_expired(priv, f)) {
-+					if (atomic_dec_and_test(&f->use_count)) {
-+#ifdef BR_EXT_DEBUG
-+#ifdef CL_IPV6_PASS
-+						panic_printk("NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
-+							"%02x%02x%02x%02x%02x%02x\n",
-+							     i,
-+							     f->macAddr[0],
-+							     f->macAddr[1],
-+							     f->macAddr[2],
-+							     f->macAddr[3],
-+							     f->macAddr[4],
-+							     f->macAddr[5],
-+							     f->networkAddr[0],
-+							     f->networkAddr[1],
-+							     f->networkAddr[2],
-+							     f->networkAddr[3],
-+							     f->networkAddr[4],
-+							     f->networkAddr[5],
-+							     f->networkAddr[6],
-+							     f->networkAddr[7],
-+							     f->networkAddr[8],
-+							     f->networkAddr[9],
-+							     f->networkAddr[10],
-+							     f->networkAddr[11],
-+							     f->networkAddr[12],
-+							     f->networkAddr[13],
-+							     f->networkAddr[14],
-+							     f->networkAddr[15],
-+							f->networkAddr[16]);
-+#else
-+
-+						panic_printk("NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
-+							     i,
-+							     f->macAddr[0],
-+							     f->macAddr[1],
-+							     f->macAddr[2],
-+							     f->macAddr[3],
-+							     f->macAddr[4],
-+							     f->macAddr[5],
-+							     f->networkAddr[0],
-+							     f->networkAddr[1],
-+							     f->networkAddr[2],
-+							     f->networkAddr[3],
-+							     f->networkAddr[4],
-+							     f->networkAddr[5],
-+							     f->networkAddr[6],
-+							     f->networkAddr[7],
-+							     f->networkAddr[8],
-+							     f->networkAddr[9],
-+							f->networkAddr[10]);
-+#endif
-+#endif
-+						if (priv->scdb_entry == f) {
-+							memset(priv->scdb_mac, 0, ETH_ALEN);
-+							memset(priv->scdb_ip, 0, 4);
-+							priv->scdb_entry = NULL;
-+						}
-+						__network_hash_unlink(f);
-+						rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry));
-+					}
-+				}
-+
-+				f = g;
-+			}
-+		}
-+	}
-+
-+	_exit_critical_bh(&priv->br_ext_lock, &irqL);
-+}
-+
-+
-+#ifdef SUPPORT_TX_MCAST2UNI
-+static int checkIPMcAndReplace(_adapter *priv, struct sk_buff *skb, unsigned int *dst_ip)
-+{
-+	struct stat_info	*pstat;
-+	struct list_head	*phead, *plist;
-+	int i;
-+
-+	phead = &priv->asoc_list;
-+	plist = phead->next;
-+
-+	while (plist != phead) {
-+		pstat = list_entry(plist, struct stat_info, asoc_list);
-+		plist = plist->next;
-+
-+		if (pstat->ipmc_num == 0)
-+			continue;
-+
-+		for (i = 0; i < MAX_IP_MC_ENTRY; i++) {
-+			if (pstat->ipmc[i].used && !memcmp(&pstat->ipmc[i].mcmac[3], ((unsigned char *)dst_ip) + 1, 3)) {
-+				memcpy(skb->data, pstat->ipmc[i].mcmac, ETH_ALEN);
-+				return 1;
-+			}
-+		}
-+	}
-+	return 0;
-+}
-+#endif
-+
-+int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method)
-+{
-+	unsigned short protocol;
-+	unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
-+
-+	if (skb == NULL)
-+		return -1;
-+
-+	if ((method <= NAT25_MIN) || (method >= NAT25_MAX))
-+		return -1;
-+
-+	protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN));
-+
-+	/*---------------------------------------------------*/
-+	/*                 Handle IP frame                  */
-+	/*---------------------------------------------------*/
-+	if (protocol == __constant_htons(ETH_P_IP)) {
-+		struct iphdr *iph = (struct iphdr *)(skb->data + ETH_HLEN);
-+
-+		if (((unsigned char *)(iph) + (iph->ihl << 2)) >= (skb->data + ETH_HLEN + skb->len)) {
-+			DEBUG_WARN("NAT25: malformed IP packet !\n");
-+			return -1;
-+		}
-+
-+		switch (method) {
-+		case NAT25_CHECK:
-+			return -1;
-+
-+		case NAT25_INSERT: {
-+			/* some muticast with source IP is all zero, maybe other case is illegal */
-+			/* in class A, B, C, host address is all zero or all one is illegal */
-+			if (iph->saddr == 0)
-+				return 0;
-+			RTW_INFO("NAT25: Insert IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr);
-+			__nat25_generate_ipv4_network_addr(networkAddr, &iph->saddr);
-+			/* record source IP address and , source mac address into db */
-+			__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
-+
-+			__nat25_db_print(priv);
-+		}
-+		return 0;
-+
-+		case NAT25_LOOKUP: {
-+			RTW_INFO("NAT25: Lookup IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr);
-+#ifdef SUPPORT_TX_MCAST2UNI
-+			if (priv->pshare->rf_ft_var.mc2u_disable ||
-+			    ((((OPMODE & (WIFI_STATION_STATE | WIFI_ASOC_STATE))
-+			       == (WIFI_STATION_STATE | WIFI_ASOC_STATE)) &&
-+			      !checkIPMcAndReplace(priv, skb, &iph->daddr)) ||
-+			     (OPMODE & WIFI_ADHOC_STATE)))
-+#endif
-+			{
-+				__nat25_generate_ipv4_network_addr(networkAddr, &iph->daddr);
-+
-+				if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) {
-+					if (*((unsigned char *)&iph->daddr + 3) == 0xff) {
-+						/* L2 is unicast but L3 is broadcast, make L2 bacome broadcast */
-+						RTW_INFO("NAT25: Set DA as boardcast\n");
-+						memset(skb->data, 0xff, ETH_ALEN);
-+					} else {
-+						/* forward unknow IP packet to upper TCP/IP */
-+						RTW_INFO("NAT25: Replace DA with BR's MAC\n");
-+						if ((*(u32 *)priv->br_mac) == 0 && (*(u16 *)(priv->br_mac + 4)) == 0) {
-+							void netdev_br_init(struct net_device *netdev);
-+							printk("Re-init netdev_br_init() due to br_mac==0!\n");
-+							netdev_br_init(priv->pnetdev);
-+						}
-+						memcpy(skb->data, priv->br_mac, ETH_ALEN);
-+					}
-+				}
-+			}
-+		}
-+		return 0;
-+
-+		default:
-+			return -1;
-+		}
-+	}
-+
-+	/*---------------------------------------------------*/
-+	/*                 Handle ARP frame                 */
-+	/*---------------------------------------------------*/
-+	else if (protocol == __constant_htons(ETH_P_ARP)) {
-+		struct arphdr *arp = (struct arphdr *)(skb->data + ETH_HLEN);
-+		unsigned char *arp_ptr = (unsigned char *)(arp + 1);
-+		unsigned int *sender, *target;
-+
-+		if (arp->ar_pro != __constant_htons(ETH_P_IP)) {
-+			DEBUG_WARN("NAT25: arp protocol unknown (%4x)!\n", htons(arp->ar_pro));
-+			return -1;
-+		}
-+
-+		switch (method) {
-+		case NAT25_CHECK:
-+			return 0;	/* skb_copy for all ARP frame */
-+
-+		case NAT25_INSERT: {
-+			RTW_INFO("NAT25: Insert ARP, MAC=%02x%02x%02x%02x%02x%02x\n", arp_ptr[0],
-+				arp_ptr[1], arp_ptr[2], arp_ptr[3], arp_ptr[4], arp_ptr[5]);
-+
-+			/* change to ARP sender mac address to wlan STA address */
-+			memcpy(arp_ptr, GET_MY_HWADDR(priv), ETH_ALEN);
-+
-+			arp_ptr += arp->ar_hln;
-+			sender = (unsigned int *)arp_ptr;
-+
-+			__nat25_generate_ipv4_network_addr(networkAddr, sender);
-+
-+			__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
-+
-+			__nat25_db_print(priv);
-+		}
-+		return 0;
-+
-+		case NAT25_LOOKUP: {
-+			RTW_INFO("NAT25: Lookup ARP\n");
-+
-+			arp_ptr += arp->ar_hln;
-+			sender = (unsigned int *)arp_ptr;
-+			arp_ptr += (arp->ar_hln + arp->ar_pln);
-+			target = (unsigned int *)arp_ptr;
-+
-+			__nat25_generate_ipv4_network_addr(networkAddr, target);
-+
-+			__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
-+
-+			/* change to ARP target mac address to Lookup result */
-+			arp_ptr = (unsigned char *)(arp + 1);
-+			arp_ptr += (arp->ar_hln + arp->ar_pln);
-+			memcpy(arp_ptr, skb->data, ETH_ALEN);
-+		}
-+		return 0;
-+
-+		default:
-+			return -1;
-+		}
-+	}
-+
-+	/*---------------------------------------------------*/
-+	/*                Handle PPPoE frame                */
-+	/*---------------------------------------------------*/
-+	else if ((protocol == __constant_htons(ETH_P_PPP_DISC)) ||
-+		 (protocol == __constant_htons(ETH_P_PPP_SES))) {
-+		struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN);
-+		unsigned short *pMagic;
-+
-+		switch (method) {
-+		case NAT25_CHECK:
-+			if (ph->sid == 0)
-+				return 0;
-+			return 1;
-+
-+		case NAT25_INSERT:
-+			if (ph->sid == 0) {	/* Discovery phase according to tag */
-+				if (ph->code == PADI_CODE || ph->code == PADR_CODE) {
-+					if (priv->ethBrExtInfo.addPPPoETag) {
-+						struct pppoe_tag *tag, *pOldTag;
-+						unsigned char tag_buf[40];
-+						int old_tag_len = 0;
-+
-+						tag = (struct pppoe_tag *)tag_buf;
-+						pOldTag = (struct pppoe_tag *)__nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID));
-+						if (pOldTag) { /* if SID existed, copy old value and delete it */
-+							old_tag_len = ntohs(pOldTag->tag_len);
-+							if (old_tag_len + TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN > sizeof(tag_buf)) {
-+								DEBUG_ERR("SID tag length too long!\n");
-+								return -1;
-+							}
-+
-+							memcpy(tag->tag_data + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN,
-+							       pOldTag->tag_data, old_tag_len);
-+
-+							if (skb_pull_and_merge(skb, (unsigned char *)pOldTag, TAG_HDR_LEN + old_tag_len) < 0) {
-+								DEBUG_ERR("call skb_pull_and_merge() failed in PADI/R packet!\n");
-+								return -1;
-+							}
-+							ph->length = htons(ntohs(ph->length) - TAG_HDR_LEN - old_tag_len);
-+						}
-+
-+						tag->tag_type = PTT_RELAY_SID;
-+						tag->tag_len = htons(MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN + old_tag_len);
-+
-+						/* insert the magic_code+client mac in relay tag */
-+						pMagic = (unsigned short *)tag->tag_data;
-+						*pMagic = htons(MAGIC_CODE);
-+						memcpy(tag->tag_data + MAGIC_CODE_LEN, skb->data + ETH_ALEN, ETH_ALEN);
-+
-+						/* Add relay tag */
-+						if (__nat25_add_pppoe_tag(skb, tag) < 0)
-+							return -1;
-+
-+						RTW_INFO("NAT25: Insert PPPoE, forward %s packet\n",
-+							(ph->code == PADI_CODE ? "PADI" : "PADR"));
-+					} else { /* not add relay tag */
-+						if (priv->pppoe_connection_in_progress &&
-+						    memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN))	 {
-+							DEBUG_ERR("Discard PPPoE packet due to another PPPoE connection is in progress!\n");
-+							return -2;
-+						}
-+
-+						if (priv->pppoe_connection_in_progress == 0)
-+							memcpy(priv->pppoe_addr, skb->data + ETH_ALEN, ETH_ALEN);
-+
-+						priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE;
-+					}
-+				} else
-+					return -1;
-+			} else {	/* session phase */
-+				RTW_INFO("NAT25: Insert PPPoE, insert session packet to %s\n", skb->dev->name);
-+
-+				__nat25_generate_pppoe_network_addr(networkAddr, skb->data, &(ph->sid));
-+
-+				__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
-+
-+				__nat25_db_print(priv);
-+
-+				if (!priv->ethBrExtInfo.addPPPoETag &&
-+				    priv->pppoe_connection_in_progress &&
-+				    !memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN))
-+					priv->pppoe_connection_in_progress = 0;
-+			}
-+			return 0;
-+
-+		case NAT25_LOOKUP:
-+			if (ph->code == PADO_CODE || ph->code == PADS_CODE) {
-+				if (priv->ethBrExtInfo.addPPPoETag) {
-+					struct pppoe_tag *tag;
-+					unsigned char *ptr;
-+					unsigned short tagType, tagLen;
-+					int offset = 0;
-+
-+					ptr = __nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID));
-+					if (ptr == 0) {
-+						DEBUG_ERR("Fail to find PTT_RELAY_SID in FADO!\n");
-+						return -1;
-+					}
-+
-+					tag = (struct pppoe_tag *)ptr;
-+					tagType = (unsigned short)((ptr[0] << 8) + ptr[1]);
-+					tagLen = (unsigned short)((ptr[2] << 8) + ptr[3]);
-+
-+					if ((tagType != ntohs(PTT_RELAY_SID)) || (tagLen < (MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN))) {
-+						DEBUG_ERR("Invalid PTT_RELAY_SID tag length [%d]!\n", tagLen);
-+						return -1;
-+					}
-+
-+					pMagic = (unsigned short *)tag->tag_data;
-+					if (ntohs(*pMagic) != MAGIC_CODE) {
-+						DEBUG_ERR("Can't find MAGIC_CODE in %s packet!\n",
-+							(ph->code == PADO_CODE ? "PADO" : "PADS"));
-+						return -1;
-+					}
-+
-+					memcpy(skb->data, tag->tag_data + MAGIC_CODE_LEN, ETH_ALEN);
-+
-+					if (tagLen > MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN)
-+						offset = TAG_HDR_LEN;
-+
-+					if (skb_pull_and_merge(skb, ptr + offset, TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN - offset) < 0) {
-+						DEBUG_ERR("call skb_pull_and_merge() failed in PADO packet!\n");
-+						return -1;
-+					}
-+					ph->length = htons(ntohs(ph->length) - (TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN - offset));
-+					if (offset > 0)
-+						tag->tag_len = htons(tagLen - MAGIC_CODE_LEN - RTL_RELAY_TAG_LEN);
-+
-+					RTW_INFO("NAT25: Lookup PPPoE, forward %s Packet from %s\n",
-+						(ph->code == PADO_CODE ? "PADO" : "PADS"),	skb->dev->name);
-+				} else { /* not add relay tag */
-+					if (!priv->pppoe_connection_in_progress) {
-+						DEBUG_ERR("Discard PPPoE packet due to no connection in progresss!\n");
-+						return -1;
-+					}
-+					memcpy(skb->data, priv->pppoe_addr, ETH_ALEN);
-+					priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE;
-+				}
-+			} else {
-+				if (ph->sid != 0) {
-+					RTW_INFO("NAT25: Lookup PPPoE, lookup session packet from %s\n", skb->dev->name);
-+					__nat25_generate_pppoe_network_addr(networkAddr, skb->data + ETH_ALEN, &(ph->sid));
-+
-+					__nat25_db_network_lookup_and_replace(priv, skb, networkAddr);
-+
-+					__nat25_db_print(priv);
-+				} else
-+					return -1;
-+
-+			}
-+			return 0;
-+
-+		default:
-+			return -1;
-+		}
-+	}
-+
-+	/*---------------------------------------------------*/
-+	/*                 Handle EAP frame                 */
-+	/*---------------------------------------------------*/
-+	else if (protocol == __constant_htons(0x888e)) {
-+		switch (method) {
-+		case NAT25_CHECK:
-+			return -1;
-+
-+		case NAT25_INSERT:
-+			return 0;
-+
-+		case NAT25_LOOKUP:
-+			return 0;
-+
-+		default:
-+			return -1;
-+		}
-+	}
-+
-+	/*---------------------------------------------------*/
-+	/*         Handle C-Media proprietary frame         */
-+	/*---------------------------------------------------*/
-+	else if ((protocol == __constant_htons(0xe2ae)) ||
-+		 (protocol == __constant_htons(0xe2af))) {
-+		switch (method) {
-+		case NAT25_CHECK:
-+			return -1;
-+
-+		case NAT25_INSERT:
-+			return 0;
-+
-+		case NAT25_LOOKUP:
-+			return 0;
-+
-+		default:
-+			return -1;
-+		}
-+	}
-+
-+	/*---------------------------------------------------*/
-+	/*         Handle IPV6 frame      							 */
-+	/*---------------------------------------------------*/
-+#ifdef CL_IPV6_PASS
-+	else if (protocol == __constant_htons(ETH_P_IPV6)) {
-+		struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN);
-+
-+		if (sizeof(*iph) >= (skb->len - ETH_HLEN)) {
-+			DEBUG_WARN("NAT25: malformed IPv6 packet !\n");
-+			return -1;
-+		}
-+
-+		switch (method) {
-+		case NAT25_CHECK:
-+			if (skb->data[0] & 1)
-+				return 0;
-+			return -1;
-+
-+		case NAT25_INSERT: {
-+			RTW_INFO("NAT25: Insert IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x,"
-+				" DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n",
-+				iph->saddr.s6_addr16[0], iph->saddr.s6_addr16[1], iph->saddr.s6_addr16[2], iph->saddr.s6_addr16[3],
-+				iph->saddr.s6_addr16[4], iph->saddr.s6_addr16[5], iph->saddr.s6_addr16[6], iph->saddr.s6_addr16[7],
-+				iph->daddr.s6_addr16[0], iph->daddr.s6_addr16[1], iph->daddr.s6_addr16[2], iph->daddr.s6_addr16[3],
-+				iph->daddr.s6_addr16[4], iph->daddr.s6_addr16[5], iph->daddr.s6_addr16[6], iph->daddr.s6_addr16[7]);
-+
-+			if (memcmp(&iph->saddr, "\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0", 16)) {
-+				__nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->saddr);
-+				__nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr);
-+				__nat25_db_print(priv);
-+
-+				if (iph->nexthdr == IPPROTO_ICMPV6 &&
-+				    skb->len > (ETH_HLEN +  sizeof(*iph) + 4)) {
-+					if (update_nd_link_layer_addr(skb->data + ETH_HLEN + sizeof(*iph),
-+						skb->len - ETH_HLEN - sizeof(*iph), GET_MY_HWADDR(priv))) {
-+						struct icmp6hdr  *hdr = (struct icmp6hdr *)(skb->data + ETH_HLEN + sizeof(*iph));
-+						hdr->icmp6_cksum = 0;
-+						hdr->icmp6_cksum = csum_ipv6_magic(&iph->saddr, &iph->daddr,
-+							iph->payload_len,
-+							IPPROTO_ICMPV6,
-+							csum_partial((__u8 *)hdr, iph->payload_len, 0));
-+					}
-+				}
-+			}
-+		}
-+		return 0;
-+
-+		case NAT25_LOOKUP:
-+			RTW_INFO("NAT25: Lookup IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x,"
-+				 " DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n",
-+				iph->saddr.s6_addr16[0], iph->saddr.s6_addr16[1], iph->saddr.s6_addr16[2], iph->saddr.s6_addr16[3],
-+				iph->saddr.s6_addr16[4], iph->saddr.s6_addr16[5], iph->saddr.s6_addr16[6], iph->saddr.s6_addr16[7],
-+				iph->daddr.s6_addr16[0], iph->daddr.s6_addr16[1], iph->daddr.s6_addr16[2], iph->daddr.s6_addr16[3],
-+				iph->daddr.s6_addr16[4], iph->daddr.s6_addr16[5], iph->daddr.s6_addr16[6], iph->daddr.s6_addr16[7]);
-+
-+
-+			__nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->daddr);
-+			if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) {
-+#ifdef SUPPORT_RX_UNI2MCAST
-+				if (iph->daddr.s6_addr[0] == 0xff)
-+					convert_ipv6_mac_to_mc(skb);
-+#endif
-+			}
-+			return 0;
-+
-+		default:
-+			return -1;
-+		}
-+	}
-+#endif /* CL_IPV6_PASS */
-+
-+	return -1;
-+}
-+
-+
-+int nat25_handle_frame(_adapter *priv, struct sk_buff *skb)
-+{
-+#ifdef BR_EXT_DEBUG
-+	if ((!priv->ethBrExtInfo.nat25_disable) && (!(skb->data[0] & 1))) {
-+		panic_printk("NAT25: Input Frame: DA=%02x%02x%02x%02x%02x%02x SA=%02x%02x%02x%02x%02x%02x\n",
-+			     skb->data[0],
-+			     skb->data[1],
-+			     skb->data[2],
-+			     skb->data[3],
-+			     skb->data[4],
-+			     skb->data[5],
-+			     skb->data[6],
-+			     skb->data[7],
-+			     skb->data[8],
-+			     skb->data[9],
-+			     skb->data[10],
-+			     skb->data[11]);
-+	}
-+#endif
-+
-+	if (!(skb->data[0] & 1)) {
-+		int is_vlan_tag = 0, i, retval = 0;
-+		unsigned short vlan_hdr = 0;
-+
-+		if (*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_8021Q)) {
-+			is_vlan_tag = 1;
-+			vlan_hdr = *((unsigned short *)(skb->data + ETH_ALEN * 2 + 2));
-+			for (i = 0; i < 6; i++)
-+				*((unsigned short *)(skb->data + ETH_ALEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + ETH_ALEN * 2 - 2 - i * 2));
-+			skb_pull(skb, 4);
-+		}
-+
-+		if (!priv->ethBrExtInfo.nat25_disable) {
-+			_irqL irqL;
-+			_enter_critical_bh(&priv->br_ext_lock, &irqL);
-+			/*
-+			 *	This function look up the destination network address from
-+			 *	the NAT2.5 database. Return value = -1 means that the
-+			 *	corresponding network protocol is NOT support.
-+			 */
-+			if (!priv->ethBrExtInfo.nat25sc_disable &&
-+			    (*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_IP)) &&
-+			    !memcmp(priv->scdb_ip, skb->data + ETH_HLEN + 16, 4)) {
-+				memcpy(skb->data, priv->scdb_mac, ETH_ALEN);
-+
-+				_exit_critical_bh(&priv->br_ext_lock, &irqL);
-+			} else {
-+				_exit_critical_bh(&priv->br_ext_lock, &irqL);
-+
-+				retval = nat25_db_handle(priv, skb, NAT25_LOOKUP);
-+			}
-+		} else {
-+			if (((*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_IP)) &&
-+			     !memcmp(priv->br_ip, skb->data + ETH_HLEN + 16, 4)) ||
-+			    ((*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_ARP)) &&
-+			     !memcmp(priv->br_ip, skb->data + ETH_HLEN + 24, 4))) {
-+				/* for traffic to upper TCP/IP */
-+				retval = nat25_db_handle(priv, skb, NAT25_LOOKUP);
-+			}
-+		}
-+
-+		if (is_vlan_tag) {
-+			skb_push(skb, 4);
-+			for (i = 0; i < 6; i++)
-+				*((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2));
-+			*((unsigned short *)(skb->data + ETH_ALEN * 2)) = __constant_htons(ETH_P_8021Q);
-+			*((unsigned short *)(skb->data + ETH_ALEN * 2 + 2)) = vlan_hdr;
-+		}
-+
-+		if (retval == -1) {
-+			/* DEBUG_ERR("NAT25: Lookup fail!\n"); */
-+			return -1;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+#if 0
-+void mac_clone(_adapter *priv, unsigned char *addr)
-+{
-+	struct sockaddr sa;
-+
-+	memcpy(sa.sa_data, addr, ETH_ALEN);
-+	RTW_INFO("MAC Clone: Addr=%02x%02x%02x%02x%02x%02x\n",
-+		 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
-+	rtl8192cd_set_hwaddr(priv->dev, &sa);
-+}
-+
-+
-+int mac_clone_handle_frame(_adapter *priv, struct sk_buff *skb)
-+{
-+	if (priv->ethBrExtInfo.macclone_enable && !priv->macclone_completed) {
-+		if (!(skb->data[ETH_ALEN] & 1)) {	/* check any other particular MAC add */
-+			if (memcmp(skb->data + ETH_ALEN, GET_MY_HWADDR(priv), ETH_ALEN) &&
-+			    ((priv->dev->br_port) &&
-+			     memcmp(skb->data + ETH_ALEN, priv->br_mac, ETH_ALEN))) {
-+				mac_clone(priv, skb->data + ETH_ALEN);
-+				priv->macclone_completed = 1;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+#endif /* 0 */
-+
-+#define SERVER_PORT			67
-+#define CLIENT_PORT			68
-+#define DHCP_MAGIC			0x63825363
-+#define BROADCAST_FLAG		0x8000
-+
-+struct dhcpMessage {
-+	u_int8_t op;
-+	u_int8_t htype;
-+	u_int8_t hlen;
-+	u_int8_t hops;
-+	u_int32_t xid;
-+	u_int16_t secs;
-+	u_int16_t flags;
-+	u_int32_t ciaddr;
-+	u_int32_t yiaddr;
-+	u_int32_t siaddr;
-+	u_int32_t giaddr;
-+	u_int8_t chaddr[16];
-+	u_int8_t sname[64];
-+	u_int8_t file[128];
-+	u_int32_t cookie;
-+	u_int8_t options[308]; /* 312 - cookie */
-+};
-+
-+void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb)
-+{
-+	if (skb == NULL)
-+		return;
-+
-+	if (!priv->ethBrExtInfo.dhcp_bcst_disable) {
-+		unsigned short protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN));
-+
-+		if (protocol == __constant_htons(ETH_P_IP)) { /* IP */
-+			struct iphdr *iph = (struct iphdr *)(skb->data + ETH_HLEN);
-+
-+			if (iph->protocol == IPPROTO_UDP) { /* UDP */
-+				struct udphdr *udph = (struct udphdr *)((SIZE_PTR)iph + (iph->ihl << 2));
-+
-+				if ((udph->source == __constant_htons(CLIENT_PORT))
-+				    && (udph->dest == __constant_htons(SERVER_PORT))) { /* DHCP request */
-+					struct dhcpMessage *dhcph =
-+						(struct dhcpMessage *)((SIZE_PTR)udph + sizeof(struct udphdr));
-+
-+					if (dhcph->cookie == __constant_htonl(DHCP_MAGIC)) { /* match magic word */
-+						if (!(dhcph->flags & htons(BROADCAST_FLAG))) { /* if not broadcast */
-+							register int sum = 0;
-+
-+							RTW_INFO("DHCP: change flag of DHCP request to broadcast.\n");
-+							/* or BROADCAST flag */
-+							dhcph->flags |= htons(BROADCAST_FLAG);
-+							/* recalculate checksum */
-+							sum = ~(udph->check) & 0xffff;
-+							sum += dhcph->flags;
-+							while (sum >> 16)
-+								sum = (sum & 0xffff) + (sum >> 16);
-+							udph->check = ~sum;
-+						}
-+					}
-+				}
-+			}
-+		}
-+	}
-+}
-+
-+
-+void *scdb_findEntry(_adapter *priv, unsigned char *macAddr,
-+		     unsigned char *ipAddr)
-+{
-+	unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
-+	struct nat25_network_db_entry *db;
-+	int hash;
-+	/* _irqL irqL; */
-+	/* _enter_critical_bh(&priv->br_ext_lock, &irqL); */
-+
-+	__nat25_generate_ipv4_network_addr(networkAddr, (unsigned int *)ipAddr);
-+	hash = __nat25_network_hash(networkAddr);
-+	db = priv->nethash[hash];
-+	while (db != NULL) {
-+		if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) {
-+			/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */
-+			return (void *)db;
-+		}
-+
-+		db = db->next_hash;
-+	}
-+
-+	/* _exit_critical_bh(&priv->br_ext_lock, &irqL); */
-+	return NULL;
-+}
-+
-+#endif /* CONFIG_BR_EXT */
-diff --git a/drivers/staging/rtl8723cs/core/rtw_bt_mp.c b/drivers/staging/rtl8723cs/core/rtw_bt_mp.c
-new file mode 100644
-index 000000000000..ce7aa29f7d11
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_bt_mp.c
-@@ -0,0 +1,1575 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+#include <drv_types.h>
-+#include <rtw_bt_mp.h>
-+
-+#if defined(CONFIG_RTL8723B)
-+	#include <rtl8723b_hal.h>
-+#endif
-+
-+#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
-+void MPh2c_timeout_handle(void *FunctionContext)
-+{
-+	PADAPTER pAdapter;
-+	PMPT_CONTEXT pMptCtx;
-+
-+
-+	RTW_INFO("[MPT], MPh2c_timeout_handle\n");
-+
-+	pAdapter = (PADAPTER)FunctionContext;
-+	pMptCtx = &pAdapter->mppriv.mpt_ctx;
-+
-+	pMptCtx->bMPh2c_timeout = _TRUE;
-+
-+	if ((_FALSE == pMptCtx->MptH2cRspEvent)
-+	    || ((_TRUE == pMptCtx->MptH2cRspEvent)
-+		&& (_FALSE == pMptCtx->MptBtC2hEvent)))
-+		_rtw_up_sema(&pMptCtx->MPh2c_Sema);
-+}
-+
-+u32 WaitC2Hevent(PADAPTER pAdapter, u8 *C2H_event, u32 delay_time)
-+{
-+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+	pMptCtx->bMPh2c_timeout = _FALSE;
-+
-+	if (pAdapter->registrypriv.mp_mode == 0) {
-+		RTW_INFO("[MPT], Error!! WaitC2Hevent mp_mode == 0!!\n");
-+		return _FALSE;
-+	}
-+
-+	_set_timer(&pMptCtx->MPh2c_timeout_timer, delay_time);
-+
-+	_rtw_down_sema(&pMptCtx->MPh2c_Sema);
-+
-+	if (pMptCtx->bMPh2c_timeout == _TRUE) {
-+		*C2H_event = _FALSE;
-+
-+		return _FALSE;
-+	}
-+
-+	/* for safty, cancel timer here again */
-+	_cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
-+
-+	return _TRUE;
-+}
-+
-+BT_CTRL_STATUS
-+mptbt_CheckC2hFrame(
-+	PADAPTER		Adapter,
-+	PBT_H2C			pH2c,
-+	PBT_EXT_C2H		pExtC2h
-+)
-+{
-+	BT_CTRL_STATUS	c2hStatus = BT_STATUS_C2H_SUCCESS;
-+
-+	/* RTW_INFO("[MPT], MPT rsp C2H hex: %x %x %x  %x %x %x\n"), pExtC2h , pExtC2h+1 ,pExtC2h+2 ,pExtC2h+3 ,pExtC2h+4 ,pExtC2h+5); */
-+
-+	RTW_INFO("[MPT], statusCode = 0x%x\n", pExtC2h->statusCode);
-+	RTW_INFO("[MPT], retLen = %d\n", pExtC2h->retLen);
-+	RTW_INFO("[MPT], opCodeVer : req/rsp=%d/%d\n", pH2c->opCodeVer, pExtC2h->opCodeVer);
-+	RTW_INFO("[MPT], reqNum : req/rsp=%d/%d\n", pH2c->reqNum, pExtC2h->reqNum);
-+	if (pExtC2h->reqNum != pH2c->reqNum) {
-+		c2hStatus = BT_STATUS_C2H_REQNUM_MISMATCH;
-+		RTW_INFO("[MPT], Error!! C2H reqNum Mismatch!!\n");
-+	} else if (pExtC2h->opCodeVer != pH2c->opCodeVer) {
-+		c2hStatus = BT_STATUS_OPCODE_L_VERSION_MISMATCH;
-+		RTW_INFO("[MPT], Error!! OPCode version L mismatch!!\n");
-+	}
-+
-+	return c2hStatus;
-+}
-+
-+BT_CTRL_STATUS
-+mptbt_SendH2c(
-+	PADAPTER	Adapter,
-+	PBT_H2C	pH2c,
-+	u16		h2cCmdLen
-+)
-+{
-+	/* KIRQL				OldIrql = KeGetCurrentIrql(); */
-+	BT_CTRL_STATUS	h2cStatus = BT_STATUS_H2C_SUCCESS;
-+	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
-+	u8				i;
-+
-+	RTW_INFO("[MPT], mptbt_SendH2c()=========>\n");
-+
-+	/* PlatformResetEvent(&pMptCtx->MptH2cRspEvent); */
-+	/* PlatformResetEvent(&pMptCtx->MptBtC2hEvent); */
-+
-+	/*	if(OldIrql == PASSIVE_LEVEL)
-+	 *	{ */
-+	/* RTPRINT_DATA(FMPBT, FMPBT_H2C_CONTENT, ("[MPT], MPT H2C hex:\n"), pH2c, h2cCmdLen); */
-+
-+	for (i = 0; i < BT_H2C_MAX_RETRY; i++) {
-+		RTW_INFO("[MPT], Send H2C command to wifi!!!\n");
-+
-+		pMptCtx->MptH2cRspEvent = _FALSE;
-+		pMptCtx->MptBtC2hEvent = _FALSE;
-+
-+#if defined(CONFIG_RTL8723B)
-+		rtl8723b_set_FwBtMpOper_cmd(Adapter, pH2c->opCode, pH2c->opCodeVer, pH2c->reqNum, pH2c->buf);
-+#endif
-+		pMptCtx->h2cReqNum++;
-+		pMptCtx->h2cReqNum %= 16;
-+
-+		if (WaitC2Hevent(Adapter, &pMptCtx->MptH2cRspEvent, 100)) {
-+			RTW_INFO("[MPT], Received WiFi MptH2cRspEvent!!!\n");
-+			if (WaitC2Hevent(Adapter, &pMptCtx->MptBtC2hEvent, 400)) {
-+				RTW_INFO("[MPT], Received MptBtC2hEvent!!!\n");
-+				break;
-+			} else {
-+				RTW_INFO("[MPT], Error!!BT MptBtC2hEvent timeout!!\n");
-+				h2cStatus = BT_STATUS_H2C_BT_NO_RSP;
-+			}
-+		} else {
-+			RTW_INFO("[MPT], Error!!WiFi  MptH2cRspEvent timeout!!\n");
-+			h2cStatus = BT_STATUS_H2C_TIMTOUT;
-+		}
-+	}
-+	/*	}
-+	 *	else
-+	 *	{
-+	 * 		RT_ASSERT(FALSE, ("[MPT],  mptbt_SendH2c() can only run under PASSIVE_LEVEL!!\n"));
-+	 *		h2cStatus = BT_STATUS_WRONG_LEVEL;
-+	 *	} */
-+
-+	RTW_INFO("[MPT], mptbt_SendH2c()<=========\n");
-+	return h2cStatus;
-+}
-+
-+
-+
-+BT_CTRL_STATUS
-+mptbt_CheckBtRspStatus(
-+	PADAPTER			Adapter,
-+	PBT_EXT_C2H			pExtC2h
-+)
-+{
-+	BT_CTRL_STATUS	retStatus = BT_OP_STATUS_SUCCESS;
-+
-+	switch (pExtC2h->statusCode) {
-+	case BT_OP_STATUS_SUCCESS:
-+		retStatus = BT_STATUS_BT_OP_SUCCESS;
-+		RTW_INFO("[MPT], BT status : BT_STATUS_SUCCESS\n");
-+		break;
-+	case BT_OP_STATUS_VERSION_MISMATCH:
-+		retStatus = BT_STATUS_OPCODE_L_VERSION_MISMATCH;
-+		RTW_INFO("[MPT], BT status : BT_STATUS_OPCODE_L_VERSION_MISMATCH\n");
-+		break;
-+	case BT_OP_STATUS_UNKNOWN_OPCODE:
-+		retStatus = BT_STATUS_UNKNOWN_OPCODE_L;
-+		RTW_INFO("[MPT], BT status : BT_STATUS_UNKNOWN_OPCODE_L\n");
-+		break;
-+	case BT_OP_STATUS_ERROR_PARAMETER:
-+		retStatus = BT_STATUS_PARAMETER_FORMAT_ERROR_L;
-+		RTW_INFO("[MPT], BT status : BT_STATUS_PARAMETER_FORMAT_ERROR_L\n");
-+		break;
-+	default:
-+		retStatus = BT_STATUS_UNKNOWN_STATUS_L;
-+		RTW_INFO("[MPT], BT status : BT_STATUS_UNKNOWN_STATUS_L\n");
-+		break;
-+	}
-+
-+	return retStatus;
-+}
-+
-+
-+
-+BT_CTRL_STATUS
-+mptbt_BtFwOpCodeProcess(
-+	PADAPTER		Adapter,
-+	u8			btFwOpCode,
-+	u8			opCodeVer,
-+	u8			*pH2cPar,
-+	u8			h2cParaLen
-+)
-+{
-+	u8				H2C_Parameter[6] = {0};
-+	PBT_H2C				pH2c = (PBT_H2C)&H2C_Parameter[0];
-+	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
-+	PBT_EXT_C2H			pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];
-+	u16				paraLen = 0, i;
-+	BT_CTRL_STATUS	h2cStatus = BT_STATUS_H2C_SUCCESS, c2hStatus = BT_STATUS_C2H_SUCCESS;
-+	BT_CTRL_STATUS	retStatus = BT_STATUS_H2C_BT_NO_RSP;
-+
-+	if (Adapter->registrypriv.mp_mode == 0) {
-+		RTW_INFO("[MPT], Error!! mptbt_BtFwOpCodeProces mp_mode == 0!!\n");
-+		return _FALSE;
-+	}
-+
-+	pH2c->opCode = btFwOpCode;
-+	pH2c->opCodeVer = opCodeVer;
-+	pH2c->reqNum = pMptCtx->h2cReqNum;
-+	/* PlatformMoveMemory(&pH2c->buf[0], pH2cPar, h2cParaLen); */
-+	/* _rtw_memcpy(&pH2c->buf[0], pH2cPar, h2cParaLen); */
-+	_rtw_memcpy(pH2c->buf, pH2cPar, h2cParaLen);
-+
-+	RTW_INFO("[MPT], pH2c->opCode=%d\n", pH2c->opCode);
-+	RTW_INFO("[MPT], pH2c->opCodeVer=%d\n", pH2c->opCodeVer);
-+	RTW_INFO("[MPT], pH2c->reqNum=%d\n", pH2c->reqNum);
-+	RTW_INFO("[MPT], h2c parameter length=%d\n", h2cParaLen);
-+	for (i = 0; i < h2cParaLen; i++)
-+		RTW_INFO("[MPT], parameter[%d]=0x%02x\n", i, pH2c->buf[i]);
-+
-+	h2cStatus = mptbt_SendH2c(Adapter, pH2c, h2cParaLen + 2);
-+	if (BT_STATUS_H2C_SUCCESS == h2cStatus) {
-+		/* if reach here, it means H2C get the correct c2h response, */
-+		c2hStatus = mptbt_CheckC2hFrame(Adapter, pH2c, pExtC2h);
-+		if (BT_STATUS_C2H_SUCCESS == c2hStatus)
-+			retStatus = mptbt_CheckBtRspStatus(Adapter, pExtC2h);
-+		else {
-+			RTW_INFO("[MPT], Error!! C2H failed for pH2c->opCode=%d\n", pH2c->opCode);
-+			/* check c2h status error, return error status code to upper layer. */
-+			retStatus = c2hStatus;
-+		}
-+	} else {
-+		RTW_INFO("[MPT], Error!! H2C failed for pH2c->opCode=%d\n", pH2c->opCode);
-+		/* check h2c status error, return error status code to upper layer. */
-+		retStatus = h2cStatus;
-+	}
-+
-+	return retStatus;
-+}
-+
-+
-+
-+
-+u16
-+mptbt_BtReady(
-+	PADAPTER		Adapter,
-+	PBT_REQ_CMD	pBtReq,
-+	PBT_RSP_CMD	pBtRsp
-+)
-+{
-+	u8				h2cParaBuf[6] = {0};
-+	u8				h2cParaLen = 0;
-+	u16				paraLen = 0;
-+	u8				retStatus = BT_STATUS_BT_OP_SUCCESS;
-+	u8				btOpcode;
-+	u8				btOpcodeVer = 0;
-+	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
-+	PBT_EXT_C2H			pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];
-+	u8				i;
-+	u8				btFwVer = 0, bdAddr[6] = {0};
-+	u16				btRealFwVer = 0;
-+	u16				*pu2Tmp = NULL;
-+
-+	/*  */
-+	/* check upper layer parameters */
-+	/*  */
-+
-+	/* 1. check upper layer opcode version */
-+	if (pBtReq->opCodeVer != 1) {
-+		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
-+		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
-+		return paraLen;
-+	}
-+
-+	pBtRsp->pParamStart[0] = MP_BT_NOT_READY;
-+	paraLen = 10;
-+	/*  */
-+	/* execute lower layer opcodes */
-+	/*  */
-+
-+	/* Get BT FW version */
-+	/* fill h2c parameters */
-+	btOpcode = BT_LO_OP_GET_BT_VERSION;
-+	/* execute h2c and check respond c2h from bt fw is correct or not */
-+	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+	/* ckeck bt return status. */
-+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+		pBtRsp->status = ((btOpcode << 8) | retStatus);
-+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+		return paraLen;
-+	} else {
-+		pu2Tmp = (u16 *)&pExtC2h->buf[0];
-+		btRealFwVer = *pu2Tmp;
-+		btFwVer = pExtC2h->buf[1];
-+		RTW_INFO("[MPT], btRealFwVer=0x%x, btFwVer=0x%x\n", btRealFwVer, btFwVer);
-+	}
-+
-+	/* Get BD Address */
-+	/* fill h2c parameters */
-+	btOpcode = BT_LO_OP_GET_BD_ADDR_L;
-+	/* execute h2c and check respond c2h from bt fw is correct or not */
-+	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+	/* ckeck bt return status. */
-+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+		pBtRsp->status = ((btOpcode << 8) | retStatus);
-+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+		return paraLen;
-+	} else {
-+		bdAddr[5] = pExtC2h->buf[0];
-+		bdAddr[4] = pExtC2h->buf[1];
-+		bdAddr[3] = pExtC2h->buf[2];
-+	}
-+
-+	/* fill h2c parameters */
-+	btOpcode = BT_LO_OP_GET_BD_ADDR_H;
-+	/* execute h2c and check respond c2h from bt fw is correct or not */
-+	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+	/* ckeck bt return status. */
-+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+		pBtRsp->status = ((btOpcode << 8) | retStatus);
-+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+		return paraLen;
-+	} else {
-+		bdAddr[2] = pExtC2h->buf[0];
-+		bdAddr[1] = pExtC2h->buf[1];
-+		bdAddr[0] = pExtC2h->buf[2];
-+	}
-+	RTW_INFO("[MPT], Local BDAddr:");
-+	for (i = 0; i < 6; i++)
-+		RTW_INFO(" 0x%x ", bdAddr[i]);
-+	pBtRsp->status = BT_STATUS_SUCCESS;
-+	pBtRsp->pParamStart[0] = MP_BT_READY;
-+	pu2Tmp = (u16 *)&pBtRsp->pParamStart[1];
-+	*pu2Tmp = btRealFwVer;
-+	pBtRsp->pParamStart[3] = btFwVer;
-+	for (i = 0; i < 6; i++)
-+		pBtRsp->pParamStart[4 + i] = bdAddr[5 - i];
-+
-+	return paraLen;
-+}
-+
-+void mptbt_close_WiFiRF(PADAPTER Adapter)
-+{
-+	phy_set_bb_reg(Adapter, 0x824, 0xF, 0x0);
-+	phy_set_bb_reg(Adapter, 0x824, 0x700000, 0x0);
-+	phy_set_rf_reg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x0);
-+}
-+
-+void mptbt_open_WiFiRF(PADAPTER	Adapter)
-+{
-+	phy_set_bb_reg(Adapter, 0x824, 0x700000, 0x3);
-+	phy_set_bb_reg(Adapter, 0x824, 0xF, 0x2);
-+	phy_set_rf_reg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x3);
-+}
-+
-+u32 mptbt_switch_RF(PADAPTER	Adapter, u8	Enter)
-+{
-+	u16	tmp_2byte = 0;
-+
-+	/* Enter test mode */
-+	if (Enter) {
-+		/* 1>. close WiFi RF */
-+		mptbt_close_WiFiRF(Adapter);
-+
-+		/* 2>. change ant switch to BT */
-+		tmp_2byte = rtw_read16(Adapter, 0x860);
-+		tmp_2byte = tmp_2byte | BIT(9);
-+		tmp_2byte = tmp_2byte & (~BIT(8));
-+		rtw_write16(Adapter, 0x860, tmp_2byte);
-+		rtw_write16(Adapter, 0x870, 0x300);
-+	} else {
-+		/* 1>. Open WiFi RF */
-+		mptbt_open_WiFiRF(Adapter);
-+
-+		/* 2>. change ant switch back */
-+		tmp_2byte = rtw_read16(Adapter, 0x860);
-+		tmp_2byte = tmp_2byte | BIT(8);
-+		tmp_2byte = tmp_2byte & (~BIT(9));
-+		rtw_write16(Adapter, 0x860, tmp_2byte);
-+		rtw_write16(Adapter, 0x870, 0x300);
-+	}
-+
-+	return 0;
-+}
-+
-+u16
-+mptbt_BtSetMode(
-+	PADAPTER		Adapter,
-+	PBT_REQ_CMD	pBtReq,
-+	PBT_RSP_CMD	pBtRsp
-+)
-+{
-+	u8				h2cParaBuf[6] = {0};
-+	u8				h2cParaLen = 0;
-+	u16				paraLen = 0;
-+	u8				retStatus = BT_STATUS_BT_OP_SUCCESS;
-+	u8				btOpcode;
-+	u8				btOpcodeVer = 0;
-+	u8				btModeToSet = 0;
-+
-+	/*  */
-+	/* check upper layer parameters */
-+	/*  */
-+	/* 1. check upper layer opcode version */
-+	if (pBtReq->opCodeVer != 1) {
-+		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
-+		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
-+		return paraLen;
-+	}
-+	/* 2. check upper layer parameter length */
-+	if (1 == pBtReq->paraLength) {
-+		btModeToSet = pBtReq->pParamStart[0];
-+		RTW_INFO("[MPT], BtTestMode=%d\n", btModeToSet);
-+	} else {
-+		RTW_INFO("[MPT], Error!! wrong parameter length=%d (should be 1)\n", pBtReq->paraLength);
-+		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
-+		return paraLen;
-+	}
-+
-+	/*  */
-+	/* execute lower layer opcodes */
-+	/*  */
-+
-+	/* 1. fill h2c parameters	 */
-+	/* check bt mode */
-+	btOpcode = BT_LO_OP_SET_BT_MODE;
-+	if (btModeToSet >= MP_BT_MODE_MAX) {
-+		pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+		return paraLen;
-+	} else {
-+		mptbt_switch_RF(Adapter, 1);
-+
-+		h2cParaBuf[0] = btModeToSet;
-+		h2cParaLen = 1;
-+		/* 2. execute h2c and check respond c2h from bt fw is correct or not */
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+	}
-+
-+	/* 3. construct respond status code and data. */
-+	if (BT_STATUS_BT_OP_SUCCESS == retStatus)
-+		pBtRsp->status = BT_STATUS_SUCCESS;
-+	else {
-+		pBtRsp->status = ((btOpcode << 8) | retStatus);
-+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+	}
-+
-+	return paraLen;
-+}
-+
-+
-+void
-+MPTBT_FwC2hBtMpCtrl(
-+	PADAPTER	Adapter,
-+	u8		*tmpBuf,
-+	u8		length
-+)
-+{
-+	u32 i;
-+	PMPT_CONTEXT	pMptCtx = &(Adapter->mppriv.mpt_ctx);
-+	PBT_EXT_C2H pExtC2h = (PBT_EXT_C2H)tmpBuf;
-+
-+	if (GET_HAL_DATA(Adapter)->bBTFWReady == _FALSE || Adapter->registrypriv.mp_mode == 0) {
-+		/* RTW_INFO("Ignore C2H BT MP Info since not in MP mode\n"); */
-+		return;
-+	}
-+	if (length > 32 || length < 3) {
-+		RTW_INFO("\n [MPT], pExtC2h->buf hex: length=%d > 32 || < 3\n", length);
-+		return;
-+	}
-+
-+	/* cancel_timeout for h2c handle */
-+	_cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
-+
-+	for (i = 0; i < length; i++)
-+		RTW_INFO("[MPT], %s, buf[%d]=0x%02x ", __FUNCTION__, i, tmpBuf[i]);
-+	RTW_INFO("[MPT], pExtC2h->extendId=0x%x\n", pExtC2h->extendId);
-+
-+	switch (pExtC2h->extendId) {
-+	case EXT_C2H_WIFI_FW_ACTIVE_RSP:
-+		RTW_INFO("[MPT], EXT_C2H_WIFI_FW_ACTIVE_RSP\n");
-+#if 0
-+		RTW_INFO("[MPT], pExtC2h->buf hex:\n");
-+		for (i = 0; i < (length - 3); i++)
-+			RTW_INFO(" 0x%x ", pExtC2h->buf[i]);
-+#endif
-+		if ((_FALSE == pMptCtx->bMPh2c_timeout)
-+		    && (_FALSE == pMptCtx->MptH2cRspEvent)) {
-+			pMptCtx->MptH2cRspEvent = _TRUE;
-+			_rtw_up_sema(&pMptCtx->MPh2c_Sema);
-+		}
-+		break;
-+
-+	case EXT_C2H_TRIG_BY_BT_FW:
-+		RTW_INFO("[MPT], EXT_C2H_TRIG_BY_BT_FW\n");
-+		_rtw_memcpy(&pMptCtx->c2hBuf[0], tmpBuf, length);
-+		RTW_INFO("[MPT], pExtC2h->statusCode=0x%x\n", pExtC2h->statusCode);
-+		RTW_INFO("[MPT], pExtC2h->retLen=0x%x\n", pExtC2h->retLen);
-+		RTW_INFO("[MPT], pExtC2h->opCodeVer=0x%x\n", pExtC2h->opCodeVer);
-+		RTW_INFO("[MPT], pExtC2h->reqNum=0x%x\n", pExtC2h->reqNum);
-+		for (i = 0; i < (length - 3); i++)
-+			RTW_INFO("[MPT], pExtC2h->buf[%d]=0x%02x\n", i, pExtC2h->buf[i]);
-+
-+		if ((_FALSE == pMptCtx->bMPh2c_timeout)
-+		    && (_TRUE == pMptCtx->MptH2cRspEvent)
-+		    && (_FALSE == pMptCtx->MptBtC2hEvent)) {
-+			pMptCtx->MptBtC2hEvent = _TRUE;
-+			_rtw_up_sema(&pMptCtx->MPh2c_Sema);
-+		}
-+		break;
-+
-+	default:
-+		RTW_INFO("[MPT], EXT_C2H Target not found,pExtC2h->extendId =%d ,pExtC2h->reqNum=%d\n", pExtC2h->extendId, pExtC2h->reqNum);
-+		break;
-+	}
-+
-+
-+
-+}
-+
-+
-+u16
-+mptbt_BtGetGeneral(
-+		PADAPTER		Adapter,
-+		PBT_REQ_CMD	pBtReq,
-+		PBT_RSP_CMD	pBtRsp
-+)
-+{
-+	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
-+	PBT_EXT_C2H		pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];
-+	u8				h2cParaBuf[6] = {0};
-+	u8				h2cParaLen = 0;
-+	u16				paraLen = 0;
-+	u8				retStatus = BT_STATUS_BT_OP_SUCCESS;
-+	u8				btOpcode, bdAddr[6] = {0};
-+	u8				btOpcodeVer = 0;
-+	u8				getType = 0, i;
-+	u16				getParaLen = 0, validParaLen = 0;
-+	u8				regType = 0, reportType = 0;
-+	u32				regAddr = 0, regValue = 0;
-+	u32 				*pu4Tmp;
-+	u16 				*pu2Tmp;
-+	u8 				*pu1Tmp;
-+
-+	/*  */
-+	/* check upper layer parameters */
-+	/*  */
-+
-+	/* check upper layer opcode version */
-+	if (pBtReq->opCodeVer != 1) {
-+		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
-+		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
-+		return paraLen;
-+	}
-+	/* check upper layer parameter length */
-+	if (pBtReq->paraLength < 1) {
-+		RTW_INFO("[MPT], Error!! wrong parameter length=%d (should larger than 1)\n", pBtReq->paraLength);
-+		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
-+		return paraLen;
-+	}
-+	getParaLen = pBtReq->paraLength - 1;
-+	getType = pBtReq->pParamStart[0];
-+
-+	RTW_INFO("[MPT], getType=%d, getParaLen=%d\n", getType, getParaLen);
-+
-+	/* check parameter first */
-+	switch (getType) {
-+	case BT_GGET_REG:
-+		RTW_INFO("[MPT], [BT_GGET_REG]\n");
-+		validParaLen = 5;
-+		if (getParaLen == validParaLen) {
-+			btOpcode = BT_LO_OP_READ_REG;
-+			regType = pBtReq->pParamStart[1];
-+			pu4Tmp = (u32 *)&pBtReq->pParamStart[2];
-+			regAddr = *pu4Tmp;
-+			RTW_INFO("[MPT], BT_GGET_REG regType=0x%02x, regAddr=0x%08x!!\n",
-+				 regType, regAddr);
-+			if (regType >= BT_REG_MAX) {
-+				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+				return paraLen;
-+			} else {
-+				if (((BT_REG_RF == regType) && (regAddr > 0x7f)) ||
-+				    ((BT_REG_MODEM == regType) && (regAddr > 0x1ff)) ||
-+				    ((BT_REG_BLUEWIZE == regType) && (regAddr > 0xfff)) ||
-+				    ((BT_REG_VENDOR == regType) && (regAddr > 0xfff)) ||
-+				    ((BT_REG_LE == regType) && (regAddr > 0xfff))) {
-+					pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+					return paraLen;
-+				}
-+			}
-+		}
-+		break;
-+	case BT_GGET_STATUS:
-+		RTW_INFO("[MPT], [BT_GGET_STATUS]\n");
-+		validParaLen = 0;
-+		break;
-+	case BT_GGET_REPORT:
-+		RTW_INFO("[MPT], [BT_GGET_REPORT]\n");
-+		validParaLen = 1;
-+		if (getParaLen == validParaLen) {
-+			reportType = pBtReq->pParamStart[1];
-+			RTW_INFO("[MPT], BT_GGET_REPORT reportType=0x%x!!\n", reportType);
-+			if (reportType >= BT_REPORT_MAX) {
-+				pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+				return paraLen;
-+			}
-+		}
-+		break;
-+	default: {
-+		RTW_INFO("[MPT], Error!! getType=%d, out of range\n", getType);
-+		pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+		return paraLen;
-+	}
-+	break;
-+	}
-+	if (getParaLen != validParaLen) {
-+		RTW_INFO("[MPT], Error!! wrong parameter length=%d for BT_GET_GEN_CMD cmd id=0x%x, paraLen should=0x%x\n",
-+			 getParaLen, getType, validParaLen);
-+		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
-+		return paraLen;
-+	}
-+
-+	/*  */
-+	/* execute lower layer opcodes */
-+	/*  */
-+	if (BT_GGET_REG == getType) {
-+		/* fill h2c parameters */
-+		/* here we should write reg value first then write the address, adviced by Austin */
-+		btOpcode = BT_LO_OP_READ_REG;
-+		h2cParaBuf[0] = regType;
-+		h2cParaBuf[1] = pBtReq->pParamStart[2];
-+		h2cParaBuf[2] = pBtReq->pParamStart[3];
-+		h2cParaLen = 3;
-+		/* execute h2c and check respond c2h from bt fw is correct or not */
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+		/* construct respond status code and data. */
-+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+			pBtRsp->status = ((btOpcode << 8) | retStatus);
-+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+			return paraLen;
-+		}
-+
-+		pu2Tmp = (u16 *)&pExtC2h->buf[0];
-+		regValue = *pu2Tmp;
-+		RTW_INFO("[MPT], read reg regType=0x%02x, regAddr=0x%08x, regValue=0x%04x\n",
-+			 regType, regAddr, regValue);
-+
-+		pu4Tmp = (u32 *)&pBtRsp->pParamStart[0];
-+		*pu4Tmp = regValue;
-+		paraLen = 4;
-+	} else if (BT_GGET_STATUS == getType) {
-+		btOpcode = BT_LO_OP_GET_BT_STATUS;
-+		h2cParaLen = 0;
-+		/* execute h2c and check respond c2h from bt fw is correct or not */
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+		/* construct respond status code and data. */
-+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+			pBtRsp->status = ((btOpcode << 8) | retStatus);
-+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+			return paraLen;
-+		}
-+
-+		pBtRsp->pParamStart[0] = pExtC2h->buf[0];
-+		pBtRsp->pParamStart[1] = pExtC2h->buf[1];
-+		RTW_INFO("[MPT], read bt status, testMode=0x%x, testStatus=0x%x\n",
-+			 pBtRsp->pParamStart[0], pBtRsp->pParamStart[1]);
-+		paraLen = 2;
-+	} else if (BT_GGET_REPORT == getType) {
-+		switch (reportType) {
-+		case BT_REPORT_RX_PACKET_CNT: {
-+			RTW_INFO("[MPT], [Rx Packet Counts]\n");
-+			btOpcode = BT_LO_OP_GET_RX_PKT_CNT_L;
-+			h2cParaLen = 0;
-+			/* execute h2c and check respond c2h from bt fw is correct or not */
-+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+			/* construct respond status code and data. */
-+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+				pBtRsp->status = ((btOpcode << 8) | retStatus);
-+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+				return paraLen;
-+			}
-+			pBtRsp->pParamStart[0] = pExtC2h->buf[0];
-+			pBtRsp->pParamStart[1] = pExtC2h->buf[1];
-+
-+			btOpcode = BT_LO_OP_GET_RX_PKT_CNT_H;
-+			h2cParaLen = 0;
-+			/* execute h2c and check respond c2h from bt fw is correct or not */
-+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+			/* construct respond status code and data. */
-+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+				pBtRsp->status = ((btOpcode << 8) | retStatus);
-+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+				return paraLen;
-+			}
-+			pBtRsp->pParamStart[2] = pExtC2h->buf[0];
-+			pBtRsp->pParamStart[3] = pExtC2h->buf[1];
-+			paraLen = 4;
-+		}
-+		break;
-+		case BT_REPORT_RX_ERROR_BITS: {
-+			RTW_INFO("[MPT], [Rx Error Bits]\n");
-+			btOpcode = BT_LO_OP_GET_RX_ERROR_BITS_L;
-+			h2cParaLen = 0;
-+			/* execute h2c and check respond c2h from bt fw is correct or not */
-+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+			/* construct respond status code and data. */
-+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+				pBtRsp->status = ((btOpcode << 8) | retStatus);
-+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+				return paraLen;
-+			}
-+			pBtRsp->pParamStart[0] = pExtC2h->buf[0];
-+			pBtRsp->pParamStart[1] = pExtC2h->buf[1];
-+
-+			btOpcode = BT_LO_OP_GET_RX_ERROR_BITS_H;
-+			h2cParaLen = 0;
-+			/* execute h2c and check respond c2h from bt fw is correct or not */
-+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+			/* construct respond status code and data. */
-+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+				pBtRsp->status = ((btOpcode << 8) | retStatus);
-+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+				return paraLen;
-+			}
-+			pBtRsp->pParamStart[2] = pExtC2h->buf[0];
-+			pBtRsp->pParamStart[3] = pExtC2h->buf[1];
-+			paraLen = 4;
-+		}
-+		break;
-+		case BT_REPORT_RSSI: {
-+			RTW_INFO("[MPT], [RSSI]\n");
-+			btOpcode = BT_LO_OP_GET_RSSI;
-+			h2cParaLen = 0;
-+			/* execute h2c and check respond c2h from bt fw is correct or not */
-+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+			/* construct respond status code and data. */
-+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+				pBtRsp->status = ((btOpcode << 8) | retStatus);
-+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+				return paraLen;
-+			}
-+			pBtRsp->pParamStart[0] = pExtC2h->buf[0];
-+			pBtRsp->pParamStart[1] = pExtC2h->buf[1];
-+			paraLen = 2;
-+		}
-+		break;
-+		case BT_REPORT_CFO_HDR_QUALITY: {
-+			RTW_INFO("[MPT], [CFO & Header Quality]\n");
-+			btOpcode = BT_LO_OP_GET_CFO_HDR_QUALITY_L;
-+			h2cParaLen = 0;
-+			/* execute h2c and check respond c2h from bt fw is correct or not */
-+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+			/* construct respond status code and data. */
-+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+				pBtRsp->status = ((btOpcode << 8) | retStatus);
-+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+				return paraLen;
-+			}
-+			pBtRsp->pParamStart[0] = pExtC2h->buf[0];
-+			pBtRsp->pParamStart[1] = pExtC2h->buf[1];
-+
-+			btOpcode = BT_LO_OP_GET_CFO_HDR_QUALITY_H;
-+			h2cParaLen = 0;
-+			/* execute h2c and check respond c2h from bt fw is correct or not */
-+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+			/* construct respond status code and data. */
-+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+				pBtRsp->status = ((btOpcode << 8) | retStatus);
-+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+				return paraLen;
-+			}
-+			pBtRsp->pParamStart[2] = pExtC2h->buf[0];
-+			pBtRsp->pParamStart[3] = pExtC2h->buf[1];
-+			paraLen = 4;
-+		}
-+		break;
-+		case BT_REPORT_CONNECT_TARGET_BD_ADDR: {
-+			RTW_INFO("[MPT], [Connected Target BD ADDR]\n");
-+			btOpcode = BT_LO_OP_GET_TARGET_BD_ADDR_L;
-+			h2cParaLen = 0;
-+			/* execute h2c and check respond c2h from bt fw is correct or not */
-+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+			/* construct respond status code and data. */
-+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+				pBtRsp->status = ((btOpcode << 8) | retStatus);
-+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+				return paraLen;
-+			}
-+			bdAddr[5] = pExtC2h->buf[0];
-+			bdAddr[4] = pExtC2h->buf[1];
-+			bdAddr[3] = pExtC2h->buf[2];
-+
-+			btOpcode = BT_LO_OP_GET_TARGET_BD_ADDR_H;
-+			h2cParaLen = 0;
-+			/* execute h2c and check respond c2h from bt fw is correct or not */
-+			retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+			/* construct respond status code and data. */
-+			if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+				pBtRsp->status = ((btOpcode << 8) | retStatus);
-+				RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+				return paraLen;
-+			}
-+			bdAddr[2] = pExtC2h->buf[0];
-+			bdAddr[1] = pExtC2h->buf[1];
-+			bdAddr[0] = pExtC2h->buf[2];
-+
-+			RTW_INFO("[MPT], Connected Target BDAddr:%s", bdAddr);
-+			for (i = 0; i < 6; i++)
-+				pBtRsp->pParamStart[i] = bdAddr[5 - i];
-+			paraLen = 6;
-+		}
-+		break;
-+		default:
-+			pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+			return paraLen;
-+			break;
-+		}
-+	}
-+
-+	pBtRsp->status = BT_STATUS_SUCCESS;
-+	return paraLen;
-+}
-+
-+
-+
-+u16
-+mptbt_BtSetGeneral(
-+		PADAPTER		Adapter,
-+		PBT_REQ_CMD	pBtReq,
-+		PBT_RSP_CMD	pBtRsp
-+)
-+{
-+	u8				h2cParaBuf[6] = {0};
-+	u8				h2cParaLen = 0;
-+	u16				paraLen = 0;
-+	u8				retStatus = BT_STATUS_BT_OP_SUCCESS;
-+	u8				btOpcode;
-+	u8				btOpcodeVer = 0;
-+	u8				setType = 0;
-+	u16				setParaLen = 0, validParaLen = 0;
-+	u8				regType = 0, bdAddr[6] = {0}, calVal = 0;
-+	u32				regAddr = 0, regValue = 0;
-+	u32 				*pu4Tmp;
-+	u16 				*pu2Tmp;
-+	u8 				*pu1Tmp;
-+
-+	/*  */
-+	/* check upper layer parameters */
-+	/*  */
-+
-+	/* check upper layer opcode version */
-+	if (pBtReq->opCodeVer != 1) {
-+		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
-+		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
-+		return paraLen;
-+	}
-+	/* check upper layer parameter length */
-+	if (pBtReq->paraLength < 1) {
-+		RTW_INFO("[MPT], Error!! wrong parameter length=%d (should larger than 1)\n", pBtReq->paraLength);
-+		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
-+		return paraLen;
-+	}
-+	setParaLen = pBtReq->paraLength - 1;
-+	setType = pBtReq->pParamStart[0];
-+
-+	RTW_INFO("[MPT], setType=%d, setParaLen=%d\n", setType, setParaLen);
-+
-+	/* check parameter first */
-+	switch (setType) {
-+	case BT_GSET_REG:
-+		RTW_INFO("[MPT], [BT_GSET_REG]\n");
-+		validParaLen = 9;
-+		if (setParaLen == validParaLen) {
-+			btOpcode = BT_LO_OP_WRITE_REG_VALUE;
-+			regType = pBtReq->pParamStart[1];
-+			pu4Tmp = (u32 *)&pBtReq->pParamStart[2];
-+			regAddr = *pu4Tmp;
-+			pu4Tmp = (u32 *)&pBtReq->pParamStart[6];
-+			regValue = *pu4Tmp;
-+			RTW_INFO("[MPT], BT_GSET_REG regType=0x%x, regAddr=0x%x, regValue=0x%x!!\n",
-+				 regType, regAddr, regValue);
-+			if (regType >= BT_REG_MAX) {
-+				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+				return paraLen;
-+			} else {
-+				if (((BT_REG_RF == regType) && (regAddr > 0x7f)) ||
-+				    ((BT_REG_MODEM == regType) && (regAddr > 0x1ff)) ||
-+				    ((BT_REG_BLUEWIZE == regType) && (regAddr > 0xfff)) ||
-+				    ((BT_REG_VENDOR == regType) && (regAddr > 0xfff)) ||
-+				    ((BT_REG_LE == regType) && (regAddr > 0xfff))) {
-+					pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+					return paraLen;
-+				}
-+			}
-+		}
-+		break;
-+	case BT_GSET_RESET:
-+		RTW_INFO("[MPT], [BT_GSET_RESET]\n");
-+		validParaLen = 0;
-+		break;
-+	case BT_GSET_TARGET_BD_ADDR:
-+		RTW_INFO("[MPT], [BT_GSET_TARGET_BD_ADDR]\n");
-+		validParaLen = 6;
-+		if (setParaLen == validParaLen) {
-+			btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_H;
-+			if ((pBtReq->pParamStart[1] == 0) &&
-+			    (pBtReq->pParamStart[2] == 0) &&
-+			    (pBtReq->pParamStart[3] == 0) &&
-+			    (pBtReq->pParamStart[4] == 0) &&
-+			    (pBtReq->pParamStart[5] == 0) &&
-+			    (pBtReq->pParamStart[6] == 0)) {
-+				RTW_INFO("[MPT], Error!! targetBDAddr=all zero\n");
-+				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+				return paraLen;
-+			}
-+			if ((pBtReq->pParamStart[1] == 0xff) &&
-+			    (pBtReq->pParamStart[2] == 0xff) &&
-+			    (pBtReq->pParamStart[3] == 0xff) &&
-+			    (pBtReq->pParamStart[4] == 0xff) &&
-+			    (pBtReq->pParamStart[5] == 0xff) &&
-+			    (pBtReq->pParamStart[6] == 0xff)) {
-+				RTW_INFO("[MPT], Error!! targetBDAddr=all 0xf\n");
-+				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+				return paraLen;
-+			}
-+			bdAddr[0] = pBtReq->pParamStart[6];
-+			bdAddr[1] = pBtReq->pParamStart[5];
-+			bdAddr[2] = pBtReq->pParamStart[4];
-+			bdAddr[3] = pBtReq->pParamStart[3];
-+			bdAddr[4] = pBtReq->pParamStart[2];
-+			bdAddr[5] = pBtReq->pParamStart[1];
-+			RTW_INFO("[MPT], target BDAddr:%x,%x,%x,%x,%x,%x\n",
-+				bdAddr[0], bdAddr[1], bdAddr[2], bdAddr[3], bdAddr[4], bdAddr[5]);
-+		}
-+		break;
-+	case BT_GSET_TX_PWR_FINETUNE:
-+		RTW_INFO("[MPT], [BT_GSET_TX_PWR_FINETUNE]\n");
-+		validParaLen = 1;
-+		if (setParaLen == validParaLen) {
-+			btOpcode = BT_LO_OP_SET_TX_POWER_CALIBRATION;
-+			calVal = pBtReq->pParamStart[1];
-+			if ((calVal < 1) || (calVal > 9)) {
-+				pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+				return paraLen;
-+			}
-+			RTW_INFO("[MPT], calVal=%d\n", calVal);
-+		}
-+		break;
-+	case BT_SET_TRACKING_INTERVAL:
-+		RTW_INFO("[MPT], [BT_SET_TRACKING_INTERVAL] setParaLen =%d\n", setParaLen);
-+
-+		validParaLen = 1;
-+		if (setParaLen == validParaLen)
-+			calVal = pBtReq->pParamStart[1];
-+		break;
-+	case BT_SET_THERMAL_METER:
-+		RTW_INFO("[MPT], [BT_SET_THERMAL_METER] setParaLen =%d\n", setParaLen);
-+		validParaLen = 1;
-+		if (setParaLen == validParaLen)
-+			calVal = pBtReq->pParamStart[1];
-+		break;
-+	case BT_ENABLE_CFO_TRACKING:
-+		RTW_INFO("[MPT], [BT_ENABLE_CFO_TRACKING] setParaLen =%d\n", setParaLen);
-+		validParaLen = 1;
-+		if (setParaLen == validParaLen)
-+			calVal = pBtReq->pParamStart[1];
-+		break;
-+	case BT_GSET_UPDATE_BT_PATCH:
-+
-+		break;
-+	default: {
-+		RTW_INFO("[MPT], Error!! setType=%d, out of range\n", setType);
-+		pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+		return paraLen;
-+	}
-+	break;
-+	}
-+	if (setParaLen != validParaLen) {
-+		RTW_INFO("[MPT], Error!! wrong parameter length=%d for BT_SET_GEN_CMD cmd id=0x%x, paraLen should=0x%x\n",
-+			 setParaLen, setType, validParaLen);
-+		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
-+		return paraLen;
-+	}
-+
-+	/*  */
-+	/* execute lower layer opcodes */
-+	/*  */
-+	if (BT_GSET_REG == setType) {
-+		/* fill h2c parameters */
-+		/* here we should write reg value first then write the address, adviced by Austin */
-+		btOpcode = BT_LO_OP_WRITE_REG_VALUE;
-+		h2cParaBuf[0] = pBtReq->pParamStart[6];
-+		h2cParaBuf[1] = pBtReq->pParamStart[7];
-+		h2cParaBuf[2] = pBtReq->pParamStart[8];
-+		h2cParaLen = 3;
-+		/* execute h2c and check respond c2h from bt fw is correct or not */
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+		/* construct respond status code and data. */
-+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+			pBtRsp->status = ((btOpcode << 8) | retStatus);
-+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+			return paraLen;
-+		}
-+
-+		/* write reg address */
-+		btOpcode = BT_LO_OP_WRITE_REG_ADDR;
-+		h2cParaBuf[0] = regType;
-+		h2cParaBuf[1] = pBtReq->pParamStart[2];
-+		h2cParaBuf[2] = pBtReq->pParamStart[3];
-+		h2cParaLen = 3;
-+		/* execute h2c and check respond c2h from bt fw is correct or not */
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+		/* construct respond status code and data. */
-+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+			pBtRsp->status = ((btOpcode << 8) | retStatus);
-+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+			return paraLen;
-+		}
-+	} else if (BT_GSET_RESET == setType) {
-+		btOpcode = BT_LO_OP_RESET;
-+		h2cParaLen = 0;
-+		/* execute h2c and check respond c2h from bt fw is correct or not */
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+		/* construct respond status code and data. */
-+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+			pBtRsp->status = ((btOpcode << 8) | retStatus);
-+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+			return paraLen;
-+		}
-+	} else if (BT_GSET_TARGET_BD_ADDR == setType) {
-+		/* fill h2c parameters */
-+		btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_L;
-+		h2cParaBuf[0] = pBtReq->pParamStart[1];
-+		h2cParaBuf[1] = pBtReq->pParamStart[2];
-+		h2cParaBuf[2] = pBtReq->pParamStart[3];
-+		h2cParaLen = 3;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+		/* ckeck bt return status. */
-+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+			pBtRsp->status = ((btOpcode << 8) | retStatus);
-+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+			return paraLen;
-+		}
-+
-+		btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_H;
-+		h2cParaBuf[0] = pBtReq->pParamStart[4];
-+		h2cParaBuf[1] = pBtReq->pParamStart[5];
-+		h2cParaBuf[2] = pBtReq->pParamStart[6];
-+		h2cParaLen = 3;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+		/* ckeck bt return status. */
-+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+			pBtRsp->status = ((btOpcode << 8) | retStatus);
-+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+			return paraLen;
-+		}
-+	} else if (BT_GSET_TX_PWR_FINETUNE == setType) {
-+		/* fill h2c parameters */
-+		btOpcode = BT_LO_OP_SET_TX_POWER_CALIBRATION;
-+		h2cParaBuf[0] = calVal;
-+		h2cParaLen = 1;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+		/* ckeck bt return status. */
-+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+			pBtRsp->status = ((btOpcode << 8) | retStatus);
-+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+			return paraLen;
-+		}
-+	} else if (BT_SET_TRACKING_INTERVAL == setType) {
-+		/*	BT_LO_OP_SET_TRACKING_INTERVAL								= 0x22, */
-+		/*	BT_LO_OP_SET_THERMAL_METER									= 0x23, */
-+		/*	BT_LO_OP_ENABLE_CFO_TRACKING									= 0x24, */
-+		btOpcode = BT_LO_OP_SET_TRACKING_INTERVAL;
-+		h2cParaBuf[0] = calVal;
-+		h2cParaLen = 1;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+		/* ckeck bt return status. */
-+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+			pBtRsp->status = ((btOpcode << 8) | retStatus);
-+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+			return paraLen;
-+		}
-+	} else if (BT_SET_THERMAL_METER == setType) {
-+		btOpcode = BT_LO_OP_SET_THERMAL_METER;
-+		h2cParaBuf[0] = calVal;
-+		h2cParaLen = 1;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+		/* ckeck bt return status. */
-+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+			pBtRsp->status = ((btOpcode << 8) | retStatus);
-+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+			return paraLen;
-+		}
-+	} else if (BT_ENABLE_CFO_TRACKING == setType) {
-+		btOpcode = BT_LO_OP_ENABLE_CFO_TRACKING;
-+		h2cParaBuf[0] = calVal;
-+		h2cParaLen = 1;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+		/* ckeck bt return status. */
-+		if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+			pBtRsp->status = ((btOpcode << 8) | retStatus);
-+			RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+			return paraLen;
-+		}
-+	}
-+
-+	pBtRsp->status = BT_STATUS_SUCCESS;
-+	return paraLen;
-+}
-+
-+
-+
-+u16
-+mptbt_BtSetTxRxPars(
-+		PADAPTER		Adapter,
-+		PBT_REQ_CMD	pBtReq,
-+		PBT_RSP_CMD	pBtRsp
-+)
-+{
-+	u8				h2cParaBuf[6] = {0};
-+	u8				h2cParaLen = 0;
-+	u16				paraLen = 0;
-+	u8				retStatus = BT_STATUS_BT_OP_SUCCESS;
-+	u8				btOpcode;
-+	u8				btOpcodeVer = 0;
-+	PBT_TXRX_PARAMETERS pTxRxPars = (PBT_TXRX_PARAMETERS)&pBtReq->pParamStart[0];
-+	u16				lenTxRx = sizeof(BT_TXRX_PARAMETERS);
-+	u8				i;
-+	u8				bdAddr[6] = {0};
-+
-+	/*  */
-+	/* check upper layer parameters */
-+	/*  */
-+
-+	/* 1. check upper layer opcode version */
-+	if (pBtReq->opCodeVer != 1) {
-+		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
-+		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
-+		return paraLen;
-+	}
-+	/* 2. check upper layer parameter length */
-+	if (pBtReq->paraLength == sizeof(BT_TXRX_PARAMETERS)) {
-+		RTW_INFO("[MPT], pTxRxPars->txrxChannel=0x%x\n", pTxRxPars->txrxChannel);
-+		RTW_INFO("[MPT], pTxRxPars->txrxTxPktCnt=0x%8x\n", pTxRxPars->txrxTxPktCnt);
-+		RTW_INFO("[MPT], pTxRxPars->txrxTxPktInterval=0x%x\n", pTxRxPars->txrxTxPktInterval);
-+		RTW_INFO("[MPT], pTxRxPars->txrxPayloadType=0x%x\n", pTxRxPars->txrxPayloadType);
-+		RTW_INFO("[MPT], pTxRxPars->txrxPktType=0x%x\n", pTxRxPars->txrxPktType);
-+		RTW_INFO("[MPT], pTxRxPars->txrxPayloadLen=0x%x\n", pTxRxPars->txrxPayloadLen);
-+		RTW_INFO("[MPT], pTxRxPars->txrxPktHeader=0x%x\n", pTxRxPars->txrxPktHeader);
-+		RTW_INFO("[MPT], pTxRxPars->txrxWhitenCoeff=0x%x\n", pTxRxPars->txrxWhitenCoeff);
-+		bdAddr[0] = pTxRxPars->txrxBdaddr[5];
-+		bdAddr[1] = pTxRxPars->txrxBdaddr[4];
-+		bdAddr[2] = pTxRxPars->txrxBdaddr[3];
-+		bdAddr[3] = pTxRxPars->txrxBdaddr[2];
-+		bdAddr[4] = pTxRxPars->txrxBdaddr[1];
-+		bdAddr[5] = pTxRxPars->txrxBdaddr[0];
-+		RTW_INFO("[MPT], pTxRxPars->txrxBdaddr: %s", &bdAddr[0]);
-+		RTW_INFO("[MPT], pTxRxPars->txrxTxGainIndex=0x%x\n", pTxRxPars->txrxTxGainIndex);
-+	} else {
-+		RTW_INFO("[MPT], Error!! pBtReq->paraLength=%d, correct Len=%d\n", pBtReq->paraLength, lenTxRx);
-+		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
-+		return paraLen;
-+	}
-+
-+	/*  */
-+	/* execute lower layer opcodes */
-+	/*  */
-+
-+	/* fill h2c parameters */
-+	btOpcode = BT_LO_OP_SET_PKT_HEADER;
-+	if (pTxRxPars->txrxPktHeader > 0x3ffff) {
-+		RTW_INFO("[MPT], Error!! pTxRxPars->txrxPktHeader=0x%x is out of range, (should be between 0x0~0x3ffff)\n", pTxRxPars->txrxPktHeader);
-+		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+		return paraLen;
-+	} else {
-+		h2cParaBuf[0] = (u8)(pTxRxPars->txrxPktHeader & 0xff);
-+		h2cParaBuf[1] = (u8)((pTxRxPars->txrxPktHeader & 0xff00) >> 8);
-+		h2cParaBuf[2] = (u8)((pTxRxPars->txrxPktHeader & 0xff0000) >> 16);
-+		h2cParaLen = 3;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+	}
-+
-+	/* ckeck bt return status. */
-+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+		pBtRsp->status = ((btOpcode << 8) | retStatus);
-+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+		return paraLen;
-+	}
-+
-+	/* fill h2c parameters */
-+	btOpcode = BT_LO_OP_SET_PKT_TYPE_LEN;
-+	{
-+		u16	payloadLenLimit = 0;
-+		switch (pTxRxPars->txrxPktType) {
-+		case MP_BT_PKT_DH1:
-+			payloadLenLimit = 27 * 8;
-+			break;
-+		case MP_BT_PKT_DH3:
-+			payloadLenLimit = 183 * 8;
-+			break;
-+		case MP_BT_PKT_DH5:
-+			payloadLenLimit = 339 * 8;
-+			break;
-+		case MP_BT_PKT_2DH1:
-+			payloadLenLimit = 54 * 8;
-+			break;
-+		case MP_BT_PKT_2DH3:
-+			payloadLenLimit = 367 * 8;
-+			break;
-+		case MP_BT_PKT_2DH5:
-+			payloadLenLimit = 679 * 8;
-+			break;
-+		case MP_BT_PKT_3DH1:
-+			payloadLenLimit = 83 * 8;
-+			break;
-+		case MP_BT_PKT_3DH3:
-+			payloadLenLimit = 552 * 8;
-+			break;
-+		case MP_BT_PKT_3DH5:
-+			payloadLenLimit = 1021 * 8;
-+			break;
-+		case MP_BT_PKT_LE:
-+			payloadLenLimit = 39 * 8;
-+			break;
-+		default: {
-+			RTW_INFO("[MPT], Error!! Unknown pTxRxPars->txrxPktType=0x%x\n", pTxRxPars->txrxPktType);
-+			pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+			return paraLen;
-+		}
-+		break;
-+		}
-+
-+		if (pTxRxPars->txrxPayloadLen > payloadLenLimit) {
-+			RTW_INFO("[MPT], Error!! pTxRxPars->txrxPayloadLen=0x%x, (should smaller than %d)\n",
-+				 pTxRxPars->txrxPayloadLen, payloadLenLimit);
-+			pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+			return paraLen;
-+		}
-+
-+		h2cParaBuf[0] = pTxRxPars->txrxPktType;
-+		h2cParaBuf[1] = (u8)((pTxRxPars->txrxPayloadLen & 0xff));
-+		h2cParaBuf[2] = (u8)((pTxRxPars->txrxPayloadLen & 0xff00) >> 8);
-+		h2cParaLen = 3;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+	}
-+
-+	/* ckeck bt return status. */
-+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+		pBtRsp->status = ((btOpcode << 8) | retStatus);
-+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+		return paraLen;
-+	}
-+
-+	/* fill h2c parameters */
-+	btOpcode = BT_LO_OP_SET_PKT_CNT_L_PL_TYPE;
-+	if (pTxRxPars->txrxPayloadType > MP_BT_PAYLOAD_MAX) {
-+		RTW_INFO("[MPT], Error!! pTxRxPars->txrxPayloadType=0x%x, (should be between 0~4)\n", pTxRxPars->txrxPayloadType);
-+		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+		return paraLen;
-+	} else {
-+		h2cParaBuf[0] = (u8)((pTxRxPars->txrxTxPktCnt & 0xff));
-+		h2cParaBuf[1] = (u8)((pTxRxPars->txrxTxPktCnt & 0xff00) >> 8);
-+		h2cParaBuf[2] = pTxRxPars->txrxPayloadType;
-+		h2cParaLen = 3;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+	}
-+
-+	/* ckeck bt return status. */
-+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+		pBtRsp->status = ((btOpcode << 8) | retStatus);
-+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+		return paraLen;
-+	}
-+
-+	/* fill h2c parameters */
-+	btOpcode = BT_LO_OP_SET_PKT_CNT_H_PKT_INTV;
-+	if (pTxRxPars->txrxTxPktInterval > 15) {
-+		RTW_INFO("[MPT], Error!! pTxRxPars->txrxTxPktInterval=0x%x, (should be between 0~15)\n", pTxRxPars->txrxTxPktInterval);
-+		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+		return paraLen;
-+	} else {
-+		h2cParaBuf[0] = (u8)((pTxRxPars->txrxTxPktCnt & 0xff0000) >> 16);
-+		h2cParaBuf[1] = (u8)((pTxRxPars->txrxTxPktCnt & 0xff000000) >> 24);
-+		h2cParaBuf[2] = pTxRxPars->txrxTxPktInterval;
-+		h2cParaLen = 3;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+	}
-+
-+	/* ckeck bt return status. */
-+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+		pBtRsp->status = ((btOpcode << 8) | retStatus);
-+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+		return paraLen;
-+	}
-+
-+	/* fill h2c parameters */
-+	btOpcode = BT_LO_OP_SET_WHITENCOEFF;
-+	{
-+		h2cParaBuf[0] = pTxRxPars->txrxWhitenCoeff;
-+		h2cParaLen = 1;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+	}
-+
-+	/* ckeck bt return status. */
-+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+		pBtRsp->status = ((btOpcode << 8) | retStatus);
-+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+		return paraLen;
-+	}
-+
-+
-+	/* fill h2c parameters */
-+	btOpcode = BT_LO_OP_SET_CHNL_TX_GAIN;
-+	if ((pTxRxPars->txrxChannel > 78) ||
-+	    (pTxRxPars->txrxTxGainIndex > 7)) {
-+		RTW_INFO("[MPT], Error!! pTxRxPars->txrxChannel=0x%x, (should be between 0~78)\n", pTxRxPars->txrxChannel);
-+		RTW_INFO("[MPT], Error!! pTxRxPars->txrxTxGainIndex=0x%x, (should be between 0~7)\n", pTxRxPars->txrxTxGainIndex);
-+		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+		return paraLen;
-+	} else {
-+		h2cParaBuf[0] = pTxRxPars->txrxChannel;
-+		h2cParaBuf[1] = pTxRxPars->txrxTxGainIndex;
-+		h2cParaLen = 2;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+	}
-+
-+	/* ckeck bt return status. */
-+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+		pBtRsp->status = ((btOpcode << 8) | retStatus);
-+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+		return paraLen;
-+	}
-+
-+	/* fill h2c parameters */
-+	btOpcode = BT_LO_OP_SET_BD_ADDR_L;
-+	if ((pTxRxPars->txrxBdaddr[0] == 0) &&
-+	    (pTxRxPars->txrxBdaddr[1] == 0) &&
-+	    (pTxRxPars->txrxBdaddr[2] == 0) &&
-+	    (pTxRxPars->txrxBdaddr[3] == 0) &&
-+	    (pTxRxPars->txrxBdaddr[4] == 0) &&
-+	    (pTxRxPars->txrxBdaddr[5] == 0)) {
-+		RTW_INFO("[MPT], Error!! pTxRxPars->txrxBdaddr=all zero\n");
-+		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+		return paraLen;
-+	}
-+	if ((pTxRxPars->txrxBdaddr[0] == 0xff) &&
-+	    (pTxRxPars->txrxBdaddr[1] == 0xff) &&
-+	    (pTxRxPars->txrxBdaddr[2] == 0xff) &&
-+	    (pTxRxPars->txrxBdaddr[3] == 0xff) &&
-+	    (pTxRxPars->txrxBdaddr[4] == 0xff) &&
-+	    (pTxRxPars->txrxBdaddr[5] == 0xff)) {
-+		RTW_INFO("[MPT], Error!! pTxRxPars->txrxBdaddr=all 0xf\n");
-+		pBtRsp->status = (btOpcode << 8) | BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+		return paraLen;
-+	}
-+
-+	{
-+		h2cParaBuf[0] = pTxRxPars->txrxBdaddr[0];
-+		h2cParaBuf[1] = pTxRxPars->txrxBdaddr[1];
-+		h2cParaBuf[2] = pTxRxPars->txrxBdaddr[2];
-+		h2cParaLen = 3;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+	}
-+	/* ckeck bt return status. */
-+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+		pBtRsp->status = ((btOpcode << 8) | retStatus);
-+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+		return paraLen;
-+	}
-+
-+	btOpcode = BT_LO_OP_SET_BD_ADDR_H;
-+	{
-+		h2cParaBuf[0] = pTxRxPars->txrxBdaddr[3];
-+		h2cParaBuf[1] = pTxRxPars->txrxBdaddr[4];
-+		h2cParaBuf[2] = pTxRxPars->txrxBdaddr[5];
-+		h2cParaLen = 3;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+	}
-+	/* ckeck bt return status. */
-+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+		pBtRsp->status = ((btOpcode << 8) | retStatus);
-+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+		return paraLen;
-+	}
-+
-+	pBtRsp->status = BT_STATUS_SUCCESS;
-+	return paraLen;
-+}
-+
-+
-+
-+u16
-+mptbt_BtTestCtrl(
-+		PADAPTER		Adapter,
-+		PBT_REQ_CMD	pBtReq,
-+		PBT_RSP_CMD	pBtRsp
-+)
-+{
-+	u8				h2cParaBuf[6] = {0};
-+	u8				h2cParaLen = 0;
-+	u16				paraLen = 0;
-+	u8				retStatus = BT_STATUS_BT_OP_SUCCESS;
-+	u8				btOpcode;
-+	u8				btOpcodeVer = 0;
-+	u8				testCtrl = 0;
-+
-+	/*  */
-+	/* check upper layer parameters */
-+	/*  */
-+
-+	/* 1. check upper layer opcode version */
-+	if (pBtReq->opCodeVer != 1) {
-+		RTW_INFO("[MPT], Error!! Upper OP code version not match!!!\n");
-+		pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH;
-+		return paraLen;
-+	}
-+	/* 2. check upper layer parameter length */
-+	if (1 == pBtReq->paraLength) {
-+		testCtrl = pBtReq->pParamStart[0];
-+		RTW_INFO("[MPT], testCtrl=%d\n", testCtrl);
-+	} else {
-+		RTW_INFO("[MPT], Error!! wrong parameter length=%d (should be 1)\n", pBtReq->paraLength);
-+		pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U;
-+		return paraLen;
-+	}
-+
-+	/*  */
-+	/* execute lower layer opcodes */
-+	/*  */
-+
-+	/* 1. fill h2c parameters	 */
-+	/* check bt mode */
-+	btOpcode = BT_LO_OP_TEST_CTRL;
-+	if (testCtrl >= MP_BT_TEST_MAX) {
-+		RTW_INFO("[MPT], Error!! testCtrl=0x%x, (should be between smaller or equal to 0x%x)\n",
-+			 testCtrl, MP_BT_TEST_MAX - 1);
-+		pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U;
-+		return paraLen;
-+	} else {
-+		h2cParaBuf[0] = testCtrl;
-+		h2cParaLen = 1;
-+		retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen);
-+	}
-+
-+	/* 3. construct respond status code and data. */
-+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+		pBtRsp->status = ((btOpcode << 8) | retStatus);
-+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+		return paraLen;
-+	}
-+
-+	pBtRsp->status = BT_STATUS_SUCCESS;
-+	return paraLen;
-+}
-+
-+
-+u16
-+mptbt_TestBT(
-+		PADAPTER		Adapter,
-+		PBT_REQ_CMD	pBtReq,
-+		PBT_RSP_CMD	pBtRsp
-+)
-+{
-+
-+	u8				h2cParaBuf[6] = {0};
-+	u8				h2cParaLen = 0;
-+	u16				paraLen = 0;
-+	u8				retStatus = BT_STATUS_BT_OP_SUCCESS;
-+	u8				btOpcode;
-+	u8				btOpcodeVer = 0;
-+	u8				testCtrl = 0;
-+
-+	/* 1. fill h2c parameters	 */
-+	btOpcode =  0x11;
-+	h2cParaBuf[0] = 0x11;
-+	h2cParaBuf[1] = 0x0;
-+	h2cParaBuf[2] = 0x0;
-+	h2cParaBuf[3] = 0x0;
-+	h2cParaBuf[4] = 0x0;
-+	h2cParaLen = 1;
-+	/*	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); */
-+	retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, h2cParaBuf, h2cParaLen);
-+
-+
-+	/* 3. construct respond status code and data. */
-+	if (BT_STATUS_BT_OP_SUCCESS != retStatus) {
-+		pBtRsp->status = ((btOpcode << 8) | retStatus);
-+		RTW_INFO("[MPT], Error!! status code=0x%x\n", pBtRsp->status);
-+		return paraLen;
-+	}
-+
-+	pBtRsp->status = BT_STATUS_SUCCESS;
-+	return paraLen;
-+}
-+
-+void
-+mptbt_BtControlProcess(
-+	PADAPTER	Adapter,
-+	void			*pInBuf
-+)
-+{
-+	u8			H2C_Parameter[6] = {0};
-+	PBT_H2C		pH2c = (PBT_H2C)&H2C_Parameter[0];
-+	PMPT_CONTEXT	pMptCtx = &(Adapter->mppriv.mpt_ctx);
-+	PBT_REQ_CMD	pBtReq = (PBT_REQ_CMD)pInBuf;
-+	PBT_RSP_CMD	pBtRsp;
-+	u8			i;
-+
-+
-+	RTW_INFO("[MPT], mptbt_BtControlProcess()=========>\n");
-+
-+	RTW_INFO("[MPT], input opCodeVer=%d\n", pBtReq->opCodeVer);
-+	RTW_INFO("[MPT], input OpCode=%d\n", pBtReq->OpCode);
-+	RTW_INFO("[MPT], paraLength=%d\n", pBtReq->paraLength);
-+	if (pBtReq->paraLength) {
-+		/* RTW_INFO("[MPT], parameters(hex):0x%x %d\n",&pBtReq->pParamStart[0], pBtReq->paraLength); */
-+	}
-+
-+	_rtw_memset((void *)pMptCtx->mptOutBuf, 0, 100);
-+	pMptCtx->mptOutLen = 4; /* length of (BT_RSP_CMD.status+BT_RSP_CMD.paraLength) */
-+
-+	pBtRsp = (PBT_RSP_CMD)pMptCtx->mptOutBuf;
-+	pBtRsp->status = BT_STATUS_SUCCESS;
-+	pBtRsp->paraLength = 0x0;
-+
-+	/* The following we should maintain the User OP codes sent by upper layer */
-+	switch (pBtReq->OpCode) {
-+	case BT_UP_OP_BT_READY:
-+		RTW_INFO("[MPT], OPcode : [BT_READY]\n");
-+		pBtRsp->paraLength = mptbt_BtReady(Adapter, pBtReq, pBtRsp);
-+		break;
-+	case BT_UP_OP_BT_SET_MODE:
-+		RTW_INFO("[MPT], OPcode : [BT_SET_MODE]\n");
-+		pBtRsp->paraLength = mptbt_BtSetMode(Adapter, pBtReq, pBtRsp);
-+		break;
-+	case BT_UP_OP_BT_SET_TX_RX_PARAMETER:
-+		RTW_INFO("[MPT], OPcode : [BT_SET_TXRX_PARAMETER]\n");
-+		pBtRsp->paraLength = mptbt_BtSetTxRxPars(Adapter, pBtReq, pBtRsp);
-+		break;
-+	case BT_UP_OP_BT_SET_GENERAL:
-+		RTW_INFO("[MPT], OPcode : [BT_SET_GENERAL]\n");
-+		pBtRsp->paraLength = mptbt_BtSetGeneral(Adapter, pBtReq, pBtRsp);
-+		break;
-+	case BT_UP_OP_BT_GET_GENERAL:
-+		RTW_INFO("[MPT], OPcode : [BT_GET_GENERAL]\n");
-+		pBtRsp->paraLength = mptbt_BtGetGeneral(Adapter, pBtReq, pBtRsp);
-+		break;
-+	case BT_UP_OP_BT_TEST_CTRL:
-+		RTW_INFO("[MPT], OPcode : [BT_TEST_CTRL]\n");
-+		pBtRsp->paraLength = mptbt_BtTestCtrl(Adapter, pBtReq, pBtRsp);
-+		break;
-+	case BT_UP_OP_TEST_BT:
-+		RTW_INFO("[MPT], OPcode : [TEST_BT]\n");
-+		pBtRsp->paraLength = mptbt_TestBT(Adapter, pBtReq, pBtRsp);
-+		break;
-+	default:
-+		RTW_INFO("[MPT], Error!! OPcode : UNDEFINED!!!!\n");
-+		pBtRsp->status = BT_STATUS_UNKNOWN_OPCODE_U;
-+		pBtRsp->paraLength = 0x0;
-+		break;
-+	}
-+
-+	pMptCtx->mptOutLen += pBtRsp->paraLength;
-+
-+	RTW_INFO("[MPT], pMptCtx->mptOutLen=%d, pBtRsp->paraLength=%d\n", pMptCtx->mptOutLen, pBtRsp->paraLength);
-+	RTW_INFO("[MPT], mptbt_BtControlProcess()<=========\n");
-+}
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/core/rtw_btcoex.c b/drivers/staging/rtl8723cs/core/rtw_btcoex.c
-new file mode 100644
-index 000000000000..5081cddfc2c7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_btcoex.c
-@@ -0,0 +1,1817 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include <drv_types.h>
-+#include <hal_data.h>
-+#ifdef CONFIG_BT_COEXIST
-+#include <hal_btcoex.h>
-+
-+void rtw_btcoex_Initialize(PADAPTER padapter)
-+{
-+	hal_btcoex_Initialize(padapter);
-+}
-+
-+void rtw_btcoex_PowerOnSetting(PADAPTER padapter)
-+{
-+	hal_btcoex_PowerOnSetting(padapter);
-+}
-+
-+void rtw_btcoex_AntInfoSetting(PADAPTER padapter)
-+{
-+	hal_btcoex_AntInfoSetting(padapter);
-+}
-+
-+void rtw_btcoex_PowerOffSetting(PADAPTER padapter)
-+{
-+	hal_btcoex_PowerOffSetting(padapter);
-+}
-+
-+void rtw_btcoex_PreLoadFirmware(PADAPTER padapter)
-+{
-+	hal_btcoex_PreLoadFirmware(padapter);
-+}
-+
-+void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly)
-+{
-+	hal_btcoex_InitHwConfig(padapter, bWifiOnly);
-+}
-+
-+void rtw_btcoex_IpsNotify(PADAPTER padapter, u8 type)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+		return;
-+
-+	hal_btcoex_IpsNotify(padapter, type);
-+}
-+
-+void rtw_btcoex_LpsNotify(PADAPTER padapter, u8 type)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+		return;
-+
-+	hal_btcoex_LpsNotify(padapter, type);
-+}
-+
-+void rtw_btcoex_ScanNotify(PADAPTER padapter, u8 type)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+	PBT_MGNT	pBtMgnt = &pcoex_info->BtMgnt;
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+		return;
-+
-+	if (_FALSE == type) {
-+		#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_SURVEY))
-+			return;
-+		#endif
-+
-+		if (DEV_MGMT_TX_NUM(adapter_to_dvobj(padapter))
-+			|| DEV_ROCH_NUM(adapter_to_dvobj(padapter)))
-+			return;
-+	}
-+
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+	if (pBtMgnt->ExtConfig.bEnableWifiScanNotify)
-+		rtw_btcoex_SendScanNotify(padapter, type);
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX	 */
-+
-+	hal_btcoex_ScanNotify(padapter, type);
-+}
-+
-+static void _rtw_btcoex_connect_notify(PADAPTER padapter, u8 action)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+		return;
-+
-+#ifdef DBG_CONFIG_ERROR_RESET
-+	if (_TRUE == rtw_hal_sreset_inprogress(padapter)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": [BTCoex] under reset, skip notify!\n",
-+			 FUNC_ADPT_ARG(padapter));
-+		return;
-+	}
-+#endif /* DBG_CONFIG_ERROR_RESET */
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (_FALSE == action) {
-+		if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING))
-+			return;
-+	}
-+#endif
-+
-+	hal_btcoex_ConnectNotify(padapter, action);
-+}
-+
-+void rtw_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+		return;
-+
-+#ifdef DBG_CONFIG_ERROR_RESET
-+	if (_TRUE == rtw_hal_sreset_inprogress(padapter)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": [BTCoex] under reset, skip notify!\n",
-+			 FUNC_ADPT_ARG(padapter));
-+		return;
-+	}
-+#endif /* DBG_CONFIG_ERROR_RESET */
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (RT_MEDIA_DISCONNECT == mediaStatus) {
-+		if (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE))
-+			return;
-+	}
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+	if ((RT_MEDIA_CONNECT == mediaStatus)
-+	    && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE))
-+		rtw_hal_set_hwreg(padapter, HW_VAR_DL_RSVD_PAGE, NULL);
-+
-+	hal_btcoex_MediaStatusNotify(padapter, mediaStatus);
-+}
-+
-+void rtw_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+		return;
-+
-+	hal_btcoex_SpecialPacketNotify(padapter, pktType);
-+}
-+
-+void rtw_btcoex_IQKNotify(PADAPTER padapter, u8 state)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+		return;
-+
-+	hal_btcoex_IQKNotify(padapter, state);
-+}
-+
-+void rtw_btcoex_WLRFKNotify(PADAPTER padapter, u8 path, u8 type, u8 state)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+		return;
-+
-+	hal_btcoex_WLRFKNotify(padapter, path, type, state);
-+}
-+
-+void rtw_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+		return;
-+
-+	hal_btcoex_BtInfoNotify(padapter, length, tmpBuf);
-+}
-+
-+void rtw_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+		return;
-+
-+	if (padapter->registrypriv.mp_mode == 1)
-+		return;
-+
-+	hal_btcoex_BtMpRptNotify(padapter, length, tmpBuf);
-+}
-+
-+void rtw_btcoex_SuspendNotify(PADAPTER padapter, u8 state)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+		return;
-+
-+	hal_btcoex_SuspendNotify(padapter, state);
-+}
-+
-+void rtw_btcoex_HaltNotify(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+	u8 do_halt = 1;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+		do_halt = 0;
-+
-+	if (_FALSE == padapter->bup) {
-+		RTW_INFO(FUNC_ADPT_FMT ": bup=%d Skip!\n",
-+			 FUNC_ADPT_ARG(padapter), padapter->bup);
-+		do_halt = 0;
-+	}
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=%s Skip!\n",
-+			FUNC_ADPT_ARG(padapter), rtw_is_surprise_removed(padapter) ? "True" : "False");
-+		do_halt = 0;
-+	}
-+
-+	hal_btcoex_HaltNotify(padapter, do_halt);
-+}
-+
-+void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type)
-+{
-+	hal_btcoex_switchband_notify(under_scan, band_type);
-+}
-+
-+void rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length)
-+{
-+	hal_btcoex_WlFwDbgInfoNotify(padapter, tmpBuf, length);
-+}
-+
-+void rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id)
-+{
-+	hal_btcoex_rx_rate_change_notify(padapter, is_data_frame, rate_id);
-+}
-+
-+void rtw_btcoex_SwitchBtTRxMask(PADAPTER padapter)
-+{
-+	hal_btcoex_SwitchBtTRxMask(padapter);
-+}
-+
-+void rtw_btcoex_Switch(PADAPTER padapter, u8 enable)
-+{
-+	hal_btcoex_SetBTCoexist(padapter, enable);
-+}
-+
-+u8 rtw_btcoex_IsBtDisabled(PADAPTER padapter)
-+{
-+	return hal_btcoex_IsBtDisabled(padapter);
-+}
-+
-+void rtw_btcoex_Handler(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	if (_FALSE == pHalData->EEPROMBluetoothCoexist)
-+		return;
-+
-+	hal_btcoex_Hanlder(padapter);
-+}
-+
-+s32 rtw_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter)
-+{
-+	s32 coexctrl;
-+
-+	coexctrl = hal_btcoex_IsBTCoexRejectAMPDU(padapter);
-+
-+	return coexctrl;
-+}
-+
-+s32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter)
-+{
-+	s32 coexctrl;
-+
-+	coexctrl = hal_btcoex_IsBTCoexCtrlAMPDUSize(padapter);
-+
-+	return coexctrl;
-+}
-+
-+u32 rtw_btcoex_GetAMPDUSize(PADAPTER padapter)
-+{
-+	u32 size;
-+
-+	size = hal_btcoex_GetAMPDUSize(padapter);
-+
-+	return size;
-+}
-+
-+void rtw_btcoex_SetManualControl(PADAPTER padapter, u8 manual)
-+{
-+	if (_TRUE == manual)
-+		hal_btcoex_SetManualControl(padapter, _TRUE);
-+	else
-+		hal_btcoex_SetManualControl(padapter, _FALSE);
-+}
-+
-+void rtw_btcoex_set_policy_control(PADAPTER padapter, u8 btc_policy)
-+{
-+	hal_btcoex_set_policy_control(padapter, btc_policy);
-+}
-+
-+u8 rtw_btcoex_1Ant(PADAPTER padapter)
-+{
-+	return hal_btcoex_1Ant(padapter);
-+}
-+
-+u8 rtw_btcoex_IsBtControlLps(PADAPTER padapter)
-+{
-+	return hal_btcoex_IsBtControlLps(padapter);
-+}
-+
-+u8 rtw_btcoex_IsLpsOn(PADAPTER padapter)
-+{
-+	return hal_btcoex_IsLpsOn(padapter);
-+}
-+
-+u8 rtw_btcoex_RpwmVal(PADAPTER padapter)
-+{
-+	return hal_btcoex_RpwmVal(padapter);
-+}
-+
-+u8 rtw_btcoex_LpsVal(PADAPTER padapter)
-+{
-+	return hal_btcoex_LpsVal(padapter);
-+}
-+
-+u32 rtw_btcoex_GetRaMask(PADAPTER padapter)
-+{
-+	return hal_btcoex_GetRaMask(padapter);
-+}
-+
-+u8 rtw_btcoex_query_reduced_wl_pwr_lvl(PADAPTER padapter)
-+{
-+	return hal_btcoex_query_reduced_wl_pwr_lvl(padapter);
-+}
-+
-+void rtw_btcoex_set_reduced_wl_pwr_lvl(PADAPTER padapter, u8 val)
-+{
-+	hal_btcoex_set_reduced_wl_pwr_lvl(padapter, val);
-+}
-+
-+void rtw_btcoex_do_reduce_wl_pwr_lvl(PADAPTER padapter)
-+{
-+	hal_btcoex_do_reduce_wl_pwr_lvl(padapter);
-+}
-+
-+void rtw_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen)
-+{
-+	hal_btcoex_RecordPwrMode(padapter, pCmdBuf, cmdLen);
-+}
-+
-+void rtw_btcoex_DisplayBtCoexInfo(PADAPTER padapter, u8 *pbuf, u32 bufsize)
-+{
-+	hal_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize);
-+}
-+
-+void rtw_btcoex_SetDBG(PADAPTER padapter, u32 *pDbgModule)
-+{
-+	hal_btcoex_SetDBG(padapter, pDbgModule);
-+}
-+
-+u32 rtw_btcoex_GetDBG(PADAPTER padapter, u8 *pStrBuf, u32 bufSize)
-+{
-+	return hal_btcoex_GetDBG(padapter, pStrBuf, bufSize);
-+}
-+
-+u8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER padapter)
-+{
-+	return hal_btcoex_IncreaseScanDeviceNum(padapter);
-+}
-+
-+u8 rtw_btcoex_IsBtLinkExist(PADAPTER padapter)
-+{
-+	return hal_btcoex_IsBtLinkExist(padapter);
-+}
-+
-+void rtw_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer)
-+{
-+	hal_btcoex_SetBtPatchVersion(padapter, btHciVer, btPatchVer);
-+}
-+
-+void rtw_btcoex_SetHciVersion(PADAPTER  padapter, u16 hciVersion)
-+{
-+	hal_btcoex_SetHciVersion(padapter, hciVersion);
-+}
-+
-+void rtw_btcoex_StackUpdateProfileInfo(void)
-+{
-+	hal_btcoex_StackUpdateProfileInfo();
-+}
-+
-+void rtw_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON)
-+{
-+	hal_btcoex_pta_off_on_notify(padapter, bBTON);
-+}
-+
-+#ifdef CONFIG_RF4CE_COEXIST
-+void rtw_btcoex_SetRf4ceLinkState(PADAPTER padapter, u8 state)
-+{
-+	hal_btcoex_set_rf4ce_link_state(state);
-+}
-+
-+u8 rtw_btcoex_GetRf4ceLinkState(PADAPTER padapter)
-+{
-+	return hal_btcoex_get_rf4ce_link_state();
-+}
-+#endif
-+
-+/* ==================================================
-+ * Below Functions are called by BT-Coex
-+ * ================================================== */
-+void rtw_btcoex_rx_ampdu_apply(PADAPTER padapter)
-+{
-+	rtw_rx_ampdu_apply(padapter);
-+}
-+
-+void rtw_btcoex_LPS_Enter(PADAPTER padapter)
-+{
-+	struct pwrctrl_priv *pwrpriv;
-+	u8 lpsVal;
-+
-+
-+	pwrpriv = adapter_to_pwrctl(padapter);
-+
-+	pwrpriv->bpower_saving = _TRUE;
-+	lpsVal = rtw_btcoex_LpsVal(padapter);
-+	rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, lpsVal, "BTCOEX");
-+}
-+
-+u8 rtw_btcoex_LPS_Leave(PADAPTER padapter)
-+{
-+	struct pwrctrl_priv *pwrpriv;
-+
-+
-+	pwrpriv = adapter_to_pwrctl(padapter);
-+
-+	if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
-+		rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "BTCOEX");
-+		pwrpriv->bpower_saving = _FALSE;
-+	}
-+
-+	return _TRUE;
-+}
-+
-+u16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data)
-+{
-+	return hal_btcoex_btreg_read(padapter, type, addr, data);
-+}
-+
-+u16 rtw_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val)
-+{
-+	return hal_btcoex_btreg_write(padapter, type, addr, val);
-+}
-+
-+u16 rtw_btcoex_btset_testmode(PADAPTER padapter, u8 type)
-+{
-+	return hal_btcoex_btset_testode(padapter, type);
-+}
-+
-+u8 rtw_btcoex_get_reduce_wl_txpwr(PADAPTER padapter)
-+{
-+	return rtw_btcoex_query_reduced_wl_pwr_lvl(padapter);
-+}
-+
-+u8 rtw_btcoex_get_bt_coexist(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	return pHalData->EEPROMBluetoothCoexist;
-+}
-+
-+u8 rtw_btcoex_get_chip_type(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	return pHalData->EEPROMBluetoothType;
-+}
-+
-+u8 rtw_btcoex_get_pg_ant_num(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	return pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1;
-+}
-+
-+u8 rtw_btcoex_get_pg_single_ant_path(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	return pHalData->ant_path;
-+}
-+
-+u8 rtw_btcoex_get_pg_rfe_type(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	return pHalData->rfe_type;
-+}
-+
-+u8 rtw_btcoex_is_tfbga_package_type(PADAPTER padapter)
-+{
-+#ifdef CONFIG_RTL8723B
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA80)
-+	    || (pHalData->PackageType == PACKAGE_TFBGA90))
-+		return _TRUE;
-+#endif
-+
-+	return _FALSE;
-+}
-+
-+u8 rtw_btcoex_get_ant_div_cfg(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	
-+	return (pHalData->AntDivCfg == 0) ? _FALSE : _TRUE;
-+}
-+
-+/* ==================================================
-+ * Below Functions are BT-Coex socket related function
-+ * ================================================== */
-+
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+_adapter *pbtcoexadapter; /* = NULL; */ /* do not initialise globals to 0 or NULL */
-+u8 rtw_btcoex_btinfo_cmd(_adapter *adapter, u8 *buf, u16 len)
-+{
-+	struct cmd_obj *ph2c;
-+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
-+	u8 *btinfo;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	btinfo = rtw_zmalloc(len);
-+	if (btinfo == NULL) {
-+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
-+		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = BTINFO_WK_CID;
-+	pdrvextra_cmd_parm->type = 0;
-+	pdrvextra_cmd_parm->size = len;
-+	pdrvextra_cmd_parm->pbuf = btinfo;
-+
-+	_rtw_memcpy(btinfo, buf, len);
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+	return res;
-+}
-+
-+u8 rtw_btcoex_send_event_to_BT(_adapter *padapter, u8 status,  u8 event_code, u8 opcode_low, u8 opcode_high, u8 *dbg_msg)
-+{
-+	u8 localBuf[6] = "";
-+	u8 *pRetPar;
-+	u8	len = 0, tx_event_length = 0;
-+	rtw_HCI_event *pEvent;
-+
-+	pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+	pEvent->EventCode = event_code;
-+	pEvent->Data[0] = 0x1;	/* packet # */
-+	pEvent->Data[1] = opcode_low;
-+	pEvent->Data[2] = opcode_high;
-+	len = len + 3;
-+
-+	/* Return parameters starts from here */
-+	pRetPar = &pEvent->Data[len];
-+	pRetPar[0] = status;		/* status */
-+
-+	len++;
-+	pEvent->Length = len;
-+
-+	/* total tx event length + EventCode length + sizeof(length) */
-+	tx_event_length = pEvent->Length + 2;
-+#if 0
-+	rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, dbg_msg);
-+#endif
-+	status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+
-+	return status;
-+}
-+
-+/*
-+Ref:
-+Realtek Wi-Fi Driver
-+Host Controller Interface for
-+Bluetooth 3.0 + HS V1.4 2013/02/07
-+
-+Window team code & BT team code
-+ */
-+
-+
-+u8 rtw_btcoex_parse_BT_info_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+#define BT_INFO_LENGTH 8
-+
-+	u8 curPollEnable = pcmd[0];
-+	u8 curPollTime = pcmd[1];
-+	u8 btInfoReason = pcmd[2];
-+	u8 btInfoLen = pcmd[3];
-+	u8 btinfo[BT_INFO_LENGTH];
-+
-+	u8 localBuf[6] = "";
-+	u8 *pRetPar;
-+	u8	len = 0, tx_event_length = 0;
-+	RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+	rtw_HCI_event *pEvent;
-+
-+	/* RTW_INFO("%s\n",__func__);
-+	RTW_INFO("current Poll Enable: %d, currrent Poll Time: %d\n",curPollEnable,curPollTime);
-+	RTW_INFO("BT Info reason: %d, BT Info length: %d\n",btInfoReason,btInfoLen);
-+	RTW_INFO("%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n"
-+		,pcmd[4],pcmd[5],pcmd[6],pcmd[7],pcmd[8],pcmd[9],pcmd[10],pcmd[11]);*/
-+
-+	_rtw_memset(btinfo, 0, BT_INFO_LENGTH);
-+
-+#if 1
-+	if (BT_INFO_LENGTH != btInfoLen) {
-+		status = HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE;
-+		RTW_INFO("Error BT Info Length: %d\n", btInfoLen);
-+		/* return _FAIL; */
-+	} else
-+#endif
-+	{
-+		if (0x1 == btInfoReason || 0x2 == btInfoReason) {
-+			_rtw_memcpy(btinfo, &pcmd[4], btInfoLen);
-+			btinfo[0] = btInfoReason;
-+			rtw_btcoex_btinfo_cmd(padapter, btinfo, btInfoLen);
-+		} else
-+			RTW_INFO("Other BT info reason\n");
-+	}
-+
-+	/* send complete event to BT */
-+	{
-+
-+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+		pEvent->Data[0] = 0x1;	/* packet # */
-+		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_INFO_NOTIFY, OGF_EXTENSION);
-+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_INFO_NOTIFY, OGF_EXTENSION);
-+		len = len + 3;
-+
-+		/* Return parameters starts from here */
-+		pRetPar = &pEvent->Data[len];
-+		pRetPar[0] = status;		/* status */
-+
-+		len++;
-+		pEvent->Length = len;
-+
-+		/* total tx event length + EventCode length + sizeof(length) */
-+		tx_event_length = pEvent->Length + 2;
-+#if 0
-+		rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT_info_event");
-+#endif
-+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+
-+		return status;
-+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+	}
-+}
-+
-+u8 rtw_btcoex_parse_BT_patch_ver_info_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+	RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+	u16		btPatchVer = 0x0, btHciVer = 0x0;
-+	/* u16		*pU2tmp; */
-+
-+	u8 localBuf[6] = "";
-+	u8 *pRetPar;
-+	u8	len = 0, tx_event_length = 0;
-+	rtw_HCI_event *pEvent;
-+
-+	btHciVer = pcmd[0] | pcmd[1] << 8;
-+	btPatchVer = pcmd[2] | pcmd[3] << 8;
-+
-+
-+	RTW_INFO("%s, cmd:%02x %02x %02x %02x\n", __func__, pcmd[0] , pcmd[1] , pcmd[2] , pcmd[3]);
-+	RTW_INFO("%s, HCI Ver:%d, Patch Ver:%d\n", __func__, btHciVer, btPatchVer);
-+
-+	rtw_btcoex_SetBtPatchVersion(padapter, btHciVer, btPatchVer);
-+
-+
-+	/* send complete event to BT */
-+	{
-+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+		pEvent->Data[0] = 0x1;	/* packet # */
-+		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_PATCH_VERSION_NOTIFY, OGF_EXTENSION);
-+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_PATCH_VERSION_NOTIFY, OGF_EXTENSION);
-+		len = len + 3;
-+
-+		/* Return parameters starts from here */
-+		pRetPar = &pEvent->Data[len];
-+		pRetPar[0] = status;		/* status */
-+
-+		len++;
-+		pEvent->Length = len;
-+
-+		/* total tx event length + EventCode length + sizeof(length) */
-+		tx_event_length = pEvent->Length + 2;
-+#if 0
-+		rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT_patch_event");
-+#endif
-+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+		return status;
-+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+	}
-+}
-+
-+u8 rtw_btcoex_parse_HCI_Ver_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+	RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+	u16 hciver = pcmd[0] | pcmd[1] << 8;
-+
-+	u8 localBuf[6] = "";
-+	u8 *pRetPar;
-+	u8	len = 0, tx_event_length = 0;
-+	rtw_HCI_event *pEvent;
-+
-+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+	PBT_MGNT	pBtMgnt = &pcoex_info->BtMgnt;
-+	pBtMgnt->ExtConfig.HCIExtensionVer = hciver;
-+	RTW_INFO("%s, HCI Version: %d\n", __func__, pBtMgnt->ExtConfig.HCIExtensionVer);
-+	if (pBtMgnt->ExtConfig.HCIExtensionVer  < 4) {
-+		status = HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE;
-+		RTW_INFO("%s, Version = %d, HCI Version < 4\n", __func__, pBtMgnt->ExtConfig.HCIExtensionVer);
-+	} else
-+		rtw_btcoex_SetHciVersion(padapter, hciver);
-+	/* send complete event to BT */
-+	{
-+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+		pEvent->Data[0] = 0x1;	/* packet # */
-+		pEvent->Data[1] = HCIOPCODELOW(HCI_EXTENSION_VERSION_NOTIFY, OGF_EXTENSION);
-+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_EXTENSION_VERSION_NOTIFY, OGF_EXTENSION);
-+		len = len + 3;
-+
-+		/* Return parameters starts from here */
-+		pRetPar = &pEvent->Data[len];
-+		pRetPar[0] = status;		/* status */
-+
-+		len++;
-+		pEvent->Length = len;
-+
-+		/* total tx event length + EventCode length + sizeof(length) */
-+		tx_event_length = pEvent->Length + 2;
-+
-+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+		return status;
-+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+	}
-+
-+}
-+
-+u8 rtw_btcoex_parse_WIFI_scan_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+	RTW_HCI_STATUS status = HCI_STATUS_SUCCESS;
-+
-+	u8 localBuf[6] = "";
-+	u8 *pRetPar;
-+	u8	len = 0, tx_event_length = 0;
-+	rtw_HCI_event *pEvent;
-+
-+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+	PBT_MGNT	pBtMgnt = &pcoex_info->BtMgnt;
-+	pBtMgnt->ExtConfig.bEnableWifiScanNotify = pcmd[0];
-+	RTW_INFO("%s, bEnableWifiScanNotify: %d\n", __func__, pBtMgnt->ExtConfig.bEnableWifiScanNotify);
-+
-+	/* send complete event to BT */
-+	{
-+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+		pEvent->Data[0] = 0x1;	/* packet # */
-+		pEvent->Data[1] = HCIOPCODELOW(HCI_ENABLE_WIFI_SCAN_NOTIFY, OGF_EXTENSION);
-+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_ENABLE_WIFI_SCAN_NOTIFY, OGF_EXTENSION);
-+		len = len + 3;
-+
-+		/* Return parameters starts from here */
-+		pRetPar = &pEvent->Data[len];
-+		pRetPar[0] = status;		/* status */
-+
-+		len++;
-+		pEvent->Length = len;
-+
-+		/* total tx event length + EventCode length + sizeof(length) */
-+		tx_event_length = pEvent->Length + 2;
-+
-+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+		return status;
-+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+	}
-+}
-+
-+u8 rtw_btcoex_parse_HCI_link_status_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
-+	struct bt_coex_info	*pcoex_info = &padapter->coex_info;
-+	PBT_MGNT	pBtMgnt = &pcoex_info->BtMgnt;
-+	/* PBT_DBG		pBtDbg=&padapter->MgntInfo.BtInfo.BtDbg; */
-+	u8		i, numOfHandle = 0, numOfAcl = 0;
-+	u16		conHandle;
-+	u8		btProfile, btCoreSpec, linkRole;
-+	u8		*pTriple;
-+
-+	u8 localBuf[6] = "";
-+	u8 *pRetPar;
-+	u8	len = 0, tx_event_length = 0;
-+	rtw_HCI_event *pEvent;
-+
-+	/* pBtDbg->dbgHciInfo.hciCmdCntLinkStatusNotify++; */
-+	/* RT_DISP_DATA(FIOCTL, IOCTL_BT_HCICMD_EXT, "LinkStatusNotify, Hex Data :\n",  */
-+	/*		&pHciCmd->Data[0], pHciCmd->Length); */
-+
-+	RTW_INFO("BTLinkStatusNotify\n");
-+
-+	/* Current only RTL8723 support this command. */
-+	/* pBtMgnt->bSupportProfile = TRUE; */
-+	pBtMgnt->bSupportProfile = _FALSE;
-+
-+	pBtMgnt->ExtConfig.NumberOfACL = 0;
-+	pBtMgnt->ExtConfig.NumberOfSCO = 0;
-+
-+	numOfHandle = pcmd[0];
-+	/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, ("numOfHandle = 0x%x\n", numOfHandle)); */
-+	/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, ("HCIExtensionVer = %d\n", pBtMgnt->ExtConfig.HCIExtensionVer)); */
-+	RTW_INFO("numOfHandle = 0x%x\n", numOfHandle);
-+	RTW_INFO("HCIExtensionVer = %d\n", pBtMgnt->ExtConfig.HCIExtensionVer);
-+
-+	pTriple = &pcmd[1];
-+	for (i = 0; i < numOfHandle; i++) {
-+		if (pBtMgnt->ExtConfig.HCIExtensionVer < 1) {
-+			conHandle = *((u8 *)&pTriple[0]);
-+			btProfile = pTriple[2];
-+			btCoreSpec = pTriple[3];
-+			if (BT_PROFILE_SCO == btProfile)
-+				pBtMgnt->ExtConfig.NumberOfSCO++;
-+			else {
-+				pBtMgnt->ExtConfig.NumberOfACL++;
-+				pBtMgnt->ExtConfig.aclLink[i].ConnectHandle = conHandle;
-+				pBtMgnt->ExtConfig.aclLink[i].BTProfile = btProfile;
-+				pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec = btCoreSpec;
-+			}
-+			/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, */
-+			/*	("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d\n", */
-+			/*		conHandle, btProfile, btCoreSpec)); */
-+			RTW_INFO("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d\n", conHandle, btProfile, btCoreSpec);
-+			pTriple += 4;
-+		} else if (pBtMgnt->ExtConfig.HCIExtensionVer >= 1) {
-+			conHandle = *((u16 *)&pTriple[0]);
-+			btProfile = pTriple[2];
-+			btCoreSpec = pTriple[3];
-+			linkRole = pTriple[4];
-+			if (BT_PROFILE_SCO == btProfile)
-+				pBtMgnt->ExtConfig.NumberOfSCO++;
-+			else {
-+				pBtMgnt->ExtConfig.NumberOfACL++;
-+				pBtMgnt->ExtConfig.aclLink[i].ConnectHandle = conHandle;
-+				pBtMgnt->ExtConfig.aclLink[i].BTProfile = btProfile;
-+				pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec = btCoreSpec;
-+				pBtMgnt->ExtConfig.aclLink[i].linkRole = linkRole;
-+			}
-+			/* RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, */
-+			RTW_INFO("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d, LinkRole=%d\n",
-+				 conHandle, btProfile, btCoreSpec, linkRole);
-+			pTriple += 5;
-+		}
-+	}
-+	rtw_btcoex_StackUpdateProfileInfo();
-+
-+	/* send complete event to BT */
-+	{
-+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+		pEvent->Data[0] = 0x1;	/* packet # */
-+		pEvent->Data[1] = HCIOPCODELOW(HCI_LINK_STATUS_NOTIFY, OGF_EXTENSION);
-+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_LINK_STATUS_NOTIFY, OGF_EXTENSION);
-+		len = len + 3;
-+
-+		/* Return parameters starts from here */
-+		pRetPar = &pEvent->Data[len];
-+		pRetPar[0] = status;		/* status */
-+
-+		len++;
-+		pEvent->Length = len;
-+
-+		/* total tx event length + EventCode length + sizeof(length) */
-+		tx_event_length = pEvent->Length + 2;
-+
-+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+		return status;
-+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+	}
-+
-+
-+}
-+
-+u8 rtw_btcoex_parse_HCI_BT_coex_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+	u8 localBuf[6] = "";
-+	u8 *pRetPar;
-+	u8	len = 0, tx_event_length = 0;
-+	rtw_HCI_event *pEvent;
-+	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
-+
-+	{
-+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+		pEvent->Data[0] = 0x1;	/* packet # */
-+		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_COEX_NOTIFY, OGF_EXTENSION);
-+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_COEX_NOTIFY, OGF_EXTENSION);
-+		len = len + 3;
-+
-+		/* Return parameters starts from here */
-+		pRetPar = &pEvent->Data[len];
-+		pRetPar[0] = status;		/* status */
-+
-+		len++;
-+		pEvent->Length = len;
-+
-+		/* total tx event length + EventCode length + sizeof(length) */
-+		tx_event_length = pEvent->Length + 2;
-+
-+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+		return status;
-+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+	}
-+}
-+
-+u8 rtw_btcoex_parse_HCI_BT_operation_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+	u8 localBuf[6] = "";
-+	u8 *pRetPar;
-+	u8	len = 0, tx_event_length = 0;
-+	rtw_HCI_event *pEvent;
-+	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
-+
-+	RTW_INFO("%s, OP code: %d\n", __func__, pcmd[0]);
-+
-+	switch (pcmd[0]) {
-+	case HCI_BT_OP_NONE:
-+		RTW_INFO("[bt operation] : Operation None!!\n");
-+		break;
-+	case HCI_BT_OP_INQUIRY_START:
-+		RTW_INFO("[bt operation] : Inquiry start!!\n");
-+		break;
-+	case HCI_BT_OP_INQUIRY_FINISH:
-+		RTW_INFO("[bt operation] : Inquiry finished!!\n");
-+		break;
-+	case HCI_BT_OP_PAGING_START:
-+		RTW_INFO("[bt operation] : Paging is started!!\n");
-+		break;
-+	case HCI_BT_OP_PAGING_SUCCESS:
-+		RTW_INFO("[bt operation] : Paging complete successfully!!\n");
-+		break;
-+	case HCI_BT_OP_PAGING_UNSUCCESS:
-+		RTW_INFO("[bt operation] : Paging complete unsuccessfully!!\n");
-+		break;
-+	case HCI_BT_OP_PAIRING_START:
-+		RTW_INFO("[bt operation] : Pairing start!!\n");
-+		break;
-+	case HCI_BT_OP_PAIRING_FINISH:
-+		RTW_INFO("[bt operation] : Pairing finished!!\n");
-+		break;
-+	case HCI_BT_OP_BT_DEV_ENABLE:
-+		RTW_INFO("[bt operation] : BT Device is enabled!!\n");
-+		break;
-+	case HCI_BT_OP_BT_DEV_DISABLE:
-+		RTW_INFO("[bt operation] : BT Device is disabled!!\n");
-+		break;
-+	default:
-+		RTW_INFO("[bt operation] : Unknown, error!!\n");
-+		break;
-+	}
-+
-+	/* send complete event to BT */
-+	{
-+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+		pEvent->Data[0] = 0x1;	/* packet # */
-+		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_OPERATION_NOTIFY, OGF_EXTENSION);
-+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_OPERATION_NOTIFY, OGF_EXTENSION);
-+		len = len + 3;
-+
-+		/* Return parameters starts from here */
-+		pRetPar = &pEvent->Data[len];
-+		pRetPar[0] = status;		/* status */
-+
-+		len++;
-+		pEvent->Length = len;
-+
-+		/* total tx event length + EventCode length + sizeof(length) */
-+		tx_event_length = pEvent->Length + 2;
-+
-+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+		return status;
-+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+	}
-+}
-+
-+u8 rtw_btcoex_parse_BT_AFH_MAP_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+	u8 localBuf[6] = "";
-+	u8 *pRetPar;
-+	u8	len = 0, tx_event_length = 0;
-+	rtw_HCI_event *pEvent;
-+	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
-+
-+	{
-+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+		pEvent->Data[0] = 0x1;	/* packet # */
-+		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_AFH_MAP_NOTIFY, OGF_EXTENSION);
-+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_AFH_MAP_NOTIFY, OGF_EXTENSION);
-+		len = len + 3;
-+
-+		/* Return parameters starts from here */
-+		pRetPar = &pEvent->Data[len];
-+		pRetPar[0] = status;		/* status */
-+
-+		len++;
-+		pEvent->Length = len;
-+
-+		/* total tx event length + EventCode length + sizeof(length) */
-+		tx_event_length = pEvent->Length + 2;
-+
-+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+		return status;
-+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+	}
-+}
-+
-+u8 rtw_btcoex_parse_BT_register_val_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+
-+	u8 localBuf[6] = "";
-+	u8 *pRetPar;
-+	u8	len = 0, tx_event_length = 0;
-+	rtw_HCI_event *pEvent;
-+	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
-+
-+	{
-+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+		pEvent->Data[0] = 0x1;	/* packet # */
-+		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_REGISTER_VALUE_NOTIFY, OGF_EXTENSION);
-+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_REGISTER_VALUE_NOTIFY, OGF_EXTENSION);
-+		len = len + 3;
-+
-+		/* Return parameters starts from here */
-+		pRetPar = &pEvent->Data[len];
-+		pRetPar[0] = status;		/* status */
-+
-+		len++;
-+		pEvent->Length = len;
-+
-+		/* total tx event length + EventCode length + sizeof(length) */
-+		tx_event_length = pEvent->Length + 2;
-+
-+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+		return status;
-+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+	}
-+}
-+
-+u8 rtw_btcoex_parse_HCI_BT_abnormal_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+	u8 localBuf[6] = "";
-+	u8 *pRetPar;
-+	u8	len = 0, tx_event_length = 0;
-+	rtw_HCI_event *pEvent;
-+	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
-+
-+	{
-+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+		pEvent->Data[0] = 0x1;	/* packet # */
-+		pEvent->Data[1] = HCIOPCODELOW(HCI_BT_ABNORMAL_NOTIFY, OGF_EXTENSION);
-+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_ABNORMAL_NOTIFY, OGF_EXTENSION);
-+		len = len + 3;
-+
-+		/* Return parameters starts from here */
-+		pRetPar = &pEvent->Data[len];
-+		pRetPar[0] = status;		/* status */
-+
-+		len++;
-+		pEvent->Length = len;
-+
-+		/* total tx event length + EventCode length + sizeof(length) */
-+		tx_event_length = pEvent->Length + 2;
-+
-+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+		return status;
-+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+	}
-+}
-+
-+u8 rtw_btcoex_parse_HCI_query_RF_status_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen)
-+{
-+	u8 localBuf[6] = "";
-+	u8 *pRetPar;
-+	u8	len = 0, tx_event_length = 0;
-+	rtw_HCI_event *pEvent;
-+	RTW_HCI_STATUS	status = HCI_STATUS_SUCCESS;
-+
-+	{
-+		pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+
-+		pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE;
-+		pEvent->Data[0] = 0x1;	/* packet # */
-+		pEvent->Data[1] = HCIOPCODELOW(HCI_QUERY_RF_STATUS, OGF_EXTENSION);
-+		pEvent->Data[2] = HCIOPCODEHIGHT(HCI_QUERY_RF_STATUS, OGF_EXTENSION);
-+		len = len + 3;
-+
-+		/* Return parameters starts from here */
-+		pRetPar = &pEvent->Data[len];
-+		pRetPar[0] = status;		/* status */
-+
-+		len++;
-+		pEvent->Length = len;
-+
-+		/* total tx event length + EventCode length + sizeof(length) */
-+		tx_event_length = pEvent->Length + 2;
-+
-+		status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+		return status;
-+		/* bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); */
-+	}
-+}
-+
-+/*****************************************
-+* HCI cmd format :
-+*| 15 - 0						|
-+*| OPcode (OCF|OGF<<10)		|
-+*| 15 - 8		|7 - 0			|
-+*|Cmd para	|Cmd para Length	|
-+*|Cmd para......				|
-+******************************************/
-+
-+/* bit 0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
-+ *	 |	OCF			             |	   OGF       | */
-+void rtw_btcoex_parse_hci_extend_cmd(_adapter *padapter, u8 *pcmd, u16 len, const u16 hci_OCF)
-+{
-+
-+	RTW_INFO("%s: OCF: %x\n", __func__, hci_OCF);
-+	switch (hci_OCF) {
-+	case HCI_EXTENSION_VERSION_NOTIFY:
-+		RTW_INFO("HCI_EXTENSION_VERSION_NOTIFY\n");
-+		rtw_btcoex_parse_HCI_Ver_notify_cmd(padapter, pcmd, len);
-+		break;
-+	case HCI_LINK_STATUS_NOTIFY:
-+		RTW_INFO("HCI_LINK_STATUS_NOTIFY\n");
-+		rtw_btcoex_parse_HCI_link_status_notify_cmd(padapter, pcmd, len);
-+		break;
-+	case HCI_BT_OPERATION_NOTIFY:
-+		/* only for 8723a 2ant */
-+		RTW_INFO("HCI_BT_OPERATION_NOTIFY\n");
-+		rtw_btcoex_parse_HCI_BT_operation_notify_cmd(padapter, pcmd, len);
-+		/*  */
-+		break;
-+	case HCI_ENABLE_WIFI_SCAN_NOTIFY:
-+		RTW_INFO("HCI_ENABLE_WIFI_SCAN_NOTIFY\n");
-+		rtw_btcoex_parse_WIFI_scan_notify_cmd(padapter, pcmd, len);
-+		break;
-+	case HCI_QUERY_RF_STATUS:
-+		/* only for 8723b 2ant */
-+		RTW_INFO("HCI_QUERY_RF_STATUS\n");
-+		rtw_btcoex_parse_HCI_query_RF_status_cmd(padapter, pcmd, len);
-+		break;
-+	case HCI_BT_ABNORMAL_NOTIFY:
-+		RTW_INFO("HCI_BT_ABNORMAL_NOTIFY\n");
-+		rtw_btcoex_parse_HCI_BT_abnormal_notify_cmd(padapter, pcmd, len);
-+		break;
-+	case HCI_BT_INFO_NOTIFY:
-+		RTW_INFO("HCI_BT_INFO_NOTIFY\n");
-+		rtw_btcoex_parse_BT_info_notify_cmd(padapter, pcmd, len);
-+		break;
-+	case HCI_BT_COEX_NOTIFY:
-+		RTW_INFO("HCI_BT_COEX_NOTIFY\n");
-+		rtw_btcoex_parse_HCI_BT_coex_notify_cmd(padapter, pcmd, len);
-+		break;
-+	case HCI_BT_PATCH_VERSION_NOTIFY:
-+		RTW_INFO("HCI_BT_PATCH_VERSION_NOTIFY\n");
-+		rtw_btcoex_parse_BT_patch_ver_info_cmd(padapter, pcmd, len);
-+		break;
-+	case HCI_BT_AFH_MAP_NOTIFY:
-+		RTW_INFO("HCI_BT_AFH_MAP_NOTIFY\n");
-+		rtw_btcoex_parse_BT_AFH_MAP_notify_cmd(padapter, pcmd, len);
-+		break;
-+	case HCI_BT_REGISTER_VALUE_NOTIFY:
-+		RTW_INFO("HCI_BT_REGISTER_VALUE_NOTIFY\n");
-+		rtw_btcoex_parse_BT_register_val_notify_cmd(padapter, pcmd, len);
-+		break;
-+	default:
-+		RTW_INFO("ERROR!!! Unknown OCF: %x\n", hci_OCF);
-+		break;
-+
-+	}
-+}
-+
-+void rtw_btcoex_parse_hci_cmd(_adapter *padapter, u8 *pcmd, u16 len)
-+{
-+	u16 opcode = pcmd[0] | pcmd[1] << 8;
-+	u16 hci_OGF = HCI_OGF(opcode);
-+	u16 hci_OCF = HCI_OCF(opcode);
-+	u8 cmdlen = len - 3;
-+	u8 pare_len = pcmd[2];
-+
-+	RTW_INFO("%s OGF: %x,OCF: %x\n", __func__, hci_OGF, hci_OCF);
-+	switch (hci_OGF) {
-+	case OGF_EXTENSION:
-+		RTW_INFO("HCI_EXTENSION_CMD_OGF\n");
-+		rtw_btcoex_parse_hci_extend_cmd(padapter, &pcmd[3], cmdlen, hci_OCF);
-+		break;
-+	default:
-+		RTW_INFO("Other OGF: %x\n", hci_OGF);
-+		break;
-+	}
-+}
-+
-+u16 rtw_btcoex_parse_recv_data(u8 *msg, u8 msg_size)
-+{
-+	u8 cmp_msg1[32] = attend_ack;
-+	u8 cmp_msg2[32] = leave_ack;
-+	u8 cmp_msg3[32] = bt_leave;
-+	u8 cmp_msg4[32] = invite_req;
-+	u8 cmp_msg5[32] = attend_req;
-+	u8 cmp_msg6[32] = invite_rsp;
-+	u8 res = OTHER;
-+
-+	if (_rtw_memcmp(cmp_msg1, msg, msg_size) == _TRUE) {
-+		/*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
-+		res = RX_ATTEND_ACK;
-+	} else if (_rtw_memcmp(cmp_msg2, msg, msg_size) == _TRUE) {
-+		/*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
-+		res = RX_LEAVE_ACK;
-+	} else if (_rtw_memcmp(cmp_msg3, msg, msg_size) == _TRUE) {
-+		/*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
-+		res = RX_BT_LEAVE;
-+	} else if (_rtw_memcmp(cmp_msg4, msg, msg_size) == _TRUE) {
-+		/*RTW_INFO("%s, msg:%s\n",__func__,msg);*/
-+		res = RX_INVITE_REQ;
-+	} else if (_rtw_memcmp(cmp_msg5, msg, msg_size) == _TRUE)
-+		res = RX_ATTEND_REQ;
-+	else if (_rtw_memcmp(cmp_msg6, msg, msg_size) == _TRUE)
-+		res = RX_INVITE_RSP;
-+	else {
-+		/*RTW_INFO("%s, %s\n", __func__, msg);*/
-+		res = OTHER;
-+	}
-+
-+	/*RTW_INFO("%s, res:%d\n", __func__, res);*/
-+
-+	return res;
-+}
-+
-+void rtw_btcoex_recvmsgbysocket(void *data)
-+{
-+	u8 recv_data[255];
-+	u8 tx_msg[255] = leave_ack;
-+	u32 len = 0;
-+	u16 recv_length = 0;
-+	u16 parse_res = 0;
-+#if 0
-+	u8 para_len = 0, polling_enable = 0, poling_interval = 0, reason = 0, btinfo_len = 0;
-+	u8 btinfo[BT_INFO_LEN] = {0};
-+#endif
-+
-+	struct bt_coex_info *pcoex_info = NULL;
-+	struct sock *sk = NULL;
-+	struct sk_buff *skb = NULL;
-+
-+	/*RTW_INFO("%s\n",__func__);*/
-+
-+	if (pbtcoexadapter == NULL) {
-+		RTW_INFO("%s: btcoexadapter NULL!\n", __func__);
-+		return;
-+	}
-+
-+	pcoex_info = &pbtcoexadapter->coex_info;
-+	sk = pcoex_info->sk_store;
-+
-+	if (sk == NULL) {
-+		RTW_INFO("%s: critical error when receive socket data!\n", __func__);
-+		return;
-+	}
-+
-+	len = skb_queue_len(&sk->sk_receive_queue);
-+	while (len > 0) {
-+		skb = skb_dequeue(&sk->sk_receive_queue);
-+
-+		/*important: cut the udp header from skb->data! header length is 8 byte*/
-+		recv_length = skb->len - 8;
-+		_rtw_memset(recv_data, 0, sizeof(recv_data));
-+		_rtw_memcpy(recv_data, skb->data + 8, recv_length);
-+
-+		parse_res = rtw_btcoex_parse_recv_data(recv_data, recv_length);
-+#if 0
-+		if (RX_ATTEND_ACK == parse_res) {
-+			/* attend ack */
-+			pcoex_info->BT_attend = _TRUE;
-+			RTW_INFO("RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+		} else if (RX_ATTEND_REQ == parse_res) {
-+			/* attend req from BT */
-+			pcoex_info->BT_attend = _TRUE;
-+			RTW_INFO("RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE);
-+		} else if (RX_INVITE_REQ == parse_res) {
-+			/* invite req from BT */
-+			pcoex_info->BT_attend = _TRUE;
-+			RTW_INFO("RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE);
-+		} else if (RX_INVITE_RSP == parse_res) {
-+			/* invite rsp */
-+			pcoex_info->BT_attend = _TRUE;
-+			RTW_INFO("RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+		} else if (RX_LEAVE_ACK == parse_res) {
-+			/* mean BT know wifi  will leave */
-+			pcoex_info->BT_attend = _FALSE;
-+			RTW_INFO("RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+		} else if (RX_BT_LEAVE == parse_res) {
-+			/* BT leave */
-+			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /*  no ack */
-+			pcoex_info->BT_attend = _FALSE;
-+			RTW_INFO("RX_BT_LEAVE!sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+		} else {
-+			/* todo: check if recv data are really hci cmds */
-+			if (_TRUE == pcoex_info->BT_attend)
-+				rtw_btcoex_parse_hci_cmd(pbtcoexadapter, recv_data, recv_length);
-+		}
-+#endif
-+		switch (parse_res) {
-+		case RX_ATTEND_ACK:
-+			/* attend ack */
-+			pcoex_info->BT_attend = _TRUE;
-+			RTW_INFO("RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
-+			break;
-+
-+		case RX_ATTEND_REQ:
-+			pcoex_info->BT_attend = _TRUE;
-+			RTW_INFO("RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE);
-+			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
-+			break;
-+
-+		case RX_INVITE_REQ:
-+			/* invite req from BT */
-+			pcoex_info->BT_attend = _TRUE;
-+			RTW_INFO("RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE);
-+			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
-+			break;
-+
-+		case RX_INVITE_RSP:
-+			/*invite rsp*/
-+			pcoex_info->BT_attend = _TRUE;
-+			RTW_INFO("RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
-+			break;
-+
-+		case RX_LEAVE_ACK:
-+			/* mean BT know wifi  will leave */
-+			pcoex_info->BT_attend = _FALSE;
-+			RTW_INFO("RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
-+			break;
-+
-+		case RX_BT_LEAVE:
-+			/* BT leave */
-+			rtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /* no ack */
-+			pcoex_info->BT_attend = _FALSE;
-+			RTW_INFO("RX_BT_LEAVE!sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+			rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
-+			break;
-+
-+		default:
-+			if (_TRUE == pcoex_info->BT_attend)
-+				rtw_btcoex_parse_hci_cmd(pbtcoexadapter, recv_data, recv_length);
-+			else
-+				RTW_INFO("ERROR!! BT is UP\n");
-+			break;
-+
-+		}
-+
-+		len--;
-+		kfree_skb(skb);
-+	}
-+}
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))
-+	void rtw_btcoex_recvmsg_init(struct sock *sk_in, s32 bytes)
-+#else
-+	void rtw_btcoex_recvmsg_init(struct sock *sk_in)
-+#endif
-+{
-+	struct bt_coex_info *pcoex_info = NULL;
-+
-+	if (pbtcoexadapter == NULL) {
-+		RTW_INFO("%s: btcoexadapter NULL\n", __func__);
-+		return;
-+	}
-+	pcoex_info = &pbtcoexadapter->coex_info;
-+	pcoex_info->sk_store = sk_in;
-+	if (pcoex_info->btcoex_wq != NULL)
-+		queue_delayed_work(pcoex_info->btcoex_wq, &pcoex_info->recvmsg_work, 0);
-+	else
-+		RTW_INFO("%s: BTCOEX workqueue NULL\n", __func__);
-+}
-+
-+u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool force)
-+{
-+	u8 error;
-+	struct msghdr	udpmsg;
-+	mm_segment_t	oldfs;
-+	struct iovec	iov;
-+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+
-+	/* RTW_INFO("%s: msg:%s, force:%s\n", __func__, msg, force == _TRUE?"TRUE":"FALSE"); */
-+	if (_FALSE == force) {
-+		if (_FALSE == pcoex_info->BT_attend) {
-+			RTW_INFO("TX Blocked: WiFi-BT disconnected\n");
-+			return _FAIL;
-+		}
-+	}
-+
-+	iov.iov_base	 = (void *)msg;
-+	iov.iov_len	 = msg_size;
-+	udpmsg.msg_name	 = &pcoex_info->bt_sockaddr;
-+	udpmsg.msg_namelen	= sizeof(struct sockaddr_in);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
-+	/* referece:sock_xmit in kernel code
-+	 * WRITE for sock_sendmsg, READ for sock_recvmsg
-+	 * third parameter for msg_iovlen
-+	 * last parameter for iov_len
-+	 */
-+	iov_iter_init(&udpmsg.msg_iter, WRITE, &iov, 1, msg_size);
-+#else
-+	udpmsg.msg_iov	 = &iov;
-+	udpmsg.msg_iovlen	= 1;
-+#endif
-+	udpmsg.msg_control	= NULL;
-+	udpmsg.msg_controllen = 0;
-+	udpmsg.msg_flags	= MSG_DONTWAIT | MSG_NOSIGNAL;
-+	oldfs = get_fs();
-+	set_fs(KERNEL_DS);
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
-+	error = sock_sendmsg(pcoex_info->udpsock, &udpmsg);
-+#else
-+	error = sock_sendmsg(pcoex_info->udpsock, &udpmsg, msg_size);
-+#endif
-+	set_fs(oldfs);
-+	if (error < 0) {
-+		RTW_INFO("Error when sendimg msg, error:%d\n", error);
-+		return _FAIL;
-+	} else
-+		return _SUCCESS;
-+}
-+
-+u8 rtw_btcoex_create_kernel_socket(_adapter *padapter)
-+{
-+	s8 kernel_socket_err;
-+	u8 tx_msg[255] = attend_req;
-+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+	s32 sock_reuse = 1;
-+	u8 status = _FAIL;
-+
-+	RTW_INFO("%s CONNECT_PORT %d\n", __func__, CONNECT_PORT);
-+
-+	if (NULL == pcoex_info) {
-+		RTW_INFO("coex_info: NULL\n");
-+		status =  _FAIL;
-+	}
-+
-+	kernel_socket_err = sock_create(PF_INET, SOCK_DGRAM, 0, &pcoex_info->udpsock);
-+
-+	if (kernel_socket_err < 0) {
-+		RTW_INFO("Error during creation of socket error:%d\n", kernel_socket_err);
-+		status = _FAIL;
-+	} else {
-+		_rtw_memset(&(pcoex_info->wifi_sockaddr), 0, sizeof(pcoex_info->wifi_sockaddr));
-+		pcoex_info->wifi_sockaddr.sin_family = AF_INET;
-+		pcoex_info->wifi_sockaddr.sin_port = htons(CONNECT_PORT);
-+		pcoex_info->wifi_sockaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
-+
-+		_rtw_memset(&(pcoex_info->bt_sockaddr), 0, sizeof(pcoex_info->bt_sockaddr));
-+		pcoex_info->bt_sockaddr.sin_family = AF_INET;
-+		pcoex_info->bt_sockaddr.sin_port = htons(CONNECT_PORT_BT);
-+		pcoex_info->bt_sockaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
-+
-+		pcoex_info->sk_store = NULL;
-+		kernel_socket_err = pcoex_info->udpsock->ops->bind(pcoex_info->udpsock, (struct sockaddr *)&pcoex_info->wifi_sockaddr,
-+				    sizeof(pcoex_info->wifi_sockaddr));
-+		if (kernel_socket_err == 0) {
-+			RTW_INFO("binding socket success\n");
-+			pcoex_info->udpsock->sk->sk_data_ready = rtw_btcoex_recvmsg_init;
-+			pcoex_info->sock_open |=  KERNEL_SOCKET_OK;
-+			pcoex_info->BT_attend = _FALSE;
-+			RTW_INFO("WIFI sending attend_req\n");
-+			rtw_btcoex_sendmsgbysocket(padapter, attend_req, sizeof(attend_req), _TRUE);
-+			status = _SUCCESS;
-+		} else {
-+			pcoex_info->BT_attend = _FALSE;
-+			sock_release(pcoex_info->udpsock); /* bind fail release socket */
-+			RTW_INFO("Error binding socket: %d\n", kernel_socket_err);
-+			status = _FAIL;
-+		}
-+
-+	}
-+
-+	return status;
-+}
-+
-+void rtw_btcoex_close_kernel_socket(_adapter *padapter)
-+{
-+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+	if (pcoex_info->sock_open & KERNEL_SOCKET_OK) {
-+		RTW_INFO("release kernel socket\n");
-+		sock_release(pcoex_info->udpsock);
-+		pcoex_info->sock_open &= ~(KERNEL_SOCKET_OK);
-+		if (_TRUE == pcoex_info->BT_attend)
-+			pcoex_info->BT_attend = _FALSE;
-+
-+		RTW_INFO("sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
-+	}
-+}
-+
-+void rtw_btcoex_init_socket(_adapter *padapter)
-+{
-+
-+	u8 is_invite = _FALSE;
-+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+	RTW_INFO("%s\n", __func__);
-+	if (_FALSE == pcoex_info->is_exist) {
-+		_rtw_memset(pcoex_info, 0, sizeof(struct bt_coex_info));
-+		pcoex_info->btcoex_wq = create_workqueue("BTCOEX");
-+		INIT_DELAYED_WORK(&pcoex_info->recvmsg_work,
-+				  (void *)rtw_btcoex_recvmsgbysocket);
-+		pbtcoexadapter = padapter;
-+		/* We expect BT is off if BT don't send ack to wifi */
-+		RTW_INFO("We expect BT is off if BT send ack to wifi\n");
-+		rtw_btcoex_pta_off_on_notify(pbtcoexadapter, _FALSE);
-+		if (rtw_btcoex_create_kernel_socket(padapter) == _SUCCESS)
-+			pcoex_info->is_exist = _TRUE;
-+		else {
-+			pcoex_info->is_exist = _FALSE;
-+			pbtcoexadapter = NULL;
-+		}
-+
-+		RTW_INFO("%s: pbtcoexadapter:%p, coex_info->is_exist: %s\n"
-+			, __func__, pbtcoexadapter, pcoex_info->is_exist == _TRUE ? "TRUE" : "FALSE");
-+	}
-+}
-+
-+void rtw_btcoex_close_socket(_adapter *padapter)
-+{
-+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+
-+	RTW_INFO("%s--coex_info->is_exist: %s, pcoex_info->BT_attend:%s\n"
-+		, __func__, pcoex_info->is_exist == _TRUE ? "TRUE" : "FALSE", pcoex_info->BT_attend == _TRUE ? "TRUE" : "FALSE");
-+
-+	if (_TRUE == pcoex_info->is_exist) {
-+		if (_TRUE == pcoex_info->BT_attend) {
-+			/*inform BT wifi leave*/
-+			rtw_btcoex_sendmsgbysocket(padapter, wifi_leave, sizeof(wifi_leave), _FALSE);
-+			msleep(50);
-+		}
-+
-+		if (pcoex_info->btcoex_wq != NULL) {
-+			flush_workqueue(pcoex_info->btcoex_wq);
-+			destroy_workqueue(pcoex_info->btcoex_wq);
-+		}
-+
-+		rtw_btcoex_close_kernel_socket(padapter);
-+		pbtcoexadapter = NULL;
-+		pcoex_info->is_exist = _FALSE;
-+	}
-+}
-+
-+void rtw_btcoex_dump_tx_msg(u8 *tx_msg, u8 len, u8 *msg_name)
-+{
-+	u8	i = 0;
-+	RTW_INFO("======> Msg name: %s\n", msg_name);
-+	for (i = 0; i < len; i++)
-+		printk("%02x ", tx_msg[i]);
-+	printk("\n");
-+	RTW_INFO("Msg name: %s <======\n", msg_name);
-+}
-+
-+/* Porting from Windows team */
-+void rtw_btcoex_SendEventExtBtCoexControl(PADAPTER padapter, u8 bNeedDbgRsp, u8 dataLen, void *pData)
-+{
-+	u8			len = 0, tx_event_length = 0;
-+	u8 			localBuf[32] = "";
-+	u8			*pRetPar;
-+	u8			opCode = 0;
-+	u8			*pInBuf = (u8 *)pData;
-+	u8			*pOpCodeContent;
-+	rtw_HCI_event *pEvent;
-+
-+	opCode = pInBuf[0];
-+
-+	RTW_INFO("%s, OPCode:%02x\n", __func__, opCode);
-+
-+	pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+	/* len += bthci_ExtensionEventHeaderRtk(&localBuf[0], */
-+	/*	HCI_EVENT_EXT_BT_COEX_CONTROL); */
-+	pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
-+	pEvent->Data[0] = HCI_EVENT_EXT_BT_COEX_CONTROL;	/* extension event code */
-+	len++;
-+
-+	/* Return parameters starts from here */
-+	pRetPar = &pEvent->Data[len];
-+	_rtw_memcpy(&pRetPar[0], pData, dataLen);
-+
-+	len += dataLen;
-+
-+	pEvent->Length = len;
-+
-+	/* total tx event length + EventCode length + sizeof(length) */
-+	tx_event_length = pEvent->Length + 2;
-+#if 0
-+	rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT COEX CONTROL", _FALSE);
-+#endif
-+	rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+
-+}
-+
-+/* Porting from Windows team */
-+void rtw_btcoex_SendEventExtBtInfoControl(PADAPTER padapter, u8 dataLen, void *pData)
-+{
-+	rtw_HCI_event *pEvent;
-+	u8			*pRetPar;
-+	u8			len = 0, tx_event_length = 0;
-+	u8 			localBuf[32] = "";
-+
-+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+	PBT_MGNT		pBtMgnt = &pcoex_info->BtMgnt;
-+
-+	/* RTW_INFO("%s\n",__func__);*/
-+	if (pBtMgnt->ExtConfig.HCIExtensionVer < 4) { /* not support */
-+		RTW_INFO("ERROR: HCIExtensionVer = %d, HCIExtensionVer<4 !!!!\n", pBtMgnt->ExtConfig.HCIExtensionVer);
-+		return;
-+	}
-+
-+	pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+	/* len += bthci_ExtensionEventHeaderRtk(&localBuf[0], */
-+	/*		HCI_EVENT_EXT_BT_INFO_CONTROL); */
-+	pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
-+	pEvent->Data[0] = HCI_EVENT_EXT_BT_INFO_CONTROL;		/* extension event code */
-+	len++;
-+
-+	/* Return parameters starts from here */
-+	pRetPar = &pEvent->Data[len];
-+	_rtw_memcpy(&pRetPar[0], pData, dataLen);
-+
-+	len += dataLen;
-+
-+	pEvent->Length = len;
-+
-+	/* total tx event length + EventCode length + sizeof(length) */
-+	tx_event_length = pEvent->Length + 2;
-+#if 0
-+	rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT INFO CONTROL");
-+#endif
-+	rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+
-+}
-+
-+void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType)
-+{
-+	u8	len = 0, tx_event_length = 0;
-+	u8 	localBuf[7] = "";
-+	u8	*pRetPar;
-+	u8	*pu1Temp;
-+	rtw_HCI_event *pEvent;
-+	struct bt_coex_info *pcoex_info = &padapter->coex_info;
-+	PBT_MGNT		pBtMgnt = &pcoex_info->BtMgnt;
-+
-+	/*	if(!pBtMgnt->BtOperationOn)
-+	 *		return; */
-+
-+	pEvent = (rtw_HCI_event *)(&localBuf[0]);
-+
-+	/*	len += bthci_ExtensionEventHeaderRtk(&localBuf[0],
-+	 *			HCI_EVENT_EXT_WIFI_SCAN_NOTIFY); */
-+
-+	pEvent->EventCode = HCI_EVENT_EXTENSION_RTK;
-+	pEvent->Data[0] = HCI_EVENT_EXT_WIFI_SCAN_NOTIFY;		/* extension event code */
-+	len++;
-+
-+	/* Return parameters starts from here */
-+	/* pRetPar = &PPacketIrpEvent->Data[len]; */
-+	/* pu1Temp = (u8 *)&pRetPar[0]; */
-+	/* *pu1Temp = scanType; */
-+	pEvent->Data[len] = scanType;
-+	len += 1;
-+
-+	pEvent->Length = len;
-+
-+	/* total tx event length + EventCode length + sizeof(length) */
-+	tx_event_length = pEvent->Length + 2;
-+#if 0
-+	rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "WIFI SCAN OPERATION");
-+#endif
-+	rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE);
-+}
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+#endif /* CONFIG_BT_COEXIST */
-+
-+void rtw_btcoex_set_ant_info(PADAPTER padapter)
-+{
-+#ifdef CONFIG_BT_COEXIST
-+	PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
-+
-+	if (hal->EEPROMBluetoothCoexist == _TRUE) {
-+		u8 bMacPwrCtrlOn = _FALSE;
-+
-+		rtw_btcoex_AntInfoSetting(padapter);
-+		rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+		if (bMacPwrCtrlOn == _TRUE)
-+			rtw_btcoex_PowerOnSetting(padapter);
-+	}
-+	else
-+#endif
-+		rtw_btcoex_wifionly_AntInfoSetting(padapter);
-+}
-+
-+void rtw_btcoex_connect_notify(PADAPTER padapter, u8 join_type)
-+{
-+#ifdef CONFIG_BT_COEXIST
-+	PHAL_DATA_TYPE	pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	if (pHalData->EEPROMBluetoothCoexist == _TRUE)
-+		_rtw_btcoex_connect_notify(padapter, join_type ? _FALSE : _TRUE);
-+	else
-+#endif /* CONFIG_BT_COEXIST */
-+	rtw_btcoex_wifionly_connect_notify(padapter);
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/core/rtw_btcoex_wifionly.c b/drivers/staging/rtl8723cs/core/rtw_btcoex_wifionly.c
-new file mode 100644
-index 000000000000..d9872b0221e7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_btcoex_wifionly.c
-@@ -0,0 +1,47 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include <drv_types.h>
-+#include <hal_btcoex_wifionly.h>
-+#include <hal_data.h>
-+
-+void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter)
-+{
-+	hal_btcoex_wifionly_switchband_notify(padapter);
-+}
-+
-+void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter)
-+{
-+	hal_btcoex_wifionly_scan_notify(padapter);
-+}
-+
-+void rtw_btcoex_wifionly_connect_notify(PADAPTER padapter)
-+{
-+	hal_btcoex_wifionly_connect_notify(padapter);
-+}
-+
-+void rtw_btcoex_wifionly_hw_config(PADAPTER padapter)
-+{
-+	hal_btcoex_wifionly_hw_config(padapter);
-+}
-+
-+void rtw_btcoex_wifionly_initialize(PADAPTER padapter)
-+{
-+	hal_btcoex_wifionly_initlizevariables(padapter);
-+}
-+
-+void rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter)
-+{
-+	hal_btcoex_wifionly_AntInfoSetting(padapter);
-+}
-diff --git a/drivers/staging/rtl8723cs/core/rtw_chplan.c b/drivers/staging/rtl8723cs/core/rtw_chplan.c
-new file mode 100644
-index 000000000000..2754b0a94d47
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_chplan.c
-@@ -0,0 +1,2516 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2018 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_CHPLAN_C_
-+
-+#include <drv_types.h>
-+
-+#define RTW_DOMAIN_MAP_VER		"54"
-+#define RTW_DOMAIN_MAP_M_VER	"g"
-+#define RTW_COUNTRY_MAP_VER		"27"
-+
-+struct ch_list_t {
-+	u8 *len_ch_attr;
-+};
-+
-+#define CLA_2G_12_14_PASSIVE	BIT0
-+
-+#define CLA_5G_B1_PASSIVE		BIT0
-+#define CLA_5G_B2_PASSIVE		BIT1
-+#define CLA_5G_B3_PASSIVE		BIT2
-+#define CLA_5G_B4_PASSIVE		BIT3
-+#define CLA_5G_B2_DFS			BIT4
-+#define CLA_5G_B3_DFS			BIT5
-+#define CLA_5G_B4_DFS			BIT6
-+
-+#define CH_LIST_ENT(_len, arg...) \
-+	{.len_ch_attr = (u8[_len + 2]) {_len, ##arg}, }
-+
-+#define CH_LIST_LEN(_ch_list) (_ch_list.len_ch_attr[0])
-+#define CH_LIST_CH(_ch_list, _i) (_ch_list.len_ch_attr[_i + 1])
-+#define CH_LIST_ATTRIB(_ch_list) (_ch_list.len_ch_attr[CH_LIST_LEN(_ch_list) + 1])
-+
-+enum rtw_chd_2g {
-+	RTW_CHD_2G_00 = 0,
-+	RTW_CHD_2G_01 = 1,
-+	RTW_CHD_2G_02 = 2,
-+	RTW_CHD_2G_03 = 3,
-+	RTW_CHD_2G_04 = 4,
-+	RTW_CHD_2G_05 = 5,
-+	RTW_CHD_2G_06 = 6,
-+
-+	RTW_CHD_2G_MAX,
-+	RTW_CHD_2G_NULL = RTW_CHD_2G_00,
-+};
-+
-+enum rtw_chd_5g {
-+	RTW_CHD_5G_00 = 0,
-+	RTW_CHD_5G_01 = 1,
-+	RTW_CHD_5G_02 = 2,
-+	RTW_CHD_5G_03 = 3,
-+	RTW_CHD_5G_04 = 4,
-+	RTW_CHD_5G_05 = 5,
-+	RTW_CHD_5G_06 = 6,
-+	RTW_CHD_5G_07 = 7,
-+	RTW_CHD_5G_08 = 8,
-+	RTW_CHD_5G_09 = 9,
-+	RTW_CHD_5G_10 = 10,
-+	RTW_CHD_5G_11 = 11,
-+	RTW_CHD_5G_12 = 12,
-+	RTW_CHD_5G_13 = 13,
-+	RTW_CHD_5G_14 = 14,
-+	RTW_CHD_5G_15 = 15,
-+	RTW_CHD_5G_16 = 16,
-+	RTW_CHD_5G_17 = 17,
-+	RTW_CHD_5G_18 = 18,
-+	RTW_CHD_5G_19 = 19,
-+	RTW_CHD_5G_20 = 20,
-+	RTW_CHD_5G_21 = 21,
-+	RTW_CHD_5G_22 = 22,
-+	RTW_CHD_5G_23 = 23,
-+	RTW_CHD_5G_24 = 24,
-+	RTW_CHD_5G_25 = 25,
-+	RTW_CHD_5G_26 = 26,
-+	RTW_CHD_5G_27 = 27,
-+	RTW_CHD_5G_28 = 28,
-+	RTW_CHD_5G_29 = 29,
-+	RTW_CHD_5G_30 = 30,
-+	RTW_CHD_5G_31 = 31,
-+	RTW_CHD_5G_32 = 32,
-+	RTW_CHD_5G_33 = 33,
-+	RTW_CHD_5G_34 = 34,
-+	RTW_CHD_5G_35 = 35,
-+	RTW_CHD_5G_36 = 36,
-+	RTW_CHD_5G_37 = 37,
-+	RTW_CHD_5G_38 = 38,
-+	RTW_CHD_5G_39 = 39,
-+	RTW_CHD_5G_40 = 40,
-+	RTW_CHD_5G_41 = 41,
-+	RTW_CHD_5G_42 = 42,
-+	RTW_CHD_5G_43 = 43,
-+	RTW_CHD_5G_44 = 44,
-+	RTW_CHD_5G_45 = 45,
-+	RTW_CHD_5G_46 = 46,
-+	RTW_CHD_5G_47 = 47,
-+	RTW_CHD_5G_48 = 48,
-+	RTW_CHD_5G_49 = 49,
-+	RTW_CHD_5G_50 = 50,
-+	RTW_CHD_5G_51 = 51,
-+
-+	RTW_CHD_5G_MAX,
-+	RTW_CHD_5G_NULL = RTW_CHD_5G_00,
-+};
-+
-+static const struct ch_list_t rtw_channel_def_2g[] = {
-+	/* 0, RTW_CHD_2G_00 */	CH_LIST_ENT(0, 0),
-+	/* 1, RTW_CHD_2G_01 */	CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, CLA_2G_12_14_PASSIVE),
-+	/* 2, RTW_CHD_2G_02 */	CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0),
-+	/* 3, RTW_CHD_2G_03 */	CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 0),
-+	/* 4, RTW_CHD_2G_04 */	CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0),
-+	/* 5, RTW_CHD_2G_05 */	CH_LIST_ENT(4, 10, 11, 12, 13, 0),
-+	/* 6, RTW_CHD_2G_06 */	CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, CLA_2G_12_14_PASSIVE),
-+};
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+static const struct ch_list_t rtw_channel_def_5g[] = {
-+	/* 0, RTW_CHD_5G_00 */	CH_LIST_ENT(0, 0),
-+	/* 1, RTW_CHD_5G_01 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 2, RTW_CHD_5G_02 */	CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 3, RTW_CHD_5G_03 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 4, RTW_CHD_5G_04 */	CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 5, RTW_CHD_5G_05 */	CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 6, RTW_CHD_5G_06 */	CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165, 0),
-+	/* 7, RTW_CHD_5G_07 */	CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_DFS),
-+	/* 8, RTW_CHD_5G_08 */	CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, CLA_5G_B2_DFS),
-+	/* 9, RTW_CHD_5G_09 */	CH_LIST_ENT(5, 149, 153, 157, 161, 165, 0),
-+	/* 10, RTW_CHD_5G_10 */	CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64, CLA_5G_B2_DFS),
-+	/* 11, RTW_CHD_5G_11 */	CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, CLA_5G_B3_DFS),
-+	/* 12, RTW_CHD_5G_12 */	CH_LIST_ENT(16, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 13, RTW_CHD_5G_13 */	CH_LIST_ENT(8, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_DFS),
-+	/* 14, RTW_CHD_5G_14 */	CH_LIST_ENT(4, 36, 40, 44, 48, 0),
-+	/* 15, RTW_CHD_5G_15 */	CH_LIST_ENT(4, 149, 153, 157, 161, 0),
-+	/* 16, RTW_CHD_5G_16 */	CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 0),
-+	/* 17, RTW_CHD_5G_17 */	CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 18, RTW_CHD_5G_18 */	CH_LIST_ENT(17, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 19, RTW_CHD_5G_19 */	CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 20, RTW_CHD_5G_20 */	CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 21, RTW_CHD_5G_21 */	CH_LIST_ENT(11, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 22, RTW_CHD_5G_22 */	CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 23, RTW_CHD_5G_23 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 24, RTW_CHD_5G_24 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE),
-+	/* 25, RTW_CHD_5G_25 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE),
-+	/* 26, RTW_CHD_5G_26 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE),
-+	/* 27, RTW_CHD_5G_27 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE),
-+	/* 28, RTW_CHD_5G_28 */	CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_PASSIVE),
-+	/* 29, RTW_CHD_5G_29 */	CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE),
-+	/* 30, RTW_CHD_5G_30 */	CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B4_PASSIVE),
-+	/* 31, RTW_CHD_5G_31 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE),
-+	/* 32, RTW_CHD_5G_32 */	CH_LIST_ENT(9, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B2_DFS),
-+	/* 33, RTW_CHD_5G_33 */	CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 34, RTW_CHD_5G_34 */	CH_LIST_ENT(13, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B3_DFS),
-+	/* 35, RTW_CHD_5G_35 */	CH_LIST_ENT(8, 100, 104, 108, 112, 116, 132, 136, 140, CLA_5G_B3_DFS),
-+	/* 36, RTW_CHD_5G_36 */	CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_PASSIVE | CLA_5G_B3_DFS | CLA_5G_B4_PASSIVE),
-+	/* 37, RTW_CHD_5G_37 */	CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE),
-+	/* 38, RTW_CHD_5G_38 */	CH_LIST_ENT(16, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 39, RTW_CHD_5G_39 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_DFS | CLA_5G_B4_DFS),
-+	/* 40, RTW_CHD_5G_40 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 41, RTW_CHD_5G_41 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS | CLA_5G_B4_PASSIVE),
-+	/* 42, RTW_CHD_5G_42 */	CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_DFS | CLA_5G_B3_DFS | CLA_5G_B4_PASSIVE),
-+	/* 43, RTW_CHD_5G_43 */	CH_LIST_ENT(23, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE),
-+	/* 44, RTW_CHD_5G_44 */	CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE | CLA_5G_B4_PASSIVE),
-+	/* 45, RTW_CHD_5G_45 */	CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165, CLA_5G_B1_PASSIVE | CLA_5G_B2_PASSIVE | CLA_5G_B4_PASSIVE),
-+	/* 46, RTW_CHD_5G_46 */	CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, CLA_5G_B2_PASSIVE),
-+	/* 47, RTW_CHD_5G_47 */	CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, CLA_5G_B2_PASSIVE | CLA_5G_B3_PASSIVE),
-+	/* 48, RTW_CHD_5G_48 */	CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 49, RTW_CHD_5G_49 */	CH_LIST_ENT(17, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 50, RTW_CHD_5G_50 */	CH_LIST_ENT(17, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 144, 149, 153, 157, 161, 165, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+	/* 51, RTW_CHD_5G_51 */	CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, CLA_5G_B2_DFS | CLA_5G_B3_DFS),
-+};
-+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-+
-+struct chplan_ent_t {
-+	u8 regd_2g; /* value of REGULATION_TXPWR_LMT */
-+	u8 chd_2g;
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	u8 regd_5g; /* value of REGULATION_TXPWR_LMT */
-+	u8 chd_5g;
-+#endif
-+};
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+#define CHPLAN_ENT(_regd_2g, _chd_2g, _regd_5g, _chd_5g) {.regd_2g = _regd_2g, .chd_2g = _chd_2g, .regd_5g = _regd_5g, .chd_5g = _chd_5g}
-+#else
-+#define CHPLAN_ENT(_regd_2g, _chd_2g, _regd_5g, _chd_5g) {.regd_2g = _regd_2g, .chd_2g = _chd_2g}
-+#endif
-+
-+#define CHPLAN_ENT_NOT_DEFINED CHPLAN_ENT(TXPWR_LMT_NONE, RTW_CHD_2G_NULL, TXPWR_LMT_NONE, RTW_CHD_5G_NULL)
-+
-+static const struct chplan_ent_t RTW_ChannelPlanMap[] = {
-+	/* 0x00 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_49),
-+	/* 0x01 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_50),
-+	/* 0x02 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_03,	TXPWR_LMT_ETSI,		RTW_CHD_5G_07),
-+	/* 0x03 */	CHPLAN_ENT(TXPWR_LMT_ACMA,		RTW_CHD_2G_02,	TXPWR_LMT_ACMA,		RTW_CHD_5G_33),
-+	/* 0x04 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_51),
-+	/* 0x05 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x06 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x07 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x08 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x09 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x0A */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x0B */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x0C */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x0D */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x0E */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x0F */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x10 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x11 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x12 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x13 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x14 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x15 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x16 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x17 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x18 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x19 */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x1A */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x1B */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x1C */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x1D */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x1E */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x1F */	CHPLAN_ENT_NOT_DEFINED,
-+	/* 0x20 */	CHPLAN_ENT(TXPWR_LMT_WW,		RTW_CHD_2G_01,	TXPWR_LMT_NONE,		RTW_CHD_5G_00),
-+	/* 0x21 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_NONE,		RTW_CHD_5G_00),
-+	/* 0x22 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_03,	TXPWR_LMT_NONE,		RTW_CHD_5G_00),
-+	/* 0x23 */	CHPLAN_ENT(TXPWR_LMT_MKK,		RTW_CHD_2G_04,	TXPWR_LMT_NONE,		RTW_CHD_5G_00),
-+	/* 0x24 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_05,	TXPWR_LMT_NONE,		RTW_CHD_5G_00),
-+	/* 0x25 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_03,	TXPWR_LMT_FCC,		RTW_CHD_5G_03),
-+	/* 0x26 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_02),
-+	/* 0x27 */	CHPLAN_ENT(TXPWR_LMT_MKK,		RTW_CHD_2G_04,	TXPWR_LMT_MKK,		RTW_CHD_5G_02),
-+	/* 0x28 */	CHPLAN_ENT(TXPWR_LMT_KCC,		RTW_CHD_2G_01,	TXPWR_LMT_KCC,		RTW_CHD_5G_05),
-+	/* 0x29 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_01,	TXPWR_LMT_FCC,		RTW_CHD_5G_06),
-+	/* 0x2A */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_02,	TXPWR_LMT_NONE,		RTW_CHD_5G_00),
-+	/* 0x2B */	CHPLAN_ENT(TXPWR_LMT_IC,		RTW_CHD_2G_02,	TXPWR_LMT_IC,		RTW_CHD_5G_33),
-+	/* 0x2C */	CHPLAN_ENT(TXPWR_LMT_MKK,		RTW_CHD_2G_02,	TXPWR_LMT_NONE,		RTW_CHD_5G_00),
-+	/* 0x2D */	CHPLAN_ENT(TXPWR_LMT_CHILE,		RTW_CHD_2G_01,	TXPWR_LMT_CHILE,	RTW_CHD_5G_22),
-+	/* 0x2E */	CHPLAN_ENT(TXPWR_LMT_WW,		RTW_CHD_2G_03,	TXPWR_LMT_WW,		RTW_CHD_5G_37),
-+	/* 0x2F */	CHPLAN_ENT(TXPWR_LMT_CHILE,		RTW_CHD_2G_01,	TXPWR_LMT_CHILE,	RTW_CHD_5G_38),
-+	/* 0x30 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_01,	TXPWR_LMT_FCC,		RTW_CHD_5G_07),
-+	/* 0x31 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_01,	TXPWR_LMT_FCC,		RTW_CHD_5G_08),
-+	/* 0x32 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_01,	TXPWR_LMT_FCC,		RTW_CHD_5G_09),
-+	/* 0x33 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_01,	TXPWR_LMT_FCC,		RTW_CHD_5G_10),
-+	/* 0x34 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_03,	TXPWR_LMT_FCC,		RTW_CHD_5G_01),
-+	/* 0x35 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_03),
-+	/* 0x36 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_04),
-+	/* 0x37 */	CHPLAN_ENT(TXPWR_LMT_MKK,		RTW_CHD_2G_04,	TXPWR_LMT_MKK,		RTW_CHD_5G_10),
-+	/* 0x38 */	CHPLAN_ENT(TXPWR_LMT_MKK,		RTW_CHD_2G_04,	TXPWR_LMT_MKK,		RTW_CHD_5G_11),
-+	/* 0x39 */	CHPLAN_ENT(TXPWR_LMT_NCC,		RTW_CHD_2G_03,	TXPWR_LMT_NCC,		RTW_CHD_5G_12),
-+	/* 0x3A */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_02),
-+	/* 0x3B */	CHPLAN_ENT(TXPWR_LMT_ACMA,		RTW_CHD_2G_02,	TXPWR_LMT_ACMA,		RTW_CHD_5G_01),
-+	/* 0x3C */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_10),
-+	/* 0x3D */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_15),
-+	/* 0x3E */	CHPLAN_ENT(TXPWR_LMT_KCC,		RTW_CHD_2G_02,	TXPWR_LMT_KCC,		RTW_CHD_5G_03),
-+	/* 0x3F */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_03,	TXPWR_LMT_FCC,		RTW_CHD_5G_22),
-+	/* 0x40 */	CHPLAN_ENT(TXPWR_LMT_NCC,		RTW_CHD_2G_03,	TXPWR_LMT_NCC,		RTW_CHD_5G_13),
-+	/* 0x41 */	CHPLAN_ENT(TXPWR_LMT_WW,		RTW_CHD_2G_06,	TXPWR_LMT_NONE,		RTW_CHD_5G_00),
-+	/* 0x42 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_14),
-+	/* 0x43 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_03,	TXPWR_LMT_FCC,		RTW_CHD_5G_06),
-+	/* 0x44 */	CHPLAN_ENT(TXPWR_LMT_NCC,		RTW_CHD_2G_03,	TXPWR_LMT_NCC,		RTW_CHD_5G_09),
-+	/* 0x45 */	CHPLAN_ENT(TXPWR_LMT_ACMA,		RTW_CHD_2G_01,	TXPWR_LMT_ACMA,		RTW_CHD_5G_01),
-+	/* 0x46 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_03,	TXPWR_LMT_FCC,		RTW_CHD_5G_15),
-+	/* 0x47 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_10),
-+	/* 0x48 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_07),
-+	/* 0x49 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_06),
-+	/* 0x4A */	CHPLAN_ENT(TXPWR_LMT_IC,		RTW_CHD_2G_03,	TXPWR_LMT_IC,		RTW_CHD_5G_33),
-+	/* 0x4B */	CHPLAN_ENT(TXPWR_LMT_KCC,		RTW_CHD_2G_02,	TXPWR_LMT_KCC,		RTW_CHD_5G_22),
-+	/* 0x4C */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_03,	TXPWR_LMT_FCC,		RTW_CHD_5G_28),
-+	/* 0x4D */	CHPLAN_ENT(TXPWR_LMT_MEXICO,	RTW_CHD_2G_02,	TXPWR_LMT_MEXICO,	RTW_CHD_5G_01),
-+	/* 0x4E */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_42),
-+	/* 0x4F */	CHPLAN_ENT(TXPWR_LMT_NONE,		RTW_CHD_2G_00,	TXPWR_LMT_MKK,		RTW_CHD_5G_43),
-+	/* 0x50 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_16),
-+	/* 0x51 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_09),
-+	/* 0x52 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_17),
-+	/* 0x53 */	CHPLAN_ENT(TXPWR_LMT_NCC,		RTW_CHD_2G_03,	TXPWR_LMT_NCC,		RTW_CHD_5G_18),
-+	/* 0x54 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_15),
-+	/* 0x55 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_03,	TXPWR_LMT_FCC,		RTW_CHD_5G_01),
-+	/* 0x56 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_19),
-+	/* 0x57 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_03,	TXPWR_LMT_FCC,		RTW_CHD_5G_20),
-+	/* 0x58 */	CHPLAN_ENT(TXPWR_LMT_MKK,		RTW_CHD_2G_02,	TXPWR_LMT_MKK,		RTW_CHD_5G_14),
-+	/* 0x59 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_21),
-+	/* 0x5A */	CHPLAN_ENT(TXPWR_LMT_NONE,		RTW_CHD_2G_00,	TXPWR_LMT_FCC,		RTW_CHD_5G_44),
-+	/* 0x5B */	CHPLAN_ENT(TXPWR_LMT_NONE,		RTW_CHD_2G_00,	TXPWR_LMT_FCC,		RTW_CHD_5G_45),
-+	/* 0x5C */	CHPLAN_ENT(TXPWR_LMT_NONE,		RTW_CHD_2G_00,	TXPWR_LMT_FCC,		RTW_CHD_5G_43),
-+	/* 0x5D */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_08),
-+	/* 0x5E */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_03),
-+	/* 0x5F */	CHPLAN_ENT(TXPWR_LMT_MKK,		RTW_CHD_2G_02,	TXPWR_LMT_MKK,		RTW_CHD_5G_47),
-+	/* 0x60 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_03,	TXPWR_LMT_FCC,		RTW_CHD_5G_09),
-+	/* 0x61 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_02,	TXPWR_LMT_FCC,		RTW_CHD_5G_01),
-+	/* 0x62 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_02,	TXPWR_LMT_FCC,		RTW_CHD_5G_03),
-+	/* 0x63 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_23),
-+	/* 0x64 */	CHPLAN_ENT(TXPWR_LMT_MKK,		RTW_CHD_2G_02,	TXPWR_LMT_MKK,		RTW_CHD_5G_24),
-+	/* 0x65 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_24),
-+	/* 0x66 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_03,	TXPWR_LMT_FCC,		RTW_CHD_5G_27),
-+	/* 0x67 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_03,	TXPWR_LMT_FCC,		RTW_CHD_5G_25),
-+	/* 0x68 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_02,	TXPWR_LMT_FCC,		RTW_CHD_5G_27),
-+	/* 0x69 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_02,	TXPWR_LMT_FCC,		RTW_CHD_5G_25),
-+	/* 0x6A */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_25),
-+	/* 0x6B */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_01,	TXPWR_LMT_FCC,		RTW_CHD_5G_29),
-+	/* 0x6C */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_01,	TXPWR_LMT_FCC,		RTW_CHD_5G_26),
-+	/* 0x6D */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_02,	TXPWR_LMT_FCC,		RTW_CHD_5G_28),
-+	/* 0x6E */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_01,	TXPWR_LMT_FCC,		RTW_CHD_5G_25),
-+	/* 0x6F */	CHPLAN_ENT(TXPWR_LMT_NONE,		RTW_CHD_2G_00,	TXPWR_LMT_ETSI,		RTW_CHD_5G_06),
-+	/* 0x70 */	CHPLAN_ENT(TXPWR_LMT_NONE,		RTW_CHD_2G_00,	TXPWR_LMT_ETSI,		RTW_CHD_5G_30),
-+	/* 0x71 */	CHPLAN_ENT(TXPWR_LMT_NONE,		RTW_CHD_2G_00,	TXPWR_LMT_ETSI,		RTW_CHD_5G_25),
-+	/* 0x72 */	CHPLAN_ENT(TXPWR_LMT_NONE,		RTW_CHD_2G_00,	TXPWR_LMT_ETSI,		RTW_CHD_5G_31),
-+	/* 0x73 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_01,	TXPWR_LMT_FCC,		RTW_CHD_5G_01),
-+	/* 0x74 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_02,	TXPWR_LMT_FCC,		RTW_CHD_5G_19),
-+	/* 0x75 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_32),
-+	/* 0x76 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_02,	TXPWR_LMT_FCC,		RTW_CHD_5G_22),
-+	/* 0x77 */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_01,	TXPWR_LMT_ETSI,		RTW_CHD_5G_34),
-+	/* 0x78 */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_03,	TXPWR_LMT_FCC,		RTW_CHD_5G_35),
-+	/* 0x79 */	CHPLAN_ENT(TXPWR_LMT_MKK,		RTW_CHD_2G_02,	TXPWR_LMT_MKK,		RTW_CHD_5G_02),
-+	/* 0x7A */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_28),
-+	/* 0x7B */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_46),
-+	/* 0x7C */	CHPLAN_ENT(TXPWR_LMT_ETSI,		RTW_CHD_2G_02,	TXPWR_LMT_ETSI,		RTW_CHD_5G_47),
-+	/* 0x7D */	CHPLAN_ENT(TXPWR_LMT_MKK,		RTW_CHD_2G_04,	TXPWR_LMT_MKK,		RTW_CHD_5G_48),
-+	/* 0x7E */	CHPLAN_ENT(TXPWR_LMT_MKK,		RTW_CHD_2G_02,	TXPWR_LMT_MKK,		RTW_CHD_5G_48),
-+	/* 0x7F */	CHPLAN_ENT(TXPWR_LMT_FCC,		RTW_CHD_2G_01,	TXPWR_LMT_FCC,		RTW_CHD_5G_03),
-+};
-+
-+const int RTW_ChannelPlanMap_size = sizeof(RTW_ChannelPlanMap) / sizeof(RTW_ChannelPlanMap[0]);
-+
-+u8 rtw_chplan_get_default_regd_2g(u8 id)
-+{
-+	return RTW_ChannelPlanMap[id].regd_2g;
-+}
-+
-+u8 rtw_chplan_get_default_regd_5g(u8 id)
-+{
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	return RTW_ChannelPlanMap[id].regd_5g;
-+#else
-+	return TXPWR_LMT_NONE;
-+#endif
-+}
-+
-+u8 rtw_chplan_get_default_regd(u8 id)
-+{
-+	u8 regd_2g = rtw_chplan_get_default_regd_2g(id);
-+	u8 regd_5g = rtw_chplan_get_default_regd_5g(id);
-+
-+	if (regd_2g != TXPWR_LMT_NONE && regd_5g != TXPWR_LMT_NONE) {
-+		if (regd_2g != regd_5g)
-+			RTW_WARN("channel_plan:0x%02x, regd_2g:%u, regd_5g:%u not the same\n", id, regd_2g, regd_5g);
-+		return regd_5g;
-+	}
-+	return regd_2g != TXPWR_LMT_NONE ? regd_2g : regd_5g;
-+}
-+
-+bool rtw_chplan_is_empty(u8 id)
-+{
-+	const struct chplan_ent_t *chplan_map = &RTW_ChannelPlanMap[id];
-+
-+	if (chplan_map->chd_2g == RTW_CHD_2G_NULL
-+		#if CONFIG_IEEE80211_BAND_5GHZ
-+		&& chplan_map->chd_5g == RTW_CHD_5G_NULL
-+		#endif
-+	)
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+bool rtw_is_channel_plan_valid(u8 id)
-+{
-+	return id < RTW_ChannelPlanMap_size && !rtw_chplan_is_empty(id);
-+}
-+
-+bool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch)
-+{
-+	int i;
-+
-+	for (i = 0; i < MAX_CHANNEL_NUM; i++) {
-+		if (regsty->excl_chs[i] == 0)
-+			break;
-+		if (regsty->excl_chs[i] == ch)
-+			return _TRUE;
-+	}
-+	return _FALSE;
-+}
-+
-+const char *_regd_src_str[] = {
-+	[REGD_SRC_RTK_PRIV] = "RTK_PRIV",
-+	[REGD_SRC_OS] = "OS",
-+	[REGD_SRC_NUM] = "UNKNOWN",
-+};
-+
-+static u8 init_channel_set_from_rtk_priv(_adapter *padapter, RT_CHANNEL_INFO *channel_set)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	struct registry_priv *regsty = adapter_to_regsty(padapter);
-+	u8 ChannelPlan = rfctl->ChannelPlan;
-+	u8 index, chanset_size = 0;
-+	u8 b5GBand = _FALSE, b2_4GBand = _FALSE;
-+	u8 ch, attrib;
-+#ifdef CONFIG_DFS_MASTER
-+	int i;
-+#endif
-+
-+	if (!rtw_is_channel_plan_valid(ChannelPlan)) {
-+		RTW_ERR("ChannelPlan ID 0x%02X error !!!!!\n", ChannelPlan);
-+		return chanset_size;
-+	}
-+
-+	_rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
-+
-+	if (IsSupported24G(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_2G))
-+		b2_4GBand = _TRUE;
-+
-+	if (is_supported_5g(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_5G))
-+		b5GBand = _TRUE;
-+
-+	if (b2_4GBand == _FALSE && b5GBand == _FALSE) {
-+		RTW_WARN("HW band_cap has no intersection with SW wireless_mode setting\n");
-+		return chanset_size;
-+	}
-+
-+	if (b2_4GBand) {
-+		u8 chd_2g = RTW_ChannelPlanMap[ChannelPlan].chd_2g;
-+
-+		attrib = CH_LIST_ATTRIB(rtw_channel_def_2g[chd_2g]);
-+
-+		for (index = 0; index < CH_LIST_LEN(rtw_channel_def_2g[chd_2g]); index++) {
-+			ch = CH_LIST_CH(rtw_channel_def_2g[chd_2g], index);
-+			if (rtw_regsty_is_excl_chs(regsty, ch) == _TRUE)
-+				continue;
-+
-+			if (chanset_size >= MAX_CHANNEL_NUM) {
-+				RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM);
-+				break;
-+			}
-+
-+			channel_set[chanset_size].ChannelNum = ch;
-+
-+			if (ch >= 12 && ch <= 14 && (attrib & CLA_2G_12_14_PASSIVE))
-+				channel_set[chanset_size].flags |= RTW_CHF_NO_IR;
-+
-+			if (channel_set[chanset_size].flags & RTW_CHF_NO_IR) {
-+				if (rfctl->country_ent || ch <= 11)
-+					RTW_INFO("ch%u is PASSIVE\n", ch);
-+			}
-+
-+			chanset_size++;
-+		}
-+	}
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	if (b5GBand) {
-+		bool dfs;
-+		u8 chd_5g = RTW_ChannelPlanMap[ChannelPlan].chd_5g;
-+
-+		attrib = CH_LIST_ATTRIB(rtw_channel_def_5g[chd_5g]);
-+
-+		for (index = 0; index < CH_LIST_LEN(rtw_channel_def_5g[chd_5g]); index++) {
-+			ch = CH_LIST_CH(rtw_channel_def_5g[chd_5g], index);
-+			if (rtw_regsty_is_excl_chs(regsty, ch) == _TRUE)
-+				continue;
-+			dfs = (rtw_is_5g_band2(ch) && (attrib & CLA_5G_B2_DFS))
-+				|| (rtw_is_5g_band3(ch) && (attrib & CLA_5G_B3_DFS))
-+				|| (rtw_is_5g_band4(ch) && (attrib & CLA_5G_B4_DFS));
-+			#if !CONFIG_DFS
-+			if (dfs)
-+				continue;
-+			#endif
-+
-+			if (chanset_size >= MAX_CHANNEL_NUM) {
-+				RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM);
-+				break;
-+			}
-+
-+			channel_set[chanset_size].ChannelNum = ch;
-+
-+			if ((rtw_is_5g_band1(ch) && (attrib & CLA_5G_B1_PASSIVE)) /* band1 passive */
-+				|| (rtw_is_5g_band2(ch) && (attrib & CLA_5G_B2_PASSIVE)) /* band2 passive */
-+				|| (rtw_is_5g_band3(ch) && (attrib & CLA_5G_B3_PASSIVE)) /* band3 passive */
-+				|| (rtw_is_5g_band4(ch) && (attrib & CLA_5G_B4_PASSIVE)) /* band4 passive */
-+			)
-+				channel_set[chanset_size].flags |= RTW_CHF_NO_IR;
-+
-+			if (dfs)
-+				channel_set[chanset_size].flags |= RTW_CHF_DFS;
-+
-+			if (channel_set[chanset_size].flags & RTW_CHF_NO_IR) {
-+				if (rfctl->country_ent || (channel_set[chanset_size].flags & RTW_CHF_DFS))
-+					RTW_INFO("ch%u is PASSIVE%s\n", ch, dfs ? " DFS" : "");
-+			}
-+
-+			chanset_size++;
-+		}
-+	}
-+
-+	#ifdef CONFIG_DFS_MASTER
-+	for (i = 0; i < chanset_size; i++)
-+		channel_set[i].non_ocp_end_time = rtw_get_current_time();
-+	#endif
-+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-+
-+	if (chanset_size)
-+		RTW_INFO(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, ch num:%d\n"
-+			, FUNC_ADPT_ARG(padapter), ChannelPlan, chanset_size);
-+	else
-+		RTW_WARN(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, final chset has no channel\n"
-+			, FUNC_ADPT_ARG(padapter), ChannelPlan);
-+
-+	return chanset_size;
-+}
-+
-+u8 init_channel_set(_adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	if (rfctl->regd_src == REGD_SRC_RTK_PRIV)
-+		return init_channel_set_from_rtk_priv(adapter, rfctl->channel_set);
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+	else if (rfctl->regd_src == REGD_SRC_OS)
-+		return rtw_os_init_channel_set(adapter, rfctl->channel_set);
-+#endif
-+	else
-+		rtw_warn_on(1);
-+
-+	return 0;
-+}
-+
-+bool rtw_chset_is_dfs_range(struct _RT_CHANNEL_INFO *chset, u32 hi, u32 lo)
-+{
-+	u8 hi_ch = rtw_freq2ch(hi);
-+	u8 lo_ch = rtw_freq2ch(lo);
-+	int i;
-+
-+	for (i = 0; i < MAX_CHANNEL_NUM && chset[i].ChannelNum != 0; i++){
-+		if (!(chset[i].flags & RTW_CHF_DFS))
-+			continue;
-+		if (hi_ch > chset[i].ChannelNum && lo_ch < chset[i].ChannelNum)
-+			return 1;
-+	}
-+
-+	return 0;
-+}
-+
-+bool rtw_chset_is_dfs_ch(struct _RT_CHANNEL_INFO *chset, u8 ch)
-+{
-+	int i;
-+
-+	for (i = 0; i < MAX_CHANNEL_NUM && chset[i].ChannelNum != 0; i++){
-+		if (chset[i].ChannelNum == ch)
-+			return chset[i].flags & RTW_CHF_DFS ? 1 : 0;
-+	}
-+
-+	return 0;
-+}
-+
-+bool rtw_chset_is_dfs_chbw(struct _RT_CHANNEL_INFO *chset, u8 ch, u8 bw, u8 offset)
-+{
-+	u32 hi, lo;
-+
-+	if (!rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo))
-+		return 0;
-+
-+	return rtw_chset_is_dfs_range(chset, hi, lo);
-+}
-+
-+u8 rtw_process_beacon_hint(_adapter *adapter, WLAN_BSSID_EX *bss)
-+{
-+#ifndef RTW_CHPLAN_BEACON_HINT_NON_WORLD_WIDE
-+#define RTW_CHPLAN_BEACON_HINT_NON_WORLD_WIDE 0
-+#endif
-+
-+#ifndef RTW_CHPLAN_BEACON_HINT_ON_2G_CH_1_11
-+#define RTW_CHPLAN_BEACON_HINT_ON_2G_CH_1_11 0
-+#endif
-+
-+#ifndef RTW_CHPLAN_BEACON_HINT_ON_DFS_CH
-+#define RTW_CHPLAN_BEACON_HINT_ON_DFS_CH 0
-+#endif
-+
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	RT_CHANNEL_INFO *chset = rfctl->channel_set;
-+	u8 ch = bss->Configuration.DSConfig;
-+	int chset_idx = rtw_chset_search_ch(chset, ch);
-+	u8 act_cnt = 0;
-+
-+	if (chset_idx < 0)
-+		goto exit;
-+
-+	if ((chset[chset_idx].flags & RTW_CHF_NO_IR)
-+		&& (RTW_CHPLAN_BEACON_HINT_NON_WORLD_WIDE || !rfctl->country_ent || IS_ALPHA2_WORLDWIDE(rfctl->country_ent->alpha2))
-+		&& (RTW_CHPLAN_BEACON_HINT_ON_2G_CH_1_11 || !(ch <= 11))
-+		&& (RTW_CHPLAN_BEACON_HINT_ON_DFS_CH || !(chset[chset_idx].flags & RTW_CHF_DFS))
-+	) {
-+		RTW_INFO("%s: change ch:%d to active\n", __func__, ch);
-+		chset[chset_idx].flags &= ~RTW_CHF_NO_IR;
-+		act_cnt++;
-+	}
-+
-+exit:
-+	return act_cnt;
-+}
-+
-+const char *_rtw_dfs_regd_str[] = {
-+	[RTW_DFS_REGD_NONE]	= "NONE",
-+	[RTW_DFS_REGD_FCC]	= "FCC",
-+	[RTW_DFS_REGD_MKK]	= "MKK",
-+	[RTW_DFS_REGD_ETSI]	= "ETSI",
-+};
-+
-+#ifdef CONFIG_80211AC_VHT
-+#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) , .en_11ac = (_val)
-+#else
-+#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val)
-+#endif
-+
-+#define COUNTRY_CHPLAN_ENT(_alpha2, _chplan, _en_11ac) \
-+	{.alpha2 = (_alpha2), .chplan = (_chplan) \
-+		COUNTRY_CHPLAN_ASSIGN_EN_11AC(_en_11ac) \
-+	}
-+
-+#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP
-+
-+#include "../platform/custom_country_chplan.h"
-+
-+#elif RTW_DEF_MODULE_REGULATORY_CERT
-+
-+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AE_HMC_M2) /* 2013 certify */
-+static const struct country_chplan RTL8821AE_HMC_M2_country_chplan_map[] = {
-+	COUNTRY_CHPLAN_ENT("AE", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("AL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AN", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("AR", 0x61, 1),
-+	COUNTRY_CHPLAN_ENT("AT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AU", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("AZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BH", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("BO", 0x73, 1),
-+	COUNTRY_CHPLAN_ENT("BR", 0x62, 1),
-+	COUNTRY_CHPLAN_ENT("BW", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("BY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CA", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("CH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CI", 0x42, 1),
-+	COUNTRY_CHPLAN_ENT("CL", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("CN", 0x51, 1),
-+	COUNTRY_CHPLAN_ENT("CO", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("CR", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("CY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DO", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("DZ", 0x00, 1),
-+	COUNTRY_CHPLAN_ENT("EC", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("EE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("EG", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("ES", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GT", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("HK", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("HN", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("HR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ID", 0x3D, 0),
-+	COUNTRY_CHPLAN_ENT("IE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IL", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("IN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("IS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("JM", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("JO", 0x49, 1),
-+	COUNTRY_CHPLAN_ENT("JP", 0x27, 1),
-+	COUNTRY_CHPLAN_ENT("KE", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("KG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1),
-+	COUNTRY_CHPLAN_ENT("KW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MA", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("MC", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ME", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MX", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("MY", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("MZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NG", 0x75, 1),
-+	COUNTRY_CHPLAN_ENT("NI", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("NL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NZ", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("OM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PA", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PE", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PK", 0x51, 1),
-+	COUNTRY_CHPLAN_ENT("PL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PR", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PY", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("QA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("RO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RU", 0x59, 1),
-+	COUNTRY_CHPLAN_ENT("SA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SN", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SV", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("TH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("TN", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("TR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TT", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1),
-+	COUNTRY_CHPLAN_ENT("UA", 0x36, 0),
-+	COUNTRY_CHPLAN_ENT("UG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("US", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("UY", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("VE", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("VN", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("ZA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("ZW", 0x26, 1),
-+};
-+#endif
-+
-+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AU) /* 2014 certify */
-+static const struct country_chplan RTL8821AU_country_chplan_map[] = {
-+	COUNTRY_CHPLAN_ENT("AE", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("AR", 0x61, 1),
-+	COUNTRY_CHPLAN_ENT("AT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AU", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("BE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CA", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("CH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("CY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("EE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ES", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HK", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("HU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ID", 0x3D, 0),
-+	COUNTRY_CHPLAN_ENT("IE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("JO", 0x49, 1),
-+	COUNTRY_CHPLAN_ENT("JP", 0x27, 1),
-+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1),
-+	COUNTRY_CHPLAN_ENT("KW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MC", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NZ", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("PL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RU", 0x59, 0),
-+	COUNTRY_CHPLAN_ENT("SA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1),
-+	COUNTRY_CHPLAN_ENT("UA", 0x36, 0),
-+	COUNTRY_CHPLAN_ENT("US", 0x34, 1),
-+};
-+#endif
-+
-+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AENF_NGFF) /* 2014 certify */
-+static const struct country_chplan RTL8812AENF_NGFF_country_chplan_map[] = {
-+	COUNTRY_CHPLAN_ENT("JP", 0x27, 1),
-+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1),
-+	COUNTRY_CHPLAN_ENT("US", 0x34, 1),
-+};
-+#endif
-+
-+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AEBT_HMC) /* 2013 certify */
-+static const struct country_chplan RTL8812AEBT_HMC_country_chplan_map[] = {
-+	COUNTRY_CHPLAN_ENT("AE", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("AT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AU", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("BE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CA", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("CH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("CY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("EE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ES", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HK", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("HR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("JO", 0x49, 1),
-+	COUNTRY_CHPLAN_ENT("JP", 0x27, 1),
-+	COUNTRY_CHPLAN_ENT("KE", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1),
-+	COUNTRY_CHPLAN_ENT("KW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MC", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NG", 0x75, 1),
-+	COUNTRY_CHPLAN_ENT("NL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NZ", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("OM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("QA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("RU", 0x59, 0),
-+	COUNTRY_CHPLAN_ENT("SA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1),
-+	COUNTRY_CHPLAN_ENT("UA", 0x36, 0),
-+	COUNTRY_CHPLAN_ENT("US", 0x34, 1),
-+};
-+#endif
-+
-+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8188EE_HMC_M2) /* 2012 certify */
-+static const struct country_chplan RTL8188EE_HMC_M2_country_chplan_map[] = {
-+	COUNTRY_CHPLAN_ENT("AE", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("AL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AN", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("AR", 0x61, 1),
-+	COUNTRY_CHPLAN_ENT("AT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AU", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("AW", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("AZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BB", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("BD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BH", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("BI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BJ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BN", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("BO", 0x73, 1),
-+	COUNTRY_CHPLAN_ENT("BR", 0x62, 1),
-+	COUNTRY_CHPLAN_ENT("BW", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("BY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CA", 0x20, 1),
-+	COUNTRY_CHPLAN_ENT("CD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CI", 0x42, 1),
-+	COUNTRY_CHPLAN_ENT("CL", 0x2D, 1),
-+	COUNTRY_CHPLAN_ENT("CM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("CO", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("CR", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("CV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DO", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("DZ", 0x00, 1),
-+	COUNTRY_CHPLAN_ENT("EC", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("EE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("EG", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("ES", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ET", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GD", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("GH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GN", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GQ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GT", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("GW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HK", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("HN", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("HR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HT", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("HU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ID", 0x5D, 1),
-+	COUNTRY_CHPLAN_ENT("IE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IL", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("IN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("IS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("JM", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("JO", 0x49, 1),
-+	COUNTRY_CHPLAN_ENT("JP", 0x27, 1),
-+	COUNTRY_CHPLAN_ENT("KE", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("KG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1),
-+	COUNTRY_CHPLAN_ENT("KW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MA", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("MC", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ME", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ML", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MX", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("MY", 0x63, 1),
-+	COUNTRY_CHPLAN_ENT("MZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NG", 0x75, 1),
-+	COUNTRY_CHPLAN_ENT("NI", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("NL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NP", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("NZ", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("OM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PA", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PE", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PK", 0x51, 1),
-+	COUNTRY_CHPLAN_ENT("PL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PR", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PY", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("QA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("RO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RU", 0x59, 1),
-+	COUNTRY_CHPLAN_ENT("RW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SC", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("SE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SN", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SV", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("TD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("TN", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("TR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TT", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1),
-+	COUNTRY_CHPLAN_ENT("TZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("UA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("UG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("US", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("UY", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("UZ", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("VC", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("VE", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("VN", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("ZA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("ZM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ZW", 0x26, 1),
-+};
-+#endif
-+
-+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BE_HMC_M2) /* 2013 certify */
-+static const struct country_chplan RTL8723BE_HMC_M2_country_chplan_map[] = {
-+	COUNTRY_CHPLAN_ENT("AE", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("AL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AN", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("AO", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("AR", 0x61, 1),
-+	COUNTRY_CHPLAN_ENT("AT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AU", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("AW", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("AZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BH", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("BI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BJ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BO", 0x73, 1),
-+	COUNTRY_CHPLAN_ENT("BR", 0x62, 1),
-+	COUNTRY_CHPLAN_ENT("BS", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("BW", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("BY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CA", 0x20, 1),
-+	COUNTRY_CHPLAN_ENT("CD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CI", 0x42, 1),
-+	COUNTRY_CHPLAN_ENT("CL", 0x2D, 1),
-+	COUNTRY_CHPLAN_ENT("CM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("CO", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("CR", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("CV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DO", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("DZ", 0x00, 1),
-+	COUNTRY_CHPLAN_ENT("EC", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("EE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("EG", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("ES", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ET", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GD", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("GH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GQ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GT", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("GW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HK", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("HN", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("HR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ID", 0x5D, 1),
-+	COUNTRY_CHPLAN_ENT("IE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IL", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("IN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("IS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("JM", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("JO", 0x49, 1),
-+	COUNTRY_CHPLAN_ENT("JP", 0x27, 1),
-+	COUNTRY_CHPLAN_ENT("KE", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("KG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1),
-+	COUNTRY_CHPLAN_ENT("KW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MA", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("MC", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ME", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ML", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MX", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("MY", 0x63, 1),
-+	COUNTRY_CHPLAN_ENT("MZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NG", 0x75, 1),
-+	COUNTRY_CHPLAN_ENT("NI", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("NL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NP", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("NZ", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("OM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PA", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PE", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PK", 0x51, 1),
-+	COUNTRY_CHPLAN_ENT("PL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PR", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PY", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("QA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("RO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RU", 0x59, 1),
-+	COUNTRY_CHPLAN_ENT("RW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SN", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SV", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("SZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("TN", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("TR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TT", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1),
-+	COUNTRY_CHPLAN_ENT("TZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("UA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("UG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("US", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("UY", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("UZ", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("VE", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("VN", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("ZA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("ZM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ZW", 0x26, 1),
-+};
-+#endif
-+
-+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BS_NGFF1216) /* 2014 certify */
-+static const struct country_chplan RTL8723BS_NGFF1216_country_chplan_map[] = {
-+	COUNTRY_CHPLAN_ENT("AE", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("AL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AN", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("AO", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("AR", 0x61, 1),
-+	COUNTRY_CHPLAN_ENT("AT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AU", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("AZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BB", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("BD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BH", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("BO", 0x73, 1),
-+	COUNTRY_CHPLAN_ENT("BR", 0x62, 1),
-+	COUNTRY_CHPLAN_ENT("BW", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("BY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CA", 0x20, 1),
-+	COUNTRY_CHPLAN_ENT("CH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CI", 0x42, 1),
-+	COUNTRY_CHPLAN_ENT("CL", 0x2D, 1),
-+	COUNTRY_CHPLAN_ENT("CN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("CO", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("CR", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("CY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DO", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("DZ", 0x00, 1),
-+	COUNTRY_CHPLAN_ENT("EC", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("EE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("EG", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("ES", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GT", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("HK", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("HN", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("HR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HT", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("HU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ID", 0x5D, 1),
-+	COUNTRY_CHPLAN_ENT("IE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IL", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("IN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("IS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("JM", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("JO", 0x49, 1),
-+	COUNTRY_CHPLAN_ENT("JP", 0x27, 1),
-+	COUNTRY_CHPLAN_ENT("KE", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("KG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1),
-+	COUNTRY_CHPLAN_ENT("KW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MA", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("MC", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ME", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MQ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MX", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("MY", 0x63, 1),
-+	COUNTRY_CHPLAN_ENT("MZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NG", 0x75, 1),
-+	COUNTRY_CHPLAN_ENT("NI", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("NL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NP", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("NZ", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("OM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PA", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PE", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PK", 0x51, 1),
-+	COUNTRY_CHPLAN_ENT("PL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PR", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PY", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("QA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("RO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RU", 0x59, 1),
-+	COUNTRY_CHPLAN_ENT("SA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SN", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SV", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("TH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("TJ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TN", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("TR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TT", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1),
-+	COUNTRY_CHPLAN_ENT("TZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("UA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("UG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("US", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("UY", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("UZ", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("VE", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("VN", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("YE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ZA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("ZW", 0x26, 1),
-+};
-+#endif
-+
-+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8192EEBT_HMC_M2) /* 2013 certify */
-+static const struct country_chplan RTL8192EEBT_HMC_M2_country_chplan_map[] = {
-+	COUNTRY_CHPLAN_ENT("AE", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("AL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AN", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("AO", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("AR", 0x61, 1),
-+	COUNTRY_CHPLAN_ENT("AT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AU", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("AW", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("AZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BH", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("BI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BJ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BO", 0x73, 1),
-+	COUNTRY_CHPLAN_ENT("BR", 0x62, 1),
-+	COUNTRY_CHPLAN_ENT("BW", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("BY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CA", 0x20, 1),
-+	COUNTRY_CHPLAN_ENT("CD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CI", 0x42, 1),
-+	COUNTRY_CHPLAN_ENT("CL", 0x2D, 1),
-+	COUNTRY_CHPLAN_ENT("CM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("CO", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("CR", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("CV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DJ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DO", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("DZ", 0x00, 1),
-+	COUNTRY_CHPLAN_ENT("EC", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("EE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("EG", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("EH", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("ES", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ET", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GD", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("GF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GQ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GT", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("GW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HK", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("HN", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("HR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ID", 0x5D, 1),
-+	COUNTRY_CHPLAN_ENT("IE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IL", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("IN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("IS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("JM", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("JO", 0x49, 1),
-+	COUNTRY_CHPLAN_ENT("JP", 0x27, 1),
-+	COUNTRY_CHPLAN_ENT("KE", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("KG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1),
-+	COUNTRY_CHPLAN_ENT("KW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MA", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("MC", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ME", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ML", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MX", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("MY", 0x63, 1),
-+	COUNTRY_CHPLAN_ENT("MZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NG", 0x75, 1),
-+	COUNTRY_CHPLAN_ENT("NI", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("NL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NP", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("NZ", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("OM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PA", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PE", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PK", 0x51, 1),
-+	COUNTRY_CHPLAN_ENT("PL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PR", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("PT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PY", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("QA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("RO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RU", 0x59, 1),
-+	COUNTRY_CHPLAN_ENT("RW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SC", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("SE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SN", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ST", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("SV", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("TD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("TN", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("TR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TT", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("TW", 0x39, 1),
-+	COUNTRY_CHPLAN_ENT("TZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("UA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("UG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("US", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("UY", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("UZ", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("VE", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("VN", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("YT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ZA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("ZM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ZW", 0x26, 1),
-+};
-+#endif
-+
-+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723DE_NGFF1630) /* 2016 certify */
-+static const struct country_chplan RTL8723DE_NGFF1630_country_chplan_map[] = {
-+	COUNTRY_CHPLAN_ENT("AE", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("AL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AN", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("AR", 0x61, 1),
-+	COUNTRY_CHPLAN_ENT("AT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AU", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("AZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BH", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("BO", 0x73, 1),
-+	COUNTRY_CHPLAN_ENT("BR", 0x62, 1),
-+	COUNTRY_CHPLAN_ENT("BY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CA", 0x2A, 1),
-+	COUNTRY_CHPLAN_ENT("CH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CI", 0x42, 1),
-+	COUNTRY_CHPLAN_ENT("CL", 0x2D, 1),
-+	COUNTRY_CHPLAN_ENT("CN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("CO", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("CR", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("CY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DO", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("DZ", 0x00, 1),
-+	COUNTRY_CHPLAN_ENT("EC", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("EE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("EG", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("ES", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GT", 0x61, 1),
-+	COUNTRY_CHPLAN_ENT("HK", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("HN", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("HR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ID", 0x5D, 1),
-+	COUNTRY_CHPLAN_ENT("IE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IL", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("IN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("IS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("JM", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("JO", 0x49, 1),
-+	COUNTRY_CHPLAN_ENT("JP", 0x27, 1),
-+	COUNTRY_CHPLAN_ENT("KE", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("KG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1),
-+	COUNTRY_CHPLAN_ENT("KW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MA", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("MC", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ME", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MX", 0x34, 1),
-+	COUNTRY_CHPLAN_ENT("MY", 0x63, 1),
-+	COUNTRY_CHPLAN_ENT("MZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NG", 0x75, 1),
-+	COUNTRY_CHPLAN_ENT("NI", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("NL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NZ", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("OM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PA", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("PE", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("PG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PK", 0x51, 1),
-+	COUNTRY_CHPLAN_ENT("PL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PR", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("PT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PY", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("QA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("RO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RU", 0x59, 1),
-+	COUNTRY_CHPLAN_ENT("SA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SN", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SV", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("TH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("TN", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("TR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TT", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("TW", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("UA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("US", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("UY", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("VE", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("VN", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("ZA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("ZW", 0x26, 1),
-+};
-+#endif
-+
-+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8822BE) /* 2016 certify */
-+static const struct country_chplan RTL8822BE_country_chplan_map[] = {
-+	COUNTRY_CHPLAN_ENT("AE", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("AL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AN", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("AO", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("AR", 0x61, 1),
-+	COUNTRY_CHPLAN_ENT("AT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AU", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("AZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BB", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("BD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BH", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("BI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BJ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BM", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("BN", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("BO", 0x73, 1),
-+	COUNTRY_CHPLAN_ENT("BR", 0x62, 1),
-+	COUNTRY_CHPLAN_ENT("BS", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("BW", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("BY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CA", 0x2B, 1),
-+	COUNTRY_CHPLAN_ENT("CD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CI", 0x42, 1),
-+	COUNTRY_CHPLAN_ENT("CL", 0x2D, 1),
-+	COUNTRY_CHPLAN_ENT("CM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("CO", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("CR", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("CV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DJ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DO", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("DZ", 0x00, 1),
-+	COUNTRY_CHPLAN_ENT("EC", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("EE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("EG", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("EH", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("ES", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FJ", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("FR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GN", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GP", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GQ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GT", 0x61, 1),
-+	COUNTRY_CHPLAN_ENT("GU", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("GW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HK", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("HN", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("HR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HT", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("HU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ID", 0x3D, 0),
-+	COUNTRY_CHPLAN_ENT("IE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IL", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("IN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("IS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("JM", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("JO", 0x49, 1),
-+	COUNTRY_CHPLAN_ENT("JP", 0x27, 1),
-+	COUNTRY_CHPLAN_ENT("KE", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("KG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1),
-+	COUNTRY_CHPLAN_ENT("KW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MA", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("MC", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ME", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ML", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MO", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("MQ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MX", 0x4D, 1),
-+	COUNTRY_CHPLAN_ENT("MY", 0x63, 1),
-+	COUNTRY_CHPLAN_ENT("MZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NG", 0x75, 1),
-+	COUNTRY_CHPLAN_ENT("NI", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("NL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NP", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("NZ", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("OM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PA", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("PE", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("PG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PK", 0x51, 1),
-+	COUNTRY_CHPLAN_ENT("PL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PR", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("PT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PY", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("QA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("RO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RU", 0x59, 1),
-+	COUNTRY_CHPLAN_ENT("SA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SC", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("SE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SN", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ST", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("SV", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("TD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("TJ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TN", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("TR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TT", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("TW", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("TZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("UA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("UG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("US", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("UY", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("UZ", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("VE", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("VN", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("YT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ZA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("ZM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ZW", 0x26, 1),
-+};
-+#endif
-+
-+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821CE) /* 2016 certify */
-+static const struct country_chplan RTL8821CE_country_chplan_map[] = {
-+	COUNTRY_CHPLAN_ENT("AE", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("AL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AN", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("AO", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("AR", 0x61, 1),
-+	COUNTRY_CHPLAN_ENT("AT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AU", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("AZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BB", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("BD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BH", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("BI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BJ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BM", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("BN", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("BO", 0x73, 1),
-+	COUNTRY_CHPLAN_ENT("BR", 0x62, 1),
-+	COUNTRY_CHPLAN_ENT("BS", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("BW", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("BY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CA", 0x2B, 1),
-+	COUNTRY_CHPLAN_ENT("CD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CI", 0x42, 1),
-+	COUNTRY_CHPLAN_ENT("CL", 0x2D, 1),
-+	COUNTRY_CHPLAN_ENT("CM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("CO", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("CR", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("CV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DJ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DO", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("DZ", 0x00, 1),
-+	COUNTRY_CHPLAN_ENT("EC", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("EE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("EG", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("EH", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("ES", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ET", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FJ", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("FR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GN", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GP", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GQ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GT", 0x61, 1),
-+	COUNTRY_CHPLAN_ENT("GU", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("GW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HK", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("HN", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("HR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HT", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("HU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ID", 0x3D, 0),
-+	COUNTRY_CHPLAN_ENT("IE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IL", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("IN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("IS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("JM", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("JO", 0x49, 1),
-+	COUNTRY_CHPLAN_ENT("JP", 0x27, 1),
-+	COUNTRY_CHPLAN_ENT("KE", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("KG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KR", 0x28, 1),
-+	COUNTRY_CHPLAN_ENT("KW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MA", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("MC", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ME", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ML", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MO", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("MQ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MX", 0x4D, 1),
-+	COUNTRY_CHPLAN_ENT("MY", 0x63, 1),
-+	COUNTRY_CHPLAN_ENT("MZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NG", 0x75, 1),
-+	COUNTRY_CHPLAN_ENT("NI", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("NL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NP", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("NZ", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("OM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PA", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("PE", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("PG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PK", 0x51, 1),
-+	COUNTRY_CHPLAN_ENT("PL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PR", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("PT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PY", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("QA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("RO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RU", 0x59, 1),
-+	COUNTRY_CHPLAN_ENT("SA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SC", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("SE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SN", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ST", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("SV", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("TD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("TJ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TN", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("TR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TW", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("TZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("UA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("UG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("US", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("UY", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("UZ", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("VE", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("VN", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("YT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ZA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("ZM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ZW", 0x26, 1),
-+};
-+#endif
-+
-+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8822CE) /* 2018 certify */
-+static const struct country_chplan RTL8822CE_country_chplan_map[] = {
-+	COUNTRY_CHPLAN_ENT("AE", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("AL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AN", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("AO", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("AR", 0x61, 1),
-+	COUNTRY_CHPLAN_ENT("AT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("AU", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("AW", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("AZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BB", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("BD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BH", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("BI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BJ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("BM", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("BN", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("BO", 0x73, 1),
-+	COUNTRY_CHPLAN_ENT("BR", 0x62, 1),
-+	COUNTRY_CHPLAN_ENT("BS", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("BW", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("BY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CA", 0x2B, 1),
-+	COUNTRY_CHPLAN_ENT("CD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CI", 0x42, 1),
-+	COUNTRY_CHPLAN_ENT("CL", 0x2D, 1),
-+	COUNTRY_CHPLAN_ENT("CM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("CO", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("CR", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("CV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CY", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("CZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DJ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("DO", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("DZ", 0x00, 1),
-+	COUNTRY_CHPLAN_ENT("EC", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("EE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("EG", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("EH", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("ES", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ET", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("FJ", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("FR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GN", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GP", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GQ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("GT", 0x61, 1),
-+	COUNTRY_CHPLAN_ENT("GU", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("GW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HK", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("HN", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("HR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("HT", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("HU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IL", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("IN", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("IS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("IT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("JM", 0x32, 1),
-+	COUNTRY_CHPLAN_ENT("JO", 0x49, 1),
-+	COUNTRY_CHPLAN_ENT("JP", 0x27, 1),
-+	COUNTRY_CHPLAN_ENT("KE", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("KG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KH", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KR", 0x4B, 1),
-+	COUNTRY_CHPLAN_ENT("KW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("KZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LB", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("LV", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MA", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("MC", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ME", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ML", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MO", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("MQ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MU", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MW", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("MX", 0x4D, 1),
-+	COUNTRY_CHPLAN_ENT("MY", 0x63, 1),
-+	COUNTRY_CHPLAN_ENT("MZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NA", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NG", 0x75, 1),
-+	COUNTRY_CHPLAN_ENT("NI", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("NL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("NP", 0x48, 1),
-+	COUNTRY_CHPLAN_ENT("NZ", 0x45, 1),
-+	COUNTRY_CHPLAN_ENT("OM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PA", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("PE", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("PG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("PK", 0x51, 1),
-+	COUNTRY_CHPLAN_ENT("PL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PR", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("PT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("PY", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("QA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("RO", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RS", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("RU", 0x59, 1),
-+	COUNTRY_CHPLAN_ENT("SA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SC", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("SE", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SG", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("SI", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SK", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SL", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("SN", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ST", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("SV", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("SZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TD", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TF", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TH", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("TJ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TN", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("TR", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("TW", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("TZ", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("UA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("UG", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("US", 0x76, 1),
-+	COUNTRY_CHPLAN_ENT("UY", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("UZ", 0x47, 1),
-+	COUNTRY_CHPLAN_ENT("VE", 0x30, 1),
-+	COUNTRY_CHPLAN_ENT("VN", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("YT", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ZA", 0x35, 1),
-+	COUNTRY_CHPLAN_ENT("ZM", 0x26, 1),
-+	COUNTRY_CHPLAN_ENT("ZW", 0x26, 1),
-+};
-+#endif
-+
-+/**
-+ * rtw_def_module_country_chplan_map -
-+ * @hal_map: returned map
-+ * @return: size of map
-+ */
-+static u16 rtw_def_module_country_chplan_map(const struct country_chplan **hal_map)
-+{
-+	u16 hal_map_sz = 0;
-+
-+	/* TODO: runtime selection for multi driver */
-+#if (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AE_HMC_M2)
-+	*hal_map = RTL8821AE_HMC_M2_country_chplan_map;
-+	hal_map_sz = sizeof(RTL8821AE_HMC_M2_country_chplan_map) / sizeof(struct country_chplan);
-+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AU)
-+	*hal_map = RTL8821AU_country_chplan_map;
-+	hal_map_sz = sizeof(RTL8821AU_country_chplan_map) / sizeof(struct country_chplan);
-+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AENF_NGFF)
-+	*hal_map = RTL8812AENF_NGFF_country_chplan_map;
-+	hal_map_sz = sizeof(RTL8812AENF_NGFF_country_chplan_map) / sizeof(struct country_chplan);
-+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AEBT_HMC)
-+	*hal_map = RTL8812AEBT_HMC_country_chplan_map;
-+	hal_map_sz = sizeof(RTL8812AEBT_HMC_country_chplan_map) / sizeof(struct country_chplan);
-+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8188EE_HMC_M2)
-+	*hal_map = RTL8188EE_HMC_M2_country_chplan_map;
-+	hal_map_sz = sizeof(RTL8188EE_HMC_M2_country_chplan_map) / sizeof(struct country_chplan);
-+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BE_HMC_M2)
-+	*hal_map = RTL8723BE_HMC_M2_country_chplan_map;
-+	hal_map_sz = sizeof(RTL8723BE_HMC_M2_country_chplan_map) / sizeof(struct country_chplan);
-+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BS_NGFF1216)
-+	*hal_map = RTL8723BS_NGFF1216_country_chplan_map;
-+	hal_map_sz = sizeof(RTL8723BS_NGFF1216_country_chplan_map) / sizeof(struct country_chplan);
-+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8192EEBT_HMC_M2)
-+	*hal_map = RTL8192EEBT_HMC_M2_country_chplan_map;
-+	hal_map_sz = sizeof(RTL8192EEBT_HMC_M2_country_chplan_map) / sizeof(struct country_chplan);
-+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723DE_NGFF1630)
-+	*hal_map = RTL8723DE_NGFF1630_country_chplan_map;
-+	hal_map_sz = sizeof(RTL8723DE_NGFF1630_country_chplan_map) / sizeof(struct country_chplan);
-+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8822BE)
-+	*hal_map = RTL8822BE_country_chplan_map;
-+	hal_map_sz = sizeof(RTL8822BE_country_chplan_map) / sizeof(struct country_chplan);
-+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821CE)
-+	*hal_map = RTL8821CE_country_chplan_map;
-+	hal_map_sz = sizeof(RTL8821CE_country_chplan_map) / sizeof(struct country_chplan);
-+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8822CE)
-+	*hal_map = RTL8822CE_country_chplan_map;
-+	hal_map_sz = sizeof(RTL8822CE_country_chplan_map) / sizeof(struct country_chplan);
-+#endif
-+
-+	return hal_map_sz;
-+}
-+#else
-+
-+static const struct country_chplan country_chplan_map[] = {
-+	COUNTRY_CHPLAN_ENT("AD", 0x26, 1), /* Andorra */
-+	COUNTRY_CHPLAN_ENT("AE", 0x35, 1), /* United Arab Emirates */
-+	COUNTRY_CHPLAN_ENT("AF", 0x42, 1), /* Afghanistan */
-+	COUNTRY_CHPLAN_ENT("AG", 0x76, 1), /* Antigua & Barbuda */
-+	COUNTRY_CHPLAN_ENT("AI", 0x26, 1), /* Anguilla(UK) */
-+	COUNTRY_CHPLAN_ENT("AL", 0x26, 1), /* Albania */
-+	COUNTRY_CHPLAN_ENT("AM", 0x26, 1), /* Armenia */
-+	COUNTRY_CHPLAN_ENT("AN", 0x76, 1), /* Netherlands Antilles */
-+	COUNTRY_CHPLAN_ENT("AO", 0x47, 1), /* Angola */
-+	COUNTRY_CHPLAN_ENT("AQ", 0x26, 1), /* Antarctica */
-+	COUNTRY_CHPLAN_ENT("AR", 0x61, 1), /* Argentina */
-+	COUNTRY_CHPLAN_ENT("AS", 0x76, 1), /* American Samoa */
-+	COUNTRY_CHPLAN_ENT("AT", 0x26, 1), /* Austria */
-+	COUNTRY_CHPLAN_ENT("AU", 0x45, 1), /* Australia */
-+	COUNTRY_CHPLAN_ENT("AW", 0x76, 1), /* Aruba */
-+	COUNTRY_CHPLAN_ENT("AZ", 0x26, 1), /* Azerbaijan */
-+	COUNTRY_CHPLAN_ENT("BA", 0x26, 1), /* Bosnia & Herzegovina */
-+	COUNTRY_CHPLAN_ENT("BB", 0x76, 1), /* Barbados */
-+	COUNTRY_CHPLAN_ENT("BD", 0x26, 1), /* Bangladesh */
-+	COUNTRY_CHPLAN_ENT("BE", 0x26, 1), /* Belgium */
-+	COUNTRY_CHPLAN_ENT("BF", 0x26, 1), /* Burkina Faso */
-+	COUNTRY_CHPLAN_ENT("BG", 0x26, 1), /* Bulgaria */
-+	COUNTRY_CHPLAN_ENT("BH", 0x48, 1), /* Bahrain */
-+	COUNTRY_CHPLAN_ENT("BI", 0x26, 1), /* Burundi */
-+	COUNTRY_CHPLAN_ENT("BJ", 0x26, 1), /* Benin */
-+	COUNTRY_CHPLAN_ENT("BM", 0x76, 1), /* Bermuda (UK) */
-+	COUNTRY_CHPLAN_ENT("BN", 0x47, 1), /* Brunei */
-+	COUNTRY_CHPLAN_ENT("BO", 0x73, 1), /* Bolivia */
-+	COUNTRY_CHPLAN_ENT("BR", 0x62, 1), /* Brazil */
-+	COUNTRY_CHPLAN_ENT("BS", 0x76, 1), /* Bahamas */
-+	COUNTRY_CHPLAN_ENT("BT", 0x26, 1), /* Bhutan */
-+	COUNTRY_CHPLAN_ENT("BV", 0x26, 1), /* Bouvet Island (Norway) */
-+	COUNTRY_CHPLAN_ENT("BW", 0x35, 1), /* Botswana */
-+	COUNTRY_CHPLAN_ENT("BY", 0x26, 1), /* Belarus */
-+	COUNTRY_CHPLAN_ENT("BZ", 0x76, 1), /* Belize */
-+	COUNTRY_CHPLAN_ENT("CA", 0x2B, 1), /* Canada */
-+	COUNTRY_CHPLAN_ENT("CC", 0x26, 1), /* Cocos (Keeling) Islands (Australia) */
-+	COUNTRY_CHPLAN_ENT("CD", 0x26, 1), /* Congo, Republic of the */
-+	COUNTRY_CHPLAN_ENT("CF", 0x26, 1), /* Central African Republic */
-+	COUNTRY_CHPLAN_ENT("CG", 0x26, 1), /* Congo, Democratic Republic of the. Zaire */
-+	COUNTRY_CHPLAN_ENT("CH", 0x26, 1), /* Switzerland */
-+	COUNTRY_CHPLAN_ENT("CI", 0x42, 1), /* Cote d'Ivoire */
-+	COUNTRY_CHPLAN_ENT("CK", 0x26, 1), /* Cook Islands */
-+	COUNTRY_CHPLAN_ENT("CL", 0x2D, 1), /* Chile */
-+	COUNTRY_CHPLAN_ENT("CM", 0x26, 1), /* Cameroon */
-+	COUNTRY_CHPLAN_ENT("CN", 0x48, 1), /* China */
-+	COUNTRY_CHPLAN_ENT("CO", 0x76, 1), /* Colombia */
-+	COUNTRY_CHPLAN_ENT("CR", 0x76, 1), /* Costa Rica */
-+	COUNTRY_CHPLAN_ENT("CV", 0x26, 1), /* Cape Verde */
-+	COUNTRY_CHPLAN_ENT("CX", 0x45, 1), /* Christmas Island (Australia) */
-+	COUNTRY_CHPLAN_ENT("CY", 0x26, 1), /* Cyprus */
-+	COUNTRY_CHPLAN_ENT("CZ", 0x26, 1), /* Czech Republic */
-+	COUNTRY_CHPLAN_ENT("DE", 0x26, 1), /* Germany */
-+	COUNTRY_CHPLAN_ENT("DJ", 0x26, 1), /* Djibouti */
-+	COUNTRY_CHPLAN_ENT("DK", 0x26, 1), /* Denmark */
-+	COUNTRY_CHPLAN_ENT("DM", 0x76, 1), /* Dominica */
-+	COUNTRY_CHPLAN_ENT("DO", 0x76, 1), /* Dominican Republic */
-+	COUNTRY_CHPLAN_ENT("DZ", 0x00, 1), /* Algeria */
-+	COUNTRY_CHPLAN_ENT("EC", 0x76, 1), /* Ecuador */
-+	COUNTRY_CHPLAN_ENT("EE", 0x26, 1), /* Estonia */
-+	COUNTRY_CHPLAN_ENT("EG", 0x47, 1), /* Egypt */
-+	COUNTRY_CHPLAN_ENT("EH", 0x47, 1), /* Western Sahara */
-+	COUNTRY_CHPLAN_ENT("ER", 0x26, 1), /* Eritrea */
-+	COUNTRY_CHPLAN_ENT("ES", 0x26, 1), /* Spain, Canary Islands, Ceuta, Melilla */
-+	COUNTRY_CHPLAN_ENT("ET", 0x26, 1), /* Ethiopia */
-+	COUNTRY_CHPLAN_ENT("FI", 0x26, 1), /* Finland */
-+	COUNTRY_CHPLAN_ENT("FJ", 0x76, 1), /* Fiji */
-+	COUNTRY_CHPLAN_ENT("FK", 0x26, 1), /* Falkland Islands (Islas Malvinas) (UK) */
-+	COUNTRY_CHPLAN_ENT("FM", 0x76, 1), /* Micronesia, Federated States of (USA) */
-+	COUNTRY_CHPLAN_ENT("FO", 0x26, 1), /* Faroe Islands (Denmark) */
-+	COUNTRY_CHPLAN_ENT("FR", 0x26, 1), /* France */
-+	COUNTRY_CHPLAN_ENT("GA", 0x26, 1), /* Gabon */
-+	COUNTRY_CHPLAN_ENT("GB", 0x26, 1), /* Great Britain (United Kingdom; England) */
-+	COUNTRY_CHPLAN_ENT("GD", 0x76, 1), /* Grenada */
-+	COUNTRY_CHPLAN_ENT("GE", 0x26, 1), /* Georgia */
-+	COUNTRY_CHPLAN_ENT("GF", 0x26, 1), /* French Guiana */
-+	COUNTRY_CHPLAN_ENT("GG", 0x26, 1), /* Guernsey (UK) */
-+	COUNTRY_CHPLAN_ENT("GH", 0x26, 1), /* Ghana */
-+	COUNTRY_CHPLAN_ENT("GI", 0x26, 1), /* Gibraltar (UK) */
-+	COUNTRY_CHPLAN_ENT("GL", 0x26, 1), /* Greenland (Denmark) */
-+	COUNTRY_CHPLAN_ENT("GM", 0x26, 1), /* Gambia */
-+	COUNTRY_CHPLAN_ENT("GN", 0x26, 1), /* Guinea */
-+	COUNTRY_CHPLAN_ENT("GP", 0x26, 1), /* Guadeloupe (France) */
-+	COUNTRY_CHPLAN_ENT("GQ", 0x26, 1), /* Equatorial Guinea */
-+	COUNTRY_CHPLAN_ENT("GR", 0x26, 1), /* Greece */
-+	COUNTRY_CHPLAN_ENT("GS", 0x26, 1), /* South Georgia and the Sandwich Islands (UK) */
-+	COUNTRY_CHPLAN_ENT("GT", 0x61, 1), /* Guatemala */
-+	COUNTRY_CHPLAN_ENT("GU", 0x76, 1), /* Guam (USA) */
-+	COUNTRY_CHPLAN_ENT("GW", 0x26, 1), /* Guinea-Bissau */
-+	COUNTRY_CHPLAN_ENT("GY", 0x44, 1), /* Guyana */
-+	COUNTRY_CHPLAN_ENT("HK", 0x35, 1), /* Hong Kong */
-+	COUNTRY_CHPLAN_ENT("HM", 0x45, 1), /* Heard and McDonald Islands (Australia) */
-+	COUNTRY_CHPLAN_ENT("HN", 0x32, 1), /* Honduras */
-+	COUNTRY_CHPLAN_ENT("HR", 0x26, 1), /* Croatia */
-+	COUNTRY_CHPLAN_ENT("HT", 0x76, 1), /* Haiti */
-+	COUNTRY_CHPLAN_ENT("HU", 0x26, 1), /* Hungary */
-+	COUNTRY_CHPLAN_ENT("ID", 0x5D, 1), /* Indonesia */
-+	COUNTRY_CHPLAN_ENT("IE", 0x26, 1), /* Ireland */
-+	COUNTRY_CHPLAN_ENT("IL", 0x47, 1), /* Israel */
-+	COUNTRY_CHPLAN_ENT("IM", 0x26, 1), /* Isle of Man (UK) */
-+	COUNTRY_CHPLAN_ENT("IN", 0x48, 1), /* India */
-+	COUNTRY_CHPLAN_ENT("IO", 0x26, 1), /* British Indian Ocean Territory (UK) */
-+	COUNTRY_CHPLAN_ENT("IQ", 0x26, 1), /* Iraq */
-+	COUNTRY_CHPLAN_ENT("IR", 0x26, 0), /* Iran */
-+	COUNTRY_CHPLAN_ENT("IS", 0x26, 1), /* Iceland */
-+	COUNTRY_CHPLAN_ENT("IT", 0x26, 1), /* Italy */
-+	COUNTRY_CHPLAN_ENT("JE", 0x26, 1), /* Jersey (UK) */
-+	COUNTRY_CHPLAN_ENT("JM", 0x32, 1), /* Jamaica */
-+	COUNTRY_CHPLAN_ENT("JO", 0x49, 1), /* Jordan */
-+	COUNTRY_CHPLAN_ENT("JP", 0x27, 1), /* Japan- Telec */
-+	COUNTRY_CHPLAN_ENT("KE", 0x47, 1), /* Kenya */
-+	COUNTRY_CHPLAN_ENT("KG", 0x26, 1), /* Kyrgyzstan */
-+	COUNTRY_CHPLAN_ENT("KH", 0x26, 1), /* Cambodia */
-+	COUNTRY_CHPLAN_ENT("KI", 0x26, 1), /* Kiribati */
-+	COUNTRY_CHPLAN_ENT("KM", 0x26, 1), /* Comoros */
-+	COUNTRY_CHPLAN_ENT("KN", 0x76, 1), /* Saint Kitts and Nevis */
-+	COUNTRY_CHPLAN_ENT("KR", 0x4B, 1), /* South Korea */
-+	COUNTRY_CHPLAN_ENT("KW", 0x26, 1), /* Kuwait */
-+	COUNTRY_CHPLAN_ENT("KY", 0x76, 1), /* Cayman Islands (UK) */
-+	COUNTRY_CHPLAN_ENT("KZ", 0x26, 1), /* Kazakhstan */
-+	COUNTRY_CHPLAN_ENT("LA", 0x26, 1), /* Laos */
-+	COUNTRY_CHPLAN_ENT("LB", 0x26, 1), /* Lebanon */
-+	COUNTRY_CHPLAN_ENT("LC", 0x76, 1), /* Saint Lucia */
-+	COUNTRY_CHPLAN_ENT("LI", 0x26, 1), /* Liechtenstein */
-+	COUNTRY_CHPLAN_ENT("LK", 0x26, 1), /* Sri Lanka */
-+	COUNTRY_CHPLAN_ENT("LR", 0x26, 1), /* Liberia */
-+	COUNTRY_CHPLAN_ENT("LS", 0x26, 1), /* Lesotho */
-+	COUNTRY_CHPLAN_ENT("LT", 0x26, 1), /* Lithuania */
-+	COUNTRY_CHPLAN_ENT("LU", 0x26, 1), /* Luxembourg */
-+	COUNTRY_CHPLAN_ENT("LV", 0x26, 1), /* Latvia */
-+	COUNTRY_CHPLAN_ENT("LY", 0x26, 1), /* Libya */
-+	COUNTRY_CHPLAN_ENT("MA", 0x47, 1), /* Morocco */
-+	COUNTRY_CHPLAN_ENT("MC", 0x26, 1), /* Monaco */
-+	COUNTRY_CHPLAN_ENT("MD", 0x26, 1), /* Moldova */
-+	COUNTRY_CHPLAN_ENT("ME", 0x26, 1), /* Montenegro */
-+	COUNTRY_CHPLAN_ENT("MF", 0x76, 1), /* Saint Martin */
-+	COUNTRY_CHPLAN_ENT("MG", 0x26, 1), /* Madagascar */
-+	COUNTRY_CHPLAN_ENT("MH", 0x76, 1), /* Marshall Islands (USA) */
-+	COUNTRY_CHPLAN_ENT("MK", 0x26, 1), /* Republic of Macedonia (FYROM) */
-+	COUNTRY_CHPLAN_ENT("ML", 0x26, 1), /* Mali */
-+	COUNTRY_CHPLAN_ENT("MM", 0x26, 1), /* Burma (Myanmar) */
-+	COUNTRY_CHPLAN_ENT("MN", 0x26, 1), /* Mongolia */
-+	COUNTRY_CHPLAN_ENT("MO", 0x35, 1), /* Macau */
-+	COUNTRY_CHPLAN_ENT("MP", 0x76, 1), /* Northern Mariana Islands (USA) */
-+	COUNTRY_CHPLAN_ENT("MQ", 0x26, 1), /* Martinique (France) */
-+	COUNTRY_CHPLAN_ENT("MR", 0x26, 1), /* Mauritania */
-+	COUNTRY_CHPLAN_ENT("MS", 0x26, 1), /* Montserrat (UK) */
-+	COUNTRY_CHPLAN_ENT("MT", 0x26, 1), /* Malta */
-+	COUNTRY_CHPLAN_ENT("MU", 0x26, 1), /* Mauritius */
-+	COUNTRY_CHPLAN_ENT("MV", 0x47, 1), /* Maldives */
-+	COUNTRY_CHPLAN_ENT("MW", 0x26, 1), /* Malawi */
-+	COUNTRY_CHPLAN_ENT("MX", 0x4D, 1), /* Mexico */
-+	COUNTRY_CHPLAN_ENT("MY", 0x63, 1), /* Malaysia */
-+	COUNTRY_CHPLAN_ENT("MZ", 0x26, 1), /* Mozambique */
-+	COUNTRY_CHPLAN_ENT("NA", 0x26, 1), /* Namibia */
-+	COUNTRY_CHPLAN_ENT("NC", 0x26, 1), /* New Caledonia */
-+	COUNTRY_CHPLAN_ENT("NE", 0x26, 1), /* Niger */
-+	COUNTRY_CHPLAN_ENT("NF", 0x45, 1), /* Norfolk Island (Australia) */
-+	COUNTRY_CHPLAN_ENT("NG", 0x75, 1), /* Nigeria */
-+	COUNTRY_CHPLAN_ENT("NI", 0x76, 1), /* Nicaragua */
-+	COUNTRY_CHPLAN_ENT("NL", 0x26, 1), /* Netherlands */
-+	COUNTRY_CHPLAN_ENT("NO", 0x26, 1), /* Norway */
-+	COUNTRY_CHPLAN_ENT("NP", 0x48, 1), /* Nepal */
-+	COUNTRY_CHPLAN_ENT("NR", 0x26, 1), /* Nauru */
-+	COUNTRY_CHPLAN_ENT("NU", 0x45, 1), /* Niue */
-+	COUNTRY_CHPLAN_ENT("NZ", 0x45, 1), /* New Zealand */
-+	COUNTRY_CHPLAN_ENT("OM", 0x26, 1), /* Oman */
-+	COUNTRY_CHPLAN_ENT("PA", 0x76, 1), /* Panama */
-+	COUNTRY_CHPLAN_ENT("PE", 0x76, 1), /* Peru */
-+	COUNTRY_CHPLAN_ENT("PF", 0x26, 1), /* French Polynesia (France) */
-+	COUNTRY_CHPLAN_ENT("PG", 0x35, 1), /* Papua New Guinea */
-+	COUNTRY_CHPLAN_ENT("PH", 0x35, 1), /* Philippines */
-+	COUNTRY_CHPLAN_ENT("PK", 0x51, 1), /* Pakistan */
-+	COUNTRY_CHPLAN_ENT("PL", 0x26, 1), /* Poland */
-+	COUNTRY_CHPLAN_ENT("PM", 0x26, 1), /* Saint Pierre and Miquelon (France) */
-+	COUNTRY_CHPLAN_ENT("PR", 0x76, 1), /* Puerto Rico */
-+	COUNTRY_CHPLAN_ENT("PT", 0x26, 1), /* Portugal */
-+	COUNTRY_CHPLAN_ENT("PW", 0x76, 1), /* Palau */
-+	COUNTRY_CHPLAN_ENT("PY", 0x76, 1), /* Paraguay */
-+	COUNTRY_CHPLAN_ENT("QA", 0x35, 1), /* Qatar */
-+	COUNTRY_CHPLAN_ENT("RE", 0x26, 1), /* Reunion (France) */
-+	COUNTRY_CHPLAN_ENT("RO", 0x26, 1), /* Romania */
-+	COUNTRY_CHPLAN_ENT("RS", 0x26, 1), /* Serbia, Kosovo */
-+	COUNTRY_CHPLAN_ENT("RU", 0x59, 1), /* Russia(fac/gost), Kaliningrad */
-+	COUNTRY_CHPLAN_ENT("RW", 0x26, 1), /* Rwanda */
-+	COUNTRY_CHPLAN_ENT("SA", 0x35, 1), /* Saudi Arabia */
-+	COUNTRY_CHPLAN_ENT("SB", 0x26, 1), /* Solomon Islands */
-+	COUNTRY_CHPLAN_ENT("SC", 0x76, 1), /* Seychelles */
-+	COUNTRY_CHPLAN_ENT("SE", 0x26, 1), /* Sweden */
-+	COUNTRY_CHPLAN_ENT("SG", 0x35, 1), /* Singapore */
-+	COUNTRY_CHPLAN_ENT("SH", 0x26, 1), /* Saint Helena (UK) */
-+	COUNTRY_CHPLAN_ENT("SI", 0x26, 1), /* Slovenia */
-+	COUNTRY_CHPLAN_ENT("SJ", 0x26, 1), /* Svalbard (Norway) */
-+	COUNTRY_CHPLAN_ENT("SK", 0x26, 1), /* Slovakia */
-+	COUNTRY_CHPLAN_ENT("SL", 0x26, 1), /* Sierra Leone */
-+	COUNTRY_CHPLAN_ENT("SM", 0x26, 1), /* San Marino */
-+	COUNTRY_CHPLAN_ENT("SN", 0x26, 1), /* Senegal */
-+	COUNTRY_CHPLAN_ENT("SO", 0x26, 1), /* Somalia */
-+	COUNTRY_CHPLAN_ENT("SR", 0x74, 1), /* Suriname */
-+	COUNTRY_CHPLAN_ENT("ST", 0x76, 1), /* Sao Tome and Principe */
-+	COUNTRY_CHPLAN_ENT("SV", 0x30, 1), /* El Salvador */
-+	COUNTRY_CHPLAN_ENT("SX", 0x76, 1), /* Sint Marteen */
-+	COUNTRY_CHPLAN_ENT("SZ", 0x26, 1), /* Swaziland */
-+	COUNTRY_CHPLAN_ENT("TC", 0x26, 1), /* Turks and Caicos Islands (UK) */
-+	COUNTRY_CHPLAN_ENT("TD", 0x26, 1), /* Chad */
-+	COUNTRY_CHPLAN_ENT("TF", 0x26, 1), /* French Southern and Antarctic Lands (FR Southern Territories) */
-+	COUNTRY_CHPLAN_ENT("TG", 0x26, 1), /* Togo */
-+	COUNTRY_CHPLAN_ENT("TH", 0x35, 1), /* Thailand */
-+	COUNTRY_CHPLAN_ENT("TJ", 0x26, 1), /* Tajikistan */
-+	COUNTRY_CHPLAN_ENT("TK", 0x45, 1), /* Tokelau */
-+	COUNTRY_CHPLAN_ENT("TM", 0x26, 1), /* Turkmenistan */
-+	COUNTRY_CHPLAN_ENT("TN", 0x47, 1), /* Tunisia */
-+	COUNTRY_CHPLAN_ENT("TO", 0x26, 1), /* Tonga */
-+	COUNTRY_CHPLAN_ENT("TR", 0x26, 1), /* Turkey, Northern Cyprus */
-+	COUNTRY_CHPLAN_ENT("TT", 0x76, 1), /* Trinidad & Tobago */
-+	COUNTRY_CHPLAN_ENT("TV", 0x21, 0), /* Tuvalu */
-+	COUNTRY_CHPLAN_ENT("TW", 0x76, 1), /* Taiwan */
-+	COUNTRY_CHPLAN_ENT("TZ", 0x26, 1), /* Tanzania */
-+	COUNTRY_CHPLAN_ENT("UA", 0x35, 1), /* Ukraine */
-+	COUNTRY_CHPLAN_ENT("UG", 0x26, 1), /* Uganda */
-+	COUNTRY_CHPLAN_ENT("US", 0x76, 1), /* United States of America (USA) */
-+	COUNTRY_CHPLAN_ENT("UY", 0x30, 1), /* Uruguay */
-+	COUNTRY_CHPLAN_ENT("UZ", 0x47, 1), /* Uzbekistan */
-+	COUNTRY_CHPLAN_ENT("VA", 0x26, 1), /* Holy See (Vatican City) */
-+	COUNTRY_CHPLAN_ENT("VC", 0x76, 1), /* Saint Vincent and the Grenadines */
-+	COUNTRY_CHPLAN_ENT("VE", 0x30, 1), /* Venezuela */
-+	COUNTRY_CHPLAN_ENT("VG", 0x76, 1), /* British Virgin Islands (UK) */
-+	COUNTRY_CHPLAN_ENT("VI", 0x76, 1), /* United States Virgin Islands (USA) */
-+	COUNTRY_CHPLAN_ENT("VN", 0x35, 1), /* Vietnam */
-+	COUNTRY_CHPLAN_ENT("VU", 0x26, 1), /* Vanuatu */
-+	COUNTRY_CHPLAN_ENT("WF", 0x26, 1), /* Wallis and Futuna (France) */
-+	COUNTRY_CHPLAN_ENT("WS", 0x76, 1), /* Samoa */
-+	COUNTRY_CHPLAN_ENT("YE", 0x26, 1), /* Yemen */
-+	COUNTRY_CHPLAN_ENT("YT", 0x26, 1), /* Mayotte (France) */
-+	COUNTRY_CHPLAN_ENT("ZA", 0x35, 1), /* South Africa */
-+	COUNTRY_CHPLAN_ENT("ZM", 0x26, 1), /* Zambia */
-+	COUNTRY_CHPLAN_ENT("ZW", 0x26, 1), /* Zimbabwe */
-+};
-+#endif /* CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP or RTW_DEF_MODULE_REGULATORY_CERT or newest */
-+
-+/*
-+* rtw_get_chplan_from_country -
-+* @country_code: string of country code
-+*
-+* Return pointer of struct country_chplan entry or NULL when unsupported country_code is given
-+*/
-+const struct country_chplan *rtw_get_chplan_from_country(const char *country_code)
-+{
-+	const struct country_chplan *ent = NULL;
-+	const struct country_chplan *map = NULL;
-+	u16 map_sz = 0;
-+	char code[2];
-+	int i;
-+
-+	code[0] = alpha_to_upper(country_code[0]);
-+	code[1] = alpha_to_upper(country_code[1]);
-+
-+#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP
-+	map = CUSTOMIZED_country_chplan_map;
-+	map_sz = sizeof(CUSTOMIZED_country_chplan_map) / sizeof(struct country_chplan);
-+#elif RTW_DEF_MODULE_REGULATORY_CERT
-+	map_sz = rtw_def_module_country_chplan_map(&map);
-+#else
-+	map = country_chplan_map;
-+	map_sz = sizeof(country_chplan_map) / sizeof(struct country_chplan);
-+#endif
-+
-+	for (i = 0; i < map_sz; i++) {
-+		if (strncmp(code, map[i].alpha2, 2) == 0) {
-+			ent = &map[i];
-+			break;
-+		}
-+	}
-+
-+	return ent;
-+}
-+
-+void dump_country_chplan(void *sel, const struct country_chplan *ent)
-+{
-+	char buf[16];
-+
-+	if (ent->chplan == RTW_CHPLAN_UNSPECIFIED)
-+		sprintf(buf, "NA");
-+	else
-+		sprintf(buf, "0x%02X", ent->chplan);
-+
-+	RTW_PRINT_SEL(sel, "\"%c%c\", %s%s\n"
-+		, ent->alpha2[0], ent->alpha2[1], buf
-+		, COUNTRY_CHPLAN_EN_11AC(ent) ? " ac" : ""
-+	);
-+}
-+
-+void dump_country_chplan_map(void *sel)
-+{
-+	const struct country_chplan *ent;
-+	u8 code[2];
-+
-+#if RTW_DEF_MODULE_REGULATORY_CERT
-+	RTW_PRINT_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT:0x%x\n", RTW_DEF_MODULE_REGULATORY_CERT);
-+#endif
-+#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP
-+	RTW_PRINT_SEL(sel, "CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\n");
-+#endif
-+
-+	for (code[0] = 'A'; code[0] <= 'Z'; code[0]++) {
-+		for (code[1] = 'A'; code[1] <= 'Z'; code[1]++) {
-+			ent = rtw_get_chplan_from_country(code);
-+			if (!ent)
-+				continue;
-+
-+			dump_country_chplan(sel, ent);
-+		}
-+	}
-+}
-+
-+void dump_chplan_id_list(void *sel)
-+{
-+	u8 first = 1;
-+	int i;
-+
-+	for (i = 0; i < RTW_ChannelPlanMap_size; i++) {
-+		if (!rtw_is_channel_plan_valid(i))
-+			continue;
-+
-+		if (first) {
-+			RTW_PRINT_SEL(sel, "0x%02X ", i);
-+			first = 0;
-+		} else
-+			_RTW_PRINT_SEL(sel, "0x%02X ", i);
-+	}
-+}
-+
-+#ifdef CONFIG_RTW_DEBUG
-+void dump_chplan_test(void *sel)
-+{
-+	int i, j;
-+
-+	/* check redundent */
-+	for (i = 0; i < RTW_CHD_2G_MAX; i++) {
-+		for (j = 0; j < i; j++) {
-+			if (CH_LIST_LEN(rtw_channel_def_2g[i]) == CH_LIST_LEN(rtw_channel_def_2g[j])
-+				&& _rtw_memcmp(&CH_LIST_CH(rtw_channel_def_2g[i], 0), &CH_LIST_CH(rtw_channel_def_2g[j], 0), CH_LIST_LEN(rtw_channel_def_2g[i]) + 1) == _TRUE)
-+				RTW_PRINT_SEL(sel, "2G chd:%u and %u is the same\n", i, j);
-+		}
-+	}
-+
-+	/* check invalid channel */
-+	for (i = 0; i < RTW_CHD_2G_MAX; i++) {
-+		for (j = 0; j < CH_LIST_LEN(rtw_channel_def_2g[i]); j++) {
-+			if (rtw_ch2freq(CH_LIST_CH(rtw_channel_def_2g[i], j)) == 0)
-+				RTW_PRINT_SEL(sel, "2G invalid ch:%u at (%d,%d)\n", CH_LIST_CH(rtw_channel_def_2g[i], j), i, j);
-+		}
-+	}
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	/* check redundent */
-+	for (i = 0; i < RTW_CHD_5G_MAX; i++) {
-+		for (j = 0; j < i; j++) {
-+			if (CH_LIST_LEN(rtw_channel_def_5g[i]) == CH_LIST_LEN(rtw_channel_def_5g[j])
-+				&& _rtw_memcmp(&CH_LIST_CH(rtw_channel_def_5g[i], 0), &CH_LIST_CH(rtw_channel_def_5g[j], 0), CH_LIST_LEN(rtw_channel_def_5g[i]) + 1) == _TRUE)
-+				RTW_PRINT_SEL(sel, "5G chd:%u and %u is the same\n", i, j);
-+		}
-+	}
-+
-+	/* check invalid channel */
-+	for (i = 0; i < RTW_CHD_5G_MAX; i++) {
-+		for (j = 0; j < CH_LIST_LEN(rtw_channel_def_5g[i]); j++) {
-+			if (rtw_ch2freq(CH_LIST_CH(rtw_channel_def_5g[i], j)) == 0)
-+				RTW_PRINT_SEL(sel, "5G invalid ch:%u at (%d,%d)\n", CH_LIST_CH(rtw_channel_def_5g[i], j), i, j);
-+		}
-+	}
-+#endif
-+
-+	/* check redundent */
-+	for (i = 0; i < RTW_ChannelPlanMap_size; i++) {
-+		if (!rtw_is_channel_plan_valid(i))
-+			continue;
-+		for (j = 0; j < i; j++) {
-+			if (!rtw_is_channel_plan_valid(j))
-+				continue;
-+			if (_rtw_memcmp(&RTW_ChannelPlanMap[i], &RTW_ChannelPlanMap[j], sizeof(RTW_ChannelPlanMap[i])) == _TRUE)
-+				RTW_PRINT_SEL(sel, "channel plan 0x%02x and 0x%02x is the same\n", i, j);
-+		}
-+	}
-+}
-+#endif /* CONFIG_RTW_DEBUG */
-+
-+void dump_chplan_ver(void *sel)
-+{
-+	RTW_PRINT_SEL(sel, "%s%s-%s\n", RTW_DOMAIN_MAP_VER, RTW_DOMAIN_MAP_M_VER, RTW_COUNTRY_MAP_VER);
-+}
-diff --git a/drivers/staging/rtl8723cs/core/rtw_chplan.h b/drivers/staging/rtl8723cs/core/rtw_chplan.h
-new file mode 100644
-index 000000000000..f7802395857a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_chplan.h
-@@ -0,0 +1,95 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2018 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_CHPLAN_H__
-+#define __RTW_CHPLAN_H__
-+
-+#define RTW_CHPLAN_UNSPECIFIED 0xFF
-+
-+u8 rtw_chplan_get_default_regd(u8 id);
-+bool rtw_chplan_is_empty(u8 id);
-+bool rtw_is_channel_plan_valid(u8 id);
-+bool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch);
-+
-+enum regd_src_t {
-+	REGD_SRC_RTK_PRIV = 0, /* Regulatory settings from Realtek framework (Realtek defined or customized) */
-+	REGD_SRC_OS = 1, /* Regulatory settings from OS */
-+	REGD_SRC_NUM,
-+};
-+
-+#define regd_src_is_valid(src) ((src) < REGD_SRC_NUM)
-+
-+extern const char *_regd_src_str[];
-+#define regd_src_str(src) ((src) >= REGD_SRC_NUM ? _regd_src_str[REGD_SRC_NUM] : _regd_src_str[src])
-+
-+struct _RT_CHANNEL_INFO;
-+u8 init_channel_set(_adapter *adapter);
-+bool rtw_chset_is_dfs_range(struct _RT_CHANNEL_INFO *chset, u32 hi, u32 lo);
-+bool rtw_chset_is_dfs_ch(struct _RT_CHANNEL_INFO *chset, u8 ch);
-+bool rtw_chset_is_dfs_chbw(struct _RT_CHANNEL_INFO *chset, u8 ch, u8 bw, u8 offset);
-+u8 rtw_process_beacon_hint(_adapter *adapter, WLAN_BSSID_EX *bss);
-+
-+#define IS_ALPHA2_NO_SPECIFIED(_alpha2) ((*((u16 *)(_alpha2))) == 0xFFFF)
-+#define IS_ALPHA2_WORLDWIDE(_alpha2) (strncmp(_alpha2, "00", 2) == 0)
-+
-+#define RTW_MODULE_RTL8821AE_HMC_M2		BIT0	/* RTL8821AE(HMC + M.2) */
-+#define RTW_MODULE_RTL8821AU			BIT1	/* RTL8821AU */
-+#define RTW_MODULE_RTL8812AENF_NGFF		BIT2	/* RTL8812AENF(8812AE+8761)_NGFF */
-+#define RTW_MODULE_RTL8812AEBT_HMC		BIT3	/* RTL8812AEBT(8812AE+8761)_HMC */
-+#define RTW_MODULE_RTL8188EE_HMC_M2		BIT4	/* RTL8188EE(HMC + M.2) */
-+#define RTW_MODULE_RTL8723BE_HMC_M2		BIT5	/* RTL8723BE(HMC + M.2) */
-+#define RTW_MODULE_RTL8723BS_NGFF1216	BIT6	/* RTL8723BS(NGFF1216) */
-+#define RTW_MODULE_RTL8192EEBT_HMC_M2	BIT7	/* RTL8192EEBT(8192EE+8761AU)_(HMC + M.2) */
-+#define RTW_MODULE_RTL8723DE_NGFF1630	BIT8	/* RTL8723DE(NGFF1630) */
-+#define RTW_MODULE_RTL8822BE			BIT9	/* RTL8822BE */
-+#define RTW_MODULE_RTL8821CE			BIT10	/* RTL8821CE */
-+#define RTW_MODULE_RTL8822CE			BIT11	/* RTL8822CE */
-+
-+enum rtw_dfs_regd {
-+	RTW_DFS_REGD_NONE	= 0,
-+	RTW_DFS_REGD_FCC	= 1,
-+	RTW_DFS_REGD_MKK	= 2,
-+	RTW_DFS_REGD_ETSI	= 3,
-+	RTW_DFS_REGD_NUM,
-+	RTW_DFS_REGD_AUTO	= 0xFF, /* follow channel plan */
-+};
-+
-+extern const char *_rtw_dfs_regd_str[];
-+#define rtw_dfs_regd_str(region) (((region) >= RTW_DFS_REGD_NUM) ? _rtw_dfs_regd_str[RTW_DFS_REGD_NONE] : _rtw_dfs_regd_str[(region)])
-+
-+struct country_chplan {
-+	char alpha2[2]; /* "00" means worldwide */
-+	u8 chplan;
-+#ifdef CONFIG_80211AC_VHT
-+	u8 en_11ac;
-+#endif
-+};
-+
-+#ifdef CONFIG_80211AC_VHT
-+#define COUNTRY_CHPLAN_EN_11AC(_ent) ((_ent)->en_11ac)
-+#else
-+#define COUNTRY_CHPLAN_EN_11AC(_ent) 0
-+#endif
-+
-+const struct country_chplan *rtw_get_chplan_from_country(const char *country_code);
-+
-+void dump_country_chplan(void *sel, const struct country_chplan *ent);
-+void dump_country_chplan_map(void *sel);
-+void dump_chplan_id_list(void *sel);
-+#ifdef CONFIG_RTW_DEBUG
-+void dump_chplan_test(void *sel);
-+#endif
-+void dump_chplan_ver(void *sel);
-+
-+#endif /* __RTW_CHPLAN_H__ */
-diff --git a/drivers/staging/rtl8723cs/core/rtw_cmd.c b/drivers/staging/rtl8723cs/core/rtw_cmd.c
-new file mode 100644
-index 000000000000..e43ee97793d0
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_cmd.c
-@@ -0,0 +1,5675 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_CMD_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#ifndef DBG_CMD_EXECUTE
-+	#define DBG_CMD_EXECUTE 0
-+#endif
-+
-+/*
-+Caller and the rtw_cmd_thread can protect cmd_q by spin_lock.
-+No irqsave is necessary.
-+*/
-+
-+sint	_rtw_init_cmd_priv(struct	cmd_priv *pcmdpriv)
-+{
-+	sint res = _SUCCESS;
-+
-+
-+	_rtw_init_sema(&(pcmdpriv->cmd_queue_sema), 0);
-+	/* _rtw_init_sema(&(pcmdpriv->cmd_done_sema), 0); */
-+	_rtw_init_sema(&(pcmdpriv->start_cmdthread_sema), 0);
-+
-+	_rtw_init_queue(&(pcmdpriv->cmd_queue));
-+
-+	/* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */
-+
-+	pcmdpriv->cmd_seq = 1;
-+
-+	pcmdpriv->cmd_allocated_buf = rtw_zmalloc(MAX_CMDSZ + CMDBUFF_ALIGN_SZ);
-+
-+	if (pcmdpriv->cmd_allocated_buf == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pcmdpriv->cmd_buf = pcmdpriv->cmd_allocated_buf  +  CMDBUFF_ALIGN_SZ - ((SIZE_PTR)(pcmdpriv->cmd_allocated_buf) & (CMDBUFF_ALIGN_SZ - 1));
-+
-+	pcmdpriv->rsp_allocated_buf = rtw_zmalloc(MAX_RSPSZ + 4);
-+
-+	if (pcmdpriv->rsp_allocated_buf == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pcmdpriv->rsp_buf = pcmdpriv->rsp_allocated_buf  +  4 - ((SIZE_PTR)(pcmdpriv->rsp_allocated_buf) & 3);
-+
-+	pcmdpriv->cmd_issued_cnt = pcmdpriv->cmd_done_cnt = pcmdpriv->rsp_cnt = 0;
-+
-+	_rtw_mutex_init(&pcmdpriv->sctx_mutex);
-+exit:
-+
-+
-+	return res;
-+
-+}
-+
-+#ifdef CONFIG_C2H_WK
-+static void c2h_wk_callback(_workitem *work)
-+{
-+	struct evt_priv *evtpriv = container_of(work, struct evt_priv, c2h_wk);
-+	_adapter *adapter = container_of(evtpriv, _adapter, evtpriv);
-+	u8 *c2h_evt;
-+	c2h_id_filter direct_hdl_filter = rtw_hal_c2h_id_handle_directly;
-+	u8 id, seq, plen;
-+	u8 *payload;
-+
-+	evtpriv->c2h_wk_alive = _TRUE;
-+
-+	while (!rtw_cbuf_empty(evtpriv->c2h_queue)) {
-+		c2h_evt = (u8 *)rtw_cbuf_pop(evtpriv->c2h_queue);
-+		if (c2h_evt != NULL) {
-+			/* This C2H event is read, clear it */
-+			c2h_evt_clear(adapter);
-+		} else {
-+			c2h_evt = (u8 *)rtw_malloc(C2H_REG_LEN);
-+			if (c2h_evt == NULL) {
-+				rtw_warn_on(1);
-+				continue;
-+			}
-+
-+			/* This C2H event is not read, read & clear now */
-+			if (rtw_hal_c2h_evt_read(adapter, c2h_evt) != _SUCCESS) {
-+				rtw_mfree(c2h_evt, C2H_REG_LEN);
-+				continue;
-+			}
-+		}
-+
-+		/* Special pointer to trigger c2h_evt_clear only */
-+		if ((void *)c2h_evt == (void *)evtpriv)
-+			continue;
-+
-+		if (!rtw_hal_c2h_valid(adapter, c2h_evt)
-+			|| rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload) != _SUCCESS
-+		) {
-+			rtw_mfree(c2h_evt, C2H_REG_LEN);
-+			continue;
-+		}
-+
-+		if (direct_hdl_filter(adapter, id, seq, plen, payload) == _TRUE) {
-+			/* Handle directly */
-+			rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
-+			rtw_mfree(c2h_evt, C2H_REG_LEN);
-+		} else {
-+			/* Enqueue into cmd_thread for others */
-+			rtw_c2h_reg_wk_cmd(adapter, c2h_evt);
-+			rtw_mfree(c2h_evt, C2H_REG_LEN);
-+		}
-+	}
-+
-+	evtpriv->c2h_wk_alive = _FALSE;
-+}
-+#endif /* CONFIG_C2H_WK */
-+
-+sint _rtw_init_evt_priv(struct evt_priv *pevtpriv)
-+{
-+	sint res = _SUCCESS;
-+
-+
-+#ifdef CONFIG_H2CLBK
-+	_rtw_init_sema(&(pevtpriv->lbkevt_done), 0);
-+	pevtpriv->lbkevt_limit = 0;
-+	pevtpriv->lbkevt_num = 0;
-+	pevtpriv->cmdevt_parm = NULL;
-+#endif
-+
-+	/* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */
-+	ATOMIC_SET(&pevtpriv->event_seq, 0);
-+	pevtpriv->evt_done_cnt = 0;
-+
-+#ifdef CONFIG_EVENT_THREAD_MODE
-+
-+	_rtw_init_sema(&(pevtpriv->evt_notify), 0);
-+
-+	pevtpriv->evt_allocated_buf = rtw_zmalloc(MAX_EVTSZ + 4);
-+	if (pevtpriv->evt_allocated_buf == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	pevtpriv->evt_buf = pevtpriv->evt_allocated_buf  +  4 - ((unsigned int)(pevtpriv->evt_allocated_buf) & 3);
-+
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	pevtpriv->allocated_c2h_mem = rtw_zmalloc(C2H_MEM_SZ + 4);
-+
-+	if (pevtpriv->allocated_c2h_mem == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pevtpriv->c2h_mem = pevtpriv->allocated_c2h_mem +  4\
-+			    - ((u32)(pevtpriv->allocated_c2h_mem) & 3);
-+#endif /* end of CONFIG_SDIO_HCI */
-+
-+	_rtw_init_queue(&(pevtpriv->evt_queue));
-+
-+exit:
-+
-+#endif /* end of CONFIG_EVENT_THREAD_MODE */
-+
-+#ifdef CONFIG_C2H_WK
-+	_init_workitem(&pevtpriv->c2h_wk, c2h_wk_callback, NULL);
-+	pevtpriv->c2h_wk_alive = _FALSE;
-+	pevtpriv->c2h_queue = rtw_cbuf_alloc(C2H_QUEUE_MAX_LEN + 1);
-+#endif
-+
-+
-+	return res;
-+}
-+
-+void _rtw_free_evt_priv(struct	evt_priv *pevtpriv)
-+{
-+
-+
-+#ifdef CONFIG_EVENT_THREAD_MODE
-+	_rtw_free_sema(&(pevtpriv->evt_notify));
-+
-+	if (pevtpriv->evt_allocated_buf)
-+		rtw_mfree(pevtpriv->evt_allocated_buf, MAX_EVTSZ + 4);
-+#endif
-+
-+#ifdef CONFIG_C2H_WK
-+	_cancel_workitem_sync(&pevtpriv->c2h_wk);
-+	while (pevtpriv->c2h_wk_alive)
-+		rtw_msleep_os(10);
-+
-+	while (!rtw_cbuf_empty(pevtpriv->c2h_queue)) {
-+		void *c2h;
-+		c2h = rtw_cbuf_pop(pevtpriv->c2h_queue);
-+		if (c2h != NULL && c2h != (void *)pevtpriv)
-+			rtw_mfree(c2h, 16);
-+	}
-+	rtw_cbuf_free(pevtpriv->c2h_queue);
-+#endif
-+
-+
-+
-+}
-+
-+void _rtw_free_cmd_priv(struct	cmd_priv *pcmdpriv)
-+{
-+
-+	if (pcmdpriv) {
-+		_rtw_spinlock_free(&(pcmdpriv->cmd_queue.lock));
-+		_rtw_free_sema(&(pcmdpriv->cmd_queue_sema));
-+		/* _rtw_free_sema(&(pcmdpriv->cmd_done_sema)); */
-+		_rtw_free_sema(&(pcmdpriv->start_cmdthread_sema));
-+
-+		if (pcmdpriv->cmd_allocated_buf)
-+			rtw_mfree(pcmdpriv->cmd_allocated_buf, MAX_CMDSZ + CMDBUFF_ALIGN_SZ);
-+
-+		if (pcmdpriv->rsp_allocated_buf)
-+			rtw_mfree(pcmdpriv->rsp_allocated_buf, MAX_RSPSZ + 4);
-+
-+		_rtw_mutex_free(&pcmdpriv->sctx_mutex);
-+	}
-+}
-+
-+/*
-+Calling Context:
-+
-+rtw_enqueue_cmd can only be called between kernel thread,
-+since only spin_lock is used.
-+
-+ISR/Call-Back functions can't call this sub-function.
-+
-+*/
-+#ifdef DBG_CMD_QUEUE
-+extern u8 dump_cmd_id;
-+#endif
-+
-+sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head)
-+{
-+	_irqL irqL;
-+
-+
-+	if (obj == NULL)
-+		goto exit;
-+
-+	/* _enter_critical_bh(&queue->lock, &irqL); */
-+	_enter_critical(&queue->lock, &irqL);
-+
-+	if (to_head)
-+		rtw_list_insert_head(&obj->list, &queue->queue);
-+	else
-+		rtw_list_insert_tail(&obj->list, &queue->queue);
-+
-+#ifdef DBG_CMD_QUEUE
-+	if (dump_cmd_id) {
-+		RTW_INFO("%s===> cmdcode:0x%02x\n", __FUNCTION__, obj->cmdcode);
-+		if (obj->cmdcode == CMD_SET_MLME_EVT) {
-+			if (obj->parmbuf) {
-+				struct rtw_evt_header *evt_hdr = (struct rtw_evt_header *)(obj->parmbuf);
-+				RTW_INFO("evt_hdr->id:%d\n", evt_hdr->id);
-+			}
-+		}
-+		if (obj->cmdcode == CMD_SET_DRV_EXTRA) {
-+			if (obj->parmbuf) {
-+				struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)(obj->parmbuf);
-+				RTW_INFO("pdrvextra_cmd_parm->ec_id:0x%02x\n", pdrvextra_cmd_parm->ec_id);
-+			}
-+		}
-+	}
-+
-+	if (queue->queue.prev->next != &queue->queue) {
-+		RTW_INFO("[%d] head %p, tail %p, tail->prev->next %p[tail], tail->next %p[head]\n", __LINE__,
-+			&queue->queue, queue->queue.prev, queue->queue.prev->prev->next, queue->queue.prev->next);
-+
-+		RTW_INFO("==========%s============\n", __FUNCTION__);
-+		RTW_INFO("head:%p,obj_addr:%p\n", &queue->queue, obj);
-+		RTW_INFO("padapter: %p\n", obj->padapter);
-+		RTW_INFO("cmdcode: 0x%02x\n", obj->cmdcode);
-+		RTW_INFO("res: %d\n", obj->res);
-+		RTW_INFO("parmbuf: %p\n", obj->parmbuf);
-+		RTW_INFO("cmdsz: %d\n", obj->cmdsz);
-+		RTW_INFO("rsp: %p\n", obj->rsp);
-+		RTW_INFO("rspsz: %d\n", obj->rspsz);
-+		RTW_INFO("sctx: %p\n", obj->sctx);
-+		RTW_INFO("list->next: %p\n", obj->list.next);
-+		RTW_INFO("list->prev: %p\n", obj->list.prev);
-+	}
-+#endif /* DBG_CMD_QUEUE */
-+
-+	/* _exit_critical_bh(&queue->lock, &irqL);	 */
-+	_exit_critical(&queue->lock, &irqL);
-+
-+exit:
-+
-+
-+	return _SUCCESS;
-+}
-+
-+struct	cmd_obj	*_rtw_dequeue_cmd(_queue *queue)
-+{
-+	_irqL irqL;
-+	struct cmd_obj *obj;
-+
-+
-+	/* _enter_critical_bh(&(queue->lock), &irqL); */
-+	_enter_critical(&queue->lock, &irqL);
-+
-+#ifdef DBG_CMD_QUEUE
-+	if (queue->queue.prev->next != &queue->queue) {
-+		RTW_INFO("[%d] head %p, tail %p, tail->prev->next %p[tail], tail->next %p[head]\n", __LINE__,
-+			&queue->queue, queue->queue.prev, queue->queue.prev->prev->next, queue->queue.prev->next);
-+	}
-+#endif /* DBG_CMD_QUEUE */
-+
-+
-+	if (rtw_is_list_empty(&(queue->queue)))
-+		obj = NULL;
-+	else {
-+		obj = LIST_CONTAINOR(get_next(&(queue->queue)), struct cmd_obj, list);
-+
-+#ifdef DBG_CMD_QUEUE
-+		if (queue->queue.prev->next != &queue->queue) {
-+			RTW_INFO("==========%s============\n", __FUNCTION__);
-+			RTW_INFO("head:%p,obj_addr:%p\n", &queue->queue, obj);
-+			RTW_INFO("padapter: %p\n", obj->padapter);
-+			RTW_INFO("cmdcode: 0x%02x\n", obj->cmdcode);
-+			RTW_INFO("res: %d\n", obj->res);
-+			RTW_INFO("parmbuf: %p\n", obj->parmbuf);
-+			RTW_INFO("cmdsz: %d\n", obj->cmdsz);
-+			RTW_INFO("rsp: %p\n", obj->rsp);
-+			RTW_INFO("rspsz: %d\n", obj->rspsz);
-+			RTW_INFO("sctx: %p\n", obj->sctx);
-+			RTW_INFO("list->next: %p\n", obj->list.next);
-+			RTW_INFO("list->prev: %p\n", obj->list.prev);
-+		}
-+
-+		if (dump_cmd_id) {
-+			RTW_INFO("%s===> cmdcode:0x%02x\n", __FUNCTION__, obj->cmdcode);
-+			if (obj->cmdcode == CMD_SET_DRV_EXTRA) {
-+				if (obj->parmbuf) {
-+					struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)(obj->parmbuf);
-+					printk("pdrvextra_cmd_parm->ec_id:0x%02x\n", pdrvextra_cmd_parm->ec_id);
-+				}
-+			}
-+
-+		}
-+#endif /* DBG_CMD_QUEUE */
-+
-+		rtw_list_delete(&obj->list);
-+	}
-+
-+	/* _exit_critical_bh(&(queue->lock), &irqL); */
-+	_exit_critical(&queue->lock, &irqL);
-+
-+
-+	return obj;
-+}
-+
-+u32	rtw_init_cmd_priv(struct cmd_priv *pcmdpriv)
-+{
-+	u32	res;
-+	res = _rtw_init_cmd_priv(pcmdpriv);
-+	return res;
-+}
-+
-+u32	rtw_init_evt_priv(struct	evt_priv *pevtpriv)
-+{
-+	int	res;
-+	res = _rtw_init_evt_priv(pevtpriv);
-+	return res;
-+}
-+
-+void rtw_free_evt_priv(struct	evt_priv *pevtpriv)
-+{
-+	_rtw_free_evt_priv(pevtpriv);
-+}
-+
-+void rtw_free_cmd_priv(struct	cmd_priv *pcmdpriv)
-+{
-+	_rtw_free_cmd_priv(pcmdpriv);
-+}
-+
-+int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj);
-+int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj)
-+{
-+#ifndef CONFIG_MAC_LOOPBACK_DRIVER
-+	u8 bAllow = _FALSE; /* set to _TRUE to allow enqueuing cmd when hw_init_completed is _FALSE */
-+#else
-+	u8 bAllow = _TRUE; /* hw_init_completed is _FALSE in the case of MAC loopback*/
-+#endif
-+
-+#ifdef SUPPORT_HW_RFOFF_DETECTED
-+	/* To decide allow or not */
-+	if ((adapter_to_pwrctl(pcmdpriv->padapter)->bHWPwrPindetect)
-+	    && (!pcmdpriv->padapter->registrypriv.usbss_enable)
-+	   ) {
-+		if (cmd_obj->cmdcode == CMD_SET_DRV_EXTRA) {
-+			struct drvextra_cmd_parm	*pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf;
-+			if (pdrvextra_cmd_parm->ec_id == POWER_SAVING_CTRL_WK_CID) {
-+				/* RTW_INFO("==>enqueue POWER_SAVING_CTRL_WK_CID\n"); */
-+				bAllow = _TRUE;
-+			}
-+		}
-+	}
-+#endif
-+
-+	if (cmd_obj->cmdcode == CMD_SET_CHANPLAN)
-+		bAllow = _TRUE;
-+
-+	if (cmd_obj->no_io)
-+		bAllow = _TRUE;
-+
-+	if ((!rtw_is_hw_init_completed(pcmdpriv->padapter) && (bAllow == _FALSE))
-+	    || ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _FALSE	/* com_thread not running */
-+	   ) {
-+		if (DBG_CMD_EXECUTE)
-+			RTW_INFO(ADPT_FMT" drop "CMD_FMT" hw_init_completed:%u, cmdthd_running:%u\n", ADPT_ARG(cmd_obj->padapter)
-+				, CMD_ARG(cmd_obj), rtw_get_hw_init_completed(cmd_obj->padapter), ATOMIC_READ(&pcmdpriv->cmdthd_running));
-+		if (0)
-+			rtw_warn_on(1);
-+
-+		return _FAIL;
-+	}
-+	return _SUCCESS;
-+}
-+
-+
-+
-+u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj)
-+{
-+	int res = _FAIL;
-+	PADAPTER padapter = pcmdpriv->padapter;
-+
-+
-+	if (cmd_obj == NULL)
-+		goto exit;
-+
-+	cmd_obj->padapter = padapter;
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	/* change pcmdpriv to primary's pcmdpriv */
-+	if (!is_primary_adapter(padapter))
-+		pcmdpriv = &(GET_PRIMARY_ADAPTER(padapter)->cmdpriv);
-+#endif
-+
-+	res = rtw_cmd_filter(pcmdpriv, cmd_obj);
-+	if ((_FAIL == res) || (cmd_obj->cmdsz > MAX_CMDSZ)) {
-+		if (cmd_obj->cmdsz > MAX_CMDSZ) {
-+			RTW_INFO("%s failed due to obj->cmdsz(%d) > MAX_CMDSZ(%d)\n", __func__, cmd_obj->cmdsz, MAX_CMDSZ);
-+			rtw_warn_on(1);
-+		}
-+
-+		if (cmd_obj->cmdcode == CMD_SET_DRV_EXTRA) {
-+			struct drvextra_cmd_parm *extra_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf;
-+
-+			if (extra_parm->pbuf && extra_parm->size > 0)
-+				rtw_mfree(extra_parm->pbuf, extra_parm->size);
-+		}
-+		rtw_free_cmd_obj(cmd_obj);
-+		goto exit;
-+	}
-+
-+	res = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, cmd_obj, 0);
-+
-+	if (res == _SUCCESS)
-+		_rtw_up_sema(&pcmdpriv->cmd_queue_sema);
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+struct	cmd_obj	*rtw_dequeue_cmd(struct cmd_priv *pcmdpriv)
-+{
-+	struct cmd_obj *cmd_obj;
-+
-+
-+	cmd_obj = _rtw_dequeue_cmd(&pcmdpriv->cmd_queue);
-+
-+	return cmd_obj;
-+}
-+
-+void rtw_cmd_clr_isr(struct	cmd_priv *pcmdpriv)
-+{
-+	pcmdpriv->cmd_done_cnt++;
-+	/* _rtw_up_sema(&(pcmdpriv->cmd_done_sema)); */
-+}
-+
-+void rtw_free_cmd_obj(struct cmd_obj *pcmd)
-+{
-+	if (pcmd->parmbuf != NULL) {
-+		/* free parmbuf in cmd_obj */
-+		rtw_mfree((unsigned char *)pcmd->parmbuf, pcmd->cmdsz);
-+	}
-+	if (pcmd->rsp != NULL) {
-+		if (pcmd->rspsz != 0) {
-+			/* free rsp in cmd_obj */
-+			rtw_mfree((unsigned char *)pcmd->rsp, pcmd->rspsz);
-+		}
-+	}
-+
-+	/* free cmd_obj */
-+	rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj));
-+}
-+
-+
-+void rtw_stop_cmd_thread(_adapter *adapter)
-+{
-+	if (adapter->cmdThread) {
-+		_rtw_up_sema(&adapter->cmdpriv.cmd_queue_sema);
-+		rtw_thread_stop(adapter->cmdThread);
-+		adapter->cmdThread = NULL;
-+	}
-+}
-+
-+thread_return rtw_cmd_thread(thread_context context)
-+{
-+	u8 ret;
-+	struct cmd_obj *pcmd;
-+	u8 *pcmdbuf, *prspbuf;
-+	systime cmd_start_time;
-+	u32 cmd_process_time;
-+	u8(*cmd_hdl)(_adapter *padapter, u8 *pbuf);
-+	void (*pcmd_callback)(_adapter *dev, struct cmd_obj *pcmd);
-+	PADAPTER padapter = (PADAPTER)context;
-+	struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
-+	struct drvextra_cmd_parm *extra_parm = NULL;
-+	_irqL irqL;
-+
-+	thread_enter("RTW_CMD_THREAD");
-+
-+	pcmdbuf = pcmdpriv->cmd_buf;
-+	prspbuf = pcmdpriv->rsp_buf;
-+	ATOMIC_SET(&(pcmdpriv->cmdthd_running), _TRUE);
-+	_rtw_up_sema(&pcmdpriv->start_cmdthread_sema);
-+
-+
-+	while (1) {
-+		if (_rtw_down_sema(&pcmdpriv->cmd_queue_sema) == _FAIL) {
-+			RTW_PRINT(FUNC_ADPT_FMT" _rtw_down_sema(&pcmdpriv->cmd_queue_sema) return _FAIL, break\n", FUNC_ADPT_ARG(padapter));
-+			break;
-+		}
-+
-+		if (RTW_CANNOT_RUN(padapter)) {
-+			RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n",
-+				FUNC_ADPT_ARG(padapter),
-+				rtw_is_drv_stopped(padapter) ? "True" : "False",
-+				rtw_is_surprise_removed(padapter) ? "True" : "False");
-+			break;
-+		}
-+
-+		_enter_critical(&pcmdpriv->cmd_queue.lock, &irqL);
-+		if (rtw_is_list_empty(&(pcmdpriv->cmd_queue.queue))) {
-+			/* RTW_INFO("%s: cmd queue is empty!\n", __func__); */
-+			_exit_critical(&pcmdpriv->cmd_queue.lock, &irqL);
-+			continue;
-+		}
-+		_exit_critical(&pcmdpriv->cmd_queue.lock, &irqL);
-+
-+_next:
-+		if (RTW_CANNOT_RUN(padapter)) {
-+			RTW_PRINT("%s: DriverStopped(%s) SurpriseRemoved(%s) break at line %d\n",
-+				  __func__
-+				, rtw_is_drv_stopped(padapter) ? "True" : "False"
-+				, rtw_is_surprise_removed(padapter) ? "True" : "False"
-+				  , __LINE__);
-+			break;
-+		}
-+
-+		pcmd = rtw_dequeue_cmd(pcmdpriv);
-+		if (!pcmd) {
-+#ifdef CONFIG_LPS_LCLK
-+			rtw_unregister_cmd_alive(padapter);
-+#endif
-+			continue;
-+		}
-+
-+		cmd_start_time = rtw_get_current_time();
-+		pcmdpriv->cmd_issued_cnt++;
-+
-+		if (pcmd->cmdsz > MAX_CMDSZ) {
-+			RTW_ERR("%s cmdsz:%d > MAX_CMDSZ:%d\n", __func__, pcmd->cmdsz, MAX_CMDSZ);
-+			pcmd->res = H2C_PARAMETERS_ERROR;
-+			goto post_process;
-+		}
-+
-+		if (pcmd->cmdcode >= (sizeof(wlancmds) / sizeof(struct rtw_cmd))) {
-+			RTW_ERR("%s undefined cmdcode:%d\n", __func__, pcmd->cmdcode);
-+			pcmd->res = H2C_PARAMETERS_ERROR;
-+			goto post_process;
-+		}
-+
-+		cmd_hdl = wlancmds[pcmd->cmdcode].cmd_hdl;
-+		if (!cmd_hdl) {
-+			RTW_ERR("%s no cmd_hdl for cmdcode:%d\n", __func__, pcmd->cmdcode);
-+			pcmd->res = H2C_PARAMETERS_ERROR;
-+			goto post_process;
-+		}
-+
-+		if (_FAIL == rtw_cmd_filter(pcmdpriv, pcmd)) {
-+			pcmd->res = H2C_DROPPED;
-+			if (pcmd->cmdcode == CMD_SET_DRV_EXTRA) {
-+				extra_parm = (struct drvextra_cmd_parm *)pcmd->parmbuf;
-+				if (extra_parm && extra_parm->pbuf && extra_parm->size > 0)
-+					rtw_mfree(extra_parm->pbuf, extra_parm->size);
-+			}
-+			#if CONFIG_DFS
-+			else if (pcmd->cmdcode == CMD_SET_CHANSWITCH)
-+				adapter_to_rfctl(padapter)->csa_ch = 0;
-+			#endif
-+			goto post_process;
-+		}
-+
-+#ifdef CONFIG_LPS_LCLK
-+		if (pcmd->no_io)
-+			rtw_unregister_cmd_alive(padapter);
-+		else {
-+			if (rtw_register_cmd_alive(padapter) != _SUCCESS) {
-+				if (DBG_CMD_EXECUTE)
-+					RTW_PRINT("%s: wait to leave LPS_LCLK\n", __func__);
-+
-+				pcmd->res = H2C_ENQ_HEAD;
-+				ret = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, pcmd, 1);
-+				if (ret == _SUCCESS) {
-+					if (DBG_CMD_EXECUTE)
-+						RTW_INFO(ADPT_FMT" "CMD_FMT" ENQ_HEAD\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd));
-+					continue;
-+				}
-+
-+				RTW_INFO(ADPT_FMT" "CMD_FMT" ENQ_HEAD_FAIL\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd));
-+				pcmd->res = H2C_ENQ_HEAD_FAIL;
-+				rtw_warn_on(1);
-+			}
-+		}
-+#endif /* CONFIG_LPS_LCLK */
-+
-+		if (DBG_CMD_EXECUTE)
-+			RTW_INFO(ADPT_FMT" "CMD_FMT" %sexecute\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd)
-+				, pcmd->res == H2C_ENQ_HEAD ? "ENQ_HEAD " : (pcmd->res == H2C_ENQ_HEAD_FAIL ? "ENQ_HEAD_FAIL " : ""));
-+
-+		_rtw_memcpy(pcmdbuf, pcmd->parmbuf, pcmd->cmdsz);
-+		ret = cmd_hdl(pcmd->padapter, pcmdbuf);
-+		pcmd->res = ret;
-+
-+		pcmdpriv->cmd_seq++;
-+
-+post_process:
-+
-+		_enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
-+		if (pcmd->sctx) {
-+			if (0)
-+				RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter));
-+			if (pcmd->res == H2C_SUCCESS)
-+				rtw_sctx_done(&pcmd->sctx);
-+			else
-+				rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_ERROR);
-+		}
-+		_exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
-+
-+		cmd_process_time = rtw_get_passing_time_ms(cmd_start_time);
-+		if (cmd_process_time > 1000) {
-+			RTW_INFO(ADPT_FMT" "CMD_FMT" process_time=%d\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd), cmd_process_time);
-+			if (0)
-+				rtw_warn_on(1);
-+		}
-+
-+		/* call callback function for post-processed */
-+		if (pcmd->cmdcode < (sizeof(wlancmds) / sizeof(struct rtw_cmd)))
-+			pcmd_callback = wlancmds[pcmd->cmdcode].callback;
-+		else
-+			pcmd_callback = NULL;
-+
-+		if (pcmd_callback == NULL) {
-+			rtw_free_cmd_obj(pcmd);
-+		} else {
-+			/* todo: !!! fill rsp_buf to pcmd->rsp if (pcmd->rsp!=NULL) */
-+			pcmd_callback(pcmd->padapter, pcmd);/* need conider that free cmd_obj in rtw_cmd_callback */
-+		}
-+
-+		flush_signals_thread();
-+
-+		goto _next;
-+
-+	}
-+
-+#ifdef CONFIG_LPS_LCLK
-+	rtw_unregister_cmd_alive(padapter);
-+#endif
-+
-+	/* to avoid enqueue cmd after free all cmd_obj */
-+	ATOMIC_SET(&(pcmdpriv->cmdthd_running), _FALSE);
-+
-+	/* free all cmd_obj resources */
-+	do {
-+		pcmd = rtw_dequeue_cmd(pcmdpriv);
-+		if (pcmd == NULL)
-+			break;
-+
-+		if (0)
-+			RTW_INFO("%s: leaving... drop "CMD_FMT"\n", __func__, CMD_ARG(pcmd));
-+
-+		if (pcmd->cmdcode == CMD_SET_DRV_EXTRA) {
-+			extra_parm = (struct drvextra_cmd_parm *)pcmd->parmbuf;
-+			if (extra_parm->pbuf && extra_parm->size > 0)
-+				rtw_mfree(extra_parm->pbuf, extra_parm->size);
-+		}
-+		#if CONFIG_DFS
-+		else if (pcmd->cmdcode == CMD_SET_CHANSWITCH)
-+			adapter_to_rfctl(padapter)->csa_ch = 0;
-+		#endif
-+
-+		_enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
-+		if (pcmd->sctx) {
-+			if (0)
-+				RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter));
-+			rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_DROP);
-+		}
-+		_exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
-+
-+		rtw_free_cmd_obj(pcmd);
-+	} while (1);
-+
-+	RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter));
-+
-+	rtw_thread_wait_stop();
-+
-+	return 0;
-+}
-+
-+
-+#ifdef CONFIG_EVENT_THREAD_MODE
-+u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj)
-+{
-+	_irqL irqL;
-+	int	res;
-+	_queue *queue = &pevtpriv->evt_queue;
-+
-+
-+	res = _SUCCESS;
-+
-+	if (obj == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+
-+	rtw_list_insert_tail(&obj->list, &queue->queue);
-+
-+	_exit_critical_bh(&queue->lock, &irqL);
-+
-+	/* rtw_evt_notify_isr(pevtpriv); */
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+struct evt_obj *rtw_dequeue_evt(_queue *queue)
-+{
-+	_irqL irqL;
-+	struct	evt_obj	*pevtobj;
-+
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+
-+	if (rtw_is_list_empty(&(queue->queue)))
-+		pevtobj = NULL;
-+	else {
-+		pevtobj = LIST_CONTAINOR(get_next(&(queue->queue)), struct evt_obj, list);
-+		rtw_list_delete(&pevtobj->list);
-+	}
-+
-+	_exit_critical_bh(&queue->lock, &irqL);
-+
-+
-+	return pevtobj;
-+}
-+
-+void rtw_free_evt_obj(struct evt_obj *pevtobj)
-+{
-+
-+	if (pevtobj->parmbuf)
-+		rtw_mfree((unsigned char *)pevtobj->parmbuf, pevtobj->evtsz);
-+
-+	rtw_mfree((unsigned char *)pevtobj, sizeof(struct evt_obj));
-+
-+}
-+
-+void rtw_evt_notify_isr(struct evt_priv *pevtpriv)
-+{
-+	pevtpriv->evt_done_cnt++;
-+	_rtw_up_sema(&(pevtpriv->evt_notify));
-+}
-+#endif
-+
-+void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm)
-+{
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+
-+	_rtw_memset(pparm, 0, sizeof(struct sitesurvey_parm));
-+	pparm->scan_mode = pmlmepriv->scan_mode;
-+}
-+
-+/*
-+rtw_sitesurvey_cmd(~)
-+	### NOTE:#### (!!!!)
-+	MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock
-+*/
-+u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm)
-+{
-+	u8 res = _FAIL;
-+	struct cmd_obj		*ph2c;
-+	struct sitesurvey_parm	*psurveyPara;
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+
-+#ifdef CONFIG_LPS
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SCAN, 0);
-+#endif
-+
-+#ifdef CONFIG_P2P_PS
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		p2p_ps_wk_cmd(padapter, P2P_PS_SCAN, 1);
-+#endif /* CONFIG_P2P_PS */
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL)
-+		return _FAIL;
-+
-+	psurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm));
-+	if (psurveyPara == NULL) {
-+		rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj));
-+		return _FAIL;
-+	}
-+
-+	if (pparm)
-+		_rtw_memcpy(psurveyPara, pparm, sizeof(struct sitesurvey_parm));
-+	else
-+		psurveyPara->scan_mode = pmlmepriv->scan_mode;
-+
-+	rtw_free_network_queue(padapter, _FALSE);
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, CMD_SITE_SURVEY);
-+
-+	set_fwstate(pmlmepriv, WIFI_UNDER_SURVEY);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+	if (res == _SUCCESS) {
-+		u32 scan_timeout_ms;
-+
-+		pmlmepriv->scan_start_time = rtw_get_current_time();
-+		scan_timeout_ms = rtw_scan_timeout_decision(padapter);
-+		mlme_set_scan_to_timer(pmlmepriv,scan_timeout_ms);
-+
-+		rtw_led_control(padapter, LED_CTL_SITE_SURVEY);
-+	} else
-+		_clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY);
-+
-+
-+	return res;
-+}
-+
-+void rtw_readtssi_cmdrsp_callback(_adapter	*padapter,  struct cmd_obj *pcmd)
-+{
-+
-+	rtw_mfree((unsigned char *) pcmd->parmbuf, pcmd->cmdsz);
-+	rtw_mfree((unsigned char *) pcmd, sizeof(struct cmd_obj));
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	if (padapter->registrypriv.mp_mode == 1)
-+		padapter->mppriv.workparam.bcompleted = _TRUE;
-+#endif
-+
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+static u8 rtw_createbss_cmd(_adapter  *adapter, int flags, bool adhoc
-+	, u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct createbss_parm *parm;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8 res = _SUCCESS;
-+
-+	if (req_ch > 0 && req_bw >= 0 && req_offset >= 0) {
-+		if (!rtw_chset_is_chbw_valid(adapter_to_chset(adapter), req_ch, req_bw, req_offset, 0, 0)) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+	}
-+
-+	/* prepare cmd parameter */
-+	parm = (struct createbss_parm *)rtw_zmalloc(sizeof(*parm));
-+	if (parm == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	if (adhoc) {
-+		/* for now, adhoc doesn't support ch,bw,offset request */
-+		parm->adhoc = 1;
-+	} else {
-+		parm->adhoc = 0;
-+		parm->ifbmp = ifbmp;
-+		parm->excl_ifbmp = excl_ifbmp;
-+		parm->req_ch = req_ch;
-+		parm->req_bw = req_bw;
-+		parm->req_offset = req_offset;
-+	}
-+
-+	if (flags & RTW_CMDF_DIRECTLY) {
-+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
-+		if (H2C_SUCCESS != createbss_hdl(adapter, (u8 *)parm))
-+			res = _FAIL;
-+		rtw_mfree((u8 *)parm, sizeof(*parm));
-+	} else {
-+		/* need enqueue, prepare cmd_obj and enqueue */
-+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
-+		if (cmdobj == NULL) {
-+			res = _FAIL;
-+			rtw_mfree((u8 *)parm, sizeof(*parm));
-+			goto exit;
-+		}
-+
-+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_CREATE_BSS);
-+
-+		if (flags & RTW_CMDF_WAIT_ACK) {
-+			cmdobj->sctx = &sctx;
-+			rtw_sctx_init(&sctx, 2000);
-+		}
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+
-+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			rtw_sctx_wait(&sctx, __func__);
-+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status == RTW_SCTX_SUBMITTED)
-+				cmdobj->sctx = NULL;
-+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+		}
-+	}
-+
-+exit:
-+	return res;
-+}
-+
-+inline u8 rtw_create_ibss_cmd(_adapter *adapter, int flags)
-+{
-+	return rtw_createbss_cmd(adapter, flags
-+		, 1
-+		, 0, 0
-+		, 0, REQ_BW_NONE, REQ_OFFSET_NONE /* for now, adhoc doesn't support ch,bw,offset request */
-+	);
-+}
-+
-+inline u8 rtw_startbss_cmd(_adapter *adapter, int flags)
-+{
-+	return rtw_createbss_cmd(adapter, flags
-+		, 0
-+		, BIT(adapter->iface_id), 0
-+		, 0, REQ_BW_NONE, REQ_OFFSET_NONE /* excute entire AP setup cmd */
-+	);
-+}
-+
-+inline u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags
-+	, u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset)
-+{
-+	return rtw_createbss_cmd(adapter, flags
-+		, 0
-+		, ifbmp, excl_ifbmp
-+		, req_ch, req_bw, req_offset
-+	);
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+u8 rtw_joinbss_cmd(_adapter  *padapter, struct wlan_network *pnetwork)
-+{
-+	u8	*auth, res = _SUCCESS;
-+	uint	t_len = 0;
-+	WLAN_BSSID_EX		*psecnetwork;
-+	struct cmd_obj		*pcmd;
-+	struct cmd_priv		*pcmdpriv = &padapter->cmdpriv;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
-+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
-+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+#ifdef CONFIG_80211N_HT
-+	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
-+#endif /* CONFIG_80211N_HT */
-+#ifdef CONFIG_80211AC_VHT
-+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
-+#endif /* CONFIG_80211AC_VHT */
-+	NDIS_802_11_NETWORK_INFRASTRUCTURE ndis_network_mode = pnetwork->network.InfrastructureMode;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	u32 tmp_len;
-+	u8 *ptmp = NULL;
-+
-+	rtw_led_control(padapter, LED_CTL_START_TO_LINK);
-+
-+	pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (pcmd == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+#if 0
-+	/*  for IEs is pointer */
-+	t_len = sizeof(u32) + sizeof(NDIS_802_11_MAC_ADDRESS) + 2 +
-+		sizeof(NDIS_802_11_SSID) + sizeof(u32) +
-+		sizeof(NDIS_802_11_RSSI) + sizeof(NDIS_802_11_NETWORK_TYPE) +
-+		sizeof(NDIS_802_11_CONFIGURATION) +
-+		sizeof(NDIS_802_11_NETWORK_INFRASTRUCTURE) +
-+		sizeof(NDIS_802_11_RATES_EX) + sizeof(WLAN_PHY_INFO) + sizeof(u32) + MAX_IE_SZ;
-+#endif
-+	/* for IEs is fix buf size */
-+	t_len = sizeof(WLAN_BSSID_EX);
-+
-+
-+	/* for hidden ap to set fw_state here */
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) != _TRUE) {
-+		switch (ndis_network_mode) {
-+		case Ndis802_11IBSS:
-+			set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
-+			break;
-+
-+		case Ndis802_11Infrastructure:
-+			set_fwstate(pmlmepriv, WIFI_STATION_STATE);
-+			break;
-+
-+		default:
-+			rtw_warn_on(1);
-+			break;
-+		}
-+	}
-+
-+	pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->network.IEs, pnetwork->network.IELength);
-+
-+#ifdef CONFIG_80211AC_VHT
-+	/* save AP beamform_cap info for BCM IOT issue */
-+	if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM)
-+		get_vht_bf_cap(pnetwork->network.IEs,
-+			pnetwork->network.IELength,
-+			&pvhtpriv->ap_bf_cap);
-+#endif
-+	/*
-+		Modified by Arvin 2015/05/13
-+		Solution for allocating a new WLAN_BSSID_EX to avoid race condition issue between disconnect and joinbss
-+	*/
-+	psecnetwork = (WLAN_BSSID_EX *)rtw_zmalloc(sizeof(WLAN_BSSID_EX));
-+	if (psecnetwork == NULL) {
-+		if (pcmd != NULL)
-+			rtw_mfree((unsigned char *)pcmd, sizeof(struct	cmd_obj));
-+
-+		res = _FAIL;
-+
-+
-+		goto exit;
-+	}
-+
-+	_rtw_memset(psecnetwork, 0, t_len);
-+
-+	_rtw_memcpy(psecnetwork, &pnetwork->network, get_WLAN_BSSID_EX_sz(&pnetwork->network));
-+
-+	auth = &psecuritypriv->authenticator_ie[0];
-+	psecuritypriv->authenticator_ie[0] = (unsigned char)psecnetwork->IELength;
-+
-+	if ((psecnetwork->IELength - 12) < (256 - 1))
-+		_rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], psecnetwork->IELength - 12);
-+	else
-+		_rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], (256 - 1));
-+
-+	psecnetwork->IELength = 0;
-+	/* Added by Albert 2009/02/18 */
-+	/* If the the driver wants to use the bssid to create the connection. */
-+	/* If not,  we have to copy the connecting AP's MAC address to it so that */
-+	/* the driver just has the bssid information for PMKIDList searching. */
-+
-+	if (pmlmepriv->assoc_by_bssid == _FALSE)
-+		_rtw_memcpy(&pmlmepriv->assoc_bssid[0], &pnetwork->network.MacAddress[0], ETH_ALEN);
-+
-+	/* copy fixed ie */
-+	_rtw_memcpy(psecnetwork->IEs, pnetwork->network.IEs, 12);
-+	psecnetwork->IELength = 12;
-+
-+	psecnetwork->IELength += rtw_restruct_sec_ie(padapter, psecnetwork->IEs + psecnetwork->IELength);
-+
-+
-+	pqospriv->qos_option = 0;
-+
-+	if (pregistrypriv->wmm_enable) {
-+#ifdef CONFIG_WMMPS_STA	
-+		rtw_uapsd_use_default_setting(padapter);
-+#endif /* CONFIG_WMMPS_STA */		
-+		tmp_len = rtw_restruct_wmm_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength, psecnetwork->IELength);
-+
-+		if (psecnetwork->IELength != tmp_len) {
-+			psecnetwork->IELength = tmp_len;
-+			pqospriv->qos_option = 1; /* There is WMM IE in this corresp. beacon */
-+		} else {
-+			pqospriv->qos_option = 0;/* There is no WMM IE in this corresp. beacon */
-+		}
-+	}
-+
-+#ifdef CONFIG_80211N_HT
-+	phtpriv->ht_option = _FALSE;
-+	if (pregistrypriv->ht_enable && is_supported_ht(pregistrypriv->wireless_mode)) {
-+		ptmp = rtw_get_ie(&pnetwork->network.IEs[12], _HT_CAPABILITY_IE_, &tmp_len, pnetwork->network.IELength - 12);
-+		if (ptmp && tmp_len > 0) {
-+			/*	Added by Albert 2010/06/23 */
-+			/*	For the WEP mode, we will use the bg mode to do the connection to avoid some IOT issue. */
-+			/*	Especially for Realtek 8192u SoftAP. */
-+			if ((padapter->securitypriv.dot11PrivacyAlgrthm != _WEP40_) &&
-+			    (padapter->securitypriv.dot11PrivacyAlgrthm != _WEP104_) &&
-+			    (padapter->securitypriv.dot11PrivacyAlgrthm != _TKIP_)) {
-+				rtw_ht_use_default_setting(padapter);
-+
-+				/* rtw_restructure_ht_ie */
-+				rtw_restructure_ht_ie(padapter, &pnetwork->network.IEs[12], &psecnetwork->IEs[0],
-+					pnetwork->network.IELength - 12, &psecnetwork->IELength,
-+					pnetwork->network.Configuration.DSConfig);
-+			}
-+		}
-+	}
-+
-+#ifdef CONFIG_80211AC_VHT
-+	pvhtpriv->vht_option = _FALSE;
-+	if (phtpriv->ht_option
-+		&& REGSTY_IS_11AC_ENABLE(pregistrypriv)
-+		&& is_supported_vht(pregistrypriv->wireless_mode)
-+		&& (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
-+	) {
-+		u8 vht_enable = 0;
-+
-+		if (pnetwork->network.Configuration.DSConfig > 14)
-+			vht_enable = 1;
-+		else if ((REGSTY_IS_11AC_24G_ENABLE(pregistrypriv)) && (padapter->registrypriv.wifi_spec == 0))
-+			vht_enable = 1;
-+
-+		if (vht_enable == 1)
-+			rtw_restructure_vht_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0],
-+				pnetwork->network.IELength, &psecnetwork->IELength);
-+	}
-+#endif
-+#endif /* CONFIG_80211N_HT */
-+
-+	rtw_append_exented_cap(padapter, &psecnetwork->IEs[0], &psecnetwork->IELength);
-+
-+#ifdef CONFIG_RTW_80211R
-+	rtw_ft_validate_akm_type(padapter, pnetwork);
-+#endif
-+
-+#if 0
-+	psecuritypriv->supplicant_ie[0] = (u8)psecnetwork->IELength;
-+
-+	if (psecnetwork->IELength < (256 - 1))
-+		_rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], psecnetwork->IELength);
-+	else
-+		_rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], (256 - 1));
-+#endif
-+
-+	pcmd->cmdsz = sizeof(WLAN_BSSID_EX);
-+
-+	_rtw_init_listhead(&pcmd->list);
-+	pcmd->cmdcode = CMD_JOINBSS;/* _JoinBss_CMD_ */
-+	pcmd->parmbuf = (unsigned char *)psecnetwork;
-+	pcmd->rsp = NULL;
-+	pcmd->rspsz = 0;
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, pcmd);
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags) /* for sta_mode */
-+{
-+	struct cmd_obj *cmdobj = NULL;
-+	struct disconnect_parm *param = NULL;
-+	struct cmd_priv *cmdpriv = &padapter->cmdpriv;
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8 res = _SUCCESS;
-+
-+	/* prepare cmd parameter */
-+	param = (struct disconnect_parm *)rtw_zmalloc(sizeof(*param));
-+	if (param == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	param->deauth_timeout_ms = deauth_timeout_ms;
-+
-+	if (flags & RTW_CMDF_DIRECTLY) {
-+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
-+		if (disconnect_hdl(padapter, (u8 *)param) != H2C_SUCCESS)
-+			res = _FAIL;
-+		rtw_mfree((u8 *)param, sizeof(*param));
-+
-+	} else {
-+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
-+		if (cmdobj == NULL) {
-+			res = _FAIL;
-+			rtw_mfree((u8 *)param, sizeof(*param));
-+			goto exit;
-+		}
-+		init_h2fwcmd_w_parm_no_rsp(cmdobj, param, CMD_DISCONNECT);
-+		if (flags & RTW_CMDF_WAIT_ACK) {
-+			cmdobj->sctx = &sctx;
-+			rtw_sctx_init(&sctx, 2000);
-+		}
-+		res = rtw_enqueue_cmd(cmdpriv, cmdobj);
-+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			rtw_sctx_wait(&sctx, __func__);
-+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status == RTW_SCTX_SUBMITTED)
-+				cmdobj->sctx = NULL;
-+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+		}
-+	}
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+u8 rtw_stop_ap_cmd(_adapter  *adapter, u8 flags)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *parm;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8 res = _SUCCESS;
-+
-+	if (flags & RTW_CMDF_DIRECTLY) {
-+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
-+		if (H2C_SUCCESS != stop_ap_hdl(adapter))
-+			res = _FAIL;
-+	} else {
-+		parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+		if (parm == NULL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		parm->ec_id = STOP_AP_WK_CID;
-+		parm->type = 0;
-+		parm->size = 0;
-+		parm->pbuf = NULL;
-+		
-+		/* need enqueue, prepare cmd_obj and enqueue */
-+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
-+		if (cmdobj == NULL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
-+
-+		if (flags & RTW_CMDF_WAIT_ACK) {
-+			cmdobj->sctx = &sctx;
-+			rtw_sctx_init(&sctx, 2000);
-+		}
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+
-+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			rtw_sctx_wait(&sctx, __func__);
-+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status == RTW_SCTX_SUBMITTED)
-+				cmdobj->sctx = NULL;
-+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+		}
-+	}
-+exit:
-+	return res;
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+u8 rtw_tx_control_cmd(_adapter *adapter)
-+{
-+	struct cmd_obj		*ph2c;
-+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+
-+	u8 res = _SUCCESS;
-+	
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL){
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = TBTX_CONTROL_TX_WK_CID;
-+	pdrvextra_cmd_parm->type = 0;
-+	pdrvextra_cmd_parm->size = 0;
-+	pdrvextra_cmd_parm->pbuf = NULL;
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+	return res;	
-+}
-+#endif
-+
-+u8 rtw_setopmode_cmd(_adapter  *adapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct setopmode_parm *parm;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8 res = _SUCCESS;
-+
-+	/* prepare cmd parameter */
-+	parm = (struct setopmode_parm *)rtw_zmalloc(sizeof(*parm));
-+	if (parm == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	parm->mode = (u8)networktype;
-+
-+	if (flags & RTW_CMDF_DIRECTLY) {
-+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
-+		if (H2C_SUCCESS != setopmode_hdl(adapter, (u8 *)parm))
-+			res = _FAIL;
-+		rtw_mfree((u8 *)parm, sizeof(*parm));
-+	} else {
-+		/* need enqueue, prepare cmd_obj and enqueue */
-+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
-+		if (cmdobj == NULL) {
-+			res = _FAIL;
-+			rtw_mfree((u8 *)parm, sizeof(*parm));
-+			goto exit;
-+		}
-+
-+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_OPMODE);
-+
-+		if (flags & RTW_CMDF_WAIT_ACK) {
-+			cmdobj->sctx = &sctx;
-+			rtw_sctx_init(&sctx, 2000);
-+		}
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+
-+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			rtw_sctx_wait(&sctx, __func__);
-+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status == RTW_SCTX_SUBMITTED)
-+				cmdobj->sctx = NULL;
-+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+		}
-+	}
-+
-+exit:
-+	return res;
-+}
-+
-+u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool enqueue)
-+{
-+	struct cmd_obj			*ph2c;
-+	struct set_stakey_parm	*psetstakey_para;
-+	struct cmd_priv			*pcmdpriv = &padapter->cmdpriv;
-+	struct set_stakey_rsp		*psetstakey_rsp = NULL;
-+
-+	struct mlme_priv			*pmlmepriv = &padapter->mlmepriv;
-+	struct security_priv		*psecuritypriv = &padapter->securitypriv;
-+	u8 key_len =16;
-+	u8	res = _SUCCESS;
-+
-+
-+	psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));
-+	if (psetstakey_para == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	_rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
-+		psetstakey_para->algorithm = (unsigned char) psecuritypriv->dot11PrivacyAlgrthm;
-+	else
-+		GET_ENCRY_ALGO(psecuritypriv, sta, psetstakey_para->algorithm, _FALSE);
-+
-+	if ((psetstakey_para->algorithm == _GCMP_256_) || (psetstakey_para->algorithm == _CCMP_256_)) 
-+		key_len = 32;
-+
-+	if (key_type == GROUP_KEY) {
-+		_rtw_memcpy(&psetstakey_para->key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, key_len);
-+		psetstakey_para->gk = 1;
-+	} else if (key_type == UNICAST_KEY)
-+		_rtw_memcpy(&psetstakey_para->key, &sta->dot118021x_UncstKey, key_len);
-+#ifdef CONFIG_TDLS
-+	else if (key_type == TDLS_KEY) {
-+		_rtw_memcpy(&psetstakey_para->key, sta->tpk.tk, key_len);
-+		psetstakey_para->algorithm = (u8)sta->dot118021XPrivacy;
-+	}
-+#endif /* CONFIG_TDLS */
-+
-+	/* jeff: set this becasue at least sw key is ready */
-+	padapter->securitypriv.busetkipkey = _TRUE;
-+
-+	if (enqueue) {
-+		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+		if (ph2c == NULL) {
-+			rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		psetstakey_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_stakey_rsp));
-+		if (psetstakey_rsp == NULL) {
-+			rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
-+			rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, CMD_SET_STAKEY);
-+		ph2c->rsp = (u8 *) psetstakey_rsp;
-+		ph2c->rspsz = sizeof(struct set_stakey_rsp);
-+		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+	} else {
-+		set_stakey_hdl(padapter, (u8 *)psetstakey_para);
-+		rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));
-+	}
-+exit:
-+
-+
-+	return res;
-+}
-+
-+u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue)
-+{
-+	struct cmd_obj			*ph2c;
-+	struct set_stakey_parm	*psetstakey_para;
-+	struct cmd_priv			*pcmdpriv = &padapter->cmdpriv;
-+	struct set_stakey_rsp		*psetstakey_rsp = NULL;
-+	s16 cam_id = 0;
-+	u8	res = _SUCCESS;
-+
-+	if (!sta) {
-+		RTW_ERR("%s sta == NULL\n", __func__);
-+		goto exit;
-+	}
-+
-+	if (!enqueue) {
-+		while ((cam_id = rtw_camid_search(padapter, sta->cmn.mac_addr, -1, -1)) >= 0) {
-+			RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(sta->cmn.mac_addr), cam_id);
-+			clear_cam_entry(padapter, cam_id);
-+			rtw_camid_free(padapter, cam_id);
-+		}
-+	} else {
-+		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+		if (ph2c == NULL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));
-+		if (psetstakey_para == NULL) {
-+			rtw_mfree((u8 *) ph2c, sizeof(struct	cmd_obj));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		psetstakey_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_stakey_rsp));
-+		if (psetstakey_rsp == NULL) {
-+			rtw_mfree((u8 *) ph2c, sizeof(struct	cmd_obj));
-+			rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, CMD_SET_STAKEY);
-+		ph2c->rsp = (u8 *) psetstakey_rsp;
-+		ph2c->rspsz = sizeof(struct set_stakey_rsp);
-+
-+		_rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN);
-+
-+		psetstakey_para->algorithm = _NO_PRIVACY_;
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+	}
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr)
-+{
-+	struct cmd_priv		*pcmdpriv = &padapter->cmdpriv;
-+	struct cmd_obj		*ph2c;
-+	struct addBaReq_parm	*paddbareq_parm;
-+
-+	u8	res = _SUCCESS;
-+
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	paddbareq_parm = (struct addBaReq_parm *)rtw_zmalloc(sizeof(struct addBaReq_parm));
-+	if (paddbareq_parm == NULL) {
-+		rtw_mfree((unsigned char *)ph2c, sizeof(struct	cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	paddbareq_parm->tid = tid;
-+	_rtw_memcpy(paddbareq_parm->addr, addr, ETH_ALEN);
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, paddbareq_parm, CMD_ADD_BAREQ);
-+
-+	/* RTW_INFO("rtw_addbareq_cmd, tid=%d\n", tid); */
-+
-+	/* rtw_enqueue_cmd(pcmdpriv, ph2c);	 */
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq)
-+{
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+	struct cmd_obj *ph2c;
-+	struct addBaRsp_parm *paddBaRsp_parm;
-+	u8 res = _SUCCESS;
-+
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	paddBaRsp_parm = (struct addBaRsp_parm *)rtw_zmalloc(sizeof(struct addBaRsp_parm));
-+
-+	if (paddBaRsp_parm == NULL) {
-+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	_rtw_memcpy(paddBaRsp_parm->addr, addr, ETH_ALEN);
-+	paddBaRsp_parm->tid = tid;
-+	paddBaRsp_parm->status = status;
-+	paddBaRsp_parm->size = size;
-+	paddBaRsp_parm->start_seq = start_seq;
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, paddBaRsp_parm, CMD_ADD_BARSP);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+
-+
-+	return res;
-+}
-+/* add for CONFIG_IEEE80211W, none 11w can use it */
-+u8 rtw_reset_securitypriv_cmd(_adapter *padapter)
-+{
-+	struct cmd_obj		*ph2c;
-+	struct drvextra_cmd_parm  *pdrvextra_cmd_parm;
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = RESET_SECURITYPRIV;
-+	pdrvextra_cmd_parm->type = 0;
-+	pdrvextra_cmd_parm->size = 0;
-+	pdrvextra_cmd_parm->pbuf = NULL;
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+
-+	/* rtw_enqueue_cmd(pcmdpriv, ph2c);	 */
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+
-+
-+	return res;
-+
-+}
-+
-+void free_assoc_resources_hdl(_adapter *padapter, u8 lock_scanned_queue)
-+{
-+	rtw_free_assoc_resources(padapter, lock_scanned_queue);
-+}
-+
-+u8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int flags)
-+{
-+	struct cmd_obj *cmd;
-+	struct drvextra_cmd_parm  *pdrvextra_cmd_parm;
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8	res = _SUCCESS;
-+
-+	if (flags & RTW_CMDF_DIRECTLY) {
-+		free_assoc_resources_hdl(padapter, lock_scanned_queue);
-+	}
-+	else {
-+		cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+		if (cmd == NULL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+		if (pdrvextra_cmd_parm == NULL) {
-+			rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		pdrvextra_cmd_parm->ec_id = FREE_ASSOC_RESOURCES;
-+		pdrvextra_cmd_parm->type = lock_scanned_queue;
-+		pdrvextra_cmd_parm->size = 0;
-+		pdrvextra_cmd_parm->pbuf = NULL;
-+
-+		init_h2fwcmd_w_parm_no_rsp(cmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+		if (flags & RTW_CMDF_WAIT_ACK) {
-+			cmd->sctx = &sctx;
-+			rtw_sctx_init(&sctx, 2000);
-+		}
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, cmd);
-+
-+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			rtw_sctx_wait(&sctx, __func__);
-+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status == RTW_SCTX_SUBMITTED)
-+				cmd->sctx = NULL;
-+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+		}
-+	}
-+exit:
-+	return res;
-+
-+}
-+
-+u8 rtw_dynamic_chk_wk_cmd(_adapter *padapter)
-+{
-+	struct cmd_obj		*ph2c;
-+	struct drvextra_cmd_parm  *pdrvextra_cmd_parm;
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+
-+
-+	/* only  primary padapter does this cmd */
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = DYNAMIC_CHK_WK_CID;
-+	pdrvextra_cmd_parm->type = 0;
-+	pdrvextra_cmd_parm->size = 0;
-+	pdrvextra_cmd_parm->pbuf = NULL;
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+
-+	/* rtw_enqueue_cmd(pcmdpriv, ph2c);	 */
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+
-+
-+	return res;
-+
-+}
-+
-+u8 rtw_iqk_cmd(_adapter *padapter, u8 flags)
-+{
-+	struct cmd_obj *pcmdobj;
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8 res = _SUCCESS;
-+
-+	if (flags & RTW_CMDF_DIRECTLY) {
-+		/* no need to enqueue, do the cmd hdl */
-+		rtw_iqk_hdl(padapter, NULL);
-+	} else {
-+		/* need enqueue, prepare cmd_obj and enqueue */
-+		pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
-+		if (pcmdobj == NULL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		init_h2fwcmd_w_parm_no_parm_rsp(pcmdobj, CMD_DO_IQK);
-+
-+		if (flags & RTW_CMDF_WAIT_ACK) {
-+			pcmdobj->sctx = &sctx;
-+			rtw_sctx_init(&sctx, 10 * 1000);
-+		}
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
-+
-+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			rtw_sctx_wait(&sctx, __func__);
-+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status == RTW_SCTX_SUBMITTED)
-+				pcmdobj->sctx = NULL;
-+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+		}
-+	}
-+
-+exit:
-+
-+	return res;
-+}
-+
-+u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags)
-+{
-+	struct cmd_obj *pcmdobj;
-+	struct set_ch_parm *set_ch_parm;
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8 res = _SUCCESS;
-+
-+
-+	RTW_INFO(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n",
-+		 FUNC_NDEV_ARG(padapter->pnetdev), ch, bw, ch_offset);
-+
-+	/* check input parameter */
-+
-+	/* prepare cmd parameter */
-+	set_ch_parm = (struct set_ch_parm *)rtw_zmalloc(sizeof(*set_ch_parm));
-+	if (set_ch_parm == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	set_ch_parm->ch = ch;
-+	set_ch_parm->bw = bw;
-+	set_ch_parm->ch_offset = ch_offset;
-+
-+	if (flags & RTW_CMDF_DIRECTLY) {
-+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
-+		if (H2C_SUCCESS != rtw_set_chbw_hdl(padapter, (u8 *)set_ch_parm))
-+			res = _FAIL;
-+
-+		rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm));
-+	} else {
-+		/* need enqueue, prepare cmd_obj and enqueue */
-+		pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
-+		if (pcmdobj == NULL) {
-+			rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		init_h2fwcmd_w_parm_no_rsp(pcmdobj, set_ch_parm, CMD_SET_CHANNEL);
-+
-+		if (flags & RTW_CMDF_WAIT_ACK) {
-+			pcmdobj->sctx = &sctx;
-+			rtw_sctx_init(&sctx, 10 * 1000);
-+		}
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
-+
-+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			rtw_sctx_wait(&sctx, __func__);
-+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status == RTW_SCTX_SUBMITTED)
-+				pcmdobj->sctx = NULL;
-+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+		}
-+	}
-+
-+	/* do something based on res... */
-+
-+exit:
-+
-+	RTW_INFO(FUNC_NDEV_FMT" res:%u\n", FUNC_NDEV_ARG(padapter->pnetdev), res);
-+
-+
-+	return res;
-+}
-+
-+static u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const struct country_chplan *country_ent, enum regd_src_t regd_src, u8 swconfig)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct	SetChannelPlan_param *parm;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8 res = _SUCCESS;
-+
-+	/* check if allow software config */
-+	if (swconfig && rtw_hal_is_disable_sw_channel_plan(adapter) == _TRUE) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	/* if country_entry is provided, replace chplan */
-+	if (country_ent)
-+		chplan = country_ent->chplan;
-+
-+	/* check input parameter */
-+	if (regd_src == REGD_SRC_RTK_PRIV && !rtw_is_channel_plan_valid(chplan)) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	/* prepare cmd parameter */
-+	parm = (struct SetChannelPlan_param *)rtw_zmalloc(sizeof(*parm));
-+	if (parm == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	parm->regd_src = regd_src;
-+	parm->country_ent = country_ent;
-+	parm->channel_plan = chplan;
-+
-+	if (flags & RTW_CMDF_DIRECTLY) {
-+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
-+		if (H2C_SUCCESS != rtw_set_chplan_hdl(adapter, (u8 *)parm))
-+			res = _FAIL;
-+		rtw_mfree((u8 *)parm, sizeof(*parm));
-+	} else {
-+		/* need enqueue, prepare cmd_obj and enqueue */
-+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
-+		if (cmdobj == NULL) {
-+			res = _FAIL;
-+			rtw_mfree((u8 *)parm, sizeof(*parm));
-+			goto exit;
-+		}
-+
-+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_CHANPLAN);
-+
-+		if (flags & RTW_CMDF_WAIT_ACK) {
-+			cmdobj->sctx = &sctx;
-+			rtw_sctx_init(&sctx, 2000);
-+		}
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+
-+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			rtw_sctx_wait(&sctx, __func__);
-+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status == RTW_SCTX_SUBMITTED)
-+				cmdobj->sctx = NULL;
-+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
-+				res = _FAIL;
-+		}
-+
-+		/* allow set channel plan when cmd_thread is not running */
-+		if (res != _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			parm = (struct SetChannelPlan_param *)rtw_zmalloc(sizeof(*parm));
-+			if (parm == NULL) {
-+				res = _FAIL;
-+				goto exit;
-+			}
-+			parm->regd_src = regd_src;
-+			parm->country_ent = country_ent;
-+			parm->channel_plan = chplan;
-+
-+			if (H2C_SUCCESS != rtw_set_chplan_hdl(adapter, (u8 *)parm))
-+				res = _FAIL;
-+			else
-+				res = _SUCCESS;
-+			rtw_mfree((u8 *)parm, sizeof(*parm));
-+		}
-+	}
-+
-+exit:
-+	return res;
-+}
-+
-+inline u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig)
-+{
-+	return _rtw_set_chplan_cmd(adapter, flags, chplan, NULL, REGD_SRC_RTK_PRIV, swconfig);
-+}
-+
-+inline u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig)
-+{
-+	const struct country_chplan *ent;
-+
-+	if (is_alpha(country_code[0]) == _FALSE
-+	    || is_alpha(country_code[1]) == _FALSE
-+	   ) {
-+		RTW_PRINT("%s input country_code is not alpha2\n", __func__);
-+		return _FAIL;
-+	}
-+
-+	ent = rtw_get_chplan_from_country(country_code);
-+
-+	if (ent == NULL) {
-+		RTW_PRINT("%s unsupported country_code:\"%c%c\"\n", __func__, country_code[0], country_code[1]);
-+		return _FAIL;
-+	}
-+
-+	RTW_PRINT("%s country_code:\"%c%c\" mapping to chplan:0x%02x\n", __func__, country_code[0], country_code[1], ent->chplan);
-+
-+	return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_UNSPECIFIED, ent, REGD_SRC_RTK_PRIV, swconfig);
-+}
-+
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+inline u8 rtw_sync_os_regd_cmd(_adapter *adapter, int flags, const char *country_code, u8 dfs_region)
-+{
-+	struct country_chplan *ent;
-+	const struct country_chplan *rtk_ent;
-+
-+	/* allocate entry for regd source out of driver */
-+	ent = rtw_malloc(sizeof(*ent));
-+	if (ent == NULL)
-+		return _FAIL;
-+
-+	rtk_ent = rtw_get_chplan_from_country(country_code);
-+
-+	_rtw_memcpy(ent->alpha2, country_code, 2);
-+
-+	/*
-+	* Regulation follows OS, the internal txpwr limit selection is searched by alpha2
-+	*     "00" => WW, others use string mapping
-+	* When  no matching txpwr limit selection is found, use
-+	*     1. txpwr lmit selection associated with alpha2 inside driver regulation database
-+	*     2. WW when driver has no support of this alpha2
-+	*/
-+
-+	ent->chplan = rtk_ent ? rtk_ent->chplan : RTW_CHPLAN_UNSPECIFIED;
-+	#ifdef CONFIG_80211AC_VHT
-+	ent->en_11ac = 1;
-+	#endif
-+
-+	/* TODO: dfs_region */
-+
-+	return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_UNSPECIFIED, ent, REGD_SRC_OS, 1);
-+}
-+#endif /* CONFIG_REGD_SRC_FROM_OS */
-+
-+u8 rtw_get_chplan_cmd(_adapter *adapter, int flags, struct get_chplan_resp **resp)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct get_channel_plan_param *parm;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8 res = _FAIL;
-+
-+	if (!(flags & (RTW_CMDF_DIRECTLY | RTW_CMDF_WAIT_ACK)))
-+		goto exit;
-+
-+	/* prepare cmd parameter */
-+	parm = rtw_zmalloc(sizeof(*parm));
-+	if (parm == NULL)
-+		goto exit;
-+	parm->resp = resp;
-+
-+	if (flags & RTW_CMDF_DIRECTLY) {
-+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
-+		if (H2C_SUCCESS == rtw_get_chplan_hdl(adapter, (u8 *)parm))
-+			res = _SUCCESS;
-+		rtw_mfree((u8 *)parm, sizeof(*parm));
-+	} else {
-+		/* need enqueue, prepare cmd_obj and enqueue */
-+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
-+		if (cmdobj == NULL) {
-+			rtw_mfree((u8 *)parm, sizeof(*parm));
-+			goto exit;
-+		}
-+
-+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_GET_CHANPLAN);
-+
-+		if (flags & RTW_CMDF_WAIT_ACK) {
-+			cmdobj->sctx = &sctx;
-+			rtw_sctx_init(&sctx, 2000);
-+		}
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+
-+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			rtw_sctx_wait(&sctx, __func__);
-+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status == RTW_SCTX_SUBMITTED)
-+				cmdobj->sctx = NULL;
-+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
-+				res = _FAIL;
-+		}
-+
-+		/* allow get channel plan when cmd_thread is not running */
-+		if (res != _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			parm = rtw_zmalloc(sizeof(*parm));
-+			if (parm == NULL)
-+				goto exit;
-+			parm->resp = resp;
-+
-+			if (H2C_SUCCESS == rtw_get_chplan_hdl(adapter, (u8 *)parm))
-+				res = _SUCCESS;
-+
-+			rtw_mfree((u8 *)parm, sizeof(*parm));
-+		}
-+	}
-+
-+exit:
-+	return res;
-+}
-+
-+u8 rtw_led_blink_cmd(_adapter *padapter, void *pLed)
-+{
-+	struct	cmd_obj	*pcmdobj;
-+	struct	LedBlink_param *ledBlink_param;
-+	struct	cmd_priv   *pcmdpriv = &padapter->cmdpriv;
-+
-+	u8	res = _SUCCESS;
-+
-+
-+
-+	pcmdobj = (struct	cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
-+	if (pcmdobj == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	ledBlink_param = (struct	LedBlink_param *)rtw_zmalloc(sizeof(struct	LedBlink_param));
-+	if (ledBlink_param == NULL) {
-+		rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	ledBlink_param->pLed = pLed;
-+
-+	init_h2fwcmd_w_parm_no_rsp(pcmdobj, ledBlink_param, CMD_LEDBLINK);
-+	res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+u8 rtw_set_csa_cmd(_adapter *adapter)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+
-+	cmdobj = rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (cmdobj == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	init_h2fwcmd_w_parm_no_parm_rsp(cmdobj, CMD_SET_CHANSWITCH);
-+	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
-+
-+exit:
-+	return res;
-+}
-+
-+u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option)
-+{
-+	u8 res = _SUCCESS;
-+#ifdef CONFIG_TDLS
-+	struct	cmd_obj	*pcmdobj;
-+	struct	TDLSoption_param	*TDLSoption;
-+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct	cmd_priv   *pcmdpriv = &padapter->cmdpriv;
-+
-+	pcmdobj = (struct	cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
-+	if (pcmdobj == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	TDLSoption = (struct TDLSoption_param *)rtw_zmalloc(sizeof(struct TDLSoption_param));
-+	if (TDLSoption == NULL) {
-+		rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	_rtw_spinlock(&(padapter->tdlsinfo.cmd_lock));
-+	if (addr != NULL)
-+		_rtw_memcpy(TDLSoption->addr, addr, 6);
-+	TDLSoption->option = option;
-+	_rtw_spinunlock(&(padapter->tdlsinfo.cmd_lock));
-+	init_h2fwcmd_w_parm_no_rsp(pcmdobj, TDLSoption, CMD_TDLS);
-+	res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
-+
-+exit:
-+#endif /* CONFIG_TDLS */
-+
-+	return res;
-+}
-+
-+u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter)
-+{
-+	struct cmd_obj *ph2c;
-+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = EN_HW_UPDATE_TSF_WK_CID;
-+	pdrvextra_cmd_parm->type = 0;
-+	pdrvextra_cmd_parm->size = 0;
-+	pdrvextra_cmd_parm->pbuf = NULL;
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+	return res;
-+}
-+
-+u8 rtw_periodic_tsf_update_end_cmd(_adapter *adapter)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *parm;
-+	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
-+	u8 res = _SUCCESS;
-+
-+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (cmdobj == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (parm == NULL) {
-+		rtw_mfree((unsigned char *)cmdobj, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	parm->ec_id = PERIOD_TSF_UPDATE_END_WK_CID;
-+	parm->type = 0;
-+	parm->size = 0;
-+	parm->pbuf = NULL;
-+
-+	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
-+
-+exit:
-+	return res;
-+}
-+u8 rtw_ssmps_wk_hdl(_adapter *adapter, struct ssmps_cmd_parm *ssmp_param)
-+{
-+	u8 res = _SUCCESS;
-+	struct sta_info *sta = ssmp_param->sta;
-+	u8 smps = ssmp_param->smps;
-+
-+	if (sta == NULL)
-+		return _FALSE;
-+
-+	if (smps)
-+		rtw_ssmps_enter(adapter, sta);
-+	else
-+		rtw_ssmps_leave(adapter, sta);
-+	return res;
-+}
-+
-+u8 rtw_ssmps_wk_cmd(_adapter *adapter, struct sta_info *sta, u8 smps, u8 enqueue)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *cmd_parm;
-+	struct ssmps_cmd_parm *ssmp_param;
-+	struct cmd_priv	*pcmdpriv = &adapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+
-+	if (enqueue) {
-+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+		if (cmdobj == NULL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+		if (cmd_parm == NULL) {
-+			rtw_mfree((unsigned char *)cmdobj, sizeof(struct cmd_obj));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		ssmp_param = (struct ssmps_cmd_parm *)rtw_zmalloc(sizeof(struct ssmps_cmd_parm));
-+		if (ssmp_param == NULL) {
-+			rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+			rtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		ssmp_param->smps = smps;
-+		ssmp_param->sta = sta;
-+
-+		cmd_parm->ec_id = SSMPS_WK_CID;
-+		cmd_parm->type = 0;
-+		cmd_parm->size = sizeof(struct ssmps_cmd_parm);
-+		cmd_parm->pbuf = (u8 *)ssmp_param;
-+
-+		init_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+	} else {
-+		struct ssmps_cmd_parm tmp_ssmp_param;
-+
-+		tmp_ssmp_param.smps = smps;
-+		tmp_ssmp_param.sta = sta;
-+		rtw_ssmps_wk_hdl(adapter, &tmp_ssmp_param);
-+	}
-+
-+exit:
-+	return res;
-+}
-+
-+#ifdef CONFIG_SUPPORT_STATIC_SMPS
-+u8 _ssmps_chk_by_tp(_adapter *adapter, u8 from_timer)
-+{
-+	u8 enter_smps = _FALSE;
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+	struct sta_info *psta;
-+	u32 tx_tp_mbits, rx_tp_mbits;
-+
-+	if (!MLME_IS_STA(adapter) ||
-+		!hal_is_mimo_support(adapter) ||
-+		!pmlmeext->ssmps_en ||
-+		(pmlmeext->cur_channel > 14)
-+	)
-+		return enter_smps;
-+
-+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
-+	if (psta == NULL) {
-+		RTW_ERR(ADPT_FMT" sta == NULL\n", ADPT_ARG(adapter));
-+		rtw_warn_on(1);
-+		return enter_smps;
-+	}
-+
-+	if (psta->cmn.mimo_type == RF_1T1R)
-+		return enter_smps;
-+
-+	tx_tp_mbits = psta->sta_stats.tx_tp_kbits >> 10;
-+	rx_tp_mbits = psta->sta_stats.rx_tp_kbits >> 10;
-+
-+	#ifdef DBG_STATIC_SMPS
-+	if (pmlmeext->ssmps_test) {
-+		enter_smps = (pmlmeext->ssmps_test_en == 1) ? _TRUE : _FALSE;
-+	}
-+	else
-+	#endif
-+	{
-+		if ((tx_tp_mbits <= pmlmeext->ssmps_tx_tp_th) &&
-+			(rx_tp_mbits <= pmlmeext->ssmps_rx_tp_th))
-+			enter_smps = _TRUE;
-+		else
-+			enter_smps = _FALSE;
-+	}
-+
-+	if (1) {
-+		RTW_INFO(FUNC_ADPT_FMT" tx_tp:%d [%d], rx_tp:%d [%d] , SSMPS enter :%s\n",
-+			FUNC_ADPT_ARG(adapter),
-+			tx_tp_mbits, pmlmeext->ssmps_tx_tp_th,
-+			rx_tp_mbits, pmlmeext->ssmps_rx_tp_th,
-+			(enter_smps == _TRUE) ? "True" : "False");
-+		#ifdef DBG_STATIC_SMPS
-+		RTW_INFO(FUNC_ADPT_FMT" test:%d test_en:%d\n",
-+			FUNC_ADPT_ARG(adapter),
-+			pmlmeext->ssmps_test,
-+			pmlmeext->ssmps_test_en);
-+		#endif
-+	}
-+
-+	if (enter_smps) {
-+		if (!from_timer && psta->cmn.sm_ps != SM_PS_STATIC)
-+			rtw_ssmps_enter(adapter, psta);
-+	} else {
-+		if (!from_timer && psta->cmn.sm_ps != SM_PS_DISABLE)
-+			rtw_ssmps_leave(adapter, psta);
-+		else {
-+			u8 ps_change = _FALSE;
-+
-+			if (enter_smps && psta->cmn.sm_ps != SM_PS_STATIC)
-+				ps_change = _TRUE;
-+			else if (!enter_smps && psta->cmn.sm_ps != SM_PS_DISABLE)
-+				ps_change = _TRUE;
-+
-+			if (ps_change)
-+				rtw_ssmps_wk_cmd(adapter, psta, enter_smps, 1);
-+		}
-+	}
-+
-+	return enter_smps;
-+}
-+#endif /*CONFIG_SUPPORT_STATIC_SMPS*/
-+
-+#ifdef CONFIG_CTRL_TXSS_BY_TP
-+void rtw_ctrl_txss_update_mimo_type(_adapter *adapter, struct sta_info *sta)
-+{
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+
-+	pmlmeext->txss_momi_type_bk = sta->cmn.mimo_type;
-+}
-+
-+u8 rtw_ctrl_txss(_adapter *adapter, struct sta_info *sta, bool tx_1ss)
-+{
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	u8 lps_changed = _FALSE;
-+	u8 rst = _SUCCESS;
-+
-+	if (pmlmeext->txss_1ss == tx_1ss)
-+		return _FALSE;
-+
-+	if (pwrpriv->bLeisurePs && pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
-+		lps_changed = _TRUE;
-+		LPS_Leave(adapter, "LPS_CTRL_TXSS");
-+	}
-+
-+	RTW_INFO(ADPT_FMT" STA [" MAC_FMT "] set tx to %d ss\n",
-+		ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr),
-+		(tx_1ss) ? 1 : rtw_get_sta_tx_nss(adapter, sta));
-+
-+	/*ra re-registed*/
-+	sta->cmn.mimo_type = (tx_1ss) ? RF_1T1R : pmlmeext->txss_momi_type_bk;
-+	rtw_phydm_ra_registed(adapter, sta);
-+
-+	/*configure trx mode*/
-+	rtw_phydm_trx_cfg(adapter, tx_1ss);
-+	pmlmeext->txss_1ss = tx_1ss;
-+
-+	if (lps_changed)
-+		LPS_Enter(adapter, "LPS_CTRL_TXSS");
-+
-+	return rst;
-+}
-+
-+u8 rtw_ctrl_txss_wk_hdl(_adapter *adapter, struct txss_cmd_parm *txss_param)
-+{
-+	if (!txss_param->sta)
-+		return _FALSE;
-+
-+	return rtw_ctrl_txss(adapter, txss_param->sta, txss_param->tx_1ss);
-+}
-+
-+u8 rtw_ctrl_txss_wk_cmd(_adapter *adapter, struct sta_info *sta, bool tx_1ss, u8 flag)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *cmd_parm;
-+	struct txss_cmd_parm *txss_param;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8	res = _SUCCESS;
-+
-+	txss_param = (struct txss_cmd_parm *)rtw_zmalloc(sizeof(struct txss_cmd_parm));
-+	if (txss_param == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	txss_param->tx_1ss = tx_1ss;
-+	txss_param->sta = sta;
-+
-+	if (flag & RTW_CMDF_DIRECTLY) {
-+		res = rtw_ctrl_txss_wk_hdl(adapter, txss_param);
-+		rtw_mfree((u8 *)txss_param, sizeof(*txss_param));
-+	} else {
-+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+		if (cmdobj == NULL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+		if (cmd_parm == NULL) {
-+			rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		cmd_parm->ec_id = TXSS_WK_CID;
-+		cmd_parm->type = 0;
-+		cmd_parm->size = sizeof(struct txss_cmd_parm);
-+		cmd_parm->pbuf = (u8 *)txss_param;
-+
-+		init_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+		if (flag & RTW_CMDF_WAIT_ACK) {
-+			cmdobj->sctx = &sctx;
-+			rtw_sctx_init(&sctx, 10 * 1000);
-+		}
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+		if (res == _SUCCESS && (flag & RTW_CMDF_WAIT_ACK)) {
-+			rtw_sctx_wait(&sctx, __func__);
-+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status == RTW_SCTX_SUBMITTED)
-+				cmdobj->sctx = NULL;
-+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
-+				res = _FAIL;
-+		}
-+	}
-+
-+exit:
-+	return res;
-+}
-+
-+void rtw_ctrl_tx_ss_by_tp(_adapter *adapter, u8 from_timer)
-+{
-+	bool tx_1ss  = _FALSE; /*change tx from 2ss to 1ss*/
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+	struct sta_info *psta;
-+	u32 tx_tp_mbits;
-+
-+	if (!MLME_IS_STA(adapter) ||
-+		!hal_is_mimo_support(adapter) ||
-+		!pmlmeext->txss_ctrl_en
-+	)
-+		return;
-+
-+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
-+	if (psta == NULL) {
-+		RTW_ERR(ADPT_FMT" sta == NULL\n", ADPT_ARG(adapter));
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	tx_tp_mbits = psta->sta_stats.tx_tp_kbits >> 10;
-+	if (tx_tp_mbits >= pmlmeext->txss_tp_th) {
-+		tx_1ss = _FALSE;
-+	} else {
-+		if (pmlmeext->txss_tp_chk_cnt && --pmlmeext->txss_tp_chk_cnt)
-+			tx_1ss = _FALSE;
-+		else
-+			tx_1ss = _TRUE;
-+	}
-+
-+	if (1) {
-+		RTW_INFO(FUNC_ADPT_FMT" tx_tp:%d [%d] tx_1ss(%d):%s\n",
-+			FUNC_ADPT_ARG(adapter),
-+			tx_tp_mbits, pmlmeext->txss_tp_th,
-+			pmlmeext->txss_tp_chk_cnt,
-+			(tx_1ss == _TRUE) ? "True" : "False");
-+	}
-+
-+	if (pmlmeext->txss_1ss != tx_1ss) {
-+		if (from_timer)
-+			rtw_ctrl_txss_wk_cmd(adapter, psta, tx_1ss, 0);
-+		else
-+			rtw_ctrl_txss(adapter, psta, tx_1ss);
-+	}
-+}
-+#ifdef DBG_CTRL_TXSS
-+void dbg_ctrl_txss(_adapter *adapter, bool tx_1ss)
-+{
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+	struct sta_info *psta;
-+
-+	if (!MLME_IS_STA(adapter) ||
-+		!hal_is_mimo_support(adapter)
-+	)
-+		return;
-+
-+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
-+	if (psta == NULL) {
-+		RTW_ERR(ADPT_FMT" sta == NULL\n", ADPT_ARG(adapter));
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	rtw_ctrl_txss(adapter, psta, tx_1ss);
-+}
-+#endif
-+#endif /*CONFIG_CTRL_TXSS_BY_TP*/
-+
-+#ifdef CONFIG_LPS
-+#ifdef CONFIG_LPS_CHK_BY_TP
-+#ifdef LPS_BCN_CNT_MONITOR
-+static u8 _bcn_cnt_expected(struct sta_info *psta)
-+{
-+	_adapter *adapter = psta->padapter;
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 dtim = rtw_get_bcn_dtim_period(adapter);
-+	u8 bcn_cnt = 0;
-+
-+	if ((pmlmeinfo->bcn_interval !=0) && (dtim != 0))
-+		bcn_cnt = 2000 / pmlmeinfo->bcn_interval / dtim * 4 / 5; /*2s*/
-+	if (0)
-+		RTW_INFO("%s bcn_cnt:%d\n", __func__, bcn_cnt);
-+
-+	if (bcn_cnt == 0) {
-+		RTW_ERR(FUNC_ADPT_FMT" bcn_cnt == 0\n", FUNC_ADPT_ARG(adapter));
-+		rtw_warn_on(1);
-+	}
-+
-+	return bcn_cnt;
-+}
-+#endif
-+u8 _lps_chk_by_tp(_adapter *adapter, u8 from_timer)
-+{
-+	u8 enter_ps = _FALSE;
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+	struct sta_info *psta;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	u32 tx_tp_mbits, rx_tp_mbits, bi_tp_mbits;
-+	u8 rx_bcn_cnt;
-+
-+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
-+	if (psta == NULL) {
-+		RTW_ERR(ADPT_FMT" sta == NULL\n", ADPT_ARG(adapter));
-+		rtw_warn_on(1);
-+		return enter_ps;
-+	}
-+
-+	rx_bcn_cnt = rtw_get_bcn_cnt(psta->padapter);
-+	psta->sta_stats.acc_tx_bytes = psta->sta_stats.tx_bytes;
-+	psta->sta_stats.acc_rx_bytes = psta->sta_stats.rx_bytes;
-+
-+#if 1
-+	tx_tp_mbits = psta->sta_stats.tx_tp_kbits >> 10;
-+	rx_tp_mbits = psta->sta_stats.rx_tp_kbits >> 10;
-+	bi_tp_mbits = tx_tp_mbits + rx_tp_mbits;
-+#else
-+	tx_tp_mbits = psta->sta_stats.smooth_tx_tp_kbits >> 10;
-+	rx_tp_mbits = psta->sta_stats.smooth_rx_tp_kbits >> 10;
-+	bi_tp_mbits = tx_tp_mbits + rx_tp_mbits;
-+#endif
-+
-+	if ((bi_tp_mbits >= pwrpriv->lps_bi_tp_th) ||
-+		(tx_tp_mbits >= pwrpriv->lps_tx_tp_th) ||
-+		(rx_tp_mbits >= pwrpriv->lps_rx_tp_th)) {
-+		enter_ps = _FALSE;
-+		pwrpriv->lps_chk_cnt = pwrpriv->lps_chk_cnt_th;
-+	}
-+	else {
-+#ifdef LPS_BCN_CNT_MONITOR
-+		u8 bcn_cnt = _bcn_cnt_expected(psta);
-+
-+		if (bcn_cnt && (rx_bcn_cnt < bcn_cnt)) {
-+			pwrpriv->lps_chk_cnt = 2;
-+			RTW_ERR(FUNC_ADPT_FMT" BCN_CNT:%d(%d) invalid\n",
-+				FUNC_ADPT_ARG(adapter), rx_bcn_cnt, bcn_cnt);
-+		}
-+#endif
-+
-+		if (pwrpriv->lps_chk_cnt && --pwrpriv->lps_chk_cnt)
-+			enter_ps = _FALSE;
-+		else
-+			enter_ps = _TRUE;
-+	}
-+
-+	if (1) {
-+		RTW_INFO(FUNC_ADPT_FMT" tx_tp:%d [%d], rx_tp:%d [%d], bi_tp:%d [%d], enter_ps(%d):%s\n",
-+			FUNC_ADPT_ARG(adapter),
-+			tx_tp_mbits, pwrpriv->lps_tx_tp_th,
-+			rx_tp_mbits, pwrpriv->lps_rx_tp_th,
-+			bi_tp_mbits, pwrpriv->lps_bi_tp_th,
-+			pwrpriv->lps_chk_cnt,
-+			(enter_ps == _TRUE) ? "True" : "False");
-+		RTW_INFO(FUNC_ADPT_FMT" tx_pkt_cnt :%d [%d], rx_pkt_cnt :%d [%d]\n",
-+			FUNC_ADPT_ARG(adapter),
-+			pmlmepriv->LinkDetectInfo.NumTxOkInPeriod,
-+			pwrpriv->lps_tx_pkts,
-+			pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod,
-+			pwrpriv->lps_rx_pkts);
-+		if (!adapter->bsta_tp_dump)
-+			RTW_INFO(FUNC_ADPT_FMT" bcn_cnt:%d (per-%d second)\n",
-+			FUNC_ADPT_ARG(adapter),
-+			rx_bcn_cnt,
-+			2);
-+	}
-+
-+	if (enter_ps) {
-+		if (!from_timer)
-+			LPS_Enter(adapter, "TRAFFIC_IDLE");
-+	} else {
-+		if (!from_timer)
-+			LPS_Leave(adapter, "TRAFFIC_BUSY");
-+		else {
-+			#ifdef CONFIG_CONCURRENT_MODE
-+			#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
-+			if (adapter->hw_port == HW_PORT0)
-+			#endif
-+			#endif
-+				rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_TRAFFIC_BUSY, 0);
-+		}
-+	}
-+
-+	return enter_ps;
-+}
-+#endif
-+
-+static u8 _lps_chk_by_pkt_cnts(_adapter *padapter, u8 from_timer, u8 bBusyTraffic)
-+{		
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	u8	bEnterPS = _FALSE;
-+
-+	/* check traffic for  powersaving. */
-+	if (((pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) > 8) ||
-+		#ifdef CONFIG_LPS_SLOW_TRANSITION
-+		(pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 2)
-+		#else /* CONFIG_LPS_SLOW_TRANSITION */
-+		(pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 4)
-+		#endif /* CONFIG_LPS_SLOW_TRANSITION */
-+	) {
-+		#ifdef DBG_RX_COUNTER_DUMP
-+		if (padapter->dump_rx_cnt_mode & DUMP_DRV_TRX_COUNTER_DATA)
-+			RTW_INFO("(-)Tx = %d, Rx = %d\n", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod, pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);
-+		#endif
-+
-+		bEnterPS = _FALSE;
-+		#ifdef CONFIG_LPS_SLOW_TRANSITION
-+		if (bBusyTraffic == _TRUE) {
-+			if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount <= 4)
-+				pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 4;
-+
-+			pmlmepriv->LinkDetectInfo.TrafficTransitionCount++;
-+
-+			/* RTW_INFO("Set TrafficTransitionCount to %d\n", pmlmepriv->LinkDetectInfo.TrafficTransitionCount); */
-+
-+			if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount > 30/*TrafficTransitionLevel*/)
-+				pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 30;
-+		}
-+		#endif /* CONFIG_LPS_SLOW_TRANSITION */
-+	} else {
-+		#ifdef DBG_RX_COUNTER_DUMP
-+		if (padapter->dump_rx_cnt_mode & DUMP_DRV_TRX_COUNTER_DATA)
-+			RTW_INFO("(+)Tx = %d, Rx = %d\n", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod, pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);
-+		#endif
-+
-+		#ifdef CONFIG_LPS_SLOW_TRANSITION
-+		if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount >= 2)
-+			pmlmepriv->LinkDetectInfo.TrafficTransitionCount -= 2;
-+		else
-+			pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;
-+
-+		if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount == 0)
-+			bEnterPS = _TRUE;
-+		#else /* CONFIG_LPS_SLOW_TRANSITION */
-+			bEnterPS = _TRUE;
-+		#endif /* CONFIG_LPS_SLOW_TRANSITION */
-+	}
-+
-+	#ifdef CONFIG_DYNAMIC_DTIM
-+	if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount == 8)
-+		bEnterPS = _FALSE;
-+
-+	RTW_INFO("LowPowerTransitionCount=%d\n", pmlmepriv->LinkDetectInfo.LowPowerTransitionCount);
-+	#endif /* CONFIG_DYNAMIC_DTIM */
-+
-+	/* LeisurePS only work in infra mode. */
-+	if (bEnterPS) {
-+		if (!from_timer) {
-+			#ifdef CONFIG_DYNAMIC_DTIM
-+			if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount < 8)
-+				adapter_to_pwrctl(padapter)->dtim = 1;
-+			else
-+				adapter_to_pwrctl(padapter)->dtim = 3;
-+			#endif /* CONFIG_DYNAMIC_DTIM */
-+			LPS_Enter(padapter, "TRAFFIC_IDLE");
-+		} else {
-+			/* do this at caller */
-+			/* rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_ENTER, 0); */
-+			/* rtw_hal_dm_watchdog_in_lps(padapter); */
-+		}
-+
-+		#ifdef CONFIG_DYNAMIC_DTIM
-+		if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)
-+			pmlmepriv->LinkDetectInfo.LowPowerTransitionCount++;
-+		#endif /* CONFIG_DYNAMIC_DTIM */
-+	} else {
-+		#ifdef CONFIG_DYNAMIC_DTIM
-+		if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount != 8)
-+			pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;
-+		else
-+			pmlmepriv->LinkDetectInfo.LowPowerTransitionCount++;
-+		#endif /* CONFIG_DYNAMIC_DTIM */
-+
-+		if (!from_timer)
-+			LPS_Leave(padapter, "TRAFFIC_BUSY");
-+		else {
-+			#ifdef CONFIG_CONCURRENT_MODE
-+			#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
-+			if (padapter->hw_port == HW_PORT0)
-+			#endif
-+			#endif
-+				rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_TRAFFIC_BUSY, 0);
-+		}
-+	}
-+
-+	return bEnterPS;
-+}
-+#endif /* CONFIG_LPS */
-+
-+/* from_timer == 1 means driver is in LPS */
-+u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer)
-+{
-+	u8	bEnterPS = _FALSE;
-+	u16 BusyThresholdHigh;
-+	u16	BusyThresholdLow;
-+	u16	BusyThreshold;
-+	u8	bBusyTraffic = _FALSE, bTxBusyTraffic = _FALSE, bRxBusyTraffic = _FALSE;
-+	u8	bHigherBusyTraffic = _FALSE, bHigherBusyRxTraffic = _FALSE, bHigherBusyTxTraffic = _FALSE;
-+
-+	struct mlme_priv		*pmlmepriv = &(padapter->mlmepriv);
-+#ifdef CONFIG_TDLS
-+	struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo);
-+	struct tdls_txmgmt txmgmt;
-+	u8 baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
-+#endif /* CONFIG_TDLS */
-+#ifdef CONFIG_TRAFFIC_PROTECT
-+	RT_LINK_DETECT_T *link_detect = &pmlmepriv->LinkDetectInfo;
-+#endif
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if (padapter->registrypriv.wifi_spec != 1) {
-+		BusyThresholdHigh = 25;
-+		BusyThresholdLow = 10;
-+	} else
-+#endif /* CONFIG_BT_COEXIST */
-+	{
-+		BusyThresholdHigh = 100;
-+		BusyThresholdLow = 75;
-+	}
-+	BusyThreshold = BusyThresholdHigh;
-+
-+
-+	/*  */
-+	/* Determine if our traffic is busy now */
-+	/*  */
-+	if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+	    /*&& !MgntInitAdapterInProgress(pMgntInfo)*/) {
-+		/* if we raise bBusyTraffic in last watchdog, using lower threshold. */
-+		if (pmlmepriv->LinkDetectInfo.bBusyTraffic)
-+			BusyThreshold = BusyThresholdLow;
-+
-+		if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > BusyThreshold ||
-+		    pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > BusyThreshold) {
-+			bBusyTraffic = _TRUE;
-+
-+			if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > pmlmepriv->LinkDetectInfo.NumTxOkInPeriod)
-+				bRxBusyTraffic = _TRUE;
-+			else
-+				bTxBusyTraffic = _TRUE;
-+		}
-+
-+		/* Higher Tx/Rx data. */
-+		if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > 4000 ||
-+		    pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > 4000) {
-+			bHigherBusyTraffic = _TRUE;
-+
-+			if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > pmlmepriv->LinkDetectInfo.NumTxOkInPeriod)
-+				bHigherBusyRxTraffic = _TRUE;
-+			else
-+				bHigherBusyTxTraffic = _TRUE;
-+		}
-+
-+#ifdef CONFIG_TRAFFIC_PROTECT
-+#define TX_ACTIVE_TH 10
-+#define RX_ACTIVE_TH 20
-+#define TRAFFIC_PROTECT_PERIOD_MS 4500
-+
-+		if (link_detect->NumTxOkInPeriod > TX_ACTIVE_TH
-+		    || link_detect->NumRxUnicastOkInPeriod > RX_ACTIVE_TH) {
-+
-+			RTW_INFO(FUNC_ADPT_FMT" acqiure wake_lock for %u ms(tx:%d,rx_unicast:%d)\n",
-+				 FUNC_ADPT_ARG(padapter),
-+				 TRAFFIC_PROTECT_PERIOD_MS,
-+				 link_detect->NumTxOkInPeriod,
-+				 link_detect->NumRxUnicastOkInPeriod);
-+
-+			rtw_lock_traffic_suspend_timeout(TRAFFIC_PROTECT_PERIOD_MS);
-+		}
-+#endif
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_TDLS_AUTOSETUP
-+		/* TDLS_WATCHDOG_PERIOD * 2sec, periodically send */
-+		if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _TRUE) {
-+			if ((ptdlsinfo->watchdog_count % TDLS_WATCHDOG_PERIOD) == 0) {
-+				_rtw_memcpy(txmgmt.peer, baddr, ETH_ALEN);
-+				issue_tdls_dis_req(padapter, &txmgmt);
-+			}
-+			ptdlsinfo->watchdog_count++;
-+		}
-+#endif /* CONFIG_TDLS_AUTOSETUP */
-+#endif /* CONFIG_TDLS */
-+
-+#ifdef CONFIG_SUPPORT_STATIC_SMPS
-+		_ssmps_chk_by_tp(padapter, from_timer);
-+#endif
-+#ifdef CONFIG_CTRL_TXSS_BY_TP
-+		rtw_ctrl_tx_ss_by_tp(padapter, from_timer);
-+#endif
-+
-+#ifdef CONFIG_LPS
-+		if (adapter_to_pwrctl(padapter)->bLeisurePs && MLME_IS_STA(padapter)) {
-+			#ifdef CONFIG_LPS_CHK_BY_TP
-+			if (adapter_to_pwrctl(padapter)->lps_chk_by_tp)
-+				bEnterPS = _lps_chk_by_tp(padapter, from_timer);
-+			else
-+			#endif /*CONFIG_LPS_CHK_BY_TP*/
-+				bEnterPS = _lps_chk_by_pkt_cnts(padapter, from_timer, bBusyTraffic);
-+		}
-+#endif /* CONFIG_LPS */
-+
-+	} else {
-+#ifdef CONFIG_LPS
-+		if (!from_timer && rtw_mi_get_assoc_if_num(padapter) == 0)
-+			LPS_Leave(padapter, "NON_LINKED");
-+#endif
-+	}
-+
-+	session_tracker_chk_cmd(padapter, NULL);
-+
-+#ifdef CONFIG_BEAMFORMING
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+	rtw_bf_update_traffic(padapter);
-+#endif /* RTW_BEAMFORMING_VERSION_2 */
-+#endif /* CONFIG_BEAMFORMING */
-+
-+	pmlmepriv->LinkDetectInfo.NumRxOkInPeriod = 0;
-+	pmlmepriv->LinkDetectInfo.NumTxOkInPeriod = 0;
-+	pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod = 0;
-+	pmlmepriv->LinkDetectInfo.bBusyTraffic = bBusyTraffic;
-+	pmlmepriv->LinkDetectInfo.bTxBusyTraffic = bTxBusyTraffic;
-+	pmlmepriv->LinkDetectInfo.bRxBusyTraffic = bRxBusyTraffic;
-+	pmlmepriv->LinkDetectInfo.bHigherBusyTraffic = bHigherBusyTraffic;
-+	pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic = bHigherBusyRxTraffic;
-+	pmlmepriv->LinkDetectInfo.bHigherBusyTxTraffic = bHigherBusyTxTraffic;
-+
-+	return bEnterPS;
-+
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+/* for 11n Logo 4.2.31/4.2.32 */
-+static void dynamic_update_bcn_check(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+
-+	if (!padapter->registrypriv.wifi_spec)
-+		return;
-+
-+	if (!padapter->registrypriv.ht_enable || !is_supported_ht(padapter->registrypriv.wireless_mode))
-+		return;
-+
-+	if (!MLME_IS_AP(padapter))
-+		return;
-+
-+	if (pmlmeext->bstart_bss) {
-+		/* In 10 * 2 = 20s, there are no legacy AP, update HT info  */
-+		static u8 count = 1;
-+
-+		if (count % 10 == 0) {
-+			count = 1;
-+#ifdef CONFIG_80211N_HT
-+			if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc)
-+				&& _FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht)) {
-+
-+				if (rtw_ht_operation_update(padapter) > 0) {
-+					update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0);
-+					update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0);
-+				}
-+			}
-+#endif /* CONFIG_80211N_HT */
-+		}
-+
-+#ifdef CONFIG_80211N_HT
-+		/* In 2s, there are any legacy AP, update HT info, and then reset count  */
-+
-+		if (_FALSE != ATOMIC_READ(&pmlmepriv->olbc)
-+			&& _FALSE != ATOMIC_READ(&pmlmepriv->olbc_ht)) {
-+					
-+			if (rtw_ht_operation_update(padapter) > 0) {
-+				update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE, 0);
-+				update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE, 0);
-+
-+			}
-+			ATOMIC_SET(&pmlmepriv->olbc, _FALSE);
-+			ATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE);
-+			count = 0;
-+		}
-+#endif /* CONFIG_80211N_HT */
-+		count ++;
-+	}
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter)
-+{
-+	#ifdef CONFIG_AP_MODE
-+	#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-+	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
-+		expire_timeout_chk(padapter);
-+		#ifdef CONFIG_RTW_MESH
-+		if (MLME_IS_MESH(padapter) && MLME_IS_ASOC(padapter))
-+			rtw_mesh_peer_status_chk(padapter);
-+		#endif
-+	}
-+	#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
-+
-+	dynamic_update_bcn_check(padapter);
-+
-+	#endif /* CONFIG_AP_MODE */
-+
-+	linked_status_chk(padapter, 0);
-+	traffic_status_watchdog(padapter, 0);
-+
-+	/* for debug purpose */
-+	_linked_info_dump(padapter);
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
-+        rtw_cfgvendor_rssi_monitor_evt(padapter);
-+#endif
-+
-+
-+}
-+void rtw_dynamic_chk_wk_hdl(_adapter *padapter)
-+{
-+	rtw_mi_dynamic_chk_wk_hdl(padapter);
-+#ifdef CONFIG_MP_INCLUDED
-+	if (rtw_mp_mode_check(padapter) == _FALSE)
-+#endif
-+	{
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+		rtw_hal_sreset_xmit_status_check(padapter);
-+		rtw_hal_sreset_linked_status_check(padapter);
-+#endif
-+	}
-+
-+	/* if(check_fwstate(pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_SURVEY)==_FALSE) */
-+	{
-+#ifdef DBG_RX_COUNTER_DUMP
-+		rtw_dump_rx_counters(padapter);
-+#endif
-+		dm_DynamicUsbTxAgg(padapter, 0);
-+	}
-+	rtw_hal_dm_watchdog(padapter);
-+
-+	/* check_hw_pbc(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type); */
-+
-+#ifdef CONFIG_BT_COEXIST
-+	/* BT-Coexist */
-+	rtw_btcoex_Handler(padapter);
-+#endif
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+	rtw_ch_util_rpt(padapter);
-+#endif
-+
-+#ifdef CONFIG_DFS_MASTER
-+	rtw_chset_chk_non_ocp_finish(adapter_to_rfctl(padapter));
-+#endif
-+
-+#ifdef CONFIG_IPS_CHECK_IN_WD
-+	/* always call rtw_ps_processor() at last one. */
-+	rtw_ps_processor(padapter);
-+#endif
-+
-+#ifdef CONFIG_MCC_MODE
-+	rtw_hal_mcc_sw_status_check(padapter);
-+#endif /* CONFIG_MCC_MODE */
-+
-+	rtw_hal_periodic_tsf_update_chk(padapter);
-+}
-+
-+#ifdef CONFIG_LPS
-+struct lps_ctrl_wk_parm {
-+	s8 lps_level;
-+	#ifdef CONFIG_LPS_1T1R
-+	s8 lps_1t1r;
-+	#endif
-+};
-+
-+void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type, u8 *buf)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct lps_ctrl_wk_parm *parm = (struct lps_ctrl_wk_parm *)buf;
-+	u8	mstatus;
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)
-+	    || (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
-+		return;
-+
-+	switch (lps_ctrl_type) {
-+	case LPS_CTRL_SCAN:
-+		/* RTW_INFO("LPS_CTRL_SCAN\n"); */
-+#ifdef CONFIG_BT_COEXIST
-+		rtw_btcoex_ScanNotify(padapter, _TRUE);
-+#endif /* CONFIG_BT_COEXIST */
-+		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+			/* connect */
-+			LPS_Leave(padapter, "LPS_CTRL_SCAN");
-+		}
-+		break;
-+	case LPS_CTRL_JOINBSS:
-+		/* RTW_INFO("LPS_CTRL_JOINBSS\n"); */
-+		LPS_Leave(padapter, "LPS_CTRL_JOINBSS");
-+		break;
-+	case LPS_CTRL_CONNECT:
-+		/* RTW_INFO("LPS_CTRL_CONNECT\n"); */
-+		mstatus = 1;/* connect */
-+		/* Reset LPS Setting */
-+		pwrpriv->LpsIdleCount = 0;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));
-+#ifdef CONFIG_BT_COEXIST
-+		rtw_btcoex_MediaStatusNotify(padapter, mstatus);
-+#endif /* CONFIG_BT_COEXIST */
-+		break;
-+	case LPS_CTRL_DISCONNECT:
-+		/* RTW_INFO("LPS_CTRL_DISCONNECT\n"); */
-+		mstatus = 0;/* disconnect */
-+#ifdef CONFIG_BT_COEXIST
-+		rtw_btcoex_MediaStatusNotify(padapter, mstatus);
-+#endif /* CONFIG_BT_COEXIST */
-+		LPS_Leave(padapter, "LPS_CTRL_DISCONNECT");
-+		rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));
-+		break;
-+	case LPS_CTRL_SPECIAL_PACKET:
-+		/* RTW_INFO("LPS_CTRL_SPECIAL_PACKET\n"); */
-+		rtw_set_lps_deny(padapter, LPS_DELAY_MS);
-+#ifdef CONFIG_BT_COEXIST
-+		rtw_btcoex_SpecialPacketNotify(padapter, PACKET_DHCP);
-+#endif /* CONFIG_BT_COEXIST */
-+		LPS_Leave(padapter, "LPS_CTRL_SPECIAL_PACKET");
-+		break;
-+	case LPS_CTRL_LEAVE:
-+		LPS_Leave(padapter, "LPS_CTRL_LEAVE");
-+		break;
-+	case LPS_CTRL_LEAVE_SET_OPTION:
-+		LPS_Leave(padapter, "LPS_CTRL_LEAVE_SET_OPTION");
-+		if (parm) {
-+			if (parm->lps_level >= 0)
-+				pwrpriv->lps_level = parm->lps_level;
-+			#ifdef CONFIG_LPS_1T1R
-+			if (parm->lps_1t1r >= 0)
-+				pwrpriv->lps_1t1r = parm->lps_1t1r;
-+			#endif
-+		}
-+		break;
-+	case LPS_CTRL_LEAVE_CFG80211_PWRMGMT:
-+		LPS_Leave(padapter, "CFG80211_PWRMGMT");
-+		break;
-+	case LPS_CTRL_TRAFFIC_BUSY:
-+		LPS_Leave(padapter, "LPS_CTRL_TRAFFIC_BUSY");
-+		break;
-+	case LPS_CTRL_TX_TRAFFIC_LEAVE:
-+		LPS_Leave(padapter, "LPS_CTRL_TX_TRAFFIC_LEAVE");
-+		break;
-+	case LPS_CTRL_RX_TRAFFIC_LEAVE:
-+		LPS_Leave(padapter, "LPS_CTRL_RX_TRAFFIC_LEAVE");
-+		break;
-+	case LPS_CTRL_ENTER:
-+		LPS_Enter(padapter, "TRAFFIC_IDLE_1");
-+		break;
-+	default:
-+		break;
-+	}
-+
-+}
-+
-+static u8 _rtw_lps_ctrl_wk_cmd(_adapter *adapter, u8 lps_ctrl_type, s8 lps_level, s8 lps_1t1r, u8 flags)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *parm;
-+	struct lps_ctrl_wk_parm *wk_parm = NULL;
-+	struct cmd_priv	*pcmdpriv = &adapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8	res = _SUCCESS;
-+
-+	if (lps_ctrl_type == LPS_CTRL_LEAVE_SET_OPTION) {
-+		wk_parm = rtw_zmalloc(sizeof(*wk_parm));
-+		if (wk_parm == NULL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+		wk_parm->lps_level = lps_level;
-+		#ifdef CONFIG_LPS_1T1R
-+		wk_parm->lps_1t1r = lps_1t1r;
-+		#endif
-+	}
-+
-+	if (flags & RTW_CMDF_DIRECTLY) {
-+		/* no need to enqueue, do the cmd hdl directly */
-+		lps_ctrl_wk_hdl(adapter, lps_ctrl_type, (u8 *)wk_parm);
-+		if (wk_parm)
-+			rtw_mfree(wk_parm, sizeof(*wk_parm));
-+	} else {
-+		/* need enqueue, prepare cmd_obj and enqueue */
-+		parm = rtw_zmalloc(sizeof(*parm));
-+		if (parm == NULL) {
-+			if (wk_parm)
-+				rtw_mfree(wk_parm, sizeof(*wk_parm));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		parm->ec_id = LPS_CTRL_WK_CID;
-+		parm->type = lps_ctrl_type;
-+		parm->size = wk_parm ? sizeof(*wk_parm) : 0;
-+		parm->pbuf = (u8 *)wk_parm;
-+
-+		cmdobj = rtw_zmalloc(sizeof(*cmdobj));
-+		if (cmdobj == NULL) {
-+			rtw_mfree(parm, sizeof(*parm));
-+			if (wk_parm)
-+				rtw_mfree(wk_parm, sizeof(*wk_parm));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
-+
-+		if (flags & RTW_CMDF_WAIT_ACK) {
-+			cmdobj->sctx = &sctx;
-+			rtw_sctx_init(&sctx, 2000);
-+		}
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+
-+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			rtw_sctx_wait(&sctx, __func__);
-+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status == RTW_SCTX_SUBMITTED)
-+				cmdobj->sctx = NULL;
-+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
-+				res = _FAIL;
-+		}
-+	}
-+
-+exit:
-+	return res;
-+}
-+
-+u8 rtw_lps_ctrl_wk_cmd(_adapter *adapter, u8 lps_ctrl_type, u8 flags)
-+{
-+	return _rtw_lps_ctrl_wk_cmd(adapter, lps_ctrl_type, -1, -1, flags);
-+}
-+
-+u8 rtw_lps_ctrl_leave_set_level_cmd(_adapter *adapter, u8 lps_level, u8 flags)
-+{
-+	return _rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_LEAVE_SET_OPTION, lps_level, -1, flags);
-+}
-+
-+#ifdef CONFIG_LPS_1T1R
-+u8 rtw_lps_ctrl_leave_set_1t1r_cmd(_adapter *adapter, u8 lps_1t1r, u8 flags)
-+{
-+	return _rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_LEAVE_SET_OPTION, -1, lps_1t1r, flags);
-+}
-+#endif
-+
-+void rtw_dm_in_lps_hdl(_adapter *padapter)
-+{
-+	rtw_hal_set_hwreg(padapter, HW_VAR_DM_IN_LPS_LCLK, NULL);
-+}
-+
-+u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter)
-+{
-+	struct cmd_obj	*ph2c;
-+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = DM_IN_LPS_WK_CID;
-+	pdrvextra_cmd_parm->type = 0;
-+	pdrvextra_cmd_parm->size = 0;
-+	pdrvextra_cmd_parm->pbuf = NULL;
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+
-+	return res;
-+
-+}
-+
-+void rtw_lps_change_dtim_hdl(_adapter *padapter, u8 dtim)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+
-+	if (dtim <= 0 || dtim > 16)
-+		return;
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
-+		return;
-+#endif
-+
-+#ifdef CONFIG_LPS_LCLK
-+	_enter_pwrlock(&pwrpriv->lock);
-+#endif
-+
-+	if (pwrpriv->dtim != dtim) {
-+		RTW_INFO("change DTIM from %d to %d, bFwCurrentInPSMode=%d, ps_mode=%d\n", pwrpriv->dtim, dtim,
-+			 pwrpriv->bFwCurrentInPSMode, pwrpriv->pwr_mode);
-+
-+		pwrpriv->dtim = dtim;
-+	}
-+
-+	if ((pwrpriv->bFwCurrentInPSMode == _TRUE) && (pwrpriv->pwr_mode > PS_MODE_ACTIVE)) {
-+		u8 ps_mode = pwrpriv->pwr_mode;
-+
-+		/* RTW_INFO("change DTIM from %d to %d, ps_mode=%d\n", pwrpriv->dtim, dtim, ps_mode); */
-+
-+		rtw_exec_lps(padapter, ps_mode);
-+	}
-+
-+#ifdef CONFIG_LPS_LCLK
-+	_exit_pwrlock(&pwrpriv->lock);
-+#endif
-+
-+}
-+
-+#endif
-+
-+u8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim)
-+{
-+	struct cmd_obj	*ph2c;
-+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+	/*
-+	#ifdef CONFIG_CONCURRENT_MODE
-+		if (padapter->hw_port != HW_PORT0)
-+			return res;
-+	#endif
-+	*/
-+	{
-+		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+		if (ph2c == NULL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+		if (pdrvextra_cmd_parm == NULL) {
-+			rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		pdrvextra_cmd_parm->ec_id = LPS_CHANGE_DTIM_CID;
-+		pdrvextra_cmd_parm->type = dtim;
-+		pdrvextra_cmd_parm->size = 0;
-+		pdrvextra_cmd_parm->pbuf = NULL;
-+
-+		init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+	}
-+
-+exit:
-+
-+	return res;
-+
-+}
-+
-+#if (RATE_ADAPTIVE_SUPPORT == 1)
-+void rpt_timer_setting_wk_hdl(_adapter *padapter, u16 minRptTime)
-+{
-+	rtw_hal_set_hwreg(padapter, HW_VAR_RPT_TIMER_SETTING, (u8 *)(&minRptTime));
-+}
-+
-+u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime)
-+{
-+	struct cmd_obj		*ph2c;
-+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+
-+	u8	res = _SUCCESS;
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = RTP_TIMER_CFG_WK_CID;
-+	pdrvextra_cmd_parm->type = minRptTime;
-+	pdrvextra_cmd_parm->size = 0;
-+	pdrvextra_cmd_parm->pbuf = NULL;
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+exit:
-+
-+
-+	return res;
-+
-+}
-+
-+#endif
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+void antenna_select_wk_hdl(_adapter *padapter, u8 antenna)
-+{
-+	rtw_hal_set_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &antenna, _TRUE);
-+}
-+
-+u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue)
-+{
-+	struct cmd_obj		*ph2c;
-+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	u8	bSupportAntDiv = _FALSE;
-+	u8	res = _SUCCESS;
-+	int	i;
-+
-+	rtw_hal_get_def_var(padapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv));
-+	if (_FALSE == bSupportAntDiv)
-+		return _FAIL;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		if (rtw_linked_check(dvobj->padapters[i]))
-+			return _FAIL;
-+	}
-+
-+	if (_TRUE == enqueue) {
-+		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+		if (ph2c == NULL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+		if (pdrvextra_cmd_parm == NULL) {
-+			rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		pdrvextra_cmd_parm->ec_id = ANT_SELECT_WK_CID;
-+		pdrvextra_cmd_parm->type = antenna;
-+		pdrvextra_cmd_parm->size = 0;
-+		pdrvextra_cmd_parm->pbuf = NULL;
-+		init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+	} else
-+		antenna_select_wk_hdl(padapter, antenna);
-+exit:
-+
-+
-+	return res;
-+
-+}
-+#endif
-+
-+void rtw_dm_ra_mask_hdl(_adapter *padapter, struct sta_info *psta)
-+{
-+	if (psta)
-+		set_sta_rate(padapter, psta);
-+}
-+
-+u8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta)
-+{
-+	struct cmd_obj	*ph2c;
-+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = DM_RA_MSK_WK_CID;
-+	pdrvextra_cmd_parm->type = 0;
-+	pdrvextra_cmd_parm->size = 0;
-+	pdrvextra_cmd_parm->pbuf = psta;
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+
-+	return res;
-+
-+}
-+
-+void power_saving_wk_hdl(_adapter *padapter)
-+{
-+	rtw_ps_processor(padapter);
-+}
-+
-+/* add for CONFIG_IEEE80211W, none 11w can use it */
-+void reset_securitypriv_hdl(_adapter *padapter)
-+{
-+	rtw_reset_securitypriv(padapter);
-+}
-+
-+#ifdef CONFIG_P2P
-+u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType)
-+{
-+	struct cmd_obj	*ph2c;
-+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
-+		return res;
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = P2P_PROTO_WK_CID;
-+	pdrvextra_cmd_parm->type = intCmdType;	/*	As the command tppe. */
-+	pdrvextra_cmd_parm->size = 0;
-+	pdrvextra_cmd_parm->pbuf = NULL;		/*	Must be NULL here */
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+
-+
-+	return res;
-+
-+}
-+#endif /* CONFIG_P2P */
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+static struct rtw_roch_parm *rtw_alloc_roch_parm(_adapter *adapter
-+	, u64 cookie, struct wireless_dev *wdev
-+	, struct ieee80211_channel *ch, enum nl80211_channel_type ch_type
-+	, unsigned int duration
-+	, u8 flags
-+)
-+{
-+	struct rtw_roch_parm *roch_parm;
-+	bool cancel = duration ? 0 : 1;
-+
-+	roch_parm = (struct rtw_roch_parm *)rtw_zmalloc(sizeof(struct rtw_roch_parm));
-+	if (!roch_parm)
-+		return NULL;
-+
-+	roch_parm->cookie = cookie;
-+	roch_parm->wdev = wdev;
-+	if (!cancel) {
-+		_rtw_memcpy(&roch_parm->ch, ch, sizeof(struct ieee80211_channel));
-+		roch_parm->ch_type = ch_type;
-+		roch_parm->duration = duration;
-+	}
-+
-+	return roch_parm;
-+}
-+
-+inline u8 rtw_roch_cmd(_adapter *adapter
-+	, u64 cookie, struct wireless_dev *wdev
-+	, struct ieee80211_channel *ch, enum nl80211_channel_type ch_type
-+	, unsigned int duration
-+	, u8 flags
-+)
-+{
-+	struct rtw_roch_parm *roch_parm;
-+
-+	roch_parm = rtw_alloc_roch_parm(adapter, cookie, wdev, ch, ch_type, duration, flags);
-+	if (!roch_parm)
-+		return _FAIL;
-+
-+	return rtw_roch_wk_cmd(adapter, ROCH_RO_CH_WK, roch_parm, flags);
-+}
-+
-+inline u8 rtw_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags)
-+{
-+	struct rtw_roch_parm *roch_parm;
-+
-+	roch_parm = rtw_alloc_roch_parm(adapter, cookie, wdev, NULL, 0, 0, flags);
-+	if (!roch_parm)
-+		return _FAIL;
-+
-+	return rtw_roch_wk_cmd(adapter, ROCH_CANCEL_RO_CH_WK, roch_parm, flags);
-+}
-+
-+inline u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *parm;
-+	struct mgnt_tx_parm *mgnt_parm;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8	res = _SUCCESS;
-+
-+	mgnt_parm = (struct mgnt_tx_parm *)rtw_zmalloc(sizeof(struct mgnt_tx_parm));
-+	if (mgnt_parm == NULL) {
-+		res = _FAIL;
-+			goto exit;
-+	}
-+
-+	mgnt_parm->tx_ch = tx_ch;
-+	mgnt_parm->no_cck = no_cck;
-+	mgnt_parm->buf = buf;
-+	mgnt_parm->len = len;
-+	mgnt_parm->wait_ack = wait_ack;
-+
-+	if (flags & RTW_CMDF_DIRECTLY) {
-+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
-+		if (H2C_SUCCESS != rtw_mgnt_tx_handler(adapter, (u8 *)mgnt_parm))
-+			res = _FAIL;
-+		rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));
-+	} else {
-+		/* need enqueue, prepare cmd_obj and enqueue */
-+		parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+		if (parm == NULL) {
-+			rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		parm->ec_id = MGNT_TX_WK_CID;
-+		parm->type = 0;
-+		parm->size = sizeof(*mgnt_parm);
-+		parm->pbuf = (u8 *)mgnt_parm;
-+
-+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
-+		if (cmdobj == NULL) {
-+			res = _FAIL;
-+			rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));
-+			rtw_mfree((u8 *)parm, sizeof(*parm));
-+			goto exit;
-+		}
-+
-+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
-+
-+		if (flags & RTW_CMDF_WAIT_ACK) {
-+			cmdobj->sctx = &sctx;
-+			rtw_sctx_init(&sctx, 10 * 1000);
-+		}
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+
-+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			rtw_sctx_wait(&sctx, __func__);
-+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status == RTW_SCTX_SUBMITTED)
-+				cmdobj->sctx = NULL;
-+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
-+				res = _FAIL;
-+		}
-+	}
-+
-+exit:
-+	return res;
-+}
-+#endif
-+
-+u8 rtw_ps_cmd(_adapter *padapter)
-+{
-+	struct cmd_obj		*ppscmd;
-+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+
-+	u8	res = _SUCCESS;
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (!is_primary_adapter(padapter))
-+		goto exit;
-+#endif
-+
-+	ppscmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ppscmd == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((unsigned char *)ppscmd, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = POWER_SAVING_CTRL_WK_CID;
-+	pdrvextra_cmd_parm->type = 0;
-+	pdrvextra_cmd_parm->size = 0;
-+	pdrvextra_cmd_parm->pbuf = NULL;
-+	init_h2fwcmd_w_parm_no_rsp(ppscmd, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ppscmd);
-+
-+exit:
-+
-+
-+	return res;
-+
-+}
-+
-+#if CONFIG_DFS
-+void rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj)
-+{
-+	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
-+	_adapter *pri_adapter = dvobj_get_primary_adapter(dvobj);
-+	struct mlme_ext_priv *pmlmeext = &pri_adapter->mlmeextpriv;
-+	u8 ifbmp_m = rtw_mi_get_ap_mesh_ifbmp(pri_adapter);
-+	u8 ifbmp_s = rtw_mi_get_ld_sta_ifbmp(pri_adapter);
-+	s16 req_ch;
-+	u8 req_bw = CHANNEL_WIDTH_20, req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+
-+	rtw_hal_macid_sleep_all_used(pri_adapter);
-+
-+	if (rtw_chset_search_ch(rfctl->channel_set, rfctl->csa_ch) >= 0
-+		&& !rtw_chset_is_ch_non_ocp(rfctl->channel_set, rfctl->csa_ch)
-+	) {
-+		/* CSA channel available and valid */
-+		req_ch = rfctl->csa_ch;
-+		RTW_INFO("%s valid CSA ch%u\n", __func__, rfctl->csa_ch);
-+	} else if (ifbmp_m) {
-+		/* no available or valid CSA channel, having AP/MESH ifaces */
-+		req_ch = REQ_CH_NONE;
-+		RTW_INFO("%s ch sel by AP/MESH ifaces\n", __func__);
-+	} else {
-+		/* no available or valid CSA channel and no AP/MESH ifaces */
-+		if (!IsSupported24G(dvobj_to_regsty(dvobj)->wireless_mode)
-+			#ifdef CONFIG_DFS_MASTER
-+			|| rfctl->radar_detected
-+			#endif
-+		)
-+			req_ch = 36;
-+		else
-+			req_ch = 1;
-+		RTW_INFO("%s switch to ch%d\n", __func__, req_ch);
-+	}
-+
-+	/* only support 80 Mhz so far */
-+	if(rfctl->csa_ch_width == 1 || rfctl->csa_ch_width == 2 || rfctl->csa_ch_width == 3) {
-+		if (rtw_get_offset_by_chbw(req_ch, CHANNEL_WIDTH_80, &req_offset)) {
-+			req_bw = CHANNEL_WIDTH_80;
-+		} else {
-+			req_bw = CHANNEL_WIDTH_20;
-+			req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		}
-+	} else if(rfctl->csa_ch_offset == 1) {
-+		req_bw = CHANNEL_WIDTH_40;
-+		req_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+	} else if(rfctl->csa_ch_offset == 3) {
-+		req_bw = CHANNEL_WIDTH_40;
-+		req_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+	} else{
-+		req_bw = CHANNEL_WIDTH_20;
-+		req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	}
-+
-+	RTW_INFO("req_ch=%d, req_bw=%d, req_offset=%d, ifbmp_m=0x%02x, ifbmp_s=0x%02x\n"
-+		, req_ch, req_bw, req_offset, ifbmp_m, ifbmp_s);
-+
-+	/*  update ch, bw, offset for all asoc STA ifaces */
-+	if (ifbmp_s) {
-+		_adapter *iface;
-+		int i;
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			if (!iface || !(ifbmp_s & BIT(iface->iface_id)))
-+				continue;
-+			
-+			/* update STA mode ch/bw/offset */
-+			iface->mlmeextpriv.cur_channel = req_ch;
-+			iface->mlmeextpriv.cur_bwmode = req_bw;
-+			iface->mlmeextpriv.cur_ch_offset = req_offset;
-+			/* updaet STA mode DSConfig , ap mode will update in rtw_change_bss_chbw_cmd */
-+			iface->mlmepriv.cur_network.network.Configuration.DSConfig = req_ch;
-+			set_fwstate(&iface->mlmepriv, WIFI_CSA_UPDATE_BEACON);
-+			
-+		}
-+	}
-+
-+	if (rfctl->csa_ch > 0) {
-+		RTW_INFO("pmlmeext->csa_timer 70 seconds\n");
-+		/* wait 70 seconds for receiving beacons */
-+		_set_timer(&pmlmeext->csa_timer, CAC_TIME_MS + 10000);
-+	}
-+
-+#ifdef CONFIG_AP_MODE
-+	if (ifbmp_m) {
-+		/* trigger channel selection with consideraton of asoc STA ifaces */
-+		rtw_change_bss_chbw_cmd(dvobj_get_primary_adapter(dvobj), RTW_CMDF_DIRECTLY
-+			, ifbmp_m, 0, req_ch, REQ_BW_ORI, REQ_OFFSET_NONE);
-+	} else
-+#endif
-+	{
-+		/* no AP/MESH iface, switch DFS status and channel directly */
-+		rtw_warn_on(req_ch <= 0);
-+		#ifdef CONFIG_DFS_MASTER
-+		rtw_dfs_rd_en_decision(pri_adapter, MLME_OPCH_SWITCH, ifbmp_s);
-+		#endif
-+		LeaveAllPowerSaveModeDirect(pri_adapter);
-+		set_channel_bwmode(pri_adapter, req_ch, req_offset, req_bw);
-+		/* update union ch/bw/offset for STA only */
-+		rtw_mi_update_union_chan_inf(pri_adapter, req_ch, req_offset, req_bw);
-+		rtw_rfctl_update_op_mode(rfctl, 0, 0);
-+	}
-+	
-+	rfctl->csa_ch = 0;
-+	rfctl->csa_switch_cnt = 0;
-+	rfctl->csa_ch_offset = 0;
-+	rfctl->csa_ch_width = 0;
-+	rfctl->csa_ch_freq_seg0 = 0;
-+	rfctl->csa_ch_freq_seg1 = 0;
-+
-+	rtw_hal_macid_wakeup_all_used(pri_adapter);
-+	rtw_mi_os_xmit_schedule(pri_adapter);
-+}
-+#endif /* CONFIG_DFS */
-+
-+#ifdef CONFIG_AP_MODE
-+
-+static void rtw_chk_hi_queue_hdl(_adapter *padapter)
-+{
-+	struct sta_info *psta_bmc;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	systime start = rtw_get_current_time();
-+	u8 empty = _FALSE;
-+
-+	psta_bmc = rtw_get_bcmc_stainfo(padapter);
-+	if (!psta_bmc)
-+		return;
-+
-+	rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);
-+
-+	while (_FALSE == empty && rtw_get_passing_time_ms(start) < rtw_get_wait_hiq_empty_ms()) {
-+		rtw_msleep_os(100);
-+		rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty);
-+	}
-+
-+	if (psta_bmc->sleepq_len == 0) {
-+		if (empty == _SUCCESS) {
-+			bool update_tim = _FALSE;
-+
-+			if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0))
-+				update_tim = _TRUE;
-+
-+			rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);
-+			rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);
-+
-+			if (update_tim == _TRUE)
-+				_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0,"bmc sleepq and HIQ empty");
-+		} else /* re check again */
-+			rtw_chk_hi_queue_cmd(padapter);
-+
-+	}
-+
-+}
-+
-+u8 rtw_chk_hi_queue_cmd(_adapter *padapter)
-+{
-+	struct cmd_obj	*ph2c;
-+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = CHECK_HIQ_WK_CID;
-+	pdrvextra_cmd_parm->type = 0;
-+	pdrvextra_cmd_parm->size = 0;
-+	pdrvextra_cmd_parm->pbuf = NULL;
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+
-+	return res;
-+
-+}
-+
-+#ifdef CONFIG_DFS_MASTER
-+u8 rtw_dfs_rd_hdl(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	u8 cch;
-+
-+	if (!rfctl->radar_detect_enabled)
-+		goto exit;
-+
-+	cch = rtw_get_center_ch(rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);
-+
-+	if (dvobj->oper_channel != rfctl->radar_detect_ch
-+		|| rtw_get_passing_time_ms(rtw_get_on_oper_ch_time(adapter)) < 300
-+	) {
-+		/* offchannel, bypass radar detect */
-+		goto cac_status_chk;
-+	}
-+
-+	if (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl)) {
-+		/* non_ocp, bypass radar detect */
-+		goto cac_status_chk;
-+	}
-+
-+	if (!rfctl->dbg_dfs_fake_radar_detect_cnt
-+		&& rtw_odm_radar_detect(adapter) != _TRUE)
-+		goto cac_status_chk;
-+
-+	if (!rfctl->dbg_dfs_fake_radar_detect_cnt
-+		&& rfctl->dbg_dfs_radar_detect_trigger_non
-+	) {
-+		/* radar detect debug mode, trigger no mlme flow */
-+		RTW_INFO("%s radar detected on test mode, trigger no mlme flow\n", __func__);
-+		goto cac_status_chk;
-+	}
-+
-+	if (rfctl->dbg_dfs_fake_radar_detect_cnt != 0) {
-+		RTW_INFO("%s fake radar detected, cnt:%d\n", __func__
-+			, rfctl->dbg_dfs_fake_radar_detect_cnt);
-+		rfctl->dbg_dfs_fake_radar_detect_cnt--;
-+	} else
-+		RTW_INFO("%s radar detected\n", __func__);
-+
-+	rfctl->radar_detected = 1;
-+
-+	rtw_chset_update_non_ocp(rfctl->channel_set
-+		, rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);
-+
-+	if (IS_UNDER_CAC(rfctl))
-+		rtw_nlrtw_cac_abort_event(adapter, cch, rfctl->radar_detect_bw);
-+	rtw_nlrtw_radar_detect_event(adapter, cch, rfctl->radar_detect_bw);
-+
-+	rtw_dfs_ch_switch_hdl(dvobj);
-+
-+	if (rfctl->radar_detect_enabled)
-+		goto set_timer;
-+	goto exit;
-+
-+cac_status_chk:
-+
-+	if (!IS_CAC_STOPPED(rfctl)
-+		&& ((IS_UNDER_CAC(rfctl) && rfctl->cac_force_stop)
-+			|| !IS_CH_WAITING(rfctl)
-+			)
-+	) {
-+		u8 pause = 0x00;
-+
-+		rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause);
-+		rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
-+		rtw_nlrtw_cac_finish_event(adapter, cch, rfctl->radar_detect_bw);
-+
-+		if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_UNDER_SURVEY) == _FALSE) {
-+			u8 doiqk = _TRUE;
-+			u8 u_ch, u_bw, u_offset;
-+
-+			rtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk);
-+
-+			if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset))
-+				set_channel_bwmode(adapter, u_ch, u_offset, u_bw);
-+			else
-+				rtw_warn_on(1);
-+
-+			doiqk = _FALSE;
-+			rtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk);
-+
-+			#ifdef CONFIG_AP_MODE
-+			ResumeTxBeacon(adapter);
-+			rtw_mi_tx_beacon_hdl(adapter);
-+			#endif
-+		}
-+	}
-+
-+set_timer:
-+	_set_timer(&rfctl->radar_detect_timer
-+		, rtw_odm_radar_detect_polling_int_ms(dvobj));
-+
-+exit:
-+	return H2C_SUCCESS;
-+}
-+
-+u8 rtw_dfs_rd_cmd(_adapter *adapter, bool enqueue)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *parm;
-+	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
-+	u8 res = _FAIL;
-+
-+	if (enqueue) {
-+		cmdobj = rtw_zmalloc(sizeof(struct cmd_obj));
-+		if (cmdobj == NULL)
-+			goto exit;
-+
-+		parm = rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+		if (parm == NULL) {
-+			rtw_mfree(cmdobj, sizeof(struct cmd_obj));
-+			goto exit;
-+		}
-+
-+		parm->ec_id = DFS_RADAR_DETECT_WK_CID;
-+		parm->type = 0;
-+		parm->size = 0;
-+		parm->pbuf = NULL;
-+
-+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
-+		res = rtw_enqueue_cmd(cmdpriv, cmdobj);
-+	} else {
-+		rtw_dfs_rd_hdl(adapter);
-+		res = _SUCCESS;
-+	}
-+
-+exit:
-+	return res;
-+}
-+
-+void rtw_dfs_rd_timer_hdl(void *ctx)
-+{
-+	struct rf_ctl_t *rfctl = (struct rf_ctl_t *)ctx;
-+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
-+
-+	rtw_dfs_rd_cmd(dvobj_get_primary_adapter(dvobj), _TRUE);
-+}
-+
-+static void rtw_dfs_rd_enable(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool bypass_cac)
-+{
-+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
-+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
-+
-+	RTW_INFO("%s on %u,%u,%u\n", __func__, ch, bw, offset);
-+
-+	if (bypass_cac)
-+		rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
-+	else if (rtw_is_cac_reset_needed(rfctl, ch, bw, offset) == _TRUE)
-+		rtw_reset_cac(rfctl, ch, bw, offset);
-+
-+	rfctl->radar_detect_by_others = _FALSE;
-+	rfctl->radar_detect_ch = ch;
-+	rfctl->radar_detect_bw = bw;
-+	rfctl->radar_detect_offset = offset;
-+
-+	rfctl->radar_detected = 0;
-+
-+	if (IS_CH_WAITING(rfctl))
-+		StopTxBeacon(adapter);
-+
-+	if (!rfctl->radar_detect_enabled) {
-+		RTW_INFO("%s set radar_detect_enabled\n", __func__);
-+		rfctl->radar_detect_enabled = 1;
-+		#ifdef CONFIG_LPS
-+		LPS_Leave(adapter, "RADAR_DETECT_EN");
-+		#endif
-+		_set_timer(&rfctl->radar_detect_timer
-+			, rtw_odm_radar_detect_polling_int_ms(dvobj));
-+
-+		if (rtw_rfctl_overlap_radar_detect_ch(rfctl)) {
-+			if (IS_CH_WAITING(rfctl)) {
-+				u8 pause = 0xFF;
-+
-+				rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause);
-+			}
-+			rtw_odm_radar_detect_enable(adapter);
-+		}
-+	}
-+}
-+
-+static void rtw_dfs_rd_disable(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool by_others)
-+{
-+	_adapter *adapter = dvobj_get_primary_adapter(rfctl_to_dvobj(rfctl));
-+
-+	rfctl->radar_detect_by_others = by_others;
-+
-+	if (rfctl->radar_detect_enabled) {
-+		bool overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl);
-+
-+		RTW_INFO("%s clear radar_detect_enabled\n", __func__);
-+
-+		rfctl->radar_detect_enabled = 0;
-+		rfctl->radar_detected = 0;
-+		rfctl->radar_detect_ch = 0;
-+		rfctl->radar_detect_bw = 0;
-+		rfctl->radar_detect_offset = 0;
-+		rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
-+		_cancel_timer_ex(&rfctl->radar_detect_timer);
-+
-+		if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_UNDER_SURVEY) == _FALSE) {
-+			ResumeTxBeacon(adapter);
-+			rtw_mi_tx_beacon_hdl(adapter);
-+		}
-+
-+		if (overlap_radar_detect_ch) {
-+			u8 pause = 0x00;
-+
-+			rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause);
-+			rtw_odm_radar_detect_disable(adapter);
-+		}
-+	}
-+
-+	if (by_others) {
-+		rfctl->radar_detect_ch = ch;
-+		rfctl->radar_detect_bw = bw;
-+		rfctl->radar_detect_offset = offset;
-+	}
-+}
-+
-+void rtw_dfs_rd_en_decision(_adapter *adapter, u8 mlme_act, u8 excl_ifbmp)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+	struct mi_state mstate;
-+	u8 ifbmp;
-+	u8 u_ch, u_bw, u_offset;
-+	bool ld_sta_in_dfs = _FALSE;
-+	bool sync_ch = _FALSE; /* _FALSE: asign channel directly */
-+	bool needed = _FALSE;
-+
-+	if (mlme_act == MLME_OPCH_SWITCH
-+		|| mlme_act == MLME_ACTION_NONE
-+	) {
-+		ifbmp = ~excl_ifbmp;
-+		rtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate);
-+		rtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp, &u_ch, &u_bw, &u_offset);
-+	} else {
-+		ifbmp = ~excl_ifbmp & ~BIT(adapter->iface_id);
-+		rtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate);
-+		rtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp, &u_ch, &u_bw, &u_offset);
-+		if (u_ch != 0)
-+			sync_ch = _TRUE;
-+
-+		switch (mlme_act) {
-+		case MLME_STA_CONNECTING:
-+			MSTATE_STA_LG_NUM(&mstate)++;
-+			break;
-+		case MLME_STA_CONNECTED:
-+			MSTATE_STA_LD_NUM(&mstate)++;
-+			break;
-+		case MLME_STA_DISCONNECTED:
-+			break;
-+#ifdef CONFIG_AP_MODE
-+		case MLME_AP_STARTED:
-+			MSTATE_AP_NUM(&mstate)++;
-+			break;
-+		case MLME_AP_STOPPED:
-+			break;
-+#endif
-+#ifdef CONFIG_RTW_MESH
-+		case MLME_MESH_STARTED:
-+			MSTATE_MESH_NUM(&mstate)++;
-+			break;
-+		case MLME_MESH_STOPPED:
-+			break;
-+#endif
-+		default:
-+			rtw_warn_on(1);
-+			break;
-+		}
-+
-+		if (sync_ch == _TRUE) {
-+			if (!MLME_IS_OPCH_SW(adapter)) {
-+				if (!rtw_is_chbw_grouped(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset)) {
-+					RTW_INFO(FUNC_ADPT_FMT" can't sync %u,%u,%u with %u,%u,%u\n", FUNC_ADPT_ARG(adapter)
-+						, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset);
-+					goto apply;
-+				}
-+
-+				rtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset
-+					, &u_ch, &u_bw, &u_offset);
-+			}
-+		} else {
-+			u_ch = mlmeext->cur_channel;
-+			u_bw = mlmeext->cur_bwmode;
-+			u_offset = mlmeext->cur_ch_offset;
-+		}
-+	}
-+
-+	if (MSTATE_STA_LG_NUM(&mstate) > 0) {
-+		/* STA mode is linking */
-+		goto apply;
-+	}
-+
-+	if (MSTATE_STA_LD_NUM(&mstate) > 0) {
-+		if (rtw_chset_is_dfs_chbw(rfctl->channel_set, u_ch, u_bw, u_offset)) {
-+			/*
-+			* if operate as slave w/o radar detect,
-+			* rely on AP on which STA mode connects
-+			*/
-+			if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_rfctl_dfs_domain_unknown(rfctl))
-+				needed = _TRUE;
-+			ld_sta_in_dfs = _TRUE;
-+		}
-+		goto apply;
-+	}
-+
-+	if (!MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) {
-+		/* No working AP/Mesh mode */
-+		goto apply;
-+	}
-+
-+	if (rtw_chset_is_dfs_chbw(rfctl->channel_set, u_ch, u_bw, u_offset))
-+		needed = _TRUE;
-+
-+apply:
-+
-+	RTW_INFO(FUNC_ADPT_FMT" needed:%d, mlme_act:%u, excl_ifbmp:0x%02x\n"
-+		, FUNC_ADPT_ARG(adapter), needed, mlme_act, excl_ifbmp);
-+	RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, mesh_num:%u, %u,%u,%u\n"
-+		, FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate)
-+		, MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate)
-+		, u_ch, u_bw, u_offset);
-+
-+	if (needed == _TRUE)
-+		rtw_dfs_rd_enable(rfctl, u_ch, u_bw, u_offset, ld_sta_in_dfs);
-+	else
-+		rtw_dfs_rd_disable(rfctl, u_ch, u_bw, u_offset, ld_sta_in_dfs);
-+}
-+
-+u8 rtw_dfs_rd_en_decision_cmd(_adapter *adapter)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *parm;
-+	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
-+	u8 res = _FAIL;
-+
-+	cmdobj = rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (cmdobj == NULL)
-+		goto exit;
-+
-+	parm = rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (parm == NULL) {
-+		rtw_mfree(cmdobj, sizeof(struct cmd_obj));
-+		goto exit;
-+	}
-+
-+	parm->ec_id = DFS_RADAR_DETECT_EN_DEC_WK_CID;
-+	parm->type = 0;
-+	parm->size = 0;
-+	parm->pbuf = NULL;
-+
-+	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
-+	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
-+
-+exit:
-+	return res;
-+}
-+#endif /* CONFIG_DFS_MASTER */
-+
-+#endif /* CONFIG_AP_MODE */
-+
-+#ifdef CONFIG_BT_COEXIST
-+struct btinfo {
-+	u8 cid;
-+	u8 len;
-+
-+	u8 bConnection:1;
-+	u8 bSCOeSCO:1;
-+	u8 bInQPage:1;
-+	u8 bACLBusy:1;
-+	u8 bSCOBusy:1;
-+	u8 bHID:1;
-+	u8 bA2DP:1;
-+	u8 bFTP:1;
-+
-+	u8 retry_cnt:4;
-+	u8 rsvd_34:1;
-+	u8 rsvd_35:1;
-+	u8 rsvd_36:1;
-+	u8 rsvd_37:1;
-+
-+	u8 rssi;
-+
-+	u8 rsvd_50:1;
-+	u8 rsvd_51:1;
-+	u8 rsvd_52:1;
-+	u8 rsvd_53:1;
-+	u8 rsvd_54:1;
-+	u8 rsvd_55:1;
-+	u8 eSCO_SCO:1;
-+	u8 Master_Slave:1;
-+
-+	u8 rsvd_6;
-+	u8 rsvd_7;
-+};
-+
-+void btinfo_evt_dump(void *sel, void *buf)
-+{
-+	struct btinfo *info = (struct btinfo *)buf;
-+
-+	RTW_PRINT_SEL(sel, "cid:0x%02x, len:%u\n", info->cid, info->len);
-+
-+	if (info->len > 2)
-+		RTW_PRINT_SEL(sel, "byte2:%s%s%s%s%s%s%s%s\n"
-+			      , info->bConnection ? "bConnection " : ""
-+			      , info->bSCOeSCO ? "bSCOeSCO " : ""
-+			      , info->bInQPage ? "bInQPage " : ""
-+			      , info->bACLBusy ? "bACLBusy " : ""
-+			      , info->bSCOBusy ? "bSCOBusy " : ""
-+			      , info->bHID ? "bHID " : ""
-+			      , info->bA2DP ? "bA2DP " : ""
-+			      , info->bFTP ? "bFTP" : ""
-+			     );
-+
-+	if (info->len > 3)
-+		RTW_PRINT_SEL(sel, "retry_cnt:%u\n", info->retry_cnt);
-+
-+	if (info->len > 4)
-+		RTW_PRINT_SEL(sel, "rssi:%u\n", info->rssi);
-+
-+	if (info->len > 5)
-+		RTW_PRINT_SEL(sel, "byte5:%s%s\n"
-+			      , info->eSCO_SCO ? "eSCO_SCO " : ""
-+			      , info->Master_Slave ? "Master_Slave " : ""
-+			     );
-+}
-+
-+static void rtw_btinfo_hdl(_adapter *adapter, u8 *buf, u16 buf_len)
-+{
-+#define BTINFO_WIFI_FETCH 0x23
-+#define BTINFO_BT_AUTO_RPT 0x27
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+	struct btinfo_8761ATV *info = (struct btinfo_8761ATV *)buf;
-+#else /* !CONFIG_BT_COEXIST_SOCKET_TRX */
-+	struct btinfo *info = (struct btinfo *)buf;
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+	u8 cmd_idx;
-+	u8 len;
-+
-+	cmd_idx = info->cid;
-+
-+	if (info->len > buf_len - 2) {
-+		rtw_warn_on(1);
-+		len = buf_len - 2;
-+	} else
-+		len = info->len;
-+
-+	/* #define DBG_PROC_SET_BTINFO_EVT */
-+#ifdef DBG_PROC_SET_BTINFO_EVT
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+	RTW_INFO("%s: btinfo[0]=%x,btinfo[1]=%x,btinfo[2]=%x,btinfo[3]=%x btinfo[4]=%x,btinfo[5]=%x,btinfo[6]=%x,btinfo[7]=%x\n"
-+		, __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
-+#else/* !CONFIG_BT_COEXIST_SOCKET_TRX */
-+	btinfo_evt_dump(RTW_DBGDUMP, info);
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+#endif /* DBG_PROC_SET_BTINFO_EVT */
-+
-+	/* transform BT-FW btinfo to WiFI-FW C2H format and notify */
-+	if (cmd_idx == BTINFO_WIFI_FETCH)
-+		buf[1] = 0;
-+	else if (cmd_idx == BTINFO_BT_AUTO_RPT)
-+		buf[1] = 2;
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+	else if (0x01 == cmd_idx || 0x02 == cmd_idx)
-+		buf[1] = buf[0];
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+	rtw_btcoex_BtInfoNotify(adapter , len + 1, &buf[1]);
-+}
-+
-+u8 rtw_btinfo_cmd(_adapter *adapter, u8 *buf, u16 len)
-+{
-+	struct cmd_obj *ph2c;
-+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
-+	u8 *btinfo;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	btinfo = rtw_zmalloc(len);
-+	if (btinfo == NULL) {
-+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
-+		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = BTINFO_WK_CID;
-+	pdrvextra_cmd_parm->type = 0;
-+	pdrvextra_cmd_parm->size = len;
-+	pdrvextra_cmd_parm->pbuf = btinfo;
-+
-+	_rtw_memcpy(btinfo, buf, len);
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+	return res;
-+}
-+
-+static void rtw_btc_reduce_wl_txpwr_hdl(_adapter *adapter, u32 pwr_lvl)
-+{
-+	rtw_btcoex_set_reduced_wl_pwr_lvl(adapter, pwr_lvl);
-+	rtw_btcoex_do_reduce_wl_pwr_lvl(adapter);
-+
-+	RTW_INFO(FUNC_ADPT_FMT ": BTC reduce WL TxPwr %d dB!\n",
-+		 FUNC_ADPT_ARG(adapter), pwr_lvl);
-+}
-+
-+u8 rtw_btc_reduce_wl_txpwr_cmd(_adapter *adapter, u32 val)
-+{
-+	struct cmd_obj *pcmdobj;
-+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+
-+	pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (pcmdobj == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = BTC_REDUCE_WL_TXPWR_CID;
-+	pdrvextra_cmd_parm->type = val;
-+	pdrvextra_cmd_parm->size = 0;
-+	pdrvextra_cmd_parm->pbuf = NULL;
-+
-+	init_h2fwcmd_w_parm_no_rsp(pcmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
-+
-+exit:
-+	return res;
-+}
-+#endif /* CONFIG_BT_COEXIST */
-+
-+u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len)
-+{
-+	struct cmd_obj *pcmdobj;
-+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
-+	u8 *ph2c_content;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+
-+	pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (pcmdobj == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	ph2c_content = rtw_zmalloc(len);
-+	if (ph2c_content == NULL) {
-+		rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj));
-+		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = TEST_H2C_CID;
-+	pdrvextra_cmd_parm->type = 0;
-+	pdrvextra_cmd_parm->size = len;
-+	pdrvextra_cmd_parm->pbuf = ph2c_content;
-+
-+	_rtw_memcpy(ph2c_content, buf, len);
-+
-+	init_h2fwcmd_w_parm_no_rsp(pcmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
-+
-+exit:
-+	return res;
-+}
-+
-+#ifdef CONFIG_MP_INCLUDED
-+static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	int ret = H2C_SUCCESS;
-+	uint status = _SUCCESS;
-+
-+	if (mp_cmd_id == MP_START) {
-+		if (padapter->registrypriv.mp_mode == 0) {
-+			rtw_intf_stop(padapter);
-+			rtw_hal_deinit(padapter);
-+			padapter->registrypriv.mp_mode = 1;
-+#ifdef CONFIG_BT_COEXIST
-+		padapter->mppriv.CureFuseBTCoex = pHalData->EEPROMBluetoothCoexist;
-+		pHalData->EEPROMBluetoothCoexist = _FALSE;
-+#endif
-+#ifdef CONFIG_RF_POWER_TRIM
-+			if (!IS_HARDWARE_TYPE_8814A(padapter) && !IS_HARDWARE_TYPE_8822B(padapter) && !IS_HARDWARE_TYPE_8822C(padapter)) {
-+				padapter->registrypriv.RegPwrTrimEnable = 1;
-+				rtw_hal_read_chip_info(padapter);
-+			}
-+#endif /*CONFIG_RF_POWER_TRIM*/
-+			rtw_reset_drv_sw(padapter);
-+#ifdef CONFIG_NEW_NETDEV_HDL
-+			if (!rtw_is_hw_init_completed(padapter)) {
-+				status = rtw_hal_init(padapter);
-+				if (status == _FAIL) {
-+					ret = H2C_REJECTED;
-+					goto exit;
-+				}
-+				rtw_hal_iface_init(padapter);
-+			}
-+#else
-+			status = rtw_hal_init(padapter);
-+			if (status == _FAIL) {
-+				ret = H2C_REJECTED;
-+				goto exit;
-+			}
-+#endif /*CONFIG_NEW_NETDEV_HDL*/
-+#ifndef RTW_HALMAC
-+			rtw_intf_start(padapter);
-+#endif /* !RTW_HALMAC */
-+#ifdef RTW_HALMAC /*for New IC*/
-+			MPT_InitializeAdapter(padapter, 1);
-+#endif /* CONFIG_MP_INCLUDED */
-+		}
-+
-+		if (padapter->registrypriv.mp_mode == 0) {
-+			ret = H2C_REJECTED;
-+			goto exit;
-+		}
-+
-+		if (padapter->mppriv.mode == MP_OFF) {
-+			if (mp_start_test(padapter) == _FAIL) {
-+				ret = H2C_REJECTED;
-+				goto exit;
-+			}
-+			padapter->mppriv.mode = MP_ON;
-+			MPT_PwrCtlDM(padapter, 0);
-+		}
-+		padapter->mppriv.bmac_filter = _FALSE;
-+#ifdef CONFIG_RTL8723B
-+#ifdef CONFIG_USB_HCI
-+		rtw_write32(padapter, 0x765, 0x0000);
-+		rtw_write32(padapter, 0x948, 0x0280);
-+#else
-+		rtw_write32(padapter, 0x765, 0x0000);
-+		rtw_write32(padapter, 0x948, 0x0000);
-+#endif
-+#ifdef CONFIG_FOR_RTL8723BS_VQ0
-+		rtw_write32(padapter, 0x765, 0x0000);
-+		rtw_write32(padapter, 0x948, 0x0280);
-+#endif
-+		rtw_write8(padapter, 0x66, 0x27); /*Open BT uart Log*/
-+		rtw_write8(padapter, 0xc50, 0x20); /*for RX init Gain*/
-+#endif
-+		odm_write_dig(&pHalData->odmpriv, 0x20);
-+
-+	} else if (mp_cmd_id == MP_STOP) {
-+		if (padapter->registrypriv.mp_mode == 1) {
-+			MPT_DeInitAdapter(padapter);
-+			rtw_intf_stop(padapter);
-+			rtw_hal_deinit(padapter);
-+			padapter->registrypriv.mp_mode = 0;
-+#ifdef CONFIG_BT_COEXIST
-+			pHalData->EEPROMBluetoothCoexist = padapter->mppriv.CureFuseBTCoex;
-+#endif
-+			rtw_reset_drv_sw(padapter);
-+#ifdef CONFIG_NEW_NETDEV_HDL
-+			if (!rtw_is_hw_init_completed(padapter)) {
-+				status = rtw_hal_init(padapter);
-+				if (status == _FAIL) {
-+					ret = H2C_REJECTED;
-+					goto exit;
-+				}
-+				rtw_hal_iface_init(padapter);
-+			}
-+#else
-+			status = rtw_hal_init(padapter);
-+			if (status == _FAIL) {
-+				ret = H2C_REJECTED;
-+				goto exit;
-+			}
-+#endif /*CONFIG_NEW_NETDEV_HDL*/
-+#ifndef RTW_HALMAC
-+			rtw_intf_start(padapter);
-+#endif /* !RTW_HALMAC */
-+		}
-+
-+		if (padapter->mppriv.mode != MP_OFF) {
-+			mp_stop_test(padapter);
-+			padapter->mppriv.mode = MP_OFF;
-+		}
-+
-+	} else {
-+		RTW_INFO(FUNC_ADPT_FMT"invalid id:%d\n", FUNC_ADPT_ARG(padapter), mp_cmd_id);
-+		ret = H2C_PARAMETERS_ERROR;
-+		rtw_warn_on(1);
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *parm;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8	res = _SUCCESS;
-+
-+	parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (parm == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	parm->ec_id = MP_CMD_WK_CID;
-+	parm->type = mp_cmd_id;
-+	parm->size = 0;
-+	parm->pbuf = NULL;
-+
-+	if (flags & RTW_CMDF_DIRECTLY) {
-+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
-+		if (H2C_SUCCESS != rtw_mp_cmd_hdl(adapter, mp_cmd_id))
-+			res = _FAIL;
-+		rtw_mfree((u8 *)parm, sizeof(*parm));
-+	} else {
-+		/* need enqueue, prepare cmd_obj and enqueue */
-+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
-+		if (cmdobj == NULL) {
-+			res = _FAIL;
-+			rtw_mfree((u8 *)parm, sizeof(*parm));
-+			goto exit;
-+		}
-+
-+		init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
-+
-+		if (flags & RTW_CMDF_WAIT_ACK) {
-+			cmdobj->sctx = &sctx;
-+			rtw_sctx_init(&sctx, 10 * 1000);
-+		}
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+
-+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			rtw_sctx_wait(&sctx, __func__);
-+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status == RTW_SCTX_SUBMITTED)
-+				cmdobj->sctx = NULL;
-+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
-+				res = _FAIL;
-+		}
-+	}
-+
-+exit:
-+	return res;
-+}
-+#endif	/*CONFIG_MP_INCLUDED*/
-+
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+static s32 rtw_customer_str_cmd_hdl(_adapter *adapter, u8 write, const u8 *cstr)
-+{
-+	int ret = H2C_SUCCESS;
-+
-+	if (write)
-+		ret = rtw_hal_h2c_customer_str_write(adapter, cstr);
-+	else
-+		ret = rtw_hal_h2c_customer_str_req(adapter);
-+
-+	return ret == _SUCCESS ? H2C_SUCCESS : H2C_REJECTED;
-+}
-+
-+static u8 rtw_customer_str_cmd(_adapter *adapter, u8 write, const u8 *cstr)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *parm;
-+	u8 *str = NULL;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8 res = _SUCCESS;
-+
-+	parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (parm == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	if (write) {
-+		str = rtw_zmalloc(RTW_CUSTOMER_STR_LEN);
-+		if (str == NULL) {
-+			rtw_mfree((u8 *)parm, sizeof(struct drvextra_cmd_parm));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+	}
-+
-+	parm->ec_id = CUSTOMER_STR_WK_CID;
-+	parm->type = write;
-+	parm->size = write ? RTW_CUSTOMER_STR_LEN : 0;
-+	parm->pbuf = write ? str : NULL;
-+
-+	if (write)
-+		_rtw_memcpy(str, cstr, RTW_CUSTOMER_STR_LEN);
-+
-+	/* need enqueue, prepare cmd_obj and enqueue */
-+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
-+	if (cmdobj == NULL) {
-+		res = _FAIL;
-+		rtw_mfree((u8 *)parm, sizeof(*parm));
-+		if (write)
-+			rtw_mfree(str, RTW_CUSTOMER_STR_LEN);
-+		goto exit;
-+	}
-+
-+	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
-+
-+	cmdobj->sctx = &sctx;
-+	rtw_sctx_init(&sctx, 2 * 1000);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+
-+	if (res == _SUCCESS) {
-+		rtw_sctx_wait(&sctx, __func__);
-+		_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+		if (sctx.status == RTW_SCTX_SUBMITTED)
-+			cmdobj->sctx = NULL;
-+		_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+		if (sctx.status != RTW_SCTX_DONE_SUCCESS)
-+			res = _FAIL;
-+	}
-+
-+exit:
-+	return res;
-+}
-+
-+inline u8 rtw_customer_str_req_cmd(_adapter *adapter)
-+{
-+	return rtw_customer_str_cmd(adapter, 0, NULL);
-+}
-+
-+inline u8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr)
-+{
-+	return rtw_customer_str_cmd(adapter, 1, cstr);
-+}
-+#endif /* CONFIG_RTW_CUSTOMER_STR */
-+
-+u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *pbuf, u16 length, u8 type)
-+{
-+	struct cmd_obj *ph2c;
-+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+	u8 *extra_cmd_buf;
-+	u8 res = _SUCCESS;
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	extra_cmd_buf = rtw_zmalloc(length);
-+	if (extra_cmd_buf == NULL) {
-+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
-+		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	_rtw_memcpy(extra_cmd_buf, pbuf, length);
-+	pdrvextra_cmd_parm->ec_id = C2H_WK_CID;
-+	pdrvextra_cmd_parm->type = type;
-+	pdrvextra_cmd_parm->size = length;
-+	pdrvextra_cmd_parm->pbuf = extra_cmd_buf;
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+	return res;
-+}
-+
-+#ifdef CONFIG_FW_C2H_REG
-+inline u8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt)
-+{
-+	return rtw_c2h_wk_cmd(adapter, c2h_evt, c2h_evt ? C2H_REG_LEN : 0, C2H_TYPE_REG);
-+}
-+#endif
-+
-+#ifdef CONFIG_FW_C2H_PKT
-+inline u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length)
-+{
-+	return rtw_c2h_wk_cmd(adapter, c2h_evt, length, C2H_TYPE_PKT);
-+}
-+#endif
-+
-+static u8 _rtw_run_in_thread_cmd(_adapter *adapter, void (*func)(void *), void *context, s32 timeout_ms)
-+{
-+	struct cmd_priv *cmdpriv = &adapter->cmdpriv;
-+	struct cmd_obj *cmdobj;
-+	struct RunInThread_param *parm;
-+	struct submit_ctx sctx;
-+	s32 res = _SUCCESS;
-+
-+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (NULL == cmdobj) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	parm = (struct RunInThread_param *)rtw_zmalloc(sizeof(struct RunInThread_param));
-+	if (NULL == parm) {
-+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	parm->func = func;
-+	parm->context = context;
-+	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_RUN_INTHREAD);
-+
-+	if (timeout_ms >= 0) {
-+		cmdobj->sctx = &sctx;
-+		rtw_sctx_init(&sctx, timeout_ms);
-+	}
-+
-+	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
-+
-+	if (res == _SUCCESS && timeout_ms >= 0) {
-+		rtw_sctx_wait(&sctx, __func__);
-+		_enter_critical_mutex(&cmdpriv->sctx_mutex, NULL);
-+		if (sctx.status == RTW_SCTX_SUBMITTED)
-+			cmdobj->sctx = NULL;
-+		_exit_critical_mutex(&cmdpriv->sctx_mutex, NULL);
-+		if (sctx.status != RTW_SCTX_DONE_SUCCESS)
-+			res = _FAIL;
-+	}
-+
-+exit:
-+	return res;
-+}
-+
-+u8 rtw_run_in_thread_cmd(_adapter *adapter, void (*func)(void *), void *context)
-+{
-+	return _rtw_run_in_thread_cmd(adapter, func, context, -1);
-+}
-+
-+u8 rtw_run_in_thread_cmd_wait(_adapter *adapter, void (*func)(void *), void *context, s32 timeout_ms)
-+{
-+	return _rtw_run_in_thread_cmd(adapter, func, context, timeout_ms);
-+}
-+
-+#ifdef CONFIG_FW_C2H_REG
-+s32 c2h_evt_hdl(_adapter *adapter, u8 *c2h_evt, c2h_id_filter filter)
-+{
-+	s32 ret = _FAIL;
-+	u8 buf[C2H_REG_LEN] = {0};
-+	u8 id, seq, plen;
-+	u8 *payload;
-+
-+	if (!c2h_evt) {
-+		/* No c2h event in cmd_obj, read c2h event before handling*/
-+		if (rtw_hal_c2h_evt_read(adapter, buf) != _SUCCESS)
-+			goto exit;
-+		c2h_evt = buf;
-+	}
-+
-+	rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload);
-+
-+	if (filter && filter(adapter, id, seq, plen, payload) == _FALSE)
-+		goto exit;
-+
-+	ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_FW_C2H_REG */
-+
-+u8 session_tracker_cmd(_adapter *adapter, u8 cmd, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
-+{
-+	struct cmd_priv	*cmdpriv = &adapter->cmdpriv;
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *cmd_parm;
-+	struct st_cmd_parm *st_parm;
-+	u8	res = _SUCCESS;
-+
-+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (cmdobj == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (cmd_parm == NULL) {
-+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	st_parm = (struct st_cmd_parm *)rtw_zmalloc(sizeof(struct st_cmd_parm));
-+	if (st_parm == NULL) {
-+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+		rtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	st_parm->cmd = cmd;
-+	st_parm->sta = sta;
-+	if (cmd != ST_CMD_CHK) {
-+		_rtw_memcpy(&st_parm->local_naddr, local_naddr, 4);
-+		_rtw_memcpy(&st_parm->local_port, local_port, 2);
-+		_rtw_memcpy(&st_parm->remote_naddr, remote_naddr, 4);
-+		_rtw_memcpy(&st_parm->remote_port, remote_port, 2);
-+	}
-+
-+	cmd_parm->ec_id = SESSION_TRACKER_WK_CID;
-+	cmd_parm->type = 0;
-+	cmd_parm->size = sizeof(struct st_cmd_parm);
-+	cmd_parm->pbuf = (u8 *)st_parm;
-+	init_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, CMD_SET_DRV_EXTRA);
-+	cmdobj->no_io = 1;
-+
-+	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
-+
-+exit:
-+	return res;
-+}
-+
-+inline u8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta)
-+{
-+	return session_tracker_cmd(adapter, ST_CMD_CHK, sta, NULL, NULL, NULL, NULL);
-+}
-+
-+inline u8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
-+{
-+	return session_tracker_cmd(adapter, ST_CMD_ADD, sta, local_naddr, local_port, remote_naddr, remote_port);
-+}
-+
-+inline u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
-+{
-+	return session_tracker_cmd(adapter, ST_CMD_DEL, sta, local_naddr, local_port, remote_naddr, remote_port);
-+}
-+
-+void session_tracker_chk_for_sta(_adapter *adapter, struct sta_info *sta)
-+{
-+	struct st_ctl_t *st_ctl = &sta->st_ctl;
-+	int i;
-+	_irqL irqL;
-+	_list *plist, *phead, *pnext;
-+	_list dlist;
-+	struct session_tracker *st = NULL;
-+	u8 op_wfd_mode = MIRACAST_DISABLED;
-+
-+	if (DBG_SESSION_TRACKER)
-+		RTW_INFO(FUNC_ADPT_FMT" sta:%p\n", FUNC_ADPT_ARG(adapter), sta);
-+
-+	if (!(sta->state & WIFI_ASOC_STATE))
-+		goto exit;
-+
-+	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) {
-+		if (st_ctl->reg[i].s_proto != 0)
-+			break;
-+	}
-+	if (i >= SESSION_TRACKER_REG_ID_NUM)
-+		goto chk_sta;
-+
-+	_rtw_init_listhead(&dlist);
-+
-+	_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
-+
-+	phead = &st_ctl->tracker_q.queue;
-+	plist = get_next(phead);
-+	pnext = get_next(plist);
-+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+		st = LIST_CONTAINOR(plist, struct session_tracker, list);
-+		plist = pnext;
-+		pnext = get_next(pnext);
-+
-+		if (st->status != ST_STATUS_ESTABLISH
-+			&& rtw_get_passing_time_ms(st->set_time) > ST_EXPIRE_MS
-+		) {
-+			rtw_list_delete(&st->list);
-+			rtw_list_insert_tail(&st->list, &dlist);
-+		}
-+
-+		/* TODO: check OS for status update */
-+		if (st->status == ST_STATUS_CHECK)
-+			st->status = ST_STATUS_ESTABLISH;
-+
-+		if (st->status != ST_STATUS_ESTABLISH)
-+			continue;
-+
-+		#ifdef CONFIG_WFD
-+		if (0)
-+			RTW_INFO(FUNC_ADPT_FMT" local:%u, remote:%u, rtsp:%u, %u, %u\n", FUNC_ADPT_ARG(adapter)
-+				, ntohs(st->local_port), ntohs(st->remote_port), adapter->wfd_info.rtsp_ctrlport, adapter->wfd_info.tdls_rtsp_ctrlport
-+				, adapter->wfd_info.peer_rtsp_ctrlport);
-+		if (ntohs(st->local_port) == adapter->wfd_info.rtsp_ctrlport)
-+			op_wfd_mode |= MIRACAST_SINK;
-+		if (ntohs(st->local_port) == adapter->wfd_info.tdls_rtsp_ctrlport)
-+			op_wfd_mode |= MIRACAST_SINK;
-+		if (ntohs(st->remote_port) == adapter->wfd_info.peer_rtsp_ctrlport)
-+			op_wfd_mode |= MIRACAST_SOURCE;
-+		#endif
-+	}
-+
-+	_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
-+
-+	plist = get_next(&dlist);
-+	while (rtw_end_of_queue_search(&dlist, plist) == _FALSE) {
-+		st = LIST_CONTAINOR(plist, struct session_tracker, list);
-+		plist = get_next(plist);
-+		rtw_mfree((u8 *)st, sizeof(struct session_tracker));
-+	}
-+
-+chk_sta:
-+	if (STA_OP_WFD_MODE(sta) != op_wfd_mode) {
-+		STA_SET_OP_WFD_MODE(sta, op_wfd_mode);
-+		rtw_sta_media_status_rpt_cmd(adapter, sta, 1);
-+	}
-+
-+exit:
-+	return;
-+}
-+
-+void session_tracker_chk_for_adapter(_adapter *adapter)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct sta_info *sta;
-+	int i;
-+	_irqL irqL;
-+	_list *plist, *phead;
-+	u8 op_wfd_mode = MIRACAST_DISABLED;
-+
-+	_enter_critical_bh(&stapriv->sta_hash_lock, &irqL);
-+
-+	for (i = 0; i < NUM_STA; i++) {
-+		phead = &(stapriv->sta_hash[i]);
-+		plist = get_next(phead);
-+
-+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+			sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+			plist = get_next(plist);
-+
-+			session_tracker_chk_for_sta(adapter, sta);
-+
-+			op_wfd_mode |= STA_OP_WFD_MODE(sta);
-+		}
-+	}
-+
-+	_exit_critical_bh(&stapriv->sta_hash_lock, &irqL);
-+
-+#ifdef CONFIG_WFD
-+	adapter->wfd_info.op_wfd_mode = MIRACAST_MODE_REVERSE(op_wfd_mode);
-+#endif
-+}
-+
-+void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm)
-+{
-+	u8 cmd = parm->cmd;
-+	struct sta_info *sta = parm->sta;
-+
-+	if (cmd == ST_CMD_CHK) {
-+		if (sta)
-+			session_tracker_chk_for_sta(adapter, sta);
-+		else
-+			session_tracker_chk_for_adapter(adapter);
-+
-+		goto exit;
-+
-+	} else if (cmd == ST_CMD_ADD || cmd == ST_CMD_DEL) {
-+		struct st_ctl_t *st_ctl;
-+		u32 local_naddr = parm->local_naddr;
-+		u16 local_port = parm->local_port;
-+		u32 remote_naddr = parm->remote_naddr;
-+		u16 remote_port = parm->remote_port;
-+		struct session_tracker *st = NULL;
-+		_irqL irqL;
-+		_list *plist, *phead;
-+		u8 free_st = 0;
-+		u8 alloc_st = 0;
-+
-+		if (DBG_SESSION_TRACKER)
-+			RTW_INFO(FUNC_ADPT_FMT" cmd:%u, sta:%p, local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT"\n"
-+				, FUNC_ADPT_ARG(adapter), cmd, sta
-+				, IP_ARG(&local_naddr), PORT_ARG(&local_port)
-+				, IP_ARG(&remote_naddr), PORT_ARG(&remote_port)
-+			);
-+
-+		if (!(sta->state & WIFI_ASOC_STATE))
-+			goto exit;
-+
-+		st_ctl = &sta->st_ctl;
-+
-+		_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
-+
-+		phead = &st_ctl->tracker_q.queue;
-+		plist = get_next(phead);
-+		while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+			st = LIST_CONTAINOR(plist, struct session_tracker, list);
-+
-+			if (st->local_naddr == local_naddr
-+				&& st->local_port == local_port
-+				&& st->remote_naddr == remote_naddr
-+				&& st->remote_port == remote_port)
-+				break;
-+
-+			plist = get_next(plist);
-+		}
-+
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			st = NULL;
-+
-+		switch (cmd) {
-+		case ST_CMD_DEL:
-+			if (st) {
-+				rtw_list_delete(plist);
-+				free_st = 1;
-+			}
-+			goto unlock;
-+		case ST_CMD_ADD:
-+			if (!st)
-+				alloc_st = 1;
-+		}
-+
-+unlock:
-+		_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
-+
-+		if (free_st) {
-+			rtw_mfree((u8 *)st, sizeof(struct session_tracker));
-+			goto exit;
-+		}
-+
-+		if (alloc_st) {
-+			st = (struct session_tracker *)rtw_zmalloc(sizeof(struct session_tracker));
-+			if (!st)
-+				goto exit;
-+
-+			st->local_naddr = local_naddr;
-+			st->local_port = local_port;
-+			st->remote_naddr = remote_naddr;
-+			st->remote_port = remote_port;
-+			st->set_time = rtw_get_current_time();
-+			st->status = ST_STATUS_CHECK;
-+
-+			_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
-+			rtw_list_insert_tail(&st->list, phead);
-+			_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
-+		}
-+	}
-+
-+exit:
-+	return;
-+}
-+
-+#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW)
-+static s32 rtw_req_per_cmd_hdl(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	struct macid_bmp req_macid_bmp, *macid_bmp;
-+	u8 i, ret = _FAIL;
-+
-+	macid_bmp = &macid_ctl->if_g[adapter->iface_id];
-+	_rtw_memcpy(&req_macid_bmp, macid_bmp, sizeof(struct macid_bmp));
-+
-+	/* Clear none mesh's macid */
-+	for (i = 0; i < macid_ctl->num; i++) {
-+		u8 role;
-+		role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]);
-+		if (role != H2C_MSR_ROLE_MESH)
-+			rtw_macid_map_clr(&req_macid_bmp, i);
-+	}
-+
-+	/* group_macid: always be 0 in NIC, so only pass macid_bitmap.m0
-+	 * rpt_type: 0 includes all info in 1, use 0 for now 
-+	 * macid_bitmap: pass m0 only for NIC
-+	 */
-+	ret = rtw_hal_set_req_per_rpt_cmd(adapter, 0, 0, req_macid_bmp.m0);
-+
-+	return ret;
-+}
-+
-+u8 rtw_req_per_cmd(_adapter *adapter)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *parm;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8 res = _SUCCESS;
-+
-+	parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (parm == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	parm->ec_id = REQ_PER_CMD_WK_CID;
-+	parm->type = 0;
-+	parm->size = 0;
-+	parm->pbuf = NULL;
-+
-+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
-+	if (cmdobj == NULL) {
-+		res = _FAIL;
-+		rtw_mfree((u8 *)parm, sizeof(*parm));
-+		goto exit;
-+	}
-+
-+	init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+
-+exit:
-+	return res;
-+}
-+#endif
-+
-+
-+void rtw_ac_parm_cmd_hdl(_adapter *padapter, u8 *_ac_parm_buf, int ac_type)
-+{
-+
-+	u32 ac_parm_buf;
-+
-+	_rtw_memcpy(&ac_parm_buf, _ac_parm_buf, sizeof(ac_parm_buf));
-+	switch (ac_type) {
-+	case XMIT_VO_QUEUE:
-+		RTW_INFO(FUNC_NDEV_FMT" AC_VO = 0x%08x\n", FUNC_ADPT_ARG(padapter), (unsigned int) ac_parm_buf);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&ac_parm_buf));
-+		break;
-+
-+	case XMIT_VI_QUEUE:
-+		RTW_INFO(FUNC_NDEV_FMT" AC_VI = 0x%08x\n", FUNC_ADPT_ARG(padapter), (unsigned int) ac_parm_buf);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&ac_parm_buf));
-+		break;
-+
-+	case XMIT_BE_QUEUE:
-+		RTW_INFO(FUNC_NDEV_FMT" AC_BE = 0x%08x\n", FUNC_ADPT_ARG(padapter), (unsigned int) ac_parm_buf);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&ac_parm_buf));
-+		break;
-+
-+	case XMIT_BK_QUEUE:
-+		RTW_INFO(FUNC_NDEV_FMT" AC_BK = 0x%08x\n", FUNC_ADPT_ARG(padapter), (unsigned int) ac_parm_buf);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&ac_parm_buf));
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+}
-+
-+
-+u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf)
-+{
-+	int ret = H2C_SUCCESS;
-+	struct drvextra_cmd_parm *pdrvextra_cmd;
-+
-+	if (!pbuf)
-+		return H2C_PARAMETERS_ERROR;
-+
-+	pdrvextra_cmd = (struct drvextra_cmd_parm *)pbuf;
-+
-+	switch (pdrvextra_cmd->ec_id) {
-+	case STA_MSTATUS_RPT_WK_CID:
-+		rtw_sta_media_status_rpt_cmd_hdl(padapter, (struct sta_media_status_rpt_cmd_parm *)pdrvextra_cmd->pbuf);
-+		break;
-+
-+	case DYNAMIC_CHK_WK_CID:/*only  primary padapter go to this cmd, but execute dynamic_chk_wk_hdl() for two interfaces */
-+		rtw_dynamic_chk_wk_hdl(padapter);
-+		break;
-+	case POWER_SAVING_CTRL_WK_CID:
-+		power_saving_wk_hdl(padapter);
-+		break;
-+#ifdef CONFIG_LPS
-+	case LPS_CTRL_WK_CID:
-+		lps_ctrl_wk_hdl(padapter, (u8)pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
-+		break;
-+	case DM_IN_LPS_WK_CID:
-+		rtw_dm_in_lps_hdl(padapter);
-+		break;
-+	case LPS_CHANGE_DTIM_CID:
-+		rtw_lps_change_dtim_hdl(padapter, (u8)pdrvextra_cmd->type);
-+		break;
-+#endif
-+#if (RATE_ADAPTIVE_SUPPORT == 1)
-+	case RTP_TIMER_CFG_WK_CID:
-+		rpt_timer_setting_wk_hdl(padapter, pdrvextra_cmd->type);
-+		break;
-+#endif
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	case ANT_SELECT_WK_CID:
-+		antenna_select_wk_hdl(padapter, pdrvextra_cmd->type);
-+		break;
-+#endif
-+#ifdef CONFIG_P2P_PS
-+	case P2P_PS_WK_CID:
-+		p2p_ps_wk_hdl(padapter, pdrvextra_cmd->type);
-+		break;
-+#endif
-+#ifdef CONFIG_P2P
-+	case P2P_PROTO_WK_CID:
-+		/*
-+		* Commented by Albert 2011/07/01
-+		* I used the type_size as the type command
-+		*/
-+		ret = p2p_protocol_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
-+		break;
-+#endif
-+#ifdef CONFIG_AP_MODE
-+	case CHECK_HIQ_WK_CID:
-+		rtw_chk_hi_queue_hdl(padapter);
-+		break;
-+#endif
-+	/* add for CONFIG_IEEE80211W, none 11w can use it */
-+	case RESET_SECURITYPRIV:
-+		reset_securitypriv_hdl(padapter);
-+		break;
-+	case FREE_ASSOC_RESOURCES:
-+		free_assoc_resources_hdl(padapter, (u8)pdrvextra_cmd->type);
-+		break;
-+	case C2H_WK_CID:
-+		switch (pdrvextra_cmd->type) {
-+		#ifdef CONFIG_FW_C2H_REG
-+		case C2H_TYPE_REG:
-+			c2h_evt_hdl(padapter, pdrvextra_cmd->pbuf, NULL);
-+			break;
-+		#endif
-+		#ifdef CONFIG_FW_C2H_PKT
-+		case C2H_TYPE_PKT:
-+			rtw_hal_c2h_pkt_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size);
-+			break;
-+		#endif
-+		default:
-+			RTW_ERR("unknown C2H type:%d\n", pdrvextra_cmd->type);
-+			rtw_warn_on(1);
-+			break;
-+		}
-+		break;
-+#ifdef CONFIG_BEAMFORMING
-+	case BEAMFORMING_WK_CID:
-+		beamforming_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
-+		break;
-+#endif
-+	case DM_RA_MSK_WK_CID:
-+		rtw_dm_ra_mask_hdl(padapter, (struct sta_info *)pdrvextra_cmd->pbuf);
-+		break;
-+#ifdef CONFIG_BT_COEXIST
-+	case BTINFO_WK_CID:
-+		rtw_btinfo_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size);
-+		break;
-+	case BTC_REDUCE_WL_TXPWR_CID:
-+		rtw_btc_reduce_wl_txpwr_hdl(padapter, pdrvextra_cmd->type);
-+		break;
-+#endif
-+#ifdef CONFIG_DFS_MASTER
-+	case DFS_RADAR_DETECT_WK_CID:
-+		rtw_dfs_rd_hdl(padapter);
-+		break;
-+	case DFS_RADAR_DETECT_EN_DEC_WK_CID:
-+		rtw_dfs_rd_en_decision(padapter, MLME_ACTION_NONE, 0);
-+		break;
-+#endif
-+	case SESSION_TRACKER_WK_CID:
-+		session_tracker_cmd_hdl(padapter, (struct st_cmd_parm *)pdrvextra_cmd->pbuf);
-+		break;
-+	case EN_HW_UPDATE_TSF_WK_CID:
-+		rtw_hal_set_hwreg(padapter, HW_VAR_EN_HW_UPDATE_TSF, NULL);
-+		break;
-+	case PERIOD_TSF_UPDATE_END_WK_CID:
-+		rtw_hal_periodic_tsf_update_chk(padapter);
-+		break;
-+	case TEST_H2C_CID:
-+		rtw_hal_fill_h2c_cmd(padapter, pdrvextra_cmd->pbuf[0], pdrvextra_cmd->size - 1, &pdrvextra_cmd->pbuf[1]);
-+		break;
-+	case MP_CMD_WK_CID:
-+#ifdef CONFIG_MP_INCLUDED
-+		ret = rtw_mp_cmd_hdl(padapter, pdrvextra_cmd->type);
-+#endif
-+		break;
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+	case CUSTOMER_STR_WK_CID:
-+		ret = rtw_customer_str_cmd_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
-+		break;
-+#endif
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	case RSON_SCAN_WK_CID:
-+		rtw_rson_scan_cmd_hdl(padapter, pdrvextra_cmd->type);
-+		break;
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	case MGNT_TX_WK_CID:
-+		ret = rtw_mgnt_tx_handler(padapter, pdrvextra_cmd->pbuf);
-+		break;
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+#if (defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)) || defined(CONFIG_IOCTL_CFG80211)
-+	case ROCH_WK_CID:
-+		ret = rtw_roch_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
-+		break;
-+#endif /* (defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)) || defined(CONFIG_IOCTL_CFG80211) */
-+
-+#ifdef CONFIG_MCC_MODE
-+	case MCC_CMD_WK_CID:
-+		ret = rtw_mcc_cmd_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
-+		break;
-+#endif /* CONFIG_MCC_MODE */
-+#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW)
-+	case REQ_PER_CMD_WK_CID:
-+		ret = rtw_req_per_cmd_hdl(padapter);
-+		break;
-+#endif
-+#ifdef CONFIG_SUPPORT_STATIC_SMPS
-+	case SSMPS_WK_CID :
-+		rtw_ssmps_wk_hdl(padapter, (struct ssmps_cmd_parm *)pdrvextra_cmd->pbuf);
-+		break;
-+#endif
-+#ifdef CONFIG_CTRL_TXSS_BY_TP
-+	case TXSS_WK_CID :
-+		rtw_ctrl_txss_wk_hdl(padapter, (struct txss_cmd_parm *)pdrvextra_cmd->pbuf);
-+		break;
-+#endif
-+	case AC_PARM_CMD_WK_CID:
-+		rtw_ac_parm_cmd_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type);
-+		break;
-+#ifdef CONFIG_AP_MODE
-+	case STOP_AP_WK_CID:
-+		stop_ap_hdl(padapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	case TBTX_CONTROL_TX_WK_CID:
-+		tx_control_hdl(padapter);
-+		break;
-+#endif
-+	default:
-+		break;
-+	}
-+
-+	if (pdrvextra_cmd->pbuf && pdrvextra_cmd->size > 0)
-+		rtw_mfree(pdrvextra_cmd->pbuf, pdrvextra_cmd->size);
-+
-+	return ret;
-+}
-+
-+void rtw_survey_cmd_callback(_adapter	*padapter ,  struct cmd_obj *pcmd)
-+{
-+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+
-+	if (pcmd->res == H2C_DROPPED) {
-+		/* TODO: cancel timer and do timeout handler directly... */
-+		/* need to make timeout handlerOS independent */
-+		mlme_set_scan_to_timer(pmlmepriv, 1);
-+	} else if (pcmd->res != H2C_SUCCESS) {
-+		mlme_set_scan_to_timer(pmlmepriv, 1);
-+	}
-+
-+	/* free cmd */
-+	rtw_free_cmd_obj(pcmd);
-+
-+}
-+void rtw_disassoc_cmd_callback(_adapter	*padapter,  struct cmd_obj *pcmd)
-+{
-+	_irqL	irqL;
-+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+
-+	if (pcmd->res != H2C_SUCCESS) {
-+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+		set_fwstate(pmlmepriv, WIFI_ASOC_STATE);
-+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+		goto exit;
-+	}
-+#ifdef CONFIG_BR_EXT
-+	else /* clear bridge database */
-+		nat25_db_cleanup(padapter);
-+#endif /* CONFIG_BR_EXT */
-+
-+	/* free cmd */
-+	rtw_free_cmd_obj(pcmd);
-+
-+exit:
-+	return;
-+}
-+
-+void rtw_joinbss_cmd_callback(_adapter	*padapter,  struct cmd_obj *pcmd)
-+{
-+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+
-+	if (pcmd->res == H2C_DROPPED) {
-+		/* TODO: cancel timer and do timeout handler directly... */
-+		/* need to make timeout handlerOS independent */
-+		_set_timer(&pmlmepriv->assoc_timer, 1);
-+	} else if (pcmd->res != H2C_SUCCESS)
-+		_set_timer(&pmlmepriv->assoc_timer, 1);
-+
-+	rtw_free_cmd_obj(pcmd);
-+
-+}
-+
-+void rtw_create_ibss_post_hdl(_adapter *padapter, int status)
-+{
-+	_irqL irqL;
-+	struct wlan_network *pwlan = NULL;
-+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network;
-+	struct wlan_network *mlme_cur_network = &(pmlmepriv->cur_network);
-+
-+	if (status != H2C_SUCCESS)
-+		_set_timer(&pmlmepriv->assoc_timer, 1);
-+
-+	_cancel_timer_ex(&pmlmepriv->assoc_timer);
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+	{
-+		_irqL irqL;
-+
-+		pwlan = _rtw_alloc_network(pmlmepriv);
-+		_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+		if (pwlan == NULL) {
-+			pwlan = rtw_get_oldest_wlan_network(&pmlmepriv->scanned_queue);
-+			if (pwlan == NULL) {
-+				_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+				goto createbss_cmd_fail;
-+			}
-+			pwlan->last_scanned = rtw_get_current_time();
-+		} else
-+			rtw_list_insert_tail(&(pwlan->list), &pmlmepriv->scanned_queue.queue);
-+
-+		pdev_network->Length = get_WLAN_BSSID_EX_sz(pdev_network);
-+		_rtw_memcpy(&(pwlan->network), pdev_network, pdev_network->Length);
-+		/* pwlan->fixed = _TRUE; */
-+
-+		/* copy pdev_network information to pmlmepriv->cur_network */
-+		_rtw_memcpy(&mlme_cur_network->network, pdev_network, (get_WLAN_BSSID_EX_sz(pdev_network)));
-+
-+#if 0
-+		/* reset DSConfig */
-+		mlme_cur_network->network.Configuration.DSConfig = (u32)rtw_ch2freq(pdev_network->Configuration.DSConfig);
-+#endif
-+
-+		_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
-+		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+		/* we will set WIFI_ASOC_STATE when there is one more sat to join us (rtw_stassoc_event_callback) */
-+	}
-+
-+createbss_cmd_fail:
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+	return;
-+}
-+
-+
-+
-+void rtw_setstaKey_cmdrsp_callback(_adapter	*padapter ,  struct cmd_obj *pcmd)
-+{
-+
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct set_stakey_rsp *psetstakey_rsp = (struct set_stakey_rsp *)(pcmd->rsp);
-+	struct sta_info	*psta = rtw_get_stainfo(pstapriv, psetstakey_rsp->addr);
-+
-+
-+	if (psta == NULL) {
-+		goto exit;
-+	}
-+
-+	/* psta->cmn.aid = psta->cmn.mac_id = psetstakey_rsp->keyid; */ /* CAM_ID(CAM_ENTRY) */
-+
-+exit:
-+
-+	rtw_free_cmd_obj(pcmd);
-+
-+
-+}
-+
-+void rtw_getrttbl_cmd_cmdrsp_callback(_adapter	*padapter,  struct cmd_obj *pcmd)
-+{
-+
-+	rtw_free_cmd_obj(pcmd);
-+#ifdef CONFIG_MP_INCLUDED
-+	if (padapter->registrypriv.mp_mode == 1)
-+		padapter->mppriv.workparam.bcompleted = _TRUE;
-+#endif
-+
-+
-+}
-+
-+u8 set_txq_params_cmd(_adapter *adapter, u32 ac_parm, u8 ac_type)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	u8 *ac_parm_buf = NULL;
-+	u8 sz;
-+	u8 res = _SUCCESS;
-+
-+
-+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (cmdobj == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	sz = sizeof(ac_parm);
-+	ac_parm_buf = rtw_zmalloc(sz);
-+	if (ac_parm_buf == NULL) {
-+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = AC_PARM_CMD_WK_CID;
-+	pdrvextra_cmd_parm->type = ac_type;
-+	pdrvextra_cmd_parm->size = sz;
-+	pdrvextra_cmd_parm->pbuf = ac_parm_buf;
-+
-+	_rtw_memcpy(ac_parm_buf, &ac_parm, sz);
-+
-+	init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+	res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+
-+exit:
-+	return res;
-+}
-diff --git a/drivers/staging/rtl8723cs/core/rtw_debug.c b/drivers/staging/rtl8723cs/core/rtw_debug.c
-new file mode 100644
-index 000000000000..d1a41e1908dd
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_debug.c
-@@ -0,0 +1,8306 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_DEBUG_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#ifdef CONFIG_RTW_DEBUG
-+const char *rtw_log_level_str[] = {
-+	"_DRV_NONE_ = 0",
-+	"_DRV_ALWAYS_ = 1",
-+	"_DRV_ERR_ = 2",
-+	"_DRV_WARNING_ = 3",
-+	"_DRV_INFO_ = 4",
-+	"_DRV_DEBUG_ = 5",
-+	"_DRV_MAX_ = 6",
-+};
-+#endif
-+
-+#ifdef CONFIG_DEBUG_RTL871X
-+	u64 GlobalDebugComponents = 0;
-+#endif /* CONFIG_DEBUG_RTL871X */
-+
-+#include <rtw_version.h>
-+
-+#ifdef CONFIG_TDLS
-+	#define TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE	41
-+#endif
-+
-+void dump_drv_version(void *sel)
-+{
-+	RTW_PRINT_SEL(sel, "%s %s\n", DRV_NAME, DRIVERVERSION);
-+	RTW_PRINT_SEL(sel, "build time: %s %s\n", __DATE__, __TIME__);
-+}
-+
-+#ifdef CONFIG_PROC_DEBUG
-+void dump_drv_cfg(void *sel)
-+{
-+extern uint rtw_recvbuf_nr;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
-+	char *kernel_version = utsname()->release;
-+
-+	RTW_PRINT_SEL(sel, "\nKernel Version: %s\n", kernel_version);
-+#endif
-+
-+	RTW_PRINT_SEL(sel, "Driver Version: %s\n", DRIVERVERSION);
-+	RTW_PRINT_SEL(sel, "------------------------------------------------\n");
-+#ifdef CONFIG_IOCTL_CFG80211
-+	RTW_PRINT_SEL(sel, "CFG80211\n");
-+#ifdef RTW_USE_CFG80211_STA_EVENT
-+	RTW_PRINT_SEL(sel, "RTW_USE_CFG80211_STA_EVENT\n");
-+#endif
-+	#ifdef CONFIG_RADIO_WORK
-+	RTW_PRINT_SEL(sel, "CONFIG_RADIO_WORK\n");
-+	#endif
-+#else
-+	RTW_PRINT_SEL(sel, "WEXT\n");
-+#endif
-+
-+	RTW_PRINT_SEL(sel, "DBG:%d\n", DBG);
-+#ifdef CONFIG_RTW_DEBUG
-+	RTW_PRINT_SEL(sel, "CONFIG_RTW_DEBUG\n");
-+#endif
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	RTW_PRINT_SEL(sel, "CONFIG_CONCURRENT_MODE\n");
-+#endif
-+
-+#ifdef CONFIG_POWER_SAVING
-+	RTW_PRINT_SEL(sel, "CONFIG_POWER_SAVING\n");
-+	#ifdef CONFIG_IPS
-+	RTW_PRINT_SEL(sel, "CONFIG_IPS\n");
-+	#endif
-+	#ifdef CONFIG_LPS
-+		RTW_PRINT_SEL(sel, "CONFIG_LPS\n");
-+		#ifdef CONFIG_LPS_LCLK
-+		RTW_PRINT_SEL(sel, "CONFIG_LPS_LCLK\n");
-+		#ifdef CONFIG_DETECT_CPWM_BY_POLLING
-+		RTW_PRINT_SEL(sel, "CONFIG_DETECT_CPWM_BY_POLLING\n");
-+		#endif
-+		#endif /*CONFIG_LPS_LCLK*/
-+		#ifdef CONFIG_LPS_CHK_BY_TP
-+		RTW_PRINT_SEL(sel, "CONFIG_LPS_CHK_BY_TP\n");
-+		#endif
-+		#ifdef CONFIG_LPS_ACK
-+		RTW_PRINT_SEL(sel, "CONFIG_LPS_ACK\n");
-+		#endif
-+	#endif/*CONFIG_LPS*/
-+#endif
-+
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+	RTW_PRINT_SEL(sel, "LOAD_PHY_PARA_FROM_FILE - REALTEK_CONFIG_PATH=%s\n", REALTEK_CONFIG_PATH);
-+	#if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER)
-+	RTW_PRINT_SEL(sel, "LOAD_PHY_PARA_FROM_FILE - REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER\n");
-+	#endif
-+
-+/* configurations about TX power */
-+#ifdef CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY
-+	RTW_PRINT_SEL(sel, "CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY\n");
-+#endif
-+#ifdef CONFIG_CALIBRATE_TX_POWER_TO_MAX
-+	RTW_PRINT_SEL(sel, "CONFIG_CALIBRATE_TX_POWER_TO_MAX\n");
-+#endif
-+#endif
-+	RTW_PRINT_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT=0x%02x\n", RTW_DEF_MODULE_REGULATORY_CERT);
-+
-+	RTW_PRINT_SEL(sel, "CONFIG_TXPWR_BY_RATE=%d\n", CONFIG_TXPWR_BY_RATE);
-+	RTW_PRINT_SEL(sel, "CONFIG_TXPWR_BY_RATE_EN=%d\n", CONFIG_TXPWR_BY_RATE_EN);
-+	RTW_PRINT_SEL(sel, "CONFIG_TXPWR_LIMIT=%d\n", CONFIG_TXPWR_LIMIT);
-+	RTW_PRINT_SEL(sel, "CONFIG_TXPWR_LIMIT_EN=%d\n", CONFIG_TXPWR_LIMIT_EN);
-+
-+
-+#ifdef CONFIG_DISABLE_ODM
-+	RTW_PRINT_SEL(sel, "CONFIG_DISABLE_ODM\n");
-+#endif
-+
-+#ifdef CONFIG_MINIMAL_MEMORY_USAGE
-+	RTW_PRINT_SEL(sel, "CONFIG_MINIMAL_MEMORY_USAGE\n");
-+#endif
-+
-+	RTW_PRINT_SEL(sel, "CONFIG_RTW_ADAPTIVITY_EN = %d\n", CONFIG_RTW_ADAPTIVITY_EN);
-+#if (CONFIG_RTW_ADAPTIVITY_EN)
-+	RTW_PRINT_SEL(sel, "ADAPTIVITY_MODE = %s\n", (CONFIG_RTW_ADAPTIVITY_MODE) ? "carrier_sense" : "normal");
-+#endif
-+
-+#ifdef CONFIG_WOWLAN
-+	RTW_PRINT_SEL(sel, "CONFIG_WOWLAN - ");
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+	RTW_PRINT_SEL(sel, "CONFIG_GPIO_WAKEUP - WAKEUP_GPIO_IDX:%d\n", WAKEUP_GPIO_IDX);
-+#endif
-+#endif
-+
-+#ifdef CONFIG_TDLS
-+	RTW_PRINT_SEL(sel, "CONFIG_TDLS\n");
-+#endif
-+
-+#ifdef CONFIG_RTW_80211R
-+	RTW_PRINT_SEL(sel, "CONFIG_RTW_80211R\n");
-+#endif
-+
-+#ifdef CONFIG_RTW_NETIF_SG
-+	RTW_PRINT_SEL(sel, "CONFIG_RTW_NETIF_SG\n");
-+#endif
-+
-+#ifdef CONFIG_RTW_WIFI_HAL
-+	RTW_PRINT_SEL(sel, "CONFIG_RTW_WIFI_HAL\n");
-+#endif
-+
-+#ifdef RTW_BUSY_DENY_SCAN
-+	RTW_PRINT_SEL(sel, "RTW_BUSY_DENY_SCAN\n");
-+	RTW_PRINT_SEL(sel, "BUSY_TRAFFIC_SCAN_DENY_PERIOD = %u ms\n", \
-+		      BUSY_TRAFFIC_SCAN_DENY_PERIOD);
-+#endif
-+
-+#ifdef CONFIG_RTW_TPT_MODE
-+	RTW_PRINT_SEL(sel, "CONFIG_RTW_TPT_MODE\n");
-+#endif 
-+
-+#ifdef CONFIG_USB_HCI
-+#ifdef CONFIG_SUPPORT_USB_INT
-+	RTW_PRINT_SEL(sel, "CONFIG_SUPPORT_USB_INT\n");
-+#endif
-+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
-+	RTW_PRINT_SEL(sel, "CONFIG_USB_INTERRUPT_IN_PIPE\n");
-+#endif
-+#ifdef CONFIG_USB_TX_AGGREGATION
-+	RTW_PRINT_SEL(sel, "CONFIG_USB_TX_AGGREGATION\n");
-+#endif
-+#ifdef CONFIG_USB_RX_AGGREGATION
-+	RTW_PRINT_SEL(sel, "CONFIG_USB_RX_AGGREGATION\n");
-+#endif
-+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX
-+	RTW_PRINT_SEL(sel, "CONFIG_USE_USB_BUFFER_ALLOC_TX\n");
-+#endif
-+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
-+	RTW_PRINT_SEL(sel, "CONFIG_USE_USB_BUFFER_ALLOC_RX\n");
-+#endif
-+#ifdef CONFIG_PREALLOC_RECV_SKB
-+	RTW_PRINT_SEL(sel, "CONFIG_PREALLOC_RECV_SKB\n");
-+#endif
-+#ifdef CONFIG_FIX_NR_BULKIN_BUFFER
-+	RTW_PRINT_SEL(sel, "CONFIG_FIX_NR_BULKIN_BUFFER\n");
-+#endif
-+#endif /*CONFIG_USB_HCI*/
-+
-+#ifdef CONFIG_SDIO_HCI
-+#ifdef CONFIG_TX_AGGREGATION
-+	RTW_PRINT_SEL(sel, "CONFIG_TX_AGGREGATION\n");
-+#endif
-+#ifdef CONFIG_RX_AGGREGATION
-+	RTW_PRINT_SEL(sel, "CONFIG_RX_AGGREGATION\n");
-+#endif
-+#ifdef RTW_XMIT_THREAD_HIGH_PRIORITY
-+	RTW_PRINT_SEL(sel, "RTW_XMIT_THREAD_HIGH_PRIORITY\n");
-+#endif
-+#ifdef RTW_XMIT_THREAD_HIGH_PRIORITY_AGG
-+	RTW_PRINT_SEL(sel, "RTW_XMIT_THREAD_HIGH_PRIORITY_AGG\n");
-+#endif
-+
-+#ifdef DBG_SDIO
-+	RTW_PRINT_SEL(sel, "DBG_SDIO = %d\n", DBG_SDIO);
-+#endif
-+#endif /*CONFIG_SDIO_HCI*/
-+
-+#ifdef CONFIG_PCI_HCI
-+#endif
-+
-+	RTW_PRINT_SEL(sel, "CONFIG_IFACE_NUMBER = %d\n", CONFIG_IFACE_NUMBER);
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+	RTW_PRINT_SEL(sel, "CONFIG_MI_WITH_MBSSID_CAM\n");
-+#endif
-+#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+	RTW_PRINT_SEL(sel, "CONFIG_SWTIMER_BASED_TXBCN\n");
-+#endif
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+	RTW_PRINT_SEL(sel, "CONFIG_FW_HANDLE_TXBCN\n");
-+	RTW_PRINT_SEL(sel, "CONFIG_LIMITED_AP_NUM = %d\n", CONFIG_LIMITED_AP_NUM);
-+#endif
-+#ifdef CONFIG_CLIENT_PORT_CFG
-+	RTW_PRINT_SEL(sel, "CONFIG_CLIENT_PORT_CFG\n");
-+#endif
-+#ifdef CONFIG_PCI_TX_POLLING
-+	RTW_PRINT_SEL(sel, "CONFIG_PCI_TX_POLLING\n");
-+#endif
-+	RTW_PRINT_SEL(sel, "CONFIG_RTW_UP_MAPPING_RULE = %s\n", (CONFIG_RTW_UP_MAPPING_RULE == 1) ? "dscp" : "tos");
-+
-+	RTW_PRINT_SEL(sel, "\n=== XMIT-INFO ===\n");
-+	RTW_PRINT_SEL(sel, "NR_XMITFRAME = %d\n", NR_XMITFRAME);
-+	RTW_PRINT_SEL(sel, "NR_XMITBUFF = %d\n", NR_XMITBUFF);
-+	RTW_PRINT_SEL(sel, "MAX_XMITBUF_SZ = %d\n", MAX_XMITBUF_SZ);
-+	RTW_PRINT_SEL(sel, "NR_XMIT_EXTBUFF = %d\n", NR_XMIT_EXTBUFF);
-+	RTW_PRINT_SEL(sel, "MAX_XMIT_EXTBUF_SZ = %d\n", MAX_XMIT_EXTBUF_SZ);
-+	RTW_PRINT_SEL(sel, "MAX_CMDBUF_SZ = %d\n", MAX_CMDBUF_SZ);
-+
-+	RTW_PRINT_SEL(sel, "\n=== RECV-INFO ===\n");
-+	RTW_PRINT_SEL(sel, "NR_RECVFRAME = %d\n", NR_RECVFRAME);
-+	RTW_PRINT_SEL(sel, "NR_RECVBUFF = %d, rtw_recvbuf_nr = %d\n", NR_RECVBUFF, rtw_recvbuf_nr);
-+	RTW_PRINT_SEL(sel, "MAX_RECVBUF_SZ = %d\n", MAX_RECVBUF_SZ);
-+
-+}
-+#endif /*	CONFIG_PROC_DEBUG	*/
-+
-+
-+void dump_log_level(void *sel)
-+{
-+#ifdef CONFIG_RTW_DEBUG
-+	int i;
-+
-+	RTW_PRINT_SEL(sel, "drv_log_level:%d\n", rtw_drv_log_level);
-+	for (i = 0; i <= _DRV_MAX_; i++) {
-+		if (rtw_log_level_str[i])
-+			RTW_PRINT_SEL(sel, "%c %s = %d\n",
-+				(rtw_drv_log_level == i) ? '+' : ' ', rtw_log_level_str[i], i);
-+	}
-+#else
-+	RTW_PRINT_SEL(sel, "CONFIG_RTW_DEBUG is disabled\n");
-+#endif
-+}
-+
-+#ifdef CONFIG_SDIO_HCI
-+void sd_f0_reg_dump(void *sel, _adapter *adapter)
-+{
-+	int i;
-+
-+	for (i = 0x0; i <= 0xff; i++) {
-+		if (i % 16 == 0)
-+			RTW_PRINT_SEL(sel, "0x%02x ", i);
-+
-+		_RTW_PRINT_SEL(sel, "%02x ", rtw_sd_f0_read8(adapter, i));
-+
-+		if (i % 16 == 15)
-+			_RTW_PRINT_SEL(sel, "\n");
-+		else if (i % 8 == 7)
-+			_RTW_PRINT_SEL(sel, "\t");
-+	}
-+}
-+
-+void sdio_local_reg_dump(void *sel, _adapter *adapter)
-+{
-+	int i, j = 1;
-+
-+	for (i = 0x0; i < 0x100; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT_SEL(sel, "0x%02x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, (0x1025 << 16) | i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT_SEL(sel, "\n");
-+	}
-+}
-+#endif /* CONFIG_SDIO_HCI */
-+
-+void mac_reg_dump(void *sel, _adapter *adapter)
-+{
-+	int i, j = 1;
-+
-+	RTW_PRINT_SEL(sel, "======= MAC REG =======\n");
-+
-+	for (i = 0x0; i < 0x800; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT_SEL(sel, "\n");
-+	}
-+
-+#ifdef CONFIG_RTL8814A
-+	{
-+		for (i = 0x1000; i < 0x1650; i += 4) {
-+			if (j % 4 == 1)
-+				RTW_PRINT_SEL(sel, "0x%04x", i);
-+			_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+			if ((j++) % 4 == 0)
-+				_RTW_PRINT_SEL(sel, "\n");
-+		}
-+	}
-+#endif /* CONFIG_RTL8814A */
-+
-+#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
-+	for (i = 0x1000; i < 0x1800; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT_SEL(sel, "\n");
-+	}
-+#endif /* CONFIG_RTL8822B  or 8821c*/
-+
-+#if defined(CONFIG_RTL8192F)
-+	for (i = 0x1000; i < 0x1100; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	for (i = 0x1300; i < 0x1360; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT_SEL(sel, "\n");
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8814B)
-+	for (i = 0x2000; i < 0x2800; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT_SEL(sel, "\n");
-+	}
-+
-+	for (i = 0x3000; i < 0x3800; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT_SEL(sel, "\n");
-+	}
-+#endif
-+
-+}
-+
-+void bb_reg_dump(void *sel, _adapter *adapter)
-+{
-+	int i, j = 1;
-+
-+	RTW_PRINT_SEL(sel, "======= BB REG =======\n");
-+	for (i = 0x800; i < 0x1000; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT_SEL(sel, "\n");
-+	}
-+
-+#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
-+	for (i = 0x1800; i < 0x2000; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT_SEL(sel, "\n");
-+	}
-+#endif /* CONFIG_RTL8822B */
-+
-+#if defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
-+	for (i = 0x2c00; i < 0x2c60; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT_SEL(sel, "\n");
-+	}
-+
-+	for (i = 0x2d00; i < 0x2df0; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT_SEL(sel, "\n");
-+	}	
-+
-+	for (i = 0x4000; i < 0x4060; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT_SEL(sel, "\n");
-+	}	
-+
-+	for (i = 0x4100; i < 0x4200; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT_SEL(sel, "\n");
-+	}	
-+
-+#endif /* CONFIG_RTL8822C || CONFIG_RTL8814B */
-+
-+#if defined(CONFIG_RTL8814B)
-+	for (i = 0x5200; i < 0x5400; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT_SEL(sel, "\n");
-+	}
-+#endif /* CONFIG_RTL8814B */
-+}
-+
-+void bb_reg_dump_ex(void *sel, _adapter *adapter)
-+{
-+	int i;
-+
-+	RTW_PRINT_SEL(sel, "======= BB REG =======\n");
-+	for (i = 0x800; i < 0x1000; i += 4) {
-+		RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+
-+#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
-+	for (i = 0x1800; i < 0x2000; i += 4) {
-+		RTW_PRINT_SEL(sel, "0x%04x", i);
-+		_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+#endif /* CONFIG_RTL8822B */
-+}
-+
-+void rf_reg_dump(void *sel, _adapter *adapter)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	int i, j = 1, path;
-+	u32 value;
-+	u8 path_nums = hal_spec->rf_reg_path_num;
-+
-+	RTW_PRINT_SEL(sel, "======= RF REG =======\n");
-+
-+	for (path = 0; path < path_nums; path++) {
-+		RTW_PRINT_SEL(sel, "RF_Path(%x)\n", path);
-+		for (i = 0; i < 0x100; i++) {
-+			value = rtw_hal_read_rfreg(adapter, path, i, 0xffffffff);
-+			if (j % 4 == 1)
-+				RTW_PRINT_SEL(sel, "0x%02x ", i);
-+			_RTW_PRINT_SEL(sel, " 0x%08x ", value);
-+			if ((j++) % 4 == 0)
-+				_RTW_PRINT_SEL(sel, "\n");
-+		}
-+	}
-+}
-+
-+void rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos)
-+{
-+	struct recv_priv *precvpriv = &(adapter->recvpriv);
-+	if (precvpriv->sink_udpport > 0) {
-+		if (*((u16 *)(ehdr_pos + 0x24)) == cpu_to_be16(precvpriv->sink_udpport)) {
-+			precvpriv->pre_rtp_rxseq = precvpriv->cur_rtp_rxseq;
-+			precvpriv->cur_rtp_rxseq = be16_to_cpu(*((u16 *)(ehdr_pos + 0x2C)));
-+			if (precvpriv->pre_rtp_rxseq + 1 != precvpriv->cur_rtp_rxseq) {
-+				if(precvpriv->pre_rtp_rxseq == 65535 ) {
-+					if( precvpriv->cur_rtp_rxseq != 0) {
-+						RTW_INFO("%s : RTP Seq num from %d to %d\n", __FUNCTION__, precvpriv->pre_rtp_rxseq, precvpriv->cur_rtp_rxseq);
-+					}
-+				} else {
-+					RTW_INFO("%s : RTP Seq num from %d to %d\n", __FUNCTION__, precvpriv->pre_rtp_rxseq, precvpriv->cur_rtp_rxseq);
-+				}
-+			}	
-+		}
-+	}
-+}
-+
-+void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta)
-+{
-+	struct recv_reorder_ctrl *reorder_ctl;
-+	int i;
-+
-+	for (i = 0; i < 16; i++) {
-+		reorder_ctl = &sta->recvreorder_ctrl[i];
-+		if (reorder_ctl->ampdu_size != RX_AMPDU_SIZE_INVALID || reorder_ctl->indicate_seq != 0xFFFF) {
-+			RTW_PRINT_SEL(sel, "tid=%d, enable=%d, ampdu_size=%u, indicate_seq=%u\n"
-+				, i, reorder_ctl->enable, reorder_ctl->ampdu_size, reorder_ctl->indicate_seq
-+				     );
-+		}
-+	}
-+}
-+
-+void dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj)
-+{
-+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
-+	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
-+	u8 bw;
-+
-+	RTW_PRINT_SEL(sel, "%-6s", "bw");
-+	if (hal_chk_proto_cap(adapter, PROTO_CAP_11AC))
-+		_RTW_PRINT_SEL(sel, " %-15s", "vht");
-+
-+	_RTW_PRINT_SEL(sel, " %-11s %-4s %-3s\n", "ht", "ofdm", "cck");
-+
-+	for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {
-+		if (!hal_is_bw_support(adapter, bw))
-+			continue;
-+
-+		RTW_PRINT_SEL(sel, "%6s", ch_width_str(bw));
-+		if (hal_chk_proto_cap(adapter, PROTO_CAP_11AC)) {
-+			_RTW_PRINT_SEL(sel, " %03x %03x %03x %03x"
-+				, RATE_BMP_GET_VHT_4SS(rfctl->rate_bmp_vht_by_bw[bw])
-+				, RATE_BMP_GET_VHT_3SS(rfctl->rate_bmp_vht_by_bw[bw])
-+				, RATE_BMP_GET_VHT_2SS(rfctl->rate_bmp_vht_by_bw[bw])
-+				, RATE_BMP_GET_VHT_1SS(rfctl->rate_bmp_vht_by_bw[bw])
-+			);
-+		}
-+
-+		_RTW_PRINT_SEL(sel, " %02x %02x %02x %02x"
-+			, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_4SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
-+			, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_3SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
-+			, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_2SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
-+			, bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_1SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
-+		);
-+
-+		_RTW_PRINT_SEL(sel, "  %03x   %01x\n"
-+			, bw <= CHANNEL_WIDTH_20 ? RATE_BMP_GET_OFDM(rfctl->rate_bmp_cck_ofdm) : 0
-+			, bw <= CHANNEL_WIDTH_20 ? RATE_BMP_GET_CCK(rfctl->rate_bmp_cck_ofdm) : 0
-+		);
-+	}
-+}
-+
-+void dump_adapters_status(void *sel, struct dvobj_priv *dvobj)
-+{
-+#if defined(CONFIG_RTW_DEBUG) || defined(CONFIG_PROC_DEBUG)
-+	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
-+	int i;
-+	_adapter *iface;
-+	u8 u_ch, u_bw, u_offset;
-+#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG)
-+	char str_val[64] = {'\0'};
-+#endif
-+	dump_mi_status(sel, dvobj);
-+
-+#if defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)
-+	RTW_PRINT_SEL(sel, "[AP] LIMITED_AP_NUM:%d\n", CONFIG_LIMITED_AP_NUM);
-+	RTW_PRINT_SEL(sel, "[AP] vap_map:0x%02x\n", dvobj->vap_map);
-+#endif
-+#ifdef CONFIG_HW_P0_TSF_SYNC
-+	RTW_PRINT_SEL(sel, "[AP] p0 tsf sync port = %d\n", dvobj->p0_tsf.sync_port);
-+	RTW_PRINT_SEL(sel, "[AP] p0 tsf timer offset = %d\n", dvobj->p0_tsf.offset);
-+#endif
-+#ifdef CONFIG_CLIENT_PORT_CFG
-+	RTW_PRINT_SEL(sel, "[CLT] clt_num = %d\n", dvobj->clt_port.num);
-+	RTW_PRINT_SEL(sel, "[CLT] clt_map = 0x%02x\n", dvobj->clt_port.bmp);
-+#endif
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+	RTW_PRINT_SEL(sel, "[MI] default port id:%d\n\n", dvobj->dft.port_id);
-+#endif /* CONFIG_FW_MULTI_PORT_SUPPORT */
-+
-+	RTW_PRINT_SEL(sel, "dev status:%s%s\n\n"
-+		, dev_is_surprise_removed(dvobj) ? " SR" : ""
-+		, dev_is_drv_stopped(dvobj) ? " DS" : ""
-+	);
-+
-+#ifdef CONFIG_P2P
-+#define P2P_INFO_TITLE_FMT	" %-3s %-4s"
-+#define P2P_INFO_TITLE_ARG	, "lch", "p2ps"
-+#ifdef CONFIG_IOCTL_CFG80211
-+#define P2P_INFO_VALUE_FMT	" %3u %c%3u"
-+#define P2P_INFO_VALUE_ARG	, iface->wdinfo.listen_channel, iface->wdev_data.p2p_enabled ? 'e' : ' ', rtw_p2p_state(&iface->wdinfo)
-+#else
-+#define P2P_INFO_VALUE_FMT	" %3u %4u"
-+#define P2P_INFO_VALUE_ARG	, iface->wdinfo.listen_channel, rtw_p2p_state(&iface->wdinfo)
-+#endif
-+#define P2P_INFO_DASH		"---------"
-+#else
-+#define P2P_INFO_TITLE_FMT	""
-+#define P2P_INFO_TITLE_ARG
-+#define P2P_INFO_VALUE_FMT	""
-+#define P2P_INFO_VALUE_ARG
-+#define P2P_INFO_DASH
-+#endif
-+
-+#ifdef DBG_TSF_UPDATE
-+#define TSF_PAUSE_TIME_TITLE_FMT " %-5s"
-+#define TSF_PAUSE_TIME_TITLE_ARG , "tsfup"
-+#define TSF_PAUSE_TIME_VALUE_FMT " %5d"
-+#define TSF_PAUSE_TIME_VALUE_ARG , ((iface->mlmeextpriv.tsf_update_required && iface->mlmeextpriv.tsf_update_pause_stime) ? (rtw_get_passing_time_ms(iface->mlmeextpriv.tsf_update_pause_stime) > 99999 ? 99999 : rtw_get_passing_time_ms(iface->mlmeextpriv.tsf_update_pause_stime)) : 0)
-+#else
-+#define TSF_PAUSE_TIME_TITLE_FMT ""
-+#define TSF_PAUSE_TIME_TITLE_ARG
-+#define TSF_PAUSE_TIME_VALUE_FMT ""
-+#define TSF_PAUSE_TIME_VALUE_ARG
-+#endif
-+
-+#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG)
-+#define INFO_FMT	" %-4s"
-+#define INFO_ARG	, "info"
-+#define INFO_CNT_FMT	" %-20s"
-+#define INFO_CNT_ARG	, str_val
-+#else
-+#define INFO_FMT	""
-+#define INFO_ARG
-+#define INFO_CNT_FMT	""
-+#define INFO_CNT_ARG
-+#endif
-+
-+	RTW_PRINT_SEL(sel, "%-2s %-15s %c %-3s %-3s %-3s %-17s %-4s %-7s %-5s"
-+		P2P_INFO_TITLE_FMT
-+		TSF_PAUSE_TIME_TITLE_FMT
-+		" %s"INFO_FMT"\n"
-+		, "id", "ifname", ' ', "bup", "nup", "ncd", "macaddr", "port", "ch", "class"
-+		P2P_INFO_TITLE_ARG
-+		TSF_PAUSE_TIME_TITLE_ARG
-+		, "status"INFO_ARG);
-+
-+	RTW_PRINT_SEL(sel, "---------------------------------------------------------------"
-+		P2P_INFO_DASH
-+		"-------\n");
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface) {
-+			#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG)
-+			_rtw_memset(&str_val, '\0', sizeof(str_val));
-+			#endif
-+			#if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)
-+			if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {
-+				u8 len;
-+				char *p = str_val;
-+				char tmp_str[10] = {'\0'};
-+
-+				len = snprintf(tmp_str, sizeof(tmp_str), "%s", "ap_id:");
-+				strncpy(p, tmp_str, len);
-+				p += len;
-+				_rtw_memset(&tmp_str, '\0', sizeof(tmp_str));
-+				#ifdef DBG_HW_PORT
-+				len = snprintf(tmp_str, sizeof(tmp_str), "%d (%d,%d)", iface->vap_id, iface->hw_port, iface->client_port);
-+				#else
-+				len = snprintf(tmp_str, sizeof(tmp_str), "%d", iface->vap_id);
-+				#endif
-+				strncpy(p, tmp_str, len);
-+			}
-+			#endif
-+			#ifdef CONFIG_CLIENT_PORT_CFG
-+			if (MLME_IS_STA(iface)) {
-+				u8 len;
-+				char *p = str_val;
-+				char tmp_str[10] = {'\0'};
-+
-+				len = snprintf(tmp_str, sizeof(tmp_str), "%s", "c_pid:");
-+				strncpy(p, tmp_str, len);
-+				p += len;
-+				_rtw_memset(&tmp_str, '\0', sizeof(tmp_str));
-+				#ifdef DBG_HW_PORT
-+				len = snprintf(tmp_str, sizeof(tmp_str), "%d (%d,%d)", iface->client_port, iface->hw_port, iface->client_port);
-+				#else
-+				len = snprintf(tmp_str, sizeof(tmp_str), "%d", iface->client_port);
-+				#endif
-+				strncpy(p, tmp_str, len);
-+			}
-+			#endif
-+
-+			RTW_PRINT_SEL(sel, "%2d %-15s %c %3u %3u %3u "MAC_FMT" %4hhu %3u,%u,%u %5u"
-+				P2P_INFO_VALUE_FMT
-+				TSF_PAUSE_TIME_VALUE_FMT
-+				" "MLME_STATE_FMT" " INFO_CNT_FMT"\n"
-+				, i, iface->registered ? ADPT_ARG(iface) : NULL
-+				, iface->registered ? 'R' : ' '
-+				, iface->bup
-+				, iface->netif_up
-+				, iface->net_closed
-+				, MAC_ARG(adapter_mac_addr(iface))
-+				, rtw_hal_get_port(iface)
-+				, iface->mlmeextpriv.cur_channel
-+				, iface->mlmeextpriv.cur_bwmode
-+				, iface->mlmeextpriv.cur_ch_offset
-+				, rtw_get_op_class_by_chbw(iface->mlmeextpriv.cur_channel
-+					, iface->mlmeextpriv.cur_bwmode
-+					, iface->mlmeextpriv.cur_ch_offset)
-+				P2P_INFO_VALUE_ARG
-+				TSF_PAUSE_TIME_VALUE_ARG
-+				, MLME_STATE_ARG(iface)
-+				INFO_CNT_ARG
-+			);
-+		}
-+	}
-+
-+	RTW_PRINT_SEL(sel, "---------------------------------------------------------------"
-+		P2P_INFO_DASH
-+		"-------\n");
-+
-+	if (rtw_mi_get_ch_setting_union(dvobj_get_primary_adapter(dvobj), &u_ch, &u_bw, &u_offset))
-+		RTW_PRINT_SEL(sel, "%55s %3u,%u,%u %5u\n"
-+			, "union:"
-+			, u_ch, u_bw, u_offset, rtw_get_op_class_by_chbw(u_ch, u_bw, u_offset));
-+
-+	RTW_PRINT_SEL(sel, "%55s %3u,%u,%u offch_state:%d\n"
-+		, "oper:"
-+		, dvobj->oper_channel
-+		, dvobj->oper_bwmode
-+		, dvobj->oper_ch_offset
-+		, rfctl->offch_state
-+	);
-+
-+#ifdef CONFIG_DFS_MASTER
-+	if (rfctl->radar_detect_ch != 0) {
-+		RTW_PRINT_SEL(sel, "%55s %3u,%u,%u"
-+			, "radar_detect:"
-+			, rfctl->radar_detect_ch
-+			, rfctl->radar_detect_bw
-+			, rfctl->radar_detect_offset
-+		);
-+
-+		if (rfctl->radar_detect_by_others)
-+			_RTW_PRINT_SEL(sel, ", by AP of STA link");
-+		else {
-+			u32 non_ocp_ms;
-+			u32 cac_ms;
-+			u8 dfs_domain = rtw_rfctl_get_dfs_domain(rfctl);
-+
-+			_RTW_PRINT_SEL(sel, ", domain:%s(%u)", rtw_dfs_regd_str(dfs_domain), dfs_domain);
-+
-+			rtw_get_ch_waiting_ms(rfctl
-+				, rfctl->radar_detect_ch
-+				, rfctl->radar_detect_bw
-+				, rfctl->radar_detect_offset
-+				, &non_ocp_ms
-+				, &cac_ms
-+			);
-+
-+			if (non_ocp_ms)
-+				_RTW_PRINT_SEL(sel, ", non_ocp:%d", non_ocp_ms);
-+			if (cac_ms)
-+				_RTW_PRINT_SEL(sel, ", cac:%d", cac_ms);
-+		}
-+
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+#endif /* CONFIG_DFS_MASTER */
-+#endif	/*	CONFIG_RTW_DEBUG || CONFIG_PROC_DEBUG	*/
-+}
-+
-+#if defined(CONFIG_RTW_DEBUG) || defined(CONFIG_PROC_DEBUG)
-+#define SEC_CAM_ENT_ID_TITLE_FMT "%-2s"
-+#define SEC_CAM_ENT_ID_TITLE_ARG "id"
-+#define SEC_CAM_ENT_ID_VALUE_FMT "%2u"
-+#define SEC_CAM_ENT_ID_VALUE_ARG(id) (id)
-+
-+#define SEC_CAM_ENT_TITLE_FMT "%-6s %-17s %-32s %-3s %-8s %-2s %-2s %-5s"
-+#define SEC_CAM_ENT_TITLE_ARG "ctrl", "addr", "key", "kid", "type", "MK", "GK", "valid"
-+#define SEC_CAM_ENT_VALUE_FMT "0x%04x "MAC_FMT" "KEY_FMT" %3u %-8s %2u %2u %5u"
-+#define SEC_CAM_ENT_VALUE_ARG(ent) \
-+	(ent)->ctrl \
-+	, MAC_ARG((ent)->mac) \
-+	, KEY_ARG((ent)->key) \
-+	, ((ent)->ctrl) & 0x03 \
-+	, (((ent)->ctrl) & 0x200) ? \
-+	security_type_str((((ent)->ctrl) >> 2 & 0x7) | _SEC_TYPE_256_) : \
-+	security_type_str(((ent)->ctrl) >> 2 & 0x7) \
-+	, (((ent)->ctrl) >> 5) & 0x01 \
-+	, (((ent)->ctrl) >> 6) & 0x01 \
-+	, (((ent)->ctrl) >> 15) & 0x01
-+
-+void dump_sec_cam_ent(void *sel, struct sec_cam_ent *ent, int id)
-+{
-+	if (id >= 0) {
-+		RTW_PRINT_SEL(sel, SEC_CAM_ENT_ID_VALUE_FMT " " SEC_CAM_ENT_VALUE_FMT"\n"
-+			, SEC_CAM_ENT_ID_VALUE_ARG(id), SEC_CAM_ENT_VALUE_ARG(ent));
-+	} else
-+		RTW_PRINT_SEL(sel, SEC_CAM_ENT_VALUE_FMT"\n", SEC_CAM_ENT_VALUE_ARG(ent));
-+}
-+
-+void dump_sec_cam_ent_title(void *sel, u8 has_id)
-+{
-+	if (has_id) {
-+		RTW_PRINT_SEL(sel, SEC_CAM_ENT_ID_TITLE_FMT " " SEC_CAM_ENT_TITLE_FMT"\n"
-+			, SEC_CAM_ENT_ID_TITLE_ARG, SEC_CAM_ENT_TITLE_ARG);
-+	} else
-+		RTW_PRINT_SEL(sel, SEC_CAM_ENT_TITLE_FMT"\n", SEC_CAM_ENT_TITLE_ARG);
-+}
-+#endif
-+
-+void dump_sec_cam(void *sel, _adapter *adapter)
-+{
-+#if defined(CONFIG_RTW_DEBUG) || defined(CONFIG_PROC_DEBUG)
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	struct sec_cam_ent ent;
-+	int i;
-+
-+	RTW_PRINT_SEL(sel, "HW sec cam:\n");
-+	dump_sec_cam_ent_title(sel, 1);
-+	for (i = 0; i < cam_ctl->num; i++) {
-+		rtw_sec_read_cam_ent(adapter, i, (u8 *)(&ent.ctrl), ent.mac, ent.key);
-+		dump_sec_cam_ent(sel , &ent, i);
-+	}
-+#endif
-+}
-+
-+void dump_sec_cam_cache(void *sel, _adapter *adapter)
-+{
-+#if defined(CONFIG_RTW_DEBUG) || defined(CONFIG_PROC_DEBUG)
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	int i;
-+
-+	RTW_PRINT_SEL(sel, "SW sec cam cache:\n");
-+	dump_sec_cam_ent_title(sel, 1);
-+	for (i = 0; i < cam_ctl->num; i++) {
-+		if (dvobj->cam_cache[i].ctrl != 0)
-+			dump_sec_cam_ent(sel, &dvobj->cam_cache[i], i);
-+	}
-+#endif
-+}
-+
-+static u8 fwdl_test_chksum_fail = 0;
-+static u8 fwdl_test_wintint_rdy_fail = 0;
-+
-+bool rtw_fwdl_test_trigger_chksum_fail(void)
-+{
-+	if (fwdl_test_chksum_fail) {
-+		RTW_PRINT("fwdl test case: trigger chksum_fail\n");
-+		fwdl_test_chksum_fail--;
-+		return _TRUE;
-+	}
-+	return _FALSE;
-+}
-+
-+bool rtw_fwdl_test_trigger_wintint_rdy_fail(void)
-+{
-+	if (fwdl_test_wintint_rdy_fail) {
-+		RTW_PRINT("fwdl test case: trigger wintint_rdy_fail\n");
-+		fwdl_test_wintint_rdy_fail--;
-+		return _TRUE;
-+	}
-+	return _FALSE;
-+}
-+
-+static u8 del_rx_ampdu_test_no_tx_fail = 0;
-+
-+bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void)
-+{
-+	if (del_rx_ampdu_test_no_tx_fail) {
-+		RTW_PRINT("del_rx_ampdu test case: trigger no_tx_fail\n");
-+		del_rx_ampdu_test_no_tx_fail--;
-+		return _TRUE;
-+	}
-+	return _FALSE;
-+}
-+
-+static u32 g_wait_hiq_empty_ms = 0;
-+
-+u32 rtw_get_wait_hiq_empty_ms(void)
-+{
-+	return g_wait_hiq_empty_ms;
-+}
-+
-+static systime sta_linking_test_start_time = 0;
-+static u32 sta_linking_test_wait_ms = 0;
-+static u8 sta_linking_test_force_fail = 0;
-+
-+void rtw_sta_linking_test_set_start(void)
-+{
-+	sta_linking_test_start_time = rtw_get_current_time();
-+}
-+
-+bool rtw_sta_linking_test_wait_done(void)
-+{
-+	return rtw_get_passing_time_ms(sta_linking_test_start_time) >= sta_linking_test_wait_ms;
-+}
-+
-+bool rtw_sta_linking_test_force_fail(void)
-+{
-+	return sta_linking_test_force_fail;
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+static u16 ap_linking_test_force_auth_fail = 0;
-+static u16 ap_linking_test_force_asoc_fail = 0;
-+
-+u16 rtw_ap_linking_test_force_auth_fail(void)
-+{
-+	return ap_linking_test_force_auth_fail;
-+}
-+
-+u16 rtw_ap_linking_test_force_asoc_fail(void)
-+{
-+	return ap_linking_test_force_asoc_fail;
-+}
-+#endif
-+
-+#ifdef CONFIG_PROC_DEBUG
-+int proc_get_defs_param(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+
-+	RTW_PRINT_SEL(m, "%s %15s\n", "lmt_sta", "lmt_time");
-+	RTW_PRINT_SEL(m, "%-15u %-15u\n"
-+		, mlme->defs_lmt_sta
-+		, mlme->defs_lmt_time
-+	);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_defs_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+
-+	char tmp[32];
-+	u32 defs_lmt_sta;
-+	u32 defs_lmt_time;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%u %u", &defs_lmt_sta, &defs_lmt_time);
-+
-+		if (num >= 1)
-+			mlme->defs_lmt_sta = defs_lmt_sta;
-+		if (num >= 2)
-+			mlme->defs_lmt_time = defs_lmt_time;
-+	}
-+
-+	return count;
-+
-+}
-+
-+ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u32 addr, val, len;
-+
-+	if (count < 3) {
-+		RTW_INFO("argument size is less than 3\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%x %x %x", &addr, &val, &len);
-+
-+		if (num !=  3) {
-+			RTW_INFO("invalid write_reg parameter!\n");
-+			return count;
-+		}
-+
-+		switch (len) {
-+		case 1:
-+			rtw_write8(padapter, addr, (u8)val);
-+			break;
-+		case 2:
-+			rtw_write16(padapter, addr, (u16)val);
-+			break;
-+		case 4:
-+			rtw_write32(padapter, addr, val);
-+			break;
-+		default:
-+			RTW_INFO("error write length=%d", len);
-+			break;
-+		}
-+
-+	}
-+
-+	return count;
-+
-+}
-+
-+static u32 proc_get_read_addr = 0xeeeeeeee;
-+static u32 proc_get_read_len = 0x4;
-+
-+int proc_get_read_reg(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (proc_get_read_addr == 0xeeeeeeee) {
-+		RTW_PRINT_SEL(m, "address not initialized\n");
-+		return 0;
-+	}
-+
-+	switch (proc_get_read_len) {
-+	case 1:
-+		RTW_PRINT_SEL(m, "rtw_read8(0x%x)=0x%x\n", proc_get_read_addr, rtw_read8(padapter, proc_get_read_addr));
-+		break;
-+	case 2:
-+		RTW_PRINT_SEL(m, "rtw_read16(0x%x)=0x%x\n", proc_get_read_addr, rtw_read16(padapter, proc_get_read_addr));
-+		break;
-+	case 4:
-+		RTW_PRINT_SEL(m, "rtw_read32(0x%x)=0x%x\n", proc_get_read_addr, rtw_read32(padapter, proc_get_read_addr));
-+		break;
-+	default:
-+		RTW_PRINT_SEL(m, "error read length=%d\n", proc_get_read_len);
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	char tmp[16];
-+	u32 addr, len;
-+
-+	if (count < 2) {
-+		RTW_INFO("argument size is less than 2\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%x %x", &addr, &len);
-+
-+		if (num !=  2) {
-+			RTW_INFO("invalid read_reg parameter!\n");
-+			return count;
-+		}
-+
-+		proc_get_read_addr = addr;
-+
-+		proc_get_read_len = len;
-+	}
-+
-+	return count;
-+
-+}
-+
-+int proc_get_rx_stat(struct seq_file *m, void *v)
-+{
-+	_irqL	 irqL;
-+	_list	*plist, *phead;
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct sta_info *psta = NULL;
-+	struct stainfo_stats	*pstats = NULL;
-+	struct sta_priv		*pstapriv = &(adapter->stapriv);
-+	u32 i, j;
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
-+
-+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+	for (i = 0; i < NUM_STA; i++) {
-+		phead = &(pstapriv->sta_hash[i]);
-+		plist = get_next(phead);
-+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+			plist = get_next(plist);
-+			pstats = &psta->sta_stats;
-+
-+			if (pstats == NULL)
-+				continue;
-+			if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE)
-+				&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)
-+				&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) {
-+				RTW_PRINT_SEL(m, "MAC :\t\t"MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
-+				RTW_PRINT_SEL(m, "data_rx_cnt :\t%llu\n", sta_rx_data_uc_pkts(psta) - pstats->last_rx_data_uc_pkts);
-+				pstats->last_rx_data_uc_pkts = sta_rx_data_uc_pkts(psta);
-+				RTW_PRINT_SEL(m, "duplicate_cnt :\t%u\n", pstats->duplicate_cnt);
-+				pstats->duplicate_cnt = 0;
-+				RTW_PRINT_SEL(m, "rx_per_rate_cnt :\n");
-+
-+				for (j = 0; j < 0x60; j++) {
-+					RTW_PRINT_SEL(m, "%08u  ", pstats->rxratecnt[j]);
-+					pstats->rxratecnt[j] = 0;
-+					if ((j%8) == 7)
-+						RTW_PRINT_SEL(m, "\n");
-+				}
-+				RTW_PRINT_SEL(m, "\n");
-+			}
-+		}
-+	}
-+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+	return 0;
-+}
-+
-+int proc_get_tx_stat(struct seq_file *m, void *v)
-+{
-+	_irqL	irqL;
-+	_list	*plist, *phead;
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct sta_info *psta = NULL;
-+	u8 sta_mac[NUM_STA][ETH_ALEN] = {{0}};
-+	uint mac_id[NUM_STA];
-+	struct stainfo_stats	*pstats = NULL;
-+	struct sta_priv	*pstapriv = &(adapter->stapriv);
-+	struct sta_priv	*pstapriv_primary = &(GET_PRIMARY_ADAPTER(adapter))->stapriv;
-+	u32 i, macid_rec_idx = 0;
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
-+	struct submit_ctx gotc2h;
-+
-+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+	for (i = 0; i < NUM_STA; i++) {
-+		phead = &(pstapriv->sta_hash[i]);
-+		plist = get_next(phead);
-+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+			plist = get_next(plist);
-+			if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE)
-+				&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)
-+				&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) {
-+				_rtw_memcpy(&sta_mac[macid_rec_idx][0], psta->cmn.mac_addr, ETH_ALEN);
-+				mac_id[macid_rec_idx] = psta->cmn.mac_id;
-+				macid_rec_idx++;
-+			}
-+		}
-+	}
-+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+	for (i = 0; i < macid_rec_idx; i++) {
-+		_rtw_memcpy(pstapriv_primary->c2h_sta_mac, &sta_mac[i][0], ETH_ALEN);
-+		pstapriv_primary->c2h_adapter_id = adapter->iface_id;
-+		rtw_sctx_init(&gotc2h, 60);
-+		pstapriv_primary->gotc2h = &gotc2h;
-+		rtw_hal_reqtxrpt(adapter, mac_id[i]);
-+		if (rtw_sctx_wait(&gotc2h, __func__)) {
-+			psta = rtw_get_stainfo(pstapriv, &sta_mac[i][0]);
-+			if(psta) {
-+				pstats = &psta->sta_stats;
-+#ifndef ROKU_PRIVATE
-+				RTW_PRINT_SEL(m, "data_sent_cnt :\t%u\n", pstats->tx_ok_cnt + pstats->tx_fail_cnt);
-+				RTW_PRINT_SEL(m, "success_cnt :\t%u\n", pstats->tx_ok_cnt);
-+				RTW_PRINT_SEL(m, "failure_cnt :\t%u\n", pstats->tx_fail_cnt);
-+				RTW_PRINT_SEL(m, "retry_cnt :\t%u\n\n", pstats->tx_retry_cnt);
-+#else
-+				RTW_PRINT_SEL(m, "MAC: " MAC_FMT " sent: %u fail: %u retry: %u\n",
-+				MAC_ARG(&sta_mac[i][0]), pstats->tx_ok_cnt, pstats->tx_fail_cnt, pstats->tx_retry_cnt);
-+#endif /* ROKU_PRIVATE */
-+
-+			} else
-+				RTW_PRINT_SEL(m, "STA is gone\n");
-+		} else {
-+			//to avoid c2h modify counters
-+			pstapriv_primary->gotc2h = NULL;
-+			_rtw_memset(pstapriv_primary->c2h_sta_mac, 0, ETH_ALEN);
-+			pstapriv_primary->c2h_adapter_id = CONFIG_IFACE_NUMBER;
-+			RTW_PRINT_SEL(m, "Warming : Query timeout, operation abort!!\n");
-+			break;
-+		}
-+		pstapriv_primary->gotc2h = NULL;
-+		_rtw_memset(pstapriv_primary->c2h_sta_mac, 0, ETH_ALEN);
-+		pstapriv_primary->c2h_adapter_id = CONFIG_IFACE_NUMBER;
-+	}
-+	return 0;
-+}
-+
-+int proc_get_fwstate(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	RTW_PRINT_SEL(m, "fwstate=0x%x\n", get_fwstate(pmlmepriv));
-+
-+	return 0;
-+}
-+
-+int proc_get_sec_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct security_priv *sec = &padapter->securitypriv;
-+
-+	RTW_PRINT_SEL(m, "auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n",
-+		sec->dot11AuthAlgrthm, sec->dot11PrivacyAlgrthm,
-+		sec->ndisauthtype, sec->ndisencryptstatus);
-+
-+	RTW_PRINT_SEL(m, "hw_decrypted=%d\n", sec->hw_decrypted);
-+
-+#ifdef DBG_SW_SEC_CNT
-+	RTW_PRINT_SEL(m, "wep_sw_enc_cnt=%llu, %llu, %llu\n"
-+		, sec->wep_sw_enc_cnt_bc , sec->wep_sw_enc_cnt_mc, sec->wep_sw_enc_cnt_uc);
-+	RTW_PRINT_SEL(m, "wep_sw_dec_cnt=%llu, %llu, %llu\n"
-+		, sec->wep_sw_dec_cnt_bc , sec->wep_sw_dec_cnt_mc, sec->wep_sw_dec_cnt_uc);
-+
-+	RTW_PRINT_SEL(m, "tkip_sw_enc_cnt=%llu, %llu, %llu\n"
-+		, sec->tkip_sw_enc_cnt_bc , sec->tkip_sw_enc_cnt_mc, sec->tkip_sw_enc_cnt_uc);
-+	RTW_PRINT_SEL(m, "tkip_sw_dec_cnt=%llu, %llu, %llu\n"
-+		, sec->tkip_sw_dec_cnt_bc , sec->tkip_sw_dec_cnt_mc, sec->tkip_sw_dec_cnt_uc);
-+
-+	RTW_PRINT_SEL(m, "aes_sw_enc_cnt=%llu, %llu, %llu\n"
-+		, sec->aes_sw_enc_cnt_bc , sec->aes_sw_enc_cnt_mc, sec->aes_sw_enc_cnt_uc);
-+	RTW_PRINT_SEL(m, "aes_sw_dec_cnt=%llu, %llu, %llu\n"
-+		, sec->aes_sw_dec_cnt_bc , sec->aes_sw_dec_cnt_mc, sec->aes_sw_dec_cnt_uc);
-+
-+	RTW_PRINT_SEL(m, "gcmp_sw_enc_cnt=%llu, %llu, %llu\n"
-+		, sec->gcmp_sw_enc_cnt_bc , sec->gcmp_sw_enc_cnt_mc, sec->gcmp_sw_enc_cnt_uc);
-+	RTW_PRINT_SEL(m, "gcmp_sw_dec_cnt=%llu, %llu, %llu\n"
-+		, sec->gcmp_sw_dec_cnt_bc , sec->gcmp_sw_dec_cnt_mc, sec->gcmp_sw_dec_cnt_uc);
-+#endif /* DBG_SW_SEC_CNT */
-+
-+	return 0;
-+}
-+
-+int proc_get_mlmext_state(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	RTW_PRINT_SEL(m, "pmlmeinfo->state=0x%x\n", pmlmeinfo->state);
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_LAYER2_ROAMING
-+int proc_get_roam_flags(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m, "0x%02x\n", rtw_roam_flags(adapter));
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_roam_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	char tmp[32];
-+	u8 flags;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhx", &flags);
-+
-+		if (num == 1)
-+			rtw_assign_roam_flags(adapter, flags);
-+	}
-+
-+	return count;
-+
-+}
-+
-+int proc_get_roam_param(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+
-+	RTW_PRINT_SEL(m, "%12s %15s %26s %16s\n", "rssi_diff_th", "scanr_exp_ms", "scan_interval(unit:2 sec)", "rssi_threshold");
-+	RTW_PRINT_SEL(m, "%-15u %-13u %-27u %-11u\n"
-+		, mlme->roam_rssi_diff_th
-+		, mlme->roam_scanr_exp_ms
-+		, mlme->roam_scan_int
-+		, mlme->roam_rssi_threshold
-+	);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+
-+	char tmp[32];
-+	u8 rssi_diff_th;
-+	u32 scanr_exp_ms;
-+	u32 scan_int;
-+	u8 rssi_threshold;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu %u %u %hhu", &rssi_diff_th, &scanr_exp_ms, &scan_int, &rssi_threshold);
-+
-+		if (num >= 1)
-+			mlme->roam_rssi_diff_th = rssi_diff_th;
-+		if (num >= 2)
-+			mlme->roam_scanr_exp_ms = scanr_exp_ms;
-+		if (num >= 3)
-+			mlme->roam_scan_int = scan_int;
-+		if (num >= 4)
-+			mlme->roam_rssi_threshold = rssi_threshold;
-+	}
-+
-+	return count;
-+
-+}
-+
-+ssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	char tmp[32];
-+	u8 addr[ETH_ALEN];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", addr, addr + 1, addr + 2, addr + 3, addr + 4, addr + 5);
-+		if (num == 6)
-+			_rtw_memcpy(adapter->mlmepriv.roam_tgt_addr, addr, ETH_ALEN);
-+
-+		RTW_INFO("set roam_tgt_addr to "MAC_FMT"\n", MAC_ARG(adapter->mlmepriv.roam_tgt_addr));
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_LAYER2_ROAMING */
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+int proc_get_war_offload_enable(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+
-+	if (_TRUE == pwrpriv->wowlan_war_offload_mode) {
-+		RTW_PRINT_SEL(m, "\n[ Offload Feature Enabled ]\n");
-+
-+		if (WAR_ARP_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) {
-+			RTW_PRINT_SEL(m, "\n ARP Reponse offload enabled\n");
-+		}
-+#ifdef CONFIG_OFFLOAD_MDNS_V4
-+		if (WAR_MDNS_V4_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) {
-+			RTW_PRINT_SEL(m, "\n MDNS v4 Reponse offload enabled\n");
-+		}
-+		if (WAR_MDNS_V4_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl) {
-+			RTW_PRINT_SEL(m, "\n MDNS v4 Wakeup offload enabled\n");
-+		}
-+#endif /* CONFIG_OFFLOAD_MDNS_v4 */
-+#ifdef CONFIG_OFFLOAD_MDNS_V6
-+		if (WAR_MDNS_V6_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) {
-+			RTW_PRINT_SEL(m, "\n MDNS v6 Reponse offload enabled\n");
-+		}
-+		if (WAR_MDNS_V6_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl) {
-+			RTW_PRINT_SEL(m, "\n MDNS v6 Wakeup offload enabled\n");
-+		}
-+#endif /* CONFIG_OFFLOAD_MDNS_V6 */
-+
-+		if (WAR_ARP_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl) {
-+			RTW_PRINT_SEL(m, "\n ARP Request wakeup enabled\n");
-+		}
-+
-+	} else {
-+		RTW_PRINT_SEL(m, "\n[ Offload Feature Disabled ]\n");
-+	}
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_war_offload_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+	char tmp[32];
-+	u32 offload_cfg = 0;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%x", &offload_cfg);
-+
-+		if (num == 1) {
-+			RTW_INFO(FUNC_ADPT_FMT ": Set war offload cfg = %x\n", FUNC_ADPT_ARG(padapter), offload_cfg);
-+			pwrpriv->wowlan_war_offload_ctrl = offload_cfg;
-+			pwrpriv->wowlan_war_offload_mode = offload_cfg?_TRUE:_FALSE;
-+
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+ssize_t proc_set_war_offload_ipv4_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+	char tmp[128];
-+	u32 ip_addr = 0, ip_subnet = 0, ip_gateway = 0, index = 0;
-+	struct war_ipv4_fmt* pip_info = &pwrpriv->wowlan_war_offload_ipv4;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%d %x %x %x", &index, &ip_addr, &ip_subnet, &ip_gateway);
-+
-+		if (num == 4) {
-+			pip_info->ip_addr[index-1] = ip_addr;
-+			pip_info->ip_subnet[index-1] = ip_subnet;
-+			pip_info->ip_gateway[index-1] = ip_gateway;
-+			RTW_INFO(FUNC_ADPT_FMT "Setup IPv4 address:\n", FUNC_ADPT_ARG(padapter));
-+			RTW_INFO("Index(%d) IP=%d.%d.%d.%d\n", index, (ip_addr & 0xff), ((ip_addr & 0xff00)>>8), ((ip_addr & 0xff0000)>>16), ((ip_addr & 0xff000000)>>24));
-+		} else {
-+			RTW_INFO("Wrong input buffer count (%d)\n", num);
-+			return -EFAULT;
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+ssize_t proc_set_war_offload_ipv6_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+	char tmp[255];
-+	u32 ip_addr = 0, ip_subnet = 0, ip_gateway = 0;
-+	struct war_ipv6_fmt* pip_info = &pwrpriv->wowlan_war_offload_ipv6;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num;
-+		int i;
-+		u32 index;
-+		u16 val[64];
-+		u16 big_endian_val[64];
-+
-+		num = sscanf(tmp, "%d %hx:%hx:%hx:%hx:%hx:%hx:%hx:%hx", &index, &val[0], &val[1], &val[2], &val[3], &val[4], &val[5], &val[6], &val[7]);
-+		for (i=0;i<8;i++) {
-+			big_endian_val[i] = htons(val[i]);
-+		}
-+		_rtw_memcpy(pip_info->ipv6_addr[index-1], big_endian_val, RTW_IPv6_ADDR_LEN);
-+
-+		if (num == 9) {
-+			RTW_INFO(FUNC_ADPT_FMT "Setup IPv6 address\n", FUNC_ADPT_ARG(padapter));
-+		} else {
-+			RTW_INFO("Wrong input count (%d)\n", num);
-+			return -EFAULT;
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
-+
-+int proc_get_war_offload_mdns_domain_name(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+
-+	if (_TRUE == pwrpriv->wowlan_war_offload_mode) {
-+		if ((WAR_MDNS_V4_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) ||
-+			(WAR_MDNS_V6_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) ||
-+			(WAR_MDNS_V4_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl) || 
-+			(WAR_MDNS_V6_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl)) {
-+			RTW_PRINT_SEL(m, "\nDomain Name:[%s](%d)\n\n", 
-+			pwrpriv->wowlan_war_offload_mdns_domain_name, pwrpriv->wowlan_war_offload_mdns_domain_name_len);
-+		} else {
-+			RTW_PRINT_SEL(m, "\nMSND RSP Not enabled\n\n");
-+		}
-+	} else {
-+		RTW_PRINT_SEL(m, "\nOffload Not enabled\n\n");
-+	}
-+
-+	return 0;
-+}
-+ 
-+ssize_t proc_set_war_offload_mdns_domain_name(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+	char tmp[MAX_MDNS_DOMAIN_NAME_LEN+1];
-+	char domain_name[MAX_MDNS_DOMAIN_NAME_LEN+1];
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is large than MAX_MDNS_DOMAIN_NAME_LEN(%d)\n", FUNC_ADPT_ARG(padapter), MAX_MDNS_DOMAIN_NAME_LEN);
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%s", domain_name);
-+		if(1 == num) {
-+			pwrpriv->wowlan_war_offload_mdns_domain_name_len = strlen(domain_name);
-+			_rtw_memset(pwrpriv->wowlan_war_offload_mdns_domain_name, 0x00, MAX_MDNS_DOMAIN_NAME_LEN);		
-+			_rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_domain_name, domain_name, strlen(domain_name));
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+
-+int proc_get_war_offload_mdns_machine_name(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+	int i=0;
-+
-+	if (_TRUE == pwrpriv->wowlan_war_offload_mode) {
-+		if ((WAR_MDNS_V4_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) ||
-+			(WAR_MDNS_V6_RSP_EN & pwrpriv->wowlan_war_offload_ctrl)  ||
-+			(WAR_MDNS_V4_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl) ||
-+			(WAR_MDNS_V6_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl)) {
-+			for(i=0; i<pwrpriv->wowlan_war_offload_mdns_mnane_num; i++)
-+			{
-+				RTW_PRINT_SEL(m, "[%d]", i);
-+				rtw_wow_war_mdns_dump_buf(m, "Machine Name", 
-+					pwrpriv->wowlan_war_offload_mdns_mnane[i].name, pwrpriv->wowlan_war_offload_mdns_mnane[i].name_len);
-+			}
-+				RTW_PRINT_SEL(m, "\n");
-+			} else {
-+				RTW_PRINT_SEL(m, "\nMSND RSP Not enabled\n\n");
-+			}
-+	} else {
-+		RTW_PRINT_SEL(m, "\nOffload Not enabled\n\n");
-+	}
-+
-+	return 0;
-+}
-+
-+ 
-+ssize_t proc_set_war_offload_mdns_machine_name(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+	char tmp[MAX_MDNS_MACHINE_NAME_LEN*3-1+1];
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length, %lu, is large than MAX_MDNS_MACHINE_NAME_LEN(%d)\n", FUNC_ADPT_ARG(padapter), (count+1)/3, MAX_MDNS_MACHINE_NAME_LEN);
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		if( strncmp(tmp, "clean", 5) == 0 )
-+		{
-+			_rtw_memset(pwrpriv->wowlan_war_offload_mdns_mnane, 0, sizeof(pwrpriv->wowlan_war_offload_mdns_mnane));
-+			pwrpriv->wowlan_war_offload_mdns_mnane_num = 0;
-+		}else{
-+			int idx = pwrpriv->wowlan_war_offload_mdns_mnane_num;
-+			if(idx == MAX_MDNS_MACHINE_NAME_NUM){
-+				RTW_INFO(FUNC_ADPT_FMT ": the num of machine name is already %d(MAX_MDNS_MACHINE_NAME_NUM)!\n", FUNC_ADPT_ARG(padapter), MAX_MDNS_MACHINE_NAME_NUM);
-+				return -EFAULT;
-+			}
-+			if(rtw_wow_war_mdns_parser_pattern(tmp, pwrpriv->wowlan_war_offload_mdns_mnane[idx].name,
-+				(u32 *) &pwrpriv->wowlan_war_offload_mdns_mnane[idx].name_len, MAX_MDNS_MACHINE_NAME_LEN))
-+				pwrpriv->wowlan_war_offload_mdns_mnane_num++;
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+
-+int proc_get_war_offload_mdns_service_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+	struct war_mdns_service_info *psinfo = pwrpriv->wowlan_war_offload_mdns_service;
-+	int i=0, j=0;
-+
-+	if (_TRUE == pwrpriv->wowlan_war_offload_mode) {
-+		if ((WAR_MDNS_V4_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) ||
-+			(WAR_MDNS_V6_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) ||
-+			(WAR_MDNS_V4_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl) ||
-+			(WAR_MDNS_V6_WAKEUP_EN & pwrpriv->wowlan_war_offload_ctrl)) {
-+				for(i=0; i<pwrpriv->wowlan_war_offload_mdns_service_info_num; i++)
-+				{
-+					RTW_PRINT_SEL(m, "[%d] service info ===> \n", i+1);  
-+					RTW_PRINT_SEL(m, "\tservice-transport-domain : %s(%d)- %s(%d)- %s(%d)\n", 
-+						psinfo[i].service, psinfo[i].service_len,
-+						psinfo[i].transport, psinfo[i].transport_len,
-+						psinfo[i].domain, psinfo[i].domain_len);
-+					RTW_PRINT_SEL(m, "\ttarget for srv rsp : %s(%d)\n", psinfo[i].target, psinfo[i].target_len);
-+					RTW_PRINT_SEL(m, "\tport : %x-%x, ttl : %d \n", psinfo[i].port[0], psinfo[i].port[1], psinfo[i].ttl);
-+					j = psinfo[i].txt_rsp_idx;
-+					RTW_PRINT_SEL(m, "\ttype txt rsp. [%d] \n", j);
-+					rtw_wow_war_mdns_dump_txt(m, "type txt rsp. (Str)", 
-+							pwrpriv->wowlan_war_offload_mdns_txt_rsp[j].txt, pwrpriv->wowlan_war_offload_mdns_txt_rsp[j].txt_len);
-+					
-+				}
-+				RTW_PRINT_SEL(m, "\n");
-+		} else {
-+			RTW_PRINT_SEL(m, "\nMSND RSP Not enabled\n\n");
-+		}
-+	} else {
-+		RTW_PRINT_SEL(m, "\nOffload Not enabled\n\n");
-+	}
-+
-+	return 0;
-+}
-+ 
-+ssize_t proc_set_war_offload_mdns_service_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+	struct war_mdns_service_info *psinfo = pwrpriv->wowlan_war_offload_mdns_service;
-+	u8 idx = 0, port[2], i=0;
-+	char *tmp=NULL;
-+	char srv[MAX_MDNS_SERVICE_NAME_LEN+1], trans[MAX_MDNS_TRANS_LEN+1], domain[MAX_MDNS_DOMAIN_LEN+1];
-+	char target[MAX_MDNS_TARGET_LEN+1];
-+	u32 ttl, tmp_txt_len=0, port0 =0, port1 =0;
-+	u16 max_input_size = (MAX_MDNS_SERVICE_NAME_LEN+MAX_MDNS_TRANS_LEN+MAX_MDNS_DOMAIN_LEN+MAX_MDNS_TARGET_LEN+2);
-+	int txt_idx;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > (sizeof(char)*(max_input_size)) ) {
-+		RTW_INFO(FUNC_ADPT_FMT ":  input length is too large\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	tmp = rtw_zvmalloc(sizeof(char)*(max_input_size));
-+	if (NULL == tmp) {
-+		RTW_INFO(FUNC_ADPT_FMT ": tmp buffer allocate fail!!\n", FUNC_ADPT_ARG(padapter));
-+		count = -EFAULT;	
-+		goto exit;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%15s %4s %5s %63s %x %x %u %d", srv, trans, domain, target, &port0, &port1, &ttl, &txt_idx);
-+		/*  MAX_MDNS_SERVICE_NAME_LEN(15),  MAX_MDNS_TRANS_LEN(4), MAX_MDNS_DOMAIN_LEN(5), MAX_MDNS_TARGET_LEN(63) */
-+		int idx = pwrpriv->wowlan_war_offload_mdns_service_info_num;
-+		u16 curent_txt_total_size = 0;
-+		//u16 sscanf_parameter_length = strlen(srv)+strlen(trans)+strlen(domain)+strlen(target)+2+2+4+1+num;
-+
-+		if( strncmp(srv, "clean", 5) == 0 ) {
-+			_rtw_memset(pwrpriv->wowlan_war_offload_mdns_service, 0, sizeof(pwrpriv->wowlan_war_offload_mdns_service));
-+			pwrpriv->wowlan_war_offload_mdns_service_info_num = 0;
-+		}
-+		/*else if(count != sscanf_parameter_length)
-+		{
-+			RTW_INFO(FUNC_ADPT_FMT ": Length of total parameters does not match the input buffer. (%d != %lu)\n", 
-+				FUNC_ADPT_ARG(padapter), sscanf_parameter_length, count);
-+			RTW_INFO(FUNC_ADPT_FMT ": Please check the content and length of each parameter.\n", FUNC_ADPT_ARG(padapter));
-+			RTW_INFO(FUNC_ADPT_FMT ": input buffer = (%s)(%lu)!\n\n", FUNC_ADPT_ARG(padapter), tmp, count);
-+			RTW_INFO(FUNC_ADPT_FMT ": srv = %s (%lu)!\n", FUNC_ADPT_ARG(padapter), srv, strlen(srv));
-+			RTW_INFO(FUNC_ADPT_FMT ": trans = %s (%lu)!\n", FUNC_ADPT_ARG(padapter), trans, strlen(trans));
-+			RTW_INFO(FUNC_ADPT_FMT ": domain = %s (%lu)!\n", FUNC_ADPT_ARG(padapter), domain, strlen(domain));
-+			RTW_INFO(FUNC_ADPT_FMT ": target = %s (%lu)!\n", FUNC_ADPT_ARG(padapter), target, strlen(target));
-+			RTW_INFO(FUNC_ADPT_FMT ": port = %x-%x, ttl = %d!\n", FUNC_ADPT_ARG(padapter), port0, port1, ttl);
-+			RTW_INFO(FUNC_ADPT_FMT ": txt idx = %d!\n", FUNC_ADPT_ARG(padapter), txt_idx);
-+			count = -EFAULT;    
-+			goto exit;
-+		}*/else
-+		{
-+			port[0] = (u8)port0;
-+			port[1] = (u8)port1;
-+
-+			if(txt_idx >= MAX_MDNS_TXT_NUM) {
-+				RTW_INFO(FUNC_ADPT_FMT ": input txt idx, %d, is out of range (0~%d)!\n", FUNC_ADPT_ARG(padapter), txt_idx, MAX_MDNS_TXT_NUM-1);
-+				count = -EFAULT;    
-+				goto exit;
-+			}
-+
-+			if(pwrpriv->wowlan_war_offload_mdns_txt_rsp[txt_idx].txt_len == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT ": wowlan_war_offload_mdns_txt_rsp[%d] is null! Please initiate it first.\n", FUNC_ADPT_ARG(padapter), txt_idx);
-+				count = -EFAULT;    
-+				goto exit;
-+			}
-+			
-+			// 1. set the value of members for this new service
-+			psinfo[idx].service_len = strlen(srv);
-+			_rtw_memcpy(psinfo[idx].service, srv, psinfo[idx].service_len );
-+			psinfo[idx].transport_len = strlen(trans);
-+			_rtw_memcpy(psinfo[idx].transport, trans, psinfo[idx].transport_len );
-+			psinfo[idx].domain_len = strlen(domain);
-+			_rtw_memcpy(psinfo[idx].domain, domain, psinfo[idx].domain_len );
-+			psinfo[idx].target_len = strlen(target);
-+			_rtw_memcpy(psinfo[idx].target, target, psinfo[idx].target_len );
-+			_rtw_memcpy(psinfo[idx].port, port, 2 );
-+			psinfo[idx].ttl = ttl;
-+			psinfo[idx].txt_rsp_idx = txt_idx;
-+			pwrpriv->wowlan_war_offload_mdns_service_info_num++;
-+		}
-+	}
-+
-+exit:	
-+	if(tmp)
-+		rtw_vmfree(tmp, sizeof(char)*(max_input_size));
-+	return count;
-+
-+}
-+
-+int proc_get_war_offload_mdns_txt_rsp(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+	int i=0;
-+
-+	if (_TRUE == pwrpriv->wowlan_war_offload_mode) {
-+		if ((WAR_MDNS_V4_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) ||
-+			(WAR_MDNS_V6_RSP_EN & pwrpriv->wowlan_war_offload_ctrl) ) {
-+			for(i=0; i<pwrpriv->wowlan_war_offload_mdns_txt_rsp_num; i++) {
-+				RTW_PRINT_SEL(m, "[%d]", i);
-+				if(pwrpriv->wowlan_war_offload_mdns_txt_rsp[i].txt_len==0){
-+					RTW_PRINT_SEL(m, " (null)\n");
-+					continue;
-+				}
-+				rtw_wow_war_mdns_dump_txt(m, "type txt rsp. (Str)", 
-+					pwrpriv->wowlan_war_offload_mdns_txt_rsp[i].txt, pwrpriv->wowlan_war_offload_mdns_txt_rsp[i].txt_len);
-+				rtw_wow_war_mdns_dump_buf(m, "type txt rsp. (Hex)", 
-+					pwrpriv->wowlan_war_offload_mdns_txt_rsp[i].txt, pwrpriv->wowlan_war_offload_mdns_txt_rsp[i].txt_len);
-+			}
-+			RTW_PRINT_SEL(m, "\n");
-+		} else {
-+			RTW_PRINT_SEL(m, "\nMSND RSP Not enabled\n\n");
-+		}
-+	} else {
-+		RTW_PRINT_SEL(m, "\nOffload Not enabled\n\n");
-+	}
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_war_offload_mdns_txt_rsp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+	u16 max_input_size = (1+6+MAX_MDNS_TXT_SINGLE_LEN+2);
-+	char* tmp=NULL;
-+	char op[7]={0}, txt_str[MAX_MDNS_TXT_SINGLE_LEN+1]={0};
-+	int idx;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	tmp = rtw_zvmalloc(sizeof(char)*(max_input_size));
-+	if (NULL == tmp) {
-+		RTW_INFO(FUNC_ADPT_FMT ": tmp buffer allocate fail!!\n", FUNC_ADPT_ARG(padapter));
-+		count = -EFAULT;	
-+		goto exit;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		if( strncmp(tmp, "clean", 5) == 0 )
-+		{
-+			/* clean ==> */
-+			if(pwrpriv->wowlan_war_offload_mdns_service_info_num==0){
-+				_rtw_memset(pwrpriv->wowlan_war_offload_mdns_txt_rsp, 0, sizeof(pwrpriv->wowlan_war_offload_mdns_txt_rsp));
-+			}else{
-+				RTW_INFO(FUNC_ADPT_FMT ": Txt rsp are refered! (Current service_info_num = %d)\n", FUNC_ADPT_ARG(padapter), pwrpriv->wowlan_war_offload_mdns_service_info_num);
-+				count = -EFAULT;
-+				goto exit;     
-+			 }
-+
-+		}else{
-+			/* set ==> */
-+			int num = sscanf(tmp, "%d %6s %256c", &idx, op, txt_str);
-+			u16 sscanf_parameter_length = 0, txt_len = 0;
-+
-+			txt_len = (strlen(txt_str)>MAX_MDNS_TXT_SINGLE_LEN)?MAX_MDNS_TXT_SINGLE_LEN:(strlen(txt_str)-1);
-+			txt_str[txt_len]='\0';
-+			sscanf_parameter_length = 1 + strlen(op) + txt_len + num;
-+
-+			if(count != sscanf_parameter_length) {
-+				RTW_INFO(FUNC_ADPT_FMT ": Length of total parameters does not match the input buffer. (%d != %lu)(num=%d)\n", 
-+					FUNC_ADPT_ARG(padapter), sscanf_parameter_length, count, num);
-+				RTW_INFO(FUNC_ADPT_FMT ": Please check the content and length of each parameter.\n", FUNC_ADPT_ARG(padapter));
-+				RTW_INFO(FUNC_ADPT_FMT ": input buffer = (%s)(%lu)!\n\n", FUNC_ADPT_ARG(padapter), tmp, count);
-+				RTW_INFO(FUNC_ADPT_FMT ": op. = %s (%lu)!\n", FUNC_ADPT_ARG(padapter), op, strlen(op));
-+				RTW_INFO(FUNC_ADPT_FMT ": txt = %s (%lu)!\n", FUNC_ADPT_ARG(padapter), txt_str, strlen(txt_str));
-+				count = -EFAULT;
-+				goto exit;
-+			} else {
-+
-+				u16 offset;
-+
-+				if(idx >= MAX_MDNS_TXT_NUM) {
-+					RTW_INFO(FUNC_ADPT_FMT ": the index, %d, is over the range of txt rsp(0~%d)!\n", FUNC_ADPT_ARG(padapter), idx, MAX_MDNS_TXT_NUM-1);
-+					count = -EFAULT;
-+					goto exit; 
-+				}
-+
-+				if( strncmp(op, "new", 3) == 0 ) {
-+					_rtw_memset(pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt, 0, pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt_len);
-+					pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt_len = 0;
-+				}else if(strncmp(op, "append", 6) == 0 ){
-+					if((pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt_len+strlen(txt_str)+1) > MAX_MDNS_TXT_LEN) {
-+						RTW_INFO(FUNC_ADPT_FMT ": the txt rsp(%d) will be over the limitation(%d) if append input string(%lu)!\n", FUNC_ADPT_ARG(padapter), 
-+						pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt_len,
-+						MAX_MDNS_TXT_LEN, strlen(txt_str)+1);
-+						count = -EFAULT;
-+						goto exit; 
-+					}
-+				}else{
-+					RTW_INFO(FUNC_ADPT_FMT ": Invaild op str %s (new/append only)!\n", FUNC_ADPT_ARG(padapter), op);
-+					count = -EFAULT;
-+					goto exit;
-+				}
-+
-+				offset = pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt_len;
-+				pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt[offset++] = strlen(txt_str);
-+				_rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt + offset, txt_str, strlen(txt_str));
-+				pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt_len += (strlen(txt_str) + 1);  /* actul len with length field */
-+
-+				/* Dump ==> */
-+				//RTW_PRINT_SEL(RTW_DBGDUMP, "[%d]", idx);
-+				//rtw_wow_war_mdns_dump_txt(RTW_DBGDUMP, "type txt rsp. (Str)", 
-+				//		pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt, pwrpriv->wowlan_war_offload_mdns_txt_rsp[idx].txt_len);         
-+			}
-+		}
-+	}
-+
-+exit:	
-+	if(tmp)
-+		rtw_vmfree(tmp, sizeof(char)*(max_input_size));
-+	return count;
-+
-+}
-+
-+#endif /* CONFIG_OFFLOAD_MDNS_V4 || CONFIG_OFFLOAD_MDNS_V6 */
-+#endif /* CONFIG_WAR_OFFLOAD */
-+
-+
-+
-+int proc_get_qos_option(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	RTW_PRINT_SEL(m, "qos_option=%d\n", pmlmepriv->qospriv.qos_option);
-+
-+	return 0;
-+}
-+
-+int proc_get_ht_option(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+#ifdef CONFIG_80211N_HT
-+	RTW_PRINT_SEL(m, "ht_option=%d\n", pmlmepriv->htpriv.ht_option);
-+#endif /* CONFIG_80211N_HT */
-+
-+	return 0;
-+}
-+
-+int proc_get_rf_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+
-+	RTW_PRINT_SEL(m, "cur_ch=%d, cur_bw=%d, cur_ch_offet=%d\n",
-+		pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
-+
-+	RTW_PRINT_SEL(m, "oper_ch=%d, oper_bw=%d, oper_ch_offet=%d\n",
-+		rtw_get_oper_ch(padapter), rtw_get_oper_bw(padapter),  rtw_get_oper_choffset(padapter));
-+
-+	return 0;
-+}
-+
-+int proc_get_scan_param(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+	struct ss_res *ss = &mlmeext->sitesurvey_res;
-+
-+#define SCAN_PARAM_TITLE_FMT "%10s"
-+#define SCAN_PARAM_VALUE_FMT "%-10u"
-+#define SCAN_PARAM_TITLE_ARG , "scan_ch_ms"
-+#define SCAN_PARAM_VALUE_ARG , ss->scan_ch_ms
-+#ifdef CONFIG_80211N_HT
-+#define SCAN_PARAM_TITLE_FMT_HT " %15s %13s"
-+#define SCAN_PARAM_VALUE_FMT_HT " %-15u %-13u"
-+#define SCAN_PARAM_TITLE_ARG_HT , "rx_ampdu_accept", "rx_ampdu_size"
-+#define SCAN_PARAM_VALUE_ARG_HT , ss->rx_ampdu_accept, ss->rx_ampdu_size
-+#else
-+#define SCAN_PARAM_TITLE_FMT_HT ""
-+#define SCAN_PARAM_VALUE_FMT_HT ""
-+#define SCAN_PARAM_TITLE_ARG_HT
-+#define SCAN_PARAM_VALUE_ARG_HT
-+#endif
-+#ifdef CONFIG_SCAN_BACKOP
-+#define SCAN_PARAM_TITLE_FMT_BACKOP " %9s %12s"
-+#define SCAN_PARAM_VALUE_FMT_BACKOP " %-9u %-12u"
-+#define SCAN_PARAM_TITLE_ARG_BACKOP , "backop_ms", "scan_cnt_max"
-+#define SCAN_PARAM_VALUE_ARG_BACKOP , ss->backop_ms, ss->scan_cnt_max
-+#else
-+#define SCAN_PARAM_TITLE_FMT_BACKOP ""
-+#define SCAN_PARAM_VALUE_FMT_BACKOP ""
-+#define SCAN_PARAM_TITLE_ARG_BACKOP
-+#define SCAN_PARAM_VALUE_ARG_BACKOP
-+#endif
-+
-+	RTW_PRINT_SEL(m,
-+		SCAN_PARAM_TITLE_FMT
-+		SCAN_PARAM_TITLE_FMT_HT
-+		SCAN_PARAM_TITLE_FMT_BACKOP
-+		"\n"
-+		SCAN_PARAM_TITLE_ARG
-+		SCAN_PARAM_TITLE_ARG_HT
-+		SCAN_PARAM_TITLE_ARG_BACKOP
-+	);
-+
-+	RTW_PRINT_SEL(m,
-+		SCAN_PARAM_VALUE_FMT
-+		SCAN_PARAM_VALUE_FMT_HT
-+		SCAN_PARAM_VALUE_FMT_BACKOP
-+		"\n"
-+		SCAN_PARAM_VALUE_ARG
-+		SCAN_PARAM_VALUE_ARG_HT
-+		SCAN_PARAM_VALUE_ARG_BACKOP
-+	);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+	struct ss_res *ss = &mlmeext->sitesurvey_res;
-+
-+	char tmp[32] = {0};
-+
-+	u16 scan_ch_ms;
-+#define SCAN_PARAM_INPUT_FMT "%hu"
-+#define SCAN_PARAM_INPUT_ARG , &scan_ch_ms
-+#ifdef CONFIG_80211N_HT
-+	u8 rx_ampdu_accept;
-+	u8 rx_ampdu_size;
-+#define SCAN_PARAM_INPUT_FMT_HT " %hhu %hhu"
-+#define SCAN_PARAM_INPUT_ARG_HT , &rx_ampdu_accept, &rx_ampdu_size
-+#else
-+#define SCAN_PARAM_INPUT_FMT_HT ""
-+#define SCAN_PARAM_INPUT_ARG_HT
-+#endif
-+#ifdef CONFIG_SCAN_BACKOP
-+	u16 backop_ms;
-+	u8 scan_cnt_max;
-+#define SCAN_PARAM_INPUT_FMT_BACKOP " %hu %hhu"
-+#define SCAN_PARAM_INPUT_ARG_BACKOP , &backop_ms, &scan_cnt_max
-+#else
-+#define SCAN_PARAM_INPUT_FMT_BACKOP ""
-+#define SCAN_PARAM_INPUT_ARG_BACKOP
-+#endif
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp,
-+			SCAN_PARAM_INPUT_FMT
-+			SCAN_PARAM_INPUT_FMT_HT
-+			SCAN_PARAM_INPUT_FMT_BACKOP
-+			SCAN_PARAM_INPUT_ARG
-+			SCAN_PARAM_INPUT_ARG_HT
-+			SCAN_PARAM_INPUT_ARG_BACKOP
-+		);
-+
-+		if (num-- > 0)
-+			ss->scan_ch_ms = scan_ch_ms;
-+#ifdef CONFIG_80211N_HT
-+		if (num-- > 0)
-+			ss->rx_ampdu_accept = rx_ampdu_accept;
-+		if (num-- > 0)
-+			ss->rx_ampdu_size = rx_ampdu_size;
-+#endif
-+#ifdef CONFIG_SCAN_BACKOP
-+		if (num-- > 0)
-+			ss->backop_ms = backop_ms;
-+		if (num-- > 0)
-+			ss->scan_cnt_max = scan_cnt_max;
-+#endif
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_scan_abort(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	u32 pass_ms;
-+
-+	pass_ms = rtw_scan_abort_timeout(adapter, 10000);
-+
-+	RTW_PRINT_SEL(m, "%u\n", pass_ms);
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+int proc_get_rson_data(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char rson_data_str[256];
-+
-+	rtw_rson_get_property_str(padapter, rson_data_str);
-+	RTW_PRINT_SEL(m, "%s\n", rson_data_str);
-+	return 0;
-+}
-+
-+ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
-+	char tmp[64] = {0};
-+	int num;
-+	u8 field[10], value[64];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		num = sscanf(tmp, "%s %s", field, value);
-+		if (num != 2) {
-+			RTW_INFO("Invalid format : echo <field> <value> > son_data\n");
-+			return count;
-+		}
-+		RTW_INFO("field=%s  value=%s\n", field, value);
-+		num = rtw_rson_set_property(padapter, field, value);
-+		if (num != 1) {
-+			RTW_INFO("Invalid field(%s) or value(%s)\n", field, value);
-+			return count;
-+		}
-+	}
-+	return count;
-+}
-+#endif /*CONFIG_RTW_REPEATER_SON*/
-+
-+int proc_get_survey_info(struct seq_file *m, void *v)
-+{
-+	_irqL irqL;
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	_queue	*queue	= &(pmlmepriv->scanned_queue);
-+	struct wlan_network	*pnetwork = NULL;
-+	_list	*plist, *phead;
-+	s32 notify_signal;
-+	s16 notify_noise = 0;
-+	u16  index = 0, ie_cap = 0;
-+	unsigned char *ie_wpa = NULL, *ie_wpa2 = NULL, *ie_wps = NULL;
-+	unsigned char *ie_p2p = NULL, *ssid = NULL;
-+	char flag_str[64];
-+	int ielen = 0;
-+	u32 wpsielen = 0;
-+#ifdef CONFIG_RTW_MESH
-+	const char *ssid_title_str = "ssid/mesh_id";
-+#else
-+	const char *ssid_title_str = "ssid";
-+#endif
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+	phead = get_list_head(queue);
-+	if (!phead)
-+		goto _exit;
-+	plist = get_next(phead);
-+	if (!plist)
-+		goto _exit;
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	rtw_rson_show_survey_info(m, plist, phead);
-+#else
-+
-+	RTW_PRINT_SEL(m, "%5s  %-17s  %3s  %-3s  %-4s  %-4s  %5s  %32s  %32s\n", "index", "bssid", "ch", "RSSI", "SdBm", "Noise", "age", "flag", ssid_title_str);
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+		if (!pnetwork)
-+			break;
-+
-+		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE &&
-+		    is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) {
-+			notify_signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);/* dbm */
-+		} else {
-+			notify_signal = translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength);/* dbm */
-+		}
-+
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+		if (IS_NM_ENABLE(padapter))
-+			notify_noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig);
-+#endif
-+
-+		ie_wpa = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12);
-+		ie_wpa2 = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12);
-+		ie_cap = rtw_get_capability(&pnetwork->network);
-+		ie_wps = rtw_get_wps_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &wpsielen);
-+#ifdef CONFIG_P2P
-+		ie_p2p = rtw_get_p2p_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &ielen);
-+#endif
-+		ssid = pnetwork->network.Ssid.Ssid;
-+		sprintf(flag_str, "%s%s%s%s%s%s%s",
-+			(ie_wpa) ? "[WPA]" : "",
-+			(ie_wpa2) ? "[WPA2]" : "",
-+			(!ie_wpa && !ie_wpa && ie_cap & BIT(4)) ? "[WEP]" : "",
-+			(ie_wps) ? "[WPS]" : "",
-+			(pnetwork->network.InfrastructureMode == Ndis802_11IBSS) ? "[IBSS]" :
-+				(pnetwork->network.InfrastructureMode == Ndis802_11_mesh) ? "[MESH]" : "",
-+			(ie_cap & BIT(0)) ? "[ESS]" : "",
-+			(ie_p2p) ? "[P2P]" : "");
-+		RTW_PRINT_SEL(m, "%5d  "MAC_FMT"  %3d  %3d  %4d  %4d    %5d  %32s  %32s\n",
-+			++index,
-+			MAC_ARG(pnetwork->network.MacAddress),
-+			pnetwork->network.Configuration.DSConfig,
-+			(int)pnetwork->network.Rssi,
-+			notify_signal,
-+			notify_noise,
-+			rtw_get_passing_time_ms(pnetwork->last_scanned),
-+			flag_str,
-+			pnetwork->network.InfrastructureMode == Ndis802_11_mesh ? pnetwork->network.mesh_id.Ssid : pnetwork->network.Ssid.Ssid
-+		);
-+		plist = get_next(plist);
-+	}
-+#endif
-+_exit:
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 _status = _FALSE;
-+	u8 ssc_chk;
-+	char tmp[32] = {0};
-+	char cmd[8] = {0};
-+	bool acs = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%s", cmd);
-+
-+		if (num < 1)
-+			return count;
-+
-+		if (strcmp("acs", cmd) == 0)
-+			acs = 1;
-+	}
-+
-+#if 1
-+	ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
-+	if (ssc_chk != SS_ALLOW)
-+		goto exit;
-+
-+	rtw_ps_deny(padapter, PS_DENY_SCAN);
-+	if (_FAIL == rtw_pwr_wakeup(padapter))
-+		goto cancel_ps_deny;
-+	if (!rtw_is_adapter_up(padapter)) {
-+		RTW_INFO("scan abort!! adapter cannot use\n");
-+		goto cancel_ps_deny;
-+	}
-+#else
-+#ifdef CONFIG_MP_INCLUDED
-+	if (rtw_mp_mode_check(padapter)) {
-+		RTW_INFO("MP mode block Scan request\n");
-+		goto exit;
-+	}
-+#endif
-+	if (rtw_is_scan_deny(padapter)) {
-+		RTW_INFO(FUNC_ADPT_FMT  ": scan deny\n", FUNC_ADPT_ARG(padapter));
-+		goto exit;
-+	}
-+
-+	rtw_ps_deny(padapter, PS_DENY_SCAN);
-+	if (_FAIL == rtw_pwr_wakeup(padapter))
-+		goto cancel_ps_deny;
-+
-+	if (!rtw_is_adapter_up(padapter)) {
-+		RTW_INFO("scan abort!! adapter cannot use\n");
-+		goto cancel_ps_deny;
-+	}
-+
-+	if (rtw_mi_busy_traffic_check(padapter)) {
-+		RTW_INFO("scan abort!! BusyTraffic == _TRUE\n");
-+		goto cancel_ps_deny;
-+	}
-+
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
-+		RTW_INFO("scan abort!! AP mode process WPS\n");
-+		goto cancel_ps_deny;
-+	}
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING) == _TRUE) {
-+		RTW_INFO("scan abort!! fwstate=0x%x\n", pmlmepriv->fw_state);
-+		goto cancel_ps_deny;
-+	}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_buddy_check_fwstate(padapter,
-+		       WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING | WIFI_UNDER_WPS)) {
-+		RTW_INFO("scan abort!! buddy_fwstate check failed\n");
-+		goto cancel_ps_deny;
-+	}
-+#endif
-+#endif
-+
-+	if (acs) {
-+		#ifdef CONFIG_RTW_ACS
-+		_status = rtw_set_acs_sitesurvey(padapter);
-+		#endif
-+	} else
-+		_status = rtw_set_802_11_bssid_list_scan(padapter, NULL);
-+
-+cancel_ps_deny:
-+	rtw_ps_deny_cancel(padapter, PS_DENY_SCAN);
-+exit:
-+	return count;
-+}
-+#ifdef ROKU_PRIVATE
-+int proc_get_infra_ap(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	struct sta_info *psta;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct ht_priv_infra_ap *phtpriv = &pmlmepriv->htpriv_infra_ap;
-+#ifdef CONFIG_80211AC_VHT
-+	struct vht_priv_infra_ap *pvhtpriv = &pmlmepriv->vhtpriv_infra_ap;
-+#endif
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
-+		psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
-+		if (psta) {
-+			unsigned int i, j;
-+			unsigned int Rx_ss = 0, Tx_ss = 0;
-+			struct recv_reorder_ctrl *preorder_ctrl;
-+
-+			RTW_PRINT_SEL(m, "SSID=%s\n", pmlmeinfo->network.Ssid.Ssid);
-+			RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
-+			RTW_PRINT_SEL(m, "Supported rate=");
-+			for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
-+				if (pmlmeinfo->SupportedRates_infra_ap[i] == 0)
-+					break;
-+				RTW_PRINT_SEL(m, " 0x%x", pmlmeinfo->SupportedRates_infra_ap[i]);
-+			}
-+			RTW_PRINT_SEL(m, "\n");
-+#ifdef CONFIG_80211N_HT
-+			if (pmlmeinfo->ht_vht_received & BIT(0)) {
-+				RTW_PRINT_SEL(m, "Supported MCS set=");
-+				for (i = 0; i < 16 ; i++)
-+					RTW_PRINT_SEL(m, " 0x%02x",  phtpriv->MCS_set_infra_ap[i]);
-+				RTW_PRINT_SEL(m, "\n");
-+				RTW_PRINT_SEL(m, "highest supported data rate=0x%x\n", phtpriv->rx_highest_data_rate_infra_ap);
-+				RTW_PRINT_SEL(m, "HT_supported_channel_width_set=0x%x\n", phtpriv->channel_width_infra_ap);
-+				RTW_PRINT_SEL(m, "sgi_20m=%d, sgi_40m=%d\n", phtpriv->sgi_20m_infra_ap, phtpriv->sgi_40m_infra_ap);
-+				RTW_PRINT_SEL(m, "ldpc_cap=0x%x, stbc_cap=0x%x\n", phtpriv->ldpc_cap_infra_ap, phtpriv->stbc_cap_infra_ap);
-+				RTW_PRINT_SEL(m, "HT_number_of_stream=%d\n", phtpriv->Rx_ss_infra_ap);
-+			}
-+#endif
-+
-+#ifdef CONFIG_80211AC_VHT
-+			if (pmlmeinfo->ht_vht_received & BIT(1)) {
-+				RTW_PRINT_SEL(m, "VHT_supported_channel_width_set=0x%x\n", pvhtpriv->channel_width_infra_ap);
-+				RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", pvhtpriv->ldpc_cap_infra_ap, pvhtpriv->stbc_cap_infra_ap, pvhtpriv->beamform_cap_infra_ap);
-+				RTW_PRINT_SEL(m, "Rx_vht_mcs_map=0x%x, Tx_vht_mcs_map=0x%x\n", *(u16 *)pvhtpriv->vht_mcs_map_infra_ap, *(u16 *)pvhtpriv->vht_mcs_map_tx_infra_ap);
-+				RTW_PRINT_SEL(m, "VHT_number_of_stream=%d\n", pvhtpriv->number_of_streams_infra_ap);
-+			}
-+#endif
-+		} else
-+			RTW_PRINT_SEL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress));
-+	} else
-+		RTW_PRINT_SEL(m, "this only applies to STA mode\n");
-+	return 0;
-+}
-+
-+#endif /* ROKU_PRIVATE */
-+
-+static int wireless_mode_to_str(u32 mode, char *str)
-+{
-+	str[0]='\0';
-+	if (mode&WIRELESS_11A)
-+		sprintf(str+strlen(str),"%s","A/");
-+	if (mode&WIRELESS_11B)
-+		sprintf(str+strlen(str),"%s","B/");
-+	if (mode&WIRELESS_11G)
-+		sprintf(str+strlen(str),"%s","G/");
-+	if (mode&(WIRELESS_11_24N|WIRELESS_11_5N))
-+		sprintf(str+strlen(str),"%s","N/");
-+	if (mode&WIRELESS_11AC)
-+		sprintf(str+strlen(str),"%s","AC/");
-+
-+	if (strlen(str)>1)
-+		str[strlen(str)-1]='\0';
-+
-+	return strlen(str);
-+}
-+
-+int proc_get_ap_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	struct sta_info *psta;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	char wl_mode[16];
-+
-+	/* ap vendor */
-+	char vendor[VENDOR_NAME_LEN] = {0};
-+	get_assoc_AP_Vendor(vendor,pmlmeinfo->assoc_AP_vendor);
-+	RTW_PRINT_SEL(m,"AP Vendor %s\n", vendor);
-+
-+	psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
-+	if (psta) {
-+		wireless_mode_to_str(psta->wireless_mode, wl_mode);
-+		RTW_PRINT_SEL(m, "SSID=%s\n", cur_network->network.Ssid.Ssid);
-+		RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
-+		RTW_PRINT_SEL(m, "cur_channel=%d, cur_bwmode=%d(%s), cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, ch_width_str(pmlmeext->cur_bwmode), pmlmeext->cur_ch_offset);
-+		RTW_PRINT_SEL(m, "wireless_mode=0x%x(%s), rtsen=%d, cts2slef=%d\n", psta->wireless_mode, wl_mode, psta->rtsen, psta->cts2self);
-+		RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n",
-+			psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);
-+#ifdef CONFIG_80211N_HT
-+		RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
-+		RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n"
-+			, psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);
-+		RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
-+		RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
-+		RTW_PRINT_SEL(m, "ldpc_cap=0x%x, stbc_cap=0x%x, beamform_cap=0x%x\n", psta->htpriv.ldpc_cap, psta->htpriv.stbc_cap, psta->htpriv.beamform_cap);
-+#endif /* CONFIG_80211N_HT */
-+#ifdef CONFIG_80211AC_VHT
-+		RTW_PRINT_SEL(m, "vht_en=%d, vht_sgi_80m=%d\n", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m);
-+		RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap);
-+		RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len);
-+#endif
-+		sta_rx_reorder_ctl_dump(m, psta);
-+	} else
-+		RTW_PRINT_SEL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress));
-+
-+	return 0;
-+}
-+
-+ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct recv_priv  *precvpriv = &padapter->recvpriv;
-+	char cmd[32] = {0};
-+	u8 cnt = 0;
-+
-+	if (count > sizeof(cmd)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(cmd, buffer, count)) {
-+		int num = sscanf(cmd, "%hhx", &cnt);
-+
-+		if (num == 1 && cnt == 0) {
-+			precvpriv->dbg_rx_ampdu_drop_count = 0;
-+			precvpriv->dbg_rx_ampdu_forced_indicate_count = 0;
-+			precvpriv->dbg_rx_ampdu_loss_count = 0;
-+			precvpriv->dbg_rx_dup_mgt_frame_drop_count = 0;
-+			precvpriv->dbg_rx_ampdu_window_shift_cnt = 0;
-+			precvpriv->dbg_rx_conflic_mac_addr_cnt = 0;
-+			precvpriv->dbg_rx_drop_count = 0;
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_trx_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	int i;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	struct recv_priv  *precvpriv = &padapter->recvpriv;
-+	struct hw_xmit *phwxmit;
-+	u16 vo_params[4], vi_params[4], be_params[4], bk_params[4];
-+
-+	padapter->hal_func.read_wmmedca_reg(padapter, vo_params, vi_params, be_params, bk_params);
-+
-+	RTW_PRINT_SEL(m, "wmm_edca_vo, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vo_params[0], vo_params[1], vo_params[2], vo_params[3]);
-+	RTW_PRINT_SEL(m, "wmm_edca_vi, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vi_params[0], vi_params[1], vi_params[2], vi_params[3]);
-+	RTW_PRINT_SEL(m, "wmm_edca_be, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", be_params[0], be_params[1], be_params[2], be_params[3]);
-+	RTW_PRINT_SEL(m, "wmm_edca_bk, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", bk_params[0], bk_params[1], bk_params[2], bk_params[3]);
-+
-+	dump_os_queue(m, padapter);
-+
-+	RTW_PRINT_SEL(m, "free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d\n"
-+		, pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt);
-+	RTW_PRINT_SEL(m, "free_ext_xmitbuf_cnt=%d, free_xframe_ext_cnt=%d\n"
-+		, pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt);
-+	RTW_PRINT_SEL(m, "free_recvframe_cnt=%d\n"
-+		      , precvpriv->free_recvframe_cnt);
-+
-+	for (i = 0; i < pxmitpriv->hwxmit_entry; i++) {
-+		phwxmit = pxmitpriv->hwxmits + i;
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+		if (i == pxmitpriv->hwxmit_entry - 1)
-+			RTW_PRINT_SEL(m, "%d, hw_mgmt_q.accnt=%d\n", i, phwxmit->accnt);
-+		else
-+#endif
-+			RTW_PRINT_SEL(m, "%d, hwq.accnt=%d\n", i, phwxmit->accnt);
-+	}
-+
-+	rtw_hal_get_hwreg(padapter, HW_VAR_DUMP_MAC_TXFIFO, (u8 *)m);
-+
-+#ifdef CONFIG_USB_HCI
-+	RTW_PRINT_SEL(m, "rx_urb_pending_cn=%d\n", ATOMIC_READ(&(precvpriv->rx_pending_cnt)));
-+#endif
-+
-+	dump_rx_bh_tk(m, &GET_PRIMARY_ADAPTER(padapter)->recvpriv);
-+
-+	/* Folowing are RX info */
-+	RTW_PRINT_SEL(m, "RX: Count of Packets dropped by Driver: %llu\n", (unsigned long long)precvpriv->dbg_rx_drop_count);
-+	/* Counts of packets whose seq_num is less than preorder_ctrl->indicate_seq, Ex delay, retransmission, redundant packets and so on */
-+	RTW_PRINT_SEL(m, "Rx: Counts of Packets Whose Seq_Num Less Than Reorder Control Seq_Num: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_drop_count);
-+	/* How many times the Rx Reorder Timer is triggered. */
-+	RTW_PRINT_SEL(m, "Rx: Reorder Time-out Trigger Counts: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_forced_indicate_count);
-+	/* Total counts of packets loss */
-+	RTW_PRINT_SEL(m, "Rx: Packet Loss Counts: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_loss_count);
-+	RTW_PRINT_SEL(m, "Rx: Duplicate Management Frame Drop Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_dup_mgt_frame_drop_count);
-+	RTW_PRINT_SEL(m, "Rx: AMPDU BA window shift Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_window_shift_cnt);
-+	/*The same mac addr counts*/
-+	RTW_PRINT_SEL(m, "Rx: Conflict MAC Address Frames Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_conflic_mac_addr_cnt);
-+	return 0;
-+}
-+
-+int proc_get_rate_ctl(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 data_rate = 0, sgi = 0, data_fb = 0;
-+
-+	if (adapter->fix_rate != 0xff) {
-+		data_rate = adapter->fix_rate & 0x7F;
-+		sgi = adapter->fix_rate >> 7;
-+		data_fb = adapter->data_fb ? 1 : 0;
-+		RTW_PRINT_SEL(m, "FIXED %s%s%s\n"
-+			, HDATA_RATE(data_rate)
-+			, data_rate > DESC_RATE54M ? (sgi ? " SGI" : " LGI") : ""
-+			, data_fb ? " FB" : ""
-+		);
-+		RTW_PRINT_SEL(m, "0x%02x %u\n", adapter->fix_rate, adapter->data_fb);
-+	} else
-+		RTW_PRINT_SEL(m, "RA\n");
-+
-+	return 0;
-+}
-+
-+#ifdef 	CONFIG_PHDYM_FW_FIXRATE
-+void phydm_fw_fix_rate(void *dm_void, u8 en, u8	macid, u8 bw, u8 rate);
-+#endif
-+ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	char tmp[32];
-+	u8 fix_rate = 0xFF;
-+#ifdef 	CONFIG_PHDYM_FW_FIXRATE
-+	u8 bw = 0;
-+#else
-+	u8 data_fb = 0;
-+#endif
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+#ifdef 	CONFIG_PHDYM_FW_FIXRATE
-+		struct dm_struct *dm = adapter_to_phydm(adapter);
-+		u8 en = 1, macid = 255;
-+		_irqL	irqL;
-+		_list	*plist, *phead;
-+		struct sta_info *psta = NULL;
-+		struct sta_priv	*pstapriv = &(adapter->stapriv);
-+		u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+		u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
-+		uint mac_id[NUM_STA];
-+		int i, macid_rec_idx = 0;
-+		int num = sscanf(tmp, "%hhx %hhu %hhu", &fix_rate, &bw, &macid);
-+
-+		if (num < 1) {
-+			RTW_INFO("Invalid input!! \"ex: echo <rate> <bw> <macid> > /proc/.../rate_ctl\"\n");
-+			return count;
-+		}
-+
-+		if ((fix_rate == 0) || (fix_rate == 0xFF))
-+			en = 0;
-+			
-+		if (macid != 255) {
-+			RTW_INFO("Call phydm_fw_fix_rate()--en[%d] mac_id[%d] bw[%d] fix_rate[%d]\n", en, macid, bw, fix_rate);
-+			phydm_fw_fix_rate(dm, en, macid, bw, fix_rate);
-+			return count;
-+		}
-+
-+		/*	no specific macid, apply to all macids except bc/mc macid */
-+		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+		for (i = 0; i < NUM_STA; i++) {
-+			phead = &(pstapriv->sta_hash[i]);
-+			plist = get_next(phead);
-+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+				plist = get_next(plist);
-+				if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE)
-+					&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)
-+					&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) {
-+						mac_id[macid_rec_idx] = psta->cmn.mac_id;
-+						macid_rec_idx++;
-+				}
-+			}
-+		}
-+		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+		for (i = 0; i < macid_rec_idx; i++) {
-+			RTW_INFO("Call phydm_fw_fix_rate()--en[%d] mac_id[%d] bw[%d] fix_rate[%d]\n", en, mac_id[i], bw, fix_rate);
-+			phydm_fw_fix_rate(dm, en, mac_id[i], bw, fix_rate);
-+		}
-+#else
-+		int num = sscanf(tmp, "%hhx %hhu", &fix_rate, &data_fb);
-+
-+		if (num >= 1) {
-+			u8 fix_rate_ori = adapter->fix_rate;
-+
-+			adapter->fix_rate = fix_rate;
-+			if (fix_rate == 0xFF)
-+				hal_data->ForcedDataRate = 0;
-+			else
-+				hal_data->ForcedDataRate = hw_rate_to_m_rate(fix_rate & 0x7F);
-+
-+			if (adapter->fix_bw != 0xFF && fix_rate_ori != fix_rate)
-+				rtw_run_in_thread_cmd(adapter, ((void *)(rtw_update_tx_rate_bmp)), adapter_to_dvobj(adapter));
-+		}
-+		if (num >= 2)
-+			adapter->data_fb = data_fb ? 1 : 0;
-+#endif
-+	}
-+
-+	return count;
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+int proc_get_bmc_tx_rate(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter)) {
-+		RTW_PRINT_SEL(m, "[ERROR] Not in SoftAP/Mesh mode !!\n");
-+		return 0;
-+	}
-+
-+	RTW_PRINT_SEL(m, " BMC Tx rate - %s\n", MGN_RATE_STR(adapter->bmc_tx_rate));
-+	return 0;
-+}
-+
-+ssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 bmc_tx_rate;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhx", &bmc_tx_rate);
-+
-+		if (num >= 1)
-+			/*adapter->bmc_tx_rate = hw_rate_to_m_rate(bmc_tx_rate);*/
-+			adapter->bmc_tx_rate = bmc_tx_rate;
-+	}
-+
-+	return count;
-+}
-+#endif /*CONFIG_AP_MODE*/
-+
-+
-+int proc_get_tx_power_offset(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m, "Tx power offset - %u\n", adapter->power_offset);
-+	return 0;
-+}
-+
-+ssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 power_offset = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu", &power_offset);
-+
-+		if (num >= 1) {
-+			if (power_offset > 5)
-+				power_offset = 0;
-+
-+			adapter->power_offset = power_offset;
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_bw_ctl(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 data_bw = 0;
-+
-+	if (adapter->fix_bw != 0xff) {
-+		data_bw = adapter->fix_bw;
-+		RTW_PRINT_SEL(m, "FIXED %s\n", ch_width_str(data_bw));
-+	} else
-+		RTW_PRINT_SEL(m, "Auto\n");
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 fix_bw;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%hhu", &fix_bw);
-+
-+		if (num >= 1) {
-+			u8 fix_bw_ori = adapter->fix_bw;
-+
-+			adapter->fix_bw = fix_bw;
-+
-+			if (adapter->fix_rate != 0xFF && fix_bw_ori != fix_bw)
-+				rtw_run_in_thread_cmd(adapter, ((void *)(rtw_update_tx_rate_bmp)), adapter_to_dvobj(adapter));
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+#ifdef DBG_RX_COUNTER_DUMP
-+int proc_get_rx_cnt_dump(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	int i;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m, "BIT0- Dump RX counters of DRV\n");
-+	RTW_PRINT_SEL(m, "BIT1- Dump RX counters of MAC\n");
-+	RTW_PRINT_SEL(m, "BIT2- Dump RX counters of PHY\n");
-+	RTW_PRINT_SEL(m, "BIT3- Dump TRX data frame of DRV\n");
-+	RTW_PRINT_SEL(m, "dump_rx_cnt_mode = 0x%02x\n", adapter->dump_rx_cnt_mode);
-+
-+	return 0;
-+}
-+ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 dump_rx_cnt_mode;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhx", &dump_rx_cnt_mode);
-+
-+		if (num == 1) {
-+			rtw_dump_phy_rxcnts_preprocess(adapter, dump_rx_cnt_mode);
-+			adapter->dump_rx_cnt_mode = dump_rx_cnt_mode;
-+		}
-+	}
-+
-+	return count;
-+}
-+#endif
-+
-+ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count))
-+		sscanf(tmp, "%hhu %hhu", &fwdl_test_chksum_fail, &fwdl_test_wintint_rdy_fail);
-+
-+	return count;
-+}
-+
-+ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count))
-+		sscanf(tmp, "%hhu", &del_rx_ampdu_test_no_tx_fail);
-+
-+	return count;
-+}
-+
-+ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count))
-+		sscanf(tmp, "%u", &g_wait_hiq_empty_ms);
-+
-+	return count;
-+}
-+
-+ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		u32 wait_ms = 0;
-+		u8 force_fail = 0;
-+		int num = sscanf(tmp, "%u %hhu", &wait_ms, &force_fail);
-+
-+		if (num >= 1)
-+			sta_linking_test_wait_ms = wait_ms;
-+		if (num >= 2)
-+			sta_linking_test_force_fail = force_fail;
-+	}
-+
-+	return count;
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+ssize_t proc_set_ap_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		u16 force_auth_fail = 0;
-+		u16 force_asoc_fail = 0;
-+		int num = sscanf(tmp, "%hu %hu", &force_auth_fail, &force_asoc_fail);
-+
-+		if (num >= 1)
-+			ap_linking_test_force_auth_fail = force_auth_fail;
-+		if (num >= 2)
-+			ap_linking_test_force_asoc_fail = force_asoc_fail;
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+int proc_get_ps_dbg_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
-+
-+	RTW_PRINT_SEL(m, "dbg_sdio_alloc_irq_cnt=%d\n", pdbgpriv->dbg_sdio_alloc_irq_cnt);
-+	RTW_PRINT_SEL(m, "dbg_sdio_free_irq_cnt=%d\n", pdbgpriv->dbg_sdio_free_irq_cnt);
-+	RTW_PRINT_SEL(m, "dbg_sdio_alloc_irq_error_cnt=%d\n", pdbgpriv->dbg_sdio_alloc_irq_error_cnt);
-+	RTW_PRINT_SEL(m, "dbg_sdio_free_irq_error_cnt=%d\n", pdbgpriv->dbg_sdio_free_irq_error_cnt);
-+	RTW_PRINT_SEL(m, "dbg_sdio_init_error_cnt=%d\n", pdbgpriv->dbg_sdio_init_error_cnt);
-+	RTW_PRINT_SEL(m, "dbg_sdio_deinit_error_cnt=%d\n", pdbgpriv->dbg_sdio_deinit_error_cnt);
-+	RTW_PRINT_SEL(m, "dbg_suspend_error_cnt=%d\n", pdbgpriv->dbg_suspend_error_cnt);
-+	RTW_PRINT_SEL(m, "dbg_suspend_cnt=%d\n", pdbgpriv->dbg_suspend_cnt);
-+	RTW_PRINT_SEL(m, "dbg_resume_cnt=%d\n", pdbgpriv->dbg_resume_cnt);
-+	RTW_PRINT_SEL(m, "dbg_resume_error_cnt=%d\n", pdbgpriv->dbg_resume_error_cnt);
-+	RTW_PRINT_SEL(m, "dbg_deinit_fail_cnt=%d\n", pdbgpriv->dbg_deinit_fail_cnt);
-+	RTW_PRINT_SEL(m, "dbg_carddisable_cnt=%d\n", pdbgpriv->dbg_carddisable_cnt);
-+	RTW_PRINT_SEL(m, "dbg_ps_insuspend_cnt=%d\n", pdbgpriv->dbg_ps_insuspend_cnt);
-+	RTW_PRINT_SEL(m, "dbg_dev_unload_inIPS_cnt=%d\n", pdbgpriv->dbg_dev_unload_inIPS_cnt);
-+	RTW_PRINT_SEL(m, "dbg_scan_pwr_state_cnt=%d\n", pdbgpriv->dbg_scan_pwr_state_cnt);
-+	RTW_PRINT_SEL(m, "dbg_downloadfw_pwr_state_cnt=%d\n", pdbgpriv->dbg_downloadfw_pwr_state_cnt);
-+	RTW_PRINT_SEL(m, "dbg_carddisable_error_cnt=%d\n", pdbgpriv->dbg_carddisable_error_cnt);
-+	RTW_PRINT_SEL(m, "dbg_fw_read_ps_state_fail_cnt=%d\n", pdbgpriv->dbg_fw_read_ps_state_fail_cnt);
-+	RTW_PRINT_SEL(m, "dbg_leave_ips_fail_cnt=%d\n", pdbgpriv->dbg_leave_ips_fail_cnt);
-+	RTW_PRINT_SEL(m, "dbg_leave_lps_fail_cnt=%d\n", pdbgpriv->dbg_leave_lps_fail_cnt);
-+	RTW_PRINT_SEL(m, "dbg_h2c_leave32k_fail_cnt=%d\n", pdbgpriv->dbg_h2c_leave32k_fail_cnt);
-+	RTW_PRINT_SEL(m, "dbg_diswow_dload_fw_fail_cnt=%d\n", pdbgpriv->dbg_diswow_dload_fw_fail_cnt);
-+	RTW_PRINT_SEL(m, "dbg_enwow_dload_fw_fail_cnt=%d\n", pdbgpriv->dbg_enwow_dload_fw_fail_cnt);
-+	RTW_PRINT_SEL(m, "dbg_ips_drvopen_fail_cnt=%d\n", pdbgpriv->dbg_ips_drvopen_fail_cnt);
-+	RTW_PRINT_SEL(m, "dbg_poll_fail_cnt=%d\n", pdbgpriv->dbg_poll_fail_cnt);
-+	RTW_PRINT_SEL(m, "dbg_rpwm_toogle_cnt=%d\n", pdbgpriv->dbg_rpwm_toogle_cnt);
-+	RTW_PRINT_SEL(m, "dbg_rpwm_timeout_fail_cnt=%d\n", pdbgpriv->dbg_rpwm_timeout_fail_cnt);
-+	RTW_PRINT_SEL(m, "dbg_sreset_cnt=%d\n", pdbgpriv->dbg_sreset_cnt);
-+	RTW_PRINT_SEL(m, "dbg_fw_mem_dl_error_cnt=%d\n", pdbgpriv->dbg_fw_mem_dl_error_cnt);
-+
-+	return 0;
-+}
-+ssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter->dvobj;
-+	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
-+	char tmp[32];
-+	u8 ps_dbg_cmd_id;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhx", &ps_dbg_cmd_id);
-+
-+		if (num == 1 && ps_dbg_cmd_id == 1) /*Clean all*/
-+			_rtw_memset(pdbgpriv, 0, sizeof(struct debug_priv));
-+
-+	}
-+
-+	return count;
-+}
-+
-+
-+#ifdef CONFIG_DBG_COUNTER
-+
-+int proc_get_rx_logs(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rx_logs *rx_logs = &padapter->rx_logs;
-+
-+	RTW_PRINT_SEL(m,
-+		      "intf_rx=%d\n"
-+		      "intf_rx_err_recvframe=%d\n"
-+		      "intf_rx_err_skb=%d\n"
-+		      "intf_rx_report=%d\n"
-+		      "core_rx=%d\n"
-+		      "core_rx_pre=%d\n"
-+		      "core_rx_pre_ver_err=%d\n"
-+		      "core_rx_pre_mgmt=%d\n"
-+		      "core_rx_pre_mgmt_err_80211w=%d\n"
-+		      "core_rx_pre_mgmt_err=%d\n"
-+		      "core_rx_pre_ctrl=%d\n"
-+		      "core_rx_pre_ctrl_err=%d\n"
-+		      "core_rx_pre_data=%d\n"
-+		      "core_rx_pre_data_wapi_seq_err=%d\n"
-+		      "core_rx_pre_data_wapi_key_err=%d\n"
-+		      "core_rx_pre_data_handled=%d\n"
-+		      "core_rx_pre_data_err=%d\n"
-+		      "core_rx_pre_data_unknown=%d\n"
-+		      "core_rx_pre_unknown=%d\n"
-+		      "core_rx_enqueue=%d\n"
-+		      "core_rx_dequeue=%d\n"
-+		      "core_rx_post=%d\n"
-+		      "core_rx_post_decrypt=%d\n"
-+		      "core_rx_post_decrypt_wep=%d\n"
-+		      "core_rx_post_decrypt_tkip=%d\n"
-+		      "core_rx_post_decrypt_aes=%d\n"
-+		      "core_rx_post_decrypt_wapi=%d\n"
-+		      "core_rx_post_decrypt_hw=%d\n"
-+		      "core_rx_post_decrypt_unknown=%d\n"
-+		      "core_rx_post_decrypt_err=%d\n"
-+		      "core_rx_post_defrag_err=%d\n"
-+		      "core_rx_post_portctrl_err=%d\n"
-+		      "core_rx_post_indicate=%d\n"
-+		      "core_rx_post_indicate_in_oder=%d\n"
-+		      "core_rx_post_indicate_reoder=%d\n"
-+		      "core_rx_post_indicate_err=%d\n"
-+		      "os_indicate=%d\n"
-+		      "os_indicate_ap_mcast=%d\n"
-+		      "os_indicate_ap_forward=%d\n"
-+		      "os_indicate_ap_self=%d\n"
-+		      "os_indicate_err=%d\n"
-+		      "os_netif_ok=%d\n"
-+		      "os_netif_err=%d\n",
-+		      rx_logs->intf_rx,
-+		      rx_logs->intf_rx_err_recvframe,
-+		      rx_logs->intf_rx_err_skb,
-+		      rx_logs->intf_rx_report,
-+		      rx_logs->core_rx,
-+		      rx_logs->core_rx_pre,
-+		      rx_logs->core_rx_pre_ver_err,
-+		      rx_logs->core_rx_pre_mgmt,
-+		      rx_logs->core_rx_pre_mgmt_err_80211w,
-+		      rx_logs->core_rx_pre_mgmt_err,
-+		      rx_logs->core_rx_pre_ctrl,
-+		      rx_logs->core_rx_pre_ctrl_err,
-+		      rx_logs->core_rx_pre_data,
-+		      rx_logs->core_rx_pre_data_wapi_seq_err,
-+		      rx_logs->core_rx_pre_data_wapi_key_err,
-+		      rx_logs->core_rx_pre_data_handled,
-+		      rx_logs->core_rx_pre_data_err,
-+		      rx_logs->core_rx_pre_data_unknown,
-+		      rx_logs->core_rx_pre_unknown,
-+		      rx_logs->core_rx_enqueue,
-+		      rx_logs->core_rx_dequeue,
-+		      rx_logs->core_rx_post,
-+		      rx_logs->core_rx_post_decrypt,
-+		      rx_logs->core_rx_post_decrypt_wep,
-+		      rx_logs->core_rx_post_decrypt_tkip,
-+		      rx_logs->core_rx_post_decrypt_aes,
-+		      rx_logs->core_rx_post_decrypt_wapi,
-+		      rx_logs->core_rx_post_decrypt_hw,
-+		      rx_logs->core_rx_post_decrypt_unknown,
-+		      rx_logs->core_rx_post_decrypt_err,
-+		      rx_logs->core_rx_post_defrag_err,
-+		      rx_logs->core_rx_post_portctrl_err,
-+		      rx_logs->core_rx_post_indicate,
-+		      rx_logs->core_rx_post_indicate_in_oder,
-+		      rx_logs->core_rx_post_indicate_reoder,
-+		      rx_logs->core_rx_post_indicate_err,
-+		      rx_logs->os_indicate,
-+		      rx_logs->os_indicate_ap_mcast,
-+		      rx_logs->os_indicate_ap_forward,
-+		      rx_logs->os_indicate_ap_self,
-+		      rx_logs->os_indicate_err,
-+		      rx_logs->os_netif_ok,
-+		      rx_logs->os_netif_err
-+		     );
-+
-+	return 0;
-+}
-+
-+int proc_get_tx_logs(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct tx_logs *tx_logs = &padapter->tx_logs;
-+
-+	RTW_PRINT_SEL(m,
-+		      "os_tx=%d\n"
-+		      "os_tx_err_up=%d\n"
-+		      "os_tx_err_xmit=%d\n"
-+		      "os_tx_m2u=%d\n"
-+		      "os_tx_m2u_ignore_fw_linked=%d\n"
-+		      "os_tx_m2u_ignore_self=%d\n"
-+		      "os_tx_m2u_entry=%d\n"
-+		      "os_tx_m2u_entry_err_xmit=%d\n"
-+		      "os_tx_m2u_entry_err_skb=%d\n"
-+		      "os_tx_m2u_stop=%d\n"
-+		      "core_tx=%d\n"
-+		      "core_tx_err_pxmitframe=%d\n"
-+		      "core_tx_err_brtx=%d\n"
-+		      "core_tx_upd_attrib=%d\n"
-+		      "core_tx_upd_attrib_adhoc=%d\n"
-+		      "core_tx_upd_attrib_sta=%d\n"
-+		      "core_tx_upd_attrib_ap=%d\n"
-+		      "core_tx_upd_attrib_unknown=%d\n"
-+		      "core_tx_upd_attrib_dhcp=%d\n"
-+		      "core_tx_upd_attrib_icmp=%d\n"
-+		      "core_tx_upd_attrib_active=%d\n"
-+		      "core_tx_upd_attrib_err_ucast_sta=%d\n"
-+		      "core_tx_upd_attrib_err_ucast_ap_link=%d\n"
-+		      "core_tx_upd_attrib_err_sta=%d\n"
-+		      "core_tx_upd_attrib_err_link=%d\n"
-+		      "core_tx_upd_attrib_err_sec=%d\n"
-+		      "core_tx_ap_enqueue_warn_fwstate=%d\n"
-+		      "core_tx_ap_enqueue_warn_sta=%d\n"
-+		      "core_tx_ap_enqueue_warn_nosta=%d\n"
-+		      "core_tx_ap_enqueue_warn_link=%d\n"
-+		      "core_tx_ap_enqueue_warn_trigger=%d\n"
-+		      "core_tx_ap_enqueue_mcast=%d\n"
-+		      "core_tx_ap_enqueue_ucast=%d\n"
-+		      "core_tx_ap_enqueue=%d\n"
-+		      "intf_tx=%d\n"
-+		      "intf_tx_pending_ac=%d\n"
-+		      "intf_tx_pending_fw_under_survey=%d\n"
-+		      "intf_tx_pending_fw_under_linking=%d\n"
-+		      "intf_tx_pending_xmitbuf=%d\n"
-+		      "intf_tx_enqueue=%d\n"
-+		      "core_tx_enqueue=%d\n"
-+		      "core_tx_enqueue_class=%d\n"
-+		      "core_tx_enqueue_class_err_sta=%d\n"
-+		      "core_tx_enqueue_class_err_nosta=%d\n"
-+		      "core_tx_enqueue_class_err_fwlink=%d\n"
-+		      "intf_tx_direct=%d\n"
-+		      "intf_tx_direct_err_coalesce=%d\n"
-+		      "intf_tx_dequeue=%d\n"
-+		      "intf_tx_dequeue_err_coalesce=%d\n"
-+		      "intf_tx_dump_xframe=%d\n"
-+		      "intf_tx_dump_xframe_err_txdesc=%d\n"
-+		      "intf_tx_dump_xframe_err_port=%d\n",
-+		      tx_logs->os_tx,
-+		      tx_logs->os_tx_err_up,
-+		      tx_logs->os_tx_err_xmit,
-+		      tx_logs->os_tx_m2u,
-+		      tx_logs->os_tx_m2u_ignore_fw_linked,
-+		      tx_logs->os_tx_m2u_ignore_self,
-+		      tx_logs->os_tx_m2u_entry,
-+		      tx_logs->os_tx_m2u_entry_err_xmit,
-+		      tx_logs->os_tx_m2u_entry_err_skb,
-+		      tx_logs->os_tx_m2u_stop,
-+		      tx_logs->core_tx,
-+		      tx_logs->core_tx_err_pxmitframe,
-+		      tx_logs->core_tx_err_brtx,
-+		      tx_logs->core_tx_upd_attrib,
-+		      tx_logs->core_tx_upd_attrib_adhoc,
-+		      tx_logs->core_tx_upd_attrib_sta,
-+		      tx_logs->core_tx_upd_attrib_ap,
-+		      tx_logs->core_tx_upd_attrib_unknown,
-+		      tx_logs->core_tx_upd_attrib_dhcp,
-+		      tx_logs->core_tx_upd_attrib_icmp,
-+		      tx_logs->core_tx_upd_attrib_active,
-+		      tx_logs->core_tx_upd_attrib_err_ucast_sta,
-+		      tx_logs->core_tx_upd_attrib_err_ucast_ap_link,
-+		      tx_logs->core_tx_upd_attrib_err_sta,
-+		      tx_logs->core_tx_upd_attrib_err_link,
-+		      tx_logs->core_tx_upd_attrib_err_sec,
-+		      tx_logs->core_tx_ap_enqueue_warn_fwstate,
-+		      tx_logs->core_tx_ap_enqueue_warn_sta,
-+		      tx_logs->core_tx_ap_enqueue_warn_nosta,
-+		      tx_logs->core_tx_ap_enqueue_warn_link,
-+		      tx_logs->core_tx_ap_enqueue_warn_trigger,
-+		      tx_logs->core_tx_ap_enqueue_mcast,
-+		      tx_logs->core_tx_ap_enqueue_ucast,
-+		      tx_logs->core_tx_ap_enqueue,
-+		      tx_logs->intf_tx,
-+		      tx_logs->intf_tx_pending_ac,
-+		      tx_logs->intf_tx_pending_fw_under_survey,
-+		      tx_logs->intf_tx_pending_fw_under_linking,
-+		      tx_logs->intf_tx_pending_xmitbuf,
-+		      tx_logs->intf_tx_enqueue,
-+		      tx_logs->core_tx_enqueue,
-+		      tx_logs->core_tx_enqueue_class,
-+		      tx_logs->core_tx_enqueue_class_err_sta,
-+		      tx_logs->core_tx_enqueue_class_err_nosta,
-+		      tx_logs->core_tx_enqueue_class_err_fwlink,
-+		      tx_logs->intf_tx_direct,
-+		      tx_logs->intf_tx_direct_err_coalesce,
-+		      tx_logs->intf_tx_dequeue,
-+		      tx_logs->intf_tx_dequeue_err_coalesce,
-+		      tx_logs->intf_tx_dump_xframe,
-+		      tx_logs->intf_tx_dump_xframe_err_txdesc,
-+		      tx_logs->intf_tx_dump_xframe_err_port
-+		     );
-+
-+	return 0;
-+}
-+
-+int proc_get_int_logs(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m,
-+		      "all=%d\n"
-+		      "err=%d\n"
-+		      "tbdok=%d\n"
-+		      "tbder=%d\n"
-+		      "bcnderr=%d\n"
-+		      "bcndma=%d\n"
-+		      "bcndma_e=%d\n"
-+		      "rx=%d\n"
-+		      "rx_rdu=%d\n"
-+		      "rx_fovw=%d\n"
-+		      "txfovw=%d\n"
-+		      "mgntok=%d\n"
-+		      "highdok=%d\n"
-+		      "bkdok=%d\n"
-+		      "bedok=%d\n"
-+		      "vidok=%d\n"
-+		      "vodok=%d\n",
-+		      padapter->int_logs.all,
-+		      padapter->int_logs.err,
-+		      padapter->int_logs.tbdok,
-+		      padapter->int_logs.tbder,
-+		      padapter->int_logs.bcnderr,
-+		      padapter->int_logs.bcndma,
-+		      padapter->int_logs.bcndma_e,
-+		      padapter->int_logs.rx,
-+		      padapter->int_logs.rx_rdu,
-+		      padapter->int_logs.rx_fovw,
-+		      padapter->int_logs.txfovw,
-+		      padapter->int_logs.mgntok,
-+		      padapter->int_logs.highdok,
-+		      padapter->int_logs.bkdok,
-+		      padapter->int_logs.bedok,
-+		      padapter->int_logs.vidok,
-+		      padapter->int_logs.vodok
-+		     );
-+
-+	return 0;
-+}
-+
-+#endif /* CONFIG_DBG_COUNTER */
-+
-+int proc_get_hw_status(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
-+	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
-+
-+	if (regsty->check_hw_status == 0)
-+		RTW_PRINT_SEL(m, "RX FIFO full count: not check in watch dog\n");
-+	else if (pdbgpriv->dbg_rx_fifo_last_overflow == 1
-+	    && pdbgpriv->dbg_rx_fifo_curr_overflow == 1
-+	    && pdbgpriv->dbg_rx_fifo_diff_overflow == 1
-+	   )
-+		RTW_PRINT_SEL(m, "RX FIFO full count: no implementation\n");
-+	else {
-+		RTW_PRINT_SEL(m, "RX FIFO full count: last_time=%llu, current_time=%llu, differential=%llu\n"
-+			, pdbgpriv->dbg_rx_fifo_last_overflow, pdbgpriv->dbg_rx_fifo_curr_overflow, pdbgpriv->dbg_rx_fifo_diff_overflow);
-+	}
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = padapter->dvobj;
-+	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
-+	char tmp[32];
-+	u32 enable;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &enable);
-+
-+		if (num == 1 && regsty && enable <= 1) {
-+			regsty->check_hw_status = enable;
-+			RTW_INFO("check_hw_status=%d\n", regsty->check_hw_status);
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+#ifdef CONFIG_HUAWEI_PROC
-+int proc_get_huawei_trx_info(struct seq_file *sel, void *v)
-+{
-+	struct net_device *dev = sel->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dm_struct *dm = adapter_to_phydm(padapter);
-+	struct sta_info *psta;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	struct ra_sta_info *ra_info;
-+	u8 curr_tx_sgi = _FALSE;
-+	u8 curr_tx_rate = 0;
-+	u8 mac_id;
-+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
-+	u8 isCCKrate, rf_path;
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
-+#endif
-+
-+	if (!dm->is_linked) {
-+		RTW_PRINT_SEL(sel, "NO link\n\n");
-+		return 0;
-+	}
-+
-+	/*============  tx info ============	*/
-+	for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {
-+		if (rtw_macid_is_used(macid_ctl, mac_id) && !rtw_macid_is_bmc(macid_ctl, mac_id)) {
-+			psta = macid_ctl->sta[mac_id];
-+			if (!psta)
-+				continue;
-+
-+			RTW_PRINT_SEL(sel, "STA [" MAC_FMT "]\n", MAC_ARG(psta->cmn.mac_addr));
-+
-+			ra_info = &psta->cmn.ra_info;
-+			curr_tx_sgi = rtw_get_current_tx_sgi(padapter, psta);
-+			curr_tx_rate = rtw_get_current_tx_rate(padapter, psta);
-+			RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n",
-+					HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L");
-+			RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw));
-+		}
-+	}
-+
-+	/*============  rx info ============	*/
-+	RTW_PRINT_SEL(sel, "rx_rate : %s\n", HDATA_RATE(dm->rx_rate));
-+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
-+	isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
-+
-+	for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++) {
-+		if (!(GET_HAL_RX_PATH_BMP(padapter) & BIT(rf_path)))
-+			continue;
-+		if (!isCCKrate)
-+			_RTW_PRINT_SEL(sel , "RF_PATH_%d : rx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
-+				rf_path, psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
-+	}
-+#endif
-+	RTW_PRINT_SEL(sel, "\n");
-+	return 0;
-+}
-+#endif /* CONFIG_HUAWEI_PROC */
-+
-+int proc_get_trx_info_debug(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	/*============  tx info ============	*/
-+	rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, m);
-+
-+	/*============  rx info ============	*/
-+	rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, m, _FALSE);
-+
-+	return 0;
-+}
-+
-+int proc_get_rx_signal(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m, "rssi:%d\n", padapter->recvpriv.rssi);
-+#ifdef CONFIG_MP_INCLUDED
-+	if (padapter->registrypriv.mp_mode == 1) {
-+		struct dm_struct *odm = adapter_to_phydm(padapter);
-+		if (padapter->mppriv.antenna_rx == ANTENNA_A)
-+			RTW_PRINT_SEL(m, "Antenna: A\n");
-+		else if (padapter->mppriv.antenna_rx == ANTENNA_B)
-+			RTW_PRINT_SEL(m, "Antenna: B\n");
-+		else if (padapter->mppriv.antenna_rx == ANTENNA_C)
-+			RTW_PRINT_SEL(m, "Antenna: C\n");
-+		else if (padapter->mppriv.antenna_rx == ANTENNA_D)
-+			RTW_PRINT_SEL(m, "Antenna: D\n");
-+		else if (padapter->mppriv.antenna_rx == ANTENNA_AB)
-+			RTW_PRINT_SEL(m, "Antenna: AB\n");
-+		else if (padapter->mppriv.antenna_rx == ANTENNA_BC)
-+			RTW_PRINT_SEL(m, "Antenna: BC\n");
-+		else if (padapter->mppriv.antenna_rx == ANTENNA_CD)
-+			RTW_PRINT_SEL(m, "Antenna: CD\n");
-+		else
-+			RTW_PRINT_SEL(m, "Antenna: __\n");
-+
-+		RTW_PRINT_SEL(m, "rx_rate = %s\n", HDATA_RATE(odm->rx_rate));
-+		return 0;
-+	} else 
-+#endif
-+	{
-+		/* RTW_PRINT_SEL(m, "rxpwdb:%d\n", padapter->recvpriv.rxpwdb); */
-+		RTW_PRINT_SEL(m, "signal_strength:%u\n", padapter->recvpriv.signal_strength);
-+		RTW_PRINT_SEL(m, "signal_qual:%u\n", padapter->recvpriv.signal_qual);
-+	}
-+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
-+	rtw_odm_get_perpkt_rssi(m, padapter);
-+	rtw_get_raw_rssi_info(m, padapter);
-+#endif
-+	return 0;
-+}
-+
-+ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u32 is_signal_dbg, signal_strength;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%u %u", &is_signal_dbg, &signal_strength);
-+
-+		if (num < 1)
-+			return count;
-+
-+		is_signal_dbg = is_signal_dbg == 0 ? 0 : 1;
-+
-+		if (is_signal_dbg && num < 2)
-+			return count;
-+
-+		signal_strength = signal_strength > 100 ? 100 : signal_strength;
-+
-+		padapter->recvpriv.is_signal_dbg = is_signal_dbg;
-+		padapter->recvpriv.signal_strength_dbg = signal_strength;
-+
-+		if (is_signal_dbg)
-+			RTW_INFO("set %s %u\n", "DBG_SIGNAL_STRENGTH", signal_strength);
-+		else
-+			RTW_INFO("set %s\n", "HW_SIGNAL_STRENGTH");
-+
-+	}
-+
-+	return count;
-+
-+}
-+
-+int proc_get_mac_rptbuf(struct seq_file *m, void *v)
-+{
-+#ifdef CONFIG_RTL8814A
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u16 i;
-+	u16 mac_id;
-+	u32 shcut_addr = 0;
-+	u32 read_addr = 0;
-+
-+	RTW_PRINT_SEL(m, "TX ShortCut:\n");
-+	for (mac_id = 0; mac_id < 64; mac_id++) {
-+		rtw_write16(padapter, 0x140, 0x662 | ((mac_id & BIT5) >> 5));
-+		shcut_addr = 0x8000;
-+		shcut_addr = shcut_addr | ((mac_id & 0x1f) << 7);
-+		RTW_PRINT_SEL(m, "mac_id=%d, 0x140=%x =>\n", mac_id, 0x662 | ((mac_id & BIT5) >> 5));
-+		for (i = 0; i < 30; i++) {
-+			read_addr = 0;
-+			read_addr = shcut_addr | (i << 2);
-+			RTW_PRINT_SEL(m, "i=%02d: MAC_%04x= %08x ", i, read_addr, rtw_read32(padapter, read_addr));
-+			if (!((i + 1) % 4))
-+				RTW_PRINT_SEL(m, "\n");
-+			if (i == 29)
-+				RTW_PRINT_SEL(m, "\n");
-+		}
-+	}
-+#endif /* CONFIG_RTL8814A */
-+	return 0;
-+}
-+
-+#ifdef CONFIG_80211N_HT
-+
-+int proc_get_ht_enable(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+
-+	if (pregpriv)
-+		RTW_PRINT_SEL(m, "%d\n", pregpriv->ht_enable);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	char tmp[32];
-+	u32 mode;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &mode);
-+
-+		if ( num == 1 && pregpriv && mode < 2) {
-+			pregpriv->ht_enable = mode;
-+			RTW_INFO("ht_enable=%d\n", pregpriv->ht_enable);
-+		}
-+	}
-+
-+	return count;
-+
-+}
-+
-+int proc_get_bw_mode(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+
-+	if (pregpriv)
-+		RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->bw_mode);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	char tmp[32];
-+	u32 mode;
-+	u8 bw_2g;
-+	u8 bw_5g;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%x ", &mode);
-+		bw_5g = mode >> 4;
-+		bw_2g = mode & 0x0f;
-+
-+		if (num == 1 && pregpriv && bw_2g <= 4 && bw_5g <= 4) {
-+			pregpriv->bw_mode = mode;
-+			printk("bw_mode=0x%x\n", mode);
-+		}
-+	}
-+
-+	return count;
-+
-+}
-+
-+int proc_get_ampdu_enable(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+
-+	if (pregpriv)
-+		RTW_PRINT_SEL(m, "%d\n", pregpriv->ampdu_enable);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	char tmp[32];
-+	u32 mode;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &mode);
-+
-+		if (num == 1 && pregpriv && mode < 2) {
-+			pregpriv->ampdu_enable = mode;
-+			printk("ampdu_enable=%d\n", mode);
-+		}
-+
-+	}
-+
-+	return count;
-+
-+}
-+
-+
-+void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter)
-+{
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+	int i;
-+
-+	RTW_PRINT_SEL(sel, "%-3s %-3s %-3s %-3s %-4s\n"
-+		, "", "20M", "40M", "80M", "160M");
-+	for (i = 0; i < 4; i++)
-+		RTW_PRINT_SEL(sel, "%dSS %3u %3u %3u %4u\n", i + 1
-+			, regsty->rx_ampdu_sz_limit_by_nss_bw[i][0]
-+			, regsty->rx_ampdu_sz_limit_by_nss_bw[i][1]
-+			, regsty->rx_ampdu_sz_limit_by_nss_bw[i][2]
-+			, regsty->rx_ampdu_sz_limit_by_nss_bw[i][3]);
-+}
-+
-+int proc_get_rx_ampdu(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	_RTW_PRINT_SEL(m, "accept: ");
-+	if (padapter->fix_rx_ampdu_accept == RX_AMPDU_ACCEPT_INVALID)
-+		RTW_PRINT_SEL(m, "%u%s\n", rtw_rx_ampdu_is_accept(padapter), "(auto)");
-+	else
-+		RTW_PRINT_SEL(m, "%u%s\n", padapter->fix_rx_ampdu_accept, "(fixed)");
-+
-+	_RTW_PRINT_SEL(m, "size: ");
-+	if (padapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID) {
-+		RTW_PRINT_SEL(m, "%u%s\n", rtw_rx_ampdu_size(padapter), "(auto) with conditional limit:");
-+		dump_regsty_rx_ampdu_size_limit(m, padapter);
-+	} else
-+		RTW_PRINT_SEL(m, "%u%s\n", padapter->fix_rx_ampdu_size, "(fixed)");
-+	RTW_PRINT_SEL(m, "\n");
-+
-+	RTW_PRINT_SEL(m, "%19s %17s\n", "fix_rx_ampdu_accept", "fix_rx_ampdu_size");
-+
-+	_RTW_PRINT_SEL(m, "%-19d %-17u\n"
-+		, padapter->fix_rx_ampdu_accept
-+		, padapter->fix_rx_ampdu_size);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 accept;
-+	u8 size;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu %hhu", &accept, &size);
-+
-+		if (num >= 1)
-+			rtw_rx_ampdu_set_accept(padapter, accept, RX_AMPDU_DRV_FIXED);
-+		if (num >= 2)
-+			rtw_rx_ampdu_set_size(padapter, size, RX_AMPDU_DRV_FIXED);
-+
-+		rtw_rx_ampdu_apply(padapter);
-+	}
-+
-+	return count;
-+}
-+#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+int proc_get_tx_aval_th(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	if (padapter) {
-+
-+		switch(dvobj->tx_aval_int_thr_mode) {
-+			case 0:
-+				RTW_PRINT_SEL(m, "tx_aval_int_thr_mode = %u (auto) \n", dvobj->tx_aval_int_thr_mode);
-+				break;
-+			case 1:
-+				RTW_PRINT_SEL(m, "tx_aval_int_thr_mode = %u (fixed)\n", dvobj->tx_aval_int_thr_mode);
-+				RTW_PRINT_SEL(m, "tx_aval_threshold = 0x%x\n", dvobj->tx_aval_int_thr_value);
-+				break;
-+			case 2:
-+				RTW_PRINT_SEL(m, "tx_aval_int_thr_mode = %u(by sdio_tx_max_len)\n", dvobj->tx_aval_int_thr_mode);
-+			   	break;
-+			default:
-+				break;
-+		}
-+	}
-+	return 0;
-+}
-+
-+ssize_t proc_set_tx_aval_th(struct file *file, const char __user *buffer
-+				 , size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	char tmp[32];
-+	u32 mode;
-+	u32 threshold;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d %d ",&mode, &threshold);
-+
-+		if(num >= 1)
-+			dvobj->tx_aval_int_thr_mode = mode;
-+		if(num >= 2)
-+			dvobj->tx_aval_int_thr_value = threshold;
-+		RTW_INFO("dvobj->tx_aval_int_thr_mode= 0x%x\n", mode);
-+		RTW_INFO("dvobj->tx_aval_int_thr_value= 0x%x(range need 1~255)\n", threshold);
-+	}
-+
-+	return count;
-+}
-+#endif /*CONFIG_SDIO_TX_ENABLE_AVAL_INT*/
-+
-+int proc_get_rx_ampdu_factor(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+
-+	if (padapter)
-+		RTW_PRINT_SEL(m, "rx ampdu factor = %x\n", padapter->driver_rx_ampdu_factor);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer
-+				 , size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u32 factor;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &factor);
-+
-+		if (padapter && (num == 1)) {
-+			RTW_INFO("padapter->driver_rx_ampdu_factor = %x\n", factor);
-+
-+			if (factor  > 0x03)
-+				padapter->driver_rx_ampdu_factor = 0xFF;
-+			else
-+				padapter->driver_rx_ampdu_factor = factor;
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_tx_max_agg_num(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+
-+	if (padapter)
-+		RTW_PRINT_SEL(m, "tx max AMPDU num = 0x%02x\n", padapter->driver_tx_max_agg_num);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_tx_max_agg_num(struct file *file, const char __user *buffer
-+				 , size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 agg_num;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhx ", &agg_num);
-+
-+		if (padapter && (num == 1)) {
-+			RTW_INFO("padapter->driver_tx_max_agg_num = 0x%02x\n", agg_num);
-+
-+			padapter->driver_tx_max_agg_num = agg_num;
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_rx_ampdu_density(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+
-+	if (padapter)
-+		RTW_PRINT_SEL(m, "rx ampdu densityg = %x\n", padapter->driver_rx_ampdu_spacing);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u32 density;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &density);
-+
-+		if (padapter && (num == 1)) {
-+			RTW_INFO("padapter->driver_rx_ampdu_spacing = %x\n", density);
-+
-+			if (density > 0x07)
-+				padapter->driver_rx_ampdu_spacing = 0xFF;
-+			else
-+				padapter->driver_rx_ampdu_spacing = density;
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_tx_ampdu_density(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+
-+	if (padapter)
-+		RTW_PRINT_SEL(m, "tx ampdu density = %x\n", padapter->driver_ampdu_spacing);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u32 density;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &density);
-+
-+		if (padapter && (num == 1)) {
-+			RTW_INFO("padapter->driver_ampdu_spacing = %x\n", density);
-+
-+			if (density > 0x07)
-+				padapter->driver_ampdu_spacing = 0xFF;
-+			else
-+				padapter->driver_ampdu_spacing = density;
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_tx_quick_addba_req(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+
-+	if (padapter)
-+		RTW_PRINT_SEL(m, "tx_quick_addba_req = %x\n", pregpriv->tx_quick_addba_req);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_tx_quick_addba_req(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	char tmp[32];
-+	u32 enable;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &enable);
-+
-+		if (padapter && (num == 1)) {
-+			pregpriv->tx_quick_addba_req = enable;
-+			RTW_INFO("tx_quick_addba_req = %d\n", pregpriv->tx_quick_addba_req);
-+		}
-+	}
-+
-+	return count;
-+}
-+#ifdef CONFIG_TX_AMSDU
-+int proc_get_tx_amsdu(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+
-+	if (padapter)
-+	{
-+		RTW_PRINT_SEL(m, "tx amsdu = %d\n", padapter->tx_amsdu);
-+		RTW_PRINT_SEL(m, "amsdu set timer conut = %u\n", pxmitpriv->amsdu_debug_set_timer);
-+		RTW_PRINT_SEL(m, "amsdu  time out count = %u\n", pxmitpriv->amsdu_debug_timeout);
-+		RTW_PRINT_SEL(m, "amsdu coalesce one count = %u\n", pxmitpriv->amsdu_debug_coalesce_one);
-+		RTW_PRINT_SEL(m, "amsdu coalesce two count = %u\n", pxmitpriv->amsdu_debug_coalesce_two);
-+	}
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_tx_amsdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	char tmp[32];
-+	u32 amsdu;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &amsdu);
-+
-+		if (padapter && (num == 1)) {
-+			RTW_INFO("padapter->tx_amsdu = %x\n", amsdu);
-+
-+			if (amsdu > 3)
-+				padapter->tx_amsdu = 0;
-+			else if(amsdu == 3)
-+			{
-+				pxmitpriv->amsdu_debug_set_timer = 0;
-+				pxmitpriv->amsdu_debug_timeout = 0;
-+				pxmitpriv->amsdu_debug_coalesce_one = 0;
-+				pxmitpriv->amsdu_debug_coalesce_two = 0;
-+			}
-+			else
-+				padapter->tx_amsdu = amsdu;
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_tx_amsdu_rate(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (padapter)
-+		RTW_PRINT_SEL(m, "tx amsdu rate = %d Mbps\n", padapter->tx_amsdu_rate);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u32 amsdu_rate;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &amsdu_rate);
-+
-+		if (padapter && (num == 1)) {
-+			RTW_INFO("padapter->tx_amsdu_rate = %x\n", amsdu_rate);
-+			padapter->tx_amsdu_rate = amsdu_rate;
-+		}
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_TX_AMSDU */
-+#endif /* CONFIG_80211N_HT */
-+
-+#ifdef CONFIG_80211AC_VHT
-+int proc_get_vht_24g_enable(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+
-+	if (pregpriv)
-+		RTW_PRINT_SEL(m, "%d\n", pregpriv->vht_24g_enable);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_vht_24g_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	char tmp[32];
-+	u32 mode;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &mode);
-+
-+		if ((num == 1) && pregpriv && (mode < 2)) {
-+			pregpriv->vht_24g_enable = mode;
-+			RTW_INFO("vht_24g_enable = %d\n", pregpriv->vht_24g_enable);
-+		}
-+	}
-+
-+	return count;
-+
-+}
-+#endif
-+
-+ssize_t proc_set_dyn_rrsr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv *pregpriv = &padapter->registrypriv;
-+
-+	char tmp[32] = {0};
-+	u32 num = 0, enable = 0, rrsr_val = 0; /* gpio_mode:0 input  1:output; */
-+
-+	if (count < 2)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		num	= sscanf(tmp, "%d 0x%x", &enable, &rrsr_val);
-+		RTW_INFO("num=%u enable=%d rrsr_val=0x%x\n", num, enable, rrsr_val);
-+		pregpriv->en_dyn_rrsr = enable;
-+		pregpriv->set_rrsr_value = rrsr_val;
-+		rtw_phydm_dyn_rrsr_en(padapter, enable);
-+		rtw_phydm_set_rrsr(padapter, rrsr_val, TRUE);
-+
-+	}
-+	return count;
-+
-+}
-+int proc_get_dyn_rrsr(struct seq_file *m, void *v) {
-+
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv *pregpriv = &padapter->registrypriv;
-+	u32 init_rrsr =0xFFFFFFFF;
-+
-+	if (padapter) 
-+		RTW_PRINT_SEL(m, "en_dyn_rrsr = %d fixed_rrsr_value =0x%x %s\n"
-+			, pregpriv->en_dyn_rrsr
-+			, pregpriv->set_rrsr_value 
-+			, (pregpriv->set_rrsr_value == init_rrsr)?"(default)":"(fixed)"
-+		);
-+
-+	return 0;
-+}
-+int proc_get_en_fwps(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+
-+	if (pregpriv)
-+		RTW_PRINT_SEL(m, "check_fw_ps = %d , 1:enable get FW PS state , 0: disable get FW PS state\n"
-+			      , pregpriv->check_fw_ps);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	char tmp[32];
-+	u32 mode;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &mode);
-+
-+		if (num == 1 && pregpriv &&  mode < 2) {
-+			pregpriv->check_fw_ps = mode;
-+			RTW_INFO("pregpriv->check_fw_ps=%d\n", pregpriv->check_fw_ps);
-+		}
-+
-+	}
-+
-+	return count;
-+}
-+
-+/*
-+int proc_get_two_path_rssi(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if(padapter)
-+		RTW_PRINT_SEL(m, "%d %d\n",
-+			padapter->recvpriv.RxRssi[0], padapter->recvpriv.RxRssi[1]);
-+
-+	return 0;
-+}
-+*/
-+#ifdef CONFIG_80211N_HT
-+void rtw_dump_dft_phy_cap(void *sel, _adapter *adapter)
-+{
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct ht_priv	*phtpriv = &pmlmepriv->htpriv;
-+	#ifdef CONFIG_80211AC_VHT
-+	struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
-+	#endif
-+
-+	#ifdef CONFIG_80211AC_VHT
-+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) ? "V" : "X");
-+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) ? "V" : "X");
-+	#endif
-+	RTW_PRINT_SEL(sel, "[DFT CAP] HT STBC Tx : %s\n", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) ? "V" : "X");
-+	RTW_PRINT_SEL(sel, "[DFT CAP] HT STBC Rx : %s\n\n", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) ? "V" : "X");
-+
-+	#ifdef CONFIG_80211AC_VHT
-+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT LDPC Tx : %s\n", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX)) ? "V" : "X");
-+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) ? "V" : "X");
-+	#endif
-+	RTW_PRINT_SEL(sel, "[DFT CAP] HT LDPC Tx : %s\n", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX)) ? "V" : "X");
-+	RTW_PRINT_SEL(sel, "[DFT CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) ? "V" : "X");
-+
-+	#ifdef CONFIG_BEAMFORMING
-+	#ifdef CONFIG_80211AC_VHT
-+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT MU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) ? "V" : "X");
-+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT MU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) ? "V" : "X");
-+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT SU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) ? "V" : "X");
-+	RTW_PRINT_SEL(sel, "[DFT CAP] VHT SU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) ? "V" : "X");
-+	#endif
-+	RTW_PRINT_SEL(sel, "[DFT CAP] HT Bfer : %s\n", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE))  ? "V" : "X");
-+	RTW_PRINT_SEL(sel, "[DFT CAP] HT Bfee : %s\n", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) ? "V" : "X");
-+	#endif
-+}
-+
-+void rtw_get_dft_phy_cap(void *sel, _adapter *adapter)
-+{
-+	RTW_PRINT_SEL(sel, "\n ======== PHY CAP protocol ========\n");
-+	rtw_ht_use_default_setting(adapter);
-+	#ifdef CONFIG_80211AC_VHT
-+	rtw_vht_use_default_setting(adapter);
-+	#endif
-+	#ifdef CONFIG_80211N_HT
-+	rtw_dump_dft_phy_cap(sel, adapter);
-+	#endif
-+}
-+
-+void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter)
-+{
-+	struct registry_priv	*pregistry_priv = &adapter->registrypriv;
-+
-+	RTW_PRINT_SEL(sel, "\n ======== DRV's configuration ========\n");
-+	#if 0
-+	RTW_PRINT_SEL(sel, "[DRV CAP] TRx Capability : 0x%08x\n", phy_spec->trx_cap);
-+	RTW_PRINT_SEL(sel, "[DRV CAP] Tx Stream Num Index : %d\n", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/
-+	RTW_PRINT_SEL(sel, "[DRV CAP] Rx Stream Num Index : %d\n", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/
-+	RTW_PRINT_SEL(sel, "[DRV CAP] Tx Path Num Index : %d\n", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index	[15:8]*/
-+	RTW_PRINT_SEL(sel, "[DRV CAP] Rx Path Num Index : %d\n", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index	[7:0]*/
-+	#endif
-+	#ifdef CONFIG_80211N_HT
-+	RTW_PRINT_SEL(sel, "[DRV CAP] STBC Capability : 0x%02x\n", pregistry_priv->stbc_cap);
-+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT STBC Tx*/
-+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT STBC Rx*/
-+	RTW_PRINT_SEL(sel, "[DRV CAP] HT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT STBC Tx*/
-+	RTW_PRINT_SEL(sel, "[DRV CAP] HT STBC Rx : %s\n\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT STBC Rx*/
-+
-+	RTW_PRINT_SEL(sel, "[DRV CAP] LDPC Capability : 0x%02x\n", pregistry_priv->ldpc_cap);
-+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT LDPC Tx*/
-+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT LDPC Rx*/
-+	RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT LDPC Tx*/
-+	RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT LDPC Rx*/
-+	#endif /* CONFIG_80211N_HT */
-+	#ifdef CONFIG_BEAMFORMING
-+	#if 0
-+	RTW_PRINT_SEL(sel, "[DRV CAP] TxBF parameter : 0x%08x\n", phy_spec->txbf_param);
-+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT Sounding Dim : %d\n", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/
-+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT Steering Ant : %d\n", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/
-+	RTW_PRINT_SEL(sel, "[DRV CAP] HT Sounding Dim : %d\n", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/
-+	RTW_PRINT_SEL(sel, "[DRV CAP] HT Steering Ant : %d\n", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/
-+	#endif
-+
-+	/*
-+	 * BIT0: Enable VHT SU Beamformer
-+	 * BIT1: Enable VHT SU Beamformee
-+	 * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer
-+	 * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee
-+	 * BIT4: Enable HT Beamformer
-+	 * BIT5: Enable HT Beamformee
-+	 */
-+	RTW_PRINT_SEL(sel, "[DRV CAP] TxBF Capability : 0x%02x\n", pregistry_priv->beamform_cap);
-+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT MU Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT2)) ? "V" : "X");
-+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT MU Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT3)) ? "V" : "X");
-+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT SU Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT0)) ? "V" : "X");
-+	RTW_PRINT_SEL(sel, "[DRV CAP] VHT SU Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT1)) ? "V" : "X");
-+	RTW_PRINT_SEL(sel, "[DRV CAP] HT Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT4))  ? "V" : "X");
-+	RTW_PRINT_SEL(sel, "[DRV CAP] HT Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT5)) ? "V" : "X");
-+
-+	RTW_PRINT_SEL(sel, "[DRV CAP] Tx Bfer rf_num : %d\n", pregistry_priv->beamformer_rf_num);
-+	RTW_PRINT_SEL(sel, "[DRV CAP] Tx Bfee rf_num : %d\n", pregistry_priv->beamformee_rf_num);
-+	#endif
-+}
-+
-+int proc_get_stbc_cap(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+
-+	if (pregpriv)
-+		RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->stbc_cap);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	char tmp[32];
-+	u32 mode;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &mode);
-+
-+		if (num == 1 && pregpriv) {
-+			pregpriv->stbc_cap = mode;
-+			RTW_INFO("stbc_cap = 0x%02x\n", mode);
-+		}
-+	}
-+
-+	return count;
-+}
-+int proc_get_rx_stbc(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+
-+	if (pregpriv)
-+		RTW_PRINT_SEL(m, "%d\n", pregpriv->rx_stbc);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	char tmp[32];
-+	u32 mode;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &mode);
-+
-+		if (num == 1 && pregpriv && (mode == 0 || mode == 1 || mode == 2 || mode == 3)) {
-+			pregpriv->rx_stbc = mode;
-+			printk("rx_stbc=%d\n", mode);
-+		}
-+	}
-+
-+	return count;
-+
-+}
-+int proc_get_ldpc_cap(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+
-+	if (pregpriv)
-+		RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->ldpc_cap);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	char tmp[32];
-+	u32 mode;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &mode);
-+
-+		if (num == 1 && pregpriv) {
-+			pregpriv->ldpc_cap = mode;
-+			RTW_INFO("ldpc_cap = 0x%02x\n", mode);
-+		}
-+	}
-+
-+	return count;
-+}
-+#ifdef CONFIG_BEAMFORMING
-+int proc_get_txbf_cap(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+
-+	if (pregpriv)
-+		RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->beamform_cap);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	char tmp[32];
-+	u32 mode;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &mode);
-+
-+		if (num == 1 && pregpriv) {
-+			pregpriv->beamform_cap = mode;
-+			RTW_INFO("beamform_cap = 0x%02x\n", mode);
-+		}
-+	}
-+
-+	return count;
-+}
-+#endif
-+#endif /* CONFIG_80211N_HT */
-+
-+/*int proc_get_rssi_disp(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	return 0;
-+}
-+*/
-+
-+/*ssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u32 enable=0;
-+
-+	if (count < 1)
-+	{
-+		RTW_INFO("argument size is less than 1\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%x", &enable);
-+
-+		if (num !=  1) {
-+			RTW_INFO("invalid set_rssi_disp parameter!\n");
-+			return count;
-+		}
-+
-+		if(enable)
-+		{
-+			RTW_INFO("Linked info Function Enable\n");
-+			padapter->bLinkInfoDump = enable ;
-+		}
-+		else
-+		{
-+			RTW_INFO("Linked info Function Disable\n");
-+			padapter->bLinkInfoDump = 0 ;
-+		}
-+
-+	}
-+
-+	return count;
-+
-+}
-+
-+*/
-+#ifdef CONFIG_AP_MODE
-+
-+int proc_get_all_sta_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_irqL irqL;
-+	struct sta_info *psta;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	int i;
-+	_list	*plist, *phead;
-+
-+	RTW_MAP_DUMP_SEL(m, "sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
-+	RTW_MAP_DUMP_SEL(m, "tim_bitmap=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len);
-+
-+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+	for (i = 0; i < NUM_STA; i++) {
-+		phead = &(pstapriv->sta_hash[i]);
-+		plist = get_next(phead);
-+
-+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+
-+			plist = get_next(plist);
-+
-+			/* if(extra_arg == psta->cmn.aid) */
-+			{
-+				RTW_PRINT_SEL(m, "==============================\n");
-+				RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
-+				RTW_PRINT_SEL(m, "rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self);
-+				RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n",
-+					psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);
-+#ifdef CONFIG_RTS_FULL_BW
-+				if(psta->vendor_8812)
-+					RTW_PRINT_SEL(m,"Vendor Realtek 8812\n");
-+#endif/*CONFIG_RTS_FULL_BW*/
-+#ifdef CONFIG_80211N_HT
-+				RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
-+				RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n"
-+					, psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);
-+				RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
-+				RTW_PRINT_SEL(m, "tx_amsdu_enable = %d\n", psta->htpriv.tx_amsdu_enable);
-+				RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
-+#endif /* CONFIG_80211N_HT */
-+#ifdef CONFIG_80211AC_VHT
-+				RTW_PRINT_SEL(m, "vht_en=%d, vht_sgi_80m=%d\n", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m);
-+				RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap);
-+				RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len);
-+#endif
-+				RTW_PRINT_SEL(m, "sleepq_len=%d\n", psta->sleepq_len);
-+				RTW_PRINT_SEL(m, "sta_xmitpriv.vo_q_qcnt=%d\n", psta->sta_xmitpriv.vo_q.qcnt);
-+				RTW_PRINT_SEL(m, "sta_xmitpriv.vi_q_qcnt=%d\n", psta->sta_xmitpriv.vi_q.qcnt);
-+				RTW_PRINT_SEL(m, "sta_xmitpriv.be_q_qcnt=%d\n", psta->sta_xmitpriv.be_q.qcnt);
-+				RTW_PRINT_SEL(m, "sta_xmitpriv.bk_q_qcnt=%d\n", psta->sta_xmitpriv.bk_q.qcnt);
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+				RTW_PRINT_SEL(m, "management sleepq_len=%d\n", psta->mgmt_sleepq_len);
-+				RTW_PRINT_SEL(m, "sta_xmitpriv.mgmt_q_qcnt=%d\n", psta->sta_xmitpriv.mgmt_q.qcnt);
-+#endif
-+
-+				RTW_PRINT_SEL(m, "capability=0x%x\n", psta->capability);
-+				RTW_PRINT_SEL(m, "flags=0x%x\n", psta->flags);
-+				RTW_PRINT_SEL(m, "wpa_psk=0x%x\n", psta->wpa_psk);
-+				RTW_PRINT_SEL(m, "wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher);
-+				RTW_PRINT_SEL(m, "wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher);
-+				RTW_PRINT_SEL(m, "qos_info=0x%x\n", psta->qos_info);
-+				RTW_PRINT_SEL(m, "dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy);
-+
-+				sta_rx_reorder_ctl_dump(m, psta);
-+
-+#ifdef CONFIG_TDLS
-+				RTW_PRINT_SEL(m, "tdls_sta_state=0x%08x\n", psta->tdls_sta_state);
-+				RTW_PRINT_SEL(m, "PeerKey_Lifetime=%d\n", psta->TDLS_PeerKey_Lifetime);
-+#endif /* CONFIG_TDLS */
-+				RTW_PRINT_SEL(m, "rx_data_uc_pkts=%llu\n", sta_rx_data_uc_pkts(psta));
-+				RTW_PRINT_SEL(m, "rx_data_mc_pkts=%llu\n", psta->sta_stats.rx_data_mc_pkts);
-+				RTW_PRINT_SEL(m, "rx_data_bc_pkts=%llu\n", psta->sta_stats.rx_data_bc_pkts);
-+				RTW_PRINT_SEL(m, "rx_uc_bytes=%llu\n", sta_rx_uc_bytes(psta));
-+				RTW_PRINT_SEL(m, "rx_mc_bytes=%llu\n", psta->sta_stats.rx_mc_bytes);
-+				RTW_PRINT_SEL(m, "rx_bc_bytes=%llu\n", psta->sta_stats.rx_bc_bytes);
-+				if (psta->sta_stats.rx_tp_kbits >> 10)
-+					RTW_PRINT_SEL(m, "rx_tp =%d (Mbps)\n", psta->sta_stats.rx_tp_kbits >> 10);
-+				else
-+					RTW_PRINT_SEL(m, "rx_tp =%d (Kbps)\n", psta->sta_stats.rx_tp_kbits);
-+
-+				RTW_PRINT_SEL(m, "tx_data_pkts=%llu\n", psta->sta_stats.tx_pkts);
-+				RTW_PRINT_SEL(m, "tx_bytes=%llu\n", psta->sta_stats.tx_bytes);
-+				if (psta->sta_stats.tx_tp_kbits >> 10)
-+					RTW_PRINT_SEL(m, "tx_tp =%d (Mbps)\n", psta->sta_stats.tx_tp_kbits >> 10);
-+				else
-+					RTW_PRINT_SEL(m, "tx_tp =%d (Kbps)\n", psta->sta_stats.tx_tp_kbits);
-+#ifdef CONFIG_RTW_80211K
-+				RTW_PRINT_SEL(m, "rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(psta->rm_en_cap));
-+#endif
-+				dump_st_ctl(m, &psta->st_ctl);
-+
-+				if (STA_OP_WFD_MODE(psta))
-+					RTW_PRINT_SEL(m, "op_wfd_mode:0x%02x\n", STA_OP_WFD_MODE(psta));
-+
-+				RTW_PRINT_SEL(m, "tx_bitrate_100kbps=%u\n", rtw_desc_rate_to_bitrate(psta->cmn.bw_mode, rtw_get_current_tx_rate(padapter, psta), rtw_get_current_tx_sgi(padapter, psta)));
-+				RTW_PRINT_SEL(m, "rx_bitrate_100kbps=%u\n", rtw_desc_rate_to_bitrate(psta->cmn.bw_mode, psta->curr_rx_rate & 0x7f, (psta->curr_rx_rate & 0x80) >> 7));
-+				RTW_PRINT_SEL(m, "rssi=%d\n", psta->cmn.rssi_stat.rssi);
-+				RTW_PRINT_SEL(m, "==============================\n");
-+			}
-+
-+		}
-+
-+	}
-+
-+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+	return 0;
-+}
-+
-+#endif
-+
-+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
-+int proc_get_rtkm_info(struct seq_file *m, void *v)
-+{
-+#ifdef CONFIG_USB_HCI
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct recv_priv	*precvpriv = &padapter->recvpriv;
-+	struct recv_buf *precvbuf;
-+
-+	precvbuf = (struct recv_buf *)precvpriv->precv_buf;
-+#endif /* CONFIG_USB_HCI */
-+
-+	RTW_PRINT_SEL(m, "============[RTKM Info]============\n");
-+	RTW_PRINT_SEL(m, "MAX_RTKM_NR_PREALLOC_RECV_SKB: %d\n", rtw_rtkm_get_nr_recv_skb());
-+	RTW_PRINT_SEL(m, "MAX_RTKM_RECVBUF_SZ: %d\n", rtw_rtkm_get_buff_size());
-+
-+	RTW_PRINT_SEL(m, "============[Driver Info]============\n");
-+	RTW_PRINT_SEL(m, "NR_PREALLOC_RECV_SKB: %d\n", NR_PREALLOC_RECV_SKB);
-+#ifdef CONFIG_USB_HCI
-+	RTW_PRINT_SEL(m, "MAX_RECVBUF_SZ: %d\n", precvbuf->alloc_sz);
-+#else /* !CONFIG_USB_HCI */
-+	RTW_PRINT_SEL(m, "MAX_RECVBUF_SZ: %d\n", MAX_RECVBUF_SZ);
-+#endif /* !CONFIG_USB_HCI */
-+
-+	return 0;
-+}
-+#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
-+
-+#ifdef DBG_MEMORY_LEAK
-+#include <asm/atomic.h>
-+extern atomic_t _malloc_cnt;;
-+extern atomic_t _malloc_size;;
-+
-+int proc_get_malloc_cnt(struct seq_file *m, void *v)
-+{
-+	RTW_PRINT_SEL(m, "_malloc_cnt=%d\n", atomic_read(&_malloc_cnt));
-+	RTW_PRINT_SEL(m, "_malloc_size=%d\n", atomic_read(&_malloc_size));
-+
-+	return 0;
-+}
-+#endif /* DBG_MEMORY_LEAK */
-+
-+#ifdef CONFIG_FIND_BEST_CHANNEL
-+int proc_get_best_channel(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0;
-+
-+	for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {
-+		if (rfctl->channel_set[i].ChannelNum == 1)
-+			index_24G = i;
-+		if (rfctl->channel_set[i].ChannelNum == 36)
-+			index_5G = i;
-+	}
-+
-+	for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {
-+		/* 2.4G */
-+		if (rfctl->channel_set[i].ChannelNum == 6) {
-+			if (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) {
-+				index_24G = i;
-+				best_channel_24G = rfctl->channel_set[i].ChannelNum;
-+			}
-+		}
-+
-+		/* 5G */
-+		if (rfctl->channel_set[i].ChannelNum >= 36
-+		    && rfctl->channel_set[i].ChannelNum < 140) {
-+			/* Find primary channel */
-+			if (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0)
-+			    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {
-+				index_5G = i;
-+				best_channel_5G = rfctl->channel_set[i].ChannelNum;
-+			}
-+		}
-+
-+		if (rfctl->channel_set[i].ChannelNum >= 149
-+		    && rfctl->channel_set[i].ChannelNum < 165) {
-+			/* find primary channel */
-+			if (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0)
-+			    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {
-+				index_5G = i;
-+				best_channel_5G = rfctl->channel_set[i].ChannelNum;
-+			}
-+		}
-+#if 1 /* debug */
-+		RTW_PRINT_SEL(m, "The rx cnt of channel %3d = %d\n",
-+			rfctl->channel_set[i].ChannelNum, rfctl->channel_set[i].rx_count);
-+#endif
-+	}
-+
-+	RTW_PRINT_SEL(m, "best_channel_5G = %d\n", best_channel_5G);
-+	RTW_PRINT_SEL(m, "best_channel_24G = %d\n", best_channel_24G);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int i;
-+		for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++)
-+			rfctl->channel_set[i].rx_count = 0;
-+
-+		RTW_INFO("set %s\n", "Clean Best Channel Count");
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_FIND_BEST_CHANNEL */
-+
-+#ifdef CONFIG_BT_COEXIST
-+int proc_get_btcoex_dbg(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	PADAPTER padapter;
-+	char buf[512] = {0};
-+	padapter = (PADAPTER)rtw_netdev_priv(dev);
-+
-+	rtw_btcoex_GetDBG(padapter, buf, 512);
-+
-+	_RTW_PRINT_SEL(m, "%s", buf);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_btcoex_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	PADAPTER padapter;
-+	u8 tmp[80] = {0};
-+	u32 module[2] = {0};
-+	u32 num;
-+
-+	padapter = (PADAPTER)rtw_netdev_priv(dev);
-+
-+	/*	RTW_INFO("+" FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(padapter)); */
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n",
-+			 FUNC_ADPT_ARG(padapter));
-+
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n",
-+			 FUNC_ADPT_ARG(padapter));
-+
-+		return -EFAULT;
-+	}
-+
-+	num = count;
-+	if (num > (sizeof(tmp) - 1))
-+		num = (sizeof(tmp) - 1);
-+
-+	if (copy_from_user(tmp, buffer, num)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n",
-+			 FUNC_ADPT_ARG(padapter));
-+
-+		return -EFAULT;
-+	}
-+
-+	num = sscanf(tmp, "%x %x", module, module + 1);
-+	if (1 == num) {
-+		if (0 == module[0])
-+			_rtw_memset(module, 0, sizeof(module));
-+		else
-+			_rtw_memset(module, 0xFF, sizeof(module));
-+	} else if (2 != num) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input(\"%s\") format incorrect!\n",
-+			 FUNC_ADPT_ARG(padapter), tmp);
-+
-+		if (0 == num)
-+			return -EFAULT;
-+	}
-+
-+	RTW_INFO(FUNC_ADPT_FMT ": input 0x%08X 0x%08X\n",
-+		 FUNC_ADPT_ARG(padapter), module[0], module[1]);
-+	rtw_btcoex_SetDBG(padapter, module);
-+
-+	return count;
-+}
-+
-+int proc_get_btcoex_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	PADAPTER padapter;
-+	const u32 bufsize = 40 * 100;
-+	u8 *pbuf = NULL;
-+
-+	padapter = (PADAPTER)rtw_netdev_priv(dev);
-+
-+	pbuf = rtw_zmalloc(bufsize);
-+	if (NULL == pbuf)
-+		return -ENOMEM;
-+
-+	rtw_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize);
-+
-+	_RTW_PRINT_SEL(m, "%s\n", pbuf);
-+
-+	rtw_mfree(pbuf, bufsize);
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_RF4CE_COEXIST
-+int proc_get_rf4ce_state(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 state = 0, voice = 0;
-+
-+	state = rtw_btcoex_GetRf4ceLinkState(adapter);
-+
-+	RTW_PRINT_SEL(m, "RF4CE %s\n", state?"Connected":"Disconnect");
-+
-+	return 0;
-+}
-+
-+/* This interface is designed for user space application to inform RF4CE state
-+ * Initial define for DHC 1295 E387 project
-+ *
-+ * echo state voice > rf4ce_state
-+ * state
-+ *	0: RF4CE disconnected
-+ *	1: RF4CE connected
-+ */
-+ssize_t proc_set_rf4ce_state(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 state;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhx", &state);
-+
-+		if (num >= 1)
-+			rtw_btcoex_SetRf4ceLinkState(adapter, state);
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_RF4CE_COEXIST */
-+#endif /* CONFIG_BT_COEXIST */
-+
-+#if defined(DBG_CONFIG_ERROR_DETECT)
-+int proc_get_sreset(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
-+
-+	if (psrtpriv->dbg_sreset_ctrl == _TRUE) {
-+		RTW_PRINT_SEL(m, "self_dect_tx_cnt:%llu\n", psrtpriv->self_dect_tx_cnt);
-+		RTW_PRINT_SEL(m, "self_dect_rx_cnt:%llu\n", psrtpriv->self_dect_rx_cnt);
-+		RTW_PRINT_SEL(m, "self_dect_fw_cnt:%llu\n", psrtpriv->self_dect_fw_cnt);
-+		RTW_PRINT_SEL(m, "tx_dma_status_cnt:%llu\n", psrtpriv->tx_dma_status_cnt);
-+		RTW_PRINT_SEL(m, "rx_dma_status_cnt:%llu\n", psrtpriv->rx_dma_status_cnt);
-+		RTW_PRINT_SEL(m, "self_dect_case:%d\n", psrtpriv->self_dect_case);
-+		RTW_PRINT_SEL(m, "dbg_sreset_cnt:%d\n", pdbgpriv->dbg_sreset_cnt);
-+	}
-+	return 0;
-+}
-+
-+ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
-+	char tmp[32];
-+	s32 trigger_point;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d", &trigger_point);
-+
-+		if (num < 1)
-+			return count;
-+
-+		if (trigger_point == SRESET_TGP_NULL)
-+			rtw_hal_sreset_reset(padapter);
-+		else if (trigger_point == SRESET_TGP_INFO)
-+			psrtpriv->dbg_sreset_ctrl = _TRUE;
-+		else
-+			sreset_set_trigger_point(padapter, trigger_point);
-+	}
-+
-+	return count;
-+
-+}
-+#endif /* DBG_CONFIG_ERROR_DETECT */
-+
-+#ifdef CONFIG_PCI_HCI
-+
-+ssize_t proc_set_pci_bridge_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
-+	struct pci_dev  *bridge_pdev = pdev->bus->self;
-+
-+	char tmp[32] = { 0 };
-+	int num;
-+
-+	u32 reg = 0, value = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		num = sscanf(tmp, "%x %x", &reg, &value);
-+		if (num != 2) {
-+			RTW_INFO("invalid parameter!\n");
-+			return count;
-+		}
-+
-+		if (reg >= 0x1000) {
-+			RTW_INFO("invalid register!\n");
-+			return count;
-+		}
-+
-+		if (value > 0xFF) {
-+			RTW_INFO("invalid value! Only one byte\n");
-+			return count;
-+		}
-+
-+		RTW_INFO(FUNC_ADPT_FMT ": register 0x%x value 0x%x\n",
-+			FUNC_ADPT_ARG(padapter), reg, value);
-+
-+		pci_write_config_byte(bridge_pdev, reg, value);
-+	}
-+	return count;
-+}
-+
-+
-+int proc_get_pci_bridge_conf_space(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
-+	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
-+	struct pci_dev  *bridge_pdev = pdev->bus->self;
-+
-+	u32 tmp[4] = { 0 };
-+	u32 i, j;
-+
-+	RTW_PRINT_SEL(m, "\n*****  PCI Host Device Configuration Space*****\n\n");
-+
-+	for (i = 0; i < 0x1000; i += 0x10) {
-+		for (j = 0 ; j < 4 ; j++)
-+			pci_read_config_dword(bridge_pdev, i + j * 4, tmp+j);
-+
-+		RTW_PRINT_SEL(m, "%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
-+			i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,
-+			tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,
-+			tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,
-+			tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);
-+	}
-+	return 0;
-+}
-+
-+
-+ssize_t proc_set_pci_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
-+
-+	char tmp[32] = { 0 };
-+	int num;
-+
-+	u32 reg = 0, value = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		num = sscanf(tmp, "%x %x", &reg, &value);
-+
-+		if (num != 2) {
-+			RTW_INFO("invalid parameter!\n");
-+			return count;
-+		}
-+
-+
-+		if (reg >= 0x1000) {
-+			RTW_INFO("invalid register!\n");
-+			return count;
-+		}
-+
-+		if (value > 0xFF) {
-+			RTW_INFO("invalid value! Only one byte\n");
-+			return count;
-+		}
-+
-+		RTW_INFO(FUNC_ADPT_FMT ": register 0x%x value 0x%x\n",
-+			FUNC_ADPT_ARG(padapter), reg, value);
-+
-+		pci_write_config_byte(pdev, reg, value);
-+
-+
-+	}
-+	return count;
-+}
-+
-+
-+int proc_get_pci_conf_space(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
-+	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
-+	struct pci_dev  *bridge_pdev = pdev->bus->self;
-+
-+	u32 tmp[4] = { 0 };
-+	u32 i, j;
-+
-+	RTW_PRINT_SEL(m, "\n*****  PCI Device Configuration Space *****\n\n");
-+
-+	for (i = 0; i < 0x1000; i += 0x10) {
-+		for (j = 0 ; j < 4 ; j++)
-+			pci_read_config_dword(pdev, i + j * 4, tmp+j);
-+
-+		RTW_PRINT_SEL(m, "%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
-+			i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,
-+			tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,
-+			tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,
-+			tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);
-+	}
-+
-+	return 0;
-+}
-+
-+
-+int proc_get_pci_aspm(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
-+	u8 tmp8 = 0;
-+	u16 tmp16 = 0;
-+	u32 tmp32 = 0;
-+	u8 l1_idle = 0;
-+
-+
-+	RTW_PRINT_SEL(m, "***** ASPM Capability *****\n");
-+
-+	pci_read_config_dword(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCAP, &tmp32);
-+
-+	RTW_PRINT_SEL(m, "CLK REQ:	%s\n", (tmp32&PCI_EXP_LNKCAP_CLKPM) ? "Enable" : "Disable");
-+	RTW_PRINT_SEL(m, "ASPM L0s:	%s\n", (tmp32&BIT10) ? "Enable" : "Disable");
-+	RTW_PRINT_SEL(m, "ASPM L1:	%s\n", (tmp32&BIT11) ? "Enable" : "Disable");
-+
-+	tmp8 = rtw_hal_pci_l1off_capability(padapter);
-+	RTW_PRINT_SEL(m, "ASPM L1OFF:	%s\n", tmp8 ? "Enable" : "Disable");
-+
-+	RTW_PRINT_SEL(m, "***** ASPM CTRL Reg *****\n");
-+
-+	pci_read_config_word(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCTL, &tmp16);
-+
-+	RTW_PRINT_SEL(m, "CLK REQ:	%s\n", (tmp16&PCI_EXP_LNKCTL_CLKREQ_EN) ? "Enable" : "Disable");
-+	RTW_PRINT_SEL(m, "ASPM L0s:	%s\n", (tmp16&BIT0) ? "Enable" : "Disable");
-+	RTW_PRINT_SEL(m, "ASPM L1:	%s\n", (tmp16&BIT1) ? "Enable" : "Disable");
-+
-+	tmp8 = rtw_hal_pci_l1off_nic_support(padapter);
-+	RTW_PRINT_SEL(m, "ASPM L1OFF:	%s\n", tmp8 ? "Enable" : "Disable");
-+
-+	RTW_PRINT_SEL(m, "***** ASPM Backdoor *****\n");
-+
-+	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);
-+	RTW_PRINT_SEL(m, "CLK REQ:	%s\n", (tmp8 & BIT4) ? "Enable" : "Disable");
-+
-+	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f);
-+	l1_idle = tmp8 & 0x38;
-+	RTW_PRINT_SEL(m, "ASPM L0s:	%s\n", (tmp8&BIT7) ? "Enable" : "Disable");
-+
-+	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);
-+	RTW_PRINT_SEL(m, "ASPM L1:	%s\n", (tmp8 & BIT3) ? "Enable" : "Disable");
-+
-+	tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718);
-+	RTW_PRINT_SEL(m, "ASPM L1OFF:	%s\n", (tmp8 & BIT5) ? "Enable" : "Disable");
-+
-+	RTW_PRINT_SEL(m, "********* MISC **********\n");
-+	RTW_PRINT_SEL(m, "ASPM L1 Idel Time: 0x%x\n", l1_idle>>3);
-+	RTW_PRINT_SEL(m, "*************************\n");
-+
-+#ifdef CONFIG_PCI_DYNAMIC_ASPM
-+	RTW_PRINT_SEL(m, "Dynamic ASPM mode: %d (%s)\n", pcipriv->aspm_mode,
-+		      pcipriv->aspm_mode == ASPM_MODE_PERF ? "Perf" :
-+		      pcipriv->aspm_mode == ASPM_MODE_PS ? "PS" : "Und");
-+#endif
-+
-+	return 0;
-+}
-+
-+int proc_get_rx_ring(struct seq_file *m, void *v)
-+{
-+	_irqL irqL;
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
-+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct recv_priv *precvpriv = &padapter->recvpriv;
-+	struct rtw_rx_ring *rx_ring = &precvpriv->rx_ring[RX_MPDU_QUEUE];
-+	int i, j;
-+
-+	RTW_PRINT_SEL(m, "rx ring (%p)\n", rx_ring);
-+	RTW_PRINT_SEL(m, "  dma: 0x%08x\n", (int) rx_ring->dma);
-+	RTW_PRINT_SEL(m, "  idx: %d\n", rx_ring->idx);
-+
-+	_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
-+	for (i = 0; i < precvpriv->rxringcount; i++) {
-+#ifdef CONFIG_TRX_BD_ARCH
-+		struct rx_buf_desc *entry = &rx_ring->buf_desc[i];
-+#else
-+		struct recv_stat *entry = &rx_ring->desc[i];
-+#endif
-+		struct sk_buff *skb = rx_ring->rx_buf[i];
-+
-+		RTW_PRINT_SEL(m, "  desc[%03d]: %p, rx_buf[%03d]: 0x%08x\n",
-+			i, entry, i, cpu_to_le32(*((dma_addr_t *)skb->cb)));
-+
-+		for (j = 0; j < sizeof(*entry) / 4; j++) {
-+			if ((j % 4) == 0)
-+				RTW_PRINT_SEL(m, "  0x%03x", j);
-+
-+			RTW_PRINT_SEL(m, " 0x%08x ", ((int *) entry)[j]);
-+
-+			if ((j % 4) == 3)
-+				RTW_PRINT_SEL(m, "\n");
-+		}
-+	}
-+	_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
-+
-+	return 0;
-+}
-+
-+int proc_get_tx_ring(struct seq_file *m, void *v)
-+{
-+	_irqL irqL;
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
-+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	int i, j, k;
-+
-+	_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
-+	for (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++) {
-+		struct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i];
-+
-+		RTW_PRINT_SEL(m, "tx ring[%d] (%p)\n", i, tx_ring);
-+		RTW_PRINT_SEL(m, "  dma: 0x%08x\n", (int) tx_ring->dma);
-+		RTW_PRINT_SEL(m, "  idx: %d\n", tx_ring->idx);
-+		RTW_PRINT_SEL(m, "  entries: %d\n", tx_ring->entries);
-+		/*		RTW_PRINT_SEL(m, "  queue: %d\n", tx_ring->queue); */
-+		RTW_PRINT_SEL(m, "  qlen: %d\n", tx_ring->qlen);
-+
-+		for (j = 0; j < pxmitpriv->txringcount[i]; j++) {
-+#ifdef CONFIG_TRX_BD_ARCH
-+			struct tx_buf_desc *entry = &tx_ring->buf_desc[j];
-+			RTW_PRINT_SEL(m, "  buf_desc[%03d]: %p\n", j, entry);
-+#else
-+			struct tx_desc *entry = &tx_ring->desc[j];
-+			RTW_PRINT_SEL(m, "  desc[%03d]: %p\n", j, entry);
-+#endif
-+
-+			for (k = 0; k < sizeof(*entry) / 4; k++) {
-+				if ((k % 4) == 0)
-+					RTW_PRINT_SEL(m, "  0x%03x", k);
-+
-+				RTW_PRINT_SEL(m, " 0x%08x ", ((int *) entry)[k]);
-+
-+				if ((k % 4) == 3)
-+					RTW_PRINT_SEL(m, "\n");
-+			}
-+		}
-+	}
-+	_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
-+
-+	return 0;
-+}
-+
-+#ifdef DBG_TXBD_DESC_DUMP
-+int proc_get_tx_ring_ext(struct seq_file *m, void *v)
-+{
-+	_irqL irqL;
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
-+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	struct rtw_tx_desc_backup *pbuf;
-+	int i, j, k, idx;
-+
-+	RTW_PRINT_SEL(m, "<<<< tx ring ext dump settings >>>>\n");
-+	RTW_PRINT_SEL(m, " - backup frame num: %d\n", TX_BAK_FRMAE_CNT);
-+	RTW_PRINT_SEL(m, " - backup max. desc size: %d bytes\n", TX_BAK_DESC_LEN);
-+	RTW_PRINT_SEL(m, " - backup data size: %d bytes\n\n", TX_BAK_DATA_LEN);
-+
-+	if (!pxmitpriv->dump_txbd_desc) {
-+		RTW_PRINT_SEL(m, "Dump function is disabled.\n");
-+		return 0;
-+	}
-+
-+	_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
-+	for (i = 0; i < HW_QUEUE_ENTRY; i++) {
-+		struct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i];
-+
-+		idx = rtw_get_tx_desc_backup(padapter, i, &pbuf);
-+
-+		RTW_PRINT_SEL(m, "Tx ring[%d]", i);
-+		switch (i) {
-+		case 0:
-+			RTW_PRINT_SEL(m, " (VO)\n");
-+			break;
-+		case 1:
-+			RTW_PRINT_SEL(m, " (VI)\n");
-+			break;
-+		case 2:
-+			RTW_PRINT_SEL(m, " (BE)\n");
-+			break;
-+		case 3:
-+			RTW_PRINT_SEL(m, " (BK)\n");
-+			break;
-+		case 4:
-+			RTW_PRINT_SEL(m, " (BCN)\n");
-+			break;
-+		case 5:
-+			RTW_PRINT_SEL(m, " (MGT)\n");
-+			break;
-+		case 6:
-+			RTW_PRINT_SEL(m, " (HIGH)\n");
-+			break;
-+		case 7:
-+			RTW_PRINT_SEL(m, " (TXCMD)\n");
-+			break;
-+		default:
-+			RTW_PRINT_SEL(m, " (?)\n");
-+			break;
-+		}
-+
-+		RTW_PRINT_SEL(m, "  Entries: %d\n", TX_BAK_FRMAE_CNT);
-+		RTW_PRINT_SEL(m, "  Last idx: %d\n", idx);
-+
-+		for (j = 0; j < TX_BAK_FRMAE_CNT; j++) {
-+			RTW_PRINT_SEL(m, "  desc[%03d]:\n", j);
-+
-+			for (k = 0; k < (pbuf->tx_desc_size) / 4; k++) {
-+				if ((k % 4) == 0)
-+					RTW_PRINT_SEL(m, "  0x%03x", k);
-+
-+				RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_desc)[k]);
-+
-+				if ((k % 4) == 3)
-+					RTW_PRINT_SEL(m, "\n");
-+			}
-+
-+#if 1 /* data dump */
-+			if (pbuf->tx_desc_size) {
-+				RTW_PRINT_SEL(m, "  data[%03d]:\n", j);
-+
-+				for (k = 0; k < (TX_BAK_DATA_LEN) / 4; k++) {
-+					if ((k % 4) == 0)
-+						RTW_PRINT_SEL(m, "  0x%03x", k);
-+
-+					RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_data_hdr)[k]);
-+
-+					if ((k % 4) == 3)
-+						RTW_PRINT_SEL(m, "\n");
-+				}
-+				RTW_PRINT_SEL(m, "\n");
-+			}
-+#endif
-+
-+			RTW_PRINT_SEL(m, "  R/W pointer: %d/%d\n", pbuf->tx_bak_rp, pbuf->tx_bak_wp);
-+
-+			pbuf = pbuf + 1;
-+		}
-+		RTW_PRINT_SEL(m, "\n");
-+	}
-+	_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	_irqL irqL;
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
-+	char tmp[32];
-+	u32 reset = 0;
-+	u32 dump = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%u %u", &dump, &reset);
-+
-+		if (num != 2) {
-+			RTW_INFO("invalid parameter!\n");
-+			return count;
-+		}
-+
-+		_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
-+		pxmitpriv->dump_txbd_desc = (BOOLEAN) dump;
-+
-+		if (reset == 1)
-+			rtw_tx_desc_backup_reset();
-+
-+		_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
-+
-+	}
-+
-+	return count;
-+}
-+
-+#endif
-+
-+#endif
-+
-+#ifdef CONFIG_WOWLAN
-+int proc_get_wow_enable(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv *registry_pair = &padapter->registrypriv;
-+
-+	RTW_PRINT_SEL(m, "wow - %s\n", (registry_pair->wowlan_enable)? "enable" : "disable");
-+	return 0;
-+}
-+
-+ssize_t proc_set_wow_enable(struct file *file, const char __user *buffer,
-+			    size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv *registry_pair = &padapter->registrypriv;
-+	char tmp[8];
-+	int num = 0;
-+	int mode = 0;
-+
-+	if (count < 1) 
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) 
-+		num = sscanf(tmp, "%d", &mode);
-+	else 
-+		return -EFAULT;
-+
-+	if (num != 1) {
-+		RTW_ERR("%s: %s - invalid parameter!\n", __func__, tmp);
-+		return -EINVAL;
-+	}
-+
-+	if (mode == 1) {
-+		RTW_PRINT("%s: wowlan - enable\n", __func__);
-+	} else if (mode == 0) {
-+		RTW_PRINT("%s: wowlan - disable\n", __func__);
-+	} else {
-+		RTW_ERR("%s: %s - invalid parameter!, mode=%d\n",
-+			__func__, tmp, mode);
-+		return -EINVAL;
-+	}
-+
-+	registry_pair->wowlan_enable = mode;
-+
-+	return count;
-+}
-+
-+int proc_get_pattern_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	u8 val8;
-+	char str_1[128];
-+	char *p_str;
-+	int i = 0 , j = 0, k = 0;
-+	int len = 0, max_len = 0, total = 0;
-+
-+	p_str = str_1;
-+	max_len = sizeof(str_1);
-+
-+	total = pwrpriv->wowlan_pattern_idx;
-+
-+	rtw_set_default_pattern(padapter);
-+
-+	/*show pattern*/
-+	RTW_PRINT_SEL(m, "\n======[Pattern Info.]======\n");
-+	RTW_PRINT_SEL(m, "pattern number: %d\n", total);
-+	RTW_PRINT_SEL(m, "support default patterns: %c\n",
-+		      (pwrpriv->default_patterns_en) ? 'Y' : 'N');
-+
-+	for (k = 0; k < total ; k++) {
-+		RTW_PRINT_SEL(m, "\npattern idx: %d\n", k);
-+		RTW_PRINT_SEL(m, "pattern content:\n");
-+
-+		p_str = str_1;
-+		max_len = sizeof(str_1);
-+		for (i = 0 ; i < MAX_WKFM_PATTERN_SIZE / 8 ; i++) {
-+			_rtw_memset(p_str, 0, max_len);
-+			len = 0;
-+			for (j = 0 ; j < 8 ; j++) {
-+				val8 = pwrpriv->patterns[k].content[i * 8 + j];
-+				len += snprintf(p_str + len, max_len - len,
-+						"%02x ", val8);
-+			}
-+			RTW_PRINT_SEL(m, "%s\n", p_str);
-+		}
-+		RTW_PRINT_SEL(m, "\npattern mask:\n");
-+		for (i = 0 ; i < MAX_WKFM_SIZE / 8 ; i++) {
-+			_rtw_memset(p_str, 0, max_len);
-+			len = 0;
-+			for (j = 0 ; j < 8 ; j++) {
-+				val8 = pwrpriv->patterns[k].mask[i * 8 + j];
-+				len += snprintf(p_str + len, max_len - len,
-+						"%02x ", val8);
-+			}
-+			RTW_PRINT_SEL(m, "%s\n", p_str);
-+		}
-+
-+		RTW_PRINT_SEL(m, "\npriv_pattern_len:\n");
-+		RTW_PRINT_SEL(m, "pattern_len: %d\n", pwrpriv->patterns[k].len);
-+		RTW_PRINT_SEL(m, "*****************\n");
-+	}
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer,
-+			      size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct wowlan_ioctl_param poidparam;
-+	u8 tmp[MAX_WKFM_PATTERN_STR_LEN + 1] = {0};
-+	int ret = 0;
-+	u8 index = 0;
-+
-+	poidparam.subcode = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count >= sizeof(tmp)) {
-+		RTW_ERR("%s: pattern string is too long, count=%zu\n",
-+			__func__, count);
-+		return -EFAULT;
-+	}
-+
-+	if (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_CAM_NUM) {
-+		RTW_ERR("priv-pattern is full(idx: %d)\n",
-+			 pwrpriv->wowlan_pattern_idx);
-+		RTW_ERR("please clean priv-pattern first\n");
-+		return -ENOMEM;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		if (strncmp(tmp, "clean", 5) == 0) {
-+			poidparam.subcode = WOWLAN_PATTERN_CLEAN;
-+			rtw_hal_set_hwreg(padapter,
-+					  HW_VAR_WOWLAN, (u8 *)&poidparam);
-+		} else {
-+			index = pwrpriv->wowlan_pattern_idx;
-+			ret = rtw_wowlan_parser_pattern_cmd(tmp,
-+					    pwrpriv->patterns[index].content,
-+					    &pwrpriv->patterns[index].len,
-+					    pwrpriv->patterns[index].mask);
-+			if (ret == _TRUE)
-+				pwrpriv->wowlan_pattern_idx++;
-+		}
-+	} else {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_wakeup_event(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv  *registry_par = &padapter->registrypriv;
-+
-+	RTW_PRINT_SEL(m, "wakeup event: %#02x\n", registry_par->wakeup_event);
-+	return 0;
-+}
-+
-+ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer,
-+			      size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+	struct registry_priv  *registry_par = &padapter->registrypriv;
-+	u32 wakeup_event = 0;
-+
-+	u8 tmp[8] = {0};
-+	int num = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count))
-+		num = sscanf(tmp, "%u", &wakeup_event);
-+	else
-+		return -EFAULT;
-+
-+	if (num == 1 && wakeup_event <= 0x0f) {
-+		registry_par->wakeup_event = wakeup_event;
-+
-+		if (wakeup_event & BIT(1))
-+			pwrctrlpriv->default_patterns_en = _TRUE;
-+		else
-+			pwrctrlpriv->default_patterns_en = _FALSE;
-+
-+		rtw_wow_pattern_sw_reset(padapter);
-+
-+		RTW_INFO("%s: wakeup_event: %#2x, default pattern: %d\n",
-+			 __func__, registry_par->wakeup_event,
-+			 pwrctrlpriv->default_patterns_en);
-+	} else {
-+		return -EINVAL;
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_wakeup_reason(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	u8 val = pwrpriv->wowlan_last_wake_reason;
-+
-+	RTW_PRINT_SEL(m, "last wake reason: %#02x\n", val);
-+	return 0;
-+}
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+int proc_dump_wow_keep_alive_info(struct seq_file *m, void *v) {
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	int i;
-+
-+	RTW_PRINT_SEL(m, "wowlan_keep_alive_mode: %d\n", pwrpriv->wowlan_keep_alive_mode);
-+	RTW_PRINT_SEL(m,"LocKeepAlive: %d\n", pwrpriv->keep_alive_pattern_loc );
-+	RTW_PRINT_SEL(m, "keep_alive_pattern_len: %d\n", pwrpriv->keep_alive_pattern_len);
-+	RTW_PRINT_SEL(m,"keep_alive_pattern= \n" );
-+	for (i=0 ; i < pwrpriv->keep_alive_pattern_len ; i++) {
-+		RTW_PRINT_SEL(m,"[0x%x] ",pwrpriv->keep_alive_pattern[i]);
-+		if(i%8 == 7)
-+			RTW_PRINT_SEL(m,"\n");
-+	}
-+	RTW_PRINT_SEL(m,"\n");
-+	RTW_PRINT_SEL(m," wowlan_keep_alive_period= %d ms\n", pwrpriv->wowlan_keep_alive_period*100);
-+	RTW_PRINT_SEL(m," wowlan_keep_alive_retry_counter= %d\n", pwrpriv->wowlan_keep_alive_retry_counter);
-+	RTW_PRINT_SEL(m," wowlan_keep_alive_retry_interval= %d ms\n", pwrpriv->wowlan_keep_alive_retry_interval*100);
-+	return 0;
-+}
-+#endif /* CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+
-+#endif /*CONFIG_WOWLAN*/
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+int proc_get_wowlan_gpio_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	u8 gpio_index = pwrpriv->wowlan_gpio_index;
-+	u8 gpio_output_state = pwrpriv->wowlan_gpio_output_state;
-+	u8 val = pwrpriv->is_high_active;
-+
-+	RTW_PRINT_SEL(m, "wakeup_gpio_idx: %d\n", gpio_index);
-+#if (!defined(CONFIG_WAKEUP_GPIO_INPUT_MODE) && !defined(CONFIG_RTW_ONE_PIN_GPIO))
-+	RTW_PRINT_SEL(m, "current_gpio_output_state: %d\n", gpio_output_state);
-+#endif
-+	RTW_PRINT_SEL(m, "high_active: %d\n", val);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer,
-+				  size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	char tmp[32] = {0};
-+	int num = 0;
-+	u32 is_high_active = 0;
-+	u8 val8 = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		num = sscanf(tmp, "%u", &is_high_active);
-+
-+		if (num != 1) {
-+			RTW_INFO("Invalid format\n");
-+			return count;
-+		}
-+
-+		is_high_active = is_high_active == 0 ? 0 : 1;
-+
-+		pwrpriv->is_high_active = is_high_active;
-+
-+		rtw_ps_deny(padapter, PS_DENY_IOCTL);
-+		LeaveAllPowerSaveModeDirect(padapter);
-+
-+#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
-+		if (pwrpriv->is_high_active == 0)
-+			rtw_hal_set_input_gpio(padapter, pwrpriv->wowlan_gpio_index);
-+		else
-+			rtw_hal_set_output_gpio(padapter, pwrpriv->wowlan_gpio_index,
-+				GPIO_OUTPUT_LOW);
-+#else
-+		val8 = (pwrpriv->is_high_active == 0) ? 1 : 0;
-+		rtw_hal_switch_gpio_wl_ctrl(padapter, pwrpriv->wowlan_gpio_index, _TRUE);
-+		rtw_hal_set_output_gpio(padapter, pwrpriv->wowlan_gpio_index, val8);
-+#endif
-+		rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
-+
-+		RTW_INFO("%s set GPIO_%d to %s_ACTIVE\n", __func__,
-+			pwrpriv->wowlan_gpio_index,
-+			pwrpriv->is_high_active ? "HIGH" : "LOW");
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_GPIO_WAKEUP */
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+int proc_get_p2p_wowlan_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	struct p2p_wowlan_info	 peerinfo = pwdinfo->p2p_wow_info;
-+	if (_TRUE == peerinfo.is_trigger) {
-+		RTW_PRINT_SEL(m, "is_trigger: TRUE\n");
-+		switch (peerinfo.wowlan_recv_frame_type) {
-+		case P2P_WOWLAN_RECV_NEGO_REQ:
-+			RTW_PRINT_SEL(m, "Frame Type: Nego Request\n");
-+			break;
-+		case P2P_WOWLAN_RECV_INVITE_REQ:
-+			RTW_PRINT_SEL(m, "Frame Type: Invitation Request\n");
-+			break;
-+		case P2P_WOWLAN_RECV_PROVISION_REQ:
-+			RTW_PRINT_SEL(m, "Frame Type: Provision Request\n");
-+			break;
-+		default:
-+			break;
-+		}
-+		RTW_PRINT_SEL(m, "Peer Addr: "MAC_FMT"\n", MAC_ARG(peerinfo.wowlan_peer_addr));
-+		RTW_PRINT_SEL(m, "Peer WPS Config: %x\n", peerinfo.wowlan_peer_wpsconfig);
-+		RTW_PRINT_SEL(m, "Persistent Group: %d\n", peerinfo.wowlan_peer_is_persistent);
-+		RTW_PRINT_SEL(m, "Intivation Type: %d\n", peerinfo.wowlan_peer_invitation_type);
-+	} else
-+		RTW_PRINT_SEL(m, "is_trigger: False\n");
-+	return 0;
-+}
-+#endif /* CONFIG_P2P_WOWLAN */
-+#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
-+int proc_get_new_bcn_max(struct seq_file *m, void *v)
-+{
-+	extern int new_bcn_max;
-+
-+	RTW_PRINT_SEL(m, "%d", new_bcn_max);
-+	return 0;
-+}
-+
-+ssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	char tmp[32];
-+	extern int new_bcn_max;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count))
-+		sscanf(tmp, "%d ", &new_bcn_max);
-+
-+	return count;
-+}
-+#endif
-+#ifdef CONFIG_POWER_SAVING
-+int proc_get_ps_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	u8 ips_mode = pwrpriv->ips_mode_req;
-+	u8 lps_mode = pwrpriv->power_mgnt;
-+	u8 lps_level = pwrpriv->lps_level;
-+#ifdef CONFIG_LPS_1T1R
-+	u8 lps_1t1r = pwrpriv->lps_1t1r;
-+#endif
-+#ifdef CONFIG_WOWLAN
-+	u8 wow_lps_mode = pwrpriv->wowlan_power_mgmt;
-+	u8 wow_lps_level = pwrpriv->wowlan_lps_level;
-+	#ifdef CONFIG_LPS_1T1R
-+	u8 wow_lps_1t1r = pwrpriv->wowlan_lps_1t1r;
-+	#endif
-+#endif /* CONFIG_WOWLAN */
-+	char *str = "";
-+
-+	RTW_PRINT_SEL(m, "======Power Saving Info:======\n");
-+	RTW_PRINT_SEL(m, "*IPS:\n");
-+
-+	if (ips_mode == IPS_NORMAL) {
-+#ifdef CONFIG_FWLPS_IN_IPS
-+		str = "FW_LPS_IN_IPS";
-+#else
-+		str = "Card Disable";
-+#endif
-+	} else if (ips_mode == IPS_NONE)
-+		str = "NO IPS";
-+	else if (ips_mode == IPS_LEVEL_2)
-+		str = "IPS_LEVEL_2";
-+	else
-+		str = "invalid ips_mode";
-+
-+	RTW_PRINT_SEL(m, " IPS mode: %s\n", str);
-+	RTW_PRINT_SEL(m, " IPS enter count:%d, IPS leave count:%d\n",
-+		      pwrpriv->ips_enter_cnts, pwrpriv->ips_leave_cnts);
-+	RTW_PRINT_SEL(m, "------------------------------\n");
-+	RTW_PRINT_SEL(m, "*LPS:\n");
-+
-+	if (lps_mode == PS_MODE_ACTIVE)
-+		str = "NO LPS";
-+	else if (lps_mode == PS_MODE_MIN)
-+		str = "MIN";
-+	else if (lps_mode == PS_MODE_MAX)
-+		str = "MAX";
-+	else if (lps_mode == PS_MODE_DTIM)
-+		str = "DTIM";
-+	else
-+		sprintf(str, "%d", lps_mode);
-+
-+	RTW_PRINT_SEL(m, " LPS mode: %s\n", str);
-+
-+	if (pwrpriv->dtim != 0)
-+		RTW_PRINT_SEL(m, " DTIM: %d\n", pwrpriv->dtim);
-+	RTW_PRINT_SEL(m, " LPS enter count:%d, LPS leave count:%d\n",
-+		      pwrpriv->lps_enter_cnts, pwrpriv->lps_leave_cnts);
-+
-+	if (lps_level == LPS_LCLK)
-+		str = "LPS_LCLK";
-+	else if  (lps_level == LPS_PG)
-+		str = "LPS_PG";
-+	else
-+		str = "LPS_NORMAL";
-+	RTW_PRINT_SEL(m, " LPS level: %s\n", str);
-+
-+#ifdef CONFIG_LPS_1T1R
-+	RTW_PRINT_SEL(m, " LPS 1T1R: %d\n", lps_1t1r);
-+#endif
-+
-+#ifdef CONFIG_WOWLAN
-+	RTW_PRINT_SEL(m, "------------------------------\n");
-+	RTW_PRINT_SEL(m, "*WOW LPS:\n");
-+
-+	if (wow_lps_mode == PS_MODE_ACTIVE)
-+		str = "NO LPS";
-+	else if (wow_lps_mode == PS_MODE_MIN)
-+		str = "MIN";
-+	else if (wow_lps_mode == PS_MODE_MAX)
-+		str = "MAX";
-+	else if (wow_lps_mode == PS_MODE_DTIM)
-+		str = "DTIM";
-+	else
-+		sprintf(str, "%d", wow_lps_mode);
-+
-+	RTW_PRINT_SEL(m, " WOW LPS mode: %s\n", str);
-+
-+	if (wow_lps_level == LPS_LCLK)
-+		str = "LPS_LCLK";
-+	else if  (wow_lps_level == LPS_PG)
-+		str = "LPS_PG";
-+	else
-+		str = "LPS_NORMAL";
-+	RTW_PRINT_SEL(m, " WOW LPS level: %s\n", str);
-+
-+	#ifdef CONFIG_LPS_1T1R
-+	RTW_PRINT_SEL(m, " WOW LPS 1T1R: %d\n", wow_lps_1t1r);
-+	#endif
-+#endif /* CONFIG_WOWLAN */
-+
-+	RTW_PRINT_SEL(m, "=============================\n");
-+	return 0;
-+}
-+
-+ssize_t proc_set_ps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	struct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[8];
-+	int num = 0;
-+	int mode = 0;
-+	int en = 0;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (!buffer || copy_from_user(tmp, buffer, count))
-+		goto exit;
-+
-+	num = sscanf(tmp, "%d %d", &mode, &en);
-+	if (num >  2) {
-+		RTW_ERR("%s: invalid parameter!\n", __FUNCTION__);
-+		goto exit;
-+	}
-+
-+	if (num == 1 && mode == 0) {
-+		/* back to original LPS/IPS Mode */
-+		RTW_INFO("%s: back to original LPS/IPS Mode\n", __FUNCTION__);
-+
-+		rtw_pm_set_lps(adapter, adapter->registrypriv.power_mgnt);
-+		
-+		rtw_pm_set_ips(adapter, adapter->registrypriv.ips_mode);
-+
-+#ifdef CONFIG_WOWLAN
-+		RTW_INFO("%s: back to original WOW LPS Mode\n", __FUNCTION__);
-+
-+		rtw_pm_set_wow_lps(adapter, adapter->registrypriv.wow_power_mgnt);
-+#endif /* CONFIG_WOWLAN */
-+
-+		goto exit;
-+	}
-+	
-+	if (mode == 1) { 
-+		/* LPS */
-+		RTW_INFO("%s: LPS: %s, en=%d\n", __FUNCTION__, (en == 0) ? "disable":"enable", en);	
-+		if (rtw_pm_set_lps(adapter, en) != 0 )
-+			RTW_ERR("%s: invalid parameter, mode=%d, level=%d\n", __FUNCTION__, mode, en);
-+		
-+	} else if (mode == 2) {
-+		/* IPS */
-+		RTW_INFO("%s: IPS: %s, en=%d\n", __FUNCTION__, (en == 0) ? "disable":"enable", en);	
-+		if (rtw_pm_set_ips(adapter, en) != 0 )
-+			RTW_ERR("%s: invalid parameter, mode=%d, level=%d\n", __FUNCTION__, mode, en);
-+	}
-+#ifdef CONFIG_WOWLAN
-+	else if (mode == 3) {
-+		/* WOW LPS */
-+		RTW_INFO("%s: WOW LPS: %s, en=%d\n", __FUNCTION__, (en == 0) ? "disable":"enable", en);
-+		if (rtw_pm_set_wow_lps(adapter, en) != 0 )
-+			RTW_ERR("%s: invalid parameter, mode=%d, level=%d\n", __FUNCTION__, mode, en);
-+	}
-+#endif /* CONFIG_WOWLAN */
-+	else
-+		RTW_ERR("%s: invalid parameter, mode = %d!\n", __FUNCTION__, mode);
-+
-+exit:
-+	return count;
-+}
-+
-+#ifdef CONFIG_WMMPS_STA
-+int proc_get_wmmps_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	char *uapsd_max_sp_str="";
-+
-+	if (pregpriv){
-+		switch(pregpriv->uapsd_max_sp_len) {
-+			case 0:
-+				uapsd_max_sp_str = "NO_LIMIT";
-+				break;
-+			case 1:
-+				uapsd_max_sp_str = "TWO_MSDU";
-+				break;
-+			case 2:
-+				uapsd_max_sp_str = "FOUR_MSDU";
-+				break;
-+			case 3:
-+				uapsd_max_sp_str = "SIX_MSDU";
-+				break;
-+			default:
-+				uapsd_max_sp_str = "UNSPECIFIED";
-+				break;
-+		}
-+
-+		RTW_PRINT_SEL(m, "====== WMMPS_STA Info:======\n");
-+		RTW_PRINT_SEL(m, "uapsd_max_sp_len=0x%02x (%s)\n", pregpriv->uapsd_max_sp_len, uapsd_max_sp_str);
-+		RTW_PRINT_SEL(m, "uapsd_ac_enable=0x%02x\n", pregpriv->uapsd_ac_enable);
-+		RTW_PRINT_SEL(m, "BIT0 - AC_VO UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VO) ? "Enabled" : "Disabled");
-+		RTW_PRINT_SEL(m, "BIT1 - AC_VI UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VI) ? "Enabled" : "Disabled");
-+		RTW_PRINT_SEL(m, "BIT2 - AC_BK UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BK) ? "Enabled" : "Disabled");
-+		RTW_PRINT_SEL(m, "BIT3 - AC_BE UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BE) ? "Enabled" : "Disabled");
-+		RTW_PRINT_SEL(m, "============================\n");
-+	}
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	char tmp[32];
-+	u8 uapsd_ac_setting;
-+	u8 uapsd_max_sp_len_setting;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu %hhx", &uapsd_max_sp_len_setting, &uapsd_ac_setting);
-+
-+		if (pregpriv) {
-+			if (num >= 1) {
-+				pregpriv->uapsd_max_sp_len = uapsd_max_sp_len_setting;
-+				RTW_INFO("uapsd_max_sp_len = %d\n", pregpriv->uapsd_max_sp_len);
-+			}
-+
-+			if (num >= 2) {
-+				pregpriv->uapsd_ac_enable = uapsd_ac_setting;
-+				RTW_INFO("uapsd_ac_enable = 0x%02x\n", pregpriv->uapsd_ac_enable);
-+			}
-+		}
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_WMMPS_STA */
-+#endif /* CONFIG_POWER_SAVING */
-+
-+#ifdef CONFIG_TDLS
-+int proc_get_tdls_enable(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv *pregpriv = &padapter->registrypriv;
-+
-+	if (pregpriv)
-+		RTW_PRINT_SEL(m, "TDLS is %s !\n", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "enabled" : "disabled");
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	char tmp[32];
-+	u32 en_tdls = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &en_tdls);
-+
-+		if (num == 1 && pregpriv) {
-+			if (en_tdls > 0)
-+				rtw_enable_tdls_func(padapter);
-+			else
-+				rtw_disable_tdls_func(padapter, _TRUE);
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+static int proc_tdls_display_tdls_function_info(struct seq_file *m)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE;
-+	u8 SpaceBtwnItemAndValueTmp = 0;
-+	BOOLEAN FirstMatchFound = _FALSE;
-+	int j = 0;
-+
-+	RTW_PRINT_SEL(m, "============[TDLS Function Info]============\n");
-+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Enable", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "_TRUE" : "_FALSE");
-+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Driver Setup", (ptdlsinfo->driver_setup == _TRUE) ? "_TRUE" : "_FALSE");
-+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Prohibited", (ptdlsinfo->ap_prohibited == _TRUE) ? "_TRUE" : "_FALSE");
-+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Channel Switch Prohibited", (ptdlsinfo->ch_switch_prohibited == _TRUE) ? "_TRUE" : "_FALSE");
-+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Link Established", (ptdlsinfo->link_established == _TRUE) ? "_TRUE" : "_FALSE");
-+	RTW_PRINT_SEL(m, "%-*s = %d/%d\n", SpaceBtwnItemAndValue, "TDLS STA Num (Linked/Allowed)", ptdlsinfo->sta_cnt, MAX_ALLOWED_TDLS_STA_NUM);
-+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Allowed STA Num Reached", (ptdlsinfo->sta_maximum == _TRUE) ? "_TRUE" : "_FALSE");
-+
-+#ifdef CONFIG_TDLS_CH_SW
-+	RTW_PRINT_SEL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS CH SW State");
-+	if (ptdlsinfo->chsw_info.ch_sw_state == TDLS_STATE_NONE)
-+		RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_STATE_NONE");
-+	else {
-+		for (j = 0; j < 32; j++) {
-+			if (ptdlsinfo->chsw_info.ch_sw_state & BIT(j)) {
-+				if (FirstMatchFound ==  _FALSE) {
-+					SpaceBtwnItemAndValueTmp = 1;
-+					FirstMatchFound = _TRUE;
-+				} else
-+					SpaceBtwnItemAndValueTmp = SpaceBtwnItemAndValue + 3;
-+				switch (BIT(j)) {
-+				case TDLS_INITIATOR_STATE:
-+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_INITIATOR_STATE");
-+					break;
-+				case TDLS_RESPONDER_STATE:
-+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_RESPONDER_STATE");
-+					break;
-+				case TDLS_LINKED_STATE:
-+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_LINKED_STATE");
-+					break;
-+				case TDLS_WAIT_PTR_STATE:
-+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_WAIT_PTR_STATE");
-+					break;
-+				case TDLS_ALIVE_STATE:
-+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_ALIVE_STATE");
-+					break;
-+				case TDLS_CH_SWITCH_ON_STATE:
-+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SWITCH_ON_STATE");
-+					break;
-+				case TDLS_PEER_AT_OFF_STATE:
-+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_PEER_AT_OFF_STATE");
-+					break;
-+				case TDLS_CH_SW_INITIATOR_STATE:
-+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SW_INITIATOR_STATE");
-+					break;
-+				case TDLS_WAIT_CH_RSP_STATE:
-+					RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValue, " ", "TDLS_WAIT_CH_RSP_STATE");
-+					break;
-+				default:
-+					RTW_PRINT_SEL(m, "%-*sBIT(%d)\n", SpaceBtwnItemAndValueTmp, " ", j);
-+					break;
-+				}
-+			}
-+		}
-+	}
-+
-+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS CH SW On", (ATOMIC_READ(&ptdlsinfo->chsw_info.chsw_on) == _TRUE) ? "_TRUE" : "_FALSE");
-+	RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Off-Channel Num", ptdlsinfo->chsw_info.off_ch_num);
-+	RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Channel Offset", ptdlsinfo->chsw_info.ch_offset);
-+	RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Current Time", ptdlsinfo->chsw_info.cur_time);
-+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS CH SW Delay Switch Back", (ptdlsinfo->chsw_info.delay_switch_back == _TRUE) ? "_TRUE" : "_FALSE");
-+	RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Dump Back", ptdlsinfo->chsw_info.dump_stack);
-+#endif
-+
-+	RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Device Discovered", (ptdlsinfo->dev_discovered == _TRUE) ? "_TRUE" : "_FALSE");
-+
-+	return 0;
-+}
-+
-+static int proc_tdls_display_network_info(struct seq_file *m)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
-+	int i = 0;
-+	u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE;
-+
-+	/* Display the linked AP/GO info */
-+	RTW_PRINT_SEL(m, "============[Associated AP/GO Info]============\n");
-+
-+	if ((pmlmepriv->fw_state & WIFI_STATION_STATE) && (pmlmepriv->fw_state & WIFI_ASOC_STATE)) {
-+		RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "BSSID", cur_network->network.Ssid.Ssid);
-+		RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(cur_network->network.MacAddress));
-+
-+		RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Wireless Mode");
-+		for (i = 0; i < 8; i++) {
-+			if (pmlmeext->cur_wireless_mode & BIT(i)) {
-+				switch (BIT(i)) {
-+				case WIRELESS_11B:
-+					RTW_PRINT_SEL(m, "%4s", "11B ");
-+					break;
-+				case WIRELESS_11G:
-+					RTW_PRINT_SEL(m, "%4s", "11G ");
-+					break;
-+				case WIRELESS_11A:
-+					RTW_PRINT_SEL(m, "%4s", "11A ");
-+					break;
-+				case WIRELESS_11_24N:
-+					RTW_PRINT_SEL(m, "%7s", "11_24N ");
-+					break;
-+				case WIRELESS_11_5N:
-+					RTW_PRINT_SEL(m, "%6s", "11_5N ");
-+					break;
-+				case WIRELESS_AUTO:
-+					RTW_PRINT_SEL(m, "%5s", "AUTO ");
-+					break;
-+				case WIRELESS_11AC:
-+					RTW_PRINT_SEL(m, "%5s", "11AC ");
-+					break;
-+				}
-+			}
-+		}
-+		RTW_PRINT_SEL(m, "\n");
-+
-+		RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy");
-+		switch (padapter->securitypriv.dot11PrivacyAlgrthm) {
-+		case _NO_PRIVACY_:
-+			RTW_PRINT_SEL(m, "%s\n", "NO PRIVACY");
-+			break;
-+		case _WEP40_:
-+			RTW_PRINT_SEL(m, "%s\n", "WEP 40");
-+			break;
-+		case _TKIP_:
-+			RTW_PRINT_SEL(m, "%s\n", "TKIP");
-+			break;
-+		case _TKIP_WTMIC_:
-+			RTW_PRINT_SEL(m, "%s\n", "TKIP WTMIC");
-+			break;
-+		case _AES_:
-+			RTW_PRINT_SEL(m, "%s\n", "AES");
-+			break;
-+		case _WEP104_:
-+			RTW_PRINT_SEL(m, "%s\n", "WEP 104");
-+			break;
-+#if 0 /* no this setting */
-+		case _WEP_WPA_MIXED_:
-+			RTW_PRINT_SEL(m, "%s\n", "WEP/WPA Mixed");
-+			break;
-+#endif
-+		case _SMS4_:
-+			RTW_PRINT_SEL(m, "%s\n", "SMS4");
-+			break;
-+#ifdef CONFIG_IEEE80211W
-+		case _BIP_CMAC_128_:
-+			RTW_PRINT_SEL(m, "%s\n", "BIP");
-+			break;
-+#endif /* CONFIG_IEEE80211W */
-+		}
-+
-+		RTW_PRINT_SEL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "Channel", pmlmeext->cur_channel);
-+		RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Channel Offset");
-+		switch (pmlmeext->cur_ch_offset) {
-+		case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
-+			RTW_PRINT_SEL(m, "%s\n", "N/A");
-+			break;
-+		case HAL_PRIME_CHNL_OFFSET_LOWER:
-+			RTW_PRINT_SEL(m, "%s\n", "Lower");
-+			break;
-+		case HAL_PRIME_CHNL_OFFSET_UPPER:
-+			RTW_PRINT_SEL(m, "%s\n", "Upper");
-+			break;
-+		}
-+
-+		RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode");
-+		switch (pmlmeext->cur_bwmode) {
-+		case CHANNEL_WIDTH_20:
-+			RTW_PRINT_SEL(m, "%s\n", "20MHz");
-+			break;
-+		case CHANNEL_WIDTH_40:
-+			RTW_PRINT_SEL(m, "%s\n", "40MHz");
-+			break;
-+		case CHANNEL_WIDTH_80:
-+			RTW_PRINT_SEL(m, "%s\n", "80MHz");
-+			break;
-+		case CHANNEL_WIDTH_160:
-+			RTW_PRINT_SEL(m, "%s\n", "160MHz");
-+			break;
-+		case CHANNEL_WIDTH_80_80:
-+			RTW_PRINT_SEL(m, "%s\n", "80MHz + 80MHz");
-+			break;
-+		}
-+	} else
-+		RTW_PRINT_SEL(m, "No association with AP/GO exists!\n");
-+
-+	return 0;
-+}
-+
-+static int proc_tdls_display_tdls_sta_info(struct seq_file *m)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	struct sta_info *psta;
-+	int i = 0, j = 0;
-+	_irqL irqL;
-+	_list	*plist, *phead;
-+	u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE;
-+	u8 SpaceBtwnItemAndValueTmp = 0;
-+	u8 NumOfTdlsStaToShow = 0;
-+	BOOLEAN FirstMatchFound = _FALSE;
-+
-+	/* Search for TDLS sta info to display */
-+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+	for (i = 0; i < NUM_STA; i++) {
-+		phead = &(pstapriv->sta_hash[i]);
-+		plist = get_next(phead);
-+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+			plist = get_next(plist);
-+			if (psta->tdls_sta_state != TDLS_STATE_NONE) {
-+				/* We got one TDLS sta info to show */
-+				RTW_PRINT_SEL(m, "============[TDLS Peer STA Info: STA %d]============\n", ++NumOfTdlsStaToShow);
-+				RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(psta->cmn.mac_addr));
-+				RTW_PRINT_SEL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS STA State");
-+				SpaceBtwnItemAndValueTmp = 0;
-+				FirstMatchFound = _FALSE;
-+				for (j = 0; j < 32; j++) {
-+					if (psta->tdls_sta_state & BIT(j)) {
-+						if (FirstMatchFound ==  _FALSE) {
-+							SpaceBtwnItemAndValueTmp = 1;
-+							FirstMatchFound = _TRUE;
-+						} else
-+							SpaceBtwnItemAndValueTmp = SpaceBtwnItemAndValue + 3;
-+						switch (BIT(j)) {
-+						case TDLS_INITIATOR_STATE:
-+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_INITIATOR_STATE");
-+							break;
-+						case TDLS_RESPONDER_STATE:
-+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_RESPONDER_STATE");
-+							break;
-+						case TDLS_LINKED_STATE:
-+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_LINKED_STATE");
-+							break;
-+						case TDLS_WAIT_PTR_STATE:
-+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_WAIT_PTR_STATE");
-+							break;
-+						case TDLS_ALIVE_STATE:
-+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_ALIVE_STATE");
-+							break;
-+						case TDLS_CH_SWITCH_ON_STATE:
-+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SWITCH_ON_STATE");
-+							break;
-+						case TDLS_PEER_AT_OFF_STATE:
-+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_PEER_AT_OFF_STATE");
-+							break;
-+						case TDLS_CH_SW_INITIATOR_STATE:
-+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SW_INITIATOR_STATE");
-+							break;
-+						case TDLS_WAIT_CH_RSP_STATE:
-+							RTW_PRINT_SEL(m, "%-*s%s\n", SpaceBtwnItemAndValue, " ", "TDLS_WAIT_CH_RSP_STATE");
-+							break;
-+						default:
-+							RTW_PRINT_SEL(m, "%-*sBIT(%d)\n", SpaceBtwnItemAndValueTmp, " ", j);
-+							break;
-+						}
-+					}
-+				}
-+
-+				RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Wireless Mode");
-+				for (j = 0; j < 8; j++) {
-+					if (psta->wireless_mode & BIT(j)) {
-+						switch (BIT(j)) {
-+						case WIRELESS_11B:
-+							RTW_PRINT_SEL(m, "%4s", "11B ");
-+							break;
-+						case WIRELESS_11G:
-+							RTW_PRINT_SEL(m, "%4s", "11G ");
-+							break;
-+						case WIRELESS_11A:
-+							RTW_PRINT_SEL(m, "%4s", "11A ");
-+							break;
-+						case WIRELESS_11_24N:
-+							RTW_PRINT_SEL(m, "%7s", "11_24N ");
-+							break;
-+						case WIRELESS_11_5N:
-+							RTW_PRINT_SEL(m, "%6s", "11_5N ");
-+							break;
-+						case WIRELESS_AUTO:
-+							RTW_PRINT_SEL(m, "%5s", "AUTO ");
-+							break;
-+						case WIRELESS_11AC:
-+							RTW_PRINT_SEL(m, "%5s", "11AC ");
-+							break;
-+						}
-+					}
-+				}
-+				RTW_PRINT_SEL(m, "\n");
-+
-+				RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode");
-+				switch (psta->cmn.bw_mode) {
-+				case CHANNEL_WIDTH_20:
-+					RTW_PRINT_SEL(m, "%s\n", "20MHz");
-+					break;
-+				case CHANNEL_WIDTH_40:
-+					RTW_PRINT_SEL(m, "%s\n", "40MHz");
-+					break;
-+				case CHANNEL_WIDTH_80:
-+					RTW_PRINT_SEL(m, "%s\n", "80MHz");
-+					break;
-+				case CHANNEL_WIDTH_160:
-+					RTW_PRINT_SEL(m, "%s\n", "160MHz");
-+					break;
-+				case CHANNEL_WIDTH_80_80:
-+					RTW_PRINT_SEL(m, "%s\n", "80MHz + 80MHz");
-+					break;
-+				case CHANNEL_WIDTH_5:
-+					RTW_PRINT_SEL(m, "%s\n", "5MHz");
-+					break;
-+				case CHANNEL_WIDTH_10:
-+					RTW_PRINT_SEL(m, "%s\n", "10MHz");
-+					break;
-+				default:
-+					RTW_PRINT_SEL(m, "(%d)%s\n", psta->cmn.bw_mode, "invalid");
-+					break;
-+				}
-+
-+				RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy");
-+				switch (psta->dot118021XPrivacy) {
-+				case _NO_PRIVACY_:
-+					RTW_PRINT_SEL(m, "%s\n", "NO PRIVACY");
-+					break;
-+				case _WEP40_:
-+					RTW_PRINT_SEL(m, "%s\n", "WEP 40");
-+					break;
-+				case _TKIP_:
-+					RTW_PRINT_SEL(m, "%s\n", "TKIP");
-+					break;
-+				case _TKIP_WTMIC_:
-+					RTW_PRINT_SEL(m, "%s\n", "TKIP WTMIC");
-+					break;
-+				case _AES_:
-+					RTW_PRINT_SEL(m, "%s\n", "AES");
-+					break;
-+				case _WEP104_:
-+					RTW_PRINT_SEL(m, "%s\n", "WEP 104");
-+					break;
-+#if 0 /* no this setting */
-+				case _WEP_WPA_MIXED_:
-+					RTW_PRINT_SEL(m, "%s\n", "WEP/WPA Mixed");
-+					break;
-+#endif
-+				case _SMS4_:
-+					RTW_PRINT_SEL(m, "%s\n", "SMS4");
-+					break;
-+#ifdef CONFIG_IEEE80211W
-+				case _BIP_CMAC_128_:
-+					RTW_PRINT_SEL(m, "%s\n", "BIP");
-+					break;
-+#endif /* CONFIG_IEEE80211W */
-+				}
-+
-+				RTW_PRINT_SEL(m, "%-*s = %d sec/%d sec\n", SpaceBtwnItemAndValue, "TPK Lifetime (Current/Expire)", psta->TPK_count, psta->TDLS_PeerKey_Lifetime);
-+				RTW_PRINT_SEL(m, "%-*s = %llu\n", SpaceBtwnItemAndValue, "Tx Packets Over Direct Link", psta->sta_stats.tx_pkts);
-+				RTW_PRINT_SEL(m, "%-*s = %llu\n", SpaceBtwnItemAndValue, "Rx Packets Over Direct Link", psta->sta_stats.rx_data_pkts);
-+			}
-+		}
-+	}
-+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+	if (NumOfTdlsStaToShow == 0) {
-+		RTW_PRINT_SEL(m, "============[TDLS Peer STA Info]============\n");
-+		RTW_PRINT_SEL(m, "No TDLS direct link exists!\n");
-+	}
-+
-+	return 0;
-+}
-+
-+int proc_get_tdls_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	struct sta_info *psta;
-+	int i = 0, j = 0;
-+	_irqL irqL;
-+	_list	*plist, *phead;
-+	u8 SpaceBtwnItemAndValue = 41;
-+	u8 SpaceBtwnItemAndValueTmp = 0;
-+	u8 NumOfTdlsStaToShow = 0;
-+	BOOLEAN FirstMatchFound = _FALSE;
-+
-+	if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {
-+		RTW_PRINT_SEL(m, "No tdls info can be shown since hal doesn't support tdls\n");
-+		return 0;
-+	}
-+
-+	proc_tdls_display_tdls_function_info(m);
-+	proc_tdls_display_network_info(m);
-+	proc_tdls_display_tdls_sta_info(m);
-+
-+	return 0;
-+}
-+#endif
-+
-+int proc_get_monitor(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	if (MLME_IS_MONITOR(padapter)) {
-+		RTW_PRINT_SEL(m, "Monitor mode : Enable\n");
-+		RTW_PRINT_SEL(m, "Device type  : %u\n", dev->type);
-+
-+		RTW_PRINT_SEL(m, "ch=%d, ch_offset=%d, bw=%d\n",
-+			rtw_get_oper_ch(padapter),
-+			rtw_get_oper_choffset(padapter),
-+			rtw_get_oper_bw(padapter));
-+	} else
-+		RTW_PRINT_SEL(m, "Monitor mode : Disable\n");
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	char tmp[32];
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u16 target_type;
-+	u8 target_ch, target_offset, target_bw;
-+
-+	if (count < 3) {
-+		RTW_INFO("argument size is less than 3\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = 0;
-+
-+		num = sscanf(tmp, "type %hu", &target_type);
-+		if ((num == 1) &&
-+			((target_type != ARPHRD_IEEE80211) &&
-+			(target_type != ARPHRD_IEEE80211_RADIOTAP))) {
-+			dev->type = ARPHRD_IEEE80211_RADIOTAP;
-+			return count;
-+		}
-+
-+		num = sscanf(tmp, "%hhu %hhu %hhu", &target_ch, &target_offset, &target_bw);
-+		if (num != 3) {
-+			RTW_INFO("invalid write_reg parameter!\n");
-+			return count;
-+		}
-+
-+		padapter->mlmeextpriv.cur_channel = target_ch;
-+		set_channel_bwmode(padapter, target_ch, target_offset, target_bw);
-+	}
-+
-+	return count;
-+}
-+
-+#ifdef RTW_SIMPLE_CONFIG
-+/* For RtwSimleConfig */
-+int proc_get_simple_config(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m, "RTW Simple Config : %s\n", padapter->rtw_simple_config ? "Enable" : "Disable");
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_simple_config(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	char tmp[32];
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 ret;
-+
-+	if (count < 1) {
-+		RTW_INFO("argument size is less than 1\n");
-+		return -EFAULT;
-+	}
-+	
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%hhd", &ret);
-+
-+		padapter->rtw_simple_config = ret ? _TRUE : _FALSE;
-+	}
-+
-+	return count;
-+}
-+#endif
-+
-+#ifdef DBG_XMIT_BLOCK
-+int proc_get_xmit_block(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_xmit_block(m, padapter);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_xmit_block(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 xb_mode, xb_reason;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhx %hhx", &xb_mode, &xb_reason);
-+
-+		if (num != 2) {
-+			RTW_INFO("invalid parameter!\n");
-+			return count;
-+		}
-+
-+		if (xb_mode == 0)/*set*/
-+			rtw_set_xmit_block(padapter, xb_reason);
-+		else if (xb_mode == 1)/*clear*/
-+			rtw_clr_xmit_block(padapter, xb_reason);
-+		else
-+			RTW_INFO("invalid parameter!\n");
-+	}
-+
-+	return count;
-+}
-+#endif
-+
-+#include <hal_data.h>
-+int proc_get_efuse_map(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+	struct pwrctrl_priv *pwrctrlpriv  = adapter_to_pwrctl(padapter);
-+	PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
-+	int i, j;
-+	u8 ips_mode = IPS_NUM;
-+	u16 mapLen;
-+
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
-+	if (mapLen > EFUSE_MAX_MAP_LEN)
-+		mapLen = EFUSE_MAX_MAP_LEN;
-+
-+	ips_mode = pwrctrlpriv->ips_mode;
-+	rtw_pm_set_ips(padapter, IPS_NONE);
-+#ifdef CONFIG_EFUSE_CONFIG_FILE
-+	if (pHalData->efuse_file_status == EFUSE_FILE_LOADED) {
-+		RTW_PRINT_SEL(m, "File eFuse Map loaded! file path:%s\nDriver eFuse Map From File\n", EFUSE_MAP_PATH);
-+		if (pHalData->bautoload_fail_flag)
-+			RTW_PRINT_SEL(m, "File Autoload fail!!!\n");
-+	} else if (pHalData->efuse_file_status ==  EFUSE_FILE_FAILED) {
-+		RTW_PRINT_SEL(m, "Open File eFuse Map Fail ! file path:%s\nDriver eFuse Map From Default\n", EFUSE_MAP_PATH);
-+		if (pHalData->bautoload_fail_flag)
-+			RTW_PRINT_SEL(m, "HW Autoload fail!!!\n");
-+	} else
-+#endif
-+
-+	{
-+		RTW_PRINT_SEL(m, "Driver eFuse Map From HW\n");
-+		if (pHalData->bautoload_fail_flag)
-+			RTW_PRINT_SEL(m, "HW Autoload fail!!!\n");
-+	}
-+	for (i = 0; i < mapLen; i += 16) {
-+		RTW_PRINT_SEL(m, "0x%02x\t", i);
-+		for (j = 0; j < 8; j++)
-+			RTW_PRINT_SEL(m, "%02X ", pHalData->efuse_eeprom_data[i + j]);
-+		RTW_PRINT_SEL(m, "\t");
-+		for (; j < 16; j++)
-+			RTW_PRINT_SEL(m, "%02X ", pHalData->efuse_eeprom_data[i + j]);
-+		RTW_PRINT_SEL(m, "\n");
-+	}
-+
-+	if (rtw_efuse_map_read(padapter, 0, mapLen, pEfuseHal->fakeEfuseInitMap) == _FAIL) {
-+		RTW_PRINT_SEL(m, "WARN - Read Realmap Failed\n");
-+		return 0;
-+	}
-+
-+	RTW_PRINT_SEL(m, "\n");
-+	RTW_PRINT_SEL(m, "HW eFuse Map\n");
-+	for (i = 0; i < mapLen; i += 16) {
-+		RTW_PRINT_SEL(m, "0x%02x\t", i);
-+		for (j = 0; j < 8; j++)
-+			RTW_PRINT_SEL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i + j]);
-+		RTW_PRINT_SEL(m, "\t");
-+		for (; j < 16; j++)
-+			RTW_PRINT_SEL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i + j]);
-+		RTW_PRINT_SEL(m, "\n");
-+	}
-+
-+	rtw_pm_set_ips(padapter, ips_mode);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+#if 0
-+	char tmp[256] = {0};
-+	u32 addr, cnts;
-+	u8 efuse_data;
-+
-+	int jj, kk;
-+
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrctrlpriv  = adapter_to_pwrctl(padapter);
-+	u8 ips_mode = IPS_NUM;
-+
-+	if (count < 3) {
-+		RTW_INFO("argument size is less than 3\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%x %d %x", &addr, &cnts, &efuse_data);
-+
-+		if (num != 3) {
-+			RTW_INFO("invalid write_reg parameter!\n");
-+			return count;
-+		}
-+	}
-+	ips_mode = pwrctrlpriv->ips_mode;
-+	rtw_pm_set_ips(padapter, IPS_NONE);
-+	if (rtw_efuse_map_write(padapter, addr, cnts, &efuse_data) == _FAIL)
-+		RTW_INFO("WARN - rtw_efuse_map_write error!!\n");
-+	rtw_pm_set_ips(padapter, ips_mode);
-+#endif
-+	return count;
-+}
-+
-+#ifdef CONFIG_IEEE80211W
-+ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct	sta_priv *pstapriv = &padapter->stapriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	struct sta_info *psta;
-+	_list	*plist, *phead;
-+	_irqL	 irqL;
-+	char tmp[16];
-+	u8	mac_addr[NUM_STA][ETH_ALEN];
-+	u32 key_type;
-+	u8 index;
-+
-+	if (count > 2) {
-+		RTW_INFO("argument size is more than 2\n");
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
-+
-+		int num = sscanf(tmp, "%x", &key_type);
-+
-+		if (num !=  1) {
-+			RTW_INFO("invalid read_reg parameter!\n");
-+			return count;
-+		}
-+		RTW_INFO("0: set sa query request , key_type=%d\n", key_type);
-+	}
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
-+	    && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) {
-+		RTW_INFO("STA:"MAC_FMT"\n", MAC_ARG(get_my_bssid(&(pmlmeinfo->network))));
-+		/* TX unicast sa_query to AP */
-+		issue_action_SA_Query(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, 0, (u8)key_type);
-+	} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) {
-+		/* TX unicast sa_query to every client STA */
-+		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+		for (index = 0; index < NUM_STA; index++) {
-+			psta = NULL;
-+
-+			phead = &(pstapriv->sta_hash[index]);
-+			plist = get_next(phead);
-+
-+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+				plist = get_next(plist);
-+				_rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN);
-+			}
-+		}
-+		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+		for (index = 0; index < macid_ctl->num && index < NUM_STA; index++) {
-+			if (rtw_macid_is_used(macid_ctl, index) && !rtw_macid_is_bmc(macid_ctl, index)) {
-+				if (!_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), &mac_addr[index][0], ETH_ALEN)
-+				    && !IS_MCAST(&mac_addr[index][0])) {
-+					issue_action_SA_Query(padapter, &mac_addr[index][0], 0, 0, (u8)key_type);
-+					RTW_INFO("STA[%u]:"MAC_FMT"\n", index , MAC_ARG(&mac_addr[index][0]));
-+				}
-+			}
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_tx_sa_query(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m, "%s\n", __func__);
-+	return 0;
-+}
-+
-+ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct	sta_priv *pstapriv = &padapter->stapriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	struct sta_info *psta;
-+	_list	*plist, *phead;
-+	_irqL	 irqL;
-+	char tmp[16];
-+	u8	mac_addr[NUM_STA][ETH_ALEN];
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	u32 key_type;
-+	u8 index;
-+
-+
-+	if (count > 2) {
-+		RTW_INFO("argument size is more than 2\n");
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
-+
-+		int num = sscanf(tmp, "%x", &key_type);
-+
-+		if (num !=  1) {
-+			RTW_INFO("invalid read_reg parameter!\n");
-+			return count;
-+		}
-+		RTW_INFO("key_type=%d\n", key_type);
-+	}
-+	if (key_type < 0 || key_type > 4)
-+		return count;
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
-+	    && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
-+		if (key_type == 3) /* key_type 3 only for AP mode */
-+			return count;
-+		/* TX unicast deauth to AP */
-+		issue_deauth_11w(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, (u8)key_type);
-+#ifdef CONFIG_AP_MODE
-+	} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
-+		u8 updated = _FALSE;
-+
-+		if (key_type == 3)
-+			issue_deauth_11w(padapter, bc_addr, 0, IEEE80211W_RIGHT_KEY);
-+
-+		/* TX unicast deauth to every client STA */
-+		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+		for (index = 0; index < NUM_STA; index++) {
-+			psta = NULL;
-+
-+			phead = &(pstapriv->sta_hash[index]);
-+			plist = get_next(phead);
-+
-+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+				plist = get_next(plist);
-+				_rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN);
-+			}
-+		}
-+		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+		for (index = 0; index < macid_ctl->num && index < NUM_STA; index++) {
-+			if (rtw_macid_is_used(macid_ctl, index) && !rtw_macid_is_bmc(macid_ctl, index)) {
-+				if (!_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), &mac_addr[index][0], ETH_ALEN)) {
-+					if (key_type != 3)
-+						issue_deauth_11w(padapter, &mac_addr[index][0], 0, (u8)key_type);
-+
-+					psta = rtw_get_stainfo(pstapriv, &mac_addr[index][0]);
-+					if (psta && key_type != IEEE80211W_WRONG_KEY && key_type != IEEE80211W_NO_KEY) {
-+						_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+						if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
-+							rtw_list_delete(&psta->asoc_list);
-+							pstapriv->asoc_list_cnt--;
-+							#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+							if (psta->tbtx_enable)
-+								pstapriv->tbtx_asoc_list_cnt--;
-+							#endif
-+							updated |= ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE);
-+
-+						}
-+						_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+					}
-+
-+					RTW_INFO("STA[%u]:"MAC_FMT"\n", index , MAC_ARG(&mac_addr[index][0]));
-+				}
-+			}
-+		}
-+
-+		associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
-+#endif /* CONFIG_AP_MODE */
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_tx_deauth(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m, "%s\n", __func__);
-+	return 0;
-+}
-+
-+ssize_t proc_set_tx_auth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct	sta_priv *pstapriv = &padapter->stapriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	struct sta_info *psta;
-+	_list	*plist, *phead;
-+	_irqL	 irqL;
-+	char tmp[16];
-+	u8	mac_addr[NUM_STA][ETH_ALEN];
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	u32 tx_auth;
-+	u8 index;
-+
-+
-+	if (count > 2) {
-+		RTW_INFO("argument size is more than 2\n");
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
-+
-+		int num = sscanf(tmp, "%x", &tx_auth);
-+
-+		if (num !=  1) {
-+			RTW_INFO("invalid read_reg parameter!\n");
-+			return count;
-+		}
-+		RTW_INFO("1: setnd auth, 2: send assoc request. tx_auth=%d\n", tx_auth);
-+	}
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
-+	    && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
-+		if (tx_auth == 1) {
-+			/* TX unicast auth to AP */
-+			issue_auth(padapter, NULL, 0);
-+		} else if (tx_auth == 2) {
-+			/* TX unicast auth to AP */
-+			issue_assocreq(padapter);
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_tx_auth(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m, "%s\n", __func__);
-+	return 0;
-+}
-+#endif /* CONFIG_IEEE80211W */
-+
-+#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
-+static u32 phase_idx;
-+int proc_get_pathb_phase(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m, "PathB phase index =%d\n", phase_idx);
-+	return 0;
-+}
-+
-+ssize_t proc_set_pathb_phase(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[255];
-+	int num;
-+	u32 tmp_idx;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		num = sscanf(tmp, "%u", &tmp_idx);
-+		if ((tmp_idx < 0) || (tmp_idx > 11)) {
-+			RTW_INFO(FUNC_ADPT_FMT "Invalid input value\n", FUNC_ADPT_ARG(padapter));
-+			return count;
-+		}
-+		phase_idx = tmp_idx;
-+		rtw_hal_set_pathb_phase(padapter, phase_idx);
-+	}
-+	return count;
-+}
-+#endif
-+
-+#ifdef CONFIG_MCC_MODE
-+int proc_get_mcc_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_adapters_status(m, adapter_to_dvobj(adapter));
-+	rtw_hal_dump_mcc_info(m, adapter_to_dvobj(adapter));
-+	return 0;
-+}
-+
-+int proc_get_mcc_policy_table(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	rtw_hal_dump_mcc_policy_table(m);
-+	return 0;
-+}
-+
-+ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[255];
-+	u32 en_mcc = 0;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+		_adapter *iface = NULL;
-+		u8 i = 0;
-+		int num = sscanf(tmp, "%u", &en_mcc);
-+
-+		if (num < 1) {
-+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
-+			return -EINVAL;
-+		}
-+
-+		RTW_INFO("%s: en_mcc = %d\n", __func__, en_mcc);
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			if (!iface)
-+				continue;
-+			iface->registrypriv.en_mcc = en_mcc;
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+ssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[255];
-+	u32 enable_runtime_duration = 0, mcc_duration = 0, type = 0;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%u %u %u", &enable_runtime_duration, &type, &mcc_duration);
-+
-+		if (num < 1) {
-+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
-+			return -EINVAL;
-+		}
-+
-+		if (num > 3) {
-+			RTW_INFO(FUNC_ADPT_FMT ": input parameters > 2\n", FUNC_ADPT_ARG(padapter));
-+			return -EINVAL;
-+		}
-+
-+		if (num == 2) {
-+			RTW_INFO(FUNC_ADPT_FMT ": input parameters > 2\n", FUNC_ADPT_ARG(padapter));
-+			return -EINVAL;
-+		}
-+
-+		if (num >= 1) {
-+			SET_MCC_RUNTIME_DURATION(padapter, enable_runtime_duration);
-+			RTW_INFO("runtime duration:%s\n", enable_runtime_duration ? "enable":"disable");
-+		}
-+
-+		if (num == 3) {
-+			RTW_INFO("type:%d, mcc duration:%d\n", type, mcc_duration);
-+			rtw_set_mcc_duration_cmd(padapter, type, mcc_duration);
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+ssize_t proc_set_mcc_phydm_offload_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[255];
-+	u32 mcc_phydm_enable = 0;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+		u8 i = 0;
-+		int num = sscanf(tmp, "%u", &mcc_phydm_enable);
-+
-+		if (num < 1) {
-+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
-+			return -EINVAL;
-+		}
-+
-+		RTW_INFO("%s: mcc phydm enable = %d\n", __func__, mcc_phydm_enable);
-+		rtw_set_mcc_phydm_offload_enable_cmd(padapter, mcc_phydm_enable, _TRUE);
-+	}
-+
-+	return count;
-+}
-+#endif
-+
-+ssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[255];
-+	u32 mcc_single_tx_criteria = 0;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+		_adapter *iface = NULL;
-+		u8 i = 0;
-+		int num = sscanf(tmp, "%u", &mcc_single_tx_criteria);
-+
-+		if (num < 1) {
-+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
-+			return -EINVAL;
-+		}
-+
-+		RTW_INFO("%s: mcc_single_tx_criteria = %d\n", __func__, mcc_single_tx_criteria);
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			if (!iface)
-+				continue;
-+			iface->registrypriv.rtw_mcc_single_tx_cri = mcc_single_tx_criteria;
-+		}
-+
-+
-+	}
-+
-+	return count;
-+}
-+
-+
-+ssize_t proc_set_mcc_ap_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[255];
-+	u32 mcc_ap_bw20_target_tp = 0;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%u", &mcc_ap_bw20_target_tp);
-+
-+		if (num < 1) {
-+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
-+			return -EINVAL;
-+		}
-+
-+		RTW_INFO("%s: mcc_ap_bw20_target_tp = %d\n", __func__, mcc_ap_bw20_target_tp);
-+
-+		padapter->registrypriv.rtw_mcc_ap_bw20_target_tx_tp = mcc_ap_bw20_target_tp;
-+
-+
-+	}
-+
-+	return count;
-+}
-+
-+ssize_t proc_set_mcc_ap_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[255];
-+	u32 mcc_ap_bw40_target_tp = 0;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%u", &mcc_ap_bw40_target_tp);
-+
-+		if (num < 1) {
-+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
-+			return -EINVAL;
-+		}
-+
-+		RTW_INFO("%s: mcc_ap_bw40_target_tp = %d\n", __func__, mcc_ap_bw40_target_tp);
-+
-+		padapter->registrypriv.rtw_mcc_ap_bw40_target_tx_tp = mcc_ap_bw40_target_tp;
-+
-+
-+	}
-+
-+	return count;
-+}
-+
-+ssize_t proc_set_mcc_ap_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[255];
-+	u32 mcc_ap_bw80_target_tp = 0;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%u", &mcc_ap_bw80_target_tp);
-+
-+		if (num < 1) {
-+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
-+			return -EINVAL;
-+		}
-+
-+		RTW_INFO("%s: mcc_ap_bw80_target_tp = %d\n", __func__, mcc_ap_bw80_target_tp);
-+
-+		padapter->registrypriv.rtw_mcc_ap_bw80_target_tx_tp = mcc_ap_bw80_target_tp;
-+
-+
-+	}
-+
-+	return count;
-+}
-+
-+ssize_t proc_set_mcc_sta_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[255];
-+	u32 mcc_sta_bw20_target_tp = 0;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%u", &mcc_sta_bw20_target_tp);
-+
-+		if (num < 1) {
-+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
-+			return -EINVAL;
-+		}
-+
-+		RTW_INFO("%s: mcc_sta_bw20_target_tp = %d\n", __func__, mcc_sta_bw20_target_tp);
-+
-+		padapter->registrypriv.rtw_mcc_sta_bw20_target_tx_tp = mcc_sta_bw20_target_tp;
-+
-+
-+	}
-+
-+	return count;
-+}
-+
-+ssize_t proc_set_mcc_sta_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[255];
-+	u32 mcc_sta_bw40_target_tp = 0;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%u", &mcc_sta_bw40_target_tp);
-+
-+		if (num < 1) {
-+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
-+			return -EINVAL;
-+		}
-+
-+		RTW_INFO("%s: mcc_sta_bw40_target_tp = %d\n", __func__, mcc_sta_bw40_target_tp);
-+
-+		padapter->registrypriv.rtw_mcc_sta_bw40_target_tx_tp = mcc_sta_bw40_target_tp;
-+
-+
-+	}
-+
-+	return count;
-+}
-+
-+ssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[255];
-+	u32 mcc_sta_bw80_target_tp = 0;
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%u", &mcc_sta_bw80_target_tp);
-+
-+		if (num < 1) {
-+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
-+			return -EINVAL;
-+		}
-+
-+		RTW_INFO("%s: mcc_sta_bw80_target_tp = %d\n", __func__, mcc_sta_bw80_target_tp);
-+
-+		padapter->registrypriv.rtw_mcc_sta_bw80_target_tx_tp = mcc_sta_bw80_target_tp;
-+
-+
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_MCC_MODE */
-+
-+int proc_get_ack_timeout(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 ack_timeout_val;
-+#ifdef CONFIG_RTL8821C
-+	u8 ack_timeout_val_cck;
-+#endif
-+
-+	ack_timeout_val = rtw_read8(padapter, REG_ACKTO);
-+
-+#ifdef CONFIG_RTL8821C
-+	ack_timeout_val_cck = rtw_read8(padapter, REG_ACKTO_CCK_8821C);
-+	RTW_PRINT_SEL(m, "Current CCK packet ACK Timeout = %d us (0x%x).\n", ack_timeout_val_cck, ack_timeout_val_cck);
-+	RTW_PRINT_SEL(m, "Current non-CCK packet ACK Timeout = %d us (0x%x).\n", ack_timeout_val, ack_timeout_val);
-+#else
-+	RTW_PRINT_SEL(m, "Current ACK Timeout = %d us (0x%x).\n", ack_timeout_val, ack_timeout_val);
-+#endif
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u32 ack_timeout_ms, ack_timeout_ms_cck;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%u %u", &ack_timeout_ms, &ack_timeout_ms_cck);
-+
-+#ifdef CONFIG_RTL8821C
-+		if (num < 2) {
-+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 2\n", FUNC_ADPT_ARG(padapter));
-+			return -EINVAL;
-+		}
-+#else
-+		if (num < 1) {
-+			RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
-+			return -EINVAL;
-+		}
-+#endif
-+		/* This register sets the Ack time out value after Tx unicast packet. It is in units of us. */
-+		rtw_write8(padapter, REG_ACKTO, (u8)ack_timeout_ms);
-+
-+#ifdef CONFIG_RTL8821C
-+		/* This register sets the Ack time out value after Tx unicast CCK packet. It is in units of us. */
-+		rtw_write8(padapter, REG_ACKTO_CCK_8821C, (u8)ack_timeout_ms_cck);
-+		RTW_INFO("Set CCK packet ACK Timeout to %d us.\n", ack_timeout_ms_cck);
-+		RTW_INFO("Set non-CCK packet ACK Timeout to %d us.\n", ack_timeout_ms);
-+#else
-+		RTW_INFO("Set ACK Timeout to %d us.\n", ack_timeout_ms);
-+#endif
-+	}
-+
-+	return count;
-+}
-+
-+ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	_adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter);
-+	HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
-+	char tmp[32];
-+	u32 iqk_offload_enable = 0, ch_switch_offload_enable = 0;
-+
-+	if (buffer == NULL) {
-+		RTW_INFO("input buffer is NULL!\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO("input length is 0!\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO("input length is too large\n");
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%d %d", &iqk_offload_enable, &ch_switch_offload_enable);
-+
-+		if (num < 2) {
-+			RTW_INFO("input parameters < 1\n");
-+			return -EINVAL;
-+		}
-+
-+		if (hal->RegIQKFWOffload != iqk_offload_enable) {
-+			hal->RegIQKFWOffload = iqk_offload_enable;
-+			rtw_run_in_thread_cmd(pri_adapter, ((void *)(rtw_hal_update_iqk_fw_offload_cap)), pri_adapter);
-+		}
-+
-+		if (hal->ch_switch_offload != ch_switch_offload_enable)
-+			hal->ch_switch_offload = ch_switch_offload_enable;
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_fw_offload(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
-+
-+
-+	RTW_PRINT_SEL(m, "IQK FW offload:%s\n", hal->RegIQKFWOffload?"enable":"disable");
-+	RTW_PRINT_SEL(m, "Channel switch FW offload:%s\n", hal->ch_switch_offload?"enable":"disable");
-+	return 0;
-+}
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+extern void rtw_hal_set_fw_ap_bcn_offload_cmd(_adapter *adapter, bool fw_bcn_en, u8 tbtt_rpt_map);
-+ssize_t proc_set_fw_tbtt_rpt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u32 fw_tbtt_rpt, fw_bcn_offload;
-+
-+
-+	if (buffer == NULL) {
-+		RTW_INFO("input buffer is NULL!\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO("input length is 0!\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO("input length is too large\n");
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%d %x",&fw_bcn_offload, &fw_tbtt_rpt);
-+
-+		if (num < 2) {
-+			RTW_INFO("input parameters < 2\n");
-+			return -EINVAL;
-+		}
-+		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, fw_bcn_offload, fw_tbtt_rpt);
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_fw_tbtt_rpt(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	RTW_PRINT_SEL(m, "FW BCN offload:%s\n", dvobj->fw_bcn_offload ? "enable" : "disable");
-+	RTW_PRINT_SEL(m, "FW TBTT RPT:%x\n", dvobj->vap_tbtt_rpt_map);
-+	return 0;
-+}
-+
-+#endif
-+
-+#ifdef CONFIG_CTRL_TXSS_BY_TP
-+ssize_t proc_set_txss_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+
-+	char tmp[32];
-+	u32 enable = 0;
-+	u32 txss_tx_tp = 0;
-+	int txss_chk_cnt = 0;
-+
-+	if (buffer == NULL) {
-+		RTW_INFO("input buffer is NULL!\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO("input length is 0!\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO("input length is too large\n");
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%u %u %d",
-+			&enable, &txss_tx_tp, &txss_chk_cnt);
-+
-+		if (num < 1) {
-+			RTW_INFO("input parameters < 1\n");
-+			return -EINVAL;
-+		}
-+		pmlmeext->txss_ctrl_en = enable;
-+
-+		if (txss_tx_tp)
-+			pmlmeext->txss_tp_th = txss_tx_tp;
-+		if (txss_chk_cnt)
-+			pmlmeext->txss_tp_chk_cnt = txss_chk_cnt;
-+
-+		RTW_INFO("%s txss_ctl_en :%s , txss_tp_th:%d, tp_chk_cnt:%d\n",
-+			__func__, pmlmeext->txss_tp_th ? "Y" : "N",
-+			pmlmeext->txss_tp_th, pmlmeext->txss_tp_chk_cnt);
-+
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_txss_tp(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+
-+	RTW_PRINT_SEL(m, "TXSS  Control - %s\n", pmlmeext->txss_ctrl_en ? "enable" : "disable");
-+	RTW_PRINT_SEL(m, "TXSS  Tx TP TH - %d\n", pmlmeext->txss_tp_th);
-+	RTW_PRINT_SEL(m, "TXSS  check cnt - %d\n", pmlmeext->txss_tp_chk_cnt);
-+
-+	return 0;
-+}
-+#ifdef DBG_CTRL_TXSS
-+ssize_t proc_set_txss_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+
-+	char tmp[32];
-+	u32 tx_1ss = 0;
-+
-+	if (buffer == NULL) {
-+		RTW_INFO("input buffer is NULL!\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO("input length is 0!\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO("input length is too large\n");
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%u",	&tx_1ss);
-+
-+		if (num < 1) {
-+			RTW_INFO("input parameters < 1\n");
-+			return -EINVAL;
-+		}
-+
-+		pmlmeext->txss_ctrl_en = _FALSE;
-+
-+		dbg_ctrl_txss(adapter, tx_1ss);
-+
-+		RTW_INFO("%s set tx to  1ss :%s\n", __func__, tx_1ss ? "Y" : "N");
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_txss_ctrl(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+
-+	RTW_PRINT_SEL(m, "TXSS  1ss - %s\n", pmlmeext->txss_1ss ? "Y" : "N");
-+
-+	return 0;
-+}
-+#endif
-+#endif
-+
-+#ifdef CONFIG_DBG_RF_CAL
-+int proc_get_iqk_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_iqk(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u32 recovery, clear, segment;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d %d %d", &recovery, &clear, &segment);
-+
-+		if (num != 3) {
-+			RTW_INFO("Invalid format\n");
-+			return count;
-+		}
-+
-+		rtw_hal_iqk_test(padapter, recovery, clear, segment);
-+	}
-+
-+	return count;
-+
-+}
-+
-+int proc_get_lck_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_lck(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u32 trigger;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d", &trigger);
-+
-+		if (num != 1) {
-+			RTW_INFO("Invalid format\n");
-+			return count;
-+		}
-+
-+		rtw_hal_lck_test(padapter);
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_DBG_RF_CAL */
-+
-+#ifdef CONFIG_LPS_CHK_BY_TP
-+ssize_t proc_set_lps_chk_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	char tmp[32];
-+	u32 enable = 0;
-+	u32 lps_tx_tp = 0, lps_rx_tp = 0, lps_bi_tp = 0;
-+	int lps_chk_cnt_th = 0;
-+	u32 lps_tx_pkts = 0, lps_rx_pkts = 0;
-+
-+	if (buffer == NULL) {
-+		RTW_INFO("input buffer is NULL!\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO("input length is 0!\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO("input length is too large\n");
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%u %u %u %u %d %u %u",
-+			&enable, &lps_tx_tp, &lps_rx_tp, &lps_bi_tp,
-+			&lps_chk_cnt_th, &lps_tx_pkts, &lps_rx_pkts);
-+
-+		if (num < 1) {
-+			RTW_INFO("input parameters < 1\n");
-+			return -EINVAL;
-+		}
-+		pwrpriv->lps_chk_by_tp = enable;
-+
-+		if (lps_tx_tp) {
-+			pwrpriv->lps_tx_tp_th = lps_tx_tp;
-+			pwrpriv->lps_rx_tp_th = lps_tx_tp;
-+			pwrpriv->lps_bi_tp_th = lps_tx_tp;
-+		}
-+		if (lps_rx_tp)
-+			pwrpriv->lps_rx_tp_th = lps_rx_tp;
-+		if (lps_bi_tp)
-+			pwrpriv->lps_bi_tp_th = lps_bi_tp;
-+
-+		if (lps_chk_cnt_th)
-+			pwrpriv->lps_chk_cnt_th = lps_chk_cnt_th;
-+
-+		if (lps_tx_pkts)
-+			pwrpriv->lps_tx_pkts = lps_tx_pkts;
-+
-+		if (lps_rx_pkts)
-+			pwrpriv->lps_rx_pkts = lps_rx_pkts;
-+
-+		RTW_INFO("%s lps_chk_by_tp:%s , lps_tx_tp_th:%d, lps_tx_tp_th:%d, lps_bi_tp:%d\n",
-+			__func__, pwrpriv->lps_chk_by_tp ? "Y" : "N",
-+			pwrpriv->lps_tx_tp_th, pwrpriv->lps_tx_tp_th, pwrpriv->lps_bi_tp_th);
-+		RTW_INFO("%s lps_chk_cnt_th:%d , lps_tx_pkts:%d, lps_rx_pkts:%d\n",
-+			__func__, pwrpriv->lps_chk_cnt_th, pwrpriv->lps_tx_pkts, pwrpriv->lps_rx_pkts);
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_lps_chk_tp(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+
-+	RTW_PRINT_SEL(m, "LPS chk by tp - %s\n", pwrpriv->lps_chk_by_tp ? "enable" : "disable");
-+	RTW_PRINT_SEL(m, "LPS Tx TP TH - %d(Mbps)\n", pwrpriv->lps_tx_tp_th);
-+	RTW_PRINT_SEL(m, "LPS Rx TP TH - %d(Mbps)\n", pwrpriv->lps_rx_tp_th);
-+	RTW_PRINT_SEL(m, "LPS BI TP TH - %d(Mbps)\n", pwrpriv->lps_bi_tp_th);
-+
-+	RTW_PRINT_SEL(m, "LPS CHK CNT - %d\n", pwrpriv->lps_chk_cnt_th);
-+	RTW_PRINT_SEL(m, "LPS Tx PKTs - %d\n", pwrpriv->lps_tx_pkts);
-+	RTW_PRINT_SEL(m, "LPS Rx PKTs - %d\n", pwrpriv->lps_rx_pkts);
-+	return 0;
-+}
-+#endif /*CONFIG_LPS_CHK_BY_TP*/
-+#ifdef CONFIG_SUPPORT_STATIC_SMPS
-+ssize_t proc_set_smps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+	char tmp[32];
-+	u32 enable = 0;
-+	u32 smps_en, smps_tx_tp = 0, smps_rx_tp = 0;
-+	u32 smps_test = 0, smps_test_en = 0;
-+
-+	if (buffer == NULL) {
-+		RTW_INFO("input buffer is NULL!\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO("input length is 0!\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_INFO("input length is too large\n");
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%u %u %u %u %u", &smps_en, &smps_tx_tp, &smps_rx_tp,
-+			&smps_test, &smps_test_en);
-+
-+		if (num < 1) {
-+			RTW_INFO("input parameters < 1\n");
-+			return -EINVAL;
-+		}
-+
-+		pmlmeext->ssmps_en = smps_en;
-+		if (smps_tx_tp) {
-+			pmlmeext->ssmps_tx_tp_th= smps_tx_tp;
-+			pmlmeext->ssmps_rx_tp_th= smps_tx_tp;
-+		}
-+		if (smps_rx_tp)
-+			pmlmeext->ssmps_rx_tp_th = smps_rx_tp;
-+
-+		#ifdef DBG_STATIC_SMPS
-+		if (num > 3) {
-+			pmlmeext->ssmps_test = smps_test;
-+			pmlmeext->ssmps_test_en = smps_test_en;
-+		}
-+		#endif
-+		RTW_INFO("SM PS : %s tx_tp_th:%d, rx_tp_th:%d\n",
-+			(smps_en) ? "Enable" : "Disable",
-+			pmlmeext->ssmps_tx_tp_th,
-+			pmlmeext->ssmps_rx_tp_th);
-+		#ifdef DBG_STATIC_SMPS
-+		RTW_INFO("SM PS : %s ssmps_test_en:%d\n",
-+			(smps_test) ? "Enable" : "Disable",
-+			pmlmeext->ssmps_test_en);
-+		#endif
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_smps(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+
-+	RTW_PRINT_SEL(m, "Static SMPS %s\n", pmlmeext->ssmps_en ? "enable" : "disable");
-+	RTW_PRINT_SEL(m, "Tx TP TH %d\n", pmlmeext->ssmps_tx_tp_th);
-+	RTW_PRINT_SEL(m, "Rx TP TH %d\n", pmlmeext->ssmps_rx_tp_th);
-+	#ifdef DBG_STATIC_SMPS
-+	RTW_PRINT_SEL(m, "test %d, test_en:%d\n", pmlmeext->ssmps_test, pmlmeext->ssmps_test_en);
-+	#endif
-+	return 0;
-+}
-+#endif /*CONFIG_SUPPORT_STATIC_SMPS*/
-+
-+#endif /* CONFIG_PROC_DEBUG */
-+#define RTW_BUFDUMP_BSIZE		16
-+#if 1
-+inline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring,
-+					bool _idx_show, const u8 *_hexdata, int _hexdatalen)
-+{
-+#ifdef CONFIG_RTW_DEBUG
-+	int __i;
-+	u8 *ptr = (u8 *)_hexdata;
-+
-+	if (_loglevel <= rtw_drv_log_level) {
-+		if (_titlestring) {
-+			if (sel == RTW_DBGDUMP)
-+				RTW_PRINT("");
-+			_RTW_PRINT_SEL(sel, "%s", _titlestring);
-+			if (_hexdatalen >= RTW_BUFDUMP_BSIZE)
-+				_RTW_PRINT_SEL(sel, "\n");
-+		}
-+
-+		for (__i = 0; __i < _hexdatalen; __i++) {
-+			if (((__i % RTW_BUFDUMP_BSIZE) == 0) && (_hexdatalen >= RTW_BUFDUMP_BSIZE)) {
-+				if (sel == RTW_DBGDUMP)
-+					RTW_PRINT("");
-+				if (_idx_show)
-+					_RTW_PRINT_SEL(sel, "0x%03X: ", __i);
-+			}
-+			_RTW_PRINT_SEL(sel, "%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? "  " : " ");
-+			if ((__i + 1 < _hexdatalen) && ((__i + 1) % RTW_BUFDUMP_BSIZE) == 0)
-+				_RTW_PRINT_SEL(sel, "\n");
-+		}
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+#endif
-+}
-+#else
-+inline void _RTW_STR_DUMP_SEL(void *sel, char *str_out)
-+{
-+	if (sel == RTW_DBGDUMP)
-+		_dbgdump("%s\n", str_out);
-+	#if defined(_seqdump)
-+	else
-+		_seqdump(sel, "%s\n", str_out);
-+	#endif /*_seqdump*/
-+}
-+inline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring,
-+					bool _idx_show, u8 *_hexdata, int _hexdatalen)
-+{
-+	int __i, len;
-+	int __j, idx;
-+	int block_num, remain_byte;
-+	char str_out[128] = {'\0'};
-+	char str_val[32] = {'\0'};
-+	char *p = NULL;
-+	u8 *ptr = (u8 *)_hexdata;
-+
-+	if (_loglevel <= rtw_drv_log_level) {
-+		/*dump title*/
-+		p = &str_out[0];
-+		if (_titlestring) {
-+			if (sel == RTW_DBGDUMP) {
-+				len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX);
-+				strncpy(p, str_val, len);
-+				p += len;
-+			}
-+			len = snprintf(str_val, sizeof(str_val), "%s", _titlestring);
-+			strncpy(p, str_val, len);
-+			p += len;
-+		}
-+		if (p != &str_out[0]) {
-+			_RTW_STR_DUMP_SEL(sel, str_out);
-+			_rtw_memset(&str_out, '\0', sizeof(str_out));
-+		}
-+
-+		/*dump buffer*/
-+		block_num = _hexdatalen / RTW_BUFDUMP_BSIZE;
-+		remain_byte = _hexdatalen % RTW_BUFDUMP_BSIZE;
-+		for (__i = 0; __i < block_num; __i++) {
-+			p = &str_out[0];
-+			if (sel == RTW_DBGDUMP) {
-+				len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX);
-+				strncpy(p, str_val, len);
-+				p += len;
-+			}
-+			if (_idx_show) {
-+				len = snprintf(str_val, sizeof(str_val), "0x%03X: ", __i * RTW_BUFDUMP_BSIZE);
-+				strncpy(p, str_val, len);
-+				p += len;
-+			}
-+			for (__j =0; __j < RTW_BUFDUMP_BSIZE; __j++) {
-+				idx = __i * RTW_BUFDUMP_BSIZE + __j;
-+				len = snprintf(str_val, sizeof(str_val), "%02X%s", ptr[idx], (((__j + 1) % 4) == 0) ? "  " : " ");
-+				strncpy(p, str_val, len);
-+				p += len;
-+			}
-+			_RTW_STR_DUMP_SEL(sel, str_out);
-+			_rtw_memset(&str_out, '\0', sizeof(str_out));
-+		}
-+
-+		p = &str_out[0];
-+		if ((sel == RTW_DBGDUMP) && remain_byte) {
-+			len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX);
-+			strncpy(p, str_val, len);
-+			p += len;
-+		}
-+		if (_idx_show && remain_byte) {
-+			len = snprintf(str_val, sizeof(str_val), "0x%03X: ", block_num * RTW_BUFDUMP_BSIZE);
-+			strncpy(p, str_val, len);
-+			p += len;
-+		}
-+		for (__i = 0; __i < remain_byte; __i++) {
-+			idx = block_num * RTW_BUFDUMP_BSIZE + __i;
-+			len = snprintf(str_val, sizeof(str_val), "%02X%s", ptr[idx], (((__i + 1) % 4) == 0) ? "  " : " ");
-+			strncpy(p, str_val, len);
-+			p += len;
-+		}
-+		_RTW_STR_DUMP_SEL(sel, str_out);
-+	}
-+}
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/core/rtw_eeprom.c b/drivers/staging/rtl8723cs/core/rtw_eeprom.c
-new file mode 100644
-index 000000000000..62c0be06ce3a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_eeprom.c
-@@ -0,0 +1,329 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_EEPROM_C_
-+
-+#include <drv_conf.h>
-+#include <osdep_service.h>
-+#include <drv_types.h>
-+
-+void up_clk(_adapter	*padapter,	 u16 *x)
-+{
-+	*x = *x | _EESK;
-+	rtw_write8(padapter, EE_9346CR, (u8)*x);
-+	rtw_udelay_os(CLOCK_RATE);
-+
-+
-+}
-+
-+void down_clk(_adapter	*padapter, u16 *x)
-+{
-+	*x = *x & ~_EESK;
-+	rtw_write8(padapter, EE_9346CR, (u8)*x);
-+	rtw_udelay_os(CLOCK_RATE);
-+}
-+
-+void shift_out_bits(_adapter *padapter, u16 data, u16 count)
-+{
-+	u16 x, mask;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		goto out;
-+	}
-+	mask = 0x01 << (count - 1);
-+	x = rtw_read8(padapter, EE_9346CR);
-+
-+	x &= ~(_EEDO | _EEDI);
-+
-+	do {
-+		x &= ~_EEDI;
-+		if (data & mask)
-+			x |= _EEDI;
-+		if (rtw_is_surprise_removed(padapter)) {
-+			goto out;
-+		}
-+		rtw_write8(padapter, EE_9346CR, (u8)x);
-+		rtw_udelay_os(CLOCK_RATE);
-+		up_clk(padapter, &x);
-+		down_clk(padapter, &x);
-+		mask = mask >> 1;
-+	} while (mask);
-+	if (rtw_is_surprise_removed(padapter)) {
-+		goto out;
-+	}
-+	x &= ~_EEDI;
-+	rtw_write8(padapter, EE_9346CR, (u8)x);
-+out:
-+	return;
-+}
-+
-+u16 shift_in_bits(_adapter *padapter)
-+{
-+	u16 x, d = 0, i;
-+	if (rtw_is_surprise_removed(padapter)) {
-+		goto out;
-+	}
-+	x = rtw_read8(padapter, EE_9346CR);
-+
-+	x &= ~(_EEDO | _EEDI);
-+	d = 0;
-+
-+	for (i = 0; i < 16; i++) {
-+		d = d << 1;
-+		up_clk(padapter, &x);
-+		if (rtw_is_surprise_removed(padapter)) {
-+			goto out;
-+		}
-+		x = rtw_read8(padapter, EE_9346CR);
-+
-+		x &= ~(_EEDI);
-+		if (x & _EEDO)
-+			d |= 1;
-+
-+		down_clk(padapter, &x);
-+	}
-+out:
-+
-+	return d;
-+}
-+
-+void standby(_adapter	*padapter)
-+{
-+	u8   x;
-+	x = rtw_read8(padapter, EE_9346CR);
-+
-+	x &= ~(_EECS | _EESK);
-+	rtw_write8(padapter, EE_9346CR, x);
-+
-+	rtw_udelay_os(CLOCK_RATE);
-+	x |= _EECS;
-+	rtw_write8(padapter, EE_9346CR, x);
-+	rtw_udelay_os(CLOCK_RATE);
-+}
-+
-+u16 wait_eeprom_cmd_done(_adapter *padapter)
-+{
-+	u8	x;
-+	u16	i, res = _FALSE;
-+	standby(padapter);
-+	for (i = 0; i < 200; i++) {
-+		x = rtw_read8(padapter, EE_9346CR);
-+		if (x & _EEDO) {
-+			res = _TRUE;
-+			goto exit;
-+		}
-+		rtw_udelay_os(CLOCK_RATE);
-+	}
-+exit:
-+	return res;
-+}
-+
-+void eeprom_clean(_adapter *padapter)
-+{
-+	u16 x;
-+	if (rtw_is_surprise_removed(padapter)) {
-+		goto out;
-+	}
-+	x = rtw_read8(padapter, EE_9346CR);
-+	if (rtw_is_surprise_removed(padapter)) {
-+		goto out;
-+	}
-+	x &= ~(_EECS | _EEDI);
-+	rtw_write8(padapter, EE_9346CR, (u8)x);
-+	if (rtw_is_surprise_removed(padapter)) {
-+		goto out;
-+	}
-+	up_clk(padapter, &x);
-+	if (rtw_is_surprise_removed(padapter)) {
-+		goto out;
-+	}
-+	down_clk(padapter, &x);
-+out:
-+	return;
-+}
-+
-+void eeprom_write16(_adapter *padapter, u16 reg, u16 data)
-+{
-+	u8 x;
-+	x = rtw_read8(padapter, EE_9346CR);
-+
-+	x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
-+	x |= _EEM1 | _EECS;
-+	rtw_write8(padapter, EE_9346CR, x);
-+
-+	shift_out_bits(padapter, EEPROM_EWEN_OPCODE, 5);
-+
-+	if (padapter->EepromAddressSize == 8)	/* CF+ and SDIO */
-+		shift_out_bits(padapter, 0, 6);
-+	else									/* USB */
-+		shift_out_bits(padapter, 0, 4);
-+
-+	standby(padapter);
-+
-+	/* Commented out by rcnjko, 2004.0
-+	 * 	  Erase this particular word.  Write the erase opcode and register
-+	 *    number in that order. The opcode is 3bits in length; reg is 6 bits long. */
-+/*	shift_out_bits(Adapter, EEPROM_ERASE_OPCODE, 3);
-+ *	shift_out_bits(Adapter, reg, Adapter->EepromAddressSize);
-+ *
-+ *	if (wait_eeprom_cmd_done(Adapter ) == FALSE)
-+ *	{
-+ *		return;
-+ *	} */
-+
-+
-+	standby(padapter);
-+
-+	/* write the new word to the EEPROM */
-+
-+	/* send the write opcode the EEPORM */
-+	shift_out_bits(padapter, EEPROM_WRITE_OPCODE, 3);
-+
-+	/* select which word in the EEPROM that we are writing to. */
-+	shift_out_bits(padapter, reg, padapter->EepromAddressSize);
-+
-+	/* write the data to the selected EEPROM word. */
-+	shift_out_bits(padapter, data, 16);
-+
-+	if (wait_eeprom_cmd_done(padapter) == _FALSE)
-+
-+		goto exit;
-+
-+	standby(padapter);
-+
-+	shift_out_bits(padapter, EEPROM_EWDS_OPCODE, 5);
-+	shift_out_bits(padapter, reg, 4);
-+
-+	eeprom_clean(padapter);
-+exit:
-+	return;
-+}
-+
-+u16 eeprom_read16(_adapter *padapter, u16 reg)  /* ReadEEprom */
-+{
-+
-+	u16 x;
-+	u16 data = 0;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		goto out;
-+	}
-+	/* select EEPROM, reset bits, set _EECS */
-+	x = rtw_read8(padapter, EE_9346CR);
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		goto out;
-+	}
-+
-+	x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
-+	x |= _EEM1 | _EECS;
-+	rtw_write8(padapter, EE_9346CR, (unsigned char)x);
-+
-+	/* write the read opcode and register number in that order */
-+	/* The opcode is 3bits in length, reg is 6 bits long */
-+	shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
-+	shift_out_bits(padapter, reg, padapter->EepromAddressSize);
-+
-+	/* Now read the data (16 bits) in from the selected EEPROM word */
-+	data = shift_in_bits(padapter);
-+
-+	eeprom_clean(padapter);
-+out:
-+
-+	return data;
-+
-+
-+}
-+
-+
-+
-+
-+/* From even offset */
-+void eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz)
-+{
-+
-+	u16 x, data16;
-+	u32 i;
-+	if (rtw_is_surprise_removed(padapter)) {
-+		goto out;
-+	}
-+	/* select EEPROM, reset bits, set _EECS */
-+	x = rtw_read8(padapter, EE_9346CR);
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		goto out;
-+	}
-+
-+	x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
-+	x |= _EEM1 | _EECS;
-+	rtw_write8(padapter, EE_9346CR, (unsigned char)x);
-+
-+	/* write the read opcode and register number in that order */
-+	/* The opcode is 3bits in length, reg is 6 bits long */
-+	shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
-+	shift_out_bits(padapter, reg, padapter->EepromAddressSize);
-+
-+
-+	for (i = 0; i < sz; i += 2) {
-+		data16 = shift_in_bits(padapter);
-+		data[i] = data16 & 0xff;
-+		data[i + 1] = data16 >> 8;
-+	}
-+
-+	eeprom_clean(padapter);
-+out:
-+	return;
-+}
-+
-+
-+/* addr_off : address offset of the entry in eeprom (not the tuple number of eeprom (reg); that is addr_off !=reg) */
-+u8 eeprom_read(_adapter *padapter, u32 addr_off, u8 sz, u8 *rbuf)
-+{
-+	u8 quotient, remainder, addr_2align_odd;
-+	u16 reg, stmp , i = 0, idx = 0;
-+	reg = (u16)(addr_off >> 1);
-+	addr_2align_odd = (u8)(addr_off & 0x1);
-+
-+	if (addr_2align_odd) { /* read that start at high part: e.g  1,3,5,7,9,... */
-+		stmp = eeprom_read16(padapter, reg);
-+		rbuf[idx++] = (u8)((stmp >> 8) & 0xff); /* return hogh-part of the short */
-+		reg++;
-+		sz--;
-+	}
-+
-+	quotient = sz >> 1;
-+	remainder = sz & 0x1;
-+
-+	for (i = 0 ; i < quotient; i++) {
-+		stmp = eeprom_read16(padapter, reg + i);
-+		rbuf[idx++] = (u8)(stmp & 0xff);
-+		rbuf[idx++] = (u8)((stmp >> 8) & 0xff);
-+	}
-+
-+	reg = reg + i;
-+	if (remainder) { /* end of read at lower part of short : 0,2,4,6,... */
-+		stmp = eeprom_read16(padapter, reg);
-+		rbuf[idx] = (u8)(stmp & 0xff);
-+	}
-+	return _TRUE;
-+}
-+
-+
-+
-+void read_eeprom_content(_adapter	*padapter)
-+{
-+
-+
-+
-+}
-diff --git a/drivers/staging/rtl8723cs/core/rtw_ft.c b/drivers/staging/rtl8723cs/core/rtw_ft.c
-new file mode 100644
-index 000000000000..1ba55ce74a9d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_ft.c
-@@ -0,0 +1,668 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#ifdef CONFIG_RTW_80211R
-+
-+#ifndef RTW_FT_DBG
-+	#define RTW_FT_DBG	0
-+#endif
-+#if RTW_FT_DBG
-+	#define RTW_FT_INFO(fmt, arg...)	\
-+		RTW_INFO(fmt, arg)
-+	#define RTW_FT_DUMP(str, data, len)	\
-+		RTW_INFO_DUMP(str, data, len)
-+#else
-+	#define RTW_FT_INFO(fmt, arg...) do {} while (0)
-+	#define RTW_FT_DUMP(str, data, len) do {} while (0)
-+#endif
-+
-+void rtw_ft_info_init(struct ft_roam_info *pft)
-+{
-+	_rtw_memset(pft, 0, sizeof(struct ft_roam_info));
-+	pft->ft_flags = 0
-+		| RTW_FT_EN
-+	/*	| RTW_FT_OTD_EN */
-+#ifdef CONFIG_RTW_BTM_ROAM
-+		| RTW_FT_BTM_ROAM
-+#endif
-+		;
-+	pft->ft_updated_bcn = _FALSE;
-+	RTW_FT_INFO("%s : ft_flags=0x%02x\n", __func__, pft->ft_flags);
-+}
-+
-+ssize_t rtw_ft_proc_flags_set(struct file *file,
-+	const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	char tmp[32];
-+	u8 flags;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%hhx", &flags);
-+		if (num == 1)
-+			adapter->mlmepriv.ft_roam.ft_flags = flags;
-+	}
-+
-+	return count;
-+
-+}
-+
-+int rtw_ft_proc_flags_get(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m, "0x%02x\n", adapter->mlmepriv.ft_roam.ft_flags);
-+
-+	return 0;
-+}
-+
-+u8 rtw_ft_chk_roaming_candidate(
-+	_adapter *padapter, struct wlan_network *competitor)
-+{
-+	u8 *pmdie;
-+	u32 mdie_len = 0;
-+	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
-+
-+	if (!(pmdie = rtw_get_ie(&competitor->network.IEs[12],
-+			_MDIE_, &mdie_len, competitor->network.IELength-12))) {
-+		RTW_INFO("FT : MDIE not foud in competitor!\n");
-+		return _FALSE;
-+	}	
-+
-+	if (!_rtw_memcmp(&pft_roam->mdid, (pmdie+2), 2)) {
-+		RTW_INFO("FT : unmatched MDIE!\n");
-+		return _FALSE;
-+	}
-+
-+	/*The candidate don't support over-the-DS*/
-+	if (rtw_ft_valid_otd_candidate(padapter, pmdie)) {
-+		RTW_INFO("FT: ignore the candidate("
-+			MAC_FMT ") for over-the-DS\n", 
-+			MAC_ARG(competitor->network.MacAddress));
-+		/*	rtw_ft_clr_flags(padapter, RTW_FT_PEER_OTD_EN); */
-+		return _FALSE;	
-+	}
-+
-+	if (rtw_ft_chk_flags(padapter, RTW_FT_TEST_RSSI_ROAM)) {
-+		if (!_rtw_memcmp(padapter->mlmepriv.cur_network.network.MacAddress, 
-+			competitor->network.MacAddress, ETH_ALEN) ) {
-+			competitor->network.Rssi +=20;
-+			RTW_FT_INFO("%s : update "MAC_FMT" RSSI to %d for RTW_FT_TEST_RSSI_ROAM\n",
-+				__func__, MAC_ARG(competitor->network.MacAddress),
-+				(int)competitor->network.Rssi);
-+			rtw_ft_clr_flags(padapter, RTW_FT_TEST_RSSI_ROAM);
-+		}
-+	}	
-+
-+	return _TRUE;
-+}
-+
-+void rtw_ft_update_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
-+{
-+	struct sta_priv		*pstapriv = &padapter->stapriv;
-+	struct sta_info		*psta = NULL;
-+
-+	psta = rtw_get_stainfo(pstapriv, pnetwork->MacAddress);
-+	if (psta == NULL)
-+		psta = rtw_alloc_stainfo(pstapriv, pnetwork->MacAddress);
-+
-+	if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {
-+
-+		padapter->securitypriv.binstallGrpkey = _FALSE;
-+		padapter->securitypriv.busetkipkey = _FALSE;
-+		padapter->securitypriv.bgrpkey_handshake = _FALSE;
-+
-+		psta->ieee8021x_blocked = _TRUE;
-+		psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
-+
-+		_rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype));
-+		_rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype));
-+		_rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype));
-+	}
-+
-+}
-+
-+void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct stassoc_event *pstassoc = (struct stassoc_event *)pbuf;
-+	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network);
-+	struct cfg80211_ft_event_params ft_evt_parms;
-+	_irqL irqL;
-+
-+	_rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms));
-+	rtw_ft_update_stainfo(padapter, pnetwork);
-+	ft_evt_parms.ies_len = pft_roam->ft_event.ies_len;
-+	ft_evt_parms.ies =  rtw_zmalloc(ft_evt_parms.ies_len);
-+	if (ft_evt_parms.ies)
-+		_rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len);
-+	 else
-+		goto err_2;
-+
-+	ft_evt_parms.target_ap = rtw_zmalloc(ETH_ALEN);
-+	if (ft_evt_parms.target_ap)
-+		_rtw_memcpy((void *)ft_evt_parms.target_ap, pstassoc->macaddr, ETH_ALEN);
-+	else
-+		goto err_1;
-+
-+	ft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies;
-+	ft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len;
-+
-+	/* It's a KERNEL issue between v4.11 ~ v4.16, 
-+	* <= v4.10, NLMSG_DEFAULT_SIZE is used for nlmsg_new().
-+	* v4.11 ~ v4.16, only used "100 + >ric_ies_len" for nlmsg_new() 
-+	*	even then DRIVER don't support RIC.
-+	* >= v4.17, issue should correct as "100 + ies_len + ric_ies_len".
-+	*/	
-+	#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)) && \
-+	(LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0)))
-+		if (!ft_evt_parms.ric_ies_len)
-+			ft_evt_parms.ric_ies_len = ft_evt_parms.ies_len;
-+		else 
-+			ft_evt_parms.ric_ies_len += ft_evt_parms.ies_len;	
-+	#endif	
-+	
-+	rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL);
-+	rtw_cfg80211_ft_event(padapter, &ft_evt_parms);
-+	RTW_INFO("%s: to "MAC_FMT"\n", __func__, MAC_ARG(ft_evt_parms.target_ap));
-+
-+	rtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN);
-+err_1:
-+	rtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len);
-+err_2:
-+	return;
-+}
-+
-+void rtw_ft_validate_akm_type(_adapter  *padapter,
-+	struct wlan_network *pnetwork)
-+{
-+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
-+	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
-+	u32 tmp_len;
-+	u8 *ptmp;
-+
-+	/*IEEE802.11-2012 Std. Table 8-101-AKM suite selectors*/
-+	if (rtw_ft_valid_akm(padapter, psecuritypriv->rsn_akm_suite_type)) {
-+		ptmp = rtw_get_ie(&pnetwork->network.IEs[12], 
-+				_MDIE_, &tmp_len, (pnetwork->network.IELength-12));
-+		if (ptmp) {
-+			pft_roam->mdid = *(u16 *)(ptmp+2);
-+			pft_roam->ft_cap = *(ptmp+4);
-+
-+			RTW_INFO("FT: target " MAC_FMT " mdid=(0x%2x), capacity=(0x%2x)\n", 
-+				MAC_ARG(pnetwork->network.MacAddress), pft_roam->mdid, pft_roam->ft_cap);
-+			rtw_ft_set_flags(padapter, RTW_FT_PEER_EN);
-+			RTW_FT_INFO("%s : peer support FTOTA(0x%02x)\n", __func__, pft_roam->ft_flags);
-+
-+			if (rtw_ft_otd_roam_en(padapter)) {
-+				rtw_ft_set_flags(padapter, RTW_FT_PEER_OTD_EN);
-+				RTW_FT_INFO("%s : peer support FTOTD(0x%02x)\n", __func__, pft_roam->ft_flags);
-+			}
-+		} else {
-+			/* Don't use FT roaming if target AP cannot support FT */
-+			rtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN));
-+			rtw_ft_reset_status(padapter);
-+		}
-+	} else {
-+		/* It could be a non-FT connection */
-+		rtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN));
-+		rtw_ft_reset_status(padapter);
-+	}	
-+
-+	RTW_FT_INFO("%s : ft_flags=0x%02x\n", __func__, pft_roam->ft_flags);
-+}
-+
-+void rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	uint len = precv_frame->u.hdr.len;
-+	WLAN_BSSID_EX *pbss;
-+
-+	if (rtw_ft_chk_status(padapter,RTW_FT_ASSOCIATED_STA) 
-+		&& (pmlmepriv->ft_roam.ft_updated_bcn == _FALSE)) {
-+		pbss = (WLAN_BSSID_EX*)rtw_malloc(sizeof(WLAN_BSSID_EX));
-+		if (pbss) {
-+			if (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) {
-+				struct beacon_keys recv_beacon;
-+
-+				update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE);
-+				/* Move into rtw_get_bcn_keys */
-+				/* rtw_get_bcn_info(&(pmlmepriv->cur_network)); */
-+				
-+				/* update bcn keys */
-+				if (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) {
-+					RTW_FT_INFO("%s: beacon keys ready\n", __func__);
-+					_rtw_memcpy(&pmlmepriv->cur_beacon_keys,
-+						&recv_beacon, sizeof(recv_beacon));
-+					if (is_hidden_ssid(recv_beacon.ssid, recv_beacon.ssid_len)) {
-+						_rtw_memcpy(pmlmepriv->cur_beacon_keys.ssid, pmlmeinfo->network.Ssid.Ssid, IW_ESSID_MAX_SIZE);
-+						pmlmepriv->cur_beacon_keys.ssid_len = pmlmeinfo->network.Ssid.SsidLength;
-+					}
-+				} else {
-+					RTW_ERR("%s: get beacon keys failed\n", __func__);
-+					_rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon));
-+				}
-+				#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
-+				pmlmepriv->new_beacon_cnts = 0;
-+				#endif
-+			}
-+			rtw_mfree((u8*)pbss, sizeof(WLAN_BSSID_EX));
-+		}
-+
-+		/* check the vendor of the assoc AP */
-+		pmlmeinfo->assoc_AP_vendor = 	
-+			check_assoc_AP(pframe+sizeof(struct rtw_ieee80211_hdr_3addr),
-+				(len - sizeof(struct rtw_ieee80211_hdr_3addr)));
-+
-+		/* update TSF Value */
-+		update_TSF(pmlmeext, pframe, len);
-+		pmlmeext->bcn_cnt = 0;
-+		pmlmeext->last_bcn_cnt = 0;
-+		pmlmepriv->ft_roam.ft_updated_bcn = _TRUE;
-+	}
-+}
-+
-+void rtw_ft_start_clnt_join(_adapter *padapter)
-+{
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct	mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
-+
-+	if (rtw_ft_otd_roam(padapter)) {
-+		pmlmeinfo->state = WIFI_FW_AUTH_SUCCESS | WIFI_FW_STATION_STATE;
-+		pft_roam->ft_event.ies =
-+			(pft_roam->ft_action + sizeof(struct rtw_ieee80211_hdr_3addr) + 16);
-+		pft_roam->ft_event.ies_len =
-+			(pft_roam->ft_action_len - sizeof(struct rtw_ieee80211_hdr_3addr));
-+
-+		/*Not support RIC*/
-+		pft_roam->ft_event.ric_ies =  NULL;
-+		pft_roam->ft_event.ric_ies_len = 0;
-+		rtw_ft_report_evt(padapter);
-+		return;
-+	}
-+
-+	pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE;
-+	start_clnt_auth(padapter);
-+}
-+
-+u8 rtw_ft_update_rsnie(
-+	_adapter *padapter, u8 bwrite, 
-+	struct pkt_attrib *pattrib, u8 **pframe)
-+{
-+	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
-+	u8 *pie;
-+	u32 len;
-+
-+	pie = rtw_get_ie(pft_roam->updated_ft_ies, EID_WPA2, &len, 
-+			pft_roam->updated_ft_ies_len);
-+
-+	if (!bwrite)
-+		return (pie)?_SUCCESS:_FAIL;
-+	
-+	if (pie) {
-+		*pframe = rtw_set_ie(((u8 *)*pframe), EID_WPA2, len, 
-+						pie+2, &(pattrib->pktlen));
-+	} else
-+		return _FAIL;
-+
-+	return _SUCCESS;	
-+}
-+
-+static u8 rtw_ft_update_mdie(
-+	_adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe)
-+{
-+	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
-+	u8 *pie, mdie[3];
-+	u32 len = 3;
-+
-+	if (rtw_ft_roam(padapter)) {
-+		if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _MDIE_, 
-+				&len, pft_roam->updated_ft_ies_len))) {
-+			pie = (pie + 2); /* ignore md-id & length */
-+		} else 
-+			return _FAIL;
-+	} else {
-+		*((u16 *)&mdie[0]) = pft_roam->mdid;
-+		mdie[2] = pft_roam->ft_cap;
-+		pie = &mdie[0];
-+	}
-+
-+	*pframe = rtw_set_ie(((u8 *)*pframe), _MDIE_, len , pie, &(pattrib->pktlen));
-+	return _SUCCESS;	
-+}
-+
-+static u8 rtw_ft_update_ftie(
-+	_adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe)
-+{
-+	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
-+	u8 *pie;
-+	u32 len;
-+
-+	if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _FTIE_, &len, 
-+				pft_roam->updated_ft_ies_len)) != NULL) {
-+		*pframe = rtw_set_ie(*pframe, _FTIE_, len , 
-+					(pie+2), &(pattrib->pktlen));
-+	} else
-+		return _FAIL;
-+
-+	return _SUCCESS;	
-+}
-+
-+void rtw_ft_build_auth_req_ies(_adapter *padapter, 
-+	struct pkt_attrib *pattrib, u8 **pframe)
-+{
-+	u8 ftie_append = _TRUE;
-+
-+	if (!pattrib || !(*pframe))
-+		return;
-+
-+	if (!rtw_ft_roam(padapter))
-+		return;
-+
-+	ftie_append = rtw_ft_update_rsnie(padapter, _TRUE, pattrib, pframe);
-+	rtw_ft_update_mdie(padapter, pattrib, pframe);
-+	if (ftie_append)
-+		rtw_ft_update_ftie(padapter, pattrib, pframe);
-+}
-+
-+void rtw_ft_build_assoc_req_ies(_adapter *padapter, 
-+	u8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe)
-+{
-+	if (!pattrib || !(*pframe))
-+		return;
-+
-+	if (rtw_ft_chk_flags(padapter, RTW_FT_PEER_EN))
-+		rtw_ft_update_mdie(padapter, pattrib, pframe);
-+
-+	if ((!is_reassoc) || (!rtw_ft_roam(padapter)))
-+		return;
-+
-+	if (rtw_ft_update_rsnie(padapter, _FALSE, pattrib, pframe))
-+		rtw_ft_update_ftie(padapter, pattrib, pframe);	
-+}
-+
-+u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len)
-+{
-+	u8 ret = _SUCCESS;
-+	u8 target_ap_addr[ETH_ALEN] = {0};
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
-+
-+	if (!rtw_ft_roam(padapter))
-+		return _FAIL;
-+
-+	/*rtw_ft_report_reassoc_evt already,
-+	 * and waiting for cfg80211_rtw_update_ft_ies */
-+	if (rtw_ft_authed_sta(padapter))
-+		return ret;
-+
-+	if (!pframe || !len)
-+		return _FAIL;
-+	
-+	rtw_buf_update(&pmlmepriv->auth_rsp, 
-+		&pmlmepriv->auth_rsp_len, pframe, len);
-+	pft_roam->ft_event.ies =
-+		(pmlmepriv->auth_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6);
-+	pft_roam->ft_event.ies_len =
-+		(pmlmepriv->auth_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6);
-+
-+	/*Not support RIC*/
-+	pft_roam->ft_event.ric_ies =  NULL;
-+	pft_roam->ft_event.ric_ies_len =  0;
-+	_rtw_memcpy(target_ap_addr, pmlmepriv->assoc_bssid, ETH_ALEN);
-+	rtw_ft_report_reassoc_evt(padapter, target_ap_addr);
-+
-+	return ret;	
-+}
-+
-+static void rtw_ft_start_clnt_action(_adapter *padapter, u8 *pTargetAddr)
-+{
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+
-+	rtw_ft_set_status(padapter, RTW_FT_REQUESTING_STA);
-+	rtw_ft_issue_action_req(padapter, pTargetAddr);
-+	_set_timer(&pmlmeext->ft_link_timer, REASSOC_TO);
-+}
-+
-+void rtw_ft_start_roam(_adapter *padapter, u8 *pTargetAddr)
-+{
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+
-+	if (rtw_ft_otd_roam(padapter)) {
-+		RTW_FT_INFO("%s : try OTD roaming\n", __func__);
-+		rtw_ft_start_clnt_action(padapter, pTargetAddr);
-+	} else {
-+		/*wait a little time to retrieve packets buffered in the current ap while scan*/
-+		RTW_FT_INFO("%s : start roaming timer\n", __func__);
-+		_set_timer(&pmlmeext->ft_roam_timer, 30);
-+	}
-+}
-+
-+void rtw_ft_issue_action_req(_adapter *padapter, u8 *pTargetAddr)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct xmit_frame *pmgntframe;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	struct pkt_attrib *pattrib;
-+	u8 *pframe;
-+	u8 category = RTW_WLAN_CATEGORY_FT;
-+	u8 action = RTW_WLAN_ACTION_FT_REQ;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+	pwlanhdr->frame_ctl = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+
-+	_rtw_memcpy(pframe, adapter_mac_addr(padapter), ETH_ALEN);
-+	pframe += ETH_ALEN;
-+	pattrib->pktlen += ETH_ALEN;
-+
-+	_rtw_memcpy(pframe, pTargetAddr, ETH_ALEN);
-+	pframe += ETH_ALEN;
-+	pattrib->pktlen += ETH_ALEN;
-+
-+	rtw_ft_update_mdie(padapter, pattrib, &pframe);
-+	if (rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe))
-+		rtw_ft_update_ftie(padapter, pattrib, &pframe);
-+
-+	RTW_INFO("FT : issue RTW_WLAN_ACTION_FT_REQ\n");
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+	dump_mgntframe(padapter, pmgntframe);
-+}
-+
-+void rtw_ft_report_evt(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network);
-+	struct cfg80211_ft_event_params ft_evt_parms;
-+	_irqL irqL;
-+
-+	_rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms));
-+	rtw_ft_update_stainfo(padapter, pnetwork);
-+
-+	if (!pnetwork)
-+		goto err_2;
-+
-+	ft_evt_parms.ies_len = pft_roam->ft_event.ies_len;
-+	ft_evt_parms.ies =  rtw_zmalloc(ft_evt_parms.ies_len);
-+	if (ft_evt_parms.ies)
-+		_rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len);
-+	 else
-+		goto err_2;
-+
-+	ft_evt_parms.target_ap = rtw_zmalloc(ETH_ALEN);
-+	if (ft_evt_parms.target_ap)
-+		_rtw_memcpy((void *)ft_evt_parms.target_ap, pnetwork->MacAddress, ETH_ALEN);
-+	else
-+		goto err_1;
-+
-+	ft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies;
-+	ft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len;
-+
-+	/* It's a KERNEL issue between v4.11 ~ v4.16, 
-+	* <= v4.10, NLMSG_DEFAULT_SIZE is used for nlmsg_new().
-+	* v4.11 ~ v4.16, only used "100 + >ric_ies_len" for nlmsg_new() 
-+	*	even then DRIVER don't support RIC.
-+	* >= v4.17, issue should correct as "100 + ies_len + ric_ies_len".
-+	*/	
-+	#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)) && \
-+	(LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0)))
-+		ft_evt_parms.ric_ies_len = (ft_evt_parms.ies_len <= 100 )?
-+			(0):(ft_evt_parms.ies_len - 100);
-+	#endif
-+	
-+	rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL);
-+	rtw_cfg80211_ft_event(padapter, &ft_evt_parms);
-+	RTW_INFO("FT: rtw_ft_report_evt\n");
-+	rtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN);
-+err_1:
-+	rtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len);
-+err_2:
-+	return;
-+}
-+
-+void rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr)
-+{
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+	struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
-+	struct cmd_obj *pcmd_obj = NULL;
-+	struct stassoc_event *passoc_sta_evt = NULL;
-+	struct rtw_evt_header *evt_hdr = NULL;
-+	u8 *pevtcmd = NULL;
-+	u32 cmdsz = 0;
-+
-+	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (pcmd_obj == NULL)
-+		return;
-+
-+	cmdsz = (sizeof(struct stassoc_event) + sizeof(struct rtw_evt_header));
-+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
-+	if (pevtcmd == NULL) {
-+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
-+		return;
-+	}
-+
-+	_rtw_init_listhead(&pcmd_obj->list);
-+	pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
-+	pcmd_obj->cmdsz = cmdsz;
-+	pcmd_obj->parmbuf = pevtcmd;
-+	pcmd_obj->rsp = NULL;
-+	pcmd_obj->rspsz  = 0;
-+
-+	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
-+	evt_hdr->len = sizeof(struct stassoc_event);
-+	evt_hdr->id = EVT_FT_REASSOC;
-+	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
-+
-+	passoc_sta_evt = (struct stassoc_event *)(pevtcmd + sizeof(struct rtw_evt_header));
-+	_rtw_memcpy((unsigned char *)(&(passoc_sta_evt->macaddr)), pMacAddr, ETH_ALEN);
-+	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
-+}
-+
-+void rtw_ft_link_timer_hdl(void *ctx)
-+{
-+	_adapter *padapter = (_adapter *)ctx;
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
-+
-+	if (rtw_ft_chk_status(padapter, RTW_FT_REQUESTING_STA)) {
-+		if (pft_roam->ft_req_retry_cnt < RTW_FT_ACTION_REQ_LMT) {
-+			pft_roam->ft_req_retry_cnt++;
-+			rtw_ft_issue_action_req(padapter, (u8 *)pmlmepriv->roam_network->network.MacAddress);
-+			_set_timer(&pmlmeext->ft_link_timer, REASSOC_TO);
-+		} else {
-+			pft_roam->ft_req_retry_cnt = 0;	
-+			if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
-+				rtw_ft_set_status(padapter, RTW_FT_ASSOCIATED_STA);
-+			else
-+				rtw_ft_reset_status(padapter);
-+		}
-+	}
-+}
-+
-+void rtw_ft_roam_timer_hdl(void *ctx)
-+{
-+	_adapter *padapter = (_adapter *)ctx;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	RTW_FT_INFO("%s : try roaming\n", __func__);
-+	receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress
-+				, WLAN_REASON_ACTIVE_ROAM, _FALSE);
-+}
-+
-+void rtw_ft_roam_status_reset(_adapter *padapter)
-+{
-+	struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
-+
-+	if ((rtw_to_roam(padapter) > 0) && 
-+		(!rtw_ft_chk_status(padapter, RTW_FT_REQUESTED_STA))) {
-+		rtw_ft_reset_status(padapter);
-+	}	
-+	
-+	padapter->mlmepriv.ft_roam.ft_updated_bcn = _FALSE;
-+}
-+
-+#endif /* CONFIG_RTW_80211R */
-diff --git a/drivers/staging/rtl8723cs/core/rtw_ieee80211.c b/drivers/staging/rtl8723cs/core/rtw_ieee80211.c
-new file mode 100644
-index 000000000000..d37273216a31
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_ieee80211.c
-@@ -0,0 +1,3166 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _IEEE80211_C
-+
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+	#include <linux/fs.h>
-+#endif
-+#include <drv_types.h>
-+#include <linux/rfkill.h>
-+
-+u8 RTW_WPA_OUI_TYPE[] = { 0x00, 0x50, 0xf2, 1 };
-+u16 RTW_WPA_VERSION = 1;
-+u8 WPA_AUTH_KEY_MGMT_NONE[] = { 0x00, 0x50, 0xf2, 0 };
-+u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x50, 0xf2, 1 };
-+u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x50, 0xf2, 2 };
-+u8 WPA_CIPHER_SUITE_NONE[] = { 0x00, 0x50, 0xf2, 0 };
-+u8 WPA_CIPHER_SUITE_WEP40[] = { 0x00, 0x50, 0xf2, 1 };
-+u8 WPA_CIPHER_SUITE_TKIP[] = { 0x00, 0x50, 0xf2, 2 };
-+u8 WPA_CIPHER_SUITE_WRAP[] = { 0x00, 0x50, 0xf2, 3 };
-+u8 WPA_CIPHER_SUITE_CCMP[] = { 0x00, 0x50, 0xf2, 4 };
-+u8 WPA_CIPHER_SUITE_WEP104[] = { 0x00, 0x50, 0xf2, 5 };
-+
-+u16 RSN_VERSION_BSD = 1;
-+u8 RSN_CIPHER_SUITE_NONE[] = { 0x00, 0x0f, 0xac, 0 };
-+u8 RSN_CIPHER_SUITE_WEP40[] = { 0x00, 0x0f, 0xac, 1 };
-+u8 RSN_CIPHER_SUITE_TKIP[] = { 0x00, 0x0f, 0xac, 2 };
-+u8 RSN_CIPHER_SUITE_WRAP[] = { 0x00, 0x0f, 0xac, 3 };
-+u8 RSN_CIPHER_SUITE_CCMP[] = { 0x00, 0x0f, 0xac, 4 };
-+u8 RSN_CIPHER_SUITE_AES_128_CMAC[] = { 0x00, 0x0f, 0xac, 6 };
-+u8 RSN_CIPHER_SUITE_GCMP[] = { 0x00, 0x0f, 0xac, 8 };
-+u8 RSN_CIPHER_SUITE_GCMP_256[] = { 0x00, 0x0f, 0xac, 9 };
-+u8 RSN_CIPHER_SUITE_CCMP_256[] = { 0x00, 0x0f, 0xac, 10 };
-+u8 RSN_CIPHER_SUITE_BIP_GMAC_128[] = { 0x00, 0x0f, 0xac, 11 };
-+u8 RSN_CIPHER_SUITE_BIP_GMAC_256[] = { 0x00, 0x0f, 0xac, 12 };
-+u8 RSN_CIPHER_SUITE_BIP_CMAC_256[] = { 0x00, 0x0f, 0xac, 13 };
-+u8 RSN_CIPHER_SUITE_WEP104[] = { 0x00, 0x0f, 0xac, 5 };
-+
-+u8 WLAN_AKM_8021X[] = {0x00, 0x0f, 0xac, 1};
-+u8 WLAN_AKM_PSK[] = {0x00, 0x0f, 0xac, 2};
-+u8 WLAN_AKM_FT_8021X[] = {0x00, 0x0f, 0xac, 3};
-+u8 WLAN_AKM_FT_PSK[] = {0x00, 0x0f, 0xac, 4};
-+u8 WLAN_AKM_8021X_SHA256[] = {0x00, 0x0f, 0xac, 5};
-+u8 WLAN_AKM_PSK_SHA256[] = {0x00, 0x0f, 0xac, 6};
-+u8 WLAN_AKM_TDLS[] = {0x00, 0x0f, 0xac, 7};
-+u8 WLAN_AKM_SAE[] = {0x00, 0x0f, 0xac, 8};
-+u8 WLAN_AKM_FT_OVER_SAE[] = {0x00, 0x0f, 0xac, 9};
-+u8 WLAN_AKM_8021X_SUITE_B[] = {0x00, 0x0f, 0xac, 11};
-+u8 WLAN_AKM_8021X_SUITE_B_192[] = {0x00, 0x0f, 0xac, 12};
-+u8 WLAN_AKM_FILS_SHA256[] = {0x00, 0x0f, 0xac, 14};
-+u8 WLAN_AKM_FILS_SHA384[] = {0x00, 0x0f, 0xac, 15};
-+u8 WLAN_AKM_FT_FILS_SHA256[] = {0x00, 0x0f, 0xac, 16};
-+u8 WLAN_AKM_FT_FILS_SHA384[] = {0x00, 0x0f, 0xac, 17};
-+/* -----------------------------------------------------------
-+ * for adhoc-master to generate ie and provide supported-rate to fw
-+ * ----------------------------------------------------------- */
-+
-+u8	WIFI_CCKRATES[] = {
-+	(IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK),
-+	(IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK),
-+	(IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK),
-+	(IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK)
-+};
-+
-+u8	WIFI_OFDMRATES[] = {
-+	(IEEE80211_OFDM_RATE_6MB),
-+	(IEEE80211_OFDM_RATE_9MB),
-+	(IEEE80211_OFDM_RATE_12MB),
-+	(IEEE80211_OFDM_RATE_18MB),
-+	(IEEE80211_OFDM_RATE_24MB),
-+	IEEE80211_OFDM_RATE_36MB,
-+	IEEE80211_OFDM_RATE_48MB,
-+	IEEE80211_OFDM_RATE_54MB
-+};
-+
-+const char *MGN_RATE_STR(enum MGN_RATE rate)
-+{
-+	u8 hw_rate;
-+
-+	if (rate == MGN_MCS32)
-+		return "MCS32";
-+
-+	hw_rate = MRateToHwRate(rate);
-+	if (hw_rate == DESC_RATE1M && rate != MGN_1M)
-+		hw_rate = DESC_RATE_NUM; /* invalid case */
-+
-+	return HDATA_RATE(hw_rate);
-+}
-+
-+u8 mgn_rates_cck[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
-+u8 mgn_rates_ofdm[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};
-+u8 mgn_rates_mcs0_7[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7};
-+u8 mgn_rates_mcs8_15[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15};
-+u8 mgn_rates_mcs16_23[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23};
-+u8 mgn_rates_mcs24_31[8] = {MGN_MCS24, MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, MGN_MCS30, MGN_MCS31};
-+u8 mgn_rates_vht1ss[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4
-+	, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9
-+			  };
-+u8 mgn_rates_vht2ss[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4
-+	, MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9
-+			  };
-+u8 mgn_rates_vht3ss[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4
-+	, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9
-+			  };
-+u8 mgn_rates_vht4ss[10] = {MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4
-+	, MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9
-+			  };
-+
-+RATE_SECTION mgn_rate_to_rs(enum MGN_RATE rate)
-+{
-+	RATE_SECTION rs = RATE_SECTION_NUM;
-+
-+	if (IS_CCK_RATE(rate))
-+		rs = CCK;
-+	else if (IS_OFDM_RATE(rate))
-+		rs = OFDM;
-+	else if (IS_HT1SS_RATE(rate))
-+		rs = HT_1SS;
-+	else if (IS_HT2SS_RATE(rate))
-+		rs = HT_2SS;
-+	else if (IS_HT3SS_RATE(rate))
-+		rs = HT_3SS;
-+	else if (IS_HT4SS_RATE(rate))
-+		rs = HT_4SS;
-+	else if (IS_VHT1SS_RATE(rate))
-+		rs = VHT_1SS;
-+	else if (IS_VHT2SS_RATE(rate))
-+		rs = VHT_2SS;
-+	else if (IS_VHT3SS_RATE(rate))
-+		rs = VHT_3SS;
-+	else if (IS_VHT4SS_RATE(rate))
-+		rs = VHT_4SS;
-+
-+	return rs;
-+}
-+
-+static const char *const _rate_section_str[] = {
-+	"CCK",
-+	"OFDM",
-+	"HT_1SS",
-+	"HT_2SS",
-+	"HT_3SS",
-+	"HT_4SS",
-+	"VHT_1SS",
-+	"VHT_2SS",
-+	"VHT_3SS",
-+	"VHT_4SS",
-+	"RATE_SECTION_UNKNOWN",
-+};
-+
-+const char *rate_section_str(u8 section)
-+{
-+	section = (section >= RATE_SECTION_NUM) ? RATE_SECTION_NUM : section;
-+	return _rate_section_str[section];
-+}
-+
-+struct rate_section_ent rates_by_sections[RATE_SECTION_NUM] = {
-+	{RF_1TX, 4, mgn_rates_cck},
-+	{RF_1TX, 8, mgn_rates_ofdm},
-+	{RF_1TX, 8, mgn_rates_mcs0_7},
-+	{RF_2TX, 8, mgn_rates_mcs8_15},
-+	{RF_3TX, 8, mgn_rates_mcs16_23},
-+	{RF_4TX, 8, mgn_rates_mcs24_31},
-+	{RF_1TX, 10, mgn_rates_vht1ss},
-+	{RF_2TX, 10, mgn_rates_vht2ss},
-+	{RF_3TX, 10, mgn_rates_vht3ss},
-+	{RF_4TX, 10, mgn_rates_vht4ss},
-+};
-+
-+int rtw_get_bit_value_from_ieee_value(u8 val)
-+{
-+	unsigned char dot11_rate_table[] = {2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108, 0}; /* last element must be zero!! */
-+
-+	int i = 0;
-+	while (dot11_rate_table[i] != 0) {
-+		if (dot11_rate_table[i] == val)
-+			return BIT(i);
-+		i++;
-+	}
-+	return 0;
-+}
-+uint rtw_get_cckrate_size(u8 *rate, u32 rate_length)
-+{
-+	int i = 0;
-+	while(i < rate_length){
-+		RTW_DBG("%s, rate[%d]=%u\n", __FUNCTION__, i, rate[i]);
-+		if (((rate[i] & 0x7f) == 2) || ((rate[i] & 0x7f) == 4) ||
-+			((rate[i] & 0x7f) == 11)  || ((rate[i] & 0x7f) == 22))
-+			i++;
-+		else
-+			break;
-+	}
-+	return i;
-+}
-+
-+uint	rtw_is_cckrates_included(u8 *rate)
-+{
-+	u32	i = 0;
-+
-+	while (rate[i] != 0) {
-+		if ((((rate[i]) & 0x7f) == 2)	|| (((rate[i]) & 0x7f) == 4) ||
-+		    (((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22))
-+			return _TRUE;
-+		i++;
-+	}
-+
-+	return _FALSE;
-+}
-+
-+uint	rtw_is_cckratesonly_included(u8 *rate)
-+{
-+	u32 i = 0;
-+
-+
-+	while (rate[i] != 0) {
-+		if ((((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&
-+		    (((rate[i]) & 0x7f) != 11)  && (((rate[i]) & 0x7f) != 22))
-+			return _FALSE;
-+
-+		i++;
-+	}
-+
-+	return _TRUE;
-+
-+}
-+
-+int rtw_check_network_type(unsigned char *rate, int ratelen, int channel)
-+{
-+	if (channel > 14) {
-+		if ((rtw_is_cckrates_included(rate)) == _TRUE)
-+			return WIRELESS_INVALID;
-+		else
-+			return WIRELESS_11A;
-+	} else { /* could be pure B, pure G, or B/G */
-+		if ((rtw_is_cckratesonly_included(rate)) == _TRUE)
-+			return WIRELESS_11B;
-+		else if ((rtw_is_cckrates_included(rate)) == _TRUE)
-+			return	WIRELESS_11BG;
-+		else
-+			return WIRELESS_11G;
-+	}
-+
-+}
-+
-+u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source,
-+		     unsigned int *frlen)
-+{
-+	_rtw_memcpy((void *)pbuf, (void *)source, len);
-+	*frlen = *frlen + len;
-+	return pbuf + len;
-+}
-+
-+/* rtw_set_ie will update frame length */
-+u8 *rtw_set_ie
-+(
-+	u8 *pbuf,
-+	sint index,
-+	uint len,
-+	const u8 *source,
-+	uint *frlen /* frame length */
-+)
-+{
-+	*pbuf = (u8)index;
-+
-+	*(pbuf + 1) = (u8)len;
-+
-+	if (len > 0)
-+		_rtw_memcpy((void *)(pbuf + 2), (void *)source, len);
-+
-+	if (frlen)
-+		*frlen = *frlen + (len + 2);
-+
-+	return pbuf + len + 2;
-+}
-+
-+inline u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode,
-+				u8 new_ch, u8 ch_switch_cnt)
-+{
-+	u8 ie_data[3];
-+
-+	ie_data[0] = ch_switch_mode;
-+	ie_data[1] = new_ch;
-+	ie_data[2] = ch_switch_cnt;
-+	return rtw_set_ie(buf, WLAN_EID_CHANNEL_SWITCH,  3, ie_data, buf_len);
-+}
-+
-+inline u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset)
-+{
-+	if (ch_offset == SCN)
-+		return HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	else if (ch_offset == SCA)
-+		return HAL_PRIME_CHNL_OFFSET_LOWER;
-+	else if (ch_offset == SCB)
-+		return HAL_PRIME_CHNL_OFFSET_UPPER;
-+
-+	return HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+}
-+
-+inline u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset)
-+{
-+	if (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
-+		return SCN;
-+	else if (ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
-+		return SCA;
-+	else if (ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
-+		return SCB;
-+
-+	return SCN;
-+}
-+
-+inline u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset)
-+{
-+	return rtw_set_ie(buf, WLAN_EID_SECONDARY_CHANNEL_OFFSET,  1, &secondary_ch_offset, buf_len);
-+}
-+
-+inline u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl,
-+		u8 flags, u16 reason, u16 precedence)
-+{
-+	u8 ie_data[6];
-+
-+	ie_data[0] = ttl;
-+	ie_data[1] = flags;
-+	RTW_PUT_LE16((u8 *)&ie_data[2], reason);
-+	RTW_PUT_LE16((u8 *)&ie_data[4], precedence);
-+
-+	return rtw_set_ie(buf, 0x118,  6, ie_data, buf_len);
-+}
-+
-+/*----------------------------------------------------------------------------
-+index: the information element id index, limit is the limit for search
-+-----------------------------------------------------------------------------*/
-+u8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit)
-+{
-+	sint tmp, i;
-+	const u8 *p;
-+	if (limit < 1) {
-+		return NULL;
-+	}
-+
-+	p = pbuf;
-+	i = 0;
-+	*len = 0;
-+	while (1) {
-+		if (*p == index) {
-+			*len = *(p + 1);
-+			return (u8 *)p;
-+		} else {
-+			tmp = *(p + 1);
-+			p += (tmp + 2);
-+			i += (tmp + 2);
-+		}
-+		if (i >= limit)
-+			break;
-+	}
-+	return NULL;
-+}
-+
-+/**
-+ * rtw_get_ie_ex - Search specific IE from a series of IEs
-+ * @in_ie: Address of IEs to search
-+ * @in_len: Length limit from in_ie
-+ * @eid: Element ID to match
-+ * @oui: OUI to match
-+ * @oui_len: OUI length
-+ * @ie: If not NULL and the specific IE is found, the IE will be copied to the buf starting from the specific IE
-+ * @ielen: If not NULL and the specific IE is found, will set to the length of the entire IE
-+ *
-+ * Returns: The address of the specific IE found, or NULL
-+ */
-+u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen)
-+{
-+	uint cnt;
-+	const u8 *target_ie = NULL;
-+
-+
-+	if (ielen)
-+		*ielen = 0;
-+
-+	if (!in_ie || in_len <= 0)
-+		return (u8 *)target_ie;
-+
-+	cnt = 0;
-+
-+	while (cnt < in_len) {
-+		if (eid == in_ie[cnt]
-+		    && (!oui || _rtw_memcmp(&in_ie[cnt + 2], oui, oui_len) == _TRUE)) {
-+			target_ie = &in_ie[cnt];
-+
-+			if (ie)
-+				_rtw_memcpy(ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
-+
-+			if (ielen)
-+				*ielen = in_ie[cnt + 1] + 2;
-+
-+			break;
-+		} else {
-+			cnt += in_ie[cnt + 1] + 2; /* goto next	 */
-+		}
-+
-+	}
-+
-+	return (u8 *)target_ie;
-+}
-+
-+/**
-+ * rtw_ies_remove_ie - Find matching IEs and remove
-+ * @ies: Address of IEs to search
-+ * @ies_len: Pointer of length of ies, will update to new length
-+ * @offset: The offset to start scarch
-+ * @eid: Element ID to match
-+ * @oui: OUI to match
-+ * @oui_len: OUI length
-+ *
-+ * Returns: _SUCCESS: ies is updated, _FAIL: not updated
-+ */
-+int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len)
-+{
-+	int ret = _FAIL;
-+	u8 *target_ie;
-+	u32 target_ielen;
-+	u8 *start;
-+	uint search_len;
-+
-+	if (!ies || !ies_len || *ies_len <= offset)
-+		goto exit;
-+
-+	start = ies + offset;
-+	search_len = *ies_len - offset;
-+
-+	while (1) {
-+		target_ie = rtw_get_ie_ex(start, search_len, eid, oui, oui_len, NULL, &target_ielen);
-+		if (target_ie && target_ielen) {
-+			u8 *remain_ies = target_ie + target_ielen;
-+			uint remain_len = search_len - (remain_ies - start);
-+
-+			_rtw_memmove(target_ie, remain_ies, remain_len);
-+			*ies_len = *ies_len - target_ielen;
-+			ret = _SUCCESS;
-+
-+			start = target_ie;
-+			search_len = remain_len;
-+		} else
-+			break;
-+	}
-+exit:
-+	return ret;
-+}
-+
-+void rtw_set_supported_rate(u8 *SupportedRates, uint mode)
-+{
-+
-+	_rtw_memset(SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX);
-+
-+	switch (mode) {
-+	case WIRELESS_11B:
-+		_rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN);
-+		break;
-+
-+	case WIRELESS_11G:
-+	case WIRELESS_11A:
-+	case WIRELESS_11_5N:
-+	case WIRELESS_11A_5N: /* Todo: no basic rate for ofdm ? */
-+	case WIRELESS_11_5AC:
-+		_rtw_memcpy(SupportedRates, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN);
-+		break;
-+
-+	case WIRELESS_11BG:
-+	case WIRELESS_11G_24N:
-+	case WIRELESS_11_24N:
-+	case WIRELESS_11BG_24N:
-+		_rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN);
-+		_rtw_memcpy(SupportedRates + IEEE80211_CCK_RATE_LEN, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN);
-+		break;
-+
-+	}
-+}
-+
-+void rtw_filter_suppport_rateie(WLAN_BSSID_EX *pbss_network, u8 keep)
-+{
-+	u8 i, idx = 0, new_rate[NDIS_802_11_LENGTH_RATES_EX], *p;
-+	uint iscck, isofdm, ie_orilen = 0, remain_len;
-+	u8 *remain_ies;
-+
-+	p = rtw_get_ie(pbss_network->IEs + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &ie_orilen, (pbss_network->IELength - _BEACON_IE_OFFSET_));
-+	if (!p)
-+		return;
-+
-+	_rtw_memset(new_rate, 0, NDIS_802_11_LENGTH_RATES_EX);
-+	for (i=0; i < ie_orilen; i++) {
-+		iscck = rtw_is_cck_rate(p[i+2]);
-+		isofdm= rtw_is_ofdm_rate(p[i+2]);
-+		if (((keep == CCK) && iscck)
-+			|| ((keep == OFDM) && isofdm))
-+			new_rate[idx++]= rtw_is_basic_rate_ofdm(p[i+2]) ? p[i+2]|IEEE80211_BASIC_RATE_MASK : p[i+2];
-+	}
-+	/*	update rate ie	*/
-+	p[1] = idx;
-+	_rtw_memcpy(p+2, new_rate, idx);
-+	/*	update remain ie & IELength*/
-+	remain_ies = p + 2 + ie_orilen;
-+	remain_len = pbss_network->IELength - (remain_ies - pbss_network->IEs);
-+	_rtw_memmove(p+2+idx, remain_ies, remain_len);
-+	pbss_network->IELength -= (ie_orilen - idx);
-+}
-+ 
-+
-+/*
-+	Adjust those items by given wireless_mode
-+		1. pbss_network->IELength
-+		2. pbss_network->IE (SUPPORTRATE & EXT_SUPPORTRATE)
-+		3. pbss_network->SupportedRates
-+*/
-+
-+u8 rtw_update_rate_bymode(WLAN_BSSID_EX *pbss_network, u32 mode)
-+{
-+	u8 network_type, *p, *ie = pbss_network->IEs;
-+	sint ie_len;
-+	uint network_ielen = pbss_network->IELength;
-+
-+	if (mode == WIRELESS_11B) {
-+		/*only keep CCK in support_rate IE and remove whole ext_support_rate IE*/
-+		rtw_filter_suppport_rateie(pbss_network, CCK);
-+		p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ie_len, pbss_network->IELength - _BEACON_IE_OFFSET_);
-+		if (p) {
-+			rtw_ies_remove_ie(ie , &network_ielen, _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, NULL, 0);
-+			pbss_network->IELength -= ie_len;
-+		}
-+		network_type = WIRELESS_11B;
-+	} else {
-+		if (pbss_network->Configuration.DSConfig > 14) {
-+			/* Remove CCK in support_rate IE */
-+			rtw_filter_suppport_rateie(pbss_network, OFDM);
-+			network_type = WIRELESS_11A;
-+		} else {
-+			if ((mode & WIRELESS_11B) == 0) {
-+				/* Remove CCK in support_rate IE */
-+				rtw_filter_suppport_rateie(pbss_network, OFDM);
-+				network_type = WIRELESS_11G;
-+			} else {
-+				network_type = WIRELESS_11BG;
-+			}
-+		}
-+	}
-+
-+	rtw_set_supported_rate(pbss_network->SupportedRates, network_type);
-+
-+	return network_type;
-+}
-+
-+uint	rtw_get_rateset_len(u8	*rateset)
-+{
-+	uint i = 0;
-+	while (1) {
-+		if ((rateset[i]) == 0)
-+			break;
-+
-+		if (i > 12)
-+			break;
-+
-+		i++;
-+	}
-+	return i;
-+}
-+
-+int rtw_generate_ie(struct registry_priv *pregistrypriv)
-+{
-+	u8	wireless_mode;
-+	int	sz = 0, rateLen;
-+	WLAN_BSSID_EX	*pdev_network = &pregistrypriv->dev_network;
-+	u8	*ie = pdev_network->IEs;
-+
-+
-+	/* timestamp will be inserted by hardware */
-+	sz += 8;
-+	ie += sz;
-+
-+	/* beacon interval : 2bytes */
-+	*(u16 *)ie = cpu_to_le16((u16)pdev_network->Configuration.BeaconPeriod); /* BCN_INTERVAL; */
-+	sz += 2;
-+	ie += 2;
-+
-+	/* capability info */
-+	*(u16 *)ie = 0;
-+
-+	*(u16 *)ie |= cpu_to_le16(cap_IBSS);
-+
-+	if (pregistrypriv->preamble == PREAMBLE_SHORT)
-+		*(u16 *)ie |= cpu_to_le16(cap_ShortPremble);
-+
-+	if (pdev_network->Privacy)
-+		*(u16 *)ie |= cpu_to_le16(cap_Privacy);
-+
-+	sz += 2;
-+	ie += 2;
-+
-+	/* SSID */
-+	ie = rtw_set_ie(ie, _SSID_IE_, pdev_network->Ssid.SsidLength, pdev_network->Ssid.Ssid, &sz);
-+
-+	/* supported rates */
-+	if (pregistrypriv->wireless_mode == WIRELESS_11ABGN) {
-+		if (pdev_network->Configuration.DSConfig > 14)
-+			wireless_mode = WIRELESS_11A_5N;
-+		else
-+			wireless_mode = WIRELESS_11BG_24N;
-+	} else if (pregistrypriv->wireless_mode == WIRELESS_MODE_MAX) { /* WIRELESS_11ABGN | WIRELESS_11AC */
-+		if (pdev_network->Configuration.DSConfig > 14)
-+			wireless_mode = WIRELESS_11_5AC;
-+		else
-+			wireless_mode = WIRELESS_11BG_24N;
-+	} else
-+		wireless_mode = pregistrypriv->wireless_mode;
-+
-+	rtw_set_supported_rate(pdev_network->SupportedRates, wireless_mode) ;
-+
-+	rateLen = rtw_get_rateset_len(pdev_network->SupportedRates);
-+
-+	if (rateLen > 8) {
-+		ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, pdev_network->SupportedRates, &sz);
-+		/* ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz); */
-+	} else
-+		ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, pdev_network->SupportedRates, &sz);
-+
-+	/* DS parameter set */
-+	ie = rtw_set_ie(ie, _DSSET_IE_, 1, (u8 *)&(pdev_network->Configuration.DSConfig), &sz);
-+
-+
-+	/* IBSS Parameter Set */
-+
-+	ie = rtw_set_ie(ie, _IBSS_PARA_IE_, 2, (u8 *)&(pdev_network->Configuration.ATIMWindow), &sz);
-+
-+	if (rateLen > 8)
-+		ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz);
-+
-+#ifdef CONFIG_80211N_HT
-+	/* HT Cap. */
-+	if (is_supported_ht(pregistrypriv->wireless_mode)
-+	    && (pregistrypriv->ht_enable == _TRUE)) {
-+		/* todo: */
-+	}
-+#endif /* CONFIG_80211N_HT */
-+
-+	/* pdev_network->IELength =  sz; */ /* update IELength */
-+
-+
-+	/* return _SUCCESS; */
-+
-+	return sz;
-+
-+}
-+
-+unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit)
-+{
-+	int len;
-+	u16 val16;
-+	unsigned char wpa_oui_type[] = {0x00, 0x50, 0xf2, 0x01};
-+	u8 *pbuf = pie;
-+	int limit_new = limit;
-+
-+	while (1) {
-+		pbuf = rtw_get_ie(pbuf, _WPA_IE_ID_, &len, limit_new);
-+
-+		if (pbuf) {
-+
-+			/* check if oui matches... */
-+			if (_rtw_memcmp((pbuf + 2), wpa_oui_type, sizeof(wpa_oui_type)) == _FALSE)
-+
-+				goto check_next_ie;
-+
-+			/* check version... */
-+			_rtw_memcpy((u8 *)&val16, (pbuf + 6), sizeof(val16));
-+
-+			val16 = le16_to_cpu(val16);
-+			if (val16 != 0x0001)
-+				goto check_next_ie;
-+
-+			*wpa_ie_len = *(pbuf + 1);
-+
-+			return pbuf;
-+
-+		} else {
-+
-+			*wpa_ie_len = 0;
-+			return NULL;
-+		}
-+
-+check_next_ie:
-+
-+		limit_new = limit - (pbuf - pie) - 2 - len;
-+
-+		if (limit_new <= 0)
-+			break;
-+
-+		pbuf += (2 + len);
-+
-+	}
-+
-+	*wpa_ie_len = 0;
-+
-+	return NULL;
-+
-+}
-+
-+unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit)
-+{
-+
-+	return rtw_get_ie(pie, _WPA2_IE_ID_, rsn_ie_len, limit);
-+
-+}
-+
-+int rtw_get_wpa_cipher_suite(u8 *s)
-+{
-+	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_NONE, WPA_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_NONE;
-+	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP40, WPA_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_WEP40;
-+	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_TKIP, WPA_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_TKIP;
-+	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_CCMP, WPA_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_CCMP;
-+	if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP104, WPA_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_WEP104;
-+
-+	return 0;
-+}
-+
-+int rtw_get_rsn_cipher_suite(u8 *s)
-+{
-+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_NONE, RSN_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_NONE;
-+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP40, RSN_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_WEP40;
-+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_TKIP, RSN_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_TKIP;
-+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_CCMP, RSN_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_CCMP;
-+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_GCMP, RSN_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_GCMP;
-+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_GCMP_256, RSN_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_GCMP_256;
-+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_CCMP_256, RSN_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_CCMP_256;
-+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP104, RSN_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_WEP104;
-+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_AES_128_CMAC, RSN_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_BIP_CMAC_128;
-+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_BIP_GMAC_128, RSN_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_BIP_GMAC_128;
-+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_BIP_GMAC_256, RSN_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_BIP_GMAC_256;
-+	if (_rtw_memcmp(s, RSN_CIPHER_SUITE_BIP_CMAC_256, RSN_SELECTOR_LEN) == _TRUE)
-+		return WPA_CIPHER_BIP_CMAC_256;
-+	return 0;
-+}
-+
-+u32 rtw_get_akm_suite_bitmap(u8 *s)
-+{
-+	if (_rtw_memcmp(s, WLAN_AKM_8021X, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_8021X;
-+	if (_rtw_memcmp(s, WLAN_AKM_PSK, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_PSK;
-+	if (_rtw_memcmp(s, WLAN_AKM_FT_8021X, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_FT_8021X;
-+	if (_rtw_memcmp(s, WLAN_AKM_FT_PSK, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_FT_PSK;
-+	if (_rtw_memcmp(s, WLAN_AKM_8021X_SHA256, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_8021X_SHA256;
-+	if (_rtw_memcmp(s, WLAN_AKM_PSK_SHA256, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_PSK_SHA256;
-+	if (_rtw_memcmp(s, WLAN_AKM_TDLS, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_TDLS;
-+	if (_rtw_memcmp(s, WLAN_AKM_SAE, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_SAE;
-+	if (_rtw_memcmp(s, WLAN_AKM_FT_OVER_SAE, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_FT_OVER_SAE;
-+	if (_rtw_memcmp(s, WLAN_AKM_8021X_SUITE_B, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_8021X_SUITE_B;
-+	if (_rtw_memcmp(s, WLAN_AKM_8021X_SUITE_B_192, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_8021X_SUITE_B_192;
-+	if (_rtw_memcmp(s, WLAN_AKM_FILS_SHA256, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_FILS_SHA256;
-+	if (_rtw_memcmp(s, WLAN_AKM_FILS_SHA384, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_FILS_SHA384;
-+	if (_rtw_memcmp(s, WLAN_AKM_FT_FILS_SHA256, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_FT_FILS_SHA256;
-+	if (_rtw_memcmp(s, WLAN_AKM_FT_FILS_SHA384, RSN_SELECTOR_LEN) == _TRUE)
-+		return WLAN_AKM_TYPE_FT_FILS_SHA384;
-+
-+	return 0;
-+}
-+
-+int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher,
-+	int *pairwise_cipher, u32 *akm)
-+{
-+	int i, ret = _SUCCESS;
-+	int left, count;
-+	u8 *pos;
-+	u8 SUITE_1X[4] = {0x00, 0x50, 0xf2, 1};
-+
-+	if (wpa_ie_len <= 0) {
-+		/* No WPA IE - fail silently */
-+		return _FAIL;
-+	}
-+
-+
-+	if ((*wpa_ie != _WPA_IE_ID_) || (*(wpa_ie + 1) != (u8)(wpa_ie_len - 2)) ||
-+	    (_rtw_memcmp(wpa_ie + 2, RTW_WPA_OUI_TYPE, WPA_SELECTOR_LEN) != _TRUE))
-+		return _FAIL;
-+
-+	pos = wpa_ie;
-+
-+	pos += 8;
-+	left = wpa_ie_len - 8;
-+
-+
-+	/* group_cipher */
-+	if (left >= WPA_SELECTOR_LEN) {
-+
-+		*group_cipher = rtw_get_wpa_cipher_suite(pos);
-+
-+		pos += WPA_SELECTOR_LEN;
-+		left -= WPA_SELECTOR_LEN;
-+
-+	} else if (left > 0) {
-+
-+		return _FAIL;
-+	}
-+
-+
-+	/* pairwise_cipher */
-+	if (left >= 2) {
-+		/* count = le16_to_cpu(*(u16*)pos);	 */
-+		count = RTW_GET_LE16(pos);
-+		pos += 2;
-+		left -= 2;
-+
-+		if (count == 0 || left < count * WPA_SELECTOR_LEN) {
-+			return _FAIL;
-+		}
-+
-+		for (i = 0; i < count; i++) {
-+			*pairwise_cipher |= rtw_get_wpa_cipher_suite(pos);
-+
-+			pos += WPA_SELECTOR_LEN;
-+			left -= WPA_SELECTOR_LEN;
-+		}
-+
-+	} else if (left == 1) {
-+		return _FAIL;
-+	}
-+
-+	if (akm) {
-+		if (left >= 6) {
-+			pos += 2;
-+			if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) {
-+				*akm = WLAN_AKM_TYPE_8021X;
-+			}
-+		}
-+	}
-+
-+	return ret;
-+
-+}
-+
-+int rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info)
-+{
-+	const u8 *pos = ie;
-+	u16 ver;
-+	u16 cnt;
-+
-+	_rtw_memset(info, 0, sizeof(struct rsne_info));
-+
-+	if (ie + ie_len < pos + 4)
-+		goto err;
-+
-+	if (*ie != WLAN_EID_RSN || *(ie + 1) != ie_len - 2)
-+		goto err;
-+	pos += 2;
-+
-+	/* Version */
-+	ver = RTW_GET_LE16(pos);
-+	if(1 != ver)
-+		goto err;
-+	pos += 2;
-+
-+	/* Group CS */
-+	if (ie + ie_len < pos + 4) {
-+		if (ie + ie_len != pos)
-+			goto err;
-+		goto exit;
-+	}
-+	info->gcs = (u8 *)pos;
-+	pos += 4;
-+
-+	/* Pairwise CS */
-+	if (ie + ie_len < pos + 2) {
-+		if (ie + ie_len != pos)
-+			goto err;
-+		goto exit;
-+	}
-+	cnt = RTW_GET_LE16(pos);
-+	pos += 2;
-+	if (ie + ie_len < pos + 4 * cnt) {
-+		if (ie + ie_len != pos)
-+			goto err;
-+		goto exit;
-+	}
-+	info->pcs_cnt = cnt;
-+	info->pcs_list = (u8 *)pos;
-+	pos += 4 * cnt;
-+
-+	/* AKM */
-+	if (ie + ie_len < pos + 2) {
-+		if (ie + ie_len != pos)
-+			goto err;
-+		goto exit;
-+	}
-+	cnt = RTW_GET_LE16(pos);
-+	pos += 2;
-+	if (ie + ie_len < pos + 4 * cnt) {
-+		if (ie + ie_len != pos)
-+			goto err;
-+		goto exit;
-+	}
-+	info->akm_cnt = cnt;
-+	info->akm_list = (u8 *)pos;
-+	pos += 4 * cnt;
-+
-+	/* RSN cap */
-+	if (ie + ie_len < pos + 2) {
-+		if (ie + ie_len != pos)
-+			goto err;
-+		goto exit;
-+	}
-+	info->cap = (u8 *)pos;
-+	pos += 2;
-+
-+	/* PMKID */
-+	if (ie + ie_len < pos + 2) {
-+		if (ie + ie_len != pos)
-+			goto err;
-+		goto exit;
-+	}
-+	cnt = RTW_GET_LE16(pos);
-+	pos += 2;
-+	if (ie + ie_len < pos + 16 * cnt)
-+		goto err;
-+	info->pmkid_cnt = cnt;
-+	info->pmkid_list = (u8 *)pos;
-+	pos += 16 * cnt;
-+
-+	/* Group Mgmt CS */
-+	if (ie + ie_len < pos + 4) {
-+		if (ie + ie_len != pos)
-+			goto err;
-+		goto exit;
-+	}
-+	info->gmcs = (u8 *)pos;
-+
-+exit:
-+	return _SUCCESS;
-+
-+err:
-+	info->err = 1;
-+	return _FAIL;
-+}
-+
-+int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher,
-+	int *pairwise_cipher, int *gmcs, u32 *akm, u8 *mfp_opt)
-+{
-+	struct rsne_info info;
-+	int i, ret = _SUCCESS;
-+
-+	ret = rtw_rsne_info_parse(rsn_ie, rsn_ie_len, &info);
-+	if (ret != _SUCCESS)
-+		goto exit;
-+
-+	if (group_cipher) {
-+		if (info.gcs)
-+			*group_cipher = rtw_get_rsn_cipher_suite(info.gcs);
-+		else
-+			*group_cipher = 0;
-+	}
-+
-+	if (pairwise_cipher) {
-+		*pairwise_cipher = 0;
-+		if (info.pcs_list) {
-+			for (i = 0; i < info.pcs_cnt; i++)
-+				*pairwise_cipher |= rtw_get_rsn_cipher_suite(info.pcs_list + 4 * i);
-+		}
-+	}
-+
-+	if (gmcs) {
-+		if (info.gmcs)
-+			*gmcs = rtw_get_rsn_cipher_suite(info.gmcs);
-+		else
-+			*gmcs = WPA_CIPHER_BIP_CMAC_128; /* default value when absent */
-+	}
-+
-+	if (akm) {
-+		*akm = 0;
-+		if (info.akm_list) {
-+			for (i = 0; i < info.akm_cnt; i++)
-+				*akm |= rtw_get_akm_suite_bitmap(info.akm_list + 4 * i);
-+		}
-+	}
-+
-+	if (mfp_opt) {
-+		*mfp_opt = MFP_NO;
-+		if (info.cap)
-+			*mfp_opt = GET_RSN_CAP_MFP_OPTION(info.cap);
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+/* #ifdef CONFIG_WAPI_SUPPORT */
-+int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len)
-+{
-+	int len = 0;
-+	u8 authmode;
-+	uint	cnt;
-+	u8 wapi_oui1[4] = {0x0, 0x14, 0x72, 0x01};
-+	u8 wapi_oui2[4] = {0x0, 0x14, 0x72, 0x02};
-+
-+
-+	if (wapi_len)
-+		*wapi_len = 0;
-+
-+	if (!in_ie || in_len <= 0)
-+		return len;
-+
-+	cnt = (_TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_);
-+
-+	while (cnt < in_len) {
-+		authmode = in_ie[cnt];
-+
-+		/* if(authmode==_WAPI_IE_) */
-+		if (authmode == _WAPI_IE_ && (_rtw_memcmp(&in_ie[cnt + 6], wapi_oui1, 4) == _TRUE ||
-+			_rtw_memcmp(&in_ie[cnt + 6], wapi_oui2, 4) == _TRUE)) {
-+			if (wapi_ie)
-+				_rtw_memcpy(wapi_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
-+
-+			if (wapi_len)
-+				*wapi_len = in_ie[cnt + 1] + 2;
-+
-+			cnt += in_ie[cnt + 1] + 2; /* get next */
-+		} else {
-+			cnt += in_ie[cnt + 1] + 2; /* get next */
-+		}
-+	}
-+
-+	if (wapi_len)
-+		len = *wapi_len;
-+
-+
-+	return len;
-+
-+}
-+/* #endif */
-+
-+int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u16 *wpa_len)
-+{
-+	u8 authmode, sec_idx;
-+	u8 wpa_oui[4] = {0x0, 0x50, 0xf2, 0x01};
-+	uint	cnt;
-+
-+
-+	/* Search required WPA or WPA2 IE and copy to sec_ie[ ] */
-+
-+	cnt = (_TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_);
-+
-+	sec_idx = 0;
-+
-+	while (cnt < in_len) {
-+		authmode = in_ie[cnt];
-+
-+		if ((authmode == _WPA_IE_ID_) && (_rtw_memcmp(&in_ie[cnt + 2], &wpa_oui[0], 4) == _TRUE)) {
-+
-+			if (wpa_ie)
-+				_rtw_memcpy(wpa_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
-+
-+			*wpa_len = in_ie[cnt + 1] + 2;
-+			cnt += in_ie[cnt + 1] + 2; /* get next */
-+		} else {
-+			if (authmode == _WPA2_IE_ID_) {
-+
-+				if (rsn_ie)
-+					_rtw_memcpy(rsn_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
-+
-+				*rsn_len = in_ie[cnt + 1] + 2;
-+				cnt += in_ie[cnt + 1] + 2; /* get next */
-+			} else {
-+				cnt += in_ie[cnt + 1] + 2; /* get next */
-+			}
-+		}
-+
-+	}
-+
-+
-+	return *rsn_len + *wpa_len;
-+
-+}
-+
-+u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen)
-+{
-+	u8 match = _FALSE;
-+	u8 eid, wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};
-+
-+	if (ie_ptr == NULL)
-+		return match;
-+
-+	eid = ie_ptr[0];
-+
-+	if ((eid == _WPA_IE_ID_) && (_rtw_memcmp(&ie_ptr[2], wps_oui, 4) == _TRUE)) {
-+		/* RTW_INFO("==> found WPS_IE.....\n"); */
-+		*wps_ielen = ie_ptr[1] + 2;
-+		match = _TRUE;
-+	}
-+	return match;
-+}
-+
-+u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, enum bss_type frame_type)
-+{
-+	u8	*wps = NULL;
-+
-+	RTW_INFO("[%s] frame_type = %d\n", __FUNCTION__, frame_type);
-+	switch (frame_type) {
-+	case BSS_TYPE_BCN:
-+	case BSS_TYPE_PROB_RSP: {
-+		/*	Beacon or Probe Response */
-+		wps = rtw_get_wps_ie(in_ie + _PROBERSP_IE_OFFSET_, in_len - _PROBERSP_IE_OFFSET_, wps_ie, wps_ielen);
-+		break;
-+	}
-+	case BSS_TYPE_PROB_REQ: {
-+		/*	Probe Request */
-+		wps = rtw_get_wps_ie(in_ie + _PROBEREQ_IE_OFFSET_ , in_len - _PROBEREQ_IE_OFFSET_ , wps_ie, wps_ielen);
-+		break;
-+	}
-+	default:
-+	case BSS_TYPE_UNDEF:
-+		break;
-+	}
-+	return wps;
-+}
-+
-+/**
-+ * rtw_get_wps_ie - Search WPS IE from a series of IEs
-+ * @in_ie: Address of IEs to search
-+ * @in_len: Length limit from in_ie
-+ * @wps_ie: If not NULL and WPS IE is found, WPS IE will be copied to the buf starting from wps_ie
-+ * @wps_ielen: If not NULL and WPS IE is found, will set to the length of the entire WPS IE
-+ *
-+ * Returns: The address of the WPS IE found, or NULL
-+ */
-+u8 *rtw_get_wps_ie(const u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen)
-+{
-+	uint cnt;
-+	const u8 *wpsie_ptr = NULL;
-+	u8 eid, wps_oui[4] = {0x00, 0x50, 0xf2, 0x04};
-+
-+	if (wps_ielen)
-+		*wps_ielen = 0;
-+
-+	if (!in_ie) {
-+		rtw_warn_on(1);
-+		return (u8 *)wpsie_ptr;
-+	}
-+
-+	if (in_len <= 0)
-+		return (u8 *)wpsie_ptr;
-+
-+	cnt = 0;
-+
-+	while (cnt + 1 + 4 < in_len) {
-+		eid = in_ie[cnt];
-+
-+		if (cnt + 1 + 4 >= MAX_IE_SZ) {
-+			rtw_warn_on(1);
-+			return NULL;
-+		}
-+
-+		if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], wps_oui, 4) == _TRUE) {
-+			wpsie_ptr = in_ie + cnt;
-+
-+			if (wps_ie)
-+				_rtw_memcpy(wps_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
-+
-+			if (wps_ielen)
-+				*wps_ielen = in_ie[cnt + 1] + 2;
-+
-+			break;
-+		} else
-+			cnt += in_ie[cnt + 1] + 2;
-+
-+	}
-+
-+	return (u8 *)wpsie_ptr;
-+}
-+
-+/**
-+ * rtw_get_wps_attr - Search a specific WPS attribute from a given WPS IE
-+ * @wps_ie: Address of WPS IE to search
-+ * @wps_ielen: Length limit from wps_ie
-+ * @target_attr_id: The attribute ID of WPS attribute to search
-+ * @buf_attr: If not NULL and the WPS attribute is found, WPS attribute will be copied to the buf starting from buf_attr
-+ * @len_attr: If not NULL and the WPS attribute is found, will set to the length of the entire WPS attribute
-+ *
-+ * Returns: the address of the specific WPS attribute found, or NULL
-+ */
-+u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_attr, u32 *len_attr)
-+{
-+	u8 *attr_ptr = NULL;
-+	u8 *target_attr_ptr = NULL;
-+	u8 wps_oui[4] = {0x00, 0x50, 0xF2, 0x04};
-+
-+	if (len_attr)
-+		*len_attr = 0;
-+
-+	if ((wps_ie[0] != _VENDOR_SPECIFIC_IE_) ||
-+	    (_rtw_memcmp(wps_ie + 2, wps_oui , 4) != _TRUE))
-+		return attr_ptr;
-+
-+	/* 6 = 1(Element ID) + 1(Length) + 4(WPS OUI) */
-+	attr_ptr = wps_ie + 6; /* goto first attr */
-+
-+	while (attr_ptr - wps_ie < wps_ielen) {
-+		/* 4 = 2(Attribute ID) + 2(Length) */
-+		u16 attr_id = RTW_GET_BE16(attr_ptr);
-+		u16 attr_data_len = RTW_GET_BE16(attr_ptr + 2);
-+		u16 attr_len = attr_data_len + 4;
-+
-+		/* RTW_INFO("%s attr_ptr:%p, id:%u, length:%u\n", __FUNCTION__, attr_ptr, attr_id, attr_data_len); */
-+		if (attr_id == target_attr_id) {
-+			target_attr_ptr = attr_ptr;
-+
-+			if (buf_attr)
-+				_rtw_memcpy(buf_attr, attr_ptr, attr_len);
-+
-+			if (len_attr)
-+				*len_attr = attr_len;
-+
-+			break;
-+		} else {
-+			attr_ptr += attr_len; /* goto next */
-+		}
-+
-+	}
-+
-+	return target_attr_ptr;
-+}
-+
-+/**
-+ * rtw_get_wps_attr_content - Search a specific WPS attribute content from a given WPS IE
-+ * @wps_ie: Address of WPS IE to search
-+ * @wps_ielen: Length limit from wps_ie
-+ * @target_attr_id: The attribute ID of WPS attribute to search
-+ * @buf_content: If not NULL and the WPS attribute is found, WPS attribute content will be copied to the buf starting from buf_content
-+ * @len_content: If not NULL and the WPS attribute is found, will set to the length of the WPS attribute content
-+ *
-+ * Returns: the address of the specific WPS attribute content found, or NULL
-+ */
-+u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_content, uint *len_content)
-+{
-+	u8 *attr_ptr;
-+	u32 attr_len;
-+
-+	if (len_content)
-+		*len_content = 0;
-+
-+	attr_ptr = rtw_get_wps_attr(wps_ie, wps_ielen, target_attr_id, NULL, &attr_len);
-+
-+	if (attr_ptr && attr_len) {
-+		if (buf_content)
-+			_rtw_memcpy(buf_content, attr_ptr + 4, attr_len - 4);
-+
-+		if (len_content)
-+			*len_content = attr_len - 4;
-+
-+		return attr_ptr + 4;
-+	}
-+
-+	return NULL;
-+}
-+
-+/* OWE */
-+
-+/**
-+ * rtw_get_OWE_ie - Search OWE IE from a series of IEs
-+ * @in_ie: Address of IEs to search
-+ * @in_len: Length limit from in_ie
-+ * @wps_ie: If not NULL and OWE IE is found, OWE IE will be copied to the buf starting from owe_ie
-+ * @wps_ielen: If not NULL and OWE IE is found, will set to the length of the entire OWE IE
-+ *
-+ * Returns: The address of the OWE IE found, or NULL
-+ */
-+u8 *rtw_get_owe_ie(const u8 *in_ie, uint in_len, u8 *owe_ie, uint *owe_ielen)
-+{
-+	uint cnt;
-+	const u8 *oweie_ptr = NULL;
-+	u8 eid;
-+
-+	if (owe_ielen)
-+		*owe_ielen = 0;
-+
-+	if (!in_ie) {
-+		rtw_warn_on(1);
-+		return (u8 *)oweie_ptr;
-+	}
-+
-+	if (in_len <= 0)
-+		return (u8 *)oweie_ptr;
-+
-+	cnt = 0;
-+
-+	while (cnt + 1 + 4 < in_len) {
-+		eid = in_ie[cnt];
-+
-+		if (cnt + 1 + 4 >= MAX_IE_SZ) {
-+			rtw_warn_on(1);
-+			return NULL;
-+		}
-+
-+		if ((eid == WLAN_EID_EXTENSION) && (in_ie[cnt + 2] == WLAN_EID_EXT_OWE_DH_PARAM)) {
-+			oweie_ptr = in_ie + cnt;
-+
-+			if (owe_ie)
-+				_rtw_memcpy(owe_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
-+
-+			if (owe_ielen)
-+				*owe_ielen = in_ie[cnt + 1] + 2;
-+
-+			break;
-+		} else
-+			cnt += in_ie[cnt + 1] + 2;
-+
-+	}
-+
-+	return (u8 *)oweie_ptr;
-+}
-+
-+static int rtw_ieee802_11_parse_vendor_specific(u8 *pos, uint elen,
-+		struct rtw_ieee802_11_elems *elems,
-+		int show_errors)
-+{
-+	unsigned int oui;
-+
-+	/* first 3 bytes in vendor specific information element are the IEEE
-+	 * OUI of the vendor. The following byte is used a vendor specific
-+	 * sub-type. */
-+	if (elen < 4) {
-+		if (show_errors) {
-+			RTW_INFO("short vendor specific "
-+				 "information element ignored (len=%lu)\n",
-+				 (unsigned long) elen);
-+		}
-+		return -1;
-+	}
-+
-+	oui = RTW_GET_BE24(pos);
-+	switch (oui) {
-+	case OUI_MICROSOFT:
-+		/* Microsoft/Wi-Fi information elements are further typed and
-+		 * subtyped */
-+		switch (pos[3]) {
-+		case 1:
-+			/* Microsoft OUI (00:50:F2) with OUI Type 1:
-+			 * real WPA information element */
-+			elems->wpa_ie = pos;
-+			elems->wpa_ie_len = elen;
-+			break;
-+		case WME_OUI_TYPE: /* this is a Wi-Fi WME info. element */
-+			if (elen < 5) {
-+				RTW_DBG("short WME "
-+					"information element ignored "
-+					"(len=%lu)\n",
-+					(unsigned long) elen);
-+				return -1;
-+			}
-+			switch (pos[4]) {
-+			case WME_OUI_SUBTYPE_INFORMATION_ELEMENT:
-+			case WME_OUI_SUBTYPE_PARAMETER_ELEMENT:
-+				elems->wme = pos;
-+				elems->wme_len = elen;
-+				break;
-+			case WME_OUI_SUBTYPE_TSPEC_ELEMENT:
-+				elems->wme_tspec = pos;
-+				elems->wme_tspec_len = elen;
-+				break;
-+			default:
-+				RTW_DBG("unknown WME "
-+					"information element ignored "
-+					"(subtype=%d len=%lu)\n",
-+					pos[4], (unsigned long) elen);
-+				return -1;
-+			}
-+			break;
-+		case 4:
-+			/* Wi-Fi Protected Setup (WPS) IE */
-+			elems->wps_ie = pos;
-+			elems->wps_ie_len = elen;
-+			break;
-+		default:
-+			RTW_DBG("Unknown Microsoft "
-+				"information element ignored "
-+				"(type=%d len=%lu)\n",
-+				pos[3], (unsigned long) elen);
-+			return -1;
-+		}
-+		break;
-+
-+	case OUI_BROADCOM:
-+		switch (pos[3]) {
-+		case VENDOR_HT_CAPAB_OUI_TYPE:
-+			elems->vendor_ht_cap = pos;
-+			elems->vendor_ht_cap_len = elen;
-+			break;
-+		default:
-+			RTW_DBG("Unknown Broadcom "
-+				"information element ignored "
-+				"(type=%d len=%lu)\n",
-+				pos[3], (unsigned long) elen);
-+			return -1;
-+		}
-+		break;
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	case OUI_REALTEK:
-+		if (elen == 8) {  // TBTX capable IE length is 8
-+			elems->tbtx_cap = pos;
-+			elems->tbtx_cap_len = elen;
-+		}
-+		break;
-+#endif
-+	default:
-+		RTW_DBG("unknown vendor specific information "
-+			"element ignored (vendor OUI %02x:%02x:%02x "
-+			"len=%lu)\n",
-+			pos[0], pos[1], pos[2], (unsigned long) elen);
-+		return -1;
-+	}
-+
-+	return 0;
-+
-+}
-+
-+/**
-+ * ieee802_11_parse_elems - Parse information elements in management frames
-+ * @start: Pointer to the start of IEs
-+ * @len: Length of IE buffer in octets
-+ * @elems: Data structure for parsed elements
-+ * @show_errors: Whether to show parsing errors in debug log
-+ * Returns: Parsing result
-+ */
-+ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len,
-+				    struct rtw_ieee802_11_elems *elems,
-+				    int show_errors)
-+{
-+	uint left = len;
-+	u8 *pos = start;
-+	int unknown = 0;
-+
-+	_rtw_memset(elems, 0, sizeof(*elems));
-+
-+	while (left >= 2) {
-+		u8 id, elen;
-+
-+		id = *pos++;
-+		elen = *pos++;
-+		left -= 2;
-+
-+		if (elen > left) {
-+			if (show_errors) {
-+				RTW_INFO("IEEE 802.11 element "
-+					 "parse failed (id=%d elen=%d "
-+					 "left=%lu)\n",
-+					 id, elen, (unsigned long) left);
-+			}
-+			return ParseFailed;
-+		}
-+
-+		switch (id) {
-+		case WLAN_EID_SSID:
-+			elems->ssid = pos;
-+			elems->ssid_len = elen;
-+			break;
-+		case WLAN_EID_SUPP_RATES:
-+			elems->supp_rates = pos;
-+			elems->supp_rates_len = elen;
-+			break;
-+		case WLAN_EID_FH_PARAMS:
-+			elems->fh_params = pos;
-+			elems->fh_params_len = elen;
-+			break;
-+		case WLAN_EID_DS_PARAMS:
-+			elems->ds_params = pos;
-+			elems->ds_params_len = elen;
-+			break;
-+		case WLAN_EID_CF_PARAMS:
-+			elems->cf_params = pos;
-+			elems->cf_params_len = elen;
-+			break;
-+		case WLAN_EID_TIM:
-+			elems->tim = pos;
-+			elems->tim_len = elen;
-+			break;
-+		case WLAN_EID_IBSS_PARAMS:
-+			elems->ibss_params = pos;
-+			elems->ibss_params_len = elen;
-+			break;
-+		case WLAN_EID_CHALLENGE:
-+			elems->challenge = pos;
-+			elems->challenge_len = elen;
-+			break;
-+		case WLAN_EID_ERP_INFO:
-+			elems->erp_info = pos;
-+			elems->erp_info_len = elen;
-+			break;
-+		case WLAN_EID_EXT_SUPP_RATES:
-+			elems->ext_supp_rates = pos;
-+			elems->ext_supp_rates_len = elen;
-+			break;
-+		case WLAN_EID_VENDOR_SPECIFIC:
-+			if (rtw_ieee802_11_parse_vendor_specific(pos, elen,
-+					elems,
-+					show_errors))
-+				unknown++;
-+			break;
-+		case WLAN_EID_RSN:
-+			elems->rsn_ie = pos;
-+			elems->rsn_ie_len = elen;
-+			break;
-+		case WLAN_EID_PWR_CAPABILITY:
-+			elems->power_cap = pos;
-+			elems->power_cap_len = elen;
-+			break;
-+		case WLAN_EID_SUPPORTED_CHANNELS:
-+			elems->supp_channels = pos;
-+			elems->supp_channels_len = elen;
-+			break;
-+		case WLAN_EID_MOBILITY_DOMAIN:
-+			elems->mdie = pos;
-+			elems->mdie_len = elen;
-+			break;
-+		case WLAN_EID_FAST_BSS_TRANSITION:
-+			elems->ftie = pos;
-+			elems->ftie_len = elen;
-+			break;
-+		case WLAN_EID_TIMEOUT_INTERVAL:
-+			elems->timeout_int = pos;
-+			elems->timeout_int_len = elen;
-+			break;
-+		case WLAN_EID_HT_CAP:
-+			elems->ht_capabilities = pos;
-+			elems->ht_capabilities_len = elen;
-+			break;
-+		case WLAN_EID_HT_OPERATION:
-+			elems->ht_operation = pos;
-+			elems->ht_operation_len = elen;
-+			break;
-+		case WLAN_EID_VHT_CAPABILITY:
-+			elems->vht_capabilities = pos;
-+			elems->vht_capabilities_len = elen;
-+			break;
-+		case WLAN_EID_VHT_OPERATION:
-+			elems->vht_operation = pos;
-+			elems->vht_operation_len = elen;
-+			break;
-+		case WLAN_EID_VHT_OP_MODE_NOTIFY:
-+			elems->vht_op_mode_notify = pos;
-+			elems->vht_op_mode_notify_len = elen;
-+			break;
-+		case _EID_RRM_EN_CAP_IE_:
-+			elems->rm_en_cap = pos;
-+			elems->rm_en_cap_len = elen;
-+			break;
-+#ifdef CONFIG_RTW_MESH
-+		case WLAN_EID_PREQ:
-+			elems->preq = pos;
-+			elems->preq_len = elen;
-+			break;
-+		case WLAN_EID_PREP:
-+			elems->prep = pos;
-+			elems->prep_len = elen;
-+			break;
-+		case WLAN_EID_PERR:
-+			elems->perr = pos;
-+			elems->perr_len = elen;
-+			break;
-+		case WLAN_EID_RANN:
-+			elems->rann = pos;
-+			elems->rann_len = elen;
-+			break;
-+#endif
-+		default:
-+			unknown++;
-+			if (!show_errors)
-+				break;
-+			RTW_DBG("IEEE 802.11 element parse "
-+				"ignored unknown element (id=%d elen=%d)\n",
-+				id, elen);
-+			break;
-+		}
-+
-+		left -= elen;
-+		pos += elen;
-+	}
-+
-+	if (left)
-+		return ParseFailed;
-+
-+	return unknown ? ParseUnknown : ParseOK;
-+
-+}
-+
-+static u8 key_char2num(u8 ch);
-+static u8 key_char2num(u8 ch)
-+{
-+	if ((ch >= '0') && (ch <= '9'))
-+		return ch - '0';
-+	else if ((ch >= 'a') && (ch <= 'f'))
-+		return ch - 'a' + 10;
-+	else if ((ch >= 'A') && (ch <= 'F'))
-+		return ch - 'A' + 10;
-+	else
-+		return 0xff;
-+}
-+
-+u8 str_2char2num(u8 hch, u8 lch);
-+u8 str_2char2num(u8 hch, u8 lch)
-+{
-+	return (key_char2num(hch) * 10) + key_char2num(lch);
-+}
-+
-+u8 key_2char2num(u8 hch, u8 lch);
-+u8 key_2char2num(u8 hch, u8 lch)
-+{
-+	return (key_char2num(hch) << 4) | key_char2num(lch);
-+}
-+
-+void macstr2num(u8 *dst, u8 *src);
-+void macstr2num(u8 *dst, u8 *src)
-+{
-+	int	jj, kk;
-+	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
-+		dst[jj] = key_2char2num(src[kk], src[kk + 1]);
-+}
-+
-+u8 convert_ip_addr(u8 hch, u8 mch, u8 lch)
-+{
-+	return (key_char2num(hch) * 100) + (key_char2num(mch) * 10) + key_char2num(lch);
-+}
-+
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+#define MAC_ADDRESS_LEN 12
-+
-+int rtw_get_mac_addr_intel(unsigned char *buf)
-+{
-+	int ret = 0;
-+	int i;
-+	struct file *fp = NULL;
-+	mm_segment_t oldfs;
-+	unsigned char c_mac[MAC_ADDRESS_LEN];
-+	char fname[] = "/config/wifi/mac.txt";
-+	int jj, kk;
-+
-+	RTW_INFO("%s Enter\n", __FUNCTION__);
-+
-+	ret = rtw_retrieve_from_file(fname, c_mac, MAC_ADDRESS_LEN);
-+	if (ret < MAC_ADDRESS_LEN)
-+		return -1;
-+
-+	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 2)
-+		buf[jj] = key_2char2num(c_mac[kk], c_mac[kk + 1]);
-+
-+	RTW_INFO("%s: read from file mac address: "MAC_FMT"\n",
-+		 __FUNCTION__, MAC_ARG(buf));
-+
-+	return 0;
-+}
-+#endif /* CONFIG_PLATFORM_INTEL_BYT */
-+
-+/*
-+ * Description:
-+ * rtw_check_invalid_mac_address:
-+ * This is only used for checking mac address valid or not.
-+ *
-+ * Input:
-+ * adapter: mac_address pointer.
-+ * check_local_bit: check locally bit or not.
-+ *
-+ * Output:
-+ * _TRUE: The mac address is invalid.
-+ * _FALSE: The mac address is valid.
-+ *
-+ * Auther: Isaac.Li
-+ */
-+u8 rtw_check_invalid_mac_address(u8 *mac_addr, u8 check_local_bit)
-+{
-+	u8 null_mac_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
-+	u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	u8 res = _FALSE;
-+
-+	if (_rtw_memcmp(mac_addr, null_mac_addr, ETH_ALEN)) {
-+		res = _TRUE;
-+		goto func_exit;
-+	}
-+
-+	if (_rtw_memcmp(mac_addr, multi_mac_addr, ETH_ALEN)) {
-+		res = _TRUE;
-+		goto func_exit;
-+	}
-+
-+	if (mac_addr[0] & BIT0) {
-+		res = _TRUE;
-+		goto func_exit;
-+	}
-+
-+	if (check_local_bit == _TRUE) {
-+		if (mac_addr[0] & BIT1) {
-+			res = _TRUE;
-+			goto func_exit;
-+		}
-+	}
-+
-+func_exit:
-+	return res;
-+}
-+
-+extern char *rtw_initmac;
-+/**
-+ * rtw_macaddr_cfg - Decide the mac address used
-+ * @out: buf to store mac address decided
-+ * @hw_mac_addr: mac address from efuse/epprom
-+ */
-+void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr)
-+{
-+#define DEFAULT_RANDOM_MACADDR 1
-+	u8 mac[ETH_ALEN];
-+
-+	if (out == NULL) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	/* Users specify the mac address */
-+	if (rtw_initmac) {
-+		int jj, kk;
-+
-+		for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
-+			mac[jj] = key_2char2num(rtw_initmac[kk], rtw_initmac[kk + 1]);
-+
-+		goto err_chk;
-+	}
-+
-+	/* platform specified */
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+	if (rtw_get_mac_addr_intel(mac) == 0)
-+		goto err_chk;
-+#endif
-+
-+	/* Use the mac address stored in the Efuse */
-+	if (hw_mac_addr) {
-+		_rtw_memcpy(mac, hw_mac_addr, ETH_ALEN);
-+	}
-+
-+	/*
-+	if (!rockchip_wifi_mac_addr(mac)) {
-+		printk("get mac address from flash=[%02x:%02x:%02x:%02x:%02x:%02x]\n", mac[0], mac[1],
-+		mac[2], mac[3], mac[4], mac[5]);
-+	}
-+          */
-+err_chk:
-+	if (rtw_check_invalid_mac_address(mac, _TRUE) == _TRUE) {
-+#if DEFAULT_RANDOM_MACADDR
-+		RTW_ERR("invalid mac addr:"MAC_FMT", assign random MAC\n", MAC_ARG(mac));
-+		*((u32 *)(&mac[2])) = rtw_random32();
-+		mac[0] = 0x00;
-+		mac[1] = 0xe0;
-+		mac[2] = 0x4c;
-+#else
-+		RTW_ERR("invalid mac addr:"MAC_FMT", assign default one\n", MAC_ARG(mac));
-+		mac[0] = 0x00;
-+		mac[1] = 0xe0;
-+		mac[2] = 0x4c;
-+		mac[3] = 0x87;
-+		mac[4] = 0x00;
-+		mac[5] = 0x00;
-+#endif
-+	}
-+
-+	_rtw_memcpy(out, mac, ETH_ALEN);
-+	RTW_INFO("%s mac addr:"MAC_FMT"\n", __func__, MAC_ARG(out));
-+}
-+
-+#ifdef CONFIG_RTW_DEBUG
-+#ifdef CONFIG_80211N_HT
-+void dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len)
-+{
-+	if (buf_len != HT_CAP_IE_LEN) {
-+		RTW_PRINT_SEL(sel, "Invalid HT capability IE len:%d != %d\n", buf_len, HT_CAP_IE_LEN);
-+		return;
-+	}
-+
-+	RTW_PRINT_SEL(sel, "cap_info:%02x%02x:%s\n", *(buf), *(buf + 1)
-+		, GET_HT_CAP_ELE_CHL_WIDTH(buf) ? " 40MHz" : " 20MHz");
-+	RTW_PRINT_SEL(sel, "A-MPDU Parameters:"HT_AMPDU_PARA_FMT"\n"
-+		      , HT_AMPDU_PARA_ARG(HT_CAP_ELE_AMPDU_PARA(buf)));
-+	RTW_PRINT_SEL(sel, "Supported MCS Set:"HT_SUP_MCS_SET_FMT"\n"
-+		      , HT_SUP_MCS_SET_ARG(HT_CAP_ELE_SUP_MCS_SET(buf)));
-+}
-+
-+void dump_ht_cap_ie(void *sel, const u8 *ie, u32 ie_len)
-+{
-+	const u8 *ht_cap_ie;
-+	sint ht_cap_ielen;
-+
-+	ht_cap_ie = rtw_get_ie(ie, WLAN_EID_HT_CAP, &ht_cap_ielen, ie_len);
-+	if (!ie || ht_cap_ie != ie)
-+		return;
-+
-+	dump_ht_cap_ie_content(sel, ht_cap_ie + 2, ht_cap_ielen);
-+}
-+
-+const char *const _ht_sc_offset_str[] = {
-+	"SCN",
-+	"SCA",
-+	"SC-RSVD",
-+	"SCB",
-+};
-+
-+void dump_ht_op_ie_content(void *sel, const u8 *buf, u32 buf_len)
-+{
-+	if (buf_len != HT_OP_IE_LEN) {
-+		RTW_PRINT_SEL(sel, "Invalid HT operation IE len:%d != %d\n", buf_len, HT_OP_IE_LEN);
-+		return;
-+	}
-+
-+	RTW_PRINT_SEL(sel, "ch:%u%s %s\n"
-+		, GET_HT_OP_ELE_PRI_CHL(buf)
-+		, GET_HT_OP_ELE_STA_CHL_WIDTH(buf) ? "" : " 20MHz only"
-+		, ht_sc_offset_str(GET_HT_OP_ELE_2ND_CHL_OFFSET(buf))
-+	);
-+}
-+
-+void dump_ht_op_ie(void *sel, const u8 *ie, u32 ie_len)
-+{
-+	const u8 *ht_op_ie;
-+	sint ht_op_ielen;
-+
-+	ht_op_ie = rtw_get_ie(ie, WLAN_EID_HT_OPERATION, &ht_op_ielen, ie_len);
-+	if (!ie || ht_op_ie != ie)
-+		return;
-+
-+	dump_ht_op_ie_content(sel, ht_op_ie + 2, ht_op_ielen);
-+}
-+#endif /* CONFIG_80211N_HT */
-+
-+void dump_wps_ie(void *sel, const u8 *ie, u32 ie_len)
-+{
-+	const u8 *pos = ie;
-+	u16 id;
-+	u16 len;
-+
-+	const u8 *wps_ie;
-+	uint wps_ielen;
-+
-+	wps_ie = rtw_get_wps_ie(ie, ie_len, NULL, &wps_ielen);
-+	if (wps_ie != ie || wps_ielen == 0)
-+		return;
-+
-+	pos += 6;
-+	while (pos - ie + 4 <= ie_len) {
-+		id = RTW_GET_BE16(pos);
-+		len = RTW_GET_BE16(pos + 2);
-+
-+		RTW_PRINT_SEL(sel, "%s ID:0x%04x, LEN:%u%s\n", __func__, id, len
-+			, ((pos - ie + 4 + len) <= ie_len) ? "" : "(exceed ie_len)");
-+
-+		pos += (4 + len);
-+	}
-+}
-+#endif	/*	CONFIG_RTW_DEBUG	*/
-+void dump_ies(void *sel, const u8 *buf, u32 buf_len)
-+{
-+#ifdef CONFIG_RTW_DEBUG
-+	const u8 *pos = buf;
-+	u8 id, len;
-+
-+	while (pos - buf + 1 < buf_len) {
-+		id = *pos;
-+		len = *(pos + 1);
-+
-+		RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u\n", __FUNCTION__, id, len);
-+#ifdef CONFIG_80211N_HT
-+		dump_ht_cap_ie(sel, pos, len + 2);
-+		dump_ht_op_ie(sel, pos, len + 2);
-+#endif
-+#ifdef CONFIG_80211AC_VHT
-+		dump_vht_cap_ie(sel, pos, len + 2);
-+		dump_vht_op_ie(sel, pos, len + 2);
-+#endif
-+		dump_wps_ie(sel, pos, len + 2);
-+#ifdef CONFIG_P2P
-+		dump_p2p_ie(sel, pos, len + 2);
-+#ifdef CONFIG_WFD
-+		dump_wfd_ie(sel, pos, len + 2);
-+#endif
-+#endif
-+#ifdef CONFIG_RTW_MULTI_AP
-+		dump_multi_ap_ie(sel, pos, len + 2);
-+#endif
-+
-+		pos += (2 + len);
-+	}
-+#endif	/*	CONFIG_RTW_DEBUG	*/
-+}
-+
-+/**
-+ * rtw_ies_get_chbw - get operation ch, bw, offset from IEs of BSS.
-+ * @ies: pointer of the first tlv IE
-+ * @ies_len: length of @ies
-+ * @ch: pointer of ch, used as output
-+ * @bw: pointer of bw, used as output
-+ * @offset: pointer of offset, used as output
-+ * @ht: check HT IEs
-+ * @vht: check VHT IEs, if true imply ht is true
-+ */
-+void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht)
-+{
-+	u8 *p;
-+	int	ie_len;
-+
-+	*ch = 0;
-+	*bw = CHANNEL_WIDTH_20;
-+	*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+
-+	p = rtw_get_ie(ies, _DSSET_IE_, &ie_len, ies_len);
-+	if (p && ie_len > 0)
-+		*ch = *(p + 2);
-+
-+#ifdef CONFIG_80211N_HT
-+	if (ht || vht) {
-+		u8 *ht_cap_ie, *ht_op_ie;
-+		int ht_cap_ielen, ht_op_ielen;
-+
-+		ht_cap_ie = rtw_get_ie(ies, EID_HTCapability, &ht_cap_ielen, ies_len);
-+		if (ht_cap_ie && ht_cap_ielen) {
-+			if (GET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2))
-+				*bw = CHANNEL_WIDTH_40;
-+		}
-+
-+		ht_op_ie = rtw_get_ie(ies, EID_HTInfo, &ht_op_ielen, ies_len);
-+		if (ht_op_ie && ht_op_ielen) {
-+			if (*ch == 0)
-+				*ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2);
-+			else if (*ch != 0 && *ch != GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2)) {
-+				RTW_INFO("%s ch inconsistent, DSSS:%u, HT primary:%u\n"
-+					, __func__, *ch, GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2));
-+			}
-+
-+			if (!GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2))
-+				*bw = CHANNEL_WIDTH_20;
-+
-+			if (*bw == CHANNEL_WIDTH_40) {
-+				switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) {
-+				case SCA:
-+					*offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+					break;
-+				case SCB:
-+					*offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+					break;
-+				}
-+			}
-+		}
-+
-+#ifdef CONFIG_80211AC_VHT
-+		if (vht) {
-+			u8 *vht_op_ie;
-+			int vht_op_ielen;
-+
-+			vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len);
-+			if (vht_op_ie && vht_op_ielen) {
-+				if (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2) >= 1)
-+					*bw = CHANNEL_WIDTH_80;
-+			}
-+		}
-+#endif /* CONFIG_80211AC_VHT */
-+
-+	}
-+#endif /* CONFIG_80211N_HT */
-+}
-+
-+void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht)
-+{
-+	rtw_ies_get_chbw(bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)
-+		, bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)
-+		, ch, bw, offset, ht, vht);
-+
-+	if (*ch == 0)
-+		*ch = bss->Configuration.DSConfig;
-+	else if (*ch != bss->Configuration.DSConfig) {
-+		RTW_INFO("inconsistent ch - ies:%u bss->Configuration.DSConfig:%u\n"
-+			 , *ch, bss->Configuration.DSConfig);
-+		*ch = bss->Configuration.DSConfig;
-+		rtw_warn_on(1);
-+	}
-+}
-+
-+/**
-+ * rtw_is_chbw_grouped - test if the two ch settings can be grouped together
-+ * @ch_a: ch of set a
-+ * @bw_a: bw of set a
-+ * @offset_a: offset of set a
-+ * @ch_b: ch of set b
-+ * @bw_b: bw of set b
-+ * @offset_b: offset of set b
-+ */
-+bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a
-+			 , u8 ch_b, u8 bw_b, u8 offset_b)
-+{
-+	bool is_grouped = _FALSE;
-+
-+	if (ch_a != ch_b) {
-+		/* ch is different */
-+		goto exit;
-+	} else if ((bw_a == CHANNEL_WIDTH_40 || bw_a == CHANNEL_WIDTH_80)
-+		   && (bw_b == CHANNEL_WIDTH_40 || bw_b == CHANNEL_WIDTH_80)
-+		  ) {
-+		if (offset_a != offset_b)
-+			goto exit;
-+	}
-+
-+	is_grouped = _TRUE;
-+
-+exit:
-+	return is_grouped;
-+}
-+
-+/**
-+ * rtw_sync_chbw - obey g_ch, adjust g_bw, g_offset, bw, offset
-+ * @req_ch: pointer of the request ch, may be modified further
-+ * @req_bw: pointer of the request bw, may be modified further
-+ * @req_offset: pointer of the request offset, may be modified further
-+ * @g_ch: pointer of the ongoing group ch
-+ * @g_bw: pointer of the ongoing group bw, may be modified further
-+ * @g_offset: pointer of the ongoing group offset, may be modified further
-+ */
-+void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset
-+		   , u8 *g_ch, u8 *g_bw, u8 *g_offset)
-+{
-+
-+	*req_ch = *g_ch;
-+
-+	if (*req_bw == CHANNEL_WIDTH_80 && *g_ch <= 14) {
-+		/*2.4G ch, downgrade to 40Mhz */
-+		*req_bw = CHANNEL_WIDTH_40;
-+	}
-+
-+	switch (*req_bw) {
-+	case CHANNEL_WIDTH_80:
-+		if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80)
-+			*req_offset = *g_offset;
-+		else if (*g_bw == CHANNEL_WIDTH_20)
-+			rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset);
-+
-+		if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
-+			RTW_ERR("%s req 80MHz BW without offset, down to 20MHz\n", __func__);
-+			rtw_warn_on(1);
-+			*req_bw = CHANNEL_WIDTH_20;
-+		}
-+		break;
-+	case CHANNEL_WIDTH_40:
-+		if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80)
-+			*req_offset = *g_offset;
-+		else if (*g_bw == CHANNEL_WIDTH_20)
-+			rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset);
-+
-+		if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
-+			RTW_ERR("%s req 40MHz BW without offset, down to 20MHz\n", __func__);
-+			rtw_warn_on(1);
-+			*req_bw = CHANNEL_WIDTH_20;
-+		}
-+		break;
-+	case CHANNEL_WIDTH_20:
-+		*req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		break;
-+	default:
-+		RTW_ERR("%s req unsupported BW:%u\n", __func__, *req_bw);
-+		rtw_warn_on(1);
-+	}
-+
-+	if (*req_bw > *g_bw) {
-+		*g_bw = *req_bw;
-+		*g_offset = *req_offset;
-+	}
-+}
-+
-+#ifdef CONFIG_P2P
-+/**
-+ * rtw_get_p2p_merged_len - Get merged ie length from muitiple p2p ies.
-+ * @in_ie: Pointer of the first p2p ie
-+ * @in_len: Total len of muiltiple p2p ies
-+ * Returns: Length of merged p2p ie length
-+ */
-+u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len)
-+{
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 };
-+	int i = 0;
-+	int len = 0;
-+
-+	while (i < in_len) {
-+		pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie + i);
-+
-+		if (pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4)) {
-+			len += pIE->Length - 4; /* 4 is P2P OUI length, don't count it in this loop */
-+		}
-+
-+		i += (pIE->Length + 2);
-+	}
-+
-+	return len + 4;	/* Append P2P OUI length at last. */
-+}
-+
-+/**
-+ * rtw_p2p_merge_ies - Merge muitiple p2p ies into one
-+ * @in_ie: Pointer of the first p2p ie
-+ * @in_len: Total len of muiltiple p2p ies
-+ * @merge_ie: Pointer of merged ie
-+ * Returns: Length of merged p2p ie
-+ */
-+int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie)
-+{
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	u8 len = 0;
-+	u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 };
-+	u8 ELOUI[6] = { 0xDD, 0x00, 0x50, 0x6f, 0x9a, 0x09 };	/* EID;Len;OUI, Len would copy at the end of function */
-+	int i = 0;
-+
-+	if (merge_ie != NULL) {
-+		/* Set first P2P OUI */
-+		_rtw_memcpy(merge_ie, ELOUI, 6);
-+		merge_ie += 6;
-+
-+		while (i < in_len) {
-+			pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie + i);
-+
-+			/* Take out the rest of P2P OUIs */
-+			if (pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4)) {
-+				_rtw_memcpy(merge_ie, pIE->data + 4, pIE->Length - 4);
-+				len += pIE->Length - 4;
-+				merge_ie += pIE->Length - 4;
-+			}
-+
-+			i += (pIE->Length + 2);
-+		}
-+
-+		return len + 4;	/* 4 is for P2P OUI */
-+
-+	}
-+
-+	return 0;
-+}
-+
-+void dump_p2p_ie(void *sel, const u8 *ie, u32 ie_len)
-+{
-+	const u8 *pos = ie;
-+	u8 id;
-+	u16 len;
-+
-+	const u8 *p2p_ie;
-+	uint p2p_ielen;
-+
-+	p2p_ie = rtw_get_p2p_ie(ie, ie_len, NULL, &p2p_ielen);
-+	if (p2p_ie != ie || p2p_ielen == 0)
-+		return;
-+
-+	pos += 6;
-+	while (pos - ie + 3 <= ie_len) {
-+		id = *pos;
-+		len = RTW_GET_LE16(pos + 1);
-+
-+		RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u%s\n", __func__, id, len
-+			, ((pos - ie + 3 + len) <= ie_len) ? "" : "(exceed ie_len)");
-+
-+		pos += (3 + len);
-+	}
-+}
-+
-+/**
-+ * rtw_get_p2p_ie - Search P2P IE from a series of IEs
-+ * @in_ie: Address of IEs to search
-+ * @in_len: Length limit from in_ie
-+ * @p2p_ie: If not NULL and P2P IE is found, P2P IE will be copied to the buf starting from p2p_ie
-+ * @p2p_ielen: If not NULL and P2P IE is found, will set to the length of the entire P2P IE
-+ *
-+ * Returns: The address of the P2P IE found, or NULL
-+ */
-+u8 *rtw_get_p2p_ie(const u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen)
-+{
-+	uint cnt;
-+	const u8 *p2p_ie_ptr = NULL;
-+	u8 eid, p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09};
-+
-+	if (p2p_ielen)
-+		*p2p_ielen = 0;
-+
-+	if (!in_ie || in_len < 0) {
-+		rtw_warn_on(1);
-+		return (u8 *)p2p_ie_ptr;
-+	}
-+
-+	if (in_len <= 0)
-+		return (u8 *)p2p_ie_ptr;
-+
-+	cnt = 0;
-+
-+	while (cnt + 1 + 4 < in_len) {
-+		eid = in_ie[cnt];
-+
-+		if (cnt + 1 + 4 >= MAX_IE_SZ) {
-+			rtw_warn_on(1);
-+			return NULL;
-+		}
-+
-+		if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], p2p_oui, 4) == _TRUE) {
-+			p2p_ie_ptr = in_ie + cnt;
-+
-+			if (p2p_ie)
-+				_rtw_memcpy(p2p_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
-+
-+			if (p2p_ielen)
-+				*p2p_ielen = in_ie[cnt + 1] + 2;
-+
-+			break;
-+		} else
-+			cnt += in_ie[cnt + 1] + 2;
-+
-+	}
-+
-+	return (u8 *)p2p_ie_ptr;
-+}
-+
-+/**
-+ * rtw_get_p2p_attr - Search a specific P2P attribute from a given P2P IE
-+ * @p2p_ie: Address of P2P IE to search
-+ * @p2p_ielen: Length limit from p2p_ie
-+ * @target_attr_id: The attribute ID of P2P attribute to search
-+ * @buf_attr: If not NULL and the P2P attribute is found, P2P attribute will be copied to the buf starting from buf_attr
-+ * @len_attr: If not NULL and the P2P attribute is found, will set to the length of the entire P2P attribute
-+ *
-+ * Returns: the address of the specific WPS attribute found, or NULL
-+ */
-+u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id , u8 *buf_attr, u32 *len_attr)
-+{
-+	u8 *attr_ptr = NULL;
-+	u8 *target_attr_ptr = NULL;
-+	u8 p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09};
-+
-+	if (len_attr)
-+		*len_attr = 0;
-+
-+	if (!p2p_ie
-+	    || p2p_ielen <= 6
-+	    || (p2p_ie[0] != WLAN_EID_VENDOR_SPECIFIC)
-+	    || (_rtw_memcmp(p2p_ie + 2, p2p_oui, 4) != _TRUE))
-+		return attr_ptr;
-+
-+	/* 6 = 1(Element ID) + 1(Length) + 3 (OUI) + 1(OUI Type) */
-+	attr_ptr = p2p_ie + 6; /* goto first attr */
-+
-+	while ((attr_ptr - p2p_ie + 3) <= p2p_ielen) {
-+		/* 3 = 1(Attribute ID) + 2(Length) */
-+		u8 attr_id = *attr_ptr;
-+		u16 attr_data_len = RTW_GET_LE16(attr_ptr + 1);
-+		u16 attr_len = attr_data_len + 3;
-+
-+		if (0)
-+			RTW_INFO("%s attr_ptr:%p, id:%u, length:%u\n", __func__, attr_ptr, attr_id, attr_data_len);
-+
-+		if ((attr_ptr - p2p_ie + attr_len) > p2p_ielen)
-+			break;
-+
-+		if (attr_id == target_attr_id) {
-+			target_attr_ptr = attr_ptr;
-+
-+			if (buf_attr)
-+				_rtw_memcpy(buf_attr, attr_ptr, attr_len);
-+
-+			if (len_attr)
-+				*len_attr = attr_len;
-+
-+			break;
-+		} else
-+			attr_ptr += attr_len;
-+	}
-+
-+	return target_attr_ptr;
-+}
-+
-+/**
-+ * rtw_get_p2p_attr_content - Search a specific P2P attribute content from a given P2P IE
-+ * @p2p_ie: Address of P2P IE to search
-+ * @p2p_ielen: Length limit from p2p_ie
-+ * @target_attr_id: The attribute ID of P2P attribute to search
-+ * @buf_content: If not NULL and the P2P attribute is found, P2P attribute content will be copied to the buf starting from buf_content
-+ * @len_content: If not NULL and the P2P attribute is found, will set to the length of the P2P attribute content
-+ *
-+ * Returns: the address of the specific P2P attribute content found, or NULL
-+ */
-+u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id , u8 *buf_content, uint *len_content)
-+{
-+	u8 *attr_ptr;
-+	u32 attr_len;
-+
-+	if (len_content)
-+		*len_content = 0;
-+
-+	attr_ptr = rtw_get_p2p_attr(p2p_ie, p2p_ielen, target_attr_id, NULL, &attr_len);
-+
-+	if (attr_ptr && attr_len) {
-+		if (buf_content)
-+			_rtw_memcpy(buf_content, attr_ptr + 3, attr_len - 3);
-+
-+		if (len_content)
-+			*len_content = attr_len - 3;
-+
-+		return attr_ptr + 3;
-+	}
-+
-+	return NULL;
-+}
-+
-+u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr)
-+{
-+	u32 a_len;
-+
-+	*pbuf = attr_id;
-+
-+	/* *(u16*)(pbuf + 1) = cpu_to_le16(attr_len); */
-+	RTW_PUT_LE16(pbuf + 1, attr_len);
-+
-+	if (pdata_attr)
-+		_rtw_memcpy(pbuf + 3, pdata_attr, attr_len);
-+
-+	a_len = attr_len + 3;
-+
-+	return a_len;
-+}
-+
-+uint rtw_del_p2p_ie(u8 *ies, uint ies_len_ori, const char *msg)
-+{
-+#define DBG_DEL_P2P_IE 0
-+
-+	u8 *target_ie;
-+	u32 target_ie_len;
-+	uint ies_len = ies_len_ori;
-+	int index = 0;
-+
-+	while (1) {
-+		target_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &target_ie_len);
-+		if (target_ie && target_ie_len) {
-+			u8 *next_ie = target_ie + target_ie_len;
-+			uint remain_len = ies_len - (next_ie - ies);
-+
-+			if (DBG_DEL_P2P_IE && msg) {
-+				RTW_INFO("%s %d before\n", __func__, index);
-+				dump_ies(RTW_DBGDUMP, ies, ies_len);
-+
-+				RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len);
-+				RTW_INFO("target_ie:%p, target_ie_len:%u\n", target_ie, target_ie_len);
-+				RTW_INFO("next_ie:%p, remain_len:%u\n", next_ie, remain_len);
-+			}
-+
-+			_rtw_memmove(target_ie, next_ie, remain_len);
-+			_rtw_memset(target_ie + remain_len, 0, target_ie_len);
-+			ies_len -= target_ie_len;
-+
-+			if (DBG_DEL_P2P_IE && msg) {
-+				RTW_INFO("%s %d after\n", __func__, index);
-+				dump_ies(RTW_DBGDUMP, ies, ies_len);
-+			}
-+
-+			index++;
-+		} else
-+			break;
-+	}
-+
-+	return ies_len;
-+}
-+
-+uint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id)
-+{
-+#define DBG_DEL_P2P_ATTR 0
-+
-+	u8 *target_attr;
-+	u32 target_attr_len;
-+	uint ielen = ielen_ori;
-+	int index = 0;
-+
-+	while (1) {
-+		target_attr = rtw_get_p2p_attr(ie, ielen, attr_id, NULL, &target_attr_len);
-+		if (target_attr && target_attr_len) {
-+			u8 *next_attr = target_attr + target_attr_len;
-+			uint remain_len = ielen - (next_attr - ie);
-+
-+			if (DBG_DEL_P2P_ATTR) {
-+				RTW_INFO("%s %d before\n", __func__, index);
-+				dump_ies(RTW_DBGDUMP, ie, ielen);
-+
-+				RTW_INFO("ie:%p, ielen:%u\n", ie, ielen);
-+				RTW_INFO("target_attr:%p, target_attr_len:%u\n", target_attr, target_attr_len);
-+				RTW_INFO("next_attr:%p, remain_len:%u\n", next_attr, remain_len);
-+			}
-+
-+			_rtw_memmove(target_attr, next_attr, remain_len);
-+			_rtw_memset(target_attr + remain_len, 0, target_attr_len);
-+			*(ie + 1) -= target_attr_len;
-+			ielen -= target_attr_len;
-+
-+			if (DBG_DEL_P2P_ATTR) {
-+				RTW_INFO("%s %d after\n", __func__, index);
-+				dump_ies(RTW_DBGDUMP, ie, ielen);
-+			}
-+
-+			index++;
-+		} else
-+			break;
-+	}
-+
-+	return ielen;
-+}
-+
-+inline u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen)
-+{
-+	return rtw_get_p2p_ie(BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex), p2p_ie, p2p_ielen);
-+}
-+
-+void rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex)
-+{
-+#define DBG_BSS_EX_DEL_P2P_IE 0
-+
-+	u8 *ies = BSS_EX_TLV_IES(bss_ex);
-+	uint ies_len_ori = BSS_EX_TLV_IES_LEN(bss_ex);
-+	uint ies_len;
-+
-+	ies_len = rtw_del_p2p_ie(ies, ies_len_ori, DBG_BSS_EX_DEL_P2P_IE ? __func__ : NULL);
-+	bss_ex->IELength -= ies_len_ori - ies_len;
-+}
-+
-+void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id)
-+{
-+#define DBG_BSS_EX_DEL_P2P_ATTR 0
-+
-+	u8 *ies = BSS_EX_TLV_IES(bss_ex);
-+	uint ies_len = BSS_EX_TLV_IES_LEN(bss_ex);
-+
-+	u8 *ie;
-+	uint ie_len, ie_len_ori;
-+
-+	int index = 0;
-+
-+	while (1) {
-+		ie = rtw_get_p2p_ie(ies, ies_len, NULL, &ie_len_ori);
-+		if (ie) {
-+			u8 *next_ie_ori = ie + ie_len_ori;
-+			uint remain_len = bss_ex->IELength - (next_ie_ori - bss_ex->IEs);
-+			u8 has_target_attr = 0;
-+
-+			if (DBG_BSS_EX_DEL_P2P_ATTR) {
-+				if (rtw_get_p2p_attr(ie, ie_len_ori, attr_id, NULL, NULL)) {
-+					RTW_INFO("%s %d before\n", __func__, index);
-+					dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));
-+
-+					RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len);
-+					RTW_INFO("ie:%p, ie_len_ori:%u\n", ie, ie_len_ori);
-+					RTW_INFO("next_ie_ori:%p, remain_len:%u\n", next_ie_ori, remain_len);
-+					has_target_attr = 1;
-+				}
-+			}
-+
-+			ie_len = rtw_del_p2p_attr(ie, ie_len_ori, attr_id);
-+			if (ie_len != ie_len_ori) {
-+				u8 *next_ie = ie + ie_len;
-+
-+				_rtw_memmove(next_ie, next_ie_ori, remain_len);
-+				_rtw_memset(next_ie + remain_len, 0, ie_len_ori - ie_len);
-+				bss_ex->IELength -= ie_len_ori - ie_len;
-+
-+				ies = next_ie;
-+			} else
-+				ies = next_ie_ori;
-+
-+			if (DBG_BSS_EX_DEL_P2P_ATTR) {
-+				if (has_target_attr) {
-+					RTW_INFO("%s %d after\n", __func__, index);
-+					dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));
-+				}
-+			}
-+
-+			ies_len = remain_len;
-+
-+			index++;
-+		} else
-+			break;
-+	}
-+}
-+#endif	/*	CONFIG_P2P	*/
-+
-+/**
-+ * rtw_get_wfd_ie - Search WFD IE from a series of IEs
-+ * @in_ie: Address of IEs to search
-+ * @in_len: Length limit from in_ie
-+ * @wfd_ie: If not NULL and WFD IE is found, WFD IE will be copied to the buf starting from wfd_ie
-+ * @wfd_ielen: If not NULL and WFD IE is found, will set to the length of the entire WFD IE
-+ *
-+ * Returns: The address of the P2P IE found, or NULL
-+ */
-+u8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen)
-+{
-+	uint cnt;
-+	const u8 *wfd_ie_ptr = NULL;
-+	u8 eid, wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A};
-+
-+	if (wfd_ielen)
-+		*wfd_ielen = 0;
-+
-+	if (!in_ie || in_len < 0) {
-+		rtw_warn_on(1);
-+		return (u8 *)wfd_ie_ptr;
-+	}
-+
-+	if (in_len <= 0)
-+		return (u8 *)wfd_ie_ptr;
-+
-+	cnt = 0;
-+
-+	while (cnt + 1 + 4 < in_len) {
-+		eid = in_ie[cnt];
-+
-+		if (cnt + 1 + 4 >= MAX_IE_SZ) {
-+			rtw_warn_on(1);
-+			return NULL;
-+		}
-+
-+		if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], wfd_oui, 4) == _TRUE) {
-+			wfd_ie_ptr = in_ie + cnt;
-+
-+			if (wfd_ie)
-+				_rtw_memcpy(wfd_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
-+
-+			if (wfd_ielen)
-+				*wfd_ielen = in_ie[cnt + 1] + 2;
-+
-+			break;
-+		} else
-+			cnt += in_ie[cnt + 1] + 2;
-+
-+	}
-+
-+	return (u8 *)wfd_ie_ptr;
-+}
-+
-+uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg)
-+{
-+#define DBG_DEL_WFD_IE 0
-+
-+	u8 *target_ie;
-+	u32 target_ie_len;
-+	uint ies_len = ies_len_ori;
-+	int index = 0;
-+
-+	while (1) {
-+		target_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &target_ie_len);
-+		if (target_ie && target_ie_len) {
-+			u8 *next_ie = target_ie + target_ie_len;
-+			uint remain_len = ies_len - (next_ie - ies);
-+
-+			if (DBG_DEL_WFD_IE && msg) {
-+				RTW_INFO("%s %d before\n", __func__, index);
-+				dump_ies(RTW_DBGDUMP, ies, ies_len);
-+
-+				RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len);
-+				RTW_INFO("target_ie:%p, target_ie_len:%u\n", target_ie, target_ie_len);
-+				RTW_INFO("next_ie:%p, remain_len:%u\n", next_ie, remain_len);
-+			}
-+
-+			_rtw_memmove(target_ie, next_ie, remain_len);
-+			_rtw_memset(target_ie + remain_len, 0, target_ie_len);
-+			ies_len -= target_ie_len;
-+
-+			if (DBG_DEL_WFD_IE && msg) {
-+				RTW_INFO("%s %d after\n", __func__, index);
-+				dump_ies(RTW_DBGDUMP, ies, ies_len);
-+			}
-+
-+			index++;
-+		} else
-+			break;
-+	}
-+
-+	return ies_len;
-+}
-+
-+void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex)
-+{
-+#define DBG_BSS_EX_DEL_WFD_IE 0
-+	u8 *ies = BSS_EX_TLV_IES(bss_ex);
-+	uint ies_len_ori = BSS_EX_TLV_IES_LEN(bss_ex);
-+	uint ies_len;
-+
-+	ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_BSS_EX_DEL_WFD_IE ? __func__ : NULL);
-+	bss_ex->IELength -= ies_len_ori - ies_len;
-+}
-+
-+#ifdef CONFIG_WFD
-+void dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len)
-+{
-+	const u8 *pos = ie;
-+	u8 id;
-+	u16 len;
-+
-+	const u8 *wfd_ie;
-+	uint wfd_ielen;
-+
-+	wfd_ie = rtw_get_wfd_ie(ie, ie_len, NULL, &wfd_ielen);
-+	if (wfd_ie != ie || wfd_ielen == 0)
-+		return;
-+
-+	pos += 6;
-+	while (pos - ie + 3 <= ie_len) {
-+		id = *pos;
-+		len = RTW_GET_BE16(pos + 1);
-+
-+		RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u%s\n", __func__, id, len
-+			, ((pos - ie + 3 + len) <= ie_len) ? "" : "(exceed ie_len)");
-+
-+		pos += (3 + len);
-+	}
-+}
-+
-+/**
-+ * rtw_get_wfd_attr - Search a specific WFD attribute from a given WFD IE
-+ * @wfd_ie: Address of WFD IE to search
-+ * @wfd_ielen: Length limit from wfd_ie
-+ * @target_attr_id: The attribute ID of WFD attribute to search
-+ * @buf_attr: If not NULL and the WFD attribute is found, WFD attribute will be copied to the buf starting from buf_attr
-+ * @len_attr: If not NULL and the WFD attribute is found, will set to the length of the entire WFD attribute
-+ *
-+ * Returns: the address of the specific WPS attribute found, or NULL
-+ */
-+u8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr)
-+{
-+	u8 *attr_ptr = NULL;
-+	u8 *target_attr_ptr = NULL;
-+	u8 wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A};
-+
-+	if (len_attr)
-+		*len_attr = 0;
-+
-+	if (!wfd_ie
-+	    || wfd_ielen <= 6
-+	    || (wfd_ie[0] != WLAN_EID_VENDOR_SPECIFIC)
-+	    || (_rtw_memcmp(wfd_ie + 2, wfd_oui, 4) != _TRUE))
-+		return attr_ptr;
-+
-+	/* 6 = 1(Element ID) + 1(Length) + 3 (OUI) + 1(OUI Type) */
-+	attr_ptr = wfd_ie + 6; /* goto first attr */
-+
-+	while ((attr_ptr - wfd_ie + 3) <= wfd_ielen) {
-+		/* 3 = 1(Attribute ID) + 2(Length) */
-+		u8 attr_id = *attr_ptr;
-+		u16 attr_data_len = RTW_GET_BE16(attr_ptr + 1);
-+		u16 attr_len = attr_data_len + 3;
-+
-+		if (0)
-+			RTW_INFO("%s attr_ptr:%p, id:%u, length:%u\n", __func__, attr_ptr, attr_id, attr_data_len);
-+
-+		if ((attr_ptr - wfd_ie + attr_len) > wfd_ielen)
-+			break;
-+
-+		if (attr_id == target_attr_id) {
-+			target_attr_ptr = attr_ptr;
-+
-+			if (buf_attr)
-+				_rtw_memcpy(buf_attr, attr_ptr, attr_len);
-+
-+			if (len_attr)
-+				*len_attr = attr_len;
-+
-+			break;
-+		} else
-+			attr_ptr += attr_len;
-+	}
-+
-+	return target_attr_ptr;
-+}
-+
-+/**
-+ * rtw_get_wfd_attr_content - Search a specific WFD attribute content from a given WFD IE
-+ * @wfd_ie: Address of WFD IE to search
-+ * @wfd_ielen: Length limit from wfd_ie
-+ * @target_attr_id: The attribute ID of WFD attribute to search
-+ * @buf_content: If not NULL and the WFD attribute is found, WFD attribute content will be copied to the buf starting from buf_content
-+ * @len_content: If not NULL and the WFD attribute is found, will set to the length of the WFD attribute content
-+ *
-+ * Returns: the address of the specific WFD attribute content found, or NULL
-+ */
-+u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content)
-+{
-+	u8 *attr_ptr;
-+	u32 attr_len;
-+
-+	if (len_content)
-+		*len_content = 0;
-+
-+	attr_ptr = rtw_get_wfd_attr(wfd_ie, wfd_ielen, target_attr_id, NULL, &attr_len);
-+
-+	if (attr_ptr && attr_len) {
-+		if (buf_content)
-+			_rtw_memcpy(buf_content, attr_ptr + 3, attr_len - 3);
-+
-+		if (len_content)
-+			*len_content = attr_len - 3;
-+
-+		return attr_ptr + 3;
-+	}
-+
-+	return NULL;
-+}
-+
-+uint rtw_del_wfd_attr(u8 *ie, uint ielen_ori, u8 attr_id)
-+{
-+#define DBG_DEL_WFD_ATTR 0
-+
-+	u8 *target_attr;
-+	u32 target_attr_len;
-+	uint ielen = ielen_ori;
-+	int index = 0;
-+
-+	while (1) {
-+		target_attr = rtw_get_wfd_attr(ie, ielen, attr_id, NULL, &target_attr_len);
-+		if (target_attr && target_attr_len) {
-+			u8 *next_attr = target_attr + target_attr_len;
-+			uint remain_len = ielen - (next_attr - ie);
-+
-+			if (DBG_DEL_WFD_ATTR) {
-+				RTW_INFO("%s %d before\n", __func__, index);
-+				dump_ies(RTW_DBGDUMP, ie, ielen);
-+
-+				RTW_INFO("ie:%p, ielen:%u\n", ie, ielen);
-+				RTW_INFO("target_attr:%p, target_attr_len:%u\n", target_attr, target_attr_len);
-+				RTW_INFO("next_attr:%p, remain_len:%u\n", next_attr, remain_len);
-+			}
-+
-+			_rtw_memmove(target_attr, next_attr, remain_len);
-+			_rtw_memset(target_attr + remain_len, 0, target_attr_len);
-+			*(ie + 1) -= target_attr_len;
-+			ielen -= target_attr_len;
-+
-+			if (DBG_DEL_WFD_ATTR) {
-+				RTW_INFO("%s %d after\n", __func__, index);
-+				dump_ies(RTW_DBGDUMP, ie, ielen);
-+			}
-+
-+			index++;
-+		} else
-+			break;
-+	}
-+
-+	return ielen;
-+}
-+
-+inline u8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ielen)
-+{
-+	return rtw_get_wfd_ie(BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex), wfd_ie, wfd_ielen);
-+}
-+
-+void rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id)
-+{
-+#define DBG_BSS_EX_DEL_WFD_ATTR 0
-+
-+	u8 *ies = BSS_EX_TLV_IES(bss_ex);
-+	uint ies_len = BSS_EX_TLV_IES_LEN(bss_ex);
-+
-+	u8 *ie;
-+	uint ie_len, ie_len_ori;
-+
-+	int index = 0;
-+
-+	while (1) {
-+		ie = rtw_get_wfd_ie(ies, ies_len, NULL, &ie_len_ori);
-+		if (ie) {
-+			u8 *next_ie_ori = ie + ie_len_ori;
-+			uint remain_len = bss_ex->IELength - (next_ie_ori - bss_ex->IEs);
-+			u8 has_target_attr = 0;
-+
-+			if (DBG_BSS_EX_DEL_WFD_ATTR) {
-+				if (rtw_get_wfd_attr(ie, ie_len_ori, attr_id, NULL, NULL)) {
-+					RTW_INFO("%s %d before\n", __func__, index);
-+					dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));
-+
-+					RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len);
-+					RTW_INFO("ie:%p, ie_len_ori:%u\n", ie, ie_len_ori);
-+					RTW_INFO("next_ie_ori:%p, remain_len:%u\n", next_ie_ori, remain_len);
-+					has_target_attr = 1;
-+				}
-+			}
-+
-+			ie_len = rtw_del_wfd_attr(ie, ie_len_ori, attr_id);
-+			if (ie_len != ie_len_ori) {
-+				u8 *next_ie = ie + ie_len;
-+
-+				_rtw_memmove(next_ie, next_ie_ori, remain_len);
-+				_rtw_memset(next_ie + remain_len, 0, ie_len_ori - ie_len);
-+				bss_ex->IELength -= ie_len_ori - ie_len;
-+
-+				ies = next_ie;
-+			} else
-+				ies = next_ie_ori;
-+
-+			if (DBG_BSS_EX_DEL_WFD_ATTR) {
-+				if (has_target_attr) {
-+					RTW_INFO("%s %d after\n", __func__, index);
-+					dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex));
-+				}
-+			}
-+
-+			ies_len = remain_len;
-+
-+			index++;
-+		} else
-+			break;
-+	}
-+}
-+#endif /*	CONFIG_WFD	*/
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+void dump_multi_ap_ie(void *sel, const u8 *ie, u32 ie_len)
-+{
-+	const u8 *pos = ie;
-+	u8 id;
-+	u8 len;
-+
-+	const u8 *multi_ap_ie;
-+	uint multi_ap_ielen;
-+
-+	multi_ap_ie = rtw_get_ie_ex(ie, ie_len, WLAN_EID_VENDOR_SPECIFIC, MULTI_AP_OUI, 4, NULL, &multi_ap_ielen);
-+	if (multi_ap_ie != ie || multi_ap_ielen == 0)
-+		return;
-+
-+	pos += 6;
-+	while (pos - ie + 2 <= ie_len) {
-+		id = *pos;
-+		len = *(pos + 1);
-+
-+		RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u%s\n", __func__, id, len
-+			, ((pos - ie + 2 + len) <= ie_len) ? "" : "(exceed ie_len)");
-+		RTW_DUMP_SEL(sel, pos + 2, len);
-+
-+		pos += (2 + len);
-+	}
-+}
-+
-+/**
-+ * rtw_get_multi_ap_ext - Search Multi-AP IE from a series of IEs and return extension subelement value
-+ * @ies: Address of IEs to search
-+ * @ies_len: Length limit from in_ie
-+ *
-+ * Returns: The address of the target IE found, or NULL
-+ */
-+u8 rtw_get_multi_ap_ie_ext(const u8 *ies, int ies_len)
-+{
-+	u8 *ie;
-+	uint ielen;
-+	u8 val = 0;
-+
-+	ie = rtw_get_ie_ex(ies, ies_len, WLAN_EID_VENDOR_SPECIFIC, MULTI_AP_OUI, 4, NULL, &ielen);
-+	if (ielen < 9)
-+		goto exit;
-+
-+	if (ie[6] != MULTI_AP_SUB_ELEM_TYPE)
-+		goto exit;
-+
-+	val = ie[8];
-+
-+exit:
-+	return val;
-+}
-+
-+u8 *rtw_set_multi_ap_ie_ext(u8 *pbuf, uint *frlen, u8 val)
-+{
-+	u8 cont_len = 7;
-+
-+	*pbuf++ = WLAN_EID_VENDOR_SPECIFIC;
-+	*pbuf++ = cont_len;
-+	_rtw_memcpy(pbuf, MULTI_AP_OUI, 4);
-+	pbuf += 4;
-+	*pbuf++ = MULTI_AP_SUB_ELEM_TYPE;
-+	*pbuf++ = 1; /* len */
-+	*pbuf++ = val;
-+
-+	if (frlen)
-+		*frlen = *frlen + (cont_len + 2);
-+
-+	return pbuf;
-+}
-+#endif /* CONFIG_RTW_MULTI_AP */
-+
-+/* Baron adds to avoid FreeBSD warning */
-+int ieee80211_is_empty_essid(const char *essid, int essid_len)
-+{
-+	/* Single white space is for Linksys APs */
-+	if (essid_len == 1 && essid[0] == ' ')
-+		return 1;
-+
-+	/* Otherwise, if the entire essid is 0, we assume it is hidden */
-+	while (essid_len) {
-+		essid_len--;
-+		if (essid[essid_len] != '\0')
-+			return 0;
-+	}
-+
-+	return 1;
-+}
-+
-+int ieee80211_get_hdrlen(u16 fc)
-+{
-+	int hdrlen = 24;
-+
-+	switch (WLAN_FC_GET_TYPE(fc)) {
-+	case RTW_IEEE80211_FTYPE_DATA:
-+		if (fc & RTW_IEEE80211_STYPE_QOS_DATA)
-+			hdrlen += 2;
-+		if ((fc & RTW_IEEE80211_FCTL_FROMDS) && (fc & RTW_IEEE80211_FCTL_TODS))
-+			hdrlen += 6; /* Addr4 */
-+		break;
-+	case RTW_IEEE80211_FTYPE_CTL:
-+		switch (WLAN_FC_GET_STYPE(fc)) {
-+		case RTW_IEEE80211_STYPE_CTS:
-+		case RTW_IEEE80211_STYPE_ACK:
-+			hdrlen = 10;
-+			break;
-+		default:
-+			hdrlen = 16;
-+			break;
-+		}
-+		break;
-+	}
-+
-+	return hdrlen;
-+}
-+
-+u8	rtw_ht_mcsset_to_nss(u8 *supp_mcs_set)
-+{
-+	u8 nss = 1;
-+
-+	if (supp_mcs_set[3])
-+		nss = 4;
-+	else if (supp_mcs_set[2])
-+		nss = 3;
-+	else if (supp_mcs_set[1])
-+		nss = 2;
-+	else if (supp_mcs_set[0])
-+		nss = 1;
-+	else
-+		RTW_INFO("%s,%d, warning! supp_mcs_set is zero\n", __func__, __LINE__);
-+	/* RTW_INFO("%s HT: %dSS\n", __FUNCTION__, nss); */
-+	return nss;
-+}
-+
-+u32	rtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss)
-+{
-+	u8 i;
-+	u32 bitmap = 0;
-+
-+	for (i = 0; i < nss; i++)
-+		bitmap |= mcs_set[i] << (i * 8);
-+
-+	RTW_INFO("ht_mcs_set=%02x %02x %02x %02x, nss=%u, bitmap=%08x\n"
-+		, mcs_set[0], mcs_set[1], mcs_set[2], mcs_set[3], nss, bitmap);
-+
-+	return bitmap;
-+}
-+
-+/* show MCS rate, unit: 100Kbps */
-+u16 rtw_ht_mcs_rate(u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate)
-+{
-+	u16 max_rate = 0;
-+
-+	if (MCS_rate[3]) {
-+		if (MCS_rate[3] & BIT(7))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 6000 : 5400) : ((short_GI) ? 2889 : 2600);
-+		else if (MCS_rate[3] & BIT(6))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 5400 : 4860) : ((short_GI) ? 2600 : 2340);
-+		else if (MCS_rate[3] & BIT(5))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 4800 : 4320) : ((short_GI) ? 2311 : 2080);
-+		else if (MCS_rate[3] & BIT(4))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 3600 : 3240) : ((short_GI) ? 1733 : 1560);
-+		else if (MCS_rate[3] & BIT(3))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 2400 : 2160) : ((short_GI) ? 1156 : 1040);
-+		else if (MCS_rate[3] & BIT(2))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780);
-+		else if (MCS_rate[3] & BIT(1))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520);
-+		else if (MCS_rate[3] & BIT(0))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260);
-+	} else if (MCS_rate[2]) {
-+		if (MCS_rate[2] & BIT(7))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 4500 : 4050) : ((short_GI) ? 2167 : 1950);
-+		else if (MCS_rate[2] & BIT(6))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 4050 : 3645) : ((short_GI) ? 1950 : 1750);
-+		else if (MCS_rate[2] & BIT(5))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 3600 : 3240) : ((short_GI) ? 1733 : 1560);
-+		else if (MCS_rate[2] & BIT(4))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 2700 : 2430) : ((short_GI) ? 1300 : 1170);
-+		else if (MCS_rate[2] & BIT(3))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780);
-+		else if (MCS_rate[2] & BIT(2))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 1350 : 1215) : ((short_GI) ? 650 : 585);
-+		else if (MCS_rate[2] & BIT(1))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390);
-+		else if (MCS_rate[2] & BIT(0))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 450 : 405) : ((short_GI) ? 217 : 195);
-+	} else if (MCS_rate[1]) {
-+		if (MCS_rate[1] & BIT(7))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 3000 : 2700) : ((short_GI) ? 1444 : 1300);
-+		else if (MCS_rate[1] & BIT(6))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 2700 : 2430) : ((short_GI) ? 1300 : 1170);
-+		else if (MCS_rate[1] & BIT(5))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 2400 : 2160) : ((short_GI) ? 1156 : 1040);
-+		else if (MCS_rate[1] & BIT(4))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780);
-+		else if (MCS_rate[1] & BIT(3))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520);
-+		else if (MCS_rate[1] & BIT(2))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390);
-+		else if (MCS_rate[1] & BIT(1))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260);
-+		else if (MCS_rate[1] & BIT(0))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130);
-+	} else {
-+		if (MCS_rate[0] & BIT(7))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 1500 : 1350) : ((short_GI) ? 722 : 650);
-+		else if (MCS_rate[0] & BIT(6))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 1350 : 1215) : ((short_GI) ? 650 : 585);
-+		else if (MCS_rate[0] & BIT(5))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520);
-+		else if (MCS_rate[0] & BIT(4))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390);
-+		else if (MCS_rate[0] & BIT(3))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260);
-+		else if (MCS_rate[0] & BIT(2))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 450 : 405) : ((short_GI) ? 217 : 195);
-+		else if (MCS_rate[0] & BIT(1))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130);
-+		else if (MCS_rate[0] & BIT(0))
-+			max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65);
-+	}
-+
-+	return max_rate;
-+}
-+
-+u8 rtw_ht_cap_get_rx_nss(u8 *ht_cap)
-+{
-+	u8 *ht_mcs_set = HT_CAP_ELE_SUP_MCS_SET(ht_cap);
-+
-+	return rtw_ht_mcsset_to_nss(ht_mcs_set);
-+}
-+
-+u8 rtw_ht_cap_get_tx_nss(u8 *ht_cap)
-+{
-+	u8 *ht_mcs_set = HT_CAP_ELE_SUP_MCS_SET(ht_cap);
-+
-+	if (GET_HT_CAP_ELE_TX_MCS_DEF(ht_cap) && GET_HT_CAP_ELE_TRX_MCS_NEQ(ht_cap))
-+		return GET_HT_CAP_ELE_TX_MAX_SS(ht_cap) + 1;
-+
-+	return rtw_ht_cap_get_rx_nss(ht_cap);
-+}
-+
-+int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8 *category, u8 *action)
-+{
-+	const u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	u16 fc;
-+	u8 c;
-+	u8 a = ACT_PUBLIC_MAX;
-+
-+	fc = le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)frame)->frame_ctl);
-+
-+	if ((fc & (RTW_IEEE80211_FCTL_FTYPE | RTW_IEEE80211_FCTL_STYPE))
-+	    != (RTW_IEEE80211_FTYPE_MGMT | RTW_IEEE80211_STYPE_ACTION)
-+	   )
-+		return _FALSE;
-+
-+	c = frame_body[0];
-+
-+	switch (c) {
-+	case RTW_WLAN_CATEGORY_P2P: /* vendor-specific */
-+		break;
-+	default:
-+		a = frame_body[1];
-+	}
-+
-+	if (category)
-+		*category = c;
-+	if (action)
-+		*action = a;
-+
-+	return _TRUE;
-+}
-+
-+static const char *_action_public_str[] = {
-+	[ACT_PUBLIC_BSSCOEXIST]				= "ACT_PUB_BSSCOEXIST",
-+	[ACT_PUBLIC_DSE_ENABLE]				= "ACT_PUB_DSE_ENABLE",
-+	[ACT_PUBLIC_DSE_DEENABLE]			= "ACT_PUB_DSE_DEENABLE",
-+	[ACT_PUBLIC_DSE_REG_LOCATION]		= "ACT_PUB_DSE_REG_LOCATION",
-+	[ACT_PUBLIC_EXT_CHL_SWITCH]			= "ACT_PUB_EXT_CHL_SWITCH",
-+	[ACT_PUBLIC_DSE_MSR_REQ]			= "ACT_PUB_DSE_MSR_REQ",
-+	[ACT_PUBLIC_DSE_MSR_RPRT]			= "ACT_PUB_DSE_MSR_RPRT",
-+	[ACT_PUBLIC_MP]						= "ACT_PUB_MP",
-+	[ACT_PUBLIC_DSE_PWR_CONSTRAINT]		= "ACT_PUB_DSE_PWR_CONSTRAINT",
-+	[ACT_PUBLIC_VENDOR]					= "ACT_PUB_VENDOR",
-+	[ACT_PUBLIC_GAS_INITIAL_REQ]		= "ACT_PUB_GAS_INITIAL_REQ",
-+	[ACT_PUBLIC_GAS_INITIAL_RSP]		= "ACT_PUB_GAS_INITIAL_RSP",
-+	[ACT_PUBLIC_GAS_COMEBACK_REQ]		= "ACT_PUB_GAS_COMEBACK_REQ",
-+	[ACT_PUBLIC_GAS_COMEBACK_RSP]		= "ACT_PUB_GAS_COMEBACK_RSP",
-+	[ACT_PUBLIC_TDLS_DISCOVERY_RSP]		= "ACT_PUB_TDLS_DISCOVERY_RSP",
-+	[ACT_PUBLIC_LOCATION_TRACK]			= "ACT_PUB_LOCATION_TRACK",
-+	[ACT_PUBLIC_QAB_REQ]				= "ACT_PUB_QAB_REQ",
-+	[ACT_PUBLIC_QAB_RSP]				= "ACT_PUB_QAB_RSP",
-+	[ACT_PUBLIC_QMF_POLICY]				= "ACT_PUB_QMF_POLICY",
-+	[ACT_PUBLIC_QMF_POLICY_CHANGE]		= "ACT_PUB_QMF_POLICY_CHANGE",
-+	[ACT_PUBLIC_QLOAD_REQ]				= "ACT_PUB_QLOAD_REQ",
-+	[ACT_PUBLIC_QLOAD_REPORT]			= "ACT_PUB_QLOAD_REPORT",
-+	[ACT_PUBLIC_HCCA_TXOP_ADV]			= "ACT_PUB_HCCA_TXOP_ADV",
-+	[ACT_PUBLIC_HCCA_TXOP_RSP]			= "ACT_PUB_HCCA_TXOP_RSP",
-+	[ACT_PUBLIC_PUBLIC_KEY]				= "ACT_PUB_PUBLIC_KEY",
-+	[ACT_PUBLIC_CH_AVAILABILITY_QUERY]	= "ACT_PUB_CH_AVAILABILITY_QUERY",
-+	[ACT_PUBLIC_CH_SCHEDULE_MGMT]		= "ACT_PUB_CH_SCHEDULE_MGMT",
-+	[ACT_PUBLIC_CONTACT_VERI_SIGNAL]	= "ACT_PUB_CONTACT_VERI_SIGNAL",
-+	[ACT_PUBLIC_GDD_ENABLE_REQ]			= "ACT_PUB_GDD_ENABLE_REQ",
-+	[ACT_PUBLIC_GDD_ENABLE_RSP]			= "ACT_PUB_GDD_ENABLE_RSP",
-+	[ACT_PUBLIC_NETWORK_CH_CONTROL]		= "ACT_PUB_NETWORK_CH_CONTROL",
-+	[ACT_PUBLIC_WHITE_SPACE_MAP_ANN]	= "ACT_PUB_WHITE_SPACE_MAP_ANN",
-+	[ACT_PUBLIC_FTM_REQ]				= "ACT_PUB_FTM_REQ",
-+	[ACT_PUBLIC_FTM]					= "ACT_PUB_FTM",
-+	[ACT_PUBLIC_MAX]					= "ACT_PUB_RSVD",
-+};
-+
-+const char *action_public_str(u8 action)
-+{
-+	action = (action >= ACT_PUBLIC_MAX) ? ACT_PUBLIC_MAX : action;
-+	return _action_public_str[action];
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/core/rtw_io.c b/drivers/staging/rtl8723cs/core/rtw_io.c
-new file mode 100644
-index 000000000000..734d3e591e0d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_io.c
-@@ -0,0 +1,952 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*
-+
-+The purpose of rtw_io.c
-+
-+a. provides the API
-+
-+b. provides the protocol engine
-+
-+c. provides the software interface between caller and the hardware interface
-+
-+
-+Compiler Flag Option:
-+
-+1. CONFIG_SDIO_HCI:
-+    a. USE_SYNC_IRP:  Only sync operations are provided.
-+    b. USE_ASYNC_IRP:Both sync/async operations are provided.
-+
-+2. CONFIG_USB_HCI:
-+   a. USE_ASYNC_IRP: Both sync/async operations are provided.
-+
-+3. CONFIG_CFIO_HCI:
-+   b. USE_SYNC_IRP: Only sync operations are provided.
-+
-+
-+Only sync read/rtw_write_mem operations are provided.
-+
-+jackson@realtek.com.tw
-+
-+*/
-+
-+#define _RTW_IO_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_PLATFORM_RTL8197D)
-+	#define rtw_le16_to_cpu(val)		val
-+	#define rtw_le32_to_cpu(val)		val
-+	#define rtw_cpu_to_le16(val)		val
-+	#define rtw_cpu_to_le32(val)		val
-+#else
-+	#define rtw_le16_to_cpu(val)		le16_to_cpu(val)
-+	#define rtw_le32_to_cpu(val)		le32_to_cpu(val)
-+	#define rtw_cpu_to_le16(val)		cpu_to_le16(val)
-+	#define rtw_cpu_to_le32(val)		cpu_to_le32(val)
-+#endif
-+
-+
-+u8 _rtw_read8(_adapter *adapter, u32 addr)
-+{
-+	u8 r_val;
-+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-+	u8(*_read8)(struct intf_hdl *pintfhdl, u32 addr);
-+	_read8 = pintfhdl->io_ops._read8;
-+
-+	r_val = _read8(pintfhdl, addr);
-+	return r_val;
-+}
-+
-+u16 _rtw_read16(_adapter *adapter, u32 addr)
-+{
-+	u16 r_val;
-+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-+	u16(*_read16)(struct intf_hdl *pintfhdl, u32 addr);
-+	_read16 = pintfhdl->io_ops._read16;
-+
-+	r_val = _read16(pintfhdl, addr);
-+	return rtw_le16_to_cpu(r_val);
-+}
-+
-+u32 _rtw_read32(_adapter *adapter, u32 addr)
-+{
-+	u32 r_val;
-+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-+	u32(*_read32)(struct intf_hdl *pintfhdl, u32 addr);
-+	_read32 = pintfhdl->io_ops._read32;
-+
-+	r_val = _read32(pintfhdl, addr);
-+	return rtw_le32_to_cpu(r_val);
-+
-+}
-+
-+int _rtw_write8(_adapter *adapter, u32 addr, u8 val)
-+{
-+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-+	int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
-+	int ret;
-+	_write8 = pintfhdl->io_ops._write8;
-+
-+	ret = _write8(pintfhdl, addr, val);
-+
-+	return RTW_STATUS_CODE(ret);
-+}
-+int _rtw_write16(_adapter *adapter, u32 addr, u16 val)
-+{
-+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-+	int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
-+	int ret;
-+	_write16 = pintfhdl->io_ops._write16;
-+
-+	val = rtw_cpu_to_le16(val);
-+	ret = _write16(pintfhdl, addr, val);
-+
-+	return RTW_STATUS_CODE(ret);
-+}
-+int _rtw_write32(_adapter *adapter, u32 addr, u32 val)
-+{
-+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-+	int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
-+	int ret;
-+	_write32 = pintfhdl->io_ops._write32;
-+
-+	val = rtw_cpu_to_le32(val);
-+	ret = _write32(pintfhdl, addr, val);
-+
-+	return RTW_STATUS_CODE(ret);
-+}
-+
-+int _rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *pdata)
-+{
-+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct	intf_hdl	*pintfhdl = (struct intf_hdl *)(&(pio_priv->intf));
-+	int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
-+	int ret;
-+	_writeN = pintfhdl->io_ops._writeN;
-+
-+	ret = _writeN(pintfhdl, addr, length, pdata);
-+
-+	return RTW_STATUS_CODE(ret);
-+}
-+
-+#ifdef CONFIG_SDIO_HCI
-+u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr)
-+{
-+	u8 r_val = 0x00;
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
-+	u8(*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr);
-+
-+	_sd_f0_read8 = pintfhdl->io_ops._sd_f0_read8;
-+
-+	if (_sd_f0_read8)
-+		r_val = _sd_f0_read8(pintfhdl, addr);
-+	else
-+		RTW_WARN(FUNC_ADPT_FMT" _sd_f0_read8 callback is NULL\n", FUNC_ADPT_ARG(adapter));
-+
-+	return r_val;
-+}
-+
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+u8 _rtw_sd_iread8(_adapter *adapter, u32 addr)
-+{
-+	u8 r_val = 0x00;
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
-+	u8(*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr);
-+
-+	_sd_iread8 = pintfhdl->io_ops._sd_iread8;
-+
-+	if (_sd_iread8)
-+		r_val = _sd_iread8(pintfhdl, addr);
-+	else
-+		RTW_ERR(FUNC_ADPT_FMT" _sd_iread8 callback is NULL\n", FUNC_ADPT_ARG(adapter));
-+
-+	return r_val;
-+}
-+
-+u16 _rtw_sd_iread16(_adapter *adapter, u32 addr)
-+{
-+	u16 r_val = 0x00;
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
-+	u16(*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr);
-+
-+	_sd_iread16 = pintfhdl->io_ops._sd_iread16;
-+
-+	if (_sd_iread16)
-+		r_val = _sd_iread16(pintfhdl, addr);
-+	else
-+		RTW_ERR(FUNC_ADPT_FMT" _sd_iread16 callback is NULL\n", FUNC_ADPT_ARG(adapter));
-+
-+	return r_val;
-+}
-+
-+u32 _rtw_sd_iread32(_adapter *adapter, u32 addr)
-+{
-+	u32 r_val = 0x00;
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
-+	u32(*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr);
-+
-+	_sd_iread32 = pintfhdl->io_ops._sd_iread32;
-+
-+	if (_sd_iread32)
-+		r_val = _sd_iread32(pintfhdl, addr);
-+	else
-+		RTW_ERR(FUNC_ADPT_FMT" _sd_iread32 callback is NULL\n", FUNC_ADPT_ARG(adapter));
-+
-+	return r_val;
-+}
-+
-+int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val)
-+{
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
-+	int (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
-+	int ret = -1;
-+
-+	_sd_iwrite8 = pintfhdl->io_ops._sd_iwrite8;
-+
-+	if (_sd_iwrite8)
-+		ret = _sd_iwrite8(pintfhdl, addr, val);
-+	else
-+		RTW_ERR(FUNC_ADPT_FMT" _sd_iwrite8 callback is NULL\n", FUNC_ADPT_ARG(adapter));
-+
-+	return RTW_STATUS_CODE(ret);
-+}
-+
-+int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val)
-+{
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
-+	int (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
-+	int ret = -1;
-+
-+	_sd_iwrite16 = pintfhdl->io_ops._sd_iwrite16;
-+
-+	if (_sd_iwrite16)
-+		ret = _sd_iwrite16(pintfhdl, addr, val);
-+	else
-+		RTW_ERR(FUNC_ADPT_FMT" _sd_iwrite16 callback is NULL\n", FUNC_ADPT_ARG(adapter));
-+
-+	return RTW_STATUS_CODE(ret);
-+}
-+int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val)
-+{
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
-+	int (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
-+	int ret = -1;
-+
-+	_sd_iwrite32 = pintfhdl->io_ops._sd_iwrite32;
-+
-+	if (_sd_iwrite32)
-+		ret = _sd_iwrite32(pintfhdl, addr, val);
-+	else
-+		RTW_ERR(FUNC_ADPT_FMT" _sd_iwrite32 callback is NULL\n", FUNC_ADPT_ARG(adapter));
-+
-+	return RTW_STATUS_CODE(ret);
-+}
-+
-+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
-+
-+#endif /* CONFIG_SDIO_HCI */
-+
-+int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val)
-+{
-+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-+	int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
-+	int ret;
-+	_write8_async = pintfhdl->io_ops._write8_async;
-+
-+	ret = _write8_async(pintfhdl, addr, val);
-+
-+	return RTW_STATUS_CODE(ret);
-+}
-+int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val)
-+{
-+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-+	int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
-+	int ret;
-+	_write16_async = pintfhdl->io_ops._write16_async;
-+	val = rtw_cpu_to_le16(val);
-+	ret = _write16_async(pintfhdl, addr, val);
-+
-+	return RTW_STATUS_CODE(ret);
-+}
-+int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val)
-+{
-+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-+	int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
-+	int ret;
-+	_write32_async = pintfhdl->io_ops._write32_async;
-+	val = rtw_cpu_to_le32(val);
-+	ret = _write32_async(pintfhdl, addr, val);
-+
-+	return RTW_STATUS_CODE(ret);
-+}
-+
-+void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
-+{
-+	void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
-+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-+
-+
-+	if (RTW_CANNOT_RUN(adapter)) {
-+		return;
-+	}
-+
-+	_read_mem = pintfhdl->io_ops._read_mem;
-+
-+	_read_mem(pintfhdl, addr, cnt, pmem);
-+
-+
-+}
-+
-+void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
-+{
-+	void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
-+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-+
-+
-+	_write_mem = pintfhdl->io_ops._write_mem;
-+
-+	_write_mem(pintfhdl, addr, cnt, pmem);
-+
-+
-+}
-+
-+void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
-+{
-+	u32(*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
-+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-+
-+
-+	if (RTW_CANNOT_RUN(adapter)) {
-+		return;
-+	}
-+
-+	_read_port = pintfhdl->io_ops._read_port;
-+
-+	_read_port(pintfhdl, addr, cnt, pmem);
-+
-+
-+}
-+
-+void _rtw_read_port_cancel(_adapter *adapter)
-+{
-+	void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
-+
-+	_read_port_cancel = pintfhdl->io_ops._read_port_cancel;
-+
-+	RTW_DISABLE_FUNC(adapter, DF_RX_BIT);
-+
-+	if (_read_port_cancel)
-+		_read_port_cancel(pintfhdl);
-+}
-+
-+u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
-+{
-+	u32(*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
-+	/* struct	io_queue  	*pio_queue = (struct io_queue *)adapter->pio_queue; */
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct	intf_hdl		*pintfhdl = &(pio_priv->intf);
-+	u32 ret = _SUCCESS;
-+
-+
-+	_write_port = pintfhdl->io_ops._write_port;
-+
-+	ret = _write_port(pintfhdl, addr, cnt, pmem);
-+
-+
-+	return ret;
-+}
-+
-+u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms)
-+{
-+	int ret = _SUCCESS;
-+	struct xmit_buf *pxmitbuf = (struct xmit_buf *)pmem;
-+	struct submit_ctx sctx;
-+
-+	rtw_sctx_init(&sctx, timeout_ms);
-+	pxmitbuf->sctx = &sctx;
-+
-+	ret = _rtw_write_port(adapter, addr, cnt, pmem);
-+
-+	if (ret == _SUCCESS) {
-+		ret = rtw_sctx_wait(&sctx, __func__);
-+
-+		if (ret != _SUCCESS)
-+			pxmitbuf->sctx = NULL;
-+	}
-+
-+	return ret;
-+}
-+
-+void _rtw_write_port_cancel(_adapter *adapter)
-+{
-+	void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
-+	struct io_priv *pio_priv = &adapter->iopriv;
-+	struct intf_hdl *pintfhdl = &(pio_priv->intf);
-+
-+	_write_port_cancel = pintfhdl->io_ops._write_port_cancel;
-+
-+	RTW_DISABLE_FUNC(adapter, DF_TX_BIT);
-+
-+	if (_write_port_cancel)
-+		_write_port_cancel(pintfhdl);
-+}
-+int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter, struct _io_ops *pops))
-+{
-+	struct io_priv	*piopriv = &padapter->iopriv;
-+	struct intf_hdl *pintf = &piopriv->intf;
-+
-+	if (set_intf_ops == NULL)
-+		return _FAIL;
-+
-+	piopriv->padapter = padapter;
-+	pintf->padapter = padapter;
-+	pintf->pintf_dev = adapter_to_dvobj(padapter);
-+
-+	set_intf_ops(padapter, &pintf->io_ops);
-+
-+	return _SUCCESS;
-+}
-+
-+/*
-+* Increase and check if the continual_io_error of this @param dvobjprive is larger than MAX_CONTINUAL_IO_ERR
-+* @return _TRUE:
-+* @return _FALSE:
-+*/
-+int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj)
-+{
-+	int ret = _FALSE;
-+	int value;
-+
-+	value = ATOMIC_INC_RETURN(&dvobj->continual_io_error);
-+	if (value > MAX_CONTINUAL_IO_ERR) {
-+		RTW_INFO("[dvobj:%p][ERROR] continual_io_error:%d > %d\n", dvobj, value, MAX_CONTINUAL_IO_ERR);
-+		ret = _TRUE;
-+	} else {
-+		/* RTW_INFO("[dvobj:%p] continual_io_error:%d\n", dvobj, value); */
-+	}
-+	return ret;
-+}
-+
-+/*
-+* Set the continual_io_error of this @param dvobjprive to 0
-+*/
-+void rtw_reset_continual_io_error(struct dvobj_priv *dvobj)
-+{
-+	ATOMIC_SET(&dvobj->continual_io_error, 0);
-+}
-+
-+#ifdef DBG_IO
-+#define RTW_IO_SNIFF_TYPE_RANGE	0 /* specific address range is accessed */
-+#define RTW_IO_SNIFF_TYPE_VALUE	1 /* value match for sniffed range */
-+
-+struct rtw_io_sniff_ent {
-+	u8 chip;
-+	u8 hci;
-+	u32 addr;
-+	u8 type;
-+	union {
-+		u32 end_addr;
-+		struct {
-+			u32 mask;
-+			u32 val;
-+			bool equal;
-+		} vm; /* value match */
-+	} u;
-+	bool trace;
-+	char *tag;
-+	bool (*assert_protsel)(_adapter *adapter, u32 addr, u8 len);
-+};
-+
-+#define RTW_IO_SNIFF_RANGE_ENT(_chip, _hci, _addr, _end_addr, _trace, _tag) \
-+	{.chip = _chip, .hci = _hci, .addr = _addr, .u.end_addr = _end_addr, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_RANGE,}
-+
-+#define RTW_IO_SNIFF_RANGE_PROT_ENT(_chip, _hci, _addr, _end_addr, _assert_protsel, _tag) \
-+	{.chip = _chip, .hci = _hci, .addr = _addr, .u.end_addr = _end_addr, .trace = 1, .assert_protsel = _assert_protsel, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_RANGE,}
-+
-+#define RTW_IO_SNIFF_VALUE_ENT(_chip, _hci, _addr, _mask, _val, _equal, _trace, _tag) \
-+	{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = _val, .u.vm.equal = _equal, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}
-+
-+/* part or all sniffed range is enabled (not all 0) */
-+#define RTW_IO_SNIFF_EN_ENT(_chip, _hci, _addr, _mask, _trace, _tag) \
-+	{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = 0, .u.vm.equal = 0, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}
-+
-+/* part or all sniffed range is disabled (not all 1) */
-+#define RTW_IO_SNIFF_DIS_ENT(_chip, _hci, _addr, _mask, _trace, _tag) \
-+	{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = 0xFFFFFFFF, .u.vm.equal = 0, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}
-+
-+const struct rtw_io_sniff_ent read_sniff[] = {
-+#ifdef DBG_IO_HCI_EN_CHK
-+	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_SDIO, 0x02, 0x1FC, 1, "SDIO 0x02[8:2] not all 0"),
-+	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_USB, 0x02, 0x1E0, 1, "USB 0x02[8:5] not all 0"),
-+	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_PCIE, 0x02, 0x01C, 1, "PCI 0x02[4:2] not all 0"),
-+#endif
-+#ifdef DBG_IO_SNIFF_EXAMPLE
-+	RTW_IO_SNIFF_RANGE_ENT(MAX_CHIP_TYPE, 0, 0x522, 0x522, 0, "read TXPAUSE"),
-+	RTW_IO_SNIFF_DIS_ENT(MAX_CHIP_TYPE, 0, 0x02, 0x3, 0, "0x02[1:0] not all 1"),
-+#endif
-+#ifdef DBG_IO_PROT_SEL
-+	RTW_IO_SNIFF_RANGE_PROT_ENT(MAX_CHIP_TYPE, 0, 0x1501, 0x1513, rtw_assert_protsel_port, "protsel port"),
-+	RTW_IO_SNIFF_RANGE_PROT_ENT(MAX_CHIP_TYPE, 0, 0x153a, 0x153b, rtw_assert_protsel_atimdtim, "protsel atimdtim"),
-+#endif
-+};
-+
-+const int read_sniff_num = sizeof(read_sniff) / sizeof(struct rtw_io_sniff_ent);
-+
-+const struct rtw_io_sniff_ent write_sniff[] = {
-+#ifdef DBG_IO_HCI_EN_CHK
-+	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_SDIO, 0x02, 0x1FC, 1, "SDIO 0x02[8:2] not all 0"),
-+	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_USB, 0x02, 0x1E0, 1, "USB 0x02[8:5] not all 0"),
-+	RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_PCIE, 0x02, 0x01C, 1, "PCI 0x02[4:2] not all 0"),
-+#endif
-+#ifdef DBG_IO_8822C_1TX_PATH_EN
-+	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x1a04, 0xc0000000, 0x02, 1, 0, "write tx_path_en_cck A enabled"),
-+	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x1a04, 0xc0000000, 0x01, 1, 0, "write tx_path_en_cck B enabled"),
-+	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x1a04, 0xc0000000, 0x03, 1, 1, "write tx_path_en_cck AB enabled"),
-+	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x03, 0x01, 1, 0, "write tx_path_en_ofdm_1sts A enabled"),
-+	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x03, 0x02, 1, 0, "write tx_path_en_ofdm_1sts B enabled"),
-+	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x03, 0x03, 1, 1, "write tx_path_en_ofdm_1sts AB enabled"),
-+	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x30, 0x01, 1, 0, "write tx_path_en_ofdm_2sts A enabled"),
-+	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x30, 0x02, 1, 0, "write tx_path_en_ofdm_2sts B enabled"),
-+	RTW_IO_SNIFF_VALUE_ENT(RTL8822C, 0, 0x820, 0x30, 0x03, 1, 1, "write tx_path_en_ofdm_2sts AB enabled"),
-+#endif
-+#ifdef DBG_IO_SNIFF_EXAMPLE
-+	RTW_IO_SNIFF_RANGE_ENT(MAX_CHIP_TYPE, 0, 0x522, 0x522, 0, "write TXPAUSE"),
-+	RTW_IO_SNIFF_DIS_ENT(MAX_CHIP_TYPE, 0, 0x02, 0x3, 0, "0x02[1:0] not all 1"),
-+#endif
-+};
-+
-+const int write_sniff_num = sizeof(write_sniff) / sizeof(struct rtw_io_sniff_ent);
-+
-+static bool match_io_sniff_ranges(_adapter *adapter
-+	, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u16 len)
-+{
-+
-+	/* check if IO range after sniff end address */
-+	if (addr > sniff->u.end_addr)
-+		return 0;
-+
-+	if (sniff->assert_protsel &&
-+	    sniff->assert_protsel(adapter, addr, len))
-+		return 0;
-+
-+	return 1;
-+}
-+
-+static bool match_io_sniff_value(_adapter *adapter
-+	, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val)
-+{
-+	u8 sniff_len;
-+	s8 mask_shift;
-+	u32 mask;
-+	s8 value_shift;
-+	u32 value;
-+	bool ret = 0;
-+
-+	/* check if IO range after sniff end address */
-+	sniff_len = 4;
-+	while (!(sniff->u.vm.mask & (0xFF << ((sniff_len - 1) * 8)))) {
-+		sniff_len--;
-+		if (sniff_len == 0)
-+			goto exit;
-+	}
-+	if (sniff->addr + sniff_len <= addr)
-+		goto exit;
-+
-+	/* align to IO addr */
-+	mask_shift = (sniff->addr - addr) * 8;
-+	value_shift = mask_shift + bitshift(sniff->u.vm.mask);
-+	if (mask_shift > 0)
-+		mask = sniff->u.vm.mask << mask_shift;
-+	else if (mask_shift < 0)
-+		mask = sniff->u.vm.mask >> -mask_shift;
-+	else
-+		mask = sniff->u.vm.mask;
-+
-+	if (value_shift > 0)
-+		value = sniff->u.vm.val << value_shift;
-+	else if (mask_shift < 0)
-+		value = sniff->u.vm.val >> -value_shift;
-+	else
-+		value = sniff->u.vm.val;
-+
-+	if ((sniff->u.vm.equal && (mask & val) == (mask & value))
-+		|| (!sniff->u.vm.equal && (mask & val) != (mask & value))
-+	) {
-+		ret = 1;
-+		if (0)
-+			RTW_INFO(FUNC_ADPT_FMT" addr:0x%x len:%u val:0x%x (i:%d sniff_len:%u m_shift:%d mask:0x%x v_shifd:%d value:0x%x equal:%d)\n"
-+				, FUNC_ADPT_ARG(adapter), addr, len, val, i, sniff_len, mask_shift, mask, value_shift, value, sniff->u.vm.equal);
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+static bool match_io_sniff(_adapter *adapter
-+	, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val)
-+{
-+	bool ret = 0;
-+
-+	if (sniff->chip != MAX_CHIP_TYPE
-+		&& sniff->chip != rtw_get_chip_type(adapter))
-+		goto exit;
-+	if (sniff->hci
-+		&& !(sniff->hci & rtw_get_intf_type(adapter)))
-+		goto exit;
-+	if (sniff->addr >= addr + len) /* IO range below sniff start address */
-+		goto exit;
-+
-+	switch (sniff->type) {
-+	case RTW_IO_SNIFF_TYPE_RANGE:
-+		ret = match_io_sniff_ranges(adapter, sniff, i, addr, len);
-+		break;
-+	case RTW_IO_SNIFF_TYPE_VALUE:
-+		if (len == 1 || len == 2 || len == 4)
-+			ret = match_io_sniff_value(adapter, sniff, i, addr, len, val);
-+		break;
-+	default:
-+		rtw_warn_on(1);
-+		break;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+u32 match_read_sniff(_adapter *adapter, u32 addr, u16 len, u32 val)
-+{
-+	int i;
-+	bool trace = 0;
-+	u32 match = 0;
-+
-+	for (i = 0; i < read_sniff_num; i++) {
-+		if (match_io_sniff(adapter, &read_sniff[i], i, addr, len, val)) {
-+			match++;
-+			trace |= read_sniff[i].trace;
-+			if (read_sniff[i].tag)
-+				RTW_INFO("DBG_IO TAG %s\n", read_sniff[i].tag);
-+		}
-+	}
-+
-+	rtw_warn_on(trace);
-+
-+	return match;
-+}
-+
-+u32 match_write_sniff(_adapter *adapter, u32 addr, u16 len, u32 val)
-+{
-+	int i;
-+	bool trace = 0;
-+	u32 match = 0;
-+
-+	for (i = 0; i < write_sniff_num; i++) {
-+		if (match_io_sniff(adapter, &write_sniff[i], i, addr, len, val)) {
-+			match++;
-+			trace |= write_sniff[i].trace;
-+			if (write_sniff[i].tag)
-+				RTW_INFO("DBG_IO TAG %s\n", write_sniff[i].tag);
-+		}
-+	}
-+
-+	rtw_warn_on(trace);
-+
-+	return match;
-+}
-+
-+struct rf_sniff_ent {
-+	u8 path;
-+	u16 reg;
-+	u32 mask;
-+};
-+
-+struct rf_sniff_ent rf_read_sniff_ranges[] = {
-+	/* example for all path addr 0x55 with all RF Reg mask */
-+	/* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */
-+};
-+
-+struct rf_sniff_ent rf_write_sniff_ranges[] = {
-+	/* example for all path addr 0x55 with all RF Reg mask */
-+	/* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */
-+};
-+
-+int rf_read_sniff_num = sizeof(rf_read_sniff_ranges) / sizeof(struct rf_sniff_ent);
-+int rf_write_sniff_num = sizeof(rf_write_sniff_ranges) / sizeof(struct rf_sniff_ent);
-+
-+bool match_rf_read_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask)
-+{
-+	int i;
-+
-+	for (i = 0; i < rf_read_sniff_num; i++) {
-+		if (rf_read_sniff_ranges[i].path == MAX_RF_PATH || rf_read_sniff_ranges[i].path == path)
-+			if (addr == rf_read_sniff_ranges[i].reg && (mask & rf_read_sniff_ranges[i].mask))
-+				return _TRUE;
-+	}
-+
-+	return _FALSE;
-+}
-+
-+bool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask)
-+{
-+	int i;
-+
-+	for (i = 0; i < rf_write_sniff_num; i++) {
-+		if (rf_write_sniff_ranges[i].path == MAX_RF_PATH || rf_write_sniff_ranges[i].path == path)
-+			if (addr == rf_write_sniff_ranges[i].reg && (mask & rf_write_sniff_ranges[i].mask))
-+				return _TRUE;
-+	}
-+
-+	return _FALSE;
-+}
-+
-+void dbg_rtw_reg_read_monitor(_adapter *adapter, u32 addr, u32 len, u32 val, const char *caller, const int line)
-+{
-+	if (match_read_sniff(adapter, addr, len, val)) {
-+		switch (len) {
-+		case 1:
-+			RTW_INFO("DBG_IO %s:%d read8(0x%04x) return 0x%02x\n"
-+				, caller, line, addr, val);
-+			break;
-+		case 2:
-+			RTW_INFO("DBG_IO %s:%d read16(0x%04x) return 0x%04x\n"
-+				, caller, line, addr, val);
-+			break;
-+		case 4:
-+			RTW_INFO("DBG_IO %s:%d read32(0x%04x) return 0x%08x\n"
-+				, caller, line, addr, val);
-+			break;
-+		default:
-+			RTW_INFO("DBG_IO %s:%d readN(0x%04x, %u)\n"
-+				, caller, line, addr, len);
-+		}
-+	}
-+}
-+
-+void dbg_rtw_reg_write_monitor(_adapter *adapter, u32 addr, u32 len, u32 val, const char *caller, const int line)
-+{
-+	if (match_write_sniff(adapter, addr, len, val)) {
-+		switch (len) {
-+		case 1:
-+			RTW_INFO("DBG_IO %s:%d write8(0x%04x, 0x%02x)\n"
-+				, caller, line, addr, val);
-+			break;
-+		case 2:
-+			RTW_INFO("DBG_IO %s:%d write16(0x%04x, 0x%04x)\n"
-+				, caller, line, addr, val);
-+			break;
-+		case 4:
-+			RTW_INFO("DBG_IO %s:%d write32(0x%04x, 0x%08x)\n"
-+				, caller, line, addr, val);
-+			break;
-+		default:
-+			RTW_INFO("DBG_IO %s:%d rtw_writeN(0x%04x, %u)\n"
-+				, caller, line, addr, len);
-+		}
-+	}
-+}
-+
-+u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line)
-+{
-+	u8 val = _rtw_read8(adapter, addr);
-+
-+	if (match_read_sniff(adapter, addr, 1, val)) {
-+		RTW_INFO("DBG_IO %s:%d rtw_read8(0x%04x) return 0x%02x\n"
-+			, caller, line, addr, val);
-+	}
-+
-+	return val;
-+}
-+
-+u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line)
-+{
-+	u16 val = _rtw_read16(adapter, addr);
-+
-+	if (match_read_sniff(adapter, addr, 2, val)) {
-+		RTW_INFO("DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x\n"
-+			, caller, line, addr, val);
-+	}
-+
-+	return val;
-+}
-+
-+u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line)
-+{
-+	u32 val = _rtw_read32(adapter, addr);
-+
-+	if (match_read_sniff(adapter, addr, 4, val)) {
-+		RTW_INFO("DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x\n"
-+			, caller, line, addr, val);
-+	}
-+
-+	return val;
-+}
-+
-+int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line)
-+{
-+	if (match_write_sniff(adapter, addr, 1, val)) {
-+		RTW_INFO("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x)\n"
-+			, caller, line, addr, val);
-+	}
-+
-+	return _rtw_write8(adapter, addr, val);
-+}
-+int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)
-+{
-+	if (match_write_sniff(adapter, addr, 2, val)) {
-+		RTW_INFO("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x)\n"
-+			, caller, line, addr, val);
-+	}
-+
-+	return _rtw_write16(adapter, addr, val);
-+}
-+int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)
-+{
-+	if (match_write_sniff(adapter, addr, 4, val)) {
-+		RTW_INFO("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x)\n"
-+			, caller, line, addr, val);
-+	}
-+
-+	return _rtw_write32(adapter, addr, val);
-+}
-+int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line)
-+{
-+	if (match_write_sniff(adapter, addr, length, 0)) {
-+		RTW_INFO("DBG_IO %s:%d rtw_writeN(0x%04x, %u)\n"
-+			, caller, line, addr, length);
-+	}
-+
-+	return _rtw_writeN(adapter, addr, length, data);
-+}
-+
-+#ifdef CONFIG_SDIO_HCI
-+u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line)
-+{
-+	u8 val = _rtw_sd_f0_read8(adapter, addr);
-+
-+#if 0
-+	if (match_read_sniff(adapter, addr, 1, val)) {
-+		RTW_INFO("DBG_IO %s:%d rtw_sd_f0_read8(0x%04x) return 0x%02x\n"
-+			, caller, line, addr, val);
-+	}
-+#endif
-+
-+	return val;
-+}
-+
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line)
-+{
-+	u8 val = rtw_sd_iread8(adapter, addr);
-+
-+	if (match_read_sniff(adapter, addr, 1, val)) {
-+		RTW_INFO("DBG_IO %s:%d rtw_sd_iread8(0x%04x) return 0x%02x\n"
-+			, caller, line, addr, val);
-+	}
-+
-+	return val;
-+}
-+
-+u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line)
-+{
-+	u16 val = _rtw_sd_iread16(adapter, addr);
-+
-+	if (match_read_sniff(adapter, addr, 2, val)) {
-+		RTW_INFO("DBG_IO %s:%d rtw_sd_iread16(0x%04x) return 0x%04x\n"
-+			, caller, line, addr, val);
-+	}
-+
-+	return val;
-+}
-+
-+u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line)
-+{
-+	u32 val = _rtw_sd_iread32(adapter, addr);
-+
-+	if (match_read_sniff(adapter, addr, 4, val)) {
-+		RTW_INFO("DBG_IO %s:%d rtw_sd_iread32(0x%04x) return 0x%08x\n"
-+			, caller, line, addr, val);
-+	}
-+
-+	return val;
-+}
-+
-+int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line)
-+{
-+	if (match_write_sniff(adapter, addr, 1, val)) {
-+		RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite8(0x%04x, 0x%02x)\n"
-+			, caller, line, addr, val);
-+	}
-+
-+	return _rtw_sd_iwrite8(adapter, addr, val);
-+}
-+int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)
-+{
-+	if (match_write_sniff(adapter, addr, 2, val)) {
-+		RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite16(0x%04x, 0x%04x)\n"
-+			, caller, line, addr, val);
-+	}
-+
-+	return _rtw_sd_iwrite16(adapter, addr, val);
-+}
-+int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)
-+{
-+	if (match_write_sniff(adapter, addr, 4, val)) {
-+		RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite32(0x%04x, 0x%08x)\n"
-+			, caller, line, addr, val);
-+	}
-+
-+	return _rtw_sd_iwrite32(adapter, addr, val);
-+}
-+
-+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
-+
-+#endif /* CONFIG_SDIO_HCI */
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/core/rtw_ioctl_query.c b/drivers/staging/rtl8723cs/core/rtw_ioctl_query.c
-new file mode 100644
-index 000000000000..939213843584
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_ioctl_query.c
-@@ -0,0 +1,19 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_IOCTL_QUERY_C_
-+
-+#include <drv_types.h>
-+
-+
-diff --git a/drivers/staging/rtl8723cs/core/rtw_ioctl_set.c b/drivers/staging/rtl8723cs/core/rtw_ioctl_set.c
-new file mode 100644
-index 000000000000..060546ce99b6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_ioctl_set.c
-@@ -0,0 +1,929 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_IOCTL_SET_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+
-+extern void indicate_wx_scan_complete_event(_adapter *padapter);
-+
-+#define IS_MAC_ADDRESS_BROADCAST(addr) \
-+	(\
-+	 ((addr[0] == 0xff) && (addr[1] == 0xff) && \
-+	  (addr[2] == 0xff) && (addr[3] == 0xff) && \
-+	  (addr[4] == 0xff) && (addr[5] == 0xff)) ? _TRUE : _FALSE \
-+	)
-+
-+u8 rtw_validate_bssid(u8 *bssid)
-+{
-+	u8 ret = _TRUE;
-+
-+	if (is_zero_mac_addr(bssid)
-+	    || is_broadcast_mac_addr(bssid)
-+	    || is_multicast_mac_addr(bssid)
-+	   )
-+		ret = _FALSE;
-+
-+	return ret;
-+}
-+
-+u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid)
-+{
-+#ifdef CONFIG_VALIDATE_SSID
-+	u8	 i;
-+#endif
-+	u8	ret = _TRUE;
-+
-+
-+	if (ssid->SsidLength > 32) {
-+		ret = _FALSE;
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_VALIDATE_SSID
-+	for (i = 0; i < ssid->SsidLength; i++) {
-+		/* wifi, printable ascii code must be supported */
-+		if (!((ssid->Ssid[i] >= 0x20) && (ssid->Ssid[i] <= 0x7e))) {
-+			ret = _FALSE;
-+			break;
-+		}
-+	}
-+#endif /* CONFIG_VALIDATE_SSID */
-+
-+exit:
-+
-+
-+	return ret;
-+}
-+
-+u8 rtw_do_join(_adapter *padapter);
-+u8 rtw_do_join(_adapter *padapter)
-+{
-+	_irqL	irqL;
-+	_list	*plist, *phead;
-+	u8 *pibss = NULL;
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct sitesurvey_parm parm;
-+	_queue	*queue	= &(pmlmepriv->scanned_queue);
-+	u8 ret = _SUCCESS;
-+
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+
-+	pmlmepriv->cur_network.join_res = -2;
-+
-+	set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
-+
-+	pmlmepriv->pscanned = plist;
-+
-+	pmlmepriv->to_join = _TRUE;
-+
-+	rtw_init_sitesurvey_parm(padapter, &parm);
-+	_rtw_memcpy(&parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
-+	parm.ssid_num = 1;
-+
-+	if (pmlmepriv->assoc_ch) {
-+		parm.ch_num = 1;
-+		parm.ch[0].hw_value = pmlmepriv->assoc_ch;
-+		parm.ch[0].flags = 0;
-+	}
-+
-+	if (_rtw_queue_empty(queue) == _TRUE) {
-+		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+		_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
-+
-+		/* when set_ssid/set_bssid for rtw_do_join(), but scanning queue is empty */
-+		/* we try to issue sitesurvey firstly	 */
-+
-+		if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE
-+		    || rtw_to_roam(padapter) > 0
-+		   ) {
-+			u8 ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
-+
-+			if ((ssc_chk == SS_ALLOW) || (ssc_chk == SS_DENY_BUSY_TRAFFIC) ){
-+				/* submit site_survey_cmd */
-+				ret = rtw_sitesurvey_cmd(padapter, &parm);
-+				if (_SUCCESS != ret)
-+					pmlmepriv->to_join = _FALSE;
-+			} else {
-+				/*if (ssc_chk == SS_DENY_BUDDY_UNDER_SURVEY)*/
-+				pmlmepriv->to_join = _FALSE;
-+				ret = _FAIL;
-+			}
-+		} else {
-+			pmlmepriv->to_join = _FALSE;
-+			ret = _FAIL;
-+		}
-+
-+		goto exit;
-+	} else {
-+		int select_ret;
-+		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+		select_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);
-+		if (select_ret == _SUCCESS) {
-+			pmlmepriv->to_join = _FALSE;
-+			_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
-+		} else {
-+			if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
-+				#ifdef CONFIG_AP_MODE
-+				/* submit createbss_cmd to change to a ADHOC_MASTER */
-+
-+				/* pmlmepriv->lock has been acquired by caller... */
-+				WLAN_BSSID_EX    *pdev_network = &(padapter->registrypriv.dev_network);
-+
-+				/*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/
-+				init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
-+
-+				pibss = padapter->registrypriv.dev_network.MacAddress;
-+
-+				_rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
-+				_rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
-+
-+				rtw_update_registrypriv_dev_network(padapter);
-+
-+				rtw_generate_random_ibss(pibss);
-+
-+				if (rtw_create_ibss_cmd(padapter, 0) != _SUCCESS) {
-+					ret =  _FALSE;
-+					goto exit;
-+				}
-+
-+				pmlmepriv->to_join = _FALSE;
-+				#endif /* CONFIG_AP_MODE */
-+			} else {
-+				/* can't associate ; reset under-linking			 */
-+				_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
-+
-+				/* when set_ssid/set_bssid for rtw_do_join(), but there are no desired bss in scanning queue */
-+				/* we try to issue sitesurvey firstly			 */
-+				if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE
-+				    || rtw_to_roam(padapter) > 0
-+				   ) {
-+					u8 ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
-+
-+					if ((ssc_chk == SS_ALLOW) || (ssc_chk == SS_DENY_BUSY_TRAFFIC)){
-+						/* RTW_INFO(("rtw_do_join() when   no desired bss in scanning queue\n"); */
-+						ret = rtw_sitesurvey_cmd(padapter, &parm);
-+						if (_SUCCESS != ret)
-+							pmlmepriv->to_join = _FALSE;
-+					} else {
-+						/*if (ssc_chk == SS_DENY_BUDDY_UNDER_SURVEY) {
-+						} else {*/
-+						ret = _FAIL;
-+						pmlmepriv->to_join = _FALSE;
-+					}
-+				} else {
-+					ret = _FAIL;
-+					pmlmepriv->to_join = _FALSE;
-+				}
-+			}
-+
-+		}
-+
-+	}
-+
-+exit:
-+
-+	return ret;
-+}
-+
-+u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid)
-+{
-+	_irqL irqL;
-+	u8 status = _SUCCESS;
-+
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+
-+	RTW_PRINT("set bssid:%pM\n", bssid);
-+
-+	if ((bssid[0] == 0x00 && bssid[1] == 0x00 && bssid[2] == 0x00 && bssid[3] == 0x00 && bssid[4] == 0x00 && bssid[5] == 0x00) ||
-+	    (bssid[0] == 0xFF && bssid[1] == 0xFF && bssid[2] == 0xFF && bssid[3] == 0xFF && bssid[4] == 0xFF && bssid[5] == 0xFF)) {
-+		status = _FAIL;
-+		goto exit;
-+	}
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+
-+	RTW_INFO("Set BSSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv));
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE)
-+		goto handle_tkip_countermeasure;
-+	else if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE)
-+		goto release_mlme_lock;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE) {
-+
-+		if (_rtw_memcmp(&pmlmepriv->cur_network.network.MacAddress, bssid, ETH_ALEN) == _TRUE) {
-+			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)
-+				goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */
-+		} else {
-+
-+			rtw_disassoc_cmd(padapter, 0, 0);
-+
-+			if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+				rtw_indicate_disconnect(padapter, 0, _FALSE);
-+
-+			rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
-+
-+			if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
-+				_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
-+				set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
-+			}
-+		}
-+	}
-+
-+handle_tkip_countermeasure:
-+	if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
-+		status = _FAIL;
-+		goto release_mlme_lock;
-+	}
-+
-+	_rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID));
-+	_rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN);
-+	pmlmepriv->assoc_ch = 0;
-+	pmlmepriv->assoc_by_bssid = _TRUE;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE)
-+		pmlmepriv->to_join = _TRUE;
-+	else
-+		status = rtw_do_join(padapter);
-+
-+release_mlme_lock:
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+exit:
-+
-+
-+	return status;
-+}
-+
-+u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid)
-+{
-+	_irqL irqL;
-+	u8 status = _SUCCESS;
-+
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct wlan_network *pnetwork = &pmlmepriv->cur_network;
-+
-+
-+	RTW_PRINT("set ssid [%s] fw_state=0x%08x\n",
-+		  ssid->Ssid, get_fwstate(pmlmepriv));
-+
-+	if (!rtw_is_hw_init_completed(padapter)) {
-+		status = _FAIL;
-+		goto exit;
-+	}
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+	RTW_INFO("Set SSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv));
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE)
-+		goto handle_tkip_countermeasure;
-+	else if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE)
-+		goto release_mlme_lock;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE) {
-+
-+		if ((pmlmepriv->assoc_ssid.SsidLength == ssid->SsidLength) &&
-+		    (_rtw_memcmp(&pmlmepriv->assoc_ssid.Ssid, ssid->Ssid, ssid->SsidLength) == _TRUE)) {
-+			if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)) {
-+
-+				if (rtw_is_same_ibss(padapter, pnetwork) == _FALSE) {
-+					/* if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again */
-+					rtw_disassoc_cmd(padapter, 0, 0);
-+
-+					if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+						rtw_indicate_disconnect(padapter, 0, _FALSE);
-+
-+					rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
-+
-+					if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) {
-+						_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
-+						set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
-+					}
-+				} else {
-+					goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */
-+				}
-+			}
-+#ifdef CONFIG_LPS
-+			else
-+				rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_JOINBSS, 0);
-+#endif
-+		} else {
-+
-+			rtw_disassoc_cmd(padapter, 0, 0);
-+
-+			if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+				rtw_indicate_disconnect(padapter, 0, _FALSE);
-+
-+			rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
-+
-+			if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) {
-+				_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
-+				set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
-+			}
-+		}
-+	}
-+
-+handle_tkip_countermeasure:
-+	if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
-+		status = _FAIL;
-+		goto release_mlme_lock;
-+	}
-+
-+	if (rtw_validate_ssid(ssid) == _FALSE) {
-+		status = _FAIL;
-+		goto release_mlme_lock;
-+	}
-+
-+	_rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID));
-+	pmlmepriv->assoc_ch = 0;
-+	pmlmepriv->assoc_by_bssid = _FALSE;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE)
-+		pmlmepriv->to_join = _TRUE;
-+	else
-+		status = rtw_do_join(padapter);
-+
-+release_mlme_lock:
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+exit:
-+
-+
-+	return status;
-+
-+}
-+
-+u8 rtw_set_802_11_connect(_adapter *padapter,
-+			  u8 *bssid, NDIS_802_11_SSID *ssid, u16 ch)
-+{
-+	_irqL irqL;
-+	u8 status = _SUCCESS;
-+	bool bssid_valid = _TRUE;
-+	bool ssid_valid = _TRUE;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+
-+	if (!ssid || rtw_validate_ssid(ssid) == _FALSE)
-+		ssid_valid = _FALSE;
-+
-+	if (!bssid || rtw_validate_bssid(bssid) == _FALSE)
-+		bssid_valid = _FALSE;
-+
-+	if (ssid_valid == _FALSE && bssid_valid == _FALSE) {
-+		RTW_INFO(FUNC_ADPT_FMT" ssid:%p, ssid_valid:%d, bssid:%p, bssid_valid:%d\n",
-+			FUNC_ADPT_ARG(padapter), ssid, ssid_valid, bssid, bssid_valid);
-+		status = _FAIL;
-+		goto exit;
-+	}
-+
-+	if (!rtw_is_hw_init_completed(padapter)) {
-+		status = _FAIL;
-+		goto exit;
-+	}
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+	RTW_PRINT(FUNC_ADPT_FMT"  fw_state=0x%08x\n",
-+		  FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv));
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE)
-+		goto handle_tkip_countermeasure;
-+	else if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE)
-+		goto release_mlme_lock;
-+
-+handle_tkip_countermeasure:
-+	if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
-+		status = _FAIL;
-+		goto release_mlme_lock;
-+	}
-+
-+	if (ssid && ssid_valid)
-+		_rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID));
-+	else
-+		_rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID));
-+
-+	if (bssid && bssid_valid) {
-+		_rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN);
-+		pmlmepriv->assoc_by_bssid = _TRUE;
-+	} else
-+		pmlmepriv->assoc_by_bssid = _FALSE;
-+
-+	pmlmepriv->assoc_ch = ch;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE)
-+		pmlmepriv->to_join = _TRUE;
-+	else
-+		status = rtw_do_join(padapter);
-+
-+release_mlme_lock:
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+exit:
-+	return status;
-+}
-+
-+u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter,
-+			      NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags)
-+{
-+	_irqL irqL;
-+	struct	mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct	wlan_network	*cur_network = &pmlmepriv->cur_network;
-+	NDIS_802_11_NETWORK_INFRASTRUCTURE *pold_state = &(cur_network->network.InfrastructureMode);
-+	u8 ap2sta_mode = _FALSE;
-+	u8 ret = _TRUE;
-+	u8 is_linked = _FALSE, is_adhoc_master = _FALSE;
-+
-+	if (*pold_state != networktype) {
-+		/* RTW_INFO("change mode, old_mode=%d, new_mode=%d, fw_state=0x%x\n", *pold_state, networktype, get_fwstate(pmlmepriv)); */
-+
-+		if (*pold_state == Ndis802_11APMode
-+			|| *pold_state == Ndis802_11_mesh
-+		) {
-+			/* change to other mode from Ndis802_11APMode/Ndis802_11_mesh */
-+			cur_network->join_res = -1;
-+			ap2sta_mode = _TRUE;
-+#ifdef CONFIG_NATIVEAP_MLME
-+			stop_ap_mode(padapter);
-+#endif
-+		}
-+
-+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+		is_linked = check_fwstate(pmlmepriv, WIFI_ASOC_STATE);
-+		is_adhoc_master = check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
-+
-+		/* flags = 0, means enqueue cmd and no wait */
-+		if (flags != 0)
-+			_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+		if ((is_linked == _TRUE) || (*pold_state == Ndis802_11IBSS))
-+			rtw_disassoc_cmd(padapter, 0, flags);
-+
-+		if ((is_linked == _TRUE) ||
-+		    (is_adhoc_master == _TRUE))
-+			rtw_free_assoc_resources_cmd(padapter, _TRUE, flags);
-+
-+		if ((*pold_state == Ndis802_11Infrastructure) || (*pold_state == Ndis802_11IBSS)) {
-+			if (is_linked == _TRUE) {
-+				rtw_indicate_disconnect(padapter, 0, _FALSE); /*will clr Linked_state; before this function, we must have checked whether issue dis-assoc_cmd or not*/
-+			}
-+		}
-+
-+		/* flags = 0, means enqueue cmd and no wait */
-+		if (flags != 0)
-+			_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+		*pold_state = networktype;
-+
-+		_clr_fwstate_(pmlmepriv, ~WIFI_NULL_STATE);
-+
-+		switch (networktype) {
-+		case Ndis802_11IBSS:
-+			set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
-+			break;
-+
-+		case Ndis802_11Infrastructure:
-+			set_fwstate(pmlmepriv, WIFI_STATION_STATE);
-+
-+			if (ap2sta_mode)
-+				rtw_init_bcmc_stainfo(padapter);
-+			break;
-+
-+		case Ndis802_11APMode:
-+			set_fwstate(pmlmepriv, WIFI_AP_STATE);
-+#ifdef CONFIG_NATIVEAP_MLME
-+			start_ap_mode(padapter);
-+			/* rtw_indicate_connect(padapter); */
-+#endif
-+
-+			break;
-+
-+#ifdef CONFIG_RTW_MESH
-+		case Ndis802_11_mesh:
-+			set_fwstate(pmlmepriv, WIFI_MESH_STATE);
-+			start_ap_mode(padapter);
-+			break;
-+#endif
-+
-+		case Ndis802_11AutoUnknown:
-+		case Ndis802_11InfrastructureMax:
-+			break;
-+#ifdef CONFIG_WIFI_MONITOR
-+		case Ndis802_11Monitor:
-+			set_fwstate(pmlmepriv, WIFI_MONITOR_STATE);
-+			break;
-+#endif /* CONFIG_WIFI_MONITOR */
-+		default:
-+			ret = _FALSE;
-+			rtw_warn_on(1);
-+		}
-+
-+		/* SecClearAllKeys(adapter); */
-+
-+
-+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+	}
-+
-+	return ret;
-+}
-+
-+
-+u8 rtw_set_802_11_disassociate(_adapter *padapter)
-+{
-+	_irqL irqL;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+
-+		rtw_disassoc_cmd(padapter, 0, 0);
-+		rtw_indicate_disconnect(padapter, 0, _FALSE);
-+		/* modify for CONFIG_IEEE80211W, none 11w can use it */
-+		rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
-+		if (_FAIL == rtw_pwr_wakeup(padapter))
-+			RTW_INFO("%s(): rtw_pwr_wakeup fail !!!\n", __FUNCTION__);
-+	}
-+
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+
-+	return _TRUE;
-+}
-+
-+#if 1
-+u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm)
-+{
-+	_irqL	irqL;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	u8	res = _TRUE;
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+	res = rtw_sitesurvey_cmd(padapter, pparm);
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+	return res;
-+}
-+
-+#else
-+u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm)
-+{
-+	_irqL	irqL;
-+	struct	mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	u8	res = _TRUE;
-+
-+
-+
-+	if (padapter == NULL) {
-+		res = _FALSE;
-+		goto exit;
-+	}
-+	if (!rtw_is_hw_init_completed(padapter)) {
-+		res = _FALSE;
-+		goto exit;
-+	}
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING) == _TRUE) ||
-+	    (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)) {
-+		/* Scan or linking is in progress, do nothing. */
-+		res = _TRUE;
-+
-+
-+	} else {
-+		if (rtw_is_scan_deny(padapter)) {
-+			RTW_INFO(FUNC_ADPT_FMT": scan deny\n", FUNC_ADPT_ARG(padapter));
-+			indicate_wx_scan_complete_event(padapter);
-+			return _SUCCESS;
-+		}
-+
-+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+		res = rtw_sitesurvey_cmd(padapter, pparm);
-+
-+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+	}
-+exit:
-+
-+
-+	return res;
-+}
-+#endif
-+
-+#ifdef CONFIG_RTW_ACS
-+u8 rtw_set_acs_sitesurvey(_adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	struct sitesurvey_parm parm;
-+	u8 uch;
-+	u8 ch_num = 0;
-+	int i;
-+	BAND_TYPE band;
-+	u8 (*center_chs_num)(u8) = NULL;
-+	u8 (*center_chs)(u8, u8) = NULL;
-+	u8 ret = _FAIL;
-+
-+	if (!rtw_mi_get_ch_setting_union(adapter, &uch, NULL, NULL))
-+		goto exit;
-+
-+	_rtw_memset(&parm, 0, sizeof(struct sitesurvey_parm));
-+	parm.scan_mode = SCAN_PASSIVE;
-+	parm.bw = CHANNEL_WIDTH_20;
-+	parm.acs = 1;
-+
-+	for (band = BAND_ON_2_4G; band < BAND_MAX; band++) {
-+		if (band == BAND_ON_2_4G) {
-+			center_chs_num = center_chs_2g_num;
-+			center_chs = center_chs_2g;
-+		} else
-+		#ifdef CONFIG_IEEE80211_BAND_5GHZ
-+		if (band == BAND_ON_5G) {
-+			center_chs_num = center_chs_5g_num;
-+			center_chs = center_chs_5g;
-+		} else
-+		#endif
-+		{
-+			center_chs_num = NULL;
-+			center_chs = NULL;
-+		}
-+
-+		if (!center_chs_num || !center_chs)
-+			continue;
-+
-+		if (rfctl->ch_sel_within_same_band) {
-+			if (rtw_is_2g_ch(uch) && band != BAND_ON_2_4G)
-+				continue;
-+			#ifdef CONFIG_IEEE80211_BAND_5GHZ
-+			if (rtw_is_5g_ch(uch) && band != BAND_ON_5G)
-+				continue;
-+			#endif
-+		}
-+
-+		ch_num = center_chs_num(CHANNEL_WIDTH_20);	
-+		for (i = 0; i < ch_num && parm.ch_num < RTW_CHANNEL_SCAN_AMOUNT; i++) {
-+			parm.ch[parm.ch_num].hw_value = center_chs(CHANNEL_WIDTH_20, i);
-+			parm.ch[parm.ch_num].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN;
-+			parm.ch_num++;
-+		}
-+	}
-+
-+	ret = rtw_set_802_11_bssid_list_scan(adapter, &parm);
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_RTW_ACS */
-+
-+u8 rtw_set_802_11_authentication_mode(_adapter *padapter, NDIS_802_11_AUTHENTICATION_MODE authmode)
-+{
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	int res;
-+	u8 ret;
-+
-+
-+
-+	psecuritypriv->ndisauthtype = authmode;
-+
-+
-+	if (psecuritypriv->ndisauthtype > 3)
-+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	if (psecuritypriv->ndisauthtype == 6)
-+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
-+#endif
-+
-+	res = rtw_set_auth(padapter, psecuritypriv);
-+
-+	if (res == _SUCCESS)
-+		ret = _TRUE;
-+	else
-+		ret = _FALSE;
-+
-+
-+	return ret;
-+}
-+
-+u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep)
-+{
-+
-+	u8		bdefaultkey;
-+	u8		btransmitkey;
-+	sint		keyid, res;
-+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
-+	u8		ret = _SUCCESS;
-+
-+
-+	bdefaultkey = (wep->KeyIndex & 0x40000000) > 0 ? _FALSE : _TRUE; /* for ??? */
-+	btransmitkey = (wep->KeyIndex & 0x80000000) > 0 ? _TRUE  : _FALSE;	/* for ??? */
-+	keyid = wep->KeyIndex & 0x3fffffff;
-+
-+	if (keyid >= 4) {
-+		ret = _FALSE;
-+		goto exit;
-+	}
-+
-+	switch (wep->KeyLength) {
-+	case 5:
-+		psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
-+		break;
-+	case 13:
-+		psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
-+		break;
-+	default:
-+		psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
-+		break;
-+	}
-+
-+
-+	_rtw_memcpy(&(psecuritypriv->dot11DefKey[keyid].skey[0]), &(wep->KeyMaterial), wep->KeyLength);
-+
-+	psecuritypriv->dot11DefKeylen[keyid] = wep->KeyLength;
-+
-+	psecuritypriv->dot11PrivacyKeyIndex = keyid;
-+
-+
-+	res = rtw_set_key(padapter, psecuritypriv, keyid, 1, _TRUE);
-+
-+	if (res == _FAIL)
-+		ret = _FALSE;
-+exit:
-+
-+
-+	return ret;
-+
-+}
-+
-+/*
-+* rtw_get_cur_max_rate -
-+* @adapter: pointer to _adapter structure
-+*
-+* Return 0 or 100Kbps
-+*/
-+u16 rtw_get_cur_max_rate(_adapter *adapter)
-+{
-+	int j;
-+	int	i = 0;
-+	u16	rate = 0, max_rate = 0;
-+	struct mlme_priv	*pmlmepriv = &adapter->mlmepriv;
-+	WLAN_BSSID_EX	*pcur_bss = &pmlmepriv->cur_network.network;
-+	int	sta_bssrate_len = 0;
-+	unsigned char	sta_bssrate[NumRates];
-+	struct sta_info *psta = NULL;
-+	u8	short_GI = 0;
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	if (adapter->registrypriv.mp_mode == 1) {
-+		if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
-+			return 0;
-+	}
-+#endif
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) != _TRUE)
-+	    && (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE))
-+		return 0;
-+
-+	psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
-+	if (psta == NULL)
-+		return 0;
-+
-+	short_GI = query_ra_short_GI(psta, rtw_get_tx_bw_mode(adapter, psta));
-+
-+#ifdef CONFIG_80211N_HT
-+	if (is_supported_ht(psta->wireless_mode)) {
-+		max_rate = rtw_ht_mcs_rate((psta->cmn.bw_mode == CHANNEL_WIDTH_40) ? 1 : 0
-+			, short_GI
-+			, psta->htpriv.ht_cap.supp_mcs_set
-+		);
-+	}
-+#ifdef CONFIG_80211AC_VHT
-+	else if (is_supported_vht(psta->wireless_mode))
-+		max_rate = ((rtw_vht_mcs_to_data_rate(psta->cmn.bw_mode, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10;
-+#endif /* CONFIG_80211AC_VHT */
-+	else
-+#endif /* CONFIG_80211N_HT */
-+	{
-+		/*station mode show :station && ap support rate; softap :show ap support rate*/	
-+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
-+			get_rate_set(adapter, sta_bssrate, &sta_bssrate_len);/*get sta rate and length*/
-+
-+
-+		while ((pcur_bss->SupportedRates[i] != 0) && (pcur_bss->SupportedRates[i] != 0xFF)) {
-+			rate = pcur_bss->SupportedRates[i] & 0x7F;/*AP support rates*/
-+			/*RTW_INFO("%s rate=%02X \n", __func__, rate);*/
-+
-+			/*check STA  support rate or not */
-+			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
-+				for (j = 0; j < sta_bssrate_len; j++) {
-+					/* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */
-+					if ((rate | IEEE80211_BASIC_RATE_MASK)
-+					    == (sta_bssrate[j] | IEEE80211_BASIC_RATE_MASK)) {
-+						if (rate > max_rate) {
-+							max_rate = rate;
-+						}
-+						break;
-+					}
-+				}
-+			} else {
-+			
-+				if (rate > max_rate)
-+					max_rate = rate;
-+
-+			}
-+			i++;
-+		}
-+
-+		max_rate = max_rate * 10 / 2;
-+	}
-+	return max_rate;
-+}
-+
-+/*
-+* rtw_set_scan_mode -
-+* @adapter: pointer to _adapter structure
-+* @scan_mode:
-+*
-+* Return _SUCCESS or _FAIL
-+*/
-+int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode)
-+{
-+	if (scan_mode != SCAN_ACTIVE && scan_mode != SCAN_PASSIVE)
-+		return _FAIL;
-+
-+	adapter->mlmepriv.scan_mode = scan_mode;
-+
-+	return _SUCCESS;
-+}
-+
-+/*
-+* rtw_set_channel_plan -
-+* @adapter: pointer to _adapter structure
-+* @channel_plan:
-+*
-+* Return _SUCCESS or _FAIL
-+*/
-+int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan)
-+{
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+
-+	if (!REGSTY_REGD_SRC_FROM_OS(regsty))
-+		return rtw_set_chplan_cmd(adapter, RTW_CMDF_WAIT_ACK, channel_plan, 1);
-+	RTW_WARN("%s(): not applied\n", __func__);
-+	return _SUCCESS;
-+}
-+
-+/*
-+* rtw_set_country -
-+* @adapter: pointer to _adapter structure
-+* @country_code: string of country code
-+*
-+* Return _SUCCESS or _FAIL
-+*/
-+int rtw_set_country(_adapter *adapter, const char *country_code)
-+{
-+#ifdef CONFIG_RTW_IOCTL_SET_COUNTRY
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+
-+	if (!REGSTY_REGD_SRC_FROM_OS(regsty))
-+		return rtw_set_country_cmd(adapter, RTW_CMDF_WAIT_ACK, country_code, 1);
-+#endif
-+	RTW_WARN("%s(): not applied\n", __func__);
-+	return _SUCCESS;
-+}
-+
-+/*
-+* rtw_set_band -
-+* @adapter: pointer to _adapter structure
-+* @band: band to set
-+*
-+* Return _SUCCESS or _FAIL
-+*/
-+int rtw_set_band(_adapter *adapter, u8 band)
-+{
-+	if (rtw_band_valid(band)) {
-+		RTW_INFO(FUNC_ADPT_FMT" band:%d\n", FUNC_ADPT_ARG(adapter), band);
-+		adapter->setband = band;
-+		return _SUCCESS;
-+	}
-+
-+	RTW_PRINT(FUNC_ADPT_FMT" band:%d fail\n", FUNC_ADPT_ARG(adapter), band);
-+	return _FAIL;
-+}
-diff --git a/drivers/staging/rtl8723cs/core/rtw_iol.c b/drivers/staging/rtl8723cs/core/rtw_iol.c
-new file mode 100644
-index 000000000000..714a3f44ede9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_iol.c
-@@ -0,0 +1,388 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_IOL
-+struct xmit_frame	*rtw_IOL_accquire_xmit_frame(ADAPTER *adapter)
-+{
-+	struct xmit_frame	*xmit_frame;
-+	struct xmit_buf	*xmitbuf;
-+	struct pkt_attrib	*pattrib;
-+	struct xmit_priv	*pxmitpriv = &(adapter->xmitpriv);
-+
-+#if 1
-+	xmit_frame = rtw_alloc_xmitframe(pxmitpriv, 0);
-+	if (xmit_frame == NULL) {
-+		RTW_INFO("%s rtw_alloc_xmitframe return null\n", __FUNCTION__);
-+		goto exit;
-+	}
-+
-+	xmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
-+	if (xmitbuf == NULL) {
-+		RTW_INFO("%s rtw_alloc_xmitbuf return null\n", __FUNCTION__);
-+		rtw_free_xmitframe(pxmitpriv, xmit_frame);
-+		xmit_frame = NULL;
-+		goto exit;
-+	}
-+
-+	xmit_frame->frame_tag = MGNT_FRAMETAG;
-+	xmit_frame->pxmitbuf = xmitbuf;
-+	xmit_frame->buf_addr = xmitbuf->pbuf;
-+	xmitbuf->priv_data = xmit_frame;
-+
-+	pattrib = &xmit_frame->attrib;
-+	update_mgntframe_attrib(adapter, pattrib);
-+	pattrib->qsel = QSLT_BEACON;/* Beacon	 */
-+	pattrib->subtype = WIFI_BEACON;
-+	pattrib->pktlen = pattrib->last_txcmdsz = 0;
-+
-+#else
-+	xmit_frame = alloc_mgtxmitframe(pxmitpriv);
-+	if (xmit_frame == NULL)
-+		RTW_INFO("%s alloc_mgtxmitframe return null\n", __FUNCTION__);
-+	else {
-+		pattrib = &xmit_frame->attrib;
-+		update_mgntframe_attrib(adapter, pattrib);
-+		pattrib->qsel = QSLT_BEACON;
-+		pattrib->pktlen = pattrib->last_txcmdsz = 0;
-+	}
-+#endif
-+
-+exit:
-+	return xmit_frame;
-+}
-+
-+
-+int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len)
-+{
-+	struct pkt_attrib	*pattrib = &xmit_frame->attrib;
-+	u16 buf_offset;
-+	u32 ori_len;
-+
-+	buf_offset = TXDESC_OFFSET;
-+	ori_len = buf_offset + pattrib->pktlen;
-+
-+	/* check if the io_buf can accommodate new cmds */
-+	if (ori_len + cmd_len + 8 > MAX_XMITBUF_SZ) {
-+		RTW_INFO("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate new cmds\n", __FUNCTION__
-+			 , ori_len + cmd_len + 8, MAX_XMITBUF_SZ);
-+		return _FAIL;
-+	}
-+
-+	_rtw_memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, IOL_cmds, cmd_len);
-+	pattrib->pktlen += cmd_len;
-+	pattrib->last_txcmdsz += cmd_len;
-+
-+	/* RTW_INFO("%s ori:%u + cmd_len:%u = %u\n", __FUNCTION__, ori_len, cmd_len, buf_offset+pattrib->pktlen); */
-+
-+	return _SUCCESS;
-+}
-+
-+bool rtw_IOL_applied(ADAPTER *adapter)
-+{
-+	if (1 == adapter->registrypriv.fw_iol)
-+		return _TRUE;
-+
-+#ifdef CONFIG_USB_HCI
-+	if ((2 == adapter->registrypriv.fw_iol) && (IS_FULL_SPEED_USB(adapter)))
-+		return _TRUE;
-+#endif
-+
-+	return _FALSE;
-+}
-+
-+int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
-+{
-+	return rtw_hal_iol_cmd(adapter, xmit_frame, max_wating_ms, bndy_cnt);
-+}
-+
-+#ifdef CONFIG_IOL_NEW_GENERATION
-+int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)
-+{
-+	return _SUCCESS;
-+}
-+int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask)
-+{
-+	struct ioreg_cfg cmd = {8, IOREG_CMD_WB_REG, 0x0, 0x0, 0x0};
-+
-+	/* RTW_PUT_LE16((u8*)&cmd.address, addr);	 */
-+	/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	 */
-+	cmd.address = cpu_to_le16(addr);
-+	cmd.data = cpu_to_le32(value);
-+
-+	if (mask != 0xFF) {
-+		cmd.length = 12;
-+		/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	 */
-+		cmd.mask = cpu_to_le32(mask);
-+	}
-+
-+	/* RTW_INFO("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask); */
-+
-+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
-+
-+}
-+int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask)
-+{
-+	struct ioreg_cfg cmd = {8, IOREG_CMD_WW_REG, 0x0, 0x0, 0x0};
-+
-+	/* RTW_PUT_LE16((u8*)&cmd.address, addr);	 */
-+	/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	 */
-+	cmd.address = cpu_to_le16(addr);
-+	cmd.data = cpu_to_le32(value);
-+
-+	if (mask != 0xFFFF) {
-+		cmd.length = 12;
-+		/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	 */
-+		cmd.mask =  cpu_to_le32(mask);
-+	}
-+
-+	/* RTW_INFO("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask); */
-+
-+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
-+
-+}
-+int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask)
-+{
-+	struct ioreg_cfg cmd = {8, IOREG_CMD_WD_REG, 0x0, 0x0, 0x0};
-+
-+	/* RTW_PUT_LE16((u8*)&cmd.address, addr);	 */
-+	/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	 */
-+	cmd.address = cpu_to_le16(addr);
-+	cmd.data = cpu_to_le32(value);
-+
-+	if (mask != 0xFFFFFFFF) {
-+		cmd.length = 12;
-+		/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	 */
-+		cmd.mask =  cpu_to_le32(mask);
-+	}
-+
-+	/* RTW_INFO("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__, addr,value,mask); */
-+
-+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
-+
-+}
-+
-+int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask)
-+{
-+	struct ioreg_cfg cmd = {8, IOREG_CMD_W_RF, 0x0, 0x0, 0x0};
-+
-+	/* RTW_PUT_LE16((u8*)&cmd.address, addr);	 */
-+	/* RTW_PUT_LE32((u8*)&cmd.value, (u32)value);	 */
-+	cmd.address = (rf_path << 8) | ((addr) & 0xFF);
-+	cmd.data = cpu_to_le32(value);
-+
-+	if (mask != 0x000FFFFF) {
-+		cmd.length = 12;
-+		/* RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);	 */
-+		cmd.mask =  cpu_to_le32(mask);
-+	}
-+
-+	/* RTW_INFO("%s rf_path:0x%02x addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__,rf_path, addr,value,mask); */
-+
-+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, cmd.length);
-+
-+}
-+
-+
-+
-+int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
-+{
-+	struct ioreg_cfg cmd = {4, IOREG_CMD_DELAY_US, 0x0, 0x0, 0x0};
-+	/* RTW_PUT_LE16((u8*)&cmd.address, us);	 */
-+	cmd.address = cpu_to_le16(us);
-+
-+	/* RTW_INFO("%s %u\n", __FUNCTION__, us); */
-+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
-+}
-+
-+int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
-+{
-+	struct ioreg_cfg cmd = {4, IOREG_CMD_DELAY_US, 0x0, 0x0, 0x0};
-+
-+	/* RTW_PUT_LE16((u8*)&cmd.address, ms);	 */
-+	cmd.address = cpu_to_le16(ms);
-+
-+	/* RTW_INFO("%s %u\n", __FUNCTION__, ms); */
-+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
-+}
-+int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
-+{
-+	struct ioreg_cfg cmd = {4, IOREG_CMD_END, 0xFFFF, 0xFF, 0x0};
-+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 4);
-+
-+}
-+
-+u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame)
-+{
-+	u8 is_cmd_bndy = _FALSE;
-+	if (((pxmit_frame->attrib.pktlen + 32) % 256) + 8 >= 256) {
-+		rtw_IOL_append_END_cmd(pxmit_frame);
-+		pxmit_frame->attrib.pktlen = ((((pxmit_frame->attrib.pktlen + 32) / 256) + 1) * 256);
-+
-+		/* printk("==> %s, pktlen(%d)\n",__FUNCTION__,pxmit_frame->attrib.pktlen); */
-+		pxmit_frame->attrib.last_txcmdsz = pxmit_frame->attrib.pktlen;
-+		is_cmd_bndy = _TRUE;
-+	}
-+	return is_cmd_bndy;
-+}
-+
-+void rtw_IOL_cmd_buf_dump(ADAPTER *Adapter, int buf_len, u8 *pbuf)
-+{
-+	int i;
-+	int j = 1;
-+
-+	printk("###### %s ######\n", __FUNCTION__);
-+	for (i = 0; i < buf_len; i++) {
-+		printk("%02x-", *(pbuf + i));
-+
-+		if (j % 32 == 0)
-+			printk("\n");
-+		j++;
-+	}
-+	printk("\n");
-+	printk("============= ioreg_cmd len = %d ===============\n", buf_len);
-+}
-+
-+
-+#else /* CONFIG_IOL_NEW_GENERATION */
-+int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)
-+{
-+	IOL_CMD cmd = {0x0, IOL_CMD_LLT, 0x0, 0x0};
-+
-+	RTW_PUT_BE32((u8 *)&cmd.value, (u32)page_boundary);
-+
-+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
-+}
-+
-+int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value)
-+{
-+	IOL_CMD cmd = {0x0, IOL_CMD_WB_REG, 0x0, 0x0};
-+
-+	RTW_PUT_BE16((u8 *)&cmd.address, (u16)addr);
-+	RTW_PUT_BE32((u8 *)&cmd.value, (u32)value);
-+
-+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
-+}
-+
-+int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value)
-+{
-+	IOL_CMD cmd = {0x0, IOL_CMD_WW_REG, 0x0, 0x0};
-+
-+	RTW_PUT_BE16((u8 *)&cmd.address, (u16)addr);
-+	RTW_PUT_BE32((u8 *)&cmd.value, (u32)value);
-+
-+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
-+}
-+
-+int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value)
-+{
-+	IOL_CMD cmd = {0x0, IOL_CMD_WD_REG, 0x0, 0x0};
-+	u8 *pos = (u8 *)&cmd;
-+
-+	RTW_PUT_BE16((u8 *)&cmd.address, (u16)addr);
-+	RTW_PUT_BE32((u8 *)&cmd.value, (u32)value);
-+
-+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
-+}
-+
-+#ifdef DBG_IO
-+int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line)
-+{
-+	if (match_write_sniff(xmit_frame->padapter, addr, 1, value)) {
-+		RTW_INFO("DBG_IO %s:%d IOL_WB(0x%04x, 0x%02x)\n"
-+			, caller, line, addr, value);
-+	}
-+
-+	return _rtw_IOL_append_WB_cmd(xmit_frame, addr, value);
-+}
-+
-+int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line)
-+{
-+	if (match_write_sniff(xmit_frame->padapter, addr, 2, value)) {
-+		RTW_INFO("DBG_IO %s:%d IOL_WW(0x%04x, 0x%04x)\n"
-+			, caller, line, addr, value);
-+	}
-+
-+	return _rtw_IOL_append_WW_cmd(xmit_frame, addr, value);
-+}
-+
-+int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line)
-+{
-+	if (match_write_sniff(xmit_frame->padapter, addr, 4, value)) {
-+		RTW_INFO("DBG_IO %s:%d IOL_WD(0x%04x, 0x%08x)\n"
-+			, caller, line, addr, value);
-+	}
-+
-+	return _rtw_IOL_append_WD_cmd(xmit_frame, addr, value);
-+}
-+#endif
-+
-+int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
-+{
-+	IOL_CMD cmd = {0x0, IOL_CMD_DELAY_US, 0x0, 0x0};
-+
-+	RTW_PUT_BE32((u8 *)&cmd.value, (u32)us);
-+
-+	/* RTW_INFO("%s %u\n", __FUNCTION__, us); */
-+
-+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
-+}
-+
-+int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
-+{
-+	IOL_CMD cmd = {0x0, IOL_CMD_DELAY_MS, 0x0, 0x0};
-+
-+	RTW_PUT_BE32((u8 *)&cmd.value, (u32)ms);
-+
-+	/* RTW_INFO("%s %u\n", __FUNCTION__, ms); */
-+
-+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&cmd, 8);
-+}
-+
-+int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
-+{
-+	IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};
-+
-+
-+	return rtw_IOL_append_cmds(xmit_frame, (u8 *)&end_cmd, 8);
-+
-+}
-+
-+int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms)
-+{
-+	struct xmit_frame	*xmit_frame;
-+
-+	xmit_frame = rtw_IOL_accquire_xmit_frame(adapter);
-+	if (xmit_frame == NULL)
-+		return _FAIL;
-+
-+	if (rtw_IOL_append_cmds(xmit_frame, IOL_cmds, cmd_num << 3) == _FAIL)
-+		return _FAIL;
-+
-+	return rtw_IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms, 0);
-+}
-+
-+int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms)
-+{
-+	IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};
-+	return rtw_IOL_exec_cmd_array_sync(adapter, (u8 *)&end_cmd, 1, max_wating_ms);
-+}
-+#endif /* CONFIG_IOL_NEW_GENERATION */
-+
-+
-+
-+
-+#endif /* CONFIG_IOL */
-diff --git a/drivers/staging/rtl8723cs/core/rtw_mbo.c b/drivers/staging/rtl8723cs/core/rtw_mbo.c
-new file mode 100644
-index 000000000000..44f93ad6ce75
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_mbo.c
-@@ -0,0 +1,803 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#ifdef CONFIG_RTW_MBO
-+
-+#ifndef RTW_MBO_DBG
-+#define RTW_MBO_DBG	0
-+#endif
-+#if RTW_MBO_DBG
-+	#define RTW_MBO_INFO(fmt, arg...)	\
-+		RTW_INFO(fmt, arg)
-+	#define RTW_MBO_DUMP(str, data, len)	\
-+		RTW_INFO_DUMP(str, data, len)	
-+#else
-+	#define RTW_MBO_INFO(fmt, arg...) do {} while (0)
-+	#define RTW_MBO_DUMP(str, data, len) do {} while (0)
-+#endif
-+
-+/* Cellular Data Connectivity field
-+ * 1 : Cellular data connection available
-+ * 2 : Cellular data connection not available
-+ * 3 : Not Cellular data capable
-+ * otherwise : Reserved
-+*/
-+int rtw_mbo_cell_data_conn = 2;
-+module_param(rtw_mbo_cell_data_conn, int, 0644);
-+
-+static u8 wfa_mbo_oui[] = {0x50, 0x6F, 0x9A, 0x16};
-+
-+#define rtw_mbo_get_oui(p) ((u8 *)(p) + 2) 
-+
-+#define rtw_mbo_get_attr_id(p) ((u8 *)(p)) 
-+
-+#define rtw_mbo_get_disallow_res(p) ((u8 *)(p) + 3) 
-+
-+#define rtw_mbo_set_1byte_ie(p, v, l)	\
-+	rtw_set_fixed_ie((p), 1, (v), (l))
-+
-+#define rtw_mbo_set_4byte_ie(p, v, l)	\
-+	rtw_set_fixed_ie((p), 4, (v), (l))
-+
-+#define rtw_mbo_set_nbyte_ie(p, sz, v, l)	\
-+	rtw_set_fixed_ie((p), (sz), (v), (l))
-+
-+#define rtw_mbo_subfield_set(p, offset, val) (*(p + offset) = val)
-+
-+#define rtw_mbo_subfields_set(p, offset, buf, len)	\
-+	do {	\
-+		u32 _offset = 0;	\
-+		u8 *_p = p + offset;	\
-+		while(_offset < len) {	\
-+			*(_p + _offset) = *(buf + _offset);	\
-+			_offset++;	\
-+		}	\
-+	} while(0)
-+	
-+static u8 *rtw_mbo_ie_get(u8 *pie, u32 *plen, u32 limit)
-+{
-+	const u8 *p = pie;
-+	u32 tmp, i;
-+	
-+	if (limit <= 1)
-+		return NULL;
-+
-+	i = 0;
-+	*plen = 0;
-+	while (1) {
-+		if ((*p == _VENDOR_SPECIFIC_IE_) && 
-+			(_rtw_memcmp(rtw_mbo_get_oui(p), wfa_mbo_oui, 4))) {
-+			*plen = *(p + 1);
-+			RTW_MBO_DUMP("VENDOR_SPECIFIC_IE MBO: ", p, *(p + 1));
-+			return (u8 *)p;
-+		} else {
-+			tmp = *(p + 1);
-+			p += (tmp + 2);
-+			i += (tmp + 2);
-+		}
-+		
-+		if (i >= limit)
-+			break;
-+	}
-+	
-+	return NULL;	
-+}
-+
-+static u8 *rtw_mbo_attrs_get(u8 *pie, u32 limit, u8 attr_id, u32 *attr_len)
-+{
-+	u8 *p = NULL;
-+	u32 offset, plen = 0;
-+
-+	if ((pie == NULL) || (limit <= 1))
-+		goto exit;
-+	
-+	if ((p = rtw_mbo_ie_get(pie, &plen, limit)) == NULL)
-+		goto exit;
-+
-+	/* shift 2 + OUI size and move to attributes content */
-+	p = p + 2 + sizeof(wfa_mbo_oui);
-+	plen = plen - 4;
-+	RTW_MBO_DUMP("Attributes contents: ", p, plen);
-+
-+	if ((p = rtw_get_ie(p, attr_id, attr_len, plen)) == NULL)
-+		goto exit;
-+
-+	RTW_MBO_INFO("%s : id=%u(len=%u)\n", __func__, attr_id, *attr_len);
-+	RTW_MBO_DUMP("contents : ", p, *attr_len);
-+
-+exit:
-+	return p;	
-+
-+}
-+
-+static u32 rtw_mbo_attr_sz_get(
-+	_adapter *padapter, u8 id)
-+{
-+	u32 len = 0;
-+
-+	switch (id) {
-+		case RTW_MBO_ATTR_NPREF_CH_RPT_ID:
-+			{
-+				struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
-+				struct npref_ch_rtp *prpt = &(prfctl->ch_rtp);
-+				struct npref_ch* pch;
-+				u32 i, attr_len, offset;
-+
-+				for (i=0; i < prpt->nm_of_rpt; i++) {
-+					pch = &prpt->ch_rpt[i];
-+					/*attr_len = ch list + op class + preference + reason */
-+					attr_len = pch->nm_of_ch + 3;
-+					/* offset = id + len field + attr_len */
-+					offset = attr_len + 2;
-+					len += offset;
-+				}							
-+			}
-+			break;
-+		case RTW_MBO_ATTR_CELL_DATA_CAP_ID:
-+		case RTW_MBO_ATTR_TRANS_REJ_ID:
-+			len = 3;
-+			break;
-+		default:
-+			break;
-+	}
-+
-+	return len;
-+}
-+
-+static void rtw_mbo_build_mbo_ie_hdr(
-+	u8 **pframe, struct pkt_attrib *pattrib, u8 payload_len)
-+{
-+	u8 eid = RTW_MBO_EID;
-+	u8 len = payload_len + 4; 
-+
-+	*pframe = rtw_mbo_set_1byte_ie(*pframe, &eid, &(pattrib->pktlen));
-+	*pframe = rtw_mbo_set_1byte_ie(*pframe, &len, &(pattrib->pktlen));
-+	*pframe = rtw_mbo_set_4byte_ie(*pframe, wfa_mbo_oui, &(pattrib->pktlen));
-+}
-+
-+void rtw_mbo_build_cell_data_cap_attr(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	u8 attr_id = RTW_MBO_ATTR_CELL_DATA_CAP_ID;
-+	u8 attr_len = 1;
-+	u8 cell_data_con = rtw_mbo_cell_data_conn;
-+
-+	/* used Cellular Data Capabilities from supplicant */
-+	if (!rtw_mbo_wifi_logo_test(padapter) &&
-+		pmlmepriv->pcell_data_cap_ie && pmlmepriv->cell_data_cap_len == 1) {
-+		cell_data_con = *pmlmepriv->pcell_data_cap_ie;
-+		RTW_MBO_INFO("%s : used Cellular Data Capabilities(%u) from supplicant!\n",
-+			__func__, *pmlmepriv->pcell_data_cap_ie);
-+	}
-+		
-+	*pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_id, &(pattrib->pktlen));
-+	*pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_len, &(pattrib->pktlen));	
-+	*pframe = rtw_mbo_set_1byte_ie(*pframe, &cell_data_con, &(pattrib->pktlen));
-+}
-+
-+static void rtw_mbo_update_cell_data_cap(
-+	_adapter *padapter, u8 *pie, u32 ie_len)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	u8 *mbo_attr;	
-+	u32	mbo_attrlen;
-+
-+	if ((pie == NULL) || (ie_len == 0))
-+		return;
-+
-+	mbo_attr = rtw_mbo_attrs_get(pie, ie_len, 
-+		RTW_MBO_ATTR_CELL_DATA_CAP_ID, &mbo_attrlen);
-+
-+	if ((mbo_attr == NULL) || (mbo_attrlen == 0) ) {
-+		RTW_INFO("MBO : Cellular Data Capabilities not found!\n");
-+		return;
-+	}
-+
-+	rtw_buf_update(&pmlmepriv->pcell_data_cap_ie, 
-+		&pmlmepriv->cell_data_cap_len, (mbo_attr + 2), mbo_attrlen);
-+	RTW_MBO_DUMP("rtw_mbo_update_cell_data_cap : ", 
-+		pmlmepriv->pcell_data_cap_ie, pmlmepriv->cell_data_cap_len);
-+}
-+
-+void rtw_mbo_update_ie_data(
-+	_adapter *padapter, u8 *pie, u32 ie_len)
-+{
-+	rtw_mbo_update_cell_data_cap(padapter, pie, ie_len);
-+}
-+
-+static u8 rtw_mbo_current_op_class_get(_adapter *padapter)
-+{
-+	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
-+	struct p2p_channels *pch_list =  &(prfctl->channel_list);	
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+	struct p2p_reg_class *preg_class;
-+	int class_idx, ch_idx;
-+	u8 cur_op_class = 0;
-+
-+	for(class_idx =0; class_idx < pch_list->reg_classes; class_idx++) {
-+		preg_class =  &pch_list->reg_class[class_idx];
-+		for (ch_idx = 0; ch_idx <= preg_class->channels; ch_idx++) {
-+			if (pmlmeext->cur_channel ==  preg_class->channel[ch_idx]) {
-+				cur_op_class = preg_class->reg_class;
-+				RTW_MBO_INFO("%s : current ch : %d, op class : %d\n",
-+					__func__, pmlmeext->cur_channel, cur_op_class);		
-+				break;
-+			}
-+		}
-+	}
-+	
-+	return cur_op_class;
-+}
-+
-+static void rtw_mbo_supp_op_classes_get(_adapter *padapter, u8 *pclasses)
-+{
-+	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
-+	struct p2p_channels *pch_list =  &(prfctl->channel_list);	
-+	int class_idx;
-+
-+	if (pclasses == NULL)
-+		return;
-+
-+	RTW_MBO_INFO("%s : support op class \n", __func__);
-+	for(class_idx = 0; class_idx < pch_list->reg_classes; class_idx++) {
-+		*(pclasses + class_idx) = pch_list->reg_class[class_idx].reg_class;
-+		RTW_MBO_INFO("%u ,", *(pclasses + class_idx));		
-+	}
-+
-+	RTW_MBO_INFO("%s : \n", __func__);	
-+}
-+
-+void rtw_mbo_build_supp_op_class_elem(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib)
-+{
-+	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
-+	u8 payload[32] = {0};
-+	u8 delimiter_130 = 130;	/*0x82*/
-+	u8 reg_class_nm, len;
-+
-+	if ((reg_class_nm = prfctl->channel_list.reg_classes) == 0)
-+		return;
-+
-+	payload[0] = rtw_mbo_current_op_class_get(padapter);
-+	rtw_mbo_supp_op_classes_get(padapter, &payload[1]);
-+
-+	/* IEEE 802.11 Std Current Operating Class Extension Sequence */
-+	payload[reg_class_nm + 1] = delimiter_130;
-+	payload[reg_class_nm + 2] = 0x00;
-+
-+	RTW_MBO_DUMP("op class :", payload, reg_class_nm);
-+
-+	/* Current Operating Class field + Operating Class field 
-+		+ OneHundredAndThirty Delimiter field */
-+	len = reg_class_nm + 3;	
-+	*pframe = rtw_set_ie(*pframe, EID_SupRegulatory, len , 
-+					payload, &(pattrib->pktlen));	
-+}
-+
-+static u8 rtw_mbo_construct_npref_ch_rpt_attr(
-+	_adapter *padapter, u8 *pbuf, u32 buf_len, u32 *plen)
-+{
-+	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
-+	struct npref_ch_rtp *prpt = &(prfctl->ch_rtp);
-+	struct npref_ch* pch;
-+	u32 attr_len, offset;
-+	int i;
-+	u8 *p = pbuf;
-+
-+	if (prpt->nm_of_rpt == 0) {
-+		*plen = 0;
-+		return _FALSE;
-+	}	
-+
-+	for (i=0; i < prpt->nm_of_rpt; i++) {
-+		pch = &prpt->ch_rpt[i];
-+		/* attr_len = ch list + op class + preference + reason */
-+		attr_len = pch->nm_of_ch + 3;
-+		/* offset = id + len field + attr_len */
-+		offset = attr_len + 2;
-+		rtw_mbo_subfield_set(p, 0, RTW_MBO_ATTR_NPREF_CH_RPT_ID);
-+		rtw_mbo_subfield_set(p, 1, attr_len);
-+		rtw_mbo_subfield_set(p, 2, pch->op_class);
-+		rtw_mbo_subfields_set(p, 3, pch->chs, pch->nm_of_ch);
-+		rtw_mbo_subfield_set(p, (offset - 2), pch->preference);
-+		rtw_mbo_subfield_set(p, (offset - 1), pch->reason);
-+		p +=  offset;
-+		*plen += offset;
-+
-+		if (*plen >=  buf_len) {
-+			RTW_ERR("MBO : construct non-preferred channel report fail!\n");
-+			return _FALSE;
-+		}
-+	}
-+
-+	return _TRUE;
-+}
-+
-+void rtw_mbo_build_npref_ch_rpt_attr(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib)
-+{
-+	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
-+	struct npref_ch_rtp *prpt = &(prfctl->ch_rtp);
-+	u32 tmp_sz = 0, body_len = 0;
-+	u8 *ptmp;
-+
-+	tmp_sz = prpt->nm_of_rpt * sizeof(struct npref_ch);
-+	ptmp = rtw_zmalloc(tmp_sz);
-+	if (ptmp == NULL)
-+		return;
-+
-+	if (rtw_mbo_construct_npref_ch_rpt_attr(padapter, ptmp, tmp_sz, &body_len) == _FALSE) {
-+		rtw_mfree(ptmp, tmp_sz);
-+		return;
-+	}	
-+
-+	RTW_MBO_DUMP("Non-preferred Channel Report :", ptmp, body_len);
-+	*pframe = rtw_mbo_set_nbyte_ie(*pframe, body_len, ptmp, &(pattrib->pktlen));
-+
-+	rtw_mfree(ptmp, tmp_sz);
-+}
-+
-+void rtw_mbo_build_trans_reject_reason_attr(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib, u8 *pres)
-+{
-+	u8 attr_id = RTW_MBO_ATTR_TRANS_REJ_ID;
-+	u8 attr_len = 1;
-+	u32 len = 0;
-+
-+	len = rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_TRANS_REJ_ID);
-+	if ((len == 0) || (len > 3)) {
-+		RTW_ERR("MBO : build Transition Rejection Reason  attribute fail(len=%u)\n", len);
-+		return;
-+	}
-+			
-+	rtw_mbo_build_mbo_ie_hdr(pframe, pattrib, len);
-+	*pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_id, &(pattrib->pktlen));
-+	*pframe = rtw_mbo_set_1byte_ie(*pframe, &attr_len, &(pattrib->pktlen));	
-+	*pframe = rtw_mbo_set_1byte_ie(*pframe, pres, &(pattrib->pktlen));
-+}
-+
-+u8 rtw_mbo_disallowed_network(struct wlan_network *pnetwork)
-+{
-+	u8 *p, *attr_id, *res;
-+	u32 attr_len = 0;
-+	u8 disallow = _FALSE;
-+
-+	if (pnetwork == NULL)
-+		goto exit;
-+
-+	p = rtw_mbo_attrs_get(pnetwork->network.IEs, 
-+		pnetwork->network.IELength, 
-+		RTW_MBO_ATTR_ASSOC_DISABLED_ID, 
-+		&attr_len);
-+
-+	if (p == NULL) {
-+		RTW_MBO_INFO("%s :Assoc Disallowed attribute not found!\n",__func__);
-+		goto exit;
-+	}
-+		
-+	RTW_MBO_DUMP("Association Disallowed attribute :",p , attr_len + 2);
-+	RTW_INFO("MBO : block "MAC_FMT" assoc disallowed reason %d\n",
-+		MAC_ARG(pnetwork->network.MacAddress), *(rtw_mbo_get_disallow_res(p)));
-+
-+	disallow = _TRUE;
-+exit:
-+	return disallow;
-+}
-+
-+void rtw_mbo_build_exented_cap(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib)
-+{
-+	u8 content[8] = { 0 };
-+
-+	rtw_wnm_set_ext_cap_btm(content, 1);
-+	rtw_mbo_set_ext_cap_internw(content, 1);
-+	*pframe = rtw_set_ie(*pframe, 
-+				EID_EXTCapability, 
-+				8, 
-+				content, 
-+				&(pattrib->pktlen));
-+}
-+
-+static void rtw_mbo_non_pref_chans_dump(struct npref_ch* pch)
-+{
-+	int i;
-+	u8 buf[128] = {0};
-+
-+	for (i=0; i < pch->nm_of_ch; i++)
-+		rtw_sprintf(buf, 128, "%s,%d", buf, pch->chs[i]);
-+
-+	RTW_MBO_INFO("%s : op_class=%01x, ch=%s, preference=%d, reason=%d\n", 
-+		__func__, pch->op_class, buf, pch->preference, pch->reason);		
-+}
-+
-+static u8 rtw_mbo_non_pref_chan_exist(struct npref_ch* pch, u8 ch)
-+{
-+	u32 i;
-+	u8 found = _FALSE;
-+
-+	for (i=0; i < pch->nm_of_ch; i++) {
-+		if (pch->chs[i] == ch) {
-+			found = _TRUE;
-+			break;
-+		}
-+	}
-+	
-+	return found;
-+}
-+
-+static struct npref_ch* rtw_mbo_non_pref_chan_get(
-+	_adapter *padapter, u8 op_class, u8  prefe, u8  res)
-+{
-+	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
-+	struct npref_ch_rtp *prpt = &(prfctl->ch_rtp);
-+	struct npref_ch* pch = NULL;
-+	int i;
-+
-+	if (prpt->nm_of_rpt == 0)
-+		return pch;
-+
-+	for (i=0; i < prpt->nm_of_rpt; i++) {
-+		if ((prpt->ch_rpt[i].op_class == op_class) &&
-+			(prpt->ch_rpt[i].preference == prefe) && 
-+			(prpt->ch_rpt[i].reason == res)) {
-+			pch = &prpt->ch_rpt[i];
-+			break;
-+		}
-+	}
-+
-+	return pch;
-+}
-+
-+static void rtw_mbo_non_pref_chan_set(
-+	struct npref_ch* pch, u8 op_class, u8 ch, u8  prefe, u8  res, u8 update)
-+{
-+	u32 offset = pch->nm_of_ch;
-+
-+	if (update) {
-+		if (rtw_mbo_non_pref_chan_exist(pch, ch) == _FALSE) {
-+			pch->chs[offset] = ch;
-+			pch->nm_of_ch++;
-+		}
-+	} else {
-+		pch->op_class = op_class;
-+		pch->chs[0] = ch;
-+		pch->preference = prefe;
-+		pch->reason = res;
-+		pch->nm_of_ch = 1;
-+	}
-+}
-+
-+static void  rtw_mbo_non_pref_chans_update(
-+	_adapter *padapter, u8 op_class, u8 ch, u8  prefe, u8  res)
-+{
-+	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
-+	struct npref_ch_rtp *pch_rpt = &(prfctl->ch_rtp);
-+	struct npref_ch* pch;
-+
-+	if (pch_rpt->nm_of_rpt >= RTW_MBO_MAX_CH_RPT_NUM) {
-+		RTW_ERR("MBO : %d non_pref_chan entries supported!", 
-+			RTW_MBO_MAX_CH_RPT_NUM);
-+		return;
-+	}
-+
-+	if (pch_rpt->nm_of_rpt == 0) {
-+		pch = &pch_rpt->ch_rpt[0];
-+		rtw_mbo_non_pref_chan_set(pch, op_class, ch, prefe, res, _FALSE);
-+		pch_rpt->nm_of_rpt = 1;
-+		return;
-+	}
-+
-+	pch = rtw_mbo_non_pref_chan_get(padapter, op_class, prefe, res);
-+	if (pch == NULL) {
-+		pch = &pch_rpt->ch_rpt[pch_rpt->nm_of_rpt];
-+		rtw_mbo_non_pref_chan_set(pch, op_class, ch, prefe, res, _FALSE);
-+		pch_rpt->nm_of_rpt++;
-+	} else
-+		rtw_mbo_non_pref_chan_set(pch, op_class, ch, prefe, res, _TRUE);
-+
-+	rtw_mbo_non_pref_chans_dump(pch);
-+}
-+
-+static void  rtw_mbo_non_pref_chans_set(
-+	_adapter *padapter, char *param, ssize_t sz)
-+{
-+	char *pnext;
-+	u32 op_class, ch, prefe, res;
-+	int i = 0;
-+	
-+	do {
-+		pnext = strsep(&param, " ");
-+		if (pnext == NULL)
-+			break;
-+
-+		sscanf(pnext, "%d:%d:%d:%d", &op_class, &ch, &prefe, &res);
-+		rtw_mbo_non_pref_chans_update(padapter, op_class, ch, prefe, res);
-+	
-+		if ((i++) > 10) {
-+			RTW_ERR("MBO : overflow %d \n", i);
-+			break;
-+		}
-+		
-+	} while(param != '\0');
-+	
-+}
-+
-+static void  rtw_mbo_non_pref_chans_del(
-+	_adapter *padapter, char *param, ssize_t sz)
-+{
-+	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
-+	struct npref_ch_rtp *prpt = &(prfctl->ch_rtp);
-+	
-+	RTW_INFO("%s : delete non_pref_chan %s\n", __func__, param);
-+	_rtw_memset(prpt, 0, sizeof(struct npref_ch_rtp));
-+}
-+
-+ssize_t rtw_mbo_proc_non_pref_chans_set(
-+	struct file *pfile, const char __user *buffer, 
-+	size_t count, loff_t *pos, void *pdata)
-+{
-+	struct net_device *dev = pdata;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	u8 tmp[128] = {0};
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		if (strncmp(tmp, "add", 3) == 0)
-+			rtw_mbo_non_pref_chans_set(padapter, &tmp[4], (count - 4));
-+		else if (strncmp(tmp, "delete", 6) == 0)
-+			rtw_mbo_non_pref_chans_del(padapter, &tmp[7], (count - 7));
-+		else {
-+			RTW_ERR("MBO : Invalid format : echo [add|delete] <oper_class>:<chan>:<preference>:<reason>\n");
-+			return -EFAULT;
-+		}
-+	}	
-+
-+#ifdef CONFIG_RTW_WNM
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) &&
-+		check_fwstate(pmlmepriv, WIFI_STATION_STATE)) 
-+		rtw_wnm_issue_action(padapter, RTW_WLAN_ACTION_WNM_NOTIF_REQ, 0, 0);
-+#endif
-+	
-+	return count;
-+}
-+
-+int rtw_mbo_proc_non_pref_chans_get(
-+	struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
-+	struct npref_ch_rtp *prpt = &(prfctl->ch_rtp);
-+	struct npref_ch* pch;
-+	int i,j;
-+	u8 buf[32] = {0};
-+
-+	RTW_PRINT_SEL(m, "op_class                     ch    preference    reason \n");
-+	RTW_PRINT_SEL(m, "=======================================================\n");
-+
-+		
-+	if (prpt->nm_of_rpt == 0) {
-+		RTW_PRINT_SEL(m, " empty table \n");
-+		return 0;
-+	}
-+
-+	for (i=0; i < prpt->nm_of_rpt; i++) {
-+		pch = &prpt->ch_rpt[i];	
-+		buf[0]='\0';
-+		for (j=0; j < pch->nm_of_ch; j++) {
-+			if (j == 0)
-+				rtw_sprintf(buf, 32, "%02u", pch->chs[j]);
-+			else				
-+				rtw_sprintf(buf, 32, "%s,%02u", buf, pch->chs[j]);
-+		}
-+
-+		RTW_PRINT_SEL(m, "    %04u    %20s           %02u        %02u\n",
-+			pch->op_class, buf, pch->preference, pch->reason);		
-+	}
-+	
-+	return 0;
-+}
-+
-+ssize_t rtw_mbo_proc_cell_data_set(
-+	struct file *pfile, const char __user *buffer,
-+	size_t count, loff_t *pos, void *pdata)
-+{
-+	struct net_device *dev = pdata;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	int mbo_cell_data = 0;
-+	u8 tmp[8] = {0};
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp))
-+		return -EFAULT;
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%d", &mbo_cell_data);
-+		if (num == 1) {
-+			rtw_mbo_cell_data_conn = mbo_cell_data;
-+		#ifdef CONFIG_RTW_WNM
-+			if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) &&
-+				check_fwstate(pmlmepriv, WIFI_STATION_STATE)) 
-+				rtw_wnm_issue_action(padapter, RTW_WLAN_ACTION_WNM_NOTIF_REQ, 0, 0);
-+		#endif
-+		}
-+	}
-+
-+
-+	return count;
-+}
-+
-+int rtw_mbo_proc_cell_data_get(
-+	struct seq_file *m, void *v)
-+{
-+#if 0
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+#endif
-+
-+	RTW_PRINT_SEL(m, "Cellular Data Connectivity : %d\n", rtw_mbo_cell_data_conn);
-+	return 0;
-+}
-+
-+static void rtw_mbo_non_pref_chan_subelem_parsing(
-+	_adapter *padapter, u8 *subelem, size_t subelem_len)
-+{
-+	u8 *pnon_pref_chans;
-+	u32 non_pref_chan_offset, op_subelem_len; 
-+	u32 oui_offset = 3;
-+	/* wpa_supplicant don't apped OUI Type */
-+	u32 oui_type_offset = 0;
-+
-+	RTW_MBO_DUMP("Non-preferred Channel subelem : ", subelem , subelem_len);
-+
-+	/* Subelem : 
-+		Vendor Specific | Length | WFA OUI | OUI Type | MBO Attributes */
-+	non_pref_chan_offset = 2 + oui_offset + oui_type_offset;
-+	pnon_pref_chans = subelem + non_pref_chan_offset;
-+	op_subelem_len = subelem_len - non_pref_chan_offset;
-+
-+	/* wpa_supplicant don't indicate non_pref_chan length,
-+		so we cannot get how many non_pref_chan in a wnm notification */
-+	RTW_MBO_DUMP("Non-preferred Channel : ", pnon_pref_chans, op_subelem_len);
-+}
-+
-+void rtw_mbo_wnm_notification_parsing(
-+	_adapter *padapter, const u8 *pdata, size_t data_len)
-+{
-+	u8 *paction;
-+	u8 category, action, dialog, type;
-+	u32 len;
-+
-+	if ((pdata == NULL) || (data_len == 0))
-+		return;
-+
-+	RTW_MBO_DUMP("WNM notification data : ", pdata, data_len);	
-+	paction = (u8 *)pdata + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	category = paction[0];
-+	action = paction[1];
-+	dialog = paction[2];
-+	type = paction[3];
-+
-+	if ((action == RTW_WLAN_ACTION_WNM_NOTIF_REQ) && 
-+		(type == WLAN_EID_VENDOR_SPECIFIC)) {
-+		rtw_mbo_non_pref_chan_subelem_parsing(padapter, &paction[4], 
-+			(data_len - sizeof(struct rtw_ieee80211_hdr_3addr)));
-+	}
-+	
-+}
-+
-+void rtw_mbo_build_wnm_notification(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib)
-+{
-+	struct rf_ctl_t *prfctl = adapter_to_rfctl(padapter);
-+	struct npref_ch_rtp *prpt = &(prfctl->ch_rtp);
-+	struct npref_ch* pch;
-+	u8 subelem_id = WLAN_EID_VENDOR_SPECIFIC;
-+	u8 non_pref_ch_oui[] = {0x50, 0x6F, 0x9A, 0x2};
-+	u8 cell_data_cap_oui[] = {0x50, 0x6F, 0x9A, 0x3};
-+	u8 cell_data_con = rtw_mbo_cell_data_conn;
-+	u8 len, cell_data_con_len = 0, *pcont = *pframe;
-+	int i;
-+
-+	if (rtw_mbo_cell_data_conn > 0) {
-+		len = 0x5;
-+		*pframe = rtw_mbo_set_1byte_ie(*pframe, &subelem_id, &(pattrib->pktlen));
-+		*pframe = rtw_mbo_set_1byte_ie(*pframe, &len, &(pattrib->pktlen));
-+		*pframe = rtw_mbo_set_4byte_ie(*pframe, cell_data_cap_oui, &(pattrib->pktlen));	
-+		*pframe = rtw_mbo_set_1byte_ie(*pframe, &cell_data_con, &(pattrib->pktlen));
-+		RTW_MBO_INFO("%s : Cellular Data Capabilities subelemen\n", __func__);
-+		RTW_MBO_DUMP(":", pcont, len + 2);
-+		pcont += len + 2 ;
-+	}
-+
-+	if (prpt->nm_of_rpt == 0) {
-+		len = 0x4;
-+		*pframe = rtw_mbo_set_1byte_ie(*pframe, &subelem_id, &(pattrib->pktlen));
-+		*pframe = rtw_mbo_set_1byte_ie(*pframe, &len, &(pattrib->pktlen));
-+		*pframe = rtw_mbo_set_4byte_ie(*pframe, non_pref_ch_oui, &(pattrib->pktlen));
-+		RTW_MBO_INFO("%s :Non-preferred Channel Report subelement without data\n", __func__);
-+		return;	
-+	}
-+
-+	for (i=0; i < prpt->nm_of_rpt; i++) {
-+		pch = &prpt->ch_rpt[i];	
-+		/* OUI(3B)  + OUT-type(1B) + op-class(1B) + ch list(nB) 
-+			+ Preference(1B) + reason(1B) */
-+		len = pch->nm_of_ch + 7;
-+		*pframe = rtw_mbo_set_1byte_ie(*pframe, &subelem_id, &(pattrib->pktlen));
-+		*pframe = rtw_mbo_set_1byte_ie(*pframe, &len, &(pattrib->pktlen));
-+		*pframe = rtw_mbo_set_4byte_ie(*pframe, non_pref_ch_oui, &(pattrib->pktlen));	
-+		*pframe = rtw_mbo_set_1byte_ie(*pframe, &pch->op_class, &(pattrib->pktlen));
-+		*pframe = rtw_mbo_set_nbyte_ie(*pframe, pch->nm_of_ch, pch->chs, &(pattrib->pktlen));
-+		*pframe = rtw_mbo_set_1byte_ie(*pframe, &pch->preference, &(pattrib->pktlen));
-+		*pframe = rtw_mbo_set_1byte_ie(*pframe, &pch->reason, &(pattrib->pktlen));
-+		RTW_MBO_INFO("%s :Non-preferred Channel Report subelement\n", __func__);
-+		RTW_MBO_DUMP(":", pcont, len);
-+		pcont = *pframe;
-+	}
-+}
-+
-+void rtw_mbo_build_probe_req_ies(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib)
-+{
-+	u32 len =0;
-+	
-+	rtw_mbo_build_exented_cap(padapter, pframe, pattrib);
-+
-+	len = rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_CELL_DATA_CAP_ID);
-+	if ((len == 0) || (len > 3)) {
-+		RTW_ERR("MBO : build Cellular Data Capabilities attribute fail(len=%u)\n", len);
-+		return;
-+	}
-+	
-+	rtw_mbo_build_mbo_ie_hdr(pframe, pattrib, len);
-+	rtw_mbo_build_cell_data_cap_attr(padapter, pframe, pattrib);
-+}
-+
-+void rtw_mbo_build_assoc_req_ies(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib)
-+{
-+	u32 len = 0;
-+	
-+	rtw_mbo_build_supp_op_class_elem(padapter, pframe, pattrib);
-+
-+	len += rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_CELL_DATA_CAP_ID);
-+	len += rtw_mbo_attr_sz_get(padapter, RTW_MBO_ATTR_NPREF_CH_RPT_ID);
-+	if ((len == 0)|| (len < 3)) {
-+		RTW_ERR("MBO : build assoc MBO IE fail(len=%u)\n", len);
-+		return;
-+	}
-+	
-+	rtw_mbo_build_mbo_ie_hdr(pframe, pattrib, len);
-+	rtw_mbo_build_cell_data_cap_attr(padapter, pframe, pattrib);
-+	rtw_mbo_build_npref_ch_rpt_attr(padapter, pframe, pattrib);
-+}
-+
-+#endif /* CONFIG_RTW_MBO */
-diff --git a/drivers/staging/rtl8723cs/core/rtw_mem.c b/drivers/staging/rtl8723cs/core/rtw_mem.c
-new file mode 100644
-index 000000000000..d42a4fb038c6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_mem.c
-@@ -0,0 +1,171 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+#include <rtw_mem.h>
-+
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("Realtek Wireless Lan Driver");
-+MODULE_AUTHOR("Realtek Semiconductor Corp.");
-+MODULE_VERSION("DRIVERVERSION");
-+
-+/* for MAX_RECVBUF_SZ */
-+#if defined(CONFIG_RTL8188E)
-+#include <rtl8188e_hal.h>
-+#elif defined(CONFIG_RTL8188F)
-+#include <rtl8188f_hal.h>
-+#elif defined(CONFIG_RTL8188GTV)
-+#include <rtl8188gtv_hal.h>
-+#elif defined(CONFIG_RTL8710B)
-+#include <rtl8710b_hal.h>
-+#elif defined(CONFIG_RTL8192E)
-+#include <rtl8192e_hal.h>
-+#elif defined(CONFIG_RTL8192F)
-+#include <rtl8192f_hal.h>
-+#elif defined(CONFIG_RTL8723B)
-+#include <rtl8723b_hal.h>
-+#elif defined(CONFIG_RTL8703B)
-+#include <rtl8703b_hal.h>
-+#elif defined(CONFIG_RTL8723D)
-+#include <rtl8723d_hal.h>
-+#elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+#include <rtl8812a_hal.h>
-+#elif defined(CONFIG_RTL8822B)
-+#include <rtl8822b_hal.h>
-+#elif defined(CONFIG_RTL8822C)
-+#include <rtl8822c_hal.h>
-+#elif defined(CONFIG_RTL8814A)
-+#include <rtl8814a_hal.h>
-+#elif defined(CONFIG_RTL8814B)
-+#include <rtl8814b_hal.h>
-+#endif
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+#define MAX_RTKM_RECVBUF_SZ		MAX_RECVBUF_SZ
-+#define MAX_RTKM_NR_PREALLOC_RECV_SKB	NR_RECVBUFF
-+#else /* !CONFIG_SDIO_HCI */
-+#ifdef CONFIG_PLATFORM_MSTAR_HIGH
-+	#define MAX_RTKM_RECVBUF_SZ (31744) /* 31k */
-+#else
-+	#define MAX_RTKM_RECVBUF_SZ (15360) /* 15k */
-+#endif /* CONFIG_PLATFORM_MSTAR_HIGH */
-+#define MAX_RTKM_NR_PREALLOC_RECV_SKB 16
-+#endif /* !CONFIG_SDIO_HCI */
-+
-+struct sk_buff_head rtk_skb_mem_q;
-+struct u8 *rtk_buf_mem[NR_RECVBUFF];
-+
-+struct u8	*rtw_get_buf_premem(int index)
-+{
-+	printk("%s, rtk_buf_mem index : %d\n", __func__, index);
-+	return rtk_buf_mem[index];
-+}
-+
-+u16 rtw_rtkm_get_buff_size(void)
-+{
-+	return MAX_RTKM_RECVBUF_SZ;
-+}
-+EXPORT_SYMBOL(rtw_rtkm_get_buff_size);
-+
-+u8 rtw_rtkm_get_nr_recv_skb(void)
-+{
-+	return MAX_RTKM_NR_PREALLOC_RECV_SKB;
-+}
-+EXPORT_SYMBOL(rtw_rtkm_get_nr_recv_skb);
-+
-+struct sk_buff *rtw_alloc_skb_premem(u16 in_size)
-+{
-+	struct sk_buff *skb = NULL;
-+
-+	if (in_size > MAX_RTKM_RECVBUF_SZ) {
-+		pr_info("warning %s: driver buffer size(%d) > rtkm buffer size(%d)\n", __func__, in_size, MAX_RTKM_RECVBUF_SZ);
-+		WARN_ON(1);
-+		return skb;
-+	}
-+
-+	skb = skb_dequeue(&rtk_skb_mem_q);
-+
-+	printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
-+
-+	return skb;
-+}
-+EXPORT_SYMBOL(rtw_alloc_skb_premem);
-+
-+int rtw_free_skb_premem(struct sk_buff *pskb)
-+{
-+	if (!pskb)
-+		return -1;
-+
-+	if (skb_queue_len(&rtk_skb_mem_q) >= MAX_RTKM_NR_PREALLOC_RECV_SKB)
-+		return -1;
-+
-+	skb_queue_tail(&rtk_skb_mem_q, pskb);
-+
-+	printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(rtw_free_skb_premem);
-+
-+static int __init rtw_mem_init(void)
-+{
-+	int i;
-+	SIZE_PTR tmpaddr = 0;
-+	SIZE_PTR alignment = 0;
-+	struct sk_buff *pskb = NULL;
-+
-+	printk("%s\n", __func__);
-+	pr_info("MAX_RTKM_NR_PREALLOC_RECV_SKB: %d\n", MAX_RTKM_NR_PREALLOC_RECV_SKB);
-+	pr_info("MAX_RTKM_RECVBUF_SZ: %d\n", MAX_RTKM_RECVBUF_SZ);
-+
-+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
-+	for (i = 0; i < NR_RECVBUFF; i++)
-+		rtk_buf_mem[i] = usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);
-+#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
-+
-+	skb_queue_head_init(&rtk_skb_mem_q);
-+
-+	for (i = 0; i < MAX_RTKM_NR_PREALLOC_RECV_SKB; i++) {
-+		pskb = __dev_alloc_skb(MAX_RTKM_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
-+		if (pskb) {
-+			tmpaddr = (SIZE_PTR)pskb->data;
-+			alignment = tmpaddr & (RECVBUFF_ALIGN_SZ - 1);
-+			skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment));
-+
-+			skb_queue_tail(&rtk_skb_mem_q, pskb);
-+		} else
-+			printk("%s, alloc skb memory fail!\n", __func__);
-+
-+		pskb = NULL;
-+	}
-+
-+	printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
-+
-+	return 0;
-+
-+}
-+
-+static void __exit rtw_mem_exit(void)
-+{
-+	if (skb_queue_len(&rtk_skb_mem_q))
-+		printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
-+
-+	skb_queue_purge(&rtk_skb_mem_q);
-+
-+	printk("%s\n", __func__);
-+}
-+
-+module_init(rtw_mem_init);
-+module_exit(rtw_mem_exit);
-diff --git a/drivers/staging/rtl8723cs/core/rtw_mi.c b/drivers/staging/rtl8723cs/core/rtw_mi.c
-new file mode 100644
-index 000000000000..099cd368b330
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_mi.c
-@@ -0,0 +1,1546 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_MI_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	if (!ch) {
-+		dvobj->union_ch_bak = dvobj->union_ch;
-+		dvobj->union_bw_bak = dvobj->union_bw;
-+		dvobj->union_offset_bak = dvobj->union_offset;
-+	}
-+	dvobj->union_ch = ch;
-+	dvobj->union_bw = bw;
-+	dvobj->union_offset = offset;
-+}
-+
-+#ifdef DBG_IFACE_STATUS
-+#ifdef CONFIG_P2P
-+static u8 _rtw_mi_p2p_listen_scan_chk(_adapter *adapter)
-+{
-+	int i;
-+	_adapter *iface;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	u8 p2p_listen_scan_state = _FALSE;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN) ||
-+			rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_SCAN)) {
-+			p2p_listen_scan_state = _TRUE;
-+			break;
-+		}
-+	}
-+	return p2p_listen_scan_state;
-+}
-+#endif
-+#endif
-+
-+u8 rtw_mi_stayin_union_ch_chk(_adapter *adapter)
-+{
-+	u8 rst = _TRUE;
-+	u8 u_ch, u_bw, u_offset;
-+	u8 o_ch, o_bw, o_offset;
-+
-+	u_ch = rtw_mi_get_union_chan(adapter);
-+	u_bw = rtw_mi_get_union_bw(adapter);
-+	u_offset = rtw_mi_get_union_offset(adapter);
-+
-+	o_ch = rtw_get_oper_ch(adapter);
-+	o_bw = rtw_get_oper_bw(adapter);
-+	o_offset = rtw_get_oper_choffset(adapter);
-+
-+	if ((u_ch != o_ch) || (u_bw != o_bw) || (u_offset != o_offset))
-+		rst = _FALSE;
-+
-+	#ifdef DBG_IFACE_STATUS
-+	if (rst == _FALSE) {
-+		RTW_ERR("%s Not stay in union channel\n", __func__);
-+		if (GET_HAL_DATA(adapter)->bScanInProcess == _TRUE)
-+			RTW_ERR("ScanInProcess\n");
-+		#ifdef CONFIG_P2P
-+		if (_rtw_mi_p2p_listen_scan_chk(adapter))
-+			RTW_ERR("P2P in listen or scan state\n");
-+		#endif
-+		RTW_ERR("union ch, bw, offset: %u,%u,%u\n", u_ch, u_bw, u_offset);
-+		RTW_ERR("oper ch, bw, offset: %u,%u,%u\n", o_ch, o_bw, o_offset);
-+		RTW_ERR("=========================\n");
-+	}
-+	#endif
-+	return rst;
-+}
-+
-+u8 rtw_mi_stayin_union_band_chk(_adapter *adapter)
-+{
-+	u8 rst = _TRUE;
-+	u8 u_ch, o_ch;
-+	u8 u_band, o_band;
-+
-+	u_ch = rtw_mi_get_union_chan(adapter);
-+	o_ch = rtw_get_oper_ch(adapter);
-+	u_band = (u_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G;
-+	o_band = (o_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G;
-+
-+	if (u_ch != o_ch)
-+		if(u_band != o_band)
-+			rst = _FALSE;
-+
-+	#ifdef DBG_IFACE_STATUS
-+	if (rst == _FALSE)
-+		RTW_ERR("%s Not stay in union band\n", __func__);
-+	#endif
-+
-+	return rst;
-+}
-+
-+/* Find union about ch, bw, ch_offset of all linked/linking interfaces */
-+int rtw_mi_get_ch_setting_union_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, u8 *ch, u8 *bw, u8 *offset)
-+{
-+	_adapter *iface;
-+	struct mlme_ext_priv *mlmeext;
-+	int i;
-+	u8 ch_ret = 0;
-+	u8 bw_ret = CHANNEL_WIDTH_20;
-+	u8 offset_ret = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	int num = 0;
-+
-+	if (ch)
-+		*ch = 0;
-+	if (bw)
-+		*bw = CHANNEL_WIDTH_20;
-+	if (offset)
-+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface || !(ifbmp & BIT(iface->iface_id)))
-+			continue;
-+
-+		mlmeext = &iface->mlmeextpriv;
-+
-+		if (!check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_LINKING))
-+			continue;
-+
-+		if (check_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING))
-+			continue;
-+
-+		if (num == 0) {
-+			ch_ret = mlmeext->cur_channel;
-+			bw_ret = mlmeext->cur_bwmode;
-+			offset_ret = mlmeext->cur_ch_offset;
-+			num++;
-+			continue;
-+		}
-+
-+		if (ch_ret != mlmeext->cur_channel) {
-+			num = 0;
-+			break;
-+		}
-+
-+		if (bw_ret < mlmeext->cur_bwmode) {
-+			bw_ret = mlmeext->cur_bwmode;
-+			offset_ret = mlmeext->cur_ch_offset;
-+		} else if (bw_ret == mlmeext->cur_bwmode && offset_ret != mlmeext->cur_ch_offset) {
-+			num = 0;
-+			break;
-+		}
-+
-+		num++;
-+	}
-+
-+	if (num) {
-+		if (ch)
-+			*ch = ch_ret;
-+		if (bw)
-+			*bw = bw_ret;
-+		if (offset)
-+			*offset = offset_ret;
-+	}
-+
-+	return num;
-+}
-+
-+inline int rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)
-+{
-+	return rtw_mi_get_ch_setting_union_by_ifbmp(adapter_to_dvobj(adapter), 0xFF, ch, bw, offset);
-+}
-+
-+inline int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)
-+{
-+	return rtw_mi_get_ch_setting_union_by_ifbmp(adapter_to_dvobj(adapter), 0xFF & ~BIT(adapter->iface_id), ch, bw, offset);
-+}
-+
-+void rtw_mi_status_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, struct mi_state *mstate)
-+{
-+	_adapter *iface;
-+	int i;
-+
-+	_rtw_memset(mstate, 0, sizeof(struct mi_state));
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface || !(ifbmp & BIT(iface->iface_id)))
-+			continue;
-+
-+		if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) {
-+			MSTATE_STA_NUM(mstate)++;
-+			if (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+				MSTATE_STA_LD_NUM(mstate)++;
-+
-+				#ifdef CONFIG_TDLS
-+				if (iface->tdlsinfo.link_established == _TRUE)
-+					MSTATE_TDLS_LD_NUM(mstate)++;
-+				#endif
-+				#ifdef CONFIG_P2P
-+				if (MLME_IS_GC(iface))
-+					MSTATE_P2P_GC_NUM(mstate)++;
-+				#endif
-+			}
-+			if (check_fwstate(&iface->mlmepriv, WIFI_UNDER_LINKING) == _TRUE)
-+				MSTATE_STA_LG_NUM(mstate)++;
-+
-+#ifdef CONFIG_AP_MODE
-+		} else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) {
-+			if (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+				MSTATE_AP_NUM(mstate)++;
-+				if (iface->stapriv.asoc_sta_count > 2)
-+					MSTATE_AP_LD_NUM(mstate)++;
-+				#ifdef CONFIG_P2P
-+				if (MLME_IS_GO(iface))
-+					MSTATE_P2P_GO_NUM(mstate)++;
-+				#endif
-+			} else
-+				MSTATE_AP_STARTING_NUM(mstate)++;
-+#endif
-+
-+		} else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE
-+			&& check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE
-+		) {
-+			MSTATE_ADHOC_NUM(mstate)++;
-+			if (iface->stapriv.asoc_sta_count > 2)
-+				MSTATE_ADHOC_LD_NUM(mstate)++;
-+
-+#ifdef CONFIG_RTW_MESH
-+		} else if (check_fwstate(&iface->mlmepriv, WIFI_MESH_STATE) == _TRUE
-+			&& check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE
-+		) {
-+			MSTATE_MESH_NUM(mstate)++;
-+			if (iface->stapriv.asoc_sta_count > 2)
-+				MSTATE_MESH_LD_NUM(mstate)++;
-+#endif
-+
-+		}
-+
-+		if (check_fwstate(&iface->mlmepriv, WIFI_UNDER_WPS) == _TRUE)
-+			MSTATE_WPS_NUM(mstate)++;
-+
-+		if (check_fwstate(&iface->mlmepriv, WIFI_UNDER_SURVEY) == _TRUE) {
-+			MSTATE_SCAN_NUM(mstate)++;
-+
-+			if (mlmeext_scan_state(&iface->mlmeextpriv) != SCAN_DISABLE
-+				&& mlmeext_scan_state(&iface->mlmeextpriv) != SCAN_BACK_OP)
-+				MSTATE_SCAN_ENTER_NUM(mstate)++;
-+		}
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+		if (rtw_cfg80211_get_is_mgmt_tx(iface))
-+			MSTATE_MGMT_TX_NUM(mstate)++;
-+
-+		if (rtw_cfg80211_get_is_roch(iface) == _TRUE)
-+			MSTATE_ROCH_NUM(mstate)++;
-+
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+#ifdef CONFIG_P2P
-+		if (MLME_IS_PD(iface))
-+			MSTATE_P2P_DV_NUM(mstate)++;
-+#endif
-+	}
-+}
-+
-+inline void rtw_mi_status(_adapter *adapter, struct mi_state *mstate)
-+{
-+	return rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), 0xFF, mstate);
-+}
-+
-+inline void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate)
-+{
-+	return rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), 0xFF & ~BIT(adapter->iface_id), mstate);
-+}
-+
-+inline void rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate)
-+{
-+	return rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), BIT(adapter->iface_id), mstate);
-+}
-+
-+inline void rtw_mi_status_merge(struct mi_state *d, struct mi_state *a)
-+{
-+	d->sta_num += a->sta_num;
-+	d->ld_sta_num += a->ld_sta_num;
-+	d->lg_sta_num += a->lg_sta_num;
-+#ifdef CONFIG_TDLS
-+	d->ld_tdls_num += a->ld_tdls_num;
-+#endif
-+#ifdef CONFIG_AP_MODE
-+	d->ap_num += a->ap_num;
-+	d->ld_ap_num += a->ld_ap_num;
-+#endif
-+	d->adhoc_num += a->adhoc_num;
-+	d->ld_adhoc_num += a->ld_adhoc_num;
-+#ifdef CONFIG_RTW_MESH
-+	d->mesh_num += a->mesh_num;
-+	d->ld_mesh_num += a->ld_mesh_num;
-+#endif
-+	d->scan_num += a->scan_num;
-+	d->scan_enter_num += a->scan_enter_num;
-+	d->uwps_num += a->uwps_num;
-+#ifdef CONFIG_IOCTL_CFG80211
-+	#ifdef CONFIG_P2P
-+	d->roch_num += a->roch_num;
-+	#endif
-+	d->mgmt_tx_num += a->mgmt_tx_num;
-+#endif
-+}
-+
-+void dump_mi_status(void *sel, struct dvobj_priv *dvobj)
-+{
-+	RTW_PRINT_SEL(sel, "== dvobj-iface_state ==\n");
-+	RTW_PRINT_SEL(sel, "sta_num:%d\n", DEV_STA_NUM(dvobj));
-+	RTW_PRINT_SEL(sel, "linking_sta_num:%d\n", DEV_STA_LG_NUM(dvobj));
-+	RTW_PRINT_SEL(sel, "linked_sta_num:%d\n", DEV_STA_LD_NUM(dvobj));
-+#ifdef CONFIG_TDLS
-+	RTW_PRINT_SEL(sel, "linked_tdls_num:%d\n", DEV_TDLS_LD_NUM(dvobj));
-+#endif
-+#ifdef CONFIG_AP_MODE
-+	RTW_PRINT_SEL(sel, "ap_num:%d\n", DEV_AP_NUM(dvobj));
-+	RTW_PRINT_SEL(sel, "starting_ap_num:%d\n", DEV_AP_STARTING_NUM(dvobj));
-+	RTW_PRINT_SEL(sel, "linked_ap_num:%d\n", DEV_AP_LD_NUM(dvobj));
-+#endif
-+	RTW_PRINT_SEL(sel, "adhoc_num:%d\n", DEV_ADHOC_NUM(dvobj));
-+	RTW_PRINT_SEL(sel, "linked_adhoc_num:%d\n", DEV_ADHOC_LD_NUM(dvobj));
-+#ifdef CONFIG_RTW_MESH
-+	RTW_PRINT_SEL(sel, "mesh_num:%d\n", DEV_MESH_NUM(dvobj));
-+	RTW_PRINT_SEL(sel, "linked_mesh_num:%d\n", DEV_MESH_LD_NUM(dvobj));
-+#endif
-+#ifdef CONFIG_P2P
-+	RTW_PRINT_SEL(sel, "p2p_device_num:%d\n", DEV_P2P_DV_NUM(dvobj));
-+	RTW_PRINT_SEL(sel, "p2p_gc_num:%d\n", DEV_P2P_GC_NUM(dvobj));
-+	RTW_PRINT_SEL(sel, "p2p_go_num:%d\n", DEV_P2P_GO_NUM(dvobj));
-+#endif
-+	RTW_PRINT_SEL(sel, "scan_num:%d\n", DEV_SCAN_NUM(dvobj));
-+	RTW_PRINT_SEL(sel, "under_wps_num:%d\n", DEV_WPS_NUM(dvobj));
-+#if defined(CONFIG_IOCTL_CFG80211)
-+	#if defined(CONFIG_P2P)
-+	RTW_PRINT_SEL(sel, "roch_num:%d\n", DEV_ROCH_NUM(dvobj));
-+	#endif
-+	RTW_PRINT_SEL(sel, "mgmt_tx_num:%d\n", DEV_MGMT_TX_NUM(dvobj));
-+#endif
-+	RTW_PRINT_SEL(sel, "union_ch:%d\n", DEV_U_CH(dvobj));
-+	RTW_PRINT_SEL(sel, "union_bw:%d\n", DEV_U_BW(dvobj));
-+	RTW_PRINT_SEL(sel, "union_offset:%d\n", DEV_U_OFFSET(dvobj));
-+	RTW_PRINT_SEL(sel, "================\n\n");
-+}
-+
-+void dump_dvobj_mi_status(void *sel, const char *fun_name, _adapter *adapter)
-+{
-+	RTW_INFO("\n[ %s ] call %s\n", fun_name, __func__);
-+	dump_mi_status(sel, adapter_to_dvobj(adapter));
-+}
-+
-+inline void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state)
-+{
-+	_adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mi_state *iface_state = &dvobj->iface_state;
-+	struct mi_state tmp_mstate;
-+
-+	if (state == WIFI_MONITOR_STATE
-+		|| state == 0xFFFFFFFF
-+	)
-+		return;
-+
-+	if (0)
-+		RTW_INFO("%s => will change or clean state to 0x%08x\n", __func__, state);
-+
-+	rtw_mi_status(adapter, &tmp_mstate);
-+	_rtw_memcpy(iface_state, &tmp_mstate, sizeof(struct mi_state));
-+
-+#ifdef DBG_IFACE_STATUS
-+	DBG_IFACE_STATUS_DUMP(adapter);
-+#endif
-+}
-+u8 rtw_mi_check_status(_adapter *adapter, u8 type)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mi_state *iface_state = &dvobj->iface_state;
-+	u8 ret = _FALSE;
-+
-+#ifdef DBG_IFACE_STATUS
-+	DBG_IFACE_STATUS_DUMP(adapter);
-+	RTW_INFO("%s-"ADPT_FMT" check type:%d\n", __func__, ADPT_ARG(adapter), type);
-+#endif
-+
-+	switch (type) {
-+	case MI_LINKED:
-+		if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_NUM(iface_state) || MSTATE_ADHOC_NUM(iface_state) || MSTATE_MESH_NUM(iface_state)) /*check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE)*/
-+			ret = _TRUE;
-+		break;
-+	case MI_ASSOC:
-+		if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_LD_NUM(iface_state) || MSTATE_ADHOC_LD_NUM(iface_state) || MSTATE_MESH_LD_NUM(iface_state))
-+			ret = _TRUE;
-+		break;
-+	case MI_UNDER_WPS:
-+		if (MSTATE_WPS_NUM(iface_state))
-+			ret = _TRUE;
-+		break;
-+
-+	case MI_AP_MODE:
-+		if (MSTATE_AP_NUM(iface_state))
-+			ret = _TRUE;
-+		break;
-+	case MI_AP_ASSOC:
-+		if (MSTATE_AP_LD_NUM(iface_state))
-+			ret = _TRUE;
-+		break;
-+
-+	case MI_ADHOC:
-+		if (MSTATE_ADHOC_NUM(iface_state))
-+			ret = _TRUE;
-+		break;
-+	case MI_ADHOC_ASSOC:
-+		if (MSTATE_ADHOC_LD_NUM(iface_state))
-+			ret = _TRUE;
-+		break;
-+
-+#ifdef CONFIG_RTW_MESH
-+	case MI_MESH:
-+		if (MSTATE_MESH_NUM(iface_state))
-+			ret = _TRUE;
-+		break;
-+	case MI_MESH_ASSOC:
-+		if (MSTATE_MESH_LD_NUM(iface_state))
-+			ret = _TRUE;
-+		break;
-+#endif
-+
-+	case MI_STA_NOLINK: /* this is misleading, but not used now */
-+		if (MSTATE_STA_NUM(iface_state) && (!(MSTATE_STA_LD_NUM(iface_state) || MSTATE_STA_LG_NUM(iface_state))))
-+			ret = _TRUE;
-+		break;
-+	case MI_STA_LINKED:
-+		if (MSTATE_STA_LD_NUM(iface_state))
-+			ret = _TRUE;
-+		break;
-+	case MI_STA_LINKING:
-+		if (MSTATE_STA_LG_NUM(iface_state))
-+			ret = _TRUE;
-+		break;
-+
-+	default:
-+		break;
-+	}
-+	return ret;
-+}
-+
-+/*
-+* return value : 0 is failed or have not interface meet condition
-+* return value : !0 is success or interface numbers which meet condition
-+* return value of ops_func must be _TRUE or _FALSE
-+*/
-+static u8 _rtw_mi_process(_adapter *padapter, bool exclude_self,
-+		  void *data, u8(*ops_func)(_adapter *padapter, void *data))
-+{
-+	int i;
-+	_adapter *iface;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	u8 ret = 0;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if ((iface) && rtw_is_adapter_up(iface)) {
-+
-+			if ((exclude_self) && (iface == padapter))
-+				continue;
-+
-+			if (ops_func)
-+				if (_TRUE == ops_func(iface, data))
-+					ret++;
-+		}
-+	}
-+	return ret;
-+}
-+static u8 _rtw_mi_process_without_schk(_adapter *padapter, bool exclude_self,
-+		  void *data, u8(*ops_func)(_adapter *padapter, void *data))
-+{
-+	int i;
-+	_adapter *iface;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	u8 ret = 0;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface) {
-+			if ((exclude_self) && (iface == padapter))
-+				continue;
-+
-+			if (ops_func)
-+				if (ops_func(iface, data) == _TRUE)
-+					ret++;
-+		}
-+	}
-+	return ret;
-+}
-+
-+static u8 _rtw_mi_netif_caroff_qstop(_adapter *padapter, void *data)
-+{
-+	struct net_device *pnetdev = padapter->pnetdev;
-+
-+	rtw_netif_carrier_off(pnetdev);
-+	rtw_netif_stop_queue(pnetdev);
-+	return _TRUE;
-+}
-+u8 rtw_mi_netif_caroff_qstop(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_caroff_qstop);
-+}
-+u8 rtw_mi_buddy_netif_caroff_qstop(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caroff_qstop);
-+}
-+
-+static u8 _rtw_mi_netif_caron_qstart(_adapter *padapter, void *data)
-+{
-+	struct net_device *pnetdev = padapter->pnetdev;
-+
-+	rtw_netif_carrier_on(pnetdev);
-+	rtw_netif_start_queue(pnetdev);
-+	return _TRUE;
-+}
-+u8 rtw_mi_netif_caron_qstart(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_caron_qstart);
-+}
-+u8 rtw_mi_buddy_netif_caron_qstart(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caron_qstart);
-+}
-+
-+static u8 _rtw_mi_netif_stop_queue(_adapter *padapter, void *data)
-+{
-+	struct net_device *pnetdev = padapter->pnetdev;
-+
-+	rtw_netif_stop_queue(pnetdev);
-+	return _TRUE;
-+}
-+u8 rtw_mi_netif_stop_queue(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_stop_queue);
-+}
-+u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_stop_queue);
-+}
-+
-+static u8 _rtw_mi_netif_wake_queue(_adapter *padapter, void *data)
-+{
-+	struct net_device *pnetdev = padapter->pnetdev;
-+
-+	if (pnetdev)
-+		rtw_netif_wake_queue(pnetdev);
-+	return _TRUE;
-+}
-+u8 rtw_mi_netif_wake_queue(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_wake_queue);
-+}
-+u8 rtw_mi_buddy_netif_wake_queue(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_wake_queue);
-+}
-+
-+static u8 _rtw_mi_netif_carrier_on(_adapter *padapter, void *data)
-+{
-+	struct net_device *pnetdev = padapter->pnetdev;
-+
-+	if (pnetdev)
-+		rtw_netif_carrier_on(pnetdev);
-+	return _TRUE;
-+}
-+u8 rtw_mi_netif_carrier_on(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_carrier_on);
-+}
-+u8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_on);
-+}
-+
-+static u8 _rtw_mi_netif_carrier_off(_adapter *padapter, void *data)
-+{
-+	struct net_device *pnetdev = padapter->pnetdev;
-+
-+	if (pnetdev)
-+		rtw_netif_carrier_off(pnetdev);
-+	return _TRUE;
-+}
-+u8 rtw_mi_netif_carrier_off(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_carrier_off);
-+}
-+u8 rtw_mi_buddy_netif_carrier_off(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_off);
-+}
-+
-+static u8 _rtw_mi_scan_abort(_adapter *adapter, void *data)
-+{
-+	bool bwait = *(bool *)data;
-+
-+	if (bwait)
-+		rtw_scan_abort(adapter);
-+	else
-+		rtw_scan_abort_no_wait(adapter);
-+
-+	return _TRUE;
-+}
-+void rtw_mi_scan_abort(_adapter *adapter, bool bwait)
-+{
-+	bool in_data = bwait;
-+
-+	_rtw_mi_process(adapter, _FALSE, &in_data, _rtw_mi_scan_abort);
-+
-+}
-+void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait)
-+{
-+	bool in_data = bwait;
-+
-+	_rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_scan_abort);
-+}
-+
-+static u32 _rtw_mi_start_drv_threads(_adapter *adapter, bool exclude_self)
-+{
-+	int i;
-+	_adapter *iface = NULL;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	u32 _status = _SUCCESS;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface) {
-+			if ((exclude_self) && (iface == adapter))
-+				continue;
-+			if (rtw_start_drv_threads(iface) == _FAIL) {
-+				_status = _FAIL;
-+				break;
-+			}
-+		}
-+	}
-+	return _status;
-+}
-+u32 rtw_mi_start_drv_threads(_adapter *adapter)
-+{
-+	return _rtw_mi_start_drv_threads(adapter, _FALSE);
-+}
-+u32 rtw_mi_buddy_start_drv_threads(_adapter *adapter)
-+{
-+	return _rtw_mi_start_drv_threads(adapter, _TRUE);
-+}
-+
-+static void _rtw_mi_stop_drv_threads(_adapter *adapter, bool exclude_self)
-+{
-+	int i;
-+	_adapter *iface = NULL;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface) {
-+			if ((exclude_self) && (iface == adapter))
-+				continue;
-+			rtw_stop_drv_threads(iface);
-+		}
-+	}
-+}
-+void rtw_mi_stop_drv_threads(_adapter *adapter)
-+{
-+	_rtw_mi_stop_drv_threads(adapter, _FALSE);
-+}
-+void rtw_mi_buddy_stop_drv_threads(_adapter *adapter)
-+{
-+	_rtw_mi_stop_drv_threads(adapter, _TRUE);
-+}
-+
-+static u8 _rtw_mi_cancel_all_timer(_adapter *adapter, void *data)
-+{
-+	rtw_cancel_all_timer(adapter);
-+	return _TRUE;
-+}
-+void rtw_mi_cancel_all_timer(_adapter *adapter)
-+{
-+	_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_cancel_all_timer);
-+}
-+void rtw_mi_buddy_cancel_all_timer(_adapter *adapter)
-+{
-+	_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_cancel_all_timer);
-+}
-+
-+static u8 _rtw_mi_reset_drv_sw(_adapter *adapter, void *data)
-+{
-+	rtw_reset_drv_sw(adapter);
-+	return _TRUE;
-+}
-+void rtw_mi_reset_drv_sw(_adapter *adapter)
-+{
-+	_rtw_mi_process_without_schk(adapter, _FALSE, NULL, _rtw_mi_reset_drv_sw);
-+}
-+void rtw_mi_buddy_reset_drv_sw(_adapter *adapter)
-+{
-+	_rtw_mi_process_without_schk(adapter, _TRUE, NULL, _rtw_mi_reset_drv_sw);
-+}
-+
-+static u8 _rtw_mi_intf_start(_adapter *adapter, void *data)
-+{
-+	rtw_intf_start(adapter);
-+	return _TRUE;
-+}
-+void rtw_mi_intf_start(_adapter *adapter)
-+{
-+	_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_intf_start);
-+}
-+void rtw_mi_buddy_intf_start(_adapter *adapter)
-+{
-+	_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_intf_start);
-+}
-+
-+static u8 _rtw_mi_intf_stop(_adapter *adapter, void *data)
-+{
-+	rtw_intf_stop(adapter);
-+	return _TRUE;
-+}
-+void rtw_mi_intf_stop(_adapter *adapter)
-+{
-+	_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_intf_stop);
-+}
-+void rtw_mi_buddy_intf_stop(_adapter *adapter)
-+{
-+	_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_intf_stop);
-+}
-+
-+#ifdef CONFIG_NEW_NETDEV_HDL
-+u8 rtw_mi_hal_iface_init(_adapter *padapter)
-+{
-+	int i;
-+	_adapter *iface;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	u8 ret = _TRUE;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface && iface->netif_up)
-+			rtw_hal_iface_init(padapter);
-+	}
-+	return ret;
-+}
-+#endif
-+
-+static u8 _rtw_mi_suspend_free_assoc_resource(_adapter *padapter, void *data)
-+{
-+	return rtw_suspend_free_assoc_resource(padapter);
-+}
-+void rtw_mi_suspend_free_assoc_resource(_adapter *adapter)
-+{
-+	_rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_suspend_free_assoc_resource);
-+}
-+void rtw_mi_buddy_suspend_free_assoc_resource(_adapter *adapter)
-+{
-+	_rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_suspend_free_assoc_resource);
-+}
-+
-+static u8 _rtw_mi_is_scan_deny(_adapter *adapter, void *data)
-+{
-+	return rtw_is_scan_deny(adapter);
-+}
-+
-+u8 rtw_mi_is_scan_deny(_adapter *adapter)
-+{
-+	return _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_is_scan_deny);
-+
-+}
-+u8 rtw_mi_buddy_is_scan_deny(_adapter *adapter)
-+{
-+	return _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_is_scan_deny);
-+}
-+
-+#ifdef CONFIG_SET_SCAN_DENY_TIMER
-+static u8 _rtw_mi_set_scan_deny(_adapter *adapter, void *data)
-+{
-+	u32 ms = *(u32 *)data;
-+
-+	rtw_set_scan_deny(adapter, ms);
-+	return _TRUE;
-+}
-+void rtw_mi_set_scan_deny(_adapter *adapter, u32 ms)
-+{
-+	u32 in_data = ms;
-+
-+	_rtw_mi_process(adapter, _FALSE, &in_data, _rtw_mi_set_scan_deny);
-+}
-+void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms)
-+{
-+	u32 in_data = ms;
-+
-+	_rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_set_scan_deny);
-+}
-+#endif /*CONFIG_SET_SCAN_DENY_TIMER*/
-+
-+#ifdef CONFIG_AP_MODE
-+static u8 _rtw_mi_beacon_update(_adapter *padapter, void *data)
-+{
-+	if (!MLME_IS_STA(padapter)
-+	    && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+		RTW_INFO(ADPT_FMT" - update_beacon\n", ADPT_ARG(padapter));
-+		update_beacon(padapter, 0xFF, NULL, _TRUE, 0);
-+	}
-+	return _TRUE;
-+}
-+
-+void rtw_mi_beacon_update(_adapter *padapter)
-+{
-+	_rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_beacon_update);
-+}
-+
-+void rtw_mi_buddy_beacon_update(_adapter *padapter)
-+{
-+	_rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_beacon_update);
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+#ifndef CONFIG_MI_WITH_MBSSID_CAM
-+static u8 _rtw_mi_hal_dump_macaddr(_adapter *padapter, void *sel)
-+{
-+	u8 mac_addr[ETH_ALEN] = {0};
-+
-+	rtw_hal_get_hwreg(padapter, HW_VAR_MAC_ADDR, mac_addr);
-+	RTW_PRINT_SEL(sel, ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n",
-+					ADPT_ARG(padapter), padapter->hw_port, MAC_ARG(mac_addr));
-+
-+	return _TRUE;
-+}
-+void rtw_mi_hal_dump_macaddr(void *sel, _adapter *padapter)
-+{
-+	_rtw_mi_process(padapter, _FALSE, sel, _rtw_mi_hal_dump_macaddr);
-+}
-+void rtw_mi_buddy_hal_dump_macaddr(void *sel, _adapter *padapter)
-+{
-+	_rtw_mi_process(padapter, _TRUE, sel, _rtw_mi_hal_dump_macaddr);
-+}
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+static u8 _rtw_mi_xmit_tasklet_schedule(_adapter *padapter, void *data)
-+{
-+	if (rtw_txframes_pending(padapter)) {
-+		/* try to deal with the pending packets */
-+		tasklet_hi_schedule(&(padapter->xmitpriv.xmit_tasklet));
-+	}
-+	return _TRUE;
-+}
-+void rtw_mi_xmit_tasklet_schedule(_adapter *padapter)
-+{
-+	_rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_xmit_tasklet_schedule);
-+}
-+void rtw_mi_buddy_xmit_tasklet_schedule(_adapter *padapter)
-+{
-+	_rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_xmit_tasklet_schedule);
-+}
-+#endif
-+
-+u8 _rtw_mi_busy_traffic_check(_adapter *padapter, void *data)
-+{
-+	return padapter->mlmepriv.LinkDetectInfo.bBusyTraffic;
-+}
-+
-+u8 rtw_mi_busy_traffic_check(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_busy_traffic_check);
-+}
-+u8 rtw_mi_buddy_busy_traffic_check(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_busy_traffic_check);
-+}
-+static u8 _rtw_mi_check_mlmeinfo_state(_adapter *padapter, void *data)
-+{
-+	u32 state = *(u32 *)data;
-+	struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;
-+
-+	/*if (mlmeext_msr(mlmeext) == state)*/
-+	if (check_mlmeinfo_state(mlmeext, state))
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+u8 rtw_mi_check_mlmeinfo_state(_adapter *padapter, u32 state)
-+{
-+	u32 in_data = state;
-+
-+	return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_check_mlmeinfo_state);
-+}
-+
-+u8 rtw_mi_buddy_check_mlmeinfo_state(_adapter *padapter, u32 state)
-+{
-+	u32 in_data = state;
-+
-+	return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_check_mlmeinfo_state);
-+}
-+
-+/*#define DBG_DUMP_FW_STATE*/
-+#ifdef DBG_DUMP_FW_STATE
-+static void rtw_dbg_dump_fwstate(_adapter *padapter, sint state)
-+{
-+	u8 buf[32] = {0};
-+
-+	if (state & WIFI_FW_NULL_STATE) {
-+		_rtw_memset(buf, 0, 32);
-+		sprintf(buf, "WIFI_FW_NULL_STATE");
-+		RTW_INFO(FUNC_ADPT_FMT"fwstate-%s\n", FUNC_ADPT_ARG(padapter), buf);
-+	}
-+
-+	if (state & WIFI_ASOC_STATE) {
-+		_rtw_memset(buf, 0, 32);
-+		sprintf(buf, "WIFI_ASOC_STATE");
-+		RTW_INFO(FUNC_ADPT_FMT"fwstate-%s\n", FUNC_ADPT_ARG(padapter), buf);
-+	}
-+
-+	if (state & WIFI_UNDER_LINKING) {
-+		_rtw_memset(buf, 0, 32);
-+		sprintf(buf, "WIFI_UNDER_LINKING");
-+		RTW_INFO(FUNC_ADPT_FMT"fwstate-%s\n", FUNC_ADPT_ARG(padapter), buf);
-+	}
-+
-+	if (state & WIFI_UNDER_SURVEY) {
-+		_rtw_memset(buf, 0, 32);
-+		sprintf(buf, "WIFI_UNDER_SURVEY");
-+		RTW_INFO(FUNC_ADPT_FMT"fwstate-%s\n", FUNC_ADPT_ARG(padapter), buf);
-+	}
-+}
-+#endif
-+
-+static u8 _rtw_mi_check_fwstate(_adapter *padapter, void *data)
-+{
-+	u8 ret = _FALSE;
-+
-+	sint state = *(sint *)data;
-+
-+	if ((state == WIFI_FW_NULL_STATE) &&
-+	    (padapter->mlmepriv.fw_state == WIFI_FW_NULL_STATE))
-+		ret = _TRUE;
-+	else if (_TRUE == check_fwstate(&padapter->mlmepriv, state))
-+		ret = _TRUE;
-+#ifdef DBG_DUMP_FW_STATE
-+	if (ret)
-+		rtw_dbg_dump_fwstate(padapter, state);
-+#endif
-+	return ret;
-+}
-+u8 rtw_mi_check_fwstate(_adapter *padapter, sint state)
-+{
-+	sint in_data = state;
-+
-+	return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_check_fwstate);
-+}
-+u8 rtw_mi_buddy_check_fwstate(_adapter *padapter, sint state)
-+{
-+	sint in_data = state;
-+
-+	return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_check_fwstate);
-+}
-+
-+static u8 _rtw_mi_traffic_statistics(_adapter *padapter , void *data)
-+{
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
-+
-+	/* Tx */
-+	pdvobjpriv->traffic_stat.tx_bytes += padapter->xmitpriv.tx_bytes;
-+	pdvobjpriv->traffic_stat.tx_pkts += padapter->xmitpriv.tx_pkts;
-+	pdvobjpriv->traffic_stat.tx_drop += padapter->xmitpriv.tx_drop;
-+
-+	/* Rx */
-+	pdvobjpriv->traffic_stat.rx_bytes += padapter->recvpriv.rx_bytes;
-+	pdvobjpriv->traffic_stat.rx_pkts += padapter->recvpriv.rx_pkts;
-+	pdvobjpriv->traffic_stat.rx_drop += padapter->recvpriv.rx_drop;
-+	return _TRUE;
-+}
-+u8 rtw_mi_traffic_statistics(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_traffic_statistics);
-+}
-+
-+static u8 _rtw_mi_check_miracast_enabled(_adapter *padapter , void *data)
-+{
-+	return is_miracast_enabled(padapter);
-+}
-+u8 rtw_mi_check_miracast_enabled(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_check_miracast_enabled);
-+}
-+
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+static u8 _rtw_mi_check_pending_xmitbuf(_adapter *padapter , void *data)
-+{
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+
-+	return check_pending_xmitbuf(pxmitpriv);
-+}
-+u8 rtw_mi_check_pending_xmitbuf(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_check_pending_xmitbuf);
-+}
-+u8 rtw_mi_buddy_check_pending_xmitbuf(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_check_pending_xmitbuf);
-+}
-+#endif
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+static u8 _rtw_mi_dequeue_writeport(_adapter *padapter , bool exclude_self)
-+{
-+	int i;
-+	u8	queue_empty = _TRUE;
-+	_adapter *iface;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if ((iface) && rtw_is_adapter_up(iface)) {
-+
-+			if ((exclude_self) && (iface == padapter))
-+				continue;
-+
-+			queue_empty &= _dequeue_writeport(iface);
-+		}
-+	}
-+	return queue_empty;
-+}
-+u8 rtw_mi_dequeue_writeport(_adapter *padapter)
-+{
-+	return _rtw_mi_dequeue_writeport(padapter, _FALSE);
-+}
-+u8 rtw_mi_buddy_dequeue_writeport(_adapter *padapter)
-+{
-+	return _rtw_mi_dequeue_writeport(padapter, _TRUE);
-+}
-+#endif
-+static void _rtw_mi_adapter_reset(_adapter *padapter , u8 exclude_self)
-+{
-+	int i;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		if (dvobj->padapters[i]) {
-+			if ((exclude_self) && (dvobj->padapters[i] == padapter))
-+				continue;
-+			dvobj->padapters[i] = NULL;
-+		}
-+	}
-+}
-+
-+void rtw_mi_adapter_reset(_adapter *padapter)
-+{
-+	_rtw_mi_adapter_reset(padapter, _FALSE);
-+}
-+
-+void rtw_mi_buddy_adapter_reset(_adapter *padapter)
-+{
-+	_rtw_mi_adapter_reset(padapter, _TRUE);
-+}
-+
-+static u8 _rtw_mi_dynamic_check_timer_handlder(_adapter *adapter, void *data)
-+{
-+	rtw_iface_dynamic_check_timer_handlder(adapter);
-+	return _TRUE;
-+}
-+u8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_dynamic_check_timer_handlder);
-+}
-+u8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_dynamic_check_timer_handlder);
-+}
-+
-+static u8 _rtw_mi_dynamic_chk_wk_hdl(_adapter *adapter, void *data)
-+{
-+	rtw_iface_dynamic_chk_wk_hdl(adapter);
-+	return _TRUE;
-+}
-+u8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_dynamic_chk_wk_hdl);
-+}
-+u8 rtw_mi_buddy_dynamic_chk_wk_hdl(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_dynamic_chk_wk_hdl);
-+}
-+
-+static u8 _rtw_mi_os_xmit_schedule(_adapter *adapter, void *data)
-+{
-+	rtw_os_xmit_schedule(adapter);
-+	return _TRUE;
-+}
-+u8 rtw_mi_os_xmit_schedule(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_os_xmit_schedule);
-+}
-+u8 rtw_mi_buddy_os_xmit_schedule(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_os_xmit_schedule);
-+}
-+
-+static u8 _rtw_mi_report_survey_event(_adapter *adapter, void *data)
-+{
-+	union recv_frame *precv_frame = (union recv_frame *)data;
-+
-+	report_survey_event(adapter, precv_frame);
-+	return _TRUE;
-+}
-+u8 rtw_mi_report_survey_event(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, precv_frame, _rtw_mi_report_survey_event);
-+}
-+u8 rtw_mi_buddy_report_survey_event(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, precv_frame, _rtw_mi_report_survey_event);
-+}
-+
-+static u8 _rtw_mi_sreset_adapter_hdl(_adapter *adapter, void *data)
-+{
-+	u8 bstart = *(u8 *)data;
-+
-+	if (bstart)
-+		sreset_start_adapter(adapter);
-+	else
-+		sreset_stop_adapter(adapter);
-+	return _TRUE;
-+}
-+u8 rtw_mi_sreset_adapter_hdl(_adapter *padapter, u8 bstart)
-+{
-+	u8 in_data = bstart;
-+
-+	return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_sreset_adapter_hdl);
-+}
-+
-+#if defined(CONFIG_AP_MODE) && defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE)
-+void rtw_mi_ap_info_restore(_adapter *adapter)
-+{
-+	int i;
-+	_adapter *iface;
-+	struct mlme_priv *pmlmepriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface) {
-+			pmlmepriv = &iface->mlmepriv;
-+
-+			if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {
-+				RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(iface), MLME_IS_AP(iface) ? "AP" : "MESH");
-+				rtw_iface_bcmc_sec_cam_map_restore(iface);
-+			}
-+		}
-+	}
-+}
-+#endif /*#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE)*/
-+
-+u8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart)
-+{
-+	u8 in_data = bstart;
-+
-+	return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_sreset_adapter_hdl);
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+static u8 _rtw_mi_tx_beacon_hdl(_adapter *adapter, void *data)
-+{
-+	if ((MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))
-+		&& check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE
-+	) {
-+		adapter->mlmepriv.update_bcn = _TRUE;
-+#ifndef CONFIG_INTERRUPT_BASED_TXBCN
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_PCI_BCN_POLLING)
-+		tx_beacon_hdl(adapter, NULL);
-+#endif
-+#endif
-+	}
-+	return _TRUE;
-+}
-+u8 rtw_mi_tx_beacon_hdl(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_tx_beacon_hdl);
-+}
-+u8 rtw_mi_buddy_tx_beacon_hdl(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_sreset_adapter_hdl);
-+}
-+
-+static u8 _rtw_mi_set_tx_beacon_cmd(_adapter *adapter, void *data)
-+{
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+
-+	if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
-+		if (pmlmepriv->update_bcn == _TRUE)
-+			set_tx_beacon_cmd(adapter, 0);
-+	}
-+	return _TRUE;
-+}
-+u8 rtw_mi_set_tx_beacon_cmd(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_set_tx_beacon_cmd);
-+}
-+u8 rtw_mi_buddy_set_tx_beacon_cmd(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_set_tx_beacon_cmd);
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+#ifdef CONFIG_P2P
-+static u8 _rtw_mi_p2p_chk_state(_adapter *adapter, void *data)
-+{
-+	struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
-+	enum P2P_STATE state = *(enum P2P_STATE *)data;
-+
-+	return rtw_p2p_chk_state(pwdinfo, state);
-+}
-+u8 rtw_mi_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state)
-+{
-+	u8 in_data = p2p_state;
-+
-+	return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_p2p_chk_state);
-+}
-+u8 rtw_mi_buddy_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state)
-+{
-+	u8 in_data  = p2p_state;
-+
-+	return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_p2p_chk_state);
-+}
-+static u8 _rtw_mi_stay_in_p2p_mode(_adapter *adapter, void *data)
-+{
-+	struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
-+
-+	if (rtw_p2p_role(pwdinfo) != P2P_ROLE_DISABLE)
-+		return _TRUE;
-+	return _FALSE;
-+}
-+u8 rtw_mi_stay_in_p2p_mode(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_stay_in_p2p_mode);
-+}
-+u8 rtw_mi_buddy_stay_in_p2p_mode(_adapter *padapter)
-+{
-+	return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_stay_in_p2p_mode);
-+}
-+#endif /*CONFIG_P2P*/
-+
-+_adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id)
-+{
-+	_adapter *iface = NULL;
-+	struct dvobj_priv *dvobj;
-+
-+	if ((padapter == NULL) || (iface_id >= CONFIG_IFACE_NUMBER)) {
-+		rtw_warn_on(1);
-+		return iface;
-+	}
-+
-+	dvobj = adapter_to_dvobj(padapter);
-+	return dvobj->padapters[iface_id];
-+}
-+
-+_adapter *rtw_get_iface_by_macddr(_adapter *padapter, const u8 *mac_addr)
-+{
-+	int i;
-+	_adapter *iface = NULL;
-+	u8 bmatch = _FALSE;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if ((iface) && (_rtw_memcmp(mac_addr, adapter_mac_addr(iface), ETH_ALEN))) {
-+			bmatch = _TRUE;
-+			break;
-+		}
-+	}
-+	if (bmatch)
-+		return iface;
-+	else
-+		return NULL;
-+}
-+
-+_adapter *rtw_get_iface_by_hwport(_adapter *padapter, u8 hw_port)
-+{
-+	int i;
-+	_adapter *iface = NULL;
-+	u8 bmatch = _FALSE;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if ((iface) && (hw_port == iface->hw_port)) {
-+			bmatch = _TRUE;
-+			break;
-+		}
-+	}
-+	if (bmatch)
-+		return iface;
-+	else
-+		return NULL;
-+}
-+
-+/*#define CONFIG_SKB_ALLOCATED*/
-+#define DBG_SKB_PROCESS
-+#ifdef DBG_SKB_PROCESS
-+void rtw_dbg_skb_process(_adapter *padapter, union recv_frame *precvframe, union recv_frame *pcloneframe)
-+{
-+	_pkt *pkt_copy, *pkt_org;
-+
-+	pkt_org = precvframe->u.hdr.pkt;
-+	pkt_copy = pcloneframe->u.hdr.pkt;
-+	/*
-+		RTW_INFO("%s ===== ORG SKB =====\n", __func__);
-+		RTW_INFO(" SKB head(%p)\n", pkt_org->head);
-+		RTW_INFO(" SKB data(%p)\n", pkt_org->data);
-+		RTW_INFO(" SKB tail(%p)\n", pkt_org->tail);
-+		RTW_INFO(" SKB end(%p)\n", pkt_org->end);
-+
-+		RTW_INFO(" recv frame head(%p)\n", precvframe->u.hdr.rx_head);
-+		RTW_INFO(" recv frame data(%p)\n", precvframe->u.hdr.rx_data);
-+		RTW_INFO(" recv frame tail(%p)\n", precvframe->u.hdr.rx_tail);
-+		RTW_INFO(" recv frame end(%p)\n", precvframe->u.hdr.rx_end);
-+
-+		RTW_INFO("%s ===== COPY SKB =====\n", __func__);
-+		RTW_INFO(" SKB head(%p)\n", pkt_copy->head);
-+		RTW_INFO(" SKB data(%p)\n", pkt_copy->data);
-+		RTW_INFO(" SKB tail(%p)\n", pkt_copy->tail);
-+		RTW_INFO(" SKB end(%p)\n", pkt_copy->end);
-+
-+		RTW_INFO(" recv frame head(%p)\n", pcloneframe->u.hdr.rx_head);
-+		RTW_INFO(" recv frame data(%p)\n", pcloneframe->u.hdr.rx_data);
-+		RTW_INFO(" recv frame tail(%p)\n", pcloneframe->u.hdr.rx_tail);
-+		RTW_INFO(" recv frame end(%p)\n", pcloneframe->u.hdr.rx_end);
-+	*/
-+	/*
-+		RTW_INFO("%s => recv_frame adapter(%p,%p)\n", __func__, precvframe->u.hdr.adapter, pcloneframe->u.hdr.adapter);
-+		RTW_INFO("%s => recv_frame dev(%p,%p)\n", __func__, pkt_org->dev , pkt_copy->dev);
-+		RTW_INFO("%s => recv_frame len(%d,%d)\n", __func__, precvframe->u.hdr.len, pcloneframe->u.hdr.len);
-+	*/
-+	if (precvframe->u.hdr.len != pcloneframe->u.hdr.len)
-+		RTW_INFO("%s [WARN]  recv_frame length(%d:%d) compare failed\n", __func__, precvframe->u.hdr.len, pcloneframe->u.hdr.len);
-+
-+	if (_rtw_memcmp(&precvframe->u.hdr.attrib, &pcloneframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib)) == _FALSE)
-+		RTW_INFO("%s [WARN]  recv_frame attrib compare failed\n", __func__);
-+
-+	if (_rtw_memcmp(precvframe->u.hdr.rx_data, pcloneframe->u.hdr.rx_data, precvframe->u.hdr.len) == _FALSE)
-+		RTW_INFO("%s [WARN]  recv_frame rx_data compare failed\n", __func__);
-+
-+}
-+#endif
-+
-+static s32 _rtw_mi_buddy_clone_bcmc_packet(_adapter *adapter, union recv_frame *precvframe, u8 *pphy_status, union recv_frame *pcloneframe)
-+{
-+	s32 ret = _SUCCESS;
-+#ifdef CONFIG_SKB_ALLOCATED
-+	u8 *pbuf = precvframe->u.hdr.rx_data;
-+#endif
-+	struct rx_pkt_attrib *pattrib = NULL;
-+
-+	if (pcloneframe) {
-+		pcloneframe->u.hdr.adapter = adapter;
-+
-+		_rtw_init_listhead(&pcloneframe->u.hdr.list);
-+		pcloneframe->u.hdr.precvbuf = NULL;	/*can't access the precvbuf for new arch.*/
-+		pcloneframe->u.hdr.len = 0;
-+
-+		_rtw_memcpy(&pcloneframe->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib));
-+
-+		pattrib = &pcloneframe->u.hdr.attrib;
-+#ifdef CONFIG_SKB_ALLOCATED
-+		if (rtw_os_alloc_recvframe(adapter, pcloneframe, pbuf, NULL) == _SUCCESS)
-+#else
-+		if (rtw_os_recvframe_duplicate_skb(adapter, pcloneframe, precvframe->u.hdr.pkt) == _SUCCESS)
-+#endif
-+		{
-+#ifdef CONFIG_SKB_ALLOCATED
-+			recvframe_put(pcloneframe, pattrib->pkt_len);
-+#endif
-+
-+#ifdef DBG_SKB_PROCESS
-+			rtw_dbg_skb_process(adapter, precvframe, pcloneframe);
-+#endif
-+
-+			if (pphy_status)
-+				rx_query_phy_status(pcloneframe, pphy_status);
-+
-+			ret = rtw_recv_entry(pcloneframe);
-+		} else {
-+			ret = -1;
-+			RTW_INFO("%s()-%d: rtw_os_alloc_recvframe() failed!\n", __func__, __LINE__);
-+		}
-+
-+	}
-+	return ret;
-+}
-+
-+void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe, u8 *pphy_status)
-+{
-+	int i;
-+	s32 ret = _SUCCESS;
-+	_adapter *iface = NULL;
-+	union recv_frame *pcloneframe = NULL;
-+	struct recv_priv *precvpriv = &padapter->recvpriv;/*primary_padapter*/
-+	_queue *pfree_recv_queue = &precvpriv->free_recv_queue;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	u8 *fhead = get_recvframe_data(precvframe);
-+	u8 type = GetFrameType(fhead);
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface || iface == padapter)
-+			continue;
-+		if (rtw_is_adapter_up(iface) == _FALSE || iface->registered == 0)
-+			continue;
-+		if (type == WIFI_DATA_TYPE && !adapter_allow_bmc_data_rx(iface))
-+			continue;
-+
-+		pcloneframe = rtw_alloc_recvframe(pfree_recv_queue);
-+		if (pcloneframe) {
-+			ret = _rtw_mi_buddy_clone_bcmc_packet(iface, precvframe, pphy_status, pcloneframe);
-+			if (_SUCCESS != ret) {
-+				if (ret == -1)
-+					rtw_free_recvframe(pcloneframe, pfree_recv_queue);
-+				/*RTW_INFO(ADPT_FMT"-clone BC/MC frame failed\n", ADPT_ARG(iface));*/
-+			}
-+		}
-+	}
-+
-+}
-+
-+#ifdef CONFIG_PCI_HCI
-+/*API be created temporary for MI, caller is interrupt-handler, PCIE's interrupt handler cannot apply to multi-AP*/
-+_adapter *rtw_mi_get_ap_adapter(_adapter *padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	int i;
-+	_adapter *iface = NULL;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+
-+		if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE
-+		    && check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+			break;
-+
-+	}
-+	return iface;
-+}
-+#endif
-+
-+u8 rtw_mi_get_ld_sta_ifbmp(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	int i;
-+	_adapter *iface = NULL;
-+	u8 ifbmp = 0;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+
-+		if (MLME_IS_STA(iface) && MLME_IS_ASOC(iface))
-+			ifbmp |= BIT(i);
-+	}
-+
-+	return ifbmp;
-+}
-+
-+u8 rtw_mi_get_ap_mesh_ifbmp(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	int i;
-+	_adapter *iface = NULL;
-+	u8 ifbmp = 0;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+
-+		if (CHK_MLME_STATE(iface, WIFI_AP_STATE | WIFI_MESH_STATE)
-+			&& MLME_IS_ASOC(iface))
-+			ifbmp |= BIT(i);
-+	}
-+
-+	return ifbmp;
-+}
-+
-+void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b)
-+{
-+#ifdef CONFIG_CONCURRENT_MODE
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+
-+	int i;
-+	_adapter *iface = NULL;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+
-+		if (macid_ctl->iface_bmc[iface->iface_id] != INVALID_SEC_MAC_CAM_ID) {
-+			if (macid_ctl->iface_bmc[iface->iface_id] == camid_a)
-+				macid_ctl->iface_bmc[iface->iface_id] = camid_b;
-+			else if (macid_ctl->iface_bmc[iface->iface_id] == camid_b)
-+				macid_ctl->iface_bmc[iface->iface_id] = camid_a;
-+			iface->securitypriv.dot118021x_bmc_cam_id  = macid_ctl->iface_bmc[iface->iface_id];
-+		}
-+	}
-+#endif
-+}
-+
-+u8 rtw_mi_get_assoc_if_num(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	u8 n_assoc_iface = 0;
-+#if 1
-+	u8 i;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		if (check_fwstate(&(dvobj->padapters[i]->mlmepriv), WIFI_ASOC_STATE))
-+			n_assoc_iface++;
-+	}
-+#else
-+	n_assoc_iface = DEV_STA_LD_NUM(dvobj) + DEV_AP_NUM(dvobj) + DEV_ADHOC_NUM(dvobj) + DEV_MESH_NUM(dvobj);
-+#endif
-+	return n_assoc_iface;
-+}
-diff --git a/drivers/staging/rtl8723cs/core/rtw_mlme.c b/drivers/staging/rtl8723cs/core/rtw_mlme.c
-new file mode 100644
-index 000000000000..3ab2fb5251eb
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_mlme.c
-@@ -0,0 +1,5955 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_MLME_C_
-+
-+#include <hal_data.h>
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+#include "../os_dep/linux/custom_multiap_intfs/custom_multiap_intfs.h"
-+#endif
-+
-+extern void indicate_wx_scan_complete_event(_adapter *padapter);
-+extern u8 rtw_do_join(_adapter *padapter);
-+
-+
-+void rtw_init_mlme_timer(_adapter *padapter)
-+{
-+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+	rtw_init_timer(&(pmlmepriv->assoc_timer), padapter, rtw_join_timeout_handler, padapter);
-+	rtw_init_timer(&(pmlmepriv->scan_to_timer), padapter, rtw_scan_timeout_handler, padapter);
-+
-+#ifdef CONFIG_SET_SCAN_DENY_TIMER
-+	rtw_init_timer(&(pmlmepriv->set_scan_deny_timer), padapter, rtw_set_scan_deny_timer_hdl, padapter);
-+#endif
-+
-+#ifdef RTK_DMP_PLATFORM
-+	_init_workitem(&(pmlmepriv->Linkup_workitem), Linkup_workitem_callback, padapter);
-+	_init_workitem(&(pmlmepriv->Linkdown_workitem), Linkdown_workitem_callback, padapter);
-+#endif
-+}
-+
-+sint	_rtw_init_mlme_priv(_adapter *padapter)
-+{
-+	sint	i;
-+	u8	*pbuf;
-+	struct wlan_network	*pnetwork;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	sint	res = _SUCCESS;
-+#ifdef CONFIG_RTW_MULTI_AP
-+	struct unassoc_sta_info *unassoc_sta;
-+#endif
-+
-+
-+	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
-+	/* _rtw_memset((u8 *)pmlmepriv, 0, sizeof(struct mlme_priv)); */
-+
-+
-+	/*qos_priv*/
-+	/*pmlmepriv->qospriv.qos_option = pregistrypriv->wmm_enable;*/
-+
-+	/*ht_priv*/
-+#ifdef CONFIG_80211N_HT
-+	pmlmepriv->htpriv.ampdu_enable = _FALSE;/*set to disabled*/
-+#endif
-+
-+	pmlmepriv->nic_hdl = (u8 *)padapter;
-+
-+	pmlmepriv->pscanned = NULL;
-+	init_fwstate(pmlmepriv, WIFI_STATION_STATE);
-+	pmlmepriv->cur_network.network.InfrastructureMode = Ndis802_11AutoUnknown;
-+	pmlmepriv->scan_mode = SCAN_ACTIVE; /* 1: active, 0: pasive. Maybe someday we should rename this varable to "active_mode" (Jeff) */
-+
-+	_rtw_spinlock_init(&(pmlmepriv->lock));
-+	_rtw_init_queue(&(pmlmepriv->free_bss_pool));
-+	_rtw_init_queue(&(pmlmepriv->scanned_queue));
-+
-+	set_scanned_network_val(pmlmepriv, 0);
-+
-+	_rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID));
-+
-+	if (padapter->registrypriv.max_bss_cnt != 0)
-+		pmlmepriv->max_bss_cnt = padapter->registrypriv.max_bss_cnt;
-+	else if (rfctl->max_chan_nums <= MAX_CHANNEL_NUM_2G)
-+		pmlmepriv->max_bss_cnt = MAX_BSS_CNT;
-+	else
-+		pmlmepriv->max_bss_cnt = MAX_BSS_CNT + MAX_BSS_CNT;
-+
-+
-+	pbuf = rtw_zvmalloc(pmlmepriv->max_bss_cnt * (sizeof(struct wlan_network)));
-+
-+	if (pbuf == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	pmlmepriv->free_bss_buf = pbuf;
-+
-+	pnetwork = (struct wlan_network *)pbuf;
-+
-+	for (i = 0; i < pmlmepriv->max_bss_cnt; i++) {
-+		_rtw_init_listhead(&(pnetwork->list));
-+
-+		rtw_list_insert_tail(&(pnetwork->list), &(pmlmepriv->free_bss_pool.queue));
-+
-+		pnetwork++;
-+	}
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+	if (is_primary_adapter(padapter)) {
-+		_rtw_init_queue(&(pmlmepriv->free_unassoc_sta_queue));
-+		_rtw_init_queue(&(pmlmepriv->unassoc_sta_queue));
-+		for (i = 0; i < UNASOC_STA_SRC_NUM; i++)
-+			pmlmepriv->unassoc_sta_mode_of_stype[i] = padapter->registrypriv.unassoc_sta_mode_of_stype[i];
-+		if (padapter->registrypriv.max_unassoc_sta_cnt != 0)
-+			pmlmepriv->max_unassoc_sta_cnt = padapter->registrypriv.max_unassoc_sta_cnt;
-+		else if (rfctl->max_chan_nums <= MAX_CHANNEL_NUM_2G)
-+			pmlmepriv->max_unassoc_sta_cnt = MAX_UNASSOC_STA_CNT;
-+		else
-+			pmlmepriv->max_unassoc_sta_cnt = MAX_UNASSOC_STA_CNT * 2;
-+		pbuf = rtw_zvmalloc(pmlmepriv->max_unassoc_sta_cnt * (sizeof(struct unassoc_sta_info)));
-+		if (pbuf == NULL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+		pmlmepriv->free_unassoc_sta_buf = pbuf;
-+		unassoc_sta = (struct unassoc_sta_info *) pbuf;
-+		for (i = 0; i < pmlmepriv->max_unassoc_sta_cnt; i++) {
-+			_rtw_init_listhead(&(unassoc_sta->list));
-+			rtw_list_insert_tail(&(unassoc_sta->list), &(pmlmepriv->free_unassoc_sta_queue.queue));
-+			unassoc_sta++;
-+		}
-+	}
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+	rtw_init_timer(&pmlmepriv->cmap_unassoc_sta_timer, padapter, cmap_unassoc_sta_report_info_timer, padapter);
-+#endif
-+#endif
-+	/* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */
-+
-+	rtw_clear_scan_deny(padapter);
-+#ifdef CONFIG_ARP_KEEP_ALIVE
-+	pmlmepriv->bGetGateway = 0;
-+	pmlmepriv->GetGatewayTryCnt = 0;
-+#endif
-+
-+#ifdef CONFIG_LAYER2_ROAMING
-+#define RTW_ROAM_SCAN_RESULT_EXP_MS (5*1000)
-+#define RTW_ROAM_RSSI_DIFF_TH 10
-+#define RTW_ROAM_SCAN_INTERVAL (5)    /* 5*(2 second)*/
-+#define RTW_ROAM_RSSI_THRESHOLD 70
-+	pmlmepriv->roam_flags = CONFIG_ROAMING_FLAG;
-+
-+	pmlmepriv->roam_scanr_exp_ms = RTW_ROAM_SCAN_RESULT_EXP_MS;
-+	pmlmepriv->roam_rssi_diff_th = RTW_ROAM_RSSI_DIFF_TH;
-+	pmlmepriv->roam_scan_int 	 = RTW_ROAM_SCAN_INTERVAL;
-+	pmlmepriv->roam_rssi_threshold = RTW_ROAM_RSSI_THRESHOLD;
-+	pmlmepriv->need_to_roam = _FALSE;
-+	pmlmepriv->last_roaming = rtw_get_current_time();
-+#endif /* CONFIG_LAYER2_ROAMING */
-+
-+#ifdef CONFIG_RTW_80211R
-+	rtw_ft_info_init(&pmlmepriv->ft_roam);
-+#endif
-+#ifdef CONFIG_LAYER2_ROAMING
-+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
-+	rtw_roam_nb_info_init(padapter);
-+	pmlmepriv->ch_cnt = 0;
-+#endif	
-+#endif
-+
-+	pmlmepriv->defs_lmt_sta = 2;
-+	pmlmepriv->defs_lmt_time = 5;
-+
-+	rtw_init_mlme_timer(padapter);
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+void rtw_mfree_mlme_priv_lock(struct mlme_priv *pmlmepriv);
-+void rtw_mfree_mlme_priv_lock(struct mlme_priv *pmlmepriv)
-+{
-+	_rtw_spinlock_free(&pmlmepriv->lock);
-+	_rtw_spinlock_free(&(pmlmepriv->free_bss_pool.lock));
-+	_rtw_spinlock_free(&(pmlmepriv->scanned_queue.lock));
-+#ifdef CONFIG_RTW_MULTI_AP
-+	if (is_primary_adapter(mlme_to_adapter(pmlmepriv))) {
-+		_rtw_spinlock_free(&(pmlmepriv->unassoc_sta_queue.lock));
-+		_rtw_spinlock_free(&(pmlmepriv->free_unassoc_sta_queue.lock));
-+	}
-+#endif
-+}
-+
-+void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv)
-+{
-+	rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len);
-+	rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len);
-+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
-+	rtw_buf_free(&pmlmepriv->wps_beacon_ie, &pmlmepriv->wps_beacon_ie_len);
-+	rtw_buf_free(&pmlmepriv->wps_probe_req_ie, &pmlmepriv->wps_probe_req_ie_len);
-+	rtw_buf_free(&pmlmepriv->wps_probe_resp_ie, &pmlmepriv->wps_probe_resp_ie_len);
-+	rtw_buf_free(&pmlmepriv->wps_assoc_resp_ie, &pmlmepriv->wps_assoc_resp_ie_len);
-+
-+	rtw_buf_free(&pmlmepriv->p2p_beacon_ie, &pmlmepriv->p2p_beacon_ie_len);
-+	rtw_buf_free(&pmlmepriv->p2p_probe_req_ie, &pmlmepriv->p2p_probe_req_ie_len);
-+	rtw_buf_free(&pmlmepriv->p2p_probe_resp_ie, &pmlmepriv->p2p_probe_resp_ie_len);
-+	rtw_buf_free(&pmlmepriv->p2p_go_probe_resp_ie, &pmlmepriv->p2p_go_probe_resp_ie_len);
-+	rtw_buf_free(&pmlmepriv->p2p_assoc_req_ie, &pmlmepriv->p2p_assoc_req_ie_len);
-+	rtw_buf_free(&pmlmepriv->p2p_assoc_resp_ie, &pmlmepriv->p2p_assoc_resp_ie_len);
-+#endif
-+
-+#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
-+	rtw_buf_free(&pmlmepriv->wfd_beacon_ie, &pmlmepriv->wfd_beacon_ie_len);
-+	rtw_buf_free(&pmlmepriv->wfd_probe_req_ie, &pmlmepriv->wfd_probe_req_ie_len);
-+	rtw_buf_free(&pmlmepriv->wfd_probe_resp_ie, &pmlmepriv->wfd_probe_resp_ie_len);
-+	rtw_buf_free(&pmlmepriv->wfd_go_probe_resp_ie, &pmlmepriv->wfd_go_probe_resp_ie_len);
-+	rtw_buf_free(&pmlmepriv->wfd_assoc_req_ie, &pmlmepriv->wfd_assoc_req_ie_len);
-+	rtw_buf_free(&pmlmepriv->wfd_assoc_resp_ie, &pmlmepriv->wfd_assoc_resp_ie_len);
-+#endif
-+
-+#ifdef CONFIG_RTW_80211R
-+	rtw_buf_free(&pmlmepriv->auth_rsp, &pmlmepriv->auth_rsp_len);
-+#endif
-+#ifdef CONFIG_RTW_MBO
-+	rtw_buf_free(&pmlmepriv->pcell_data_cap_ie, &pmlmepriv->cell_data_cap_len);
-+#endif
-+}
-+
-+#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
-+int rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_len)
-+{
-+	_adapter *adapter = mlme_to_adapter(mlme);
-+	struct wifi_display_info *wfd_info = &adapter->wfd_info;
-+	u8 clear = 0;
-+	u8 **t_ie = NULL;
-+	u32 *t_ie_len = NULL;
-+	int ret = _FAIL;
-+
-+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
-+		goto success;
-+
-+	if (wfd_info->wfd_enable == _TRUE)
-+		goto success; /* WFD IE is build by self */
-+
-+	if (!ie && !ie_len)
-+		clear = 1;
-+	else if (!ie || !ie_len) {
-+		RTW_PRINT(FUNC_ADPT_FMT" type:%u, ie:%p, ie_len:%u"
-+			  , FUNC_ADPT_ARG(adapter), type, ie, ie_len);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	switch (type) {
-+	case MLME_BEACON_IE:
-+		t_ie = &mlme->wfd_beacon_ie;
-+		t_ie_len = &mlme->wfd_beacon_ie_len;
-+		break;
-+	case MLME_PROBE_REQ_IE:
-+		t_ie = &mlme->wfd_probe_req_ie;
-+		t_ie_len = &mlme->wfd_probe_req_ie_len;
-+		break;
-+	case MLME_PROBE_RESP_IE:
-+		t_ie = &mlme->wfd_probe_resp_ie;
-+		t_ie_len = &mlme->wfd_probe_resp_ie_len;
-+		break;
-+	case MLME_GO_PROBE_RESP_IE:
-+		t_ie = &mlme->wfd_go_probe_resp_ie;
-+		t_ie_len = &mlme->wfd_go_probe_resp_ie_len;
-+		break;
-+	case MLME_ASSOC_REQ_IE:
-+		t_ie = &mlme->wfd_assoc_req_ie;
-+		t_ie_len = &mlme->wfd_assoc_req_ie_len;
-+		break;
-+	case MLME_ASSOC_RESP_IE:
-+		t_ie = &mlme->wfd_assoc_resp_ie;
-+		t_ie_len = &mlme->wfd_assoc_resp_ie_len;
-+		break;
-+	default:
-+		RTW_PRINT(FUNC_ADPT_FMT" unsupported type:%u"
-+			  , FUNC_ADPT_ARG(adapter), type);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (*t_ie) {
-+		u32 free_len = *t_ie_len;
-+		*t_ie_len = 0;
-+		rtw_mfree(*t_ie, free_len);
-+		*t_ie = NULL;
-+	}
-+
-+	if (!clear) {
-+		*t_ie = rtw_malloc(ie_len);
-+		if (*t_ie == NULL) {
-+			RTW_ERR(FUNC_ADPT_FMT" type:%u, rtw_malloc() fail\n"
-+				, FUNC_ADPT_ARG(adapter), type);
-+			goto exit;
-+		}
-+		_rtw_memcpy(*t_ie, ie, ie_len);
-+		*t_ie_len = ie_len;
-+	}
-+
-+	if (*t_ie && *t_ie_len) {
-+		u8 *attr_content;
-+		u32 attr_contentlen = 0;
-+
-+		attr_content = rtw_get_wfd_attr_content(*t_ie, *t_ie_len, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen);
-+		if (attr_content && attr_contentlen) {
-+			if (RTW_GET_BE16(attr_content + 2) != wfd_info->rtsp_ctrlport) {
-+				wfd_info->rtsp_ctrlport = RTW_GET_BE16(attr_content + 2);
-+				RTW_INFO(FUNC_ADPT_FMT" type:%u, RTSP CTRL port = %u\n"
-+					, FUNC_ADPT_ARG(adapter), type, wfd_info->rtsp_ctrlport);
-+			}
-+		}
-+	}
-+
-+success:
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+#endif /* defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) */
-+
-+void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv)
-+{
-+	_adapter *adapter = mlme_to_adapter(pmlmepriv);
-+	if (NULL == pmlmepriv) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+	rtw_free_mlme_priv_ie_data(pmlmepriv);
-+
-+	if (pmlmepriv) {
-+		rtw_mfree_mlme_priv_lock(pmlmepriv);
-+
-+		if (pmlmepriv->free_bss_buf)
-+			rtw_vmfree(pmlmepriv->free_bss_buf, pmlmepriv->max_bss_cnt * sizeof(struct wlan_network));
-+#ifdef CONFIG_RTW_MULTI_AP
-+		if (is_primary_adapter(adapter)) {
-+			if (pmlmepriv->free_unassoc_sta_buf)
-+				rtw_vmfree(pmlmepriv->free_unassoc_sta_buf, pmlmepriv->max_unassoc_sta_cnt * sizeof(struct unassoc_sta_info));
-+		}
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+		_cancel_timer_ex(&pmlmepriv->cmap_unassoc_sta_timer);
-+#endif
-+#endif
-+	}
-+exit:
-+	return;
-+}
-+
-+sint	_rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork)
-+{
-+	_irqL irqL;
-+
-+
-+	if (pnetwork == NULL)
-+		goto exit;
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+
-+	rtw_list_insert_tail(&pnetwork->list, &queue->queue);
-+
-+	_exit_critical_bh(&queue->lock, &irqL);
-+
-+exit:
-+
-+
-+	return _SUCCESS;
-+}
-+
-+/*
-+struct	wlan_network *_rtw_dequeue_network(_queue *queue)
-+{
-+	_irqL irqL;
-+
-+	struct wlan_network *pnetwork;
-+
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+
-+	if (_rtw_queue_empty(queue) == _TRUE)
-+
-+		pnetwork = NULL;
-+
-+	else
-+	{
-+		pnetwork = LIST_CONTAINOR(get_next(&queue->queue), struct wlan_network, list);
-+
-+		rtw_list_delete(&(pnetwork->list));
-+	}
-+
-+	_exit_critical_bh(&queue->lock, &irqL);
-+
-+
-+	return pnetwork;
-+}
-+*/
-+
-+struct	wlan_network *_rtw_alloc_network(struct	mlme_priv *pmlmepriv) /* (_queue *free_queue) */
-+{
-+	_irqL	irqL;
-+	struct	wlan_network	*pnetwork;
-+	_queue *free_queue = &pmlmepriv->free_bss_pool;
-+	_list *plist = NULL;
-+
-+
-+	_enter_critical_bh(&free_queue->lock, &irqL);
-+
-+	if (_rtw_queue_empty(free_queue) == _TRUE) {
-+		pnetwork = NULL;
-+		goto exit;
-+	}
-+	plist = get_next(&(free_queue->queue));
-+
-+	pnetwork = LIST_CONTAINOR(plist , struct wlan_network, list);
-+
-+	rtw_list_delete(&pnetwork->list);
-+
-+	pnetwork->network_type = 0;
-+	pnetwork->fixed = _FALSE;
-+	pnetwork->last_scanned = rtw_get_current_time();
-+	pnetwork->last_non_hidden_ssid_ap = pnetwork->last_scanned;
-+#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
-+	pnetwork->acnode_stime = 0;
-+	pnetwork->acnode_notify_etime = 0;
-+#endif
-+
-+	pnetwork->aid = 0;
-+	pnetwork->join_res = 0;
-+
-+	pmlmepriv->num_of_scanned++;
-+
-+exit:
-+	_exit_critical_bh(&free_queue->lock, &irqL);
-+
-+
-+	return pnetwork;
-+}
-+
-+void _rtw_free_network(struct	mlme_priv *pmlmepriv , struct wlan_network *pnetwork, u8 isfreeall)
-+{
-+	u32 delta_time;
-+	u32 lifetime = SCANQUEUE_LIFETIME;
-+	_irqL irqL;
-+	_queue *free_queue = &(pmlmepriv->free_bss_pool);
-+
-+
-+	if (pnetwork == NULL)
-+		goto exit;
-+
-+	if (pnetwork->fixed == _TRUE)
-+		goto exit;
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
-+	    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
-+		lifetime = 1;
-+
-+	if (!isfreeall) {
-+		delta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned);
-+		if (delta_time < lifetime) /* unit:msec */
-+			goto exit;
-+	}
-+
-+	_enter_critical_bh(&free_queue->lock, &irqL);
-+
-+	rtw_list_delete(&(pnetwork->list));
-+
-+	rtw_list_insert_tail(&(pnetwork->list), &(free_queue->queue));
-+
-+	pmlmepriv->num_of_scanned--;
-+
-+
-+	/* RTW_INFO("_rtw_free_network:SSID=%s\n", pnetwork->network.Ssid.Ssid); */
-+
-+	_exit_critical_bh(&free_queue->lock, &irqL);
-+
-+exit:
-+	return;
-+}
-+
-+void _rtw_free_network_nolock(struct	mlme_priv *pmlmepriv, struct wlan_network *pnetwork)
-+{
-+
-+	_queue *free_queue = &(pmlmepriv->free_bss_pool);
-+
-+
-+	if (pnetwork == NULL)
-+		goto exit;
-+
-+	if (pnetwork->fixed == _TRUE)
-+		goto exit;
-+
-+	/* _enter_critical(&free_queue->lock, &irqL); */
-+
-+	rtw_list_delete(&(pnetwork->list));
-+
-+	rtw_list_insert_tail(&(pnetwork->list), get_list_head(free_queue));
-+
-+	pmlmepriv->num_of_scanned--;
-+
-+	/* _exit_critical(&free_queue->lock, &irqL); */
-+
-+exit:
-+	return;
-+}
-+
-+void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall)
-+{
-+	_irqL irqL;
-+	_list *phead, *plist;
-+	struct wlan_network *pnetwork;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	_queue *scanned_queue = &pmlmepriv->scanned_queue;
-+
-+
-+
-+	_enter_critical_bh(&scanned_queue->lock, &irqL);
-+
-+	phead = get_list_head(scanned_queue);
-+	plist = get_next(phead);
-+
-+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+
-+		plist = get_next(plist);
-+
-+		_rtw_free_network(pmlmepriv, pnetwork, isfreeall);
-+
-+	}
-+
-+	_exit_critical_bh(&scanned_queue->lock, &irqL);
-+
-+
-+}
-+
-+
-+
-+
-+sint rtw_if_up(_adapter *padapter)
-+{
-+
-+	sint res;
-+
-+	if (RTW_CANNOT_RUN(padapter) ||
-+	    (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE)) {
-+		res = _FALSE;
-+	} else
-+		res =  _TRUE;
-+
-+	return res;
-+}
-+
-+
-+void rtw_generate_random_ibss(u8 *pibss)
-+{
-+	*((u32 *)(&pibss[2])) = rtw_random32();
-+	pibss[0] = 0x02; /* in ad-hoc mode local bit must set to 1 */
-+	pibss[1] = 0x11;
-+	pibss[2] = 0x87;
-+}
-+
-+u8 *rtw_get_capability_from_ie(u8 *ie)
-+{
-+	return ie + 8 + 2;
-+}
-+
-+
-+u16 rtw_get_capability(WLAN_BSSID_EX *bss)
-+{
-+	u16	val;
-+
-+	_rtw_memcpy((u8 *)&val, rtw_get_capability_from_ie(bss->IEs), 2);
-+
-+	return le16_to_cpu(val);
-+}
-+
-+u8 *rtw_get_timestampe_from_ie(u8 *ie)
-+{
-+	return ie + 0;
-+}
-+
-+u8 *rtw_get_beacon_interval_from_ie(u8 *ie)
-+{
-+	return ie + 8;
-+}
-+
-+
-+int	rtw_init_mlme_priv(_adapter *padapter) /* (struct	mlme_priv *pmlmepriv) */
-+{
-+	int	res;
-+	res = _rtw_init_mlme_priv(padapter);/* (pmlmepriv); */
-+	return res;
-+}
-+
-+void rtw_free_mlme_priv(struct mlme_priv *pmlmepriv)
-+{
-+	_rtw_free_mlme_priv(pmlmepriv);
-+}
-+
-+int	rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork);
-+int	rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork)
-+{
-+	int	res;
-+	res = _rtw_enqueue_network(queue, pnetwork);
-+	return res;
-+}
-+
-+/*
-+static struct	wlan_network *rtw_dequeue_network(_queue *queue)
-+{
-+	struct wlan_network *pnetwork;
-+	pnetwork = _rtw_dequeue_network(queue);
-+	return pnetwork;
-+}
-+*/
-+
-+struct	wlan_network *rtw_alloc_network(struct	mlme_priv *pmlmepriv);
-+struct	wlan_network *rtw_alloc_network(struct	mlme_priv *pmlmepriv) /* (_queue	*free_queue) */
-+{
-+	struct	wlan_network	*pnetwork;
-+	pnetwork = _rtw_alloc_network(pmlmepriv);
-+	return pnetwork;
-+}
-+
-+void rtw_free_network(struct mlme_priv *pmlmepriv, struct	wlan_network *pnetwork, u8 is_freeall);
-+void rtw_free_network(struct mlme_priv *pmlmepriv, struct	wlan_network *pnetwork, u8 is_freeall)/* (struct	wlan_network *pnetwork, _queue	*free_queue) */
-+{
-+	_rtw_free_network(pmlmepriv, pnetwork, is_freeall);
-+}
-+
-+void rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork);
-+void rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork)
-+{
-+	_rtw_free_network_nolock(&(padapter->mlmepriv), pnetwork);
-+#ifdef CONFIG_IOCTL_CFG80211
-+	rtw_cfg80211_unlink_bss(padapter, pnetwork);
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+}
-+
-+
-+void rtw_free_network_queue(_adapter *dev, u8 isfreeall)
-+{
-+	_rtw_free_network_queue(dev, isfreeall);
-+}
-+
-+struct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr)
-+{
-+	_list	*phead, *plist;
-+	struct	wlan_network *pnetwork = NULL;
-+	u8 zero_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
-+
-+	if (_rtw_memcmp(zero_addr, addr, ETH_ALEN)) {
-+		pnetwork = NULL;
-+		goto exit;
-+	}
-+
-+	phead = get_list_head(scanned_queue);
-+	plist = get_next(phead);
-+
-+	while (plist != phead) {
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network , list);
-+
-+		if (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE)
-+			break;
-+
-+		plist = get_next(plist);
-+	}
-+
-+	if (plist == phead)
-+		pnetwork = NULL;
-+
-+exit:
-+	return pnetwork;
-+}
-+
-+struct wlan_network *rtw_find_network(_queue *scanned_queue, const u8 *addr)
-+{
-+	struct	wlan_network *pnetwork;
-+	_irqL irqL;
-+
-+	 _enter_critical_bh(&scanned_queue->lock, &irqL);
-+	pnetwork = _rtw_find_network(scanned_queue, addr);
-+	_exit_critical_bh(&scanned_queue->lock, &irqL);
-+
-+	return pnetwork;
-+}
-+
-+int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork)
-+{
-+	int ret = _TRUE;
-+	struct security_priv *psecuritypriv = &adapter->securitypriv;
-+
-+	if ((psecuritypriv->dot11PrivacyAlgrthm != _NO_PRIVACY_) &&
-+	    (pnetwork->network.Privacy == 0))
-+		ret = _FALSE;
-+	else if ((psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_) &&
-+		 (pnetwork->network.Privacy == 1))
-+		ret = _FALSE;
-+	else
-+		ret = _TRUE;
-+
-+	return ret;
-+
-+}
-+
-+inline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b)
-+{
-+	return (a->Ssid.SsidLength == b->Ssid.SsidLength)
-+	       &&  _rtw_memcmp(a->Ssid.Ssid, b->Ssid.Ssid, a->Ssid.SsidLength) == _TRUE;
-+}
-+
-+int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature)
-+{
-+	u16 s_cap, d_cap;
-+
-+
-+	if (rtw_bug_check(dst, src, &s_cap, &d_cap) == _FALSE)
-+		return _FALSE;
-+
-+	_rtw_memcpy((u8 *)&s_cap, rtw_get_capability_from_ie(src->IEs), 2);
-+	_rtw_memcpy((u8 *)&d_cap, rtw_get_capability_from_ie(dst->IEs), 2);
-+
-+
-+	s_cap = le16_to_cpu(s_cap);
-+	d_cap = le16_to_cpu(d_cap);
-+
-+
-+#ifdef CONFIG_P2P
-+	if ((feature == 1) && /* 1: P2P supported */
-+	    (_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN) == _TRUE)
-+	   )
-+		return _TRUE;
-+#endif
-+
-+	/* Wi-Fi driver doesn't consider the situation of BCN and ProbRsp sent from the same hidden AP, 
-+	  * it considers these two packets are sent from different AP. 
-+	  * Therefore, the scan queue may store two scan results of the same hidden AP, likes below.
-+	  *
-+	  *  index            bssid              ch    RSSI   SdBm  Noise   age          flag             ssid
-+	  *    1    00:e0:4c:55:50:01    153   -73     -73        0     7044   [WPS][ESS]     RTK5G
-+	  *    3    00:e0:4c:55:50:01    153   -73     -73        0     7044   [WPS][ESS]
-+	  *
-+	  * Original rules will compare Ssid, SsidLength, MacAddress, s_cap, d_cap at the same time.
-+	  * Wi-Fi driver will assume that the BCN and ProbRsp sent from the same hidden AP are the same network
-+	  * after we add an additional rule to compare SsidLength and Ssid.
-+	  * It means the scan queue will not store two scan results of the same hidden AP, it only store ProbRsp.
-+	  * For customer request.
-+	  */
-+	  
-+	if (((_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) &&
-+		((s_cap & WLAN_CAPABILITY_IBSS) == (d_cap & WLAN_CAPABILITY_IBSS)) &&
-+		((s_cap & WLAN_CAPABILITY_BSS) == (d_cap & WLAN_CAPABILITY_BSS))) {
-+		if ((src->Ssid.SsidLength == dst->Ssid.SsidLength) && 
-+			(((_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) || //Case of normal AP
-+			(is_all_null(src->Ssid.Ssid, src->Ssid.SsidLength) == _TRUE || is_all_null(dst->Ssid.Ssid, dst->Ssid.SsidLength) == _TRUE))) //Case of hidden AP
-+			return _TRUE;
-+		else if ((src->Ssid.SsidLength == 0 || dst->Ssid.SsidLength == 0)) //Case of hidden AP
-+			return _TRUE;
-+		else
-+			return _FALSE;
-+	} else {
-+		return _FALSE;
-+	}
-+}
-+
-+struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network)
-+{
-+	_list *phead, *plist;
-+	struct wlan_network *found = NULL;
-+
-+	phead = get_list_head(scanned_queue);
-+	plist = get_next(phead);
-+
-+	while (plist != phead) {
-+		found = LIST_CONTAINOR(plist, struct wlan_network , list);
-+
-+		if (is_same_network(&network->network, &found->network, 0))
-+			break;
-+
-+		plist = get_next(plist);
-+	}
-+
-+	if (plist == phead)
-+		found = NULL;
-+
-+	return found;
-+}
-+
-+struct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network)
-+{
-+	_irqL irqL;
-+	struct wlan_network *found = NULL;
-+
-+	if (scanned_queue == NULL || network == NULL)
-+		goto exit;
-+
-+	_enter_critical_bh(&scanned_queue->lock, &irqL);
-+	found = _rtw_find_same_network(scanned_queue, network);
-+	_exit_critical_bh(&scanned_queue->lock, &irqL);
-+
-+exit:
-+	return found;
-+}
-+
-+struct	wlan_network	*rtw_get_oldest_wlan_network(_queue *scanned_queue)
-+{
-+	_list	*plist, *phead;
-+
-+
-+	struct	wlan_network	*pwlan = NULL;
-+	struct	wlan_network	*oldest = NULL;
-+	phead = get_list_head(scanned_queue);
-+
-+	plist = get_next(phead);
-+
-+	while (1) {
-+
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pwlan = LIST_CONTAINOR(plist, struct wlan_network, list);
-+
-+		if (pwlan->fixed != _TRUE) {
-+			if (oldest == NULL || rtw_time_after(oldest->last_scanned, pwlan->last_scanned))
-+				oldest = pwlan;
-+		}
-+
-+		plist = get_next(plist);
-+	}
-+	return oldest;
-+
-+}
-+
-+void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src,
-+		    _adapter *padapter, bool update_ie)
-+{
-+#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1
-+	u8 ss_ori = dst->PhyInfo.SignalStrength;
-+	u8 sq_ori = dst->PhyInfo.SignalQuality;
-+	u8 ss_smp = src->PhyInfo.SignalStrength;
-+	long rssi_smp = src->Rssi;
-+#endif
-+	long rssi_ori = dst->Rssi;
-+
-+	u8 sq_smp = src->PhyInfo.SignalQuality;
-+	u8 ss_final;
-+	u8 sq_final;
-+	long rssi_final;
-+
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	rtw_hal_antdiv_rssi_compared(padapter, dst, src); /* this will update src.Rssi, need consider again */
-+#endif
-+
-+#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1
-+	if (strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {
-+		RTW_INFO(FUNC_ADPT_FMT" %s("MAC_FMT", ch%u) ss_ori:%3u, sq_ori:%3u, rssi_ori:%3ld, ss_smp:%3u, sq_smp:%3u, rssi_smp:%3ld\n"
-+			 , FUNC_ADPT_ARG(padapter)
-+			, src->Ssid.Ssid, MAC_ARG(src->MacAddress), src->Configuration.DSConfig
-+			 , ss_ori, sq_ori, rssi_ori
-+			 , ss_smp, sq_smp, rssi_smp
-+			);
-+	}
-+#endif
-+
-+	/* The rule below is 1/5 for sample value, 4/5 for history value */
-+	if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) && is_same_network(&(padapter->mlmepriv.cur_network.network), src, 0)) {
-+		/* Take the recvpriv's value for the connected AP*/
-+		ss_final = padapter->recvpriv.signal_strength;
-+		sq_final = padapter->recvpriv.signal_qual;
-+		/* the rssi value here is undecorated, and will be used for antenna diversity */
-+		if (sq_smp != 101) /* from the right channel */
-+			rssi_final = (src->Rssi + dst->Rssi * 4) / 5;
-+		else
-+			rssi_final = rssi_ori;
-+	} else {
-+		if (sq_smp != 101) { /* from the right channel */
-+			ss_final = ((u32)(src->PhyInfo.SignalStrength) + (u32)(dst->PhyInfo.SignalStrength) * 4) / 5;
-+			sq_final = ((u32)(src->PhyInfo.SignalQuality) + (u32)(dst->PhyInfo.SignalQuality) * 4) / 5;
-+			rssi_final = (src->Rssi + dst->Rssi * 4) / 5;
-+		} else {
-+			/* bss info not receving from the right channel, use the original RX signal infos */
-+			ss_final = dst->PhyInfo.SignalStrength;
-+			sq_final = dst->PhyInfo.SignalQuality;
-+			rssi_final = dst->Rssi;
-+		}
-+
-+	}
-+
-+	if (update_ie) {
-+		dst->Reserved[0] = src->Reserved[0];
-+		dst->Reserved[1] = src->Reserved[1];
-+		_rtw_memcpy((u8 *)dst, (u8 *)src, get_WLAN_BSSID_EX_sz(src));
-+	}
-+
-+	dst->PhyInfo.SignalStrength = ss_final;
-+	dst->PhyInfo.SignalQuality = sq_final;
-+	dst->Rssi = rssi_final;
-+
-+#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1
-+	if (strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {
-+		RTW_INFO(FUNC_ADPT_FMT" %s("MAC_FMT"), SignalStrength:%u, SignalQuality:%u, RawRSSI:%ld\n"
-+			 , FUNC_ADPT_ARG(padapter)
-+			, dst->Ssid.Ssid, MAC_ARG(dst->MacAddress), dst->PhyInfo.SignalStrength, dst->PhyInfo.SignalQuality, dst->Rssi);
-+	}
-+#endif
-+
-+#if 0 /* old codes, may be useful one day...
-+ * 	RTW_INFO("update_network: rssi=0x%lx dst->Rssi=%d ,dst->Rssi=0x%lx , src->Rssi=0x%lx",(dst->Rssi+src->Rssi)/2,dst->Rssi,dst->Rssi,src->Rssi); */
-+	if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) && is_same_network(&(padapter->mlmepriv.cur_network.network), src)) {
-+
-+		/* RTW_INFO("b:ssid=%s update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Ssid.Ssid,src->Rssi,padapter->recvpriv.signal); */
-+		if (padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) {
-+			padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;
-+			last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];
-+			padapter->recvpriv.signal_qual_data.total_val -= last_evm;
-+		}
-+		padapter->recvpriv.signal_qual_data.total_val += query_rx_pwr_percentage(src->Rssi);
-+
-+		padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = query_rx_pwr_percentage(src->Rssi);
-+		if (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)
-+			padapter->recvpriv.signal_qual_data.index = 0;
-+
-+		/* RTW_INFO("Total SQ=%d  pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, src->Rssi); */
-+
-+		/* <1> Showed on UI for user,in percentage. */
-+		tmpVal = padapter->recvpriv.signal_qual_data.total_val / padapter->recvpriv.signal_qual_data.total_num;
-+		padapter->recvpriv.signal = (u8)tmpVal; /* Link quality */
-+
-+		src->Rssi = translate_percentage_to_dbm(padapter->recvpriv.signal) ;
-+	} else {
-+		/*	RTW_INFO("ELSE:ssid=%s update_network: src->rssi=0x%d dst->rssi=%d\n",src->Ssid.Ssid,src->Rssi,dst->Rssi); */
-+		src->Rssi = (src->Rssi + dst->Rssi) / 2; /* dBM */
-+	}
-+
-+	/*	RTW_INFO("a:update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Rssi,padapter->recvpriv.signal); */
-+
-+#endif
-+
-+}
-+
-+static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)
-+{
-+	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
-+
-+
-+	rtw_bug_check(&(pmlmepriv->cur_network.network),
-+		      &(pmlmepriv->cur_network.network),
-+		      &(pmlmepriv->cur_network.network),
-+		      &(pmlmepriv->cur_network.network));
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) && (is_same_network(&(pmlmepriv->cur_network.network), pnetwork, 0))) {
-+
-+		/* if(pmlmepriv->cur_network.network.IELength<= pnetwork->IELength) */
-+		{
-+			update_network(&(pmlmepriv->cur_network.network), pnetwork, adapter, _TRUE);
-+			rtw_update_protection(adapter, (pmlmepriv->cur_network.network.IEs) + sizeof(NDIS_802_11_FIXED_IEs),
-+				      pmlmepriv->cur_network.network.IELength);
-+		}
-+	}
-+
-+
-+}
-+
-+
-+/*
-+
-+Caller must hold pmlmepriv->lock first.
-+
-+
-+*/
-+bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target)
-+{
-+	_irqL irqL;
-+	_list	*plist, *phead;
-+	u32	bssid_ex_sz;
-+	struct mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
-+#endif /* CONFIG_P2P */
-+	_queue	*queue	= &(pmlmepriv->scanned_queue);
-+	struct wlan_network	*pnetwork = NULL;
-+	struct wlan_network	*choice = NULL;
-+	int target_find = 0;
-+	u8 feature = 0;
-+	bool update_ie = _FALSE;
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+#if 0
-+	RTW_INFO("%s => ssid:%s , rssi:%ld , ss:%d\n",
-+		__func__, target->Ssid.Ssid, target->Rssi, target->PhyInfo.SignalStrength);
-+#endif
-+
-+#ifdef CONFIG_P2P
-+	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
-+		feature = 1; /* p2p enable */
-+#endif
-+
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+
-+		rtw_bug_check(pnetwork, pnetwork, pnetwork, pnetwork);
-+
-+#ifdef CONFIG_P2P
-+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) &&
-+		    (_rtw_memcmp(pnetwork->network.MacAddress, target->MacAddress, ETH_ALEN) == _TRUE)) {
-+			target_find = 1;
-+			break;
-+		}
-+#endif
-+
-+		if (is_same_network(&(pnetwork->network), target, feature)) {
-+			target_find = 1;
-+			break;
-+		}
-+
-+		if (rtw_roam_flags(adapter)) {
-+			/* TODO: don't  select netowrk in the same ess as choice if it's new enough*/
-+		}
-+		if (pnetwork->fixed) {
-+			plist = get_next(plist);
-+			continue;
-+		}
-+			
-+#ifdef CONFIG_RSSI_PRIORITY
-+		if ((choice == NULL) || (pnetwork->network.PhyInfo.SignalStrength < choice->network.PhyInfo.SignalStrength))
-+			#ifdef CONFIG_RTW_MESH
-+			if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter)
-+				|| !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network))
-+			#endif
-+				choice = pnetwork;
-+#else
-+		if (choice == NULL || rtw_time_after(choice->last_scanned, pnetwork->last_scanned))
-+			#ifdef CONFIG_RTW_MESH
-+			if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter)
-+				|| !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network))
-+			#endif
-+				choice = pnetwork;
-+#endif
-+		plist = get_next(plist);
-+
-+	}
-+
-+
-+	/* If we didn't find a match, then get a new network slot to initialize
-+	 * with this beacon's information */
-+	/* if (rtw_end_of_queue_search(phead,plist)== _TRUE) { */
-+	if (!target_find) {
-+		if (_rtw_queue_empty(&(pmlmepriv->free_bss_pool)) == _TRUE) {
-+			/* If there are no more slots, expire the choice */
-+			/* list_del_init(&choice->list); */
-+			pnetwork = choice;
-+			if (pnetwork == NULL)
-+				goto unlock_scan_queue;
-+
-+#ifdef CONFIG_RSSI_PRIORITY
-+		RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT"  will be deleted from scanned_queue (rssi:%ld , ss:%d)\n",
-+			__func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Rssi, pnetwork->network.PhyInfo.SignalStrength);
-+#else
-+		RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue\n",
-+			__func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress));
-+#endif
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+			rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(target->PhyInfo.Optimum_antenna), NULL);
-+#endif
-+			_rtw_memcpy(&(pnetwork->network), target,  get_WLAN_BSSID_EX_sz(target));
-+			pnetwork->bcn_keys_valid = 0;
-+			if (target->Reserved[0] == BSS_TYPE_BCN || target->Reserved[0] == BSS_TYPE_PROB_RSP)
-+				rtw_update_bcn_keys_of_network(pnetwork);
-+			/* variable initialize */
-+			pnetwork->fixed = _FALSE;
-+			pnetwork->last_scanned = rtw_get_current_time();
-+			pnetwork->last_non_hidden_ssid_ap = pnetwork->last_scanned;
-+			#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
-+			pnetwork->acnode_stime = 0;
-+			pnetwork->acnode_notify_etime = 0;
-+			#endif
-+
-+			pnetwork->network_type = 0;
-+			pnetwork->aid = 0;
-+			pnetwork->join_res = 0;
-+
-+			/* bss info not receving from the right channel */
-+			if (pnetwork->network.PhyInfo.SignalQuality == 101)
-+				pnetwork->network.PhyInfo.SignalQuality = 0;
-+		} else {
-+			/* Otherwise just pull from the free list */
-+
-+			pnetwork = rtw_alloc_network(pmlmepriv); /* will update scan_time */
-+			if (pnetwork == NULL)
-+				goto unlock_scan_queue;
-+
-+			bssid_ex_sz = get_WLAN_BSSID_EX_sz(target);
-+			target->Length = bssid_ex_sz;
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+			rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(target->PhyInfo.Optimum_antenna), NULL);
-+#endif
-+			_rtw_memcpy(&(pnetwork->network), target, bssid_ex_sz);
-+			pnetwork->bcn_keys_valid = 0;
-+			if (target->Reserved[0] == BSS_TYPE_BCN || target->Reserved[0] == BSS_TYPE_PROB_RSP)
-+				rtw_update_bcn_keys_of_network(pnetwork);
-+
-+			/* bss info not receving from the right channel */
-+			if (pnetwork->network.PhyInfo.SignalQuality == 101)
-+				pnetwork->network.PhyInfo.SignalQuality = 0;
-+
-+			rtw_list_insert_tail(&(pnetwork->list), &(queue->queue));
-+
-+		}
-+	} else {
-+		/* we have an entry and we are going to update it. But this entry may
-+		 * be already expired. In this case we do the same as we found a new
-+		 * net and call the new_net handler
-+		 */
-+		#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
-+		systime last_scanned = pnetwork->last_scanned;
-+		#endif
-+		struct beacon_keys bcn_keys;
-+		bool bcn_keys_valid = 0;
-+		bool is_hidden_ssid_ap = 0;
-+
-+		pnetwork->last_scanned = rtw_get_current_time();
-+
-+		if (target->Reserved[0] == BSS_TYPE_BCN || target->Reserved[0] == BSS_TYPE_PROB_RSP) {
-+			if (target->InfrastructureMode == Ndis802_11Infrastructure) {
-+				is_hidden_ssid_ap = hidden_ssid_ap(target);
-+				if (!is_hidden_ssid_ap) /* update last time it's non hidden ssid AP */
-+					pnetwork->last_non_hidden_ssid_ap = rtw_get_current_time();
-+			}
-+			bcn_keys_valid = rtw_get_bcn_keys_from_bss(target, &bcn_keys);
-+		}
-+
-+		if (target->InfrastructureMode == Ndis802_11_mesh
-+			|| target->Reserved[0] >= pnetwork->network.Reserved[0])
-+			update_ie = _TRUE;
-+		else if (target->InfrastructureMode == Ndis802_11Infrastructure && !pnetwork->fixed
-+			&& rtw_get_passing_time_ms(pnetwork->last_non_hidden_ssid_ap) > SCANQUEUE_LIFETIME)
-+			update_ie = _TRUE;
-+		else if (bcn_keys_valid) {
-+			if (is_hidden_ssid(bcn_keys.ssid, bcn_keys.ssid_len)) {
-+				/* hidden ssid, replace with current beacon ssid directly */
-+				_rtw_memcpy(bcn_keys.ssid, pnetwork->bcn_keys.ssid, pnetwork->bcn_keys.ssid_len);
-+				bcn_keys.ssid_len = pnetwork->bcn_keys.ssid_len;
-+			}
-+			if (rtw_bcn_key_compare(&pnetwork->bcn_keys, &bcn_keys) == _FALSE)
-+				update_ie = _TRUE;
-+		}
-+
-+		#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
-+		if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter)
-+			|| pnetwork->network.Configuration.DSConfig != target->Configuration.DSConfig
-+			|| rtw_get_passing_time_ms(last_scanned) > adapter->mesh_cfg.peer_sel_policy.scanr_exp_ms
-+			|| !rtw_bss_is_same_mbss(&pnetwork->network, target)
-+		) {
-+			pnetwork->acnode_stime = 0;
-+			pnetwork->acnode_notify_etime = 0;
-+		}
-+		#endif
-+
-+		if (bcn_keys_valid) {
-+			_rtw_memcpy(&pnetwork->bcn_keys, &bcn_keys, sizeof(bcn_keys));
-+			pnetwork->bcn_keys_valid = 1;
-+		} else if (update_ie)
-+			pnetwork->bcn_keys_valid = 0;
-+
-+		update_network(&(pnetwork->network), target, adapter, update_ie);
-+	}
-+
-+	#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT
-+	if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))
-+		rtw_mesh_update_scanned_acnode_status(adapter, pnetwork);
-+	#endif
-+
-+unlock_scan_queue:
-+	_exit_critical_bh(&queue->lock, &irqL);
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (pnetwork && MLME_IS_MESH(adapter)
-+		&& check_fwstate(pmlmepriv, WIFI_ASOC_STATE)
-+		&& !check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)
-+	)
-+		rtw_chk_candidate_peer_notify(adapter, pnetwork);
-+#endif
-+
-+	return update_ie;
-+}
-+
-+void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork);
-+void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)
-+{
-+	bool update_ie;
-+	/* _queue	*queue	= &(pmlmepriv->scanned_queue); */
-+
-+	/* _enter_critical_bh(&queue->lock, &irqL); */
-+
-+#if defined(CONFIG_P2P) && defined(CONFIG_P2P_REMOVE_GROUP_INFO)
-+	if (adapter->registrypriv.wifi_spec == 0)
-+		rtw_bss_ex_del_p2p_attr(pnetwork, P2P_ATTR_GROUP_INFO);
-+#endif
-+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
-+		rtw_bss_ex_del_wfd_ie(pnetwork);
-+	/* Wi-Fi driver will update the current network if the scan result of the connected AP be updated by scan. */
-+	update_ie = rtw_update_scanned_network(adapter, pnetwork);
-+
-+	if (update_ie)
-+		update_current_network(adapter, pnetwork);
-+
-+	/* _exit_critical_bh(&queue->lock, &irqL); */
-+
-+}
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+void rtw_unassoc_sta_set_mode(_adapter *adapter, u8 stype, u8 mode)
-+{
-+	if (stype >= UNASOC_STA_SRC_NUM
-+		|| mode >= UNASOC_STA_MODE_NUM)
-+		return;
-+
-+	adapter = GET_PRIMARY_ADAPTER(adapter);
-+
-+	if (adapter->mlmepriv.unassoc_sta_mode_of_stype[stype] == mode)
-+		return;
-+		
-+	adapter->mlmepriv.unassoc_sta_mode_of_stype[stype] = mode;
-+
-+	rtw_run_in_thread_cmd_wait(adapter, ((void *)(rtw_hal_rcr_set_chk_bssid_act_non)), adapter, 2000);
-+}
-+
-+bool rtw_unassoc_sta_src_chk(_adapter *adapter, u8 stype)
-+{
-+	if (stype >= UNASOC_STA_SRC_NUM)
-+		return 0;
-+
-+	adapter = GET_PRIMARY_ADAPTER(adapter);
-+
-+	return adapter->mlmepriv.unassoc_sta_mode_of_stype[stype] == UNASOC_STA_MODE_ALL
-+		|| (adapter->mlmepriv.unassoc_sta_mode_of_stype[stype] == UNASOC_STA_MODE_INTERESTED
-+			&& adapter->mlmepriv.interested_unassoc_sta_cnt)
-+		;
-+}
-+
-+const char *unasoc_sta_src_str[] = {
-+	"BMC",
-+	"NMY_UC",
-+};
-+
-+const char *unasoc_sta_mode_str[] = {
-+	"DISABLED",
-+	"INTERESTED",
-+	"ALL",
-+};
-+
-+void dump_unassoc_sta(void *sel, _adapter *adapter)
-+{
-+	struct mlme_priv *mlmepriv;
-+	_queue *queue;
-+	_list *list, *head;
-+	struct unassoc_sta_info **unassoc_sta_arr;
-+	struct unassoc_sta_info *unassoc_sta;
-+	u16 i, unassoc_sta_cnt = 0;
-+
-+	adapter = GET_PRIMARY_ADAPTER(adapter);
-+	mlmepriv = &(adapter->mlmepriv);
-+	queue = &(mlmepriv->unassoc_sta_queue);
-+
-+	for (i = 0; i < UNASOC_STA_SRC_NUM; i++) {
-+		RTW_PRINT_SEL(sel, "[%u]%-6s:%u(%s)\n", i, unasoc_sta_src_str[i]
-+			, mlmepriv->unassoc_sta_mode_of_stype[i], unasoc_sta_mode_str[mlmepriv->unassoc_sta_mode_of_stype[i]]);
-+	}
-+	RTW_PRINT_SEL(sel, "interested_unassoc_sta_cnt:%u\n", mlmepriv->interested_unassoc_sta_cnt);
-+
-+	unassoc_sta_arr = rtw_zvmalloc(mlmepriv->max_unassoc_sta_cnt * sizeof(struct unassoc_sta_info *));
-+	if (!unassoc_sta_arr)
-+		return;
-+
-+	enter_critical_bh(&queue->lock);
-+	head = get_list_head(queue);
-+	list = get_next(head);
-+
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		unassoc_sta = LIST_CONTAINOR(list, struct unassoc_sta_info, list);
-+		list = get_next(list);
-+
-+		unassoc_sta_arr[unassoc_sta_cnt++] = unassoc_sta;
-+	}
-+
-+	exit_critical_bh(&queue->lock);
-+
-+	RTW_PRINT_SEL(sel, "  %17s %18s %6s\n", "mac_addr", "measure_delta_time", "rssi");
-+
-+	for (i = 0; i < unassoc_sta_cnt; i++) {
-+		u8 rcpi;
-+		s8 rx_power;
-+		u32 measure_delta_time;
-+
-+		unassoc_sta = unassoc_sta_arr[i];
-+
-+		measure_delta_time = rtw_systime_to_ms(rtw_get_current_time() - unassoc_sta->time);
-+
-+		RTW_PRINT_SEL(sel, "%c "MAC_FMT" %18u %6d\n"
-+			, unassoc_sta->interested ? '*' : ' '
-+			, MAC_ARG(unassoc_sta->addr), measure_delta_time, unassoc_sta->recv_signal_power);
-+	}
-+
-+	rtw_vmfree(unassoc_sta_arr, mlmepriv->max_unassoc_sta_cnt * sizeof(struct unassoc_sta_info *));
-+}
-+
-+static void del_unassoc_sta(struct mlme_priv *mlmepriv, struct unassoc_sta_info *unassoc_sta)
-+{
-+	_irqL irqL;
-+	_queue *free_queue = &(mlmepriv->free_unassoc_sta_queue);
-+
-+	if (unassoc_sta->interested)
-+		mlmepriv->interested_unassoc_sta_cnt--;
-+	if (mlmepriv->interested_unassoc_sta_cnt == 0) {
-+		rtw_run_in_thread_cmd(mlme_to_adapter(mlmepriv)
-+			, ((void *)(rtw_hal_rcr_set_chk_bssid_act_non)), mlme_to_adapter(mlmepriv));
-+	}
-+
-+	_enter_critical_bh(&free_queue->lock, &irqL);
-+	rtw_list_delete(&(unassoc_sta->list));
-+	rtw_list_insert_tail(&(unassoc_sta->list), &(free_queue->queue));
-+	_exit_critical_bh(&free_queue->lock, &irqL);
-+}
-+
-+static u8 del_unassoc_sta_chk(struct mlme_priv *mlmepriv, struct unassoc_sta_info *unassoc_sta)
-+{
-+	systime cur, lifetime;
-+
-+	if (unassoc_sta == NULL)
-+		return UNASOC_STA_DEL_CHK_SKIP;
-+
-+	if (unassoc_sta->interested)
-+		return UNASOC_STA_DEL_CHK_SKIP;
-+
-+	cur = rtw_get_current_time();
-+	lifetime = unassoc_sta->time + rtw_ms_to_systime(UNASSOC_STA_LIFETIME_MS);
-+	if (rtw_time_before(cur, lifetime))
-+		return UNASOC_STA_DEL_CHK_ALIVE;
-+
-+	del_unassoc_sta(mlmepriv, unassoc_sta);
-+
-+	return UNASOC_STA_DEL_CHK_DELETED;
-+}
-+
-+static struct unassoc_sta_info *alloc_unassoc_sta(struct mlme_priv *mlmepriv)
-+{
-+	_irqL	irqL;
-+	struct	unassoc_sta_info *unassoc_sta;
-+	_queue *free_queue = &mlmepriv->free_unassoc_sta_queue;
-+	_list *list = NULL;
-+
-+
-+	_enter_critical_bh(&free_queue->lock, &irqL);
-+
-+	if (_rtw_queue_empty(free_queue) == _TRUE) {
-+		unassoc_sta = NULL;
-+		goto exit;
-+	}
-+	list = get_next(&(free_queue->queue));
-+
-+	unassoc_sta = LIST_CONTAINOR(list, struct unassoc_sta_info, list);
-+
-+	rtw_list_delete(&unassoc_sta->list);
-+
-+	_rtw_memset(unassoc_sta->addr, 0, ETH_ALEN);
-+	unassoc_sta->recv_signal_power = 0;
-+	unassoc_sta->time = 0;
-+	unassoc_sta->interested = 0;
-+exit:
-+	_exit_critical_bh(&free_queue->lock, &irqL);
-+
-+	return unassoc_sta;
-+
-+}
-+
-+void rtw_del_unassoc_sta_queue(_adapter *adapter)
-+{
-+	struct unassoc_sta_info *unassoc_sta;
-+	struct mlme_priv *mlmepriv;
-+	_queue *queue;
-+	_irqL irqL;
-+	_list *head, *list;
-+
-+	adapter = GET_PRIMARY_ADAPTER(adapter);
-+	mlmepriv = &(adapter->mlmepriv);
-+	queue = &(mlmepriv->unassoc_sta_queue);
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+	head = get_list_head(queue);
-+	list = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
-+		unassoc_sta = LIST_CONTAINOR(list , struct unassoc_sta_info, list);
-+		list = get_next(list);
-+
-+		del_unassoc_sta(mlmepriv, unassoc_sta);
-+	}
-+
-+	_exit_critical_bh(&queue->lock, &irqL);
-+
-+}
-+
-+void rtw_del_unassoc_sta(_adapter *adapter, u8 *addr)
-+{
-+	struct unassoc_sta_info *unassoc_sta;
-+	struct mlme_priv *mlmepriv;
-+	_queue *queue;
-+	_irqL irqL;
-+	_list *head, *list;
-+
-+	adapter = GET_PRIMARY_ADAPTER(adapter);
-+	mlmepriv = &(adapter->mlmepriv);
-+	queue = &(mlmepriv->unassoc_sta_queue);
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+	head = get_list_head(queue);
-+	list = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
-+		unassoc_sta = LIST_CONTAINOR(list , struct unassoc_sta_info, list);
-+		list = get_next(list);
-+
-+		if (_rtw_memcmp(addr, unassoc_sta->addr, ETH_ALEN) == _TRUE) {
-+			del_unassoc_sta(mlmepriv, unassoc_sta);
-+			goto unlock_unassoc_sta_queue;
-+		}
-+	}
-+
-+unlock_unassoc_sta_queue:
-+	_exit_critical_bh(&queue->lock, &irqL);
-+}
-+
-+void rtw_rx_add_unassoc_sta(_adapter *adapter, u8 stype, u8 *addr, s8 recv_signal_power)
-+{
-+	struct unassoc_sta_info *unassoc_sta;
-+	struct unassoc_sta_info *oldest_unassoc_sta = NULL;
-+	struct mlme_priv *mlmepriv;
-+	_queue *queue;
-+	_irqL irqL;
-+	_list *head, *list;
-+
-+	adapter = GET_PRIMARY_ADAPTER(adapter);
-+	mlmepriv = &(adapter->mlmepriv);
-+	queue = &(mlmepriv->unassoc_sta_queue);
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+	head = get_list_head(queue);
-+	list = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
-+		unassoc_sta = LIST_CONTAINOR(list , struct unassoc_sta_info, list);
-+		list = get_next(list);
-+
-+		if (_rtw_memcmp(addr, unassoc_sta->addr, ETH_ALEN) == _TRUE) {
-+			if (unassoc_sta->interested
-+				|| mlmepriv->unassoc_sta_mode_of_stype[stype] >= UNASOC_STA_MODE_ALL
-+			) {
-+				unassoc_sta->recv_signal_power = recv_signal_power;
-+				unassoc_sta->time = rtw_get_current_time();
-+				goto unlock_unassoc_sta_queue;
-+			}
-+		}
-+
-+		if (del_unassoc_sta_chk(mlmepriv, unassoc_sta) == UNASOC_STA_DEL_CHK_ALIVE) {
-+			if (oldest_unassoc_sta == NULL)
-+				oldest_unassoc_sta = unassoc_sta;
-+			else if (rtw_time_before(unassoc_sta->time, oldest_unassoc_sta->time))
-+				oldest_unassoc_sta = unassoc_sta;
-+		}
-+	}
-+
-+	if (mlmepriv->unassoc_sta_mode_of_stype[stype] <= UNASOC_STA_MODE_INTERESTED)
-+		goto unlock_unassoc_sta_queue;
-+
-+	unassoc_sta = alloc_unassoc_sta(mlmepriv);
-+	if (unassoc_sta == NULL) {
-+		if (oldest_unassoc_sta) {
-+			del_unassoc_sta(mlmepriv, oldest_unassoc_sta);
-+			unassoc_sta = alloc_unassoc_sta(mlmepriv);
-+		} else
-+			goto unlock_unassoc_sta_queue;
-+	}
-+	_rtw_memcpy(unassoc_sta->addr, addr, ETH_ALEN);
-+	unassoc_sta->recv_signal_power = recv_signal_power;
-+	unassoc_sta->time = rtw_get_current_time();
-+	rtw_list_insert_tail(&(unassoc_sta->list), &(queue->queue));
-+
-+unlock_unassoc_sta_queue:
-+	_exit_critical_bh(&queue->lock, &irqL);
-+}
-+
-+void rtw_add_interested_unassoc_sta(_adapter *adapter, u8 *addr)
-+{
-+	struct unassoc_sta_info *unassoc_sta;
-+	struct unassoc_sta_info *oldest_unassoc_sta = NULL;
-+	struct mlme_priv *mlmepriv;
-+	_queue *queue;
-+	_irqL irqL;
-+	_list *head, *list;
-+
-+	adapter = GET_PRIMARY_ADAPTER(adapter);
-+	mlmepriv = &(adapter->mlmepriv);
-+	queue = &(mlmepriv->unassoc_sta_queue);
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+	head = get_list_head(queue);
-+	list = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
-+		unassoc_sta = LIST_CONTAINOR(list , struct unassoc_sta_info, list);
-+		list = get_next(list);
-+
-+		if (_rtw_memcmp(addr, unassoc_sta->addr, ETH_ALEN) == _TRUE) {
-+			if (!unassoc_sta->interested) {
-+				unassoc_sta->interested = 1;
-+				mlmepriv->interested_unassoc_sta_cnt++;
-+				if (mlmepriv->interested_unassoc_sta_cnt == 1) {
-+					rtw_run_in_thread_cmd(mlme_to_adapter(mlmepriv)
-+						, ((void *)(rtw_hal_rcr_set_chk_bssid_act_non)), mlme_to_adapter(mlmepriv));
-+				}
-+			}
-+			goto unlock_unassoc_sta_queue;
-+		}
-+
-+		if (del_unassoc_sta_chk(mlmepriv, unassoc_sta) == UNASOC_STA_DEL_CHK_ALIVE) {
-+			if (oldest_unassoc_sta == NULL)
-+				oldest_unassoc_sta = unassoc_sta;
-+			else if (rtw_time_after(unassoc_sta->time, oldest_unassoc_sta->time))
-+				oldest_unassoc_sta = unassoc_sta;
-+		}
-+	}
-+	unassoc_sta = alloc_unassoc_sta(mlmepriv);
-+	if (unassoc_sta == NULL) {
-+		RTW_INFO(FUNC_ADPT_FMT": Allocate fail\n", FUNC_ADPT_ARG(adapter));
-+		if (oldest_unassoc_sta) {
-+			RTW_INFO(FUNC_ADPT_FMT": Delete oldest entry and try again.\n", FUNC_ADPT_ARG(adapter));
-+			del_unassoc_sta(mlmepriv, oldest_unassoc_sta);
-+			unassoc_sta = alloc_unassoc_sta(mlmepriv);
-+		} else
-+			goto unlock_unassoc_sta_queue;
-+	}
-+	_rtw_memcpy(unassoc_sta->addr, addr, ETH_ALEN);
-+	unassoc_sta->interested = 1;
-+	unassoc_sta->recv_signal_power = 0;
-+	unassoc_sta->time = rtw_get_current_time() - rtw_ms_to_systime(UNASSOC_STA_LIFETIME_MS);
-+	rtw_list_insert_tail(&(unassoc_sta->list), &(queue->queue));
-+	mlmepriv->interested_unassoc_sta_cnt++;
-+	if (mlmepriv->interested_unassoc_sta_cnt == 1) {
-+		rtw_run_in_thread_cmd(mlme_to_adapter(mlmepriv)
-+			, ((void *)(rtw_hal_rcr_set_chk_bssid_act_non)), mlme_to_adapter(mlmepriv));
-+	}
-+
-+unlock_unassoc_sta_queue:
-+	_exit_critical_bh(&queue->lock, &irqL);
-+}
-+
-+void rtw_undo_interested_unassoc_sta(_adapter *adapter, u8 *addr)
-+{
-+	struct unassoc_sta_info *unassoc_sta;
-+	struct mlme_priv *mlmepriv;
-+	_queue *queue;
-+	_irqL irqL;
-+	_list *head, *list;
-+
-+	adapter = GET_PRIMARY_ADAPTER(adapter);
-+	mlmepriv = &(adapter->mlmepriv);
-+	queue = &(mlmepriv->unassoc_sta_queue);
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+	head = get_list_head(queue);
-+	list = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
-+		unassoc_sta = LIST_CONTAINOR(list , struct unassoc_sta_info, list);
-+		list = get_next(list);
-+
-+		if (_rtw_memcmp(addr, unassoc_sta->addr, ETH_ALEN) == _TRUE) {
-+			if (unassoc_sta->interested) {
-+				unassoc_sta->interested = 0;
-+				mlmepriv->interested_unassoc_sta_cnt--;
-+				if (mlmepriv->interested_unassoc_sta_cnt == 0) {
-+					rtw_run_in_thread_cmd(mlme_to_adapter(mlmepriv)
-+						, ((void *)(rtw_hal_rcr_set_chk_bssid_act_non)), mlme_to_adapter(mlmepriv));
-+				}
-+			}
-+			goto unlock_unassoc_sta_queue;
-+		}
-+	}
-+unlock_unassoc_sta_queue:
-+	_exit_critical_bh(&queue->lock, &irqL);
-+}
-+
-+void rtw_undo_all_interested_unassoc_sta(_adapter *adapter)
-+{
-+	struct unassoc_sta_info *unassoc_sta;
-+	struct mlme_priv *mlmepriv;
-+	_queue *queue;
-+	_irqL irqL;
-+	_list *head, *list;
-+
-+	adapter = GET_PRIMARY_ADAPTER(adapter);
-+	mlmepriv = &(adapter->mlmepriv);
-+	queue = &(mlmepriv->unassoc_sta_queue);
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+	head = get_list_head(queue);
-+	list = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
-+		unassoc_sta = LIST_CONTAINOR(list , struct unassoc_sta_info, list);
-+		list = get_next(list);
-+
-+		if (unassoc_sta->interested) {
-+			unassoc_sta->interested = 0;
-+			mlmepriv->interested_unassoc_sta_cnt--;
-+			if (mlmepriv->interested_unassoc_sta_cnt == 0) {
-+				rtw_run_in_thread_cmd(mlme_to_adapter(mlmepriv)
-+					, ((void *)(rtw_hal_rcr_set_chk_bssid_act_non)), mlme_to_adapter(mlmepriv));
-+				goto unlock_unassoc_sta_queue;
-+			}
-+		}
-+	}
-+unlock_unassoc_sta_queue:
-+	_exit_critical_bh(&queue->lock, &irqL);
-+}
-+
-+u8 rtw_search_unassoc_sta(_adapter *adapter, u8 *addr, struct unassoc_sta_info *ret_sta)
-+{
-+	struct unassoc_sta_info *unassoc_sta = NULL;
-+	struct mlme_priv *mlmepriv;
-+	_queue *queue;
-+	_irqL irqL;
-+	_list *head, *list;
-+	u8 searched = 0;
-+
-+	adapter = GET_PRIMARY_ADAPTER(adapter);
-+	mlmepriv = &(adapter->mlmepriv);
-+	queue = &(mlmepriv->unassoc_sta_queue);
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+	head = get_list_head(queue);
-+	list = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
-+		unassoc_sta = LIST_CONTAINOR(list , struct unassoc_sta_info, list);
-+		list = get_next(list);
-+
-+		if (_rtw_memcmp(addr, unassoc_sta->addr, ETH_ALEN) == _TRUE) {
-+			memcpy(ret_sta, unassoc_sta, sizeof(struct unassoc_sta_info));
-+			searched = 1;
-+			break;
-+		}
-+	}
-+	_exit_critical_bh(&queue->lock, &irqL);
-+
-+	return searched;
-+}
-+#endif /* CONFIG_RTW_MULTI_AP */
-+
-+/* select the desired network based on the capability of the (i)bss.
-+ * check items: (1) security
-+ *			   (2) network_type
-+ *			   (3) WMM
-+ *			   (4) HT
-+ * (5) others */
-+int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork);
-+int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork)
-+{
-+	struct security_priv *psecuritypriv = &adapter->securitypriv;
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	u32 desired_encmode;
-+	u32 privacy;
-+
-+	/* u8 wps_ie[512]; */
-+	uint wps_ielen;
-+
-+	int bselected = _TRUE;
-+
-+	desired_encmode = psecuritypriv->ndisencryptstatus;
-+	privacy = pnetwork->network.Privacy;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
-+		if (rtw_get_wps_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, pnetwork->network.IELength - _FIXED_IE_LENGTH_, NULL, &wps_ielen) != NULL)
-+			return _TRUE;
-+		else
-+			return _FALSE;
-+	}
-+	if (adapter->registrypriv.wifi_spec == 1) { /* for  correct flow of 8021X  to do.... */
-+		u8 *p = NULL;
-+		uint ie_len = 0;
-+
-+		if ((desired_encmode == Ndis802_11EncryptionDisabled) && (privacy != 0))
-+			bselected = _FALSE;
-+
-+		if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {
-+			p = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_));
-+			if (p && ie_len > 0)
-+				bselected = _TRUE;
-+			else
-+				bselected = _FALSE;
-+		}
-+	}
-+
-+
-+	if ((desired_encmode != Ndis802_11EncryptionDisabled) && (privacy == 0)) {
-+		RTW_INFO("desired_encmode: %d, privacy: %d\n", desired_encmode, privacy);
-+		bselected = _FALSE;
-+	}
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
-+		if (pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode)
-+			bselected = _FALSE;
-+	}
-+
-+#ifdef CONFIG_RTW_MBO
-+	if (rtw_mbo_disallowed_network(pnetwork) == _TRUE)
-+		bselected = _FALSE;
-+#endif
-+
-+	return bselected;
-+}
-+
-+#ifdef CONFIG_80211D
-+static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	struct registry_priv *pregistrypriv;
-+	struct mlme_ext_priv *pmlmeext;
-+	RT_CHANNEL_INFO *chplan_new;
-+	u8 channel;
-+	u8 i;
-+
-+
-+	pregistrypriv = &padapter->registrypriv;
-+	pmlmeext = &padapter->mlmeextpriv;
-+
-+	/* Adjust channel plan by AP Country IE */
-+	if (pregistrypriv->enable80211d
-+	    && (!pmlmeext->update_channel_plan_by_ap_done)) {
-+		u8 *ie, *p;
-+		u32 len;
-+		RT_CHANNEL_PLAN chplan_ap;
-+		RT_CHANNEL_INFO *chplan_sta = NULL;
-+		u8 country[4];
-+		u8 fcn; /* first channel number */
-+		u8 noc; /* number of channel */
-+		u8 j, k;
-+
-+		ie = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _COUNTRY_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_);
-+		if (!ie)
-+			return;
-+		if (len < 6)
-+			return;
-+
-+		ie += 2;
-+		p = ie;
-+		ie += len;
-+
-+		_rtw_memset(country, 0, 4);
-+		_rtw_memcpy(country, p, 3);
-+		p += 3;
-+		RTW_INFO("%s: 802.11d country=%s\n", __FUNCTION__, country);
-+
-+		i = 0;
-+		while ((ie - p) >= 3) {
-+			fcn = *(p++);
-+			noc = *(p++);
-+			p++;
-+
-+			for (j = 0; j < noc; j++) {
-+				if (fcn <= 14)
-+					channel = fcn + j; /* 2.4 GHz */
-+				else
-+					channel = fcn + j * 4; /* 5 GHz */
-+
-+				chplan_ap.Channel[i++] = channel;
-+			}
-+		}
-+		chplan_ap.Len = i;
-+
-+#ifdef CONFIG_RTW_DEBUG
-+		i = 0;
-+		RTW_INFO("%s: AP[%s] channel plan {", __FUNCTION__, bssid->Ssid.Ssid);
-+		while ((i < chplan_ap.Len) && (chplan_ap.Channel[i] != 0)) {
-+			_RTW_INFO("%02d,", chplan_ap.Channel[i]);
-+			i++;
-+		}
-+		_RTW_INFO("}\n");
-+#endif
-+
-+		chplan_sta = rtw_malloc(sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
-+		if (!chplan_sta)
-+			goto done_update_chplan_from_ap;
-+
-+		_rtw_memcpy(chplan_sta, rfctl->channel_set, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
-+#ifdef CONFIG_RTW_DEBUG
-+		i = 0;
-+		RTW_INFO("%s: STA channel plan {", __FUNCTION__);
-+		while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) {
-+			_RTW_INFO("%02d(%c),", chplan_sta[i].ChannelNum, chplan_sta[i].flags & RTW_CHF_NO_IR ? 'p' : 'a');
-+			i++;
-+		}
-+		_RTW_INFO("}\n");
-+#endif
-+
-+		_rtw_memset(rfctl->channel_set, 0, sizeof(rfctl->channel_set));
-+		chplan_new = rfctl->channel_set;
-+
-+		i = j = k = 0;
-+		if (pregistrypriv->wireless_mode & WIRELESS_11G) {
-+			do {
-+				if ((i == MAX_CHANNEL_NUM)
-+				    || (chplan_sta[i].ChannelNum == 0)
-+				    || (chplan_sta[i].ChannelNum > 14))
-+					break;
-+
-+				if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] > 14))
-+					break;
-+
-+				if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) {
-+					chplan_new[k].ChannelNum = chplan_ap.Channel[j];
-+					i++;
-+					j++;
-+					k++;
-+				} else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) {
-+					chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
-+#if 0
-+					if (chplan_sta[i].flags & RTW_CHF_NO_IR)
-+						chplan_new[k].flags |= RTW_CHF_NO_IR;
-+#else
-+					chplan_new[k].flags |= RTW_CHF_NO_IR;
-+#endif
-+					i++;
-+					k++;
-+				} else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) {
-+					chplan_new[k].ChannelNum = chplan_ap.Channel[j];
-+					j++;
-+					k++;
-+				}
-+			} while (1);
-+
-+			/* change AP not support channel to Passive scan */
-+			while ((i < MAX_CHANNEL_NUM)
-+			       && (chplan_sta[i].ChannelNum != 0)
-+			       && (chplan_sta[i].ChannelNum <= 14)) {
-+				chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
-+#if 0
-+				if (chplan_sta[i].flags & RTW_CHF_NO_IR)
-+					chplan_new[k].flags |= RTW_CHF_NO_IR;
-+#else
-+				chplan_new[k].flags |= RTW_CHF_NO_IR;
-+#endif
-+				i++;
-+				k++;
-+			}
-+
-+			/* add channel AP supported */
-+			while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14)) {
-+				chplan_new[k].ChannelNum = chplan_ap.Channel[j];
-+				j++;
-+				k++;
-+			}
-+		} else {
-+			/* keep original STA 2.4G channel plan */
-+			while ((i < MAX_CHANNEL_NUM)
-+			       && (chplan_sta[i].ChannelNum != 0)
-+			       && (chplan_sta[i].ChannelNum <= 14)) {
-+				chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
-+				if (chplan_sta[i].flags & RTW_CHF_NO_IR)
-+					chplan_new[k].flags |= RTW_CHF_NO_IR;
-+				i++;
-+				k++;
-+			}
-+
-+			/* skip AP 2.4G channel plan */
-+			while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14))
-+				j++;
-+		}
-+
-+		if (pregistrypriv->wireless_mode & WIRELESS_11A) {
-+			do {
-+				if ((i >= MAX_CHANNEL_NUM)
-+				    || (chplan_sta[i].ChannelNum == 0))
-+					break;
-+
-+				if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] == 0))
-+					break;
-+
-+				if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) {
-+					chplan_new[k].ChannelNum = chplan_ap.Channel[j];
-+					i++;
-+					j++;
-+					k++;
-+				} else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) {
-+					chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
-+#if 0
-+					if (chplan_sta[i].flags & RTW_CHF_NO_IR)
-+						chplan_new[k].flags |= RTW_CHF_NO_IR;
-+#else
-+					chplan_new[k].flags |= RTW_CHF_NO_IR;
-+#endif
-+					i++;
-+					k++;
-+				} else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) {
-+					chplan_new[k].ChannelNum = chplan_ap.Channel[j];
-+					j++;
-+					k++;
-+				}
-+			} while (1);
-+
-+			/* change AP not support channel to Passive scan */
-+			while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) {
-+				chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
-+#if 0
-+				if (chplan_sta[i].flags & RTW_CHF_NO_IR)
-+					chplan_new[k].flags |= RTW_CHF_NO_IR;
-+#else
-+				chplan_new[k].flags |= RTW_CHF_NO_IR;
-+#endif
-+				i++;
-+				k++;
-+			}
-+
-+			/* add channel AP supported */
-+			while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] != 0)) {
-+				chplan_new[k].ChannelNum = chplan_ap.Channel[j];
-+				j++;
-+				k++;
-+			}
-+		} else {
-+			/* keep original STA 5G channel plan */
-+			while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) {
-+				chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum;
-+				if (chplan_sta[i].flags & RTW_CHF_NO_IR)
-+					chplan_new[k].flags |= RTW_CHF_NO_IR;
-+				i++;
-+				k++;
-+			}
-+		}
-+
-+		pmlmeext->update_channel_plan_by_ap_done = 1;
-+		rtw_nlrtw_reg_change_event(padapter);
-+
-+#ifdef CONFIG_RTW_DEBUG
-+		k = 0;
-+		RTW_INFO("%s: new STA channel plan {", __FUNCTION__);
-+		while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) {
-+			_RTW_INFO("%02d(%c),", chplan_new[k].ChannelNum, chplan_new[k].flags & RTW_CHF_NO_IR ? 'p' : 'c');
-+			k++;
-+		}
-+		_RTW_INFO("}\n");
-+#endif
-+
-+#if 0
-+		/* recover the right channel index */
-+		channel = chplan_sta[pmlmeext->sitesurvey_res.channel_idx].ChannelNum;
-+		k = 0;
-+		while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) {
-+			if (chplan_new[k].ChannelNum == channel) {
-+				RTW_INFO("%s: change mlme_ext sitesurvey channel index from %d to %d\n",
-+					__FUNCTION__, pmlmeext->sitesurvey_res.channel_idx, k);
-+				pmlmeext->sitesurvey_res.channel_idx = k;
-+				break;
-+			}
-+			k++;
-+		}
-+#endif
-+
-+done_update_chplan_from_ap:
-+		if (chplan_sta)
-+			rtw_mfree(chplan_sta, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
-+	}
-+}
-+#endif
-+
-+void rtw_survey_event_callback(_adapter	*adapter, u8 *pbuf)
-+{
-+	_irqL  irqL;
-+	u32 len;
-+	u8 val8;
-+	WLAN_BSSID_EX *pnetwork;
-+	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
-+
-+	pnetwork = (WLAN_BSSID_EX *)pbuf;
-+
-+	len = get_WLAN_BSSID_EX_sz(pnetwork);
-+	if (len > (sizeof(WLAN_BSSID_EX))) {
-+		return;
-+	}
-+
-+#ifdef CONFIG_RTW_80211K
-+    	val8 = 0;
-+	rtw_hal_get_hwreg(adapter, HW_VAR_FREECNT, &val8);
-+
-+	/* use TSF if no free run counter */
-+	if (val8==0)
-+		pnetwork->PhyInfo.free_cnt = (u32)rtw_hal_get_tsftr_by_port(
-+			adapter, rtw_hal_get_port(adapter));
-+#endif
-+
-+	if (pnetwork->InfrastructureMode == Ndis802_11Infrastructure) {
-+		#ifdef CONFIG_80211D
-+		process_80211d(adapter, pnetwork);
-+		#endif
-+		if (MLME_IS_SCAN(adapter)) {
-+			adapter->mlmeextpriv.sitesurvey_res.activate_ch_cnt
-+				+= rtw_process_beacon_hint(adapter, pnetwork);
-+		}
-+	}
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+	/* update IBSS_network 's timestamp */
-+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) {
-+		if (_rtw_memcmp(&(pmlmepriv->cur_network.network.MacAddress), pnetwork->MacAddress, ETH_ALEN)) {
-+			struct wlan_network *ibss_wlan = NULL;
-+			_irqL	irqL;
-+
-+			_rtw_memcpy(pmlmepriv->cur_network.network.IEs, pnetwork->IEs, 8);
-+			_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+			ibss_wlan = _rtw_find_network(&pmlmepriv->scanned_queue,  pnetwork->MacAddress);
-+			if (ibss_wlan) {
-+				_rtw_memcpy(ibss_wlan->network.IEs , pnetwork->IEs, 8);
-+				_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+				goto exit;
-+			}
-+			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+		}
-+	}
-+
-+	/* lock pmlmepriv->lock when you accessing network_q */
-+	if ((check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)) == _FALSE) {
-+		if (pnetwork->Ssid.Ssid[0] == 0)
-+			pnetwork->Ssid.SsidLength = 0;
-+		rtw_add_network(adapter, pnetwork);
-+	}
-+
-+exit:
-+
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+
-+	return;
-+}
-+
-+void rtw_surveydone_event_callback(_adapter	*adapter, u8 *pbuf)
-+{
-+	_irqL  irqL;
-+	struct surveydone_event *parm = (struct surveydone_event *)pbuf;
-+	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
-+
-+#ifdef CONFIG_MLME_EXT
-+	mlmeext_surveydone_event_callback(adapter);
-+#endif
-+
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+	if (pmlmepriv->wps_probe_req_ie) {
-+		u32 free_len = pmlmepriv->wps_probe_req_ie_len;
-+		pmlmepriv->wps_probe_req_ie_len = 0;
-+		rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);
-+		pmlmepriv->wps_probe_req_ie = NULL;
-+	}
-+
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _FALSE) {
-+		RTW_INFO(FUNC_ADPT_FMT" fw_state:0x%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));
-+		/* rtw_warn_on(1); */
-+	}
-+
-+	if (pmlmeext->scan_abort == _TRUE)
-+		pmlmeext->scan_abort = _FALSE;
-+
-+	_clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY);
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+	_cancel_timer_ex(&pmlmepriv->scan_to_timer);
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+	rtw_set_signal_stat_timer(&adapter->recvpriv);
-+#endif
-+
-+	if (pmlmepriv->to_join == _TRUE) {
-+		if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) {
-+			if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) {
-+				set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
-+
-+				if (rtw_select_and_join_from_scanned_queue(pmlmepriv) == _SUCCESS)
-+					_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
-+				#ifdef CONFIG_AP_MODE
-+				else {
-+					WLAN_BSSID_EX    *pdev_network = &(adapter->registrypriv.dev_network);
-+					u8 *pibss = adapter->registrypriv.dev_network.MacAddress;
-+
-+					/* pmlmepriv->fw_state ^= WIFI_UNDER_SURVEY; */ /* because don't set assoc_timer */
-+					_clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY);
-+
-+
-+					_rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
-+					_rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
-+
-+					rtw_update_registrypriv_dev_network(adapter);
-+					rtw_generate_random_ibss(pibss);
-+
-+					/*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/
-+					init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
-+
-+					if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS)
-+						RTW_ERR("rtw_create_ibss_cmd FAIL\n");
-+
-+					pmlmepriv->to_join = _FALSE;
-+				}
-+				#endif /* CONFIG_AP_MODE */
-+			}
-+		} else {
-+			int s_ret;
-+			set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
-+			pmlmepriv->to_join = _FALSE;
-+			s_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);
-+			if (_SUCCESS == s_ret)
-+				_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
-+			else if (s_ret == 2) { /* there is no need to wait for join */
-+				_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
-+				rtw_indicate_connect(adapter);
-+			} else {
-+				RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(adapter));
-+
-+				if (rtw_to_roam(adapter) != 0) {
-+					struct sitesurvey_parm scan_parm;
-+					u8 ssc_chk = rtw_sitesurvey_condition_check(adapter, _FALSE);
-+
-+					rtw_init_sitesurvey_parm(adapter, &scan_parm);
-+					_rtw_memcpy(&scan_parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
-+					scan_parm.ssid_num = 1;
-+
-+					if (rtw_dec_to_roam(adapter) == 0
-+						|| (ssc_chk != SS_ALLOW && ssc_chk != SS_DENY_BUSY_TRAFFIC)
-+						|| _SUCCESS != rtw_sitesurvey_cmd(adapter, &scan_parm)
-+					   ) {
-+						rtw_set_to_roam(adapter, 0);
-+						rtw_free_assoc_resources(adapter, _TRUE);
-+						rtw_indicate_disconnect(adapter, 0, _FALSE);
-+					} else
-+						pmlmepriv->to_join = _TRUE;
-+				} else
-+					rtw_indicate_disconnect(adapter, 0, _FALSE);
-+				_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
-+			}
-+		}
-+	} else {
-+		if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)
-+		#if (defined(CONFIG_RTW_WNM) && defined(CONFIG_RTW_80211R))
-+			|| rtw_wnm_btm_roam_triggered(adapter)
-+		#endif
-+		) {
-+			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
-+			    && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
-+				if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) {
-+			#ifdef CONFIG_RTW_80211R
-+					rtw_ft_start_roam(adapter,
-+						(u8 *)pmlmepriv->roam_network->network.MacAddress);
-+			#else
-+					receive_disconnect(adapter, pmlmepriv->cur_network.network.MacAddress
-+						, WLAN_REASON_ACTIVE_ROAM, _FALSE);
-+			#endif
-+				}
-+			}
-+		}
-+	}
-+
-+	/* RTW_INFO("scan complete in %dms\n",rtw_get_passing_time_ms(pmlmepriv->scan_start_time)); */
-+
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+#ifdef CONFIG_P2P_PS
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		p2p_ps_wk_cmd(adapter, P2P_PS_SCAN_DONE, 0);
-+#endif /* CONFIG_P2P_PS */
-+
-+	rtw_mi_os_xmit_schedule(adapter);
-+
-+#ifdef CONFIG_DRVEXT_MODULE_WSC
-+	drvext_surveydone_callback(&adapter->drvextpriv);
-+#endif
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	{
-+		struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+		if (pmlmeext->sitesurvey_res.bss_cnt == 0) {
-+			/* rtw_hal_sreset_reset(adapter); */
-+		}
-+	}
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	rtw_cfg80211_surveydone_event_callback(adapter);
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+	rtw_indicate_scan_done(adapter, _FALSE);
-+
-+#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211)
-+	rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _FALSE);
-+#endif
-+
-+	if (parm->activate_ch_cnt) {
-+		op_class_pref_apply_regulatory(adapter, REG_BEACON_HINT);
-+		rtw_nlrtw_reg_beacon_hint_event(adapter);
-+	}
-+
-+#ifdef CONFIG_RTW_MESH
-+	#if CONFIG_RTW_MESH_OFFCH_CAND
-+	if (rtw_mesh_offch_candidate_accepted(adapter)) {
-+		u8 ch;
-+
-+		ch = rtw_mesh_select_operating_ch(adapter);
-+		if (ch && pmlmepriv->cur_network.network.Configuration.DSConfig != ch) {
-+			u8 ifbmp = rtw_mi_get_ap_mesh_ifbmp(adapter);
-+
-+			if (ifbmp) {
-+				/* switch to selected channel */
-+				rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, ifbmp, 0, ch, REQ_BW_ORI, REQ_OFFSET_NONE);
-+				issue_probereq_ex(adapter, &pmlmepriv->cur_network.network.mesh_id, NULL, 0, 0, 0, 0);
-+			} else
-+				rtw_warn_on(1);
-+		}
-+	}
-+	#endif
-+#endif /* CONFIG_RTW_MESH */
-+
-+#ifdef CONFIG_RTW_ACS
-+	if (parm->acs) {
-+		u8 ifbmp = rtw_mi_get_ap_mesh_ifbmp(adapter);
-+
-+		if (ifbmp)
-+			rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, ifbmp, 0, REQ_CH_INT_INFO, REQ_BW_ORI, REQ_OFFSET_NONE);
-+	}
-+#endif
-+}
-+
-+u8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval)
-+{
-+	u8 ss_condition = SS_ALLOW;
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct registry_priv *registry_par = &adapter->registrypriv;
-+
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	if (rtw_mp_mode_check(adapter)) {
-+		RTW_INFO("%s ("ADPT_FMT") MP mode block Scan request\n", caller, ADPT_ARG(adapter));
-+		ss_condition = SS_DENY_MP_MODE;
-+		goto _exit;
-+	}
-+#endif
-+
-+#ifdef DBG_LA_MODE
-+	if(registry_par->la_mode_en == 1 && MLME_IS_ASOC(adapter)) {
-+		RTW_INFO("%s ("ADPT_FMT") LA debug mode block Scan request\n", caller, ADPT_ARG(adapter));
-+		ss_condition = SS_DENY_LA_MODE;
-+		goto _exit;
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	if (adapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) {
-+		RTW_INFO("%s ("ADPT_FMT") blocking scan for under rson scanning process\n", caller, ADPT_ARG(adapter));
-+		ss_condition = SS_DENY_RSON_SCANING;
-+		goto _exit;
-+	}
-+#endif
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (adapter_wdev_data(adapter)->block_scan == _TRUE) {
-+		RTW_INFO("%s ("ADPT_FMT") wdev_priv.block_scan is set\n", caller, ADPT_ARG(adapter));
-+		ss_condition = SS_DENY_BLOCK_SCAN;
-+		goto _exit;
-+	}
-+#endif
-+
-+	if (adapter_to_dvobj(adapter)->scan_deny == _TRUE) {
-+		RTW_INFO("%s ("ADPT_FMT") tpt mode, scan deny!\n", caller, ADPT_ARG(adapter));
-+		ss_condition = SS_DENY_BLOCK_SCAN;
-+		goto _exit;
-+	}
-+
-+	if (rtw_is_scan_deny(adapter)) {
-+		RTW_INFO("%s ("ADPT_FMT") : scan deny\n", caller, ADPT_ARG(adapter));
-+		ss_condition = SS_DENY_BY_DRV;
-+		goto _exit;
-+	}
-+
-+#ifdef CONFIG_ADAPTIVITY_DENY_SCAN
-+	if (registry_par->adaptivity_en
-+	    && rtw_phydm_get_edcca_flag(adapter)
-+	    && rtw_is_2g_ch(GET_HAL_DATA(adapter)->current_channel)) {
-+		RTW_WARN(FUNC_ADPT_FMT": Adaptivity block scan! (ch=%u)\n",
-+			 FUNC_ADPT_ARG(adapter),
-+			 GET_HAL_DATA(adapter)->current_channel);
-+		ss_condition = SS_DENY_ADAPTIVITY;
-+		goto _exit;
-+	}
-+#endif /* CONFIG_ADAPTIVITY_DENY_SCAN */
-+
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE)){
-+		if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
-+			RTW_INFO("%s ("ADPT_FMT") : scan abort!! AP mode process WPS\n", caller, ADPT_ARG(adapter));
-+			ss_condition = SS_DENY_SELF_AP_UNDER_WPS;
-+			goto _exit;
-+		} else if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) {
-+			RTW_INFO("%s ("ADPT_FMT") : scan abort!!AP mode under linking (fwstate=0x%x)\n",
-+				caller, ADPT_ARG(adapter), pmlmepriv->fw_state);
-+			ss_condition = SS_DENY_SELF_AP_UNDER_LINKING;
-+			goto _exit;
-+		} else if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE) {
-+			RTW_INFO("%s ("ADPT_FMT") : scan abort!!AP mode under survey (fwstate=0x%x)\n",
-+				caller, ADPT_ARG(adapter), pmlmepriv->fw_state);
-+			ss_condition = SS_DENY_SELF_AP_UNDER_SURVEY;
-+			goto _exit;
-+		}
-+	} else {
-+		if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) {
-+			RTW_INFO("%s ("ADPT_FMT") : scan abort!!STA mode under linking (fwstate=0x%x)\n",
-+				caller, ADPT_ARG(adapter), pmlmepriv->fw_state);
-+			ss_condition = SS_DENY_SELF_STA_UNDER_LINKING;
-+			goto _exit;
-+		} else if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE) {
-+			RTW_INFO("%s ("ADPT_FMT") : scan abort!!STA mode under survey (fwstate=0x%x)\n",
-+				caller, ADPT_ARG(adapter), pmlmepriv->fw_state);
-+			ss_condition = SS_DENY_SELF_STA_UNDER_SURVEY;
-+			goto _exit;
-+		}
-+	}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_buddy_check_fwstate(adapter, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)) {
-+		RTW_INFO("%s ("ADPT_FMT") : scan abort!! buddy_intf under linking or wps\n", caller, ADPT_ARG(adapter));
-+		ss_condition = SS_DENY_BUDDY_UNDER_LINK_WPS;
-+		goto _exit;
-+
-+	} else if (rtw_mi_buddy_check_fwstate(adapter, WIFI_UNDER_SURVEY)) {
-+		RTW_INFO("%s ("ADPT_FMT") : scan abort!! buddy_intf under survey\n", caller, ADPT_ARG(adapter));
-+		ss_condition = SS_DENY_BUDDY_UNDER_SURVEY;
-+		goto _exit;
-+	}
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+#ifdef RTW_BUSY_DENY_SCAN
-+	/*
-+	 * busy traffic check
-+	 * Rules:
-+	 * 1. If (scan interval <= BUSY_TRAFFIC_SCAN_DENY_PERIOD) always allow
-+	 *    scan, otherwise goto rule 2.
-+	 * 2. Deny scan if any interface is busy, otherwise allow scan.
-+	 */
-+	if (pmlmepriv->lastscantime
-+	    && (rtw_get_passing_time_ms(pmlmepriv->lastscantime) >
-+		registry_par->scan_interval_thr)
-+	    && rtw_mi_busy_traffic_check(adapter)) {
-+		RTW_WARN("%s ("ADPT_FMT") : scan abort!! BusyTraffic\n",
-+			 caller, ADPT_ARG(adapter));
-+		ss_condition = SS_DENY_BUSY_TRAFFIC;
-+		goto _exit;
-+	}
-+#endif /* RTW_BUSY_DENY_SCAN */
-+
-+_exit:
-+	return ss_condition;
-+}
-+
-+static void free_scanqueue(struct	mlme_priv *pmlmepriv)
-+{
-+	_irqL irqL, irqL0;
-+	_queue *free_queue = &pmlmepriv->free_bss_pool;
-+	_queue *scan_queue = &pmlmepriv->scanned_queue;
-+	_list	*plist, *phead, *ptemp;
-+
-+
-+	_enter_critical_bh(&scan_queue->lock, &irqL0);
-+	_enter_critical_bh(&free_queue->lock, &irqL);
-+
-+	phead = get_list_head(scan_queue);
-+	plist = get_next(phead);
-+
-+	while (plist != phead) {
-+		ptemp = get_next(plist);
-+		rtw_list_delete(plist);
-+		rtw_list_insert_tail(plist, &free_queue->queue);
-+		plist = ptemp;
-+		pmlmepriv->num_of_scanned--;
-+	}
-+
-+	_exit_critical_bh(&free_queue->lock, &irqL);
-+	_exit_critical_bh(&scan_queue->lock, &irqL0);
-+
-+}
-+
-+void rtw_reset_rx_info(_adapter *adapter)
-+{
-+	struct recv_priv  *precvpriv = &adapter->recvpriv;
-+
-+	precvpriv->dbg_rx_ampdu_drop_count = 0;
-+	precvpriv->dbg_rx_ampdu_forced_indicate_count = 0;
-+	precvpriv->dbg_rx_ampdu_loss_count = 0;
-+	precvpriv->dbg_rx_dup_mgt_frame_drop_count = 0;
-+	precvpriv->dbg_rx_ampdu_window_shift_cnt = 0;
-+	precvpriv->dbg_rx_drop_count = 0;
-+	precvpriv->dbg_rx_conflic_mac_addr_cnt = 0;
-+}
-+
-+/*
-+*rtw_free_assoc_resources: the caller has to lock pmlmepriv->lock
-+*/
-+void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue)
-+{
-+	_irqL irqL;
-+	struct wlan_network *pwlan = NULL;
-+	struct	mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct wlan_network *tgt_network = &pmlmepriv->cur_network;
-+
-+
-+#ifdef CONFIG_TDLS
-+	struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
-+#endif /* CONFIG_TDLS */
-+
-+
-+	RTW_INFO("%s-"ADPT_FMT" tgt_network MacAddress=" MAC_FMT" ssid=%s\n",
-+		__func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress), tgt_network->network.Ssid.Ssid);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
-+		struct sta_info *psta;
-+
-+		psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress);
-+
-+#ifdef CONFIG_TDLS
-+		rtw_free_all_tdls_sta(adapter, _TRUE);
-+		rtw_reset_tdls_info(adapter);
-+
-+		if (ptdlsinfo->link_established == _TRUE)
-+			rtw_tdls_cmd(adapter, NULL, TDLS_RS_RCR);
-+#endif /* CONFIG_TDLS */
-+
-+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
-+		rtw_free_stainfo(adapter, psta);
-+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
-+
-+	}
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
-+		struct sta_info *psta;
-+
-+		rtw_free_all_stainfo(adapter);
-+
-+		psta = rtw_get_bcmc_stainfo(adapter);
-+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
-+		rtw_free_stainfo(adapter, psta);
-+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
-+
-+		rtw_init_bcmc_stainfo(adapter);
-+	}
-+
-+	if (lock_scanned_queue)
-+		_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS) || (pmlmepriv->wpa_phase == _TRUE)){
-+		RTW_INFO("Dont free disconnecting network of scanned_queue due to uner %s %s phase\n\n",
-+			check_fwstate(pmlmepriv, WIFI_UNDER_WPS) ? "WPS" : "",
-+			(pmlmepriv->wpa_phase == _TRUE) ? "WPA" : "");
-+	} else {
-+		pwlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, tgt_network);
-+		if (pwlan) {
-+			pwlan->fixed = _FALSE;
-+
-+			RTW_INFO("Free disconnecting network of scanned_queue\n");
-+			rtw_free_network_nolock(adapter, pwlan);
-+#ifdef CONFIG_P2P
-+			if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) {
-+				rtw_set_scan_deny(adapter, 2000);
-+				/* rtw_clear_scan_deny(adapter); */
-+			}
-+#endif /* CONFIG_P2P */
-+		} else
-+			RTW_ERR("Free disconnecting network of scanned_queue failed due to pwlan == NULL\n\n");
-+	}
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) && (adapter->stapriv.asoc_sta_count == 1))
-+	    /*||check_fwstate(pmlmepriv, WIFI_STATION_STATE)*/) {
-+		if (pwlan)
-+			rtw_free_network_nolock(adapter, pwlan);
-+	}
-+
-+	if (lock_scanned_queue)
-+		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	adapter->securitypriv.key_mask = 0;
-+
-+	rtw_reset_rx_info(adapter);
-+
-+
-+}
-+
-+/*
-+*rtw_indicate_connect: the caller has to lock pmlmepriv->lock
-+*/
-+void rtw_indicate_connect(_adapter *padapter)
-+{
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+
-+	pmlmepriv->to_join = _FALSE;
-+
-+	if (!check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) {
-+
-+		set_fwstate(pmlmepriv, WIFI_ASOC_STATE);
-+
-+		rtw_led_control(padapter, LED_CTL_LINK);
-+
-+		rtw_os_indicate_connect(padapter);
-+
-+		#ifdef CONFIG_RTW_WDS
-+		if (MLME_IS_STA(padapter))
-+			rtw_wds_gptr_tbl_init(padapter);
-+		#endif
-+	}
-+
-+	rtw_set_to_roam(padapter, 0);
-+	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
-+		rtw_mi_set_scan_deny(padapter, 3000);
-+
-+
-+}
-+
-+
-+/*
-+*rtw_indicate_disconnect: the caller has to lock pmlmepriv->lock
-+*/
-+void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated)
-+{
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX	*cur_network = &(pmlmeinfo->network);
-+#ifdef CONFIG_WAPI_SUPPORT
-+	struct sta_info *psta;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+#endif
-+	u8 *wps_ie = NULL;
-+	uint wpsie_len = 0;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS))
-+		pmlmepriv->wpa_phase = _TRUE;
-+
-+	_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS | WIFI_OP_CH_SWITCHING | WIFI_UNDER_KEY_HANDSHAKE);
-+
-+	/* force to clear cur_network_scanned's SELECTED REGISTRAR */
-+	if (pmlmepriv->cur_network_scanned) {
-+		WLAN_BSSID_EX	*current_joined_bss = &(pmlmepriv->cur_network_scanned->network);
-+		if (current_joined_bss) {
-+			wps_ie = rtw_get_wps_ie(current_joined_bss->IEs + _FIXED_IE_LENGTH_,
-+				current_joined_bss->IELength - _FIXED_IE_LENGTH_, NULL, &wpsie_len);
-+			if (wps_ie && wpsie_len > 0) {
-+				u8 *attr = NULL;
-+				u32 attr_len;
-+				attr = rtw_get_wps_attr(wps_ie, wpsie_len, WPS_ATTR_SELECTED_REGISTRAR,
-+							NULL, &attr_len);
-+				if (attr)
-+					*(attr + 4) = 0;
-+			}
-+		}
-+	}
-+	/* RTW_INFO("clear wps when %s\n", __func__); */
-+
-+	if (rtw_to_roam(padapter) > 0)
-+		_clr_fwstate_(pmlmepriv, WIFI_ASOC_STATE);
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
-+		rtw_wapi_return_one_sta_info(padapter, psta->cmn.mac_addr);
-+	else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) ||
-+		 check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE))
-+		rtw_wapi_return_all_sta_info(padapter);
-+#endif
-+
-+	if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)
-+	    || (rtw_to_roam(padapter) <= 0)
-+	   ) {
-+		#ifdef CONFIG_RTW_WDS
-+		adapter_set_use_wds(padapter, 0);
-+		rtw_wds_gptr_tbl_unregister(padapter);
-+		#endif
-+		#ifdef CONFIG_RTW_MULTI_AP
-+		padapter->multi_ap = 0;
-+		#endif
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+		if (ATOMIC_READ(&padapter->tbtx_tx_pause) == _TRUE) {
-+			ATOMIC_SET(&padapter->tbtx_tx_pause, _FALSE);
-+			rtw_tx_control_cmd(padapter);
-+		}
-+#endif
-+
-+		rtw_os_indicate_disconnect(padapter, reason, locally_generated);
-+
-+		/* set ips_deny_time to avoid enter IPS before LPS leave */
-+		rtw_set_ips_deny(padapter, 3000);
-+
-+		_clr_fwstate_(pmlmepriv, WIFI_ASOC_STATE);
-+
-+		rtw_led_control(padapter, LED_CTL_NO_LINK);
-+
-+		rtw_clear_scan_deny(padapter);
-+	}
-+
-+#ifdef CONFIG_P2P_PS
-+	p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);
-+#endif /* CONFIG_P2P_PS */
-+
-+#ifdef CONFIG_LPS
-+	rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, 0);
-+#endif
-+
-+#ifdef CONFIG_BEAMFORMING
-+	beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, cur_network->MacAddress, ETH_ALEN, 1);
-+#endif /*CONFIG_BEAMFORMING*/
-+
-+}
-+
-+inline void rtw_indicate_scan_done(_adapter *padapter, bool aborted)
-+{
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+
-+	rtw_os_indicate_scan_done(padapter, aborted);
-+
-+#ifdef CONFIG_IPS
-+	if (is_primary_adapter(padapter)
-+	    && (_FALSE == adapter_to_pwrctl(padapter)->bInSuspend)
-+	    && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_LINKING) == _FALSE)) {
-+		struct pwrctrl_priv *pwrpriv;
-+
-+		pwrpriv = adapter_to_pwrctl(padapter);
-+		rtw_set_ips_deny(padapter, 0);
-+#ifdef CONFIG_IPS_CHECK_IN_WD
-+		_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 1);
-+#else /* !CONFIG_IPS_CHECK_IN_WD */
-+		_rtw_set_pwr_state_check_timer(pwrpriv, 1);
-+#endif /* !CONFIG_IPS_CHECK_IN_WD */
-+	}
-+#endif /* CONFIG_IPS */
-+}
-+
-+static u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms)
-+{
-+	systime start;
-+	u32 pass_ms;
-+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+
-+	start = rtw_get_current_time();
-+
-+	pmlmeext->scan_abort = abort;
-+
-+	while (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)
-+	       && rtw_get_passing_time_ms(start) <= timeout_ms) {
-+
-+		if (RTW_CANNOT_RUN(adapter))
-+			break;
-+
-+		RTW_INFO(FUNC_NDEV_FMT"fw_state=WIFI_UNDER_SURVEY!\n", FUNC_NDEV_ARG(adapter->pnetdev));
-+		rtw_msleep_os(20);
-+	}
-+
-+	if (_TRUE == abort) {
-+		if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) {
-+			if (!RTW_CANNOT_RUN(adapter))
-+				RTW_INFO(FUNC_NDEV_FMT"waiting for scan_abort time out!\n", FUNC_NDEV_ARG(adapter->pnetdev));
-+#ifdef CONFIG_PLATFORM_MSTAR
-+			/*_clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY);*/
-+			set_survey_timer(pmlmeext, 0);
-+			mlme_set_scan_to_timer(pmlmepriv, 50);
-+#endif
-+			rtw_indicate_scan_done(adapter, _TRUE);
-+		}
-+	}
-+
-+	pmlmeext->scan_abort = _FALSE;
-+	pass_ms = rtw_get_passing_time_ms(start);
-+
-+	return pass_ms;
-+
-+}
-+
-+void rtw_scan_wait_completed(_adapter *adapter)
-+{
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	struct ss_res *ss = &pmlmeext->sitesurvey_res;
-+
-+	_rtw_wait_scan_done(adapter, _FALSE, ss->scan_timeout_ms);
-+}
-+
-+u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms)
-+{
-+	return _rtw_wait_scan_done(adapter, _TRUE, timeout_ms);
-+}
-+
-+void rtw_scan_abort_no_wait(_adapter *adapter)
-+{
-+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY))
-+		pmlmeext->scan_abort = _TRUE;
-+}
-+
-+void rtw_scan_abort(_adapter *adapter)
-+{
-+	rtw_scan_abort_timeout(adapter, 200);
-+}
-+
-+static u32 _rtw_wait_join_done(_adapter *adapter, u8 abort, u32 timeout_ms)
-+{
-+	systime start;
-+	u32 pass_ms;
-+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+
-+	start = rtw_get_current_time();
-+
-+	pmlmeext->join_abort = abort;
-+	if (abort)
-+		set_link_timer(pmlmeext, 1);
-+
-+	while (rtw_get_passing_time_ms(start) <= timeout_ms
-+		&& (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)
-+			#ifdef CONFIG_IOCTL_CFG80211
-+			|| rtw_cfg80211_is_connect_requested(adapter)
-+			#endif
-+			)
-+	) {
-+		if (RTW_CANNOT_RUN(adapter))
-+			break;
-+
-+		RTW_INFO(FUNC_ADPT_FMT" linking...\n", FUNC_ADPT_ARG(adapter));
-+		rtw_msleep_os(20);
-+	}
-+
-+	if (abort) {
-+		if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)
-+			#ifdef CONFIG_IOCTL_CFG80211
-+			|| rtw_cfg80211_is_connect_requested(adapter)
-+			#endif
-+		) {
-+			if (!RTW_CANNOT_RUN(adapter))
-+				RTW_INFO(FUNC_ADPT_FMT" waiting for join_abort time out!\n", FUNC_ADPT_ARG(adapter));
-+		}
-+	}
-+
-+	pmlmeext->join_abort = 0;
-+	pass_ms = rtw_get_passing_time_ms(start);
-+
-+	return pass_ms;
-+}
-+
-+u32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms)
-+{
-+	return _rtw_wait_join_done(adapter, _TRUE, timeout_ms);
-+}
-+
-+static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork)
-+{
-+	int i;
-+	struct sta_info *psta = NULL;
-+	struct recv_reorder_ctrl *preorder_ctrl;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+#ifdef CONFIG_RTS_FULL_BW
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct wlan_network  *cur_network = &(pmlmepriv->cur_network);
-+#endif/*CONFIG_RTS_FULL_BW*/
-+
-+	psta = rtw_get_stainfo(pstapriv, pnetwork->network.MacAddress);
-+	if (psta == NULL)
-+		psta = rtw_alloc_stainfo(pstapriv, pnetwork->network.MacAddress);
-+
-+	if (psta) { /* update ptarget_sta */
-+		RTW_INFO("%s\n", __FUNCTION__);
-+
-+		psta->cmn.aid  = pnetwork->join_res;
-+
-+		update_sta_info(padapter, psta);
-+
-+		/* update station supportRate */
-+		psta->bssratelen = rtw_get_rateset_len(pnetwork->network.SupportedRates);
-+		_rtw_memcpy(psta->bssrateset, pnetwork->network.SupportedRates, psta->bssratelen);
-+		rtw_hal_update_sta_ra_info(padapter, psta);
-+
-+		psta->wireless_mode = pmlmeext->cur_wireless_mode;
-+		rtw_hal_update_sta_wset(padapter, psta);
-+
-+		/* sta mode */
-+		rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
-+
-+		/* security related */
-+#ifdef CONFIG_RTW_80211R
-+		if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
-+			&& (psta->ft_pairwise_key_installed == _FALSE)) {
-+#else
-+		if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {
-+#endif
-+			u8 *ie;
-+			sint ie_len;
-+			u8 mfp_opt = MFP_NO;
-+
-+			padapter->securitypriv.binstallGrpkey = _FALSE;
-+			padapter->securitypriv.busetkipkey = _FALSE;
-+			padapter->securitypriv.bgrpkey_handshake = _FALSE;
-+
-+			ie = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, WLAN_EID_RSN
-+				, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_));
-+			if (ie && ie_len > 0
-+				&& rtw_parse_wpa2_ie(ie, ie_len + 2, NULL, NULL, NULL, NULL, &mfp_opt) == _SUCCESS
-+			) {
-+				if (padapter->securitypriv.mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL)
-+					psta->flags |= WLAN_STA_MFP;
-+			}
-+
-+			psta->ieee8021x_blocked = _TRUE;
-+			psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
-+
-+			_rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype));
-+			_rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype));
-+			_rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype));
-+		}
-+
-+		/*	Commented by Albert 2012/07/21 */
-+		/*	When doing the WPS, the wps_ie_len won't equal to 0 */
-+		/*	And the Wi-Fi driver shouldn't allow the data packet to be tramsmitted. */
-+		if (padapter->securitypriv.wps_ie_len != 0) {
-+			psta->ieee8021x_blocked = _TRUE;
-+			padapter->securitypriv.wps_ie_len = 0;
-+		}
-+
-+
-+		/* for A-MPDU Rx reordering buffer control for sta_info */
-+		/* if A-MPDU Rx is enabled, reseting  rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff */
-+		/* todo: check if AP can send A-MPDU packets */
-+		for (i = 0; i < 16 ; i++) {
-+			/* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */
-+			preorder_ctrl = &psta->recvreorder_ctrl[i];
-+			preorder_ctrl->enable = _FALSE;
-+			preorder_ctrl->indicate_seq = 0xffff;
-+			rtw_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack);
-+			#ifdef DBG_RX_SEQ
-+			RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%u preorder_ctrl->rec_abba_rsp_ack:%lu\n"
-+				, FUNC_ADPT_ARG(padapter)
-+				, i
-+				, preorder_ctrl->indicate_seq
-+				,preorder_ctrl->rec_abba_rsp_ack
-+				);
-+			#endif
-+			preorder_ctrl->wend_b = 0xffff;
-+			preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */
-+			preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;
-+		}
-+	}
-+
-+#ifdef	CONFIG_RTW_80211K
-+	_rtw_memcpy(&psta->rm_en_cap, pnetwork->network.PhyInfo.rm_en_cap, 5);
-+#endif
-+#ifdef CONFIG_RTW_MULTI_AP
-+	if (padapter->multi_ap & MULTI_AP_BACKHAUL_STA) {
-+		u8 multi_ap = rtw_get_multi_ap_ie_ext(pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6
-+				, pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6);
-+
-+		if (multi_ap & MULTI_AP_BACKHAUL_BSS) /* backhaul bss, enable WDS */
-+			psta->flags |= WLAN_STA_MULTI_AP | WLAN_STA_WDS;
-+		else if (multi_ap & MULTI_AP_FRONTHAUL_BSS) /* fronthaul bss only */
-+			psta->flags |= WLAN_STA_MULTI_AP;
-+	}
-+#endif
-+#ifdef CONFIG_RTS_FULL_BW
-+	rtw_parse_sta_vendor_ie_8812(padapter, psta, BSS_EX_TLV_IES(&cur_network->network), BSS_EX_TLV_IES_LEN(&cur_network->network));
-+#endif
-+	return psta;
-+
-+}
-+
-+/* pnetwork : returns from rtw_joinbss_event_callback
-+ * ptarget_wlan: found from scanned_queue */
-+static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network *ptarget_wlan, struct wlan_network  *pnetwork)
-+{
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct wlan_network  *cur_network = &(pmlmepriv->cur_network);
-+	sint tmp_fw_state = 0x0;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	/* why not use ptarget_wlan?? */
-+	_rtw_memcpy(&cur_network->network, &pnetwork->network, pnetwork->network.Length);
-+	/* some IEs in pnetwork is wrong, so we should use ptarget_wlan IEs */
-+	cur_network->network.IELength = ptarget_wlan->network.IELength;
-+	_rtw_memcpy(&cur_network->network.IEs[0], &ptarget_wlan->network.IEs[0], MAX_IE_SZ);
-+
-+	cur_network->aid = pnetwork->join_res;
-+
-+
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+	rtw_set_signal_stat_timer(&padapter->recvpriv);
-+#endif
-+	padapter->recvpriv.signal_strength = ptarget_wlan->network.PhyInfo.SignalStrength;
-+	padapter->recvpriv.signal_qual = ptarget_wlan->network.PhyInfo.SignalQuality;
-+	/* the ptarget_wlan->network.Rssi is raw data, we use ptarget_wlan->network.PhyInfo.SignalStrength instead (has scaled) */
-+	padapter->recvpriv.rssi = translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength);
-+#if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1
-+	RTW_INFO(FUNC_ADPT_FMT" signal_strength:%3u, rssi:%3d, signal_qual:%3u"
-+		 "\n"
-+		 , FUNC_ADPT_ARG(padapter)
-+		 , padapter->recvpriv.signal_strength
-+		 , padapter->recvpriv.rssi
-+		 , padapter->recvpriv.signal_qual
-+		);
-+#endif
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+	rtw_set_signal_stat_timer(&padapter->recvpriv);
-+#endif
-+
-+	/* update fw_state */ /* will clr WIFI_UNDER_LINKING here indirectly */
-+
-+	switch (pnetwork->network.InfrastructureMode) {
-+	case Ndis802_11Infrastructure:
-+		/* Check encryption */
-+		if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
-+			tmp_fw_state = tmp_fw_state | WIFI_UNDER_KEY_HANDSHAKE;
-+
-+		if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS))
-+			tmp_fw_state = tmp_fw_state | WIFI_UNDER_WPS;
-+
-+		init_fwstate(pmlmepriv, WIFI_STATION_STATE | tmp_fw_state);
-+
-+		break;
-+	case Ndis802_11IBSS:
-+		/*pmlmepriv->fw_state = WIFI_ADHOC_STATE;*/
-+		init_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
-+		break;
-+	default:
-+		/*pmlmepriv->fw_state = WIFI_NULL_STATE;*/
-+		init_fwstate(pmlmepriv, WIFI_NULL_STATE);
-+		break;
-+	}
-+
-+	rtw_update_protection(padapter, (cur_network->network.IEs) + sizeof(NDIS_802_11_FIXED_IEs),
-+			      (cur_network->network.IELength));
-+
-+#ifdef CONFIG_80211N_HT
-+	rtw_update_ht_cap(padapter, cur_network->network.IEs, cur_network->network.IELength, (u8) cur_network->network.Configuration.DSConfig);
-+#endif
-+}
-+
-+/* Notes: the fucntion could be > passive_level (the same context as Rx tasklet)
-+ * pnetwork : returns from rtw_joinbss_event_callback
-+ * ptarget_wlan: found from scanned_queue
-+ * if join_res > 0, for (fw_state==WIFI_STATION_STATE), we check if  "ptarget_sta" & "ptarget_wlan" exist.
-+ * if join_res > 0, for (fw_state==WIFI_ADHOC_STATE), we only check if "ptarget_wlan" exist.
-+ * if join_res > 0, update "cur_network->network" from "pnetwork->network" if (ptarget_wlan !=NULL).
-+ */
-+/* #define REJOIN */
-+void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status)
-+{
-+	_irqL irqL;
-+	static u8 retry = 0;
-+	struct sta_info *ptarget_sta = NULL, *pcur_sta = NULL;
-+	struct	sta_priv *pstapriv = &adapter->stapriv;
-+	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
-+	struct wlan_network	*pnetwork	= (struct wlan_network *)pbuf;
-+	struct wlan_network	*cur_network = &(pmlmepriv->cur_network);
-+	struct wlan_network	*pcur_wlan = NULL, *ptarget_wlan = NULL;
-+	unsigned int		the_same_macaddr = _FALSE;
-+
-+	rtw_get_encrypt_decrypt_from_registrypriv(adapter);
-+
-+	the_same_macaddr = _rtw_memcmp(pnetwork->network.MacAddress, cur_network->network.MacAddress, ETH_ALEN);
-+
-+	pnetwork->network.Length = get_WLAN_BSSID_EX_sz(&pnetwork->network);
-+	if (pnetwork->network.Length > sizeof(WLAN_BSSID_EX))
-+		goto exit;
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+	pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;
-+	pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;
-+
-+
-+	if (pnetwork->join_res > 0) {
-+		_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+		retry = 0;
-+		if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)) {
-+			/* s1. find ptarget_wlan */
-+			if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
-+				if (the_same_macaddr == _TRUE)
-+					ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
-+				else {
-+					pcur_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
-+					if (pcur_wlan)
-+						pcur_wlan->fixed = _FALSE;
-+
-+					pcur_sta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
-+					if (pcur_sta) {
-+						/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
-+						rtw_free_stainfo(adapter,  pcur_sta);
-+						/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
-+					}
-+
-+					ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress);
-+					if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
-+						if (ptarget_wlan)
-+							ptarget_wlan->fixed = _TRUE;
-+					}
-+				}
-+
-+			} else {
-+				ptarget_wlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, pnetwork);
-+				if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
-+					if (ptarget_wlan)
-+						ptarget_wlan->fixed = _TRUE;
-+				}
-+			}
-+
-+			/* s2. update cur_network */
-+			if (ptarget_wlan)
-+				rtw_joinbss_update_network(adapter, ptarget_wlan, pnetwork);
-+			else {
-+				RTW_PRINT("Can't find ptarget_wlan when joinbss_event callback\n");
-+				_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+				goto ignore_joinbss_callback;
-+			}
-+
-+
-+			/* s3. find ptarget_sta & update ptarget_sta after update cur_network only for station mode */
-+			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
-+				ptarget_sta = rtw_joinbss_update_stainfo(adapter, pnetwork);
-+				if (ptarget_sta == NULL) {
-+					RTW_ERR("Can't update stainfo when joinbss_event callback\n");
-+					_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+					goto ignore_joinbss_callback;
-+				}
-+
-+				/* Queue TX packets before FW/HW ready */
-+				/* clear in mlmeext_joinbss_event_callback() */
-+				rtw_xmit_queue_set(ptarget_sta);
-+			}
-+
-+			/* s4. indicate connect			 */
-+			if (MLME_IS_STA(adapter) || MLME_IS_ADHOC(adapter)) {
-+				pmlmepriv->cur_network_scanned = ptarget_wlan;
-+				rtw_indicate_connect(adapter);
-+			}
-+
-+			/* s5. Cancle assoc_timer					 */
-+			_cancel_timer_ex(&pmlmepriv->assoc_timer);
-+
-+
-+		} else {
-+			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+			goto ignore_joinbss_callback;
-+		}
-+
-+		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	} else if (pnetwork->join_res == -4) {
-+		rtw_reset_securitypriv(adapter);
-+		pmlmepriv->join_status = status;
-+		_set_timer(&pmlmepriv->assoc_timer, 1);
-+
-+		/* rtw_free_assoc_resources(adapter, _TRUE); */
-+
-+		if ((check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)) == _TRUE) {
-+			_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
-+		}
-+
-+	} else { /* if join_res < 0 (join fails), then try again */
-+
-+#ifdef REJOIN
-+		res = _FAIL;
-+		if (retry < 2) {
-+			res = rtw_select_and_join_from_scanned_queue(pmlmepriv);
-+		}
-+
-+		if (res == _SUCCESS) {
-+			/* extend time of assoc_timer */
-+			_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
-+			retry++;
-+		} else if (res == 2) { /* there is no need to wait for join */
-+			_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
-+			rtw_indicate_connect(adapter);
-+		} else {
-+#endif
-+			pmlmepriv->join_status = status;
-+			_set_timer(&pmlmepriv->assoc_timer, 1);
-+			/* rtw_free_assoc_resources(adapter, _TRUE); */
-+			_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
-+
-+#ifdef REJOIN
-+			retry = 0;
-+		}
-+#endif
-+	}
-+
-+ignore_joinbss_callback:
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+exit:
-+	return;
-+}
-+
-+void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf)
-+{
-+	struct wlan_network	*pnetwork	= (struct wlan_network *)pbuf;
-+
-+
-+	mlmeext_joinbss_event_callback(adapter, pnetwork->join_res);
-+
-+	rtw_mi_os_xmit_schedule(adapter);
-+
-+}
-+
-+void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected)
-+{
-+	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
-+	bool miracast_enabled = 0;
-+	bool miracast_sink = 0;
-+	u8 role = H2C_MSR_ROLE_RSVD;
-+
-+	if (sta == NULL) {
-+		RTW_PRINT(FUNC_ADPT_FMT" sta is NULL\n"
-+			  , FUNC_ADPT_ARG(adapter));
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	if (sta->cmn.mac_id >= macid_ctl->num) {
-+		RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n"
-+			  , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id);
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	if (!rtw_macid_is_used(macid_ctl, sta->cmn.mac_id)) {
-+		RTW_PRINT(FUNC_ADPT_FMT" macid:%u not is used, set connected to 0\n"
-+			  , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id);
-+		connected = 0;
-+		rtw_warn_on(1);
-+	}
-+
-+	if (connected && !rtw_macid_is_bmc(macid_ctl, sta->cmn.mac_id)) {
-+		miracast_enabled = STA_OP_WFD_MODE(sta) != 0 && is_miracast_enabled(adapter);
-+		miracast_sink = miracast_enabled && (STA_OP_WFD_MODE(sta) & MIRACAST_SINK);
-+
-+#ifdef CONFIG_TDLS
-+		if (sta->tdls_sta_state & TDLS_LINKED_STATE)
-+			role = H2C_MSR_ROLE_TDLS;
-+		else
-+#endif
-+		if (MLME_IS_STA(adapter)) {
-+			if (MLME_IS_GC(adapter))
-+				role = H2C_MSR_ROLE_GO;
-+			else
-+				role = H2C_MSR_ROLE_AP;
-+		} else if (MLME_IS_AP(adapter)) {
-+			if (MLME_IS_GO(adapter))
-+				role = H2C_MSR_ROLE_GC;
-+			else
-+				role = H2C_MSR_ROLE_STA;
-+		} else if (MLME_IS_ADHOC(adapter) || MLME_IS_ADHOC_MASTER(adapter))
-+			role = H2C_MSR_ROLE_ADHOC;
-+		else if (MLME_IS_MESH(adapter))
-+			role = H2C_MSR_ROLE_MESH;
-+
-+#ifdef CONFIG_WFD
-+		if (role == H2C_MSR_ROLE_GC
-+			|| role == H2C_MSR_ROLE_GO
-+			|| role == H2C_MSR_ROLE_TDLS
-+		) {
-+			if (adapter->wfd_info.rtsp_ctrlport
-+				|| adapter->wfd_info.tdls_rtsp_ctrlport
-+				|| adapter->wfd_info.peer_rtsp_ctrlport)
-+				rtw_wfd_st_switch(sta, 1);
-+		}
-+#endif
-+	}
-+
-+	rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter
-+		, connected
-+		, miracast_enabled
-+		, miracast_sink
-+		, role
-+		, sta->cmn.mac_id
-+	);
-+}
-+
-+u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected)
-+{
-+	struct cmd_priv	*cmdpriv = &adapter->cmdpriv;
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *cmd_parm;
-+	struct sta_media_status_rpt_cmd_parm *rpt_parm;
-+	u8	res = _SUCCESS;
-+
-+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (cmdobj == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (cmd_parm == NULL) {
-+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	rpt_parm = (struct sta_media_status_rpt_cmd_parm *)rtw_zmalloc(sizeof(struct sta_media_status_rpt_cmd_parm));
-+	if (rpt_parm == NULL) {
-+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+		rtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	rpt_parm->sta = sta;
-+	rpt_parm->connected = connected;
-+
-+	cmd_parm->ec_id = STA_MSTATUS_RPT_WK_CID;
-+	cmd_parm->type = 0;
-+	cmd_parm->size = sizeof(struct sta_media_status_rpt_cmd_parm);
-+	cmd_parm->pbuf = (u8 *)rpt_parm;
-+	init_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(cmdpriv, cmdobj);
-+
-+exit:
-+	return res;
-+}
-+
-+inline void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm)
-+{
-+	rtw_sta_media_status_rpt(adapter, parm->sta, parm->connected);
-+}
-+
-+void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf)
-+{
-+	_irqL irqL;
-+	struct sta_info *psta;
-+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
-+	struct stassoc_event	*pstassoc	= (struct stassoc_event *)pbuf;
-+	struct wlan_network	*cur_network = &(pmlmepriv->cur_network);
-+	struct wlan_network	*ptarget_wlan = NULL;
-+
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+	if (rtw_access_ctrl(adapter, pstassoc->macaddr) == _FALSE)
-+		return;
-+#endif
-+
-+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
-+	if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
-+		psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr);
-+		if (psta) {
-+			u8 *passoc_req = NULL;
-+			u32 assoc_req_len = 0;
-+
-+			rtw_sta_media_status_rpt(adapter, psta, 1);
-+
-+#ifdef CONFIG_MCC_MODE
-+			rtw_hal_mcc_update_macid_bitmap(adapter, psta->cmn.mac_id, _TRUE);
-+#endif /* CONFIG_MCC_MODE */
-+
-+#ifndef CONFIG_AUTO_AP_MODE
-+			ap_sta_info_defer_update(adapter, psta);
-+
-+			if (!MLME_IS_MESH(adapter)) {
-+				/* report to upper layer */
-+				RTW_INFO("indicate_sta_assoc_event to upper layer - hostapd\n");
-+				#ifdef CONFIG_IOCTL_CFG80211
-+				_enter_critical_bh(&psta->lock, &irqL);
-+				if (psta->passoc_req && psta->assoc_req_len > 0) {
-+					passoc_req = rtw_zmalloc(psta->assoc_req_len);
-+					if (passoc_req) {
-+						assoc_req_len = psta->assoc_req_len;
-+						_rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len);
-+					}
-+				}
-+				_exit_critical_bh(&psta->lock, &irqL);
-+
-+				if (passoc_req && assoc_req_len > 0) {
-+					rtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len);
-+					rtw_mfree(passoc_req, assoc_req_len);
-+				}
-+				#else /* !CONFIG_IOCTL_CFG80211	 */
-+				rtw_indicate_sta_assoc_event(adapter, psta);
-+				#endif /* !CONFIG_IOCTL_CFG80211 */
-+			}
-+#endif /* !CONFIG_AUTO_AP_MODE */
-+
-+#ifdef CONFIG_BEAMFORMING
-+			beamforming_wk_cmd(adapter, BEAMFORMING_CTRL_ENTER, (u8 *)psta, sizeof(struct sta_info), 0);
-+#endif/*CONFIG_BEAMFORMING*/
-+			if (is_wep_enc(adapter->securitypriv.dot11PrivacyAlgrthm))
-+				rtw_ap_wep_pk_setting(adapter, psta);
-+
-+			#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+			if (MLME_IS_AP(adapter)) {
-+				cmap_intfs_nl_sta_event(psta->cmn.mac_addr, adapter_mac_addr(adapter), 1
-+					, psta->passoc_req + IEEE80211_3ADDR_LEN, psta->assoc_req_len - IEEE80211_3ADDR_LEN);
-+			}
-+			#endif
-+		}
-+		goto exit;
-+	}
-+#endif /* defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
-+
-+	/* for AD-HOC mode */
-+	psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr);
-+	if (psta == NULL) {
-+		RTW_ERR(FUNC_ADPT_FMT" get no sta_info with "MAC_FMT"\n"
-+			, FUNC_ADPT_ARG(adapter), MAC_ARG(pstassoc->macaddr));
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	rtw_sta_media_status_rpt(adapter, psta, 1);
-+
-+	if (adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
-+		psta->dot118021XPrivacy = adapter->securitypriv.dot11PrivacyAlgrthm;
-+
-+
-+	psta->ieee8021x_blocked = _FALSE;
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
-+	    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) {
-+		if (adapter->stapriv.asoc_sta_count == 2) {
-+			_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+			ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
-+			pmlmepriv->cur_network_scanned = ptarget_wlan;
-+			if (ptarget_wlan)
-+				ptarget_wlan->fixed = _TRUE;
-+			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+			/* a sta + bc/mc_stainfo (not Ibss_stainfo) */
-+			rtw_indicate_connect(adapter);
-+		}
-+	}
-+
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+
-+	mlmeext_sta_add_event_callback(adapter, psta);
-+
-+#ifdef CONFIG_RTL8711
-+	/* submit SetStaKey_cmd to tell fw, fw will allocate an CAM entry for this sta	 */
-+	rtw_setstakey_cmd(adapter, psta, GROUP_KEY, _TRUE);
-+#endif
-+
-+exit:
-+#ifdef CONFIG_RTS_FULL_BW
-+	rtw_set_rts_bw(adapter);
-+#endif/*CONFIG_RTS_FULL_BW*/
-+	return;
-+}
-+
-+#ifdef CONFIG_IEEE80211W
-+void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf)
-+{
-+#ifdef CONFIG_AP_MODE
-+	_irqL irqL;
-+	struct sta_info *psta;
-+	struct stadel_event *pstadel = (struct stadel_event *)pbuf;
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+
-+	psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr);
-+
-+	if (psta) {
-+		u8 updated = _FALSE;
-+
-+		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+		if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
-+			rtw_list_delete(&psta->asoc_list);
-+			pstapriv->asoc_list_cnt--;
-+			#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+			if (psta->tbtx_enable)
-+				pstapriv->tbtx_asoc_list_cnt--;
-+			#endif
-+			updated = ap_free_sta(adapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE);
-+		}
-+		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+		associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL);
-+	}
-+#endif /* CONFIG_AP_MODE */
-+}
-+#endif /* CONFIG_IEEE80211W */
-+
-+void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id)
-+{
-+	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
-+
-+	if (mac_id < macid_ctl->num) {
-+		u8 id_is_shared = mac_id == RTW_DEFAULT_MGMT_MACID; /* TODO: real shared macid judgment */
-+
-+		RTW_INFO(FUNC_ADPT_FMT" - mac_id=%d%s\n", FUNC_ADPT_ARG(adapter)
-+			, mac_id, id_is_shared ? " shared" : "");
-+
-+		if (!id_is_shared) {
-+			rtw_hal_macid_drop(adapter, mac_id);
-+			rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter, 0, 0, 0, 0, mac_id);
-+			/*
-+			 * For safety, prevent from keeping macid sleep.
-+			 * If we can sure all power mode enter/leave are paired,
-+			 * this check can be removed.
-+			 * Lucas@20131113
-+			 */
-+			/* wakeup macid after disconnect. */
-+			/*if (MLME_IS_STA(adapter))*/
-+			rtw_hal_macid_wakeup(adapter, mac_id);
-+		}
-+	} else {
-+		RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n"
-+			  , FUNC_ADPT_ARG(adapter), mac_id);
-+		rtw_warn_on(1);
-+	}
-+}
-+void rtw_sta_mstatus_report(_adapter *adapter)
-+{
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct wlan_network *tgt_network = &pmlmepriv->cur_network;
-+	struct sta_info *psta = NULL;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
-+		psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress);
-+		if (psta)
-+			rtw_sta_mstatus_disc_rpt(adapter, psta->cmn.mac_id);
-+		else {
-+			RTW_INFO("%s "ADPT_FMT" - mac_addr: "MAC_FMT" psta == NULL\n", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress));
-+			rtw_warn_on(1);
-+		}
-+	}
-+}
-+
-+void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)
-+{
-+	_irqL irqL, irqL2;
-+
-+	struct sta_info *psta;
-+	struct wlan_network *pwlan = NULL;
-+	WLAN_BSSID_EX    *pdev_network = NULL;
-+	u8 *pibss = NULL;
-+	struct	mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
-+	struct	stadel_event *pstadel	= (struct stadel_event *)pbuf;
-+	struct wlan_network *tgt_network = &(pmlmepriv->cur_network);
-+
-+	RTW_INFO("%s(mac_id=%d)=" MAC_FMT "\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr));
-+	rtw_sta_mstatus_disc_rpt(adapter, pstadel->mac_id);
-+
-+#ifdef CONFIG_MCC_MODE
-+	rtw_hal_mcc_update_macid_bitmap(adapter, pstadel->mac_id, _FALSE);
-+#endif /* CONFIG_MCC_MODE */
-+
-+	psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr);
-+
-+	if (psta == NULL) {
-+		RTW_INFO("%s(mac_id=%d)=" MAC_FMT " psta == NULL\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr));
-+		/*rtw_warn_on(1);*/
-+	}
-+
-+	if (psta)
-+		rtw_wfd_st_switch(psta, 0);
-+
-+	if (MLME_IS_MESH(adapter)) {
-+		rtw_free_stainfo(adapter, psta);
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_AP_MODE
-+	if (MLME_IS_AP(adapter)) {
-+#ifdef CONFIG_IOCTL_CFG80211
-+#ifdef COMPAT_KERNEL_RELEASE
-+
-+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
-+		rtw_cfg80211_indicate_sta_disassoc(adapter, pstadel->macaddr, *(u16 *)pstadel->rsvd);
-+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+		#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+		cmap_intfs_nl_sta_event(pstadel->macaddr, adapter_mac_addr(adapter), 0, NULL, 0);
-+		#endif
-+
-+		rtw_free_stainfo(adapter, psta);
-+
-+		goto exit;
-+	}
-+#endif /* CONFIG_AP_MODE */
-+
-+	mlmeext_sta_del_event_callback(adapter);
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL2);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
-+		u16 reason = *((unsigned short *)(pstadel->rsvd));
-+		bool roam = _FALSE;
-+		struct wlan_network *roam_target = NULL;
-+
-+#ifdef CONFIG_LAYER2_ROAMING
-+#ifdef CONFIG_RTW_80211R
-+		if (rtw_ft_roam_expired(adapter, reason))
-+			pmlmepriv->ft_roam.ft_roam_on_expired = _TRUE;
-+		else
-+			pmlmepriv->ft_roam.ft_roam_on_expired = _FALSE;
-+#endif
-+		if (adapter->registrypriv.wifi_spec == 1)
-+			roam = _FALSE;
-+		else if (reason == WLAN_REASON_EXPIRATION_CHK && rtw_chk_roam_flags(adapter, RTW_ROAM_ON_EXPIRED))
-+			roam = _TRUE;
-+		else if (reason == WLAN_REASON_ACTIVE_ROAM && rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) {
-+			roam = _TRUE;
-+			roam_target = pmlmepriv->roam_network;
-+		}
-+
-+#ifdef CONFIG_RTW_80211R
-+		if (reason == WLAN_REASON_ACTIVE_ROAM && rtw_ft_chk_flags(adapter, RTW_FT_BTM_ROAM)) {
-+			roam = _TRUE;
-+			roam_target = pmlmepriv->roam_network;
-+		}
-+#endif
-+
-+		if (roam == _TRUE) {
-+			if (rtw_to_roam(adapter) > 0)
-+				rtw_dec_to_roam(adapter); /* this stadel_event is caused by roaming, decrease to_roam */
-+			else if (rtw_to_roam(adapter) == 0)
-+				rtw_set_to_roam(adapter, adapter->registrypriv.max_roaming_times);
-+		} else
-+			rtw_set_to_roam(adapter, 0);
-+#endif /* CONFIG_LAYER2_ROAMING */
-+
-+		rtw_free_uc_swdec_pending_queue(adapter);
-+
-+		rtw_free_assoc_resources(adapter, _TRUE);
-+		rtw_free_mlme_priv_ie_data(pmlmepriv);
-+
-+		rtw_indicate_disconnect(adapter, *(u16 *)pstadel->rsvd, pstadel->locally_generated);
-+
-+		_rtw_roaming(adapter, roam_target);
-+	}
-+
-+#ifdef CONFIG_AP_MODE
-+	if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) ||
-+	    check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) {
-+
-+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
-+		rtw_free_stainfo(adapter,  psta);
-+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
-+
-+		if (adapter->stapriv.asoc_sta_count == 1) { /* a sta + bc/mc_stainfo (not Ibss_stainfo) */
-+			/* rtw_indicate_disconnect(adapter); */ /* removed@20091105 */
-+			_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+			/* free old ibss network */
-+			/* pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); */
-+			pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress);
-+			if (pwlan) {
-+				pwlan->fixed = _FALSE;
-+				rtw_free_network_nolock(adapter, pwlan);
-+			}
-+			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+			/* re-create ibss */
-+			pdev_network = &(adapter->registrypriv.dev_network);
-+			pibss = adapter->registrypriv.dev_network.MacAddress;
-+
-+			_rtw_memcpy(pdev_network, &tgt_network->network, get_WLAN_BSSID_EX_sz(&tgt_network->network));
-+
-+			_rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
-+			_rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
-+
-+			rtw_update_registrypriv_dev_network(adapter);
-+
-+			rtw_generate_random_ibss(pibss);
-+
-+			if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) {
-+				set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
-+				_clr_fwstate_(pmlmepriv, WIFI_ADHOC_STATE);
-+			}
-+
-+			if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS)
-+				RTW_ERR("rtw_create_ibss_cmd FAIL\n");
-+
-+		}
-+
-+	}
-+#endif /* CONFIG_AP_MODE */
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL2);
-+exit:
-+	#ifdef CONFIG_RTS_FULL_BW
-+	rtw_set_rts_bw(adapter);
-+	#endif/*CONFIG_RTS_FULL_BW*/
-+	return;
-+}
-+
-+void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf)
-+{
-+
-+	WMMOnAssocRsp(padapter);
-+
-+
-+}
-+
-+/*
-+* rtw_join_timeout_handler - Timeout/failure handler for CMD JoinBss
-+*/
-+void rtw_join_timeout_handler(void *ctx)
-+{
-+	_adapter *adapter = (_adapter *)ctx;
-+	_irqL irqL;
-+	struct	mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+
-+#if 0
-+	if (rtw_is_drv_stopped(adapter)) {
-+		_rtw_up_sema(&pmlmepriv->assoc_terminate);
-+		return;
-+	}
-+#endif
-+
-+
-+
-+	RTW_INFO("%s, fw_state=%x\n", __FUNCTION__, get_fwstate(pmlmepriv));
-+
-+	if (RTW_CANNOT_RUN(adapter))
-+		return;
-+
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+#ifdef CONFIG_LAYER2_ROAMING
-+	if (rtw_to_roam(adapter) > 0) { /* join timeout caused by roaming */
-+		while (1) {
-+			rtw_dec_to_roam(adapter);
-+			if (rtw_to_roam(adapter) != 0) { /* try another */
-+				int do_join_r;
-+				RTW_INFO("%s try another roaming\n", __FUNCTION__);
-+				do_join_r = rtw_do_join(adapter);
-+				if (_SUCCESS != do_join_r) {
-+					RTW_INFO("%s roaming do_join return %d\n", __FUNCTION__ , do_join_r);
-+					continue;
-+				}
-+				break;
-+			} else {
-+				RTW_INFO("%s We've try roaming but fail\n", __FUNCTION__);
-+#ifdef CONFIG_RTW_80211R
-+				rtw_ft_clr_flags(adapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN);
-+				rtw_ft_reset_status(adapter);
-+#endif
-+				rtw_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE);
-+				break;
-+			}
-+		}
-+
-+	} else
-+#endif
-+	{
-+		rtw_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE);
-+		free_scanqueue(pmlmepriv);/* ??? */
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+		/* indicate disconnect for the case that join_timeout and check_fwstate != FW_LINKED */
-+		rtw_cfg80211_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE);
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+	}
-+
-+	pmlmepriv->join_status = 0; /* reset */
-+
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+
-+#ifdef CONFIG_DRVEXT_MODULE_WSC
-+	drvext_assoc_fail_indicate(&adapter->drvextpriv);
-+#endif
-+
-+
-+
-+}
-+
-+/*
-+* rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey
-+* @adapter: pointer to _adapter structure
-+*/
-+void rtw_scan_timeout_handler(void *ctx)
-+{
-+	_adapter *adapter = (_adapter *)ctx;
-+	_irqL irqL;
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	RTW_INFO(FUNC_ADPT_FMT" fw_state=%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+	_clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY);
-+
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	rtw_cfg80211_surveydone_event_callback(adapter);
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+	rtw_indicate_scan_done(adapter, _TRUE);
-+
-+#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211)
-+	rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _TRUE);
-+#endif
-+}
-+
-+void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason)
-+{
-+#if defined(CONFIG_RTW_MESH) && defined(CONFIG_DFS_MASTER)
-+#if CONFIG_RTW_MESH_OFFCH_CAND 
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+#endif
-+#endif
-+	u8 u_ch;
-+	u32 interval_ms = 0xffffffff; /* 0xffffffff: special value to make min() works well, also means no auto scan */
-+
-+	*reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED;
-+	rtw_mi_get_ch_setting_union(adapter, &u_ch, NULL, NULL);
-+
-+	if (hal_chk_bw_cap(adapter, BW_CAP_40M)
-+		&& is_client_associated_to_ap(adapter) == _TRUE
-+		&& u_ch >= 1 && u_ch <= 14
-+		&& adapter->registrypriv.wifi_spec
-+		/* TODO: AP Connected is 40MHz capability? */
-+	) {
-+		interval_ms = rtw_min(interval_ms, 60 * 1000);
-+		*reason |= RTW_AUTO_SCAN_REASON_2040_BSS;
-+	}
-+
-+#ifdef CONFIG_RTW_MESH
-+	#if CONFIG_RTW_MESH_OFFCH_CAND
-+	if (adapter->mesh_cfg.peer_sel_policy.offch_find_int_ms
-+		&& rtw_mesh_offch_candidate_accepted(adapter)
-+		#ifdef CONFIG_DFS_MASTER
-+		&& (!rfctl->radar_detect_ch || (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl)))
-+		#endif
-+	) {
-+		interval_ms = rtw_min(interval_ms, adapter->mesh_cfg.peer_sel_policy.offch_find_int_ms);
-+		*reason |= RTW_AUTO_SCAN_REASON_MESH_OFFCH_CAND;
-+	}
-+	#endif
-+#endif /* CONFIG_RTW_MESH */
-+
-+	if (interval_ms == 0xffffffff)
-+		interval_ms = 0;
-+
-+	rtw_mlme_set_auto_scan_int(adapter, interval_ms);
-+	return;
-+}
-+
-+void rtw_drv_scan_by_self(_adapter *padapter, u8 reason)
-+{
-+	struct sitesurvey_parm parm;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	int i;
-+#if 1
-+	u8 ssc_chk;
-+
-+	ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
-+	if( ssc_chk == SS_DENY_BUSY_TRAFFIC) {
-+		#ifdef CONFIG_LAYER2_ROAMING
-+		if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE)
-+			RTW_INFO(FUNC_ADPT_FMT" need to roam, don't care BusyTraffic\n", FUNC_ADPT_ARG(padapter));
-+		else
-+		#endif
-+		{
-+			RTW_INFO(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter));
-+			goto exit;
-+		}
-+	}
-+	else if (ssc_chk != SS_ALLOW)
-+		goto exit;
-+
-+	if (!rtw_is_adapter_up(padapter))
-+		goto exit;
-+#else
-+	if (rtw_is_scan_deny(padapter))
-+		goto exit;
-+
-+	if (!rtw_is_adapter_up(padapter))
-+		goto exit;
-+
-+	if (rtw_mi_busy_traffic_check(padapter)) {
-+#ifdef CONFIG_LAYER2_ROAMING
-+		if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE) {
-+			RTW_INFO("need to roam, don't care BusyTraffic\n");
-+		} else
-+#endif
-+		{
-+			RTW_INFO(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter));
-+			goto exit;
-+		}
-+	}
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
-+		RTW_INFO(FUNC_ADPT_FMT" WIFI_AP_STATE && WIFI_UNDER_WPS\n", FUNC_ADPT_ARG(padapter));
-+		goto exit;
-+	}
-+	if (check_fwstate(pmlmepriv, (WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING)) == _TRUE) {
-+		RTW_INFO(FUNC_ADPT_FMT" WIFI_UNDER_SURVEY|WIFI_UNDER_LINKING\n", FUNC_ADPT_ARG(padapter));
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_buddy_check_fwstate(padapter, (WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING | WIFI_UNDER_WPS))) {
-+		RTW_INFO(FUNC_ADPT_FMT", but buddy_intf is under scanning or linking or wps_phase\n", FUNC_ADPT_ARG(padapter));
-+		goto exit;
-+	}
-+#endif
-+#endif
-+
-+	RTW_INFO(FUNC_ADPT_FMT" reason:0x%02x\n", FUNC_ADPT_ARG(padapter), reason);
-+
-+	/* only for 20/40 BSS */
-+	if (reason == RTW_AUTO_SCAN_REASON_2040_BSS) {
-+		rtw_init_sitesurvey_parm(padapter, &parm);
-+		for (i=0;i<14;i++) {
-+			parm.ch[i].hw_value = i + 1;
-+			parm.ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN;
-+		}
-+		parm.ch_num = 14;
-+		rtw_set_802_11_bssid_list_scan(padapter, &parm);
-+		goto exit;
-+	}
-+
-+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
-+	if ((reason == RTW_AUTO_SCAN_REASON_ROAM) 
-+		&& (rtw_roam_nb_scan_list_set(padapter, &parm)))
-+		goto exit;
-+#endif
-+
-+	rtw_set_802_11_bssid_list_scan(padapter, NULL);
-+exit:
-+	return;
-+}
-+
-+static void rtw_auto_scan_handler(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	u8 reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED;
-+
-+	rtw_mlme_reset_auto_scan_int(padapter, &reason);
-+
-+#ifdef CONFIG_P2P
-+	if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE))
-+		goto exit;
-+#endif
-+
-+#ifdef CONFIG_TDLS
-+	if (padapter->tdlsinfo.link_established == _TRUE)
-+		goto exit;
-+#endif
-+
-+	if (pmlmepriv->auto_scan_int_ms == 0
-+	    || rtw_get_passing_time_ms(pmlmepriv->scan_start_time) < pmlmepriv->auto_scan_int_ms)
-+		goto exit;
-+
-+	rtw_drv_scan_by_self(padapter, reason);
-+
-+exit:
-+	return;
-+}
-+static u8 is_drv_in_lps(_adapter *adapter)
-+{
-+	u8 is_in_lps = _FALSE;
-+
-+	#ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/
-+	if ((adapter_to_pwrctl(adapter)->bFwCurrentInPSMode == _TRUE)
-+	#ifdef CONFIG_BT_COEXIST
-+		&& (rtw_btcoex_IsBtControlLps(adapter) == _FALSE)
-+	#endif
-+		)
-+		is_in_lps = _TRUE;
-+	#endif /* CONFIG_LPS_LCLK_WD_TIMER*/
-+	return is_in_lps;
-+}
-+void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter)
-+{
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+
-+	if (adapter->net_closed == _TRUE)
-+		return;
-+	#ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/
-+	if (is_drv_in_lps(adapter)) {
-+		u8 bEnterPS;
-+
-+		linked_status_chk(adapter, 1);
-+
-+		bEnterPS = traffic_status_watchdog(adapter, 1);
-+		if (bEnterPS) {
-+			/* rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_ENTER, 0); */
-+			rtw_hal_dm_watchdog_in_lps(adapter);
-+		} else {
-+			/* call rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0) in traffic_status_watchdog() */
-+		}
-+	}
-+	#endif /* CONFIG_LPS_LCLK_WD_TIMER	*/
-+
-+	/* auto site survey */
-+	rtw_auto_scan_handler(adapter);
-+
-+#ifdef CONFIG_AP_MODE
-+	if (MLME_IS_AP(adapter)|| MLME_IS_MESH(adapter)) {
-+		#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-+		expire_timeout_chk(adapter);
-+		#endif /* !CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
-+
-+		#ifdef CONFIG_BMC_TX_RATE_SELECT
-+		rtw_update_bmc_sta_tx_rate(adapter);
-+		#endif /*CONFIG_BMC_TX_RATE_SELECT*/
-+	}
-+#endif /*CONFIG_AP_MODE*/
-+
-+
-+#ifdef CONFIG_BR_EXT
-+if (!adapter_use_wds(adapter)) {
-+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
-+	rcu_read_lock();
-+#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) */
-+
-+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
-+	if (adapter->pnetdev->br_port
-+#else	/* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
-+	if (rcu_dereference(adapter->pnetdev->rx_handler_data)
-+#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
-+		&& (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE)) {
-+		/* expire NAT2.5 entry */
-+		void nat25_db_expire(_adapter *priv);
-+		nat25_db_expire(adapter);
-+
-+		if (adapter->pppoe_connection_in_progress > 0)
-+			adapter->pppoe_connection_in_progress--;
-+		/* due to rtw_dynamic_check_timer_handlder() is called every 2 seconds */
-+		if (adapter->pppoe_connection_in_progress > 0)
-+			adapter->pppoe_connection_in_progress--;
-+	}
-+
-+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
-+	rcu_read_unlock();
-+#endif /* (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) */
-+}
-+#endif /* CONFIG_BR_EXT */
-+
-+}
-+
-+/*TP_avg(t) = (1/10) * TP_avg(t-1) + (9/10) * TP(t) MBps*/
-+static void collect_sta_traffic_statistics(_adapter *adapter)
-+{
-+	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
-+	struct sta_info *sta;
-+	u64 curr_tx_bytes = 0, curr_rx_bytes = 0;
-+	u32 curr_tx_mbytes = 0, curr_rx_mbytes = 0;
-+	int i;
-+
-+	for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
-+		sta = macid_ctl->sta[i];
-+		if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) {
-+			if (sta->sta_stats.last_tx_bytes > sta->sta_stats.tx_bytes)
-+				sta->sta_stats.last_tx_bytes =  sta->sta_stats.tx_bytes;
-+			if (sta->sta_stats.last_rx_bytes > sta->sta_stats.rx_bytes)
-+				sta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes;
-+			if (sta->sta_stats.last_rx_bc_bytes > sta->sta_stats.rx_bc_bytes)
-+				sta->sta_stats.last_rx_bc_bytes = sta->sta_stats.rx_bc_bytes;
-+			if (sta->sta_stats.last_rx_mc_bytes > sta->sta_stats.rx_mc_bytes)
-+				sta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes;
-+
-+			curr_tx_bytes = sta->sta_stats.tx_bytes - sta->sta_stats.last_tx_bytes;
-+			curr_rx_bytes = sta->sta_stats.rx_bytes - sta->sta_stats.last_rx_bytes;
-+			sta->sta_stats.tx_tp_kbits = (curr_tx_bytes * 8 / 2) >> 10;/*Kbps*/
-+			sta->sta_stats.rx_tp_kbits = (curr_rx_bytes * 8 / 2) >> 10;/*Kbps*/
-+
-+			sta->sta_stats.smooth_tx_tp_kbits = (sta->sta_stats.smooth_tx_tp_kbits * 6 / 10) + (sta->sta_stats.tx_tp_kbits * 4 / 10);/*Kbps*/
-+			sta->sta_stats.smooth_rx_tp_kbits = (sta->sta_stats.smooth_rx_tp_kbits * 6 / 10) + (sta->sta_stats.rx_tp_kbits * 4 / 10);/*Kbps*/
-+
-+			curr_tx_mbytes = (curr_tx_bytes / 2) >> 20;/*MBps*/
-+			curr_rx_mbytes = (curr_rx_bytes / 2) >> 20;/*MBps*/
-+
-+			sta->cmn.tx_moving_average_tp =
-+				(sta->cmn.tx_moving_average_tp / 10) + (curr_tx_mbytes * 9 / 10); /*MBps*/
-+
-+			sta->cmn.rx_moving_average_tp =
-+				(sta->cmn.rx_moving_average_tp / 10) + (curr_rx_mbytes * 9 /10); /*MBps*/
-+
-+			rtw_collect_bcn_info(sta->padapter);
-+
-+			if (adapter->bsta_tp_dump)
-+				dump_sta_traffic(RTW_DBGDUMP, adapter, sta);
-+
-+			sta->sta_stats.last_tx_bytes = sta->sta_stats.tx_bytes;
-+			sta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes;
-+			sta->sta_stats.last_rx_bc_bytes = sta->sta_stats.rx_bc_bytes;
-+			sta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes;
-+		}
-+	}
-+}
-+
-+void rtw_sta_traffic_info(void *sel, _adapter *adapter)
-+{
-+	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
-+	struct sta_info *sta;
-+	int i;
-+
-+	for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
-+		sta = macid_ctl->sta[i];
-+		if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr))
-+			dump_sta_traffic(sel, adapter, sta);
-+	}
-+}
-+
-+/*#define DBG_TRAFFIC_STATISTIC*/
-+static void collect_traffic_statistics(_adapter *padapter)
-+{
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
-+
-+	/*_rtw_memset(&pdvobjpriv->traffic_stat, 0, sizeof(struct rtw_traffic_statistics));*/
-+
-+	/* Tx bytes reset*/
-+	pdvobjpriv->traffic_stat.tx_bytes = 0;
-+	pdvobjpriv->traffic_stat.tx_pkts = 0;
-+	pdvobjpriv->traffic_stat.tx_drop = 0;
-+
-+	/* Rx bytes reset*/
-+	pdvobjpriv->traffic_stat.rx_bytes = 0;
-+	pdvobjpriv->traffic_stat.rx_pkts = 0;
-+	pdvobjpriv->traffic_stat.rx_drop = 0;
-+
-+	rtw_mi_traffic_statistics(padapter);
-+
-+	/* Calculate throughput in last interval */
-+	pdvobjpriv->traffic_stat.cur_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes - pdvobjpriv->traffic_stat.last_tx_bytes;
-+	pdvobjpriv->traffic_stat.cur_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes - pdvobjpriv->traffic_stat.last_rx_bytes;
-+	pdvobjpriv->traffic_stat.last_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes;
-+	pdvobjpriv->traffic_stat.last_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes;
-+
-+	pdvobjpriv->traffic_stat.cur_tx_tp = (u32)(pdvobjpriv->traffic_stat.cur_tx_bytes * 8 / 2 / 1024 / 1024);/*Mbps*/
-+	pdvobjpriv->traffic_stat.cur_rx_tp = (u32)(pdvobjpriv->traffic_stat.cur_rx_bytes * 8 / 2 / 1024 / 1024);/*Mbps*/
-+
-+	#ifdef DBG_TRAFFIC_STATISTIC
-+	RTW_INFO("\n========================\n");
-+	RTW_INFO("cur_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.cur_tx_bytes);
-+	RTW_INFO("cur_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.cur_rx_bytes);
-+
-+	RTW_INFO("last_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_tx_bytes);
-+	RTW_INFO("last_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_rx_bytes);
-+
-+	RTW_INFO("cur_tx_tp:%d (Mbps)\n", pdvobjpriv->traffic_stat.cur_tx_tp);
-+	RTW_INFO("cur_rx_tp:%d (Mbps)\n", pdvobjpriv->traffic_stat.cur_rx_tp);
-+	#endif
-+
-+#ifdef CONFIG_RTW_NAPI
-+#ifdef CONFIG_RTW_NAPI_DYNAMIC
-+	dynamic_napi_th_chk (padapter);
-+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
-+#endif
-+	
-+}
-+
-+void rtw_dynamic_check_timer_handlder(void *ctx)
-+{
-+	struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx;
-+	_adapter *adapter = dvobj_get_primary_adapter(pdvobj);
-+
-+	if (!adapter)
-+		goto exit;
-+
-+#if (MP_DRIVER == 1)
-+	if (adapter->registrypriv.mp_mode == 1 && adapter->mppriv.mp_dm == 0) { /* for MP ODM dynamic Tx power tracking */
-+		/* RTW_INFO("%s mp_dm =0 return\n", __func__); */
-+		goto exit;
-+	}
-+#endif
-+
-+	if (!rtw_is_hw_init_completed(adapter))
-+		goto exit;
-+
-+	if (RTW_CANNOT_RUN(adapter))
-+		goto exit;
-+
-+	collect_traffic_statistics(adapter);
-+	collect_sta_traffic_statistics(adapter);
-+	rtw_mi_dynamic_check_timer_handlder(adapter);
-+
-+	if (!is_drv_in_lps(adapter))
-+		rtw_dynamic_chk_wk_cmd(adapter);
-+
-+exit:
-+	_set_timer(&pdvobj->dynamic_chk_timer, 2000);
-+}
-+
-+
-+#ifdef CONFIG_SET_SCAN_DENY_TIMER
-+inline bool rtw_is_scan_deny(_adapter *adapter)
-+{
-+	struct mlme_priv *mlmepriv = &adapter->mlmepriv;
-+	return (ATOMIC_READ(&mlmepriv->set_scan_deny) != 0) ? _TRUE : _FALSE;
-+}
-+
-+inline void rtw_clear_scan_deny(_adapter *adapter)
-+{
-+	struct mlme_priv *mlmepriv = &adapter->mlmepriv;
-+	ATOMIC_SET(&mlmepriv->set_scan_deny, 0);
-+	if (0)
-+		RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
-+}
-+
-+void rtw_set_scan_deny_timer_hdl(void *ctx)
-+{
-+	_adapter *adapter = (_adapter *)ctx;
-+
-+	rtw_clear_scan_deny(adapter);
-+}
-+void rtw_set_scan_deny(_adapter *adapter, u32 ms)
-+{
-+	struct mlme_priv *mlmepriv = &adapter->mlmepriv;
-+	if (0)
-+		RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
-+	ATOMIC_SET(&mlmepriv->set_scan_deny, 1);
-+	_set_timer(&mlmepriv->set_scan_deny_timer, ms);
-+}
-+#endif
-+
-+#ifdef CONFIG_LAYER2_ROAMING
-+/*
-+* Select a new roaming candidate from the original @param candidate and @param competitor
-+* @return _TRUE: candidate is updated
-+* @return _FALSE: candidate is not updated
-+*/
-+static int rtw_check_roaming_candidate(struct mlme_priv *mlme
-+	, struct wlan_network **candidate, struct wlan_network *competitor)
-+{
-+	int updated = _FALSE;
-+	_adapter *adapter = container_of(mlme, _adapter, mlmepriv);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	RT_CHANNEL_INFO *chset = rfctl->channel_set;
-+	u8 ch = competitor->network.Configuration.DSConfig;
-+
-+	if (rtw_chset_search_ch(chset, ch) < 0)
-+		goto exit;
-+	if (IS_DFS_SLAVE_WITH_RD(rfctl)
-+		&& !rtw_rfctl_dfs_domain_unknown(rfctl)
-+		&& rtw_chset_is_ch_non_ocp(chset, ch))
-+		goto exit;
-+
-+#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
-+	if (rtw_rson_isupdate_roamcan(mlme, candidate, competitor))
-+		goto  update;
-+	goto exit;
-+#endif
-+
-+	if (is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE)
-+		goto exit;
-+
-+	if (rtw_is_desired_network(adapter, competitor) == _FALSE)
-+		goto exit;
-+
-+#ifdef CONFIG_LAYER2_ROAMING
-+	if (mlme->need_to_roam == _FALSE)
-+		goto exit;
-+#endif
-+
-+	RTW_INFO("roam candidate:%s %s("MAC_FMT", ch%3u) rssi:%d dBm, age:%5d\n",
-+		 (competitor == mlme->cur_network_scanned) ? "*" : " " ,
-+		 competitor->network.Ssid.Ssid,
-+		 MAC_ARG(competitor->network.MacAddress),
-+		 competitor->network.Configuration.DSConfig,
-+		 (int)competitor->network.Rssi,
-+		 rtw_get_passing_time_ms(competitor->last_scanned)
-+		);
-+
-+	/* got specific addr to roam */
-+	if (!is_zero_mac_addr(mlme->roam_tgt_addr)) {
-+		if (_rtw_memcmp(mlme->roam_tgt_addr, competitor->network.MacAddress, ETH_ALEN) == _TRUE)
-+			goto update;
-+		else
-+			goto exit;
-+	}
-+
-+#ifdef CONFIG_RTW_80211R
-+	if (rtw_ft_chk_flags(adapter, RTW_FT_PEER_EN)) {
-+		if (rtw_ft_chk_roaming_candidate(adapter, competitor) == _FALSE)
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_RTW_WNM
-+	if (rtw_wnm_btm_diff_bss(adapter) && 
-+		rtw_wnm_btm_roam_candidate(adapter, competitor)) {
-+		goto update;
-+	}	
-+#endif
-+#endif
-+
-+#if 1
-+	if (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms)
-+		goto exit;
-+
-+	if (competitor->network.Rssi - mlme->cur_network_scanned->network.Rssi < mlme->roam_rssi_diff_th)
-+		goto exit;
-+
-+	if (*candidate != NULL && (*candidate)->network.Rssi >= competitor->network.Rssi)
-+		goto exit;
-+#else
-+	goto exit;
-+#endif
-+
-+update:
-+	*candidate = competitor;
-+	updated = _TRUE;
-+
-+exit:
-+	return updated;
-+}
-+
-+int rtw_select_roaming_candidate(struct mlme_priv *mlme)
-+{
-+	_irqL	irqL;
-+	int ret = _FAIL;
-+	_list	*phead;
-+	_adapter *adapter;
-+	_queue	*queue	= &(mlme->scanned_queue);
-+	struct	wlan_network	*pnetwork = NULL;
-+	struct	wlan_network	*candidate = NULL;
-+
-+	if (mlme->cur_network_scanned == NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	_enter_critical_bh(&(mlme->scanned_queue.lock), &irqL);
-+	phead = get_list_head(queue);
-+	adapter = (_adapter *)mlme->nic_hdl;
-+
-+	mlme->pscanned = get_next(phead);
-+
-+	while (!rtw_end_of_queue_search(phead, mlme->pscanned)) {
-+
-+		pnetwork = LIST_CONTAINOR(mlme->pscanned, struct wlan_network, list);
-+		if (pnetwork == NULL) {
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+
-+		mlme->pscanned = get_next(mlme->pscanned);
-+
-+		if (0)
-+			RTW_INFO("%s("MAC_FMT", ch%u) rssi:%d\n"
-+				 , pnetwork->network.Ssid.Ssid
-+				 , MAC_ARG(pnetwork->network.MacAddress)
-+				 , pnetwork->network.Configuration.DSConfig
-+				 , (int)pnetwork->network.Rssi);
-+
-+		rtw_check_roaming_candidate(mlme, &candidate, pnetwork);
-+
-+	}
-+
-+	if (candidate == NULL) {
-+	/*	if parent note lost the path to root and there is no other cadidate, report disconnection	*/
-+#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
-+		struct rtw_rson_struct  rson_curr;
-+		u8 rson_score;
-+
-+		rtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr);
-+		rson_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi);
-+		if (check_fwstate(mlme, WIFI_ASOC_STATE)
-+			&& ((rson_score == RTW_RSON_SCORE_NOTCNNT)
-+			|| (rson_score == RTW_RSON_SCORE_NOTSUP)))
-+			receive_disconnect(adapter, mlme->cur_network_scanned->network.MacAddress
-+								, WLAN_REASON_EXPIRATION_CHK, _FALSE);
-+#endif
-+		RTW_INFO("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__);
-+		ret = _FAIL;
-+		goto exit;
-+	} else {
-+#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
-+		struct rtw_rson_struct  rson_curr;
-+		u8 rson_score;
-+
-+		rtw_get_rson_struct(&(candidate->network), &rson_curr);
-+		rson_score = rtw_cal_rson_score(&rson_curr, candidate->network.Rssi);
-+		RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u) rson_score:%d\n", __FUNCTION__,
-+			candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),
-+			 candidate->network.Configuration.DSConfig, rson_score);
-+#else
-+		RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__,
-+			candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),
-+			 candidate->network.Configuration.DSConfig);
-+#endif
-+		mlme->roam_network = candidate;
-+
-+		if (_rtw_memcmp(candidate->network.MacAddress, mlme->roam_tgt_addr, ETH_ALEN) == _TRUE)
-+			_rtw_memset(mlme->roam_tgt_addr, 0, ETH_ALEN);
-+	}
-+
-+	ret = _SUCCESS;
-+exit:
-+	_exit_critical_bh(&(mlme->scanned_queue.lock), &irqL);
-+
-+	return ret;
-+}
-+#endif /* CONFIG_LAYER2_ROAMING */
-+
-+/*
-+* Select a new join candidate from the original @param candidate and @param competitor
-+* @return _TRUE: candidate is updated
-+* @return _FALSE: candidate is not updated
-+*/
-+static int rtw_check_join_candidate(struct mlme_priv *mlme
-+	    , struct wlan_network **candidate, struct wlan_network *competitor)
-+{
-+	int updated = _FALSE;
-+	_adapter *adapter = container_of(mlme, _adapter, mlmepriv);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	RT_CHANNEL_INFO *chset = rfctl->channel_set;
-+	u8 ch = competitor->network.Configuration.DSConfig;
-+
-+	if (rtw_chset_search_ch(chset, ch) < 0)
-+		goto exit;
-+	if (IS_DFS_SLAVE_WITH_RD(rfctl)
-+		&& !rtw_rfctl_dfs_domain_unknown(rfctl)
-+		&& rtw_chset_is_ch_non_ocp(chset, ch))
-+		goto exit;
-+
-+#if defined(CONFIG_RTW_REPEATER_SON) &&  (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
-+	s16 rson_score;
-+	struct rtw_rson_struct  rson_data;
-+
-+	if (rtw_rson_choose(candidate, competitor)) {
-+		*candidate = competitor;
-+		rtw_get_rson_struct(&((*candidate)->network), &rson_data);
-+		rson_score = rtw_cal_rson_score(&rson_data, (*candidate)->network.Rssi);
-+		RTW_INFO("[assoc_ssid:%s] new candidate: %s("MAC_FMT", ch%u) rson_score:%d\n",
-+			 mlme->assoc_ssid.Ssid,
-+			 (*candidate)->network.Ssid.Ssid,
-+			 MAC_ARG((*candidate)->network.MacAddress),
-+			 (*candidate)->network.Configuration.DSConfig,
-+			 rson_score);
-+		return _TRUE;
-+	}
-+	return _FALSE;
-+#endif
-+
-+	/* check bssid, if needed */
-+	if (mlme->assoc_by_bssid == _TRUE) {
-+		if (_rtw_memcmp(competitor->network.MacAddress, mlme->assoc_bssid, ETH_ALEN) == _FALSE)
-+			goto exit;
-+	}
-+
-+	/* check ssid, if needed */
-+	if (mlme->assoc_ssid.Ssid[0] && mlme->assoc_ssid.SsidLength) {
-+		if (competitor->network.Ssid.SsidLength != mlme->assoc_ssid.SsidLength
-+		    || _rtw_memcmp(competitor->network.Ssid.Ssid, mlme->assoc_ssid.Ssid, mlme->assoc_ssid.SsidLength) == _FALSE
-+		   )
-+			goto exit;
-+	}
-+
-+	if (rtw_is_desired_network(adapter, competitor)  == _FALSE)
-+		goto exit;
-+
-+#ifdef CONFIG_LAYER2_ROAMING
-+	if (rtw_to_roam(adapter) > 0) {
-+		if (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms
-+		    || is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE
-+		   )
-+			goto exit;
-+	}
-+#endif
-+
-+	if (*candidate == NULL || (*candidate)->network.Rssi < competitor->network.Rssi) {
-+		*candidate = competitor;
-+		updated = _TRUE;
-+	}
-+
-+	if (updated) {
-+		RTW_INFO("[by_bssid:%u][assoc_ssid:%s][to_roam:%u] "
-+			 "new candidate: %s("MAC_FMT", ch%u) rssi:%d dBm\n",
-+			 mlme->assoc_by_bssid,
-+			 mlme->assoc_ssid.Ssid,
-+			 rtw_to_roam(adapter),
-+			 (*candidate)->network.Ssid.Ssid,
-+			 MAC_ARG((*candidate)->network.MacAddress),
-+			 (*candidate)->network.Configuration.DSConfig,
-+			 (int)(*candidate)->network.Rssi
-+			);
-+	}
-+
-+exit:
-+	return updated;
-+}
-+
-+/*
-+Calling context:
-+The caller of the sub-routine will be in critical section...
-+
-+The caller must hold the following spinlock
-+
-+pmlmepriv->lock
-+
-+
-+*/
-+
-+int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv)
-+{
-+	_irqL	irqL;
-+	int ret;
-+	_list	*phead;
-+	_adapter *adapter;
-+	_queue	*queue	= &(pmlmepriv->scanned_queue);
-+	struct	wlan_network	*pnetwork = NULL;
-+	struct	wlan_network	*candidate = NULL;
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	u8		bSupportAntDiv = _FALSE;
-+#endif
-+
-+	adapter = (_adapter *)pmlmepriv->nic_hdl;
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+#ifdef CONFIG_LAYER2_ROAMING
-+	if (pmlmepriv->roam_network) {
-+		candidate = pmlmepriv->roam_network;
-+		pmlmepriv->roam_network = NULL;
-+		goto candidate_exist;
-+	}
-+#endif
-+
-+	phead = get_list_head(queue);
-+	pmlmepriv->pscanned = get_next(phead);
-+
-+	while (!rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) {
-+
-+		pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
-+		if (pnetwork == NULL) {
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+
-+		pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
-+
-+		if (0)
-+			RTW_INFO("%s("MAC_FMT", ch%u) rssi:%d\n"
-+				 , pnetwork->network.Ssid.Ssid
-+				 , MAC_ARG(pnetwork->network.MacAddress)
-+				 , pnetwork->network.Configuration.DSConfig
-+				 , (int)pnetwork->network.Rssi);
-+
-+		rtw_check_join_candidate(pmlmepriv, &candidate, pnetwork);
-+
-+	}
-+
-+	if (candidate == NULL) {
-+		RTW_INFO("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__);
-+#ifdef CONFIG_WOWLAN
-+		_clr_fwstate_(pmlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_LINKING);
-+#endif
-+		ret = _FAIL;
-+		goto exit;
-+	} else {
-+		RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__,
-+			candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),
-+			 candidate->network.Configuration.DSConfig);
-+		goto candidate_exist;
-+	}
-+
-+candidate_exist:
-+
-+	/* check for situation of  WIFI_ASOC_STATE */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+		RTW_INFO("%s: WIFI_ASOC_STATE while ask_for_joinbss!!!\n", __FUNCTION__);
-+
-+#if 0 /* for WPA/WPA2 authentication, wpa_supplicant will expect authentication from AP, it is needed to reconnect AP... */
-+		if (is_same_network(&pmlmepriv->cur_network.network, &candidate->network)) {
-+			RTW_INFO("%s: WIFI_ASOC_STATE and is same network, it needn't join again\n", __FUNCTION__);
-+
-+			rtw_indicate_connect(adapter);/* rtw_indicate_connect again */
-+
-+			ret = 2;
-+			goto exit;
-+		} else
-+#endif
-+		{
-+			rtw_disassoc_cmd(adapter, 0, 0);
-+			rtw_indicate_disconnect(adapter, 0, _FALSE);
-+			rtw_free_assoc_resources_cmd(adapter, _TRUE, 0);
-+		}
-+	}
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	rtw_hal_get_def_var(adapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv));
-+	if (_TRUE == bSupportAntDiv) {
-+		u8 CurrentAntenna;
-+		rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(CurrentAntenna), NULL);
-+		RTW_INFO("#### Opt_Ant_(%s) , cur_Ant(%s)\n",
-+			(MAIN_ANT == candidate->network.PhyInfo.Optimum_antenna) ? "MAIN_ANT" : "AUX_ANT",
-+			 (MAIN_ANT == CurrentAntenna) ? "MAIN_ANT" : "AUX_ANT"
-+			);
-+	}
-+#endif
-+	set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
-+	ret = rtw_joinbss_cmd(adapter, candidate);
-+
-+exit:
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+
-+	return ret;
-+}
-+
-+sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv)
-+{
-+	struct	cmd_obj *pcmd;
-+	struct	setauth_parm *psetauthparm;
-+	struct	cmd_priv	*pcmdpriv = &(adapter->cmdpriv);
-+	sint		res = _SUCCESS;
-+
-+
-+	pcmd = (struct	cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
-+	if (pcmd == NULL) {
-+		res = _FAIL; /* try again */
-+		goto exit;
-+	}
-+
-+	psetauthparm = (struct setauth_parm *)rtw_zmalloc(sizeof(struct setauth_parm));
-+	if (psetauthparm == NULL) {
-+		rtw_mfree((unsigned char *)pcmd, sizeof(struct	cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	_rtw_memset(psetauthparm, 0, sizeof(struct setauth_parm));
-+	psetauthparm->mode = (unsigned char)psecuritypriv->dot11AuthAlgrthm;
-+
-+	pcmd->cmdcode = CMD_SET_AUTH;
-+	pcmd->parmbuf = (unsigned char *)psetauthparm;
-+	pcmd->cmdsz = (sizeof(struct setauth_parm));
-+	pcmd->rsp = NULL;
-+	pcmd->rspsz = 0;
-+
-+
-+	_rtw_init_listhead(&pcmd->list);
-+
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, pcmd);
-+
-+exit:
-+
-+
-+	return res;
-+
-+}
-+
-+
-+sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint keyid, u8 set_tx, bool enqueue)
-+{
-+	u8	keylen;
-+	struct cmd_obj		*pcmd;
-+	struct setkey_parm	*psetkeyparm;
-+	struct cmd_priv		*pcmdpriv = &(adapter->cmdpriv);
-+	sint	res = _SUCCESS;
-+
-+
-+	psetkeyparm = (struct setkey_parm *)rtw_zmalloc(sizeof(struct setkey_parm));
-+	if (psetkeyparm == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	_rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm));
-+
-+	if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {
-+		psetkeyparm->algorithm = (unsigned char)psecuritypriv->dot118021XGrpPrivacy;
-+	} else {
-+		psetkeyparm->algorithm = (u8)psecuritypriv->dot11PrivacyAlgrthm;
-+
-+	}
-+	psetkeyparm->keyid = (u8)keyid;/* 0~3 */
-+	psetkeyparm->set_tx = set_tx;
-+	if (is_wep_enc(psetkeyparm->algorithm))
-+		adapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid);
-+
-+	RTW_INFO("==> rtw_set_key algorithm(%x),keyid(%x),key_mask(%x)\n", psetkeyparm->algorithm, psetkeyparm->keyid, adapter->securitypriv.key_mask);
-+
-+	switch (psetkeyparm->algorithm) {
-+
-+	case _WEP40_:
-+		keylen = 5;
-+		_rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen);
-+		break;
-+	case _WEP104_:
-+		keylen = 13;
-+		_rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen);
-+		break;
-+	case _TKIP_:
-+		keylen = 16;
-+		_rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen);
-+		break;
-+	case _AES_:
-+	case _GCMP_:
-+		keylen = 16;
-+		_rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen);
-+		break;
-+	case _GCMP_256_:
-+	case _CCMP_256_:
-+		keylen = 32;
-+		_rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen);
-+		break;
-+	default:
-+		res = _FAIL;
-+		rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm));
-+		goto exit;
-+	}
-+
-+
-+	if (enqueue) {
-+		pcmd = (struct	cmd_obj *)rtw_zmalloc(sizeof(struct	cmd_obj));
-+		if (pcmd == NULL) {
-+			rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm));
-+			res = _FAIL; /* try again */
-+			goto exit;
-+		}
-+
-+		pcmd->cmdcode =CMD_SET_KEY;
-+		pcmd->parmbuf = (u8 *)psetkeyparm;
-+		pcmd->cmdsz = (sizeof(struct setkey_parm));
-+		pcmd->rsp = NULL;
-+		pcmd->rspsz = 0;
-+
-+		_rtw_init_listhead(&pcmd->list);
-+
-+		/* _rtw_init_sema(&(pcmd->cmd_sem), 0); */
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, pcmd);
-+	} else {
-+		setkey_hdl(adapter, (u8 *)psetkeyparm);
-+		rtw_mfree((u8 *) psetkeyparm, sizeof(struct setkey_parm));
-+	}
-+exit:
-+	return res;
-+
-+}
-+
-+#ifdef CONFIG_WMMPS_STA
-+/*
-+ * rtw_uapsd_use_default_setting
-+ * This function is used for setting default uapsd max sp length to uapsd_max_sp_len
-+ * in qos_priv data structure from registry. In additional, it will also map default uapsd 
-+ * ac to each uapsd TID, delivery-enabled and trigger-enabled of corresponding TID. 
-+ * 
-+ * Arguments:
-+ * @padapter: _adapter pointer.
-+ *
-+ * Auther: Arvin Liu
-+ * Date: 2017/05/03
-+ */
-+void	rtw_uapsd_use_default_setting(_adapter *padapter)
-+{
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
-+	struct registry_priv		*pregistrypriv = &padapter->registrypriv;
-+
-+	if (pregistrypriv->uapsd_ac_enable != 0) {
-+		pqospriv->uapsd_max_sp_len = pregistrypriv->uapsd_max_sp_len;
-+		
-+		CLEAR_FLAGS(pqospriv->uapsd_tid);
-+		CLEAR_FLAGS(pqospriv->uapsd_tid_delivery_enabled);
-+		CLEAR_FLAGS(pqospriv->uapsd_tid_trigger_enabled);
-+
-+		/* check the uapsd setting of AC_VO from registry then map these setting to each TID if necessary  */
-+		if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_VO)) {
-+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID7);
-+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID7);
-+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID7);
-+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID6);
-+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID6);
-+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID6);
-+		}
-+
-+		/* check the uapsd setting of AC_VI from registry then map these setting to each TID if necessary  */
-+		if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_VI)) {	
-+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID5);
-+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID5);
-+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID5);
-+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID4);
-+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID4);
-+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID4);
-+		}
-+
-+		/* check the uapsd setting of AC_BK from registry then map these setting to each TID if necessary  */
-+		if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_BK)) {
-+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID2);
-+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID2);
-+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID2);
-+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID1);
-+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID1);
-+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID1);
-+		}
-+
-+		/* check the uapsd setting of AC_BE from registry then map these setting to each TID if necessary  */
-+		if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_BE)) {
-+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID3);
-+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID3);
-+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID3);
-+			SET_FLAG(pqospriv->uapsd_tid, WMM_TID0);
-+			SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID0);
-+			SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID0);
-+		}
-+
-+		RTW_INFO("[WMMPS] UAPSD MAX SP Len = 0x%02x, UAPSD TID enabled = 0x%02x\n", 
-+			pqospriv->uapsd_max_sp_len, (u8)pqospriv->uapsd_tid);
-+	}
-+
-+}
-+
-+/*
-+ * rtw_is_wmmps_mode
-+ * This function is used for checking whether Driver and an AP support uapsd function or not.
-+ * If both of them support uapsd function, it will return true. Otherwise returns false.
-+ * 
-+ * Arguments:
-+ * @padapter: _adapter pointer.
-+ *
-+ * Auther: Arvin Liu
-+ * Date: 2017/06/12
-+ */
-+bool rtw_is_wmmps_mode(_adapter *padapter) 
-+{
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct qos_priv	*pqospriv = &pmlmepriv->qospriv;
-+		
-+	if ((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT_MASK_TID_TC)  != 0))
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+#endif /* CONFIG_WMMPS_STA */
-+
-+/* adjust IEs for rtw_joinbss_cmd in WMM */
-+int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len)
-+{
-+#ifdef CONFIG_WMMPS_STA
-+	struct mlme_priv		*pmlmepriv = &adapter->mlmepriv;
-+	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
-+#endif /* CONFIG_WMMPS_STA */
-+	unsigned	int ielength = 0;
-+	unsigned int i, j;
-+	u8 qos_info = 0;
-+
-+	i = 12; /* after the fixed IE */
-+	while (i < in_len) {
-+		ielength = initial_out_len;
-+
-+		if (in_ie[i] == 0xDD && in_ie[i + 2] == 0x00 && in_ie[i + 3] == 0x50  && in_ie[i + 4] == 0xF2 && in_ie[i + 5] == 0x02 && i + 5 < in_len) { /* WMM element ID and OUI */
-+
-+			/* Append WMM IE to the last index of out_ie */
-+#if 0
-+			for (j = i; j < i + (in_ie[i + 1] + 2); j++) {
-+				out_ie[ielength] = in_ie[j];
-+				ielength++;
-+			}
-+			out_ie[initial_out_len + 8] = 0x00; /* force the QoS Info Field to be zero */
-+#endif
-+
-+			for (j = i; j < i + 9; j++) {
-+				out_ie[ielength] = in_ie[j];
-+				ielength++;
-+			}
-+			out_ie[initial_out_len + 1] = 0x07;
-+			out_ie[initial_out_len + 6] = 0x00;
-+
-+#ifdef CONFIG_WMMPS_STA
-+			switch(pqospriv->uapsd_max_sp_len) {
-+				case NO_LIMIT: 
-+					/* do nothing */
-+					break;
-+				case TWO_MSDU: 
-+					SET_FLAG(qos_info, BIT5);
-+					break;
-+				case FOUR_MSDU: 
-+					SET_FLAG(qos_info, BIT6);
-+					break;	
-+				case SIX_MSDU: 
-+					SET_FLAG(qos_info, BIT5);
-+					SET_FLAG(qos_info, BIT6);
-+					break;
-+				default:
-+					/* do nothing */
-+					break;
-+			};
-+
-+			/* check TID7 and TID6 for AC_VO to set corresponding Qos_info bit in WMM IE  */
-+			if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID7)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID6)))
-+				SET_FLAG(qos_info, WMM_IE_UAPSD_VO);
-+			/* check TID5 and TID4 for AC_VI to set corresponding Qos_info bit in WMM IE  */
-+			if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID5)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID4)))
-+				SET_FLAG(qos_info, WMM_IE_UAPSD_VI);
-+			/* check TID2 and TID1 for AC_BK to set corresponding Qos_info bit in WMM IE  */
-+			if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID2)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID1)))
-+				SET_FLAG(qos_info, WMM_IE_UAPSD_BK);
-+			/* check TID3 and TID0 for AC_BE to set corresponding Qos_info bit in WMM IE  */
-+			if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID3)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID0)))
-+				SET_FLAG(qos_info, WMM_IE_UAPSD_BE);
-+#endif /* CONFIG_WMMPS_STA */
-+			
-+			out_ie[initial_out_len + 8] = qos_info;
-+
-+			break;
-+		}
-+
-+		i += (in_ie[i + 1] + 2); /* to the next IE element */
-+	}
-+
-+	return ielength;
-+
-+}
-+
-+
-+/*
-+ * Ported from 8185: IsInPreAuthKeyList(). (Renamed from SecIsInPreAuthKeyList(), 2006-10-13.)
-+ * Added by Annie, 2006-05-07.
-+ *
-+ * Search by BSSID,
-+ * Return Value:
-+ *		-1		:if there is no pre-auth key in the  table
-+ *		>=0		:if there is pre-auth key, and   return the entry id
-+ *
-+ *   */
-+
-+static int SecIsInPMKIDList(_adapter *Adapter, u8 *bssid)
-+{
-+	struct security_priv *psecuritypriv = &Adapter->securitypriv;
-+	int i = 0;
-+
-+	do {
-+		if ((psecuritypriv->PMKIDList[i].bUsed) &&
-+		    (_rtw_memcmp(psecuritypriv->PMKIDList[i].Bssid, bssid, ETH_ALEN) == _TRUE))
-+			break;
-+		else {
-+			i++;
-+			/* continue; */
-+		}
-+
-+	} while (i < NUM_PMKID_CACHE);
-+
-+	if (i == NUM_PMKID_CACHE) {
-+		i = -1;/* Could not find. */
-+	} else {
-+		/* There is one Pre-Authentication Key for the specific BSSID. */
-+	}
-+
-+	return i;
-+
-+}
-+
-+int rtw_cached_pmkid(_adapter *Adapter, u8 *bssid)
-+{
-+	return SecIsInPMKIDList(Adapter, bssid);
-+}
-+
-+int rtw_rsn_sync_pmkid(_adapter *adapter, u8 *ie, uint ie_len, int i_ent)
-+{
-+	struct security_priv *sec = &adapter->securitypriv;
-+	struct rsne_info info;
-+	u8 gm_cs[4];
-+	int i;
-+
-+	rtw_rsne_info_parse(ie, ie_len, &info);
-+
-+	if (info.err) {
-+		RTW_WARN(FUNC_ADPT_FMT" rtw_rsne_info_parse error\n"
-+			, FUNC_ADPT_ARG(adapter));
-+		return 0;
-+	}
-+
-+	if (i_ent < 0 && info.pmkid_cnt == 0)
-+		goto exit;
-+
-+	if (info.pmkid_list == NULL)
-+		goto exit;
-+
-+	if (i_ent >= 0 && info.pmkid_cnt == 1 && _rtw_memcmp(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16)) {
-+		RTW_INFO(FUNC_ADPT_FMT" has carried the same PMKID:"KEY_FMT"\n"
-+			, FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[i_ent].PMKID));
-+		goto exit;
-+	}
-+
-+	/* bakcup group mgmt cs */
-+	if (info.gmcs)
-+		_rtw_memcpy(gm_cs, info.gmcs, 4);
-+
-+	if (info.pmkid_cnt) {
-+		RTW_INFO(FUNC_ADPT_FMT" remove original PMKID, count:%u\n"
-+			 , FUNC_ADPT_ARG(adapter), info.pmkid_cnt);
-+		for (i = 0; i < info.pmkid_cnt; i++)
-+			RTW_INFO("    "KEY_FMT"\n", KEY_ARG(info.pmkid_list + i * 16));
-+	}
-+
-+	if (i_ent >= 0) {
-+		RTW_INFO(FUNC_ADPT_FMT" append PMKID:"KEY_FMT"\n"
-+			, FUNC_ADPT_ARG(adapter), KEY_ARG(sec->PMKIDList[i_ent].PMKID));
-+
-+		info.pmkid_cnt = 1; /* update new pmkid_cnt */
-+		_rtw_memcpy(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16);
-+	} else
-+		info.pmkid_cnt = 0; /* update new pmkid_cnt */
-+
-+	RTW_PUT_LE16(info.pmkid_list - 2, info.pmkid_cnt);
-+	if (info.gmcs)
-+		_rtw_memcpy(info.pmkid_list + 16 * info.pmkid_cnt, gm_cs, 4);
-+
-+	ie_len = 1 + 1 + 2 + 4
-+		+ 2 + 4 * info.pcs_cnt
-+		+ 2 + 4 * info.akm_cnt
-+		+ 2
-+		+ 2 + 16 * info.pmkid_cnt
-+		+ (info.gmcs ? 4 : 0)
-+		;
-+	
-+	ie[1] = (u8)(ie_len - 2);
-+
-+exit:
-+	return ie_len;
-+}
-+
-+sint rtw_restruct_sec_ie(_adapter *adapter, u8 *out_ie)
-+{
-+	u8 authmode = 0x0;
-+	uint	ielength = 0;
-+	int iEntry;
-+
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct security_priv *psecuritypriv = &adapter->securitypriv;
-+	uint	ndisauthmode = psecuritypriv->ndisauthtype;
-+
-+	if ((ndisauthmode == Ndis802_11AuthModeWPA) || (ndisauthmode == Ndis802_11AuthModeWPAPSK))
-+		authmode = _WPA_IE_ID_;
-+	if ((ndisauthmode == Ndis802_11AuthModeWPA2) || (ndisauthmode == Ndis802_11AuthModeWPA2PSK))
-+		authmode = _WPA2_IE_ID_;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
-+		_rtw_memcpy(out_ie, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len);
-+		ielength = psecuritypriv->wps_ie_len;
-+
-+	} else if ((authmode == _WPA_IE_ID_) || (authmode == _WPA2_IE_ID_)) {
-+		/* copy RSN or SSN		 */
-+		_rtw_memcpy(out_ie, psecuritypriv->supplicant_ie, psecuritypriv->supplicant_ie[1] + 2);
-+		/* debug for CONFIG_IEEE80211W
-+		{
-+			int jj;
-+			printk("supplicant_ie_length=%d &&&&&&&&&&&&&&&&&&&\n", psecuritypriv->supplicant_ie[1]+2);
-+			for(jj=0; jj < psecuritypriv->supplicant_ie[1]+2; jj++)
-+				printk(" %02x ", psecuritypriv->supplicant_ie[jj]);
-+			printk("\n");
-+		}*/
-+		ielength = psecuritypriv->supplicant_ie[1] + 2;
-+		rtw_report_sec_ie(adapter, authmode, psecuritypriv->supplicant_ie);
-+	}
-+
-+	if (authmode == WLAN_EID_RSN) {
-+		iEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid);
-+		ielength = rtw_rsn_sync_pmkid(adapter, out_ie, ielength, iEntry);
-+	}
-+
-+	return ielength;
-+}
-+
-+void rtw_init_registrypriv_dev_network(_adapter *adapter)
-+{
-+	struct registry_priv *pregistrypriv = &adapter->registrypriv;
-+	WLAN_BSSID_EX    *pdev_network = &pregistrypriv->dev_network;
-+	u8 *myhwaddr = adapter_mac_addr(adapter);
-+
-+
-+	_rtw_memcpy(pdev_network->MacAddress, myhwaddr, ETH_ALEN);
-+
-+	_rtw_memcpy(&pdev_network->Ssid, &pregistrypriv->ssid, sizeof(NDIS_802_11_SSID));
-+
-+	pdev_network->Configuration.Length = sizeof(NDIS_802_11_CONFIGURATION);
-+	pdev_network->Configuration.BeaconPeriod = 100;
-+}
-+
-+void rtw_update_registrypriv_dev_network(_adapter *adapter)
-+{
-+	int sz = 0;
-+	struct registry_priv *pregistrypriv = &adapter->registrypriv;
-+	WLAN_BSSID_EX    *pdev_network = &pregistrypriv->dev_network;
-+	struct	security_priv	*psecuritypriv = &adapter->securitypriv;
-+	struct	wlan_network	*cur_network = &adapter->mlmepriv.cur_network;
-+	/* struct	xmit_priv	*pxmitpriv = &adapter->xmitpriv; */
-+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
-+
-+
-+#if 0
-+	pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense;
-+	pxmitpriv->vcs = pregistrypriv->vcs_type;
-+	pxmitpriv->vcs_type = pregistrypriv->vcs_type;
-+	/* pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; */
-+	pxmitpriv->frag_len = pregistrypriv->frag_thresh;
-+
-+	adapter->qospriv.qos_option = pregistrypriv->wmm_enable;
-+#endif
-+
-+	pdev_network->Privacy = (psecuritypriv->dot11PrivacyAlgrthm > 0 ? 1 : 0) ; /* adhoc no 802.1x */
-+
-+	pdev_network->Rssi = 0;
-+
-+	pdev_network->Configuration.DSConfig = (pregistrypriv->channel);
-+
-+	if (cur_network->network.InfrastructureMode == Ndis802_11IBSS) {
-+		pdev_network->Configuration.ATIMWindow = (0);
-+
-+		if (pmlmeext->cur_channel != 0)
-+			pdev_network->Configuration.DSConfig = pmlmeext->cur_channel;
-+		else
-+			pdev_network->Configuration.DSConfig = 1;
-+	}
-+
-+	pdev_network->InfrastructureMode = (cur_network->network.InfrastructureMode);
-+
-+	/* 1. Supported rates */
-+	/* 2. IE */
-+
-+	/* rtw_set_supported_rate(pdev_network->SupportedRates, pregistrypriv->wireless_mode) ; */ /* will be called in rtw_generate_ie */
-+	sz = rtw_generate_ie(pregistrypriv);
-+
-+	pdev_network->IELength = sz;
-+
-+	pdev_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pdev_network);
-+
-+	/* notes: translate IELength & Length after assign the Length to cmdsz in createbss_cmd(); */
-+	/* pdev_network->IELength = cpu_to_le32(sz); */
-+
-+
-+}
-+
-+void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter)
-+{
-+
-+
-+
-+}
-+
-+/* the fucntion is at passive_level */
-+void rtw_joinbss_reset(_adapter *padapter)
-+{
-+	u8	threshold;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	/* todo: if you want to do something io/reg/hw setting before join_bss, please add code here */
-+
-+#ifdef CONFIG_80211N_HT
-+	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
-+
-+	pmlmepriv->num_FortyMHzIntolerant = 0;
-+
-+	pmlmepriv->num_sta_no_ht = 0;
-+
-+	phtpriv->ampdu_enable = _FALSE;/* reset to disabled */
-+
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
-+	/* TH=1 => means that invalidate usb rx aggregation */
-+	/* TH=0 => means that validate usb rx aggregation, use init value. */
-+	if (phtpriv->ht_option) {
-+		if (padapter->registrypriv.wifi_spec == 1)
-+			threshold = 1;
-+		else
-+			threshold = 0;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
-+	} else {
-+		threshold = 1;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
-+	}
-+#endif/* #if defined( CONFIG_USB_HCI) || defined (CONFIG_SDIO_HCI) */
-+
-+#endif/* #ifdef CONFIG_80211N_HT */
-+
-+}
-+
-+
-+#ifdef CONFIG_80211N_HT
-+void	rtw_ht_use_default_setting(_adapter *padapter)
-+{
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
-+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+	BOOLEAN		bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE;
-+#ifdef CONFIG_BEAMFORMING
-+	BOOLEAN		bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE;
-+#endif /* CONFIG_BEAMFORMING */
-+
-+	if (pregistrypriv->wifi_spec)
-+		phtpriv->bss_coexist = 1;
-+	else
-+		phtpriv->bss_coexist = 0;
-+
-+	phtpriv->sgi_40m = TEST_FLAG(pregistrypriv->short_gi, BIT1) ? _TRUE : _FALSE;
-+	phtpriv->sgi_20m = TEST_FLAG(pregistrypriv->short_gi, BIT0) ? _TRUE : _FALSE;
-+
-+	/* LDPC support */
-+	rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport);
-+	CLEAR_FLAGS(phtpriv->ldpc_cap);
-+	if (bHwLDPCSupport) {
-+		if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT4))
-+			SET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX);
-+	}
-+	rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport);
-+	if (bHwLDPCSupport) {
-+		if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT5))
-+			SET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX);
-+	}
-+	if (phtpriv->ldpc_cap)
-+		RTW_INFO("[HT] HAL Support LDPC = 0x%02X\n", phtpriv->ldpc_cap);
-+
-+	/* STBC */
-+	rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport);
-+	CLEAR_FLAGS(phtpriv->stbc_cap);
-+	if (bHwSTBCSupport) {
-+		if (TEST_FLAG(pregistrypriv->stbc_cap, BIT5))
-+			SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX);
-+	}
-+	rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport);
-+	if (bHwSTBCSupport) {
-+		if (TEST_FLAG(pregistrypriv->stbc_cap, BIT4))
-+			SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX);
-+	}
-+	if (phtpriv->stbc_cap)
-+		RTW_INFO("[HT] HAL Support STBC = 0x%02X\n", phtpriv->stbc_cap);
-+
-+	/* Beamforming setting */
-+	CLEAR_FLAGS(phtpriv->beamform_cap);
-+#ifdef CONFIG_BEAMFORMING
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+#ifdef CONFIG_CONCURRENT_MODE
-+	/* only enable beamforming in STA client mode */
-+	if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter))
-+#else
-+	if ((MLME_IS_AP(padapter) && !MLME_IS_GO(padapter)) ||
-+	    (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter)))
-+#endif
-+#endif
-+	{
-+		rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer);
-+		rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee);
-+		if (TEST_FLAG(pregistrypriv->beamform_cap, BIT4) && bHwSupportBeamformer) {
-+			SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
-+			RTW_INFO("[HT] HAL Support Beamformer\n");
-+		}
-+		if (TEST_FLAG(pregistrypriv->beamform_cap, BIT5) && bHwSupportBeamformee) {
-+			SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
-+			RTW_INFO("[HT] HAL Support Beamformee\n");
-+		}
-+	}
-+#endif /* CONFIG_BEAMFORMING */
-+}
-+void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len)
-+{
-+	unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00};
-+	int out_len;
-+	u8 *pframe;
-+
-+	if (padapter->mlmepriv.qospriv.qos_option == 0) {
-+		out_len = *pout_len;
-+		pframe = rtw_set_ie(out_ie + out_len, _VENDOR_SPECIFIC_IE_,
-+				    _WMM_IE_Length_, WMM_IE, pout_len);
-+
-+		padapter->mlmepriv.qospriv.qos_option = 1;
-+	}
-+}
-+#if defined(CONFIG_80211N_HT)
-+/* the fucntion is >= passive_level */
-+unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel)
-+{
-+	u32 ielen, out_len;
-+	u32 rx_packet_offset, max_recvbuf_sz;
-+	HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor;
-+	HT_CAP_AMPDU_DENSITY best_ampdu_density;
-+	unsigned char *p, *pframe;
-+	struct rtw_ieee80211_ht_cap ht_capie;
-+	u8	cbw40_enable = 0, rf_num = 0, rx_stbc_nss = 0, rx_nss = 0;
-+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+#ifdef CONFIG_80211AC_VHT
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
-+#endif /* CONFIG_80211AC_VHT */
-+
-+	phtpriv->ht_option = _FALSE;
-+
-+	out_len = *pout_len;
-+
-+	_rtw_memset(&ht_capie, 0, sizeof(struct rtw_ieee80211_ht_cap));
-+
-+	ht_capie.cap_info = IEEE80211_HT_CAP_DSSSCCK40;
-+
-+	if (phtpriv->sgi_20m)
-+		ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_20;
-+
-+	/* check if 40MHz is allowed according to hal cap and registry */
-+	if (hal_chk_bw_cap(padapter, BW_CAP_40M)) {
-+		if (channel > 14) {
-+			if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
-+				cbw40_enable = 1;
-+		} else {
-+			if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
-+				cbw40_enable = 1;
-+		}
-+	}
-+
-+	if (cbw40_enable) {
-+		struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+		RT_CHANNEL_INFO *chset = rfctl->channel_set;
-+		u8 oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+
-+		if (in_ie == NULL) {
-+			/* TDLS: TODO 20/40 issue */
-+			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
-+				oper_bw = padapter->mlmeextpriv.cur_bwmode;
-+				if (oper_bw > CHANNEL_WIDTH_40)
-+					oper_bw = CHANNEL_WIDTH_40;
-+			} else
-+				/* TDLS: TODO 40? */
-+				oper_bw = CHANNEL_WIDTH_40;
-+		} else {
-+			p = rtw_get_ie(in_ie, WLAN_EID_HT_OPERATION, &ielen, in_len);
-+			if (p && ielen == HT_OP_IE_LEN) {
-+				if (GET_HT_OP_ELE_STA_CHL_WIDTH(p + 2)) {
-+					switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(p + 2)) {
-+					case SCA:
-+						oper_bw = CHANNEL_WIDTH_40;
-+						oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+						break;
-+					case SCB:
-+						oper_bw = CHANNEL_WIDTH_40;
-+						oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+						break;
-+					}
-+				}
-+			}
-+			// IOT issue : AP TP-Link WDR6500
-+			if(oper_bw == CHANNEL_WIDTH_40){ 
-+				p = rtw_get_ie(in_ie, WLAN_EID_HT_CAP, &ielen, in_len);
-+				if (p && ielen == HT_CAP_IE_LEN) {
-+					oper_bw = GET_HT_CAP_ELE_CHL_WIDTH(p + 2)  ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20;
-+					if(oper_bw == CHANNEL_WIDTH_20)
-+						oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+				}
-+			}
-+		}
-+
-+		/* adjust bw to fit in channel plan setting */
-+		if (oper_bw == CHANNEL_WIDTH_40
-+			&& oper_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE /* check this because TDLS has no info to set offset */
-+			&& (!rtw_chset_is_chbw_valid(chset, channel, oper_bw, oper_offset, 1, 1)
-+				|| (IS_DFS_SLAVE_WITH_RD(rfctl)
-+					&& !rtw_rfctl_dfs_domain_unknown(rfctl)
-+					&& rtw_chset_is_chbw_non_ocp(chset, channel, oper_bw, oper_offset))
-+				)
-+		) {
-+			oper_bw = CHANNEL_WIDTH_20;
-+			oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+			rtw_warn_on(!rtw_chset_is_chbw_valid(chset, channel, oper_bw, oper_offset, 1, 1));
-+			if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_rfctl_dfs_domain_unknown(rfctl))
-+				rtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, channel, oper_bw, oper_offset));
-+		}
-+
-+		if (oper_bw == CHANNEL_WIDTH_40) {
-+			ht_capie.cap_info |= IEEE80211_HT_CAP_SUP_WIDTH;
-+			if (phtpriv->sgi_40m)
-+				ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_40;
-+		}
-+
-+		cbw40_enable = oper_bw == CHANNEL_WIDTH_40 ? 1 : 0;
-+	}
-+
-+	/* todo: disable SM power save mode */
-+	ht_capie.cap_info |= IEEE80211_HT_CAP_SM_PS;
-+
-+	/* RX LDPC */
-+	if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) {
-+		ht_capie.cap_info |= IEEE80211_HT_CAP_LDPC_CODING;
-+		RTW_INFO("[HT] Declare supporting RX LDPC\n");
-+	}
-+
-+	/* TX STBC */
-+	if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) {
-+		ht_capie.cap_info |= IEEE80211_HT_CAP_TX_STBC;
-+		RTW_INFO("[HT] Declare supporting TX STBC\n");
-+	}
-+
-+	/* RX STBC */
-+	if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) {
-+		if ((pregistrypriv->rx_stbc == 0x3) ||							/* enable for 2.4/5 GHz */
-+		    ((channel <= 14) && (pregistrypriv->rx_stbc == 0x1)) ||		/* enable for 2.4GHz */
-+		    ((channel > 14) && (pregistrypriv->rx_stbc == 0x2)) ||		/* enable for 5GHz */
-+		    (pregistrypriv->wifi_spec == 1)) {
-+			/* HAL_DEF_RX_STBC means STBC RX spatial stream, todo: VHT 4 streams */
-+			rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss));
-+			SET_HT_CAP_ELE_RX_STBC(&ht_capie, rx_stbc_nss);
-+			RTW_INFO("[HT] Declare supporting RX STBC = %d\n", rx_stbc_nss);
-+		}
-+	}
-+
-+	/* fill default supported_mcs_set */
-+	_rtw_memcpy(ht_capie.supp_mcs_set, pmlmeext->default_supported_mcs_set, 16);
-+
-+	/* update default supported_mcs_set */
-+	rx_nss = GET_HAL_RX_NSS(padapter);
-+
-+	switch (rx_nss) {
-+	case 1:
-+		set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_1R);
-+		break;
-+	case 2:
-+		#ifdef CONFIG_DISABLE_MCS13TO15
-+		if (cbw40_enable && pregistrypriv->wifi_spec != 1)
-+			set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R_13TO15_OFF);
-+		else
-+		#endif
-+			set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R);
-+		break;
-+	case 3:
-+		set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_3R);
-+		break;
-+	case 4:
-+		set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_4R);
-+		break;
-+	default:
-+		RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", GET_HAL_RFPATH(padapter), rx_nss);
-+	}
-+
-+	{
-+		rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset);
-+		rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz);
-+		if (max_recvbuf_sz - rx_packet_offset >= (8191 - 256)) {
-+			RTW_INFO("%s IEEE80211_HT_CAP_MAX_AMSDU is set\n", __FUNCTION__);
-+			ht_capie.cap_info = ht_capie.cap_info | IEEE80211_HT_CAP_MAX_AMSDU;
-+		}
-+	}
-+	/*
-+	AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k
-+	AMPDU_para [4:2]:Min MPDU Start Spacing
-+	*/
-+
-+	/*
-+	#if defined(CONFIG_RTL8188E) && defined(CONFIG_SDIO_HCI)
-+	ht_capie.ampdu_params_info = 2;
-+	#else
-+	ht_capie.ampdu_params_info = (IEEE80211_HT_CAP_AMPDU_FACTOR&0x03);
-+	#endif
-+	*/
-+
-+	if (padapter->driver_rx_ampdu_factor != 0xFF)
-+		max_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)padapter->driver_rx_ampdu_factor;
-+	else
-+		rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor);
-+
-+	/* rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); */
-+	ht_capie.ampdu_params_info = (max_rx_ampdu_factor & 0x03);
-+
-+	if (padapter->driver_rx_ampdu_spacing != 0xFF)
-+		ht_capie.ampdu_params_info |= ((padapter->driver_rx_ampdu_spacing & 0x07) << 2);
-+	else {
-+		if (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) {
-+			/*
-+			*	Todo : Each chip must to ask DD , this chip best ampdu_density setting
-+			*	By yiwei.sun
-+			*/
-+			rtw_hal_get_def_var(padapter, HW_VAR_BEST_AMPDU_DENSITY, &best_ampdu_density);
-+
-+			ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (best_ampdu_density << 2));
-+
-+		} else
-+			ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & 0x00);
-+	}
-+#ifdef CONFIG_BEAMFORMING
-+	ht_capie.tx_BF_cap_info = 0;
-+
-+	/* HT Beamformer*/
-+	if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {
-+		/* Transmit NDP Capable */
-+		SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(&ht_capie, 1);
-+		/* Explicit Compressed Steering Capable */
-+		SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(&ht_capie, 1);
-+		/* Compressed Steering Number Antennas */
-+		SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(&ht_capie, 1);
-+		rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);
-+		SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(&ht_capie, rf_num);
-+	}
-+
-+	/* HT Beamformee */
-+	if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {
-+		/* Receive NDP Capable */
-+		SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(&ht_capie, 1);
-+		/* Explicit Compressed Beamforming Feedback Capable */
-+		SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(&ht_capie, 2);
-+
-+		rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
-+#ifdef CONFIG_80211AC_VHT
-+		/* IOT action suggested by Yu Chen 2017/3/3 */
-+		if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) &&
-+			!pvhtpriv->ap_bf_cap.is_mu_bfer &&
-+			pvhtpriv->ap_bf_cap.su_sound_dim == 2)
-+			rf_num = (rf_num >= 2 ? 2 : rf_num);
-+#endif
-+		SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(&ht_capie, rf_num);
-+	}
-+#endif/*CONFIG_BEAMFORMING*/
-+
-+	pframe = rtw_set_ie(out_ie + out_len, _HT_CAPABILITY_IE_,
-+		sizeof(struct rtw_ieee80211_ht_cap), (unsigned char *)&ht_capie, pout_len);
-+
-+	phtpriv->ht_option = _TRUE;
-+
-+	if (in_ie != NULL) {
-+		p = rtw_get_ie(in_ie, _HT_ADD_INFO_IE_, &ielen, in_len);
-+		if (p && (ielen == sizeof(struct ieee80211_ht_addt_info))) {
-+			out_len = *pout_len;
-+			pframe = rtw_set_ie(out_ie + out_len, _HT_ADD_INFO_IE_, ielen, p + 2 , pout_len);
-+		}
-+	}
-+
-+	return phtpriv->ht_option;
-+
-+}
-+
-+/* the fucntion is > passive_level (in critical_section) */
-+void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel)
-+{
-+	u8 *p, max_ampdu_sz;
-+	int len;
-+	/* struct sta_info *bmc_sta, *psta; */
-+	struct rtw_ieee80211_ht_cap *pht_capie;
-+	struct ieee80211_ht_addt_info *pht_addtinfo;
-+	/* struct recv_reorder_ctrl *preorder_ctrl; */
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
-+	/* struct recv_priv *precvpriv = &padapter->recvpriv; */
-+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+	/* struct wlan_network *pcur_network = &(pmlmepriv->cur_network);; */
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 cbw40_enable = 0;
-+
-+
-+	if (!phtpriv->ht_option)
-+		return;
-+
-+	if ((!pmlmeinfo->HT_info_enable) || (!pmlmeinfo->HT_caps_enable))
-+		return;
-+
-+	RTW_INFO("+rtw_update_ht_cap()\n");
-+
-+	/* maybe needs check if ap supports rx ampdu. */
-+	if ((phtpriv->ampdu_enable == _FALSE) && (pregistrypriv->ampdu_enable == 1)) {
-+		if (pregistrypriv->wifi_spec == 1) {
-+			/* remove this part because testbed AP should disable RX AMPDU */
-+			/* phtpriv->ampdu_enable = _FALSE; */
-+			phtpriv->ampdu_enable = _TRUE;
-+		} else
-+			phtpriv->ampdu_enable = _TRUE;
-+	} 
-+
-+
-+	/* check Max Rx A-MPDU Size */
-+	len = 0;
-+	p = rtw_get_ie(pie + sizeof(NDIS_802_11_FIXED_IEs), _HT_CAPABILITY_IE_, &len, ie_len - sizeof(NDIS_802_11_FIXED_IEs));
-+	if (p && len > 0) {
-+		pht_capie = (struct rtw_ieee80211_ht_cap *)(p + 2);
-+		max_ampdu_sz = (pht_capie->ampdu_params_info & IEEE80211_HT_CAP_AMPDU_FACTOR);
-+		max_ampdu_sz = 1 << (max_ampdu_sz + 3); /* max_ampdu_sz (kbytes); */
-+
-+		/* RTW_INFO("rtw_update_ht_cap(): max_ampdu_sz=%d\n", max_ampdu_sz); */
-+		phtpriv->rx_ampdu_maxlen = max_ampdu_sz;
-+
-+	}
-+
-+
-+	len = 0;
-+	p = rtw_get_ie(pie + sizeof(NDIS_802_11_FIXED_IEs), _HT_ADD_INFO_IE_, &len, ie_len - sizeof(NDIS_802_11_FIXED_IEs));
-+	if (p && len > 0) {
-+		pht_addtinfo = (struct ieee80211_ht_addt_info *)(p + 2);
-+		/* todo: */
-+	}
-+
-+	if (hal_chk_bw_cap(padapter, BW_CAP_40M)) {
-+		if (channel > 14) {
-+			if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
-+				cbw40_enable = 1;
-+		} else {
-+			if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
-+				cbw40_enable = 1;
-+		}
-+	}
-+
-+	/* update cur_bwmode & cur_ch_offset */
-+	if ((cbw40_enable) &&
-+	    (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) &&
-+	    (pmlmeinfo->HT_info.infos[0] & BIT(2))) {
-+		int i;
-+		u8 rx_nss = 0;
-+
-+		rx_nss = GET_HAL_RX_NSS(padapter);
-+
-+		/* update the MCS set */
-+		for (i = 0; i < 16; i++)
-+			pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i];
-+
-+		/* update the MCS rates */
-+		switch (rx_nss) {
-+		case 1:
-+			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R);
-+			break;
-+		case 2:
-+			#ifdef CONFIG_DISABLE_MCS13TO15
-+			if (pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1)
-+				set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF);
-+			else
-+			#endif
-+				set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R);
-+			break;
-+		case 3:
-+			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R);
-+			break;
-+		case 4:
-+			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R);
-+			break;
-+		default:
-+			RTW_WARN("rx_nss:%u is not expected\n", rx_nss);
-+		}
-+
-+		/* switch to the 40M Hz mode accoring to the AP */
-+		/* pmlmeext->cur_bwmode = CHANNEL_WIDTH_40; */
-+		switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) {
-+		case EXTCHNL_OFFSET_UPPER:
-+			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+			break;
-+
-+		case EXTCHNL_OFFSET_LOWER:
-+			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+			break;
-+
-+		default:
-+			pmlmeext->cur_bwmode = CHANNEL_WIDTH_20;
-+			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+			RTW_INFO("%s : ch offset is not assigned for HT40 mod , update cur_bwmode=%u, cur_ch_offset=%u\n", 
-+					__func__, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
-+			break;
-+		}
-+	}
-+
-+	/*  */
-+	/* Config SM Power Save setting */
-+	/*  */
-+	pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;
-+	if (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) {
-+#if 0
-+		u8 i;
-+		/* update the MCS rates */
-+		for (i = 0; i < 16; i++)
-+			pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
-+#endif
-+		RTW_INFO("%s(): WLAN_HT_CAP_SM_PS_STATIC\n", __FUNCTION__);
-+	}
-+
-+	/*  */
-+	/* Config current HT Protection mode. */
-+	/*  */
-+	pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3;
-+}
-+#endif
-+
-+#ifdef CONFIG_TDLS
-+void rtw_issue_addbareq_cmd_tdls(_adapter *padapter, struct xmit_frame *pxmitframe)
-+{
-+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
-+	struct sta_info *ptdls_sta = NULL;
-+	u8 issued;
-+	int priority;
-+	struct ht_priv	*phtpriv;
-+
-+	priority = pattrib->priority;
-+
-+	if (pattrib->direct_link == _TRUE) {
-+		ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst);
-+		if ((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) {
-+			phtpriv = &ptdls_sta->htpriv;
-+
-+			if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) {
-+				issued = (phtpriv->agg_enable_bitmap >> priority) & 0x1;
-+				issued |= (phtpriv->candidate_tid_bitmap >> priority) & 0x1;
-+
-+				if (0 == issued) {
-+					RTW_INFO("[%s], p=%d\n", __FUNCTION__, priority);
-+					ptdls_sta->htpriv.candidate_tid_bitmap |= BIT((u8)priority);
-+					rtw_addbareq_cmd(padapter, (u8)priority, pattrib->dst);
-+				}
-+			}
-+		}
-+	}
-+}
-+#endif /* CONFIG_TDLS */
-+
-+#ifdef CONFIG_80211N_HT
-+static u8 rtw_issue_addbareq_check(_adapter *padapter, struct xmit_frame *pxmitframe, u8 issue_when_busy)
-+{
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct registry_priv *pregistry = &padapter->registrypriv;
-+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
-+	s32 bmcst = IS_MCAST(pattrib->ra);
-+
-+	if (bmcst)
-+		return _FALSE;
-+
-+	if (pregistry->tx_quick_addba_req == 0) {
-+		if ((issue_when_busy == _TRUE) && (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE))
-+			return _FALSE;
-+
-+		if (pmlmepriv->LinkDetectInfo.NumTxOkInPeriod < 100)
-+			return _FALSE;
-+	}
-+
-+	return _TRUE;
-+}
-+
-+void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe, u8 issue_when_busy)
-+{
-+	u8 issued;
-+	int priority;
-+	struct sta_info *psta = NULL;
-+	struct ht_priv	*phtpriv;
-+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
-+
-+	if (rtw_issue_addbareq_check(padapter,pxmitframe, issue_when_busy) == _FALSE)
-+		return;
-+
-+	priority = pattrib->priority;
-+
-+#ifdef CONFIG_TDLS
-+	rtw_issue_addbareq_cmd_tdls(padapter, pxmitframe);
-+#endif /* CONFIG_TDLS */
-+
-+	psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
-+	if (pattrib->psta != psta) {
-+		RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
-+		return;
-+	}
-+
-+	if (psta == NULL) {
-+		RTW_INFO("%s, psta==NUL\n", __func__);
-+		return;
-+	}
-+
-+	if (!(psta->state & WIFI_ASOC_STATE)) {
-+		RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
-+		return;
-+	}
-+
-+
-+	phtpriv = &psta->htpriv;
-+
-+	if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) {
-+		issued = (phtpriv->agg_enable_bitmap >> priority) & 0x1;
-+		issued |= (phtpriv->candidate_tid_bitmap >> priority) & 0x1;
-+
-+		if (0 == issued) {
-+			RTW_INFO("rtw_issue_addbareq_cmd, p=%d\n", priority);
-+			psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority);
-+			rtw_addbareq_cmd(padapter, (u8) priority, pattrib->ra);
-+		}
-+	}
-+
-+}
-+#endif /* CONFIG_80211N_HT */
-+void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len)
-+{
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
-+#ifdef CONFIG_80211AC_VHT
-+	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
-+#endif /* CONFIG_80211AC_VHT */
-+	u8	cap_content[8] = { 0 };
-+	u8	*pframe;
-+	u8   null_content[8] = {0};
-+
-+	if (phtpriv->bss_coexist)
-+		SET_EXT_CAPABILITY_ELE_BSS_COEXIST(cap_content, 1);
-+
-+#ifdef CONFIG_80211AC_VHT
-+	if (pvhtpriv->vht_option)
-+		SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(cap_content, 1);
-+#endif /* CONFIG_80211AC_VHT */
-+#ifdef CONFIG_RTW_WNM
-+	rtw_wnm_set_ext_cap_btm(cap_content, 1);
-+#endif
-+
-+#ifdef CONFIG_RTW_MBO
-+	rtw_mbo_set_ext_cap_internw(cap_content, 1);
-+#endif
-+	/*
-+		From 802.11 specification,if a STA does not support any of capabilities defined
-+		in the Extended Capabilities element, then the STA is not required to
-+		transmit the Extended Capabilities element.
-+	*/
-+	if (_FALSE == _rtw_memcmp(cap_content, null_content, 8))
-+		pframe = rtw_set_ie(out_ie + *pout_len, EID_EXTCapability, 8, cap_content , pout_len);
-+}
-+#endif
-+
-+#ifdef CONFIG_LAYER2_ROAMING
-+inline void rtw_set_to_roam(_adapter *adapter, u8 to_roam)
-+{
-+	if (to_roam == 0)
-+		adapter->mlmepriv.to_join = _FALSE;
-+	adapter->mlmepriv.to_roam = to_roam;
-+}
-+
-+inline u8 rtw_dec_to_roam(_adapter *adapter)
-+{
-+	adapter->mlmepriv.to_roam--;
-+	return adapter->mlmepriv.to_roam;
-+}
-+
-+inline u8 rtw_to_roam(_adapter *adapter)
-+{
-+	return adapter->mlmepriv.to_roam;
-+}
-+
-+void rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network)
-+{
-+	_irqL irqL;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+	_rtw_roaming(padapter, tgt_network);
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+}
-+void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network)
-+{
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct wlan_network *cur_network = &pmlmepriv->cur_network;
-+	int do_join_r;
-+
-+	if (0 < rtw_to_roam(padapter)) {
-+		RTW_INFO("roaming from %s("MAC_FMT"), length:%d\n",
-+			cur_network->network.Ssid.Ssid, MAC_ARG(cur_network->network.MacAddress),
-+			 cur_network->network.Ssid.SsidLength);
-+		_rtw_memcpy(&pmlmepriv->assoc_ssid, &cur_network->network.Ssid, sizeof(NDIS_802_11_SSID));
-+		pmlmepriv->assoc_ch = 0;
-+		pmlmepriv->assoc_by_bssid = _FALSE;
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+		rtw_wapi_return_all_sta_info(padapter);
-+#endif
-+
-+		while (1) {
-+			do_join_r = rtw_do_join(padapter);
-+			if (_SUCCESS == do_join_r)
-+				break;
-+			else {
-+				RTW_INFO("roaming do_join return %d\n", do_join_r);
-+				rtw_dec_to_roam(padapter);
-+
-+				if (rtw_to_roam(padapter) > 0)
-+					continue;
-+				else {
-+					RTW_INFO("%s(%d) -to roaming fail, indicate_disconnect\n", __FUNCTION__, __LINE__);
-+#ifdef CONFIG_RTW_80211R
-+					rtw_ft_clr_flags(padapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN);
-+					rtw_ft_reset_status(padapter);
-+#endif
-+					rtw_indicate_disconnect(padapter, 0, _FALSE);
-+					break;
-+				}
-+			}
-+		}
-+	}
-+
-+}
-+#endif /* CONFIG_LAYER2_ROAMING */
-+
-+bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset)
-+{
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+	u8 allowed_bw;
-+
-+	if (req_ch < 14)
-+		allowed_bw = REGSTY_BW_2G(regsty);
-+	else if (req_ch == 14)
-+		allowed_bw = CHANNEL_WIDTH_20;
-+	else
-+		allowed_bw = REGSTY_BW_5G(regsty);
-+
-+	allowed_bw = hal_largest_bw(adapter, allowed_bw);
-+
-+	if (allowed_bw == CHANNEL_WIDTH_80 && *req_bw > CHANNEL_WIDTH_80)
-+		*req_bw = CHANNEL_WIDTH_80;
-+	else if (allowed_bw == CHANNEL_WIDTH_40 && *req_bw > CHANNEL_WIDTH_40)
-+		*req_bw = CHANNEL_WIDTH_40;
-+	else if (allowed_bw == CHANNEL_WIDTH_20 && *req_bw > CHANNEL_WIDTH_20) {
-+		*req_bw = CHANNEL_WIDTH_20;
-+		*req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	} else
-+		return _FALSE;
-+
-+	return _TRUE;
-+}
-+
-+sint rtw_linked_check(_adapter *padapter)
-+{
-+	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)
-+		|| MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter)
-+	) {
-+		if (padapter->stapriv.asoc_sta_count > 2)
-+			return _TRUE;
-+	} else {
-+		/* Station mode */
-+		if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+			return _TRUE;
-+	}
-+	return _FALSE;
-+}
-+/*#define DBG_ADAPTER_STATE_CHK*/
-+u8 rtw_is_adapter_up(_adapter *padapter)
-+{
-+	if (padapter == NULL)
-+		return _FALSE;
-+
-+	if (RTW_CANNOT_RUN(padapter)) {
-+		#ifdef DBG_ADAPTER_STATE_CHK
-+		RTW_INFO(FUNC_ADPT_FMT " FALSE -bDriverStopped(%s) bSurpriseRemoved(%s)\n"
-+			, FUNC_ADPT_ARG(padapter)
-+			, rtw_is_drv_stopped(padapter) ? "True" : "False"
-+			, rtw_is_surprise_removed(padapter) ? "True" : "False");
-+		#endif
-+		return _FALSE;
-+	}
-+
-+	if (!rtw_is_hw_init_completed(padapter)) {
-+		#ifdef DBG_ADAPTER_STATE_CHK
-+		RTW_INFO(FUNC_ADPT_FMT " FALSE -(hw_init_completed == _FALSE)\n", FUNC_ADPT_ARG(padapter));
-+		#endif
-+		return _FALSE;
-+	}
-+
-+	if (padapter->bup == _FALSE) {
-+		#ifdef DBG_ADAPTER_STATE_CHK
-+		RTW_INFO(FUNC_ADPT_FMT " FALSE -(bup == _FALSE)\n", FUNC_ADPT_ARG(padapter));
-+		#endif
-+		return _FALSE;
-+	}
-+
-+	return _TRUE;
-+}
-+
-+bool is_miracast_enabled(_adapter *adapter)
-+{
-+	bool enabled = 0;
-+#ifdef CONFIG_WFD
-+	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
-+
-+	enabled = (wfdinfo->stack_wfd_mode & (MIRACAST_SOURCE | MIRACAST_SINK))
-+		  || (wfdinfo->op_wfd_mode & (MIRACAST_SOURCE | MIRACAST_SINK));
-+#endif
-+
-+	return enabled;
-+}
-+
-+bool rtw_chk_miracast_mode(_adapter *adapter, u8 mode)
-+{
-+	bool ret = 0;
-+#ifdef CONFIG_WFD
-+	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
-+
-+	ret = (wfdinfo->stack_wfd_mode & mode) || (wfdinfo->op_wfd_mode & mode);
-+#endif
-+
-+	return ret;
-+}
-+
-+const char *get_miracast_mode_str(int mode)
-+{
-+	if (mode == MIRACAST_SOURCE)
-+		return "SOURCE";
-+	else if (mode == MIRACAST_SINK)
-+		return "SINK";
-+	else if (mode == (MIRACAST_SOURCE | MIRACAST_SINK))
-+		return "SOURCE&SINK";
-+	else if (mode == MIRACAST_DISABLED)
-+		return "DISABLED";
-+	else
-+		return "INVALID";
-+}
-+
-+#ifdef CONFIG_WFD
-+static bool wfd_st_match_rule(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
-+{
-+	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
-+
-+	if (ntohs(*((u16 *)local_port)) == wfdinfo->rtsp_ctrlport
-+	    || ntohs(*((u16 *)local_port)) == wfdinfo->tdls_rtsp_ctrlport
-+	    || ntohs(*((u16 *)remote_port)) == wfdinfo->peer_rtsp_ctrlport)
-+		return _TRUE;
-+	return _FALSE;
-+}
-+
-+static struct st_register wfd_st_reg = {
-+	.s_proto = 0x06,
-+	.rule = wfd_st_match_rule,
-+};
-+#endif /* CONFIG_WFD */
-+
-+inline void rtw_wfd_st_switch(struct sta_info *sta, bool on)
-+{
-+#ifdef CONFIG_WFD
-+	if (on)
-+		rtw_st_ctl_register(&sta->st_ctl, SESSION_TRACKER_REG_ID_WFD, &wfd_st_reg);
-+	else
-+		rtw_st_ctl_unregister(&sta->st_ctl, SESSION_TRACKER_REG_ID_WFD);
-+#endif
-+}
-+
-+void dump_arp_pkt(void *sel, u8 *da, u8 *sa, u8 *arp, bool tx)
-+{
-+	RTW_PRINT_SEL(sel, "%s ARP da="MAC_FMT", sa="MAC_FMT"\n"
-+		, tx ? "send" : "recv", MAC_ARG(da), MAC_ARG(sa));
-+	RTW_PRINT_SEL(sel, "htype=%u, ptype=0x%04x, hlen=%u, plen=%u, oper=%u\n"
-+		, GET_ARP_HTYPE(arp), GET_ARP_PTYPE(arp), GET_ARP_HLEN(arp)
-+		, GET_ARP_PLEN(arp), GET_ARP_OPER(arp));
-+	RTW_PRINT_SEL(sel, "sha="MAC_FMT", spa="IP_FMT"\n"
-+		, MAC_ARG(ARP_SENDER_MAC_ADDR(arp)), IP_ARG(ARP_SENDER_IP_ADDR(arp)));
-+	RTW_PRINT_SEL(sel, "tha="MAC_FMT", tpa="IP_FMT"\n"
-+		, MAC_ARG(ARP_TARGET_MAC_ADDR(arp)), IP_ARG(ARP_TARGET_IP_ADDR(arp)));
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/core/rtw_mlme_ext.c b/drivers/staging/rtl8723cs/core/rtw_mlme_ext.c
-new file mode 100644
-index 000000000000..11da273bee38
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_mlme_ext.c
-@@ -0,0 +1,16603 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_MLME_EXT_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+struct mlme_handler mlme_sta_tbl[] = {
-+	{WIFI_ASSOCREQ,		"OnAssocReq",	&OnAssocReq},
-+	{WIFI_ASSOCRSP,		"OnAssocRsp",	&OnAssocRsp},
-+	{WIFI_REASSOCREQ,	"OnReAssocReq",	&OnAssocReq},
-+	{WIFI_REASSOCRSP,	"OnReAssocRsp",	&OnAssocRsp},
-+	{WIFI_PROBEREQ,		"OnProbeReq",	&OnProbeReq},
-+	{WIFI_PROBERSP,		"OnProbeRsp",		&OnProbeRsp},
-+
-+	/*----------------------------------------------------------
-+					below 2 are reserved
-+	-----------------------------------------------------------*/
-+	{0,					"DoReserved",		&DoReserved},
-+	{0,					"DoReserved",		&DoReserved},
-+	{WIFI_BEACON,		"OnBeacon",		&OnBeacon},
-+	{WIFI_ATIM,			"OnATIM",		&OnAtim},
-+	{WIFI_DISASSOC,		"OnDisassoc",		&OnDisassoc},
-+	{WIFI_AUTH,			"OnAuth",		&OnAuthClient},
-+	{WIFI_DEAUTH,		"OnDeAuth",		&OnDeAuth},
-+	{WIFI_ACTION,		"OnAction",		&OnAction},
-+	{WIFI_ACTION_NOACK, "OnActionNoAck",	&OnAction},
-+};
-+
-+#ifdef _CONFIG_NATIVEAP_MLME_
-+struct mlme_handler mlme_ap_tbl[] = {
-+	{WIFI_ASSOCREQ,		"OnAssocReq",	&OnAssocReq},
-+	{WIFI_ASSOCRSP,		"OnAssocRsp",	&OnAssocRsp},
-+	{WIFI_REASSOCREQ,	"OnReAssocReq",	&OnAssocReq},
-+	{WIFI_REASSOCRSP,	"OnReAssocRsp",	&OnAssocRsp},
-+	{WIFI_PROBEREQ,		"OnProbeReq",	&OnProbeReq},
-+	{WIFI_PROBERSP,		"OnProbeRsp",		&OnProbeRsp},
-+
-+	/*----------------------------------------------------------
-+					below 2 are reserved
-+	-----------------------------------------------------------*/
-+	{0,					"DoReserved",		&DoReserved},
-+	{0,					"DoReserved",		&DoReserved},
-+	{WIFI_BEACON,		"OnBeacon",		&OnBeacon},
-+	{WIFI_ATIM,			"OnATIM",		&OnAtim},
-+	{WIFI_DISASSOC,		"OnDisassoc",		&OnDisassoc},
-+	{WIFI_AUTH,			"OnAuth",		&OnAuth},
-+	{WIFI_DEAUTH,		"OnDeAuth",		&OnDeAuth},
-+	{WIFI_ACTION,		"OnAction",		&OnAction},
-+	{WIFI_ACTION_NOACK, "OnActionNoAck",	&OnAction},
-+};
-+#endif
-+
-+struct action_handler OnAction_tbl[] = {
-+	{RTW_WLAN_CATEGORY_SPECTRUM_MGMT,	 "ACTION_SPECTRUM_MGMT", on_action_spct},
-+	{RTW_WLAN_CATEGORY_QOS, "ACTION_QOS", &OnAction_qos},
-+	{RTW_WLAN_CATEGORY_DLS, "ACTION_DLS", &OnAction_dls},
-+	{RTW_WLAN_CATEGORY_BACK, "ACTION_BACK", &OnAction_back},
-+	{RTW_WLAN_CATEGORY_PUBLIC, "ACTION_PUBLIC", on_action_public},
-+	{RTW_WLAN_CATEGORY_RADIO_MEAS, "ACTION_RADIO_MEAS", &on_action_rm},
-+	{RTW_WLAN_CATEGORY_FT, "ACTION_FT",	&OnAction_ft},
-+	{RTW_WLAN_CATEGORY_HT,	"ACTION_HT",	&OnAction_ht},
-+#ifdef CONFIG_IEEE80211W
-+	{RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &OnAction_sa_query},
-+#else
-+	{RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &DoReserved},
-+#endif /* CONFIG_IEEE80211W */
-+#ifdef CONFIG_RTW_WNM
-+	{RTW_WLAN_CATEGORY_WNM, "ACTION_WNM", &on_action_wnm},
-+#endif
-+	{RTW_WLAN_CATEGORY_UNPROTECTED_WNM, "ACTION_UNPROTECTED_WNM", &DoReserved},
-+#ifdef CONFIG_RTW_MESH
-+	{RTW_WLAN_CATEGORY_MESH, "ACTION_MESH", &on_action_mesh},
-+	{RTW_WLAN_CATEGORY_SELF_PROTECTED, "ACTION_SELF_PROTECTED", &on_action_self_protected},
-+#endif
-+	{RTW_WLAN_CATEGORY_WMM, "ACTION_WMM", &OnAction_wmm},
-+	{RTW_WLAN_CATEGORY_VHT, "ACTION_VHT", &OnAction_vht},
-+	{RTW_WLAN_CATEGORY_P2P, "ACTION_P2P", &OnAction_p2p},
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	{RTW_WLAN_CATEGORY_TBTX, "ACTION_TBTX_TOKEN", &OnAction_tbtx_token}
-+#endif
-+};
-+
-+
-+u8	null_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
-+
-+/**************************************************
-+OUI definitions for the vendor specific IE
-+***************************************************/
-+unsigned char	RTW_WPA_OUI[] = {0x00, 0x50, 0xf2, 0x01};
-+unsigned char WMM_OUI[] = {0x00, 0x50, 0xf2, 0x02};
-+unsigned char	WPS_OUI[] = {0x00, 0x50, 0xf2, 0x04};
-+unsigned char	P2P_OUI[] = {0x50, 0x6F, 0x9A, 0x09};
-+unsigned char	WFD_OUI[] = {0x50, 0x6F, 0x9A, 0x0A};
-+unsigned char	DPP_OUI[] = {0x50, 0x6F, 0x9A, 0x1A};
-+unsigned char	MULTI_AP_OUI[] = {0x50, 0x6F, 0x9A, 0x1B};
-+
-+unsigned char	WMM_INFO_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01};
-+unsigned char	WMM_PARA_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};
-+
-+unsigned char WPA_TKIP_CIPHER[4] = {0x00, 0x50, 0xf2, 0x02};
-+unsigned char RSN_TKIP_CIPHER[4] = {0x00, 0x0f, 0xac, 0x02};
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+unsigned char REALTEK_TBTX_IE[] = {0x00, 0xe0, 0x4c, 0x01, 0x00, 0x00, 0x00, 0x00};
-+#endif
-+extern unsigned char REALTEK_96B_IE[];
-+
-+static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set
-+	, struct p2p_channels *channel_list)
-+{
-+	struct registry_priv *regsty = adapter_to_regsty(padapter);
-+
-+	struct p2p_oper_class_map op_class[] = {
-+		{ IEEE80211G,  81,   1,  13,  1, BW20 },
-+		{ IEEE80211G,  82,  14,  14,  1, BW20 },
-+#if 0 /* Do not enable HT40 on 2 GHz */
-+		{ IEEE80211G,  83,   1,   9,  1, BW40PLUS },
-+		{ IEEE80211G,  84,   5,  13,  1, BW40MINUS },
-+#endif
-+		{ IEEE80211A, 115,  36,  48,  4, BW20 },
-+		{ IEEE80211A, 116,  36,  44,  8, BW40PLUS },
-+		{ IEEE80211A, 117,  40,  48,  8, BW40MINUS },
-+		{ IEEE80211A, 124, 149, 161,  4, BW20 },
-+		{ IEEE80211A, 125, 149, 169,  4, BW20 },
-+		{ IEEE80211A, 126, 149, 157,  8, BW40PLUS },
-+		{ IEEE80211A, 127, 153, 161,  8, BW40MINUS },
-+		{ -1, 0, 0, 0, 0, BW20 }
-+	};
-+
-+	int cla, op;
-+
-+	cla = 0;
-+
-+	for (op = 0; op_class[op].op_class; op++) {
-+		u8 ch;
-+		struct p2p_oper_class_map *o = &op_class[op];
-+		struct p2p_reg_class *reg = NULL;
-+
-+		for (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) {
-+			if (rtw_chset_search_ch(channel_set, ch) == -1)
-+				continue;
-+#if defined(CONFIG_80211N_HT) || defined(CONFIG_80211AC_VHT)
-+			if ((padapter->registrypriv.ht_enable == 0) && (o->inc == 8))
-+				continue;
-+
-+			if ((REGSTY_IS_BW_5G_SUPPORT(regsty, CHANNEL_WIDTH_40)) &&
-+			    ((o->bw == BW40MINUS) || (o->bw == BW40PLUS)))
-+				continue;
-+#endif
-+			if (reg == NULL) {
-+				reg = &channel_list->reg_class[cla];
-+				cla++;
-+				reg->reg_class = o->op_class;
-+				reg->channels = 0;
-+			}
-+			reg->channel[reg->channels] = ch;
-+			reg->channels++;
-+		}
-+	}
-+	channel_list->reg_classes = cla;
-+
-+}
-+
-+#if CONFIG_TXPWR_LIMIT
-+void rtw_txpwr_init_regd(struct rf_ctl_t *rfctl)
-+{
-+	u8 regd;
-+	struct regd_exc_ent *exc;
-+	struct txpwr_lmt_ent *ent;
-+	_irqL irqL;
-+
-+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+	rfctl->regd_name = NULL;
-+
-+	if (rfctl->txpwr_regd_num == 0) {
-+		RTW_PRINT("there is no any txpwr_regd\n");
-+		goto release_lock;
-+	}
-+
-+	/* search from exception mapping */
-+	exc = _rtw_regd_exc_search(rfctl
-+		, rfctl->country_ent ? rfctl->country_ent->alpha2 : NULL
-+		, rfctl->ChannelPlan);
-+	if (exc) {
-+		u8 has_country = (exc->country[0] == '\0' && exc->country[1] == '\0') ? 0 : 1;
-+
-+		if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_NONE)) == 0)
-+			rfctl->regd_name = regd_str(TXPWR_LMT_NONE);
-+		else if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_WW)) == 0)
-+			rfctl->regd_name = regd_str(TXPWR_LMT_WW);
-+		else {
-+			ent = _rtw_txpwr_lmt_get_by_name(rfctl, exc->regd_name);
-+			if (ent)
-+				rfctl->regd_name = ent->regd_name;
-+		}
-+
-+		RTW_PRINT("exception mapping country:%c%c domain:0x%02x to%s regd_name:%s\n"
-+			, has_country ? exc->country[0] : '0'
-+			, has_country ? exc->country[1] : '0'
-+			, exc->domain
-+			, rfctl->regd_name ? "" : " unknown"
-+			, exc->regd_name
-+		);
-+		if (rfctl->regd_name)
-+			goto release_lock;
-+	}
-+
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+	if (rfctl->regd_src == REGD_SRC_OS) {
-+		if (IS_ALPHA2_WORLDWIDE(rfctl->country_ent->alpha2))
-+			rfctl->regd_name = regd_str(TXPWR_LMT_WW);
-+		else {
-+			char alpha2[3] = {
-+				rfctl->country_ent->alpha2[0], rfctl->country_ent->alpha2[1], 0};
-+
-+			ent = _rtw_txpwr_lmt_get_by_name(rfctl, alpha2);
-+			if (ent)
-+				rfctl->regd_name = ent->regd_name;
-+		}
-+
-+		if (rfctl->regd_name) {
-+			RTW_PRINT("mapping country:%c%c to regd_name:%s\n"
-+				, rfctl->country_ent->alpha2[0]
-+				, rfctl->country_ent->alpha2[1]
-+				, rfctl->regd_name
-+			);
-+			goto release_lock;
-+		}
-+
-+		if (rfctl->ChannelPlan == RTW_CHPLAN_UNSPECIFIED) {
-+			rfctl->regd_name = regd_str(TXPWR_LMT_WW);
-+			RTW_PRINT("mapping unsupported country:%c%c to regd_name:%s\n"
-+				, rfctl->country_ent->alpha2[0]
-+				, rfctl->country_ent->alpha2[1]
-+				, rfctl->regd_name
-+			);
-+			goto release_lock;
-+		}
-+	}
-+#endif
-+
-+	/* follow default channel plan mapping */
-+	regd = rtw_chplan_get_default_regd(rfctl->ChannelPlan);
-+	if (regd == TXPWR_LMT_NONE)
-+		rfctl->regd_name = regd_str(TXPWR_LMT_NONE);
-+	else if (regd == TXPWR_LMT_WW)
-+		rfctl->regd_name = regd_str(TXPWR_LMT_WW);
-+	else {
-+		ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd));
-+		if (ent)
-+			rfctl->regd_name = ent->regd_name;
-+	}
-+
-+	RTW_PRINT("default mapping domain:0x%02x to%s regd_name:%s\n"
-+		, rfctl->ChannelPlan
-+		, rfctl->regd_name ? "" : " unknown"
-+		, regd_str(regd)
-+	);
-+	if (rfctl->regd_name)
-+		goto release_lock;
-+
-+	switch (regd) {
-+	/*
-+	* To support older chips without new predefined regd:
-+	* - use FCC if IC or CHILE or MEXICO not found
-+	* - use ETSI if KCC or ACMA not found
-+	*/
-+	case TXPWR_LMT_IC:
-+	case TXPWR_LMT_KCC:
-+	case TXPWR_LMT_NCC:
-+	case TXPWR_LMT_ACMA:
-+	case TXPWR_LMT_CHILE:
-+	case TXPWR_LMT_MEXICO:
-+		if (regd == TXPWR_LMT_IC || regd == TXPWR_LMT_NCC || regd == TXPWR_LMT_CHILE || regd == TXPWR_LMT_MEXICO)
-+			regd = TXPWR_LMT_FCC;
-+		else if (regd == TXPWR_LMT_KCC || regd == TXPWR_LMT_ACMA)
-+			regd = TXPWR_LMT_ETSI;
-+		ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd));
-+		if (ent)
-+			rfctl->regd_name = ent->regd_name;
-+		RTW_PRINT("alternate regd_name:%s %s\n"
-+			, regd_str(regd)
-+			, rfctl->regd_name ? "is used" : "not found"
-+		);
-+		if (rfctl->regd_name)
-+			break;
-+		fallthrough;
-+	default:
-+		rfctl->regd_name = regd_str(TXPWR_LMT_WW);
-+		RTW_PRINT("assign %s for default case\n", regd_str(TXPWR_LMT_WW));
-+		break;
-+	};
-+
-+release_lock:
-+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+}
-+#endif /* CONFIG_TXPWR_LIMIT */
-+
-+int rtw_rfctl_init(_adapter *adapter)
-+{
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	int ret;
-+
-+	_rtw_mutex_init(&rfctl->offch_mutex);
-+
-+#if CONFIG_TXPWR_LIMIT
-+	_rtw_mutex_init(&rfctl->txpwr_lmt_mutex);
-+	_rtw_init_listhead(&rfctl->reg_exc_list);
-+	_rtw_init_listhead(&rfctl->txpwr_lmt_list);
-+#endif
-+
-+	rfctl->ch_sel_within_same_band = 1;
-+
-+#ifdef CONFIG_DFS_MASTER
-+	rfctl->dfs_region_domain = regsty->dfs_region_domain;
-+	rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
-+	rtw_init_timer(&(rfctl->radar_detect_timer), adapter, rtw_dfs_rd_timer_hdl, rfctl);
-+#endif
-+#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
-+	rfctl->dfs_slave_with_rd = 1;
-+#endif
-+
-+	if (regsty->antenna_gain != UNSPECIFIED_MBM)
-+		rfctl->antenna_gain = regsty->antenna_gain;
-+
-+	ret = op_class_pref_init(adapter);
-+	if (ret != _SUCCESS)
-+		op_class_pref_deinit(adapter);
-+
-+	return ret;
-+}
-+
-+void rtw_rfctl_deinit(_adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	_rtw_mutex_free(&rfctl->offch_mutex);
-+
-+#if CONFIG_TXPWR_LIMIT
-+	rtw_regd_exc_list_free(rfctl);
-+	rtw_txpwr_lmt_list_free(rfctl);
-+	_rtw_mutex_free(&rfctl->txpwr_lmt_mutex);
-+#endif
-+
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+	if (rfctl->regd_src == REGD_SRC_OS)
-+		rtw_mfree((void *)rfctl->country_ent, sizeof(struct country_chplan));
-+#endif
-+
-+	op_class_pref_deinit(adapter);
-+}
-+
-+void rtw_rfctl_chplan_init(_adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	rfctl->max_chan_nums = init_channel_set(adapter);
-+	op_class_pref_apply_regulatory(adapter, REG_CHANGE);
-+	init_channel_list(adapter, rfctl->channel_set, &rfctl->channel_list);
-+}
-+
-+void rtw_rfctl_update_op_mode(struct rf_ctl_t *rfctl, u8 ifbmp_mod, u8 if_op)
-+{
-+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
-+	_adapter *iface;
-+	struct mlme_ext_priv *mlmeext;
-+	u8 op_class = 0;
-+	u8 op_ch = 0;
-+	s16 op_txpwr_max;
-+	u8 if_op_class[CONFIG_IFACE_NUMBER] = {0};
-+	u8 if_op_ch[CONFIG_IFACE_NUMBER] = {0};
-+	u8 ch, bw, offset;
-+	u8 u_ch = 0, u_bw, u_offset;
-+	bool notify = 0;
-+	int i;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+		mlmeext = &iface->mlmeextpriv;
-+
-+		if (ifbmp_mod & BIT(i)) {
-+			if (!if_op)
-+				continue;
-+		} else if (!MLME_IS_ASOC(iface) || MLME_IS_OPCH_SW(iface))
-+			continue;
-+
-+		ch = mlmeext->cur_channel;
-+		bw = mlmeext->cur_bwmode;
-+		offset = mlmeext->cur_ch_offset;
-+		if_op_class[i] = rtw_get_op_class_by_chbw(ch, bw, offset);
-+		if_op_ch[i] = if_op_class[i] ? ch : 0;
-+
-+		if (!u_ch) {
-+			u_ch = ch;
-+			u_bw = bw;
-+			u_offset = offset;
-+		} else {
-+			rtw_warn_on(!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, ch, bw, offset));
-+			rtw_sync_chbw(&ch, &bw, &offset, &u_ch, &u_bw, &u_offset);
-+		}
-+	}
-+
-+	op_class = rtw_get_op_class_by_chbw(u_ch, u_bw, u_offset);
-+	op_ch = op_class ? u_ch : 0;
-+	op_txpwr_max = rtw_rfctl_get_oper_txpwr_max_mbm(rfctl, u_ch, u_bw, u_offset, ifbmp_mod, if_op, 1);
-+
-+	if (op_class != rfctl->op_class
-+		|| op_ch != rfctl->op_ch
-+		|| op_txpwr_max != rfctl->op_txpwr_max
-+		|| _rtw_memcmp(if_op_class, rfctl->if_op_class, sizeof(u8) * CONFIG_IFACE_NUMBER) == _FALSE
-+		|| _rtw_memcmp(if_op_ch, rfctl->if_op_ch, sizeof(u8) * CONFIG_IFACE_NUMBER) == _FALSE)
-+		notify = 1;
-+
-+	rfctl->op_class = op_class;
-+	rfctl->op_ch = op_ch;
-+	rfctl->op_txpwr_max = op_txpwr_max;
-+	_rtw_memcpy(rfctl->if_op_class, if_op_class, sizeof(u8) * CONFIG_IFACE_NUMBER);
-+	_rtw_memcpy(rfctl->if_op_ch, if_op_ch, sizeof(u8) * CONFIG_IFACE_NUMBER);
-+
-+	if (0)
-+		RTW_INFO("radio: %u,%u,%u %d notify:%d\n", u_ch, u_bw, u_offset, op_txpwr_max, notify);
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+		mlmeext = &iface->mlmeextpriv;
-+
-+		if (ifbmp_mod & BIT(i)) {
-+			if (!if_op)
-+				continue;
-+		} else if (!MLME_IS_ASOC(iface))
-+			continue;
-+		if (0)
-+			RTW_INFO(ADPT_FMT": %u,%u,%u\n", ADPT_ARG(iface)
-+				, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
-+	}
-+
-+	if (notify)
-+		rtw_nlrtw_radio_opmode_notify(rfctl);
-+
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+		cmap_intfs_nl_bss_status_event(iface, 0);
-+	}
-+#endif
-+}
-+
-+inline u8 rtw_rfctl_get_dfs_domain(struct rf_ctl_t *rfctl)
-+{
-+#ifdef CONFIG_DFS_MASTER
-+	return rfctl->dfs_region_domain;
-+#else
-+	return RTW_DFS_REGD_NONE;
-+#endif
-+}
-+
-+inline u8 rtw_rfctl_dfs_domain_unknown(struct rf_ctl_t *rfctl)
-+{
-+#ifdef CONFIG_DFS_MASTER
-+	return rtw_rfctl_get_dfs_domain(rfctl) == RTW_DFS_REGD_NONE;
-+#else
-+	return 1;
-+#endif
-+}
-+
-+#ifdef CONFIG_DFS_MASTER
-+/*
-+* called in rtw_dfs_rd_enable()
-+* assume the request channel coverage is DFS range
-+* base on the current status and the request channel coverage to check if need to reset complete CAC time
-+*/
-+bool rtw_is_cac_reset_needed(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset)
-+{
-+	bool needed = _FALSE;
-+	u32 cur_hi, cur_lo, hi, lo;
-+
-+	if (rfctl->radar_detected == 1) {
-+		needed = _TRUE;
-+		goto exit;
-+	}
-+
-+	if (rfctl->radar_detect_ch == 0) {
-+		needed = _TRUE;
-+		goto exit;
-+	}
-+
-+	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) {
-+		RTW_ERR("request detection range ch:%u, bw:%u, offset:%u\n", ch, bw, offset);
-+		rtw_warn_on(1);
-+	}
-+
-+	if (rtw_chbw_to_freq_range(rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset, &cur_hi, &cur_lo) == _FALSE) {
-+		RTW_ERR("cur detection range ch:%u, bw:%u, offset:%u\n", rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);
-+		rtw_warn_on(1);
-+	}
-+
-+	if (hi <= lo || cur_hi <= cur_lo) {
-+		RTW_ERR("hi:%u, lo:%u, cur_hi:%u, cur_lo:%u\n", hi, lo, cur_hi, cur_lo);
-+		rtw_warn_on(1);
-+	}
-+
-+	if (rtw_is_range_a_in_b(hi, lo, cur_hi, cur_lo)) {
-+		/* request is in current detect range */
-+		goto exit;
-+	}
-+
-+	/* check if request channel coverage has new range and the new range is in DFS range */
-+	if (!rtw_is_range_overlap(hi, lo, cur_hi, cur_lo)) {
-+		/* request has no overlap with current */
-+		needed = _TRUE;
-+	} else if (rtw_is_range_a_in_b(cur_hi, cur_lo, hi, lo)) {
-+		/* request is supper set of current */
-+		if ((hi != cur_hi && rtw_chset_is_dfs_range(rfctl->channel_set, hi, cur_hi))
-+			|| (lo != cur_lo && rtw_chset_is_dfs_range(rfctl->channel_set, cur_lo, lo)))
-+			needed = _TRUE;
-+	} else {
-+		/* request is not supper set of current, but has overlap */
-+		if ((lo < cur_lo && rtw_chset_is_dfs_range(rfctl->channel_set, cur_lo, lo))
-+			|| (hi > cur_hi && rtw_chset_is_dfs_range(rfctl->channel_set, hi, cur_hi)))
-+			needed = _TRUE;
-+	}
-+
-+exit:
-+	return needed;
-+}
-+
-+bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset)
-+{
-+	bool ret = _FALSE;
-+	u32 hi = 0, lo = 0;
-+	u32 r_hi = 0, r_lo = 0;
-+	int i;
-+
-+	if (rfctl->radar_detect_by_others)
-+		goto exit;
-+
-+	if (rfctl->radar_detect_ch == 0)
-+		goto exit;
-+
-+	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (rtw_chbw_to_freq_range(rfctl->radar_detect_ch
-+			, rfctl->radar_detect_bw, rfctl->radar_detect_offset
-+			, &r_hi, &r_lo) == _FALSE) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (rtw_is_range_overlap(hi, lo, r_hi, r_lo))
-+		ret = _TRUE;
-+
-+exit:
-+	return ret;
-+}
-+
-+bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl)
-+{
-+	return _rtw_rfctl_overlap_radar_detect_ch(rfctl
-+				, rfctl_to_dvobj(rfctl)->oper_channel
-+				, rfctl_to_dvobj(rfctl)->oper_bwmode
-+				, rfctl_to_dvobj(rfctl)->oper_ch_offset);
-+}
-+
-+bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl)
-+{
-+	return rtw_rfctl_overlap_radar_detect_ch(rfctl) && IS_CH_WAITING(rfctl);
-+}
-+
-+bool rtw_chset_is_chbw_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
-+{
-+	bool ret = _FALSE;
-+	u32 hi = 0, lo = 0;
-+	int i;
-+
-+	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
-+		goto exit;
-+
-+	for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
-+		if (!rtw_ch2freq(ch_set[i].ChannelNum)) {
-+			rtw_warn_on(1);
-+			continue;
-+		}
-+
-+		if (!CH_IS_NON_OCP(&ch_set[i]))
-+			continue;
-+
-+		if (lo <= rtw_ch2freq(ch_set[i].ChannelNum)
-+			&& rtw_ch2freq(ch_set[i].ChannelNum) <= hi
-+		) {
-+			ret = _TRUE;
-+			break;
-+		}
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch)
-+{
-+	return rtw_chset_is_chbw_non_ocp(ch_set, ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
-+}
-+
-+u32 rtw_chset_get_ch_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
-+{
-+	int ms = 0;
-+	systime current_time;
-+	u32 hi = 0, lo = 0;
-+	int i;
-+
-+	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
-+		goto exit;
-+
-+	current_time = rtw_get_current_time();
-+
-+	for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
-+		if (!rtw_ch2freq(ch_set[i].ChannelNum)) {
-+			rtw_warn_on(1);
-+			continue;
-+		}
-+
-+		if (!CH_IS_NON_OCP(&ch_set[i]))
-+			continue;
-+
-+		if (lo <= rtw_ch2freq(ch_set[i].ChannelNum)
-+			&& rtw_ch2freq(ch_set[i].ChannelNum) <= hi
-+		) {
-+			if (rtw_systime_to_ms(ch_set[i].non_ocp_end_time - current_time) > ms)
-+				ms = rtw_systime_to_ms(ch_set[i].non_ocp_end_time - current_time);
-+		}
-+	}
-+
-+exit:
-+	return ms;
-+}
-+
-+/**
-+ * rtw_chset_update_non_ocp - update non_ocp_end_time according to the given @ch, @bw, @offset into @ch_set
-+ * @ch_set: the given channel set
-+ * @ch: channel number on which radar is detected
-+ * @bw: bandwidth on which radar is detected
-+ * @offset: bandwidth offset on which radar is detected
-+ * @ms: ms to add from now to update non_ocp_end_time, ms < 0 means use NON_OCP_TIME_MS
-+ */
-+static bool _rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms)
-+{
-+	u32 hi = 0, lo = 0;
-+	int i;
-+	bool updated = 0;
-+
-+	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
-+		goto exit;
-+
-+	for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
-+		if (!rtw_ch2freq(ch_set[i].ChannelNum)) {
-+			rtw_warn_on(1);
-+			continue;
-+		}
-+
-+		if (lo <= rtw_ch2freq(ch_set[i].ChannelNum)
-+			&& rtw_ch2freq(ch_set[i].ChannelNum) <= hi
-+		) {
-+			if (ms >= 0)
-+				ch_set[i].non_ocp_end_time = rtw_get_current_time() + rtw_ms_to_systime(ms);
-+			else
-+				ch_set[i].non_ocp_end_time = rtw_get_current_time() + rtw_ms_to_systime(NON_OCP_TIME_MS);
-+			ch_set[i].flags |= RTW_CHF_NON_OCP;
-+			updated = 1;
-+		}
-+	}
-+
-+exit:
-+	return updated;
-+}
-+
-+inline bool rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
-+{
-+	return _rtw_chset_update_non_ocp(ch_set, ch, bw, offset, -1);
-+}
-+
-+inline bool rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms)
-+{
-+	return _rtw_chset_update_non_ocp(ch_set, ch, bw, offset, ms);
-+}
-+
-+static bool rtw_chset_chk_non_ocp_finish_for_chbw(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset)
-+{
-+	RT_CHANNEL_INFO *ch_set = rfctl->channel_set;
-+	u8 cch;
-+	u8 *op_chs;
-+	u8 op_ch_num;
-+	int i;
-+	int ch_idx;
-+	bool ret = 0;
-+
-+	cch = rtw_get_center_ch(ch, bw, offset);
-+
-+	if (!rtw_get_op_chs_by_cch_bw(cch, bw, &op_chs, &op_ch_num))
-+		goto exit;
-+
-+	for (i = 0; i < op_ch_num; i++) {
-+		if (0)
-+			RTW_INFO("%u,%u,%u - cch:%u, bw:%u, op_ch:%u\n", ch, bw, offset, cch, bw, *(op_chs + i));
-+		ch_idx = rtw_chset_search_ch(ch_set, *(op_chs + i));
-+		if (ch_idx == -1)
-+			break;
-+		if (!(ch_set[ch_idx].flags & RTW_CHF_NON_OCP) || CH_IS_NON_OCP(&ch_set[ch_idx]))
-+			break;
-+	}
-+
-+	if (op_ch_num != 0 && i == op_ch_num) {
-+		ret = 1;
-+		/* clear RTTW_CHF_NON_OCP flag */
-+		for (i = 0; i < op_ch_num; i++) {
-+			ch_idx = rtw_chset_search_ch(ch_set, *(op_chs + i));
-+			ch_set[ch_idx].flags &= ~RTW_CHF_NON_OCP;
-+		}
-+		rtw_nlrtw_nop_finish_event(dvobj_get_primary_adapter(rfctl_to_dvobj(rfctl)), cch, bw);
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+/* called by watchdog to clear RTW_CHF_NON_OCP and generate NON_OCP finish event */
-+void rtw_chset_chk_non_ocp_finish(struct rf_ctl_t *rfctl)
-+{
-+	u8 ch, bw, offset;
-+	int i;
-+
-+	bw = CHANNEL_WIDTH_160;
-+	while (1) {
-+		for (i = 0; i < rfctl->max_chan_nums; i++) {
-+			ch = rfctl->channel_set[i].ChannelNum;
-+			if (!(rfctl->channel_set[i].flags & RTW_CHF_NON_OCP))
-+				continue;
-+			if (!rtw_get_offset_by_chbw(ch, bw, &offset))
-+				continue;
-+
-+			rtw_chset_chk_non_ocp_finish_for_chbw(rfctl, ch, bw, offset);
-+		}
-+		if (bw-- == CHANNEL_WIDTH_20)
-+			break;
-+	}
-+}
-+
-+u32 rtw_get_ch_waiting_ms(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms)
-+{
-+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
-+	u32 non_ocp_ms;
-+	u32 cac_ms;
-+	u8 in_rd_range = 0; /* if in current radar detection range*/
-+
-+	if (rtw_chset_is_chbw_non_ocp(rfctl->channel_set, ch, bw, offset))
-+		non_ocp_ms = rtw_chset_get_ch_non_ocp_ms(rfctl->channel_set, ch, bw, offset);
-+	else
-+		non_ocp_ms = 0;
-+
-+	if (rfctl->radar_detect_enabled) {
-+		u32 cur_hi, cur_lo, hi, lo;
-+
-+		if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) {
-+			RTW_ERR("input range ch:%u, bw:%u, offset:%u\n", ch, bw, offset);
-+			rtw_warn_on(1);
-+		}
-+
-+		if (rtw_chbw_to_freq_range(rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset, &cur_hi, &cur_lo) == _FALSE) {
-+			RTW_ERR("cur detection range ch:%u, bw:%u, offset:%u\n", rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);
-+			rtw_warn_on(1);
-+		}
-+
-+		if (rtw_is_range_a_in_b(hi, lo, cur_hi, cur_lo))
-+			in_rd_range = 1;
-+	}
-+
-+	if (!rtw_chset_is_dfs_chbw(rfctl->channel_set, ch, bw, offset))
-+		cac_ms = 0;
-+	else if (in_rd_range && !non_ocp_ms) {
-+		if (IS_CH_WAITING(rfctl))
-+			cac_ms = rtw_systime_to_ms(rfctl->cac_end_time - rtw_get_current_time());
-+		else
-+			cac_ms = 0;
-+	} else if (rtw_is_long_cac_ch(ch, bw, offset, rtw_rfctl_get_dfs_domain(rfctl)))
-+		cac_ms = CAC_TIME_CE_MS;
-+	else
-+		cac_ms = CAC_TIME_MS;
-+
-+	if (r_non_ocp_ms)
-+		*r_non_ocp_ms = non_ocp_ms;
-+	if (r_cac_ms)
-+		*r_cac_ms = cac_ms;
-+
-+	return non_ocp_ms + cac_ms;
-+}
-+
-+void rtw_reset_cac(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset)
-+{
-+	u32 non_ocp_ms;
-+	u32 cac_ms;
-+
-+	rtw_get_ch_waiting_ms(rfctl
-+		, ch
-+		, bw
-+		, offset
-+		, &non_ocp_ms
-+		, &cac_ms
-+	);
-+
-+	rfctl->cac_start_time = rtw_get_current_time() + rtw_ms_to_systime(non_ocp_ms);
-+	rfctl->cac_end_time = rfctl->cac_start_time + rtw_ms_to_systime(cac_ms);
-+
-+	/* skip special value */
-+	if (rfctl->cac_start_time == RTW_CAC_STOPPED) {
-+		rfctl->cac_start_time++;
-+		rfctl->cac_end_time++;
-+	}
-+	if (rfctl->cac_end_time == RTW_CAC_STOPPED)
-+		rfctl->cac_end_time++;
-+}
-+
-+u32 rtw_force_stop_cac(struct rf_ctl_t *rfctl, u32 timeout_ms)
-+{
-+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
-+	systime start;
-+	u32 pass_ms;
-+
-+	start = rtw_get_current_time();
-+
-+	rfctl->cac_force_stop = 1;
-+
-+	while (rtw_get_passing_time_ms(start) <= timeout_ms
-+		&& IS_UNDER_CAC(rfctl)
-+	) {
-+		if (dev_is_surprise_removed(dvobj) || dev_is_drv_stopped(dvobj))
-+			break;
-+		rtw_msleep_os(20);
-+	}
-+
-+	if (IS_UNDER_CAC(rfctl)) {
-+		if (!dev_is_surprise_removed(dvobj) && !dev_is_drv_stopped(dvobj))
-+			RTW_INFO("%s waiting for cac stop timeout!\n", __func__);
-+	}
-+
-+	rfctl->cac_force_stop = 0;
-+
-+	pass_ms = rtw_get_passing_time_ms(start);
-+
-+	return pass_ms;
-+}
-+#endif /* CONFIG_DFS_MASTER */
-+
-+/* choose channel with shortest waiting (non ocp + cac) time */
-+bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw
-+	, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset
-+	, u8 e_flags, u8 d_flags, u8 cur_ch, bool by_int_info, u8 mesh_only)
-+{
-+#ifndef DBG_CHOOSE_SHORTEST_WAITING_CH
-+#define DBG_CHOOSE_SHORTEST_WAITING_CH 0
-+#endif
-+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
-+#ifdef CONFIG_RTW_ACS
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(dvobj_get_primary_adapter(dvobj));
-+#endif
-+	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
-+	u8 ch, bw, offset;
-+	u8 ch_c = 0, bw_c = 0, offset_c = 0;
-+	int i;
-+	u32 min_waiting_ms = 0;
-+	u16 int_factor_c = 0;
-+
-+	if (!dec_ch || !dec_bw || !dec_offset) {
-+		rtw_warn_on(1);
-+		return _FALSE;
-+	}
-+
-+	RTW_INFO("%s: sel_ch:%u max_bw:%u e_flags:0x%02x d_flags:0x%02x cur_ch:%u within_sb:%d%s%s\n"
-+		, __func__, sel_ch, max_bw, e_flags, d_flags, cur_ch, rfctl->ch_sel_within_same_band
-+		, by_int_info ? " int" : "", mesh_only ? " mesh_only" : "");
-+
-+	/* full search and narrow bw judegement first to avoid potetial judegement timing issue */
-+	for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {
-+		if (!hal_is_bw_support(dvobj_get_primary_adapter(dvobj), bw))
-+			continue;
-+
-+		for (i = 0; i < rfctl->max_chan_nums; i++) {
-+			u32 non_ocp_ms = 0;
-+			u32 cac_ms = 0;
-+			u32 waiting_ms = 0;
-+			u16 int_factor = 0;
-+			bool dfs_ch;
-+			bool non_ocp;
-+			bool long_cac;
-+
-+			ch = rfctl->channel_set[i].ChannelNum;
-+			if (sel_ch) {
-+				if (ch != sel_ch)
-+					continue;
-+			} else if (rfctl->ch_sel_within_same_band && !rtw_is_same_band(cur_ch, ch))
-+				continue;
-+
-+			if (ch > 14) {
-+				if (bw > REGSTY_BW_5G(regsty))
-+					continue;
-+			} else {
-+				if (bw > REGSTY_BW_2G(regsty))
-+					continue;
-+			}
-+
-+			if (mesh_only && ch >= 5 && ch <= 9 && bw > CHANNEL_WIDTH_20)
-+				continue;
-+
-+			if (!rtw_get_offset_by_chbw(ch, bw, &offset))
-+				continue;
-+
-+			if (!rtw_chset_is_chbw_valid(rfctl->channel_set, ch, bw, offset, 0, 0))
-+				continue;
-+
-+			if ((e_flags & RTW_CHF_DFS) || (d_flags & RTW_CHF_DFS)) {
-+				dfs_ch = rtw_chset_is_dfs_chbw(rfctl->channel_set, ch, bw, offset);
-+				if (((e_flags & RTW_CHF_DFS) && !dfs_ch)
-+					|| ((d_flags & RTW_CHF_DFS) && dfs_ch))
-+					continue;
-+			}
-+
-+			if ((e_flags & RTW_CHF_LONG_CAC) || (d_flags & RTW_CHF_LONG_CAC)) {
-+				long_cac = rtw_is_long_cac_ch(ch, bw, offset, rtw_rfctl_get_dfs_domain(rfctl));
-+				if (((e_flags & RTW_CHF_LONG_CAC) && !long_cac)
-+					|| ((d_flags & RTW_CHF_LONG_CAC) && long_cac))
-+					continue;
-+			}
-+
-+			if ((e_flags & RTW_CHF_NON_OCP) || (d_flags & RTW_CHF_NON_OCP)) {
-+				non_ocp = rtw_chset_is_chbw_non_ocp(rfctl->channel_set, ch, bw, offset);
-+				if (((e_flags & RTW_CHF_NON_OCP) && !non_ocp)
-+					|| ((d_flags & RTW_CHF_NON_OCP) && non_ocp))
-+					continue;
-+			}
-+
-+			#ifdef CONFIG_DFS_MASTER
-+			waiting_ms = rtw_get_ch_waiting_ms(rfctl, ch, bw, offset, &non_ocp_ms, &cac_ms);
-+			#endif
-+
-+			#ifdef CONFIG_RTW_ACS
-+			if (by_int_info) {
-+				/* for now, consider only primary channel */
-+				int_factor = hal_data->acs.interference_time[i];
-+			}
-+			#endif
-+
-+			if (DBG_CHOOSE_SHORTEST_WAITING_CH)
-+				RTW_INFO("%s:%u,%u,%u %u(non_ocp:%u, cac:%u), int:%u\n"
-+					, __func__, ch, bw, offset, waiting_ms, non_ocp_ms, cac_ms, int_factor);
-+
-+			if (ch_c == 0
-+				/* first: smaller wating time */
-+				|| min_waiting_ms > waiting_ms
-+				/* then: less interference */
-+				|| (min_waiting_ms == waiting_ms && int_factor_c > int_factor)
-+				/* then: wider bw */
-+				|| (min_waiting_ms == waiting_ms && int_factor_c == int_factor && bw > bw_c)
-+				/* if all condition equal, same channel -> same band prefer */
-+				|| (min_waiting_ms == waiting_ms && int_factor_c == int_factor && bw == bw_c
-+					&& ((cur_ch != ch_c && cur_ch == ch)
-+						|| (!rtw_is_same_band(cur_ch, ch_c) && rtw_is_same_band(cur_ch, ch)))
-+					)
-+			) {
-+				ch_c = ch;
-+				bw_c = bw;
-+				offset_c = offset;
-+				min_waiting_ms = waiting_ms;
-+				int_factor_c = int_factor;
-+			}
-+		}
-+	}
-+
-+	if (ch_c != 0) {
-+		RTW_INFO("%s: select %u,%u,%u waiting_ms:%u\n"
-+			, __func__, ch_c, bw_c, offset_c, min_waiting_ms);
-+		*dec_ch = ch_c;
-+		*dec_bw = bw_c;
-+		*dec_offset = offset_c;
-+		return _TRUE;
-+	} else {
-+		RTW_INFO("%s: not found\n", __func__);
-+		if (d_flags == 0)
-+			rtw_warn_on(1);
-+	}
-+
-+	return _FALSE;
-+}
-+
-+#ifdef CONFIG_PROC_DEBUG
-+#define RTW_CHF_FMT "%s%s%s%s%s%s"
-+
-+#define RTW_CHF_ARG_NO_IR(flags)		(flags & RTW_CHF_NO_IR) ? " NO_IR" : ""
-+#define RTW_CHF_ARG_DFS(flags)			, (flags & RTW_CHF_DFS) ? " DFS" : ""
-+#define RTW_CHF_ARG_NO_HT40U(flags)		, (flags & RTW_CHF_NO_HT40U) ? " NO_40M+" : ""
-+#define RTW_CHF_ARG_NO_HT40L(flags)		, (flags & RTW_CHF_NO_HT40L) ? " NO_40M-" : ""
-+#define RTW_CHF_ARG_NO_80MHZ(flags)		, (flags & RTW_CHF_NO_80MHZ) ? " NO_80M" : ""
-+#define RTW_CHF_ARG_NO_160MHZ(flags)	, (flags & RTW_CHF_NO_160MHZ) ? " NO_160M" : ""
-+
-+#define RTW_CHF_ARG(flags) \
-+	RTW_CHF_ARG_NO_IR(flags) \
-+	RTW_CHF_ARG_DFS(flags) \
-+	RTW_CHF_ARG_NO_HT40U(flags) \
-+	RTW_CHF_ARG_NO_HT40L(flags) \
-+	RTW_CHF_ARG_NO_80MHZ(flags) \
-+	RTW_CHF_ARG_NO_160MHZ(flags)
-+
-+void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set, u8 chset_num)
-+{
-+	char buf[8];
-+	u8 i;
-+
-+	RTW_PRINT_SEL(sel, "%-3s %-4s %-4s flags\n", "ch", "freq", "nocp");
-+
-+	for (i = 0; i < MAX_CHANNEL_NUM && i < chset_num && ch_set[i].ChannelNum != 0; i++) {
-+		#ifdef CONFIG_DFS_MASTER
-+		if ((ch_set[i].flags & RTW_CHF_DFS) && CH_IS_NON_OCP(&ch_set[i]))
-+			snprintf(buf, 8, "%d", rtw_systime_to_ms(ch_set[i].non_ocp_end_time - rtw_get_current_time()) / 1000);
-+		else
-+		#endif
-+			snprintf(buf, 8, "0");
-+
-+		RTW_PRINT_SEL(sel, "%3u %4u %4s"RTW_CHF_FMT"\n"
-+			, ch_set[i].ChannelNum, rtw_ch2freq(ch_set[i].ChannelNum), buf
-+			, RTW_CHF_ARG(ch_set[i].flags)
-+		);
-+	}
-+
-+	RTW_PRINT_SEL(sel, "total ch number:%d\n", i);
-+}
-+
-+void dump_cur_chset(void *sel, struct rf_ctl_t *rfctl)
-+{
-+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
-+	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
-+	struct get_chplan_resp *chplan;
-+	int i;
-+
-+	if (rtw_get_chplan_cmd(dvobj_get_primary_adapter(dvobj), RTW_CMDF_WAIT_ACK, &chplan) == _FAIL)
-+		return;
-+
-+	RTW_PRINT_SEL(sel, "regd_src:%s(%d)\n", regd_src_str(chplan->regd_src), chplan->regd_src);
-+
-+	if (chplan->has_country)
-+		dump_country_chplan(sel, &chplan->country_ent);
-+	else
-+		RTW_PRINT_SEL(sel, "chplan:0x%02X\n", chplan->channel_plan);
-+
-+#if CONFIG_TXPWR_LIMIT
-+	RTW_PRINT_SEL(sel, "PLS regd:%s\n", chplan->regd_name);
-+#endif
-+
-+#ifdef CONFIG_DFS_MASTER
-+	RTW_PRINT_SEL(sel, "dfs_domain:%s(%u)\n", rtw_dfs_regd_str(chplan->dfs_domain), chplan->dfs_domain);
-+#endif
-+
-+	for (i = 0; i < MAX_CHANNEL_NUM; i++)
-+		if (regsty->excl_chs[i] != 0)
-+			break;
-+
-+	if (i < MAX_CHANNEL_NUM) {
-+		RTW_PRINT_SEL(sel, "excl_chs:");
-+		for (i = 0; i < MAX_CHANNEL_NUM; i++) {
-+			if (regsty->excl_chs[i] == 0)
-+				break;
-+			_RTW_PRINT_SEL(sel, "%u ", regsty->excl_chs[i]);
-+		}
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+
-+	dump_chset(sel, chplan->chset, chplan->chset_num);
-+
-+	rtw_vmfree(chplan, sizeof(struct get_chplan_resp) + sizeof(RT_CHANNEL_INFO) * chplan->chset_num);
-+}
-+#endif
-+
-+/*
-+ * Search the @param ch in given @param ch_set
-+ * @ch_set: the given channel set
-+ * @ch: the given channel number
-+ *
-+ * return the index of channel_num in channel_set, -1 if not found
-+ */
-+int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch)
-+{
-+	int i;
-+
-+	if (ch == 0)
-+		return -1;
-+
-+	for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
-+		if (ch == ch_set[i].ChannelNum)
-+			return i;
-+	}
-+
-+	return -1;
-+}
-+
-+/*
-+ * Check if the @param ch, bw, offset is valid for the given @param ch_set
-+ * @ch_set: the given channel set
-+ * @ch: the given channel number
-+ * @bw: the given bandwidth
-+ * @offset: the given channel offset
-+ *
-+ * return valid (1) or not (0)
-+ */
-+u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset
-+	, bool allow_primary_passive, bool allow_passive)
-+{
-+	u8 cch;
-+	u8 *op_chs;
-+	u8 op_ch_num;
-+	u8 valid = 0;
-+	int i;
-+	int ch_idx;
-+
-+	cch = rtw_get_center_ch(ch, bw, offset);
-+
-+	if (!rtw_get_op_chs_by_cch_bw(cch, bw, &op_chs, &op_ch_num))
-+		goto exit;
-+
-+	for (i = 0; i < op_ch_num; i++) {
-+		if (0)
-+			RTW_INFO("%u,%u,%u - cch:%u, bw:%u, op_ch:%u\n", ch, bw, offset, cch, bw, *(op_chs + i));
-+		ch_idx = rtw_chset_search_ch(ch_set, *(op_chs + i));
-+		if (ch_idx == -1)
-+			break;
-+		if (ch_set[ch_idx].flags & RTW_CHF_NO_IR) {
-+			if ((!allow_primary_passive && ch_set[ch_idx].ChannelNum == ch)
-+				|| (!allow_passive && ch_set[ch_idx].ChannelNum != ch))
-+			break;
-+		}
-+		if (bw >= CHANNEL_WIDTH_40) {
-+			if ((ch_set[ch_idx].flags & RTW_CHF_NO_HT40U) && i % 2 == 0)
-+				break;
-+			if ((ch_set[ch_idx].flags & RTW_CHF_NO_HT40L) && i % 2 == 1)
-+				break;
-+		}
-+		if (bw >= CHANNEL_WIDTH_80 && (ch_set[ch_idx].flags & RTW_CHF_NO_80MHZ))
-+			break;
-+		if (bw >= CHANNEL_WIDTH_160 && (ch_set[ch_idx].flags & RTW_CHF_NO_160MHZ))
-+			break;
-+	}
-+
-+	if (op_ch_num != 0 && i == op_ch_num)
-+		valid = 1;
-+
-+exit:
-+	return valid;
-+}
-+
-+/**
-+ * rtw_chset_sync_chbw - obey g_ch, adjust g_bw, g_offset, bw, offset to fit in channel plan
-+ * @ch_set: channel plan to check
-+ * @req_ch: pointer of the request ch, may be modified further
-+ * @req_bw: pointer of the request bw, may be modified further
-+ * @req_offset: pointer of the request offset, may be modified further
-+ * @g_ch: pointer of the ongoing group ch
-+ * @g_bw: pointer of the ongoing group bw, may be modified further
-+ * @g_offset: pointer of the ongoing group offset, may be modified further
-+ * @allow_primary_passive: if allow passive primary ch when deciding chbw
-+ * @allow_passive: if allow passive ch (not primary) when deciding chbw
-+ */
-+void rtw_chset_sync_chbw(RT_CHANNEL_INFO *ch_set, u8 *req_ch, u8 *req_bw, u8 *req_offset
-+	, u8 *g_ch, u8 *g_bw, u8 *g_offset, bool allow_primary_passive, bool allow_passive)
-+{
-+	u8 r_ch, r_bw, r_offset;
-+	u8 u_ch, u_bw, u_offset;
-+	u8 cur_bw = *req_bw;
-+
-+	while (1) {
-+		r_ch = *req_ch;
-+		r_bw = cur_bw;
-+		r_offset = *req_offset;
-+		u_ch = *g_ch;
-+		u_bw = *g_bw;
-+		u_offset = *g_offset;
-+
-+		rtw_sync_chbw(&r_ch, &r_bw, &r_offset, &u_ch, &u_bw, &u_offset);
-+
-+		if (rtw_chset_is_chbw_valid(ch_set, r_ch, r_bw, r_offset, allow_primary_passive, allow_passive))
-+			break;
-+		if (cur_bw == CHANNEL_WIDTH_20) {
-+			rtw_warn_on(1);
-+			break;
-+		}
-+		cur_bw--;
-+	};
-+
-+	*req_ch = r_ch;
-+	*req_bw = r_bw;
-+	*req_offset = r_offset;
-+	*g_ch = u_ch;
-+	*g_bw = u_bw;
-+	*g_offset = u_offset;
-+}
-+
-+/*
-+ * Check the @param ch is fit with setband setting of @param adapter
-+ * @adapter: the given adapter
-+ * @ch: the given channel number
-+ *
-+ * return _TRUE when check valid, _FALSE not valid
-+ */
-+bool rtw_mlme_band_check(_adapter *adapter, const u32 ch)
-+{
-+	if (adapter->setband == WIFI_FREQUENCY_BAND_AUTO /* 2.4G and 5G */
-+		|| (adapter->setband == WIFI_FREQUENCY_BAND_2GHZ && ch < 35) /* 2.4G only */
-+		|| (adapter->setband == WIFI_FREQUENCY_BAND_5GHZ && ch > 35) /* 5G only */
-+	)
-+		return _TRUE;
-+	return _FALSE;
-+}
-+inline void RTW_SET_SCAN_BAND_SKIP(_adapter *padapter, int skip_band)
-+{
-+	int bs = ATOMIC_READ(&padapter->bandskip);
-+
-+	bs |= skip_band;
-+	ATOMIC_SET(&padapter->bandskip, bs);
-+}
-+
-+inline void RTW_CLR_SCAN_BAND_SKIP(_adapter *padapter, int skip_band)
-+{
-+	int bs = ATOMIC_READ(&padapter->bandskip);
-+
-+	bs &= ~(skip_band);
-+	ATOMIC_SET(&padapter->bandskip, bs);
-+}
-+inline int RTW_GET_SCAN_BAND_SKIP(_adapter *padapter)
-+{
-+	return ATOMIC_READ(&padapter->bandskip);
-+}
-+
-+#define RTW_IS_SCAN_BAND_SKIP(padapter, skip_band) (ATOMIC_READ(&padapter->bandskip) & (skip_band))
-+
-+bool rtw_mlme_ignore_chan(_adapter *adapter, const u32 ch)
-+{
-+	if (RTW_IS_SCAN_BAND_SKIP(adapter, BAND_24G) && ch < 35) /* SKIP 2.4G Band channel */
-+		return _TRUE;
-+	if (RTW_IS_SCAN_BAND_SKIP(adapter, BAND_5G)  && ch > 35) /* SKIP 5G Band channel */
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+
-+/****************************************************************************
-+
-+Following are the initialization functions for WiFi MLME
-+
-+*****************************************************************************/
-+
-+int init_hw_mlme_ext(_adapter *padapter)
-+{
-+	struct	mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+	u8 rx_bar_enble = _TRUE;
-+
-+	/*
-+	 * Sync driver status and hardware setting
-+	 */
-+
-+	/* Modify to make sure first time change channel(band) would be done properly */
-+	pHalData->current_channel = 0;
-+	pHalData->current_channel_bw = CHANNEL_WIDTH_MAX;
-+	#if CONFIG_IEEE80211_BAND_5GHZ
-+	pHalData->current_band_type = BAND_MAX;
-+	#else
-+	pHalData->current_band_type = BAND_ON_2_4G;
-+	#endif
-+
-+	/* set_opmode_cmd(padapter, infra_client_with_mlme); */ /* removed */
-+	rtw_hal_set_hwreg(padapter, HW_VAR_ENABLE_RX_BAR, &rx_bar_enble);
-+	set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
-+
-+	return _SUCCESS;
-+}
-+
-+void init_mlme_default_rate_set(_adapter *padapter)
-+{
-+	struct	mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	unsigned	char end_set[1] = {0xff};
-+	u8	offset_datarate = 0;
-+	u8	offset_basicrate = 0;
-+#ifdef CONFIG_80211N_HT
-+	unsigned char	supported_mcs_set[16] = {0xff, 0xff, 0xff, 0xff, 0x00, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
-+#endif
-+
-+	if (IsSupportedTxCCK(padapter->registrypriv.wireless_mode)) {
-+
-+		unsigned char	datarate_b[B_MODE_RATE_NUM] ={_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_};
-+		_rtw_memcpy(pmlmeext->datarate, datarate_b, B_MODE_RATE_NUM);
-+		_rtw_memcpy(pmlmeext->basicrate, datarate_b, B_MODE_RATE_NUM);
-+		offset_datarate += B_MODE_RATE_NUM;
-+		offset_basicrate += B_MODE_RATE_NUM;
-+		RTW_INFO("%s: support CCK\n", __func__);
-+	}
-+	if(IsSupportedTxOFDM(padapter->registrypriv.wireless_mode)) {
-+		unsigned char	datarate_g[G_MODE_RATE_NUM] ={_6M_RATE_, _9M_RATE_, _12M_RATE_, _18M_RATE_,_24M_RATE_, _36M_RATE_, _48M_RATE_, _54M_RATE_};
-+		unsigned char	basicrate_g[G_MODE_BASIC_RATE_NUM] = {_6M_RATE_, _12M_RATE_, _24M_RATE_};
-+		_rtw_memcpy(pmlmeext->datarate + offset_datarate, datarate_g, G_MODE_RATE_NUM);
-+		_rtw_memcpy(pmlmeext->basicrate + offset_basicrate,basicrate_g, G_MODE_BASIC_RATE_NUM);
-+		offset_datarate += G_MODE_RATE_NUM;
-+		offset_basicrate += G_MODE_BASIC_RATE_NUM;
-+		RTW_INFO("%s: support OFDM\n", __func__);
-+
-+	}
-+	_rtw_memcpy(pmlmeext->datarate + offset_datarate, end_set, 1);
-+	_rtw_memcpy(pmlmeext->basicrate + offset_basicrate, end_set, 1);
-+
-+#ifdef CONFIG_80211N_HT
-+	if( padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode))
-+		_rtw_memcpy(pmlmeext->default_supported_mcs_set, supported_mcs_set, sizeof(pmlmeext->default_supported_mcs_set));
-+#endif
-+}
-+
-+static void init_mlme_ext_priv_value(_adapter *padapter)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	ATOMIC_SET(&pmlmeext->event_seq, 0);
-+	pmlmeext->mgnt_seq = 0;/* reset to zero when disconnect at client mode */
-+#ifdef CONFIG_IEEE80211W
-+	pmlmeext->sa_query_seq = 0;
-+#endif
-+	pmlmeext->cur_channel = padapter->registrypriv.channel;
-+	pmlmeext->cur_bwmode = CHANNEL_WIDTH_20;
-+	pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+
-+	pmlmeext->retry = 0;
-+
-+	pmlmeext->cur_wireless_mode = padapter->registrypriv.wireless_mode;
-+	init_mlme_default_rate_set(padapter);
-+
-+	if ((pmlmeext->cur_channel > 14) || ((padapter->registrypriv.wireless_mode & WIRELESS_11B) == 0))
-+		pmlmeext->tx_rate = IEEE80211_OFDM_RATE_6MB;
-+	else
-+		pmlmeext->tx_rate = IEEE80211_CCK_RATE_1MB;
-+
-+	mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE);
-+	pmlmeext->sitesurvey_res.channel_idx = 0;
-+	pmlmeext->sitesurvey_res.bss_cnt = 0;
-+	pmlmeext->sitesurvey_res.scan_ch_ms = SURVEY_TO;
-+	pmlmeext->sitesurvey_res.rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID;
-+	pmlmeext->sitesurvey_res.rx_ampdu_size = RX_AMPDU_SIZE_INVALID;
-+#ifdef CONFIG_SCAN_BACKOP
-+	mlmeext_assign_scan_backop_flags_sta(pmlmeext, /*SS_BACKOP_EN|*/SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME);
-+	#ifdef CONFIG_AP_MODE
-+		#ifdef CONFIG_CUSTOMER_EZVIZ_CHIME2
-+			mlmeext_assign_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN | SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME | SS_BACKOP_EN_NL);
-+		#else
-+			mlmeext_assign_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN | SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME);
-+		#endif
-+	#endif
-+	#ifdef CONFIG_RTW_MESH
-+	mlmeext_assign_scan_backop_flags_mesh(pmlmeext, /*SS_BACKOP_EN | */SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME);
-+	#endif
-+	pmlmeext->sitesurvey_res.scan_cnt = 0;
-+	pmlmeext->sitesurvey_res.scan_cnt_max = RTW_SCAN_NUM_OF_CH;
-+	pmlmeext->sitesurvey_res.backop_ms = RTW_BACK_OP_CH_MS;
-+#endif
-+#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
-+	pmlmeext->sitesurvey_res.is_sw_antdiv_bl_scan = 0;
-+#endif
-+	pmlmeext->scan_abort = _FALSE;
-+
-+	pmlmeinfo->state = WIFI_FW_NULL_STATE;
-+	pmlmeinfo->reauth_count = 0;
-+	pmlmeinfo->reassoc_count = 0;
-+	pmlmeinfo->link_count = 0;
-+	pmlmeinfo->auth_seq = 0;
-+	pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open;
-+	pmlmeinfo->key_index = 0;
-+	pmlmeinfo->iv = 0;
-+
-+	pmlmeinfo->enc_algo = _NO_PRIVACY_;
-+	pmlmeinfo->authModeToggle = 0;
-+
-+	_rtw_memset(pmlmeinfo->chg_txt, 0, 128);
-+
-+	pmlmeinfo->slotTime = SHORT_SLOT_TIME;
-+	pmlmeinfo->preamble_mode = PREAMBLE_AUTO;
-+
-+	pmlmeinfo->dialogToken = 0;
-+
-+	pmlmeext->action_public_rxseq = 0xffff;
-+	pmlmeext->action_public_dialog_token = 0xff;
-+#ifdef ROKU_PRIVATE
-+/*infra mode, used to store AP's info*/
-+	_rtw_memset(pmlmeinfo->SupportedRates_infra_ap, 0, NDIS_802_11_LENGTH_RATES_EX);
-+	pmlmeinfo->ht_vht_received = 0;
-+#endif /* ROKU_PRIVATE */
-+}
-+
-+void init_mlme_ext_timer(_adapter *padapter)
-+{
-+	struct	mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+
-+	rtw_init_timer(&pmlmeext->survey_timer, padapter, survey_timer_hdl, padapter);
-+	rtw_init_timer(&pmlmeext->link_timer, padapter, link_timer_hdl, padapter);
-+#ifdef CONFIG_RTW_80211R
-+	rtw_init_timer(&pmlmeext->ft_link_timer, padapter, rtw_ft_link_timer_hdl, padapter);
-+	rtw_init_timer(&pmlmeext->ft_roam_timer, padapter, rtw_ft_roam_timer_hdl, padapter);
-+#endif
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	rtw_init_timer(&pmlmeext->rson_scan_timer, padapter, rson_timer_hdl, padapter);
-+#endif
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	rtw_init_timer(&pmlmeext->tbtx_xmit_timer, padapter, rtw_tbtx_xmit_timer_hdl, padapter);
-+	rtw_init_timer(&pmlmeext->tbtx_token_dispatch_timer, padapter, rtw_tbtx_token_dispatch_timer_hdl, padapter);
-+#endif
-+#ifdef CONFIG_DFS
-+	rtw_init_timer(&pmlmeext->csa_timer, padapter->pnetdev, csa_timer_hdl, padapter);
-+#endif
-+}
-+
-+int	init_mlme_ext_priv(_adapter *padapter)
-+{
-+	int	res = _SUCCESS;
-+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
-+	/* _rtw_memset((u8 *)pmlmeext, 0, sizeof(struct mlme_ext_priv)); */
-+
-+	pmlmeext->padapter = padapter;
-+
-+	/* fill_fwpriv(padapter, &(pmlmeext->fwpriv)); */
-+
-+	init_mlme_ext_priv_value(padapter);
-+	pmlmeinfo->bAcceptAddbaReq = pregistrypriv->bAcceptAddbaReq;
-+
-+	init_mlme_ext_timer(padapter);
-+
-+#ifdef CONFIG_AP_MODE
-+	init_mlme_ap_info(padapter);
-+#endif
-+
-+	pmlmeext->last_scan_time = 0;
-+	pmlmeext->mlmeext_init = _TRUE;
-+
-+
-+#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-+	pmlmeext->active_keep_alive_check = _TRUE;
-+#else
-+	pmlmeext->active_keep_alive_check = _FALSE;
-+#endif
-+
-+#ifdef DBG_FIXED_CHAN
-+	pmlmeext->fixed_chan = 0xFF;
-+#endif
-+
-+	pmlmeext->tsf_update_pause_factor = pregistrypriv->tsf_update_pause_factor;
-+	pmlmeext->tsf_update_restore_factor = pregistrypriv->tsf_update_restore_factor;
-+
-+#ifdef CONFIG_SUPPORT_STATIC_SMPS
-+	pmlmeext->ssmps_en = _FALSE;
-+	pmlmeext->ssmps_tx_tp_th = SSMPS_TX_TP_TH;/*Mbps*/
-+	pmlmeext->ssmps_rx_tp_th = SSMPS_RX_TP_TH;/*Mbps*/
-+	#ifdef DBG_STATIC_SMPS
-+	pmlmeext->ssmps_test = _FALSE;
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_CTRL_TXSS_BY_TP
-+	pmlmeext->txss_ctrl_en = _TRUE;
-+	pmlmeext->txss_tp_th = TXSS_TP_TH;
-+	pmlmeext->txss_tp_chk_cnt = TXSS_TP_CHK_CNT;
-+#endif
-+
-+	return res;
-+
-+}
-+
-+void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext)
-+{
-+	_adapter *padapter = pmlmeext->padapter;
-+
-+	if (!padapter)
-+		return;
-+
-+	if (rtw_is_drv_stopped(padapter)) {
-+		_cancel_timer_ex(&pmlmeext->survey_timer);
-+		_cancel_timer_ex(&pmlmeext->link_timer);
-+#ifdef CONFIG_DFS
-+		_cancel_timer_ex(&pmlmeext->csa_timer);
-+#endif /* CONFIG_DFS */
-+	}
-+}
-+
-+#ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL
-+static u8 cmp_pkt_chnl_diff(_adapter *padapter, u8 *pframe, uint packet_len)
-+{
-+	/* if the channel is same, return 0. else return channel differential	 */
-+	uint len;
-+	u8 channel;
-+	u8 *p;
-+
-+	p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, _DSSET_IE_, &len, packet_len - _BEACON_IE_OFFSET_);
-+	if (p) {
-+		channel = *(p + 2);
-+		if (padapter->mlmeextpriv.cur_channel >= channel)
-+			return padapter->mlmeextpriv.cur_channel - channel;
-+		else
-+			return channel - padapter->mlmeextpriv.cur_channel;
-+	} else
-+		return 0;
-+}
-+#endif /* CONFIG_PATCH_JOIN_WRONG_CHANNEL */
-+
-+static void _mgt_dispatcher(_adapter *padapter, struct mlme_handler *ptable, union recv_frame *precv_frame)
-+{
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+
-+	if (ptable->func) {
-+		/* receive the frames that ra(a1) is my address or ra(a1) is bc address. */
-+		if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) &&
-+		    !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN))
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+		{
-+			struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+
-+			if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) != _TRUE)
-+				return;
-+
-+		    if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+				return;
-+
-+		    if ( pwdev_priv->pno_mac_addr[0] == 0xFF)
-+				return;
-+
-+		    if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_pno_mac_addr(padapter), ETH_ALEN))
-+				return;
-+		}
-+#else
-+			return;
-+#endif
-+
-+		ptable->func(padapter, precv_frame);
-+	}
-+
-+}
-+
-+void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	int index;
-+	struct mlme_handler *ptable;
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(pframe));
-+	struct recv_priv  *precvpriv = &padapter->recvpriv;
-+
-+
-+#if 0
-+	{
-+		u8 *pbuf;
-+		pbuf = GetAddr1Ptr(pframe);
-+		RTW_INFO("A1-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));
-+		pbuf = get_addr2_ptr(pframe);
-+		RTW_INFO("A2-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));
-+		pbuf = GetAddr3Ptr(pframe);
-+		RTW_INFO("A3-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));
-+	}
-+#endif
-+
-+	if (GetFrameType(pframe) != WIFI_MGT_TYPE) {
-+		return;
-+	}
-+
-+	/* receive the frames that ra(a1) is my address or ra(a1) is bc address. */
-+	if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) &&
-+	    !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN))
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+		{
-+			struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+
-+			if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) != _TRUE)
-+				return;
-+
-+			if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+				return;
-+
-+			if ( pwdev_priv->pno_mac_addr[0] == 0xFF)
-+				return;
-+
-+			if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_pno_mac_addr(padapter), ETH_ALEN))
-+				return;
-+		}
-+#else
-+		return;
-+#endif
-+
-+	ptable = mlme_sta_tbl;
-+
-+	index = get_frame_sub_type(pframe) >> 4;
-+
-+#ifdef CONFIG_TDLS
-+	if ((index << 4) == WIFI_ACTION) {
-+		/* category==public (4), action==TDLS_DISCOVERY_RESPONSE */
-+		if (*(pframe + 24) == RTW_WLAN_CATEGORY_PUBLIC && *(pframe + 25) == TDLS_DISCOVERY_RESPONSE) {
-+			RTW_INFO("[TDLS] Recv %s from "MAC_FMT"\n", rtw_tdls_action_txt(TDLS_DISCOVERY_RESPONSE), MAC_ARG(get_addr2_ptr(pframe)));
-+			On_TDLS_Dis_Rsp(padapter, precv_frame);
-+		}
-+	}
-+#endif /* CONFIG_TDLS */
-+
-+	if (index >= (sizeof(mlme_sta_tbl) / sizeof(struct mlme_handler))) {
-+		return;
-+	}
-+	ptable += index;
-+
-+#if 1
-+	if (psta != NULL) {
-+		if (GetRetry(pframe)) {
-+			if (precv_frame->u.hdr.attrib.seq_num == psta->RxMgmtFrameSeqNum) {
-+				/* drop the duplicate management frame */
-+				precvpriv->dbg_rx_dup_mgt_frame_drop_count++;
-+				RTW_INFO("Drop duplicate management frame with seq_num = %d.\n", precv_frame->u.hdr.attrib.seq_num);
-+				return;
-+			}
-+		}
-+		psta->RxMgmtFrameSeqNum = precv_frame->u.hdr.attrib.seq_num;
-+	}
-+#else
-+
-+	if (GetRetry(pframe)) {
-+		/* return; */
-+	}
-+#endif
-+
-+#ifdef CONFIG_AP_MODE
-+	switch (get_frame_sub_type(pframe)) {
-+	case WIFI_AUTH:
-+		if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter))
-+			ptable->func = &OnAuth;
-+		else
-+			ptable->func = &OnAuthClient;
-+		fallthrough;
-+	case WIFI_ASSOCREQ:
-+	case WIFI_REASSOCREQ:
-+		_mgt_dispatcher(padapter, ptable, precv_frame);
-+		#ifdef CONFIG_HOSTAPD_MLME
-+		if (MLME_IS_AP(padapter))
-+			rtw_hostapd_mlme_rx(padapter, precv_frame);
-+		#endif
-+		break;
-+	case WIFI_PROBEREQ:
-+		_mgt_dispatcher(padapter, ptable, precv_frame);
-+		#ifdef CONFIG_HOSTAPD_MLME
-+		if (MLME_IS_AP(padapter))
-+			rtw_hostapd_mlme_rx(padapter, precv_frame);
-+		#endif
-+		break;
-+	case WIFI_BEACON:
-+		_mgt_dispatcher(padapter, ptable, precv_frame);
-+		break;
-+	case WIFI_ACTION:
-+		_mgt_dispatcher(padapter, ptable, precv_frame);
-+		break;
-+	default:
-+		_mgt_dispatcher(padapter, ptable, precv_frame);
-+		#ifdef CONFIG_HOSTAPD_MLME
-+		if (MLME_IS_AP(padapter))
-+			rtw_hostapd_mlme_rx(padapter, precv_frame);
-+		#endif
-+		break;
-+	}
-+#else
-+
-+	_mgt_dispatcher(padapter, ptable, precv_frame);
-+
-+#endif
-+
-+}
-+
-+#ifdef CONFIG_P2P
-+u32 p2p_listen_state_process(_adapter *padapter, unsigned char *da)
-+{
-+	bool response = _TRUE;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) {
-+		if (rtw_cfg80211_get_is_roch(padapter) == _FALSE
-+			|| rtw_get_oper_ch(padapter) != padapter->wdinfo.listen_channel
-+			|| adapter_wdev_data(padapter)->p2p_enabled == _FALSE
-+			|| padapter->mlmepriv.wps_probe_resp_ie == NULL
-+			|| padapter->mlmepriv.p2p_probe_resp_ie == NULL
-+		) {
-+#ifdef CONFIG_DEBUG_CFG80211
-+			RTW_INFO(ADPT_FMT" DON'T issue_probersp_p2p: p2p_enabled:%d, wps_probe_resp_ie:%p, p2p_probe_resp_ie:%p\n"
-+				, ADPT_ARG(padapter)
-+				, adapter_wdev_data(padapter)->p2p_enabled
-+				, padapter->mlmepriv.wps_probe_resp_ie
-+				, padapter->mlmepriv.p2p_probe_resp_ie);
-+			RTW_INFO(ADPT_FMT" DON'T issue_probersp_p2p: is_ro_ch:%d, op_ch:%d, p2p_listen_channel:%d\n"
-+				, ADPT_ARG(padapter)
-+				, rtw_cfg80211_get_is_roch(padapter)
-+				, rtw_get_oper_ch(padapter)
-+				, padapter->wdinfo.listen_channel);
-+#endif
-+			response = _FALSE;
-+		}
-+	} else
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+		if (padapter->wdinfo.driver_interface == DRIVER_WEXT) {
-+			/*	do nothing if the device name is empty */
-+			if (!padapter->wdinfo.device_name_len)
-+				response	= _FALSE;
-+		}
-+
-+	if (response == _TRUE)
-+		issue_probersp_p2p(padapter, da);
-+
-+	return _SUCCESS;
-+}
-+#endif /* CONFIG_P2P */
-+
-+
-+/****************************************************************************
-+
-+Following are the callback functions for each subtype of the management frames
-+
-+*****************************************************************************/
-+
-+unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	unsigned int	ielen;
-+	unsigned char	*p;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX	*cur = &(pmlmeinfo->network);
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	uint len = precv_frame->u.hdr.len;
-+	u8 is_valid_p2p_probereq = _FALSE;
-+
-+#ifdef CONFIG_ATMEL_RC_PATCH
-+	u8 *target_ie = NULL, *wps_ie = NULL;
-+	u8 *start;
-+	uint search_len = 0, wps_ielen = 0, target_ielen = 0;
-+	struct sta_info	*psta;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+#endif
-+
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
-+	u8 wifi_test_chk_rate = 1;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if ((pwdinfo->driver_interface == DRIVER_CFG80211)
-+	    && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
-+	    && (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_PROBE_REQ) == _TRUE)
-+	) {
-+		rtw_cfg80211_rx_probe_request(padapter, precv_frame);
-+		return _SUCCESS;
-+	}
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) &&
-+	    !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) &&
-+	    !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) &&
-+	    !rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) &&
-+	    !rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN)
-+	   ) {
-+		/*	Commented by Albert 2011/03/17 */
-+		/*	mcs_rate = 0->CCK 1M rate */
-+		/*	mcs_rate = 1->CCK 2M rate */
-+		/*	mcs_rate = 2->CCK 5.5M rate */
-+		/*	mcs_rate = 3->CCK 11M rate */
-+		/*	In the P2P mode, the driver should not support the CCK rate */
-+
-+		/*	Commented by Kurt 2012/10/16 */
-+		/*	IOT issue: Google Nexus7 use 1M rate to send p2p_probe_req after GO nego completed and Nexus7 is client */
-+		if (padapter->registrypriv.wifi_spec == 1) {
-+			if (pattrib->data_rate <= DESC_RATE11M)
-+				wifi_test_chk_rate = 0;
-+		}
-+
-+		if (wifi_test_chk_rate == 1) {
-+			is_valid_p2p_probereq = process_probe_req_p2p_ie(pwdinfo, pframe, len);
-+			if (is_valid_p2p_probereq == _TRUE) {
-+				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) {
-+					/* FIXME */
-+					if (padapter->wdinfo.driver_interface == DRIVER_WEXT)
-+						report_survey_event(padapter, precv_frame);
-+
-+					p2p_listen_state_process(padapter,  get_sa(pframe));
-+
-+					return _SUCCESS;
-+				}
-+
-+				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
-+					goto _continue;
-+			}
-+		}
-+	}
-+
-+_continue:
-+#endif /* CONFIG_P2P */
-+
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
-+		return _SUCCESS;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE &&
-+	    check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE | WIFI_MESH_STATE) == _FALSE)
-+		return _SUCCESS;
-+
-+
-+	/* RTW_INFO("+OnProbeReq\n"); */
-+
-+
-+#ifdef CONFIG_ATMEL_RC_PATCH
-+	wps_ie = rtw_get_wps_ie(
-+			      pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_,
-+			      len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_,
-+			      NULL, &wps_ielen);
-+	if (wps_ie)
-+		target_ie = rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_MANUFACTURER, NULL, &target_ielen);
-+	if ((target_ie && (target_ielen == 4)) && (_TRUE == _rtw_memcmp((void *)target_ie, "Ozmo", 4))) {
-+		/* psta->flag_atmel_rc = 1; */
-+		unsigned char *sa_addr = get_sa(pframe);
-+		printk("%s: Find Ozmo RC -- %02x:%02x:%02x:%02x:%02x:%02x  \n\n",
-+		       __func__, *sa_addr, *(sa_addr + 1), *(sa_addr + 2), *(sa_addr + 3), *(sa_addr + 4), *(sa_addr + 5));
-+		_rtw_memcpy(pstapriv->atmel_rc_pattern, get_sa(pframe), ETH_ALEN);
-+	}
-+#endif
-+
-+
-+#ifdef CONFIG_AUTO_AP_MODE
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE &&
-+	    pmlmepriv->cur_network.join_res == _TRUE) {
-+		_irqL	irqL;
-+		struct sta_info	*psta;
-+		u8 *mac_addr, *peer_addr;
-+		struct sta_priv *pstapriv = &padapter->stapriv;
-+		u8 RC_OUI[4] = {0x00, 0xE0, 0x4C, 0x0A};
-+		/* EID[1] + EID_LEN[1] + RC_OUI[4] + MAC[6] + PairingID[2] + ChannelNum[2] */
-+
-+		p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, (int *)&ielen,
-+			       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
-+
-+		if (!p || ielen != 14)
-+			goto _non_rc_device;
-+
-+		if (!_rtw_memcmp(p + 2, RC_OUI, sizeof(RC_OUI)))
-+			goto _non_rc_device;
-+
-+		if (!_rtw_memcmp(p + 6, get_sa(pframe), ETH_ALEN)) {
-+			RTW_INFO("%s, do rc pairing ("MAC_FMT"), but mac addr mismatch!("MAC_FMT")\n", __FUNCTION__,
-+				 MAC_ARG(get_sa(pframe)), MAC_ARG(p + 6));
-+
-+			goto _non_rc_device;
-+		}
-+
-+		RTW_INFO("%s, got the pairing device("MAC_FMT")\n", __FUNCTION__,  MAC_ARG(get_sa(pframe)));
-+
-+		/* new a station */
-+		psta = rtw_get_stainfo(pstapriv, get_sa(pframe));
-+		if (psta == NULL) {
-+			/* allocate a new one */
-+			RTW_INFO("going to alloc stainfo for rc="MAC_FMT"\n",  MAC_ARG(get_sa(pframe)));
-+			psta = rtw_alloc_stainfo(pstapriv, get_sa(pframe));
-+			if (psta == NULL) {
-+				/* TODO: */
-+				RTW_INFO(" Exceed the upper limit of supported clients...\n");
-+				return _SUCCESS;
-+			}
-+
-+			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+			if (rtw_is_list_empty(&psta->asoc_list)) {
-+				psta->expire_to = pstapriv->expire_to;
-+				rtw_list_insert_tail(&psta->asoc_list, &pstapriv->asoc_list);
-+				pstapriv->asoc_list_cnt++;
-+				#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+				if (psta->tbtx_enable)
-+					pstapriv->tbtx_asoc_list_cnt++;
-+				#endif
-+			}
-+			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+			/* generate pairing ID */
-+			mac_addr = adapter_mac_addr(padapter);
-+			peer_addr = psta->cmn.mac_addr;
-+			psta->pid = (u16)(((mac_addr[4] << 8) + mac_addr[5]) + ((peer_addr[4] << 8) + peer_addr[5]));
-+
-+			/* update peer stainfo */
-+			psta->isrc = _TRUE;
-+
-+			/* AID assignment */
-+			if (psta->cmn.aid > 0)
-+				RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), psta->cmn.aid);
-+			else {
-+				if (!rtw_aid_alloc(padapter, psta)) {
-+					RTW_INFO(FUNC_ADPT_FMT" no room for more AIDs\n", FUNC_ADPT_ARG(padapter));
-+					return _SUCCESS;
-+				}
-+				RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), psta->cmn.aid);
-+			}
-+
-+			psta->qos_option = 1;
-+			psta->cmn.bw_mode = CHANNEL_WIDTH_20;
-+			psta->ieee8021x_blocked = _FALSE;
-+#ifdef CONFIG_80211N_HT
-+			if(padapter->registrypriv.ht_enable &&
-+				is_supported_ht(padapter->registrypriv.wireless_mode)) {
-+				psta->htpriv.ht_option = _TRUE;
-+				psta->htpriv.ampdu_enable = _FALSE;
-+				psta->htpriv.sgi_20m = _FALSE;
-+				psta->htpriv.sgi_40m = _FALSE;
-+				psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+				psta->htpriv.agg_enable_bitmap = 0x0;/* reset */
-+				psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */
-+			}
-+#endif
-+
-+			rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
-+
-+			_rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats));
-+
-+			_enter_critical_bh(&psta->lock, &irqL);
-+			psta->state |= WIFI_ASOC_STATE;
-+			_exit_critical_bh(&psta->lock, &irqL);
-+
-+			report_add_sta_event(padapter, psta->cmn.mac_addr);
-+
-+		}
-+
-+		issue_probersp(padapter, get_sa(pframe), _FALSE);
-+
-+		return _SUCCESS;
-+
-+	}
-+
-+_non_rc_device:
-+
-+	return _SUCCESS;
-+
-+#endif /* CONFIG_AUTO_AP_MODE */
-+
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) &&
-+	    rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING | WIFI_UNDER_SURVEY)) {
-+		/* don't process probe req */
-+		return _SUCCESS;
-+	}
-+#endif
-+
-+	p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ielen,
-+		       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
-+
-+
-+	/* check (wildcard) SSID */
-+	if (p != NULL) {
-+		if (is_valid_p2p_probereq == _TRUE)
-+			goto _issue_probersp;
-+
-+		if ((ielen != 0 && _FALSE == _rtw_memcmp((void *)(p + 2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength))
-+			|| (ielen == 0 && pmlmeinfo->hidden_ssid_mode))
-+			goto exit;
-+
-+		#ifdef CONFIG_RTW_MESH
-+		if (MLME_IS_MESH(padapter)) {
-+			p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, WLAN_EID_MESH_ID, (int *)&ielen,
-+					len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
-+
-+			if (!p)
-+				goto exit;
-+			if (ielen != 0 && _rtw_memcmp((void *)(p + 2), (void *)cur->mesh_id.Ssid, cur->mesh_id.SsidLength) == _FALSE)
-+				goto exit;
-+		}
-+		#endif
-+
-+_issue_probersp:
-+		if (((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE &&
-+		      pmlmepriv->cur_network.join_res == _TRUE)) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) {
-+			/* RTW_INFO("+issue_probersp during ap mode\n"); */
-+			issue_probersp(padapter, get_sa(pframe), is_valid_p2p_probereq);
-+		}
-+
-+	}
-+
-+exit:
-+	return _SUCCESS;
-+
-+}
-+
-+unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	u8	*pframe = precv_frame->u.hdr.rx_data;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
-+#endif
-+
-+
-+#ifdef CONFIG_P2P
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) {
-+		if (_TRUE == pwdinfo->tx_prov_disc_info.benable) {
-+			if (_rtw_memcmp(pwdinfo->tx_prov_disc_info.peerIFAddr, get_addr2_ptr(pframe), ETH_ALEN)) {
-+				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
-+					pwdinfo->tx_prov_disc_info.benable = _FALSE;
-+					issue_p2p_provision_request(padapter,
-+						pwdinfo->tx_prov_disc_info.ssid.Ssid,
-+						pwdinfo->tx_prov_disc_info.ssid.SsidLength,
-+						pwdinfo->tx_prov_disc_info.peerDevAddr);
-+				} else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+					pwdinfo->tx_prov_disc_info.benable = _FALSE;
-+					issue_p2p_provision_request(padapter,
-+								    NULL,
-+								    0,
-+						pwdinfo->tx_prov_disc_info.peerDevAddr);
-+				}
-+			}
-+		}
-+		return _SUCCESS;
-+	} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) {
-+		if (_TRUE == pwdinfo->nego_req_info.benable) {
-+			RTW_INFO("[%s] P2P State is GONEGO ING!\n", __FUNCTION__);
-+			if (_rtw_memcmp(pwdinfo->nego_req_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN)) {
-+				pwdinfo->nego_req_info.benable = _FALSE;
-+				issue_p2p_GO_request(padapter, pwdinfo->nego_req_info.peerDevAddr);
-+			}
-+		}
-+	} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ)) {
-+		if (_TRUE == pwdinfo->invitereq_info.benable) {
-+			RTW_INFO("[%s] P2P_STATE_TX_INVITE_REQ!\n", __FUNCTION__);
-+			if (_rtw_memcmp(pwdinfo->invitereq_info.peer_macaddr, get_addr2_ptr(pframe), ETH_ALEN)) {
-+				pwdinfo->invitereq_info.benable = _FALSE;
-+				issue_p2p_invitation_request(padapter, pwdinfo->invitereq_info.peer_macaddr);
-+			}
-+		}
-+	}
-+#endif
-+
-+
-+	if ((mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS))
-+		|| (MLME_IS_MESH(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE))
-+		#ifdef CONFIG_RTW_REPEATER_SON
-+		|| (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS)
-+		#endif
-+	) {
-+		struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+		if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)
-+			&& (pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
-+		) {
-+			if (!rtw_check_bcn_info(padapter, pframe, precv_frame->u.hdr.len)) {
-+				RTW_PRINT(FUNC_ADPT_FMT" ap has changed, disconnect now\n", FUNC_ADPT_ARG(padapter));
-+				receive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0, _FALSE);
-+			}
-+		}
-+
-+		rtw_mi_report_survey_event(padapter, precv_frame);
-+		return _SUCCESS;
-+	}
-+
-+#if 0 /* move to validate_recv_mgnt_frame */
-+	if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) {
-+		if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {
-+			psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
-+			if (psta != NULL)
-+				psta->sta_stats.rx_mgnt_pkts++;
-+		}
-+	}
-+#endif
-+
-+	return _SUCCESS;
-+
-+}
-+
-+/* for 11n Logo 4.2.31/4.2.32 */
-+#ifdef CONFIG_AP_MODE
-+static void rtw_check_legacy_ap(_adapter *padapter, u8 *pframe, u32 len)
-+{
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+	if (!padapter->registrypriv.wifi_spec)
-+		return;
-+
-+	if(!MLME_IS_AP(padapter))
-+		return;
-+
-+	if (pmlmeext->bstart_bss == _TRUE) {
-+		int left;
-+		unsigned char *pos;
-+		struct rtw_ieee802_11_elems elems;
-+#ifdef CONFIG_80211N_HT
-+		u16 cur_op_mode; 
-+#endif
-+		/* checking IEs */
-+		left = len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_;
-+		pos = pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_;
-+		if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) {
-+			RTW_INFO("%s: parse fail for "MAC_FMT"\n", __func__, MAC_ARG(GetAddr3Ptr(pframe)));
-+			return;
-+		}
-+#ifdef CONFIG_80211N_HT
-+		cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK;
-+#endif
-+		/* for legacy ap */
-+		if (elems.ht_capabilities == NULL && elems.ht_capabilities_len == 0) {
-+
-+			if (0)
-+				RTW_INFO("%s: "MAC_FMT" is legacy ap\n", __func__, MAC_ARG(GetAddr3Ptr(pframe)));
-+
-+			ATOMIC_SET(&pmlmepriv->olbc, _TRUE);
-+			ATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE);
-+		}
-+	}
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	struct sta_info	*psta;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct sta_priv	*pstapriv = &padapter->stapriv;
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	uint len = precv_frame->u.hdr.len;
-+	WLAN_BSSID_EX *pbss;
-+	int ret = _SUCCESS;
-+#ifdef CONFIG_TDLS
-+	struct sta_info *ptdls_sta;
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+#ifdef CONFIG_TDLS_CH_SW
-+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
-+#endif
-+#endif /* CONFIG_TDLS */
-+
-+	if (validate_beacon_len(pframe, len) == _FALSE)
-+		return _SUCCESS;
-+
-+	if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)
-+		|| (MLME_IS_MESH(padapter) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
-+	) {
-+		if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)
-+			&& (pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
-+		) {
-+			if (!rtw_check_bcn_info(padapter, pframe, len)) {
-+				RTW_PRINT(FUNC_ADPT_FMT" ap has changed, disconnect now\n", FUNC_ADPT_ARG(padapter));
-+				receive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0, _FALSE);
-+			}
-+		}
-+
-+		rtw_mi_report_survey_event(padapter, precv_frame);
-+		return _SUCCESS;
-+	}
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS)
-+		rtw_mi_report_survey_event(padapter, precv_frame);
-+#endif
-+
-+#ifdef CONFIG_AP_MODE
-+	rtw_check_legacy_ap(padapter, pframe, len);
-+#endif
-+
-+	if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) {
-+		if ((pmlmeinfo->state & WIFI_FW_AUTH_NULL)
-+			&& (rtw_sta_linking_test_wait_done() || pmlmeext->join_abort)
-+		) {
-+			if (rtw_sta_linking_test_force_fail() || pmlmeext->join_abort) {
-+				set_link_timer(pmlmeext, 1);
-+				return _SUCCESS;
-+			}
-+
-+			/* we should update current network before auth, or some IE is wrong */
-+			pbss = (WLAN_BSSID_EX *)rtw_malloc(sizeof(WLAN_BSSID_EX));
-+			if (pbss) {
-+				if (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) {
-+					struct beacon_keys recv_beacon;
-+
-+					update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE);
-+
-+					/* update bcn keys */
-+					if (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) {
-+						RTW_INFO("%s: beacon keys ready\n", __func__);
-+						_rtw_memcpy(&pmlmepriv->cur_beacon_keys,
-+							&recv_beacon, sizeof(recv_beacon));
-+						if (is_hidden_ssid(recv_beacon.ssid, recv_beacon.ssid_len)) {
-+							_rtw_memcpy(pmlmepriv->cur_beacon_keys.ssid, pmlmeinfo->network.Ssid.Ssid, IW_ESSID_MAX_SIZE);
-+							pmlmepriv->cur_beacon_keys.ssid_len = pmlmeinfo->network.Ssid.SsidLength;
-+						}
-+					} else {
-+						RTW_ERR("%s: get beacon keys failed\n", __func__);
-+						_rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon));
-+					}
-+					#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
-+					pmlmepriv->new_beacon_cnts = 0;
-+					#endif
-+				}
-+				rtw_mfree((u8 *)pbss, sizeof(WLAN_BSSID_EX));
-+			}
-+
-+			/* check the vendor of the assoc AP */
-+			pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pframe + sizeof(struct rtw_ieee80211_hdr_3addr), len - sizeof(struct rtw_ieee80211_hdr_3addr));
-+
-+			/* update TSF Value */
-+			update_TSF(pmlmeext, pframe, len);
-+			pmlmeext->bcn_cnt = 0;
-+			pmlmeext->last_bcn_cnt = 0;
-+
-+#ifdef CONFIG_P2P_PS
-+			/* Comment by YiWei , in wifi p2p spec the "3.3 P2P Power Management" , "These mechanisms are available in a P2P Group in which only P2P Devices are associated." */
-+			/* process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); */
-+#endif /* CONFIG_P2P_PS */
-+
-+#if defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)
-+			if (padapter->registrypriv.wifi_spec) {
-+				if (process_p2p_cross_connect_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)) == _FALSE) {
-+					if (rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) {
-+						RTW_PRINT("no issue auth, P2P cross-connect does not permit\n ");
-+						return _SUCCESS;
-+					}
-+				}
-+			}
-+#endif /* CONFIG_P2P CONFIG_P2P and CONFIG_CONCURRENT_MODE */
-+
-+			/* start auth */
-+			start_clnt_auth(padapter);
-+
-+			return _SUCCESS;
-+		}
-+
-+		if (((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {
-+			psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
-+			if (psta != NULL) {
-+#ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL
-+				/* Merge from 8712 FW code */
-+				if (cmp_pkt_chnl_diff(padapter, pframe, len) != 0) {
-+					/* join wrong channel, deauth and reconnect           */
-+					issue_deauth(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_DEAUTH_LEAVING);
-+
-+					report_del_sta_event(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_JOIN_WRONG_CHANNEL, _TRUE, _FALSE);
-+					pmlmeinfo->state &= (~WIFI_FW_ASSOC_SUCCESS);
-+					return _SUCCESS;
-+				}
-+#endif /* CONFIG_PATCH_JOIN_WRONG_CHANNEL */
-+#ifdef CONFIG_RTW_80211R
-+				rtw_ft_update_bcn(padapter, precv_frame);
-+#endif
-+				ret = rtw_check_bcn_info(padapter, pframe, len);
-+				if (!ret) {
-+					RTW_PRINT(FUNC_ADPT_FMT" ap has changed, disconnect now\n", FUNC_ADPT_ARG(padapter));
-+					receive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0, _FALSE);
-+					return _SUCCESS;
-+				}
-+				/* update WMM, ERP in the beacon */
-+				/* todo: the timer is used instead of the number of the beacon received */
-+				if ((sta_rx_pkts(psta) & 0xf) == 0) {
-+					/* RTW_INFO("update_bcn_info\n"); */
-+					update_beacon_info(padapter, pframe, len, psta);
-+				}
-+
-+				pmlmepriv->cur_network_scanned->network.Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power;
-+				pmlmeext->bcn_cnt++;
-+#ifdef CONFIG_BCN_RECV_TIME
-+				rtw_rx_bcn_time_update(padapter, len, precv_frame->u.hdr.attrib.data_rate);
-+#endif
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_TDLS_CH_SW
-+				if (rtw_tdls_is_chsw_allowed(padapter) == _TRUE) {
-+					/* Send TDLS Channel Switch Request when receiving Beacon */
-+					if ((padapter->tdlsinfo.chsw_info.ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) && (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE)
-+					    && (pmlmeext->cur_channel == rtw_get_oper_ch(padapter))) {
-+						ptdls_sta = rtw_get_stainfo(&padapter->stapriv, padapter->tdlsinfo.chsw_info.addr);
-+						if (ptdls_sta != NULL) {
-+							if (ptdls_sta->tdls_sta_state | TDLS_LINKED_STATE)
-+								_set_timer(&ptdls_sta->stay_on_base_chnl_timer, TDLS_CH_SW_STAY_ON_BASE_CHNL_TIMEOUT);
-+						}
-+					}
-+				}
-+#endif
-+#endif /* CONFIG_TDLS */
-+
-+				#if CONFIG_DFS
-+				process_csa_ie(padapter
-+					, pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_
-+					, len - (WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_));
-+				#endif
-+
-+#ifdef CONFIG_P2P_PS
-+				process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN));
-+#endif /* CONFIG_P2P_PS */
-+
-+				if (pmlmeext->tsf_update_required && pmlmeext->en_hw_update_tsf)
-+					rtw_enable_hw_update_tsf_cmd(padapter);
-+
-+#if 0 /* move to validate_recv_mgnt_frame */
-+				psta->sta_stats.rx_mgnt_pkts++;
-+#endif
-+			}
-+
-+		} else if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
-+			u8 rate_set[16];
-+			u8 rate_num = 0;
-+
-+			psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
-+			if (psta != NULL) {
-+				/*
-+				* update WMM, ERP in the beacon
-+				* todo: the timer is used instead of the number of the beacon received
-+				*/
-+				if ((sta_rx_pkts(psta) & 0xf) == 0)
-+					update_beacon_info(padapter, pframe, len, psta);
-+
-+				if (pmlmeext->tsf_update_required && pmlmeext->en_hw_update_tsf)
-+					rtw_enable_hw_update_tsf_cmd(padapter);
-+			} else {
-+				rtw_ies_get_supported_rate(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, len - WLAN_HDR_A3_LEN - _BEACON_IE_OFFSET_, rate_set, &rate_num);
-+				if (rate_num == 0) {
-+					RTW_INFO(FUNC_ADPT_FMT" RX beacon with no supported rate\n", FUNC_ADPT_ARG(padapter));
-+					goto _END_ONBEACON_;
-+				}
-+
-+				psta = rtw_alloc_stainfo(pstapriv, get_addr2_ptr(pframe));
-+				if (psta == NULL) {
-+					RTW_INFO(FUNC_ADPT_FMT" Exceed the upper limit of supported clients\n", FUNC_ADPT_ARG(padapter));
-+					goto _END_ONBEACON_;
-+				}
-+
-+				psta->expire_to = pstapriv->adhoc_expire_to;
-+
-+				_rtw_memcpy(psta->bssrateset, rate_set, rate_num);
-+				psta->bssratelen = rate_num;
-+
-+				/* update TSF Value */
-+				update_TSF(pmlmeext, pframe, len);
-+
-+				/* report sta add event */
-+				report_add_sta_event(padapter, get_addr2_ptr(pframe));
-+			}
-+		}
-+	}
-+
-+_END_ONBEACON_:
-+
-+	return _SUCCESS;
-+
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+static u32 rtw_get_sta_num_by_state(_adapter *padapter, u32 state)
-+{
-+	_irqL irqL;
-+	_list	*plist, *phead;
-+	u32	index, sta_num = 0;
-+	struct sta_info *psta = NULL;
-+	struct sta_priv *pstapriv = &(padapter->stapriv);
-+
-+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);	
-+	for (index = 0; index < NUM_STA; index++) {		
-+		phead = &(pstapriv->sta_hash[index]);
-+		plist = get_next(phead);
-+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+			psta = LIST_CONTAINOR(plist, struct sta_info , hash_list);
-+			if ((psta->state & (state)))
-+				sta_num++;
-+			plist = get_next(plist);
-+		}
-+	}
-+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+	/* RTW_INFO("%s : waiting for %u sta under linking \n", __func__, sta_num); */
-+	return sta_num;
-+}
-+
-+static u8  rtw_defs_attack_chk(_adapter *padapter)
-+{
-+	struct mlme_priv *mlme = &(padapter->mlmepriv);
-+	u8 is_reject = _FALSE;
-+	u32 sta_limit = 0;
-+	u32 stime = rtw_systime_to_ms(rtw_get_current_time());
-+	static u32 ptime = 0;
-+
-+	/* RTW_INFO("%s : ptime=%u, stime=%u, diff=%u\n", __func__, ptime, stime, (stime - ptime)); */
-+	if ((ptime > 0) && ((stime - ptime) < mlme->defs_lmt_time)) {
-+		sta_limit = rtw_get_sta_num_by_state(padapter, WIFI_FW_LINKING_STATE);
-+		if (sta_limit >= mlme->defs_lmt_sta)
-+			is_reject = _TRUE;
-+	}
-+
-+	ptime = stime;
-+	/* RTW_INFO("%s : current linking num=%u\n", __func__, sta_limit); */
-+	return is_reject;	
-+}
-+#endif
-+
-+unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+#ifdef CONFIG_AP_MODE
-+	_irqL irqL;
-+	unsigned int	auth_mode, seq, ie_len;
-+	unsigned char	*sa, *p;
-+	u16	algorithm;
-+	int	status;
-+	static struct sta_info stat;
-+	struct	sta_info	*pstat = NULL;
-+	struct	sta_priv *pstapriv = &padapter->stapriv;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	uint len = precv_frame->u.hdr.len;
-+	u8	offset = 0;
-+
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) &&
-+	    rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING | WIFI_UNDER_SURVEY)) {
-+		/* don't process auth request; */
-+		return _SUCCESS;
-+	}
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
-+		return _FAIL;
-+
-+	if (!MLME_IS_ASOC(padapter))
-+		return _SUCCESS;
-+
-+#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_RTW_MESH)
-+	if (MLME_IS_MESH(padapter))
-+		return rtw_mesh_on_auth(padapter, precv_frame);
-+#endif
-+
-+	RTW_INFO("+OnAuth\n");
-+
-+	sa = get_addr2_ptr(pframe);
-+
-+	auth_mode = psecuritypriv->dot11AuthAlgrthm;
-+
-+	if (GetPrivacy(pframe)) {
-+		u8	*iv;
-+		struct rx_pkt_attrib	*prxattrib = &(precv_frame->u.hdr.attrib);
-+
-+		prxattrib->hdrlen = WLAN_HDR_A3_LEN;
-+		prxattrib->encrypt = _WEP40_;
-+
-+		iv = pframe + prxattrib->hdrlen;
-+		prxattrib->key_index = ((iv[3] >> 6) & 0x3);
-+
-+		prxattrib->iv_len = 4;
-+		prxattrib->icv_len = 4;
-+
-+		rtw_wep_decrypt(padapter, (u8 *)precv_frame);
-+
-+		offset = 4;
-+	}
-+
-+	algorithm = le16_to_cpu(*(u16 *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset));
-+	seq	= le16_to_cpu(*(u16 *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2));
-+
-+	RTW_INFO("auth alg=%x, seq=%X\n", algorithm, seq);
-+
-+	if (rtw_check_invalid_mac_address(sa, _FALSE)){
-+		RTW_INFO("%s : reject invalid AUTH-req "MAC_FMT"\n", 
-+			__func__, MAC_ARG(get_addr2_ptr(pframe)));
-+		return _FAIL;
-+	}
-+
-+	if(rtw_defs_attack_chk(padapter))  {
-+		struct sta_info *_psta;
-+		_psta = rtw_get_stainfo(pstapriv, sa);
-+		if ((_psta == NULL) || !(_psta->state & WIFI_FW_ASSOC_SUCCESS)) {
-+			status = _STATS_REFUSED_TEMPORARILY_;
-+			RTW_ERR("%s : refused temporarily for sa "MAC_FMT" !\n", __func__, MAC_ARG(sa));
-+			goto auth_fail;
-+		}
-+	}
-+
-+	if (rtw_ap_linking_test_force_auth_fail()) {
-+		status = rtw_ap_linking_test_force_auth_fail();
-+		RTW_INFO(FUNC_ADPT_FMT" force auth fail with status:%u\n"
-+			, FUNC_ADPT_ARG(padapter), status);
-+		goto auth_fail;
-+	}
-+
-+	if ((auth_mode == 2) && (algorithm != WLAN_AUTH_SAE) &&
-+	    (psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) &&
-+	    (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_))
-+		auth_mode = 0;
-+
-+	if ((algorithm > 0 && auth_mode == 0) ||	/* rx a shared-key auth but shared not enabled */
-+	    (algorithm == 0 && auth_mode == 1)) {	/* rx a open-system auth but shared-key is enabled */
-+		RTW_INFO("auth rejected due to bad alg [alg=%d, auth_mib=%d] %02X%02X%02X%02X%02X%02X\n",
-+			algorithm, auth_mode, sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]);
-+
-+		status = _STATS_NO_SUPP_ALG_;
-+
-+		goto auth_fail;
-+	}
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+	if (rtw_access_ctrl(padapter, sa) == _FALSE) {
-+		status = _STATS_UNABLE_HANDLE_STA_;
-+		goto auth_fail;
-+	}
-+#endif
-+
-+	pstat = rtw_get_stainfo(pstapriv, sa);
-+	if (pstat == NULL) {
-+
-+		/* allocate a new one */
-+		RTW_INFO("going to alloc stainfo for sa="MAC_FMT"\n",  MAC_ARG(sa));
-+		pstat = rtw_alloc_stainfo(pstapriv, sa);
-+		if (pstat == NULL) {
-+			RTW_INFO(" Exceed the upper limit of supported clients...\n");
-+			status = _STATS_UNABLE_HANDLE_STA_;
-+			goto auth_fail;
-+		}
-+
-+		pstat->state = WIFI_FW_AUTH_NULL;
-+		pstat->auth_seq = 0;
-+
-+		/* pstat->flags = 0; */
-+		/* pstat->capability = 0; */
-+	} else {
-+#ifdef CONFIG_IEEE80211W
-+		if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
-+			|| !(pstat->flags & WLAN_STA_MFP))
-+#endif /* CONFIG_IEEE80211W */
-+		{
-+
-+			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+			if (rtw_is_list_empty(&pstat->asoc_list) == _FALSE) {
-+				rtw_list_delete(&pstat->asoc_list);
-+				pstapriv->asoc_list_cnt--;
-+				#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+				if (pstat->tbtx_enable)
-+					pstapriv->tbtx_asoc_list_cnt--;
-+				#endif
-+				if (pstat->expire_to > 0)
-+					;/* TODO: STA re_auth within expire_to */
-+			}
-+			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+			if (seq == 1)
-+				; /* TODO: STA re_auth and auth timeout */
-+
-+		}
-+	}
-+
-+#ifdef CONFIG_IEEE80211W
-+	if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
-+		|| !(pstat->flags & WLAN_STA_MFP))
-+#endif /* CONFIG_IEEE80211W */
-+	{
-+		_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);
-+		if (rtw_is_list_empty(&pstat->auth_list)) {
-+
-+			rtw_list_insert_tail(&pstat->auth_list, &pstapriv->auth_list);
-+			pstapriv->auth_list_cnt++;
-+		}
-+		_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
-+	}
-+
-+	if (pstat->auth_seq == 0)
-+		pstat->expire_to = pstapriv->auth_to;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_AUTH) == _TRUE) {
-+		if ((algorithm == WLAN_AUTH_SAE) &&
-+			(auth_mode == dot11AuthAlgrthm_8021X)) {
-+			pstat->authalg = algorithm;
-+
-+			rtw_cfg80211_rx_mframe(padapter, precv_frame, NULL);
-+			return _SUCCESS;
-+		}
-+	}
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+	if ((pstat->auth_seq + 1) != seq) {
-+		RTW_INFO("(1)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n",
-+			 seq, pstat->auth_seq + 1);
-+		status = _STATS_OUT_OF_AUTH_SEQ_;
-+		goto auth_fail;
-+	}
-+
-+	if (algorithm == 0 && (auth_mode == 0 || auth_mode == 2 || auth_mode == 3)) {
-+		if (seq == 1) {
-+#ifdef CONFIG_IEEE80211W
-+			if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
-+				|| !(pstat->flags & WLAN_STA_MFP))
-+#endif /* CONFIG_IEEE80211W */
-+			{
-+				pstat->state &= ~WIFI_FW_AUTH_NULL;
-+				pstat->state |= WIFI_FW_AUTH_SUCCESS;
-+				pstat->expire_to = pstapriv->assoc_to;
-+			}
-+			pstat->authalg = algorithm;
-+		} else {
-+			RTW_INFO("(2)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n",
-+				 seq, pstat->auth_seq + 1);
-+			status = _STATS_OUT_OF_AUTH_SEQ_;
-+			goto auth_fail;
-+		}
-+	} else { /* shared system or auto authentication */
-+		if (seq == 1) {
-+			/* prepare for the challenging txt... */
-+
-+			/* get_random_bytes((void *)pstat->chg_txt, 128); */ /* TODO: */
-+			_rtw_memset((void *)pstat->chg_txt, 78, 128);
-+#ifdef CONFIG_IEEE80211W
-+			if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
-+				|| !(pstat->flags & WLAN_STA_MFP))
-+#endif /* CONFIG_IEEE80211W */
-+			{
-+				pstat->state &= ~WIFI_FW_AUTH_NULL;
-+				pstat->state |= WIFI_FW_AUTH_STATE;
-+			}
-+			pstat->authalg = algorithm;
-+			pstat->auth_seq = 2;
-+		} else if (seq == 3) {
-+			/* checking for challenging txt... */
-+			RTW_INFO("checking for challenging txt...\n");
-+
-+			p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + 4 + _AUTH_IE_OFFSET_ , _CHLGETXT_IE_, (int *)&ie_len,
-+				len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_ - 4);
-+
-+			if ((p == NULL) || (ie_len <= 0)) {
-+				RTW_INFO("auth rejected because challenge failure!(1)\n");
-+				status = _STATS_CHALLENGE_FAIL_;
-+				goto auth_fail;
-+			}
-+
-+			if (_rtw_memcmp((void *)(p + 2), pstat->chg_txt, 128)) {
-+#ifdef CONFIG_IEEE80211W
-+				if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
-+					|| !(pstat->flags & WLAN_STA_MFP))
-+#endif /* CONFIG_IEEE80211W */
-+				{
-+					pstat->state &= (~WIFI_FW_AUTH_STATE);
-+					pstat->state |= WIFI_FW_AUTH_SUCCESS;
-+					/* challenging txt is correct... */
-+					pstat->expire_to =  pstapriv->assoc_to;
-+				}
-+			} else {
-+				RTW_INFO("auth rejected because challenge failure!\n");
-+				status = _STATS_CHALLENGE_FAIL_;
-+				goto auth_fail;
-+			}
-+		} else {
-+			RTW_INFO("(3)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n",
-+				 seq, pstat->auth_seq + 1);
-+			status = _STATS_OUT_OF_AUTH_SEQ_;
-+			goto auth_fail;
-+		}
-+	}
-+
-+
-+	/* Now, we are going to issue_auth... */
-+	pstat->auth_seq = seq + 1;
-+
-+#ifdef CONFIG_NATIVEAP_MLME
-+	issue_auth(padapter, pstat, (unsigned short)(_STATS_SUCCESSFUL_));
-+#endif
-+
-+	if ((pstat->state & WIFI_FW_AUTH_SUCCESS) || (pstat->state & WIFI_FW_ASSOC_SUCCESS))
-+		pstat->auth_seq = 0;
-+
-+
-+	return _SUCCESS;
-+
-+auth_fail:
-+
-+	if (pstat)
-+		rtw_free_stainfo(padapter , pstat);
-+
-+	pstat = &stat;
-+	_rtw_memset((char *)pstat, '\0', sizeof(stat));
-+	pstat->auth_seq = 2;
-+	_rtw_memcpy(pstat->cmn.mac_addr, sa, ETH_ALEN);
-+
-+#ifdef CONFIG_NATIVEAP_MLME
-+	issue_auth(padapter, pstat, (unsigned short)status);
-+#endif
-+
-+#endif /* CONFIG_AP_MODE */
-+	return _FAIL;
-+
-+}
-+
-+unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	unsigned int	seq, len, status, algthm, offset;
-+	unsigned char	*p;
-+	unsigned int	go2asoc = 0;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	uint pkt_len = precv_frame->u.hdr.len;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_AUTH) == _TRUE) {
-+		if (rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE)) {
-+			if (rtw_cached_pmkid(padapter, get_my_bssid(&pmlmeinfo->network)) != -1) {
-+				RTW_INFO("SAE: PMKSA cache entry found\n");
-+				goto normal;
-+			}
-+			rtw_cfg80211_rx_mframe(padapter, precv_frame, NULL);
-+			return _SUCCESS;
-+		}
-+	}
-+
-+normal:
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+	/* check A1 matches or not */
-+	if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN))
-+		return _SUCCESS;
-+
-+	if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE) || pmlmeext->join_abort)
-+		return _SUCCESS;
-+
-+	offset = (GetPrivacy(pframe)) ? 4 : 0;
-+
-+	algthm	= le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset));
-+	seq	= le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2));
-+	status	= le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 4));
-+
-+	if (status != 0) {
-+		RTW_INFO("clnt auth fail, status: %d\n", status);
-+		if (status == 13) { /* && pmlmeinfo->auth_algo == dot11AuthAlgrthm_Auto) */
-+			if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)
-+				pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open;
-+			else
-+				pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared;
-+			/* pmlmeinfo->reauth_count = 0; */
-+		}
-+
-+		pmlmeinfo->auth_status = status;
-+		set_link_timer(pmlmeext, 1);
-+		goto authclnt_fail;
-+	}
-+
-+	if (seq == 2) {
-+		if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) {
-+			/* legendary shared system */
-+			p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _AUTH_IE_OFFSET_, _CHLGETXT_IE_, (int *)&len,
-+				pkt_len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_);
-+
-+			if (p == NULL) {
-+				/* RTW_INFO("marc: no challenge text?\n"); */
-+				goto authclnt_fail;
-+			}
-+
-+			_rtw_memcpy((void *)(pmlmeinfo->chg_txt), (void *)(p + 2), len);
-+			pmlmeinfo->auth_seq = 3;
-+			issue_auth(padapter, NULL, 0);
-+			set_link_timer(pmlmeext, REAUTH_TO);
-+
-+			return _SUCCESS;
-+		} else {
-+			/* open, or 802.11r FTAA system */
-+			go2asoc = 1;
-+		}
-+	} else if (seq == 4) {
-+		if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)
-+			go2asoc = 1;
-+		else
-+			goto authclnt_fail;
-+	} else {
-+		/* this is also illegal */
-+		/* RTW_INFO("marc: clnt auth failed due to illegal seq=%x\n", seq); */
-+		goto authclnt_fail;
-+	}
-+
-+	if (go2asoc) {
-+#ifdef CONFIG_RTW_80211R
-+		if (rtw_ft_update_auth_rsp_ies(padapter, pframe, pkt_len))
-+			return _SUCCESS;
-+#endif
-+		RTW_PRINT("auth success, start assoc\n");
-+		start_clnt_assoc(padapter);
-+		return _SUCCESS;
-+	}
-+
-+authclnt_fail:
-+
-+	/* pmlmeinfo->state &= ~(WIFI_FW_AUTH_STATE); */
-+
-+	return _FAIL;
-+
-+}
-+
-+unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+#ifdef CONFIG_AP_MODE
-+	_irqL irqL;
-+	u16 listen_interval;
-+	struct rtw_ieee802_11_elems elems;
-+	struct sta_info	*pstat;
-+	unsigned char		reassoc, *pos;
-+	int		left;
-+	unsigned short		status = _STATS_SUCCESSFUL_;
-+	unsigned short		frame_type, ie_offset = 0;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX	*cur = &(pmlmeinfo->network);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	uint pkt_len = precv_frame->u.hdr.len;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	u8 p2p_status_code = P2P_STATUS_SUCCESS;
-+	u8 *p2pie;
-+	u32 p2pielen = 0;
-+#endif /* CONFIG_P2P */
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	u8 sta_tbtx_enable = _FALSE;
-+#endif
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) &&
-+	    rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING | WIFI_UNDER_SURVEY)) {
-+		/* don't process assoc request; */
-+		return _SUCCESS;
-+	}
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
-+		return _FAIL;
-+
-+	if (rtw_check_invalid_mac_address(get_addr2_ptr(pframe), _FALSE)) {
-+		RTW_INFO("%s : reject invalid ASSOC-req "MAC_FMT"\n", 
-+			__func__, MAC_ARG(get_addr2_ptr(pframe)));
-+		return _FAIL;
-+	}
-+
-+	frame_type = get_frame_sub_type(pframe);
-+	if (frame_type == WIFI_ASSOCREQ) {
-+		reassoc = 0;
-+		ie_offset = _ASOCREQ_IE_OFFSET_;
-+	} else { /* WIFI_REASSOCREQ */
-+		reassoc = 1;
-+		ie_offset = _REASOCREQ_IE_OFFSET_;
-+	}
-+
-+
-+	if (pkt_len < IEEE80211_3ADDR_LEN + ie_offset) {
-+		RTW_INFO("handle_assoc(reassoc=%d) - too short payload (len=%lu)"
-+			 "\n", reassoc, (unsigned long)pkt_len);
-+		return _FAIL;
-+	}
-+
-+	pstat = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
-+	if (pstat == (struct sta_info *)NULL) {
-+		status = _RSON_CLS2_;
-+		goto asoc_class2_error;
-+	}
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	if (pstat->authalg == WLAN_AUTH_SAE) {
-+		/* WPA3-SAE */
-+		if (((pstat->state) & WIFI_FW_AUTH_NULL)) {
-+			/* TODO:
-+			   Queue AssocReq and Proccess
-+			   by external auth trigger. */
-+			RTW_INFO("%s: wait external auth trigger\n", __func__);
-+			return _SUCCESS;
-+		}
-+	}
-+
-+	/* check if this stat has been successfully authenticated/assocated */
-+	if (!((pstat->state) & WIFI_FW_AUTH_SUCCESS)) {
-+		if (!((pstat->state) & WIFI_FW_ASSOC_SUCCESS)) {
-+			status = _RSON_CLS2_;
-+			goto asoc_class2_error;
-+		} else {
-+			pstat->state &= (~WIFI_FW_ASSOC_SUCCESS);
-+			pstat->state |= WIFI_FW_ASSOC_STATE;
-+		}
-+	} else {
-+		pstat->state &= (~WIFI_FW_AUTH_SUCCESS);
-+		pstat->state |= WIFI_FW_ASSOC_STATE;
-+	}
-+
-+#if 0/* todo:tkip_countermeasures */
-+	if (hapd->tkip_countermeasures) {
-+		resp = WLAN_REASON_MICHAEL_MIC_FAILURE;
-+		goto fail;
-+	}
-+#endif
-+
-+	if (rtw_ap_linking_test_force_asoc_fail()) {
-+		status = rtw_ap_linking_test_force_asoc_fail();
-+		RTW_INFO(FUNC_ADPT_FMT" force asoc fail with status:%u\n"
-+			, FUNC_ADPT_ARG(padapter), status);
-+		goto OnAssocReqFail;
-+	}
-+
-+	/* now parse all ieee802_11 ie to point to elems */
-+	left = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset);
-+	pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset);
-+	if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) {
-+		RTW_INFO("STA " MAC_FMT " sent invalid association request\n",
-+			 MAC_ARG(pstat->cmn.mac_addr));
-+		status = _STATS_FAILURE_;
-+		goto OnAssocReqFail;
-+	}
-+
-+	rtw_ap_parse_sta_capability(padapter, pstat, pframe + WLAN_HDR_A3_LEN);
-+
-+	listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN + 2);
-+#if 0/* todo: */
-+	/* check listen_interval */
-+	if (listen_interval > hapd->conf->max_listen_interval) {
-+		hostapd_logger(hapd, mgmt->sa, HOSTAPD_MODULE_IEEE80211,
-+			       HOSTAPD_LEVEL_DEBUG,
-+			       "Too large Listen Interval (%d)",
-+			       listen_interval);
-+		resp = WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE;
-+		goto fail;
-+	}
-+
-+	pstat->listen_interval = listen_interval;
-+#endif
-+
-+	/* now we should check all the fields... */
-+	/* checking SSID */
-+	if (elems.ssid == NULL
-+		|| elems.ssid_len == 0
-+		|| elems.ssid_len != cur->Ssid.SsidLength
-+		|| _rtw_memcmp(elems.ssid, cur->Ssid.Ssid, cur->Ssid.SsidLength) == _FALSE
-+	) {
-+		status = _STATS_FAILURE_;
-+		goto OnAssocReqFail;
-+	}
-+
-+	/* (Extended) Supported rates */
-+	status = rtw_ap_parse_sta_supported_rates(padapter, pstat
-+		, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
-+	if (status != _STATS_SUCCESSFUL_)
-+		goto OnAssocReqFail;
-+
-+	/* check RSN/WPA/WPS */
-+	status = rtw_ap_parse_sta_security_ie(padapter, pstat, &elems);
-+	if (status != _STATS_SUCCESSFUL_)
-+		goto OnAssocReqFail;
-+
-+	/* check if there is WMM IE & support WWM-PS */
-+	rtw_ap_parse_sta_wmm_ie(padapter, pstat
-+		, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
-+
-+#ifdef CONFIG_RTS_FULL_BW
-+	/*check vendor IE*/
-+	rtw_parse_sta_vendor_ie_8812(padapter, pstat
-+		, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
-+#endif/*CONFIG_RTS_FULL_BW*/
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	if (elems.tbtx_cap && elems.tbtx_cap_len != 0) {
-+		if(rtw_is_tbtx_capabilty(elems.tbtx_cap, elems.tbtx_cap_len)) {
-+			sta_tbtx_enable = _TRUE;
-+		}
-+	}
-+
-+#endif
-+
-+	rtw_ap_parse_sta_ht_ie(padapter, pstat, &elems);
-+	rtw_ap_parse_sta_vht_ie(padapter, pstat, &elems);
-+
-+	if (((pstat->flags & WLAN_STA_HT) || (pstat->flags & WLAN_STA_VHT)) &&
-+	    ((pstat->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) ||
-+	     (pstat->wpa_pairwise_cipher & WPA_CIPHER_TKIP))) {
-+
-+		RTW_INFO("(V)HT: " MAC_FMT " tried to use TKIP with (V)HT association\n", MAC_ARG(pstat->cmn.mac_addr));
-+
-+		pstat->flags &= ~WLAN_STA_HT;
-+		pstat->flags &= ~WLAN_STA_VHT;
-+		/*status = WLAN_STATUS_CIPHER_REJECTED_PER_POLICY;
-+		  * goto OnAssocReqFail;
-+		*/
-+	}
-+
-+#ifdef CONFIG_P2P
-+	pstat->is_p2p_device = _FALSE;
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+		p2pie = rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + ie_offset , pkt_len - WLAN_HDR_A3_LEN - ie_offset , NULL, &p2pielen);
-+		if (p2pie) {
-+			pstat->is_p2p_device = _TRUE;
-+			p2p_status_code = (u8)process_assoc_req_p2p_ie(pwdinfo, pframe, pkt_len, pstat);
-+			if (p2p_status_code > 0) {
-+				pstat->p2p_status_code = p2p_status_code;
-+				status = _STATS_CAP_FAIL_;
-+				goto OnAssocReqFail;
-+			}
-+		}
-+#ifdef CONFIG_WFD
-+		rtw_process_wfd_ies(padapter, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset, __func__);
-+#endif
-+	}
-+	pstat->p2p_status_code = p2p_status_code;
-+#endif /* CONFIG_P2P */
-+
-+	rtw_ap_parse_sta_multi_ap_ie(padapter, pstat, pos, left);
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	if (rtw_rson_ap_check_sta(padapter, pframe, pkt_len, ie_offset))
-+		goto OnAssocReqFail;
-+#endif
-+
-+	/* TODO: identify_proprietary_vendor_ie(); */
-+	/* Realtek proprietary IE */
-+	/* identify if this is Broadcom sta */
-+	/* identify if this is ralink sta */
-+	/* Customer proprietary IE */
-+
-+#ifdef CONFIG_RTW_80211K
-+	rtw_ap_parse_sta_rm_en_cap(padapter, pstat, &elems);
-+#endif
-+
-+	/* AID assignment */
-+	if (pstat->cmn.aid > 0)
-+		RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->cmn.aid);
-+	else {
-+		if (!rtw_aid_alloc(padapter, pstat)) {
-+			RTW_INFO(FUNC_ADPT_FMT" no room for more AIDs\n", FUNC_ADPT_ARG(padapter));
-+			status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA;
-+			goto OnAssocReqFail;
-+		}
-+		RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->cmn.aid);
-+	}
-+
-+	pstat->state &= (~WIFI_FW_ASSOC_STATE);
-+	pstat->state |= WIFI_FW_ASSOC_SUCCESS;
-+	/* RTW_INFO("==================%s, %d,  (%x), bpairwise_key_installed=%d, MAC:"MAC_FMT"\n"
-+	, __func__, __LINE__, pstat->state, pstat->bpairwise_key_installed, MAC_ARG(pstat->cmn.mac_addr)); */
-+#ifdef CONFIG_IEEE80211W
-+	if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
-+		|| !(pstat->flags & WLAN_STA_MFP))
-+#endif /* CONFIG_IEEE80211W */
-+	{
-+		_enter_critical_bh(&pstapriv->auth_list_lock, &irqL);
-+		if (!rtw_is_list_empty(&pstat->auth_list)) {
-+			rtw_list_delete(&pstat->auth_list);
-+			pstapriv->auth_list_cnt--;
-+		}
-+		_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
-+
-+		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+		if (rtw_is_list_empty(&pstat->asoc_list)) {
-+			pstat->expire_to = pstapriv->expire_to;
-+			rtw_list_insert_tail(&pstat->asoc_list, &pstapriv->asoc_list);
-+			pstapriv->asoc_list_cnt++;
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+			if (sta_tbtx_enable) {
-+				pstat->tbtx_enable = _TRUE;
-+				pstapriv->tbtx_asoc_list_cnt++;
-+			}
-+#endif
-+		}
-+		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+	}
-+
-+	/* now the station is qualified to join our BSS...	 */
-+	if (pstat && (pstat->state & WIFI_FW_ASSOC_SUCCESS) && (_STATS_SUCCESSFUL_ == status)) {
-+#ifdef CONFIG_NATIVEAP_MLME
-+#ifdef CONFIG_IEEE80211W
-+		if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
-+			|| !(pstat->flags & WLAN_STA_MFP))
-+#endif /* CONFIG_IEEE80211W */
-+		{
-+			/* .1 bss_cap_update & sta_info_update */
-+			bss_cap_update_on_sta_join(padapter, pstat);
-+			sta_info_update(padapter, pstat);
-+		}
-+#ifdef CONFIG_IEEE80211W
-+		if (pstat->bpairwise_key_installed == _TRUE && (pstat->flags & WLAN_STA_MFP))
-+			status = _STATS_REFUSED_TEMPORARILY_;
-+#endif /* CONFIG_IEEE80211W */
-+		/* .2 issue assoc rsp before notify station join event. */
-+		if (frame_type == WIFI_ASSOCREQ)
-+			issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP);
-+		else
-+			issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP);
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+		_enter_critical_bh(&pstat->lock, &irqL);
-+		if (pstat->passoc_req) {
-+			rtw_mfree(pstat->passoc_req, pstat->assoc_req_len);
-+			pstat->passoc_req = NULL;
-+			pstat->assoc_req_len = 0;
-+		}
-+
-+		pstat->passoc_req =  rtw_zmalloc(pkt_len);
-+		if (pstat->passoc_req) {
-+			_rtw_memcpy(pstat->passoc_req, pframe, pkt_len);
-+			pstat->assoc_req_len = pkt_len;
-+		}
-+		_exit_critical_bh(&pstat->lock, &irqL);
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+#ifdef CONFIG_IEEE80211W
-+		if ((pstat->bpairwise_key_installed != _TRUE && (pstat->flags & WLAN_STA_MFP)) 
-+			|| !(pstat->flags & WLAN_STA_MFP))
-+#endif /* CONFIG_IEEE80211W */
-+		{
-+			/* .3-(1) report sta add event */
-+			report_add_sta_event(padapter, pstat->cmn.mac_addr);
-+		}
-+#ifdef CONFIG_IEEE80211W
-+		if (pstat->bpairwise_key_installed == _TRUE && (pstat->flags & WLAN_STA_MFP)) {
-+			RTW_INFO(MAC_FMT"\n", MAC_ARG(pstat->cmn.mac_addr));
-+			issue_action_SA_Query(padapter, pstat->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY);
-+		}
-+#endif /* CONFIG_IEEE80211W */
-+#endif /* CONFIG_NATIVEAP_MLME */
-+	}
-+
-+	return _SUCCESS;
-+
-+asoc_class2_error:
-+
-+#ifdef CONFIG_NATIVEAP_MLME
-+	issue_deauth(padapter, (void *)get_addr2_ptr(pframe), status);
-+#endif
-+
-+	return _FAIL;
-+
-+OnAssocReqFail:
-+
-+
-+#ifdef CONFIG_NATIVEAP_MLME
-+	/* pstat->cmn.aid = 0; */
-+	if (frame_type == WIFI_ASSOCREQ)
-+		issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP);
-+	else
-+		issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP);
-+#endif
-+
-+
-+#endif /* CONFIG_AP_MODE */
-+
-+	return _FAIL;
-+
-+}
-+
-+#if defined(CONFIG_LAYER2_ROAMING) && defined(CONFIG_RTW_80211K)
-+void rtw_roam_nb_discover(_adapter *padapter, u8 bfroce)
-+{
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);	
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *psta;
-+	u8 nb_req_issue = _FALSE;
-+
-+	if (!check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
-+		return;
-+
-+	if (!rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE))
-+		return;
-+
-+	psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
-+	if (!psta)
-+		return;
-+	
-+	if (bfroce || (!pmlmepriv->nb_info.nb_rpt_is_same))
-+		nb_req_issue = _TRUE;
-+	
-+	if (nb_req_issue && (psta->rm_en_cap[0] & RTW_RRM_NB_RPT_EN)) 
-+		rm_add_nb_req(padapter, psta);
-+}
-+#endif
-+
-+unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	uint i;
-+	int res;
-+	unsigned short	status;
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	/* WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network); */
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	uint pkt_len = precv_frame->u.hdr.len;
-+#ifdef CONFIG_WAPI_SUPPORT
-+	PNDIS_802_11_VARIABLE_IEs	pWapiIE = NULL;
-+#endif
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	/* check A1 matches or not */
-+	if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN))
-+		return _SUCCESS;
-+
-+	if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)) || pmlmeext->join_abort)
-+		return _SUCCESS;
-+
-+	if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
-+		return _SUCCESS;
-+
-+	_cancel_timer_ex(&pmlmeext->link_timer);
-+
-+	/* status */
-+	status = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 2));
-+	if (status > 0) {
-+		RTW_INFO("assoc reject, status code: %d\n", status);
-+		pmlmeinfo->state = WIFI_FW_NULL_STATE;
-+		res = -4;
-+		goto report_assoc_result;
-+	}
-+
-+	/* get capabilities */
-+	pmlmeinfo->capability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
-+
-+	/* set slot time */
-+	pmlmeinfo->slotTime = (pmlmeinfo->capability & BIT(10)) ? 9 : 20;
-+
-+	/* AID */
-+	res = pmlmeinfo->aid = (int)(le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 4)) & 0x3fff);
-+	
-+	/* check aid value */
-+	if (res < 1 || res > 2007) {
-+		RTW_INFO("assoc reject, aid: %d\n", res);
-+		pmlmeinfo->state = WIFI_FW_NULL_STATE;
-+		res = -4;
-+		goto report_assoc_result;
-+	}
-+
-+	/* following are moved to join event callback function */
-+	/* to handle HT, WMM, rate adaptive, update MAC reg */
-+	/* for not to handle the synchronous IO in the tasklet */
-+	for (i = (6 + WLAN_HDR_A3_LEN); i < pkt_len;) {
-+		pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i);
-+
-+		switch (pIE->ElementID) {
-+		case _VENDOR_SPECIFIC_IE_:
-+			if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6))	/* WMM */
-+				WMM_param_handler(padapter, pIE);
-+#if defined(CONFIG_P2P) && defined(CONFIG_WFD)
-+			else if (_rtw_memcmp(pIE->data, WFD_OUI, 4))		/* WFD */
-+				rtw_process_wfd_ie(padapter, (u8 *)pIE, pIE->Length, __func__);
-+#endif
-+			break;
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+		case _WAPI_IE_:
-+			pWapiIE = pIE;
-+			break;
-+#endif
-+
-+		case _HT_CAPABILITY_IE_:	/* HT caps */
-+			HT_caps_handler(padapter, pIE);
-+#ifdef ROKU_PRIVATE
-+			HT_caps_handler_infra_ap(padapter, pIE);
-+#endif /* ROKU_PRIVATE */
-+			break;
-+
-+		case _HT_EXTRA_INFO_IE_:	/* HT info */
-+			HT_info_handler(padapter, pIE);
-+			break;
-+
-+#ifdef CONFIG_80211AC_VHT
-+		case EID_VHTCapability:
-+			VHT_caps_handler(padapter, pIE);
-+#ifdef ROKU_PRIVATE
-+			VHT_caps_handler_infra_ap(padapter, pIE);
-+#endif /* ROKU_PRIVATE */
-+			break;
-+
-+		case EID_VHTOperation:
-+			VHT_operation_handler(padapter, pIE);
-+			break;
-+#endif
-+
-+		case _ERPINFO_IE_:
-+			ERP_IE_handler(padapter, pIE);
-+			break;
-+#ifdef CONFIG_TDLS
-+		case _EXT_CAP_IE_:
-+			if (check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE)
-+				padapter->tdlsinfo.ap_prohibited = _TRUE;
-+			if (check_ap_tdls_ch_switching_prohibited(pIE->data, pIE->Length) == _TRUE)
-+				padapter->tdlsinfo.ch_switch_prohibited = _TRUE;
-+			break;
-+#endif /* CONFIG_TDLS */
-+
-+#ifdef CONFIG_RTW_80211K
-+		case _EID_RRM_EN_CAP_IE_:
-+			RM_IE_handler(padapter, pIE);
-+			break;
-+#endif
-+
-+#ifdef ROKU_PRIVATE
-+		/* Infra mode, used to store AP's info , Parse the supported rates from AssocRsp */
-+		case _SUPPORTEDRATES_IE_:
-+			Supported_rate_infra_ap(padapter, pIE);
-+			break;
-+
-+		case _EXT_SUPPORTEDRATES_IE_:
-+			Extended_Supported_rate_infra_ap(padapter, pIE);
-+			break;
-+#endif /* ROKU_PRIVATE */
-+		default:
-+			break;
-+		}
-+
-+		i += (pIE->Length + 2);
-+	}
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	rtw_wapi_on_assoc_ok(padapter, pIE);
-+#endif
-+
-+	pmlmeinfo->state &= (~WIFI_FW_ASSOC_STATE);
-+	pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
-+
-+	/* Update Basic Rate Table for spec, 2010-12-28 , by thomas */
-+	UpdateBrateTbl(padapter, pmlmeinfo->network.SupportedRates);
-+
-+report_assoc_result:
-+	if (res > 0)
-+		rtw_buf_update(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len, pframe, pkt_len);
-+	else
-+		rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len);
-+
-+	report_join_res(padapter, res, status);
-+
-+#if defined(CONFIG_LAYER2_ROAMING) && defined(CONFIG_RTW_80211K)
-+	rtw_roam_nb_discover(padapter, _TRUE);
-+#endif
-+	return _SUCCESS;
-+}
-+
-+unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	unsigned short	reason;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+#endif /* CONFIG_P2P */
-+
-+	/* check A3 */
-+	if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))
-+		return _SUCCESS;
-+
-+	RTW_INFO(FUNC_ADPT_FMT" - Start to Disconnect\n", FUNC_ADPT_ARG(padapter));
-+
-+#ifdef CONFIG_P2P
-+	if (pwdinfo->rx_invitereq_info.scan_op_ch_only) {
-+		_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
-+		_set_timer(&pwdinfo->reset_ch_sitesurvey, 10);
-+	}
-+#endif /* CONFIG_P2P */
-+
-+	reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
-+
-+#ifdef CONFIG_AP_MODE
-+	if (MLME_IS_AP(padapter)) {
-+		_irqL irqL;
-+		struct sta_info *psta;
-+		struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
-+		/* rtw_free_stainfo(padapter, psta); */
-+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
-+
-+		RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
-+			, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));
-+
-+		psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
-+		if (psta) {
-+			u8 updated = _FALSE;
-+
-+			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+			if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
-+				rtw_list_delete(&psta->asoc_list);
-+				pstapriv->asoc_list_cnt--;
-+				#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+				if (psta->tbtx_enable)
-+					pstapriv->tbtx_asoc_list_cnt--;
-+				#endif
-+				updated = ap_free_sta(padapter, psta, _FALSE, reason, _TRUE);
-+
-+			}
-+			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+			associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
-+		}
-+
-+
-+		return _SUCCESS;
-+	} else
-+#endif
-+	if (!MLME_IS_MESH(padapter)) {
-+		int	ignore_received_deauth = 0;
-+
-+		/*	Commented by Albert 20130604 */
-+		/*	Before sending the auth frame to start the STA/GC mode connection with AP/GO,  */
-+		/*	we will send the deauth first. */
-+		/*	However, the Win8.1 with BRCM Wi-Fi will send the deauth with reason code 6 to us after receieving our deauth. */
-+		/*	Added the following code to avoid this case. */
-+		if ((pmlmeinfo->state & WIFI_FW_AUTH_STATE) ||
-+		    (pmlmeinfo->state & WIFI_FW_ASSOC_STATE)) {
-+			if (reason == WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA)
-+				ignore_received_deauth = 1;
-+			else if (WLAN_REASON_PREV_AUTH_NOT_VALID == reason) {
-+				/* TODO: 802.11r */
-+				ignore_received_deauth = 1;
-+			}
-+		}
-+
-+		RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM, ignore=%d\n"
-+			, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe), ignore_received_deauth);
-+
-+		if (0 == ignore_received_deauth)
-+			receive_disconnect(padapter, get_addr2_ptr(pframe), reason, _FALSE);
-+	}
-+	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
-+	return _SUCCESS;
-+
-+}
-+
-+unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	unsigned short	reason;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+#endif /* CONFIG_P2P */
-+
-+	/* check A3 */
-+	if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))
-+		return _SUCCESS;
-+
-+	RTW_INFO(FUNC_ADPT_FMT" - Start to Disconnect\n", FUNC_ADPT_ARG(padapter));
-+
-+#ifdef CONFIG_P2P
-+	if (pwdinfo->rx_invitereq_info.scan_op_ch_only) {
-+		_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
-+		_set_timer(&pwdinfo->reset_ch_sitesurvey, 10);
-+	}
-+#endif /* CONFIG_P2P */
-+
-+	reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
-+
-+#ifdef CONFIG_AP_MODE
-+	if (MLME_IS_AP(padapter)) {
-+		_irqL irqL;
-+		struct sta_info *psta;
-+		struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);	 */
-+		/* rtw_free_stainfo(padapter, psta); */
-+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
-+
-+		RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
-+			, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));
-+
-+		psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
-+		if (psta) {
-+			u8 updated = _FALSE;
-+
-+			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+			if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
-+				rtw_list_delete(&psta->asoc_list);
-+				pstapriv->asoc_list_cnt--;
-+				#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+				if (psta->tbtx_enable)
-+					pstapriv->tbtx_asoc_list_cnt--;
-+				#endif
-+				updated = ap_free_sta(padapter, psta, _FALSE, reason, _TRUE);
-+
-+			}
-+			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+			associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
-+		}
-+
-+		return _SUCCESS;
-+	} else
-+#endif
-+	if (!MLME_IS_MESH(padapter)) {
-+		RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
-+			, FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));
-+
-+	#ifdef CONFIG_RTW_WNM
-+		if (rtw_wnm_try_btm_roam_imnt(padapter) > 0)
-+	#endif
-+		receive_disconnect(padapter, get_addr2_ptr(pframe), reason, _FALSE);
-+	}
-+	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
-+	return _SUCCESS;
-+
-+}
-+
-+unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	RTW_INFO("%s\n", __FUNCTION__);
-+	return _SUCCESS;
-+}
-+
-+unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta, u8 *ies, uint ies_len)
-+{
-+	unsigned int ret = _FAIL;
-+	struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(mlmeext->mlmext_info);
-+
-+	if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {
-+		ret = _SUCCESS;
-+		goto exit;
-+	}
-+
-+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {
-+
-+		int ch_switch_mode = -1, ch = -1, ch_switch_cnt = -1;
-+		int ch_offset = -1;
-+		u8 bwmode;
-+		struct ieee80211_info_element *ie;
-+
-+		RTW_INFO(FUNC_NDEV_FMT" from "MAC_FMT"\n",
-+			FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->cmn.mac_addr));
-+
-+		for_each_ie(ie, ies, ies_len) {
-+			if (ie->id == WLAN_EID_CHANNEL_SWITCH) {
-+				ch_switch_mode = ie->data[0];
-+				ch = ie->data[1];
-+				ch_switch_cnt = ie->data[2];
-+				RTW_INFO("ch_switch_mode:%d, ch:%d, ch_switch_cnt:%d\n",
-+					 ch_switch_mode, ch, ch_switch_cnt);
-+			} else if (ie->id == WLAN_EID_SECONDARY_CHANNEL_OFFSET) {
-+				ch_offset = secondary_ch_offset_to_hal_ch_offset(ie->data[0]);
-+				RTW_INFO("ch_offset:%d\n", ch_offset);
-+			}
-+		}
-+
-+		if (ch == -1)
-+			return _SUCCESS;
-+
-+		if (ch_offset == -1)
-+			bwmode = mlmeext->cur_bwmode;
-+		else
-+			bwmode = (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) ?
-+				 CHANNEL_WIDTH_20 : CHANNEL_WIDTH_40;
-+
-+		ch_offset = (ch_offset == -1) ? mlmeext->cur_ch_offset : ch_offset;
-+
-+		/* todo:
-+		 * 1. the decision of channel switching
-+		 * 2. things after channel switching
-+		 */
-+
-+		ret = rtw_set_chbw_cmd(padapter, ch, bwmode, ch_offset, 0);
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	unsigned int ret = _FAIL;
-+	struct sta_info *psta = NULL;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	uint frame_len = precv_frame->u.hdr.len;
-+	u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
-+	u8 category;
-+	u8 action;
-+
-+	psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
-+
-+	if (!psta)
-+		goto exit;
-+
-+	category = frame_body[0];
-+	if (category != RTW_WLAN_CATEGORY_SPECTRUM_MGMT)
-+		goto exit;
-+
-+	action = frame_body[1];
-+
-+	RTW_INFO(FUNC_ADPT_FMT" action:%u\n", FUNC_ADPT_ARG(padapter), action);
-+
-+	switch (action) {
-+	case RTW_WLAN_ACTION_SPCT_MSR_REQ:
-+	case RTW_WLAN_ACTION_SPCT_MSR_RPRT:
-+	case RTW_WLAN_ACTION_SPCT_TPC_REQ:
-+	case RTW_WLAN_ACTION_SPCT_TPC_RPRT:
-+		break;
-+	case RTW_WLAN_ACTION_SPCT_CHL_SWITCH:
-+#ifdef CONFIG_SPCT_CH_SWITCH
-+		ret = on_action_spct_ch_switch(padapter, psta
-+				, frame_body + 2, frame_len - (frame_body - pframe) - 2);
-+#elif CONFIG_DFS
-+		if (MLME_IS_STA(padapter) && MLME_IS_ASOC(padapter)) {
-+			process_csa_ie(padapter
-+				, frame_body + 2, frame_len - (frame_body - pframe) - 2);
-+		}
-+#endif
-+		break;
-+	default:
-+		break;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	return _SUCCESS;
-+}
-+
-+unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	return _SUCCESS;
-+}
-+
-+#ifdef CONFIG_RTW_WNM
-+unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe)
-+{
-+	unsigned int ret = _FAIL;
-+	struct sta_info *sta = NULL;
-+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
-+	struct sta_priv *stapriv = &(adapter->stapriv);
-+	u8 *frame = rframe->u.hdr.rx_data;
-+	u32 frame_len = rframe->u.hdr.len;
-+	u8 *frame_body = (u8 *)(frame + sizeof(struct rtw_ieee80211_hdr_3addr));
-+	u32 frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr);	
-+	u8 category, action;
-+	int cnt = 0;
-+	char msg[16];
-+
-+	sta = rtw_get_stainfo(stapriv, get_addr2_ptr(frame));
-+	if (!sta)
-+		goto exit;
-+
-+	category = frame_body[0];
-+	if (category != RTW_WLAN_CATEGORY_WNM)
-+		goto exit;
-+
-+	action = frame_body[1];
-+
-+	switch (action) {
-+#ifdef CONFIG_RTW_80211R
-+	case RTW_WLAN_ACTION_WNM_BTM_REQ:
-+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
-+			RTW_INFO("WNM: BSS Transition Management Request recv.\n");
-+			rtw_wnm_process_btm_req(adapter, frame_body, frame_body_len);
-+		}
-+		ret = _SUCCESS;
-+		break;
-+#endif
-+	case RTW_WLAN_ACTION_WNM_BTM_RSP:
-+		if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) &&
-+			(pmlmepriv->nb_info.features & RTW_WNM_FEATURE_BTM_REQ_EN)) {
-+			struct btm_rsp_hdr rsp;
-+			u32 sz;
-+
-+			RTW_INFO("WNM: BSS Transition Management Response recv.\n");
-+			sz = rtw_wnm_btm_rsp_candidates_sz_get(adapter,
-+					frame_body, frame_body_len);
-+			_rtw_memset(&rsp, 0, sizeof(rsp));
-+
-+			if (sz > 0)
-+				rsp.pcandidates = rtw_zmalloc(sz);
-+
-+			rtw_wnm_process_btm_rsp(adapter, frame_body, frame_body_len, &rsp);
-+			/* TODO : handle candidates info in rsp.pcandidates for upper-layer services */
-+			#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+			cmap_intfs_nl_btm_resp_event(adapter, sta->cmn.mac_addr,
-+						     adapter_mac_addr(adapter),
-+						     rsp.status, rsp.bssid,
-+						     rsp.pcandidates,
-+						     rsp.candidates_num);
-+			#endif
-+			if (0 && rsp.pcandidates && (rsp.candidates_num > 0))
-+				RTW_INFO_DUMP("pcandidates : ", rsp.pcandidates, sz);
-+
-+			if ((sz > 0) && (rsp.pcandidates != NULL))
-+				rtw_mfree(rsp.pcandidates, sz);
-+		}
-+		 /* fall through */
-+	default:
-+		#ifdef CONFIG_IOCTL_CFG80211
-+		cnt += sprintf((msg + cnt), "ACT_WNM %u", action);
-+		rtw_cfg80211_rx_action(adapter, rframe, msg);
-+		#endif
-+		ret = _SUCCESS;
-+		break;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_RTW_WNM */
-+
-+/**
-+ * rtw_rx_ampdu_size - Get the target RX AMPDU buffer size for the specific @adapter
-+ * @adapter: the adapter to get target RX AMPDU buffer size
-+ *
-+ * Returns: the target RX AMPDU buffer size
-+ */
-+u8 rtw_rx_ampdu_size(_adapter *adapter)
-+{
-+	u8 size;
-+	HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor;
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if (rtw_btcoex_IsBTCoexCtrlAMPDUSize(adapter) == _TRUE) {
-+		size = rtw_btcoex_GetAMPDUSize(adapter);
-+		goto exit;
-+	}
-+#endif
-+
-+	/* for scan */
-+	if (!mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_DISABLE)
-+	    && !mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_COMPLETE)
-+	    && adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_size != RX_AMPDU_SIZE_INVALID
-+	   ) {
-+		size = adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_size;
-+		goto exit;
-+	}
-+
-+	/* default value based on max_rx_ampdu_factor */
-+	if (adapter->driver_rx_ampdu_factor != 0xFF)
-+		max_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)adapter->driver_rx_ampdu_factor;
-+	else
-+		rtw_hal_get_def_var(adapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor);
-+	
-+	/* In Maximum A-MPDU Length Exponent subfield of A-MPDU Parameters field of HT Capabilities element,
-+		the unit of max_rx_ampdu_factor are octets. 8K, 16K, 32K, 64K is right.
-+		But the buffer size subfield of Block Ack Parameter Set field in ADDBA action frame indicates
-+		the number of buffers available for this particular TID. Each buffer is equal to max. size of 
-+		MSDU or AMSDU. 
-+		The size variable means how many MSDUs or AMSDUs, it's not Kbytes.
-+	*/
-+	if (MAX_AMPDU_FACTOR_64K == max_rx_ampdu_factor)
-+		size = 64;
-+	else if (MAX_AMPDU_FACTOR_32K == max_rx_ampdu_factor)
-+		size = 32;
-+	else if (MAX_AMPDU_FACTOR_16K == max_rx_ampdu_factor)
-+		size = 16;
-+	else if (MAX_AMPDU_FACTOR_8K == max_rx_ampdu_factor)
-+		size = 8;
-+	else
-+		size = 64;
-+
-+exit:
-+
-+	if (size > 127)
-+		size = 127;
-+
-+	return size;
-+}
-+
-+/**
-+ * rtw_rx_ampdu_is_accept - Get the permission if RX AMPDU should be set up for the specific @adapter
-+ * @adapter: the adapter to get the permission if RX AMPDU should be set up
-+ *
-+ * Returns: accept or not
-+ */
-+bool rtw_rx_ampdu_is_accept(_adapter *adapter)
-+{
-+	bool accept;
-+
-+	if (adapter->fix_rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID) {
-+		accept = adapter->fix_rx_ampdu_accept;
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if (rtw_btcoex_IsBTCoexRejectAMPDU(adapter) == _TRUE) {
-+		accept = _FALSE;
-+		goto exit;
-+	}
-+#endif
-+
-+	/* for scan */
-+	if (!mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_DISABLE)
-+	    && !mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_COMPLETE)
-+	    && adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID
-+	   ) {
-+		accept = adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept;
-+		goto exit;
-+	}
-+
-+	/* default value for other cases */
-+	accept = adapter->mlmeextpriv.mlmext_info.bAcceptAddbaReq;
-+
-+exit:
-+	return accept;
-+}
-+
-+/**
-+ * rtw_rx_ampdu_set_size - Set the target RX AMPDU buffer size for the specific @adapter and specific @reason
-+ * @adapter: the adapter to set target RX AMPDU buffer size
-+ * @size: the target RX AMPDU buffer size to set
-+ * @reason: reason for the target RX AMPDU buffer size setting
-+ *
-+ * Returns: whether the target RX AMPDU buffer size is changed
-+ */
-+bool rtw_rx_ampdu_set_size(_adapter *adapter, u8 size, u8 reason)
-+{
-+	bool is_adj = _FALSE;
-+	struct mlme_ext_priv *mlmeext;
-+	struct mlme_ext_info *mlmeinfo;
-+
-+	mlmeext = &adapter->mlmeextpriv;
-+	mlmeinfo = &mlmeext->mlmext_info;
-+
-+	if (reason == RX_AMPDU_DRV_FIXED) {
-+		if (adapter->fix_rx_ampdu_size != size) {
-+			adapter->fix_rx_ampdu_size = size;
-+			is_adj = _TRUE;
-+			RTW_INFO(FUNC_ADPT_FMT" fix_rx_ampdu_size:%u\n", FUNC_ADPT_ARG(adapter), size);
-+		}
-+	} else if (reason == RX_AMPDU_DRV_SCAN) {
-+		struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res;
-+
-+		if (ss->rx_ampdu_size != size) {
-+			ss->rx_ampdu_size = size;
-+			is_adj = _TRUE;
-+			RTW_INFO(FUNC_ADPT_FMT" ss.rx_ampdu_size:%u\n", FUNC_ADPT_ARG(adapter), size);
-+		}
-+	}
-+
-+	return is_adj;
-+}
-+
-+/**
-+ * rtw_rx_ampdu_set_accept - Set the permission if RX AMPDU should be set up for the specific @adapter and specific @reason
-+ * @adapter: the adapter to set if RX AMPDU should be set up
-+ * @accept: if RX AMPDU should be set up
-+ * @reason: reason for the permission if RX AMPDU should be set up
-+ *
-+ * Returns: whether the permission if RX AMPDU should be set up is changed
-+ */
-+bool rtw_rx_ampdu_set_accept(_adapter *adapter, u8 accept, u8 reason)
-+{
-+	bool is_adj = _FALSE;
-+	struct mlme_ext_priv *mlmeext;
-+	struct mlme_ext_info *mlmeinfo;
-+
-+	mlmeext = &adapter->mlmeextpriv;
-+	mlmeinfo = &mlmeext->mlmext_info;
-+
-+	if (reason == RX_AMPDU_DRV_FIXED) {
-+		if (adapter->fix_rx_ampdu_accept != accept) {
-+			adapter->fix_rx_ampdu_accept = accept;
-+			is_adj = _TRUE;
-+			RTW_INFO(FUNC_ADPT_FMT" fix_rx_ampdu_accept:%u\n", FUNC_ADPT_ARG(adapter), accept);
-+		}
-+	} else if (reason == RX_AMPDU_DRV_SCAN) {
-+		if (adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept != accept) {
-+			adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept = accept;
-+			is_adj = _TRUE;
-+			RTW_INFO(FUNC_ADPT_FMT" ss.rx_ampdu_accept:%u\n", FUNC_ADPT_ARG(adapter), accept);
-+		}
-+	}
-+
-+	return is_adj;
-+}
-+
-+/**
-+ * rx_ampdu_apply_sta_tid - Apply RX AMPDU setting to the specific @sta and @tid
-+ * @adapter: the adapter to which @sta belongs
-+ * @sta: the sta to be checked
-+ * @tid: the tid to be checked
-+ * @accept: the target permission if RX AMPDU should be set up
-+ * @size: the target RX AMPDU buffer size
-+ *
-+ * Returns:
-+ * 0: no canceled
-+ * 1: canceled by no permission
-+ * 2: canceled by different buffer size
-+ * 3: canceled by potential mismatched status
-+ *
-+ * Blocking function, may sleep
-+ */
-+u8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 accept, u8 size)
-+{
-+	u8 ret = 0;
-+	struct recv_reorder_ctrl *reorder_ctl = &sta->recvreorder_ctrl[tid];
-+
-+	if (reorder_ctl->enable == _FALSE) {
-+		if (reorder_ctl->ampdu_size != RX_AMPDU_SIZE_INVALID) {
-+			send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 1);
-+			ret = 3;
-+		}
-+		goto exit;
-+	}
-+
-+	if (accept == _FALSE) {
-+		send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 0);
-+		ret = 1;
-+	} else if (reorder_ctl->ampdu_size != size) {
-+		send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 0);
-+		ret = 2;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+u8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta)
-+{
-+	u8 sz_limit = 0xFF;
-+
-+#ifdef CONFIG_80211N_HT
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+	struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info;
-+	s8 nss = -1;
-+	u8 bw = rtw_min(sta->cmn.bw_mode, adapter->mlmeextpriv.cur_bwmode);
-+
-+	#ifdef CONFIG_80211AC_VHT
-+	if (is_supported_vht(sta->wireless_mode)) {
-+		nss = rtw_min(rtw_vht_mcsmap_to_nss(mlme->vhtpriv.vht_mcs_map)
-+				, rtw_vht_mcsmap_to_nss(sta->vhtpriv.vht_mcs_map));
-+	} else
-+	#endif
-+	if (is_supported_ht(sta->wireless_mode)) {
-+		nss = rtw_min(rtw_ht_mcsset_to_nss(mlmeinfo->HT_caps.u.HT_cap_element.MCS_rate)
-+				, rtw_ht_mcsset_to_nss(sta->htpriv.ht_cap.supp_mcs_set));
-+	}
-+
-+	if (nss >= 1)
-+		sz_limit = regsty->rx_ampdu_sz_limit_by_nss_bw[nss - 1][bw];
-+#endif /* CONFIG_80211N_HT */
-+
-+	return sz_limit;
-+}
-+
-+/**
-+ * rx_ampdu_apply_sta - Apply RX AMPDU setting to the specific @sta
-+ * @adapter: the adapter to which @sta belongs
-+ * @sta: the sta to be checked
-+ * @accept: the target permission if RX AMPDU should be set up
-+ * @size: the target RX AMPDU buffer size
-+ *
-+ * Returns: number of the RX AMPDU assciation canceled for applying current target setting
-+ *
-+ * Blocking function, may sleep
-+ */
-+u8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 size)
-+{
-+	u8 change_cnt = 0;
-+	int i;
-+
-+	for (i = 0; i < TID_NUM; i++) {
-+		if (rx_ampdu_apply_sta_tid(adapter, sta, i, accept, size) != 0)
-+			change_cnt++;
-+	}
-+
-+	return change_cnt;
-+}
-+
-+/**
-+ * rtw_rx_ampdu_apply - Apply the current target RX AMPDU setting for the specific @adapter
-+ * @adapter: the adapter to be applied
-+ *
-+ * Returns: number of the RX AMPDU assciation canceled for applying current target setting
-+ */
-+u16 rtw_rx_ampdu_apply(_adapter *adapter)
-+{
-+	u16 adj_cnt = 0;
-+	struct sta_info *sta;
-+	u8 accept = rtw_rx_ampdu_is_accept(adapter);
-+	u8 size;
-+
-+	if (adapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID)
-+		size = adapter->fix_rx_ampdu_size;
-+	else
-+		size = rtw_rx_ampdu_size(adapter);
-+
-+	if (MLME_IS_STA(adapter)) {
-+		sta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv));
-+		if (sta) {
-+			u8 sta_size = size;
-+
-+			if (adapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID)
-+				sta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta));
-+			adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size);
-+		}
-+		/* TODO: TDLS peer */
-+#ifdef CONFIG_AP_MODE
-+	} else if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
-+		_irqL irqL;
-+		_list *phead, *plist;
-+		u8 peer_num = 0;
-+		char peers[NUM_STA];
-+		struct sta_priv *pstapriv = &adapter->stapriv;
-+		int i;
-+
-+		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+		phead = &pstapriv->asoc_list;
-+		plist = get_next(phead);
-+
-+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+			int stainfo_offset;
-+
-+			sta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+			plist = get_next(plist);
-+
-+			stainfo_offset = rtw_stainfo_offset(pstapriv, sta);
-+			if (stainfo_offset_valid(stainfo_offset))
-+				peers[peer_num++] = stainfo_offset;
-+		}
-+
-+		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+		for (i = 0; i < peer_num; i++) {
-+			sta = rtw_get_stainfo_by_offset(pstapriv, peers[i]);
-+			if (sta) {
-+				u8 sta_size = size;
-+
-+				if (adapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID)
-+					sta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta));
-+				adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size);
-+			}
-+		}
-+#endif /* CONFIG_AP_MODE */
-+	}
-+
-+	/* TODO: ADHOC */
-+
-+	return adj_cnt;
-+}
-+
-+unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	u8 *addr;
-+	struct sta_info *psta = NULL;
-+	struct recv_reorder_ctrl *preorder_ctrl;
-+	unsigned char		*frame_body;
-+	unsigned char		category, action;
-+	unsigned short	tid, status, reason_code = 0;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct registry_priv *pregpriv = &padapter->registrypriv;
-+
-+#ifdef CONFIG_80211N_HT
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	/* check RA matches or not	 */
-+	if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))
-+		return _SUCCESS;
-+
-+#if 0
-+	/* check A1 matches or not */
-+	if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN))
-+		return _SUCCESS;
-+#endif
-+
-+	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
-+		if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS))
-+			return _SUCCESS;
-+
-+	addr = get_addr2_ptr(pframe);
-+	psta = rtw_get_stainfo(pstapriv, addr);
-+
-+	if (psta == NULL)
-+		return _SUCCESS;
-+
-+	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
-+
-+	category = frame_body[0];
-+	if (category == RTW_WLAN_CATEGORY_BACK) { /* representing Block Ack */
-+#ifdef CONFIG_TDLS
-+		if ((psta->tdls_sta_state & TDLS_LINKED_STATE) &&
-+		    (psta->htpriv.ht_option == _TRUE) &&
-+		    (psta->htpriv.ampdu_enable == _TRUE))
-+			RTW_INFO("Recv [%s] from direc link\n", __FUNCTION__);
-+		else
-+#endif /* CONFIG_TDLS */
-+			if (!pmlmeinfo->HT_enable)
-+				return _SUCCESS;
-+
-+		action = frame_body[1];
-+		RTW_INFO("%s, action=%d\n", __FUNCTION__, action);
-+		switch (action) {
-+		case RTW_WLAN_ACTION_ADDBA_REQ: /* ADDBA request */
-+
-+			_rtw_memcpy(&(pmlmeinfo->ADDBA_req), &(frame_body[2]), sizeof(struct ADDBA_request));
-+			/* process_addba_req(padapter, (u8*)&(pmlmeinfo->ADDBA_req), GetAddr3Ptr(pframe)); */
-+			process_addba_req(padapter, (u8 *)&(pmlmeinfo->ADDBA_req), addr);
-+
-+			break;
-+
-+		case RTW_WLAN_ACTION_ADDBA_RESP: /* ADDBA response */
-+
-+			/* status = frame_body[3] | (frame_body[4] << 8); */ /* endian issue */
-+			status = RTW_GET_LE16(&frame_body[3]);
-+			tid = ((frame_body[5] >> 2) & 0x7);
-+			if (status == 0) {
-+				/* successful */
-+				RTW_INFO("agg_enable for TID=%d\n", tid);
-+				psta->htpriv.agg_enable_bitmap |= 1 << tid;
-+				psta->htpriv.candidate_tid_bitmap &= ~BIT(tid);
-+				/* amsdu in ampdu */
-+				if (pregpriv->tx_ampdu_amsdu == 0)
-+					psta->htpriv.tx_amsdu_enable = _FALSE;
-+				else if (pregpriv->tx_ampdu_amsdu == 1)
-+					psta->htpriv.tx_amsdu_enable = _TRUE;
-+				else {
-+					if (frame_body[5] & 1)
-+						psta->htpriv.tx_amsdu_enable = _TRUE;
-+				}
-+			} else
-+				psta->htpriv.agg_enable_bitmap &= ~BIT(tid);
-+
-+			#ifdef CONFIG_AP_MODE
-+			if (psta->state & WIFI_STA_ALIVE_CHK_STATE) {
-+				RTW_INFO("%s alive check - rx ADDBA response\n", __func__);
-+				psta->htpriv.agg_enable_bitmap &= ~BIT(tid);
-+				psta->expire_to = pstapriv->expire_to;
-+				psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
-+			}
-+			#endif
-+
-+			/* RTW_INFO("marc: ADDBA RSP: %x\n", pmlmeinfo->agg_enable_bitmap); */
-+			break;
-+
-+		case RTW_WLAN_ACTION_DELBA: /* DELBA */
-+			if ((frame_body[3] & BIT(3)) == 0) {
-+				psta->htpriv.agg_enable_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf));
-+				psta->htpriv.candidate_tid_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf));
-+
-+				/* reason_code = frame_body[4] | (frame_body[5] << 8); */
-+				reason_code = RTW_GET_LE16(&frame_body[4]);
-+			} else if ((frame_body[3] & BIT(3)) == BIT(3)) {
-+				tid = (frame_body[3] >> 4) & 0x0F;
-+
-+				preorder_ctrl = &psta->recvreorder_ctrl[tid];
-+				preorder_ctrl->enable = _FALSE;
-+				preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;
-+			}
-+
-+			RTW_INFO("%s(): DELBA: %x(%x)\n", __FUNCTION__, pmlmeinfo->agg_enable_bitmap, reason_code);
-+			/* todo: how to notify the host while receiving DELETE BA */
-+			break;
-+
-+		default:
-+			break;
-+		}
-+	}
-+#endif /* CONFIG_80211N_HT */
-+	return _SUCCESS;
-+}
-+
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+u32 rtw_build_vendor_ie(_adapter *padapter , unsigned char **pframe , u8 mgmt_frame_tyte)
-+{
-+	int vendor_ie_num = 0;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	u32 len = 0;
-+
-+	for (vendor_ie_num = 0 ; vendor_ie_num < WLAN_MAX_VENDOR_IE_NUM ; vendor_ie_num++) {
-+		if (pmlmepriv->vendor_ielen[vendor_ie_num] > 0 && pmlmepriv->vendor_ie_mask[vendor_ie_num] & mgmt_frame_tyte) {
-+			_rtw_memcpy(*pframe , pmlmepriv->vendor_ie[vendor_ie_num] , pmlmepriv->vendor_ielen[vendor_ie_num]);
-+			*pframe +=  pmlmepriv->vendor_ielen[vendor_ie_num];
-+			len += pmlmepriv->vendor_ielen[vendor_ie_num];
-+		}
-+	}
-+
-+	return len;
-+}
-+#endif
-+
-+#ifdef CONFIG_P2P
-+int get_reg_classes_full_count(struct p2p_channels *channel_list)
-+{
-+	int cnt = 0;
-+	int i;
-+
-+	for (i = 0; i < channel_list->reg_classes; i++)
-+		cnt += channel_list->reg_class[i].channels;
-+
-+	return cnt;
-+}
-+
-+void issue_p2p_GO_request(_adapter *padapter, u8 *raddr)
-+{
-+	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
-+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
-+	u8			action = P2P_PUB_ACTION_ACTION;
-+	u32			p2poui = cpu_to_be32(P2POUI);
-+	u8			oui_subtype = P2P_GO_NEGO_REQ;
-+	u8			wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };
-+	u8			wpsielen = 0, p2pielen = 0;
-+	u16			len_channellist_attr = 0;
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	RTW_INFO("[%s] In\n", __FUNCTION__);
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
-+	pwdinfo->negotiation_dialog_token = 1;	/*	Initialize the dialog value */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &pwdinfo->negotiation_dialog_token, &(pattrib->pktlen));
-+
-+
-+
-+	/*	WPS Section */
-+	wpsielen = 0;
-+	/*	WPS OUI */
-+	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
-+	wpsielen += 4;
-+
-+	/*	WPS version */
-+	/*	Type: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
-+	wpsielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+	wpsielen += 2;
-+
-+	/*	Value: */
-+	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
-+
-+	/*	Device Password ID */
-+	/*	Type: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);
-+	wpsielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
-+	wpsielen += 2;
-+
-+	/*	Value: */
-+
-+	if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN)
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC);
-+	else if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN)
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);
-+	else if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC)
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC);
-+
-+	wpsielen += 2;
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
-+
-+
-+	/*	P2P IE Section. */
-+
-+	/*	P2P OUI */
-+	p2pielen = 0;
-+	p2pie[p2pielen++] = 0x50;
-+	p2pie[p2pielen++] = 0x6F;
-+	p2pie[p2pielen++] = 0x9A;
-+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+	/*	Commented by Albert 20110306 */
-+	/*	According to the P2P Specification, the group negoitation request frame should contain 9 P2P attributes */
-+	/*	1. P2P Capability */
-+	/*	2. Group Owner Intent */
-+	/*	3. Configuration Timeout */
-+	/*	4. Listen Channel */
-+	/*	5. Extended Listen Timing */
-+	/*	6. Intended P2P Interface Address */
-+	/*	7. Channel List */
-+	/*	8. P2P Device Info */
-+	/*	9. Operating Channel */
-+
-+
-+	/*	P2P Capability */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Device Capability Bitmap, 1 byte */
-+	p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
-+
-+	/*	Group Capability Bitmap, 1 byte */
-+	if (pwdinfo->persistent_supported)
-+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
-+	else
-+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;
-+
-+
-+	/*	Group Owner Intent */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_GO_INTENT;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Todo the tie breaker bit. */
-+	p2pie[p2pielen++] = ((pwdinfo->intent << 1) &  0xFE);
-+
-+	/*	Configuration Timeout */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
-+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
-+
-+
-+	/*	Listen Channel */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_LISTEN_CH;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Country String */
-+	p2pie[p2pielen++] = 'X';
-+	p2pie[p2pielen++] = 'X';
-+
-+	/*	The third byte should be set to 0x04. */
-+	/*	Described in the "Operating Channel Attribute" section. */
-+	p2pie[p2pielen++] = 0x04;
-+
-+	/*	Operating Class */
-+	p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
-+
-+	/*	Channel Number */
-+	p2pie[p2pielen++] = pwdinfo->listen_channel;	/*	listening channel number */
-+
-+
-+	/*	Extended Listen Timing ATTR */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Availability Period */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
-+	p2pielen += 2;
-+
-+	/*	Availability Interval */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
-+	p2pielen += 2;
-+
-+
-+	/*	Intended P2P Interface Address */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
-+	p2pielen += ETH_ALEN;
-+
-+
-+	/*	Channel List */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
-+
-+	/* Length: */
-+	/* Country String(3) */
-+	/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
-+	/* + number of channels in all classes */
-+	len_channellist_attr = 3
-+		       + (1 + 1) * (u16)(ch_list->reg_classes)
-+		       + get_reg_classes_full_count(ch_list);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
-+	else
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
-+#else
-+
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
-+
-+#endif
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Country String */
-+	p2pie[p2pielen++] = 'X';
-+	p2pie[p2pielen++] = 'X';
-+
-+	/*	The third byte should be set to 0x04. */
-+	/*	Described in the "Operating Channel Attribute" section. */
-+	p2pie[p2pielen++] = 0x04;
-+
-+	/*	Channel Entry List */
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
-+		u8 union_ch = rtw_mi_get_union_chan(padapter);
-+
-+		/*	Operating Class */
-+		if (union_ch > 14) {
-+			if (union_ch >= 149)
-+				p2pie[p2pielen++] = 0x7c;
-+			else
-+				p2pie[p2pielen++] = 0x73;
-+		} else
-+			p2pie[p2pielen++] = 0x51;
-+
-+
-+		/*	Number of Channels */
-+		/*	Just support 1 channel and this channel is AP's channel */
-+		p2pie[p2pielen++] = 1;
-+
-+		/*	Channel List */
-+		p2pie[p2pielen++] = union_ch;
-+	} else
-+#endif /* CONFIG_CONCURRENT_MODE */
-+	{
-+		int i, j;
-+		for (j = 0; j < ch_list->reg_classes; j++) {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
-+
-+			/*	Number of Channels */
-+			p2pie[p2pielen++] = ch_list->reg_class[j].channels;
-+
-+			/*	Channel List */
-+			for (i = 0; i < ch_list->reg_class[j].channels; i++)
-+				p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
-+		}
-+	}
-+
-+	/*	Device Info */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
-+	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	P2P Device Address */
-+	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
-+	p2pielen += ETH_ALEN;
-+
-+	/*	Config Method */
-+	/*	This field should be big endian. Noted by P2P specification. */
-+
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
-+
-+	p2pielen += 2;
-+
-+	/*	Primary Device Type */
-+	/*	Category ID */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
-+	p2pielen += 2;
-+
-+	/*	OUI */
-+	*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
-+	p2pielen += 4;
-+
-+	/*	Sub Category ID */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
-+	p2pielen += 2;
-+
-+	/*	Number of Secondary Device Types */
-+	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
-+
-+	/*	Device Name */
-+	/*	Type: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
-+	p2pielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len);
-+	p2pielen += pwdinfo->device_name_len;
-+
-+
-+	/*	Operating Channel */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Country String */
-+	p2pie[p2pielen++] = 'X';
-+	p2pie[p2pielen++] = 'X';
-+
-+	/*	The third byte should be set to 0x04. */
-+	/*	Described in the "Operating Channel Attribute" section. */
-+	p2pie[p2pielen++] = 0x04;
-+
-+	/*	Operating Class */
-+	if (pwdinfo->operating_channel <= 14) {
-+		/*	Operating Class */
-+		p2pie[p2pielen++] = 0x51;
-+	} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
-+		/*	Operating Class */
-+		p2pie[p2pielen++] = 0x73;
-+	} else {
-+		/*	Operating Class */
-+		p2pie[p2pielen++] = 0x7c;
-+	}
-+
-+	/*	Channel Number */
-+	p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = build_nego_req_wfd_ie(pwdinfo, pframe);
-+	pframe += wfdielen;
-+	pattrib->pktlen += wfdielen;
-+#endif
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return;
-+
-+}
-+
-+
-+void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint len, u8 result)
-+{
-+	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
-+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
-+	u8			action = P2P_PUB_ACTION_ACTION;
-+	u32			p2poui = cpu_to_be32(P2POUI);
-+	u8			oui_subtype = P2P_GO_NEGO_RESP;
-+	u8			wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };
-+	u8			p2pielen = 0;
-+	uint			wpsielen = 0;
-+	u16			wps_devicepassword_id = 0x0000;
-+	uint			wps_devicepassword_id_len = 0;
-+	u16			len_channellist_attr = 0;
-+
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	RTW_INFO("[%s] In, result = %d\n", __FUNCTION__,  result);
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
-+	pwdinfo->negotiation_dialog_token = frame_body[7];	/*	The Dialog Token of provisioning discovery request frame. */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen));
-+
-+	/*	Commented by Albert 20110328 */
-+	/*	Try to get the device password ID from the WPS IE of group negotiation request frame */
-+	/*	WiFi Direct test plan 5.1.15 */
-+	rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen);
-+	rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len);
-+	wps_devicepassword_id = be16_to_cpu(wps_devicepassword_id);
-+
-+	_rtw_memset(wpsie, 0x00, 255);
-+	wpsielen = 0;
-+
-+	/*	WPS Section */
-+	wpsielen = 0;
-+	/*	WPS OUI */
-+	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
-+	wpsielen += 4;
-+
-+	/*	WPS version */
-+	/*	Type: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
-+	wpsielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+	wpsielen += 2;
-+
-+	/*	Value: */
-+	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
-+
-+	/*	Device Password ID */
-+	/*	Type: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);
-+	wpsielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
-+	wpsielen += 2;
-+
-+	/*	Value: */
-+	if (wps_devicepassword_id == WPS_DPID_USER_SPEC)
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);
-+	else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC);
-+	else
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC);
-+	wpsielen += 2;
-+
-+	/*	Commented by Kurt 20120113 */
-+	/*	If some device wants to do p2p handshake without sending prov_disc_req */
-+	/*	We have to get peer_req_cm from here. */
-+	if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3)) {
-+		if (wps_devicepassword_id == WPS_DPID_USER_SPEC)
-+			_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3);
-+		else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)
-+			_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3);
-+		else
-+			_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3);
-+	}
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
-+
-+
-+	/*	P2P IE Section. */
-+
-+	/*	P2P OUI */
-+	p2pielen = 0;
-+	p2pie[p2pielen++] = 0x50;
-+	p2pie[p2pielen++] = 0x6F;
-+	p2pie[p2pielen++] = 0x9A;
-+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+	/*	Commented by Albert 20100908 */
-+	/*	According to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes */
-+	/*	1. Status */
-+	/*	2. P2P Capability */
-+	/*	3. Group Owner Intent */
-+	/*	4. Configuration Timeout */
-+	/*	5. Operating Channel */
-+	/*	6. Intended P2P Interface Address */
-+	/*	7. Channel List */
-+	/*	8. Device Info */
-+	/*	9. Group ID	( Only GO ) */
-+
-+
-+	/*	ToDo: */
-+
-+	/*	P2P Status */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_STATUS;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	p2pie[p2pielen++] = result;
-+
-+	/*	P2P Capability */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Device Capability Bitmap, 1 byte */
-+
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
-+		/*	Commented by Albert 2011/03/08 */
-+		/*	According to the P2P specification */
-+		/*	if the sending device will be client, the P2P Capability should be reserved of group negotation response frame */
-+		p2pie[p2pielen++] = 0;
-+	} else {
-+		/*	Be group owner or meet the error case */
-+		p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
-+	}
-+
-+	/*	Group Capability Bitmap, 1 byte */
-+	if (pwdinfo->persistent_supported)
-+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
-+	else
-+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;
-+
-+	/*	Group Owner Intent */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_GO_INTENT;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	if (pwdinfo->peer_intent & 0x01) {
-+		/*	Peer's tie breaker bit is 1, our tie breaker bit should be 0 */
-+		p2pie[p2pielen++] = (pwdinfo->intent << 1);
-+	} else {
-+		/*	Peer's tie breaker bit is 0, our tie breaker bit should be 1 */
-+		p2pie[p2pielen++] = ((pwdinfo->intent << 1) | BIT(0));
-+	}
-+
-+
-+	/*	Configuration Timeout */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
-+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
-+
-+	/*	Operating Channel */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Country String */
-+	p2pie[p2pielen++] = 'X';
-+	p2pie[p2pielen++] = 'X';
-+
-+	/*	The third byte should be set to 0x04. */
-+	/*	Described in the "Operating Channel Attribute" section. */
-+	p2pie[p2pielen++] = 0x04;
-+
-+	/*	Operating Class */
-+	if (pwdinfo->operating_channel <= 14) {
-+		/*	Operating Class */
-+		p2pie[p2pielen++] = 0x51;
-+	} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
-+		/*	Operating Class */
-+		p2pie[p2pielen++] = 0x73;
-+	} else {
-+		/*	Operating Class */
-+		p2pie[p2pielen++] = 0x7c;
-+	}
-+
-+	/*	Channel Number */
-+	p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
-+
-+	/*	Intended P2P Interface Address	 */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
-+	p2pielen += ETH_ALEN;
-+
-+	/*	Channel List */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
-+
-+	/* Country String(3) */
-+	/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
-+	/* + number of channels in all classes */
-+	len_channellist_attr = 3
-+		       + (1 + 1) * (u16)ch_list->reg_classes
-+		       + get_reg_classes_full_count(ch_list);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
-+	else
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
-+#else
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
-+
-+#endif
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Country String */
-+	p2pie[p2pielen++] = 'X';
-+	p2pie[p2pielen++] = 'X';
-+
-+	/*	The third byte should be set to 0x04. */
-+	/*	Described in the "Operating Channel Attribute" section. */
-+	p2pie[p2pielen++] = 0x04;
-+
-+	/*	Channel Entry List */
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
-+
-+		u8 union_chan = rtw_mi_get_union_chan(padapter);
-+
-+		/*Operating Class*/
-+		if (union_chan > 14) {
-+			if (union_chan >= 149)
-+				p2pie[p2pielen++] = 0x7c;
-+			else
-+				p2pie[p2pielen++] = 0x73;
-+
-+		} else
-+			p2pie[p2pielen++] = 0x51;
-+
-+		/*	Number of Channels
-+			Just support 1 channel and this channel is AP's channel*/
-+		p2pie[p2pielen++] = 1;
-+
-+		/*Channel List*/
-+		p2pie[p2pielen++] = union_chan;
-+	} else
-+#endif /* CONFIG_CONCURRENT_MODE */
-+	{
-+		int i, j;
-+		for (j = 0; j < ch_list->reg_classes; j++) {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
-+
-+			/*	Number of Channels */
-+			p2pie[p2pielen++] = ch_list->reg_class[j].channels;
-+
-+			/*	Channel List */
-+			for (i = 0; i < ch_list->reg_class[j].channels; i++)
-+				p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
-+		}
-+	}
-+
-+	/*	Device Info */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
-+	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	P2P Device Address */
-+	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
-+	p2pielen += ETH_ALEN;
-+
-+	/*	Config Method */
-+	/*	This field should be big endian. Noted by P2P specification. */
-+
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
-+
-+	p2pielen += 2;
-+
-+	/*	Primary Device Type */
-+	/*	Category ID */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
-+	p2pielen += 2;
-+
-+	/*	OUI */
-+	*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
-+	p2pielen += 4;
-+
-+	/*	Sub Category ID */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
-+	p2pielen += 2;
-+
-+	/*	Number of Secondary Device Types */
-+	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
-+
-+	/*	Device Name */
-+	/*	Type: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
-+	p2pielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len);
-+	p2pielen += pwdinfo->device_name_len;
-+
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+		/*	Group ID Attribute */
-+		/*	Type: */
-+		p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
-+
-+		/*	Length: */
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen);
-+		p2pielen += 2;
-+
-+		/*	Value: */
-+		/*	p2P Device Address */
-+		_rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN);
-+		p2pielen += ETH_ALEN;
-+
-+		/*	SSID */
-+		_rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
-+		p2pielen += pwdinfo->nego_ssidlen;
-+
-+	}
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe);
-+	pframe += wfdielen;
-+	pattrib->pktlen += wfdielen;
-+#endif
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return;
-+
-+}
-+
-+void issue_p2p_GO_confirm(_adapter *padapter, u8 *raddr, u8 result)
-+{
-+
-+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
-+	u8			action = P2P_PUB_ACTION_ACTION;
-+	u32			p2poui = cpu_to_be32(P2POUI);
-+	u8			oui_subtype = P2P_GO_NEGO_CONF;
-+	u8			p2pie[255] = { 0x00 };
-+	u8			p2pielen = 0;
-+
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	RTW_INFO("[%s] In\n", __FUNCTION__);
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen));
-+
-+
-+
-+	/*	P2P IE Section. */
-+
-+	/*	P2P OUI */
-+	p2pielen = 0;
-+	p2pie[p2pielen++] = 0x50;
-+	p2pie[p2pielen++] = 0x6F;
-+	p2pie[p2pielen++] = 0x9A;
-+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+	/*	Commented by Albert 20110306 */
-+	/*	According to the P2P Specification, the group negoitation request frame should contain 5 P2P attributes */
-+	/*	1. Status */
-+	/*	2. P2P Capability */
-+	/*	3. Operating Channel */
-+	/*	4. Channel List */
-+	/*	5. Group ID	( if this WiFi is GO ) */
-+
-+	/*	P2P Status */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_STATUS;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	p2pie[p2pielen++] = result;
-+
-+	/*	P2P Capability */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Device Capability Bitmap, 1 byte */
-+	p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
-+
-+	/*	Group Capability Bitmap, 1 byte */
-+	if (pwdinfo->persistent_supported)
-+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
-+	else
-+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;
-+
-+
-+	/*	Operating Channel */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Country String */
-+	p2pie[p2pielen++] = 'X';
-+	p2pie[p2pielen++] = 'X';
-+
-+	/*	The third byte should be set to 0x04. */
-+	/*	Described in the "Operating Channel Attribute" section. */
-+	p2pie[p2pielen++] = 0x04;
-+
-+
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
-+		if (pwdinfo->peer_operating_ch <= 14) {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x51;
-+		} else if ((pwdinfo->peer_operating_ch >= 36) && (pwdinfo->peer_operating_ch <= 48)) {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x73;
-+		} else {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x7c;
-+		}
-+
-+		p2pie[p2pielen++] = pwdinfo->peer_operating_ch;
-+	} else {
-+		if (pwdinfo->operating_channel <= 14) {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x51;
-+		} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x73;
-+		} else {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x7c;
-+		}
-+
-+		/*	Channel Number */
-+		p2pie[p2pielen++] = pwdinfo->operating_channel;		/*	Use the listen channel as the operating channel */
-+	}
-+
-+
-+	/*	Channel List */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
-+
-+	*(u16 *)(p2pie + p2pielen) = 6;
-+	p2pielen += 2;
-+
-+	/*	Country String */
-+	p2pie[p2pielen++] = 'X';
-+	p2pie[p2pielen++] = 'X';
-+
-+	/*	The third byte should be set to 0x04. */
-+	/*	Described in the "Operating Channel Attribute" section. */
-+	p2pie[p2pielen++] = 0x04;
-+
-+	/*	Value: */
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
-+		if (pwdinfo->peer_operating_ch <= 14) {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x51;
-+		} else if ((pwdinfo->peer_operating_ch >= 36) && (pwdinfo->peer_operating_ch <= 48)) {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x73;
-+		} else {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x7c;
-+		}
-+		p2pie[p2pielen++] = 1;
-+		p2pie[p2pielen++] = pwdinfo->peer_operating_ch;
-+	} else {
-+		if (pwdinfo->operating_channel <= 14) {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x51;
-+		} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x73;
-+		} else {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x7c;
-+		}
-+
-+		/*	Channel Number */
-+		p2pie[p2pielen++] = 1;
-+		p2pie[p2pielen++] = pwdinfo->operating_channel;		/*	Use the listen channel as the operating channel */
-+	}
-+
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+		/*	Group ID Attribute */
-+		/*	Type: */
-+		p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
-+
-+		/*	Length: */
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen);
-+		p2pielen += 2;
-+
-+		/*	Value: */
-+		/*	p2P Device Address */
-+		_rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN);
-+		p2pielen += ETH_ALEN;
-+
-+		/*	SSID */
-+		_rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
-+		p2pielen += pwdinfo->nego_ssidlen;
-+	}
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = build_nego_confirm_wfd_ie(pwdinfo, pframe);
-+	pframe += wfdielen;
-+	pattrib->pktlen += wfdielen;
-+#endif
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return;
-+
-+}
-+
-+void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr)
-+{
-+	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
-+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
-+	u8			action = P2P_PUB_ACTION_ACTION;
-+	u32			p2poui = cpu_to_be32(P2POUI);
-+	u8			oui_subtype = P2P_INVIT_REQ;
-+	u8			p2pie[255] = { 0x00 };
-+	u8			p2pielen = 0;
-+	u8			dialogToken = 3;
-+	u16			len_channellist_attr = 0;
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, raddr,  ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
-+
-+	/*	P2P IE Section. */
-+
-+	/*	P2P OUI */
-+	p2pielen = 0;
-+	p2pie[p2pielen++] = 0x50;
-+	p2pie[p2pielen++] = 0x6F;
-+	p2pie[p2pielen++] = 0x9A;
-+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+	/*	Commented by Albert 20101011 */
-+	/*	According to the P2P Specification, the P2P Invitation request frame should contain 7 P2P attributes */
-+	/*	1. Configuration Timeout */
-+	/*	2. Invitation Flags */
-+	/*	3. Operating Channel	( Only GO ) */
-+	/*	4. P2P Group BSSID	( Should be included if I am the GO ) */
-+	/*	5. Channel List */
-+	/*	6. P2P Group ID */
-+	/*	7. P2P Device Info */
-+
-+	/*	Configuration Timeout */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
-+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
-+
-+	/*	Invitation Flags */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_INVITATION_FLAGS;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	p2pie[p2pielen++] = P2P_INVITATION_FLAGS_PERSISTENT;
-+
-+
-+	/*	Operating Channel */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Country String */
-+	p2pie[p2pielen++] = 'X';
-+	p2pie[p2pielen++] = 'X';
-+
-+	/*	The third byte should be set to 0x04. */
-+	/*	Described in the "Operating Channel Attribute" section. */
-+	p2pie[p2pielen++] = 0x04;
-+
-+	/*	Operating Class */
-+	if (pwdinfo->invitereq_info.operating_ch <= 14)
-+		p2pie[p2pielen++] = 0x51;
-+	else if ((pwdinfo->invitereq_info.operating_ch >= 36) && (pwdinfo->invitereq_info.operating_ch <= 48))
-+		p2pie[p2pielen++] = 0x73;
-+	else
-+		p2pie[p2pielen++] = 0x7c;
-+
-+	/*	Channel Number */
-+	p2pie[p2pielen++] = pwdinfo->invitereq_info.operating_ch;	/*	operating channel number */
-+
-+	if (_rtw_memcmp(adapter_mac_addr(padapter), pwdinfo->invitereq_info.go_bssid, ETH_ALEN)) {
-+		/*	P2P Group BSSID */
-+		/*	Type: */
-+		p2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID;
-+
-+		/*	Length: */
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
-+		p2pielen += 2;
-+
-+		/*	Value: */
-+		/*	P2P Device Address for GO */
-+		_rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN);
-+		p2pielen += ETH_ALEN;
-+	}
-+
-+	/*	Channel List */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
-+
-+
-+	/*	Length: */
-+	/* Country String(3) */
-+	/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
-+	/* + number of channels in all classes */
-+	len_channellist_attr = 3
-+		       + (1 + 1) * (u16)ch_list->reg_classes
-+		       + get_reg_classes_full_count(ch_list);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
-+	else
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
-+#else
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
-+#endif
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Country String */
-+	p2pie[p2pielen++] = 'X';
-+	p2pie[p2pielen++] = 'X';
-+
-+	/*	The third byte should be set to 0x04. */
-+	/*	Described in the "Operating Channel Attribute" section. */
-+	p2pie[p2pielen++] = 0x04;
-+
-+	/*	Channel Entry List */
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
-+		u8 union_ch =  rtw_mi_get_union_chan(padapter);
-+
-+		/*	Operating Class */
-+		if (union_ch > 14) {
-+			if (union_ch >= 149)
-+				p2pie[p2pielen++] = 0x7c;
-+			else
-+				p2pie[p2pielen++] = 0x73;
-+		} else
-+			p2pie[p2pielen++] = 0x51;
-+
-+
-+		/*	Number of Channels */
-+		/*	Just support 1 channel and this channel is AP's channel */
-+		p2pie[p2pielen++] = 1;
-+
-+		/*	Channel List */
-+		p2pie[p2pielen++] = union_ch;
-+	} else
-+#endif /* CONFIG_CONCURRENT_MODE */
-+	{
-+		int i, j;
-+		for (j = 0; j < ch_list->reg_classes; j++) {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
-+
-+			/*	Number of Channels */
-+			p2pie[p2pielen++] = ch_list->reg_class[j].channels;
-+
-+			/*	Channel List */
-+			for (i = 0; i < ch_list->reg_class[j].channels; i++)
-+				p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
-+		}
-+	}
-+
-+
-+	/*	P2P Group ID */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(6 + pwdinfo->invitereq_info.ssidlen);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	P2P Device Address for GO */
-+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN);
-+	p2pielen += ETH_ALEN;
-+
-+	/*	SSID */
-+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_ssid, pwdinfo->invitereq_info.ssidlen);
-+	p2pielen += pwdinfo->invitereq_info.ssidlen;
-+
-+
-+	/*	Device Info */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
-+	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	P2P Device Address */
-+	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
-+	p2pielen += ETH_ALEN;
-+
-+	/*	Config Method */
-+	/*	This field should be big endian. Noted by P2P specification. */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_DISPLAY);
-+	p2pielen += 2;
-+
-+	/*	Primary Device Type */
-+	/*	Category ID */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
-+	p2pielen += 2;
-+
-+	/*	OUI */
-+	*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
-+	p2pielen += 4;
-+
-+	/*	Sub Category ID */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
-+	p2pielen += 2;
-+
-+	/*	Number of Secondary Device Types */
-+	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
-+
-+	/*	Device Name */
-+	/*	Type: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
-+	p2pielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);
-+	p2pielen += pwdinfo->device_name_len;
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = build_invitation_req_wfd_ie(pwdinfo, pframe);
-+	pframe += wfdielen;
-+	pattrib->pktlen += wfdielen;
-+#endif
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return;
-+
-+}
-+
-+void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 status_code)
-+{
-+	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
-+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
-+	u8			action = P2P_PUB_ACTION_ACTION;
-+	u32			p2poui = cpu_to_be32(P2POUI);
-+	u8			oui_subtype = P2P_INVIT_RESP;
-+	u8			p2pie[255] = { 0x00 };
-+	u8			p2pielen = 0;
-+	u16			len_channellist_attr = 0;
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, raddr,  ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
-+
-+	/*	P2P IE Section. */
-+
-+	/*	P2P OUI */
-+	p2pielen = 0;
-+	p2pie[p2pielen++] = 0x50;
-+	p2pie[p2pielen++] = 0x6F;
-+	p2pie[p2pielen++] = 0x9A;
-+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+	/*	Commented by Albert 20101005 */
-+	/*	According to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes */
-+	/*	1. Status */
-+	/*	2. Configuration Timeout */
-+	/*	3. Operating Channel	( Only GO ) */
-+	/*	4. P2P Group BSSID	( Only GO ) */
-+	/*	5. Channel List */
-+
-+	/*	P2P Status */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_STATUS;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	When status code is P2P_STATUS_FAIL_INFO_UNAVAILABLE. */
-+	/*	Sent the event receiving the P2P Invitation Req frame to DMP UI. */
-+	/*	DMP had to compare the MAC address to find out the profile. */
-+	/*	So, the WiFi driver will send the P2P_STATUS_FAIL_INFO_UNAVAILABLE to NB. */
-+	/*	If the UI found the corresponding profile, the WiFi driver sends the P2P Invitation Req */
-+	/*	to NB to rebuild the persistent group. */
-+	p2pie[p2pielen++] = status_code;
-+
-+	/*	Configuration Timeout */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
-+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
-+
-+	if (status_code == P2P_STATUS_SUCCESS) {
-+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+			/*	The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO */
-+			/*	In this case, the P2P Invitation response frame should carry the two more P2P attributes. */
-+			/*	First one is operating channel attribute. */
-+			/*	Second one is P2P Group BSSID attribute. */
-+
-+			/*	Operating Channel */
-+			/*	Type: */
-+			p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
-+
-+			/*	Length: */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
-+			p2pielen += 2;
-+
-+			/*	Value: */
-+			/*	Country String */
-+			p2pie[p2pielen++] = 'X';
-+			p2pie[p2pielen++] = 'X';
-+
-+			/*	The third byte should be set to 0x04. */
-+			/*	Described in the "Operating Channel Attribute" section. */
-+			p2pie[p2pielen++] = 0x04;
-+
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
-+
-+			/*	Channel Number */
-+			p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
-+
-+
-+			/*	P2P Group BSSID */
-+			/*	Type: */
-+			p2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID;
-+
-+			/*	Length: */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
-+			p2pielen += 2;
-+
-+			/*	Value: */
-+			/*	P2P Device Address for GO */
-+			_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
-+			p2pielen += ETH_ALEN;
-+
-+		}
-+
-+		/*	Channel List */
-+		/*	Type: */
-+		p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
-+
-+		/*	Length: */
-+		/* Country String(3) */
-+		/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
-+		/* + number of channels in all classes */
-+		len_channellist_attr = 3
-+			+ (1 + 1) * (u16)ch_list->reg_classes
-+			+ get_reg_classes_full_count(ch_list);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
-+		else
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
-+#else
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
-+#endif
-+		p2pielen += 2;
-+
-+		/*	Value: */
-+		/*	Country String */
-+		p2pie[p2pielen++] = 'X';
-+		p2pie[p2pielen++] = 'X';
-+
-+		/*	The third byte should be set to 0x04. */
-+		/*	Described in the "Operating Channel Attribute" section. */
-+		p2pie[p2pielen++] = 0x04;
-+
-+		/*	Channel Entry List */
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
-+			u8 union_ch = rtw_mi_get_union_chan(padapter);
-+
-+			/*	Operating Class */
-+			if (union_ch > 14) {
-+				if (union_ch >= 149)
-+					p2pie[p2pielen++]  = 0x7c;
-+				else
-+					p2pie[p2pielen++] = 0x73;
-+			} else
-+				p2pie[p2pielen++] = 0x51;
-+
-+
-+			/*	Number of Channels */
-+			/*	Just support 1 channel and this channel is AP's channel */
-+			p2pie[p2pielen++] = 1;
-+
-+			/*	Channel List */
-+			p2pie[p2pielen++] = union_ch;
-+		} else
-+#endif /* CONFIG_CONCURRENT_MODE */
-+		{
-+			int i, j;
-+			for (j = 0; j < ch_list->reg_classes; j++) {
-+				/*	Operating Class */
-+				p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
-+
-+				/*	Number of Channels */
-+				p2pie[p2pielen++] = ch_list->reg_class[j].channels;
-+
-+				/*	Channel List */
-+				for (i = 0; i < ch_list->reg_class[j].channels; i++)
-+					p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
-+			}
-+		}
-+	}
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = build_invitation_resp_wfd_ie(pwdinfo, pframe);
-+	pframe += wfdielen;
-+	pattrib->pktlen += wfdielen;
-+#endif
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return;
-+
-+}
-+
-+void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr)
-+{
-+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
-+	u8			action = P2P_PUB_ACTION_ACTION;
-+	u8			dialogToken = 1;
-+	u32			p2poui = cpu_to_be32(P2POUI);
-+	u8			oui_subtype = P2P_PROVISION_DISC_REQ;
-+	u8			wpsie[100] = { 0x00 };
-+	u8			wpsielen = 0;
-+	u32			p2pielen = 0;
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	RTW_INFO("[%s] In\n", __FUNCTION__);
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, pdev_raddr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, pdev_raddr, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
-+
-+	p2pielen = build_prov_disc_request_p2p_ie(pwdinfo, pframe, pssid, ussidlen, pdev_raddr);
-+
-+	pframe += p2pielen;
-+	pattrib->pktlen += p2pielen;
-+
-+	wpsielen = 0;
-+	/*	WPS OUI */
-+	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
-+	wpsielen += 4;
-+
-+	/*	WPS version */
-+	/*	Type: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
-+	wpsielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+	wpsielen += 2;
-+
-+	/*	Value: */
-+	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
-+
-+	/*	Config Method */
-+	/*	Type: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
-+	wpsielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
-+	wpsielen += 2;
-+
-+	/*	Value: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->tx_prov_disc_info.wps_config_method_request);
-+	wpsielen += 2;
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
-+
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe);
-+	pframe += wfdielen;
-+	pattrib->pktlen += wfdielen;
-+#endif
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return;
-+
-+}
-+
-+
-+u8 is_matched_in_profilelist(u8 *peermacaddr, struct profile_info *profileinfo)
-+{
-+	u8 i, match_result = 0;
-+
-+	RTW_INFO("[%s] peermac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__,
-+		peermacaddr[0], peermacaddr[1], peermacaddr[2], peermacaddr[3], peermacaddr[4], peermacaddr[5]);
-+
-+	for (i = 0; i < P2P_MAX_PERSISTENT_GROUP_NUM; i++, profileinfo++) {
-+		RTW_INFO("[%s] profileinfo_mac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__,
-+			profileinfo->peermac[0], profileinfo->peermac[1], profileinfo->peermac[2], profileinfo->peermac[3], profileinfo->peermac[4], profileinfo->peermac[5]);
-+		if (_rtw_memcmp(peermacaddr, profileinfo->peermac, ETH_ALEN)) {
-+			match_result = 1;
-+			RTW_INFO("[%s] Match!\n", __FUNCTION__);
-+			break;
-+		}
-+	}
-+
-+	return match_result ;
-+}
-+
-+void issue_probersp_p2p(_adapter *padapter, unsigned char *da)
-+{
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	unsigned char					*mac;
-+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	/* WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network); */
-+	u16					beacon_interval = 100;
-+	u16					capInfo = 0;
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	u8					wpsie[255] = { 0x00 };
-+	u32					wpsielen = 0, p2pielen = 0;
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+	/* RTW_INFO("%s\n", __FUNCTION__); */
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	if (IS_CCK_RATE(pattrib->rate)) {
-+		/* force OFDM 6M rate */
-+		pattrib->rate = MGN_6M;
-+		pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);
-+	}
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	mac = adapter_mac_addr(padapter);
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
-+
-+	/*	Use the device address for BSSID field.	 */
-+	_rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(fctrl, WIFI_PROBERSP);
-+
-+	pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = pattrib->hdrlen;
-+	pframe += pattrib->hdrlen;
-+
-+	/* timestamp will be inserted by hardware */
-+	pframe += 8;
-+	pattrib->pktlen += 8;
-+
-+	/* beacon interval: 2 bytes */
-+	_rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2);
-+	pframe += 2;
-+	pattrib->pktlen += 2;
-+
-+	/*	capability info: 2 bytes */
-+	/*	ESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) */
-+	capInfo |= cap_ShortPremble;
-+	capInfo |= cap_ShortSlot;
-+
-+	_rtw_memcpy(pframe, (unsigned char *) &capInfo, 2);
-+	pframe += 2;
-+	pattrib->pktlen += 2;
-+
-+
-+	/* SSID */
-+	pframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pattrib->pktlen);
-+
-+	/* supported rates... */
-+	/*	Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) */
-+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen);
-+
-+	/* DS parameter set */
-+	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pattrib->pktlen);
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
-+		if (pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL) {
-+			/* WPS IE */
-+			_rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);
-+			pattrib->pktlen += pmlmepriv->wps_probe_resp_ie_len;
-+			pframe += pmlmepriv->wps_probe_resp_ie_len;
-+
-+			/* P2P IE */
-+			_rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len);
-+			pattrib->pktlen += pmlmepriv->p2p_probe_resp_ie_len;
-+			pframe += pmlmepriv->p2p_probe_resp_ie_len;
-+		}
-+	} else
-+#endif /* CONFIG_IOCTL_CFG80211		 */
-+	{
-+
-+		/*	Todo: WPS IE */
-+		/*	Noted by Albert 20100907 */
-+		/*	According to the WPS specification, all the WPS attribute is presented by Big Endian. */
-+
-+		wpsielen = 0;
-+		/*	WPS OUI */
-+		*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
-+		wpsielen += 4;
-+
-+		/*	WPS version */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
-+
-+		/*	WiFi Simple Config State */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SIMPLE_CONF_STATE);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		wpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG;	/*	Not Configured. */
-+
-+		/*	Response Type */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_RESP_TYPE);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		wpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X;
-+
-+		/*	UUID-E */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		if (pwdinfo->external_uuid == 0) {
-+			_rtw_memset(wpsie + wpsielen, 0x0, 16);
-+			_rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN);
-+		} else
-+			_rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10);
-+		wpsielen += 0x10;
-+
-+		/*	Manufacturer */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MANUFACTURER);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0007);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		_rtw_memcpy(wpsie + wpsielen, "Realtek", 7);
-+		wpsielen += 7;
-+
-+		/*	Model Name */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NAME);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0006);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		_rtw_memcpy(wpsie + wpsielen, "8192CU", 6);
-+		wpsielen += 6;
-+
-+		/*	Model Number */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NUMBER);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		wpsie[wpsielen++] = 0x31;		/*	character 1 */
-+
-+		/*	Serial Number */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SERIAL_NUMBER);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(ETH_ALEN);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		_rtw_memcpy(wpsie + wpsielen, "123456" , ETH_ALEN);
-+		wpsielen += ETH_ALEN;
-+
-+		/*	Primary Device Type */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		/*	Category ID */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
-+		wpsielen += 2;
-+
-+		/*	OUI */
-+		*(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI);
-+		wpsielen += 4;
-+
-+		/*	Sub Category ID */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
-+		wpsielen += 2;
-+
-+		/*	Device Name */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		_rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len);
-+		wpsielen += pwdinfo->device_name_len;
-+
-+		/*	Config Method */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
-+		wpsielen += 2;
-+
-+
-+		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
-+
-+
-+		p2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe);
-+		pframe += p2pielen;
-+		pattrib->pktlen += p2pielen;
-+	}
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = rtw_append_probe_resp_wfd_ie(padapter, pframe);
-+	pframe += wfdielen;
-+	pattrib->pktlen += wfdielen;
-+#endif
-+
-+/* Vendor Specific IE */
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+	pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_P2P_PROBERESP_VENDOR_IE_BIT);
-+#endif
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return;
-+
-+}
-+
-+int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack)
-+{
-+	int ret = _FAIL;
-+	struct xmit_frame		*pmgntframe;
-+	struct pkt_attrib		*pattrib;
-+	unsigned char			*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short		*fctrl;
-+	unsigned char			*mac;
-+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	u8					wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };
-+	u16					wpsielen = 0, p2pielen = 0;
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	if (IS_CCK_RATE(pattrib->rate)) {
-+		/* force OFDM 6M rate */
-+		pattrib->rate = MGN_6M;
-+		pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);
-+	}
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	mac = adapter_mac_addr(padapter);
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	if (da) {
-+		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
-+	} else {
-+		if ((pwdinfo->p2p_info.scan_op_ch_only) || (pwdinfo->rx_invitereq_info.scan_op_ch_only)) {
-+			/*	This two flags will be set when this is only the P2P client mode. */
-+			_rtw_memcpy(pwlanhdr->addr1, pwdinfo->p2p_peer_interface_addr, ETH_ALEN);
-+			_rtw_memcpy(pwlanhdr->addr3, pwdinfo->p2p_peer_interface_addr, ETH_ALEN);
-+		} else {
-+			/*	broadcast probe request frame */
-+			_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
-+			_rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);
-+		}
-+	}
-+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_PROBEREQ);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ))
-+		pframe = rtw_set_ie(pframe, _SSID_IE_, pwdinfo->tx_prov_disc_info.ssid.SsidLength, pwdinfo->tx_prov_disc_info.ssid.Ssid, &(pattrib->pktlen));
-+	else
-+		pframe = rtw_set_ie(pframe, _SSID_IE_, P2P_WILDCARD_SSID_LEN, pwdinfo->p2p_wildcard_ssid, &(pattrib->pktlen));
-+	/*	Use the OFDM rate in the P2P probe request frame. ( 6(B), 9(B), 12(B), 24(B), 36, 48, 54 ) */
-+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen);
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
-+		if (pmlmepriv->wps_probe_req_ie != NULL && pmlmepriv->p2p_probe_req_ie != NULL) {
-+			/* WPS IE */
-+			_rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len);
-+			pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len;
-+			pframe += pmlmepriv->wps_probe_req_ie_len;
-+
-+			/* P2P IE */
-+			_rtw_memcpy(pframe, pmlmepriv->p2p_probe_req_ie, pmlmepriv->p2p_probe_req_ie_len);
-+			pattrib->pktlen += pmlmepriv->p2p_probe_req_ie_len;
-+			pframe += pmlmepriv->p2p_probe_req_ie_len;
-+		}
-+	} else
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+	{
-+
-+		/*	WPS IE */
-+		/*	Noted by Albert 20110221 */
-+		/*	According to the WPS specification, all the WPS attribute is presented by Big Endian. */
-+
-+		wpsielen = 0;
-+		/*	WPS OUI */
-+		*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
-+		wpsielen += 4;
-+
-+		/*	WPS version */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
-+
-+		if (pmlmepriv->wps_probe_req_ie == NULL) {
-+			/*	UUID-E */
-+			/*	Type: */
-+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E);
-+			wpsielen += 2;
-+
-+			/*	Length: */
-+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010);
-+			wpsielen += 2;
-+
-+			/*	Value: */
-+			if (pwdinfo->external_uuid == 0) {
-+				_rtw_memset(wpsie + wpsielen, 0x0, 16);
-+				_rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN);
-+			} else
-+				_rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10);
-+			wpsielen += 0x10;
-+
-+			/*	Config Method */
-+			/*	Type: */
-+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
-+			wpsielen += 2;
-+
-+			/*	Length: */
-+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
-+			wpsielen += 2;
-+
-+			/*	Value: */
-+			*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
-+			wpsielen += 2;
-+		}
-+
-+		/*	Device Name */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		_rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len);
-+		wpsielen += pwdinfo->device_name_len;
-+
-+		/*	Primary Device Type */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		/*	Category ID */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_RTK_WIDI);
-+		wpsielen += 2;
-+
-+		/*	OUI */
-+		*(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI);
-+		wpsielen += 4;
-+
-+		/*	Sub Category ID */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_RTK_DMP);
-+		wpsielen += 2;
-+
-+		/*	Device Password ID */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);	/*	Registrar-specified */
-+		wpsielen += 2;
-+
-+		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
-+
-+		/*	P2P OUI */
-+		p2pielen = 0;
-+		p2pie[p2pielen++] = 0x50;
-+		p2pie[p2pielen++] = 0x6F;
-+		p2pie[p2pielen++] = 0x9A;
-+		p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+		/*	Commented by Albert 20110221 */
-+		/*	According to the P2P Specification, the probe request frame should contain 5 P2P attributes */
-+		/*	1. P2P Capability */
-+		/*	2. P2P Device ID if this probe request wants to find the specific P2P device */
-+		/*	3. Listen Channel */
-+		/*	4. Extended Listen Timing */
-+		/*	5. Operating Channel if this WiFi is working as the group owner now */
-+
-+		/*	P2P Capability */
-+		/*	Type: */
-+		p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
-+
-+		/*	Length: */
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
-+		p2pielen += 2;
-+
-+		/*	Value: */
-+		/*	Device Capability Bitmap, 1 byte */
-+		p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
-+
-+		/*	Group Capability Bitmap, 1 byte */
-+		if (pwdinfo->persistent_supported)
-+			p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
-+		else
-+			p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;
-+
-+		/*	Listen Channel */
-+		/*	Type: */
-+		p2pie[p2pielen++] = P2P_ATTR_LISTEN_CH;
-+
-+		/*	Length: */
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
-+		p2pielen += 2;
-+
-+		/*	Value: */
-+		/*	Country String */
-+		p2pie[p2pielen++] = 'X';
-+		p2pie[p2pielen++] = 'X';
-+
-+		/*	The third byte should be set to 0x04. */
-+		/*	Described in the "Operating Channel Attribute" section. */
-+		p2pie[p2pielen++] = 0x04;
-+
-+		/*	Operating Class */
-+		p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
-+
-+		/*	Channel Number */
-+		p2pie[p2pielen++] = pwdinfo->listen_channel;	/*	listen channel */
-+
-+
-+		/*	Extended Listen Timing */
-+		/*	Type: */
-+		p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;
-+
-+		/*	Length: */
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004);
-+		p2pielen += 2;
-+
-+		/*	Value: */
-+		/*	Availability Period */
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
-+		p2pielen += 2;
-+
-+		/*	Availability Interval */
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
-+		p2pielen += 2;
-+
-+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+			/*	Operating Channel (if this WiFi is working as the group owner now) */
-+			/*	Type: */
-+			p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
-+
-+			/*	Length: */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
-+			p2pielen += 2;
-+
-+			/*	Value: */
-+			/*	Country String */
-+			p2pie[p2pielen++] = 'X';
-+			p2pie[p2pielen++] = 'X';
-+
-+			/*	The third byte should be set to 0x04. */
-+			/*	Described in the "Operating Channel Attribute" section. */
-+			p2pie[p2pielen++] = 0x04;
-+
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
-+
-+			/*	Channel Number */
-+			p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
-+
-+		}
-+
-+		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
-+
-+	}
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = rtw_append_probe_req_wfd_ie(padapter, pframe);
-+	pframe += wfdielen;
-+	pattrib->pktlen += wfdielen;
-+#endif
-+
-+/* Vendor Specific IE */
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+	pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_P2P_PROBEREQ_VENDOR_IE_BIT);
-+#endif
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+
-+	if (wait_ack)
-+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
-+	else {
-+		dump_mgntframe(padapter, pmgntframe);
-+		ret = _SUCCESS;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+inline void issue_probereq_p2p(_adapter *adapter, u8 *da)
-+{
-+	_issue_probereq_p2p(adapter, da, _FALSE);
-+}
-+
-+/*
-+ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
-+ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
-+ * try_cnt means the maximal TX count to try
-+ */
-+int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms)
-+{
-+	int ret;
-+	int i = 0;
-+	systime start = rtw_get_current_time();
-+
-+	do {
-+		ret = _issue_probereq_p2p(adapter, da, wait_ms > 0 ? _TRUE : _FALSE);
-+
-+		i++;
-+
-+		if (RTW_CANNOT_RUN(adapter))
-+			break;
-+
-+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
-+			rtw_msleep_os(wait_ms);
-+
-+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
-+
-+	if (ret != _FAIL) {
-+		ret = _SUCCESS;
-+#ifndef DBG_XMIT_ACK
-+		goto exit;
-+#endif
-+	}
-+
-+	if (try_cnt && wait_ms) {
-+		if (da)
-+			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
-+				FUNC_ADPT_ARG(adapter), MAC_ARG(da), rtw_get_oper_ch(adapter),
-+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+		else
-+			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
-+				FUNC_ADPT_ARG(adapter), rtw_get_oper_ch(adapter),
-+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+	}
-+exit:
-+	return ret;
-+}
-+
-+#endif /* CONFIG_P2P */
-+
-+s32 rtw_action_public_decache(union recv_frame *rframe, u8 token_offset)
-+{
-+	_adapter *adapter = rframe->u.hdr.adapter;
-+	struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv);
-+	u8 *frame = rframe->u.hdr.rx_data;
-+	u16 seq_ctrl = ((rframe->u.hdr.attrib.seq_num & 0xffff) << 4) | (rframe->u.hdr.attrib.frag_num & 0xf);
-+	u8 token = *(rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + token_offset);
-+
-+	if (GetRetry(frame)) {
-+		if ((seq_ctrl == mlmeext->action_public_rxseq)
-+		    && (token == mlmeext->action_public_dialog_token)
-+		   ) {
-+			RTW_INFO(FUNC_ADPT_FMT" seq_ctrl=0x%x, rxseq=0x%x, token:%d\n",
-+				FUNC_ADPT_ARG(adapter), seq_ctrl, mlmeext->action_public_rxseq, token);
-+			return _FAIL;
-+		}
-+	}
-+
-+	/* TODO: per sta seq & token */
-+	mlmeext->action_public_rxseq = seq_ctrl;
-+	mlmeext->action_public_dialog_token = token;
-+
-+	return _SUCCESS;
-+}
-+
-+unsigned int on_action_public_p2p(union recv_frame *precv_frame)
-+{
-+	_adapter *padapter = precv_frame->u.hdr.adapter;
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	uint len = precv_frame->u.hdr.len;
-+	u8 *frame_body;
-+#ifdef CONFIG_P2P
-+	u8 *p2p_ie;
-+	u32	p2p_ielen;
-+	struct	wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	u8	result = P2P_STATUS_SUCCESS;
-+	u8	empty_addr[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
-+	u8 *merged_p2pie = NULL;
-+	u32 merged_p2p_ielen = 0;
-+#ifdef CONFIG_CONCURRENT_MODE
-+	struct roch_info *prochinfo = &padapter->rochinfo;
-+#endif
-+#endif /* CONFIG_P2P */
-+
-+	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
-+
-+#ifdef CONFIG_P2P
-+	_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211)
-+		rtw_cfg80211_rx_p2p_action_public(padapter, precv_frame);
-+	else
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+	{
-+		/*	Do nothing if the driver doesn't enable the P2P function. */
-+		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE))
-+			return _SUCCESS;
-+
-+		len -= sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+		switch (frame_body[6]) { /* OUI Subtype */
-+		case P2P_GO_NEGO_REQ: {
-+			RTW_INFO("[%s] Got GO Nego Req Frame\n", __FUNCTION__);
-+			_rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info));
-+
-+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ))
-+				rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
-+
-+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) {
-+				/*	Commented by Albert 20110526 */
-+				/*	In this case, this means the previous nego fail doesn't be reset yet. */
-+				_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
-+				/*	Restore the previous p2p state */
-+				rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
-+				RTW_INFO("[%s] Restore the previous p2p state to %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo));
-+			}
-+#ifdef CONFIG_CONCURRENT_MODE
-+			if (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE))
-+				_cancel_timer_ex(&prochinfo->ap_roch_ch_switch_timer);
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+			/*	Commented by Kurt 20110902 */
-+			/* Add if statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. */
-+			if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING))
-+				rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
-+
-+			/*	Commented by Kurt 20120113 */
-+			/*	Get peer_dev_addr here if peer doesn't issue prov_disc frame. */
-+			if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.peerDevAddr, empty_addr, ETH_ALEN))
-+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN);
-+
-+			result = process_p2p_group_negotation_req(pwdinfo, frame_body, len);
-+			issue_p2p_GO_response(padapter, get_addr2_ptr(pframe), frame_body, len, result);
-+
-+			/*	Commented by Albert 20110718 */
-+			/*	No matter negotiating or negotiation failure, the driver should set up the restore P2P state timer. */
-+#ifdef CONFIG_CONCURRENT_MODE
-+			/*	Commented by Albert 20120107 */
-+			_set_timer(&pwdinfo->restore_p2p_state_timer, 3000);
-+#else /* CONFIG_CONCURRENT_MODE */
-+			_set_timer(&pwdinfo->restore_p2p_state_timer, 5000);
-+#endif /* CONFIG_CONCURRENT_MODE */
-+			break;
-+		}
-+		case P2P_GO_NEGO_RESP: {
-+			RTW_INFO("[%s] Got GO Nego Resp Frame\n", __FUNCTION__);
-+
-+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) {
-+				/*	Commented by Albert 20110425 */
-+				/*	The restore timer is enabled when issuing the nego request frame of rtw_p2p_connect function. */
-+				_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
-+				pwdinfo->nego_req_info.benable = _FALSE;
-+				result = process_p2p_group_negotation_resp(pwdinfo, frame_body, len);
-+				issue_p2p_GO_confirm(pwdinfo->padapter, get_addr2_ptr(pframe), result);
-+				if (P2P_STATUS_SUCCESS == result) {
-+					if (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) {
-+						pwdinfo->p2p_info.operation_ch[0] = pwdinfo->peer_operating_ch;
-+#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
-+						pwdinfo->p2p_info.operation_ch[1] = 1;	/* Check whether GO is operating in channel 1; */
-+						pwdinfo->p2p_info.operation_ch[2] = 6;	/* Check whether GO is operating in channel 6; */
-+						pwdinfo->p2p_info.operation_ch[3] = 11;	/* Check whether GO is operating in channel 11; */
-+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
-+						pwdinfo->p2p_info.scan_op_ch_only = 1;
-+						_set_timer(&pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH);
-+					}
-+				}
-+
-+				/*	Reset the dialog token for group negotiation frames. */
-+				pwdinfo->negotiation_dialog_token = 1;
-+
-+				if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL))
-+					_set_timer(&pwdinfo->restore_p2p_state_timer, 5000);
-+			} else
-+				RTW_INFO("[%s] Skipped GO Nego Resp Frame (p2p_state != P2P_STATE_GONEGO_ING)\n", __FUNCTION__);
-+
-+			break;
-+		}
-+		case P2P_GO_NEGO_CONF: {
-+			RTW_INFO("[%s] Got GO Nego Confirm Frame\n", __FUNCTION__);
-+			result = process_p2p_group_negotation_confirm(pwdinfo, frame_body, len);
-+			if (P2P_STATUS_SUCCESS == result) {
-+				if (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) {
-+					pwdinfo->p2p_info.operation_ch[0] = pwdinfo->peer_operating_ch;
-+#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
-+					pwdinfo->p2p_info.operation_ch[1] = 1;	/* Check whether GO is operating in channel 1; */
-+					pwdinfo->p2p_info.operation_ch[2] = 6;	/* Check whether GO is operating in channel 6; */
-+					pwdinfo->p2p_info.operation_ch[3] = 11;	/* Check whether GO is operating in channel 11; */
-+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
-+					pwdinfo->p2p_info.scan_op_ch_only = 1;
-+					_set_timer(&pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH);
-+				}
-+			}
-+			break;
-+		}
-+		case P2P_INVIT_REQ: {
-+			/*	Added by Albert 2010/10/05 */
-+			/*	Received the P2P Invite Request frame. */
-+
-+			RTW_INFO("[%s] Got invite request frame!\n", __FUNCTION__);
-+			p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);
-+			if (p2p_ie) {
-+				/*	Parse the necessary information from the P2P Invitation Request frame. */
-+				/*	For example: The MAC address of sending this P2P Invitation Request frame. */
-+				u32	attr_contentlen = 0;
-+				u8	status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
-+				struct group_id_info group_id;
-+				u8	invitation_flag = 0;
-+
-+				merged_p2p_ielen = rtw_get_p2p_merged_ies_len(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_);
-+
-+				merged_p2pie = rtw_zmalloc(merged_p2p_ielen + 2);	/* 2 is for EID and Length */
-+				if (merged_p2pie == NULL) {
-+					RTW_INFO("[%s] Malloc p2p ie fail\n", __FUNCTION__);
-+					goto exit;
-+				}
-+				_rtw_memset(merged_p2pie, 0x00, merged_p2p_ielen);
-+
-+				merged_p2p_ielen = rtw_p2p_merge_ies(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, merged_p2pie);
-+
-+				rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_INVITATION_FLAGS, &invitation_flag, &attr_contentlen);
-+				if (attr_contentlen) {
-+
-+					rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_BSSID, pwdinfo->p2p_peer_interface_addr, &attr_contentlen);
-+					/*	Commented by Albert 20120510 */
-+					/*	Copy to the pwdinfo->p2p_peer_interface_addr. */
-+					/*	So that the WFD UI ( or Sigma ) can get the peer interface address by using the following command. */
-+					/*	#> iwpriv wlan0 p2p_get peer_ifa */
-+					/*	After having the peer interface address, the sigma can find the correct conf file for wpa_supplicant. */
-+
-+					if (attr_contentlen) {
-+						RTW_INFO("[%s] GO's BSSID = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__,
-+							pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1],
-+							pwdinfo->p2p_peer_interface_addr[2], pwdinfo->p2p_peer_interface_addr[3],
-+							pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
-+					}
-+
-+					if (invitation_flag & P2P_INVITATION_FLAGS_PERSISTENT) {
-+						/*	Re-invoke the persistent group. */
-+
-+						_rtw_memset(&group_id, 0x00, sizeof(struct group_id_info));
-+						rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, (u8 *) &group_id, &attr_contentlen);
-+						if (attr_contentlen) {
-+							if (_rtw_memcmp(group_id.go_device_addr, adapter_mac_addr(padapter), ETH_ALEN)) {
-+								/*	The p2p device sending this p2p invitation request wants this Wi-Fi device to be the persistent GO. */
-+								rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_GO);
-+								rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
-+								status_code = P2P_STATUS_SUCCESS;
-+							} else {
-+								/*	The p2p device sending this p2p invitation request wants to be the persistent GO. */
-+								if (is_matched_in_profilelist(pwdinfo->p2p_peer_interface_addr, &pwdinfo->profileinfo[0])) {
-+									u8 operatingch_info[5] = { 0x00 };
-+									if (rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info,
-+										&attr_contentlen)) {
-+										if (rtw_chset_search_ch(adapter_to_chset(padapter), (u32)operatingch_info[4]) >= 0) {
-+											/*	The operating channel is acceptable for this device. */
-+											pwdinfo->rx_invitereq_info.operation_ch[0] = operatingch_info[4];
-+#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
-+											pwdinfo->rx_invitereq_info.operation_ch[1] = 1;		/* Check whether GO is operating in channel 1; */
-+											pwdinfo->rx_invitereq_info.operation_ch[2] = 6;		/* Check whether GO is operating in channel 6; */
-+											pwdinfo->rx_invitereq_info.operation_ch[3] = 11;		/* Check whether GO is operating in channel 11; */
-+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
-+											pwdinfo->rx_invitereq_info.scan_op_ch_only = 1;
-+											_set_timer(&pwdinfo->reset_ch_sitesurvey, P2P_RESET_SCAN_CH);
-+											rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH);
-+											rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
-+											status_code = P2P_STATUS_SUCCESS;
-+										} else {
-+											/*	The operating channel isn't supported by this device. */
-+											rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH);
-+											rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
-+											status_code = P2P_STATUS_FAIL_NO_COMMON_CH;
-+											_set_timer(&pwdinfo->restore_p2p_state_timer, 3000);
-+										}
-+									} else {
-+										/*	Commented by Albert 20121130 */
-+										/*	Intel will use the different P2P IE to store the operating channel information */
-+										/*	Workaround for Intel WiDi 3.5 */
-+										rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH);
-+										rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
-+										status_code = P2P_STATUS_SUCCESS;
-+									}
-+								} else {
-+									rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH);
-+									status_code = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP;
-+								}
-+							}
-+						} else {
-+							RTW_INFO("[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__);
-+							status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
-+						}
-+					} else {
-+						/*	Received the invitation to join a P2P group. */
-+
-+						_rtw_memset(&group_id, 0x00, sizeof(struct group_id_info));
-+						rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, (u8 *) &group_id, &attr_contentlen);
-+						if (attr_contentlen) {
-+							if (_rtw_memcmp(group_id.go_device_addr, adapter_mac_addr(padapter), ETH_ALEN)) {
-+								/*	In this case, the GO can't be myself. */
-+								rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH);
-+								status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
-+							} else {
-+								/*	The p2p device sending this p2p invitation request wants to join an existing P2P group */
-+								/*	Commented by Albert 2012/06/28 */
-+								/*	In this case, this Wi-Fi device should use the iwpriv command to get the peer device address. */
-+								/*	The peer device address should be the destination address for the provisioning discovery request. */
-+								/*	Then, this Wi-Fi device should use the iwpriv command to get the peer interface address. */
-+								/*	The peer interface address should be the address for WPS mac address */
-+								_rtw_memcpy(pwdinfo->p2p_peer_device_addr, group_id.go_device_addr , ETH_ALEN);
-+								rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
-+								rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_JOIN);
-+								status_code = P2P_STATUS_SUCCESS;
-+							}
-+						} else {
-+							RTW_INFO("[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__);
-+							status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
-+						}
-+					}
-+				} else {
-+					RTW_INFO("[%s] P2P Invitation Flags Attribute NOT FOUND!\n", __FUNCTION__);
-+					status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
-+				}
-+
-+				RTW_INFO("[%s] status_code = %d\n", __FUNCTION__, status_code);
-+
-+				pwdinfo->inviteresp_info.token = frame_body[7];
-+				issue_p2p_invitation_response(padapter, get_addr2_ptr(pframe), pwdinfo->inviteresp_info.token, status_code);
-+				_set_timer(&pwdinfo->restore_p2p_state_timer, 3000);
-+			}
-+			break;
-+		}
-+		case P2P_INVIT_RESP: {
-+			u8	attr_content = 0x00;
-+			u32	attr_contentlen = 0;
-+
-+			RTW_INFO("[%s] Got invite response frame!\n", __FUNCTION__);
-+			_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
-+			p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);
-+			if (p2p_ie) {
-+				rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);
-+
-+				if (attr_contentlen == 1) {
-+					RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content);
-+					pwdinfo->invitereq_info.benable = _FALSE;
-+
-+					if (attr_content == P2P_STATUS_SUCCESS) {
-+						if (_rtw_memcmp(pwdinfo->invitereq_info.go_bssid, adapter_mac_addr(padapter), ETH_ALEN))
-+							rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
-+						else
-+							rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
-+
-+						rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_OK);
-+					} else {
-+						rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
-+						rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL);
-+					}
-+				} else {
-+					rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
-+					rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL);
-+				}
-+			} else {
-+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
-+				rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL);
-+			}
-+
-+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL))
-+				_set_timer(&pwdinfo->restore_p2p_state_timer, 5000);
-+			break;
-+		}
-+		case P2P_DEVDISC_REQ:
-+
-+			process_p2p_devdisc_req(pwdinfo, pframe, len);
-+
-+			break;
-+
-+		case P2P_DEVDISC_RESP:
-+
-+			process_p2p_devdisc_resp(pwdinfo, pframe, len);
-+
-+			break;
-+
-+		case P2P_PROVISION_DISC_REQ:
-+			RTW_INFO("[%s] Got Provisioning Discovery Request Frame\n", __FUNCTION__);
-+			process_p2p_provdisc_req(pwdinfo, pframe, len);
-+			_rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN);
-+
-+			/* 20110902 Kurt */
-+			/* Add the following statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. */
-+			if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ))
-+				rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
-+
-+			rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ);
-+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);
-+			break;
-+
-+		case P2P_PROVISION_DISC_RESP:
-+			/*	Commented by Albert 20110707 */
-+			/*	Should we check the pwdinfo->tx_prov_disc_info.bsent flag here?? */
-+			RTW_INFO("[%s] Got Provisioning Discovery Response Frame\n", __FUNCTION__);
-+			/*	Commented by Albert 20110426 */
-+			/*	The restore timer is enabled when issuing the provisioing request frame in rtw_p2p_prov_disc function. */
-+			_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
-+			rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP);
-+			process_p2p_provdisc_resp(pwdinfo, pframe);
-+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);
-+			break;
-+
-+		}
-+	}
-+
-+
-+exit:
-+
-+	if (merged_p2pie)
-+		rtw_mfree(merged_p2pie, merged_p2p_ielen + 2);
-+#endif /* CONFIG_P2P */
-+	return _SUCCESS;
-+}
-+
-+unsigned int on_action_public_vendor(union recv_frame *precv_frame)
-+{
-+	unsigned int ret = _FAIL;
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	_adapter *adapter = precv_frame->u.hdr.adapter;
-+	int cnt = 0;
-+	char msg[64];
-+
-+	if (_rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE) {
-+		if (rtw_action_public_decache(precv_frame, 7) == _FAIL)
-+			goto exit;
-+
-+		if (!hal_chk_wl_func(precv_frame->u.hdr.adapter, WL_FUNC_MIRACAST))
-+			rtw_rframe_del_wfd_ie(precv_frame, 8);
-+
-+		ret = on_action_public_p2p(precv_frame);
-+	} else if (_rtw_memcmp(frame_body + 2, DPP_OUI, 4) == _TRUE) {
-+		u8 dpp_type = frame_body[7];
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+		cnt += sprintf((msg + cnt), "DPP(type:%u)", dpp_type);
-+		rtw_cfg80211_rx_action(adapter, precv_frame, msg);
-+#endif
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+unsigned int on_action_public_default(union recv_frame *precv_frame, u8 action)
-+{
-+	unsigned int ret = _FAIL;
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	u8 token;
-+	_adapter *adapter = precv_frame->u.hdr.adapter;
-+	int cnt = 0;
-+	char msg[64];
-+
-+	token = frame_body[2];
-+
-+	if (rtw_action_public_decache(precv_frame, 2) == _FAIL)
-+		goto exit;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	cnt += sprintf((msg + cnt), "%s(token:%u)", action_public_str(action), token);
-+	rtw_cfg80211_rx_action(adapter, precv_frame, msg);
-+#endif
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	unsigned int ret = _FAIL;
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	uint frame_len = precv_frame->u.hdr.len;
-+	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	u8 category, action;
-+
-+	/* check RA matches or broadcast */
-+	if (!(_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN) ||
-+		is_broadcast_mac_addr(GetAddr1Ptr(pframe))))
-+		goto exit;
-+
-+	category = frame_body[0];
-+	if (category != RTW_WLAN_CATEGORY_PUBLIC)
-+		goto exit;
-+
-+	action = frame_body[1];
-+	switch (action) {
-+	case ACT_PUBLIC_BSSCOEXIST:
-+#ifdef CONFIG_80211N_HT
-+#ifdef CONFIG_AP_MODE
-+		/*20/40 BSS Coexistence Management frame is a Public Action frame*/
-+		if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
-+			rtw_process_public_act_bsscoex(padapter, pframe, frame_len);
-+#endif /*CONFIG_AP_MODE*/
-+#endif /*CONFIG_80211N_HT*/
-+		break;
-+	case ACT_PUBLIC_VENDOR:
-+		ret = on_action_public_vendor(precv_frame);
-+		break;
-+	default:
-+		ret = on_action_public_default(precv_frame, action);
-+		break;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+#ifdef CONFIG_RTW_80211R
-+	u32	ret = _FAIL;
-+	u32	frame_len = 0;
-+	u8	action_code = 0;
-+	u8	category = 0;
-+	u8	*pframe = NULL;
-+	u8	*pframe_body = NULL;
-+	u8 	tgt_addr[ETH_ALEN];
-+	u8	*pie = NULL;
-+	u32	ft_ie_len = 0;
-+	u32 status_code = 0;
-+	struct mlme_ext_priv *pmlmeext = NULL;
-+	struct mlme_ext_info *pmlmeinfo = NULL;
-+	struct mlme_priv *pmlmepriv = NULL;
-+	struct wlan_network *proam_target = NULL;
-+	struct ft_roam_info *pft_roam = NULL;
-+	_irqL  irqL;
-+
-+	pmlmeext = &(padapter->mlmeextpriv);
-+	pmlmeinfo = &(pmlmeext->mlmext_info);
-+	pmlmepriv = &(padapter->mlmepriv);
-+	pft_roam = &(pmlmepriv->ft_roam);
-+	pframe = precv_frame->u.hdr.rx_data;
-+	frame_len = precv_frame->u.hdr.len;
-+	pframe_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	category = pframe_body[0];
-+
-+	if (category != RTW_WLAN_CATEGORY_FT)
-+		goto exit;
-+
-+	action_code = pframe_body[1];
-+	switch (action_code) {
-+	case RTW_WLAN_ACTION_FT_RSP:
-+		RTW_INFO("FT: RTW_WLAN_ACTION_FT_RSP recv.\n");
-+		if (!_rtw_memcmp(adapter_mac_addr(padapter), &pframe_body[2], ETH_ALEN)) {
-+			RTW_ERR("FT: Unmatched STA MAC Address "MAC_FMT"\n", MAC_ARG(&pframe_body[2]));
-+			goto exit;
-+		}
-+
-+		status_code = le16_to_cpu(*(u16 *)((SIZE_PTR)pframe +  sizeof(struct rtw_ieee80211_hdr_3addr) + 14));
-+		if (status_code != 0) {
-+			RTW_ERR("FT: WLAN ACTION FT RESPONSE fail, status: %d\n", status_code);
-+			goto exit;
-+		}
-+
-+		_rtw_memcpy(tgt_addr, &pframe_body[8], ETH_ALEN);
-+		if (is_zero_mac_addr(tgt_addr) || is_broadcast_mac_addr(tgt_addr)) {
-+			RTW_ERR("FT: Invalid Target MAC Address "MAC_FMT"\n", MAC_ARG(tgt_addr));
-+			goto exit;
-+		}
-+
-+		pie = rtw_get_ie(pframe_body, _MDIE_, &ft_ie_len, frame_len);
-+		if (pie) {
-+			if (!_rtw_memcmp(&pft_roam->mdid, pie+2, 2)) {
-+				RTW_ERR("FT: Invalid MDID\n");
-+				goto exit;
-+			}
-+		}
-+
-+		rtw_ft_set_status(padapter, RTW_FT_REQUESTED_STA);
-+		_cancel_timer_ex(&pmlmeext->ft_link_timer);
-+
-+		/*Disconnect current AP*/
-+		receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress, WLAN_REASON_ACTIVE_ROAM, _FALSE);
-+
-+		pft_roam->ft_action_len = frame_len;
-+		_rtw_memcpy(pft_roam->ft_action, pframe, rtw_min(frame_len, RTW_FT_MAX_IE_SZ));
-+		ret = _SUCCESS;
-+		break;
-+	case RTW_WLAN_ACTION_FT_REQ:
-+	case RTW_WLAN_ACTION_FT_CONF:
-+	case RTW_WLAN_ACTION_FT_ACK:
-+	default:
-+		RTW_ERR("FT: Unsupported FT Action!\n");
-+		break;
-+	}
-+
-+exit:
-+	return ret;
-+#else
-+	return _SUCCESS;
-+#endif
-+}
-+
-+unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	u8 category, action;
-+
-+	/* check RA matches or not */
-+	if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))
-+		goto exit;
-+
-+	category = frame_body[0];
-+	if (category != RTW_WLAN_CATEGORY_HT)
-+		goto exit;
-+
-+	action = frame_body[1];
-+	switch (action) {
-+	case RTW_WLAN_ACTION_HT_SM_PS:
-+#ifdef CONFIG_80211N_HT
-+#ifdef CONFIG_AP_MODE
-+		if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
-+			rtw_process_ht_action_smps(padapter, get_addr2_ptr(pframe), frame_body[2]);
-+#endif /*CONFIG_AP_MODE*/
-+#endif /*CONFIG_80211N_HT*/
-+		break;
-+	case RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING:
-+#ifdef CONFIG_BEAMFORMING
-+		/*RTW_INFO("RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING\n");*/
-+		rtw_beamforming_get_report_frame(padapter, precv_frame);
-+#endif /*CONFIG_BEAMFORMING*/
-+		break;
-+	default:
-+		break;
-+	}
-+
-+exit:
-+
-+	return _SUCCESS;
-+}
-+
-+#ifdef CONFIG_IEEE80211W
-+unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct sta_info		*psta;
-+	struct sta_priv		*pstapriv = &padapter->stapriv;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	u16 tid;
-+	/* Baron */
-+
-+	RTW_INFO("OnAction_sa_query\n");
-+
-+	switch (pframe[WLAN_HDR_A3_LEN + 1]) {
-+	case 0: /* SA Query req */
-+		_rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN + 2], sizeof(u16));
-+		RTW_INFO("OnAction_sa_query request,action=%d, tid=%04x, pframe=%02x-%02x\n"
-+			, pframe[WLAN_HDR_A3_LEN + 1], tid, pframe[WLAN_HDR_A3_LEN + 2], pframe[WLAN_HDR_A3_LEN + 3]);
-+		issue_action_SA_Query(padapter, get_addr2_ptr(pframe), 1, tid, IEEE80211W_RIGHT_KEY);
-+		break;
-+
-+	case 1: /* SA Query rsp */
-+		psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
-+		if (psta != NULL)
-+			_cancel_timer_ex(&psta->dot11w_expire_timer);
-+
-+		_rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN + 2], sizeof(u16));
-+		RTW_INFO("OnAction_sa_query response,action=%d, tid=%04x, cancel timer\n", pframe[WLAN_HDR_A3_LEN + 1], tid);
-+		break;
-+	default:
-+		break;
-+	}
-+	if (0) {
-+		int pp;
-+		printk("pattrib->pktlen = %d =>", pattrib->pkt_len);
-+		for (pp = 0; pp < pattrib->pkt_len; pp++)
-+			printk(" %02x ", pframe[pp]);
-+		printk("\n");
-+	}
-+
-+	return _SUCCESS;
-+}
-+#endif /* CONFIG_IEEE80211W */
-+
-+unsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+#ifdef CONFIG_RTW_80211K
-+	return rm_on_action(padapter, precv_frame);
-+#else
-+	return _SUCCESS;
-+#endif  /* CONFIG_RTW_80211K */
-+}
-+
-+unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	return _SUCCESS;
-+}
-+
-+unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+#ifdef CONFIG_80211AC_VHT
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	struct rtw_ieee80211_hdr_3addr *whdr = (struct rtw_ieee80211_hdr_3addr *)pframe;
-+	u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	u8 category, action;
-+	struct sta_info *psta = NULL;
-+
-+	/* check RA matches or not */
-+	if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))
-+		goto exit;
-+
-+	category = frame_body[0];
-+	if (category != RTW_WLAN_CATEGORY_VHT)
-+		goto exit;
-+
-+	action = frame_body[1];
-+	switch (action) {
-+	case RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING:
-+#ifdef CONFIG_BEAMFORMING
-+		/*RTW_INFO("RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING\n");*/
-+		rtw_beamforming_get_report_frame(padapter, precv_frame);
-+#endif /*CONFIG_BEAMFORMING*/
-+		break;
-+	case RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION:
-+		/* CategoryCode(1) + ActionCode(1) + OpModeNotification(1) */
-+		/* RTW_INFO("RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION\n"); */
-+		psta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2);
-+		if (psta)
-+			rtw_process_vht_op_mode_notify(padapter, &frame_body[2], psta);
-+		break;
-+	case RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT:
-+#ifdef CONFIG_BEAMFORMING
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+		rtw_beamforming_get_vht_gid_mgnt_frame(padapter, precv_frame);
-+#endif /* RTW_BEAMFORMING_VERSION_2 */
-+#endif /* CONFIG_BEAMFORMING */
-+		break;
-+	default:
-+		break;
-+	}
-+
-+exit:
-+#endif /* CONFIG_80211AC_VHT */
-+
-+	return _SUCCESS;
-+}
-+
-+unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+#ifdef CONFIG_P2P
-+	u8 *frame_body;
-+	u8 category, OUI_Subtype, dialogToken = 0;
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	uint len = precv_frame->u.hdr.len;
-+	struct	wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+	/* check RA matches or not */
-+	if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN))
-+		return _SUCCESS;
-+
-+	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
-+
-+	category = frame_body[0];
-+	if (category != RTW_WLAN_CATEGORY_P2P)
-+		return _SUCCESS;
-+
-+	if (cpu_to_be32(*((u32 *)(frame_body + 1))) != P2POUI)
-+		return _SUCCESS;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (adapter_wdev_data(padapter)->p2p_enabled
-+		&& pwdinfo->driver_interface == DRIVER_CFG80211
-+	) {
-+		rtw_cfg80211_rx_action_p2p(padapter, precv_frame);
-+		return _SUCCESS;
-+	} else
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+	{
-+		len -= sizeof(struct rtw_ieee80211_hdr_3addr);
-+		OUI_Subtype = frame_body[5];
-+		dialogToken = frame_body[6];
-+
-+		switch (OUI_Subtype) {
-+		case P2P_NOTICE_OF_ABSENCE:
-+
-+			break;
-+
-+		case P2P_PRESENCE_REQUEST:
-+
-+			process_p2p_presence_req(pwdinfo, pframe, len);
-+
-+			break;
-+
-+		case P2P_PRESENCE_RESPONSE:
-+
-+			break;
-+
-+		case P2P_GO_DISC_REQUEST:
-+
-+			break;
-+
-+		default:
-+			break;
-+
-+		}
-+	}
-+#endif /* CONFIG_P2P */
-+
-+	return _SUCCESS;
-+
-+}
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+unsigned int OnAction_tbtx_token(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+#define TOKEN_REQ 0x00
-+#define TOKEN_REL 0x01
-+
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *psta;
-+	u32 xmit_time;
-+	u8 *src=NULL, *pframe = precv_frame->u.hdr.rx_data;
-+	u8 tbtx_action_code;
-+	u8 i, nr_send;
-+	uint tx_duration = 0;
-+
-+	if (padapter->tbtx_capability == _FALSE)
-+		goto exit;
-+
-+	tbtx_action_code = *(pframe + WLAN_HDR_A3_LEN + 1);
-+
-+
-+	switch (tbtx_action_code)
-+	{
-+		case TOKEN_REQ:
-+			// parse duration
-+			tx_duration = le32_to_cpu(*(uint *)(pframe + WLAN_HDR_A3_LEN + 2));
-+			padapter->tbtx_duration = tx_duration/1000; // Mirocsecond to Millisecond
-+			ATOMIC_SET(&padapter->tbtx_tx_pause, _FALSE);
-+			rtw_tx_control_cmd(padapter);
-+			_set_timer(&pmlmeext->tbtx_xmit_timer, padapter->tbtx_duration);
-+			ATOMIC_SET(&padapter->tbtx_remove_tx_pause, _FALSE);
-+#if defined(CONFIG_SDIO_HCI) && !defined(CONFIG_SDIO_TX_TASKLET)
-+			_rtw_up_sema(&pxmitpriv->SdioXmitSema);
-+#else
-+			tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
-+#endif
-+			break;
-+#ifdef CONFIG_AP_MODE
-+		case TOKEN_REL:
-+			src = get_addr2_ptr(pframe);
-+			if (!src)
-+				goto exit;
-+			psta = rtw_get_stainfo(&padapter->stapriv, src);
-+			if (!psta)
-+				goto exit;
-+
-+			if (ATOMIC_READ(&pstapriv->nr_token_keeper) < 1)
-+				goto exit;
-+
-+			for (i=0; i< NR_MAXSTA_INSLOT; i++) {
-+				if (pstapriv->token_holder[i] == psta) {
-+					pstapriv->token_holder[i] = NULL;
-+					//RTW_INFO("macaddr1:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
-+					ATOMIC_DEC(&pstapriv->nr_token_keeper);
-+					break;
-+				}
-+			}
-+
-+			if (ATOMIC_READ(&pstapriv->nr_token_keeper) == 0)
-+				_set_timer(&pmlmeext->tbtx_token_dispatch_timer, 1);
-+
-+			break;
-+#endif
-+		default:
-+			RTW_INFO("Undefined Action Code\n");
-+			goto exit;
-+			break;
-+	}
-+
-+exit:
-+	return _SUCCESS;
-+}
-+
-+void rtw_issue_action_token_rel(_adapter *padapter)
-+{
-+
-+	// Todo: 
-+	// gen token
-+	/* Token Release Format
-+		Category code : 	1 Byte
-+		Action code : 		1 Byte */
-+	int ret = _FAIL;
-+	//u16	*fctrl;
-+	u8	val = 0x01;
-+	u8	category = RTW_WLAN_CATEGORY_TBTX;
-+	u8	*pframe;
-+	struct xmit_frame		*pmgntframe;
-+	struct pkt_attrib		*pattrib;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	struct	mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	//struct sta_info			*psta;
-+	//struct sta_priv			*pstapriv = &padapter->stapriv;
-+	//struct registry_priv		*pregpriv = &padapter->registrypriv;
-+	
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		return;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+	
-+	/*update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+	pattrib->rate = MGN_24M; /* issue action release using OFDM rate? 20190716 Bruce add */ 
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+	
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	//fctrl = &(pwlanhdr->frame_ctl);
-+	//*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	// SetSeqNum??
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(val), &(pattrib->pktlen));
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	//RTW_INFO("%s\n", __func__);
-+
-+}
-+#endif
-+
-+unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	int i;
-+	unsigned char	category;
-+	struct action_handler *ptable;
-+	unsigned char	*frame_body;
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+
-+	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
-+
-+	category = frame_body[0];
-+
-+	for (i = 0; i < sizeof(OnAction_tbl) / sizeof(struct action_handler); i++) {
-+		ptable = &OnAction_tbl[i];
-+
-+		if (category == ptable->num)
-+			ptable->func(padapter, precv_frame);
-+
-+	}
-+
-+	return _SUCCESS;
-+
-+}
-+
-+unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+
-+	/* RTW_INFO("rcvd mgt frame(%x, %x)\n", (get_frame_sub_type(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe)); */
-+	return _SUCCESS;
-+}
-+
-+struct xmit_frame *_alloc_mgtxmitframe(struct xmit_priv *pxmitpriv, bool once)
-+{
-+	struct xmit_frame *pmgntframe;
-+	struct xmit_buf *pxmitbuf;
-+
-+	if (once)
-+		pmgntframe = rtw_alloc_xmitframe_once(pxmitpriv);
-+	else
-+		pmgntframe = rtw_alloc_xmitframe_ext(pxmitpriv);
-+
-+	if (pmgntframe == NULL) {
-+		RTW_INFO(FUNC_ADPT_FMT" alloc xmitframe fail, once:%d\n", FUNC_ADPT_ARG(pxmitpriv->adapter), once);
-+		goto exit;
-+	}
-+
-+	pxmitbuf = rtw_alloc_xmitbuf_ext(pxmitpriv);
-+	if (pxmitbuf == NULL) {
-+		RTW_INFO(FUNC_ADPT_FMT" alloc xmitbuf fail\n", FUNC_ADPT_ARG(pxmitpriv->adapter));
-+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+		pmgntframe = NULL;
-+		goto exit;
-+	}
-+
-+	pmgntframe->frame_tag = MGNT_FRAMETAG;
-+	pmgntframe->pxmitbuf = pxmitbuf;
-+	pmgntframe->buf_addr = pxmitbuf->pbuf;
-+	pxmitbuf->priv_data = pmgntframe;
-+
-+exit:
-+	return pmgntframe;
-+
-+}
-+
-+inline struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv)
-+{
-+	return _alloc_mgtxmitframe(pxmitpriv, _FALSE);
-+}
-+
-+inline struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv)
-+{
-+	return _alloc_mgtxmitframe(pxmitpriv, _TRUE);
-+}
-+
-+
-+/****************************************************************************
-+
-+Following are some TX fuctions for WiFi MLME
-+
-+*****************************************************************************/
-+
-+void update_mgnt_tx_rate(_adapter *padapter, u8 rate)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+
-+	pmlmeext->tx_rate = rate;
-+	/* RTW_INFO("%s(): rate = %x\n",__FUNCTION__, rate); */
-+}
-+
-+
-+void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	u8	wireless_mode;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
-+	struct sta_info		*psta = NULL;
-+	struct sta_priv		*pstapriv = &padapter->stapriv;
-+
-+	psta = rtw_get_stainfo(pstapriv, pattrib->ra);
-+
-+	pattrib->hdrlen = 24;
-+	pattrib->nr_frags = 1;
-+	pattrib->priority = 7;
-+	pattrib->mac_id = RTW_DEFAULT_MGMT_MACID;
-+	pattrib->qsel = QSLT_MGNT;
-+
-+	pattrib->pktlen = 0;
-+
-+	if (pmlmeext->tx_rate == IEEE80211_CCK_RATE_1MB)
-+		wireless_mode = WIRELESS_11B;
-+	else
-+		wireless_mode = WIRELESS_11G;
-+
-+	pattrib->raid = rtw_get_mgntframe_raid(padapter, wireless_mode);
-+#ifdef CONFIG_80211AC_VHT
-+	if (pHalData->rf_type == RF_1T1R)
-+		pattrib->raid = RATEID_IDX_VHT_1SS;
-+	else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
-+		pattrib->raid = RATEID_IDX_VHT_2SS;
-+	else if (pHalData->rf_type == RF_3T3R)
-+		pattrib->raid = RATEID_IDX_VHT_3SS;
-+	else
-+		pattrib->raid = RATEID_IDX_BGN_40M_1SS;
-+#endif
-+
-+#ifdef CONFIG_80211AC_VHT
-+	pattrib->rate = MGN_VHT1SS_MCS9;
-+#else
-+	pattrib->rate = MGN_MCS7;
-+#endif
-+
-+	pattrib->encrypt = _NO_PRIVACY_;
-+	pattrib->bswenc = _FALSE;
-+
-+	pattrib->qos_en = _FALSE;
-+	pattrib->ht_en = 1;
-+	pattrib->bwmode = CHANNEL_WIDTH_20;
-+	pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	pattrib->sgi = _FALSE;
-+
-+	pattrib->seqnum = pmlmeext->mgnt_seq;
-+
-+	pattrib->retry_ctrl = _TRUE;
-+
-+	pattrib->mbssid = 0;
-+	pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no;
-+
-+}
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+void update_mgntframe_subtype(_adapter *padapter, struct xmit_frame *pmgntframe)
-+{
-+	struct pkt_attrib *pattrib = &pmgntframe->attrib;
-+	u8 *pframe;
-+	u8 subtype, category ,action;
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */
-+	pattrib->subtype = subtype;
-+
-+	rtw_action_frame_parse(pframe, pattrib->pktlen, &category, &action);
-+
-+	if ((subtype == WIFI_ACTION && !(action == ACT_PUBLIC_FTM_REQ || action == ACT_PUBLIC_FTM)) ||
-+		subtype == WIFI_DISASSOC || subtype == WIFI_DEAUTH ||
-+		(subtype == WIFI_PROBERSP && MLME_IS_ADHOC(padapter)))
-+		pattrib->ps_dontq = 0;
-+	else
-+		pattrib->ps_dontq = 1;
-+}
-+#endif
-+
-+void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
-+{
-+	u8	wireless_mode;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *psta;
-+
-+#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */
-+
-+	/* _rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib)); */
-+
-+	pattrib->hdrlen = 24;
-+	pattrib->nr_frags = 1;
-+	pattrib->priority = 7;
-+	pattrib->mac_id = RTW_DEFAULT_MGMT_MACID;
-+	pattrib->qsel = QSLT_MGNT;
-+
-+#ifdef CONFIG_MCC_MODE
-+	update_mcc_mgntframe_attrib(padapter, pattrib);
-+#endif
-+
-+
-+#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE))
-+#endif /* CONFIG_CONCURRENT_MODE */
-+		if (MLME_IS_GC(padapter)) {
-+			if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) {
-+				struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+				struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+				WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
-+
-+				psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
-+				if (psta) {
-+					/* use macid sleep during NoA, mgmt frame use ac queue & ap macid */
-+					pattrib->mac_id = psta->cmn.mac_id;
-+					pattrib->qsel = QSLT_VO;
-+				} else {
-+					if (pwdinfo->p2p_ps_state != P2P_PS_DISABLE)
-+						RTW_ERR("%s , psta was NULL\n", __func__);
-+				}
-+			}
-+		}
-+#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */
-+
-+	pattrib->pktlen = 0;
-+
-+	if (IS_CCK_RATE(pmlmeext->tx_rate))
-+		wireless_mode = WIRELESS_11B;
-+	else
-+		wireless_mode = WIRELESS_11G;
-+	pattrib->raid =  rtw_get_mgntframe_raid(padapter, wireless_mode);
-+	pattrib->rate = pmlmeext->tx_rate;
-+
-+	pattrib->encrypt = _NO_PRIVACY_;
-+	pattrib->bswenc = _FALSE;
-+
-+	pattrib->qos_en = _FALSE;
-+	pattrib->ht_en = _FALSE;
-+	pattrib->bwmode = CHANNEL_WIDTH_20;
-+	pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	pattrib->sgi = _FALSE;
-+
-+	pattrib->seqnum = pmlmeext->mgnt_seq;
-+
-+	pattrib->retry_ctrl = _TRUE;
-+
-+	pattrib->mbssid = 0;
-+	pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no;
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	pattrib->ps_dontq = 1;
-+#endif
-+}
-+
-+void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe)
-+{
-+	u8 *pframe;
-+	struct pkt_attrib *pattrib = &pmgntframe->attrib;
-+#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) || defined(CONFIG_RTW_MGMT_QUEUE)
-+	struct sta_info *sta = NULL;
-+#endif
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+
-+	_rtw_memcpy(pattrib->ra, GetAddr1Ptr(pframe), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, get_addr2_ptr(pframe), ETH_ALEN);
-+
-+#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) || defined(CONFIG_RTW_MGMT_QUEUE)
-+	sta = pattrib->psta;
-+	if (!sta) {
-+		sta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
-+		pattrib->psta = sta;
-+	}
-+
-+	#ifdef CONFIG_BEAMFORMING
-+	if (sta)
-+		update_attrib_txbf_info(padapter, pattrib, sta);
-+	#endif
-+#endif /* defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) || defined(CONFIG_RTW_MGMT_QUEUE) */
-+}
-+
-+void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe)
-+{
-+	if (RTW_CANNOT_RUN(padapter)) {
-+		rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);
-+		return;
-+	}
-+
-+	rtw_hal_mgnt_xmit(padapter, pmgntframe);
-+}
-+
-+s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms)
-+{
-+	s32 ret = _FAIL;
-+	_irqL irqL;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	struct xmit_buf *pxmitbuf = pmgntframe->pxmitbuf;
-+	struct submit_ctx sctx;
-+
-+	if (RTW_CANNOT_RUN(padapter)) {
-+		rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);
-+		return ret;
-+	}
-+
-+	rtw_sctx_init(&sctx, timeout_ms);
-+	pxmitbuf->sctx = &sctx;
-+
-+	ret = rtw_hal_mgnt_xmit(padapter, pmgntframe);
-+
-+	if (ret == _SUCCESS
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	|| ret == RTW_QUEUE_MGMT
-+#endif
-+	)
-+		ret = rtw_sctx_wait(&sctx, __func__);
-+
-+	_enter_critical(&pxmitpriv->lock_sctx, &irqL);
-+	pxmitbuf->sctx = NULL;
-+	_exit_critical(&pxmitpriv->lock_sctx, &irqL);
-+
-+	return ret;
-+}
-+
-+s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms)
-+{
-+#ifdef CONFIG_XMIT_ACK
-+	static u8 seq_no = 0;
-+	s32 ret = _FAIL;
-+	struct xmit_priv	*pxmitpriv = &(GET_PRIMARY_ADAPTER(padapter))->xmitpriv;
-+
-+	if (RTW_CANNOT_RUN(padapter)) {
-+		rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe);
-+		return -1;
-+	}
-+
-+	_enter_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL);
-+	pxmitpriv->ack_tx = _TRUE;
-+	pxmitpriv->seq_no = seq_no++;
-+	pmgntframe->ack_report = 1;
-+	rtw_sctx_init(&(pxmitpriv->ack_tx_ops), timeout_ms);
-+
-+	ret = rtw_hal_mgnt_xmit(padapter, pmgntframe);
-+
-+	if (ret == _SUCCESS
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	|| ret == RTW_QUEUE_MGMT
-+#endif
-+	)
-+		ret = rtw_sctx_wait(&(pxmitpriv->ack_tx_ops), __func__);
-+
-+	pxmitpriv->ack_tx = _FALSE;
-+	_exit_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL);
-+
-+	return ret;
-+#else /* !CONFIG_XMIT_ACK */
-+	dump_mgntframe(padapter, pmgntframe);
-+	rtw_msleep_os(50);
-+	return _SUCCESS;
-+#endif /* !CONFIG_XMIT_ACK */
-+}
-+
-+s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe)
-+{
-+	/* In this case, use 500 ms as the default wait_ack timeout */
-+	return dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, 500);
-+}
-+
-+
-+int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode)
-+{
-+	u8 *ssid_ie;
-+	sint ssid_len_ori;
-+	int len_diff = 0;
-+
-+	ssid_ie = rtw_get_ie(ies,  WLAN_EID_SSID, &ssid_len_ori, ies_len);
-+
-+	/* RTW_INFO("%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\n", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); */
-+
-+	if (ssid_ie && ssid_len_ori > 0) {
-+		switch (hidden_ssid_mode) {
-+		case 1: {
-+			u8 *next_ie = ssid_ie + 2 + ssid_len_ori;
-+			u32 remain_len = 0;
-+
-+			remain_len = ies_len - (next_ie - ies);
-+
-+			ssid_ie[1] = 0;
-+			_rtw_memcpy(ssid_ie + 2, next_ie, remain_len);
-+			len_diff -= ssid_len_ori;
-+
-+			break;
-+		}
-+		case 2:
-+			_rtw_memset(&ssid_ie[2], 0, ssid_len_ori);
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	return len_diff;
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+void issue_beacon(_adapter *padapter, int timeout_ms)
-+{
-+	struct xmit_frame	*pmgntframe;
-+	struct pkt_attrib	*pattrib;
-+	unsigned char	*pframe;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	unsigned short *fctrl;
-+	unsigned int	rate_len;
-+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
-+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
-+	_irqL irqL;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
-+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+#endif /* CONFIG_P2P */
-+
-+
-+	/* RTW_INFO("%s\n", __FUNCTION__); */
-+
-+#ifdef CONFIG_BCN_ICF
-+	pmgntframe = rtw_alloc_bcnxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+#else
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+#endif
-+	{
-+		RTW_INFO("%s, alloc mgnt frame fail\n", __FUNCTION__);
-+		return;
-+	}
-+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
-+	_enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
-+#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+	pattrib->qsel = QSLT_BEACON;
-+
-+#if defined(CONFIG_CONCURRENT_MODE) && (!defined(CONFIG_SWTIMER_BASED_TXBCN))
-+	if (padapter->hw_port == HW_PORT1)
-+		pattrib->mbssid = 1;
-+#endif
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+	if (padapter->vap_id != CONFIG_LIMITED_AP_NUM)
-+		pattrib->mbssid = padapter->vap_id;
-+#endif
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
-+	/* pmlmeext->mgnt_seq++; */
-+	set_frame_sub_type(pframe, WIFI_BEACON);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
-+		/* RTW_INFO("ie len=%d\n", cur_network->IELength); */
-+#ifdef CONFIG_P2P
-+		/* for P2P : Primary Device Type & Device Name */
-+		u32 wpsielen = 0, insert_len = 0;
-+		u8 *wpsie = NULL;
-+		wpsie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen);
-+
-+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen > 0) {
-+			uint wps_offset, remainder_ielen;
-+			u8 *premainder_ie, *pframe_wscie;
-+
-+			wps_offset = (uint)(wpsie - cur_network->IEs);
-+
-+			premainder_ie = wpsie + wpsielen;
-+
-+			remainder_ielen = cur_network->IELength - wps_offset - wpsielen;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+			if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
-+				if (pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len > 0) {
-+					_rtw_memcpy(pframe, cur_network->IEs, wps_offset);
-+					pframe += wps_offset;
-+					pattrib->pktlen += wps_offset;
-+
-+					_rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);
-+					pframe += pmlmepriv->wps_beacon_ie_len;
-+					pattrib->pktlen += pmlmepriv->wps_beacon_ie_len;
-+
-+					/* copy remainder_ie to pframe */
-+					_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
-+					pframe += remainder_ielen;
-+					pattrib->pktlen += remainder_ielen;
-+				} else {
-+					_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
-+					pframe += cur_network->IELength;
-+					pattrib->pktlen += cur_network->IELength;
-+				}
-+			} else
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+			{
-+				pframe_wscie = pframe + wps_offset;
-+				_rtw_memcpy(pframe, cur_network->IEs, wps_offset + wpsielen);
-+				pframe += (wps_offset + wpsielen);
-+				pattrib->pktlen += (wps_offset + wpsielen);
-+
-+				/* now pframe is end of wsc ie, insert Primary Device Type & Device Name */
-+				/*	Primary Device Type */
-+				/*	Type: */
-+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
-+				insert_len += 2;
-+
-+				/*	Length: */
-+				*(u16 *)(pframe + insert_len) = cpu_to_be16(0x0008);
-+				insert_len += 2;
-+
-+				/*	Value: */
-+				/*	Category ID */
-+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
-+				insert_len += 2;
-+
-+				/*	OUI */
-+				*(u32 *)(pframe + insert_len) = cpu_to_be32(WPSOUI);
-+				insert_len += 4;
-+
-+				/*	Sub Category ID */
-+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
-+				insert_len += 2;
-+
-+
-+				/*	Device Name */
-+				/*	Type: */
-+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
-+				insert_len += 2;
-+
-+				/*	Length: */
-+				*(u16 *)(pframe + insert_len) = cpu_to_be16(pwdinfo->device_name_len);
-+				insert_len += 2;
-+
-+				/*	Value: */
-+				_rtw_memcpy(pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len);
-+				insert_len += pwdinfo->device_name_len;
-+
-+
-+				/* update wsc ie length */
-+				*(pframe_wscie + 1) = (wpsielen - 2) + insert_len;
-+
-+				/* pframe move to end */
-+				pframe += insert_len;
-+				pattrib->pktlen += insert_len;
-+
-+				/* copy remainder_ie to pframe */
-+				_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
-+				pframe += remainder_ielen;
-+				pattrib->pktlen += remainder_ielen;
-+			}
-+		} else
-+#endif /* CONFIG_P2P */
-+		{
-+			int len_diff;
-+			_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
-+			len_diff = update_hidden_ssid(
-+					   pframe + _BEACON_IE_OFFSET_
-+				   , cur_network->IELength - _BEACON_IE_OFFSET_
-+					   , pmlmeinfo->hidden_ssid_mode
-+				   );
-+			pframe += (cur_network->IELength + len_diff);
-+			pattrib->pktlen += (cur_network->IELength + len_diff);
-+		}
-+
-+		{
-+			u8 *wps_ie;
-+			uint wps_ielen;
-+			u8 sr = 0;
-+			wps_ie = rtw_get_wps_ie(pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_,
-+				pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_, NULL, &wps_ielen);
-+			if (wps_ie && wps_ielen > 0)
-+				rtw_get_wps_attr_content(wps_ie,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);
-+			if (sr != 0)
-+				set_fwstate(pmlmepriv, WIFI_UNDER_WPS);
-+			else
-+				_clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS);
-+		}
-+
-+#ifdef CONFIG_P2P
-+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+			u32 len;
-+#ifdef CONFIG_IOCTL_CFG80211
-+			if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
-+				len = pmlmepriv->p2p_beacon_ie_len;
-+				if (pmlmepriv->p2p_beacon_ie && len > 0)
-+					_rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len);
-+			} else
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+			{
-+				len = build_beacon_p2p_ie(pwdinfo, pframe);
-+			}
-+
-+			pframe += len;
-+			pattrib->pktlen += len;
-+
-+#ifdef CONFIG_MCC_MODE
-+			pframe = rtw_hal_mcc_append_go_p2p_ie(padapter, pframe, &pattrib->pktlen);
-+#endif /* CONFIG_MCC_MODE*/
-+
-+#ifdef CONFIG_WFD
-+			len = rtw_append_beacon_wfd_ie(padapter, pframe);
-+			pframe += len;
-+			pattrib->pktlen += len;
-+#endif
-+		}
-+#endif /* CONFIG_P2P */
-+#ifdef CONFIG_RTW_REPEATER_SON
-+		rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);
-+#endif
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+		pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_BEACON_VENDOR_IE_BIT);
-+#endif
-+
-+#ifdef CONFIG_RTL8812A 
-+		pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen );
-+#endif/*CONFIG_RTL8812A*/
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+		if (padapter->tbtx_capability == _TRUE)
-+			pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 8, REALTEK_TBTX_IE, &pattrib->pktlen);
-+#endif
-+
-+		goto _issue_bcn;
-+
-+	}
-+
-+	/* below for ad-hoc mode */
-+
-+	/* timestamp will be inserted by hardware */
-+	pframe += 8;
-+	pattrib->pktlen += 8;
-+
-+	/* beacon interval: 2 bytes */
-+
-+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
-+
-+	pframe += 2;
-+	pattrib->pktlen += 2;
-+
-+	/* capability info: 2 bytes */
-+
-+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
-+
-+	pframe += 2;
-+	pattrib->pktlen += 2;
-+
-+	/* SSID */
-+	pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen);
-+
-+	/* supported rates... */
-+	rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
-+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pattrib->pktlen);
-+
-+	/* DS parameter set */
-+	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen);
-+
-+	/* if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) */
-+	{
-+		u8 erpinfo = 0;
-+		u32 ATIMWindow;
-+		/* IBSS Parameter Set... */
-+		/* ATIMWindow = cur->Configuration.ATIMWindow; */
-+		ATIMWindow = 0;
-+		pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen);
-+
-+		/* ERP IE */
-+		pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen);
-+	}
-+
-+
-+	/* EXTERNDED SUPPORTED RATE */
-+	if (rate_len > 8)
-+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen);
-+
-+
-+	/* todo:HT for adhoc */
-+
-+_issue_bcn:
-+
-+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
-+	pmlmepriv->update_bcn = _FALSE;
-+
-+	_exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
-+#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
-+
-+	if ((pattrib->pktlen + TXDESC_SIZE) > MAX_BEACON_LEN) {
-+		RTW_ERR("beacon frame too large ,len(%d,%d)\n",
-+			(pattrib->pktlen + TXDESC_SIZE), MAX_BEACON_LEN);
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	/* RTW_INFO("issue bcn_sz=%d\n", pattrib->last_txcmdsz); */
-+	if (timeout_ms > 0)
-+		dump_mgntframe_and_wait(padapter, pmgntframe, timeout_ms);
-+	else
-+		dump_mgntframe(padapter, pmgntframe);
-+
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq)
-+{
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	unsigned char					*mac, *bssid;
-+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
-+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
-+	u8 *pwps_ie;
-+	uint wps_ielen;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
-+	unsigned int	rate_len;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+#endif /* CONFIG_P2P */
-+
-+	/* RTW_INFO("%s\n", __FUNCTION__); */
-+
-+	if (da == NULL)
-+		return;
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		return;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL) {
-+		RTW_INFO("%s, alloc mgnt frame fail\n", __FUNCTION__);
-+		return;
-+	}
-+
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	mac = adapter_mac_addr(padapter);
-+	bssid = cur_network->MacAddress;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(fctrl, WIFI_PROBERSP);
-+
-+	pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = pattrib->hdrlen;
-+	pframe += pattrib->hdrlen;
-+
-+
-+	if (cur_network->IELength > MAX_IE_SZ)
-+		return;
-+
-+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
-+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
-+		pwps_ie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wps_ielen);
-+
-+		/* inerset & update wps_probe_resp_ie */
-+		if ((pmlmepriv->wps_probe_resp_ie != NULL) && pwps_ie && (wps_ielen > 0)) {
-+			uint wps_offset, remainder_ielen;
-+			u8 *premainder_ie;
-+
-+			wps_offset = (uint)(pwps_ie - cur_network->IEs);
-+
-+			premainder_ie = pwps_ie + wps_ielen;
-+
-+			remainder_ielen = cur_network->IELength - wps_offset - wps_ielen;
-+
-+			_rtw_memcpy(pframe, cur_network->IEs, wps_offset);
-+			pframe += wps_offset;
-+			pattrib->pktlen += wps_offset;
-+
-+			wps_ielen = (uint)pmlmepriv->wps_probe_resp_ie[1];/* to get ie data len */
-+			if ((wps_offset + wps_ielen + 2) <= MAX_IE_SZ) {
-+				_rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, wps_ielen + 2);
-+				pframe += wps_ielen + 2;
-+				pattrib->pktlen += wps_ielen + 2;
-+			}
-+
-+			if ((wps_offset + wps_ielen + 2 + remainder_ielen) <= MAX_IE_SZ) {
-+				_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
-+				pframe += remainder_ielen;
-+				pattrib->pktlen += remainder_ielen;
-+			}
-+		} else {
-+			_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
-+			pframe += cur_network->IELength;
-+			pattrib->pktlen += cur_network->IELength;
-+		}
-+
-+		/* retrieve SSID IE from cur_network->Ssid */
-+		{
-+			u8 *ssid_ie;
-+			sint ssid_ielen;
-+			sint ssid_ielen_diff;
-+			u8 buf[MAX_IE_SZ];
-+			u8 *ies = pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+			ssid_ie = rtw_get_ie(ies + _FIXED_IE_LENGTH_, _SSID_IE_, &ssid_ielen,
-+				     (pframe - ies) - _FIXED_IE_LENGTH_);
-+
-+			ssid_ielen_diff = cur_network->Ssid.SsidLength - ssid_ielen;
-+
-+			if (ssid_ie &&  cur_network->Ssid.SsidLength) {
-+				uint remainder_ielen;
-+				u8 *remainder_ie;
-+				remainder_ie = ssid_ie + 2;
-+				remainder_ielen = (pframe - remainder_ie);
-+
-+				if (remainder_ielen > MAX_IE_SZ) {
-+					RTW_WARN(FUNC_ADPT_FMT" remainder_ielen > MAX_IE_SZ\n", FUNC_ADPT_ARG(padapter));
-+					remainder_ielen = MAX_IE_SZ;
-+				}
-+
-+				_rtw_memcpy(buf, remainder_ie, remainder_ielen);
-+				_rtw_memcpy(remainder_ie + ssid_ielen_diff, buf, remainder_ielen);
-+				*(ssid_ie + 1) = cur_network->Ssid.SsidLength;
-+				_rtw_memcpy(ssid_ie + 2, cur_network->Ssid.Ssid, cur_network->Ssid.SsidLength);
-+
-+				pframe += ssid_ielen_diff;
-+				pattrib->pktlen += ssid_ielen_diff;
-+			}
-+		}
-+#ifdef CONFIG_RTW_REPEATER_SON
-+		rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);
-+#endif
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+		pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_PROBERESP_VENDOR_IE_BIT);
-+#endif
-+	} else
-+#endif
-+	{
-+
-+		/* timestamp will be inserted by hardware */
-+		pframe += 8;
-+		pattrib->pktlen += 8;
-+
-+		/* beacon interval: 2 bytes */
-+
-+		_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
-+
-+		pframe += 2;
-+		pattrib->pktlen += 2;
-+
-+		/* capability info: 2 bytes */
-+
-+		_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
-+
-+		pframe += 2;
-+		pattrib->pktlen += 2;
-+
-+		/* below for ad-hoc mode */
-+
-+		/* SSID */
-+		pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen);
-+
-+		/* supported rates... */
-+		rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
-+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pattrib->pktlen);
-+
-+		/* DS parameter set */
-+		pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen);
-+
-+		if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
-+			u8 erpinfo = 0;
-+			u32 ATIMWindow;
-+			/* IBSS Parameter Set... */
-+			/* ATIMWindow = cur->Configuration.ATIMWindow; */
-+			ATIMWindow = 0;
-+			pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen);
-+
-+			/* ERP IE */
-+			pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen);
-+		}
-+
-+
-+		/* EXTERNDED SUPPORTED RATE */
-+		if (rate_len > 8)
-+			pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen);
-+
-+
-+		/* todo:HT for adhoc */
-+
-+	}
-+
-+#ifdef CONFIG_P2P
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)
-+	    /* IOT issue, When wifi_spec is not set, send probe_resp with P2P IE even if probe_req has no P2P IE */
-+	    && (is_valid_p2p_probereq || !padapter->registrypriv.wifi_spec)) {
-+		u32 len;
-+#ifdef CONFIG_IOCTL_CFG80211
-+		if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
-+			/* if pwdinfo->role == P2P_ROLE_DEVICE will call issue_probersp_p2p() */
-+			len = pmlmepriv->p2p_go_probe_resp_ie_len;
-+			if (pmlmepriv->p2p_go_probe_resp_ie && len > 0)
-+				_rtw_memcpy(pframe, pmlmepriv->p2p_go_probe_resp_ie, len);
-+		} else
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+		{
-+			len = build_probe_resp_p2p_ie(pwdinfo, pframe);
-+		}
-+
-+		pframe += len;
-+		pattrib->pktlen += len;
-+
-+#ifdef CONFIG_MCC_MODE
-+		pframe = rtw_hal_mcc_append_go_p2p_ie(padapter, pframe, &pattrib->pktlen);
-+#endif /* CONFIG_MCC_MODE*/
-+
-+#ifdef CONFIG_WFD
-+		len = rtw_append_probe_resp_wfd_ie(padapter, pframe);
-+		pframe += len;
-+		pattrib->pktlen += len;
-+#endif
-+	}
-+#endif /* CONFIG_P2P */
-+
-+
-+#ifdef CONFIG_AUTO_AP_MODE
-+	{
-+		struct sta_info	*psta;
-+		struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+		RTW_INFO("(%s)\n", __FUNCTION__);
-+
-+		/* check rc station */
-+		psta = rtw_get_stainfo(pstapriv, da);
-+		if (psta && psta->isrc && psta->pid > 0) {
-+			u8 RC_OUI[4] = {0x00, 0xE0, 0x4C, 0x0A};
-+			u8 RC_INFO[14] = {0};
-+			/* EID[1] + EID_LEN[1] + RC_OUI[4] + MAC[6] + PairingID[2] + ChannelNum[2] */
-+			u16 cu_ch = (u16)cur_network->Configuration.DSConfig;
-+
-+			RTW_INFO("%s, reply rc(pid=0x%x) device "MAC_FMT" in ch=%d\n", __FUNCTION__,
-+				 psta->pid, MAC_ARG(psta->cmn.mac_addr), cu_ch);
-+
-+			/* append vendor specific ie */
-+			_rtw_memcpy(RC_INFO, RC_OUI, sizeof(RC_OUI));
-+			_rtw_memcpy(&RC_INFO[4], mac, ETH_ALEN);
-+			_rtw_memcpy(&RC_INFO[10], (u8 *)&psta->pid, 2);
-+			_rtw_memcpy(&RC_INFO[12], (u8 *)&cu_ch, 2);
-+
-+			pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, sizeof(RC_INFO), RC_INFO, &pattrib->pktlen);
-+		}
-+	}
-+#endif /* CONFIG_AUTO_AP_MODE */
-+
-+#ifdef CONFIG_RTL8812A 
-+	pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen);
-+#endif/*CONFIG_RTL8812A*/
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return;
-+
-+}
-+
-+int _issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int wait_ack)
-+{
-+	int ret = _FAIL;
-+	struct xmit_frame		*pmgntframe;
-+	struct pkt_attrib		*pattrib;
-+	unsigned char			*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short		*fctrl;
-+	unsigned char			*mac;
-+	unsigned char			bssrate[NumRates];
-+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	int	bssrate_len = 0;
-+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+#endif
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		goto exit;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+	if ((pwdev_priv->pno_mac_addr[0] != 0xFF)
-+	    && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)
-+	    && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE))
-+		mac = pwdev_priv->pno_mac_addr;
-+	else
-+#endif
-+	mac = adapter_mac_addr(padapter);
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	if (da) {
-+		/*	unicast probe request frame */
-+		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
-+	} else {
-+		/*	broadcast probe request frame */
-+		_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);
-+	}
-+
-+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+	if ((pwdev_priv->pno_mac_addr[0] != 0xFF)
-+	    && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)
-+	    && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE)) {
-+#ifdef CONFIG_RTW_DEBUG
-+		RTW_DBG("%s pno_scan_seq_num: %d\n", __func__,
-+			 pwdev_priv->pno_scan_seq_num);
-+#endif
-+		SetSeqNum(pwlanhdr, pwdev_priv->pno_scan_seq_num);
-+		pattrib->seqnum = pwdev_priv->pno_scan_seq_num;
-+		pattrib->qos_en = 1;
-+		pwdev_priv->pno_scan_seq_num++;
-+	} else
-+#endif
-+	{
-+		SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+		pmlmeext->mgnt_seq++;
-+	}
-+	set_frame_sub_type(pframe, WIFI_PROBEREQ);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	if (pssid && !MLME_IS_MESH(padapter))
-+		pframe = rtw_set_ie(pframe, _SSID_IE_, pssid->SsidLength, pssid->Ssid, &(pattrib->pktlen));
-+	else
-+		pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &(pattrib->pktlen));
-+
-+	get_rate_set(padapter, bssrate, &bssrate_len);
-+
-+	if (bssrate_len > 8) {
-+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));
-+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));
-+	} else
-+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
-+
-+	if (ch)
-+		pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, &ch, &pattrib->pktlen);
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(padapter)) {
-+		if (pssid)
-+			pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, pssid->Ssid, pssid->SsidLength);
-+		else
-+			pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, NULL, 0);
-+	}
-+#endif
-+
-+	if (append_wps) {
-+		/* add wps_ie for wps2.0 */
-+		if (pmlmepriv->wps_probe_req_ie_len > 0 && pmlmepriv->wps_probe_req_ie) {
-+			_rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len);
-+			pframe += pmlmepriv->wps_probe_req_ie_len;
-+			pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len;
-+			/* pmlmepriv->wps_probe_req_ie_len = 0 ; */ /* reset to zero */
-+		}
-+	}
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+	pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_PROBEREQ_VENDOR_IE_BIT);
-+#endif
-+
-+#ifdef CONFIG_RTL8812A 
-+	pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen );
-+#endif/*CONFIG_RTL8812A*/
-+
-+
-+#ifdef CONFIG_RTW_MBO
-+	rtw_mbo_build_probe_req_ies(	padapter, &pframe, pattrib);
-+#endif
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+
-+	if (wait_ack)
-+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
-+	else {
-+		dump_mgntframe(padapter, pmgntframe);
-+		ret = _SUCCESS;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+inline void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da)
-+{
-+	_issue_probereq(padapter, pssid, da, 0, 1, _FALSE);
-+}
-+
-+/*
-+ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
-+ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
-+ * try_cnt means the maximal TX count to try
-+ */
-+int issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps,
-+		      int try_cnt, int wait_ms)
-+{
-+	int ret = _FAIL;
-+	int i = 0;
-+	systime start = rtw_get_current_time();
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		goto exit;
-+
-+	do {
-+		ret = _issue_probereq(padapter, pssid, da, ch, append_wps, wait_ms > 0 ? _TRUE : _FALSE);
-+
-+		i++;
-+
-+		if (RTW_CANNOT_RUN(padapter))
-+			break;
-+
-+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
-+			rtw_msleep_os(wait_ms);
-+
-+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
-+
-+	if (ret != _FAIL) {
-+		ret = _SUCCESS;
-+#ifndef DBG_XMIT_ACK
-+		goto exit;
-+#endif
-+	}
-+
-+	if (try_cnt && wait_ms) {
-+		if (da)
-+			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
-+				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
-+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+		else
-+			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
-+				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
-+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+	}
-+exit:
-+	return ret;
-+}
-+
-+/* if psta == NULL, indiate we are station(client) now... */
-+void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status)
-+{
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	unsigned int					val32;
-+	unsigned short				val16;
-+	int use_shared_key = 0;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		return;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_AUTH);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+
-+	if (psta) { /* for AP mode */
-+#ifdef CONFIG_NATIVEAP_MLME
-+
-+		_rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
-+
-+
-+		/* setting auth algo number */
-+		val16 = (u16)psta->authalg;
-+
-+		if (status != _STATS_SUCCESSFUL_)
-+			val16 = 0;
-+
-+		if (val16)	{
-+			val16 = cpu_to_le16(val16);
-+			use_shared_key = 1;
-+		}
-+
-+		pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
-+
-+		/* setting auth seq number */
-+		val16 = (u16)psta->auth_seq;
-+		val16 = cpu_to_le16(val16);
-+		pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
-+
-+		/* setting status code... */
-+		val16 = status;
-+		val16 = cpu_to_le16(val16);
-+		pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen));
-+
-+		/* added challenging text... */
-+		if ((psta->auth_seq == 2) && (psta->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1))
-+			pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, psta->chg_txt, &(pattrib->pktlen));
-+#endif
-+	} else {
-+		_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
-+
-+#ifdef CONFIG_RTW_80211R
-+		if (rtw_ft_roam(padapter)) {
-+			/* 2: 802.11R FTAA */
-+			val16 = cpu_to_le16(2);
-+		} else
-+#endif
-+		{
-+			/* setting auth algo number */
-+			val16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ? 1 : 0;	/* 0:OPEN System, 1:Shared key */
-+			if (val16) {
-+				val16 = cpu_to_le16(val16);
-+				use_shared_key = 1;
-+			}
-+		}
-+
-+		/* RTW_INFO("%s auth_algo= %s auth_seq=%d\n",__FUNCTION__,(pmlmeinfo->auth_algo==0)?"OPEN":"SHARED",pmlmeinfo->auth_seq); */
-+
-+		/* setting IV for auth seq #3 */
-+		if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) {
-+			/* RTW_INFO("==> iv(%d),key_index(%d)\n",pmlmeinfo->iv,pmlmeinfo->key_index); */
-+			val32 = ((pmlmeinfo->iv++) | (pmlmeinfo->key_index << 30));
-+			val32 = cpu_to_le32(val32);
-+			pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *)&val32, &(pattrib->pktlen));
-+
-+			pattrib->iv_len = 4;
-+		}
-+
-+		pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
-+
-+		/* setting auth seq number */
-+		val16 = pmlmeinfo->auth_seq;
-+		val16 = cpu_to_le16(val16);
-+		pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen));
-+
-+
-+		/* setting status code... */
-+		val16 = status;
-+		val16 = cpu_to_le16(val16);
-+		pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen));
-+
-+#ifdef CONFIG_RTW_80211R
-+		rtw_ft_build_auth_req_ies(padapter, pattrib, &pframe);
-+#endif
-+
-+		/* then checking to see if sending challenging text... */
-+		if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) {
-+			pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, pmlmeinfo->chg_txt, &(pattrib->pktlen));
-+
-+			SetPrivacy(fctrl);
-+
-+			pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+			pattrib->encrypt = _WEP40_;
-+
-+			pattrib->icv_len = 4;
-+
-+			pattrib->pktlen += pattrib->icv_len;
-+
-+		}
-+
-+	}
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	rtw_wep_encrypt(padapter, (u8 *)pmgntframe);
-+	RTW_INFO("%s\n", __FUNCTION__);
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return;
-+}
-+
-+
-+void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type)
-+{
-+#ifdef CONFIG_AP_MODE
-+	struct xmit_frame	*pmgntframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	struct pkt_attrib *pattrib;
-+	unsigned char	*pbuf, *pframe;
-+	unsigned short val, ie_status;
-+	unsigned short *fctrl;
-+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network);
-+	u8 *ie = pnetwork->IEs, cap[5], i;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+#endif /* CONFIG_P2P */
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		return;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->cmn.mac_addr, ETH_ALEN);
-+	_rtw_memcpy((void *)get_addr2_ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	if ((pkt_type == WIFI_ASSOCRSP) || (pkt_type == WIFI_REASSOCRSP))
-+		set_frame_sub_type(pwlanhdr, pkt_type);
-+	else
-+		return;
-+
-+	pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen += pattrib->hdrlen;
-+	pframe += pattrib->hdrlen;
-+
-+	/* capability */
-+	val = *(unsigned short *)rtw_get_capability_from_ie(ie);
-+#ifdef CONFIG_RTW_80211K
-+	val |= cap_RM;
-+#endif
-+	pframe = rtw_set_fixed_ie(pframe, _CAPABILITY_ , (unsigned char *)&val, &(pattrib->pktlen));
-+
-+	ie_status = cpu_to_le16(status);
-+	pframe = rtw_set_fixed_ie(pframe , _STATUS_CODE_ , (unsigned char *)&ie_status, &(pattrib->pktlen));
-+
-+	val = cpu_to_le16(pstat->cmn.aid | BIT(14) | BIT(15));
-+	pframe = rtw_set_fixed_ie(pframe, _ASOC_ID_ , (unsigned char *)&val, &(pattrib->pktlen));
-+
-+	if (pstat->bssratelen <= 8)
-+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, pstat->bssratelen, pstat->bssrateset, &(pattrib->pktlen));
-+	else {
-+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pstat->bssrateset, &(pattrib->pktlen));
-+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (pstat->bssratelen - 8), pstat->bssrateset + 8, &(pattrib->pktlen));
-+	}
-+
-+#ifdef CONFIG_IEEE80211W
-+	if (status == _STATS_REFUSED_TEMPORARILY_) {
-+		u8 timeout_itvl[5];
-+		u32 timeout_interval = 3000;
-+		/* Association Comeback time */
-+		timeout_itvl[0] = 0x03;
-+		timeout_interval = cpu_to_le32(timeout_interval);
-+		_rtw_memcpy(timeout_itvl + 1, &timeout_interval, 4);
-+		pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen));
-+	}
-+#endif /* CONFIG_IEEE80211W */
-+
-+#ifdef CONFIG_80211N_HT
-+	if ((pstat->flags & WLAN_STA_HT) && (pmlmepriv->htpriv.ht_option)) {
-+		uint ie_len = 0;
-+
-+		/* FILL HT CAP INFO IE */
-+		/* p = hostapd_eid_ht_capabilities_info(hapd, p); */
-+		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
-+		if (pbuf && ie_len > 0) {
-+			_rtw_memcpy(pframe, pbuf, ie_len + 2);
-+			pframe += (ie_len + 2);
-+			pattrib->pktlen += (ie_len + 2);
-+		}
-+
-+		/* FILL HT ADD INFO IE */
-+		/* p = hostapd_eid_ht_operation(hapd, p); */
-+		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
-+		if (pbuf && ie_len > 0) {
-+			_rtw_memcpy(pframe, pbuf, ie_len + 2);
-+			pframe += (ie_len + 2);
-+			pattrib->pktlen += (ie_len + 2);
-+		}
-+
-+	}
-+#endif
-+
-+	/*adding EXT_CAPAB_IE */
-+	if (pmlmepriv->ext_capab_ie_len > 0) {
-+		uint ie_len = 0;
-+
-+		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
-+		if (pbuf && ie_len > 0) {
-+			_rtw_memcpy(pframe, pbuf, ie_len + 2);
-+			pframe += (ie_len + 2);
-+			pattrib->pktlen += (ie_len + 2);
-+		}
-+	}
-+
-+#ifdef CONFIG_80211AC_VHT
-+	if ((pstat->flags & WLAN_STA_VHT) && (pmlmepriv->vhtpriv.vht_option)
-+	    && (pstat->wpa_pairwise_cipher != WPA_CIPHER_TKIP)
-+	    && (pstat->wpa2_pairwise_cipher != WPA_CIPHER_TKIP)) {
-+		u32 ie_len = 0;
-+
-+		/* FILL VHT CAP IE */
-+		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
-+		if (pbuf && ie_len > 0) {
-+			_rtw_memcpy(pframe, pbuf, ie_len + 2);
-+			pframe += (ie_len + 2);
-+			pattrib->pktlen += (ie_len + 2);
-+		}
-+
-+		/* FILL VHT OPERATION IE */
-+		pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTOperation, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
-+		if (pbuf && ie_len > 0) {
-+			_rtw_memcpy(pframe, pbuf, ie_len + 2);
-+			pframe += (ie_len + 2);
-+			pattrib->pktlen += (ie_len + 2);
-+		}
-+	}
-+#endif /* CONFIG_80211AC_VHT */
-+
-+#ifdef CONFIG_RTW_80211K
-+	/* FILL RM Enabled Capabilities with joint capabilities */
-+	for (i = 0; i < 5; i++) {
-+		cap[i] = padapter->rmpriv.rm_en_cap_def[i]
-+			 & pstat->rm_en_cap[i];
-+	}
-+	if (pstat->capability & cap_RM)
-+		pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, 5,
-+				    (u8 *)cap, &(pattrib->pktlen));
-+#endif /* CONFIG_RTW_80211K */
-+
-+	/* FILL WMM IE */
-+	if ((pstat->flags & WLAN_STA_WME) && (pmlmepriv->qospriv.qos_option)) {
-+		uint ie_len = 0;
-+		unsigned char WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};
-+
-+		for (pbuf = ie + _BEACON_IE_OFFSET_; ; pbuf += (ie_len + 2)) {
-+			pbuf = rtw_get_ie(pbuf, _VENDOR_SPECIFIC_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));
-+			if (pbuf && _rtw_memcmp(pbuf + 2, WMM_PARA_IE, 6)) {
-+				_rtw_memcpy(pframe, pbuf, ie_len + 2);
-+				pframe += (ie_len + 2);
-+				pattrib->pktlen += (ie_len + 2);
-+
-+				break;
-+			}
-+
-+			if ((pbuf == NULL) || (ie_len == 0))
-+				break;
-+		}
-+
-+	}
-+
-+
-+	if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK)
-+		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen));
-+
-+	/* add WPS IE ie for wps 2.0 */
-+	if (pmlmepriv->wps_assoc_resp_ie && pmlmepriv->wps_assoc_resp_ie_len > 0) {
-+		_rtw_memcpy(pframe, pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len);
-+
-+		pframe += pmlmepriv->wps_assoc_resp_ie_len;
-+		pattrib->pktlen += pmlmepriv->wps_assoc_resp_ie_len;
-+	}
-+
-+#ifdef CONFIG_P2P
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && (pstat->is_p2p_device == _TRUE)) {
-+		u32 len;
-+
-+		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) {
-+			len = 0;
-+			if (pmlmepriv->p2p_assoc_resp_ie && pmlmepriv->p2p_assoc_resp_ie_len > 0) {
-+				len = pmlmepriv->p2p_assoc_resp_ie_len;
-+				_rtw_memcpy(pframe, pmlmepriv->p2p_assoc_resp_ie, len);
-+			}
-+		} else
-+			len = build_assoc_resp_p2p_ie(pwdinfo, pframe, pstat->p2p_status_code);
-+		pframe += len;
-+		pattrib->pktlen += len;
-+	}
-+
-+#ifdef CONFIG_WFD
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+		wfdielen = rtw_append_assoc_resp_wfd_ie(padapter, pframe);
-+		pframe += wfdielen;
-+		pattrib->pktlen += wfdielen;
-+	}
-+#endif
-+
-+#endif /* CONFIG_P2P */
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+	if (padapter->multi_ap && (pstat->flags & WLAN_STA_MULTI_AP))
-+		pframe = rtw_set_multi_ap_ie_ext(pframe, &pattrib->pktlen, padapter->multi_ap);
-+#endif
-+
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+	pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_ASSOCRESP_VENDOR_IE_BIT);
-+#endif
-+
-+#ifdef CONFIG_RTL8812A 
-+	pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen );
-+#endif/*CONFIG_RTL8812A*/
-+
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	if (padapter->tbtx_capability == _TRUE)
-+		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 8, REALTEK_TBTX_IE, &pattrib->pktlen);
-+#endif
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+#endif
-+}
-+
-+static u32 rtw_append_assoc_req_owe_ie(_adapter *adapter, u8 *pbuf)
-+{
-+	struct security_priv *sec = &adapter->securitypriv;
-+	u32 len = 0;
-+
-+	if (sec == NULL)
-+		goto exit;
-+
-+	if (sec->owe_ie_len > 0) {
-+		len = sec->owe_ie_len;
-+		_rtw_memcpy(pbuf, sec->owe_ie, len);
-+	}
-+
-+exit:
-+	return len;
-+}
-+
-+void _issue_assocreq(_adapter *padapter, u8 is_reassoc)
-+{
-+	int ret = _FAIL;
-+	struct xmit_frame				*pmgntframe;
-+	struct pkt_attrib				*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr			*pwlanhdr;
-+	unsigned short				*fctrl;
-+	unsigned short				val16;
-+	unsigned int					i, j, index = 0;
-+	unsigned char					bssrate[NumRates], sta_bssrate[NumRates];
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	int	bssrate_len = 0, sta_bssrate_len = 0;
-+	u8	vs_ie_length = 0;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	u8					p2pie[255] = { 0x00 };
-+	u16					p2pielen = 0;
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+#endif /* CONFIG_P2P */
-+
-+#if CONFIG_DFS
-+	u16	cap;
-+#endif
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		goto exit;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	if (is_reassoc == _TRUE)
-+		set_frame_sub_type(pframe, WIFI_REASSOCREQ);
-+	else
-+		set_frame_sub_type(pframe, WIFI_ASSOCREQ);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	/* caps */
-+
-+#if CONFIG_DFS
-+	_rtw_memcpy(&cap, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);
-+	cap |= cap_SpecMgmt;
-+#ifdef CONFIG_RTW_80211K
-+	cap |= cap_RM;
-+#endif
-+	_rtw_memcpy(pframe, &cap, 2);
-+#else
-+	_rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);
-+#endif
-+
-+	pframe += 2;
-+	pattrib->pktlen += 2;
-+
-+	/* listen interval */
-+	/* todo: listen interval for power saving */
-+	val16 = cpu_to_le16(3);
-+	_rtw_memcpy(pframe , (unsigned char *)&val16, 2);
-+	pframe += 2;
-+	pattrib->pktlen += 2;
-+
-+	/*Construct Current AP Field for Reassoc-Req only*/
-+	if (is_reassoc == _TRUE) {
-+		_rtw_memcpy(pframe, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+		pframe += ETH_ALEN;
-+		pattrib->pktlen += ETH_ALEN;
-+	}
-+
-+	/* SSID */
-+	pframe = rtw_set_ie(pframe, _SSID_IE_,  pmlmeinfo->network.Ssid.SsidLength, pmlmeinfo->network.Ssid.Ssid, &(pattrib->pktlen));
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS
-+	/* Dot H */
-+	if (pmlmeext->cur_channel > 14) {
-+		struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+		u8 pow_cap_ele[2] = { 0x00 };
-+		u8 sup_ch[30 * 2] = {0x00 }, sup_ch_idx = 0, idx_5g = 2;	/* For supported channel */
-+
-+		pow_cap_ele[0] = 13;	/* Minimum transmit power capability */
-+		pow_cap_ele[1] = 21;	/* Maximum transmit power capability */
-+		pframe = rtw_set_ie(pframe, EID_PowerCap, 2, pow_cap_ele, &(pattrib->pktlen));
-+
-+		/* supported channels */
-+		while (sup_ch_idx < rfctl->max_chan_nums && rfctl->channel_set[sup_ch_idx].ChannelNum != 0) {
-+			if (rfctl->channel_set[sup_ch_idx].ChannelNum <= 14) {
-+				/* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */
-+				sup_ch[0] = 1;	/* First channel number */
-+				sup_ch[1] = rfctl->channel_set[sup_ch_idx].ChannelNum;	/* Number of channel */
-+			} else {
-+				sup_ch[idx_5g++] = rfctl->channel_set[sup_ch_idx].ChannelNum;
-+				sup_ch[idx_5g++] = 1;
-+			}
-+			sup_ch_idx++;
-+		}
-+		pframe = rtw_set_ie(pframe, EID_SupportedChannels, idx_5g, sup_ch, &(pattrib->pktlen));
-+	}
-+#endif /* CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS */
-+
-+	/* supported rate & extended supported rate */
-+
-+#if 1	/* Check if the AP's supported rates are also supported by STA. */
-+	get_rate_set(padapter, sta_bssrate, &sta_bssrate_len);
-+	/* RTW_INFO("sta_bssrate_len=%d\n", sta_bssrate_len); */
-+
-+	if (pmlmeext->cur_channel == 14) /* for JAPAN, channel 14 can only uses B Mode(CCK) */
-+		sta_bssrate_len = 4;
-+
-+
-+	/* for (i = 0; i < sta_bssrate_len; i++) { */
-+	/*	RTW_INFO("sta_bssrate[%d]=%02X\n", i, sta_bssrate[i]); */
-+	/* } */
-+
-+	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
-+		if (pmlmeinfo->network.SupportedRates[i] == 0)
-+			break;
-+		RTW_INFO("network.SupportedRates[%d]=%02X\n", i, pmlmeinfo->network.SupportedRates[i]);
-+	}
-+
-+
-+	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
-+		if (pmlmeinfo->network.SupportedRates[i] == 0)
-+			break;
-+
-+
-+		/* Check if the AP's supported rates are also supported by STA. */
-+		for (j = 0; j < sta_bssrate_len; j++) {
-+			/* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */
-+			if ((pmlmeinfo->network.SupportedRates[i] | IEEE80211_BASIC_RATE_MASK)
-+			    == (sta_bssrate[j] | IEEE80211_BASIC_RATE_MASK)) {
-+				/* RTW_INFO("match i = %d, j=%d\n", i, j); */
-+				break;
-+			} else {
-+				/* RTW_INFO("not match: %02X != %02X\n", (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK), (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK)); */
-+			}
-+		}
-+
-+		if (j == sta_bssrate_len) {
-+			/* the rate is not supported by STA */
-+			RTW_INFO("%s(): the rate[%d]=%02X is not supported by STA!\n", __FUNCTION__, i, pmlmeinfo->network.SupportedRates[i]);
-+		} else {
-+			/* the rate is supported by STA */
-+			bssrate[index++] = pmlmeinfo->network.SupportedRates[i];
-+		}
-+	}
-+
-+	bssrate_len = index;
-+	RTW_INFO("bssrate_len = %d\n", bssrate_len);
-+
-+#else	/* Check if the AP's supported rates are also supported by STA. */
-+#if 0
-+	get_rate_set(padapter, bssrate, &bssrate_len);
-+#else
-+	for (bssrate_len = 0; bssrate_len < NumRates; bssrate_len++) {
-+		if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0)
-+			break;
-+
-+		if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0x2C) /* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */
-+			break;
-+
-+		bssrate[bssrate_len] = pmlmeinfo->network.SupportedRates[bssrate_len];
-+	}
-+#endif
-+#endif /* Check if the AP's supported rates are also supported by STA. */
-+
-+	if ((bssrate_len == 0) && (pmlmeinfo->network.SupportedRates[0] != 0)) {
-+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+		goto exit; /* don't connect to AP if no joint supported rate */
-+	}
-+
-+
-+	if (bssrate_len > 8) {
-+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));
-+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));
-+	} else if (bssrate_len > 0)
-+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
-+	else
-+		RTW_INFO("%s: Connect to AP without 11b and 11g data rate!\n", __FUNCTION__);
-+
-+#ifdef CONFIG_RTW_MBO
-+	rtw_mbo_build_assoc_req_ies(padapter, &pframe, pattrib);
-+#endif
-+#ifdef CONFIG_RTW_80211R
-+	rtw_ft_build_assoc_req_ies(padapter, is_reassoc, pattrib, &pframe);
-+#endif
-+#ifdef CONFIG_RTW_80211K
-+	pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, 5, 
-+			(u8 *)padapter->rmpriv.rm_en_cap_def, 
-+			&(pattrib->pktlen));
-+#endif /* CONFIG_RTW_80211K */
-+
-+	/* vendor specific IE, such as WPA, WMM, WPS */
-+	for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) {
-+		pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);
-+
-+		switch (pIE->ElementID) {
-+		case _VENDOR_SPECIFIC_IE_:
-+			if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) ||
-+			    (_rtw_memcmp(pIE->data, WMM_OUI, 4)) ||
-+			    (_rtw_memcmp(pIE->data, WPS_OUI, 4))) {
-+				vs_ie_length = pIE->Length;
-+				if ((!padapter->registrypriv.wifi_spec) && (_rtw_memcmp(pIE->data, WPS_OUI, 4))) {
-+					/* Commented by Kurt 20110629 */
-+					/* In some older APs, WPS handshake */
-+					/* would be fail if we append vender extensions informations to AP */
-+
-+					vs_ie_length = 14;
-+				}
-+
-+				pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, vs_ie_length, pIE->data, &(pattrib->pktlen));
-+			}
-+			break;
-+
-+		case EID_WPA2:
-+#ifdef CONFIG_RTW_80211R
-+			if ((is_reassoc) && (rtw_ft_roam(padapter))) {
-+				rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe);
-+			} else
-+#endif
-+			{
-+#ifdef CONFIG_IOCTL_CFG80211
-+				if (rtw_sec_chk_auth_alg(padapter, WLAN_AUTH_OPEN) &&
-+					rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE)) {
-+					s32 entry = rtw_cached_pmkid(padapter, pmlmepriv->assoc_bssid);
-+
-+					rtw_rsn_sync_pmkid(padapter, (u8 *)pIE, (pIE->Length + 2), entry);
-+				}
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+				pframe = rtw_set_ie(pframe, EID_WPA2, pIE->Length, pIE->data, &(pattrib->pktlen));
-+			}
-+			break;
-+#ifdef CONFIG_80211N_HT
-+		case EID_HTCapability:
-+			if (padapter->mlmepriv.htpriv.ht_option == _TRUE) {
-+				if (!(is_ap_in_tkip(padapter))) {
-+					_rtw_memcpy(&(pmlmeinfo->HT_caps), pIE->data, sizeof(struct HT_caps_element));
-+
-+					pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = cpu_to_le16(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info);
-+
-+					pframe = rtw_set_ie(pframe, EID_HTCapability, pIE->Length , (u8 *)(&(pmlmeinfo->HT_caps)), &(pattrib->pktlen));
-+				}
-+			}
-+			break;
-+
-+		case EID_EXTCapability:
-+			if (padapter->mlmepriv.htpriv.ht_option == _TRUE)
-+				pframe = rtw_set_ie(pframe, EID_EXTCapability, pIE->Length, pIE->data, &(pattrib->pktlen));
-+			break;
-+#endif /* CONFIG_80211N_HT */
-+#ifdef CONFIG_80211AC_VHT
-+		case EID_VHTCapability:
-+			if (padapter->mlmepriv.vhtpriv.vht_option == _TRUE)
-+				pframe = rtw_set_ie(pframe, EID_VHTCapability, pIE->Length, pIE->data, &(pattrib->pktlen));
-+			break;
-+
-+		case EID_OpModeNotification:
-+			if (padapter->mlmepriv.vhtpriv.vht_option == _TRUE)
-+				pframe = rtw_set_ie(pframe, EID_OpModeNotification, pIE->Length, pIE->data, &(pattrib->pktlen));
-+			break;
-+#endif /* CONFIG_80211AC_VHT */
-+		default:
-+			break;
-+		}
-+
-+		i += (pIE->Length + 2);
-+	}
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	if (padapter->tbtx_capability == _TRUE)
-+		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 8 , REALTEK_TBTX_IE, &(pattrib->pktlen));
-+#endif
-+
-+	if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK)
-+		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen));
-+
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	rtw_build_assoc_req_wapi_ie(padapter, pframe, pattrib);
-+#endif
-+
-+
-+#ifdef CONFIG_P2P
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) {
-+		if (pmlmepriv->p2p_assoc_req_ie && pmlmepriv->p2p_assoc_req_ie_len > 0) {
-+			_rtw_memcpy(pframe, pmlmepriv->p2p_assoc_req_ie, pmlmepriv->p2p_assoc_req_ie_len);
-+			pframe += pmlmepriv->p2p_assoc_req_ie_len;
-+			pattrib->pktlen += pmlmepriv->p2p_assoc_req_ie_len;
-+		}
-+	} else
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+	{
-+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {
-+			/*	Should add the P2P IE in the association request frame.	 */
-+			/*	P2P OUI */
-+
-+			p2pielen = 0;
-+			p2pie[p2pielen++] = 0x50;
-+			p2pie[p2pielen++] = 0x6F;
-+			p2pie[p2pielen++] = 0x9A;
-+			p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+			/*	Commented by Albert 20101109 */
-+			/*	According to the P2P Specification, the association request frame should contain 3 P2P attributes */
-+			/*	1. P2P Capability */
-+			/*	2. Extended Listen Timing */
-+			/*	3. Device Info */
-+			/*	Commented by Albert 20110516 */
-+			/*	4. P2P Interface */
-+
-+			/*	P2P Capability */
-+			/*	Type: */
-+			p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
-+
-+			/*	Length: */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
-+			p2pielen += 2;
-+
-+			/*	Value: */
-+			/*	Device Capability Bitmap, 1 byte */
-+			p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
-+
-+			/*	Group Capability Bitmap, 1 byte */
-+			if (pwdinfo->persistent_supported)
-+				p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
-+			else
-+				p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;
-+
-+			/*	Extended Listen Timing */
-+			/*	Type: */
-+			p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;
-+
-+			/*	Length: */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004);
-+			p2pielen += 2;
-+
-+			/*	Value: */
-+			/*	Availability Period */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
-+			p2pielen += 2;
-+
-+			/*	Availability Interval */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF);
-+			p2pielen += 2;
-+
-+			/*	Device Info */
-+			/*	Type: */
-+			p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
-+
-+			/*	Length: */
-+			/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
-+			/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
-+			p2pielen += 2;
-+
-+			/*	Value: */
-+			/*	P2P Device Address */
-+			_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
-+			p2pielen += ETH_ALEN;
-+
-+			/*	Config Method */
-+			/*	This field should be big endian. Noted by P2P specification. */
-+			if ((pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN) ||
-+			    (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN))
-+				*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_DISPLAY);
-+			else
-+				*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_PBC);
-+
-+			p2pielen += 2;
-+
-+			/*	Primary Device Type */
-+			/*	Category ID */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
-+			p2pielen += 2;
-+
-+			/*	OUI */
-+			*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
-+			p2pielen += 4;
-+
-+			/*	Sub Category ID */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
-+			p2pielen += 2;
-+
-+			/*	Number of Secondary Device Types */
-+			p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
-+
-+			/*	Device Name */
-+			/*	Type: */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
-+			p2pielen += 2;
-+
-+			/*	Length: */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
-+			p2pielen += 2;
-+
-+			/*	Value: */
-+			_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);
-+			p2pielen += pwdinfo->device_name_len;
-+
-+			/*	P2P Interface */
-+			/*	Type: */
-+			p2pie[p2pielen++] = P2P_ATTR_INTERFACE;
-+
-+			/*	Length: */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x000D);
-+			p2pielen += 2;
-+
-+			/*	Value: */
-+			_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);	/*	P2P Device Address */
-+			p2pielen += ETH_ALEN;
-+
-+			p2pie[p2pielen++] = 1;	/*	P2P Interface Address Count */
-+
-+			_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);	/*	P2P Interface Address List */
-+			p2pielen += ETH_ALEN;
-+
-+			pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
-+		}
-+	}
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = rtw_append_assoc_req_wfd_ie(padapter, pframe);
-+	pframe += wfdielen;
-+	pattrib->pktlen += wfdielen;
-+#endif
-+#endif /* CONFIG_P2P */
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+	if (padapter->multi_ap)
-+		pframe = rtw_set_multi_ap_ie_ext(pframe, &pattrib->pktlen, padapter->multi_ap);
-+#endif
-+
-+	/* OWE */
-+	{
-+	u32 owe_ie_len;
-+	
-+	owe_ie_len = rtw_append_assoc_req_owe_ie(padapter, pframe);
-+	pframe += owe_ie_len;
-+	pattrib->pktlen += owe_ie_len;
-+	}
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);
-+#endif
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+	pattrib->pktlen += rtw_build_vendor_ie(padapter , &pframe , WIFI_ASSOCREQ_VENDOR_IE_BIT);
-+#endif
-+
-+#ifdef CONFIG_RTL8812A 
-+	pframe = rtw_hal_set_8812a_vendor_ie(padapter, pframe, &pattrib->pktlen );
-+#endif/*CONFIG_RTL8812A*/
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	if (ret == _SUCCESS) {
-+		rtw_buf_update(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len, (u8 *)pwlanhdr, pattrib->pktlen);
-+	#ifdef CONFIG_RTW_WNM
-+		if (is_reassoc == _TRUE)
-+			rtw_wnm_update_reassoc_req_ie(padapter);
-+	#endif
-+	} else
-+		rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len);
-+
-+	return;
-+}
-+
-+void issue_assocreq(_adapter *padapter)
-+{
-+	_issue_assocreq(padapter, _FALSE);
-+}
-+
-+void issue_reassocreq(_adapter *padapter)
-+{
-+	_issue_assocreq(padapter, _TRUE);
-+}
-+
-+/* when wait_ack is ture, this function shoule be called at process context */
-+static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack)
-+{
-+	int ret = _FAIL;
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	struct xmit_priv	*pxmitpriv;
-+	struct mlme_ext_priv	*pmlmeext;
-+	struct mlme_ext_info	*pmlmeinfo;
-+	u8 a4_shift;
-+
-+	/* RTW_INFO("%s:%d\n", __FUNCTION__, power_mode); */
-+
-+	if (!padapter)
-+		goto exit;
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		goto exit;
-+
-+	pxmitpriv = &(padapter->xmitpriv);
-+	pmlmeext = &(padapter->mlmeextpriv);
-+	pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+	pattrib->retry_ctrl = _FALSE;
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	if (MLME_IS_AP(padapter))
-+		SetFrDs(fctrl);
-+	else if (MLME_IS_STA(padapter))
-+		SetToDs(fctrl);
-+	else if (MLME_IS_MESH(padapter)) {
-+		SetToDs(fctrl);
-+		SetFrDs(fctrl);
-+	}
-+
-+	if (power_mode)
-+		SetPwrMgt(fctrl);
-+
-+	if (get_tofr_ds(fctrl) == 3) {
-+		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN);
-+		a4_shift = ETH_ALEN;
-+		pattrib->hdrlen += ETH_ALEN;
-+	} else {
-+		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+		a4_shift = 0;
-+	}
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_DATA_NULL);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift;
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift;
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	if (wait_ack)
-+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
-+	else {
-+		dump_mgntframe(padapter, pmgntframe);
-+		ret = _SUCCESS;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+/*
-+ * When wait_ms > 0, this function should be called at process context
-+ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
-+ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
-+ * try_cnt means the maximal TX count to try
-+ * da == NULL for station mode
-+ */
-+int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms)
-+{
-+	int ret = _FAIL;
-+	int i = 0;
-+	systime start = rtw_get_current_time();
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		goto exit;
-+
-+	/* da == NULL, assum it's null data for sta to ap */
-+	if (da == NULL)
-+		da = get_my_bssid(&(pmlmeinfo->network));
-+
-+	do {
-+		ret = _issue_nulldata(padapter, da, power_mode, wait_ms > 0 ? _TRUE : _FALSE);
-+
-+		i++;
-+
-+		if (RTW_CANNOT_RUN(padapter))
-+			break;
-+
-+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
-+			rtw_msleep_os(wait_ms);
-+
-+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
-+
-+	if (ret != _FAIL) {
-+		ret = _SUCCESS;
-+#ifndef DBG_XMIT_ACK
-+		goto exit;
-+#endif
-+	}
-+
-+	if (try_cnt && wait_ms) {
-+		if (da)
-+			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
-+				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
-+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+		else
-+			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
-+				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
-+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+	}
-+exit:
-+	return ret;
-+}
-+
-+/* when wait_ack is ture, this function shoule be called at process context */
-+static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int wait_ack)
-+{
-+	int ret = _FAIL;
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl, *qc;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 a4_shift;
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		goto exit;
-+
-+	/* RTW_INFO("%s\n", __FUNCTION__); */
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	pattrib->hdrlen += 2;
-+	pattrib->qos_en = _TRUE;
-+	pattrib->eosp = 1;
-+	pattrib->ack_policy = 0;
-+	pattrib->mdata = 0;
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	if (MLME_IS_AP(padapter))
-+		SetFrDs(fctrl);
-+	else if (MLME_IS_STA(padapter))
-+		SetToDs(fctrl);
-+	else if (MLME_IS_MESH(padapter)) {
-+		SetToDs(fctrl);
-+		SetFrDs(fctrl);
-+	}
-+
-+	if (ps)
-+		SetPwrMgt(fctrl);
-+
-+	if (pattrib->mdata)
-+		SetMData(fctrl);
-+
-+	if (get_tofr_ds(fctrl) == 3) {
-+		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN);
-+		a4_shift = ETH_ALEN;
-+		pattrib->hdrlen += ETH_ALEN;
-+	} else {
-+		_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+		a4_shift = 0;
-+	}
-+
-+	qc = (unsigned short *)(pframe + pattrib->hdrlen - 2);
-+
-+	SetPriority(qc, tid);
-+
-+	SetEOSP(qc, pattrib->eosp);
-+
-+	SetAckpolicy(qc, pattrib->ack_policy);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift;
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift;
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	if (wait_ack)
-+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
-+	else {
-+		dump_mgntframe(padapter, pmgntframe);
-+		ret = _SUCCESS;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+/*
-+ * when wait_ms >0 , this function should be called at process context
-+ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
-+ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
-+ * try_cnt means the maximal TX count to try
-+ * da == NULL for station mode
-+ */
-+int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms)
-+{
-+	int ret = _FAIL;
-+	int i = 0;
-+	systime start = rtw_get_current_time();
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		goto exit;
-+
-+	/* da == NULL, assum it's null data for sta to ap*/
-+	if (da == NULL)
-+		da = get_my_bssid(&(pmlmeinfo->network));
-+
-+	do {
-+		ret = _issue_qos_nulldata(padapter, da, tid, ps, wait_ms > 0 ? _TRUE : _FALSE);
-+
-+		i++;
-+
-+		if (RTW_CANNOT_RUN(padapter))
-+			break;
-+
-+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
-+			rtw_msleep_os(wait_ms);
-+
-+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
-+
-+	if (ret != _FAIL) {
-+		ret = _SUCCESS;
-+#ifndef DBG_XMIT_ACK
-+		goto exit;
-+#endif
-+	}
-+
-+	if (try_cnt && wait_ms) {
-+		if (da)
-+			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
-+				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
-+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+		else
-+			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
-+				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
-+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+	}
-+exit:
-+	return ret;
-+}
-+
-+static int _issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason, u8 wait_ack, u8 key_type)
-+{
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	int ret = _FAIL;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+#endif /* CONFIG_P2P	 */
-+
-+	/* RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); */
-+
-+#ifdef CONFIG_P2P
-+	if (!(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) && (pwdinfo->rx_invitereq_info.scan_op_ch_only)) {
-+		_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
-+		_set_timer(&pwdinfo->reset_ch_sitesurvey, 10);
-+	}
-+#endif /* CONFIG_P2P */
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		goto exit;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+	pattrib->retry_ctrl = _FALSE;
-+	pattrib->key_type = key_type;
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_DEAUTH);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	reason = cpu_to_le16(reason);
-+	pframe = rtw_set_fixed_ie(pframe, _RSON_CODE_ , (unsigned char *)&reason, &(pattrib->pktlen));
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+
-+	if (wait_ack)
-+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
-+	else {
-+		dump_mgntframe(padapter, pmgntframe);
-+		ret = _SUCCESS;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason)
-+{
-+	RTW_INFO("%s reason(%u) to "MAC_FMT"\n", __func__, reason, MAC_ARG(da));
-+	return _issue_deauth(padapter, da, reason, _FALSE, IEEE80211W_RIGHT_KEY);
-+}
-+
-+#ifdef CONFIG_IEEE80211W
-+int issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reason, u8 key_type)
-+{
-+	RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(da));
-+	return _issue_deauth(padapter, da, reason, _FALSE, key_type);
-+}
-+#endif /* CONFIG_IEEE80211W */
-+
-+/*
-+ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
-+ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
-+ * try_cnt means the maximal TX count to try
-+ */
-+int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt,
-+		    int wait_ms)
-+{
-+	int ret = _FAIL;
-+	int i = 0;
-+	systime start = rtw_get_current_time();
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		goto exit;
-+
-+	do {
-+		ret = _issue_deauth(padapter, da, reason, wait_ms > 0 ? _TRUE : _FALSE, IEEE80211W_RIGHT_KEY);
-+
-+		i++;
-+
-+		if (RTW_CANNOT_RUN(padapter))
-+			break;
-+
-+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
-+			rtw_msleep_os(wait_ms);
-+
-+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
-+
-+	if (ret != _FAIL) {
-+		ret = _SUCCESS;
-+#ifndef DBG_XMIT_ACK
-+		goto exit;
-+#endif
-+	}
-+
-+	if (try_cnt && wait_ms) {
-+		if (da)
-+			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
-+				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
-+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+		else
-+			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
-+				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
-+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+	}
-+exit:
-+	return ret;
-+}
-+
-+void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset)
-+{
-+	struct xmit_frame *pmgntframe;
-+	struct pkt_attrib *pattrib;
-+	unsigned char				*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short			*fctrl;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		return;
-+
-+	RTW_INFO(FUNC_NDEV_FMT" ra="MAC_FMT", ch:%u, offset:%u\n",
-+		FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(ra), new_ch, ch_offset);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); /* RA */
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */
-+	_rtw_memcpy(pwlanhdr->addr3, ra, ETH_ALEN); /* DA = RA */
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	/* category, action */
-+	{
-+		u8 category, action;
-+		category = RTW_WLAN_CATEGORY_SPECTRUM_MGMT;
-+		action = RTW_WLAN_ACTION_SPCT_CHL_SWITCH;
-+
-+		pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+		pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+	}
-+
-+	pframe = rtw_set_ie_ch_switch(pframe, &(pattrib->pktlen), 0, new_ch, 0);
-+	pframe = rtw_set_ie_secondary_ch_offset(pframe, &(pattrib->pktlen),
-+			hal_ch_offset_to_secondary_ch_offset(ch_offset));
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+}
-+
-+#ifdef CONFIG_IEEE80211W
-+void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type)
-+{
-+	u8	category = RTW_WLAN_CATEGORY_SA_QUERY;
-+	u16	reason_code;
-+	struct xmit_frame		*pmgntframe;
-+	struct pkt_attrib		*pattrib;
-+	u8					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	u16					*fctrl;
-+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct sta_info		*psta;
-+	struct sta_priv		*pstapriv = &padapter->stapriv;
-+	struct registry_priv		*pregpriv = &padapter->registrypriv;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		return;
-+
-+	RTW_INFO("%s, %04x\n", __FUNCTION__, tid);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL) {
-+		RTW_INFO("%s: alloc_mgtxmitframe fail\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+	pattrib->key_type = key_type;
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	if (raddr)
-+		_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
-+	else
-+		_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &category, &pattrib->pktlen);
-+	pframe = rtw_set_fixed_ie(pframe, 1, &action, &pattrib->pktlen);
-+
-+	switch (action) {
-+	case 0: /* SA Query req */
-+		pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&pmlmeext->sa_query_seq, &pattrib->pktlen);
-+		pmlmeext->sa_query_seq++;
-+		/* send sa query request to AP, AP should reply sa query response in 1 second */
-+		if (pattrib->key_type == IEEE80211W_RIGHT_KEY) {
-+			psta = rtw_get_stainfo(pstapriv, pwlanhdr->addr1);
-+			if (psta != NULL) {
-+				/* RTW_INFO("%s, %d, set dot11w_expire_timer\n", __func__, __LINE__); */
-+				_set_timer(&psta->dot11w_expire_timer, 1000);
-+			}
-+		}
-+		break;
-+
-+	case 1: /* SA Query rsp */
-+		tid = cpu_to_le16(tid);
-+		/* RTW_INFO("rtw_set_fixed_ie, %04x\n", tid); */
-+		pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&tid, &pattrib->pktlen);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+}
-+#endif /* CONFIG_IEEE80211W */
-+
-+/**
-+ * issue_action_ba - internal function to TX Block Ack action frame
-+ * @padapter: the adapter to TX
-+ * @raddr: receiver address
-+ * @action: Block Ack Action
-+ * @tid: tid
-+ * @size: the announced AMPDU buffer size. used by ADDBA_RESP
-+ * @status: status/reason code. used by ADDBA_RESP, DELBA
-+ * @initiator: if we are the initiator of AMPDU association. used by DELBA
-+ * @wait_ack: used xmit ack
-+ *
-+ * Returns:
-+ * _SUCCESS: No xmit ack is used or acked
-+ * _FAIL: not acked when using xmit ack
-+ */
-+static int issue_action_ba(_adapter *padapter, unsigned char *raddr, unsigned char action
-+		   , u8 tid, u8 size, u16 status, u8 initiator, int wait_ack)
-+{
-+	int ret = _FAIL;
-+	u8	category = RTW_WLAN_CATEGORY_BACK;
-+	u16	start_seq;
-+	u16	BA_para_set;
-+	u16	BA_timeout_value;
-+	u16	BA_starting_seqctrl;
-+	struct xmit_frame		*pmgntframe;
-+	struct pkt_attrib		*pattrib;
-+	u8					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	u16					*fctrl;
-+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct sta_info		*psta;
-+	struct sta_priv		*pstapriv = &padapter->stapriv;
-+	struct registry_priv		*pregpriv = &padapter->registrypriv;
-+
-+#ifdef CONFIG_80211N_HT
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		goto exit;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	/* _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); */
-+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+
-+	if (category == 3) {
-+		switch (action) {
-+		case RTW_WLAN_ACTION_ADDBA_REQ:
-+			do {
-+				pmlmeinfo->dialogToken++;
-+			} while (pmlmeinfo->dialogToken == 0);
-+			pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->dialogToken), &(pattrib->pktlen));
-+
-+#if defined(CONFIG_RTL8188E) && defined(CONFIG_SDIO_HCI)
-+			BA_para_set = (0x0802 | ((tid & 0xf) << 2)); /* immediate ack & 16 buffer size */
-+#else
-+			BA_para_set = (0x1002 | ((tid & 0xf) << 2)); /* immediate ack & 64 buffer size */
-+#endif
-+
-+#ifdef CONFIG_TX_AMSDU
-+			if (padapter->tx_amsdu >= 1) /* TX AMSDU  enabled */
-+				BA_para_set |= BIT(0);
-+			else /* TX AMSDU disabled */
-+				BA_para_set &= ~BIT(0);
-+#endif
-+			BA_para_set = cpu_to_le16(BA_para_set);
-+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));
-+
-+			/* BA_timeout_value = 0xffff; */ /* max: 65535 TUs(~ 65 ms) */
-+			BA_timeout_value = 5000;/* ~ 5ms */
-+			BA_timeout_value = cpu_to_le16(BA_timeout_value);
-+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_timeout_value)), &(pattrib->pktlen));
-+
-+			/* if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) */
-+			psta = rtw_get_stainfo(pstapriv, raddr);
-+			if (psta != NULL) {
-+				start_seq = (psta->sta_xmitpriv.txseq_tid[tid & 0x07] & 0xfff) + 1;
-+
-+				RTW_INFO("BA_starting_seqctrl = %d for TID=%d\n", start_seq, tid & 0x07);
-+
-+				psta->BA_starting_seqctrl[tid & 0x07] = start_seq;
-+
-+				BA_starting_seqctrl = start_seq << 4;
-+			}
-+
-+			BA_starting_seqctrl = cpu_to_le16(BA_starting_seqctrl);
-+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_starting_seqctrl)), &(pattrib->pktlen));
-+			break;
-+
-+		case RTW_WLAN_ACTION_ADDBA_RESP:
-+			pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->ADDBA_req.dialog_token), &(pattrib->pktlen));
-+			status = cpu_to_le16(status);
-+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&status), &(pattrib->pktlen));
-+
-+			BA_para_set = le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set);
-+
-+			BA_para_set &= ~IEEE80211_ADDBA_PARAM_TID_MASK;
-+			BA_para_set |= (tid << 2) & IEEE80211_ADDBA_PARAM_TID_MASK;
-+
-+			BA_para_set &= ~RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK;
-+			BA_para_set |= (size << 6) & RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK;
-+
-+			if (!padapter->registrypriv.wifi_spec) {
-+				if (pregpriv->rx_ampdu_amsdu == 0) /* disabled */
-+					BA_para_set &= ~BIT(0);
-+				else if (pregpriv->rx_ampdu_amsdu == 1) /* enabled */
-+					BA_para_set |= BIT(0);
-+			}
-+
-+			BA_para_set = cpu_to_le16(BA_para_set);
-+
-+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));
-+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(pmlmeinfo->ADDBA_req.BA_timeout_value)), &(pattrib->pktlen));
-+			break;
-+
-+		case RTW_WLAN_ACTION_DELBA:
-+			BA_para_set = 0;
-+			BA_para_set |= (tid << 12) & IEEE80211_DELBA_PARAM_TID_MASK;
-+			BA_para_set |= (initiator << 11) & IEEE80211_DELBA_PARAM_INITIATOR_MASK;
-+
-+			BA_para_set = cpu_to_le16(BA_para_set);
-+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));
-+			status = cpu_to_le16(status);
-+			pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(status)), &(pattrib->pktlen));
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	if (wait_ack)
-+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
-+	else {
-+		dump_mgntframe(padapter, pmgntframe);
-+		ret = _SUCCESS;
-+	}
-+
-+exit:
-+#endif /* CONFIG_80211N_HT */
-+	return ret;
-+}
-+
-+/**
-+ * issue_addba_req - TX ADDBA_REQ
-+ * @adapter: the adapter to TX
-+ * @ra: receiver address
-+ * @tid: tid
-+ */
-+inline void issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid)
-+{
-+	issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_REQ
-+			, tid
-+			, 0 /* unused */
-+			, 0 /* unused */
-+			, 0 /* unused */
-+			, _FALSE
-+		       );
-+	RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" tid=%u\n"
-+		 , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), tid);
-+
-+}
-+
-+/**
-+ * issue_addba_rsp - TX ADDBA_RESP
-+ * @adapter: the adapter to TX
-+ * @ra: receiver address
-+ * @tid: tid
-+ * @status: status code
-+ * @size: the announced AMPDU buffer size
-+ */
-+inline void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size)
-+{
-+	issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP
-+			, tid
-+			, size
-+			, status
-+			, 0 /* unused */
-+			, _FALSE
-+		       );
-+	RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" status=%u, tid=%u, size=%u\n"
-+		 , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size);
-+}
-+
-+/**
-+ * issue_addba_rsp_wait_ack - TX ADDBA_RESP and wait ack
-+ * @adapter: the adapter to TX
-+ * @ra: receiver address
-+ * @tid: tid
-+ * @status: status code
-+ * @size: the announced AMPDU buffer size
-+ * @try_cnt: the maximal TX count to try
-+ * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
-+ *           > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
-+ */
-+inline u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms)
-+{
-+	int ret = _FAIL;
-+	int i = 0;
-+	systime start = rtw_get_current_time();
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter)))
-+		goto exit;
-+
-+	do {
-+		ret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP
-+				      , tid
-+				      , size
-+				      , status
-+				      , 0 /* unused */
-+				      , _TRUE
-+				     );
-+
-+		i++;
-+
-+		if (RTW_CANNOT_RUN(adapter))
-+			break;
-+
-+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
-+			rtw_msleep_os(wait_ms);
-+
-+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
-+
-+	if (ret != _FAIL) {
-+		ret = _SUCCESS;
-+#ifndef DBG_XMIT_ACK
-+		/* goto exit; */
-+#endif
-+	}
-+
-+	if (try_cnt && wait_ms) {
-+		RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" status:=%u tid=%u size:%u%s, %d/%d in %u ms\n"
-+			, FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size
-+			, ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+/**
-+ * issue_del_ba - TX DELBA
-+ * @adapter: the adapter to TX
-+ * @ra: receiver address
-+ * @tid: tid
-+ * @reason: reason code
-+ * @initiator: if we are the initiator of AMPDU association. used by DELBA
-+ */
-+inline void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator)
-+{
-+	issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA
-+			, tid
-+			, 0 /* unused */
-+			, reason
-+			, initiator
-+			, _FALSE
-+		       );
-+	RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" reason=%u, tid=%u, initiator=%u\n"
-+		 , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator);
-+}
-+
-+/**
-+ * issue_del_ba_ex - TX DELBA with xmit ack options
-+ * @adapter: the adapter to TX
-+ * @ra: receiver address
-+ * @tid: tid
-+ * @reason: reason code
-+ * @initiator: if we are the initiator of AMPDU association. used by DELBA
-+ * @try_cnt: the maximal TX count to try
-+ * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
-+ *           > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
-+ */
-+int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator
-+		    , int try_cnt, int wait_ms)
-+{
-+	int ret = _FAIL;
-+	int i = 0;
-+	systime start = rtw_get_current_time();
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter)))
-+		goto exit;
-+
-+	do {
-+		ret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA
-+				      , tid
-+				      , 0 /* unused */
-+				      , reason
-+				      , initiator
-+				      , wait_ms > 0 ? _TRUE : _FALSE
-+				     );
-+
-+		i++;
-+
-+		if (RTW_CANNOT_RUN(adapter))
-+			break;
-+
-+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
-+			rtw_msleep_os(wait_ms);
-+
-+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
-+
-+	if (ret != _FAIL) {
-+		ret = _SUCCESS;
-+#ifndef DBG_XMIT_ACK
-+		/* goto exit; */
-+#endif
-+	}
-+
-+	if (try_cnt && wait_ms) {
-+		RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" reason=%u, tid=%u, initiator=%u%s, %d/%d in %u ms\n"
-+			, FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator
-+			, ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+	}
-+exit:
-+	return ret;
-+}
-+
-+void issue_action_BSSCoexistPacket(_adapter *padapter)
-+{
-+	_irqL	irqL;
-+	_list		*plist, *phead;
-+	unsigned char category, action;
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char				*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short			*fctrl;
-+	struct	wlan_network	*pnetwork = NULL;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	_queue		*queue	= &(pmlmepriv->scanned_queue);
-+	u8 InfoContent[16] = {0};
-+	u8 ICS[8][15];
-+#ifdef CONFIG_80211N_HT
-+	if ((pmlmepriv->num_FortyMHzIntolerant == 0) && (pmlmepriv->num_sta_no_ht == 0))
-+		return;
-+
-+	if (_TRUE == pmlmeinfo->bwmode_updated)
-+		return;
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		return;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+
-+	category = RTW_WLAN_CATEGORY_PUBLIC;
-+	action = ACT_PUBLIC_BSSCOEXIST;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+
-+	/* TODO calculate 40Mhz intolerant via ch and ch offset */
-+	/* if (pmlmepriv->num_FortyMHzIntolerant > 0) */
-+	{
-+		u8 iedata = 0;
-+
-+		iedata |= BIT(2);/* 20 MHz BSS Width Request */
-+		pframe = rtw_set_ie(pframe, EID_BSSCoexistence,  1, &iedata, &(pattrib->pktlen));
-+	}
-+
-+	/*  */
-+	_rtw_memset(ICS, 0, sizeof(ICS));
-+	if (pmlmepriv->num_sta_no_ht > 0) {
-+		int i;
-+
-+		_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+		phead = get_list_head(queue);
-+		plist = get_next(phead);
-+
-+		while (1) {
-+			int len;
-+			u8 *p;
-+			WLAN_BSSID_EX *pbss_network;
-+
-+			if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+				break;
-+
-+			pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+
-+			plist = get_next(plist);
-+
-+			pbss_network = (WLAN_BSSID_EX *)&pnetwork->network;
-+
-+			p = rtw_get_ie(pbss_network->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pbss_network->IELength - _FIXED_IE_LENGTH_);
-+			if ((p == NULL) || (len == 0)) { /* non-HT */
-+				if ((pbss_network->Configuration.DSConfig <= 0) || (pbss_network->Configuration.DSConfig > 14))
-+					continue;
-+
-+				ICS[0][pbss_network->Configuration.DSConfig] = 1;
-+
-+				if (ICS[0][0] == 0)
-+					ICS[0][0] = 1;
-+			}
-+
-+		}
-+
-+		_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+
-+		for (i = 0; i < 8; i++) {
-+			if (ICS[i][0] == 1) {
-+				int j, k = 0;
-+
-+				InfoContent[k] = i;
-+				/* SET_BSS_INTOLERANT_ELE_REG_CLASS(InfoContent,i); */
-+				k++;
-+
-+				for (j = 1; j <= 14; j++) {
-+					if (ICS[i][j] == 1) {
-+						if (k < 16) {
-+							InfoContent[k] = j; /* channel number */
-+							/* SET_BSS_INTOLERANT_ELE_CHANNEL(InfoContent+k, j); */
-+							k++;
-+						}
-+					}
-+				}
-+
-+				pframe = rtw_set_ie(pframe, EID_BSSIntolerantChlReport, k, InfoContent, &(pattrib->pktlen));
-+
-+			}
-+
-+		}
-+
-+
-+	}
-+
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+#endif /* CONFIG_80211N_HT */
-+}
-+
-+/* Spatial Multiplexing Powersave (SMPS) action frame */
-+int _issue_action_SM_PS(_adapter *padapter ,  unsigned char *raddr , u8 NewMimoPsMode ,  u8 wait_ack)
-+{
-+
-+	int ret = _FAIL;
-+	unsigned char category = RTW_WLAN_CATEGORY_HT;
-+	u8 action = RTW_WLAN_ACTION_HT_SM_PS;
-+	u8 sm_power_control = 0;
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+
-+	if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_DISABLED) {
-+		sm_power_control = sm_power_control  & ~(BIT(0)); /* SM Power Save Enable = 0 SM Power Save Disable */
-+	} else if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_STATIC) {
-+		sm_power_control = sm_power_control | BIT(0);    /* SM Power Save Enable = 1 SM Power Save Enable  */
-+		sm_power_control = sm_power_control & ~(BIT(1)); /* SM Mode = 0 Static Mode */
-+	} else if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_DYNAMIC) {
-+		sm_power_control = sm_power_control | BIT(0); /* SM Power Save Enable = 1 SM Power Save Enable  */
-+		sm_power_control = sm_power_control | BIT(1); /* SM Mode = 1 Dynamic Mode */
-+	} else
-+		return ret;
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		return ret;
-+
-+	RTW_INFO("%s, sm_power_control=%u, NewMimoPsMode=%u\n", __FUNCTION__ , sm_power_control , NewMimoPsMode);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return ret;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); /* RA */
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); /* DA = RA */
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	/* category, action */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(sm_power_control), &(pattrib->pktlen));
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	if (wait_ack)
-+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
-+	else {
-+		dump_mgntframe(padapter, pmgntframe);
-+		ret = _SUCCESS;
-+	}
-+
-+	if (ret != _SUCCESS)
-+		RTW_INFO("%s, ack to\n", __func__);
-+
-+	return ret;
-+}
-+
-+/*
-+ * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
-+ * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
-+ * try_cnt means the maximal TX count to try
-+ */
-+int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms)
-+{
-+	int ret = _FAIL;
-+	int i = 0;
-+	systime start = rtw_get_current_time();
-+
-+	if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
-+		goto exit;
-+
-+	do {
-+		ret = _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , wait_ms > 0 ? _TRUE : _FALSE);
-+
-+		i++;
-+
-+		if (RTW_CANNOT_RUN(padapter))
-+			break;
-+
-+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
-+			rtw_msleep_os(wait_ms);
-+
-+	} while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0)));
-+
-+	if (ret != _FAIL) {
-+		ret = _SUCCESS;
-+#ifndef DBG_XMIT_ACK
-+		goto exit;
-+#endif
-+	}
-+
-+	if (try_cnt && wait_ms) {
-+		if (raddr)
-+			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", %s , %d/%d in %u ms\n",
-+				 FUNC_ADPT_ARG(padapter), MAC_ARG(raddr),
-+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+		else
-+			RTW_INFO(FUNC_ADPT_FMT", %s , %d/%d in %u ms\n",
-+				 FUNC_ADPT_ARG(padapter),
-+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+	}
-+exit:
-+
-+	return ret;
-+}
-+
-+int issue_action_SM_PS(_adapter *padapter ,  unsigned char *raddr , u8 NewMimoPsMode)
-+{
-+	RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(raddr));
-+	return _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , _FALSE);
-+}
-+
-+/**
-+ * _send_delba_sta_tid - Cancel the AMPDU association for the specific @sta, @tid
-+ * @adapter: the adapter to which @sta belongs
-+ * @initiator: if we are the initiator of AMPDU association
-+ * @sta: the sta to be checked
-+ * @tid: the tid to be checked
-+ * @force: cancel and send DELBA even when no AMPDU association is setup
-+ * @wait_ack: send delba with xmit ack (valid when initiator == 0)
-+ *
-+ * Returns:
-+ * _FAIL if sta is NULL
-+ * when initiator is 1, always _SUCCESS
-+ * when initiator is 0, _SUCCESS if DELBA is acked
-+ */
-+static unsigned int _send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid
-+					, u8 force, int wait_ack)
-+{
-+	int ret = _SUCCESS;
-+
-+	if (sta == NULL) {
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	if (initiator == 0) {
-+		/* recipient */
-+		if (force || sta->recvreorder_ctrl[tid].enable == _TRUE) {
-+			u8 ampdu_size_bak = sta->recvreorder_ctrl[tid].ampdu_size;
-+
-+			sta->recvreorder_ctrl[tid].enable = _FALSE;
-+			sta->recvreorder_ctrl[tid].ampdu_size = RX_AMPDU_SIZE_INVALID;
-+
-+			if (rtw_del_rx_ampdu_test_trigger_no_tx_fail())
-+				ret = _FAIL;
-+			else if (wait_ack)
-+				ret = issue_del_ba_ex(adapter, sta->cmn.mac_addr, tid, 37, initiator, 3, 1);
-+			else
-+				issue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator);
-+
-+			if (ret == _FAIL && sta->recvreorder_ctrl[tid].enable == _FALSE)
-+				sta->recvreorder_ctrl[tid].ampdu_size = ampdu_size_bak;
-+		}
-+	} else if (initiator == 1) {
-+		/* originator */
-+#ifdef CONFIG_80211N_HT
-+		if (force || sta->htpriv.agg_enable_bitmap & BIT(tid)) {
-+			sta->htpriv.agg_enable_bitmap &= ~BIT(tid);
-+			sta->htpriv.candidate_tid_bitmap &= ~BIT(tid);
-+			issue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator);
-+		}
-+#endif
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+inline unsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid
-+				       , u8 force)
-+{
-+	return _send_delba_sta_tid(adapter, initiator, sta, tid, force, 0);
-+}
-+
-+inline unsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid
-+		, u8 force)
-+{
-+	return _send_delba_sta_tid(adapter, initiator, sta, tid, force, 1);
-+}
-+
-+unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr)
-+{
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *psta = NULL;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u16 tid;
-+
-+	if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
-+		if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS))
-+			return _SUCCESS;
-+
-+	psta = rtw_get_stainfo(pstapriv, addr);
-+	if (psta == NULL)
-+		return _SUCCESS;
-+
-+#if 0
-+	RTW_INFO("%s:%s\n", __func__, (initiator == 0) ? "RX_DIR" : "TX_DIR");
-+	if (initiator == 1) /* originator */
-+		RTW_INFO("tx agg_enable_bitmap(0x%08x)\n", psta->htpriv.agg_enable_bitmap);
-+#endif
-+
-+	for (tid = 0; tid < TID_NUM; tid++)
-+		send_delba_sta_tid(padapter, initiator, psta, tid, 0);
-+
-+	return _SUCCESS;
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+unsigned int send_beacon(_adapter *padapter)
-+{
-+#if defined(CONFIG_PCI_HCI) && !defined(CONFIG_PCI_BCN_POLLING)
-+	#ifdef CONFIG_FW_HANDLE_TXBCN
-+	u8 vap_id = padapter->vap_id;
-+
-+	/* bypass TX BCN because vap_id is invalid*/
-+	if (vap_id == CONFIG_LIMITED_AP_NUM)
-+		return _SUCCESS;
-+	#endif
-+
-+	/* bypass TX BCN queue because op ch is switching/waiting */
-+	if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)
-+		|| IS_CH_WAITING(adapter_to_rfctl(padapter))
-+	)
-+		return _SUCCESS;
-+
-+	/* RTW_INFO("%s\n", __FUNCTION__); */
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
-+
-+	/* 8192EE Port select for Beacon DL */
-+	rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
-+	#ifdef CONFIG_FW_HANDLE_TXBCN
-+	rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);
-+	#endif
-+
-+	issue_beacon(padapter, 0);
-+
-+	#ifdef CONFIG_FW_HANDLE_TXBCN
-+	vap_id = 0xFF;
-+	rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);
-+	#endif
-+
-+	#ifdef RTL8814AE_SW_BCN
-+	if (GET_HAL_DATA(padapter)->bCorrectBCN != 0)
-+		RTW_INFO("%s, line%d, Warnning, pHalData->bCorrectBCN != 0\n", __func__, __LINE__);
-+	GET_HAL_DATA(padapter)->bCorrectBCN = 1;
-+	#endif
-+
-+	return _SUCCESS;
-+#endif
-+
-+/* CONFIG_PCI_BCN_POLLING is for pci interface beacon polling mode */
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)|| defined(CONFIG_PCI_BCN_POLLING) 
-+	u8 bxmitok = _FALSE;
-+	int issue = 0;
-+	int poll = 0;
-+	systime start = rtw_get_current_time();
-+	#ifdef CONFIG_FW_HANDLE_TXBCN
-+	u8 vap_id = padapter->vap_id;
-+
-+	/* bypass TX BCN because vap_id is invalid*/
-+	if (vap_id == CONFIG_LIMITED_AP_NUM)
-+		return _SUCCESS;
-+	#endif
-+
-+	/* bypass TX BCN queue because op ch is switching/waiting */
-+	if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)
-+		|| IS_CH_WAITING(adapter_to_rfctl(padapter))
-+	)
-+		return _SUCCESS;
-+
-+	#if defined(CONFIG_USB_HCI)
-+	#if defined(CONFIG_RTL8812A)
-+	if (IS_FULL_SPEED_USB(padapter)) {
-+		issue_beacon(padapter, 300);
-+		bxmitok = _TRUE;
-+	} else
-+	#endif
-+	#endif
-+	{
-+		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
-+		#ifdef CONFIG_FW_HANDLE_TXBCN
-+		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);
-+		#endif
-+		do {
-+			#if defined(CONFIG_PCI_BCN_POLLING) 
-+			issue_beacon(padapter, 0);
-+			#else
-+			issue_beacon(padapter, 100);
-+			#endif
-+			issue++;
-+			do {
-+				#if defined(CONFIG_PCI_BCN_POLLING) 
-+				rtw_msleep_os(1);
-+				#else
-+				rtw_yield_os();
-+				#endif
-+				rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bxmitok));
-+				poll++;
-+			} while ((poll % 10) != 0 && _FALSE == bxmitok && !RTW_CANNOT_RUN(padapter));
-+			#if defined(CONFIG_PCI_BCN_POLLING) 
-+			rtw_hal_unmap_beacon_icf(padapter);
-+			#endif
-+		} while (bxmitok == _FALSE && (issue < 100) && !RTW_CANNOT_RUN(padapter));
-+		#ifdef CONFIG_FW_HANDLE_TXBCN
-+		vap_id = 0xFF;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id);
-+		#endif
-+	}
-+	if (RTW_CANNOT_RUN(padapter))
-+		return _FAIL;
-+
-+
-+	if (_FALSE == bxmitok) {
-+		RTW_INFO("%s fail! %u ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
-+		#ifdef CONFIG_BCN_RECOVERY
-+		GET_HAL_DATA(padapter)->issue_bcn_fail++;
-+		#endif  /*CONFIG_BCN_RECOVERY*/
-+		return _FAIL;
-+	} else {
-+		u32 passing_time = rtw_get_passing_time_ms(start);
-+
-+		if (passing_time > 100 || issue > 3)
-+			RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start));
-+		else if (0)
-+			RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start));
-+
-+		#ifdef CONFIG_FW_CORRECT_BCN
-+		rtw_hal_fw_correct_bcn(padapter);
-+		#endif
-+		return _SUCCESS;
-+	}
-+
-+#endif /*defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)*/
-+
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+/****************************************************************************
-+
-+Following are some utitity fuctions for WiFi MLME
-+
-+*****************************************************************************/
-+
-+BOOLEAN IsLegal5GChannel(
-+	PADAPTER			Adapter,
-+	u8			channel)
-+{
-+
-+	int i = 0;
-+	u8 Channel_5G[45] = {36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
-+		60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,
-+		124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159,
-+			     161, 163, 165
-+			    };
-+	for (i = 0; i < sizeof(Channel_5G); i++)
-+		if (channel == Channel_5G[i])
-+			return _TRUE;
-+	return _FALSE;
-+}
-+
-+/* collect bss info from Beacon and Probe request/response frames. */
-+u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid)
-+{
-+	int	i;
-+	sint len;
-+	u8	*p;
-+	u8	rf_path;
-+	u16	val16, subtype;
-+	u8	*pframe = precv_frame->u.hdr.rx_data;
-+	u32	packet_len = precv_frame->u.hdr.len;
-+	u8 ie_offset;
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+
-+	len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	if (len > MAX_IE_SZ) {
-+		/* RTW_INFO("IE too long for survey event\n"); */
-+		return _FAIL;
-+	}
-+
-+	_rtw_memset(bssid, 0, sizeof(WLAN_BSSID_EX));
-+
-+	subtype = get_frame_sub_type(pframe);
-+
-+	if (subtype == WIFI_BEACON) {
-+		bssid->Reserved[0] = BSS_TYPE_BCN;
-+		ie_offset = _BEACON_IE_OFFSET_;
-+	} else {
-+		/* FIXME : more type */
-+		if (subtype == WIFI_PROBERSP) {
-+			ie_offset = _PROBERSP_IE_OFFSET_;
-+			bssid->Reserved[0] = BSS_TYPE_PROB_RSP;
-+		} else if (subtype == WIFI_PROBEREQ) {
-+			ie_offset = _PROBEREQ_IE_OFFSET_;
-+			bssid->Reserved[0] = BSS_TYPE_PROB_REQ;
-+		} else {
-+			bssid->Reserved[0] = BSS_TYPE_UNDEF;
-+			ie_offset = _FIXED_IE_LENGTH_;
-+		}
-+	}
-+
-+	bssid->Length = sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + len;
-+
-+	/* below is to copy the information element */
-+	bssid->IELength = len;
-+	_rtw_memcpy(bssid->IEs, (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)), bssid->IELength);
-+
-+	/* get the signal strength */
-+	/* bssid->Rssi = precv_frame->u.hdr.attrib.SignalStrength; */ /* 0-100 index. */
-+	bssid->Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power; /* in dBM.raw data */
-+	bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.signal_quality;/* in percentage */
-+	bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.signal_strength;/* in percentage */
-+
-+	/* get rx_snr */
-+	if (precv_frame->u.hdr.attrib.data_rate >= DESC_RATE11M) {
-+		bssid->PhyInfo.is_cck_rate = 0;
-+		for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++)
-+			bssid->PhyInfo.rx_snr[rf_path] =
-+				precv_frame->u.hdr.attrib.phy_info.rx_snr[rf_path];
-+	} else
-+		bssid->PhyInfo.is_cck_rate = 1;
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &(bssid->PhyInfo.Optimum_antenna), NULL);
-+#endif
-+
-+	/* checking SSID */
-+	p = rtw_get_ie(bssid->IEs + ie_offset, _SSID_IE_, &len, bssid->IELength - ie_offset);
-+	if (p == NULL) {
-+		RTW_INFO("marc: cannot find SSID for survey event\n");
-+		return _FAIL;
-+	}
-+
-+	if (*(p + 1)) {
-+		if (len > NDIS_802_11_LENGTH_SSID) {
-+			RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len);
-+			return _FAIL;
-+		}
-+		_rtw_memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1));
-+		bssid->Ssid.SsidLength = *(p + 1);
-+	} else
-+		bssid->Ssid.SsidLength = 0;
-+
-+	_rtw_memset(bssid->SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX);
-+
-+	/* checking rate info... */
-+	i = 0;
-+	p = rtw_get_ie(bssid->IEs + ie_offset, _SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset);
-+	if (p != NULL) {
-+		if (len > NDIS_802_11_LENGTH_RATES_EX) {
-+			RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len);
-+			return _FAIL;
-+		}
-+#ifdef CONFIG_CHECK_SPECIFIC_IE_CONTENT
-+		if (rtw_validate_value(_SUPPORTEDRATES_IE_, p+2, len) == _FALSE) {
-+			rtw_absorb_ssid_ifneed(padapter, bssid, pframe);
-+			RTW_DBG_DUMP("Invalidated Support Rate IE --", p, len+2);
-+			return _FAIL;
-+		}
-+#endif /* #ifdef CONFIG_CHECK_SPECIFIC_IE_CONTENT */
-+		_rtw_memcpy(bssid->SupportedRates, (p + 2), len);
-+		i = len;
-+	}
-+
-+	p = rtw_get_ie(bssid->IEs + ie_offset, _EXT_SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset);
-+	if (p != NULL) {
-+		if (len > (NDIS_802_11_LENGTH_RATES_EX - i)) {
-+			RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len);
-+			return _FAIL;
-+		}
-+#ifdef CONFIG_CHECK_SPECIFIC_IE_CONTENT
-+		if (rtw_validate_value(_EXT_SUPPORTEDRATES_IE_, p+2, len) == _FALSE) {
-+			rtw_absorb_ssid_ifneed(padapter, bssid, pframe);
-+			RTW_DBG_DUMP("Invalidated EXT Support Rate IE --", p, len+2);
-+			return _FAIL;
-+		}
-+#endif /* #ifdef CONFIG_CHECK_SPECIFIC_IE_CONTENT */
-+		_rtw_memcpy(bssid->SupportedRates + i, (p + 2), len);
-+	}
-+
-+#ifdef CONFIG_P2P
-+	if (subtype == WIFI_PROBEREQ) {
-+		u8 *p2p_ie;
-+		u32	p2p_ielen;
-+		/* Set Listion Channel */
-+		p2p_ie = rtw_get_p2p_ie(bssid->IEs, bssid->IELength, NULL, &p2p_ielen);
-+		if (p2p_ie) {
-+			u32	attr_contentlen = 0;
-+			u8 listen_ch[5] = { 0x00 };
-+
-+			rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, listen_ch, &attr_contentlen);
-+			bssid->Configuration.DSConfig = listen_ch[4];
-+		} else {
-+			/* use current channel */
-+			bssid->Configuration.DSConfig = padapter->mlmeextpriv.cur_channel;
-+			RTW_INFO("%s()-%d: Cannot get p2p_ie. set DSconfig to op_ch(%d)\n", __FUNCTION__, __LINE__, bssid->Configuration.DSConfig);
-+		}
-+
-+		/* FIXME */
-+		bssid->InfrastructureMode = Ndis802_11Infrastructure;
-+		_rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN);
-+		bssid->Privacy = 1;
-+		return _SUCCESS;
-+	}
-+#endif /* CONFIG_P2P */
-+
-+	if (bssid->IELength < 12)
-+		return _FAIL;
-+
-+	/* Checking for DSConfig */
-+	p = rtw_get_ie(bssid->IEs + ie_offset, _DSSET_IE_, &len, bssid->IELength - ie_offset);
-+
-+	bssid->Configuration.DSConfig = 0;
-+	bssid->Configuration.Length = 0;
-+
-+	if (p)
-+		bssid->Configuration.DSConfig = *(p + 2);
-+	else {
-+		/* In 5G, some ap do not have DSSET IE */
-+		/* checking HT info for channel */
-+		p = rtw_get_ie(bssid->IEs + ie_offset, _HT_ADD_INFO_IE_, &len, bssid->IELength - ie_offset);
-+		if (p) {
-+			struct HT_info_element *HT_info = (struct HT_info_element *)(p + 2);
-+			bssid->Configuration.DSConfig = HT_info->primary_channel;
-+		} else {
-+			/* use current channel */
-+			bssid->Configuration.DSConfig = rtw_get_oper_ch(padapter);
-+		}
-+	}
-+
-+	_rtw_memcpy(&bssid->Configuration.BeaconPeriod, rtw_get_beacon_interval_from_ie(bssid->IEs), 2);
-+	bssid->Configuration.BeaconPeriod = le32_to_cpu(bssid->Configuration.BeaconPeriod);
-+
-+	val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid);
-+
-+	if ((val16 & 0x03) == cap_ESS) {
-+		bssid->InfrastructureMode = Ndis802_11Infrastructure;
-+		_rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN);
-+	} else if ((val16 & 0x03) == cap_IBSS){
-+		bssid->InfrastructureMode = Ndis802_11IBSS;
-+		_rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);
-+	} else if ((val16 & 0x03) == 0x00){
-+		u8 *mesh_id_ie, *mesh_conf_ie;
-+		sint mesh_id_ie_len, mesh_conf_ie_len;
-+
-+		mesh_id_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_ID, &mesh_id_ie_len, bssid->IELength - ie_offset);
-+		mesh_conf_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_CONFIG, &mesh_conf_ie_len, bssid->IELength - ie_offset);
-+		if (mesh_id_ie || mesh_conf_ie) {
-+			if (!mesh_id_ie) {
-+				RTW_INFO("cannot find Mesh ID for survey event\n");
-+				return _FAIL;
-+			}
-+			if (mesh_id_ie_len) {
-+				if (mesh_id_ie_len > NDIS_802_11_LENGTH_SSID) {
-+					RTW_INFO("Mesh ID too long (%d) for survey event\n", mesh_id_ie_len);
-+					return _FAIL;
-+				}
-+				_rtw_memcpy(bssid->mesh_id.Ssid, (mesh_id_ie + 2), mesh_id_ie_len);
-+				bssid->mesh_id.SsidLength = mesh_id_ie_len;
-+			} else
-+				bssid->mesh_id.SsidLength = 0;
-+
-+			if (!mesh_conf_ie) {
-+				RTW_INFO("cannot find Mesh config for survey event\n");
-+				return _FAIL;
-+			}
-+			if (mesh_conf_ie_len != 7) {
-+				RTW_INFO("invalid Mesh conf IE len (%d) for survey event\n", mesh_conf_ie_len);
-+				return _FAIL;
-+			}
-+
-+			bssid->InfrastructureMode = Ndis802_11_mesh;
-+			_rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);
-+		} else {
-+			/* default cases */
-+			bssid->InfrastructureMode = Ndis802_11IBSS;
-+			_rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);
-+		}
-+	}
-+
-+	if (val16 & BIT(4))
-+		bssid->Privacy = 1;
-+	else
-+		bssid->Privacy = 0;
-+
-+	bssid->Configuration.ATIMWindow = 0;
-+
-+	/* 20/40 BSS Coexistence check */
-+	if ((pregistrypriv->wifi_spec == 1) && (_FALSE == pmlmeinfo->bwmode_updated)) {
-+		struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+#ifdef CONFIG_80211N_HT
-+		p = rtw_get_ie(bssid->IEs + ie_offset, _HT_CAPABILITY_IE_, &len, bssid->IELength - ie_offset);
-+		if (p && len > 0) {
-+			struct HT_caps_element	*pHT_caps;
-+			pHT_caps = (struct HT_caps_element *)(p + 2);
-+
-+			if (pHT_caps->u.HT_cap_element.HT_caps_info & BIT(14))
-+				pmlmepriv->num_FortyMHzIntolerant++;
-+		} else
-+			pmlmepriv->num_sta_no_ht++;
-+#endif /* CONFIG_80211N_HT */
-+
-+	}
-+
-+#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) & 1
-+	if (strcmp(bssid->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) {
-+		RTW_INFO("Receiving %s("MAC_FMT", DSConfig:%u) from ch%u with ss:%3u, sq:%3u, RawRSSI:%3ld\n"
-+			, bssid->Ssid.Ssid, MAC_ARG(bssid->MacAddress), bssid->Configuration.DSConfig
-+			 , rtw_get_oper_ch(padapter)
-+			, bssid->PhyInfo.SignalStrength, bssid->PhyInfo.SignalQuality, bssid->Rssi
-+			);
-+	}
-+#endif
-+
-+	/* mark bss info receving from nearby channel as SignalQuality 101 */
-+	if (bssid->Configuration.DSConfig != rtw_get_oper_ch(padapter))
-+		bssid->PhyInfo.SignalQuality = 101;
-+
-+#ifdef CONFIG_RTW_80211K
-+	p = rtw_get_ie(bssid->IEs + ie_offset, _EID_RRM_EN_CAP_IE_, &len, bssid->IELength - ie_offset);
-+	if (p)
-+		_rtw_memcpy(bssid->PhyInfo.rm_en_cap, (p + 2), *(p + 1));
-+
-+	/* save freerun counter */
-+	bssid->PhyInfo.free_cnt = precv_frame->u.hdr.attrib.free_cnt;
-+#endif
-+	return _SUCCESS;
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+void start_create_ibss(_adapter *padapter)
-+{
-+	unsigned short	caps;
-+	u8	val8;
-+	u8	join_type;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
-+	u8 doiqk = _FALSE;
-+	pmlmeext->cur_channel = (u8)pnetwork->Configuration.DSConfig;
-+	pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork);
-+
-+	/* update wireless mode */
-+	update_wireless_mode(padapter);
-+
-+	/* udpate capability */
-+	caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork);
-+	update_capinfo(padapter, caps);
-+	if (caps & cap_IBSS) { /* adhoc master */
-+		/* set_opmode_cmd(padapter, adhoc); */ /* removed */
-+
-+		val8 = 0xcf;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
-+
-+		doiqk = _TRUE;
-+		rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
-+
-+		/* switch channel */
-+		set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+
-+		doiqk = _FALSE;
-+		rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
-+
-+		beacon_timing_control(padapter);
-+
-+		/* set msr to WIFI_FW_ADHOC_STATE */
-+		pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
-+		Set_MSR(padapter, (pmlmeinfo->state & 0x3));
-+
-+		/* issue beacon */
-+		if (send_beacon(padapter) == _FAIL) {
-+
-+			report_join_res(padapter, -1, WLAN_STATUS_UNSPECIFIED_FAILURE);
-+			pmlmeinfo->state = WIFI_FW_NULL_STATE;
-+		} else {
-+			rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);
-+			rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
-+			join_type = 0;
-+			rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
-+
-+			rtw_btcoex_connect_notify(padapter, join_type);
-+
-+			report_join_res(padapter, 1, WLAN_STATUS_SUCCESS);
-+			pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
-+			rtw_indicate_connect(padapter);
-+		}
-+	} else {
-+		RTW_INFO("start_create_ibss, invalid cap:%x\n", caps);
-+		return;
-+	}
-+	/* update bc/mc sta_info */
-+	update_bmc_sta(padapter);
-+
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+void start_clnt_join(_adapter *padapter)
-+{
-+	unsigned short	caps;
-+	u8	val8;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
-+	int beacon_timeout;
-+	u8 ASIX_ID[] = {0x00, 0x0E, 0xC6};
-+
-+	/* update wireless mode */
-+	update_wireless_mode(padapter);
-+
-+	/* udpate capability */
-+	caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork);
-+	update_capinfo(padapter, caps);
-+
-+	/* check if sta is ASIX peer and fix IOT issue if it is. */
-+	if (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) , ASIX_ID , 3)) {
-+		u8 iot_flag = _TRUE;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag));
-+	}
-+
-+	if (caps & cap_ESS) {
-+		Set_MSR(padapter, WIFI_FW_STATION_STATE);
-+
-+		val8 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) ? 0xcc : 0xcf;
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+		if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) {
-+			/* Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey. */
-+			val8 = 0x4c;
-+		}
-+#endif
-+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
-+
-+#ifdef CONFIG_DEAUTH_BEFORE_CONNECT
-+		/* Because of AP's not receiving deauth before */
-+		/* AP may: 1)not response auth or 2)deauth us after link is complete */
-+		/* issue deauth before issuing auth to deal with the situation */
-+
-+		/*	Commented by Albert 2012/07/21 */
-+		/*	For the Win8 P2P connection, it will be hard to have a successful connection if this Wi-Fi doesn't connect to it. */
-+		{
-+#ifdef CONFIG_P2P
-+			_queue *queue = &(padapter->mlmepriv.scanned_queue);
-+			_list	*head = get_list_head(queue);
-+			_list *pos = get_next(head);
-+			struct wlan_network *scanned = NULL;
-+			u8 ie_offset = 0;
-+			_irqL irqL;
-+			bool has_p2p_ie = _FALSE;
-+
-+			_enter_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL);
-+
-+			for (pos = get_next(head); !rtw_end_of_queue_search(head, pos); pos = get_next(pos)) {
-+
-+				scanned = LIST_CONTAINOR(pos, struct wlan_network, list);
-+
-+				if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE
-+				    && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE
-+				   ) {
-+					ie_offset = (scanned->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12);
-+					if (rtw_get_p2p_ie(scanned->network.IEs + ie_offset, scanned->network.IELength - ie_offset, NULL, NULL))
-+						has_p2p_ie = _TRUE;
-+					break;
-+				}
-+			}
-+
-+			_exit_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL);
-+
-+			if (scanned == NULL || rtw_end_of_queue_search(head, pos) || has_p2p_ie == _FALSE)
-+#endif /* CONFIG_P2P */
-+				/* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */
-+				issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100);
-+		}
-+#endif /* CONFIG_DEAUTH_BEFORE_CONNECT */
-+
-+		/* here wait for receiving the beacon to start auth */
-+		/* and enable a timer */
-+		beacon_timeout = decide_wait_for_beacon_timeout(pmlmeinfo->bcn_interval);
-+		set_link_timer(pmlmeext, beacon_timeout);
-+		_set_timer(&padapter->mlmepriv.assoc_timer,
-+			(REAUTH_TO * REAUTH_LIMIT) + (REASSOC_TO * REASSOC_LIMIT) + beacon_timeout);
-+
-+#ifdef CONFIG_RTW_80211R
-+		if (rtw_ft_roam(padapter)) {
-+			rtw_ft_start_clnt_join(padapter);
-+		} else
-+#endif
-+		{
-+			rtw_sta_linking_test_set_start();
-+			pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE;
-+		}
-+	} else if (caps & cap_IBSS) { /* adhoc client */
-+		Set_MSR(padapter, WIFI_FW_ADHOC_STATE);
-+
-+		val8 = 0xcf;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
-+
-+		beacon_timing_control(padapter);
-+
-+		pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
-+
-+		report_join_res(padapter, 1, WLAN_STATUS_SUCCESS);
-+	} else {
-+		/* RTW_INFO("marc: invalid cap:%x\n", caps); */
-+		return;
-+	}
-+
-+}
-+
-+void start_clnt_auth(_adapter *padapter)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	_cancel_timer_ex(&pmlmeext->link_timer);
-+
-+	pmlmeinfo->state &= (~WIFI_FW_AUTH_NULL);
-+	pmlmeinfo->state |= WIFI_FW_AUTH_STATE;
-+
-+	pmlmeinfo->auth_seq = 1;
-+	pmlmeinfo->reauth_count = 0;
-+	pmlmeinfo->reassoc_count = 0;
-+	pmlmeinfo->link_count = 0;
-+	pmlmeext->retry = 0;
-+
-+#ifdef CONFIG_RTW_80211R
-+	if (rtw_ft_roam(padapter)) {
-+		rtw_ft_set_status(padapter, RTW_FT_AUTHENTICATING_STA);
-+		RTW_PRINT("start ft auth\n");
-+	} else
-+#endif
-+		RTW_PRINT("start auth\n");
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE)) {
-+		if (rtw_cached_pmkid(padapter, get_my_bssid(&pmlmeinfo->network)) != -1) {
-+			RTW_INFO("SAE: PMKSA cache entry found\n");
-+			padapter->securitypriv.auth_alg = WLAN_AUTH_OPEN;
-+			goto no_external_auth;
-+		}
-+
-+		RTW_PRINT("SAE: start external auth\n");
-+		rtw_cfg80211_external_auth_request(padapter, NULL);
-+		return;
-+	}
-+no_external_auth:
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+	issue_auth(padapter, NULL, 0);
-+
-+	set_link_timer(pmlmeext, REAUTH_TO);
-+
-+}
-+
-+
-+void start_clnt_assoc(_adapter *padapter)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	_cancel_timer_ex(&pmlmeext->link_timer);
-+
-+	pmlmeinfo->state &= (~(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE));
-+	pmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE);
-+
-+#ifdef CONFIG_RTW_80211R
-+	if (rtw_ft_roam(padapter)
-+	#ifdef CONFIG_RTW_WNM
-+		|| rtw_wnm_btm_reassoc_req(padapter)
-+	#endif
-+	)
-+		issue_reassocreq(padapter);
-+	else
-+#endif
-+		issue_assocreq(padapter);
-+
-+	set_link_timer(pmlmeext, REASSOC_TO);
-+}
-+
-+unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if (!(_rtw_memcmp(MacAddr, get_my_bssid(&pmlmeinfo->network), ETH_ALEN)))
-+		return _SUCCESS;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	rtw_rson_do_disconnect(padapter);
-+#endif
-+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {
-+		if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {
-+			if (report_del_sta_event(padapter, MacAddr, reason, _TRUE, locally_generated) != _FAIL)
-+				pmlmeinfo->state = WIFI_FW_NULL_STATE;
-+		} else if (pmlmeinfo->state & WIFI_FW_LINKING_STATE) {
-+			if (report_join_res(padapter, -2, reason) != _FAIL)
-+				pmlmeinfo->state = WIFI_FW_NULL_STATE;
-+		} else
-+			RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(padapter));
-+#ifdef CONFIG_RTW_80211R
-+		rtw_ft_roam_status_reset(padapter);
-+#endif
-+#ifdef CONFIG_RTW_WNM
-+		rtw_wnm_reset_btm_state(padapter);
-+#endif
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+static void rtw_hidden_ssid_bss_count(_adapter *adapter, WLAN_BSSID_EX *bss)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	RT_CHANNEL_INFO *chset = rfctl->channel_set;
-+	int chset_idx;
-+
-+	if (bss->InfrastructureMode != Ndis802_11Infrastructure)
-+		return;
-+
-+	if (!hidden_ssid_ap(bss))
-+		return;
-+
-+	chset_idx = rtw_chset_search_ch(chset, bss->Configuration.DSConfig);
-+	if (chset_idx < 0)
-+		return;
-+	
-+	chset[chset_idx].hidden_bss_cnt++;
-+}
-+
-+/****************************************************************************
-+
-+Following are the functions to report events
-+
-+*****************************************************************************/
-+
-+void report_survey_event(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	struct cmd_obj *pcmd_obj;
-+	u8 *pevtcmd;
-+	u32 cmdsz;
-+	struct survey_event *psurvey_evt;
-+	struct rtw_evt_header *evt_hdr;
-+	struct mlme_ext_priv *pmlmeext;
-+	struct cmd_priv *pcmdpriv;
-+	/* u8 *pframe = precv_frame->u.hdr.rx_data; */
-+	/* uint len = precv_frame->u.hdr.len; */
-+
-+	if (!padapter)
-+		return;
-+
-+	pmlmeext = &padapter->mlmeextpriv;
-+	pcmdpriv = &padapter->cmdpriv;
-+
-+	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (pcmd_obj == NULL)
-+		return;
-+
-+	cmdsz = (sizeof(struct survey_event) + sizeof(struct rtw_evt_header));
-+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
-+	if (pevtcmd == NULL) {
-+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
-+		return;
-+	}
-+
-+	_rtw_init_listhead(&pcmd_obj->list);
-+
-+	pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
-+	pcmd_obj->cmdsz = cmdsz;
-+	pcmd_obj->parmbuf = pevtcmd;
-+
-+	pcmd_obj->rsp = NULL;
-+	pcmd_obj->rspsz  = 0;
-+
-+	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
-+	evt_hdr->len = sizeof(struct survey_event);
-+	evt_hdr->id = EVT_SURVEY;
-+	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
-+
-+	psurvey_evt = (struct survey_event *)(pevtcmd + sizeof(struct rtw_evt_header));
-+
-+	if (collect_bss_info(padapter, precv_frame, (WLAN_BSSID_EX *)&psurvey_evt->bss) == _FAIL) {
-+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
-+		rtw_mfree((u8 *)pevtcmd, cmdsz);
-+		return;
-+	}
-+
-+	rtw_hidden_ssid_bss_count(padapter, &psurvey_evt->bss);
-+
-+	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
-+
-+	pmlmeext->sitesurvey_res.bss_cnt++;
-+
-+	return;
-+
-+}
-+
-+/*
-+* @acs: aim to trigger channel selection
-+*/
-+void report_surveydone_event(_adapter *padapter, bool acs)
-+{
-+	struct cmd_obj *pcmd_obj;
-+	u8	*pevtcmd;
-+	u32 cmdsz;
-+	struct surveydone_event *psurveydone_evt;
-+	struct rtw_evt_header *evt_hdr;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+
-+	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (pcmd_obj == NULL)
-+		return;
-+
-+	cmdsz = (sizeof(struct surveydone_event) + sizeof(struct rtw_evt_header));
-+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
-+	if (pevtcmd == NULL) {
-+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
-+		return;
-+	}
-+
-+	_rtw_init_listhead(&pcmd_obj->list);
-+
-+	pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
-+	pcmd_obj->cmdsz = cmdsz;
-+	pcmd_obj->parmbuf = pevtcmd;
-+
-+	pcmd_obj->rsp = NULL;
-+	pcmd_obj->rspsz  = 0;
-+
-+	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
-+	evt_hdr->len = sizeof(struct surveydone_event);
-+	evt_hdr->id = EVT_SURVEY_DONE;
-+	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
-+
-+	psurveydone_evt = (struct surveydone_event *)(pevtcmd + sizeof(struct rtw_evt_header));
-+	psurveydone_evt->bss_cnt = pmlmeext->sitesurvey_res.bss_cnt;
-+	psurveydone_evt->activate_ch_cnt = pmlmeext->sitesurvey_res.activate_ch_cnt;
-+	psurveydone_evt->acs = acs;
-+
-+	RTW_INFO("survey done event(%x) band:%d for "ADPT_FMT"\n", psurveydone_evt->bss_cnt, padapter->setband, ADPT_ARG(padapter));
-+
-+	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
-+
-+	return;
-+
-+}
-+
-+u32 report_join_res(_adapter *padapter, int aid_res, u16 status)
-+{
-+	struct cmd_obj *pcmd_obj;
-+	u8	*pevtcmd;
-+	u32 cmdsz;
-+	struct joinbss_event *pjoinbss_evt;
-+	struct rtw_evt_header *evt_hdr;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+	u32 ret = _FAIL;
-+
-+	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (pcmd_obj == NULL)
-+		goto exit;
-+
-+	cmdsz = (sizeof(struct joinbss_event) + sizeof(struct rtw_evt_header));
-+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
-+	if (pevtcmd == NULL) {
-+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
-+		goto exit;
-+	}
-+
-+	_rtw_init_listhead(&pcmd_obj->list);
-+
-+	pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
-+	pcmd_obj->cmdsz = cmdsz;
-+	pcmd_obj->parmbuf = pevtcmd;
-+
-+	pcmd_obj->rsp = NULL;
-+	pcmd_obj->rspsz  = 0;
-+
-+	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
-+	evt_hdr->len = sizeof(struct joinbss_event);
-+	evt_hdr->id = EVT_JOINBSS;
-+	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
-+
-+	pjoinbss_evt = (struct joinbss_event *)(pevtcmd + sizeof(struct rtw_evt_header));
-+	_rtw_memcpy((unsigned char *)(&(pjoinbss_evt->network.network)), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX));
-+	pjoinbss_evt->network.join_res = pjoinbss_evt->network.aid = aid_res;
-+
-+	RTW_INFO("report_join_res(%d, %u)\n", aid_res, status);
-+
-+
-+	rtw_joinbss_event_prehandle(padapter, (u8 *)&pjoinbss_evt->network, status);
-+
-+
-+	ret = rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
-+
-+exit:
-+	return ret;
-+}
-+
-+void report_wmm_edca_update(_adapter *padapter)
-+{
-+	struct cmd_obj *pcmd_obj;
-+	u8 *pevtcmd;
-+	u32 cmdsz;
-+	struct wmm_event *pwmm_event;
-+	struct rtw_evt_header *evt_hdr;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+
-+	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (pcmd_obj == NULL)
-+		return;
-+
-+	cmdsz = (sizeof(struct wmm_event) + sizeof(struct rtw_evt_header));
-+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
-+	if (pevtcmd == NULL) {
-+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
-+		return;
-+	}
-+
-+	_rtw_init_listhead(&pcmd_obj->list);
-+
-+	pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
-+	pcmd_obj->cmdsz = cmdsz;
-+	pcmd_obj->parmbuf = pevtcmd;
-+
-+	pcmd_obj->rsp = NULL;
-+	pcmd_obj->rspsz  = 0;
-+
-+	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
-+	evt_hdr->len = sizeof(struct wmm_event);
-+	evt_hdr->id = EVT_WMM_UPDATE;
-+	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
-+
-+	pwmm_event = (struct wmm_event *)(pevtcmd + sizeof(struct rtw_evt_header));
-+	pwmm_event->wmm = 0;
-+
-+	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
-+
-+	return;
-+
-+}
-+
-+u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated)
-+{
-+	struct cmd_obj *pcmd_obj;
-+	u8 *pevtcmd;
-+	u32 cmdsz;
-+	struct sta_info *psta;
-+	int mac_id = -1;
-+	struct stadel_event *pdel_sta_evt;
-+	struct rtw_evt_header *evt_hdr;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+	u8 res = _SUCCESS;
-+
-+	/* prepare cmd parameter */
-+	cmdsz = (sizeof(struct stadel_event) + sizeof(struct rtw_evt_header));
-+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
-+	if (pevtcmd == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
-+	evt_hdr->len = sizeof(struct stadel_event);
-+	evt_hdr->id = EVT_DEL_STA;
-+	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
-+
-+	pdel_sta_evt = (struct stadel_event *)(pevtcmd + sizeof(struct rtw_evt_header));
-+	_rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN);
-+	_rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2);
-+	psta = rtw_get_stainfo(&padapter->stapriv, MacAddr);
-+	if (psta)
-+		mac_id = (int)psta->cmn.mac_id;
-+	else
-+		mac_id = (-1);
-+	pdel_sta_evt->mac_id = mac_id;
-+	pdel_sta_evt->locally_generated = locally_generated;
-+
-+	if (!enqueue) {
-+		/* do directly */
-+		rtw_stadel_event_callback(padapter, (u8 *)pdel_sta_evt);
-+		rtw_mfree(pevtcmd, cmdsz);
-+	} else {
-+		pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+		if (pcmd_obj == NULL) {
-+			rtw_mfree(pevtcmd, cmdsz);
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		_rtw_init_listhead(&pcmd_obj->list);
-+		pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
-+		pcmd_obj->cmdsz = cmdsz;
-+		pcmd_obj->parmbuf = pevtcmd;
-+
-+		pcmd_obj->rsp = NULL;
-+		pcmd_obj->rspsz  = 0;
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
-+	}
-+
-+exit:
-+
-+	RTW_INFO(FUNC_ADPT_FMT" "MAC_FMT" mac_id=%d, enqueue:%d, res:%u\n"
-+		, FUNC_ADPT_ARG(padapter), MAC_ARG(MacAddr), mac_id, enqueue, res);
-+
-+	return res;
-+}
-+
-+void report_add_sta_event(_adapter *padapter, unsigned char *MacAddr)
-+{
-+	struct cmd_obj *pcmd_obj;
-+	u8 *pevtcmd;
-+	u32 cmdsz;
-+	struct stassoc_event *padd_sta_evt;
-+	struct rtw_evt_header *evt_hdr;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+
-+	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (pcmd_obj == NULL)
-+		return;
-+
-+	cmdsz = (sizeof(struct stassoc_event) + sizeof(struct rtw_evt_header));
-+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
-+	if (pevtcmd == NULL) {
-+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
-+		return;
-+	}
-+
-+	_rtw_init_listhead(&pcmd_obj->list);
-+
-+	pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
-+	pcmd_obj->cmdsz = cmdsz;
-+	pcmd_obj->parmbuf = pevtcmd;
-+
-+	pcmd_obj->rsp = NULL;
-+	pcmd_obj->rspsz  = 0;
-+
-+	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
-+	evt_hdr->len = sizeof(struct stassoc_event);
-+	evt_hdr->id = EVT_ADD_STA;
-+	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
-+
-+	padd_sta_evt = (struct stassoc_event *)(pevtcmd + sizeof(struct rtw_evt_header));
-+	_rtw_memcpy((unsigned char *)(&(padd_sta_evt->macaddr)), MacAddr, ETH_ALEN);
-+
-+	RTW_INFO("report_add_sta_event: add STA\n");
-+
-+	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
-+
-+	return;
-+}
-+
-+
-+bool rtw_port_switch_chk(_adapter *adapter)
-+{
-+	bool switch_needed = _FALSE;
-+#ifdef CONFIG_CONCURRENT_MODE
-+#ifdef CONFIG_RUNTIME_PORT_SWITCH
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(dvobj);
-+	_adapter *if_port0 = NULL;
-+	_adapter *if_port1 = NULL;
-+	struct mlme_ext_info *if_port0_mlmeinfo = NULL;
-+	struct mlme_ext_info *if_port1_mlmeinfo = NULL;
-+	int i;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		if (get_hw_port(dvobj->padapters[i]) == HW_PORT0) {
-+			if_port0 = dvobj->padapters[i];
-+			if_port0_mlmeinfo = &(if_port0->mlmeextpriv.mlmext_info);
-+		} else if (get_hw_port(dvobj->padapters[i]) == HW_PORT1) {
-+			if_port1 = dvobj->padapters[i];
-+			if_port1_mlmeinfo = &(if_port1->mlmeextpriv.mlmext_info);
-+		}
-+	}
-+
-+	if (if_port0 == NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (if_port1 == NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+#ifdef DBG_RUNTIME_PORT_SWITCH
-+	RTW_INFO(FUNC_ADPT_FMT" wowlan_mode:%u\n"
-+		 ADPT_FMT", port0, mlmeinfo->state:0x%08x, p2p_state:%d, %d\n"
-+		 ADPT_FMT", port1, mlmeinfo->state:0x%08x, p2p_state:%d, %d\n",
-+		 FUNC_ADPT_ARG(adapter), pwrctl->wowlan_mode,
-+		ADPT_ARG(if_port0), if_port0_mlmeinfo->state, rtw_p2p_state(&if_port0->wdinfo), rtw_p2p_chk_state(&if_port0->wdinfo, P2P_STATE_NONE),
-+		ADPT_ARG(if_port1), if_port1_mlmeinfo->state, rtw_p2p_state(&if_port1->wdinfo), rtw_p2p_chk_state(&if_port1->wdinfo, P2P_STATE_NONE));
-+#endif /* DBG_RUNTIME_PORT_SWITCH */
-+
-+#ifdef CONFIG_WOWLAN
-+	/* WOWLAN interface(primary, for now) should be port0 */
-+	if (pwrctl->wowlan_mode == _TRUE) {
-+		if (!is_primary_adapter(if_port0)) {
-+			RTW_INFO("%s "ADPT_FMT" enable WOWLAN\n", __func__, ADPT_ARG(if_port1));
-+			switch_needed = _TRUE;
-+		}
-+		goto exit;
-+	}
-+#endif /* CONFIG_WOWLAN */
-+
-+	/* AP/Mesh should use port0 for ctl frame's ack */
-+	if ((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
-+		RTW_INFO("%s "ADPT_FMT" is AP/GO/Mesh\n", __func__, ADPT_ARG(if_port1));
-+		switch_needed = _TRUE;
-+		goto exit;
-+	}
-+
-+	/* GC should use port0 for p2p ps */
-+	if (((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)
-+	    && (if_port1_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
-+#ifdef CONFIG_P2P
-+	    && !rtw_p2p_chk_state(&if_port1->wdinfo, P2P_STATE_NONE)
-+#endif
-+	    && !check_fwstate(&if_port1->mlmepriv, WIFI_UNDER_WPS)
-+	   ) {
-+		RTW_INFO("%s "ADPT_FMT" is GC\n", __func__, ADPT_ARG(if_port1));
-+		switch_needed = _TRUE;
-+		goto exit;
-+	}
-+
-+	/* port1 linked, but port0 not linked */
-+	if ((if_port1_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
-+	    && !(if_port0_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
-+	    && ((if_port0_mlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
-+	   ) {
-+		RTW_INFO("%s "ADPT_FMT" is SINGLE_LINK\n", __func__, ADPT_ARG(if_port1));
-+		switch_needed = _TRUE;
-+		goto exit;
-+	}
-+
-+exit:
-+#ifdef DBG_RUNTIME_PORT_SWITCH
-+	RTW_INFO(FUNC_ADPT_FMT" ret:%d\n", FUNC_ADPT_ARG(adapter), switch_needed);
-+#endif /* DBG_RUNTIME_PORT_SWITCH */
-+#endif /* CONFIG_RUNTIME_PORT_SWITCH */
-+#endif /* CONFIG_CONCURRENT_MODE */
-+	return switch_needed;
-+}
-+
-+/****************************************************************************
-+
-+Following are the event callback functions
-+
-+*****************************************************************************/
-+
-+/* for sta/adhoc mode */
-+void update_sta_info(_adapter *padapter, struct sta_info *psta)
-+{
-+	_irqL	irqL;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	/* ERP */
-+	VCS_update(padapter, psta);
-+
-+#ifdef CONFIG_80211N_HT
-+	/* HT */
-+	if (pmlmepriv->htpriv.ht_option) {
-+		psta->htpriv.ht_option = _TRUE;
-+
-+		psta->htpriv.ampdu_enable = pmlmepriv->htpriv.ampdu_enable;
-+
-+		psta->htpriv.rx_ampdu_min_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & IEEE80211_HT_CAP_AMPDU_DENSITY) >> 2;
-+
-+		if (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_20))
-+			psta->htpriv.sgi_20m = _TRUE;
-+
-+		if (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_40))
-+			psta->htpriv.sgi_40m = _TRUE;
-+
-+		psta->qos_option = _TRUE;
-+
-+		psta->htpriv.ldpc_cap = pmlmepriv->htpriv.ldpc_cap;
-+		psta->htpriv.stbc_cap = pmlmepriv->htpriv.stbc_cap;
-+		psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap;
-+
-+		_rtw_memcpy(&psta->htpriv.ht_cap, &pmlmeinfo->HT_caps, sizeof(struct rtw_ieee80211_ht_cap));
-+		#ifdef CONFIG_BEAMFORMING
-+		psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap;
-+		psta->cmn.bf_info.ht_beamform_cap = pmlmepriv->htpriv.beamform_cap;
-+		#endif
-+	} else
-+#endif /* CONFIG_80211N_HT */
-+	{
-+#ifdef CONFIG_80211N_HT
-+		psta->htpriv.ht_option = _FALSE;
-+		psta->htpriv.ampdu_enable = _FALSE;
-+		psta->htpriv.tx_amsdu_enable = _FALSE;
-+		psta->htpriv.sgi_20m = _FALSE;
-+		psta->htpriv.sgi_40m = _FALSE;
-+#endif /* CONFIG_80211N_HT */
-+		psta->qos_option = _FALSE;
-+
-+	}
-+
-+#ifdef CONFIG_80211N_HT
-+	psta->htpriv.ch_offset = pmlmeext->cur_ch_offset;
-+
-+	psta->htpriv.agg_enable_bitmap = 0x0;/* reset */
-+	psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */
-+#endif /* CONFIG_80211N_HT */
-+
-+	psta->cmn.bw_mode = pmlmeext->cur_bwmode;
-+
-+	/* QoS */
-+	if (pmlmepriv->qospriv.qos_option)
-+		psta->qos_option = _TRUE;
-+
-+#ifdef CONFIG_80211AC_VHT
-+	_rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv));
-+	if (psta->vhtpriv.vht_option) {
-+		psta->cmn.ra_info.is_vht_enable = _TRUE;
-+		#ifdef CONFIG_BEAMFORMING
-+		psta->vhtpriv.beamform_cap = pmlmepriv->vhtpriv.beamform_cap;
-+		psta->cmn.bf_info.vht_beamform_cap = pmlmepriv->vhtpriv.beamform_cap;
-+		#endif /*CONFIG_BEAMFORMING*/
-+	}
-+#endif /* CONFIG_80211AC_VHT */
-+	psta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta));
-+	update_ldpc_stbc_cap(psta);
-+
-+	_enter_critical_bh(&psta->lock, &irqL);
-+	psta->state = WIFI_ASOC_STATE;
-+	_exit_critical_bh(&psta->lock, &irqL);
-+
-+}
-+
-+static void rtw_mlmeext_disconnect(_adapter *padapter)
-+{
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 self_action = MLME_ACTION_UNKNOWN;
-+	u8 state_backup = (pmlmeinfo->state & 0x03);
-+	u8 ASIX_ID[] = {0x00, 0x0E, 0xC6};
-+
-+	if (MLME_IS_AP(padapter))
-+		self_action = MLME_AP_STOPPED;
-+	else if (MLME_IS_MESH(padapter))
-+		self_action = MLME_MESH_STOPPED;
-+	else if (MLME_IS_STA(padapter))
-+		self_action = MLME_STA_DISCONNECTED;
-+	else if (MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter))
-+		self_action = MLME_ADHOC_STOPPED;
-+	else {
-+		RTW_INFO("state:0x%x\n", MLME_STATE(padapter));
-+		rtw_warn_on(1);
-+	}
-+
-+	/* set_opmode_cmd(padapter, infra_client_with_mlme); */
-+#ifdef CONFIG_HW_P0_TSF_SYNC
-+	if (self_action == MLME_STA_DISCONNECTED)
-+		correct_TSF(padapter, self_action);
-+#endif
-+	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0);
-+	rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr);
-+	if (self_action == MLME_STA_DISCONNECTED)
-+		rtw_hal_rcr_set_chk_bssid(padapter, self_action);
-+
-+	/* set MSR to no link state->infra. mode */
-+	Set_MSR(padapter, _HW_STATE_STATION_);
-+
-+	/* check if sta is ASIX peer and fix IOT issue if it is. */
-+	if (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) , ASIX_ID , 3)) {
-+		u8 iot_flag = _FALSE;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag));
-+	}
-+	pmlmeinfo->state = WIFI_FW_NULL_STATE;
-+
-+#ifdef CONFIG_MCC_MODE
-+	/* mcc disconnect setting before download LPS rsvd page */
-+	rtw_hal_set_mcc_setting_disconnect(padapter);
-+#endif /* CONFIG_MCC_MODE */
-+
-+	if (state_backup == WIFI_FW_STATION_STATE) {
-+		if (rtw_port_switch_chk(padapter) == _TRUE) {
-+			rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
-+#ifdef CONFIG_LPS
-+			{
-+				_adapter *port0_iface = dvobj_get_port0_adapter(adapter_to_dvobj(padapter));
-+				if (port0_iface)
-+					rtw_lps_ctrl_wk_cmd(port0_iface, LPS_CTRL_CONNECT, RTW_CMDF_DIRECTLY);
-+			}
-+#endif
-+		}
-+	}
-+
-+	/* switch to the 20M Hz mode after disconnect */
-+	pmlmeext->cur_bwmode = CHANNEL_WIDTH_20;
-+	pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+#ifdef CONFIG_CTRL_TXSS_BY_TP
-+	pmlmeext->txss_1ss = _FALSE;
-+#endif
-+
-+#ifdef CONFIG_FCS_MODE
-+	if (EN_FCS(padapter))
-+		rtw_hal_set_hwreg(padapter, HW_VAR_STOP_FCS_MODE, NULL);
-+#endif
-+
-+	if (!(MLME_IS_STA(padapter) && MLME_IS_OPCH_SW(padapter))) {
-+		/* DFS and channel status no need to check here for STA under OPCH_SW */
-+		u8 ch, bw, offset;
-+
-+		#ifdef CONFIG_DFS_MASTER
-+		rtw_dfs_rd_en_decision(padapter, self_action, 0);
-+		#endif
-+
-+		if (rtw_mi_get_ch_setting_union_no_self(padapter, &ch, &bw, &offset) != 0)
-+			set_channel_bwmode(padapter, ch, offset, bw);
-+		rtw_mi_update_union_chan_inf(padapter, ch, offset, bw);
-+		rtw_rfctl_update_op_mode(adapter_to_rfctl(padapter), BIT(padapter->iface_id), 0);
-+	}
-+
-+	flush_all_cam_entry(padapter);
-+
-+	_cancel_timer_ex(&pmlmeext->link_timer);
-+
-+	/* pmlmepriv->LinkDetectInfo.TrafficBusyState = _FALSE; */
-+	pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;
-+	pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;
-+
-+#ifdef CONFIG_TDLS
-+	padapter->tdlsinfo.ap_prohibited = _FALSE;
-+
-+	/* For TDLS channel switch, currently we only allow it to work in wifi logo test mode */
-+	if (padapter->registrypriv.wifi_spec == 1)
-+		padapter->tdlsinfo.ch_switch_prohibited = _FALSE;
-+#endif /* CONFIG_TDLS */
-+
-+#ifdef CONFIG_WMMPS_STA
-+	 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
-+		/* reset currently related uapsd setting when the connection has broken */
-+		pmlmepriv->qospriv.uapsd_max_sp_len = 0;
-+		pmlmepriv->qospriv.uapsd_tid = 0;
-+		pmlmepriv->qospriv.uapsd_tid_delivery_enabled = 0;
-+		pmlmepriv->qospriv.uapsd_tid_trigger_enabled = 0;
-+		pmlmepriv->qospriv.uapsd_ap_supported = 0;
-+	}
-+#endif /* CONFIG_WMMPS_STA */
-+#ifdef CONFIG_RTS_FULL_BW
-+	rtw_set_rts_bw(padapter);
-+#endif/*CONFIG_RTS_FULL_BW*/
-+
-+}
-+
-+void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res)
-+{
-+	struct sta_info		*psta;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
-+	struct sta_priv		*pstapriv = &padapter->stapriv;
-+	u8	join_type;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+
-+#ifndef CONFIG_IOCTL_CFG80211
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+#endif
-+
-+	if (pmlmepriv->wpa_phase == _TRUE)
-+		pmlmepriv->wpa_phase = _FALSE;
-+
-+	if (join_res < 0) {
-+		join_type = 1;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
-+		rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr);
-+		if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)
-+			rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_DISCONNECTED);
-+
-+		rtw_btcoex_connect_notify(padapter, join_type);
-+
-+		goto exit_mlmeext_joinbss_event_callback;
-+	}
-+
-+#ifdef CONFIG_ARP_KEEP_ALIVE
-+	pmlmepriv->bGetGateway = 1;
-+	pmlmepriv->GetGatewayTryCnt = 0;
-+#endif
-+
-+#ifdef CONFIG_AP_MODE
-+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
-+		/* update bc/mc sta_info */
-+		update_bmc_sta(padapter);
-+	}
-+#endif
-+
-+	/* turn on dynamic functions */
-+	/* Switch_DM_Func(padapter, DYNAMIC_ALL_FUNC_ENABLE, _TRUE); */
-+
-+	/* update IOT-releated issue */
-+	update_IOT_info(padapter);
-+
-+	#ifdef CONFIG_RTS_FULL_BW
-+	rtw_set_rts_bw(padapter);
-+	#endif/*CONFIG_RTS_FULL_BW*/
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, cur_network->SupportedRates);
-+
-+	/* BCN interval */
-+	rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pmlmeinfo->bcn_interval));
-+
-+	/* udpate capability */
-+	update_capinfo(padapter, pmlmeinfo->capability);
-+
-+	/* WMM, Update EDCA param */
-+	WMMOnAssocRsp(padapter);
-+#ifdef CONFIG_80211N_HT
-+	/* HT */
-+	HTOnAssocRsp(padapter);
-+#endif /* CONFIG_80211N_HT */
-+#ifdef CONFIG_80211AC_VHT
-+	/* VHT */
-+	VHTOnAssocRsp(padapter);
-+#endif
-+
-+	psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
-+	if (psta) { /* only for infra. mode */
-+		psta->wireless_mode = pmlmeext->cur_wireless_mode;
-+
-+		/* set per sta rate after updating HT cap. */
-+		set_sta_rate(padapter, psta);
-+
-+		rtw_sta_media_status_rpt(padapter, psta, 1);
-+
-+		/* wakeup macid after join bss successfully to ensure
-+			the subsequent data frames can be sent out normally */
-+		rtw_hal_macid_wakeup(padapter, psta->cmn.mac_id);
-+
-+		rtw_xmit_queue_clear(psta);
-+	}
-+
-+#ifndef CONFIG_IOCTL_CFG80211
-+	if (is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm))
-+		rtw_sec_restore_wep_key(padapter);
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+	if (rtw_port_switch_chk(padapter) == _TRUE)
-+		rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
-+
-+	join_type = 2;
-+	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
-+
-+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {
-+		rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTED);
-+
-+		/* correcting TSF */
-+		correct_TSF(padapter, MLME_STA_CONNECTED);
-+
-+		/* set_link_timer(pmlmeext, DISCONNECT_TO); */
-+	}
-+
-+#ifdef CONFIG_LPS
-+	#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
-+	if (get_hw_port(padapter) == HW_PORT0)
-+	#endif
-+		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_CONNECT, RTW_CMDF_DIRECTLY);
-+#endif
-+
-+	rtw_btcoex_connect_notify(padapter, join_type);
-+
-+#ifdef CONFIG_BEAMFORMING
-+	if (psta)
-+		beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_ENTER, (u8 *)psta, sizeof(struct sta_info), 0);
-+#endif/*CONFIG_BEAMFORMING*/
-+
-+exit_mlmeext_joinbss_event_callback:
-+
-+	rtw_join_done_chk_ch(padapter, join_res);
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	rtw_rson_join_done(padapter);
-+#endif
-+
-+	RTW_INFO("=>%s - End to Connection without 4-way\n", __FUNCTION__);
-+}
-+
-+/* currently only adhoc mode will go here */
-+void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8	join_type;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
-+		if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { /* adhoc master or sta_count>1 */
-+			/* nothing to do */
-+		} else { /* adhoc client */
-+			#ifdef CONFIG_AP_MODE
-+			/* update TSF Value */
-+			/* update_TSF(pmlmeext, pframe, len);			 */
-+
-+			/* correcting TSF */
-+			correct_TSF(padapter, MLME_ADHOC_STARTED);
-+
-+			/* start beacon */
-+			if (send_beacon(padapter) == _FAIL)
-+				rtw_warn_on(1);
-+
-+			pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
-+			#endif
-+		}
-+
-+		join_type = 2;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
-+
-+		rtw_btcoex_connect_notify(padapter, join_type);
-+	}
-+
-+	/* update adhoc sta_info */
-+	update_sta_info(padapter, psta);
-+
-+	rtw_hal_update_sta_ra_info(padapter, psta);
-+
-+	/* ToDo: HT for Ad-hoc */
-+	psta->wireless_mode = rtw_check_network_type(psta->bssrateset, psta->bssratelen, pmlmeext->cur_channel);
-+	rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
-+
-+	/* rate radaptive */
-+	Update_RA_Entry(padapter, psta);
-+}
-+
-+void mlmeext_sta_del_event_callback(_adapter *padapter)
-+{
-+	if (is_client_associated_to_ap(padapter) || is_IBSS_empty(padapter))
-+		rtw_mlmeext_disconnect(padapter);
-+}
-+
-+/****************************************************************************
-+
-+Following are the functions for the timer handlers
-+
-+*****************************************************************************/
-+void _linked_info_dump(_adapter *padapter)
-+{
-+	if (padapter->bLinkInfoDump) {
-+		rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, RTW_DBGDUMP);
-+		rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, RTW_DBGDUMP, _FALSE);
-+	}
-+}
-+/********************************************************************
-+
-+When station does not receive any packet in MAX_CONTINUAL_NORXPACKET_COUNT*2 seconds,
-+recipient station will teardown the block ack by issuing DELBA frame.
-+
-+*********************************************************************/
-+void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer)
-+{
-+	int	i = 0;
-+	int ret = _SUCCESS;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	/*
-+		IOT issue,occur Broadcom ap(Buffalo WZR-D1800H,Netgear R6300).
-+		AP is originator.AP does not transmit unicast packets when STA response its BAR.
-+		This case probably occur ap issue BAR after AP builds BA.
-+
-+		Follow 802.11 spec, STA shall maintain an inactivity timer for every negotiated Block Ack setup.
-+		The inactivity timer is not reset when MPDUs corresponding to other TIDs are received.
-+	*/
-+	if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) {
-+		for (i = 0; i < TID_NUM ; i++) {
-+			if ((psta->recvreorder_ctrl[i].enable) && 
-+                        (sta_rx_data_qos_pkts(psta, i) == sta_last_rx_data_qos_pkts(psta, i)) ) {			
-+					if (_TRUE == rtw_inc_and_chk_continual_no_rx_packet(psta, i)) {					
-+						/* send a DELBA frame to the peer STA with the Reason Code field set to TIMEOUT */
-+						if (!from_timer)
-+							ret = issue_del_ba_ex(padapter, psta->cmn.mac_addr, i, 39, 0, 3, 1);
-+						else
-+							issue_del_ba(padapter,  psta->cmn.mac_addr, i, 39, 0);
-+						psta->recvreorder_ctrl[i].enable = _FALSE;
-+						if (ret != _FAIL)
-+							psta->recvreorder_ctrl[i].ampdu_size = RX_AMPDU_SIZE_INVALID;
-+						rtw_reset_continual_no_rx_packet(psta, i);
-+					}				
-+			} else {
-+				/* The inactivity timer is reset when MPDUs to the TID is received. */
-+				rtw_reset_continual_no_rx_packet(psta, i);
-+			}
-+		}
-+	}
-+}
-+
-+
-+u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta)
-+{
-+	u8 ret = _FALSE;
-+#ifdef DBG_EXPIRATION_CHK
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	RTW_INFO(FUNC_ADPT_FMT" rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu"
-+		/*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/
-+		 ", retry:%u\n"
-+		 , FUNC_ADPT_ARG(padapter)
-+		 , STA_RX_PKTS_DIFF_ARG(psta)
-+		, psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts
-+		, psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts
-+		/*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts
-+		, psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts
-+		, psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts
-+		 , pmlmeinfo->bcn_interval*/
-+		 , pmlmeext->retry
-+		);
-+
-+	RTW_INFO(FUNC_ADPT_FMT" tx_pkts:%llu, link_count:%u\n", FUNC_ADPT_ARG(padapter)
-+		 , sta_tx_pkts(psta)
-+		 , pmlmeinfo->link_count
-+		);
-+#endif
-+
-+	if ((sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta))
-+	    && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta)
-+	    && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta)
-+	   )
-+		ret = _FALSE;
-+	else
-+		ret = _TRUE;
-+
-+	sta_update_last_rx_pkts(psta);
-+
-+	return ret;
-+}
-+
-+u8 chk_adhoc_peer_is_alive(struct sta_info *psta)
-+{
-+	u8 ret = _TRUE;
-+
-+#ifdef DBG_EXPIRATION_CHK
-+	RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu"
-+		/*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/
-+		 ", expire_to:%u\n"
-+		 , MAC_ARG(psta->cmn.mac_addr)
-+		 , psta->cmn.rssi_stat.rssi
-+		 , STA_RX_PKTS_DIFF_ARG(psta)
-+		, psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts
-+		, psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts
-+		/*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts
-+		, psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts
-+		, psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts
-+		 , pmlmeinfo->bcn_interval*/
-+		 , psta->expire_to
-+		);
-+#endif
-+
-+	if (sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta)
-+	    && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta)
-+	    && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta))
-+		ret = _FALSE;
-+
-+	sta_update_last_rx_pkts(psta);
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_TDLS
-+u8 chk_tdls_peer_sta_is_alive(_adapter *padapter, struct sta_info *psta)
-+{
-+	if ((psta->sta_stats.rx_data_pkts == psta->sta_stats.last_rx_data_pkts)
-+	    && (psta->sta_stats.rx_tdls_disc_rsp_pkts == psta->sta_stats.last_rx_tdls_disc_rsp_pkts))
-+		return _FALSE;
-+
-+	return _TRUE;
-+}
-+
-+void linked_status_chk_tdls(_adapter *padapter)
-+{
-+	struct candidate_pool {
-+		struct sta_info *psta;
-+		u8 addr[ETH_ALEN];
-+	};
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	_irqL irqL;
-+	u8 ack_chk;
-+	struct sta_info *psta;
-+	int i, num_teardown = 0, num_checkalive = 0;
-+	_list	*plist, *phead;
-+	struct tdls_txmgmt txmgmt;
-+	struct candidate_pool checkalive[MAX_ALLOWED_TDLS_STA_NUM];
-+	struct candidate_pool teardown[MAX_ALLOWED_TDLS_STA_NUM];
-+	u8 tdls_sta_max = _FALSE;
-+
-+#define ALIVE_MIN 2
-+#define ALIVE_MAX 5
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	_rtw_memset(checkalive, 0x00, sizeof(checkalive));
-+	_rtw_memset(teardown, 0x00, sizeof(teardown));
-+
-+	if ((padapter->tdlsinfo.link_established == _TRUE)) {
-+		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+		for (i = 0; i < NUM_STA; i++) {
-+			phead = &(pstapriv->sta_hash[i]);
-+			plist = get_next(phead);
-+
-+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+				plist = get_next(plist);
-+
-+				if (psta->tdls_sta_state & TDLS_LINKED_STATE) {
-+					psta->alive_count++;
-+					if (psta->alive_count >= ALIVE_MIN) {
-+						if (chk_tdls_peer_sta_is_alive(padapter, psta) == _FALSE) {
-+							if (psta->alive_count < ALIVE_MAX) {
-+								_rtw_memcpy(checkalive[num_checkalive].addr, psta->cmn.mac_addr, ETH_ALEN);
-+								checkalive[num_checkalive].psta = psta;
-+								num_checkalive++;
-+							} else {
-+								_rtw_memcpy(teardown[num_teardown].addr, psta->cmn.mac_addr, ETH_ALEN);
-+								teardown[num_teardown].psta = psta;
-+								num_teardown++;
-+							}
-+						} else
-+							psta->alive_count = 0;
-+					}
-+					psta->sta_stats.last_rx_data_pkts = psta->sta_stats.rx_data_pkts;
-+					psta->sta_stats.last_rx_tdls_disc_rsp_pkts = psta->sta_stats.rx_tdls_disc_rsp_pkts;
-+
-+					if ((num_checkalive >= MAX_ALLOWED_TDLS_STA_NUM) || (num_teardown >= MAX_ALLOWED_TDLS_STA_NUM)) {
-+						tdls_sta_max = _TRUE;
-+						break;
-+					}
-+				}
-+			}
-+
-+			if (tdls_sta_max == _TRUE)
-+				break;
-+		}
-+		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+		if (num_checkalive > 0) {
-+			for (i = 0; i < num_checkalive; i++) {
-+				_rtw_memcpy(txmgmt.peer, checkalive[i].addr, ETH_ALEN);
-+				issue_tdls_dis_req(padapter, &txmgmt);
-+				issue_tdls_dis_req(padapter, &txmgmt);
-+				issue_tdls_dis_req(padapter, &txmgmt);
-+			}
-+		}
-+
-+		if (num_teardown > 0) {
-+			for (i = 0; i < num_teardown; i++) {
-+				RTW_INFO("[%s %d] Send teardown to "MAC_FMT"\n", __FUNCTION__, __LINE__, MAC_ARG(teardown[i].addr));
-+				txmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_;
-+				_rtw_memcpy(txmgmt.peer, teardown[i].addr, ETH_ALEN);
-+				issue_tdls_teardown(padapter, &txmgmt, _FALSE);
-+			}
-+		}
-+	}
-+
-+}
-+#endif /* CONFIG_TDLS */
-+
-+inline int rtw_get_rx_chk_limit(_adapter *adapter)
-+{
-+	return adapter->stapriv.rx_chk_limit;
-+}
-+
-+inline void rtw_set_rx_chk_limit(_adapter *adapter, int limit)
-+{
-+	adapter->stapriv.rx_chk_limit = limit;
-+}
-+
-+/* from_timer == 1 means driver is in LPS */
-+void linked_status_chk(_adapter *padapter, u8 from_timer)
-+{
-+	u32	i;
-+	struct sta_info		*psta;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct sta_priv		*pstapriv = &padapter->stapriv;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+#ifdef CONFIG_LAYER2_ROAMING
-+	struct recv_priv	*precvpriv = &padapter->recvpriv;
-+#endif
-+
-+#ifdef CONFIG_RTW_WDS
-+	rtw_wds_gptr_expire(padapter);
-+#endif
-+
-+	if (padapter->registrypriv.mp_mode == _TRUE)
-+		return;
-+		
-+	if (check_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON))
-+		return;
-+
-+	if (is_client_associated_to_ap(padapter)) {
-+		/* linked infrastructure client mode */
-+
-+		int tx_chk = _SUCCESS, rx_chk = _SUCCESS;
-+		int rx_chk_limit;
-+		int link_count_limit;
-+
-+#if defined(CONFIG_RTW_REPEATER_SON)
-+	rtw_rson_scan_wk_cmd(padapter, RSON_SCAN_PROCESS);
-+#elif defined(CONFIG_LAYER2_ROAMING)
-+		if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) {
-+			RTW_INFO("signal_strength_data.avg_val = %d\n", precvpriv->signal_strength_data.avg_val);
-+			if ((precvpriv->signal_strength_data.avg_val < pmlmepriv->roam_rssi_threshold)
-+				&& (rtw_get_passing_time_ms(pmlmepriv->last_roaming) >= pmlmepriv->roam_scan_int*2000)) {
-+#ifdef CONFIG_RTW_80211K
-+				rtw_roam_nb_discover(padapter, _FALSE);
-+#endif
-+				pmlmepriv->need_to_roam = _TRUE;
-+				rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM);
-+				pmlmepriv->last_roaming = rtw_get_current_time();
-+			} else
-+				pmlmepriv->need_to_roam = _FALSE;
-+		}
-+#endif
-+#ifdef CONFIG_MCC_MODE
-+		/*
-+		 * due to tx ps null date to ao, so ap doest not tx pkt to driver
-+		 * we may check chk_ap_is_alive fail, and may issue_probereq to wrong channel under sitesurvey
-+		 * don't keep alive check under MCC
-+		 */
-+		if (rtw_hal_mcc_link_status_chk(padapter, __func__) == _FALSE)
-+			return;
-+#endif
-+
-+		rx_chk_limit = rtw_get_rx_chk_limit(padapter);
-+
-+#ifdef CONFIG_ARP_KEEP_ALIVE
-+		if (!from_timer && pmlmepriv->bGetGateway == 1 && pmlmepriv->GetGatewayTryCnt < 3) {
-+			RTW_INFO("do rtw_gw_addr_query() : %d\n", pmlmepriv->GetGatewayTryCnt);
-+			pmlmepriv->GetGatewayTryCnt++;
-+			if (rtw_gw_addr_query(padapter) == 0)
-+				pmlmepriv->bGetGateway = 0;
-+			else {
-+				_rtw_memset(pmlmepriv->gw_ip, 0, 4);
-+				_rtw_memset(pmlmepriv->gw_mac_addr, 0, ETH_ALEN);
-+			}
-+		}
-+#endif
-+#ifdef CONFIG_P2P
-+		if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) {
-+			if (!from_timer)
-+				link_count_limit = 3; /* 8 sec */
-+			else
-+				link_count_limit = 15; /* 32 sec */
-+		} else
-+#endif /* CONFIG_P2P */
-+		{
-+			if (!from_timer)
-+				link_count_limit = 7; /* 16 sec */
-+			else
-+				link_count_limit = 29; /* 60 sec */
-+		}
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_TDLS_CH_SW
-+		if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) == _TRUE)
-+			return;
-+#endif /* CONFIG_TDLS_CH_SW */
-+
-+#ifdef CONFIG_TDLS_AUTOCHECKALIVE
-+		linked_status_chk_tdls(padapter);
-+#endif /* CONFIG_TDLS_AUTOCHECKALIVE */
-+#endif /* CONFIG_TDLS */
-+
-+		psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
-+		if (psta != NULL) {
-+			bool is_p2p_enable = _FALSE;
-+#ifdef CONFIG_P2P
-+			is_p2p_enable = !rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE);
-+#endif
-+
-+#ifdef CONFIG_ISSUE_DELBA_WHEN_NO_TRAFFIC 
-+			/*issue delba when ap does not tx data packet that is Broadcom ap */
-+			rtw_delba_check(padapter, psta, from_timer);
-+#endif
-+			if (chk_ap_is_alive(padapter, psta) == _FALSE)
-+				rx_chk = _FAIL;
-+
-+			if (sta_last_tx_pkts(psta) == sta_tx_pkts(psta))
-+				tx_chk = _FAIL;
-+
-+#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-+			if (!from_timer && pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL)
-+			) {
-+				u8 backup_ch = 0, backup_bw = 0, backup_offset = 0;
-+				u8 union_ch = 0, union_bw = 0, union_offset = 0;
-+				u8 switch_channel_by_drv = _TRUE;
-+
-+				
-+#ifdef CONFIG_MCC_MODE
-+				if (MCC_EN(padapter)) {
-+					/* driver doesn't switch channel under MCC */
-+					if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
-+						switch_channel_by_drv = _FALSE;
-+				}
-+#endif
-+				if (switch_channel_by_drv) {
-+					if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset)
-+						|| pmlmeext->cur_channel != union_ch)
-+							goto bypass_active_keep_alive;
-+
-+					/* switch to correct channel of current network  before issue keep-alive frames */
-+					if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) {
-+						backup_ch = rtw_get_oper_ch(padapter);
-+						backup_bw = rtw_get_oper_bw(padapter);
-+						backup_offset = rtw_get_oper_choffset(padapter);
-+						set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
-+					}
-+				}
-+
-+				if (rx_chk != _SUCCESS)
-+					issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->cmn.mac_addr, 0, 0, 3, 1);
-+
-+				if ((tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit) || rx_chk != _SUCCESS) {
-+					if (rtw_mi_check_fwstate(padapter, WIFI_UNDER_SURVEY))
-+						tx_chk = issue_nulldata(padapter, psta->cmn.mac_addr, 1, 3, 1);
-+					else
-+						tx_chk = issue_nulldata(padapter, psta->cmn.mac_addr, 0, 3, 1);
-+					/* if tx acked and p2p disabled, set rx_chk _SUCCESS to reset retry count */
-+					if (tx_chk == _SUCCESS && !is_p2p_enable)
-+						rx_chk = _SUCCESS;
-+				}
-+
-+				/* back to the original operation channel */
-+				if (backup_ch > 0 && switch_channel_by_drv)
-+					set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw);
-+
-+bypass_active_keep_alive:
-+				;
-+			} else
-+#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
-+			{
-+				if (rx_chk != _SUCCESS) {
-+					if (pmlmeext->retry == 0) {
-+#ifdef DBG_EXPIRATION_CHK
-+						RTW_INFO("issue_probereq to trigger probersp, retry=%d\n", pmlmeext->retry);
-+#endif
-+						issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));
-+						issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));
-+						issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));
-+					}
-+				}
-+
-+				if (tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit
-+#ifdef CONFIG_MCC_MODE
-+				    /* FW tx nulldata under MCC mode, we just check  ap is alive */
-+				    && (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC))
-+#endif /* CONFIG_MCC_MODE */
-+				) {
-+					#ifdef DBG_EXPIRATION_CHK
-+					RTW_INFO("%s issue_nulldata(%d)\n", __FUNCTION__, from_timer ? 1 : 0);
-+					#endif
-+					if (from_timer || rtw_mi_check_fwstate(padapter, WIFI_UNDER_SURVEY))
-+						tx_chk = issue_nulldata(padapter, NULL, 1, 0, 0);
-+					else
-+						tx_chk = issue_nulldata(padapter, NULL, 0, 1, 1);
-+				}
-+			}
-+
-+			if (rx_chk == _FAIL) {
-+				pmlmeext->retry++;
-+				if (pmlmeext->retry > rx_chk_limit) {
-+					RTW_PRINT(FUNC_ADPT_FMT" disconnect or roaming\n",
-+						  FUNC_ADPT_ARG(padapter));
-+					receive_disconnect(padapter, pmlmeinfo->network.MacAddress
-+						, WLAN_REASON_EXPIRATION_CHK, _FALSE);
-+					return;
-+				}
-+			} else
-+				pmlmeext->retry = 0;
-+
-+			if (tx_chk == _FAIL)
-+				pmlmeinfo->link_count %= (link_count_limit + 1);
-+			else {
-+				psta->sta_stats.last_tx_pkts = psta->sta_stats.tx_pkts;
-+				pmlmeinfo->link_count = 0;
-+			}
-+
-+		} /* end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL) */
-+
-+	} else if (is_client_associated_to_ibss(padapter)) {
-+		_irqL irqL;
-+		_list *phead, *plist, dlist;
-+
-+		_rtw_init_listhead(&dlist);
-+
-+		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+		for (i = 0; i < NUM_STA; i++) {
-+
-+			phead = &(pstapriv->sta_hash[i]);
-+			plist = get_next(phead);
-+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+				plist = get_next(plist);
-+
-+				if (is_broadcast_mac_addr(psta->cmn.mac_addr))
-+					continue;
-+
-+				if (chk_adhoc_peer_is_alive(psta) || !psta->expire_to)
-+					psta->expire_to = pstapriv->adhoc_expire_to;
-+				else
-+					psta->expire_to--;
-+
-+				if (psta->expire_to <= 0) {
-+					rtw_list_delete(&psta->list);
-+					rtw_list_insert_tail(&psta->list, &dlist);
-+				}
-+			}
-+		}
-+
-+		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+		plist = get_next(&dlist);
-+		while (rtw_end_of_queue_search(&dlist, plist) == _FALSE) {
-+			psta = LIST_CONTAINOR(plist, struct sta_info, list);
-+			plist = get_next(plist);
-+			rtw_list_delete(&psta->list);
-+			RTW_INFO(FUNC_ADPT_FMT" ibss expire "MAC_FMT"\n"
-+				, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
-+			report_del_sta_event(padapter, psta->cmn.mac_addr, WLAN_REASON_EXPIRATION_CHK, from_timer ? _TRUE : _FALSE, _FALSE);
-+		}
-+	}
-+
-+}
-+
-+void survey_timer_hdl(void *ctx)
-+{
-+	_adapter *padapter = (_adapter *)ctx;
-+	struct cmd_obj *cmd;
-+	struct sitesurvey_parm *psurveyPara;
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+
-+	if (mlmeext_scan_state(pmlmeext) > SCAN_DISABLE) {
-+		cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+		if (cmd == NULL) {
-+			rtw_warn_on(1);
-+			goto exit;
-+		}
-+
-+		psurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm));
-+		if (psurveyPara == NULL) {
-+			rtw_warn_on(1);
-+			rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj));
-+			goto exit;
-+		}
-+
-+		init_h2fwcmd_w_parm_no_rsp(cmd, psurveyPara, CMD_SITE_SURVEY);
-+		rtw_enqueue_cmd(pcmdpriv, cmd);
-+	}
-+
-+exit:
-+	return;
-+}
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+/*	 100ms pass, stop rson_scan	*/
-+void rson_timer_hdl(void *ctx)
-+{
-+	_adapter *padapter = (_adapter *)ctx;
-+
-+	rtw_rson_scan_wk_cmd(padapter, RSON_SCAN_DISABLE);
-+}
-+
-+#endif
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+void rtw_tbtx_xmit_timer_hdl(void *ctx)
-+{
-+	_adapter *padapter = (_adapter *)ctx;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+
-+	if (ATOMIC_READ(&padapter->tbtx_remove_tx_pause) == _TRUE){
-+		ATOMIC_SET(&padapter->tbtx_tx_pause, _FALSE);
-+		rtw_tx_control_cmd(padapter);
-+	}else {
-+		rtw_issue_action_token_rel(padapter);
-+		ATOMIC_SET(&padapter->tbtx_tx_pause, _TRUE);
-+		rtw_tx_control_cmd(padapter);
-+		_set_timer(&pmlmeext->tbtx_xmit_timer, MAX_TXPAUSE_DURATION);
-+		ATOMIC_SET(&padapter->tbtx_remove_tx_pause, _TRUE);
-+	}
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+void rtw_tbtx_token_dispatch_timer_hdl(void *ctx)
-+{
-+	_adapter *padapter = (_adapter *)ctx;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	_irqL irqL;
-+	struct sta_info *psta = NULL;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	_list *phead, *plist;
-+	int i, found = _FALSE;
-+	u8 nr_send, th_idx = 0;
-+
-+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+	RTW_DBG("%s:asoc_cnt: %d\n",__func__, pstapriv->tbtx_asoc_list_cnt);
-+
-+	// check number of TBTX sta
-+	if (padapter->stapriv.tbtx_asoc_list_cnt < 2)
-+		goto exit;
-+
-+	// dispatch token
-+	
-+	nr_send = RTW_DIV_ROUND_UP(pstapriv->tbtx_asoc_list_cnt, NR_TBTX_SLOT);
-+
-+	phead = &pstapriv->asoc_list;
-+	plist = get_next(phead);
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+		/* psta is supporting TBTX */
-+		if ((!psta) || (!psta->tbtx_enable))
-+			RTW_DBG("sta tbtx_enable is false\n");
-+		else {
-+			for (i = 0; i < nr_send; i++) {
-+				if (pstapriv->last_token_holder == psta) {
-+					found = _TRUE;
-+					goto outof_loop;
-+				}
-+			}
-+		}
-+		plist = get_next(plist);
-+	}
-+outof_loop:
-+	
-+	RTW_DBG("rtw_tbtx_token_dispatch_timer_hdl()   th_idx=%d,  nr_send=%d, phead=%p, plist=%p, found=%d\n ", th_idx ,  nr_send, phead, plist, found);
-+	if (!found) {
-+		plist = get_next(phead);
-+		while(rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+			psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+			if ((!psta) || (!psta->tbtx_enable))
-+				RTW_DBG("sta tbtx_enable is false\n");
-+			else {
-+					pstapriv->token_holder[th_idx] = psta;
-+					rtw_issue_action_token_req(padapter, pstapriv->token_holder[th_idx++]);
-+					break;
-+			}
-+			plist = get_next(plist);
-+		}
-+	}
-+
-+	for (i=th_idx; i<nr_send;) {
-+		plist = get_next(plist);
-+		if (plist == phead)
-+			plist = get_next(plist);
-+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+		if ((!psta) || (!psta->tbtx_enable))
-+			RTW_DBG("sta tbtx_enable is false\n");		
-+		else {
-+			pstapriv->token_holder[th_idx] = psta;
-+			rtw_issue_action_token_req(padapter, pstapriv->token_holder[th_idx++]);
-+			i++;
-+		}
-+	}
-+	ATOMIC_SET(&pstapriv->nr_token_keeper, nr_send);
-+	
-+
-+exit:
-+	// set_timer
-+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+	_set_timer(&pmlmeext->tbtx_token_dispatch_timer, TBTX_TX_DURATION); 
-+}
-+#endif /* CONFIG_AP_MODE */
-+#endif /* CONFIG_RTW_TOKEN_BASED_XMIT */
-+
-+void link_timer_hdl(void *ctx)
-+{
-+	_adapter *padapter = (_adapter *)ctx;
-+	/* static unsigned int		rx_pkt = 0; */
-+	/* static u64				tx_cnt = 0; */
-+	/* struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv); */
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	/* struct sta_priv		*pstapriv = &padapter->stapriv; */
-+#ifdef CONFIG_RTW_80211R
-+	struct	sta_priv		*pstapriv = &padapter->stapriv;
-+	struct	sta_info		*psta = NULL;
-+	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
-+#endif
-+
-+	if (rtw_sta_linking_test_force_fail())
-+		RTW_INFO("rtw_sta_linking_test_force_fail\n");
-+
-+	if (pmlmeext->join_abort && pmlmeinfo->state != WIFI_FW_NULL_STATE) {
-+		RTW_INFO(FUNC_ADPT_FMT" join abort\n", FUNC_ADPT_ARG(padapter));
-+		pmlmeinfo->state = WIFI_FW_NULL_STATE;
-+		report_join_res(padapter, -4, WLAN_STATUS_UNSPECIFIED_FAILURE);
-+		goto exit;
-+	}
-+
-+	if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) {
-+		RTW_INFO("link_timer_hdl:no beacon while connecting\n");
-+		pmlmeinfo->state = WIFI_FW_NULL_STATE;
-+		report_join_res(padapter, -3, WLAN_STATUS_UNSPECIFIED_FAILURE);
-+	} else if (pmlmeinfo->state & WIFI_FW_AUTH_STATE) {
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+		if (rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE))
-+			return;
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+		/* re-auth timer */
-+		if (++pmlmeinfo->reauth_count > REAUTH_LIMIT) {
-+			/* if (pmlmeinfo->auth_algo != dot11AuthAlgrthm_Auto) */
-+			/* { */
-+			pmlmeinfo->state = 0;
-+			if (pmlmeinfo->auth_status) {
-+				report_join_res(padapter, -1, pmlmeinfo->auth_status);
-+				pmlmeinfo->auth_status = 0; /* reset */
-+			} else
-+				report_join_res(padapter, -1, WLAN_STATUS_UNSPECIFIED_FAILURE);
-+			return;
-+			/* } */
-+			/* else */
-+			/* { */
-+			/*	pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared; */
-+			/*	pmlmeinfo->reauth_count = 0; */
-+			/* } */
-+		}
-+
-+		RTW_INFO("link_timer_hdl: auth timeout and try again\n");
-+		pmlmeinfo->auth_seq = 1;
-+		issue_auth(padapter, NULL, 0);
-+		set_link_timer(pmlmeext, REAUTH_TO);
-+	} else if (pmlmeinfo->state & WIFI_FW_ASSOC_STATE) {
-+		/* re-assoc timer */
-+		if (++pmlmeinfo->reassoc_count > REASSOC_LIMIT) {
-+			pmlmeinfo->state = WIFI_FW_NULL_STATE;
-+#ifdef CONFIG_RTW_80211R
-+			if (rtw_ft_roam(padapter)) {
-+				psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
-+				if (psta)
-+					rtw_free_stainfo(padapter,  psta);
-+			}
-+#endif
-+			report_join_res(padapter, -2, WLAN_STATUS_UNSPECIFIED_FAILURE);
-+			return;
-+		}
-+
-+#ifdef CONFIG_RTW_80211R
-+		if (rtw_ft_roam(padapter)) {
-+			RTW_INFO("link_timer_hdl: reassoc timeout and try again\n");
-+			issue_reassocreq(padapter);
-+		} else
-+#endif
-+		{
-+			RTW_INFO("link_timer_hdl: assoc timeout and try again\n");
-+			issue_assocreq(padapter);
-+		}
-+
-+		set_link_timer(pmlmeext, REASSOC_TO);
-+	}
-+
-+exit:
-+	return;
-+}
-+
-+void addba_timer_hdl(void *ctx)
-+{
-+	struct sta_info *psta = (struct sta_info *)ctx;
-+
-+#ifdef CONFIG_80211N_HT
-+	struct ht_priv	*phtpriv;
-+
-+	if (!psta)
-+		return;
-+
-+	phtpriv = &psta->htpriv;
-+
-+	if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) {
-+		if (phtpriv->candidate_tid_bitmap)
-+			phtpriv->candidate_tid_bitmap = 0x0;
-+
-+	}
-+#endif /* CONFIG_80211N_HT */
-+}
-+
-+#ifdef CONFIG_IEEE80211W
-+void report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short reason)
-+{
-+	struct cmd_obj *pcmd_obj;
-+	u8 *pevtcmd;
-+	u32 cmdsz;
-+	struct sta_info *psta;
-+	int	mac_id;
-+	struct stadel_event *pdel_sta_evt;
-+	struct rtw_evt_header *evt_hdr;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+
-+	pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (pcmd_obj == NULL)
-+		return;
-+
-+	cmdsz = (sizeof(struct stadel_event) + sizeof(struct rtw_evt_header));
-+	pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
-+	if (pevtcmd == NULL) {
-+		rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
-+		return;
-+	}
-+
-+	_rtw_init_listhead(&pcmd_obj->list);
-+
-+	pcmd_obj->cmdcode = CMD_SET_MLME_EVT;
-+	pcmd_obj->cmdsz = cmdsz;
-+	pcmd_obj->parmbuf = pevtcmd;
-+
-+	pcmd_obj->rsp = NULL;
-+	pcmd_obj->rspsz  = 0;
-+
-+	evt_hdr = (struct rtw_evt_header *)(pevtcmd);
-+	evt_hdr->len = sizeof(struct stadel_event);
-+	evt_hdr->id = EVT_TIMEOUT_STA;
-+	evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
-+
-+	pdel_sta_evt = (struct stadel_event *)(pevtcmd + sizeof(struct rtw_evt_header));
-+	_rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN);
-+	_rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2);
-+
-+
-+	psta = rtw_get_stainfo(&padapter->stapriv, MacAddr);
-+	if (psta)
-+		mac_id = (int)psta->cmn.mac_id;
-+	else
-+		mac_id = (-1);
-+
-+	pdel_sta_evt->mac_id = mac_id;
-+
-+	RTW_INFO("report_del_sta_event: delete STA, mac_id=%d\n", mac_id);
-+
-+	rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
-+
-+	return;
-+}
-+
-+void clnt_sa_query_timeout(_adapter *padapter)
-+{
-+	struct mlme_ext_priv *mlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+	receive_disconnect(padapter, get_my_bssid(&(mlmeinfo->network)), WLAN_REASON_SA_QUERY_TIMEOUT, _FALSE);
-+}
-+
-+void sa_query_timer_hdl(void *ctx)
-+{
-+	struct sta_info *psta = (struct sta_info *)ctx;
-+	_adapter *padapter = psta->padapter;
-+	_irqL irqL;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE &&
-+	    check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		clnt_sa_query_timeout(padapter);
-+	else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
-+		report_sta_timeout_event(padapter, psta->cmn.mac_addr, WLAN_REASON_PREV_AUTH_NOT_VALID);
-+}
-+
-+#endif /* CONFIG_IEEE80211W */
-+
-+#ifdef CONFIG_AUTO_AP_MODE
-+void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos)
-+{
-+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
-+	struct sta_info *psta = precv_frame->u.hdr.psta;
-+	struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos;
-+
-+	RTW_INFO("eth rx: got eth_type=0x%x\n", ntohs(ehdr->h_proto));
-+
-+	if (psta && psta->isrc && psta->pid > 0) {
-+		u16 rx_pid;
-+
-+		rx_pid = *(u16 *)(ehdr_pos + ETH_HLEN);
-+
-+		RTW_INFO("eth rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n",
-+			 rx_pid, MAC_ARG(psta->cmn.mac_addr), psta->pid);
-+
-+		if (rx_pid == psta->pid) {
-+			int i;
-+			u16 len = *(u16 *)(ehdr_pos + ETH_HLEN + 2);
-+			/* u16 ctrl_type = *(u16 *)(ehdr_pos + ETH_HLEN + 4); */
-+
-+			/* RTW_INFO("eth, RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type);  */
-+			RTW_INFO("eth, RC: len=0x%x\n", len);
-+
-+			for (i = 0; i < len; i++)
-+				RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 4 + i));
-+			/* RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 6 + i)); */
-+
-+			RTW_INFO("eth, RC-end\n");
-+		}
-+	}
-+
-+}
-+
-+void rtw_start_auto_ap(_adapter *adapter)
-+{
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11APMode, 0);
-+
-+	rtw_setopmode_cmd(adapter, Ndis802_11APMode, RTW_CMDF_WAIT_ACK);
-+}
-+
-+static int rtw_auto_ap_start_beacon(_adapter *adapter)
-+{
-+	int ret = 0;
-+	u8 *pbuf = NULL;
-+	uint len;
-+	u8	supportRate[16];
-+	int	sz = 0, rateLen;
-+	u8	*ie;
-+	u8	wireless_mode, oper_channel;
-+	u8 ssid[3] = {0}; /* hidden ssid */
-+	u32 ssid_len = sizeof(ssid);
-+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
-+		return -EINVAL;
-+
-+
-+	len = 128;
-+	pbuf = rtw_zmalloc(len);
-+	if (!pbuf)
-+		return -ENOMEM;
-+
-+
-+	/* generate beacon */
-+	ie = pbuf;
-+
-+	/* timestamp will be inserted by hardware */
-+	sz += 8;
-+	ie += sz;
-+
-+	/* beacon interval : 2bytes */
-+	*(u16 *)ie = cpu_to_le16((u16)100); /* BCN_INTERVAL=100; */
-+	sz += 2;
-+	ie += 2;
-+
-+	/* capability info */
-+	*(u16 *)ie = 0;
-+	*(u16 *)ie |= cpu_to_le16(cap_ESS);
-+	*(u16 *)ie |= cpu_to_le16(cap_ShortPremble);
-+	/* *(u16*)ie |= cpu_to_le16(cap_Privacy); */
-+	sz += 2;
-+	ie += 2;
-+
-+	/* SSID */
-+	ie = rtw_set_ie(ie, _SSID_IE_, ssid_len, ssid, &sz);
-+
-+	/* supported rates */
-+	wireless_mode = (WIRELESS_11BG_24N & padapter->registrypriv.wireless_mode);
-+	rtw_set_supported_rate(supportRate, wireless_mode);
-+	rateLen = rtw_get_rateset_len(supportRate);
-+	if (rateLen > 8)
-+		ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, supportRate, &sz);
-+	else
-+		ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, supportRate, &sz);
-+
-+
-+	/* DS parameter set */
-+	if (rtw_mi_check_status(adapter, MI_LINKED))
-+		oper_channel = rtw_mi_get_union_chan(adapter);
-+	else
-+		oper_channel = adapter_to_dvobj(adapter)->oper_channel;
-+
-+	ie = rtw_set_ie(ie, _DSSET_IE_, 1, &oper_channel, &sz);
-+
-+	/* ext supported rates */
-+	if (rateLen > 8)
-+		ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (supportRate + 8), &sz);
-+
-+	RTW_INFO("%s, start auto ap beacon sz=%d\n", __FUNCTION__, sz);
-+
-+	/* lunch ap mode & start to issue beacon */
-+	if (rtw_check_beacon_data(adapter, pbuf,  sz) == _SUCCESS) {
-+
-+	} else
-+		ret = -EINVAL;
-+
-+
-+	rtw_mfree(pbuf, len);
-+
-+	return ret;
-+
-+}
-+#endif/* CONFIG_AUTO_AP_MODE */
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+u8 tx_control_hdl(_adapter *adapter)
-+{
-+	u8 val;
-+
-+	if(ATOMIC_READ(&adapter->tbtx_tx_pause))
-+		val = 0xff;
-+	else
-+		val = 0x00;
-+
-+	rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &val);
-+
-+	return H2C_SUCCESS;
-+}
-+#endif
-+
-+#ifdef CONFIG_AP_MODE
-+u8 stop_ap_hdl(_adapter *adapter)
-+{
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
-+
-+	rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY);
-+	rtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY);
-+
-+	return H2C_SUCCESS;
-+}
-+#endif
-+
-+u8 setopmode_hdl(_adapter *padapter, u8 *pbuf)
-+{
-+	u8	type;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct setopmode_parm *psetop = (struct setopmode_parm *)pbuf;
-+
-+	if (psetop->mode == Ndis802_11APMode
-+		|| psetop->mode == Ndis802_11_mesh
-+	) {
-+		pmlmeinfo->state = WIFI_FW_AP_STATE;
-+		type = _HW_STATE_AP_;
-+	} else if (psetop->mode == Ndis802_11Infrastructure) {
-+		pmlmeinfo->state &= ~(BIT(0) | BIT(1)); /* clear state */
-+		pmlmeinfo->state |= WIFI_FW_STATION_STATE;/* set to 	STATION_STATE */
-+		type = _HW_STATE_STATION_;
-+	} else if (psetop->mode == Ndis802_11IBSS)
-+		type = _HW_STATE_ADHOC_;
-+	else if (psetop->mode == Ndis802_11Monitor)
-+		type = _HW_STATE_MONITOR_;
-+	else
-+		type = _HW_STATE_NOLINK_;
-+
-+#ifdef CONFIG_AP_PORT_SWAP
-+	rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, (u8 *)(&type));
-+#endif
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_SET_OPMODE, (u8 *)(&type));
-+
-+#ifdef CONFIG_AUTO_AP_MODE
-+	if (psetop->mode == Ndis802_11APMode)
-+		rtw_auto_ap_start_beacon(padapter);
-+#endif
-+
-+	if (rtw_port_switch_chk(padapter) == _TRUE) {
-+		rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
-+
-+		if (psetop->mode == Ndis802_11APMode)
-+			adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff; /* ap mode won't dowload rsvd pages */
-+		else if (psetop->mode == Ndis802_11Infrastructure) {
-+#ifdef CONFIG_LPS
-+			_adapter *port0_iface = dvobj_get_port0_adapter(adapter_to_dvobj(padapter));
-+			if (port0_iface)
-+				rtw_lps_ctrl_wk_cmd(port0_iface, LPS_CTRL_CONNECT, RTW_CMDF_DIRECTLY);
-+#endif
-+		}
-+	}
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if (psetop->mode == Ndis802_11APMode
-+		|| psetop->mode == Ndis802_11_mesh
-+		|| psetop->mode == Ndis802_11Monitor
-+	) {
-+		/* Do this after port switch to */
-+		/* prevent from downloading rsvd page to wrong port */
-+		rtw_btcoex_MediaStatusNotify(padapter, 1); /* connect */
-+	}
-+#endif /* CONFIG_BT_COEXIST */
-+
-+	return H2C_SUCCESS;
-+
-+}
-+
-+u8 createbss_hdl(_adapter *padapter, u8 *pbuf)
-+{
-+#ifdef CONFIG_AP_MODE
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX	*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
-+	WLAN_BSSID_EX	*pdev_network = &padapter->registrypriv.dev_network;
-+	struct createbss_parm *parm = (struct createbss_parm *)pbuf;
-+	u8 ret = H2C_SUCCESS;
-+	/* u8	initialgain; */
-+
-+	if ((parm->req_ch == 0 && pmlmeinfo->state == WIFI_FW_AP_STATE)
-+		|| parm->req_ch != 0
-+	) {
-+		start_bss_network(padapter, parm);
-+		goto exit;
-+	}
-+
-+	/* below is for ad-hoc master */
-+	if (parm->adhoc) {
-+		rtw_warn_on(pdev_network->InfrastructureMode != Ndis802_11IBSS);
-+		rtw_joinbss_reset(padapter);
-+
-+		pmlmeext->cur_bwmode = CHANNEL_WIDTH_20;
-+		pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		pmlmeinfo->ERP_enable = 0;
-+		pmlmeinfo->WMM_enable = 0;
-+		pmlmeinfo->HT_enable = 0;
-+		pmlmeinfo->HT_caps_enable = 0;
-+		pmlmeinfo->HT_info_enable = 0;
-+		pmlmeinfo->agg_enable_bitmap = 0;
-+		pmlmeinfo->candidate_tid_bitmap = 0;
-+
-+		/* cancel link timer */
-+		_cancel_timer_ex(&pmlmeext->link_timer);
-+
-+		/* clear CAM */
-+		flush_all_cam_entry(padapter);
-+
-+		pdev_network->Length = get_WLAN_BSSID_EX_sz(pdev_network);
-+		_rtw_memcpy(pnetwork, pdev_network, FIELD_OFFSET(WLAN_BSSID_EX, IELength));
-+		pnetwork->IELength = pdev_network->IELength;
-+
-+		if (pnetwork->IELength > MAX_IE_SZ) {
-+			ret = H2C_PARAMETERS_ERROR;
-+			goto ibss_post_hdl;
-+		}
-+
-+		_rtw_memcpy(pnetwork->IEs, pdev_network->IEs, pnetwork->IELength);
-+		start_create_ibss(padapter);
-+	} else {
-+		rtw_warn_on(1);
-+		ret = H2C_PARAMETERS_ERROR;
-+	}
-+
-+ibss_post_hdl:
-+	rtw_create_ibss_post_hdl(padapter, ret);
-+
-+exit:
-+	return ret;
-+#else
-+	return H2C_SUCCESS;
-+#endif /* CONFIG_AP_MODE */
-+}
-+
-+u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf)
-+{
-+	u8	join_type;
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	struct joinbss_parm	*pparm = (struct joinbss_parm *)pbuf;
-+#endif /* CONFIG_ANTENNA_DIVERSITY */
-+	u32 i;
-+	/* u8	initialgain; */
-+	/* u32	acparm; */
-+	u8 u_ch, u_bw, u_offset;
-+	u8 doiqk = _FALSE;
-+
-+	/* check already connecting to AP or not */
-+	if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {
-+		if (pmlmeinfo->state & WIFI_FW_STATION_STATE)
-+			issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100);
-+		pmlmeinfo->state = WIFI_FW_NULL_STATE;
-+
-+		/* clear CAM */
-+		flush_all_cam_entry(padapter);
-+
-+		_cancel_timer_ex(&pmlmeext->link_timer);
-+
-+		/* set MSR to nolink->infra. mode		 */
-+		/* Set_MSR(padapter, _HW_STATE_NOLINK_); */
-+		Set_MSR(padapter, _HW_STATE_STATION_);
-+
-+
-+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0);
-+		if (pmlmeinfo->state & WIFI_FW_STATION_STATE)
-+			rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_DISCONNECTED);
-+	}
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	rtw_antenna_select_cmd(padapter, pparm->network.PhyInfo.Optimum_antenna, _FALSE);
-+#endif
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	rtw_wapi_clear_all_cam_entry(padapter);
-+#endif
-+
-+	rtw_joinbss_reset(padapter);
-+
-+	pmlmeinfo->ERP_enable = 0;
-+	pmlmeinfo->WMM_enable = 0;
-+	pmlmeinfo->HT_enable = 0;
-+	pmlmeinfo->HT_caps_enable = 0;
-+	pmlmeinfo->HT_info_enable = 0;
-+	pmlmeinfo->agg_enable_bitmap = 0;
-+	pmlmeinfo->candidate_tid_bitmap = 0;
-+	pmlmeinfo->bwmode_updated = _FALSE;
-+	/* pmlmeinfo->assoc_AP_vendor = HT_IOT_PEER_MAX; */
-+	pmlmeinfo->VHT_enable = 0;
-+#ifdef ROKU_PRIVATE
-+	pmlmeinfo->ht_vht_received = 0;
-+	_rtw_memset(pmlmeinfo->SupportedRates_infra_ap, 0, NDIS_802_11_LENGTH_RATES_EX);
-+#endif /* ROKU_PRIVATE */
-+	_rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength));
-+	pnetwork->IELength = ((WLAN_BSSID_EX *)pbuf)->IELength;
-+
-+	if (pnetwork->IELength > MAX_IE_SZ) /* Check pbuf->IELength */
-+		return H2C_PARAMETERS_ERROR;
-+
-+	if (pnetwork->IELength < 2) {
-+		report_join_res(padapter, (-4), WLAN_STATUS_UNSPECIFIED_FAILURE);
-+		return H2C_SUCCESS;
-+	}
-+	_rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength);
-+
-+	pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork);
-+
-+	/* Check AP vendor to move rtw_joinbss_cmd() */
-+	/* pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->IEs, pnetwork->IELength); */
-+
-+	/* sizeof(NDIS_802_11_FIXED_IEs)	 */
-+	for (i = _FIXED_IE_LENGTH_ ; i < pnetwork->IELength - 2 ;) {
-+		pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i);
-+
-+		switch (pIE->ElementID) {
-+		case _VENDOR_SPECIFIC_IE_: /* Get WMM IE. */
-+			if (_rtw_memcmp(pIE->data, WMM_OUI, 4))
-+				WMM_param_handler(padapter, pIE);
-+			break;
-+
-+#ifdef CONFIG_80211N_HT
-+		case _HT_CAPABILITY_IE_:	/* Get HT Cap IE. */
-+			pmlmeinfo->HT_caps_enable = 1;
-+			break;
-+
-+		case _HT_EXTRA_INFO_IE_:	/* Get HT Info IE. */
-+			pmlmeinfo->HT_info_enable = 1;
-+			break;
-+#endif /* CONFIG_80211N_HT */
-+
-+#ifdef CONFIG_80211AC_VHT
-+		case EID_VHTCapability: /* Get VHT Cap IE. */
-+			pmlmeinfo->VHT_enable = 1;
-+			break;
-+
-+		case EID_VHTOperation: /* Get VHT Operation IE. */
-+			break;
-+#endif /* CONFIG_80211AC_VHT */
-+		default:
-+			break;
-+		}
-+
-+		i += (pIE->Length + 2);
-+	}
-+
-+	rtw_bss_get_chbw(pnetwork
-+		, &pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset, 1, 1);
-+
-+	rtw_adjust_chbw(padapter, pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset);
-+
-+#if 0
-+	if (padapter->registrypriv.wifi_spec) {
-+		/* for WiFi test, follow WMM test plan spec */
-+		acparm = 0x002F431C; /* VO */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm));
-+		acparm = 0x005E541C; /* VI */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm));
-+		acparm = 0x0000A525; /* BE */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
-+		acparm = 0x0000A549; /* BK */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm));
-+
-+		/* for WiFi test, mixed mode with intel STA under bg mode throughput issue */
-+		if (padapter->mlmepriv.htpriv.ht_option == _FALSE) {
-+			acparm = 0x00004320;
-+			rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
-+		}
-+	} else {
-+		acparm = 0x002F3217; /* VO */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm));
-+		acparm = 0x005E4317; /* VI */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm));
-+		acparm = 0x00105320; /* BE */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm));
-+		acparm = 0x0000A444; /* BK */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm));
-+	}
-+#endif
-+
-+	/* check channel, bandwidth, offset and switch */
-+	if (rtw_chk_start_clnt_join(padapter, &u_ch, &u_bw, &u_offset) == _FAIL) {
-+		report_join_res(padapter, (-4), WLAN_STATUS_UNSPECIFIED_FAILURE);
-+		return H2C_SUCCESS;
-+	}
-+
-+	/* disable dynamic functions, such as high power, DIG */
-+	/*rtw_phydm_func_disable_all(padapter);*/
-+
-+	/* config the initial gain under linking, need to write the BB registers */
-+	/* initialgain = 0x1E; */
-+	/*rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);*/
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
-+	if (MLME_IS_STA(padapter))
-+		rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING);
-+	else
-+		rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
-+
-+	join_type = 0;
-+	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
-+
-+	rtw_btcoex_connect_notify(padapter, join_type);
-+
-+	doiqk = _TRUE;
-+	rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
-+
-+	set_channel_bwmode(padapter, u_ch, u_offset, u_bw);
-+
-+	doiqk = _FALSE;
-+	rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
-+
-+	/* cancel link timer */
-+	_cancel_timer_ex(&pmlmeext->link_timer);
-+
-+	start_clnt_join(padapter);
-+
-+	return H2C_SUCCESS;
-+
-+}
-+
-+u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf)
-+{
-+#if CONFIG_DFS
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+#endif
-+	struct disconnect_parm *param = (struct disconnect_parm *)pbuf;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
-+	u8 val8;
-+
-+	if (is_client_associated_to_ap(padapter)
-+		#if CONFIG_DFS
-+		&& !IS_RADAR_DETECTED(rfctl) && !rfctl->csa_ch
-+		#endif
-+	) {
-+		#ifdef CONFIG_PLATFORM_ROCKCHIPS
-+		/* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */
-+		issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100);
-+		#else
-+		issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, param->deauth_timeout_ms / 100, 100);
-+		#endif /* CONFIG_PLATFORM_ROCKCHIPS */
-+	}
-+
-+#ifndef CONFIG_SUPPORT_MULTI_BCN
-+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
-+		/* Stop BCN */
-+		val8 = 0;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_FUNC, (u8 *)(&val8));
-+	}
-+#endif
-+
-+	rtw_sta_mstatus_report(padapter);
-+	
-+	rtw_mlmeext_disconnect(padapter);
-+
-+	rtw_free_uc_swdec_pending_queue(padapter);
-+
-+	return	H2C_SUCCESS;
-+}
-+
-+static const char *const _scan_state_str[] = {
-+	"SCAN_DISABLE",
-+	"SCAN_START",
-+	"SCAN_PS_ANNC_WAIT",
-+	"SCAN_ENTER",
-+	"SCAN_PROCESS",
-+	"SCAN_BACKING_OP",
-+	"SCAN_BACK_OP",
-+	"SCAN_LEAVING_OP",
-+	"SCAN_LEAVE_OP",
-+	"SCAN_SW_ANTDIV_BL",
-+	"SCAN_TO_P2P_LISTEN",
-+	"SCAN_P2P_LISTEN",
-+	"SCAN_COMPLETE",
-+	"SCAN_STATE_MAX",
-+};
-+
-+const char *scan_state_str(u8 state)
-+{
-+	state = (state >= SCAN_STATE_MAX) ? SCAN_STATE_MAX : state;
-+	return _scan_state_str[state];
-+}
-+
-+static bool scan_abort_hdl(_adapter *adapter)
-+{
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	struct ss_res *ss = &pmlmeext->sitesurvey_res;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &adapter->wdinfo;
-+#endif
-+	bool ret = _FALSE;
-+
-+	if (pmlmeext->scan_abort == _TRUE) {
-+#ifdef CONFIG_P2P
-+		if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) {
-+			rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_MAX);
-+			ss->channel_idx = 3;
-+			RTW_INFO("%s idx:%d, cnt:%u\n", __FUNCTION__
-+				 , ss->channel_idx
-+				 , pwdinfo->find_phase_state_exchange_cnt
-+				);
-+		} else
-+#endif
-+		{
-+			ss->channel_idx = ss->ch_num;
-+			RTW_INFO("%s idx:%d\n", __FUNCTION__
-+				 , ss->channel_idx
-+				);
-+		}
-+		ret = _TRUE;
-+	}
-+
-+	return ret;
-+}
-+
-+u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_num)
-+{
-+	/* interval larger than this is treated as backgroud scan */
-+#ifndef RTW_SCAN_SPARSE_BG_INTERVAL_MS
-+#define RTW_SCAN_SPARSE_BG_INTERVAL_MS 12000
-+#endif
-+
-+#ifndef RTW_SCAN_SPARSE_CH_NUM_MIRACAST
-+#define RTW_SCAN_SPARSE_CH_NUM_MIRACAST 1
-+#endif
-+#ifndef RTW_SCAN_SPARSE_CH_NUM_BG
-+#define RTW_SCAN_SPARSE_CH_NUM_BG 4
-+#endif
-+#ifdef CONFIG_LAYER2_ROAMING
-+#ifndef RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE
-+#define RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE 1
-+#endif
-+#endif
-+
-+#define SCAN_SPARSE_CH_NUM_INVALID 255
-+
-+	static u8 token = 255;
-+	u32 interval;
-+	bool busy_traffic = _FALSE;
-+	bool miracast_enabled = _FALSE;
-+	bool bg_scan = _FALSE;
-+	u8 max_allow_ch = SCAN_SPARSE_CH_NUM_INVALID;
-+	u8 scan_division_num;
-+	u8 ret_num = ch_num;
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+
-+	if (mlmeext->last_scan_time == 0)
-+		mlmeext->last_scan_time = rtw_get_current_time();
-+
-+	interval = rtw_get_passing_time_ms(mlmeext->last_scan_time);
-+
-+
-+	if (rtw_mi_busy_traffic_check(adapter))
-+		busy_traffic = _TRUE;
-+
-+	if (rtw_mi_check_miracast_enabled(adapter))
-+		miracast_enabled = _TRUE;
-+
-+	if (interval > RTW_SCAN_SPARSE_BG_INTERVAL_MS)
-+		bg_scan = _TRUE;
-+
-+	/* max_allow_ch by conditions*/
-+
-+#if RTW_SCAN_SPARSE_MIRACAST
-+	if (miracast_enabled == _TRUE && busy_traffic == _TRUE)
-+		max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_MIRACAST);
-+#endif
-+
-+#if RTW_SCAN_SPARSE_BG
-+	if (bg_scan == _TRUE)
-+		max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_BG);
-+#endif
-+
-+#if  defined(CONFIG_LAYER2_ROAMING) && defined(RTW_SCAN_SPARSE_ROAMING_ACTIVE)
-+	if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) {
-+		if (busy_traffic == _TRUE && adapter->mlmepriv.need_to_roam == _TRUE)
-+			max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE);
-+	}
-+#endif
-+
-+
-+	if (max_allow_ch != SCAN_SPARSE_CH_NUM_INVALID) {
-+		int i;
-+		int k = 0;
-+
-+		scan_division_num = (ch_num / max_allow_ch) + ((ch_num % max_allow_ch) ? 1 : 0);
-+		token = (token + 1) % scan_division_num;
-+
-+		if (0)
-+			RTW_INFO("scan_division_num:%u, token:%u\n", scan_division_num, token);
-+
-+		for (i = 0; i < ch_num; i++) {
-+			if (ch[i].hw_value && (i % scan_division_num) == token
-+			   ) {
-+				if (i != k)
-+					_rtw_memcpy(&ch[k], &ch[i], sizeof(struct rtw_ieee80211_channel));
-+				k++;
-+			}
-+		}
-+
-+		_rtw_memset(&ch[k], 0, sizeof(struct rtw_ieee80211_channel));
-+
-+		ret_num = k;
-+		mlmeext->last_scan_time = rtw_get_current_time();
-+	}
-+
-+	return ret_num;
-+}
-+
-+#ifdef CONFIG_SCAN_BACKOP
-+u8 rtw_scan_backop_decision(_adapter *adapter)
-+{
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+	struct mi_state mstate;
-+	u8 backop_flags = 0;
-+
-+	rtw_mi_status(adapter, &mstate);
-+
-+	if ((MSTATE_STA_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(mlmeext, SS_BACKOP_EN))
-+		|| (MSTATE_STA_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(mlmeext, SS_BACKOP_EN_NL)))
-+		backop_flags |= mlmeext_scan_backop_flags_sta(mlmeext);
-+
-+#ifdef CONFIG_AP_MODE
-+	if ((MSTATE_AP_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(mlmeext, SS_BACKOP_EN))
-+		|| (MSTATE_AP_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(mlmeext, SS_BACKOP_EN_NL)))
-+		backop_flags |= mlmeext_scan_backop_flags_ap(mlmeext);
-+#endif
-+
-+#ifdef CONFIG_RTW_MESH
-+	if ((MSTATE_MESH_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_mesh(mlmeext, SS_BACKOP_EN))
-+		|| (MSTATE_MESH_NUM(&mstate) && mlmeext_chk_scan_backop_flags_mesh(mlmeext, SS_BACKOP_EN_NL)))
-+		backop_flags |= mlmeext_scan_backop_flags_mesh(mlmeext);
-+#endif
-+
-+	return backop_flags;
-+}
-+#endif
-+
-+#define SCANNING_TIMEOUT_EX	2000
-+u32 rtw_scan_timeout_decision(_adapter *padapter)
-+{
-+	u32 back_op_times= 0;
-+	u8 max_chan_num;
-+	u16 scan_ms;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct ss_res *ss = &pmlmeext->sitesurvey_res;
-+
-+	if (is_supported_5g(padapter->registrypriv.wireless_mode)
-+		&& IsSupported24G(padapter->registrypriv.wireless_mode)) 
-+		max_chan_num = MAX_CHANNEL_NUM;/* dual band */
-+	else
-+		max_chan_num = MAX_CHANNEL_NUM_2G;/*single band*/
-+
-+	#ifdef CONFIG_SCAN_BACKOP
-+	if (rtw_scan_backop_decision(padapter))
-+		back_op_times = (max_chan_num / ss->scan_cnt_max) * ss->backop_ms;
-+	#endif
-+
-+	if (ss->duration)
-+		scan_ms = ss->duration;
-+	else
-+	#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
-+	if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter))
-+		scan_ms = rtw_acs_get_adv_st(padapter);
-+	else
-+	#endif /*CONFIG_RTW_ACS*/
-+		scan_ms = ss->scan_ch_ms;
-+
-+	ss->scan_timeout_ms = (scan_ms * max_chan_num) + back_op_times + SCANNING_TIMEOUT_EX;
-+	#ifdef DBG_SITESURVEY
-+	RTW_INFO("%s , scan_timeout_ms = %d (ms)\n", __func__, ss->scan_timeout_ms);
-+	#endif /*DBG_SITESURVEY*/
-+	return ss->scan_timeout_ms;
-+}
-+
-+static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out,
-+		u32 out_num, struct rtw_ieee80211_channel *in, u32 in_num, bool no_sparse)
-+{
-+	int i, j;
-+	int set_idx;
-+	u8 chan;
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(padapter));
-+
-+	/* clear first */
-+	_rtw_memset(out, 0, sizeof(struct rtw_ieee80211_channel) * out_num);
-+
-+	/* acquire channels from in */
-+	j = 0;
-+	for (i = 0; i < in_num; i++) {
-+
-+		if (0)
-+			RTW_INFO(FUNC_ADPT_FMT" "CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(&in[i]));
-+
-+		if (!in[i].hw_value || (in[i].flags & RTW_IEEE80211_CHAN_DISABLED))
-+			continue;
-+		if (rtw_mlme_band_check(padapter, in[i].hw_value) == _FALSE)
-+			continue;
-+
-+		set_idx = rtw_chset_search_ch(rfctl->channel_set, in[i].hw_value);
-+		if (set_idx >= 0) {
-+			if (j >= out_num) {
-+				RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n",
-+					  FUNC_ADPT_ARG(padapter), out_num);
-+				break;
-+			}
-+
-+			_rtw_memcpy(&out[j], &in[i], sizeof(struct rtw_ieee80211_channel));
-+
-+			if (rfctl->channel_set[set_idx].flags & (RTW_CHF_NO_IR | RTW_CHF_DFS))
-+				out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN;
-+
-+			j++;
-+		}
-+		if (j >= out_num)
-+			break;
-+	}
-+
-+	/* if out is empty, use channel_set as default */
-+	if (j == 0) {
-+		for (i = 0; i < rfctl->max_chan_nums; i++) {
-+			chan = rfctl->channel_set[i].ChannelNum;
-+			if (rtw_mlme_band_check(padapter, chan) == _TRUE) {
-+				if (rtw_mlme_ignore_chan(padapter, chan) == _TRUE)
-+					continue;
-+
-+				if (0)
-+					RTW_INFO(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter), chan);
-+
-+				if (j >= out_num) {
-+					RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n",
-+						FUNC_ADPT_ARG(padapter), out_num);
-+					break;
-+				}
-+
-+				out[j].hw_value = chan;
-+
-+				if (rfctl->channel_set[i].flags & (RTW_CHF_NO_IR | RTW_CHF_DFS))
-+					out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN;
-+
-+				j++;
-+			}
-+		}
-+	}
-+
-+	if (!no_sparse
-+		&& !regsty->wifi_spec
-+		&& j > 6 /* assume ch_num > 6 is normal scan */
-+	) {
-+		/* scan_sparse */
-+		j = rtw_scan_sparse(padapter, out, j);
-+	}
-+
-+	return j;
-+}
-+
-+static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm)
-+{
-+	struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res;
-+	RT_CHANNEL_INFO *chset = adapter_to_chset(adapter);
-+	int i;
-+
-+	ss->bss_cnt = 0;
-+	ss->activate_ch_cnt = 0;
-+	ss->channel_idx = 0;
-+	ss->force_ssid_scan = 0;
-+	ss->igi_scan = 0;
-+	ss->igi_before_scan = 0;
-+#ifdef CONFIG_SCAN_BACKOP
-+	ss->scan_cnt = 0;
-+#endif
-+#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
-+	ss->is_sw_antdiv_bl_scan = 0;
-+#endif
-+	ss->ssid_num = 0;
-+	for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) {
-+		if (parm->ssid[i].SsidLength) {
-+			_rtw_memcpy(ss->ssid[i].Ssid, parm->ssid[i].Ssid, IW_ESSID_MAX_SIZE);
-+			ss->ssid[i].SsidLength = parm->ssid[i].SsidLength;
-+			ss->ssid_num++;
-+		} else
-+			ss->ssid[i].SsidLength = 0;
-+	}
-+
-+	ss->ch_num = rtw_scan_ch_decision(adapter
-+					, ss->ch, RTW_CHANNEL_SCAN_AMOUNT
-+					, parm->ch, parm->ch_num
-+					, parm->acs
-+				);
-+
-+	for (i = 0; i < MAX_CHANNEL_NUM; i++)
-+		chset[i].hidden_bss_cnt = 0;
-+
-+	ss->bw = parm->bw;
-+	ss->igi = parm->igi;
-+	ss->token = parm->token;
-+	ss->duration = parm->duration;
-+	ss->scan_mode = parm->scan_mode;
-+	ss->token = parm->token;
-+	ss->acs = parm->acs;
-+}
-+
-+static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE *type)
-+{
-+	u8 next_state;
-+	u8 scan_ch = 0;
-+	RT_SCAN_TYPE scan_type = SCAN_PASSIVE;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct ss_res *ss = &pmlmeext->sitesurvey_res;
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	int ch_set_idx;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
-+#endif
-+#ifdef CONFIG_SCAN_BACKOP
-+	u8 backop_flags = 0;
-+#endif
-+
-+	/* handle scan abort request */
-+	scan_abort_hdl(padapter);
-+
-+#ifdef CONFIG_P2P
-+	if (pwdinfo->rx_invitereq_info.scan_op_ch_only || pwdinfo->p2p_info.scan_op_ch_only) {
-+		if (pwdinfo->rx_invitereq_info.scan_op_ch_only)
-+			scan_ch = pwdinfo->rx_invitereq_info.operation_ch[ss->channel_idx];
-+		else
-+			scan_ch = pwdinfo->p2p_info.operation_ch[ss->channel_idx];
-+		scan_type = SCAN_ACTIVE;
-+	} else if (rtw_p2p_findphase_ex_is_social(pwdinfo)) {
-+		/*
-+		* Commented by Albert 2011/06/03
-+		* The driver is in the find phase, it should go through the social channel.
-+		*/
-+		scan_ch = pwdinfo->social_chan[ss->channel_idx];
-+		ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scan_ch);
-+		if (ch_set_idx >= 0)
-+			scan_type = rfctl->channel_set[ch_set_idx].flags & RTW_CHF_NO_IR ? SCAN_PASSIVE : SCAN_ACTIVE;
-+		else
-+			scan_type = SCAN_ACTIVE;
-+	} else
-+#endif /* CONFIG_P2P */
-+	{
-+		struct rtw_ieee80211_channel *ch;
-+
-+		#ifdef CONFIG_SCAN_BACKOP
-+		backop_flags = rtw_scan_backop_decision(padapter);
-+		#endif
-+
-+		#ifdef CONFIG_SCAN_BACKOP
-+		if (!(backop_flags && ss->scan_cnt >= ss->scan_cnt_max))
-+		#endif
-+		{
-+			#ifdef CONFIG_RTW_WIFI_HAL
-+			if (adapter_to_dvobj(padapter)->nodfs) {
-+				while (ss->channel_idx < ss->ch_num && rtw_chset_is_dfs_ch(rfctl->channel_set, ss->ch[ss->channel_idx].hw_value))
-+					ss->channel_idx++;
-+			} else
-+			#endif
-+			if (ss->channel_idx != 0 && ss->force_ssid_scan == 0
-+				&& pmlmeext->sitesurvey_res.ssid_num
-+				&& (ss->ch[ss->channel_idx - 1].flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN)
-+			) {
-+				ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, ss->ch[ss->channel_idx - 1].hw_value);
-+				if (ch_set_idx != -1 && rfctl->channel_set[ch_set_idx].hidden_bss_cnt
-+					&& (!IS_DFS_SLAVE_WITH_RD(rfctl)
-+						|| rtw_rfctl_dfs_domain_unknown(rfctl)
-+						|| !CH_IS_NON_OCP(&rfctl->channel_set[ch_set_idx]))
-+				) {
-+					ss->channel_idx--;
-+					ss->force_ssid_scan = 1;
-+				}
-+			} else
-+				ss->force_ssid_scan = 0;
-+		}
-+
-+		if (ss->channel_idx < ss->ch_num) {
-+			ch = &ss->ch[ss->channel_idx];
-+			scan_ch = ch->hw_value;
-+
-+			#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
-+			if (IS_ACS_ENABLE(padapter) && rtw_is_acs_passiv_scan(padapter))
-+				scan_type = SCAN_PASSIVE;
-+			else
-+			#endif /*CONFIG_RTW_ACS*/
-+				scan_type = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE;
-+		}
-+	}
-+
-+	if (scan_ch != 0) {
-+		next_state = SCAN_PROCESS;
-+
-+		#ifdef CONFIG_SCAN_BACKOP
-+		if (backop_flags) {
-+			if (ss->scan_cnt < ss->scan_cnt_max)
-+				ss->scan_cnt++;
-+			else {
-+				mlmeext_assign_scan_backop_flags(pmlmeext, backop_flags);
-+				next_state = SCAN_BACKING_OP;
-+			}
-+		}
-+		#endif
-+
-+	} else if (rtw_p2p_findphase_ex_is_needed(pwdinfo)) {
-+		/* go p2p listen */
-+		next_state = SCAN_TO_P2P_LISTEN;
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	} else if (rtw_hal_antdiv_before_linked(padapter)) {
-+		/* go sw antdiv before link */
-+		next_state = SCAN_SW_ANTDIV_BL;
-+#endif
-+	} else {
-+		next_state = SCAN_COMPLETE;
-+
-+#if defined(DBG_SCAN_SW_ANTDIV_BL)
-+		{
-+			/* for SCAN_SW_ANTDIV_BL state testing */
-+			struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+			int i;
-+			bool is_linked = _FALSE;
-+
-+			for (i = 0; i < dvobj->iface_nums; i++) {
-+				if (rtw_linked_check(dvobj->padapters[i]))
-+					is_linked = _TRUE;
-+			}
-+
-+			if (!is_linked) {
-+				static bool fake_sw_antdiv_bl_state = 0;
-+
-+				if (fake_sw_antdiv_bl_state == 0) {
-+					next_state = SCAN_SW_ANTDIV_BL;
-+					fake_sw_antdiv_bl_state = 1;
-+				} else
-+					fake_sw_antdiv_bl_state = 0;
-+			}
-+		}
-+#endif /* defined(DBG_SCAN_SW_ANTDIV_BL) */
-+	}
-+
-+#ifdef CONFIG_SCAN_BACKOP
-+	if (next_state != SCAN_PROCESS)
-+		ss->scan_cnt = 0;
-+#endif
-+
-+
-+#ifdef DBG_FIXED_CHAN
-+	if (pmlmeext->fixed_chan != 0xff && next_state == SCAN_PROCESS)
-+		scan_ch = pmlmeext->fixed_chan;
-+#endif
-+
-+	if (ch)
-+		*ch = scan_ch;
-+	if (type)
-+		*type = scan_type;
-+
-+	return next_state;
-+}
-+
-+void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType)
-+{
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct ss_res *ss = &pmlmeext->sitesurvey_res;
-+	u8 ssid_scan = 0;
-+
-+#ifdef CONFIG_P2P
-+#ifndef CONFIG_IOCTL_CFG80211
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+#endif
-+#endif
-+
-+	if (survey_channel != 0) {
-+		set_channel_bwmode(padapter, survey_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+
-+		if (ScanType == SCAN_PASSIVE && ss->force_ssid_scan)
-+			ssid_scan = 1;
-+		else if (ScanType == SCAN_ACTIVE) {
-+#ifdef CONFIG_P2P
-+			#ifdef CONFIG_IOCTL_CFG80211
-+			if (rtw_cfg80211_is_p2p_scan(padapter))
-+			#else
-+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN)
-+				|| rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH))
-+			#endif
-+			{
-+				issue_probereq_p2p(padapter, NULL);
-+				issue_probereq_p2p(padapter, NULL);
-+				issue_probereq_p2p(padapter, NULL);
-+			} else
-+#endif /* CONFIG_P2P */
-+			{
-+				if (pmlmeext->sitesurvey_res.scan_mode == SCAN_ACTIVE) {
-+					/* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */
-+					if (padapter->registrypriv.wifi_spec)
-+						issue_probereq(padapter, NULL, NULL);
-+					else
-+						issue_probereq_ex(padapter, NULL, NULL, 0, 0, 0, 0);
-+					issue_probereq(padapter, NULL, NULL);
-+				}
-+
-+				ssid_scan = 1;
-+			}
-+		}
-+
-+		if (ssid_scan) {
-+			int i;
-+
-+			for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) {
-+				if (pmlmeext->sitesurvey_res.ssid[i].SsidLength) {
-+					/* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */
-+					if (padapter->registrypriv.wifi_spec)
-+						issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL);
-+					else
-+						issue_probereq_ex(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL, 0, 0, 0, 0);
-+					issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL);
-+				}
-+			}
-+		}
-+	} else {
-+		/* channel number is 0 or this channel is not valid. */
-+		rtw_warn_on(1);
-+	}
-+
-+	return;
-+}
-+
-+void survey_done_set_ch_bw(_adapter *padapter)
-+{
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	u8 cur_channel = 0;
-+	u8 cur_bwmode;
-+	u8 cur_ch_offset;
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (!rtw_hal_mcc_change_scan_flag(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset)) {
-+		if (0)
-+			RTW_INFO(FUNC_ADPT_FMT" back to AP channel - ch:%u, bw:%u, offset:%u\n",
-+				FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset);
-+		goto exit;
-+	}
-+#endif
-+
-+	if (rtw_mi_get_ch_setting_union(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset) != 0) {
-+		if (0)
-+			RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n",
-+				FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset);
-+	} else {
-+#ifdef CONFIG_P2P
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+		_adapter *iface;
-+		int i;
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			if (!iface)
-+				continue;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+			if (iface->wdinfo.driver_interface == DRIVER_CFG80211 && !adapter_wdev_data(iface)->p2p_enabled)
-+				continue;
-+#endif
-+
-+			if (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN)) {
-+				cur_channel = iface->wdinfo.listen_channel;
-+				cur_bwmode = CHANNEL_WIDTH_20;
-+				cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+				if (0)
-+					RTW_INFO(FUNC_ADPT_FMT" back to "ADPT_FMT"'s listen ch - ch:%u, bw:%u, offset:%u\n",
-+						FUNC_ADPT_ARG(padapter), ADPT_ARG(iface), cur_channel, cur_bwmode, cur_ch_offset);
-+				break;
-+			}
-+		}
-+#endif /* CONFIG_P2P */
-+
-+		if (cur_channel == 0) {
-+			cur_channel = pmlmeext->cur_channel;
-+			cur_bwmode = pmlmeext->cur_bwmode;
-+			cur_ch_offset = pmlmeext->cur_ch_offset;
-+			if (0)
-+				RTW_INFO(FUNC_ADPT_FMT" back to ch:%u, bw:%u, offset:%u\n",
-+					FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset);
-+		}
-+	}
-+#ifdef CONFIG_MCC_MODE
-+exit:
-+#endif
-+	set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode);
-+}
-+
-+/**
-+ * rtw_ps_annc - check and doing ps announcement for all the adapters
-+ * @adapter: the requesting adapter
-+ * @ps: power saving or not
-+ *
-+ * Returns: 0: no ps announcement is doing. 1: ps announcement is doing
-+ */
-+u8 rtw_ps_annc(_adapter *adapter, bool ps)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	_adapter *iface;
-+	int i;
-+	u8 ps_anc = 0;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+
-+		if (MLME_IS_STA(iface)) {
-+			if (is_client_associated_to_ap(iface) == _TRUE) {
-+				/* TODO: TDLS peers */
-+				#ifdef CONFIG_MCC_MODE
-+				/* for two station case */
-+				if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_NEED_MCC)) {
-+					u8 ch = iface->mlmeextpriv.cur_channel;
-+					u8 offset = iface->mlmeextpriv.cur_ch_offset;
-+					u8 bw = iface->mlmeextpriv.cur_bwmode;
-+
-+					set_channel_bwmode(iface, ch, offset, bw);
-+				}
-+				#endif /* CONFIG_MCC_MODE */
-+				issue_nulldata(iface, NULL, ps, 3, 500);
-+				ps_anc = 1;
-+			}
-+		#ifdef CONFIG_RTW_MESH
-+		} else if (MLME_IS_MESH(iface)) {
-+			if (rtw_mesh_ps_annc(iface, ps))
-+				ps_anc = 1;
-+		#endif
-+		}
-+	}
-+	return ps_anc;
-+}
-+
-+void rtw_leave_opch(_adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
-+		return;
-+#endif
-+
-+	_enter_critical_mutex(&rfctl->offch_mutex, NULL);
-+
-+	if (rfctl->offch_state == OFFCHS_NONE) {
-+		/* prepare to leave operating channel */
-+		rfctl->offch_state = OFFCHS_LEAVING_OP;
-+
-+		/* clear HW TX queue */
-+		rtw_hal_set_hwreg(adapter, HW_VAR_CHECK_TXBUF, 0);
-+
-+		rtw_hal_macid_sleep_all_used(adapter);
-+
-+		rtw_ps_annc(adapter, 1);
-+
-+		rfctl->offch_state = OFFCHS_LEAVE_OP;
-+	}
-+
-+	_exit_critical_mutex(&rfctl->offch_mutex, NULL);
-+}
-+
-+void rtw_back_opch(_adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
-+		return;
-+#endif
-+
-+	_enter_critical_mutex(&rfctl->offch_mutex, NULL);
-+
-+	if (rfctl->offch_state != OFFCHS_NONE) {
-+		rfctl->offch_state = OFFCHS_BACKING_OP;
-+		rtw_hal_macid_wakeup_all_used(adapter);
-+		rtw_ps_annc(adapter, 0);
-+
-+		rfctl->offch_state = OFFCHS_NONE;
-+		rtw_mi_os_xmit_schedule(adapter);
-+	}
-+
-+	_exit_critical_mutex(&rfctl->offch_mutex, NULL);
-+}
-+
-+void sitesurvey_set_igi(_adapter *adapter)
-+{
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+	struct ss_res *ss = &mlmeext->sitesurvey_res;
-+	u8 igi;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &adapter->wdinfo;
-+#endif
-+
-+	switch (mlmeext_scan_state(mlmeext)) {
-+	case SCAN_ENTER:
-+		#ifdef CONFIG_P2P
-+		#ifdef CONFIG_IOCTL_CFG80211
-+		if (pwdinfo->driver_interface == DRIVER_CFG80211 && rtw_cfg80211_is_p2p_scan(adapter))
-+			igi = 0x30;
-+		else
-+		#endif /* CONFIG_IOCTL_CFG80211 */
-+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
-+			igi = 0x28;
-+		else
-+		#endif /* CONFIG_P2P */
-+
-+		if (ss->igi)
-+			igi = ss->igi;
-+		else
-+		#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
-+		if (IS_ACS_ENABLE(adapter) && rtw_is_acs_igi_valid(adapter))
-+			igi = rtw_acs_get_adv_igi(adapter);
-+		else
-+		#endif /*CONFIG_RTW_ACS*/
-+			igi = 0x1e;
-+
-+		/* record IGI status */
-+		ss->igi_scan = igi;
-+		rtw_hal_get_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &ss->igi_before_scan, NULL);
-+
-+		/* disable DIG and set IGI for scan */
-+		rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE);
-+		break;
-+	case SCAN_COMPLETE:
-+	case SCAN_TO_P2P_LISTEN:
-+		/* enable DIG and restore IGI */
-+		igi = 0xff;
-+		rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE);
-+		break;
-+#ifdef CONFIG_SCAN_BACKOP
-+	case SCAN_BACKING_OP:
-+		/* write IGI for op channel when DIG is not enabled */
-+		odm_write_dig(adapter_to_phydm(adapter), ss->igi_before_scan);
-+		break;
-+	case SCAN_LEAVE_OP:
-+		/* write IGI for scan when DIG is not enabled */
-+		odm_write_dig(adapter_to_phydm(adapter), ss->igi_scan);
-+		break;
-+#endif /* CONFIG_SCAN_BACKOP */
-+	default:
-+		rtw_warn_on(1);
-+		break;
-+	}
-+}
-+void sitesurvey_set_msr(_adapter *adapter, bool enter)
-+{
-+	u8 network_type;
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if (enter) {
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+		rtw_hal_get_hwreg(adapter, HW_VAR_MEDIA_STATUS, (u8 *)(&pmlmeinfo->hw_media_state));
-+#endif
-+		/* set MSR to no link state */
-+		network_type = _HW_STATE_NOLINK_;
-+	} else {
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+		network_type = pmlmeinfo->hw_media_state;
-+#else
-+		network_type = pmlmeinfo->state & 0x3;
-+#endif
-+	}
-+	Set_MSR(adapter, network_type);
-+}
-+
-+void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	_enter_critical_mutex(&rfctl->offch_mutex, NULL);
-+
-+	switch (scan_state) {
-+	case SCAN_DISABLE:
-+	case SCAN_BACK_OP:
-+		rfctl->offch_state = OFFCHS_NONE;
-+		break;
-+	case SCAN_START:
-+	case SCAN_LEAVING_OP:
-+		rfctl->offch_state = OFFCHS_LEAVING_OP;
-+		break;
-+	case SCAN_ENTER:
-+	case SCAN_LEAVE_OP:
-+		rfctl->offch_state = OFFCHS_LEAVE_OP;
-+		break;
-+	case SCAN_COMPLETE:
-+	case SCAN_BACKING_OP:
-+		rfctl->offch_state = OFFCHS_BACKING_OP;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	_exit_critical_mutex(&rfctl->offch_mutex, NULL);
-+}
-+
-+u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
-+{
-+	struct sitesurvey_parm	*pparm = (struct sitesurvey_parm *)pbuf;
-+#ifdef DBG_CHECK_FW_PS_STATE
-+	struct dvobj_priv *dvobj = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
-+#endif
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct ss_res *ss = &pmlmeext->sitesurvey_res;
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+		struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+#endif
-+	u8 val8;
-+
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
-+#ifdef CONFIG_CONCURRENT_MODE
-+	struct roch_info *prochinfo = &padapter->rochinfo;
-+#endif
-+#endif
-+
-+#ifdef DBG_CHECK_FW_PS_STATE
-+	if (rtw_fw_ps_state(padapter) == _FAIL) {
-+		RTW_INFO("scan without leave 32k\n");
-+		pdbgpriv->dbg_scan_pwr_state_cnt++;
-+	}
-+#endif /* DBG_CHECK_FW_PS_STATE */
-+
-+	/* increase channel idx */
-+	if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS))
-+		ss->channel_idx++;
-+
-+	/* update scan state to next state (assigned by previous cmd hdl) */
-+	if (mlmeext_scan_state(pmlmeext) != mlmeext_scan_next_state(pmlmeext))
-+		mlmeext_set_scan_state(pmlmeext, mlmeext_scan_next_state(pmlmeext));
-+
-+operation_by_state:
-+	switch (mlmeext_scan_state(pmlmeext)) {
-+
-+	case SCAN_DISABLE:
-+		/*
-+		* SW parameter initialization
-+		*/
-+
-+		sitesurvey_res_reset(padapter, pparm);
-+		mlmeext_set_scan_state(pmlmeext, SCAN_START);
-+		goto operation_by_state;
-+
-+	case SCAN_START:
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+		if ((pwdev_priv->pno_mac_addr[0] != 0xFF)
-+			    && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)
-+	    	    && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE)) {
-+			u16 seq_num;
-+
-+			rtw_hal_pno_random_gen_mac_addr(padapter);
-+			rtw_hal_set_hw_mac_addr(padapter, pwdev_priv->pno_mac_addr);
-+			get_random_bytes(&seq_num, 2);
-+			pwdev_priv->pno_scan_seq_num = seq_num & 0xFFF;
-+			RTW_INFO("%s pno_scan_seq_num %d\n", __func__,
-+				 pwdev_priv->pno_scan_seq_num);
-+		}
-+#endif
-+
-+		/*
-+		* prepare to leave operating channel
-+		*/
-+
-+#ifdef CONFIG_MCC_MODE
-+		rtw_hal_set_mcc_setting_scan_start(padapter);
-+#endif /* CONFIG_MCC_MODE */
-+
-+		/* apply rx ampdu setting */
-+		if (ss->rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID
-+			|| ss->rx_ampdu_size != RX_AMPDU_SIZE_INVALID)
-+			rtw_rx_ampdu_apply(padapter);
-+
-+		/* clear HW TX queue before scan */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
-+
-+		rtw_hal_macid_sleep_all_used(padapter);
-+
-+		/* power save state announcement */
-+		if (rtw_ps_annc(padapter, 1)) {
-+			mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT);
-+			mlmeext_set_scan_next_state(pmlmeext, SCAN_ENTER);
-+			set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */
-+		} else {
-+			mlmeext_set_scan_state(pmlmeext, SCAN_ENTER);
-+			goto operation_by_state;
-+		}
-+
-+		break;
-+
-+	case SCAN_ENTER:
-+		/*
-+		* HW register and DM setting for enter scan
-+		*/
-+
-+		rtw_phydm_ability_backup(padapter);
-+
-+		sitesurvey_set_igi(padapter);
-+
-+		/* config dynamic functions for off channel */
-+		rtw_phydm_func_for_offchannel(padapter);
-+		/* set MSR to no link state */
-+		sitesurvey_set_msr(padapter, _TRUE);
-+
-+		val8 = 1; /* under site survey */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+
-+		mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS);
-+		goto operation_by_state;
-+
-+	case SCAN_PROCESS: {
-+		u8 scan_ch;
-+		RT_SCAN_TYPE scan_type;
-+		u8 next_state;
-+		u32 scan_ms;
-+
-+#ifdef CONFIG_RTW_ACS
-+		if (IS_ACS_ENABLE(padapter))
-+			rtw_acs_get_rst(padapter);
-+#endif
-+
-+		next_state = sitesurvey_pick_ch_behavior(padapter, &scan_ch, &scan_type);
-+
-+		if (next_state != SCAN_PROCESS) {
-+			mlmeext_set_scan_state(pmlmeext, next_state);
-+			goto operation_by_state;
-+		}
-+
-+		/* still SCAN_PROCESS state */
-+		#ifdef DBG_SITESURVEY
-+			#ifdef CONFIG_P2P
-+			RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (cnt:%u,idx:%d) at %dms, %c%c%c%c\n"
-+				, FUNC_ADPT_ARG(padapter)
-+				, mlmeext_scan_state_str(pmlmeext)
-+				, scan_ch
-+				, pwdinfo->find_phase_state_exchange_cnt, ss->channel_idx
-+				, rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time)
-+				, scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P'
-+				, ss->ssid[0].SsidLength ? 'S' : ' '
-+				, ss->force_ssid_scan ? 'F' : ' '
-+			);
-+			#else
-+			RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (idx:%d) at %dms, %c%c%c%c\n"
-+				, FUNC_ADPT_ARG(padapter)
-+				, mlmeext_scan_state_str(pmlmeext)
-+				, scan_ch
-+				, ss->channel_idx
-+				, rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time)
-+				, scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P'
-+				, ss->ssid[0].SsidLength ? 'S' : ' '
-+				, ss->force_ssid_scan ? 'F' : ' '
-+			);
-+			#endif /* CONFIG_P2P */
-+		#endif /*DBG_SITESURVEY*/
-+#ifdef DBG_FIXED_CHAN
-+		if (pmlmeext->fixed_chan != 0xff)
-+			RTW_INFO(FUNC_ADPT_FMT" fixed_chan:%u\n", pmlmeext->fixed_chan);
-+#endif
-+
-+		site_survey(padapter, scan_ch, scan_type);
-+
-+#if defined(CONFIG_ATMEL_RC_PATCH)
-+		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+			scan_ms = 20;
-+		else
-+			scan_ms = 40;
-+#else
-+		#if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
-+		if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter))
-+			scan_ms = rtw_acs_get_adv_st(padapter);
-+		else
-+		#endif /*CONFIG_RTW_ACS*/
-+			scan_ms = ss->scan_ch_ms;
-+#endif
-+
-+#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
-+		if (ss->is_sw_antdiv_bl_scan)
-+			scan_ms = scan_ms / 2;
-+#endif
-+
-+#ifdef CONFIG_RTW_ACS
-+		if (IS_ACS_ENABLE(padapter)) {
-+			if (pparm->token)
-+				rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_IEEE_11K_HIGH);
-+			else
-+				rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_ACS);
-+		}
-+#endif
-+
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+		if (IS_NM_ENABLE(padapter))
-+			rtw_noise_measure(padapter, scan_ch, _FALSE, 0, scan_ms / 2);
-+#endif
-+		set_survey_timer(pmlmeext, scan_ms);
-+		break;
-+	}
-+
-+#ifdef CONFIG_SCAN_BACKOP
-+	case SCAN_BACKING_OP: {
-+		u8 back_ch, back_bw, back_ch_offset;
-+		u8 need_ch_setting_union = _TRUE;
-+
-+#ifdef CONFIG_MCC_MODE
-+		need_ch_setting_union = rtw_hal_mcc_change_scan_flag(padapter,
-+				&back_ch, &back_bw, &back_ch_offset);
-+#endif /* CONFIG_MCC_MODE */
-+
-+		if (need_ch_setting_union) {
-+			if (rtw_mi_get_ch_setting_union(padapter, &back_ch, &back_bw, &back_ch_offset) == 0) {
-+				rtw_warn_on(1);
-+				back_ch = pmlmeext->cur_channel;
-+				back_bw = pmlmeext->cur_bwmode;
-+				back_ch_offset = pmlmeext->cur_ch_offset;
-+			}
-+		}
-+
-+		#ifdef DBG_SITESURVEY
-+			RTW_INFO(FUNC_ADPT_FMT" %s ch:%u, bw:%u, offset:%u at %dms\n"
-+				 , FUNC_ADPT_ARG(padapter)
-+				 , mlmeext_scan_state_str(pmlmeext)
-+				 , back_ch, back_bw, back_ch_offset
-+				, rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time)
-+				);
-+		#endif /*DBG_SITESURVEY*/
-+		set_channel_bwmode(padapter, back_ch, back_ch_offset, back_bw);
-+
-+		sitesurvey_set_msr(padapter, _FALSE);
-+
-+		val8 = 0; /* survey done */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+
-+		if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) {
-+			sitesurvey_set_igi(padapter);
-+			rtw_hal_macid_wakeup_all_used(padapter);
-+			rtw_ps_annc(padapter, 0);
-+		}
-+
-+		mlmeext_set_scan_state(pmlmeext, SCAN_BACK_OP);
-+		ss->backop_time = rtw_get_current_time();
-+
-+		if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_TX_RESUME))
-+			rtw_mi_os_xmit_schedule(padapter);
-+
-+
-+		goto operation_by_state;
-+	}
-+
-+	case SCAN_BACK_OP:
-+		if (rtw_get_passing_time_ms(ss->backop_time) >= ss->backop_ms
-+		    || pmlmeext->scan_abort
-+		   ) {
-+			mlmeext_set_scan_state(pmlmeext, SCAN_LEAVING_OP);
-+			goto operation_by_state;
-+		}
-+		set_survey_timer(pmlmeext, 50);
-+		break;
-+
-+	case SCAN_LEAVING_OP:
-+		/*
-+		 * prepare to leave operating channel
-+		 */
-+
-+		/* clear HW TX queue before scan */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
-+
-+		rtw_hal_macid_sleep_all_used(padapter);
-+		if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)
-+			&& rtw_ps_annc(padapter, 1)
-+		) {
-+			mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT);
-+			mlmeext_set_scan_next_state(pmlmeext, SCAN_LEAVE_OP);
-+			set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */
-+		} else {
-+			mlmeext_set_scan_state(pmlmeext, SCAN_LEAVE_OP);
-+			goto operation_by_state;
-+		}
-+
-+		break;
-+
-+	case SCAN_LEAVE_OP:
-+		/*
-+		* HW register and DM setting for enter scan
-+		*/
-+
-+		if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC))
-+			sitesurvey_set_igi(padapter);
-+
-+		sitesurvey_set_msr(padapter, _TRUE);
-+
-+		val8 = 1; /* under site survey */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+
-+		mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS);
-+		goto operation_by_state;
-+
-+#endif /* CONFIG_SCAN_BACKOP */
-+
-+#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
-+	case SCAN_SW_ANTDIV_BL:
-+		/*
-+		* 20100721
-+		* For SW antenna diversity before link, it needs to switch to another antenna and scan again.
-+		* It compares the scan result and select better one to do connection.
-+		*/
-+		ss->bss_cnt = 0;
-+		ss->channel_idx = 0;
-+		ss->is_sw_antdiv_bl_scan = 1;
-+
-+		mlmeext_set_scan_next_state(pmlmeext, SCAN_PROCESS);
-+		set_survey_timer(pmlmeext, ss->scan_ch_ms);
-+		break;
-+#endif
-+
-+#ifdef CONFIG_P2P
-+	case SCAN_TO_P2P_LISTEN:
-+		/*
-+		* Set the P2P State to the listen state of find phase
-+		* and set the current channel to the listen channel
-+		*/
-+		set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+		rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_LISTEN);
-+
-+		/* turn on phy-dynamic functions */
-+		rtw_phydm_ability_restore(padapter);
-+
-+		sitesurvey_set_igi(padapter);
-+
-+		mlmeext_set_scan_state(pmlmeext, SCAN_P2P_LISTEN);
-+		_set_timer(&pwdinfo->find_phase_timer, (u32)((u32)pwdinfo->listen_dwell * 100));
-+		break;
-+
-+	case SCAN_P2P_LISTEN:
-+		mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS);
-+		ss->channel_idx = 0;
-+		goto operation_by_state;
-+#endif /* CONFIG_P2P */
-+
-+	case SCAN_COMPLETE:
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+		rtw_hal_set_hw_mac_addr(padapter, adapter_mac_addr(padapter));
-+#endif
-+#ifdef CONFIG_P2P
-+		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN)
-+		    || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)
-+		   ) {
-+#ifdef CONFIG_CONCURRENT_MODE
-+			if (pwdinfo->driver_interface == DRIVER_WEXT) {
-+				if (rtw_mi_check_status(padapter, MI_LINKED))
-+					_set_timer(&prochinfo->ap_roch_ch_switch_timer, 500);
-+			}
-+#endif
-+
-+			rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
-+		}
-+		rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
-+#endif /* CONFIG_P2P */
-+
-+		/* switch channel */
-+		survey_done_set_ch_bw(padapter);
-+
-+		sitesurvey_set_msr(padapter, _FALSE);
-+
-+		val8 = 0; /* survey done */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+
-+		/* turn on phy-dynamic functions */
-+		rtw_phydm_ability_restore(padapter);
-+
-+		sitesurvey_set_igi(padapter);
-+
-+#ifdef CONFIG_MCC_MODE
-+		/* start MCC fail, then tx null data */
-+		if (!rtw_hal_set_mcc_setting_scan_complete(padapter))
-+#endif
-+		{
-+			rtw_hal_macid_wakeup_all_used(padapter);
-+			rtw_ps_annc(padapter, 0);
-+		}
-+
-+		/* apply rx ampdu setting */
-+		rtw_rx_ampdu_apply(padapter);
-+
-+		mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE);
-+
-+		report_surveydone_event(padapter, ss->acs);
-+#ifdef CONFIG_RTW_ACS
-+		if (IS_ACS_ENABLE(padapter))
-+			rtw_acs_select_best_chan(padapter);
-+#endif
-+
-+#if defined(CONFIG_BACKGROUND_NOISE_MONITOR) && defined(DBG_NOISE_MONITOR)
-+		if (IS_NM_ENABLE(padapter))
-+			rtw_noise_info_dump(RTW_DBGDUMP, padapter);
-+#endif
-+		issue_action_BSSCoexistPacket(padapter);
-+		issue_action_BSSCoexistPacket(padapter);
-+		issue_action_BSSCoexistPacket(padapter);
-+
-+#ifdef CONFIG_RTW_80211K
-+		if (ss->token)
-+			rm_post_event(padapter, ss->token, RM_EV_survey_done);
-+#endif /* CONFIG_RTW_80211K */
-+
-+		break;
-+	}
-+
-+	return H2C_SUCCESS;
-+}
-+
-+u8 setauth_hdl(_adapter *padapter, unsigned char *pbuf)
-+{
-+	struct setauth_parm		*pparm = (struct setauth_parm *)pbuf;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if (pparm->mode < 4)
-+		pmlmeinfo->auth_algo = pparm->mode;
-+
-+	return	H2C_SUCCESS;
-+}
-+
-+/*
-+SEC CAM Entry format (32 bytes)
-+DW0 - MAC_ADDR[15:0] | Valid[15] | MFB[14:8] | RSVD[7]  | GK[6] | MIC_KEY[5] | SEC_TYPE[4:2] | KID[1:0]
-+DW0 - MAC_ADDR[15:0] | Valid[15] |RSVD[14:9] | RPT_MODE[8] | SPP_MODE[7]  | GK[6] | MIC_KEY[5] | SEC_TYPE[4:2] | KID[1:0] (92E/8812A/8814A)
-+DW1 - MAC_ADDR[47:16]
-+DW2 - KEY[31:0]
-+DW3 - KEY[63:32]
-+DW4 - KEY[95:64]
-+DW5 - KEY[127:96]
-+DW6 - RSVD
-+DW7 - RSVD
-+*/
-+
-+/*Set WEP key or Group Key*/
-+u8 setkey_hdl(_adapter *padapter, u8 *pbuf)
-+{
-+	u16	ctrl = 0;
-+	s16 cam_id = 0;
-+	struct setkey_parm		*pparm = (struct setkey_parm *)pbuf;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	unsigned char null_addr[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
-+	u8 *addr;
-+	bool used = _FALSE;
-+
-+	/* main tx key for wep. */
-+	if (pparm->set_tx)
-+		pmlmeinfo->key_index = pparm->keyid;
-+
-+#ifndef SEC_DEFAULT_KEY_SEARCH
-+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE))
-+		cam_id = rtw_iface_bcmc_id_get(padapter);
-+	else
-+#endif
-+		cam_id = rtw_camid_alloc(padapter, NULL, pparm->keyid, 1,
-+			!!(pparm->algorithm & _SEC_TYPE_256_), &used);
-+
-+	if (cam_id < 0)
-+		goto enable_mc;
-+
-+#ifdef SEC_DEFAULT_KEY_SEARCH
-+	if (cam_id >= 0 && cam_id <= 3) {
-+		/* default key camid */
-+		addr = null_addr;
-+	} else
-+#endif
-+	{
-+		/* not default key camid */
-+		if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) {
-+			/* group TX, force sec cam entry_id */
-+			addr = adapter_mac_addr(padapter);
-+		} else {
-+			/* group RX, searched by A2 (TA) */
-+			addr = get_bssid(&padapter->mlmepriv);
-+		}
-+	}
-+
-+#ifdef CONFIG_LPS_PG
-+	if (adapter_to_pwrctl(padapter)->lps_level == LPS_PG)
-+		LPS_Leave(padapter, "SET_KEY");
-+#endif
-+
-+	/* cam entry searched is pairwise key */
-+	if (used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _FALSE) {
-+		s16 camid_clr;
-+
-+		RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" id:%u the same key id as pairwise key\n"
-+			, FUNC_ADPT_ARG(padapter), MAC_ARG(addr), pparm->keyid);
-+
-+		/* HW has problem to distinguish this group key with existing pairwise key, stop HW enc and dec for BMC */
-+		rtw_camctl_set_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL);
-+
-+		/* clear group key */
-+		while ((camid_clr = rtw_camid_search(padapter, addr, -1, 1)) >= 0) {
-+			RTW_PRINT("clear group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(addr), camid_clr);
-+			clear_cam_entry(padapter, camid_clr);
-+			rtw_camid_free(padapter, camid_clr);
-+		}
-+
-+		goto enable_mc;
-+	}
-+
-+	ctrl = BIT(15) | BIT(6) | ((pparm->algorithm & 0x07) << 2) | pparm->keyid;
-+
-+	RTW_PRINT("set group key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n"
-+		, cam_id, MAC_ARG(addr), pparm->keyid, security_type_str(pparm->algorithm));
-+
-+	if (pparm->algorithm & _SEC_TYPE_256_)  {
-+		RTW_INFO_DUMP("GTK : ", pparm->key, sizeof(pparm->key));
-+		ctrl |= BIT(9);
-+	}	
-+
-+	write_cam(padapter, cam_id, ctrl, addr, pparm->key);
-+
-+	/* if ((cam_id > 3) && (((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)))*/
-+#ifndef SEC_DEFAULT_KEY_SEARCH
-+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) {
-+		if (is_wep_enc(pparm->algorithm)) {
-+			padapter->securitypriv.dot11Def_camid[pparm->keyid] = cam_id;
-+			padapter->securitypriv.dot118021x_bmc_cam_id =
-+				padapter->securitypriv.dot11Def_camid[padapter->securitypriv.dot11PrivacyKeyIndex];
-+			RTW_PRINT("wep group key - force camid:%d\n", padapter->securitypriv.dot118021x_bmc_cam_id);
-+		} else {
-+			/*u8 org_cam_id = padapter->securitypriv.dot118021x_bmc_cam_id;*/
-+
-+			/*force GK's cam id*/
-+			padapter->securitypriv.dot118021x_bmc_cam_id = cam_id;
-+
-+			/* for GTK rekey
-+			if ((org_cam_id != INVALID_SEC_MAC_CAM_ID) &&
-+				(org_cam_id != cam_id)) {
-+				RTW_PRINT("clear group key for addr:"MAC_FMT", org_camid:%d new_camid:%d\n", MAC_ARG(addr), org_cam_id, cam_id);
-+				clear_cam_entry(padapter, org_cam_id);
-+				rtw_camid_free(padapter, org_cam_id);
-+			}*/
-+		}
-+	}
-+#else
-+	if (cam_id >= 0 && cam_id <= 3)
-+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_TRUE);
-+#endif
-+
-+	/* 8814au should set both broadcast and unicast CAM entry for WEP key in STA mode */
-+	if (is_wep_enc(pparm->algorithm) && check_mlmeinfo_state(pmlmeext, WIFI_FW_STATION_STATE) &&
-+	    _rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_BMC)) {
-+		struct set_stakey_parm	sta_pparm;
-+
-+		_rtw_memset(&sta_pparm, 0, sizeof(struct set_stakey_parm));
-+		sta_pparm.algorithm = pparm->algorithm;
-+		sta_pparm.keyid = pparm->keyid;
-+		_rtw_memcpy(sta_pparm.key, pparm->key, 16);
-+		_rtw_memcpy(sta_pparm.addr, get_bssid(&padapter->mlmepriv), ETH_ALEN);
-+		set_stakey_hdl(padapter, (u8 *)&sta_pparm);
-+	}
-+
-+enable_mc:
-+	/* allow multicast packets to driver */
-+	rtw_hal_set_hwreg(padapter, HW_VAR_ON_RCR_AM, null_addr);
-+
-+	return H2C_SUCCESS;
-+}
-+
-+void rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta)
-+{
-+	struct security_priv *psecuritypriv = &(adapter->securitypriv);
-+	struct set_stakey_parm	sta_pparm;
-+	sint keyid;
-+
-+	if (!is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm))
-+		return;
-+
-+	for (keyid = 0; keyid < 4; keyid++) {
-+		if ((psecuritypriv->key_mask & BIT(keyid)) && (keyid == psecuritypriv->dot11PrivacyKeyIndex)) {
-+			sta_pparm.algorithm = psecuritypriv->dot11PrivacyAlgrthm;
-+			sta_pparm.keyid = keyid;
-+			sta_pparm.gk = 0;
-+			_rtw_memcpy(sta_pparm.key, &(psecuritypriv->dot11DefKey[keyid].skey[0]), 16);
-+			_rtw_memcpy(sta_pparm.addr, psta->cmn.mac_addr, ETH_ALEN);
-+
-+			RTW_PRINT(FUNC_ADPT_FMT"set WEP - PK with "MAC_FMT" keyid:%u\n"
-+				, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr), keyid);
-+
-+			set_stakey_hdl(adapter, (u8 *)&sta_pparm);
-+		}
-+	}
-+}
-+
-+u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf)
-+{
-+	u16 ctrl = 0;
-+	s16 cam_id = 0;
-+	bool used;
-+	u8 ret = H2C_SUCCESS;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct set_stakey_parm	*pparm = (struct set_stakey_parm *)pbuf;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *psta;
-+
-+	if (pparm->algorithm == _NO_PRIVACY_)
-+		goto write_to_cam;
-+
-+	psta = rtw_get_stainfo(pstapriv, pparm->addr);
-+	if (!psta) {
-+		RTW_PRINT("%s sta:"MAC_FMT" not found\n", __func__, MAC_ARG(pparm->addr));
-+		ret = H2C_REJECTED;
-+		goto exit;
-+	}
-+
-+	pmlmeinfo->enc_algo = pparm->algorithm;
-+
-+	cam_id = rtw_camid_alloc(padapter, psta, pparm->keyid, pparm->gk,
-+		!!(pparm->algorithm & _SEC_TYPE_256_), &used);
-+	if (cam_id < 0)
-+		goto exit;
-+
-+#ifdef CONFIG_LPS_PG
-+	if (adapter_to_pwrctl(padapter)->lps_level == LPS_PG)
-+		LPS_Leave(padapter, "SET_KEY");
-+#endif
-+
-+	/* cam entry searched is group key when setting pariwise key */
-+	if (!pparm->gk && used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _TRUE) {
-+		s16 camid_clr;
-+
-+		RTW_PRINT(FUNC_ADPT_FMT" pairwise key with "MAC_FMT" id:%u the same key id as group key\n"
-+			, FUNC_ADPT_ARG(padapter), MAC_ARG(pparm->addr), pparm->keyid);
-+
-+		/* HW has problem to distinguish this pairwise key with existing group key, stop HW enc and dec for BMC */
-+		rtw_camctl_set_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL);
-+
-+		/* clear group key */
-+		while ((camid_clr = rtw_camid_search(padapter, pparm->addr, -1, 1)) >= 0) {
-+			RTW_PRINT("clear group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(pparm->addr), camid_clr);
-+			clear_cam_entry(padapter, camid_clr);
-+			rtw_camid_free(padapter, camid_clr);
-+		}
-+	}
-+
-+write_to_cam:
-+	if (pparm->algorithm == _NO_PRIVACY_) {
-+		while ((cam_id = rtw_camid_search(padapter, pparm->addr, -1, -1)) >= 0) {
-+			RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(pparm->addr), cam_id);
-+			clear_cam_entry(padapter, cam_id);
-+			rtw_camid_free(padapter, cam_id);
-+		}
-+	} else {
-+		RTW_PRINT("set %s key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n"
-+			, pparm->gk ? "group" : "pairwise"
-+			, cam_id, MAC_ARG(pparm->addr), pparm->keyid, security_type_str(pparm->algorithm));
-+		ctrl = BIT(15) | ((pparm->algorithm & 0x07) << 2) | pparm->keyid;
-+		if (pparm->gk)
-+			ctrl |= BIT(6);
-+		if (pparm->algorithm & _SEC_TYPE_256_) {
-+			RTW_INFO_DUMP("PTK : ", pparm->key, sizeof(pparm->key));
-+			ctrl |= BIT(9);
-+		}
-+
-+		write_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key);
-+	}
-+	ret = H2C_SUCCESS_RSP;
-+
-+exit:
-+	return ret;
-+}
-+
-+u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf)
-+{
-+	struct addBaReq_parm	*pparm = (struct addBaReq_parm *)pbuf;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, pparm->addr);
-+
-+	if (!psta)
-+		return	H2C_SUCCESS;
-+
-+#ifdef CONFIG_80211N_HT
-+	if (((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && (pmlmeinfo->HT_enable)) ||
-+	    ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
-+		/* pmlmeinfo->ADDBA_retry_count = 0; */
-+		/* pmlmeinfo->candidate_tid_bitmap |= (0x1 << pparm->tid);		 */
-+		/* psta->htpriv.candidate_tid_bitmap |= BIT(pparm->tid); */
-+		issue_addba_req(padapter, pparm->addr, (u8)pparm->tid);
-+		_set_timer(&psta->addba_retry_timer, ADDBA_TO);
-+	}
-+#ifdef CONFIG_TDLS
-+	else if ((psta->tdls_sta_state & TDLS_LINKED_STATE) &&
-+		 (psta->htpriv.ht_option == _TRUE) &&
-+		 (psta->htpriv.ampdu_enable == _TRUE)) {
-+		issue_addba_req(padapter, pparm->addr, (u8)pparm->tid);
-+		_set_timer(&psta->addba_retry_timer, ADDBA_TO);
-+	}
-+#endif /* CONFIG */
-+	else
-+		psta->htpriv.candidate_tid_bitmap &= ~BIT(pparm->tid);
-+#endif /* CONFIG_80211N_HT */
-+	return	H2C_SUCCESS;
-+}
-+
-+
-+u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf)
-+{
-+	struct addBaRsp_parm *pparm = (struct addBaRsp_parm *)pbuf;
-+	struct recv_reorder_ctrl *preorder_ctrl;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *psta;
-+	u8 ret = _TRUE;
-+
-+	psta = rtw_get_stainfo(pstapriv, pparm->addr);
-+	if (!psta)
-+		goto exit;
-+
-+	preorder_ctrl = &psta->recvreorder_ctrl[pparm->tid];
-+	ret = issue_addba_rsp_wait_ack(padapter, pparm->addr, pparm->tid, pparm->status, pparm->size, 3, 50);
-+
-+#ifdef CONFIG_UPDATE_INDICATE_SEQ_WHILE_PROCESS_ADDBA_REQ
-+	/* status = 0 means accept this addba req, so update indicate seq = start_seq under this compile flag */
-+	if (pparm->status == 0) {
-+		preorder_ctrl->indicate_seq = pparm->start_seq;
-+		#ifdef DBG_RX_SEQ
-+		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_UPDATE indicate_seq:%d, start_seq:%d\n"
-+			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pparm->start_seq);
-+		#endif
-+	}
-+#else
-+	rtw_set_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack);
-+	#ifdef DBG_RX_SEQ
-+	RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d, start_seq:%d preorder_ctrl->rec_abba_rsp_ack =%lu \n"
-+		, FUNC_ADPT_ARG(padapter)
-+		, preorder_ctrl->tid
-+		, preorder_ctrl->indicate_seq
-+		, pparm->start_seq
-+		,preorder_ctrl->rec_abba_rsp_ack
-+		);
-+	#endif
-+#endif
-+
-+	/*
-+	  * status = 0 means accept this addba req
-+	  * status = 37 means reject this addba req
-+	  */
-+	if (pparm->status == 0) {
-+		preorder_ctrl->enable = _TRUE;
-+		preorder_ctrl->ampdu_size = pparm->size;
-+	} else if (pparm->status == 37)
-+		preorder_ctrl->enable = _FALSE;
-+
-+exit:
-+	return H2C_SUCCESS;
-+}
-+
-+u8 chk_bmc_sleepq_cmd(_adapter *padapter)
-+{
-+	struct cmd_obj *ph2c;
-+	struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
-+	u8 res = _SUCCESS;
-+
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	init_h2fwcmd_w_parm_no_parm_rsp(ph2c, CMD_CHK_BMCSLEEPQ);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+u8 set_tx_beacon_cmd(_adapter *padapter, u8 flags)
-+{
-+	struct cmd_obj	*ph2c;
-+	struct Tx_Beacon_param	*ptxBeacon_parm;
-+	struct cmd_priv	*pcmdpriv = &(padapter->cmdpriv);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct submit_ctx sctx;
-+	u8	res = _SUCCESS;
-+	int len_diff = 0;
-+
-+	/*prepare cmd parameter*/
-+	ptxBeacon_parm = (struct Tx_Beacon_param *)rtw_zmalloc(sizeof(struct Tx_Beacon_param));
-+	if (ptxBeacon_parm == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	_rtw_memcpy(&(ptxBeacon_parm->network), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX));
-+
-+	len_diff = update_hidden_ssid(
-+			   ptxBeacon_parm->network.IEs + _BEACON_IE_OFFSET_
-+		   , ptxBeacon_parm->network.IELength - _BEACON_IE_OFFSET_
-+			   , pmlmeinfo->hidden_ssid_mode
-+		   );
-+	ptxBeacon_parm->network.IELength += len_diff;
-+
-+
-+	/* need enqueue, prepare cmd_obj and enqueue */
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		rtw_mfree((u8 *)ptxBeacon_parm, sizeof(*ptxBeacon_parm));
-+		goto exit;
-+	}
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, ptxBeacon_parm, CMD_TX_BEACON);
-+
-+	if (flags & RTW_CMDF_WAIT_ACK) {
-+		ph2c->sctx = &sctx;
-+		rtw_sctx_init(&sctx, 10 * 1000);
-+	}
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+	if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+		rtw_sctx_wait(&sctx, __func__);
-+		_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+		if (sctx.status == RTW_SCTX_SUBMITTED)
-+			ph2c->sctx = NULL;
-+		_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+	}
-+	
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+
-+u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf)
-+{
-+	struct rtw_evt_header *evt_hdr;
-+	u8 *peventbuf;
-+	void (*event_callback)(_adapter *dev, u8 *pbuf);
-+	struct evt_priv *pevt_priv = &(padapter->evtpriv);
-+
-+	if (pbuf == NULL)
-+		goto _abort_event_;
-+
-+	evt_hdr = (struct rtw_evt_header *)pbuf;
-+	peventbuf = pbuf + sizeof(struct rtw_evt_header);
-+
-+#ifdef CHECK_EVENT_SEQ
-+	/* checking event sequence...		 */
-+	if (evt_hdr->seq != (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f)) {
-+		pevt_priv->event_seq = (evt_hdr->seq + 1) & 0x7f;
-+		goto _abort_event_;
-+	}
-+#endif
-+
-+	/* checking if event code is valid */
-+	if (evt_hdr->id >= EVT_ID_MAX) {
-+		goto _abort_event_;
-+	}
-+
-+	/* checking if event size match the event parm size	 */
-+	if ((wlanevents[evt_hdr->id].parmsize != 0) &&
-+	    (wlanevents[evt_hdr->id].parmsize != evt_hdr->len)) {
-+
-+		goto _abort_event_;
-+
-+	}
-+
-+	ATOMIC_INC(&pevt_priv->event_seq);
-+
-+	if (peventbuf) {
-+		event_callback = wlanevents[evt_hdr->id].event_callback;
-+		event_callback(padapter, (u8 *)peventbuf);
-+		pevt_priv->evt_done_cnt++;
-+	}
-+
-+_abort_event_:
-+	return H2C_SUCCESS;
-+
-+}
-+
-+u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf)
-+{
-+#ifdef CONFIG_AP_MODE
-+	_irqL irqL;
-+	struct sta_info *psta_bmc;
-+	_list	*xmitframe_plist, *xmitframe_phead;
-+	struct xmit_frame *pxmitframe = NULL;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	struct sta_priv  *pstapriv = &padapter->stapriv;
-+
-+	/* for BC/MC Frames */
-+	psta_bmc = rtw_get_bcmc_stainfo(padapter);
-+	if (!psta_bmc)
-+		return H2C_SUCCESS;
-+
-+	if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) {
-+#ifndef CONFIG_PCI_HCI
-+		rtw_msleep_os(10);/* 10ms, ATIM(HIQ) Windows */
-+#endif
-+		/* _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); */
-+		_enter_critical_bh(&pxmitpriv->lock, &irqL);
-+
-+		xmitframe_phead = get_list_head(&psta_bmc->sleep_q);
-+		xmitframe_plist = get_next(xmitframe_phead);
-+
-+		while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
-+			pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
-+
-+			xmitframe_plist = get_next(xmitframe_plist);
-+
-+			rtw_list_delete(&pxmitframe->list);
-+
-+			psta_bmc->sleepq_len--;
-+			if (psta_bmc->sleepq_len > 0)
-+				pxmitframe->attrib.mdata = 1;
-+			else
-+				pxmitframe->attrib.mdata = 0;
-+
-+			pxmitframe->attrib.triggered = 1;
-+
-+			if (xmitframe_hiq_filter(pxmitframe) == _TRUE)
-+				pxmitframe->attrib.qsel = QSLT_HIGH;/* HIQ */
-+
-+#if 0
-+			_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
-+			if (rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
-+				rtw_os_xmit_complete(padapter, pxmitframe);
-+			_enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
-+#endif
-+			rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
-+		}
-+
-+		/* _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); */
-+		_exit_critical_bh(&pxmitpriv->lock, &irqL);
-+
-+		if (rtw_get_intf_type(padapter) != RTW_PCIE) {
-+			/* check hi queue and bmc_sleepq */
-+			rtw_chk_hi_queue_cmd(padapter);
-+		}
-+	}
-+#endif
-+
-+	return H2C_SUCCESS;
-+}
-+
-+u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf)
-+{
-+#ifdef CONFIG_AP_MODE
-+	/*RTW_INFO(FUNC_ADPT_FMT, FUNC_ADPT_ARG(padapter));*/
-+#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+
-+	tx_beacon_handlder(padapter->dvobj);
-+
-+#else
-+
-+	if (send_beacon(padapter) == _FAIL) {
-+		RTW_INFO("issue_beacon, fail!\n");
-+		return H2C_PARAMETERS_ERROR;
-+	}
-+
-+	/* tx bc/mc frames after update TIM */
-+	chk_bmc_sleepq_hdl(padapter, NULL);
-+#endif
-+#endif /* CONFIG_AP_MODE */
-+	return H2C_SUCCESS;
-+}
-+
-+/*
-+* according to channel
-+* add/remove WLAN_BSSID_EX.IEs's ERP ie
-+* set WLAN_BSSID_EX.SupportedRates
-+* update WLAN_BSSID_EX.IEs's Supported Rate and Extended Supported Rate ie
-+*/
-+#ifdef CONFIG_AP_MODE
-+void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch)
-+{
-+	u8	network_type, rate_len, total_rate_len, remainder_rate_len;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	u8	erpinfo = 0x4;
-+
-+	if (ch >= 36) {
-+		network_type = WIRELESS_11A;
-+		total_rate_len = IEEE80211_NUM_OFDM_RATESLEN;
-+		rtw_remove_bcn_ie(padapter, pnetwork, _ERPINFO_IE_);
-+		#ifdef CONFIG_80211AC_VHT
-+		/* if channel in 5G band, then add vht ie . */
-+		if ((pmlmepriv->htpriv.ht_option == _TRUE)
-+			&& REGSTY_IS_11AC_ENABLE(&padapter->registrypriv)
-+			&& is_supported_vht(padapter->registrypriv.wireless_mode)
-+			&& (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
-+		) {
-+			if (REGSTY_IS_11AC_AUTO(&padapter->registrypriv)
-+				|| pmlmepriv->ori_vht_en)
-+				rtw_vht_ies_attach(padapter, pnetwork);
-+		}
-+		#endif
-+	} else {
-+		network_type = 0;
-+		total_rate_len = 0;
-+		if (padapter->registrypriv.wireless_mode & WIRELESS_11B) {
-+			network_type |= WIRELESS_11B;
-+			total_rate_len += IEEE80211_CCK_RATE_LEN;
-+		}
-+		if (padapter->registrypriv.wireless_mode & WIRELESS_11G) {
-+			network_type |= WIRELESS_11G;
-+			total_rate_len += IEEE80211_NUM_OFDM_RATESLEN;
-+		}
-+		rtw_add_bcn_ie(padapter, pnetwork, _ERPINFO_IE_, &erpinfo, 1);
-+		#ifdef CONFIG_80211AC_VHT
-+		rtw_vht_ies_detach(padapter, pnetwork);
-+		#endif
-+	}
-+
-+	rtw_set_supported_rate(pnetwork->SupportedRates, network_type);
-+
-+	UpdateBrateTbl(padapter, pnetwork->SupportedRates);
-+
-+	if (total_rate_len > 8) {
-+		rate_len = 8;
-+		remainder_rate_len = total_rate_len - 8;
-+	} else {
-+		rate_len = total_rate_len;
-+		remainder_rate_len = 0;
-+	}
-+
-+	rtw_add_bcn_ie(padapter, pnetwork, _SUPPORTEDRATES_IE_, pnetwork->SupportedRates, rate_len);
-+
-+	if (remainder_rate_len)
-+		rtw_add_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_, (pnetwork->SupportedRates + 8), remainder_rate_len);
-+	else
-+		rtw_remove_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_);
-+
-+	pnetwork->Length = get_WLAN_BSSID_EX_sz(pnetwork);
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+void rtw_join_done_chk_ch(_adapter *adapter, int join_res)
-+{
-+#define DUMP_ADAPTERS_STATUS 0
-+
-+	struct dvobj_priv *dvobj;
-+	_adapter *iface;
-+	struct mlme_priv *mlme;
-+	struct mlme_ext_priv *mlmeext;
-+	u8 u_ch, u_offset, u_bw;
-+	int i, ret;
-+
-+	dvobj = adapter_to_dvobj(adapter);
-+
-+	if (DUMP_ADAPTERS_STATUS) {
-+		RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter));
-+		dump_adapters_status(RTW_DBGDUMP , dvobj);
-+	}
-+
-+	ret = rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset);
-+	if (join_res >= 0 && ret <= 0) {
-+		join_res = -1;
-+		dump_adapters_status(RTW_DBGDUMP , dvobj);
-+		rtw_warn_on(1);
-+	}
-+
-+	if (join_res >= 0) {
-+#ifdef CONFIG_MCC_MODE
-+		/* MCC setting success, don't go to ch union process */
-+		if (rtw_hal_set_mcc_setting_join_done_chk_ch(adapter))
-+			return;
-+#endif /* CONFIG_MCC_MODE */
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			mlme = &iface->mlmepriv;
-+			mlmeext = &iface->mlmeextpriv;
-+
-+			if (!iface || iface == adapter)
-+				continue;
-+
-+#ifdef CONFIG_AP_MODE
-+			if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
-+				&& check_fwstate(mlme, WIFI_ASOC_STATE)
-+			) {
-+				u8 ori_ch, ori_bw, ori_offset;
-+				bool is_grouped = rtw_is_chbw_grouped(u_ch, u_bw, u_offset
-+					, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
-+
-+				if (is_grouped == _FALSE) {
-+					/* handle AP which need to switch ch setting */
-+
-+					ori_ch = mlmeext->cur_channel;
-+					ori_bw = mlmeext->cur_bwmode;
-+					ori_offset = mlmeext->cur_ch_offset;
-+
-+					/* restore original bw, adjust bw by registry setting on target ch */
-+					mlmeext->cur_bwmode = mlme->ori_bw;
-+					mlmeext->cur_channel = u_ch;
-+					rtw_adjust_chbw(iface, mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset);
-+					#ifdef CONFIG_RTW_MESH
-+					if (MLME_IS_MESH(iface))
-+						rtw_mesh_adjust_chbw(mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset);
-+					#endif
-+
-+					rtw_chset_sync_chbw(adapter_to_chset(adapter)
-+						, &mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset
-+						, &u_ch, &u_bw, &u_offset, 1, 0);
-+
-+					RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u\n", FUNC_ADPT_ARG(iface)
-+						, ori_ch, ori_bw, ori_offset
-+						, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
-+
-+					rtw_ap_update_bss_chbw(iface, &(mlmeext->mlmext_info.network)
-+						, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
-+
-+					_rtw_memcpy(&(mlme->cur_network.network), &(mlmeext->mlmext_info.network), sizeof(WLAN_BSSID_EX));
-+
-+					rtw_start_bss_hdl_after_chbw_decided(iface);
-+
-+					{
-+						#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
-+						u8 ht_option = 0;
-+
-+						#ifdef CONFIG_80211N_HT
-+						ht_option = mlme->htpriv.ht_option;
-+						#endif
-+
-+						rtw_cfg80211_ch_switch_notify(iface
-+							, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset
-+							, ht_option, 0);
-+						#endif
-+					}
-+				}
-+
-+				clr_fwstate(mlme, WIFI_OP_CH_SWITCHING);
-+				update_beacon(iface, 0xFF, NULL, _TRUE, 0);
-+			}
-+#endif /* CONFIG_AP_MODE */
-+		}
-+
-+#ifdef CONFIG_DFS_MASTER
-+		rtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTED, 0);
-+#endif
-+	} else {
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			mlme = &iface->mlmepriv;
-+			mlmeext = &iface->mlmeextpriv;
-+
-+			if (!iface || iface == adapter)
-+				continue;
-+#ifdef CONFIG_AP_MODE
-+			if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
-+				&& check_fwstate(mlme, WIFI_ASOC_STATE)
-+			) {
-+				clr_fwstate(mlme, WIFI_OP_CH_SWITCHING);
-+				update_beacon(iface, 0xFF, NULL, _TRUE, 0);
-+			}
-+#endif
-+		}
-+#ifdef CONFIG_DFS_MASTER
-+		rtw_dfs_rd_en_decision(adapter, MLME_STA_DISCONNECTED, 0);
-+#endif
-+	}
-+
-+	if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) {
-+		RTW_INFO(FUNC_ADPT_FMT" union:%u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);
-+		set_channel_bwmode(adapter, u_ch, u_offset, u_bw);
-+	}
-+
-+	rtw_mi_update_union_chan_inf(adapter, u_ch, u_offset, u_bw);
-+
-+	if (join_res >= 0)
-+		rtw_rfctl_update_op_mode(adapter_to_rfctl(adapter), BIT(adapter->iface_id), 1);
-+
-+	if (DUMP_ADAPTERS_STATUS) {
-+		RTW_INFO(FUNC_ADPT_FMT" exit\n", FUNC_ADPT_ARG(adapter));
-+		dump_adapters_status(RTW_DBGDUMP , dvobj);
-+	}
-+}
-+
-+int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)
-+{
-+#ifdef CONFIG_CONCURRENT_MODE
-+	bool chbw_allow = _TRUE;
-+#endif
-+	bool connect_allow = _TRUE;
-+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
-+	u8 cur_ch, cur_bw, cur_ch_offset;
-+	u8 u_ch, u_offset, u_bw;
-+
-+	u_ch = cur_ch = pmlmeext->cur_channel;
-+	u_bw = cur_bw = pmlmeext->cur_bwmode;
-+	u_offset = cur_ch_offset = pmlmeext->cur_ch_offset;
-+
-+	if (!ch || !bw || !offset) {
-+		connect_allow = _FALSE;
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (cur_ch == 0) {
-+		connect_allow = _FALSE;
-+		RTW_ERR(FUNC_ADPT_FMT" cur_ch:%u\n"
-+			, FUNC_ADPT_ARG(adapter), cur_ch);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+	RTW_INFO(FUNC_ADPT_FMT" req: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	{
-+		struct dvobj_priv *dvobj;
-+		_adapter *iface;
-+		struct mlme_priv *mlme;
-+		struct mlme_ext_priv *mlmeext;
-+		struct mi_state mstate;
-+		int i;
-+
-+		dvobj = adapter_to_dvobj(adapter);
-+
-+		rtw_mi_status_no_self(adapter, &mstate);
-+		RTW_INFO(FUNC_ADPT_FMT" others ld_sta_num:%u, ap_num:%u, mesh_num:%u\n"
-+			, FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate)
-+			, MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate));
-+
-+		if (!MSTATE_STA_LD_NUM(&mstate) && !MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) {
-+			/* consider linking STA? */
-+			goto connect_allow_hdl;
-+		}
-+
-+		if (rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset) <= 0) {
-+			dump_adapters_status(RTW_DBGDUMP , dvobj);
-+			rtw_warn_on(1);
-+		}
-+		RTW_INFO(FUNC_ADPT_FMT" others union:%u,%u,%u\n"
-+			 , FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);
-+
-+		/* chbw_allow? */
-+		chbw_allow = rtw_is_chbw_grouped(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset
-+						 , u_ch, u_bw, u_offset);
-+
-+		RTW_INFO(FUNC_ADPT_FMT" chbw_allow:%d\n"
-+			 , FUNC_ADPT_ARG(adapter), chbw_allow);
-+
-+#ifdef CONFIG_MCC_MODE
-+		/* check setting success, don't go to ch union process */
-+		if (rtw_hal_set_mcc_setting_chk_start_clnt_join(adapter, &u_ch, &u_bw, &u_offset, chbw_allow))
-+			goto exit;
-+#endif
-+
-+		if (chbw_allow == _TRUE) {
-+			rtw_sync_chbw(&cur_ch, &cur_bw, &cur_ch_offset, &u_ch, &u_bw, &u_offset);
-+			rtw_warn_on(cur_ch != pmlmeext->cur_channel);
-+			rtw_warn_on(cur_bw != pmlmeext->cur_bwmode);
-+			rtw_warn_on(cur_ch_offset != pmlmeext->cur_ch_offset);
-+			goto connect_allow_hdl;
-+		}
-+
-+#ifdef CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT
-+		/* chbw_allow is _FALSE, connect allow? */
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			mlme = &iface->mlmepriv;
-+			mlmeext = &iface->mlmeextpriv;
-+
-+			if (check_fwstate(mlme, WIFI_STATION_STATE)
-+			    && check_fwstate(mlme, WIFI_ASOC_STATE)
-+#if defined(CONFIG_P2P)
-+			    && rtw_p2p_chk_state(&(iface->wdinfo), P2P_STATE_NONE)
-+#endif
-+			   ) {
-+				connect_allow = _FALSE;
-+				break;
-+			}
-+		}
-+#endif /* CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT */
-+
-+		if (MSTATE_STA_LD_NUM(&mstate) + MSTATE_AP_LD_NUM(&mstate) + MSTATE_MESH_LD_NUM(&mstate) >= 4)
-+			connect_allow = _FALSE;
-+
-+		RTW_INFO(FUNC_ADPT_FMT" connect_allow:%d\n"
-+			 , FUNC_ADPT_ARG(adapter), connect_allow);
-+
-+		if (connect_allow == _FALSE)
-+			goto exit;
-+
-+connect_allow_hdl:
-+		/* connect_allow == _TRUE */
-+
-+		if (chbw_allow == _FALSE) {
-+			u_ch = cur_ch;
-+			u_bw = cur_bw;
-+			u_offset = cur_ch_offset;
-+
-+			for (i = 0; i < dvobj->iface_nums; i++) {
-+				iface = dvobj->padapters[i];
-+				mlme = &iface->mlmepriv;
-+				mlmeext = &iface->mlmeextpriv;
-+
-+				if (!iface || iface == adapter)
-+					continue;
-+
-+				#ifdef CONFIG_AP_MODE
-+				if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
-+					&& check_fwstate(mlme, WIFI_ASOC_STATE)
-+				) {
-+					#ifdef CONFIG_SPCT_CH_SWITCH
-+					if (1)
-+						rtw_ap_inform_ch_switch(iface, pmlmeext->cur_channel , pmlmeext->cur_ch_offset);
-+					else
-+					#endif
-+						rtw_sta_flush(iface, _FALSE);
-+
-+					rtw_hal_set_hwreg(iface, HW_VAR_CHECK_TXBUF, 0);
-+					set_fwstate(mlme, WIFI_OP_CH_SWITCHING);
-+				} else
-+				#endif /* CONFIG_AP_MODE */
-+				if (check_fwstate(mlme, WIFI_STATION_STATE)
-+					&& check_fwstate(mlme, WIFI_ASOC_STATE)
-+				) {
-+					rtw_disassoc_cmd(iface, 500, RTW_CMDF_DIRECTLY);
-+					rtw_indicate_disconnect(iface, 0, _FALSE);
-+					rtw_free_assoc_resources(iface, _TRUE);
-+				}
-+			}
-+		}
-+
-+		#ifdef CONFIG_DFS_MASTER
-+		rtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTING, 0);
-+		#endif
-+	}
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+exit:
-+
-+	if (connect_allow == _TRUE) {
-+		RTW_INFO(FUNC_ADPT_FMT" union: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);
-+		rtw_mi_update_union_chan_inf(adapter, u_ch, u_offset, u_bw);
-+		*ch = u_ch;
-+		*bw = u_bw;
-+		*offset = u_offset;
-+
-+#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
-+		{
-+			u8 ht_option = 0;
-+
-+#ifdef CONFIG_80211N_HT
-+			ht_option = adapter->mlmepriv.htpriv.ht_option;
-+#endif /* CONFIG_80211N_HT */
-+
-+			/*
-+				when supplicant send the mlme frame,
-+				the bss freq is updated by channel switch event.
-+			*/
-+			rtw_cfg80211_ch_switch_notify(adapter,
-+				cur_ch, cur_bw, cur_ch_offset, ht_option, 1);
-+		}
-+#endif
-+	}
-+
-+	return connect_allow == _TRUE ? _SUCCESS : _FAIL;
-+}
-+
-+void rtw_set_external_auth_status(_adapter *padapter,
-+	const void *data, int len)
-+{
-+#ifdef CONFIG_IOCTL_CFG80211
-+	struct net_device *dev = padapter->pnetdev;
-+	struct wiphy *wiphy = adapter_to_wiphy(padapter);
-+	struct rtw_external_auth_params params;
-+
-+	/* convert data to external_auth_params */
-+	params.action = RTW_GET_BE32((u8 *)data);
-+	_rtw_memcpy(&params.bssid, (u8 *)data + 4, ETH_ALEN);
-+	_rtw_memcpy(&params.ssid.ssid, (u8 *)data + 10, WLAN_SSID_MAXLEN);
-+	params.ssid.ssid_len = RTW_GET_BE64((u8 *)data + 42);
-+	params.key_mgmt_suite = RTW_GET_BE32((u8 *)data + 58);
-+	params.status = RTW_GET_BE16((u8 *)data + 62);
-+	_rtw_memcpy(&params.pmkid, (u8 *)data + 64, PMKID_LEN);
-+
-+	rtw_cfg80211_external_auth_status(wiphy, dev, &params);
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+}
-+
-+u8 rtw_iqk_hdl(_adapter *padapter, unsigned char *pbuf)
-+{
-+	rtw_hal_phydm_cal_trigger(padapter);
-+	return	H2C_SUCCESS;
-+}
-+
-+u8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf)
-+{
-+	struct set_ch_parm *set_ch_parm;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	u8 ifbmp_s = rtw_mi_get_ld_sta_ifbmp(padapter);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	u8 u_ch, u_bw, u_offset;
-+
-+	if (!pbuf)
-+		return H2C_PARAMETERS_ERROR;
-+
-+	set_ch_parm = (struct set_ch_parm *)pbuf;
-+
-+	RTW_INFO(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n",
-+		 FUNC_NDEV_ARG(padapter->pnetdev),
-+		 set_ch_parm->ch, set_ch_parm->bw, set_ch_parm->ch_offset);
-+
-+	/*  update ch, bw, offset for all asoc STA ifaces */
-+	if (ifbmp_s) {
-+		_adapter *iface;
-+		int i;
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			if (!iface || !(ifbmp_s & BIT(iface->iface_id)))
-+				continue;
-+			
-+			/* update STA mode ch/bw/offset */
-+			iface->mlmeextpriv.cur_channel = set_ch_parm->ch;
-+			iface->mlmeextpriv.cur_bwmode = set_ch_parm->bw;
-+			iface->mlmeextpriv.cur_ch_offset = set_ch_parm->ch_offset;
-+			/* updaet STA mode DSConfig , ap mode will update in rtw_change_bss_chbw_cmd */
-+			iface->mlmepriv.cur_network.network.Configuration.DSConfig = set_ch_parm->ch;
-+		}
-+	}
-+	
-+	LeaveAllPowerSaveModeDirect(padapter);
-+	
-+	set_channel_bwmode(padapter, set_ch_parm->ch, set_ch_parm->ch_offset, set_ch_parm->bw);
-+
-+	rtw_mi_get_ch_setting_union(padapter, &u_ch, &u_bw, &u_offset);
-+	rtw_mi_update_union_chan_inf(padapter, u_ch, u_offset, u_bw);
-+	rtw_rfctl_update_op_mode(dvobj_to_rfctl(dvobj), 0, 0);
-+	
-+	return	H2C_SUCCESS;
-+}
-+
-+u8 rtw_set_chplan_hdl(_adapter *padapter, unsigned char *pbuf)
-+{
-+	struct SetChannelPlan_param *param;
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+
-+	if (!pbuf)
-+		return H2C_PARAMETERS_ERROR;
-+
-+	param = (struct SetChannelPlan_param *)pbuf;
-+
-+	if (param->regd_src == REGD_SRC_RTK_PRIV
-+		&& !rtw_is_channel_plan_valid(param->channel_plan))
-+		return H2C_PARAMETERS_ERROR;
-+
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+	if (rfctl->regd_src == REGD_SRC_OS)
-+		rtw_mfree((void *)rfctl->country_ent, sizeof(struct country_chplan));
-+#endif
-+
-+	rfctl->regd_src = param->regd_src;
-+	rfctl->country_ent = param->country_ent;
-+	rfctl->ChannelPlan = param->channel_plan;
-+
-+#if CONFIG_TXPWR_LIMIT
-+	rtw_txpwr_init_regd(rfctl);
-+#endif
-+
-+	rtw_rfctl_chplan_init(padapter);
-+
-+	rtw_hal_set_odm_var(padapter, HAL_ODM_REGULATION, NULL, _TRUE);
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	rtw_regd_apply_flags(adapter_to_wiphy(padapter));
-+#endif
-+
-+	rtw_nlrtw_reg_change_event(padapter);
-+
-+	if (GET_HAL_DATA(padapter)->txpwr_limit_loaded
-+		&& rtw_get_hw_init_completed(padapter))
-+		rtw_hal_update_txpwr_level(padapter);
-+
-+	return	H2C_SUCCESS;
-+}
-+
-+u8 rtw_get_chplan_hdl(_adapter *padapter, unsigned char *pbuf)
-+{
-+	struct get_channel_plan_param *param;
-+	struct get_chplan_resp *resp;
-+	struct rf_ctl_t *rfctl;
-+
-+	if (!pbuf)
-+		return H2C_PARAMETERS_ERROR;
-+
-+	rfctl = adapter_to_rfctl(padapter);
-+	param = (struct get_channel_plan_param *)pbuf;
-+
-+	resp = rtw_vmalloc(sizeof(struct get_chplan_resp) + sizeof(RT_CHANNEL_INFO) * rfctl->max_chan_nums);
-+	if (!resp)
-+		return H2C_CMD_FAIL;
-+
-+	resp->regd_src = rfctl->regd_src;
-+
-+	if (rfctl->country_ent) {
-+		_rtw_memcpy(&resp->country_ent, rfctl->country_ent, sizeof(struct country_chplan));
-+		resp->has_country = 1;
-+	} else
-+		resp->has_country = 0;
-+	
-+	resp->channel_plan = rfctl->ChannelPlan;
-+#if CONFIG_TXPWR_LIMIT
-+	resp->regd_name = rfctl->regd_name;
-+#endif
-+#ifdef CONFIG_DFS_MASTER
-+	resp->dfs_domain = rtw_rfctl_get_dfs_domain(rfctl);
-+#endif
-+	resp->chset_num = rfctl->max_chan_nums;
-+
-+	_rtw_memcpy(resp->chset, rfctl->channel_set, sizeof(RT_CHANNEL_INFO) * rfctl->max_chan_nums);
-+	*param->resp = resp;
-+
-+	return	H2C_SUCCESS;
-+}
-+
-+u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf)
-+{
-+	struct LedBlink_param *ledBlink_param;
-+
-+	if (!pbuf)
-+		return H2C_PARAMETERS_ERROR;
-+
-+	ledBlink_param = (struct LedBlink_param *)pbuf;
-+
-+#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD
-+	BlinkHandler((PLED_DATA)ledBlink_param->pLed);
-+#endif
-+
-+	return	H2C_SUCCESS;
-+}
-+
-+void csa_timer_hdl(void *FunctionContext)
-+{
-+	_adapter *padapter = (_adapter *)FunctionContext;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 i, update_beacon = _FALSE;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		_adapter *iface;
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+		if (check_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON)) {
-+			clr_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON);
-+			update_beacon = _TRUE;
-+		}
-+	}
-+	
-+	/* wait beacons more than 70 seconds */
-+	if(update_beacon == _TRUE) {
-+		RTW_INFO("wait beacons more than 70 seconds\n");
-+		return ;
-+	}
-+	
-+	if(rfctl->csa_ch == 0) {
-+		RTW_INFO("channel switch done\n");
-+		return ;
-+	}
-+	
-+	/* channel switch */
-+	if (rtw_set_csa_cmd(padapter) != _SUCCESS) {
-+			rfctl->csa_ch = 0;
-+			rfctl->csa_switch_cnt = 0;
-+			rfctl->csa_ch_offset = 0;
-+			rfctl->csa_ch_width = 0;
-+			rfctl->csa_ch_freq_seg0 = 0;
-+			rfctl->csa_ch_freq_seg1 = 0;
-+	}
-+}
-+
-+u8 set_csa_hdl(_adapter *adapter, unsigned char *pbuf)
-+{
-+#if CONFIG_DFS
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	if (rfctl->csa_ch)
-+		rtw_dfs_ch_switch_hdl(adapter_to_dvobj(adapter));
-+#endif
-+	return	H2C_SUCCESS;
-+}
-+
-+u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
-+{
-+#ifdef CONFIG_TDLS
-+	_irqL irqL;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+#ifdef CONFIG_TDLS_CH_SW
-+	struct tdls_ch_switch *pchsw_info = &ptdlsinfo->chsw_info;
-+#endif
-+	struct TDLSoption_param *TDLSoption;
-+	struct sta_info *ptdls_sta = NULL;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
-+	struct sta_info *ap_sta = rtw_get_stainfo(&padapter->stapriv, get_my_bssid(&(pmlmeinfo->network)));
-+	u8 survey_channel, i, min, option;
-+	struct tdls_txmgmt txmgmt;
-+	u32 setchtime, resp_sleep = 0, wait_time;
-+	u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
-+	u8 ret;
-+	u8 doiqk;
-+	u64 tx_ra_bitmap = 0;
-+
-+	if (!pbuf)
-+		return H2C_PARAMETERS_ERROR;
-+
-+	TDLSoption = (struct TDLSoption_param *)pbuf;
-+	option = TDLSoption->option;
-+
-+	if (!_rtw_memcmp(TDLSoption->addr, zaddr, ETH_ALEN)) {
-+		ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), TDLSoption->addr);
-+		if (ptdls_sta == NULL)
-+			return H2C_REJECTED;
-+	} else {
-+		if (!(option == TDLS_RS_RCR))
-+			return H2C_REJECTED;
-+	}
-+
-+	/* _enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); */
-+	/* RTW_INFO("[%s] option:%d\n", __FUNCTION__, option); */
-+
-+	switch (option) {
-+	case TDLS_ESTABLISHED: {
-+		/* As long as TDLS handshake success, we should set RCR_CBSSID_DATA bit to 0 */
-+		/* So we can receive all kinds of data frames. */
-+		u8 sta_band = 0;
-+
-+		/* leave ALL PS when TDLS is established */
-+		rtw_pwr_wakeup(padapter);
-+
-+		rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_LINKED);
-+		RTW_INFO("Created Direct Link with "MAC_FMT"\n", MAC_ARG(ptdls_sta->cmn.mac_addr));
-+
-+		/* Set TDLS sta rate. */
-+		/* Update station supportRate */
-+		rtw_hal_update_sta_ra_info(padapter, ptdls_sta);
-+		tx_ra_bitmap = ptdls_sta->cmn.ra_info.ramask;
-+
-+		if (pmlmeext->cur_channel > 14) {
-+			if (tx_ra_bitmap & 0xffff000)
-+				sta_band |= WIRELESS_11_5N ;
-+
-+			if (tx_ra_bitmap & 0xff0)
-+				sta_band |= WIRELESS_11A;
-+
-+			/* 5G band */
-+#ifdef CONFIG_80211AC_VHT
-+			if (ptdls_sta->vhtpriv.vht_option)
-+				sta_band = WIRELESS_11_5AC;
-+#endif
-+
-+		} else {
-+			if (tx_ra_bitmap & 0xffff000)
-+				sta_band |= WIRELESS_11_24N;
-+
-+			if (tx_ra_bitmap & 0xff0)
-+				sta_band |= WIRELESS_11G;
-+
-+			if (tx_ra_bitmap & 0x0f)
-+				sta_band |= WIRELESS_11B;
-+		}
-+		ptdls_sta->wireless_mode = sta_band;
-+		rtw_hal_update_sta_wset(padapter, ptdls_sta);
-+		/* Sta mode */
-+		rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, ptdls_sta, _TRUE);
-+
-+		set_sta_rate(padapter, ptdls_sta);
-+		rtw_sta_media_status_rpt(padapter, ptdls_sta, 1);
-+		break;
-+	}
-+	case TDLS_ISSUE_PTI:
-+		ptdls_sta->tdls_sta_state |= TDLS_WAIT_PTR_STATE;
-+		issue_tdls_peer_traffic_indication(padapter, ptdls_sta);
-+		_set_timer(&ptdls_sta->pti_timer, TDLS_PTI_TIME);
-+		break;
-+#ifdef CONFIG_TDLS_CH_SW
-+	case TDLS_CH_SW_RESP:
-+		_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+		txmgmt.status_code = 0;
-+		_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
-+
-+		if (ap_sta)
-+			rtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id);
-+		issue_nulldata(padapter, NULL, 1, 3, 3);
-+
-+		RTW_INFO("[TDLS ] issue tdls channel switch response\n");
-+		ret = issue_tdls_ch_switch_rsp(padapter, &txmgmt, _TRUE);
-+
-+		/* If we receive TDLS_CH_SW_REQ at off channel which it's target is AP's channel */
-+		/* then we just switch to AP's channel*/
-+		if (padapter->mlmeextpriv.cur_channel == pchsw_info->off_ch_num) {
-+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL);
-+			break;
-+		}
-+
-+		if (ret == _SUCCESS)
-+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL);
-+		else
-+			RTW_INFO("[TDLS] issue_tdls_ch_switch_rsp wait ack fail !!!!!!!!!!\n");
-+
-+		break;
-+	case TDLS_CH_SW_PREPARE:
-+		pchsw_info->ch_sw_state |= TDLS_CH_SWITCH_PREPARE_STATE;
-+
-+		/* to collect IQK info of off-chnl */
-+		doiqk = _TRUE;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk);
-+		set_channel_bwmode(padapter, pchsw_info->off_ch_num, pchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20);
-+		doiqk = _FALSE;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk);
-+
-+		/* switch back to base-chnl */
-+		doiqk = _TRUE;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk);
-+		set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
-+		doiqk = _FALSE;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk);
-+
-+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);
-+
-+		pchsw_info->ch_sw_state &= ~(TDLS_CH_SWITCH_PREPARE_STATE);
-+
-+		break;
-+	case TDLS_CH_SW_START:
-+		rtw_tdls_set_ch_sw_oper_control(padapter, _TRUE);
-+		break;
-+	case TDLS_CH_SW_TO_OFF_CHNL:
-+		if (ap_sta)
-+			rtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id);
-+		issue_nulldata(padapter, NULL, 1, 3, 3);
-+
-+		if (padapter->registrypriv.wifi_spec == 0) {
-+		if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
-+			_set_timer(&ptdls_sta->ch_sw_timer, (u32)(ptdls_sta->ch_switch_timeout) / 1000);
-+		}
-+
-+		if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_OFF_CHNL, pchsw_info->off_ch_num,
-+			pchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20, ptdls_sta->ch_switch_time) == _SUCCESS) {
-+			pchsw_info->ch_sw_state &= ~(TDLS_PEER_AT_OFF_STATE);
-+			if (pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) {
-+				if (issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta->cmn.mac_addr, 0, 1, 
-+					(padapter->registrypriv.wifi_spec == 0) ? 3 : 0) == _FAIL)
-+					rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);
-+			}
-+		} else {
-+			if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
-+				_cancel_timer_ex(&ptdls_sta->ch_sw_timer);
-+		}
-+
-+
-+		break;
-+	case TDLS_CH_SW_END:
-+	case TDLS_CH_SW_END_TO_BASE_CHNL:
-+		rtw_tdls_set_ch_sw_oper_control(padapter, _FALSE);
-+		_cancel_timer_ex(&ptdls_sta->ch_sw_timer);
-+		_cancel_timer_ex(&ptdls_sta->stay_on_base_chnl_timer);
-+		_cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer);
-+#if 0
-+		_rtw_memset(pHalData->tdls_ch_sw_iqk_info_base_chnl, 0x00, sizeof(pHalData->tdls_ch_sw_iqk_info_base_chnl));
-+		_rtw_memset(pHalData->tdls_ch_sw_iqk_info_off_chnl, 0x00, sizeof(pHalData->tdls_ch_sw_iqk_info_off_chnl));
-+#endif
-+
-+		if (option == TDLS_CH_SW_END_TO_BASE_CHNL)
-+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);
-+
-+		break;
-+	case TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED:
-+	case TDLS_CH_SW_TO_BASE_CHNL:
-+		pchsw_info->ch_sw_state &= ~(TDLS_PEER_AT_OFF_STATE | TDLS_WAIT_CH_RSP_STATE);
-+
-+		if (option == TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED) {
-+			if (ptdls_sta != NULL) {
-+				/* Send unsolicited channel switch rsp. to peer */
-+				_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+				txmgmt.status_code = 0;
-+				_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
-+				issue_tdls_ch_switch_rsp(padapter, &txmgmt, _FALSE);
-+			}
-+		}
-+
-+		if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_BASE_CHNL, pmlmeext->cur_channel,
-+			pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode, ptdls_sta->ch_switch_time) == _SUCCESS) {
-+			if (ap_sta)
-+				rtw_hal_macid_wakeup(padapter, ap_sta->cmn.mac_id);
-+			issue_nulldata(padapter, NULL, 0, 3, 3);
-+			/* set ch sw monitor timer for responder */
-+			if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
-+				_set_timer(&ptdls_sta->ch_sw_monitor_timer, TDLS_CH_SW_MONITOR_TIMEOUT);
-+		}
-+
-+		break;
-+#endif
-+	case TDLS_RS_RCR:
-+		rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_NOLINK);
-+		break;
-+	case TDLS_TEARDOWN_STA:
-+	case TDLS_TEARDOWN_STA_NO_WAIT:
-+		_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+		txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;
-+		_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
-+
-+		issue_tdls_teardown(padapter, &txmgmt, (option == TDLS_TEARDOWN_STA) ? _TRUE : _FALSE);
-+
-+		break;
-+	case TDLS_TEARDOWN_STA_LOCALLY:
-+	case TDLS_TEARDOWN_STA_LOCALLY_POST:
-+#ifdef CONFIG_TDLS_CH_SW
-+		if (_rtw_memcmp(TDLSoption->addr, pchsw_info->addr, ETH_ALEN) == _TRUE) {
-+			pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE |
-+						     TDLS_CH_SWITCH_ON_STATE |
-+						     TDLS_PEER_AT_OFF_STATE);
-+			rtw_tdls_set_ch_sw_oper_control(padapter, _FALSE);
-+			_rtw_memset(pchsw_info->addr, 0x00, ETH_ALEN);
-+		}
-+#endif
-+
-+		if (option == TDLS_TEARDOWN_STA_LOCALLY)
-+			rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
-+
-+		rtw_tdls_teardown_post_hdl(padapter, ptdls_sta, _FALSE);
-+
-+		if (ptdlsinfo->tdls_sctx != NULL)
-+			rtw_sctx_done(&(ptdlsinfo->tdls_sctx));
-+
-+		break;
-+	}
-+
-+	/* _exit_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); */
-+
-+	return H2C_SUCCESS;
-+#else
-+	return H2C_REJECTED;
-+#endif /* CONFIG_TDLS */
-+
-+}
-+
-+u8 run_in_thread_hdl(_adapter *padapter, u8 *pbuf)
-+{
-+	struct RunInThread_param *p;
-+
-+
-+	if (NULL == pbuf)
-+		return H2C_PARAMETERS_ERROR;
-+	p = (struct RunInThread_param *)pbuf;
-+
-+	if (p->func)
-+		p->func(p->context);
-+
-+	return H2C_SUCCESS;
-+}
-+
-+int rtw_sae_preprocess(_adapter *adapter, const u8 *buf, u32 len, u8 tx)
-+{
-+#ifdef CONFIG_IOCTL_CFG80211
-+	const u8 *frame_body = buf + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	u16 alg;
-+	u16 seq;
-+	u16 status;
-+	int ret = _FAIL;
-+
-+	alg = RTW_GET_LE16(frame_body);
-+	if (alg != WLAN_AUTH_SAE)
-+		goto exit;
-+
-+	seq = RTW_GET_LE16(frame_body + 2);
-+	status = RTW_GET_LE16(frame_body + 4);
-+
-+	RTW_INFO("RTW_%s:AUTH alg:0x%04x, seq:0x%04x, status:0x%04x, mesg:%s\n",
-+		(tx == _TRUE) ? "Tx" : "Rx", alg, seq, status,
-+		(seq == 1) ? "Commit" : "Confirm");
-+
-+	ret = _SUCCESS;
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(adapter)) {
-+		rtw_mesh_sae_check_frames(adapter, buf, len, tx, alg, seq, status);
-+		goto exit;
-+	}
-+#endif
-+
-+	if (tx && (seq == 2) && (status == 0)) {
-+		/* quere commit frame until external auth statue update */
-+		struct sta_priv *pstapriv = &adapter->stapriv;
-+		struct sta_info	*psta = NULL;
-+		_irqL irqL;
-+
-+		psta = rtw_get_stainfo(pstapriv, GetAddr1Ptr(buf));
-+		if (psta) {
-+			_enter_critical_bh(&psta->lock, &irqL);
-+			if (psta->pauth_frame) {
-+				rtw_mfree(psta->pauth_frame, psta->auth_len);
-+				psta->pauth_frame = NULL;
-+				psta->auth_len = 0;
-+			}
-+
-+			psta->pauth_frame =  rtw_zmalloc(len);
-+			if (psta->pauth_frame) {
-+				_rtw_memcpy(psta->pauth_frame, buf, len);
-+				psta->auth_len = len;
-+			}
-+			_exit_critical_bh(&psta->lock, &irqL);
-+
-+			ret = 2;
-+		}
-+	}
-+exit:
-+	return ret;
-+#else
-+	return _SUCCESS;
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/core/rtw_mp.c b/drivers/staging/rtl8723cs/core/rtw_mp.c
-new file mode 100644
-index 000000000000..65ae02f61b28
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_mp.c
-@@ -0,0 +1,3991 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_MP_C_
-+#include <drv_types.h>
-+#ifdef PLATFORM_FREEBSD
-+	#include <sys/unistd.h>		/* for RFHIGHPID */
-+#endif
-+
-+#include "../hal/phydm/phydm_precomp.h"
-+#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
-+	#include <rtw_bt_mp.h>
-+#endif
-+
-+#ifdef CONFIG_MP_VHT_HW_TX_MODE
-+#define CEILING_POS(X) ((X - (int)(X)) > 0 ? (int)(X + 1) : (int)(X))
-+#define CEILING_NEG(X) ((X - (int)(X)) < 0 ? (int)(X - 1) : (int)(X))
-+#define ceil(X) (((X) > 0) ? CEILING_POS(X) : CEILING_NEG(X))
-+
-+int rtfloor(float x)
-+{
-+	int i = x - 2;
-+	while
-+	(++i <= x - 1)
-+		;
-+	return i;
-+}
-+#endif
-+
-+#ifdef CONFIG_MP_INCLUDED
-+u32 read_macreg(_adapter *padapter, u32 addr, u32 sz)
-+{
-+	u32 val = 0;
-+
-+	switch (sz) {
-+	case 1:
-+		val = rtw_read8(padapter, addr);
-+		break;
-+	case 2:
-+		val = rtw_read16(padapter, addr);
-+		break;
-+	case 4:
-+		val = rtw_read32(padapter, addr);
-+		break;
-+	default:
-+		val = 0xffffffff;
-+		break;
-+	}
-+
-+	return val;
-+
-+}
-+
-+void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz)
-+{
-+	switch (sz) {
-+	case 1:
-+		rtw_write8(padapter, addr, (u8)val);
-+		break;
-+	case 2:
-+		rtw_write16(padapter, addr, (u16)val);
-+		break;
-+	case 4:
-+		rtw_write32(padapter, addr, val);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+}
-+
-+u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask)
-+{
-+	return rtw_hal_read_bbreg(padapter, addr, bitmask);
-+}
-+
-+void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val)
-+{
-+	rtw_hal_write_bbreg(padapter, addr, bitmask, val);
-+}
-+
-+u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask)
-+{
-+	return rtw_hal_read_rfreg(padapter, rfpath, addr, bitmask);
-+}
-+
-+void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val)
-+{
-+	rtw_hal_write_rfreg(padapter, rfpath, addr, bitmask, val);
-+}
-+
-+u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr)
-+{
-+	return _read_rfreg(padapter, rfpath, addr, bRFRegOffsetMask);
-+}
-+
-+void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val)
-+{
-+	_write_rfreg(padapter, rfpath, addr, bRFRegOffsetMask, val);
-+}
-+
-+static void _init_mp_priv_(struct mp_priv *pmp_priv)
-+{
-+	WLAN_BSSID_EX *pnetwork;
-+
-+	_rtw_memset(pmp_priv, 0, sizeof(struct mp_priv));
-+
-+	pmp_priv->mode = MP_OFF;
-+
-+	pmp_priv->channel = 1;
-+	pmp_priv->bandwidth = CHANNEL_WIDTH_20;
-+	pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	pmp_priv->rateidx = RATE_1M;
-+	pmp_priv->txpoweridx = 0x2A;
-+
-+	pmp_priv->antenna_tx = ANTENNA_A;
-+	pmp_priv->antenna_rx = ANTENNA_AB;
-+
-+	pmp_priv->check_mp_pkt = 0;
-+
-+	pmp_priv->tx_pktcount = 0;
-+
-+	pmp_priv->rx_bssidpktcount = 0;
-+	pmp_priv->rx_pktcount = 0;
-+	pmp_priv->rx_crcerrpktcount = 0;
-+
-+	pmp_priv->network_macaddr[0] = 0x00;
-+	pmp_priv->network_macaddr[1] = 0xE0;
-+	pmp_priv->network_macaddr[2] = 0x4C;
-+	pmp_priv->network_macaddr[3] = 0x87;
-+	pmp_priv->network_macaddr[4] = 0x66;
-+	pmp_priv->network_macaddr[5] = 0x55;
-+
-+	pmp_priv->bSetRxBssid = _FALSE;
-+	pmp_priv->bRTWSmbCfg = _FALSE;
-+	pmp_priv->bloopback = _FALSE;
-+
-+	pmp_priv->bloadefusemap = _FALSE;
-+	pmp_priv->brx_filter_beacon = _FALSE;
-+	pmp_priv->mplink_brx = _FALSE;
-+
-+	pnetwork = &pmp_priv->mp_network.network;
-+	_rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN);
-+
-+	pnetwork->Ssid.SsidLength = 8;
-+	_rtw_memcpy(pnetwork->Ssid.Ssid, "mp_871x", pnetwork->Ssid.SsidLength);
-+
-+	pmp_priv->tx.payload = MP_TX_Payload_default_random;
-+#ifdef CONFIG_80211N_HT
-+	pmp_priv->tx.attrib.ht_en = 1;
-+#endif
-+
-+	pmp_priv->mpt_ctx.mpt_rate_index = 1;
-+
-+}
-+
-+
-+static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	struct pkt_attrib *pattrib;
-+
-+	/* init xmitframe attribute */
-+	pattrib = &pmptx->attrib;
-+	_rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));
-+	_rtw_memset(pmptx->desc, 0, TXDESC_SIZE);
-+
-+	pattrib->ether_type = 0x8712;
-+#if 0
-+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+#endif
-+	_rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
-+
-+	/*	pattrib->dhcp_pkt = 0;
-+	 *	pattrib->pktlen = 0; */
-+	pattrib->ack_policy = 0;
-+	/*	pattrib->pkt_hdrlen = ETH_HLEN; */
-+	pattrib->hdrlen = WLAN_HDR_A3_LEN;
-+	pattrib->subtype = WIFI_DATA;
-+	pattrib->priority = 0;
-+	pattrib->qsel = pattrib->priority;
-+	/*	do_queue_select(padapter, pattrib); */
-+	pattrib->nr_frags = 1;
-+	pattrib->encrypt = 0;
-+	pattrib->bswenc = _FALSE;
-+	pattrib->qos_en = _FALSE;
-+
-+	pattrib->pktlen = 1500;
-+
-+	if (pHalData->rf_type == RF_2T2R)
-+		pattrib->raid = RATEID_IDX_BGN_40M_2SS;
-+	else
-+		pattrib->raid = RATEID_IDX_BGN_40M_1SS;
-+
-+#ifdef CONFIG_80211AC_VHT
-+	if (pHalData->rf_type == RF_1T1R)
-+		pattrib->raid = RATEID_IDX_VHT_1SS;
-+	else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
-+		pattrib->raid = RATEID_IDX_VHT_2SS;
-+	else if (pHalData->rf_type == RF_3T3R)
-+		pattrib->raid = RATEID_IDX_VHT_3SS;
-+	else
-+		pattrib->raid = RATEID_IDX_BGN_40M_1SS;
-+#endif
-+}
-+
-+s32 init_mp_priv(PADAPTER padapter)
-+{
-+	struct mp_priv *pmppriv = &padapter->mppriv;
-+	PHAL_DATA_TYPE pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	_init_mp_priv_(pmppriv);
-+	pmppriv->papdater = padapter;
-+	if (IS_HARDWARE_TYPE_8822C(padapter))
-+		pmppriv->mp_dm = 1;/* default enable dpk tracking */
-+	else
-+		pmppriv->mp_dm = 0;
-+
-+	pmppriv->tx.stop = 1;
-+	pmppriv->bSetTxPower = 0;		/*for  manually set tx power*/
-+	pmppriv->bTxBufCkFail = _FALSE;
-+	pmppriv->pktInterval = 0;
-+	pmppriv->pktLength = 1000;
-+	pmppriv->bprocess_mp_mode = _FALSE;
-+	pmppriv->efuse_update_file= _FALSE;
-+
-+	mp_init_xmit_attrib(&pmppriv->tx, padapter);
-+
-+	switch (GET_HAL_RFPATH(padapter)) {
-+	case RF_1T1R:
-+		pmppriv->antenna_tx = ANTENNA_A;
-+		pmppriv->antenna_rx = ANTENNA_A;
-+		break;
-+	case RF_1T2R:
-+	default:
-+		pmppriv->antenna_tx = ANTENNA_A;
-+		pmppriv->antenna_rx = ANTENNA_AB;
-+		break;
-+	case RF_2T2R:
-+		pmppriv->antenna_tx = ANTENNA_AB;
-+		pmppriv->antenna_rx = ANTENNA_AB;
-+		break;
-+	case RF_2T4R:
-+		pmppriv->antenna_tx = ANTENNA_BC;
-+		pmppriv->antenna_rx = ANTENNA_ABCD;
-+		break;
-+	}
-+
-+	pHalData->AntennaRxPath = pmppriv->antenna_rx;
-+	pHalData->antenna_tx_path = pmppriv->antenna_tx;
-+
-+	return _SUCCESS;
-+}
-+
-+void free_mp_priv(struct mp_priv *pmp_priv)
-+{
-+	if (pmp_priv->pallocated_mp_xmitframe_buf) {
-+		rtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0);
-+		pmp_priv->pallocated_mp_xmitframe_buf = NULL;
-+	}
-+	pmp_priv->pmp_xmtframe_buf = NULL;
-+}
-+
-+#if 0
-+static void PHY_IQCalibrate_default(
-+		PADAPTER	pAdapter,
-+		BOOLEAN	bReCovery
-+)
-+{
-+	RTW_INFO("%s\n", __func__);
-+}
-+
-+static void PHY_LCCalibrate_default(
-+		PADAPTER	pAdapter
-+)
-+{
-+	RTW_INFO("%s\n", __func__);
-+}
-+
-+static void PHY_SetRFPathSwitch_default(
-+		PADAPTER	pAdapter,
-+		BOOLEAN		bMain
-+)
-+{
-+	RTW_INFO("%s\n", __func__);
-+}
-+#endif
-+
-+void mpt_InitHWConfig(PADAPTER Adapter)
-+{
-+	PHAL_DATA_TYPE hal;
-+
-+	hal = GET_HAL_DATA(Adapter);
-+
-+	if (IS_HARDWARE_TYPE_8723B(Adapter)) {
-+		/* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */
-+		/* TODO:  A better solution is configure it according EFUSE during the run-time. */
-+
-+		phy_set_mac_reg(Adapter, 0x64, BIT20, 0x0);		/* 0x66[4]=0		 */
-+		phy_set_mac_reg(Adapter, 0x64, BIT24, 0x0);		/* 0x66[8]=0 */
-+		phy_set_mac_reg(Adapter, 0x40, BIT4, 0x0);		/* 0x40[4]=0		 */
-+		phy_set_mac_reg(Adapter, 0x40, BIT3, 0x1);		/* 0x40[3]=1		 */
-+		phy_set_mac_reg(Adapter, 0x4C, BIT24, 0x1);		/* 0x4C[24:23]=10 */
-+		phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0);		/* 0x4C[24:23]=10 */
-+		phy_set_bb_reg(Adapter, 0x944, BIT1 | BIT0, 0x3);	/* 0x944[1:0]=11	 */
-+		phy_set_bb_reg(Adapter, 0x930, bMaskByte0, 0x77);/* 0x930[7:0]=77	  */
-+		phy_set_mac_reg(Adapter, 0x38, BIT11, 0x1);/* 0x38[11]=1 */
-+
-+		/* TODO: <20130206, Kordan> The default setting is wrong, hard-coded here. */
-+		phy_set_mac_reg(Adapter, 0x778, 0x3, 0x3);					/* Turn off hardware PTA control (Asked by Scott) */
-+		phy_set_mac_reg(Adapter, 0x64, bMaskDWord, 0x36000000);/* Fix BT S0/S1 */
-+		phy_set_mac_reg(Adapter, 0x948, bMaskDWord, 0x0);		/* Fix BT can't Tx */
-+
-+		/* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */
-+		phy_set_bb_reg(Adapter, 0xA00, BIT8, 0x0);			/*0xA01[0] = 0*/
-+	} else if (IS_HARDWARE_TYPE_8821(Adapter)) {
-+		/* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock)
-+		<20131122, VincentL> Enable for all 8821A/8811AU  (Asked by Alex)*/
-+		phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0);		/*0x4C[23:22]=01*/
-+		phy_set_mac_reg(Adapter, 0x4C, BIT22, 0x1);		/*0x4C[23:22]=01*/
-+	} else if (IS_HARDWARE_TYPE_8188ES(Adapter))
-+		phy_set_mac_reg(Adapter, 0x4C , BIT23, 0);		/*select DPDT_P and DPDT_N as output pin*/
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(Adapter))
-+		PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000);
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(Adapter)) {
-+		rtw_write32(Adapter, 0x520, rtw_read32(Adapter, 0x520) | 0x8000);
-+		rtw_write32(Adapter, 0x524, rtw_read32(Adapter, 0x524) & (~0x800));
-+	}
-+#endif
-+
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(Adapter)) {
-+		u32 tmp_reg = 0;
-+
-+		PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000);
-+		/* fixed wifi can't 2.4g tx suggest by Szuyitasi 20160504 */
-+		phy_set_bb_reg(Adapter, 0x70, bMaskByte3, 0x0e);
-+		RTW_INFO(" 0x73 = 0x%x\n", phy_query_bb_reg(Adapter, 0x70, bMaskByte3));
-+		phy_set_bb_reg(Adapter, 0x1704, bMaskDWord, 0x0000ff00);
-+		RTW_INFO(" 0x1704 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1704, bMaskDWord));
-+		phy_set_bb_reg(Adapter, 0x1700, bMaskDWord, 0xc00f0038);
-+		RTW_INFO(" 0x1700 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1700, bMaskDWord));
-+	}
-+#endif /* CONFIG_RTL8822B */
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(Adapter))
-+		PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000);
-+#endif /* CONFIG_RTL8821C */
-+#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
-+	else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
-+		if (IS_A_CUT(hal->version_id) || IS_B_CUT(hal->version_id)) {
-+			RTW_INFO("%s() Active large power detection\n", __func__);
-+			phy_active_large_power_detection_8188f(&(GET_HAL_DATA(Adapter)->odmpriv));
-+		}
-+	}
-+#endif
-+#if defined(CONFIG_RTL8822C)
-+	else if( IS_HARDWARE_TYPE_8822C(Adapter)) {
-+		rtw_write16(Adapter, REG_RXFLTMAP1_8822C, 0x2000);
-+		/* 0x7D8[31] : time out enable when cca is not assert
-+			0x60D[7:0] : time out value (Unit : us)*/
-+		rtw_write8(Adapter, 0x7db, 0xc0);
-+		RTW_INFO(" 0x7d8 = 0x%x\n", rtw_read8(Adapter, 0x7d8));
-+		rtw_write8(Adapter, 0x60d, 0x0c);
-+		RTW_INFO(" 0x60d = 0x%x\n", rtw_read8(Adapter, 0x60d));
-+		phy_set_bb_reg(Adapter, 0x1c44, BIT10, 0x1);
-+		RTW_INFO(" 0x1c44 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1c44, bMaskDWord));
-+	}
-+#endif
-+#if defined(CONFIG_RTL8814B)
-+	else if(IS_HARDWARE_TYPE_8814B(Adapter))
-+	{
-+		PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814B, 0x2000);
-+	}
-+#endif
-+#if defined(CONFIG_RTL8723F)
-+	/* todo: 8723F not verify yet */
-+	else if (IS_HARDWARE_TYPE_8723F(Adapter)) {
-+		/* 8723F mac is similar with 8723D,
-+		 * but can't find 8723D here.
-+		 */
-+	}
-+#endif
-+}
-+
-+static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)
-+{
-+	halrf_iqk_trigger(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
-+}
-+
-+static void PHY_LCCalibrate(PADAPTER padapter)
-+{
-+	halrf_lck_trigger(&(GET_HAL_DATA(padapter)->odmpriv));
-+}
-+
-+static u8 PHY_QueryRFPathSwitch(PADAPTER padapter)
-+{
-+	u8 bmain = 0;
-+/*
-+	if (IS_HARDWARE_TYPE_8723B(padapter)) {
-+#ifdef CONFIG_RTL8723B
-+		bmain = PHY_QueryRFPathSwitch_8723B(padapter);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8188E(padapter)) {
-+#ifdef CONFIG_RTL8188E
-+		bmain = PHY_QueryRFPathSwitch_8188E(padapter);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8814A(padapter)) {
-+#ifdef CONFIG_RTL8814A
-+		bmain = PHY_QueryRFPathSwitch_8814A(padapter);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+		bmain = PHY_QueryRFPathSwitch_8812A(padapter);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8192E(padapter)) {
-+#ifdef CONFIG_RTL8192E
-+		bmain = PHY_QueryRFPathSwitch_8192E(padapter);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8703B(padapter)) {
-+#ifdef CONFIG_RTL8703B
-+		bmain = PHY_QueryRFPathSwitch_8703B(padapter);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8188F(padapter)) {
-+#ifdef CONFIG_RTL8188F
-+		bmain = PHY_QueryRFPathSwitch_8188F(padapter);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8188GTV(padapter)) {
-+#ifdef CONFIG_RTL8188GTV
-+		bmain = PHY_QueryRFPathSwitch_8188GTV(padapter);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8822B(padapter)) {
-+#ifdef CONFIG_RTL8822B
-+		bmain = PHY_QueryRFPathSwitch_8822B(padapter);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8723D(padapter)) {
-+#ifdef CONFIG_RTL8723D
-+		bmain = PHY_QueryRFPathSwitch_8723D(padapter);
-+#endif
-+	} else
-+*/
-+
-+	if (IS_HARDWARE_TYPE_8821C(padapter)) {
-+#ifdef CONFIG_RTL8821C
-+		bmain = phy_query_rf_path_switch_8821c(padapter);
-+#endif
-+	}
-+
-+	return bmain;
-+}
-+
-+static void  PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) {
-+
-+	PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
-+	struct dm_struct *phydm = &hal->odmpriv;
-+
-+	if (IS_HARDWARE_TYPE_8723B(padapter)) {
-+#ifdef CONFIG_RTL8723B
-+		phy_set_rf_path_switch_8723b(phydm, bMain);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8188E(padapter)) {
-+#ifdef CONFIG_RTL8188E
-+		phy_set_rf_path_switch_8188e(phydm, bMain);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8814A(padapter)) {
-+#ifdef CONFIG_RTL8814A
-+		phy_set_rf_path_switch_8814a(phydm, bMain);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+		phy_set_rf_path_switch_8812a(phydm, bMain);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8192E(padapter)) {
-+#ifdef CONFIG_RTL8192E
-+		phy_set_rf_path_switch_8192e(phydm, bMain);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8703B(padapter)) {
-+#ifdef CONFIG_RTL8703B
-+		phy_set_rf_path_switch_8703b(phydm, bMain);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8188F(padapter) || IS_HARDWARE_TYPE_8188GTV(padapter)) {
-+#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
-+		phy_set_rf_path_switch_8188f(phydm, bMain);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8192F(padapter)) {
-+#ifdef CONFIG_RTL8192F
-+		phy_set_rf_path_switch_8192f(padapter, bMain);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8822B(padapter)) {
-+#ifdef CONFIG_RTL8822B
-+		phy_set_rf_path_switch_8822b(phydm, bMain);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8723D(padapter)) {
-+#ifdef CONFIG_RTL8723D
-+		phy_set_rf_path_switch_8723d(phydm, bMain);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8821C(padapter)) {
-+#ifdef CONFIG_RTL8821C
-+		phy_set_rf_path_switch_8821c(phydm, bMain);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8822C(padapter)) {
-+#ifdef CONFIG_RTL8822C
-+		phy_set_rf_path_switch_8822c(phydm, bMain);
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8814B(padapter)) {
-+#ifdef CONFIG_RTL8814B
-+		/* phy_set_rf_path_switch_8814b(phydm, bMain); */
-+#endif
-+	} else if (IS_HARDWARE_TYPE_8723F(padapter)) {
-+#ifdef CONFIG_RTL8723F
-+		phy_set_rf_path_switch_8723f(phydm, bMain);
-+#endif
-+	}
-+}
-+
-+
-+static void phy_switch_rf_path_set(PADAPTER padapter , u8 *prf_set_State) {
-+#ifdef CONFIG_RTL8821C
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+	struct dm_struct *p_dm = &pHalData->odmpriv;
-+
-+	if (IS_HARDWARE_TYPE_8821C(padapter)) {
-+		config_phydm_set_ant_path(p_dm, *prf_set_State, p_dm->current_ant_num_8821c);
-+		/* Do IQK when switching to BTG/WLG, requested by RF Binson */
-+		if (*prf_set_State == SWITCH_TO_BTG || *prf_set_State == SWITCH_TO_WLG)
-+			PHY_IQCalibrate(padapter, FALSE);
-+	}
-+#endif
-+
-+}
-+
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+	u8 cur_ant, change_ant;
-+
-+	if (!pHalData->AntDivCfg)
-+		return _FALSE;
-+	/*rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);*/
-+	change_ant = (bMain == MAIN_ANT) ? MAIN_ANT : AUX_ANT;
-+
-+	RTW_INFO("%s: config %s\n", __func__, (bMain == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
-+	rtw_antenna_select_cmd(padapter, change_ant, _FALSE);
-+
-+	return _TRUE;
-+}
-+#endif
-+
-+s32
-+MPT_InitializeAdapter(
-+		PADAPTER			pAdapter,
-+		u8				Channel
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	s32		rtStatus = _SUCCESS;
-+	PMPT_CONTEXT	pMptCtx = &pAdapter->mppriv.mpt_ctx;
-+	u32		ledsetting;
-+
-+	pMptCtx->bMptDrvUnload = _FALSE;
-+	pMptCtx->bMassProdTest = _FALSE;
-+	pMptCtx->bMptIndexEven = _TRUE;	/* default gain index is -6.0db */
-+	pMptCtx->h2cReqNum = 0x0;
-+	/* init for BT MP */
-+#if defined(CONFIG_RTL8723B)
-+	pMptCtx->bMPh2c_timeout = _FALSE;
-+	pMptCtx->MptH2cRspEvent = _FALSE;
-+	pMptCtx->MptBtC2hEvent = _FALSE;
-+	_rtw_init_sema(&pMptCtx->MPh2c_Sema, 0);
-+	rtw_init_timer(&pMptCtx->MPh2c_timeout_timer, pAdapter, MPh2c_timeout_handle, pAdapter);
-+#endif
-+
-+	mpt_InitHWConfig(pAdapter);
-+
-+#ifdef CONFIG_RTL8723B
-+	rtl8723b_InitAntenna_Selection(pAdapter);
-+	if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
-+
-+		/* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/
-+		phy_set_bb_reg(pAdapter, 0xA00, BIT8, 0x0);
-+		PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/
-+
-+		if (pHalData->PackageType == PACKAGE_DEFAULT)
-+			phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
-+		else
-+			phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6F10E);
-+
-+	}
-+	/*set ant to wifi side in mp mode*/
-+	rtw_write16(pAdapter, 0x870, 0x300);
-+	rtw_write16(pAdapter, 0x860, 0x110);
-+#endif
-+
-+	pMptCtx->bMptWorkItemInProgress = _FALSE;
-+	pMptCtx->CurrMptAct = NULL;
-+	pMptCtx->mpt_rf_path = RF_PATH_A;
-+	/* ------------------------------------------------------------------------- */
-+	/* Don't accept any packets */
-+	rtw_write32(pAdapter, REG_RCR, 0);
-+
-+	/* ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); */
-+	/* rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); */
-+
-+	/* rtw_write32(pAdapter, REG_LEDCFG0, 0x08080); */
-+	ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
-+
-+
-+	PHY_LCCalibrate(pAdapter);
-+	PHY_IQCalibrate(pAdapter, _FALSE);
-+	/* dm_check_txpowertracking(&pHalData->odmpriv);	*/ /* trigger thermal meter */
-+
-+	PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /* default use Main */
-+
-+	pMptCtx->backup0xc50 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
-+	pMptCtx->backup0xc58 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
-+	pMptCtx->backup0xc30 = (u8)phy_query_bb_reg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
-+	pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
-+	pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
-+#ifdef CONFIG_RTL8188E
-+	rtw_write32(pAdapter, REG_MACID_NO_LINK_0, 0x0);
-+	rtw_write32(pAdapter, REG_MACID_NO_LINK_1, 0x0);
-+#endif
-+#ifdef CONFIG_RTL8814A
-+	if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
-+		pHalData->BackUp_IG_REG_4_Chnl_Section[0] = (u8)phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
-+		pHalData->BackUp_IG_REG_4_Chnl_Section[1] = (u8)phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
-+		pHalData->BackUp_IG_REG_4_Chnl_Section[2] = (u8)phy_query_bb_reg(pAdapter, rC_IGI_Jaguar2, bMaskByte0);
-+		pHalData->BackUp_IG_REG_4_Chnl_Section[3] = (u8)phy_query_bb_reg(pAdapter, rD_IGI_Jaguar2, bMaskByte0);
-+	}
-+#endif
-+	return	rtStatus;
-+}
-+
-+/*-----------------------------------------------------------------------------
-+ * Function:	MPT_DeInitAdapter()
-+ *
-+ * Overview:	Extra DeInitialization for Mass Production Test.
-+ *
-+ * Input:		PADAPTER	pAdapter
-+ *
-+ * Output:		NONE
-+ *
-+ * Return:		NONE
-+ *
-+ * Revised History:
-+ *	When		Who		Remark
-+ *	05/08/2007	MHC		Create Version 0.
-+ *	05/18/2007	MHC		Add normal driver MPHalt code.
-+ *
-+ *---------------------------------------------------------------------------*/
-+void
-+MPT_DeInitAdapter(
-+		PADAPTER	pAdapter
-+)
-+{
-+	PMPT_CONTEXT		pMptCtx = &pAdapter->mppriv.mpt_ctx;
-+
-+	pMptCtx->bMptDrvUnload = _TRUE;
-+#if defined(CONFIG_RTL8723B)
-+	_rtw_free_sema(&(pMptCtx->MPh2c_Sema));
-+	_cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
-+#endif
-+#if	defined(CONFIG_RTL8723B)
-+	phy_set_bb_reg(pAdapter, 0xA01, BIT0, 1); /* /suggestion  by jerry for MP Rx. */
-+#endif
-+#if 0 /* for Windows */
-+	PlatformFreeWorkItem(&(pMptCtx->MptWorkItem));
-+
-+	while (pMptCtx->bMptWorkItemInProgress) {
-+		if (NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50))
-+			break;
-+	}
-+	NdisFreeSpinLock(&(pMptCtx->MptWorkItemSpinLock));
-+#endif
-+}
-+
-+static u8 mpt_ProStartTest(PADAPTER padapter)
-+{
-+	PMPT_CONTEXT pMptCtx = &padapter->mppriv.mpt_ctx;
-+
-+	pMptCtx->bMassProdTest = _TRUE;
-+	pMptCtx->is_start_cont_tx = _FALSE;
-+	pMptCtx->bCckContTx = _FALSE;
-+	pMptCtx->bOfdmContTx = _FALSE;
-+	pMptCtx->bSingleCarrier = _FALSE;
-+	pMptCtx->is_carrier_suppression = _FALSE;
-+	pMptCtx->is_single_tone = _FALSE;
-+	pMptCtx->HWTxmode = PACKETS_TX;
-+
-+	return _SUCCESS;
-+}
-+
-+/*
-+ * General use
-+ */
-+s32 SetPowerTracking(PADAPTER padapter, u8 enable)
-+{
-+
-+	hal_mpt_SetPowerTracking(padapter, enable);
-+	return 0;
-+}
-+
-+void GetPowerTracking(PADAPTER padapter, u8 *enable)
-+{
-+	hal_mpt_GetPowerTracking(padapter, enable);
-+}
-+
-+void rtw_mp_trigger_iqk(PADAPTER padapter)
-+{
-+	PHY_IQCalibrate(padapter, _FALSE);
-+}
-+
-+void rtw_mp_trigger_lck(PADAPTER padapter)
-+{
-+	PHY_LCCalibrate(padapter);
-+}
-+
-+void rtw_mp_trigger_dpk(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
-+
-+	halrf_dpk_trigger(pDM_Odm);
-+}
-+
-+static void init_mp_data(PADAPTER padapter)
-+{
-+	u8 v8;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
-+
-+	/*disable BCN*/
-+#ifdef CONFIG_PROTSEL_PORT
-+	rtw_hal_hw_port_disable(padapter);
-+#else
-+	v8 = rtw_read8(padapter, REG_BCN_CTRL);
-+	v8 &= ~EN_BCN_FUNCTION;
-+	rtw_write8(padapter, REG_BCN_CTRL, v8);
-+#endif
-+
-+	pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
-+}
-+
-+
-+void MPT_PwrCtlDM(PADAPTER padapter, u32 trk_type)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
-+	u32	rf_ability;
-+
-+	padapter->mppriv.tssitrk_on = trk_type == 3;
-+
-+	if (trk_type == 0) { /* thermal PwrTrk off*/
-+		struct txpwrtrack_cfg c;
-+		u8	chnl = 0 ;
-+
-+		RTW_INFO("in Thermal tracking off\n");
-+		rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) & ~HAL_RF_TX_PWR_TRACK;
-+		halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
-+		halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_POWER_TRACK_CONTROL, trk_type);
-+		halrf_set_pwr_track(pDM_Odm, FALSE);
-+		pDM_Odm->rf_calibrate_info.txpowertrack_control = trk_type;
-+		if (IS_HARDWARE_TYPE_8822C(padapter))
-+			padapter->mppriv.mp_dm = 1; /* default enable dpk tracking */
-+		else
-+			padapter->mppriv.mp_dm = 0;
-+
-+		_rtw_memset(&c, 0, sizeof(struct txpwrtrack_cfg));
-+		configure_txpower_track(pDM_Odm, &c);
-+		odm_clear_txpowertracking_state(pDM_Odm);
-+		if (*c.odm_tx_pwr_track_set_pwr) {
-+			if (pDM_Odm->support_ic_type == ODM_RTL8188F)
-+				(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
-+			else if (pDM_Odm->support_ic_type == ODM_RTL8723D) {
-+				(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
-+				SetTxPower(padapter);
-+			} else if (pDM_Odm->support_ic_type == ODM_RTL8192F) {
-+				(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
-+				(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_B, chnl);
-+			} else {
-+				(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
-+				(*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_B, chnl);
-+			}
-+		}
-+		return ;
-+	}
-+
-+	rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) | HAL_RF_TX_PWR_TRACK;
-+	halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
-+	halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_POWER_TRACK_CONTROL, trk_type);
-+	if (trk_type == 1 || trk_type == 3) /* Thermal PwrTrk ON , TSSI PwrTrk ON */
-+		halrf_set_pwr_track(pDM_Odm, TRUE);
-+	else
-+		halrf_set_pwr_track(pDM_Odm, false);/* TSSI K */
-+	pDM_Odm->rf_calibrate_info.txpowertrack_control = trk_type;
-+	padapter->mppriv.mp_dm = 1;
-+
-+}
-+
-+
-+u32 mp_join(PADAPTER padapter, u8 mode)
-+{
-+	WLAN_BSSID_EX bssid;
-+	struct sta_info *psta;
-+	u32 length;
-+	_irqL irqL;
-+	s32 res = _SUCCESS;
-+
-+	struct mp_priv *pmppriv = &padapter->mppriv;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct wlan_network *tgt_network = &pmlmepriv->cur_network;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
-+
-+	/* 1. initialize a new WLAN_BSSID_EX */
-+	_rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX));
-+	RTW_INFO("%s ,pmppriv->network_macaddr=%x %x %x %x %x %x\n", __func__,
-+		pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
-+		 pmppriv->network_macaddr[5]);
-+	_rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN);
-+
-+	if (mode == WIFI_FW_ADHOC_STATE) {
-+		bssid.Ssid.SsidLength = strlen("mp_pseudo_adhoc");
-+		_rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_adhoc", bssid.Ssid.SsidLength);
-+		bssid.InfrastructureMode = Ndis802_11IBSS;
-+		bssid.IELength = 0;
-+		bssid.Configuration.DSConfig = pmppriv->channel;
-+
-+	} else if (mode == WIFI_FW_STATION_STATE) {
-+		bssid.Ssid.SsidLength = strlen("mp_pseudo_STATION");
-+		_rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_STATION", bssid.Ssid.SsidLength);
-+		bssid.InfrastructureMode = Ndis802_11Infrastructure;
-+		bssid.IELength = 0;
-+	}
-+
-+	length = get_WLAN_BSSID_EX_sz(&bssid);
-+	if (length % 4)
-+		bssid.Length = ((length >> 2) + 1) << 2; /* round up to multiple of 4 bytes. */
-+	else
-+		bssid.Length = length;
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
-+		goto end_of_mp_start_test;
-+
-+	/* init mp_start_test status */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+		rtw_disassoc_cmd(padapter, 500, 0);
-+		rtw_indicate_disconnect(padapter, 0, _FALSE);
-+		rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
-+	}
-+	pmppriv->prev_fw_state = get_fwstate(pmlmepriv);
-+	/*pmlmepriv->fw_state = WIFI_MP_STATE;*/
-+	init_fwstate(pmlmepriv, WIFI_MP_STATE);
-+
-+	set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
-+
-+	/* 3 2. create a new psta for mp driver */
-+	/* clear psta in the cur_network, if any */
-+	psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
-+	if (psta)
-+		rtw_free_stainfo(padapter, psta);
-+
-+	psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress);
-+	if (psta == NULL) {
-+		/*pmlmepriv->fw_state = pmppriv->prev_fw_state;*/
-+		init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
-+		res = _FAIL;
-+		goto end_of_mp_start_test;
-+	}
-+	if (mode == WIFI_FW_ADHOC_STATE)
-+	set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
-+	else
-+		set_fwstate(pmlmepriv, WIFI_STATION_STATE);
-+	/* 3 3. join psudo AdHoc */
-+	tgt_network->join_res = 1;
-+	tgt_network->aid = psta->cmn.aid = 1;
-+
-+	_rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length);
-+	rtw_update_registrypriv_dev_network(padapter);
-+	_rtw_memcpy(&tgt_network->network, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
-+	_rtw_memcpy(pnetwork, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
-+
-+	rtw_indicate_connect(padapter);
-+	_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
-+	set_fwstate(pmlmepriv, WIFI_ASOC_STATE);
-+
-+end_of_mp_start_test:
-+
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+	if (1) { /* (res == _SUCCESS) */
-+		/* set MSR to WIFI_FW_ADHOC_STATE */
-+		if (mode == WIFI_FW_ADHOC_STATE) {
-+			/* set msr to WIFI_FW_ADHOC_STATE */
-+			pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
-+			Set_MSR(padapter, (pmlmeinfo->state & 0x3));
-+			rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);
-+			rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
-+			pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
-+		} else {
-+			Set_MSR(padapter, WIFI_FW_STATION_STATE);
-+
-+			RTW_INFO("%s , pmppriv->network_macaddr =%x %x %x %x %x %x\n", __func__,
-+				pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
-+				 pmppriv->network_macaddr[5]);
-+
-+			rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmppriv->network_macaddr);
-+		}
-+	}
-+
-+	return res;
-+}
-+/* This function initializes the DUT to the MP test mode */
-+s32 mp_start_test(PADAPTER padapter)
-+{
-+	struct mp_priv *pmppriv = &padapter->mppriv;
-+#ifdef CONFIG_PCI_HCI
-+	PHAL_DATA_TYPE hal;
-+#endif
-+	s32 res = _SUCCESS;
-+
-+	padapter->registrypriv.mp_mode = 1;
-+
-+	init_mp_data(padapter);
-+#ifdef CONFIG_RTL8814A
-+	rtl8814_InitHalDm(padapter);
-+#endif /* CONFIG_RTL8814A */
-+#ifdef CONFIG_RTL8812A
-+	rtl8812_InitHalDm(padapter);
-+#endif /* CONFIG_RTL8812A */
-+#ifdef CONFIG_RTL8723B
-+	rtl8723b_InitHalDm(padapter);
-+#endif /* CONFIG_RTL8723B */
-+#ifdef CONFIG_RTL8703B
-+	rtl8703b_InitHalDm(padapter);
-+#endif /* CONFIG_RTL8703B */
-+#ifdef CONFIG_RTL8192E
-+	rtl8192e_InitHalDm(padapter);
-+#endif
-+#ifdef CONFIG_RTL8188F
-+	rtl8188f_InitHalDm(padapter);
-+#endif
-+#ifdef CONFIG_RTL8188GTV
-+	rtl8188gtv_InitHalDm(padapter);
-+#endif
-+#ifdef CONFIG_RTL8188E
-+	rtl8188e_InitHalDm(padapter);
-+#endif
-+#ifdef CONFIG_RTL8723D
-+	rtl8723d_InitHalDm(padapter);
-+#endif /* CONFIG_RTL8723D */
-+
-+#ifdef CONFIG_PCI_HCI
-+	hal = GET_HAL_DATA(padapter);
-+	hal->pci_backdoor_ctrl = 0;
-+	rtw_pci_aspm_config(padapter);
-+#endif
-+
-+
-+	/* 3 0. update mp_priv */
-+	switch (GET_HAL_RFPATH(padapter)) {
-+		case RF_1T1R:
-+			pmppriv->antenna_tx = ANTENNA_A;
-+			pmppriv->antenna_rx = ANTENNA_A;
-+			break;
-+		case RF_1T2R:
-+		default:
-+			pmppriv->antenna_tx = ANTENNA_A;
-+			pmppriv->antenna_rx = ANTENNA_AB;
-+			break;
-+		case RF_2T2R:
-+			pmppriv->antenna_tx = ANTENNA_AB;
-+			pmppriv->antenna_rx = ANTENNA_AB;
-+			break;
-+		case RF_2T4R:
-+			pmppriv->antenna_tx = ANTENNA_AB;
-+			pmppriv->antenna_rx = ANTENNA_ABCD;
-+			break;
-+	}
-+
-+	mpt_ProStartTest(padapter);
-+
-+	mp_join(padapter, WIFI_FW_ADHOC_STATE);
-+
-+	return res;
-+}
-+/* ------------------------------------------------------------------------------
-+ * This function change the DUT from the MP test mode into normal mode */
-+void mp_stop_test(PADAPTER padapter)
-+{
-+	struct mp_priv *pmppriv = &padapter->mppriv;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct wlan_network *tgt_network = &pmlmepriv->cur_network;
-+	struct sta_info *psta;
-+#ifdef CONFIG_PCI_HCI
-+	struct registry_priv  *registry_par = &padapter->registrypriv;
-+	PHAL_DATA_TYPE hal;
-+#endif
-+
-+	_irqL irqL;
-+
-+	if (pmppriv->mode == MP_ON) {
-+		pmppriv->bSetTxPower = 0;
-+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+		if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)
-+			goto end_of_mp_stop_test;
-+
-+		/* 3 1. disconnect psudo AdHoc */
-+		rtw_indicate_disconnect(padapter, 0, _FALSE);
-+
-+		/* 3 2. clear psta used in mp test mode.
-+		*	rtw_free_assoc_resources(padapter, _TRUE); */
-+		psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
-+		if (psta)
-+			rtw_free_stainfo(padapter, psta);
-+
-+		/* 3 3. return to normal state (default:station mode) */
-+		/*pmlmepriv->fw_state = pmppriv->prev_fw_state; */ /* WIFI_STATION_STATE;*/
-+		init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
-+
-+		/* flush the cur_network */
-+		_rtw_memset(tgt_network, 0, sizeof(struct wlan_network));
-+
-+		_clr_fwstate_(pmlmepriv, WIFI_MP_STATE);
-+
-+end_of_mp_stop_test:
-+
-+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+#ifdef CONFIG_PCI_HCI
-+		hal = GET_HAL_DATA(padapter);
-+		hal->pci_backdoor_ctrl = registry_par->pci_aspm_config;
-+		rtw_pci_aspm_config(padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+		rtl8812_InitHalDm(padapter);
-+#endif
-+#ifdef CONFIG_RTL8723B
-+		rtl8723b_InitHalDm(padapter);
-+#endif
-+#ifdef CONFIG_RTL8703B
-+		rtl8703b_InitHalDm(padapter);
-+#endif
-+#ifdef CONFIG_RTL8192E
-+		rtl8192e_InitHalDm(padapter);
-+#endif
-+#ifdef CONFIG_RTL8188F
-+		rtl8188f_InitHalDm(padapter);
-+#endif
-+#ifdef CONFIG_RTL8188GTV
-+		rtl8188gtv_InitHalDm(padapter);
-+#endif
-+#ifdef CONFIG_RTL8723D
-+		rtl8723d_InitHalDm(padapter);
-+#endif
-+	}
-+}
-+/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
-+#if 0
-+/* #ifdef CONFIG_USB_HCI */
-+static void mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID)
-+{
-+	u8		eRFPath;
-+	u32		rfReg0x26;
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
-+
-+
-+	if (RateIdx < MPT_RATE_6M) 	/* CCK rate,for 88cu */
-+		rfReg0x26 = 0xf400;
-+	else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {/* OFDM rate,for 88cu */
-+		if ((4 == Channel) || (8 == Channel) || (12 == Channel))
-+			rfReg0x26 = 0xf000;
-+		else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
-+			rfReg0x26 = 0xf400;
-+		else
-+			rfReg0x26 = 0x4f200;
-+	} else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {
-+		/* MCS 20M ,for 88cu */ /* MCS40M rate,for 88cu */
-+
-+		if (CHANNEL_WIDTH_20 == BandWidthID) {
-+			if ((4 == Channel) || (8 == Channel))
-+				rfReg0x26 = 0xf000;
-+			else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
-+				rfReg0x26 = 0xf400;
-+			else
-+				rfReg0x26 = 0x4f200;
-+		} else {
-+			if ((4 == Channel) || (8 == Channel))
-+				rfReg0x26 = 0xf000;
-+			else if ((5 == Channel) || (7 == Channel))
-+				rfReg0x26 = 0xf400;
-+			else
-+				rfReg0x26 = 0x4f200;
-+		}
-+	}
-+
-+	for (eRFPath = 0; eRFPath < hal_spec->rf_reg_path_num; eRFPath++)
-+		write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26);
-+}
-+#endif
-+/*-----------------------------------------------------------------------------
-+ * Function:	mpt_SwitchRfSetting
-+ *
-+ * Overview:	Change RF Setting when we siwthc channel/rate/BW for MP.
-+ *
-+ * Input:       	PADAPTER				pAdapter
-+ *
-+ * Output:      NONE
-+ *
-+ * Return:      NONE
-+ *
-+ * Revised History:
-+ * When			Who		Remark
-+ * 01/08/2009	MHC		Suggestion from SD3 Willis for 92S series.
-+ * 01/09/2009	MHC		Add CCK modification for 40MHZ. Suggestion from SD3.
-+ *
-+ *---------------------------------------------------------------------------*/
-+#if 0
-+static void mpt_SwitchRfSetting(PADAPTER pAdapter)
-+{
-+	hal_mpt_SwitchRfSetting(pAdapter);
-+}
-+
-+/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
-+/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
-+static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
-+{
-+	hal_mpt_CCKTxPowerAdjust(Adapter, bInCH14);
-+}
-+#endif
-+
-+/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
-+
-+/*
-+ * SetChannel
-+ * Description
-+ *	Use H2C command to change channel,
-+ *	not only modify rf register, but also other setting need to be done.
-+ */
-+void SetChannel(PADAPTER pAdapter)
-+{
-+	hal_mpt_SetChannel(pAdapter);
-+}
-+
-+/*
-+ * Notice
-+ *	Switch bandwitdth may change center frequency(channel)
-+ */
-+void SetBandwidth(PADAPTER pAdapter)
-+{
-+	hal_mpt_SetBandwidth(pAdapter);
-+
-+}
-+
-+void SetAntenna(PADAPTER pAdapter)
-+{
-+	hal_mpt_SetAntenna(pAdapter);
-+}
-+
-+int SetTxPower(PADAPTER pAdapter)
-+{
-+
-+	hal_mpt_SetTxPower(pAdapter);
-+	return _TRUE;
-+}
-+
-+void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
-+{
-+	u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
-+
-+	TxAGCOffset_B = (ulTxAGCOffset & 0x000000ff);
-+	TxAGCOffset_C = ((ulTxAGCOffset & 0x0000ff00) >> 8);
-+	TxAGCOffset_D = ((ulTxAGCOffset & 0x00ff0000) >> 16);
-+
-+	tmpAGC = (TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B);
-+	write_bbreg(pAdapter, rFPGA0_TxGainStage,
-+		    (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);
-+}
-+
-+void SetDataRate(PADAPTER pAdapter)
-+{
-+	hal_mpt_SetDataRate(pAdapter);
-+}
-+
-+void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain)
-+{
-+
-+	PHY_SetRFPathSwitch(pAdapter, bMain);
-+
-+}
-+
-+void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate)
-+{
-+
-+	phy_switch_rf_path_set(pAdapter, pstate);
-+
-+}
-+
-+u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter)
-+{
-+	return PHY_QueryRFPathSwitch(pAdapter);
-+}
-+
-+s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
-+{
-+	return hal_mpt_SetThermalMeter(pAdapter, target_ther);
-+}
-+
-+#if 0
-+static void TriggerRFThermalMeter(PADAPTER pAdapter)
-+{
-+	hal_mpt_TriggerRFThermalMeter(pAdapter);
-+}
-+
-+static u8 ReadRFThermalMeter(PADAPTER pAdapter)
-+{
-+	return hal_mpt_ReadRFThermalMeter(pAdapter);
-+}
-+#endif
-+
-+void GetThermalMeter(PADAPTER pAdapter, u8 rfpath ,u8 *value)
-+{
-+	hal_mpt_GetThermalMeter(pAdapter, rfpath, value);
-+}
-+
-+void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
-+{
-+	PhySetTxPowerLevel(pAdapter);
-+	hal_mpt_SetSingleCarrierTx(pAdapter, bStart);
-+}
-+
-+void SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
-+{
-+	PhySetTxPowerLevel(pAdapter);
-+	hal_mpt_SetSingleToneTx(pAdapter, bStart);
-+}
-+
-+void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
-+{
-+	PhySetTxPowerLevel(pAdapter);
-+	hal_mpt_SetCarrierSuppressionTx(pAdapter, bStart);
-+}
-+
-+void SetContinuousTx(PADAPTER pAdapter, u8 bStart)
-+{
-+	PhySetTxPowerLevel(pAdapter);
-+	hal_mpt_SetContinuousTx(pAdapter, bStart);
-+}
-+
-+
-+void PhySetTxPowerLevel(PADAPTER pAdapter)
-+{
-+	struct mp_priv *pmp_priv = &pAdapter->mppriv;
-+
-+
-+	if (pmp_priv->bSetTxPower == 0) /* for NO manually set power index */
-+		rtw_hal_set_tx_power_level(pAdapter, pmp_priv->channel);
-+}
-+
-+/* ------------------------------------------------------------------------------ */
-+static void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe)
-+{
-+	rtw_hal_mgnt_xmit(padapter, pmpframe);
-+}
-+
-+static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv)
-+{
-+	struct xmit_frame	*pmpframe;
-+	struct xmit_buf	*pxmitbuf;
-+
-+	pmpframe = rtw_alloc_xmitframe(pxmitpriv, 0);
-+	if (pmpframe == NULL)
-+		return NULL;
-+
-+	pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
-+	if (pxmitbuf == NULL) {
-+		rtw_free_xmitframe(pxmitpriv, pmpframe);
-+		return NULL;
-+	}
-+
-+	pmpframe->frame_tag = MP_FRAMETAG;
-+
-+	pmpframe->pxmitbuf = pxmitbuf;
-+
-+	pmpframe->buf_addr = pxmitbuf->pbuf;
-+
-+	pxmitbuf->priv_data = pmpframe;
-+
-+	return pmpframe;
-+
-+}
-+
-+#ifdef CONFIG_PCI_HCI
-+static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib)
-+{
-+	u32 prio;
-+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
-+	struct rtw_tx_ring	*ring;
-+
-+	switch (pattrib->qsel) {
-+	case 0:
-+	case 3:
-+		prio = BE_QUEUE_INX;
-+		break;
-+	case 1:
-+	case 2:
-+		prio = BK_QUEUE_INX;
-+		break;
-+	case 4:
-+	case 5:
-+		prio = VI_QUEUE_INX;
-+		break;
-+	case 6:
-+	case 7:
-+		prio = VO_QUEUE_INX;
-+		break;
-+	default:
-+		prio = BE_QUEUE_INX;
-+		break;
-+	}
-+
-+	ring = &pxmitpriv->tx_ring[prio];
-+
-+	/*
-+	 * for now we reserve two free descriptor as a safety boundary
-+	 * between the tail and the head
-+	 */
-+	if ((ring->entries - ring->qlen) >= 2)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+#endif
-+
-+static thread_return mp_xmit_packet_thread(thread_context context)
-+{
-+	struct xmit_frame	*pxmitframe;
-+	struct mp_tx		*pmptx;
-+	struct mp_priv	*pmp_priv;
-+	struct xmit_priv	*pxmitpriv;
-+	PADAPTER padapter;
-+
-+	pmp_priv = (struct mp_priv *)context;
-+	pmptx = &pmp_priv->tx;
-+	padapter = pmp_priv->papdater;
-+	pxmitpriv = &(padapter->xmitpriv);
-+
-+	thread_enter("RTW_MP_THREAD");
-+
-+	RTW_INFO("%s:pkTx Start\n", __func__);
-+	while (1) {
-+		pxmitframe = alloc_mp_xmitframe(pxmitpriv);
-+#ifdef CONFIG_PCI_HCI
-+		if(check_nic_enough_desc(padapter, &pmptx->attrib) == _FALSE) {
-+			rtw_usleep_os(1000);
-+			continue;
-+		}
-+#endif
-+		if (pxmitframe == NULL) {
-+			if (pmptx->stop ||
-+			    RTW_CANNOT_RUN(padapter))
-+				goto exit;
-+			else {
-+				rtw_usleep_os(10);
-+				continue;
-+			}
-+		}
-+		_rtw_memcpy((u8 *)(pxmitframe->buf_addr + TXDESC_OFFSET), pmptx->buf, pmptx->write_size);
-+		_rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib));
-+
-+
-+		rtw_usleep_os(padapter->mppriv.pktInterval);
-+		dump_mpframe(padapter, pxmitframe);
-+
-+		pmptx->sended++;
-+		pmp_priv->tx_pktcount++;
-+
-+		if (pmptx->stop ||
-+		    RTW_CANNOT_RUN(padapter))
-+			goto exit;
-+		if ((pmptx->count != 0) &&
-+		    (pmptx->count == pmptx->sended))
-+			goto exit;
-+
-+		flush_signals_thread();
-+	}
-+
-+exit:
-+	/* RTW_INFO("%s:pkTx Exit\n", __func__); */
-+	rtw_mfree(pmptx->pallocated_buf, pmptx->buf_size);
-+	pmptx->pallocated_buf = NULL;
-+	pmptx->stop = 1;
-+
-+	thread_exit(NULL);
-+	return 0;
-+}
-+
-+void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc)
-+{
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	_rtw_memcpy(ptxdesc, pmp_priv->tx.desc, TXDESC_SIZE);
-+}
-+
-+#if defined(CONFIG_RTL8188E)
-+void fill_tx_desc_8188e(PADAPTER padapter)
-+{
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	struct tx_desc *desc   = (struct tx_desc *)&(pmp_priv->tx.desc);
-+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
-+	u32	pkt_size = pattrib->last_txcmdsz;
-+	s32 bmcast = IS_MCAST(pattrib->ra);
-+	/* offset 0 */
-+#if !defined(CONFIG_RTL8188E_SDIO) && !defined(CONFIG_PCI_HCI)
-+	desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
-+	desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); /* packet size */
-+	desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); /* 32 bytes for TX Desc */
-+	if (bmcast)
-+		desc->txdw0 |= cpu_to_le32(BMC); /* broadcast packet */
-+
-+	desc->txdw1 |= cpu_to_le32((0x01 << 26) & 0xff000000);
-+#endif
-+
-+	desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x3F); /* CAM_ID(MAC_ID) */
-+	desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); /* Queue Select, TID */
-+	desc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); /* Rate Adaptive ID */
-+	/* offset 8 */
-+	/* desc->txdw2 |= cpu_to_le32(AGG_BK); */ /* AGG BK */
-+
-+	desc->txdw3 |= cpu_to_le32((pattrib->seqnum << 16) & 0x0fff0000);
-+	desc->txdw4 |= cpu_to_le32(HW_SSN);
-+
-+	desc->txdw4 |= cpu_to_le32(USERATE);
-+	desc->txdw4 |= cpu_to_le32(DISDATAFB);
-+
-+	if (pmp_priv->preamble) {
-+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
-+			desc->txdw4 |= cpu_to_le32(DATA_SHORT); /* CCK Short Preamble */
-+	}
-+
-+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
-+		desc->txdw4 |= cpu_to_le32(DATA_BW);
-+
-+	/* offset 20 */
-+	desc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F);
-+
-+	if (pmp_priv->preamble) {
-+		if (HwRateToMPTRate(pmp_priv->rateidx) > MPT_RATE_54M)
-+			desc->txdw5 |= cpu_to_le32(SGI); /* MCS Short Guard Interval */
-+	}
-+
-+	desc->txdw5 |= cpu_to_le32(RTY_LMT_EN); /* retry limit enable */
-+	desc->txdw5 |= cpu_to_le32(0x00180000); /* DATA/RTS Rate Fallback Limit	 */
-+
-+
-+}
-+#endif
-+
-+#if defined(CONFIG_RTL8814A)
-+void fill_tx_desc_8814a(PADAPTER padapter)
-+{
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	u8 *pDesc   = (u8 *)&(pmp_priv->tx.desc);
-+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
-+
-+	u32	pkt_size = pattrib->last_txcmdsz;
-+	s32 bmcast = IS_MCAST(pattrib->ra);
-+	u8 offset;
-+
-+	/* SET_TX_DESC_FIRST_SEG_8814A(pDesc, 1); */
-+	SET_TX_DESC_LAST_SEG_8814A(pDesc, 1);
-+	/* SET_TX_DESC_OWN_(pDesc, 1); */
-+
-+	SET_TX_DESC_PKT_SIZE_8814A(pDesc, pkt_size);
-+
-+	offset = TXDESC_SIZE + OFFSET_SZ;
-+
-+	SET_TX_DESC_OFFSET_8814A(pDesc, offset);
-+#if defined(CONFIG_PCI_HCI)
-+	SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 0); /* 8814AE pkt_offset is 0 */
-+#else
-+	SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 1);
-+#endif
-+
-+	if (bmcast)
-+		SET_TX_DESC_BMC_8814A(pDesc, 1);
-+
-+	SET_TX_DESC_MACID_8814A(pDesc, pattrib->mac_id);
-+	SET_TX_DESC_RATE_ID_8814A(pDesc, pattrib->raid);
-+
-+	/* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
-+	SET_TX_DESC_QUEUE_SEL_8814A(pDesc,  pattrib->qsel);
-+	/* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */
-+
-+	if (pmp_priv->preamble)
-+		SET_TX_DESC_DATA_SHORT_8814A(pDesc, 1);
-+
-+	if (!pattrib->qos_en) {
-+		SET_TX_DESC_HWSEQ_EN_8814A(pDesc, 1); /* Hw set sequence number */
-+	} else
-+		SET_TX_DESC_SEQ_8814A(pDesc, pattrib->seqnum);
-+
-+	if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
-+		SET_TX_DESC_DATA_BW_8814A(pDesc, pmp_priv->bandwidth);
-+	else {
-+		RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
-+		SET_TX_DESC_DATA_BW_8814A(pDesc, CHANNEL_WIDTH_20);
-+	}
-+
-+	SET_TX_DESC_DISABLE_FB_8814A(pDesc, 1);
-+	SET_TX_DESC_USE_RATE_8814A(pDesc, 1);
-+	SET_TX_DESC_TX_RATE_8814A(pDesc, pmp_priv->rateidx);
-+
-+}
-+#endif
-+
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+void fill_tx_desc_8812a(PADAPTER padapter)
-+{
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	u8 *pDesc   = (u8 *)&(pmp_priv->tx.desc);
-+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
-+
-+	u32	pkt_size = pattrib->last_txcmdsz;
-+	s32 bmcast = IS_MCAST(pattrib->ra);
-+	u8 data_rate, pwr_status, offset;
-+
-+	SET_TX_DESC_FIRST_SEG_8812(pDesc, 1);
-+	SET_TX_DESC_LAST_SEG_8812(pDesc, 1);
-+	SET_TX_DESC_OWN_8812(pDesc, 1);
-+
-+	SET_TX_DESC_PKT_SIZE_8812(pDesc, pkt_size);
-+
-+	offset = TXDESC_SIZE + OFFSET_SZ;
-+
-+	SET_TX_DESC_OFFSET_8812(pDesc, offset);
-+
-+#if defined(CONFIG_PCI_HCI)
-+	SET_TX_DESC_PKT_OFFSET_8812(pDesc, 0);
-+#else
-+	SET_TX_DESC_PKT_OFFSET_8812(pDesc, 1);
-+#endif
-+	if (bmcast)
-+		SET_TX_DESC_BMC_8812(pDesc, 1);
-+
-+	SET_TX_DESC_MACID_8812(pDesc, pattrib->mac_id);
-+	SET_TX_DESC_RATE_ID_8812(pDesc, pattrib->raid);
-+
-+	/* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
-+	SET_TX_DESC_QUEUE_SEL_8812(pDesc,  pattrib->qsel);
-+	/* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */
-+
-+	if (!pattrib->qos_en) {
-+		SET_TX_DESC_HWSEQ_EN_8812(pDesc, 1); /* Hw set sequence number */
-+	} else
-+		SET_TX_DESC_SEQ_8812(pDesc, pattrib->seqnum);
-+
-+	if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
-+		SET_TX_DESC_DATA_BW_8812(pDesc, pmp_priv->bandwidth);
-+	else {
-+		RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
-+		SET_TX_DESC_DATA_BW_8812(pDesc, CHANNEL_WIDTH_20);
-+	}
-+
-+	SET_TX_DESC_DISABLE_FB_8812(pDesc, 1);
-+	SET_TX_DESC_USE_RATE_8812(pDesc, 1);
-+	SET_TX_DESC_TX_RATE_8812(pDesc, pmp_priv->rateidx);
-+
-+}
-+#endif
-+#if defined(CONFIG_RTL8192E)
-+void fill_tx_desc_8192e(PADAPTER padapter)
-+{
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	u8 *pDesc	= (u8 *)&(pmp_priv->tx.desc);
-+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
-+
-+	u32 pkt_size = pattrib->last_txcmdsz;
-+	s32 bmcast = IS_MCAST(pattrib->ra);
-+	u8 data_rate, pwr_status, offset;
-+
-+
-+	SET_TX_DESC_PKT_SIZE_92E(pDesc, pkt_size);
-+
-+	offset = TXDESC_SIZE + OFFSET_SZ;
-+
-+	SET_TX_DESC_OFFSET_92E(pDesc, offset);
-+#if defined(CONFIG_PCI_HCI) /* 8192EE */
-+
-+	SET_TX_DESC_PKT_OFFSET_92E(pDesc, 0); /* 8192EE pkt_offset is 0 */
-+#else /* 8192EU 8192ES */
-+	SET_TX_DESC_PKT_OFFSET_92E(pDesc, 1);
-+#endif
-+
-+	if (bmcast)
-+		SET_TX_DESC_BMC_92E(pDesc, 1);
-+
-+	SET_TX_DESC_MACID_92E(pDesc, pattrib->mac_id);
-+	SET_TX_DESC_RATE_ID_92E(pDesc, pattrib->raid);
-+
-+
-+	SET_TX_DESC_QUEUE_SEL_92E(pDesc,  pattrib->qsel);
-+	/* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */
-+
-+	if (!pattrib->qos_en) {
-+		SET_TX_DESC_EN_HWSEQ_92E(pDesc, 1);/* Hw set sequence number */
-+		SET_TX_DESC_HWSEQ_SEL_92E(pDesc, pattrib->hw_ssn_sel);
-+	} else
-+		SET_TX_DESC_SEQ_92E(pDesc, pattrib->seqnum);
-+
-+	if ((pmp_priv->bandwidth == CHANNEL_WIDTH_20) || (pmp_priv->bandwidth == CHANNEL_WIDTH_40))
-+		SET_TX_DESC_DATA_BW_92E(pDesc, pmp_priv->bandwidth);
-+	else {
-+		RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
-+		SET_TX_DESC_DATA_BW_92E(pDesc, CHANNEL_WIDTH_20);
-+	}
-+
-+	/* SET_TX_DESC_DATA_SC_92E(pDesc, SCMapping_92E(padapter,pattrib)); */
-+
-+	SET_TX_DESC_DISABLE_FB_92E(pDesc, 1);
-+	SET_TX_DESC_USE_RATE_92E(pDesc, 1);
-+	SET_TX_DESC_TX_RATE_92E(pDesc, pmp_priv->rateidx);
-+
-+}
-+#endif
-+
-+#if defined(CONFIG_RTL8723B)
-+void fill_tx_desc_8723b(PADAPTER padapter)
-+{
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
-+	u8 *ptxdesc = pmp_priv->tx.desc;
-+
-+	SET_TX_DESC_AGG_BREAK_8723B(ptxdesc, 1);
-+	SET_TX_DESC_MACID_8723B(ptxdesc, pattrib->mac_id);
-+	SET_TX_DESC_QUEUE_SEL_8723B(ptxdesc, pattrib->qsel);
-+
-+	SET_TX_DESC_RATE_ID_8723B(ptxdesc, pattrib->raid);
-+	SET_TX_DESC_SEQ_8723B(ptxdesc, pattrib->seqnum);
-+	SET_TX_DESC_HWSEQ_EN_8723B(ptxdesc, 1);
-+	SET_TX_DESC_USE_RATE_8723B(ptxdesc, 1);
-+	SET_TX_DESC_DISABLE_FB_8723B(ptxdesc, 1);
-+
-+	if (pmp_priv->preamble) {
-+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
-+			SET_TX_DESC_DATA_SHORT_8723B(ptxdesc, 1);
-+	}
-+
-+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
-+		SET_TX_DESC_DATA_BW_8723B(ptxdesc, 1);
-+
-+	SET_TX_DESC_TX_RATE_8723B(ptxdesc, pmp_priv->rateidx);
-+
-+	SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(ptxdesc, 0x1F);
-+	SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(ptxdesc, 0xF);
-+}
-+#endif
-+
-+#if defined(CONFIG_RTL8703B)
-+void fill_tx_desc_8703b(PADAPTER padapter)
-+{
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
-+	u8 *ptxdesc = pmp_priv->tx.desc;
-+
-+	SET_TX_DESC_AGG_BREAK_8703B(ptxdesc, 1);
-+	SET_TX_DESC_MACID_8703B(ptxdesc, pattrib->mac_id);
-+	SET_TX_DESC_QUEUE_SEL_8703B(ptxdesc, pattrib->qsel);
-+
-+	SET_TX_DESC_RATE_ID_8703B(ptxdesc, pattrib->raid);
-+	SET_TX_DESC_SEQ_8703B(ptxdesc, pattrib->seqnum);
-+	SET_TX_DESC_HWSEQ_EN_8703B(ptxdesc, 1);
-+	SET_TX_DESC_USE_RATE_8703B(ptxdesc, 1);
-+	SET_TX_DESC_DISABLE_FB_8703B(ptxdesc, 1);
-+
-+	if (pmp_priv->preamble) {
-+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
-+			SET_TX_DESC_DATA_SHORT_8703B(ptxdesc, 1);
-+	}
-+
-+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
-+		SET_TX_DESC_DATA_BW_8703B(ptxdesc, 1);
-+
-+	SET_TX_DESC_TX_RATE_8703B(ptxdesc, pmp_priv->rateidx);
-+
-+	SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(ptxdesc, 0x1F);
-+	SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(ptxdesc, 0xF);
-+}
-+#endif
-+
-+#if defined(CONFIG_RTL8188F)
-+void fill_tx_desc_8188f(PADAPTER padapter)
-+{
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
-+	u8 *ptxdesc = pmp_priv->tx.desc;
-+
-+	SET_TX_DESC_AGG_BREAK_8188F(ptxdesc, 1);
-+	SET_TX_DESC_MACID_8188F(ptxdesc, pattrib->mac_id);
-+	SET_TX_DESC_QUEUE_SEL_8188F(ptxdesc, pattrib->qsel);
-+
-+	SET_TX_DESC_RATE_ID_8188F(ptxdesc, pattrib->raid);
-+	SET_TX_DESC_SEQ_8188F(ptxdesc, pattrib->seqnum);
-+	SET_TX_DESC_HWSEQ_EN_8188F(ptxdesc, 1);
-+	SET_TX_DESC_USE_RATE_8188F(ptxdesc, 1);
-+	SET_TX_DESC_DISABLE_FB_8188F(ptxdesc, 1);
-+
-+	if (pmp_priv->preamble)
-+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
-+			SET_TX_DESC_DATA_SHORT_8188F(ptxdesc, 1);
-+
-+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
-+		SET_TX_DESC_DATA_BW_8188F(ptxdesc, 1);
-+
-+	SET_TX_DESC_TX_RATE_8188F(ptxdesc, pmp_priv->rateidx);
-+
-+	SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(ptxdesc, 0x1F);
-+	SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(ptxdesc, 0xF);
-+}
-+#endif
-+
-+#if defined(CONFIG_RTL8188GTV)
-+void fill_tx_desc_8188gtv(PADAPTER padapter)
-+{
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
-+	u8 *ptxdesc = pmp_priv->tx.desc;
-+
-+	SET_TX_DESC_AGG_BREAK_8188GTV(ptxdesc, 1);
-+	SET_TX_DESC_MACID_8188GTV(ptxdesc, pattrib->mac_id);
-+	SET_TX_DESC_QUEUE_SEL_8188GTV(ptxdesc, pattrib->qsel);
-+
-+	SET_TX_DESC_RATE_ID_8188GTV(ptxdesc, pattrib->raid);
-+	SET_TX_DESC_SEQ_8188GTV(ptxdesc, pattrib->seqnum);
-+	SET_TX_DESC_HWSEQ_EN_8188GTV(ptxdesc, 1);
-+	SET_TX_DESC_USE_RATE_8188GTV(ptxdesc, 1);
-+	SET_TX_DESC_DISABLE_FB_8188GTV(ptxdesc, 1);
-+
-+	if (pmp_priv->preamble)
-+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
-+			SET_TX_DESC_DATA_SHORT_8188GTV(ptxdesc, 1);
-+
-+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
-+		SET_TX_DESC_DATA_BW_8188GTV(ptxdesc, 1);
-+
-+	SET_TX_DESC_TX_RATE_8188GTV(ptxdesc, pmp_priv->rateidx);
-+
-+	SET_TX_DESC_DATA_RATE_FB_LIMIT_8188GTV(ptxdesc, 0x1F);
-+	SET_TX_DESC_RTS_RATE_FB_LIMIT_8188GTV(ptxdesc, 0xF);
-+}
-+#endif
-+
-+#if defined(CONFIG_RTL8723D)
-+void fill_tx_desc_8723d(PADAPTER padapter)
-+{
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
-+	u8 *ptxdesc = pmp_priv->tx.desc;
-+
-+	SET_TX_DESC_BK_8723D(ptxdesc, 1);
-+	SET_TX_DESC_MACID_8723D(ptxdesc, pattrib->mac_id);
-+	SET_TX_DESC_QUEUE_SEL_8723D(ptxdesc, pattrib->qsel);
-+
-+	SET_TX_DESC_RATE_ID_8723D(ptxdesc, pattrib->raid);
-+	SET_TX_DESC_SEQ_8723D(ptxdesc, pattrib->seqnum);
-+	SET_TX_DESC_HWSEQ_EN_8723D(ptxdesc, 1);
-+	SET_TX_DESC_USE_RATE_8723D(ptxdesc, 1);
-+	SET_TX_DESC_DISABLE_FB_8723D(ptxdesc, 1);
-+
-+	if (pmp_priv->preamble) {
-+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
-+			SET_TX_DESC_DATA_SHORT_8723D(ptxdesc, 1);
-+	}
-+
-+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
-+		SET_TX_DESC_DATA_BW_8723D(ptxdesc, 1);
-+
-+	SET_TX_DESC_TX_RATE_8723D(ptxdesc, pmp_priv->rateidx);
-+
-+	SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(ptxdesc, 0x1F);
-+	SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(ptxdesc, 0xF);
-+}
-+#endif
-+
-+#if defined(CONFIG_RTL8710B)
-+void fill_tx_desc_8710b(PADAPTER padapter)
-+{
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
-+	u8 *ptxdesc = pmp_priv->tx.desc;
-+
-+	SET_TX_DESC_BK_8710B(ptxdesc, 1);
-+	SET_TX_DESC_MACID_8710B(ptxdesc, pattrib->mac_id);
-+	SET_TX_DESC_QUEUE_SEL_8710B(ptxdesc, pattrib->qsel);
-+
-+	SET_TX_DESC_RATE_ID_8710B(ptxdesc, pattrib->raid);
-+	SET_TX_DESC_SEQ_8710B(ptxdesc, pattrib->seqnum);
-+	SET_TX_DESC_HWSEQ_EN_8710B(ptxdesc, 1);
-+	SET_TX_DESC_USE_RATE_8710B(ptxdesc, 1);
-+	SET_TX_DESC_DISABLE_FB_8710B(ptxdesc, 1);
-+
-+	if (pmp_priv->preamble) {
-+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
-+			SET_TX_DESC_DATA_SHORT_8710B(ptxdesc, 1);
-+	}
-+
-+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
-+		SET_TX_DESC_DATA_BW_8710B(ptxdesc, 1);
-+
-+	SET_TX_DESC_TX_RATE_8710B(ptxdesc, pmp_priv->rateidx);
-+
-+	SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(ptxdesc, 0x1F);
-+	SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(ptxdesc, 0xF);
-+}
-+#endif
-+
-+#if defined(CONFIG_RTL8192F)
-+void fill_tx_desc_8192f(PADAPTER padapter)
-+{
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
-+	u8 *ptxdesc = pmp_priv->tx.desc;
-+
-+	SET_TX_DESC_BK_8192F(ptxdesc, 1);
-+	SET_TX_DESC_MACID_8192F(ptxdesc, pattrib->mac_id);
-+	SET_TX_DESC_QUEUE_SEL_8192F(ptxdesc, pattrib->qsel);
-+
-+	SET_TX_DESC_RATE_ID_8192F(ptxdesc, pattrib->raid);
-+	SET_TX_DESC_SEQ_8192F(ptxdesc, pattrib->seqnum);
-+	SET_TX_DESC_HWSEQ_EN_8192F(ptxdesc, 1);
-+	SET_TX_DESC_USE_RATE_8192F(ptxdesc, 1);
-+	SET_TX_DESC_DISABLE_FB_8192F(ptxdesc, 1);
-+
-+	if (pmp_priv->preamble) {
-+		if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
-+			SET_TX_DESC_DATA_SHORT_8192F(ptxdesc, 1);
-+	}
-+
-+	if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
-+		SET_TX_DESC_DATA_BW_8192F(ptxdesc, 1);
-+
-+	SET_TX_DESC_TX_RATE_8192F(ptxdesc, pmp_priv->rateidx);
-+
-+	SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(ptxdesc, 0x1F);
-+	SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(ptxdesc, 0xF);
-+}
-+
-+#endif
-+static void Rtw_MPSetMacTxEDCA(PADAPTER padapter)
-+{
-+
-+	rtw_write32(padapter, 0x508 , 0x00a422); /* Disable EDCA BE Txop for MP pkt tx adjust Packet interval */
-+	/* RTW_INFO("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508)); */
-+	phy_set_mac_reg(padapter, 0x458 , bMaskDWord , 0x0);
-+	/*RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));*/
-+	phy_set_mac_reg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out value*/
-+	/*phy_set_mac_reg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);*/
-+	/*phy_set_mac_reg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);*/
-+	/*phy_set_mac_reg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);*/
-+	RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));
-+
-+}
-+
-+void SetPacketTx(PADAPTER padapter)
-+{
-+	u8 *ptr, *pkt_start, *pkt_end;
-+	u32 pkt_size = 0, i = 0, idx = 0, tmp_idx = 0;
-+	struct rtw_ieee80211_hdr *hdr;
-+	u8 payload;
-+	s32 bmcast;
-+	struct pkt_attrib *pattrib;
-+	struct mp_priv *pmp_priv;
-+
-+	pmp_priv = &padapter->mppriv;
-+
-+	if (pmp_priv->tx.stop)
-+		return;
-+	pmp_priv->tx.sended = 0;
-+	pmp_priv->tx.stop = 0;
-+	pmp_priv->tx_pktcount = 0;
-+
-+	/* 3 1. update_attrib() */
-+	pattrib = &pmp_priv->tx.attrib;
-+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+	_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
-+	bmcast = IS_MCAST(pattrib->ra);
-+	if (bmcast)
-+		pattrib->psta = rtw_get_bcmc_stainfo(padapter);
-+	else
-+		pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
-+
-+	if (pattrib->psta == NULL) {
-+		RTW_INFO("%s:psta = NULL !!\n", __func__);
-+		return;
-+	}
-+
-+	pattrib->mac_id = pattrib->psta->cmn.mac_id;
-+	pattrib->mbssid = 0;
-+
-+	pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
-+
-+	/* 3 2. allocate xmit buffer */
-+	pkt_size = pattrib->last_txcmdsz;
-+
-+	if (pmp_priv->tx.pallocated_buf)
-+		rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size);
-+	pmp_priv->tx.write_size = pkt_size;
-+	pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ;
-+	pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size);
-+	if (pmp_priv->tx.pallocated_buf == NULL) {
-+		RTW_INFO("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size);
-+		return;
-+	}
-+	pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ);
-+	ptr = pmp_priv->tx.buf;
-+
-+	_rtw_memset(pmp_priv->tx.desc, 0, TXDESC_SIZE);
-+	pkt_start = ptr;
-+	pkt_end = pkt_start + pkt_size;
-+
-+	/* 3 3. init TX descriptor */
-+#if defined(CONFIG_RTL8188E)
-+	if (IS_HARDWARE_TYPE_8188E(padapter))
-+		fill_tx_desc_8188e(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8814A)
-+	if (IS_HARDWARE_TYPE_8814A(padapter))
-+		fill_tx_desc_8814a(padapter);
-+#endif /* defined(CONFIG_RTL8814A) */
-+
-+#if defined(CONFIG_RTL8822B)
-+	if (IS_HARDWARE_TYPE_8822B(padapter))
-+		rtl8822b_prepare_mp_txdesc(padapter, pmp_priv);
-+#endif /* CONFIG_RTL8822B */
-+
-+#if defined(CONFIG_RTL8822C)
-+	if (IS_HARDWARE_TYPE_8822C(padapter))
-+		rtl8822c_prepare_mp_txdesc(padapter, pmp_priv);
-+#endif /* CONFIG_RTL8822C */
-+
-+#if defined(CONFIG_RTL8821C)
-+	if (IS_HARDWARE_TYPE_8821C(padapter))
-+		rtl8821c_prepare_mp_txdesc(padapter, pmp_priv);
-+#endif /* CONFIG_RTL8821C */
-+
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+	if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter))
-+		fill_tx_desc_8812a(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8192E)
-+	if (IS_HARDWARE_TYPE_8192E(padapter))
-+		fill_tx_desc_8192e(padapter);
-+#endif
-+#if defined(CONFIG_RTL8723B)
-+	if (IS_HARDWARE_TYPE_8723B(padapter))
-+		fill_tx_desc_8723b(padapter);
-+#endif
-+#if defined(CONFIG_RTL8703B)
-+	if (IS_HARDWARE_TYPE_8703B(padapter))
-+		fill_tx_desc_8703b(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8188F)
-+	if (IS_HARDWARE_TYPE_8188F(padapter))
-+		fill_tx_desc_8188f(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8188GTV)
-+	if (IS_HARDWARE_TYPE_8188GTV(padapter))
-+		fill_tx_desc_8188gtv(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8723D)
-+	if (IS_HARDWARE_TYPE_8723D(padapter))
-+		fill_tx_desc_8723d(padapter);
-+#endif
-+#if defined(CONFIG_RTL8192F)
-+		if (IS_HARDWARE_TYPE_8192F(padapter))
-+			fill_tx_desc_8192f(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8710B)
-+	if (IS_HARDWARE_TYPE_8710B(padapter))
-+		fill_tx_desc_8710b(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8814B)
-+	if (IS_HARDWARE_TYPE_8814B(padapter))
-+		rtl8814b_prepare_mp_txdesc(padapter, pmp_priv);
-+#endif /* CONFIG_RTL8814B */
-+
-+#if defined(CONFIG_RTL8723F)
-+	if (IS_HARDWARE_TYPE_8723F(padapter))
-+		rtl8723f_prepare_mp_txdesc(padapter, pmp_priv);
-+#endif /* CONFIG_RTL8723F */
-+
-+	/* 3 4. make wlan header, make_wlanhdr() */
-+	hdr = (struct rtw_ieee80211_hdr *)pkt_start;
-+	set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype);
-+
-+	_rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */
-+	_rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */
-+	_rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */
-+
-+	/* 3 5. make payload */
-+	ptr = pkt_start + pattrib->hdrlen;
-+
-+	if (pmp_priv->mplink_btx == _TRUE) {
-+		_rtw_memcpy(ptr, pmp_priv->mplink_buf, pkt_end - ptr);
-+	} else {
-+		switch (pmp_priv->tx.payload) {
-+		case MP_TX_Payload_00:
-+			RTW_INFO("MP packet tx 0x00 payload!\n");
-+			payload = 0x00;
-+			_rtw_memset(ptr, 0x00, pkt_end - ptr);
-+			break;
-+		case MP_TX_Payload_5a:
-+			RTW_INFO("MP packet tx 0x5a payload!\n");
-+			payload = 0x5a;
-+			_rtw_memset(ptr, 0x5a, pkt_end - ptr);
-+			break;
-+		case MP_TX_Payload_a5:
-+			RTW_INFO("MP packet tx 0xa5 payload!\n");
-+			payload = 0xa5;
-+			_rtw_memset(ptr, 0xa5, pkt_end - ptr);
-+			break;
-+		case MP_TX_Payload_ff:
-+			RTW_INFO("MP packet tx 0xff payload!\n");
-+			payload = 0xff;
-+			_rtw_memset(ptr, 0xff, pkt_end - ptr);
-+			break;
-+		case MP_TX_Payload_prbs9:
-+			RTW_INFO("MP packet tx PRBS9 payload!\n");
-+			while (idx <= pkt_end - ptr) {
-+				int start = 0x02;
-+				int a = start;
-+
-+				for (i = 0;; i++) {
-+						int newbit = (((a >> 8) ^ (a >> 4)) & 1);
-+						a = ((a << 1) | newbit) & 0x1ff;
-+						RTW_DBG("%x ", a);
-+						ptr[idx + i] = a;
-+
-+						if (a == start) {
-+							RTW_INFO("payload repetition period is %d , end %d\n", i , idx);
-+							tmp_idx += i;
-+							break;
-+						}
-+						if (idx + i >= (pkt_end - ptr)) {
-+							tmp_idx += (idx + i);
-+							RTW_INFO(" repetition period payload end curr ptr %d\n", idx + i);
-+							break;
-+						}
-+				}
-+				idx = tmp_idx;
-+			}
-+			break;
-+		case MP_TX_Payload_default_random:
-+			RTW_INFO("MP packet tx default random payload!\n");
-+			for (i = 0; i < pkt_end - ptr; i++)
-+				ptr[i] = rtw_random32() % 0xFF;
-+			break;
-+		default:
-+			RTW_INFO("Config payload type default use 0x%x\n!", pmp_priv->tx.payload);
-+			_rtw_memset(ptr, pmp_priv->tx.payload, pkt_end - ptr);
-+			break;
-+		}
-+	}
-+	/* 3 6. start thread */
-+#ifdef PLATFORM_LINUX
-+	pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD");
-+	if (IS_ERR(pmp_priv->tx.PktTxThread)) {
-+		RTW_ERR("Create PktTx Thread Fail !!!!!\n");
-+		pmp_priv->tx.PktTxThread = NULL;
-+	}
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	{
-+		struct proc *p;
-+		struct thread *td;
-+		pmp_priv->tx.PktTxThread = kproc_kthread_add(mp_xmit_packet_thread, pmp_priv,
-+			&p, &td, RFHIGHPID, 0, "MPXmitThread", "MPXmitThread");
-+
-+		if (pmp_priv->tx.PktTxThread < 0)
-+			RTW_INFO("Create PktTx Thread Fail !!!!!\n");
-+	}
-+#endif
-+
-+	Rtw_MPSetMacTxEDCA(padapter);
-+	return;
-+}
-+
-+void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
-+	struct mp_priv *pmppriv = &pAdapter->mppriv;
-+
-+
-+	if (bStartRx) {
-+#ifdef CONFIG_RTL8723B
-+		phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x3); /* Power on adc  (in RX_WAIT_CCA state) */
-+		write_bbreg(pAdapter, 0xa01, BIT0, bDisable);/* improve Rx performance by jerry	 */
-+#endif
-+		pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AMF | RCR_HTC_LOC_CTRL;
-+		pHalData->ReceiveConfig |= RCR_ACRC32;
-+		pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
-+
-+		if (pmppriv->bSetRxBssid == _TRUE) {
-+			RTW_INFO("%s: pmppriv->network_macaddr=" MAC_FMT "\n", __func__,
-+				 MAC_ARG(pmppriv->network_macaddr));
-+			pHalData->ReceiveConfig = 0;
-+			pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF;
-+			pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF;
-+
-+#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
-+/* todo: 8723F */
-+			write_bbreg(pAdapter, 0x550, BIT3, bEnable);
-+#endif
-+			rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFEF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
-+			pmppriv->brx_filter_beacon = _TRUE;
-+
-+		} else {
-+			pHalData->ReceiveConfig |= RCR_ADF;
-+			/* Accept all data frames */
-+			rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF);
-+		}
-+
-+		if (bAB)
-+			pHalData->ReceiveConfig |= RCR_AB;
-+	} else {
-+#ifdef CONFIG_RTL8723B
-+		phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x00); /* Power off adc  (in RX_WAIT_CCA state)*/
-+		write_bbreg(pAdapter, 0xa01, BIT0, bEnable);/* improve Rx performance by jerry	 */
-+#endif
-+		pHalData->ReceiveConfig = 0;
-+		rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFFF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
-+	}
-+
-+	rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
-+}
-+
-+void ResetPhyRxPktCount(PADAPTER pAdapter)
-+{
-+	u32 i, phyrx_set = 0;
-+
-+	for (i = 0; i <= 0xF; i++) {
-+		phyrx_set = 0;
-+		phyrx_set |= _RXERR_RPT_SEL(i);	/* select */
-+		phyrx_set |= RXERR_RPT_RST;	/* set counter to zero */
-+		rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
-+	}
-+}
-+
-+static u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit)
-+{
-+	/* selection */
-+	u32 phyrx_set = 0, count = 0;
-+
-+	phyrx_set = _RXERR_RPT_SEL(selbit & 0xF);
-+	rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
-+
-+	/* Read packet count */
-+	count = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK;
-+
-+	return count;
-+}
-+
-+u32 GetPhyRxPktReceived(PADAPTER pAdapter)
-+{
-+	u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
-+
-+	OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK);
-+	CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK);
-+	HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK);
-+
-+	return OFDM_cnt + CCK_cnt + HT_cnt;
-+}
-+
-+u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter)
-+{
-+	u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
-+
-+	OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL);
-+	CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL);
-+	HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL);
-+
-+	return OFDM_cnt + CCK_cnt + HT_cnt;
-+}
-+
-+struct psd_init_regs {
-+	/* 3 wire */
-+	int reg_88c;
-+	int reg_c00;
-+	int reg_e00;
-+	int reg_1800;
-+	int reg_1a00;
-+	/* cck */
-+	int reg_800;
-+	int reg_808;
-+};
-+
-+static int rtw_mp_psd_init(PADAPTER padapter, struct psd_init_regs *regs)
-+{
-+	HAL_DATA_TYPE	*phal_data	= GET_HAL_DATA(padapter);
-+
-+	switch (phal_data->rf_type) {
-+	/* 1R */
-+	case RF_1T1R:
-+		if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
-+			/* 11AC 1R PSD Setting 3wire & cck off */
-+			regs->reg_c00 = rtw_read32(padapter, 0xC00);
-+			phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
-+			regs->reg_808 = rtw_read32(padapter, 0x808);
-+			phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
-+		} else {
-+			/* 11N 3-wire off 1 */
-+			regs->reg_88c = rtw_read32(padapter, 0x88C);
-+			phy_set_bb_reg(padapter, 0x88C, 0x300000, 0x3);
-+			/* 11N CCK off */
-+			regs->reg_800 = rtw_read32(padapter, 0x800);
-+			phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);
-+		}
-+	break;
-+
-+	/* 2R */
-+	case RF_1T2R:
-+	case RF_2T2R:
-+		if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
-+			/* 11AC 2R PSD Setting 3wire & cck off */
-+			regs->reg_c00 = rtw_read32(padapter, 0xC00);
-+			regs->reg_e00 = rtw_read32(padapter, 0xE00);
-+			phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
-+			phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
-+			regs->reg_808 = rtw_read32(padapter, 0x808);
-+			phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
-+		} else {
-+			/* 11N 3-wire off 2 */
-+			regs->reg_88c = rtw_read32(padapter, 0x88C);
-+			phy_set_bb_reg(padapter, 0x88C, 0xF00000, 0xF);
-+			/* 11N CCK off */
-+			regs->reg_800 = rtw_read32(padapter, 0x800);
-+			phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);
-+		}
-+	break;
-+
-+	/* 3R */
-+	case RF_2T3R:
-+	case RF_3T3R:
-+		if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
-+			/* 11AC 3R PSD Setting 3wire & cck off */
-+			regs->reg_c00 = rtw_read32(padapter, 0xC00);
-+			regs->reg_e00 = rtw_read32(padapter, 0xE00);
-+			regs->reg_1800 = rtw_read32(padapter, 0x1800);
-+			phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
-+			phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
-+			phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);
-+			regs->reg_808 = rtw_read32(padapter, 0x808);
-+			phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
-+		} else {
-+			RTW_ERR("%s: 11n don't support 3R\n", __func__);
-+			return -1;
-+		}
-+		break;
-+
-+	/* 4R */
-+	case RF_2T4R:
-+	case RF_3T4R:
-+	case RF_4T4R:
-+		if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
-+			/* 11AC 4R PSD Setting 3wire & cck off */
-+			regs->reg_c00 = rtw_read32(padapter, 0xC00);
-+			regs->reg_e00 = rtw_read32(padapter, 0xE00);
-+			regs->reg_1800 = rtw_read32(padapter, 0x1800);
-+			regs->reg_1a00 = rtw_read32(padapter, 0x1A00);
-+			phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
-+			phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
-+			phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);
-+			phy_set_bb_reg(padapter, 0x1A00, 0x3, 0x00);
-+			regs->reg_808 = rtw_read32(padapter, 0x808);
-+			phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
-+		} else {
-+			RTW_ERR("%s: 11n don't support 4R\n", __func__);
-+			return -1;
-+		}
-+		break;
-+
-+	default:
-+		RTW_ERR("%s: unknown %d rf type\n", __func__, phal_data->rf_type);
-+		return -1;
-+	}
-+
-+	/* Set PSD points, 0=128, 1=256, 2=512, 3=1024 */
-+	if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC))
-+		phy_set_bb_reg(padapter, 0x910, 0xC000, 3);
-+	else
-+		phy_set_bb_reg(padapter, 0x808, 0xC000, 3);
-+
-+	RTW_INFO("%s: set %d rf type done\n", __func__, phal_data->rf_type);
-+	return 0;
-+}
-+
-+static int rtw_mp_psd_close(PADAPTER padapter, struct psd_init_regs *regs)
-+{
-+	HAL_DATA_TYPE	*phal_data	= GET_HAL_DATA(padapter);
-+
-+
-+	if (!hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
-+		/* 11n 3wire restore */
-+		rtw_write32(padapter, 0x88C, regs->reg_88c);
-+		/* 11n cck restore */
-+		rtw_write32(padapter, 0x800, regs->reg_800);
-+		RTW_INFO("%s: restore %d rf type\n", __func__, phal_data->rf_type);
-+		return 0;
-+	}
-+
-+	/* 11ac 3wire restore */
-+	switch (phal_data->rf_type) {
-+	case RF_1T1R:
-+		rtw_write32(padapter, 0xC00, regs->reg_c00);
-+		break;
-+	case RF_1T2R:
-+	case RF_2T2R:
-+		rtw_write32(padapter, 0xC00, regs->reg_c00);
-+		rtw_write32(padapter, 0xE00, regs->reg_e00);
-+		break;
-+	case RF_2T3R:
-+	case RF_3T3R:
-+		rtw_write32(padapter, 0xC00, regs->reg_c00);
-+		rtw_write32(padapter, 0xE00, regs->reg_e00);
-+		rtw_write32(padapter, 0x1800, regs->reg_1800);
-+		break;
-+	case RF_2T4R:
-+	case RF_3T4R:
-+	case RF_4T4R:
-+		rtw_write32(padapter, 0xC00, regs->reg_c00);
-+		rtw_write32(padapter, 0xE00, regs->reg_e00);
-+		rtw_write32(padapter, 0x1800, regs->reg_1800);
-+		rtw_write32(padapter, 0x1A00, regs->reg_1a00);
-+		break;
-+	default:
-+		RTW_WARN("%s: unknown %d rf type\n", __func__, phal_data->rf_type);
-+		break;
-+	}
-+
-+	/* 11ac cck restore */
-+	rtw_write32(padapter, 0x808, regs->reg_808);
-+	RTW_INFO("%s: restore %d rf type done\n", __func__, phal_data->rf_type);
-+	return 0;
-+}
-+
-+/* reg 0x808[9:0]: FFT data x
-+ * reg 0x808[22]:  0  -->  1  to get 1 FFT data y
-+ * reg 0x8B4[15:0]: FFT data y report */
-+static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point)
-+{
-+	u32 psd_val = 0;
-+
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) \
-+			|| defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
-+
-+	u16 psd_reg = 0x910;
-+	u16 psd_regL = 0xF44;
-+#else
-+	u16 psd_reg = 0x808;
-+	u16 psd_regL = 0x8B4;
-+#endif
-+
-+	psd_val = rtw_read32(pAdapter, psd_reg);
-+
-+	psd_val &= 0xFFBFFC00;
-+	psd_val |= point;
-+
-+	rtw_write32(pAdapter, psd_reg, psd_val);
-+	rtw_mdelay_os(1);
-+	psd_val |= 0x00400000;
-+
-+	rtw_write32(pAdapter, psd_reg, psd_val);
-+	rtw_mdelay_os(1);
-+
-+	psd_val = rtw_read32(pAdapter, psd_regL);
-+#if defined(CONFIG_RTL8821C)
-+	psd_val = (psd_val & 0x00FFFFFF) / 32;
-+#else
-+	psd_val &= 0x0000FFFF;
-+#endif
-+
-+	return psd_val;
-+}
-+
-+/*
-+ * pts	start_point_min		stop_point_max
-+ * 128	64			64 + 128 = 192
-+ * 256	128			128 + 256 = 384
-+ * 512	256			256 + 512 = 768
-+ * 1024	512			512 + 1024 = 1536
-+ *
-+ */
-+u32 mp_query_psd(PADAPTER pAdapter, u8 *data)
-+{
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
-+	struct dm_struct *p_dm = adapter_to_phydm(pAdapter);
-+
-+	u32 i, psd_pts = 0, psd_start = 0, psd_stop = 0;
-+	u32 psd_data = 0;
-+	struct psd_init_regs regs = {};
-+	int psd_analysis = 0;
-+	char *pdata = NULL;
-+
-+
-+#ifdef PLATFORM_LINUX
-+	if (!netif_running(pAdapter->pnetdev)) {
-+		return 0;
-+	}
-+#endif
-+
-+	if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
-+		return 0;
-+	}
-+
-+	if (strlen(data) == 0) { /* default value */
-+		psd_pts = 128;
-+		psd_start = 64;
-+		psd_stop = 128;
-+	} else if (strncmp(data, "analysis,", 9) == 0) {
-+		if (rtw_mp_psd_init(pAdapter, &regs) != 0)
-+			return 0;
-+		psd_analysis = 1;
-+		sscanf(data + 9, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
-+	} else
-+		sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
-+
-+	data[0] = '\0';
-+	pdata = data;
-+
-+	if (psd_stop > 1792 || psd_stop < 1) {
-+		rtw_warn_on(1);
-+		psd_stop = 1792;
-+	}
-+
-+	if (IS_HARDWARE_TYPE_8822C(pAdapter) || IS_HARDWARE_TYPE_8723F(pAdapter)) {
-+			u32 *psdbuf = rtw_zmalloc(sizeof(u32)*256);
-+
-+			if (psdbuf == NULL) {
-+				RTW_INFO("%s: psd buf malloc fail!!\n", __func__);
-+				return 0;
-+			}
-+
-+			halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_POINT, psd_pts);
-+			halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_START_POINT, psd_start);
-+			halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_STOP_POINT, psd_stop);
-+			halrf_cmn_info_set(p_dm, HALRF_CMNINFO_MP_PSD_AVERAGE, 0x20000);
-+
-+			halrf_psd_init(p_dm);
-+#ifdef CONFIG_LONG_DELAY_ISSUE
-+		rtw_msleep_os(100);
-+#else
-+		rtw_mdelay_os(10);
-+#endif
-+			halrf_psd_query(p_dm, psdbuf, 256);
-+
-+			i = 0;
-+			while (i < 256) {
-+				pdata += sprintf(pdata, "%x ", (psdbuf[i]));
-+				i++;
-+			}
-+
-+		if (psdbuf)
-+			rtw_mfree(psdbuf, sizeof(u32)*256);
-+
-+	} else {
-+			i = psd_start;
-+
-+			while (i < psd_stop) {
-+				if (i >= psd_pts)
-+					psd_data = rtw_GetPSDData(pAdapter, i - psd_pts);
-+				else
-+					psd_data = rtw_GetPSDData(pAdapter, i);
-+
-+				pdata += sprintf(pdata, "%x ", psd_data);
-+				i++;
-+			}
-+
-+	}
-+
-+#ifdef CONFIG_LONG_DELAY_ISSUE
-+	rtw_msleep_os(100);
-+#else
-+	rtw_mdelay_os(100);
-+#endif
-+
-+	if (psd_analysis)
-+		rtw_mp_psd_close(pAdapter, &regs);
-+
-+	return strlen(data) + 1;
-+}
-+
-+
-+#if 0
-+void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv)
-+{
-+	int i, res;
-+	_adapter *padapter = pxmitpriv->adapter;
-+	struct xmit_frame	*pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
-+	struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
-+
-+	u32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
-+	u32 num_xmit_extbuf = NR_XMIT_EXTBUFF;
-+	if (padapter->registrypriv.mp_mode == 0) {
-+		max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
-+		num_xmit_extbuf = NR_XMIT_EXTBUFF;
-+	} else {
-+		max_xmit_extbuf_size = 6000;
-+		num_xmit_extbuf = 8;
-+	}
-+
-+	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
-+	for (i = 0; i < num_xmit_extbuf; i++) {
-+		rtw_os_xmit_resource_free(padapter, pxmitbuf, (max_xmit_extbuf_size + XMITBUF_ALIGN_SZ), _FALSE);
-+
-+		pxmitbuf++;
-+	}
-+
-+	if (pxmitpriv->pallocated_xmit_extbuf)
-+		rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
-+
-+	if (padapter->registrypriv.mp_mode == 0) {
-+		max_xmit_extbuf_size = 6000;
-+		num_xmit_extbuf = 8;
-+	} else {
-+		max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
-+		num_xmit_extbuf = NR_XMIT_EXTBUFF;
-+	}
-+
-+	/* Init xmit extension buff */
-+	_rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);
-+
-+	pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
-+
-+	if (pxmitpriv->pallocated_xmit_extbuf  == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);
-+
-+	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
-+
-+	for (i = 0; i < num_xmit_extbuf; i++) {
-+		_rtw_init_listhead(&pxmitbuf->list);
-+
-+		pxmitbuf->priv_data = NULL;
-+		pxmitbuf->padapter = padapter;
-+		pxmitbuf->buf_tag = XMITBUF_MGNT;
-+
-+		res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, max_xmit_extbuf_size + XMITBUF_ALIGN_SZ, _TRUE);
-+		if (res == _FAIL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+		pxmitbuf->phead = pxmitbuf->pbuf;
-+		pxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size;
-+		pxmitbuf->len = 0;
-+		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
-+#endif
-+
-+		rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));
-+#ifdef DBG_XMIT_BUF_EXT
-+		pxmitbuf->no = i;
-+#endif
-+		pxmitbuf++;
-+
-+	}
-+
-+	pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf;
-+
-+exit:
-+	;
-+}
-+#endif
-+
-+u8
-+mpt_to_mgnt_rate(
-+		u32	MptRateIdx
-+)
-+{
-+	/* Mapped to MGN_XXX defined in MgntGen.h */
-+	switch (MptRateIdx) {
-+	/* CCK rate. */
-+	case	MPT_RATE_1M:
-+		return MGN_1M;
-+	case	MPT_RATE_2M:
-+		return MGN_2M;
-+	case	MPT_RATE_55M:
-+		return MGN_5_5M;
-+	case	MPT_RATE_11M:
-+		return MGN_11M;
-+
-+	/* OFDM rate. */
-+	case	MPT_RATE_6M:
-+		return MGN_6M;
-+	case	MPT_RATE_9M:
-+		return MGN_9M;
-+	case	MPT_RATE_12M:
-+		return MGN_12M;
-+	case	MPT_RATE_18M:
-+		return MGN_18M;
-+	case	MPT_RATE_24M:
-+		return MGN_24M;
-+	case	MPT_RATE_36M:
-+		return MGN_36M;
-+	case	MPT_RATE_48M:
-+		return MGN_48M;
-+	case	MPT_RATE_54M:
-+		return MGN_54M;
-+
-+	/* HT rate. */
-+	case	MPT_RATE_MCS0:
-+		return MGN_MCS0;
-+	case	MPT_RATE_MCS1:
-+		return MGN_MCS1;
-+	case	MPT_RATE_MCS2:
-+		return MGN_MCS2;
-+	case	MPT_RATE_MCS3:
-+		return MGN_MCS3;
-+	case	MPT_RATE_MCS4:
-+		return MGN_MCS4;
-+	case	MPT_RATE_MCS5:
-+		return MGN_MCS5;
-+	case	MPT_RATE_MCS6:
-+		return MGN_MCS6;
-+	case	MPT_RATE_MCS7:
-+		return MGN_MCS7;
-+	case	MPT_RATE_MCS8:
-+		return MGN_MCS8;
-+	case	MPT_RATE_MCS9:
-+		return MGN_MCS9;
-+	case	MPT_RATE_MCS10:
-+		return MGN_MCS10;
-+	case	MPT_RATE_MCS11:
-+		return MGN_MCS11;
-+	case	MPT_RATE_MCS12:
-+		return MGN_MCS12;
-+	case	MPT_RATE_MCS13:
-+		return MGN_MCS13;
-+	case	MPT_RATE_MCS14:
-+		return MGN_MCS14;
-+	case	MPT_RATE_MCS15:
-+		return MGN_MCS15;
-+	case	MPT_RATE_MCS16:
-+		return MGN_MCS16;
-+	case	MPT_RATE_MCS17:
-+		return MGN_MCS17;
-+	case	MPT_RATE_MCS18:
-+		return MGN_MCS18;
-+	case	MPT_RATE_MCS19:
-+		return MGN_MCS19;
-+	case	MPT_RATE_MCS20:
-+		return MGN_MCS20;
-+	case	MPT_RATE_MCS21:
-+		return MGN_MCS21;
-+	case	MPT_RATE_MCS22:
-+		return MGN_MCS22;
-+	case	MPT_RATE_MCS23:
-+		return MGN_MCS23;
-+	case	MPT_RATE_MCS24:
-+		return MGN_MCS24;
-+	case	MPT_RATE_MCS25:
-+		return MGN_MCS25;
-+	case	MPT_RATE_MCS26:
-+		return MGN_MCS26;
-+	case	MPT_RATE_MCS27:
-+		return MGN_MCS27;
-+	case	MPT_RATE_MCS28:
-+		return MGN_MCS28;
-+	case	MPT_RATE_MCS29:
-+		return MGN_MCS29;
-+	case	MPT_RATE_MCS30:
-+		return MGN_MCS30;
-+	case	MPT_RATE_MCS31:
-+		return MGN_MCS31;
-+
-+	/* VHT rate. */
-+	case	MPT_RATE_VHT1SS_MCS0:
-+		return MGN_VHT1SS_MCS0;
-+	case	MPT_RATE_VHT1SS_MCS1:
-+		return MGN_VHT1SS_MCS1;
-+	case	MPT_RATE_VHT1SS_MCS2:
-+		return MGN_VHT1SS_MCS2;
-+	case	MPT_RATE_VHT1SS_MCS3:
-+		return MGN_VHT1SS_MCS3;
-+	case	MPT_RATE_VHT1SS_MCS4:
-+		return MGN_VHT1SS_MCS4;
-+	case	MPT_RATE_VHT1SS_MCS5:
-+		return MGN_VHT1SS_MCS5;
-+	case	MPT_RATE_VHT1SS_MCS6:
-+		return MGN_VHT1SS_MCS6;
-+	case	MPT_RATE_VHT1SS_MCS7:
-+		return MGN_VHT1SS_MCS7;
-+	case	MPT_RATE_VHT1SS_MCS8:
-+		return MGN_VHT1SS_MCS8;
-+	case	MPT_RATE_VHT1SS_MCS9:
-+		return MGN_VHT1SS_MCS9;
-+	case	MPT_RATE_VHT2SS_MCS0:
-+		return MGN_VHT2SS_MCS0;
-+	case	MPT_RATE_VHT2SS_MCS1:
-+		return MGN_VHT2SS_MCS1;
-+	case	MPT_RATE_VHT2SS_MCS2:
-+		return MGN_VHT2SS_MCS2;
-+	case	MPT_RATE_VHT2SS_MCS3:
-+		return MGN_VHT2SS_MCS3;
-+	case	MPT_RATE_VHT2SS_MCS4:
-+		return MGN_VHT2SS_MCS4;
-+	case	MPT_RATE_VHT2SS_MCS5:
-+		return MGN_VHT2SS_MCS5;
-+	case	MPT_RATE_VHT2SS_MCS6:
-+		return MGN_VHT2SS_MCS6;
-+	case	MPT_RATE_VHT2SS_MCS7:
-+		return MGN_VHT2SS_MCS7;
-+	case	MPT_RATE_VHT2SS_MCS8:
-+		return MGN_VHT2SS_MCS8;
-+	case	MPT_RATE_VHT2SS_MCS9:
-+		return MGN_VHT2SS_MCS9;
-+	case	MPT_RATE_VHT3SS_MCS0:
-+		return MGN_VHT3SS_MCS0;
-+	case	MPT_RATE_VHT3SS_MCS1:
-+		return MGN_VHT3SS_MCS1;
-+	case	MPT_RATE_VHT3SS_MCS2:
-+		return MGN_VHT3SS_MCS2;
-+	case	MPT_RATE_VHT3SS_MCS3:
-+		return MGN_VHT3SS_MCS3;
-+	case	MPT_RATE_VHT3SS_MCS4:
-+		return MGN_VHT3SS_MCS4;
-+	case	MPT_RATE_VHT3SS_MCS5:
-+		return MGN_VHT3SS_MCS5;
-+	case	MPT_RATE_VHT3SS_MCS6:
-+		return MGN_VHT3SS_MCS6;
-+	case	MPT_RATE_VHT3SS_MCS7:
-+		return MGN_VHT3SS_MCS7;
-+	case	MPT_RATE_VHT3SS_MCS8:
-+		return MGN_VHT3SS_MCS8;
-+	case	MPT_RATE_VHT3SS_MCS9:
-+		return MGN_VHT3SS_MCS9;
-+	case	MPT_RATE_VHT4SS_MCS0:
-+		return MGN_VHT4SS_MCS0;
-+	case	MPT_RATE_VHT4SS_MCS1:
-+		return MGN_VHT4SS_MCS1;
-+	case	MPT_RATE_VHT4SS_MCS2:
-+		return MGN_VHT4SS_MCS2;
-+	case	MPT_RATE_VHT4SS_MCS3:
-+		return MGN_VHT4SS_MCS3;
-+	case	MPT_RATE_VHT4SS_MCS4:
-+		return MGN_VHT4SS_MCS4;
-+	case	MPT_RATE_VHT4SS_MCS5:
-+		return MGN_VHT4SS_MCS5;
-+	case	MPT_RATE_VHT4SS_MCS6:
-+		return MGN_VHT4SS_MCS6;
-+	case	MPT_RATE_VHT4SS_MCS7:
-+		return MGN_VHT4SS_MCS7;
-+	case	MPT_RATE_VHT4SS_MCS8:
-+		return MGN_VHT4SS_MCS8;
-+	case	MPT_RATE_VHT4SS_MCS9:
-+		return MGN_VHT4SS_MCS9;
-+
-+	case	MPT_RATE_LAST:	/* fully automatiMGN_VHT2SS_MCS1;	 */
-+	default:
-+		RTW_INFO("<===mpt_to_mgnt_rate(), Invalid Rate: %d!!\n", MptRateIdx);
-+		return 0x0;
-+	}
-+}
-+
-+
-+u8 HwRateToMPTRate(u8 rate)
-+{
-+	u8	ret_rate = MGN_1M;
-+
-+	switch (rate) {
-+	case DESC_RATE1M:
-+		ret_rate = MPT_RATE_1M;
-+		break;
-+	case DESC_RATE2M:
-+		ret_rate = MPT_RATE_2M;
-+		break;
-+	case DESC_RATE5_5M:
-+		ret_rate = MPT_RATE_55M;
-+		break;
-+	case DESC_RATE11M:
-+		ret_rate = MPT_RATE_11M;
-+		break;
-+	case DESC_RATE6M:
-+		ret_rate = MPT_RATE_6M;
-+		break;
-+	case DESC_RATE9M:
-+		ret_rate = MPT_RATE_9M;
-+		break;
-+	case DESC_RATE12M:
-+		ret_rate = MPT_RATE_12M;
-+		break;
-+	case DESC_RATE18M:
-+		ret_rate = MPT_RATE_18M;
-+		break;
-+	case DESC_RATE24M:
-+		ret_rate = MPT_RATE_24M;
-+		break;
-+	case DESC_RATE36M:
-+		ret_rate = MPT_RATE_36M;
-+		break;
-+	case DESC_RATE48M:
-+		ret_rate = MPT_RATE_48M;
-+		break;
-+	case DESC_RATE54M:
-+		ret_rate = MPT_RATE_54M;
-+		break;
-+	case DESC_RATEMCS0:
-+		ret_rate = MPT_RATE_MCS0;
-+		break;
-+	case DESC_RATEMCS1:
-+		ret_rate = MPT_RATE_MCS1;
-+		break;
-+	case DESC_RATEMCS2:
-+		ret_rate = MPT_RATE_MCS2;
-+		break;
-+	case DESC_RATEMCS3:
-+		ret_rate = MPT_RATE_MCS3;
-+		break;
-+	case DESC_RATEMCS4:
-+		ret_rate = MPT_RATE_MCS4;
-+		break;
-+	case DESC_RATEMCS5:
-+		ret_rate = MPT_RATE_MCS5;
-+		break;
-+	case DESC_RATEMCS6:
-+		ret_rate = MPT_RATE_MCS6;
-+		break;
-+	case DESC_RATEMCS7:
-+		ret_rate = MPT_RATE_MCS7;
-+		break;
-+	case DESC_RATEMCS8:
-+		ret_rate = MPT_RATE_MCS8;
-+		break;
-+	case DESC_RATEMCS9:
-+		ret_rate = MPT_RATE_MCS9;
-+		break;
-+	case DESC_RATEMCS10:
-+		ret_rate = MPT_RATE_MCS10;
-+		break;
-+	case DESC_RATEMCS11:
-+		ret_rate = MPT_RATE_MCS11;
-+		break;
-+	case DESC_RATEMCS12:
-+		ret_rate = MPT_RATE_MCS12;
-+		break;
-+	case DESC_RATEMCS13:
-+		ret_rate = MPT_RATE_MCS13;
-+		break;
-+	case DESC_RATEMCS14:
-+		ret_rate = MPT_RATE_MCS14;
-+		break;
-+	case DESC_RATEMCS15:
-+		ret_rate = MPT_RATE_MCS15;
-+		break;
-+	case DESC_RATEMCS16:
-+		ret_rate = MPT_RATE_MCS16;
-+		break;
-+	case DESC_RATEMCS17:
-+		ret_rate = MPT_RATE_MCS17;
-+		break;
-+	case DESC_RATEMCS18:
-+		ret_rate = MPT_RATE_MCS18;
-+		break;
-+	case DESC_RATEMCS19:
-+		ret_rate = MPT_RATE_MCS19;
-+		break;
-+	case DESC_RATEMCS20:
-+		ret_rate = MPT_RATE_MCS20;
-+		break;
-+	case DESC_RATEMCS21:
-+		ret_rate = MPT_RATE_MCS21;
-+		break;
-+	case DESC_RATEMCS22:
-+		ret_rate = MPT_RATE_MCS22;
-+		break;
-+	case DESC_RATEMCS23:
-+		ret_rate = MPT_RATE_MCS23;
-+		break;
-+	case DESC_RATEMCS24:
-+		ret_rate = MPT_RATE_MCS24;
-+		break;
-+	case DESC_RATEMCS25:
-+		ret_rate = MPT_RATE_MCS25;
-+		break;
-+	case DESC_RATEMCS26:
-+		ret_rate = MPT_RATE_MCS26;
-+		break;
-+	case DESC_RATEMCS27:
-+		ret_rate = MPT_RATE_MCS27;
-+		break;
-+	case DESC_RATEMCS28:
-+		ret_rate = MPT_RATE_MCS28;
-+		break;
-+	case DESC_RATEMCS29:
-+		ret_rate = MPT_RATE_MCS29;
-+		break;
-+	case DESC_RATEMCS30:
-+		ret_rate = MPT_RATE_MCS30;
-+		break;
-+	case DESC_RATEMCS31:
-+		ret_rate = MPT_RATE_MCS31;
-+		break;
-+	case DESC_RATEVHTSS1MCS0:
-+		ret_rate = MPT_RATE_VHT1SS_MCS0;
-+		break;
-+	case DESC_RATEVHTSS1MCS1:
-+		ret_rate = MPT_RATE_VHT1SS_MCS1;
-+		break;
-+	case DESC_RATEVHTSS1MCS2:
-+		ret_rate = MPT_RATE_VHT1SS_MCS2;
-+		break;
-+	case DESC_RATEVHTSS1MCS3:
-+		ret_rate = MPT_RATE_VHT1SS_MCS3;
-+		break;
-+	case DESC_RATEVHTSS1MCS4:
-+		ret_rate = MPT_RATE_VHT1SS_MCS4;
-+		break;
-+	case DESC_RATEVHTSS1MCS5:
-+		ret_rate = MPT_RATE_VHT1SS_MCS5;
-+		break;
-+	case DESC_RATEVHTSS1MCS6:
-+		ret_rate = MPT_RATE_VHT1SS_MCS6;
-+		break;
-+	case DESC_RATEVHTSS1MCS7:
-+		ret_rate = MPT_RATE_VHT1SS_MCS7;
-+		break;
-+	case DESC_RATEVHTSS1MCS8:
-+		ret_rate = MPT_RATE_VHT1SS_MCS8;
-+		break;
-+	case DESC_RATEVHTSS1MCS9:
-+		ret_rate = MPT_RATE_VHT1SS_MCS9;
-+		break;
-+	case DESC_RATEVHTSS2MCS0:
-+		ret_rate = MPT_RATE_VHT2SS_MCS0;
-+		break;
-+	case DESC_RATEVHTSS2MCS1:
-+		ret_rate = MPT_RATE_VHT2SS_MCS1;
-+		break;
-+	case DESC_RATEVHTSS2MCS2:
-+		ret_rate = MPT_RATE_VHT2SS_MCS2;
-+		break;
-+	case DESC_RATEVHTSS2MCS3:
-+		ret_rate = MPT_RATE_VHT2SS_MCS3;
-+		break;
-+	case DESC_RATEVHTSS2MCS4:
-+		ret_rate = MPT_RATE_VHT2SS_MCS4;
-+		break;
-+	case DESC_RATEVHTSS2MCS5:
-+		ret_rate = MPT_RATE_VHT2SS_MCS5;
-+		break;
-+	case DESC_RATEVHTSS2MCS6:
-+		ret_rate = MPT_RATE_VHT2SS_MCS6;
-+		break;
-+	case DESC_RATEVHTSS2MCS7:
-+		ret_rate = MPT_RATE_VHT2SS_MCS7;
-+		break;
-+	case DESC_RATEVHTSS2MCS8:
-+		ret_rate = MPT_RATE_VHT2SS_MCS8;
-+		break;
-+	case DESC_RATEVHTSS2MCS9:
-+		ret_rate = MPT_RATE_VHT2SS_MCS9;
-+		break;
-+	case DESC_RATEVHTSS3MCS0:
-+		ret_rate = MPT_RATE_VHT3SS_MCS0;
-+		break;
-+	case DESC_RATEVHTSS3MCS1:
-+		ret_rate = MPT_RATE_VHT3SS_MCS1;
-+		break;
-+	case DESC_RATEVHTSS3MCS2:
-+		ret_rate = MPT_RATE_VHT3SS_MCS2;
-+		break;
-+	case DESC_RATEVHTSS3MCS3:
-+		ret_rate = MPT_RATE_VHT3SS_MCS3;
-+		break;
-+	case DESC_RATEVHTSS3MCS4:
-+		ret_rate = MPT_RATE_VHT3SS_MCS4;
-+		break;
-+	case DESC_RATEVHTSS3MCS5:
-+		ret_rate = MPT_RATE_VHT3SS_MCS5;
-+		break;
-+	case DESC_RATEVHTSS3MCS6:
-+		ret_rate = MPT_RATE_VHT3SS_MCS6;
-+		break;
-+	case DESC_RATEVHTSS3MCS7:
-+		ret_rate = MPT_RATE_VHT3SS_MCS7;
-+		break;
-+	case DESC_RATEVHTSS3MCS8:
-+		ret_rate = MPT_RATE_VHT3SS_MCS8;
-+		break;
-+	case DESC_RATEVHTSS3MCS9:
-+		ret_rate = MPT_RATE_VHT3SS_MCS9;
-+		break;
-+	case DESC_RATEVHTSS4MCS0:
-+		ret_rate = MPT_RATE_VHT4SS_MCS0;
-+		break;
-+	case DESC_RATEVHTSS4MCS1:
-+		ret_rate = MPT_RATE_VHT4SS_MCS1;
-+		break;
-+	case DESC_RATEVHTSS4MCS2:
-+		ret_rate = MPT_RATE_VHT4SS_MCS2;
-+		break;
-+	case DESC_RATEVHTSS4MCS3:
-+		ret_rate = MPT_RATE_VHT4SS_MCS3;
-+		break;
-+	case DESC_RATEVHTSS4MCS4:
-+		ret_rate = MPT_RATE_VHT4SS_MCS4;
-+		break;
-+	case DESC_RATEVHTSS4MCS5:
-+		ret_rate = MPT_RATE_VHT4SS_MCS5;
-+		break;
-+	case DESC_RATEVHTSS4MCS6:
-+		ret_rate = MPT_RATE_VHT4SS_MCS6;
-+		break;
-+	case DESC_RATEVHTSS4MCS7:
-+		ret_rate = MPT_RATE_VHT4SS_MCS7;
-+		break;
-+	case DESC_RATEVHTSS4MCS8:
-+		ret_rate = MPT_RATE_VHT4SS_MCS8;
-+		break;
-+	case DESC_RATEVHTSS4MCS9:
-+		ret_rate = MPT_RATE_VHT4SS_MCS9;
-+		break;
-+
-+	default:
-+		RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate);
-+		break;
-+	}
-+	return ret_rate;
-+}
-+
-+u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr)
-+{
-+	u16 i = 0;
-+	u8 *rateindex_Array[] = { "1M", "2M", "5.5M", "11M", "6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M",
-+		"HTMCS0", "HTMCS1", "HTMCS2", "HTMCS3", "HTMCS4", "HTMCS5", "HTMCS6", "HTMCS7",
-+		"HTMCS8", "HTMCS9", "HTMCS10", "HTMCS11", "HTMCS12", "HTMCS13", "HTMCS14", "HTMCS15",
-+		"HTMCS16", "HTMCS17", "HTMCS18", "HTMCS19", "HTMCS20", "HTMCS21", "HTMCS22", "HTMCS23",
-+		"HTMCS24", "HTMCS25", "HTMCS26", "HTMCS27", "HTMCS28", "HTMCS29", "HTMCS30", "HTMCS31",
-+		"VHT1MCS0", "VHT1MCS1", "VHT1MCS2", "VHT1MCS3", "VHT1MCS4", "VHT1MCS5", "VHT1MCS6", "VHT1MCS7", "VHT1MCS8", "VHT1MCS9",
-+		"VHT2MCS0", "VHT2MCS1", "VHT2MCS2", "VHT2MCS3", "VHT2MCS4", "VHT2MCS5", "VHT2MCS6", "VHT2MCS7", "VHT2MCS8", "VHT2MCS9",
-+		"VHT3MCS0", "VHT3MCS1", "VHT3MCS2", "VHT3MCS3", "VHT3MCS4", "VHT3MCS5", "VHT3MCS6", "VHT3MCS7", "VHT3MCS8", "VHT3MCS9",
-+		"VHT4MCS0", "VHT4MCS1", "VHT4MCS2", "VHT4MCS3", "VHT4MCS4", "VHT4MCS5", "VHT4MCS6", "VHT4MCS7", "VHT4MCS8", "VHT4MCS9"
-+				};
-+
-+	for (i = 0; i <= 83; i++) {
-+		if (strcmp(targetStr, rateindex_Array[i]) == 0) {
-+			RTW_INFO("%s , index = %d\n", __func__ , i);
-+			return i;
-+		}
-+	}
-+
-+	printk("%s ,please input a Data RATE String as:", __func__);
-+	for (i = 0; i <= 83; i++) {
-+		printk("%s ", rateindex_Array[i]);
-+		if (i % 10 == 0)
-+			printk("\n");
-+	}
-+	return _FAIL;
-+}
-+
-+u8 rtw_mp_mode_check(PADAPTER pAdapter)
-+{
-+	PADAPTER primary_adapter = GET_PRIMARY_ADAPTER(pAdapter);
-+
-+	if (primary_adapter->registrypriv.mp_mode == 1 || primary_adapter->mppriv.bprocess_mp_mode == _TRUE)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+bool rtw_is_mp_tssitrk_on(_adapter *adapter)
-+{
-+	_adapter *primary_adapter = GET_PRIMARY_ADAPTER(adapter);
-+
-+	return primary_adapter->mppriv.tssitrk_on;
-+}
-+
-+u32 mpt_ProQueryCalTxPower(
-+	PADAPTER	pAdapter,
-+	u8		RfPath
-+)
-+{
-+
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
-+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+
-+	u32			TxPower = 1;
-+	struct txpwr_idx_comp tic;
-+	u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
-+	RATE_SECTION rs = mgn_rate_to_rs(mgn_rate);
-+
-+	TxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, rs, mgn_rate
-+		, pHalData->current_channel_bw, pHalData->current_band_type, pHalData->current_channel, 0, &tic);
-+
-+	dump_tx_power_index_inline(RTW_DBGDUMP, pAdapter, RfPath
-+		, pHalData->current_channel_bw, pHalData->current_channel
-+		, mgn_rate, TxPower, &tic);
-+
-+	pAdapter->mppriv.txpoweridx = (u8)TxPower;
-+	if (RfPath == RF_PATH_A)
-+		pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)TxPower;
-+	else if (RfPath == RF_PATH_B)
-+		pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)TxPower;
-+	else if (RfPath == RF_PATH_C)
-+		pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)TxPower;
-+	else if (RfPath == RF_PATH_D)
-+		pMptCtx->TxPwrLevel[RF_PATH_D] = (u8)TxPower;
-+	hal_mpt_SetTxPower(pAdapter);
-+
-+	return TxPower;
-+}
-+
-+u32 mpt_get_tx_power_finalabs_val(PADAPTER	padapter, u8 rf_path)
-+{
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
-+	PMPT_CONTEXT		pMptCtx = &(padapter->mppriv.mpt_ctx);
-+
-+	u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
-+	u32 powerdbm = 0;
-+
-+	powerdbm = phy_get_tx_power_final_absolute_value(padapter, rf_path, mgn_rate, pHalData->current_channel_bw, pHalData->current_channel);
-+	
-+	RTW_INFO("bw=%d, ch=%d, rateid=%d, TSSI Power(dBm):%d\n",
-+		pHalData->current_channel_bw, pHalData->current_channel, mgn_rate ,powerdbm);
-+
-+	return powerdbm;
-+}
-+
-+#ifdef CONFIG_MP_VHT_HW_TX_MODE
-+static inline void dump_buf(u8 *buf, u32 len)
-+{
-+	u32 i;
-+
-+	RTW_INFO("-----------------Len %d----------------\n", len);
-+	for (i = 0; i < len; i++)
-+		RTW_INFO("%2.2x-", *(buf + i));
-+	RTW_INFO("\n");
-+}
-+
-+void ByteToBit(
-+	u8	*out,
-+	bool	*in,
-+	u8	in_size)
-+{
-+	u8 i = 0, j = 0;
-+
-+	for (i = 0; i < in_size; i++) {
-+		for (j = 0; j < 8; j++) {
-+			if (in[8 * i + j])
-+				out[i] |= (1 << j);
-+		}
-+	}
-+}
-+
-+
-+void CRC16_generator(
-+	bool *out,
-+	bool *in,
-+	u8 in_size
-+)
-+{
-+	u8 i = 0;
-+	bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
-+
-+	for (i = 0; i < in_size; i++) {/* take one's complement and bit reverse*/
-+		temp = in[i] ^ reg[15];
-+		reg[15]	= reg[14];
-+		reg[14]	= reg[13];
-+		reg[13]	= reg[12];
-+		reg[12]	= reg[11];
-+		reg[11]	= reg[10];
-+		reg[10]	= reg[9];
-+		reg[9]	= reg[8];
-+		reg[8]	= reg[7];
-+
-+		reg[7]	= reg[6];
-+		reg[6]	= reg[5];
-+		reg[5]	= reg[4];
-+		reg[4]	= reg[3];
-+		reg[3]	= reg[2];
-+		reg[2]	= reg[1];
-+		reg[1]	= reg[0];
-+		reg[12]	= reg[12] ^ temp;
-+		reg[5]	= reg[5] ^ temp;
-+		reg[0]	= temp;
-+	}
-+	for (i = 0; i < 16; i++)	/* take one's complement and bit reverse*/
-+		out[i] = 1 - reg[15 - i];
-+}
-+
-+
-+
-+/*========================================
-+	SFD		SIGNAL	SERVICE	LENGTH	CRC
-+	16 bit	8 bit	8 bit	16 bit	16 bit
-+========================================*/
-+void CCK_generator(
-+	PRT_PMAC_TX_INFO	pPMacTxInfo,
-+	PRT_PMAC_PKT_INFO	pPMacPktInfo
-+)
-+{
-+	double	ratio = 0;
-+	bool	crc16_in[32] = {0}, crc16_out[16] = {0};
-+	bool LengthExtBit;
-+	double LengthExact;
-+	double LengthPSDU;
-+	u8 i;
-+	u32 PacketLength = pPMacTxInfo->PacketLength;
-+
-+	if (pPMacTxInfo->bSPreamble)
-+		pPMacTxInfo->SFD = 0x05CF;
-+	else
-+		pPMacTxInfo->SFD = 0xF3A0;
-+
-+	switch (pPMacPktInfo->MCS) {
-+	case 0:
-+		pPMacTxInfo->SignalField = 0xA;
-+		ratio = 8;
-+		/*CRC16_in(1,0:7)=[0 1 0 1 0 0 0 0]*/
-+		crc16_in[1] = crc16_in[3] = 1;
-+		break;
-+	case 1:
-+		pPMacTxInfo->SignalField = 0x14;
-+		ratio = 4;
-+		/*CRC16_in(1,0:7)=[0 0 1 0 1 0 0 0];*/
-+		crc16_in[2] = crc16_in[4] = 1;
-+		break;
-+	case 2:
-+		pPMacTxInfo->SignalField = 0x37;
-+		ratio = 8.0 / 5.5;
-+		/*CRC16_in(1,0:7)=[1 1 1 0 1 1 0 0];*/
-+		crc16_in[0] = crc16_in[1] = crc16_in[2] = crc16_in[4] = crc16_in[5] = 1;
-+		break;
-+	case 3:
-+		pPMacTxInfo->SignalField = 0x6E;
-+		ratio = 8.0 / 11.0;
-+		/*CRC16_in(1,0:7)=[0 1 1 1 0 1 1 0];*/
-+		crc16_in[1] = crc16_in[2] = crc16_in[3] = crc16_in[5] = crc16_in[6] = 1;
-+		break;
-+	}
-+
-+	LengthExact = PacketLength * ratio;
-+	LengthPSDU = ceil(LengthExact);
-+
-+	if ((pPMacPktInfo->MCS == 3) &&
-+	    ((LengthPSDU - LengthExact) >= 0.727 || (LengthPSDU - LengthExact) <= -0.727))
-+		LengthExtBit = 1;
-+	else
-+		LengthExtBit = 0;
-+
-+
-+	pPMacTxInfo->LENGTH = (u32)LengthPSDU;
-+	/* CRC16_in(1,16:31) = LengthPSDU[0:15]*/
-+	for (i = 0; i < 16; i++)
-+		crc16_in[i + 16] = (pPMacTxInfo->LENGTH >> i) & 0x1;
-+
-+	if (LengthExtBit == 0) {
-+		pPMacTxInfo->ServiceField = 0x0;
-+		/* CRC16_in(1,8:15) = [0 0 0 0 0 0 0 0];*/
-+	} else {
-+		pPMacTxInfo->ServiceField = 0x80;
-+		/*CRC16_in(1,8:15)=[0 0 0 0 0 0 0 1];*/
-+		crc16_in[15] = 1;
-+	}
-+
-+	CRC16_generator(crc16_out, crc16_in, 32);
-+
-+	_rtw_memset(pPMacTxInfo->CRC16, 0, 2);
-+	ByteToBit(pPMacTxInfo->CRC16, crc16_out, 2);
-+
-+}
-+
-+
-+void PMAC_Get_Pkt_Param(
-+	PRT_PMAC_TX_INFO	pPMacTxInfo,
-+	PRT_PMAC_PKT_INFO	pPMacPktInfo)
-+{
-+
-+	u8		TX_RATE_HEX = 0, MCS = 0;
-+	u8		TX_RATE = pPMacTxInfo->TX_RATE;
-+
-+	/*	TX_RATE & Nss	*/
-+	if (MPT_IS_2SS_RATE(TX_RATE))
-+		pPMacPktInfo->Nss = 2;
-+	else if (MPT_IS_3SS_RATE(TX_RATE))
-+		pPMacPktInfo->Nss = 3;
-+	else if (MPT_IS_4SS_RATE(TX_RATE))
-+		pPMacPktInfo->Nss = 4;
-+	else
-+		pPMacPktInfo->Nss = 1;
-+
-+	RTW_INFO("PMacTxInfo.Nss =%d\n", pPMacPktInfo->Nss);
-+
-+	/*	MCS & TX_RATE_HEX*/
-+	if (MPT_IS_CCK_RATE(TX_RATE)) {
-+		switch (TX_RATE) {
-+		case MPT_RATE_1M:
-+			TX_RATE_HEX = MCS = 0;
-+			break;
-+		case MPT_RATE_2M:
-+			TX_RATE_HEX = MCS = 1;
-+			break;
-+		case MPT_RATE_55M:
-+			TX_RATE_HEX = MCS = 2;
-+			break;
-+		case MPT_RATE_11M:
-+			TX_RATE_HEX = MCS = 3;
-+			break;
-+		}
-+	} else if (MPT_IS_OFDM_RATE(TX_RATE)) {
-+		MCS = TX_RATE - MPT_RATE_6M;
-+		TX_RATE_HEX = MCS + 4;
-+	} else if (MPT_IS_HT_RATE(TX_RATE)) {
-+		MCS = TX_RATE - MPT_RATE_MCS0;
-+		TX_RATE_HEX = MCS + 12;
-+	} else if (MPT_IS_VHT_RATE(TX_RATE)) {
-+		TX_RATE_HEX = TX_RATE - MPT_RATE_VHT1SS_MCS0 + 44;
-+
-+		if (MPT_IS_VHT_2S_RATE(TX_RATE))
-+			MCS = TX_RATE - MPT_RATE_VHT2SS_MCS0;
-+		else if (MPT_IS_VHT_3S_RATE(TX_RATE))
-+			MCS = TX_RATE - MPT_RATE_VHT3SS_MCS0;
-+		else if (MPT_IS_VHT_4S_RATE(TX_RATE))
-+			MCS = TX_RATE - MPT_RATE_VHT4SS_MCS0;
-+		else
-+			MCS = TX_RATE - MPT_RATE_VHT1SS_MCS0;
-+	}
-+
-+	pPMacPktInfo->MCS = MCS;
-+	pPMacTxInfo->TX_RATE_HEX = TX_RATE_HEX;
-+
-+	RTW_INFO(" MCS=%d, TX_RATE_HEX =0x%x\n", MCS, pPMacTxInfo->TX_RATE_HEX);
-+	/*	mSTBC & Nsts*/
-+	pPMacPktInfo->Nsts = pPMacPktInfo->Nss;
-+	if (pPMacTxInfo->bSTBC) {
-+		if (pPMacPktInfo->Nss == 1) {
-+			pPMacTxInfo->m_STBC = 2;
-+			pPMacPktInfo->Nsts = pPMacPktInfo->Nss * 2;
-+		} else
-+			pPMacTxInfo->m_STBC = 1;
-+	} else
-+		pPMacTxInfo->m_STBC = 1;
-+}
-+
-+
-+u32 LDPC_parameter_generator(
-+	u32 N_pld_int,
-+	u32 N_CBPSS,
-+	u32 N_SS,
-+	u32 R,
-+	u32 m_STBC,
-+	u32 N_TCB_int
-+)
-+{
-+	double	CR = 0.;
-+	double	N_pld = (double)N_pld_int;
-+	double	N_TCB = (double)N_TCB_int;
-+	double	N_CW = 0., N_shrt = 0., N_spcw = 0., N_fshrt = 0.;
-+	double	L_LDPC = 0., K_LDPC = 0., L_LDPC_info = 0.;
-+	double	N_punc = 0., N_ppcw = 0., N_fpunc = 0., N_rep = 0., N_rpcw = 0., N_frep = 0.;
-+	double	R_eff = 0.;
-+	u32	VHTSIGA2B3  = 0;/* extra symbol from VHT-SIG-A2 Bit 3*/
-+
-+	if (R == 0)
-+		CR	= 0.5;
-+	else if (R == 1)
-+		CR = 2. / 3.;
-+	else if (R == 2)
-+		CR = 3. / 4.;
-+	else if (R == 3)
-+		CR = 5. / 6.;
-+
-+	if (N_TCB <= 648.) {
-+		N_CW	= 1.;
-+		if (N_TCB >= N_pld + 912.*(1. - CR))
-+			L_LDPC	= 1296.;
-+		else
-+			L_LDPC	= 648.;
-+	} else if (N_TCB <= 1296.) {
-+		N_CW	= 1.;
-+		if (N_TCB >= (double)N_pld + 1464.*(1. - CR))
-+			L_LDPC	= 1944.;
-+		else
-+			L_LDPC	= 1296.;
-+	} else if	(N_TCB <= 1944.) {
-+		N_CW	= 1.;
-+		L_LDPC	= 1944.;
-+	} else if (N_TCB <= 2592.) {
-+		N_CW	= 2.;
-+		if (N_TCB >= N_pld + 2916.*(1. - CR))
-+			L_LDPC	= 1944.;
-+		else
-+			L_LDPC	= 1296.;
-+	} else {
-+		N_CW = ceil(N_pld / 1944. / CR);
-+		L_LDPC	= 1944.;
-+	}
-+	/*	Number of information bits per CW*/
-+	K_LDPC = L_LDPC * CR;
-+	/*	Number of shortening bits					max(0, (N_CW * L_LDPC * R) - N_pld)*/
-+	N_shrt = (N_CW * K_LDPC - N_pld) > 0. ? (N_CW * K_LDPC - N_pld) : 0.;
-+	/*	Number of shortening bits per CW			N_spcw = rtfloor(N_shrt/N_CW)*/
-+	N_spcw = rtfloor(N_shrt / N_CW);
-+	/*	The first N_fshrt CWs shorten 1 bit more*/
-+	N_fshrt = (double)((int)N_shrt % (int)N_CW);
-+	/*	Number of data bits for the last N_CW-N_fshrt CWs*/
-+	L_LDPC_info = K_LDPC - N_spcw;
-+	/*	Number of puncturing bits*/
-+	N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
-+	if (((N_punc > .1 * N_CW * L_LDPC * (1. - CR)) && (N_shrt < 1.2 * N_punc * CR / (1. - CR))) ||
-+	    (N_punc > 0.3 * N_CW * L_LDPC * (1. - CR))) {
-+		/*cout << "*** N_TCB and N_punc are Recomputed ***" << endl;*/
-+		VHTSIGA2B3 = 1;
-+		N_TCB += (double)N_CBPSS * N_SS * m_STBC;
-+		N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
-+	} else
-+		VHTSIGA2B3 = 0;
-+
-+	return VHTSIGA2B3;
-+}	/* function end of LDPC_parameter_generator */
-+
-+/*========================================
-+	Data field of PPDU
-+	Get N_sym and SIGA2BB3
-+========================================*/
-+void PMAC_Nsym_generator(
-+	PRT_PMAC_TX_INFO	pPMacTxInfo,
-+	PRT_PMAC_PKT_INFO	pPMacPktInfo)
-+{
-+	u32	SIGA2B3 = 0;
-+	u8	TX_RATE = pPMacTxInfo->TX_RATE;
-+
-+	u32 R, R_list[10] = {0, 0, 2, 0, 2, 1, 2, 3, 2, 3};
-+	double CR = 0;
-+	u32 N_SD, N_BPSC_list[10] = {1, 2, 2, 4, 4, 6, 6, 6, 8, 8};
-+	u32 N_BPSC = 0, N_CBPS = 0, N_DBPS = 0, N_ES = 0, N_SYM = 0, N_pld = 0, N_TCB = 0;
-+	int D_R = 0;
-+
-+	RTW_INFO("TX_RATE = %d\n", TX_RATE);
-+	/*	N_SD*/
-+	if (pPMacTxInfo->BandWidth == 0)
-+		N_SD = 52;
-+	else if (pPMacTxInfo->BandWidth == 1)
-+		N_SD = 108;
-+	else
-+		N_SD = 234;
-+
-+	if (MPT_IS_HT_RATE(TX_RATE)) {
-+		u8 MCS_temp;
-+
-+		if (pPMacPktInfo->MCS > 23)
-+			MCS_temp = pPMacPktInfo->MCS - 24;
-+		else if (pPMacPktInfo->MCS > 15)
-+			MCS_temp = pPMacPktInfo->MCS - 16;
-+		else if (pPMacPktInfo->MCS > 7)
-+			MCS_temp = pPMacPktInfo->MCS - 8;
-+		else
-+			MCS_temp = pPMacPktInfo->MCS;
-+
-+		R = R_list[MCS_temp];
-+
-+		switch (R) {
-+		case 0:
-+			CR = .5;
-+			break;
-+		case 1:
-+			CR = 2. / 3.;
-+			break;
-+		case 2:
-+			CR = 3. / 4.;
-+			break;
-+		case 3:
-+			CR = 5. / 6.;
-+			break;
-+		}
-+
-+		N_BPSC = N_BPSC_list[MCS_temp];
-+		N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
-+		N_DBPS = (u32)((double)N_CBPS * CR);
-+
-+		if (pPMacTxInfo->bLDPC == FALSE) {
-+			N_ES = (u32)ceil((double)(N_DBPS * pPMacPktInfo->Nss) / 4. / 300.);
-+			RTW_INFO("N_ES = %d\n", N_ES);
-+
-+			/*	N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
-+			N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) /
-+					(double)(N_DBPS * pPMacTxInfo->m_STBC));
-+
-+		} else {
-+			N_ES = 1;
-+			/*	N_pld = length * 8 + 16*/
-+			N_pld = pPMacTxInfo->PacketLength * 8 + 16;
-+			RTW_INFO("N_pld = %d\n", N_pld);
-+			N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(N_pld) /
-+					(double)(N_DBPS * pPMacTxInfo->m_STBC));
-+			RTW_INFO("N_SYM = %d\n", N_SYM);
-+			/*	N_avbits = N_CBPS *m_STBC *(N_pld/N_CBPS*R*m_STBC)*/
-+			N_TCB = N_CBPS * N_SYM;
-+			RTW_INFO("N_TCB = %d\n", N_TCB);
-+			SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
-+			RTW_INFO("SIGA2B3 = %d\n", SIGA2B3);
-+			N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
-+			RTW_INFO("N_SYM = %d\n", N_SYM);
-+		}
-+	} else if (MPT_IS_VHT_RATE(TX_RATE)) {
-+		R = R_list[pPMacPktInfo->MCS];
-+
-+		switch (R) {
-+		case 0:
-+			CR = .5;
-+			break;
-+		case 1:
-+			CR = 2. / 3.;
-+			break;
-+		case 2:
-+			CR = 3. / 4.;
-+			break;
-+		case 3:
-+			CR = 5. / 6.;
-+			break;
-+		}
-+		N_BPSC = N_BPSC_list[pPMacPktInfo->MCS];
-+		N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
-+		N_DBPS = (u32)((double)N_CBPS * CR);
-+		if (pPMacTxInfo->bLDPC == FALSE) {
-+			if (pPMacTxInfo->bSGI)
-+				N_ES = (u32)ceil((double)(N_DBPS) / 3.6 / 600.);
-+			else
-+				N_ES = (u32)ceil((double)(N_DBPS) / 4. / 600.);
-+			/*	N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
-+			N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
-+			SIGA2B3 = 0;
-+		} else {
-+			N_ES = 1;
-+			/*	N_SYM = m_STBC* (8*length+N_service) / (m_STBC*N_DBPS)*/
-+			N_SYM = pPMacTxInfo->m_STBC * (u32)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
-+			/*	N_avbits = N_sys_init * N_CBPS*/
-+			N_TCB = N_CBPS * N_SYM;
-+			/*	N_pld = N_sys_init * N_DBPS*/
-+			N_pld = N_SYM * N_DBPS;
-+			SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
-+			N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
-+		}
-+
-+		switch (R) {
-+		case 0:
-+			D_R = 2;
-+			break;
-+		case 1:
-+			D_R = 3;
-+			break;
-+		case 2:
-+			D_R = 4;
-+			break;
-+		case 3:
-+			D_R = 6;
-+			break;
-+		}
-+
-+		if (((N_CBPS / N_ES) % D_R) != 0) {
-+			RTW_INFO("MCS= %d is not supported when Nss=%d and BW= %d !!\n",  pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
-+			return;
-+		}
-+
-+		RTW_INFO("MCS= %d Nss=%d and BW= %d !!\n",  pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
-+	}
-+
-+	pPMacPktInfo->N_sym = N_SYM;
-+	pPMacPktInfo->SIGA2B3 = SIGA2B3;
-+}
-+
-+/*========================================
-+	L-SIG	Rate	R	Length	P	Tail
-+			4b		1b	12b		1b	6b
-+========================================*/
-+
-+void L_SIG_generator(
-+	u32	N_SYM,		/* Max: 750*/
-+	PRT_PMAC_TX_INFO	pPMacTxInfo,
-+	PRT_PMAC_PKT_INFO	pPMacPktInfo)
-+{
-+	u8	sig_bi[24] = {0};	/* 24 BIT*/
-+	u32	mode, LENGTH;
-+	int i;
-+
-+	if (MPT_IS_OFDM_RATE(pPMacTxInfo->TX_RATE)) {
-+		mode = pPMacPktInfo->MCS;
-+		LENGTH = pPMacTxInfo->PacketLength;
-+	} else {
-+		u8	N_LTF;
-+		double	T_data;
-+		u32	OFDM_symbol;
-+
-+		mode = 0;
-+
-+		/*	Table 20-13 Num of HT-DLTFs request*/
-+		if (pPMacPktInfo->Nsts <= 2)
-+			N_LTF = pPMacPktInfo->Nsts;
-+		else
-+			N_LTF = 4;
-+
-+		if (pPMacTxInfo->bSGI)
-+			T_data = 3.6;
-+		else
-+			T_data = 4.0;
-+
-+		/*(L-SIG, HT-SIG, HT-STF, HT-LTF....HT-LTF, Data)*/
-+		if (MPT_IS_VHT_RATE(pPMacTxInfo->TX_RATE))
-+			OFDM_symbol = (u32)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data + 4) / 4.);
-+		else
-+			OFDM_symbol = (u32)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data) / 4.);
-+
-+		RTW_INFO("%s , OFDM_symbol =%d\n", __func__, OFDM_symbol);
-+		LENGTH = OFDM_symbol * 3 - 3;
-+		RTW_INFO("%s , LENGTH =%d\n", __func__, LENGTH);
-+
-+	}
-+	/*	Rate Field*/
-+	switch (mode) {
-+	case	0:
-+		sig_bi[0] = 1;
-+		sig_bi[1] = 1;
-+		sig_bi[2] = 0;
-+		sig_bi[3] = 1;
-+		break;
-+	case	1:
-+		sig_bi[0] = 1;
-+		sig_bi[1] = 1;
-+		sig_bi[2] = 1;
-+		sig_bi[3] = 1;
-+		break;
-+	case	2:
-+		sig_bi[0] = 0;
-+		sig_bi[1] = 1;
-+		sig_bi[2] = 0;
-+		sig_bi[3] = 1;
-+		break;
-+	case	3:
-+		sig_bi[0] = 0;
-+		sig_bi[1] = 1;
-+		sig_bi[2] = 1;
-+		sig_bi[3] = 1;
-+		break;
-+	case	4:
-+		sig_bi[0] = 1;
-+		sig_bi[1] = 0;
-+		sig_bi[2] = 0;
-+		sig_bi[3] = 1;
-+		break;
-+	case	5:
-+		sig_bi[0] = 1;
-+		sig_bi[1] = 0;
-+		sig_bi[2] = 1;
-+		sig_bi[3] = 1;
-+		break;
-+	case	6:
-+		sig_bi[0] = 0;
-+		sig_bi[1] = 0;
-+		sig_bi[2] = 0;
-+		sig_bi[3] = 1;
-+		break;
-+	case	7:
-+		sig_bi[0] = 0;
-+		sig_bi[1] = 0;
-+		sig_bi[2] = 1;
-+		sig_bi[3] = 1;
-+		break;
-+	}
-+	/*Reserved bit*/
-+	sig_bi[4] = 0;
-+
-+	/*	Length Field*/
-+	for (i = 0; i < 12; i++)
-+		sig_bi[i + 5] = (LENGTH >> i) & 1;
-+
-+	/* Parity Bit*/
-+	sig_bi[17] = 0;
-+	for (i = 0; i < 17; i++)
-+		sig_bi[17] = sig_bi[17] + sig_bi[i];
-+
-+	sig_bi[17] %= 2;
-+
-+	/*	Tail Field*/
-+	for (i = 18; i < 24; i++)
-+		sig_bi[i] = 0;
-+
-+	/* dump_buf(sig_bi,24);*/
-+	_rtw_memset(pPMacTxInfo->LSIG, 0, 3);
-+	ByteToBit(pPMacTxInfo->LSIG, (bool *)sig_bi, 3);
-+}
-+
-+
-+void CRC8_generator(
-+	bool	*out,
-+	bool	*in,
-+	u8	in_size
-+)
-+{
-+	u8 i = 0;
-+	bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1};
-+
-+	for (i = 0; i < in_size; i++) { /* take one's complement and bit reverse*/
-+		temp = in[i] ^ reg[7];
-+		reg[7]	= reg[6];
-+		reg[6]	= reg[5];
-+		reg[5]	= reg[4];
-+		reg[4]	= reg[3];
-+		reg[3]	= reg[2];
-+		reg[2]	= reg[1] ^ temp;
-+		reg[1]	= reg[0] ^ temp;
-+		reg[0]	= temp;
-+	}
-+	for (i = 0; i < 8; i++)/* take one's complement and bit reverse*/
-+		out[i] = reg[7 - i] ^ 1;
-+}
-+
-+/*/================================================================================
-+	HT-SIG1	MCS	CW	Length		24BIT + 24BIT
-+			7b	1b	16b
-+	HT-SIG2	Smoothing	Not sounding	Rsvd		AGG	STBC	FEC	SGI	N_ELTF	CRC	Tail
-+			1b			1b			1b		1b	2b		1b	1b	2b		8b	6b
-+================================================================================*/
-+void HT_SIG_generator(
-+	PRT_PMAC_TX_INFO	pPMacTxInfo,
-+	PRT_PMAC_PKT_INFO	pPMacPktInfo
-+)
-+{
-+	u32 i;
-+	bool sig_bi[48] = {0}, crc8[8] = {0};
-+	/*	MCS Field*/
-+	for (i = 0; i < 7; i++)
-+		sig_bi[i] = (pPMacPktInfo->MCS >> i) & 0x1;
-+	/*	Packet BW Setting*/
-+	sig_bi[7] = pPMacTxInfo->BandWidth;
-+	/*	HT-Length Field*/
-+	for (i = 0; i < 16; i++)
-+		sig_bi[i + 8] = (pPMacTxInfo->PacketLength >> i) & 0x1;
-+	/*	Smoothing;	1->allow smoothing*/
-+	sig_bi[24] = 1;
-+	/*Not Sounding*/
-+	sig_bi[25] = 1 - pPMacTxInfo->NDP_sound;
-+	/*Reserved bit*/
-+	sig_bi[26] = 1;
-+	/*/Aggregate*/
-+	sig_bi[27] = 0;
-+	/*STBC Field*/
-+	if (pPMacTxInfo->bSTBC) {
-+		sig_bi[28] = 1;
-+		sig_bi[29] = 0;
-+	} else {
-+		sig_bi[28] = 0;
-+		sig_bi[29] = 0;
-+	}
-+	/*Advance Coding,	0: BCC, 1: LDPC*/
-+	sig_bi[30] = pPMacTxInfo->bLDPC;
-+	/* Short GI*/
-+	sig_bi[31] = pPMacTxInfo->bSGI;
-+	/* N_ELTFs*/
-+	if (pPMacTxInfo->NDP_sound == FALSE) {
-+		sig_bi[32]	= 0;
-+		sig_bi[33]	= 0;
-+	} else {
-+		int	N_ELTF = pPMacTxInfo->Ntx - pPMacPktInfo->Nss;
-+
-+		for (i = 0; i < 2; i++)
-+			sig_bi[32 + i] = (N_ELTF >> i) % 2;
-+	}
-+	/*	CRC-8*/
-+	CRC8_generator(crc8, sig_bi, 34);
-+
-+	for (i = 0; i < 8; i++)
-+		sig_bi[34 + i] = crc8[i];
-+
-+	/*Tail*/
-+	for (i = 42; i < 48; i++)
-+		sig_bi[i] = 0;
-+
-+	_rtw_memset(pPMacTxInfo->HT_SIG, 0, 6);
-+	ByteToBit(pPMacTxInfo->HT_SIG, sig_bi, 6);
-+}
-+
-+
-+/*======================================================================================
-+	VHT-SIG-A1
-+	BW	Reserved	STBC	G_ID	SU_Nsts	P_AID	TXOP_PS_NOT_ALLOW	Reserved
-+	2b	1b			1b		6b	3b	9b		1b		2b					1b
-+	VHT-SIG-A2
-+	SGI	SGI_Nsym	SU/MU coding	LDPC_Extra	SU_NCS	Beamformed	Reserved	CRC	Tail
-+	1b	1b			1b				1b			4b		1b			1b			8b	6b
-+======================================================================================*/
-+void VHT_SIG_A_generator(
-+	PRT_PMAC_TX_INFO	pPMacTxInfo,
-+	PRT_PMAC_PKT_INFO	pPMacPktInfo)
-+{
-+	u32 i;
-+	bool sig_bi[48], crc8[8];
-+
-+	_rtw_memset(sig_bi, 0, 48);
-+	_rtw_memset(crc8, 0, 8);
-+
-+	/*	BW Setting*/
-+	for (i = 0; i < 2; i++)
-+		sig_bi[i] = (pPMacTxInfo->BandWidth >> i) & 0x1;
-+	/* Reserved Bit*/
-+	sig_bi[2] = 1;
-+	/*STBC Field*/
-+	sig_bi[3] = pPMacTxInfo->bSTBC;
-+	/*Group ID: Single User->A value of 0 or 63 indicates an SU PPDU. */
-+	for (i = 0; i < 6; i++)
-+		sig_bi[4 + i] = 0;
-+	/*	N_STS/Partial AID*/
-+	for (i = 0; i < 12; i++) {
-+		if (i < 3)
-+			sig_bi[10 + i] = ((pPMacPktInfo->Nsts - 1) >> i) & 0x1;
-+		else
-+			sig_bi[10 + i] = 0;
-+	}
-+	/*TXOP_PS_NOT_ALLPWED*/
-+	sig_bi[22]	= 0;
-+	/*Reserved Bits*/
-+	sig_bi[23]	= 1;
-+	/*Short GI*/
-+	sig_bi[24] = pPMacTxInfo->bSGI;
-+	if (pPMacTxInfo->bSGI > 0 && (pPMacPktInfo->N_sym % 10) == 9)
-+		sig_bi[25] = 1;
-+	else
-+		sig_bi[25] = 0;
-+	/* SU/MU[0] Coding*/
-+	sig_bi[26] = pPMacTxInfo->bLDPC;	/*	0:BCC, 1:LDPC		*/
-+	sig_bi[27] = pPMacPktInfo->SIGA2B3;	/*/	Record Extra OFDM Symols is added or not when LDPC is used*/
-+	/*SU MCS/MU[1-3] Coding*/
-+	for (i = 0; i < 4; i++)
-+		sig_bi[28 + i] = (pPMacPktInfo->MCS >> i) & 0x1;
-+	/*SU Beamform */
-+	sig_bi[32] = 0;	/*packet.TXBF_en;*/
-+	/*Reserved Bit*/
-+	sig_bi[33] = 1;
-+	/*CRC-8*/
-+	CRC8_generator(crc8, sig_bi, 34);
-+	for (i = 0; i < 8; i++)
-+		sig_bi[34 + i]	= crc8[i];
-+	/*Tail*/
-+	for (i = 42; i < 48; i++)
-+		sig_bi[i] = 0;
-+
-+	_rtw_memset(pPMacTxInfo->VHT_SIG_A, 0, 6);
-+	ByteToBit(pPMacTxInfo->VHT_SIG_A, sig_bi, 6);
-+}
-+
-+/*======================================================================================
-+	VHT-SIG-B
-+	Length				Resesrved	Trail
-+	17/19/21 BIT		3/2/2 BIT	6b
-+======================================================================================*/
-+void VHT_SIG_B_generator(
-+	PRT_PMAC_TX_INFO	pPMacTxInfo)
-+{
-+	bool sig_bi[32], crc8_bi[8];
-+	u32 i, len, res, tail = 6, total_len, crc8_in_len;
-+	u32 sigb_len;
-+
-+	_rtw_memset(sig_bi, 0, 32);
-+	_rtw_memset(crc8_bi, 0, 8);
-+
-+	/*Sounding Packet*/
-+	if (pPMacTxInfo->NDP_sound == 1) {
-+		if (pPMacTxInfo->BandWidth == 0) {
-+			bool sigb_temp[26] = {0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
-+
-+			_rtw_memcpy(sig_bi, sigb_temp, 26);
-+		} else if (pPMacTxInfo->BandWidth == 1) {
-+			bool sigb_temp[27] = {1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0};
-+
-+			_rtw_memcpy(sig_bi, sigb_temp, 27);
-+		} else if (pPMacTxInfo->BandWidth == 2) {
-+			bool sigb_temp[29] = {0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
-+
-+			_rtw_memcpy(sig_bi, sigb_temp, 29);
-+		}
-+	} else {	/* Not NDP Sounding*/
-+		bool *sigb_temp[29] = {0};
-+
-+		if (pPMacTxInfo->BandWidth == 0) {
-+			len = 17;
-+			res = 3;
-+		} else if (pPMacTxInfo->BandWidth == 1) {
-+			len = 19;
-+			res = 2;
-+		} else if (pPMacTxInfo->BandWidth == 2) {
-+			len	= 21;
-+			res	= 2;
-+		} else {
-+			len	= 21;
-+			res	= 2;
-+		}
-+		total_len = len + res + tail;
-+		crc8_in_len = len + res;
-+
-+		/*Length Field*/
-+		sigb_len = (pPMacTxInfo->PacketLength + 3) >> 2;
-+
-+		for (i = 0; i < len; i++)
-+			sig_bi[i] = (sigb_len >> i) & 0x1;
-+		/*Reserved Field*/
-+		for (i = 0; i < res; i++)
-+			sig_bi[len + i] = 1;
-+		/* CRC-8*/
-+		CRC8_generator(crc8_bi, sig_bi, crc8_in_len);
-+
-+		/* Tail */
-+		for (i = 0; i < tail; i++)
-+			sig_bi[len + res + i] = 0;
-+	}
-+
-+	_rtw_memset(pPMacTxInfo->VHT_SIG_B, 0, 4);
-+	ByteToBit(pPMacTxInfo->VHT_SIG_B, sig_bi, 4);
-+
-+	pPMacTxInfo->VHT_SIG_B_CRC = 0;
-+	ByteToBit(&(pPMacTxInfo->VHT_SIG_B_CRC), crc8_bi, 1);
-+}
-+
-+/*=======================
-+ VHT Delimiter
-+=======================*/
-+void VHT_Delimiter_generator(
-+	PRT_PMAC_TX_INFO	pPMacTxInfo
-+)
-+{
-+	bool sig_bi[32] = {0}, crc8[8] = {0};
-+	u32 crc8_in_len = 16;
-+	u32 PacketLength = pPMacTxInfo->PacketLength;
-+	int j;
-+
-+	/* Delimiter[0]: EOF*/
-+	sig_bi[0] = 1;
-+	/* Delimiter[1]: Reserved*/
-+	sig_bi[1] = 0;
-+	/* Delimiter[3:2]: MPDU Length High*/
-+	sig_bi[2] = ((PacketLength - 4) >> 12) % 2;
-+	sig_bi[3] = ((PacketLength - 4) >> 13) % 2;
-+	/* Delimiter[15:4]: MPDU Length Low*/
-+	for (j = 4; j < 16; j++)
-+		sig_bi[j] = ((PacketLength - 4) >> (j - 4)) % 2;
-+	CRC8_generator(crc8, sig_bi, crc8_in_len);
-+	for (j = 16; j < 24; j++) /* Delimiter[23:16]: CRC 8*/
-+		sig_bi[j] = crc8[j - 16];
-+	for (j = 24; j < 32; j++) /* Delimiter[31:24]: Signature ('4E' in Hex, 78 in Dec)*/
-+		sig_bi[j]	= (78 >> (j - 24)) % 2;
-+
-+	_rtw_memset(pPMacTxInfo->VHT_Delimiter, 0, 4);
-+	ByteToBit(pPMacTxInfo->VHT_Delimiter, sig_bi, 4);
-+}
-+
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/core/rtw_odm.c b/drivers/staging/rtl8723cs/core/rtw_odm.c
-new file mode 100644
-index 000000000000..9651d4fdd045
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_odm.c
-@@ -0,0 +1,600 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <rtw_odm.h>
-+#include <hal_data.h>
-+
-+u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
-+	struct dm_struct *podmpriv = &pHalData->odmpriv;
-+	u32 result = 0;
-+
-+	switch (ops) {
-+	case HAL_PHYDM_DIS_ALL_FUNC:
-+		podmpriv->support_ability = DYNAMIC_FUNC_DISABLE;
-+		halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, DYNAMIC_FUNC_DISABLE);
-+		break;
-+	case HAL_PHYDM_FUNC_SET:
-+		podmpriv->support_ability |= ability;
-+		break;
-+	case HAL_PHYDM_FUNC_CLR:
-+		podmpriv->support_ability &= ~(ability);
-+		break;
-+	case HAL_PHYDM_ABILITY_BK:
-+		/* dm flag backup*/
-+		podmpriv->bk_support_ability = podmpriv->support_ability;
-+		pHalData->bk_rf_ability = halrf_cmn_info_get(podmpriv, HALRF_CMNINFO_ABILITY);
-+		break;
-+	case HAL_PHYDM_ABILITY_RESTORE:
-+		/* restore dm flag */
-+		podmpriv->support_ability = podmpriv->bk_support_ability;
-+		halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, pHalData->bk_rf_ability);
-+		break;
-+	case HAL_PHYDM_ABILITY_SET:
-+		podmpriv->support_ability = ability;
-+		break;
-+	case HAL_PHYDM_ABILITY_GET:
-+		result = podmpriv->support_ability;
-+		break;
-+	}
-+	return result;
-+}
-+
-+/* set ODM_CMNINFO_IC_TYPE based on chip_type */
-+void rtw_odm_init_ic_type(_adapter *adapter)
-+{
-+	struct dm_struct *odm = adapter_to_phydm(adapter);
-+	u32 ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter));
-+
-+	rtw_warn_on(!ic_type);
-+
-+	odm_cmn_info_init(odm, ODM_CMNINFO_IC_TYPE, ic_type);
-+}
-+
-+void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
-+{
-+	RTW_PRINT_SEL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n");
-+}
-+
-+#define RTW_ADAPTIVITY_EN_DISABLE 0
-+#define RTW_ADAPTIVITY_EN_ENABLE 1
-+
-+void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
-+{
-+	struct registry_priv *regsty = &adapter->registrypriv;
-+
-+	RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_EN_");
-+
-+	if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE)
-+		_RTW_PRINT_SEL(sel, "DISABLE\n");
-+	else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
-+		_RTW_PRINT_SEL(sel, "ENABLE\n");
-+	else
-+		_RTW_PRINT_SEL(sel, "INVALID\n");
-+}
-+
-+#define RTW_ADAPTIVITY_MODE_NORMAL 0
-+#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
-+
-+void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)
-+{
-+	struct registry_priv *regsty = &adapter->registrypriv;
-+
-+	RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_MODE_");
-+
-+	if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL)
-+		_RTW_PRINT_SEL(sel, "NORMAL\n");
-+	else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE)
-+		_RTW_PRINT_SEL(sel, "CARRIER_SENSE\n");
-+	else
-+		_RTW_PRINT_SEL(sel, "INVALID\n");
-+}
-+
-+void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter)
-+{
-+	rtw_odm_adaptivity_ver_msg(sel, adapter);
-+	rtw_odm_adaptivity_en_msg(sel, adapter);
-+	rtw_odm_adaptivity_mode_msg(sel, adapter);
-+}
-+
-+bool rtw_odm_adaptivity_needed(_adapter *adapter)
-+{
-+	struct registry_priv *regsty = &adapter->registrypriv;
-+	bool ret = _FALSE;
-+
-+	if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
-+		ret = _TRUE;
-+
-+	return ret;
-+}
-+
-+void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
-+{
-+	struct dm_struct *odm = adapter_to_phydm(adapter);
-+
-+	rtw_odm_adaptivity_config_msg(sel, adapter);
-+
-+	RTW_PRINT_SEL(sel, "%10s %16s\n"
-+		, "th_l2h_ini", "th_edcca_hl_diff");
-+	RTW_PRINT_SEL(sel, "0x%-8x %-16d\n"
-+		, (u8)odm->th_l2h_ini
-+		, odm->th_edcca_hl_diff
-+	);
-+}
-+
-+void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff)
-+{
-+	struct dm_struct *odm = adapter_to_phydm(adapter);
-+
-+	odm->th_l2h_ini = th_l2h_ini;
-+	odm->th_edcca_hl_diff = th_edcca_hl_diff;
-+}
-+
-+void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
-+{
-+	struct dm_struct *odm = adapter_to_phydm(adapter);
-+
-+	RTW_PRINT_SEL(sel, "rx_rate = %s, rssi_a = %d(%%), rssi_b = %d(%%)\n",
-+		      HDATA_RATE(odm->rx_rate), odm->rssi_a, odm->rssi_b);
-+}
-+
-+
-+void rtw_odm_acquirespinlock(_adapter *adapter,	enum rt_spinlock_type type)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
-+	_irqL irqL;
-+
-+	switch (type) {
-+	case RT_IQK_SPINLOCK:
-+		_enter_critical_bh(&pHalData->IQKSpinLock, &irqL);
-+	default:
-+		break;
-+	}
-+}
-+
-+void rtw_odm_releasespinlock(_adapter *adapter,	enum rt_spinlock_type type)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
-+	_irqL irqL;
-+
-+	switch (type) {
-+	case RT_IQK_SPINLOCK:
-+		_exit_critical_bh(&pHalData->IQKSpinLock, &irqL);
-+	default:
-+		break;
-+	}
-+}
-+
-+s16 rtw_odm_get_tx_power_mbm(struct dm_struct *dm, u8 rfpath, u8 rate, u8 bw, u8 cch)
-+{
-+	return phy_get_txpwr_single_mbm(dm->adapter, rfpath, mgn_rate_to_rs(rate), rate, bw, cch, 0, 0, 0, NULL);
-+}
-+
-+#ifdef CONFIG_DFS_MASTER
-+inline void rtw_odm_radar_detect_reset(_adapter *adapter)
-+{
-+	phydm_radar_detect_reset(adapter_to_phydm(adapter));
-+}
-+
-+inline void rtw_odm_radar_detect_disable(_adapter *adapter)
-+{
-+	phydm_radar_detect_disable(adapter_to_phydm(adapter));
-+}
-+
-+/* called after ch, bw is set */
-+inline void rtw_odm_radar_detect_enable(_adapter *adapter)
-+{
-+	phydm_radar_detect_enable(adapter_to_phydm(adapter));
-+}
-+
-+inline BOOLEAN rtw_odm_radar_detect(_adapter *adapter)
-+{
-+	return phydm_radar_detect(adapter_to_phydm(adapter));
-+}
-+
-+static enum phydm_dfs_region_domain _rtw_dfs_regd_to_phydm[] = {
-+	[RTW_DFS_REGD_NONE]	= PHYDM_DFS_DOMAIN_UNKNOWN,
-+	[RTW_DFS_REGD_FCC]	= PHYDM_DFS_DOMAIN_FCC,
-+	[RTW_DFS_REGD_MKK]	= PHYDM_DFS_DOMAIN_MKK,
-+	[RTW_DFS_REGD_ETSI]	= PHYDM_DFS_DOMAIN_ETSI,
-+};
-+
-+#define rtw_dfs_regd_to_phydm(region) (((region) >= RTW_DFS_REGD_NUM) ? _rtw_dfs_regd_to_phydm[RTW_DFS_REGD_NONE] : _rtw_dfs_regd_to_phydm[(region)])
-+
-+void rtw_odm_update_dfs_region(struct dvobj_priv *dvobj)
-+{
-+	odm_cmn_info_init(dvobj_to_phydm(dvobj), ODM_CMNINFO_DFS_REGION_DOMAIN, rtw_dfs_regd_to_phydm(rtw_rfctl_get_dfs_domain(dvobj_to_rfctl(dvobj))));
-+}
-+
-+inline u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj)
-+{
-+	return phydm_dfs_polling_time(dvobj_to_phydm(dvobj));
-+}
-+#endif /* CONFIG_DFS_MASTER */
-+
-+void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys)
-+{
-+#ifndef DBG_RX_PHYSTATUS_CHINFO
-+#define DBG_RX_PHYSTATUS_CHINFO 0
-+#endif
-+
-+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
-+	_adapter *adapter = rframe->u.hdr.adapter;
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+	struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;
-+	u8 *wlanhdr = get_recvframe_data(rframe);
-+
-+	if (phydm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
-+		/*
-+		* 8723D:
-+		* type_0(CCK)
-+		*     l_rxsc
-+		*         is filled with primary channel SC, not real rxsc.
-+		*         0:LSC, 1:USC
-+		* type_1(OFDM)
-+		*     rf_mode
-+		*         RF bandwidth when RX
-+		*     l_rxsc(legacy), ht_rxsc
-+		*         see below RXSC N-series
-+		* type_2(Not used)
-+		*/
-+		/*
-+		* 8821C, 8822B:
-+		* type_0(CCK)
-+		*     l_rxsc
-+		*         is filled with primary channel SC, not real rxsc.
-+		*         0:LSC, 1:USC
-+		* type_1(OFDM)
-+		*     rf_mode
-+		*         RF bandwidth when RX
-+		*     l_rxsc(legacy), ht_rxsc
-+		*         see below RXSC AC-series
-+		* type_2(Not used)
-+		*/
-+
-+		if ((*phys & 0xf) == 0) {
-+			struct phy_sts_rpt_jgr2_type0 *phys_t0 = (struct phy_sts_rpt_jgr2_type0 *)phys;
-+
-+			if (DBG_RX_PHYSTATUS_CHINFO) {
-+				RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u)\n"
-+					, *phys & 0xf
-+					, MAC_ARG(get_ta(wlanhdr))
-+					, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
-+					, HDATA_RATE(attrib->data_rate)
-+					, phys_t0->band, phys_t0->channel, phys_t0->rxsc
-+				);
-+			}
-+
-+		} else if ((*phys & 0xf) == 1) {
-+			struct phy_sts_rpt_jgr2_type1 *phys_t1 = (struct phy_sts_rpt_jgr2_type1 *)phys;
-+			u8 rxsc = (attrib->data_rate > DESC_RATE11M && attrib->data_rate < DESC_RATEMCS0) ? phys_t1->l_rxsc : phys_t1->ht_rxsc;
-+			u8 pkt_cch = 0;
-+			u8 pkt_bw = CHANNEL_WIDTH_20;
-+
-+			#if	ODM_IC_11N_SERIES_SUPPORT
-+			if (phydm->support_ic_type & ODM_IC_11N_SERIES) {
-+				/* RXSC N-series */
-+				#define RXSC_DUP	0
-+				#define RXSC_LSC	1
-+				#define RXSC_USC	2
-+				#define RXSC_40M	3
-+
-+				static const s8 cch_offset_by_rxsc[4] = {0, -2, 2, 0};
-+
-+				if (phys_t1->rf_mode == 0) {
-+					pkt_cch = phys_t1->channel;
-+					pkt_bw = CHANNEL_WIDTH_20;
-+				} else if (phys_t1->rf_mode == 1) {
-+					if (rxsc == RXSC_LSC || rxsc == RXSC_USC) {
-+						pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
-+						pkt_bw = CHANNEL_WIDTH_20;
-+					} else if (rxsc == RXSC_40M) {
-+						pkt_cch = phys_t1->channel;
-+						pkt_bw = CHANNEL_WIDTH_40;
-+					}
-+				} else
-+					rtw_warn_on(1);
-+
-+				goto type1_end;
-+			}
-+			#endif /* ODM_IC_11N_SERIES_SUPPORT */
-+
-+			#if	ODM_IC_11AC_SERIES_SUPPORT
-+			if (phydm->support_ic_type & ODM_IC_11AC_SERIES) {
-+				/* RXSC AC-series */
-+				#define RXSC_DUP			0 /* 0: RX from all SC of current rf_mode */
-+
-+				#define RXSC_LL20M_OF_160M	8 /* 1~8: RX from 20MHz SC */
-+				#define RXSC_L20M_OF_160M	6
-+				#define RXSC_L20M_OF_80M	4
-+				#define RXSC_L20M_OF_40M	2
-+				#define RXSC_U20M_OF_40M	1
-+				#define RXSC_U20M_OF_80M	3
-+				#define RXSC_U20M_OF_160M	5
-+				#define RXSC_UU20M_OF_160M	7
-+
-+				#define RXSC_L40M_OF_160M	12 /* 9~12: RX from 40MHz SC */
-+				#define RXSC_L40M_OF_80M	10
-+				#define RXSC_U40M_OF_80M	9
-+				#define RXSC_U40M_OF_160M	11
-+
-+				#define RXSC_L80M_OF_160M	14 /* 13~14: RX from 80MHz SC */
-+				#define RXSC_U80M_OF_160M	13
-+
-+				static const s8 cch_offset_by_rxsc[15] = {0, 2, -2, 6, -6, 10, -10, 14, -14, 4, -4, 12, -12, 8, -8};
-+
-+				if (phys_t1->rf_mode == 0) {
-+					/* RF 20MHz */
-+					pkt_cch = phys_t1->channel;
-+					pkt_bw = CHANNEL_WIDTH_20;
-+					goto type1_end;
-+				}
-+
-+				if (rxsc == 0) {
-+					/* RF and RX with same BW */
-+					if (attrib->data_rate >= DESC_RATEMCS0) {
-+						pkt_cch = phys_t1->channel;
-+						pkt_bw = phys_t1->rf_mode;
-+					}
-+					goto type1_end;
-+				}
-+
-+				if ((phys_t1->rf_mode == 1 && rxsc >= 1 && rxsc <= 2) /* RF 40MHz, RX 20MHz */
-+					|| (phys_t1->rf_mode == 2 && rxsc >= 1 && rxsc <= 4) /* RF 80MHz, RX 20MHz */
-+					|| (phys_t1->rf_mode == 3 && rxsc >= 1 && rxsc <= 8) /* RF 160MHz, RX 20MHz */
-+				) {
-+					pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
-+					pkt_bw = CHANNEL_WIDTH_20;
-+				} else if ((phys_t1->rf_mode == 2 && rxsc >= 9 && rxsc <= 10) /* RF 80MHz, RX 40MHz */
-+					|| (phys_t1->rf_mode == 3 && rxsc >= 9 && rxsc <= 12) /* RF 160MHz, RX 40MHz */
-+				) {
-+					if (attrib->data_rate >= DESC_RATEMCS0) {
-+						pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
-+						pkt_bw = CHANNEL_WIDTH_40;
-+					}
-+				} else if ((phys_t1->rf_mode == 3 && rxsc >= 13 && rxsc <= 14) /* RF 160MHz, RX 80MHz */
-+				) {
-+					if (attrib->data_rate >= DESC_RATEMCS0) {
-+						pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
-+						pkt_bw = CHANNEL_WIDTH_80;
-+					}
-+				} else
-+					rtw_warn_on(1);
-+
-+			}
-+			#endif /* ODM_IC_11AC_SERIES_SUPPORT */
-+
-+type1_end:
-+			if (DBG_RX_PHYSTATUS_CHINFO) {
-+				RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, rf_mode:%u, l_rxsc:%u, ht_rxsc:%u) => %u,%u\n"
-+					, *phys & 0xf
-+					, MAC_ARG(get_ta(wlanhdr))
-+					, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
-+					, HDATA_RATE(attrib->data_rate)
-+					, phys_t1->band, phys_t1->channel, phys_t1->rf_mode, phys_t1->l_rxsc, phys_t1->ht_rxsc
-+					, pkt_cch, pkt_bw
-+				);
-+			}
-+
-+			/* for now, only return cneter channel of 20MHz packet */
-+			if (pkt_cch && pkt_bw == CHANNEL_WIDTH_20)
-+				attrib->ch = pkt_cch;
-+
-+		} else {
-+			struct phy_sts_rpt_jgr2_type2 *phys_t2 = (struct phy_sts_rpt_jgr2_type2 *)phys;
-+
-+			if (DBG_RX_PHYSTATUS_CHINFO) {
-+				RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u, ht_rxsc:%u)\n"
-+					, *phys & 0xf
-+					, MAC_ARG(get_ta(wlanhdr))
-+					, is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
-+					, HDATA_RATE(attrib->data_rate)
-+					, phys_t2->band, phys_t2->channel, phys_t2->l_rxsc, phys_t2->ht_rxsc
-+				);
-+			}
-+		}
-+	}
-+#endif /* (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) */
-+
-+}
-+
-+#if defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG)
-+void
-+debug_DACK(
-+	struct dm_struct *dm
-+)
-+{
-+	//P_PHYDM_FUNC dm;
-+	//dm = &(SysMib.ODM.Phydm);
-+	//PIQK_OFFLOAD_PARM pIQK_info;
-+	//pIQK_info= &(SysMib.ODM.IQKParm);
-+	u8 i;
-+	u32 temp1, temp2, temp3;
-+
-+	temp1 = odm_get_bb_reg(dm, 0x1860, bMaskDWord);
-+	temp2 = odm_get_bb_reg(dm, 0x4160, bMaskDWord);
-+	temp3 = odm_get_bb_reg(dm, 0x9b4, bMaskDWord);
-+
-+	odm_set_bb_reg(dm, 0x9b4, bMaskDWord, 0xdb66db00);
-+
-+	//pathA
-+	odm_set_bb_reg(dm, 0x1830, BIT(30), 0x0);
-+	odm_set_bb_reg(dm, 0x1860, 0xfc000000, 0x3c);
-+
-+	RTW_INFO("path A i\n");
-+	//i
-+	for (i = 0; i < 0xf; i++) {
-+		odm_set_bb_reg(dm, 0x18b0, 0xf0000000, i);
-+		RTW_INFO("[0][0][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000));
-+		//pIQK_info->msbk_d[0][0][i] = (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000);
-+	}
-+	RTW_INFO("path A q\n");
-+	//q
-+	for (i = 0; i < 0xf; i++) {
-+		odm_set_bb_reg(dm, 0x18cc, 0xf0000000, i);
-+		RTW_INFO("[0][1][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000));
-+		//pIQK_info->msbk_d[0][1][i] = (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000);
-+	}
-+	//pathB
-+	odm_set_bb_reg(dm, 0x4130, BIT(30), 0x0);
-+	odm_set_bb_reg(dm, 0x4160, 0xfc000000, 0x3c);
-+
-+	RTW_INFO("\npath B i\n");
-+	//i
-+	for (i = 0; i < 0xf; i++) {
-+		odm_set_bb_reg(dm, 0x41b0, 0xf0000000, i);
-+		RTW_INFO("[1][0][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x4510,0x7fc0000));
-+		//pIQK_info->msbk_d[1][0][i] = (u16)odm_get_bb_reg(dm,0x2810,0x7fc0000);
-+	}
-+	RTW_INFO("path B q\n");
-+	//q
-+	for (i = 0; i < 0xf; i++) {
-+		odm_set_bb_reg(dm, 0x41cc, 0xf0000000, i);
-+		RTW_INFO("[1][1][%d] = 0x%08x\n", i, (u16)odm_get_bb_reg(dm,0x453c,0x7fc0000));
-+		//pIQK_info->msbk_d[1][1][i] = (u16)odm_get_bb_reg(dm,0x283c,0x7fc0000);
-+	}
-+
-+	//restore to normal
-+	odm_set_bb_reg(dm, 0x1830, BIT(30), 0x1);
-+	odm_set_bb_reg(dm, 0x4130, BIT(30), 0x1);
-+	odm_set_bb_reg(dm, 0x1860, bMaskDWord, temp1);
-+	odm_set_bb_reg(dm, 0x4160, bMaskDWord, temp2);
-+	odm_set_bb_reg(dm, 0x9b4, bMaskDWord, temp3);
-+
-+
-+}
-+
-+void
-+debug_IQK(
-+	struct dm_struct *dm,
-+	IN	u8 idx,
-+	IN	u8 path
-+)
-+{
-+	u8 i, ch;
-+	u32 tmp;
-+	u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
-+
-+	RTW_INFO("idx = %d, path = %d\n", idx, path);
-+
-+	odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0x8 | path << 1);
-+
-+	if (idx == TX_IQK) {//TXCFIR
-+		odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x3);
-+	} else {//RXCFIR
-+		odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x1);		
-+	}
-+	odm_set_bb_reg(dm, R_0x1bd4, BIT(21), 0x1);
-+	odm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10);
-+	for (i = 0; i <= 16; i++) {
-+		odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 | i << 2);
-+		tmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
-+		RTW_INFO("iqk_cfir_real[%d][%d][%d] = 0x%x\n", path, idx, i, ((tmp & 0x0fff0000) >> 16));
-+		//iqk_info->iqk_cfir_real[ch][path][idx][i] =
-+		//				(tmp & 0x0fff0000) >> 16;
-+		RTW_INFO("iqk_cfir_imag[%d][%d][%d] = 0x%x\n", path, idx, i, (tmp & 0x0fff));
-+		//iqk_info->iqk_cfir_imag[ch][path][idx][i] = tmp & 0x0fff;		
-+	}
-+	odm_set_bb_reg(dm, R_0x1b20, BIT(31) | BIT(30), 0x0);
-+	//odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
-+}
-+
-+__odm_func__ void
-+debug_information_8822c(
-+	struct dm_struct *dm)
-+{
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+
-+	u32  reg_rf18;
-+
-+	if (odm_get_bb_reg(dm, R_0x1e7c, BIT(30)))
-+		dpk_info->is_tssi_mode = true;
-+	else
-+		dpk_info->is_tssi_mode = false;
-+
-+	reg_rf18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK);
-+
-+	dpk_info->dpk_band = (u8)((reg_rf18 & BIT(16)) >> 16); /*0/1:G/A*/
-+	dpk_info->dpk_ch = (u8)reg_rf18 & 0xff;
-+	dpk_info->dpk_bw = (u8)((reg_rf18 & 0x3000) >> 12); /*3/2/1:20/40/80*/
-+
-+	RTW_INFO("[DPK] TSSI/ Band/ CH/ BW = %d / %s / %d / %s\n",
-+	       dpk_info->is_tssi_mode, dpk_info->dpk_band == 0 ? "2G" : "5G",
-+	       dpk_info->dpk_ch,
-+	       dpk_info->dpk_bw == 3 ? "20M" : (dpk_info->dpk_bw == 2 ? "40M" : "80M"));
-+}
-+
-+extern void _dpk_get_coef_8822c(void *dm_void, u8 path);
-+
-+__odm_func__ void
-+debug_reload_data_8822c(
-+	void *dm_void)
-+{	
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+
-+	u8 path;
-+	u32 u32tmp;
-+
-+	debug_information_8822c(dm);
-+
-+	for (path = 0; path < DPK_RF_PATH_NUM_8822C; path++) {
-+
-+		RTW_INFO("[DPK] Reload path: 0x%x\n", path);
-+
-+		odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0x8 | (path << 1));
-+
-+		 /*txagc bnd*/
-+		if (dpk_info->dpk_band == 0x0)
-+			u32tmp = odm_get_bb_reg(dm, R_0x1b60, MASKDWORD);
-+		else
-+			u32tmp = odm_get_bb_reg(dm, R_0x1b60, MASKDWORD);
-+
-+ 		RTW_INFO("[DPK] txagc bnd = 0x%08x\n", u32tmp);
-+
-+		u32tmp = odm_get_bb_reg(dm, R_0x1b64, MASKBYTE3);
-+		RTW_INFO("[DPK] dpk_txagc = 0x%08x\n", u32tmp);
-+		
-+		//debug_coef_write_8822c(dm, path, dpk_info->dpk_path_ok & BIT(path) >> path);
-+		_dpk_get_coef_8822c(dm, path);
-+
-+		//debug_one_shot_8822c(dm, path, DPK_ON);
-+
-+		odm_set_bb_reg(dm, R_0x1b00, 0x0000000f, 0xc);
-+
-+		if (path == RF_PATH_A)
-+			u32tmp = odm_get_bb_reg(dm, R_0x1b04, 0x0fffffff);
-+		else 
-+			u32tmp = odm_get_bb_reg(dm, R_0x1b5c, 0x0fffffff);
-+
-+		RTW_INFO("[DPK] dpk_gs = 0x%08x\n", u32tmp);
-+		
-+	}
-+}
-+
-+void odm_lps_pg_debug_8822c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	debug_DACK(dm);
-+	debug_IQK(dm, TX_IQK, RF_PATH_A);
-+	debug_IQK(dm, RX_IQK, RF_PATH_A);
-+	debug_IQK(dm, TX_IQK, RF_PATH_B);
-+	debug_IQK(dm, RX_IQK, RF_PATH_B);	
-+	debug_reload_data_8822c(dm);
-+}
-+#endif /* defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG) */
-+
-diff --git a/drivers/staging/rtl8723cs/core/rtw_p2p.c b/drivers/staging/rtl8723cs/core/rtw_p2p.c
-new file mode 100644
-index 000000000000..24372de57a85
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_p2p.c
-@@ -0,0 +1,5017 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_P2P_C_
-+
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_P2P
-+
-+int rtw_p2p_is_channel_list_ok(u8 desired_ch, u8 *ch_list, u8 ch_cnt)
-+{
-+	int found = 0, i = 0;
-+
-+	for (i = 0; i < ch_cnt; i++) {
-+		if (ch_list[i] == desired_ch) {
-+			found = 1;
-+			break;
-+		}
-+	}
-+	return found ;
-+}
-+
-+int is_any_client_associated(_adapter *padapter)
-+{
-+	return padapter->stapriv.asoc_list_cnt ? _TRUE : _FALSE;
-+}
-+
-+static u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	_irqL irqL;
-+	_list	*phead, *plist;
-+	u32 len = 0;
-+	u16 attr_len = 0;
-+	u8 tmplen, *pdata_attr, *pstart, *pcur;
-+	struct sta_info *psta = NULL;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+
-+	pdata_attr = rtw_zmalloc(MAX_P2P_IE_LEN);
-+
-+	if (NULL == pdata_attr) {
-+		RTW_INFO("%s pdata_attr malloc failed\n", __FUNCTION__);
-+		goto _exit;
-+	}
-+
-+	pstart = pdata_attr;
-+	pcur = pdata_attr;
-+
-+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+	phead = &pstapriv->asoc_list;
-+	plist = get_next(phead);
-+
-+	/* look up sta asoc_queue */
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+
-+		plist = get_next(plist);
-+
-+
-+		if (psta->is_p2p_device) {
-+			tmplen = 0;
-+
-+			pcur++;
-+
-+			/* P2P device address */
-+			_rtw_memcpy(pcur, psta->dev_addr, ETH_ALEN);
-+			pcur += ETH_ALEN;
-+
-+			/* P2P interface address */
-+			_rtw_memcpy(pcur, psta->cmn.mac_addr, ETH_ALEN);
-+			pcur += ETH_ALEN;
-+
-+			*pcur = psta->dev_cap;
-+			pcur++;
-+
-+			/* *(u16*)(pcur) = cpu_to_be16(psta->config_methods); */
-+			RTW_PUT_BE16(pcur, psta->config_methods);
-+			pcur += 2;
-+
-+			_rtw_memcpy(pcur, psta->primary_dev_type, 8);
-+			pcur += 8;
-+
-+			*pcur = psta->num_of_secdev_type;
-+			pcur++;
-+
-+			_rtw_memcpy(pcur, psta->secdev_types_list, psta->num_of_secdev_type * 8);
-+			pcur += psta->num_of_secdev_type * 8;
-+
-+			if (psta->dev_name_len > 0) {
-+				/* *(u16*)(pcur) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */
-+				RTW_PUT_BE16(pcur, WPS_ATTR_DEVICE_NAME);
-+				pcur += 2;
-+
-+				/* *(u16*)(pcur) = cpu_to_be16( psta->dev_name_len ); */
-+				RTW_PUT_BE16(pcur, psta->dev_name_len);
-+				pcur += 2;
-+
-+				_rtw_memcpy(pcur, psta->dev_name, psta->dev_name_len);
-+				pcur += psta->dev_name_len;
-+			}
-+
-+
-+			tmplen = (u8)(pcur - pstart);
-+
-+			*pstart = (tmplen - 1);
-+
-+			attr_len += tmplen;
-+
-+			/* pstart += tmplen; */
-+			pstart = pcur;
-+
-+		}
-+
-+
-+	}
-+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+	if (attr_len > 0)
-+		len = rtw_set_p2p_attr_content(pbuf, P2P_ATTR_GROUP_INFO, attr_len, pdata_attr);
-+
-+	rtw_mfree(pdata_attr, MAX_P2P_IE_LEN);
-+
-+_exit:
-+	return len;
-+
-+}
-+
-+static void issue_group_disc_req(struct wifidirect_info *pwdinfo, u8 *da)
-+{
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	unsigned char category = RTW_WLAN_CATEGORY_P2P;/* P2P action frame	 */
-+	u32	p2poui = cpu_to_be32(P2POUI);
-+	u8	oui_subtype = P2P_GO_DISC_REQUEST;
-+	u8	dialogToken = 0;
-+
-+	RTW_INFO("[%s]\n", __FUNCTION__);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	/* Build P2P action frame header */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
-+
-+	/* there is no IE in this P2P action frame */
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+}
-+
-+static void issue_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken)
-+{
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
-+	u8			action = P2P_PUB_ACTION_ACTION;
-+	u32			p2poui = cpu_to_be32(P2POUI);
-+	u8			oui_subtype = P2P_DEVDISC_RESP;
-+	u8 p2pie[8] = { 0x00 };
-+	u32 p2pielen = 0;
-+
-+	RTW_INFO("[%s]\n", __FUNCTION__);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, pwdinfo->device_addr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, pwdinfo->device_addr, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	/* Build P2P public action frame header */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
-+
-+
-+	/* Build P2P IE */
-+	/*	P2P OUI */
-+	p2pielen = 0;
-+	p2pie[p2pielen++] = 0x50;
-+	p2pie[p2pielen++] = 0x6F;
-+	p2pie[p2pielen++] = 0x9A;
-+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+	/* P2P_ATTR_STATUS */
-+	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status);
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &pattrib->pktlen);
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+}
-+
-+static void issue_p2p_provision_resp(struct wifidirect_info *pwdinfo, u8 *raddr, u8 *frame_body, u16 config_method)
-+{
-+	_adapter *padapter = pwdinfo->padapter;
-+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
-+	u8			action = P2P_PUB_ACTION_ACTION;
-+	u8			dialogToken = frame_body[7];	/*	The Dialog Token of provisioning discovery request frame. */
-+	u32			p2poui = cpu_to_be32(P2POUI);
-+	u8			oui_subtype = P2P_PROVISION_DISC_RESP;
-+	u8			wpsie[100] = { 0x00 };
-+	u8			wpsielen = 0;
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
-+
-+	wpsielen = 0;
-+	/*	WPS OUI */
-+	/* *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); */
-+	RTW_PUT_BE32(wpsie, WPSOUI);
-+	wpsielen += 4;
-+
-+#if 0
-+	/*	WPS version */
-+	/*	Type: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
-+	wpsielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+	wpsielen += 2;
-+
-+	/*	Value: */
-+	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
-+#endif
-+
-+	/*	Config Method */
-+	/*	Type: */
-+	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); */
-+	RTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD);
-+	wpsielen += 2;
-+
-+	/*	Length: */
-+	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); */
-+	RTW_PUT_BE16(wpsie + wpsielen, 0x0002);
-+	wpsielen += 2;
-+
-+	/*	Value: */
-+	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method ); */
-+	RTW_PUT_BE16(wpsie + wpsielen, config_method);
-+	wpsielen += 2;
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe);
-+	pframe += wfdielen;
-+	pattrib->pktlen += wfdielen;
-+#endif
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return;
-+
-+}
-+
-+static void issue_p2p_presence_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken)
-+{
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	unsigned char category = RTW_WLAN_CATEGORY_P2P;/* P2P action frame	 */
-+	u32	p2poui = cpu_to_be32(P2POUI);
-+	u8	oui_subtype = P2P_PRESENCE_RESPONSE;
-+	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
-+	u8 noa_attr_content[32] = { 0x00 };
-+	u32 p2pielen = 0;
-+
-+	RTW_INFO("[%s]\n", __FUNCTION__);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	/* Build P2P action frame header */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
-+
-+
-+	/* Add P2P IE header */
-+	/*	P2P OUI */
-+	p2pielen = 0;
-+	p2pie[p2pielen++] = 0x50;
-+	p2pie[p2pielen++] = 0x6F;
-+	p2pie[p2pielen++] = 0x9A;
-+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+	/* Add Status attribute in P2P IE */
-+	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status);
-+
-+	/* Add NoA attribute in P2P IE */
-+	noa_attr_content[0] = 0x1;/* index */
-+	noa_attr_content[1] = 0x0;/* CTWindow and OppPS Parameters */
-+
-+	/* todo: Notice of Absence Descriptor(s) */
-+
-+	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_NOA, 2, noa_attr_content);
-+
-+
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &(pattrib->pktlen));
-+
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+}
-+
-+u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
-+	u16 capability = 0;
-+	u32 len = 0, p2pielen = 0;
-+
-+
-+	/*	P2P OUI */
-+	p2pielen = 0;
-+	p2pie[p2pielen++] = 0x50;
-+	p2pie[p2pielen++] = 0x6F;
-+	p2pie[p2pielen++] = 0x9A;
-+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+
-+	/*	According to the P2P Specification, the beacon frame should contain 3 P2P attributes */
-+	/*	1. P2P Capability */
-+	/*	2. P2P Device ID */
-+	/*	3. Notice of Absence ( NOA )	 */
-+
-+	/*	P2P Capability ATTR */
-+	/*	Type: */
-+	/*	Length: */
-+	/*	Value: */
-+	/*	Device Capability Bitmap, 1 byte */
-+	/*	Be able to participate in additional P2P Groups and */
-+	/*	support the P2P Invitation Procedure	 */
-+	/*	Group Capability Bitmap, 1 byte	 */
-+	capability = P2P_DEVCAP_INVITATION_PROC | P2P_DEVCAP_CLIENT_DISCOVERABILITY;
-+	capability |= ((P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS) << 8);
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
-+		capability |= (P2P_GRPCAP_GROUP_FORMATION << 8);
-+
-+	capability = cpu_to_le16(capability);
-+
-+	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_CAPABILITY, 2, (u8 *)&capability);
-+
-+
-+	/* P2P Device ID ATTR */
-+	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_DEVICE_ID, ETH_ALEN, pwdinfo->device_addr);
-+
-+
-+	/* Notice of Absence ATTR */
-+	/*	Type:  */
-+	/*	Length: */
-+	/*	Value: */
-+
-+	/* go_add_noa_attr(pwdinfo); */
-+
-+
-+	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
-+
-+
-+	return len;
-+
-+}
-+
-+#ifdef CONFIG_WFD
-+u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
-+	u16 val16 = 0;
-+	u32 len = 0, wfdielen = 0;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
-+
-+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+	/*	WFD OUI */
-+	wfdielen = 0;
-+	wfdie[wfdielen++] = 0x50;
-+	wfdie[wfdielen++] = 0x6F;
-+	wfdie[wfdielen++] = 0x9A;
-+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
-+
-+	/*	Commented by Albert 20110812 */
-+	/*	According to the WFD Specification, the beacon frame should contain 4 WFD attributes */
-+	/*	1. WFD Device Information */
-+	/*	2. Associated BSSID */
-+	/*	3. Coupled Sink Information */
-+
-+
-+	/*	WFD Device Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value1: */
-+	/*	WFD device information */
-+
-+	if (P2P_ROLE_GO == pwdinfo->role) {
-+		if (is_any_client_associated(pwdinfo->padapter)) {
-+			/*	WFD primary sink + WiFi Direct mode + WSD (WFD Service Discovery) */
-+			val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD;
-+			RTW_PUT_BE16(wfdie + wfdielen, val16);
-+		} else {
-+			/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD (WFD Service Discovery) */
-+			val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
-+			RTW_PUT_BE16(wfdie + wfdielen, val16);
-+		}
-+
-+	} else {
-+		/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
-+		val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
-+		RTW_PUT_BE16(wfdie + wfdielen, val16);
-+	}
-+
-+	wfdielen += 2;
-+
-+	/*	Value2: */
-+	/*	Session Management Control Port */
-+	/*	Default TCP port for RTSP messages is 554 */
-+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
-+	wfdielen += 2;
-+
-+	/*	Value3: */
-+	/*	WFD Device Maximum Throughput */
-+	/*	300Mbps is the maximum throughput */
-+	RTW_PUT_BE16(wfdie + wfdielen, 300);
-+	wfdielen += 2;
-+
-+	/*	Associated BSSID ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Associated BSSID */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
-+	else
-+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
-+
-+	wfdielen += ETH_ALEN;
-+
-+	/*	Coupled Sink Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Coupled Sink Status bitmap */
-+	/*	Not coupled/available for Coupling */
-+	wfdie[wfdielen++] = 0;
-+	/* MAC Addr. */
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+
-+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
-+
-+exit:
-+	return len;
-+}
-+
-+u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
-+	u16 val16 = 0;
-+	u32 len = 0, wfdielen = 0;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
-+
-+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+	/*	WFD OUI */
-+	wfdielen = 0;
-+	wfdie[wfdielen++] = 0x50;
-+	wfdie[wfdielen++] = 0x6F;
-+	wfdie[wfdielen++] = 0x9A;
-+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
-+
-+	/*	Commented by Albert 20110812 */
-+	/*	According to the WFD Specification, the probe request frame should contain 4 WFD attributes */
-+	/*	1. WFD Device Information */
-+	/*	2. Associated BSSID */
-+	/*	3. Coupled Sink Information */
-+
-+
-+	/*	WFD Device Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value1: */
-+	/*	WFD device information */
-+
-+	if (1 == pwdinfo->wfd_tdls_enable) {
-+		/*	WFD primary sink + available for WFD session + WiFi TDLS mode + WSC ( WFD Service Discovery )	 */
-+		val16 = pwfd_info->wfd_device_type |
-+			WFD_DEVINFO_SESSION_AVAIL |
-+			WFD_DEVINFO_WSD |
-+			WFD_DEVINFO_PC_TDLS;
-+		RTW_PUT_BE16(wfdie + wfdielen, val16);
-+	} else {
-+		/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSC ( WFD Service Discovery )	 */
-+		val16 = pwfd_info->wfd_device_type |
-+			WFD_DEVINFO_SESSION_AVAIL |
-+			WFD_DEVINFO_WSD;
-+		RTW_PUT_BE16(wfdie + wfdielen, val16);
-+	}
-+
-+	wfdielen += 2;
-+
-+	/*	Value2: */
-+	/*	Session Management Control Port */
-+	/*	Default TCP port for RTSP messages is 554 */
-+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
-+	wfdielen += 2;
-+
-+	/*	Value3: */
-+	/*	WFD Device Maximum Throughput */
-+	/*	300Mbps is the maximum throughput */
-+	RTW_PUT_BE16(wfdie + wfdielen, 300);
-+	wfdielen += 2;
-+
-+	/*	Associated BSSID ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Associated BSSID */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
-+	else
-+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
-+
-+	wfdielen += ETH_ALEN;
-+
-+	/*	Coupled Sink Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Coupled Sink Status bitmap */
-+	/*	Not coupled/available for Coupling */
-+	wfdie[wfdielen++] = 0;
-+	/* MAC Addr. */
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+
-+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
-+
-+exit:
-+	return len;
-+}
-+
-+u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled)
-+{
-+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
-+	u32 len = 0, wfdielen = 0;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
-+	u16 v16 = 0;
-+
-+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+	/*	WFD OUI */
-+	wfdielen = 0;
-+	wfdie[wfdielen++] = 0x50;
-+	wfdie[wfdielen++] = 0x6F;
-+	wfdie[wfdielen++] = 0x9A;
-+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
-+
-+	/*	Commented by Albert 20110812 */
-+	/*	According to the WFD Specification, the probe response frame should contain 4 WFD attributes */
-+	/*	1. WFD Device Information */
-+	/*	2. Associated BSSID */
-+	/*	3. Coupled Sink Information */
-+	/*	4. WFD Session Information */
-+
-+
-+	/*	WFD Device Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value1: */
-+	/*	WFD device information */
-+	/*	WFD primary sink + available for WFD session + WiFi Direct mode */
-+
-+	if (_TRUE == pwdinfo->session_available) {
-+		if (P2P_ROLE_GO == pwdinfo->role) {
-+			if (is_any_client_associated(pwdinfo->padapter)) {
-+				if (pwdinfo->wfd_tdls_enable) {
-+					/*	TDLS mode + WSD ( WFD Service Discovery ) */
-+					v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
-+					RTW_PUT_BE16(wfdie + wfdielen, v16);
-+				} else {
-+					/*	WiFi Direct mode + WSD ( WFD Service Discovery ) */
-+					v16 =  pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
-+					RTW_PUT_BE16(wfdie + wfdielen, v16);
-+				}
-+			} else {
-+				if (pwdinfo->wfd_tdls_enable) {
-+					/*	available for WFD session + TDLS mode + WSD ( WFD Service Discovery ) */
-+					v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
-+					RTW_PUT_BE16(wfdie + wfdielen, v16);
-+				} else {
-+					/*	available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
-+					v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
-+					RTW_PUT_BE16(wfdie + wfdielen, v16);
-+				}
-+			}
-+		} else {
-+			if (pwdinfo->wfd_tdls_enable) {
-+				/*	available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
-+				v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
-+				RTW_PUT_BE16(wfdie + wfdielen, v16);
-+			} else {
-+				/*	available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
-+				v16 =  pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
-+				RTW_PUT_BE16(wfdie + wfdielen, v16);
-+			}
-+		}
-+	} else {
-+		if (pwdinfo->wfd_tdls_enable) {
-+			v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
-+			RTW_PUT_BE16(wfdie + wfdielen, v16);
-+		} else {
-+			v16 =  pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
-+			RTW_PUT_BE16(wfdie + wfdielen, v16);
-+		}
-+	}
-+
-+	wfdielen += 2;
-+
-+	/*	Value2: */
-+	/*	Session Management Control Port */
-+	/*	Default TCP port for RTSP messages is 554 */
-+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
-+	wfdielen += 2;
-+
-+	/*	Value3: */
-+	/*	WFD Device Maximum Throughput */
-+	/*	300Mbps is the maximum throughput */
-+	RTW_PUT_BE16(wfdie + wfdielen, 300);
-+	wfdielen += 2;
-+
-+	/*	Associated BSSID ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Associated BSSID */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
-+	else
-+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
-+
-+	wfdielen += ETH_ALEN;
-+
-+	/*	Coupled Sink Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Coupled Sink Status bitmap */
-+	/*	Not coupled/available for Coupling */
-+	wfdie[wfdielen++] = 0;
-+	/* MAC Addr. */
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+		/*	WFD Session Information ATTR */
-+		/*	Type: */
-+		wfdie[wfdielen++] = WFD_ATTR_SESSION_INFO;
-+
-+		/*	Length: */
-+		/*	Note: In the WFD specification, the size of length field is 2. */
-+		RTW_PUT_BE16(wfdie + wfdielen, 0x0000);
-+		wfdielen += 2;
-+
-+		/*	Todo: to add the list of WFD device info descriptor in WFD group. */
-+
-+	}
-+#ifdef CONFIG_CONCURRENT_MODE
-+#ifdef CONFIG_TDLS
-+	{
-+		int i;
-+		_adapter *iface = NULL;
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			if ((iface) && rtw_is_adapter_up(iface)) {
-+				if (iface == padapter)
-+					continue;
-+
-+				if ((tunneled == 0) && (iface->wdinfo.wfd_tdls_enable == 1)) {
-+					/*	Alternative MAC Address ATTR
-+						Type:					*/
-+					wfdie[wfdielen++] = WFD_ATTR_ALTER_MAC;
-+
-+					/*	Length:
-+						Note: In the WFD specification, the size of length field is 2.*/
-+					RTW_PUT_BE16(wfdie + wfdielen,  ETH_ALEN);
-+					wfdielen += 2;
-+
-+					/*	Value:
-+						Alternative MAC Address*/
-+					_rtw_memcpy(wfdie + wfdielen, adapter_mac_addr(iface), ETH_ALEN);
-+					wfdielen += ETH_ALEN;
-+				}
-+			}
-+		}
-+	}
-+
-+#endif /* CONFIG_TDLS*/
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
-+
-+exit:
-+	return len;
-+}
-+
-+u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
-+	u16 val16 = 0;
-+	u32 len = 0, wfdielen = 0;
-+	_adapter					*padapter = NULL;
-+	struct mlme_priv			*pmlmepriv = NULL;
-+	struct wifi_display_info		*pwfd_info = NULL;
-+
-+	padapter = pwdinfo->padapter;
-+	pmlmepriv = &padapter->mlmepriv;
-+	pwfd_info = padapter->wdinfo.wfd_info;
-+
-+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE))
-+		goto exit;
-+
-+	/* WFD OUI */
-+	wfdielen = 0;
-+	wfdie[wfdielen++] = 0x50;
-+	wfdie[wfdielen++] = 0x6F;
-+	wfdie[wfdielen++] = 0x9A;
-+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
-+
-+	/*	Commented by Albert 20110812 */
-+	/*	According to the WFD Specification, the probe request frame should contain 4 WFD attributes */
-+	/*	1. WFD Device Information */
-+	/*	2. Associated BSSID */
-+	/*	3. Coupled Sink Information */
-+
-+
-+	/*	WFD Device Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value1: */
-+	/*	WFD device information */
-+	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
-+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
-+	RTW_PUT_BE16(wfdie + wfdielen, val16);
-+	wfdielen += 2;
-+
-+	/*	Value2: */
-+	/*	Session Management Control Port */
-+	/*	Default TCP port for RTSP messages is 554 */
-+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
-+	wfdielen += 2;
-+
-+	/*	Value3: */
-+	/*	WFD Device Maximum Throughput */
-+	/*	300Mbps is the maximum throughput */
-+	RTW_PUT_BE16(wfdie + wfdielen, 300);
-+	wfdielen += 2;
-+
-+	/*	Associated BSSID ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Associated BSSID */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
-+	else
-+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
-+
-+	wfdielen += ETH_ALEN;
-+
-+	/*	Coupled Sink Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Coupled Sink Status bitmap */
-+	/*	Not coupled/available for Coupling */
-+	wfdie[wfdielen++] = 0;
-+	/* MAC Addr. */
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+
-+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
-+
-+exit:
-+	return len;
-+}
-+
-+u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
-+	u32 len = 0, wfdielen = 0;
-+	u16 val16 = 0;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
-+
-+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+	/*	WFD OUI */
-+	wfdielen = 0;
-+	wfdie[wfdielen++] = 0x50;
-+	wfdie[wfdielen++] = 0x6F;
-+	wfdie[wfdielen++] = 0x9A;
-+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
-+
-+	/*	Commented by Albert 20110812 */
-+	/*	According to the WFD Specification, the probe request frame should contain 4 WFD attributes */
-+	/*	1. WFD Device Information */
-+	/*	2. Associated BSSID */
-+	/*	3. Coupled Sink Information */
-+
-+
-+	/*	WFD Device Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value1: */
-+	/*	WFD device information */
-+	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
-+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
-+	RTW_PUT_BE16(wfdie + wfdielen, val16);
-+	wfdielen += 2;
-+
-+	/*	Value2: */
-+	/*	Session Management Control Port */
-+	/*	Default TCP port for RTSP messages is 554 */
-+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
-+	wfdielen += 2;
-+
-+	/*	Value3: */
-+	/*	WFD Device Maximum Throughput */
-+	/*	300Mbps is the maximum throughput */
-+	RTW_PUT_BE16(wfdie + wfdielen, 300);
-+	wfdielen += 2;
-+
-+	/*	Associated BSSID ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Associated BSSID */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
-+	else
-+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
-+
-+	wfdielen += ETH_ALEN;
-+
-+	/*	Coupled Sink Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Coupled Sink Status bitmap */
-+	/*	Not coupled/available for Coupling */
-+	wfdie[wfdielen++] = 0;
-+	/* MAC Addr. */
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+
-+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
-+
-+exit:
-+	return len;
-+}
-+
-+u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
-+	u32 len = 0, wfdielen = 0;
-+	u16 val16 = 0;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
-+
-+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+	/*	WFD OUI */
-+	wfdielen = 0;
-+	wfdie[wfdielen++] = 0x50;
-+	wfdie[wfdielen++] = 0x6F;
-+	wfdie[wfdielen++] = 0x9A;
-+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
-+
-+	/*	Commented by Albert 20110825 */
-+	/*	According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */
-+	/*	1. WFD Device Information */
-+	/*	2. Associated BSSID ( Optional ) */
-+	/*	3. Local IP Adress ( Optional ) */
-+
-+
-+	/*	WFD Device Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value1: */
-+	/*	WFD device information */
-+	/*	WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */
-+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL;
-+	RTW_PUT_BE16(wfdie + wfdielen, val16);
-+	wfdielen += 2;
-+
-+	/*	Value2: */
-+	/*	Session Management Control Port */
-+	/*	Default TCP port for RTSP messages is 554 */
-+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
-+	wfdielen += 2;
-+
-+	/*	Value3: */
-+	/*	WFD Device Maximum Throughput */
-+	/*	300Mbps is the maximum throughput */
-+	RTW_PUT_BE16(wfdie + wfdielen, 300);
-+	wfdielen += 2;
-+
-+	/*	Associated BSSID ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Associated BSSID */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
-+	else
-+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
-+
-+	wfdielen += ETH_ALEN;
-+
-+	/*	Coupled Sink Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Coupled Sink Status bitmap */
-+	/*	Not coupled/available for Coupling */
-+	wfdie[wfdielen++] = 0;
-+	/* MAC Addr. */
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+
-+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
-+
-+exit:
-+	return len;
-+}
-+
-+u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
-+	u32 len = 0, wfdielen = 0;
-+	u16 val16 = 0;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
-+
-+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+	/*	WFD OUI */
-+	wfdielen = 0;
-+	wfdie[wfdielen++] = 0x50;
-+	wfdie[wfdielen++] = 0x6F;
-+	wfdie[wfdielen++] = 0x9A;
-+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
-+
-+	/*	Commented by Albert 20110825 */
-+	/*	According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */
-+	/*	1. WFD Device Information */
-+	/*	2. Associated BSSID ( Optional ) */
-+	/*	3. Local IP Adress ( Optional ) */
-+
-+
-+	/*	WFD Device Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value1: */
-+	/*	WFD device information */
-+	/*	WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */
-+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL;
-+	RTW_PUT_BE16(wfdie + wfdielen, val16);
-+	wfdielen += 2;
-+
-+	/*	Value2: */
-+	/*	Session Management Control Port */
-+	/*	Default TCP port for RTSP messages is 554 */
-+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
-+	wfdielen += 2;
-+
-+	/*	Value3: */
-+	/*	WFD Device Maximum Throughput */
-+	/*	300Mbps is the maximum throughput */
-+	RTW_PUT_BE16(wfdie + wfdielen, 300);
-+	wfdielen += 2;
-+
-+	/*	Associated BSSID ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Associated BSSID */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
-+	else
-+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
-+
-+	wfdielen += ETH_ALEN;
-+
-+	/*	Coupled Sink Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Coupled Sink Status bitmap */
-+	/*	Not coupled/available for Coupling */
-+	wfdie[wfdielen++] = 0;
-+	/* MAC Addr. */
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+
-+
-+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
-+
-+exit:
-+	return len;
-+}
-+
-+u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
-+	u32 len = 0, wfdielen = 0;
-+	u16 val16 = 0;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
-+
-+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+	/*	WFD OUI */
-+	wfdielen = 0;
-+	wfdie[wfdielen++] = 0x50;
-+	wfdie[wfdielen++] = 0x6F;
-+	wfdie[wfdielen++] = 0x9A;
-+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
-+
-+	/*	Commented by Albert 20110825 */
-+	/*	According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */
-+	/*	1. WFD Device Information */
-+	/*	2. Associated BSSID ( Optional ) */
-+	/*	3. Local IP Adress ( Optional ) */
-+
-+
-+	/*	WFD Device Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value1: */
-+	/*	WFD device information */
-+	/*	WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */
-+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL;
-+	RTW_PUT_BE16(wfdie + wfdielen, val16);
-+	wfdielen += 2;
-+
-+	/*	Value2: */
-+	/*	Session Management Control Port */
-+	/*	Default TCP port for RTSP messages is 554 */
-+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
-+	wfdielen += 2;
-+
-+	/*	Value3: */
-+	/*	WFD Device Maximum Throughput */
-+	/*	300Mbps is the maximum throughput */
-+	RTW_PUT_BE16(wfdie + wfdielen, 300);
-+	wfdielen += 2;
-+
-+	/*	Associated BSSID ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Associated BSSID */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
-+	else
-+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
-+
-+	wfdielen += ETH_ALEN;
-+
-+	/*	Coupled Sink Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Coupled Sink Status bitmap */
-+	/*	Not coupled/available for Coupling */
-+	wfdie[wfdielen++] = 0;
-+	/* MAC Addr. */
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+
-+
-+	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
-+
-+exit:
-+	return len;
-+}
-+
-+u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
-+	u32 len = 0, wfdielen = 0;
-+	u16 val16 = 0;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
-+
-+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+	/*	WFD OUI */
-+	wfdielen = 0;
-+	wfdie[wfdielen++] = 0x50;
-+	wfdie[wfdielen++] = 0x6F;
-+	wfdie[wfdielen++] = 0x9A;
-+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
-+
-+	/*	Commented by Albert 20110825 */
-+	/*	According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */
-+	/*	1. WFD Device Information */
-+	/*	2. Associated BSSID ( Optional ) */
-+	/*	3. Local IP Adress ( Optional ) */
-+
-+
-+	/*	WFD Device Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value1: */
-+	/*	WFD device information */
-+	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
-+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
-+	RTW_PUT_BE16(wfdie + wfdielen, val16);
-+	wfdielen += 2;
-+
-+	/*	Value2: */
-+	/*	Session Management Control Port */
-+	/*	Default TCP port for RTSP messages is 554 */
-+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
-+	wfdielen += 2;
-+
-+	/*	Value3: */
-+	/*	WFD Device Maximum Throughput */
-+	/*	300Mbps is the maximum throughput */
-+	RTW_PUT_BE16(wfdie + wfdielen, 300);
-+	wfdielen += 2;
-+
-+	/*	Associated BSSID ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Associated BSSID */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
-+	else
-+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
-+
-+	wfdielen += ETH_ALEN;
-+
-+	/*	Coupled Sink Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Coupled Sink Status bitmap */
-+	/*	Not coupled/available for Coupling */
-+	wfdie[wfdielen++] = 0;
-+	/* MAC Addr. */
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+
-+	if (P2P_ROLE_GO == pwdinfo->role) {
-+		/*	WFD Session Information ATTR */
-+		/*	Type: */
-+		wfdie[wfdielen++] = WFD_ATTR_SESSION_INFO;
-+
-+		/*	Length: */
-+		/*	Note: In the WFD specification, the size of length field is 2. */
-+		RTW_PUT_BE16(wfdie + wfdielen, 0x0000);
-+		wfdielen += 2;
-+
-+		/*	Todo: to add the list of WFD device info descriptor in WFD group. */
-+
-+	}
-+
-+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
-+
-+exit:
-+	return len;
-+}
-+
-+u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
-+	u16 val16 = 0;
-+	u32 len = 0, wfdielen = 0;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
-+
-+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+	/*	WFD OUI */
-+	wfdielen = 0;
-+	wfdie[wfdielen++] = 0x50;
-+	wfdie[wfdielen++] = 0x6F;
-+	wfdie[wfdielen++] = 0x9A;
-+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
-+
-+	/*	Commented by Albert 20110825 */
-+	/*	According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */
-+	/*	1. WFD Device Information */
-+	/*	2. Associated BSSID ( Optional ) */
-+	/*	3. Local IP Adress ( Optional ) */
-+
-+
-+	/*	WFD Device Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value1: */
-+	/*	WFD device information */
-+	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
-+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
-+	RTW_PUT_BE16(wfdie + wfdielen, val16);
-+	wfdielen += 2;
-+
-+	/*	Value2: */
-+	/*	Session Management Control Port */
-+	/*	Default TCP port for RTSP messages is 554 */
-+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
-+	wfdielen += 2;
-+
-+	/*	Value3: */
-+	/*	WFD Device Maximum Throughput */
-+	/*	300Mbps is the maximum throughput */
-+	RTW_PUT_BE16(wfdie + wfdielen, 300);
-+	wfdielen += 2;
-+
-+	/*	Associated BSSID ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Associated BSSID */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
-+	else
-+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
-+
-+	wfdielen += ETH_ALEN;
-+
-+	/*	Coupled Sink Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Coupled Sink Status bitmap */
-+	/*	Not coupled/available for Coupling */
-+	wfdie[wfdielen++] = 0;
-+	/* MAC Addr. */
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+
-+	if (P2P_ROLE_GO == pwdinfo->role) {
-+		/*	WFD Session Information ATTR */
-+		/*	Type: */
-+		wfdie[wfdielen++] = WFD_ATTR_SESSION_INFO;
-+
-+		/*	Length: */
-+		/*	Note: In the WFD specification, the size of length field is 2. */
-+		RTW_PUT_BE16(wfdie + wfdielen, 0x0000);
-+		wfdielen += 2;
-+
-+		/*	Todo: to add the list of WFD device info descriptor in WFD group. */
-+
-+	}
-+
-+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
-+
-+exit:
-+	return len;
-+}
-+
-+u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
-+	u32 len = 0, wfdielen = 0;
-+	u16 val16 = 0;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
-+
-+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+	/*	WFD OUI */
-+	wfdielen = 0;
-+	wfdie[wfdielen++] = 0x50;
-+	wfdie[wfdielen++] = 0x6F;
-+	wfdie[wfdielen++] = 0x9A;
-+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
-+
-+	/*	Commented by Albert 20110825 */
-+	/*	According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */
-+	/*	1. WFD Device Information */
-+	/*	2. Associated BSSID ( Optional ) */
-+	/*	3. Local IP Adress ( Optional ) */
-+
-+
-+	/*	WFD Device Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value1: */
-+	/*	WFD device information */
-+	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
-+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
-+	RTW_PUT_BE16(wfdie + wfdielen, val16);
-+	wfdielen += 2;
-+
-+	/*	Value2: */
-+	/*	Session Management Control Port */
-+	/*	Default TCP port for RTSP messages is 554 */
-+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
-+	wfdielen += 2;
-+
-+	/*	Value3: */
-+	/*	WFD Device Maximum Throughput */
-+	/*	300Mbps is the maximum throughput */
-+	RTW_PUT_BE16(wfdie + wfdielen, 300);
-+	wfdielen += 2;
-+
-+	/*	Associated BSSID ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Associated BSSID */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
-+	else
-+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
-+
-+	wfdielen += ETH_ALEN;
-+
-+	/*	Coupled Sink Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Coupled Sink Status bitmap */
-+	/*	Not coupled/available for Coupling */
-+	wfdie[wfdielen++] = 0;
-+	/* MAC Addr. */
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+
-+
-+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
-+
-+exit:
-+	return len;
-+}
-+
-+u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
-+	u32 len = 0, wfdielen = 0;
-+	u16 val16 = 0;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct wifi_display_info	*pwfd_info = padapter->wdinfo.wfd_info;
-+
-+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+	/*	WFD OUI */
-+	wfdielen = 0;
-+	wfdie[wfdielen++] = 0x50;
-+	wfdie[wfdielen++] = 0x6F;
-+	wfdie[wfdielen++] = 0x9A;
-+	wfdie[wfdielen++] = 0x0A;	/*	WFA WFD v1.0 */
-+
-+	/*	Commented by Albert 20110825 */
-+	/*	According to the WFD Specification, the provision discovery response frame should contain 3 WFD attributes */
-+	/*	1. WFD Device Information */
-+	/*	2. Associated BSSID ( Optional ) */
-+	/*	3. Local IP Adress ( Optional ) */
-+
-+
-+	/*	WFD Device Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value1: */
-+	/*	WFD device information */
-+	/*	WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
-+	val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD;
-+	RTW_PUT_BE16(wfdie + wfdielen, val16);
-+	wfdielen += 2;
-+
-+	/*	Value2: */
-+	/*	Session Management Control Port */
-+	/*	Default TCP port for RTSP messages is 554 */
-+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport);
-+	wfdielen += 2;
-+
-+	/*	Value3: */
-+	/*	WFD Device Maximum Throughput */
-+	/*	300Mbps is the maximum throughput */
-+	RTW_PUT_BE16(wfdie + wfdielen, 300);
-+	wfdielen += 2;
-+
-+	/*	Associated BSSID ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Associated BSSID */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
-+	else
-+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
-+
-+	wfdielen += ETH_ALEN;
-+
-+	/*	Coupled Sink Information ATTR */
-+	/*	Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO;
-+
-+	/*	Length: */
-+	/*	Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0007);
-+	wfdielen += 2;
-+
-+	/*	Value: */
-+	/*	Coupled Sink Status bitmap */
-+	/*	Not coupled/available for Coupling */
-+	wfdie[wfdielen++] = 0;
-+	/* MAC Addr. */
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+	wfdie[wfdielen++] = 0;
-+
-+	rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len);
-+
-+exit:
-+	return len;
-+}
-+#endif /* CONFIG_WFD */
-+
-+u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
-+	u32 len = 0, p2pielen = 0;
-+
-+	/*	P2P OUI */
-+	p2pielen = 0;
-+	p2pie[p2pielen++] = 0x50;
-+	p2pie[p2pielen++] = 0x6F;
-+	p2pie[p2pielen++] = 0x9A;
-+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+	/*	Commented by Albert 20100907 */
-+	/*	According to the P2P Specification, the probe response frame should contain 5 P2P attributes */
-+	/*	1. P2P Capability */
-+	/*	2. Extended Listen Timing */
-+	/*	3. Notice of Absence ( NOA )	( Only GO needs this ) */
-+	/*	4. Device Info */
-+	/*	5. Group Info	( Only GO need this ) */
-+
-+	/*	P2P Capability ATTR */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
-+
-+	/*	Length: */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */
-+	RTW_PUT_LE16(p2pie + p2pielen, 0x0002);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Device Capability Bitmap, 1 byte */
-+	p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
-+
-+	/*	Group Capability Bitmap, 1 byte */
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+		p2pie[p2pielen] = (P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS);
-+
-+		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
-+			p2pie[p2pielen] |= P2P_GRPCAP_GROUP_FORMATION;
-+
-+		p2pielen++;
-+	} else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) {
-+		/*	Group Capability Bitmap, 1 byte */
-+		if (pwdinfo->persistent_supported)
-+			p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
-+		else
-+			p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;
-+	}
-+
-+	/*	Extended Listen Timing ATTR */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING;
-+
-+	/*	Length: */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); */
-+	RTW_PUT_LE16(p2pie + p2pielen, 0x0004);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Availability Period */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); */
-+	RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF);
-+	p2pielen += 2;
-+
-+	/*	Availability Interval */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); */
-+	RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF);
-+	p2pielen += 2;
-+
-+
-+	/* Notice of Absence ATTR */
-+	/*	Type:  */
-+	/*	Length: */
-+	/*	Value: */
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+		/* go_add_noa_attr(pwdinfo); */
-+	}
-+
-+	/*	Device Info ATTR */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
-+	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */
-+	RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	P2P Device Address */
-+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);
-+	p2pielen += ETH_ALEN;
-+
-+	/*	Config Method */
-+	/*	This field should be big endian. Noted by P2P specification. */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); */
-+	RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->supported_wps_cm);
-+	p2pielen += 2;
-+
-+	{
-+		/*	Primary Device Type */
-+		/*	Category ID */
-+		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); */
-+		RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA);
-+		p2pielen += 2;
-+
-+		/*	OUI */
-+		/* *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); */
-+		RTW_PUT_BE32(p2pie + p2pielen, WPSOUI);
-+		p2pielen += 4;
-+
-+		/*	Sub Category ID */
-+		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); */
-+		RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER);
-+		p2pielen += 2;
-+	}
-+
-+	/*	Number of Secondary Device Types */
-+	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
-+
-+	/*	Device Name */
-+	/*	Type: */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */
-+	RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME);
-+	p2pielen += 2;
-+
-+	/*	Length: */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); */
-+	RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);
-+	p2pielen += pwdinfo->device_name_len;
-+
-+	/* Group Info ATTR */
-+	/*	Type: */
-+	/*	Length: */
-+	/*	Value: */
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
-+		p2pielen += go_add_group_info_attr(pwdinfo, p2pie + p2pielen);
-+
-+
-+	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
-+
-+
-+	return len;
-+
-+}
-+
-+u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 *pssid, u8 ussidlen, u8 *pdev_raddr)
-+{
-+	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
-+	u32 len = 0, p2pielen = 0;
-+
-+	/*	P2P OUI */
-+	p2pielen = 0;
-+	p2pie[p2pielen++] = 0x50;
-+	p2pie[p2pielen++] = 0x6F;
-+	p2pie[p2pielen++] = 0x9A;
-+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+	/*	Commented by Albert 20110301 */
-+	/*	According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes */
-+	/*	1. P2P Capability */
-+	/*	2. Device Info */
-+	/*	3. Group ID ( When joining an operating P2P Group ) */
-+
-+	/*	P2P Capability ATTR */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
-+
-+	/*	Length: */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */
-+	RTW_PUT_LE16(p2pie + p2pielen, 0x0002);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Device Capability Bitmap, 1 byte */
-+	p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
-+
-+	/*	Group Capability Bitmap, 1 byte */
-+	if (pwdinfo->persistent_supported)
-+		p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT;
-+	else
-+		p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT;
-+
-+
-+	/*	Device Info ATTR */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
-+	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */
-+	RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	P2P Device Address */
-+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN);
-+	p2pielen += ETH_ALEN;
-+
-+	/*	Config Method */
-+	/*	This field should be big endian. Noted by P2P specification. */
-+	if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC) {
-+		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_PBC ); */
-+		RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_PBC);
-+	} else {
-+		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); */
-+		RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_DISPLAY);
-+	}
-+
-+	p2pielen += 2;
-+
-+	/*	Primary Device Type */
-+	/*	Category ID */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); */
-+	RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA);
-+	p2pielen += 2;
-+
-+	/*	OUI */
-+	/* *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); */
-+	RTW_PUT_BE32(p2pie + p2pielen, WPSOUI);
-+	p2pielen += 4;
-+
-+	/*	Sub Category ID */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); */
-+	RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER);
-+	p2pielen += 2;
-+
-+	/*	Number of Secondary Device Types */
-+	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
-+
-+	/*	Device Name */
-+	/*	Type: */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */
-+	RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME);
-+	p2pielen += 2;
-+
-+	/*	Length: */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); */
-+	RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len);
-+	p2pielen += pwdinfo->device_name_len;
-+
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
-+		/*	Added by Albert 2011/05/19 */
-+		/*	In this case, the pdev_raddr is the device address of the group owner. */
-+
-+		/*	P2P Group ID ATTR */
-+		/*	Type: */
-+		p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
-+
-+		/*	Length: */
-+		/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + ussidlen ); */
-+		RTW_PUT_LE16(p2pie + p2pielen, ETH_ALEN + ussidlen);
-+		p2pielen += 2;
-+
-+		/*	Value: */
-+		_rtw_memcpy(p2pie + p2pielen, pdev_raddr, ETH_ALEN);
-+		p2pielen += ETH_ALEN;
-+
-+		_rtw_memcpy(p2pie + p2pielen, pssid, ussidlen);
-+		p2pielen += ussidlen;
-+
-+	}
-+
-+	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
-+
-+
-+	return len;
-+
-+}
-+
-+
-+u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code)
-+{
-+	u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 };
-+	u32 len = 0, p2pielen = 0;
-+
-+	/*	P2P OUI */
-+	p2pielen = 0;
-+	p2pie[p2pielen++] = 0x50;
-+	p2pie[p2pielen++] = 0x6F;
-+	p2pie[p2pielen++] = 0x9A;
-+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+	/* According to the P2P Specification, the Association response frame should contain 2 P2P attributes */
-+	/*	1. Status */
-+	/*	2. Extended Listen Timing (optional) */
-+
-+
-+	/*	Status ATTR */
-+	p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status_code);
-+
-+
-+	/* Extended Listen Timing ATTR */
-+	/*	Type: */
-+	/*	Length: */
-+	/*	Value: */
-+
-+
-+	pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len);
-+
-+	return len;
-+
-+}
-+
-+u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf)
-+{
-+	u32 len = 0;
-+
-+	return len;
-+}
-+
-+u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
-+{
-+	u8 *p;
-+	u32 ret = _FALSE;
-+	u8 *p2pie;
-+	u32	p2pielen = 0;
-+	int ssid_len = 0, rate_cnt = 0;
-+
-+	p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SUPPORTEDRATES_IE_, (int *)&rate_cnt,
-+		       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
-+
-+	if (rate_cnt <= 4) {
-+		int i, g_rate = 0;
-+
-+		for (i = 0; i < rate_cnt; i++) {
-+			if (((*(p + 2 + i) & 0xff) != 0x02) &&
-+			    ((*(p + 2 + i) & 0xff) != 0x04) &&
-+			    ((*(p + 2 + i) & 0xff) != 0x0B) &&
-+			    ((*(p + 2 + i) & 0xff) != 0x16))
-+				g_rate = 1;
-+		}
-+
-+		if (g_rate == 0) {
-+			/*	There is no OFDM rate included in SupportedRates IE of this probe request frame */
-+			/*	The driver should response this probe request. */
-+			return ret;
-+		}
-+	} else {
-+		/*	rate_cnt > 4 means the SupportRates IE contains the OFDM rate because the count of CCK rates are 4. */
-+		/*	We should proceed the following check for this probe request. */
-+	}
-+
-+	/*	Added comments by Albert 20100906 */
-+	/*	There are several items we should check here. */
-+	/*	1. This probe request frame must contain the P2P IE. (Done) */
-+	/*	2. This probe request frame must contain the wildcard SSID. (Done) */
-+	/*	3. Wildcard BSSID. (Todo) */
-+	/*	4. Destination Address. ( Done in mgt_dispatcher function ) */
-+	/*	5. Requested Device Type in WSC IE. (Todo) */
-+	/*	6. Device ID attribute in P2P IE. (Todo) */
-+
-+	p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ssid_len,
-+		       len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
-+
-+	ssid_len &= 0xff;	/*	Just last 1 byte is valid for ssid len of the probe request */
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+		p2pie = rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_ , len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_ , NULL, &p2pielen);
-+		if (p2pie) {
-+			if ((p != NULL) && _rtw_memcmp((void *)(p + 2), (void *) pwdinfo->p2p_wildcard_ssid , 7)) {
-+				/* todo: */
-+				/* Check Requested Device Type attributes in WSC IE. */
-+				/* Check Device ID attribute in P2P IE */
-+
-+				ret = _TRUE;
-+			} else if ((p != NULL) && (ssid_len == 0))
-+				ret = _TRUE;
-+		} else {
-+			/* non -p2p device */
-+		}
-+
-+	}
-+
-+
-+	return ret;
-+
-+}
-+
-+u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta)
-+{
-+	u8 status_code = P2P_STATUS_SUCCESS;
-+	u8 *pbuf, *pattr_content = NULL;
-+	u32 attr_contentlen = 0;
-+	u16 cap_attr = 0;
-+	unsigned short	frame_type, ie_offset = 0;
-+	u8 *ies;
-+	u32 ies_len;
-+	u8 *p2p_ie;
-+	u32	p2p_ielen = 0;
-+
-+	if (!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
-+		return P2P_STATUS_FAIL_REQUEST_UNABLE;
-+
-+	frame_type = get_frame_sub_type(pframe);
-+	if (frame_type == WIFI_ASSOCREQ)
-+		ie_offset = _ASOCREQ_IE_OFFSET_;
-+	else /* WIFI_REASSOCREQ */
-+		ie_offset = _REASOCREQ_IE_OFFSET_;
-+
-+	ies = pframe + WLAN_HDR_A3_LEN + ie_offset;
-+	ies_len = len - WLAN_HDR_A3_LEN - ie_offset;
-+
-+	p2p_ie = rtw_get_p2p_ie(ies , ies_len , NULL, &p2p_ielen);
-+
-+	if (!p2p_ie) {
-+		RTW_INFO("[%s] P2P IE not Found!!\n", __FUNCTION__);
-+		status_code =  P2P_STATUS_FAIL_INVALID_PARAM;
-+	} else
-+		RTW_INFO("[%s] P2P IE Found!!\n", __FUNCTION__);
-+
-+	while (p2p_ie) {
-+		/* Check P2P Capability ATTR */
-+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *) &attr_contentlen)) {
-+			RTW_INFO("[%s] Got P2P Capability Attr!!\n", __FUNCTION__);
-+			cap_attr = le16_to_cpu(cap_attr);
-+			psta->dev_cap = cap_attr & 0xff;
-+		}
-+
-+		/* Check Extended Listen Timing ATTR */
-+
-+
-+		/* Check P2P Device Info ATTR */
-+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, NULL, (uint *)&attr_contentlen)) {
-+			RTW_INFO("[%s] Got P2P DEVICE INFO Attr!!\n", __FUNCTION__);
-+			pattr_content = pbuf = rtw_zmalloc(attr_contentlen);
-+			if (pattr_content) {
-+				u8 num_of_secdev_type;
-+				u16 dev_name_len;
-+
-+
-+				rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO , pattr_content, (uint *)&attr_contentlen);
-+
-+				_rtw_memcpy(psta->dev_addr, 	pattr_content, ETH_ALEN);/* P2P Device Address */
-+
-+				pattr_content += ETH_ALEN;
-+
-+				_rtw_memcpy(&psta->config_methods, pattr_content, 2);/* Config Methods */
-+				psta->config_methods = be16_to_cpu(psta->config_methods);
-+
-+				pattr_content += 2;
-+
-+				_rtw_memcpy(psta->primary_dev_type, pattr_content, 8);
-+
-+				pattr_content += 8;
-+
-+				num_of_secdev_type = *pattr_content;
-+				pattr_content += 1;
-+
-+				if (num_of_secdev_type == 0)
-+					psta->num_of_secdev_type = 0;
-+				else {
-+					u32 len;
-+
-+					psta->num_of_secdev_type = num_of_secdev_type;
-+
-+					len = (sizeof(psta->secdev_types_list) < (num_of_secdev_type * 8)) ? (sizeof(psta->secdev_types_list)) : (num_of_secdev_type * 8);
-+
-+					_rtw_memcpy(psta->secdev_types_list, pattr_content, len);
-+
-+					pattr_content += (num_of_secdev_type * 8);
-+				}
-+
-+
-+				/* dev_name_len = attr_contentlen - ETH_ALEN - 2 - 8 - 1 - (num_of_secdev_type*8); */
-+				psta->dev_name_len = 0;
-+				if (WPS_ATTR_DEVICE_NAME == be16_to_cpu(*(u16 *)pattr_content)) {
-+					dev_name_len = be16_to_cpu(*(u16 *)(pattr_content + 2));
-+
-+					psta->dev_name_len = (sizeof(psta->dev_name) < dev_name_len) ? sizeof(psta->dev_name) : dev_name_len;
-+
-+					_rtw_memcpy(psta->dev_name, pattr_content + 4, psta->dev_name_len);
-+				}
-+
-+				rtw_mfree(pbuf, attr_contentlen);
-+
-+			}
-+
-+		}
-+
-+		/* Get the next P2P IE */
-+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
-+
-+	}
-+
-+	return status_code;
-+
-+}
-+
-+u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
-+{
-+	u8 *frame_body;
-+	u8 status, dialogToken;
-+	struct sta_info *psta = NULL;
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	u8 *p2p_ie;
-+	u32	p2p_ielen = 0;
-+
-+	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
-+
-+	dialogToken = frame_body[7];
-+	status = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP;
-+
-+	p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);
-+	if (p2p_ie) {
-+		u8 groupid[38] = { 0x00 };
-+		u8 dev_addr[ETH_ALEN] = { 0x00 };
-+		u32	attr_contentlen = 0;
-+
-+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) {
-+			if (_rtw_memcmp(pwdinfo->device_addr, groupid, ETH_ALEN) &&
-+			    _rtw_memcmp(pwdinfo->p2p_group_ssid, groupid + ETH_ALEN, pwdinfo->p2p_group_ssid_len)) {
-+				attr_contentlen = 0;
-+				if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_ID, dev_addr, &attr_contentlen)) {
-+					_irqL irqL;
-+					_list	*phead, *plist;
-+
-+					_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+					phead = &pstapriv->asoc_list;
-+					plist = get_next(phead);
-+
-+					/* look up sta asoc_queue */
-+					while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+						psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+
-+						plist = get_next(plist);
-+
-+						if (psta->is_p2p_device && (psta->dev_cap & P2P_DEVCAP_CLIENT_DISCOVERABILITY) &&
-+						    _rtw_memcmp(psta->dev_addr, dev_addr, ETH_ALEN)) {
-+
-+							/* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */
-+							/* issue GO Discoverability Request */
-+							issue_group_disc_req(pwdinfo, psta->cmn.mac_addr);
-+							/* _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); */
-+
-+							status = P2P_STATUS_SUCCESS;
-+
-+							break;
-+						} else
-+							status = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
-+
-+					}
-+					_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+				} else
-+					status = P2P_STATUS_FAIL_INVALID_PARAM;
-+
-+			} else
-+				status = P2P_STATUS_FAIL_INVALID_PARAM;
-+
-+		}
-+
-+	}
-+
-+
-+	/* issue Device Discoverability Response */
-+	issue_p2p_devdisc_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken);
-+
-+
-+	return (status == P2P_STATUS_SUCCESS) ? _TRUE : _FALSE;
-+
-+}
-+
-+u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
-+{
-+	return _TRUE;
-+}
-+
-+u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo,  u8 *pframe, uint len)
-+{
-+	u8 *frame_body;
-+	u8 *wpsie;
-+	uint	wps_ielen = 0, attr_contentlen = 0;
-+	u16	uconfig_method = 0;
-+
-+
-+	frame_body = (pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
-+
-+	wpsie = rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen);
-+	if (wpsie) {
-+		if (rtw_get_wps_attr_content(wpsie, wps_ielen, WPS_ATTR_CONF_METHOD , (u8 *) &uconfig_method, &attr_contentlen)) {
-+			uconfig_method = be16_to_cpu(uconfig_method);
-+			switch (uconfig_method) {
-+			case WPS_CM_DISPLYA: {
-+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3);
-+				break;
-+			}
-+			case WPS_CM_LABEL: {
-+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "lab", 3);
-+				break;
-+			}
-+			case WPS_CM_PUSH_BUTTON: {
-+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3);
-+				break;
-+			}
-+			case WPS_CM_KEYPAD: {
-+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3);
-+				break;
-+			}
-+			}
-+			issue_p2p_provision_resp(pwdinfo, get_addr2_ptr(pframe), frame_body, uconfig_method);
-+		}
-+	}
-+	RTW_INFO("[%s] config method = %s\n", __FUNCTION__, pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req);
-+	return _TRUE;
-+
-+}
-+
-+u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo,  u8 *pframe)
-+{
-+
-+	return _TRUE;
-+}
-+
-+u8 rtw_p2p_get_peer_ch_list(struct wifidirect_info *pwdinfo, u8 *ch_content, u8 ch_cnt, u8 *peer_ch_list)
-+{
-+	u8 i = 0, j = 0;
-+	u8 temp = 0;
-+	u8 ch_no = 0;
-+	ch_content += 3;
-+	ch_cnt -= 3;
-+
-+	while (ch_cnt > 0) {
-+		ch_content += 1;
-+		ch_cnt -= 1;
-+		temp = *ch_content;
-+		for (i = 0 ; i < temp ; i++, j++)
-+			peer_ch_list[j] = *(ch_content + 1 + i);
-+		ch_content += (temp + 1);
-+		ch_cnt -= (temp + 1);
-+		ch_no += temp ;
-+	}
-+
-+	return ch_no;
-+}
-+
-+u8 rtw_p2p_ch_inclusion(_adapter *adapter, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	int	i = 0, j = 0, temp = 0;
-+	u8 ch_no = 0;
-+
-+	for (i = 0; i < peer_ch_num; i++) {
-+		for (j = temp; j < rfctl->max_chan_nums; j++) {
-+			if (*(peer_ch_list + i) == rfctl->channel_set[j].ChannelNum) {
-+				ch_list_inclusioned[ch_no++] = *(peer_ch_list + i);
-+				temp = j;
-+				break;
-+			}
-+		}
-+	}
-+
-+	return ch_no;
-+}
-+
-+u8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
-+{
-+	_adapter *padapter = pwdinfo->padapter;
-+	u8	result = P2P_STATUS_SUCCESS;
-+	u32	p2p_ielen = 0, wps_ielen = 0;
-+	u8 *ies;
-+	u32 ies_len;
-+	u8 *p2p_ie;
-+	u8 *wpsie;
-+	u16		wps_devicepassword_id = 0x0000;
-+	uint	wps_devicepassword_id_len = 0;
-+#ifdef CONFIG_WFD
-+#ifdef CONFIG_TDLS
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+#endif /* CONFIG_TDLS	 */
-+#endif /* CONFIG_WFD */
-+	wpsie = rtw_get_wps_ie(pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen);
-+	if (wpsie) {
-+		/*	Commented by Kurt 20120113 */
-+		/*	If some device wants to do p2p handshake without sending prov_disc_req */
-+		/*	We have to get peer_req_cm from here. */
-+		if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3)) {
-+			rtw_get_wps_attr_content(wpsie, wps_ielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len);
-+			wps_devicepassword_id = be16_to_cpu(wps_devicepassword_id);
-+
-+			if (wps_devicepassword_id == WPS_DPID_USER_SPEC)
-+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3);
-+			else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)
-+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3);
-+			else
-+				_rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3);
-+		}
-+	} else {
-+		RTW_INFO("[%s] WPS IE not Found!!\n", __FUNCTION__);
-+		result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
-+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
-+		return result ;
-+	}
-+
-+	ies = pframe + _PUBLIC_ACTION_IE_OFFSET_;
-+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
-+
-+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
-+
-+	if (!p2p_ie) {
-+		RTW_INFO("[%s] P2P IE not Found!!\n", __FUNCTION__);
-+		result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
-+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
-+	}
-+
-+	while (p2p_ie) {
-+		u8	attr_content = 0x00;
-+		u32	attr_contentlen = 0;
-+		u8	ch_content[100] = { 0x00 };
-+		uint	ch_cnt = 0;
-+		u8	peer_ch_list[100] = { 0x00 };
-+		u8	peer_ch_num = 0;
-+		u8	ch_list_inclusioned[100] = { 0x00 };
-+		u8	ch_num_inclusioned = 0;
-+		u16	cap_attr;
-+		u8 listen_ch_attr[5] = { 0x00 };
-+
-+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING);
-+
-+		/* Check P2P Capability ATTR */
-+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *)&attr_contentlen)) {
-+			cap_attr = le16_to_cpu(cap_attr);
-+
-+#if defined(CONFIG_WFD) && defined(CONFIG_TDLS)
-+			if (!(cap_attr & P2P_GRPCAP_INTRABSS))
-+				ptdlsinfo->ap_prohibited = _TRUE;
-+#endif /* defined(CONFIG_WFD) && defined(CONFIG_TDLS) */
-+		}
-+
-+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen)) {
-+			RTW_INFO("[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01);
-+			pwdinfo->peer_intent = attr_content;	/*	include both intent and tie breaker values. */
-+
-+			if (pwdinfo->intent == (pwdinfo->peer_intent >> 1)) {
-+				/*	Try to match the tie breaker value */
-+				if (pwdinfo->intent == P2P_MAX_INTENT) {
-+					rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
-+					result = P2P_STATUS_FAIL_BOTH_GOINTENT_15;
-+				} else {
-+					if (attr_content & 0x01)
-+						rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
-+					else
-+						rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
-+				}
-+			} else if (pwdinfo->intent > (pwdinfo->peer_intent >> 1))
-+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
-+			else
-+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
-+
-+			if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+				/*	Store the group id information. */
-+				_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN);
-+				_rtw_memcpy(pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
-+			}
-+		}
-+
-+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8 *)listen_ch_attr, (uint *) &attr_contentlen) && attr_contentlen == 5)
-+			pwdinfo->nego_req_info.peer_ch = listen_ch_attr[4];
-+
-+		RTW_INFO(FUNC_ADPT_FMT" listen channel :%u\n", FUNC_ADPT_ARG(padapter), pwdinfo->nego_req_info.peer_ch);
-+
-+		attr_contentlen = 0;
-+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) {
-+			if (attr_contentlen != ETH_ALEN)
-+				_rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN);
-+		}
-+
-+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, ch_content, &ch_cnt)) {
-+			peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, ch_content, ch_cnt, peer_ch_list);
-+			ch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned);
-+
-+			if (ch_num_inclusioned == 0) {
-+				RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__);
-+				result = P2P_STATUS_FAIL_NO_COMMON_CH;
-+				rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
-+				break;
-+			}
-+
-+			if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+				if (!rtw_p2p_is_channel_list_ok(pwdinfo->operating_channel,
-+					ch_list_inclusioned, ch_num_inclusioned)) {
-+#ifdef CONFIG_CONCURRENT_MODE
-+					if (rtw_mi_check_status(padapter, MI_LINKED)
-+					    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
-+						RTW_INFO("[%s] desired channel NOT Found!\n", __FUNCTION__);
-+						result = P2P_STATUS_FAIL_NO_COMMON_CH;
-+						rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
-+						break;
-+					} else
-+#endif /* CONFIG_CONCURRENT_MODE */
-+					{
-+						u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0;
-+						attr_contentlen = 0;
-+
-+						if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen))
-+							peer_operating_ch = operatingch_info[4];
-+
-+						if (rtw_p2p_is_channel_list_ok(peer_operating_ch,
-+							ch_list_inclusioned, ch_num_inclusioned)) {
-+							/**
-+							 *	Change our operating channel as peer's for compatibility.
-+							 */
-+							pwdinfo->operating_channel = peer_operating_ch;
-+							RTW_INFO("[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel);
-+						} else {
-+							/* Take first channel of ch_list_inclusioned as operating channel */
-+							pwdinfo->operating_channel = ch_list_inclusioned[0];
-+							RTW_INFO("[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel);
-+						}
-+					}
-+
-+				}
-+			}
-+		}
-+
-+		/* Get the next P2P IE */
-+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
-+	}
-+
-+	if (pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO) {
-+		result = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
-+		rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INFOR_NOREADY);
-+		return result;
-+	}
-+
-+#ifdef CONFIG_WFD
-+	rtw_process_wfd_ies(padapter, pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, __func__);
-+#endif
-+
-+	return result ;
-+}
-+
-+u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
-+{
-+	_adapter *padapter = pwdinfo->padapter;
-+	u8	result = P2P_STATUS_SUCCESS;
-+	u32	p2p_ielen, wps_ielen;
-+	u8 *ies;
-+	u32 ies_len;
-+	u8 *p2p_ie;
-+#ifdef CONFIG_WFD
-+#ifdef CONFIG_TDLS
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+#endif /* CONFIG_TDLS	 */
-+#endif /* CONFIG_WFD */
-+
-+	ies = pframe + _PUBLIC_ACTION_IE_OFFSET_;
-+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
-+
-+	/*	Be able to know which one is the P2P GO and which one is P2P client. */
-+
-+	if (rtw_get_wps_ie(ies, ies_len, NULL, &wps_ielen)) {
-+
-+	} else {
-+		RTW_INFO("[%s] WPS IE not Found!!\n", __FUNCTION__);
-+		result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
-+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
-+	}
-+
-+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
-+	if (!p2p_ie) {
-+		rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
-+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
-+		result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM;
-+	} else {
-+
-+		u8	attr_content = 0x00;
-+		u32	attr_contentlen = 0;
-+		u8	operatingch_info[5] = { 0x00 };
-+		u8	groupid[38];
-+		u16	cap_attr;
-+		u8	peer_ch_list[100] = { 0x00 };
-+		u8	peer_ch_num = 0;
-+		u8	ch_list_inclusioned[100] = { 0x00 };
-+		u8	ch_num_inclusioned = 0;
-+
-+		while (p2p_ie) {	/*	Found the P2P IE. */
-+
-+			/* Check P2P Capability ATTR */
-+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *)&attr_contentlen)) {
-+				cap_attr = le16_to_cpu(cap_attr);
-+#ifdef CONFIG_TDLS
-+				if (!(cap_attr & P2P_GRPCAP_INTRABSS))
-+					ptdlsinfo->ap_prohibited = _TRUE;
-+#endif /* CONFIG_TDLS */
-+			}
-+
-+			rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);
-+			if (attr_contentlen == 1) {
-+				RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content);
-+				if (attr_content == P2P_STATUS_SUCCESS) {
-+					/*	Do nothing. */
-+				} else {
-+					if (P2P_STATUS_FAIL_INFO_UNAVAILABLE == attr_content)
-+						rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INFOR_NOREADY);
-+					else
-+						rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
-+					rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
-+					result = attr_content;
-+					break;
-+				}
-+			}
-+
-+			/*	Try to get the peer's interface address */
-+			attr_contentlen = 0;
-+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) {
-+				if (attr_contentlen != ETH_ALEN)
-+					_rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN);
-+			}
-+
-+			/*	Try to get the peer's intent and tie breaker value. */
-+			attr_content = 0x00;
-+			attr_contentlen = 0;
-+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen)) {
-+				RTW_INFO("[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01);
-+				pwdinfo->peer_intent = attr_content;	/*	include both intent and tie breaker values. */
-+
-+				if (pwdinfo->intent == (pwdinfo->peer_intent >> 1)) {
-+					/*	Try to match the tie breaker value */
-+					if (pwdinfo->intent == P2P_MAX_INTENT) {
-+						rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
-+						result = P2P_STATUS_FAIL_BOTH_GOINTENT_15;
-+						rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
-+					} else {
-+						rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
-+						rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
-+						if (attr_content & 0x01)
-+							rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
-+						else
-+							rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
-+					}
-+				} else if (pwdinfo->intent > (pwdinfo->peer_intent >> 1)) {
-+					rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
-+					rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
-+					rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
-+				} else {
-+					rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
-+					rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
-+					rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
-+				}
-+
-+				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+					/*	Store the group id information. */
-+					_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN);
-+					_rtw_memcpy(pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
-+
-+				}
-+			}
-+
-+			/*	Try to get the operation channel information */
-+
-+			attr_contentlen = 0;
-+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) {
-+				RTW_INFO("[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4]);
-+				pwdinfo->peer_operating_ch = operatingch_info[4];
-+			}
-+
-+			/*	Try to get the channel list information */
-+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, pwdinfo->channel_list_attr, &pwdinfo->channel_list_attr_len)) {
-+				RTW_INFO("[%s] channel list attribute found, len = %d\n", __FUNCTION__,  pwdinfo->channel_list_attr_len);
-+
-+				peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, pwdinfo->channel_list_attr, pwdinfo->channel_list_attr_len, peer_ch_list);
-+				ch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned);
-+
-+				if (ch_num_inclusioned == 0) {
-+					RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__);
-+					result = P2P_STATUS_FAIL_NO_COMMON_CH;
-+					rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
-+					break;
-+				}
-+
-+				if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+					if (!rtw_p2p_is_channel_list_ok(pwdinfo->operating_channel,
-+						ch_list_inclusioned, ch_num_inclusioned)) {
-+#ifdef CONFIG_CONCURRENT_MODE
-+						if (rtw_mi_check_status(padapter, MI_LINKED)
-+						    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
-+							RTW_INFO("[%s] desired channel NOT Found!\n", __FUNCTION__);
-+							result = P2P_STATUS_FAIL_NO_COMMON_CH;
-+							rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
-+							break;
-+						} else
-+#endif /* CONFIG_CONCURRENT_MODE */
-+						{
-+							u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0;
-+							attr_contentlen = 0;
-+
-+							if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen))
-+								peer_operating_ch = operatingch_info[4];
-+
-+							if (rtw_p2p_is_channel_list_ok(peer_operating_ch,
-+								ch_list_inclusioned, ch_num_inclusioned)) {
-+								/**
-+								 *	Change our operating channel as peer's for compatibility.
-+								 */
-+								pwdinfo->operating_channel = peer_operating_ch;
-+								RTW_INFO("[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel);
-+							} else {
-+								/* Take first channel of ch_list_inclusioned as operating channel */
-+								pwdinfo->operating_channel = ch_list_inclusioned[0];
-+								RTW_INFO("[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel);
-+							}
-+						}
-+
-+					}
-+				}
-+
-+			} else
-+				RTW_INFO("[%s] channel list attribute not found!\n", __FUNCTION__);
-+
-+			/*	Try to get the group id information if peer is GO */
-+			attr_contentlen = 0;
-+			_rtw_memset(groupid, 0x00, 38);
-+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) {
-+				_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN);
-+				_rtw_memcpy(pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN);
-+			}
-+
-+			/* Get the next P2P IE */
-+			p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
-+		}
-+
-+	}
-+
-+#ifdef CONFIG_WFD
-+	rtw_process_wfd_ies(padapter, pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, __func__);
-+#endif
-+
-+	return result ;
-+
-+}
-+
-+u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
-+{
-+#ifdef CONFIG_CONCURRENT_MODE
-+	_adapter *padapter = pwdinfo->padapter;
-+	struct roch_info *prochinfo = &padapter->rochinfo;
-+#endif
-+	u8 *ies;
-+	u32 ies_len;
-+	u8 *p2p_ie;
-+	u32	p2p_ielen = 0;
-+	u8	result = P2P_STATUS_SUCCESS;
-+	ies = pframe + _PUBLIC_ACTION_IE_OFFSET_;
-+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
-+
-+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
-+	while (p2p_ie) {	/*	Found the P2P IE. */
-+		u8	attr_content = 0x00, operatingch_info[5] = { 0x00 };
-+		u8	groupid[38] = { 0x00 };
-+		u32	attr_contentlen = 0;
-+
-+		pwdinfo->negotiation_dialog_token = 1;
-+		rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen);
-+		if (attr_contentlen == 1) {
-+			RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content);
-+			result = attr_content;
-+
-+			if (attr_content == P2P_STATUS_SUCCESS) {
-+
-+				_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
-+
-+				/*	Commented by Albert 20100911 */
-+				/*	Todo: Need to handle the case which both Intents are the same. */
-+				rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
-+				rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
-+				if ((pwdinfo->intent) > (pwdinfo->peer_intent >> 1))
-+					rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
-+				else if ((pwdinfo->intent) < (pwdinfo->peer_intent >> 1))
-+					rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
-+				else {
-+					/*	Have to compare the Tie Breaker */
-+					if (pwdinfo->peer_intent & 0x01)
-+						rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
-+					else
-+						rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
-+				}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+				if (rtw_mi_check_status(padapter, MI_LINKED)
-+				    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
-+					/*	Switch back to the AP channel soon. */
-+					_set_timer(&prochinfo->ap_roch_ch_switch_timer, 100);
-+				}
-+#endif
-+			} else {
-+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
-+				rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL);
-+				break;
-+			}
-+		}
-+
-+		/*	Try to get the group id information */
-+		attr_contentlen = 0;
-+		_rtw_memset(groupid, 0x00, 38);
-+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) {
-+			RTW_INFO("[%s] Ssid = %s, ssidlen = %zu\n", __FUNCTION__, &groupid[ETH_ALEN], strlen(&groupid[ETH_ALEN]));
-+			_rtw_memcpy(pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN);
-+			_rtw_memcpy(pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN);
-+		}
-+
-+		attr_contentlen = 0;
-+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) {
-+			RTW_INFO("[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4]);
-+			pwdinfo->peer_operating_ch = operatingch_info[4];
-+		}
-+
-+		/* Get the next P2P IE */
-+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
-+
-+	}
-+
-+	return result ;
-+}
-+
-+u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len)
-+{
-+	u8 *frame_body;
-+	u8 dialogToken = 0;
-+	u8 status = P2P_STATUS_SUCCESS;
-+
-+	frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
-+
-+	dialogToken = frame_body[6];
-+
-+	/* todo: check NoA attribute */
-+
-+	issue_p2p_presence_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken);
-+
-+	return _TRUE;
-+}
-+
-+void find_phase_handler(_adapter	*padapter)
-+{
-+	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct sitesurvey_parm parm;
-+	_irqL				irqL;
-+	u8					_status = 0;
-+
-+
-+	rtw_init_sitesurvey_parm(padapter, &parm);
-+	_rtw_memcpy(&parm.ssid[0].Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN);
-+	parm.ssid[0].SsidLength = P2P_WILDCARD_SSID_LEN;
-+	parm.ssid_num = 1;
-+
-+	rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+	_status = rtw_sitesurvey_cmd(padapter, &parm);
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+
-+}
-+
-+void restore_p2p_state_handler(_adapter	*padapter)
-+{
-+	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL))
-+		rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_check_status(padapter, MI_LINKED)) {
-+		u8 union_ch = rtw_mi_get_union_chan(padapter);
-+		u8 union_bw = rtw_mi_get_union_bw(padapter);
-+		u8 union_offset = rtw_mi_get_union_offset(padapter);
-+
-+		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP)) {
-+			set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
-+			rtw_back_opch(padapter);
-+		}
-+	}
-+#endif
-+
-+	rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
-+
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) {
-+#ifdef CONFIG_CONCURRENT_MODE
-+		rtw_concurrent_handler(padapter);
-+#else
-+		/*	In the P2P client mode, the driver should not switch back to its listen channel */
-+		/*	because this P2P client should stay at the operating channel of P2P GO. */
-+		set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+#endif
-+	}
-+}
-+
-+void pre_tx_invitereq_handler(_adapter	*padapter)
-+{
-+	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
-+	u8	val8 = 1;
-+
-+	set_channel_bwmode(padapter, pwdinfo->invitereq_info.peer_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+	issue_probereq_p2p(padapter, NULL);
-+	_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
-+
-+}
-+
-+void pre_tx_provdisc_handler(_adapter	*padapter)
-+{
-+	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
-+	u8	val8 = 1;
-+
-+	set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+	issue_probereq_p2p(padapter, NULL);
-+	_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
-+
-+}
-+
-+void pre_tx_negoreq_handler(_adapter	*padapter)
-+{
-+	struct wifidirect_info  *pwdinfo = &padapter->wdinfo;
-+	u8	val8 = 1;
-+
-+	set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+	rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+	issue_probereq_p2p(padapter , NULL);
-+	/* WIN Phone only accept unicast probe request when nego back */
-+	issue_probereq_p2p(padapter , pwdinfo->nego_req_info.peerDevAddr);
-+	_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
-+
-+}
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+
-+#if 0
-+static void rtw_change_p2pie_op_ch(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch)
-+{
-+	u8 *ies, *p2p_ie;
-+	u32 ies_len, p2p_ielen;
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(padapter))
-+		return;
-+#endif /* CONFIG_MCC_MODE */
-+
-+	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
-+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
-+
-+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
-+
-+	while (p2p_ie) {
-+		u32	attr_contentlen = 0;
-+		u8 *pattr = NULL;
-+
-+		/* Check P2P_ATTR_OPERATING_CH */
-+		attr_contentlen = 0;
-+		pattr = NULL;
-+		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen);
-+		if (pattr != NULL)
-+			*(pattr + 4) = ch;
-+
-+		/* Get the next P2P IE */
-+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
-+	}
-+}
-+#endif
-+
-+#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
-+static void rtw_change_p2pie_ch_list(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch)
-+{
-+	u8 *ies, *p2p_ie;
-+	u32 ies_len, p2p_ielen;
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(padapter))
-+		return;
-+#endif /* CONFIG_MCC_MODE */
-+
-+	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
-+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
-+
-+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
-+
-+	while (p2p_ie) {
-+		u32	attr_contentlen = 0;
-+		u8 *pattr = NULL;
-+
-+		/* Check P2P_ATTR_CH_LIST */
-+		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint *)&attr_contentlen);
-+		if (pattr != NULL) {
-+			int i;
-+			u32 num_of_ch;
-+			u8 *pattr_temp = pattr + 3 ;
-+
-+			attr_contentlen -= 3;
-+
-+			while (attr_contentlen > 0) {
-+				num_of_ch = *(pattr_temp + 1);
-+
-+				for (i = 0; i < num_of_ch; i++)
-+					*(pattr_temp + 2 + i) = ch;
-+
-+				pattr_temp += (2 + num_of_ch);
-+				attr_contentlen -= (2 + num_of_ch);
-+			}
-+		}
-+
-+		/* Get the next P2P IE */
-+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
-+	}
-+}
-+#endif
-+
-+#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
-+static bool rtw_chk_p2pie_ch_list_with_buddy(_adapter *padapter, const u8 *frame_body, u32 len)
-+{
-+	bool fit = _FALSE;
-+	u8 *ies, *p2p_ie;
-+	u32 ies_len, p2p_ielen;
-+	u8 union_ch = rtw_mi_get_union_chan(padapter);
-+
-+	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
-+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
-+
-+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
-+
-+	while (p2p_ie) {
-+		u32	attr_contentlen = 0;
-+		u8 *pattr = NULL;
-+
-+		/* Check P2P_ATTR_CH_LIST */
-+		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint *)&attr_contentlen);
-+		if (pattr != NULL) {
-+			int i;
-+			u32 num_of_ch;
-+			u8 *pattr_temp = pattr + 3 ;
-+
-+			attr_contentlen -= 3;
-+
-+			while (attr_contentlen > 0) {
-+				num_of_ch = *(pattr_temp + 1);
-+
-+				for (i = 0; i < num_of_ch; i++) {
-+					if (*(pattr_temp + 2 + i) == union_ch) {
-+						RTW_INFO(FUNC_ADPT_FMT" ch_list fit buddy_ch:%u\n", FUNC_ADPT_ARG(padapter), union_ch);
-+						fit = _TRUE;
-+						break;
-+					}
-+				}
-+
-+				pattr_temp += (2 + num_of_ch);
-+				attr_contentlen -= (2 + num_of_ch);
-+			}
-+		}
-+
-+		/* Get the next P2P IE */
-+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
-+	}
-+
-+	return fit;
-+}
-+
-+#if defined(CONFIG_P2P_INVITE_IOT)
-+static bool rtw_chk_p2pie_op_ch_with_buddy(_adapter *padapter, const u8 *frame_body, u32 len)
-+{
-+	bool fit = _FALSE;
-+	u8 *ies, *p2p_ie;
-+	u32 ies_len, p2p_ielen;
-+	u8 union_ch = rtw_mi_get_union_chan(padapter);
-+
-+	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
-+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
-+
-+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
-+
-+	while (p2p_ie) {
-+		u32	attr_contentlen = 0;
-+		u8 *pattr = NULL;
-+
-+		/* Check P2P_ATTR_OPERATING_CH */
-+		attr_contentlen = 0;
-+		pattr = NULL;
-+		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen);
-+		if (pattr != NULL) {
-+			if (*(pattr + 4) == union_ch) {
-+				RTW_INFO(FUNC_ADPT_FMT" op_ch fit buddy_ch:%u\n", FUNC_ADPT_ARG(padapter), union_ch);
-+				fit = _TRUE;
-+				break;
-+			}
-+		}
-+
-+		/* Get the next P2P IE */
-+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
-+	}
-+
-+	return fit;
-+}
-+#endif
-+
-+static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *frame_body, u32 len)
-+{
-+	u8 *ies, *p2p_ie;
-+	u32 ies_len, p2p_ielen;
-+	u8 union_ch = rtw_mi_get_union_chan(padapter);
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(padapter))
-+		return;
-+#endif /* CONFIG_MCC_MODE */
-+
-+	ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
-+	ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
-+
-+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
-+
-+	while (p2p_ie) {
-+		u32	attr_contentlen = 0;
-+		u8 *pattr = NULL;
-+
-+		/* Check P2P_ATTR_CH_LIST */
-+		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint *)&attr_contentlen);
-+		if (pattr != NULL) {
-+			int i;
-+			u32 num_of_ch;
-+			u8 *pattr_temp = pattr + 3 ;
-+
-+			attr_contentlen -= 3;
-+
-+			while (attr_contentlen > 0) {
-+				num_of_ch = *(pattr_temp + 1);
-+
-+				for (i = 0; i < num_of_ch; i++) {
-+					if (*(pattr_temp + 2 + i) && *(pattr_temp + 2 + i) != union_ch) {
-+						#ifdef RTW_SINGLE_WIPHY
-+						RTW_ERR("replace ch_list:%u with:%u\n", *(pattr_temp + 2 + i), union_ch);
-+						#endif
-+						*(pattr_temp + 2 + i) = union_ch; /*forcing to the same channel*/
-+					}
-+				}
-+
-+				pattr_temp += (2 + num_of_ch);
-+				attr_contentlen -= (2 + num_of_ch);
-+			}
-+		}
-+
-+		/* Check P2P_ATTR_OPERATING_CH */
-+		attr_contentlen = 0;
-+		pattr = NULL;
-+		pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen);
-+		if (pattr != NULL) {
-+			if (*(pattr + 4) && *(pattr + 4) != union_ch) {
-+				#ifdef RTW_SINGLE_WIPHY
-+				RTW_ERR("replace op_ch:%u with:%u\n", *(pattr + 4), union_ch);
-+				#endif
-+				*(pattr + 4) = union_ch; /*forcing to the same channel	*/
-+			}
-+		}
-+
-+		/* Get the next P2P IE */
-+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
-+
-+	}
-+
-+}
-+#endif
-+
-+#ifdef CONFIG_WFD
-+u32 rtw_xframe_build_wfd_ie(struct xmit_frame *xframe)
-+{
-+	_adapter *adapter = xframe->padapter;
-+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
-+	u8 *frame = xframe->buf_addr + TXDESC_OFFSET;
-+	u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	u8 *frame_tail = frame + xframe->attrib.pktlen;
-+	u8 category, action, OUI_Subtype, dialogToken = 0;
-+	u32	wfdielen = 0;
-+
-+	category = frame_body[0];
-+	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
-+		action = frame_body[1];
-+		if (action == ACT_PUBLIC_VENDOR
-+		    && _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE
-+		   ) {
-+			OUI_Subtype = frame_body[6];
-+			dialogToken = frame_body[7];
-+
-+			switch (OUI_Subtype) {
-+			case P2P_GO_NEGO_REQ:
-+				wfdielen = build_nego_req_wfd_ie(wdinfo, frame_tail);
-+				break;
-+			case P2P_GO_NEGO_RESP:
-+				wfdielen = build_nego_resp_wfd_ie(wdinfo, frame_tail);
-+				break;
-+			case P2P_GO_NEGO_CONF:
-+				wfdielen = build_nego_confirm_wfd_ie(wdinfo, frame_tail);
-+				break;
-+			case P2P_INVIT_REQ:
-+				wfdielen = build_invitation_req_wfd_ie(wdinfo, frame_tail);
-+				break;
-+			case P2P_INVIT_RESP:
-+				wfdielen = build_invitation_resp_wfd_ie(wdinfo, frame_tail);
-+				break;
-+			case P2P_PROVISION_DISC_REQ:
-+				wfdielen = build_provdisc_req_wfd_ie(wdinfo, frame_tail);
-+				break;
-+			case P2P_PROVISION_DISC_RESP:
-+				wfdielen = build_provdisc_resp_wfd_ie(wdinfo, frame_tail);
-+				break;
-+			case P2P_DEVDISC_REQ:
-+			case P2P_DEVDISC_RESP:
-+			default:
-+				break;
-+			}
-+
-+		}
-+	} else if (category == RTW_WLAN_CATEGORY_P2P) {
-+		OUI_Subtype = frame_body[5];
-+		dialogToken = frame_body[6];
-+
-+#ifdef CONFIG_DEBUG_CFG80211
-+		RTW_INFO("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n"
-+			, cpu_to_be32(*((u32 *)(frame_body + 1))), OUI_Subtype, dialogToken);
-+#endif
-+
-+		switch (OUI_Subtype) {
-+		case P2P_NOTICE_OF_ABSENCE:
-+			break;
-+		case P2P_PRESENCE_REQUEST:
-+			break;
-+		case P2P_PRESENCE_RESPONSE:
-+			break;
-+		case P2P_GO_DISC_REQUEST:
-+			break;
-+		default:
-+			break;
-+		}
-+	} else
-+		RTW_INFO("%s, action frame category=%d\n", __func__, category);
-+
-+	xframe->attrib.pktlen += wfdielen;
-+
-+	return wfdielen;
-+}
-+#endif /* CONFIG_WFD */
-+
-+bool rtw_xframe_del_wfd_ie(struct xmit_frame *xframe)
-+{
-+#define DBG_XFRAME_DEL_WFD_IE 0
-+	u8 *frame = xframe->buf_addr + TXDESC_OFFSET;
-+	u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	u8 *frame_tail = frame + xframe->attrib.pktlen;
-+	u8 category, action, OUI_Subtype;
-+	u8 *ies = NULL;
-+	uint ies_len_ori = 0;
-+	uint ies_len = 0;
-+
-+	category = frame_body[0];
-+	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
-+		action = frame_body[1];
-+		if (action == ACT_PUBLIC_VENDOR
-+		    && _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE
-+		   ) {
-+			OUI_Subtype = frame_body[6];
-+
-+			switch (OUI_Subtype) {
-+			case P2P_GO_NEGO_REQ:
-+			case P2P_GO_NEGO_RESP:
-+			case P2P_GO_NEGO_CONF:
-+			case P2P_INVIT_REQ:
-+			case P2P_INVIT_RESP:
-+			case P2P_PROVISION_DISC_REQ:
-+			case P2P_PROVISION_DISC_RESP:
-+				ies = frame_body + 8;
-+				ies_len_ori = frame_tail - (frame_body + 8);
-+				break;
-+			}
-+		}
-+	}
-+
-+	if (ies && ies_len_ori) {
-+		ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_XFRAME_DEL_WFD_IE ? __func__ : NULL);
-+		xframe->attrib.pktlen -= (ies_len_ori - ies_len);
-+	}
-+
-+	return ies_len_ori != ies_len;
-+}
-+
-+/*
-+* rtw_xframe_chk_wfd_ie -
-+*
-+*/
-+void rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe)
-+{
-+	_adapter *adapter = xframe->padapter;
-+#ifdef CONFIG_IOCTL_CFG80211
-+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
-+#endif
-+	u8 build = 0;
-+	u8 del = 0;
-+
-+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
-+		del = 1;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (wdinfo->wfd_info->wfd_enable == _TRUE)
-+#endif
-+		del = build = 1;
-+
-+	if (del)
-+		rtw_xframe_del_wfd_ie(xframe);
-+
-+#ifdef CONFIG_WFD
-+	if (build)
-+		rtw_xframe_build_wfd_ie(xframe);
-+#endif
-+}
-+
-+u8 *dump_p2p_attr_ch_list(u8 *p2p_ie, uint p2p_ielen, u8 *buf, u32 buf_len)
-+{
-+	uint attr_contentlen = 0;
-+	u8 *pattr = NULL;
-+	int w_sz = 0;
-+	u8 ch_cnt = 0;
-+	u8 ch_list[40];
-+
-+	pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, &attr_contentlen);
-+	if (pattr != NULL) {
-+		int i, j;
-+		u32 num_of_ch;
-+		u8 *pattr_temp = pattr + 3 ;
-+
-+		attr_contentlen -= 3;
-+
-+		_rtw_memset(ch_list, 0, 40);
-+
-+		while (attr_contentlen > 0) {
-+			num_of_ch = *(pattr_temp + 1);
-+
-+			for (i = 0; i < num_of_ch; i++) {
-+				for (j = 0; j < ch_cnt; j++) {
-+					if (ch_list[j] == *(pattr_temp + 2 + i))
-+						break;
-+				}
-+				if (j >= ch_cnt)
-+					ch_list[ch_cnt++] = *(pattr_temp + 2 + i);
-+
-+			}
-+
-+			pattr_temp += (2 + num_of_ch);
-+			attr_contentlen -= (2 + num_of_ch);
-+		}
-+
-+		for (j = 0; j < ch_cnt; j++) {
-+			if (j == 0)
-+				w_sz += snprintf(buf + w_sz, buf_len - w_sz, "%u", ch_list[j]);
-+			else if (ch_list[j] - ch_list[j - 1] != 1)
-+				w_sz += snprintf(buf + w_sz, buf_len - w_sz, ", %u", ch_list[j]);
-+			else if (j != ch_cnt - 1 && ch_list[j + 1] - ch_list[j] == 1) {
-+				/* empty */
-+			} else
-+				w_sz += snprintf(buf + w_sz, buf_len - w_sz, "-%u", ch_list[j]);
-+		}
-+	}
-+	return buf;
-+}
-+
-+/*
-+ * return _TRUE if requester is GO, _FALSE if responder is GO
-+ */
-+bool rtw_p2p_nego_intent_compare(u8 req, u8 resp)
-+{
-+	if (req >> 1 == resp >> 1)
-+		return  req & 0x01 ? _TRUE : _FALSE;
-+	else if (req >> 1 > resp >> 1)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
-+{
-+	int is_p2p_frame = (-1);
-+	unsigned char	*frame_body;
-+	u8 category, action, OUI_Subtype, dialogToken = 0;
-+	u8 *p2p_ie = NULL;
-+	uint p2p_ielen = 0;
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+	int status = -1;
-+	u8 ch_list_buf[128] = {'\0'};
-+	int op_ch = -1;
-+	int listen_ch = -1;
-+	u8 intent = 0;
-+	u8 *iaddr = NULL;
-+	u8 *gbssid = NULL;
-+
-+	frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr));
-+	category = frame_body[0];
-+	/* just for check */
-+	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
-+		action = frame_body[1];
-+		if (action == ACT_PUBLIC_VENDOR
-+			&& _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE
-+		) {
-+			OUI_Subtype = frame_body[6];
-+			dialogToken = frame_body[7];
-+			is_p2p_frame = OUI_Subtype;
-+
-+			#ifdef CONFIG_DEBUG_CFG80211
-+			RTW_INFO("ACTION_CATEGORY_PUBLIC: ACT_PUBLIC_VENDOR, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n",
-+				cpu_to_be32(*((u32 *)(frame_body + 2))), OUI_Subtype, dialogToken);
-+			#endif
-+
-+			p2p_ie = rtw_get_p2p_ie(
-+				(u8 *)buf + sizeof(struct rtw_ieee80211_hdr_3addr) + _PUBLIC_ACTION_IE_OFFSET_
-+				, len - sizeof(struct rtw_ieee80211_hdr_3addr) - _PUBLIC_ACTION_IE_OFFSET_
-+				, NULL, &p2p_ielen);
-+
-+			switch (OUI_Subtype) { /* OUI Subtype */
-+				u8 *cont;
-+				uint cont_len;
-+			case P2P_GO_NEGO_REQ: {
-+				struct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info;
-+
-+				if (tx) {
-+					#ifdef CONFIG_DRV_ISSUE_PROV_REQ /* IOT FOR S2 */
-+					if (pwdev_priv->provdisc_req_issued == _FALSE)
-+						rtw_cfg80211_issue_p2p_provision_request(padapter, buf, len);
-+					#endif /* CONFIG_DRV_ISSUE_PROV_REQ */
-+
-+					/* pwdev_priv->provdisc_req_issued = _FALSE; */
-+
-+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
-+					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
-+						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
-+					#endif
-+				}
-+
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
-+				if (cont)
-+					op_ch = *(cont + 4);
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, NULL, &cont_len);
-+				if (cont)
-+					listen_ch = *(cont + 4);
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len);
-+				if (cont)
-+					intent = *cont;
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, NULL, &cont_len);
-+				if (cont && cont_len == 6)
-+					iaddr = cont;
-+
-+				if (nego_info->token != dialogToken)
-+					rtw_wdev_nego_info_init(nego_info);
-+
-+				_rtw_memcpy(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN);
-+				if (iaddr)
-+					_rtw_memcpy(tx ? nego_info->iface_addr : nego_info->peer_iface_addr, iaddr, ETH_ALEN);
-+				nego_info->active = tx ? 1 : 0;
-+				nego_info->token = dialogToken;
-+				nego_info->req_op_ch = op_ch;
-+				nego_info->req_listen_ch = listen_ch;
-+				nego_info->req_intent = intent;
-+				nego_info->state = 0;
-+
-+				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
-+				RTW_INFO("RTW_%s:P2P_GO_NEGO_REQ, dialogToken=%d, intent:%u%s, listen_ch:%d, op_ch:%d, ch_list:%s"
-+					, (tx == _TRUE) ? "Tx" : "Rx" , dialogToken , (intent >> 1) , intent & 0x1 ? "+" : "-" , listen_ch , op_ch , ch_list_buf);
-+				if (iaddr)
-+					_RTW_INFO(", iaddr:"MAC_FMT, MAC_ARG(iaddr));
-+				_RTW_INFO("\n");
-+
-+				if (!tx) {
-+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
-+					if (rtw_mi_check_status(padapter, MI_LINKED)
-+					    && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE
-+					    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
-+						RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
-+						rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
-+					}
-+					#endif
-+				}
-+
-+				break;
-+			}
-+			case P2P_GO_NEGO_RESP: {
-+				struct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info;
-+
-+				if (tx) {
-+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
-+					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
-+						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
-+					#endif
-+				}
-+
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
-+				if (cont)
-+					op_ch = *(cont + 4);
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len);
-+				if (cont)
-+					intent = *cont;
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
-+				if (cont)
-+					status = *cont;
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, NULL, &cont_len);
-+				if (cont && cont_len == 6)
-+					iaddr = cont;
-+
-+				if (nego_info->token == dialogToken && nego_info->state == 0
-+					&& _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE
-+				) {
-+					if (iaddr)
-+						_rtw_memcpy(tx ? nego_info->iface_addr : nego_info->peer_iface_addr, iaddr, ETH_ALEN);
-+					nego_info->status = (status == -1) ? 0xff : status;
-+					nego_info->rsp_op_ch = op_ch;
-+					nego_info->rsp_intent = intent;
-+					nego_info->state = 1;
-+					if (status != 0)
-+						nego_info->token = 0; /* init */
-+				}
-+
-+				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
-+				RTW_INFO("RTW_%s:P2P_GO_NEGO_RESP, dialogToken=%d, intent:%u%s, status:%d, op_ch:%d, ch_list:%s"
-+					, (tx == _TRUE) ? "Tx" : "Rx", dialogToken, (intent >> 1), intent & 0x1 ? "+" : "-", status, op_ch, ch_list_buf);
-+				if (iaddr)
-+					_RTW_INFO(", iaddr:"MAC_FMT, MAC_ARG(iaddr));
-+				_RTW_INFO("\n");
-+
-+				if (!tx) {
-+					pwdev_priv->provdisc_req_issued = _FALSE;
-+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
-+					if (rtw_mi_check_status(padapter, MI_LINKED)
-+					    && rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE
-+					    && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
-+						RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
-+						rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
-+					}
-+					#endif
-+				}
-+
-+				break;
-+			}
-+			case P2P_GO_NEGO_CONF: {
-+				struct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info;
-+				bool is_go = _FALSE;
-+
-+				if (tx) {
-+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
-+					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
-+						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
-+					#endif
-+				}
-+
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
-+				if (cont)
-+					op_ch = *(cont + 4);
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
-+				if (cont)
-+					status = *cont;
-+
-+				if (nego_info->token == dialogToken && nego_info->state == 1
-+				    && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE
-+				   ) {
-+					nego_info->status = (status == -1) ? 0xff : status;
-+					nego_info->conf_op_ch = (op_ch == -1) ? 0 : op_ch;
-+					nego_info->state = 2;
-+
-+					if (status == 0) {
-+						if (rtw_p2p_nego_intent_compare(nego_info->req_intent, nego_info->rsp_intent) ^ !tx)
-+							is_go = _TRUE;
-+					}
-+
-+					nego_info->token = 0; /* init */
-+				}
-+
-+				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
-+				RTW_INFO("RTW_%s:P2P_GO_NEGO_CONF, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n"
-+					, (tx == _TRUE) ? "Tx" : "Rx", dialogToken, status, op_ch, ch_list_buf);
-+
-+				if (!tx) {
-+				}
-+
-+				break;
-+			}
-+			case P2P_INVIT_REQ: {
-+				struct rtw_wdev_invit_info *invit_info = &pwdev_priv->invit_info;
-+				int flags = -1;
-+
-+				if (tx) {
-+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
-+					if (rtw_mi_check_status(padapter, MI_LINKED)
-+					    && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
-+						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
-+					#endif
-+				}
-+
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INVITATION_FLAGS, NULL, &cont_len);
-+				if (cont)
-+					flags = *cont;
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
-+				if (cont)
-+					op_ch = *(cont + 4);
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_BSSID, NULL, &cont_len);
-+				if (cont && cont_len == 6)
-+					gbssid = cont;
-+
-+				if (invit_info->token != dialogToken)
-+					rtw_wdev_invit_info_init(invit_info);
-+
-+				_rtw_memcpy(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN);
-+				if (gbssid)
-+					_rtw_memcpy(invit_info->group_bssid, gbssid, ETH_ALEN);
-+				invit_info->active = tx ? 1 : 0;
-+				invit_info->token = dialogToken;
-+				invit_info->flags = (flags == -1) ? 0x0 : flags;
-+				invit_info->req_op_ch = op_ch;
-+				invit_info->state = 0;
-+
-+				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
-+				RTW_INFO("RTW_%s:P2P_INVIT_REQ, dialogToken=%d, flags:0x%02x, op_ch:%d, ch_list:%s"
-+					, (tx == _TRUE) ? "Tx" : "Rx", dialogToken, flags, op_ch, ch_list_buf);
-+				if (gbssid)
-+					_RTW_INFO(", gbssid:"MAC_FMT, MAC_ARG(gbssid));
-+				_RTW_INFO("\n");
-+
-+				if (!tx) {
-+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
-+					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
-+						#if defined(CONFIG_P2P_INVITE_IOT)
-+						if (op_ch != -1 && rtw_chk_p2pie_op_ch_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) {
-+							RTW_INFO(FUNC_ADPT_FMT" op_ch:%u has no intersect with buddy\n", FUNC_ADPT_ARG(padapter), op_ch);
-+							rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
-+						} else
-+						#endif
-+						if (rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) {
-+							RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
-+							rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
-+						}
-+					}
-+					#endif
-+				}
-+
-+				break;
-+			}
-+			case P2P_INVIT_RESP: {
-+				struct rtw_wdev_invit_info *invit_info = &pwdev_priv->invit_info;
-+
-+				if (tx) {
-+					#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
-+					if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
-+						rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
-+					#endif
-+				}
-+
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
-+				if (cont) {
-+					#ifdef CONFIG_P2P_INVITE_IOT
-+					if (tx && *cont == 7) {
-+						RTW_INFO("TX_P2P_INVITE_RESP, status is no common channel, change to unknown group\n");
-+						*cont = 8; /* unknow group status */
-+					}
-+					#endif /* CONFIG_P2P_INVITE_IOT */
-+					status = *cont;
-+				}
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
-+				if (cont)
-+					op_ch = *(cont + 4);
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_BSSID, NULL, &cont_len);
-+				if (cont && cont_len == 6)
-+					gbssid = cont;
-+
-+				if (invit_info->token == dialogToken && invit_info->state == 0
-+				    && _rtw_memcmp(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE
-+				   ) {
-+					invit_info->status = (status == -1) ? 0xff : status;
-+					invit_info->rsp_op_ch = op_ch;
-+					invit_info->state = 1;
-+					invit_info->token = 0; /* init */
-+				}
-+
-+				dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
-+				RTW_INFO("RTW_%s:P2P_INVIT_RESP, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s"
-+					, (tx == _TRUE) ? "Tx" : "Rx", dialogToken, status, op_ch, ch_list_buf);
-+				if (gbssid)
-+					_RTW_INFO(", gbssid:"MAC_FMT, MAC_ARG(gbssid));
-+				_RTW_INFO("\n");
-+
-+				if (!tx) {
-+				}
-+
-+				break;
-+			}
-+			case P2P_DEVDISC_REQ:
-+				RTW_INFO("RTW_%s:P2P_DEVDISC_REQ, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
-+				break;
-+			case P2P_DEVDISC_RESP:
-+				cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
-+				RTW_INFO("RTW_%s:P2P_DEVDISC_RESP, dialogToken=%d, status:%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken, cont ? *cont : -1);
-+				break;
-+			case P2P_PROVISION_DISC_REQ: {
-+				size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr);
-+				u8 *p2p_ie;
-+				uint p2p_ielen = 0;
-+				uint contentlen = 0;
-+
-+				RTW_INFO("RTW_%s:P2P_PROVISION_DISC_REQ, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
-+
-+				/* if(tx) */
-+				{
-+					pwdev_priv->provdisc_req_issued = _FALSE;
-+
-+					p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen);
-+					if (p2p_ie) {
-+
-+						if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, NULL, &contentlen)) {
-+							pwdev_priv->provdisc_req_issued = _FALSE;/* case: p2p_client join p2p GO */
-+						} else {
-+							#ifdef CONFIG_DEBUG_CFG80211
-+							RTW_INFO("provdisc_req_issued is _TRUE\n");
-+							#endif /*CONFIG_DEBUG_CFG80211*/
-+							pwdev_priv->provdisc_req_issued = _TRUE;/* case: p2p_devices connection before Nego req. */
-+						}
-+
-+					}
-+				}
-+			}
-+			break;
-+			case P2P_PROVISION_DISC_RESP:
-+				RTW_INFO("RTW_%s:P2P_PROVISION_DISC_RESP, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
-+				break;
-+			default:
-+				RTW_INFO("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", OUI_Subtype, dialogToken);
-+				break;
-+			}
-+
-+		}
-+
-+	} else if (category == RTW_WLAN_CATEGORY_P2P) {
-+		OUI_Subtype = frame_body[5];
-+		dialogToken = frame_body[6];
-+
-+		#ifdef CONFIG_DEBUG_CFG80211
-+		RTW_INFO("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n",
-+			cpu_to_be32(*((u32 *)(frame_body + 1))), OUI_Subtype, dialogToken);
-+		#endif
-+
-+		is_p2p_frame = OUI_Subtype;
-+
-+		switch (OUI_Subtype) {
-+		case P2P_NOTICE_OF_ABSENCE:
-+			RTW_INFO("RTW_%s:P2P_NOTICE_OF_ABSENCE, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
-+			break;
-+		case P2P_PRESENCE_REQUEST:
-+			RTW_INFO("RTW_%s:P2P_PRESENCE_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
-+			break;
-+		case P2P_PRESENCE_RESPONSE:
-+			RTW_INFO("RTW_%s:P2P_PRESENCE_RESPONSE, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
-+			break;
-+		case P2P_GO_DISC_REQUEST:
-+			RTW_INFO("RTW_%s:P2P_GO_DISC_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
-+			break;
-+		default:
-+			RTW_INFO("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", OUI_Subtype, dialogToken);
-+			break;
-+		}
-+
-+	}
-+
-+	return is_p2p_frame;
-+}
-+#endif /* CONFIG_IOCTL_CFG80211	 */
-+
-+s32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf)
-+{
-+	int ret = H2C_SUCCESS;
-+
-+	switch (intCmdType) {
-+	case P2P_FIND_PHASE_WK:
-+		find_phase_handler(padapter);
-+		break;
-+
-+	case P2P_RESTORE_STATE_WK:
-+		restore_p2p_state_handler(padapter);
-+		break;
-+
-+	case P2P_PRE_TX_PROVDISC_PROCESS_WK:
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED))
-+			rtw_concurrent_handler(padapter);
-+		else
-+			pre_tx_provdisc_handler(padapter);
-+#else
-+		pre_tx_provdisc_handler(padapter);
-+#endif
-+		break;
-+
-+	case P2P_PRE_TX_INVITEREQ_PROCESS_WK:
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED))
-+			rtw_concurrent_handler(padapter);
-+		else
-+			pre_tx_invitereq_handler(padapter);
-+#else
-+		pre_tx_invitereq_handler(padapter);
-+#endif
-+		break;
-+
-+	case P2P_PRE_TX_NEGOREQ_PROCESS_WK:
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED))
-+			rtw_concurrent_handler(padapter);
-+		else
-+			pre_tx_negoreq_handler(padapter);
-+#else
-+		pre_tx_negoreq_handler(padapter);
-+#endif
-+		break;
-+
-+	default:
-+		rtw_warn_on(1);
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength)
-+{
-+	int ret = _TRUE;
-+	u8 *ies;
-+	u32 ies_len;
-+	u8 *p2p_ie;
-+	u32	p2p_ielen = 0;
-+	u8	p2p_attr[MAX_P2P_IE_LEN] = { 0x00 };/* NoA length should be n*(13) + 2 */
-+	u32	attr_contentlen = 0;
-+
-+
-+
-+	if (IELength <= _BEACON_IE_OFFSET_)
-+		return ret;
-+
-+	ies = IEs + _BEACON_IE_OFFSET_;
-+	ies_len = IELength - _BEACON_IE_OFFSET_;
-+
-+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
-+
-+	while (p2p_ie) {
-+		/* Get P2P Manageability IE. */
-+		if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_MANAGEABILITY, p2p_attr, &attr_contentlen)) {
-+			if ((p2p_attr[0] & (BIT(0) | BIT(1))) == 0x01)
-+				ret = _FALSE;
-+			break;
-+		}
-+		/* Get the next P2P IE */
-+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
-+	}
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_P2P_PS
-+void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength)
-+{
-+	u8 *ies;
-+	u32 ies_len;
-+	u8 *p2p_ie;
-+	u32	p2p_ielen = 0;
-+	u8 *noa_attr; /* NoA length should be n*(13) + 2 */
-+	u32	attr_contentlen = 0;
-+
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	u8	find_p2p = _FALSE, find_p2p_ps = _FALSE;
-+	u8	noa_offset, noa_num, noa_index;
-+
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
-+		return;
-+#ifdef CONFIG_CONCURRENT_MODE
-+#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
-+	if (padapter->hw_port != HW_PORT0)
-+		return;
-+#endif
-+#endif
-+	if (IELength <= _BEACON_IE_OFFSET_)
-+		return;
-+
-+	ies = IEs + _BEACON_IE_OFFSET_;
-+	ies_len = IELength - _BEACON_IE_OFFSET_;
-+
-+	p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen);
-+
-+	while (p2p_ie) {
-+		find_p2p = _TRUE;
-+		/* Get Notice of Absence IE. */
-+		noa_attr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_NOA, NULL, &attr_contentlen);
-+		if (noa_attr) {
-+			find_p2p_ps = _TRUE;
-+			noa_index = noa_attr[0];
-+
-+			if ((pwdinfo->p2p_ps_mode == P2P_PS_NONE) ||
-+			    (noa_index != pwdinfo->noa_index)) { /* if index change, driver should reconfigure related setting. */
-+				pwdinfo->noa_index = noa_index;
-+				pwdinfo->opp_ps = noa_attr[1] >> 7;
-+				if (pwdinfo->opp_ps != 1)
-+					pwdinfo->ctwindow = 0;
-+				else
-+					pwdinfo->ctwindow = noa_attr[1] & 0x7F;
-+				noa_offset = 2;
-+				noa_num = 0;
-+				/* NoA length should be n*(13) + 2 */
-+				if (attr_contentlen > 2 && (attr_contentlen - 2) % 13 == 0) {
-+					while (noa_offset < attr_contentlen && noa_num < P2P_MAX_NOA_NUM) {
-+						/* _rtw_memcpy(&wifidirect_info->noa_count[noa_num], &noa_attr[noa_offset], 1); */
-+						pwdinfo->noa_count[noa_num] = noa_attr[noa_offset];
-+						noa_offset += 1;
-+
-+						_rtw_memcpy(&pwdinfo->noa_duration[noa_num], &noa_attr[noa_offset], 4);
-+						noa_offset += 4;
-+
-+						_rtw_memcpy(&pwdinfo->noa_interval[noa_num], &noa_attr[noa_offset], 4);
-+						noa_offset += 4;
-+
-+						_rtw_memcpy(&pwdinfo->noa_start_time[noa_num], &noa_attr[noa_offset], 4);
-+						noa_offset += 4;
-+
-+						noa_num++;
-+					}
-+				}
-+				pwdinfo->noa_num = noa_num;
-+
-+				if (pwdinfo->opp_ps == 1) {
-+					pwdinfo->p2p_ps_mode = P2P_PS_CTWINDOW;
-+					/* driver should wait LPS for entering CTWindow */
-+					if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)
-+						p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1);
-+				} else if (pwdinfo->noa_num > 0) {
-+					pwdinfo->p2p_ps_mode = P2P_PS_NOA;
-+					p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1);
-+				} else if (pwdinfo->p2p_ps_mode > P2P_PS_NONE)
-+					p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);
-+			}
-+
-+			break; /* find target, just break. */
-+		}
-+
-+		/* Get the next P2P IE */
-+		p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
-+
-+	}
-+
-+	if (find_p2p == _TRUE) {
-+		if ((pwdinfo->p2p_ps_mode > P2P_PS_NONE) && (find_p2p_ps == _FALSE))
-+			p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);
-+	}
-+
-+}
-+
-+void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state)
-+{
-+	struct pwrctrl_priv		*pwrpriv = adapter_to_pwrctl(padapter);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	u32 ps_deny = 0;
-+
-+	/* Pre action for p2p state */
-+	switch (p2p_ps_state) {
-+	case P2P_PS_DISABLE:
-+		pwdinfo->p2p_ps_state = p2p_ps_state;
-+
-+		rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));
-+
-+#ifdef CONFIG_LPS
-+		if (pwdinfo->opp_ps == 1) {
-+			if (pwrpriv->smart_ps == 0) {
-+				pwrpriv->smart_ps = 2;
-+				if (pwrpriv->pwr_mode != PS_MODE_ACTIVE)
-+					rtw_exec_lps(padapter, pwrpriv->pwr_mode);
-+			}
-+		}
-+#endif /* CONFIG_LPS */
-+
-+		pwdinfo->noa_index = 0;
-+		pwdinfo->ctwindow = 0;
-+		pwdinfo->opp_ps = 0;
-+		pwdinfo->noa_num = 0;
-+		pwdinfo->p2p_ps_mode = P2P_PS_NONE;
-+
-+		break;
-+	case P2P_PS_ENABLE:
-+		_enter_pwrlock(&adapter_to_pwrctl(padapter)->lock);
-+		ps_deny = rtw_ps_deny_get(padapter);
-+		_exit_pwrlock(&adapter_to_pwrctl(padapter)->lock);
-+
-+		if ((ps_deny & (PS_DENY_SCAN | PS_DENY_JOIN))
-+			|| rtw_mi_check_fwstate(padapter, (WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING))) {
-+			pwdinfo->p2p_ps_mode = P2P_PS_NONE;
-+			RTW_DBG(FUNC_ADPT_FMT" Block P2P PS under site survey or LINKING\n", FUNC_ADPT_ARG(padapter));
-+			return;
-+		}
-+		if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) {
-+#ifdef CONFIG_MCC_MODE
-+			if (MCC_EN(padapter)) {
-+				if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
-+					RTW_INFO("P2P PS enble under MCC\n");
-+					rtw_warn_on(1);
-+				}
-+
-+			}
-+#endif /* CONFIG_MCC_MODE */
-+			pwdinfo->p2p_ps_state = p2p_ps_state;
-+
-+#ifdef CONFIG_LPS
-+			if (pwdinfo->ctwindow > 0) {
-+				if (pwrpriv->smart_ps != 0) {
-+					pwrpriv->smart_ps = 0;
-+					RTW_INFO("%s(): Enter CTW, change SmartPS\n", __FUNCTION__);
-+					if (pwrpriv->pwr_mode != PS_MODE_ACTIVE)
-+						rtw_exec_lps(padapter, pwrpriv->pwr_mode);
-+				}
-+			}
-+#endif /* CONFIG_LPS */
-+
-+			rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));
-+		}
-+		break;
-+	case P2P_PS_SCAN:
-+	case P2P_PS_SCAN_DONE:
-+	case P2P_PS_ALLSTASLEEP:
-+		if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) {
-+			pwdinfo->p2p_ps_state = p2p_ps_state;
-+			rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state));
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+
-+#ifdef CONFIG_MCC_MODE
-+	rtw_hal_mcc_process_noa(padapter);
-+#endif /* CONFIG_MCC_MODE */
-+}
-+
-+u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue)
-+{
-+	struct cmd_obj	*ph2c;
-+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm;
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+	u8	res = _SUCCESS;
-+
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
-+#ifdef CONFIG_CONCURRENT_MODE
-+#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
-+	    || (padapter->hw_port != HW_PORT0)
-+#endif
-+#endif
-+	   )
-+		return res;
-+
-+	if (enqueue) {
-+		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+		if (ph2c == NULL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+		if (pdrvextra_cmd_parm == NULL) {
-+			rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		pdrvextra_cmd_parm->ec_id = P2P_PS_WK_CID;
-+		pdrvextra_cmd_parm->type = p2p_ps_state;
-+		pdrvextra_cmd_parm->size = 0;
-+		pdrvextra_cmd_parm->pbuf = NULL;
-+
-+		init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+	} else
-+		p2p_ps_wk_hdl(padapter, p2p_ps_state);
-+
-+exit:
-+
-+
-+	return res;
-+
-+}
-+#endif /* CONFIG_P2P_PS */
-+
-+static void reset_ch_sitesurvey_timer_process(void *FunctionContext)
-+{
-+	_adapter *adapter = (_adapter *)FunctionContext;
-+	struct	wifidirect_info		*pwdinfo = &adapter->wdinfo;
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
-+		return;
-+
-+	RTW_INFO("[%s] In\n", __FUNCTION__);
-+	/*	Reset the operation channel information */
-+	pwdinfo->rx_invitereq_info.operation_ch[0] = 0;
-+#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
-+	pwdinfo->rx_invitereq_info.operation_ch[1] = 0;
-+	pwdinfo->rx_invitereq_info.operation_ch[2] = 0;
-+	pwdinfo->rx_invitereq_info.operation_ch[3] = 0;
-+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
-+	pwdinfo->rx_invitereq_info.scan_op_ch_only = 0;
-+}
-+
-+static void reset_ch_sitesurvey_timer_process2(void *FunctionContext)
-+{
-+	_adapter *adapter = (_adapter *)FunctionContext;
-+	struct	wifidirect_info		*pwdinfo = &adapter->wdinfo;
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
-+		return;
-+
-+	RTW_INFO("[%s] In\n", __FUNCTION__);
-+	/*	Reset the operation channel information */
-+	pwdinfo->p2p_info.operation_ch[0] = 0;
-+#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
-+	pwdinfo->p2p_info.operation_ch[1] = 0;
-+	pwdinfo->p2p_info.operation_ch[2] = 0;
-+	pwdinfo->p2p_info.operation_ch[3] = 0;
-+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
-+	pwdinfo->p2p_info.scan_op_ch_only = 0;
-+}
-+
-+static void restore_p2p_state_timer_process(void *FunctionContext)
-+{
-+	_adapter *adapter = (_adapter *)FunctionContext;
-+	struct	wifidirect_info		*pwdinfo = &adapter->wdinfo;
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
-+		return;
-+
-+	p2p_protocol_wk_cmd(adapter, P2P_RESTORE_STATE_WK);
-+}
-+
-+static void pre_tx_scan_timer_process(void *FunctionContext)
-+{
-+	_adapter							*adapter = (_adapter *) FunctionContext;
-+	struct	wifidirect_info				*pwdinfo = &adapter->wdinfo;
-+	_irqL							irqL;
-+	struct mlme_priv					*pmlmepriv = &adapter->mlmepriv;
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
-+		return;
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) {
-+		if (_TRUE == pwdinfo->tx_prov_disc_info.benable) {	/*	the provision discovery request frame is trigger to send or not */
-+			p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_PROVDISC_PROCESS_WK);
-+			/* issue_probereq_p2p(adapter, NULL); */
-+			/* _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); */
-+		}
-+	} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) {
-+		if (_TRUE == pwdinfo->nego_req_info.benable)
-+			p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_NEGOREQ_PROCESS_WK);
-+	} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ)) {
-+		if (_TRUE == pwdinfo->invitereq_info.benable)
-+			p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_INVITEREQ_PROCESS_WK);
-+	} else
-+		RTW_INFO("[%s] p2p_state is %d, ignore!!\n", __FUNCTION__, rtw_p2p_state(pwdinfo));
-+
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+}
-+
-+static void find_phase_timer_process(void *FunctionContext)
-+{
-+	_adapter *adapter = (_adapter *)FunctionContext;
-+	struct	wifidirect_info		*pwdinfo = &adapter->wdinfo;
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
-+		return;
-+
-+	adapter->wdinfo.find_phase_state_exchange_cnt++;
-+
-+	p2p_protocol_wk_cmd(adapter, P2P_FIND_PHASE_WK);
-+}
-+
-+void reset_global_wifidirect_info(_adapter *padapter)
-+{
-+	struct wifidirect_info	*pwdinfo;
-+
-+	pwdinfo = &padapter->wdinfo;
-+	pwdinfo->persistent_supported = 0;
-+	pwdinfo->session_available = _TRUE;
-+	rtw_tdls_wfd_enable(padapter, 0);
-+	pwdinfo->wfd_tdls_weaksec = _TRUE;
-+}
-+
-+#ifdef CONFIG_WFD
-+int rtw_init_wifi_display_info(_adapter *padapter)
-+{
-+	int	res = _SUCCESS;
-+	struct wifi_display_info *pwfd_info = &padapter->wfd_info;
-+
-+	/* Used in P2P and TDLS */
-+	pwfd_info->init_rtsp_ctrlport = 554;
-+#ifdef CONFIG_IOCTL_CFG80211
-+	pwfd_info->rtsp_ctrlport = 0;
-+#else
-+	pwfd_info->rtsp_ctrlport = pwfd_info->init_rtsp_ctrlport; /* set non-zero value for legacy wfd */
-+#endif
-+	pwfd_info->tdls_rtsp_ctrlport = 0;
-+	pwfd_info->peer_rtsp_ctrlport = 0;	/*	Reset to 0 */
-+	pwfd_info->wfd_enable = _FALSE;
-+	pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK;
-+	pwfd_info->scan_result_type = SCAN_RESULT_P2P_ONLY;
-+
-+	/* Used in P2P */
-+	pwfd_info->peer_session_avail = _TRUE;
-+	pwfd_info->wfd_pc = _FALSE;
-+
-+	/* Used in TDLS */
-+	_rtw_memset(pwfd_info->ip_address, 0x00, 4);
-+	_rtw_memset(pwfd_info->peer_ip_address, 0x00, 4);
-+	return res;
-+
-+}
-+
-+inline void rtw_wfd_enable(_adapter *adapter, bool on)
-+{
-+	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
-+
-+	if (on) {
-+		wfdinfo->rtsp_ctrlport = wfdinfo->init_rtsp_ctrlport;
-+		wfdinfo->wfd_enable = _TRUE;
-+
-+	} else {
-+		wfdinfo->wfd_enable = _FALSE;
-+		wfdinfo->rtsp_ctrlport = 0;
-+	}
-+}
-+
-+inline void rtw_wfd_set_ctrl_port(_adapter *adapter, u16 port)
-+{
-+	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
-+
-+	wfdinfo->init_rtsp_ctrlport = port;
-+	if (wfdinfo->wfd_enable == _TRUE)
-+		wfdinfo->rtsp_ctrlport = port;
-+	if (adapter->wdinfo.wfd_tdls_enable == 1)
-+		wfdinfo->tdls_rtsp_ctrlport = port;
-+}
-+
-+inline void rtw_tdls_wfd_enable(_adapter *adapter, bool on)
-+{
-+	struct wifi_display_info *wfdinfo = &adapter->wfd_info;
-+
-+	if (on) {
-+		wfdinfo->tdls_rtsp_ctrlport = wfdinfo->init_rtsp_ctrlport;
-+		adapter->wdinfo.wfd_tdls_enable = 1;
-+
-+	} else {
-+		adapter->wdinfo.wfd_tdls_enable = 0;
-+		wfdinfo->tdls_rtsp_ctrlport = 0;
-+	}
-+}
-+
-+u32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf)
-+{
-+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+	u8 build_ie_by_self = 0;
-+	u32 len = 0;
-+
-+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (_TRUE == wdinfo->wfd_info->wfd_enable)
-+#endif
-+		build_ie_by_self = 1;
-+
-+	if (build_ie_by_self)
-+		len = build_beacon_wfd_ie(wdinfo, pbuf);
-+#ifdef CONFIG_IOCTL_CFG80211
-+	else if (mlme->wfd_beacon_ie && mlme->wfd_beacon_ie_len > 0) {
-+		len = mlme->wfd_beacon_ie_len;
-+		_rtw_memcpy(pbuf, mlme->wfd_beacon_ie, len);
-+	}
-+#endif
-+
-+exit:
-+	return len;
-+}
-+
-+u32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf)
-+{
-+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+	u8 build_ie_by_self = 0;
-+	u32 len = 0;
-+
-+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (_TRUE == wdinfo->wfd_info->wfd_enable)
-+#endif
-+		build_ie_by_self = 1;
-+
-+	if (build_ie_by_self)
-+		len = build_probe_req_wfd_ie(wdinfo, pbuf);
-+#ifdef CONFIG_IOCTL_CFG80211
-+	else if (mlme->wfd_probe_req_ie && mlme->wfd_probe_req_ie_len > 0) {
-+		len = mlme->wfd_probe_req_ie_len;
-+		_rtw_memcpy(pbuf, mlme->wfd_probe_req_ie, len);
-+	}
-+#endif
-+
-+exit:
-+	return len;
-+}
-+
-+u32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf)
-+{
-+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+	u8 build_ie_by_self = 0;
-+	u32 len = 0;
-+
-+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (_TRUE == wdinfo->wfd_info->wfd_enable)
-+#endif
-+		build_ie_by_self = 1;
-+
-+	if (build_ie_by_self)
-+		len = build_probe_resp_wfd_ie(wdinfo, pbuf, 0);
-+#ifdef CONFIG_IOCTL_CFG80211
-+	else if (mlme->wfd_probe_resp_ie && mlme->wfd_probe_resp_ie_len > 0) {
-+		len = mlme->wfd_probe_resp_ie_len;
-+		_rtw_memcpy(pbuf, mlme->wfd_probe_resp_ie, len);
-+	}
-+#endif
-+
-+exit:
-+	return len;
-+}
-+
-+u32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf)
-+{
-+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+	u8 build_ie_by_self = 0;
-+	u32 len = 0;
-+
-+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (_TRUE == wdinfo->wfd_info->wfd_enable)
-+#endif
-+		build_ie_by_self = 1;
-+
-+	if (build_ie_by_self)
-+		len = build_assoc_req_wfd_ie(wdinfo, pbuf);
-+#ifdef CONFIG_IOCTL_CFG80211
-+	else if (mlme->wfd_assoc_req_ie && mlme->wfd_assoc_req_ie_len > 0) {
-+		len = mlme->wfd_assoc_req_ie_len;
-+		_rtw_memcpy(pbuf, mlme->wfd_assoc_req_ie, len);
-+	}
-+#endif
-+
-+exit:
-+	return len;
-+}
-+
-+u32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf)
-+{
-+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+	u8 build_ie_by_self = 0;
-+	u32 len = 0;
-+
-+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
-+		goto exit;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (_TRUE == wdinfo->wfd_info->wfd_enable)
-+#endif
-+		build_ie_by_self = 1;
-+
-+	if (build_ie_by_self)
-+		len = build_assoc_resp_wfd_ie(wdinfo, pbuf);
-+#ifdef CONFIG_IOCTL_CFG80211
-+	else if (mlme->wfd_assoc_resp_ie && mlme->wfd_assoc_resp_ie_len > 0) {
-+		len = mlme->wfd_assoc_resp_ie_len;
-+		_rtw_memcpy(pbuf, mlme->wfd_assoc_resp_ie, len);
-+	}
-+#endif
-+
-+exit:
-+	return len;
-+}
-+
-+#endif /* CONFIG_WFD */
-+
-+void rtw_init_wifidirect_timers(_adapter *padapter)
-+{
-+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
-+
-+	rtw_init_timer(&pwdinfo->find_phase_timer, padapter, find_phase_timer_process, padapter);
-+	rtw_init_timer(&pwdinfo->restore_p2p_state_timer, padapter, restore_p2p_state_timer_process, padapter);
-+	rtw_init_timer(&pwdinfo->pre_tx_scan_timer, padapter, pre_tx_scan_timer_process, padapter);
-+	rtw_init_timer(&pwdinfo->reset_ch_sitesurvey, padapter, reset_ch_sitesurvey_timer_process, padapter);
-+	rtw_init_timer(&pwdinfo->reset_ch_sitesurvey2, padapter, reset_ch_sitesurvey_timer_process2, padapter);
-+}
-+
-+void rtw_init_wifidirect_addrs(_adapter *padapter, u8 *dev_addr, u8 *iface_addr)
-+{
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
-+
-+	/*init device&interface address */
-+	if (dev_addr)
-+		_rtw_memcpy(pwdinfo->device_addr, dev_addr, ETH_ALEN);
-+	if (iface_addr)
-+		_rtw_memcpy(pwdinfo->interface_addr, iface_addr, ETH_ALEN);
-+#endif
-+}
-+
-+void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role)
-+{
-+	struct wifidirect_info	*pwdinfo;
-+#ifdef CONFIG_WFD
-+	struct wifi_display_info	*pwfd_info = &padapter->wfd_info;
-+#endif
-+	pwdinfo = &padapter->wdinfo;
-+
-+	pwdinfo->padapter = padapter;
-+
-+	/*	1, 6, 11 are the social channel defined in the WiFi Direct specification. */
-+	pwdinfo->social_chan[0] = 1;
-+	pwdinfo->social_chan[1] = 6;
-+	pwdinfo->social_chan[2] = 11;
-+	pwdinfo->social_chan[3] = 0;	/*	channel 0 for scanning ending in site survey function. */
-+
-+	if (role != P2P_ROLE_DISABLE
-+		&& pwdinfo->driver_interface != DRIVER_CFG80211
-+	) {
-+		#ifdef CONFIG_CONCURRENT_MODE
-+		u8 union_ch = 0;
-+
-+		if (rtw_mi_check_status(padapter, MI_LINKED))
-+			union_ch = rtw_mi_get_union_chan(padapter);
-+
-+		if (union_ch != 0 &&
-+			(union_ch == 1 || union_ch == 6 || union_ch == 11)
-+		) {
-+			/* Use the AP's channel as the listen channel */
-+			/* This will avoid the channel switch between AP's channel and listen channel */
-+			pwdinfo->listen_channel = union_ch;
-+		} else
-+		#endif /* CONFIG_CONCURRENT_MODE */
-+		{
-+			/* Use the channel 11 as the listen channel */
-+			pwdinfo->listen_channel = 11;
-+		}
-+	}
-+
-+	if (role == P2P_ROLE_DEVICE) {
-+		rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED))
-+			rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE);
-+		else
-+#endif
-+			rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
-+
-+		pwdinfo->intent = 1;
-+		rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_LISTEN);
-+	} else if (role == P2P_ROLE_CLIENT) {
-+		rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
-+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
-+		pwdinfo->intent = 1;
-+		rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
-+	} else if (role == P2P_ROLE_GO) {
-+		rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
-+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
-+		pwdinfo->intent = 15;
-+		rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK);
-+	}
-+
-+	/*	Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 )	 */
-+	pwdinfo->support_rate[0] = 0x8c;	/*	6(B) */
-+	pwdinfo->support_rate[1] = 0x92;	/*	9(B) */
-+	pwdinfo->support_rate[2] = 0x18;	/*	12 */
-+	pwdinfo->support_rate[3] = 0x24;	/*	18 */
-+	pwdinfo->support_rate[4] = 0x30;	/*	24 */
-+	pwdinfo->support_rate[5] = 0x48;	/*	36 */
-+	pwdinfo->support_rate[6] = 0x60;	/*	48 */
-+	pwdinfo->support_rate[7] = 0x6c;	/*	54 */
-+
-+	_rtw_memcpy((void *) pwdinfo->p2p_wildcard_ssid, "DIRECT-", 7);
-+
-+	_rtw_memset(pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN);
-+	pwdinfo->device_name_len = 0;
-+
-+	_rtw_memset(&pwdinfo->invitereq_info, 0x00, sizeof(struct tx_invite_req_info));
-+	pwdinfo->invitereq_info.token = 3;	/*	Token used for P2P invitation request frame. */
-+
-+	_rtw_memset(&pwdinfo->inviteresp_info, 0x00, sizeof(struct tx_invite_resp_info));
-+	pwdinfo->inviteresp_info.token = 0;
-+
-+	pwdinfo->profileindex = 0;
-+	_rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM);
-+
-+	rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
-+
-+	pwdinfo->listen_dwell = (u8)((rtw_get_current_time() % 3) + 1);
-+	/* RTW_INFO( "[%s] listen_dwell time is %d00ms\n", __FUNCTION__, pwdinfo->listen_dwell ); */
-+
-+	_rtw_memset(&pwdinfo->tx_prov_disc_info, 0x00, sizeof(struct tx_provdisc_req_info));
-+	pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_NONE;
-+
-+	_rtw_memset(&pwdinfo->nego_req_info, 0x00, sizeof(struct tx_nego_req_info));
-+
-+	pwdinfo->device_password_id_for_nego = WPS_DPID_PBC;
-+	pwdinfo->negotiation_dialog_token = 1;
-+
-+	_rtw_memset(pwdinfo->nego_ssid, 0x00, WLAN_SSID_MAXLEN);
-+	pwdinfo->nego_ssidlen = 0;
-+
-+	pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;
-+#ifdef CONFIG_WFD
-+	pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY  | WPS_CONFIG_METHOD_PBC;
-+	pwdinfo->wfd_info = pwfd_info;
-+#else
-+	pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY | WPS_CONFIG_METHOD_PBC | WPS_CONFIG_METHOD_KEYPAD;
-+#endif /* CONFIG_WFD */
-+	pwdinfo->channel_list_attr_len = 0;
-+	_rtw_memset(pwdinfo->channel_list_attr, 0x00, 100);
-+
-+	_rtw_memset(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, 0x00, 4);
-+	_rtw_memset(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, '0', 3);
-+	_rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info));
-+#ifdef CONFIG_CONCURRENT_MODE
-+#ifdef CONFIG_IOCTL_CFG80211
-+	pwdinfo->ext_listen_interval = 1000; /* The interval to be available with legacy AP during p2p0-find/scan */
-+	pwdinfo->ext_listen_period = 3000; /* The time period to be available for P2P during nego */
-+#else /* !CONFIG_IOCTL_CFG80211 */
-+	/* pwdinfo->ext_listen_interval = 3000; */
-+	/* pwdinfo->ext_listen_period = 400; */
-+	pwdinfo->ext_listen_interval = 1000;
-+	pwdinfo->ext_listen_period = 1000;
-+#endif /* !CONFIG_IOCTL_CFG80211 */
-+#endif
-+
-+	/* Commented by Kurt 20130319
-+	 * For WiDi purpose: Use CFG80211 interface but controled WFD/RDS frame by driver itself. */
-+#ifdef CONFIG_IOCTL_CFG80211
-+	pwdinfo->driver_interface = DRIVER_CFG80211;
-+#else
-+	pwdinfo->driver_interface = DRIVER_WEXT;
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+	pwdinfo->wfd_tdls_enable = 0;
-+	_rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN);
-+	_rtw_memset(pwdinfo->p2p_peer_device_addr, 0x00, ETH_ALEN);
-+
-+	pwdinfo->rx_invitereq_info.operation_ch[0] = 0;
-+	pwdinfo->rx_invitereq_info.operation_ch[1] = 0;	/*	Used to indicate the scan end in site survey function */
-+#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
-+	pwdinfo->rx_invitereq_info.operation_ch[2] = 0;
-+	pwdinfo->rx_invitereq_info.operation_ch[3] = 0;
-+	pwdinfo->rx_invitereq_info.operation_ch[4] = 0;
-+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
-+	pwdinfo->rx_invitereq_info.scan_op_ch_only = 0;
-+	pwdinfo->p2p_info.operation_ch[0] = 0;
-+	pwdinfo->p2p_info.operation_ch[1] = 0;			/*	Used to indicate the scan end in site survey function */
-+#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
-+	pwdinfo->p2p_info.operation_ch[2] = 0;
-+	pwdinfo->p2p_info.operation_ch[3] = 0;
-+	pwdinfo->p2p_info.operation_ch[4] = 0;
-+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
-+	pwdinfo->p2p_info.scan_op_ch_only = 0;
-+}
-+
-+void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role)
-+{
-+	if (wdinfo->role != role) {
-+		wdinfo->role = role;
-+		rtw_mi_update_iface_status(&(wdinfo->padapter->mlmepriv), 0);
-+	}
-+}
-+
-+#ifdef CONFIG_DBG_P2P
-+
-+/**
-+ * rtw_p2p_role_txt - Get the p2p role name as a text string
-+ * @role: P2P role
-+ * Returns: The state name as a printable text string
-+ */
-+const char *rtw_p2p_role_txt(enum P2P_ROLE role)
-+{
-+	switch (role) {
-+	case P2P_ROLE_DISABLE:
-+		return "P2P_ROLE_DISABLE";
-+	case P2P_ROLE_DEVICE:
-+		return "P2P_ROLE_DEVICE";
-+	case P2P_ROLE_CLIENT:
-+		return "P2P_ROLE_CLIENT";
-+	case P2P_ROLE_GO:
-+		return "P2P_ROLE_GO";
-+	default:
-+		return "UNKNOWN";
-+	}
-+}
-+
-+/**
-+ * rtw_p2p_state_txt - Get the p2p state name as a text string
-+ * @state: P2P state
-+ * Returns: The state name as a printable text string
-+ */
-+const char *rtw_p2p_state_txt(enum P2P_STATE state)
-+{
-+	switch (state) {
-+	case P2P_STATE_NONE:
-+		return "P2P_STATE_NONE";
-+	case P2P_STATE_IDLE:
-+		return "P2P_STATE_IDLE";
-+	case P2P_STATE_LISTEN:
-+		return "P2P_STATE_LISTEN";
-+	case P2P_STATE_SCAN:
-+		return "P2P_STATE_SCAN";
-+	case P2P_STATE_FIND_PHASE_LISTEN:
-+		return "P2P_STATE_FIND_PHASE_LISTEN";
-+	case P2P_STATE_FIND_PHASE_SEARCH:
-+		return "P2P_STATE_FIND_PHASE_SEARCH";
-+	case P2P_STATE_TX_PROVISION_DIS_REQ:
-+		return "P2P_STATE_TX_PROVISION_DIS_REQ";
-+	case P2P_STATE_RX_PROVISION_DIS_RSP:
-+		return "P2P_STATE_RX_PROVISION_DIS_RSP";
-+	case P2P_STATE_RX_PROVISION_DIS_REQ:
-+		return "P2P_STATE_RX_PROVISION_DIS_REQ";
-+	case P2P_STATE_GONEGO_ING:
-+		return "P2P_STATE_GONEGO_ING";
-+	case P2P_STATE_GONEGO_OK:
-+		return "P2P_STATE_GONEGO_OK";
-+	case P2P_STATE_GONEGO_FAIL:
-+		return "P2P_STATE_GONEGO_FAIL";
-+	case P2P_STATE_RECV_INVITE_REQ_MATCH:
-+		return "P2P_STATE_RECV_INVITE_REQ_MATCH";
-+	case P2P_STATE_PROVISIONING_ING:
-+		return "P2P_STATE_PROVISIONING_ING";
-+	case P2P_STATE_PROVISIONING_DONE:
-+		return "P2P_STATE_PROVISIONING_DONE";
-+	case P2P_STATE_TX_INVITE_REQ:
-+		return "P2P_STATE_TX_INVITE_REQ";
-+	case P2P_STATE_RX_INVITE_RESP_OK:
-+		return "P2P_STATE_RX_INVITE_RESP_OK";
-+	case P2P_STATE_RECV_INVITE_REQ_DISMATCH:
-+		return "P2P_STATE_RECV_INVITE_REQ_DISMATCH";
-+	case P2P_STATE_RECV_INVITE_REQ_GO:
-+		return "P2P_STATE_RECV_INVITE_REQ_GO";
-+	case P2P_STATE_RECV_INVITE_REQ_JOIN:
-+		return "P2P_STATE_RECV_INVITE_REQ_JOIN";
-+	case P2P_STATE_RX_INVITE_RESP_FAIL:
-+		return "P2P_STATE_RX_INVITE_RESP_FAIL";
-+	case P2P_STATE_RX_INFOR_NOREADY:
-+		return "P2P_STATE_RX_INFOR_NOREADY";
-+	case P2P_STATE_TX_INFOR_NOREADY:
-+		return "P2P_STATE_TX_INFOR_NOREADY";
-+	default:
-+		return "UNKNOWN";
-+	}
-+}
-+
-+void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line)
-+{
-+	if (!_rtw_p2p_chk_state(wdinfo, state)) {
-+		enum P2P_STATE old_state = _rtw_p2p_state(wdinfo);
-+		_rtw_p2p_set_state(wdinfo, state);
-+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_state from %s to %s\n", caller, line
-+			, rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_state(wdinfo))
-+			);
-+	} else {
-+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_state to same state %s\n", caller, line
-+			 , rtw_p2p_state_txt(_rtw_p2p_state(wdinfo))
-+			);
-+	}
-+}
-+void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line)
-+{
-+	if (_rtw_p2p_pre_state(wdinfo) != state) {
-+		enum P2P_STATE old_state = _rtw_p2p_pre_state(wdinfo);
-+		_rtw_p2p_set_pre_state(wdinfo, state);
-+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_pre_state from %s to %s\n", caller, line
-+			, rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo))
-+			);
-+	} else {
-+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_pre_state to same state %s\n", caller, line
-+			 , rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo))
-+			);
-+	}
-+}
-+#if 0
-+void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line)
-+{
-+	if (wdinfo->pre_p2p_state != -1) {
-+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d restore from %s to %s\n", caller, line
-+			, p2p_state_str[wdinfo->p2p_state], p2p_state_str[wdinfo->pre_p2p_state]
-+			);
-+		_rtw_p2p_restore_state(wdinfo);
-+	} else {
-+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d restore no pre state, cur state %s\n", caller, line
-+			 , p2p_state_str[wdinfo->p2p_state]
-+			);
-+	}
-+}
-+#endif
-+void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line)
-+{
-+	if (wdinfo->role != role) {
-+		enum P2P_ROLE old_role = wdinfo->role;
-+		_rtw_p2p_set_role(wdinfo, role);
-+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_role from %s to %s\n", caller, line
-+			, rtw_p2p_role_txt(old_role), rtw_p2p_role_txt(wdinfo->role)
-+			);
-+	} else {
-+		RTW_INFO("[CONFIG_DBG_P2P]%s:%d set_role to same role %s\n", caller, line
-+			 , rtw_p2p_role_txt(wdinfo->role)
-+			);
-+	}
-+}
-+#endif /* CONFIG_DBG_P2P */
-+
-+
-+int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role)
-+{
-+	int ret = _SUCCESS;
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+#ifdef CONFIG_CONCURRENT_MODE
-+	struct roch_info *prochinfo = &padapter->rochinfo;
-+#endif
-+
-+	if (role == P2P_ROLE_DEVICE || role == P2P_ROLE_CLIENT || role == P2P_ROLE_GO) {
-+#if defined(CONFIG_CONCURRENT_MODE) && (!defined(RTW_P2P_GROUP_INTERFACE) || !RTW_P2P_GROUP_INTERFACE)
-+		/*	Commented by Albert 2011/12/30 */
-+		/*	The driver just supports 1 P2P group operation. */
-+		/*	So, this function will do nothing if the buddy adapter had enabled the P2P function. */
-+		/*if(!rtw_p2p_chk_state(pbuddy_wdinfo, P2P_STATE_NONE))
-+			return ret;*/
-+		/* Only selected interface can be P2P interface */
-+		if (padapter->iface_id != padapter->registrypriv.sel_p2p_iface) {
-+			RTW_ERR("%s, iface_id:%d is not P2P interface!\n", __func__, padapter->iface_id);
-+			ret = _FAIL;
-+			return ret;
-+		}
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+		/* leave IPS/Autosuspend */
-+		if (_FAIL == rtw_pwr_wakeup(padapter)) {
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+
-+		/*	Added by Albert 2011/03/22 */
-+		/*	In the P2P mode, the driver should not support the b mode. */
-+		/*	So, the Tx packet shouldn't use the CCK rate */
-+		#ifdef CONFIG_IOCTL_CFG80211
-+		if (rtw_cfg80211_iface_has_p2p_group_cap(padapter))
-+		#endif
-+			update_tx_basic_rate(padapter, WIRELESS_11AGN);
-+
-+		/* Enable P2P function */
-+		init_wifidirect_info(padapter, role);
-+
-+		#ifdef CONFIG_IOCTL_CFG80211
-+		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
-+			adapter_wdev_data(padapter)->p2p_enabled = _TRUE;
-+		#endif
-+
-+		rtw_hal_set_odm_var(padapter, HAL_ODM_P2P_STATE, NULL, _TRUE);
-+#ifdef CONFIG_WFD
-+		if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+			rtw_hal_set_odm_var(padapter, HAL_ODM_WIFI_DISPLAY_STATE, NULL, _TRUE);
-+#endif
-+
-+	} else if (role == P2P_ROLE_DISABLE) {
-+
-+		#ifdef CONFIG_IOCTL_CFG80211
-+		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
-+			adapter_wdev_data(padapter)->p2p_enabled = _FALSE;
-+		#endif
-+
-+		pwdinfo->listen_channel = 0;
-+
-+		/* Disable P2P function */
-+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
-+			_cancel_timer_ex(&pwdinfo->find_phase_timer);
-+			_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
-+			_cancel_timer_ex(&pwdinfo->pre_tx_scan_timer);
-+			_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
-+			_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey2);
-+			reset_ch_sitesurvey_timer_process(padapter);
-+			reset_ch_sitesurvey_timer_process2(padapter);
-+#ifdef CONFIG_CONCURRENT_MODE
-+			_cancel_timer_ex(&prochinfo->ap_roch_ch_switch_timer);
-+#endif
-+			rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE);
-+			rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_NONE);
-+			rtw_p2p_set_role(pwdinfo, P2P_ROLE_DISABLE);
-+			_rtw_memset(&pwdinfo->rx_prov_disc_info, 0x00, sizeof(struct rx_provdisc_req_info));
-+
-+			/* Remove profiles in wifidirect_info structure. */
-+			_rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM);
-+			pwdinfo->profileindex = 0;
-+		}
-+
-+		rtw_hal_set_odm_var(padapter, HAL_ODM_P2P_STATE, NULL, _FALSE);
-+#ifdef CONFIG_WFD
-+		if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+			rtw_hal_set_odm_var(padapter, HAL_ODM_WIFI_DISPLAY_STATE, NULL, _FALSE);
-+#endif
-+
-+		if (_FAIL == rtw_pwr_wakeup(padapter)) {
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+
-+		/* Restore to initial setting. */
-+		update_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode);
-+
-+		/* For WiDi purpose. */
-+#ifdef CONFIG_IOCTL_CFG80211
-+		pwdinfo->driver_interface = DRIVER_CFG80211;
-+#else
-+		pwdinfo->driver_interface = DRIVER_WEXT;
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+#endif /* CONFIG_P2P */
-diff --git a/drivers/staging/rtl8723cs/core/rtw_pwrctrl.c b/drivers/staging/rtl8723cs/core/rtw_pwrctrl.c
-new file mode 100644
-index 000000000000..5c519a5d39bb
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_pwrctrl.c
-@@ -0,0 +1,2958 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_PWRCTRL_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+#include <hal_com_h2c.h>
-+
-+#ifdef DBG_CHECK_FW_PS_STATE
-+int rtw_fw_ps_state(PADAPTER padapter)
-+{
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+	int ret = _FAIL, dont_care = 0;
-+	u16 fw_ps_state = 0;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct registry_priv  *registry_par = &padapter->registrypriv;
-+
-+	if (registry_par->check_fw_ps != 1)
-+		return _SUCCESS;
-+
-+	_enter_pwrlock(&pwrpriv->check_32k_lock);
-+
-+	if (RTW_CANNOT_RUN(padapter)) {
-+		RTW_INFO("%s: bSurpriseRemoved=%s , hw_init_completed=%d, bDriverStopped=%s\n", __func__
-+			 , rtw_is_surprise_removed(padapter) ? "True" : "False"
-+			 , rtw_get_hw_init_completed(padapter)
-+			 , rtw_is_drv_stopped(padapter) ? "True" : "False");
-+		goto exit_fw_ps_state;
-+	}
-+	#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
-+	rtw_hal_get_hwreg(padapter, HW_VAR_FW_PS_STATE, (u8 *)&fw_ps_state);
-+	if ((fw_ps_state & BIT_LPS_STATUS) == 0)
-+		ret = _SUCCESS;
-+	else {
-+		pdbgpriv->dbg_poll_fail_cnt++;
-+		RTW_INFO("%s: fw_ps_state=%04x\n", __FUNCTION__, fw_ps_state);
-+	}
-+	#else
-+	rtw_hal_set_hwreg(padapter, HW_VAR_SET_REQ_FW_PS, (u8 *)&dont_care);
-+	{
-+		/* 4. if 0x88[7]=1, driver set cmd to leave LPS/IPS. */
-+		/* Else, hw will keep in active mode. */
-+		/* debug info: */
-+		/* 0x88[7] = 32kpermission, */
-+		/* 0x88[6:0] = current_ps_state */
-+		/* 0x89[7:0] = last_rpwm */
-+
-+		rtw_hal_get_hwreg(padapter, HW_VAR_FW_PS_STATE, (u8 *)&fw_ps_state);
-+
-+		if ((fw_ps_state & 0x80) == 0)
-+			ret = _SUCCESS;
-+		else {
-+			pdbgpriv->dbg_poll_fail_cnt++;
-+			RTW_INFO("%s: fw_ps_state=%04x\n", __FUNCTION__, fw_ps_state);
-+		}
-+	}
-+	#endif
-+
-+exit_fw_ps_state:
-+	_exit_pwrlock(&pwrpriv->check_32k_lock);
-+	return ret;
-+}
-+#endif /*DBG_CHECK_FW_PS_STATE*/
-+#ifdef CONFIG_IPS
-+void _ips_enter(_adapter *padapter)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+
-+	pwrpriv->bips_processing = _TRUE;
-+
-+	/* syn ips_mode with request */
-+	pwrpriv->ips_mode = pwrpriv->ips_mode_req;
-+
-+	pwrpriv->ips_enter_cnts++;
-+	RTW_INFO("==>ips_enter cnts:%d\n", pwrpriv->ips_enter_cnts);
-+
-+	if (rf_off == pwrpriv->change_rfpwrstate) {
-+		pwrpriv->bpower_saving = _TRUE;
-+		RTW_PRINT("nolinked power save enter\n");
-+
-+		if (pwrpriv->ips_mode == IPS_LEVEL_2)
-+			pwrpriv->bkeepfwalive = _TRUE;
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS		
-+		pwrpriv->pwr_saving_start_time = rtw_get_current_time();
-+#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
-+
-+		rtw_ips_pwr_down(padapter);
-+		pwrpriv->rf_pwrstate = rf_off;
-+	}
-+	pwrpriv->bips_processing = _FALSE;
-+
-+}
-+
-+void ips_enter(_adapter *padapter)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+
-+
-+#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req);
-+#endif /* CONFIG_BT_COEXIST */
-+
-+	_enter_pwrlock(&pwrpriv->lock);
-+	_ips_enter(padapter);
-+	_exit_pwrlock(&pwrpriv->lock);
-+
-+#ifdef CONFIG_PCI_DYNAMIC_ASPM
-+	rtw_pci_dynamic_aspm_set_mode(padapter, ASPM_MODE_PS);
-+#endif
-+}
-+
-+int _ips_leave(_adapter *padapter)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	int result = _SUCCESS;
-+
-+	if ((pwrpriv->rf_pwrstate == rf_off) && (!pwrpriv->bips_processing)) {
-+		pwrpriv->bips_processing = _TRUE;
-+		pwrpriv->change_rfpwrstate = rf_on;
-+		pwrpriv->ips_leave_cnts++;
-+		RTW_INFO("==>ips_leave cnts:%d\n", pwrpriv->ips_leave_cnts);
-+
-+		result = rtw_ips_pwr_up(padapter);
-+		if (result == _SUCCESS)
-+			pwrpriv->rf_pwrstate = rf_on;
-+		
-+#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS	
-+		pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);
-+#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
-+
-+		RTW_PRINT("nolinked power save leave\n");
-+
-+		RTW_INFO("==> ips_leave.....LED(0x%08x)...\n", rtw_read32(padapter, 0x4c));
-+		pwrpriv->bips_processing = _FALSE;
-+
-+		pwrpriv->bkeepfwalive = _FALSE;
-+		pwrpriv->bpower_saving = _FALSE;
-+	}
-+
-+	return result;
-+}
-+
-+int ips_leave(_adapter *padapter)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+#ifdef DBG_CHECK_FW_PS_STATE
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+#endif
-+	int ret;
-+
-+	if (!is_primary_adapter(padapter))
-+		return _SUCCESS;
-+
-+	_enter_pwrlock(&pwrpriv->lock);
-+	ret = _ips_leave(padapter);
-+#ifdef DBG_CHECK_FW_PS_STATE
-+	if (rtw_fw_ps_state(padapter) == _FAIL) {
-+		RTW_INFO("ips leave doesn't leave 32k\n");
-+		pdbgpriv->dbg_leave_ips_fail_cnt++;
-+	}
-+#endif /* DBG_CHECK_FW_PS_STATE */
-+	_exit_pwrlock(&pwrpriv->lock);
-+
-+#ifdef CONFIG_PCI_DYNAMIC_ASPM
-+	rtw_pci_dynamic_aspm_set_mode(padapter, ASPM_MODE_PERF);
-+#endif
-+
-+	if (_SUCCESS == ret)
-+		odm_dm_reset(&GET_HAL_DATA(padapter)->odmpriv);
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if (_SUCCESS == ret)
-+		rtw_btcoex_IpsNotify(padapter, IPS_NONE);
-+#endif /* CONFIG_BT_COEXIST */
-+
-+	return ret;
-+}
-+#endif /* CONFIG_IPS */
-+
-+#ifdef SUPPORT_HW_RFOFF_DETECTED
-+	int rtw_hw_suspend(_adapter *padapter);
-+	int rtw_hw_resume(_adapter *padapter);
-+#endif
-+
-+bool rtw_pwr_unassociated_idle(_adapter *adapter)
-+{
-+	u8 i;
-+	_adapter *iface;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct xmit_priv *pxmit_priv = &adapter->xmitpriv;
-+	struct mlme_priv *pmlmepriv;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo;
-+#endif
-+
-+	bool ret = _FALSE;
-+
-+	if (adapter_to_pwrctl(adapter)->bpower_saving == _TRUE) {
-+		/* RTW_INFO("%s: already in LPS or IPS mode\n", __func__); */
-+		goto exit;
-+	}
-+
-+	if (rtw_time_after(adapter_to_pwrctl(adapter)->ips_deny_time, rtw_get_current_time())) {
-+		/* RTW_INFO("%s ips_deny_time\n", __func__); */
-+		goto exit;
-+	}
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if ((iface) && rtw_is_adapter_up(iface)) {
-+			pmlmepriv = &(iface->mlmepriv);
-+#ifdef CONFIG_P2P
-+			pwdinfo = &(iface->wdinfo);
-+#endif
-+			if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_SURVEY)
-+				|| check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)
-+				|| MLME_IS_AP(iface)
-+				|| MLME_IS_MESH(iface)
-+				|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE)
-+				#if defined(CONFIG_IOCTL_CFG80211)
-+				|| rtw_cfg80211_get_is_roch(iface) == _TRUE
-+				|| (rtw_cfg80211_is_ro_ch_once(adapter)
-+					&& rtw_cfg80211_get_last_ro_ch_passing_ms(adapter) < 3000)
-+				#elif defined(CONFIG_P2P)
-+				|| rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)
-+				|| rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)
-+				#endif
-+			)
-+				goto exit;
-+
-+		}
-+	}
-+
-+#if (MP_DRIVER == 1)
-+	if (adapter->registrypriv.mp_mode == 1)
-+		goto exit;
-+#endif
-+
-+	if (pxmit_priv->free_xmitbuf_cnt != NR_XMITBUFF ||
-+	    pxmit_priv->free_xmit_extbuf_cnt != NR_XMIT_EXTBUFF) {
-+		RTW_PRINT("There are some pkts to transmit\n");
-+		RTW_PRINT("free_xmitbuf_cnt: %d, free_xmit_extbuf_cnt: %d\n",
-+			pxmit_priv->free_xmitbuf_cnt, pxmit_priv->free_xmit_extbuf_cnt);
-+		goto exit;
-+	}
-+
-+	ret = _TRUE;
-+
-+exit:
-+	return ret;
-+}
-+
-+
-+/*
-+ * ATTENTION:
-+ *	rtw_ps_processor() doesn't handle LPS.
-+ */
-+void rtw_ps_processor(_adapter *padapter)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+#ifdef SUPPORT_HW_RFOFF_DETECTED
-+	rt_rf_power_state rfpwrstate;
-+#endif /* SUPPORT_HW_RFOFF_DETECTED */
-+	u32 ps_deny = 0;
-+
-+	_enter_pwrlock(&adapter_to_pwrctl(padapter)->lock);
-+	ps_deny = rtw_ps_deny_get(padapter);
-+	_exit_pwrlock(&adapter_to_pwrctl(padapter)->lock);
-+	if (ps_deny != 0) {
-+		if (!MLME_IS_MONITOR(padapter)) {
-+			RTW_INFO(FUNC_ADPT_FMT ": ps_deny=0x%08X, skip power save!\n",
-+				 FUNC_ADPT_ARG(padapter), ps_deny);
-+		}
-+		goto exit;
-+	}
-+
-+	if (pwrpriv->bInSuspend == _TRUE) { /* system suspend or autosuspend */
-+		pdbgpriv->dbg_ps_insuspend_cnt++;
-+		RTW_INFO("%s, pwrpriv->bInSuspend == _TRUE ignore this process\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	pwrpriv->ps_processing = _TRUE;
-+
-+#ifdef SUPPORT_HW_RFOFF_DETECTED
-+	if (pwrpriv->bips_processing == _TRUE)
-+		goto exit;
-+
-+	/* RTW_INFO("==> fw report state(0x%x)\n",rtw_read8(padapter,0x1ca));	 */
-+	if (pwrpriv->bHWPwrPindetect) {
-+		
-+		rfpwrstate = RfOnOffDetect(padapter);
-+		RTW_INFO("@@@@- #2  %s==> rfstate:%s\n", __FUNCTION__, (rfpwrstate == rf_on) ? "rf_on" : "rf_off");
-+
-+		if (rfpwrstate != pwrpriv->rf_pwrstate) {
-+			if (rfpwrstate == rf_off) {
-+				pwrpriv->change_rfpwrstate = rf_off;
-+				pwrpriv->brfoffbyhw = _TRUE;
-+				rtw_hw_suspend(padapter);
-+			} else {
-+				pwrpriv->change_rfpwrstate = rf_on;
-+				rtw_hw_resume(padapter);
-+			}
-+			RTW_INFO("current rf_pwrstate(%s)\n", (pwrpriv->rf_pwrstate == rf_off) ? "rf_off" : "rf_on");
-+		}
-+		
-+		pwrpriv->pwr_state_check_cnts++;
-+	}
-+#endif /* SUPPORT_HW_RFOFF_DETECTED */
-+
-+	if (pwrpriv->ips_mode_req == IPS_NONE)
-+		goto exit;
-+
-+	if (rtw_pwr_unassociated_idle(padapter) == _FALSE)
-+		goto exit;
-+
-+	if ((pwrpriv->rf_pwrstate == rf_on) && ((pwrpriv->pwr_state_check_cnts % 4) == 0)) {
-+		RTW_INFO("==>%s .fw_state(%x)\n", __FUNCTION__, get_fwstate(pmlmepriv));
-+		pwrpriv->change_rfpwrstate = rf_off;	
-+
-+#ifdef CONFIG_IPS
-+			ips_enter(padapter);
-+#endif
-+
-+	}
-+exit:
-+#ifndef CONFIG_IPS_CHECK_IN_WD
-+	rtw_set_pwr_state_check_timer(pwrpriv);
-+#endif
-+	pwrpriv->ps_processing = _FALSE;
-+	return;
-+}
-+
-+void pwr_state_check_handler(void *ctx)
-+{
-+	_adapter *padapter = (_adapter *)ctx;
-+	rtw_ps_cmd(padapter);
-+}
-+
-+#ifdef CONFIG_LPS
-+#ifdef CONFIG_CHECK_LEAVE_LPS
-+#ifdef CONFIG_LPS_CHK_BY_TP
-+void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta)
-+{
-+	struct stainfo_stats *pstats = &sta->sta_stats;
-+	u64 cur_acc_tx_bytes = 0, cur_acc_rx_bytes = 0;
-+	u32 tx_tp_kbyte = 0, rx_tp_kbyte = 0;
-+	u32 tx_tp_th = 0, rx_tp_th = 0;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	u8	leave_lps = _FALSE;
-+
-+	if (tx) { /* from tx */
-+		cur_acc_tx_bytes = pstats->tx_bytes - pstats->acc_tx_bytes;
-+		tx_tp_kbyte = cur_acc_tx_bytes >> 10;
-+		tx_tp_th = pwrpriv->lps_tx_tp_th * 1024 / 8 * 2; /*KBytes @2s*/
-+
-+		if (tx_tp_kbyte >= tx_tp_th ||
-+			padapter->mlmepriv.LinkDetectInfo.NumTxOkInPeriod >= pwrpriv->lps_tx_pkts){
-+			if (pwrpriv->bLeisurePs
-+				&& (pwrpriv->pwr_mode != PS_MODE_ACTIVE)
-+				#ifdef CONFIG_BT_COEXIST
-+				&& (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
-+				#endif
-+			) {
-+				leave_lps = _TRUE;
-+			}
-+		}
-+
-+	} else { /* from rx path */
-+		cur_acc_rx_bytes = pstats->rx_bytes - pstats->acc_rx_bytes;
-+		rx_tp_kbyte = cur_acc_rx_bytes >> 10;
-+		rx_tp_th = pwrpriv->lps_rx_tp_th * 1024 / 8 * 2;
-+
-+		if (rx_tp_kbyte>= rx_tp_th ||
-+			padapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod >= pwrpriv->lps_rx_pkts) {
-+			if (pwrpriv->bLeisurePs
-+				&& (pwrpriv->pwr_mode != PS_MODE_ACTIVE)
-+				#ifdef CONFIG_BT_COEXIST
-+				&& (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
-+				#endif
-+			) {
-+				leave_lps = _TRUE;
-+			}
-+		}
-+	}
-+
-+	if (leave_lps) {
-+		#ifdef DBG_LPS_CHK_BY_TP
-+		RTW_INFO("leave lps via %s, ", tx ? "Tx" : "Rx");
-+		if (tx)
-+			RTW_INFO("Tx = %d [%d] (KB)\n", tx_tp_kbyte, tx_tp_th);
-+		else
-+			RTW_INFO("Rx = %d [%d] (KB)\n", rx_tp_kbyte, rx_tp_th);
-+		#endif
-+		pwrpriv->lps_chk_cnt = pwrpriv->lps_chk_cnt_th;
-+		/* rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0); */
-+		rtw_lps_ctrl_wk_cmd(padapter, tx ? LPS_CTRL_TX_TRAFFIC_LEAVE : LPS_CTRL_RX_TRAFFIC_LEAVE, 0);
-+	}
-+}
-+#endif /*CONFIG_LPS_CHK_BY_TP*/
-+
-+void	traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets)
-+{
-+	static systime start_time = 0;
-+	static u32 xmit_cnt = 0;
-+	u8	bLeaveLPS = _FALSE;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+
-+
-+
-+	if (tx) { /* from tx */
-+		xmit_cnt += tx_packets;
-+
-+		if (start_time == 0)
-+			start_time = rtw_get_current_time();
-+
-+		if (rtw_get_passing_time_ms(start_time) > 2000) { /* 2 sec == watch dog timer */
-+			if (xmit_cnt > 8) {
-+				if ((adapter_to_pwrctl(padapter)->bLeisurePs)
-+				    && (adapter_to_pwrctl(padapter)->pwr_mode != PS_MODE_ACTIVE)
-+#ifdef CONFIG_BT_COEXIST
-+				    && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
-+#endif
-+				   ) {
-+					/* RTW_INFO("leave lps via Tx = %d\n", xmit_cnt);			 */
-+					bLeaveLPS = _TRUE;
-+				}
-+			}
-+
-+			start_time = rtw_get_current_time();
-+			xmit_cnt = 0;
-+		}
-+
-+	} else { /* from rx path */
-+		if (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 4/*2*/) {
-+			if ((adapter_to_pwrctl(padapter)->bLeisurePs)
-+			    && (adapter_to_pwrctl(padapter)->pwr_mode != PS_MODE_ACTIVE)
-+#ifdef CONFIG_BT_COEXIST
-+			    && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
-+#endif
-+			   ) {
-+				/* RTW_INFO("leave lps via Rx = %d\n", pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);	 */
-+				bLeaveLPS = _TRUE;
-+			}
-+		}
-+	}
-+
-+	if (bLeaveLPS) {
-+		/* RTW_INFO("leave lps via %s, Tx = %d, Rx = %d\n", tx?"Tx":"Rx", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod,pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod);	 */
-+		/* rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0); */
-+		rtw_lps_ctrl_wk_cmd(padapter, tx ? LPS_CTRL_TX_TRAFFIC_LEAVE : LPS_CTRL_RX_TRAFFIC_LEAVE, tx ? RTW_CMDF_DIRECTLY : 0);
-+	}
-+}
-+#endif /* CONFIG_CHECK_LEAVE_LPS */
-+
-+#ifdef CONFIG_LPS_LCLK
-+#define LPS_CPWM_TIMEOUT_MS	10 /*ms*/
-+#define LPS_RPWM_RETRY_CNT		3
-+
-+u8 rtw_cpwm_polling(_adapter *adapter, u8 rpwm, u8 cpwm_orig)
-+{
-+	u8 rst = _FAIL;
-+	u8 cpwm_now = 0;
-+	systime start_time;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	#ifdef DBG_CHECK_FW_PS_STATE
-+	struct debug_priv *pdbgpriv = &(adapter_to_dvobj(adapter)->drv_dbg);
-+	#endif
-+
-+	pwrpriv->rpwm_retry = 0;
-+
-+	do {
-+		start_time = rtw_get_current_time();
-+		do {
-+			rtw_msleep_os(1);
-+			rtw_hal_get_hwreg(adapter, HW_VAR_CPWM, &cpwm_now);
-+
-+			if ((cpwm_orig ^ cpwm_now) & 0x80) {
-+				pwrpriv->cpwm = PS_STATE_S4;
-+				pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE;
-+				rst = _SUCCESS;
-+				break;
-+			}
-+		} while (rtw_get_passing_time_ms(start_time) < LPS_CPWM_TIMEOUT_MS && !RTW_CANNOT_RUN(adapter));
-+
-+		if (rst == _SUCCESS)
-+			break;
-+		else {
-+			/* rpwm retry */
-+			cpwm_orig = cpwm_now;
-+			rpwm &= ~PS_TOGGLE;
-+			rpwm |= pwrpriv->tog;
-+			rtw_hal_set_hwreg(adapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));
-+			pwrpriv->tog += 0x80;
-+		}
-+	} while (pwrpriv->rpwm_retry++ < LPS_RPWM_RETRY_CNT && !RTW_CANNOT_RUN(adapter));
-+
-+	if (rst == _SUCCESS) {
-+		#ifdef DBG_CHECK_FW_PS_STATE
-+		RTW_INFO("%s: polling cpwm OK! rpwm_retry=%d, cpwm_orig=%02x, cpwm_now=%02x , 0x100=0x%x\n"
-+			, __func__, pwrpriv->rpwm_retry, cpwm_orig, cpwm_now, rtw_read8(adapter, REG_CR));
-+		if (rtw_fw_ps_state(adapter) == _FAIL) {
-+			RTW_INFO("leave 32k but fw state in 32k\n");
-+			pdbgpriv->dbg_rpwm_toogle_cnt++;
-+		}
-+		#endif /* DBG_CHECK_FW_PS_STATE */
-+	} else {
-+		RTW_ERR("%s: polling cpwm timeout! rpwm_retry=%d, cpwm_orig=%02x, cpwm_now=%02x\n"
-+				, __func__, pwrpriv->rpwm_retry, cpwm_orig, cpwm_now);
-+		#ifdef DBG_CHECK_FW_PS_STATE
-+		if (rtw_fw_ps_state(adapter) == _FAIL) {
-+			RTW_INFO("rpwm timeout and fw ps state in 32k\n");
-+			pdbgpriv->dbg_rpwm_timeout_fail_cnt++;
-+		}
-+		#endif /* DBG_CHECK_FW_PS_STATE */
-+
-+		#ifdef CONFIG_LPS_RPWM_TIMER
-+		_set_timer(&pwrpriv->pwr_rpwm_timer, 1);
-+		#endif /* CONFIG_LPS_RPWM_TIMER */
-+	}
-+
-+	return rst;
-+}
-+#endif
-+/*
-+ * Description:
-+ *	This function MUST be called under power lock protect
-+ *
-+ * Parameters
-+ *	padapter
-+ *	pslv			power state level, only could be PS_STATE_S0 ~ PS_STATE_S4
-+ *
-+ */
-+u8 rtw_set_rpwm(PADAPTER padapter, u8 pslv)
-+{
-+	u8	rpwm = 0xFF;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+#ifdef CONFIG_LPS_LCLK
-+	u8 cpwm_orig;
-+#endif
-+
-+	pslv = PS_STATE(pslv);
-+
-+#ifdef CONFIG_LPS_RPWM_TIMER
-+	if (pwrpriv->brpwmtimeout == _TRUE)
-+		RTW_INFO("%s: RPWM timeout, force to set RPWM(0x%02X) again!\n", __FUNCTION__, pslv);
-+	else
-+#endif /* CONFIG_LPS_RPWM_TIMER */
-+	{
-+		if ((pwrpriv->rpwm == pslv)
-+#ifdef CONFIG_LPS_LCLK
-+		    || ((pwrpriv->rpwm >= PS_STATE_S2) && (pslv >= PS_STATE_S2))
-+#endif
-+			|| (pwrpriv->lps_level == LPS_NORMAL)
-+		   ) {
-+			return rpwm;
-+		}
-+	}
-+
-+	if (rtw_is_surprise_removed(padapter) ||
-+	    (!rtw_is_hw_init_completed(padapter))) {
-+
-+		pwrpriv->cpwm = PS_STATE_S4;
-+
-+		return rpwm;
-+	}
-+
-+	if (rtw_is_drv_stopped(padapter))
-+		if (pslv < PS_STATE_S2)
-+			return rpwm;
-+
-+	rpwm = pslv | pwrpriv->tog;
-+#ifdef CONFIG_LPS_LCLK
-+	/* only when from PS_STATE S0/S1 to S2 and higher needs ACK */
-+	if ((pwrpriv->cpwm < PS_STATE_S2) && (pslv >= PS_STATE_S2))
-+		rpwm |= PS_ACK;
-+#endif
-+
-+	pwrpriv->rpwm = pslv;
-+
-+#ifdef CONFIG_LPS_LCLK
-+	cpwm_orig = 0;
-+	if (rpwm & PS_ACK)
-+		rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
-+#endif
-+
-+#if defined(CONFIG_LPS_RPWM_TIMER) && !defined(CONFIG_DETECT_CPWM_BY_POLLING)
-+	if (rpwm & PS_ACK) {
-+		#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)
-+		if (pwrpriv->wowlan_mode != _TRUE &&
-+			pwrpriv->wowlan_ap_mode != _TRUE &&
-+			pwrpriv->wowlan_p2p_mode != _TRUE)
-+		#endif
-+		_set_timer(&pwrpriv->pwr_rpwm_timer, LPS_CPWM_TIMEOUT_MS);
-+	}
-+#endif /* CONFIG_LPS_RPWM_TIMER & !CONFIG_DETECT_CPWM_BY_POLLING */
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));
-+
-+	pwrpriv->tog += 0x80;
-+
-+#ifdef CONFIG_LPS_LCLK
-+	/* No LPS 32K, No Ack */
-+	if (rpwm & PS_ACK) {
-+		#ifdef CONFIG_DETECT_CPWM_BY_POLLING
-+		rtw_cpwm_polling(padapter, rpwm, cpwm_orig);
-+		#else
-+		#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)
-+		if (pwrpriv->wowlan_mode == _TRUE ||
-+			pwrpriv->wowlan_ap_mode == _TRUE ||
-+			pwrpriv->wowlan_p2p_mode == _TRUE)
-+				rtw_cpwm_polling(padapter, rpwm, cpwm_orig);
-+		#endif /*#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)*/
-+		#endif /*#ifdef CONFIG_DETECT_CPWM_BY_POLLING*/
-+	} else
-+#endif /* CONFIG_LPS_LCLK */
-+	{
-+		pwrpriv->cpwm = pslv;
-+	}
-+
-+	return rpwm;
-+}
-+
-+u8 PS_RDY_CHECK(_adapter *padapter)
-+{
-+	struct pwrctrl_priv	*pwrpriv = adapter_to_pwrctl(padapter);
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+	if (_TRUE == pwrpriv->bInSuspend && pwrpriv->wowlan_mode)
-+		return _TRUE;
-+	else if (_TRUE == pwrpriv->bInSuspend && pwrpriv->wowlan_ap_mode)
-+		return _TRUE;
-+	else if (_TRUE == pwrpriv->bInSuspend)
-+		return _FALSE;
-+#else
-+	if (_TRUE == pwrpriv->bInSuspend)
-+		return _FALSE;
-+#endif
-+
-+	if (rtw_time_after(pwrpriv->lps_deny_time, rtw_get_current_time()))
-+		return _FALSE;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)
-+		|| check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)
-+		|| MLME_IS_AP(padapter)
-+		|| MLME_IS_MESH(padapter)
-+		|| MLME_IS_MONITOR(padapter)
-+		|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE)
-+		#if defined(CONFIG_IOCTL_CFG80211)
-+		|| rtw_cfg80211_get_is_roch(padapter) == _TRUE
-+		#endif
-+		|| rtw_is_scan_deny(padapter)
-+		#ifdef CONFIG_TDLS
-+		/* TDLS link is established. */
-+		|| (padapter->tdlsinfo.link_established == _TRUE)
-+		#endif /* CONFIG_TDLS		 */
-+		#ifdef CONFIG_DFS_MASTER
-+		|| adapter_to_rfctl(padapter)->radar_detect_enabled
-+		#endif
-+	)
-+		return _FALSE;
-+
-+	if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (padapter->securitypriv.binstallGrpkey == _FALSE)) {
-+		RTW_INFO("Group handshake still in progress !!!\n");
-+		return _FALSE;
-+	}
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (!rtw_cfg80211_pwr_mgmt(padapter))
-+		return _FALSE;
-+#endif
-+
-+	return _TRUE;
-+}
-+
-+#if defined(CONFIG_FWLPS_IN_IPS)
-+void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	int cnt = 0;
-+	systime start_time;
-+	u8 val8 = 0;
-+	u8 cpwm_orig = 0, cpwm_now = 0;
-+	u8 parm[H2C_INACTIVE_PS_LEN] = {0};
-+
-+	if (padapter->netif_up == _FALSE) {
-+		RTW_INFO("%s: ERROR, netif is down\n", __func__);
-+		return;
-+	}
-+
-+	/* u8 cmd_param; */ /* BIT0:enable, BIT1:NoConnect32k */
-+	if (enable) {
-+#ifdef CONFIG_BT_COEXIST
-+		rtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req);
-+#endif
-+		/* Enter IPS */
-+		RTW_INFO("%s: issue H2C to FW when entering IPS\n", __func__);
-+
-+		parm[0] = 0x1;/* suggest by Isaac.Hsu*/
-+#ifdef CONFIG_PNO_SUPPORT
-+		if (pwrpriv->pno_inited) {
-+			parm[1] = pwrpriv->pnlo_info->fast_scan_iterations;
-+			parm[2] = pwrpriv->pnlo_info->slow_scan_period;
-+		}
-+#endif
-+
-+		rtw_hal_fill_h2c_cmd(padapter, /* H2C_FWLPS_IN_IPS_, */
-+				     H2C_INACTIVE_PS_,
-+				     H2C_INACTIVE_PS_LEN, parm);
-+		/* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */
-+		do {
-+			val8 = rtw_read8(padapter, REG_HMETFR);
-+			cnt++;
-+			RTW_INFO("%s  polling REG_HMETFR=0x%x, cnt=%d\n",
-+				 __func__, val8, cnt);
-+			rtw_mdelay_os(10);
-+		} while (cnt < 100 && (val8 != 0));
-+
-+#ifdef CONFIG_LPS_LCLK
-+		/* H2C done, enter 32k */
-+		if (val8 == 0) {
-+			/* ser rpwm to enter 32k */
-+			rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &val8);
-+			RTW_INFO("%s: read rpwm=%02x\n", __FUNCTION__, val8);
-+			val8 += 0x80;
-+			val8 |= BIT(0);
-+			rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&val8));
-+			RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
-+			adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
-+			cnt = val8 = 0;
-+			if (parm[1] == 0 || parm[2] == 0) {
-+				do {
-+					val8 = rtw_read8(padapter, REG_CR);
-+					cnt++;
-+					RTW_INFO("%s  polling 0x100=0x%x, cnt=%d\n",
-+						 __func__, val8, cnt);
-+					RTW_INFO("%s 0x08:%02x, 0x03:%02x\n",
-+						 __func__,
-+						 rtw_read8(padapter, 0x08),
-+						 rtw_read8(padapter, 0x03));
-+					rtw_mdelay_os(10);
-+				} while (cnt < 20 && (val8 != 0xEA));
-+			}
-+		}
-+#endif
-+	} else {
-+		/* Leave IPS */
-+		RTW_INFO("%s: Leaving IPS in FWLPS state\n", __func__);
-+
-+#ifdef CONFIG_LPS_LCLK
-+		/* for polling cpwm */
-+		cpwm_orig = 0;
-+		rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
-+
-+		/* ser rpwm */
-+		rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &val8);
-+		val8 += 0x80;
-+		val8 |= BIT(6);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&val8));
-+		RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
-+		adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
-+
-+		/* do polling cpwm */
-+		start_time = rtw_get_current_time();
-+		do {
-+
-+			rtw_mdelay_os(1);
-+
-+			rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
-+			if ((cpwm_orig ^ cpwm_now) & 0x80)
-+				break;
-+
-+			if (rtw_get_passing_time_ms(start_time) > 100) {
-+				RTW_INFO("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __FUNCTION__);
-+				break;
-+			}
-+		} while (1);
-+
-+#endif
-+		parm[0] = 0x0;
-+		parm[1] = 0x0;
-+		parm[2] = 0x0;
-+		rtw_hal_fill_h2c_cmd(padapter, H2C_INACTIVE_PS_,
-+				     H2C_INACTIVE_PS_LEN, parm);
-+#ifdef CONFIG_BT_COEXIST
-+		rtw_btcoex_IpsNotify(padapter, IPS_NONE);
-+#endif
-+	}
-+}
-+#endif /* CONFIG_PNO_SUPPORT */
-+
-+void rtw_exec_lps(_adapter *padapter, u8 ps_mode)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+
-+	if (ps_mode == PS_MODE_ACTIVE) {
-+#ifdef CONFIG_LPS_ACK
-+		_enter_critical_mutex(&pwrpriv->lps_ack_mutex, NULL);
-+		rtw_sctx_init(&pwrpriv->lps_ack_sctx, 100);
-+#endif /* CONFIG_LPS_ACK */
-+
-+		rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));
-+		rtw_hal_set_hwreg(padapter, HW_VAR_LPS_STATE_CHK, (u8 *)(&ps_mode));
-+
-+#ifdef CONFIG_LPS_ACK
-+		_exit_critical_mutex(&pwrpriv->lps_ack_mutex, NULL);
-+#endif /* CONFIG_LPS_ACK */
-+	} else {
-+		if (MLME_IS_ASOC(padapter))
-+			rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));
-+		else
-+			RTW_INFO(FUNC_ADPT_FMT": It can't execute LPS without Wi-Fi connection!\n",
-+				FUNC_ADPT_ARG(padapter));
-+	}
-+}
-+
-+void rtw_lps_rfon_ctrl(_adapter *padapter, u8 rfon_ctrl)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	u8 rpwm = 0;
-+
-+	if (pwrpriv->bFwCurrentInPSMode && pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
-+		if (rfon_ctrl == rf_on) {
-+#ifdef CONFIG_LPS_LCLK
-+			if (pwrpriv->lps_level >= LPS_LCLK) {
-+				s32 ready = _FAIL;
-+				systime stime;
-+				s32 utime;
-+				u32 timeout; /* unit: ms */
-+
-+#ifdef LPS_RPWM_WAIT_MS
-+				timeout = LPS_RPWM_WAIT_MS;
-+#else
-+				timeout = 30;
-+#endif /* !LPS_RPWM_WAIT_MS */
-+
-+				stime = rtw_get_current_time();
-+				do {
-+					ready = rtw_register_task_alive(padapter, LPS_ALIVE);
-+					if (ready == _SUCCESS)
-+						break;
-+
-+					utime = rtw_get_passing_time_ms(stime);
-+					if (utime > timeout)
-+						break;
-+
-+					rtw_msleep_os(1);
-+				} while (1);
-+
-+				if (ready == _FAIL)
-+					RTW_INFO(FUNC_ADPT_FMT": It is not ready to leave 32K !!!\n", 
-+						FUNC_ADPT_ARG(padapter));
-+			}
-+#endif /* CONFIG_LPS_LCLK */
-+
-+#ifdef CONFIG_LPS_ACK
-+			_enter_critical_mutex(&pwrpriv->lps_ack_mutex, NULL);
-+			rtw_sctx_init(&pwrpriv->lps_ack_sctx, 100);
-+#endif /* CONFIG_LPS_ACK */
-+
-+			rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE_RFON_CTRL, (u8 *)(&rfon_ctrl));
-+			rtw_hal_set_hwreg(padapter, HW_VAR_LPS_RFON_CHK, (u8 *)(&rfon_ctrl));
-+
-+#ifdef CONFIG_LPS_ACK
-+			_exit_critical_mutex(&pwrpriv->lps_ack_mutex, NULL);
-+#endif /* CONFIG_LPS_ACK */
-+		} else {
-+			if (MLME_IS_ASOC(padapter)) {
-+#ifdef CONFIG_LPS_PG
-+				if (pwrpriv->lps_level == LPS_PG) {
-+						 if (rtw_hal_set_lps_pg_info_cmd(padapter) == _FAIL)
-+						 	RTW_INFO(FUNC_ADPT_FMT": Send PG H2C command Fail! \n", 
-+						 			    FUNC_ADPT_ARG(padapter));
-+				}
-+#endif /* CONFIG_LPS_PG */
-+				rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE_RFON_CTRL, (u8 *)(&rfon_ctrl));
-+			} else {
-+				RTW_INFO(FUNC_ADPT_FMT": It can't execute RFON without Wi-Fi connection!\n",
-+					FUNC_ADPT_ARG(padapter));
-+			}
-+
-+#ifdef CONFIG_LPS_LCLK
-+			if (pwrpriv->lps_level >= LPS_LCLK) {
-+				rtw_unregister_task_alive(padapter, LPS_ALIVE);
-+
-+				if (pwrpriv->alives == 0) {
-+					u8 polling_cnt = 0;
-+					u8 reg_val8 = 0;
-+					u8 result = _FAIL;
-+
-+					do {
-+						rtw_msleep_os(1);
-+						reg_val8 = rtw_read8(padapter, REG_CR);
-+						if (reg_val8 == 0xEA) {
-+							result= _SUCCESS;
-+							break;
-+						}
-+						polling_cnt++;
-+					} while (polling_cnt < 100);
-+
-+					if (result == _FAIL )
-+						RTW_INFO(FUNC_ADPT_FMT": It is not finished to enter 32K !!!\n", 
-+							FUNC_ADPT_ARG(padapter));
-+				}
-+			}
-+#endif /* CONFIG_LPS_LCLK */
-+		}
-+	} else {
-+		RTW_INFO(FUNC_ADPT_FMT": RFON can't work due to ps state is not in LPS !\n", 
-+							FUNC_ADPT_ARG(padapter));
-+	}
-+}
-+
-+void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+#endif
-+#ifdef CONFIG_WMMPS_STA	
-+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+#endif
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+#endif /* CONFIG_P2P */
-+#ifdef CONFIG_TDLS
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	_irqL irqL;
-+	int i, j;
-+	_list	*plist, *phead;
-+	struct sta_info *ptdls_sta;
-+#endif /* CONFIG_TDLS */
-+#ifdef CONFIG_LPS_PG
-+	u8 lps_pg_hdl_id = 0;
-+#endif
-+
-+
-+
-+	if (ps_mode > PM_Card_Disable) {
-+		return;
-+	}
-+
-+	if (pwrpriv->pwr_mode == ps_mode) {
-+		if (PS_MODE_ACTIVE == ps_mode)
-+			return;
-+
-+#ifndef CONFIG_BT_COEXIST
-+#ifdef CONFIG_WMMPS_STA	
-+		if (!rtw_is_wmmps_mode(padapter))
-+#endif /* CONFIG_WMMPS_STA */
-+			if ((pwrpriv->smart_ps == smart_ps) &&
-+			    (pwrpriv->bcn_ant_mode == bcn_ant_mode))
-+				return;
-+#endif /* !CONFIG_BT_COEXIST */
-+	}
-+
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+	if (PS_MODE_ACTIVE != ps_mode) {
-+		rtw_set_ps_rsvd_page(padapter);
-+		rtw_set_default_port_id(padapter);
-+	}
-+#endif
-+
-+#ifdef CONFIG_LPS_PG
-+	if ((PS_MODE_ACTIVE != ps_mode) && (pwrpriv->lps_level == LPS_PG)) {
-+		if (pwrpriv->wowlan_mode != _TRUE) {
-+				/*rtw_hal_set_lps_pg_info(padapter);*/
-+				lps_pg_hdl_id = LPS_PG_INFO_CFG;
-+				rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
-+		}
-+	}
-+#endif
-+
-+#ifdef CONFIG_LPS_LCLK
-+	_enter_pwrlock(&pwrpriv->lock);
-+#endif
-+
-+	/* if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) */
-+	if (ps_mode == PS_MODE_ACTIVE) {
-+		if (1
-+#ifdef CONFIG_BT_COEXIST
-+		    && (((rtw_btcoex_IsBtControlLps(padapter) == _FALSE)
-+#ifdef CONFIG_P2P_PS
-+			 && (pwdinfo->opp_ps == 0)
-+#endif /* CONFIG_P2P_PS */
-+			)
-+			|| ((rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
-+			    && (rtw_btcoex_IsLpsOn(padapter) == _FALSE))
-+		       )
-+#else /* !CONFIG_BT_COEXIST */
-+#ifdef CONFIG_P2P_PS
-+		    && (pwdinfo->opp_ps == 0)
-+#endif /* CONFIG_P2P_PS */
-+#endif /* !CONFIG_BT_COEXIST */
-+		   ) {
-+			RTW_INFO(FUNC_ADPT_FMT" Leave 802.11 power save - %s\n",
-+				 FUNC_ADPT_ARG(padapter), msg);
-+
-+			if (pwrpriv->lps_leave_cnts < UINT_MAX)
-+				pwrpriv->lps_leave_cnts++;
-+			else
-+				pwrpriv->lps_leave_cnts = 0;
-+#ifdef CONFIG_TDLS
-+			for (i = 0; i < NUM_STA; i++) {
-+				phead = &(pstapriv->sta_hash[i]);
-+				plist = get_next(phead);
-+
-+				while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+					ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+
-+					if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
-+						issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0);
-+					plist = get_next(plist);
-+				}
-+			}
-+#endif /* CONFIG_TDLS */
-+
-+			pwrpriv->pwr_mode = ps_mode;
-+			rtw_set_rpwm(padapter, PS_STATE_S4);
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)
-+			if (pwrpriv->wowlan_mode == _TRUE ||
-+			    pwrpriv->wowlan_ap_mode == _TRUE ||
-+			    pwrpriv->wowlan_p2p_mode == _TRUE) {
-+				systime start_time;
-+				u32 delay_ms;
-+				u8 val8;
-+				delay_ms = 20;
-+				start_time = rtw_get_current_time();
-+				do {
-+					rtw_hal_get_hwreg(padapter, HW_VAR_SYS_CLKR, &val8);
-+					if (!(val8 & BIT(4))) { /* 0x08 bit4 =1 --> in 32k, bit4 = 0 --> leave 32k */
-+						pwrpriv->cpwm = PS_STATE_S4;
-+						break;
-+					}
-+					if (rtw_get_passing_time_ms(start_time) > delay_ms) {
-+						RTW_INFO("%s: Wait for FW 32K leave more than %u ms!!!\n",
-+							__FUNCTION__, delay_ms);
-+						pdbgpriv->dbg_wow_leave_ps_fail_cnt++;
-+						break;
-+					}
-+					rtw_usleep_os(100);
-+				} while (1);
-+			}
-+#endif
-+#ifdef CONFIG_LPS_PG
-+			if (pwrpriv->lps_level == LPS_PG) {
-+				lps_pg_hdl_id = LPS_PG_REDLEMEM;
-+				rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
-+			}
-+#endif
-+#ifdef CONFIG_WOWLAN
-+			if (pwrpriv->wowlan_mode == _TRUE)
-+				rtw_hal_set_hwreg(padapter, HW_VAR_H2C_INACTIVE_IPS, (u8 *)(&ps_mode));
-+#endif /* CONFIG_WOWLAN */
-+
-+			rtw_exec_lps(padapter, ps_mode);
-+
-+#ifdef CONFIG_LPS_PG
-+			if (pwrpriv->lps_level == LPS_PG) {
-+				lps_pg_hdl_id = LPS_PG_PHYDM_EN;
-+				rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
-+			}
-+#endif
-+
-+#ifdef CONFIG_LPS_POFF
-+			rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_SET_MODE,
-+					  (u8 *)(&ps_mode));
-+#endif /*CONFIG_LPS_POFF*/
-+
-+			pwrpriv->bFwCurrentInPSMode = _FALSE;
-+
-+#ifdef CONFIG_BT_COEXIST
-+			rtw_btcoex_LpsNotify(padapter, ps_mode);
-+#endif /* CONFIG_BT_COEXIST */
-+		}
-+	} else {
-+		if ((PS_RDY_CHECK(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE))
-+#ifdef CONFIG_BT_COEXIST
-+		    || ((rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
-+			&& (rtw_btcoex_IsLpsOn(padapter) == _TRUE))
-+#endif
-+#ifdef CONFIG_P2P_WOWLAN
-+		    || (_TRUE == pwrpriv->wowlan_p2p_mode)
-+#endif /* CONFIG_P2P_WOWLAN */
-+#ifdef CONFIG_WOWLAN
-+			|| WOWLAN_IS_STA_MIX_MODE(padapter)
-+#endif /* CONFIG_WOWLAN */
-+		   ) {
-+			u8 pslv;
-+
-+			RTW_INFO(FUNC_ADPT_FMT" Enter 802.11 power save - %s\n",
-+				 FUNC_ADPT_ARG(padapter), msg);
-+
-+			if (pwrpriv->lps_enter_cnts < UINT_MAX)
-+				pwrpriv->lps_enter_cnts++;
-+			else
-+				pwrpriv->lps_enter_cnts = 0;
-+#ifdef CONFIG_TDLS
-+			for (i = 0; i < NUM_STA; i++) {
-+				phead = &(pstapriv->sta_hash[i]);
-+				plist = get_next(phead);
-+
-+				while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+					ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+
-+					if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
-+						issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 0, 0);
-+					plist = get_next(plist);
-+				}
-+			}
-+#endif /* CONFIG_TDLS */
-+
-+#ifdef CONFIG_BT_COEXIST
-+			rtw_btcoex_LpsNotify(padapter, ps_mode);
-+#endif /* CONFIG_BT_COEXIST */
-+
-+#ifdef CONFIG_LPS_POFF
-+			rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_SET_MODE,
-+					  (u8 *)(&ps_mode));
-+#endif /*CONFIG_LPS_POFF*/
-+
-+			pwrpriv->bFwCurrentInPSMode = _TRUE;
-+			pwrpriv->pwr_mode = ps_mode;
-+			pwrpriv->smart_ps = smart_ps;
-+			pwrpriv->bcn_ant_mode = bcn_ant_mode;
-+#ifdef CONFIG_LPS_PG
-+			if (pwrpriv->lps_level == LPS_PG) {
-+				lps_pg_hdl_id = LPS_PG_PHYDM_DIS;
-+				rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
-+			}
-+#endif
-+
-+#ifdef CONFIG_WMMPS_STA	
-+			pwrpriv->wmm_smart_ps = pregistrypriv->wmm_smart_ps;
-+#endif /* CONFIG_WMMPS_STA */
-+			
-+			rtw_exec_lps(padapter, ps_mode);
-+			
-+#ifdef CONFIG_WOWLAN
-+			if (pwrpriv->wowlan_mode == _TRUE)
-+				rtw_hal_set_hwreg(padapter, HW_VAR_H2C_INACTIVE_IPS, (u8 *)(&ps_mode));
-+#endif /* CONFIG_WOWLAN */
-+
-+#ifdef CONFIG_P2P_PS
-+			/* Set CTWindow after LPS */
-+			if (pwdinfo->opp_ps == 1)
-+				p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 0);
-+#endif /* CONFIG_P2P_PS */
-+
-+			pslv = PS_STATE_S2;
-+#ifdef CONFIG_LPS_LCLK
-+			if (pwrpriv->alives == 0)
-+				pslv = PS_STATE_S0;
-+#endif /* CONFIG_LPS_LCLK */
-+
-+#ifdef CONFIG_BT_COEXIST
-+			if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)
-+			    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {
-+				u8 val8;
-+
-+				val8 = rtw_btcoex_LpsVal(padapter);
-+				if (val8 & BIT(4))
-+					pslv = PS_STATE_S2;
-+
-+			}
-+#endif /* CONFIG_BT_COEXIST */
-+
-+			rtw_set_rpwm(padapter, pslv);
-+		}
-+	}
-+
-+#ifdef CONFIG_LPS_LCLK
-+	_exit_pwrlock(&pwrpriv->lock);
-+#endif
-+
-+}
-+
-+const char * const LPS_CTRL_PHYDM = "LPS_CTRL_PHYDM";
-+
-+/*
-+ *	Description:
-+ *		Enter the leisure power save mode.
-+ *   */
-+void LPS_Enter(PADAPTER padapter, const char *msg)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(dvobj);
-+	int i;
-+	char buf[32] = {0};
-+#ifdef DBG_LA_MODE
-+	struct registry_priv *registry_par = &(padapter->registrypriv);
-+#endif
-+
-+	/*	RTW_INFO("+LeisurePSEnter\n"); */
-+	if (GET_HAL_DATA(padapter)->bFWReady == _FALSE)
-+		return;
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
-+		return;
-+#endif
-+
-+#ifdef DBG_LA_MODE
-+	if(registry_par->la_mode_en == 1) {
-+		RTW_INFO("%s LA debug mode lps_leave \n", __func__);
-+		return;
-+	}
-+#endif
-+	/* Skip lps enter request if number of assocated adapters is not 1 */
-+	if (rtw_mi_get_assoc_if_num(padapter) != 1)
-+		return;
-+
-+#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
-+	/* Skip lps enter request for adapter not port0 */
-+	if (get_hw_port(padapter) != HW_PORT0)
-+		return;
-+#endif
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		if (PS_RDY_CHECK(dvobj->padapters[i]) == _FALSE)
-+			return;
-+	}
-+
-+#ifdef CONFIG_CLIENT_PORT_CFG
-+	if ((rtw_hal_get_port(padapter) == CLT_PORT_INVALID) ||
-+		get_clt_num(padapter) > MAX_CLIENT_PORT_NUM){
-+		RTW_ERR(ADPT_FMT" cannot get client port or clt num(%d) over than 4\n", ADPT_ARG(padapter), get_clt_num(padapter));
-+		return;
-+	}
-+#endif
-+
-+#ifdef CONFIG_P2P_PS
-+	if (padapter->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
-+		return;/* supporting p2p client ps NOA via H2C_8723B_P2P_PS_OFFLOAD */
-+	}
-+#endif /* CONFIG_P2P_PS */
-+
-+	if (pwrpriv->bLeisurePs) {
-+		/* Idle for a while if we connect to AP a while ago. */
-+		if (pwrpriv->LpsIdleCount >= 2) { /* 4 Sec */
-+			if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) {
-+
-+#ifdef CONFIG_WMMPS_STA
-+				if (rtw_is_wmmps_mode(padapter))
-+					msg = "WMMPS_IDLE";
-+#endif /* CONFIG_WMMPS_STA */
-+				
-+				sprintf(buf, "WIFI-%s", msg);
-+				pwrpriv->bpower_saving = _TRUE;
-+				
-+#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
-+				pwrpriv->pwr_saving_start_time = rtw_get_current_time();
-+#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
-+
-+				rtw_set_ps_mode(padapter, pwrpriv->power_mgnt, padapter->registrypriv.smart_ps, 0, buf);
-+
-+#ifdef CONFIG_PCI_DYNAMIC_ASPM
-+				if (msg != LPS_CTRL_PHYDM)
-+					rtw_pci_dynamic_aspm_set_mode(padapter, ASPM_MODE_PS);
-+#endif
-+			}
-+		} else
-+			pwrpriv->LpsIdleCount++;
-+	}
-+
-+	/*	RTW_INFO("-LeisurePSEnter\n"); */
-+
-+}
-+
-+/*
-+ *	Description:
-+ *		Leave the leisure power save mode.
-+ *   */
-+void LPS_Leave(PADAPTER padapter, const char *msg)
-+{
-+#define LPS_LEAVE_TIMEOUT_MS 100
-+
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(dvobj);
-+	char buf[32] = {0};
-+#ifdef DBG_CHECK_FW_PS_STATE
-+	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
-+#endif
-+
-+
-+	/*	RTW_INFO("+LeisurePSLeave\n"); */
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
-+		return;
-+#endif
-+
-+	if (pwrpriv->bLeisurePs) {
-+		if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
-+#ifdef CONFIG_PCI_DYNAMIC_ASPM
-+			if (msg != LPS_CTRL_PHYDM)
-+				rtw_pci_dynamic_aspm_set_mode(padapter, ASPM_MODE_PERF);
-+#endif
-+#ifdef CONFIG_WMMPS_STA
-+			if (rtw_is_wmmps_mode(padapter))
-+				msg = "WMMPS_BUSY";
-+#endif /* CONFIG_WMMPS_STA */
-+			
-+			sprintf(buf, "WIFI-%s", msg);
-+			rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, buf);
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS	
-+			pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);
-+#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
-+		}
-+	}
-+
-+	pwrpriv->bpower_saving = _FALSE;
-+#ifdef DBG_CHECK_FW_PS_STATE
-+	if (rtw_fw_ps_state(padapter) == _FAIL) {
-+		RTW_INFO("leave lps, fw in 32k\n");
-+		pdbgpriv->dbg_leave_lps_fail_cnt++;
-+	}
-+#endif /* DBG_CHECK_FW_PS_STATE
-+ * 	RTW_INFO("-LeisurePSLeave\n"); */
-+
-+}
-+
-+#ifdef CONFIG_WOWLAN
-+void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+
-+	if (wow_en) {
-+		pwrpriv->lps_level_bk = pwrpriv->lps_level;
-+		pwrpriv->lps_level = pwrpriv->wowlan_lps_level;
-+		#ifdef CONFIG_LPS_1T1R
-+		pwrpriv->lps_1t1r_bk = pwrpriv->lps_1t1r;
-+		pwrpriv->lps_1t1r = pwrpriv->wowlan_lps_1t1r;
-+		#endif
-+	} else {
-+		pwrpriv->lps_level = pwrpriv->lps_level_bk;
-+		#ifdef CONFIG_LPS_1T1R
-+		pwrpriv->lps_1t1r = pwrpriv->lps_1t1r_bk;
-+		#endif
-+	}
-+}
-+#endif /* CONFIG_WOWLAN */
-+#endif /* CONFIG_LPS */
-+
-+void LeaveAllPowerSaveModeDirect(PADAPTER Adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
-+	PADAPTER pri_padapter = GET_PRIMARY_ADAPTER(Adapter);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);
-+#ifdef CONFIG_LPS_LCLK
-+#ifndef CONFIG_DETECT_CPWM_BY_POLLING
-+	u8 cpwm_orig;
-+#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
-+	u8 rpwm;
-+#endif
-+	int i;
-+
-+	RTW_INFO("%s.....\n", __FUNCTION__);
-+
-+	if (rtw_is_surprise_removed(Adapter)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter));
-+		return;
-+	}
-+
-+	if (rtw_mi_check_status(Adapter, MI_LINKED)) { /*connect*/
-+
-+		if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) {
-+			RTW_INFO("%s: Driver Already Leave LPS\n", __FUNCTION__);
-+			return;
-+		}
-+
-+#ifdef CONFIG_LPS_LCLK
-+		_enter_pwrlock(&pwrpriv->lock);
-+
-+#ifndef CONFIG_DETECT_CPWM_BY_POLLING
-+		cpwm_orig = 0;
-+		rtw_hal_get_hwreg(Adapter, HW_VAR_CPWM, &cpwm_orig);
-+#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
-+		rpwm = rtw_set_rpwm(Adapter, PS_STATE_S4);
-+
-+#ifndef CONFIG_DETECT_CPWM_BY_POLLING
-+		if (rpwm != 0xFF && rpwm & PS_ACK)
-+			rtw_cpwm_polling(Adapter, rpwm, cpwm_orig);
-+#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
-+
-+		_exit_pwrlock(&pwrpriv->lock);
-+#endif/*CONFIG_LPS_LCLK*/
-+
-+#ifdef CONFIG_P2P_PS
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			_adapter *iface = dvobj->padapters[i];
-+			struct wifidirect_info *pwdinfo = &(iface->wdinfo);
-+
-+			if (pwdinfo->p2p_ps_mode > P2P_PS_NONE)
-+				p2p_ps_wk_cmd(iface, P2P_PS_DISABLE, 0);
-+		}
-+#endif /* CONFIG_P2P_PS */
-+
-+#ifdef CONFIG_LPS
-+		rtw_lps_ctrl_wk_cmd(pri_padapter, LPS_CTRL_LEAVE, RTW_CMDF_DIRECTLY);
-+#endif
-+	} else {
-+		if (pwrpriv->rf_pwrstate == rf_off) {
-+
-+#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_RTL8188E)
-+#ifdef CONFIG_IPS
-+			if (_FALSE == ips_leave(pri_padapter))
-+				RTW_INFO("======> ips_leave fail.............\n");
-+#endif
-+#endif /* CONFIG_SWLPS_IN_IPS || (CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E) */
-+
-+		}
-+	}
-+
-+}
-+
-+/*
-+ * Description: Leave all power save mode: LPS, FwLPS, IPS if needed.
-+ * Move code to function by tynli. 2010.03.26.
-+ *   */
-+void LeaveAllPowerSaveMode(PADAPTER Adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
-+	u8	enqueue = 0;
-+	int i;
-+
-+	#ifndef CONFIG_NEW_NETDEV_HDL
-+	if (_FALSE == Adapter->bup) {
-+		RTW_INFO(FUNC_ADPT_FMT ": bup=%d Skip!\n",
-+			 FUNC_ADPT_ARG(Adapter), Adapter->bup);
-+		return;
-+	}
-+	#endif
-+
-+/*	RTW_INFO(FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(Adapter));*/
-+
-+	if (rtw_is_surprise_removed(Adapter)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter));
-+		return;
-+	}
-+
-+	if (rtw_mi_get_assoc_if_num(Adapter)) {
-+		/* connect */
-+#ifdef CONFIG_LPS_LCLK
-+		enqueue = 1;
-+#endif
-+
-+#ifdef CONFIG_P2P_PS
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			_adapter *iface = dvobj->padapters[i];
-+			struct wifidirect_info *pwdinfo = &(iface->wdinfo);
-+
-+			if (pwdinfo->p2p_ps_mode > P2P_PS_NONE)
-+				p2p_ps_wk_cmd(iface, P2P_PS_DISABLE, enqueue);
-+		}
-+#endif /* CONFIG_P2P_PS */
-+
-+#ifdef CONFIG_LPS
-+		rtw_lps_ctrl_wk_cmd(Adapter, LPS_CTRL_LEAVE, enqueue ? 0 : RTW_CMDF_DIRECTLY);
-+#endif
-+
-+#ifdef CONFIG_LPS_LCLK
-+		LPS_Leave_check(Adapter);
-+#endif
-+	} else {
-+		if (adapter_to_pwrctl(Adapter)->rf_pwrstate == rf_off) {
-+			
-+#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) || (defined(CONFIG_PLATFORM_SPRD) && defined(CONFIG_RTL8188E))
-+#ifdef CONFIG_IPS
-+			if (_FALSE == ips_leave(Adapter))
-+				RTW_INFO("======> ips_leave fail.............\n");
-+#endif
-+#endif /* CONFIG_SWLPS_IN_IPS || (CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E) */
-+			
-+		}
-+	}
-+
-+}
-+
-+#ifdef CONFIG_LPS_LCLK
-+void LPS_Leave_check(
-+	PADAPTER padapter)
-+{
-+	struct pwrctrl_priv *pwrpriv;
-+	systime	start_time;
-+	u8	bReady;
-+
-+
-+	pwrpriv = adapter_to_pwrctl(padapter);
-+
-+	bReady = _FALSE;
-+	start_time = rtw_get_current_time();
-+
-+	rtw_yield_os();
-+
-+	while (1) {
-+		_enter_pwrlock(&pwrpriv->lock);
-+
-+		if (rtw_is_surprise_removed(padapter)
-+		    || (!rtw_is_hw_init_completed(padapter))
-+#ifdef CONFIG_USB_HCI
-+		    || rtw_is_drv_stopped(padapter)
-+#endif
-+		    || (pwrpriv->pwr_mode == PS_MODE_ACTIVE)
-+		   )
-+			bReady = _TRUE;
-+
-+		_exit_pwrlock(&pwrpriv->lock);
-+
-+		if (_TRUE == bReady)
-+			break;
-+
-+		if (rtw_get_passing_time_ms(start_time) > 100) {
-+			RTW_ERR("Wait for cpwm event  than 100 ms!!!\n");
-+			break;
-+		}
-+		rtw_msleep_os(1);
-+	}
-+
-+}
-+
-+/*
-+ * Caller:ISR handler...
-+ *
-+ * This will be called when CPWM interrupt is up.
-+ *
-+ * using to update cpwn of drv; and drv willl make a decision to up or down pwr level
-+ */
-+void cpwm_int_hdl(
-+	PADAPTER padapter,
-+	struct reportpwrstate_parm *preportpwrstate)
-+{
-+	struct pwrctrl_priv *pwrpriv;
-+
-+	if (!padapter)
-+		goto exit;
-+
-+	if (RTW_CANNOT_RUN(padapter))
-+		goto exit;
-+
-+	pwrpriv = adapter_to_pwrctl(padapter);
-+#if 0
-+	if (pwrpriv->cpwm_tog == (preportpwrstate->state & PS_TOGGLE)) {
-+		goto exit;
-+	}
-+#endif
-+
-+	_enter_pwrlock(&pwrpriv->lock);
-+
-+#ifdef CONFIG_LPS_RPWM_TIMER
-+	if (pwrpriv->rpwm < PS_STATE_S2) {
-+		RTW_INFO("%s: Redundant CPWM Int. RPWM=0x%02X CPWM=0x%02x\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
-+		_exit_pwrlock(&pwrpriv->lock);
-+		goto exit;
-+	}
-+#endif /* CONFIG_LPS_RPWM_TIMER */
-+
-+	pwrpriv->cpwm = PS_STATE(preportpwrstate->state);
-+	pwrpriv->cpwm_tog = preportpwrstate->state & PS_TOGGLE;
-+
-+	if (pwrpriv->cpwm >= PS_STATE_S2) {
-+		if (pwrpriv->alives & CMD_ALIVE)
-+			_rtw_up_sema(&padapter->cmdpriv.cmd_queue_sema);
-+
-+		if (pwrpriv->alives & XMIT_ALIVE)
-+			_rtw_up_sema(&padapter->xmitpriv.xmit_sema);
-+	}
-+
-+	_exit_pwrlock(&pwrpriv->lock);
-+
-+exit:
-+	return;
-+}
-+
-+static void cpwm_event_callback(struct work_struct *work)
-+{
-+	struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, cpwm_event);
-+	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
-+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
-+	struct reportpwrstate_parm report;
-+
-+	/* RTW_INFO("%s\n",__FUNCTION__); */
-+
-+	report.state = PS_STATE_S2;
-+	cpwm_int_hdl(adapter, &report);
-+}
-+
-+static void dma_event_callback(struct work_struct *work)
-+{
-+	struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, dma_event);
-+	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
-+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
-+
-+	rtw_unregister_tx_alive(adapter);
-+}
-+
-+#ifdef CONFIG_LPS_RPWM_TIMER
-+
-+#define DBG_CPWM_CHK_FAIL
-+#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) \
-+				   || defined(CONFIG_RTL8723F))
-+#define CPU_EXCEPTION_CODE 0xFAFAFAFA
-+static void rtw_cpwm_chk_fail_debug(_adapter *padapter)
-+{
-+	u32 cpu_state;
-+
-+	cpu_state = rtw_read32(padapter, 0x10FC);
-+
-+	RTW_INFO("[PS-DBG] Reg_10FC =0x%08x\n", cpu_state);
-+	RTW_INFO("[PS-DBG] Reg_10F8 =0x%08x\n", rtw_read32(padapter, 0x10F8));
-+	RTW_INFO("[PS-DBG] Reg_11F8 =0x%08x\n", rtw_read32(padapter, 0x11F8));
-+	RTW_INFO("[PS-DBG] Reg_4A4 =0x%08x\n", rtw_read32(padapter, 0x4A4));
-+	RTW_INFO("[PS-DBG] Reg_4A8 =0x%08x\n", rtw_read32(padapter, 0x4A8));
-+
-+	if (cpu_state == CPU_EXCEPTION_CODE) {
-+		RTW_INFO("[PS-DBG] Reg_48C =0x%08x\n", rtw_read32(padapter, 0x48C));
-+		RTW_INFO("[PS-DBG] Reg_490 =0x%08x\n", rtw_read32(padapter, 0x490));
-+		RTW_INFO("[PS-DBG] Reg_494 =0x%08x\n", rtw_read32(padapter, 0x494));
-+		RTW_INFO("[PS-DBG] Reg_498 =0x%08x\n", rtw_read32(padapter, 0x498));
-+		RTW_INFO("[PS-DBG] Reg_49C =0x%08x\n", rtw_read32(padapter, 0x49C));
-+		RTW_INFO("[PS-DBG] Reg_4A0 =0x%08x\n", rtw_read32(padapter, 0x4A0));
-+		RTW_INFO("[PS-DBG] Reg_1BC =0x%08x\n", rtw_read32(padapter, 0x1BC));
-+
-+		RTW_INFO("[PS-DBG] Reg_008 =0x%08x\n", rtw_read32(padapter, 0x08));
-+		RTW_INFO("[PS-DBG] Reg_2F0 =0x%08x\n", rtw_read32(padapter, 0x2F0));
-+		RTW_INFO("[PS-DBG] Reg_2F4 =0x%08x\n", rtw_read32(padapter, 0x2F4));
-+		RTW_INFO("[PS-DBG] Reg_2F8 =0x%08x\n", rtw_read32(padapter, 0x2F8));
-+		RTW_INFO("[PS-DBG] Reg_2FC =0x%08x\n", rtw_read32(padapter, 0x2FC));
-+
-+		rtw_dump_fifo(RTW_DBGDUMP, padapter, 5, 0, 3072);
-+	}
-+}
-+#endif
-+static void rpwmtimeout_workitem_callback(struct work_struct *work)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *dvobj;
-+	struct pwrctrl_priv *pwrpriv;
-+
-+
-+	pwrpriv = container_of(work, struct pwrctrl_priv, rpwmtimeoutwi);
-+	dvobj = pwrctl_to_dvobj(pwrpriv);
-+	padapter = dvobj_get_primary_adapter(dvobj);
-+
-+	if (!padapter)
-+		return;
-+
-+	if (RTW_CANNOT_RUN(padapter))
-+		return;
-+
-+	_enter_pwrlock(&pwrpriv->lock);
-+	if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {
-+		RTW_INFO("%s: rpwm=0x%02X cpwm=0x%02X CPWM done!\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
-+		goto exit;
-+	}
-+
-+	if (pwrpriv->rpwm_retry++ < LPS_RPWM_RETRY_CNT) {
-+		u8 rpwm = (pwrpriv->rpwm | pwrpriv->tog | PS_ACK);
-+
-+		rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));
-+
-+		pwrpriv->tog += 0x80;
-+		_set_timer(&pwrpriv->pwr_rpwm_timer, LPS_CPWM_TIMEOUT_MS);
-+		goto exit;
-+	}
-+
-+	pwrpriv->rpwm_retry = 0;
-+	_exit_pwrlock(&pwrpriv->lock);
-+
-+#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) \
-+				   || defined(CONFIG_RTL8723F))
-+	RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
-+	rtw_cpwm_chk_fail_debug(padapter);
-+#endif
-+
-+	if (rtw_read8(padapter, 0x100) != 0xEA) {
-+#if 1
-+		struct reportpwrstate_parm report;
-+
-+		report.state = PS_STATE_S2;
-+		RTW_INFO("\n%s: FW already leave 32K!\n\n", __func__);
-+		cpwm_int_hdl(padapter, &report);
-+#else
-+		RTW_INFO("\n%s: FW already leave 32K!\n\n", __func__);
-+		cpwm_event_callback(&pwrpriv->cpwm_event);
-+#endif
-+		return;
-+	}
-+
-+	_enter_pwrlock(&pwrpriv->lock);
-+
-+	if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {
-+		RTW_INFO("%s: cpwm=%d, nothing to do!\n", __func__, pwrpriv->cpwm);
-+		goto exit;
-+	}
-+	pwrpriv->brpwmtimeout = _TRUE;
-+	rtw_set_rpwm(padapter, pwrpriv->rpwm);
-+	pwrpriv->brpwmtimeout = _FALSE;
-+
-+exit:
-+	_exit_pwrlock(&pwrpriv->lock);
-+}
-+
-+/*
-+ * This function is a timer handler, can't do any IO in it.
-+ */
-+static void pwr_rpwm_timeout_handler(void *FunctionContext)
-+{
-+	PADAPTER padapter;
-+	struct pwrctrl_priv *pwrpriv;
-+
-+
-+	padapter = (PADAPTER)FunctionContext;
-+	pwrpriv = adapter_to_pwrctl(padapter);
-+	if (!padapter)
-+		return;
-+
-+	if (RTW_CANNOT_RUN(padapter))
-+		return;
-+
-+	RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
-+
-+	if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {
-+		RTW_INFO("+%s: cpwm=%d, nothing to do!\n", __func__, pwrpriv->cpwm);
-+		return;
-+	}
-+
-+	_set_workitem(&pwrpriv->rpwmtimeoutwi);
-+}
-+#endif /* CONFIG_LPS_RPWM_TIMER */
-+
-+__inline static void register_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag)
-+{
-+	pwrctrl->alives |= tag;
-+}
-+
-+__inline static void unregister_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag)
-+{
-+	pwrctrl->alives &= ~tag;
-+}
-+
-+
-+/*
-+ * Description:
-+ *	Check if the fw_pwrstate is okay for I/O.
-+ *	If not (cpwm is less than S2), then the sub-routine
-+ *	will raise the cpwm to be greater than or equal to S2.
-+ *
-+ *	Calling Context: Passive
-+ *
-+ *	Constraint:
-+ *		1. this function will request pwrctrl->lock
-+ *
-+ * Return Value:
-+ *	_SUCCESS	hardware is ready for I/O
-+ *	_FAIL		can't I/O right now
-+ */
-+s32 rtw_register_task_alive(PADAPTER padapter, u32 task)
-+{
-+	s32 res;
-+	struct pwrctrl_priv *pwrctrl;
-+	u8 pslv;
-+
-+
-+	res = _SUCCESS;
-+	pwrctrl = adapter_to_pwrctl(padapter);
-+	pslv = PS_STATE_S2;
-+
-+	_enter_pwrlock(&pwrctrl->lock);
-+
-+	register_task_alive(pwrctrl, task);
-+
-+	if (pwrctrl->bFwCurrentInPSMode == _TRUE) {
-+
-+		if (pwrctrl->cpwm < pslv) {
-+			if (pwrctrl->cpwm < PS_STATE_S2)
-+				res = _FAIL;
-+			if (pwrctrl->rpwm < pslv)
-+				rtw_set_rpwm(padapter, pslv);
-+		}
-+	}
-+
-+	_exit_pwrlock(&pwrctrl->lock);
-+
-+#ifdef CONFIG_DETECT_CPWM_BY_POLLING
-+	if (_FAIL == res) {
-+		if (pwrctrl->cpwm >= PS_STATE_S2)
-+			res = _SUCCESS;
-+	}
-+#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
-+
-+
-+	return res;
-+}
-+
-+/*
-+ * Description:
-+ *	If task is done, call this func. to power down firmware again.
-+ *
-+ *	Constraint:
-+ *		1. this function will request pwrctrl->lock
-+ *
-+ * Return Value:
-+ *	none
-+ */
-+void rtw_unregister_task_alive(PADAPTER padapter, u32 task)
-+{
-+	struct pwrctrl_priv *pwrctrl;
-+	u8 pslv;
-+
-+
-+	pwrctrl = adapter_to_pwrctl(padapter);
-+	pslv = PS_STATE_S0;
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)
-+	    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {
-+		u8 val8;
-+
-+		val8 = rtw_btcoex_LpsVal(padapter);
-+		if (val8 & BIT(4))
-+			pslv = PS_STATE_S2;
-+
-+	}
-+#endif /* CONFIG_BT_COEXIST */
-+
-+	_enter_pwrlock(&pwrctrl->lock);
-+
-+	unregister_task_alive(pwrctrl, task);
-+
-+	if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)
-+	    && (pwrctrl->bFwCurrentInPSMode == _TRUE)) {
-+
-+		if (pwrctrl->cpwm > pslv) {
-+			if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))
-+				rtw_set_rpwm(padapter, pslv);
-+		}
-+	}
-+
-+	_exit_pwrlock(&pwrctrl->lock);
-+
-+}
-+
-+/*
-+ * Caller: rtw_xmit_thread
-+ *
-+ * Check if the fw_pwrstate is okay for xmit.
-+ * If not (cpwm is less than S3), then the sub-routine
-+ * will raise the cpwm to be greater than or equal to S3.
-+ *
-+ * Calling Context: Passive
-+ *
-+ * Return Value:
-+ *	 _SUCCESS	rtw_xmit_thread can write fifo/txcmd afterwards.
-+ *	 _FAIL		rtw_xmit_thread can not do anything.
-+ */
-+s32 rtw_register_tx_alive(PADAPTER padapter)
-+{
-+	s32 res;
-+	struct pwrctrl_priv *pwrctrl;
-+	u8 pslv;
-+
-+
-+	res = _SUCCESS;
-+	pwrctrl = adapter_to_pwrctl(padapter);
-+	pslv = PS_STATE_S2;
-+
-+	_enter_pwrlock(&pwrctrl->lock);
-+
-+	register_task_alive(pwrctrl, XMIT_ALIVE);
-+
-+	if (pwrctrl->bFwCurrentInPSMode == _TRUE) {
-+
-+		if (pwrctrl->cpwm < pslv) {
-+			if (pwrctrl->cpwm < PS_STATE_S2)
-+				res = _FAIL;
-+			if (pwrctrl->rpwm < pslv)
-+				rtw_set_rpwm(padapter, pslv);
-+		}
-+	}
-+
-+	_exit_pwrlock(&pwrctrl->lock);
-+
-+#ifdef CONFIG_DETECT_CPWM_BY_POLLING
-+	if (_FAIL == res) {
-+		if (pwrctrl->cpwm >= PS_STATE_S2)
-+			res = _SUCCESS;
-+	}
-+#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
-+
-+
-+	return res;
-+}
-+
-+/*
-+ * Caller: rtw_cmd_thread
-+ *
-+ * Check if the fw_pwrstate is okay for issuing cmd.
-+ * If not (cpwm should be is less than S2), then the sub-routine
-+ * will raise the cpwm to be greater than or equal to S2.
-+ *
-+ * Calling Context: Passive
-+ *
-+ * Return Value:
-+ *	_SUCCESS	rtw_cmd_thread can issue cmds to firmware afterwards.
-+ *	_FAIL		rtw_cmd_thread can not do anything.
-+ */
-+s32 rtw_register_cmd_alive(PADAPTER padapter)
-+{
-+	s32 res;
-+	struct pwrctrl_priv *pwrctrl;
-+	u8 pslv;
-+
-+
-+	res = _SUCCESS;
-+	pwrctrl = adapter_to_pwrctl(padapter);
-+	pslv = PS_STATE_S2;
-+
-+	_enter_pwrlock(&pwrctrl->lock);
-+
-+	register_task_alive(pwrctrl, CMD_ALIVE);
-+
-+	if (pwrctrl->bFwCurrentInPSMode == _TRUE) {
-+
-+		if (pwrctrl->cpwm < pslv) {
-+			if (pwrctrl->cpwm < PS_STATE_S2)
-+				res = _FAIL;
-+			if (pwrctrl->rpwm < pslv)
-+				rtw_set_rpwm(padapter, pslv);
-+		}
-+	}
-+
-+	_exit_pwrlock(&pwrctrl->lock);
-+
-+#ifdef CONFIG_DETECT_CPWM_BY_POLLING
-+	if (_FAIL == res) {
-+		if (pwrctrl->cpwm >= PS_STATE_S2)
-+			res = _SUCCESS;
-+	}
-+#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
-+
-+
-+	return res;
-+}
-+
-+/*
-+ * Caller: rx_isr
-+ *
-+ * Calling Context: Dispatch/ISR
-+ *
-+ * Return Value:
-+ *	_SUCCESS
-+ *	_FAIL
-+ */
-+s32 rtw_register_rx_alive(PADAPTER padapter)
-+{
-+	struct pwrctrl_priv *pwrctrl;
-+
-+
-+	pwrctrl = adapter_to_pwrctl(padapter);
-+
-+	_enter_pwrlock(&pwrctrl->lock);
-+
-+	register_task_alive(pwrctrl, RECV_ALIVE);
-+
-+	_exit_pwrlock(&pwrctrl->lock);
-+
-+
-+	return _SUCCESS;
-+}
-+
-+/*
-+ * Caller: evt_isr or evt_thread
-+ *
-+ * Calling Context: Dispatch/ISR or Passive
-+ *
-+ * Return Value:
-+ *	_SUCCESS
-+ *	_FAIL
-+ */
-+s32 rtw_register_evt_alive(PADAPTER padapter)
-+{
-+	struct pwrctrl_priv *pwrctrl;
-+
-+
-+	pwrctrl = adapter_to_pwrctl(padapter);
-+
-+	_enter_pwrlock(&pwrctrl->lock);
-+
-+	register_task_alive(pwrctrl, EVT_ALIVE);
-+
-+	_exit_pwrlock(&pwrctrl->lock);
-+
-+
-+	return _SUCCESS;
-+}
-+
-+/*
-+ * Caller: ISR
-+ *
-+ * If ISR's txdone,
-+ * No more pkts for TX,
-+ * Then driver shall call this fun. to power down firmware again.
-+ */
-+void rtw_unregister_tx_alive(PADAPTER padapter)
-+{
-+	struct pwrctrl_priv *pwrctrl;
-+	_adapter *iface;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	u8 pslv, i;
-+
-+
-+	pwrctrl = adapter_to_pwrctl(padapter);
-+	pslv = PS_STATE_S0;
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)
-+	    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {
-+		u8 val8;
-+
-+		val8 = rtw_btcoex_LpsVal(padapter);
-+		if (val8 & BIT(4))
-+			pslv = PS_STATE_S2;
-+
-+	}
-+#endif /* CONFIG_BT_COEXIST */
-+
-+#ifdef CONFIG_P2P_PS
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if ((iface) && rtw_is_adapter_up(iface)) {
-+			if (iface->wdinfo.p2p_ps_mode > P2P_PS_NONE) {
-+				pslv = PS_STATE_S2;
-+				break;
-+			}
-+		}
-+	}
-+#endif
-+	_enter_pwrlock(&pwrctrl->lock);
-+
-+	unregister_task_alive(pwrctrl, XMIT_ALIVE);
-+
-+	if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)
-+	    && (pwrctrl->bFwCurrentInPSMode == _TRUE)) {
-+
-+		if (pwrctrl->cpwm > pslv) {
-+			if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))
-+				rtw_set_rpwm(padapter, pslv);
-+		}
-+	}
-+
-+	_exit_pwrlock(&pwrctrl->lock);
-+
-+}
-+
-+/*
-+ * Caller: ISR
-+ *
-+ * If all commands have been done,
-+ * and no more command to do,
-+ * then driver shall call this fun. to power down firmware again.
-+ */
-+void rtw_unregister_cmd_alive(PADAPTER padapter)
-+{
-+	_adapter *iface;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pwrctrl_priv *pwrctrl;
-+	u8 pslv, i;
-+
-+
-+	pwrctrl = adapter_to_pwrctl(padapter);
-+	pslv = PS_STATE_S0;
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE)
-+	    && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) {
-+		u8 val8;
-+
-+		val8 = rtw_btcoex_LpsVal(padapter);
-+		if (val8 & BIT(4))
-+			pslv = PS_STATE_S2;
-+
-+	}
-+#endif /* CONFIG_BT_COEXIST */
-+
-+#ifdef CONFIG_P2P_PS
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if ((iface) && rtw_is_adapter_up(iface)) {
-+			if (iface->wdinfo.p2p_ps_mode > P2P_PS_NONE) {
-+				pslv = PS_STATE_S2;
-+				break;
-+			}
-+		}
-+	}
-+#endif
-+
-+	_enter_pwrlock(&pwrctrl->lock);
-+
-+	unregister_task_alive(pwrctrl, CMD_ALIVE);
-+
-+	if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)
-+	    && (pwrctrl->bFwCurrentInPSMode == _TRUE)) {
-+
-+		if (pwrctrl->cpwm > pslv) {
-+			if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))
-+				rtw_set_rpwm(padapter, pslv);
-+		}
-+	}
-+
-+	_exit_pwrlock(&pwrctrl->lock);
-+
-+}
-+
-+/*
-+ * Caller: ISR
-+ */
-+void rtw_unregister_rx_alive(PADAPTER padapter)
-+{
-+	struct pwrctrl_priv *pwrctrl;
-+
-+
-+	pwrctrl = adapter_to_pwrctl(padapter);
-+
-+	_enter_pwrlock(&pwrctrl->lock);
-+
-+	unregister_task_alive(pwrctrl, RECV_ALIVE);
-+
-+
-+	_exit_pwrlock(&pwrctrl->lock);
-+
-+}
-+
-+void rtw_unregister_evt_alive(PADAPTER padapter)
-+{
-+	struct pwrctrl_priv *pwrctrl;
-+
-+
-+	pwrctrl = adapter_to_pwrctl(padapter);
-+
-+	unregister_task_alive(pwrctrl, EVT_ALIVE);
-+
-+
-+	_exit_pwrlock(&pwrctrl->lock);
-+
-+}
-+#endif	/* CONFIG_LPS_LCLK */
-+
-+#ifdef CONFIG_RESUME_IN_WORKQUEUE
-+	static void resume_workitem_callback(struct work_struct *work);
-+#endif /* CONFIG_RESUME_IN_WORKQUEUE */
-+
-+void rtw_init_pwrctrl_priv(PADAPTER padapter)
-+{
-+#ifdef CONFIG_LPS_1T1R
-+#define LPS_1T1R_FMT ", LPS_1T1R=%d"
-+#define LPS_1T1R_ARG , pwrctrlpriv->lps_1t1r
-+#else
-+#define LPS_1T1R_FMT ""
-+#define LPS_1T1R_ARG
-+#endif
-+
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+#ifdef CONFIG_WOWLAN
-+	struct registry_priv  *registry_par = &padapter->registrypriv;
-+#endif
-+#ifdef CONFIG_GPIO_WAKEUP
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+#endif
-+
-+#if defined(CONFIG_CONCURRENT_MODE)
-+	if (!is_primary_adapter(padapter))
-+		return;
-+#endif
-+
-+	_init_pwrlock(&pwrctrlpriv->lock);
-+	_init_pwrlock(&pwrctrlpriv->check_32k_lock);
-+	pwrctrlpriv->rf_pwrstate = rf_on;
-+	pwrctrlpriv->ips_enter_cnts = 0;
-+	pwrctrlpriv->ips_leave_cnts = 0;
-+	pwrctrlpriv->lps_enter_cnts = 0;
-+	pwrctrlpriv->lps_leave_cnts = 0;
-+	pwrctrlpriv->bips_processing = _FALSE;
-+#ifdef CONFIG_LPS_CHK_BY_TP
-+	pwrctrlpriv->lps_chk_by_tp = padapter->registrypriv.lps_chk_by_tp;
-+	pwrctrlpriv->lps_tx_tp_th = LPS_TX_TP_TH;
-+	pwrctrlpriv->lps_rx_tp_th = LPS_RX_TP_TH;
-+	pwrctrlpriv->lps_bi_tp_th = LPS_BI_TP_TH;
-+	pwrctrlpriv->lps_chk_cnt = pwrctrlpriv->lps_chk_cnt_th = LPS_TP_CHK_CNT;
-+	pwrctrlpriv->lps_tx_pkts = LPS_CHK_PKTS_TX;
-+	pwrctrlpriv->lps_rx_pkts = LPS_CHK_PKTS_RX;
-+#endif
-+
-+	pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode;
-+	pwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode;
-+	pwrctrlpriv->ips_deny_time = rtw_get_current_time();
-+	pwrctrlpriv->lps_level = padapter->registrypriv.lps_level;
-+#ifdef CONFIG_LPS_1T1R
-+	pwrctrlpriv->lps_1t1r = padapter->registrypriv.lps_1t1r;
-+#endif
-+
-+	pwrctrlpriv->pwr_state_check_interval = RTW_PWR_STATE_CHK_INTERVAL;
-+	pwrctrlpriv->pwr_state_check_cnts = 0;
-+	pwrctrlpriv->bInSuspend = _FALSE;
-+	pwrctrlpriv->bkeepfwalive = _FALSE;
-+	pwrctrlpriv->LpsIdleCount = 0;
-+
-+	/* pwrctrlpriv->FWCtrlPSMode =padapter->registrypriv.power_mgnt; */ /* PS_MODE_MIN; */
-+	if (padapter->registrypriv.mp_mode == 1)
-+		pwrctrlpriv->power_mgnt = PS_MODE_ACTIVE ;
-+	else
-+		pwrctrlpriv->power_mgnt = padapter->registrypriv.power_mgnt; /* PS_MODE_MIN; */
-+	pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt) ? _TRUE : _FALSE;
-+
-+	pwrctrlpriv->bFwCurrentInPSMode = _FALSE;
-+	pwrctrlpriv->lps_deny_time = rtw_get_current_time();
-+
-+	pwrctrlpriv->rpwm = 0;
-+	pwrctrlpriv->cpwm = PS_STATE_S4;
-+
-+	pwrctrlpriv->pwr_mode = PS_MODE_ACTIVE;
-+	pwrctrlpriv->smart_ps = padapter->registrypriv.smart_ps;
-+	pwrctrlpriv->bcn_ant_mode = 0;
-+	pwrctrlpriv->dtim = 0;
-+
-+	pwrctrlpriv->tog = 0x80;
-+	pwrctrlpriv->rpwm_retry = 0;
-+
-+	RTW_INFO("%s: IPS_mode=%d, LPS_mode=%d, LPS_level=%d"LPS_1T1R_FMT"\n", 
-+		__func__, pwrctrlpriv->ips_mode, pwrctrlpriv->power_mgnt, pwrctrlpriv->lps_level
-+		LPS_1T1R_ARG
-+	);
-+
-+#ifdef CONFIG_LPS_LCLK
-+	rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&pwrctrlpriv->rpwm));
-+
-+	_init_workitem(&pwrctrlpriv->cpwm_event, cpwm_event_callback, NULL);
-+
-+	_init_workitem(&pwrctrlpriv->dma_event, dma_event_callback, NULL);
-+
-+#ifdef CONFIG_LPS_RPWM_TIMER
-+	pwrctrlpriv->brpwmtimeout = _FALSE;
-+	_init_workitem(&pwrctrlpriv->rpwmtimeoutwi, rpwmtimeout_workitem_callback, NULL);
-+	rtw_init_timer(&pwrctrlpriv->pwr_rpwm_timer, padapter, pwr_rpwm_timeout_handler, padapter);
-+#endif /* CONFIG_LPS_RPWM_TIMER */
-+#endif /* CONFIG_LPS_LCLK */
-+
-+#ifdef CONFIG_LPS_PG
-+	pwrctrlpriv->lpspg_info.name = "LPSPG_INFO";
-+	#ifdef CONFIG_RTL8822C
-+	pwrctrlpriv->lpspg_dpk_info.name = "LPSPG_DPK_INFO";
-+	pwrctrlpriv->lpspg_iqk_info.name = "LPSPG_IQK_INFO";
-+	#endif
-+#endif
-+
-+	rtw_init_timer(&pwrctrlpriv->pwr_state_check_timer, padapter, pwr_state_check_handler, padapter);
-+
-+	pwrctrlpriv->wowlan_mode = _FALSE;
-+	pwrctrlpriv->wowlan_ap_mode = _FALSE;
-+	pwrctrlpriv->wowlan_p2p_mode = _FALSE;
-+	pwrctrlpriv->wowlan_in_resume = _FALSE;
-+	pwrctrlpriv->wowlan_last_wake_reason = 0;
-+
-+#ifdef CONFIG_RESUME_IN_WORKQUEUE
-+	_init_workitem(&pwrctrlpriv->resume_work, resume_workitem_callback, NULL);
-+	pwrctrlpriv->rtw_workqueue = create_singlethread_workqueue("rtw_workqueue");
-+#endif /* CONFIG_RESUME_IN_WORKQUEUE */
-+
-+#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
-+	pwrctrlpriv->early_suspend.suspend = NULL;
-+	rtw_register_early_suspend(pwrctrlpriv);
-+#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+	pwrctrlpriv->wowlan_gpio_index = WAKEUP_GPIO_IDX;
-+	/* set output low state in initial */
-+	pwrctrlpriv->wowlan_gpio_output_state = GPIO_OUTPUT_LOW;
-+	/*default low active*/
-+	pwrctrlpriv->is_high_active = HIGH_ACTIVE_DEV2HST;
-+	pwrctrlpriv->hst2dev_high_active = HIGH_ACTIVE_HST2DEV;
-+
-+#if (defined(CONFIG_RTL8192F) && defined(CONFIG_USB_HCI) && defined(CONFIG_BT_COEXIST))
-+	if (pHalData->EEPROMBluetoothCoexist == _TRUE) {
-+		/* for 8725AU case */
-+		pwrctrlpriv->wowlan_gpio_index = WAKEUP_GPIO_IDX_8725AU;
-+		pwrctrlpriv->is_high_active = HIGH_ACTIVE_DEV2HST_8725AU;
-+	}
-+#endif
-+#ifdef CONFIG_RTW_ONE_PIN_GPIO
-+	rtw_hal_switch_gpio_wl_ctrl(padapter, pwrctrlpriv->wowlan_gpio_index, _TRUE);
-+	rtw_hal_set_input_gpio(padapter, pwrctrlpriv->wowlan_gpio_index);
-+#else
-+	#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
-+	if (pwrctrlpriv->is_high_active == 0)
-+		rtw_hal_set_input_gpio(padapter, pwrctrlpriv->wowlan_gpio_index);
-+	else
-+		rtw_hal_set_output_gpio(padapter, pwrctrlpriv->wowlan_gpio_index,
-+			GPIO_OUTPUT_LOW);
-+	#else
-+	rtw_hal_set_output_gpio(padapter, pwrctrlpriv->wowlan_gpio_index
-+		, pwrctrlpriv->wowlan_gpio_output_state);
-+	rtw_hal_switch_gpio_wl_ctrl(padapter, pwrctrlpriv->wowlan_gpio_index, _TRUE);
-+	RTW_INFO("%s: set GPIO_%d to OUTPUT %s state in initial and %s_ACTIVE.\n",
-+		 __func__, pwrctrlpriv->wowlan_gpio_index, 
-+		 pwrctrlpriv->wowlan_gpio_output_state ? "HIGH" : "LOW",
-+		 pwrctrlpriv->is_high_active ? "HIGI" : "LOW");
-+	#endif /*CONFIG_WAKEUP_GPIO_INPUT_MODE*/
-+#endif /* CONFIG_RTW_ONE_PIN_GPIO */
-+#endif /* CONFIG_GPIO_WAKEUP */
-+
-+#ifdef CONFIG_WOWLAN
-+#ifdef CONFIG_LPS_1T1R
-+#define WOW_LPS_1T1R_FMT ", WOW_LPS_1T1R=%d"
-+#define WOW_LPS_1T1R_ARG , pwrctrlpriv->wowlan_lps_1t1r
-+#else
-+#define WOW_LPS_1T1R_FMT ""
-+#define WOW_LPS_1T1R_ARG
-+#endif
-+
-+	pwrctrlpriv->wowlan_power_mgmt = padapter->registrypriv.wow_power_mgnt;
-+	pwrctrlpriv->wowlan_lps_level = padapter->registrypriv.wow_lps_level;
-+#ifdef CONFIG_LPS_1T1R
-+	pwrctrlpriv->wowlan_lps_1t1r = padapter->registrypriv.wow_lps_1t1r;
-+#endif
-+
-+	RTW_INFO("%s: WOW_LPS_mode=%d, WOW_LPS_level=%d"WOW_LPS_1T1R_FMT"\n",
-+		__func__, pwrctrlpriv->wowlan_power_mgmt, pwrctrlpriv->wowlan_lps_level
-+		WOW_LPS_1T1R_ARG
-+	);
-+
-+	if (registry_par->wakeup_event & BIT(1))
-+		pwrctrlpriv->default_patterns_en = _TRUE;
-+	else
-+		pwrctrlpriv->default_patterns_en = _FALSE;
-+
-+	rtw_wow_pattern_sw_reset(padapter);
-+#ifdef CONFIG_PNO_SUPPORT
-+	pwrctrlpriv->pno_inited = _FALSE;
-+	pwrctrlpriv->pnlo_info = NULL;
-+	pwrctrlpriv->pscan_info = NULL;
-+	pwrctrlpriv->pno_ssid_list = NULL;
-+#endif /* CONFIG_PNO_SUPPORT */
-+#ifdef CONFIG_WOW_PATTERN_HW_CAM
-+	_rtw_mutex_init(&pwrctrlpriv->wowlan_pattern_cam_mutex);
-+#endif
-+
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+	pwrctrlpriv->wowlan_keep_alive_ack_index = 0xFF;
-+	pwrctrlpriv->wowlan_wake_pattern_index = 0xFF;
-+#endif/*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+	pwrctrlpriv->wowlan_aoac_rpt_loc = 0;
-+#ifdef CONFIG_WAR_OFFLOAD
-+#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
-+	rtw_wow_war_mdns_parms_reset(padapter, _TRUE);
-+#endif /* defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) */
-+#endif /* CONFIG_WAR_OFFLOAD */
-+#endif /* CONFIG_WOWLAN */
-+
-+#ifdef CONFIG_LPS_POFF
-+	rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_INIT, 0);
-+#endif
-+
-+#ifdef CONFIG_LPS_ACK
-+	_rtw_mutex_init(&pwrctrlpriv->lps_ack_mutex);
-+	pwrctrlpriv->lps_ack_status = -1;
-+#endif /* CONFIG_LPS_ACK */
-+}
-+
-+
-+void rtw_free_pwrctrl_priv(PADAPTER adapter)
-+{
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter);
-+
-+#if defined(CONFIG_CONCURRENT_MODE)
-+	if (!is_primary_adapter(adapter))
-+		return;
-+#endif
-+
-+
-+	/* _rtw_memset((unsigned char *)pwrctrlpriv, 0, sizeof(struct pwrctrl_priv)); */
-+
-+
-+#ifdef CONFIG_RESUME_IN_WORKQUEUE
-+	if (pwrctrlpriv->rtw_workqueue) {
-+		flush_workqueue(pwrctrlpriv->rtw_workqueue);
-+		destroy_workqueue(pwrctrlpriv->rtw_workqueue);
-+	}
-+#endif
-+
-+#ifdef CONFIG_LPS_POFF
-+	rtw_hal_set_hwreg(adapter, HW_VAR_LPS_POFF_DEINIT, 0);
-+#endif
-+
-+#ifdef CONFIG_LPS_LCLK
-+	_cancel_workitem_sync(&pwrctrlpriv->cpwm_event);
-+	_cancel_workitem_sync(&pwrctrlpriv->dma_event);
-+	#ifdef CONFIG_LPS_RPWM_TIMER
-+	_cancel_workitem_sync(&pwrctrlpriv->rpwmtimeoutwi);
-+	#endif
-+#endif /* CONFIG_LPS_LCLK */
-+
-+#ifdef CONFIG_LPS_PG
-+	rsvd_page_cache_free(&pwrctrlpriv->lpspg_info);
-+	#ifdef CONFIG_RTL8822C
-+	rsvd_page_cache_free(&pwrctrlpriv->lpspg_dpk_info);
-+	rsvd_page_cache_free(&pwrctrlpriv->lpspg_iqk_info);
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_WOWLAN
-+#ifdef CONFIG_PNO_SUPPORT
-+	if (pwrctrlpriv->pnlo_info != NULL)
-+		printk("****** pnlo_info memory leak********\n");
-+
-+	if (pwrctrlpriv->pscan_info != NULL)
-+		printk("****** pscan_info memory leak********\n");
-+
-+	if (pwrctrlpriv->pno_ssid_list != NULL)
-+		printk("****** pno_ssid_list memory leak********\n");
-+#endif
-+#ifdef CONFIG_WOW_PATTERN_HW_CAM
-+	_rtw_mutex_free(&pwrctrlpriv->wowlan_pattern_cam_mutex);
-+#endif
-+
-+#endif /* CONFIG_WOWLAN */
-+
-+#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
-+	rtw_unregister_early_suspend(pwrctrlpriv);
-+#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
-+
-+	_free_pwrlock(&pwrctrlpriv->lock);
-+	_free_pwrlock(&pwrctrlpriv->check_32k_lock);
-+
-+#ifdef CONFIG_LPS_ACK
-+	_rtw_mutex_free(&pwrctrlpriv->lps_ack_mutex);
-+#endif /* CONFIG_LPS_ACK */
-+}
-+
-+#ifdef CONFIG_RESUME_IN_WORKQUEUE
-+extern int rtw_resume_process(_adapter *padapter);
-+
-+static void resume_workitem_callback(struct work_struct *work)
-+{
-+	struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, resume_work);
-+	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
-+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
-+        PSDIO_DATA psdio = &dvobj->intf_data;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	rtw_resume_process(adapter);
-+
-+	pm_relax(&psdio->func->dev);
-+}
-+
-+void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv)
-+{
-+	/* accquire system's suspend lock preventing from falliing asleep while resume in workqueue */
-+	/* rtw_lock_suspend(); */
-+	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
-+        PSDIO_DATA psdio = &dvobj->intf_data;
-+
-+	pm_stay_awake(&psdio->func->dev);
-+
-+#if 1
-+	queue_work(pwrpriv->rtw_workqueue, &pwrpriv->resume_work);
-+#else
-+	_set_workitem(&pwrpriv->resume_work);
-+#endif
-+}
-+#endif /* CONFIG_RESUME_IN_WORKQUEUE */
-+
-+#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
-+inline bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv)
-+{
-+	return (pwrpriv->early_suspend.suspend) ? _TRUE : _FALSE;
-+}
-+
-+inline bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv)
-+{
-+	return (pwrpriv->do_late_resume) ? _TRUE : _FALSE;
-+}
-+
-+inline void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable)
-+{
-+	pwrpriv->do_late_resume = enable;
-+}
-+#endif
-+
-+#ifdef CONFIG_HAS_EARLYSUSPEND
-+extern int rtw_resume_process(_adapter *padapter);
-+static void rtw_early_suspend(struct early_suspend *h)
-+{
-+	struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	rtw_set_do_late_resume(pwrpriv, _FALSE);
-+}
-+
-+static void rtw_late_resume(struct early_suspend *h)
-+{
-+	struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
-+	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
-+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	if (pwrpriv->do_late_resume) {
-+		rtw_set_do_late_resume(pwrpriv, _FALSE);
-+		rtw_resume_process(adapter);
-+	}
-+}
-+
-+void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv)
-+{
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	/* jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit */
-+	pwrpriv->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20;
-+	pwrpriv->early_suspend.suspend = rtw_early_suspend;
-+	pwrpriv->early_suspend.resume = rtw_late_resume;
-+	register_early_suspend(&pwrpriv->early_suspend);
-+
-+
-+}
-+
-+void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv)
-+{
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	rtw_set_do_late_resume(pwrpriv, _FALSE);
-+
-+	if (pwrpriv->early_suspend.suspend)
-+		unregister_early_suspend(&pwrpriv->early_suspend);
-+
-+	pwrpriv->early_suspend.suspend = NULL;
-+	pwrpriv->early_suspend.resume = NULL;
-+}
-+#endif /* CONFIG_HAS_EARLYSUSPEND */
-+
-+#ifdef CONFIG_ANDROID_POWER
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	extern int rtw_resume_process(PADAPTER padapter);
-+#endif
-+static void rtw_early_suspend(android_early_suspend_t *h)
-+{
-+	struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	rtw_set_do_late_resume(pwrpriv, _FALSE);
-+}
-+
-+static void rtw_late_resume(android_early_suspend_t *h)
-+{
-+	struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
-+	struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
-+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+	if (pwrpriv->do_late_resume) {
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+		rtw_set_do_late_resume(pwrpriv, _FALSE);
-+		rtw_resume_process(adapter);
-+#endif
-+	}
-+}
-+
-+void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv)
-+{
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	/* jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit */
-+	pwrpriv->early_suspend.level = ANDROID_EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20;
-+	pwrpriv->early_suspend.suspend = rtw_early_suspend;
-+	pwrpriv->early_suspend.resume = rtw_late_resume;
-+	android_register_early_suspend(&pwrpriv->early_suspend);
-+}
-+
-+void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv)
-+{
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	rtw_set_do_late_resume(pwrpriv, _FALSE);
-+
-+	if (pwrpriv->early_suspend.suspend)
-+		android_unregister_early_suspend(&pwrpriv->early_suspend);
-+
-+	pwrpriv->early_suspend.suspend = NULL;
-+	pwrpriv->early_suspend.resume = NULL;
-+}
-+#endif /* CONFIG_ANDROID_POWER */
-+
-+u8 rtw_interface_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)
-+{
-+	u8 bResult = _TRUE;
-+	rtw_hal_intf_ps_func(padapter, efunc_id, val);
-+
-+	return bResult;
-+}
-+
-+
-+inline void rtw_set_ips_deny(_adapter *padapter, u32 ms)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ms);
-+}
-+
-+/*
-+* rtw_pwr_wakeup - Wake the NIC up from: 1)IPS. 2)USB autosuspend
-+* @adapter: pointer to _adapter structure
-+* @ips_deffer_ms: the ms wiil prevent from falling into IPS after wakeup
-+* Return _SUCCESS or _FAIL
-+*/
-+
-+int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+	struct mlme_priv *pmlmepriv;
-+	int ret = _SUCCESS;
-+	systime start = rtw_get_current_time();
-+
-+	/*RTW_INFO(FUNC_ADPT_FMT "===>\n", FUNC_ADPT_ARG(padapter));*/
-+	/* for LPS */
-+	LeaveAllPowerSaveMode(padapter);
-+
-+	/* IPS still bound with primary adapter */
-+	padapter = GET_PRIMARY_ADAPTER(padapter);
-+	pmlmepriv = &padapter->mlmepriv;
-+
-+	if (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time))
-+		pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms);
-+
-+
-+	if (pwrpriv->ps_processing) {
-+		RTW_INFO("%s wait ps_processing...\n", __func__);
-+		while (pwrpriv->ps_processing && rtw_get_passing_time_ms(start) <= 3000)
-+			rtw_msleep_os(10);
-+		if (pwrpriv->ps_processing)
-+			RTW_INFO("%s wait ps_processing timeout\n", __func__);
-+		else
-+			RTW_INFO("%s wait ps_processing done\n", __func__);
-+	}
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	if (rtw_hal_sreset_inprogress(padapter)) {
-+		RTW_INFO("%s wait sreset_inprogress...\n", __func__);
-+		while (rtw_hal_sreset_inprogress(padapter) && rtw_get_passing_time_ms(start) <= 4000)
-+			rtw_msleep_os(10);
-+		if (rtw_hal_sreset_inprogress(padapter))
-+			RTW_INFO("%s wait sreset_inprogress timeout\n", __func__);
-+		else
-+			RTW_INFO("%s wait sreset_inprogress done\n", __func__);
-+	}
-+#endif
-+
-+	if (pwrpriv->bInSuspend) {
-+		RTW_INFO("%s wait bInSuspend...\n", __func__);
-+		while (pwrpriv->bInSuspend
-+		       && ((rtw_get_passing_time_ms(start) <= 3000 && !rtw_is_do_late_resume(pwrpriv))
-+			|| (rtw_get_passing_time_ms(start) <= 500 && rtw_is_do_late_resume(pwrpriv)))
-+		      )
-+			rtw_msleep_os(10);
-+		if (pwrpriv->bInSuspend)
-+			RTW_INFO("%s wait bInSuspend timeout\n", __func__);
-+		else
-+			RTW_INFO("%s wait bInSuspend done\n", __func__);
-+	}
-+
-+	/* System suspend is not allowed to wakeup */
-+	if (_TRUE == pwrpriv->bInSuspend) {
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+	/* I think this should be check in IPS, LPS, autosuspend functions... */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+		ret = _SUCCESS;
-+		goto exit;
-+	}
-+
-+	if (rf_off == pwrpriv->rf_pwrstate) {
-+		
-+#ifdef CONFIG_IPS
-+		RTW_INFO("%s call ips_leave....\n", __FUNCTION__);
-+		if (_FAIL ==  ips_leave(padapter)) {
-+			RTW_INFO("======> ips_leave fail.............\n");
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+#endif
-+		
-+	}
-+
-+	/* TODO: the following checking need to be merged... */
-+	if (rtw_is_drv_stopped(padapter)
-+	    || !padapter->bup
-+	    || !rtw_is_hw_init_completed(padapter)
-+	   ) {
-+		RTW_INFO("%s: bDriverStopped=%s, bup=%d, hw_init_completed=%u\n"
-+			 , caller
-+			 , rtw_is_drv_stopped(padapter) ? "True" : "False"
-+			 , padapter->bup
-+			 , rtw_get_hw_init_completed(padapter));
-+		ret = _FALSE;
-+		goto exit;
-+	}
-+
-+exit:
-+	if (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time))
-+		pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms);
-+	/*RTW_INFO(FUNC_ADPT_FMT "<===\n", FUNC_ADPT_ARG(padapter));*/
-+	return ret;
-+
-+}
-+
-+int rtw_pm_set_lps(_adapter *padapter, u8 mode)
-+{
-+	int	ret = 0;
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+
-+	if (mode < PS_MODE_NUM) {
-+		if (pwrctrlpriv->power_mgnt != mode) {
-+			if (PS_MODE_ACTIVE == mode)
-+				LeaveAllPowerSaveMode(padapter);
-+			else
-+				pwrctrlpriv->LpsIdleCount = 2;
-+			pwrctrlpriv->power_mgnt = mode;
-+			pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt) ? _TRUE : _FALSE;
-+		}
-+	} else
-+		ret = -EINVAL;
-+
-+	return ret;
-+}
-+
-+int rtw_pm_set_lps_level(_adapter *padapter, u8 level)
-+{
-+	int	ret = 0;
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+
-+	if (level < LPS_LEVEL_MAX) {
-+		if (pwrctrlpriv->lps_level != level) {
-+			#ifdef CONFIG_LPS
-+			if (rtw_lps_ctrl_leave_set_level_cmd(padapter, level, RTW_CMDF_WAIT_ACK) != _SUCCESS)
-+			#endif
-+				pwrctrlpriv->lps_level = level;
-+		}
-+	} else
-+		ret = -EINVAL;
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_LPS_1T1R
-+int rtw_pm_set_lps_1t1r(_adapter *padapter, u8 en)
-+{
-+	int	ret = 0;
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+
-+	en = en ? 1 : 0;
-+	if (pwrctrlpriv->lps_1t1r != en) {
-+		if (rtw_lps_ctrl_leave_set_1t1r_cmd(padapter, en, RTW_CMDF_WAIT_ACK) != _SUCCESS)
-+			pwrctrlpriv->lps_1t1r = en;
-+	}
-+
-+	return ret;
-+}
-+#endif
-+
-+inline void rtw_set_lps_deny(_adapter *adapter, u32 ms)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	pwrpriv->lps_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ms);
-+}
-+
-+#ifdef CONFIG_WOWLAN
-+int rtw_pm_set_wow_lps(_adapter *padapter, u8 mode)
-+{
-+	int	ret = 0;
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+
-+	if (mode < PS_MODE_NUM) {
-+		if (pwrctrlpriv->wowlan_power_mgmt != mode) 
-+			pwrctrlpriv->wowlan_power_mgmt = mode;
-+	} else
-+		ret = -EINVAL;
-+
-+	return ret;
-+}
-+int rtw_pm_set_wow_lps_level(_adapter *padapter, u8 level)
-+{
-+	int	ret = 0;
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+
-+	if (level < LPS_LEVEL_MAX)
-+		pwrctrlpriv->wowlan_lps_level = level;
-+	else
-+		ret = -EINVAL;
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_LPS_1T1R
-+int rtw_pm_set_wow_lps_1t1r(_adapter *padapter, u8 en)
-+{
-+	int	ret = 0;
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+
-+	en = en ? 1 : 0;
-+	pwrctrlpriv->wowlan_lps_1t1r = en;
-+
-+	return ret;
-+}
-+#endif /* CONFIG_LPS_1T1R */
-+#endif /* CONFIG_WOWLAN */
-+
-+int rtw_pm_set_ips(_adapter *padapter, u8 mode)
-+{
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+
-+	if (mode == IPS_NORMAL || mode == IPS_LEVEL_2) {
-+		rtw_ips_mode_req(pwrctrlpriv, mode);
-+		RTW_INFO("%s %s\n", __FUNCTION__, mode == IPS_NORMAL ? "IPS_NORMAL" : "IPS_LEVEL_2");
-+		return 0;
-+	} else if (mode == IPS_NONE) {
-+		rtw_ips_mode_req(pwrctrlpriv, mode);
-+		RTW_INFO("%s %s\n", __FUNCTION__, "IPS_NONE");
-+		if (!rtw_is_surprise_removed(padapter) && (_FAIL == rtw_pwr_wakeup(padapter)))
-+			return -EFAULT;
-+	} else
-+		return -EINVAL;
-+	return 0;
-+}
-+
-+/*
-+ * ATTENTION:
-+ *	This function will request pwrctrl LOCK!
-+ */
-+void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason)
-+{
-+	struct pwrctrl_priv *pwrpriv;
-+
-+	/* 	RTW_INFO("+" FUNC_ADPT_FMT ": Request PS deny for %d (0x%08X)\n",
-+	 *		FUNC_ADPT_ARG(padapter), reason, BIT(reason)); */
-+
-+	pwrpriv = adapter_to_pwrctl(padapter);
-+
-+	_enter_pwrlock(&pwrpriv->lock);
-+	if (pwrpriv->ps_deny & BIT(reason)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": [WARNING] Reason %d had been set before!!\n",
-+			 FUNC_ADPT_ARG(padapter), reason);
-+	}
-+	pwrpriv->ps_deny |= BIT(reason);
-+	_exit_pwrlock(&pwrpriv->lock);
-+
-+	/* 	RTW_INFO("-" FUNC_ADPT_FMT ": Now PS deny for 0x%08X\n",
-+	 *		FUNC_ADPT_ARG(padapter), pwrpriv->ps_deny); */
-+}
-+
-+/*
-+ * ATTENTION:
-+ *	This function will request pwrctrl LOCK!
-+ */
-+void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason)
-+{
-+	struct pwrctrl_priv *pwrpriv;
-+
-+
-+	/* 	RTW_INFO("+" FUNC_ADPT_FMT ": Cancel PS deny for %d(0x%08X)\n",
-+	 *		FUNC_ADPT_ARG(padapter), reason, BIT(reason)); */
-+
-+	pwrpriv = adapter_to_pwrctl(padapter);
-+
-+	_enter_pwrlock(&pwrpriv->lock);
-+	if ((pwrpriv->ps_deny & BIT(reason)) == 0) {
-+		RTW_INFO(FUNC_ADPT_FMT ": [ERROR] Reason %d had been canceled before!!\n",
-+			 FUNC_ADPT_ARG(padapter), reason);
-+	}
-+	pwrpriv->ps_deny &= ~BIT(reason);
-+	_exit_pwrlock(&pwrpriv->lock);
-+
-+	/* 	RTW_INFO("-" FUNC_ADPT_FMT ": Now PS deny for 0x%08X\n",
-+	 *		FUNC_ADPT_ARG(padapter), pwrpriv->ps_deny); */
-+}
-+
-+/*
-+ * ATTENTION:
-+ *	Before calling this function pwrctrl lock should be occupied already,
-+ *	otherwise it may return incorrect value.
-+ */
-+u32 rtw_ps_deny_get(PADAPTER padapter)
-+{
-+	u32 deny;
-+
-+
-+	deny = adapter_to_pwrctl(padapter)->ps_deny;
-+
-+	return deny;
-+}
-+
-+static void _rtw_ssmps(_adapter *adapter, struct sta_info *sta)
-+{
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if (MLME_IS_STA(adapter)) {
-+		issue_action_SM_PS_wait_ack(adapter , get_my_bssid(&(pmlmeinfo->network)),
-+			sta->cmn.sm_ps, 3 , 1);
-+	}
-+	else if (MLME_IS_AP(adapter)) {
-+
-+	}
-+	rtw_phydm_ra_registed(adapter, sta);
-+}
-+void rtw_ssmps_enter(_adapter *adapter, struct sta_info *sta)
-+{
-+	if (sta->cmn.sm_ps == SM_PS_STATIC)
-+		return;
-+
-+	RTW_INFO(ADPT_FMT" STA [" MAC_FMT "]\n", ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
-+
-+	sta->cmn.sm_ps = SM_PS_STATIC;
-+	_rtw_ssmps(adapter, sta);
-+}
-+void rtw_ssmps_leave(_adapter *adapter, struct sta_info *sta)
-+{
-+	if (sta->cmn.sm_ps == SM_PS_DISABLE)
-+		return;
-+
-+	RTW_INFO(ADPT_FMT" STA [" MAC_FMT "] \n", ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
-+	sta->cmn.sm_ps = SM_PS_DISABLE;
-+	_rtw_ssmps(adapter, sta);
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/core/rtw_recv.c b/drivers/staging/rtl8723cs/core/rtw_recv.c
-new file mode 100644
-index 000000000000..fa416896e0c6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_recv.c
-@@ -0,0 +1,4763 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_RECV_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+static void rtw_signal_stat_timer_hdl(void *ctx);
-+
-+enum {
-+	SIGNAL_STAT_CALC_PROFILE_0 = 0,
-+	SIGNAL_STAT_CALC_PROFILE_1,
-+	SIGNAL_STAT_CALC_PROFILE_2,
-+	SIGNAL_STAT_CALC_PROFILE_MAX
-+};
-+
-+u8 signal_stat_calc_profile[SIGNAL_STAT_CALC_PROFILE_MAX][3] = {
-+	{4, 1},	/* Profile 0 => pre_stat : curr_stat = 4 : 1 */
-+	{3, 7},	/* Profile 1 => pre_stat : curr_stat = 3 : 7 */
-+	{0, 10}	/* Profile 2 => pre_stat : curr_stat = 0 : 10 */
-+};
-+
-+#ifndef RTW_SIGNAL_STATE_CALC_PROFILE
-+	#define RTW_SIGNAL_STATE_CALC_PROFILE SIGNAL_STAT_CALC_PROFILE_1
-+#endif
-+
-+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+
-+u8 rtw_bridge_tunnel_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 };
-+u8 rtw_rfc1042_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };
-+static u8 SNAP_ETH_TYPE_IPX[2] = {0x81, 0x37};
-+static u8 SNAP_ETH_TYPE_APPLETALK_AARP[2] = {0x80, 0xf3};
-+#ifdef CONFIG_TDLS
-+static u8 SNAP_ETH_TYPE_TDLS[2] = {0x89, 0x0d};
-+#endif
-+
-+void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv)
-+{
-+
-+
-+
-+	_rtw_memset((u8 *)psta_recvpriv, 0, sizeof(struct sta_recv_priv));
-+
-+	_rtw_spinlock_init(&psta_recvpriv->lock);
-+
-+	/* for(i=0; i<MAX_RX_NUMBLKS; i++) */
-+	/*	_rtw_init_queue(&psta_recvpriv->blk_strms[i]); */
-+
-+	_rtw_init_queue(&psta_recvpriv->defrag_q);
-+
-+
-+}
-+
-+sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter)
-+{
-+	sint i;
-+
-+	union recv_frame *precvframe;
-+	sint	res = _SUCCESS;
-+
-+
-+	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
-+	/* _rtw_memset((unsigned char *)precvpriv, 0, sizeof (struct  recv_priv)); */
-+
-+	_rtw_spinlock_init(&precvpriv->lock);
-+
-+#ifdef CONFIG_RECV_THREAD_MODE
-+	_rtw_init_sema(&precvpriv->recv_sema, 0);
-+
-+#endif
-+
-+	_rtw_init_queue(&precvpriv->free_recv_queue);
-+	_rtw_init_queue(&precvpriv->recv_pending_queue);
-+	_rtw_init_queue(&precvpriv->uc_swdec_pending_queue);
-+
-+	precvpriv->adapter = padapter;
-+
-+	precvpriv->free_recvframe_cnt = NR_RECVFRAME;
-+
-+	precvpriv->sink_udpport = 0;
-+	precvpriv->pre_rtp_rxseq = 0;
-+	precvpriv->cur_rtp_rxseq = 0;
-+
-+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
-+	precvpriv->store_law_data_flag = 1;
-+#else
-+	precvpriv->store_law_data_flag = 0;
-+#endif
-+
-+	rtw_os_recv_resource_init(precvpriv, padapter);
-+
-+	precvpriv->pallocated_frame_buf = rtw_zvmalloc(NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ);
-+
-+	if (precvpriv->pallocated_frame_buf == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	/* _rtw_memset(precvpriv->pallocated_frame_buf, 0, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); */
-+
-+	precvpriv->precv_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_frame_buf), RXFRAME_ALIGN_SZ);
-+	/* precvpriv->precv_frame_buf = precvpriv->pallocated_frame_buf + RXFRAME_ALIGN_SZ - */
-+	/*						((SIZE_PTR) (precvpriv->pallocated_frame_buf) &(RXFRAME_ALIGN_SZ-1)); */
-+
-+	precvframe = (union recv_frame *) precvpriv->precv_frame_buf;
-+
-+
-+	for (i = 0; i < NR_RECVFRAME ; i++) {
-+		_rtw_init_listhead(&(precvframe->u.list));
-+
-+		rtw_list_insert_tail(&(precvframe->u.list), &(precvpriv->free_recv_queue.queue));
-+
-+		rtw_os_recv_resource_alloc(padapter, precvframe);
-+
-+		precvframe->u.hdr.len = 0;
-+
-+		precvframe->u.hdr.adapter = padapter;
-+		precvframe++;
-+
-+	}
-+
-+#ifdef CONFIG_USB_HCI
-+
-+	ATOMIC_SET(&(precvpriv->rx_pending_cnt), 1);
-+
-+	_rtw_init_sema(&precvpriv->allrxreturnevt, 0);
-+
-+#endif
-+
-+	res = rtw_hal_init_recv_priv(padapter);
-+
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+	rtw_init_timer(&precvpriv->signal_stat_timer, padapter, rtw_signal_stat_timer_hdl, padapter);
-+
-+	precvpriv->signal_stat_sampling_interval = 2000; /* ms */
-+	/* precvpriv->signal_stat_converging_constant = 5000; */ /* ms */
-+
-+	rtw_set_signal_stat_timer(precvpriv);
-+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+
-+exit:
-+
-+
-+	return res;
-+
-+}
-+
-+void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv);
-+void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv)
-+{
-+	_rtw_spinlock_free(&precvpriv->lock);
-+#ifdef CONFIG_RECV_THREAD_MODE
-+	_rtw_free_sema(&precvpriv->recv_sema);
-+#endif
-+
-+	_rtw_spinlock_free(&precvpriv->free_recv_queue.lock);
-+	_rtw_spinlock_free(&precvpriv->recv_pending_queue.lock);
-+
-+	_rtw_spinlock_free(&precvpriv->free_recv_buf_queue.lock);
-+
-+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
-+	_rtw_spinlock_free(&precvpriv->recv_buf_pending_queue.lock);
-+#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
-+}
-+
-+void _rtw_free_recv_priv(struct recv_priv *precvpriv)
-+{
-+	_adapter	*padapter = precvpriv->adapter;
-+
-+
-+	rtw_free_uc_swdec_pending_queue(padapter);
-+
-+	rtw_mfree_recv_priv_lock(precvpriv);
-+
-+	rtw_os_recv_resource_free(precvpriv);
-+
-+	if (precvpriv->pallocated_frame_buf)
-+		rtw_vmfree(precvpriv->pallocated_frame_buf, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ);
-+
-+	rtw_hal_free_recv_priv(padapter);
-+
-+
-+}
-+
-+bool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset)
-+{
-+#define DBG_RFRAME_DEL_WFD_IE 0
-+	u8 *ies = rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + ies_offset;
-+	uint ies_len_ori = rframe->u.hdr.len - (ies - rframe->u.hdr.rx_data);
-+	uint ies_len;
-+
-+	ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_RFRAME_DEL_WFD_IE ? __func__ : NULL);
-+	rframe->u.hdr.len -= ies_len_ori - ies_len;
-+
-+	return ies_len_ori != ies_len;
-+}
-+
-+union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue)
-+{
-+
-+	union recv_frame  *precvframe;
-+	_list	*plist, *phead;
-+	_adapter *padapter;
-+	struct recv_priv *precvpriv;
-+
-+	if (_rtw_queue_empty(pfree_recv_queue) == _TRUE)
-+		precvframe = NULL;
-+	else {
-+		phead = get_list_head(pfree_recv_queue);
-+
-+		plist = get_next(phead);
-+
-+		precvframe = LIST_CONTAINOR(plist, union recv_frame, u);
-+
-+		rtw_list_delete(&precvframe->u.hdr.list);
-+		padapter = precvframe->u.hdr.adapter;
-+		if (padapter != NULL) {
-+			precvpriv = &padapter->recvpriv;
-+			if (pfree_recv_queue == &precvpriv->free_recv_queue)
-+				precvpriv->free_recvframe_cnt--;
-+		}
-+	}
-+
-+
-+	return precvframe;
-+
-+}
-+
-+union recv_frame *rtw_alloc_recvframe(_queue *pfree_recv_queue)
-+{
-+	_irqL irqL;
-+	union recv_frame  *precvframe;
-+
-+	_enter_critical_bh(&pfree_recv_queue->lock, &irqL);
-+
-+	precvframe = _rtw_alloc_recvframe(pfree_recv_queue);
-+
-+	_exit_critical_bh(&pfree_recv_queue->lock, &irqL);
-+
-+	return precvframe;
-+}
-+
-+void rtw_init_recvframe(union recv_frame *precvframe, struct recv_priv *precvpriv)
-+{
-+	/* Perry: This can be removed */
-+	_rtw_init_listhead(&precvframe->u.hdr.list);
-+
-+	precvframe->u.hdr.len = 0;
-+}
-+
-+int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue)
-+{
-+	_irqL irqL;
-+	_adapter *padapter = precvframe->u.hdr.adapter;
-+	struct recv_priv *precvpriv = &padapter->recvpriv;
-+
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	padapter = GET_PRIMARY_ADAPTER(padapter);
-+	precvpriv = &padapter->recvpriv;
-+	pfree_recv_queue = &precvpriv->free_recv_queue;
-+	precvframe->u.hdr.adapter = padapter;
-+#endif
-+
-+
-+	rtw_os_free_recvframe(precvframe);
-+
-+
-+	_enter_critical_bh(&pfree_recv_queue->lock, &irqL);
-+
-+	rtw_list_delete(&(precvframe->u.hdr.list));
-+
-+	precvframe->u.hdr.len = 0;
-+	precvframe->u.hdr.attrib.phy_info.physts_rpt_valid = _FALSE;
-+
-+	rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(pfree_recv_queue));
-+
-+	if (padapter != NULL) {
-+		if (pfree_recv_queue == &precvpriv->free_recv_queue)
-+			precvpriv->free_recvframe_cnt++;
-+	}
-+
-+	_exit_critical_bh(&pfree_recv_queue->lock, &irqL);
-+
-+
-+	return _SUCCESS;
-+
-+}
-+
-+
-+
-+
-+sint _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)
-+{
-+
-+	_adapter *padapter = precvframe->u.hdr.adapter;
-+	struct recv_priv *precvpriv = &padapter->recvpriv;
-+
-+
-+	/* _rtw_init_listhead(&(precvframe->u.hdr.list)); */
-+	rtw_list_delete(&(precvframe->u.hdr.list));
-+
-+
-+	rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(queue));
-+
-+	if (padapter != NULL) {
-+		if (queue == &precvpriv->free_recv_queue)
-+			precvpriv->free_recvframe_cnt++;
-+	}
-+
-+
-+	return _SUCCESS;
-+}
-+
-+sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)
-+{
-+	sint ret;
-+	_irqL irqL;
-+
-+	/* _spinlock(&pfree_recv_queue->lock); */
-+	_enter_critical_bh(&queue->lock, &irqL);
-+	ret = _rtw_enqueue_recvframe(precvframe, queue);
-+	/* _rtw_spinunlock(&pfree_recv_queue->lock); */
-+	_exit_critical_bh(&queue->lock, &irqL);
-+
-+	return ret;
-+}
-+
-+/*
-+sint	rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)
-+{
-+	return rtw_free_recvframe(precvframe, queue);
-+}
-+*/
-+
-+
-+
-+
-+/*
-+caller : defrag ; recvframe_chk_defrag in recv_thread  (passive)
-+pframequeue: defrag_queue : will be accessed in recv_thread  (passive)
-+
-+using spinlock to protect
-+
-+*/
-+
-+void rtw_free_recvframe_queue(_queue *pframequeue,  _queue *pfree_recv_queue)
-+{
-+	union	recv_frame	*precvframe;
-+	_list	*plist, *phead;
-+
-+	_rtw_spinlock(&pframequeue->lock);
-+
-+	phead = get_list_head(pframequeue);
-+	plist = get_next(phead);
-+
-+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+		precvframe = LIST_CONTAINOR(plist, union recv_frame, u);
-+
-+		plist = get_next(plist);
-+
-+		/* rtw_list_delete(&precvframe->u.hdr.list); */ /* will do this in rtw_free_recvframe() */
-+
-+		rtw_free_recvframe(precvframe, pfree_recv_queue);
-+	}
-+
-+	_rtw_spinunlock(&pframequeue->lock);
-+
-+
-+}
-+
-+u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter)
-+{
-+	u32 cnt = 0;
-+	union recv_frame *pending_frame;
-+	while ((pending_frame = rtw_alloc_recvframe(&adapter->recvpriv.uc_swdec_pending_queue))) {
-+		rtw_free_recvframe(pending_frame, &adapter->recvpriv.free_recv_queue);
-+		cnt++;
-+	}
-+
-+	if (cnt)
-+		RTW_INFO(FUNC_ADPT_FMT" dequeue %d\n", FUNC_ADPT_ARG(adapter), cnt);
-+
-+	return cnt;
-+}
-+
-+
-+sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue)
-+{
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+
-+	rtw_list_delete(&precvbuf->list);
-+	rtw_list_insert_head(&precvbuf->list, get_list_head(queue));
-+
-+	_exit_critical_bh(&queue->lock, &irqL);
-+
-+	return _SUCCESS;
-+}
-+
-+sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue)
-+{
-+	_irqL irqL;
-+#ifdef CONFIG_SDIO_HCI
-+	_enter_critical_bh(&queue->lock, &irqL);
-+#else
-+	_enter_critical_ex(&queue->lock, &irqL);
-+#endif/*#ifdef CONFIG_SDIO_HCI*/
-+
-+	rtw_list_delete(&precvbuf->list);
-+
-+	rtw_list_insert_tail(&precvbuf->list, get_list_head(queue));
-+#ifdef CONFIG_SDIO_HCI
-+	_exit_critical_bh(&queue->lock, &irqL);
-+#else
-+	_exit_critical_ex(&queue->lock, &irqL);
-+#endif/*#ifdef CONFIG_SDIO_HCI*/
-+	return _SUCCESS;
-+
-+}
-+
-+struct recv_buf *rtw_dequeue_recvbuf(_queue *queue)
-+{
-+	_irqL irqL;
-+	struct recv_buf *precvbuf;
-+	_list	*plist, *phead;
-+
-+#ifdef CONFIG_SDIO_HCI
-+	_enter_critical_bh(&queue->lock, &irqL);
-+#else
-+	_enter_critical_ex(&queue->lock, &irqL);
-+#endif/*#ifdef CONFIG_SDIO_HCI*/
-+
-+	if (_rtw_queue_empty(queue) == _TRUE)
-+		precvbuf = NULL;
-+	else {
-+		phead = get_list_head(queue);
-+
-+		plist = get_next(phead);
-+
-+		precvbuf = LIST_CONTAINOR(plist, struct recv_buf, list);
-+
-+		rtw_list_delete(&precvbuf->list);
-+
-+	}
-+
-+#ifdef CONFIG_SDIO_HCI
-+	_exit_critical_bh(&queue->lock, &irqL);
-+#else
-+	_exit_critical_ex(&queue->lock, &irqL);
-+#endif/*#ifdef CONFIG_SDIO_HCI*/
-+
-+	return precvbuf;
-+
-+}
-+
-+sint recvframe_chkmic(_adapter *adapter,  union recv_frame *precvframe);
-+sint recvframe_chkmic(_adapter *adapter,  union recv_frame *precvframe)
-+{
-+
-+	sint	i, res = _SUCCESS;
-+	u32	datalen;
-+	u8	miccode[8];
-+	u8	bmic_err = _FALSE, brpt_micerror = _TRUE;
-+	u8	*pframe, *payload, *pframemic;
-+	u8	*mickey;
-+	/* u8	*iv,rxdata_key_idx=0; */
-+	struct	sta_info		*stainfo;
-+	struct	rx_pkt_attrib	*prxattrib = &precvframe->u.hdr.attrib;
-+	struct	security_priv	*psecuritypriv = &adapter->securitypriv;
-+
-+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	stainfo = rtw_get_stainfo(&adapter->stapriv , &prxattrib->ta[0]);
-+
-+	if (prxattrib->encrypt == _TKIP_) {
-+
-+		/* calculate mic code */
-+		if (stainfo != NULL) {
-+			if (IS_MCAST(prxattrib->ra)) {
-+				/* mickey=&psecuritypriv->dot118021XGrprxmickey.skey[0]; */
-+				/* iv = precvframe->u.hdr.rx_data+prxattrib->hdrlen; */
-+				/* rxdata_key_idx =( ((iv[3])>>6)&0x3) ; */
-+				mickey = &psecuritypriv->dot118021XGrprxmickey[prxattrib->key_index].skey[0];
-+
-+				/* RTW_INFO("\n recvframe_chkmic: bcmc key psecuritypriv->dot118021XGrpKeyid(%d),pmlmeinfo->key_index(%d) ,recv key_id(%d)\n", */
-+				/*								psecuritypriv->dot118021XGrpKeyid,pmlmeinfo->key_index,rxdata_key_idx); */
-+
-+				if (psecuritypriv->binstallGrpkey == _FALSE) {
-+					res = _FAIL;
-+					RTW_INFO("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n");
-+					goto exit;
-+				}
-+			} else {
-+				mickey = &stainfo->dot11tkiprxmickey.skey[0];
-+			}
-+
-+			datalen = precvframe->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len - prxattrib->icv_len - 8; /* icv_len included the mic code */
-+			pframe = precvframe->u.hdr.rx_data;
-+			payload = pframe + prxattrib->hdrlen + prxattrib->iv_len;
-+
-+
-+			/* rtw_seccalctkipmic(&stainfo->dot11tkiprxmickey.skey[0],pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); */ /* care the length of the data */
-+
-+			rtw_seccalctkipmic(mickey, pframe, payload, datalen , &miccode[0], (unsigned char)prxattrib->priority); /* care the length of the data */
-+
-+			pframemic = payload + datalen;
-+
-+			bmic_err = _FALSE;
-+
-+			for (i = 0; i < 8; i++) {
-+				if (miccode[i] != *(pframemic + i)) {
-+					bmic_err = _TRUE;
-+				}
-+			}
-+
-+
-+			if (bmic_err == _TRUE) {
-+
-+
-+
-+				/* double check key_index for some timing issue , */
-+				/* cannot compare with psecuritypriv->dot118021XGrpKeyid also cause timing issue */
-+				if ((IS_MCAST(prxattrib->ra) == _TRUE)  && (prxattrib->key_index != pmlmeinfo->key_index))
-+					brpt_micerror = _FALSE;
-+
-+				if ((prxattrib->bdecrypted == _TRUE) && (brpt_micerror == _TRUE)) {
-+					rtw_handle_tkip_mic_err(adapter, stainfo, (u8)IS_MCAST(prxattrib->ra));
-+					RTW_INFO(" mic error :prxattrib->bdecrypted=%d\n", prxattrib->bdecrypted);
-+				} else {
-+					RTW_INFO(" mic error :prxattrib->bdecrypted=%d\n", prxattrib->bdecrypted);
-+				}
-+
-+				res = _FAIL;
-+
-+			} else {
-+				/* mic checked ok */
-+				if ((psecuritypriv->bcheck_grpkey == _FALSE) && (IS_MCAST(prxattrib->ra) == _TRUE)) {
-+					psecuritypriv->bcheck_grpkey = _TRUE;
-+				}
-+			}
-+
-+		}
-+
-+		recvframe_pull_tail(precvframe, 8);
-+
-+	}
-+
-+exit:
-+
-+
-+	return res;
-+
-+}
-+
-+/*#define DBG_RX_SW_DECRYPTOR*/
-+
-+/* decrypt and set the ivlen,icvlen of the recv_frame */
-+union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame);
-+union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+
-+	struct rx_pkt_attrib *prxattrib = &precv_frame->u.hdr.attrib;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	union recv_frame *return_packet = precv_frame;
-+	u32	 res = _SUCCESS;
-+
-+
-+	DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt);
-+
-+
-+	if (prxattrib->encrypt > 0) {
-+		u8 *iv = precv_frame->u.hdr.rx_data + prxattrib->hdrlen;
-+		prxattrib->key_index = (((iv[3]) >> 6) & 0x3) ;
-+
-+		if (prxattrib->key_index > WEP_KEYS) {
-+			RTW_INFO("prxattrib->key_index(%d) > WEP_KEYS\n", prxattrib->key_index);
-+
-+			switch (prxattrib->encrypt) {
-+			case _WEP40_:
-+			case _WEP104_:
-+				prxattrib->key_index = psecuritypriv->dot11PrivacyKeyIndex;
-+				break;
-+			case _TKIP_:
-+			case _AES_:
-+			case _GCMP_:
-+			case _GCMP_256_:
-+			case _CCMP_256_:
-+			default:
-+				prxattrib->key_index = psecuritypriv->dot118021XGrpKeyid;
-+				break;
-+			}
-+		}
-+	}
-+
-+	if (prxattrib->encrypt && !prxattrib->bdecrypted) {
-+		if (GetFrameType(get_recvframe_data(precv_frame)) == WIFI_DATA
-+			#ifdef CONFIG_CONCURRENT_MODE
-+			&& !IS_MCAST(prxattrib->ra) /* bc/mc packets may use sw decryption for concurrent mode */
-+			#endif
-+		)
-+			psecuritypriv->hw_decrypted = _FALSE;
-+
-+#ifdef DBG_RX_SW_DECRYPTOR
-+		RTW_INFO(ADPT_FMT" - sec_type:%s DO SW decryption\n",
-+			ADPT_ARG(padapter), security_type_str(prxattrib->encrypt));
-+#endif
-+
-+#ifdef DBG_RX_DECRYPTOR
-+		RTW_INFO("[%s] %d:prxstat->bdecrypted:%d,  prxattrib->encrypt:%d,  Setting psecuritypriv->hw_decrypted = %d\n",
-+			 __FUNCTION__,
-+			 __LINE__,
-+			 prxattrib->bdecrypted,
-+			 prxattrib->encrypt,
-+			 psecuritypriv->hw_decrypted);
-+#endif
-+
-+		switch (prxattrib->encrypt) {
-+		case _WEP40_:
-+		case _WEP104_:
-+			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_wep);
-+			rtw_wep_decrypt(padapter, (u8 *)precv_frame);
-+			break;
-+		case _TKIP_:
-+			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_tkip);
-+			res = rtw_tkip_decrypt(padapter, (u8 *)precv_frame);
-+			break;
-+		case _AES_:
-+		case _CCMP_256_:
-+			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_aes);
-+			res = rtw_aes_decrypt(padapter, (u8 *)precv_frame);
-+			break;
-+		case _GCMP_:
-+		case _GCMP_256_:
-+			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_gcmp);
-+			res = rtw_gcmp_decrypt(padapter, (u8 *)precv_frame);
-+			break;
-+#ifdef CONFIG_WAPI_SUPPORT
-+		case _SMS4_:
-+			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_wapi);
-+			rtw_sms4_decrypt(padapter, (u8 *)precv_frame);
-+			break;
-+#endif
-+		default:
-+			break;
-+		}
-+	} else if (prxattrib->bdecrypted == 1
-+		   && prxattrib->encrypt > 0
-+		&& (psecuritypriv->busetkipkey == 1 || prxattrib->encrypt != _TKIP_)
-+		  ) {
-+#if 0
-+		if ((prxstat->icv == 1) && (prxattrib->encrypt != _AES_)) {
-+			psecuritypriv->hw_decrypted = _FALSE;
-+
-+
-+			rtw_free_recvframe(precv_frame, &padapter->recvpriv.free_recv_queue);
-+
-+			return_packet = NULL;
-+
-+		} else
-+#endif
-+		{
-+			DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_hw);
-+
-+			psecuritypriv->hw_decrypted = _TRUE;
-+#ifdef DBG_RX_DECRYPTOR
-+			RTW_INFO("[%s] %d:prxstat->bdecrypted:%d,  prxattrib->encrypt:%d,  Setting psecuritypriv->hw_decrypted = %d\n",
-+				 __FUNCTION__,
-+				 __LINE__,
-+				 prxattrib->bdecrypted,
-+				 prxattrib->encrypt,
-+				 psecuritypriv->hw_decrypted);
-+
-+#endif
-+		}
-+	} else {
-+		DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_unknown);
-+#ifdef DBG_RX_DECRYPTOR
-+		RTW_INFO("[%s] %d:prxstat->bdecrypted:%d,  prxattrib->encrypt:%d,  Setting psecuritypriv->hw_decrypted = %d\n",
-+			 __FUNCTION__,
-+			 __LINE__,
-+			 prxattrib->bdecrypted,
-+			 prxattrib->encrypt,
-+			 psecuritypriv->hw_decrypted);
-+#endif
-+	}
-+
-+	#ifdef CONFIG_RTW_MESH
-+	if (res != _FAIL
-+		&& !prxattrib->amsdu
-+		&& prxattrib->mesh_ctrl_present)
-+		res = rtw_mesh_rx_validate_mctrl_non_amsdu(padapter, precv_frame);
-+	#endif
-+
-+	if (res == _FAIL) {
-+		rtw_free_recvframe(return_packet, &padapter->recvpriv.free_recv_queue);
-+		return_packet = NULL;
-+	} else
-+		prxattrib->bdecrypted = _TRUE;
-+	/* recvframe_chkmic(adapter, precv_frame);   */ /* move to recvframme_defrag function */
-+
-+
-+	return return_packet;
-+
-+}
-+/* ###set the security information in the recv_frame */
-+union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame);
-+union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame)
-+{
-+	u8 *psta_addr = NULL;
-+	u8 *ptr;
-+	uint  auth_alg;
-+	struct recv_frame_hdr *pfhdr;
-+	struct sta_info *psta;
-+	struct sta_priv *pstapriv ;
-+	union recv_frame *prtnframe;
-+	u16	ether_type = 0;
-+	u16  eapol_type = 0x888e;/* for Funia BD's WPA issue  */
-+	struct rx_pkt_attrib *pattrib;
-+
-+
-+	pstapriv = &adapter->stapriv;
-+
-+	auth_alg = adapter->securitypriv.dot11AuthAlgrthm;
-+
-+	ptr = get_recvframe_data(precv_frame);
-+	pfhdr = &precv_frame->u.hdr;
-+	pattrib = &pfhdr->attrib;
-+	psta_addr = pattrib->ta;
-+
-+	prtnframe = NULL;
-+
-+	psta = rtw_get_stainfo(pstapriv, psta_addr);
-+
-+
-+	if (auth_alg == dot11AuthAlgrthm_8021X) {
-+		if ((psta != NULL) && (psta->ieee8021x_blocked)) {
-+			/* blocked */
-+			/* only accept EAPOL frame */
-+
-+			prtnframe = precv_frame;
-+
-+			/* get ether_type */
-+			ptr = ptr + pfhdr->attrib.hdrlen + pfhdr->attrib.iv_len + LLC_HEADER_SIZE;
-+			_rtw_memcpy(&ether_type, ptr, 2);
-+			ether_type = ntohs((unsigned short)ether_type);
-+
-+			if (ether_type == eapol_type)
-+				prtnframe = precv_frame;
-+			else {
-+				/* free this frame */
-+				rtw_free_recvframe(precv_frame, &adapter->recvpriv.free_recv_queue);
-+				prtnframe = NULL;
-+			}
-+		} else {
-+			/* allowed */
-+			/* check decryption status, and decrypt the frame if needed */
-+
-+
-+			prtnframe = precv_frame;
-+			/* check is the EAPOL frame or not (Rekey) */
-+			/* if(ether_type == eapol_type){ */
-+			/* check Rekey */
-+
-+			/*	prtnframe=precv_frame; */
-+			/* } */
-+		}
-+	} else
-+		prtnframe = precv_frame;
-+
-+
-+	return prtnframe;
-+
-+}
-+
-+/* VALID_PN_CHK
-+ * Return true when PN is legal, otherwise false.
-+ * Legal PN:
-+ *	1. If old PN is 0, any PN is legal
-+ *	2. PN > old PN
-+ */
-+#define PN_LESS_CHK(a, b)	(((a-b) & 0x800000000000) != 0)
-+#define VALID_PN_CHK(new, old)	(((old) == 0) || PN_LESS_CHK(old, new))
-+#define CCMPH_2_KEYID(ch)	(((ch) & 0x00000000c0000000) >> 30)
-+sint recv_ucast_pn_decache(union recv_frame *precv_frame);
-+sint recv_ucast_pn_decache(union recv_frame *precv_frame)
-+{
-+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
-+	struct sta_info *sta = precv_frame->u.hdr.psta;
-+	struct stainfo_rxcache *prxcache = &sta->sta_recvpriv.rxcache;
-+	u8 *pdata = precv_frame->u.hdr.rx_data;
-+	sint tid = precv_frame->u.hdr.attrib.priority;
-+	u64 tmp_iv_hdr = 0;
-+	u64 curr_pn = 0, pkt_pn = 0;
-+
-+	if (tid > 15)
-+		return _FAIL;
-+
-+	if (pattrib->encrypt == _AES_) {
-+		tmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen));
-+		pkt_pn = CCMPH_2_PN(tmp_iv_hdr);
-+		tmp_iv_hdr = le64_to_cpu(*(u64*)prxcache->iv[tid]);
-+		curr_pn = CCMPH_2_PN(tmp_iv_hdr);
-+
-+		if (!VALID_PN_CHK(pkt_pn, curr_pn)) {
-+			/* return _FAIL; */
-+		} else {
-+			prxcache->last_tid = tid;
-+			_rtw_memcpy(prxcache->iv[tid],
-+				    (pdata + pattrib->hdrlen),
-+				    sizeof(prxcache->iv[tid]));
-+		}
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+sint recv_bcast_pn_decache(union recv_frame *precv_frame);
-+sint recv_bcast_pn_decache(union recv_frame *precv_frame)
-+{
-+	_adapter *padapter = precv_frame->u.hdr.adapter;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
-+	u8 *pdata = precv_frame->u.hdr.rx_data;
-+	u64 tmp_iv_hdr = 0;
-+	u64 curr_pn = 0, pkt_pn = 0;
-+	u8 key_id;
-+
-+	if ((pattrib->encrypt == _AES_) &&
-+		(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) {
-+
-+		tmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen));
-+		key_id = CCMPH_2_KEYID(tmp_iv_hdr);
-+		pkt_pn = CCMPH_2_PN(tmp_iv_hdr);
-+
-+		curr_pn = le64_to_cpu(*(u64*)psecuritypriv->iv_seq[key_id]);
-+		curr_pn &= 0x0000ffffffffffff;
-+
-+		if (!VALID_PN_CHK(pkt_pn, curr_pn))
-+			return _FAIL;
-+
-+		*(u64*)psecuritypriv->iv_seq[key_id] = cpu_to_le64(pkt_pn);
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+sint recv_decache(union recv_frame *precv_frame)
-+{
-+	struct sta_info *psta = precv_frame->u.hdr.psta;
-+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
-+	_adapter *adapter = psta->padapter;
-+	sint tid = pattrib->priority;
-+	u16 seq_ctrl = ((precv_frame->u.hdr.attrib.seq_num & 0xffff) << 4) |
-+		       (precv_frame->u.hdr.attrib.frag_num & 0xf);
-+	u16 *prxseq;
-+
-+	if (tid > 15)
-+		return _FAIL;
-+
-+	if (pattrib->qos) {
-+		if (IS_MCAST(pattrib->ra))
-+			prxseq = &psta->sta_recvpriv.bmc_tid_rxseq[tid];
-+		else
-+			prxseq = &psta->sta_recvpriv.rxcache.tid_rxseq[tid];
-+	} else {
-+		if (IS_MCAST(pattrib->ra)) {
-+			prxseq = &psta->sta_recvpriv.nonqos_bmc_rxseq;
-+			#ifdef DBG_RX_SEQ
-+			RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" nonqos bmc seq_num:%d\n"
-+				, FUNC_ADPT_ARG(adapter), pattrib->seq_num);
-+			#endif
-+
-+		} else {
-+			prxseq = &psta->sta_recvpriv.nonqos_rxseq;
-+			#ifdef DBG_RX_SEQ
-+			RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" nonqos seq_num:%d\n"
-+				, FUNC_ADPT_ARG(adapter), pattrib->seq_num);
-+			#endif
-+		}
-+	}
-+
-+	if (seq_ctrl == *prxseq) {
-+		/* for non-AMPDU case	*/
-+		psta->sta_stats.duplicate_cnt++;
-+
-+		if (psta->sta_stats.duplicate_cnt % 100 == 0)
-+			RTW_INFO("%s: tid=%u seq=%d frag=%d\n", __func__
-+				, tid, precv_frame->u.hdr.attrib.seq_num
-+				, precv_frame->u.hdr.attrib.frag_num);
-+
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_decache _FAIL for sta="MAC_FMT"\n"
-+			, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));
-+		#endif
-+		return _FAIL;
-+	}
-+	*prxseq = seq_ctrl;
-+
-+	return _SUCCESS;
-+}
-+
-+void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta)
-+{
-+#ifdef CONFIG_AP_MODE
-+	unsigned char pwrbit;
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+
-+	pwrbit = GetPwrMgt(ptr);
-+
-+	if (pwrbit) {
-+		if (!(psta->state & WIFI_SLEEP_STATE)) {
-+			/* psta->state |= WIFI_SLEEP_STATE; */
-+			/* rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */
-+
-+			stop_sta_xmit(padapter, psta);
-+			/* RTW_INFO_DUMP("to sleep, sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */
-+		}
-+	} else {
-+		if (psta->state & WIFI_SLEEP_STATE) {
-+			/* psta->state ^= WIFI_SLEEP_STATE; */
-+			/* rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */
-+
-+			wakeup_sta_to_xmit(padapter, psta);
-+			/* RTW_INFO_DUMP("to wakeup, sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */
-+		}
-+	}
-+#endif
-+}
-+
-+void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta)
-+{
-+#ifdef CONFIG_AP_MODE
-+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
-+
-+#ifdef CONFIG_TDLS
-+	if (!(psta->tdls_sta_state & TDLS_LINKED_STATE)) {
-+#endif /* CONFIG_TDLS */
-+
-+		if (!psta->qos_option)
-+			return;
-+
-+		if (!(psta->qos_info & 0xf))
-+			return;
-+
-+#ifdef CONFIG_TDLS
-+	}
-+#endif /* CONFIG_TDLS		 */
-+
-+	if (psta->state & WIFI_SLEEP_STATE) {
-+		u8 wmmps_ac = 0;
-+
-+		switch (pattrib->priority) {
-+		case 1:
-+		case 2:
-+			wmmps_ac = psta->uapsd_bk & BIT(1);
-+			break;
-+		case 4:
-+		case 5:
-+			wmmps_ac = psta->uapsd_vi & BIT(1);
-+			break;
-+		case 6:
-+		case 7:
-+			wmmps_ac = psta->uapsd_vo & BIT(1);
-+			break;
-+		case 0:
-+		case 3:
-+		default:
-+			wmmps_ac = psta->uapsd_be & BIT(1);
-+			break;
-+		}
-+
-+		if (wmmps_ac) {
-+			if (psta->sleepq_ac_len > 0) {
-+				/* process received triggered frame */
-+				xmit_delivery_enabled_frames(padapter, psta);
-+			} else {
-+				/* issue one qos null frame with More data bit = 0 and the EOSP bit set (=1) */
-+				issue_qos_nulldata(padapter, psta->cmn.mac_addr, (u16)pattrib->priority, 0, 0, 0);
-+			}
-+		}
-+
-+	}
-+
-+
-+#endif
-+
-+}
-+
-+#ifdef CONFIG_TDLS
-+sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame)
-+{
-+	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
-+	sint ret = _SUCCESS;
-+	u8 *paction = get_recvframe_data(precv_frame);
-+	u8 category_field = 1;
-+#ifdef CONFIG_WFD
-+	u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a };
-+#endif /* CONFIG_WFD */
-+	struct tdls_info *ptdlsinfo = &(adapter->tdlsinfo);
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	struct sta_priv *pstapriv = &(adapter->stapriv);
-+	struct sta_info *ptdls_sta = NULL;
-+
-+	/* point to action field */
-+	paction += pattrib->hdrlen
-+		   + pattrib->iv_len
-+		   + SNAP_SIZE
-+		   + ETH_TYPE_LEN
-+		   + PAYLOAD_TYPE_LEN
-+		   + category_field;
-+
-+	RTW_INFO("[TDLS] Recv %s from "MAC_FMT" with SeqNum = %d\n", rtw_tdls_action_txt(*paction), MAC_ARG(pattrib->src), GetSequence(get_recvframe_data(precv_frame)));
-+
-+	if (hal_chk_wl_func(adapter, WL_FUNC_TDLS) == _FALSE) {
-+		RTW_INFO("Ignore tdls frame since hal doesn't support tdls\n");
-+		ret = _FAIL;
-+		return ret;
-+	}
-+
-+	if (rtw_is_tdls_enabled(adapter) == _FALSE) {
-+		RTW_INFO("recv tdls frame, "
-+			 "but tdls haven't enabled\n");
-+		ret = _FAIL;
-+		return ret;
-+	}
-+
-+	ptdls_sta = rtw_get_stainfo(pstapriv, get_sa(ptr));
-+	if (ptdls_sta == NULL) {
-+		switch (*paction) {
-+		case TDLS_SETUP_REQUEST:
-+		case TDLS_DISCOVERY_REQUEST:
-+			break;
-+		default:
-+			RTW_INFO("[TDLS] %s - Direct Link Peer = "MAC_FMT" not found for action = %d\n", __func__, MAC_ARG(get_sa(ptr)), *paction);
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+	}
-+
-+	switch (*paction) {
-+	case TDLS_SETUP_REQUEST:
-+		ret = On_TDLS_Setup_Req(adapter, precv_frame, ptdls_sta);
-+		break;
-+	case TDLS_SETUP_RESPONSE:
-+		ret = On_TDLS_Setup_Rsp(adapter, precv_frame, ptdls_sta);
-+		break;
-+	case TDLS_SETUP_CONFIRM:
-+		ret = On_TDLS_Setup_Cfm(adapter, precv_frame, ptdls_sta);
-+		break;
-+	case TDLS_TEARDOWN:
-+		ret = On_TDLS_Teardown(adapter, precv_frame, ptdls_sta);
-+		break;
-+	case TDLS_DISCOVERY_REQUEST:
-+		ret = On_TDLS_Dis_Req(adapter, precv_frame);
-+		break;
-+	case TDLS_PEER_TRAFFIC_INDICATION:
-+		ret = On_TDLS_Peer_Traffic_Indication(adapter, precv_frame, ptdls_sta);
-+		break;
-+	case TDLS_PEER_TRAFFIC_RESPONSE:
-+		ret = On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame, ptdls_sta);
-+		break;
-+#ifdef CONFIG_TDLS_CH_SW
-+	case TDLS_CHANNEL_SWITCH_REQUEST:
-+		ret = On_TDLS_Ch_Switch_Req(adapter, precv_frame, ptdls_sta);
-+		break;
-+	case TDLS_CHANNEL_SWITCH_RESPONSE:
-+		ret = On_TDLS_Ch_Switch_Rsp(adapter, precv_frame, ptdls_sta);
-+		break;
-+#endif
-+#ifdef CONFIG_WFD
-+	/* First byte of WFA OUI */
-+	case 0x50:
-+		if (_rtw_memcmp(WFA_OUI, paction, 3)) {
-+			/* Probe request frame */
-+			if (*(paction + 3) == 0x04) {
-+				/* WFDTDLS: for sigma test, do not setup direct link automatically */
-+				ptdlsinfo->dev_discovered = _TRUE;
-+				RTW_INFO("recv tunneled probe request frame\n");
-+				issue_tunneled_probe_rsp(adapter, precv_frame);
-+			}
-+			/* Probe response frame */
-+			if (*(paction + 3) == 0x05) {
-+				/* WFDTDLS: for sigma test, do not setup direct link automatically */
-+				ptdlsinfo->dev_discovered = _TRUE;
-+				RTW_INFO("recv tunneled probe response frame\n");
-+			}
-+		}
-+		break;
-+#endif /* CONFIG_WFD */
-+	default:
-+		RTW_INFO("receive TDLS frame %d but not support\n", *paction);
-+		ret = _FAIL;
-+		break;
-+	}
-+
-+exit:
-+	return ret;
-+
-+}
-+
-+sint rtw_tdls_rx_data_validate_hdr(
-+	_adapter *adapter,
-+	union recv_frame *precv_frame,
-+	struct sta_info **psta
-+)
-+{
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	sint ret = _SUCCESS;
-+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
-+	struct	sta_priv		*pstapriv = &adapter->stapriv;
-+	struct	mlme_priv	*pmlmepriv = &adapter->mlmepriv;
-+	u8 *mybssid  = get_bssid(pmlmepriv);
-+	u8 *myhwaddr = adapter_mac_addr(adapter);
-+	u8 *sta_addr = pattrib->ta;
-+	sint bmcast = IS_MCAST(pattrib->dst);
-+
-+	struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
-+#ifdef CONFIG_TDLS_CH_SW
-+	struct tdls_ch_switch *pchsw_info = &ptdlsinfo->chsw_info;
-+#endif
-+	struct sta_info *ptdls_sta = NULL;
-+	u8 *psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE;
-+	/* frame body located after [+2]: ether-type, [+1]: payload type */
-+	u8 *pframe_body = psnap_type + 2 + 1;
-+
-+	*psta = ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->ta);
-+	if (ptdls_sta == NULL) {
-+		ret = _FAIL;
-+		goto exit;
-+	} else if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
-+		/* filter packets that SA is myself or multicast or broadcast */
-+		if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) {
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+		/* da should be for me */
-+		if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) {
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+		/* check BSSID */
-+		if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
-+		    _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
-+		    (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) {
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+
-+#ifdef CONFIG_TDLS_CH_SW
-+		if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) {
-+			if (adapter->mlmeextpriv.cur_channel != rtw_get_oper_ch(adapter)) {
-+				pchsw_info->ch_sw_state |= TDLS_PEER_AT_OFF_STATE;
-+				if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
-+					_cancel_timer_ex(&ptdls_sta->ch_sw_timer);
-+				/* On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame); */
-+			}
-+		}
-+#endif
-+
-+		/* process UAPSD tdls sta */
-+		process_pwrbit_data(adapter, precv_frame, ptdls_sta);
-+
-+		/* if NULL-frame, check pwrbit */
-+		if ((get_frame_sub_type(ptr) & WIFI_DATA_NULL) == WIFI_DATA_NULL) {
-+			/* NULL-frame with pwrbit=1, buffer_STA should buffer frames for sleep_STA */
-+			if (GetPwrMgt(ptr)) {
-+				/* it would be triggered when we are off channel and receiving NULL DATA */
-+				/* we can confirm that peer STA is at off channel */
-+				RTW_INFO("TDLS: recv peer null frame with pwr bit 1\n");
-+				/* ptdls_sta->tdls_sta_state|=TDLS_PEER_SLEEP_STATE; */
-+			}
-+
-+			/* TODO: Updated BSSID's seq. */
-+			/* RTW_INFO("drop Null Data\n"); */
-+			ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE);
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+
-+		/* receive some of all TDLS management frames, process it at ON_TDLS */
-+		if (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, 2)) {
-+			ret = OnTDLS(adapter, precv_frame);
-+			goto exit;
-+		}
-+
-+		if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE)
-+			process_wmmps_data(adapter, precv_frame, ptdls_sta);
-+
-+		ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE);
-+
-+	}
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_TDLS */
-+
-+void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta)
-+{
-+	int	sz;
-+	struct sta_info		*psta = NULL;
-+	struct stainfo_stats	*pstats = NULL;
-+	struct rx_pkt_attrib	*pattrib = &prframe->u.hdr.attrib;
-+	struct recv_priv		*precvpriv = &padapter->recvpriv;
-+
-+	sz = get_recvframe_len(prframe);
-+	precvpriv->rx_bytes += sz;
-+
-+	padapter->mlmepriv.LinkDetectInfo.NumRxOkInPeriod++;
-+
-+	if ((!MacAddr_isBcst(pattrib->dst)) && (!IS_MCAST(pattrib->dst)))
-+		padapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod++;
-+
-+	if (sta)
-+		psta = sta;
-+	else
-+		psta = prframe->u.hdr.psta;
-+
-+	if (psta) {
-+		u8 is_ra_bmc = IS_MCAST(pattrib->ra);
-+
-+		pstats = &psta->sta_stats;
-+
-+		pstats->last_rx_time = rtw_get_current_time();
-+		pstats->rx_data_pkts++;
-+		pstats->rx_bytes += sz;
-+		if (is_broadcast_mac_addr(pattrib->ra)) {
-+			pstats->rx_data_bc_pkts++;
-+			pstats->rx_bc_bytes += sz;
-+		} else if (is_ra_bmc) {
-+			pstats->rx_data_mc_pkts++;
-+			pstats->rx_mc_bytes += sz;
-+		}
-+
-+		if (!is_ra_bmc) {
-+			pstats->rxratecnt[pattrib->data_rate]++;
-+			/*record rx packets for every tid*/
-+			pstats->rx_data_qos_pkts[pattrib->priority]++;
-+		}
-+#ifdef CONFIG_DYNAMIC_SOML
-+		rtw_dyn_soml_byte_update(padapter, pattrib->data_rate, sz);
-+#endif
-+#if defined(CONFIG_CHECK_LEAVE_LPS) && defined(CONFIG_LPS_CHK_BY_TP)
-+		if (adapter_to_pwrctl(padapter)->lps_chk_by_tp)
-+			traffic_check_for_leave_lps_by_tp(padapter, _FALSE, psta);
-+#endif /* CONFIG_LPS */
-+
-+	}
-+
-+#ifdef CONFIG_CHECK_LEAVE_LPS
-+#ifdef CONFIG_LPS_CHK_BY_TP
-+	if (!adapter_to_pwrctl(padapter)->lps_chk_by_tp)
-+#endif
-+		traffic_check_for_leave_lps(padapter, _FALSE, 0);
-+#endif /* CONFIG_CHECK_LEAVE_LPS */
-+
-+}
-+
-+int rtw_sta_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	u8 *mybssid  = get_bssid(&adapter->mlmepriv);
-+	u8 *myhwaddr = adapter_mac_addr(adapter);
-+	struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
-+	u8 *whdr = get_recvframe_data(rframe);
-+	u8 is_ra_bmc = IS_MCAST(GetAddr1Ptr(whdr)) ? 1 : 0;
-+	sint ret = _FAIL;
-+
-+	if (rattrib->to_fr_ds == 0) {
-+		_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->src, get_addr2_ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->bssid, GetAddr3Ptr(whdr), ETH_ALEN);
-+
-+		#ifdef CONFIG_TDLS
-+		if (adapter->tdlsinfo.link_established == _TRUE)
-+			ret = rtw_tdls_rx_data_validate_hdr(adapter, rframe, sta);
-+		else
-+		#endif
-+		{
-+			/* For Station mode, sa and bssid should always be BSSID, and DA is my mac-address */
-+			if (!_rtw_memcmp(rattrib->bssid, rattrib->src, ETH_ALEN))
-+				goto exit;
-+
-+			*sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr));
-+			if (*sta)
-+				ret = _SUCCESS;
-+		}
-+		goto exit;
-+	}
-+
-+	if (!(MLME_STATE(adapter) & (WIFI_ASOC_STATE | WIFI_UNDER_LINKING))) {
-+		if (!is_ra_bmc) {
-+			/* for AP multicast issue , modify by yiwei */
-+			static systime send_issue_deauth_time = 0;
-+
-+			/* RTW_INFO("After send deauth , %u ms has elapsed.\n", rtw_get_passing_time_ms(send_issue_deauth_time)); */
-+			if (rtw_get_passing_time_ms(send_issue_deauth_time) > 10000 || send_issue_deauth_time == 0) {
-+				send_issue_deauth_time = rtw_get_current_time();
-+				RTW_INFO(FUNC_ADPT_FMT" issue_deauth to "MAC_FMT" with reason(7), mlme_state:0x%x\n"
-+					, FUNC_ADPT_ARG(adapter), MAC_ARG(get_addr2_ptr(whdr)), MLME_STATE(adapter));
-+				issue_deauth(adapter, get_addr2_ptr(whdr), WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
-+			}
-+		}
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fw_state:0x%x\n"
-+			, FUNC_ADPT_ARG(adapter), MLME_STATE(adapter));
-+		#endif
-+		goto exit;
-+	}
-+
-+	_rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
-+	_rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
-+
-+	switch (rattrib->to_fr_ds) {
-+	case 2:
-+		_rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN);
-+		_rtw_memcpy(rattrib->src, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
-+		_rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN);
-+		break;
-+	case 3:
-+		_rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
-+		_rtw_memcpy(rattrib->src, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
-+		_rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN);
-+		break;
-+	default:
-+		ret = RTW_RX_HANDLED; /* don't count for drop */
-+		goto exit;
-+	}
-+
-+	/* filter packets that SA is myself */
-+	if (!rattrib->amsdu && _rtw_memcmp(myhwaddr, rattrib->src, ETH_ALEN)) {
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" SA="MAC_FMT", myhwaddr="MAC_FMT"\n"
-+			, FUNC_ADPT_ARG(adapter), MAC_ARG(rattrib->src), MAC_ARG(myhwaddr));
-+		#endif
-+		goto exit;
-+	}
-+
-+	*sta = rtw_get_stainfo(stapriv, rattrib->ta);
-+	if (*sta == NULL) {
-+		#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL
-+		if (!is_ra_bmc && !IS_RADAR_DETECTED(adapter_to_rfctl(adapter))) {
-+			RTW_INFO(FUNC_ADPT_FMT" issue_deauth to "MAC_FMT" with reason(7), unknown TA\n"
-+				, FUNC_ADPT_ARG(adapter), MAC_ARG(rattrib->ta));
-+			issue_deauth(adapter, rattrib->ta, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
-+		}
-+		#endif
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under STATION_MODE ; drop pkt\n"
-+			, FUNC_ADPT_ARG(adapter));
-+		#endif
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_RTW_WDS_AUTO_EN
-+	if (rattrib->to_fr_ds == 3 && !(sta->flags & WLAN_STA_WDS))
-+		sta->flags |= WLAN_STA_WDS;
-+#endif
-+
-+	/*if ((get_frame_sub_type(whdr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) {
-+	}
-+	*/
-+
-+	if (get_frame_sub_type(whdr) & BIT(6)) {
-+		/* No data, will not indicate to upper layer, temporily count it here */
-+		count_rx_stats(adapter, rframe, *sta);
-+		ret = RTW_RX_HANDLED;
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_RTW_WDS
-+	if (adapter_use_wds(adapter)
-+		&& !rattrib->amsdu && IS_MCAST(rattrib->dst)
-+		&& rtw_rx_wds_gptr_check(adapter, rattrib->src)
-+	) {
-+		/* will not indicate to upper layer, temporily count it here */
-+		count_rx_stats(adapter, rframe, *sta);
-+		ret = RTW_RX_HANDLED;
-+		goto exit;
-+	}
-+#endif
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+int rtw_sta_rx_amsdu_act_check(union recv_frame *rframe
-+	, const u8 *da, const u8 *sa)
-+{
-+	int act = RTW_RX_MSDU_ACT_INDICATE;
-+
-+#ifdef CONFIG_RTW_WDS
-+	_adapter *adapter = rframe->u.hdr.adapter;
-+
-+	if (adapter_use_wds(adapter)
-+		&& IS_MCAST(da)
-+		&& rtw_rx_wds_gptr_check(adapter, sa)
-+	) {
-+		act = 0;
-+	}
-+#endif
-+
-+	return act;
-+}
-+
-+sint sta2sta_data_frame(
-+	_adapter *adapter,
-+	union recv_frame *precv_frame,
-+	struct sta_info **psta
-+)
-+{
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	sint ret = _SUCCESS;
-+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
-+	struct	sta_priv		*pstapriv = &adapter->stapriv;
-+	struct	mlme_priv	*pmlmepriv = &adapter->mlmepriv;
-+	u8 *mybssid  = get_bssid(pmlmepriv);
-+	u8 *myhwaddr = adapter_mac_addr(adapter);
-+	u8 *sta_addr = pattrib->ta;
-+	sint bmcast = IS_MCAST(pattrib->dst);
-+
-+	/* RTW_INFO("[%s] %d, seqnum:%d\n", __FUNCTION__, __LINE__, pattrib->seq_num); */
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||
-+	    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
-+
-+		/* filter packets that SA is myself or multicast or broadcast */
-+		if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) {
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+
-+		if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN))	&& (!bmcast)) {
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+
-+		if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
-+		    _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
-+		    (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) {
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+
-+	} else if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) {
-+		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
-+		_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+
-+		sta_addr = mybssid;
-+	} else
-+		ret  = _FAIL;
-+
-+	*psta = rtw_get_stainfo(pstapriv, sta_addr);
-+	if (*psta == NULL) {
-+#ifdef CONFIG_MP_INCLUDED
-+		if (adapter->registrypriv.mp_mode == 1) {
-+			if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
-+				adapter->mppriv.rx_pktloss++;
-+		}
-+#endif
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+sint ap2sta_data_frame(
-+	_adapter *adapter,
-+	union recv_frame *precv_frame,
-+	struct sta_info **psta)
-+{
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
-+	sint ret = _SUCCESS;
-+	struct	sta_priv		*pstapriv = &adapter->stapriv;
-+	struct	mlme_priv	*pmlmepriv = &adapter->mlmepriv;
-+	u8 *myhwaddr = adapter_mac_addr(adapter);
-+	sint bmcast = IS_MCAST(pattrib->dst);
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) &&
-+		   (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
-+		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
-+		_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+
-+
-+		*psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */
-+		if (*psta == NULL) {
-+			#ifdef DBG_RX_DROP_FRAME
-+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under WIFI_MP_STATE ; drop pkt\n"
-+				, FUNC_ADPT_ARG(adapter));
-+			#endif
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+
-+	} else {
-+		if (_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN) && (!bmcast)) {
-+			*psta = rtw_get_stainfo(pstapriv, pattrib->ta);
-+			if (*psta == NULL) {
-+
-+				/* for AP multicast issue , modify by yiwei */
-+				static systime send_issue_deauth_time = 0;
-+
-+				/* RTW_INFO("After send deauth , %u ms has elapsed.\n", rtw_get_passing_time_ms(send_issue_deauth_time)); */
-+
-+				if (rtw_get_passing_time_ms(send_issue_deauth_time) > 10000 || send_issue_deauth_time == 0) {
-+					send_issue_deauth_time = rtw_get_current_time();
-+
-+					RTW_INFO("issue_deauth to the ap=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->bssid));
-+
-+					issue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
-+				}
-+			}
-+		}
-+
-+		ret = _FAIL;
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fw_state:0x%x\n"
-+			, FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));
-+		#endif
-+	}
-+
-+exit:
-+	return ret;
-+
-+}
-+
-+sint sta2ap_data_frame(
-+	_adapter *adapter,
-+	union recv_frame *precv_frame,
-+	struct sta_info **psta)
-+{
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
-+	struct	sta_priv		*pstapriv = &adapter->stapriv;
-+	struct	mlme_priv	*pmlmepriv = &adapter->mlmepriv;
-+	unsigned char *mybssid  = get_bssid(pmlmepriv);
-+	sint ret = _SUCCESS;
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) &&
-+		   (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
-+		/* RTW_INFO("%s ,in WIFI_MP_STATE\n",__func__); */
-+		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
-+		_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+
-+
-+		*psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */
-+		if (*psta == NULL) {
-+			#ifdef DBG_RX_DROP_FRAME
-+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under WIFI_MP_STATE ; drop pkt\n"
-+				, FUNC_ADPT_ARG(adapter));
-+			#endif
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+
-+	} else {
-+		u8 *myhwaddr = adapter_mac_addr(adapter);
-+		if (!_rtw_memcmp(pattrib->ra, myhwaddr, ETH_ALEN)) {
-+			ret = RTW_RX_HANDLED;
-+			goto exit;
-+		}
-+#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL
-+		RTW_INFO("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src));
-+		issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
-+#endif
-+		ret = RTW_RX_HANDLED;
-+		goto exit;
-+	}
-+
-+exit:
-+
-+
-+	return ret;
-+
-+}
-+
-+sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame);
-+sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	struct sta_info *psta = NULL;
-+	/* uint len = precv_frame->u.hdr.len; */
-+
-+	/* RTW_INFO("+validate_recv_ctrl_frame\n"); */
-+
-+	if (GetFrameType(pframe) != WIFI_CTRL_TYPE)
-+		return _FAIL;
-+
-+	/* receive the frames that ra(a1) is my address */
-+	if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN))
-+		return _FAIL;
-+
-+	psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
-+	if (psta == NULL)
-+		return _FAIL;
-+
-+	/* for rx pkt statistics */
-+	psta->sta_stats.last_rx_time = rtw_get_current_time();
-+	psta->sta_stats.rx_ctrl_pkts++;
-+
-+	/* only handle ps-poll */
-+	if (get_frame_sub_type(pframe) == WIFI_PSPOLL) {
-+#ifdef CONFIG_AP_MODE
-+		u16 aid;
-+		u8 wmmps_ac = 0;
-+
-+		aid = GetAid(pframe);
-+		if (psta->cmn.aid != aid)
-+			return _FAIL;
-+
-+		switch (pattrib->priority) {
-+		case 1:
-+		case 2:
-+			wmmps_ac = psta->uapsd_bk & BIT(0);
-+			break;
-+		case 4:
-+		case 5:
-+			wmmps_ac = psta->uapsd_vi & BIT(0);
-+			break;
-+		case 6:
-+		case 7:
-+			wmmps_ac = psta->uapsd_vo & BIT(0);
-+			break;
-+		case 0:
-+		case 3:
-+		default:
-+			wmmps_ac = psta->uapsd_be & BIT(0);
-+			break;
-+		}
-+
-+		if (wmmps_ac)
-+			return _FAIL;
-+
-+		#ifdef CONFIG_AP_MODE
-+		if (psta->state & WIFI_STA_ALIVE_CHK_STATE) {
-+			RTW_INFO("%s alive check-rx ps-poll\n", __func__);
-+			psta->expire_to = pstapriv->expire_to;
-+			psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
-+		}
-+		#endif
-+
-+		if ((psta->state & WIFI_SLEEP_STATE) && (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid))) {
-+			_irqL irqL;
-+			_list	*xmitframe_plist, *xmitframe_phead;
-+			struct xmit_frame *pxmitframe = NULL;
-+			struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+
-+			/* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */
-+			_enter_critical_bh(&pxmitpriv->lock, &irqL);
-+
-+			xmitframe_phead = get_list_head(&psta->sleep_q);
-+			xmitframe_plist = get_next(xmitframe_phead);
-+
-+			if ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
-+				pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
-+
-+				xmitframe_plist = get_next(xmitframe_plist);
-+
-+				rtw_list_delete(&pxmitframe->list);
-+
-+				psta->sleepq_len--;
-+
-+				if (psta->sleepq_len > 0)
-+					pxmitframe->attrib.mdata = 1;
-+				else
-+					pxmitframe->attrib.mdata = 0;
-+
-+				pxmitframe->attrib.triggered = 1;
-+
-+				/* RTW_INFO("handling ps-poll, q_len=%d\n", psta->sleepq_len); */
-+				/* RTW_INFO_DUMP("handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
-+
-+#if 0
-+				_exit_critical_bh(&psta->sleep_q.lock, &irqL);
-+				if (rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
-+					rtw_os_xmit_complete(padapter, pxmitframe);
-+				_enter_critical_bh(&psta->sleep_q.lock, &irqL);
-+#endif
-+				rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
-+
-+				if (psta->sleepq_len == 0) {
-+					rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
-+
-+					/* RTW_INFO("after handling ps-poll\n"); */
-+					/* RTW_INFO_DUMP("after handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
-+
-+					/* upate BCN for TIM IE */
-+					/* update_BCNTIM(padapter);		 */
-+					update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0);
-+				}
-+
-+				/* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */
-+				_exit_critical_bh(&pxmitpriv->lock, &irqL);
-+
-+			} else {
-+				/* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */
-+				_exit_critical_bh(&pxmitpriv->lock, &irqL);
-+
-+				/* RTW_INFO("no buffered packets to xmit\n"); */
-+				if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {
-+					if (psta->sleepq_len == 0) {
-+						RTW_INFO("no buffered packets to xmit\n");
-+
-+						/* issue nulldata with More data bit = 0 to indicate we have no buffered packets */
-+						issue_nulldata(padapter, psta->cmn.mac_addr, 0, 0, 0);
-+					} else {
-+						RTW_INFO("error!psta->sleepq_len=%d\n", psta->sleepq_len);
-+						psta->sleepq_len = 0;
-+					}
-+
-+					rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
-+
-+					/* upate BCN for TIM IE */
-+					/* update_BCNTIM(padapter); */
-+					update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0);
-+				}
-+			}
-+		}
-+#endif /* CONFIG_AP_MODE */
-+	} else if (get_frame_sub_type(pframe) == WIFI_NDPA) {
-+#ifdef CONFIG_BEAMFORMING
-+		rtw_beamforming_get_ndpa_frame(padapter, precv_frame);
-+#endif/*CONFIG_BEAMFORMING*/
-+	} else if (get_frame_sub_type(pframe) == WIFI_BAR) {
-+		rtw_process_bar_frame(padapter, precv_frame);
-+	}
-+
-+	return _FAIL;
-+
-+}
-+
-+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
-+static sint validate_mgmt_protect(_adapter *adapter, union recv_frame *precv_frame)
-+{
-+#define DBG_VALIDATE_MGMT_PROTECT 0
-+#define DBG_VALIDATE_MGMT_DEC 0
-+
-+	struct security_priv *sec = &adapter->securitypriv;
-+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
-+	struct sta_info	*psta = precv_frame->u.hdr.psta;
-+	u8 *ptr;
-+	u8 type;
-+	u8 subtype;
-+	u8 is_bmc;
-+	u8 category = 0xFF;
-+
-+#ifdef CONFIG_IEEE80211W
-+	const u8 *igtk;
-+	u16 igtk_id;
-+	u64* ipn;
-+	enum security_type bip_cipher;
-+#endif
-+
-+	u8 *mgmt_DATA;
-+	u32 data_len = 0;
-+
-+	sint ret;
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(adapter)) {
-+		if (!adapter->mesh_info.mesh_auth_id)
-+			return pattrib->privacy ? _FAIL : _SUCCESS;
-+	} else
-+#endif
-+	if (SEC_IS_BIP_KEY_INSTALLED(sec) == _FALSE)
-+		return _SUCCESS;
-+
-+	ptr = precv_frame->u.hdr.rx_data;
-+	type = GetFrameType(ptr);
-+	subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */
-+	is_bmc = IS_MCAST(GetAddr1Ptr(ptr));
-+
-+#if DBG_VALIDATE_MGMT_PROTECT
-+	if (subtype == WIFI_DEAUTH) {
-+		RTW_INFO(FUNC_ADPT_FMT" bmc:%u, deauth, privacy:%u, encrypt:%u, bdecrypted:%u\n"
-+			, FUNC_ADPT_ARG(adapter)
-+			, is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
-+	} else if (subtype == WIFI_DISASSOC) {
-+		RTW_INFO(FUNC_ADPT_FMT" bmc:%u, disassoc, privacy:%u, encrypt:%u, bdecrypted:%u\n"
-+			, FUNC_ADPT_ARG(adapter)
-+			, is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
-+	} if (subtype == WIFI_ACTION) {
-+		if (pattrib->privacy) {
-+			RTW_INFO(FUNC_ADPT_FMT" bmc:%u, action(?), privacy:%u, encrypt:%u, bdecrypted:%u\n"
-+				, FUNC_ADPT_ARG(adapter)
-+				, is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
-+		} else {
-+			RTW_INFO(FUNC_ADPT_FMT" bmc:%u, action(%u), privacy:%u, encrypt:%u, bdecrypted:%u\n"
-+				, FUNC_ADPT_ARG(adapter), is_bmc
-+				, *(ptr + sizeof(struct rtw_ieee80211_hdr_3addr))
-+				, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
-+		}
-+	}
-+#endif
-+
-+	if (!pattrib->privacy) {
-+		if (!psta || !(psta->flags & WLAN_STA_MFP)) {
-+			/* peer is not MFP capable, no need to check */
-+			goto exit;
-+		}
-+
-+		if (subtype == WIFI_ACTION)
-+			category = *(ptr + sizeof(struct rtw_ieee80211_hdr_3addr));
-+
-+		if (is_bmc) {
-+			/* broadcast cases */
-+			if (subtype == WIFI_ACTION) {
-+				if (CATEGORY_IS_GROUP_PRIVACY(category)) {
-+					/* drop broadcast group privacy action frame without encryption */
-+					#if DBG_VALIDATE_MGMT_PROTECT
-+					RTW_INFO(FUNC_ADPT_FMT" broadcast gp action(%u) w/o encrypt\n"
-+						, FUNC_ADPT_ARG(adapter), category);
-+					#endif
-+					goto fail;
-+				}
-+				if (CATEGORY_IS_ROBUST(category)) {
-+					/* broadcast robust action frame need BIP check */
-+					goto bip_verify;
-+				}
-+			}
-+			if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) {
-+				/* broadcast deauth or disassoc frame need BIP check */
-+				goto bip_verify;
-+			}
-+			goto exit;
-+
-+		} else {
-+			/* unicast cases */
-+			#ifdef CONFIG_IEEE80211W
-+			if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) {
-+				if (!MLME_IS_MESH(adapter)) {
-+					unsigned short reason = le16_to_cpu(*(unsigned short *)(ptr + WLAN_HDR_A3_LEN));
-+
-+					#if DBG_VALIDATE_MGMT_PROTECT
-+					RTW_INFO(FUNC_ADPT_FMT" unicast %s, reason=%d w/o encrypt\n"
-+						, FUNC_ADPT_ARG(adapter), subtype == WIFI_DEAUTH ? "deauth" : "disassoc", reason);
-+					#endif
-+					if (reason == 6 || reason == 7) {
-+						/* issue sa query request */
-+						issue_action_SA_Query(adapter, psta->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY);
-+					}
-+				}
-+				goto fail;
-+			}
-+			#endif
-+
-+			if (subtype == WIFI_ACTION && CATEGORY_IS_ROBUST(category)) {
-+				if (psta->bpairwise_key_installed == _TRUE) {
-+					#if DBG_VALIDATE_MGMT_PROTECT
-+					RTW_INFO(FUNC_ADPT_FMT" unicast robust action(%d) w/o encrypt\n"
-+						, FUNC_ADPT_ARG(adapter), category);
-+					#endif
-+					goto fail;
-+				}
-+			}
-+			goto exit;
-+		}
-+
-+bip_verify:
-+#ifdef CONFIG_IEEE80211W
-+		#ifdef CONFIG_RTW_MESH
-+		if (MLME_IS_MESH(adapter)) {
-+			if (psta->igtk_bmp) {
-+				bip_cipher = psta->dot11wCipher;
-+				igtk = psta->igtk.skey;
-+				igtk_id = psta->igtk_id;
-+				ipn = &psta->igtk_pn.val;
-+			} else {
-+				/* mesh MFP without IGTK */
-+				goto exit;
-+			}
-+		} else
-+		#endif
-+		{
-+			bip_cipher = sec->dot11wCipher;
-+			igtk = sec->dot11wBIPKey[sec->dot11wBIPKeyid].skey;
-+			igtk_id = sec->dot11wBIPKeyid;
-+			ipn = &sec->dot11wBIPrxpn.val;
-+		}
-+
-+		/* verify BIP MME IE */
-+		ret = rtw_bip_verify(bip_cipher, pattrib->pkt_len,
-+			get_recvframe_data(precv_frame),
-+			get_recvframe_len(precv_frame),
-+			igtk, igtk_id, ipn);
-+
-+		if (ret == _FAIL) {
-+			/* RTW_INFO("802.11w BIP verify fail\n"); */
-+			goto fail;
-+
-+		} else if (ret == RTW_RX_HANDLED) {
-+			#if DBG_VALIDATE_MGMT_PROTECT
-+			RTW_INFO(FUNC_ADPT_FMT" none protected packet\n", FUNC_ADPT_ARG(adapter));
-+			#endif
-+			goto fail;
-+		}
-+#endif /* CONFIG_IEEE80211W */
-+		goto exit;
-+	}
-+
-+	if (!psta || !(psta->flags & WLAN_STA_MFP)) {
-+		/* not peer or peer is not MFP capable, drop it */
-+		goto fail;
-+	}
-+
-+	/* cases to decrypt mgmt frame */
-+	pattrib->bdecrypted = 0;
-+#ifdef CONFIG_RTW_MESH
-+	if (is_bmc)
-+		pattrib->encrypt = psta->group_privacy;
-+	else
-+#endif
-+	pattrib->encrypt = psta->dot118021XPrivacy;
-+	pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	/* set iv and icv length */
-+	SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt);
-+	_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
-+
-+	/* actual management data frame body */
-+	data_len = pattrib->pkt_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
-+	mgmt_DATA = rtw_zmalloc(data_len);
-+	if (mgmt_DATA == NULL) {
-+		RTW_INFO(FUNC_ADPT_FMT" mgmt allocate fail  !!!!!!!!!\n", FUNC_ADPT_ARG(adapter));
-+		goto fail;
-+	}
-+
-+#if DBG_VALIDATE_MGMT_DEC
-+	/* dump the packet content before decrypt */
-+	{
-+		int pp;
-+
-+		printk("pattrib->pktlen = %d =>", pattrib->pkt_len);
-+		for (pp = 0; pp < pattrib->pkt_len; pp++)
-+		printk(" %02x ", ptr[pp]);
-+		printk("\n");
-+	}
-+#endif
-+
-+	precv_frame = decryptor(adapter, precv_frame);
-+	/* save actual management data frame body */
-+	_rtw_memcpy(mgmt_DATA, ptr + pattrib->hdrlen + pattrib->iv_len, data_len);
-+	/* overwrite the iv field */
-+	_rtw_memcpy(ptr + pattrib->hdrlen, mgmt_DATA, data_len);
-+	/* remove the iv and icv length */
-+	pattrib->pkt_len = pattrib->pkt_len - pattrib->iv_len - pattrib->icv_len;
-+	rtw_mfree(mgmt_DATA, data_len);
-+
-+#if DBG_VALIDATE_MGMT_DEC
-+	/* print packet content after decryption */
-+	{
-+		int pp;
-+
-+		printk("after decryption pattrib->pktlen = %d @@=>", pattrib->pkt_len);
-+		for (pp = 0; pp < pattrib->pkt_len; pp++)
-+		printk(" %02x ", ptr[pp]);
-+		printk("\n");
-+	}
-+#endif
-+
-+	if (!precv_frame) {
-+		#if DBG_VALIDATE_MGMT_PROTECT
-+		RTW_INFO(FUNC_ADPT_FMT" mgmt descrypt fail  !!!!!!!!!\n", FUNC_ADPT_ARG(adapter));
-+		#endif
-+		goto fail;
-+	}
-+
-+exit:
-+	return _SUCCESS;
-+
-+fail:
-+	return _FAIL;
-+
-+}
-+#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */
-+
-+union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame);
-+
-+sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame)
-+{
-+	struct sta_info *psta = precv_frame->u.hdr.psta
-+		= rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(precv_frame->u.hdr.rx_data));
-+
-+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
-+	if (validate_mgmt_protect(padapter, precv_frame) == _FAIL) {
-+		DBG_COUNTER(padapter->rx_logs.core_rx_pre_mgmt_err_80211w);
-+		goto exit;
-+	}
-+#endif
-+
-+	precv_frame = recvframe_chk_defrag(padapter, precv_frame);
-+	if (precv_frame == NULL)
-+		return _SUCCESS;
-+
-+	/* for rx pkt statistics */
-+	if (psta) {
-+		psta->sta_stats.last_rx_time = rtw_get_current_time();
-+		psta->sta_stats.rx_mgnt_pkts++;
-+		if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_BEACON)
-+			psta->sta_stats.rx_beacon_pkts++;
-+		else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ)
-+			psta->sta_stats.rx_probereq_pkts++;
-+		else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) {
-+			if (_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE)
-+				psta->sta_stats.rx_probersp_pkts++;
-+			else if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data))
-+				|| is_multicast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)))
-+				psta->sta_stats.rx_probersp_bm_pkts++;
-+			else
-+				psta->sta_stats.rx_probersp_uo_pkts++;
-+		}
-+	}
-+
-+	mgt_dispatcher(padapter, precv_frame);
-+
-+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
-+exit:
-+#endif
-+	return _SUCCESS;
-+
-+}
-+
-+sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame)
-+{
-+	u8 bretry, a4_shift;
-+	struct sta_info *psta = NULL;
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
-+	struct security_priv	*psecuritypriv = &adapter->securitypriv;
-+	sint ret = _SUCCESS;
-+
-+	bretry = GetRetry(ptr);
-+	a4_shift = (pattrib->to_fr_ds == 3) ? ETH_ALEN : 0;
-+
-+	/* some address fields are different when using AMSDU */
-+	if (pattrib->qos)
-+		pattrib->amsdu = GetAMsdu(ptr + WLAN_HDR_A3_LEN + a4_shift);
-+	else
-+		pattrib->amsdu = 0;
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(adapter)) {
-+		ret = rtw_mesh_rx_data_validate_hdr(adapter, precv_frame, &psta);
-+		goto pre_validate_status_chk;
-+	} else
-+#endif
-+#ifdef CONFIG_AP_MODE
-+	if (MLME_IS_AP(adapter)) {
-+		ret = rtw_ap_rx_data_validate_hdr(adapter, precv_frame, &psta);
-+		goto pre_validate_status_chk;
-+	} else
-+#endif
-+	if (MLME_IS_STA(adapter)) {
-+		ret = rtw_sta_rx_data_validate_hdr(adapter, precv_frame, &psta);
-+		goto pre_validate_status_chk;
-+	}
-+
-+	switch (pattrib->to_fr_ds) {
-+	case 0:
-+		_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
-+		ret = sta2sta_data_frame(adapter, precv_frame, &psta);
-+		break;
-+
-+	case 1:
-+		_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->dst, GetAddr3Ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->bssid, GetAddr1Ptr(ptr), ETH_ALEN);
-+		ret = sta2ap_data_frame(adapter, precv_frame, &psta);
-+		break;
-+
-+	case 2:
-+		_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->src, GetAddr3Ptr(ptr), ETH_ALEN);
-+		_rtw_memcpy(pattrib->bssid, get_addr2_ptr(ptr), ETH_ALEN);
-+		ret = ap2sta_data_frame(adapter, precv_frame, &psta);
-+		break;
-+
-+	case 3:
-+	default:
-+		/* WDS is not supported */
-+		ret = _FAIL;
-+		break;
-+	}
-+
-+pre_validate_status_chk:
-+
-+	if (ret == _FAIL) {
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" case:%d, res:%d, ra="MAC_FMT", ta="MAC_FMT"\n"
-+			, FUNC_ADPT_ARG(adapter), pattrib->to_fr_ds, ret, MAC_ARG(GetAddr1Ptr(ptr)), MAC_ARG(get_addr2_ptr(ptr)));
-+		#endif
-+		goto exit;
-+	} else if (ret == RTW_RX_HANDLED)
-+		goto exit;
-+
-+
-+	if (psta == NULL) {
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" psta == NULL, ra="MAC_FMT", ta="MAC_FMT"\n"
-+			, FUNC_ADPT_ARG(adapter), MAC_ARG(GetAddr1Ptr(ptr)), MAC_ARG(get_addr2_ptr(ptr)));
-+		#endif
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	precv_frame->u.hdr.psta = psta;
-+	precv_frame->u.hdr.preorder_ctrl = NULL;
-+	pattrib->ack_policy = 0;
-+
-+	/* parsing QC field */
-+	if (pattrib->qos == 1) {
-+		pattrib->priority = GetPriority((ptr + WLAN_HDR_A3_LEN + a4_shift)); /* point to Qos field*/
-+		pattrib->ack_policy = GetAckpolicy((ptr + WLAN_HDR_A3_LEN + a4_shift));
-+		pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN + a4_shift;
-+		if (pattrib->priority != 0 && pattrib->priority != 3)
-+			adapter->recvpriv.is_any_non_be_pkts = _TRUE;
-+		else
-+			adapter->recvpriv.is_any_non_be_pkts = _FALSE;
-+	} else {
-+		pattrib->priority = 0;
-+		pattrib->hdrlen = WLAN_HDR_A3_LEN + a4_shift;
-+	}
-+
-+	if (pattrib->order) /* HT-CTRL 11n */
-+		pattrib->hdrlen += 4;
-+
-+	/* decache, drop duplicate recv packets */
-+	ret = recv_decache(precv_frame);
-+	if (ret  == _FAIL)
-+		goto exit;
-+
-+	if (!IS_MCAST(pattrib->ra)) {
-+
-+		if (pattrib->qos)
-+			precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority];
-+
-+		if (recv_ucast_pn_decache(precv_frame) == _FAIL) {
-+			#ifdef DBG_RX_DROP_FRAME
-+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_ucast_pn_decache return _FAIL for sta="MAC_FMT"\n"
-+				, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));
-+			#endif
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+	} else {
-+		if (recv_bcast_pn_decache(precv_frame) == _FAIL) {
-+			#ifdef DBG_RX_DROP_FRAME
-+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_bcast_pn_decache return _FAIL for sta="MAC_FMT"\n"
-+				, FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));
-+			#endif
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+	}
-+
-+	if (pattrib->privacy) {
-+#ifdef CONFIG_TDLS
-+		if ((psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta->dot118021XPrivacy == _AES_))
-+			pattrib->encrypt = psta->dot118021XPrivacy;
-+		else
-+#endif /* CONFIG_TDLS */
-+			GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, IS_MCAST(pattrib->ra));
-+
-+
-+		SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt);
-+	} else {
-+		pattrib->encrypt = 0;
-+		pattrib->iv_len = pattrib->icv_len = 0;
-+	}
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (!pattrib->amsdu
-+		&& pattrib->mesh_ctrl_present
-+		&& (!pattrib->encrypt || pattrib->bdecrypted))
-+		ret = rtw_mesh_rx_validate_mctrl_non_amsdu(adapter, precv_frame);
-+#endif
-+
-+exit:
-+	return ret;
-+}
-+
-+static inline void dump_rx_packet(u8 *ptr)
-+{
-+	int i;
-+
-+	RTW_INFO("#############################\n");
-+	for (i = 0; i < 64; i = i + 8)
-+		RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr + i),
-+			*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));
-+	RTW_INFO("#############################\n");
-+}
-+
-+sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame);
-+sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
-+{
-+	/* shall check frame subtype, to / from ds, da, bssid */
-+
-+	/* then call check if rx seq/frag. duplicated. */
-+
-+	u8 type;
-+	u8 subtype;
-+	sint retval = _SUCCESS;
-+
-+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
-+	struct recv_priv  *precvpriv = &adapter->recvpriv;
-+
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	u8  ver = (unsigned char)(*ptr) & 0x3 ;
-+#ifdef CONFIG_FIND_BEST_CHANNEL
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+#endif
-+
-+#ifdef CONFIG_TDLS
-+	struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
-+#endif /* CONFIG_TDLS */
-+#ifdef CONFIG_WAPI_SUPPORT
-+	PRT_WAPI_T	pWapiInfo = &adapter->wapiInfo;
-+	struct recv_frame_hdr *phdr = &precv_frame->u.hdr;
-+	u8 wai_pkt = 0;
-+	u16 sc;
-+	u8	external_len = 0;
-+#endif
-+
-+
-+#ifdef CONFIG_FIND_BEST_CHANNEL
-+	if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
-+		int ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, rtw_get_oper_ch(adapter));
-+		if (ch_set_idx >= 0)
-+			rfctl->channel_set[ch_set_idx].rx_count++;
-+	}
-+#endif
-+
-+#ifdef CONFIG_TDLS
-+	if (ptdlsinfo->ch_sensing == 1 && ptdlsinfo->cur_channel != 0)
-+		ptdlsinfo->collect_pkt_num[ptdlsinfo->cur_channel - 1]++;
-+#endif /* CONFIG_TDLS */
-+
-+#ifdef RTK_DMP_PLATFORM
-+	if (0) {
-+		RTW_INFO("++\n");
-+		{
-+			int i;
-+			for (i = 0; i < 64; i = i + 8)
-+				RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:", *(ptr + i),
-+					*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));
-+
-+		}
-+		RTW_INFO("--\n");
-+	}
-+#endif /* RTK_DMP_PLATFORM */
-+
-+	/* add version chk */
-+	if (ver != 0) {
-+		retval = _FAIL;
-+		DBG_COUNTER(adapter->rx_logs.core_rx_pre_ver_err);
-+		goto exit;
-+	}
-+
-+	type =  GetFrameType(ptr);
-+	subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */
-+
-+	pattrib->to_fr_ds = get_tofr_ds(ptr);
-+
-+	pattrib->frag_num = GetFragNum(ptr);
-+	pattrib->seq_num = GetSequence(ptr);
-+
-+	pattrib->pw_save = GetPwrMgt(ptr);
-+	pattrib->mfrag = GetMFrag(ptr);
-+	pattrib->mdata = GetMData(ptr);
-+	pattrib->privacy = GetPrivacy(ptr);
-+	pattrib->order = GetOrder(ptr);
-+#ifdef CONFIG_WAPI_SUPPORT
-+	sc = (pattrib->seq_num << 4) | pattrib->frag_num;
-+#endif
-+
-+#if 1 /* Dump rx packets */
-+	{
-+		u8 bDumpRxPkt = 0;
-+
-+		rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt));
-+		if (bDumpRxPkt == 1) /* dump all rx packets */
-+			dump_rx_packet(ptr);
-+		else if ((bDumpRxPkt == 2) && (type == WIFI_MGT_TYPE))
-+			dump_rx_packet(ptr);
-+		else if ((bDumpRxPkt == 3) && (type == WIFI_DATA_TYPE))
-+			dump_rx_packet(ptr);
-+	}
-+#endif
-+	switch (type) {
-+	case WIFI_MGT_TYPE: /* mgnt */
-+		DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt);
-+		retval = validate_recv_mgnt_frame(adapter, precv_frame);
-+		if (retval == _FAIL) {
-+			DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt_err);
-+		}
-+		retval = _FAIL; /* only data frame return _SUCCESS */
-+		break;
-+	case WIFI_CTRL_TYPE: /* ctrl */
-+		DBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl);
-+		retval = validate_recv_ctrl_frame(adapter, precv_frame);
-+		if (retval == _FAIL) {
-+			DBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl_err);
-+		}
-+		retval = _FAIL; /* only data frame return _SUCCESS */
-+		break;
-+	case WIFI_DATA_TYPE: /* data */
-+		DBG_COUNTER(adapter->rx_logs.core_rx_pre_data);
-+#ifdef CONFIG_WAPI_SUPPORT
-+		if (pattrib->qos)
-+			external_len = 2;
-+		else
-+			external_len = 0;
-+
-+		wai_pkt = rtw_wapi_is_wai_packet(adapter, ptr);
-+
-+		phdr->bIsWaiPacket = wai_pkt;
-+
-+		if (wai_pkt != 0) {
-+			if (sc != adapter->wapiInfo.wapiSeqnumAndFragNum)
-+				adapter->wapiInfo.wapiSeqnumAndFragNum = sc;
-+			else {
-+				retval = _FAIL;
-+				DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_wapi_seq_err);
-+				break;
-+			}
-+		} else {
-+
-+			if (rtw_wapi_drop_for_key_absent(adapter, get_addr2_ptr(ptr))) {
-+				retval = _FAIL;
-+				WAPI_TRACE(WAPI_RX, "drop for key absent for rx\n");
-+				DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_wapi_key_err);
-+				break;
-+			}
-+		}
-+
-+#endif
-+
-+		pattrib->qos = (subtype & BIT(7)) ? 1 : 0;
-+		retval = validate_recv_data_frame(adapter, precv_frame);
-+		if (retval == _FAIL) {
-+			precvpriv->dbg_rx_drop_count++;
-+			DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_err);
-+		} else if (retval == _SUCCESS) {
-+			#ifdef DBG_RX_DUMP_EAP
-+			if (!pattrib->encrypt || pattrib->bdecrypted) {
-+				u8 bDumpRxPkt;
-+				u16 eth_type;
-+
-+				/* dump eapol */
-+				rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt));
-+				/* get ether_type */
-+				_rtw_memcpy(&eth_type, ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + LLC_HEADER_SIZE, 2);
-+				eth_type = ntohs((unsigned short) eth_type);
-+				if ((bDumpRxPkt == 4) && (eth_type == 0x888e))
-+					dump_rx_packet(ptr);
-+			}
-+			#endif
-+		} else
-+			DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_handled);
-+		break;
-+	default:
-+		DBG_COUNTER(adapter->rx_logs.core_rx_pre_unknown);
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fail! type=0x%x\n"
-+			, FUNC_ADPT_ARG(adapter), type);
-+		#endif
-+		retval = _FAIL;
-+		break;
-+	}
-+
-+exit:
-+
-+
-+	return retval;
-+}
-+
-+/* Reture expected handling for LLC */
-+enum rtw_rx_llc_hdl rtw_recv_llc_parse(u8 *msdu, u16 msdu_len)
-+{
-+	u16	eth_type;
-+
-+	if (msdu_len < 8)
-+		return RTW_RX_LLC_KEEP;
-+
-+	eth_type = RTW_GET_BE16(msdu + SNAP_SIZE);
-+
-+	if ((_rtw_memcmp(msdu, rtw_rfc1042_header, SNAP_SIZE)
-+			&& eth_type != ETH_P_AARP && eth_type != ETH_P_IPX)
-+		|| _rtw_memcmp(msdu, rtw_bridge_tunnel_header, SNAP_SIZE)) {
-+		/* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */
-+		return RTW_RX_LLC_REMOVE;
-+	} else {
-+		/* Leave Ethernet header part of hdr and full payload */
-+		return RTW_RX_LLC_KEEP;
-+	}
-+
-+	/* TODO: VLAN tagged */
-+}
-+
-+/* remove the wlanhdr and add the eth_hdr */
-+sint wlanhdr_to_ethhdr(union recv_frame *precvframe, enum rtw_rx_llc_hdl llc_hdl)
-+{
-+	u8	*ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */
-+	struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
-+	sint rmv_len;
-+	u16	eth_type, len;
-+	sint ret = _SUCCESS;
-+
-+	if (pattrib->encrypt)
-+		recvframe_pull_tail(precvframe, pattrib->icv_len);
-+
-+	rmv_len = pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + (llc_hdl ? SNAP_SIZE : 0);
-+	len = precvframe->u.hdr.len - rmv_len;
-+
-+	ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + (llc_hdl ? 2 : 0)));
-+	if (!ptr) {
-+		ret = _FAIL;
-+		goto exiting;
-+	}
-+
-+	_rtw_memcpy(ptr, pattrib->dst, ETH_ALEN);
-+	_rtw_memcpy(ptr + ETH_ALEN, pattrib->src, ETH_ALEN);
-+
-+	if (!llc_hdl) {
-+		len = htons(len);
-+		_rtw_memcpy(ptr + 12, &len, 2);
-+	}
-+
-+	rtw_rframe_set_os_pkt(precvframe);
-+
-+exiting:
-+	return ret;
-+}
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+#ifndef CONFIG_SDIO_RX_COPY
-+#ifdef PLATFORM_LINUX
-+static void recvframe_expand_pkt(
-+	PADAPTER padapter,
-+	union recv_frame *prframe)
-+{
-+	struct recv_frame_hdr *pfhdr;
-+	_pkt *ppkt;
-+	u8 shift_sz;
-+	u32 alloc_sz;
-+	u8 *ptr;
-+
-+
-+	pfhdr = &prframe->u.hdr;
-+
-+	/*	6 is for IP header 8 bytes alignment in QoS packet case. */
-+	if (pfhdr->attrib.qos)
-+		shift_sz = 6;
-+	else
-+		shift_sz = 0;
-+
-+	/* for first fragment packet, need to allocate */
-+	/* (1536 + RXDESC_SIZE + drvinfo_sz) to reassemble packet */
-+	/*	8 is for skb->data 8 bytes alignment.
-+	*	alloc_sz = _RND(1536 + RXDESC_SIZE + pfhdr->attrib.drvinfosize + shift_sz + 8, 128); */
-+	alloc_sz = 1664; /* round (1536 + 24 + 32 + shift_sz + 8) to 128 bytes alignment */
-+
-+	/* 3 1. alloc new skb */
-+	/* prepare extra space for 4 bytes alignment */
-+	ppkt = rtw_skb_alloc(alloc_sz);
-+
-+	if (!ppkt)
-+		return; /* no way to expand */
-+
-+	/* 3 2. Prepare new skb to replace & release old skb */
-+	/* force ppkt->data at 8-byte alignment address */
-+	skb_reserve(ppkt, 8 - ((SIZE_PTR)ppkt->data & 7));
-+	/* force ip_hdr at 8-byte alignment address according to shift_sz */
-+	skb_reserve(ppkt, shift_sz);
-+
-+	/* copy data to new pkt */
-+	ptr = skb_put(ppkt, pfhdr->len);
-+	if (ptr)
-+		_rtw_memcpy(ptr, pfhdr->rx_data, pfhdr->len);
-+
-+	rtw_skb_free(pfhdr->pkt);
-+
-+	/* attach new pkt to recvframe */
-+	pfhdr->pkt = ppkt;
-+	pfhdr->rx_head = ppkt->head;
-+	pfhdr->rx_data = ppkt->data;
-+	pfhdr->rx_tail = skb_tail_pointer(ppkt);
-+	pfhdr->rx_end = skb_end_pointer(ppkt);
-+}
-+#else /*!= PLATFORM_LINUX*/
-+#warning "recvframe_expand_pkt not implement, defrag may crash system"
-+#endif
-+#endif /*#ifndef CONFIG_SDIO_RX_COPY*/
-+#endif
-+
-+/* perform defrag */
-+union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q);
-+union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q)
-+{
-+	_list	*plist, *phead;
-+	u8	*data, wlanhdr_offset;
-+	u8	curfragnum;
-+	struct recv_frame_hdr *pfhdr, *pnfhdr;
-+	union recv_frame *prframe, *pnextrframe;
-+	_queue	*pfree_recv_queue;
-+
-+
-+	curfragnum = 0;
-+	pfree_recv_queue = &adapter->recvpriv.free_recv_queue;
-+
-+	phead = get_list_head(defrag_q);
-+	plist = get_next(phead);
-+	prframe = LIST_CONTAINOR(plist, union recv_frame, u);
-+	pfhdr = &prframe->u.hdr;
-+	rtw_list_delete(&(prframe->u.list));
-+
-+	if (curfragnum != pfhdr->attrib.frag_num) {
-+		/* the first fragment number must be 0 */
-+		/* free the whole queue */
-+		rtw_free_recvframe(prframe, pfree_recv_queue);
-+		rtw_free_recvframe_queue(defrag_q, pfree_recv_queue);
-+
-+		return NULL;
-+	}
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+#ifndef CONFIG_SDIO_RX_COPY
-+	recvframe_expand_pkt(adapter, prframe);
-+#endif
-+#endif
-+
-+	curfragnum++;
-+
-+	plist = get_list_head(defrag_q);
-+
-+	plist = get_next(plist);
-+
-+	data = get_recvframe_data(prframe);
-+
-+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+		pnextrframe = LIST_CONTAINOR(plist, union recv_frame , u);
-+		pnfhdr = &pnextrframe->u.hdr;
-+
-+
-+		/* check the fragment sequence  (2nd ~n fragment frame) */
-+
-+		if (curfragnum != pnfhdr->attrib.frag_num) {
-+			/* the fragment number must be increasing  (after decache) */
-+			/* release the defrag_q & prframe */
-+			rtw_free_recvframe(prframe, pfree_recv_queue);
-+			rtw_free_recvframe_queue(defrag_q, pfree_recv_queue);
-+			return NULL;
-+		}
-+
-+		curfragnum++;
-+
-+		/* copy the 2nd~n fragment frame's payload to the first fragment */
-+		/* get the 2nd~last fragment frame's payload */
-+
-+		wlanhdr_offset = pnfhdr->attrib.hdrlen + pnfhdr->attrib.iv_len;
-+
-+		recvframe_pull(pnextrframe, wlanhdr_offset);
-+
-+		/* append  to first fragment frame's tail (if privacy frame, pull the ICV) */
-+		recvframe_pull_tail(prframe, pfhdr->attrib.icv_len);
-+
-+		/* memcpy */
-+		_rtw_memcpy(pfhdr->rx_tail, pnfhdr->rx_data, pnfhdr->len);
-+
-+		recvframe_put(prframe, pnfhdr->len);
-+
-+		pfhdr->attrib.icv_len = pnfhdr->attrib.icv_len;
-+		plist = get_next(plist);
-+
-+	};
-+
-+	/* free the defrag_q queue and return the prframe */
-+	rtw_free_recvframe_queue(defrag_q, pfree_recv_queue);
-+
-+
-+
-+	return prframe;
-+}
-+
-+/* check if need to defrag, if needed queue the frame to defrag_q */
-+union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame)
-+{
-+	u8	ismfrag;
-+	u8	fragnum;
-+	u8	*psta_addr;
-+	struct recv_frame_hdr *pfhdr;
-+	struct sta_info *psta;
-+	struct sta_priv *pstapriv;
-+	_list *phead;
-+	union recv_frame *prtnframe = NULL;
-+	_queue *pfree_recv_queue, *pdefrag_q = NULL;
-+
-+
-+	pstapriv = &padapter->stapriv;
-+
-+	pfhdr = &precv_frame->u.hdr;
-+
-+	pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
-+
-+	/* need to define struct of wlan header frame ctrl */
-+	ismfrag = pfhdr->attrib.mfrag;
-+	fragnum = pfhdr->attrib.frag_num;
-+
-+	psta_addr = pfhdr->attrib.ta;
-+	psta = rtw_get_stainfo(pstapriv, psta_addr);
-+	if (psta == NULL) {
-+		u8 type = GetFrameType(pfhdr->rx_data);
-+		if (type != WIFI_DATA_TYPE) {
-+			psta = rtw_get_bcmc_stainfo(padapter);
-+			if (psta)
-+				pdefrag_q = &psta->sta_recvpriv.defrag_q;
-+		} else
-+			pdefrag_q = NULL;
-+	} else
-+		pdefrag_q = &psta->sta_recvpriv.defrag_q;
-+
-+	if ((ismfrag == 0) && (fragnum == 0)) {
-+		prtnframe = precv_frame;/* isn't a fragment frame */
-+	}
-+
-+	if (ismfrag == 1) {
-+		/* 0~(n-1) fragment frame */
-+		/* enqueue to defraf_g */
-+		if (pdefrag_q != NULL) {
-+			if (fragnum == 0) {
-+				/* the first fragment */
-+				if (_rtw_queue_empty(pdefrag_q) == _FALSE) {
-+					/* free current defrag_q */
-+					rtw_free_recvframe_queue(pdefrag_q, pfree_recv_queue);
-+				}
-+			}
-+
-+
-+			/* Then enqueue the 0~(n-1) fragment into the defrag_q */
-+
-+			/* _rtw_spinlock(&pdefrag_q->lock); */
-+			phead = get_list_head(pdefrag_q);
-+			rtw_list_insert_tail(&pfhdr->list, phead);
-+			/* _rtw_spinunlock(&pdefrag_q->lock); */
-+
-+
-+			prtnframe = NULL;
-+
-+		} else {
-+			/* can't find this ta's defrag_queue, so free this recv_frame */
-+			rtw_free_recvframe(precv_frame, pfree_recv_queue);
-+			prtnframe = NULL;
-+		}
-+
-+	}
-+
-+	if ((ismfrag == 0) && (fragnum != 0)) {
-+		/* the last fragment frame */
-+		/* enqueue the last fragment */
-+		if (pdefrag_q != NULL) {
-+			/* _rtw_spinlock(&pdefrag_q->lock); */
-+			phead = get_list_head(pdefrag_q);
-+			rtw_list_insert_tail(&pfhdr->list, phead);
-+			/* _rtw_spinunlock(&pdefrag_q->lock); */
-+
-+			/* call recvframe_defrag to defrag */
-+			precv_frame = recvframe_defrag(padapter, pdefrag_q);
-+			prtnframe = precv_frame;
-+
-+		} else {
-+			/* can't find this ta's defrag_queue, so free this recv_frame */
-+			rtw_free_recvframe(precv_frame, pfree_recv_queue);
-+			prtnframe = NULL;
-+		}
-+
-+	}
-+
-+
-+	if ((prtnframe != NULL) && (prtnframe->u.hdr.attrib.privacy)) {
-+		/* after defrag we must check tkip mic code */
-+		if (recvframe_chkmic(padapter,  prtnframe) == _FAIL) {
-+			rtw_free_recvframe(prtnframe, pfree_recv_queue);
-+			prtnframe = NULL;
-+		}
-+	}
-+
-+
-+	return prtnframe;
-+
-+}
-+
-+static int rtw_recv_indicatepkt_check(union recv_frame *rframe, u8 *ehdr_pos, u32 pkt_len)
-+{
-+	_adapter *adapter = rframe->u.hdr.adapter;
-+	struct recv_priv *recvpriv = &adapter->recvpriv;
-+	struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos;
-+	struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib;
-+#ifdef DBG_IP_R_MONITOR
-+	int i;
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_priv	*pmlmepriv = &adapter->mlmepriv;
-+	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
-+#endif/*DBG_IP_R_MONITOR*/
-+	enum eap_type eapol_type;
-+	int ret = _FAIL;
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	if (rtw_wapi_check_for_drop(adapter, rframe, ehdr_pos)) {
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_wapi_check_for_drop\n"
-+			, FUNC_ADPT_ARG(adapter));
-+		#endif
-+		goto exit;
-+	}
-+#endif
-+
-+	if (rframe->u.hdr.psta)
-+		rtw_st_ctl_rx(rframe->u.hdr.psta, ehdr_pos);
-+
-+	if (ntohs(ehdr->h_proto) == 0x888e) {
-+		eapol_type = parsing_eapol_packet(adapter, ehdr_pos + ETH_HLEN, rframe->u.hdr.psta, 0);
-+		if ((eapol_type == EAPOL_1_4 || eapol_type == EAPOL_3_4) && pattrib->encrypt == 0) {
-+			rframe->u.hdr.psta->resp_nonenc_eapol_key_starttime = rtw_get_current_time();
-+			RTW_INFO("Receive unencrypted eapol key\n");
-+		}
-+	}
-+#ifdef DBG_ARP_DUMP
-+	else if (ntohs(ehdr->h_proto) == ETH_P_ARP)
-+		dump_arp_pkt(RTW_DBGDUMP, ehdr->h_dest, ehdr->h_source, ehdr_pos + ETH_HLEN, 0);
-+#endif
-+
-+	if (recvpriv->sink_udpport > 0)
-+		rtw_sink_rtp_seq_dbg(adapter, ehdr_pos);
-+
-+#ifdef DBG_UDP_PKT_LOSE_11AC
-+	#define PAYLOAD_LEN_LOC_OF_IP_HDR 0x10 /*ethernet payload length location of ip header (DA + SA+eth_type+(version&hdr_len)) */
-+
-+	if (ntohs(ehdr->h_proto) == ETH_P_ARP) {
-+		/* ARP Payload length will be 42bytes or 42+18(tailer)=60bytes*/
-+		if (pkt_len != 42 && pkt_len != 60)
-+			RTW_INFO("Error !!%s,ARP Payload length %u not correct\n" , __func__ , pkt_len);
-+	} else if (ntohs(ehdr->h_proto) == ETH_P_IP) {
-+		if (be16_to_cpu(*((u16 *)(ehdr_pos + PAYLOAD_LEN_LOC_OF_IP_HDR))) != (pkt_len) - ETH_HLEN) {
-+			RTW_INFO("Error !!%s,Payload length not correct\n" , __func__);
-+			RTW_INFO("%s, IP header describe Total length=%u\n" , __func__ , be16_to_cpu(*((u16 *)(ehdr_pos + PAYLOAD_LEN_LOC_OF_IP_HDR))));
-+			RTW_INFO("%s, Pkt real length=%u\n" , __func__ , (pkt_len) - ETH_HLEN);
-+		}
-+	}
-+#endif
-+
-+#ifdef DBG_IP_R_MONITOR
-+	#define LEN_ARP_OP_HDR 7 /*ARP OERATION */
-+	if (ntohs(ehdr->h_proto) == ETH_P_ARP) {
-+
-+		if(check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE){
-+			if(ehdr_pos[ETHERNET_HEADER_SIZE+LEN_ARP_OP_HDR] == 2) {
-+
-+				RTW_INFO("%s,[DBG_ARP] Rx ARP RSP Packet;SeqNum = %d !\n",
-+					__FUNCTION__, pattrib->seq_num);
-+
-+				dump_arp_pkt(RTW_DBGDUMP, ehdr->h_dest, ehdr->h_source, ehdr_pos + ETH_HLEN, 0);
-+
-+			}
-+		}
-+	}
-+#endif/*DBG_IP_R_MONITOR*/
-+
-+#ifdef CONFIG_AUTO_AP_MODE
-+	if (ntohs(ehdr->h_proto) == 0x8899)
-+		rtw_auto_ap_rx_msg_dump(adapter, rframe, ehdr_pos);
-+#endif
-+
-+	ret = _SUCCESS;
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+exit:
-+#endif
-+	return ret;
-+}
-+
-+#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
-+static void recv_free_fwd_resource(_adapter *adapter, struct xmit_frame *fwd_frame, _list *b2u_list)
-+{
-+	struct xmit_priv *xmitpriv = &adapter->xmitpriv;
-+
-+	if (fwd_frame)
-+		rtw_free_xmitframe(xmitpriv, fwd_frame);
-+
-+#if CONFIG_RTW_DATA_BMC_TO_UC
-+	if (!rtw_is_list_empty(b2u_list)) {
-+		struct xmit_frame *b2uframe;
-+		_list *list;
-+
-+		list = get_next(b2u_list);
-+		while (rtw_end_of_queue_search(b2u_list, list) == _FALSE) {
-+			b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);
-+			list = get_next(list);
-+			rtw_list_delete(&b2uframe->list);
-+			rtw_free_xmitframe(xmitpriv, b2uframe);
-+		}
-+	}
-+#endif
-+}
-+
-+static void recv_fwd_pkt_hdl(_adapter *adapter, _pkt *pkt
-+	, u8 act, struct xmit_frame *fwd_frame, _list *b2u_list)
-+{
-+	struct xmit_priv *xmitpriv = &adapter->xmitpriv;
-+	_pkt *fwd_pkt = pkt;
-+
-+	if (act & RTW_RX_MSDU_ACT_INDICATE) {
-+		fwd_pkt = rtw_os_pkt_copy(pkt);
-+		if (!fwd_pkt) {
-+			#ifdef DBG_TX_DROP_FRAME
-+			RTW_INFO("DBG_TX_DROP_FRAME %s rtw_os_pkt_copy fail\n", __func__);
-+			#endif
-+			recv_free_fwd_resource(adapter, fwd_frame, b2u_list);
-+			goto exit;
-+		}
-+	}
-+
-+#if CONFIG_RTW_DATA_BMC_TO_UC
-+	if (!rtw_is_list_empty(b2u_list)) {
-+		_list *list = get_next(b2u_list);
-+		struct xmit_frame *b2uframe;
-+
-+		while (rtw_end_of_queue_search(b2u_list, list) == _FALSE) {
-+			b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);
-+			list = get_next(list);
-+			rtw_list_delete(&b2uframe->list);
-+
-+			if (!fwd_frame && rtw_is_list_empty(b2u_list)) /* the last fwd_pkt */
-+				b2uframe->pkt = fwd_pkt;
-+			else
-+				b2uframe->pkt = rtw_os_pkt_copy(fwd_pkt);
-+			if (!b2uframe->pkt) {
-+				rtw_free_xmitframe(xmitpriv, b2uframe);
-+				continue;
-+			}
-+
-+			rtw_xmit_posthandle(adapter, b2uframe, b2uframe->pkt);
-+		}
-+	}
-+#endif
-+
-+	if (fwd_frame) {
-+		fwd_frame->pkt = fwd_pkt;
-+		if (rtw_xmit_posthandle(adapter, fwd_frame, fwd_pkt) < 0) {
-+			#ifdef DBG_TX_DROP_FRAME
-+			RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit_posthandle fail\n", __func__);
-+			#endif
-+			xmitpriv->tx_drop++;
-+		}
-+	}
-+
-+exit:
-+	return;
-+}
-+#endif /* defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) */
-+
-+int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe)
-+{
-+	struct rx_pkt_attrib *rattrib = &prframe->u.hdr.attrib;
-+	int	a_len, padding_len;
-+	u16	nSubframe_Length;
-+	u8	nr_subframes, i;
-+	u8	*pdata;
-+	_pkt *sub_pkt, *subframes[MAX_SUBFRAME_COUNT];
-+	struct recv_priv *precvpriv = &padapter->recvpriv;
-+	_queue *pfree_recv_queue = &(precvpriv->free_recv_queue);
-+	const u8 *da, *sa;
-+	int act;
-+#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
-+	struct xmit_frame *fwd_frame;
-+	_list b2u_list;
-+#endif
-+	enum rtw_rx_llc_hdl llc_hdl;
-+	u8 mctrl_len = 0;
-+	int	ret = _SUCCESS;
-+
-+	nr_subframes = 0;
-+
-+	recvframe_pull(prframe, rattrib->hdrlen);
-+
-+	if (rattrib->iv_len > 0)
-+		recvframe_pull(prframe, rattrib->iv_len);
-+	if (rattrib->encrypt)
-+		recvframe_pull_tail(prframe, rattrib->icv_len);
-+
-+	a_len = prframe->u.hdr.len;
-+	pdata = prframe->u.hdr.rx_data;
-+
-+	while (a_len > ETH_HLEN) {
-+		/* Offset 12 denote 2 mac address */
-+		nSubframe_Length = RTW_GET_BE16(pdata + 12);
-+		if (a_len < (ETHERNET_HEADER_SIZE + nSubframe_Length)) {
-+			RTW_INFO("nRemain_Length is %d and nSubframe_Length is : %d\n", a_len, nSubframe_Length);
-+			break;
-+		}
-+
-+		act = RTW_RX_MSDU_ACT_INDICATE;
-+		#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
-+		fwd_frame = NULL;
-+		#endif
-+
-+		#ifdef CONFIG_RTW_MESH
-+		if (MLME_IS_MESH(padapter)) {
-+			u8 *mda = pdata, *msa = pdata + ETH_ALEN;
-+			struct rtw_ieee80211s_hdr *mctrl = (struct rtw_ieee80211s_hdr *)(pdata + ETH_HLEN);
-+			int v_ret;
-+
-+			v_ret = rtw_mesh_rx_data_validate_mctrl(padapter, prframe
-+				, mctrl, mda, msa, &mctrl_len, &da, &sa);
-+			if (v_ret != _SUCCESS)
-+				goto move_to_next;
-+
-+			llc_hdl = rtw_recv_llc_parse(pdata + ETH_HLEN + mctrl_len, nSubframe_Length - mctrl_len);
-+			act = rtw_mesh_rx_msdu_act_check(prframe
-+				, mda, msa, da, sa, mctrl
-+				, pdata + ETH_HLEN + mctrl_len, llc_hdl
-+				, &fwd_frame, &b2u_list);
-+		} else
-+		#endif
-+		{
-+			da = pdata;
-+			sa = pdata + ETH_ALEN;
-+			llc_hdl = rtw_recv_llc_parse(pdata + ETH_HLEN, nSubframe_Length);
-+			#ifdef CONFIG_AP_MODE
-+			if (MLME_IS_AP(padapter)) {
-+				act = rtw_ap_rx_msdu_act_check(prframe, da, sa
-+					, pdata + ETH_HLEN, llc_hdl, &fwd_frame, &b2u_list);
-+			} else
-+			#endif
-+			if (MLME_IS_STA(padapter))
-+				act = rtw_sta_rx_amsdu_act_check(prframe, da, sa);
-+		}
-+
-+		if (!act)
-+			goto move_to_next;
-+
-+		rtw_led_rx_control(padapter, da);
-+
-+		sub_pkt = rtw_os_alloc_msdu_pkt(prframe, da, sa
-+			, pdata + ETH_HLEN + mctrl_len, nSubframe_Length - mctrl_len, llc_hdl);
-+		if (sub_pkt == NULL) {
-+			if (act & RTW_RX_MSDU_ACT_INDICATE) {
-+				#ifdef DBG_RX_DROP_FRAME
-+				RTW_INFO("DBG_RX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\n", __func__);
-+				#endif
-+			}
-+			#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
-+			if (act & RTW_RX_MSDU_ACT_FORWARD) {
-+				#ifdef DBG_TX_DROP_FRAME
-+				RTW_INFO("DBG_TX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\n", __func__);
-+				#endif
-+				recv_free_fwd_resource(padapter, fwd_frame, &b2u_list);
-+			}
-+			#endif
-+			break;
-+		}
-+
-+		#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
-+		if (act & RTW_RX_MSDU_ACT_FORWARD) {
-+			recv_fwd_pkt_hdl(padapter, sub_pkt, act, fwd_frame, &b2u_list);
-+			if (!(act & RTW_RX_MSDU_ACT_INDICATE))
-+				goto move_to_next;
-+		}
-+		#endif
-+
-+		if (rtw_recv_indicatepkt_check(prframe, rtw_os_pkt_data(sub_pkt), rtw_os_pkt_len(sub_pkt)) == _SUCCESS)
-+			subframes[nr_subframes++] = sub_pkt;
-+		else
-+			rtw_os_pkt_free(sub_pkt);
-+
-+move_to_next:
-+		/* move the data point to data content */
-+		pdata += ETH_HLEN;
-+		a_len -= ETH_HLEN;
-+
-+		if (nr_subframes >= MAX_SUBFRAME_COUNT) {
-+			RTW_WARN("ParseSubframe(): Too many Subframes! Packets dropped!\n");
-+			break;
-+		}
-+
-+		pdata += nSubframe_Length;
-+		a_len -= nSubframe_Length;
-+		if (a_len != 0) {
-+			padding_len = 4 - ((nSubframe_Length + ETH_HLEN) & (4 - 1));
-+			if (padding_len == 4)
-+				padding_len = 0;
-+
-+			if (a_len < padding_len) {
-+				RTW_INFO("ParseSubframe(): a_len < padding_len !\n");
-+				break;
-+			}
-+			pdata += padding_len;
-+			a_len -= padding_len;
-+		}
-+	}
-+
-+	for (i = 0; i < nr_subframes; i++) {
-+		sub_pkt = subframes[i];
-+
-+		/* Indicat the packets to upper layer */
-+		if (sub_pkt)
-+			rtw_os_recv_indicate_pkt(padapter, sub_pkt, prframe);
-+	}
-+
-+	prframe->u.hdr.len = 0;
-+	rtw_free_recvframe(prframe, pfree_recv_queue);/* free this recv_frame */
-+
-+	return ret;
-+}
-+
-+static int recv_process_mpdu(_adapter *padapter, union recv_frame *prframe)
-+{
-+	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
-+	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
-+	int ret;
-+
-+	if (pattrib->amsdu) {
-+		ret = amsdu_to_msdu(padapter, prframe);
-+		if (ret != _SUCCESS) {
-+			#ifdef DBG_RX_DROP_FRAME
-+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" amsdu_to_msdu fail\n"
-+				, FUNC_ADPT_ARG(padapter));
-+			#endif
-+			rtw_free_recvframe(prframe, pfree_recv_queue);
-+			goto exit;
-+		}
-+	} else {
-+		u8 *msdu = get_recvframe_data(prframe)
-+			+ pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib);
-+		u16 msdu_len = prframe->u.hdr.len
-+			- pattrib->hdrlen - pattrib->iv_len - RATTRIB_GET_MCTRL_LEN(pattrib)
-+			- (pattrib->encrypt ? pattrib->icv_len : 0);
-+		enum rtw_rx_llc_hdl llc_hdl = rtw_recv_llc_parse(msdu, msdu_len);
-+		int act = RTW_RX_MSDU_ACT_INDICATE;
-+
-+		#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
-+		struct xmit_frame *fwd_frame = NULL;
-+		_list b2u_list;
-+
-+		#ifdef CONFIG_RTW_MESH
-+		if (MLME_IS_MESH(padapter)) {
-+			if (pattrib->mesh_ctrl_present)
-+				act = rtw_mesh_rx_msdu_act_check(prframe
-+					, pattrib->mda, pattrib->msa
-+					, pattrib->dst, pattrib->src
-+					, (struct rtw_ieee80211s_hdr *)(msdu - RATTRIB_GET_MCTRL_LEN(pattrib))
-+					, msdu, llc_hdl
-+					, &fwd_frame, &b2u_list);
-+		} else
-+		#endif
-+		if (MLME_IS_AP(padapter))
-+			act = rtw_ap_rx_msdu_act_check(prframe, pattrib->dst, pattrib->src
-+					, msdu, llc_hdl, &fwd_frame, &b2u_list);
-+		#endif
-+
-+		#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
-+		if (!act) {
-+			rtw_free_recvframe(prframe, pfree_recv_queue);
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+		#endif
-+
-+		rtw_led_rx_control(padapter, pattrib->dst);
-+
-+		ret = wlanhdr_to_ethhdr(prframe, llc_hdl);
-+		if (ret != _SUCCESS) {
-+			if (act & RTW_RX_MSDU_ACT_INDICATE) {
-+				#ifdef DBG_RX_DROP_FRAME
-+				RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" wlanhdr_to_ethhdr: drop pkt\n"
-+					, FUNC_ADPT_ARG(padapter));
-+				#endif
-+			}
-+			#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
-+			if (act & RTW_RX_MSDU_ACT_FORWARD) {
-+				#ifdef DBG_TX_DROP_FRAME
-+				RTW_INFO("DBG_TX_DROP_FRAME %s wlanhdr_to_ethhdr fail\n", __func__);
-+				#endif
-+				recv_free_fwd_resource(padapter, fwd_frame, &b2u_list);
-+			}
-+			#endif
-+			rtw_free_recvframe(prframe, pfree_recv_queue);
-+			goto exit;
-+		}
-+
-+		#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
-+		if (act & RTW_RX_MSDU_ACT_FORWARD) {
-+			recv_fwd_pkt_hdl(padapter, prframe->u.hdr.pkt, act, fwd_frame, &b2u_list);
-+			if (!(act & RTW_RX_MSDU_ACT_INDICATE)) {
-+				prframe->u.hdr.pkt = NULL;
-+				rtw_free_recvframe(prframe, pfree_recv_queue);
-+				goto exit;
-+			}
-+		}
-+		#endif
-+
-+		if (!RTW_CANNOT_RUN(padapter)) {
-+			ret = rtw_recv_indicatepkt_check(prframe
-+				, get_recvframe_data(prframe), get_recvframe_len(prframe));
-+			if (ret != _SUCCESS) {
-+				rtw_free_recvframe(prframe, pfree_recv_queue);
-+				goto exit;
-+			}
-+
-+			/* indicate this recv_frame */
-+			ret = rtw_recv_indicatepkt(padapter, prframe);
-+			if (ret != _SUCCESS) {
-+				#ifdef DBG_RX_DROP_FRAME
-+				RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_recv_indicatepkt fail!\n"
-+					, FUNC_ADPT_ARG(padapter));
-+				#endif
-+				goto exit;
-+			}
-+		} else {
-+			#ifdef DBG_RX_DROP_FRAME
-+			RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DS:%u SR:%u\n"
-+				, FUNC_ADPT_ARG(padapter)
-+				, rtw_is_drv_stopped(padapter)
-+				, rtw_is_surprise_removed(padapter));
-+			#endif
-+			ret = _SUCCESS; /* don't count as packet drop */
-+			rtw_free_recvframe(prframe, pfree_recv_queue);
-+		}
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
-+static int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num)
-+{
-+	PADAPTER padapter = preorder_ctrl->padapter;
-+	struct recv_priv  *precvpriv = &padapter->recvpriv;
-+	u8	wsize = preorder_ctrl->wsize_b;
-+	u16	wend;
-+
-+	/* Rx Reorder initialize condition. */
-+	if (preorder_ctrl->indicate_seq == 0xFFFF) {
-+		preorder_ctrl->indicate_seq = seq_num;
-+		#ifdef DBG_RX_SEQ
-+		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_INIT indicate_seq:%d, seq_num:%d\n"
-+			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
-+		#endif
-+	}
-+	wend = (preorder_ctrl->indicate_seq + wsize - 1) & 0xFFF; /* % 4096; */
-+
-+	/* Drop out the packet which SeqNum is smaller than WinStart */
-+	if (SN_LESS(seq_num, preorder_ctrl->indicate_seq)) {
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO(FUNC_ADPT_FMT" tid:%u indicate_seq:%d > seq_num:%d\n"
-+			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
-+		#endif
-+		return _FALSE;
-+	}
-+
-+	/*
-+	* Sliding window manipulation. Conditions includes:
-+	* 1. Incoming SeqNum is equal to WinStart =>Window shift 1
-+	* 2. Incoming SeqNum is larger than the WinEnd => Window shift N
-+	*/
-+	if (SN_EQUAL(seq_num, preorder_ctrl->indicate_seq)) {
-+		preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF;
-+		#ifdef DBG_RX_SEQ
-+		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_EQUAL indicate_seq:%d, seq_num:%d\n"
-+			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
-+		#endif
-+
-+	} else if (SN_LESS(wend, seq_num)) {
-+		/* boundary situation, when seq_num cross 0xFFF */
-+		if (seq_num >= (wsize - 1))
-+			preorder_ctrl->indicate_seq = seq_num + 1 - wsize;
-+		else
-+			preorder_ctrl->indicate_seq = 0xFFF - (wsize - (seq_num + 1)) + 1;
-+
-+		precvpriv->dbg_rx_ampdu_window_shift_cnt++;
-+		#ifdef DBG_RX_SEQ
-+		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_LESS(wend, seq_num) indicate_seq:%d, seq_num:%d\n"
-+			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
-+		#endif
-+	}
-+
-+	return _TRUE;
-+}
-+
-+static int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe)
-+{
-+	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
-+	_queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
-+	_list	*phead, *plist;
-+	union recv_frame *pnextrframe;
-+	struct rx_pkt_attrib *pnextattrib;
-+
-+	/* DbgPrint("+enqueue_reorder_recvframe()\n"); */
-+
-+	/* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */
-+	/* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */
-+
-+
-+	phead = get_list_head(ppending_recvframe_queue);
-+	plist = get_next(phead);
-+
-+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+		pnextrframe = LIST_CONTAINOR(plist, union recv_frame, u);
-+		pnextattrib = &pnextrframe->u.hdr.attrib;
-+
-+		if (SN_LESS(pnextattrib->seq_num, pattrib->seq_num))
-+			plist = get_next(plist);
-+		else if (SN_EQUAL(pnextattrib->seq_num, pattrib->seq_num)) {
-+			/* Duplicate entry is found!! Do not insert current entry. */
-+
-+			/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
-+
-+			return _FALSE;
-+		} else
-+			break;
-+
-+		/* DbgPrint("enqueue_reorder_recvframe():while\n"); */
-+
-+	}
-+
-+
-+	/* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */
-+	/* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */
-+
-+	rtw_list_delete(&(prframe->u.hdr.list));
-+
-+	rtw_list_insert_tail(&(prframe->u.hdr.list), plist);
-+
-+	/* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */
-+	/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
-+
-+
-+	return _TRUE;
-+
-+}
-+
-+static void recv_indicatepkts_pkt_loss_cnt(_adapter *padapter, u64 prev_seq, u64 current_seq)
-+{
-+	struct recv_priv *precvpriv = &padapter->recvpriv;
-+
-+	if (current_seq < prev_seq) {
-+		precvpriv->dbg_rx_ampdu_loss_count += (4096 + current_seq - prev_seq);
-+		precvpriv->rx_drop += (4096 + current_seq - prev_seq);
-+	} else {
-+		precvpriv->dbg_rx_ampdu_loss_count += (current_seq - prev_seq);
-+		precvpriv->rx_drop += (current_seq - prev_seq);
-+	}
-+}
-+
-+static int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced)
-+{
-+	/* _irqL irql; */
-+	_list	*phead, *plist;
-+	union recv_frame *prframe;
-+	struct rx_pkt_attrib *pattrib;
-+	/* u8 index = 0; */
-+	int bPktInBuf = _FALSE;
-+	struct recv_priv *precvpriv = &padapter->recvpriv;
-+	_queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
-+
-+	DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_in_oder);
-+
-+	/* DbgPrint("+recv_indicatepkts_in_order\n"); */
-+
-+	/* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */
-+	/* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */
-+
-+	phead =	get_list_head(ppending_recvframe_queue);
-+	plist = get_next(phead);
-+
-+#if 0
-+	/* Check if there is any other indication thread running. */
-+	if (pTS->RxIndicateState == RXTS_INDICATE_PROCESSING)
-+		return;
-+#endif
-+
-+	/* Handling some condition for forced indicate case. */
-+	if (bforced == _TRUE) {
-+		precvpriv->dbg_rx_ampdu_forced_indicate_count++;
-+		if (rtw_is_list_empty(phead)) {
-+			/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
-+			/* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */
-+			return _TRUE;
-+		}
-+
-+		prframe = LIST_CONTAINOR(plist, union recv_frame, u);
-+		pattrib = &prframe->u.hdr.attrib;
-+
-+		#ifdef DBG_RX_SEQ
-+		RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u FORCE indicate_seq:%d, seq_num:%d\n"
-+			, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pattrib->seq_num);
-+		#endif
-+		recv_indicatepkts_pkt_loss_cnt(padapter, preorder_ctrl->indicate_seq, pattrib->seq_num);
-+		preorder_ctrl->indicate_seq = pattrib->seq_num;
-+	}
-+
-+	/* Prepare indication list and indication. */
-+	/* Check if there is any packet need indicate. */
-+	while (!rtw_is_list_empty(phead)) {
-+
-+		prframe = LIST_CONTAINOR(plist, union recv_frame, u);
-+		pattrib = &prframe->u.hdr.attrib;
-+
-+		if (!SN_LESS(preorder_ctrl->indicate_seq, pattrib->seq_num)) {
-+
-+#if 0
-+			/* This protect buffer from overflow. */
-+			if (index >= REORDER_WIN_SIZE) {
-+				RT_ASSERT(FALSE, ("IndicateRxReorderList(): Buffer overflow!!\n"));
-+				bPktInBuf = TRUE;
-+				break;
-+			}
-+#endif
-+
-+			plist = get_next(plist);
-+			rtw_list_delete(&(prframe->u.hdr.list));
-+
-+			if (SN_EQUAL(preorder_ctrl->indicate_seq, pattrib->seq_num)) {
-+				preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF;
-+				#ifdef DBG_RX_SEQ
-+				RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_EQUAL indicate_seq:%d, seq_num:%d\n"
-+					, FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pattrib->seq_num);
-+				#endif
-+			}
-+
-+#if 0
-+			index++;
-+			if (index == 1) {
-+				/* Cancel previous pending timer. */
-+				/* PlatformCancelTimer(Adapter, &pTS->RxPktPendingTimer); */
-+				if (bforced != _TRUE) {
-+					/* RTW_INFO("_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);\n"); */
-+					_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
-+				}
-+			}
-+#endif
-+
-+			/* Set this as a lock to make sure that only one thread is indicating packet. */
-+			/* pTS->RxIndicateState = RXTS_INDICATE_PROCESSING; */
-+
-+			/* Indicate packets */
-+			/* RT_ASSERT((index<=REORDER_WIN_SIZE), ("RxReorderIndicatePacket(): Rx Reorder buffer full!!\n")); */
-+
-+
-+			/* indicate this recv_frame */
-+			/* DbgPrint("recv_indicatepkts_in_order, indicate_seq=%d, seq_num=%d\n", precvpriv->indicate_seq, pattrib->seq_num); */
-+			if (recv_process_mpdu(padapter, prframe) != _SUCCESS)
-+				precvpriv->dbg_rx_drop_count++;
-+
-+			/* Update local variables. */
-+			bPktInBuf = _FALSE;
-+
-+		} else {
-+			bPktInBuf = _TRUE;
-+			break;
-+		}
-+
-+		/* DbgPrint("recv_indicatepkts_in_order():while\n"); */
-+
-+	}
-+
-+	/* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */
-+	/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
-+
-+#if 0
-+	/* Release the indication lock and set to new indication step. */
-+	if (bPktInBuf) {
-+		/*  Set new pending timer. */
-+		/* pTS->RxIndicateState = RXTS_INDICATE_REORDER; */
-+		/* PlatformSetTimer(Adapter, &pTS->RxPktPendingTimer, pHTInfo->RxReorderPendingTime); */
-+
-+		_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);
-+	} else {
-+		/* pTS->RxIndicateState = RXTS_INDICATE_IDLE; */
-+	}
-+#endif
-+	/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
-+
-+	/* return _TRUE; */
-+	return bPktInBuf;
-+
-+}
-+
-+static int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe)
-+{
-+	_irqL irql;
-+	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
-+	struct recv_reorder_ctrl *preorder_ctrl = prframe->u.hdr.preorder_ctrl;
-+	_queue *ppending_recvframe_queue = preorder_ctrl ? &preorder_ctrl->pending_recvframe_queue : NULL;
-+	struct recv_priv  *precvpriv = &padapter->recvpriv;
-+
-+	if (!pattrib->qos || !preorder_ctrl || preorder_ctrl->enable == _FALSE)
-+		goto _success_exit;
-+
-+
-+	DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_reoder);
-+
-+	_enter_critical_bh(&ppending_recvframe_queue->lock, &irql);
-+
-+
-+	if(rtw_test_and_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack))
-+		preorder_ctrl->indicate_seq = 0xFFFF;
-+	#ifdef DBG_RX_SEQ
-+	RTW_INFO("DBG_RX_SEQ %s:preorder_ctrl->rec_abba_rsp_ack = %u,indicate_seq = %d\n"
-+		, __func__
-+		, preorder_ctrl->rec_abba_rsp_ack
-+		, preorder_ctrl->indicate_seq);
-+	#endif
-+
-+	/* s2. check if winstart_b(indicate_seq) needs to been updated */
-+	if (!check_indicate_seq(preorder_ctrl, pattrib->seq_num)) {
-+		precvpriv->dbg_rx_ampdu_drop_count++;
-+		/* pHTInfo->RxReorderDropCounter++; */
-+		/* ReturnRFDList(Adapter, pRfd); */
-+		/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
-+		/* return _FAIL; */
-+
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" check_indicate_seq fail\n"
-+			, FUNC_ADPT_ARG(padapter));
-+		#endif
-+#if 0
-+		rtw_recv_indicatepkt(padapter, prframe);
-+
-+		_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
-+
-+		goto _success_exit;
-+#else
-+		goto _err_exit;
-+#endif
-+	}
-+
-+
-+	/* s3. Insert all packet into Reorder Queue to maintain its ordering. */
-+	if (!enqueue_reorder_recvframe(preorder_ctrl, prframe)) {
-+		/* DbgPrint("recv_indicatepkt_reorder, enqueue_reorder_recvframe fail!\n"); */
-+		/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
-+		/* return _FAIL; */
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" enqueue_reorder_recvframe fail\n"
-+			, FUNC_ADPT_ARG(padapter));
-+		#endif
-+		goto _err_exit;
-+	}
-+
-+
-+	/* s4. */
-+	/* Indication process. */
-+	/* After Packet dropping and Sliding Window shifting as above, we can now just indicate the packets */
-+	/* with the SeqNum smaller than latest WinStart and buffer other packets. */
-+	/*  */
-+	/* For Rx Reorder condition: */
-+	/* 1. All packets with SeqNum smaller than WinStart => Indicate */
-+	/* 2. All packets with SeqNum larger than or equal to WinStart => Buffer it. */
-+	/*  */
-+
-+	/* recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE); */
-+	if (recv_indicatepkts_in_order(padapter, preorder_ctrl, _FALSE) == _TRUE) {
-+		if (!preorder_ctrl->bReorderWaiting) {
-+			preorder_ctrl->bReorderWaiting = _TRUE;
-+			_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);
-+		}
-+		_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
-+	} else {
-+		preorder_ctrl->bReorderWaiting = _FALSE;
-+		_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
-+		_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
-+	}
-+
-+	return RTW_RX_HANDLED;
-+
-+_success_exit:
-+
-+	return _SUCCESS;
-+
-+_err_exit:
-+
-+	_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
-+
-+	return _FAIL;
-+}
-+
-+
-+void rtw_reordering_ctrl_timeout_handler(void *pcontext)
-+{
-+	_irqL irql;
-+	struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)pcontext;
-+	_adapter *padapter = NULL;
-+	_queue *ppending_recvframe_queue = NULL;
-+
-+
-+	if (preorder_ctrl == NULL)
-+		return;
-+
-+	padapter = preorder_ctrl->padapter;
-+	if (RTW_CANNOT_RUN(padapter))
-+		return;
-+
-+	ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
-+
-+	/* RTW_INFO("+rtw_reordering_ctrl_timeout_handler()=>\n"); */
-+
-+	_enter_critical_bh(&ppending_recvframe_queue->lock, &irql);
-+
-+	preorder_ctrl->bReorderWaiting = _FALSE;
-+
-+	if (recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE) == _TRUE)
-+		_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME);
-+
-+	_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
-+
-+}
-+#endif /* defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) */
-+
-+static void recv_set_iseq_before_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller)
-+{
-+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
-+	struct recv_reorder_ctrl *reorder_ctrl = rframe->u.hdr.preorder_ctrl;
-+
-+	if (reorder_ctrl) {
-+		reorder_ctrl->indicate_seq = seq_num;
-+		#ifdef DBG_RX_SEQ
-+		RTW_INFO("DBG_RX_SEQ %s("ADPT_FMT")-B tid:%u indicate_seq:%d, seq_num:%d\n"
-+			, caller, ADPT_ARG(reorder_ctrl->padapter)
-+			, reorder_ctrl->tid, reorder_ctrl->indicate_seq, seq_num);
-+		#endif
-+	}
-+#endif
-+}
-+
-+static void recv_set_iseq_after_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller)
-+{
-+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
-+	struct recv_reorder_ctrl *reorder_ctrl = rframe->u.hdr.preorder_ctrl;
-+
-+	if (reorder_ctrl) {
-+		reorder_ctrl->indicate_seq = (reorder_ctrl->indicate_seq + 1) % 4096;
-+		#ifdef DBG_RX_SEQ
-+		RTW_INFO("DBG_RX_SEQ %s("ADPT_FMT")-A tid:%u indicate_seq:%d, seq_num:%d\n"
-+			, caller, ADPT_ARG(reorder_ctrl->padapter)
-+			, reorder_ctrl->tid, reorder_ctrl->indicate_seq, seq_num);
-+		#endif
-+	}
-+#endif
-+}
-+
-+#ifdef CONFIG_MP_INCLUDED
-+int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
-+{
-+	int ret = _SUCCESS;
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	u8 type, subtype;
-+	struct mp_priv *pmppriv = &adapter->mppriv;
-+	struct mp_tx		*pmptx;
-+	unsigned char	*sa , *da, *bs;
-+	struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
-+	u32 i = 0;
-+	u8 rtk_prefix[]={0x52, 0x65, 0x61, 0x6C, 0x4C, 0x6F, 0x76, 0x65, 0x54, 0x65, 0x6B};
-+	u8 *prx_data;
-+	pmptx = &pmppriv->tx;
-+
-+
-+	if (pmppriv->mplink_brx == _FALSE) {
-+
-+		u8 bDumpRxPkt = 0;
-+		type =  GetFrameType(ptr);
-+		subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2)	 */
-+
-+		RTW_DBG("hdr len = %d iv_len=%d \n", pattrib->hdrlen , pattrib->iv_len);
-+		prx_data = ptr + pattrib->hdrlen + pattrib->iv_len;
-+
-+		for (i = 0; i < precv_frame->u.hdr.len; i++) {
-+			if (precv_frame->u.hdr.len < (11 + i))
-+				break;
-+
-+			if (_rtw_memcmp(prx_data + i, (void *)&rtk_prefix, 11) == _FALSE) {
-+				bDumpRxPkt = 0;
-+				RTW_DBG("prx_data = %02X != rtk_prefix[%d] = %02X \n", *(prx_data + i), i , rtk_prefix[i]);
-+				} else {
-+				bDumpRxPkt = 1;
-+				RTW_DBG("prx_data = %02X = rtk_prefix[%d] = %02X \n", *(prx_data + i), i , rtk_prefix[i]);
-+				break;
-+				}
-+		}
-+
-+		if (bDumpRxPkt == 1) { /* dump all rx packets */
-+			int i;
-+			RTW_INFO("############ type:0x%02x subtype:0x%02x #################\n", type, subtype);
-+
-+			for (i = 0; i < precv_frame->u.hdr.len; i = i + 8)
-+				RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr + i),
-+					*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));
-+				RTW_INFO("#############################\n");
-+				_rtw_memset(pmppriv->mplink_buf, '\0' , sizeof(pmppriv->mplink_buf));
-+				_rtw_memcpy(pmppriv->mplink_buf, ptr, precv_frame->u.hdr.len);
-+				pmppriv->mplink_rx_len = precv_frame->u.hdr.len;
-+				pmppriv->mplink_brx =_TRUE;
-+		}
-+	}
-+	if (pmppriv->bloopback) {
-+		if (_rtw_memcmp(ptr + 24, pmptx->buf + 24, precv_frame->u.hdr.len - 24) == _FALSE) {
-+			RTW_INFO("Compare payload content Fail !!!\n");
-+			ret = _FAIL;
-+		}
-+	}
-+ 	if (pmppriv->bSetRxBssid == _TRUE) {
-+
-+		sa = get_addr2_ptr(ptr);
-+		da = GetAddr1Ptr(ptr);
-+		bs = GetAddr3Ptr(ptr);
-+		type =	GetFrameType(ptr);
-+		subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2)  */
-+
-+		if (_rtw_memcmp(bs, adapter->mppriv.network_macaddr, ETH_ALEN) == _FALSE)
-+			ret = _FAIL;
-+
-+		RTW_DBG("############ type:0x%02x subtype:0x%02x #################\n", type, subtype);
-+		RTW_DBG("A2 sa %02X:%02X:%02X:%02X:%02X:%02X \n", *(sa) , *(sa + 1), *(sa+ 2), *(sa + 3), *(sa + 4), *(sa + 5));
-+		RTW_DBG("A1 da %02X:%02X:%02X:%02X:%02X:%02X \n", *(da) , *(da + 1), *(da+ 2), *(da + 3), *(da + 4), *(da + 5));
-+		RTW_DBG("A3 bs %02X:%02X:%02X:%02X:%02X:%02X \n --------------------------\n", *(bs) , *(bs + 1), *(bs+ 2), *(bs + 3), *(bs + 4), *(bs + 5));
-+	}
-+
-+	if (!adapter->mppriv.bmac_filter)
-+		return ret;
-+
-+	if (_rtw_memcmp(get_addr2_ptr(ptr), adapter->mppriv.mac_filter, ETH_ALEN) == _FALSE)
-+		ret = _FAIL;
-+
-+	return ret;
-+}
-+
-+static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe)
-+{
-+	sint	rmv_len;
-+	u16 len;
-+	u8 mcastheadermac[] = {0x01, 0x00, 0x5e};
-+	sint ret = _SUCCESS;
-+	_adapter			*adapter = precvframe->u.hdr.adapter;
-+
-+	u8	*ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */
-+	struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
-+	enum rtw_rx_llc_hdl llc_hdl;
-+
-+
-+	if (pattrib->encrypt)
-+		recvframe_pull_tail(precvframe, pattrib->icv_len);
-+
-+	llc_hdl = rtw_recv_llc_parse(ptr + pattrib->hdrlen + pattrib->iv_len
-+				, precvframe->u.hdr.len - pattrib->hdrlen - pattrib->iv_len);
-+
-+	rmv_len = pattrib->hdrlen + pattrib->iv_len + (llc_hdl ? SNAP_SIZE : 0);
-+	len = precvframe->u.hdr.len - rmv_len;
-+
-+	ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + (llc_hdl ? 2 : 0)));
-+
-+	_rtw_memcpy(ptr, pattrib->dst, ETH_ALEN);
-+	_rtw_memcpy(ptr + ETH_ALEN, pattrib->src, ETH_ALEN);
-+
-+	if (!llc_hdl) {
-+		len = htons(len);
-+		_rtw_memcpy(ptr + 12, &len, 2);
-+	}
-+
-+
-+	len = htons(pattrib->seq_num);
-+	/* RTW_INFO("wlan seq = %d ,seq_num =%x\n",len,pattrib->seq_num); */
-+	_rtw_memcpy(ptr + 12, &len, 2);
-+	if (adapter->mppriv.bRTWSmbCfg == _TRUE) {
-+		/* if(_rtw_memcmp(mcastheadermac, pattrib->dst, 3) == _TRUE) */ /* SimpleConfig Dest. */
-+		/*			_rtw_memcpy(ptr+ETH_ALEN, pattrib->bssid, ETH_ALEN); */
-+
-+		if (_rtw_memcmp(mcastheadermac, pattrib->bssid, 3) == _TRUE) /* SimpleConfig Dest. */
-+			_rtw_memcpy(ptr, pattrib->bssid, ETH_ALEN);
-+
-+	}
-+
-+
-+	return ret;
-+
-+}
-+
-+
-+int mp_recv_frame(_adapter *padapter, union recv_frame *rframe)
-+{
-+	int ret = _SUCCESS;
-+	struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib;
-+	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
-+#ifdef CONFIG_MP_INCLUDED
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct mp_priv *pmppriv = &padapter->mppriv;
-+#endif /* CONFIG_MP_INCLUDED */
-+	u8 type;
-+	u8 *ptr = rframe->u.hdr.rx_data;
-+	u8 *psa, *pda, *pbssid;
-+	struct sta_info *psta = NULL;
-+	DBG_COUNTER(padapter->rx_logs.core_rx_pre);
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) { /* &&(padapter->mppriv.check_mp_pkt == 0)) */
-+		if (pattrib->crc_err == 1)
-+			padapter->mppriv.rx_crcerrpktcount++;
-+		else {
-+			if (_SUCCESS == validate_mp_recv_frame(padapter, rframe))
-+				padapter->mppriv.rx_pktcount++;
-+			else
-+				padapter->mppriv.rx_pktcount_filter_out++;
-+		}
-+
-+		if (pmppriv->rx_bindicatePkt == _FALSE) {
-+			ret = _FAIL;
-+			rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
-+			goto exit;
-+		} else {
-+			type =	GetFrameType(ptr);
-+			pattrib->to_fr_ds = get_tofr_ds(ptr);
-+			pattrib->frag_num = GetFragNum(ptr);
-+			pattrib->seq_num = GetSequence(ptr);
-+			pattrib->pw_save = GetPwrMgt(ptr);
-+			pattrib->mfrag = GetMFrag(ptr);
-+			pattrib->mdata = GetMData(ptr);
-+			pattrib->privacy = GetPrivacy(ptr);
-+			pattrib->order = GetOrder(ptr);
-+
-+			if (type == WIFI_DATA_TYPE) {
-+				pda = get_da(ptr);
-+				psa = get_sa(ptr);
-+				pbssid = get_hdr_bssid(ptr);
-+
-+				_rtw_memcpy(pattrib->dst, pda, ETH_ALEN);
-+				_rtw_memcpy(pattrib->src, psa, ETH_ALEN);
-+				_rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN);
-+
-+				switch (pattrib->to_fr_ds) {
-+				case 0:
-+					_rtw_memcpy(pattrib->ra, pda, ETH_ALEN);
-+					_rtw_memcpy(pattrib->ta, psa, ETH_ALEN);
-+					ret = sta2sta_data_frame(padapter, rframe, &psta);
-+					break;
-+				case 1:
-+					_rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN);
-+					_rtw_memcpy(pattrib->ta, psa, ETH_ALEN);
-+					ret = sta2ap_data_frame(padapter, rframe, &psta);
-+					break;
-+				case 2:
-+					_rtw_memcpy(pattrib->ra, pda, ETH_ALEN);
-+					_rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN);
-+					ret = ap2sta_data_frame(padapter, rframe, &psta);
-+					break;
-+				case 3:
-+					_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
-+					_rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
-+					ret = _FAIL;
-+					break;
-+				default:
-+					ret = _FAIL;
-+					break;
-+				}
-+
-+				if (ret != _SUCCESS) {
-+#ifdef DBG_RX_DROP_FRAME
-+					RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" 2_data_frame fail: drop pkt\n"
-+															, FUNC_ADPT_ARG(padapter));
-+#endif
-+					ret = _FAIL;
-+					goto exit;
-+				}
-+
-+				ret = MPwlanhdr_to_ethhdr(rframe);
-+
-+				if (ret != _SUCCESS) {
-+					#ifdef DBG_RX_DROP_FRAME
-+					RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" wlanhdr_to_ethhdr: drop pkt\n"
-+						, FUNC_ADPT_ARG(padapter));
-+					#endif
-+					ret = _FAIL;
-+					goto exit;
-+				}
-+				if (!RTW_CANNOT_RUN(padapter)) {
-+					/* indicate this recv_frame */
-+					ret = rtw_recv_indicatepkt(padapter, rframe);
-+					if (ret != _SUCCESS) {
-+						#ifdef DBG_RX_DROP_FRAME
-+						RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_recv_indicatepkt fail!\n"
-+							, FUNC_ADPT_ARG(padapter));
-+						#endif
-+						ret = _FAIL;
-+						goto exit;
-+					}
-+				} else {
-+					#ifdef DBG_RX_DROP_FRAME
-+					RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" bDriverStopped(%s) OR bSurpriseRemoved(%s)\n"
-+						, FUNC_ADPT_ARG(padapter)
-+						, rtw_is_drv_stopped(padapter) ? "True" : "False"
-+						, rtw_is_surprise_removed(padapter) ? "True" : "False");
-+					#endif
-+					ret = _FAIL;
-+					goto exit;
-+				}
-+
-+			}
-+		}
-+	}
-+exit:
-+	rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
-+	ret = _FAIL;
-+	return ret;
-+
-+}
-+#endif
-+
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
-+int recv_frame_monitor(_adapter *padapter, union recv_frame *rframe)
-+{
-+	int ret = _SUCCESS;
-+	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
-+
-+#ifdef CONFIG_WIFI_MONITOR
-+	struct net_device *ndev = padapter->pnetdev;
-+	_pkt *pskb = NULL;
-+
-+	if (rframe == NULL)
-+		goto exit;
-+
-+	/* read skb information from recv frame */
-+	pskb = rframe->u.hdr.pkt;
-+	pskb->len = rframe->u.hdr.len;
-+	pskb->data = rframe->u.hdr.rx_data;
-+	skb_set_tail_pointer(pskb, rframe->u.hdr.len);
-+
-+	if (ndev->type == ARPHRD_IEEE80211_RADIOTAP) {
-+		/* fill radiotap header */
-+		if (rtw_fill_radiotap_hdr(padapter, &rframe->u.hdr.attrib, (u8 *)pskb) == _FAIL) {
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+	}
-+
-+	/* write skb information to recv frame */
-+	skb_reset_mac_header(pskb);
-+	rframe->u.hdr.len = pskb->len;
-+	rframe->u.hdr.rx_data = pskb->data;
-+	rframe->u.hdr.rx_head = pskb->head;
-+	rframe->u.hdr.rx_tail = skb_tail_pointer(pskb);
-+	rframe->u.hdr.rx_end = skb_end_pointer(pskb);
-+
-+	if (!RTW_CANNOT_RUN(padapter)) {
-+		/* indicate this recv_frame */
-+		ret = rtw_recv_monitor(padapter, rframe);
-+	} else 
-+		ret = _FAIL;
-+
-+exit:
-+#endif /* CONFIG_WIFI_MONITOR */
-+
-+	if (rframe) /* free this recv_frame */
-+		rtw_free_recvframe(rframe, pfree_recv_queue);
-+
-+	return ret;
-+}
-+#endif
-+int recv_func_prehandle(_adapter *padapter, union recv_frame *rframe)
-+{
-+	int ret = _SUCCESS;
-+#ifdef DBG_RX_COUNTER_DUMP
-+	struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib;
-+#endif
-+	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
-+
-+#ifdef DBG_RX_COUNTER_DUMP
-+	if (padapter->dump_rx_cnt_mode & DUMP_DRV_RX_COUNTER) {
-+		if (pattrib->crc_err == 1)
-+			padapter->drv_rx_cnt_crcerror++;
-+		else
-+			padapter->drv_rx_cnt_ok++;
-+	}
-+#endif
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	if (padapter->registrypriv.mp_mode == 1 || padapter->mppriv.bRTWSmbCfg == _TRUE) {
-+		mp_recv_frame(padapter, rframe);
-+		ret = _FAIL;
-+		goto exit;
-+	} else
-+#endif
-+	{
-+		/* check the frame crtl field and decache */
-+		ret = validate_recv_frame(padapter, rframe);
-+		if (ret != _SUCCESS) {
-+			rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
-+			goto exit;
-+		}
-+	}
-+exit:
-+	return ret;
-+}
-+
-+/*#define DBG_RX_BMC_FRAME*/
-+int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe)
-+{
-+	int ret = _SUCCESS;
-+	union recv_frame *orig_prframe = prframe;
-+	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
-+	struct recv_priv *precvpriv = &padapter->recvpriv;
-+	_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
-+#ifdef CONFIG_TDLS
-+	u8 *psnap_type, *pcategory;
-+#endif /* CONFIG_TDLS */
-+
-+	DBG_COUNTER(padapter->rx_logs.core_rx_post);
-+
-+	prframe = decryptor(padapter, prframe);
-+	if (prframe == NULL) {
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" decryptor: drop pkt\n"
-+			, FUNC_ADPT_ARG(padapter));
-+		#endif
-+		ret = _FAIL;
-+		DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_err);
-+		goto _recv_data_drop;
-+	}
-+
-+#ifdef DBG_RX_BMC_FRAME
-+	if (IS_MCAST(pattrib->ra))
-+		RTW_INFO("%s =>"ADPT_FMT" Rx BC/MC from "MAC_FMT"\n", __func__, ADPT_ARG(padapter), MAC_ARG(pattrib->ta));
-+#endif
-+
-+#if 0
-+	if (is_primary_adapter(padapter)) {
-+		RTW_INFO("+++\n");
-+		{
-+			int i;
-+			u8	*ptr = get_recvframe_data(prframe);
-+			for (i = 0; i < 140; i = i + 8)
-+				RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:", *(ptr + i),
-+					*(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7));
-+
-+		}
-+		RTW_INFO("---\n");
-+	}
-+#endif
-+
-+#ifdef CONFIG_TDLS
-+	/* check TDLS frame */
-+	psnap_type = get_recvframe_data(orig_prframe) + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE;
-+	pcategory = psnap_type + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
-+
-+	if ((_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, ETH_TYPE_LEN)) &&
-+	    ((*pcategory == RTW_WLAN_CATEGORY_TDLS) || (*pcategory == RTW_WLAN_CATEGORY_P2P))) {
-+		ret = OnTDLS(padapter, prframe);
-+		if (ret == _FAIL)
-+			goto _exit_recv_func;
-+	}
-+#endif /* CONFIG_TDLS */
-+
-+	prframe = recvframe_chk_defrag(padapter, prframe);
-+	if (prframe == NULL)	{
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recvframe_chk_defrag: drop pkt\n"
-+			, FUNC_ADPT_ARG(padapter));
-+		#endif
-+		DBG_COUNTER(padapter->rx_logs.core_rx_post_defrag_err);
-+		goto _recv_data_drop;
-+	}
-+
-+	prframe = portctrl(padapter, prframe);
-+	if (prframe == NULL) {
-+		#ifdef DBG_RX_DROP_FRAME
-+		RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" portctrl: drop pkt\n"
-+			, FUNC_ADPT_ARG(padapter));
-+		#endif
-+		ret = _FAIL;
-+		DBG_COUNTER(padapter->rx_logs.core_rx_post_portctrl_err);
-+		goto _recv_data_drop;
-+	}
-+
-+	count_rx_stats(padapter, prframe, NULL);
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	rtw_wapi_update_info(padapter, prframe);
-+#endif
-+
-+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
-+	/* including perform A-MPDU Rx Ordering Buffer Control */
-+	ret = recv_indicatepkt_reorder(padapter, prframe);
-+	if (ret == _FAIL) {
-+		rtw_free_recvframe(orig_prframe, pfree_recv_queue);
-+		goto _recv_data_drop;
-+	} else if (ret == RTW_RX_HANDLED) /* queued OR indicated in order */
-+		goto _exit_recv_func;
-+#endif
-+
-+	recv_set_iseq_before_mpdu_process(prframe, pattrib->seq_num, __func__);
-+	ret = recv_process_mpdu(padapter, prframe);
-+	recv_set_iseq_after_mpdu_process(prframe, pattrib->seq_num, __func__);
-+	if (ret == _FAIL)
-+		goto _recv_data_drop;
-+
-+_exit_recv_func:
-+	return ret;
-+
-+_recv_data_drop:
-+	precvpriv->dbg_rx_drop_count++;
-+	return ret;
-+}
-+
-+int recv_func(_adapter *padapter, union recv_frame *rframe)
-+{
-+	int ret;
-+	struct rx_pkt_attrib *prxattrib = &rframe->u.hdr.attrib;
-+	struct recv_priv *recvpriv = &padapter->recvpriv;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
-+	u8 *ptr = rframe->u.hdr.rx_data;
-+#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
-+	u8 type;
-+#endif
-+
-+	if (check_fwstate(mlmepriv, WIFI_MONITOR_STATE) 
-+#ifdef RTW_SIMPLE_CONFIG
-+		|| (check_fwstate(mlmepriv, WIFI_AP_STATE) && padapter->rtw_simple_config == _TRUE && IS_MCAST(get_ra(ptr)))
-+#endif
-+		) {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
-+		recv_frame_monitor(padapter, rframe);
-+#endif
-+		ret = _SUCCESS;
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
-+	type = GetFrameType(ptr);
-+	if ((type == WIFI_DATA_TYPE)&& check_fwstate(mlmepriv, WIFI_STATION_STATE)) {
-+		struct wlan_network *cur_network = &(mlmepriv->cur_network);
-+		if ( _rtw_memcmp(get_addr2_ptr(ptr), cur_network->network.MacAddress, ETH_ALEN)==0) {
-+			recv_frame_monitor(padapter, rframe);
-+			ret = _SUCCESS;
-+			goto exit;
-+		}
-+	}
-+#endif
-+		/* check if need to handle uc_swdec_pending_queue*/
-+		if (check_fwstate(mlmepriv, WIFI_STATION_STATE) && psecuritypriv->busetkipkey) {
-+			union recv_frame *pending_frame;
-+			int cnt = 0;
-+
-+			while ((pending_frame = rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue))) {
-+				cnt++;
-+				DBG_COUNTER(padapter->rx_logs.core_rx_dequeue);
-+				recv_func_posthandle(padapter, pending_frame);
-+			}
-+
-+			if (cnt)
-+				RTW_INFO(FUNC_ADPT_FMT" dequeue %d from uc_swdec_pending_queue\n",
-+					 FUNC_ADPT_ARG(padapter), cnt);
-+		}
-+
-+	DBG_COUNTER(padapter->rx_logs.core_rx);
-+	ret = recv_func_prehandle(padapter, rframe);
-+
-+	if (ret == _SUCCESS) {
-+
-+		/* check if need to enqueue into uc_swdec_pending_queue*/
-+		if (check_fwstate(mlmepriv, WIFI_STATION_STATE) &&
-+		    !IS_MCAST(prxattrib->ra) && prxattrib->encrypt > 0 &&
-+		    (prxattrib->bdecrypted == 0 || psecuritypriv->sw_decrypt == _TRUE) &&
-+		    psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK &&
-+		    !psecuritypriv->busetkipkey) {
-+			DBG_COUNTER(padapter->rx_logs.core_rx_enqueue);
-+			rtw_enqueue_recvframe(rframe, &padapter->recvpriv.uc_swdec_pending_queue);
-+			/* RTW_INFO("%s: no key, enqueue uc_swdec_pending_queue\n", __func__); */
-+
-+			if (recvpriv->free_recvframe_cnt < NR_RECVFRAME / 4) {
-+				/* to prevent from recvframe starvation, get recvframe from uc_swdec_pending_queue to free_recvframe_cnt */
-+				rframe = rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue);
-+				if (rframe)
-+					goto do_posthandle;
-+			}
-+			goto exit;
-+		}
-+
-+do_posthandle:
-+		ret = recv_func_posthandle(padapter, rframe);
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+
-+s32 rtw_recv_entry(union recv_frame *precvframe)
-+{
-+	_adapter *padapter;
-+	struct recv_priv *precvpriv;
-+	s32 ret = _SUCCESS;
-+
-+
-+
-+	padapter = precvframe->u.hdr.adapter;
-+
-+	precvpriv = &padapter->recvpriv;
-+
-+
-+	ret = recv_func(padapter, precvframe);
-+	if (ret == _FAIL) {
-+		goto _recv_entry_drop;
-+	}
-+
-+
-+	precvpriv->rx_pkts++;
-+
-+
-+	return ret;
-+
-+_recv_entry_drop:
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	if (padapter->registrypriv.mp_mode == 1)
-+		padapter->mppriv.rx_pktloss = precvpriv->rx_drop;
-+#endif
-+
-+
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+static void rtw_signal_stat_timer_hdl(void *ctx)
-+{
-+	_adapter *adapter = (_adapter *)ctx;
-+	struct recv_priv *recvpriv = &adapter->recvpriv;
-+
-+	u32 tmp_s, tmp_q;
-+	u8 avg_signal_strength = 0;
-+	u8 avg_signal_qual = 0;
-+	u32 num_signal_strength = 0;
-+	u32 num_signal_qual = 0;
-+	u8 ratio_pre_stat = 0, ratio_curr_stat = 0, ratio_total = 0, ratio_profile = SIGNAL_STAT_CALC_PROFILE_0;
-+
-+	if (adapter->recvpriv.is_signal_dbg) {
-+		/* update the user specific value, signal_strength_dbg, to signal_strength, rssi */
-+		adapter->recvpriv.signal_strength = adapter->recvpriv.signal_strength_dbg;
-+		adapter->recvpriv.rssi = (s8)translate_percentage_to_dbm((u8)adapter->recvpriv.signal_strength_dbg);
-+	} else {
-+
-+		if (recvpriv->signal_strength_data.update_req == 0) { /* update_req is clear, means we got rx */
-+			avg_signal_strength = recvpriv->signal_strength_data.avg_val;
-+			num_signal_strength = recvpriv->signal_strength_data.total_num;
-+			/* after avg_vals are accquired, we can re-stat the signal values */
-+			recvpriv->signal_strength_data.update_req = 1;
-+		}
-+
-+		if (recvpriv->signal_qual_data.update_req == 0) { /* update_req is clear, means we got rx */
-+			avg_signal_qual = recvpriv->signal_qual_data.avg_val;
-+			num_signal_qual = recvpriv->signal_qual_data.total_num;
-+			/* after avg_vals are accquired, we can re-stat the signal values */
-+			recvpriv->signal_qual_data.update_req = 1;
-+		}
-+
-+		if (num_signal_strength == 0) {
-+			if (rtw_get_on_cur_ch_time(adapter) == 0
-+			    || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 2 * adapter->mlmeextpriv.mlmext_info.bcn_interval
-+			   )
-+				goto set_timer;
-+		}
-+
-+		if (check_fwstate(&adapter->mlmepriv, WIFI_UNDER_SURVEY) == _TRUE
-+		    || check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _FALSE
-+		   )
-+			goto set_timer;
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_buddy_check_fwstate(adapter, WIFI_UNDER_SURVEY) == _TRUE)
-+			goto set_timer;
-+#endif
-+		if (adapter->registrypriv.mp_mode == 1)
-+			ratio_profile = SIGNAL_STAT_CALC_PROFILE_2;
-+		else if (RTW_SIGNAL_STATE_CALC_PROFILE < SIGNAL_STAT_CALC_PROFILE_MAX)
-+			ratio_profile = RTW_SIGNAL_STATE_CALC_PROFILE;
-+
-+		ratio_pre_stat = signal_stat_calc_profile[ratio_profile][0];
-+		ratio_curr_stat = signal_stat_calc_profile[ratio_profile][1];
-+		ratio_total = ratio_pre_stat + ratio_curr_stat;
-+
-+		/* update value of signal_strength, rssi, signal_qual */
-+		tmp_s = (ratio_curr_stat * avg_signal_strength + ratio_pre_stat * recvpriv->signal_strength);
-+		if (tmp_s % ratio_total)
-+			tmp_s = tmp_s / ratio_total + 1;
-+		else
-+			tmp_s = tmp_s / ratio_total;
-+		if (tmp_s > 100)
-+			tmp_s = 100;
-+
-+		tmp_q = (ratio_curr_stat * avg_signal_qual + ratio_pre_stat * recvpriv->signal_qual);
-+		if (tmp_q % ratio_total)
-+			tmp_q = tmp_q / ratio_total + 1;
-+		else
-+			tmp_q = tmp_q / ratio_total;
-+		if (tmp_q > 100)
-+			tmp_q = 100;
-+
-+		recvpriv->signal_strength = tmp_s;
-+		recvpriv->rssi = (s8)translate_percentage_to_dbm(tmp_s);
-+		recvpriv->signal_qual = tmp_q;
-+
-+#if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1
-+		RTW_INFO(FUNC_ADPT_FMT" signal_strength:%3u, rssi:%3d, signal_qual:%3u"
-+			 ", num_signal_strength:%u, num_signal_qual:%u"
-+			 ", on_cur_ch_ms:%d"
-+			 "\n"
-+			 , FUNC_ADPT_ARG(adapter)
-+			 , recvpriv->signal_strength
-+			 , recvpriv->rssi
-+			 , recvpriv->signal_qual
-+			 , num_signal_strength, num_signal_qual
-+			, rtw_get_on_cur_ch_time(adapter) ? rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) : 0
-+			);
-+#endif
-+	}
-+
-+set_timer:
-+	rtw_set_signal_stat_timer(recvpriv);
-+
-+}
-+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+
-+static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe)
-+{
-+	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+	struct signal_stat *signal_stat = &padapter->recvpriv.signal_strength_data;
-+#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+	u32 last_rssi, tmp_val;
-+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+
-+	/* RTW_INFO("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->recv_signal_power,pattrib->signal_strength); */
-+	/* if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) */
-+	{
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+		if (signal_stat->update_req) {
-+			signal_stat->total_num = 0;
-+			signal_stat->total_val = 0;
-+			signal_stat->update_req = 0;
-+		}
-+
-+		signal_stat->total_num++;
-+		signal_stat->total_val  += pattrib->phy_info.signal_strength;
-+		signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
-+#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+
-+		/* Adapter->RxStats.RssiCalculateCnt++;	 */ /* For antenna Test */
-+		if (padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX) {
-+			padapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX;
-+			last_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index];
-+			padapter->recvpriv.signal_strength_data.total_val -= last_rssi;
-+		}
-+		padapter->recvpriv.signal_strength_data.total_val  += pattrib->phy_info.signal_strength;
-+
-+		padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.signal_strength;
-+		if (padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX)
-+			padapter->recvpriv.signal_strength_data.index = 0;
-+
-+
-+		tmp_val = padapter->recvpriv.signal_strength_data.total_val / padapter->recvpriv.signal_strength_data.total_num;
-+
-+		if (padapter->recvpriv.is_signal_dbg) {
-+			padapter->recvpriv.signal_strength = padapter->recvpriv.signal_strength_dbg;
-+			padapter->recvpriv.rssi = (s8)translate_percentage_to_dbm(padapter->recvpriv.signal_strength_dbg);
-+		} else {
-+			padapter->recvpriv.signal_strength = tmp_val;
-+			padapter->recvpriv.rssi = (s8)translate_percentage_to_dbm(tmp_val);
-+		}
-+
-+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+	}
-+}
-+
-+static void rx_process_link_qual(_adapter *padapter, union recv_frame *prframe)
-+{
-+	struct rx_pkt_attrib *pattrib;
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+	struct signal_stat *signal_stat;
-+#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+	u32 last_evm = 0, tmpVal;
-+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+
-+	if (prframe == NULL || padapter == NULL)
-+		return;
-+
-+	pattrib = &prframe->u.hdr.attrib;
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+	signal_stat = &padapter->recvpriv.signal_qual_data;
-+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+
-+	/* RTW_INFO("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual); */
-+
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+	if (signal_stat->update_req) {
-+		signal_stat->total_num = 0;
-+		signal_stat->total_val = 0;
-+		signal_stat->update_req = 0;
-+	}
-+
-+	signal_stat->total_num++;
-+	signal_stat->total_val  += pattrib->phy_info.signal_quality;
-+	signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
-+
-+#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+	if (pattrib->phy_info.signal_quality != 0) {
-+		/*  */
-+		/* 1. Record the general EVM to the sliding window. */
-+		/*  */
-+		if (padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) {
-+			padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;
-+			last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];
-+			padapter->recvpriv.signal_qual_data.total_val -= last_evm;
-+		}
-+		padapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.signal_quality;
-+
-+		padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.signal_quality;
-+		if (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)
-+			padapter->recvpriv.signal_qual_data.index = 0;
-+
-+
-+		/* <1> Showed on UI for user, in percentage. */
-+		tmpVal = padapter->recvpriv.signal_qual_data.total_val / padapter->recvpriv.signal_qual_data.total_num;
-+		padapter->recvpriv.signal_qual = (u8)tmpVal;
-+
-+	}
-+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+}
-+
-+void rx_process_phy_info(_adapter *padapter, union recv_frame *rframe)
-+{
-+	/* Check RSSI */
-+	rx_process_rssi(padapter, rframe);
-+
-+	/* Check PWDB */
-+	/* process_PWDB(padapter, rframe); */
-+
-+	/* UpdateRxSignalStatistics8192C(Adapter, pRfd); */
-+
-+	/* Check EVM */
-+	rx_process_link_qual(padapter, rframe);
-+	rtw_store_phy_info(padapter, rframe);
-+}
-+
-+void rx_query_phy_status(
-+	union recv_frame	*precvframe,
-+	u8 *pphy_status)
-+{
-+	PADAPTER			padapter = precvframe->u.hdr.adapter;
-+	struct rx_pkt_attrib	*pattrib = &precvframe->u.hdr.attrib;
-+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
-+	struct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info;
-+	u8					*wlanhdr;
-+	struct phydm_perpkt_info_struct pkt_info;
-+	u8 *ta, *ra;
-+	u8 is_ra_bmc;
-+	struct sta_priv *pstapriv;
-+	struct sta_info *psta = NULL;
-+	struct recv_priv  *precvpriv = &padapter->recvpriv;
-+	/* _irqL		irqL; */
-+
-+	pkt_info.is_packet_match_bssid = _FALSE;
-+	pkt_info.is_packet_to_self = _FALSE;
-+	pkt_info.is_packet_beacon = _FALSE;
-+	pkt_info.ppdu_cnt = pattrib->ppdu_cnt;
-+	pkt_info.station_id = 0xFF;
-+
-+	wlanhdr = get_recvframe_data(precvframe);
-+
-+	ta = get_ta(wlanhdr);
-+	ra = get_ra(wlanhdr);
-+	is_ra_bmc = IS_MCAST(ra);
-+
-+	if (_rtw_memcmp(adapter_mac_addr(padapter), ta, ETH_ALEN) == _TRUE) {
-+		static systime start_time = 0;
-+
-+#if 0 /*For debug */
-+		if (IsFrameTypeCtrl(wlanhdr)) {
-+			RTW_INFO("-->Control frame: Y\n");
-+			RTW_INFO("-->pkt_len: %d\n", pattrib->pkt_len);
-+			RTW_INFO("-->Sub Type = 0x%X\n", get_frame_sub_type(wlanhdr));
-+		}
-+
-+		/* Dump first 40 bytes of header */
-+		int i = 0;
-+
-+		for (i = 0; i < 40; i++)
-+			RTW_INFO("%d: %X\n", i, *((u8 *)wlanhdr + i));
-+
-+		RTW_INFO("\n");
-+#endif
-+
-+		if ((start_time == 0) || (rtw_get_passing_time_ms(start_time) > 5000)) {
-+			RTW_PRINT("Warning!!! %s: Confilc mac addr!!\n", __func__);
-+			start_time = rtw_get_current_time();
-+		}
-+		precvpriv->dbg_rx_conflic_mac_addr_cnt++;
-+	} else {
-+		pstapriv = &padapter->stapriv;
-+		psta = rtw_get_stainfo(pstapriv, ta);
-+		if (psta)
-+			pkt_info.station_id = psta->cmn.mac_id;
-+	}
-+
-+	pkt_info.is_packet_match_bssid = (!IsFrameTypeCtrl(wlanhdr))
-+		&& (!pattrib->icv_err) && (!pattrib->crc_err)
-+		&& ((!MLME_IS_MESH(padapter) && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN))
-+			|| (MLME_IS_MESH(padapter) && psta));
-+
-+	pkt_info.is_to_self = (!pattrib->icv_err) && (!pattrib->crc_err)
-+		&& _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN);
-+
-+	pkt_info.is_packet_to_self = pkt_info.is_packet_match_bssid
-+		&& _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN);
-+
-+	pkt_info.is_packet_beacon = pkt_info.is_packet_match_bssid
-+				 && (get_frame_sub_type(wlanhdr) == WIFI_BEACON);
-+
-+	if (psta && IsFrameTypeData(wlanhdr)
-+		&& !(get_frame_sub_type(wlanhdr) & BIT(6)) /* don't count NULL data */
-+	) {
-+		if (is_ra_bmc)
-+			psta->curr_rx_rate_bmc = pattrib->data_rate;
-+		else
-+			psta->curr_rx_rate = pattrib->data_rate;
-+	}
-+	pkt_info.data_rate = pattrib->data_rate;
-+
-+	odm_phy_status_query(&pHalData->odmpriv, p_phy_info, pphy_status, &pkt_info);
-+
-+	/* If bw is initial value, get from phy status */
-+	if (pattrib->bw == CHANNEL_WIDTH_MAX)
-+		pattrib->bw = p_phy_info->band_width;
-+
-+	if (p_phy_info->physts_rpt_valid == _TRUE) {
-+		precvframe->u.hdr.psta = NULL;
-+		if (padapter->registrypriv.mp_mode != 1) {
-+			if ((!MLME_IS_MESH(padapter) && pkt_info.is_packet_match_bssid)
-+				|| (MLME_IS_MESH(padapter) && psta)) {
-+				if (psta) {
-+					precvframe->u.hdr.psta = psta;
-+					rx_process_phy_info(padapter, precvframe);
-+				}
-+			} else if (pkt_info.is_packet_to_self || pkt_info.is_packet_beacon) {
-+				if (psta)
-+					precvframe->u.hdr.psta = psta;
-+				rx_process_phy_info(padapter, precvframe);
-+			}
-+		} else {
-+#ifdef CONFIG_MP_INCLUDED
-+			if (padapter->mppriv.brx_filter_beacon == _TRUE) {
-+				if (pkt_info.is_packet_beacon) {
-+					RTW_INFO("in MP Rx is_packet_beacon\n");
-+					if (psta)
-+						precvframe->u.hdr.psta = psta;
-+					rx_process_phy_info(padapter, precvframe);
-+				}
-+			} else
-+#endif
-+			{
-+					if (psta)
-+						precvframe->u.hdr.psta = psta;
-+					rx_process_phy_info(padapter, precvframe);
-+			}
-+		}
-+	}
-+
-+	rtw_odm_parse_rx_phy_status_chinfo(precvframe, pphy_status);
-+}
-+/*
-+* Increase and check if the continual_no_rx_packet of this @param pmlmepriv is larger than MAX_CONTINUAL_NORXPACKET_COUNT
-+* @return _TRUE:
-+* @return _FALSE:
-+*/
-+int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index)
-+{
-+
-+	int ret = _FALSE;
-+	int value = ATOMIC_INC_RETURN(&sta->continual_no_rx_packet[tid_index]);
-+
-+	if (value >= MAX_CONTINUAL_NORXPACKET_COUNT)
-+		ret = _TRUE;
-+
-+	return ret;
-+}
-+
-+/*
-+* Set the continual_no_rx_packet of this @param pmlmepriv to 0
-+*/
-+void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index)
-+{
-+	ATOMIC_SET(&sta->continual_no_rx_packet[tid_index], 0);
-+}
-+
-+u8 adapter_allow_bmc_data_rx(_adapter *adapter)
-+{
-+	if (check_fwstate(&adapter->mlmepriv, WIFI_MONITOR_STATE | WIFI_MP_STATE) == _TRUE)
-+		return 1;
-+
-+#ifdef RTW_SIMPLE_CONFIG
-+	/* allow AP to receive multicast packet for RtwSimpleConfigV4 */
-+	if (MLME_IS_AP(adapter) && adapter->rtw_simple_config)
-+		return 1;
-+#endif
-+
-+	if (MLME_IS_AP(adapter))
-+		return 0;
-+
-+	if (rtw_linked_check(adapter) == _FALSE)
-+		return 0;
-+
-+	return 1;
-+}
-+
-+s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status)
-+{
-+	s32 ret = _SUCCESS;
-+	u8 *pbuf = precvframe->u.hdr.rx_data;
-+	u8 *ra = get_ra(pbuf);
-+	u8 ra_is_bmc = IS_MCAST(ra);
-+	bool phy_queried = 0;
-+	_adapter *primary_padapter = precvframe->u.hdr.adapter;
-+	_adapter *iface = NULL;
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	if (rtw_mp_mode_check(primary_padapter))
-+		goto query_phy_status;
-+#endif
-+#ifdef CONFIG_WIFI_MONITOR
-+	if (MLME_IS_MONITOR(primary_padapter))
-+		goto query_phy_status;
-+#endif
-+
-+	if (ra_is_bmc == _FALSE) {
-+		/* UC frame */
-+		iface = rtw_get_iface_by_macddr(primary_padapter , ra);
-+		if (!iface) {
-+			#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+			if (_rtw_memcmp(ra, adapter_pno_mac_addr(primary_padapter), ETH_ALEN))
-+				goto query_phy_status;
-+			#endif
-+
-+			#ifdef CONFIG_RTW_MULTI_AP
-+			/* unasoc STA RCPI */
-+			if (rtw_unassoc_sta_src_chk(primary_padapter, UNASOC_STA_SRC_RX_NMY_UC)) {
-+				if (pphy_status) {
-+					rx_query_phy_status(precvframe, pphy_status);
-+					rtw_rx_add_unassoc_sta(primary_padapter, UNASOC_STA_SRC_RX_NMY_UC, get_ta(pbuf)
-+						, precvframe->u.hdr.attrib.phy_info.recv_signal_power);
-+				}
-+			} else
-+			#endif
-+				RTW_INFO("%s [WARN] Cannot find appropriate adapter - mac_addr : "MAC_FMT"\n"
-+					, __func__, MAC_ARG(ra));
-+
-+			rtw_free_recvframe(precvframe, &precvframe->u.hdr.adapter->recvpriv.free_recv_queue);
-+			goto exit;
-+		}
-+		#ifdef CONFIG_CONCURRENT_MODE
-+		else
-+			precvframe->u.hdr.adapter = iface;
-+		#endif
-+
-+	} else {
-+		/* BMC frame */
-+		#ifdef CONFIG_CONCURRENT_MODE
-+		rtw_mi_buddy_clone_bcmc_packet(primary_padapter, precvframe, pphy_status);
-+		#endif
-+
-+		#ifdef CONFIG_RTW_MULTI_AP
-+		/* unasoc STA RCPI */
-+		if (pphy_status
-+			&& rtw_unassoc_sta_src_chk(primary_padapter, UNASOC_STA_SRC_RX_BMC)
-+		) {
-+			phy_queried = 1;
-+			rx_query_phy_status(precvframe, pphy_status);
-+			rtw_rx_add_unassoc_sta(primary_padapter, UNASOC_STA_SRC_RX_BMC, get_ta(pbuf)
-+				, precvframe->u.hdr.attrib.phy_info.recv_signal_power);
-+		}
-+		#endif
-+
-+		/* skip unnecessary BMC data frame for primary adapter */
-+		if (GetFrameType(pbuf) == WIFI_DATA_TYPE
-+			&& !adapter_allow_bmc_data_rx(precvframe->u.hdr.adapter)
-+		) {
-+			rtw_free_recvframe(precvframe, &precvframe->u.hdr.adapter->recvpriv.free_recv_queue);
-+			goto exit;
-+		}
-+	}
-+#if defined(CONFIG_MP_INCLUDED) || defined(CONFIG_WIFI_MONITOR) || defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI)
-+query_phy_status:
-+#endif
-+	if (pphy_status) {
-+		if (!phy_queried)
-+			rx_query_phy_status(precvframe, pphy_status);
-+		#ifdef CONFIG_WIFI_MONITOR
-+		if (MLME_IS_MONITOR(primary_padapter))
-+			rx_query_moinfo(&precvframe->u.hdr.attrib, pphy_status);
-+		#endif
-+	}
-+
-+	ret = rtw_recv_entry(precvframe);
-+
-+exit:
-+	return ret;
-+}
-+
-+#ifdef CONFIG_RECV_THREAD_MODE
-+thread_return rtw_recv_thread(thread_context context)
-+{
-+	_adapter *adapter = (_adapter *)context;
-+	struct recv_priv *recvpriv = &adapter->recvpriv;
-+	s32 err = _SUCCESS;
-+#ifdef RTW_RECV_THREAD_HIGH_PRIORITY
-+#ifdef PLATFORM_LINUX
-+	struct sched_param param = { .sched_priority = 1 };
-+
-+	sched_setscheduler(current, SCHED_FIFO, &param);
-+#endif /* PLATFORM_LINUX */
-+#endif /*RTW_RECV_THREAD_HIGH_PRIORITY*/
-+	thread_enter("RTW_RECV_THREAD");
-+
-+	RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter));
-+
-+	do {
-+		err = _rtw_down_sema(&recvpriv->recv_sema);
-+		if (_FAIL == err) {
-+			RTW_ERR(FUNC_ADPT_FMT" down recv_sema fail!\n", FUNC_ADPT_ARG(adapter));
-+			goto exit;
-+		}
-+
-+		if (RTW_CANNOT_RUN(adapter)) {
-+			RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n",
-+				FUNC_ADPT_ARG(adapter),
-+				rtw_is_drv_stopped(adapter) ? "True" : "False",
-+				rtw_is_surprise_removed(adapter) ? "True" : "False");
-+			goto exit;
-+		}
-+
-+		err = rtw_hal_recv_hdl(adapter);
-+
-+		if (err == RTW_RFRAME_UNAVAIL
-+			|| err == RTW_RFRAME_PKT_UNAVAIL
-+		) {
-+			rtw_msleep_os(1);
-+			_rtw_up_sema(&recvpriv->recv_sema);
-+		}
-+
-+		flush_signals_thread();
-+
-+	} while (err != _FAIL);
-+
-+exit:
-+
-+	RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(adapter));
-+
-+	rtw_thread_wait_stop();
-+
-+	return 0;
-+}
-+#endif /* CONFIG_RECV_THREAD_MODE */
-+
-+#if DBG_RX_BH_TRACKING
-+void rx_bh_tk_set_stage(struct recv_priv *recv, u32 s)
-+{
-+	recv->rx_bh_stage = s;
-+}
-+
-+void rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen)
-+{
-+	if (recv->rx_bh_cbuf)
-+		recv->rx_bh_lbuf = recv->rx_bh_cbuf;
-+	recv->rx_bh_cbuf = buf;
-+	if (buf) {
-+		recv->rx_bh_cbuf_data = data;
-+		recv->rx_bh_cbuf_dlen = dlen;
-+		recv->rx_bh_buf_dq_cnt++;
-+	} else {
-+		recv->rx_bh_cbuf_data = NULL;
-+		recv->rx_bh_cbuf_dlen = 0;
-+	}
-+}
-+
-+void rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos)
-+{
-+	if (recv->rx_bh_cbuf) {
-+		recv->rx_bh_cbuf_pos = pos - recv->rx_bh_cbuf_data;
-+	} else {
-+		rtw_warn_on(1);
-+		recv->rx_bh_cbuf_pos = 0;
-+	}
-+}
-+
-+void rx_bh_tk_set_frame(struct recv_priv *recv, void *frame)
-+{
-+	recv->rx_bh_cframe = frame;
-+}
-+
-+void dump_rx_bh_tk(void *sel, struct recv_priv *recv)
-+{
-+	RTW_PRINT_SEL(sel, "[RXBHTK]s:%u, buf_dqc:%u, lbuf:%p, cbuf:%p, dlen:%u, pos:%u, cframe:%p\n"
-+		, recv->rx_bh_stage
-+		, recv->rx_bh_buf_dq_cnt
-+		, recv->rx_bh_lbuf
-+		, recv->rx_bh_cbuf
-+		, recv->rx_bh_cbuf_dlen
-+		, recv->rx_bh_cbuf_pos
-+		, recv->rx_bh_cframe
-+	);
-+}
-+#endif /* DBG_RX_BH_TRACKING */
-+
-diff --git a/drivers/staging/rtl8723cs/core/rtw_rf.c b/drivers/staging/rtl8723cs/core/rtw_rf.c
-new file mode 100644
-index 000000000000..60c95c7f1f89
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_rf.c
-@@ -0,0 +1,2437 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_RF_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+u8 center_ch_2g[CENTER_CH_2G_NUM] = {
-+/* G00 */1, 2,
-+/* G01 */3, 4, 5,
-+/* G02 */6, 7, 8,
-+/* G03 */9, 10, 11,
-+/* G04 */12, 13,
-+/* G05 */14
-+};
-+
-+#define ch_to_cch_2g_idx(ch) ((ch) - 1)
-+
-+u8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM] = {
-+	3,
-+	4,
-+	5,
-+	6,
-+	7,
-+	8,
-+	9,
-+	10,
-+	11,
-+};
-+
-+u8 op_chs_of_cch_2g_40m[CENTER_CH_2G_40M_NUM][2] = {
-+	{1, 5}, /* 3 */
-+	{2, 6}, /* 4 */
-+	{3, 7}, /* 5 */
-+	{4, 8}, /* 6 */
-+	{5, 9}, /* 7 */
-+	{6, 10}, /* 8 */
-+	{7, 11}, /* 9 */
-+	{8, 12}, /* 10 */
-+	{9, 13}, /* 11 */
-+};
-+
-+u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM] = {
-+/* G00 */36, 38, 40,
-+	42,
-+/* G01 */44, 46, 48,
-+	/* 50, */
-+/* G02 */52, 54, 56,
-+	58,
-+/* G03 */60, 62, 64,
-+/* G04 */100, 102, 104,
-+	106,
-+/* G05 */108, 110, 112,
-+	/* 114, */
-+/* G06 */116, 118, 120,
-+	122,
-+/* G07 */124, 126, 128,
-+/* G08 */132, 134, 136,
-+	138,
-+/* G09 */140, 142, 144,
-+/* G10 */149, 151, 153,
-+	155,
-+/* G11 */157, 159, 161,
-+	/* 163, */
-+/* G12 */165, 167, 169,
-+	171,
-+/* G13 */173, 175, 177
-+};
-+
-+u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM] = {
-+/* G00 */36, 40,
-+/* G01 */44, 48,
-+/* G02 */52, 56,
-+/* G03 */60, 64,
-+/* G04 */100, 104,
-+/* G05 */108, 112,
-+/* G06 */116, 120,
-+/* G07 */124, 128,
-+/* G08 */132, 136,
-+/* G09 */140, 144,
-+/* G10 */149, 153,
-+/* G11 */157, 161,
-+/* G12 */165, 169,
-+/* G13 */173, 177
-+};
-+
-+#define ch_to_cch_5g_20m_idx(ch) \
-+	( \
-+		((ch) >= 36 && (ch) <= 64) ? (((ch) - 36) >> 2) : \
-+		((ch) >= 100 && (ch) <= 144) ? 8 + (((ch) - 100) >> 2) : \
-+		((ch) >= 149 && (ch) <= 177) ? 20 + (((ch) - 149) >> 2) : 255 \
-+	)
-+
-+u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM] = {
-+/* G00 */38,
-+/* G01 */46,
-+/* G02 */54,
-+/* G03 */62,
-+/* G04 */102,
-+/* G05 */110,
-+/* G06 */118,
-+/* G07 */126,
-+/* G08 */134,
-+/* G09 */142,
-+/* G10 */151,
-+/* G11 */159,
-+/* G12 */167,
-+/* G13 */175
-+};
-+
-+u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM] = {
-+/* G00 */36, 38, 40,
-+/* G01 */44, 46, 48,
-+/* G02 */52, 54, 56,
-+/* G03 */60, 62, 64,
-+/* G04 */100, 102, 104,
-+/* G05 */108, 110, 112,
-+/* G06 */116, 118, 120,
-+/* G07 */124, 126, 128,
-+/* G08 */132, 134, 136,
-+/* G09 */140, 142, 144,
-+/* G10 */149, 151, 153,
-+/* G11 */157, 159, 161,
-+/* G12 */165, 167, 169,
-+/* G13 */173, 175, 177
-+};
-+
-+u8 op_chs_of_cch_5g_40m[CENTER_CH_5G_40M_NUM][2] = {
-+	{36, 40}, /* 38 */
-+	{44, 48}, /* 46 */
-+	{52, 56}, /* 54 */
-+	{60, 64}, /* 62 */
-+	{100, 104}, /* 102 */
-+	{108, 112}, /* 110 */
-+	{116, 120}, /* 118 */
-+	{124, 128}, /* 126 */
-+	{132, 136}, /* 134 */
-+	{140, 144}, /* 142 */
-+	{149, 153}, /* 151 */
-+	{157, 161}, /* 159 */
-+	{165, 169}, /* 167 */
-+	{173, 177}, /* 175 */
-+};
-+
-+u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM] = {
-+/* G00 ~ G01*/42,
-+/* G02 ~ G03*/58,
-+/* G04 ~ G05*/106,
-+/* G06 ~ G07*/122,
-+/* G08 ~ G09*/138,
-+/* G10 ~ G11*/155,
-+/* G12 ~ G13*/171
-+};
-+
-+u8 op_chs_of_cch_5g_80m[CENTER_CH_5G_80M_NUM][4] = {
-+	{36, 40, 44, 48}, /* 42 */
-+	{52, 56, 60, 64}, /* 58 */
-+	{100, 104, 108, 112}, /* 106 */
-+	{116, 120, 124, 128}, /* 122 */
-+	{132, 136, 140, 144}, /* 138 */
-+	{149, 153, 157, 161}, /* 155 */
-+	{165, 169, 173, 177}, /* 171 */
-+};
-+
-+u8 center_ch_5g_160m[CENTER_CH_5G_160M_NUM] = {
-+/* G00 ~ G03*/50,
-+/* G04 ~ G07*/114,
-+/* G10 ~ G13*/163
-+};
-+
-+u8 op_chs_of_cch_5g_160m[CENTER_CH_5G_160M_NUM][8] = {
-+	{36, 40, 44, 48, 52, 56, 60, 64}, /* 50 */
-+	{100, 104, 108, 112, 116, 120, 124, 128}, /* 114 */
-+	{149, 153, 157, 161, 165, 169, 173, 177}, /* 163 */
-+};
-+
-+struct center_chs_ent_t {
-+	u8 ch_num;
-+	u8 *chs;
-+};
-+
-+struct center_chs_ent_t center_chs_2g_by_bw[] = {
-+	{CENTER_CH_2G_NUM, center_ch_2g},
-+	{CENTER_CH_2G_40M_NUM, center_ch_2g_40m},
-+};
-+
-+struct center_chs_ent_t center_chs_5g_by_bw[] = {
-+	{CENTER_CH_5G_20M_NUM, center_ch_5g_20m},
-+	{CENTER_CH_5G_40M_NUM, center_ch_5g_40m},
-+	{CENTER_CH_5G_80M_NUM, center_ch_5g_80m},
-+	{CENTER_CH_5G_160M_NUM, center_ch_5g_160m},
-+};
-+
-+/*
-+ * Get center channel of smaller bandwidth by @param cch, @param bw, @param offset
-+ * @cch: the given center channel
-+ * @bw: the given bandwidth
-+ * @offset: the given primary SC offset of the given bandwidth
-+ *
-+ * return center channel of smaller bandiwdth if valid, or 0
-+ */
-+u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset)
-+{
-+	u8 t_cch = 0;
-+
-+	if (bw == CHANNEL_WIDTH_20) {
-+		t_cch = cch;
-+		goto exit;
-+	}
-+
-+	if (offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	/* 2.4G, 40MHz */
-+	if (cch >= 3 && cch <= 11 && bw == CHANNEL_WIDTH_40) {
-+		t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2;
-+		goto exit;
-+	}
-+
-+	/* 5G, 160MHz */
-+	if (cch >= 50 && cch <= 163 && bw == CHANNEL_WIDTH_160) {
-+		t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 8 : cch - 8;
-+		goto exit;
-+
-+	/* 5G, 80MHz */
-+	} else if (cch >= 42 && cch <= 171 && bw == CHANNEL_WIDTH_80) {
-+		t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 4 : cch - 4;
-+		goto exit;
-+
-+	/* 5G, 40MHz */
-+	} else if (cch >= 38 && cch <= 175 && bw == CHANNEL_WIDTH_40) {
-+		t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2;
-+		goto exit;
-+
-+	} else {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+exit:
-+	return t_cch;
-+}
-+
-+/*
-+ * Get center channel of smaller bandwidth by @param cch, @param bw, @param opch
-+ * @cch: the given center channel
-+ * @bw: the given bandwidth
-+ * @opch: the given operating channel
-+ *
-+ * return center channel of smaller bandiwdth if valid, or 0
-+ */
-+u8 rtw_get_scch_by_cch_opch(u8 cch, u8 bw, u8 opch)
-+{
-+	u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+
-+	if (opch > cch)
-+		offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+	else if (opch < cch)
-+		offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+
-+	return rtw_get_scch_by_cch_offset(cch, bw, offset);
-+}
-+
-+struct op_chs_ent_t {
-+	u8 ch_num;
-+	u8 *chs;
-+};
-+
-+struct op_chs_ent_t op_chs_of_cch_2g_by_bw[] = {
-+	{1, center_ch_2g},
-+	{2, (u8 *)op_chs_of_cch_2g_40m},
-+};
-+
-+struct op_chs_ent_t op_chs_of_cch_5g_by_bw[] = {
-+	{1, center_ch_5g_20m},
-+	{2, (u8 *)op_chs_of_cch_5g_40m},
-+	{4, (u8 *)op_chs_of_cch_5g_80m},
-+	{8, (u8 *)op_chs_of_cch_5g_160m},
-+};
-+
-+inline u8 center_chs_2g_num(u8 bw)
-+{
-+	if (bw > CHANNEL_WIDTH_40)
-+		return 0;
-+
-+	return center_chs_2g_by_bw[bw].ch_num;
-+}
-+
-+inline u8 center_chs_2g(u8 bw, u8 id)
-+{
-+	if (bw > CHANNEL_WIDTH_40)
-+		return 0;
-+
-+	if (id >= center_chs_2g_num(bw))
-+		return 0;
-+
-+	return center_chs_2g_by_bw[bw].chs[id];
-+}
-+
-+inline u8 center_chs_5g_num(u8 bw)
-+{
-+	if (bw > CHANNEL_WIDTH_160)
-+		return 0;
-+
-+	return center_chs_5g_by_bw[bw].ch_num;
-+}
-+
-+inline u8 center_chs_5g(u8 bw, u8 id)
-+{
-+	if (bw > CHANNEL_WIDTH_160)
-+		return 0;
-+
-+	if (id >= center_chs_5g_num(bw))
-+		return 0;
-+
-+	return center_chs_5g_by_bw[bw].chs[id];
-+}
-+
-+/*
-+ * Get available op channels by @param cch, @param bw
-+ * @cch: the given center channel
-+ * @bw: the given bandwidth
-+ * @op_chs: the pointer to return pointer of op channel array
-+ * @op_ch_num: the pointer to return pointer of op channel number
-+ *
-+ * return valid (1) or not (0)
-+ */
-+u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num)
-+{
-+	int i;
-+	struct center_chs_ent_t *c_chs_ent = NULL;
-+	struct op_chs_ent_t *op_chs_ent = NULL;
-+	u8 valid = 1;
-+
-+	if (cch <= 14
-+		&& bw <= CHANNEL_WIDTH_40
-+	) {
-+		c_chs_ent = &center_chs_2g_by_bw[bw];
-+		op_chs_ent = &op_chs_of_cch_2g_by_bw[bw];
-+	} else if (cch >= 36 && cch <= 177
-+		&& bw <= CHANNEL_WIDTH_160
-+	) {
-+		c_chs_ent = &center_chs_5g_by_bw[bw];
-+		op_chs_ent = &op_chs_of_cch_5g_by_bw[bw];
-+	} else {
-+		valid = 0;
-+		goto exit;
-+	}
-+
-+	for (i = 0; i < c_chs_ent->ch_num; i++)
-+		if (cch == *(c_chs_ent->chs + i))
-+			break;
-+
-+	if (i == c_chs_ent->ch_num) {
-+		valid = 0;
-+		goto exit;
-+	}
-+
-+	*op_chs = op_chs_ent->chs + op_chs_ent->ch_num * i;
-+	*op_ch_num = op_chs_ent->ch_num;
-+
-+exit:
-+	return valid;
-+}
-+
-+u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset)
-+{
-+	u8 valid = 1;
-+	u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+
-+	if (bw == CHANNEL_WIDTH_20)
-+		goto exit;
-+
-+	if (bw >= CHANNEL_WIDTH_80 && ch <= 14) {
-+		valid = 0;
-+		goto exit;
-+	}
-+
-+	if (ch >= 1 && ch <= 4)
-+		offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+	else if (ch >= 5 && ch <= 9) {
-+		if (*r_offset == HAL_PRIME_CHNL_OFFSET_LOWER || *r_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
-+			offset = *r_offset; /* both lower and upper is valid, obey input value */
-+		else
-+			offset = HAL_PRIME_CHNL_OFFSET_UPPER; /* default use upper */
-+	} else if (ch >= 10 && ch <= 13)
-+		offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+	else if (ch == 14) {
-+		valid = 0; /* ch14 doesn't support 40MHz bandwidth */
-+		goto exit;
-+	} else if (ch >= 36 && ch <= 177) {
-+		switch (ch) {
-+		case 36:
-+		case 44:
-+		case 52:
-+		case 60:
-+		case 100:
-+		case 108:
-+		case 116:
-+		case 124:
-+		case 132:
-+		case 140:
-+		case 149:
-+		case 157:
-+		case 165:
-+		case 173:
-+			offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+			break;
-+		case 40:
-+		case 48:
-+		case 56:
-+		case 64:
-+		case 104:
-+		case 112:
-+		case 120:
-+		case 128:
-+		case 136:
-+		case 144:
-+		case 153:
-+		case 161:
-+		case 169:
-+		case 177:
-+			offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+			break;
-+		default:
-+			valid = 0;
-+			break;
-+		}
-+	} else
-+		valid = 0;
-+
-+exit:
-+	if (valid && r_offset)
-+		*r_offset = offset;
-+	return valid;
-+}
-+
-+u8 rtw_get_center_ch(u8 ch, u8 bw, u8 offset)
-+{
-+	u8 cch = ch;
-+
-+	if (bw == CHANNEL_WIDTH_160) {
-+		if (ch % 4 == 0) {
-+			if (ch >= 36 && ch <= 64)
-+				cch = 50;
-+			else if (ch >= 100 && ch <= 128)
-+				cch = 114;
-+		} else if (ch % 4 == 1) {
-+			if (ch >= 149 && ch <= 177)
-+				cch = 163;
-+		}
-+
-+	} else if (bw == CHANNEL_WIDTH_80) {
-+		if (ch <= 14)
-+			cch = 7; /* special case for 2.4G */
-+		else if (ch % 4 == 0) {
-+			if (ch >= 36 && ch <= 48)
-+				cch = 42;
-+			else if (ch >= 52 && ch <= 64)
-+				cch = 58;
-+			else if (ch >= 100 && ch <= 112)
-+				cch = 106;
-+			else if (ch >= 116 && ch <= 128)
-+				cch = 122;
-+			else if (ch >= 132 && ch <= 144)
-+				cch = 138;
-+		} else if (ch % 4 == 1) {
-+			if (ch >= 149 && ch <= 161)
-+				cch = 155;
-+			else if (ch >= 165 && ch <= 177)
-+				cch = 171;
-+		}
-+
-+	} else if (bw == CHANNEL_WIDTH_40) {
-+		if (offset == HAL_PRIME_CHNL_OFFSET_LOWER)
-+			cch = ch + 2;
-+		else if (offset == HAL_PRIME_CHNL_OFFSET_UPPER)
-+			cch = ch - 2;
-+
-+	} else if (bw == CHANNEL_WIDTH_20
-+		|| bw == CHANNEL_WIDTH_10
-+		|| bw == CHANNEL_WIDTH_5
-+	)
-+		; /* same as ch */
-+	else
-+		rtw_warn_on(1);
-+
-+	return cch;
-+}
-+
-+u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group)
-+{
-+	BAND_TYPE band = BAND_MAX;
-+	s8 gp = -1, cck_gp = -1;
-+
-+	if (ch <= 14) {
-+		band = BAND_ON_2_4G;
-+
-+		if (1 <= ch && ch <= 2)
-+			gp = 0;
-+		else if (3  <= ch && ch <= 5)
-+			gp = 1;
-+		else if (6  <= ch && ch <= 8)
-+			gp = 2;
-+		else if (9  <= ch && ch <= 11)
-+			gp = 3;
-+		else if (12 <= ch && ch <= 14)
-+			gp = 4;
-+		else
-+			band = BAND_MAX;
-+
-+		if (ch == 14)
-+			cck_gp = 5;
-+		else
-+			cck_gp = gp;
-+	} else {
-+		band = BAND_ON_5G;
-+
-+		if (36 <= ch && ch <= 42)
-+			gp = 0;
-+		else if (44   <= ch && ch <=  48)
-+			gp = 1;
-+		else if (50   <= ch && ch <=  58)
-+			gp = 2;
-+		else if (60   <= ch && ch <=  64)
-+			gp = 3;
-+		else if (100  <= ch && ch <= 106)
-+			gp = 4;
-+		else if (108  <= ch && ch <= 114)
-+			gp = 5;
-+		else if (116  <= ch && ch <= 122)
-+			gp = 6;
-+		else if (124  <= ch && ch <= 130)
-+			gp = 7;
-+		else if (132  <= ch && ch <= 138)
-+			gp = 8;
-+		else if (140  <= ch && ch <= 144)
-+			gp = 9;
-+		else if (149  <= ch && ch <= 155)
-+			gp = 10;
-+		else if (157  <= ch && ch <= 161)
-+			gp = 11;
-+		else if (165  <= ch && ch <= 171)
-+			gp = 12;
-+		else if (173  <= ch && ch <= 177)
-+			gp = 13;
-+		else
-+			band = BAND_MAX;
-+	}
-+
-+	if (band == BAND_MAX
-+		|| (band == BAND_ON_2_4G && cck_gp == -1)
-+		|| gp == -1
-+	) {
-+		RTW_WARN("%s invalid channel:%u", __func__, ch);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (group)
-+		*group = gp;
-+	if (cck_group && band == BAND_ON_2_4G)
-+		*cck_group = cck_gp;
-+
-+exit:
-+	return band;
-+}
-+
-+int rtw_ch2freq(int chan)
-+{
-+	/* see 802.11 17.3.8.3.2 and Annex J
-+	* there are overlapping channel numbers in 5GHz and 2GHz bands */
-+
-+	/*
-+	* RTK: don't consider the overlapping channel numbers: 5G channel <= 14,
-+	* because we don't support it. simply judge from channel number
-+	*/
-+
-+	if (chan >= 1 && chan <= 14) {
-+		if (chan == 14)
-+			return 2484;
-+		else if (chan < 14)
-+			return 2407 + chan * 5;
-+	} else if (chan >= 36 && chan <= 177)
-+		return 5000 + chan * 5;
-+
-+	return 0; /* not supported */
-+}
-+
-+int rtw_freq2ch(int freq)
-+{
-+	/* see 802.11 17.3.8.3.2 and Annex J */
-+	if (freq == 2484)
-+		return 14;
-+	else if (freq < 2484)
-+		return (freq - 2407) / 5;
-+	else if (freq >= 4910 && freq <= 4980)
-+		return (freq - 4000) / 5;
-+	else if (freq <= 45000) /* DMG band lower limit */
-+		return (freq - 5000) / 5;
-+	else if (freq >= 58320 && freq <= 64800)
-+		return (freq - 56160) / 2160;
-+	else
-+		return 0;
-+}
-+
-+bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo)
-+{
-+	u8 c_ch;
-+	u32 freq;
-+	u32 hi_ret = 0, lo_ret = 0;
-+	bool valid = _FALSE;
-+
-+	if (hi)
-+		*hi = 0;
-+	if (lo)
-+		*lo = 0;
-+
-+	c_ch = rtw_get_center_ch(ch, bw, offset);
-+	freq = rtw_ch2freq(c_ch);
-+
-+	if (!freq) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (bw == CHANNEL_WIDTH_160) {
-+		hi_ret = freq + 80;
-+		lo_ret = freq - 80;
-+	} else if (bw == CHANNEL_WIDTH_80) {
-+		hi_ret = freq + 40;
-+		lo_ret = freq - 40;
-+	} else if (bw == CHANNEL_WIDTH_40) {
-+		hi_ret = freq + 20;
-+		lo_ret = freq - 20;
-+	} else if (bw == CHANNEL_WIDTH_20) {
-+		hi_ret = freq + 10;
-+		lo_ret = freq - 10;
-+	} else
-+		rtw_warn_on(1);
-+
-+	if (hi)
-+		*hi = hi_ret;
-+	if (lo)
-+		*lo = lo_ret;
-+
-+	valid = _TRUE;
-+
-+exit:
-+	return valid;
-+}
-+
-+const char *const _ch_width_str[CHANNEL_WIDTH_MAX] = {
-+	[CHANNEL_WIDTH_20]		= "20MHz",
-+	[CHANNEL_WIDTH_40]		= "40MHz",
-+	[CHANNEL_WIDTH_80]		= "80MHz",
-+	[CHANNEL_WIDTH_160]		= "160MHz",
-+	[CHANNEL_WIDTH_80_80]	= "80_80MHz",
-+	[CHANNEL_WIDTH_5]		= "5MHz",
-+	[CHANNEL_WIDTH_10]		= "10MHz",
-+};
-+
-+const u8 _ch_width_to_bw_cap[CHANNEL_WIDTH_MAX] = {
-+	[CHANNEL_WIDTH_20]		= BW_CAP_20M,
-+	[CHANNEL_WIDTH_40]		= BW_CAP_40M,
-+	[CHANNEL_WIDTH_80]		= BW_CAP_80M,
-+	[CHANNEL_WIDTH_160]		= BW_CAP_160M,
-+	[CHANNEL_WIDTH_80_80]	= BW_CAP_80_80M,
-+	[CHANNEL_WIDTH_5]		= BW_CAP_5M,
-+	[CHANNEL_WIDTH_10]		= BW_CAP_10M,
-+};
-+
-+const char *const _band_str[] = {
-+	"2.4G",
-+	"5G",
-+	"BAND_MAX",
-+};
-+
-+const u8 _band_to_band_cap[] = {
-+	BAND_CAP_2G,
-+	BAND_CAP_5G,
-+	0,
-+};
-+
-+const char *const _opc_bw_str[OPC_BW_NUM] = {
-+	"20M ",		/* OPC_BW20 */
-+	"40M+",		/* OPC_BW40PLUS */
-+	"40M-",		/* OPC_BW40MINUS */
-+	"80M ",		/* OPC_BW80 */
-+	"160M ",	/* OPC_BW160 */
-+	"80+80M ",	/* OPC_BW80P80 */
-+};
-+
-+const u8 _opc_bw_to_ch_width[OPC_BW_NUM] = {
-+	CHANNEL_WIDTH_20,		/* OPC_BW20 */
-+	CHANNEL_WIDTH_40,		/* OPC_BW40PLUS */
-+	CHANNEL_WIDTH_40,		/* OPC_BW40MINUS */
-+	CHANNEL_WIDTH_80,		/* OPC_BW80 */
-+	CHANNEL_WIDTH_160,		/* OPC_BW160 */
-+	CHANNEL_WIDTH_80_80,	/* OPC_BW80P80 */
-+};
-+
-+/* global operating class database */
-+
-+struct op_class_t {
-+	u8 class_id;
-+	BAND_TYPE band;
-+	enum opc_bw bw;
-+	u8 *len_ch_attr;
-+};
-+
-+#define OPC_CH_LIST_LEN(_opc) (_opc.len_ch_attr[0])
-+#define OPC_CH_LIST_CH(_opc, _i) (_opc.len_ch_attr[_i + 1])
-+
-+#define OP_CLASS_ENT(_class, _band, _bw, _len, arg...) \
-+	{.class_id = _class, .band = _band, .bw = _bw, .len_ch_attr = (uint8_t[_len + 1]) {_len, ##arg},}
-+
-+/* 802.11-2016 Table E-4, partial */
-+static const struct op_class_t global_op_class[] = {
-+	/* 2G ch1~13, 20M */
-+	OP_CLASS_ENT(81,	BAND_ON_2_4G,	OPC_BW20,		13,	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),
-+	/* 2G ch14, 20M */
-+	OP_CLASS_ENT(82,	BAND_ON_2_4G,	OPC_BW20,		1,	14),
-+	/* 2G, 40M */
-+	OP_CLASS_ENT(83,	BAND_ON_2_4G, 	OPC_BW40PLUS,	9,	1, 2, 3, 4, 5, 6, 7, 8, 9),
-+	OP_CLASS_ENT(84,	BAND_ON_2_4G,	OPC_BW40MINUS,	9,	5, 6, 7, 8, 9, 10, 11, 12, 13),
-+	/* 5G band 1, 20M & 40M */
-+	OP_CLASS_ENT(115,	BAND_ON_5G,		OPC_BW20,		4,	36, 40, 44, 48),
-+	OP_CLASS_ENT(116,	BAND_ON_5G,		OPC_BW40PLUS,	2,	36, 44),
-+	OP_CLASS_ENT(117,	BAND_ON_5G,		OPC_BW40MINUS,	2,	40, 48),
-+	/* 5G band 2, 20M & 40M */
-+	OP_CLASS_ENT(118,	BAND_ON_5G,		OPC_BW20,		4,	52, 56, 60, 64),
-+	OP_CLASS_ENT(119,	BAND_ON_5G,		OPC_BW40PLUS,	2,	52, 60),
-+	OP_CLASS_ENT(120,	BAND_ON_5G,		OPC_BW40MINUS,	2,	56, 64),
-+	/* 5G band 3, 20M & 40M */
-+	OP_CLASS_ENT(121,	BAND_ON_5G,		OPC_BW20,		12,	100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144),
-+	OP_CLASS_ENT(122,	BAND_ON_5G,		OPC_BW40PLUS,	6,	100, 108, 116, 124, 132, 140),
-+	OP_CLASS_ENT(123,	BAND_ON_5G,		OPC_BW40MINUS,	6,	104, 112, 120, 128, 136, 144),
-+	/* 5G band 4, 20M & 40M */
-+	OP_CLASS_ENT(124,	BAND_ON_5G,		OPC_BW20,		4,	149, 153, 157, 161),
-+	OP_CLASS_ENT(125,	BAND_ON_5G,		OPC_BW20,		6,	149, 153, 157, 161, 165, 169),
-+	OP_CLASS_ENT(126,	BAND_ON_5G,		OPC_BW40PLUS,	2,	149, 157),
-+	OP_CLASS_ENT(127,	BAND_ON_5G,		OPC_BW40MINUS,	2,	153, 161),
-+	/* 5G, 80M & 160M */
-+	OP_CLASS_ENT(128,	BAND_ON_5G,		OPC_BW80,		24,	36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161),
-+	OP_CLASS_ENT(129,	BAND_ON_5G,		OPC_BW160,		16,	36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128),
-+	#if 0 /* TODO */
-+	/* 5G, 80+80M */
-+	{130,	BAND_ON_5G,		OPC_BW80P80,	0x0FFFFFF},
-+	#endif
-+};
-+
-+static const int global_op_class_num = sizeof(global_op_class) / sizeof(struct op_class_t);
-+
-+static const struct op_class_t *get_global_op_class_by_id(u8 gid)
-+{
-+	int i;
-+
-+	for (i = 0; i < global_op_class_num; i++)
-+		if (global_op_class[i].class_id == gid)
-+			break;
-+
-+	return i < global_op_class_num ? &global_op_class[i] : NULL;
-+}
-+
-+bool is_valid_global_op_class_id(u8 gid)
-+{
-+	return get_global_op_class_by_id(gid) ? 1 : 0;
-+}
-+
-+static bool is_valid_global_op_class_ch(const struct op_class_t *opc, u8 ch)
-+{
-+	int array_idx;
-+	int i;
-+
-+	if (opc < global_op_class
-+		|| (((u8 *)opc) - ((u8 *)global_op_class)) % sizeof(struct op_class_t)
-+	) {
-+		RTW_ERR("Invalid opc pointer:%p (global_op_class:%p, sizeof(struct op_class_t):%zu, %zu)\n"
-+			, opc, global_op_class, sizeof(struct op_class_t), (((u8 *)opc) - ((u8 *)global_op_class)) % sizeof(struct op_class_t));
-+		return 0;
-+	}
-+
-+	array_idx = (((u8 *)opc) - ((u8 *)global_op_class)) / sizeof(struct op_class_t);
-+
-+	for (i = 0; i < OPC_CH_LIST_LEN(global_op_class[array_idx]); i++)
-+		if (OPC_CH_LIST_CH(global_op_class[array_idx], i) == ch)
-+			break;
-+
-+	return i < OPC_CH_LIST_LEN(global_op_class[array_idx]);
-+}
-+
-+static enum opc_bw get_global_opc_bw_by_id(u8 gid)
-+{
-+	int i;
-+
-+	for (i = 0; i < global_op_class_num; i++)
-+		if (global_op_class[i].class_id == gid)
-+			break;
-+
-+	return i < global_op_class_num ? global_op_class[i].bw : OPC_BW_NUM;
-+}
-+
-+/* -2: logic error, -1: error, 0: is already BW20 */
-+s16 get_sub_op_class(u8 gid, u8 ch)
-+{
-+	const struct op_class_t *opc = get_global_op_class_by_id(gid);
-+	int i;
-+	enum channel_width bw; 
-+
-+	if (!opc)
-+		return -1;
-+
-+	if (!is_valid_global_op_class_ch(opc, ch)) {
-+		return -1;
-+	}
-+
-+	if (opc->bw == OPC_BW20)
-+		return 0;
-+
-+	bw = opc_bw_to_ch_width(opc->bw);
-+
-+	for (i = 0; i < global_op_class_num; i++) {
-+		if (bw != opc_bw_to_ch_width(global_op_class[i].bw) + 1)
-+			continue;
-+		if (is_valid_global_op_class_ch(&global_op_class[i], ch))
-+			break;
-+	}
-+
-+	return i < global_op_class_num ? global_op_class[i].class_id : -2;
-+}
-+
-+static void dump_op_class_ch_title(void *sel)
-+{
-+	RTW_PRINT_SEL(sel, "%-5s %-4s %-7s ch_list\n"
-+		, "class", "band", "bw");
-+}
-+
-+static void dump_global_op_class_ch_single(void *sel, u8 gid)
-+{
-+	u8 i;
-+	char buf[100];
-+	char *pos = buf;
-+
-+	for (i = 0; i < OPC_CH_LIST_LEN(global_op_class[gid]); i++)
-+		pos += snprintf(pos, 100 - (pos - buf), " %u", OPC_CH_LIST_CH(global_op_class[gid], i));
-+
-+	RTW_PRINT_SEL(sel, "%5u %4s %7s%s\n"
-+		, global_op_class[gid].class_id
-+		, band_str(global_op_class[gid].band)
-+		, opc_bw_str(global_op_class[gid].bw), buf);
-+}
-+
-+#ifdef CONFIG_RTW_DEBUG
-+static bool dbg_global_op_class_validate(u8 gid)
-+{
-+	u8 i;
-+	u8 ch, bw, offset, cch;
-+	bool ret = 1;
-+
-+	switch (global_op_class[gid].bw) {
-+	case OPC_BW20:
-+		bw = CHANNEL_WIDTH_20;
-+		offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		break;
-+	case OPC_BW40PLUS:
-+		bw = CHANNEL_WIDTH_40;
-+		offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+		break;
-+	case OPC_BW40MINUS:
-+		bw = CHANNEL_WIDTH_40;
-+		offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+		break;
-+	case OPC_BW80:
-+		bw = CHANNEL_WIDTH_80;
-+		offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		break;
-+	case OPC_BW160:
-+		bw = CHANNEL_WIDTH_160;
-+		offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		break;
-+	case OPC_BW80P80: /* TODO */
-+	default:
-+		RTW_ERR("%s class:%u unsupported opc_bw:%u\n"
-+			, __func__, global_op_class[gid].class_id, global_op_class[gid].bw);
-+		ret = 0;
-+		goto exit;
-+	}
-+
-+	for (i = 0; i < OPC_CH_LIST_LEN(global_op_class[gid]); i++) {
-+		u8 *op_chs;
-+		u8 op_ch_num;
-+		u8 k;
-+
-+		ch = OPC_CH_LIST_CH(global_op_class[gid], i);
-+		cch = rtw_get_center_ch(ch ,bw, offset);
-+		if (!cch) {
-+			RTW_ERR("%s can't get cch from class:%u ch:%u\n"
-+				, __func__, global_op_class[gid].class_id, ch);
-+			ret = 0;
-+			continue;
-+		}
-+
-+		if (!rtw_get_op_chs_by_cch_bw(cch, bw, &op_chs, &op_ch_num)) {
-+			RTW_ERR("%s can't get op chs from class:%u cch:%u\n"
-+				, __func__, global_op_class[gid].class_id, cch);
-+			ret = 0;
-+			continue;
-+		}
-+
-+		for (k = 0; k < op_ch_num; k++) {
-+			if (*(op_chs + k) == ch)
-+				break;
-+		}
-+		if (k >= op_ch_num) {
-+			RTW_ERR("%s can't get ch:%u from op_chs class:%u cch:%u\n"
-+				, __func__, ch, global_op_class[i].class_id, cch);
-+			ret = 0;
-+		}
-+	}
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_RTW_DEBUG */
-+
-+void dump_global_op_class(void *sel)
-+{
-+	u8 i;
-+
-+	dump_op_class_ch_title(sel);
-+
-+	for (i = 0; i < global_op_class_num; i++)
-+		dump_global_op_class_ch_single(sel, i);
-+}
-+
-+u8 rtw_get_op_class_by_chbw(u8 ch, u8 bw, u8 offset)
-+{
-+	BAND_TYPE band = BAND_MAX;
-+	int i;
-+	u8 gid = 0; /* invalid */
-+
-+	if (rtw_is_2g_ch(ch))
-+		band = BAND_ON_2_4G;
-+	else if (rtw_is_5g_ch(ch))
-+		band = BAND_ON_5G;
-+	else
-+		goto exit;
-+
-+	switch (bw) {
-+	case CHANNEL_WIDTH_20:
-+	case CHANNEL_WIDTH_40:
-+	case CHANNEL_WIDTH_80:
-+	case CHANNEL_WIDTH_160:
-+	#if 0 /* TODO */
-+	case CHANNEL_WIDTH_80_80:
-+	#endif
-+		break;
-+	default:
-+		goto exit;
-+	}
-+
-+	for (i = 0; i < global_op_class_num; i++) {
-+		if (band != global_op_class[i].band)
-+			continue;
-+
-+		if (opc_bw_to_ch_width(global_op_class[i].bw) != bw)
-+			continue;
-+
-+		if ((global_op_class[i].bw == OPC_BW40PLUS
-+				&& offset != HAL_PRIME_CHNL_OFFSET_LOWER)
-+			|| (global_op_class[i].bw == OPC_BW40MINUS
-+				&& offset != HAL_PRIME_CHNL_OFFSET_UPPER)
-+		)
-+			continue;
-+
-+		if (is_valid_global_op_class_ch(&global_op_class[i], ch))
-+			goto get;
-+	}
-+
-+get:
-+	if (i < global_op_class_num) {
-+		#if 0 /* TODO */
-+		if (bw == CHANNEL_WIDTH_80_80) {
-+			/* search another ch */
-+			if (!is_valid_global_op_class_ch(&global_op_class[i], ch2))
-+				goto exit;
-+		}
-+		#endif
-+
-+		gid = global_op_class[i].class_id;
-+	}
-+
-+exit:
-+	return gid;
-+}
-+
-+u8 rtw_get_bw_offset_by_op_class_ch(u8 gid, u8 ch, u8 *bw, u8 *offset)
-+{
-+	enum opc_bw opc_bw;
-+	u8 valid = 0;
-+	int i;
-+
-+	opc_bw = get_global_opc_bw_by_id(gid);
-+	if (opc_bw == OPC_BW_NUM)
-+		goto exit;
-+
-+	*bw = opc_bw_to_ch_width(opc_bw);
-+
-+	if (opc_bw == OPC_BW40PLUS)
-+		*offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+	else if (opc_bw == OPC_BW40MINUS)
-+		*offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+
-+	if (rtw_get_offset_by_chbw(ch, *bw, offset))
-+		valid = 1;
-+
-+exit:
-+	return valid;
-+}
-+
-+static struct op_class_pref_t *opc_pref_alloc(u8 class_id)
-+{
-+	int i, j;
-+	struct op_class_pref_t *opc_pref = NULL;
-+
-+	for (i = 0; i < global_op_class_num; i++)
-+		if (global_op_class[i].class_id == class_id)
-+			break;
-+
-+	if (i >= global_op_class_num)
-+		goto exit;
-+
-+	opc_pref = rtw_zmalloc(sizeof(*opc_pref));
-+	if (!opc_pref)
-+		goto exit;
-+
-+	opc_pref->class_id = global_op_class[i].class_id;
-+	opc_pref->band = global_op_class[i].band;
-+	opc_pref->bw = global_op_class[i].bw;
-+
-+	for (j = 0; j < OPC_CH_LIST_LEN(global_op_class[i]); j++) {
-+		opc_pref->chs[j].ch = OPC_CH_LIST_CH(global_op_class[i], j);
-+		opc_pref->chs[j].static_non_op = 1;
-+		opc_pref->chs[j].no_ir = 1;
-+		opc_pref->chs[j].max_txpwr = UNSPECIFIED_MBM;
-+	}
-+	opc_pref->ch_num = OPC_CH_LIST_LEN(global_op_class[i]);
-+
-+exit:
-+	return opc_pref;
-+}
-+
-+static void opc_pref_free(struct op_class_pref_t *opc_pref)
-+{
-+	rtw_mfree(opc_pref, sizeof(*opc_pref));
-+}
-+
-+int op_class_pref_init(_adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+	u8 bw;
-+	struct op_class_pref_t *opc_pref;
-+	int i;
-+	u8 op_class_num = 0;
-+	u8 band_bmp = 0;
-+	u8 bw_bmp[BAND_MAX] = {0};
-+	int ret = _FAIL;
-+
-+	rfctl->spt_op_class_ch = rtw_zmalloc(sizeof(struct op_class_pref_t *) * global_op_class_num);
-+	if (!rfctl->spt_op_class_ch) {
-+		RTW_ERR("%s alloc rfctl->spt_op_class_ch fail\n", __func__);
-+		goto exit;
-+	}
-+
-+	if (IsSupported24G(regsty->wireless_mode) && hal_chk_band_cap(adapter, BAND_CAP_2G))
-+		band_bmp |= BAND_CAP_2G;
-+	if (is_supported_5g(regsty->wireless_mode) && hal_chk_band_cap(adapter, BAND_CAP_5G))
-+		band_bmp |= BAND_CAP_5G;
-+
-+	bw_bmp[BAND_ON_2_4G] = (ch_width_to_bw_cap(REGSTY_BW_2G(regsty) + 1) - 1) & (GET_HAL_SPEC(adapter)->bw_cap);
-+	bw_bmp[BAND_ON_5G] = (ch_width_to_bw_cap(REGSTY_BW_5G(regsty) + 1) - 1) & (GET_HAL_SPEC(adapter)->bw_cap);
-+	if (!REGSTY_IS_11AC_ENABLE(regsty)
-+		|| !is_supported_vht(regsty->wireless_mode)
-+	)
-+		bw_bmp[BAND_ON_5G] &= ~(BW_CAP_80M | BW_CAP_160M);
-+
-+	if (0) {
-+		RTW_INFO("REGSTY_BW_2G(regsty):%u\n", REGSTY_BW_2G(regsty));
-+		RTW_INFO("REGSTY_BW_5G(regsty):%u\n", REGSTY_BW_5G(regsty));
-+		RTW_INFO("GET_HAL_SPEC(adapter)->bw_cap:0x%x\n", GET_HAL_SPEC(adapter)->bw_cap);
-+		RTW_INFO("band_bmp:0x%x\n", band_bmp);
-+		RTW_INFO("bw_bmp[2G]:0x%x\n", bw_bmp[BAND_ON_2_4G]);
-+		RTW_INFO("bw_bmp[5G]:0x%x\n", bw_bmp[BAND_ON_5G]);
-+	}
-+
-+	for (i = 0; i < global_op_class_num; i++) {
-+		#ifdef CONFIG_RTW_DEBUG
-+		rtw_warn_on(!dbg_global_op_class_validate(i));
-+		#endif
-+
-+		if (!(band_bmp & band_to_band_cap(global_op_class[i].band)))
-+			continue;
-+
-+		bw = opc_bw_to_ch_width(global_op_class[i].bw);
-+		if (bw == CHANNEL_WIDTH_MAX
-+			|| bw == CHANNEL_WIDTH_80_80 /* TODO */
-+		)
-+			continue;
-+
-+		if (!(bw_bmp[global_op_class[i].band] & ch_width_to_bw_cap(bw)))
-+			continue;
-+
-+		opc_pref = opc_pref_alloc(global_op_class[i].class_id);
-+		if (!opc_pref) {
-+			RTW_ERR("%s opc_pref_alloc(%u) fail\n", __func__, global_op_class[i].class_id);
-+			goto exit;
-+		}
-+
-+		if (opc_pref->ch_num) {
-+			rfctl->spt_op_class_ch[i] = opc_pref;
-+			op_class_num++;
-+		} else
-+			opc_pref_free(opc_pref);
-+	}
-+
-+	rfctl->cap_spt_op_class_num = op_class_num;
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+void op_class_pref_deinit(_adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	int i;
-+
-+	if (!rfctl->spt_op_class_ch)
-+		return;
-+
-+	for (i = 0; i < global_op_class_num; i++) {
-+		if (rfctl->spt_op_class_ch[i]) {
-+			opc_pref_free(rfctl->spt_op_class_ch[i]);
-+			rfctl->spt_op_class_ch[i] = NULL;
-+		}
-+	}
-+
-+	rtw_mfree(rfctl->spt_op_class_ch, sizeof(struct op_class_pref_t *) * global_op_class_num);
-+	rfctl->spt_op_class_ch = NULL;
-+}
-+
-+void op_class_pref_apply_regulatory(_adapter *adapter, u8 reason)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	RT_CHANNEL_INFO *chset = rfctl->channel_set;
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+	u8 ch, bw, offset, cch;
-+	struct op_class_pref_t *opc_pref;
-+	int i, j;
-+	u8 reg_op_class_num = 0;
-+	u8 op_class_num = 0;
-+
-+	for (i = 0; i < global_op_class_num; i++) {
-+		if (!rfctl->spt_op_class_ch[i])
-+			continue;
-+		opc_pref = rfctl->spt_op_class_ch[i];
-+
-+		/* reset all channel */
-+		for (j = 0; opc_pref->chs[j].ch != 0; j++) {
-+			if (reason >= REG_CHANGE)
-+				opc_pref->chs[j].static_non_op = 1;
-+			if (reason != REG_TXPWR_CHANGE)
-+				opc_pref->chs[j].no_ir = 1;
-+			if (reason >= REG_TXPWR_CHANGE)
-+				opc_pref->chs[j].max_txpwr = UNSPECIFIED_MBM;
-+		}
-+		if (reason >= REG_CHANGE)
-+			opc_pref->op_ch_num = 0;
-+		if (reason != REG_TXPWR_CHANGE)
-+			opc_pref->ir_ch_num = 0;
-+
-+		switch (opc_pref->bw) {
-+		case OPC_BW20:
-+			bw = CHANNEL_WIDTH_20;
-+			offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+			break;
-+		case OPC_BW40PLUS:
-+			bw = CHANNEL_WIDTH_40;
-+			offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+			break;
-+		case OPC_BW40MINUS:
-+			bw = CHANNEL_WIDTH_40;
-+			offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+			break;
-+		case OPC_BW80:
-+			bw = CHANNEL_WIDTH_80;
-+			offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+			break;
-+		case OPC_BW160:
-+			bw = CHANNEL_WIDTH_160;
-+			offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+			break;
-+		case OPC_BW80P80: /* TODO */
-+		default:
-+			continue;
-+		}
-+
-+		if (rfctl->country_ent && !COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)
-+			&& (bw == CHANNEL_WIDTH_80 || bw == CHANNEL_WIDTH_160))
-+			continue;
-+
-+		for (j = 0; opc_pref->chs[j].ch != 0; j++) {
-+			u8 *op_chs;
-+			u8 op_ch_num;
-+			u8 k, l;
-+			int chset_idx;
-+
-+			ch = opc_pref->chs[j].ch;
-+
-+			if (reason >= REG_TXPWR_CHANGE)
-+				opc_pref->chs[j].max_txpwr = rtw_rfctl_get_reg_max_txpwr_mbm(rfctl, ch, bw, offset, 1);
-+
-+			if (reason == REG_TXPWR_CHANGE)
-+				continue;
-+
-+			cch = rtw_get_center_ch(ch ,bw, offset);
-+			if (!cch)
-+				continue;
-+
-+			if (!rtw_get_op_chs_by_cch_bw(cch, bw, &op_chs, &op_ch_num))
-+				continue;
-+
-+			for (k = 0, l = 0; k < op_ch_num; k++) {
-+				chset_idx = rtw_chset_search_ch(chset, *(op_chs + k));
-+				if (chset_idx == -1)
-+					break;
-+				if (bw >= CHANNEL_WIDTH_40) {
-+					if ((chset[chset_idx].flags & RTW_CHF_NO_HT40U) && k % 2 == 0)
-+						break;
-+					if ((chset[chset_idx].flags & RTW_CHF_NO_HT40L) && k % 2 == 1)
-+						break;
-+				}
-+				if (bw >= CHANNEL_WIDTH_80 && (chset[chset_idx].flags & RTW_CHF_NO_80MHZ))
-+					break;
-+				if (bw >= CHANNEL_WIDTH_160 && (chset[chset_idx].flags & RTW_CHF_NO_160MHZ))
-+					break;
-+				if ((chset[chset_idx].flags & RTW_CHF_DFS) && rtw_rfctl_dfs_domain_unknown(rfctl))
-+					continue;
-+				if (chset[chset_idx].flags & RTW_CHF_NO_IR)
-+					continue;
-+				l++;
-+			}
-+			if (k < op_ch_num)
-+				continue;
-+
-+			if (reason >= REG_CHANGE) {
-+				opc_pref->chs[j].static_non_op = 0;
-+				opc_pref->op_ch_num++;
-+			}
-+
-+			if (l >= op_ch_num) {
-+				opc_pref->chs[j].no_ir = 0;
-+				opc_pref->ir_ch_num++;
-+			}
-+		}
-+
-+		if (opc_pref->op_ch_num)
-+			reg_op_class_num++;
-+		if (opc_pref->ir_ch_num)
-+			op_class_num++;
-+	}
-+
-+	rfctl->reg_spt_op_class_num = reg_op_class_num;
-+	rfctl->cur_spt_op_class_num = op_class_num;
-+}
-+
-+static void dump_opc_pref_single(void *sel, struct op_class_pref_t *opc_pref, bool show_snon_ocp, bool show_no_ir, bool detail)
-+{
-+	u8 i;
-+	u8 ch_num = 0;
-+	char buf[256];
-+	char *pos = buf;
-+
-+	if (!show_snon_ocp && !opc_pref->op_ch_num)
-+		return;
-+	if (!show_no_ir && !opc_pref->ir_ch_num)
-+		return;
-+
-+	for (i = 0; opc_pref->chs[i].ch != 0; i++) {
-+		if ((show_snon_ocp || !opc_pref->chs[i].static_non_op)
-+			&& (show_no_ir || !opc_pref->chs[i].no_ir)
-+		) {
-+			if (detail)
-+				pos += snprintf(pos, 256 - (pos - buf), " %4u", opc_pref->chs[i].ch);
-+			else
-+				pos += snprintf(pos, 256 - (pos - buf), " %u", opc_pref->chs[i].ch);
-+		}
-+	}
-+
-+	RTW_PRINT_SEL(sel, "%5u %4s %7s%s\n"
-+		, opc_pref->class_id
-+		, band_str(opc_pref->band)
-+		, opc_bw_str(opc_pref->bw), buf);
-+
-+	if (!detail)
-+		return;
-+
-+	pos = buf;
-+	for (i = 0; opc_pref->chs[i].ch != 0; i++) {
-+		if ((show_snon_ocp || !opc_pref->chs[i].static_non_op)
-+			&& (show_no_ir || !opc_pref->chs[i].no_ir)
-+		) {
-+			pos += snprintf(pos, 256 - (pos - buf), "   %c%c"
-+				, opc_pref->chs[i].no_ir ? ' ' : 'I'
-+				, opc_pref->chs[i].static_non_op ? ' ' : 'E'
-+			);
-+		}
-+	}
-+	RTW_PRINT_SEL(sel, "                  %s\n", buf);
-+
-+	pos = buf;
-+	for (i = 0; opc_pref->chs[i].ch != 0; i++) {
-+		if ((show_snon_ocp || !opc_pref->chs[i].static_non_op)
-+			&& (show_no_ir || !opc_pref->chs[i].no_ir)
-+		) {
-+			if (opc_pref->chs[i].max_txpwr == UNSPECIFIED_MBM)
-+				pos += snprintf(pos, 256 - (pos - buf), "     ");
-+			else
-+				pos += snprintf(pos, 256 - (pos - buf), " %4d", opc_pref->chs[i].max_txpwr);
-+		}
-+	}
-+	RTW_PRINT_SEL(sel, "                  %s\n", buf);
-+}
-+
-+void dump_cap_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool detail)
-+{
-+	u8 i;
-+
-+	dump_op_class_ch_title(sel);
-+
-+	for (i = 0; i < global_op_class_num; i++) {
-+		if (!rfctl->spt_op_class_ch[i])
-+			continue;
-+		dump_opc_pref_single(sel, rfctl->spt_op_class_ch[i], 1, 1, detail);
-+	}
-+
-+	RTW_PRINT_SEL(sel, "op_class number:%d\n", rfctl->cap_spt_op_class_num);
-+}
-+
-+void dump_reg_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool detail)
-+{
-+	u8 i;
-+
-+	dump_op_class_ch_title(sel);
-+
-+	for (i = 0; i < global_op_class_num; i++) {
-+		if (!rfctl->spt_op_class_ch[i])
-+			continue;
-+		dump_opc_pref_single(sel, rfctl->spt_op_class_ch[i], 0, 1, detail);
-+	}
-+
-+	RTW_PRINT_SEL(sel, "op_class number:%d\n", rfctl->reg_spt_op_class_num);
-+}
-+
-+void dump_cur_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool detail)
-+{
-+	u8 i;
-+
-+	dump_op_class_ch_title(sel);
-+
-+	for (i = 0; i < global_op_class_num; i++) {
-+		if (!rfctl->spt_op_class_ch[i])
-+			continue;
-+		dump_opc_pref_single(sel, rfctl->spt_op_class_ch[i], 0, 0, detail);
-+	}
-+
-+	RTW_PRINT_SEL(sel, "op_class number:%d\n", rfctl->cur_spt_op_class_num);
-+}
-+
-+const u8 _rf_type_to_rf_tx_cnt[RF_TYPE_MAX] = {
-+	[RF_1T1R] = 1,
-+	[RF_1T2R] = 1,
-+	[RF_1T3R] = 1,
-+	[RF_1T4R] = 1,
-+	[RF_2T1R] = 2,
-+	[RF_2T2R] = 2,
-+	[RF_2T3R] = 2,
-+	[RF_2T4R] = 2,
-+	[RF_3T1R] = 3,
-+	[RF_3T2R] = 3,
-+	[RF_3T3R] = 3,
-+	[RF_3T4R] = 3,
-+	[RF_4T1R] = 4,
-+	[RF_4T2R] = 4,
-+	[RF_4T3R] = 4,
-+	[RF_4T4R] = 4,
-+};
-+
-+const u8 _rf_type_to_rf_rx_cnt[RF_TYPE_MAX] = {
-+	[RF_1T1R] = 1,
-+	[RF_1T2R] = 2,
-+	[RF_1T3R] = 3,
-+	[RF_1T4R] = 4,
-+	[RF_2T1R] = 1,
-+	[RF_2T2R] = 2,
-+	[RF_2T3R] = 3,
-+	[RF_2T4R] = 4,
-+	[RF_3T1R] = 1,
-+	[RF_3T2R] = 2,
-+	[RF_3T3R] = 3,
-+	[RF_3T4R] = 4,
-+	[RF_4T1R] = 1,
-+	[RF_4T2R] = 2,
-+	[RF_4T3R] = 3,
-+	[RF_4T4R] = 4,
-+};
-+
-+const char *const _rf_type_to_rfpath_str[RF_TYPE_MAX] = {
-+	[RF_1T1R] = "RF_1T1R",
-+	[RF_1T2R] = "RF_1T2R",
-+	[RF_1T3R] = "RF_1T3R",
-+	[RF_1T4R] = "RF_1T4R",
-+	[RF_2T1R] = "RF_2T1R",
-+	[RF_2T2R] = "RF_2T2R",
-+	[RF_2T3R] = "RF_2T3R",
-+	[RF_2T4R] = "RF_2T4R",
-+	[RF_3T1R] = "RF_3T1R",
-+	[RF_3T2R] = "RF_3T2R",
-+	[RF_3T3R] = "RF_3T3R",
-+	[RF_3T4R] = "RF_3T4R",
-+	[RF_4T1R] = "RF_4T1R",
-+	[RF_4T2R] = "RF_4T2R",
-+	[RF_4T3R] = "RF_4T3R",
-+	[RF_4T4R] = "RF_4T4R",
-+};
-+
-+void rf_type_to_default_trx_bmp(enum rf_type rf, enum bb_path *tx, enum bb_path *rx)
-+{
-+	u8 tx_num = rf_type_to_rf_tx_cnt(rf);
-+	u8 rx_num = rf_type_to_rf_rx_cnt(rf);
-+	int i;
-+
-+	*tx = *rx = 0;
-+
-+	for (i = 0; i < tx_num; i++)
-+		*tx |= BIT(i);
-+	for (i = 0; i < rx_num; i++)
-+		*rx |= BIT(i);
-+}
-+
-+static const u8 _trx_num_to_rf_type[RF_PATH_MAX][RF_PATH_MAX] = {
-+	{RF_1T1R,	RF_1T2R,	RF_1T3R,	RF_1T4R},
-+	{RF_2T1R,	RF_2T2R,	RF_2T3R,	RF_2T4R},
-+	{RF_3T1R,	RF_3T2R,	RF_3T3R,	RF_3T4R},
-+	{RF_4T1R,	RF_4T2R,	RF_4T3R,	RF_4T4R},
-+};
-+
-+enum rf_type trx_num_to_rf_type(u8 tx_num, u8 rx_num)
-+{
-+	if (tx_num > 0 && tx_num <= RF_PATH_MAX && rx_num > 0 && rx_num <= RF_PATH_MAX)
-+		return _trx_num_to_rf_type[tx_num - 1][rx_num - 1];
-+	return RF_TYPE_MAX;
-+}
-+
-+enum rf_type trx_bmp_to_rf_type(u8 tx_bmp, u8 rx_bmp)
-+{
-+	u8 tx_num = 0;
-+	u8 rx_num = 0;
-+	int i;
-+
-+	for (i = 0; i < RF_PATH_MAX; i++) {
-+		if (tx_bmp >> i & BIT0)
-+			tx_num++;
-+		if (rx_bmp >> i & BIT0)
-+			rx_num++;
-+	}
-+
-+	return trx_num_to_rf_type(tx_num, rx_num);
-+}
-+
-+bool rf_type_is_a_in_b(enum rf_type a, enum rf_type b)
-+{
-+	return rf_type_to_rf_tx_cnt(a) <= rf_type_to_rf_tx_cnt(b)
-+		&& rf_type_to_rf_rx_cnt(a) <= rf_type_to_rf_rx_cnt(b);
-+}
-+
-+static void rtw_path_bmp_limit_from_higher(u8 *bmp, u8 *bmp_bit_cnt, u8 bit_cnt_lmt)
-+{
-+	int i;
-+
-+	for (i = RF_PATH_MAX - 1; *bmp_bit_cnt > bit_cnt_lmt && i >= 0; i--) {
-+		if (*bmp & BIT(i)) {
-+			*bmp &= ~BIT(i);
-+			(*bmp_bit_cnt)--;
-+		}
-+	}
-+}
-+
-+u8 rtw_restrict_trx_path_bmp_by_trx_num_lmt(u8 trx_path_bmp, u8 tx_num_lmt, u8 rx_num_lmt, u8 *tx_num, u8 *rx_num)
-+{
-+	u8 bmp_tx = (trx_path_bmp & 0xF0) >> 4;
-+	u8 bmp_rx = trx_path_bmp & 0x0F;
-+	u8 bmp_tx_num = 0, bmp_rx_num = 0;
-+	enum rf_type ret_type = RF_TYPE_MAX;
-+	int i, j;
-+
-+	for (i = 0; i < RF_PATH_MAX; i++) {
-+		if (bmp_tx & BIT(i))
-+			bmp_tx_num++;
-+		if (bmp_rx & BIT(i))
-+			bmp_rx_num++;
-+	}
-+
-+	/* limit higher bit first according to input type */
-+	if (tx_num_lmt)
-+		rtw_path_bmp_limit_from_higher(&bmp_tx, &bmp_tx_num, tx_num_lmt);
-+	if (rx_num_lmt)
-+		rtw_path_bmp_limit_from_higher(&bmp_rx, &bmp_rx_num, rx_num_lmt);
-+
-+	/* search for valid rf_type (larger RX prefer) */
-+	for (j = bmp_rx_num; j > 0; j--) {
-+		for (i = bmp_tx_num; i > 0; i--) {
-+			ret_type = trx_num_to_rf_type(i, j);
-+			if (RF_TYPE_VALID(ret_type)) {
-+				rtw_path_bmp_limit_from_higher(&bmp_tx, &bmp_tx_num, i);
-+				rtw_path_bmp_limit_from_higher(&bmp_rx, &bmp_rx_num, j);
-+				if (tx_num)
-+					*tx_num = bmp_tx_num;
-+				if (rx_num)
-+					*rx_num = bmp_rx_num;
-+				goto exit;
-+			}
-+		}
-+	}
-+
-+exit:
-+	return RF_TYPE_VALID(ret_type) ? ((bmp_tx << 4) | bmp_rx) : 0x00;
-+}
-+
-+u8 rtw_restrict_trx_path_bmp_by_rftype(u8 trx_path_bmp, enum rf_type type, u8 *tx_num, u8 *rx_num)
-+{
-+	return rtw_restrict_trx_path_bmp_by_trx_num_lmt(trx_path_bmp
-+		, rf_type_to_rf_tx_cnt(type), rf_type_to_rf_rx_cnt(type), tx_num, rx_num);
-+}
-+
-+/* config to non N-TX value, path with lower index prefer */
-+void tx_path_nss_set_default(enum bb_path txpath_nss[], u8 txpath_num_nss[], u8 txpath)
-+{
-+	int i, j;
-+	u8 cnt;
-+
-+	for (i = 4; i > 0; i--) {
-+		cnt = 0;
-+		txpath_nss[i - 1] = 0;
-+		for (j = 0; j < RF_PATH_MAX; j++) {
-+			if (txpath & BIT(j)) {
-+				txpath_nss[i - 1] |= BIT(j);
-+				if (++cnt == i)
-+					break;
-+			}
-+		}
-+		txpath_num_nss[i - 1] = i;
-+	}
-+}
-+
-+/* config to full N-TX value */
-+void tx_path_nss_set_full_tx(enum bb_path txpath_nss[], u8 txpath_num_nss[], u8 txpath)
-+{
-+	u8 tx_num = 0;
-+	int i;
-+
-+	for (i = 0; i < RF_PATH_MAX; i++)
-+		if (txpath & BIT(i))
-+			tx_num++;
-+
-+	for (i = 4; i > 0; i--) {
-+		txpath_nss[i - 1] = txpath;
-+		txpath_num_nss[i - 1] = tx_num;
-+	}
-+}
-+
-+const char *const _regd_str[] = {
-+	"NONE",
-+	"FCC",
-+	"MKK",
-+	"ETSI",
-+	"IC",
-+	"KCC",
-+	"NCC",
-+	"ACMA",
-+	"CHILE",
-+	"UKRAINE",
-+	"MEXICO",
-+	"CN",
-+	"WW",
-+};
-+
-+/*
-+* input with txpwr value in unit of txpwr index
-+* return string in length 6 at least (for -xx.xx)
-+*/
-+void txpwr_idx_get_dbm_str(s8 idx, u8 txgi_max, u8 txgi_pdbm, SIZE_T cwidth, char dbm_str[], u8 dbm_str_len)
-+{
-+	char fmt[16];
-+
-+	if (idx == txgi_max) {
-+		snprintf(fmt, 16, "%%%zus", cwidth >= 6 ? cwidth + 1 : 6);
-+		snprintf(dbm_str, dbm_str_len, fmt, "NA");
-+	} else if (idx > -txgi_pdbm && idx < 0) { /* -0.xx */
-+		snprintf(fmt, 16, "%%%zus-0.%%02d", cwidth >= 6 ? cwidth - 4 : 1);
-+		snprintf(dbm_str, dbm_str_len, fmt, "", (rtw_abs(idx) % txgi_pdbm) * 100 / txgi_pdbm);
-+	} else if (idx % txgi_pdbm) { /* d.xx */
-+		snprintf(fmt, 16, "%%%zud.%%02d", cwidth >= 6 ? cwidth - 2 : 3);
-+		snprintf(dbm_str, dbm_str_len, fmt, idx / txgi_pdbm, (rtw_abs(idx) % txgi_pdbm) * 100 / txgi_pdbm);
-+	} else { /* d */
-+		snprintf(fmt, 16, "%%%zud", cwidth >= 6 ? cwidth + 1 : 6);
-+		snprintf(dbm_str, dbm_str_len, fmt, idx / txgi_pdbm);
-+	}
-+}
-+
-+/*
-+* input with txpwr value in unit of mbm
-+* return string in length 6 at least (for -xx.xx)
-+*/
-+void txpwr_mbm_get_dbm_str(s16 mbm, SIZE_T cwidth, char dbm_str[], u8 dbm_str_len)
-+{
-+	char fmt[16];
-+
-+	if (mbm == UNSPECIFIED_MBM) {
-+		snprintf(fmt, 16, "%%%zus", cwidth >= 6 ? cwidth + 1 : 6);
-+		snprintf(dbm_str, dbm_str_len, fmt, "NA");
-+	} else if (mbm > -MBM_PDBM && mbm < 0) { /* -0.xx */
-+		snprintf(fmt, 16, "%%%zus-0.%%02d", cwidth >= 6 ? cwidth - 4 : 1);
-+		snprintf(dbm_str, dbm_str_len, fmt, "", (rtw_abs(mbm) % MBM_PDBM) * 100 / MBM_PDBM);
-+	} else if (mbm % MBM_PDBM) { /* d.xx */
-+		snprintf(fmt, 16, "%%%zud.%%02d", cwidth >= 6 ? cwidth - 2 : 3);
-+		snprintf(dbm_str, dbm_str_len, fmt, mbm / MBM_PDBM, (rtw_abs(mbm) % MBM_PDBM) * 100 / MBM_PDBM);
-+	} else { /* d */
-+		snprintf(fmt, 16, "%%%zud", cwidth >= 6 ? cwidth + 1 : 6);
-+		snprintf(dbm_str, dbm_str_len, fmt, mbm / MBM_PDBM);
-+	}
-+}
-+
-+static const s16 _mb_of_ntx[] = {
-+	0,		/* 1TX */
-+	301,	/* 2TX */
-+	477,	/* 3TX */
-+	602,	/* 4TX */
-+	699,	/* 5TX */
-+	778,	/* 6TX */
-+	845,	/* 7TX */
-+	903,	/* 8TX */
-+};
-+
-+/* get mB(100 *dB) for specifc TX count relative to 1TX */
-+s16 mb_of_ntx(u8 ntx)
-+{
-+	if (ntx == 0 || ntx > 8) {
-+		RTW_ERR("ntx=%u, out of range\n", ntx);
-+		rtw_warn_on(1);
-+	}
-+
-+	return _mb_of_ntx[ntx - 1];
-+}
-+
-+#if CONFIG_TXPWR_LIMIT
-+void _dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl)
-+{
-+	struct regd_exc_ent *ent;
-+	_list *cur, *head;
-+
-+	RTW_PRINT_SEL(sel, "regd_exc_num:%u\n", rfctl->regd_exc_num);
-+
-+	if (!rfctl->regd_exc_num)
-+		goto exit;
-+
-+	RTW_PRINT_SEL(sel, "%-7s %-6s %-9s\n", "country", "domain", "regd_name");
-+
-+	head = &rfctl->reg_exc_list;
-+	cur = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+		u8 has_country;
-+
-+		ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
-+		cur = get_next(cur);
-+		has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1;
-+
-+		RTW_PRINT_SEL(sel, "     %c%c   0x%02x %s\n"
-+			, has_country ? ent->country[0] : '0'
-+			, has_country ? ent->country[1] : '0'
-+			, ent->domain
-+			, ent->regd_name
-+		);
-+	}
-+
-+exit:
-+	return;
-+}
-+
-+inline void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl)
-+{
-+	_irqL irqL;
-+
-+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+	_dump_regd_exc_list(sel, rfctl);
-+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+}
-+
-+void rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen)
-+{
-+	struct regd_exc_ent *ent;
-+	_irqL irqL;
-+
-+	if (!regd_name || !nlen) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	ent = (struct regd_exc_ent *)rtw_zmalloc(sizeof(struct regd_exc_ent) + nlen + 1);
-+	if (!ent)
-+		goto exit;
-+
-+	_rtw_init_listhead(&ent->list);
-+	if (country)
-+		_rtw_memcpy(ent->country, country, 2);
-+	ent->domain = domain;
-+	_rtw_memcpy(ent->regd_name, regd_name, nlen);
-+
-+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+	rtw_list_insert_tail(&ent->list, &rfctl->reg_exc_list);
-+	rfctl->regd_exc_num++;
-+
-+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+exit:
-+	return;
-+}
-+
-+inline void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name)
-+{
-+	rtw_regd_exc_add_with_nlen(rfctl, country, domain, regd_name, strlen(regd_name));
-+}
-+
-+struct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain)
-+{
-+	struct regd_exc_ent *ent;
-+	_list *cur, *head;
-+	u8 match = 0;
-+
-+	head = &rfctl->reg_exc_list;
-+	cur = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+		u8 has_country;
-+
-+		ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
-+		cur = get_next(cur);
-+		has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1;
-+
-+		/* entry has country condition to match */
-+		if (has_country) {
-+			if (!country)
-+				continue;
-+			if (ent->country[0] != country[0]
-+				|| ent->country[1] != country[1])
-+				continue;
-+		}
-+
-+		/* entry has domain condition to match */
-+		if (ent->domain != 0xFF) {
-+			if (domain == 0xFF)
-+				continue;
-+			if (ent->domain != domain)
-+				continue;
-+		}
-+
-+		match = 1;
-+		break;
-+	}
-+
-+	if (match)
-+		return ent;
-+	else
-+		return NULL;
-+}
-+
-+inline struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain)
-+{
-+	struct regd_exc_ent *ent;
-+	_irqL irqL;
-+
-+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+	ent = _rtw_regd_exc_search(rfctl, country, domain);
-+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+	return ent;
-+}
-+
-+void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl)
-+{
-+	struct regd_exc_ent *ent;
-+	_irqL irqL;
-+	_list *cur, *head;
-+
-+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+	head = &rfctl->reg_exc_list;
-+	cur = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+		ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
-+		cur = get_next(cur);
-+		rtw_list_delete(&ent->list);
-+		rtw_mfree((u8 *)ent, sizeof(struct regd_exc_ent) + strlen(ent->regd_name) + 1);
-+	}
-+	rfctl->regd_exc_num = 0;
-+
-+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+}
-+
-+void dump_txpwr_lmt(void *sel, _adapter *adapter)
-+{
-+#define TMP_STR_LEN 16
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	_irqL irqL;
-+	char fmt[16];
-+	char tmp_str[TMP_STR_LEN];
-+	s8 *lmt_idx = NULL;
-+	int bw, band, ch_num, tlrs, ntx_idx, rs, i, path;
-+	u8 ch, n, rfpath_num;
-+
-+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+	_dump_regd_exc_list(sel, rfctl);
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	if (!rfctl->txpwr_regd_num)
-+		goto release_lock;
-+
-+	lmt_idx = rtw_malloc(sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num);
-+	if (!lmt_idx) {
-+		RTW_ERR("%s alloc fail\n", __func__);
-+		goto release_lock;
-+	}
-+
-+	RTW_PRINT_SEL(sel, "txpwr_lmt_2g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_2g_cck_ofdm_state);
-+	#if CONFIG_IEEE80211_BAND_5GHZ
-+	if (IS_HARDWARE_TYPE_JAGUAR_ALL(adapter)) {
-+		RTW_PRINT_SEL(sel, "txpwr_lmt_5g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_5g_cck_ofdm_state);
-+		RTW_PRINT_SEL(sel, "txpwr_lmt_5g_20_40_ref:0x%02x\n", rfctl->txpwr_lmt_5g_20_40_ref);
-+	}
-+	#endif
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
-+		if (!hal_is_band_support(adapter, band))
-+			continue;
-+
-+		rfpath_num = (band == BAND_ON_2_4G ? hal_spec->rfpath_num_2g : hal_spec->rfpath_num_5g);
-+
-+		for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; bw++) {
-+
-+			if (bw >= CHANNEL_WIDTH_160)
-+				break;
-+			if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80)
-+				break;
-+
-+			if (band == BAND_ON_2_4G)
-+				ch_num = CENTER_CH_2G_NUM;
-+			else
-+				ch_num = center_chs_5g_num(bw);
-+
-+			if (ch_num == 0) {
-+				rtw_warn_on(1);
-+				break;
-+			}
-+
-+			for (tlrs = TXPWR_LMT_RS_CCK; tlrs < TXPWR_LMT_RS_NUM; tlrs++) {
-+
-+				if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT)
-+					continue;
-+				if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK)
-+					continue;
-+				if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM))
-+					continue;
-+				if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT)
-+					continue;
-+				if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
-+					continue;
-+
-+				for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
-+					struct txpwr_lmt_ent *ent;
-+					_list *cur, *head;
-+
-+					if (ntx_idx + 1 > hal_data->max_tx_cnt)
-+						continue;
-+
-+					/* bypass CCK multi-TX is not defined */
-+					if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) {
-+						if (band == BAND_ON_2_4G
-+							&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx)))
-+							continue;
-+					}
-+
-+					/* bypass OFDM multi-TX is not defined */
-+					if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) {
-+						if (band == BAND_ON_2_4G
-+							&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
-+							continue;
-+						#if CONFIG_IEEE80211_BAND_5GHZ
-+						if (band == BAND_ON_5G
-+							&& !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
-+							continue;
-+						#endif
-+					}
-+
-+					/* bypass 5G 20M, 40M pure reference */
-+					#if CONFIG_IEEE80211_BAND_5GHZ
-+					if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) {
-+						if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) {
-+							if (tlrs == TXPWR_LMT_RS_HT)
-+								continue;
-+						} else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) {
-+							if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40)
-+								continue;
-+						}
-+					}
-+					#endif
-+
-+					/* choose n-SS mapping rate section to get lmt diff value */
-+					if (tlrs == TXPWR_LMT_RS_CCK)
-+						rs = CCK;
-+					else if (tlrs == TXPWR_LMT_RS_OFDM)
-+						rs = OFDM;
-+					else if (tlrs == TXPWR_LMT_RS_HT)
-+						rs = HT_1SS + ntx_idx;
-+					else if (tlrs == TXPWR_LMT_RS_VHT)
-+						rs = VHT_1SS + ntx_idx;
-+					else {
-+						RTW_ERR("%s invalid tlrs %u\n", __func__, tlrs);
-+						continue;
-+					}
-+
-+					RTW_PRINT_SEL(sel, "[%s][%s][%s][%uT]\n"
-+						, band_str(band)
-+						, ch_width_str(bw)
-+						, txpwr_lmt_rs_str(tlrs)
-+						, ntx_idx + 1
-+					);
-+
-+					/* header for limit in db */
-+					RTW_PRINT_SEL(sel, "%3s ", "ch");
-+
-+					head = &rfctl->txpwr_lmt_list;
-+					cur = get_next(head);
-+					while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+						ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
-+						cur = get_next(cur);
-+
-+						sprintf(fmt, "%%%zus%%s ", strlen(ent->regd_name) >= 6 ? 1 : 6 - strlen(ent->regd_name));
-+						snprintf(tmp_str, TMP_STR_LEN, fmt
-+							, strcmp(ent->regd_name, rfctl->regd_name) == 0 ? "*" : ""
-+							, ent->regd_name);
-+						_RTW_PRINT_SEL(sel, "%s", tmp_str);
-+					}
-+					sprintf(fmt, "%%%zus%%s ", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? 1 : 6 - strlen(regd_str(TXPWR_LMT_WW)));
-+					snprintf(tmp_str, TMP_STR_LEN, fmt
-+						, strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? "*" : ""
-+						, regd_str(TXPWR_LMT_WW));
-+					_RTW_PRINT_SEL(sel, "%s", tmp_str);
-+
-+					/* header for limit offset */
-+					for (path = 0; path < RF_PATH_MAX; path++) {
-+						if (path >= rfpath_num)
-+							break;
-+						_RTW_PRINT_SEL(sel, "|");
-+						head = &rfctl->txpwr_lmt_list;
-+						cur = get_next(head);
-+						while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+							ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
-+							cur = get_next(cur);
-+							_RTW_PRINT_SEL(sel, "%3c "
-+								, strcmp(ent->regd_name, rfctl->regd_name) == 0 ? rf_path_char(path) : ' ');
-+						}
-+						_RTW_PRINT_SEL(sel, "%3c "
-+								, strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? rf_path_char(path) : ' ');
-+					}
-+					_RTW_PRINT_SEL(sel, "\n");
-+
-+					for (n = 0; n < ch_num; n++) {
-+						s8 lmt;
-+						s8 lmt_offset;
-+						u8 base;
-+
-+						if (band == BAND_ON_2_4G)
-+							ch = n + 1;
-+						else
-+							ch = center_chs_5g(bw, n);
-+
-+						if (ch == 0) {
-+							rtw_warn_on(1);
-+							break;
-+						}
-+
-+						/* dump limit in dBm */
-+						RTW_PRINT_SEL(sel, "%3u ", ch);
-+						head = &rfctl->txpwr_lmt_list;
-+						cur = get_next(head);
-+						while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+							ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
-+							cur = get_next(cur);
-+							lmt = phy_get_txpwr_lmt(adapter, ent->regd_name, band, bw, tlrs, ntx_idx, ch, 0);
-+							txpwr_idx_get_dbm_str(lmt, hal_spec->txgi_max, hal_spec->txgi_pdbm, strlen(ent->regd_name), tmp_str, TMP_STR_LEN);
-+							_RTW_PRINT_SEL(sel, "%s ", tmp_str);
-+						}
-+						lmt = phy_get_txpwr_lmt(adapter, regd_str(TXPWR_LMT_WW), band, bw, tlrs, ntx_idx, ch, 0);
-+						txpwr_idx_get_dbm_str(lmt, hal_spec->txgi_max, hal_spec->txgi_pdbm, strlen(regd_str(TXPWR_LMT_WW)), tmp_str, TMP_STR_LEN);
-+						_RTW_PRINT_SEL(sel, "%s ", tmp_str);
-+
-+						/* dump limit offset of each path */
-+						for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
-+							if (path >= rfpath_num)
-+								break;
-+
-+							base = phy_get_target_txpwr(adapter, band, path, rs);
-+
-+							_RTW_PRINT_SEL(sel, "|");
-+							head = &rfctl->txpwr_lmt_list;
-+							cur = get_next(head);
-+							i = 0;
-+							while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+								ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
-+								cur = get_next(cur);
-+								lmt_offset = phy_get_txpwr_lmt_diff(adapter, ent->regd_name, band, bw, path, rs, tlrs, ntx_idx, ch, 0);
-+								if (lmt_offset == hal_spec->txgi_max) {
-+									*(lmt_idx + i * RF_PATH_MAX + path) = hal_spec->txgi_max;
-+									_RTW_PRINT_SEL(sel, "%3s ", "NA");
-+								} else {
-+									*(lmt_idx + i * RF_PATH_MAX + path) = lmt_offset + base;
-+									_RTW_PRINT_SEL(sel, "%3d ", lmt_offset);
-+								}
-+								i++;
-+							}
-+							lmt_offset = phy_get_txpwr_lmt_diff(adapter, regd_str(TXPWR_LMT_WW), band, bw, path, rs, tlrs, ntx_idx, ch, 0);
-+							if (lmt_offset == hal_spec->txgi_max)
-+								_RTW_PRINT_SEL(sel, "%3s ", "NA");
-+							else
-+								_RTW_PRINT_SEL(sel, "%3d ", lmt_offset);
-+
-+						}
-+
-+						/* compare limit_idx of each path, print 'x' when mismatch */
-+						if (rfpath_num > 1) {
-+							for (i = 0; i < rfctl->txpwr_regd_num; i++) {
-+								for (path = 0; path < RF_PATH_MAX; path++) {
-+									if (path >= rfpath_num)
-+										break;
-+									if (*(lmt_idx + i * RF_PATH_MAX + path) != *(lmt_idx + i * RF_PATH_MAX + ((path + 1) % rfpath_num)))
-+										break;
-+								}
-+								if (path >= rfpath_num)
-+									_RTW_PRINT_SEL(sel, " ");
-+								else
-+									_RTW_PRINT_SEL(sel, "x");
-+							}
-+						}
-+						_RTW_PRINT_SEL(sel, "\n");
-+
-+					}
-+					RTW_PRINT_SEL(sel, "\n");
-+				}
-+			} /* loop for rate sections */
-+		} /* loop for bandwidths */
-+	} /* loop for bands */
-+
-+	if (lmt_idx)
-+		rtw_mfree(lmt_idx, sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num);
-+
-+release_lock:
-+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+}
-+
-+/* search matcing first, if not found, alloc one */
-+void rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen
-+	, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj_get_primary_adapter(rfctl_to_dvobj(rfctl)));
-+	struct txpwr_lmt_ent *ent;
-+	_irqL irqL;
-+	_list *cur, *head;
-+	s8 pre_lmt;
-+
-+	if (!regd_name || !nlen) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+	/* search for existed entry */
-+	head = &rfctl->txpwr_lmt_list;
-+	cur = get_next(head);
-+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
-+		cur = get_next(cur);
-+
-+		if (strlen(ent->regd_name) == nlen
-+			&& _rtw_memcmp(ent->regd_name, regd_name, nlen) == _TRUE)
-+			goto chk_lmt_val;
-+	}
-+
-+	/* alloc new one */
-+	ent = (struct txpwr_lmt_ent *)rtw_zvmalloc(sizeof(struct txpwr_lmt_ent) + nlen + 1);
-+	if (!ent)
-+		goto release_lock;
-+
-+	_rtw_init_listhead(&ent->list);
-+	_rtw_memcpy(ent->regd_name, regd_name, nlen);
-+	{
-+		u8 j, k, l, m;
-+
-+		for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
-+			for (k = 0; k < TXPWR_LMT_RS_NUM_2G; ++k)
-+				for (m = 0; m < CENTER_CH_2G_NUM; ++m)
-+					for (l = 0; l < MAX_TX_COUNT; ++l)
-+						ent->lmt_2g[j][k][m][l] = hal_spec->txgi_max;
-+		#if CONFIG_IEEE80211_BAND_5GHZ
-+		for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j)
-+			for (k = 0; k < TXPWR_LMT_RS_NUM_5G; ++k)
-+				for (m = 0; m < CENTER_CH_5G_ALL_NUM; ++m)
-+					for (l = 0; l < MAX_TX_COUNT; ++l)
-+						ent->lmt_5g[j][k][m][l] = hal_spec->txgi_max;
-+		#endif
-+	}
-+
-+	rtw_list_insert_tail(&ent->list, &rfctl->txpwr_lmt_list);
-+	rfctl->txpwr_regd_num++;
-+
-+chk_lmt_val:
-+	if (band == BAND_ON_2_4G)
-+		pre_lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx];
-+	#if CONFIG_IEEE80211_BAND_5GHZ
-+	else if (band == BAND_ON_5G)
-+		pre_lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx];
-+	#endif
-+	else
-+		goto release_lock;
-+
-+	if (pre_lmt != hal_spec->txgi_max)
-+		RTW_PRINT("duplicate txpwr_lmt for [%s][%s][%s][%s][%uT][%d]\n"
-+			, regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1
-+			, band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]);
-+
-+	lmt = rtw_min(pre_lmt, lmt);
-+	if (band == BAND_ON_2_4G)
-+		ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] = lmt;
-+	#if CONFIG_IEEE80211_BAND_5GHZ
-+	else if (band == BAND_ON_5G)
-+		ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] = lmt;
-+	#endif
-+
-+	if (0)
-+		RTW_PRINT("%s, %4s, %6s, %7s, %uT, ch%3d = %d\n"
-+			, regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1
-+			, band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]
-+			, lmt);
-+
-+release_lock:
-+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+exit:
-+	return;
-+}
-+
-+inline void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name
-+	, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt)
-+{
-+	rtw_txpwr_lmt_add_with_nlen(rfctl, regd_name, strlen(regd_name)
-+		, band, bw, tlrs, ntx_idx, ch_idx, lmt);
-+}
-+
-+struct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name)
-+{
-+	struct txpwr_lmt_ent *ent;
-+	_list *cur, *head;
-+	u8 found = 0;
-+
-+	head = &rfctl->txpwr_lmt_list;
-+	cur = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
-+		cur = get_next(cur);
-+
-+		if (strcmp(ent->regd_name, regd_name) == 0) {
-+			found = 1;
-+			break;
-+		}
-+	}
-+
-+	if (found)
-+		return ent;
-+	return NULL;
-+}
-+
-+inline struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name)
-+{
-+	struct txpwr_lmt_ent *ent;
-+	_irqL irqL;
-+
-+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+	ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name);
-+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+	return ent;
-+}
-+
-+void rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl)
-+{
-+	struct txpwr_lmt_ent *ent;
-+	_irqL irqL;
-+	_list *cur, *head;
-+
-+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+	head = &rfctl->txpwr_lmt_list;
-+	cur = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
-+		cur = get_next(cur);
-+		if (ent->regd_name == rfctl->regd_name)
-+			rfctl->regd_name = regd_str(TXPWR_LMT_NONE);
-+		rtw_list_delete(&ent->list);
-+		rtw_vmfree((u8 *)ent, sizeof(struct txpwr_lmt_ent) + strlen(ent->regd_name) + 1);
-+	}
-+	rfctl->txpwr_regd_num = 0;
-+
-+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+}
-+#endif /* CONFIG_TXPWR_LIMIT */
-+
-+int rtw_ch_to_bb_gain_sel(int ch)
-+{
-+	int sel = -1;
-+
-+	if (ch >= 1 && ch <= 14)
-+		sel = BB_GAIN_2G;
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	else if (ch >= 36 && ch < 48)
-+		sel = BB_GAIN_5GLB1;
-+	else if (ch >= 52 && ch <= 64)
-+		sel = BB_GAIN_5GLB2;
-+	else if (ch >= 100 && ch <= 120)
-+		sel = BB_GAIN_5GMB1;
-+	else if (ch >= 124 && ch <= 144)
-+		sel = BB_GAIN_5GMB2;
-+	else if (ch >= 149 && ch <= 177)
-+		sel = BB_GAIN_5GHB;
-+#endif
-+
-+	return sel;
-+}
-+
-+s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch)
-+{
-+	s8 kfree_offset = 0;
-+
-+#ifdef CONFIG_RF_POWER_TRIM
-+	struct kfree_data_t *kfree_data = GET_KFREE_DATA(padapter);
-+	s8 bb_gain_sel = rtw_ch_to_bb_gain_sel(ch);
-+
-+	if (bb_gain_sel < BB_GAIN_2G || bb_gain_sel >= BB_GAIN_NUM) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (kfree_data->flag & KFREE_FLAG_ON) {
-+		kfree_offset = kfree_data->bb_gain[bb_gain_sel][path];
-+		if (IS_HARDWARE_TYPE_8723D(padapter))
-+			RTW_INFO("%s path:%s, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
-+				, __func__, (path == 0)?"S1":"S0", 
-+				ch, bb_gain_sel, kfree_offset);
-+		else
-+			RTW_INFO("%s path:%u, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
-+				, __func__, path, ch, bb_gain_sel, kfree_offset);
-+	}
-+exit:
-+#endif /* CONFIG_RF_POWER_TRIM */
-+	return kfree_offset;
-+}
-+
-+void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset)
-+{
-+#if !defined(CONFIG_RTL8814A) && !defined(CONFIG_RTL8822B) && !defined(CONFIG_RTL8821C) && !defined(CONFIG_RTL8822C) \
-+    && !defined(CONFIG_RTL8723F)
-+	u8 write_value;
-+#endif
-+	u8 target_path = 0;
-+	u32 val32 = 0;
-+
-+	if (IS_HARDWARE_TYPE_8723D(adapter)) {
-+		target_path = RF_PATH_A; /*in 8723D case path means S0/S1*/
-+		if (path == PPG_8723D_S1)
-+			RTW_INFO("kfree gain_offset 0x55:0x%x ",
-+			rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
-+		else if (path == PPG_8723D_S0)
-+			RTW_INFO("kfree gain_offset 0x65:0x%x ",
-+			rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff));
-+	} else {
-+		target_path = path;
-+		RTW_INFO("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
-+	}
-+	
-+	switch (rtw_get_chip_type(adapter)) {
-+#ifdef CONFIG_RTL8723D
-+	case RTL8723D:
-+		write_value = RF_TX_GAIN_OFFSET_8723D(offset);
-+		if (path == PPG_8723D_S1)
-+			rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
-+		else if (path == PPG_8723D_S0)
-+			rtw_hal_write_rfreg(adapter, target_path, 0x65, 0x0f8000, write_value);
-+		break;
-+#endif /* CONFIG_RTL8723D */
-+#ifdef CONFIG_RTL8703B
-+	case RTL8703B:
-+		write_value = RF_TX_GAIN_OFFSET_8703B(offset);
-+		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);
-+		break;
-+#endif /* CONFIG_RTL8703B */
-+#ifdef CONFIG_RTL8188F
-+	case RTL8188F:
-+		write_value = RF_TX_GAIN_OFFSET_8188F(offset);
-+		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);
-+		break;
-+#endif /* CONFIG_RTL8188F */
-+#ifdef CONFIG_RTL8188GTV
-+	case RTL8188GTV:
-+		write_value = RF_TX_GAIN_OFFSET_8188GTV(offset);
-+		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);
-+		break;
-+#endif /* CONFIG_RTL8188GTV */
-+#ifdef CONFIG_RTL8192E
-+	case RTL8192E:
-+		write_value = RF_TX_GAIN_OFFSET_8192E(offset);
-+		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
-+		break;
-+#endif /* CONFIG_RTL8188F */
-+
-+#ifdef CONFIG_RTL8821A
-+	case RTL8821:
-+		write_value = RF_TX_GAIN_OFFSET_8821A(offset);
-+		rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
-+		break;
-+#endif /* CONFIG_RTL8821A */
-+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822C) \
-+    || defined(CONFIG_RTL8723F)
-+	case RTL8814A:
-+	case RTL8822B:
-+	case RTL8822C:	
-+	case RTL8821C:
-+	case RTL8192F:
-+	case RTL8723F:
-+		RTW_INFO("\nkfree by PhyDM on the sw CH. path %d\n", path);
-+		break;
-+#endif /* CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C || CONFIG_RTL8723F */
-+
-+	default:
-+		rtw_warn_on(1);
-+		break;
-+	}
-+	
-+	if (IS_HARDWARE_TYPE_8723D(adapter)) {
-+		if (path == PPG_8723D_S1)
-+			val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
-+		else if (path == PPG_8723D_S0)
-+			val32 = rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff);
-+	} else {
-+		val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
-+	}
-+	RTW_INFO(" after :0x%x\n", val32);
-+}
-+
-+void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	s8 kfree_offset = 0;
-+	s8 tx_pwr_track_offset = 0; /* TODO: 8814A should consider tx pwr track when setting tx gain offset */
-+	s8 total_offset;
-+	int i, total = 0;
-+
-+	if (IS_HARDWARE_TYPE_8723D(adapter))
-+		total = 2; /* S1 and S0 */
-+	else
-+		total = hal_spec->rf_reg_path_num;
-+
-+	for (i = 0; i < total; i++) {
-+		kfree_offset = rtw_rf_get_kfree_tx_gain_offset(adapter, i, ch);
-+		total_offset = kfree_offset + tx_pwr_track_offset;
-+		rtw_rf_set_tx_gain_offset(adapter, i, total_offset);
-+	}
-+}
-+
-+bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region)
-+{
-+	return (dfs_region == RTW_DFS_REGD_ETSI && rtw_is_range_overlap(hi, lo, 5650, 5600)) ? _TRUE : _FALSE;
-+}
-+
-+bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region)
-+{
-+	u32 hi, lo;
-+
-+	if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
-+		return _FALSE;
-+
-+	return rtw_is_long_cac_range(hi, lo, dfs_region) ? _TRUE : _FALSE;
-+}
-diff --git a/drivers/staging/rtl8723cs/core/rtw_rm.c b/drivers/staging/rtl8723cs/core/rtw_rm.c
-new file mode 100644
-index 000000000000..38ceb2e265fe
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_rm.c
-@@ -0,0 +1,2825 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+#ifdef CONFIG_RTW_80211K
-+#include "rtw_rm_fsm.h"
-+#include "rtw_rm_util.h"
-+#endif
-+
-+#define pstr(s) s+strlen(s)
-+#ifndef MIN
-+#define MIN(x, y) (((x) < (y)) ? (x) : (y))
-+#endif
-+
-+u8 rm_post_event_hdl(_adapter *padapter, u8 *pbuf)
-+{
-+#ifdef CONFIG_RTW_80211K
-+	struct rm_event *pev = (struct rm_event *)pbuf;
-+
-+	_rm_post_event(padapter, pev->rmid, pev->evid);
-+	rm_handler(padapter, pev);
-+#endif
-+	return H2C_SUCCESS;
-+}
-+
-+#ifdef CONFIG_RTW_80211K
-+struct cmd_meas_type_ {
-+	u8 id;
-+	char *name;
-+};
-+
-+char *rm_type_req_name(u8 meas_type) {
-+
-+	switch (meas_type) {
-+	case basic_req:
-+		return "basic_req";
-+	case cca_req:
-+		return "cca_req";
-+	case rpi_histo_req:
-+		return "rpi_histo_req";
-+	case ch_load_req:
-+		return "ch_load_req";
-+	case noise_histo_req:
-+		return "noise_histo_req";
-+	case bcn_req:
-+		return "bcn_req";
-+	case frame_req:
-+		return "frame_req";
-+	case sta_statis_req:
-+		return "sta_statis_req";
-+	}
-+	return "unknown_req";
-+};
-+
-+char *rm_type_rep_name(u8 meas_type) {
-+
-+	switch (meas_type) {
-+	case basic_rep:
-+		return "basic_rep";
-+	case cca_rep:
-+		return "cca_rep";
-+	case rpi_histo_rep:
-+		return "rpi_histo_rep";
-+	case ch_load_rep:
-+		return "ch_load_rep";
-+	case noise_histo_rep:
-+		return "noise_histo_rep";
-+	case bcn_rep:
-+		return "bcn_rep";
-+	case frame_rep:
-+		return "frame_rep";
-+	case sta_statis_rep:
-+		return "sta_statis_rep";
-+	}
-+	return "unknown_rep";
-+};
-+
-+char *rm_en_cap_name(enum rm_cap_en en)
-+{
-+	switch (en) {
-+	case RM_LINK_MEAS_CAP_EN:
-+		return "RM_LINK_MEAS_CAP_EN";
-+	case RM_NB_REP_CAP_EN:
-+		return "RM_NB_REP_CAP_EN";
-+	case RM_PARAL_MEAS_CAP_EN:
-+		return "RM_PARAL_MEAS_CAP_EN";
-+	case RM_REPEAT_MEAS_CAP_EN:
-+		return "RM_REPEAT_MEAS_CAP_EN";
-+	case RM_BCN_PASSIVE_MEAS_CAP_EN:
-+		return "RM_BCN_PASSIVE_MEAS_CAP_EN";
-+	case RM_BCN_ACTIVE_MEAS_CAP_EN:
-+		return "RM_BCN_ACTIVE_MEAS_CAP_EN";
-+	case RM_BCN_TABLE_MEAS_CAP_EN:
-+		return "RM_BCN_TABLE_MEAS_CAP_EN";
-+	case RM_BCN_MEAS_REP_COND_CAP_EN:
-+		return "RM_BCN_MEAS_REP_COND_CAP_EN";
-+
-+	case RM_FRAME_MEAS_CAP_EN:
-+		return "RM_FRAME_MEAS_CAP_EN";
-+	case RM_CH_LOAD_CAP_EN:
-+		return "RM_CH_LOAD_CAP_EN";
-+	case RM_NOISE_HISTO_CAP_EN:
-+		return "RM_NOISE_HISTO_CAP_EN";
-+	case RM_STATIS_MEAS_CAP_EN:
-+		return "RM_STATIS_MEAS_CAP_EN";
-+	case RM_LCI_MEAS_CAP_EN:
-+		return "RM_LCI_MEAS_CAP_EN";
-+	case RM_LCI_AMIMUTH_CAP_EN:
-+		return "RM_LCI_AMIMUTH_CAP_EN";
-+	case RM_TRANS_STREAM_CAT_MEAS_CAP_EN:
-+		return "RM_TRANS_STREAM_CAT_MEAS_CAP_EN";
-+	case RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN:
-+		return "RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN";
-+
-+	case RM_AP_CH_REP_CAP_EN:
-+		return "RM_AP_CH_REP_CAP_EN";
-+	case RM_RM_MIB_CAP_EN:
-+		return "RM_RM_MIB_CAP_EN";
-+	case RM_OP_CH_MAX_MEAS_DUR0:
-+		return "RM_OP_CH_MAX_MEAS_DUR0";
-+	case RM_OP_CH_MAX_MEAS_DUR1:
-+		return "RM_OP_CH_MAX_MEAS_DUR1";
-+	case RM_OP_CH_MAX_MEAS_DUR2:
-+		return "RM_OP_CH_MAX_MEAS_DUR2";
-+	case RM_NONOP_CH_MAX_MEAS_DUR0:
-+		return "RM_NONOP_CH_MAX_MEAS_DUR0";
-+	case RM_NONOP_CH_MAX_MEAS_DUR1:
-+		return "RM_NONOP_CH_MAX_MEAS_DUR1";
-+	case RM_NONOP_CH_MAX_MEAS_DUR2:
-+		return "RM_NONOP_CH_MAX_MEAS_DUR2";
-+
-+	case RM_MEAS_PILOT_CAP0:
-+		return "RM_MEAS_PILOT_CAP0";		/* 24-26 */
-+	case RM_MEAS_PILOT_CAP1:
-+		return "RM_MEAS_PILOT_CAP1";
-+	case RM_MEAS_PILOT_CAP2:
-+		return "RM_MEAS_PILOT_CAP2";
-+	case RM_MEAS_PILOT_TRANS_INFO_CAP_EN:
-+		return "RM_MEAS_PILOT_TRANS_INFO_CAP_EN";
-+	case RM_NB_REP_TSF_OFFSET_CAP_EN:
-+		return "RM_NB_REP_TSF_OFFSET_CAP_EN";
-+	case RM_RCPI_MEAS_CAP_EN:
-+		return "RM_RCPI_MEAS_CAP_EN";		/* 29 */
-+	case RM_RSNI_MEAS_CAP_EN:
-+		return "RM_RSNI_MEAS_CAP_EN";
-+	case RM_BSS_AVG_ACCESS_DELAY_CAP_EN:
-+		return "RM_BSS_AVG_ACCESS_DELAY_CAP_EN";
-+
-+	case RM_AVALB_ADMIS_CAPACITY_CAP_EN:
-+		return "RM_AVALB_ADMIS_CAPACITY_CAP_EN";
-+	case RM_ANT_CAP_EN:
-+		return "RM_ANT_CAP_EN";
-+	case RM_RSVD:
-+	case RM_MAX:
-+	default:
-+		break;
-+	}
-+	return "unknown";
-+}
-+
-+int rm_en_cap_chk_and_set(struct rm_obj *prm, enum rm_cap_en en)
-+{
-+	int idx;
-+	u8 cap;
-+
-+
-+	if (en >= RM_MAX)
-+		return _FALSE;
-+
-+	idx = en / 8;
-+	cap = prm->psta->padapter->rmpriv.rm_en_cap_def[idx];
-+
-+	if (!(cap & BIT(en - (idx*8)))) {
-+		RTW_INFO("RM: %s incapable\n",rm_en_cap_name(en));
-+		rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
-+		return _FALSE;
-+	}
-+	return _SUCCESS;
-+}
-+
-+/* for caller outside rm */
-+u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta)
-+{
-+	struct rm_obj *prm;
-+
-+
-+	prm = rm_alloc_rmobj(padapter);
-+
-+	if (prm == NULL) {
-+		RTW_ERR("RM: unable to alloc rm obj for requeset\n");
-+		return _FALSE;
-+	}
-+
-+	prm->psta = psta;
-+	prm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS;
-+	prm->q.diag_token = rm_gen_dialog_token(padapter);
-+	prm->q.m_token = rm_gen_meas_token(padapter);
-+	prm->rmid = rm_gen_rmid(padapter, prm, RM_MASTER);
-+
-+	prm->q.action_code = RM_ACT_NB_REP_REQ;
-+
-+	#if 0
-+	if (pmac) { /* find sta_info according to bssid */
-+		pmac += 4; /* skip mac= */
-+		if (hwaddr_parse(pmac, bssid) == NULL) {
-+			sprintf(pstr(s), "Err: \nincorrect mac format\n");
-+			return _FAIL;
-+		}
-+		psta = rm_get_sta(padapter, 0xff, bssid);
-+	}
-+	#endif
-+
-+	/* enquee rmobj */
-+	rm_enqueue_rmobj(padapter, prm, _FALSE);
-+
-+	RTW_INFO("RM: rmid=%x add req to " MAC_FMT "\n",
-+		prm->rmid, MAC_ARG(psta->cmn.mac_addr));
-+
-+	return _SUCCESS;
-+}
-+
-+static u8 *build_wlan_hdr(_adapter *padapter, struct xmit_frame *pmgntframe,
-+	struct sta_info *psta, u16 frame_type)
-+{
-+	u8 *pframe;
-+	u16 *fctrl;
-+	struct pkt_attrib *pattr;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
-+
-+
-+	/* update attribute */
-+	pattr = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattr);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3,
-+		get_my_bssid(&(pmlmeinfo->network)),ETH_ALEN);
-+
-+	RTW_INFO("RM: dst = " MAC_FMT "\n", MAC_ARG(pwlanhdr->addr1));
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	SetFragNum(pframe, 0);
-+
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattr->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	return pframe;
-+}
-+
-+void rm_set_rep_mode(struct rm_obj *prm, u8 mode)
-+{
-+
-+	RTW_INFO("RM: rmid=%x set %s\n",
-+		prm->rmid,
-+		mode|MEAS_REP_MOD_INCAP?"INCAP":
-+		mode|MEAS_REP_MOD_REFUSE?"REFUSE":
-+		mode|MEAS_REP_MOD_LATE?"LATE":"");
-+
-+	prm->p.m_mode |= mode;
-+}
-+
-+int issue_null_reply(struct rm_obj *prm)
-+{
-+	int len=0, my_len;
-+	u8 *pframe, m_mode;
-+	_adapter *padapter = prm->psta->padapter;
-+	struct pkt_attrib *pattr;
-+	struct xmit_frame *pmgntframe;
-+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
-+
-+
-+	m_mode = prm->p.m_mode;
-+	if (m_mode || prm->p.rpt == 0) {
-+		RTW_INFO("RM: rmid=%x reply (%s repeat=%d)\n",
-+			prm->rmid,
-+			m_mode&MEAS_REP_MOD_INCAP?"INCAP":
-+			m_mode&MEAS_REP_MOD_REFUSE?"REFUSE":
-+			m_mode&MEAS_REP_MOD_LATE?"LATE":"no content",
-+			prm->p.rpt);
-+	}
-+
-+	switch (prm->p.action_code) {
-+	case RM_ACT_RADIO_MEAS_REQ:
-+		len = 8;
-+		break;
-+	case RM_ACT_NB_REP_REQ:
-+		len = 3;
-+		break;
-+	case RM_ACT_LINK_MEAS_REQ:
-+		len = 3;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (len==0)
-+		return _FALSE;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL) {
-+		RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
-+		return _FALSE;
-+	}
-+	pattr = &pmgntframe->attrib;
-+	pframe = build_wlan_hdr(padapter, pmgntframe, prm->psta, WIFI_ACTION);
-+	pframe = rtw_set_fixed_ie(pframe, 3, &prm->p.category, &pattr->pktlen);
-+
-+	my_len = 0;
-+	if (len>5) {
-+		prm->p.len = len - 3 - 2;
-+		pframe = rtw_set_fixed_ie(pframe, len - 3,
-+			&prm->p.e_id, &my_len);
-+	}
-+
-+	pattr->pktlen += my_len;
-+	pattr->last_txcmdsz = pattr->pktlen;
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return _SUCCESS;
-+}
-+
-+int ready_for_scan(struct rm_obj *prm)
-+{
-+	_adapter *padapter = prm->psta->padapter;
-+	u8 ssc_chk;
-+
-+	if (!rtw_is_adapter_up(padapter))
-+		return _FALSE;
-+
-+	ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
-+
-+	if (ssc_chk == SS_ALLOW)
-+		return _SUCCESS;
-+
-+	return _FALSE;
-+}
-+
-+int rm_sitesurvey(struct rm_obj *prm)
-+{
-+	int meas_ch_amount=0;
-+	u8 op_class=0, val8;
-+	struct rtw_ieee80211_channel *pch_set;
-+	struct sitesurvey_parm parm;
-+
-+
-+	RTW_INFO("RM: rmid=%x %s\n",prm->rmid, __func__);
-+
-+	pch_set = &prm->q.ch_set[0];
-+
-+	_rtw_memset(pch_set, 0,
-+		sizeof(struct rtw_ieee80211_channel) * RTW_CHANNEL_SCAN_AMOUNT);
-+
-+	op_class = prm->q.op_class;
-+	if (prm->q.ch_num == 0) {
-+		/* ch_num=0   : scan all ch in operating class */
-+		meas_ch_amount = rm_get_ch_set(pch_set,
-+			op_class, prm->q.ch_num);
-+
-+	} else if (prm->q.ch_num == 255) {
-+		/* 802.11 p.1066 */
-+		/* ch_num=255 : If the Channel Number is 255 and includes
-+		 * AP Channel Report subelements
-+		 */
-+		meas_ch_amount = rm_get_ch_set_from_bcn_req_opt(pch_set, &prm->q.opt.bcn);
-+	} else
-+		meas_ch_amount = rm_get_ch_set(pch_set, op_class, prm->q.ch_num);
-+
-+	/* get means channel */
-+	prm->q.ch_set_ch_amount = meas_ch_amount;
-+
-+#if (RM_MORE_DBG_MSG)
-+	RTW_INFO("survey (%d) chaannels\n", meas_ch_amount);
-+#endif
-+
-+	_rtw_memset(&parm, 0, sizeof(struct sitesurvey_parm));
-+	_rtw_memcpy(parm.ch, pch_set,
-+		sizeof(struct rtw_ieee80211_channel) *
-+			MIN(meas_ch_amount, RTW_CHANNEL_SCAN_AMOUNT));
-+
-+	_rtw_memcpy(&parm.ssid[0], &prm->q.opt.bcn.ssid, IW_ESSID_MAX_SIZE);
-+
-+	parm.ssid_num = 1;
-+	parm.scan_mode = prm->q.m_mode;
-+	parm.ch_num = meas_ch_amount;
-+	parm.igi = 0;
-+	parm.token = prm->rmid;
-+	parm.duration = prm->q.meas_dur;
-+	/* parm.bw = BW_20M; */
-+
-+	rtw_sitesurvey_cmd(prm->psta->padapter, &parm);
-+
-+	return _SUCCESS;
-+}
-+
-+static int rm_parse_ch_load_s_elem(struct rm_obj *prm, u8 *pbody, int req_len)
-+{
-+	u8 *popt_id;
-+	int i, p=0; /* position */
-+	int len = req_len;
-+
-+
-+	prm->q.opt_s_elem_len = len;
-+#if (RM_MORE_DBG_MSG)
-+	RTW_INFO("RM: opt_s_elem_len=%d\n", len);
-+#endif
-+	while (len) {
-+
-+		switch (pbody[p]) {
-+		case ch_load_rep_info:
-+			/* check RM_EN */
-+			rm_en_cap_chk_and_set(prm, RM_CH_LOAD_CAP_EN);
-+
-+			_rtw_memcpy(&(prm->q.opt.clm.rep_cond),
-+				&pbody[p+2], sizeof(prm->q.opt.clm.rep_cond));
-+
-+			RTW_INFO("RM: ch_load_rep_info=%u:%u\n",
-+				prm->q.opt.clm.rep_cond.cond,
-+				prm->q.opt.clm.rep_cond.threshold);
-+			break;
-+		default:
-+			break;
-+
-+		}
-+		len = len - (int)pbody[p+1] - 2;
-+		p = p + (int)pbody[p+1] + 2;
-+#if (RM_MORE_DBG_MSG)
-+		RTW_INFO("RM: opt_s_elem_len=%d\n",len);
-+#endif
-+	}
-+	return _SUCCESS;
-+}
-+
-+static int rm_parse_noise_histo_s_elem(struct rm_obj *prm,
-+	u8 *pbody, int req_len)
-+{
-+	u8 *popt_id;
-+	int i, p=0; /* position */
-+	int len = req_len;
-+
-+
-+	prm->q.opt_s_elem_len = len;
-+#if (RM_MORE_DBG_MSG)
-+	RTW_INFO("RM: opt_s_elem_len=%d\n", len);
-+#endif
-+
-+	while (len) {
-+
-+		switch (pbody[p]) {
-+		case noise_histo_rep_info:
-+			/* check RM_EN */
-+			rm_en_cap_chk_and_set(prm, RM_NOISE_HISTO_CAP_EN);
-+
-+			_rtw_memcpy(&(prm->q.opt.nhm.rep_cond),
-+				&pbody[p+2], sizeof(prm->q.opt.nhm.rep_cond));
-+
-+			RTW_INFO("RM: noise_histo_rep_info=%u:%u\n",
-+				prm->q.opt.nhm.rep_cond.cond,
-+				prm->q.opt.nhm.rep_cond.threshold);
-+			break;
-+		default:
-+			break;
-+
-+       		}
-+		len = len - (int)pbody[p+1] - 2;
-+		p = p + (int)pbody[p+1] + 2;
-+#if (RM_MORE_DBG_MSG)
-+		RTW_INFO("RM: opt_s_elem_len=%d\n",len);
-+#endif
-+	}
-+	return _SUCCESS;
-+}
-+
-+static int rm_parse_bcn_req_s_elem(struct rm_obj *prm, u8 *pbody, int req_len)
-+{
-+	u8 *popt_id;
-+	int i, p=0; /* position */
-+	int len = req_len;
-+	int ap_ch_rpt_idx = 0;
-+	struct _RT_OPERATING_CLASS *op;
-+
-+
-+	/* opt length,2:pbody[0]+ pbody[1] */
-+	/* first opt id : pbody[18] */
-+
-+	prm->q.opt_s_elem_len = len;
-+#if (RM_MORE_DBG_MSG)
-+	RTW_INFO("RM: opt_s_elem_len=%d\n", len);
-+#endif
-+
-+	popt_id = prm->q.opt.bcn.opt_id;
-+	while (len && prm->q.opt.bcn.opt_id_num < BCN_REQ_OPT_MAX_NUM) {
-+
-+		switch (pbody[p]) {
-+		case bcn_req_ssid:
-+			RTW_INFO("bcn_req_ssid\n");
-+
-+#if (DBG_BCN_REQ_WILDCARD)
-+			RTW_INFO("DBG set ssid to WILDCARD\n");
-+#else
-+#if (DBG_BCN_REQ_SSID)
-+			RTW_INFO("DBG set ssid to %s\n",DBG_BCN_REQ_SSID_NAME);
-+			i = strlen(DBG_BCN_REQ_SSID_NAME);
-+			prm->q.opt.bcn.ssid.SsidLength = i;
-+			_rtw_memcpy(&(prm->q.opt.bcn.ssid.Ssid),
-+				DBG_BCN_REQ_SSID_NAME, i);
-+
-+#else /* original */
-+			prm->q.opt.bcn.ssid.SsidLength = pbody[p+1];
-+			_rtw_memcpy(&(prm->q.opt.bcn.ssid.Ssid),
-+				&pbody[p+2], pbody[p+1]);
-+#endif
-+#endif
-+			RTW_INFO("RM: bcn_req_ssid=%s\n",
-+				prm->q.opt.bcn.ssid.Ssid);
-+
-+			popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
-+			break;
-+
-+		case bcn_req_rep_info:
-+			/* check RM_EN */
-+			rm_en_cap_chk_and_set(prm, RM_BCN_MEAS_REP_COND_CAP_EN);
-+
-+			_rtw_memcpy(&(prm->q.opt.bcn.rep_cond),
-+				&pbody[p+2], sizeof(prm->q.opt.bcn.rep_cond));
-+
-+			RTW_INFO("bcn_req_rep_info=%u:%u\n",
-+				prm->q.opt.bcn.rep_cond.cond,
-+				prm->q.opt.bcn.rep_cond.threshold);
-+
-+			/*popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];*/
-+			break;
-+
-+		case bcn_req_rep_detail:
-+#if DBG_BCN_REQ_DETAIL
-+			prm->q.opt.bcn.rep_detail = 2; /* all IE in beacon */
-+#else
-+			prm->q.opt.bcn.rep_detail = pbody[p+2];
-+#endif
-+			popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
-+
-+#if (RM_MORE_DBG_MSG)
-+			RTW_INFO("RM: report_detail=%d\n",
-+				prm->q.opt.bcn.rep_detail);
-+#endif
-+			break;
-+
-+		case bcn_req_req:
-+			RTW_INFO("RM: bcn_req_req\n");
-+
-+			prm->q.opt.bcn.req_start = rtw_malloc(pbody[p+1]);
-+
-+			if (prm->q.opt.bcn.req_start == NULL) {
-+				RTW_ERR("RM: req_start malloc fail!!\n");
-+				break;
-+			}
-+
-+			for (i = 0; i < pbody[p+1]; i++)
-+				*((prm->q.opt.bcn.req_start)+i) =
-+					pbody[p+2+i];
-+
-+			prm->q.opt.bcn.req_len = pbody[p+1];
-+			popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
-+			break;
-+
-+		case bcn_req_ap_ch_rep:
-+#if (RM_MORE_DBG_MSG)
-+			RTW_INFO("RM: bcn_req_ap_ch_rep\n");
-+#endif
-+			if (ap_ch_rpt_idx > BCN_REQ_OPT_AP_CH_RPT_MAX_NUM) {
-+				RTW_ERR("RM: bcn_req_ap_ch_rep over size\n");
-+				break;
-+			}
-+
-+			popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
-+			/* get channel list
-+			 * EID:len:op-class:ch-list
-+			 */
-+			op = rtw_malloc(sizeof (*op));
-+			op->global_op_class = pbody[p + 2];
-+			i = pbody[p + 1] - 1; /* ch list len; (-1) is op class */
-+
-+#if (RM_MORE_DBG_MSG)
-+			RTW_INFO("%d op class %d has %d ch\n",
-+				ap_ch_rpt_idx,op->global_op_class,i);
-+#endif
-+			op->Len = i;
-+			memcpy(op->Channel, &pbody[p + 3],
-+				MIN(i, MAX_CH_NUM_IN_OP_CLASS));
-+			prm->q.opt.bcn.ap_ch_rpt[ap_ch_rpt_idx++] = op;
-+			prm->q.opt.bcn.ap_ch_rpt_num = ap_ch_rpt_idx;
-+			break;
-+
-+		default:
-+			break;
-+
-+       		}
-+		len = len - (int)pbody[p+1] - 2;
-+		p = p + (int)pbody[p+1] + 2;
-+#if (RM_MORE_DBG_MSG)
-+		RTW_INFO("RM: opt_s_elem_len=%d\n",len);
-+#endif
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+static int rm_parse_meas_req(struct rm_obj *prm, u8 *pbody)
-+{
-+	int p; /* position */
-+	int req_len;
-+
-+
-+	req_len = (int)pbody[1];
-+	p = 5;
-+
-+	prm->q.op_class = pbody[p++];
-+	prm->q.ch_num = pbody[p++];
-+	prm->q.rand_intvl = le16_to_cpu(*(u16*)(&pbody[p]));
-+	p+=2;
-+	prm->q.meas_dur = le16_to_cpu(*(u16*)(&pbody[p]));
-+	p+=2;
-+
-+	if (prm->q.m_type == bcn_req) {
-+		/*
-+		 * 0: passive
-+		 * 1: active
-+		 * 2: bcn_table
-+		 */
-+		prm->q.m_mode = pbody[p++];
-+
-+		/* BSSID */
-+		_rtw_memcpy(&(prm->q.bssid), &pbody[p], 6);
-+		p+=6;
-+
-+		/*
-+		 * default, used when Reporting detail subelement
-+		 * is not included in Beacon Request
-+		 */
-+		prm->q.opt.bcn.rep_detail = 2;
-+	}
-+
-+	if (req_len-(p-2) <= 0) /* without sub-element */
-+		return _SUCCESS;
-+
-+	switch (prm->q.m_type) {
-+	case bcn_req:
-+		rm_parse_bcn_req_s_elem(prm, &pbody[p], req_len-(p-2));
-+		break;
-+	case ch_load_req:
-+		rm_parse_ch_load_s_elem(prm, &pbody[p], req_len-(p-2));
-+		break;
-+	case noise_histo_req:
-+		rm_parse_noise_histo_s_elem(prm, &pbody[p], req_len-(p-2));
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+/* receive measurement request */
-+int rm_recv_radio_mens_req(_adapter *padapter,
-+	union recv_frame *precv_frame, struct sta_info *psta)
-+{
-+	struct rm_obj *prm;
-+	struct rm_priv *prmpriv = &padapter->rmpriv;
-+	u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
-+		sizeof(struct rtw_ieee80211_hdr_3addr));
-+	u8 *pmeas_body = &pdiag_body[5];
-+	u8 rmid, update = 0;
-+
-+
-+#if 0
-+	/* search existing rm_obj */
-+	rmid = psta->cmn.aid << 16
-+		| pdiag_body[2] << 8
-+		| RM_SLAVE;
-+
-+	prm = rm_get_rmobj(padapter, rmid);
-+	if (prm) {
-+		RTW_INFO("RM: Found an exist meas rmid=%u\n", rmid);
-+		update = 1;
-+	} else
-+#endif
-+	prm = rm_alloc_rmobj(padapter);
-+
-+	if (prm == NULL) {
-+		RTW_ERR("RM: unable to alloc rm obj for requeset\n");
-+		return _FALSE;
-+	}
-+
-+	prm->psta = psta;
-+	prm->q.diag_token = pdiag_body[2];
-+	prm->q.rpt = le16_to_cpu(*(u16*)(&pdiag_body[3]));
-+
-+	/* Figure 8-104 Measurement Requested format */
-+	prm->q.e_id = pmeas_body[0];
-+	prm->q.m_token = pmeas_body[2];
-+	prm->q.m_mode = pmeas_body[3];
-+	prm->q.m_type = pmeas_body[4];
-+	prm->rmid = rm_gen_rmid(padapter, prm, RM_SLAVE);
-+
-+	RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid,
-+		MAC_ARG(prm->psta->cmn.mac_addr));
-+
-+#if (RM_MORE_DBG_MSG)
-+	RTW_INFO("RM: element_id = %d\n", prm->q.e_id);
-+	RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]);
-+	RTW_INFO("RM: meas_token = %d\n", prm->q.m_token);
-+	RTW_INFO("RM: meas_mode = %d\n", prm->q.m_mode);
-+	RTW_INFO("RM: meas_type = %d\n", prm->q.m_type);
-+#endif
-+
-+	if (prm->q.e_id != _MEAS_REQ_IE_) /* 38 */
-+		return _FALSE;
-+
-+	switch (prm->q.m_type) {
-+	case bcn_req:
-+		RTW_INFO("RM: recv beacon_request\n");
-+		switch (prm->q.m_mode) {
-+		case bcn_req_passive:
-+			rm_en_cap_chk_and_set(prm, RM_BCN_PASSIVE_MEAS_CAP_EN);
-+			break;
-+		case bcn_req_active:
-+			rm_en_cap_chk_and_set(prm, RM_BCN_ACTIVE_MEAS_CAP_EN);
-+			break;
-+		case bcn_req_bcn_table:
-+			rm_en_cap_chk_and_set(prm, RM_BCN_TABLE_MEAS_CAP_EN);
-+			break;
-+		default:
-+			rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
-+			break;
-+		}
-+		break;
-+	case ch_load_req:
-+		RTW_INFO("RM: recv ch_load_request\n");
-+		rm_en_cap_chk_and_set(prm, RM_CH_LOAD_CAP_EN);
-+		break;
-+	case noise_histo_req:
-+		RTW_INFO("RM: recv noise_histogram_request\n");
-+		rm_en_cap_chk_and_set(prm, RM_NOISE_HISTO_CAP_EN);
-+		break;
-+	default:
-+		RTW_INFO("RM: recv unknown request type 0x%02x\n",
-+			prm->q.m_type);
-+		rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
-+		goto done;
-+       }
-+	rm_parse_meas_req(prm, pmeas_body);
-+done:
-+	if (!update)
-+		rm_enqueue_rmobj(padapter, prm, _FALSE);
-+
-+	return _SUCCESS;
-+}
-+
-+/* receive measurement report */
-+int rm_recv_radio_mens_rep(_adapter *padapter,
-+	union recv_frame *precv_frame, struct sta_info *psta)
-+{
-+	int len, ret = _FALSE;
-+	struct rm_obj *prm;
-+	u32 rmid;
-+	u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
-+		sizeof(struct rtw_ieee80211_hdr_3addr));
-+	u8 *pmeas_body = &pdiag_body[3];
-+
-+
-+	rmid = psta->cmn.aid << 16
-+		| pdiag_body[2] << 8
-+		| RM_MASTER;
-+
-+	prm = rm_get_rmobj(padapter, rmid);
-+	if (prm == NULL) {
-+		/* not belong to us, report to upper */
-+		rtw_cfg80211_rx_rrm_action(psta->padapter, precv_frame);
-+		return _TRUE;
-+	}
-+
-+	prm->p.action_code = pdiag_body[1];
-+	prm->p.diag_token = pdiag_body[2];
-+
-+	/* Figure 8-140 Measuremnt Report format */
-+	prm->p.e_id = pmeas_body[0];
-+	prm->p.m_token = pmeas_body[2];
-+	prm->p.m_mode = pmeas_body[3];
-+	prm->p.m_type = pmeas_body[4];
-+
-+	RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid,
-+		MAC_ARG(prm->psta->cmn.mac_addr));
-+
-+#if (RM_MORE_DBG_MSG)
-+	RTW_INFO("RM: element_id = %d\n", prm->p.e_id);
-+	RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]);
-+	RTW_INFO("RM: meas_token = %d\n", prm->p.m_token);
-+	RTW_INFO("RM: meas_mode = %d\n", prm->p.m_mode);
-+	RTW_INFO("RM: meas_type = %d\n", prm->p.m_type);
-+#endif
-+	if (prm->p.e_id != _MEAS_RSP_IE_) /* 39 */
-+		return _FALSE;
-+
-+	RTW_INFO("RM: recv %s\n", rm_type_rep_name(prm->p.m_type));
-+	rm_post_event(padapter, prm->rmid, RM_EV_recv_rep);
-+
-+	/* report to upper via ioctl */
-+	if ((prm->from_ioctl == true) &&
-+		prm->q.m_type == bcn_req) {
-+		len = pmeas_body[1] + 2; /* 2 : EID(1B)  length(1B) */
-+		indicate_beacon_report(prm->psta->cmn.mac_addr,
-+			1, len, pmeas_body);
-+	}
-+	return ret;
-+}
-+
-+/* receive link measurement request */
-+int rm_recv_link_mens_req(_adapter *padapter,
-+	union recv_frame *precv_frame, struct sta_info *psta)
-+{
-+	struct rm_obj *prm;
-+	struct rm_priv *prmpriv = &padapter->rmpriv;
-+	u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
-+		sizeof(struct rtw_ieee80211_hdr_3addr));
-+	u8 *pmeas_body = &pdiag_body[3];
-+	u8 rmid, update = 0;
-+	int i;
-+
-+
-+	prm = rm_alloc_rmobj(padapter);
-+
-+	if (prm == NULL) {
-+		RTW_ERR("RM: unable to alloc rm obj for requeset\n");
-+		return _FALSE;
-+	}
-+
-+	prm->psta = psta;
-+	prm->q.action_code = pdiag_body[1];
-+	prm->q.diag_token = pdiag_body[2];
-+
-+	prm->q.tx_pwr_used = pmeas_body[0];
-+	prm->q.tx_pwr_max = pmeas_body[1];
-+	prm->q.rx_pwr = precv_frame->u.hdr.attrib.phy_info.rx_power;
-+	prm->q.rx_rate = hw_rate_to_m_rate(precv_frame->u.hdr.attrib.data_rate);
-+	prm->q.rx_bw = precv_frame->u.hdr.attrib.bw;
-+	prm->q.rx_rsni = rm_get_frame_rsni(prm, precv_frame);
-+	prm->rmid = rm_gen_rmid(padapter, prm, RM_SLAVE);
-+
-+	RTW_INFO("RM: rmid=%x, bssid" MAC_FMT " rx_pwr=%ddBm, rate=%s\n",
-+		prm->rmid, MAC_ARG(prm->psta->cmn.mac_addr), prm->q.rx_pwr,
-+		MGN_RATE_STR(prm->q.rx_rate));
-+
-+#if (RM_MORE_DBG_MSG)
-+	RTW_INFO("RM: tx_pwr_used =%d dBm\n", prm->q.tx_pwr_used);
-+	RTW_INFO("RM: tx_pwr_max  =%d dBm\n", prm->q.tx_pwr_max);
-+#endif
-+
-+	if (!update)
-+		rm_enqueue_rmobj(padapter, prm, _FALSE);
-+
-+	return _SUCCESS;
-+}
-+
-+/* receive link measurement report */
-+int rm_recv_link_mens_rep(_adapter *padapter,
-+	union recv_frame *precv_frame, struct sta_info *psta)
-+{
-+	int ret = _FALSE;
-+	struct rm_obj *prm;
-+	u32 rmid;
-+	u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
-+		sizeof(struct rtw_ieee80211_hdr_3addr));
-+	u8 *pmeas_body = pdiag_body + 3;
-+	s8 val;
-+
-+
-+	rmid = psta->cmn.aid << 16
-+		| pdiag_body[2] << 8
-+		| RM_MASTER;
-+
-+	prm = rm_get_rmobj(padapter, rmid);
-+	if (prm == NULL) {
-+		/* not belong to us, report to upper */
-+		rtw_cfg80211_rx_rrm_action(psta->padapter, precv_frame);
-+		return _TRUE;
-+	}
-+
-+	RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid,
-+		MAC_ARG(prm->psta->cmn.mac_addr));
-+
-+	prm->p.action_code = pdiag_body[1];
-+	prm->p.diag_token = pdiag_body[2];
-+
-+#if (RM_MORE_DBG_MSG)
-+	RTW_INFO("RM: action_code = %d\n", prm->p.action_code);
-+	RTW_INFO("RM: diag_token  = %d\n", prm->p.diag_token);
-+	RTW_INFO("RM: xmit_power  = %d dBm\n", pmeas_body[2]);
-+	RTW_INFO("RM: link_margin = %d dBm\n", pmeas_body[3]);
-+	RTW_INFO("RM: xmit_ant    = %d\n", pmeas_body[4]);
-+	RTW_INFO("RM: recv_ant    = %d\n", pmeas_body[5]);
-+	RTW_INFO("RM: RCPI        = %d\n", pmeas_body[6]);
-+	RTW_INFO("RM: RSNI        = %d\n", pmeas_body[7]);
-+#endif
-+	RTW_INFO("RM: recv link meas report ...\n");
-+	ret = rm_post_event(padapter, prm->rmid, RM_EV_recv_rep);
-+
-+	return ret;
-+}
-+
-+
-+int rm_radio_mens_nb_rep(_adapter *padapter,
-+	union recv_frame *precv_frame, struct sta_info *psta)
-+{
-+	u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
-+		sizeof(struct rtw_ieee80211_hdr_3addr));
-+	u8 *pmeas_body = &pdiag_body[3];
-+	u32 len = precv_frame->u.hdr.len;
-+	u32 rmid;
-+	struct rm_obj *prm;
-+
-+
-+	rmid = psta->cmn.aid << 16
-+		| pdiag_body[2] << 8
-+		| RM_MASTER;
-+
-+	prm = rm_get_rmobj(padapter, rmid);
-+
-+	if (prm == NULL) {
-+		/* not belong to us, report to upper */
-+		rtw_cfg80211_rx_rrm_action(psta->padapter, precv_frame);
-+		return _TRUE;
-+	}
-+
-+	prm->p.action_code = pdiag_body[1];
-+	prm->p.diag_token = pdiag_body[2];
-+	prm->p.e_id = pmeas_body[0];
-+
-+	RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid,
-+		MAC_ARG(prm->psta->cmn.mac_addr));
-+
-+#if (RM_MORE_DBG_MSG)
-+	RTW_INFO("RM: element_id = %d\n", prm->p.e_id);
-+	RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]);
-+#endif
-+	rm_post_event(padapter, prm->rmid, RM_EV_recv_rep);
-+
-+#ifdef CONFIG_LAYER2_ROAMING
-+	if (rtw_wnm_btm_candidates_survey(padapter
-+			,(pdiag_body + 3)
-+			,(len - sizeof(struct rtw_ieee80211_hdr_3addr))
-+			,_FALSE) == _FAIL)
-+		return _FALSE;
-+#endif
-+	rtw_cfg80211_rx_rrm_action(padapter, precv_frame);
-+
-+	return _TRUE;
-+}
-+
-+unsigned int rm_on_action(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	u32 ret = _FAIL;
-+	u8 *pframe = NULL;
-+	u8 *pframe_body = NULL;
-+	u8 action_code = 0;
-+	u8 diag_token = 0;
-+	struct rtw_ieee80211_hdr_3addr *whdr;
-+	struct sta_info *psta;
-+
-+
-+	pframe = precv_frame->u.hdr.rx_data;
-+
-+	/* check RA matches or not */
-+	if (!_rtw_memcmp(adapter_mac_addr(padapter),
-+		GetAddr1Ptr(pframe), ETH_ALEN))
-+		goto exit;
-+
-+	whdr = (struct rtw_ieee80211_hdr_3addr *)pframe;
-+	RTW_INFO("RM: %s bssid = " MAC_FMT "\n",
-+		__func__, MAC_ARG(whdr->addr2));
-+
-+	psta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2);
-+
-+        if (!psta) {
-+		RTW_ERR("RM: psta not found\n");
-+                goto exit;
-+        }
-+
-+	pframe_body = (unsigned char *)(pframe +
-+		sizeof(struct rtw_ieee80211_hdr_3addr));
-+
-+	/* Figure 8-438 radio measurement request frame Action field format */
-+	/* Category = pframe_body[0] = 5 (Radio Measurement) */
-+	action_code = pframe_body[1];
-+	diag_token = pframe_body[2];
-+
-+#if (RM_MORE_DBG_MSG)
-+	RTW_INFO("RM: %s radio_action=%x, diag_token=%x\n", __func__,
-+		action_code, diag_token);
-+#endif
-+
-+	switch (action_code) {
-+
-+	case RM_ACT_RADIO_MEAS_REQ:
-+		RTW_INFO("RM: RM_ACT_RADIO_MEAS_REQ\n");
-+		ret = rm_recv_radio_mens_req(padapter, precv_frame, psta);
-+		break;
-+
-+	case RM_ACT_RADIO_MEAS_REP:
-+		RTW_INFO("RM: RM_ACT_RADIO_MEAS_REP\n");
-+		ret = rm_recv_radio_mens_rep(padapter, precv_frame, psta);
-+		break;
-+
-+	case RM_ACT_LINK_MEAS_REQ:
-+		RTW_INFO("RM: RM_ACT_LINK_MEAS_REQ\n");
-+		ret = rm_recv_link_mens_req(padapter, precv_frame, psta);
-+		break;
-+
-+	case RM_ACT_LINK_MEAS_REP:
-+		RTW_INFO("RM: RM_ACT_LINK_MEAS_REP\n");
-+		ret = rm_recv_link_mens_rep(padapter, precv_frame, psta);
-+		break;
-+
-+	case RM_ACT_NB_REP_REQ:
-+		RTW_INFO("RM: RM_ACT_NB_REP_REQ\n");
-+		break;
-+
-+	case RM_ACT_NB_REP_RESP:
-+		RTW_INFO("RM: RM_ACT_NB_REP_RESP\n");
-+		ret = rm_radio_mens_nb_rep(padapter, precv_frame, psta);
-+		break;
-+
-+	default:
-+		/* TODO reply incabable */
-+		RTW_ERR("RM: unknown specturm management action %2x\n",
-+			action_code);
-+		break;
-+	}
-+exit:
-+	return ret;
-+}
-+
-+static u8 *rm_gen_bcn_detail_elem(_adapter *padapter, u8 *pframe,
-+	struct rm_obj *prm, struct wlan_network *pnetwork,
-+	unsigned int *fr_len)
-+{
-+	WLAN_BSSID_EX *pbss = &pnetwork->network;
-+	unsigned int my_len;
-+	int j, k, len;
-+	u8 *plen;
-+	u8 *ptr;
-+	u8 val8, eid;
-+
-+
-+	my_len = 0;
-+	/* Reporting Detail values
-+	 * 0: No fixed length fields or elements
-+	 * 1: All fixed length fields and any requested elements
-+	 *    in the Request info element if present
-+	 * 2: All fixed length fields and elements
-+	 * 3-255: Reserved
-+	 */
-+
-+	/* report_detail = 0 */
-+	if (prm->q.opt.bcn.rep_detail == 0
-+		|| prm->q.opt.bcn.rep_detail > 2) {
-+		return pframe;
-+	}
-+
-+	/* ID */
-+	val8 = 1; /* 1:reported frame body */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	plen = pframe;
-+	val8 = 0;
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	/* report_detail = 2 */
-+	if (prm->q.opt.bcn.rep_detail == 2) {
-+		pframe = rtw_set_fixed_ie(pframe, pbss->IELength - 4,
-+			pbss->IEs, &my_len); /* -4 remove FCS */
-+		goto done;
-+	}
-+
-+	/* report_detail = 1 */
-+	/* all fixed lenght fields */
-+	pframe = rtw_set_fixed_ie(pframe,
-+		_FIXED_IE_LENGTH_, pbss->IEs, &my_len);
-+
-+	for (j = 0; j < prm->q.opt.bcn.opt_id_num; j++) {
-+		switch (prm->q.opt.bcn.opt_id[j]) {
-+		case bcn_req_ssid:
-+			/* SSID */
-+#if (RM_MORE_DBG_MSG)
-+			RTW_INFO("RM: bcn_req_ssid\n");
-+#endif
-+			pframe = rtw_set_ie(pframe, _SSID_IE_,
-+				pbss->Ssid.SsidLength,
-+				pbss->Ssid.Ssid, &my_len);
-+			break;
-+		case bcn_req_req:
-+			if (prm->q.opt.bcn.req_start == NULL)
-+				break;
-+#if (RM_MORE_DBG_MSG)
-+			RTW_INFO("RM: bcn_req_req");
-+#endif
-+			for (k=0; k<prm->q.opt.bcn.req_len; k++) {
-+				eid = prm->q.opt.bcn.req_start[k];
-+
-+				val8 = pbss->IELength - _FIXED_IE_LENGTH_;
-+				ptr = rtw_get_ie(pbss->IEs + _FIXED_IE_LENGTH_,
-+					eid, &len, val8);
-+
-+				if (!ptr)
-+					continue;
-+#if (RM_MORE_DBG_MSG)
-+				switch (eid) {
-+				case EID_SsId:
-+					RTW_INFO("RM: EID_SSID\n");
-+					break;
-+				case EID_QBSSLoad:
-+					RTW_INFO("RM: EID_QBSSLoad\n");
-+					break;
-+				case EID_HTCapability:
-+					RTW_INFO("RM: EID_HTCapability\n");
-+					break;
-+				case _MDIE_:
-+					RTW_INFO("RM: EID_MobilityDomain\n");
-+					break;
-+				case EID_Vendor:
-+					RTW_INFO("RM: EID_Vendor\n");
-+					break;
-+				default:
-+					RTW_INFO("RM: EID %d todo\n",eid);
-+					break;
-+				}
-+#endif
-+				pframe = rtw_set_ie(pframe, eid,
-+					len, ptr+2, &my_len);
-+			} /* for() */
-+			break;
-+		case bcn_req_rep_detail:
-+			RTW_INFO("RM: bcn_req_rep_detail\n");
-+			break;
-+		case bcn_req_ap_ch_rep:
-+			RTW_INFO("RM: bcn_req_ap_ch_rep\n");
-+			break;
-+		default:
-+			RTW_INFO("RM: OPT %d TODO\n",prm->q.opt.bcn.opt_id[j]);
-+			break;
-+		}
-+	}
-+done:
-+	/*
-+	 * update my length
-+	 * content length does NOT include ID and LEN
-+	 */
-+	val8 = my_len - 2;
-+	rtw_set_fixed_ie(plen, 1, &val8, &j);
-+
-+	/* update length to caller */
-+	*fr_len += my_len;
-+
-+	return pframe;
-+}
-+
-+u8 rm_bcn_req_cond_mach(struct rm_obj *prm, struct wlan_network *pnetwork)
-+{
-+	u8 val8;
-+
-+
-+	switch(prm->q.opt.bcn.rep_cond.cond) {
-+	case bcn_rep_cond_immediately:
-+		return _SUCCESS;
-+	case bcn_req_cond_rcpi_greater:
-+		val8 = rm_get_bcn_rcpi(prm, pnetwork);
-+		if (val8 > prm->q.opt.bcn.rep_cond.threshold)
-+			return _SUCCESS;
-+		break;
-+	case bcn_req_cond_rcpi_less:
-+		val8 = rm_get_bcn_rcpi(prm, pnetwork);
-+		if (val8 < prm->q.opt.bcn.rep_cond.threshold)
-+			return _SUCCESS;
-+		break;
-+	case bcn_req_cond_rsni_greater:
-+		val8 = rm_get_bcn_rsni(prm, pnetwork);
-+		if (val8 != 255 && val8 > prm->q.opt.bcn.rep_cond.threshold)
-+			return _SUCCESS;
-+		break;
-+	case bcn_req_cond_rsni_less:
-+		val8 = rm_get_bcn_rsni(prm, pnetwork);
-+		if (val8 != 255 && val8 < prm->q.opt.bcn.rep_cond.threshold)
-+			return _SUCCESS;
-+		break;
-+	default:
-+		RTW_ERR("RM: bcn_req cond %u not support\n",
-+			prm->q.opt.bcn.rep_cond.cond);
-+		break;
-+	}
-+	return _FALSE;
-+}
-+
-+static u8 *rm_gen_bcn_rep_ie (struct rm_obj *prm,
-+	u8 *pframe, struct wlan_network *pnetwork, unsigned int *fr_len)
-+{
-+	int snr, i;
-+	u8 val8, *plen;
-+	u16 val16;
-+	u32 val32;
-+	u64 val64;
-+	unsigned int my_len;
-+	_adapter *padapter = prm->psta->padapter;
-+
-+
-+	my_len = 0;
-+	plen = pframe + 1;
-+	pframe = rtw_set_fixed_ie(pframe, 7, &prm->p.e_id, &my_len);
-+
-+	/* Actual Measurement StartTime */
-+	val64 = cpu_to_le64(prm->meas_start_time);
-+	pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len);
-+
-+	/* Measurement Duration */
-+	val16 = prm->meas_end_time - prm->meas_start_time;
-+	val16 = cpu_to_le16(val16);
-+	pframe = rtw_set_fixed_ie(pframe, 2, (u8*)&val16, &my_len);
-+
-+	/* TODO
-+	* ReportedFrameInformation:
-+	* 0 :beacon or probe rsp
-+	* 1 :pilot frame
-+	*/
-+	val8 = 0; /* report frame info */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	/* RCPI */
-+	val8 = rm_get_bcn_rcpi(prm, pnetwork);
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	/* RSNI */
-+	val8 = rm_get_bcn_rsni(prm, pnetwork);
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	/* BSSID */
-+	pframe = rtw_set_fixed_ie(pframe, 6,
-+		(u8 *)&pnetwork->network.MacAddress, &my_len);
-+
-+	/*
-+	 * AntennaID
-+	 * 0: unknown
-+	 * 255: multiple antenna (Diversity)
-+	 */
-+	val8 = 0;
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	/* ParentTSF */
-+	val32 = pnetwork->network.PhyInfo.free_cnt;
-+	if (prm->free_run_counter_valid)
-+		val32 += prm->meas_start_time;
-+
-+	pframe = rtw_set_fixed_ie(pframe, 4, (u8 *)&val32, &my_len);
-+
-+	/* Generate Beacon detail */
-+	pframe = rm_gen_bcn_detail_elem(padapter, pframe,
-+		prm, pnetwork, &my_len);
-+	/*
-+	* update my length
-+	* content length does NOT include ID and LEN
-+	*/
-+	val8 = my_len - 2;
-+	rtw_set_fixed_ie(plen, 1, &val8, &i);
-+
-+	/* update length to caller */
-+	*fr_len += my_len;
-+
-+	return pframe;
-+}
-+
-+#if 0 /* check MBO logo */
-+static int rm_match_sub_elem(_adapter *padapter,
-+	struct rm_obj *prm, struct wlan_network *pnetwork)
-+{
-+	WLAN_BSSID_EX *pbss = &pnetwork->network;
-+	unsigned int my_len;
-+	int j, k, len;
-+	u8 *plen;
-+	u8 *ptr;
-+	u8 val8, eid;
-+
-+
-+	my_len = 0;
-+	/* Reporting Detail values
-+	 * 0: No fixed length fields or elements
-+	 * 1: All fixed length fields and any requested elements
-+	 *    in the Request info element if present
-+	 * 2: All fixed length fields and elements
-+	 * 3-255: Reserved
-+	 */
-+
-+	/* report_detail != 1  */
-+	if (prm->q.opt.bcn.rep_detail != 1)
-+		return _TRUE;
-+
-+	/* report_detail = 1 */
-+
-+	for (j = 0; j < prm->q.opt.bcn.opt_id_num; j++) {
-+		switch (prm->q.opt.bcn.opt_id[j]) {
-+		case bcn_req_ssid:
-+			/* SSID */
-+#if (RM_MORE_DBG_MSG)
-+			RTW_INFO("RM: bcn_req_ssid\n");
-+#endif
-+			if (pbss->Ssid.SsidLength == 0)
-+				return _FALSE;
-+			break;
-+		case bcn_req_req:
-+			if (prm->q.opt.bcn.req_start == NULL)
-+				break;
-+#if (RM_MORE_DBG_MSG)
-+			RTW_INFO("RM: bcn_req_req");
-+#endif
-+			for (k=0; k<prm->q.opt.bcn.req_len; k++) {
-+				eid = prm->q.opt.bcn.req_start[k];
-+
-+				val8 = pbss->IELength - _FIXED_IE_LENGTH_;
-+				ptr = rtw_get_ie(pbss->IEs + _FIXED_IE_LENGTH_,
-+					eid, &len, val8);
-+
-+#if (RM_MORE_DBG_MSG)
-+				switch (eid) {
-+				case EID_SsId:
-+					RTW_INFO("RM: EID_SSID\n");
-+					break;
-+				case EID_QBSSLoad:
-+					RTW_INFO("RM: EID_QBSSLoad\n");
-+					break;
-+				case EID_HTCapability:
-+					RTW_INFO("RM: EID_HTCapability\n");
-+					break;
-+				case _MDIE_:
-+					RTW_INFO("RM: EID_MobilityDomain\n");
-+					break;
-+				case EID_Vendor:
-+					RTW_INFO("RM: EID_Vendor\n");
-+					break;
-+				default:
-+					RTW_INFO("RM: EID %d todo\n",eid);
-+					break;
-+				}
-+#endif
-+				if (!ptr) {
-+					RTW_INFO("RM: EID %d not found\n",eid);
-+					return _FALSE;
-+				}
-+			} /* for() */
-+			break;
-+		case bcn_req_rep_detail:
-+			RTW_INFO("RM: bcn_req_rep_detail\n");
-+			break;
-+		case bcn_req_ap_ch_rep:
-+			RTW_INFO("RM: bcn_req_ap_ch_rep\n");
-+			break;
-+		default:
-+			RTW_INFO("RM: OPT %d TODO\n",prm->q.opt.bcn.opt_id[j]);
-+			break;
-+		}
-+	}
-+	return _TRUE;
-+}
-+#endif
-+
-+static int retrieve_scan_result(struct rm_obj *prm)
-+{
-+	_irqL irqL;
-+	_list *plist, *phead;
-+	_queue *queue;
-+	_adapter *padapter = prm->psta->padapter;
-+	struct rtw_ieee80211_channel *pch_set;
-+	struct wlan_network *pnetwork = NULL;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	int i;
-+	PWLAN_BSSID_EX pbss;
-+	unsigned int matched_network;
-+	int len, my_len;
-+	u8 buf_idx, *pbuf = NULL, *tmp_buf = NULL;
-+
-+
-+	tmp_buf = rtw_malloc(MAX_XMIT_EXTBUF_SZ);
-+	if (tmp_buf == NULL)
-+		return 0;
-+
-+	my_len = 0;
-+	buf_idx = 0;
-+	matched_network = 0;
-+	queue = &(pmlmepriv->scanned_queue);
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+	/* get requested measurement channel set */
-+	pch_set = prm->q.ch_set;
-+
-+	/* search scan queue to find requested SSID */
-+	while (1) {
-+
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+		pbss = &pnetwork->network;
-+
-+#if 0
-+		RTW_INFO("RM: ooo ch %u ssid %s bssid "MAC_FMT"\n",
-+			pbss->Configuration.DSConfig, pbss->Ssid.Ssid,
-+			MAC_ARG(pbss->MacAddress));
-+		/*
-+		* report network if requested channel set contains
-+		* the channel matchs selected network
-+		*/
-+		if (rtw_chset_search_ch(adapter_to_chset(padapter),
-+			pbss->Configuration.DSConfig) < 0) /* not match */
-+			goto next;
-+
-+		if (rtw_mlme_band_check(padapter, pbss->Configuration.DSConfig)
-+			== _FALSE)
-+			goto next;
-+#endif
-+		if (rtw_validate_ssid(&(pbss->Ssid)) == _FALSE)
-+			goto next;
-+
-+		/* match bssid */
-+		if (is_wildcard_bssid(prm->q.bssid) == FALSE)
-+			if (_rtw_memcmp(prm->q.bssid,
-+				pbss->MacAddress, 6) == _FALSE)
-+				//continue;
-+				goto next;
-+		/*
-+		 * default wildcard SSID. wildcard SSID:
-+		 * A SSID value (null) used to represent all SSIDs
-+		 */
-+
-+		/* match ssid */
-+		if ((prm->q.opt.bcn.ssid.SsidLength > 0) &&
-+			_rtw_memcmp(prm->q.opt.bcn.ssid.Ssid,
-+			pbss->Ssid.Ssid,
-+			prm->q.opt.bcn.ssid.SsidLength) == _FALSE)
-+			goto next;
-+
-+		/* go through measurement requested channels */
-+		for (i = 0; i < prm->q.ch_set_ch_amount; i++) {
-+			if ((pch_set[i].hw_value) ==
-+				(pbss->Configuration.DSConfig)) /* match ch */
-+				break;
-+		}
-+		if (i >= prm->q.ch_set_ch_amount) /* channel mismatch */
-+			goto next;
-+
-+		/* match condition */
-+		if (rm_bcn_req_cond_mach(prm, pnetwork) == _FALSE) {
-+			RTW_INFO("RM: condition mismatch ch %u ssid %s bssid "MAC_FMT"\n",
-+				pbss->Configuration.DSConfig, pbss->Ssid.Ssid,
-+				MAC_ARG(pbss->MacAddress));
-+			RTW_INFO("RM: condition %u:%u\n",
-+				prm->q.opt.bcn.rep_cond.cond,
-+				prm->q.opt.bcn.rep_cond.threshold);
-+			goto next;
-+			//continue;
-+		}
-+#if 0 /* check MBO logo */
-+		/* match subelement */
-+		if (rm_match_sub_elem(padapter, prm, pnetwork) == _FALSE)
-+			goto next;
-+#endif
-+		/* Found a matched SSID */
-+		matched_network++;
-+
-+		RTW_INFO("RM: ch %u Found %s bssid "MAC_FMT"\n",
-+			pbss->Configuration.DSConfig, pbss->Ssid.Ssid,
-+			MAC_ARG(pbss->MacAddress));
-+
-+		len = 0;
-+		_rtw_memset(tmp_buf, 0, MAX_XMIT_EXTBUF_SZ);
-+		rm_gen_bcn_rep_ie(prm, tmp_buf, pnetwork, &len);
-+new_packet:
-+		if (my_len == 0) {
-+			pbuf = rtw_malloc(MAX_XMIT_EXTBUF_SZ);
-+			if (pbuf == NULL)
-+				goto fail;
-+			prm->buf[buf_idx].pbuf = pbuf;
-+		}
-+
-+		if ((MAX_XMIT_EXTBUF_SZ - (my_len+len+24+4)) > 0) {
-+			pbuf = rtw_set_fixed_ie(pbuf,
-+				len, tmp_buf, &my_len);
-+			prm->buf[buf_idx].len = my_len;
-+		} else {
-+			if (my_len == 0) /* not enough space */
-+				goto fail;
-+
-+			my_len = 0;
-+			buf_idx++;
-+			goto new_packet;
-+		}
-+next:
-+		plist = get_next(plist);
-+	} /* while() */
-+fail:
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	if (tmp_buf)
-+		rtw_mfree(tmp_buf, MAX_XMIT_EXTBUF_SZ);
-+
-+	RTW_INFO("RM: Found %d matched %s\n", matched_network,
-+		prm->q.opt.bcn.ssid.Ssid);
-+
-+	if (prm->buf[buf_idx].pbuf)
-+		return buf_idx+1;
-+
-+	return 0;
-+}
-+
-+int issue_beacon_rep(struct rm_obj *prm)
-+{
-+	int i, my_len;
-+	u8 *pframe;
-+	_adapter *padapter = prm->psta->padapter;
-+	struct pkt_attrib *pattr;
-+	struct xmit_frame *pmgntframe;
-+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
-+	int pkt_num;
-+
-+
-+	pkt_num = retrieve_scan_result(prm);
-+
-+	if (pkt_num == 0) {
-+		issue_null_reply(prm);
-+		return _SUCCESS;
-+	}
-+
-+	for (i=0;i<pkt_num;i++) {
-+
-+		pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+		if (pmgntframe == NULL) {
-+			RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
-+			goto fail;
-+		}
-+		pattr = &pmgntframe->attrib;
-+		pframe = build_wlan_hdr(padapter,
-+			pmgntframe, prm->psta, WIFI_ACTION);
-+		pframe = rtw_set_fixed_ie(pframe,
-+			3, &prm->p.category, &pattr->pktlen);
-+
-+		my_len = 0;
-+		pframe = rtw_set_fixed_ie(pframe,
-+			prm->buf[i].len, prm->buf[i].pbuf, &my_len);
-+
-+		pattr->pktlen += my_len;
-+		pattr->last_txcmdsz = pattr->pktlen;
-+		dump_mgntframe(padapter, pmgntframe);
-+	}
-+fail:
-+	for (i=0;i<pkt_num;i++) {
-+		if (prm->buf[i].pbuf) {
-+			rtw_mfree(prm->buf[i].pbuf, MAX_XMIT_EXTBUF_SZ);
-+			prm->buf[i].pbuf = NULL;
-+			prm->buf[i].len = 0;
-+		}
-+	}
-+	return _SUCCESS;
-+}
-+
-+/* neighbor request */
-+int issue_nb_req(struct rm_obj *prm)
-+{
-+	_adapter *padapter = prm->psta->padapter;
-+	struct sta_info *psta = prm->psta;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	struct xmit_frame *pmgntframe = NULL;
-+	struct pkt_attrib *pattr = NULL;
-+	u8 val8;
-+	u8 *pframe = NULL;
-+
-+
-+	RTW_INFO("RM: %s\n", __func__);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL) {
-+		RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
-+		return _FALSE;
-+	}
-+	pattr = &pmgntframe->attrib;
-+	pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION);
-+	pframe = rtw_set_fixed_ie(pframe,
-+		3, &prm->q.category, &pattr->pktlen);
-+
-+	if (prm->q.pssid) {
-+
-+		u8 sub_ie[64] = {0};
-+		u8 *pie = &sub_ie[2];
-+
-+		RTW_INFO("RM: Send NB Req to "MAC_FMT" for(SSID) %s searching\n",
-+			MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
-+			pmlmepriv->cur_network.network.Ssid.Ssid);
-+
-+		val8 = strlen(prm->q.pssid);
-+		sub_ie[0] = 0; /*SSID*/
-+		sub_ie[1] = val8;
-+
-+		_rtw_memcpy(pie, prm->q.pssid, val8);
-+
-+		pframe = rtw_set_fixed_ie(pframe, val8 + 2,
-+			sub_ie, &pattr->pktlen);
-+	} else {
-+
-+		if (!pmlmepriv->cur_network.network.Ssid.SsidLength)
-+			RTW_INFO("RM: Send NB Req to "MAC_FMT"\n",
-+				MAC_ARG(pmlmepriv->cur_network.network.MacAddress));
-+		else {
-+			u8 sub_ie[64] = {0};
-+			u8 *pie = &sub_ie[2];
-+
-+			RTW_INFO("RM: Send NB Req to "MAC_FMT" for(SSID) %s searching\n",
-+				MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
-+				pmlmepriv->cur_network.network.Ssid.Ssid);
-+
-+			sub_ie[0] = 0; /*SSID*/
-+			sub_ie[1] = pmlmepriv->cur_network.network.Ssid.SsidLength;
-+
-+			_rtw_memcpy(pie, pmlmepriv->cur_network.network.Ssid.Ssid,
-+				pmlmepriv->cur_network.network.Ssid.SsidLength);
-+
-+			pframe = rtw_set_fixed_ie(pframe,
-+				pmlmepriv->cur_network.network.Ssid.SsidLength + 2,
-+				sub_ie, &pattr->pktlen);
-+		}
-+	}
-+
-+	pattr->last_txcmdsz = pattr->pktlen;
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return _SUCCESS;
-+}
-+
-+/* issue link measurement request */
-+int issue_link_meas_req(struct rm_obj *prm)
-+{
-+	_adapter *padapter = prm->psta->padapter;
-+	struct sta_info *psta = prm->psta;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	struct xmit_frame *pmgntframe = NULL;
-+	struct pkt_attrib *pattr = NULL;
-+	u8 *pframe = NULL;
-+	s8 pwr_used, path_a_pwr;
-+
-+
-+	RTW_INFO("RM: %s\n", __func__);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL) {
-+		RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
-+		return _FALSE;
-+	}
-+	pattr = &pmgntframe->attrib;
-+	pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION);
-+
-+	/* Category, Action code, Dialog token */
-+	pframe = rtw_set_fixed_ie(pframe,
-+		3, &prm->q.category, &pattr->pktlen);
-+
-+	/* xmit power used */
-+	/* we don't know actual TX power due to RA may change TX rate;
-+	 * But if we fix TX rate then we can get specific tx power
-+	 */
-+	pattr->rate = MGN_6M;
-+	rm_get_tx_power(padapter, RF_PATH_A, MGN_6M, &pwr_used);
-+	pframe = rtw_set_fixed_ie(pframe,
-+		1, &pwr_used, &pattr->pktlen);
-+
-+	/* Max xmit power */
-+	rm_get_path_a_max_tx_power(padapter, &path_a_pwr);
-+	pframe = rtw_set_fixed_ie(pframe,
-+		1, &path_a_pwr, &pattr->pktlen);
-+
-+	pattr->last_txcmdsz = pattr->pktlen;
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return _SUCCESS;
-+}
-+
-+/* issue link measurement report */
-+int issue_link_meas_rep(struct rm_obj *prm)
-+{
-+	u8 val8;
-+	u8 *pframe;
-+	unsigned int my_len;
-+	_adapter *padapter = prm->psta->padapter;
-+	struct xmit_frame *pmgntframe;
-+	struct pkt_attrib *pattr;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct sta_info *psta = prm->psta;
-+	int i;
-+	u8 tpc[4];
-+	s8 pwr_used;
-+
-+
-+	RTW_INFO("RM: %s\n", __func__);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL) {
-+		RTW_ERR("RM: ERR %s alloc xmit_frame fail\n",__func__);
-+		return _FALSE;
-+	}
-+	pattr = &pmgntframe->attrib;
-+	pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION);
-+	/* Category, action code, Dialog token */
-+	pframe = rtw_set_fixed_ie(pframe, 3,
-+		&prm->p.category, &pattr->pktlen);
-+
-+	my_len = 0;
-+
-+	/* TPC report */
-+	rm_get_tx_power(padapter, RF_PATH_A, MGN_6M, &pwr_used);
-+	tpc[0] = EID_TPC;
-+	tpc[1] = 2; /* length */
-+
-+	/* TX power */
-+	tpc[2] = pwr_used;
-+
-+	/* link margin */
-+	rm_get_rx_sensitivity(padapter, prm->q.rx_bw, prm->q.rx_rate, &pwr_used);
-+	tpc[3] = prm->q.rx_pwr - pwr_used; /* RX sensitivity */
-+	pattr->rate = MGN_6M; /* use fix rate to get fixed RX sensitivity */
-+
-+#if (RM_MORE_DBG_MSG)
-+	RTW_INFO("RM: rx_pwr=%ddBm - rx_sensitivity=%ddBm = link_margin=%ddB\n",
-+		prm->q.rx_pwr, pwr_used, tpc[3]);
-+#endif
-+	pframe = rtw_set_fixed_ie(pframe, 4, tpc, &my_len);
-+
-+	/* RECV antenna ID */
-+	val8 = 0; /* unknown antenna */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	/* XMIT antenna ID */
-+	/* Fix rate 6M(1T) always use main antenna to TX */
-+	val8 = 1; /* main antenna */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	/* RCPI */
-+	val8 = translate_dbm_to_rcpi(prm->q.rx_pwr);
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	/* RSNI */
-+	val8 = prm->q.rx_rsni;
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	/* length */
-+	//val8 = (u8)my_len-2;
-+	//rtw_set_fixed_ie(plen, 1, &val8, &i); /* use variable i to ignore it */
-+
-+	pattr->pktlen += my_len;
-+	pattr->last_txcmdsz = pattr->pktlen;
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return _SUCCESS;
-+}
-+
-+static u8 *rm_gen_bcn_req_s_elem(_adapter *padapter,
-+	struct rm_obj *prm, u8 *pframe, unsigned int *fr_len)
-+{
-+	u8 val8, l;
-+	int i;
-+	unsigned int my_len = 0;
-+	struct _RT_OPERATING_CLASS *op;
-+
-+	/* meas mode */
-+	val8 = bcn_req_active; /* measurement mode T8-64 */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	/* bssid */
-+	pframe = rtw_set_fixed_ie(pframe, 6, prm->q.bssid, &my_len);
-+
-+	/*
-+	 * opt ssid (0)
-+	 */
-+	l = MIN(32, (int)prm->q.opt.bcn.ssid.SsidLength);
-+
-+	l = (int)prm->q.opt.bcn.ssid.SsidLength;
-+
-+	if (l > 32)
-+		RTW_ERR("RM: %s SSID len over size %d! skip it!\n",__func__, l);
-+
-+	if (l > 0 && l <= 32) {
-+		/* Type */
-+		val8 = bcn_req_ssid;
-+		pframe = rtw_set_fixed_ie(pframe, 1,
-+			&val8, &my_len);
-+		/* Len */
-+		pframe = rtw_set_fixed_ie(pframe, 1,
-+			&l, &my_len);
-+		/* Value */
-+		pframe = rtw_set_fixed_ie(pframe, l,
-+			prm->q.opt.bcn.ssid.Ssid, &my_len);
-+	}
-+
-+	/*
-+	 * opt reporting detail (2)
-+	 */
-+	/* Type */
-+	val8 = bcn_req_rep_detail;
-+	pframe = rtw_set_fixed_ie(pframe, 1,
-+		&val8, &my_len);
-+	/* Len */
-+	l = 1;
-+	pframe = rtw_set_fixed_ie(pframe, 1,
-+		&l, &my_len);
-+	/* Value */
-+	pframe = rtw_set_fixed_ie(pframe, l,
-+		&prm->q.opt.bcn.rep_detail, &my_len);
-+
-+	/*
-+	 * opt request (10)
-+	 */
-+
-+	if (prm->q.opt.bcn.req_id_num > 0) {
-+		/* Type */
-+		val8 = bcn_req_req;
-+		pframe = rtw_set_fixed_ie(pframe, 1,
-+			&val8, &my_len);
-+		/* Len */
-+		l = prm->q.opt.bcn.req_id_num;
-+		pframe = rtw_set_fixed_ie(pframe, 1,
-+			&l, &my_len);
-+		/* Value */
-+		pframe = rtw_set_fixed_ie(pframe, l,
-+			prm->q.opt.bcn.req_id, &my_len);
-+	}
-+
-+	/*
-+	 * opt ap channel report (51)
-+	 */
-+	for (i = 0; i < prm->q.opt.bcn.ap_ch_rpt_num; i++) {
-+		op = prm->q.opt.bcn.ap_ch_rpt[i];
-+		if (op == NULL)
-+			break;
-+		/* Type */
-+		val8 = bcn_req_ap_ch_rep;
-+		pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+		l = (u8)op->Len + 1;
-+		/* length */
-+		pframe = rtw_set_fixed_ie(pframe, 1, &l, &my_len);
-+
-+		/* op class */
-+		val8 = op->global_op_class;
-+		pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+		/* channel */
-+		pframe = rtw_set_fixed_ie(pframe, op->Len, op->Channel, &my_len);
-+	}
-+
-+	/* update length to caller */
-+	*fr_len += my_len;
-+
-+	/* optional subelements */
-+	return pframe;
-+}
-+
-+static u8 *rm_gen_ch_load_req_s_elem(_adapter *padapter,
-+	u8 *pframe, unsigned int *fr_len)
-+{
-+	u8 val8;
-+	unsigned int my_len = 0;
-+
-+
-+	val8 = 1; /* 1: channel load T8-60 */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	val8 = 2; /* channel load length = 2 (extensible)  */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	val8 = 0; /* channel load condition : 0 (issue when meas done) T8-61 */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	val8 = 0; /* channel load reference value : 0 */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	/* update length to caller */
-+	*fr_len += my_len;
-+
-+	return pframe;
-+}
-+
-+static u8 *rm_gen_noise_histo_req_s_elem(_adapter *padapter,
-+	u8 *pframe, unsigned int *fr_len)
-+{
-+	u8 val8;
-+	unsigned int my_len = 0;
-+
-+
-+	val8 = 1; /* 1: noise histogram T8-62 */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	val8 = 2; /* noise histogram length = 2 (extensible)  */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	val8 = 0; /* noise histogram condition : 0 (issue when meas done) T8-63 */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	val8 = 0; /* noise histogram reference value : 0 */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+
-+	/* update length to caller */
-+	*fr_len += my_len;
-+
-+	return pframe;
-+}
-+
-+int issue_radio_meas_req(struct rm_obj *prm)
-+{
-+	u8 val8;
-+	u8 *pframe;
-+	u8 *plen;
-+	u16 val16;
-+	int my_len, i;
-+	struct xmit_frame *pmgntframe;
-+	struct pkt_attrib *pattr;
-+	_adapter *padapter = prm->psta->padapter;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+
-+
-+	RTW_INFO("RM: %s - %s\n", __func__, rm_type_req_name(prm->q.m_type));
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL) {
-+		RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
-+		return _FALSE;
-+	}
-+	pattr = &pmgntframe->attrib;
-+	pframe = build_wlan_hdr(padapter, pmgntframe, prm->psta, WIFI_ACTION);
-+
-+	/* Category, Action code, Dialog token */
-+	pframe = rtw_set_fixed_ie(pframe, 3, &prm->q.category, &pattr->pktlen);
-+
-+	/* repeat */
-+	val16 = cpu_to_le16(prm->q.rpt);
-+	pframe = rtw_set_fixed_ie(pframe, 2,
-+		(unsigned char *)&(val16), &pattr->pktlen);
-+
-+	my_len = 0;
-+	plen = pframe + 1;
-+	/* Element ID, Length, Meas token, Meas Mode, Meas type, op class, ch */
-+	pframe = rtw_set_fixed_ie(pframe, 7, &prm->q.e_id, &my_len);
-+
-+	/* random interval */
-+	val16 = cpu_to_le16(prm->q.rand_intvl); /* TU */
-+	pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);
-+
-+	/* measurement duration */
-+	val16 = cpu_to_le16(prm->q.meas_dur);
-+	pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);
-+
-+	/* optional subelement */
-+	switch (prm->q.m_type) {
-+	case bcn_req:
-+		pframe = rm_gen_bcn_req_s_elem(padapter, prm,  pframe, &my_len);
-+		break;
-+	case ch_load_req:
-+		pframe = rm_gen_ch_load_req_s_elem(padapter, pframe, &my_len);
-+		break;
-+	case noise_histo_req:
-+		pframe = rm_gen_noise_histo_req_s_elem(padapter,
-+			pframe, &my_len);
-+		break;
-+	case basic_req:
-+	default:
-+		break;
-+	}
-+
-+	/* length */
-+	val8 = (u8)my_len - 2;
-+	rtw_set_fixed_ie(plen, 1, &val8, &i);
-+
-+	pattr->pktlen += my_len;
-+
-+	pattr->last_txcmdsz = pattr->pktlen;
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return _SUCCESS;
-+}
-+
-+int rm_radio_meas_report_cond(struct rm_obj *prm)
-+{
-+	u8 val8;
-+	int i;
-+
-+
-+	switch (prm->q.m_type) {
-+	case ch_load_req:
-+
-+		val8 = prm->p.ch_load;
-+		switch (prm->q.opt.clm.rep_cond.cond) {
-+		case ch_load_cond_immediately:
-+			return _SUCCESS;
-+		case ch_load_cond_anpi_equal_greater:
-+			if (val8 >= prm->q.opt.clm.rep_cond.threshold)
-+				return _SUCCESS;
-+			break;
-+		case ch_load_cond_anpi_equal_less:
-+			if (val8 <= prm->q.opt.clm.rep_cond.threshold)
-+				return _SUCCESS;
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+	case noise_histo_req:
-+		val8 = prm->p.anpi;
-+		switch (prm->q.opt.nhm.rep_cond.cond) {
-+		case noise_histo_cond_immediately:
-+			return _SUCCESS;
-+		case noise_histo_cond_anpi_equal_greater:
-+			if (val8 >= prm->q.opt.nhm.rep_cond.threshold)
-+				return _SUCCESS;
-+			break;
-+		case noise_histo_cond_anpi_equal_less:
-+			if (val8 <= prm->q.opt.nhm.rep_cond.threshold)
-+				return _SUCCESS;
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+	return _FAIL;
-+}
-+
-+int retrieve_radio_meas_result(struct rm_obj *prm)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(prm->psta->padapter);
-+	int i, ch = -1;
-+	u8 val8;
-+
-+
-+	ch = rtw_chset_search_ch(adapter_to_chset(prm->psta->padapter),
-+		prm->q.ch_num);
-+
-+	if ((ch == -1) || (ch >= MAX_CHANNEL_NUM)) {
-+		RTW_ERR("RM: get ch(CH:%d) fail\n", prm->q.ch_num);
-+		ch = 0;
-+	}
-+
-+	switch (prm->q.m_type) {
-+	case ch_load_req:
-+#ifdef CONFIG_RTW_ACS
-+		val8 = hal_data->acs.clm_ratio[ch];
-+#else
-+		val8 = 0;
-+#endif
-+		prm->p.ch_load = val8;
-+		break;
-+	case noise_histo_req:
-+#ifdef CONFIG_RTW_ACS
-+		/* ANPI */
-+		prm->p.anpi = hal_data->acs.nhm_ratio[ch];
-+
-+		/* IPI 0~10 */
-+		for (i=0;i<11;i++)
-+			prm->p.ipi[i] = hal_data->acs.nhm[ch][i];
-+		
-+#else
-+		val8 = 0;
-+		prm->p.anpi = val8;
-+		for (i=0;i<11;i++)
-+			prm->p.ipi[i] = val8;
-+#endif
-+		break;
-+	default:
-+		break;
-+	}
-+	return _SUCCESS;
-+}
-+
-+int issue_radio_meas_rep(struct rm_obj *prm)
-+{
-+	u8 val8;
-+	u8 *pframe;
-+	u8 *plen;
-+	u16 val16;
-+	u64 val64;
-+	unsigned int my_len;
-+	_adapter *padapter = prm->psta->padapter;
-+	struct xmit_frame *pmgntframe;
-+	struct pkt_attrib *pattr;
-+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
-+	struct sta_info *psta = prm->psta;
-+	int i;
-+
-+
-+	RTW_INFO("RM: %s\n", __func__);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL) {
-+		RTW_ERR("RM: ERR %s alloc xmit_frame fail\n",__func__);
-+		return _FALSE;
-+	}
-+	pattr = &pmgntframe->attrib;
-+	pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION);
-+	pframe = rtw_set_fixed_ie(pframe, 3,
-+		&prm->p.category, &pattr->pktlen);
-+
-+	my_len = 0;
-+	plen = pframe + 1;
-+	pframe = rtw_set_fixed_ie(pframe, 7, &prm->p.e_id, &my_len);
-+
-+	/* Actual Meas start time - 8 bytes */
-+	val64 = cpu_to_le64(prm->meas_start_time);
-+	pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len);
-+
-+	/* measurement duration */
-+	val16 = prm->meas_end_time - prm->meas_start_time;
-+	val16 = cpu_to_le16(val16);
-+	pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);
-+
-+	/* optional subelement */
-+	switch (prm->q.m_type) {
-+	case ch_load_req:
-+		val8 = prm->p.ch_load;
-+		pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+		break;
-+	case noise_histo_req:
-+		/*
-+		 * AntennaID
-+		 * 0: unknown
-+		 * 255: multiple antenna (Diversity)
-+		 */
-+		val8 = 0;
-+		pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+		/* ANPI */
-+		val8 = prm->p.anpi;
-+		pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+		/* IPI 0~10 */
-+		for (i=0;i<11;i++) {
-+			val8 = prm->p.ipi[i];
-+			pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+	/* length */
-+	val8 = (u8)my_len-2;
-+	rtw_set_fixed_ie(plen, 1, &val8, &i); /* use variable i to ignore it */
-+
-+	pattr->pktlen += my_len;
-+	pattr->last_txcmdsz = pattr->pktlen;
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	return _SUCCESS;
-+}
-+
-+void rtw_ap_parse_sta_rm_en_cap(_adapter *padapter,
-+	struct sta_info *psta, struct rtw_ieee802_11_elems *elem)
-+{
-+	if (elem->rm_en_cap) {
-+		RTW_INFO("assoc.rm_en_cap="RM_CAP_FMT"\n",
-+			RM_CAP_ARG(elem->rm_en_cap));
-+		_rtw_memcpy(psta->rm_en_cap,
-+			(elem->rm_en_cap), elem->rm_en_cap_len);
-+	}
-+}
-+
-+void RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+	int i;
-+
-+	_rtw_memcpy(&padapter->rmpriv.rm_en_cap_assoc, pIE->data, pIE->Length);
-+	RTW_INFO("assoc.rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(pIE->data));
-+}
-+
-+/* Debug command */
-+
-+#if (RM_SUPPORT_IWPRIV_DBG)
-+static int hex2num(char c)
-+{
-+	if (c >= '0' && c <= '9')
-+		return c - '0';
-+	if (c >= 'a' && c <= 'f')
-+		return c - 'a' + 10;
-+	if (c >= 'A' && c <= 'F')
-+		return c - 'A' + 10;
-+	return -1;
-+}
-+
-+int hex2byte(const char *hex)
-+{
-+	int a, b;
-+	a = hex2num(*hex++);
-+	if (a < 0)
-+		return -1;
-+	b = hex2num(*hex++);
-+	if (b < 0)
-+		return -1;
-+	return (a << 4) | b;
-+}
-+
-+static char * hwaddr_parse(char *txt, u8 *addr)
-+{
-+	size_t i;
-+
-+	for (i = 0; i < ETH_ALEN; i++) {
-+		int a;
-+
-+		a = hex2byte(txt);
-+		if (a < 0)
-+			return NULL;
-+		txt += 2;
-+		addr[i] = a;
-+		if (i < ETH_ALEN - 1 && *txt++ != ':')
-+			return NULL;
-+	}
-+	return txt;
-+}
-+
-+void rm_dbg_list_sta(_adapter *padapter, char *s)
-+{
-+	int i;
-+	_irqL irqL;
-+	struct sta_info *psta;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	_list *plist, *phead;
-+
-+
-+	sprintf(pstr(s), "\n");
-+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+	for (i = 0; i < NUM_STA; i++) {
-+		phead = &(pstapriv->sta_hash[i]);
-+		plist = get_next(phead);
-+
-+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+			psta = LIST_CONTAINOR(plist,
-+				struct sta_info, hash_list);
-+
-+			plist = get_next(plist);
-+
-+			sprintf(pstr(s), "=========================================\n");
-+			sprintf(pstr(s), "mac=" MAC_FMT "\n",
-+				MAC_ARG(psta->cmn.mac_addr));
-+			sprintf(pstr(s), "state=0x%x, aid=%d, macid=%d\n",
-+				psta->state, psta->cmn.aid, psta->cmn.mac_id);
-+			sprintf(pstr(s), "rm_cap="RM_CAP_FMT"\n",
-+				RM_CAP_ARG(psta->rm_en_cap));
-+		}
-+
-+	}
-+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+	sprintf(pstr(s), "=========================================\n");
-+}
-+
-+void rm_dbg_help(_adapter *padapter, char *s)
-+{
-+	int i;
-+
-+
-+	sprintf(pstr(s), "\n");
-+	sprintf(pstr(s), "rrm list_sta\n");
-+	sprintf(pstr(s), "rrm list_meas\n");
-+
-+	sprintf(pstr(s), "rrm add_meas <aid=1|mac=>,m=<bcn|clm|nhm|nb|link>,rpt=\n");
-+	sprintf(pstr(s), "rrm run_meas <aid=1|evid=>\n");
-+	sprintf(pstr(s), "rrm del_meas\n");
-+
-+	sprintf(pstr(s), "rrm run_meas rmid=xxxx,ev=xx\n");
-+	sprintf(pstr(s), "rrm activate\n");
-+
-+	for (i=0;i<RM_EV_max;i++)
-+		sprintf(pstr(s), "\t%2d %s\n",i, rm_event_name(i) );
-+	sprintf(pstr(s), "\n");
-+}
-+
-+struct sta_info *rm_get_sta(_adapter *padapter, u16 aid, u8* pbssid)
-+{
-+	int i;
-+	_irqL irqL;
-+	struct sta_info *psta = NULL;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	_list *plist, *phead;
-+
-+
-+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+	for (i = 0; i < NUM_STA; i++) {
-+		phead = &(pstapriv->sta_hash[i]);
-+		plist = get_next(phead);
-+
-+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+			psta = LIST_CONTAINOR(plist,
-+				struct sta_info, hash_list);
-+
-+			plist = get_next(plist);
-+
-+			if (psta->cmn.aid == aid)
-+				goto done;
-+
-+			if (pbssid && _rtw_memcmp(psta->cmn.mac_addr,
-+				pbssid, 6))
-+				goto done;
-+		}
-+
-+	}
-+	psta = NULL;
-+done:
-+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+	return psta;
-+}
-+
-+static int rm_dbg_modify_meas(_adapter *padapter, char *s)
-+{
-+	struct rm_priv *prmpriv = &padapter->rmpriv;
-+	struct rm_obj *prm;
-+	struct sta_info *psta;
-+	char *pmac, *ptr, *paid, *prpt, *pnbp, *pclm, *pnhm, *pbcn, *plnk;
-+	unsigned val;
-+	u8 bssid[ETH_ALEN];
-+
-+
-+	/* example :
-+	* rrm add_meas <aid=1|mac=>,m=<nb|clm|nhm|bcn|link>,<rept=>
-+	* rrm run_meas <aid=1|evid=>
-+	*/
-+	paid = strstr(s, "aid=");
-+	pmac = strstr(s, "mac=");
-+	pbcn = strstr(s, "m=bcn");
-+	pclm = strstr(s, "m=clm");
-+	pnhm = strstr(s, "m=nhm");
-+	pnbp = strstr(s, "m=nb");
-+	plnk = strstr(s, "m=link");
-+	prpt = strstr(s, "rpt=");
-+
-+	/* set all ',' to NULL (end of line) */
-+	ptr = s;
-+	while (ptr) {
-+		ptr = strchr(ptr, ',');
-+		if (ptr) {
-+			*(ptr) = 0x0;
-+			ptr++;
-+		}
-+	}
-+	prm = (struct rm_obj *)prmpriv->prm_sel;
-+	prm->q.m_token = rm_gen_meas_token(padapter);
-+	psta = prm->psta;
-+
-+	if (paid) { /* find sta_info according to aid */
-+		paid += 4; /* skip aid= */
-+		sscanf(paid, "%u", &val); /* aid=x */
-+		psta = rm_get_sta(padapter, val, NULL);
-+
-+	} else if (pmac) { /* find sta_info according to bssid */
-+		pmac += 4; /* skip mac= */
-+		if (hwaddr_parse(pmac, bssid) == NULL) {
-+			sprintf(pstr(s), "Err: \nincorrect mac format\n");
-+			return _FAIL;
-+		}
-+		psta = rm_get_sta(padapter, 0xff, bssid);
-+	}
-+
-+	if (psta) {
-+		prm->psta = psta;
-+		prm->q.diag_token = rm_gen_dialog_token(padapter);
-+		prm->rmid = rm_gen_rmid(padapter, prm, RM_MASTER);
-+	} else
-+		return _FAIL;
-+
-+	prm->q.action_code = RM_ACT_RADIO_MEAS_REQ;
-+	if (pbcn) {
-+		prm->q.m_type = bcn_req;
-+		prm->q.rand_intvl = le16_to_cpu(100);
-+		prm->q.meas_dur = le16_to_cpu(100);
-+	} else if (pnhm) {
-+		prm->q.m_type = noise_histo_req;
-+	} else if (pclm) {
-+		prm->q.m_type = ch_load_req;
-+	} else if (pnbp) {
-+		prm->q.action_code = RM_ACT_NB_REP_REQ;
-+	} else if (plnk) {
-+		prm->q.action_code = RM_ACT_LINK_MEAS_REQ;
-+	} else
-+		return _FAIL;
-+
-+	if (prpt) {
-+		prpt += 4; /* skip rpt= */
-+		sscanf(prpt, "%u", &val);
-+		prm->q.rpt = (u8)val;
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+static void rm_dbg_activate_meas(_adapter *padapter, char *s)
-+{
-+	struct rm_priv *prmpriv = &(padapter->rmpriv);
-+	struct rm_obj *prm;
-+
-+
-+	if (prmpriv->prm_sel == NULL) {
-+		sprintf(pstr(s), "\nErr: No inActivate measurement\n");
-+		return;
-+	}
-+	prm = (struct rm_obj *)prmpriv->prm_sel;
-+
-+	/* verify attributes */
-+	if (prm->psta == NULL) {
-+		sprintf(pstr(s), "\nErr: inActivate meas has no psta\n");
-+		return;
-+	}
-+
-+	/* measure current channel */
-+	prm->q.ch_num = padapter->mlmeextpriv.cur_channel;
-+	prm->q.op_class = rm_get_oper_class_via_ch(prm->q.ch_num);
-+
-+	/* enquee rmobj */
-+	rm_enqueue_rmobj(padapter, prm, _FALSE);
-+
-+	sprintf(pstr(s), "\nActivate rmid=%x, state=%s, meas_type=%s\n",
-+		prm->rmid, rm_state_name(prm->state),
-+		rm_type_req_name(prm->q.m_type));
-+
-+	sprintf(pstr(s), "aid=%d, mac=" MAC_FMT "\n",
-+		prm->psta->cmn.aid, MAC_ARG(prm->psta->cmn.mac_addr));
-+
-+	/* clearn inActivate prm info */
-+	prmpriv->prm_sel = NULL;
-+}
-+
-+/* for ioctl */
-+int rm_send_bcn_reqs(_adapter *padapter, u8 *sta_addr, u8 op_class, u8 ch,
-+	u16 measure_duration, u8 measure_mode, u8 *bssid, u8 *ssid,
-+	u8 reporting_detail,
-+	u8 n_ap_ch_rpt, struct _RT_OPERATING_CLASS *rpt,
-+	u8 n_elem_id, u8 *elem_id_list)
-+
-+{
-+	struct rm_obj *prm;
-+	char *pact;
-+	struct sta_info *psta;
-+	struct _RT_OPERATING_CLASS *prpt;
-+	void *ptr;
-+	int i,j,sz;
-+	u8 bcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+
-+
-+	if (n_ap_ch_rpt > BCN_REQ_OPT_AP_CH_RPT_MAX_NUM) {
-+		RTW_ERR("RM: chset num %d > %d\n",
-+			n_ap_ch_rpt, BCN_REQ_OPT_AP_CH_RPT_MAX_NUM);
-+		return -1;
-+	}
-+	/* dest sta */
-+	psta = rtw_get_stainfo(&padapter->stapriv, sta_addr);
-+        if (!psta) {
-+		RTW_ERR("RM: psta not found\n");
-+		return -2;
-+        }
-+	prm = rm_alloc_rmobj(padapter);
-+	if (prm == NULL) {
-+		RTW_ERR("RM: unable to alloc rm obj for requeset\n");
-+		return -3;
-+	}
-+
-+	prm->psta = psta;
-+	prm->q.meas_dur = measure_duration;
-+
-+	/* Figure 8-104 Measurement Requested format */
-+	prm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS;
-+	prm->q.action_code = RM_ACT_RADIO_MEAS_REQ;
-+	prm->q.m_mode = measure_mode;
-+	prm->q.m_type = bcn_req;
-+	prm->q.diag_token = rm_gen_dialog_token(padapter);
-+	prm->q.m_token = rm_gen_meas_token(padapter);
-+	prm->rmid = rm_gen_rmid(padapter, prm, RM_MASTER);
-+
-+	prm->q.e_id = _MEAS_REQ_IE_; /* 38 */
-+	prm->q.ch_num = ch;
-+	prm->q.op_class = op_class;
-+	prm->from_ioctl = true;
-+
-+	if (bssid != NULL)
-+		memcpy(prm->q.bssid, bssid, ETH_ALEN);
-+	else
-+		memcpy(prm->q.bssid, bcast, ETH_ALEN);
-+
-+	if (ssid != NULL) {
-+		i = MIN(32, strlen(ssid));
-+		prm->q.opt.bcn.ssid.SsidLength = i;
-+		memcpy(prm->q.opt.bcn.ssid.Ssid, ssid, i);
-+	}
-+
-+	if (n_ap_ch_rpt > 0) {
-+		prm->q.opt.bcn.ap_ch_rpt_num = n_ap_ch_rpt;
-+		j = 0;
-+		for (i = 0; i < n_ap_ch_rpt; i++) {
-+			prpt = rpt++;
-+			if (prpt == NULL)
-+				break;
-+
-+			sz = sizeof(struct _RT_OPERATING_CLASS) * prpt->Len;
-+			ptr = rtw_malloc(sz);
-+			_rtw_memcpy(ptr, prpt, sz);
-+			prm->q.opt.bcn.ap_ch_rpt[i] = (struct _RT_OPERATING_CLASS *)ptr;
-+		}
-+	}
-+	prm->q.opt.bcn.rep_detail = reporting_detail;
-+
-+	if ((n_elem_id > 0) && (n_elem_id < BCN_REQ_REQ_OPT_MAX_NUM)) {
-+		prm->q.opt.bcn.req_id_num = n_elem_id;
-+		_rtw_memcpy(prm->q.opt.bcn.req_id, elem_id_list, n_elem_id);
-+	}
-+	/* enquee rmobj */
-+	rm_enqueue_rmobj(padapter, prm, _FALSE);
-+
-+	RTW_INFO("\nAdd rmid=%x, meas_type=%s ok\n",
-+		prm->rmid, rm_type_req_name(prm->q.m_type));
-+
-+	if (prm->psta)
-+		RTW_INFO("mac="MAC_FMT"\n", MAC_ARG(prm->psta->cmn.mac_addr));
-+	return 0;
-+}
-+
-+void indicate_beacon_report(u8 *sta_addr,
-+	u8 n_measure_rpt, u32 elem_len, u8 *elem)
-+{
-+	RTW_INFO("RM: recv bcn reprot from mac="MAC_FMT"\n", MAC_ARG(sta_addr));
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+	cmap_intfs_nl_beacon_report_event(sta_addr, n_measure_rpt, elem_len, elem);
-+#endif
-+}
-+
-+static void rm_dbg_add_meas(_adapter *padapter, char *s)
-+{
-+	struct rm_priv *prmpriv = &(padapter->rmpriv);
-+	struct rm_obj *prm;
-+	char *pact;
-+
-+
-+	/* example :
-+	* rrm add_meas <aid=1|mac=>,m=<nb|clm|nhm|link>
-+	* rrm run_meas <aid=1|evid=>
-+	*/
-+	prm = (struct rm_obj *)prmpriv->prm_sel;
-+	if (prm == NULL)
-+		prm = rm_alloc_rmobj(padapter);
-+
-+	if (prm == NULL) {
-+		sprintf(pstr(s), "\nErr: alloc meas fail\n");
-+		return;
-+	}
-+
-+        prmpriv->prm_sel = prm;
-+
-+	pact = strstr(s, "act");
-+	if (rm_dbg_modify_meas(padapter, s) == _FAIL) {
-+
-+		sprintf(pstr(s), "\nErr: add meas fail\n");
-+		rm_free_rmobj(prm);
-+		prmpriv->prm_sel = NULL;
-+		return;
-+	}
-+	prm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS;
-+	prm->q.e_id = _MEAS_REQ_IE_; /* 38 */
-+
-+	sprintf(pstr(s), "\nAdd rmid=%x, meas_type=%s ok\n",
-+		prm->rmid, rm_type_req_name(prm->q.m_type));
-+
-+	if (prm->psta)
-+		sprintf(pstr(s), "mac="MAC_FMT"\n",
-+			MAC_ARG(prm->psta->cmn.mac_addr));
-+
-+	if (pact)
-+		rm_dbg_activate_meas(padapter, pstr(s));
-+}
-+
-+static void rm_dbg_del_meas(_adapter *padapter, char *s)
-+{
-+	struct rm_priv *prmpriv = &padapter->rmpriv;
-+	struct rm_obj *prm = (struct rm_obj *)prmpriv->prm_sel;
-+
-+
-+	if (prm) {
-+		sprintf(pstr(s), "\ndelete rmid=%x\n",prm->rmid);
-+
-+		/* free inActivate meas - enqueue yet  */
-+		prmpriv->prm_sel = NULL;
-+		rtw_mfree(prmpriv->prm_sel, sizeof(struct rm_obj));
-+	} else
-+		sprintf(pstr(s), "Err: no inActivate measurement\n");
-+}
-+
-+static void rm_dbg_run_meas(_adapter *padapter, char *s)
-+{
-+	struct rm_obj *prm;
-+	char *pevid, *prmid;
-+	u32 rmid, evid;
-+
-+
-+	prmid = strstr(s, "rmid="); /* hex */
-+	pevid = strstr(s, "evid="); /* dec */
-+
-+	if (prmid && pevid) {
-+		prmid += 5; /* rmid= */
-+		sscanf(prmid, "%x", &rmid);
-+
-+		pevid += 5; /* evid= */
-+		sscanf(pevid, "%u", &evid);
-+	} else {
-+		sprintf(pstr(s), "\nErr: incorrect attribute\n");
-+		return;
-+	}
-+
-+	prm = rm_get_rmobj(padapter, rmid);
-+
-+	if (!prm) {
-+		sprintf(pstr(s), "\nErr: measurement not found\n");
-+		return;
-+	}
-+
-+	if (evid >= RM_EV_max) {
-+		sprintf(pstr(s), "\nErr: wrong event id\n");
-+		return;
-+	}
-+
-+	rm_post_event(padapter, prm->rmid, evid);
-+	sprintf(pstr(s), "\npost %s to rmid=%x\n",rm_event_name(evid), rmid);
-+}
-+
-+static void rm_dbg_show_meas(struct rm_obj *prm, char *s)
-+{
-+	struct sta_info *psta;
-+
-+	psta = prm->psta;
-+
-+	if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
-+
-+		sprintf(pstr(s), "\nrmid=%x, meas_type=%s\n",
-+			prm->rmid, rm_type_req_name(prm->q.m_type));
-+
-+	} else  if (prm->q.action_code == RM_ACT_NB_REP_REQ) {
-+
-+		sprintf(pstr(s), "\nrmid=%x, action=neighbor_req\n",
-+			prm->rmid);
-+	} else
-+		sprintf(pstr(s), "\nrmid=%x, action=unknown\n",
-+			prm->rmid);
-+
-+	if (psta)
-+		sprintf(pstr(s), "aid=%d, mac="MAC_FMT"\n",
-+			psta->cmn.aid, MAC_ARG(psta->cmn.mac_addr));
-+
-+	sprintf(pstr(s), "clock=%d, state=%s, rpt=%u/%u\n",
-+		(int)ATOMIC_READ(&prm->pclock->counter),
-+		rm_state_name(prm->state), prm->p.rpt, prm->q.rpt);
-+}
-+
-+static void rm_dbg_list_meas(_adapter *padapter, char *s)
-+{
-+	int meas_amount;
-+	_irqL irqL;
-+	struct rm_obj *prm;
-+	struct sta_info *psta;
-+	struct rm_priv *prmpriv = &padapter->rmpriv;
-+	_queue *queue = &prmpriv->rm_queue;
-+	_list *plist, *phead;
-+
-+
-+	sprintf(pstr(s), "\n");
-+	_enter_critical(&queue->lock, &irqL);
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+	meas_amount = 0;
-+
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+		prm = LIST_CONTAINOR(plist, struct rm_obj, list);
-+		meas_amount++;
-+		plist = get_next(plist);
-+		psta = prm->psta;
-+		sprintf(pstr(s), "=========================================\n");
-+
-+		rm_dbg_show_meas(prm, s);
-+	}
-+	_exit_critical(&queue->lock, &irqL);
-+
-+	sprintf(pstr(s), "=========================================\n");
-+
-+	if (meas_amount==0) {
-+		sprintf(pstr(s), "No Activate measurement\n");
-+		sprintf(pstr(s), "=========================================\n");
-+	}
-+
-+	if (prmpriv->prm_sel == NULL)
-+		sprintf(pstr(s), "\nNo inActivate measurement\n");
-+	else {
-+		sprintf(pstr(s), "\ninActivate measurement\n");
-+		rm_dbg_show_meas((struct rm_obj *)prmpriv->prm_sel, s);
-+	}
-+}
-+#endif /* RM_SUPPORT_IWPRIV_DBG */
-+
-+int verify_bcn_req(_adapter *padapter, struct sta_info *psta)
-+{
-+	char *bssid =  NULL;
-+	char ssid[] = "RealKungFu";
-+	u8 op_class = 0;
-+	u8 ch = 255;
-+	u16 measure_duration = 100;
-+	u8 reporting_detaial = 0;
-+	u8 n_ap_ch_rpt = 6;
-+	u8 measure_mode = bcn_req_active;
-+	u8 req[] = {1,2,3};
-+	u8 req_len = sizeof(req);
-+
-+
-+	static RT_OPERATING_CLASS US[] = {
-+	/* 0, OP_CLASS_NULL */	//{  0,  0, {}},
-+	/* 1, OP_CLASS_1 */	{115,  4, {36, 40, 44, 48}},
-+	/* 2, OP_CLASS_2 */	{118,  4, {52, 56, 60, 64}},
-+	/* 3, OP_CLASS_3 */	{124,  4, {149, 153, 157, 161}},
-+	/* 4, OP_CLASS_4 */	{121, 11, {100, 104, 108, 112, 116, 120, 124,
-+						128, 132, 136, 140}},
-+	/* 5, OP_CLASS_5 */	{125,  5, {149, 153, 157, 161, 165}},
-+	/* 6, OP_CLASS_12 */	{ 81, 11, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}}
-+	};
-+
-+	rm_send_bcn_reqs(padapter, psta->cmn.mac_addr, op_class, ch,
-+		measure_duration, measure_mode, bssid, ssid,
-+		reporting_detaial, n_ap_ch_rpt, US, req_len, req);
-+	return 0;
-+}
-+
-+void rm_dbg_cmd(_adapter *padapter, char *s)
-+{
-+	unsigned val;
-+	char *paid;
-+	struct sta_info *psta=NULL;
-+
-+#if (RM_SUPPORT_IWPRIV_DBG)
-+	if (_rtw_memcmp(s, "help", 4)) {
-+		rm_dbg_help(padapter, s);
-+
-+	} else if (_rtw_memcmp(s, "send_bcn_req", 12)) {
-+
-+		/* rtwpriv wls1 rrm send_bcn_req aid=1 */
-+		paid = strstr(s, "aid=");
-+		if (paid) { /* find sta_info according to aid */
-+			paid += 4; /* skip aid= */
-+			sscanf(paid, "%u", &val); /* aid=x */
-+			psta = rm_get_sta(padapter, val, NULL);
-+
-+			if (psta)
-+				verify_bcn_req(padapter, psta);
-+		}
-+
-+	} else if (_rtw_memcmp(s, "list_sta", 8)) {
-+		rm_dbg_list_sta(padapter, s);
-+
-+	} else if (_rtw_memcmp(s, "list_meas", 9)) {
-+		rm_dbg_list_meas(padapter, s);
-+
-+	} else if (_rtw_memcmp(s, "add_meas", 8)) {
-+		rm_dbg_add_meas(padapter, s);
-+
-+	} else if (_rtw_memcmp(s, "del_meas", 8)) {
-+		rm_dbg_del_meas(padapter, s);
-+
-+	} else if (_rtw_memcmp(s, "activate", 8)) {
-+		rm_dbg_activate_meas(padapter, s);
-+
-+	} else if (_rtw_memcmp(s, "run_meas", 8)) {
-+		rm_dbg_run_meas(padapter, s);
-+
-+	} else if (_rtw_memcmp(s, "nb", 2)) {
-+
-+		paid = strstr(s, "aid=");
-+
-+		if (paid) { /* find sta_info according to aid */
-+			paid += 4; /* skip aid= */
-+			sscanf(paid, "%u", &val); /* aid=x */
-+			psta = rm_get_sta(padapter, val, NULL);
-+
-+			if (psta)
-+				rm_add_nb_req(padapter, psta);
-+		}
-+	}
-+#else
-+	sprintf(pstr(s), "\n");
-+	sprintf(pstr(s), "rrm debug command was disabled\n");
-+#endif
-+}
-+#endif /* CONFIG_RTW_80211K */
-diff --git a/drivers/staging/rtl8723cs/core/rtw_rm_fsm.c b/drivers/staging/rtl8723cs/core/rtw_rm_fsm.c
-new file mode 100644
-index 000000000000..244b799a2f1a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_rm_fsm.c
-@@ -0,0 +1,1017 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+#ifdef CONFIG_RTW_80211K
-+#include "rtw_rm_fsm.h"
-+#include "rtw_rm_util.h"
-+
-+struct fsm_state {
-+	u8 *name;
-+	int(*fsm_func)(struct rm_obj *prm, enum RM_EV_ID evid);
-+};
-+
-+static void rm_state_initial(struct rm_obj *prm);
-+static void rm_state_goto(struct rm_obj *prm, enum RM_STATE rm_state);
-+static void rm_state_run(struct rm_obj *prm, enum RM_EV_ID evid);
-+static struct rm_event *rm_dequeue_ev(_queue *queue);
-+static struct rm_obj *rm_dequeue_rm(_queue *queue);
-+
-+void rm_timer_callback(void *data)
-+{
-+	int i;
-+	_adapter *padapter = (_adapter *)data;
-+	struct rm_priv *prmpriv = &padapter->rmpriv;
-+	struct rm_clock *pclock;
-+
-+
-+	/* deal with clock */
-+	for (i=0;i<RM_TIMER_NUM;i++) {
-+		pclock = &prmpriv->clock[i];
-+		if (pclock->prm == NULL
-+			||(ATOMIC_READ(&(pclock->counter)) == 0))
-+			continue;
-+
-+		ATOMIC_DEC(&(pclock->counter));
-+
-+		if (ATOMIC_READ(&(pclock->counter)) == 0)
-+			rm_post_event(pclock->prm->psta->padapter,
-+				pclock->prm->rmid, prmpriv->clock[i].evid);
-+	}
-+	_set_timer(&prmpriv->rm_timer, CLOCK_UNIT);
-+}
-+
-+int rtw_init_rm(_adapter *padapter)
-+{
-+	struct rm_priv *prmpriv = &padapter->rmpriv;
-+
-+
-+	RTW_INFO("RM: %s\n",__func__);
-+	_rtw_init_queue(&(prmpriv->rm_queue));
-+	_rtw_init_queue(&(prmpriv->ev_queue));
-+
-+	/* bit 0-7 */
-+	prmpriv->rm_en_cap_def[0] = 0
-+		| BIT(RM_LINK_MEAS_CAP_EN)
-+		| BIT(RM_NB_REP_CAP_EN)
-+		/*| BIT(RM_PARAL_MEAS_CAP_EN)*/
-+		| BIT(RM_REPEAT_MEAS_CAP_EN)
-+		| BIT(RM_BCN_PASSIVE_MEAS_CAP_EN)
-+		| BIT(RM_BCN_ACTIVE_MEAS_CAP_EN)
-+		| BIT(RM_BCN_TABLE_MEAS_CAP_EN)
-+		/*| BIT(RM_BCN_MEAS_REP_COND_CAP_EN)*/;
-+
-+	/* bit  8-15 */
-+	prmpriv->rm_en_cap_def[1] = 0
-+		/*| BIT(RM_FRAME_MEAS_CAP_EN - 8)*/
-+#ifdef CONFIG_RTW_ACS
-+		| BIT(RM_CH_LOAD_CAP_EN - 8)
-+		| BIT(RM_NOISE_HISTO_CAP_EN - 8)
-+#endif
-+		/*| BIT(RM_STATIS_MEAS_CAP_EN - 8)*/
-+		/*| BIT(RM_LCI_MEAS_CAP_EN - 8)*/
-+		/*| BIT(RM_LCI_AMIMUTH_CAP_EN - 8)*/
-+		/*| BIT(RM_TRANS_STREAM_CAT_MEAS_CAP_EN - 8)*/
-+		/*| BIT(RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN - 8)*/;
-+
-+	/* bit 16-23 */
-+	prmpriv->rm_en_cap_def[2] = 0
-+		/*| BIT(RM_AP_CH_REP_CAP_EN - 16)*/
-+		/*| BIT(RM_RM_MIB_CAP_EN - 16)*/
-+		/*| BIT(RM_OP_CH_MAX_MEAS_DUR0 - 16)*/
-+		/*| BIT(RM_OP_CH_MAX_MEAS_DUR1 - 16)*/
-+		/*| BIT(RM_OP_CH_MAX_MEAS_DUR2 - 16)*/
-+		/*| BIT(RM_NONOP_CH_MAX_MEAS_DUR0 - 16)*/
-+		/*| BIT(RM_NONOP_CH_MAX_MEAS_DUR1 - 16)*/
-+		/*| BIT(RM_NONOP_CH_MAX_MEAS_DUR2 - 16)*/;
-+
-+	/* bit 24-31 */
-+	prmpriv->rm_en_cap_def[3] = 0
-+		/*| BIT(RM_MEAS_PILOT_CAP0 - 24)*/
-+		/*| BIT(RM_MEAS_PILOT_CAP1 - 24)*/
-+		/*| BIT(RM_MEAS_PILOT_CAP2 - 24)*/
-+		/*| BIT(RM_MEAS_PILOT_TRANS_INFO_CAP_EN - 24)*/
-+		/*| BIT(RM_NB_REP_TSF_OFFSET_CAP_EN - 24)*/
-+		| BIT(RM_RCPI_MEAS_CAP_EN - 24)
-+		| BIT(RM_RSNI_MEAS_CAP_EN - 24)
-+		/*| BIT(RM_BSS_AVG_ACCESS_DELAY_CAP_EN - 24)*/;
-+
-+	/* bit 32-39 */
-+	prmpriv->rm_en_cap_def[4] = 0
-+		/*| BIT(RM_BSS_AVG_ACCESS_DELAY_CAP_EN - 32)*/
-+		/*| BIT(RM_AVALB_ADMIS_CAPACITY_CAP_EN - 32)*/
-+		/*| BIT(RM_ANT_CAP_EN - 32)*/;
-+
-+	prmpriv->enable = _TRUE;
-+
-+	/* clock timer */
-+	rtw_init_timer(&prmpriv->rm_timer,
-+		padapter, rm_timer_callback, padapter);
-+	_set_timer(&prmpriv->rm_timer, CLOCK_UNIT);
-+
-+	prmpriv->meas_token = 1;
-+	return _SUCCESS;
-+}
-+
-+int rtw_deinit_rm(_adapter *padapter)
-+{
-+	struct rm_priv *prmpriv = &padapter->rmpriv;
-+	struct rm_obj *prm;
-+	struct rm_event *pev;
-+
-+
-+	RTW_INFO("RM: %s\n",__func__);
-+	prmpriv->enable = _FALSE;
-+	_cancel_timer_ex(&prmpriv->rm_timer);
-+
-+	/* free all events and measurements */
-+	while((pev = rm_dequeue_ev(&prmpriv->ev_queue)) != NULL)
-+		rtw_mfree((void *)pev, sizeof(struct rm_event));
-+
-+	while((prm = rm_dequeue_rm(&prmpriv->rm_queue)) != NULL)
-+		rm_state_run(prm, RM_EV_cancel);
-+
-+	_rtw_deinit_queue(&(prmpriv->rm_queue));
-+	_rtw_deinit_queue(&(prmpriv->ev_queue));
-+
-+	return _SUCCESS;
-+}
-+
-+int rtw_free_rm_priv(_adapter *padapter)
-+{
-+	return rtw_deinit_rm(padapter);
-+}
-+
-+static int rm_enqueue_ev(_queue *queue, struct rm_event *obj, bool to_head)
-+{
-+	_irqL irqL;
-+
-+
-+	if (obj == NULL)
-+		return _FAIL;
-+
-+	_enter_critical(&queue->lock, &irqL);
-+
-+	if (to_head)
-+		rtw_list_insert_head(&obj->list, &queue->queue);
-+	else
-+		rtw_list_insert_tail(&obj->list, &queue->queue);
-+
-+	_exit_critical(&queue->lock, &irqL);
-+
-+	return _SUCCESS;
-+}
-+
-+static void rm_set_clock(struct rm_obj *prm, u32 ms, enum RM_EV_ID evid)
-+{
-+	ATOMIC_SET(&(prm->pclock->counter), (ms/CLOCK_UNIT));
-+	prm->pclock->evid = evid;
-+}
-+
-+static struct rm_clock *rm_alloc_clock(_adapter *padapter, struct rm_obj *prm)
-+{
-+	int i;
-+	struct rm_priv *prmpriv = &padapter->rmpriv;
-+	struct rm_clock *pclock = NULL;
-+
-+
-+	for (i=0;i<RM_TIMER_NUM;i++) {
-+		pclock = &prmpriv->clock[i];
-+
-+		if (pclock->prm == NULL) {
-+			pclock->prm = prm;
-+			ATOMIC_SET(&(pclock->counter), 0);
-+			pclock->evid = RM_EV_max;
-+			break;
-+		}
-+	}
-+	return pclock;
-+}
-+
-+static void rm_cancel_clock(struct rm_obj *prm)
-+{
-+	ATOMIC_SET(&(prm->pclock->counter), 0);
-+	prm->pclock->evid = RM_EV_max;
-+}
-+
-+static void rm_free_clock(struct rm_clock *pclock)
-+{
-+	pclock->prm = NULL;
-+	ATOMIC_SET(&(pclock->counter), 0);
-+	pclock->evid = RM_EV_max;
-+}
-+
-+static int is_list_linked(const struct list_head *head)
-+{
-+	return head->prev != NULL;
-+}
-+
-+void rm_free_rmobj(struct rm_obj *prm)
-+{
-+	if (is_list_linked(&prm->list))
-+		rtw_list_delete(&prm->list);
-+
-+	if (prm->q.pssid)
-+		rtw_mfree(prm->q.pssid, strlen(prm->q.pssid)+1);
-+
-+	if (prm->q.opt.bcn.req_start)
-+		rtw_mfree(prm->q.opt.bcn.req_start,
-+			prm->q.opt.bcn.req_len);
-+
-+	if (prm->pclock)
-+		rm_free_clock(prm->pclock);
-+
-+	rtw_mfree((void *)prm, sizeof(struct rm_obj));
-+}
-+
-+struct rm_obj *rm_alloc_rmobj(_adapter *padapter)
-+{
-+	struct rm_obj *prm;
-+
-+
-+	prm = (struct rm_obj *)rtw_malloc(sizeof(struct rm_obj));
-+	if (prm == NULL)
-+		return NULL;
-+
-+	_rtw_memset(prm, 0, sizeof(struct rm_obj));
-+
-+	/* alloc timer */
-+	if ((prm->pclock = rm_alloc_clock(padapter, prm)) == NULL) {
-+		rm_free_rmobj(prm);
-+		return NULL;
-+	}
-+	return prm;
-+}
-+
-+int rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *prm, bool to_head)
-+{
-+	_irqL irqL;
-+	struct rm_priv *prmpriv = &padapter->rmpriv;
-+	_queue *queue = &prmpriv->rm_queue;
-+
-+
-+	if (prm == NULL)
-+		return _FAIL;
-+
-+	_enter_critical(&queue->lock, &irqL);
-+	if (to_head)
-+		rtw_list_insert_head(&prm->list, &queue->queue);
-+	else
-+		rtw_list_insert_tail(&prm->list, &queue->queue);
-+	_exit_critical(&queue->lock, &irqL);
-+
-+	rm_state_initial(prm);
-+
-+	return _SUCCESS;
-+}
-+
-+static struct rm_obj *rm_dequeue_rm(_queue *queue)
-+{
-+	_irqL irqL;
-+	struct rm_obj *prm;
-+
-+
-+	_enter_critical(&queue->lock, &irqL);
-+	if (rtw_is_list_empty(&(queue->queue)))
-+		prm = NULL;
-+	else {
-+		prm = LIST_CONTAINOR(get_next(&(queue->queue)),
-+			struct rm_obj, list);
-+		/* rtw_list_delete(&prm->list); */
-+	}
-+	_exit_critical(&queue->lock, &irqL);
-+
-+	return prm;
-+}
-+
-+static struct rm_event *rm_dequeue_ev(_queue *queue)
-+{
-+	_irqL irqL;
-+	struct rm_event *ev;
-+
-+
-+	_enter_critical(&queue->lock, &irqL);
-+	if (rtw_is_list_empty(&(queue->queue)))
-+		ev = NULL;
-+	else {
-+		ev = LIST_CONTAINOR(get_next(&(queue->queue)),
-+			struct rm_event, list);
-+		rtw_list_delete(&ev->list);
-+	}
-+	_exit_critical(&queue->lock, &irqL);
-+
-+	return ev;
-+}
-+
-+static struct rm_obj *_rm_get_rmobj(_queue *queue, u32 rmid)
-+{
-+	_irqL irqL;
-+	_list *phead, *plist;
-+	struct rm_obj *prm = NULL;
-+
-+
-+	if (rmid == 0)
-+		return NULL;
-+
-+	_enter_critical(&queue->lock, &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+
-+		prm = LIST_CONTAINOR(plist, struct rm_obj, list);
-+		if (rmid == (prm->rmid)) {
-+			_exit_critical(&queue->lock, &irqL);
-+			return prm;
-+		}
-+		plist = get_next(plist);
-+	}
-+	_exit_critical(&queue->lock, &irqL);
-+
-+	return NULL;
-+}
-+
-+struct sta_info *rm_get_psta(_adapter *padapter, u32 rmid)
-+{
-+	struct rm_priv *prmpriv = &padapter->rmpriv;
-+	struct rm_obj *prm;
-+
-+
-+	prm = _rm_get_rmobj(&prmpriv->rm_queue, rmid);
-+
-+	if (prm)
-+		return prm->psta;
-+
-+	return NULL;
-+}
-+
-+struct rm_obj *rm_get_rmobj(_adapter *padapter, u32 rmid)
-+{
-+	struct rm_priv *prmpriv = &padapter->rmpriv;
-+
-+	return _rm_get_rmobj(&prmpriv->rm_queue, rmid);
-+}
-+
-+u8 rtw_rm_post_envent_cmd(_adapter *padapter, u32 rmid, u8 evid)
-+{
-+	struct cmd_obj *pcmd;
-+	struct rm_event *pev;
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+	u8 res = _SUCCESS;
-+
-+
-+	pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (pcmd == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	pev = (struct rm_event*)rtw_zmalloc(sizeof(struct rm_event));
-+
-+	if (pev == NULL) {
-+		rtw_mfree((u8 *) pcmd, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	pev->rmid = rmid;
-+	pev->evid = evid;
-+
-+	init_h2fwcmd_w_parm_no_rsp(pcmd, pev, CMD_RM_POST_EVENT);
-+	res = rtw_enqueue_cmd(pcmdpriv, pcmd);
-+exit:
-+	return res;
-+}
-+
-+int rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid)
-+{
-+	if (padapter->rmpriv.enable == _FALSE)
-+		return _FALSE;
-+
-+	RTW_INFO("RM: post asyn %s to rmid=%x\n", rm_event_name(evid), rmid);
-+	rtw_rm_post_envent_cmd(padapter, rmid, evid);
-+	return _SUCCESS;
-+}
-+
-+int _rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid)
-+{
-+	struct rm_priv *prmpriv = &padapter->rmpriv;
-+	struct rm_event *pev;
-+
-+	if (evid >= RM_EV_max || rmid == 0)
-+		return _FALSE;
-+
-+	pev = (struct rm_event *)rtw_malloc(sizeof(struct rm_event));
-+	if (pev == NULL)
-+		return _FALSE;
-+
-+	pev->rmid = rmid;
-+	pev->evid = evid;
-+
-+	RTW_INFO("RM: post sync %s to rmid=%x\n", rm_event_name(evid), rmid);
-+	rm_enqueue_ev(&prmpriv->ev_queue, pev, FALSE);
-+
-+	return _SUCCESS;
-+}
-+
-+static void rm_bcast_aid_handler(_adapter *padapter, struct rm_event *pev)
-+{
-+	_irqL irqL;
-+	_list *phead, *plist;
-+	_queue *queue = &padapter->rmpriv.rm_queue;
-+	struct rm_obj *prm;
-+
-+
-+	_enter_critical(&queue->lock, &irqL);
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+
-+		prm = LIST_CONTAINOR(plist, struct rm_obj, list);
-+		plist = get_next(plist);
-+		if (RM_GET_AID(pev->rmid) == RM_GET_AID(prm->rmid)) {
-+			_exit_critical(&queue->lock, &irqL);
-+			rm_state_run(prm, pev->evid);
-+			_enter_critical(&queue->lock, &irqL);
-+		}
-+	}
-+	_exit_critical(&queue->lock, &irqL);
-+	return;
-+}
-+
-+/* main handler of RM (Resource Management) */
-+void rm_handler(_adapter *padapter, struct rm_event *pe)
-+{
-+	int i;
-+	struct rm_priv *prmpriv = &padapter->rmpriv;
-+	struct rm_obj *prm;
-+	struct rm_event *pev;
-+
-+
-+	/* dequeue event */
-+	while((pev = rm_dequeue_ev(&prmpriv->ev_queue)) != NULL)
-+	{
-+		if (RM_IS_ID_FOR_ALL(pev->rmid)) {
-+			/* apply to all aid mateched measurement */
-+			rm_bcast_aid_handler(padapter, pev);
-+			rtw_mfree((void *)pev, sizeof(struct rm_event));
-+			continue;
-+		}
-+
-+		/* retrieve rmobj */
-+		prm = _rm_get_rmobj(&prmpriv->rm_queue, pev->rmid);
-+		if (prm == NULL) {
-+			RTW_ERR("RM: rmid=%x event=%s doesn't find rm obj\n",
-+				pev->rmid, rm_event_name(pev->evid));
-+			rtw_mfree((void *)pev, sizeof(struct rm_event));
-+			return;
-+		}
-+		/* run state machine */
-+		rm_state_run(prm, pev->evid);
-+		rtw_mfree((void *)pev, sizeof(struct rm_event));
-+	}
-+}
-+
-+static int rm_issue_meas_req(struct rm_obj *prm)
-+{
-+	switch (prm->q.action_code) {
-+	case RM_ACT_RADIO_MEAS_REQ:
-+		switch (prm->q.m_type) {
-+		case bcn_req:
-+		case ch_load_req:
-+		case noise_histo_req:
-+			issue_radio_meas_req(prm);
-+			break;
-+		default:
-+			break;
-+		} /* meas_type */
-+		break;
-+	case RM_ACT_NB_REP_REQ:
-+		/* issue neighbor request */
-+		issue_nb_req(prm);
-+		break;
-+	case RM_ACT_LINK_MEAS_REQ:
-+		issue_link_meas_req(prm);
-+		break;
-+	default:
-+		return _FALSE;
-+	} /* action_code */
-+
-+	return _SUCCESS;
-+}
-+
-+/*
-+* RM state machine
-+*/
-+
-+static int rm_state_idle(struct rm_obj *prm, enum RM_EV_ID evid)
-+{
-+	_adapter *padapter = prm->psta->padapter;
-+	u8 val8;
-+	u32 val32;
-+
-+
-+	prm->p.category = RTW_WLAN_CATEGORY_RADIO_MEAS;
-+
-+	switch (evid) {
-+	case RM_EV_state_in:
-+		switch (prm->q.action_code) {
-+		case RM_ACT_RADIO_MEAS_REQ:
-+			/* copy attrib from meas_req to meas_rep */
-+			prm->p.action_code = RM_ACT_RADIO_MEAS_REP;
-+			prm->p.diag_token = prm->q.diag_token;
-+			prm->p.e_id = _MEAS_RSP_IE_;
-+			prm->p.m_token = prm->q.m_token;
-+			prm->p.m_type = prm->q.m_type;
-+			prm->p.rpt = prm->q.rpt;
-+			prm->p.ch_num = prm->q.ch_num;
-+			prm->p.op_class = prm->q.op_class;
-+
-+			if (prm->q.m_type == ch_load_req
-+				|| prm->q.m_type == noise_histo_req) {
-+				/*
-+				 * phydm measure current ch periodically
-+				 * scan current ch is not necessary
-+				 */
-+				val8 = padapter->mlmeextpriv.cur_channel;
-+				if (prm->q.ch_num == val8)
-+					prm->poll_mode = 1;
-+			}
-+			RTW_INFO("RM: rmid=%x %s switch in repeat=%u\n",
-+				prm->rmid, rm_type_req_name(prm->q.m_type),
-+				prm->q.rpt);
-+			break;
-+		case RM_ACT_NB_REP_REQ:
-+			prm->p.action_code = RM_ACT_NB_REP_RESP;
-+			RTW_INFO("RM: rmid=%x Neighbor request switch in\n",
-+				prm->rmid);
-+			break;
-+		case RM_ACT_LINK_MEAS_REQ:
-+			prm->p.diag_token = prm->q.diag_token;
-+			prm->p.action_code = RM_ACT_LINK_MEAS_REP;
-+			RTW_INFO("RM: rmid=%x Link meas switch in\n",
-+				prm->rmid);
-+			break;
-+		default:
-+			prm->p.action_code = prm->q.action_code;
-+			rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
-+			RTW_INFO("RM: rmid=%x recv unknown action %d\n",
-+				prm->rmid,prm->p.action_code);
-+			break;
-+		} /* switch() */
-+
-+		if (prm->rmid & RM_MASTER) {
-+			if (rm_issue_meas_req(prm) == _SUCCESS)
-+				rm_state_goto(prm, RM_ST_WAIT_MEAS);
-+			else
-+				rm_state_goto(prm, RM_ST_END);
-+			return _SUCCESS;
-+		} else {
-+			rm_state_goto(prm, RM_ST_DO_MEAS);
-+			return _SUCCESS;
-+		}
-+
-+		if (prm->p.m_mode) {
-+			issue_null_reply(prm);
-+			rm_state_goto(prm, RM_ST_END);
-+			return _SUCCESS;
-+		}
-+		if (prm->q.rand_intvl) {
-+			/* get low tsf to generate random interval */
-+			val32 = rtw_read32(padapter, REG_TSFTR);
-+			val32 = val32 % prm->q.rand_intvl;
-+			RTW_INFO("RM: rmid=%x rand_intval=%d, rand=%d\n",
-+				prm->rmid, (int)prm->q.rand_intvl,val32);
-+			rm_set_clock(prm, prm->q.rand_intvl,
-+				RM_EV_delay_timer_expire);
-+			return _SUCCESS;
-+		}
-+		break;
-+	case RM_EV_delay_timer_expire:
-+		rm_state_goto(prm, RM_ST_DO_MEAS);
-+		break;
-+	case RM_EV_cancel:
-+		rm_state_goto(prm, RM_ST_END);
-+		break;
-+	case RM_EV_state_out:
-+		rm_cancel_clock(prm);
-+		break;
-+	default:
-+		break;
-+	}
-+	return _SUCCESS;
-+}
-+
-+/* we do the measuring */
-+static int rm_state_do_meas(struct rm_obj *prm, enum RM_EV_ID evid)
-+{
-+	_adapter *padapter = prm->psta->padapter;
-+	u8 val8;
-+	u64 val64;
-+
-+
-+	switch (evid) {
-+	case RM_EV_state_in:
-+		if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
-+			switch (prm->q.m_type) {
-+			case bcn_req:
-+				if (prm->q.m_mode == bcn_req_bcn_table) {
-+					RTW_INFO("RM: rmid=%x Beacon table\n",
-+						prm->rmid);
-+					_rm_post_event(padapter, prm->rmid,
-+						RM_EV_survey_done);
-+					return _SUCCESS;
-+				}
-+				break;
-+			case ch_load_req:
-+			case noise_histo_req:
-+				if (prm->poll_mode)
-+					_rm_post_event(padapter, prm->rmid,
-+						RM_EV_survey_done);
-+				return _SUCCESS;
-+			default:
-+				rm_state_goto(prm, RM_ST_END);
-+				return _SUCCESS;
-+			}
-+
-+			if (!ready_for_scan(prm)) {
-+				prm->wait_busy = RM_BUSY_TRAFFIC_TIMES;
-+				RTW_INFO("RM: wait busy traffic - %d\n",
-+					prm->wait_busy);
-+				rm_set_clock(prm, RM_WAIT_BUSY_TIMEOUT,
-+					RM_EV_busy_timer_expire);
-+				return _SUCCESS;
-+			}
-+		} else if (prm->q.action_code == RM_ACT_LINK_MEAS_REQ) {
-+			; /* do nothing */
-+			rm_state_goto(prm, RM_ST_SEND_REPORT);
-+			return _SUCCESS;
-+		}
-+		_rm_post_event(padapter, prm->rmid, RM_EV_start_meas);
-+		break;
-+	case RM_EV_start_meas:
-+		if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
-+			/* resotre measurement start time */
-+			prm->meas_start_time = rtw_hal_get_tsftr_by_port(padapter
-+									, rtw_hal_get_port(padapter));
-+
-+			switch (prm->q.m_type) {
-+			case bcn_req:
-+				val8 = 1; /* Enable free run counter */
-+				prm->free_run_counter_valid = rtw_hal_set_hwreg(
-+					padapter, HW_VAR_FREECNT, &val8);
-+
-+				rm_sitesurvey(prm);
-+				break;
-+			case ch_load_req:
-+			case noise_histo_req:
-+				rm_sitesurvey(prm);
-+				break;
-+			default:
-+				rm_state_goto(prm, RM_ST_END);
-+				return _SUCCESS;
-+				break;
-+			}
-+		}
-+		/* handle measurement timeout */
-+		rm_set_clock(prm, RM_MEAS_TIMEOUT, RM_EV_meas_timer_expire);
-+		break;
-+	case RM_EV_survey_done:
-+		if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
-+			switch (prm->q.m_type) {
-+			case bcn_req:
-+				rm_cancel_clock(prm);
-+				rm_state_goto(prm, RM_ST_SEND_REPORT);
-+				return _SUCCESS;
-+			case ch_load_req:
-+			case noise_histo_req:
-+				retrieve_radio_meas_result(prm);
-+
-+				if (rm_radio_meas_report_cond(prm) == _SUCCESS)
-+					rm_state_goto(prm, RM_ST_SEND_REPORT);
-+				else
-+					rm_set_clock(prm, RM_COND_INTVL,
-+						RM_EV_retry_timer_expire);
-+				break;
-+			default:
-+				rm_state_goto(prm, RM_ST_END);
-+				return _SUCCESS;
-+			}
-+		}
-+		break;
-+	case RM_EV_meas_timer_expire:
-+		RTW_INFO("RM: rmid=%x measurement timeount\n",prm->rmid);
-+		rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
-+		issue_null_reply(prm);
-+		rm_state_goto(prm, RM_ST_END);
-+		break;
-+	case RM_EV_busy_timer_expire:
-+		if (!ready_for_scan(prm) && prm->wait_busy--) {
-+			RTW_INFO("RM: wait busy - %d\n",prm->wait_busy);
-+			rm_set_clock(prm, RM_WAIT_BUSY_TIMEOUT,
-+				RM_EV_busy_timer_expire);
-+			break;
-+		}
-+		else if (prm->wait_busy <= 0) {
-+			RTW_INFO("RM: wait busy timeout\n");
-+			rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
-+			issue_null_reply(prm);
-+			rm_state_goto(prm, RM_ST_END);
-+			return _SUCCESS;
-+		}
-+		_rm_post_event(padapter, prm->rmid, RM_EV_start_meas);
-+		break;
-+	case RM_EV_request_timer_expire:
-+		rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
-+		issue_null_reply(prm);
-+		rm_state_goto(prm, RM_ST_END);
-+		break;
-+	case RM_EV_retry_timer_expire:
-+		/* expired due to meas condition mismatch, meas again */
-+		_rm_post_event(padapter, prm->rmid, RM_EV_start_meas);
-+		break;
-+	case RM_EV_cancel:
-+		rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
-+		issue_null_reply(prm);
-+		rm_state_goto(prm, RM_ST_END);
-+		break;
-+	case RM_EV_state_out:
-+		rm_cancel_clock(prm);
-+		/* resotre measurement end time */
-+		prm->meas_end_time = rtw_hal_get_tsftr_by_port(padapter
-+								, rtw_hal_get_port(padapter));
-+
-+		val8 = 0; /* Disable free run counter */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_FREECNT, &val8);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+static int rm_state_wait_meas(struct rm_obj *prm, enum RM_EV_ID evid)
-+{
-+	u8 val8;
-+	u64 val64;
-+
-+
-+	switch (evid) {
-+	case RM_EV_state_in:
-+		/* we create meas_req, waiting for peer report */
-+		rm_set_clock(prm, RM_REQ_TIMEOUT,
-+			RM_EV_request_timer_expire);
-+		break;
-+	case RM_EV_recv_rep:
-+		rm_state_goto(prm, RM_ST_RECV_REPORT);
-+		break;
-+	case RM_EV_request_timer_expire:
-+	case RM_EV_cancel:
-+		rm_state_goto(prm, RM_ST_END);
-+		break;
-+	case RM_EV_state_out:
-+		rm_cancel_clock(prm);
-+		break;
-+	default:
-+		break;
-+	}
-+	return _SUCCESS;
-+}
-+
-+static int rm_state_send_report(struct rm_obj *prm, enum RM_EV_ID evid)
-+{
-+	u8 val8;
-+
-+
-+	switch (evid) {
-+	case RM_EV_state_in:
-+		/* we have to issue report */
-+		if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
-+			switch (prm->q.m_type) {
-+			case bcn_req:
-+				issue_beacon_rep(prm);
-+				break;
-+			case ch_load_req:
-+			case noise_histo_req:
-+				issue_radio_meas_rep(prm);
-+				break;
-+			default:
-+				rm_state_goto(prm, RM_ST_END);
-+				return _SUCCESS;
-+			}
-+
-+		} else if (prm->q.action_code == RM_ACT_LINK_MEAS_REQ) {
-+			issue_link_meas_rep(prm);
-+			rm_state_goto(prm, RM_ST_END);
-+			return _SUCCESS;
-+
-+		} else {
-+			rm_state_goto(prm, RM_ST_END);
-+			return _SUCCESS;
-+		}
-+
-+		/* check repeat */
-+		if (prm->p.rpt) {
-+			RTW_INFO("RM: rmid=%x repeat=%u/%u\n",
-+				prm->rmid, prm->p.rpt,
-+				prm->q.rpt);
-+			prm->p.rpt--;
-+			/*
-+			* we recv meas_req,
-+			* delay for a wihile and than meas again
-+			*/
-+			if (prm->poll_mode)
-+				rm_set_clock(prm, RM_REPT_POLL_INTVL,
-+					RM_EV_repeat_delay_expire);
-+			else
-+				rm_set_clock(prm, RM_REPT_SCAN_INTVL,
-+					RM_EV_repeat_delay_expire);
-+			return _SUCCESS;
-+		}
-+		/* we are done */
-+		rm_state_goto(prm, RM_ST_END);
-+		break;
-+	case RM_EV_repeat_delay_expire:
-+		rm_state_goto(prm, RM_ST_DO_MEAS);
-+		break;
-+	case RM_EV_cancel:
-+		rm_state_goto(prm, RM_ST_END);
-+		break;
-+	case RM_EV_state_out:
-+		rm_cancel_clock(prm);
-+		break;
-+	default:
-+		break;
-+	}
-+	return _SUCCESS;
-+}
-+
-+static int rm_state_recv_report(struct rm_obj *prm, enum RM_EV_ID evid)
-+{
-+	u8 val8;
-+
-+
-+	switch (evid) {
-+	case RM_EV_state_in:
-+		/* we issue meas_req, got peer's meas report */
-+		switch (prm->p.action_code) {
-+		case RM_ACT_RADIO_MEAS_REP:
-+			/* check refuse, incapable and repeat */
-+			val8 = prm->p.m_mode;
-+			if (val8) {
-+				RTW_INFO("RM: rmid=%x peer reject (%s repeat=%d)\n",
-+					prm->rmid,
-+					val8|MEAS_REP_MOD_INCAP?"INCAP":
-+					val8|MEAS_REP_MOD_REFUSE?"REFUSE":
-+					val8|MEAS_REP_MOD_LATE?"LATE":"",
-+					prm->p.rpt);
-+				rm_state_goto(prm, RM_ST_END);
-+				return _SUCCESS;
-+			}
-+			break;
-+		case RM_ACT_NB_REP_RESP:
-+			/* report to upper layer if needing */
-+			rm_state_goto(prm, RM_ST_END);
-+			return _SUCCESS;
-+		default:
-+			rm_state_goto(prm, RM_ST_END);
-+			return _SUCCESS;
-+		}
-+		/* check repeat */
-+		if (prm->p.rpt) {
-+			RTW_INFO("RM: rmid=%x repeat=%u/%u\n",
-+				prm->rmid, prm->p.rpt,
-+				prm->q.rpt);
-+			prm->p.rpt--;
-+			/* waitting more report */
-+			rm_state_goto(prm, RM_ST_WAIT_MEAS);
-+			break;
-+		}
-+		/* we are done */
-+		rm_state_goto(prm, RM_ST_END);
-+		break;
-+	case RM_EV_cancel:
-+		rm_state_goto(prm, RM_ST_END);
-+		break;
-+	case RM_EV_state_out:
-+		rm_cancel_clock(prm);
-+		break;
-+	default:
-+		break;
-+	}
-+	return _SUCCESS;
-+}
-+
-+static int rm_state_end(struct rm_obj *prm, enum RM_EV_ID evid)
-+{
-+	switch (evid) {
-+	case RM_EV_state_in:
-+		_rm_post_event(prm->psta->padapter, prm->rmid, RM_EV_state_out);
-+		break;
-+
-+	case RM_EV_cancel:
-+	case RM_EV_state_out:
-+	default:
-+		rm_free_rmobj(prm);
-+		break;
-+	}
-+	return _SUCCESS;
-+}
-+
-+struct fsm_state rm_fsm[] = {
-+	{"RM_ST_IDLE",		rm_state_idle},
-+	{"RM_ST_DO_MEAS",	rm_state_do_meas},
-+	{"RM_ST_WAIT_MEAS", 	rm_state_wait_meas},
-+	{"RM_ST_SEND_REPORT", 	rm_state_send_report},
-+	{"RM_ST_RECV_REPORT", 	rm_state_recv_report},
-+	{"RM_ST_END", 		rm_state_end}
-+};
-+
-+char *rm_state_name(enum RM_STATE state)
-+{
-+	return rm_fsm[state].name;
-+}
-+
-+char *rm_event_name(enum RM_EV_ID evid)
-+{
-+	switch(evid) {
-+	case RM_EV_state_in:
-+		return "RM_EV_state_in";
-+	case RM_EV_busy_timer_expire:
-+		return "RM_EV_busy_timer_expire";
-+	case RM_EV_delay_timer_expire:
-+		return "RM_EV_delay_timer_expire";
-+	case RM_EV_meas_timer_expire:
-+		return "RM_EV_meas_timer_expire";
-+	case RM_EV_repeat_delay_expire:
-+		return "RM_EV_repeat_delay_expire";
-+	case RM_EV_retry_timer_expire:
-+		return "RM_EV_retry_timer_expire";
-+	case RM_EV_request_timer_expire:
-+		return "RM_EV_request_timer_expire";
-+	case RM_EV_wait_report:
-+		return "RM_EV_wait_report";
-+	case RM_EV_start_meas:
-+		return "RM_EV_start_meas";
-+	case RM_EV_survey_done:
-+		return "RM_EV_survey_done";
-+	case RM_EV_recv_rep:
-+		return "RM_EV_recv_report";
-+	case RM_EV_cancel:
-+		return "RM_EV_cancel";
-+	case RM_EV_state_out:
-+		return "RM_EV_state_out";
-+	case RM_EV_max:
-+		return "RM_EV_max";
-+	default:
-+		return "RM_EV_unknown";
-+	}
-+	return "UNKNOWN";
-+}
-+
-+static void rm_state_initial(struct rm_obj *prm)
-+{
-+	prm->state = RM_ST_IDLE;
-+
-+	RTW_INFO("\n");
-+	RTW_INFO("RM: rmid=%x %-18s -> %s\n",prm->rmid,
-+		"new measurement", rm_fsm[prm->state].name);
-+
-+	rm_post_event(prm->psta->padapter, prm->rmid, RM_EV_state_in);
-+}
-+
-+static void rm_state_run(struct rm_obj *prm, enum RM_EV_ID evid)
-+{
-+	RTW_INFO("RM: rmid=%x %-18s    %s\n",prm->rmid,
-+		rm_fsm[prm->state].name,rm_event_name(evid));
-+
-+	rm_fsm[prm->state].fsm_func(prm, evid);
-+}
-+
-+static void rm_state_goto(struct rm_obj *prm, enum RM_STATE rm_state)
-+{
-+	if (prm->state == rm_state)
-+		return;
-+
-+	rm_state_run(prm, RM_EV_state_out);
-+
-+	RTW_INFO("\n");
-+	RTW_INFO("RM: rmid=%x %-18s -> %s\n",prm->rmid,
-+		rm_fsm[prm->state].name, rm_fsm[rm_state].name);
-+
-+	prm->state = rm_state;
-+	rm_state_run(prm, RM_EV_state_in);
-+}
-+#endif /* CONFIG_RTW_80211K */
-diff --git a/drivers/staging/rtl8723cs/core/rtw_rm_util.c b/drivers/staging/rtl8723cs/core/rtw_rm_util.c
-new file mode 100644
-index 000000000000..b0c24287bb08
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_rm_util.c
-@@ -0,0 +1,501 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+#ifdef CONFIG_RTW_80211K
-+#include "rtw_rm_fsm.h"
-+#include "rtw_rm_util.h"
-+
-+/* 802.11-2012 Table E-1 Operationg classes in United States */
-+static RT_OPERATING_CLASS RTW_OP_CLASS_US[] = {
-+	/* 0, OP_CLASS_NULL */	{  0,  0, {}},
-+	/* 1, OP_CLASS_1 */	{115,  4, {36, 40, 44, 48}},
-+	/* 2, OP_CLASS_2 */	{118,  4, {52, 56, 60, 64}},
-+	/* 3, OP_CLASS_3 */	{124,  4, {149, 153, 157, 161}},
-+	/* 4, OP_CLASS_4 */	{121, 11, {100, 104, 108, 112, 116, 120, 124,
-+						128, 132, 136, 140}},
-+	/* 5, OP_CLASS_5 */	{125,  5, {149, 153, 157, 161, 165}},
-+	/* 6, OP_CLASS_12 */	{ 81, 11, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}}
-+};
-+
-+u8 rm_get_ch_set(
-+	struct rtw_ieee80211_channel *pch_set, u8 op_class, u8 ch_num)
-+{
-+	int i,j,sz;
-+	u8 ch_amount = 0;
-+
-+
-+	sz = sizeof(RTW_OP_CLASS_US)/sizeof(struct _RT_OPERATING_CLASS);
-+
-+	if (ch_num != 0) {
-+		pch_set[0].hw_value = ch_num;
-+		ch_amount = 1;
-+		RTW_INFO("RM: meas_ch->hw_value = %u\n", pch_set->hw_value);
-+		goto done;
-+	}
-+
-+	for (i = 0; i < sz; i++) {
-+
-+		if (RTW_OP_CLASS_US[i].global_op_class == op_class) {
-+
-+			for (j = 0; j < RTW_OP_CLASS_US[i].Len; j++) {
-+				pch_set[j].hw_value =
-+					RTW_OP_CLASS_US[i].Channel[j];
-+				RTW_INFO("RM: meas_ch[%d].hw_value = %u\n",
-+					j, pch_set[j].hw_value);
-+			}
-+			ch_amount = RTW_OP_CLASS_US[i].Len;
-+			break;
-+		}
-+	}
-+done:
-+	return ch_amount;
-+}
-+
-+u8 rm_get_ch_set_from_bcn_req_opt(
-+	struct rtw_ieee80211_channel *pch_set, struct bcn_req_opt *opt)
-+{
-+	int i,j,k,sz;
-+	struct _RT_OPERATING_CLASS *ap_ch_rpt;
-+	u8 ch_amount = 0;
-+
-+	k = 0;
-+	for (i = 0; i < opt->ap_ch_rpt_num; i++) {
-+		if (opt->ap_ch_rpt[i] == NULL)
-+			break;
-+		ap_ch_rpt = opt->ap_ch_rpt[i];
-+		for (j = 0; j < ap_ch_rpt->Len; j++) {
-+			pch_set[k].hw_value =
-+				ap_ch_rpt->Channel[j];
-+			RTW_INFO("RM: meas_ch[%d].hw_value = %u\n",
-+				j, pch_set[k].hw_value);
-+			k++;
-+		}
-+	}
-+	return k;
-+}
-+
-+u8 rm_get_oper_class_via_ch(u8 ch)
-+{
-+	int i,j,sz;
-+
-+
-+	sz = sizeof(RTW_OP_CLASS_US)/sizeof(struct _RT_OPERATING_CLASS);
-+
-+	for (i = 0; i < sz; i++) {
-+		for (j = 0; j < RTW_OP_CLASS_US[i].Len; j++) {
-+			if ( ch == RTW_OP_CLASS_US[i].Channel[j]) {
-+				RTW_INFO("RM: ch %u in oper_calss %u\n",
-+					ch, RTW_OP_CLASS_US[i].global_op_class);
-+				return RTW_OP_CLASS_US[i].global_op_class;
-+				break;
-+			}
-+		}
-+	}
-+	return 0;
-+}
-+
-+int is_wildcard_bssid(u8 *bssid)
-+{
-+	int i;
-+	u8 val8 = 0xff;
-+
-+
-+	for (i=0;i<6;i++)
-+		val8 &= bssid[i];
-+
-+	if (val8 == 0xff)
-+		return _SUCCESS;
-+	return _FALSE;
-+}
-+
-+u8 translate_dbm_to_rcpi(s8 SignalPower)
-+{
-+	/* RCPI = Int{(Power in dBm + 110)*2} for 0dBm > Power > -110dBm
-+	 *    0	: power <= -110.0 dBm
-+	 *    1	: power =  -109.5 dBm
-+	 *    2	: power =  -109.0 dBm
-+	 */
-+	return (SignalPower + 110)*2;
-+}
-+
-+u8 translate_percentage_to_rcpi(u32 SignalStrengthIndex)
-+{
-+	/* Translate to dBm (x=y-100) */
-+	return translate_dbm_to_rcpi(SignalStrengthIndex - 100);
-+}
-+
-+u8 rm_get_bcn_rcpi(struct rm_obj *prm, struct wlan_network *pnetwork)
-+{
-+	return translate_percentage_to_rcpi(
-+		pnetwork->network.PhyInfo.SignalStrength);
-+}
-+
-+u8 rm_get_frame_rsni(struct rm_obj *prm, union recv_frame *pframe)
-+{
-+	int i;
-+	u8 val8, snr, rx_num;
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(prm->psta->padapter);
-+
-+	if (IS_CCK_RATE((hw_rate_to_m_rate(pframe->u.hdr.attrib.data_rate))))
-+		val8 = 255;
-+	else {
-+		snr = rx_num = 0;
-+		for (i = 0; i < hal_spec->rf_reg_path_num; i++) {
-+			if (GET_HAL_RX_PATH_BMP(prm->psta->padapter) & BIT(i)) {
-+				snr += pframe->u.hdr.attrib.phy_info.rx_snr[i];
-+				rx_num++;
-+			}
-+		}
-+		snr = snr / rx_num;
-+		val8 = (u8)(snr + 10)*2;
-+	}
-+	return val8;
-+}
-+
-+u8 rm_get_bcn_rsni(struct rm_obj *prm, struct wlan_network *pnetwork)
-+{
-+	int i;
-+	u8 val8, snr, rx_num;
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(prm->psta->padapter);
-+
-+	if (pnetwork->network.PhyInfo.is_cck_rate) {
-+		/* current HW doesn't have CCK RSNI */
-+		/* 255 indicates RSNI is unavailable */
-+		val8 = 255;
-+	} else {
-+		snr = rx_num = 0;
-+		for (i = 0; i < hal_spec->rf_reg_path_num; i++) {
-+			if (GET_HAL_RX_PATH_BMP(prm->psta->padapter) & BIT(i)) {
-+				snr += pnetwork->network.PhyInfo.rx_snr[i];
-+				rx_num++;
-+			}
-+		}
-+		snr = snr / rx_num;
-+		val8 = (u8)(snr + 10)*2;
-+	}
-+	return val8;
-+}
-+
-+/* output: pwr (unit dBm) */
-+int rm_get_tx_power(PADAPTER adapter, enum rf_path path, enum MGN_RATE rate, s8 *pwr)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	int tx_num, band, bw, ch, n, rs;
-+	u8 base;
-+	s8 limt_offset = 127; /* max value of s8 */
-+	s8 rate_offset;
-+	s8 powr_offset;
-+	int rate_pos;
-+
-+
-+	band = hal_data->current_band_type;
-+	bw = hal_data->current_channel_bw;
-+	ch = hal_data->current_channel;
-+
-+	if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
-+		return -1;
-+
-+	if (HAL_IsLegalChannel(adapter, ch) == _FALSE) {
-+		RTW_INFO("Illegal channel!!\n");
-+		return -2;
-+	}
-+
-+	*pwr = phy_get_tx_power_final_absolute_value(adapter, path, rate, bw, ch);
-+
-+	return 0;
-+}
-+
-+int rm_get_rx_sensitivity(PADAPTER adapter, enum channel_width bw, enum MGN_RATE rate, s8 *pwr)
-+{
-+	s8 rx_sensitivity = -110;
-+
-+	switch(rate) {
-+	case MGN_1M:
-+		rx_sensitivity= -101;
-+		break;
-+	case MGN_2M:
-+		rx_sensitivity= -98;
-+		break;
-+	case MGN_5_5M:
-+		rx_sensitivity= -92;
-+		break;
-+	case MGN_11M:
-+		rx_sensitivity= -89;
-+		break;
-+	case MGN_6M:
-+	case MGN_9M:
-+	case MGN_12M:
-+		rx_sensitivity = -92;
-+		break;
-+	case MGN_18M:
-+		rx_sensitivity = -90;
-+		break;
-+	case MGN_24M:
-+		rx_sensitivity = -88;
-+		break;
-+	case MGN_36M:
-+		rx_sensitivity = -84;
-+		break;
-+	case MGN_48M:
-+		rx_sensitivity = -79;
-+		break;
-+	case MGN_54M:
-+		rx_sensitivity = -78;
-+		break;
-+
-+	case MGN_MCS0:
-+	case MGN_MCS8:
-+	case MGN_MCS16:
-+	case MGN_MCS24:
-+	case MGN_VHT1SS_MCS0:
-+	case MGN_VHT2SS_MCS0:
-+	case MGN_VHT3SS_MCS0:
-+	case MGN_VHT4SS_MCS0:
-+		/* BW20 BPSK 1/2 */
-+		rx_sensitivity = -82;
-+		break;
-+
-+	case MGN_MCS1:
-+	case MGN_MCS9:
-+	case MGN_MCS17:
-+	case MGN_MCS25:
-+	case MGN_VHT1SS_MCS1:
-+	case MGN_VHT2SS_MCS1:
-+	case MGN_VHT3SS_MCS1:
-+	case MGN_VHT4SS_MCS1:
-+		/* BW20 QPSK 1/2 */
-+		rx_sensitivity = -79;
-+		break;
-+
-+	case MGN_MCS2:
-+	case MGN_MCS10:
-+	case MGN_MCS18:
-+	case MGN_MCS26:
-+	case MGN_VHT1SS_MCS2:
-+	case MGN_VHT2SS_MCS2:
-+	case MGN_VHT3SS_MCS2:
-+	case MGN_VHT4SS_MCS2:
-+		/* BW20 QPSK 3/4 */
-+		rx_sensitivity = -77;
-+		break;
-+
-+	case MGN_MCS3:
-+	case MGN_MCS11:
-+	case MGN_MCS19:
-+	case MGN_MCS27:
-+	case MGN_VHT1SS_MCS3:
-+	case MGN_VHT2SS_MCS3:
-+	case MGN_VHT3SS_MCS3:
-+	case MGN_VHT4SS_MCS3:
-+		/* BW20 16-QAM 1/2 */
-+		rx_sensitivity = -74;
-+		break;
-+
-+	case MGN_MCS4:
-+	case MGN_MCS12:
-+	case MGN_MCS20:
-+	case MGN_MCS28:
-+	case MGN_VHT1SS_MCS4:
-+	case MGN_VHT2SS_MCS4:
-+	case MGN_VHT3SS_MCS4:
-+	case MGN_VHT4SS_MCS4:
-+		/* BW20 16-QAM 3/4 */
-+		rx_sensitivity = -70;
-+		break;
-+
-+	case MGN_MCS5:
-+	case MGN_MCS13:
-+	case MGN_MCS21:
-+	case MGN_MCS29:
-+	case MGN_VHT1SS_MCS5:
-+	case MGN_VHT2SS_MCS5:
-+	case MGN_VHT3SS_MCS5:
-+	case MGN_VHT4SS_MCS5:
-+		/* BW20 64-QAM 2/3 */
-+		rx_sensitivity = -66;
-+		break;
-+
-+	case MGN_MCS6:
-+	case MGN_MCS14:
-+	case MGN_MCS22:
-+	case MGN_MCS30:
-+	case MGN_VHT1SS_MCS6:
-+	case MGN_VHT2SS_MCS6:
-+	case MGN_VHT3SS_MCS6:
-+	case MGN_VHT4SS_MCS6:
-+		/* BW20 64-QAM 3/4 */
-+		rx_sensitivity = -65;
-+		break;
-+
-+	case MGN_MCS7:
-+	case MGN_MCS15:
-+	case MGN_MCS23:
-+	case MGN_MCS31:
-+	case MGN_VHT1SS_MCS7:
-+	case MGN_VHT2SS_MCS7:
-+	case MGN_VHT3SS_MCS7:
-+	case MGN_VHT4SS_MCS7:
-+		/* BW20 64-QAM 5/6 */
-+		rx_sensitivity = -64;
-+		break;
-+
-+	case MGN_VHT1SS_MCS8:
-+	case MGN_VHT2SS_MCS8:
-+	case MGN_VHT3SS_MCS8:
-+	case MGN_VHT4SS_MCS8:
-+		/* BW20 256-QAM 3/4 */
-+		rx_sensitivity = -59;
-+		break;
-+
-+	case MGN_VHT1SS_MCS9:
-+	case MGN_VHT2SS_MCS9:
-+	case MGN_VHT3SS_MCS9:
-+	case MGN_VHT4SS_MCS9:
-+		/* BW20 256-QAM 5/6 */
-+		rx_sensitivity = -57;
-+		break;
-+
-+	default:
-+		return -1;
-+		break;
-+
-+	}
-+
-+	switch(bw) {
-+	case CHANNEL_WIDTH_20:
-+		break;
-+	case CHANNEL_WIDTH_40:
-+		rx_sensitivity -= 3;
-+		break;
-+	case CHANNEL_WIDTH_80:
-+		rx_sensitivity -= 6;
-+		break;
-+	case CHANNEL_WIDTH_160:
-+		rx_sensitivity -= 9;
-+		break;
-+	case CHANNEL_WIDTH_5:
-+	case CHANNEL_WIDTH_10:
-+	case CHANNEL_WIDTH_80_80:
-+	default:
-+		return -1;
-+		break;
-+	}
-+	*pwr = rx_sensitivity;
-+
-+	return 0;
-+}
-+
-+/* output: path_a max tx power in dBm */
-+int rm_get_path_a_max_tx_power(_adapter *adapter, s8 *path_a)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	int path, tx_num, band, bw, ch, n, rs;
-+	u8 rate_num;
-+	s8 max_pwr[RF_PATH_MAX], pwr;
-+
-+
-+	band = hal_data->current_band_type;
-+	bw = hal_data->current_channel_bw;
-+	ch = hal_data->current_channel;
-+
-+	for (path = 0; path < RF_PATH_MAX; path++) {
-+		if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
-+			break;
-+
-+		max_pwr[path] = -127; /* min value of s8 */
-+#if (RM_MORE_DBG_MSG)
-+		RTW_INFO("RM: [%s][%c]\n", band_str(band), rf_path_char(path));
-+#endif
-+		for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
-+			tx_num = rate_section_to_tx_num(rs);
-+
-+			if (tx_num >= hal_spec->tx_nss_num)
-+				continue;
-+
-+			if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
-+				continue;
-+
-+			if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
-+				continue;
-+
-+			rate_num = rate_section_rate_num(rs);
-+
-+			/* get power by rate in db */
-+			for (n = rate_num - 1; n >= 0; n--) {
-+				pwr = phy_get_tx_power_final_absolute_value(adapter, path, rates_by_sections[rs].rates[n], bw, ch);
-+				max_pwr[path] = MAX(max_pwr[path], pwr);
-+#if (RM_MORE_DBG_MSG)
-+				RTW_INFO("RM: %9s = %2d\n",
-+					MGN_RATE_STR(rates_by_sections[rs].rates[n]), pwr);
-+#endif
-+			}
-+		}
-+	}
-+#if (RM_MORE_DBG_MSG)
-+	RTW_INFO("RM: path_a max_pwr=%ddBm\n", max_pwr[0]);
-+#endif
-+	*path_a = max_pwr[0];
-+	return 0;
-+}
-+
-+u8 rm_gen_dialog_token(_adapter *padapter)
-+{
-+	struct rm_priv *prmpriv = &(padapter->rmpriv);
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
-+
-+	do {
-+		pmlmeinfo->dialogToken++;
-+	} while (pmlmeinfo->dialogToken == 0);
-+
-+	return pmlmeinfo->dialogToken;
-+}
-+
-+u8 rm_gen_meas_token(_adapter *padapter)
-+{
-+	struct rm_priv *prmpriv = &(padapter->rmpriv);
-+
-+	do {
-+		prmpriv->meas_token++;
-+	} while (prmpriv->meas_token == 0);
-+
-+	return prmpriv->meas_token;
-+}
-+
-+u32 rm_gen_rmid(_adapter *padapter, struct rm_obj *prm, u8 role)
-+{
-+	u32 rmid;
-+
-+	if (prm->psta == NULL)
-+		goto err;
-+
-+	if (prm->q.diag_token == 0)
-+		goto err;
-+
-+	rmid = prm->psta->cmn.aid << 16
-+		| prm->q.diag_token << 8
-+		| role;
-+
-+	return rmid;
-+err:
-+	RTW_ERR("RM: unable to gen rmid\n");
-+	return 0;
-+}
-+
-+#endif /* CONFIG_RTW_80211K */
-diff --git a/drivers/staging/rtl8723cs/core/rtw_roch.c b/drivers/staging/rtl8723cs/core/rtw_roch.c
-new file mode 100644
-index 000000000000..4be863192a65
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_roch.c
-@@ -0,0 +1,591 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2020 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+u8 rtw_roch_stay_in_cur_chan(_adapter *padapter)
-+{
-+	int i;
-+	_adapter *iface;
-+	struct mlme_priv *pmlmepriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	u8 rst = _FALSE;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface) {
-+			pmlmepriv = &iface->mlmepriv;
-+
-+			if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS | WIFI_UNDER_KEY_HANDSHAKE) == _TRUE) {
-+				RTW_INFO(ADPT_FMT"- WIFI_UNDER_LINKING |WIFI_UNDER_WPS | WIFI_UNDER_KEY_HANDSHAKE (mlme state:0x%x)\n",
-+						ADPT_ARG(iface), get_fwstate(&iface->mlmepriv));
-+				rst = _TRUE;
-+				break;
-+			}
-+			#ifdef CONFIG_AP_MODE
-+			if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {
-+				if (rtw_ap_sta_states_check(iface) == _TRUE) {
-+					rst = _TRUE;
-+					break;
-+				}
-+			}
-+			#endif
-+		}
-+	}
-+
-+	return rst;
-+}
-+
-+static int rtw_ro_ch_handler(_adapter *adapter, u8 *buf)
-+{
-+	int ret = H2C_SUCCESS;
-+	struct rtw_roch_parm *roch_parm = (struct rtw_roch_parm *)buf;
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
-+	struct roch_info *prochinfo = &adapter->rochinfo;
-+#ifdef CONFIG_CONCURRENT_MODE
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+#endif
-+	u8 ready_on_channel = _FALSE;
-+	u8 remain_ch;
-+	unsigned int duration;
-+
-+	_enter_critical_mutex(&pwdev_priv->roch_mutex, NULL);
-+
-+	if (rtw_cfg80211_get_is_roch(adapter) != _TRUE)
-+		goto exit;
-+
-+	remain_ch = (u8)ieee80211_frequency_to_channel(roch_parm->ch.center_freq);
-+	duration = roch_parm->duration;
-+
-+	RTW_INFO(FUNC_ADPT_FMT" ch:%u duration:%d, cookie:0x%llx\n"
-+		, FUNC_ADPT_ARG(adapter), remain_ch, roch_parm->duration, roch_parm->cookie);
-+
-+	if (roch_parm->wdev && roch_parm->cookie) {
-+		if (prochinfo->ro_ch_wdev != roch_parm->wdev) {
-+			RTW_WARN(FUNC_ADPT_FMT" ongoing wdev:%p, wdev:%p\n"
-+				, FUNC_ADPT_ARG(adapter), prochinfo->ro_ch_wdev, roch_parm->wdev);
-+			rtw_warn_on(1);
-+		}
-+
-+		if (prochinfo->remain_on_ch_cookie != roch_parm->cookie) {
-+			RTW_WARN(FUNC_ADPT_FMT" ongoing cookie:0x%llx, cookie:0x%llx\n"
-+				, FUNC_ADPT_ARG(adapter), prochinfo->remain_on_ch_cookie, roch_parm->cookie);
-+			rtw_warn_on(1);
-+		}
-+	}
-+
-+	if (rtw_roch_stay_in_cur_chan(adapter) == _TRUE) {
-+		remain_ch = rtw_mi_get_union_chan(adapter);
-+		RTW_INFO(FUNC_ADPT_FMT" stay in union ch:%d\n", FUNC_ADPT_ARG(adapter), remain_ch);
-+	}
-+
-+	#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_check_status(adapter, MI_LINKED) && (0 != rtw_mi_get_union_chan(adapter))) {
-+		if ((remain_ch != rtw_mi_get_union_chan(adapter)) && !check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE)) {
-+			if (remain_ch != pmlmeext->cur_channel
-+				#ifdef RTW_ROCH_BACK_OP
-+				|| ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1
-+				#endif
-+			) {
-+				rtw_leave_opch(adapter);
-+
-+				#ifdef RTW_ROCH_BACK_OP
-+				RTW_INFO("%s, set switch ch timer, duration=%d\n", __func__, prochinfo->max_away_dur);
-+				ATOMIC_SET(&pwdev_priv->switch_ch_to, 0);
-+				/* remain_ch is not same as union channel. duration is max_away_dur to
-+				 * back to AP's channel.
-+				 */
-+				_set_timer(&prochinfo->ap_roch_ch_switch_timer, prochinfo->max_away_dur);
-+				#endif
-+			}
-+		}
-+		ready_on_channel = _TRUE;
-+	} else
-+	#endif /* CONFIG_CONCURRENT_MODE */
-+	{
-+		if (remain_ch != rtw_get_oper_ch(adapter))
-+			ready_on_channel = _TRUE;
-+	}
-+
-+	if (ready_on_channel == _TRUE) {
-+		#ifndef RTW_SINGLE_WIPHY
-+		if (!check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE))
-+		#endif
-+		{
-+			#ifdef CONFIG_CONCURRENT_MODE
-+			if (rtw_get_oper_ch(adapter) != remain_ch)
-+			#endif
-+			{
-+				/* if (!padapter->mlmepriv.LinkDetectInfo.bBusyTraffic) */
-+				set_channel_bwmode(adapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+			}
-+		}
-+	}
-+
-+	#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_ScanNotify(adapter, _TRUE);
-+	#endif
-+
-+	RTW_INFO("%s, set ro ch timer, duration=%d\n", __func__, duration);
-+	_set_timer(&prochinfo->remain_on_ch_timer, duration);
-+
-+exit:
-+	_exit_critical_mutex(&pwdev_priv->roch_mutex, NULL);
-+
-+	return ret;
-+}
-+
-+static int rtw_cancel_ro_ch_handler(_adapter *padapter, u8 *buf)
-+{
-+	int ret = H2C_SUCCESS;
-+	struct rtw_roch_parm *roch_parm = (struct rtw_roch_parm *)buf;
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+	struct roch_info *prochinfo = &padapter->rochinfo;
-+	struct wireless_dev *wdev;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
-+#endif
-+	u8 ch, bw, offset;
-+
-+	_enter_critical_mutex(&pwdev_priv->roch_mutex, NULL);
-+
-+	if (rtw_cfg80211_get_is_roch(padapter) != _TRUE)
-+		goto exit;
-+
-+	if (roch_parm->wdev && roch_parm->cookie) {
-+		if (prochinfo->ro_ch_wdev != roch_parm->wdev) {
-+			RTW_WARN(FUNC_ADPT_FMT" ongoing wdev:%p, wdev:%p\n"
-+				, FUNC_ADPT_ARG(padapter), prochinfo->ro_ch_wdev, roch_parm->wdev);
-+			rtw_warn_on(1);
-+		}
-+
-+		if (prochinfo->remain_on_ch_cookie != roch_parm->cookie) {
-+			RTW_WARN(FUNC_ADPT_FMT" ongoing cookie:0x%llx, cookie:0x%llx\n"
-+				, FUNC_ADPT_ARG(padapter), prochinfo->remain_on_ch_cookie, roch_parm->cookie);
-+			rtw_warn_on(1);
-+		}
-+	}
-+
-+#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE)
-+	_cancel_timer_ex(&prochinfo->ap_roch_ch_switch_timer);
-+	ATOMIC_SET(&pwdev_priv->switch_ch_to, 1);
-+#endif
-+
-+	if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {
-+		if (0)
-+			RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n",
-+				 FUNC_ADPT_ARG(padapter), ch, bw, offset);
-+#ifdef CONFIG_P2P
-+	} else if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->listen_channel) {
-+		ch = pwdinfo->listen_channel;
-+		bw = CHANNEL_WIDTH_20;
-+		offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		if (0)
-+			RTW_INFO(FUNC_ADPT_FMT" back to listen ch - ch:%u, bw:%u, offset:%u\n",
-+				 FUNC_ADPT_ARG(padapter), ch, bw, offset);
-+#endif
-+	} else {
-+		ch = prochinfo->restore_channel;
-+		bw = CHANNEL_WIDTH_20;
-+		offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		if (0)
-+			RTW_INFO(FUNC_ADPT_FMT" back to restore ch - ch:%u, bw:%u, offset:%u\n",
-+				 FUNC_ADPT_ARG(padapter), ch, bw, offset);
-+	}
-+
-+	set_channel_bwmode(padapter, ch, offset, bw);
-+	rtw_back_opch(padapter);
-+#ifdef CONFIG_P2P
-+	rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
-+#ifdef CONFIG_DEBUG_CFG80211
-+	RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
-+#endif
-+#endif
-+
-+	wdev = prochinfo->ro_ch_wdev;
-+
-+	rtw_cfg80211_set_is_roch(padapter, _FALSE);
-+	prochinfo->ro_ch_wdev = NULL;
-+	rtw_cfg80211_set_last_ro_ch_time(padapter);
-+
-+	rtw_cfg80211_remain_on_channel_expired(wdev
-+		, prochinfo->remain_on_ch_cookie
-+		, &prochinfo->remain_on_ch_channel
-+		, prochinfo->remain_on_ch_type, GFP_KERNEL);
-+
-+	RTW_INFO("cfg80211_remain_on_channel_expired cookie:0x%llx\n"
-+		, prochinfo->remain_on_ch_cookie);
-+
-+#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_ScanNotify(padapter, _FALSE);
-+#endif
-+
-+exit:
-+	_exit_critical_mutex(&pwdev_priv->roch_mutex, NULL);
-+
-+	return ret;
-+}
-+
-+static void rtw_ro_ch_timer_process(void *FunctionContext)
-+{
-+	_adapter *adapter = (_adapter *)FunctionContext;
-+
-+	rtw_cancel_roch_cmd(adapter, 0, NULL, 0);
-+}
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+#if (defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)) || defined(CONFIG_IOCTL_CFG80211)
-+s32 rtw_roch_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf)
-+{
-+	int ret = H2C_SUCCESS;
-+
-+	switch (intCmdType) {
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	case ROCH_RO_CH_WK:
-+		ret = rtw_ro_ch_handler(padapter, buf);
-+		break;
-+	case ROCH_CANCEL_RO_CH_WK:
-+		ret = rtw_cancel_ro_ch_handler(padapter, buf);
-+		break;
-+#endif
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	case ROCH_AP_ROCH_CH_SWITCH_PROCESS_WK:
-+		rtw_concurrent_handler(padapter);
-+		break;
-+#endif
-+
-+	default:
-+		rtw_warn_on(1);
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+static int get_roch_parm_size(struct rtw_roch_parm *roch_parm)
-+{
-+#ifdef CONFIG_IOCTL_CFG80211
-+	return (roch_parm ? sizeof(*roch_parm) : 0);
-+#else
-+	rtw_warn_on(roch_parm);
-+	return 0;
-+#endif
-+}
-+
-+u8 rtw_roch_wk_cmd(_adapter *padapter, int intCmdType, struct rtw_roch_parm *roch_parm, u8 flags)
-+{
-+	struct cmd_obj	*ph2c = NULL;
-+	struct drvextra_cmd_parm	*pdrvextra_cmd_parm = NULL;
-+	struct cmd_priv	*pcmdpriv = &padapter->cmdpriv;
-+	struct submit_ctx sctx;
-+	u8	res = _SUCCESS;
-+
-+	if (flags & RTW_CMDF_DIRECTLY) {
-+		/* no need to enqueue, do the cmd hdl directly and free cmd parameter */
-+		if (H2C_SUCCESS != rtw_roch_wk_hdl(padapter, intCmdType, (u8 *)roch_parm))
-+			res = _FAIL;
-+		goto free_parm;
-+	} else {
-+		ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+		if (!ph2c) {
-+			res = _FAIL;
-+			goto free_parm;
-+		}
-+
-+		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+		if (!pdrvextra_cmd_parm) {
-+			res = _FAIL;
-+			goto free_parm;
-+		}
-+
-+		pdrvextra_cmd_parm->ec_id = ROCH_WK_CID;
-+		pdrvextra_cmd_parm->type = intCmdType;
-+		pdrvextra_cmd_parm->size = get_roch_parm_size(roch_parm);
-+		pdrvextra_cmd_parm->pbuf = (u8 *)roch_parm;
-+
-+		init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+		if (flags & RTW_CMDF_WAIT_ACK) {
-+			ph2c->sctx = &sctx;
-+			rtw_sctx_init(&sctx, 10 * 1000);
-+		}
-+
-+		res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+		if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
-+			rtw_sctx_wait(&sctx, __func__);
-+			_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status == RTW_SCTX_SUBMITTED)
-+				ph2c->sctx = NULL;
-+			_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
-+			if (sctx.status != RTW_SCTX_DONE_SUCCESS)
-+				res = _FAIL;
-+		}
-+	}
-+
-+	return res;
-+
-+free_parm:
-+	if (roch_parm)
-+		rtw_mfree((u8 *)roch_parm, get_roch_parm_size(roch_parm));
-+	if (ph2c)
-+		rtw_mfree((u8 *)ph2c, sizeof(*ph2c));
-+
-+	return res;
-+}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+void rtw_ap_roch_ch_switch_timer_process(void *ctx)
-+{
-+	_adapter *adapter = (_adapter *)ctx;
-+#ifdef CONFIG_IOCTL_CFG80211
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	ATOMIC_SET(&pwdev_priv->switch_ch_to, 1);
-+#endif
-+
-+	rtw_roch_wk_cmd(adapter, ROCH_AP_ROCH_CH_SWITCH_PROCESS_WK, NULL, 0);
-+}
-+
-+static bool chk_need_stay_in_cur_chan(_adapter *padapter)
-+{
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
-+
-+	/* When CONFIG_FULL_CH_IN_P2P_HANDSHAKE is defined and the
-+	 * interface is in the P2P_STATE_GONEGO_OK state, do not let the
-+	 * interface switch to the listen channel, because the interface will
-+	 * switch to the OP channel after the GO negotiation is successful.
-+	 */
-+	if (padapter->registrypriv.full_ch_in_p2p_handshake == 1 && rtw_p2p_chk_state(pwdinfo , P2P_STATE_GONEGO_OK)) {
-+		RTW_INFO("%s, No linked interface now, but go nego ok, do not back to listen channel\n", __func__);
-+		return _TRUE;
-+	}
-+#endif
-+
-+	return _FALSE;
-+}
-+
-+static bool chk_driver_interface(_adapter *padapter, u8 driver_interface)
-+{
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
-+
-+	if (pwdinfo->driver_interface == driver_interface)
-+		return _TRUE;
-+#elif defined(CONFIG_IOCTL_CFG80211)
-+	if (driver_interface == DRIVER_CFG80211)
-+		return _TRUE;
-+#endif
-+
-+	return _FALSE;
-+}
-+
-+static u8 get_remain_ch(_adapter *padapter)
-+{
-+	struct roch_info *prochinfo = &padapter->rochinfo;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
-+#endif
-+	u8 remain_ch;
-+
-+#ifdef CONFIG_P2P
-+	remain_ch = pwdinfo->listen_channel;
-+#elif defined(CONFIG_IOCTL_CFG80211)
-+	if (chk_driver_interface(padapter, DRIVER_CFG80211))
-+		remain_ch = ieee80211_frequency_to_channel(prochinfo->remain_on_ch_channel.center_freq);
-+	else
-+		rtw_warn_on(1);
-+#endif
-+
-+	return remain_ch;
-+}
-+
-+void rtw_concurrent_handler(_adapter	*padapter)
-+{
-+#ifdef CONFIG_IOCTL_CFG80211
-+	struct rtw_wdev_priv	*pwdev_priv = adapter_wdev_data(padapter);
-+#endif
-+	struct dvobj_priv	*pdvobj = adapter_to_dvobj(padapter);
-+	struct roch_info	*prochinfo = &padapter->rochinfo;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
-+	u8			val8;
-+#endif
-+	u8			remain_ch = get_remain_ch(padapter);
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (chk_driver_interface(padapter, DRIVER_CFG80211)
-+		&& !rtw_cfg80211_get_is_roch(padapter))
-+		return;
-+#endif
-+
-+	if (rtw_mi_check_status(padapter, MI_LINKED)) {
-+		u8 union_ch = rtw_mi_get_union_chan(padapter);
-+		u8 union_bw = rtw_mi_get_union_bw(padapter);
-+		u8 union_offset = rtw_mi_get_union_offset(padapter);
-+		unsigned int duration;
-+
-+	#ifdef CONFIG_P2P
-+		pwdinfo->operating_channel = union_ch;
-+	#endif
-+
-+		if (chk_driver_interface(padapter, DRIVER_CFG80211)) {
-+	#ifdef CONFIG_IOCTL_CFG80211
-+			_enter_critical_mutex(&pwdev_priv->roch_mutex, NULL);
-+
-+			if (rtw_get_oper_ch(padapter) != union_ch) {
-+				/* Current channel is not AP's channel - switching to AP's channel */
-+				RTW_INFO("%s, switch ch back to union=%u,%u, %u\n"
-+					, __func__, union_ch, union_bw, union_offset);
-+				set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
-+				rtw_back_opch(padapter);
-+
-+				/* Now, the driver stays on AP's channel. We should stay on AP's
-+				 * channel for min_home_dur (duration) and next switch channel is
-+				 * listen channel.
-+				 */
-+				duration = prochinfo->min_home_dur;
-+			} else {
-+				/* Current channel is AP's channel - switching to listen channel */
-+				RTW_INFO("%s, switch ch to roch=%u\n"
-+					, __func__, remain_ch);
-+				rtw_leave_opch(padapter);
-+				set_channel_bwmode(padapter,
-+						remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+
-+				/* Now, the driver stays on listen channel. We should stay on listen
-+				 * channel for max_away_dur (duration) and next switch channel is AP's
-+				 * channel.
-+				 */
-+				duration = prochinfo->max_away_dur;
-+			}
-+
-+			/* set channel switch timer */
-+			ATOMIC_SET(&pwdev_priv->switch_ch_to, 0);
-+			_set_timer(&prochinfo->ap_roch_ch_switch_timer, duration);
-+			RTW_INFO("%s, set switch ch timer, duration=%d\n", __func__, duration);
-+
-+			_exit_critical_mutex(&pwdev_priv->roch_mutex, NULL);
-+	#endif
-+		}
-+	#ifdef CONFIG_P2P
-+		else if (chk_driver_interface(padapter, DRIVER_WEXT)) {
-+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {
-+				/*	Now, the driver stays on the AP's channel. */
-+				/*	If the pwdinfo->ext_listen_period = 0, that means the P2P listen state is not available on listen channel. */
-+				if (pwdinfo->ext_listen_period > 0) {
-+					RTW_INFO("[%s] P2P_STATE_IDLE, ext_listen_period = %d\n", __FUNCTION__, pwdinfo->ext_listen_period);
-+
-+					if (union_ch != pwdinfo->listen_channel) {
-+						rtw_leave_opch(padapter);
-+						set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+					}
-+
-+					rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
-+
-+					if (!rtw_mi_check_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) {
-+						val8 = 1;
-+						rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+					}
-+					/*	Todo: To check the value of pwdinfo->ext_listen_period is equal to 0 or not. */
-+					_set_timer(&prochinfo->ap_roch_ch_switch_timer, pwdinfo->ext_listen_period);
-+				}
-+
-+			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) ||
-+				rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL) ||
-+				(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _FALSE) ||
-+				rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ)) {
-+				/*	Now, the driver is in the listen state of P2P mode. */
-+				RTW_INFO("[%s] P2P_STATE_IDLE, ext_listen_interval = %d\n", __FUNCTION__, pwdinfo->ext_listen_interval);
-+
-+				/*	Commented by Albert 2012/11/01 */
-+				/*	If the AP's channel is the same as the listen channel, we should still be in the listen state */
-+				/*	Other P2P device is still able to find this device out even this device is in the AP's channel. */
-+				/*	So, configure this device to be able to receive the probe request frame and set it to listen state. */
-+				if (union_ch != pwdinfo->listen_channel) {
-+
-+					set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
-+					if (!rtw_mi_check_status(padapter, MI_AP_MODE)) {
-+						val8 = 0;
-+						rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+					}
-+					rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE);
-+					rtw_back_opch(padapter);
-+				}
-+
-+				/*	Todo: To check the value of pwdinfo->ext_listen_interval is equal to 0 or not. */
-+				_set_timer(&prochinfo->ap_roch_ch_switch_timer, pwdinfo->ext_listen_interval);
-+
-+			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) {
-+				/*	The driver had finished the P2P handshake successfully. */
-+				val8 = 0;
-+				rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+				set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
-+				rtw_back_opch(padapter);
-+
-+			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) {
-+				val8 = 1;
-+				set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+				rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+				issue_probereq_p2p(padapter, NULL);
-+				_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
-+			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _TRUE) {
-+				val8 = 1;
-+				set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+				rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+				issue_probereq_p2p(padapter, NULL);
-+				_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
-+			} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ) && pwdinfo->invitereq_info.benable == _TRUE) {
-+				/*
-+				val8 = 1;
-+				set_channel_bwmode(padapter, , HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+				rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+				issue_probereq_p2p(padapter, NULL);
-+				_set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT );
-+				*/
-+			}
-+		}
-+	#endif /* CONFIG_P2P */
-+	} else if (!chk_need_stay_in_cur_chan(padapter)) {
-+		set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+	}
-+}
-+#endif  /* CONFIG_CONCURRENT_MODE */
-+
-+void rtw_init_roch_info(_adapter *padapter)
-+{
-+	struct roch_info *prochinfo = &padapter->rochinfo;
-+
-+	_rtw_memset(prochinfo, 0x00, sizeof(struct roch_info));
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	rtw_init_timer(&prochinfo->ap_roch_ch_switch_timer, padapter, rtw_ap_roch_ch_switch_timer_process, padapter);
-+#ifdef CONFIG_IOCTL_CFG80211
-+	prochinfo->min_home_dur = 1500; 		/* min duration for traffic, home_time */
-+	prochinfo->max_away_dur = 250;		/* max acceptable away duration, home_away_time */
-+#endif
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	rtw_init_timer(&prochinfo->remain_on_ch_timer, padapter, rtw_ro_ch_timer_process, padapter);
-+#endif
-+}
-+#endif /* (defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)) || defined(CONFIG_IOCTL_CFG80211) */
-\ No newline at end of file
-diff --git a/drivers/staging/rtl8723cs/core/rtw_rson.c b/drivers/staging/rtl8723cs/core/rtw_rson.c
-new file mode 100644
-index 000000000000..dba8fb73bdbc
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_rson.c
-@@ -0,0 +1,592 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
-+ *
-+ *
-+ ******************************************************************************/
-+#define _RTW_RSON_C_
-+
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+
-+/********	Custommize Part	***********************/
-+
-+unsigned char	RTW_RSON_OUI[] = {0xFA, 0xFA, 0xFA};
-+#define RSON_SCORE_DIFF_TH				8
-+
-+/*
-+	Calculate the corresponding score.
-+*/
-+inline u8 rtw_cal_rson_score(struct rtw_rson_struct *cand_rson_data, NDIS_802_11_RSSI  Rssi)
-+{
-+	if ((cand_rson_data->hopcnt == RTW_RSON_HC_NOTREADY)
-+		|| (cand_rson_data->connectible == RTW_RSON_DENYCONNECT))
-+		return RTW_RSON_SCORE_NOTCNNT;
-+
-+	return RTW_RSON_SCORE_MAX - (cand_rson_data->hopcnt * 10) + (Rssi/10);
-+}
-+
-+/*************************************************/
-+
-+
-+static u8 rtw_rson_block_bssid_idx = 0;
-+u8 rtw_rson_block_bssid[10][6] = {
-+			/*{0x02, 0xE0, 0x4C, 0x07, 0xC3, 0xF6}*/
-+};
-+
-+/* fake root, regard a real AP as a SO root */
-+static u8 rtw_rson_root_bssid_idx = 0;
-+u8 rtw_rson_root_bssid[10][6] = {
-+			/*{0x1c, 0x5f, 0x2b, 0x5a, 0x60, 0x24}*/
-+};
-+
-+int is_match_bssid(u8 *mac, u8 bssid_array[][6], int num)
-+{
-+	int i;
-+
-+	for (i = 0; i < num; i++)
-+		if (_rtw_memcmp(mac, bssid_array[i], 6) == _TRUE)
-+			return _TRUE;
-+	return _FALSE;
-+}
-+
-+void init_rtw_rson_data(struct dvobj_priv *dvobj)
-+{
-+	/*Aries  todo.  if pdvobj->rson_data.ver == 1 */
-+	dvobj->rson_data.ver = RTW_RSON_VER;
-+	dvobj->rson_data.id = CONFIG_RTW_REPEATER_SON_ID;
-+#ifdef CONFIG_RTW_REPEATER_SON_ROOT
-+	dvobj->rson_data.hopcnt = RTW_RSON_HC_ROOT;
-+	dvobj->rson_data.connectible = RTW_RSON_ALLOWCONNECT;
-+#else
-+	dvobj->rson_data.hopcnt = RTW_RSON_HC_NOTREADY;
-+	dvobj->rson_data.connectible = RTW_RSON_DENYCONNECT;
-+#endif
-+	dvobj->rson_data.loading = 0;
-+	_rtw_memset(dvobj->rson_data.res, 0xAA, sizeof(dvobj->rson_data.res));
-+}
-+
-+void	rtw_rson_get_property_str(_adapter *padapter, char *rson_data_str)
-+{
-+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
-+
-+	sprintf(rson_data_str, "version : \t%d\nid : \t\t%08x\nhop count : \t%d\nconnectible : \t%s\nloading : \t%d\nreserve : \t%16ph\n",
-+		pdvobj->rson_data.ver,
-+		pdvobj->rson_data.id,
-+		pdvobj->rson_data.hopcnt,
-+		pdvobj->rson_data.connectible ? "connectable":"unconnectable",
-+		pdvobj->rson_data.loading,
-+		pdvobj->rson_data.res);
-+}
-+
-+int str2hexbuf(char *str, u8 *hexbuf, int len)
-+{
-+	u8 *p;
-+	int i, slen, idx = 0;
-+
-+	p = (unsigned char *)str;
-+	if ((*p != '0') || (*(p+1) != 'x'))
-+		return _FALSE;
-+	slen = strlen(str);
-+	if (slen > (len*2) + 2)
-+		return _FALSE;
-+	p += 2;
-+	for (i = 0 ; i < len; i++, idx = idx+2) {
-+		hexbuf[i] = key_2char2num(p[idx], p[idx + 1]);
-+		if (slen <= idx+2)
-+			break;
-+	}
-+	return _TRUE;
-+}
-+
-+int rtw_rson_set_property(_adapter *padapter, char *field, char *value)
-+{
-+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
-+	int num = 0;
-+
-+	if (_rtw_memcmp(field, (u8 *)"ver", 3) == _TRUE)
-+		pdvobj->rson_data.ver = rtw_atoi(value);
-+	else if (_rtw_memcmp(field, (u8 *)"id", 2) == _TRUE)
-+		num = sscanf(value, "%08x",   &(pdvobj->rson_data.id));
-+	else if (_rtw_memcmp(field, (u8 *)"hc", 2) == _TRUE)
-+		num = sscanf(value, "%hhu", &(pdvobj->rson_data.hopcnt));
-+	else if (_rtw_memcmp(field, (u8 *)"cnt", 3) == _TRUE)
-+		num = sscanf(value, "%hhu", &(pdvobj->rson_data.connectible));
-+	else if (_rtw_memcmp(field, (u8 *)"loading", 2) == _TRUE)
-+		num = sscanf(value, "%hhu", &(pdvobj->rson_data.loading));
-+	else if (_rtw_memcmp(field, (u8 *)"res", 2) == _TRUE) {
-+		str2hexbuf(value, pdvobj->rson_data.res, 16);
-+		return 1;
-+	} else
-+		return _FALSE;
-+	return num;
-+}
-+
-+/*
-+	return :	TRUE  -- competitor is taking advantage than condidate
-+			FALSE -- we should continue keeping candidate
-+*/
-+int rtw_rson_choose(struct wlan_network **candidate, struct wlan_network *competitor)
-+{
-+	s16 comp_score = 0, cand_score = 0;
-+	struct rtw_rson_struct rson_cand, rson_comp;
-+
-+	if (is_match_bssid(competitor->network.MacAddress, rtw_rson_block_bssid, rtw_rson_block_bssid_idx) == _TRUE)
-+		return _FALSE;
-+
-+	if ((competitor == NULL)
-+		|| (rtw_get_rson_struct(&(competitor->network), &rson_comp) != _TRUE)
-+		|| (rson_comp.id != CONFIG_RTW_REPEATER_SON_ID))
-+		return _FALSE;
-+
-+	comp_score = rtw_cal_rson_score(&rson_comp, competitor->network.Rssi);
-+	if (comp_score == RTW_RSON_SCORE_NOTCNNT)
-+		return _FALSE;
-+
-+	if (*candidate == NULL)
-+		return _TRUE;
-+	if (rtw_get_rson_struct(&((*candidate)->network), &rson_cand) != _TRUE)
-+		return _FALSE;
-+
-+	cand_score = rtw_cal_rson_score(&rson_cand, (*candidate)->network.Rssi);
-+	RTW_INFO("%s: competitor_score=%d,  candidate_score=%d\n", __func__, comp_score, cand_score);
-+	if (comp_score - cand_score > RSON_SCORE_DIFF_TH)
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+inline u8 rtw_rson_varify_ie(u8 *p)
-+{
-+	u8 *ptr = NULL;
-+	u8 ver;
-+	u32 id;
-+	u8 hopcnt;
-+	u8 allcnnt;
-+
-+	ptr = p + 2 + sizeof(RTW_RSON_OUI);
-+	ver = *ptr;
-+
-+	/*	for (ver == 1)	*/
-+	if (ver != 1)
-+		return _FALSE;
-+
-+	return _TRUE;
-+}
-+
-+/*
-+	Parsing RTK self-organization vendor IE
-+*/
-+int rtw_get_rson_struct(WLAN_BSSID_EX *bssid, struct  rtw_rson_struct *rson_data)
-+{
-+	sint  limit = 0;
-+	u32	len;
-+	u8	*p;
-+
-+	if ((rson_data == NULL) || (bssid == NULL))
-+		return -EINVAL;
-+
-+	/*	Default		*/
-+	rson_data->id = 0;
-+	rson_data->ver = 0;
-+	rson_data->hopcnt = 0;
-+	rson_data->connectible = 0;
-+	rson_data->loading = 0;
-+	/*	fake root		*/
-+	if (is_match_bssid(bssid->MacAddress, rtw_rson_root_bssid, rtw_rson_root_bssid_idx) == _TRUE) {
-+		rson_data->id = CONFIG_RTW_REPEATER_SON_ID;
-+		rson_data->ver = RTW_RSON_VER;
-+		rson_data->hopcnt = RTW_RSON_HC_ROOT;
-+		rson_data->connectible = RTW_RSON_ALLOWCONNECT;
-+		rson_data->loading = 0;
-+		return _TRUE;
-+	}
-+	limit = bssid->IELength - _BEACON_IE_OFFSET_;
-+
-+	for (p = bssid->IEs + _BEACON_IE_OFFSET_; ; p += (len + 2)) {
-+		p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &len, limit);
-+		limit -= len;
-+		if ((p == NULL) || (len == 0))
-+			break;
-+		if (p && (_rtw_memcmp(p + 2, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)) == _TRUE)
-+			&& rtw_rson_varify_ie(p)) {
-+			p = p + 2 + sizeof(RTW_RSON_OUI);
-+			rson_data->ver = *p;
-+			/*	for (ver == 1)		*/
-+			p = p + 1;
-+			rson_data->id = le32_to_cpup((__le32 *)p);
-+			p = p + 4;
-+			rson_data->hopcnt = *p;
-+			p = p + 1;
-+			rson_data->connectible = *p;
-+			p = p + 1;
-+			rson_data->loading = *p;
-+
-+			return _TRUE;
-+		}
-+	}
-+	return -EBADMSG;
-+}
-+
-+u32 rtw_rson_append_ie(_adapter *padapter, unsigned char *pframe, u32 *len)
-+{
-+	u8 *ptr, *ori, ie_len = 0;
-+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+/*	static int iii = 0;*/
-+
-+	if ((!pdvobj) || (!pframe))
-+		return 0;
-+	ptr = ori = pframe;
-+	*ptr++ = _VENDOR_SPECIFIC_IE_;
-+	*ptr++ = ie_len = sizeof(RTW_RSON_OUI)+sizeof(pdvobj->rson_data);
-+	_rtw_memcpy(ptr, RTW_RSON_OUI, sizeof(RTW_RSON_OUI));
-+	ptr = ptr + sizeof(RTW_RSON_OUI);
-+	*ptr++ = pdvobj->rson_data.ver;
-+	*(s32 *)ptr = cpu_to_le32(pdvobj->rson_data.id);
-+	ptr = ptr + sizeof(pdvobj->rson_data.id);
-+	*ptr++ = pdvobj->rson_data.hopcnt;
-+	*ptr++ = pdvobj->rson_data.connectible;
-+	*ptr++ = pdvobj->rson_data.loading;
-+	_rtw_memcpy(ptr, pdvobj->rson_data.res, sizeof(pdvobj->rson_data.res));
-+	pframe = ptr;
-+/*
-+	iii = iii % 20;
-+	if (iii++ == 0)
-+		RTW_INFO("%s : RTW RSON IE : %20ph\n", __func__, ori);
-+*/
-+	*len += (ie_len+2);
-+	return ie_len;
-+
-+}
-+
-+void rtw_rson_do_disconnect(_adapter *padapter)
-+{
-+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+#ifndef CONFIG_RTW_REPEATER_SON_ROOT
-+	pdvobj->rson_data.ver = RTW_RSON_VER;
-+	pdvobj->rson_data.id = CONFIG_RTW_REPEATER_SON_ID;
-+	pdvobj->rson_data.hopcnt = RTW_RSON_HC_NOTREADY;
-+	pdvobj->rson_data.connectible = RTW_RSON_DENYCONNECT;
-+	pdvobj->rson_data.loading = 0;
-+	#ifdef CONFIG_AP_MODE
-+	rtw_mi_tx_beacon_hdl(padapter);
-+	#endif
-+#endif
-+}
-+
-+void rtw_rson_join_done(_adapter *padapter)
-+{
-+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
-+	WLAN_BSSID_EX	*cur_network = NULL;
-+	struct rtw_rson_struct  rson_data;
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+	if (!padapter->mlmepriv.cur_network_scanned)
-+		return;
-+	cur_network = &(padapter->mlmepriv.cur_network_scanned->network);
-+	if (rtw_get_rson_struct(cur_network, &rson_data) != _TRUE) {
-+		RTW_ERR("%s: try to join a improper network(%s)\n", __func__, cur_network->Ssid.Ssid);
-+		return;
-+	}
-+
-+#ifndef CONFIG_RTW_REPEATER_SON_ROOT
-+	/* update rson_data */
-+	pdvobj->rson_data.ver = RTW_RSON_VER;
-+	pdvobj->rson_data.id = rson_data.id;
-+	pdvobj->rson_data.hopcnt = rson_data.hopcnt + 1;
-+	pdvobj->rson_data.connectible = RTW_RSON_ALLOWCONNECT;
-+	pdvobj->rson_data.loading = 0;
-+	#ifdef CONFIG_AP_MODE
-+	rtw_mi_tx_beacon_hdl(padapter);
-+	#endif
-+#endif
-+}
-+
-+int rtw_rson_isupdate_roamcan(struct mlme_priv *mlme
-+	, struct wlan_network **candidate, struct wlan_network *competitor)
-+{
-+	struct rtw_rson_struct  rson_cand, rson_comp, rson_curr;
-+	s16 comp_score, cand_score, curr_score;
-+
-+	if ((competitor == NULL)
-+		|| (rtw_get_rson_struct(&(competitor->network), &rson_comp) != _TRUE)
-+		|| (rson_comp.id != CONFIG_RTW_REPEATER_SON_ID))
-+		return _FALSE;
-+
-+	if (is_match_bssid(competitor->network.MacAddress, rtw_rson_block_bssid, rtw_rson_block_bssid_idx) == _TRUE)
-+		return _FALSE;
-+
-+	if ((!mlme->cur_network_scanned)
-+		|| (mlme->cur_network_scanned == competitor)
-+		|| (rtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr)) != _TRUE)
-+		return _FALSE;
-+
-+	if (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms)
-+		return _FALSE;
-+
-+	comp_score = rtw_cal_rson_score(&rson_comp, competitor->network.Rssi);
-+	curr_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi);
-+	if (comp_score - curr_score < RSON_SCORE_DIFF_TH)
-+		return _FALSE;
-+
-+	if (*candidate == NULL)
-+		return _TRUE;
-+
-+	if (rtw_get_rson_struct(&((*candidate)->network), &rson_cand) != _TRUE) {
-+		RTW_ERR("%s : Unable to get rson_struct from candidate(%s -- " MAC_FMT")\n",
-+				__func__, (*candidate)->network.Ssid.Ssid, MAC_ARG((*candidate)->network.MacAddress));
-+		return _FALSE;
-+	}
-+	cand_score = rtw_cal_rson_score(&rson_cand, (*candidate)->network.Rssi);
-+	RTW_DBG("comp_score=%d , cand_score=%d , curr_score=%d\n", comp_score, cand_score, curr_score);
-+	if (cand_score < comp_score)
-+		return _TRUE;
-+
-+#if 0		/*	Handle 11R protocol	*/
-+#ifdef CONFIG_RTW_80211R
-+	if (rtw_chk_ft_flags(adapter, RTW_FT_SUPPORTED)) {
-+		ptmp = rtw_get_ie(&competitor->network.IEs[12], _MDIE_, &mdie_len, competitor->network.IELength-12);
-+		if (ptmp) {
-+			if (!_rtw_memcmp(&pftpriv->mdid, ptmp+2, 2))
-+				goto exit;
-+
-+			/*The candidate don't support over-the-DS*/
-+			if (rtw_chk_ft_flags(adapter, RTW_FT_STA_OVER_DS_SUPPORTED)) {
-+				if ((rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && !(*(ptmp+4) & 0x01)) ||
-+					(!rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && (*(ptmp+4) & 0x01))) {
-+					RTW_INFO("FT: ignore the candidate(" MAC_FMT ") for over-the-DS\n", MAC_ARG(competitor->network.MacAddress));
-+					rtw_clr_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED);
-+					goto exit;
-+				}
-+			}
-+		} else
-+			goto exit;
-+	}
-+#endif
-+#endif
-+	return _FALSE;
-+}
-+
-+void rtw_rson_show_survey_info(struct seq_file *m, _list *plist, _list *phead)
-+{
-+	struct wlan_network	*pnetwork = NULL;
-+	struct rtw_rson_struct  rson_data;
-+	s16 rson_score;
-+	u16  index = 0;
-+
-+	RTW_PRINT_SEL(m, "%5s  %-17s  %3s  %5s %14s  %10s  %-3s  %5s %32s\n", "index", "bssid", "ch", "id", "hop_cnt", "loading", "RSSI", "score", "ssid");
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+		if (!pnetwork)
-+			break;
-+
-+		_rtw_memset(&rson_data, 0, sizeof(rson_data));
-+		rson_score = 0;
-+		if (rtw_get_rson_struct(&(pnetwork->network), &rson_data) == _TRUE)
-+			rson_score = rtw_cal_rson_score(&rson_data, pnetwork->network.Rssi);
-+		RTW_PRINT_SEL(m, "%5d  "MAC_FMT" %3d  0x%08x %6d %10d   %6d %6d   %32s\n",
-+			      ++index,
-+			      MAC_ARG(pnetwork->network.MacAddress),
-+			      pnetwork->network.Configuration.DSConfig,
-+			      rson_data.id,
-+			      rson_data.hopcnt,
-+			      rson_data.loading,
-+			      (int)pnetwork->network.Rssi,
-+			      rson_score,
-+			      pnetwork->network.Ssid.Ssid);
-+		plist = get_next(plist);
-+		}
-+
-+}
-+
-+/*
-+	Description :	As a AP role, We need to check the qualify of associating STA.
-+					We also need to check if we are ready to be associated.
-+
-+	return :	TRUE  -- AP REJECT this STA
-+				FALSE -- AP ACCEPT this STA
-+*/
-+u8 rtw_rson_ap_check_sta(_adapter *padapter, u8 *pframe, uint pkt_len, unsigned short ie_offset)
-+{
-+	struct wlan_network	*pnetwork = NULL;
-+	struct rtw_rson_struct  rson_target;
-+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
-+	int len = 0;
-+	u8 ret = _FALSE;
-+	u8 *p;
-+
-+#ifndef CONFIG_RTW_REPEATER_SON_ROOT
-+	_rtw_memset(&rson_target, 0, sizeof(rson_target));
-+	for (p = pframe + WLAN_HDR_A3_LEN + ie_offset; ; p += (len + 2)) {
-+		p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &len, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
-+
-+		if ((p == NULL) || (len == 0))
-+			break;
-+
-+		if (p && (_rtw_memcmp(p + 2, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)) == _TRUE)
-+			&& rtw_rson_varify_ie(p)) {
-+			p = p + 2 + sizeof(RTW_RSON_OUI);
-+			rson_target.ver = *p;
-+			/*	for (ver == 1)		*/
-+			p = p + 1;
-+			rson_target.id = le32_to_cpup((__le32 *)p);
-+			p = p + 4;
-+			rson_target.hopcnt = *p;
-+			p = p + 1;
-+			rson_target.connectible = *p;
-+			p = p + 1;
-+			rson_target.loading = *p;
-+			break;
-+		}
-+	}
-+
-+	if (rson_target.id == 0)		/*	Normal STA, not a RSON STA	*/
-+		ret = _FALSE;
-+	else if (rson_target.id != pdvobj->rson_data.id) {
-+		ret = _TRUE;
-+		RTW_INFO("%s : Reject AssoReq because RSON ID not match, STA=%08x, our=%08x\n",
-+				__func__, rson_target.id, pdvobj->rson_data.id);
-+	} else if ((pdvobj->rson_data.hopcnt == RTW_RSON_HC_NOTREADY)
-+		|| (pdvobj->rson_data.connectible == RTW_RSON_DENYCONNECT)) {
-+		ret = _TRUE;
-+		RTW_INFO("%s : Reject AssoReq becuase our hopcnt=%d or connectbile=%d\n",
-+				__func__, pdvobj->rson_data.hopcnt, pdvobj->rson_data.connectible);
-+	}
-+#endif
-+	return ret;
-+}
-+
-+u8 rtw_rson_scan_wk_cmd(_adapter *padapter, int op)
-+{
-+	struct cmd_obj *ph2c;
-+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+	u8 *extra_cmd_buf;
-+	u8 res = _SUCCESS;
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	pdrvextra_cmd_parm->ec_id = RSON_SCAN_WK_CID;
-+	pdrvextra_cmd_parm->type = op;
-+	pdrvextra_cmd_parm->size = 0;
-+	pdrvextra_cmd_parm->pbuf = NULL;
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+
-+	res = rtw_enqueue_cmd(pcmdpriv, ph2c);
-+
-+exit:
-+	return res;
-+
-+}
-+
-+void rtw_rson_scan_cmd_hdl(_adapter *padapter, int op)
-+{
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	u8 val8;
-+
-+	if (mlmeext_chk_scan_state(pmlmeext, SCAN_DISABLE) != _TRUE)
-+		return;
-+	if (op == RSON_SCAN_PROCESS) {
-+		padapter->rtw_rson_scanstage = RSON_SCAN_PROCESS;
-+		val8 = 0x1e;
-+		rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &val8, _FALSE);
-+		val8 = 1;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+		issue_probereq(padapter, NULL, NULL);
-+		/*	stop rson_scan after 100ms	*/
-+		_set_timer(&(pmlmeext->rson_scan_timer), 100);
-+	} else if  (op == RSON_SCAN_DISABLE) {
-+		padapter->rtw_rson_scanstage = RSON_SCAN_DISABLE;
-+		val8 = 0;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
-+		val8 = 0xff;
-+		rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &val8, _FALSE);
-+		/*	report_surveydone_event(padapter);*/
-+		if (pmlmepriv->to_join == _TRUE) {
-+			if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) != _TRUE) {
-+				int s_ret;
-+
-+				set_fwstate(pmlmepriv, WIFI_UNDER_LINKING);
-+				pmlmepriv->to_join = _FALSE;
-+				s_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);
-+				if (s_ret == _SUCCESS)
-+					_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
-+				else if (s_ret == 2) {
-+					_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
-+					rtw_indicate_connect(padapter);
-+				} else {
-+					RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(padapter));
-+					if (rtw_to_roam(padapter) != 0) {
-+						if (rtw_dec_to_roam(padapter) == 0) {
-+							rtw_set_to_roam(padapter, 0);
-+							rtw_free_assoc_resources(padapter, _TRUE);
-+							rtw_indicate_disconnect(padapter, 0, _FALSE);
-+						} else
-+							pmlmepriv->to_join = _TRUE;
-+					} else
-+						rtw_indicate_disconnect(padapter, 0, _FALSE);
-+					_clr_fwstate_(pmlmepriv, WIFI_UNDER_LINKING);
-+				}
-+			}
-+		} else {
-+			if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) {
-+				if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
-+				    && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
-+					if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) {
-+#ifdef CONFIG_RTW_80211R
-+						if (rtw_chk_ft_flags(padapter, RTW_FT_OVER_DS_SUPPORTED)) {
-+							start_clnt_ft_action(adapter, (u8 *)pmlmepriv->roam_network->network.MacAddress);
-+						} else {
-+							/*wait a little time to retrieve packets buffered in the current ap while scan*/
-+							_set_timer(&pmlmeext->ft_roam_timer, 30);
-+						}
-+#else
-+						receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress
-+							, WLAN_REASON_ACTIVE_ROAM, _FALSE);
-+#endif
-+					}
-+				}
-+			}
-+			issue_action_BSSCoexistPacket(padapter);
-+			issue_action_BSSCoexistPacket(padapter);
-+			issue_action_BSSCoexistPacket(padapter);
-+		}
-+	} else {
-+		RTW_ERR("%s : improper parameter -- op = %d\n", __func__, op);
-+	}
-+}
-+
-+#endif	/* CONFIG_RTW_REPEATER_SON */
-diff --git a/drivers/staging/rtl8723cs/core/rtw_sdio.c b/drivers/staging/rtl8723cs/core/rtw_sdio.c
-new file mode 100644
-index 000000000000..cdadbaff7465
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_sdio.c
-@@ -0,0 +1,157 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_SDIO_C_
-+
-+#include <drv_types.h>		/* struct dvobj_priv and etc. */
-+#include <drv_types_sdio.h>	/* RTW_SDIO_ADDR_CMD52_GEN */
-+
-+/*
-+ * Description:
-+ *	Use SDIO cmd52 or cmd53 to read/write data
-+ *
-+ * Parameters:
-+ *	d	pointer of device object(struct dvobj_priv)
-+ *	addr	SDIO address, 17 bits
-+ *	buf	buffer for I/O
-+ *	len	length
-+ *	write	0:read, 1:write
-+ *	cmd52	0:cmd52, 1:cmd53
-+ *
-+ * Return:
-+ *	_SUCCESS	I/O ok.
-+ *	_FAIL		I/O fail.
-+ */
-+static u8 sdio_io(struct dvobj_priv *d, u32 addr, void *buf, size_t len, u8 write, u8 cmd52)
-+{
-+#ifdef DBG_SDIO
-+#if (DBG_SDIO >= 3)
-+	struct sdio_data *sdio;
-+#endif /* DBG_SDIO >= 3 */
-+#endif /* DBG_SDIO */
-+	u32 addr_drv;	/* address with driver defined bit */
-+	int err;
-+	u8 retry = 0;
-+	u8 stop_retry = _FALSE;	/* flag for stopping retry or not */
-+
-+
-+#ifdef DBG_SDIO
-+#if (DBG_SDIO >= 3)
-+	sdio = &d->intf_data;
-+#endif /* DBG_SDIO >= 3 */
-+#endif /* DBG_SDIO */
-+
-+	if (rtw_is_surprise_removed(dvobj_get_primary_adapter(d))) {
-+		RTW_ERR("%s: bSurpriseRemoved, skip %s 0x%05x, %zu bytes\n",
-+			__FUNCTION__, write?"write":"read", addr, len);
-+		return _FAIL;
-+	}
-+
-+	addr_drv = addr;
-+	if (cmd52)
-+		addr_drv = RTW_SDIO_ADDR_CMD52_GEN(addr_drv);
-+
-+	do {
-+		if (write)
-+			err = d->intf_ops->write(d, addr_drv, buf, len, 0);
-+		else
-+			err = d->intf_ops->read(d, addr_drv, buf, len, 0);
-+		if (!err) {
-+			if (retry) {
-+				RTW_INFO("%s: Retry %s OK! addr=0x%05x %zu bytes, retry=%u,%u\n",
-+					 __FUNCTION__, write?"write":"read",
-+					 addr, len, retry, ATOMIC_READ(&d->continual_io_error));
-+				RTW_INFO_DUMP("Data: ", buf, len);
-+			}
-+			rtw_reset_continual_io_error(d);
-+			break;
-+		}
-+		RTW_ERR("%s: %s FAIL! error(%d) addr=0x%05x %zu bytes, retry=%u,%u\n",
-+			__FUNCTION__, write?"write":"read", err, addr, len,
-+			retry, ATOMIC_READ(&d->continual_io_error));
-+
-+#ifdef DBG_SDIO
-+#if (DBG_SDIO >= 3)
-+		if (sdio->dbg_enable) {
-+			if (sdio->err_test && sdio->err_test_triggered)
-+				sdio->err_test = 0;
-+
-+			if (sdio->err_stop) {
-+				RTW_ERR("%s: I/O error! Set surprise remove flag ON!\n",
-+					__FUNCTION__);
-+				rtw_set_surprise_removed(dvobj_get_primary_adapter(d));
-+				return _FAIL;
-+			}
-+		}
-+#endif /* DBG_SDIO >= 3 */
-+#endif /* DBG_SDIO */
-+
-+		retry++;
-+		stop_retry = rtw_inc_and_chk_continual_io_error(d);
-+		if ((err == -1) || (stop_retry == _TRUE) || (retry > SD_IO_TRY_CNT)) {
-+			/* critical error, unrecoverable */
-+			RTW_ERR("%s: Fatal error! Set surprise remove flag ON! (retry=%u,%u)\n",
-+				__FUNCTION__, retry, ATOMIC_READ(&d->continual_io_error));
-+			rtw_set_surprise_removed(dvobj_get_primary_adapter(d));
-+			return _FAIL;
-+		}
-+
-+		/* WLAN IOREG or SDIO Local */
-+		if ((addr & 0x10000) || !(addr & 0xE000)) {
-+			RTW_WARN("%s: Retry %s addr=0x%05x %zu bytes, retry=%u,%u\n",
-+				 __FUNCTION__, write?"write":"read", addr, len,
-+				 retry, ATOMIC_READ(&d->continual_io_error));
-+			continue;
-+		}
-+		return _FAIL;
-+	} while (1);
-+
-+	return _SUCCESS;
-+}
-+
-+u8 rtw_sdio_read_cmd52(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
-+{
-+	return sdio_io(d, addr, buf, len, 0, 1);
-+}
-+
-+u8 rtw_sdio_read_cmd53(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
-+{
-+	return sdio_io(d, addr, buf, len, 0, 0);
-+}
-+
-+u8 rtw_sdio_write_cmd52(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
-+{
-+	return sdio_io(d, addr, buf, len, 1, 1);
-+}
-+
-+u8 rtw_sdio_write_cmd53(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
-+{
-+	return sdio_io(d, addr, buf, len, 1, 0);
-+}
-+
-+u8 rtw_sdio_f0_read(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
-+{
-+	int err;
-+	u8 ret;
-+
-+
-+	ret = _SUCCESS;
-+	addr = RTW_SDIO_ADDR_F0_GEN(addr);
-+
-+	err = d->intf_ops->read(d, addr, buf, len, 0);
-+	if (err)
-+		ret = _FAIL;
-+
-+	return ret;
-+}
-diff --git a/drivers/staging/rtl8723cs/core/rtw_security.c b/drivers/staging/rtl8723cs/core/rtw_security.c
-new file mode 100644
-index 000000000000..c7c013789d82
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_security.c
-@@ -0,0 +1,2872 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define  _RTW_SECURITY_C_
-+
-+#include <drv_types.h>
-+#include <rtw_swcrypto.h>
-+
-+static const char *_security_type_str[] = {
-+	"N/A",
-+	"WEP40",
-+	"TKIP",
-+	"TKIP_WM",
-+	"AES",
-+	"WEP104",
-+	"SMS4",
-+	"GCMP",
-+};
-+
-+static const char *_security_type_bip_str[] = {
-+	"BIP_CMAC_128",
-+	"BIP_GMAC_128",
-+	"BIP_GMAC_256",
-+	"BIP_CMAC_256",
-+};
-+
-+const char *security_type_str(u8 value)
-+{
-+#ifdef CONFIG_IEEE80211W
-+	if ((_BIP_MAX_ > value) && (value >= _BIP_CMAC_128_))
-+		return _security_type_bip_str[value & ~_SEC_TYPE_BIT_];
-+#endif
-+
-+	if (_CCMP_256_ == value)
-+		return "CCMP_256";
-+	if (_GCMP_256_ == value)
-+		return "GCMP_256";
-+
-+	if (_SEC_TYPE_MAX_ > value)
-+		return _security_type_str[value];
-+
-+	return NULL;
-+}
-+
-+#ifdef CONFIG_IEEE80211W
-+u32 security_type_bip_to_gmcs(enum security_type type)
-+{
-+	switch (type) {
-+	case _BIP_CMAC_128_:
-+		return WPA_CIPHER_BIP_CMAC_128;
-+	case _BIP_GMAC_128_:
-+		return WPA_CIPHER_BIP_GMAC_128;
-+	case _BIP_GMAC_256_:
-+		return WPA_CIPHER_BIP_GMAC_256;
-+	case _BIP_CMAC_256_:
-+		return WPA_CIPHER_BIP_CMAC_256;
-+	default:
-+		return 0;
-+	}
-+}
-+#endif
-+
-+#ifdef DBG_SW_SEC_CNT
-+#define WEP_SW_ENC_CNT_INC(sec, ra) do {\
-+	if (is_broadcast_mac_addr(ra)) \
-+		sec->wep_sw_enc_cnt_bc++; \
-+	else if (is_multicast_mac_addr(ra)) \
-+		sec->wep_sw_enc_cnt_mc++; \
-+	else \
-+		sec->wep_sw_enc_cnt_uc++; \
-+	} while (0)
-+
-+#define WEP_SW_DEC_CNT_INC(sec, ra) do {\
-+	if (is_broadcast_mac_addr(ra)) \
-+		sec->wep_sw_dec_cnt_bc++; \
-+	else if (is_multicast_mac_addr(ra)) \
-+		sec->wep_sw_dec_cnt_mc++; \
-+	else \
-+		sec->wep_sw_dec_cnt_uc++; \
-+	} while (0)
-+
-+#define TKIP_SW_ENC_CNT_INC(sec, ra) do {\
-+	if (is_broadcast_mac_addr(ra)) \
-+		sec->tkip_sw_enc_cnt_bc++; \
-+	else if (is_multicast_mac_addr(ra)) \
-+		sec->tkip_sw_enc_cnt_mc++; \
-+	else \
-+		sec->tkip_sw_enc_cnt_uc++; \
-+	} while (0)
-+
-+#define TKIP_SW_DEC_CNT_INC(sec, ra) do {\
-+	if (is_broadcast_mac_addr(ra)) \
-+		sec->tkip_sw_dec_cnt_bc++; \
-+	else if (is_multicast_mac_addr(ra)) \
-+		sec->tkip_sw_dec_cnt_mc++; \
-+	else \
-+		sec->tkip_sw_dec_cnt_uc++; \
-+	} while (0)
-+
-+#define AES_SW_ENC_CNT_INC(sec, ra) do {\
-+	if (is_broadcast_mac_addr(ra)) \
-+		sec->aes_sw_enc_cnt_bc++; \
-+	else if (is_multicast_mac_addr(ra)) \
-+		sec->aes_sw_enc_cnt_mc++; \
-+	else \
-+		sec->aes_sw_enc_cnt_uc++; \
-+	} while (0)
-+
-+#define AES_SW_DEC_CNT_INC(sec, ra) do {\
-+	if (is_broadcast_mac_addr(ra)) \
-+		sec->aes_sw_dec_cnt_bc++; \
-+	else if (is_multicast_mac_addr(ra)) \
-+		sec->aes_sw_dec_cnt_mc++; \
-+	else \
-+		sec->aes_sw_dec_cnt_uc++; \
-+	} while (0)
-+
-+#define GCMP_SW_ENC_CNT_INC(sec, ra) do {\
-+	if (is_broadcast_mac_addr(ra)) \
-+		sec->gcmp_sw_enc_cnt_bc++; \
-+	else if (is_multicast_mac_addr(ra)) \
-+		sec->gcmp_sw_enc_cnt_mc++; \
-+	else \
-+		sec->gcmp_sw_enc_cnt_uc++; \
-+	} while (0)
-+
-+#define GCMP_SW_DEC_CNT_INC(sec, ra) do {\
-+	if (is_broadcast_mac_addr(ra)) \
-+		sec->gcmp_sw_dec_cnt_bc++; \
-+	else if (is_multicast_mac_addr(ra)) \
-+		sec->gcmp_sw_dec_cnt_mc++; \
-+	else \
-+		sec->gcmp_sw_dec_cnt_uc++; \
-+	} while (0)
-+#else
-+#define WEP_SW_ENC_CNT_INC(sec, ra)
-+#define WEP_SW_DEC_CNT_INC(sec, ra)
-+#define TKIP_SW_ENC_CNT_INC(sec, ra)
-+#define TKIP_SW_DEC_CNT_INC(sec, ra)
-+#define AES_SW_ENC_CNT_INC(sec, ra)
-+#define AES_SW_DEC_CNT_INC(sec, ra)
-+#define GCMP_SW_ENC_CNT_INC(sec, ra)
-+#define GCMP_SW_DEC_CNT_INC(sec, ra)
-+#endif /* DBG_SW_SEC_CNT */
-+
-+/* *****WEP related***** */
-+
-+#define CRC32_POLY 0x04c11db7
-+
-+struct arc4context {
-+	u32 x;
-+	u32 y;
-+	u8 state[256];
-+};
-+
-+
-+static void arcfour_init(struct arc4context	*parc4ctx, u8 *key, u32	key_len)
-+{
-+	u32	t, u;
-+	u32	keyindex;
-+	u32	stateindex;
-+	u8 *state;
-+	u32	counter;
-+	state = parc4ctx->state;
-+	parc4ctx->x = 0;
-+	parc4ctx->y = 0;
-+	for (counter = 0; counter < 256; counter++)
-+		state[counter] = (u8)counter;
-+	keyindex = 0;
-+	stateindex = 0;
-+	for (counter = 0; counter < 256; counter++) {
-+		t = state[counter];
-+		stateindex = (stateindex + key[keyindex] + t) & 0xff;
-+		u = state[stateindex];
-+		state[stateindex] = (u8)t;
-+		state[counter] = (u8)u;
-+		if (++keyindex >= key_len)
-+			keyindex = 0;
-+	}
-+}
-+static u32 arcfour_byte(struct arc4context	*parc4ctx)
-+{
-+	u32 x;
-+	u32 y;
-+	u32 sx, sy;
-+	u8 *state;
-+	state = parc4ctx->state;
-+	x = (parc4ctx->x + 1) & 0xff;
-+	sx = state[x];
-+	y = (sx + parc4ctx->y) & 0xff;
-+	sy = state[y];
-+	parc4ctx->x = x;
-+	parc4ctx->y = y;
-+	state[y] = (u8)sx;
-+	state[x] = (u8)sy;
-+	return state[(sx + sy) & 0xff];
-+}
-+
-+
-+static void arcfour_encrypt(struct arc4context	*parc4ctx,
-+			    u8 *dest,
-+			    u8 *src,
-+			    u32 len)
-+{
-+	u32	i;
-+	for (i = 0; i < len; i++)
-+		dest[i] = src[i] ^ (unsigned char)arcfour_byte(parc4ctx);
-+}
-+
-+static sint bcrc32initialized = 0;
-+static u32 crc32_table[256];
-+
-+
-+static u8 crc32_reverseBit(u8 data)
-+{
-+	return (u8)((data << 7) & 0x80) | ((data << 5) & 0x40) | ((data << 3) & 0x20) | ((data << 1) & 0x10) | ((data >> 1) & 0x08) | ((data >> 3) & 0x04) | ((data >> 5) & 0x02) | ((
-+				data >> 7) & 0x01) ;
-+}
-+
-+static void crc32_init(void)
-+{
-+	if (bcrc32initialized == 1)
-+		goto exit;
-+	else {
-+		sint i, j;
-+		u32 c;
-+		u8 *p = (u8 *)&c, *p1;
-+		u8 k;
-+
-+		c = 0x12340000;
-+
-+		for (i = 0; i < 256; ++i) {
-+			k = crc32_reverseBit((u8)i);
-+			for (c = ((u32)k) << 24, j = 8; j > 0; --j)
-+				c = c & 0x80000000 ? (c << 1) ^ CRC32_POLY : (c << 1);
-+			p1 = (u8 *)&crc32_table[i];
-+
-+			p1[0] = crc32_reverseBit(p[3]);
-+			p1[1] = crc32_reverseBit(p[2]);
-+			p1[2] = crc32_reverseBit(p[1]);
-+			p1[3] = crc32_reverseBit(p[0]);
-+		}
-+		bcrc32initialized = 1;
-+	}
-+exit:
-+	return;
-+}
-+
-+static u32 getcrc32(u8 *buf, sint len)
-+{
-+	u8 *p;
-+	u32  crc;
-+	if (bcrc32initialized == 0)
-+		crc32_init();
-+
-+	crc = 0xffffffff;       /* preload shift register, per CRC-32 spec */
-+
-+	for (p = buf; len > 0; ++p, --len)
-+		crc = crc32_table[(crc ^ *p) & 0xff] ^ (crc >> 8);
-+	return ~crc;    /* transmit complement, per CRC-32 spec */
-+}
-+
-+
-+/*
-+	Need to consider the fragment  situation
-+*/
-+void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe)
-+{
-+	/* exclude ICV */
-+
-+	unsigned char	crc[4];
-+	struct arc4context	 mycontext;
-+
-+	sint	curfragnum, length;
-+	u32	keylength;
-+
-+	u8	*pframe, *payload, *iv;   /* ,*wepkey */
-+	u8	wepkey[16];
-+	u8   hw_hdr_offset = 0;
-+	struct	pkt_attrib	*pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
-+	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
-+	struct	xmit_priv		*pxmitpriv = &padapter->xmitpriv;
-+
-+
-+
-+	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
-+		return;
-+
-+#ifdef CONFIG_USB_TX_AGGREGATION
-+	hw_hdr_offset = TXDESC_SIZE +
-+		(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
-+#else
-+#ifdef CONFIG_TX_EARLY_MODE
-+	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
-+#else
-+	hw_hdr_offset = TXDESC_OFFSET;
-+#endif
-+#endif
-+
-+	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;
-+
-+	/* start to encrypt each fragment */
-+	if ((pattrib->encrypt == _WEP40_) || (pattrib->encrypt == _WEP104_)) {
-+		keylength = psecuritypriv->dot11DefKeylen[psecuritypriv->dot11PrivacyKeyIndex];
-+
-+		for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
-+			iv = pframe + pattrib->hdrlen;
-+			_rtw_memcpy(&wepkey[0], iv, 3);
-+			_rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0], keylength);
-+			payload = pframe + pattrib->iv_len + pattrib->hdrlen;
-+
-+			if ((curfragnum + 1) == pattrib->nr_frags) {
-+				/* the last fragment */
-+
-+				length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
-+
-+				*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length));
-+
-+				arcfour_init(&mycontext, wepkey, 3 + keylength);
-+				arcfour_encrypt(&mycontext, payload, payload, length);
-+				arcfour_encrypt(&mycontext, payload + length, crc, 4);
-+
-+			} else {
-+				length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ;
-+				*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length));
-+				arcfour_init(&mycontext, wepkey, 3 + keylength);
-+				arcfour_encrypt(&mycontext, payload, payload, length);
-+				arcfour_encrypt(&mycontext, payload + length, crc, 4);
-+
-+				pframe += pxmitpriv->frag_len;
-+				pframe = (u8 *)RND4((SIZE_PTR)(pframe));
-+
-+			}
-+
-+		}
-+
-+		WEP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);
-+	}
-+
-+
-+}
-+
-+void rtw_wep_decrypt(_adapter  *padapter, u8 *precvframe)
-+{
-+	/* exclude ICV */
-+	u8	crc[4];
-+	struct arc4context	 mycontext;
-+	sint	length;
-+	u32	keylength;
-+	u8	*pframe, *payload, *iv, wepkey[16];
-+	u8	 keyindex;
-+	struct	rx_pkt_attrib	*prxattrib = &(((union recv_frame *)precvframe)->u.hdr.attrib);
-+	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
-+
-+
-+	pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
-+
-+	/* start to decrypt recvframe */
-+	if ((prxattrib->encrypt == _WEP40_) || (prxattrib->encrypt == _WEP104_)) {
-+		iv = pframe + prxattrib->hdrlen;
-+		/* keyindex=(iv[3]&0x3); */
-+		keyindex = prxattrib->key_index;
-+		keylength = psecuritypriv->dot11DefKeylen[keyindex];
-+		_rtw_memcpy(&wepkey[0], iv, 3);
-+		/* _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0],keylength); */
-+		_rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[keyindex].skey[0], keylength);
-+		length = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len;
-+
-+		payload = pframe + prxattrib->iv_len + prxattrib->hdrlen;
-+
-+		/* decrypt payload include icv */
-+		arcfour_init(&mycontext, wepkey, 3 + keylength);
-+		arcfour_encrypt(&mycontext, payload, payload,  length);
-+
-+		/* calculate icv and compare the icv */
-+		*((u32 *)crc) = le32_to_cpu(getcrc32(payload, length - 4));
-+
-+
-+		WEP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
-+	}
-+
-+
-+	return;
-+
-+}
-+
-+/* 3		=====TKIP related===== */
-+
-+static u32 secmicgetuint32(u8 *p)
-+/* Convert from Byte[] to Us4Byte32 in a portable way */
-+{
-+	s32 i;
-+	u32 res = 0;
-+	for (i = 0; i < 4; i++)
-+		res |= ((u32)(*p++)) << (8 * i);
-+	return res;
-+}
-+
-+static void secmicputuint32(u8 *p, u32 val)
-+/* Convert from Us4Byte32 to Byte[] in a portable way */
-+{
-+	long i;
-+	for (i = 0; i < 4; i++) {
-+		*p++ = (u8)(val & 0xff);
-+		val >>= 8;
-+	}
-+}
-+
-+static void secmicclear(struct mic_data *pmicdata)
-+{
-+	/* Reset the state to the empty message. */
-+	pmicdata->L = pmicdata->K0;
-+	pmicdata->R = pmicdata->K1;
-+	pmicdata->nBytesInM = 0;
-+	pmicdata->M = 0;
-+}
-+
-+void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key)
-+{
-+	/* Set the key */
-+	pmicdata->K0 = secmicgetuint32(key);
-+	pmicdata->K1 = secmicgetuint32(key + 4);
-+	/* and reset the message */
-+	secmicclear(pmicdata);
-+}
-+
-+void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b)
-+{
-+	/* Append the byte to our word-sized buffer */
-+	pmicdata->M |= ((unsigned long)b) << (8 * pmicdata->nBytesInM);
-+	pmicdata->nBytesInM++;
-+	/* Process the word if it is full. */
-+	if (pmicdata->nBytesInM >= 4) {
-+		pmicdata->L ^= pmicdata->M;
-+		pmicdata->R ^= ROL32(pmicdata->L, 17);
-+		pmicdata->L += pmicdata->R;
-+		pmicdata->R ^= ((pmicdata->L & 0xff00ff00) >> 8) | ((pmicdata->L & 0x00ff00ff) << 8);
-+		pmicdata->L += pmicdata->R;
-+		pmicdata->R ^= ROL32(pmicdata->L, 3);
-+		pmicdata->L += pmicdata->R;
-+		pmicdata->R ^= ROR32(pmicdata->L, 2);
-+		pmicdata->L += pmicdata->R;
-+		/* Clear the buffer */
-+		pmicdata->M = 0;
-+		pmicdata->nBytesInM = 0;
-+	}
-+}
-+
-+void rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nbytes)
-+{
-+	/* This is simple */
-+	while (nbytes > 0) {
-+		rtw_secmicappendbyte(pmicdata, *src++);
-+		nbytes--;
-+	}
-+}
-+
-+void rtw_secgetmic(struct mic_data *pmicdata, u8 *dst)
-+{
-+	/* Append the minimum padding */
-+	rtw_secmicappendbyte(pmicdata, 0x5a);
-+	rtw_secmicappendbyte(pmicdata, 0);
-+	rtw_secmicappendbyte(pmicdata, 0);
-+	rtw_secmicappendbyte(pmicdata, 0);
-+	rtw_secmicappendbyte(pmicdata, 0);
-+	/* and then zeroes until the length is a multiple of 4 */
-+	while (pmicdata->nBytesInM != 0)
-+		rtw_secmicappendbyte(pmicdata, 0);
-+	/* The appendByte function has already computed the result. */
-+	secmicputuint32(dst, pmicdata->L);
-+	secmicputuint32(dst + 4, pmicdata->R);
-+	/* Reset to the empty message. */
-+	secmicclear(pmicdata);
-+}
-+
-+
-+void rtw_seccalctkipmic(u8 *key, u8 *header, u8 *data, u32 data_len, u8 *mic_code, u8 pri)
-+{
-+
-+	struct mic_data	micdata;
-+	u8 priority[4] = {0x0, 0x0, 0x0, 0x0};
-+	rtw_secmicsetkey(&micdata, key);
-+	priority[0] = pri;
-+
-+	/* Michael MIC pseudo header: DA, SA, 3 x 0, Priority */
-+	if (header[1] & 1) { /* ToDS==1 */
-+		rtw_secmicappend(&micdata, &header[16], 6);  /* DA */
-+		if (header[1] & 2) /* From Ds==1 */
-+			rtw_secmicappend(&micdata, &header[24], 6);
-+		else
-+			rtw_secmicappend(&micdata, &header[10], 6);
-+	} else {	/* ToDS==0 */
-+		rtw_secmicappend(&micdata, &header[4], 6);   /* DA */
-+		if (header[1] & 2) /* From Ds==1 */
-+			rtw_secmicappend(&micdata, &header[16], 6);
-+		else
-+			rtw_secmicappend(&micdata, &header[10], 6);
-+
-+	}
-+	rtw_secmicappend(&micdata, &priority[0], 4);
-+
-+
-+	rtw_secmicappend(&micdata, data, data_len);
-+
-+	rtw_secgetmic(&micdata, mic_code);
-+}
-+
-+
-+
-+
-+/* macros for extraction/creation of unsigned char/unsigned short values */
-+#define RotR1(v16)   ((((v16) >> 1) & 0x7FFF) ^ (((v16) & 1) << 15))
-+#define   Lo8(v16)   ((u8)((v16)       & 0x00FF))
-+#define   Hi8(v16)   ((u8)(((v16) >> 8) & 0x00FF))
-+#define  Lo16(v32)   ((u16)((v32)       & 0xFFFF))
-+#define  Hi16(v32)   ((u16)(((v32) >> 16) & 0xFFFF))
-+#define  Mk16(hi, lo) ((lo) ^ (((u16)(hi)) << 8))
-+
-+/* select the Nth 16-bit word of the temporal key unsigned char array TK[]  */
-+#define  TK16(N)     Mk16(tk[2*(N)+1], tk[2*(N)])
-+
-+/* S-box lookup: 16 bits --> 16 bits */
-+#define _S_(v16)     (Sbox1[0][Lo8(v16)] ^ Sbox1[1][Hi8(v16)])
-+
-+/* fixed algorithm "parameters" */
-+#define PHASE1_LOOP_CNT   8    /* this needs to be "big enough"     */
-+#define TA_SIZE           6    /*  48-bit transmitter address      */
-+#define TK_SIZE          16    /* 128-bit temporal key             */
-+#define P1K_SIZE         10    /*  80-bit Phase1 key               */
-+#define RC4_KEY_SIZE     16    /* 128-bit RC4KEY (104 bits unknown) */
-+
-+
-+/* 2-unsigned char by 2-unsigned char subset of the full AES S-box table */
-+static const unsigned short Sbox1[2][256] =      /* Sbox for hash (can be in ROM)    */
-+{ {
-+		0xC6A5, 0xF884, 0xEE99, 0xF68D, 0xFF0D, 0xD6BD, 0xDEB1, 0x9154,
-+		0x6050, 0x0203, 0xCEA9, 0x567D, 0xE719, 0xB562, 0x4DE6, 0xEC9A,
-+		0x8F45, 0x1F9D, 0x8940, 0xFA87, 0xEF15, 0xB2EB, 0x8EC9, 0xFB0B,
-+		0x41EC, 0xB367, 0x5FFD, 0x45EA, 0x23BF, 0x53F7, 0xE496, 0x9B5B,
-+		0x75C2, 0xE11C, 0x3DAE, 0x4C6A, 0x6C5A, 0x7E41, 0xF502, 0x834F,
-+		0x685C, 0x51F4, 0xD134, 0xF908, 0xE293, 0xAB73, 0x6253, 0x2A3F,
-+		0x080C, 0x9552, 0x4665, 0x9D5E, 0x3028, 0x37A1, 0x0A0F, 0x2FB5,
-+		0x0E09, 0x2436, 0x1B9B, 0xDF3D, 0xCD26, 0x4E69, 0x7FCD, 0xEA9F,
-+		0x121B, 0x1D9E, 0x5874, 0x342E, 0x362D, 0xDCB2, 0xB4EE, 0x5BFB,
-+		0xA4F6, 0x764D, 0xB761, 0x7DCE, 0x527B, 0xDD3E, 0x5E71, 0x1397,
-+		0xA6F5, 0xB968, 0x0000, 0xC12C, 0x4060, 0xE31F, 0x79C8, 0xB6ED,
-+		0xD4BE, 0x8D46, 0x67D9, 0x724B, 0x94DE, 0x98D4, 0xB0E8, 0x854A,
-+		0xBB6B, 0xC52A, 0x4FE5, 0xED16, 0x86C5, 0x9AD7, 0x6655, 0x1194,
-+		0x8ACF, 0xE910, 0x0406, 0xFE81, 0xA0F0, 0x7844, 0x25BA, 0x4BE3,
-+		0xA2F3, 0x5DFE, 0x80C0, 0x058A, 0x3FAD, 0x21BC, 0x7048, 0xF104,
-+		0x63DF, 0x77C1, 0xAF75, 0x4263, 0x2030, 0xE51A, 0xFD0E, 0xBF6D,
-+		0x814C, 0x1814, 0x2635, 0xC32F, 0xBEE1, 0x35A2, 0x88CC, 0x2E39,
-+		0x9357, 0x55F2, 0xFC82, 0x7A47, 0xC8AC, 0xBAE7, 0x322B, 0xE695,
-+		0xC0A0, 0x1998, 0x9ED1, 0xA37F, 0x4466, 0x547E, 0x3BAB, 0x0B83,
-+		0x8CCA, 0xC729, 0x6BD3, 0x283C, 0xA779, 0xBCE2, 0x161D, 0xAD76,
-+		0xDB3B, 0x6456, 0x744E, 0x141E, 0x92DB, 0x0C0A, 0x486C, 0xB8E4,
-+		0x9F5D, 0xBD6E, 0x43EF, 0xC4A6, 0x39A8, 0x31A4, 0xD337, 0xF28B,
-+		0xD532, 0x8B43, 0x6E59, 0xDAB7, 0x018C, 0xB164, 0x9CD2, 0x49E0,
-+		0xD8B4, 0xACFA, 0xF307, 0xCF25, 0xCAAF, 0xF48E, 0x47E9, 0x1018,
-+		0x6FD5, 0xF088, 0x4A6F, 0x5C72, 0x3824, 0x57F1, 0x73C7, 0x9751,
-+		0xCB23, 0xA17C, 0xE89C, 0x3E21, 0x96DD, 0x61DC, 0x0D86, 0x0F85,
-+		0xE090, 0x7C42, 0x71C4, 0xCCAA, 0x90D8, 0x0605, 0xF701, 0x1C12,
-+		0xC2A3, 0x6A5F, 0xAEF9, 0x69D0, 0x1791, 0x9958, 0x3A27, 0x27B9,
-+		0xD938, 0xEB13, 0x2BB3, 0x2233, 0xD2BB, 0xA970, 0x0789, 0x33A7,
-+		0x2DB6, 0x3C22, 0x1592, 0xC920, 0x8749, 0xAAFF, 0x5078, 0xA57A,
-+		0x038F, 0x59F8, 0x0980, 0x1A17, 0x65DA, 0xD731, 0x84C6, 0xD0B8,
-+		0x82C3, 0x29B0, 0x5A77, 0x1E11, 0x7BCB, 0xA8FC, 0x6DD6, 0x2C3A,
-+	},
-+
-+
-+	{  /* second half of table is unsigned char-reversed version of first! */
-+		0xA5C6, 0x84F8, 0x99EE, 0x8DF6, 0x0DFF, 0xBDD6, 0xB1DE, 0x5491,
-+		0x5060, 0x0302, 0xA9CE, 0x7D56, 0x19E7, 0x62B5, 0xE64D, 0x9AEC,
-+		0x458F, 0x9D1F, 0x4089, 0x87FA, 0x15EF, 0xEBB2, 0xC98E, 0x0BFB,
-+		0xEC41, 0x67B3, 0xFD5F, 0xEA45, 0xBF23, 0xF753, 0x96E4, 0x5B9B,
-+		0xC275, 0x1CE1, 0xAE3D, 0x6A4C, 0x5A6C, 0x417E, 0x02F5, 0x4F83,
-+		0x5C68, 0xF451, 0x34D1, 0x08F9, 0x93E2, 0x73AB, 0x5362, 0x3F2A,
-+		0x0C08, 0x5295, 0x6546, 0x5E9D, 0x2830, 0xA137, 0x0F0A, 0xB52F,
-+		0x090E, 0x3624, 0x9B1B, 0x3DDF, 0x26CD, 0x694E, 0xCD7F, 0x9FEA,
-+		0x1B12, 0x9E1D, 0x7458, 0x2E34, 0x2D36, 0xB2DC, 0xEEB4, 0xFB5B,
-+		0xF6A4, 0x4D76, 0x61B7, 0xCE7D, 0x7B52, 0x3EDD, 0x715E, 0x9713,
-+		0xF5A6, 0x68B9, 0x0000, 0x2CC1, 0x6040, 0x1FE3, 0xC879, 0xEDB6,
-+		0xBED4, 0x468D, 0xD967, 0x4B72, 0xDE94, 0xD498, 0xE8B0, 0x4A85,
-+		0x6BBB, 0x2AC5, 0xE54F, 0x16ED, 0xC586, 0xD79A, 0x5566, 0x9411,
-+		0xCF8A, 0x10E9, 0x0604, 0x81FE, 0xF0A0, 0x4478, 0xBA25, 0xE34B,
-+		0xF3A2, 0xFE5D, 0xC080, 0x8A05, 0xAD3F, 0xBC21, 0x4870, 0x04F1,
-+		0xDF63, 0xC177, 0x75AF, 0x6342, 0x3020, 0x1AE5, 0x0EFD, 0x6DBF,
-+		0x4C81, 0x1418, 0x3526, 0x2FC3, 0xE1BE, 0xA235, 0xCC88, 0x392E,
-+		0x5793, 0xF255, 0x82FC, 0x477A, 0xACC8, 0xE7BA, 0x2B32, 0x95E6,
-+		0xA0C0, 0x9819, 0xD19E, 0x7FA3, 0x6644, 0x7E54, 0xAB3B, 0x830B,
-+		0xCA8C, 0x29C7, 0xD36B, 0x3C28, 0x79A7, 0xE2BC, 0x1D16, 0x76AD,
-+		0x3BDB, 0x5664, 0x4E74, 0x1E14, 0xDB92, 0x0A0C, 0x6C48, 0xE4B8,
-+		0x5D9F, 0x6EBD, 0xEF43, 0xA6C4, 0xA839, 0xA431, 0x37D3, 0x8BF2,
-+		0x32D5, 0x438B, 0x596E, 0xB7DA, 0x8C01, 0x64B1, 0xD29C, 0xE049,
-+		0xB4D8, 0xFAAC, 0x07F3, 0x25CF, 0xAFCA, 0x8EF4, 0xE947, 0x1810,
-+		0xD56F, 0x88F0, 0x6F4A, 0x725C, 0x2438, 0xF157, 0xC773, 0x5197,
-+		0x23CB, 0x7CA1, 0x9CE8, 0x213E, 0xDD96, 0xDC61, 0x860D, 0x850F,
-+		0x90E0, 0x427C, 0xC471, 0xAACC, 0xD890, 0x0506, 0x01F7, 0x121C,
-+		0xA3C2, 0x5F6A, 0xF9AE, 0xD069, 0x9117, 0x5899, 0x273A, 0xB927,
-+		0x38D9, 0x13EB, 0xB32B, 0x3322, 0xBBD2, 0x70A9, 0x8907, 0xA733,
-+		0xB62D, 0x223C, 0x9215, 0x20C9, 0x4987, 0xFFAA, 0x7850, 0x7AA5,
-+		0x8F03, 0xF859, 0x8009, 0x171A, 0xDA65, 0x31D7, 0xC684, 0xB8D0,
-+		0xC382, 0xB029, 0x775A, 0x111E, 0xCB7B, 0xFCA8, 0xD66D, 0x3A2C,
-+	}
-+};
-+
-+/*
-+**********************************************************************
-+* Routine: Phase 1 -- generate P1K, given TA, TK, IV32
-+*
-+* Inputs:
-+*     tk[]      = temporal key                         [128 bits]
-+*     ta[]      = transmitter's MAC address            [ 48 bits]
-+*     iv32      = upper 32 bits of IV                  [ 32 bits]
-+* Output:
-+*     p1k[]     = Phase 1 key                          [ 80 bits]
-+*
-+* Note:
-+*     This function only needs to be called every 2**16 packets,
-+*     although in theory it could be called every packet.
-+*
-+**********************************************************************
-+*/
-+static void phase1(u16 *p1k, const u8 *tk, const u8 *ta, u32 iv32)
-+{
-+	sint  i;
-+	/* Initialize the 80 bits of P1K[] from IV32 and TA[0..5]    */
-+	p1k[0]      = Lo16(iv32);
-+	p1k[1]      = Hi16(iv32);
-+	p1k[2]      = Mk16(ta[1], ta[0]); /* use TA[] as little-endian */
-+	p1k[3]      = Mk16(ta[3], ta[2]);
-+	p1k[4]      = Mk16(ta[5], ta[4]);
-+
-+	/* Now compute an unbalanced Feistel cipher with 80-bit block */
-+	/* size on the 80-bit block P1K[], using the 128-bit key TK[] */
-+	for (i = 0; i < PHASE1_LOOP_CNT ; i++) {
-+		/* Each add operation here is mod 2**16 */
-+		p1k[0] += _S_(p1k[4] ^ TK16((i & 1) + 0));
-+		p1k[1] += _S_(p1k[0] ^ TK16((i & 1) + 2));
-+		p1k[2] += _S_(p1k[1] ^ TK16((i & 1) + 4));
-+		p1k[3] += _S_(p1k[2] ^ TK16((i & 1) + 6));
-+		p1k[4] += _S_(p1k[3] ^ TK16((i & 1) + 0));
-+		p1k[4] += (unsigned short)i;                     /* avoid "slide attacks" */
-+	}
-+}
-+
-+
-+/*
-+**********************************************************************
-+* Routine: Phase 2 -- generate RC4KEY, given TK, P1K, IV16
-+*
-+* Inputs:
-+*     tk[]      = Temporal key                         [128 bits]
-+*     p1k[]     = Phase 1 output key                   [ 80 bits]
-+*     iv16      = low 16 bits of IV counter            [ 16 bits]
-+* Output:
-+*     rc4key[]  = the key used to encrypt the packet   [128 bits]
-+*
-+* Note:
-+*     The value {TA,IV32,IV16} for Phase1/Phase2 must be unique
-+*     across all packets using the same key TK value. Then, for a
-+*     given value of TK[], this TKIP48 construction guarantees that
-+*     the final RC4KEY value is unique across all packets.
-+*
-+* Suggested implementation optimization: if PPK[] is "overlaid"
-+*     appropriately on RC4KEY[], there is no need for the final
-+*     for loop below that copies the PPK[] result into RC4KEY[].
-+*
-+**********************************************************************
-+*/
-+static void phase2(u8 *rc4key, const u8 *tk, const u16 *p1k, u16 iv16)
-+{
-+	sint  i;
-+	u16 PPK[6];                          /* temporary key for mixing   */
-+	/* Note: all adds in the PPK[] equations below are mod 2**16        */
-+	for (i = 0; i < 5; i++)
-+		PPK[i] = p1k[i];    /* first, copy P1K to PPK     */
-+	PPK[5]  =  p1k[4] + iv16;            /* next,  add in IV16         */
-+
-+	/* Bijective non-linear mixing of the 96 bits of PPK[0..5]          */
-+	PPK[0] +=    _S_(PPK[5] ^ TK16(0));   /* Mix key in each "round"     */
-+	PPK[1] +=    _S_(PPK[0] ^ TK16(1));
-+	PPK[2] +=    _S_(PPK[1] ^ TK16(2));
-+	PPK[3] +=    _S_(PPK[2] ^ TK16(3));
-+	PPK[4] +=    _S_(PPK[3] ^ TK16(4));
-+	PPK[5] +=    _S_(PPK[4] ^ TK16(5));   /* Total # S-box lookups == 6 */
-+
-+	/* Final sweep: bijective, "linear". Rotates kill LSB correlations   */
-+	PPK[0] +=  RotR1(PPK[5] ^ TK16(6));
-+	PPK[1] +=  RotR1(PPK[0] ^ TK16(7));   /* Use all of TK[] in Phase2  */
-+	PPK[2] +=  RotR1(PPK[1]);
-+	PPK[3] +=  RotR1(PPK[2]);
-+	PPK[4] +=  RotR1(PPK[3]);
-+	PPK[5] +=  RotR1(PPK[4]);
-+	/* Note: At this point, for a given key TK[0..15], the 96-bit output */
-+	/*       value PPK[0..5] is guaranteed to be unique, as a function  */
-+	/*       of the 96-bit "input" value   {TA,IV32,IV16}. That is, P1K  */
-+	/*       is now a keyed permutation of {TA,IV32,IV16}.              */
-+
-+	/* Set RC4KEY[0..3], which includes "cleartext" portion of RC4 key   */
-+	rc4key[0] = Hi8(iv16);                /* RC4KEY[0..2] is the WEP IV */
-+	rc4key[1] = (Hi8(iv16) | 0x20) & 0x7F; /* Help avoid weak (FMS) keys */
-+	rc4key[2] = Lo8(iv16);
-+	rc4key[3] = Lo8((PPK[5] ^ TK16(0)) >> 1);
-+
-+
-+	/* Copy 96 bits of PPK[0..5] to RC4KEY[4..15]  (little-endian)      */
-+	for (i = 0; i < 6; i++) {
-+		rc4key[4 + 2 * i] = Lo8(PPK[i]);
-+		rc4key[5 + 2 * i] = Hi8(PPK[i]);
-+	}
-+}
-+
-+
-+/* The hlen isn't include the IV */
-+u32	rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe)
-+{
-+	/* exclude ICV */
-+	u16	pnl;
-+	u32	pnh;
-+	u8	rc4key[16];
-+	u8   ttkey[16];
-+	u8	crc[4];
-+	u8   hw_hdr_offset = 0;
-+	struct arc4context mycontext;
-+	sint			curfragnum, length;
-+	u32	prwskeylen;
-+
-+	u8	*pframe, *payload, *iv, *prwskey;
-+	union pn48 dot11txpn;
-+	/* struct	sta_info		*stainfo; */
-+	struct	pkt_attrib	*pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
-+	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
-+	struct	xmit_priv		*pxmitpriv = &padapter->xmitpriv;
-+	u32	res = _SUCCESS;
-+
-+	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
-+		return _FAIL;
-+
-+#ifdef CONFIG_USB_TX_AGGREGATION
-+	hw_hdr_offset = TXDESC_SIZE +
-+		(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
-+#else
-+#ifdef CONFIG_TX_EARLY_MODE
-+	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
-+#else
-+	hw_hdr_offset = TXDESC_OFFSET;
-+#endif
-+#endif
-+
-+	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;
-+	/* 4 start to encrypt each fragment */
-+	if (pattrib->encrypt == _TKIP_) {
-+
-+		/*
-+				if(pattrib->psta)
-+				{
-+					stainfo = pattrib->psta;
-+				}
-+				else
-+				{
-+					RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
-+					stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );
-+				}
-+		*/
-+		/* if (stainfo!=NULL) */
-+		{
-+			/*
-+						if(!(stainfo->state &WIFI_ASOC_STATE))
-+						{
-+							RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, stainfo->state);
-+							return _FAIL;
-+						}
-+			*/
-+
-+			if (IS_MCAST(pattrib->ra))
-+				prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
-+			else {
-+				/* prwskey=&stainfo->dot118021x_UncstKey.skey[0]; */
-+				prwskey = pattrib->dot118021x_UncstKey.skey;
-+			}
-+
-+			prwskeylen = 16;
-+
-+			for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
-+				iv = pframe + pattrib->hdrlen;
-+				payload = pframe + pattrib->iv_len + pattrib->hdrlen;
-+
-+				GET_TKIP_PN(iv, dot11txpn);
-+
-+				pnl = (u16)(dot11txpn.val);
-+				pnh = (u32)(dot11txpn.val >> 16);
-+
-+				phase1((u16 *)&ttkey[0], prwskey, &pattrib->ta[0], pnh);
-+
-+				phase2(&rc4key[0], prwskey, (u16 *)&ttkey[0], pnl);
-+
-+				if ((curfragnum + 1) == pattrib->nr_frags) {	/* 4 the last fragment */
-+					length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
-+					*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); /* modified by Amy*/
-+
-+					arcfour_init(&mycontext, rc4key, 16);
-+					arcfour_encrypt(&mycontext, payload, payload, length);
-+					arcfour_encrypt(&mycontext, payload + length, crc, 4);
-+
-+				} else {
-+					length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ;
-+					*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); /* modified by Amy*/
-+					arcfour_init(&mycontext, rc4key, 16);
-+					arcfour_encrypt(&mycontext, payload, payload, length);
-+					arcfour_encrypt(&mycontext, payload + length, crc, 4);
-+
-+					pframe += pxmitpriv->frag_len;
-+					pframe = (u8 *)RND4((SIZE_PTR)(pframe));
-+
-+				}
-+			}
-+
-+			TKIP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);
-+		}
-+		/*
-+				else{
-+					RTW_INFO("%s, psta==NUL\n", __func__);
-+					res=_FAIL;
-+				}
-+		*/
-+
-+	}
-+	return res;
-+
-+}
-+
-+
-+/* The hlen isn't include the IV */
-+u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe)
-+{
-+	/* exclude ICV */
-+	u16 pnl;
-+	u32 pnh;
-+	u8   rc4key[16];
-+	u8   ttkey[16];
-+	u8	crc[4];
-+	struct arc4context mycontext;
-+	sint			length;
-+	u32	prwskeylen;
-+
-+	u8	*pframe, *payload, *iv, *prwskey;
-+	union pn48 dot11txpn;
-+	struct	sta_info		*stainfo;
-+	struct	rx_pkt_attrib	*prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
-+	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
-+	/*	struct	recv_priv		*precvpriv=&padapter->recvpriv; */
-+	u32		res = _SUCCESS;
-+
-+
-+	pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
-+
-+	/* 4 start to decrypt recvframe */
-+	if (prxattrib->encrypt == _TKIP_) {
-+
-+		stainfo = rtw_get_stainfo(&padapter->stapriv , &prxattrib->ta[0]);
-+		if (stainfo != NULL) {
-+
-+			if (IS_MCAST(prxattrib->ra)) {
-+				static systime start = 0;
-+				static u32 no_gkey_bc_cnt = 0;
-+				static u32 no_gkey_mc_cnt = 0;
-+
-+				if (psecuritypriv->binstallGrpkey == _FALSE) {
-+					res = _FAIL;
-+
-+					if (start == 0)
-+						start = rtw_get_current_time();
-+
-+					if (is_broadcast_mac_addr(prxattrib->ra))
-+						no_gkey_bc_cnt++;
-+					else
-+						no_gkey_mc_cnt++;
-+
-+					if (rtw_get_passing_time_ms(start) > 1000) {
-+						if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
-+							RTW_PRINT(FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
-+								FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
-+						}
-+						start = rtw_get_current_time();
-+						no_gkey_bc_cnt = 0;
-+						no_gkey_mc_cnt = 0;
-+					}
-+					goto exit;
-+				}
-+
-+				if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
-+					RTW_PRINT(FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
-+						FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
-+				}
-+				start = 0;
-+				no_gkey_bc_cnt = 0;
-+				no_gkey_mc_cnt = 0;
-+
-+				/* RTW_INFO("rx bc/mc packets, to perform sw rtw_tkip_decrypt\n"); */
-+				/* prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; */
-+				prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;
-+				prwskeylen = 16;
-+			} else {
-+				prwskey = &stainfo->dot118021x_UncstKey.skey[0];
-+				prwskeylen = 16;
-+			}
-+
-+			iv = pframe + prxattrib->hdrlen;
-+			payload = pframe + prxattrib->iv_len + prxattrib->hdrlen;
-+			length = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len;
-+
-+			GET_TKIP_PN(iv, dot11txpn);
-+
-+			pnl = (u16)(dot11txpn.val);
-+			pnh = (u32)(dot11txpn.val >> 16);
-+
-+			phase1((u16 *)&ttkey[0], prwskey, &prxattrib->ta[0], pnh);
-+			phase2(&rc4key[0], prwskey, (unsigned short *)&ttkey[0], pnl);
-+
-+			/* 4 decrypt payload include icv */
-+
-+			arcfour_init(&mycontext, rc4key, 16);
-+			arcfour_encrypt(&mycontext, payload, payload, length);
-+
-+			*((u32 *)crc) = le32_to_cpu(getcrc32(payload, length - 4));
-+
-+			if (crc[3] != payload[length - 1] || crc[2] != payload[length - 2] || crc[1] != payload[length - 3] || crc[0] != payload[length - 4]) {
-+				res = _FAIL;
-+			}
-+
-+			TKIP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
-+		} else {
-+			res = _FAIL;
-+		}
-+
-+	}
-+exit:
-+	return res;
-+
-+}
-+
-+
-+/* 3			=====AES related===== */
-+#if (NEW_CRYPTO == 0)
-+
-+#define MAX_MSG_SIZE	2048
-+/*****************************/
-+/******** SBOX Table *********/
-+/*****************************/
-+
-+static  u8 sbox_table[256] = {
-+	0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5,
-+	0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
-+	0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0,
-+	0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
-+	0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc,
-+	0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
-+	0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a,
-+	0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
-+	0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0,
-+	0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
-+	0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b,
-+	0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
-+	0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85,
-+	0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
-+	0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5,
-+	0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
-+	0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17,
-+	0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
-+	0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88,
-+	0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
-+	0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c,
-+	0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
-+	0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9,
-+	0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
-+	0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6,
-+	0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
-+	0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e,
-+	0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
-+	0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94,
-+	0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
-+	0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68,
-+	0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
-+};
-+
-+/*****************************/
-+/**** Function Prototypes ****/
-+/*****************************/
-+
-+static void bitwise_xor(u8 *ina, u8 *inb, u8 *out);
-+static void construct_mic_iv(
-+	u8 *mic_header1,
-+	sint qc_exists,
-+	sint a4_exists,
-+	u8 *mpdu,
-+	uint payload_length,
-+	u8 *pn_vector,
-+	uint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */
-+static void construct_mic_header1(
-+	u8 *mic_header1,
-+	sint header_length,
-+	u8 *mpdu,
-+	uint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */
-+static void construct_mic_header2(
-+	u8 *mic_header2,
-+	u8 *mpdu,
-+	sint a4_exists,
-+	sint qc_exists);
-+static void construct_ctr_preload(
-+	u8 *ctr_preload,
-+	sint a4_exists,
-+	sint qc_exists,
-+	u8 *mpdu,
-+	u8 *pn_vector,
-+	sint c,
-+	uint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */
-+static void xor_128(u8 *a, u8 *b, u8 *out);
-+static void xor_32(u8 *a, u8 *b, u8 *out);
-+static u8 sbox(u8 a);
-+static void next_key(u8 *key, sint round);
-+static void byte_sub(u8 *in, u8 *out);
-+static void shift_row(u8 *in, u8 *out);
-+static void mix_column(u8 *in, u8 *out);
-+static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext);
-+
-+
-+/****************************************/
-+/* aes128k128d()                       */
-+/* Performs a 128 bit AES encrypt with */
-+/* 128 bit data.                       */
-+/****************************************/
-+static void xor_128(u8 *a, u8 *b, u8 *out)
-+{
-+	sint i;
-+	for (i = 0; i < 16; i++)
-+		out[i] = a[i] ^ b[i];
-+}
-+
-+
-+static void xor_32(u8 *a, u8 *b, u8 *out)
-+{
-+	sint i;
-+	for (i = 0; i < 4; i++)
-+		out[i] = a[i] ^ b[i];
-+}
-+
-+
-+static u8 sbox(u8 a)
-+{
-+	return sbox_table[(sint)a];
-+}
-+
-+
-+static void next_key(u8 *key, sint round)
-+{
-+	u8 rcon;
-+	u8 sbox_key[4];
-+	u8 rcon_table[12] = {
-+		0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,
-+		0x1b, 0x36, 0x36, 0x36
-+	};
-+	sbox_key[0] = sbox(key[13]);
-+	sbox_key[1] = sbox(key[14]);
-+	sbox_key[2] = sbox(key[15]);
-+	sbox_key[3] = sbox(key[12]);
-+
-+	rcon = rcon_table[round];
-+
-+	xor_32(&key[0], sbox_key, &key[0]);
-+	key[0] = key[0] ^ rcon;
-+
-+	xor_32(&key[4], &key[0], &key[4]);
-+	xor_32(&key[8], &key[4], &key[8]);
-+	xor_32(&key[12], &key[8], &key[12]);
-+}
-+
-+
-+static void byte_sub(u8 *in, u8 *out)
-+{
-+	sint i;
-+	for (i = 0; i < 16; i++)
-+		out[i] = sbox(in[i]);
-+}
-+
-+
-+static void shift_row(u8 *in, u8 *out)
-+{
-+	out[0] =  in[0];
-+	out[1] =  in[5];
-+	out[2] =  in[10];
-+	out[3] =  in[15];
-+	out[4] =  in[4];
-+	out[5] =  in[9];
-+	out[6] =  in[14];
-+	out[7] =  in[3];
-+	out[8] =  in[8];
-+	out[9] =  in[13];
-+	out[10] = in[2];
-+	out[11] = in[7];
-+	out[12] = in[12];
-+	out[13] = in[1];
-+	out[14] = in[6];
-+	out[15] = in[11];
-+}
-+
-+
-+static void mix_column(u8 *in, u8 *out)
-+{
-+	sint i;
-+	u8 add1b[4];
-+	u8 add1bf7[4];
-+	u8 rotl[4];
-+	u8 swap_halfs[4];
-+	u8 andf7[4];
-+	u8 rotr[4];
-+	u8 temp[4];
-+	u8 tempb[4];
-+	for (i = 0 ; i < 4; i++) {
-+		if ((in[i] & 0x80) == 0x80)
-+			add1b[i] = 0x1b;
-+		else
-+			add1b[i] = 0x00;
-+	}
-+
-+	swap_halfs[0] = in[2];    /* Swap halfs */
-+	swap_halfs[1] = in[3];
-+	swap_halfs[2] = in[0];
-+	swap_halfs[3] = in[1];
-+
-+	rotl[0] = in[3];        /* Rotate left 8 bits */
-+	rotl[1] = in[0];
-+	rotl[2] = in[1];
-+	rotl[3] = in[2];
-+
-+	andf7[0] = in[0] & 0x7f;
-+	andf7[1] = in[1] & 0x7f;
-+	andf7[2] = in[2] & 0x7f;
-+	andf7[3] = in[3] & 0x7f;
-+
-+	for (i = 3; i > 0; i--) { /* logical shift left 1 bit */
-+		andf7[i] = andf7[i] << 1;
-+		if ((andf7[i - 1] & 0x80) == 0x80)
-+			andf7[i] = (andf7[i] | 0x01);
-+	}
-+	andf7[0] = andf7[0] << 1;
-+	andf7[0] = andf7[0] & 0xfe;
-+
-+	xor_32(add1b, andf7, add1bf7);
-+
-+	xor_32(in, add1bf7, rotr);
-+
-+	temp[0] = rotr[0];         /* Rotate right 8 bits */
-+	rotr[0] = rotr[1];
-+	rotr[1] = rotr[2];
-+	rotr[2] = rotr[3];
-+	rotr[3] = temp[0];
-+
-+	xor_32(add1bf7, rotr, temp);
-+	xor_32(swap_halfs, rotl, tempb);
-+	xor_32(temp, tempb, out);
-+}
-+
-+
-+static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext)
-+{
-+	sint round;
-+	sint i;
-+	u8 intermediatea[16];
-+	u8 intermediateb[16];
-+	u8 round_key[16];
-+	for (i = 0; i < 16; i++)
-+		round_key[i] = key[i];
-+
-+	for (round = 0; round < 11; round++) {
-+		if (round == 0) {
-+			xor_128(round_key, data, ciphertext);
-+			next_key(round_key, round);
-+		} else if (round == 10) {
-+			byte_sub(ciphertext, intermediatea);
-+			shift_row(intermediatea, intermediateb);
-+			xor_128(intermediateb, round_key, ciphertext);
-+		} else { /* 1 - 9 */
-+			byte_sub(ciphertext, intermediatea);
-+			shift_row(intermediatea, intermediateb);
-+			mix_column(&intermediateb[0], &intermediatea[0]);
-+			mix_column(&intermediateb[4], &intermediatea[4]);
-+			mix_column(&intermediateb[8], &intermediatea[8]);
-+			mix_column(&intermediateb[12], &intermediatea[12]);
-+			xor_128(intermediatea, round_key, ciphertext);
-+			next_key(round_key, round);
-+		}
-+	}
-+}
-+
-+
-+/************************************************/
-+/* construct_mic_iv()                          */
-+/* Builds the MIC IV from header fields and PN */
-+/* Baron think the function is construct CCM   */
-+/* nonce                                       */
-+/************************************************/
-+static void construct_mic_iv(
-+	u8 *mic_iv,
-+	sint qc_exists,
-+	sint a4_exists,
-+	u8 *mpdu,
-+	uint payload_length,
-+	u8 *pn_vector,
-+	uint frtype/* add for CONFIG_IEEE80211W, none 11w also can use */
-+)
-+{
-+	sint i;
-+	mic_iv[0] = 0x59;
-+	if (qc_exists && a4_exists)
-+		mic_iv[1] = mpdu[30] & 0x0f;    /* QoS_TC          */
-+	if (qc_exists && !a4_exists)
-+		mic_iv[1] = mpdu[24] & 0x0f;   /* mute bits 7-4   */
-+	if (!qc_exists)
-+		mic_iv[1] = 0x00;
-+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
-+	/* 802.11w management frame should set management bit(4) */
-+	if (frtype == WIFI_MGT_TYPE)
-+		mic_iv[1] |= BIT(4);
-+#endif
-+	for (i = 2; i < 8; i++)
-+		mic_iv[i] = mpdu[i + 8];                    /* mic_iv[2:7] = A2[0:5] = mpdu[10:15] */
-+#ifdef CONSISTENT_PN_ORDER
-+	for (i = 8; i < 14; i++)
-+		mic_iv[i] = pn_vector[i - 8];           /* mic_iv[8:13] = PN[0:5] */
-+#else
-+	for (i = 8; i < 14; i++)
-+		mic_iv[i] = pn_vector[13 - i];          /* mic_iv[8:13] = PN[5:0] */
-+#endif
-+	mic_iv[14] = (unsigned char)(payload_length / 256);
-+	mic_iv[15] = (unsigned char)(payload_length % 256);
-+}
-+
-+
-+/************************************************/
-+/* construct_mic_header1()                     */
-+/* Builds the first MIC header block from      */
-+/* header fields.                              */
-+/* Build AAD SC,A1,A2                          */
-+/************************************************/
-+static void construct_mic_header1(
-+	u8 *mic_header1,
-+	sint header_length,
-+	u8 *mpdu,
-+	uint frtype/* add for CONFIG_IEEE80211W, none 11w also can use */
-+)
-+{
-+	mic_header1[0] = (u8)((header_length - 2) / 256);
-+	mic_header1[1] = (u8)((header_length - 2) % 256);
-+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
-+	/* 802.11w management frame don't AND subtype bits 4,5,6 of frame control field */
-+	if (frtype == WIFI_MGT_TYPE)
-+		mic_header1[2] = mpdu[0];
-+	else
-+#endif
-+		mic_header1[2] = mpdu[0] & 0xcf;    /* Mute CF poll & CF ack bits */
-+
-+	mic_header1[3] = mpdu[1] & 0xc7;    /* Mute retry, more data and pwr mgt bits */
-+	mic_header1[4] = mpdu[4];       /* A1 */
-+	mic_header1[5] = mpdu[5];
-+	mic_header1[6] = mpdu[6];
-+	mic_header1[7] = mpdu[7];
-+	mic_header1[8] = mpdu[8];
-+	mic_header1[9] = mpdu[9];
-+	mic_header1[10] = mpdu[10];     /* A2 */
-+	mic_header1[11] = mpdu[11];
-+	mic_header1[12] = mpdu[12];
-+	mic_header1[13] = mpdu[13];
-+	mic_header1[14] = mpdu[14];
-+	mic_header1[15] = mpdu[15];
-+}
-+
-+
-+/************************************************/
-+/* construct_mic_header2()                     */
-+/* Builds the last MIC header block from       */
-+/* header fields.                              */
-+/************************************************/
-+static void construct_mic_header2(
-+	u8 *mic_header2,
-+	u8 *mpdu,
-+	sint a4_exists,
-+	sint qc_exists
-+)
-+{
-+	sint i;
-+	for (i = 0; i < 16; i++)
-+		mic_header2[i] = 0x00;
-+
-+	mic_header2[0] = mpdu[16];    /* A3 */
-+	mic_header2[1] = mpdu[17];
-+	mic_header2[2] = mpdu[18];
-+	mic_header2[3] = mpdu[19];
-+	mic_header2[4] = mpdu[20];
-+	mic_header2[5] = mpdu[21];
-+
-+	/* mic_header2[6] = mpdu[22] & 0xf0;    SC */
-+	mic_header2[6] = 0x00;
-+	mic_header2[7] = 0x00; /* mpdu[23]; */
-+
-+
-+	if (!qc_exists && a4_exists) {
-+		for (i = 0; i < 6; i++)
-+			mic_header2[8 + i] = mpdu[24 + i]; /* A4 */
-+
-+	}
-+
-+	if (qc_exists && !a4_exists) {
-+		mic_header2[8] = mpdu[24] & 0x0f; /* mute bits 15 - 4 */
-+		mic_header2[9] = mpdu[25] & 0x00;
-+	}
-+
-+	if (qc_exists && a4_exists) {
-+		for (i = 0; i < 6; i++)
-+			mic_header2[8 + i] = mpdu[24 + i]; /* A4 */
-+
-+		mic_header2[14] = mpdu[30] & 0x0f;
-+		mic_header2[15] = mpdu[31] & 0x00;
-+	}
-+
-+}
-+
-+
-+/************************************************/
-+/* construct_mic_header2()                     */
-+/* Builds the last MIC header block from       */
-+/* header fields.                              */
-+/* Baron think the function is construct CCM   */
-+/* nonce                                       */
-+/************************************************/
-+static void construct_ctr_preload(
-+	u8 *ctr_preload,
-+	sint a4_exists,
-+	sint qc_exists,
-+	u8 *mpdu,
-+	u8 *pn_vector,
-+	sint c,
-+	uint frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
-+)
-+{
-+	sint i = 0;
-+	for (i = 0; i < 16; i++)
-+		ctr_preload[i] = 0x00;
-+	i = 0;
-+
-+	ctr_preload[0] = 0x01;                                  /* flag */
-+	if (qc_exists && a4_exists)
-+		ctr_preload[1] = mpdu[30] & 0x0f;   /* QoC_Control */
-+	if (qc_exists && !a4_exists)
-+		ctr_preload[1] = mpdu[24] & 0x0f;
-+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
-+	/* 802.11w management frame should set management bit(4) */
-+	if (frtype == WIFI_MGT_TYPE)
-+		ctr_preload[1] |= BIT(4);
-+#endif
-+	for (i = 2; i < 8; i++)
-+		ctr_preload[i] = mpdu[i + 8];                       /* ctr_preload[2:7] = A2[0:5] = mpdu[10:15] */
-+#ifdef CONSISTENT_PN_ORDER
-+	for (i = 8; i < 14; i++)
-+		ctr_preload[i] =    pn_vector[i - 8];           /* ctr_preload[8:13] = PN[0:5] */
-+#else
-+	for (i = 8; i < 14; i++)
-+		ctr_preload[i] =    pn_vector[13 - i];          /* ctr_preload[8:13] = PN[5:0] */
-+#endif
-+	ctr_preload[14] = (unsigned char)(c / 256);   /* Ctr */
-+	ctr_preload[15] = (unsigned char)(c % 256);
-+}
-+
-+
-+/************************************/
-+/* bitwise_xor()                   */
-+/* A 128 bit, bitwise exclusive or */
-+/************************************/
-+static void bitwise_xor(u8 *ina, u8 *inb, u8 *out)
-+{
-+	sint i;
-+	for (i = 0; i < 16; i++)
-+		out[i] = ina[i] ^ inb[i];
-+}
-+
-+
-+static sint aes_cipher(u8 *key, uint	hdrlen,
-+		       u8 *pframe, uint plen)
-+{
-+	/*	static unsigned char	message[MAX_MSG_SIZE]; */
-+	uint	qc_exists, a4_exists, i, j, payload_remainder,
-+		num_blocks, payload_index;
-+
-+	u8 pn_vector[6];
-+	u8 mic_iv[16];
-+	u8 mic_header1[16];
-+	u8 mic_header2[16];
-+	u8 ctr_preload[16];
-+
-+	/* Intermediate Buffers */
-+	u8 chain_buffer[16];
-+	u8 aes_out[16];
-+	u8 padded_buffer[16];
-+	u8 mic[8];
-+	/*	uint	offset = 0; */
-+	uint	frtype  = GetFrameType(pframe);
-+	uint	frsubtype  = get_frame_sub_type(pframe);
-+
-+	frsubtype = frsubtype >> 4;
-+
-+
-+	_rtw_memset((void *)mic_iv, 0, 16);
-+	_rtw_memset((void *)mic_header1, 0, 16);
-+	_rtw_memset((void *)mic_header2, 0, 16);
-+	_rtw_memset((void *)ctr_preload, 0, 16);
-+	_rtw_memset((void *)chain_buffer, 0, 16);
-+	_rtw_memset((void *)aes_out, 0, 16);
-+	_rtw_memset((void *)padded_buffer, 0, 16);
-+
-+	if ((hdrlen == WLAN_HDR_A3_LEN) || (hdrlen ==  WLAN_HDR_A3_QOS_LEN))
-+		a4_exists = 0;
-+	else
-+		a4_exists = 1;
-+
-+	if (
-+		((frtype | frsubtype) == WIFI_DATA_CFACK) ||
-+		((frtype | frsubtype) == WIFI_DATA_CFPOLL) ||
-+		((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) {
-+		qc_exists = 1;
-+		if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
-+			hdrlen += 2;
-+	}
-+	/* add for CONFIG_IEEE80211W, none 11w also can use */
-+	else if ((frtype == WIFI_DATA) &&
-+		 ((frsubtype == 0x08) ||
-+		  (frsubtype == 0x09) ||
-+		  (frsubtype == 0x0a) ||
-+		  (frsubtype == 0x0b))) {
-+		if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
-+			hdrlen += 2;
-+		qc_exists = 1;
-+	} else
-+		qc_exists = 0;
-+
-+	pn_vector[0] = pframe[hdrlen];
-+	pn_vector[1] = pframe[hdrlen + 1];
-+	pn_vector[2] = pframe[hdrlen + 4];
-+	pn_vector[3] = pframe[hdrlen + 5];
-+	pn_vector[4] = pframe[hdrlen + 6];
-+	pn_vector[5] = pframe[hdrlen + 7];
-+
-+	construct_mic_iv(
-+		mic_iv,
-+		qc_exists,
-+		a4_exists,
-+		pframe,	 /* message, */
-+		plen,
-+		pn_vector,
-+		frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
-+	);
-+
-+	construct_mic_header1(
-+		mic_header1,
-+		hdrlen,
-+		pframe,	/* message */
-+		frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
-+	);
-+	construct_mic_header2(
-+		mic_header2,
-+		pframe,	/* message, */
-+		a4_exists,
-+		qc_exists
-+	);
-+
-+
-+	payload_remainder = plen % 16;
-+	num_blocks = plen / 16;
-+
-+	/* Find start of payload */
-+	payload_index = (hdrlen + 8);
-+
-+	/* Calculate MIC */
-+	aes128k128d(key, mic_iv, aes_out);
-+	bitwise_xor(aes_out, mic_header1, chain_buffer);
-+	aes128k128d(key, chain_buffer, aes_out);
-+	bitwise_xor(aes_out, mic_header2, chain_buffer);
-+	aes128k128d(key, chain_buffer, aes_out);
-+
-+	for (i = 0; i < num_blocks; i++) {
-+		bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);/* bitwise_xor(aes_out, &message[payload_index], chain_buffer); */
-+
-+		payload_index += 16;
-+		aes128k128d(key, chain_buffer, aes_out);
-+	}
-+
-+	/* Add on the final payload block if it needs padding */
-+	if (payload_remainder > 0) {
-+		for (j = 0; j < 16; j++)
-+			padded_buffer[j] = 0x00;
-+		for (j = 0; j < payload_remainder; j++) {
-+			padded_buffer[j] = pframe[payload_index++];/* padded_buffer[j] = message[payload_index++]; */
-+		}
-+		bitwise_xor(aes_out, padded_buffer, chain_buffer);
-+		aes128k128d(key, chain_buffer, aes_out);
-+
-+	}
-+
-+	for (j = 0 ; j < 8; j++)
-+		mic[j] = aes_out[j];
-+
-+	/* Insert MIC into payload */
-+	for (j = 0; j < 8; j++)
-+		pframe[payload_index + j] = mic[j];	/* message[payload_index+j] = mic[j]; */
-+
-+	payload_index = hdrlen + 8;
-+	for (i = 0; i < num_blocks; i++) {
-+		construct_ctr_preload(
-+			ctr_preload,
-+			a4_exists,
-+			qc_exists,
-+			pframe,	/* message, */
-+			pn_vector,
-+			i + 1,
-+			frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
-+		aes128k128d(key, ctr_preload, aes_out);
-+		bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);/* bitwise_xor(aes_out, &message[payload_index], chain_buffer); */
-+		for (j = 0; j < 16; j++)
-+			pframe[payload_index++] = chain_buffer[j];/* for (j=0; j<16;j++) message[payload_index++] = chain_buffer[j]; */
-+	}
-+
-+	if (payload_remainder > 0) {        /* If there is a short final block, then pad it,*/
-+		/* encrypt it and copy the unpadded part back  */
-+		construct_ctr_preload(
-+			ctr_preload,
-+			a4_exists,
-+			qc_exists,
-+			pframe,	/* message, */
-+			pn_vector,
-+			num_blocks + 1,
-+			frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
-+
-+		for (j = 0; j < 16; j++)
-+			padded_buffer[j] = 0x00;
-+		for (j = 0; j < payload_remainder; j++) {
-+			padded_buffer[j] = pframe[payload_index + j]; /* padded_buffer[j] = message[payload_index+j]; */
-+		}
-+		aes128k128d(key, ctr_preload, aes_out);
-+		bitwise_xor(aes_out, padded_buffer, chain_buffer);
-+		for (j = 0; j < payload_remainder; j++)
-+			pframe[payload_index++] = chain_buffer[j];/* for (j=0; j<payload_remainder;j++) message[payload_index++] = chain_buffer[j]; */
-+	}
-+
-+	/* Encrypt the MIC */
-+	construct_ctr_preload(
-+		ctr_preload,
-+		a4_exists,
-+		qc_exists,
-+		pframe,	/* message, */
-+		pn_vector,
-+		0,
-+		frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
-+
-+	for (j = 0; j < 16; j++)
-+		padded_buffer[j] = 0x00;
-+	for (j = 0; j < 8; j++) {
-+		padded_buffer[j] = pframe[j + hdrlen + 8 + plen]; /* padded_buffer[j] = message[j+hdrlen+8+plen]; */
-+	}
-+
-+	aes128k128d(key, ctr_preload, aes_out);
-+	bitwise_xor(aes_out, padded_buffer, chain_buffer);
-+	for (j = 0; j < 8; j++)
-+		pframe[payload_index++] = chain_buffer[j];/* for (j=0; j<8;j++) message[payload_index++] = chain_buffer[j]; */
-+	return _SUCCESS;
-+}
-+#endif /* (NEW_CRYPTO == 0) */
-+
-+
-+#if NEW_CRYPTO
-+u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe)
-+{
-+	/* Intermediate Buffers */
-+	struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	sint curfragnum, plen;
-+	u32 prwskeylen;
-+	u8 *pframe;
-+	u8 *prwskey;
-+	u8 hw_hdr_offset = 0;
-+
-+	u32 res = _SUCCESS;
-+
-+	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
-+		return _FAIL;
-+
-+#ifdef CONFIG_USB_TX_AGGREGATION
-+	hw_hdr_offset = TXDESC_SIZE +
-+		(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
-+#else
-+#ifdef CONFIG_TX_EARLY_MODE
-+	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
-+#else
-+	hw_hdr_offset = TXDESC_OFFSET;
-+#endif
-+#endif
-+
-+	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;
-+
-+	/* start to encrypt each fragment */
-+	if ((pattrib->encrypt == _AES_) ||
-+	    (pattrib->encrypt == _CCMP_256_)) {
-+
-+		if (IS_MCAST(pattrib->ra))
-+			prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
-+		else {
-+			prwskey = pattrib->dot118021x_UncstKey.skey;
-+		}
-+
-+#ifdef CONFIG_TDLS
-+		{
-+			/* Swencryption */
-+			struct	sta_info		*ptdls_sta;
-+			ptdls_sta = rtw_get_stainfo(&padapter->stapriv, &pattrib->dst[0]);
-+			if ((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) {
-+				RTW_INFO("[%s] for tdls link\n", __FUNCTION__);
-+				prwskey = &ptdls_sta->tpk.tk[0];
-+			}
-+		}
-+#endif /* CONFIG_TDLS */
-+
-+		prwskeylen = (pattrib->encrypt == _CCMP_256_) ? 32 : 16;
-+
-+		for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
-+
-+			if ((curfragnum + 1) == pattrib->nr_frags) {    /* the last fragment */
-+				plen = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
-+
-+				_rtw_ccmp_encrypt(prwskey, prwskeylen, pattrib->hdrlen, pframe, plen);
-+			} else {
-+				plen = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
-+
-+				_rtw_ccmp_encrypt(prwskey, prwskeylen, pattrib->hdrlen, pframe, plen);
-+				pframe += pxmitpriv->frag_len;
-+				pframe = (u8 *)RND4((SIZE_PTR)(pframe));
-+
-+			}
-+		}
-+
-+		AES_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);
-+
-+	}
-+
-+
-+
-+	return res;
-+}
-+#else
-+u32	rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe)
-+{
-+	/* exclude ICV */
-+
-+
-+	/*static*/
-+	/*	unsigned char	message[MAX_MSG_SIZE]; */
-+
-+	/* Intermediate Buffers */
-+	sint	curfragnum, length;
-+	u32	prwskeylen;
-+	u8	*pframe, *prwskey;	/* , *payload,*iv */
-+	u8   hw_hdr_offset = 0;
-+	/* struct	sta_info		*stainfo=NULL; */
-+	struct	pkt_attrib	*pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
-+	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
-+	struct	xmit_priv		*pxmitpriv = &padapter->xmitpriv;
-+
-+	/*	uint	offset = 0; */
-+	u32 res = _SUCCESS;
-+
-+	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
-+		return _FAIL;
-+
-+#ifdef CONFIG_USB_TX_AGGREGATION
-+	hw_hdr_offset = TXDESC_SIZE +
-+		(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
-+#else
-+#ifdef CONFIG_TX_EARLY_MODE
-+	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
-+#else
-+	hw_hdr_offset = TXDESC_OFFSET;
-+#endif
-+#endif
-+
-+	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;
-+
-+	/* 4 start to encrypt each fragment */
-+	if ((pattrib->encrypt == _AES_)) {
-+		/*
-+				if(pattrib->psta)
-+				{
-+					stainfo = pattrib->psta;
-+				}
-+				else
-+				{
-+					RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
-+					stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );
-+				}
-+		*/
-+		/* if (stainfo!=NULL) */
-+		{
-+			/*
-+						if(!(stainfo->state &WIFI_ASOC_STATE))
-+						{
-+							RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, stainfo->state);
-+							return _FAIL;
-+						}
-+			*/
-+
-+			if (IS_MCAST(pattrib->ra))
-+				prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
-+			else {
-+				/* prwskey=&stainfo->dot118021x_UncstKey.skey[0]; */
-+				prwskey = pattrib->dot118021x_UncstKey.skey;
-+			}
-+
-+#ifdef CONFIG_TDLS
-+			{
-+				/* Swencryption */
-+				struct	sta_info		*ptdls_sta;
-+				ptdls_sta = rtw_get_stainfo(&padapter->stapriv , &pattrib->dst[0]);
-+				if ((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) {
-+					RTW_INFO("[%s] for tdls link\n", __FUNCTION__);
-+					prwskey = &ptdls_sta->tpk.tk[0];
-+				}
-+			}
-+#endif /* CONFIG_TDLS */
-+
-+			prwskeylen = 16;
-+
-+			for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
-+
-+				if ((curfragnum + 1) == pattrib->nr_frags) {	/* 4 the last fragment */
-+					length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
-+
-+					aes_cipher(prwskey, pattrib->hdrlen, pframe, length);
-+				} else {
-+					length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ;
-+
-+					aes_cipher(prwskey, pattrib->hdrlen, pframe, length);
-+					pframe += pxmitpriv->frag_len;
-+					pframe = (u8 *)RND4((SIZE_PTR)(pframe));
-+
-+				}
-+			}
-+
-+			AES_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);
-+		}
-+		/*
-+				else{
-+					RTW_INFO("%s, psta==NUL\n", __func__);
-+					res=_FAIL;
-+				}
-+		*/
-+	}
-+
-+
-+
-+	return res;
-+}
-+#endif
-+
-+#if (NEW_CRYPTO == 0)
-+static sint aes_decipher(u8 *key, uint	hdrlen,
-+			 u8 *pframe, uint plen)
-+{
-+	static u8	message[MAX_MSG_SIZE];
-+	uint	qc_exists, a4_exists, i, j, payload_remainder,
-+		num_blocks, payload_index;
-+	sint res = _SUCCESS;
-+	u8 pn_vector[6];
-+	u8 mic_iv[16];
-+	u8 mic_header1[16];
-+	u8 mic_header2[16];
-+	u8 ctr_preload[16];
-+
-+	/* Intermediate Buffers */
-+	u8 chain_buffer[16];
-+	u8 aes_out[16];
-+	u8 padded_buffer[16];
-+	u8 mic[8];
-+
-+
-+	/*	uint	offset = 0; */
-+	uint	frtype  = GetFrameType(pframe);
-+	uint	frsubtype  = get_frame_sub_type(pframe);
-+	frsubtype = frsubtype >> 4;
-+
-+
-+	_rtw_memset((void *)mic_iv, 0, 16);
-+	_rtw_memset((void *)mic_header1, 0, 16);
-+	_rtw_memset((void *)mic_header2, 0, 16);
-+	_rtw_memset((void *)ctr_preload, 0, 16);
-+	_rtw_memset((void *)chain_buffer, 0, 16);
-+	_rtw_memset((void *)aes_out, 0, 16);
-+	_rtw_memset((void *)padded_buffer, 0, 16);
-+
-+	/* start to decrypt the payload */
-+
-+	num_blocks = (plen - 8) / 16; /* (plen including LLC, payload_length and mic ) */
-+
-+	payload_remainder = (plen - 8) % 16;
-+
-+	pn_vector[0]  = pframe[hdrlen];
-+	pn_vector[1]  = pframe[hdrlen + 1];
-+	pn_vector[2]  = pframe[hdrlen + 4];
-+	pn_vector[3]  = pframe[hdrlen + 5];
-+	pn_vector[4]  = pframe[hdrlen + 6];
-+	pn_vector[5]  = pframe[hdrlen + 7];
-+
-+	if ((hdrlen == WLAN_HDR_A3_LEN) || (hdrlen ==  WLAN_HDR_A3_QOS_LEN))
-+		a4_exists = 0;
-+	else
-+		a4_exists = 1;
-+
-+	if (
-+		((frtype | frsubtype) == WIFI_DATA_CFACK) ||
-+		((frtype | frsubtype) == WIFI_DATA_CFPOLL) ||
-+		((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) {
-+		qc_exists = 1;
-+		if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
-+			hdrlen += 2;
-+	} /* only for data packet . add for CONFIG_IEEE80211W, none 11w also can use */
-+	else if ((frtype == WIFI_DATA) &&
-+		 ((frsubtype == 0x08) ||
-+		  (frsubtype == 0x09) ||
-+		  (frsubtype == 0x0a) ||
-+		  (frsubtype == 0x0b))) {
-+		if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
-+			hdrlen += 2;
-+		qc_exists = 1;
-+	} else
-+		qc_exists = 0;
-+
-+
-+	/* now, decrypt pframe with hdrlen offset and plen long */
-+
-+	payload_index = hdrlen + 8; /* 8 is for extiv */
-+
-+	for (i = 0; i < num_blocks; i++) {
-+		construct_ctr_preload(
-+			ctr_preload,
-+			a4_exists,
-+			qc_exists,
-+			pframe,
-+			pn_vector,
-+			i + 1,
-+			frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
-+		);
-+
-+		aes128k128d(key, ctr_preload, aes_out);
-+		bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);
-+
-+		for (j = 0; j < 16; j++)
-+			pframe[payload_index++] = chain_buffer[j];
-+	}
-+
-+	if (payload_remainder > 0) {        /* If there is a short final block, then pad it,*/
-+		/* encrypt it and copy the unpadded part back  */
-+		construct_ctr_preload(
-+			ctr_preload,
-+			a4_exists,
-+			qc_exists,
-+			pframe,
-+			pn_vector,
-+			num_blocks + 1,
-+			frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
-+		);
-+
-+		for (j = 0; j < 16; j++)
-+			padded_buffer[j] = 0x00;
-+		for (j = 0; j < payload_remainder; j++)
-+			padded_buffer[j] = pframe[payload_index + j];
-+		aes128k128d(key, ctr_preload, aes_out);
-+		bitwise_xor(aes_out, padded_buffer, chain_buffer);
-+		for (j = 0; j < payload_remainder; j++)
-+			pframe[payload_index++] = chain_buffer[j];
-+	}
-+
-+	/* start to calculate the mic	 */
-+	if ((hdrlen + plen + 8) <= MAX_MSG_SIZE)
-+		_rtw_memcpy((void *)message, pframe, (hdrlen + plen + 8)); /* 8 is for ext iv len */
-+
-+
-+	pn_vector[0] = pframe[hdrlen];
-+	pn_vector[1] = pframe[hdrlen + 1];
-+	pn_vector[2] = pframe[hdrlen + 4];
-+	pn_vector[3] = pframe[hdrlen + 5];
-+	pn_vector[4] = pframe[hdrlen + 6];
-+	pn_vector[5] = pframe[hdrlen + 7];
-+
-+
-+
-+	construct_mic_iv(
-+		mic_iv,
-+		qc_exists,
-+		a4_exists,
-+		message,
-+		plen - 8,
-+		pn_vector,
-+		frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
-+	);
-+
-+	construct_mic_header1(
-+		mic_header1,
-+		hdrlen,
-+		message,
-+		frtype /* add for CONFIG_IEEE80211W, none 11w also can use */
-+	);
-+	construct_mic_header2(
-+		mic_header2,
-+		message,
-+		a4_exists,
-+		qc_exists
-+	);
-+
-+
-+	payload_remainder = (plen - 8) % 16;
-+	num_blocks = (plen - 8) / 16;
-+
-+	/* Find start of payload */
-+	payload_index = (hdrlen + 8);
-+
-+	/* Calculate MIC */
-+	aes128k128d(key, mic_iv, aes_out);
-+	bitwise_xor(aes_out, mic_header1, chain_buffer);
-+	aes128k128d(key, chain_buffer, aes_out);
-+	bitwise_xor(aes_out, mic_header2, chain_buffer);
-+	aes128k128d(key, chain_buffer, aes_out);
-+
-+	for (i = 0; i < num_blocks; i++) {
-+		bitwise_xor(aes_out, &message[payload_index], chain_buffer);
-+
-+		payload_index += 16;
-+		aes128k128d(key, chain_buffer, aes_out);
-+	}
-+
-+	/* Add on the final payload block if it needs padding */
-+	if (payload_remainder > 0) {
-+		for (j = 0; j < 16; j++)
-+			padded_buffer[j] = 0x00;
-+		for (j = 0; j < payload_remainder; j++)
-+			padded_buffer[j] = message[payload_index++];
-+		bitwise_xor(aes_out, padded_buffer, chain_buffer);
-+		aes128k128d(key, chain_buffer, aes_out);
-+
-+	}
-+
-+	for (j = 0 ; j < 8; j++)
-+		mic[j] = aes_out[j];
-+
-+	/* Insert MIC into payload */
-+	for (j = 0; j < 8; j++)
-+		message[payload_index + j] = mic[j];
-+
-+	payload_index = hdrlen + 8;
-+	for (i = 0; i < num_blocks; i++) {
-+		construct_ctr_preload(
-+			ctr_preload,
-+			a4_exists,
-+			qc_exists,
-+			message,
-+			pn_vector,
-+			i + 1,
-+			frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
-+		aes128k128d(key, ctr_preload, aes_out);
-+		bitwise_xor(aes_out, &message[payload_index], chain_buffer);
-+		for (j = 0; j < 16; j++)
-+			message[payload_index++] = chain_buffer[j];
-+	}
-+
-+	if (payload_remainder > 0) {        /* If there is a short final block, then pad it,*/
-+		/* encrypt it and copy the unpadded part back  */
-+		construct_ctr_preload(
-+			ctr_preload,
-+			a4_exists,
-+			qc_exists,
-+			message,
-+			pn_vector,
-+			num_blocks + 1,
-+			frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
-+
-+		for (j = 0; j < 16; j++)
-+			padded_buffer[j] = 0x00;
-+		for (j = 0; j < payload_remainder; j++)
-+			padded_buffer[j] = message[payload_index + j];
-+		aes128k128d(key, ctr_preload, aes_out);
-+		bitwise_xor(aes_out, padded_buffer, chain_buffer);
-+		for (j = 0; j < payload_remainder; j++)
-+			message[payload_index++] = chain_buffer[j];
-+	}
-+
-+	/* Encrypt the MIC */
-+	construct_ctr_preload(
-+		ctr_preload,
-+		a4_exists,
-+		qc_exists,
-+		message,
-+		pn_vector,
-+		0,
-+		frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */
-+
-+	for (j = 0; j < 16; j++)
-+		padded_buffer[j] = 0x00;
-+	for (j = 0; j < 8; j++)
-+		padded_buffer[j] = message[j + hdrlen + 8 + plen - 8];
-+
-+	aes128k128d(key, ctr_preload, aes_out);
-+	bitwise_xor(aes_out, padded_buffer, chain_buffer);
-+	for (j = 0; j < 8; j++)
-+		message[payload_index++] = chain_buffer[j];
-+
-+	/* compare the mic */
-+	for (i = 0; i < 8; i++) {
-+		if (pframe[hdrlen + 8 + plen - 8 + i] != message[hdrlen + 8 + plen - 8 + i]) {
-+			RTW_INFO("aes_decipher:mic check error mic[%d]: pframe(%x) != message(%x)\n",
-+				i, pframe[hdrlen + 8 + plen - 8 + i], message[hdrlen + 8 + plen - 8 + i]);
-+			res = _FAIL;
-+		}
-+	}
-+	return res;
-+}
-+#endif /* (NEW_CRYPTO == 0) */
-+
-+#if NEW_CRYPTO
-+u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe)
-+{
-+	struct sta_info *stainfo;
-+	struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	u8 *pframe;
-+	u8 *prwskey;
-+	u32 res = _SUCCESS;
-+
-+	pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
-+	/* start to encrypt each fragment */
-+	if ((prxattrib->encrypt == _AES_) ||
-+	    (prxattrib->encrypt == _CCMP_256_)) {
-+
-+		stainfo = rtw_get_stainfo(&padapter->stapriv, &prxattrib->ta[0]);
-+		if (stainfo != NULL) {
-+
-+			if (IS_MCAST(prxattrib->ra)) {
-+				static systime start = 0;
-+				static u32 no_gkey_bc_cnt = 0;
-+				static u32 no_gkey_mc_cnt = 0;
-+
-+				if ((!MLME_IS_MESH(padapter) && psecuritypriv->binstallGrpkey == _FALSE)
-+					#ifdef CONFIG_RTW_MESH
-+					|| !(stainfo->gtk_bmp | BIT(prxattrib->key_index))
-+					#endif
-+				) {
-+					res = _FAIL;
-+
-+					if (start == 0)
-+						start = rtw_get_current_time();
-+
-+					if (is_broadcast_mac_addr(prxattrib->ra))
-+						no_gkey_bc_cnt++;
-+					else
-+						no_gkey_mc_cnt++;
-+
-+					if (rtw_get_passing_time_ms(start) > 1000) {
-+						if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
-+							RTW_PRINT(FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
-+								FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
-+						}
-+						start = rtw_get_current_time();
-+						no_gkey_bc_cnt = 0;
-+						no_gkey_mc_cnt = 0;
-+					}
-+
-+					goto exit;
-+				}
-+
-+				if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
-+					RTW_PRINT(FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
-+						FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
-+				}
-+				start = 0;
-+				no_gkey_bc_cnt = 0;
-+				no_gkey_mc_cnt = 0;
-+
-+				#ifdef CONFIG_RTW_MESH
-+				if (MLME_IS_MESH(padapter)) {
-+					/* TODO: multiple GK? */
-+					prwskey = &stainfo->gtk.skey[0];
-+				} else
-+				#endif
-+				{
-+					prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;
-+					if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) {
-+						RTW_DBG("not match packet_index=%d, install_index=%d\n"
-+							, prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid);
-+						res = _FAIL;
-+						goto exit;
-+					}
-+				}
-+			} else
-+				prwskey = &stainfo->dot118021x_UncstKey.skey[0];
-+
-+			res = _rtw_ccmp_decrypt(prwskey,
-+				prxattrib->encrypt == _CCMP_256_ ? 32 : 16,
-+				prxattrib->hdrlen, pframe,
-+				((union recv_frame *)precvframe)->u.hdr.len);
-+
-+			AES_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
-+		} else {
-+			res = _FAIL;
-+		}
-+
-+	}
-+exit:
-+	return res;
-+}
-+#else
-+u32	rtw_aes_decrypt(_adapter *padapter, u8 *precvframe)
-+{
-+	/* exclude ICV */
-+
-+
-+	/*static*/
-+	/*	unsigned char	message[MAX_MSG_SIZE]; */
-+
-+
-+	/* Intermediate Buffers */
-+
-+
-+	sint		length;
-+	u8	*pframe, *prwskey;	/* , *payload,*iv */
-+	struct	sta_info		*stainfo;
-+	struct	rx_pkt_attrib	*prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
-+	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
-+	/*	struct	recv_priv		*precvpriv=&padapter->recvpriv; */
-+	u32	res = _SUCCESS;
-+	pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
-+	/* 4 start to encrypt each fragment */
-+	if ((prxattrib->encrypt == _AES_)) {
-+
-+		stainfo = rtw_get_stainfo(&padapter->stapriv , &prxattrib->ta[0]);
-+		if (stainfo != NULL) {
-+
-+			if (IS_MCAST(prxattrib->ra)) {
-+				static systime start = 0;
-+				static u32 no_gkey_bc_cnt = 0;
-+				static u32 no_gkey_mc_cnt = 0;
-+
-+				/* RTW_INFO("rx bc/mc packets, to perform sw rtw_aes_decrypt\n"); */
-+				/* prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; */
-+				if ((!MLME_IS_MESH(padapter) && psecuritypriv->binstallGrpkey == _FALSE)
-+					#ifdef CONFIG_RTW_MESH
-+					|| !(stainfo->gtk_bmp | BIT(prxattrib->key_index))
-+					#endif
-+				) {
-+					res = _FAIL;
-+
-+					if (start == 0)
-+						start = rtw_get_current_time();
-+
-+					if (is_broadcast_mac_addr(prxattrib->ra))
-+						no_gkey_bc_cnt++;
-+					else
-+						no_gkey_mc_cnt++;
-+
-+					if (rtw_get_passing_time_ms(start) > 1000) {
-+						if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
-+							RTW_PRINT(FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
-+								FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
-+						}
-+						start = rtw_get_current_time();
-+						no_gkey_bc_cnt = 0;
-+						no_gkey_mc_cnt = 0;
-+					}
-+
-+					goto exit;
-+				}
-+
-+				if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
-+					RTW_PRINT(FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
-+						FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
-+				}
-+				start = 0;
-+				no_gkey_bc_cnt = 0;
-+				no_gkey_mc_cnt = 0;
-+
-+				#ifdef CONFIG_RTW_MESH
-+				if (MLME_IS_MESH(padapter)) {
-+					/* TODO: multiple GK? */
-+					prwskey = &stainfo->gtk.skey[0];
-+				} else
-+				#endif
-+				{
-+					prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;
-+					if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) {
-+						RTW_DBG("not match packet_index=%d, install_index=%d\n"
-+							, prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid);
-+						res = _FAIL;
-+						goto exit;
-+					}
-+				}
-+			} else
-+				prwskey = &stainfo->dot118021x_UncstKey.skey[0];
-+
-+			length = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len;
-+#if 0
-+			/*  add for CONFIG_IEEE80211W, debug */
-+			if (0)
-+				printk("@@@@@@@@@@@@@@@@@@ length=%d, prxattrib->hdrlen=%d, prxattrib->pkt_len=%d\n"
-+				       , length, prxattrib->hdrlen, prxattrib->pkt_len);
-+			if (0) {
-+				int no;
-+				/* test print PSK */
-+				printk("PSK key below:\n");
-+				for (no = 0; no < 16; no++)
-+					printk(" %02x ", prwskey[no]);
-+				printk("\n");
-+			}
-+			if (0) {
-+				int no;
-+				/* test print PSK */
-+				printk("frame:\n");
-+				for (no = 0; no < prxattrib->pkt_len; no++)
-+					printk(" %02x ", pframe[no]);
-+				printk("\n");
-+			}
-+#endif
-+
-+			res = aes_decipher(prwskey, prxattrib->hdrlen, pframe, length);
-+
-+			AES_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
-+		} else {
-+			res = _FAIL;
-+		}
-+
-+	}
-+exit:
-+	return res;
-+}
-+#endif
-+
-+#ifdef CONFIG_RTW_MESH_AEK
-+/* for AES-SIV, wrapper to ase_siv_encrypt and aes_siv_decrypt */
-+int rtw_aes_siv_encrypt(const u8 *key, size_t key_len, const u8 *pw,
-+	size_t pwlen, size_t num_elem,
-+	const u8 *addr[], const size_t *len, u8 *out)
-+{
-+	return _aes_siv_encrypt(key, key_len, pw, pwlen,
-+		num_elem, addr, len, out);
-+}
-+
-+int rtw_aes_siv_decrypt(const u8 *key, size_t key_len, const u8 *iv_crypt, size_t iv_c_len,
-+	size_t num_elem, const u8 *addr[], const size_t *len, u8 *out)
-+{
-+	return _aes_siv_decrypt(key, key_len, iv_crypt,
-+		iv_c_len, num_elem, addr, len, out);
-+}
-+#endif /* CONFIG_RTW_MESH_AEK */
-+
-+#ifdef CONFIG_TDLS
-+void wpa_tdls_generate_tpk(_adapter *padapter, void *sta)
-+{
-+	struct sta_info *psta = (struct sta_info *)sta;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+	_tdls_generate_tpk(psta, adapter_mac_addr(padapter), get_bssid(pmlmepriv));
-+}
-+
-+/**
-+ * wpa_tdls_ftie_mic - Calculate TDLS FTIE MIC
-+ * @kck: TPK-KCK
-+ * @lnkid: Pointer to the beginning of Link Identifier IE
-+ * @rsnie: Pointer to the beginning of RSN IE used for handshake
-+ * @timeoutie: Pointer to the beginning of Timeout IE used for handshake
-+ * @ftie: Pointer to the beginning of FT IE
-+ * @mic: Pointer for writing MIC
-+ *
-+ * Calculate MIC for TDLS frame.
-+ */
-+int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq,
-+		      u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie,
-+		      u8 *mic)
-+{
-+	u8 *buf, *pos;
-+	struct wpa_tdls_ftie *_ftie;
-+	struct wpa_tdls_lnkid *_lnkid;
-+	int ret;
-+	int len = 2 * ETH_ALEN + 1 + 2 + lnkid[1] + 2 + rsnie[1] +
-+		  2 + timeoutie[1] + 2 + ftie[1];
-+	buf = rtw_zmalloc(len);
-+	if (!buf) {
-+		RTW_INFO("TDLS: No memory for MIC calculation\n");
-+		return -1;
-+	}
-+
-+	pos = buf;
-+	_lnkid = (struct wpa_tdls_lnkid *) lnkid;
-+	/* 1) TDLS initiator STA MAC address */
-+	_rtw_memcpy(pos, _lnkid->init_sta, ETH_ALEN);
-+	pos += ETH_ALEN;
-+	/* 2) TDLS responder STA MAC address */
-+	_rtw_memcpy(pos, _lnkid->resp_sta, ETH_ALEN);
-+	pos += ETH_ALEN;
-+	/* 3) Transaction Sequence number */
-+	*pos++ = trans_seq;
-+	/* 4) Link Identifier IE */
-+	_rtw_memcpy(pos, lnkid, 2 + lnkid[1]);
-+	pos += 2 + lnkid[1];
-+	/* 5) RSN IE */
-+	_rtw_memcpy(pos, rsnie, 2 + rsnie[1]);
-+	pos += 2 + rsnie[1];
-+	/* 6) Timeout Interval IE */
-+	_rtw_memcpy(pos, timeoutie, 2 + timeoutie[1]);
-+	pos += 2 + timeoutie[1];
-+	/* 7) FTIE, with the MIC field of the FTIE set to 0 */
-+	_rtw_memcpy(pos, ftie, 2 + ftie[1]);
-+	_ftie = (struct wpa_tdls_ftie *) pos;
-+	_rtw_memset(_ftie->mic, 0, TDLS_MIC_LEN);
-+	pos += 2 + ftie[1];
-+
-+	/* ret = omac1_aes_128(kck, buf, pos - buf, mic); */
-+	ret = _bip_ccmp_protect(kck, 16, buf, pos - buf, mic);
-+	rtw_mfree(buf, len);
-+	return ret;
-+
-+}
-+
-+/**
-+ * wpa_tdls_teardown_ftie_mic - Calculate TDLS TEARDOWN FTIE MIC
-+ * @kck: TPK-KCK
-+ * @lnkid: Pointer to the beginning of Link Identifier IE
-+ * @reason: Reason code of TDLS Teardown
-+ * @dialog_token: Dialog token that was used in the MIC calculation for TPK Handshake Message 3
-+ * @trans_seq: Transaction Sequence number (1 octet) which shall be set to the value 4
-+ * @ftie: Pointer to the beginning of FT IE
-+ * @mic: Pointer for writing MIC
-+ *
-+ * Calculate MIC for TDLS TEARDOWN frame according to Section 10.22.5 in IEEE 802.11 - 2012.
-+ */
-+int wpa_tdls_teardown_ftie_mic(u8 *kck, u8 *lnkid, u16 reason,
-+			       u8 dialog_token, u8 trans_seq, u8 *ftie, u8 *mic)
-+{
-+	u8 *buf, *pos;
-+	struct wpa_tdls_ftie *_ftie;
-+	int ret;
-+	int len = 2 + lnkid[1] + 2 + 1 + 1 + 2 + ftie[1];
-+
-+	buf = rtw_zmalloc(len);
-+	if (!buf) {
-+		RTW_INFO("TDLS: No memory for MIC calculation\n");
-+		return -1;
-+	}
-+
-+	pos = buf;
-+	/* 1) Link Identifier IE */
-+	_rtw_memcpy(pos, lnkid, 2 + lnkid[1]);
-+	pos += 2 + lnkid[1];
-+	/* 2) Reason Code */
-+	_rtw_memcpy(pos, (u8 *)&reason, 2);
-+	pos += 2;
-+	/* 3) Dialog Token */
-+	*pos++ = dialog_token;
-+	/* 4) Transaction Sequence number */
-+	*pos++ = trans_seq;
-+	/* 5) FTIE, with the MIC field of the FTIE set to 0 */
-+	_rtw_memcpy(pos, ftie, 2 + ftie[1]);
-+	_ftie = (struct wpa_tdls_ftie *) pos;
-+	_rtw_memset(_ftie->mic, 0, TDLS_MIC_LEN);
-+	pos += 2 + ftie[1];
-+
-+	/* ret = omac1_aes_128(kck, buf, pos - buf, mic); */
-+	ret = _bip_ccmp_protect(kck, 16, buf, pos - buf, mic);
-+	rtw_mfree(buf, len);
-+	return ret;
-+
-+}
-+
-+int tdls_verify_mic(u8 *kck, u8 trans_seq,
-+		    u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie)
-+{
-+	u8 *buf, *pos;
-+	int len;
-+	u8 mic[16];
-+	int ret;
-+	u8 *rx_ftie, *tmp_ftie;
-+
-+	if (lnkid == NULL || rsnie == NULL ||
-+	    timeoutie == NULL || ftie == NULL)
-+		return _FAIL;
-+
-+	len = 2 * ETH_ALEN + 1 + 2 + 18 + 2 + *(rsnie + 1) + 2 + *(timeoutie + 1) + 2 + *(ftie + 1);
-+
-+	buf = rtw_zmalloc(len);
-+	if (buf == NULL)
-+		return _FAIL;
-+
-+	pos = buf;
-+	/* 1) TDLS initiator STA MAC address */
-+	_rtw_memcpy(pos, lnkid + ETH_ALEN + 2, ETH_ALEN);
-+	pos += ETH_ALEN;
-+	/* 2) TDLS responder STA MAC address */
-+	_rtw_memcpy(pos, lnkid + 2 * ETH_ALEN + 2, ETH_ALEN);
-+	pos += ETH_ALEN;
-+	/* 3) Transaction Sequence number */
-+	*pos++ = trans_seq;
-+	/* 4) Link Identifier IE */
-+	_rtw_memcpy(pos, lnkid, 2 + 18);
-+	pos += 2 + 18;
-+	/* 5) RSN IE */
-+	_rtw_memcpy(pos, rsnie, 2 + *(rsnie + 1));
-+	pos += 2 + *(rsnie + 1);
-+	/* 6) Timeout Interval IE */
-+	_rtw_memcpy(pos, timeoutie, 2 + *(timeoutie + 1));
-+	pos += 2 + *(timeoutie + 1);
-+	/* 7) FTIE, with the MIC field of the FTIE set to 0 */
-+	_rtw_memcpy(pos, ftie, 2 + *(ftie + 1));
-+	pos += 2;
-+	tmp_ftie = (u8 *)(pos + 2);
-+	_rtw_memset(tmp_ftie, 0, 16);
-+	pos += *(ftie + 1);
-+
-+	/* ret = omac1_aes_128(kck, buf, pos - buf, mic); */
-+	ret = _bip_ccmp_protect(kck, 16, buf, pos - buf, mic);
-+	rtw_mfree(buf, len);
-+	if (ret == _FAIL)
-+		return _FAIL;
-+	rx_ftie = ftie + 4;
-+
-+	if (_rtw_memcmp2(mic, rx_ftie, 16) == 0) {
-+		/* Valid MIC */
-+		return _SUCCESS;
-+	}
-+
-+	/* Invalid MIC */
-+	RTW_INFO("[%s] Invalid MIC\n", __FUNCTION__);
-+	return _FAIL;
-+
-+}
-+#endif /* CONFIG_TDLS */
-+
-+/* Restore HW wep key setting according to key_mask */
-+void rtw_sec_restore_wep_key(_adapter *adapter)
-+{
-+	struct security_priv *securitypriv = &(adapter->securitypriv);
-+	sint keyid;
-+
-+	if ((_WEP40_ == securitypriv->dot11PrivacyAlgrthm) || (_WEP104_ == securitypriv->dot11PrivacyAlgrthm)) {
-+		for (keyid = 0; keyid < 4; keyid++) {
-+			if (securitypriv->key_mask & BIT(keyid)) {
-+				if (keyid == securitypriv->dot11PrivacyKeyIndex)
-+					rtw_set_key(adapter, securitypriv, keyid, 1, _FALSE);
-+				else
-+					rtw_set_key(adapter, securitypriv, keyid, 0, _FALSE);
-+			}
-+		}
-+	}
-+}
-+
-+u8 rtw_handle_tkip_countermeasure(_adapter *adapter, const char *caller)
-+{
-+	struct security_priv *securitypriv = &(adapter->securitypriv);
-+	u8 status = _SUCCESS;
-+
-+	if (securitypriv->btkip_countermeasure == _TRUE) {
-+		u32 passing_ms = rtw_get_passing_time_ms(securitypriv->btkip_countermeasure_time);
-+		if (passing_ms > 60 * 1000) {
-+			RTW_PRINT("%s("ADPT_FMT") countermeasure time:%ds > 60s\n",
-+				  caller, ADPT_ARG(adapter), passing_ms / 1000);
-+			securitypriv->btkip_countermeasure = _FALSE;
-+			securitypriv->btkip_countermeasure_time = 0;
-+		} else {
-+			RTW_PRINT("%s("ADPT_FMT") countermeasure time:%ds < 60s\n",
-+				  caller, ADPT_ARG(adapter), passing_ms / 1000);
-+			status = _FAIL;
-+		}
-+	}
-+
-+	return status;
-+}
-+
-+#ifdef CONFIG_WOWLAN
-+u16 rtw_cal_crc16(u8 data, u16 crc)
-+{
-+	u8 shift_in, data_bit;
-+	u8 crc_bit4, crc_bit11, crc_bit15;
-+	u16 crc_result;
-+	int index;
-+
-+	for (index = 0; index < 8; index++) {
-+		crc_bit15 = ((crc & BIT15) ? 1 : 0);
-+		data_bit = (data & (BIT0 << index) ? 1 : 0);
-+		shift_in = crc_bit15 ^ data_bit;
-+		/*printf("crc_bit15=%d, DataBit=%d, shift_in=%d\n",
-+		 * crc_bit15, data_bit, shift_in);*/
-+
-+		crc_result = crc << 1;
-+
-+		if (shift_in == 0)
-+			crc_result &= (~BIT0);
-+		else
-+			crc_result |= BIT0;
-+		/*printf("CRC =%x\n",CRC_Result);*/
-+
-+		crc_bit11 = ((crc & BIT11) ? 1 : 0) ^ shift_in;
-+
-+		if (crc_bit11 == 0)
-+			crc_result &= (~BIT12);
-+		else
-+			crc_result |= BIT12;
-+
-+		/*printf("bit12 CRC =%x\n",CRC_Result);*/
-+
-+		crc_bit4 = ((crc & BIT4) ? 1 : 0) ^ shift_in;
-+
-+		if (crc_bit4 == 0)
-+			crc_result &= (~BIT5);
-+		else
-+			crc_result |= BIT5;
-+
-+		/* printf("bit5 CRC =%x\n",CRC_Result); */
-+		/* repeat using the last result*/
-+		crc = crc_result;
-+	}
-+	return crc;
-+}
-+
-+/*
-+ * function name :rtw_calc_crc
-+ *
-+ * input: char* pattern , pattern size
-+ *
-+ */
-+u16 rtw_calc_crc(u8  *pdata, int length)
-+{
-+	u16 crc = 0xffff;
-+	int i;
-+
-+	for (i = 0; i < length; i++)
-+		crc = rtw_cal_crc16(pdata[i], crc);
-+	/* get 1' complement */
-+	crc = ~crc;
-+
-+	return crc;
-+}
-+#endif /*CONFIG_WOWLAN*/
-+
-+u32 rtw_calc_crc32(u8 *data, size_t len)
-+{
-+	size_t i;
-+	u32 crc = 0xFFFFFFFF;
-+
-+	if (bcrc32initialized == 0)
-+		crc32_init();
-+
-+	for (i = 0; i < len; i++)
-+		crc = crc32_table[(crc ^ data[i]) & 0xff] ^ (crc >> 8);
-+
-+	/* return 1' complement */
-+	return ~crc;
-+}
-+
-+
-+/**
-+ * rtw_gcmp_encrypt - 
-+ * @padapter:
-+ * @pxmitframe:
-+ *
-+ */
-+u32 rtw_gcmp_encrypt(_adapter *padapter, u8 *pxmitframe)
-+{
-+	struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	/* Intermediate Buffers */
-+	sint curfragnum, plen;
-+	u32 prwskeylen;
-+	u8 *pframe = NULL;
-+	u8 *prwskey = NULL;
-+	u8 hw_hdr_offset = 0;
-+	u32 res = _SUCCESS;
-+
-+	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
-+		return _FAIL;
-+
-+#ifdef CONFIG_USB_TX_AGGREGATION
-+	hw_hdr_offset = TXDESC_SIZE +
-+		(((struct xmit_frame *)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ);
-+#else
-+#ifdef CONFIG_TX_EARLY_MODE
-+	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
-+#else
-+	hw_hdr_offset = TXDESC_OFFSET;
-+#endif
-+#endif
-+
-+	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset;
-+
-+	/* start to encrypt each fragment */
-+	if ((pattrib->encrypt == _GCMP_) ||
-+		(pattrib->encrypt == _GCMP_256_)) {
-+
-+		if (IS_MCAST(pattrib->ra))
-+			prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
-+		else
-+			prwskey = pattrib->dot118021x_UncstKey.skey;
-+
-+		prwskeylen = (pattrib->encrypt == _GCMP_256_) ? 32 : 16;
-+
-+		for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
-+			if ((curfragnum + 1) == pattrib->nr_frags) {
-+				/* the last fragment */
-+				plen = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
-+
-+				_rtw_gcmp_encrypt(prwskey, prwskeylen, pattrib->hdrlen, pframe, plen);
-+			} else {
-+				plen = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
-+
-+				_rtw_gcmp_encrypt(prwskey, prwskeylen, pattrib->hdrlen, pframe, plen);
-+				pframe += pxmitpriv->frag_len;
-+				pframe = (u8 *)RND4((SIZE_PTR)(pframe));
-+			}
-+		}
-+
-+		GCMP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);
-+	}
-+
-+	return res;
-+}
-+
-+u32 rtw_gcmp_decrypt(_adapter *padapter, u8 *precvframe)
-+{
-+	u32 prwskeylen;
-+	u8 * pframe,*prwskey;
-+	struct sta_info *stainfo;
-+	struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	u32 res = _SUCCESS;
-+	pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
-+
-+	if ((prxattrib->encrypt == _GCMP_) ||
-+		(prxattrib->encrypt == _GCMP_256_)) {
-+		stainfo = rtw_get_stainfo(&padapter->stapriv, &prxattrib->ta[0]);
-+		if (stainfo != NULL) {
-+			if (IS_MCAST(prxattrib->ra)) {
-+				static systime start = 0;
-+				static u32 no_gkey_bc_cnt = 0;
-+				static u32 no_gkey_mc_cnt = 0;
-+
-+				if ((!MLME_IS_MESH(padapter) && psecuritypriv->binstallGrpkey == _FALSE)
-+					#ifdef CONFIG_RTW_MESH
-+					|| !(stainfo->gtk_bmp | BIT(prxattrib->key_index))
-+					#endif
-+				) {
-+					res = _FAIL;
-+
-+					if (start == 0)
-+						start = rtw_get_current_time();
-+
-+					if (is_broadcast_mac_addr(prxattrib->ra))
-+						no_gkey_bc_cnt++;
-+					else
-+						no_gkey_mc_cnt++;
-+
-+					if (rtw_get_passing_time_ms(start) > 1000) {
-+						if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
-+							RTW_PRINT(FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
-+								FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
-+						}
-+						start = rtw_get_current_time();
-+						no_gkey_bc_cnt = 0;
-+						no_gkey_mc_cnt = 0;
-+					}
-+
-+					goto exit;
-+				}
-+
-+				if (no_gkey_bc_cnt || no_gkey_mc_cnt) {
-+					RTW_PRINT(FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n",
-+						FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt);
-+				}
-+				start = 0;
-+				no_gkey_bc_cnt = 0;
-+				no_gkey_mc_cnt = 0;
-+
-+				#ifdef CONFIG_RTW_MESH
-+				if (MLME_IS_MESH(padapter)) {
-+					/* TODO: multiple GK? */
-+					prwskey = &stainfo->gtk.skey[0];
-+				} else
-+				#endif
-+				{
-+					prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;
-+					if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) {
-+						RTW_DBG("not match packet_index=%d, install_index=%d\n"
-+							, prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid);
-+						res = _FAIL;
-+						goto exit;
-+					}
-+				}
-+			} else
-+				prwskey = &stainfo->dot118021x_UncstKey.skey[0];
-+
-+			res = _rtw_gcmp_decrypt(prwskey,
-+				prxattrib->encrypt == _GCMP_256_ ? 32 : 16,
-+				prxattrib->hdrlen, pframe,
-+				((union recv_frame *)precvframe)->u.hdr.len);
-+
-+			GCMP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
-+		} else {
-+			res = _FAIL;
-+		}
-+
-+	}
-+exit:
-+	return res;
-+}
-+
-+
-+#ifdef CONFIG_IEEE80211W
-+u8 rtw_calculate_bip_mic(enum security_type gmcs, u8 *whdr_pos, s32 len,
-+	const u8 *key, const u8 *data, size_t data_len, u8 *mic)
-+{
-+	u8 res = _SUCCESS;
-+
-+	if (gmcs == _BIP_CMAC_128_) {
-+		if (_bip_ccmp_protect(key, 16, data, data_len, mic) == _FALSE) {
-+			res = _FAIL;
-+			RTW_ERR("%s : _bip_ccmp_protect(128) fail!", __func__);
-+		}
-+	} else if (gmcs == _BIP_CMAC_256_) {
-+		if (_bip_ccmp_protect(key, 32, data, data_len, mic) == _FALSE) {
-+			res = _FAIL;
-+			RTW_ERR("%s : _bip_ccmp_protect(256) fail!", __func__);
-+		}
-+	} else if (gmcs == _BIP_GMAC_128_) {
-+		if (_bip_gcmp_protect(whdr_pos, len, key, 16,
-+				data, data_len, mic) == _FALSE) {
-+			res = _FAIL;
-+			RTW_ERR("%s : _bip_gcmp_protect(128) fail!", __func__);
-+		}
-+	} else if (gmcs == _BIP_GMAC_256_) {
-+		if (_bip_gcmp_protect(whdr_pos, len, key, 32,
-+				data, data_len, mic) == _FALSE) {
-+			res = _FAIL;
-+			RTW_ERR("%s : _bip_gcmp_protect(256) fail!", __func__);
-+		}
-+	} else {
-+		res = _FAIL;
-+		RTW_ERR("%s : unsupport dot11wCipher !\n", __func__);
-+	}
-+
-+	return res;
-+}
-+
-+
-+u32 rtw_bip_verify(enum security_type gmcs, u16 pkt_len,
-+	u8 *whdr_pos, sint flen, const u8 *key, u16 keyid, u64 *ipn)
-+{
-+	u8 * BIP_AAD,*mme;
-+	u32 res = _FAIL;
-+	uint len, ori_len;
-+	u16 pkt_keyid = 0;
-+	u64 pkt_ipn = 0;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	u8 mic[16];
-+	u8 mic_len, mme_offset;
-+
-+	mic_len = (gmcs == _BIP_CMAC_128_) ? 8 : 16;
-+
-+	if (flen < WLAN_HDR_A3_LEN || flen - WLAN_HDR_A3_LEN < mic_len)
-+		return RTW_RX_HANDLED;
-+
-+	mme_offset = (mic_len == 8) ? 18 : 26;
-+	mme = whdr_pos + flen - mme_offset;
-+	if (*mme != _MME_IE_)
-+		return RTW_RX_HANDLED;
-+
-+	/* copy key index */
-+	_rtw_memcpy(&pkt_keyid, mme + 2, 2);
-+	pkt_keyid = le16_to_cpu(pkt_keyid);
-+	if (pkt_keyid != keyid) {
-+		RTW_INFO("BIP key index error!\n");
-+		return _FAIL;
-+	}
-+
-+	/* save packet number */
-+	_rtw_memcpy(&pkt_ipn, mme + 4, 6);
-+	pkt_ipn = le64_to_cpu(pkt_ipn);
-+	/* BIP packet number should bigger than previous BIP packet */
-+	if (pkt_ipn <= *ipn) { /* wrap around? */
-+		RTW_INFO("replay BIP packet\n");
-+		return _FAIL;
-+	}
-+
-+	ori_len = flen - WLAN_HDR_A3_LEN + BIP_AAD_SIZE;
-+	BIP_AAD = rtw_zmalloc(ori_len);
-+	if (BIP_AAD == NULL) {
-+		RTW_INFO("BIP AAD allocate fail\n");
-+		return _FAIL;
-+	}
-+
-+	/* mapping to wlan header */
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)whdr_pos;
-+
-+	/* save the frame body + MME (w/o mic) */
-+	_rtw_memcpy(BIP_AAD + BIP_AAD_SIZE,
-+		whdr_pos + WLAN_HDR_A3_LEN,
-+		flen - WLAN_HDR_A3_LEN - mic_len);
-+
-+	/* conscruct AAD, copy frame control field */
-+	_rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2);
-+	ClearRetry(BIP_AAD);
-+	ClearPwrMgt(BIP_AAD);
-+	ClearMData(BIP_AAD);
-+	/* conscruct AAD, copy address 1 to address 3 */
-+	_rtw_memcpy(BIP_AAD + 2, GetAddr1Ptr((u8 *)pwlanhdr), 18);
-+
-+	if (rtw_calculate_bip_mic(gmcs, whdr_pos,
-+			pkt_len, key, BIP_AAD, ori_len, mic) == _FAIL)
-+		goto BIP_exit;
-+
-+	/* MIC field should be last 8 bytes of packet (packet without FCS) */
-+	if (_rtw_memcmp(mic, whdr_pos + flen - mic_len, mic_len)) {
-+		*ipn = pkt_ipn;
-+		res = _SUCCESS;
-+	} else
-+		RTW_INFO("BIP MIC error!\n");
-+
-+#if 0
-+	/* management packet content */
-+	{
-+		int pp;
-+		RTW_INFO("pkt: ");
-+		RTW_INFO_DUMP("", whdr_pos, flen);
-+		RTW_INFO("\n");
-+		/* BIP AAD + management frame body + MME(MIC is zero) */
-+		RTW_INFO("AAD+PKT: ");
-+		RTW_INFO_DUMP("", BIP_AAD, ori_len);
-+		RTW_INFO("\n");
-+		/* show the MIC result */
-+		RTW_INFO("mic: ");
-+		RTW_INFO_DUMP("", mic, mic_len);
-+		RTW_INFO("\n");
-+	}
-+#endif
-+
-+BIP_exit:
-+
-+	rtw_mfree(BIP_AAD, ori_len);
-+	return res;
-+}
-+
-+#endif /* CONFIG_IEEE80211W */
-+
-diff --git a/drivers/staging/rtl8723cs/core/rtw_sreset.c b/drivers/staging/rtl8723cs/core/rtw_sreset.c
-new file mode 100644
-index 000000000000..21cc18bc4f5d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_sreset.c
-@@ -0,0 +1,320 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+#include <rtw_sreset.h>
-+
-+void sreset_init_value(_adapter *padapter)
-+{
-+#if defined(DBG_CONFIG_ERROR_DETECT)
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
-+
-+	_rtw_mutex_init(&psrtpriv->silentreset_mutex);
-+	psrtpriv->silent_reset_inprogress = _FALSE;
-+	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
-+	psrtpriv->last_tx_time = 0;
-+	psrtpriv->last_tx_complete_time = 0;
-+#endif
-+}
-+void sreset_reset_value(_adapter *padapter)
-+{
-+#if defined(DBG_CONFIG_ERROR_DETECT)
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
-+
-+	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
-+	psrtpriv->last_tx_time = 0;
-+	psrtpriv->last_tx_complete_time = 0;
-+#endif
-+}
-+
-+u8 sreset_get_wifi_status(_adapter *padapter)
-+{
-+#if defined(DBG_CONFIG_ERROR_DETECT)
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
-+	u8 status = WIFI_STATUS_SUCCESS;
-+	u32 val32 = 0;
-+
-+	if (psrtpriv->silent_reset_inprogress == _TRUE)
-+		return status;
-+	val32 = rtw_read32(padapter, REG_TXDMA_STATUS);
-+	if (val32 == 0xeaeaeaea)
-+		psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST;
-+	else if (val32 != 0) {
-+		RTW_INFO("txdmastatu(%x)\n", val32);
-+		psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR;
-+	}
-+
-+	if (WIFI_STATUS_SUCCESS != psrtpriv->Wifi_Error_Status) {
-+		RTW_INFO("==>%s error_status(0x%x)\n", __FUNCTION__, psrtpriv->Wifi_Error_Status);
-+		status = (psrtpriv->Wifi_Error_Status & (~(USB_READ_PORT_FAIL | USB_WRITE_PORT_FAIL)));
-+	}
-+	RTW_INFO("==> %s wifi_status(0x%x)\n", __FUNCTION__, status);
-+
-+	/* status restore */
-+	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
-+
-+	return status;
-+#else
-+	return WIFI_STATUS_SUCCESS;
-+#endif
-+}
-+
-+void sreset_set_wifi_error_status(_adapter *padapter, u32 status)
-+{
-+#if defined(DBG_CONFIG_ERROR_DETECT)
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	pHalData->srestpriv.Wifi_Error_Status = status;
-+#endif
-+}
-+
-+void sreset_set_trigger_point(_adapter *padapter, s32 tgp)
-+{
-+#if defined(DBG_CONFIG_ERROR_DETECT)
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	pHalData->srestpriv.dbg_trigger_point = tgp;
-+#endif
-+}
-+
-+bool sreset_inprogress(_adapter *padapter)
-+{
-+#if defined(DBG_CONFIG_ERROR_RESET)
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	return pHalData->srestpriv.silent_reset_inprogress;
-+#else
-+	return _FALSE;
-+#endif
-+}
-+
-+void sreset_restore_security_station(_adapter *padapter)
-+{
-+	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *psta;
-+	struct mlme_ext_info	*pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
-+
-+	{
-+		u8 val8;
-+
-+		if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) {
-+			val8 = 0xcc;
-+#ifdef CONFIG_WAPI_SUPPORT
-+		} else if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) {
-+			/* Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey. */
-+			val8 = 0x4c;
-+#endif
-+		} else
-+			val8 = 0xcf;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
-+	}
-+
-+	if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
-+	    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {
-+		psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv));
-+		if (psta == NULL) {
-+			/* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */
-+		} else {
-+			/* pairwise key */
-+			rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE);
-+			/* group key */
-+			rtw_set_key(padapter, &padapter->securitypriv, padapter->securitypriv.dot118021XGrpKeyid, 0, _FALSE);
-+		}
-+	}
-+}
-+
-+void sreset_restore_network_station(_adapter *padapter)
-+{
-+	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 doiqk = _FALSE;
-+
-+	rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY);
-+
-+	{
-+		u8 threshold;
-+#ifdef CONFIG_USB_HCI
-+		/* TH=1 => means that invalidate usb rx aggregation */
-+		/* TH=0 => means that validate usb rx aggregation, use init value. */
-+#ifdef CONFIG_80211N_HT
-+		if (mlmepriv->htpriv.ht_option) {
-+			if (padapter->registrypriv.wifi_spec == 1)
-+				threshold = 1;
-+			else
-+				threshold = 0;
-+			rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
-+		} else {
-+			threshold = 1;
-+			rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
-+		}
-+#endif /* CONFIG_80211N_HT */
-+#endif
-+	}
-+
-+	doiqk = _TRUE;
-+	rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK , &doiqk);
-+
-+	set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
-+
-+	doiqk = _FALSE;
-+	rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
-+	/* disable dynamic functions, such as high power, DIG */
-+	/*rtw_phydm_func_disable_all(padapter);*/
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
-+
-+	{
-+		u8	join_type = 0;
-+
-+		rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
-+
-+		rtw_btcoex_connect_notify(padapter, join_type);
-+	}
-+
-+	Set_MSR(padapter, (pmlmeinfo->state & 0x3));
-+
-+	mlmeext_joinbss_event_callback(padapter, 1);
-+	/* restore Sequence No. */
-+	rtw_hal_set_hwreg(padapter, HW_VAR_RESTORE_HW_SEQ, 0);
-+
-+	sreset_restore_security_station(padapter);
-+}
-+
-+
-+void sreset_restore_network_status(_adapter *padapter)
-+{
-+	struct mlme_priv *mlmepriv = &padapter->mlmepriv;
-+
-+	if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) {
-+		RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
-+		sreset_restore_network_station(padapter);
-+	}
-+#ifdef CONFIG_AP_MODE
-+	else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
-+		RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(padapter), MLME_IS_AP(padapter) ? "AP" : "MESH");
-+		rtw_ap_restore_network(padapter);
-+	}
-+#endif
-+	else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE))
-+		RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
-+	else
-+		RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
-+}
-+
-+void sreset_stop_adapter(_adapter *padapter)
-+{
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
-+
-+	if (padapter == NULL)
-+		return;
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+
-+	rtw_netif_stop_queue(padapter->pnetdev);
-+
-+	rtw_cancel_all_timer(padapter);
-+
-+	/* TODO: OS and HCI independent */
-+#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
-+	tasklet_kill(&pxmitpriv->xmit_tasklet);
-+#endif
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY))
-+		rtw_scan_abort(padapter);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING)) {
-+		rtw_set_to_roam(padapter, 0);
-+		rtw_join_timeout_handler(padapter);
-+	}
-+
-+}
-+
-+void sreset_start_adapter(_adapter *padapter)
-+{
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
-+
-+	if (padapter == NULL)
-+		return;
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
-+		sreset_restore_network_status(padapter);
-+
-+	/* TODO: OS and HCI independent */
-+#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
-+	tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
-+#endif
-+
-+	if (is_primary_adapter(padapter))
-+		_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
-+
-+	rtw_netif_wake_queue(padapter->pnetdev);
-+}
-+
-+void sreset_reset(_adapter *padapter)
-+{
-+#ifdef DBG_CONFIG_ERROR_RESET
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
-+	_irqL irqL;
-+	systime start = rtw_get_current_time();
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
-+
-+
-+#ifdef CONFIG_LPS
-+	rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "SRESET");
-+#endif/* #ifdef CONFIG_LPS */
-+
-+	_enter_pwrlock(&pwrpriv->lock);
-+
-+	psrtpriv->silent_reset_inprogress = _TRUE;
-+	pwrpriv->change_rfpwrstate = rf_off;
-+
-+	rtw_mi_sreset_adapter_hdl(padapter, _FALSE);/*sreset_stop_adapter*/
-+#ifdef CONFIG_IPS
-+	_ips_enter(padapter);
-+	_ips_leave(padapter);
-+#endif
-+#if defined(CONFIG_AP_MODE) && defined(CONFIG_CONCURRENT_MODE)
-+	rtw_mi_ap_info_restore(padapter);
-+#endif
-+	rtw_mi_sreset_adapter_hdl(padapter, _TRUE);/*sreset_start_adapter*/
-+
-+	psrtpriv->silent_reset_inprogress = _FALSE;
-+
-+	_exit_pwrlock(&pwrpriv->lock);
-+
-+	RTW_INFO("%s done in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
-+	pdbgpriv->dbg_sreset_cnt++;
-+
-+	psrtpriv->self_dect_fw = _FALSE;
-+	psrtpriv->rx_cnt = 0;
-+#endif
-+}
-diff --git a/drivers/staging/rtl8723cs/core/rtw_sta_mgt.c b/drivers/staging/rtl8723cs/core/rtw_sta_mgt.c
-new file mode 100644
-index 000000000000..28a76fd9749a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_sta_mgt.c
-@@ -0,0 +1,1369 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_STA_MGT_C_
-+
-+#include <drv_types.h>
-+
-+bool test_st_match_rule(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
-+{
-+	if (ntohs(*((u16 *)local_port)) == 5001 || ntohs(*((u16 *)remote_port)) == 5001)
-+		return _TRUE;
-+	return _FALSE;
-+}
-+
-+struct st_register test_st_reg = {
-+	.s_proto = 0x06,
-+	.rule = test_st_match_rule,
-+};
-+
-+inline void rtw_st_ctl_init(struct st_ctl_t *st_ctl)
-+{
-+	_rtw_memset(st_ctl->reg, 0 , sizeof(struct st_register) * SESSION_TRACKER_REG_ID_NUM);
-+	_rtw_init_queue(&st_ctl->tracker_q);
-+}
-+
-+inline void rtw_st_ctl_clear_tracker_q(struct st_ctl_t *st_ctl)
-+{
-+	_irqL irqL;
-+	_list *plist, *phead;
-+	struct session_tracker *st;
-+
-+	_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
-+	phead = &st_ctl->tracker_q.queue;
-+	plist = get_next(phead);
-+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+		st = LIST_CONTAINOR(plist, struct session_tracker, list);
-+		plist = get_next(plist);
-+		rtw_list_delete(&st->list);
-+		rtw_mfree((u8 *)st, sizeof(struct session_tracker));
-+	}
-+	_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
-+}
-+
-+inline void rtw_st_ctl_deinit(struct st_ctl_t *st_ctl)
-+{
-+	rtw_st_ctl_clear_tracker_q(st_ctl);
-+	_rtw_deinit_queue(&st_ctl->tracker_q);
-+}
-+
-+inline void rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_register *reg)
-+{
-+	if (st_reg_id >= SESSION_TRACKER_REG_ID_NUM) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	st_ctl->reg[st_reg_id].s_proto = reg->s_proto;
-+	st_ctl->reg[st_reg_id].rule = reg->rule;
-+}
-+
-+inline void rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id)
-+{
-+	int i;
-+
-+	if (st_reg_id >= SESSION_TRACKER_REG_ID_NUM) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	st_ctl->reg[st_reg_id].s_proto = 0;
-+	st_ctl->reg[st_reg_id].rule = NULL;
-+
-+	/* clear tracker queue if no session trecker registered */
-+	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++)
-+		if (st_ctl->reg[i].s_proto != 0)
-+			break;
-+	if (i >= SESSION_TRACKER_REG_ID_NUM)
-+		rtw_st_ctl_clear_tracker_q(st_ctl);
-+}
-+
-+inline bool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto)
-+{
-+	bool ret = _FALSE;
-+	int i;
-+
-+	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) {
-+		if (st_ctl->reg[i].s_proto == s_proto) {
-+			ret = _TRUE;
-+			break;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+inline bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
-+{
-+	bool ret = _FALSE;
-+	int i;
-+	st_match_rule rule;
-+
-+	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) {
-+		rule = st_ctl->reg[i].rule;
-+		if (rule && rule(adapter, local_naddr, local_port, remote_naddr, remote_port) == _TRUE) {
-+			ret = _TRUE;
-+			break;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+void rtw_st_ctl_rx(struct sta_info *sta, u8 *ehdr_pos)
-+{
-+	_adapter *adapter = sta->padapter;
-+	struct ethhdr *etherhdr = (struct ethhdr *)ehdr_pos;
-+
-+	if (ntohs(etherhdr->h_proto) == ETH_P_IP) {
-+		u8 *ip = ehdr_pos + ETH_HLEN;
-+
-+		if (GET_IPV4_PROTOCOL(ip) == 0x06  /* TCP */
-+			&& rtw_st_ctl_chk_reg_s_proto(&sta->st_ctl, 0x06) == _TRUE
-+		) {
-+			u8 *tcp = ip + GET_IPV4_IHL(ip) * 4;
-+
-+			if (rtw_st_ctl_chk_reg_rule(&sta->st_ctl, adapter, IPV4_DST(ip), TCP_DST(tcp), IPV4_SRC(ip), TCP_SRC(tcp)) == _TRUE) {
-+				if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) {
-+					session_tracker_add_cmd(adapter, sta
-+						, IPV4_DST(ip), TCP_DST(tcp)
-+						, IPV4_SRC(ip), TCP_SRC(tcp));
-+					if (DBG_SESSION_TRACKER)
-+						RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n"
-+							, FUNC_ADPT_ARG(adapter)
-+							, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))
-+							, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)));
-+				}
-+				if (GET_TCP_FIN(tcp)) {
-+					session_tracker_del_cmd(adapter, sta
-+						, IPV4_DST(ip), TCP_DST(tcp)
-+						, IPV4_SRC(ip), TCP_SRC(tcp));
-+					if (DBG_SESSION_TRACKER)
-+						RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n"
-+							, FUNC_ADPT_ARG(adapter)
-+							, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))
-+							, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)));
-+				}
-+			}
-+
-+		}
-+	}
-+}
-+
-+#define SESSION_TRACKER_FMT IP_FMT":"PORT_FMT" "IP_FMT":"PORT_FMT" %u %d"
-+#define SESSION_TRACKER_ARG(st) IP_ARG(&(st)->local_naddr), PORT_ARG(&(st)->local_port), IP_ARG(&(st)->remote_naddr), PORT_ARG(&(st)->remote_port), (st)->status, rtw_get_passing_time_ms((st)->set_time)
-+
-+void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl)
-+{
-+	int i;
-+	_irqL irqL;
-+	_list *plist, *phead;
-+	struct session_tracker *st;
-+
-+	if (!DBG_SESSION_TRACKER)
-+		return;
-+
-+	for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++)
-+		RTW_PRINT_SEL(sel, "reg%d: %u %p\n", i, st_ctl->reg[i].s_proto, st_ctl->reg[i].rule);
-+
-+	_enter_critical_bh(&st_ctl->tracker_q.lock, &irqL);
-+	phead = &st_ctl->tracker_q.queue;
-+	plist = get_next(phead);
-+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+		st = LIST_CONTAINOR(plist, struct session_tracker, list);
-+		plist = get_next(plist);
-+
-+		RTW_PRINT_SEL(sel, SESSION_TRACKER_FMT"\n", SESSION_TRACKER_ARG(st));
-+	}
-+	_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
-+
-+}
-+
-+void _rtw_init_stainfo(struct sta_info *psta);
-+void _rtw_init_stainfo(struct sta_info *psta)
-+{
-+	_rtw_memset((u8 *)psta, 0, sizeof(struct sta_info));
-+
-+	_rtw_spinlock_init(&psta->lock);
-+	_rtw_init_listhead(&psta->list);
-+	_rtw_init_listhead(&psta->hash_list);
-+	/* _rtw_init_listhead(&psta->asoc_list); */
-+	/* _rtw_init_listhead(&psta->sleep_list); */
-+	/* _rtw_init_listhead(&psta->wakeup_list);	 */
-+
-+	_rtw_init_queue(&psta->sleep_q);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	_rtw_init_queue(&psta->mgmt_sleep_q);
-+#endif
-+	_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
-+	_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
-+
-+#ifdef CONFIG_AP_MODE
-+	_rtw_init_listhead(&psta->asoc_list);
-+	_rtw_init_listhead(&psta->auth_list);
-+	psta->bpairwise_key_installed = _FALSE;
-+
-+#ifdef CONFIG_RTW_80211R
-+	psta->ft_pairwise_key_installed = _FALSE;
-+#endif
-+#endif /* CONFIG_AP_MODE	 */
-+
-+	rtw_st_ctl_init(&psta->st_ctl);
-+}
-+
-+u32	_rtw_init_sta_priv(struct	sta_priv *pstapriv)
-+{
-+	_adapter *adapter = container_of(pstapriv, _adapter, stapriv);
-+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
-+	struct sta_info *psta;
-+	s32 i;
-+	u32 ret = _FAIL;
-+
-+	pstapriv->padapter = adapter;
-+
-+	pstapriv->pallocated_stainfo_buf = rtw_zvmalloc(
-+		sizeof(struct sta_info) * NUM_STA + MEM_ALIGNMENT_OFFSET);
-+	if (!pstapriv->pallocated_stainfo_buf)
-+		goto exit;
-+
-+	pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf;
-+	if ((SIZE_PTR)pstapriv->pstainfo_buf & MEM_ALIGNMENT_PADDING)
-+		pstapriv->pstainfo_buf += MEM_ALIGNMENT_OFFSET -
-+			((SIZE_PTR)pstapriv->pstainfo_buf & MEM_ALIGNMENT_PADDING);
-+
-+	_rtw_init_queue(&pstapriv->free_sta_queue);
-+
-+	_rtw_spinlock_init(&pstapriv->sta_hash_lock);
-+
-+	/* _rtw_init_queue(&pstapriv->asoc_q); */
-+	pstapriv->asoc_sta_count = 0;
-+	_rtw_init_queue(&pstapriv->sleep_q);
-+	_rtw_init_queue(&pstapriv->wakeup_q);
-+
-+	psta = (struct sta_info *)(pstapriv->pstainfo_buf);
-+
-+
-+	for (i = 0; i < NUM_STA; i++) {
-+		_rtw_init_stainfo(psta);
-+
-+		_rtw_init_listhead(&(pstapriv->sta_hash[i]));
-+
-+		rtw_list_insert_tail(&psta->list, get_list_head(&pstapriv->free_sta_queue));
-+
-+		psta++;
-+	}
-+
-+	pstapriv->adhoc_expire_to = 4; /* 4 * 2 = 8 sec */
-+
-+#ifdef CONFIG_AP_MODE
-+	pstapriv->max_aid = macid_ctl->num;
-+	pstapriv->rr_aid = 0;
-+	pstapriv->started_aid = 1;
-+	pstapriv->sta_aid = rtw_zmalloc(pstapriv->max_aid * sizeof(struct sta_info *));
-+	if (!pstapriv->sta_aid)
-+		goto exit;
-+	pstapriv->aid_bmp_len = AID_BMP_LEN(pstapriv->max_aid);
-+	pstapriv->sta_dz_bitmap = rtw_zmalloc(pstapriv->aid_bmp_len);
-+	if (!pstapriv->sta_dz_bitmap)
-+		goto exit;
-+	pstapriv->tim_bitmap = rtw_zmalloc(pstapriv->aid_bmp_len);
-+	if (!pstapriv->tim_bitmap)
-+		goto exit;
-+
-+	_rtw_init_listhead(&pstapriv->asoc_list);
-+	_rtw_init_listhead(&pstapriv->auth_list);
-+	_rtw_spinlock_init(&pstapriv->asoc_list_lock);
-+	_rtw_spinlock_init(&pstapriv->auth_list_lock);
-+	pstapriv->asoc_list_cnt = 0;
-+	pstapriv->auth_list_cnt = 0;
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	pstapriv->tbtx_asoc_list_cnt = 0;
-+#endif
-+
-+	pstapriv->auth_to = 3; /* 3*2 = 6 sec */
-+	pstapriv->assoc_to = 3;
-+	/* pstapriv->expire_to = 900; */ /* 900*2 = 1800 sec = 30 min, expire after no any traffic. */
-+	/* pstapriv->expire_to = 30; */ /* 30*2 = 60 sec = 1 min, expire after no any traffic. */
-+#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-+	pstapriv->expire_to = 3; /* 3*2 = 6 sec */
-+#else
-+	pstapriv->expire_to = 60;/* 60*2 = 120 sec = 2 min, expire after no any traffic. */
-+#endif
-+#ifdef CONFIG_ATMEL_RC_PATCH
-+	_rtw_memset(pstapriv->atmel_rc_pattern, 0, ETH_ALEN);
-+#endif
-+	pstapriv->max_num_sta = NUM_STA;
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+	for (i = 0; i < RTW_ACL_PERIOD_NUM; i++)
-+		rtw_macaddr_acl_init(adapter, i);
-+#endif
-+#endif /* CONFIG_AP_MODE */
-+
-+#if CONFIG_RTW_PRE_LINK_STA
-+	rtw_pre_link_sta_ctl_init(pstapriv);
-+#endif
-+
-+#if defined(DBG_ROAMING_TEST) || defined(CONFIG_RTW_REPEATER_SON)
-+	rtw_set_rx_chk_limit(adapter,1);
-+#elif defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && !defined(CONFIG_LPS_LCLK_WD_TIMER)
-+	rtw_set_rx_chk_limit(adapter,4);
-+#else
-+	rtw_set_rx_chk_limit(adapter,8);
-+#endif
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	if (ret != _SUCCESS) {
-+		if (pstapriv->pallocated_stainfo_buf)
-+			rtw_vmfree(pstapriv->pallocated_stainfo_buf,
-+				sizeof(struct sta_info) * NUM_STA + MEM_ALIGNMENT_OFFSET);
-+		#ifdef CONFIG_AP_MODE
-+		if (pstapriv->sta_aid)
-+			rtw_mfree(pstapriv->sta_aid, pstapriv->max_aid * sizeof(struct sta_info *));
-+		if (pstapriv->sta_dz_bitmap)
-+			rtw_mfree(pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
-+		#endif
-+	}
-+
-+	return ret;
-+}
-+
-+inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta)
-+{
-+	int offset = (((u8 *)sta) - stapriv->pstainfo_buf) / sizeof(struct sta_info);
-+
-+	if (!stainfo_offset_valid(offset))
-+		RTW_INFO("%s invalid offset(%d), out of range!!!", __func__, offset);
-+
-+	return offset;
-+}
-+
-+inline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset)
-+{
-+	if (!stainfo_offset_valid(offset))
-+		RTW_INFO("%s invalid offset(%d), out of range!!!", __func__, offset);
-+
-+	return (struct sta_info *)(stapriv->pstainfo_buf + offset * sizeof(struct sta_info));
-+}
-+
-+void	_rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv);
-+void	_rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv)
-+{
-+
-+	_rtw_spinlock_free(&psta_xmitpriv->lock);
-+
-+	_rtw_spinlock_free(&(psta_xmitpriv->be_q.sta_pending.lock));
-+	_rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock));
-+	_rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock));
-+	_rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock));
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	_rtw_spinlock_free(&(psta_xmitpriv->mgmt_q.sta_pending.lock));
-+#endif
-+}
-+
-+static void	_rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv)
-+{
-+
-+	_rtw_spinlock_free(&psta_recvpriv->lock);
-+
-+	_rtw_spinlock_free(&(psta_recvpriv->defrag_q.lock));
-+
-+
-+}
-+
-+void rtw_mfree_stainfo(struct sta_info *psta);
-+void rtw_mfree_stainfo(struct sta_info *psta)
-+{
-+
-+	if (&psta->lock != NULL)
-+		_rtw_spinlock_free(&psta->lock);
-+
-+	_rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv);
-+	_rtw_free_sta_recv_priv_lock(&psta->sta_recvpriv);
-+
-+}
-+
-+
-+/* this function is used to free the memory of lock || sema for all stainfos */
-+void rtw_mfree_all_stainfo(struct sta_priv *pstapriv);
-+void rtw_mfree_all_stainfo(struct sta_priv *pstapriv)
-+{
-+	_irqL	 irqL;
-+	_list	*plist, *phead;
-+	struct sta_info *psta = NULL;
-+
-+
-+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+	phead = get_list_head(&pstapriv->free_sta_queue);
-+	plist = get_next(phead);
-+
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+		psta = LIST_CONTAINOR(plist, struct sta_info , list);
-+		plist = get_next(plist);
-+
-+		rtw_mfree_stainfo(psta);
-+	}
-+
-+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+
-+}
-+
-+void rtw_mfree_sta_priv_lock(struct	sta_priv *pstapriv);
-+void rtw_mfree_sta_priv_lock(struct	sta_priv *pstapriv)
-+{
-+	rtw_mfree_all_stainfo(pstapriv); /* be done before free sta_hash_lock */
-+
-+	_rtw_spinlock_free(&pstapriv->free_sta_queue.lock);
-+
-+	_rtw_spinlock_free(&pstapriv->sta_hash_lock);
-+	_rtw_spinlock_free(&pstapriv->wakeup_q.lock);
-+	_rtw_spinlock_free(&pstapriv->sleep_q.lock);
-+
-+#ifdef CONFIG_AP_MODE
-+	_rtw_spinlock_free(&pstapriv->asoc_list_lock);
-+	_rtw_spinlock_free(&pstapriv->auth_list_lock);
-+#endif
-+
-+}
-+
-+u32	_rtw_free_sta_priv(struct	sta_priv *pstapriv)
-+{
-+	_irqL	irqL;
-+	_list	*phead, *plist;
-+	struct sta_info *psta = NULL;
-+	struct recv_reorder_ctrl *preorder_ctrl;
-+	int	index;
-+
-+	if (pstapriv) {
-+
-+		/*	delete all reordering_ctrl_timer		*/
-+		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+		for (index = 0; index < NUM_STA; index++) {
-+			phead = &(pstapriv->sta_hash[index]);
-+			plist = get_next(phead);
-+
-+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+				int i;
-+				psta = LIST_CONTAINOR(plist, struct sta_info , hash_list);
-+				plist = get_next(plist);
-+
-+				for (i = 0; i < 16 ; i++) {
-+					preorder_ctrl = &psta->recvreorder_ctrl[i];
-+					_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
-+				}
-+			}
-+		}
-+		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+		/*===============================*/
-+
-+		rtw_mfree_sta_priv_lock(pstapriv);
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+		for (index = 0; index < RTW_ACL_PERIOD_NUM; index++)
-+			rtw_macaddr_acl_deinit(pstapriv->padapter, index);
-+#endif
-+
-+#if CONFIG_RTW_PRE_LINK_STA
-+		rtw_pre_link_sta_ctl_deinit(pstapriv);
-+#endif
-+
-+		if (pstapriv->pallocated_stainfo_buf)
-+			rtw_vmfree(pstapriv->pallocated_stainfo_buf,
-+				sizeof(struct sta_info) * NUM_STA + MEM_ALIGNMENT_OFFSET);
-+		#ifdef CONFIG_AP_MODE
-+		if (pstapriv->sta_aid)
-+			rtw_mfree(pstapriv->sta_aid, pstapriv->max_aid * sizeof(struct sta_info *));
-+		if (pstapriv->sta_dz_bitmap)
-+			rtw_mfree(pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
-+		if (pstapriv->tim_bitmap)
-+			rtw_mfree(pstapriv->tim_bitmap, pstapriv->aid_bmp_len);
-+		#endif
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+
-+static void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl)
-+{
-+	_adapter *padapter = preorder_ctrl->padapter;
-+
-+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
-+	rtw_init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter, rtw_reordering_ctrl_timeout_handler, preorder_ctrl);
-+#endif
-+}
-+
-+/* struct	sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr) */
-+struct	sta_info *rtw_alloc_stainfo(struct	sta_priv *pstapriv, const u8 *hwaddr)
-+{
-+	_irqL irqL2;
-+	s32	index;
-+	_list	*phash_list;
-+	struct sta_info	*psta;
-+	_queue *pfree_sta_queue;
-+	struct recv_reorder_ctrl *preorder_ctrl;
-+	int i = 0;
-+	u16  wRxSeqInitialValue = 0xffff;
-+
-+
-+	pfree_sta_queue = &pstapriv->free_sta_queue;
-+
-+	/* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL); */
-+	_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
-+	if (_rtw_queue_empty(pfree_sta_queue) == _TRUE) {
-+		/* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */
-+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
-+		psta = NULL;
-+	} else {
-+		psta = LIST_CONTAINOR(get_next(&pfree_sta_queue->queue), struct sta_info, list);
-+
-+		rtw_list_delete(&(psta->list));
-+
-+		/* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */
-+		_rtw_init_stainfo(psta);
-+
-+		psta->padapter = pstapriv->padapter;
-+
-+		_rtw_memcpy(psta->cmn.mac_addr, hwaddr, ETH_ALEN);
-+
-+		index = wifi_mac_hash(hwaddr);
-+
-+
-+		if (index >= NUM_STA) {
-+			psta = NULL;
-+			goto exit;
-+		}
-+		phash_list = &(pstapriv->sta_hash[index]);
-+
-+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
-+
-+		rtw_list_insert_tail(&psta->hash_list, phash_list);
-+
-+		pstapriv->asoc_sta_count++;
-+
-+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
-+
-+		/* Commented by Albert 2009/08/13
-+		 * For the SMC router, the sequence number of first packet of WPS handshake will be 0.
-+		 * In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable.
-+		 * So, we initialize the tid_rxseq variable as the 0xffff. */
-+
-+		for (i = 0; i < 16; i++) {
-+			_rtw_memcpy(&psta->sta_recvpriv.rxcache.tid_rxseq[i], &wRxSeqInitialValue, 2);
-+			_rtw_memcpy(&psta->sta_recvpriv.bmc_tid_rxseq[i], &wRxSeqInitialValue, 2);
-+			_rtw_memset(&psta->sta_recvpriv.rxcache.iv[i], 0, sizeof(psta->sta_recvpriv.rxcache.iv[i]));
-+		}
-+		_rtw_memcpy(&psta->sta_recvpriv.nonqos_bmc_rxseq,&wRxSeqInitialValue,2);
-+		_rtw_memcpy(&psta->sta_recvpriv.nonqos_rxseq,&wRxSeqInitialValue,2);
-+
-+		rtw_init_timer(&psta->addba_retry_timer, psta->padapter, addba_timer_hdl, psta);
-+#ifdef CONFIG_IEEE80211W
-+		rtw_init_timer(&psta->dot11w_expire_timer, psta->padapter, sa_query_timer_hdl, psta);
-+#endif /* CONFIG_IEEE80211W */
-+#ifdef CONFIG_TDLS
-+		rtw_init_tdls_timer(pstapriv->padapter, psta);
-+#endif /* CONFIG_TDLS */
-+
-+		/* for A-MPDU Rx reordering buffer control */
-+		for (i = 0; i < 16 ; i++) {
-+			preorder_ctrl = &psta->recvreorder_ctrl[i];
-+			preorder_ctrl->padapter = pstapriv->padapter;
-+			preorder_ctrl->tid = i;
-+			preorder_ctrl->enable = _FALSE;
-+			preorder_ctrl->indicate_seq = 0xffff;
-+			#ifdef DBG_RX_SEQ
-+			RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d\n"
-+				, FUNC_ADPT_ARG(pstapriv->padapter), i, preorder_ctrl->indicate_seq);
-+			#endif
-+			preorder_ctrl->wend_b = 0xffff;
-+			preorder_ctrl->wsize_b = 64;/* 64; */
-+			preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;
-+
-+			_rtw_init_queue(&preorder_ctrl->pending_recvframe_queue);
-+
-+			rtw_init_recv_timer(preorder_ctrl);
-+			rtw_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack);
-+
-+		}
-+
-+
-+		/* init for DM */
-+		psta->cmn.rssi_stat.rssi = (-1);
-+		psta->cmn.rssi_stat.rssi_cck = (-1);
-+		psta->cmn.rssi_stat.rssi_ofdm = (-1);
-+#ifdef CONFIG_ATMEL_RC_PATCH
-+		psta->flag_atmel_rc = 0;
-+#endif
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+		psta->tbtx_enable = _FALSE;
-+#endif
-+		/* init for the sequence number of received management frame */
-+		psta->RxMgmtFrameSeqNum = 0xffff;
-+		_rtw_memset(&psta->sta_stats, 0, sizeof(struct stainfo_stats));
-+
-+		rtw_alloc_macid(pstapriv->padapter, psta);
-+
-+		psta->tx_q_enable = 0;
-+		_rtw_init_queue(&psta->tx_queue);
-+		_init_workitem(&psta->tx_q_work, rtw_xmit_dequeue_callback, NULL);
-+	}
-+
-+exit:
-+
-+	_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
-+
-+
-+	if (psta)
-+		rtw_mi_update_iface_status(&(pstapriv->padapter->mlmepriv), 0);
-+
-+	return psta;
-+}
-+
-+
-+/* using pstapriv->sta_hash_lock to protect */
-+u32	rtw_free_stainfo(_adapter *padapter , struct sta_info *psta)
-+{
-+	int i;
-+	_irqL irqL0;
-+	_queue *pfree_sta_queue;
-+	struct recv_reorder_ctrl *preorder_ctrl;
-+	struct	sta_xmit_priv	*pstaxmitpriv;
-+	struct	xmit_priv	*pxmitpriv = &padapter->xmitpriv;
-+	struct	sta_priv *pstapriv = &padapter->stapriv;
-+	struct hw_xmit *phwxmit;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	int pending_qcnt[4];
-+	u8 is_pre_link_sta = _FALSE;
-+
-+	if (psta == NULL)
-+		goto exit;
-+
-+#ifdef CONFIG_RTW_80211K
-+	rm_post_event(padapter, RM_ID_FOR_ALL(psta->cmn.aid), RM_EV_cancel);
-+#endif
-+
-+	is_pre_link_sta = rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr);
-+
-+	if (is_pre_link_sta == _FALSE) {
-+		_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
-+		rtw_list_delete(&psta->hash_list);
-+		pstapriv->asoc_sta_count--;
-+		_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
-+		rtw_mi_update_iface_status(&(padapter->mlmepriv), 0);
-+	} else {
-+		_enter_critical_bh(&psta->lock, &irqL0);
-+		psta->state = WIFI_FW_PRE_LINK;
-+		_exit_critical_bh(&psta->lock, &irqL0);
-+	}
-+
-+	_enter_critical_bh(&psta->lock, &irqL0);
-+	psta->state &= ~WIFI_ASOC_STATE;
-+	_exit_critical_bh(&psta->lock, &irqL0);
-+
-+	pfree_sta_queue = &pstapriv->free_sta_queue;
-+
-+
-+	pstaxmitpriv = &psta->sta_xmitpriv;
-+
-+	/* rtw_list_delete(&psta->sleep_list); */
-+
-+	/* rtw_list_delete(&psta->wakeup_list); */
-+
-+	rtw_free_xmitframe_queue(pxmitpriv, &psta->tx_queue);
-+	_rtw_deinit_queue(&psta->tx_queue);
-+
-+	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
-+
-+	rtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q);
-+	psta->sleepq_len = 0;
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	rtw_free_mgmt_xmitframe_queue(pxmitpriv, &psta->mgmt_sleep_q);
-+	psta->mgmt_sleepq_len = 0;
-+#endif
-+
-+	/* vo */
-+	/* _enter_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); */
-+	rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vo_q.sta_pending);
-+	rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
-+	phwxmit = pxmitpriv->hwxmits;
-+	phwxmit->accnt -= pstaxmitpriv->vo_q.qcnt;
-+	pending_qcnt[0] = pstaxmitpriv->vo_q.qcnt;
-+	pstaxmitpriv->vo_q.qcnt = 0;
-+	/* _exit_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); */
-+
-+	/* vi */
-+	/* _enter_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); */
-+	rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vi_q.sta_pending);
-+	rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
-+	phwxmit = pxmitpriv->hwxmits + 1;
-+	phwxmit->accnt -= pstaxmitpriv->vi_q.qcnt;
-+	pending_qcnt[1] = pstaxmitpriv->vi_q.qcnt;
-+	pstaxmitpriv->vi_q.qcnt = 0;
-+	/* _exit_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); */
-+
-+	/* be */
-+	/* _enter_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); */
-+	rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->be_q.sta_pending);
-+	rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
-+	phwxmit = pxmitpriv->hwxmits + 2;
-+	phwxmit->accnt -= pstaxmitpriv->be_q.qcnt;
-+	pending_qcnt[2] = pstaxmitpriv->be_q.qcnt;
-+	pstaxmitpriv->be_q.qcnt = 0;
-+	/* _exit_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); */
-+
-+	/* bk */
-+	/* _enter_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); */
-+	rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->bk_q.sta_pending);
-+	rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
-+	phwxmit = pxmitpriv->hwxmits + 3;
-+	phwxmit->accnt -= pstaxmitpriv->bk_q.qcnt;
-+	pending_qcnt[3] = pstaxmitpriv->bk_q.qcnt;
-+	pstaxmitpriv->bk_q.qcnt = 0;
-+	/* _exit_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); */
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	/* mgmt */
-+	rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->mgmt_q.sta_pending);
-+	rtw_list_delete(&(pstaxmitpriv->mgmt_q.tx_pending));
-+	phwxmit = pxmitpriv->hwxmits + 4;
-+	phwxmit->accnt -= pstaxmitpriv->mgmt_q.qcnt;
-+	pstaxmitpriv->mgmt_q.qcnt = 0;
-+#endif
-+
-+	rtw_os_wake_queue_at_free_stainfo(padapter, pending_qcnt);
-+
-+	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
-+
-+
-+	/* re-init sta_info; 20061114 */ /* will be init in alloc_stainfo */
-+	/* _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); */
-+	/* _rtw_init_sta_recv_priv(&psta->sta_recvpriv); */
-+#ifdef CONFIG_IEEE80211W
-+	_cancel_timer_ex(&psta->dot11w_expire_timer);
-+#endif /* CONFIG_IEEE80211W */
-+	_cancel_timer_ex(&psta->addba_retry_timer);
-+
-+#ifdef CONFIG_TDLS
-+	psta->tdls_sta_state = TDLS_STATE_NONE;
-+#endif /* CONFIG_TDLS */
-+
-+	/* for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer */
-+	for (i = 0; i < 16 ; i++) {
-+		_irqL irqL;
-+		_list	*phead, *plist;
-+		union recv_frame *prframe;
-+		_queue *ppending_recvframe_queue;
-+		_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
-+
-+		preorder_ctrl = &psta->recvreorder_ctrl[i];
-+		rtw_clear_bit(RTW_RECV_ACK_OR_TIMEOUT, &preorder_ctrl->rec_abba_rsp_ack);
-+		
-+		_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
-+
-+
-+		ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
-+
-+		_enter_critical_bh(&ppending_recvframe_queue->lock, &irqL);
-+
-+		phead =	get_list_head(ppending_recvframe_queue);
-+		plist = get_next(phead);
-+
-+		while (!rtw_is_list_empty(phead)) {
-+			prframe = LIST_CONTAINOR(plist, union recv_frame, u);
-+
-+			plist = get_next(plist);
-+
-+			rtw_list_delete(&(prframe->u.hdr.list));
-+
-+			rtw_free_recvframe(prframe, pfree_recv_queue);
-+		}
-+
-+		_exit_critical_bh(&ppending_recvframe_queue->lock, &irqL);
-+
-+	}
-+
-+	if (!((psta->state & WIFI_AP_STATE) || MacAddr_isBcst(psta->cmn.mac_addr)) && is_pre_link_sta == _FALSE)
-+		rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _FALSE);
-+
-+
-+	/* release mac id for non-bc/mc station, */
-+	if (is_pre_link_sta == _FALSE)
-+		rtw_release_macid(pstapriv->padapter, psta);
-+
-+#ifdef CONFIG_AP_MODE
-+
-+	/*
-+		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
-+		rtw_list_delete(&psta->asoc_list);
-+		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
-+	*/
-+	_enter_critical_bh(&pstapriv->auth_list_lock, &irqL0);
-+	if (!rtw_is_list_empty(&psta->auth_list)) {
-+		rtw_list_delete(&psta->auth_list);
-+		pstapriv->auth_list_cnt--;
-+	}
-+	_exit_critical_bh(&pstapriv->auth_list_lock, &irqL0);
-+
-+	psta->expire_to = 0;
-+#ifdef CONFIG_ATMEL_RC_PATCH
-+	psta->flag_atmel_rc = 0;
-+#endif
-+	psta->sleepq_ac_len = 0;
-+	psta->qos_info = 0;
-+
-+	psta->max_sp_len = 0;
-+	psta->uapsd_bk = 0;
-+	psta->uapsd_be = 0;
-+	psta->uapsd_vi = 0;
-+	psta->uapsd_vo = 0;
-+
-+	psta->has_legacy_ac = 0;
-+
-+#ifdef CONFIG_NATIVEAP_MLME
-+
-+	if (pmlmeinfo->state == _HW_STATE_AP_) {
-+		rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);
-+		rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
-+
-+		/* rtw_indicate_sta_disassoc_event(padapter, psta); */
-+
-+		if ((psta->cmn.aid > 0) && (pstapriv->sta_aid[psta->cmn.aid - 1] == psta)) {
-+			pstapriv->sta_aid[psta->cmn.aid - 1] = NULL;
-+			psta->cmn.aid = 0;
-+		}
-+	}
-+
-+#endif /* CONFIG_NATIVEAP_MLME	 */
-+
-+#if !defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && defined(CONFIG_80211N_HT)
-+	psta->under_exist_checking = 0;
-+#endif
-+
-+#endif /* CONFIG_AP_MODE	 */
-+
-+	rtw_st_ctl_deinit(&psta->st_ctl);
-+
-+	if (is_pre_link_sta == _FALSE) {
-+		_rtw_spinlock_free(&psta->lock);
-+
-+		/* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL0); */
-+		_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
-+		rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue));
-+		_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
-+		/* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL0); */
-+	}
-+
-+exit:
-+	return _SUCCESS;
-+}
-+
-+/* free all stainfo which in sta_hash[all] */
-+void rtw_free_all_stainfo(_adapter *padapter)
-+{
-+	_irqL	 irqL;
-+	_list	*plist, *phead;
-+	s32	index;
-+	struct sta_info *psta = NULL;
-+	struct	sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *pbcmc_stainfo = rtw_get_bcmc_stainfo(padapter);
-+	u8 free_sta_num = 0;
-+	char free_sta_list[NUM_STA];
-+	int stainfo_offset;
-+
-+
-+	if (pstapriv->asoc_sta_count == 1)
-+		goto exit;
-+
-+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+	for (index = 0; index < NUM_STA; index++) {
-+		phead = &(pstapriv->sta_hash[index]);
-+		plist = get_next(phead);
-+
-+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+			psta = LIST_CONTAINOR(plist, struct sta_info , hash_list);
-+
-+			plist = get_next(plist);
-+
-+			if (pbcmc_stainfo != psta) {
-+				if (rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr) == _FALSE)
-+					rtw_list_delete(&psta->hash_list);
-+
-+				stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
-+				if (stainfo_offset_valid(stainfo_offset))
-+					free_sta_list[free_sta_num++] = stainfo_offset;
-+			}
-+
-+		}
-+	}
-+
-+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+
-+	for (index = 0; index < free_sta_num; index++) {
-+		psta = rtw_get_stainfo_by_offset(pstapriv, free_sta_list[index]);
-+		rtw_free_stainfo(padapter , psta);
-+	}
-+
-+exit:
-+	return;
-+}
-+
-+/* any station allocated can be searched by hash list */
-+struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr)
-+{
-+
-+	_irqL	 irqL;
-+
-+	_list	*plist, *phead;
-+
-+	struct sta_info *psta = NULL;
-+
-+	u32	index;
-+
-+	const u8 *addr;
-+
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+
-+
-+	if (hwaddr == NULL)
-+		return NULL;
-+
-+	if (IS_MCAST(hwaddr))
-+		addr = bc_addr;
-+	else
-+		addr = hwaddr;
-+
-+	index = wifi_mac_hash(addr);
-+
-+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+	phead = &(pstapriv->sta_hash[index]);
-+	plist = get_next(phead);
-+
-+
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+
-+		psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+
-+		if ((_rtw_memcmp(psta->cmn.mac_addr, addr, ETH_ALEN)) == _TRUE) {
-+			/* if found the matched address */
-+			break;
-+		}
-+		psta = NULL;
-+		plist = get_next(plist);
-+	}
-+
-+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+	return psta;
-+
-+}
-+
-+u32 rtw_init_bcmc_stainfo(_adapter *padapter)
-+{
-+
-+	struct sta_info	*psta;
-+	struct tx_servq	*ptxservq;
-+	u32 res = _SUCCESS;
-+	NDIS_802_11_MAC_ADDRESS	bcast_addr = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+
-+	struct	sta_priv *pstapriv = &padapter->stapriv;
-+
-+
-+	psta = rtw_alloc_stainfo(pstapriv, bcast_addr);
-+
-+	if (psta == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+#ifdef CONFIG_BEAMFORMING
-+	psta->cmn.bf_info.g_id = 63;
-+	psta->cmn.bf_info.p_aid = 0;
-+#endif
-+
-+	ptxservq = &(psta->sta_xmitpriv.be_q);
-+
-+	/*
-+		_enter_critical(&pstapending->lock, &irqL0);
-+
-+		if (rtw_is_list_empty(&ptxservq->tx_pending))
-+			rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(pstapending));
-+
-+		_exit_critical(&pstapending->lock, &irqL0);
-+	*/
-+
-+exit:
-+	return _SUCCESS;
-+
-+}
-+
-+
-+struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter)
-+{
-+	struct sta_info	*psta;
-+	struct sta_priv	*pstapriv = &padapter->stapriv;
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	psta = rtw_get_stainfo(pstapriv, bc_addr);
-+	return psta;
-+
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+u16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	u16 aid, i, used_cnt = 0;
-+
-+	for (i = 0; i < stapriv->max_aid; i++) {
-+		aid = ((i + stapriv->started_aid - 1) % stapriv->max_aid) + 1;
-+		if (stapriv->sta_aid[aid - 1] == NULL)
-+			break;
-+		if (++used_cnt >= stapriv->max_num_sta)
-+			break;
-+	}
-+
-+	/* check for aid limit and assoc limit  */
-+	if (i >= stapriv->max_aid || used_cnt >= stapriv->max_num_sta)
-+		aid = 0;
-+
-+	sta->cmn.aid = aid;
-+	if (aid) {
-+		stapriv->sta_aid[aid - 1] = sta;
-+		if (stapriv->rr_aid)
-+			stapriv->started_aid = (aid % stapriv->max_aid) + 1;
-+	}
-+
-+	return aid;
-+}
-+
-+void dump_aid_status(void *sel, _adapter *adapter)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	u8 *aid_bmp;
-+	u16 i, used_cnt = 0;
-+
-+	aid_bmp = rtw_zmalloc(stapriv->aid_bmp_len);
-+	if (!aid_bmp)
-+		return;
-+
-+	for (i = 1; i <= stapriv->max_aid; i++) {
-+		if (stapriv->sta_aid[i - 1]) {
-+			aid_bmp[i / 8] |= BIT(i % 8);
-+			++used_cnt;
-+		}
-+	}
-+
-+	RTW_PRINT_SEL(sel, "used_cnt:%u/%u\n", used_cnt, stapriv->max_aid);
-+	RTW_MAP_DUMP_SEL(sel, "aid_map:", aid_bmp, stapriv->aid_bmp_len);
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "%-2s %-11s\n", "rr", "started_aid");
-+	RTW_PRINT_SEL(sel, "%2d %11d\n", stapriv->rr_aid, stapriv->started_aid);
-+
-+	rtw_mfree(aid_bmp, stapriv->aid_bmp_len);
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+const char *const _acl_period_str[RTW_ACL_PERIOD_NUM] = {
-+	"DEV",
-+	"BSS",
-+};
-+
-+const char *const _acl_mode_str[RTW_ACL_MODE_MAX] = {
-+	"DISABLED",
-+	"ACCEPT_UNLESS_LISTED",
-+	"DENY_UNLESS_LISTED",
-+};
-+
-+u8 _rtw_access_ctrl(_adapter *adapter, u8 period, const u8 *mac_addr)
-+{
-+	u8 res = _TRUE;
-+	_irqL irqL;
-+	_list *list, *head;
-+	struct rtw_wlan_acl_node *acl_node;
-+	u8 match = _FALSE;
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct wlan_acl_pool *acl;
-+	_queue	*acl_node_q;
-+
-+	if (period >= RTW_ACL_PERIOD_NUM) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	acl = &stapriv->acl_list[period];
-+	acl_node_q = &acl->acl_node_q;
-+
-+	if (acl->mode != RTW_ACL_MODE_ACCEPT_UNLESS_LISTED
-+		&& acl->mode != RTW_ACL_MODE_DENY_UNLESS_LISTED)
-+		goto exit;
-+
-+	_enter_critical_bh(&(acl_node_q->lock), &irqL);
-+	head = get_list_head(acl_node_q);
-+	list = get_next(head);
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list);
-+		list = get_next(list);
-+
-+		if (_rtw_memcmp(acl_node->addr, mac_addr, ETH_ALEN)) {
-+			if (acl_node->valid == _TRUE) {
-+				match = _TRUE;
-+				break;
-+			}
-+		}
-+	}
-+	_exit_critical_bh(&(acl_node_q->lock), &irqL);
-+
-+	if (acl->mode == RTW_ACL_MODE_ACCEPT_UNLESS_LISTED)
-+		res = (match == _TRUE) ?  _FALSE : _TRUE;
-+	else /* RTW_ACL_MODE_DENY_UNLESS_LISTED */
-+		res = (match == _TRUE) ?  _TRUE : _FALSE;
-+
-+exit:
-+	return res;
-+}
-+
-+u8 rtw_access_ctrl(_adapter *adapter, const u8 *mac_addr)
-+{
-+	int i;
-+
-+	for (i = 0; i < RTW_ACL_PERIOD_NUM; i++)
-+		if (_rtw_access_ctrl(adapter, i, mac_addr) == _FALSE)
-+			return _FALSE;
-+
-+	return _TRUE;
-+}
-+
-+void dump_macaddr_acl(void *sel, _adapter *adapter)
-+{
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct wlan_acl_pool *acl;
-+	int i, j;
-+
-+	for (j = 0; j < RTW_ACL_PERIOD_NUM; j++) {
-+		RTW_PRINT_SEL(sel, "period:%s(%d)\n", acl_period_str(j), j);
-+
-+		acl = &stapriv->acl_list[j];
-+		RTW_PRINT_SEL(sel, "mode:%s(%d)\n", acl_mode_str(acl->mode), acl->mode);
-+		RTW_PRINT_SEL(sel, "num:%d/%d\n", acl->num, NUM_ACL);
-+		for (i = 0; i < NUM_ACL; i++) {
-+			if (acl->aclnode[i].valid == _FALSE)
-+				continue;
-+			RTW_PRINT_SEL(sel, MAC_FMT"\n", MAC_ARG(acl->aclnode[i].addr));
-+		}
-+		RTW_PRINT_SEL(sel, "\n");
-+	}
-+}
-+#endif /* CONFIG_RTW_MACADDR_ACL */
-+
-+bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr)
-+{
-+#if CONFIG_RTW_PRE_LINK_STA
-+	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
-+	struct sta_info *sta = NULL;
-+	u8 exist = _FALSE;
-+	int i;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
-+	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
-+		if (pre_link_sta_ctl->node[i].valid == _TRUE
-+			&& _rtw_memcmp(pre_link_sta_ctl->node[i].addr, addr, ETH_ALEN) == _TRUE
-+		) {
-+			exist = _TRUE;
-+			break;
-+		}
-+	}
-+	_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
-+
-+	return exist;
-+#else
-+	return _FALSE;
-+#endif
-+}
-+
-+#if CONFIG_RTW_PRE_LINK_STA
-+struct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr)
-+{
-+	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
-+	struct pre_link_sta_node_t *node = NULL;
-+	struct sta_info *sta = NULL;
-+	u8 exist = _FALSE;
-+	int i;
-+	_irqL irqL;
-+
-+	if (rtw_check_invalid_mac_address(hwaddr, _FALSE) == _TRUE)
-+		goto exit;
-+
-+	_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
-+	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
-+		if (pre_link_sta_ctl->node[i].valid == _TRUE
-+			&& _rtw_memcmp(pre_link_sta_ctl->node[i].addr, hwaddr, ETH_ALEN) == _TRUE
-+		) {
-+			node = &pre_link_sta_ctl->node[i];
-+			exist = _TRUE;
-+			break;
-+		}
-+
-+		if (node == NULL && pre_link_sta_ctl->node[i].valid == _FALSE)
-+			node = &pre_link_sta_ctl->node[i];
-+	}
-+
-+	if (exist == _FALSE && node) {
-+		_rtw_memcpy(node->addr, hwaddr, ETH_ALEN);
-+		node->valid = _TRUE;
-+		pre_link_sta_ctl->num++;
-+	}
-+	_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
-+
-+	if (node == NULL)
-+		goto exit;
-+
-+	sta = rtw_get_stainfo(stapriv, hwaddr);
-+	if (sta)
-+		goto odm_hook;
-+
-+	sta = rtw_alloc_stainfo(stapriv, hwaddr);
-+	if (!sta)
-+		goto exit;
-+
-+	sta->state = WIFI_FW_PRE_LINK;
-+
-+odm_hook:
-+	rtw_hal_set_odm_var(stapriv->padapter, HAL_ODM_STA_INFO, sta, _TRUE);
-+
-+exit:
-+	return sta;
-+}
-+
-+void rtw_pre_link_sta_del(struct sta_priv *stapriv, u8 *hwaddr)
-+{
-+	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
-+	struct pre_link_sta_node_t *node = NULL;
-+	struct sta_info *sta = NULL;
-+	u8 exist = _FALSE;
-+	int i;
-+	_irqL irqL;
-+
-+	if (rtw_check_invalid_mac_address(hwaddr, _FALSE) == _TRUE)
-+		goto exit;
-+
-+	_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
-+	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
-+		if (pre_link_sta_ctl->node[i].valid == _TRUE
-+			&& _rtw_memcmp(pre_link_sta_ctl->node[i].addr, hwaddr, ETH_ALEN) == _TRUE
-+		) {
-+			node = &pre_link_sta_ctl->node[i];
-+			exist = _TRUE;
-+			break;
-+		}
-+	}
-+
-+	if (exist == _TRUE && node) {
-+		node->valid = _FALSE;
-+		pre_link_sta_ctl->num--;
-+	}
-+	_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
-+
-+	if (exist == _FALSE)
-+		goto exit;
-+
-+	sta = rtw_get_stainfo(stapriv, hwaddr);
-+	if (!sta)
-+		goto exit;
-+
-+	if (sta->state == WIFI_FW_PRE_LINK)
-+		rtw_free_stainfo(stapriv->padapter, sta);
-+
-+exit:
-+	return;
-+}
-+
-+void rtw_pre_link_sta_ctl_reset(struct sta_priv *stapriv)
-+{
-+	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
-+	struct pre_link_sta_node_t *node = NULL;
-+	struct sta_info *sta = NULL;
-+	int i, j = 0;
-+	_irqL irqL;
-+
-+	u8 addrs[RTW_PRE_LINK_STA_NUM][ETH_ALEN];
-+
-+	_rtw_memset(addrs, 0, RTW_PRE_LINK_STA_NUM * ETH_ALEN);
-+
-+	_enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
-+	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
-+		if (pre_link_sta_ctl->node[i].valid == _FALSE)
-+			continue;
-+		_rtw_memcpy(&(addrs[j][0]), pre_link_sta_ctl->node[i].addr, ETH_ALEN);
-+		pre_link_sta_ctl->node[i].valid = _FALSE;
-+		pre_link_sta_ctl->num--;
-+		j++;
-+	}
-+	_exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
-+
-+	for (i = 0; i < j; i++) {
-+		sta = rtw_get_stainfo(stapriv, &(addrs[i][0]));
-+		if (!sta)
-+			continue;
-+
-+		if (sta->state == WIFI_FW_PRE_LINK)
-+			rtw_free_stainfo(stapriv->padapter, sta);
-+	}
-+}
-+
-+void rtw_pre_link_sta_ctl_init(struct sta_priv *stapriv)
-+{
-+	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
-+	int i;
-+
-+	_rtw_spinlock_init(&pre_link_sta_ctl->lock);
-+	pre_link_sta_ctl->num = 0;
-+	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++)
-+		pre_link_sta_ctl->node[i].valid = _FALSE;
-+}
-+
-+void rtw_pre_link_sta_ctl_deinit(struct sta_priv *stapriv)
-+{
-+	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
-+	int i;
-+
-+	rtw_pre_link_sta_ctl_reset(stapriv);
-+
-+	_rtw_spinlock_free(&pre_link_sta_ctl->lock);
-+}
-+
-+void dump_pre_link_sta_ctl(void *sel, struct sta_priv *stapriv)
-+{
-+	struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
-+	int i;
-+
-+	RTW_PRINT_SEL(sel, "num:%d/%d\n", pre_link_sta_ctl->num, RTW_PRE_LINK_STA_NUM);
-+
-+	for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
-+		if (pre_link_sta_ctl->node[i].valid == _FALSE)
-+			continue;
-+		RTW_PRINT_SEL(sel, MAC_FMT"\n", MAC_ARG(pre_link_sta_ctl->node[i].addr));
-+	}
-+}
-+#endif /* CONFIG_RTW_PRE_LINK_STA */
-+
-diff --git a/drivers/staging/rtl8723cs/core/rtw_swcrypto.c b/drivers/staging/rtl8723cs/core/rtw_swcrypto.c
-new file mode 100644
-index 000000000000..3659b35768c6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_swcrypto.c
-@@ -0,0 +1,296 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include <drv_types.h>
-+#include <hal_data.h>
-+#include <aes.h>
-+#include <aes_siv.h>
-+#include <aes_wrap.h>
-+#include <sha256.h>
-+#include <wlancrypto_wrap.h>
-+
-+/**
-+ * rtw_ccmp_encrypt - 
-+ * @key: the temporal key 
-+ * @hdrlen: mac header length
-+ * @frame: the frame including the mac header, pn and payload
-+ * @plen: payload length, i.e., length of the plain text, without PN and MIC
-+ */
-+int _rtw_ccmp_encrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen)
-+{
-+	u8 *enc = NULL;
-+	size_t enc_len = 0;
-+
-+	if (key_len == 16) { /* 128 bits */
-+		enc = ccmp_encrypt(key,
-+			frame,
-+			hdrlen + plen,
-+			hdrlen,
-+			(hdrlen == 26) ? (frame + hdrlen - 2) : NULL,
-+			NULL, 0, &enc_len);
-+	} else if (key_len == 32) { /* 256 bits */
-+		enc = ccmp_256_encrypt(key,
-+			frame,
-+			hdrlen + plen,
-+			hdrlen,
-+			(hdrlen == 26) ? (frame + hdrlen - 2) : NULL,
-+			NULL, 0, &enc_len);
-+	}
-+
-+	if (enc == NULL) {
-+		RTW_INFO("Failed to encrypt CCMP(%u) frame", key_len);
-+		return _FAIL;
-+	}
-+
-+	/* Copy @enc back to @frame and free @enc */
-+	_rtw_memcpy(frame, enc, enc_len);
-+	rtw_mfree(enc, enc_len + AES_BLOCK_SIZE);
-+
-+	return _SUCCESS;
-+}
-+
-+
-+/**
-+ * rtw_ccmp_decrypt -
-+ * @key: the temporal key
-+ * @hdrlen: length of the mac header
-+ * @frame: the raw frame (@hdrlen + PN + enc_data + MIC)
-+ * @plen: length of the frame (@hdrlen + PN + enc_data + MIC)
-+ */
-+int _rtw_ccmp_decrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame,
-+	uint plen)
-+{
-+	u8 *plain = NULL;
-+	size_t plain_len = 0;
-+	const struct ieee80211_hdr *hdr;
-+
-+	hdr = (const struct ieee80211_hdr *)frame;
-+
-+	if (key_len == 16) { /* 128 bits */
-+		plain = ccmp_decrypt(key,
-+			hdr,
-+			frame + hdrlen, /* PN + enc_data + MIC */
-+			plen - hdrlen, /* PN + enc_data + MIC */
-+			&plain_len);
-+	} else if (key_len == 32) { /* 256 bits */
-+		plain = ccmp_256_decrypt(key,
-+			hdr,
-+			frame + hdrlen, /* PN + enc_data + MIC */
-+			plen - hdrlen, /* PN + enc_data + MIC */
-+			&plain_len);
-+	}
-+
-+	if (plain == NULL) {
-+		RTW_INFO("Failed to decrypt CCMP(%u) frame", key_len);
-+		return _FAIL;
-+	}
-+
-+	/* Copy @plain back to @frame and free @plain */
-+	_rtw_memcpy(frame + hdrlen + 8, plain, plain_len);
-+	rtw_mfree(plain, plen - hdrlen + AES_BLOCK_SIZE);
-+
-+	RTW_DBG_DUMP("ccmp_decrypt(): decrypted frame\n",
-+		frame, hdrlen + 8 + plen);
-+
-+	return _SUCCESS;
-+}
-+
-+
-+#ifdef CONFIG_RTW_MESH_AEK
-+/* wrapper to ase_siv_encrypt and aes_siv_decrypt */
-+int _aes_siv_encrypt(const u8 *key, size_t key_len,
-+	const u8 *pw, size_t pwlen,
-+	size_t num_elem, const u8 *addr[], const size_t *len, u8 *out)
-+{
-+	return aes_siv_encrypt(key, key_len, pw, pwlen, num_elem, addr, len, out);
-+}
-+int _aes_siv_decrypt(const u8 *key, size_t key_len,
-+	const u8 *iv_crypt, size_t iv_c_len,
-+	size_t num_elem, const u8 *addr[], const size_t *len, u8 *out)
-+{
-+	return aes_siv_decrypt(key, key_len, iv_crypt, iv_c_len, num_elem, addr, len, out);
-+}
-+#endif
-+
-+
-+/**
-+ * _rtw_gcmp_encrypt - 
-+ * @key: the temporal key 
-+ * @hdrlen: mac header length
-+ * @frame: the frame including the mac header, pn and payload
-+ * @plen: payload length, i.e., length of the plain text, without PN and MIC
-+ */
-+int _rtw_gcmp_encrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen)
-+{
-+	u8 *enc = NULL;
-+	size_t enc_len = 0;
-+
-+	enc = gcmp_encrypt(key, key_len,
-+		frame,
-+		hdrlen + plen,
-+		hdrlen,
-+		(hdrlen == 26) ? (frame + hdrlen - 2) : NULL,
-+		NULL, 0, &enc_len);
-+	if (enc == NULL) {
-+		RTW_INFO("Failed to encrypt GCMP frame");
-+		return _FAIL;
-+	}
-+
-+	/* Copy @enc back to @frame and free @enc */
-+	_rtw_memcpy(frame, enc, enc_len);
-+	rtw_mfree(enc, enc_len + AES_BLOCK_SIZE);
-+
-+	return _SUCCESS;
-+}
-+
-+
-+/**
-+ * _rtw_gcmp_decrypt -
-+ * @key: the temporal key
-+ * @hdrlen: length of the mac header
-+ * @frame: the raw frame (@hdrlen + PN + enc_data + MIC)
-+ * @plen: length of the frame (@hdrlen + PN + enc_data + MIC)
-+ */
-+int _rtw_gcmp_decrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen)
-+{
-+	u8 *plain = NULL;
-+	size_t plain_len = 0;
-+	const struct ieee80211_hdr *hdr;
-+
-+	hdr = (const struct ieee80211_hdr *)frame;
-+
-+	plain = gcmp_decrypt(key, key_len,
-+		hdr,
-+		frame + hdrlen, /* PN + enc_data + MIC */
-+		plen - hdrlen, /* PN + enc_data + MIC */
-+		&plain_len);
-+
-+	if (plain == NULL) {
-+		RTW_INFO("Failed to decrypt GCMP(%u) frame", key_len);
-+		return _FAIL;
-+	}
-+
-+	/* Copy @plain back to @frame and free @plain */
-+	_rtw_memcpy(frame + hdrlen + 8, plain, plain_len);
-+	rtw_mfree(plain, plen - hdrlen + AES_BLOCK_SIZE);
-+
-+	RTW_DBG_DUMP("gcmp_decipher(): decrypted frame\n",
-+		frame, hdrlen + 8 + plen);
-+
-+	return _SUCCESS;
-+}
-+
-+
-+#if  defined(CONFIG_IEEE80211W) | defined(CONFIG_TDLS)
-+u8 _bip_ccmp_protect(const u8 *key, size_t key_len,
-+	const u8 *data, size_t data_len, u8 *mic)
-+{
-+	u8 res = _SUCCESS;
-+
-+	if (key_len == 16) {
-+		if (omac1_aes_128(key, data, data_len, mic)) {
-+			res = _FAIL;
-+			RTW_ERR("%s : omac1_aes_128 fail!", __func__);
-+		}
-+	} else if (key_len == 32) {
-+		if (omac1_aes_256(key, data, data_len, mic)) {
-+			res = _FAIL;
-+			RTW_ERR("%s : omac1_aes_256 fail!", __func__);
-+		}
-+	} else {
-+		RTW_ERR("%s : key_len not match!", __func__);
-+		res = _FAIL;
-+	}
-+
-+	return  res;
-+}
-+
-+
-+u8 _bip_gcmp_protect(u8 *whdr_pos, size_t len,
-+	const u8 *key, size_t key_len,
-+	const u8 *data, size_t data_len, u8 *mic)
-+{
-+	u8 res = _SUCCESS;
-+	u32 mic_len = 16;
-+	u8 nonce[12], *npos;
-+	const u8 *gcmp_ipn;
-+
-+	gcmp_ipn = whdr_pos + len - mic_len - 6;
-+
-+	/* Nonce: A2 | IPN */
-+	_rtw_memcpy(nonce, get_addr2_ptr(whdr_pos), ETH_ALEN);
-+	npos = nonce + ETH_ALEN;
-+	*npos++ = gcmp_ipn[5];
-+	*npos++ = gcmp_ipn[4];
-+	*npos++ = gcmp_ipn[3];
-+	*npos++ = gcmp_ipn[2];
-+	*npos++ = gcmp_ipn[1];
-+	*npos++ = gcmp_ipn[0];
-+
-+	if (aes_gmac(key, key_len, nonce, sizeof(nonce),
-+			data, data_len, mic)) {
-+		res = _FAIL;
-+		RTW_ERR("%s : aes_gmac fail!", __func__);
-+	}
-+
-+	return res;
-+}
-+#endif /* CONFIG_IEEE80211W */
-+
-+
-+#ifdef CONFIG_TDLS
-+void _tdls_generate_tpk(void *sta, const u8 *own_addr, const u8 *bssid)
-+{
-+	struct sta_info *psta = (struct sta_info *)sta;
-+	u8 *SNonce = psta->SNonce;
-+	u8 *ANonce = psta->ANonce;
-+
-+	u8 key_input[SHA256_MAC_LEN];
-+	const u8 *nonce[2];
-+	size_t len[2];
-+	u8 data[3 * ETH_ALEN];
-+
-+	/* IEEE Std 802.11z-2010 8.5.9.1:
-+	 * TPK-Key-Input = SHA-256(min(SNonce, ANonce) || max(SNonce, ANonce))
-+	 */
-+	len[0] = 32;
-+	len[1] = 32;
-+	if (_rtw_memcmp2(SNonce, ANonce, 32) < 0) {
-+		nonce[0] = SNonce;
-+		nonce[1] = ANonce;
-+	} else {
-+		nonce[0] = ANonce;
-+		nonce[1] = SNonce;
-+	}
-+
-+	sha256_vector(2, nonce, len, key_input);
-+
-+	/*
-+	 * TPK = KDF-Hash-Length(TPK-Key-Input, "TDLS PMK",
-+	 *	min(MAC_I, MAC_R) || max(MAC_I, MAC_R) || BSSID)
-+	 */
-+
-+	if (_rtw_memcmp2(own_addr, psta->cmn.mac_addr, ETH_ALEN) < 0) {
-+		_rtw_memcpy(data, own_addr, ETH_ALEN);
-+		_rtw_memcpy(data + ETH_ALEN, psta->cmn.mac_addr, ETH_ALEN);
-+	} else {
-+		_rtw_memcpy(data, psta->cmn.mac_addr, ETH_ALEN);
-+		_rtw_memcpy(data + ETH_ALEN, own_addr, ETH_ALEN);
-+	}
-+
-+	_rtw_memcpy(data + 2 * ETH_ALEN, bssid, ETH_ALEN);
-+
-+	sha256_prf(key_input, SHA256_MAC_LEN, "TDLS PMK", data, sizeof(data), (u8 *)&psta->tpk, sizeof(psta->tpk));
-+}
-+#endif /* CONFIG_TDLS */
-diff --git a/drivers/staging/rtl8723cs/core/rtw_tdls.c b/drivers/staging/rtl8723cs/core/rtw_tdls.c
-new file mode 100644
-index 000000000000..d557234109be
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_tdls.c
-@@ -0,0 +1,3516 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_TDLS_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#ifdef CONFIG_TDLS
-+#define ONE_SEC 	1000 /* 1000 ms */
-+
-+extern unsigned char MCS_rate_2R[16];
-+extern unsigned char MCS_rate_1R[16];
-+
-+inline void rtw_tdls_set_link_established(_adapter *adapter, bool en)
-+{
-+	adapter->tdlsinfo.link_established = en;
-+	rtw_mi_update_iface_status(&(adapter->mlmepriv), 0);
-+}
-+
-+void rtw_reset_tdls_info(_adapter *padapter)
-+{
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+
-+	ptdlsinfo->ap_prohibited = _FALSE;
-+
-+	/* For TDLS channel switch, currently we only allow it to work in wifi logo test mode */
-+	if (padapter->registrypriv.wifi_spec == 1)
-+		ptdlsinfo->ch_switch_prohibited = _FALSE;
-+	else
-+		ptdlsinfo->ch_switch_prohibited = _TRUE;
-+
-+	rtw_tdls_set_link_established(padapter, _FALSE);
-+	ptdlsinfo->sta_cnt = 0;
-+	ptdlsinfo->sta_maximum = _FALSE;
-+
-+#ifdef CONFIG_TDLS_CH_SW
-+	ptdlsinfo->chsw_info.ch_sw_state = TDLS_STATE_NONE;
-+	ATOMIC_SET(&ptdlsinfo->chsw_info.chsw_on, _FALSE);
-+	ptdlsinfo->chsw_info.off_ch_num = 0;
-+	ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	ptdlsinfo->chsw_info.cur_time = 0;
-+	ptdlsinfo->chsw_info.delay_switch_back = _FALSE;
-+	ptdlsinfo->chsw_info.dump_stack = _FALSE;
-+#endif
-+
-+	ptdlsinfo->ch_sensing = 0;
-+	ptdlsinfo->watchdog_count = 0;
-+	ptdlsinfo->dev_discovered = _FALSE;
-+
-+#ifdef CONFIG_WFD
-+	ptdlsinfo->wfd_info = &padapter->wfd_info;
-+#endif
-+
-+	ptdlsinfo->tdls_sctx = NULL;
-+}
-+
-+int rtw_init_tdls_info(_adapter *padapter)
-+{
-+	int	res = _SUCCESS;
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+
-+	rtw_reset_tdls_info(padapter);
-+
-+#ifdef CONFIG_TDLS_DRIVER_SETUP
-+	ptdlsinfo->driver_setup = _TRUE;
-+#else
-+	ptdlsinfo->driver_setup = _FALSE;
-+#endif /* CONFIG_TDLS_DRIVER_SETUP */
-+
-+	_rtw_spinlock_init(&ptdlsinfo->cmd_lock);
-+	_rtw_spinlock_init(&ptdlsinfo->hdl_lock);
-+
-+	return res;
-+
-+}
-+
-+void rtw_free_tdls_info(struct tdls_info *ptdlsinfo)
-+{
-+	_rtw_spinlock_free(&ptdlsinfo->cmd_lock);
-+	_rtw_spinlock_free(&ptdlsinfo->hdl_lock);
-+
-+	_rtw_memset(ptdlsinfo, 0, sizeof(struct tdls_info));
-+
-+}
-+
-+void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd)
-+{
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	_irqL	 irqL;
-+	_list	*plist, *phead;
-+	s32	index;
-+	struct sta_info *psta = NULL;
-+	struct sta_info *ptdls_sta[NUM_STA];
-+	u8 empty_hwaddr[ETH_ALEN] = { 0x00 };
-+
-+	_rtw_memset(ptdls_sta, 0x00, sizeof(ptdls_sta));
-+
-+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+	for (index = 0; index < NUM_STA; index++) {
-+		phead = &(pstapriv->sta_hash[index]);
-+		plist = get_next(phead);
-+
-+		while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+
-+			plist = get_next(plist);
-+
-+			if (psta->tdls_sta_state != TDLS_STATE_NONE)
-+				ptdls_sta[index] = psta;
-+		}
-+	}
-+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+	for (index = 0; index < NUM_STA; index++) {
-+		if (ptdls_sta[index]) {
-+			struct TDLSoption_param tdls_param;
-+
-+			psta = ptdls_sta[index];
-+
-+			RTW_INFO("Do tear down to "MAC_FMT" by enqueue_cmd = %d\n", MAC_ARG(psta->cmn.mac_addr), enqueue_cmd);
-+
-+			_rtw_memcpy(&(tdls_param.addr), psta->cmn.mac_addr, ETH_ALEN);
-+			tdls_param.option = TDLS_TEARDOWN_STA_NO_WAIT;
-+			tdls_hdl(padapter, (unsigned char *)&(tdls_param));
-+
-+			rtw_tdls_teardown_pre_hdl(padapter, psta);
-+
-+			if (enqueue_cmd == _TRUE)
-+				rtw_tdls_cmd(padapter, psta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
-+			else
-+			 {
-+				tdls_param.option = TDLS_TEARDOWN_STA_LOCALLY_POST;
-+				tdls_hdl(padapter, (unsigned char *)&(tdls_param));
-+			}
-+		}
-+	}
-+}
-+
-+int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len)
-+{
-+	u8 tdls_prohibited_bit = 0x40; /* bit(38); TDLS_prohibited */
-+
-+	if (pkt_len < 5)
-+		return _FALSE;
-+
-+	pframe += 4;
-+	if ((*pframe) & tdls_prohibited_bit)
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+int check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len)
-+{
-+	u8 tdls_ch_swithcing_prohibited_bit = 0x80; /* bit(39); TDLS_channel_switching prohibited */
-+
-+	if (pkt_len < 5)
-+		return _FALSE;
-+
-+	pframe += 4;
-+	if ((*pframe) & tdls_ch_swithcing_prohibited_bit)
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+u8 rtw_is_tdls_enabled(_adapter *padapter)
-+{
-+	return padapter->registrypriv.en_tdls;
-+}
-+
-+void rtw_set_tdls_enable(_adapter *padapter, u8 enable)
-+{
-+	padapter->registrypriv.en_tdls = enable;
-+	RTW_INFO("%s: en_tdls = %d\n", __func__, rtw_is_tdls_enabled(padapter));
-+}
-+
-+void rtw_enable_tdls_func(_adapter *padapter)
-+{
-+	if (rtw_is_tdls_enabled(padapter) == _TRUE)
-+		return;
-+
-+#if 0
-+#ifdef CONFIG_MCC_MODE
-+	if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC) == _TRUE) {
-+		RTW_INFO("[TDLS] MCC is running, can't enable TDLS !\n");
-+		return;
-+	}
-+#endif
-+#endif
-+	rtw_set_tdls_enable(padapter, _TRUE);
-+}
-+
-+void rtw_disable_tdls_func(_adapter *padapter, u8 enqueue_cmd)
-+{
-+	if (rtw_is_tdls_enabled(padapter) == _FALSE)
-+		return;
-+
-+	rtw_free_all_tdls_sta(padapter, enqueue_cmd);
-+	rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR);
-+	rtw_reset_tdls_info(padapter);
-+
-+	rtw_set_tdls_enable(padapter, _FALSE);
-+}
-+
-+u8 rtw_is_tdls_sta_existed(_adapter *padapter)
-+{
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *psta;
-+	int i = 0;
-+	_irqL irqL;
-+	_list	*plist, *phead;
-+	u8 ret = _FALSE;
-+
-+	if (rtw_is_tdls_enabled(padapter) == _FALSE)
-+		return _FALSE;
-+
-+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+	for (i = 0; i < NUM_STA; i++) {
-+		phead = &(pstapriv->sta_hash[i]);
-+		plist = get_next(phead);
-+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+			plist = get_next(plist);
-+			if (psta->tdls_sta_state != TDLS_STATE_NONE) {
-+				ret = _TRUE;
-+				goto Exit;
-+			}
-+		}
-+	}
-+
-+Exit:
-+
-+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+	return ret;
-+}
-+
-+u8 rtw_tdls_is_setup_allowed(_adapter *padapter)
-+{
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+
-+	if (is_client_associated_to_ap(padapter) == _FALSE)
-+		return _FALSE;
-+
-+	if (ptdlsinfo->ap_prohibited == _TRUE)
-+		return _FALSE;
-+
-+	return _TRUE;
-+}
-+
-+#ifdef CONFIG_TDLS_CH_SW
-+u8 rtw_tdls_is_chsw_allowed(_adapter *padapter)
-+{
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+
-+	if (ptdlsinfo->ch_switch_prohibited == _TRUE)
-+		return _FALSE;
-+
-+	if (padapter->registrypriv.wifi_spec == 0)
-+		return _FALSE;
-+
-+	return _TRUE;
-+}
-+#endif
-+
-+int _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ms)
-+{
-+	int ret = _FAIL;
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl, *qc;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	pattrib->hdrlen += 2;
-+	pattrib->qos_en = _TRUE;
-+	pattrib->eosp = 1;
-+	pattrib->ack_policy = 0;
-+	pattrib->mdata = 0;
-+	pattrib->retry_ctrl = _FALSE;
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	if (power_mode)
-+		SetPwrMgt(fctrl);
-+
-+	qc = (unsigned short *)(pframe + pattrib->hdrlen - 2);
-+
-+	SetPriority(qc, 7);	/* Set priority to VO */
-+
-+	SetEOSP(qc, pattrib->eosp);
-+
-+	SetAckpolicy(qc, pattrib->ack_policy);
-+
-+	_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	if (wait_ms)
-+		ret = dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, wait_ms);
-+	else {
-+		dump_mgntframe(padapter, pmgntframe);
-+		ret = _SUCCESS;
-+	}
-+
-+exit:
-+	return ret;
-+
-+}
-+
-+/*
-+ *wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
-+ *wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
-+ *try_cnt means the maximal TX count to try
-+ */
-+int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms)
-+{
-+	int ret;
-+	int i = 0;
-+	systime start = rtw_get_current_time();
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+#if 0
-+	psta = rtw_get_stainfo(&padapter->stapriv, da);
-+	if (psta) {
-+		if (power_mode)
-+			rtw_hal_macid_sleep(padapter, psta->cmn.mac_id);
-+		else
-+			rtw_hal_macid_wakeup(padapter, psta->cmn.mac_id);
-+	} else {
-+		RTW_INFO(FUNC_ADPT_FMT ": Can't find sta info for " MAC_FMT ", skip macid %s!!\n",
-+			FUNC_ADPT_ARG(padapter), MAC_ARG(da), power_mode ? "sleep" : "wakeup");
-+		rtw_warn_on(1);
-+	}
-+#endif
-+
-+	do {
-+		ret = _issue_nulldata_to_TDLS_peer_STA(padapter, da, power_mode, wait_ms);
-+
-+		i++;
-+
-+		if (RTW_CANNOT_RUN(padapter))
-+			break;
-+
-+		if (i < try_cnt && wait_ms > 0 && ret == _FAIL)
-+			rtw_msleep_os(wait_ms);
-+
-+	} while ((i < try_cnt) && (ret == _FAIL || wait_ms == 0));
-+
-+	if (ret != _FAIL) {
-+		ret = _SUCCESS;
-+#ifndef DBG_XMIT_ACK
-+		goto exit;
-+#endif
-+	}
-+
-+	if (try_cnt && wait_ms) {
-+		if (da)
-+			RTW_INFO(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n",
-+				FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter),
-+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+		else
-+			RTW_INFO(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n",
-+				FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter),
-+				ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
-+	}
-+exit:
-+	return ret;
-+}
-+
-+/* TDLS encryption(if needed) will always be CCMP */
-+void rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta)
-+{
-+	ptdls_sta->dot118021XPrivacy = _AES_;
-+	rtw_setstakey_cmd(padapter, ptdls_sta, TDLS_KEY, _TRUE);
-+}
-+
-+#ifdef CONFIG_80211N_HT
-+void rtw_tdls_process_ht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
-+	u8	max_AMPDU_len, min_MPDU_spacing;
-+	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0;
-+
-+	/* Save HT capabilities in the sta object */
-+	_rtw_memset(&ptdls_sta->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap));
-+	if (data && Length >= sizeof(struct rtw_ieee80211_ht_cap)) {
-+		ptdls_sta->flags |= WLAN_STA_HT;
-+		ptdls_sta->flags |= WLAN_STA_WME;
-+
-+		_rtw_memcpy(&ptdls_sta->htpriv.ht_cap, data, sizeof(struct rtw_ieee80211_ht_cap));
-+	} else {
-+		ptdls_sta->flags &= ~WLAN_STA_HT;
-+		return;
-+	}
-+
-+	if (ptdls_sta->flags & WLAN_STA_HT) {
-+		if (padapter->registrypriv.ht_enable == _TRUE && is_supported_ht(padapter->registrypriv.wireless_mode) ) {
-+			ptdls_sta->htpriv.ht_option = _TRUE;
-+			ptdls_sta->qos_option = _TRUE;
-+		} else {
-+			ptdls_sta->htpriv.ht_option = _FALSE;
-+			ptdls_sta->qos_option = _FALSE;
-+		}
-+	}
-+
-+	/* HT related cap */
-+	if (ptdls_sta->htpriv.ht_option) {
-+		/* Check if sta supports rx ampdu */
-+		if (padapter->registrypriv.ampdu_enable == 1)
-+			ptdls_sta->htpriv.ampdu_enable = _TRUE;
-+
-+		/* AMPDU Parameters field */
-+		/* Get MIN of MAX AMPDU Length Exp */
-+		if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (data[2] & 0x3))
-+			max_AMPDU_len = (data[2] & 0x3);
-+		else
-+			max_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3);
-+		/* Get MAX of MIN MPDU Start Spacing */
-+		if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (data[2] & 0x1c))
-+			min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c);
-+		else
-+			min_MPDU_spacing = (data[2] & 0x1c);
-+		ptdls_sta->htpriv.rx_ampdu_min_spacing = max_AMPDU_len | min_MPDU_spacing;
-+
-+		/* Check if sta support s Short GI 20M */
-+		if ((phtpriv->sgi_20m == _TRUE) && (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_20)))
-+			ptdls_sta->htpriv.sgi_20m = _TRUE;
-+
-+		/* Check if sta support s Short GI 40M */
-+		if ((phtpriv->sgi_40m == _TRUE) && (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)))
-+			ptdls_sta->htpriv.sgi_40m = _TRUE;
-+
-+		/* Bwmode would still followed AP's setting */
-+		if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) {
-+			if (padapter->mlmeextpriv.cur_bwmode >= CHANNEL_WIDTH_40)
-+				ptdls_sta->cmn.bw_mode = CHANNEL_WIDTH_40;
-+			ptdls_sta->htpriv.ch_offset = padapter->mlmeextpriv.cur_ch_offset;
-+		}
-+
-+		/* Config LDPC Coding Capability */
-+		if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP(data)) {
-+			SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX));
-+			RTW_INFO("Enable HT Tx LDPC!\n");
-+		}
-+		ptdls_sta->htpriv.ldpc_cap = cur_ldpc_cap;
-+
-+		/* Config STBC setting */
-+		if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(data)) {
-+			SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX));
-+			RTW_INFO("Enable HT Tx STBC!\n");
-+		}
-+		ptdls_sta->htpriv.stbc_cap = cur_stbc_cap;
-+
-+#ifdef CONFIG_BEAMFORMING
-+		/* Config Tx beamforming setting */
-+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
-+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(data))
-+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
-+
-+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
-+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(data))
-+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
-+		ptdls_sta->htpriv.beamform_cap = cur_beamform_cap;
-+		if (cur_beamform_cap)
-+			RTW_INFO("Client HT Beamforming Cap = 0x%02X\n", cur_beamform_cap);
-+#endif /* CONFIG_BEAMFORMING */
-+	}
-+
-+}
-+
-+u8 *rtw_tdls_set_ht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
-+{
-+	rtw_ht_use_default_setting(padapter);
-+
-+	if (padapter->registrypriv.wifi_spec == 1) {
-+		padapter->mlmepriv.htpriv.sgi_20m = _FALSE;
-+		padapter->mlmepriv.htpriv.sgi_40m = _FALSE;
-+	}
-+
-+	rtw_restructure_ht_ie(padapter, NULL, pframe, 0, &(pattrib->pktlen), padapter->mlmeextpriv.cur_channel);
-+
-+	return pframe + pattrib->pktlen;
-+}
-+#endif
-+
-+#ifdef CONFIG_80211AC_VHT
-+void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct vht_priv			*pvhtpriv = &pmlmepriv->vhtpriv;
-+	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0, tx_nss = 0;
-+	u16 cur_beamform_cap = 0;
-+	u8	*pcap_mcs;
-+
-+	_rtw_memset(&ptdls_sta->vhtpriv, 0, sizeof(struct vht_priv));
-+	if (data && Length == 12) {
-+		ptdls_sta->flags |= WLAN_STA_VHT;
-+
-+		_rtw_memcpy(ptdls_sta->vhtpriv.vht_cap, data, 12);
-+
-+#if 0
-+		if (elems.vht_op_mode_notify && elems.vht_op_mode_notify_len == 1)
-+			_rtw_memcpy(&pstat->vhtpriv.vht_op_mode_notify, elems.vht_op_mode_notify, 1);
-+		else /* for Frame without Operating Mode notify ie; default: 80M */
-+			pstat->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80;
-+#else
-+		ptdls_sta->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80;
-+#endif
-+	} else {
-+		ptdls_sta->flags &= ~WLAN_STA_VHT;
-+		return;
-+	}
-+
-+	if (ptdls_sta->flags & WLAN_STA_VHT) {
-+		if (REGSTY_IS_11AC_ENABLE(&padapter->registrypriv)
-+		    && is_supported_vht(padapter->registrypriv.wireless_mode)
-+		    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))) {
-+			ptdls_sta->vhtpriv.vht_option = _TRUE;
-+			ptdls_sta->cmn.ra_info.is_vht_enable = _TRUE;
-+		}
-+		else
-+			ptdls_sta->vhtpriv.vht_option = _FALSE;
-+	}
-+
-+	/* B4 Rx LDPC */
-+	if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
-+	    GET_VHT_CAPABILITY_ELE_RX_LDPC(data)) {
-+		SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
-+		RTW_INFO("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap);
-+	}
-+	ptdls_sta->vhtpriv.ldpc_cap = cur_ldpc_cap;
-+
-+	/* B5 Short GI for 80 MHz */
-+	ptdls_sta->vhtpriv.sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE;
-+
-+	/* B8 B9 B10 Rx STBC */
-+	if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) &&
-+	    GET_VHT_CAPABILITY_ELE_RX_STBC(data)) {
-+		SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
-+		RTW_INFO("Current VHT STBC Setting = %02X\n", cur_stbc_cap);
-+	}
-+	ptdls_sta->vhtpriv.stbc_cap = cur_stbc_cap;
-+
-+	#ifdef CONFIG_BEAMFORMING
-+	/* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
-+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
-+	    GET_VHT_CAPABILITY_ELE_SU_BFEE(data))
-+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
-+
-+	/* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
-+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
-+	    GET_VHT_CAPABILITY_ELE_SU_BFER(data))
-+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
-+	ptdls_sta->vhtpriv.beamform_cap = cur_beamform_cap;
-+	ptdls_sta->cmn.bf_info.vht_beamform_cap = cur_beamform_cap;
-+	if (cur_beamform_cap)
-+		RTW_INFO("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap);
-+	#endif /*CONFIG_BEAMFORMING*/
-+
-+	/* B23 B24 B25 Maximum A-MPDU Length Exponent */
-+	ptdls_sta->vhtpriv.ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(data);
-+
-+	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(data);
-+	tx_nss = GET_HAL_TX_NSS(padapter);
-+	rtw_vht_nss_to_mcsmap(tx_nss, ptdls_sta->vhtpriv.vht_mcs_map, pcap_mcs);
-+	ptdls_sta->vhtpriv.vht_highest_rate = rtw_get_vht_highest_rate(ptdls_sta->vhtpriv.vht_mcs_map);
-+}
-+
-+void rtw_tdls_process_vht_operation(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
-+{
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct registry_priv *regsty = adapter_to_regsty(padapter);
-+	u8 operation_bw = 0;
-+
-+	if (GET_VHT_OPERATION_ELE_CHL_WIDTH(data) >= 1) {
-+
-+		operation_bw = CHANNEL_WIDTH_80;
-+
-+		if (hal_is_bw_support(padapter, operation_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, operation_bw)
-+			&& (operation_bw <= pmlmeext->cur_bwmode))
-+			ptdls_sta->cmn.bw_mode = operation_bw;
-+		else
-+			ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;
-+	} else
-+		ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;
-+}
-+
-+void rtw_tdls_process_vht_op_mode_notify(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
-+{
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct registry_priv *regsty = adapter_to_regsty(padapter);
-+	u8	target_bw;
-+	u8	target_rxss, current_rxss;
-+
-+	if (pvhtpriv->vht_option == _FALSE)
-+		return;
-+
-+	target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(data);
-+	target_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(data) + 1);
-+
-+	if (hal_is_bw_support(padapter, target_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw)
-+		&& (target_bw <= pmlmeext->cur_bwmode))
-+		ptdls_sta->cmn.bw_mode = target_bw;
-+	else
-+		ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;
-+
-+	current_rxss = rtw_vht_mcsmap_to_nss(ptdls_sta->vhtpriv.vht_mcs_map);
-+	if (target_rxss != current_rxss) {
-+		u8	vht_mcs_map[2] = {};
-+
-+		rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, ptdls_sta->vhtpriv.vht_mcs_map);
-+		_rtw_memcpy(ptdls_sta->vhtpriv.vht_mcs_map, vht_mcs_map, 2);
-+	}
-+}
-+
-+u8 *rtw_tdls_set_aid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
-+{
-+	return rtw_set_ie(pframe, EID_AID, 2, (u8 *)&(padapter->mlmepriv.cur_network.aid), &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_vht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
-+{
-+	u32 ie_len = 0;
-+
-+	rtw_vht_use_default_setting(padapter);
-+
-+	ie_len = rtw_build_vht_cap_ie(padapter, pframe);
-+	pattrib->pktlen += ie_len;
-+
-+	return pframe + ie_len;
-+}
-+
-+u8 *rtw_tdls_set_vht_operation(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 channel)
-+{
-+	u32 ie_len = 0;
-+
-+	ie_len = rtw_build_vht_operation_ie(padapter, pframe, channel);
-+	pattrib->pktlen += ie_len;
-+
-+	return pframe + ie_len;
-+}
-+
-+u8 *rtw_tdls_set_vht_op_mode_notify(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 bw)
-+{
-+	u32 ie_len = 0;
-+
-+	ie_len = rtw_build_vht_op_mode_notify_ie(padapter, pframe, bw);
-+	pattrib->pktlen += ie_len;
-+
-+	return pframe + ie_len;
-+}
-+#endif
-+
-+
-+u8 *rtw_tdls_set_sup_ch(_adapter *adapter, u8 *pframe, struct pkt_attrib *pattrib)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	u8 sup_ch[30 * 2] = {0x00}, ch_set_idx = 0, sup_ch_idx = 2;
-+
-+	while (ch_set_idx < rfctl->max_chan_nums && rfctl->channel_set[ch_set_idx].ChannelNum != 0) {
-+		if (rfctl->channel_set[ch_set_idx].ChannelNum <= 14) {
-+			/* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */
-+			sup_ch[0] = 1;	/* First channel number */
-+			sup_ch[1] = rfctl->channel_set[ch_set_idx].ChannelNum;	/* Number of channel */
-+		} else {
-+			sup_ch[sup_ch_idx++] = rfctl->channel_set[ch_set_idx].ChannelNum;
-+			sup_ch[sup_ch_idx++] = 1;
-+		}
-+		ch_set_idx++;
-+	}
-+
-+	return rtw_set_ie(pframe, _SUPPORTED_CH_IE_, sup_ch_idx, sup_ch, &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_rsnie(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib,  int init, struct sta_info *ptdls_sta)
-+{
-+	u8 *p = NULL;
-+	int len = 0;
-+
-+	if (ptxmgmt->len > 0)
-+		p = rtw_get_ie(ptxmgmt->buf, _RSN_IE_2_, &len, ptxmgmt->len);
-+
-+	if (p != NULL)
-+		return rtw_set_ie(pframe, _RSN_IE_2_, len, p + 2, &(pattrib->pktlen));
-+	else if (init == _TRUE)
-+		return rtw_set_ie(pframe, _RSN_IE_2_, sizeof(TDLS_RSNIE), TDLS_RSNIE, &(pattrib->pktlen));
-+	else
-+		return rtw_set_ie(pframe, _RSN_IE_2_, sizeof(ptdls_sta->TDLS_RSNIE), ptdls_sta->TDLS_RSNIE, &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_ext_cap(u8 *pframe, struct pkt_attrib *pattrib)
-+{
-+	return rtw_set_ie(pframe, _EXT_CAP_IE_ , sizeof(TDLS_EXT_CAPIE), TDLS_EXT_CAPIE, &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_qos_cap(u8 *pframe, struct pkt_attrib *pattrib)
-+{
-+	return rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, sizeof(TDLS_WMMIE), TDLS_WMMIE,  &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_ftie(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib, u8 *ANonce, u8 *SNonce)
-+{
-+	struct wpa_tdls_ftie FTIE = {0};
-+	u8 *p = NULL;
-+	int len = 0;
-+
-+	if (ptxmgmt->len > 0)
-+		p = rtw_get_ie(ptxmgmt->buf, _FTIE_, &len, ptxmgmt->len);
-+
-+	if (p != NULL)
-+		return rtw_set_ie(pframe, _FTIE_, len, p + 2, &(pattrib->pktlen));
-+	else {
-+		if (ANonce != NULL)
-+			_rtw_memcpy(FTIE.Anonce, ANonce, WPA_NONCE_LEN);
-+		if (SNonce != NULL)
-+			_rtw_memcpy(FTIE.Snonce, SNonce, WPA_NONCE_LEN);
-+
-+		return rtw_set_ie(pframe, _FTIE_, TDLS_FTIE_DATA_LEN,
-+						  (u8 *)FTIE.data, &(pattrib->pktlen));
-+	}
-+}
-+
-+u8 *rtw_tdls_set_timeout_interval(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib, int init, struct sta_info *ptdls_sta)
-+{
-+	u8 timeout_itvl[5];	/* set timeout interval to maximum value */
-+	u32 timeout_interval = TDLS_TPK_RESEND_COUNT;
-+	u8 *p = NULL;
-+	int len = 0;
-+
-+	if (ptxmgmt->len > 0)
-+		p = rtw_get_ie(ptxmgmt->buf, _TIMEOUT_ITVL_IE_, &len, ptxmgmt->len);
-+
-+	if (p != NULL)
-+		return rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, len, p + 2, &(pattrib->pktlen));
-+	else {
-+		/* Timeout interval */
-+		timeout_itvl[0] = 0x02;
-+		if (init == _TRUE)
-+			_rtw_memcpy(timeout_itvl + 1, &timeout_interval, 4);
-+		else
-+			_rtw_memcpy(timeout_itvl + 1, (u8 *)(&ptdls_sta->TDLS_PeerKey_Lifetime), 4);
-+
-+		return rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen));
-+	}
-+}
-+
-+u8 *rtw_tdls_set_bss_coexist(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
-+{
-+	u8 iedata = 0;
-+
-+	if (padapter->mlmepriv.num_FortyMHzIntolerant > 0)
-+		iedata |= BIT(2);	/* 20 MHz BSS Width Request */
-+
-+	/* Information Bit should be set by TDLS test plan 5.9 */
-+	iedata |= BIT(0);
-+	return rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_payload_type(u8 *pframe, struct pkt_attrib *pattrib)
-+{
-+	u8 payload_type = 0x02;
-+	return rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_category(u8 *pframe, struct pkt_attrib *pattrib, u8 category)
-+{
-+	return rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_action(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)
-+{
-+	return rtw_set_fixed_ie(pframe, 1, &(ptxmgmt->action_code), &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_status_code(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)
-+{
-+	return rtw_set_fixed_ie(pframe, 2, (u8 *)&(ptxmgmt->status_code), &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_dialog(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)
-+{
-+	u8 dialogtoken = 1;
-+	if (ptxmgmt->dialog_token)
-+		return rtw_set_fixed_ie(pframe, 1, &(ptxmgmt->dialog_token), &(pattrib->pktlen));
-+	else
-+		return rtw_set_fixed_ie(pframe, 1, &(dialogtoken), &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_reg_class(u8 *pframe, struct pkt_attrib *pattrib, struct sta_info *ptdls_sta)
-+{
-+	u8 reg_class = 22;
-+	return rtw_set_fixed_ie(pframe, 1, &(reg_class), &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_second_channel_offset(u8 *pframe, struct pkt_attrib *pattrib, u8 ch_offset)
-+{
-+	return rtw_set_ie(pframe, EID_SecondaryChnlOffset , 1, &ch_offset, &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_capability(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &pmlmeext->mlmext_info;
-+	u8 cap_from_ie[2] = {0};
-+
-+	_rtw_memcpy(cap_from_ie, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2);
-+
-+	return rtw_set_fixed_ie(pframe, 2, cap_from_ie, &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_supported_rate(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
-+{
-+	u8 bssrate[NDIS_802_11_LENGTH_RATES_EX];
-+	int bssrate_len = 0;
-+	u8 more_supportedrates = 0;
-+
-+	rtw_set_supported_rate(bssrate, (padapter->registrypriv.wireless_mode == WIRELESS_MODE_MAX) ? padapter->mlmeextpriv.cur_wireless_mode : padapter->registrypriv.wireless_mode);
-+	bssrate_len = rtw_get_rateset_len(bssrate);
-+
-+	if (bssrate_len > 8) {
-+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen));
-+		more_supportedrates = 1;
-+	} else
-+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen));
-+
-+	/* extended supported rates */
-+	if (more_supportedrates == 1)
-+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen));
-+
-+	return pframe;
-+}
-+
-+u8 *rtw_tdls_set_sup_reg_class(u8 *pframe, struct pkt_attrib *pattrib)
-+{
-+	return rtw_set_ie(pframe, _SRC_IE_ , sizeof(TDLS_SRC), TDLS_SRC, &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_linkid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 init)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	u8 link_id_addr[18] = {0};
-+
-+	_rtw_memcpy(link_id_addr, get_my_bssid(&(pmlmeinfo->network)), 6);
-+
-+	if (init == _TRUE) {
-+		_rtw_memcpy((link_id_addr + 6), pattrib->src, 6);
-+		_rtw_memcpy((link_id_addr + 12), pattrib->dst, 6);
-+	} else {
-+		_rtw_memcpy((link_id_addr + 6), pattrib->dst, 6);
-+		_rtw_memcpy((link_id_addr + 12), pattrib->src, 6);
-+	}
-+	return rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen));
-+}
-+
-+#ifdef CONFIG_TDLS_CH_SW
-+u8 *rtw_tdls_set_target_ch(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
-+{
-+	u8 target_ch = 1;
-+	if (padapter->tdlsinfo.chsw_info.off_ch_num)
-+		return rtw_set_fixed_ie(pframe, 1, &(padapter->tdlsinfo.chsw_info.off_ch_num), &(pattrib->pktlen));
-+	else
-+		return rtw_set_fixed_ie(pframe, 1, &(target_ch), &(pattrib->pktlen));
-+}
-+
-+u8 *rtw_tdls_set_ch_sw(u8 *pframe, struct pkt_attrib *pattrib, struct sta_info *ptdls_sta)
-+{
-+	u8 ch_switch_timing[4] = {0};
-+	u16 switch_time = (ptdls_sta->ch_switch_time >= TDLS_CH_SWITCH_TIME * 1000) ?
-+			  ptdls_sta->ch_switch_time : TDLS_CH_SWITCH_TIME;
-+	u16 switch_timeout = (ptdls_sta->ch_switch_timeout >= TDLS_CH_SWITCH_TIMEOUT * 1000) ?
-+		     ptdls_sta->ch_switch_timeout : TDLS_CH_SWITCH_TIMEOUT;
-+
-+	_rtw_memcpy(ch_switch_timing, &switch_time, 2);
-+	_rtw_memcpy(ch_switch_timing + 2, &switch_timeout, 2);
-+
-+	return rtw_set_ie(pframe, _CH_SWITCH_TIMING_,  4, ch_switch_timing, &(pattrib->pktlen));
-+}
-+
-+void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+	u8 bcn_early_case;
-+
-+	if (enable == _TRUE) {
-+#ifdef CONFIG_TDLS_CH_SW_V2
-+		pHalData->ch_switch_offload = _TRUE;
-+#endif
-+
-+#ifdef CONFIG_TDLS_CH_SW_BY_DRV
-+		pHalData->ch_switch_offload = _FALSE;
-+#endif
-+		bcn_early_case = TDLS_BCN_ERLY_ON;
-+	}
-+	else {
-+		pHalData->ch_switch_offload = _FALSE;
-+		bcn_early_case = TDLS_BCN_ERLY_OFF;
-+	}
-+
-+	if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) != enable)
-+		ATOMIC_SET(&padapter->tdlsinfo.chsw_info.chsw_on, enable);
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_BCN_EARLY_C2H_RPT, &enable);
-+	rtw_hal_set_hwreg(padapter, HW_VAR_SET_DRV_ERLY_INT, &bcn_early_case);
-+	RTW_INFO("[TDLS] %s Bcn Early C2H Report\n", (enable == _TRUE) ? "Start" : "Stop");
-+}
-+
-+void rtw_tdls_ch_sw_back_to_base_chnl(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv;
-+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
-+
-+	pmlmepriv = &padapter->mlmepriv;
-+
-+	if ((ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) &&
-+	    (padapter->mlmeextpriv.cur_channel != rtw_get_oper_ch(padapter)))
-+		rtw_tdls_cmd(padapter, pchsw_info->addr, TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED);
-+}
-+
-+#ifndef CONFIG_TDLS_CH_SW_V2
-+static void rtw_tdls_chsw_oper_init(_adapter *padapter, u32 timeout_ms)
-+{
-+	struct submit_ctx	*chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx;
-+
-+	rtw_sctx_init(chsw_sctx, timeout_ms);
-+}
-+
-+static int rtw_tdls_chsw_oper_wait(_adapter *padapter)
-+{
-+	struct submit_ctx	*chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx;
-+
-+	return rtw_sctx_wait(chsw_sctx, __func__);
-+}
-+
-+void rtw_tdls_chsw_oper_done(_adapter *padapter)
-+{
-+	struct submit_ctx	*chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx;
-+
-+	rtw_sctx_done(&chsw_sctx);
-+}
-+#endif
-+
-+s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_type, u8 channel, u8 channel_offset, u16 bwmode, u16 ch_switch_time)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+	u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	u32 ch_sw_time_start, ch_sw_time_spent, wait_time;
-+	u8 take_care_iqk;
-+	s32 ret = _FAIL;
-+
-+	ch_sw_time_start = rtw_systime_to_ms(rtw_get_current_time());
-+
-+	/* set mac_id sleep before channel switch */
-+	rtw_hal_macid_sleep(padapter, ptdls_sta->cmn.mac_id);
-+
-+#if defined(CONFIG_TDLS_CH_SW_BY_DRV) || defined(CONFIG_TDLS_CH_SW_V2)
-+	set_channel_bwmode(padapter, channel, channel_offset, bwmode);
-+	ret = _SUCCESS;
-+#else
-+	rtw_tdls_chsw_oper_init(padapter, TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT);
-+
-+	/* channel switch IOs offload to FW */
-+	if (rtw_hal_ch_sw_oper_offload(padapter, channel, channel_offset, bwmode) == _SUCCESS) {
-+		if (rtw_tdls_chsw_oper_wait(padapter) == _SUCCESS) {
-+			/* set channel and bw related variables in driver */
-+			_enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
-+
-+			rtw_set_oper_ch(padapter, channel);
-+			rtw_set_oper_choffset(padapter, channel_offset);
-+			rtw_set_oper_bw(padapter, bwmode);
-+
-+			center_ch = rtw_get_center_ch(channel, bwmode, channel_offset);
-+			pHalData->current_channel = center_ch;
-+			pHalData->CurrentCenterFrequencyIndex1 = center_ch;
-+			pHalData->current_channel_bw = bwmode;
-+			pHalData->nCur40MhzPrimeSC = channel_offset;
-+
-+			if (bwmode == CHANNEL_WIDTH_80) {
-+				if (center_ch > channel)
-+					chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
-+				else if (center_ch < channel)
-+					chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
-+				else
-+					chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+			}
-+			pHalData->nCur80MhzPrimeSC = chnl_offset80;
-+
-+			pHalData->CurrentCenterFrequencyIndex1 = center_ch;
-+
-+			_exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
-+
-+			rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
-+			if (take_care_iqk == _TRUE)
-+				rtw_hal_ch_sw_iqk_info_restore(padapter, CH_SW_USE_CASE_TDLS);
-+
-+			ret = _SUCCESS;
-+		} else
-+			RTW_INFO("[TDLS] chsw oper wait fail !!\n");
-+	}
-+#endif
-+
-+	if (ret == _SUCCESS) {
-+		ch_sw_time_spent = rtw_systime_to_ms(rtw_get_current_time()) - ch_sw_time_start;
-+		if (chnl_type == TDLS_CH_SW_OFF_CHNL) {
-+			if ((u32)ch_switch_time / 1000 > ch_sw_time_spent)
-+				wait_time = (u32)ch_switch_time / 1000 - ch_sw_time_spent;
-+			else
-+				wait_time = 0;
-+
-+			if (wait_time > 0)
-+				rtw_msleep_os(wait_time);
-+		}
-+	}
-+
-+	/* set mac_id wakeup after channel switch */
-+	rtw_hal_macid_wakeup(padapter, ptdls_sta->cmn.mac_id);
-+
-+	return ret;
-+}
-+#endif
-+
-+u8 *rtw_tdls_set_wmm_params(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 wmm_param_ele[24] = {0};
-+
-+	if (&pmlmeinfo->WMM_param) {
-+		_rtw_memcpy(wmm_param_ele, WMM_PARA_OUI, 6);
-+		if (_rtw_memcmp(&pmlmeinfo->WMM_param, &wmm_param_ele[6], 18) == _TRUE)
-+			/* Use default WMM Param */
-+			_rtw_memcpy(wmm_param_ele + 6, (u8 *)&TDLS_WMM_PARAM_IE, sizeof(TDLS_WMM_PARAM_IE));
-+		else
-+			_rtw_memcpy(wmm_param_ele + 6, (u8 *)&pmlmeinfo->WMM_param, sizeof(pmlmeinfo->WMM_param));
-+		return rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_,  24, wmm_param_ele, &(pattrib->pktlen));
-+	} else
-+		return pframe;
-+}
-+
-+#ifdef CONFIG_WFD
-+void rtw_tdls_process_wfd_ie(struct tdls_info *ptdlsinfo, u8 *ptr, u8 length)
-+{
-+	u8 *wfd_ie;
-+	u32	wfd_ielen = 0;
-+
-+	if (!hal_chk_wl_func(tdls_info_to_adapter(ptdlsinfo), WL_FUNC_MIRACAST))
-+		return;
-+
-+	/* Try to get the TCP port information when receiving the negotiation response. */
-+
-+	wfd_ie = rtw_get_wfd_ie(ptr, length, NULL, &wfd_ielen);
-+	while (wfd_ie) {
-+		u8 *attr_content;
-+		u32	attr_contentlen = 0;
-+		int	i;
-+
-+		RTW_INFO("[%s] WFD IE Found!!\n", __FUNCTION__);
-+		attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen);
-+		if (attr_content && attr_contentlen) {
-+			ptdlsinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16(attr_content + 2);
-+			RTW_INFO("[%s] Peer PORT NUM = %d\n", __FUNCTION__, ptdlsinfo->wfd_info->peer_rtsp_ctrlport);
-+		}
-+
-+		attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_LOCAL_IP_ADDR, NULL, &attr_contentlen);
-+		if (attr_content && attr_contentlen) {
-+			_rtw_memcpy(ptdlsinfo->wfd_info->peer_ip_address, (attr_content + 1), 4);
-+			RTW_INFO("[%s] Peer IP = %02u.%02u.%02u.%02u\n", __FUNCTION__,
-+				ptdlsinfo->wfd_info->peer_ip_address[0], ptdlsinfo->wfd_info->peer_ip_address[1],
-+				ptdlsinfo->wfd_info->peer_ip_address[2], ptdlsinfo->wfd_info->peer_ip_address[3]);
-+		}
-+
-+		wfd_ie = rtw_get_wfd_ie(wfd_ie + wfd_ielen, (ptr + length) - (wfd_ie + wfd_ielen), NULL, &wfd_ielen);
-+	}
-+}
-+
-+int issue_tunneled_probe_req(_adapter *padapter)
-+{
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	u8 baddr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	struct tdls_txmgmt txmgmt;
-+	int ret = _FAIL;
-+
-+	RTW_INFO("[%s]\n", __FUNCTION__);
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	txmgmt.action_code = TUNNELED_PROBE_REQ;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	pattrib = &pmgntframe->attrib;
-+
-+	pmgntframe->frame_tag = DATA_FRAMETAG;
-+	pattrib->ether_type = 0x890d;
-+
-+	_rtw_memcpy(pattrib->dst, baddr, ETH_ALEN);
-+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+
-+	update_tdls_attrib(padapter, pattrib);
-+	pattrib->qsel = pattrib->priority;
-+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {
-+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+		goto exit;
-+	}
-+	dump_mgntframe(padapter, pmgntframe);
-+	ret = _SUCCESS;
-+exit:
-+
-+	return ret;
-+}
-+
-+int issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct tdls_txmgmt txmgmt;
-+	int ret = _FAIL;
-+
-+	RTW_INFO("[%s]\n", __FUNCTION__);
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	txmgmt.action_code = TUNNELED_PROBE_RSP;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	pattrib = &pmgntframe->attrib;
-+
-+	pmgntframe->frame_tag = DATA_FRAMETAG;
-+	pattrib->ether_type = 0x890d;
-+
-+	_rtw_memcpy(pattrib->dst, precv_frame->u.hdr.attrib.src, ETH_ALEN);
-+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+
-+	update_tdls_attrib(padapter, pattrib);
-+	pattrib->qsel = pattrib->priority;
-+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {
-+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+		goto exit;
-+	}
-+	dump_mgntframe(padapter, pmgntframe);
-+	ret = _SUCCESS;
-+exit:
-+
-+	return ret;
-+}
-+#endif /* CONFIG_WFD */
-+
-+int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack)
-+{
-+	struct tdls_info	*ptdlsinfo = &padapter->tdlsinfo;
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *ptdls_sta = NULL;
-+	_irqL irqL;
-+	int ret = _FAIL;
-+	/* Retry timer should be set at least 301 sec, using TPK_count counting 301 times. */
-+	u32 timeout_interval = TDLS_TPK_RESEND_COUNT;
-+
-+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
-+
-+	if (rtw_tdls_is_setup_allowed(padapter) == _FALSE)
-+		goto exit;
-+
-+	if (IS_MCAST(ptxmgmt->peer))
-+		goto exit;
-+
-+	ptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer);
-+	if (ptdlsinfo->sta_maximum == _TRUE) {
-+		if (ptdls_sta == NULL)
-+			goto exit;
-+		else if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE))
-+			goto exit;
-+	}
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	if (ptdls_sta == NULL) {
-+		ptdls_sta = rtw_alloc_stainfo(pstapriv, ptxmgmt->peer);
-+		if (ptdls_sta == NULL) {
-+			RTW_INFO("[%s] rtw_alloc_stainfo fail\n", __FUNCTION__);
-+			rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
-+			rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+			goto exit;
-+		}
-+		ptdlsinfo->sta_cnt++;
-+	}
-+
-+	ptxmgmt->action_code = TDLS_SETUP_REQUEST;
-+
-+	pattrib = &pmgntframe->attrib;
-+	pmgntframe->frame_tag = DATA_FRAMETAG;
-+	pattrib->ether_type = 0x890d;
-+
-+	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
-+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+
-+	update_tdls_attrib(padapter, pattrib);
-+
-+	if (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM)
-+		ptdlsinfo->sta_maximum  = _TRUE;
-+
-+	ptdls_sta->tdls_sta_state |= TDLS_RESPONDER_STATE;
-+
-+	if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
-+		ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;
-+		_set_timer(&ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME);
-+	}
-+
-+	pattrib->qsel = pattrib->priority;
-+
-+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
-+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+		goto exit;
-+	}
-+
-+	if (wait_ack)
-+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
-+	else {
-+		dump_mgntframe(padapter, pmgntframe);
-+		ret = _SUCCESS;
-+	}
-+
-+exit:
-+
-+	return ret;
-+}
-+
-+int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta, u8 wait_ack)
-+{
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	_irqL irqL;
-+	int ret = _FAIL;
-+
-+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
-+
-+	ptxmgmt->action_code = TDLS_TEARDOWN;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	rtw_mi_set_scan_deny(padapter, 550);
-+	rtw_mi_scan_abort(padapter, _TRUE);
-+
-+	pattrib = &pmgntframe->attrib;
-+
-+	pmgntframe->frame_tag = DATA_FRAMETAG;
-+	pattrib->ether_type = 0x890d;
-+
-+	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
-+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
-+
-+	if (ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_)
-+		_rtw_memcpy(pattrib->ra, ptxmgmt->peer, ETH_ALEN);
-+	else
-+		_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
-+
-+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+
-+	update_tdls_attrib(padapter, pattrib);
-+	pattrib->qsel = pattrib->priority;
-+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
-+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+		goto exit;
-+	}
-+
-+	if (rtw_tdls_is_driver_setup(padapter) == _TRUE)
-+		if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
-+			if (pattrib->encrypt)
-+				_cancel_timer_ex(&ptdls_sta->TPK_timer);
-+
-+	if (wait_ack)
-+		ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
-+	else {
-+		dump_mgntframe(padapter, pmgntframe);
-+		ret = _SUCCESS;
-+	}
-+
-+exit:
-+
-+	return ret;
-+}
-+
-+int issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack)
-+{
-+	struct sta_info *ptdls_sta = NULL;
-+	int ret = _FAIL;
-+
-+	ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), ptxmgmt->peer);
-+	if (ptdls_sta == NULL) {
-+		RTW_INFO("No tdls_sta for tearing down\n");
-+		goto exit;
-+	}
-+
-+	ret = _issue_tdls_teardown(padapter, ptxmgmt, ptdls_sta, wait_ack);
-+	if ((ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) && (ret == _FAIL)) {
-+		/* Change status code and send teardown again via AP */
-+		ptxmgmt->status_code = _RSON_TDLS_TEAR_TOOFAR_;
-+		ret = _issue_tdls_teardown(padapter, ptxmgmt, ptdls_sta, wait_ack);
-+	}
-+
-+	if (rtw_tdls_is_driver_setup(padapter)) {
-+		rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
-+		rtw_tdls_cmd(padapter, ptxmgmt->peer, TDLS_TEARDOWN_STA_LOCALLY_POST);
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+int issue_tdls_dis_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt)
-+{
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	int ret = _FAIL;
-+
-+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
-+
-+	ptxmgmt->action_code = TDLS_DISCOVERY_REQUEST;
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	pattrib = &pmgntframe->attrib;
-+	pmgntframe->frame_tag = DATA_FRAMETAG;
-+	pattrib->ether_type = 0x890d;
-+
-+	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
-+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+
-+	update_tdls_attrib(padapter, pattrib);
-+	pattrib->qsel = pattrib->priority;
-+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
-+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+		goto exit;
-+	}
-+	dump_mgntframe(padapter, pmgntframe);
-+	RTW_INFO("issue tdls dis req\n");
-+
-+	ret = _SUCCESS;
-+exit:
-+
-+	return ret;
-+}
-+
-+int issue_tdls_setup_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt)
-+{
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	int ret = _FAIL;
-+
-+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
-+
-+	ptxmgmt->action_code = TDLS_SETUP_RESPONSE;
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	pattrib = &pmgntframe->attrib;
-+	pmgntframe->frame_tag = DATA_FRAMETAG;
-+	pattrib->ether_type = 0x890d;
-+
-+	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
-+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ra, get_bssid(&(padapter->mlmepriv)), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+
-+	update_tdls_attrib(padapter, pattrib);
-+	pattrib->qsel = pattrib->priority;
-+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
-+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+		goto exit;
-+	}
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	ret = _SUCCESS;
-+exit:
-+
-+	return ret;
-+
-+}
-+
-+int issue_tdls_setup_cfm(_adapter *padapter, struct tdls_txmgmt *ptxmgmt)
-+{
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	int ret = _FAIL;
-+
-+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
-+
-+	ptxmgmt->action_code = TDLS_SETUP_CONFIRM;
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	pattrib = &pmgntframe->attrib;
-+	pmgntframe->frame_tag = DATA_FRAMETAG;
-+	pattrib->ether_type = 0x890d;
-+
-+	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
-+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ra, get_bssid(&padapter->mlmepriv), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+
-+	update_tdls_attrib(padapter, pattrib);
-+	pattrib->qsel = pattrib->priority;
-+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
-+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+		goto exit;
-+	}
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+	ret = _SUCCESS;
-+exit:
-+
-+	return ret;
-+
-+}
-+
-+/* TDLS Discovery Response frame is a management action frame */
-+int issue_tdls_dis_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 privacy)
-+{
-+	struct xmit_frame		*pmgntframe;
-+	struct pkt_attrib		*pattrib;
-+	unsigned char			*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short		*fctrl;
-+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	int ret = _FAIL;
-+
-+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	/* unicast probe request frame */
-+	_rtw_memcpy(pwlanhdr->addr1, ptxmgmt->peer, ETH_ALEN);
-+	_rtw_memcpy(pattrib->dst, pwlanhdr->addr1, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pattrib->src, pwlanhdr->addr2, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ra, pwlanhdr->addr3, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	rtw_build_tdls_dis_rsp_ies(padapter, pmgntframe, pframe, ptxmgmt, privacy);
-+
-+	pattrib->nr_frags = 1;
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+int issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *ptdls_sta, struct tdls_txmgmt *ptxmgmt)
-+{
-+	struct xmit_frame	*pmgntframe;
-+	struct pkt_attrib	*pattrib;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
-+	int ret = _FAIL;
-+
-+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
-+
-+	ptxmgmt->action_code = TDLS_PEER_TRAFFIC_RESPONSE;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	pattrib = &pmgntframe->attrib;
-+
-+	pmgntframe->frame_tag = DATA_FRAMETAG;
-+	pattrib->ether_type = 0x890d;
-+
-+	_rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);
-+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+
-+	update_tdls_attrib(padapter, pattrib);
-+	pattrib->qsel = pattrib->priority;
-+
-+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
-+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+		goto exit;
-+	}
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+	ret = _SUCCESS;
-+
-+exit:
-+
-+	return ret;
-+}
-+
-+int issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *ptdls_sta)
-+{
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct tdls_txmgmt txmgmt;
-+	int ret = _FAIL;
-+
-+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	txmgmt.action_code = TDLS_PEER_TRAFFIC_INDICATION;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	pattrib = &pmgntframe->attrib;
-+
-+	pmgntframe->frame_tag = DATA_FRAMETAG;
-+	pattrib->ether_type = 0x890d;
-+
-+	_rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);
-+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+
-+	/* PTI frame's priority should be AC_VO */
-+	pattrib->priority = 7;
-+
-+	update_tdls_attrib(padapter, pattrib);
-+	pattrib->qsel = pattrib->priority;
-+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {
-+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+		goto exit;
-+	}
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+	ret = _SUCCESS;
-+
-+exit:
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_TDLS_CH_SW
-+int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta)
-+{
-+	struct xmit_frame	*pmgntframe;
-+	struct pkt_attrib	*pattrib;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
-+	struct tdls_txmgmt txmgmt;
-+	int ret = _FAIL;
-+
-+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
-+
-+	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
-+		RTW_INFO("[TDLS] Ignore %s since channel switch is not allowed\n", __func__);
-+		goto exit;
-+	}
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	txmgmt.action_code = TDLS_CHANNEL_SWITCH_REQUEST;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	pattrib = &pmgntframe->attrib;
-+
-+	pmgntframe->frame_tag = DATA_FRAMETAG;
-+	pattrib->ether_type = 0x890d;
-+
-+	_rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);
-+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+
-+	update_tdls_attrib(padapter, pattrib);
-+	pattrib->qsel = pattrib->priority;
-+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) {
-+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+		goto exit;
-+	}
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+	ret = _SUCCESS;
-+exit:
-+
-+	return ret;
-+}
-+
-+int issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack)
-+{
-+	struct xmit_frame	*pmgntframe;
-+	struct pkt_attrib	*pattrib;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
-+	int ret = _FAIL;
-+
-+	RTW_INFO("[TDLS] %s\n", __FUNCTION__);
-+
-+	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
-+		RTW_INFO("[TDLS] Ignore %s since channel switch is not allowed\n", __func__);
-+		goto exit;
-+	}
-+
-+	ptxmgmt->action_code = TDLS_CHANNEL_SWITCH_RESPONSE;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		goto exit;
-+
-+	pattrib = &pmgntframe->attrib;
-+
-+	pmgntframe->frame_tag = DATA_FRAMETAG;
-+	pattrib->ether_type = 0x890d;
-+
-+	_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
-+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ra, ptxmgmt->peer, ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+
-+	update_tdls_attrib(padapter, pattrib);
-+	pattrib->qsel = pattrib->priority;
-+	/*
-+		_enter_critical_bh(&pxmitpriv->lock, &irqL);
-+		if(xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pmgntframe)==_TRUE){
-+			_exit_critical_bh(&pxmitpriv->lock, &irqL);
-+			return _FALSE;
-+		}
-+	*/
-+	if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) {
-+		rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
-+		rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+		goto exit;
-+	}
-+
-+	if (wait_ack)
-+		ret = dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, 10);
-+	else {
-+		dump_mgntframe(padapter, pmgntframe);
-+		ret = _SUCCESS;
-+	}
-+exit:
-+
-+	return ret;
-+}
-+#endif
-+
-+int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	struct sta_info *ptdls_sta = NULL, *psta = rtw_get_stainfo(&(padapter->stapriv), get_bssid(&(padapter->mlmepriv)));
-+	struct recv_priv *precvpriv = &(padapter->recvpriv);
-+	u8 *ptr = precv_frame->u.hdr.rx_data, *psa;
-+	struct rx_pkt_attrib *pattrib = &(precv_frame->u.hdr.attrib);
-+	struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo);
-+	u8 empty_addr[ETH_ALEN] = { 0x00 };
-+	int rssi = 0;
-+	struct tdls_txmgmt txmgmt;
-+	int ret = _SUCCESS;
-+
-+	if (psta)
-+		rssi = psta->cmn.rssi_stat.rssi;
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	/* WFDTDLS: for sigma test, not to setup direct link automatically */
-+	ptdlsinfo->dev_discovered = _TRUE;
-+
-+	psa = get_sa(ptr);
-+	ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), psa);
-+	if (ptdls_sta != NULL)
-+		ptdls_sta->sta_stats.rx_tdls_disc_rsp_pkts++;
-+
-+#ifdef CONFIG_TDLS_AUTOSETUP
-+	if (ptdls_sta != NULL) {
-+		/* Record the tdls sta with lowest signal strength */
-+		if (ptdlsinfo->sta_maximum == _TRUE && ptdls_sta->alive_count >= 1) {
-+			if (_rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN)) {
-+				_rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN);
-+				ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.rx_pwdb_all;
-+			} else {
-+				if (ptdlsinfo->ss_record.RxPWDBAll < pattrib->phy_info.rx_pwdb_all) {
-+					_rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN);
-+					ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.rx_pwdb_all;
-+				}
-+			}
-+		}
-+	} else {
-+		if (ptdlsinfo->sta_maximum == _TRUE) {
-+			if (_rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN)) {
-+				/* All traffics are busy, do not set up another direct link. */
-+				ret = _FAIL;
-+				goto exit;
-+			} else {
-+				if (pattrib->phy_info.rx_pwdb_all > ptdlsinfo->ss_record.RxPWDBAll) {
-+					_rtw_memcpy(txmgmt.peer, ptdlsinfo->ss_record.macaddr, ETH_ALEN);
-+					/* issue_tdls_teardown(padapter, ptdlsinfo->ss_record.macaddr, _FALSE); */
-+				} else {
-+					ret = _FAIL;
-+					goto exit;
-+				}
-+			}
-+		}
-+
-+
-+		if (pattrib->phy_info.rx_pwdb_all + TDLS_SIGNAL_THRESH >= rssi) {
-+			RTW_INFO("pattrib->RxPWDBAll=%d, pdmpriv->undecorated_smoothed_pwdb=%d\n", pattrib->phy_info.rx_pwdb_all, rssi);
-+			_rtw_memcpy(txmgmt.peer, psa, ETH_ALEN);
-+			issue_tdls_setup_req(padapter, &txmgmt, _FALSE);
-+		}
-+	}
-+exit:
-+#endif /* CONFIG_TDLS_AUTOSETUP */
-+
-+	return ret;
-+
-+}
-+
-+sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
-+{
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	u8 *psa, *pmyid;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	_irqL irqL;
-+	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
-+	u8 *prsnie, *ppairwise_cipher;
-+	u8 i, k;
-+	u8 ccmp_included = 0, rsnie_included = 0;
-+	u16 j, pairwise_count;
-+	u8 SNonce[32];
-+	u32 timeout_interval = TDLS_TPK_RESEND_COUNT;
-+	sint parsing_length;	/* Frame body length, without icv_len */
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	u8 FIXED_IE = 5;
-+	unsigned char		supportRate[16];
-+	int				supportRateNum = 0;
-+	struct tdls_txmgmt txmgmt;
-+
-+	if (rtw_tdls_is_setup_allowed(padapter) == _FALSE)
-+		goto exit;
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	psa = get_sa(ptr);
-+
-+	if (ptdlsinfo->sta_maximum == _TRUE) {
-+		if (ptdls_sta == NULL)
-+			goto exit;
-+		else if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE))
-+			goto exit;
-+	}
-+
-+	pmyid = adapter_mac_addr(padapter);
-+	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
-+	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
-+			 - prx_pkt_attrib->hdrlen
-+			 - prx_pkt_attrib->iv_len
-+			 - prx_pkt_attrib->icv_len
-+			 - LLC_HEADER_SIZE
-+			 - ETH_TYPE_LEN
-+			 - PAYLOAD_TYPE_LEN;
-+
-+	if (ptdls_sta == NULL) {
-+		ptdls_sta = rtw_alloc_stainfo(pstapriv, psa);
-+		if (ptdls_sta == NULL)
-+			goto exit;
-+		
-+		ptdlsinfo->sta_cnt++;
-+	}
-+	else {
-+		if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
-+			/* If the direct link is already set up */
-+			/* Process as re-setup after tear down */
-+			RTW_INFO("re-setup a direct link\n");
-+		}
-+		/* Already receiving TDLS setup request */
-+		else if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) {
-+			RTW_INFO("receive duplicated TDLS setup request frame in handshaking\n");
-+			goto exit;
-+		}
-+		/* When receiving and sending setup_req to the same link at the same time */
-+		/* STA with higher MAC_addr would be initiator */
-+		else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) {
-+			RTW_INFO("receive setup_req after sending setup_req\n");
-+			for (i = 0; i < 6; i++) {
-+				if (*(pmyid + i) == *(psa + i)) {
-+				} else if (*(pmyid + i) > *(psa + i)) {
-+					ptdls_sta->tdls_sta_state = TDLS_INITIATOR_STATE;
-+					break;
-+				} else if (*(pmyid + i) < *(psa + i))
-+					goto exit;
-+			}
-+		}
-+	}
-+
-+	if (ptdls_sta) {
-+		txmgmt.dialog_token = *(ptr + 2);	/* Copy dialog token */
-+		txmgmt.status_code = _STATS_SUCCESSFUL_;
-+
-+		/* Parsing information element */
-+		for (j = FIXED_IE; j < parsing_length;) {
-+
-+			pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
-+
-+			switch (pIE->ElementID) {
-+			case _SUPPORTEDRATES_IE_:
-+				_rtw_memcpy(supportRate, pIE->data, pIE->Length);
-+				supportRateNum = pIE->Length;
-+				break;
-+			case _COUNTRY_IE_:
-+				break;
-+			case _EXT_SUPPORTEDRATES_IE_:
-+				if (supportRateNum < sizeof(supportRate)) {
-+					_rtw_memcpy(supportRate + supportRateNum, pIE->data, pIE->Length);
-+					supportRateNum += pIE->Length;
-+				}
-+				break;
-+			case _SUPPORTED_CH_IE_:
-+				break;
-+			case _RSN_IE_2_:
-+				rsnie_included = 1;
-+				if (prx_pkt_attrib->encrypt) {
-+					prsnie = (u8 *)pIE;
-+					/* Check CCMP pairwise_cipher presence. */
-+					ppairwise_cipher = prsnie + 10;
-+					_rtw_memcpy(ptdls_sta->TDLS_RSNIE, pIE->data, pIE->Length);
-+					pairwise_count = *(u16 *)(ppairwise_cipher - 2);
-+					for (k = 0; k < pairwise_count; k++) {
-+						if (_rtw_memcmp(ppairwise_cipher + 4 * k, RSN_CIPHER_SUITE_CCMP, 4) == _TRUE)
-+							ccmp_included = 1;
-+					}
-+
-+					if (ccmp_included == 0)
-+						txmgmt.status_code = _STATS_INVALID_RSNIE_;
-+				}
-+				break;
-+			case _EXT_CAP_IE_:
-+				break;
-+			case _VENDOR_SPECIFIC_IE_:
-+				break;
-+			case _FTIE_:
-+				if (prx_pkt_attrib->encrypt)
-+					_rtw_memcpy(SNonce, (ptr + j + 52), 32);
-+				break;
-+			case _TIMEOUT_ITVL_IE_:
-+				if (prx_pkt_attrib->encrypt)
-+					timeout_interval = cpu_to_le32(*(u32 *)(ptr + j + 3));
-+				break;
-+			case _RIC_Descriptor_IE_:
-+				break;
-+#ifdef CONFIG_80211N_HT
-+			case _HT_CAPABILITY_IE_:
-+				rtw_tdls_process_ht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);
-+				break;
-+#endif
-+#ifdef CONFIG_80211AC_VHT
-+			case EID_AID:
-+				break;
-+			case EID_VHTCapability:
-+				rtw_tdls_process_vht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);
-+				break;
-+#endif
-+			case EID_BSSCoexistence:
-+				break;
-+			case _LINK_ID_IE_:
-+				if (_rtw_memcmp(get_bssid(pmlmepriv), pIE->data, 6) == _FALSE)
-+					txmgmt.status_code = _STATS_NOT_IN_SAME_BSS_;
-+				break;
-+			default:
-+				break;
-+			}
-+
-+			j += (pIE->Length + 2);
-+
-+		}
-+
-+		/* Check status code */
-+		/* If responder STA has/hasn't security on AP, but request hasn't/has RSNIE, it should reject */
-+		if (txmgmt.status_code == _STATS_SUCCESSFUL_) {
-+			if (rsnie_included && prx_pkt_attrib->encrypt == 0)
-+				txmgmt.status_code = _STATS_SEC_DISABLED_;
-+			else if (rsnie_included == 0 && prx_pkt_attrib->encrypt)
-+				txmgmt.status_code = _STATS_INVALID_PARAMETERS_;
-+
-+#ifdef CONFIG_WFD
-+			/* WFD test plan version 0.18.2 test item 5.1.5 */
-+			/* SoUT does not use TDLS if AP uses weak security */
-+			if (padapter->wdinfo.wfd_tdls_enable && (rsnie_included && prx_pkt_attrib->encrypt != _AES_))
-+				txmgmt.status_code = _STATS_SEC_DISABLED_;
-+#endif /* CONFIG_WFD */
-+		}
-+
-+		ptdls_sta->tdls_sta_state |= TDLS_INITIATOR_STATE;
-+		if (prx_pkt_attrib->encrypt) {
-+			_rtw_memcpy(ptdls_sta->SNonce, SNonce, 32);
-+
-+			if (timeout_interval <= 300)
-+				ptdls_sta->TDLS_PeerKey_Lifetime = TDLS_TPK_RESEND_COUNT;
-+			else
-+				ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;
-+		}
-+
-+		/* Update station supportRate */
-+		ptdls_sta->bssratelen = supportRateNum;
-+		_rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum);
-+
-+		/* -2: AP + BC/MC sta, -4: default key */
-+		if (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM)
-+			ptdlsinfo->sta_maximum = _TRUE;
-+
-+#ifdef CONFIG_WFD
-+		rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length);
-+#endif
-+
-+	} else
-+		goto exit;
-+
-+	_rtw_memcpy(txmgmt.peer, prx_pkt_attrib->src, ETH_ALEN);
-+
-+	if (rtw_tdls_is_driver_setup(padapter)) {
-+		issue_tdls_setup_rsp(padapter, &txmgmt);
-+
-+		if (txmgmt.status_code == _STATS_SUCCESSFUL_)
-+			_set_timer(&ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME);
-+		else {
-+			rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
-+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
-+		}
-+	}
-+
-+exit:
-+
-+	return _SUCCESS;
-+}
-+
-+int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
-+{
-+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	_irqL irqL;
-+	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
-+	u8 *psa;
-+	u16 status_code = 0;
-+	sint parsing_length;	/* Frame body length, without icv_len */
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	u8 FIXED_IE = 7;
-+	u8 ANonce[32];
-+	u8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL, *ppairwise_cipher = NULL;
-+	u16 pairwise_count, j, k;
-+	u8 verify_ccmp = 0;
-+	unsigned char		supportRate[16];
-+	int				supportRateNum = 0;
-+	struct tdls_txmgmt txmgmt;
-+	int ret = _SUCCESS;
-+	u32 timeout_interval = TDLS_TPK_RESEND_COUNT;
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	psa = get_sa(ptr);
-+
-+	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
-+	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
-+			 - prx_pkt_attrib->hdrlen
-+			 - prx_pkt_attrib->iv_len
-+			 - prx_pkt_attrib->icv_len
-+			 - LLC_HEADER_SIZE
-+			 - ETH_TYPE_LEN
-+			 - PAYLOAD_TYPE_LEN;
-+
-+	_rtw_memcpy(&status_code, ptr + 2, 2);
-+
-+	if (status_code != 0) {
-+		RTW_INFO("[TDLS] %s status_code = %d, free_tdls_sta\n", __FUNCTION__, status_code);
-+		rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
-+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	status_code = 0;
-+
-+	/* parsing information element */
-+	for (j = FIXED_IE; j < parsing_length;) {
-+		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
-+
-+		switch (pIE->ElementID) {
-+		case _SUPPORTEDRATES_IE_:
-+			_rtw_memcpy(supportRate, pIE->data, pIE->Length);
-+			supportRateNum = pIE->Length;
-+			break;
-+		case _COUNTRY_IE_:
-+			break;
-+		case _EXT_SUPPORTEDRATES_IE_:
-+			if (supportRateNum < sizeof(supportRate)) {
-+				_rtw_memcpy(supportRate + supportRateNum, pIE->data, pIE->Length);
-+				supportRateNum += pIE->Length;
-+			}
-+			break;
-+		case _SUPPORTED_CH_IE_:
-+			break;
-+		case _RSN_IE_2_:
-+			prsnie = (u8 *)pIE;
-+			/* Check CCMP pairwise_cipher presence. */
-+			ppairwise_cipher = prsnie + 10;
-+			_rtw_memcpy(&pairwise_count, (u16 *)(ppairwise_cipher - 2), 2);
-+			for (k = 0; k < pairwise_count; k++) {
-+				if (_rtw_memcmp(ppairwise_cipher + 4 * k, RSN_CIPHER_SUITE_CCMP, 4) == _TRUE)
-+					verify_ccmp = 1;
-+			}
-+		case _EXT_CAP_IE_:
-+			break;
-+		case _VENDOR_SPECIFIC_IE_:
-+			if (_rtw_memcmp((u8 *)pIE + 2, WMM_INFO_OUI, 6) == _TRUE) {
-+				/* WMM Info ID and OUI */
-+				if ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE))
-+					ptdls_sta->qos_option = _TRUE;
-+			}
-+			break;
-+		case _FTIE_:
-+			pftie = (u8 *)pIE;
-+			_rtw_memcpy(ANonce, (ptr + j + 20), 32);
-+			break;
-+		case _TIMEOUT_ITVL_IE_:
-+			ptimeout_ie = (u8 *)pIE;
-+			timeout_interval = cpu_to_le32(*(u32 *)(ptimeout_ie + 3));
-+			break;
-+		case _RIC_Descriptor_IE_:
-+			break;
-+#ifdef CONFIG_80211N_HT
-+		case _HT_CAPABILITY_IE_:
-+			rtw_tdls_process_ht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);
-+			break;
-+#endif
-+#ifdef CONFIG_80211AC_VHT
-+		case EID_AID:
-+			/* todo in the future if necessary */
-+			break;
-+		case EID_VHTCapability:
-+			rtw_tdls_process_vht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);
-+			break;
-+		case EID_OpModeNotification:
-+			rtw_tdls_process_vht_op_mode_notify(padapter, ptdls_sta, pIE->data, pIE->Length);
-+			break;
-+#endif
-+		case EID_BSSCoexistence:
-+			break;
-+		case _LINK_ID_IE_:
-+			plinkid_ie = (u8 *)pIE;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+		j += (pIE->Length + 2);
-+
-+	}
-+
-+	ptdls_sta->bssratelen = supportRateNum;
-+	_rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum);
-+	_rtw_memcpy(ptdls_sta->ANonce, ANonce, 32);
-+
-+#ifdef CONFIG_WFD
-+	rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length);
-+#endif
-+
-+	if (prx_pkt_attrib->encrypt) {
-+		if (verify_ccmp == 1) {
-+			txmgmt.status_code = _STATS_SUCCESSFUL_;
-+			if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
-+				wpa_tdls_generate_tpk(padapter, ptdls_sta);
-+				if (tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL) {
-+					RTW_INFO("[TDLS] %s tdls_verify_mic fail, free_tdls_sta\n", __FUNCTION__);
-+					rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
-+					rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
-+					ret = _FAIL;
-+					goto exit;
-+				}
-+				ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;
-+			}
-+		} else
-+			txmgmt.status_code = _STATS_INVALID_RSNIE_;
-+	} else
-+		txmgmt.status_code = _STATS_SUCCESSFUL_;
-+
-+	if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
-+		_rtw_memcpy(txmgmt.peer, prx_pkt_attrib->src, ETH_ALEN);
-+		issue_tdls_setup_cfm(padapter, &txmgmt);
-+
-+		if (txmgmt.status_code == _STATS_SUCCESSFUL_) {
-+			rtw_tdls_set_link_established(padapter, _TRUE);
-+
-+			if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) {
-+				ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;
-+				ptdls_sta->state |= WIFI_ASOC_STATE;
-+				_cancel_timer_ex(&ptdls_sta->handshake_timer);
-+			}
-+
-+			if (prx_pkt_attrib->encrypt)
-+				rtw_tdls_set_key(padapter, ptdls_sta);
-+
-+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED);
-+
-+		}
-+	}
-+
-+exit:
-+	if (rtw_tdls_is_driver_setup(padapter) == _TRUE)
-+		return ret;
-+	else
-+		return _SUCCESS;
-+
-+}
-+
-+int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
-+{
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	_irqL irqL;
-+	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
-+	u8 *psa;
-+	u16 status_code = 0;
-+	sint parsing_length;
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	u8 FIXED_IE = 5;
-+	u8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL, *ppairwise_cipher = NULL;
-+	u16 j, pairwise_count;
-+	int ret = _SUCCESS;
-+
-+	psa = get_sa(ptr);
-+
-+	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
-+	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
-+			 - prx_pkt_attrib->hdrlen
-+			 - prx_pkt_attrib->iv_len
-+			 - prx_pkt_attrib->icv_len
-+			 - LLC_HEADER_SIZE
-+			 - ETH_TYPE_LEN
-+			 - PAYLOAD_TYPE_LEN;
-+
-+	_rtw_memcpy(&status_code, ptr + 2, 2);
-+
-+	if (status_code != 0) {
-+		RTW_INFO("[%s] status_code = %d\n, free_tdls_sta", __FUNCTION__, status_code);
-+		rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
-+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	/* Parsing information element */
-+	for (j = FIXED_IE; j < parsing_length;) {
-+
-+		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
-+
-+		switch (pIE->ElementID) {
-+		case _RSN_IE_2_:
-+			prsnie = (u8 *)pIE;
-+			break;
-+		case _VENDOR_SPECIFIC_IE_:
-+			if (_rtw_memcmp((u8 *)pIE + 2, WMM_PARA_OUI, 6) == _TRUE) {
-+				/* WMM Parameter ID and OUI */
-+				ptdls_sta->qos_option = _TRUE;
-+			}
-+			break;
-+		case _FTIE_:
-+			pftie = (u8 *)pIE;
-+			break;
-+		case _TIMEOUT_ITVL_IE_:
-+			ptimeout_ie = (u8 *)pIE;
-+			break;
-+#ifdef CONFIG_80211N_HT
-+		case _HT_EXTRA_INFO_IE_:
-+			break;
-+#endif
-+#ifdef CONFIG_80211AC_VHT
-+		case EID_VHTOperation:
-+			rtw_tdls_process_vht_operation(padapter, ptdls_sta, pIE->data, pIE->Length);
-+			break;
-+		case EID_OpModeNotification:
-+			rtw_tdls_process_vht_op_mode_notify(padapter, ptdls_sta, pIE->data, pIE->Length);
-+			break;
-+#endif
-+		case _LINK_ID_IE_:
-+			plinkid_ie = (u8 *)pIE;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+		j += (pIE->Length + 2);
-+
-+	}
-+
-+	if (prx_pkt_attrib->encrypt) {
-+		/* Verify mic in FTIE MIC field */
-+		if (rtw_tdls_is_driver_setup(padapter) &&
-+		    (tdls_verify_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL)) {
-+			rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
-+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
-+			ret = _FAIL;
-+			goto exit;
-+		}
-+	}
-+
-+	if (rtw_tdls_is_driver_setup(padapter)) {
-+		rtw_tdls_set_link_established(padapter, _TRUE);
-+
-+		if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) {
-+			ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;
-+			ptdls_sta->state |= WIFI_ASOC_STATE;
-+			_cancel_timer_ex(&ptdls_sta->handshake_timer);
-+		}
-+
-+		if (prx_pkt_attrib->encrypt) {
-+			rtw_tdls_set_key(padapter, ptdls_sta);
-+
-+			/* Start  TPK timer */
-+			ptdls_sta->TPK_count = 0;
-+			_set_timer(&ptdls_sta->TPK_timer, ONE_SEC);
-+		}
-+
-+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED);
-+	}
-+
-+exit:
-+	return ret;
-+
-+}
-+
-+int On_TDLS_Dis_Req(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *psta_ap;
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	sint parsing_length;	/* Frame body length, without icv_len */
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	u8 FIXED_IE = 3, *dst;
-+	u16 j;
-+	struct tdls_txmgmt txmgmt;
-+	int ret = _SUCCESS;
-+
-+	if (rtw_tdls_is_driver_setup(padapter) == _FALSE)
-+		goto exit;
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
-+	txmgmt.dialog_token = *(ptr + 2);
-+	_rtw_memcpy(&txmgmt.peer, precv_frame->u.hdr.attrib.src, ETH_ALEN);
-+	txmgmt.action_code = TDLS_DISCOVERY_RESPONSE;
-+	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
-+			 - prx_pkt_attrib->hdrlen
-+			 - prx_pkt_attrib->iv_len
-+			 - prx_pkt_attrib->icv_len
-+			 - LLC_HEADER_SIZE
-+			 - ETH_TYPE_LEN
-+			 - PAYLOAD_TYPE_LEN;
-+
-+	/* Parsing information element */
-+	for (j = FIXED_IE; j < parsing_length;) {
-+
-+		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
-+
-+		switch (pIE->ElementID) {
-+		case _LINK_ID_IE_:
-+			psta_ap = rtw_get_stainfo(pstapriv, pIE->data);
-+			if (psta_ap == NULL)
-+				goto exit;
-+			dst = pIE->data + 12;
-+			if (MacAddr_isBcst(dst) == _FALSE && (_rtw_memcmp(adapter_mac_addr(padapter), dst, ETH_ALEN) == _FALSE))
-+				goto exit;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+		j += (pIE->Length + 2);
-+
-+	}
-+
-+	issue_tdls_dis_rsp(padapter, &txmgmt, prx_pkt_attrib->privacy);
-+
-+exit:
-+	return ret;
-+
-+}
-+
-+int On_TDLS_Teardown(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
-+{
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct sta_priv	*pstapriv = &padapter->stapriv;
-+	_irqL irqL;
-+	u8 reason;
-+
-+	reason = *(ptr + prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN + 2);
-+	RTW_INFO("[TDLS] %s Reason code(%d)\n", __FUNCTION__, reason);
-+
-+	if (rtw_tdls_is_driver_setup(padapter)) {
-+		rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
-+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
-+	}
-+
-+	return _SUCCESS;
-+
-+}
-+
-+#if 0
-+u8 TDLS_check_ch_state(uint state)
-+{
-+	if (state & TDLS_CH_SWITCH_ON_STATE &&
-+	    state & TDLS_PEER_AT_OFF_STATE) {
-+		if (state & TDLS_PEER_SLEEP_STATE)
-+			return 2;	/* U-APSD + ch. switch */
-+		else
-+			return 1;	/* ch. switch */
-+	} else
-+		return 0;
-+}
-+#endif
-+
-+int On_TDLS_Peer_Traffic_Indication(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
-+{
-+	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	struct tdls_txmgmt txmgmt;
-+
-+	ptr += pattrib->hdrlen + pattrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+
-+		txmgmt.dialog_token = *(ptr + 2);
-+		issue_tdls_peer_traffic_rsp(padapter, ptdls_sta, &txmgmt);
-+		/* issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0); */
-+
-+	return _SUCCESS;
-+}
-+
-+/* We process buffered data for 1. U-APSD, 2. ch. switch, 3. U-APSD + ch. switch here */
-+int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
-+{
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct rx_pkt_attrib	*pattrib = &precv_frame->u.hdr.attrib;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	u8 wmmps_ac = 0;
-+	/* u8 state=TDLS_check_ch_state(ptdls_sta->tdls_sta_state); */
-+	int i;
-+
-+	ptdls_sta->sta_stats.rx_data_pkts++;
-+
-+	ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE);
-+
-+	/* Check 4-AC queue bit */
-+	if (ptdls_sta->uapsd_vo || ptdls_sta->uapsd_vi || ptdls_sta->uapsd_be || ptdls_sta->uapsd_bk)
-+		wmmps_ac = 1;
-+
-+	/* If it's a direct link and have buffered frame */
-+	if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
-+		if (wmmps_ac) {
-+			_irqL irqL;
-+			_list	*xmitframe_plist, *xmitframe_phead;
-+			struct xmit_frame *pxmitframe = NULL;
-+
-+			_enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
-+
-+			xmitframe_phead = get_list_head(&ptdls_sta->sleep_q);
-+			xmitframe_plist = get_next(xmitframe_phead);
-+
-+			/* transmit buffered frames */
-+			while (rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist) == _FALSE) {
-+				pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
-+				xmitframe_plist = get_next(xmitframe_plist);
-+				rtw_list_delete(&pxmitframe->list);
-+
-+				ptdls_sta->sleepq_len--;
-+				ptdls_sta->sleepq_ac_len--;
-+				if (ptdls_sta->sleepq_len > 0) {
-+					pxmitframe->attrib.mdata = 1;
-+					pxmitframe->attrib.eosp = 0;
-+				} else {
-+					pxmitframe->attrib.mdata = 0;
-+					pxmitframe->attrib.eosp = 1;
-+				}
-+				pxmitframe->attrib.triggered = 1;
-+
-+				rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
-+			}
-+
-+			if (ptdls_sta->sleepq_len == 0)
-+				RTW_INFO("no buffered packets for tdls to xmit\n");
-+			else {
-+				RTW_INFO("error!psta->sleepq_len=%d\n", ptdls_sta->sleepq_len);
-+				ptdls_sta->sleepq_len = 0;
-+			}
-+
-+			_exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
-+
-+		}
-+
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+#ifdef CONFIG_TDLS_CH_SW
-+sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
-+{
-+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
-+	sint parsing_length;
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	u8 FIXED_IE = 4;
-+	u16 j;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
-+	u16 switch_time = TDLS_CH_SWITCH_TIME * 1000, switch_timeout = TDLS_CH_SWITCH_TIMEOUT * 1000;
-+	u8 take_care_iqk;
-+
-+	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
-+		RTW_INFO("[TDLS] Ignore %s since channel switch is not allowed\n", __func__);
-+		return _FAIL;
-+	}
-+
-+	ptdls_sta->ch_switch_time = switch_time;
-+	ptdls_sta->ch_switch_timeout = switch_timeout;
-+
-+	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
-+	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
-+			 - prx_pkt_attrib->hdrlen
-+			 - prx_pkt_attrib->iv_len
-+			 - prx_pkt_attrib->icv_len
-+			 - LLC_HEADER_SIZE
-+			 - ETH_TYPE_LEN
-+			 - PAYLOAD_TYPE_LEN;
-+
-+	pchsw_info->off_ch_num = *(ptr + 2);
-+
-+	if ((*(ptr + 2) == 2) && (hal_is_band_support(padapter, BAND_ON_5G)))
-+		pchsw_info->off_ch_num = 44;
-+
-+	if (pchsw_info->off_ch_num != pmlmeext->cur_channel)
-+		pchsw_info->delay_switch_back = _FALSE;
-+
-+	/* Parsing information element */
-+	for (j = FIXED_IE; j < parsing_length;) {
-+		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
-+
-+		switch (pIE->ElementID) {
-+		case EID_SecondaryChnlOffset:
-+			switch (*(pIE->data)) {
-+			case EXTCHNL_OFFSET_UPPER:
-+				pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+				break;
-+
-+			case EXTCHNL_OFFSET_LOWER:
-+				pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+				break;
-+
-+			default:
-+				pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+				break;
-+			}
-+			break;
-+		case _LINK_ID_IE_:
-+			break;
-+		case _CH_SWITCH_TIMING_:
-+			ptdls_sta->ch_switch_time = (RTW_GET_LE16(pIE->data) >= TDLS_CH_SWITCH_TIME * 1000) ?
-+				RTW_GET_LE16(pIE->data) : TDLS_CH_SWITCH_TIME * 1000;
-+			ptdls_sta->ch_switch_timeout = (RTW_GET_LE16(pIE->data + 2) >= TDLS_CH_SWITCH_TIMEOUT * 1000) ?
-+				RTW_GET_LE16(pIE->data + 2) : TDLS_CH_SWITCH_TIMEOUT * 1000;
-+			RTW_INFO("[TDLS] %s ch_switch_time:%d, ch_switch_timeout:%d\n"
-+				, __FUNCTION__, RTW_GET_LE16(pIE->data), RTW_GET_LE16(pIE->data + 2));
-+		default:
-+			break;
-+		}
-+
-+		j += (pIE->Length + 2);
-+	}
-+
-+#ifndef CONFIG_TDLS_CH_SW_V2
-+	rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
-+	if (take_care_iqk == _TRUE) {
-+		u8 central_chnl;
-+		u8 bw_mode;
-+
-+		bw_mode = (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20;
-+		central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset);
-+		if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) < 0) {
-+			if (!(pchsw_info->ch_sw_state & TDLS_CH_SWITCH_PREPARE_STATE))
-+				rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE);
-+
-+			return _FAIL;
-+		}
-+	}
-+#endif
-+
-+	/* cancel ch sw monitor timer for responder */
-+	if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
-+		_cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer);
-+
-+	if (_rtw_memcmp(pchsw_info->addr, zaddr, ETH_ALEN) == _TRUE)
-+		_rtw_memcpy(pchsw_info->addr, ptdls_sta->cmn.mac_addr, ETH_ALEN);
-+
-+	if (ATOMIC_READ(&pchsw_info->chsw_on) == _FALSE)
-+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);
-+
-+	rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_RESP);
-+
-+	return _SUCCESS;
-+}
-+
-+sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
-+{
-+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	u8 *ptr = precv_frame->u.hdr.rx_data;
-+	struct rx_pkt_attrib	*prx_pkt_attrib = &precv_frame->u.hdr.attrib;
-+	sint parsing_length;
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	u8 FIXED_IE = 4;
-+	u16 status_code, j, switch_time, switch_timeout;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	int ret = _SUCCESS;
-+
-+	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
-+		RTW_INFO("[TDLS] Ignore %s since channel switch is not allowed\n", __func__);
-+		return _SUCCESS;
-+	}
-+
-+	/* If we receive Unsolicited TDLS Channel Switch Response when channel switch is running, */
-+	/* we will go back to base channel and terminate this channel switch procedure */
-+	if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) {
-+		if (pmlmeext->cur_channel != rtw_get_oper_ch(padapter)) {
-+			RTW_INFO("[TDLS] Rx unsolicited channel switch response\n");
-+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);
-+			goto exit;
-+		}
-+	}
-+
-+	ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
-+	parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
-+			 - prx_pkt_attrib->hdrlen
-+			 - prx_pkt_attrib->iv_len
-+			 - prx_pkt_attrib->icv_len
-+			 - LLC_HEADER_SIZE
-+			 - ETH_TYPE_LEN
-+			 - PAYLOAD_TYPE_LEN;
-+
-+	_rtw_memcpy(&status_code, ptr + 2, 2);
-+
-+	if (status_code != 0) {
-+		RTW_INFO("[TDLS] %s status_code:%d\n", __func__, status_code);
-+		pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE);
-+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END);
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	/* Parsing information element */
-+	for (j = FIXED_IE; j < parsing_length;) {
-+		pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j);
-+
-+		switch (pIE->ElementID) {
-+		case _LINK_ID_IE_:
-+			break;
-+		case _CH_SWITCH_TIMING_:
-+			_rtw_memcpy(&switch_time, pIE->data, 2);
-+			if (switch_time > ptdls_sta->ch_switch_time)
-+				_rtw_memcpy(&ptdls_sta->ch_switch_time, &switch_time, 2);
-+
-+			_rtw_memcpy(&switch_timeout, pIE->data + 2, 2);
-+			if (switch_timeout > ptdls_sta->ch_switch_timeout)
-+				_rtw_memcpy(&ptdls_sta->ch_switch_timeout, &switch_timeout, 2);
-+			break;
-+		default:
-+			break;
-+		}
-+
-+		j += (pIE->Length + 2);
-+	}
-+
-+	if ((pmlmeext->cur_channel == rtw_get_oper_ch(padapter)) &&
-+	    (pchsw_info->ch_sw_state & TDLS_WAIT_CH_RSP_STATE)) {
-+		if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE)
-+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL);
-+	}
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_TDLS_CH_SW */
-+
-+#ifdef CONFIG_WFD
-+void wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen)
-+{
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct wifi_display_info	*pwfd_info = padapter->tdlsinfo.wfd_info;
-+	u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
-+	u32 wfdielen = 0;
-+	u16 v16 = 0;
-+
-+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
-+		return;
-+
-+	/* WFD OUI */
-+	wfdielen = 0;
-+	wfdie[wfdielen++] = 0x50;
-+	wfdie[wfdielen++] = 0x6F;
-+	wfdie[wfdielen++] = 0x9A;
-+	wfdie[wfdielen++] = 0x0A;	/* WFA WFD v1.0 */
-+
-+	/*
-+	 *	Commented by Albert 20110825
-+	 *	According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes
-+	 *	1. WFD Device Information
-+	 *	2. Associated BSSID ( Optional )
-+	 *	3. Local IP Adress ( Optional )
-+	 */
-+
-+	/* WFD Device Information ATTR */
-+	/* Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO;
-+
-+	/* Length: */
-+	/* Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/* Value1: */
-+	/* WFD device information */
-+	/* available for WFD session + Preferred TDLS + WSD ( WFD Service Discovery ) */
-+	v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL
-+		| WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_WSD;
-+	RTW_PUT_BE16(wfdie + wfdielen, v16);
-+	wfdielen += 2;
-+
-+	/* Value2: */
-+	/* Session Management Control Port */
-+	/* Default TCP port for RTSP messages is 554 */
-+	RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->tdls_rtsp_ctrlport);
-+	wfdielen += 2;
-+
-+	/* Value3: */
-+	/* WFD Device Maximum Throughput */
-+	/* 300Mbps is the maximum throughput */
-+	RTW_PUT_BE16(wfdie + wfdielen, 300);
-+	wfdielen += 2;
-+
-+	/* Associated BSSID ATTR */
-+	/* Type: */
-+	wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID;
-+
-+	/* Length: */
-+	/* Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0006);
-+	wfdielen += 2;
-+
-+	/* Value: */
-+	/* Associated BSSID */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+		_rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN);
-+	else
-+		_rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN);
-+
-+	/* Local IP Address ATTR */
-+	wfdie[wfdielen++] = WFD_ATTR_LOCAL_IP_ADDR;
-+
-+	/* Length: */
-+	/* Note: In the WFD specification, the size of length field is 2. */
-+	RTW_PUT_BE16(wfdie + wfdielen, 0x0005);
-+	wfdielen += 2;
-+
-+	/* Version: */
-+	/* 0x01: Version1;IPv4 */
-+	wfdie[wfdielen++] = 0x01;
-+
-+	/* IPv4 Address */
-+	_rtw_memcpy(wfdie + wfdielen, pwfd_info->ip_address, 4);
-+	wfdielen += 4;
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, pktlen);
-+
-+}
-+#endif /* CONFIG_WFD */
-+
-+void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+	int i = 0 ;
-+	u32 time;
-+	u8 *pframe_head;
-+
-+	/* SNonce */
-+	if (pattrib->encrypt) {
-+		for (i = 0; i < 8; i++) {
-+			time = rtw_get_current_time();
-+			_rtw_memcpy(&ptdls_sta->SNonce[4 * i], (u8 *)&time, 4);
-+		}
-+	}
-+
-+	pframe_head = pframe;	/* For rtw_tdls_set_ht_cap() */
-+
-+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
-+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
-+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
-+	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
-+
-+	pframe = rtw_tdls_set_capability(padapter, pframe, pattrib);
-+	pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);
-+	pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);
-+	pframe = rtw_tdls_set_sup_reg_class(pframe, pattrib);
-+
-+	if (pattrib->encrypt)
-+		pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib,  _TRUE, ptdls_sta);
-+
-+	pframe = rtw_tdls_set_ext_cap(pframe, pattrib);
-+
-+	if (pattrib->encrypt) {
-+		pframe = rtw_tdls_set_ftie(ptxmgmt
-+					   , pframe
-+					   , pattrib
-+					   , NULL
-+					   , ptdls_sta->SNonce);
-+
-+		pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta);
-+	}
-+
-+#ifdef CONFIG_80211N_HT
-+	/* Sup_reg_classes(optional) */
-+	if (pregistrypriv->ht_enable == _TRUE)
-+		pframe = rtw_tdls_set_ht_cap(padapter, pframe_head, pattrib);
-+#endif
-+
-+	pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);
-+
-+	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
-+
-+	if ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE))
-+		pframe = rtw_tdls_set_qos_cap(pframe, pattrib);
-+
-+#ifdef CONFIG_80211AC_VHT
-+	if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14)
-+	    && REGSTY_IS_11AC_ENABLE(pregistrypriv)
-+	    && is_supported_vht(pregistrypriv->wireless_mode)
-+	    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
-+	   ) {
-+		pframe = rtw_tdls_set_aid(padapter, pframe, pattrib);
-+		pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib);
-+	}
-+#endif
-+
-+#ifdef CONFIG_WFD
-+	if (padapter->wdinfo.wfd_tdls_enable == 1)
-+		wfd_ie_tdls(padapter, pframe, &(pattrib->pktlen));
-+#endif
-+
-+}
-+
-+void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+	u8 k; /* for random ANonce */
-+	u8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL;
-+	u32 time;
-+	u8 *pframe_head;
-+
-+	if (pattrib->encrypt) {
-+		for (k = 0; k < 8; k++) {
-+			time = rtw_get_current_time();
-+			_rtw_memcpy(&ptdls_sta->ANonce[4 * k], (u8 *)&time, 4);
-+		}
-+	}
-+
-+	pframe_head = pframe;
-+
-+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
-+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
-+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
-+	pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);
-+
-+	if (ptxmgmt->status_code != 0) {
-+		RTW_INFO("[%s] status_code:%04x\n", __FUNCTION__, ptxmgmt->status_code);
-+		return;
-+	}
-+
-+	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
-+	pframe = rtw_tdls_set_capability(padapter, pframe, pattrib);
-+	pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);
-+	pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);
-+	pframe = rtw_tdls_set_sup_reg_class(pframe, pattrib);
-+
-+	if (pattrib->encrypt) {
-+		prsnie = pframe;
-+		pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib,  _FALSE, ptdls_sta);
-+	}
-+
-+	pframe = rtw_tdls_set_ext_cap(pframe, pattrib);
-+
-+	if (pattrib->encrypt) {
-+		if (rtw_tdls_is_driver_setup(padapter) == _TRUE)
-+			wpa_tdls_generate_tpk(padapter, ptdls_sta);
-+
-+		pftie = pframe;
-+		pftie_mic = pframe + 4;
-+		pframe = rtw_tdls_set_ftie(ptxmgmt
-+					   , pframe
-+					   , pattrib
-+					   , ptdls_sta->ANonce
-+					   , ptdls_sta->SNonce);
-+
-+		ptimeout_ie = pframe;
-+		pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _FALSE, ptdls_sta);
-+	}
-+
-+#ifdef CONFIG_80211N_HT
-+	/* Sup_reg_classes(optional) */
-+	if (pregistrypriv->ht_enable == _TRUE)
-+		pframe = rtw_tdls_set_ht_cap(padapter, pframe_head, pattrib);
-+#endif
-+
-+	pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);
-+
-+	plinkid_ie = pframe;
-+	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
-+
-+	/* Fill FTIE mic */
-+	if (pattrib->encrypt && rtw_tdls_is_driver_setup(padapter) == _TRUE)
-+		wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic);
-+
-+	if ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE))
-+		pframe = rtw_tdls_set_qos_cap(pframe, pattrib);
-+
-+#ifdef CONFIG_80211AC_VHT
-+	if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14)
-+	    && REGSTY_IS_11AC_ENABLE(pregistrypriv)
-+	    && is_supported_vht(pregistrypriv->wireless_mode)
-+	    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
-+	   ) {
-+		pframe = rtw_tdls_set_aid(padapter, pframe, pattrib);
-+		pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib);
-+		pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode);
-+	}
-+#endif
-+
-+#ifdef CONFIG_WFD
-+	if (padapter->wdinfo.wfd_tdls_enable)
-+		wfd_ie_tdls(padapter, pframe, &(pattrib->pktlen));
-+#endif
-+
-+}
-+
-+void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+
-+	unsigned int ie_len;
-+	unsigned char *p;
-+	u8 wmm_param_ele[24] = {0};
-+	u8  *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL;
-+
-+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
-+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
-+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
-+	pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);
-+	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
-+
-+	if (ptxmgmt->status_code != 0)
-+		return;
-+
-+	if (pattrib->encrypt) {
-+		prsnie = pframe;
-+		pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta);
-+	}
-+
-+	if (pattrib->encrypt) {
-+		pftie = pframe;
-+		pftie_mic = pframe + 4;
-+		pframe = rtw_tdls_set_ftie(ptxmgmt
-+					   , pframe
-+					   , pattrib
-+					   , ptdls_sta->ANonce
-+					   , ptdls_sta->SNonce);
-+
-+		ptimeout_ie = pframe;
-+		pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta);
-+
-+		if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
-+			/* Start TPK timer */
-+			ptdls_sta->TPK_count = 0;
-+			_set_timer(&ptdls_sta->TPK_timer, ONE_SEC);
-+		}
-+	}
-+
-+	/* HT operation; todo */
-+
-+	plinkid_ie = pframe;
-+	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
-+
-+	if (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE))
-+		wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic);
-+
-+	if (ptdls_sta->qos_option == _TRUE)
-+		pframe = rtw_tdls_set_wmm_params(padapter, pframe, pattrib);
-+
-+#ifdef CONFIG_80211AC_VHT
-+	if ((padapter->mlmepriv.htpriv.ht_option == _TRUE)
-+	    && (ptdls_sta->vhtpriv.vht_option == _TRUE) && (pmlmeext->cur_channel > 14)
-+	    && REGSTY_IS_11AC_ENABLE(pregistrypriv)
-+	    && is_supported_vht(pregistrypriv->wireless_mode)
-+	    && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
-+	   ) {
-+		pframe = rtw_tdls_set_vht_operation(padapter, pframe, pattrib, pmlmeext->cur_channel);
-+		pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode);
-+	}
-+#endif
-+}
-+
-+void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
-+{
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+	u8  *pftie = NULL, *pftie_mic = NULL, *plinkid_ie = NULL;
-+
-+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
-+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
-+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
-+	pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);
-+
-+	if (pattrib->encrypt) {
-+		pftie = pframe;
-+		pftie_mic = pframe + 4;
-+		pframe = rtw_tdls_set_ftie(ptxmgmt
-+					   , pframe
-+					   , pattrib
-+					   , ptdls_sta->ANonce
-+					   , ptdls_sta->SNonce);
-+	}
-+
-+	plinkid_ie = pframe;
-+	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
-+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
-+	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
-+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
-+
-+	if (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE))
-+		wpa_tdls_teardown_ftie_mic(ptdls_sta->tpk.kck, plinkid_ie, ptxmgmt->status_code, 1, 4, pftie, pftie_mic);
-+}
-+
-+void rtw_build_tdls_dis_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
-+{
-+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
-+
-+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
-+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
-+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
-+	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
-+	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
-+
-+}
-+
-+void rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, u8 privacy)
-+{
-+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+	u8 *pframe_head, pktlen_index;
-+
-+	pktlen_index = pattrib->pktlen;
-+	pframe_head = pframe;
-+
-+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_PUBLIC);
-+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
-+	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
-+	pframe = rtw_tdls_set_capability(padapter, pframe, pattrib);
-+
-+	pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);
-+
-+	pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);
-+
-+	if (privacy)
-+		pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _TRUE, NULL);
-+
-+	pframe = rtw_tdls_set_ext_cap(pframe, pattrib);
-+
-+	if (privacy) {
-+		pframe = rtw_tdls_set_ftie(ptxmgmt, pframe, pattrib, NULL, NULL);
-+		pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib,  _TRUE, NULL);
-+	}
-+
-+#ifdef CONFIG_80211N_HT
-+	if (pregistrypriv->ht_enable == _TRUE)
-+		pframe = rtw_tdls_set_ht_cap(padapter, pframe_head - pktlen_index, pattrib);
-+#endif
-+
-+	pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);
-+	pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
-+
-+}
-+
-+
-+void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
-+{
-+
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+	u8 AC_queue = 0;
-+
-+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
-+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
-+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
-+	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
-+
-+	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
-+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
-+	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
-+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
-+
-+	/* PTI control */
-+	/* PU buffer status */
-+	if (ptdls_sta->uapsd_bk & BIT(1))
-+		AC_queue = BIT(0);
-+	if (ptdls_sta->uapsd_be & BIT(1))
-+		AC_queue = BIT(1);
-+	if (ptdls_sta->uapsd_vi & BIT(1))
-+		AC_queue = BIT(2);
-+	if (ptdls_sta->uapsd_vo & BIT(1))
-+		AC_queue = BIT(3);
-+	pframe = rtw_set_ie(pframe, _PTI_BUFFER_STATUS_, 1, &AC_queue, &(pattrib->pktlen));
-+
-+}
-+
-+void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
-+{
-+
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+
-+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
-+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
-+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
-+	pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
-+
-+	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
-+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
-+	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
-+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
-+}
-+
-+#ifdef CONFIG_TDLS_CH_SW
-+void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
-+{
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+	struct sta_priv	*pstapriv = &padapter->stapriv;
-+	u16 switch_time = TDLS_CH_SWITCH_TIME * 1000, switch_timeout = TDLS_CH_SWITCH_TIMEOUT * 1000;
-+
-+	ptdls_sta->ch_switch_time = switch_time;
-+	ptdls_sta->ch_switch_timeout = switch_timeout;
-+
-+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
-+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
-+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
-+	pframe = rtw_tdls_set_target_ch(padapter, pframe, pattrib);
-+	pframe = rtw_tdls_set_reg_class(pframe, pattrib, ptdls_sta);
-+
-+	if (ptdlsinfo->chsw_info.ch_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
-+		switch (ptdlsinfo->chsw_info.ch_offset) {
-+		case HAL_PRIME_CHNL_OFFSET_LOWER:
-+			pframe = rtw_tdls_set_second_channel_offset(pframe, pattrib, SCA);
-+			break;
-+		case HAL_PRIME_CHNL_OFFSET_UPPER:
-+			pframe = rtw_tdls_set_second_channel_offset(pframe, pattrib, SCB);
-+			break;
-+		}
-+	}
-+
-+	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
-+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
-+	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
-+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
-+
-+	pframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta);
-+
-+}
-+
-+void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
-+{
-+
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+	struct sta_priv	*pstapriv = &padapter->stapriv;
-+
-+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
-+	pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
-+	pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
-+	pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);
-+
-+	if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
-+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
-+	else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
-+		pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
-+
-+	pframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta);
-+}
-+#endif
-+
-+#ifdef CONFIG_WFD
-+void rtw_build_tunneled_probe_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe)
-+{
-+	u8 i;
-+	_adapter *iface = NULL;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
-+	struct wifidirect_info *pwdinfo;
-+
-+	u8 category = RTW_WLAN_CATEGORY_P2P;
-+	u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a};
-+	u8 probe_req = 4;
-+	u8 wfdielen = 0;
-+
-+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 3, WFA_OUI, &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(probe_req), &(pattrib->pktlen));
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if ((iface) && rtw_is_adapter_up(iface)) {
-+			pwdinfo = &iface->wdinfo;
-+			if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
-+				wfdielen = build_probe_req_wfd_ie(pwdinfo, pframe);
-+				pframe += wfdielen;
-+				pattrib->pktlen += wfdielen;
-+			}
-+		}
-+	}
-+}
-+
-+void rtw_build_tunneled_probe_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe)
-+{
-+	u8 i;
-+	_adapter *iface = NULL;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+	struct wifidirect_info *pwdinfo;
-+	u8 category = RTW_WLAN_CATEGORY_P2P;
-+	u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a};
-+	u8 probe_rsp = 5;
-+	u8 wfdielen = 0;
-+
-+	pframe = rtw_tdls_set_payload_type(pframe, pattrib);
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 3, WFA_OUI, &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(probe_rsp), &(pattrib->pktlen));
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if ((iface) && rtw_is_adapter_up(iface)) {
-+			pwdinfo = &iface->wdinfo;
-+			if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
-+				wfdielen = build_probe_resp_wfd_ie(pwdinfo, pframe, 1);
-+				pframe += wfdielen;
-+				pattrib->pktlen += wfdielen;
-+			}
-+		}
-+	}
-+}
-+#endif /* CONFIG_WFD */
-+
-+void _tdls_tpk_timer_hdl(void *FunctionContext)
-+{
-+	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
-+	struct tdls_txmgmt txmgmt;
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	ptdls_sta->TPK_count++;
-+	/* TPK_timer expired in a second */
-+	/* Retry timer should set at least 301 sec. */
-+	if (ptdls_sta->TPK_count >= (ptdls_sta->TDLS_PeerKey_Lifetime - 3)) {
-+		RTW_INFO("[TDLS] %s, Re-Setup TDLS link with "MAC_FMT" since TPK lifetime expires!\n",
-+			__FUNCTION__, MAC_ARG(ptdls_sta->cmn.mac_addr));
-+		ptdls_sta->TPK_count = 0;
-+		_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
-+		issue_tdls_setup_req(ptdls_sta->padapter, &txmgmt, _FALSE);
-+	}
-+
-+	_set_timer(&ptdls_sta->TPK_timer, ONE_SEC);
-+}
-+
-+#ifdef CONFIG_TDLS_CH_SW
-+void _tdls_ch_switch_timer_hdl(void *FunctionContext)
-+{
-+	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
-+	_adapter *padapter = ptdls_sta->padapter;
-+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
-+
-+	rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL);
-+	RTW_INFO("[TDLS] %s, can't get traffic from op_ch:%d\n", __func__, rtw_get_oper_ch(padapter));
-+}
-+
-+void _tdls_delay_timer_hdl(void *FunctionContext)
-+{
-+	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
-+	_adapter *padapter = ptdls_sta->padapter;
-+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
-+
-+	RTW_INFO("[TDLS] %s, op_ch:%d, tdls_state:0x%08x\n", __func__, rtw_get_oper_ch(padapter), ptdls_sta->tdls_sta_state);
-+	pchsw_info->delay_switch_back = _TRUE;
-+}
-+
-+void _tdls_stay_on_base_chnl_timer_hdl(void *FunctionContext)
-+{
-+	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
-+	_adapter *padapter = ptdls_sta->padapter;
-+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
-+
-+	if (ptdls_sta != NULL) {
-+		issue_tdls_ch_switch_req(padapter, ptdls_sta);
-+		pchsw_info->ch_sw_state |= TDLS_WAIT_CH_RSP_STATE;
-+	}
-+}
-+
-+void _tdls_ch_switch_monitor_timer_hdl(void *FunctionContext)
-+{
-+	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
-+	_adapter *padapter = ptdls_sta->padapter;
-+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
-+
-+	rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END);
-+	RTW_INFO("[TDLS] %s, does not receive ch sw req\n", __func__);
-+}
-+
-+#endif
-+
-+void _tdls_handshake_timer_hdl(void *FunctionContext)
-+{
-+	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
-+	_adapter *padapter = NULL;
-+	struct tdls_txmgmt txmgmt;
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
-+	txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;
-+
-+	if (ptdls_sta != NULL) {
-+		padapter = ptdls_sta->padapter;
-+
-+		RTW_INFO("[TDLS] Handshake time out\n");
-+		if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
-+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA);
-+		else
-+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY);
-+	}
-+}
-+
-+void _tdls_pti_timer_hdl(void *FunctionContext)
-+{
-+	struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
-+	_adapter *padapter = NULL;
-+	struct tdls_txmgmt txmgmt;
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	_rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
-+	txmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_;
-+
-+	if (ptdls_sta != NULL) {
-+		padapter = ptdls_sta->padapter;
-+
-+		if (ptdls_sta->tdls_sta_state & TDLS_WAIT_PTR_STATE) {
-+			RTW_INFO("[TDLS] Doesn't receive PTR from peer dev:"MAC_FMT"; "
-+				"Send TDLS Tear Down\n", MAC_ARG(ptdls_sta->cmn.mac_addr));
-+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA);
-+		}
-+	}
-+}
-+
-+void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta)
-+{
-+	psta->padapter = padapter;
-+	rtw_init_timer(&psta->TPK_timer, padapter, _tdls_tpk_timer_hdl, psta);
-+#ifdef CONFIG_TDLS_CH_SW
-+	rtw_init_timer(&psta->ch_sw_timer, padapter, _tdls_ch_switch_timer_hdl, psta);
-+	rtw_init_timer(&psta->delay_timer, padapter, _tdls_delay_timer_hdl, psta);
-+	rtw_init_timer(&psta->stay_on_base_chnl_timer, padapter, _tdls_stay_on_base_chnl_timer_hdl, psta);
-+	rtw_init_timer(&psta->ch_sw_monitor_timer, padapter, _tdls_ch_switch_monitor_timer_hdl, psta);
-+#endif
-+	rtw_init_timer(&psta->handshake_timer, padapter, _tdls_handshake_timer_hdl, psta);
-+	rtw_init_timer(&psta->pti_timer, padapter, _tdls_pti_timer_hdl, psta);
-+}
-+
-+void rtw_cancel_tdls_timer(struct sta_info *psta)
-+{
-+	_cancel_timer_ex(&psta->TPK_timer);
-+#ifdef CONFIG_TDLS_CH_SW
-+	_cancel_timer_ex(&psta->ch_sw_timer);
-+	_cancel_timer_ex(&psta->delay_timer);
-+	_cancel_timer_ex(&psta->stay_on_base_chnl_timer);
-+	_cancel_timer_ex(&psta->ch_sw_monitor_timer);
-+#endif
-+	_cancel_timer_ex(&psta->handshake_timer);
-+	_cancel_timer_ex(&psta->pti_timer);
-+}
-+
-+void rtw_tdls_teardown_pre_hdl(_adapter *padapter, struct sta_info *psta)
-+{
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	_irqL irqL;
-+
-+	rtw_cancel_tdls_timer(psta);
-+
-+	_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
-+	if (ptdlsinfo->sta_cnt != 0)
-+		ptdlsinfo->sta_cnt--;
-+	_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
-+
-+	if (ptdlsinfo->sta_cnt < MAX_ALLOWED_TDLS_STA_NUM) {
-+		ptdlsinfo->sta_maximum = _FALSE;
-+		_rtw_memset(&ptdlsinfo->ss_record, 0x00, sizeof(struct tdls_ss_record));
-+	}
-+
-+	if (ptdlsinfo->sta_cnt == 0)
-+		rtw_tdls_set_link_established(padapter, _FALSE);
-+	else
-+		RTW_INFO("Remain tdls sta:%02x\n", ptdlsinfo->sta_cnt);
-+}
-+
-+void rtw_tdls_teardown_post_hdl(_adapter *padapter, struct sta_info *psta, u8 enqueue_cmd)
-+{
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+
-+	/* Clear cam */
-+	rtw_clearstakey_cmd(padapter, psta, enqueue_cmd);
-+
-+	/* Update sta media status */
-+	if (enqueue_cmd)
-+		rtw_sta_media_status_rpt_cmd(padapter, psta, 0);
-+	else
-+		rtw_sta_media_status_rpt(padapter, psta, 0);
-+
-+	/* Set RCR if necessary */
-+	if (ptdlsinfo->sta_cnt == 0) {
-+		if (enqueue_cmd)
-+			rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR);
-+		else
-+			rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_NOLINK);
-+	}
-+
-+	/* Free tdls sta info */
-+	rtw_free_stainfo(padapter,  psta);
-+}
-+
-+int rtw_tdls_is_driver_setup(_adapter *padapter)
-+{
-+	return padapter->tdlsinfo.driver_setup;
-+}
-+
-+const char *rtw_tdls_action_txt(enum TDLS_ACTION_FIELD action)
-+{
-+	switch (action) {
-+	case TDLS_SETUP_REQUEST:
-+		return "TDLS_SETUP_REQUEST";
-+	case TDLS_SETUP_RESPONSE:
-+		return "TDLS_SETUP_RESPONSE";
-+	case TDLS_SETUP_CONFIRM:
-+		return "TDLS_SETUP_CONFIRM";
-+	case TDLS_TEARDOWN:
-+		return "TDLS_TEARDOWN";
-+	case TDLS_PEER_TRAFFIC_INDICATION:
-+		return "TDLS_PEER_TRAFFIC_INDICATION";
-+	case TDLS_CHANNEL_SWITCH_REQUEST:
-+		return "TDLS_CHANNEL_SWITCH_REQUEST";
-+	case TDLS_CHANNEL_SWITCH_RESPONSE:
-+		return "TDLS_CHANNEL_SWITCH_RESPONSE";
-+	case TDLS_PEER_PSM_REQUEST:
-+		return "TDLS_PEER_PSM_REQUEST";
-+	case TDLS_PEER_PSM_RESPONSE:
-+		return "TDLS_PEER_PSM_RESPONSE";
-+	case TDLS_PEER_TRAFFIC_RESPONSE:
-+		return "TDLS_PEER_TRAFFIC_RESPONSE";
-+	case TDLS_DISCOVERY_REQUEST:
-+		return "TDLS_DISCOVERY_REQUEST";
-+	case TDLS_DISCOVERY_RESPONSE:
-+		return "TDLS_DISCOVERY_RESPONSE";
-+	default:
-+		return "UNKNOWN";
-+	}
-+}
-+
-+#endif /* CONFIG_TDLS */
-diff --git a/drivers/staging/rtl8723cs/core/rtw_vht.c b/drivers/staging/rtl8723cs/core/rtw_vht.c
-new file mode 100644
-index 000000000000..55b170962458
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_vht.c
-@@ -0,0 +1,1141 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_VHT_C
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#ifdef CONFIG_80211AC_VHT
-+const u16 _vht_max_mpdu_len[] = {
-+	3895,
-+	7991,
-+	11454,
-+	0,
-+};
-+
-+const u8 _vht_sup_ch_width_set_to_bw_cap[] = {
-+	BW_CAP_80M,
-+	BW_CAP_80M | BW_CAP_160M,
-+	BW_CAP_80M | BW_CAP_160M | BW_CAP_80_80M,
-+	0,
-+};
-+
-+#ifdef CONFIG_RTW_DEBUG
-+const char *const _vht_sup_ch_width_set_str[] = {
-+	"80MHz",
-+	"160MHz",
-+	"160MHz & 80+80MHz",
-+	"BW-RSVD",
-+};
-+
-+void dump_vht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len)
-+{
-+	if (buf_len != VHT_CAP_IE_LEN) {
-+		RTW_PRINT_SEL(sel, "Invalid VHT capability IE len:%d != %d\n", buf_len, VHT_CAP_IE_LEN);
-+		return;
-+	}
-+
-+	RTW_PRINT_SEL(sel, "cap_info:%02x %02x %02x %02x: MAX_MPDU_LEN:%u %s%s%s%s%s RX-STBC:%u MAX_AMPDU_LEN:%u\n"
-+		, *(buf), *(buf + 1), *(buf + 2), *(buf + 3)
-+		, vht_max_mpdu_len(GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(buf))
-+		, vht_sup_ch_width_set_str(GET_VHT_CAPABILITY_ELE_CHL_WIDTH(buf))
-+		, GET_VHT_CAPABILITY_ELE_RX_LDPC(buf) ? " RX-LDPC" : ""
-+		, GET_VHT_CAPABILITY_ELE_SHORT_GI80M(buf) ? " SGI-80" : ""
-+		, GET_VHT_CAPABILITY_ELE_SHORT_GI160M(buf) ? " SGI-160" : ""
-+		, GET_VHT_CAPABILITY_ELE_TX_STBC(buf) ? " TX-STBC" : ""
-+		, GET_VHT_CAPABILITY_ELE_RX_STBC(buf)
-+		, VHT_MAX_AMPDU_LEN(GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(buf))
-+	);
-+}
-+
-+void dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len)
-+{
-+	const u8 *vht_cap_ie;
-+	sint vht_cap_ielen;
-+
-+	vht_cap_ie = rtw_get_ie(ie, WLAN_EID_VHT_CAPABILITY, &vht_cap_ielen, ie_len);
-+	if (!ie || vht_cap_ie != ie)
-+		return;
-+
-+	dump_vht_cap_ie_content(sel, vht_cap_ie + 2, vht_cap_ielen);
-+}
-+
-+const char *const _vht_op_ch_width_str[] = {
-+	"20 or 40MHz",
-+	"80MHz",
-+	"160MHz",
-+	"80+80MHz",
-+	"BW-RSVD",
-+};
-+
-+void dump_vht_op_ie_content(void *sel, const u8 *buf, u32 buf_len)
-+{
-+	if (buf_len != VHT_OP_IE_LEN) {
-+		RTW_PRINT_SEL(sel, "Invalid VHT operation IE len:%d != %d\n", buf_len, VHT_OP_IE_LEN);
-+		return;
-+	}
-+
-+	RTW_PRINT_SEL(sel, "%s, ch0:%u, ch1:%u\n"
-+		, vht_op_ch_width_str(GET_VHT_OPERATION_ELE_CHL_WIDTH(buf))
-+		, GET_VHT_OPERATION_ELE_CENTER_FREQ1(buf)
-+		, GET_VHT_OPERATION_ELE_CENTER_FREQ2(buf)
-+	);
-+}
-+
-+void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len)
-+{
-+	const u8 *vht_op_ie;
-+	sint vht_op_ielen;
-+
-+	vht_op_ie = rtw_get_ie(ie, WLAN_EID_VHT_OPERATION, &vht_op_ielen, ie_len);
-+	if (!ie || vht_op_ie != ie)
-+		return;
-+
-+	dump_vht_op_ie_content(sel, vht_op_ie + 2, vht_op_ielen);
-+}
-+#endif
-+
-+/*				20/40/80,	ShortGI,	MCS Rate  */
-+const u16 VHT_MCS_DATA_RATE[3][2][40] = {	/* unit: 0.5M */
-+	{	{
-+			13, 26, 39, 52, 78, 104, 117, 130, 156, 156,
-+			26, 52, 78, 104, 156, 208, 234, 260, 312, 312,
-+			39, 78, 117, 156, 234, 312, 351, 390, 468, 520,
-+			52, 104, 156, 208, 312, 416, 468, 520, 624, 624,
-+		},			/* Long GI, 20MHz */
-+		{
-+			14, 29, 43, 58, 87, 116, 130, 144, 173, 173,
-+			29, 58, 87, 116, 173, 231, 260, 289, 347, 347,
-+			43, 87, 130, 173, 260, 347, 390, 433, 520, 578,
-+			58, 116, 173, 231, 347, 462, 520, 578, 693, 693,
-+		}
-+	},		/* Short GI, 20MHz */
-+	{	{
-+			27, 54, 81, 108, 162, 216, 243, 270, 324, 360,
-+			54, 108, 162, 216, 324, 432, 486, 540, 648, 720,
-+			81, 162, 243, 324, 486, 648, 729, 810, 972, 1080,
-+			108, 216, 324, 432, 648, 864, 972, 1080, 1296, 1440,
-+		}, 		/* Long GI, 40MHz */
-+		{
-+			30, 60, 90, 120, 180, 240, 270, 300, 360, 400,
-+			60, 120, 180, 240, 360, 480, 540, 600, 720, 800,
-+			90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200,
-+			120, 240, 360, 480, 720, 960, 1080, 1200, 1440, 1600,
-+		}
-+	},		/* Short GI, 40MHz */
-+	{	{
-+			59, 117, 176, 234, 351, 468, 527, 585, 702, 780,
-+			117, 234, 351, 468, 702, 936, 1053, 1170, 1404, 1560,
-+			176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2340,
-+			234, 468, 702, 936, 1404, 1872, 2106, 2340, 2808, 3120,
-+		},	/* Long GI, 80MHz */
-+		{
-+			65, 130, 195, 260, 390, 520, 585, 650, 780, 867,
-+			130, 260, 390, 520, 780, 1040, 1170, 1300, 1560, 1734,
-+			195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2600,
-+			260, 520, 780, 1040, 1560, 2080, 2340, 2600, 3120, 3467,
-+		}
-+	}	/* Short GI, 80MHz */
-+};
-+
-+u8	rtw_get_vht_highest_rate(u8 *pvht_mcs_map)
-+{
-+	u8	i, j;
-+	u8	bit_map;
-+	u8	vht_mcs_rate = 0;
-+
-+	for (i = 0; i < 2; i++) {
-+		if (pvht_mcs_map[i] != 0xff) {
-+			for (j = 0; j < 8; j += 2) {
-+				bit_map = (pvht_mcs_map[i] >> j) & 3;
-+
-+				if (bit_map != 3)
-+					vht_mcs_rate = MGN_VHT1SS_MCS7 + 10 * j / 2 + i * 40 + bit_map; /* VHT rate indications begin from 0x90 */
-+			}
-+		}
-+	}
-+
-+	/* RTW_INFO("HighestVHTMCSRate is %x\n", vht_mcs_rate); */
-+	return vht_mcs_rate;
-+}
-+
-+u8	rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map)
-+{
-+	u8	i, j;
-+	u8	bit_map;
-+	u8	nss = 0;
-+
-+	for (i = 0; i < 2; i++) {
-+		if (pvht_mcs_map[i] != 0xff) {
-+			for (j = 0; j < 8; j += 2) {
-+				bit_map = (pvht_mcs_map[i] >> j) & 3;
-+
-+				if (bit_map != 3)
-+					nss++;
-+			}
-+		}
-+	}
-+
-+	/* RTW_INFO("%s : %dSS\n", __FUNCTION__, nss); */
-+	return nss;
-+}
-+
-+void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map)
-+{
-+	u8	i, j;
-+	u8	cur_rate, target_rate;
-+
-+	for (i = 0; i < 2; i++) {
-+		target_mcs_map[i] = 0;
-+		for (j = 0; j < 8; j += 2) {
-+			cur_rate = (cur_mcs_map[i] >> j) & 3;
-+			if (cur_rate == 3) /* 0x3 indicates not supported that num of SS */
-+				target_rate = 3;
-+			else if (nss <= ((j / 2) + i * 4))
-+				target_rate = 3;
-+			else
-+				target_rate = cur_rate;
-+
-+			target_mcs_map[i] |= (target_rate << j);
-+		}
-+	}
-+
-+	/* RTW_INFO("%s : %dSS\n", __FUNCTION__, nss); */
-+}
-+
-+u16	rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate)
-+{
-+	if (vht_mcs_rate > MGN_VHT4SS_MCS9)
-+		vht_mcs_rate = MGN_VHT4SS_MCS9;
-+	/* RTW_INFO("bw=%d, short_GI=%d, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)=%d\n", bw, short_GI, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)); */
-+	return VHT_MCS_DATA_RATE[bw][short_GI][((vht_mcs_rate - MGN_VHT1SS_MCS0) & 0x3f)];
-+}
-+
-+void	rtw_vht_use_default_setting(_adapter *padapter)
-+{
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
-+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+	BOOLEAN		bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE;
-+#ifdef CONFIG_BEAMFORMING
-+	BOOLEAN		bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE;
-+	u8	mu_bfer, mu_bfee;
-+#endif /* CONFIG_BEAMFORMING */
-+	u8 tx_nss, rx_nss;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	pvhtpriv->sgi_80m = TEST_FLAG(pregistrypriv->short_gi, BIT2) ? _TRUE : _FALSE;
-+
-+	/* LDPC support */
-+	rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport);
-+	CLEAR_FLAGS(pvhtpriv->ldpc_cap);
-+	if (bHwLDPCSupport) {
-+		if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT0))
-+			SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX);
-+	}
-+	rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport);
-+	if (bHwLDPCSupport) {
-+		if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT1))
-+			SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX);
-+	}
-+	if (pvhtpriv->ldpc_cap)
-+		RTW_INFO("[VHT] Support LDPC = 0x%02X\n", pvhtpriv->ldpc_cap);
-+
-+	/* STBC */
-+	rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport);
-+	CLEAR_FLAGS(pvhtpriv->stbc_cap);
-+	if (bHwSTBCSupport) {
-+		if (TEST_FLAG(pregistrypriv->stbc_cap, BIT1))
-+			SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX);
-+	}
-+	rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport);
-+	if (bHwSTBCSupport) {
-+		if (TEST_FLAG(pregistrypriv->stbc_cap, BIT0))
-+			SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX);
-+	}
-+	if (pvhtpriv->stbc_cap)
-+		RTW_INFO("[VHT] Support STBC = 0x%02X\n", pvhtpriv->stbc_cap);
-+
-+	/* Beamforming setting */
-+	CLEAR_FLAGS(pvhtpriv->beamform_cap);
-+#ifdef CONFIG_BEAMFORMING
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+#ifdef CONFIG_CONCURRENT_MODE
-+	/* only enable beamforming in STA client mode */
-+	if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter))
-+#else
-+	if ((MLME_IS_AP(padapter) && !MLME_IS_GO(padapter)) ||
-+	    (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter)))
-+#endif
-+#endif
-+	{
-+		rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER,
-+			(u8 *)&bHwSupportBeamformer);
-+		rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE,
-+			(u8 *)&bHwSupportBeamformee);
-+		mu_bfer = _FALSE;
-+		mu_bfee = _FALSE;
-+		rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMER, &mu_bfer);
-+		rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMEE, &mu_bfee);
-+		if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) {
-+#ifdef CONFIG_CONCURRENT_MODE
-+			if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
-+				SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
-+				RTW_INFO("[VHT] CONCURRENT AP Support Beamformer\n");
-+				if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))
-+				    && (_TRUE == mu_bfer)) {
-+					SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
-+					RTW_INFO("[VHT] Support MU-MIMO AP\n");
-+				}
-+			} else
-+				RTW_INFO("[VHT] CONCURRENT not AP ;not allow  Support Beamformer\n");
-+#else
-+			SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
-+			RTW_INFO("[VHT] Support Beamformer\n");
-+			if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))
-+			    && (_TRUE == mu_bfer)
-+			    && ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
-+				SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
-+				RTW_INFO("[VHT] Support MU-MIMO AP\n");
-+			}
-+#endif
-+		}
-+		if (TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) {
-+			SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
-+			RTW_INFO("[VHT] Support Beamformee\n");
-+			if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(3))
-+			    && (_TRUE == mu_bfee)
-+			    && ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)) {
-+				SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
-+				RTW_INFO("[VHT] Support MU-MIMO STA\n");
-+			}
-+		}
-+	}
-+#endif /* CONFIG_BEAMFORMING */
-+
-+	pvhtpriv->ampdu_len = pregistrypriv->ampdu_factor;
-+
-+	tx_nss = GET_HAL_TX_NSS(padapter);
-+	rx_nss = GET_HAL_RX_NSS(padapter);
-+
-+	/* for now, vhtpriv.vht_mcs_map comes from RX NSS */
-+	rtw_vht_nss_to_mcsmap(rx_nss, pvhtpriv->vht_mcs_map, pregistrypriv->vht_rx_mcs_map);
-+	pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
-+}
-+
-+u64	rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss)
-+{
-+	u8 i, j, tmp;
-+	u64 bitmap = 0;
-+	u8 bits_nss = nss * 2;
-+
-+	for (i = j = 0; i < bits_nss; i += 2, j += 10) {
-+		/* every two bits means single sptial stream */
-+		tmp = (mcs_map[i / 8] >> i) & 3;
-+
-+		switch (tmp) {
-+		case 2:
-+			bitmap = bitmap | ((u64)0x03ff << j);
-+			break;
-+		case 1:
-+			bitmap = bitmap | ((u64)0x01ff << j);
-+			break;
-+		case 0:
-+			bitmap = bitmap | ((u64)0x00ff << j);
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	RTW_INFO("vht_mcs_map=%02x %02x, nss=%u => bitmap=%016llx\n"
-+		, mcs_map[0], mcs_map[1], nss, bitmap);
-+
-+	return bitmap;
-+}
-+
-+#ifdef CONFIG_BEAMFORMING
-+void update_sta_vht_info_apmode_bf_cap(_adapter *padapter, struct sta_info *psta)
-+{
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct vht_priv	*pvhtpriv_ap = &pmlmepriv->vhtpriv;
-+	struct vht_priv	*pvhtpriv_sta = &psta->vhtpriv;
-+	u16	cur_beamform_cap = 0;
-+
-+	/* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
-+	if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
-+	    GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap)) {
-+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
-+		/*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/
-+		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pvhtpriv_sta->vht_cap) << 8);
-+	}
-+
-+	/* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
-+	if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
-+	    GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap)) {
-+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
-+		/*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/
-+		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pvhtpriv_sta->vht_cap) << 12);
-+	}
-+
-+	if (cur_beamform_cap)
-+		RTW_INFO("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->cmn.aid, cur_beamform_cap);
-+
-+	pvhtpriv_sta->beamform_cap = cur_beamform_cap;
-+	psta->cmn.bf_info.vht_beamform_cap = cur_beamform_cap;
-+}
-+#endif
-+
-+void	update_sta_vht_info_apmode(_adapter *padapter, void *sta)
-+{
-+	struct sta_info	*psta = (struct sta_info *)sta;
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct vht_priv	*pvhtpriv_ap = &pmlmepriv->vhtpriv;
-+	struct vht_priv	*pvhtpriv_sta = &psta->vhtpriv;
-+	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0;
-+	s8 bw_mode = -1;
-+	u8	*pcap_mcs;
-+
-+	if (pvhtpriv_sta->vht_option == _FALSE)
-+		return;
-+
-+	if (pvhtpriv_sta->op_present) {
-+		switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(pvhtpriv_sta->vht_op)) {
-+		case 1: /* 80MHz */
-+		case 2: /* 160MHz */
-+		case 3: /* 80+80 */
-+			bw_mode = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */
-+			break;
-+		}
-+	}
-+
-+	if (pvhtpriv_sta->notify_present)
-+		bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify);
-+	else if (MLME_IS_AP(padapter)) {
-+		/* for VHT client without Operating Mode Notify IE; minimal 80MHz */
-+		if (bw_mode < CHANNEL_WIDTH_80)
-+			bw_mode = CHANNEL_WIDTH_80;
-+	}
-+
-+	if (bw_mode != -1)
-+		psta->cmn.bw_mode = bw_mode; /* update bw_mode only if get value from VHT IEs */
-+
-+	psta->cmn.ra_info.is_vht_enable = _TRUE;
-+
-+	/* B4 Rx LDPC */
-+	if (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
-+	    GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap)) {
-+		SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
-+		RTW_INFO("Current STA(%d) VHT LDPC = %02X\n", psta->cmn.aid, cur_ldpc_cap);
-+	}
-+	pvhtpriv_sta->ldpc_cap = cur_ldpc_cap;
-+
-+	if (psta->cmn.bw_mode > pmlmeext->cur_bwmode)
-+		psta->cmn.bw_mode = pmlmeext->cur_bwmode;
-+
-+	if (psta->cmn.bw_mode == CHANNEL_WIDTH_80) {
-+		/* B5 Short GI for 80 MHz */
-+		pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
-+		/* RTW_INFO("Current STA ShortGI80MHz = %d\n", pvhtpriv_sta->sgi_80m); */
-+	} else if (psta->cmn.bw_mode >= CHANNEL_WIDTH_160) {
-+		/* B5 Short GI for 80 MHz */
-+		pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
-+		/* RTW_INFO("Current STA ShortGI160MHz = %d\n", pvhtpriv_sta->sgi_80m); */
-+	}
-+
-+	/* B8 B9 B10 Rx STBC */
-+	if (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) &&
-+	    GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap)) {
-+		SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
-+		RTW_INFO("Current STA(%d) VHT STBC = %02X\n", psta->cmn.aid, cur_stbc_cap);
-+	}
-+	pvhtpriv_sta->stbc_cap = cur_stbc_cap;
-+
-+#ifdef CONFIG_BEAMFORMING
-+	update_sta_vht_info_apmode_bf_cap(padapter, psta);
-+#endif
-+
-+	/* B23 B24 B25 Maximum A-MPDU Length Exponent */
-+	pvhtpriv_sta->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pvhtpriv_sta->vht_cap);
-+
-+	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pvhtpriv_sta->vht_cap);
-+	_rtw_memcpy(pvhtpriv_sta->vht_mcs_map, pcap_mcs, 2);
-+	pvhtpriv_sta->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv_sta->vht_mcs_map);
-+}
-+
-+void	update_hw_vht_param(_adapter *padapter)
-+{
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8	ht_AMPDU_len;
-+
-+	ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
-+
-+	if (pvhtpriv->ampdu_len > ht_AMPDU_len)
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len));
-+}
-+
-+#ifdef ROKU_PRIVATE
-+u8 VHT_get_ss_from_map(u8 *vht_mcs_map)
-+{
-+	u8 i, j;
-+	u8 ss = 0;
-+
-+	for (i = 0; i < 2; i++) {
-+		if (vht_mcs_map[i] != 0xff) {
-+			for (j = 0; j < 8; j += 2) {
-+				if (((vht_mcs_map[i] >> j) & 0x03) == 0x03)
-+					break;
-+				ss++;
-+			}
-+		}
-+
-+	}
-+
-+return ss;
-+}
-+
-+void VHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct vht_priv_infra_ap	*pvhtpriv = &pmlmepriv->vhtpriv_infra_ap;
-+	u8      cur_stbc_cap_infra_ap = 0;
-+	u16	cur_beamform_cap_infra_ap = 0;
-+	u8	*pcap_mcs;
-+	u8	*pcap_mcs_tx;
-+	u8	Rx_ss = 0, Tx_ss = 0;
-+
-+	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info		*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if (pIE == NULL)
-+		return;
-+
-+	pmlmeinfo->ht_vht_received |= BIT(1);
-+
-+	pvhtpriv->ldpc_cap_infra_ap = GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data);
-+
-+	if (GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data))
-+		SET_FLAG(cur_stbc_cap_infra_ap, STBC_VHT_ENABLE_RX);
-+	if (GET_VHT_CAPABILITY_ELE_TX_STBC(pIE->data))
-+		SET_FLAG(cur_stbc_cap_infra_ap, STBC_VHT_ENABLE_TX);
-+	pvhtpriv->stbc_cap_infra_ap = cur_stbc_cap_infra_ap;
-+
-+	/*store ap info for channel bandwidth*/
-+	pvhtpriv->channel_width_infra_ap = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(pIE->data);
-+
-+	/*check B11: SU Beamformer Capable and B12: SU Beamformee B19: MU Beamformer B20:MU Beamformee*/
-+	if (GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data))
-+		SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
-+	if (GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data))
-+		SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
-+	if (GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data))
-+		SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
-+	if (GET_VHT_CAPABILITY_ELE_MU_BFEE(pIE->data))
-+		SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
-+	pvhtpriv->beamform_cap_infra_ap = cur_beamform_cap_infra_ap;
-+
-+	/*store information about vht_mcs_set*/
-+	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data);
-+	pcap_mcs_tx = GET_VHT_CAPABILITY_ELE_TX_MCS(pIE->data);
-+	_rtw_memcpy(pvhtpriv->vht_mcs_map_infra_ap, pcap_mcs, 2);
-+	_rtw_memcpy(pvhtpriv->vht_mcs_map_tx_infra_ap, pcap_mcs_tx, 2);
-+
-+	Rx_ss = VHT_get_ss_from_map(pvhtpriv->vht_mcs_map_infra_ap);
-+	Tx_ss = VHT_get_ss_from_map(pvhtpriv->vht_mcs_map_tx_infra_ap);
-+	if (Rx_ss >= Tx_ss) {
-+		pvhtpriv->number_of_streams_infra_ap = Rx_ss;
-+	} else{
-+		pvhtpriv->number_of_streams_infra_ap = Tx_ss;
-+	}
-+
-+}
-+#endif /* ROKU_PRIVATE */
-+
-+void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0, rx_nss = 0;
-+	u16	cur_beamform_cap = 0;
-+	u8	*pcap_mcs;
-+
-+	if (pIE == NULL)
-+		return;
-+
-+	if (pvhtpriv->vht_option == _FALSE)
-+		return;
-+
-+	pmlmeinfo->VHT_enable = 1;
-+
-+	/* B4 Rx LDPC */
-+	if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
-+	    GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data)) {
-+		SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
-+		RTW_INFO("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap);
-+	}
-+	pvhtpriv->ldpc_cap = cur_ldpc_cap;
-+
-+	/* B5 Short GI for 80 MHz */
-+	pvhtpriv->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pIE->data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE;
-+	/* RTW_INFO("Current ShortGI80MHz = %d\n", pvhtpriv->sgi_80m); */
-+
-+	/* B8 B9 B10 Rx STBC */
-+	if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) &&
-+	    GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data)) {
-+		SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
-+		RTW_INFO("Current VHT STBC Setting = %02X\n", cur_stbc_cap);
-+	}
-+	pvhtpriv->stbc_cap = cur_stbc_cap;
-+#ifdef CONFIG_BEAMFORMING
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+	/*
-+	 * B11 SU Beamformer Capable,
-+	 * the target supports Beamformer and we are Beamformee
-+	 */
-+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)
-+	    && GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) {
-+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
-+
-+		/* Shift to BEAMFORMING_VHT_BEAMFORMEE_STS_CAP */
-+		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data) << 8);
-+
-+		/*
-+		 * B19 MU Beamformer Capable,
-+		 * the target supports Beamformer and we are Beamformee
-+		 */
-+		if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)
-+		    && GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data))
-+			SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
-+	}
-+
-+	/*
-+	 * B12 SU Beamformee Capable,
-+	 * the target supports Beamformee and we are Beamformer
-+	 */
-+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)
-+	    && GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) {
-+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
-+
-+		/* Shit to BEAMFORMING_VHT_BEAMFORMER_SOUND_DIM */
-+		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data) << 12);
-+
-+		/*
-+		 * B20 MU Beamformee Capable,
-+		 * the target supports Beamformee and we are Beamformer
-+		 */
-+		if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)
-+		    && GET_VHT_CAPABILITY_ELE_MU_BFEE(pIE->data))
-+			SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
-+	}
-+
-+	pvhtpriv->beamform_cap = cur_beamform_cap;
-+	RTW_INFO("Current VHT Beamforming Setting=0x%04X\n", cur_beamform_cap);
-+#else /* !RTW_BEAMFORMING_VERSION_2 */
-+	/* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
-+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
-+	    GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) {
-+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
-+		/*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/
-+		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data) << 8);
-+	}
-+
-+	/* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
-+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
-+	    GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) {
-+		SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
-+		/*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/
-+		SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data) << 12);
-+
-+	}
-+	pvhtpriv->beamform_cap = cur_beamform_cap;
-+	if (cur_beamform_cap)
-+		RTW_INFO("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap);
-+#endif /* !RTW_BEAMFORMING_VERSION_2 */
-+#endif /* CONFIG_BEAMFORMING */
-+	/* B23 B24 B25 Maximum A-MPDU Length Exponent */
-+	pvhtpriv->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pIE->data);
-+
-+	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data);
-+	rx_nss = GET_HAL_RX_NSS(padapter);
-+	rtw_vht_nss_to_mcsmap(rx_nss, pvhtpriv->vht_mcs_map, pcap_mcs);
-+	pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
-+}
-+
-+void VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
-+
-+	if (pIE == NULL)
-+		return;
-+
-+	if (pvhtpriv->vht_option == _FALSE)
-+		return;
-+}
-+
-+void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, void *sta)
-+{
-+	struct sta_info		*psta = (struct sta_info *)sta;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
-+	struct registry_priv *regsty = adapter_to_regsty(padapter);
-+	u8	target_bw;
-+	u8	target_rxss, current_rxss;
-+	u8	update_ra = _FALSE;
-+	u8 tx_nss = 0;
-+
-+	if (pvhtpriv->vht_option == _FALSE)
-+		return;
-+
-+	target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(pframe);
-+	tx_nss = GET_HAL_TX_NSS(padapter);
-+	target_rxss = rtw_min(tx_nss, (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe) + 1));
-+
-+	if (target_bw != psta->cmn.bw_mode) {
-+		if (hal_is_bw_support(padapter, target_bw)
-+		    && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw)
-+		   ) {
-+			update_ra = _TRUE;
-+			psta->cmn.bw_mode = target_bw;
-+		}
-+	}
-+
-+	current_rxss = rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map);
-+	if (target_rxss != current_rxss) {
-+		u8	vht_mcs_map[2] = {};
-+
-+		update_ra = _TRUE;
-+
-+		rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map);
-+		_rtw_memcpy(psta->vhtpriv.vht_mcs_map, vht_mcs_map, 2);
-+
-+		rtw_hal_update_sta_ra_info(padapter, psta);
-+	}
-+
-+	if (update_ra)
-+		rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta);
-+}
-+
-+u32	rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel)
-+{
-+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
-+	/* struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv; */
-+	u8	ChnlWidth, center_freq, bw_mode;
-+	u32	len = 0;
-+	u8	operation[5];
-+
-+	_rtw_memset(operation, 0, 5);
-+
-+	bw_mode = REGSTY_BW_5G(pregistrypriv); /* TODO: control op bw with other info */
-+
-+	if (hal_chk_bw_cap(padapter, BW_CAP_80M | BW_CAP_160M)
-+	    && REGSTY_BW_5G(pregistrypriv) >= CHANNEL_WIDTH_80
-+	   ) {
-+		center_freq = rtw_get_center_ch(channel, bw_mode, HAL_PRIME_CHNL_OFFSET_LOWER);
-+		ChnlWidth = 1;
-+	} else {
-+		center_freq = 0;
-+		ChnlWidth = 0;
-+	}
-+
-+
-+	SET_VHT_OPERATION_ELE_CHL_WIDTH(operation, ChnlWidth);
-+	/* center frequency */
-+	SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(operation, center_freq);/* Todo: need to set correct center channel */
-+	SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(operation, 0);
-+
-+	_rtw_memcpy(operation + 3, pvhtpriv->vht_mcs_map, 2);
-+
-+	rtw_set_ie(pbuf, EID_VHTOperation, 5, operation, &len);
-+
-+	return len;
-+}
-+
-+u32	rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw)
-+{
-+	/* struct registry_priv *pregistrypriv = &padapter->registrypriv; */
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
-+	u32	len = 0;
-+	u8	opmode = 0;
-+	u8	chnl_width, rx_nss;
-+
-+	chnl_width = bw;
-+	rx_nss = rtw_vht_mcsmap_to_nss(pvhtpriv->vht_mcs_map);
-+
-+	SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&opmode, chnl_width);
-+	SET_VHT_OPERATING_MODE_FIELD_RX_NSS(&opmode, (rx_nss - 1));
-+	SET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(&opmode, 0); /* Todo */
-+
-+	pvhtpriv->vht_op_mode_notify = opmode;
-+
-+	pbuf = rtw_set_ie(pbuf, EID_OpModeNotification, 1, &opmode, &len);
-+
-+	return len;
-+}
-+
-+u32	rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
-+{
-+	u8	bw, rf_num, rx_stbc_nss = 0;
-+	u16	HighestRate;
-+	u8	*pcap, *pcap_mcs;
-+	u32	len = 0;
-+	u32 rx_packet_offset, max_recvbuf_sz;
-+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	pcap = pvhtpriv->vht_cap;
-+	_rtw_memset(pcap, 0, 32);
-+
-+	/* B0 B1 Maximum MPDU Length */
-+	rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset);
-+	rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz);
-+
-+	RTW_DBG("%s, line%d, Available RX buf size = %d bytes\n", __FUNCTION__, __LINE__, max_recvbuf_sz - rx_packet_offset);
-+
-+	if ((max_recvbuf_sz - rx_packet_offset) >= 11454) {
-+		SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 2);
-+		RTW_INFO("%s, line%d, Set MAX MPDU len = 11454 bytes\n", __FUNCTION__, __LINE__);
-+	} else if ((max_recvbuf_sz - rx_packet_offset) >= 7991) {
-+		SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 1);
-+		RTW_INFO("%s, line%d, Set MAX MPDU len = 7991 bytes\n", __FUNCTION__, __LINE__);
-+	} else if ((max_recvbuf_sz - rx_packet_offset) >= 3895) {
-+		SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 0);
-+		RTW_INFO("%s, line%d, Set MAX MPDU len = 3895 bytes\n", __FUNCTION__, __LINE__);
-+	} else
-+		RTW_ERR("%s, line%d, Error!! Available RX buf size < 3895 bytes\n", __FUNCTION__, __LINE__);
-+
-+	/* B2 B3 Supported Channel Width Set */
-+	if (hal_chk_bw_cap(padapter, BW_CAP_160M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_160)) {
-+		if (hal_chk_bw_cap(padapter, BW_CAP_80_80M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_80_80))
-+			SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 2);
-+		else
-+			SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 1);
-+	} else
-+		SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0);
-+
-+	/* B4 Rx LDPC */
-+	if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) {
-+		SET_VHT_CAPABILITY_ELE_RX_LDPC(pcap, 1);
-+		RTW_INFO("[VHT] Declare supporting RX LDPC\n");
-+	}
-+
-+	/* B5 ShortGI for 80MHz */
-+	SET_VHT_CAPABILITY_ELE_SHORT_GI80M(pcap, pvhtpriv->sgi_80m ? 1 : 0); /* We can receive Short GI of 80M */
-+	if (pvhtpriv->sgi_80m)
-+		RTW_INFO("[VHT] Declare supporting SGI 80MHz\n");
-+
-+	/* B6 ShortGI for 160MHz */
-+	/* SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pcap, pvhtpriv->sgi_80m? 1 : 0); */
-+
-+	/* B7 Tx STBC */
-+	if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) {
-+		SET_VHT_CAPABILITY_ELE_TX_STBC(pcap, 1);
-+		RTW_INFO("[VHT] Declare supporting TX STBC\n");
-+	}
-+
-+	/* B8 B9 B10 Rx STBC */
-+	if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) {
-+		rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss));
-+
-+		SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, rx_stbc_nss);
-+		RTW_INFO("[VHT] Declare supporting RX STBC = %d\n", rx_stbc_nss);
-+	}
-+	#ifdef CONFIG_BEAMFORMING
-+	/* B11 SU Beamformer Capable */
-+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
-+		SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1);
-+		RTW_INFO("[VHT] Declare supporting SU Bfer\n");
-+		/* B16 17 18 Number of Sounding Dimensions */
-+		rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);
-+		SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, rf_num);
-+		/* B19 MU Beamformer Capable */
-+		if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {
-+			SET_VHT_CAPABILITY_ELE_MU_BFER(pcap, 1);
-+			RTW_INFO("[VHT] Declare supporting MU Bfer\n");
-+		}
-+	}
-+
-+	/* B12 SU Beamformee Capable */
-+	if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
-+		SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1);
-+		RTW_INFO("[VHT] Declare supporting SU Bfee\n");
-+
-+		rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
-+
-+		/* IOT action suggested by Yu Chen 2017/3/3 */
-+#ifdef CONFIG_80211AC_VHT
-+		if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) &&
-+			!pvhtpriv->ap_bf_cap.is_mu_bfer &&
-+			pvhtpriv->ap_bf_cap.su_sound_dim == 2)
-+			rf_num = (rf_num >= 2 ? 2 : rf_num);
-+#endif
-+		/* B13 14 15 Compressed Steering Number of Beamformer Antennas Supported */
-+		SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, rf_num);
-+		/* B20 SU Beamformee Capable */
-+		if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) {
-+			SET_VHT_CAPABILITY_ELE_MU_BFEE(pcap, 1);
-+			RTW_INFO("[VHT] Declare supporting MU Bfee\n");
-+		}
-+	}
-+	#endif/*CONFIG_BEAMFORMING*/
-+
-+	/* B21 VHT TXOP PS */
-+	SET_VHT_CAPABILITY_ELE_TXOP_PS(pcap, 0);
-+	/* B22 +HTC-VHT Capable */
-+	SET_VHT_CAPABILITY_ELE_HTC_VHT(pcap, 1);
-+	/* B23 24 25 Maximum A-MPDU Length Exponent */
-+	if (pregistrypriv->ampdu_factor != 0xFE)
-+		SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, pregistrypriv->ampdu_factor);
-+	else
-+		SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, 7);
-+	/* B26 27 VHT Link Adaptation Capable */
-+	SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(pcap, 0);
-+
-+	pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pcap);
-+	_rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);
-+
-+	pcap_mcs = GET_VHT_CAPABILITY_ELE_TX_MCS(pcap);
-+	_rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2);
-+
-+	/* find the largest bw supported by both registry and hal */
-+	bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
-+
-+	HighestRate = VHT_MCS_DATA_RATE[bw][pvhtpriv->sgi_80m][((pvhtpriv->vht_highest_rate - MGN_VHT1SS_MCS0) & 0x3f)];
-+	HighestRate = (HighestRate + 1) >> 1;
-+
-+	SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(pcap, HighestRate); /* indicate we support highest rx rate is 600Mbps. */
-+	SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(pcap, HighestRate); /* indicate we support highest tx rate is 600Mbps. */
-+
-+	pbuf = rtw_set_ie(pbuf, EID_VHTCapability, 12, pcap, &len);
-+
-+	return len;
-+}
-+
-+u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	RT_CHANNEL_INFO *chset = rfctl->channel_set;
-+	u32	ielen;
-+	u8 max_bw;
-+	u8 oper_ch, oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	u8 *out_vht_op_ie, *ht_op_ie, *vht_cap_ie, *vht_op_ie;
-+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct vht_priv	*pvhtpriv = &pmlmepriv->vhtpriv;
-+
-+	rtw_vht_use_default_setting(padapter);
-+
-+	ht_op_ie = rtw_get_ie(in_ie + 12, WLAN_EID_HT_OPERATION, &ielen, in_len - 12);
-+	if (!ht_op_ie || ielen != HT_OP_IE_LEN)
-+		goto exit;
-+	vht_cap_ie = rtw_get_ie(in_ie + 12, EID_VHTCapability, &ielen, in_len - 12);
-+	if (!vht_cap_ie || ielen != VHT_CAP_IE_LEN)
-+		goto exit;
-+	vht_op_ie = rtw_get_ie(in_ie + 12, EID_VHTOperation, &ielen, in_len - 12);
-+	if (!vht_op_ie || ielen != VHT_OP_IE_LEN)
-+		goto exit;
-+
-+	/* VHT Capabilities element */
-+	*pout_len += rtw_build_vht_cap_ie(padapter, out_ie + *pout_len);
-+
-+
-+	/* VHT Operation element */
-+	out_vht_op_ie = out_ie + *pout_len;
-+	rtw_set_ie(out_vht_op_ie, EID_VHTOperation, VHT_OP_IE_LEN, vht_op_ie + 2 , pout_len);
-+
-+	/* get primary channel from HT_OP_IE */
-+	oper_ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2);
-+
-+	/* find the largest bw supported by both registry and hal */
-+	max_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
-+
-+	if (max_bw >= CHANNEL_WIDTH_40) {
-+		/* get bw offset form HT_OP_IE */
-+		if (GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2)) {
-+			switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) {
-+			case SCA:
-+				oper_bw = CHANNEL_WIDTH_40;
-+				oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+				break;
-+			case SCB:
-+				oper_bw = CHANNEL_WIDTH_40;
-+				oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+				break;
-+			}
-+		}
-+
-+		if (oper_bw == CHANNEL_WIDTH_40) {
-+			switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2)) {
-+			case 1: /* 80MHz */
-+			case 2: /* 160MHz */
-+			case 3: /* 80+80 */
-+				oper_bw = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */
-+				break;
-+			}
-+
-+			oper_bw = rtw_min(oper_bw, max_bw);
-+
-+			/* try downgrage bw to fit in channel plan setting */
-+			while (!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset, 1, 1)
-+				|| (IS_DFS_SLAVE_WITH_RD(rfctl)
-+					&& !rtw_rfctl_dfs_domain_unknown(rfctl)
-+					&& rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset))
-+			) {
-+				oper_bw--;
-+				if (oper_bw == CHANNEL_WIDTH_20) {
-+					oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+					break;
-+				}
-+			}
-+		}
-+	}
-+
-+	rtw_warn_on(!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset, 1, 1));
-+	if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_rfctl_dfs_domain_unknown(rfctl))
-+		rtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset));
-+
-+	/* update VHT_OP_IE */
-+	if (oper_bw < CHANNEL_WIDTH_80) {
-+		SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 0);
-+		SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, 0);
-+		SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0);
-+	} else if (oper_bw == CHANNEL_WIDTH_80) {
-+		u8 cch = rtw_get_center_ch(oper_ch, oper_bw, oper_offset);
-+
-+		SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 1);
-+		SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, cch);
-+		SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0);
-+	} else {
-+		RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(padapter), oper_bw);
-+		rtw_warn_on(1);
-+	}
-+
-+	/* Operating Mode Notification element */
-+	*pout_len += rtw_build_vht_op_mode_notify_ie(padapter, out_ie + *pout_len, oper_bw);
-+
-+	pvhtpriv->vht_option = _TRUE;
-+
-+exit:
-+	return pvhtpriv->vht_option;
-+
-+}
-+
-+void VHTOnAssocRsp(_adapter *padapter)
-+{
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct vht_priv		*pvhtpriv = &pmlmepriv->vhtpriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8	ht_AMPDU_len;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	if (!pmlmeinfo->HT_enable)
-+		return;
-+
-+	if (!pmlmeinfo->VHT_enable)
-+		return;
-+
-+	ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
-+
-+	if (pvhtpriv->ampdu_len > ht_AMPDU_len)
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len));
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MAX_TIME, (u8 *)(&pvhtpriv->vht_highest_rate));
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	u8 cap_len, operation_len;
-+	uint len = 0;
-+	sint ie_len = 0;
-+	u8 *p = NULL;
-+
-+	p = rtw_get_ie(pnetwork->IEs + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len,
-+			(pnetwork->IELength - _BEACON_IE_OFFSET_));
-+	if (p && ie_len > 0)
-+		return;
-+
-+	rtw_vht_use_default_setting(padapter);
-+
-+	/* VHT Operation mode notifiy bit in Extended IE (127) */
-+	SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1);
-+	pmlmepriv->ext_capab_ie_len = 10;
-+	rtw_set_ie(pnetwork->IEs + pnetwork->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len);
-+	pnetwork->IELength += pmlmepriv->ext_capab_ie_len;
-+
-+	/* VHT Capabilities element */
-+	cap_len = rtw_build_vht_cap_ie(padapter, pnetwork->IEs + pnetwork->IELength);
-+	pnetwork->IELength += cap_len;
-+
-+	/* VHT Operation element */
-+	operation_len = rtw_build_vht_operation_ie(padapter, pnetwork->IEs + pnetwork->IELength,
-+										pnetwork->Configuration.DSConfig);
-+	pnetwork->IELength += operation_len;
-+
-+	rtw_check_for_vht20(padapter, pnetwork->IEs + _BEACON_IE_OFFSET_, pnetwork->IELength - _BEACON_IE_OFFSET_);
-+
-+	pmlmepriv->vhtpriv.vht_option = _TRUE;
-+}
-+
-+void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	rtw_remove_bcn_ie(padapter, pnetwork, EID_EXTCapability);
-+	rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTCapability);
-+	rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTOperation);
-+
-+	pmlmepriv->vhtpriv.vht_option = _FALSE;
-+}
-+
-+void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len)
-+{
-+	u8 ht_ch, ht_bw, ht_offset;
-+	u8 vht_ch, vht_bw, vht_offset;
-+
-+	rtw_ies_get_chbw(ies, ies_len, &ht_ch, &ht_bw, &ht_offset, 1, 0);
-+	rtw_ies_get_chbw(ies, ies_len, &vht_ch, &vht_bw, &vht_offset, 1, 1);
-+
-+	if (ht_bw == CHANNEL_WIDTH_20 && vht_bw >= CHANNEL_WIDTH_80) {
-+		u8 *vht_op_ie;
-+		int vht_op_ielen;
-+
-+		RTW_INFO(FUNC_ADPT_FMT" vht80 is not allowed without ht40\n", FUNC_ADPT_ARG(adapter));
-+		vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len);
-+		if (vht_op_ie && vht_op_ielen) {
-+			RTW_INFO(FUNC_ADPT_FMT" switch to vht20\n", FUNC_ADPT_ARG(adapter));
-+			SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0);
-+			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0);
-+			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);
-+		}
-+	}
-+}
-+#endif /* CONFIG_AP_MODE */
-+#endif /* CONFIG_80211AC_VHT */
-diff --git a/drivers/staging/rtl8723cs/core/rtw_wapi.c b/drivers/staging/rtl8723cs/core/rtw_wapi.c
-new file mode 100644
-index 000000000000..94b26e72513f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_wapi.c
-@@ -0,0 +1,1320 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifdef CONFIG_WAPI_SUPPORT
-+
-+#include <linux/unistd.h>
-+#include <linux/etherdevice.h>
-+#include <drv_types.h>
-+#include <rtw_wapi.h>
-+
-+
-+u32 wapi_debug_component =
-+	/*				WAPI_INIT	|
-+	 *				WAPI_API	|
-+	 *				WAPI_TX	|
-+	 *				WAPI_RX	| */
-+	WAPI_ERR ; /* always open err flags on */
-+
-+void WapiFreeAllStaInfo(_adapter *padapter)
-+{
-+	PRT_WAPI_T				pWapiInfo;
-+	PRT_WAPI_STA_INFO		pWapiStaInfo;
-+	PRT_WAPI_BKID			pWapiBkid;
-+
-+	WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__);
-+	pWapiInfo = &padapter->wapiInfo;
-+
-+	/* Pust to Idle List */
-+	rtw_wapi_return_all_sta_info(padapter);
-+
-+	/* Sta Info List */
-+	while (!list_empty(&(pWapiInfo->wapiSTAIdleList))) {
-+		pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAIdleList.next, RT_WAPI_STA_INFO, list);
-+		list_del_init(&pWapiStaInfo->list);
-+	}
-+
-+	/* BKID List */
-+	while (!list_empty(&(pWapiInfo->wapiBKIDIdleList))) {
-+		pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDIdleList.next, RT_WAPI_BKID, list);
-+		list_del_init(&pWapiBkid->list);
-+	}
-+	WAPI_TRACE(WAPI_INIT, "<=========== %s\n", __FUNCTION__);
-+	return;
-+}
-+
-+void WapiSetIE(_adapter *padapter)
-+{
-+	PRT_WAPI_T		pWapiInfo = &(padapter->wapiInfo);
-+	/* PRT_WAPI_BKID	pWapiBkid; */
-+	u16		protocolVer = 1;
-+	u16		akmCnt = 1;
-+	u16		suiteCnt = 1;
-+	u16		capability = 0;
-+	u8		OUI[3];
-+
-+	OUI[0] = 0x00;
-+	OUI[1] = 0x14;
-+	OUI[2] = 0x72;
-+
-+	pWapiInfo->wapiIELength = 0;
-+	/* protocol version */
-+	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &protocolVer, 2);
-+	pWapiInfo->wapiIELength += 2;
-+	/* akm */
-+	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &akmCnt, 2);
-+	pWapiInfo->wapiIELength += 2;
-+
-+	if (pWapiInfo->bWapiPSK) {
-+		memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);
-+		pWapiInfo->wapiIELength += 3;
-+		pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x2;
-+		pWapiInfo->wapiIELength += 1;
-+	} else {
-+		memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);
-+		pWapiInfo->wapiIELength += 3;
-+		pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1;
-+		pWapiInfo->wapiIELength += 1;
-+	}
-+
-+	/* usk */
-+	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &suiteCnt, 2);
-+	pWapiInfo->wapiIELength += 2;
-+	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);
-+	pWapiInfo->wapiIELength += 3;
-+	pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1;
-+	pWapiInfo->wapiIELength += 1;
-+
-+	/* msk */
-+	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, OUI, 3);
-+	pWapiInfo->wapiIELength += 3;
-+	pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1;
-+	pWapiInfo->wapiIELength += 1;
-+
-+	/* Capbility */
-+	memcpy(pWapiInfo->wapiIE + pWapiInfo->wapiIELength, &capability, 2);
-+	pWapiInfo->wapiIELength += 2;
-+}
-+
-+
-+/*  PN1 > PN2, return 1,
-+ *  else return 0.
-+ */
-+u32 WapiComparePN(u8 *PN1, u8 *PN2)
-+{
-+	char i;
-+
-+	if ((NULL == PN1) || (NULL == PN2))
-+		return 1;
-+
-+	/* overflow case */
-+	if ((PN2[15] - PN1[15]) & 0x80)
-+		return 1;
-+
-+	for (i = 16; i > 0; i--) {
-+		if (PN1[i - 1] == PN2[i - 1])
-+			continue;
-+		else if (PN1[i - 1] > PN2[i - 1])
-+			return 1;
-+		else
-+			return 0;
-+	}
-+
-+	return 0;
-+}
-+
-+u8
-+WapiGetEntryForCamWrite(_adapter *padapter, u8 *pMacAddr, u8 KID, BOOLEAN IsMsk)
-+{
-+	PRT_WAPI_T		pWapiInfo = NULL;
-+	/* PRT_WAPI_CAM_ENTRY	pEntry=NULL; */
-+	u8 i = 0;
-+	u8 ret = 0xff;
-+
-+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
-+
-+	pWapiInfo =  &padapter->wapiInfo;
-+
-+	/* exist? */
-+	for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
-+		if (pWapiInfo->wapiCamEntry[i].IsUsed
-+		    && (_rtw_memcmp(pMacAddr, pWapiInfo->wapiCamEntry[i].PeerMacAddr, ETH_ALEN) == _TRUE)
-+		    && pWapiInfo->wapiCamEntry[i].keyidx == KID
-+		    && pWapiInfo->wapiCamEntry[i].type == IsMsk) {
-+			ret = pWapiInfo->wapiCamEntry[i].entry_idx; /* cover it */
-+			break;
-+		}
-+	}
-+
-+	if (i == WAPI_CAM_ENTRY_NUM) { /* not found */
-+		for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
-+			if (pWapiInfo->wapiCamEntry[i].IsUsed == 0) {
-+				pWapiInfo->wapiCamEntry[i].IsUsed = 1;
-+				pWapiInfo->wapiCamEntry[i].type = IsMsk;
-+				pWapiInfo->wapiCamEntry[i].keyidx = KID;
-+				_rtw_memcpy(pWapiInfo->wapiCamEntry[i].PeerMacAddr, pMacAddr, ETH_ALEN);
-+				ret = pWapiInfo->wapiCamEntry[i].entry_idx;
-+				break;
-+			}
-+		}
-+	}
-+
-+	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
-+	return ret;
-+
-+	/*
-+		if(RTIsListEmpty(&pWapiInfo->wapiCamIdleList)) {
-+			return 0;
-+		}
-+
-+		pEntry = (PRT_WAPI_CAM_ENTRY)RTRemoveHeadList(&pWapiInfo->wapiCamIdleList);
-+		RTInsertTailList(&pWapiInfo->wapiCamUsedList, &pEntry->list);
-+
-+
-+		return pEntry->entry_idx;*/
-+}
-+
-+u8 WapiGetEntryForCamClear(_adapter *padapter, u8 *pPeerMac, u8 keyid, u8 IsMsk)
-+{
-+	PRT_WAPI_T		pWapiInfo = NULL;
-+	u8		i = 0;
-+
-+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
-+
-+	pWapiInfo =  &padapter->wapiInfo;
-+
-+	for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
-+		if (pWapiInfo->wapiCamEntry[i].IsUsed
-+		    && (_rtw_memcmp(pPeerMac, pWapiInfo->wapiCamEntry[i].PeerMacAddr, ETH_ALEN) == _TRUE)
-+		    && pWapiInfo->wapiCamEntry[i].keyidx == keyid
-+		    && pWapiInfo->wapiCamEntry[i].type == IsMsk) {
-+			pWapiInfo->wapiCamEntry[i].IsUsed = 0;
-+			pWapiInfo->wapiCamEntry[i].keyidx = 2;
-+			_rtw_memset(pWapiInfo->wapiCamEntry[i].PeerMacAddr, 0, ETH_ALEN);
-+
-+			WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
-+			return pWapiInfo->wapiCamEntry[i].entry_idx;
-+		}
-+	}
-+
-+	WAPI_TRACE(WAPI_API, "<====WapiGetReturnCamEntry(), No this cam entry.\n");
-+	return 0xff;
-+	/*
-+		if(RTIsListEmpty(&pWapiInfo->wapiCamUsedList)) {
-+			return FALSE;
-+		}
-+
-+		pList = &pWapiInfo->wapiCamUsedList;
-+		while(pList->Flink != &pWapiInfo->wapiCamUsedList)
-+		{
-+			pEntry = (PRT_WAPI_CAM_ENTRY)pList->Flink;
-+			if(PlatformCompareMemory(pPeerMac,pEntry->PeerMacAddr, ETHER_ADDRLEN)== 0
-+				&& keyid == pEntry->keyidx)
-+			{
-+				RTRemoveEntryList(pList);
-+				RTInsertHeadList(&pWapiInfo->wapiCamIdleList, pList);
-+				return pEntry->entry_idx;
-+			}
-+			pList = pList->Flink;
-+		}
-+
-+		return 0;
-+	*/
-+}
-+
-+void
-+WapiResetAllCamEntry(_adapter *padapter)
-+{
-+	PRT_WAPI_T		pWapiInfo;
-+	int				i;
-+
-+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
-+
-+	pWapiInfo =  &padapter->wapiInfo;
-+
-+	for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
-+		_rtw_memset(pWapiInfo->wapiCamEntry[i].PeerMacAddr, 0, ETH_ALEN);
-+		pWapiInfo->wapiCamEntry[i].IsUsed = 0;
-+		pWapiInfo->wapiCamEntry[i].keyidx = 2; /* invalid */
-+		pWapiInfo->wapiCamEntry[i].entry_idx = 4 + i * 2;
-+	}
-+
-+	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
-+
-+	return;
-+}
-+
-+u8 WapiWriteOneCamEntry(
-+	_adapter	*padapter,
-+	u8			*pMacAddr,
-+	u8			KeyId,
-+	u8			EntryId,
-+	u8			EncAlg,
-+	u8			bGroupKey,
-+	u8			*pKey
-+)
-+{
-+	u8 retVal = 0;
-+	u16 usConfig = 0;
-+
-+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
-+
-+	if (EntryId >= 32) {
-+		WAPI_TRACE(WAPI_ERR, "<=== CamAddOneEntry(): ulKeyId exceed!\n");
-+		return retVal;
-+	}
-+
-+	usConfig = usConfig | (0x01 << 15) | ((u16)(EncAlg) << 2) | (KeyId);
-+
-+	if (EncAlg == _SMS4_) {
-+		if (bGroupKey == 1)
-+			usConfig |= (0x01 << 6);
-+		if ((EntryId % 2) == 1) /* ==0 sec key; == 1mic key */
-+			usConfig |= (0x01 << 5);
-+	}
-+
-+	write_cam(padapter, EntryId, usConfig, pMacAddr, pKey);
-+
-+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
-+	return 1;
-+}
-+
-+void rtw_wapi_init(_adapter *padapter)
-+{
-+	PRT_WAPI_T		pWapiInfo;
-+	int				i;
-+
-+	WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__);
-+	RT_ASSERT_RET(padapter);
-+
-+	if (!padapter->WapiSupport) {
-+		WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	pWapiInfo =  &padapter->wapiInfo;
-+	pWapiInfo->bWapiEnable = false;
-+
-+	/* Init BKID List */
-+	INIT_LIST_HEAD(&pWapiInfo->wapiBKIDIdleList);
-+	INIT_LIST_HEAD(&pWapiInfo->wapiBKIDStoreList);
-+	for (i = 0; i < WAPI_MAX_BKID_NUM; i++)
-+		list_add_tail(&pWapiInfo->wapiBKID[i].list, &pWapiInfo->wapiBKIDIdleList);
-+
-+	/* Init STA List */
-+	INIT_LIST_HEAD(&pWapiInfo->wapiSTAIdleList);
-+	INIT_LIST_HEAD(&pWapiInfo->wapiSTAUsedList);
-+	for (i = 0; i < WAPI_MAX_STAINFO_NUM; i++)
-+		list_add_tail(&pWapiInfo->wapiSta[i].list, &pWapiInfo->wapiSTAIdleList);
-+
-+	for (i = 0; i < WAPI_CAM_ENTRY_NUM; i++) {
-+		pWapiInfo->wapiCamEntry[i].IsUsed = 0;
-+		pWapiInfo->wapiCamEntry[i].keyidx = 2; /* invalid */
-+		pWapiInfo->wapiCamEntry[i].entry_idx = 4 + i * 2;
-+	}
-+
-+	WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__);
-+}
-+
-+void rtw_wapi_free(_adapter *padapter)
-+{
-+	WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__);
-+	RT_ASSERT_RET(padapter);
-+
-+	if (!padapter->WapiSupport) {
-+		WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	WapiFreeAllStaInfo(padapter);
-+
-+	WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__);
-+}
-+
-+void rtw_wapi_disable_tx(_adapter *padapter)
-+{
-+	WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__);
-+	RT_ASSERT_RET(padapter);
-+
-+	if (!padapter->WapiSupport) {
-+		WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	padapter->wapiInfo.wapiTxMsk.bTxEnable = false;
-+	padapter->wapiInfo.wapiTxMsk.bSet = false;
-+
-+	WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__);
-+}
-+
-+u8 rtw_wapi_is_wai_packet(_adapter *padapter, u8 *pkt_data)
-+{
-+	PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct security_priv   *psecuritypriv = &padapter->securitypriv;
-+	PRT_WAPI_STA_INFO pWapiSta = NULL;
-+	u8 WaiPkt = 0, *pTaddr, bFind = false;
-+	u8 Offset_TypeWAI = 0 ;	/* (mac header len + llc length) */
-+
-+	WAPI_TRACE(WAPI_TX | WAPI_RX, "===========> %s\n", __FUNCTION__);
-+
-+	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
-+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
-+		return 0;
-+	}
-+
-+	Offset_TypeWAI = 24 + 6 ;
-+
-+	/* YJ,add,091103. Data frame may also have skb->data[30]=0x88 and skb->data[31]=0xb4. */
-+	if ((pkt_data[1] & 0x40) != 0) {
-+		/* RTW_INFO("data is privacy\n"); */
-+		return 0;
-+	}
-+
-+	pTaddr = get_addr2_ptr(pkt_data);
-+	if (list_empty(&pWapiInfo->wapiSTAUsedList))
-+		bFind = false;
-+	else {
-+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
-+			if (_rtw_memcmp(pTaddr, pWapiSta->PeerMacAddr, 6) == _TRUE) {
-+				bFind = true;
-+				break;
-+			}
-+		}
-+	}
-+
-+	WAPI_TRACE(WAPI_TX | WAPI_RX, "%s: bFind=%d pTaddr="MAC_FMT"\n", __FUNCTION__, bFind, MAC_ARG(pTaddr));
-+
-+	if (pkt_data[0] == WIFI_QOS_DATA_TYPE)
-+		Offset_TypeWAI += 2;
-+
-+	/* 88b4? */
-+	if ((pkt_data[Offset_TypeWAI] == 0x88) && (pkt_data[Offset_TypeWAI + 1] == 0xb4)) {
-+		WaiPkt = pkt_data[Offset_TypeWAI + 5];
-+
-+		psecuritypriv->hw_decrypted = _TRUE;
-+	} else
-+		WAPI_TRACE(WAPI_TX | WAPI_RX, "%s(): non wai packet\n", __FUNCTION__);
-+
-+	WAPI_TRACE(WAPI_TX | WAPI_RX, "%s(): Recvd WAI frame. IsWAIPkt(%d)\n", __FUNCTION__, WaiPkt);
-+
-+	return	WaiPkt;
-+}
-+
-+
-+void rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	PRT_WAPI_T     pWapiInfo = &(padapter->wapiInfo);
-+	struct recv_frame_hdr *precv_hdr;
-+	u8	*ptr;
-+	u8	*pTA;
-+	u8	*pRecvPN;
-+
-+
-+	WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
-+
-+	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
-+		WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	precv_hdr = &precv_frame->u.hdr;
-+	ptr = precv_hdr->rx_data;
-+
-+	if (precv_hdr->attrib.qos == 1)
-+		precv_hdr->UserPriority = GetTid(ptr);
-+	else
-+		precv_hdr->UserPriority = 0;
-+
-+	pTA = get_addr2_ptr(ptr);
-+	_rtw_memcpy((u8 *)precv_hdr->WapiSrcAddr, pTA, 6);
-+	pRecvPN = ptr + precv_hdr->attrib.hdrlen + 2;
-+	_rtw_memcpy((u8 *)precv_hdr->WapiTempPN, pRecvPN, 16);
-+
-+	WAPI_TRACE(WAPI_RX, "<========== %s\n", __FUNCTION__);
-+}
-+
-+/****************************************************************************
-+TRUE-----------------Drop
-+FALSE---------------- handle
-+add to support WAPI to N-mode
-+*****************************************************************************/
-+u8 rtw_wapi_check_for_drop(
-+	_adapter *padapter,
-+	union recv_frame *precv_frame,
-+	u8 *ehdr_ops
-+)
-+{
-+	PRT_WAPI_T     pWapiInfo = &(padapter->wapiInfo);
-+	u8			*pLastRecvPN = NULL;
-+	u8			bFind = false;
-+	PRT_WAPI_STA_INFO	pWapiSta = NULL;
-+	u8			bDrop = false;
-+	struct recv_frame_hdr *precv_hdr = &precv_frame->u.hdr;
-+	u8					WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
-+	u8					WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
-+	u8					*ptr = ehdr_ops;
-+	int					i;
-+
-+	WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
-+
-+	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
-+		WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
-+		return false;
-+	}
-+
-+	if (precv_hdr->bIsWaiPacket != 0) {
-+		if (precv_hdr->bIsWaiPacket == 0x8) {
-+
-+			RTW_INFO("rtw_wapi_check_for_drop: dump packet\n");
-+			for (i = 0; i < 50; i++) {
-+				RTW_INFO("%02X  ", ptr[i]);
-+				if ((i + 1) % 8 == 0)
-+					RTW_INFO("\n");
-+			}
-+			RTW_INFO("\n rtw_wapi_check_for_drop: dump packet\n");
-+
-+			for (i = 0; i < 16; i++) {
-+				if (ptr[i + 27] != 0)
-+					break;
-+			}
-+
-+			if (i == 16) {
-+				WAPI_TRACE(WAPI_RX, "rtw_wapi_check_for_drop: drop with zero BKID\n");
-+				return true;
-+			} else
-+				return false;
-+		} else
-+			return false;
-+	}
-+
-+	if (list_empty(&pWapiInfo->wapiSTAUsedList))
-+		bFind = false;
-+	else {
-+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
-+			if (_rtw_memcmp(precv_hdr->WapiSrcAddr, pWapiSta->PeerMacAddr, ETH_ALEN) == _TRUE) {
-+				bFind = true;
-+				break;
-+			}
-+		}
-+	}
-+	WAPI_TRACE(WAPI_RX, "%s: bFind=%d prxb->WapiSrcAddr="MAC_FMT"\n", __FUNCTION__, bFind, MAC_ARG(precv_hdr->WapiSrcAddr));
-+
-+	if (bFind) {
-+		if (IS_MCAST(precv_hdr->attrib.ra)) {
-+			WAPI_TRACE(WAPI_RX, "rtw_wapi_check_for_drop: multicast case\n");
-+			pLastRecvPN = pWapiSta->lastRxMulticastPN;
-+		} else {
-+			WAPI_TRACE(WAPI_RX, "rtw_wapi_check_for_drop: unicast case\n");
-+			switch (precv_hdr->UserPriority) {
-+			case 0:
-+			case 3:
-+				pLastRecvPN = pWapiSta->lastRxUnicastPNBEQueue;
-+				break;
-+			case 1:
-+			case 2:
-+				pLastRecvPN = pWapiSta->lastRxUnicastPNBKQueue;
-+				break;
-+			case 4:
-+			case 5:
-+				pLastRecvPN = pWapiSta->lastRxUnicastPNVIQueue;
-+				break;
-+			case 6:
-+			case 7:
-+				pLastRecvPN = pWapiSta->lastRxUnicastPNVOQueue;
-+				break;
-+			default:
-+				WAPI_TRACE(WAPI_ERR, "%s: Unknown TID\n", __FUNCTION__);
-+				break;
-+			}
-+		}
-+
-+		if (!WapiComparePN(precv_hdr->WapiTempPN, pLastRecvPN)) {
-+			WAPI_TRACE(WAPI_RX, "%s: Equal PN!!\n", __FUNCTION__);
-+			if (IS_MCAST(precv_hdr->attrib.ra))
-+				_rtw_memcpy(pLastRecvPN, WapiAEMultiCastPNInitialValueSrc, 16);
-+			else
-+				_rtw_memcpy(pLastRecvPN, WapiAEPNInitialValueSrc, 16);
-+			bDrop = true;
-+		} else
-+			_rtw_memcpy(pLastRecvPN, precv_hdr->WapiTempPN, 16);
-+	}
-+
-+	WAPI_TRACE(WAPI_RX, "<========== %s\n", __FUNCTION__);
-+	return bDrop;
-+}
-+
-+void rtw_build_probe_resp_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib)
-+{
-+	PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);
-+	u8 WapiIELength = 0;
-+
-+	WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__);
-+
-+	if ((!padapter->WapiSupport)  || (!pWapiInfo->bWapiEnable)) {
-+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	WapiSetIE(padapter);
-+	WapiIELength = pWapiInfo->wapiIELength;
-+	pframe[0] = _WAPI_IE_;
-+	pframe[1] = WapiIELength;
-+	_rtw_memcpy(pframe + 2, pWapiInfo->wapiIE, WapiIELength);
-+	pframe += WapiIELength + 2;
-+	pattrib->pktlen += WapiIELength + 2;
-+
-+	WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__);
-+}
-+
-+void rtw_build_beacon_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib)
-+{
-+	PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);
-+	u8 WapiIELength = 0;
-+	WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__);
-+
-+	if ((!padapter->WapiSupport)  || (!pWapiInfo->bWapiEnable)) {
-+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	WapiSetIE(padapter);
-+	WapiIELength = pWapiInfo->wapiIELength;
-+	pframe[0] = _WAPI_IE_;
-+	pframe[1] = WapiIELength;
-+	_rtw_memcpy(pframe + 2, pWapiInfo->wapiIE, WapiIELength);
-+	pframe += WapiIELength + 2;
-+	pattrib->pktlen += WapiIELength + 2;
-+
-+	WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__);
-+}
-+
-+void rtw_build_assoc_req_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib)
-+{
-+	PRT_WAPI_BKID		pWapiBKID;
-+	u16					bkidNum;
-+	PRT_WAPI_T			pWapiInfo = &(padapter->wapiInfo);
-+	u8					WapiIELength = 0;
-+
-+	WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__);
-+
-+	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
-+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	WapiSetIE(padapter);
-+	WapiIELength = pWapiInfo->wapiIELength;
-+	bkidNum = 0;
-+	if (!list_empty(&(pWapiInfo->wapiBKIDStoreList))) {
-+		list_for_each_entry(pWapiBKID, &pWapiInfo->wapiBKIDStoreList, list) {
-+			bkidNum++;
-+			_rtw_memcpy(pWapiInfo->wapiIE + WapiIELength + 2, pWapiBKID->bkid, 16);
-+			WapiIELength += 16;
-+		}
-+	}
-+	_rtw_memcpy(pWapiInfo->wapiIE + WapiIELength, &bkidNum, 2);
-+	WapiIELength += 2;
-+
-+	pframe[0] = _WAPI_IE_;
-+	pframe[1] = WapiIELength;
-+	_rtw_memcpy(pframe + 2, pWapiInfo->wapiIE, WapiIELength);
-+	pframe += WapiIELength + 2;
-+	pattrib->pktlen += WapiIELength + 2;
-+	WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__);
-+}
-+
-+void rtw_wapi_on_assoc_ok(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+	PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);
-+	PRT_WAPI_STA_INFO pWapiSta;
-+	u8 WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
-+	/* u8 WapiASUEPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; */
-+	u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
-+
-+	WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__);
-+
-+	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
-+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	pWapiSta = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAIdleList.next, RT_WAPI_STA_INFO, list);
-+	list_del_init(&pWapiSta->list);
-+	list_add_tail(&pWapiSta->list, &pWapiInfo->wapiSTAUsedList);
-+	_rtw_memcpy(pWapiSta->PeerMacAddr, padapter->mlmeextpriv.mlmext_info.network.MacAddress, 6);
-+	_rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16);
-+	_rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16);
-+
-+	/* For chenk PN error with Qos Data after s3: add by ylb 20111114 */
-+	_rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16);
-+	_rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16);
-+	_rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16);
-+	_rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16);
-+
-+	WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__);
-+}
-+
-+
-+void rtw_wapi_return_one_sta_info(_adapter *padapter, u8 *MacAddr)
-+{
-+	PRT_WAPI_T				pWapiInfo;
-+	PRT_WAPI_STA_INFO		pWapiStaInfo = NULL;
-+	PRT_WAPI_BKID			pWapiBkid = NULL;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+
-+	pWapiInfo = &padapter->wapiInfo;
-+
-+	WAPI_TRACE(WAPI_API, "==========> %s\n", __FUNCTION__);
-+
-+	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
-+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
-+		while (!list_empty(&(pWapiInfo->wapiBKIDStoreList))) {
-+			pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDStoreList.next, RT_WAPI_BKID, list);
-+			list_del_init(&pWapiBkid->list);
-+			_rtw_memset(pWapiBkid->bkid, 0, 16);
-+			list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDIdleList);
-+		}
-+	}
-+
-+
-+	WAPI_TRACE(WAPI_API, " %s: after clear bkid\n", __FUNCTION__);
-+
-+
-+	/* Remove STA info */
-+	if (list_empty(&(pWapiInfo->wapiSTAUsedList))) {
-+		WAPI_TRACE(WAPI_API, " %s: wapiSTAUsedList is null\n", __FUNCTION__);
-+		return;
-+	} else {
-+
-+		WAPI_TRACE(WAPI_API, " %s: wapiSTAUsedList is not null\n", __FUNCTION__);
-+#if 0
-+		pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry((pWapiInfo->wapiSTAUsedList.next), RT_WAPI_STA_INFO, list);
-+
-+		list_for_each_entry(pWapiStaInfo, &(pWapiInfo->wapiSTAUsedList), list) {
-+
-+			RTW_INFO("MAC Addr %02x-%02x-%02x-%02x-%02x-%02x\n", MacAddr[0], MacAddr[1], MacAddr[2], MacAddr[3], MacAddr[4], MacAddr[5]);
-+
-+
-+			RTW_INFO("peer Addr %02x-%02x-%02x-%02x-%02x-%02x\n", pWapiStaInfo->PeerMacAddr[0], pWapiStaInfo->PeerMacAddr[1], pWapiStaInfo->PeerMacAddr[2], pWapiStaInfo->PeerMacAddr[3],
-+				pWapiStaInfo->PeerMacAddr[4], pWapiStaInfo->PeerMacAddr[5]);
-+
-+			if (pWapiStaInfo == NULL) {
-+				WAPI_TRACE(WAPI_API, " %s: pWapiStaInfo == NULL Case\n", __FUNCTION__);
-+				return;
-+			}
-+
-+			if (pWapiStaInfo->PeerMacAddr == NULL) {
-+				WAPI_TRACE(WAPI_API, " %s: pWapiStaInfo->PeerMacAddr == NULL Case\n", __FUNCTION__);
-+				return;
-+			}
-+
-+			if (MacAddr == NULL) {
-+				WAPI_TRACE(WAPI_API, " %s: MacAddr == NULL Case\n", __FUNCTION__);
-+				return;
-+			}
-+
-+			if (_rtw_memcmp(pWapiStaInfo->PeerMacAddr, MacAddr, ETH_ALEN) == _TRUE) {
-+				pWapiStaInfo->bAuthenticateInProgress = false;
-+				pWapiStaInfo->bSetkeyOk = false;
-+				_rtw_memset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN);
-+				list_del_init(&pWapiStaInfo->list);
-+				list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList);
-+				break;
-+			}
-+
-+		}
-+#endif
-+
-+		while (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {
-+			pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAUsedList.next, RT_WAPI_STA_INFO, list);
-+
-+			RTW_INFO("peer Addr %02x-%02x-%02x-%02x-%02x-%02x\n", pWapiStaInfo->PeerMacAddr[0], pWapiStaInfo->PeerMacAddr[1], pWapiStaInfo->PeerMacAddr[2], pWapiStaInfo->PeerMacAddr[3],
-+				pWapiStaInfo->PeerMacAddr[4], pWapiStaInfo->PeerMacAddr[5]);
-+
-+			list_del_init(&pWapiStaInfo->list);
-+			memset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN);
-+			pWapiStaInfo->bSetkeyOk = 0;
-+			list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList);
-+		}
-+
-+	}
-+
-+	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
-+	return;
-+}
-+
-+void rtw_wapi_return_all_sta_info(_adapter *padapter)
-+{
-+	PRT_WAPI_T				pWapiInfo;
-+	PRT_WAPI_STA_INFO		pWapiStaInfo;
-+	PRT_WAPI_BKID			pWapiBkid;
-+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
-+
-+	pWapiInfo = &padapter->wapiInfo;
-+
-+	if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) {
-+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	/* Sta Info List */
-+	while (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {
-+		pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAUsedList.next, RT_WAPI_STA_INFO, list);
-+		list_del_init(&pWapiStaInfo->list);
-+		memset(pWapiStaInfo->PeerMacAddr, 0, ETH_ALEN);
-+		pWapiStaInfo->bSetkeyOk = 0;
-+		list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList);
-+	}
-+
-+	/* BKID List */
-+	while (!list_empty(&(pWapiInfo->wapiBKIDStoreList))) {
-+		pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDStoreList.next, RT_WAPI_BKID, list);
-+		list_del_init(&pWapiBkid->list);
-+		memset(pWapiBkid->bkid, 0, 16);
-+		list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDIdleList);
-+	}
-+	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
-+}
-+
-+void CAM_empty_entry(
-+	PADAPTER	Adapter,
-+	u8			ucIndex
-+)
-+{
-+	rtw_hal_set_hwreg(Adapter, HW_VAR_CAM_EMPTY_ENTRY, (u8 *)(&ucIndex));
-+}
-+
-+void rtw_wapi_clear_cam_entry(_adapter *padapter, u8 *pMacAddr)
-+{
-+	u8 UcIndex = 0;
-+
-+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
-+
-+	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
-+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 0, 0);
-+	if (UcIndex != 0xff) {
-+		/* CAM_mark_invalid(Adapter, UcIndex); */
-+		CAM_empty_entry(padapter, UcIndex);
-+	}
-+
-+	UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 1, 0);
-+	if (UcIndex != 0xff) {
-+		/* CAM_mark_invalid(Adapter, UcIndex); */
-+		CAM_empty_entry(padapter, UcIndex);
-+	}
-+
-+	UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 0, 1);
-+	if (UcIndex != 0xff) {
-+		/* CAM_mark_invalid(Adapter, UcIndex); */
-+		CAM_empty_entry(padapter, UcIndex);
-+	}
-+
-+	UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 1, 1);
-+	if (UcIndex != 0xff) {
-+		/* CAM_mark_invalid(padapter, UcIndex); */
-+		CAM_empty_entry(padapter, UcIndex);
-+	}
-+
-+	WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__);
-+}
-+
-+void rtw_wapi_clear_all_cam_entry(_adapter *padapter)
-+{
-+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
-+
-+	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
-+		WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	invalidate_cam_all(padapter); /* is this ok? */
-+	WapiResetAllCamEntry(padapter);
-+
-+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
-+}
-+
-+void rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey, u8 bUseDefaultKey)
-+{
-+	PRT_WAPI_T		pWapiInfo =  &padapter->wapiInfo;
-+	u8				*pMacAddr = pWapiSta->PeerMacAddr;
-+	u32 EntryId = 0;
-+	BOOLEAN IsPairWise = false ;
-+	u8 EncAlgo;
-+
-+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
-+
-+	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
-+		WAPI_TRACE(WAPI_API, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__);
-+		return;
-+	}
-+
-+	EncAlgo = _SMS4_;
-+
-+	/* For Tx bc/mc pkt,use defualt key entry */
-+	if (bUseDefaultKey) {
-+		/* when WAPI update key, keyid will be 0 or 1 by turns. */
-+		if (pWapiKey->keyId == 0)
-+			EntryId = 0;
-+		else
-+			EntryId = 2;
-+	} else {
-+		/* tx/rx unicast pkt, or rx broadcast, find the key entry by peer's MacAddr */
-+		EntryId = WapiGetEntryForCamWrite(padapter, pMacAddr, pWapiKey->keyId, bGroupKey);
-+	}
-+
-+	if (EntryId == 0xff) {
-+		WAPI_TRACE(WAPI_API, "===>No entry for WAPI setkey! !!\n");
-+		return;
-+	}
-+
-+	/* EntryId is also used to diff Sec key and Mic key */
-+	/* Sec Key */
-+	WapiWriteOneCamEntry(padapter,
-+			     pMacAddr,
-+			     pWapiKey->keyId, /* keyid */
-+			     EntryId,	/* entry */
-+			     EncAlgo, /* type */
-+			     bGroupKey, /* pairwise or group key */
-+			     pWapiKey->dataKey);
-+	/* MIC key */
-+	WapiWriteOneCamEntry(padapter,
-+			     pMacAddr,
-+			     pWapiKey->keyId, /* keyid */
-+			     EntryId + 1,	/* entry */
-+			     EncAlgo, /* type */
-+			     bGroupKey, /* pairwise or group key */
-+			     pWapiKey->micKey);
-+
-+	WAPI_TRACE(WAPI_API, "Set Wapi Key :KeyId:%d,EntryId:%d,PairwiseKey:%d.\n", pWapiKey->keyId, EntryId, !bGroupKey);
-+	WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__);
-+
-+}
-+
-+#if 0
-+/* YJ,test,091013 */
-+void wapi_test_set_key(struct _adapter *padapter, u8 *buf)
-+{
-+	/*Data: keyType(1) + bTxEnable(1) + bAuthenticator(1) + bUpdate(1) + PeerAddr(6) + DataKey(16) + MicKey(16) + KeyId(1)*/
-+	PRT_WAPI_T			pWapiInfo = &padapter->wapiInfo;
-+	PRT_WAPI_BKID		pWapiBkid;
-+	PRT_WAPI_STA_INFO	pWapiSta;
-+	u8					data[43];
-+	bool					bTxEnable;
-+	bool					bUpdate;
-+	bool					bAuthenticator;
-+	u8					PeerAddr[6];
-+	u8					WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
-+	u8					WapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
-+	u8					WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
-+
-+	WAPI_TRACE(WAPI_INIT, "===========>%s\n", __FUNCTION__);
-+
-+	if (!padapter->WapiSupport)
-+		return;
-+
-+	copy_from_user(data, buf, 43);
-+	bTxEnable = data[1];
-+	bAuthenticator = data[2];
-+	bUpdate = data[3];
-+	memcpy(PeerAddr, data + 4, 6);
-+
-+	if (data[0] == 0x3) {
-+		if (!list_empty(&(pWapiInfo->wapiBKIDIdleList))) {
-+			pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDIdleList.next, RT_WAPI_BKID, list);
-+			list_del_init(&pWapiBkid->list);
-+			memcpy(pWapiBkid->bkid, data + 10, 16);
-+			WAPI_DATA(WAPI_INIT, "SetKey - BKID", pWapiBkid->bkid, 16);
-+			list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDStoreList);
-+		}
-+	} else {
-+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
-+			if (!memcmp(pWapiSta->PeerMacAddr, PeerAddr, 6)) {
-+				pWapiSta->bAuthenticatorInUpdata = false;
-+				switch (data[0]) {
-+				case 1:              /* usk */
-+					if (bAuthenticator) {       /* authenticator */
-+						memcpy(pWapiSta->lastTxUnicastPN, WapiAEPNInitialValueSrc, 16);
-+						if (!bUpdate) {    /* first */
-+							WAPI_TRACE(WAPI_INIT, "AE fisrt set usk\n");
-+							pWapiSta->wapiUsk.bSet = true;
-+							memcpy(pWapiSta->wapiUsk.dataKey, data + 10, 16);
-+							memcpy(pWapiSta->wapiUsk.micKey, data + 26, 16);
-+							pWapiSta->wapiUsk.keyId = *(data + 42);
-+							pWapiSta->wapiUsk.bTxEnable = true;
-+							WAPI_DATA(WAPI_INIT, "SetKey - AE USK Data Key", pWapiSta->wapiUsk.dataKey, 16);
-+							WAPI_DATA(WAPI_INIT, "SetKey - AE USK Mic Key", pWapiSta->wapiUsk.micKey, 16);
-+						} else {           /* update */
-+							WAPI_TRACE(WAPI_INIT, "AE update usk\n");
-+							pWapiSta->wapiUskUpdate.bSet = true;
-+							pWapiSta->bAuthenticatorInUpdata = true;
-+							memcpy(pWapiSta->wapiUskUpdate.dataKey, data + 10, 16);
-+							memcpy(pWapiSta->wapiUskUpdate.micKey, data + 26, 16);
-+							memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiASUEPNInitialValueSrc, 16);
-+							memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiASUEPNInitialValueSrc, 16);
-+							memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiASUEPNInitialValueSrc, 16);
-+							memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiASUEPNInitialValueSrc, 16);
-+							memcpy(pWapiSta->lastRxUnicastPN, WapiASUEPNInitialValueSrc, 16);
-+							pWapiSta->wapiUskUpdate.keyId = *(data + 42);
-+							pWapiSta->wapiUskUpdate.bTxEnable = true;
-+						}
-+					} else {
-+						if (!bUpdate) {
-+							WAPI_TRACE(WAPI_INIT, "ASUE fisrt set usk\n");
-+							if (bTxEnable) {
-+								pWapiSta->wapiUsk.bTxEnable = true;
-+								memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16);
-+							} else {
-+								pWapiSta->wapiUsk.bSet = true;
-+								memcpy(pWapiSta->wapiUsk.dataKey, data + 10, 16);
-+								memcpy(pWapiSta->wapiUsk.micKey, data + 26, 16);
-+								pWapiSta->wapiUsk.keyId = *(data + 42);
-+								pWapiSta->wapiUsk.bTxEnable = false;
-+							}
-+						} else {
-+							WAPI_TRACE(WAPI_INIT, "ASUE update usk\n");
-+							if (bTxEnable) {
-+								pWapiSta->wapiUskUpdate.bTxEnable = true;
-+								if (pWapiSta->wapiUskUpdate.bSet) {
-+									memcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16);
-+									memcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16);
-+									pWapiSta->wapiUsk.keyId = pWapiSta->wapiUskUpdate.keyId;
-+									memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiASUEPNInitialValueSrc, 16);
-+									memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiASUEPNInitialValueSrc, 16);
-+									memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiASUEPNInitialValueSrc, 16);
-+									memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiASUEPNInitialValueSrc, 16);
-+									memcpy(pWapiSta->lastRxUnicastPN, WapiASUEPNInitialValueSrc, 16);
-+									pWapiSta->wapiUskUpdate.bTxEnable = false;
-+									pWapiSta->wapiUskUpdate.bSet = false;
-+								}
-+								memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16);
-+							} else {
-+								pWapiSta->wapiUskUpdate.bSet = true;
-+								memcpy(pWapiSta->wapiUskUpdate.dataKey, data + 10, 16);
-+								memcpy(pWapiSta->wapiUskUpdate.micKey, data + 26, 16);
-+								pWapiSta->wapiUskUpdate.keyId = *(data + 42);
-+								pWapiSta->wapiUskUpdate.bTxEnable = false;
-+							}
-+						}
-+					}
-+					break;
-+				case 2:		/* msk */
-+					if (bAuthenticator) {        /* authenticator */
-+						pWapiInfo->wapiTxMsk.bSet = true;
-+						memcpy(pWapiInfo->wapiTxMsk.dataKey, data + 10, 16);
-+						memcpy(pWapiInfo->wapiTxMsk.micKey, data + 26, 16);
-+						pWapiInfo->wapiTxMsk.keyId = *(data + 42);
-+						pWapiInfo->wapiTxMsk.bTxEnable = true;
-+						memcpy(pWapiInfo->lastTxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16);
-+
-+						if (!bUpdate) {    /* first */
-+							WAPI_TRACE(WAPI_INIT, "AE fisrt set msk\n");
-+							if (!pWapiSta->bSetkeyOk)
-+								pWapiSta->bSetkeyOk = true;
-+							pWapiInfo->bFirstAuthentiateInProgress = false;
-+						} else                /* update */
-+							WAPI_TRACE(WAPI_INIT, "AE update msk\n");
-+
-+						WAPI_DATA(WAPI_INIT, "SetKey - AE MSK Data Key", pWapiInfo->wapiTxMsk.dataKey, 16);
-+						WAPI_DATA(WAPI_INIT, "SetKey - AE MSK Mic Key", pWapiInfo->wapiTxMsk.micKey, 16);
-+					} else {
-+						if (!bUpdate) {
-+							WAPI_TRACE(WAPI_INIT, "ASUE fisrt set msk\n");
-+							pWapiSta->wapiMsk.bSet = true;
-+							memcpy(pWapiSta->wapiMsk.dataKey, data + 10, 16);
-+							memcpy(pWapiSta->wapiMsk.micKey, data + 26, 16);
-+							pWapiSta->wapiMsk.keyId = *(data + 42);
-+							pWapiSta->wapiMsk.bTxEnable = false;
-+							if (!pWapiSta->bSetkeyOk)
-+								pWapiSta->bSetkeyOk = true;
-+							pWapiInfo->bFirstAuthentiateInProgress = false;
-+							WAPI_DATA(WAPI_INIT, "SetKey - ASUE MSK Data Key", pWapiSta->wapiMsk.dataKey, 16);
-+							WAPI_DATA(WAPI_INIT, "SetKey - ASUE MSK Mic Key", pWapiSta->wapiMsk.micKey, 16);
-+						} else {
-+							WAPI_TRACE(WAPI_INIT, "ASUE update msk\n");
-+							pWapiSta->wapiMskUpdate.bSet = true;
-+							memcpy(pWapiSta->wapiMskUpdate.dataKey, data + 10, 16);
-+							memcpy(pWapiSta->wapiMskUpdate.micKey, data + 26, 16);
-+							pWapiSta->wapiMskUpdate.keyId = *(data + 42);
-+							pWapiSta->wapiMskUpdate.bTxEnable = false;
-+						}
-+					}
-+					break;
-+				default:
-+					WAPI_TRACE(WAPI_ERR, "Unknown Flag\n");
-+					break;
-+				}
-+			}
-+		}
-+	}
-+	WAPI_TRACE(WAPI_INIT, "<===========%s\n", __FUNCTION__);
-+}
-+
-+
-+void wapi_test_init(struct _adapter *padapter)
-+{
-+	u8 keybuf[100];
-+	u8 mac_addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x72, 0x04, 0x70};
-+	u8 UskDataKey[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f};
-+	u8 UskMicKey[16] = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f};
-+	u8 UskId = 0;
-+	u8 MskDataKey[16] = {0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f};
-+	u8 MskMicKey[16] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f};
-+	u8 MskId = 0;
-+
-+	WAPI_TRACE(WAPI_INIT, "===========>%s\n", __FUNCTION__);
-+
-+	/* Enable Wapi */
-+	WAPI_TRACE(WAPI_INIT, "%s: Enable wapi!!!!\n", __FUNCTION__);
-+	padapter->wapiInfo.bWapiEnable = true;
-+	padapter->pairwise_key_type = KEY_TYPE_SMS4;
-+	ieee->group_key_type = KEY_TYPE_SMS4;
-+	padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN;
-+	padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN;
-+
-+	/* set usk */
-+	WAPI_TRACE(WAPI_INIT, "%s: Set USK!!!!\n", __FUNCTION__);
-+	memset(keybuf, 0, 100);
-+	keybuf[0] = 1;                           /* set usk */
-+	keybuf[1] = 1; 				/* enable tx */
-+	keybuf[2] = 1; 				/* AE */
-+	keybuf[3] = 0; 				/* not update */
-+
-+	memcpy(keybuf + 4, mac_addr, ETH_ALEN);
-+	memcpy(keybuf + 10, UskDataKey, 16);
-+	memcpy(keybuf + 26, UskMicKey, 16);
-+	keybuf[42] = UskId;
-+	wapi_test_set_key(padapter, keybuf);
-+
-+	memset(keybuf, 0, 100);
-+	keybuf[0] = 1;                           /* set usk */
-+	keybuf[1] = 1; 				/* enable tx */
-+	keybuf[2] = 0; 				/* AE */
-+	keybuf[3] = 0; 				/* not update */
-+
-+	memcpy(keybuf + 4, mac_addr, ETH_ALEN);
-+	memcpy(keybuf + 10, UskDataKey, 16);
-+	memcpy(keybuf + 26, UskMicKey, 16);
-+	keybuf[42] = UskId;
-+	wapi_test_set_key(padapter, keybuf);
-+
-+	/* set msk */
-+	WAPI_TRACE(WAPI_INIT, "%s: Set MSK!!!!\n", __FUNCTION__);
-+	memset(keybuf, 0, 100);
-+	keybuf[0] = 2;                                /* set msk */
-+	keybuf[1] = 1;                               /* Enable TX */
-+	keybuf[2] = 1; 				/* AE */
-+	keybuf[3] = 0;                              /* not update */
-+	memcpy(keybuf + 4, mac_addr, ETH_ALEN);
-+	memcpy(keybuf + 10, MskDataKey, 16);
-+	memcpy(keybuf + 26, MskMicKey, 16);
-+	keybuf[42] = MskId;
-+	wapi_test_set_key(padapter, keybuf);
-+
-+	memset(keybuf, 0, 100);
-+	keybuf[0] = 2;                                /* set msk */
-+	keybuf[1] = 1;                               /* Enable TX */
-+	keybuf[2] = 0; 				/* AE */
-+	keybuf[3] = 0;                              /* not update */
-+	memcpy(keybuf + 4, mac_addr, ETH_ALEN);
-+	memcpy(keybuf + 10, MskDataKey, 16);
-+	memcpy(keybuf + 26, MskMicKey, 16);
-+	keybuf[42] = MskId;
-+	wapi_test_set_key(padapter, keybuf);
-+	WAPI_TRACE(WAPI_INIT, "<===========%s\n", __FUNCTION__);
-+}
-+#endif
-+
-+void rtw_wapi_get_iv(_adapter *padapter, u8 *pRA, u8 *IV)
-+{
-+	PWLAN_HEADER_WAPI_EXTENSION pWapiExt = NULL;
-+	PRT_WAPI_T         pWapiInfo = &padapter->wapiInfo;
-+	bool	bPNOverflow = false;
-+	bool	bFindMatchPeer = false;
-+	PRT_WAPI_STA_INFO  pWapiSta = NULL;
-+
-+	pWapiExt = (PWLAN_HEADER_WAPI_EXTENSION)IV;
-+
-+	WAPI_DATA(WAPI_RX, "wapi_get_iv: pra", pRA, 6);
-+
-+	if (IS_MCAST(pRA)) {
-+		if (!pWapiInfo->wapiTxMsk.bTxEnable) {
-+			WAPI_TRACE(WAPI_ERR, "%s: bTxEnable = 0!!\n", __FUNCTION__);
-+			return;
-+		}
-+
-+		if (pWapiInfo->wapiTxMsk.keyId <= 1) {
-+			pWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId;
-+			pWapiExt->Reserved = 0;
-+			bPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1);
-+			memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16);
-+		}
-+	} else {
-+		if (list_empty(&pWapiInfo->wapiSTAUsedList)) {
-+			WAPI_TRACE(WAPI_RX, "rtw_wapi_get_iv: list is empty\n");
-+			_rtw_memset(IV, 10, 18);
-+			return;
-+		} else {
-+			list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
-+				WAPI_DATA(WAPI_RX, "rtw_wapi_get_iv: peermacaddr ", pWapiSta->PeerMacAddr, 6);
-+				if (_rtw_memcmp((u8 *)pWapiSta->PeerMacAddr, pRA, 6) == _TRUE) {
-+					bFindMatchPeer = true;
-+					break;
-+				}
-+			}
-+
-+			WAPI_TRACE(WAPI_RX, "bFindMatchPeer: %d\n", bFindMatchPeer);
-+			WAPI_DATA(WAPI_RX, "Addr", pRA, 6);
-+
-+			if (bFindMatchPeer) {
-+				if ((!pWapiSta->wapiUskUpdate.bTxEnable) && (!pWapiSta->wapiUsk.bTxEnable))
-+					return;
-+
-+				if (pWapiSta->wapiUsk.keyId <= 1) {
-+					if (pWapiSta->wapiUskUpdate.bTxEnable)
-+						pWapiExt->KeyIdx = pWapiSta->wapiUskUpdate.keyId;
-+					else
-+						pWapiExt->KeyIdx = pWapiSta->wapiUsk.keyId;
-+
-+					pWapiExt->Reserved = 0;
-+					bPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2);
-+					_rtw_memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16);
-+
-+				}
-+			}
-+		}
-+
-+	}
-+
-+}
-+
-+bool rtw_wapi_drop_for_key_absent(_adapter *padapter, u8 *pRA)
-+{
-+	PRT_WAPI_T         pWapiInfo = &padapter->wapiInfo;
-+	bool				bFindMatchPeer = false;
-+	bool				bDrop = false;
-+	PRT_WAPI_STA_INFO  pWapiSta = NULL;
-+	struct security_priv		*psecuritypriv = &padapter->securitypriv;
-+
-+	WAPI_DATA(WAPI_RX, "rtw_wapi_drop_for_key_absent: ra ", pRA, 6);
-+
-+	if (psecuritypriv->dot11PrivacyAlgrthm == _SMS4_) {
-+		if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable))
-+			return true;
-+
-+		if (IS_MCAST(pRA)) {
-+			if (!pWapiInfo->wapiTxMsk.bTxEnable) {
-+				bDrop = true;
-+				WAPI_TRACE(WAPI_RX, "rtw_wapi_drop_for_key_absent: multicast key is absent\n");
-+				return bDrop;
-+			}
-+		} else {
-+			if (!list_empty(&pWapiInfo->wapiSTAUsedList)) {
-+				list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
-+					WAPI_DATA(WAPI_RX, "rtw_wapi_drop_for_key_absent: pWapiSta->PeerMacAddr ", pWapiSta->PeerMacAddr, 6);
-+					if (_rtw_memcmp(pRA, pWapiSta->PeerMacAddr, 6) == _TRUE) {
-+						bFindMatchPeer = true;
-+						break;
-+					}
-+				}
-+				if (bFindMatchPeer)	{
-+					if (!pWapiSta->wapiUsk.bTxEnable) {
-+						bDrop = true;
-+						WAPI_TRACE(WAPI_RX, "rtw_wapi_drop_for_key_absent: unicast key is absent\n");
-+						return bDrop;
-+					}
-+				} else {
-+					bDrop = true;
-+					WAPI_TRACE(WAPI_RX, "rtw_wapi_drop_for_key_absent: no peer find\n");
-+					return bDrop;
-+				}
-+
-+			} else {
-+				bDrop = true;
-+				WAPI_TRACE(WAPI_RX, "rtw_wapi_drop_for_key_absent: no sta  exist\n");
-+				return bDrop;
-+			}
-+		}
-+	} else
-+		return bDrop;
-+
-+	return bDrop;
-+}
-+
-+void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param)
-+{
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	PRT_WAPI_T			pWapiInfo = &padapter->wapiInfo;
-+	PRT_WAPI_STA_INFO	pWapiSta;
-+	u8					WapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
-+	u8					WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
-+	u8					WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
-+
-+	if (param->u.crypt.set_tx == 1) {
-+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
-+			if (_rtw_memcmp(pWapiSta->PeerMacAddr, param->sta_addr, 6)) {
-+				_rtw_memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16);
-+
-+				pWapiSta->wapiUsk.bSet = true;
-+				_rtw_memcpy(pWapiSta->wapiUsk.dataKey, param->u.crypt.key, 16);
-+				_rtw_memcpy(pWapiSta->wapiUsk.micKey, param->u.crypt.key + 16, 16);
-+				pWapiSta->wapiUsk.keyId = param->u.crypt.idx ;
-+				pWapiSta->wapiUsk.bTxEnable = true;
-+
-+				_rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16);
-+				_rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16);
-+				_rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16);
-+				_rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16);
-+				_rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16);
-+				pWapiSta->wapiUskUpdate.bTxEnable = false;
-+				pWapiSta->wapiUskUpdate.bSet = false;
-+
-+				if (psecuritypriv->sw_encrypt == false || psecuritypriv->sw_decrypt == false) {
-+					/* set unicast key for ASUE */
-+					rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false);
-+				}
-+			}
-+		}
-+	} else {
-+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
-+			if (_rtw_memcmp(pWapiSta->PeerMacAddr, get_bssid(pmlmepriv), 6)) {
-+				pWapiSta->wapiMsk.bSet = true;
-+				_rtw_memcpy(pWapiSta->wapiMsk.dataKey, param->u.crypt.key, 16);
-+				_rtw_memcpy(pWapiSta->wapiMsk.micKey, param->u.crypt.key + 16, 16);
-+				pWapiSta->wapiMsk.keyId = param->u.crypt.idx ;
-+				pWapiSta->wapiMsk.bTxEnable = false;
-+				if (!pWapiSta->bSetkeyOk)
-+					pWapiSta->bSetkeyOk = true;
-+				pWapiSta->bAuthenticateInProgress = false;
-+
-+				_rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16);
-+
-+				if (psecuritypriv->sw_decrypt == false) {
-+					/* set rx broadcast key for ASUE */
-+					rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false);
-+				}
-+			}
-+		}
-+	}
-+}
-+#endif
-diff --git a/drivers/staging/rtl8723cs/core/rtw_wapi_sms4.c b/drivers/staging/rtl8723cs/core/rtw_wapi_sms4.c
-new file mode 100644
-index 000000000000..4b7cf957c8f2
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_wapi_sms4.c
-@@ -0,0 +1,922 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifdef CONFIG_WAPI_SUPPORT
-+
-+#include <linux/unistd.h>
-+#include <linux/etherdevice.h>
-+#include <drv_types.h>
-+#include <rtw_wapi.h>
-+
-+
-+#ifdef CONFIG_WAPI_SW_SMS4
-+
-+#define WAPI_LITTLE_ENDIAN
-+/* #define BIG_ENDIAN */
-+#define ENCRYPT  0
-+#define DECRYPT  1
-+
-+
-+/**********************************************************
-+ **********************************************************/
-+const u8 Sbox[256] = {
-+	0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7, 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
-+	0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3, 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
-+	0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a, 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
-+	0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95, 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
-+	0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba, 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
-+	0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b, 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
-+	0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2, 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
-+	0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52, 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
-+	0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5, 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
-+	0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55, 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
-+	0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60, 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
-+	0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f, 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
-+	0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f, 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
-+	0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd, 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
-+	0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e, 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
-+	0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20, 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48
-+};
-+
-+const u32 CK[32] = {
-+	0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269,
-+	0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9,
-+	0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249,
-+	0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9,
-+	0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229,
-+	0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299,
-+	0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209,
-+	0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279
-+};
-+
-+#define Rotl(_x, _y) (((_x) << (_y)) | ((_x) >> (32 - (_y))))
-+
-+#define ByteSub(_A) (Sbox[(_A) >> 24 & 0xFF] << 24 | \
-+		     Sbox[(_A) >> 16 & 0xFF] << 16 | \
-+		     Sbox[(_A) >>  8 & 0xFF] <<  8 | \
-+		     Sbox[(_A) & 0xFF])
-+
-+#define L1(_B) ((_B) ^ Rotl(_B, 2) ^ Rotl(_B, 10) ^ Rotl(_B, 18) ^ Rotl(_B, 24))
-+#define L2(_B) ((_B) ^ Rotl(_B, 13) ^ Rotl(_B, 23))
-+
-+static void
-+xor_block(void *dst, void *src1, void *src2)
-+/* 128-bit xor: *dst = *src1 xor *src2. Pointers must be 32-bit aligned */
-+{
-+	((u32 *)dst)[0] = ((u32 *)src1)[0] ^ ((u32 *)src2)[0];
-+	((u32 *)dst)[1] = ((u32 *)src1)[1] ^ ((u32 *)src2)[1];
-+	((u32 *)dst)[2] = ((u32 *)src1)[2] ^ ((u32 *)src2)[2];
-+	((u32 *)dst)[3] = ((u32 *)src1)[3] ^ ((u32 *)src2)[3];
-+}
-+
-+
-+void SMS4Crypt(u8 *Input, u8 *Output, u32 *rk)
-+{
-+	u32 r, mid, x0, x1, x2, x3, *p;
-+	p = (u32 *)Input;
-+	x0 = p[0];
-+	x1 = p[1];
-+	x2 = p[2];
-+	x3 = p[3];
-+#ifdef WAPI_LITTLE_ENDIAN
-+	x0 = Rotl(x0, 16);
-+	x0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
-+	x1 = Rotl(x1, 16);
-+	x1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
-+	x2 = Rotl(x2, 16);
-+	x2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
-+	x3 = Rotl(x3, 16);
-+	x3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
-+#endif
-+	for (r = 0; r < 32; r += 4) {
-+		mid = x1 ^ x2 ^ x3 ^ rk[r + 0];
-+		mid = ByteSub(mid);
-+		x0 ^= L1(mid);
-+		mid = x2 ^ x3 ^ x0 ^ rk[r + 1];
-+		mid = ByteSub(mid);
-+		x1 ^= L1(mid);
-+		mid = x3 ^ x0 ^ x1 ^ rk[r + 2];
-+		mid = ByteSub(mid);
-+		x2 ^= L1(mid);
-+		mid = x0 ^ x1 ^ x2 ^ rk[r + 3];
-+		mid = ByteSub(mid);
-+		x3 ^= L1(mid);
-+	}
-+#ifdef WAPI_LITTLE_ENDIAN
-+	x0 = Rotl(x0, 16);
-+	x0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
-+	x1 = Rotl(x1, 16);
-+	x1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
-+	x2 = Rotl(x2, 16);
-+	x2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
-+	x3 = Rotl(x3, 16);
-+	x3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
-+#endif
-+	p = (u32 *)Output;
-+	p[0] = x3;
-+	p[1] = x2;
-+	p[2] = x1;
-+	p[3] = x0;
-+}
-+
-+
-+
-+void SMS4KeyExt(u8 *Key, u32 *rk, u32 CryptFlag)
-+{
-+	u32 r, mid, x0, x1, x2, x3, *p;
-+
-+	p = (u32 *)Key;
-+	x0 = p[0];
-+	x1 = p[1];
-+	x2 = p[2];
-+	x3 = p[3];
-+#ifdef WAPI_LITTLE_ENDIAN
-+	x0 = Rotl(x0, 16);
-+	x0 = ((x0 & 0xFF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8);
-+	x1 = Rotl(x1, 16);
-+	x1 = ((x1 & 0xFF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8);
-+	x2 = Rotl(x2, 16);
-+	x2 = ((x2 & 0xFF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8);
-+	x3 = Rotl(x3, 16);
-+	x3 = ((x3 & 0xFF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8);
-+#endif
-+
-+	x0 ^= 0xa3b1bac6;
-+	x1 ^= 0x56aa3350;
-+	x2 ^= 0x677d9197;
-+	x3 ^= 0xb27022dc;
-+	for (r = 0; r < 32; r += 4) {
-+		mid = x1 ^ x2 ^ x3 ^ CK[r + 0];
-+		mid = ByteSub(mid);
-+		rk[r + 0] = x0 ^= L2(mid);
-+		mid = x2 ^ x3 ^ x0 ^ CK[r + 1];
-+		mid = ByteSub(mid);
-+		rk[r + 1] = x1 ^= L2(mid);
-+		mid = x3 ^ x0 ^ x1 ^ CK[r + 2];
-+		mid = ByteSub(mid);
-+		rk[r + 2] = x2 ^= L2(mid);
-+		mid = x0 ^ x1 ^ x2 ^ CK[r + 3];
-+		mid = ByteSub(mid);
-+		rk[r + 3] = x3 ^= L2(mid);
-+	}
-+	if (CryptFlag == DECRYPT) {
-+		for (r = 0; r < 16; r++)
-+			mid = rk[r], rk[r] = rk[31 - r], rk[31 - r] = mid;
-+	}
-+}
-+
-+
-+void WapiSMS4Cryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
-+		      u8 *Output, u16 *OutputLength, u32 CryptFlag)
-+{
-+	u32 blockNum, i, j, rk[32];
-+	u16 remainder;
-+	u8 blockIn[16], blockOut[16], tempIV[16], k;
-+
-+	*OutputLength = 0;
-+	remainder = InputLength & 0x0F;
-+	blockNum = InputLength >> 4;
-+	if (remainder != 0)
-+		blockNum++;
-+	else
-+		remainder = 16;
-+
-+	for (k = 0; k < 16; k++)
-+		tempIV[k] = IV[15 - k];
-+
-+	memcpy(blockIn, tempIV, 16);
-+
-+	SMS4KeyExt((u8 *)Key, rk, CryptFlag);
-+
-+	for (i = 0; i < blockNum - 1; i++) {
-+		SMS4Crypt((u8 *)blockIn, blockOut, rk);
-+		xor_block(&Output[i * 16], &Input[i * 16], blockOut);
-+		memcpy(blockIn, blockOut, 16);
-+	}
-+
-+	*OutputLength = i * 16;
-+
-+	SMS4Crypt((u8 *)blockIn, blockOut, rk);
-+
-+	for (j = 0; j < remainder; j++)
-+		Output[i * 16 + j] = Input[i * 16 + j] ^ blockOut[j];
-+	*OutputLength += remainder;
-+
-+}
-+
-+void WapiSMS4Encryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
-+			u8 *Output, u16 *OutputLength)
-+{
-+
-+	WapiSMS4Cryption(Key, IV, Input, InputLength, Output, OutputLength, ENCRYPT);
-+}
-+
-+void WapiSMS4Decryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength,
-+			u8 *Output, u16 *OutputLength)
-+{
-+	/* OFB mode: is also ENCRYPT flag */
-+	WapiSMS4Cryption(Key, IV, Input, InputLength, Output, OutputLength, ENCRYPT);
-+}
-+
-+void WapiSMS4CalculateMic(u8 *Key, u8 *IV, u8 *Input1, u8 Input1Length,
-+		  u8 *Input2, u16 Input2Length, u8 *Output, u8 *OutputLength)
-+{
-+	u32 blockNum, i, remainder, rk[32];
-+	u8 BlockIn[16], BlockOut[16], TempBlock[16], tempIV[16], k;
-+
-+	*OutputLength = 0;
-+	remainder = Input1Length & 0x0F;
-+	blockNum = Input1Length >> 4;
-+
-+	for (k = 0; k < 16; k++)
-+		tempIV[k] = IV[15 - k];
-+
-+	memcpy(BlockIn, tempIV, 16);
-+
-+	SMS4KeyExt((u8 *)Key, rk, ENCRYPT);
-+
-+	SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
-+
-+	for (i = 0; i < blockNum; i++) {
-+		xor_block(BlockIn, (Input1 + i * 16), BlockOut);
-+		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
-+	}
-+
-+	if (remainder != 0) {
-+		memset(TempBlock, 0, 16);
-+		memcpy(TempBlock, (Input1 + blockNum * 16), remainder);
-+
-+		xor_block(BlockIn, TempBlock, BlockOut);
-+		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
-+	}
-+
-+	remainder = Input2Length & 0x0F;
-+	blockNum = Input2Length >> 4;
-+
-+	for (i = 0; i < blockNum; i++) {
-+		xor_block(BlockIn, (Input2 + i * 16), BlockOut);
-+		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
-+	}
-+
-+	if (remainder != 0) {
-+		memset(TempBlock, 0, 16);
-+		memcpy(TempBlock, (Input2 + blockNum * 16), remainder);
-+
-+		xor_block(BlockIn, TempBlock, BlockOut);
-+		SMS4Crypt((u8 *)BlockIn, BlockOut, rk);
-+	}
-+
-+	memcpy(Output, BlockOut, 16);
-+	*OutputLength = 16;
-+}
-+
-+void SecCalculateMicSMS4(
-+	u8		KeyIdx,
-+	u8        *MicKey,
-+	u8        *pHeader,
-+	u8        *pData,
-+	u16       DataLen,
-+	u8        *MicBuffer
-+)
-+{
-+#if 0
-+	struct ieee80211_hdr_3addr_qos *header;
-+	u8 TempBuf[34], TempLen = 32, MicLen, QosOffset, *IV;
-+	u16 *pTemp, fc;
-+
-+	WAPI_TRACE(WAPI_TX | WAPI_RX, "=========>%s\n", __FUNCTION__);
-+
-+	header = (struct ieee80211_hdr_3addr_qos *)pHeader;
-+	memset(TempBuf, 0, 34);
-+	memcpy(TempBuf, pHeader, 2); /* FrameCtrl */
-+	pTemp = (u16 *)TempBuf;
-+	*pTemp &= 0xc78f;       /* bit4,5,6,11,12,13 */
-+
-+	memcpy((TempBuf + 2), (pHeader + 4), 12); /* Addr1, Addr2 */
-+	memcpy((TempBuf + 14), (pHeader + 22), 2); /* SeqCtrl */
-+	pTemp = (u16 *)(TempBuf + 14);
-+	*pTemp &= 0x000f;
-+
-+	memcpy((TempBuf + 16), (pHeader + 16), 6); /* Addr3 */
-+
-+	fc = le16_to_cpu(header->frame_ctl);
-+
-+
-+
-+	if (GetFrDs((u16 *)&fc) && GetToDs((u16 *)&fc)) {
-+		memcpy((TempBuf + 22), (pHeader + 24), 6);
-+		QosOffset = 30;
-+	} else {
-+		memset((TempBuf + 22), 0, 6);
-+		QosOffset = 24;
-+	}
-+
-+	if ((fc & 0x0088) == 0x0088) {
-+		memcpy((TempBuf + 28), (pHeader + QosOffset), 2);
-+		TempLen += 2;
-+		/* IV = pHeader + QosOffset + 2 + SNAP_SIZE + sizeof(u16) + 2; */
-+		IV = pHeader + QosOffset + 2 + 2;
-+	} else {
-+		IV = pHeader + QosOffset + 2;
-+		/* IV = pHeader + QosOffset + SNAP_SIZE + sizeof(u16) + 2; */
-+	}
-+
-+	TempBuf[TempLen - 1] = (u8)(DataLen & 0xff);
-+	TempBuf[TempLen - 2] = (u8)((DataLen & 0xff00) >> 8);
-+	TempBuf[TempLen - 4] = KeyIdx;
-+
-+	WAPI_DATA(WAPI_TX, "CalculateMic - KEY", MicKey, 16);
-+	WAPI_DATA(WAPI_TX, "CalculateMic - IV", IV, 16);
-+	WAPI_DATA(WAPI_TX, "CalculateMic - TempBuf", TempBuf, TempLen);
-+	WAPI_DATA(WAPI_TX, "CalculateMic - pData", pData, DataLen);
-+
-+	WapiSMS4CalculateMic(MicKey, IV, TempBuf, TempLen,
-+			     pData, DataLen, MicBuffer, &MicLen);
-+
-+	if (MicLen != 16)
-+		WAPI_TRACE(WAPI_ERR, "%s: MIC Length Error!!\n", __FUNCTION__);
-+
-+	WAPI_TRACE(WAPI_TX | WAPI_RX, "<=========%s\n", __FUNCTION__);
-+#endif
-+}
-+
-+/* AddCount: 1 or 2.
-+ *  If overflow, return 1,
-+ *  else return 0.
-+ */
-+u8 WapiIncreasePN(u8 *PN, u8 AddCount)
-+{
-+	u8  i;
-+
-+	if (NULL == PN)
-+		return 1;
-+	/* YJ,test,091102 */
-+	/*
-+	if(AddCount == 2){
-+		RTW_INFO("############################%s(): PN[0]=0x%x\n", __FUNCTION__, PN[0]);
-+		if(PN[0] == 0x48){
-+			PN[0] += AddCount;
-+			return 1;
-+		}else{
-+			PN[0] += AddCount;
-+			return 0;
-+		}
-+	}
-+	*/
-+	/* YJ,test,091102,end */
-+
-+	for (i = 0; i < 16; i++) {
-+		if (PN[i] + AddCount <= 0xff) {
-+			PN[i] += AddCount;
-+			return 0;
-+		} else {
-+			PN[i] += AddCount;
-+			AddCount = 1;
-+		}
-+	}
-+	return 1;
-+}
-+
-+
-+void WapiGetLastRxUnicastPNForQoSData(
-+	u8			UserPriority,
-+	PRT_WAPI_STA_INFO    pWapiStaInfo,
-+	u8 *PNOut
-+)
-+{
-+	WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
-+	switch (UserPriority) {
-+	case 0:
-+	case 3:
-+		memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNBEQueue, 16);
-+		break;
-+	case 1:
-+	case 2:
-+		memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNBKQueue, 16);
-+		break;
-+	case 4:
-+	case 5:
-+		memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNVIQueue, 16);
-+		break;
-+	case 6:
-+	case 7:
-+		memcpy(PNOut, pWapiStaInfo->lastRxUnicastPNVOQueue, 16);
-+		break;
-+	default:
-+		WAPI_TRACE(WAPI_ERR, "%s: Unknown TID\n", __FUNCTION__);
-+		break;
-+	}
-+	WAPI_TRACE(WAPI_RX, "<=========== %s\n", __FUNCTION__);
-+}
-+
-+
-+void WapiSetLastRxUnicastPNForQoSData(
-+	u8		UserPriority,
-+	u8           *PNIn,
-+	PRT_WAPI_STA_INFO    pWapiStaInfo
-+)
-+{
-+	WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
-+	switch (UserPriority) {
-+	case 0:
-+	case 3:
-+		memcpy(pWapiStaInfo->lastRxUnicastPNBEQueue, PNIn, 16);
-+		break;
-+	case 1:
-+	case 2:
-+		memcpy(pWapiStaInfo->lastRxUnicastPNBKQueue, PNIn, 16);
-+		break;
-+	case 4:
-+	case 5:
-+		memcpy(pWapiStaInfo->lastRxUnicastPNVIQueue, PNIn, 16);
-+		break;
-+	case 6:
-+	case 7:
-+		memcpy(pWapiStaInfo->lastRxUnicastPNVOQueue, PNIn, 16);
-+		break;
-+	default:
-+		WAPI_TRACE(WAPI_ERR, "%s: Unknown TID\n", __FUNCTION__);
-+		break;
-+	}
-+	WAPI_TRACE(WAPI_RX, "<=========== %s\n", __FUNCTION__);
-+}
-+
-+
-+/****************************************************************************
-+ FALSE not RX-Reorder
-+ TRUE do RX Reorder
-+add to support WAPI to N-mode
-+*****************************************************************************/
-+u8 WapiCheckPnInSwDecrypt(
-+	_adapter *padapter,
-+	struct sk_buff *pskb
-+)
-+{
-+	u8				ret = false;
-+
-+#if 0
-+	struct ieee80211_hdr_3addr_qos *header;
-+	u16				fc;
-+	u8				*pDaddr, *pTaddr, *pRaddr;
-+
-+	header = (struct ieee80211_hdr_3addr_qos *)pskb->data;
-+	pTaddr = header->addr2;
-+	pRaddr = header->addr1;
-+	fc = le16_to_cpu(header->frame_ctl);
-+
-+	if (GetToDs(&fc))
-+		pDaddr = header->addr3;
-+	else
-+		pDaddr = header->addr1;
-+
-+	if ((_rtw_memcmp(pRaddr, padapter->pnetdev->dev_addr, ETH_ALEN) == 0)
-+	    &&	!(pDaddr)
-+	    && (GetFrameType(&fc) == WIFI_QOS_DATA_TYPE))
-+		/* && ieee->pHTInfo->bCurrentHTSupport && */
-+		/* ieee->pHTInfo->bCurRxReorderEnable) */
-+		ret = false;
-+	else
-+		ret = true;
-+#endif
-+	WAPI_TRACE(WAPI_RX, "%s: return %d\n", __FUNCTION__, ret);
-+	return ret;
-+}
-+
-+int SecSMS4HeaderFillIV(_adapter *padapter, u8 *pxmitframe)
-+{
-+	struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
-+	u8 *frame = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_OFFSET;
-+	u8 *pSecHeader = NULL, *pos = NULL, *pRA = NULL;
-+	u8 bPNOverflow = false, bFindMatchPeer = false, hdr_len = 0;
-+	PWLAN_HEADER_WAPI_EXTENSION pWapiExt = NULL;
-+	PRT_WAPI_T         pWapiInfo = &padapter->wapiInfo;
-+	PRT_WAPI_STA_INFO  pWapiSta = NULL;
-+	int ret = 0;
-+
-+	WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
-+
-+	return ret;
-+#if 0
-+	hdr_len = sMacHdrLng;
-+	if (GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE)
-+		hdr_len += 2;
-+	/* hdr_len += SNAP_SIZE + sizeof(u16); */
-+
-+	pos = skb_push(pskb, padapter->wapiInfo.extra_prefix_len);
-+	memmove(pos, pos + padapter->wapiInfo.extra_prefix_len, hdr_len);
-+
-+	pSecHeader = pskb->data + hdr_len;
-+	pWapiExt = (PWLAN_HEADER_WAPI_EXTENSION)pSecHeader;
-+	pRA = pskb->data + 4;
-+
-+	WAPI_DATA(WAPI_TX, "FillIV - Before Fill IV", pskb->data, pskb->len);
-+
-+	/* Address 1 is always receiver's address */
-+	if (IS_MCAST(pRA)) {
-+		if (!pWapiInfo->wapiTxMsk.bTxEnable) {
-+			WAPI_TRACE(WAPI_ERR, "%s: bTxEnable = 0!!\n", __FUNCTION__);
-+			return -2;
-+		}
-+		if (pWapiInfo->wapiTxMsk.keyId <= 1) {
-+			pWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId;
-+			pWapiExt->Reserved = 0;
-+			bPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1);
-+			memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16);
-+			if (bPNOverflow) {
-+				/* Update MSK Notification. */
-+				WAPI_TRACE(WAPI_ERR, "===============>%s():multicast PN overflow\n", __FUNCTION__);
-+				rtw_wapi_app_event_handler(padapter, NULL, 0, pRA, false, false, true, 0, false);
-+			}
-+		} else {
-+			WAPI_TRACE(WAPI_ERR, "%s: Invalid Wapi Multicast KeyIdx!!\n", __FUNCTION__);
-+			ret = -3;
-+		}
-+	} else {
-+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
-+			if (!memcmp(pWapiSta->PeerMacAddr, pRA, 6)) {
-+				bFindMatchPeer = true;
-+				break;
-+			}
-+		}
-+		if (bFindMatchPeer) {
-+			if ((!pWapiSta->wapiUskUpdate.bTxEnable) && (!pWapiSta->wapiUsk.bTxEnable)) {
-+				WAPI_TRACE(WAPI_ERR, "%s: bTxEnable = 0!!\n", __FUNCTION__);
-+				return -4;
-+			}
-+			if (pWapiSta->wapiUsk.keyId <= 1) {
-+				if (pWapiSta->wapiUskUpdate.bTxEnable)
-+					pWapiExt->KeyIdx = pWapiSta->wapiUskUpdate.keyId;
-+				else
-+					pWapiExt->KeyIdx = pWapiSta->wapiUsk.keyId;
-+
-+				pWapiExt->Reserved = 0;
-+				bPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2);
-+				memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16);
-+				if (bPNOverflow) {
-+					/* Update USK Notification. */
-+					WAPI_TRACE(WAPI_ERR, "===============>%s():unicast PN overflow\n", __FUNCTION__);
-+					rtw_wapi_app_event_handler(padapter, NULL, 0, pWapiSta->PeerMacAddr, false, true, false, 0, false);
-+				}
-+			} else {
-+				WAPI_TRACE(WAPI_ERR, "%s: Invalid Wapi Unicast KeyIdx!!\n", __FUNCTION__);
-+				ret = -5;
-+			}
-+		} else {
-+			WAPI_TRACE(WAPI_ERR, "%s: Can not find Peer Sta "MAC_FMT"!!\n", __FUNCTION__, MAC_ARG(pRA));
-+			ret = -6;
-+		}
-+	}
-+
-+	WAPI_DATA(WAPI_TX, "FillIV - After Fill IV", pskb->data, pskb->len);
-+	WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
-+	return ret;
-+#endif
-+}
-+
-+/* WAPI SW Enc: must have done Coalesce! */
-+void SecSWSMS4Encryption(
-+	_adapter *padapter,
-+	u8 *pxmitframe
-+)
-+{
-+	PRT_WAPI_T		pWapiInfo = &padapter->wapiInfo;
-+	PRT_WAPI_STA_INFO   pWapiSta = NULL;
-+	u8 *pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_SIZE;
-+	struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib;
-+
-+	u8 *SecPtr = NULL, *pRA, *pMicKey = NULL, *pDataKey = NULL, *pIV = NULL;
-+	u8 IVOffset, DataOffset, bFindMatchPeer = false, KeyIdx = 0, MicBuffer[16];
-+	u16 OutputLength;
-+
-+	WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
-+
-+	WAPI_TRACE(WAPI_TX, "hdrlen: %d\n", pattrib->hdrlen);
-+
-+	return;
-+
-+	DataOffset = pattrib->hdrlen + pattrib->iv_len;
-+
-+	pRA = pframe + 4;
-+
-+
-+	if (IS_MCAST(pRA)) {
-+		KeyIdx = pWapiInfo->wapiTxMsk.keyId;
-+		pIV = pWapiInfo->lastTxMulticastPN;
-+		pMicKey = pWapiInfo->wapiTxMsk.micKey;
-+		pDataKey = pWapiInfo->wapiTxMsk.dataKey;
-+	} else {
-+		if (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {
-+			list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
-+				if (0 == memcmp(pWapiSta->PeerMacAddr, pRA, 6)) {
-+					bFindMatchPeer = true;
-+					break;
-+				}
-+			}
-+
-+			if (bFindMatchPeer) {
-+				if (pWapiSta->wapiUskUpdate.bTxEnable) {
-+					KeyIdx = pWapiSta->wapiUskUpdate.keyId;
-+					WAPI_TRACE(WAPI_TX, "%s(): Use update USK!! KeyIdx=%d\n", __FUNCTION__, KeyIdx);
-+					pIV = pWapiSta->lastTxUnicastPN;
-+					pMicKey = pWapiSta->wapiUskUpdate.micKey;
-+					pDataKey = pWapiSta->wapiUskUpdate.dataKey;
-+				} else {
-+					KeyIdx = pWapiSta->wapiUsk.keyId;
-+					WAPI_TRACE(WAPI_TX, "%s(): Use USK!! KeyIdx=%d\n", __FUNCTION__, KeyIdx);
-+					pIV = pWapiSta->lastTxUnicastPN;
-+					pMicKey = pWapiSta->wapiUsk.micKey;
-+					pDataKey = pWapiSta->wapiUsk.dataKey;
-+				}
-+			} else {
-+				WAPI_TRACE(WAPI_ERR, "%s: Can not find Peer Sta!!\n", __FUNCTION__);
-+				return;
-+			}
-+		} else {
-+			WAPI_TRACE(WAPI_ERR, "%s: wapiSTAUsedList is empty!!\n", __FUNCTION__);
-+			return;
-+		}
-+	}
-+
-+	SecPtr = pframe;
-+	SecCalculateMicSMS4(KeyIdx, pMicKey, SecPtr, (SecPtr + DataOffset), pattrib->pktlen, MicBuffer);
-+
-+	WAPI_DATA(WAPI_TX, "Encryption - MIC", MicBuffer, padapter->wapiInfo.extra_postfix_len);
-+
-+	memcpy(pframe + pattrib->hdrlen + pattrib->iv_len + pattrib->pktlen - pattrib->icv_len,
-+	       (u8 *)MicBuffer,
-+	       padapter->wapiInfo.extra_postfix_len
-+	      );
-+
-+
-+	WapiSMS4Encryption(pDataKey, pIV, (SecPtr + DataOffset), pattrib->pktlen + pattrib->icv_len, (SecPtr + DataOffset), &OutputLength);
-+
-+	WAPI_DATA(WAPI_TX, "Encryption - After SMS4 encryption", pframe, pattrib->hdrlen + pattrib->iv_len + pattrib->pktlen);
-+
-+	WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
-+}
-+
-+u8 SecSWSMS4Decryption(
-+	_adapter *padapter,
-+	u8		*precv_frame,
-+	struct recv_priv *precv_priv
-+)
-+{
-+	PRT_WAPI_T pWapiInfo = &padapter->wapiInfo;
-+	struct recv_frame_hdr *precv_hdr;
-+	PRT_WAPI_STA_INFO   pWapiSta = NULL;
-+	u8 IVOffset, DataOffset, bFindMatchPeer = false, bUseUpdatedKey = false;
-+	u8 KeyIdx, MicBuffer[16], lastRxPNforQoS[16];
-+	u8 *pRA, *pTA, *pMicKey, *pDataKey, *pLastRxPN, *pRecvPN, *pSecData, *pRecvMic, *pos;
-+	u8 TID = 0;
-+	u16 OutputLength, DataLen;
-+	u8   bQosData;
-+	struct sk_buff	*pskb;
-+
-+	WAPI_TRACE(WAPI_RX, "=========>%s\n", __FUNCTION__);
-+
-+	return 0;
-+
-+	precv_hdr = &((union recv_frame *)precv_frame)->u.hdr;
-+	pskb = (struct sk_buff *)(precv_hdr->rx_data);
-+	precv_hdr->bWapiCheckPNInDecrypt = WapiCheckPnInSwDecrypt(padapter, pskb);
-+	WAPI_TRACE(WAPI_RX, "=========>%s: check PN  %d\n", __FUNCTION__, precv_hdr->bWapiCheckPNInDecrypt);
-+	WAPI_DATA(WAPI_RX, "Decryption - Before decryption", pskb->data, pskb->len);
-+
-+	IVOffset = sMacHdrLng;
-+	bQosData = GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE;
-+	if (bQosData)
-+		IVOffset += 2;
-+
-+	/* if(GetHTC()) */
-+	/*	IVOffset += 4; */
-+
-+	/* IVOffset += SNAP_SIZE + sizeof(u16); */
-+
-+	DataOffset = IVOffset + padapter->wapiInfo.extra_prefix_len;
-+
-+	pRA = pskb->data + 4;
-+	pTA = pskb->data + 10;
-+	KeyIdx = *(pskb->data + IVOffset);
-+	pRecvPN = pskb->data + IVOffset + 2;
-+	pSecData = pskb->data + DataOffset;
-+	DataLen = pskb->len - DataOffset;
-+	pRecvMic = pskb->data + pskb->len - padapter->wapiInfo.extra_postfix_len;
-+	TID = GetTid(pskb->data);
-+
-+	if (!list_empty(&(pWapiInfo->wapiSTAUsedList))) {
-+		list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
-+			if (0 == memcmp(pWapiSta->PeerMacAddr, pTA, 6)) {
-+				bFindMatchPeer = true;
-+				break;
-+			}
-+		}
-+	}
-+
-+	if (!bFindMatchPeer) {
-+		WAPI_TRACE(WAPI_ERR, "%s: Can not find Peer Sta "MAC_FMT" for Key Info!!!\n", __FUNCTION__, MAC_ARG(pTA));
-+		return false;
-+	}
-+
-+	if (IS_MCAST(pRA)) {
-+		WAPI_TRACE(WAPI_RX, "%s: Multicast decryption !!!\n", __FUNCTION__);
-+		if (pWapiSta->wapiMsk.keyId == KeyIdx && pWapiSta->wapiMsk.bSet) {
-+			pLastRxPN = pWapiSta->lastRxMulticastPN;
-+			if (!WapiComparePN(pRecvPN, pLastRxPN)) {
-+				WAPI_TRACE(WAPI_ERR, "%s: MSK PN is not larger than last, Dropped!!!\n", __FUNCTION__);
-+				WAPI_DATA(WAPI_ERR, "pRecvPN:", pRecvPN, 16);
-+				WAPI_DATA(WAPI_ERR, "pLastRxPN:", pLastRxPN, 16);
-+				return false;
-+			}
-+
-+			memcpy(pLastRxPN, pRecvPN, 16);
-+			pMicKey = pWapiSta->wapiMsk.micKey;
-+			pDataKey = pWapiSta->wapiMsk.dataKey;
-+		} else if (pWapiSta->wapiMskUpdate.keyId == KeyIdx && pWapiSta->wapiMskUpdate.bSet) {
-+			WAPI_TRACE(WAPI_RX, "%s: Use Updated MSK for Decryption !!!\n", __FUNCTION__);
-+			bUseUpdatedKey = true;
-+			memcpy(pWapiSta->lastRxMulticastPN, pRecvPN, 16);
-+			pMicKey = pWapiSta->wapiMskUpdate.micKey;
-+			pDataKey = pWapiSta->wapiMskUpdate.dataKey;
-+		} else {
-+			WAPI_TRACE(WAPI_ERR, "%s: Can not find MSK with matched KeyIdx(%d), Dropped !!!\n", __FUNCTION__, KeyIdx);
-+			return false;
-+		}
-+	} else {
-+		WAPI_TRACE(WAPI_RX, "%s: Unicast decryption !!!\n", __FUNCTION__);
-+		if (pWapiSta->wapiUsk.keyId == KeyIdx && pWapiSta->wapiUsk.bSet) {
-+			WAPI_TRACE(WAPI_RX, "%s: Use USK for Decryption!!!\n", __FUNCTION__);
-+			if (precv_hdr->bWapiCheckPNInDecrypt) {
-+				if (GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE) {
-+					WapiGetLastRxUnicastPNForQoSData(TID, pWapiSta, lastRxPNforQoS);
-+					pLastRxPN = lastRxPNforQoS;
-+				} else
-+					pLastRxPN = pWapiSta->lastRxUnicastPN;
-+				if (!WapiComparePN(pRecvPN, pLastRxPN))
-+					return false;
-+				if (bQosData)
-+					WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta);
-+				else
-+					memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16);
-+			} else
-+				memcpy(precv_hdr->WapiTempPN, pRecvPN, 16);
-+
-+			if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE)) {
-+				if ((pRecvPN[0] & 0x1) == 0) {
-+					WAPI_TRACE(WAPI_ERR, "%s: Rx USK PN is not odd when Infra STA mode, Dropped !!!\n", __FUNCTION__);
-+					return false;
-+				}
-+			}
-+
-+			pMicKey = pWapiSta->wapiUsk.micKey;
-+			pDataKey = pWapiSta->wapiUsk.dataKey;
-+		} else if (pWapiSta->wapiUskUpdate.keyId == KeyIdx && pWapiSta->wapiUskUpdate.bSet) {
-+			WAPI_TRACE(WAPI_RX, "%s: Use Updated USK for Decryption!!!\n", __FUNCTION__);
-+			if (pWapiSta->bAuthenticatorInUpdata)
-+				bUseUpdatedKey = true;
-+			else
-+				bUseUpdatedKey = false;
-+
-+			if (bQosData)
-+				WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta);
-+			else
-+				memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16);
-+			pMicKey = pWapiSta->wapiUskUpdate.micKey;
-+			pDataKey = pWapiSta->wapiUskUpdate.dataKey;
-+		} else {
-+			WAPI_TRACE(WAPI_ERR, "%s: No valid USK!!!KeyIdx=%d pWapiSta->wapiUsk.keyId=%d pWapiSta->wapiUskUpdate.keyId=%d\n", __FUNCTION__, KeyIdx, pWapiSta->wapiUsk.keyId,
-+				   pWapiSta->wapiUskUpdate.keyId);
-+			/* dump_buf(pskb->data,pskb->len); */
-+			return false;
-+		}
-+	}
-+
-+	WAPI_DATA(WAPI_RX, "Decryption - DataKey", pDataKey, 16);
-+	WAPI_DATA(WAPI_RX, "Decryption - IV", pRecvPN, 16);
-+	WapiSMS4Decryption(pDataKey, pRecvPN, pSecData, DataLen, pSecData, &OutputLength);
-+
-+	if (OutputLength != DataLen)
-+		WAPI_TRACE(WAPI_ERR, "%s:  Output Length Error!!!!\n", __FUNCTION__);
-+
-+	WAPI_DATA(WAPI_RX, "Decryption - After decryption", pskb->data, pskb->len);
-+
-+	DataLen -= padapter->wapiInfo.extra_postfix_len;
-+
-+	SecCalculateMicSMS4(KeyIdx, pMicKey, pskb->data, pSecData, DataLen, MicBuffer);
-+
-+	WAPI_DATA(WAPI_RX, "Decryption - MIC received", pRecvMic, SMS4_MIC_LEN);
-+	WAPI_DATA(WAPI_RX, "Decryption - MIC calculated", MicBuffer, SMS4_MIC_LEN);
-+
-+	if (0 == memcmp(MicBuffer, pRecvMic, padapter->wapiInfo.extra_postfix_len)) {
-+		WAPI_TRACE(WAPI_RX, "%s: Check MIC OK!!\n", __FUNCTION__);
-+		if (bUseUpdatedKey) {
-+			/* delete the old key */
-+			if (IS_MCAST(pRA)) {
-+				WAPI_TRACE(WAPI_API, "%s(): AE use new update MSK!!\n", __FUNCTION__);
-+				pWapiSta->wapiMsk.keyId = pWapiSta->wapiMskUpdate.keyId;
-+				memcpy(pWapiSta->wapiMsk.dataKey, pWapiSta->wapiMskUpdate.dataKey, 16);
-+				memcpy(pWapiSta->wapiMsk.micKey, pWapiSta->wapiMskUpdate.micKey, 16);
-+				pWapiSta->wapiMskUpdate.bTxEnable = pWapiSta->wapiMskUpdate.bSet = false;
-+			} else {
-+				WAPI_TRACE(WAPI_API, "%s(): AE use new update USK!!\n", __FUNCTION__);
-+				pWapiSta->wapiUsk.keyId = pWapiSta->wapiUskUpdate.keyId;
-+				memcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16);
-+				memcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16);
-+				pWapiSta->wapiUskUpdate.bTxEnable = pWapiSta->wapiUskUpdate.bSet = false;
-+			}
-+		}
-+	} else {
-+		WAPI_TRACE(WAPI_ERR, "%s:  Check MIC Error, Dropped !!!!\n", __FUNCTION__);
-+		return false;
-+	}
-+
-+	pos = pskb->data;
-+	memmove(pos + padapter->wapiInfo.extra_prefix_len, pos, IVOffset);
-+	skb_pull(pskb, padapter->wapiInfo.extra_prefix_len);
-+
-+	WAPI_TRACE(WAPI_RX, "<=========%s\n", __FUNCTION__);
-+
-+	return true;
-+}
-+
-+u32	rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe)
-+{
-+
-+	u8	*pframe;
-+	u32 res = _SUCCESS;
-+
-+	WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__);
-+
-+	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
-+		WAPI_TRACE(WAPI_TX, "<========== %s, WAPI not supported or enabled!\n", __FUNCTION__);
-+		return _FAIL;
-+	}
-+
-+	if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
-+		return _FAIL;
-+
-+	pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_OFFSET;
-+
-+	SecSWSMS4Encryption(padapter, pxmitframe);
-+
-+	WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__);
-+	return res;
-+}
-+
-+u32	rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe)
-+{
-+	u8	*pframe;
-+	u32 res = _SUCCESS;
-+
-+	WAPI_TRACE(WAPI_RX, "=========>%s\n", __FUNCTION__);
-+
-+	if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) {
-+		WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or enabled!\n", __FUNCTION__);
-+		return _FAIL;
-+	}
-+
-+
-+	/* drop packet when hw decrypt fail
-+	* return tempraily */
-+	return _FAIL;
-+
-+	/* pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; */
-+
-+	if (false == SecSWSMS4Decryption(padapter, precvframe, &padapter->recvpriv)) {
-+		WAPI_TRACE(WAPI_ERR, "%s():SMS4 decrypt frame error\n", __FUNCTION__);
-+		return _FAIL;
-+	}
-+
-+	WAPI_TRACE(WAPI_RX, "<=========%s\n", __FUNCTION__);
-+	return res;
-+}
-+
-+#else
-+
-+u32	rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe)
-+{
-+	WAPI_TRACE(WAPI_TX, "=========>Dummy %s\n", __FUNCTION__);
-+	WAPI_TRACE(WAPI_TX, "<=========Dummy %s\n", __FUNCTION__);
-+	return _SUCCESS;
-+}
-+
-+u32	rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe)
-+{
-+	WAPI_TRACE(WAPI_RX, "=========>Dummy %s\n", __FUNCTION__);
-+	WAPI_TRACE(WAPI_RX, "<=========Dummy %s\n", __FUNCTION__);
-+	return _SUCCESS;
-+}
-+
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/core/rtw_wlan_util.c b/drivers/staging/rtl8723cs/core/rtw_wlan_util.c
-new file mode 100644
-index 000000000000..59e9c8680460
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_wlan_util.c
-@@ -0,0 +1,5662 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_WLAN_UTIL_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+	#include <linux/inetdevice.h>
-+	#define ETH_TYPE_OFFSET	12
-+	#define PROTOCOL_OFFSET	23
-+	#define IP_OFFSET	30
-+	#define IPv6_OFFSET	38
-+	#define IPv6_PROTOCOL_OFFSET	20
-+#endif
-+
-+unsigned char ARTHEROS_OUI1[] = {0x00, 0x03, 0x7f};
-+unsigned char ARTHEROS_OUI2[] = {0x00, 0x13, 0x74};
-+
-+unsigned char BROADCOM_OUI1[] = {0x00, 0x10, 0x18};
-+unsigned char BROADCOM_OUI2[] = {0x00, 0x0a, 0xf7};
-+unsigned char BROADCOM_OUI3[] = {0x00, 0x05, 0xb5};
-+
-+
-+unsigned char CISCO_OUI[] = {0x00, 0x40, 0x96};
-+unsigned char MARVELL_OUI[] = {0x00, 0x50, 0x43};
-+unsigned char RALINK_OUI[] = {0x00, 0x0c, 0x43};
-+unsigned char REALTEK_OUI[] = {0x00, 0xe0, 0x4c};
-+unsigned char AIRGOCAP_OUI[] = {0x00, 0x0a, 0xf5};
-+
-+unsigned char REALTEK_96B_IE[] = {0x00, 0xe0, 0x4c, 0x02, 0x01, 0x20};
-+
-+extern unsigned char RTW_WPA_OUI[];
-+extern unsigned char WPA_TKIP_CIPHER[4];
-+extern unsigned char RSN_TKIP_CIPHER[4];
-+
-+#define R2T_PHY_DELAY	(0)
-+
-+/* #define WAIT_FOR_BCN_TO_MIN	(3000) */
-+#define WAIT_FOR_BCN_TO_MIN	(6000)
-+#define WAIT_FOR_BCN_TO_MAX	(20000)
-+
-+static u8 rtw_basic_rate_cck[4] = {
-+	IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK,
-+	IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK
-+};
-+
-+static u8 rtw_basic_rate_ofdm[3] = {
-+	IEEE80211_OFDM_RATE_6MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB | IEEE80211_BASIC_RATE_MASK,
-+	IEEE80211_OFDM_RATE_24MB | IEEE80211_BASIC_RATE_MASK
-+};
-+
-+static u8 rtw_basic_rate_mix[7] = {
-+	IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK,
-+	IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK,
-+	IEEE80211_OFDM_RATE_6MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB | IEEE80211_BASIC_RATE_MASK,
-+	IEEE80211_OFDM_RATE_24MB | IEEE80211_BASIC_RATE_MASK
-+};
-+
-+extern u8	WIFI_CCKRATES[];
-+bool rtw_is_cck_rate(u8 rate)
-+{
-+	int i;
-+
-+	for (i = 0; i < 4; i++)
-+		if ((WIFI_CCKRATES[i] & 0x7F) == (rate & 0x7F))
-+			return 1;
-+	return 0;
-+}
-+
-+extern u8	WIFI_OFDMRATES[];
-+bool rtw_is_ofdm_rate(u8 rate)
-+{
-+	int i;
-+
-+	for (i = 0; i < 8; i++)
-+		if ((WIFI_OFDMRATES[i] & 0x7F) == (rate & 0x7F))
-+			return 1;
-+	return 0;
-+}
-+
-+/* test if rate is defined in rtw_basic_rate_cck */
-+bool rtw_is_basic_rate_cck(u8 rate)
-+{
-+	int i;
-+
-+	for (i = 0; i < 4; i++)
-+		if ((rtw_basic_rate_cck[i] & 0x7F) == (rate & 0x7F))
-+			return 1;
-+	return 0;
-+}
-+
-+/* test if rate is defined in rtw_basic_rate_ofdm */
-+bool rtw_is_basic_rate_ofdm(u8 rate)
-+{
-+	int i;
-+
-+	for (i = 0; i < 3; i++)
-+		if ((rtw_basic_rate_ofdm[i] & 0x7F) == (rate & 0x7F))
-+			return 1;
-+	return 0;
-+}
-+
-+/* test if rate is defined in rtw_basic_rate_mix */
-+bool rtw_is_basic_rate_mix(u8 rate)
-+{
-+	int i;
-+
-+	for (i = 0; i < 7; i++)
-+		if ((rtw_basic_rate_mix[i] & 0x7F) == (rate & 0x7F))
-+			return 1;
-+	return 0;
-+}
-+#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
-+int new_bcn_max = 3;
-+#endif
-+int cckrates_included(unsigned char *rate, int ratelen)
-+{
-+	int	i;
-+
-+	for (i = 0; i < ratelen; i++) {
-+		if ((((rate[i]) & 0x7f) == 2)	|| (((rate[i]) & 0x7f) == 4) ||
-+		    (((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22))
-+			return _TRUE;
-+	}
-+
-+	return _FALSE;
-+
-+}
-+
-+int cckratesonly_included(unsigned char *rate, int ratelen)
-+{
-+	int	i;
-+
-+	for (i = 0; i < ratelen; i++) {
-+		if ((((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&
-+		    (((rate[i]) & 0x7f) != 11)  && (((rate[i]) & 0x7f) != 22))
-+			return _FALSE;
-+	}
-+
-+	return _TRUE;
-+}
-+
-+s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta)
-+{
-+	s8 nss = 1;
-+
-+	if (!psta)
-+		return nss;
-+
-+	nss = GET_HAL_RX_NSS(adapter);
-+
-+#ifdef CONFIG_80211N_HT
-+	#ifdef CONFIG_80211AC_VHT
-+	if (psta->vhtpriv.vht_option)
-+		nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map));
-+	else
-+	#endif /* CONFIG_80211AC_VHT */
-+	if (psta->htpriv.ht_option)
-+		nss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set));
-+#endif /*CONFIG_80211N_HT*/
-+	RTW_INFO("%s: %d ss\n", __func__, nss);
-+	return nss;
-+}
-+
-+s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta)
-+{
-+	s8 nss = 1;
-+
-+	if (!psta)
-+		return nss;
-+
-+	nss = GET_HAL_TX_NSS(adapter);
-+
-+#ifdef CONFIG_80211N_HT
-+	#ifdef CONFIG_80211AC_VHT
-+	if (psta->vhtpriv.vht_option)
-+		nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map));
-+	else
-+	#endif /* CONFIG_80211AC_VHT */
-+	if (psta->htpriv.ht_option)
-+		nss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set));
-+#endif /*CONFIG_80211N_HT*/
-+	RTW_INFO("%s: %d SS\n", __func__, nss);
-+	return nss;
-+}
-+
-+u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen)
-+{
-+	u8 network_type = 0;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+
-+	if (pmlmeext->cur_channel > 14) {
-+		if (pmlmeinfo->VHT_enable)
-+			network_type = WIRELESS_11AC;
-+		else if (pmlmeinfo->HT_enable)
-+			network_type = WIRELESS_11_5N;
-+
-+		network_type |= WIRELESS_11A;
-+	} else {
-+		if (pmlmeinfo->HT_enable)
-+			network_type = WIRELESS_11_24N;
-+
-+		if ((cckratesonly_included(rate, ratelen)) == _TRUE)
-+			network_type |= WIRELESS_11B;
-+		else if ((cckrates_included(rate, ratelen)) == _TRUE)
-+			network_type |= WIRELESS_11BG;
-+		else
-+			network_type |= WIRELESS_11G;
-+	}
-+
-+	return	network_type;
-+}
-+
-+unsigned char ratetbl_val_2wifirate(unsigned char rate);
-+unsigned char ratetbl_val_2wifirate(unsigned char rate)
-+{
-+	unsigned char val = 0;
-+
-+	switch (rate & 0x7f) {
-+	case 0:
-+		val = IEEE80211_CCK_RATE_1MB;
-+		break;
-+
-+	case 1:
-+		val = IEEE80211_CCK_RATE_2MB;
-+		break;
-+
-+	case 2:
-+		val = IEEE80211_CCK_RATE_5MB;
-+		break;
-+
-+	case 3:
-+		val = IEEE80211_CCK_RATE_11MB;
-+		break;
-+
-+	case 4:
-+		val = IEEE80211_OFDM_RATE_6MB;
-+		break;
-+
-+	case 5:
-+		val = IEEE80211_OFDM_RATE_9MB;
-+		break;
-+
-+	case 6:
-+		val = IEEE80211_OFDM_RATE_12MB;
-+		break;
-+
-+	case 7:
-+		val = IEEE80211_OFDM_RATE_18MB;
-+		break;
-+
-+	case 8:
-+		val = IEEE80211_OFDM_RATE_24MB;
-+		break;
-+
-+	case 9:
-+		val = IEEE80211_OFDM_RATE_36MB;
-+		break;
-+
-+	case 10:
-+		val = IEEE80211_OFDM_RATE_48MB;
-+		break;
-+
-+	case 11:
-+		val = IEEE80211_OFDM_RATE_54MB;
-+		break;
-+
-+	}
-+
-+	return val;
-+
-+}
-+
-+int is_basicrate(_adapter *padapter, unsigned char rate);
-+int is_basicrate(_adapter *padapter, unsigned char rate)
-+{
-+	int i;
-+	unsigned char val;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+
-+	for (i = 0; i < NumRates; i++) {
-+		val = pmlmeext->basicrate[i];
-+
-+		if ((val != 0xff) && (val != 0xfe)) {
-+			if (rate == ratetbl_val_2wifirate(val))
-+				return _TRUE;
-+		}
-+	}
-+
-+	return _FALSE;
-+}
-+
-+unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset);
-+unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset)
-+{
-+	int i;
-+	unsigned char rate;
-+	unsigned int	len = 0;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+
-+	for (i = 0; i < NumRates; i++) {
-+		rate = pmlmeext->datarate[i];
-+
-+		if (rtw_get_oper_ch(padapter) > 14 && rate < _6M_RATE_) /*5G no support CCK rate*/
-+			continue;
-+
-+		switch (rate) {
-+		case 0xff:
-+			return len;
-+
-+		case 0xfe:
-+			continue;
-+
-+		default:
-+			rate = ratetbl_val_2wifirate(rate);
-+
-+			if (is_basicrate(padapter, rate) == _TRUE)
-+				rate |= IEEE80211_BASIC_RATE_MASK;
-+
-+			rateset[len] = rate;
-+			len++;
-+			break;
-+		}
-+	}
-+	return len;
-+}
-+
-+void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len)
-+{
-+	unsigned char supportedrates[NumRates];
-+
-+	_rtw_memset(supportedrates, 0, NumRates);
-+	*bssrate_len = ratetbl2rateset(padapter, supportedrates);
-+	_rtw_memcpy(pbssrate, supportedrates, *bssrate_len);
-+}
-+
-+void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask)
-+{
-+	u8 mcs_rate_1r = (u8)(mask & 0xff);
-+	u8 mcs_rate_2r = (u8)((mask >> 8) & 0xff);
-+	u8 mcs_rate_3r = (u8)((mask >> 16) & 0xff);
-+	u8 mcs_rate_4r = (u8)((mask >> 24) & 0xff);
-+
-+	mcs_set[0] &= mcs_rate_1r;
-+	mcs_set[1] &= mcs_rate_2r;
-+	mcs_set[2] &= mcs_rate_3r;
-+	mcs_set[3] &= mcs_rate_4r;
-+}
-+
-+void UpdateBrateTbl(
-+	PADAPTER		Adapter,
-+	u8			*mBratesOS
-+)
-+{
-+	u8	i;
-+	u8	rate;
-+
-+	/* 1M, 2M, 5.5M, 11M, 6M, 12M, 24M are mandatory. */
-+	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
-+		rate = mBratesOS[i] & 0x7f;
-+		switch (rate) {
-+		case IEEE80211_CCK_RATE_1MB:
-+		case IEEE80211_CCK_RATE_2MB:
-+		case IEEE80211_CCK_RATE_5MB:
-+		case IEEE80211_CCK_RATE_11MB:
-+		case IEEE80211_OFDM_RATE_6MB:
-+		case IEEE80211_OFDM_RATE_12MB:
-+		case IEEE80211_OFDM_RATE_24MB:
-+			mBratesOS[i] |= IEEE80211_BASIC_RATE_MASK;
-+			break;
-+		}
-+	}
-+
-+}
-+
-+void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen)
-+{
-+	u8	i;
-+	u8	rate;
-+
-+	for (i = 0; i < bssratelen; i++) {
-+		rate = bssrateset[i] & 0x7f;
-+		switch (rate) {
-+		case IEEE80211_CCK_RATE_1MB:
-+		case IEEE80211_CCK_RATE_2MB:
-+		case IEEE80211_CCK_RATE_5MB:
-+		case IEEE80211_CCK_RATE_11MB:
-+			bssrateset[i] |= IEEE80211_BASIC_RATE_MASK;
-+			break;
-+		}
-+	}
-+
-+}
-+void Set_MSR(_adapter *padapter, u8 type)
-+{
-+	rtw_hal_set_hwreg(padapter, HW_VAR_MEDIA_STATUS, (u8 *)(&type));
-+}
-+
-+inline u8 rtw_get_oper_ch(_adapter *adapter)
-+{
-+	return adapter_to_dvobj(adapter)->oper_channel;
-+}
-+
-+inline void rtw_set_oper_ch(_adapter *adapter, u8 ch)
-+{
-+#ifdef DBG_CH_SWITCH
-+	const int len = 128;
-+	char msg[128] = {0};
-+	int cnt = 0;
-+	int i = 0;
-+#endif  /* DBG_CH_SWITCH */
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	if (dvobj->oper_channel != ch) {
-+		dvobj->on_oper_ch_time = rtw_get_current_time();
-+
-+#ifdef DBG_CH_SWITCH
-+		cnt += snprintf(msg + cnt, len - cnt, "switch to ch %3u", ch);
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			_adapter *iface = dvobj->padapters[i];
-+			cnt += snprintf(msg + cnt, len - cnt, " ["ADPT_FMT":", ADPT_ARG(iface));
-+			if (iface->mlmeextpriv.cur_channel == ch)
-+				cnt += snprintf(msg + cnt, len - cnt, "C");
-+			else
-+				cnt += snprintf(msg + cnt, len - cnt, "_");
-+			if (iface->wdinfo.listen_channel == ch && !rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_NONE))
-+				cnt += snprintf(msg + cnt, len - cnt, "L");
-+			else
-+				cnt += snprintf(msg + cnt, len - cnt, "_");
-+			cnt += snprintf(msg + cnt, len - cnt, "]");
-+		}
-+
-+		RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(adapter), msg);
-+#endif /* DBG_CH_SWITCH */
-+	}
-+
-+	dvobj->oper_channel = ch;
-+}
-+
-+inline u8 rtw_get_oper_bw(_adapter *adapter)
-+{
-+	return adapter_to_dvobj(adapter)->oper_bwmode;
-+}
-+
-+inline void rtw_set_oper_bw(_adapter *adapter, u8 bw)
-+{
-+	adapter_to_dvobj(adapter)->oper_bwmode = bw;
-+}
-+
-+inline u8 rtw_get_oper_choffset(_adapter *adapter)
-+{
-+	return adapter_to_dvobj(adapter)->oper_ch_offset;
-+}
-+
-+inline void rtw_set_oper_choffset(_adapter *adapter, u8 offset)
-+{
-+	adapter_to_dvobj(adapter)->oper_ch_offset = offset;
-+}
-+
-+inline systime rtw_get_on_oper_ch_time(_adapter *adapter)
-+{
-+	return adapter_to_dvobj(adapter)->on_oper_ch_time;
-+}
-+
-+inline systime rtw_get_on_cur_ch_time(_adapter *adapter)
-+{
-+	if (adapter->mlmeextpriv.cur_channel == adapter_to_dvobj(adapter)->oper_channel)
-+		return adapter_to_dvobj(adapter)->on_oper_ch_time;
-+	else
-+		return 0;
-+}
-+
-+void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode)
-+{
-+	u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE)
-+	u8 iqk_info_backup = _FALSE;
-+#endif
-+
-+	if (padapter->bNotifyChannelChange)
-+		RTW_INFO("[%s] ch = %d, offset = %d, bwmode = %d\n", __FUNCTION__, channel, channel_offset, bwmode);
-+
-+	center_ch = rtw_get_center_ch(channel, bwmode, channel_offset);
-+
-+	if (bwmode == CHANNEL_WIDTH_80) {
-+		if (center_ch > channel)
-+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
-+		else if (center_ch < channel)
-+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
-+		else
-+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	}
-+	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(padapter)) {
-+		/* driver doesn't set channel setting reg under MCC */
-+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
-+			RTW_INFO("Warning: Do not set channel setting reg MCC mode\n");
-+	}
-+#endif
-+
-+#ifdef CONFIG_DFS_MASTER
-+	{
-+		struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+		bool ori_overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl);
-+		bool new_overlap_radar_detect_ch = _rtw_rfctl_overlap_radar_detect_ch(rfctl, channel, bwmode, channel_offset);
-+
-+		if (new_overlap_radar_detect_ch && IS_CH_WAITING(rfctl)) {
-+			u8 pause = 0xFF;
-+
-+			rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause);
-+		}
-+#endif /* CONFIG_DFS_MASTER */
-+
-+		/* set Channel */
-+		/* saved channel/bw info */
-+		rtw_set_oper_ch(padapter, channel);
-+		rtw_set_oper_bw(padapter, bwmode);
-+		rtw_set_oper_choffset(padapter, channel_offset);
-+
-+#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE)
-+		/* To check if we need to backup iqk info after switch chnl & bw */
-+		{
-+			u8 take_care_iqk, do_iqk;
-+
-+			rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
-+			rtw_hal_get_hwreg(padapter, HW_VAR_DO_IQK, &do_iqk);
-+			if ((take_care_iqk == _TRUE) && (do_iqk == _TRUE))
-+				iqk_info_backup = _TRUE;
-+		}
-+#endif
-+
-+		rtw_hal_set_chnl_bw(padapter, center_ch, bwmode, channel_offset, chnl_offset80); /* set center channel */
-+
-+#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE)
-+		if (iqk_info_backup == _TRUE)
-+			rtw_hal_ch_sw_iqk_info_backup(padapter);
-+#endif
-+
-+#ifdef CONFIG_DFS_MASTER
-+		if (new_overlap_radar_detect_ch)
-+			rtw_odm_radar_detect_enable(padapter);
-+		else if (ori_overlap_radar_detect_ch) {
-+			u8 pause = 0x00;
-+
-+			rtw_odm_radar_detect_disable(padapter);
-+			rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause);
-+		}
-+	}
-+#endif /* CONFIG_DFS_MASTER */
-+
-+	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
-+}
-+
-+__inline u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork)
-+{
-+	return pnetwork->MacAddress;
-+}
-+
-+u16 get_beacon_interval(WLAN_BSSID_EX *bss)
-+{
-+	unsigned short val;
-+	_rtw_memcpy((unsigned char *)&val, rtw_get_beacon_interval_from_ie(bss->IEs), 2);
-+
-+	return le16_to_cpu(val);
-+
-+}
-+
-+int is_client_associated_to_ap(_adapter *padapter)
-+{
-+	struct mlme_ext_priv	*pmlmeext;
-+	struct mlme_ext_info	*pmlmeinfo;
-+
-+	if (!padapter)
-+		return _FAIL;
-+
-+	pmlmeext = &padapter->mlmeextpriv;
-+	pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE))
-+		return _TRUE;
-+	else
-+		return _FAIL;
-+}
-+
-+int is_client_associated_to_ibss(_adapter *padapter)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE))
-+		return _TRUE;
-+	else
-+		return _FAIL;
-+}
-+
-+int is_IBSS_empty(_adapter *padapter)
-+{
-+	int i;
-+	struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl;
-+
-+	for (i = 0; i < macid_ctl->num; i++) {
-+		if (!rtw_macid_is_used(macid_ctl, i))
-+			continue;
-+		if (!rtw_macid_is_iface_specific(macid_ctl, i, padapter))
-+			continue;
-+		if (!GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[i]))
-+			continue;
-+		if (GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]) == H2C_MSR_ROLE_ADHOC)
-+			return _FAIL;
-+	}
-+
-+	return _TRUE;
-+}
-+
-+unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval)
-+{
-+	if ((bcn_interval << 2) < WAIT_FOR_BCN_TO_MIN)
-+		return WAIT_FOR_BCN_TO_MIN;
-+	else if ((bcn_interval << 2) > WAIT_FOR_BCN_TO_MAX)
-+		return WAIT_FOR_BCN_TO_MAX;
-+	else
-+		return bcn_interval << 2;
-+}
-+
-+void invalidate_cam_all(_adapter *padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	u8 bmc_id = rtw_iface_bcmc_id_get(padapter);
-+	_irqL irqL;
-+	u8 val8 = 0;
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, &val8);
-+
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	rtw_sec_cam_map_clr_all(&cam_ctl->used);
-+
-+#ifndef SEC_DEFAULT_KEY_SEARCH
-+	/* for BMC data TX with force camid */
-+	if (bmc_id != INVALID_SEC_MAC_CAM_ID) {
-+		rtw_sec_cam_map_set(&cam_ctl->used, bmc_id);
-+		if (_rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_EXTRA_SEC))
-+			rtw_sec_cam_map_set(&cam_ctl->used, bmc_id + 1);
-+	}
-+#endif
-+
-+	_rtw_memset(dvobj->cam_cache, 0, sizeof(struct sec_cam_ent) * SEC_CAM_ENT_NUM_SW_LIMIT);
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+
-+#ifdef SEC_DEFAULT_KEY_SEARCH//!BMC TX force camid
-+	/* clear default key related key search setting */
-+	rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_FALSE);
-+#endif
-+}
-+
-+void _clear_cam_entry(_adapter *padapter, u8 entry)
-+{
-+	unsigned char null_sta[6] = {0};
-+	unsigned char null_key[32] = {0};
-+
-+	rtw_sec_write_cam_ent(padapter, entry, 0, null_sta, null_key);
-+}
-+
-+inline void _write_cam(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
-+{
-+#ifdef CONFIG_WRITE_CACHE_ONLY
-+	write_cam_cache(adapter, id , ctrl, mac, key);
-+#else
-+	rtw_sec_write_cam_ent(adapter, id, ctrl, mac, key);
-+	write_cam_cache(adapter, id , ctrl, mac, key);
-+#endif
-+}
-+
-+inline void write_cam(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
-+{
-+	if (ctrl & BIT(9)) {
-+		_write_cam(adapter, id, ctrl, mac, key);
-+		_write_cam(adapter, (id + 1), ctrl | BIT(5), mac, (key + 16));
-+		RTW_INFO_DUMP("key-0: ", key, 16);
-+		RTW_INFO_DUMP("key-1: ", (key + 16), 16);
-+	} else
-+		_write_cam(adapter, id, ctrl, mac, key);
-+}
-+
-+inline void clear_cam_entry(_adapter *adapter, u8 id)
-+{
-+	_clear_cam_entry(adapter, id);
-+	clear_cam_cache(adapter, id);
-+}
-+
-+inline void write_cam_from_cache(_adapter *adapter, u8 id)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	_irqL irqL;
-+	struct sec_cam_ent cache;
-+
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+	_rtw_memcpy(&cache, &dvobj->cam_cache[id], sizeof(struct sec_cam_ent));
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	rtw_sec_write_cam_ent(adapter, id, cache.ctrl, cache.mac, cache.key);
-+}
-+void write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	dvobj->cam_cache[id].ctrl = ctrl;
-+	_rtw_memcpy(dvobj->cam_cache[id].mac, mac, ETH_ALEN);
-+	_rtw_memcpy(dvobj->cam_cache[id].key, key, 16);
-+
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+}
-+
-+void clear_cam_cache(_adapter *adapter, u8 id)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	_rtw_memset(&(dvobj->cam_cache[id]), 0, sizeof(struct sec_cam_ent));
-+
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+}
-+
-+inline bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+
-+	if (cam_ctl->sec_cap & cap)
-+		return _TRUE;
-+	return _FALSE;
-+}
-+
-+inline void _rtw_camctl_set_flags(_adapter *adapter, u32 flags)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+
-+	cam_ctl->flags |= flags;
-+}
-+
-+inline void rtw_camctl_set_flags(_adapter *adapter, u32 flags)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+	_rtw_camctl_set_flags(adapter, flags);
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+}
-+
-+inline void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+
-+	cam_ctl->flags &= ~flags;
-+}
-+
-+inline void rtw_camctl_clr_flags(_adapter *adapter, u32 flags)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+	_rtw_camctl_clr_flags(adapter, flags);
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+}
-+
-+inline bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+
-+	if (cam_ctl->flags & flags)
-+		return _TRUE;
-+	return _FALSE;
-+}
-+
-+void dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num)
-+{
-+	RTW_PRINT_SEL(sel, "0x%08x\n", map->m0);
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
-+	if (max_num && max_num > 32)
-+		RTW_PRINT_SEL(sel, "0x%08x\n", map->m1);
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
-+	if (max_num && max_num > 64)
-+		RTW_PRINT_SEL(sel, "0x%08x\n", map->m2);
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
-+	if (max_num && max_num > 96)
-+		RTW_PRINT_SEL(sel, "0x%08x\n", map->m3);
-+#endif
-+}
-+
-+inline bool rtw_sec_camid_is_set(struct sec_cam_bmp *map, u8 id)
-+{
-+	if (id < 32)
-+		return map->m0 & BIT(id);
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
-+	else if (id < 64)
-+		return map->m1 & BIT(id - 32);
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
-+	else if (id < 96)
-+		return map->m2 & BIT(id - 64);
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
-+	else if (id < 128)
-+		return map->m3 & BIT(id - 96);
-+#endif
-+	else
-+		rtw_warn_on(1);
-+
-+	return 0;
-+}
-+
-+inline void rtw_sec_cam_map_set(struct sec_cam_bmp *map, u8 id)
-+{
-+	if (id < 32)
-+		map->m0 |= BIT(id);
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
-+	else if (id < 64)
-+		map->m1 |= BIT(id - 32);
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
-+	else if (id < 96)
-+		map->m2 |= BIT(id - 64);
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
-+	else if (id < 128)
-+		map->m3 |= BIT(id - 96);
-+#endif
-+	else
-+		rtw_warn_on(1);
-+}
-+
-+inline void rtw_sec_cam_map_clr(struct sec_cam_bmp *map, u8 id)
-+{
-+	if (id < 32)
-+		map->m0 &= ~BIT(id);
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
-+	else if (id < 64)
-+		map->m1 &= ~BIT(id - 32);
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
-+	else if (id < 96)
-+		map->m2 &= ~BIT(id - 64);
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
-+	else if (id < 128)
-+		map->m3 &= ~BIT(id - 96);
-+#endif
-+	else
-+		rtw_warn_on(1);
-+}
-+
-+inline void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map)
-+{
-+	map->m0 = 0;
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
-+	map->m1 = 0;
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
-+	map->m2 = 0;
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
-+	map->m3 = 0;
-+#endif
-+}
-+
-+inline bool rtw_sec_camid_is_drv_forbid(struct cam_ctl_t *cam_ctl, u8 id)
-+{
-+	struct sec_cam_bmp forbid_map;
-+
-+	forbid_map.m0 = 0x00000ff0;
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
-+	forbid_map.m1 = 0x00000000;
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
-+	forbid_map.m2 = 0x00000000;
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
-+	forbid_map.m3 = 0x00000000;
-+#endif
-+
-+	if (id < 32)
-+		return forbid_map.m0 & BIT(id);
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
-+	else if (id < 64)
-+		return forbid_map.m1 & BIT(id - 32);
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
-+	else if (id < 96)
-+		return forbid_map.m2 & BIT(id - 64);
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
-+	else if (id < 128)
-+		return forbid_map.m3 & BIT(id - 96);
-+#endif
-+	else
-+		rtw_warn_on(1);
-+
-+	return 1;
-+}
-+
-+bool _rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id)
-+{
-+	bool ret = _FALSE;
-+
-+	if (id >= cam_ctl->num) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+#if 0 /* for testing */
-+	if (rtw_sec_camid_is_drv_forbid(cam_ctl, id)) {
-+		ret = _TRUE;
-+		goto exit;
-+	}
-+#endif
-+
-+	ret = rtw_sec_camid_is_set(&cam_ctl->used, id);
-+
-+exit:
-+	return ret;
-+}
-+
-+inline bool rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id)
-+{
-+	_irqL irqL;
-+	bool ret;
-+
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+	ret = _rtw_sec_camid_is_used(cam_ctl, id);
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	return ret;
-+}
-+u8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	int i;
-+	_irqL irqL;
-+	u8 sec_cam_num = 0;
-+
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+	for (i = 0; i < cam_ctl->num; i++) {
-+		if (_rtw_sec_camid_is_used(cam_ctl, i)) {
-+			sec_key_id[sec_cam_num++] = i;
-+			if (sec_cam_num == max_bk_key_num)
-+				break;
-+		}
-+	}
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	return sec_cam_num;
-+}
-+
-+inline bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	bool ret = _FALSE;
-+
-+	if (cam_id >= cam_ctl->num) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (_rtw_sec_camid_is_used(cam_ctl, cam_id) == _FALSE)
-+		goto exit;
-+
-+	ret = (dvobj->cam_cache[cam_id].ctrl & BIT6) ? _TRUE : _FALSE;
-+
-+exit:
-+	return ret;
-+}
-+
-+inline bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	_irqL irqL;
-+	bool ret;
-+
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+	ret = _rtw_camid_is_gk(adapter, cam_id);
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	return ret;
-+}
-+
-+bool cam_cache_chk(_adapter *adapter, u8 id, u8 *addr, s16 kid, s8 gk)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	bool ret = _FALSE;
-+
-+	if (addr && _rtw_memcmp(dvobj->cam_cache[id].mac, addr, ETH_ALEN) == _FALSE)
-+		goto exit;
-+	if (kid >= 0 && kid != (dvobj->cam_cache[id].ctrl & 0x03))
-+		goto exit;
-+	if (gk != -1 && (gk ? _TRUE : _FALSE) != _rtw_camid_is_gk(adapter, id))
-+		goto exit;
-+
-+	ret = _TRUE;
-+
-+exit:
-+	return ret;
-+}
-+
-+s16 _rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	int i;
-+	s16 cam_id = -1;
-+
-+	for (i = 0; i < cam_ctl->num; i++) {
-+		if (cam_cache_chk(adapter, i, addr, kid, gk)) {
-+			cam_id = i;
-+			break;
-+		}
-+	}
-+
-+	if (0) {
-+		if (addr)
-+			RTW_INFO(FUNC_ADPT_FMT" addr:"MAC_FMT" kid:%d, gk:%d, return cam_id:%d\n"
-+				, FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid, gk, cam_id);
-+		else
-+			RTW_INFO(FUNC_ADPT_FMT" addr:%p kid:%d, gk:%d, return cam_id:%d\n"
-+				, FUNC_ADPT_ARG(adapter), addr, kid, gk, cam_id);
-+	}
-+
-+	return cam_id;
-+}
-+
-+s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	_irqL irqL;
-+	s16 cam_id = -1;
-+
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+	cam_id = _rtw_camid_search(adapter, addr, kid, gk);
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	return cam_id;
-+}
-+
-+s16 rtw_get_camid(_adapter *adapter, u8 *addr, s16 kid, u8 gk, bool ext_sec)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	int i;
-+#if 0 /* for testing */
-+	static u8 start_id = 0;
-+#else
-+	u8 start_id = 0;
-+#endif
-+	s16 cam_id = -1;
-+
-+	if (addr == NULL) {
-+		RTW_PRINT(FUNC_ADPT_FMT" mac_address is NULL\n"
-+			  , FUNC_ADPT_ARG(adapter));
-+		rtw_warn_on(1);
-+		goto _exit;
-+	}
-+
-+	/* find cam entry which has the same addr, kid (, gk bit) */
-+	if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC) == _TRUE)
-+		i = _rtw_camid_search(adapter, addr, kid, gk);
-+	else
-+		i = _rtw_camid_search(adapter, addr, kid, -1);
-+
-+	if (i >= 0) {
-+		cam_id = i;
-+		goto _exit;
-+	}
-+
-+	for (i = 0; i < cam_ctl->num; i++) {
-+		/* bypass default key which is allocated statically */
-+#ifdef SEC_DEFAULT_KEY_SEARCH
-+		if (((i + start_id) % cam_ctl->num) < 4)
-+			continue;
-+#endif
-+		if (_rtw_sec_camid_is_used(cam_ctl, ((i + start_id) % cam_ctl->num)) == _FALSE) {
-+			if (ext_sec) {
-+				/* look out continue slot */
-+				if (((i + 1) < cam_ctl->num) &&
-+					(_rtw_sec_camid_is_used(cam_ctl, (((i + 1) + start_id) % cam_ctl->num)) == _FALSE))
-+					break;
-+				else
-+					continue;
-+			} else
-+				break;
-+		}
-+	}
-+
-+	if (i == cam_ctl->num) {
-+		RTW_PRINT(FUNC_ADPT_FMT" %s key with "MAC_FMT" id:%u no room\n"
-+			, FUNC_ADPT_ARG(adapter), gk ? "group" : "pairwise", MAC_ARG(addr), kid);
-+		rtw_warn_on(1);
-+		goto _exit;
-+	}
-+
-+	cam_id = ((i + start_id) % cam_ctl->num);
-+	start_id = ((i + start_id + 1) % cam_ctl->num);
-+
-+_exit:
-+	return cam_id;
-+}
-+
-+s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool ext_sec, bool *used)
-+{
-+	struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	_irqL irqL;
-+	s16 cam_id = -1;
-+
-+	*used = _FALSE;
-+
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	if ((((mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE))
-+	    && !sta) {
-+		/*
-+		* 1. non-STA mode WEP key
-+		* 2. group TX key
-+		*/
-+#ifdef SEC_DEFAULT_KEY_SEARCH
-+		/* static alloction to default key by key ID when concurrent is not defined */
-+		if (kid > 3) {
-+			RTW_PRINT(FUNC_ADPT_FMT" group key with invalid key id:%u\n"
-+				  , FUNC_ADPT_ARG(adapter), kid);
-+			rtw_warn_on(1);
-+			goto bitmap_handle;
-+		}
-+		cam_id = kid;
-+#else
-+		u8 *addr = adapter_mac_addr(adapter);
-+
-+		cam_id = rtw_get_camid(adapter, addr, kid, gk, ext_sec);
-+		if (1)
-+			RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" assigned cam_id:%u\n"
-+				, FUNC_ADPT_ARG(adapter), MAC_ARG(addr), cam_id);
-+#endif
-+	} else {
-+		/*
-+		* 1. STA mode WEP key
-+		* 2. STA mode group RX key
-+		* 3. sta key (pairwise, group RX)
-+		*/
-+		u8 *addr = sta ? sta->cmn.mac_addr : NULL;
-+
-+		if (!sta) {
-+			if (!(mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {
-+				/* bypass STA mode group key setting before connected(ex:WEP) because bssid is not ready */
-+				goto bitmap_handle;
-+			}
-+			addr = get_bssid(&adapter->mlmepriv);/*A2*/
-+		}
-+		cam_id = rtw_get_camid(adapter, addr, kid, gk, ext_sec);
-+	}
-+
-+
-+bitmap_handle:
-+	if (cam_id >= 0) {
-+		*used = _rtw_sec_camid_is_used(cam_ctl, cam_id);
-+		rtw_sec_cam_map_set(&cam_ctl->used, cam_id);
-+		if (ext_sec)
-+			rtw_sec_cam_map_set(&cam_ctl->used, cam_id + 1);
-+	}
-+
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	return cam_id;
-+}
-+
-+void rtw_camid_set(_adapter *adapter, u8 cam_id)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	if (cam_id < cam_ctl->num)
-+		rtw_sec_cam_map_set(&cam_ctl->used, cam_id);
-+
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+}
-+
-+void rtw_camid_free(_adapter *adapter, u8 cam_id)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	if (cam_id < cam_ctl->num)
-+		rtw_sec_cam_map_clr(&cam_ctl->used, cam_id);
-+
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+}
-+
-+/*Must pause TX/RX before use this API*/
-+inline void rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	struct sec_cam_ent cache_a, cache_b;
-+	_irqL irqL;
-+	bool cam_a_used, cam_b_used;
-+
-+	if (1)
-+		RTW_INFO(ADPT_FMT" - sec_cam %d,%d swap\n", ADPT_ARG(adapter), cam_id_a, cam_id_b);
-+
-+	if (cam_id_a == cam_id_b)
-+		return;
-+
-+	rtw_mi_update_ap_bmc_camid(adapter, cam_id_a, cam_id_b);
-+
-+	/*setp-1. backup org cam_info*/
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	cam_a_used = _rtw_sec_camid_is_used(cam_ctl, cam_id_a);
-+	cam_b_used = _rtw_sec_camid_is_used(cam_ctl, cam_id_b);
-+
-+	if (cam_a_used)
-+		_rtw_memcpy(&cache_a, &dvobj->cam_cache[cam_id_a], sizeof(struct sec_cam_ent));
-+
-+	if (cam_b_used)
-+		_rtw_memcpy(&cache_b, &dvobj->cam_cache[cam_id_b], sizeof(struct sec_cam_ent));
-+
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	/*setp-2. clean cam_info*/
-+	if (cam_a_used) {
-+		rtw_camid_free(adapter, cam_id_a);
-+		clear_cam_entry(adapter, cam_id_a);
-+	}
-+	if (cam_b_used) {
-+		rtw_camid_free(adapter, cam_id_b);
-+		clear_cam_entry(adapter, cam_id_b);
-+	}
-+
-+	/*setp-3. set cam_info*/
-+	if (cam_a_used) {
-+		write_cam(adapter, cam_id_b, cache_a.ctrl, cache_a.mac, cache_a.key);
-+		rtw_camid_set(adapter, cam_id_b);
-+	}
-+
-+	if (cam_b_used) {
-+		write_cam(adapter, cam_id_a, cache_b.ctrl, cache_b.mac, cache_b.key);
-+		rtw_camid_set(adapter, cam_id_a);
-+	}
-+}
-+
-+s16 rtw_get_empty_cam_entry(_adapter *adapter, u8 start_camid)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	_irqL irqL;
-+	int i;
-+	s16 cam_id = -1;
-+
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+	for (i = start_camid; i < cam_ctl->num; i++) {
-+		if (_FALSE == _rtw_sec_camid_is_used(cam_ctl, i)) {
-+			cam_id = i;
-+			break;
-+		}
-+	}
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+
-+	return cam_id;
-+}
-+void rtw_clean_dk_section(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
-+	s16 ept_cam_id;
-+	int i;
-+
-+	for (i = 0; i < 4; i++) {
-+		if (rtw_sec_camid_is_used(cam_ctl, i)) {
-+			ept_cam_id = rtw_get_empty_cam_entry(adapter, 4);
-+			if (ept_cam_id > 0)
-+				rtw_sec_cam_swap(adapter, i, ept_cam_id);
-+		}
-+	}
-+}
-+void rtw_clean_hw_dk_cam(_adapter *adapter)
-+{
-+	int i;
-+
-+	for (i = 0; i < 4; i++) {
-+		if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_WRITE_CAM_NEW_RULE))
-+			_clear_cam_entry(adapter, i);
-+		else
-+			rtw_sec_clr_cam_ent(adapter, i);
-+	}
-+}
-+
-+void flush_all_cam_entry(_adapter *padapter)
-+{
-+#ifdef CONFIG_CONCURRENT_MODE
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
-+		struct sta_priv	*pstapriv = &padapter->stapriv;
-+		struct sta_info		*psta;
-+
-+		psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
-+		if (psta) {
-+			if (psta->state & WIFI_AP_STATE) {
-+				/*clear cam when ap free per sta_info*/
-+			} else
-+				rtw_clearstakey_cmd(padapter, psta, _FALSE);
-+		}
-+	} else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
-+#ifdef CONFIG_AP_MODE
-+#ifndef SEC_DEFAULT_KEY_SEARCH
-+		int cam_id = -1;
-+		u8 *addr = adapter_mac_addr(padapter);
-+		u8 bmc_id = rtw_iface_bcmc_id_get(padapter);
-+
-+		while ((cam_id = rtw_camid_search(padapter, addr, -1, -1)) >= 0) {
-+			RTW_PRINT("clear wep or group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(addr), cam_id);
-+			clear_cam_entry(padapter, cam_id);
-+			/* clear cam_ctl.used bit for data BMC TX force camid in rtw_release_macid() */
-+			if (bmc_id == INVALID_SEC_MAC_CAM_ID || cam_id != bmc_id)
-+				rtw_camid_free(padapter, cam_id);
-+		}
-+#else
-+		/* clear default key */
-+		int i, cam_id;
-+		u8 null_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
-+
-+		for (i = 0; i < 4; i++) {
-+			cam_id = rtw_camid_search(padapter, null_addr, i, -1);
-+			if (cam_id >= 0) {
-+				clear_cam_entry(padapter, cam_id);
-+				rtw_camid_free(padapter, cam_id);
-+			}
-+		}
-+		/* clear default key related key search setting */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_FALSE);
-+#endif
-+#endif /* CONFIG_AP_MODE */
-+	}
-+
-+#else /*NON CONFIG_CONCURRENT_MODE*/
-+
-+	invalidate_cam_all(padapter);
-+#endif
-+}
-+
-+#if defined(CONFIG_P2P) && defined(CONFIG_WFD)
-+void rtw_process_wfd_ie(_adapter *adapter, u8 *wfd_ie, u8 wfd_ielen, const char *tag)
-+{
-+	struct wifidirect_info *wdinfo = &adapter->wdinfo;
-+
-+	u8 *attr_content;
-+	u32 attr_contentlen = 0;
-+
-+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
-+		return;
-+
-+	RTW_INFO("[%s] Found WFD IE\n", tag);
-+	attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen);
-+	if (attr_content && attr_contentlen) {
-+		wdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16(attr_content + 2);
-+		RTW_INFO("[%s] Peer PORT NUM = %d\n", tag, wdinfo->wfd_info->peer_rtsp_ctrlport);
-+	}
-+}
-+
-+void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag)
-+{
-+	u8 *wfd_ie;
-+	u32	wfd_ielen;
-+
-+	if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
-+		return;
-+
-+	wfd_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &wfd_ielen);
-+	while (wfd_ie) {
-+		rtw_process_wfd_ie(adapter, wfd_ie, wfd_ielen, tag);
-+		wfd_ie = rtw_get_wfd_ie(wfd_ie + wfd_ielen, (ies + ies_len) - (wfd_ie + wfd_ielen), NULL, &wfd_ielen);
-+	}
-+}
-+#endif /* defined(CONFIG_P2P) && defined(CONFIG_WFD) */
-+
-+int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs	pIE)
-+{
-+	/* struct registry_priv	*pregpriv = &padapter->registrypriv; */
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if (pmlmepriv->qospriv.qos_option == 0) {
-+		pmlmeinfo->WMM_enable = 0;
-+		return _FALSE;
-+	}
-+
-+	if (_rtw_memcmp(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)))
-+		return _FALSE;
-+	else
-+		_rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element));
-+	pmlmeinfo->WMM_enable = 1;
-+	return _TRUE;
-+
-+#if 0
-+	if (pregpriv->wifi_spec == 1) {
-+		if (pmlmeinfo->WMM_enable == 1) {
-+			/* todo: compare the parameter set count & decide wheher to update or not */
-+			return _FAIL;
-+		} else {
-+			pmlmeinfo->WMM_enable = 1;
-+			_rtw_rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element));
-+			return _TRUE;
-+		}
-+	} else {
-+		pmlmeinfo->WMM_enable = 0;
-+		return _FAIL;
-+	}
-+#endif
-+
-+}
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+u8 rtw_is_tbtx_capabilty(u8 *p, u8 len){
-+	int i;
-+	u8 tbtx_cap_ie[8] = {0x00, 0xe0, 0x4c, 0x01, 0x00, 0x00, 0x00, 0x00};
-+
-+	for (i = 0; i < len; i++) {
-+		if (*(p + i) != tbtx_cap_ie[i]) 
-+			return _FALSE;
-+		else
-+			continue;
-+	}
-+	return _TRUE;
-+}
-+#endif
-+
-+void WMMOnAssocRsp(_adapter *padapter)
-+{
-+	u8	ACI, ACM, AIFS, ECWMin, ECWMax, aSifsTime;
-+	u8	acm_mask;
-+	u16	TXOP;
-+	u32	acParm, i;
-+	u32	edca[4], inx[4];
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+#ifdef CONFIG_WMMPS_STA
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct qos_priv	*pqospriv = &pmlmepriv->qospriv;
-+#endif /* CONFIG_WMMPS_STA */	
-+
-+	acm_mask = 0;
-+
-+	if (is_supported_5g(pmlmeext->cur_wireless_mode) ||
-+	    (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
-+		aSifsTime = 16;
-+	else
-+		aSifsTime = 10;
-+
-+	if (pmlmeinfo->WMM_enable == 0) {
-+		padapter->mlmepriv.acm_mask = 0;
-+
-+		AIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
-+
-+		if (pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11A)) {
-+			ECWMin = 4;
-+			ECWMax = 10;
-+		} else if (pmlmeext->cur_wireless_mode & WIRELESS_11B) {
-+			ECWMin = 5;
-+			ECWMax = 10;
-+		} else {
-+			ECWMin = 4;
-+			ECWMax = 10;
-+		}
-+
-+		TXOP = 0;
-+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));
-+
-+		ECWMin = 2;
-+		ECWMax = 3;
-+		TXOP = 0x2f;
-+		acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));
-+	} else {
-+		edca[0] = edca[1] = edca[2] = edca[3] = 0;
-+
-+		for (i = 0; i < 4; i++) {
-+			ACI = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 5) & 0x03;
-+			ACM = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 4) & 0x01;
-+
-+			/* AIFS = AIFSN * slot time + SIFS - r2t phy delay */
-+			AIFS = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN & 0x0f) * pmlmeinfo->slotTime + aSifsTime;
-+
-+			ECWMin = (pmlmeinfo->WMM_param.ac_param[i].CW & 0x0f);
-+			ECWMax = (pmlmeinfo->WMM_param.ac_param[i].CW & 0xf0) >> 4;
-+			TXOP = le16_to_cpu(pmlmeinfo->WMM_param.ac_param[i].TXOP_limit);
-+
-+			acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
-+
-+			switch (ACI) {
-+			case 0x0:
-+				rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm));
-+				acm_mask |= (ACM ? BIT(1) : 0);
-+				edca[XMIT_BE_QUEUE] = acParm;
-+				break;
-+
-+			case 0x1:
-+				rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm));
-+				/* acm_mask |= (ACM? BIT(0):0); */
-+				edca[XMIT_BK_QUEUE] = acParm;
-+				break;
-+
-+			case 0x2:
-+				rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm));
-+				acm_mask |= (ACM ? BIT(2) : 0);
-+				edca[XMIT_VI_QUEUE] = acParm;
-+				break;
-+
-+			case 0x3:
-+				rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm));
-+				acm_mask |= (ACM ? BIT(3) : 0);
-+				edca[XMIT_VO_QUEUE] = acParm;
-+				break;
-+			}
-+
-+			RTW_INFO("WMM(%x): %x, %x\n", ACI, ACM, acParm);
-+		}
-+
-+		if (padapter->registrypriv.acm_method == 1)
-+			rtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask));
-+		else
-+			padapter->mlmepriv.acm_mask = acm_mask;
-+
-+		inx[0] = 0;
-+		inx[1] = 1;
-+		inx[2] = 2;
-+		inx[3] = 3;
-+
-+		if (pregpriv->wifi_spec == 1) {
-+			u32	j, tmp, change_inx = _FALSE;
-+
-+			/* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */
-+			for (i = 0; i < 4; i++) {
-+				for (j = i + 1; j < 4; j++) {
-+					/* compare CW and AIFS */
-+					if ((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF))
-+						change_inx = _TRUE;
-+					else if ((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) {
-+						/* compare TXOP */
-+						if ((edca[j] >> 16) > (edca[i] >> 16))
-+							change_inx = _TRUE;
-+					}
-+
-+					if (change_inx) {
-+						tmp = edca[i];
-+						edca[i] = edca[j];
-+						edca[j] = tmp;
-+
-+						tmp = inx[i];
-+						inx[i] = inx[j];
-+						inx[j] = tmp;
-+
-+						change_inx = _FALSE;
-+					}
-+				}
-+			}
-+		}
-+
-+		for (i = 0; i < 4; i++) {
-+			pxmitpriv->wmm_para_seq[i] = inx[i];
-+			RTW_INFO("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]);
-+		}
-+		
-+#ifdef CONFIG_WMMPS_STA
-+		/* if AP supports UAPSD function, driver must set each uapsd TID to coresponding mac register 0x693 */
-+		if (pmlmeinfo->WMM_param.QoS_info & AP_SUPPORTED_UAPSD) {
-+			pqospriv->uapsd_ap_supported = 1;
-+			rtw_hal_set_hwreg(padapter, HW_VAR_UAPSD_TID, NULL);
-+		}
-+#endif /* CONFIG_WMMPS_STA */
-+	}
-+}
-+
-+static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+#ifdef CONFIG_80211N_HT
-+	unsigned char	 new_bwmode;
-+	unsigned char  new_ch_offset;
-+	struct HT_info_element	*pHT_info;
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
-+	u8	cbw40_enable = 0;
-+
-+	if (!pIE)
-+		return;
-+
-+	if (phtpriv->ht_option == _FALSE)
-+		return;
-+
-+	if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_80)
-+		return;
-+
-+	if (pIE->Length > sizeof(struct HT_info_element))
-+		return;
-+
-+	pHT_info = (struct HT_info_element *)pIE->data;
-+
-+	if (hal_chk_bw_cap(padapter, BW_CAP_40M)) {
-+		if (pmlmeext->cur_channel > 14) {
-+			if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
-+				cbw40_enable = 1;
-+		} else {
-+			if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
-+				cbw40_enable = 1;
-+		}
-+	}
-+
-+	if ((pHT_info->infos[0] & BIT(2)) && cbw40_enable) {
-+		new_bwmode = CHANNEL_WIDTH_40;
-+
-+		switch (pHT_info->infos[0] & 0x3) {
-+		case 1:
-+			new_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+			break;
-+
-+		case 3:
-+			new_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+			break;
-+
-+		default:
-+			new_bwmode = CHANNEL_WIDTH_20;
-+			new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+			break;
-+		}
-+	} else {
-+		new_bwmode = CHANNEL_WIDTH_20;
-+		new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	}
-+
-+
-+	if ((new_bwmode != pmlmeext->cur_bwmode || new_ch_offset != pmlmeext->cur_ch_offset)
-+	    && new_bwmode < pmlmeext->cur_bwmode
-+	   ) {
-+		pmlmeinfo->bwmode_updated = _TRUE;
-+
-+		pmlmeext->cur_bwmode = new_bwmode;
-+		pmlmeext->cur_ch_offset = new_ch_offset;
-+
-+		/* update HT info also */
-+		HT_info_handler(padapter, pIE);
-+	} else
-+		pmlmeinfo->bwmode_updated = _FALSE;
-+
-+
-+	if (_TRUE == pmlmeinfo->bwmode_updated) {
-+		struct sta_info *psta;
-+		WLAN_BSSID_EX	*cur_network = &(pmlmeinfo->network);
-+		struct sta_priv	*pstapriv = &padapter->stapriv;
-+
-+		/* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */
-+
-+
-+		/* update ap's stainfo */
-+		psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
-+		if (psta) {
-+			struct ht_priv	*phtpriv_sta = &psta->htpriv;
-+
-+			if (phtpriv_sta->ht_option) {
-+				/* bwmode				 */
-+				psta->cmn.bw_mode = pmlmeext->cur_bwmode;
-+				phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset;
-+			} else {
-+				psta->cmn.bw_mode = CHANNEL_WIDTH_20;
-+				phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+			}
-+
-+			rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta);
-+		}
-+
-+		/* pmlmeinfo->bwmode_updated = _FALSE; */ /* bwmode_updated done, reset it! */
-+	}
-+#endif /* CONFIG_80211N_HT */
-+}
-+
-+#ifdef ROKU_PRIVATE
-+void Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+	unsigned int	i;
-+	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info		*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if (pIE == NULL)
-+		return;
-+
-+	for (i = 0 ; i < pIE->Length; i++)
-+		pmlmeinfo->SupportedRates_infra_ap[i] = (pIE->data[i]);
-+
-+}
-+
-+void Extended_Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+	unsigned int i, j;
-+	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info		*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if (pIE == NULL)
-+		return;
-+
-+	if (pIE->Length > 0) {
-+		for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
-+			if (pmlmeinfo->SupportedRates_infra_ap[i] == 0)
-+				break;
-+		}
-+		for (j = 0; j < pIE->Length; j++)
-+			pmlmeinfo->SupportedRates_infra_ap[i+j] = (pIE->data[j]);
-+	}
-+
-+}
-+
-+void HT_get_ss_from_mcs_set(u8 *mcs_set, u8 *Rx_ss)
-+{
-+	u8 i, j;
-+	u8 r_ss = 0, t_ss = 0;
-+
-+	for (i = 0; i < 4; i++) {
-+		if ((mcs_set[3-i] & 0xff) != 0x00) {
-+			r_ss = 4-i;
-+			break;
-+		}
-+	}
-+
-+	*Rx_ss = r_ss;
-+}
-+
-+void HT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+	unsigned int	i;
-+	u8	cur_stbc_cap_infra_ap = 0;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct ht_priv_infra_ap		*phtpriv = &pmlmepriv->htpriv_infra_ap;
-+
-+	struct mlme_ext_priv		*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info		*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if (pIE == NULL)
-+		return;
-+
-+	pmlmeinfo->ht_vht_received |= BIT(0);
-+
-+	/*copy MCS_SET*/
-+	for (i = 3; i < 19; i++)
-+		phtpriv->MCS_set_infra_ap[i-3] = (pIE->data[i]);
-+
-+	/*get number of stream from mcs set*/
-+	HT_get_ss_from_mcs_set(phtpriv->MCS_set_infra_ap, &phtpriv->Rx_ss_infra_ap);
-+
-+	phtpriv->rx_highest_data_rate_infra_ap = le16_to_cpu(GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(pIE->data));
-+
-+	phtpriv->ldpc_cap_infra_ap = GET_HT_CAP_ELE_LDPC_CAP(pIE->data);
-+
-+	if (GET_HT_CAP_ELE_RX_STBC(pIE->data))
-+		SET_FLAG(cur_stbc_cap_infra_ap, STBC_HT_ENABLE_RX);
-+	if (GET_HT_CAP_ELE_TX_STBC(pIE->data))
-+		SET_FLAG(cur_stbc_cap_infra_ap, STBC_HT_ENABLE_TX);
-+	phtpriv->stbc_cap_infra_ap = cur_stbc_cap_infra_ap;
-+
-+	/*store ap info SGI 20m 40m*/
-+	phtpriv->sgi_20m_infra_ap = GET_HT_CAP_ELE_SHORT_GI20M(pIE->data);
-+	phtpriv->sgi_40m_infra_ap = GET_HT_CAP_ELE_SHORT_GI40M(pIE->data);
-+
-+	/*store ap info for supported channel bandwidth*/
-+	phtpriv->channel_width_infra_ap = GET_HT_CAP_ELE_CHL_WIDTH(pIE->data);
-+}
-+#endif /* ROKU_PRIVATE */
-+
-+void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+#ifdef CONFIG_80211N_HT
-+	unsigned int	i;
-+	u8	max_AMPDU_len, min_MPDU_spacing;
-+	u8	cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, rx_nss = 0;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
-+#ifdef CONFIG_DISABLE_MCS13TO15
-+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+#endif
-+
-+	if (pIE == NULL)
-+		return;
-+
-+	if (phtpriv->ht_option == _FALSE)
-+		return;
-+
-+	pmlmeinfo->HT_caps_enable = 1;
-+
-+	for (i = 0; i < (pIE->Length); i++) {
-+		if (i != 2) {
-+			/*	Commented by Albert 2010/07/12 */
-+			/*	Got the endian issue here. */
-+			pmlmeinfo->HT_caps.u.HT_cap[i] &= (pIE->data[i]);
-+		} else {
-+			/* AMPDU Parameters field */
-+
-+			/* Get MIN of MAX AMPDU Length Exp */
-+			if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (pIE->data[i] & 0x3))
-+				max_AMPDU_len = (pIE->data[i] & 0x3);
-+			else
-+				max_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3);
-+
-+			/* Get MAX of MIN MPDU Start Spacing */
-+			if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (pIE->data[i] & 0x1c))
-+				min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c);
-+			else
-+				min_MPDU_spacing = (pIE->data[i] & 0x1c);
-+
-+			pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para = max_AMPDU_len | min_MPDU_spacing;
-+		}
-+	}
-+
-+	/*	Commented by Albert 2010/07/12 */
-+	/*	Have to handle the endian issue after copying. */
-+	/*	HT_ext_caps didn't be used yet.	 */
-+	pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info);
-+	pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps);
-+
-+	/* update the MCS set */
-+	for (i = 0; i < 16; i++)
-+		pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i];
-+
-+	rx_nss = GET_HAL_RX_NSS(padapter);
-+
-+	switch (rx_nss) {
-+	case 1:
-+		set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R);
-+		break;
-+	case 2:
-+		#ifdef CONFIG_DISABLE_MCS13TO15
-+		if (pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1)
-+			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF);
-+		else
-+		#endif
-+			set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R);
-+		break;
-+	case 3:
-+		set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R);
-+		break;
-+	case 4:
-+		set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R);
-+		break;
-+	default:
-+		RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", GET_HAL_RFPATH(padapter), rx_nss);
-+	}
-+
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
-+		/* Config STBC setting */
-+		if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) {
-+			SET_FLAG(cur_stbc_cap, STBC_HT_ENABLE_TX);
-+			RTW_INFO("Enable HT Tx STBC !\n");
-+		}
-+		phtpriv->stbc_cap = cur_stbc_cap;
-+
-+#ifdef CONFIG_BEAMFORMING
-+		/* Config Tx beamforming setting */
-+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
-+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) {
-+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
-+			/* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
-+			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6);
-+		}
-+
-+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
-+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) {
-+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
-+			/* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
-+			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4);
-+		}
-+		phtpriv->beamform_cap = cur_beamform_cap;
-+		if (cur_beamform_cap)
-+			RTW_INFO("AP HT Beamforming Cap = 0x%02X\n", cur_beamform_cap);
-+#endif /*CONFIG_BEAMFORMING*/
-+	} else {
-+		/*WIFI_STATION_STATEorI_ADHOC_STATE or WIFI_ADHOC_MASTER_STATE*/
-+		/* Config LDPC Coding Capability */
-+		if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP(pIE->data)) {
-+			SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX));
-+			RTW_INFO("Enable HT Tx LDPC!\n");
-+		}
-+		phtpriv->ldpc_cap = cur_ldpc_cap;
-+
-+		/* Config STBC setting */
-+		if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) {
-+			SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX));
-+			RTW_INFO("Enable HT Tx STBC!\n");
-+		}
-+		phtpriv->stbc_cap = cur_stbc_cap;
-+
-+#ifdef CONFIG_BEAMFORMING
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+		/* Config beamforming setting */
-+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
-+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) {
-+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
-+			/* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
-+			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6);
-+		}
-+
-+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
-+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) {
-+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
-+			/* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
-+			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4);
-+		}
-+#else /* !RTW_BEAMFORMING_VERSION_2 */
-+		/* Config Tx beamforming setting */
-+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
-+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) {
-+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
-+			/* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
-+			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6);
-+		}
-+
-+		if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
-+		    GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) {
-+			SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
-+			/* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
-+			SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4);
-+		}
-+#endif /* !RTW_BEAMFORMING_VERSION_2 */
-+		phtpriv->beamform_cap = cur_beamform_cap;
-+		if (cur_beamform_cap)
-+			RTW_INFO("Client HT Beamforming Cap = 0x%02X\n", cur_beamform_cap);
-+#endif /*CONFIG_BEAMFORMING*/
-+	}
-+
-+#endif /* CONFIG_80211N_HT */
-+}
-+
-+void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+#ifdef CONFIG_80211N_HT
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct ht_priv			*phtpriv = &pmlmepriv->htpriv;
-+
-+	if (pIE == NULL)
-+		return;
-+
-+	if (phtpriv->ht_option == _FALSE)
-+		return;
-+
-+
-+	if (pIE->Length > sizeof(struct HT_info_element))
-+		return;
-+
-+	pmlmeinfo->HT_info_enable = 1;
-+	_rtw_memcpy(&(pmlmeinfo->HT_info), pIE->data, pIE->Length);
-+#endif /* CONFIG_80211N_HT */
-+	return;
-+}
-+
-+void HTOnAssocRsp(_adapter *padapter)
-+{
-+	unsigned char		max_AMPDU_len;
-+	unsigned char		min_MPDU_spacing;
-+	/* struct registry_priv	 *pregpriv = &padapter->registrypriv; */
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable))
-+		pmlmeinfo->HT_enable = 1;
-+	else {
-+		pmlmeinfo->HT_enable = 0;
-+		/* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */
-+		return;
-+	}
-+
-+	/* handle A-MPDU parameter field */
-+	/*
-+		AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k
-+		AMPDU_para [4:2]:Min MPDU Start Spacing
-+	*/
-+	max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03;
-+
-+	min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2;
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing));
-+#ifdef CONFIG_80211N_HT
-+	rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len));
-+#endif /* CONFIG_80211N_HT */
-+#if 0 /* move to rtw_update_ht_cap() */
-+	if ((pregpriv->bw_mode > 0) &&
-+	    (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) &&
-+	    (pmlmeinfo->HT_info.infos[0] & BIT(2))) {
-+		/* switch to the 40M Hz mode accoring to the AP */
-+		pmlmeext->cur_bwmode = CHANNEL_WIDTH_40;
-+		switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) {
-+		case EXTCHNL_OFFSET_UPPER:
-+			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+			break;
-+
-+		case EXTCHNL_OFFSET_LOWER:
-+			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+			break;
-+
-+		default:
-+			pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+			break;
-+		}
-+	}
-+#endif
-+
-+	/* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */
-+
-+#if 0 /* move to rtw_update_ht_cap() */
-+	/*  */
-+	/* Config SM Power Save setting */
-+	/*  */
-+	pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2;
-+	if (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) {
-+#if 0
-+		u8 i;
-+		/* update the MCS rates */
-+		for (i = 0; i < 16; i++)
-+			pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i];
-+#endif
-+		RTW_INFO("%s(): WLAN_HT_CAP_SM_PS_STATIC\n", __FUNCTION__);
-+	}
-+
-+	/*  */
-+	/* Config current HT Protection mode. */
-+	/*  */
-+	pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3;
-+#endif
-+
-+}
-+
-+void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if (pIE->Length > 1)
-+		return;
-+
-+	pmlmeinfo->ERP_enable = 1;
-+	_rtw_memcpy(&(pmlmeinfo->ERP_IE), pIE->data, pIE->Length);
-+}
-+
-+void VCS_update(_adapter *padapter, struct sta_info *psta)
-+{
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	switch (pregpriv->vrtl_carrier_sense) { /* 0:off 1:on 2:auto */
-+	case 0: /* off */
-+		psta->rtsen = 0;
-+		psta->cts2self = 0;
-+		break;
-+
-+	case 1: /* on */
-+		if (pregpriv->vcs_type == 1) { /* 1:RTS/CTS 2:CTS to self */
-+			psta->rtsen = 1;
-+			psta->cts2self = 0;
-+		} else {
-+			psta->rtsen = 0;
-+			psta->cts2self = 1;
-+		}
-+		break;
-+
-+	case 2: /* auto */
-+	default:
-+		if (((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1)))
-+			/*||(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/
-+		) {
-+			if (pregpriv->vcs_type == 1) {
-+				psta->rtsen = 1;
-+				psta->cts2self = 0;
-+			} else {
-+				psta->rtsen = 0;
-+				psta->cts2self = 1;
-+			}
-+		} else {
-+			psta->rtsen = 0;
-+			psta->cts2self = 0;
-+		}
-+		break;
-+	}
-+}
-+
-+void	update_ldpc_stbc_cap(struct sta_info *psta)
-+{
-+#ifdef CONFIG_80211N_HT
-+
-+#ifdef CONFIG_80211AC_VHT
-+	if (psta->vhtpriv.vht_option) {
-+		if (TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_ENABLE_TX))
-+			psta->cmn.ldpc_en = VHT_LDPC_EN;
-+		else
-+			psta->cmn.ldpc_en = 0;
-+
-+		if (TEST_FLAG(psta->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX))
-+			psta->cmn.stbc_en = VHT_STBC_EN;
-+		else
-+			psta->cmn.stbc_en = 0;
-+	} else
-+#endif /* CONFIG_80211AC_VHT */
-+		if (psta->htpriv.ht_option) {
-+			if (TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_ENABLE_TX))
-+				psta->cmn.ldpc_en = HT_LDPC_EN;
-+			else
-+				psta->cmn.ldpc_en = 0;
-+
-+			if (TEST_FLAG(psta->htpriv.stbc_cap, STBC_HT_ENABLE_TX))
-+				psta->cmn.stbc_en = HT_STBC_EN;
-+			else
-+				psta->cmn.stbc_en = 0;
-+		} else {
-+			psta->cmn.ldpc_en = 0;
-+			psta->cmn.stbc_en = 0;
-+		}
-+
-+#endif /* CONFIG_80211N_HT */
-+}
-+
-+int check_ielen(u8 *start, uint len)
-+{
-+	int left = len;
-+	u8 *pos = start;
-+	u8 id, elen;
-+
-+	while (left >= 2) {
-+		id = *pos++;
-+		elen = *pos++;
-+		left -= 2;
-+
-+		if (elen > left) {
-+			RTW_INFO("IEEE 802.11 element parse failed (id=%d elen=%d left=%lu)\n",
-+					id, elen, (unsigned long) left);
-+			return _FALSE;
-+		}
-+		if ((id == WLAN_EID_VENDOR_SPECIFIC) && (elen < 3))
-+				return _FALSE;
-+
-+		left -= elen;
-+		pos += elen;
-+	}
-+	if (left)
-+		return _FALSE;
-+
-+	return _TRUE;
-+}
-+
-+int validate_beacon_len(u8 *pframe, u32 len)
-+{
-+	u8 ie_offset = _BEACON_IE_OFFSET_ + sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	if (len < ie_offset) {
-+		RTW_INFO("%s: incorrect beacon length(%d)\n", __func__, len);
-+		return _FALSE;
-+	}
-+
-+	if (check_ielen(pframe + ie_offset, len - ie_offset) == _FALSE)
-+		return _FALSE;
-+
-+	return _TRUE;
-+}
-+
-+#ifdef CONFIG_CHECK_SPECIFIC_IE_CONTENT
-+u8 support_rate_ranges[] = {
-+	IEEE80211_CCK_RATE_1MB,
-+	IEEE80211_CCK_RATE_2MB,
-+	IEEE80211_CCK_RATE_5MB,
-+	IEEE80211_CCK_RATE_11MB,
-+	IEEE80211_OFDM_RATE_6MB,
-+	IEEE80211_OFDM_RATE_9MB,
-+	IEEE80211_OFDM_RATE_12MB,
-+	IEEE80211_OFDM_RATE_18MB,
-+	IEEE80211_PBCC_RATE_22MB,
-+	IEEE80211_FREAK_RATE_22_5MB,
-+	IEEE80211_OFDM_RATE_24MB,
-+	IEEE80211_OFDM_RATE_36MB,
-+	IEEE80211_OFDM_RATE_48MB,
-+	IEEE80211_OFDM_RATE_54MB,
-+};
-+
-+inline bool match_ranges(u16 EID, u32 value)
-+{
-+	int i;
-+	int nr_range;
-+
-+	switch (EID) {
-+	case _EXT_SUPPORTEDRATES_IE_:
-+	case _SUPPORTEDRATES_IE_:
-+		nr_range = sizeof(support_rate_ranges)/sizeof(u8);
-+		for (i = 0; i < nr_range; i++) {
-+			/*	clear bit7 before searching.	*/
-+			value &= ~BIT(7);
-+			if (value == support_rate_ranges[i])
-+				return _TRUE;
-+		}
-+		break;
-+	default:
-+		break;
-+	};
-+	return _FALSE;
-+}
-+
-+/*
-+ * rtw_validate_value: validate the IE contain.
-+ *
-+ *	Input : 
-+ *		EID : Element ID
-+ *		p	: IE buffer (without EID & length)
-+ *		len	: IE length
-+ *	return: 
-+ * 		_TRUE	: All Values are validated.
-+ *		_FALSE	: At least one value is NOT validated.
-+ */
-+bool rtw_validate_value(u16 EID, u8 *p, u16 len)
-+{
-+	u8 rate;
-+	u32 i, nr_val;
-+
-+	switch (EID) {
-+	case _EXT_SUPPORTEDRATES_IE_:
-+	case _SUPPORTEDRATES_IE_:
-+		nr_val = len;
-+		for (i=0; i<nr_val; i++) {
-+			rate = *(p+i);
-+			if (match_ranges(EID, rate) == _FALSE)
-+				return _FALSE;
-+		}
-+		break;
-+	default:
-+		break;
-+	};
-+	return _TRUE;
-+}
-+#endif /* CONFIG_CHECK_SPECIFIC_IE_CONTENT */
-+
-+bool is_hidden_ssid(char *ssid, int len)
-+{
-+	return len == 0 || is_all_null(ssid, len) == _TRUE;
-+}
-+
-+inline bool hidden_ssid_ap(WLAN_BSSID_EX *snetwork)
-+{
-+	return is_hidden_ssid(snetwork->Ssid.Ssid, snetwork->Ssid.SsidLength);
-+}
-+
-+/*
-+	Get SSID if this ilegal frame(probe resp) comes from a hidden SSID AP.
-+	Update the SSID to the corresponding pnetwork in scan queue.
-+*/
-+void rtw_absorb_ssid_ifneed(_adapter *padapter, WLAN_BSSID_EX *bssid, u8 *pframe)
-+{
-+	struct wlan_network *scanned = NULL;
-+	WLAN_BSSID_EX	*snetwork;
-+	u8 ie_offset, *p=NULL, *next_ie=NULL, *mac = get_addr2_ptr(pframe);
-+	sint ssid_len_ori;
-+	u32 remain_len = 0;
-+	u8 backupIE[MAX_IE_SZ];
-+	u16 subtype = get_frame_sub_type(pframe);
-+	_irqL irqL;
-+
-+	if (subtype == WIFI_BEACON) {
-+		bssid->Reserved[0] = BSS_TYPE_BCN;
-+		ie_offset = _BEACON_IE_OFFSET_;
-+	} else {
-+		/* FIXME : more type */
-+		if (subtype == WIFI_PROBERSP) {
-+			ie_offset = _PROBERSP_IE_OFFSET_;
-+			bssid->Reserved[0] = BSS_TYPE_PROB_RSP;
-+		} else if (subtype == WIFI_PROBEREQ) {
-+			ie_offset = _PROBEREQ_IE_OFFSET_;
-+			bssid->Reserved[0] = BSS_TYPE_PROB_REQ;
-+		} else {
-+			bssid->Reserved[0] = BSS_TYPE_UNDEF;
-+			ie_offset = _FIXED_IE_LENGTH_;
-+		}
-+	}
-+	
-+	_enter_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);
-+	scanned = _rtw_find_network(&padapter->mlmepriv.scanned_queue, mac);
-+	if (!scanned) {
-+		_exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);
-+		return;
-+	}
-+
-+	snetwork = &(scanned->network);
-+	/* scan queue records as Hidden SSID && Input frame is NOT Hidden SSID	*/
-+	if (hidden_ssid_ap(snetwork) && !hidden_ssid_ap(bssid)) {
-+		p = rtw_get_ie(snetwork->IEs+ie_offset, _SSID_IE_, &ssid_len_ori, snetwork->IELength-ie_offset);
-+		if (!p) {
-+			_exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);
-+			return;
-+		}
-+		next_ie = p + 2 + ssid_len_ori;
-+		remain_len = snetwork->IELength - (next_ie - snetwork->IEs);
-+		scanned->network.Ssid.SsidLength = bssid->Ssid.SsidLength;
-+		_rtw_memcpy(scanned->network.Ssid.Ssid, bssid->Ssid.Ssid, bssid->Ssid.SsidLength);
-+
-+		//update pnetwork->ssid, pnetwork->ssidlen
-+		_rtw_memcpy(backupIE, next_ie, remain_len);
-+		*(p+1) = bssid->Ssid.SsidLength;
-+		_rtw_memcpy(p+2, bssid->Ssid.Ssid, bssid->Ssid.SsidLength);
-+		_rtw_memcpy(p+2+bssid->Ssid.SsidLength, backupIE, remain_len);
-+		snetwork->IELength += bssid->Ssid.SsidLength;
-+	}
-+	_exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL);
-+}
-+
-+#ifdef DBG_RX_BCN
-+void rtw_debug_rx_bcn(_adapter *adapter, u8 *pframe, u32 packet_len)
-+{
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info *mlmeinfo = &(pmlmeext->mlmext_info);
-+	u16 sn = ((struct rtw_ieee80211_hdr_3addr *)pframe)->seq_ctl >> 4;
-+	u64 tsf, tsf_offset;
-+	u8 dtim_cnt, dtim_period, tim_bmap, tim_pvbit;
-+
-+	update_TSF(pmlmeext, pframe, packet_len);
-+	tsf = pmlmeext->TSFValue;
-+	tsf_offset = rtw_modular64(pmlmeext->TSFValue, (mlmeinfo->bcn_interval * 1024));
-+
-+	/*get TIM IE*/
-+	/*DTIM Count*/
-+	dtim_cnt = pmlmeext->tim[0];
-+	/*DTIM Period*/
-+	dtim_period = pmlmeext->tim[1];
-+	/*Bitmap*/
-+	tim_bmap = pmlmeext->tim[2];
-+	/*Partial VBitmap AID 0 ~ 7*/
-+	tim_pvbit = pmlmeext->tim[3];
-+
-+	RTW_INFO("[BCN] SN-%d, TSF-%lld(us), offset-%lld, bcn_interval-%d DTIM-%d[%d] bitmap-0x%02x-0x%02x\n",
-+		sn, tsf, tsf_offset, mlmeinfo->bcn_interval, dtim_period, dtim_cnt, tim_bmap, tim_pvbit);
-+}
-+#endif
-+
-+/*
-+ * rtw_get_bcn_keys: get beacon keys from recv frame
-+ *
-+ * TODO:
-+ *	WLAN_EID_COUNTRY
-+ *	WLAN_EID_ERP_INFO
-+ *	WLAN_EID_CHANNEL_SWITCH
-+ *	WLAN_EID_PWR_CONSTRAINT
-+ */
-+int _rtw_get_bcn_keys(u8 *cap_info, u32 buf_len, u8 def_ch, ADAPTER *adapter
-+	, struct beacon_keys *recv_beacon)
-+{
-+	int left;
-+	u16 capability;
-+	unsigned char *pos;
-+	struct rtw_ieee802_11_elems elems;
-+
-+	_rtw_memset(recv_beacon, 0, sizeof(*recv_beacon));
-+
-+	/* checking capabilities */
-+	capability = le16_to_cpu(*(unsigned short *)(cap_info));
-+
-+	/* checking IEs */
-+	left = buf_len - 2;
-+	pos = cap_info + 2;
-+	if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed)
-+		return _FALSE;
-+
-+	if (elems.ht_capabilities) {
-+		if (elems.ht_capabilities_len != 26)
-+			return _FALSE;
-+	}
-+
-+	if (elems.ht_operation) {
-+		if (elems.ht_operation_len != 22)
-+			return _FALSE;
-+	}
-+
-+	if (elems.vht_capabilities) {
-+		if (elems.vht_capabilities_len != 12)
-+			return _FALSE;
-+	}
-+
-+	if (elems.vht_operation) {
-+		if (elems.vht_operation_len != 5)
-+			return _FALSE;
-+	}
-+
-+	if (rtw_ies_get_supported_rate(pos, left, recv_beacon->rate_set, &recv_beacon->rate_num) == _FAIL)
-+		return _FALSE;
-+
-+	if (cckratesonly_included(recv_beacon->rate_set, recv_beacon->rate_num) == _TRUE)
-+		recv_beacon->proto_cap |= PROTO_CAP_11B;
-+	else if (cckrates_included(recv_beacon->rate_set, recv_beacon->rate_num) == _TRUE)
-+		recv_beacon->proto_cap |= PROTO_CAP_11B | PROTO_CAP_11G;
-+	else
-+		recv_beacon->proto_cap |= PROTO_CAP_11G;
-+
-+	if (elems.ht_capabilities && elems.ht_operation)
-+		recv_beacon->proto_cap |= PROTO_CAP_11N;
-+
-+	if (elems.vht_capabilities && elems.vht_operation)
-+		recv_beacon->proto_cap |= PROTO_CAP_11AC;
-+
-+	/* check bw and channel offset */
-+	rtw_ies_get_chbw(pos, left, &recv_beacon->ch, &recv_beacon->bw, &recv_beacon->offset, 1, 1);
-+	if (!recv_beacon->ch)
-+		recv_beacon->ch = def_ch;
-+
-+	/* checking SSID */
-+	if (elems.ssid) {
-+		if (elems.ssid_len > sizeof(recv_beacon->ssid))
-+			return _FALSE;
-+
-+		_rtw_memcpy(recv_beacon->ssid, elems.ssid, elems.ssid_len);
-+		recv_beacon->ssid_len = elems.ssid_len;
-+	}
-+
-+	/* checking RSN first */
-+	if (elems.rsn_ie && elems.rsn_ie_len) {
-+		recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA2;
-+		rtw_parse_wpa2_ie(elems.rsn_ie - 2, elems.rsn_ie_len + 2,
-+			&recv_beacon->group_cipher, &recv_beacon->pairwise_cipher,
-+			NULL, &recv_beacon->akm, NULL);
-+	}
-+	/* checking WPA secon */
-+	else if (elems.wpa_ie && elems.wpa_ie_len) {
-+		recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA;
-+		rtw_parse_wpa_ie(elems.wpa_ie - 2, elems.wpa_ie_len + 2,
-+			&recv_beacon->group_cipher, &recv_beacon->pairwise_cipher,
-+				 &recv_beacon->akm);
-+	} else if (capability & BIT(4))
-+		recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WEP;
-+
-+	if (adapter) {
-+		struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+
-+		if (elems.tim && elems.tim_len) {
-+			#ifdef DBG_RX_BCN
-+			_rtw_memcpy(pmlmeext->tim, elems.tim, 4);
-+			#endif
-+			pmlmeext->dtim = elems.tim[1];
-+		}
-+
-+		/* checking RTW TBTX */
-+		#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+		if (elems.tbtx_cap && elems.tbtx_cap_len) {
-+			struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+			if (rtw_is_tbtx_capabilty(elems.tbtx_cap, elems.tbtx_cap_len))
-+				RTW_DBG("AP support TBTX\n");
-+		}
-+		#endif
-+	}
-+
-+	return _TRUE;
-+}
-+
-+int rtw_get_bcn_keys(_adapter *adapter, u8 *whdr, u32 flen, struct beacon_keys *bcn_keys)
-+{
-+	return _rtw_get_bcn_keys(
-+		whdr + WLAN_HDR_A3_LEN + 10
-+		, flen - WLAN_HDR_A3_LEN - 10
-+		, adapter->mlmeextpriv.cur_channel, adapter
-+		, bcn_keys);
-+}
-+
-+int rtw_get_bcn_keys_from_bss(WLAN_BSSID_EX *bss, struct beacon_keys *bcn_keys)
-+{
-+	return _rtw_get_bcn_keys(
-+		bss->IEs + 10
-+		, bss->IELength - 10
-+		, bss->Configuration.DSConfig, NULL
-+		, bcn_keys);
-+}
-+
-+int rtw_update_bcn_keys_of_network(struct wlan_network *network)
-+{
-+	network->bcn_keys_valid = rtw_get_bcn_keys_from_bss(&network->network, &network->bcn_keys);
-+	return network->bcn_keys_valid;
-+}
-+
-+void rtw_dump_bcn_keys(void *sel, struct beacon_keys *recv_beacon)
-+{
-+#if defined(CONFIG_RTW_DEBUG) || defined(CONFIG_PROC_DEBUG)
-+	u8 ssid[IW_ESSID_MAX_SIZE + 1];
-+
-+	_rtw_memcpy(ssid, recv_beacon->ssid, recv_beacon->ssid_len);
-+	ssid[recv_beacon->ssid_len] = '\0';
-+
-+	RTW_PRINT_SEL(sel, "ssid = %s (len = %u)\n", ssid, recv_beacon->ssid_len);
-+	RTW_PRINT_SEL(sel, "ch = %u,%u,%u\n"
-+		, recv_beacon->ch, recv_beacon->bw, recv_beacon->offset);
-+	RTW_PRINT_SEL(sel, "proto_cap = 0x%02x\n", recv_beacon->proto_cap);
-+	RTW_MAP_DUMP_SEL(sel, "rate_set = "
-+		, recv_beacon->rate_set, recv_beacon->rate_num);
-+	RTW_PRINT_SEL(sel, "sec = %d, group = 0x%x, pair = 0x%x, akm = 0x%08x\n"
-+		, recv_beacon->encryp_protocol, recv_beacon->group_cipher
-+		, recv_beacon->pairwise_cipher, recv_beacon->akm);
-+#endif
-+}
-+
-+void rtw_bcn_key_err_fix(struct beacon_keys *cur, struct beacon_keys *recv)
-+{
-+	if ((recv->ch == cur->ch) && (recv->bw == cur->bw) && (recv->bw > CHANNEL_WIDTH_20)) {
-+		if ((recv->offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) 
-+			&& (cur->offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE)) {
-+			RTW_DBG("recv_bcn offset = %d is invalid, try to use cur_bcn offset = %d to replace it !\n", recv->offset, cur->offset);
-+			recv->offset = cur->offset;
-+		}
-+	}
-+}
-+
-+bool rtw_bcn_key_compare(struct beacon_keys *cur, struct beacon_keys *recv)
-+{
-+#define BCNKEY_VERIFY_PROTO_CAP 0
-+#define BCNKEY_VERIFY_WHOLE_RATE_SET 0
-+
-+	struct beacon_keys tmp;
-+	bool ret = _FALSE;
-+
-+	if (!rtw_is_chbw_grouped(cur->ch, cur->bw, cur->offset
-+			, recv->ch, recv->bw, recv->offset))
-+		goto exit;
-+
-+	_rtw_memcpy(&tmp, cur, sizeof(tmp));
-+
-+	/* check fields excluding below */
-+	tmp.ch = recv->ch;
-+	tmp.bw = recv->bw;
-+	tmp.offset = recv->offset;
-+	if (!BCNKEY_VERIFY_PROTO_CAP)
-+		tmp.proto_cap = recv->proto_cap;
-+	if (!BCNKEY_VERIFY_WHOLE_RATE_SET) {
-+		tmp.rate_num = recv->rate_num;
-+		_rtw_memcpy(tmp.rate_set, recv->rate_set, 12);
-+	}
-+
-+	if (_rtw_memcmp(&tmp, recv, sizeof(*recv)) == _FALSE)
-+		goto exit;
-+
-+	ret = _TRUE;
-+
-+exit:
-+	return ret;
-+}
-+
-+int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len)
-+{
-+	u8 *pbssid = GetAddr3Ptr(pframe);
-+	struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
-+	struct wlan_network *cur_network = &(Adapter->mlmepriv.cur_network);
-+	struct beacon_keys *cur_beacon = &pmlmepriv->cur_beacon_keys;
-+	struct beacon_keys recv_beacon;
-+	int ret = 0;
-+	u8 ifbmp_m = rtw_mi_get_ap_mesh_ifbmp(Adapter);
-+	u8 ifbmp_s = rtw_mi_get_ld_sta_ifbmp(Adapter);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
-+	_adapter *pri_adapter = dvobj_get_primary_adapter(dvobj);
-+	struct mlme_ext_priv *pmlmeext = &pri_adapter->mlmeextpriv;
-+
-+	if (is_client_associated_to_ap(Adapter) == _FALSE)
-+		goto exit_success;
-+
-+	if (rtw_get_bcn_keys(Adapter, pframe, packet_len, &recv_beacon) == _FALSE)
-+		goto exit_success; /* parsing failed => broken IE */
-+
-+#ifdef DBG_RX_BCN
-+	rtw_debug_rx_bcn(Adapter, pframe, packet_len);
-+#endif
-+
-+	/* hidden ssid, replace with current beacon ssid directly */
-+	if (is_hidden_ssid(recv_beacon.ssid, recv_beacon.ssid_len)) {
-+		_rtw_memcpy(recv_beacon.ssid, cur_beacon->ssid, cur_beacon->ssid_len);
-+		recv_beacon.ssid_len = cur_beacon->ssid_len;
-+	}
-+
-+	if (check_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON)) {
-+		u8 u_ch, u_offset, u_bw;
-+		struct sta_info	*psta = NULL;
-+		_rtw_memcpy(cur_beacon, &recv_beacon, sizeof(recv_beacon));
-+		clr_fwstate(pmlmepriv, WIFI_CSA_UPDATE_BEACON);
-+		rtw_mi_get_ch_setting_union(Adapter, &u_ch, &u_bw, &u_offset);
-+		
-+		/* RTW_INFO("u_ch=%d, u_bw=%d, u_offset=%d \n", u_ch, u_bw, u_offset);
-+		RTW_INFO("recv_beacon.ch=%d, recv_beacon.bw=%d, recv_beacon.offset=%d \n", recv_beacon.ch, recv_beacon.bw, recv_beacon.offset); */
-+		/* rtw_dump_bcn_keys(RTW_DBGDUMP, &recv_beacon); */
-+		
-+		/* RTW_INFO("_cancel_timer_async csa_timer\n"); */
-+		_cancel_timer_async(&pmlmeext->csa_timer);
-+		
-+		/* beacon bw/offset is different from CSA IE */
-+		if((recv_beacon.bw > u_bw) || 
-+			((recv_beacon.offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE) && ((u_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE))
-+			&& (recv_beacon.offset != u_offset))) {
-+			
-+			/*  update ch, bw, offset for all asoc STA ifaces */
-+			if (ifbmp_s) {
-+				_adapter *iface;
-+				int i;
-+
-+				for (i = 0; i < dvobj->iface_nums; i++) {
-+					iface = dvobj->padapters[i];
-+					if (!iface || !(ifbmp_s & BIT(iface->iface_id)))
-+						continue;
-+					
-+					iface->mlmeextpriv.cur_channel = recv_beacon.ch;
-+					iface->mlmeextpriv.cur_bwmode = recv_beacon.bw;
-+					iface->mlmeextpriv.cur_ch_offset = recv_beacon.offset;
-+					iface->mlmepriv.cur_network.network.Configuration.DSConfig = recv_beacon.ch;
-+				}
-+			}
-+			
-+#ifdef CONFIG_AP_MODE
-+			if (ifbmp_m) {
-+				rtw_change_bss_chbw_cmd(dvobj_get_primary_adapter(dvobj), 0
-+					, ifbmp_m, 0, recv_beacon.ch, REQ_BW_ORI, REQ_OFFSET_NONE);
-+			} else
-+#endif
-+			{
-+				#ifdef CONFIG_DFS_MASTER
-+				rtw_dfs_rd_en_decision(dvobj_get_primary_adapter(dvobj), MLME_OPCH_SWITCH, ifbmp_s);
-+				#endif
-+				rtw_set_chbw_cmd(Adapter, recv_beacon.ch, recv_beacon.bw, recv_beacon.offset, 0);
-+			}
-+			rtw_mi_get_ch_setting_union(Adapter, &u_ch, &u_bw, &u_offset);
-+		
-+			/* RTW_INFO("u_ch=%d, u_bw=%d, u_offset=%d \n", u_ch, u_bw, u_offset); */
-+		} else {
-+			RTW_INFO("u_ch=%d, u_bw=%d, u_offset=%d, recv_beacon.ch=%d, recv_beacon.bw=%d, recv_beacon.offset=%d\n"
-+			, u_ch, u_bw, u_offset, recv_beacon.ch, recv_beacon.bw, recv_beacon.offset);
-+		}
-+		
-+		rtw_iqk_cmd(Adapter, 0);
-+		psta = rtw_get_stainfo(&Adapter->stapriv, get_bssid(&Adapter->mlmepriv));
-+		if (psta)
-+			rtw_dm_ra_mask_wk_cmd(Adapter, (u8 *)psta);
-+		
-+	}
-+
-+#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
-+	if (_rtw_memcmp(&recv_beacon, cur_beacon, sizeof(recv_beacon)) == _TRUE)
-+		pmlmepriv->new_beacon_cnts = 0;
-+	else if ((pmlmepriv->new_beacon_cnts == 0) ||
-+		_rtw_memcmp(&recv_beacon, &pmlmepriv->new_beacon_keys, sizeof(recv_beacon)) == _FALSE) {
-+		RTW_DBG("%s: start new beacon (seq=%d)\n", __func__, GetSequence(pframe));
-+
-+		if (pmlmepriv->new_beacon_cnts == 0) {
-+			RTW_ERR("%s: cur beacon key\n", __func__);
-+			RTW_DBG_EXPR(rtw_dump_bcn_keys(RTW_DBGDUMP, cur_beacon));
-+		}
-+
-+		RTW_DBG("%s: new beacon key\n", __func__);
-+		RTW_DBG_EXPR(rtw_dump_bcn_keys(RTW_DBGDUMP, &recv_beacon));
-+
-+		_rtw_memcpy(&pmlmepriv->new_beacon_keys, &recv_beacon, sizeof(recv_beacon));
-+		pmlmepriv->new_beacon_cnts = 1;
-+	} else {
-+		RTW_DBG("%s: new beacon again (seq=%d)\n", __func__, GetSequence(pframe));
-+		pmlmepriv->new_beacon_cnts++;
-+	}
-+
-+	/* if counter >= max, it means beacon is changed really */
-+	if (pmlmepriv->new_beacon_cnts >= new_bcn_max)
-+#else
-+	if (_rtw_memcmp(&recv_beacon, cur_beacon, sizeof(recv_beacon)) == _FALSE)
-+#endif
-+	{
-+		RTW_INFO(FUNC_ADPT_FMT" new beacon occur!!\n", FUNC_ADPT_ARG(Adapter));
-+		RTW_INFO(FUNC_ADPT_FMT" cur beacon key:\n", FUNC_ADPT_ARG(Adapter));
-+		rtw_dump_bcn_keys(RTW_DBGDUMP, cur_beacon);
-+		RTW_INFO(FUNC_ADPT_FMT" new beacon key:\n", FUNC_ADPT_ARG(Adapter));
-+		rtw_dump_bcn_keys(RTW_DBGDUMP, &recv_beacon);
-+
-+		rtw_bcn_key_err_fix(cur_beacon, &recv_beacon);
-+
-+		if (rtw_bcn_key_compare(cur_beacon, &recv_beacon) == _FALSE)
-+			goto exit;
-+
-+		_rtw_memcpy(cur_beacon, &recv_beacon, sizeof(recv_beacon));
-+		#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
-+		pmlmepriv->new_beacon_cnts = 0;
-+		#endif
-+	}
-+
-+exit_success:
-+	ret = 1;
-+
-+exit:
-+	return ret;
-+}
-+
-+void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta_info *psta)
-+{
-+	unsigned int i;
-+	unsigned int len;
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+
-+#ifdef CONFIG_TDLS
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	u8 tdls_prohibited[] = { 0x00, 0x00, 0x00, 0x00, 0x10 }; /* bit(38): TDLS_prohibited */
-+#endif /* CONFIG_TDLS */
-+
-+	len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN);
-+
-+	for (i = 0; i < len;) {
-+		pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i);
-+
-+		switch (pIE->ElementID) {
-+		case _VENDOR_SPECIFIC_IE_:
-+			/* to update WMM paramter set while receiving beacon */
-+			if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6) && pIE->Length == WLAN_WMM_LEN)	/* WMM */
-+				(WMM_param_handler(padapter, pIE)) ? report_wmm_edca_update(padapter) : 0;
-+
-+			break;
-+
-+		case _HT_EXTRA_INFO_IE_:	/* HT info */
-+			/* HT_info_handler(padapter, pIE); */
-+			bwmode_update_check(padapter, pIE);
-+			break;
-+#ifdef CONFIG_80211AC_VHT
-+		case EID_OpModeNotification:
-+			rtw_process_vht_op_mode_notify(padapter, pIE->data, psta);
-+			break;
-+#endif /* CONFIG_80211AC_VHT */
-+		case _ERPINFO_IE_:
-+			ERP_IE_handler(padapter, pIE);
-+			VCS_update(padapter, psta);
-+			break;
-+
-+#ifdef CONFIG_TDLS
-+		case _EXT_CAP_IE_:
-+			if (check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE)
-+				ptdlsinfo->ap_prohibited = _TRUE;
-+			if (check_ap_tdls_ch_switching_prohibited(pIE->data, pIE->Length) == _TRUE)
-+				ptdlsinfo->ch_switch_prohibited = _TRUE;
-+			break;
-+#endif /* CONFIG_TDLS */
-+		default:
-+			break;
-+		}
-+
-+		i += (pIE->Length + 2);
-+	}
-+}
-+
-+#if CONFIG_DFS
-+void process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+		struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	unsigned int i, j, countdown;
-+	PNDIS_802_11_VARIABLE_IEs	pIE, sub_pie;
-+	u8 ch = 0, csa_ch_offset = 0, csa_ch_width = 0, csa_ch_freq_seg0 = 0, csa_ch_freq_seg1 = 0, csa_switch_cnt = 0;
-+
-+	/* TODO: compare with scheduling CSA */
-+	if (rfctl->csa_ch)
-+		return;
-+
-+	for (i = 0; i + 1 < ies_len;) {
-+		pIE = (PNDIS_802_11_VARIABLE_IEs)(ies + i);
-+
-+		switch (pIE->ElementID) {
-+		case _CH_SWTICH_ANNOUNCE_:
-+			ch = *(pIE->data + 1);
-+			csa_switch_cnt = *(pIE->data + 2);
-+			break;
-+		case WLAN_EID_SECONDARY_CHANNEL_OFFSET:
-+			csa_ch_offset = *(pIE->data);
-+			break;
-+		case WLAN_EID_WIDE_BANDWIDTH_CHANNEL_SWITCH:
-+			csa_ch_width = *(pIE->data);
-+			csa_ch_freq_seg0 = *(pIE->data+1);
-+			csa_ch_freq_seg1 = *(pIE->data+2);
-+			/* RTW_INFO("bw:%02x center_freq_0:%d center_freq_1:%d, ch=%d\n"
-+					, csa_ch_width, csa_ch_freq_seg0, csa_ch_freq_seg1, ch); */
-+			break;
-+		case WLAN_EID_CHANNEL_SWITCH_WRAPPER:
-+			for(j=0; j + 1 < pIE->Length;) {
-+				sub_pie = (PNDIS_802_11_VARIABLE_IEs)(ies + i + j + 2);
-+				if(sub_pie->ElementID == WLAN_EID_WIDE_BANDWIDTH_CHANNEL_SWITCH) {
-+					csa_ch_width = *(sub_pie->data);
-+					csa_ch_freq_seg0 = *(sub_pie->data+1);
-+					csa_ch_freq_seg1 = *(sub_pie->data+2);
-+					/* RTW_INFO("2. sub_IE:%02x IE_length:%02x bw:%02x center_freq_0:%d center_freq_1:%d, ch=%d\n"
-+					, sub_pie->ElementID, sub_pie->Length, csa_ch_width, csa_ch_freq_seg0, csa_ch_freq_seg1, ch); */
-+				}
-+				j += (sub_pie->Length + 2);
-+			}
-+			
-+			break;
-+		default:
-+			break;
-+		}
-+
-+		i += (pIE->Length + 2);
-+	}
-+
-+	if (ch != 0) {
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+		_adapter *pri_adapter = dvobj_get_primary_adapter(dvobj);
-+		
-+		rfctl->csa_ch = ch;
-+		rfctl->csa_switch_cnt = csa_switch_cnt;
-+		rfctl->csa_ch_offset = csa_ch_offset;
-+		rfctl->csa_ch_width = csa_ch_width;
-+		rfctl->csa_ch_freq_seg0 = csa_ch_freq_seg0;
-+		rfctl->csa_ch_freq_seg1 = csa_ch_freq_seg1;
-+		
-+		countdown = pmlmeinfo->network.Configuration.BeaconPeriod * (csa_switch_cnt+1); /* ms */
-+		RTW_INFO("csa: set countdown timer to %d ms\n", countdown);
-+		_set_timer(&pri_adapter->mlmeextpriv.csa_timer, countdown);
-+
-+	}
-+}
-+#endif /* CONFIG_DFS */
-+
-+enum eap_type parsing_eapol_packet(_adapter *padapter, u8 *key_payload, struct sta_info *psta, u8 trx_type)
-+{
-+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
-+	struct ieee802_1x_hdr *hdr;
-+	struct wpa_eapol_key *key;
-+	u16 key_info, key_data_length;
-+	char *trx_msg = trx_type ? "send" : "recv";
-+	enum eap_type eapol_type;
-+
-+	hdr = (struct ieee802_1x_hdr *) key_payload;
-+
-+	 /* WPS - eapol start packet */
-+	if (hdr->type == 1 && hdr->length == 0) {
-+		RTW_INFO("%s eapol start packet\n", trx_msg);
-+		return EAPOL_START;
-+	}
-+
-+	if (hdr->type == 0) { /* WPS - eapol packet */
-+		RTW_INFO("%s eapol packet\n", trx_msg);
-+		return EAPOL_PACKET;
-+	}
-+
-+	key = (struct wpa_eapol_key *) (hdr + 1);
-+	key_info = be16_to_cpu(*((u16 *)(key->key_info)));
-+	key_data_length = be16_to_cpu(*((u16 *)(key->key_data_length)));
-+
-+	if (!(key_info & WPA_KEY_INFO_KEY_TYPE)) { /* WPA group key handshake */
-+		if (key_info & WPA_KEY_INFO_ACK) {
-+			RTW_PRINT("%s eapol packet - WPA Group Key 1/2\n", trx_msg);
-+			eapol_type = EAPOL_WPA_GROUP_KEY_1_2;
-+		} else {
-+			RTW_PRINT("%s eapol packet - WPA Group Key 2/2\n", trx_msg);
-+			eapol_type = EAPOL_WPA_GROUP_KEY_2_2;
-+
-+			/* WPA key-handshake has completed */
-+			if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK)
-+				psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE);
-+		}
-+	} else if (key_info & WPA_KEY_INFO_MIC) {
-+		if (key_data_length == 0) {
-+			RTW_PRINT("%s eapol packet 4/4\n", trx_msg);
-+			eapol_type = EAPOL_4_4;
-+		} else if (key_info & WPA_KEY_INFO_ACK) {
-+			RTW_PRINT("%s eapol packet 3/4\n", trx_msg);
-+			eapol_type = EAPOL_3_4;
-+		} else {
-+			RTW_PRINT("%s eapol packet 2/4\n", trx_msg);
-+			eapol_type = EAPOL_2_4;
-+		}
-+	} else {
-+		RTW_PRINT("%s eapol packet 1/4\n", trx_msg);
-+		eapol_type = EAPOL_1_4;
-+	}
-+
-+	return eapol_type;
-+}
-+
-+unsigned int is_ap_in_tkip(_adapter *padapter)
-+{
-+	u32 i;
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
-+
-+	if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) {
-+		for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) {
-+			pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);
-+
-+			switch (pIE->ElementID) {
-+			case _VENDOR_SPECIFIC_IE_:
-+				if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) && (_rtw_memcmp((pIE->data + 12), WPA_TKIP_CIPHER, 4)))
-+					return _TRUE;
-+				break;
-+
-+			case _RSN_IE_2_:
-+				if (_rtw_memcmp((pIE->data + 8), RSN_TKIP_CIPHER, 4))
-+					return _TRUE;
-+
-+			default:
-+				break;
-+			}
-+
-+			i += (pIE->Length + 2);
-+		}
-+
-+		return _FALSE;
-+	} else
-+		return _FALSE;
-+
-+}
-+
-+unsigned int should_forbid_n_rate(_adapter *padapter)
-+{
-+	u32 i;
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	WLAN_BSSID_EX  *cur_network = &pmlmepriv->cur_network.network;
-+
-+	if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) {
-+		for (i = sizeof(NDIS_802_11_FIXED_IEs); i < cur_network->IELength;) {
-+			pIE = (PNDIS_802_11_VARIABLE_IEs)(cur_network->IEs + i);
-+
-+			switch (pIE->ElementID) {
-+			case _VENDOR_SPECIFIC_IE_:
-+				if (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4) &&
-+				    ((_rtw_memcmp((pIE->data + 12), WPA_CIPHER_SUITE_CCMP, 4)) ||
-+				     (_rtw_memcmp((pIE->data + 16), WPA_CIPHER_SUITE_CCMP, 4))))
-+					return _FALSE;
-+				break;
-+
-+			case _RSN_IE_2_:
-+				if ((_rtw_memcmp((pIE->data + 8), RSN_CIPHER_SUITE_CCMP, 4))  ||
-+				    (_rtw_memcmp((pIE->data + 12), RSN_CIPHER_SUITE_CCMP, 4)))
-+					return _FALSE;
-+
-+			default:
-+				break;
-+			}
-+
-+			i += (pIE->Length + 2);
-+		}
-+
-+		return _TRUE;
-+	} else
-+		return _FALSE;
-+
-+}
-+
-+
-+unsigned int is_ap_in_wep(_adapter *padapter)
-+{
-+	u32 i;
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
-+
-+	if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) {
-+		for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) {
-+			pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);
-+
-+			switch (pIE->ElementID) {
-+			case _VENDOR_SPECIFIC_IE_:
-+				if (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4))
-+					return _FALSE;
-+				break;
-+
-+			case _RSN_IE_2_:
-+				return _FALSE;
-+
-+			default:
-+				break;
-+			}
-+
-+			i += (pIE->Length + 2);
-+		}
-+
-+		return _TRUE;
-+	} else
-+		return _FALSE;
-+
-+}
-+
-+int wifirate2_ratetbl_inx(unsigned char rate);
-+int wifirate2_ratetbl_inx(unsigned char rate)
-+{
-+	int	inx = 0;
-+	rate = rate & 0x7f;
-+
-+	switch (rate) {
-+	case 54*2:
-+		inx = 11;
-+		break;
-+
-+	case 48*2:
-+		inx = 10;
-+		break;
-+
-+	case 36*2:
-+		inx = 9;
-+		break;
-+
-+	case 24*2:
-+		inx = 8;
-+		break;
-+
-+	case 18*2:
-+		inx = 7;
-+		break;
-+
-+	case 12*2:
-+		inx = 6;
-+		break;
-+
-+	case 9*2:
-+		inx = 5;
-+		break;
-+
-+	case 6*2:
-+		inx = 4;
-+		break;
-+
-+	case 11*2:
-+		inx = 3;
-+		break;
-+	case 11:
-+		inx = 2;
-+		break;
-+
-+	case 2*2:
-+		inx = 1;
-+		break;
-+
-+	case 1*2:
-+		inx = 0;
-+		break;
-+
-+	}
-+	return inx;
-+}
-+
-+unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz)
-+{
-+	unsigned int i, num_of_rate;
-+	unsigned int mask = 0;
-+
-+	num_of_rate = (ptn_sz > NumRates) ? NumRates : ptn_sz;
-+
-+	for (i = 0; i < num_of_rate; i++) {
-+		if ((*(ptn + i)) & 0x80)
-+			mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i));
-+	}
-+	return mask;
-+}
-+
-+unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz)
-+{
-+	unsigned int i, num_of_rate;
-+	unsigned int mask = 0;
-+
-+	num_of_rate = (ptn_sz > NumRates) ? NumRates : ptn_sz;
-+
-+	for (i = 0; i < num_of_rate; i++)
-+		mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i));
-+
-+	return mask;
-+}
-+
-+int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode)
-+{
-+	unsigned char					bit_offset;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	if (!(pmlmeinfo->HT_enable))
-+		return _FAIL;
-+
-+	bit_offset = (bwmode & CHANNEL_WIDTH_40) ? 6 : 5;
-+
-+	if (pHT_caps->u.HT_cap_element.HT_caps_info & (0x1 << bit_offset))
-+		return _SUCCESS;
-+	else
-+		return _FAIL;
-+}
-+
-+unsigned char get_highest_rate_idx(u64 mask)
-+{
-+	int i;
-+	unsigned char rate_idx = 0;
-+
-+	for (i = 63; i >= 0; i--) {
-+		if ((mask >> i) & 0x01) {
-+			rate_idx = i;
-+			break;
-+		}
-+	}
-+
-+	return rate_idx;
-+}
-+unsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit)
-+{
-+	int i;
-+	unsigned char rate_idx = 0;
-+
-+	for (i = start_bit; i < 64; i++) {
-+		if ((mask >> i) & 0x01) {
-+			rate_idx = i;
-+			break;
-+		}
-+	}
-+
-+	return rate_idx;
-+}
-+
-+void Update_RA_Entry(_adapter *padapter, struct sta_info *psta)
-+{
-+	rtw_hal_update_ra_mask(psta);
-+}
-+
-+void set_sta_rate(_adapter *padapter, struct sta_info *psta)
-+{
-+	/* rate adaptive	 */
-+	rtw_hal_update_ra_mask(psta);
-+}
-+
-+/* Update RRSR and Rate for USERATE */
-+void update_tx_basic_rate(_adapter *padapter, u8 wirelessmode)
-+{
-+	NDIS_802_11_RATES_EX	supported_rates;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
-+
-+	/*	Added by Albert 2011/03/22 */
-+	/*	In the P2P mode, the driver should not support the b mode. */
-+	/*	So, the Tx packet shouldn't use the CCK rate */
-+	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
-+		return;
-+#endif /* CONFIG_P2P */
-+
-+	_rtw_memset(supported_rates, 0, NDIS_802_11_LENGTH_RATES_EX);
-+
-+	/* clear B mod if current channel is in 5G band, avoid tx cck rate in 5G band. */
-+	if (pmlmeext->cur_channel > 14)
-+		wirelessmode &= ~(WIRELESS_11B);
-+
-+	if ((wirelessmode & WIRELESS_11B) && (wirelessmode == WIRELESS_11B))
-+		_rtw_memcpy(supported_rates, rtw_basic_rate_cck, 4);
-+	else if (wirelessmode & WIRELESS_11B)
-+		_rtw_memcpy(supported_rates, rtw_basic_rate_mix, 7);
-+	else
-+		_rtw_memcpy(supported_rates, rtw_basic_rate_ofdm, 3);
-+
-+	if (wirelessmode & WIRELESS_11B)
-+		update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB);
-+	else
-+		update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB);
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, supported_rates);
-+}
-+
-+unsigned char check_assoc_AP(u8 *pframe, uint len)
-+{
-+	unsigned int	i;
-+	PNDIS_802_11_VARIABLE_IEs	pIE;
-+
-+	for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) {
-+		pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i);
-+
-+		switch (pIE->ElementID) {
-+		case _VENDOR_SPECIFIC_IE_:
-+			if ((_rtw_memcmp(pIE->data, ARTHEROS_OUI1, 3)) || (_rtw_memcmp(pIE->data, ARTHEROS_OUI2, 3))) {
-+				RTW_INFO("link to Artheros AP\n");
-+				return HT_IOT_PEER_ATHEROS;
-+			} else if ((_rtw_memcmp(pIE->data, BROADCOM_OUI1, 3))
-+				   || (_rtw_memcmp(pIE->data, BROADCOM_OUI2, 3))
-+				|| (_rtw_memcmp(pIE->data, BROADCOM_OUI3, 3))) {
-+				RTW_INFO("link to Broadcom AP\n");
-+				return HT_IOT_PEER_BROADCOM;
-+			} else if (_rtw_memcmp(pIE->data, MARVELL_OUI, 3)) {
-+				RTW_INFO("link to Marvell AP\n");
-+				return HT_IOT_PEER_MARVELL;
-+			} else if (_rtw_memcmp(pIE->data, RALINK_OUI, 3)) {
-+				RTW_INFO("link to Ralink AP\n");
-+				return HT_IOT_PEER_RALINK;
-+			} else if (_rtw_memcmp(pIE->data, CISCO_OUI, 3)) {
-+				RTW_INFO("link to Cisco AP\n");
-+				return HT_IOT_PEER_CISCO;
-+			} else if (_rtw_memcmp(pIE->data, REALTEK_OUI, 3)) {
-+				u32	Vender = HT_IOT_PEER_REALTEK;
-+
-+				if (pIE->Length >= 5) {
-+					if (pIE->data[4] == 1) {
-+						/* if(pIE->data[5] & RT_HT_CAP_USE_LONG_PREAMBLE) */
-+						/*	bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_LONG_PREAMBLE; */
-+
-+						if (pIE->data[5] & RT_HT_CAP_USE_92SE) {
-+							/* bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_92SE; */
-+							Vender = HT_IOT_PEER_REALTEK_92SE;
-+						}
-+					}
-+
-+					if (pIE->data[5] & RT_HT_CAP_USE_SOFTAP)
-+						Vender = HT_IOT_PEER_REALTEK_SOFTAP;
-+
-+					if (pIE->data[4] == 2) {
-+						if (pIE->data[6] & RT_HT_CAP_USE_JAGUAR_BCUT) {
-+							Vender = HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP;
-+							RTW_INFO("link to Realtek JAGUAR_BCUTAP\n");
-+						}
-+						if (pIE->data[6] & RT_HT_CAP_USE_JAGUAR_CCUT) {
-+							Vender = HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP;
-+							RTW_INFO("link to Realtek JAGUAR_CCUTAP\n");
-+						}
-+					}
-+				}
-+
-+				RTW_INFO("link to Realtek AP\n");
-+				return Vender;
-+			} else if (_rtw_memcmp(pIE->data, AIRGOCAP_OUI, 3)) {
-+				RTW_INFO("link to Airgo Cap\n");
-+				return HT_IOT_PEER_AIRGO;
-+			} else
-+				break;
-+
-+		default:
-+			break;
-+		}
-+
-+		i += (pIE->Length + 2);
-+	}
-+
-+	RTW_INFO("link to new AP\n");
-+	return HT_IOT_PEER_UNKNOWN;
-+}
-+
-+void get_assoc_AP_Vendor(char *vendor, u8 assoc_AP_vendor)
-+{
-+	switch (assoc_AP_vendor) {
-+	
-+	case HT_IOT_PEER_UNKNOWN:
-+	sprintf(vendor, "%s", "unknown");
-+	break;
-+
-+	case HT_IOT_PEER_REALTEK:
-+	case HT_IOT_PEER_REALTEK_92SE:
-+	case HT_IOT_PEER_REALTEK_SOFTAP:
-+	case HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP:
-+	case HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP:
-+
-+	sprintf(vendor, "%s", "Realtek");
-+	break;
-+
-+	case HT_IOT_PEER_BROADCOM:
-+	sprintf(vendor, "%s", "Broadcom");
-+	break;
-+
-+	case HT_IOT_PEER_MARVELL:
-+	sprintf(vendor, "%s", "Marvell");
-+	break;
-+
-+	case HT_IOT_PEER_RALINK:
-+	sprintf(vendor, "%s", "Ralink");
-+	break;
-+
-+	case HT_IOT_PEER_CISCO:
-+	sprintf(vendor, "%s", "Cisco");
-+	break;
-+
-+	case HT_IOT_PEER_AIRGO:
-+	sprintf(vendor, "%s", "Airgo");
-+	break;
-+
-+	case HT_IOT_PEER_ATHEROS:
-+	sprintf(vendor, "%s", "Atheros");
-+	break;
-+
-+	default:
-+	sprintf(vendor, "%s", "unkown");
-+	break;
-+	}
-+
-+}
-+#ifdef CONFIG_RTS_FULL_BW
-+void rtw_parse_sta_vendor_ie_8812(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len)
-+{
-+	unsigned char REALTEK_OUI[] = {0x00,0xe0, 0x4c};
-+	u8 *p;
-+
-+	p = rtw_get_ie_ex(tlv_ies, tlv_ies_len, WLAN_EID_VENDOR_SPECIFIC, REALTEK_OUI, 3, NULL, NULL);
-+	if (!p)
-+		goto exit;
-+	else {
-+		if(*(p+1) > 6 ) {
-+
-+			if(*(p+6) != 2)
-+				goto exit;
-+			
-+			if(*(p+8) == RT_HT_CAP_USE_JAGUAR_BCUT)
-+				sta->vendor_8812 = TRUE;
-+			else if (*(p+8) == RT_HT_CAP_USE_JAGUAR_CCUT)
-+				sta->vendor_8812 = TRUE;
-+		}
-+	}
-+exit:
-+	return;
-+}
-+#endif/*CONFIG_RTS_FULL_BW*/
-+
-+#ifdef CONFIG_80211AC_VHT
-+void get_vht_bf_cap(u8 *pframe, uint len, struct vht_bf_cap *bf_cap)
-+{
-+	unsigned int i;
-+	PNDIS_802_11_VARIABLE_IEs pIE;
-+
-+	for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) {
-+		pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i);
-+
-+		switch (pIE->ElementID) {
-+
-+		case EID_VHTCapability:
-+			bf_cap->is_mu_bfer = GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data);
-+			bf_cap->su_sound_dim = GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data);
-+			break;
-+		default:
-+			break;
-+		}
-+		i += (pIE->Length + 2);
-+	}
-+}
-+#endif
-+
-+void update_capinfo(PADAPTER Adapter, u16 updateCap)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	BOOLEAN		ShortPreamble;
-+
-+	/* Check preamble mode, 2005.01.06, by rcnjko. */
-+	/* Mark to update preamble value forever, 2008.03.18 by lanhsin */
-+	/* if( pMgntInfo->RegPreambleMode == PREAMBLE_AUTO ) */
-+	{
-+
-+		if (updateCap & cShortPreamble) {
-+			/* Short Preamble */
-+			if (pmlmeinfo->preamble_mode != PREAMBLE_SHORT) { /* PREAMBLE_LONG or PREAMBLE_AUTO */
-+				ShortPreamble = _TRUE;
-+				pmlmeinfo->preamble_mode = PREAMBLE_SHORT;
-+				rtw_hal_set_hwreg(Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble);
-+			}
-+		} else {
-+			/* Long Preamble */
-+			if (pmlmeinfo->preamble_mode != PREAMBLE_LONG) { /* PREAMBLE_SHORT or PREAMBLE_AUTO */
-+				ShortPreamble = _FALSE;
-+				pmlmeinfo->preamble_mode = PREAMBLE_LONG;
-+				rtw_hal_set_hwreg(Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble);
-+			}
-+		}
-+	}
-+
-+	if (updateCap & cIBSS) {
-+		/* Filen: See 802.11-2007 p.91 */
-+		pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;
-+	} else {
-+		/* Filen: See 802.11-2007 p.90 */
-+		if (pmlmeext->cur_wireless_mode & (WIRELESS_11_24N | WIRELESS_11A | WIRELESS_11_5N | WIRELESS_11AC))
-+			pmlmeinfo->slotTime = SHORT_SLOT_TIME;
-+		else if (pmlmeext->cur_wireless_mode & (WIRELESS_11G)) {
-+			if ((updateCap & cShortSlotTime) /* && (!(pMgntInfo->pHTInfo->RT2RT_HT_Mode & RT_HT_CAP_USE_LONG_PREAMBLE)) */) {
-+				/* Short Slot Time */
-+				pmlmeinfo->slotTime = SHORT_SLOT_TIME;
-+			} else {
-+				/* Long Slot Time */
-+				pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;
-+			}
-+		} else {
-+			/* B Mode */
-+			pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME;
-+		}
-+	}
-+
-+	rtw_hal_set_hwreg(Adapter, HW_VAR_SLOT_TIME, &pmlmeinfo->slotTime);
-+
-+}
-+
-+/*
-+* set adapter.mlmeextpriv.mlmext_info.HT_enable
-+* set adapter.mlmeextpriv.cur_wireless_mode
-+* set SIFS register
-+* set mgmt tx rate
-+*/
-+void update_wireless_mode(_adapter *padapter)
-+{
-+	int ratelen, network_type = 0;
-+	u32 SIFS_Timer;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
-+	unsigned char			*rate = cur_network->SupportedRates;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+#endif /* CONFIG_P2P */
-+
-+	ratelen = rtw_get_rateset_len(cur_network->SupportedRates);
-+
-+	if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable))
-+		pmlmeinfo->HT_enable = 1;
-+
-+	if (pmlmeext->cur_channel > 14) {
-+		if (pmlmeinfo->VHT_enable)
-+			network_type = WIRELESS_11AC;
-+		else if (pmlmeinfo->HT_enable)
-+			network_type = WIRELESS_11_5N;
-+
-+		network_type |= WIRELESS_11A;
-+	} else {
-+		if (pmlmeinfo->VHT_enable)
-+			network_type = WIRELESS_11AC;
-+		else if (pmlmeinfo->HT_enable)
-+			network_type = WIRELESS_11_24N;
-+
-+		if ((cckratesonly_included(rate, ratelen)) == _TRUE)
-+			network_type |= WIRELESS_11B;
-+		else if ((cckrates_included(rate, ratelen)) == _TRUE)
-+			network_type |= WIRELESS_11BG;
-+		else
-+			network_type |= WIRELESS_11G;
-+	}
-+
-+	pmlmeext->cur_wireless_mode = network_type & padapter->registrypriv.wireless_mode;
-+	/* RTW_INFO("network_type=%02x, padapter->registrypriv.wireless_mode=%02x\n", network_type, padapter->registrypriv.wireless_mode); */
-+
-+#ifndef RTW_HALMAC
-+	/* HALMAC IC do not set HW_VAR_RESP_SIFS here */
-+#if 0
-+	if ((pmlmeext->cur_wireless_mode == WIRELESS_11G) ||
-+	    (pmlmeext->cur_wireless_mode == WIRELESS_11BG)) /* WIRELESS_MODE_G) */
-+		SIFS_Timer = 0x0a0a;/* CCK */
-+	else
-+		SIFS_Timer = 0x0e0e;/* pHalData->SifsTime; //OFDM */
-+#endif
-+
-+	SIFS_Timer = 0x0a0a0808; /* 0x0808->for CCK, 0x0a0a->for OFDM
-+                              * change this value if having IOT issues. */
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_RESP_SIFS, (u8 *)&SIFS_Timer);
-+#endif
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_WIRELESS_MODE, (u8 *)&(pmlmeext->cur_wireless_mode));
-+
-+	if ((pmlmeext->cur_wireless_mode & WIRELESS_11B)
-+		#ifdef CONFIG_P2P
-+		&& (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
-+			#ifdef CONFIG_IOCTL_CFG80211
-+			|| !rtw_cfg80211_iface_has_p2p_group_cap(padapter)
-+			#endif
-+			)
-+		#endif
-+	)
-+		update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB);
-+	else
-+		update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB);
-+}
-+
-+void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value);
-+void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value)
-+{
-+#if 0
-+	struct cmd_obj					*ph2c;
-+	struct reg_rw_parm			*pwriteMacPara;
-+	struct cmd_priv					*pcmdpriv = &(padapter->cmdpriv);
-+
-+	ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (ph2c == NULL)
-+		return;
-+
-+	pwriteMacPara = (struct reg_rw_parm *)rtw_malloc(sizeof(struct reg_rw_parm));
-+	if (pwriteMacPara == NULL) {
-+		rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
-+		return;
-+	}
-+
-+	pwriteMacPara->rw = 1;
-+	pwriteMacPara->addr = addr;
-+	pwriteMacPara->value = value;
-+
-+	init_h2fwcmd_w_parm_no_rsp(ph2c, pwriteMacPara, GEN_CMD_CODE(_Write_MACREG));
-+	rtw_enqueue_cmd(pcmdpriv, ph2c);
-+#endif
-+}
-+
-+void update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode)
-+{
-+	if (IsSupportedTxCCK(wireless_mode)) {
-+		/* Only B, B/G, and B/G/N AP could use CCK rate */
-+		_rtw_memcpy(psta->bssrateset, rtw_basic_rate_cck, 4);
-+		psta->bssratelen = 4;
-+	} else {
-+		_rtw_memcpy(psta->bssrateset, rtw_basic_rate_ofdm, 3);
-+		psta->bssratelen = 3;
-+	}
-+}
-+
-+int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num)
-+{
-+	u8 *ie, *p;
-+	unsigned int ie_len;
-+	int i, j;
-+
-+	struct support_rate_handler support_rate_tbl[] = {
-+		{IEEE80211_CCK_RATE_1MB, 		_FALSE,		_FALSE},
-+		{IEEE80211_CCK_RATE_2MB, 		_FALSE,		_FALSE},
-+		{IEEE80211_CCK_RATE_5MB, 		_FALSE,		_FALSE},
-+		{IEEE80211_CCK_RATE_11MB,		_FALSE,		_FALSE},
-+		{IEEE80211_OFDM_RATE_6MB,		_FALSE,		_FALSE},
-+		{IEEE80211_OFDM_RATE_9MB,		_FALSE,		_FALSE},
-+		{IEEE80211_OFDM_RATE_12MB,		_FALSE,		_FALSE},
-+		{IEEE80211_OFDM_RATE_18MB,		_FALSE,		_FALSE},
-+		{IEEE80211_OFDM_RATE_24MB,		_FALSE,		_FALSE},
-+		{IEEE80211_OFDM_RATE_36MB,		_FALSE,		_FALSE},
-+		{IEEE80211_OFDM_RATE_48MB,		_FALSE,		_FALSE},
-+		{IEEE80211_OFDM_RATE_54MB,		_FALSE,		_FALSE},
-+	};
-+		
-+	if (!rate_set || !rate_num)
-+		return _FALSE;
-+
-+	*rate_num = 0;
-+	ie = rtw_get_ie(ies, _SUPPORTEDRATES_IE_, &ie_len, ies_len);
-+	if (ie == NULL)
-+		goto ext_rate;
-+
-+	/* get valid supported rates */
-+	for (i = 0; i < 12; i++) {
-+		p = ie + 2;
-+		for (j = 0; j < ie_len; j++) {
-+			if ((*p & ~BIT(7)) == support_rate_tbl[i].rate){
-+				support_rate_tbl[i].existence = _TRUE;
-+				if ((*p) & BIT(7))
-+					support_rate_tbl[i].basic = _TRUE;
-+			}
-+			p++;
-+		}
-+	}
-+
-+ext_rate:
-+	ie = rtw_get_ie(ies, _EXT_SUPPORTEDRATES_IE_, &ie_len, ies_len);
-+	if (ie) {
-+		/* get valid extended supported rates */
-+		for (i = 0; i < 12; i++) {
-+			p = ie + 2;
-+			for (j = 0; j < ie_len; j++) {
-+				if ((*p & ~BIT(7)) == support_rate_tbl[i].rate){
-+					support_rate_tbl[i].existence = _TRUE;
-+					if ((*p) & BIT(7))
-+						support_rate_tbl[i].basic = _TRUE;
-+				}
-+				p++;
-+			}
-+		}
-+	}
-+
-+	for (i = 0; i < 12; i++){
-+		if (support_rate_tbl[i].existence){
-+			if (support_rate_tbl[i].basic)
-+				rate_set[*rate_num] = support_rate_tbl[i].rate | IEEE80211_BASIC_RATE_MASK;
-+			else
-+				rate_set[*rate_num] = support_rate_tbl[i].rate;
-+			*rate_num += 1;
-+		}
-+	}
-+
-+	if (*rate_num == 0)
-+		return _FAIL;
-+
-+	if (0) {
-+		int i;
-+
-+		for (i = 0; i < *rate_num; i++)
-+			RTW_INFO("rate:0x%02x\n", *(rate_set + i));
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr)
-+{
-+	struct sta_info *psta;
-+	u16 tid, start_seq, param;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct ADDBA_request	*preq = (struct ADDBA_request *)paddba_req;
-+	u8 size, accept = _FALSE;
-+
-+	psta = rtw_get_stainfo(pstapriv, addr);
-+	if (!psta)
-+		goto exit;
-+
-+	start_seq = le16_to_cpu(preq->BA_starting_seqctrl) >> 4;
-+
-+	param = le16_to_cpu(preq->BA_para_set);
-+	tid = (param >> 2) & 0x0f;
-+
-+
-+	accept = rtw_rx_ampdu_is_accept(padapter);
-+	if (padapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID)
-+		size = padapter->fix_rx_ampdu_size;
-+	else {
-+		size = rtw_rx_ampdu_size(padapter);
-+		size = rtw_min(size, rx_ampdu_size_sta_limit(padapter, psta));
-+	}
-+
-+	if (accept == _TRUE)
-+		rtw_addbarsp_cmd(padapter, addr, tid, 0, size, start_seq);
-+	else
-+		rtw_addbarsp_cmd(padapter, addr, tid, 37, size, start_seq); /* reject ADDBA Req */
-+
-+exit:
-+	return;
-+}
-+
-+void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	struct sta_info *psta = NULL;
-+	struct recv_reorder_ctrl *preorder_ctrl = NULL;
-+	u8 tid = 0;
-+	u16 start_seq=0;
-+
-+	psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
-+	if (psta == NULL)
-+		goto exit;
-+
-+	tid = ((cpu_to_le16((*(u16 *)(pframe + 16))) & 0xf000) >> 12);
-+	preorder_ctrl = &psta->recvreorder_ctrl[tid];
-+	start_seq = ((cpu_to_le16(*(u16 *)(pframe + 18))) >> 4);
-+	preorder_ctrl->indicate_seq = start_seq;
-+
-+	/* for Debug use */
-+	if (0)
-+		RTW_INFO(FUNC_ADPT_FMT" tid=%d, start_seq=%d\n", FUNC_ADPT_ARG(padapter),  tid, start_seq);
-+
-+exit:
-+	return;
-+}
-+
-+void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len)
-+{
-+	u8 *pIE;
-+	u32 *pbuf;
-+
-+	pIE = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pbuf = (u32 *)pIE;
-+
-+	pmlmeext->TSFValue = le32_to_cpu(*(pbuf + 1));
-+
-+	pmlmeext->TSFValue = pmlmeext->TSFValue << 32;
-+
-+	pmlmeext->TSFValue |= le32_to_cpu(*pbuf);
-+}
-+
-+void correct_TSF(_adapter *padapter, u8 mlme_state)
-+{
-+	u8 m_state = mlme_state;
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_CORRECT_TSF, (u8 *)&m_state);
-+}
-+
-+#ifdef CONFIG_BCN_RECV_TIME
-+/*	calculate beacon receiving time
-+	1.RxBCNTime(CCK_1M) = [192us(preamble)] + [length of beacon(byte)*8us] + [10us]
-+	2.RxBCNTime(OFDM_6M) = [8us(S) + 8us(L) + 4us(L-SIG)] + [(length of beacon(byte)/3 + 1] *4us] + [10us]
-+*/
-+inline u16 _rx_bcn_time_calculate(uint bcn_len, u8 data_rate)
-+{
-+	u16 rx_bcn_time = 0;/*us*/
-+
-+	if (data_rate == DESC_RATE1M)
-+		rx_bcn_time = 192 + bcn_len * 8 + 10;
-+	else if(data_rate == DESC_RATE6M)
-+		rx_bcn_time = 8 + 8 + 4 + (bcn_len /3 + 1) * 4 + 10;
-+/*
-+	else
-+		RTW_ERR("%s invalid data rate(0x%02x)\n", __func__, data_rate);
-+*/
-+	return rx_bcn_time;
-+}
-+void rtw_rx_bcn_time_update(_adapter *adapter, uint bcn_len, u8 data_rate)
-+{
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+
-+	pmlmeext->bcn_rx_time = _rx_bcn_time_calculate(bcn_len, data_rate);
-+}
-+#endif
-+
-+void beacon_timing_control(_adapter *padapter)
-+{
-+	rtw_hal_bcn_related_reg_setting(padapter);
-+}
-+
-+inline bool _rtw_macid_ctl_chk_cap(_adapter *adapter, u8 cap)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct macid_ctl_t *macid_ctl = &dvobj->macid_ctl;
-+
-+	if (macid_ctl->macid_cap & cap)
-+		return _TRUE;
-+	return _FALSE;
-+}
-+
-+void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num)
-+{
-+	RTW_PRINT_SEL(sel, "0x%08x\n", map->m0);
-+#if (MACID_NUM_SW_LIMIT > 32)
-+	if (max_num && max_num > 32)
-+		RTW_PRINT_SEL(sel, "0x%08x\n", map->m1);
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 64)
-+	if (max_num && max_num > 64)
-+		RTW_PRINT_SEL(sel, "0x%08x\n", map->m2);
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 96)
-+	if (max_num && max_num > 96)
-+		RTW_PRINT_SEL(sel, "0x%08x\n", map->m3);
-+#endif
-+}
-+
-+inline bool rtw_macid_is_set(struct macid_bmp *map, u8 id)
-+{
-+	if (id < 32)
-+		return map->m0 & BIT(id);
-+#if (MACID_NUM_SW_LIMIT > 32)
-+	else if (id < 64)
-+		return map->m1 & BIT(id - 32);
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 64)
-+	else if (id < 96)
-+		return map->m2 & BIT(id - 64);
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 96)
-+	else if (id < 128)
-+		return map->m3 & BIT(id - 96);
-+#endif
-+	else
-+		rtw_warn_on(1);
-+
-+	return 0;
-+}
-+
-+inline void rtw_macid_map_set(struct macid_bmp *map, u8 id)
-+{
-+	if (id < 32)
-+		map->m0 |= BIT(id);
-+#if (MACID_NUM_SW_LIMIT > 32)
-+	else if (id < 64)
-+		map->m1 |= BIT(id - 32);
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 64)
-+	else if (id < 96)
-+		map->m2 |= BIT(id - 64);
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 96)
-+	else if (id < 128)
-+		map->m3 |= BIT(id - 96);
-+#endif
-+	else
-+		rtw_warn_on(1);
-+}
-+
-+inline void rtw_macid_map_clr(struct macid_bmp *map, u8 id)
-+{
-+	if (id < 32)
-+		map->m0 &= ~BIT(id);
-+#if (MACID_NUM_SW_LIMIT > 32)
-+	else if (id < 64)
-+		map->m1 &= ~BIT(id - 32);
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 64)
-+	else if (id < 96)
-+		map->m2 &= ~BIT(id - 64);
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 96)
-+	else if (id < 128)
-+		map->m3 &= ~BIT(id - 96);
-+#endif
-+	else
-+		rtw_warn_on(1);
-+}
-+
-+inline bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id)
-+{
-+	return rtw_macid_is_set(&macid_ctl->used, id);
-+}
-+
-+inline bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id)
-+{
-+	return rtw_macid_is_set(&macid_ctl->bmc, id);
-+}
-+
-+inline u8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id)
-+{
-+	int i;
-+	u8 iface_bmp = 0;
-+
-+	for (i = 0; i < CONFIG_IFACE_NUMBER; i++) {
-+		if (rtw_macid_is_set(&macid_ctl->if_g[i], id))
-+			iface_bmp |= BIT(i);
-+	}
-+	return iface_bmp;
-+}
-+
-+inline bool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id)
-+{
-+#if CONFIG_IFACE_NUMBER >= 2
-+	int i;
-+	u8 iface_bmp = 0;
-+
-+	for (i = 0; i < CONFIG_IFACE_NUMBER; i++) {
-+		if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) {
-+			if (iface_bmp)
-+				return 1;
-+			iface_bmp |= BIT(i);
-+		}
-+	}
-+#endif
-+	return 0;
-+}
-+
-+inline bool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter)
-+{
-+	int i;
-+	u8 iface_bmp = 0;
-+
-+	for (i = 0; i < CONFIG_IFACE_NUMBER; i++) {
-+		if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) {
-+			if (iface_bmp || i != adapter->iface_id)
-+				return 0;
-+			iface_bmp |= BIT(i);
-+		}
-+	}
-+
-+	return iface_bmp ? 1 : 0;
-+}
-+
-+inline s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id)
-+{
-+	int i;
-+
-+	for (i = 0; i < 2; i++) {
-+		if (rtw_macid_is_set(&macid_ctl->ch_g[i], id))
-+			return i;
-+	}
-+	return -1;
-+}
-+
-+/*Record bc's mac-id and sec-cam-id*/
-+inline void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+
-+	macid_ctl->iface_bmc[padapter->iface_id] = mac_id;
-+}
-+inline u8 rtw_iface_bcmc_id_get(_adapter *padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+
-+	return macid_ctl->iface_bmc[padapter->iface_id];
-+}
-+#if defined(DBG_CONFIG_ERROR_RESET)
-+void rtw_iface_bcmc_sec_cam_map_restore(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
-+	int cam_id = -1;
-+
-+	cam_id = rtw_iface_bcmc_id_get(adapter);
-+	if (cam_id != INVALID_SEC_MAC_CAM_ID)
-+		rtw_sec_cam_map_set(&cam_ctl->used, cam_id);
-+}
-+#endif
-+void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta)
-+{
-+	int i;
-+	_irqL irqL;
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	struct macid_bmp *used_map = &macid_ctl->used;
-+	/* static u8 last_id = 0;  for testing */
-+	u8 last_id = 0;
-+	u8 is_bc_sta = _FALSE;
-+
-+	if (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)) {
-+		psta->cmn.mac_id = macid_ctl->num;
-+		return;
-+	}
-+
-+	if (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) {
-+		is_bc_sta = _TRUE;
-+		rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID);	/*init default value*/
-+	}
-+
-+	if (is_bc_sta
-+		#ifndef SEC_DEFAULT_KEY_SEARCH
-+		&& (MLME_IS_STA(padapter) || MLME_IS_NULL(padapter))
-+		#endif
-+	) {
-+		/* STA mode have no BMC data TX, shared with this macid */
-+		/* When non-concurrent, only one BMC data TX is used, shared with this macid */
-+		/* TODO: When concurrent, non-security BMC data TX may use this, but will not control by specific macid sleep */
-+		i = RTW_DEFAULT_MGMT_MACID;
-+		goto assigned;
-+	}
-+
-+	_enter_critical_bh(&macid_ctl->lock, &irqL);
-+
-+	for (i = last_id; i < macid_ctl->num; i++) {
-+#ifdef CONFIG_MCC_MODE
-+		/* macid 0/1 reserve for mcc for mgnt queue macid */
-+		if (MCC_EN(padapter)) {
-+			if (i == MCC_ROLE_STA_GC_MGMT_QUEUE_MACID)
-+				continue;
-+			if (i == MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID)
-+				continue;
-+		}
-+#endif /* CONFIG_MCC_MODE */
-+
-+		#ifndef SEC_DEFAULT_KEY_SEARCH
-+		/* for BMC data TX with force camid */
-+		if (is_bc_sta && rtw_sec_camid_is_used(dvobj_to_sec_camctl(dvobj), i))
-+			continue;
-+		#endif
-+
-+		if (!rtw_macid_is_used(macid_ctl, i))
-+			break;
-+	}
-+
-+	if (i < macid_ctl->num) {
-+
-+		rtw_macid_map_set(used_map, i);
-+
-+		#ifndef SEC_DEFAULT_KEY_SEARCH
-+		/* for BMC data TX with force camid */
-+		if (is_bc_sta) {
-+			struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
-+
-+			rtw_macid_map_set(&macid_ctl->bmc, i);
-+			rtw_iface_bcmc_id_set(padapter, i);
-+			rtw_sec_cam_map_set(&cam_ctl->used, i);
-+			if (_rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_EXTRA_SEC))
-+				rtw_sec_cam_map_set(&cam_ctl->used, i + 1);
-+		}
-+		#endif
-+
-+		rtw_macid_map_set(&macid_ctl->if_g[padapter->iface_id], i);
-+		macid_ctl->sta[i] = psta;
-+
-+		/* TODO ch_g? */
-+
-+		last_id++;
-+		last_id %= macid_ctl->num;
-+	}
-+
-+	_exit_critical_bh(&macid_ctl->lock, &irqL);
-+
-+	if (i >= macid_ctl->num) {
-+		psta->cmn.mac_id = macid_ctl->num;
-+		RTW_ERR(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" no available macid\n"
-+			, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr));
-+		rtw_warn_on(1);
-+		goto exit;
-+	} else
-+		goto assigned;
-+
-+assigned:
-+	psta->cmn.mac_id = i;
-+	RTW_INFO(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u\n"
-+		, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
-+
-+exit:
-+	return;
-+}
-+
-+void rtw_release_macid(_adapter *padapter, struct sta_info *psta)
-+{
-+	_irqL irqL;
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	u8 ifbmp;
-+	int i;
-+
-+	if (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN))
-+		goto exit;
-+
-+	if (psta->cmn.mac_id >= macid_ctl->num) {
-+		RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not valid\n"
-+			, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
-+			, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (psta->cmn.mac_id == RTW_DEFAULT_MGMT_MACID)
-+		goto msg;
-+
-+	_enter_critical_bh(&macid_ctl->lock, &irqL);
-+
-+	if (!rtw_macid_is_used(macid_ctl, psta->cmn.mac_id)) {
-+		RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not used\n"
-+			, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
-+			, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
-+		_exit_critical_bh(&macid_ctl->lock, &irqL);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	ifbmp = rtw_macid_get_iface_bmp(macid_ctl, psta->cmn.mac_id);
-+	if (!(ifbmp & BIT(padapter->iface_id))) {
-+		RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not used by self\n"
-+			, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
-+			, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
-+		_exit_critical_bh(&macid_ctl->lock, &irqL);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) {
-+		struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
-+		u8 id = rtw_iface_bcmc_id_get(padapter);
-+
-+		if ((id != INVALID_SEC_MAC_CAM_ID) && (id < cam_ctl->num)) {
-+			rtw_sec_cam_map_clr(&cam_ctl->used, id);
-+			if (_rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_EXTRA_SEC))
-+				rtw_sec_cam_map_clr(&cam_ctl->used, id + 1);
-+		}
-+
-+		rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID);
-+	}
-+
-+	rtw_macid_map_clr(&macid_ctl->if_g[padapter->iface_id], psta->cmn.mac_id);
-+
-+	ifbmp &= ~BIT(padapter->iface_id);
-+	if (!ifbmp) { /* only used by self */
-+		rtw_macid_map_clr(&macid_ctl->used, psta->cmn.mac_id);
-+		rtw_macid_map_clr(&macid_ctl->bmc, psta->cmn.mac_id);
-+		for (i = 0; i < 2; i++)
-+			rtw_macid_map_clr(&macid_ctl->ch_g[i], psta->cmn.mac_id);
-+		macid_ctl->sta[psta->cmn.mac_id] = NULL;
-+	}
-+
-+	_exit_critical_bh(&macid_ctl->lock, &irqL);
-+
-+msg:
-+	RTW_INFO(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u\n"
-+		, FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
-+		, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id
-+	);
-+
-+exit:
-+	psta->cmn.mac_id = macid_ctl->num;
-+}
-+
-+/* For 8188E RA */
-+u8 rtw_search_max_mac_id(_adapter *padapter)
-+{
-+	u8 max_mac_id = 0;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	int i;
-+	_irqL irqL;
-+
-+	/* TODO: Only search for connected macid? */
-+
-+	_enter_critical_bh(&macid_ctl->lock, &irqL);
-+	for (i = (macid_ctl->num - 1); i > 0 ; i--) {
-+		if (rtw_macid_is_used(macid_ctl, i))
-+			break;
-+	}
-+	_exit_critical_bh(&macid_ctl->lock, &irqL);
-+	max_mac_id = i;
-+
-+	return max_mac_id;
-+}
-+
-+inline u8 rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr)
-+{
-+	u8 op_num_change_bmp = 0;
-+
-+	if (id >= macid_ctl->num) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[id])
-+		&& !GET_H2CCMD_MSRRPT_PARM_OPMODE(&h2c_msr)
-+	) {
-+		u8 role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[id]);
-+
-+		if (role < H2C_MSR_ROLE_MAX) {
-+			macid_ctl->op_num[role]--;
-+			op_num_change_bmp |= BIT(role);
-+		}
-+	} else if (!GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[id])
-+		&& GET_H2CCMD_MSRRPT_PARM_OPMODE(&h2c_msr)
-+	) {
-+		u8 role = GET_H2CCMD_MSRRPT_PARM_ROLE(&h2c_msr);
-+
-+		if (role < H2C_MSR_ROLE_MAX) {
-+			macid_ctl->op_num[role]++;
-+			op_num_change_bmp |= BIT(role);
-+		}
-+	}
-+
-+	macid_ctl->h2c_msr[id] = h2c_msr;
-+	if (0)
-+		RTW_INFO("macid:%u, h2c_msr:"H2C_MSR_FMT"\n", id, H2C_MSR_ARG(&macid_ctl->h2c_msr[id]));
-+
-+exit:
-+	return op_num_change_bmp;
-+}
-+
-+inline void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw)
-+{
-+	if (id >= macid_ctl->num) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	macid_ctl->bw[id] = bw;
-+	if (0)
-+		RTW_INFO("macid:%u, bw:%s\n", id, ch_width_str(macid_ctl->bw[id]));
-+}
-+
-+inline void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en)
-+{
-+	if (id >= macid_ctl->num) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	macid_ctl->vht_en[id] = en;
-+	if (0)
-+		RTW_INFO("macid:%u, vht_en:%u\n", id, macid_ctl->vht_en[id]);
-+}
-+
-+inline void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp)
-+{
-+	if (id >= macid_ctl->num) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	macid_ctl->rate_bmp0[id] = bmp;
-+	if (0)
-+		RTW_INFO("macid:%u, rate_bmp0:0x%08X\n", id, macid_ctl->rate_bmp0[id]);
-+}
-+
-+inline void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp)
-+{
-+	if (id >= macid_ctl->num) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	macid_ctl->rate_bmp1[id] = bmp;
-+	if (0)
-+		RTW_INFO("macid:%u, rate_bmp1:0x%08X\n", id, macid_ctl->rate_bmp1[id]);
-+}
-+
-+#ifdef CONFIG_PROTSEL_MACSLEEP
-+inline void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 reg_ctrl, u16 reg_info)
-+{
-+	macid_ctl->reg_sleep_ctrl = reg_ctrl;
-+	macid_ctl->reg_sleep_info = reg_info;
-+}
-+inline void rtw_macid_ctl_init_drop_reg(struct macid_ctl_t *macid_ctl, u16 reg_ctrl, u16 reg_info)
-+{
-+	macid_ctl->reg_drop_ctrl = reg_ctrl;
-+	macid_ctl->reg_drop_info = reg_info;
-+}
-+
-+#else
-+inline void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3)
-+{
-+	macid_ctl->reg_sleep_m0 = m0;
-+#if (MACID_NUM_SW_LIMIT > 32)
-+	macid_ctl->reg_sleep_m1 = m1;
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 64)
-+	macid_ctl->reg_sleep_m2 = m2;
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 96)
-+	macid_ctl->reg_sleep_m3 = m3;
-+#endif
-+}
-+
-+inline void rtw_macid_ctl_init_drop_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3)
-+{
-+	macid_ctl->reg_drop_m0 = m0;
-+#if (MACID_NUM_SW_LIMIT > 32)
-+	macid_ctl->reg_drop_m1 = m1;
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 64)
-+	macid_ctl->reg_drop_m2 = m2;
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 96)
-+	macid_ctl->reg_drop_m3 = m3;
-+#endif
-+}
-+#endif
-+
-+inline void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl)
-+{
-+	int i;
-+	u8 id = RTW_DEFAULT_MGMT_MACID;
-+
-+	rtw_macid_map_set(&macid_ctl->used, id);
-+	rtw_macid_map_set(&macid_ctl->bmc, id);
-+	for (i = 0; i < CONFIG_IFACE_NUMBER; i++)
-+		rtw_macid_map_set(&macid_ctl->if_g[i], id);
-+	macid_ctl->sta[id] = NULL;
-+
-+	_rtw_spinlock_init(&macid_ctl->lock);
-+}
-+
-+inline void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl)
-+{
-+	_rtw_spinlock_free(&macid_ctl->lock);
-+}
-+
-+inline bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id)
-+{
-+	if (id / 8 >= bmp_len)
-+		return 0;
-+
-+	return bmp[id / 8] & BIT(id % 8);
-+}
-+
-+inline void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id)
-+{
-+	if (id / 8 < bmp_len)
-+		bmp[id / 8] |= BIT(id % 8);
-+}
-+
-+inline void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id)
-+{
-+	if (id / 8 < bmp_len)
-+		bmp[id / 8] &= ~BIT(id % 8);
-+}
-+
-+inline bool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len)
-+{
-+	int i;
-+
-+	for (i = 0; i < bmp_len; i++) {
-+		if (bmp[i])
-+			return 1;
-+	}
-+
-+	return 0;
-+}
-+
-+inline bool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len)
-+{
-+	int i;
-+
-+	for (i = 0; i < bmp_len; i++) {
-+		if (i == 0) {
-+			if (bmp[i] & 0xFE)
-+				return 1;
-+		} else {
-+			if (bmp[i])
-+				return 1;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+/* Check the id be set or not in map , if yes , return a none zero value*/
-+bool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id)
-+{
-+	return rtw_bmp_is_set(map, padapter->stapriv.aid_bmp_len, id);
-+}
-+
-+/* Set the id into map array*/
-+void rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id)
-+{
-+	rtw_bmp_set(map, padapter->stapriv.aid_bmp_len, id);
-+}
-+
-+/* Clear the id from map array*/
-+void rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id)
-+{
-+	rtw_bmp_clear(map, padapter->stapriv.aid_bmp_len, id);
-+}
-+
-+/* Check have anyone bit be set , if yes return true*/
-+bool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map)
-+{
-+	return rtw_bmp_not_empty(map, padapter->stapriv.aid_bmp_len);
-+}
-+
-+/* Check have anyone bit be set exclude bit0 , if yes return true*/
-+bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map)
-+{
-+	return rtw_bmp_not_empty_exclude_bit0(map, padapter->stapriv.aid_bmp_len);
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+#if 0
-+unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame)
-+{
-+	unsigned short				ATIMWindow;
-+	unsigned char					*pframe;
-+	struct tx_desc				*ptxdesc;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	unsigned int					rate_len, len = 0;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
-+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+
-+	_rtw_memset(beacon_frame, 0, 256);
-+
-+	pframe = beacon_frame + TXDESC_SIZE;
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
-+
-+	set_frame_sub_type(pframe, WIFI_BEACON);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	len = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	/* timestamp will be inserted by hardware */
-+	pframe += 8;
-+	len += 8;
-+
-+	/* beacon interval: 2 bytes */
-+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
-+
-+	pframe += 2;
-+	len += 2;
-+
-+	/* capability info: 2 bytes */
-+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
-+
-+	pframe += 2;
-+	len += 2;
-+
-+	/* SSID */
-+	pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &len);
-+
-+	/* supported rates... */
-+	rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
-+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &len);
-+
-+	/* DS parameter set */
-+	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &len);
-+
-+	/* IBSS Parameter Set... */
-+	/* ATIMWindow = cur->Configuration.ATIMWindow; */
-+	ATIMWindow = 0;
-+	pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &len);
-+
-+	/* todo: ERP IE */
-+
-+	/* EXTERNDED SUPPORTED RATE */
-+	if (rate_len > 8)
-+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &len);
-+
-+	if ((len + TXDESC_SIZE) > 256) {
-+		/* RTW_INFO("marc: beacon frame too large\n"); */
-+		return 0;
-+	}
-+
-+	/* fill the tx descriptor */
-+	ptxdesc = (struct tx_desc *)beacon_frame;
-+
-+	/* offset 0	 */
-+	ptxdesc->txdw0 |= cpu_to_le32(len & 0x0000ffff);
-+	ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00ff0000); /* default = 32 bytes for TX Desc */
-+
-+	/* offset 4	 */
-+	ptxdesc->txdw1 |= cpu_to_le32((0x10 << QSEL_SHT) & 0x00001f00);
-+
-+	/* offset 8		 */
-+	ptxdesc->txdw2 |= cpu_to_le32(BMC);
-+	ptxdesc->txdw2 |= cpu_to_le32(BK);
-+
-+	/* offset 16		 */
-+	ptxdesc->txdw4 = 0x80000000;
-+
-+	/* offset 20 */
-+	ptxdesc->txdw5 = 0x00000000; /* 1M	 */
-+
-+	return len + TXDESC_SIZE;
-+}
-+#endif
-+
-+_adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj)
-+{
-+	_adapter *port0_iface = NULL;
-+	int i;
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		if (get_hw_port(dvobj->padapters[i]) == HW_PORT0)
-+			break;
-+	}
-+
-+	if (i < 0 || i >= dvobj->iface_nums)
-+		rtw_warn_on(1);
-+	else
-+		port0_iface = dvobj->padapters[i];
-+
-+	return port0_iface;
-+}
-+
-+_adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj)
-+{
-+	_adapter *adapter = NULL;
-+	int i;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		if (dvobj->padapters[i]->registered == 0)
-+			break;
-+	}
-+
-+	if (i < dvobj->iface_nums)
-+		adapter = dvobj->padapters[i];
-+
-+	return adapter;
-+}
-+
-+_adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr)
-+{
-+	_adapter *adapter = NULL;
-+	int i;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		if (_rtw_memcmp(dvobj->padapters[i]->mac_addr, addr, ETH_ALEN) == _TRUE)
-+			break;
-+	}
-+
-+	if (i < dvobj->iface_nums)
-+		adapter = dvobj->padapters[i];
-+
-+	return adapter;
-+}
-+
-+#ifdef CONFIG_WOWLAN
-+bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern,
-+				   int *pattern_len, char *bit_mask)
-+{
-+	char *cp = NULL;
-+	size_t len = 0;
-+	int pos = 0, mask_pos = 0, res = 0;
-+
-+	/* To get the pattern string after "=", when we use :
-+	 * iwpriv wlanX pattern=XX:XX:..:XX
-+	 */
-+	cp = strchr(input, '=');
-+	if (cp) {
-+		*cp = 0;
-+		cp++;
-+		input = cp;
-+	}
-+
-+	/* To take off the newline character '\n'(0x0a) at the end of pattern string,
-+	 * when we use echo xxxx > /proc/xxxx
-+	 */
-+	cp = strchr(input, '\n');
-+	if (cp)
-+		*cp = 0;
-+
-+	while (input) {
-+		cp = strsep((char **)(&input), ":");
-+
-+		if (bit_mask && (strcmp(cp, "-") == 0 ||
-+				 strcmp(cp, "xx") == 0 ||
-+				 strcmp(cp, "--") == 0)) {
-+			/* skip this byte and leave mask bit unset */
-+		} else {
-+			u8 hex;
-+
-+			if (strlen(cp) != 2) {
-+				RTW_ERR("%s:[ERROR] hex len != 2, input=[%s]\n",
-+					__func__, cp);
-+				goto error;
-+			}
-+
-+			if (hexstr2bin(cp, &hex, 1) < 0) {
-+				RTW_ERR("%s:[ERROR] pattern is invalid, input=[%s]\n",
-+					__func__, cp);
-+				goto error;
-+			}
-+
-+			pattern[pos] = hex;
-+			mask_pos = pos / 8;
-+			if (bit_mask)
-+				bit_mask[mask_pos] |= 1 << (pos % 8);
-+		}
-+
-+		pos++;
-+	}
-+
-+	(*pattern_len) = pos;
-+
-+	return _TRUE;
-+error:
-+	return _FALSE;
-+}
-+
-+void rtw_wow_pattern_sw_reset(_adapter *adapter)
-+{
-+	int i;
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter);
-+
-+	if (pwrctrlpriv->default_patterns_en == _TRUE)
-+		pwrctrlpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM;
-+	else
-+		pwrctrlpriv->wowlan_pattern_idx = 0;
-+
-+	for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {
-+		_rtw_memset(pwrctrlpriv->patterns[i].content, '\0', sizeof(pwrctrlpriv->patterns[i].content));
-+		_rtw_memset(pwrctrlpriv->patterns[i].mask, '\0', sizeof(pwrctrlpriv->patterns[i].mask));
-+		pwrctrlpriv->patterns[i].len = 0;
-+	}
-+}
-+
-+u8 rtw_set_default_pattern(_adapter *adapter)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
-+	u8 index = 0;
-+	u8 multicast_addr[3] = {0x01, 0x00, 0x5e};
-+	u8 multicast_ip[4] = {0xe0, 0x28, 0x28, 0x2a};
-+
-+	u8 unicast_mask[5] = {0x3f, 0x70, 0x80, 0xc0, 0x03};
-+	u8 icmpv6_mask[7] = {0x00, 0x70, 0x10, 0x00, 0xc0, 0xc0, 0x3f};
-+	u8 multicast_mask[5] = {0x07, 0x70, 0x80, 0xc0, 0x03};
-+
-+	u8 ip_protocol[3] = {0x08, 0x00, 0x45};
-+	u8 ipv6_protocol[3] = {0x86, 0xdd, 0x60};
-+
-+	u8 *target = NULL;
-+
-+	if (pwrpriv->default_patterns_en == _FALSE)
-+		return 0;
-+
-+	for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) {
-+		_rtw_memset(pwrpriv->patterns[index].content, 0,
-+			    sizeof(pwrpriv->patterns[index].content));
-+		_rtw_memset(pwrpriv->patterns[index].mask, 0,
-+			    sizeof(pwrpriv->patterns[index].mask));
-+		pwrpriv->patterns[index].len = 0;
-+	}
-+
-+	/*TCP/ICMP unicast*/
-+	for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) {
-+		switch (index) {
-+		case 0:
-+			target = pwrpriv->patterns[index].content;
-+			_rtw_memcpy(target, adapter_mac_addr(adapter),
-+				    ETH_ALEN);
-+
-+			target += ETH_TYPE_OFFSET;
-+			_rtw_memcpy(target, &ip_protocol,
-+				    sizeof(ip_protocol));
-+
-+			/* TCP */
-+			target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);
-+			_rtw_memset(target, 0x06, 1);
-+
-+			target += (IP_OFFSET - PROTOCOL_OFFSET);
-+
-+			_rtw_memcpy(target, pmlmeinfo->ip_addr,
-+				    RTW_IP_ADDR_LEN);
-+
-+			_rtw_memcpy(pwrpriv->patterns[index].mask,
-+				    &unicast_mask, sizeof(unicast_mask));
-+
-+			pwrpriv->patterns[index].len =
-+				IP_OFFSET + RTW_IP_ADDR_LEN;
-+			break;
-+		case 1:
-+			target = pwrpriv->patterns[index].content;
-+			_rtw_memcpy(target, adapter_mac_addr(adapter),
-+				    ETH_ALEN);
-+
-+			target += ETH_TYPE_OFFSET;
-+			_rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol));
-+
-+			/* ICMP */
-+			target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);
-+			_rtw_memset(target, 0x01, 1);
-+
-+			target += (IP_OFFSET - PROTOCOL_OFFSET);
-+			_rtw_memcpy(target, pmlmeinfo->ip_addr,
-+				    RTW_IP_ADDR_LEN);
-+
-+			_rtw_memcpy(pwrpriv->patterns[index].mask,
-+				    &unicast_mask, sizeof(unicast_mask));
-+			pwrpriv->patterns[index].len =
-+
-+				IP_OFFSET + RTW_IP_ADDR_LEN;
-+			break;
-+#ifdef CONFIG_IPV6
-+		case 2:
-+			if (pwrpriv->wowlan_ns_offload_en == _TRUE) {
-+				target = pwrpriv->patterns[index].content;
-+				target += ETH_TYPE_OFFSET;
-+
-+				_rtw_memcpy(target, &ipv6_protocol,
-+					    sizeof(ipv6_protocol));
-+
-+				/* ICMPv6 */
-+				target += (IPv6_PROTOCOL_OFFSET -
-+					   ETH_TYPE_OFFSET);
-+				_rtw_memset(target, 0x3a, 1);
-+
-+				target += (IPv6_OFFSET - IPv6_PROTOCOL_OFFSET);
-+				_rtw_memcpy(target, pmlmeinfo->ip6_addr,
-+					    RTW_IPv6_ADDR_LEN);
-+
-+				_rtw_memcpy(pwrpriv->patterns[index].mask,
-+					    &icmpv6_mask, sizeof(icmpv6_mask));
-+				pwrpriv->patterns[index].len =
-+					IPv6_OFFSET + RTW_IPv6_ADDR_LEN;
-+			}
-+			break;
-+#endif /*CONFIG_IPV6*/
-+		case 3:
-+			target = pwrpriv->patterns[index].content;
-+			_rtw_memcpy(target, &multicast_addr,
-+				    sizeof(multicast_addr));
-+
-+			target += ETH_TYPE_OFFSET;
-+			_rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol));
-+
-+			/* UDP */
-+			target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);
-+			_rtw_memset(target, 0x11, 1);
-+
-+			target += (IP_OFFSET - PROTOCOL_OFFSET);
-+			_rtw_memcpy(target, &multicast_ip,
-+				    sizeof(multicast_ip));
-+
-+			_rtw_memcpy(pwrpriv->patterns[index].mask,
-+				    &multicast_mask, sizeof(multicast_mask));
-+
-+			pwrpriv->patterns[index].len =
-+				IP_OFFSET + sizeof(multicast_ip);
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+	return index;
-+}
-+
-+void rtw_dump_priv_pattern(_adapter *adapter, u8 idx)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+	char str_1[128];
-+	char *p_str;
-+	u8 val8 = 0;
-+	int i = 0, j = 0, len = 0, max_len = 0;
-+
-+	RTW_INFO("=========[%d]========\n", idx);
-+
-+	RTW_INFO(">>>priv_pattern_content:\n");
-+	p_str = str_1;
-+	max_len = sizeof(str_1);
-+	for (i = 0 ; i < MAX_WKFM_PATTERN_SIZE / 8 ; i++) {
-+		_rtw_memset(p_str, 0, max_len);
-+		len = 0;
-+		for (j = 0 ; j < 8 ; j++) {
-+			val8 = pwrctl->patterns[idx].content[i * 8 + j];
-+			len += snprintf(p_str + len, max_len - len,
-+					"%02x ", val8);
-+		}
-+		RTW_INFO("%s\n", p_str);
-+	}
-+
-+	RTW_INFO(">>>priv_pattern_mask:\n");
-+	for (i = 0 ; i < MAX_WKFM_SIZE / 8 ; i++) {
-+		_rtw_memset(p_str, 0, max_len);
-+		len = 0;
-+		for (j = 0 ; j < 8 ; j++) {
-+			val8 = pwrctl->patterns[idx].mask[i * 8 + j];
-+			len += snprintf(p_str + len, max_len - len,
-+					"%02x ", val8);
-+		}
-+		RTW_INFO("%s\n", p_str);
-+	}
-+
-+	RTW_INFO(">>>priv_pattern_len:\n");
-+	RTW_INFO("%s: len: %d\n", __func__, pwrctl->patterns[idx].len);
-+}
-+
-+void rtw_wow_pattern_sw_dump(_adapter *adapter)
-+{
-+	int i;
-+
-+	RTW_INFO("********[RTK priv-patterns]*********\n");
-+	for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++)
-+		rtw_dump_priv_pattern(adapter, i);
-+}
-+
-+void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr)
-+{
-+	struct sta_info		*psta;
-+	struct security_priv *psecpriv = &padapter->securitypriv;
-+
-+	_rtw_memset(pcur_dot11txpn, 0, 8);
-+	if (NULL == StaAddr)
-+		return;
-+	psta = rtw_get_stainfo(&padapter->stapriv, StaAddr);
-+	RTW_INFO("%s(): StaAddr: %02x %02x %02x %02x %02x %02x\n",
-+		 __func__, StaAddr[0], StaAddr[1], StaAddr[2],
-+		 StaAddr[3], StaAddr[4], StaAddr[5]);
-+
-+	if (psta) {
-+		if ((psecpriv->dot11PrivacyAlgrthm == _AES_) ||
-+			(psecpriv->dot11PrivacyAlgrthm == _CCMP_256_))
-+			AES_IV(pcur_dot11txpn, psta->dot11txpn, 0);
-+		else if (psecpriv->dot11PrivacyAlgrthm == _TKIP_)
-+			TKIP_IV(pcur_dot11txpn, psta->dot11txpn, 0);
-+		else if ((psecpriv->dot11PrivacyAlgrthm == _GCMP_) ||
-+				(psecpriv->dot11PrivacyAlgrthm == _GCMP_256_))
-+			GCMP_IV(pcur_dot11txpn, psta->dot11txpn, 0);
-+
-+		RTW_INFO("%s(): CurrentIV: %02x %02x %02x %02x %02x %02x %02x %02x\n"
-+			 , __func__, pcur_dot11txpn[0], pcur_dot11txpn[1],
-+			pcur_dot11txpn[2], pcur_dot11txpn[3], pcur_dot11txpn[4],
-+			pcur_dot11txpn[5], pcur_dot11txpn[6], pcur_dot11txpn[7]);
-+	}
-+}
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
-+void rtw_wow_war_mdns_dump_buf(struct seq_file *m, u8 *title, u8 *buf, u32 len)
-+{
-+	u32 i;
-+
-+	RTW_PRINT_SEL(m, "\t%s (%d)\n\t\t", title, len);
-+	for (i = 1; i <= len; i++)
-+	{
-+		RTW_PRINT_SEL(m, "%2.2x-", *(buf + i - 1));
-+		if( (i%16 == 0) && (len != i) ) RTW_PRINT_SEL(m, "\n\t\t");
-+	}	
-+	RTW_PRINT_SEL(m, "\n\n");
-+}
-+
-+void rtw_wow_war_mdns_dump_txt(struct seq_file *m, u8 *title, u8 *buf, u32 len)
-+{
-+	u16 idx=1, offset=0; /* offset = the location of L in the Length.Value */
-+
-+	RTW_PRINT_SEL(m, "\t%s (%d)\n\t", title, len);
-+	for (; offset < len; idx++)
-+	{
-+		int item_len = buf[offset];
-+		u8 item_buf[256]={0};
-+
-+		_rtw_memcpy(item_buf, (buf + offset + 1), item_len);
-+		RTW_PRINT_SEL(m, "\t[%d] => %s (%d)\n\t", idx, item_buf, item_len);
-+		_rtw_memset(item_buf, 0, sizeof(item_buf));
-+		offset += (1+item_len);
-+	}	
-+	RTW_PRINT_SEL(m, "\n\n");
-+}
-+
-+bool rtw_wow_war_mdns_parser_pattern(u8 *input, char *target,
-+				   u32 *target_len, u32 type)
-+{
-+	char *cp = NULL, *end = NULL;
-+	size_t len = 0;
-+	int pos = 0, mask_pos = 0, res = 0;
-+	u8 member[2] = {0};
-+
-+	/* reset */
-+	_rtw_memset(target, '\0', type);
-+	(*target_len) = 0;
-+
-+	cp = strchr(input, '=');
-+	if (cp) {
-+		*cp = 0;
-+		cp++;
-+		input = cp;
-+	}
-+
-+	while (1) {
-+		cp = strchr(input, ':');
-+
-+		if (cp) {
-+			len = strlen(input) - strlen(cp);
-+			*cp = 0;
-+			cp++;
-+		} else
-+			len = 2;
-+		
-+		{
-+			u8 hex,idx=0, pos_in_unit_as_4bit = 0;
-+
-+			strncpy(member, input, len);
-+			res = sscanf(member, "%02hhx", &hex);
-+			
-+			target[pos] = hex;
-+			
-+			/* RTW_INFO("==> in; input-member = %s, hex = %x,  target[%d] = %x\n", member, hex, target[pos], pos); */
-+
-+			for(idx = 0; idx<2;idx++)
-+			{
-+				pos_in_unit_as_4bit =  pos*2 + (1-idx); 
-+				mask_pos = (pos_in_unit_as_4bit /8);
-+
-+				if(!IsHexDigit(member[idx]))
-+				{
-+					RTW_ERR("%s:[ERROR] pattern is invalid!!(%c)\n",__func__, member[idx]);
-+					goto error;
-+				}
-+
-+				/* RTW_INFO("==> in; pos = %d, pos_in_unit_as_4bit = %d, mask-pos = %d \n", pos, pos_in_unit_as_4bit, mask_pos); 
-+				RTW_INFO("==> in; hex(0x%02x), member(%c%c) \n", pattern[pos], member[1], member[0]); */
-+			}
-+			/* RTW_INFO_DUMP("Pattern Mask: ",bit_mask, 6); */
-+		}
-+
-+		pos++;
-+		if (!cp)
-+			break;
-+		input = cp;
-+	}
-+
-+	(*target_len) = pos;
-+
-+	return _TRUE;
-+error:
-+	return _FALSE;
-+
-+}
-+
-+static struct war_mdns_service_info default_sinfo[] = {  
-+/*	example of default setting */
-+	RTW_MDNS_SRV_INFO("_ipp", 4, "_tcp", 4, "local", 5, 0x02, 0x77, 7200, "KM1", 3, 0),
-+	RTW_MDNS_SRV_INFO("_ipps", 5, "_tcp", 4, "local", 5, 0x02, 0x77, 7200, "KM2", 3, 0),
-+	RTW_MDNS_SRV_INFO("_http", 5, "_tcp", 4, "local", 5, 0x00, 0x50, 7200, "KM3", 3, 2),
-+	RTW_MDNS_SRV_INFO("_privet", 7, "_tcp", 4, "local", 5, 0x00, 0x50, 7200, "KM4", 3, 3),
-+	RTW_MDNS_SRV_INFO("_https", 6, "_tcp", 4, "local", 5, 0x01, 0xbb, 7200, "KM5", 3, 2),
-+	RTW_MDNS_SRV_INFO("_uscan", 6, "_tcp", 4, "local", 5, 0x1f, 0x91, 7200, "KM6", 3, 4),
-+	RTW_MDNS_SRV_INFO("_printer", 8, "_tcp", 4, "local", 5, 0x23, 0x8c, 7200, "KM7", 3, 1),
-+	RTW_MDNS_SRV_INFO("_pdl-datastream", 15, "_tcp", 4, "local", 5, 0x23, 0x8c, 7200, "KM8", 3, 1) 
-+
-+};
-+
-+void rtw_wow_war_mdns_parms_reset(_adapter *adapter, u8 is_set_default)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	u8 i =0;
-+	u16	offset=0;
-+	u8 default_domain_name[] = "Generic";
-+	//u8 default_machine_name[] = { 0x0a, 0x5f, 0x75, 0x6e, 0x69, 0x76, 0x65, 0x72, 0x73, 0x61, 0x6c, 0x04, 0x5f, 0x73, 0x75, 0x62 };
-+	//u8 default_machine_name_len = 16;
-+	u8 default_machine_name[] = { 0x0a, 0x5f, 0x75, 0x6e, 0x69, 0x76, 0x65, 0x72, 0x73, 0x61, 0x6c}; /* length : 10 name : _universal */
-+	u8 default_machine_name_len = 11;
-+
-+	/* set default txt value*/
-+	char *default_txt_rsp_0_for_serive[2] = { "_ipp", "_ipps" };
-+	char *default_txt_rsp_0[25] = {
-+		"txtvers=1", "qtotal=1", "usb_MFG=KONICA MINOLTA", "usb_MDL=C754Series",
-+		"rp=ipp/print","priority=54","tr=Generic 35c-4", "product=DriverName", 
-+		"pdl=application/postscript,image/urf,application/octet-stream,image/jpeg",
-+		"adminurl=http://KM00D91C.local./wcd/a_network.xml",
-+		"note=Copy Room", "Transparent=T", "Binary=T", "TBCP=T", 
-+		"URF=V1,4,w8,SRGB24,ADOBERGB24-48,DEVW8,DEVRGB24,DEVCMYK32,RS150000000,IS19-20-21,MT1-3,OB1,PQ4,DM1,FN3-14,CP255",
-+		"rfo=ipp/faxout", "Fax=T", "Scan=T", "Duplex=T", "Color=T", "air=none",
-+		"Kind=document,envelope,photo",
-+		"PaperMax=tabloid-A3", "UUID=6c183832-69ba-541b-baf6-6d947c144325", "TLS=1.2"
-+	};
-+
-+	char *default_txt_rsp_1_for_serive[2] = { "_printer", "_pdl-datastream" };
-+	char *default_txt_rsp_1[13] = {
-+		"txtvers=1", "qtotal=1", "usb_MFG=KONICA MINOLTA", "usb_MDL=C754Series",
-+		"rp=print","priority=51","tr=Generic 35c-4", "product=DriverName",   
-+		"pdl=application/postscript", "note=Copy Room", "Transparent=T", "Binary=T", "TBCP=F"
-+	};
-+
-+	char *default_txt_rsp_2_for_serive[2] = { "_http", "_https" };
-+	char *default_txt_rsp_2[1] = { 
-+		"Path=/" 
-+	};
-+
-+	char *default_txt_rsp_3_for_serive[1] = { "_privet" };
-+	char *default_txt_rsp_3[5] = {
-+		"txtvers=1", "url=https://www.google.com/cloudprint",
-+		"type=printer", "cs=not-configured","note=Copy Room"
-+	};
-+
-+	char *default_txt_rsp_4_for_serive[1] = { "_uscan" };
-+	char *default_txt_rsp_4[11] = {
-+		"txtvers=1", "vers=2.5", "adminurl=http://KM00D91C.local./wsd/a_network_airprint.xml",
-+		"representation=http://KM00D91C.local./wcd/DeviceIcon_1283png",
-+		"rs=eSCL", "ty=KONICA MINOLTA bishub C287", "note=japan",
-+		"pdl=image/jpeg,image/tiff,application/pdf",
-+		"UUID=dd5454cc-e196-5711-aa1f-35be49a6ca9f",
-+		"cs=color,grayscale,binary", "is=platen,adf,duplex=T"
-+	};
-+
-+
-+	/* reset ===>  */
-+
-+	_rtw_memset(pwrpriv->wowlan_war_offload_mdns_domain_name, 0, MAX_MDNS_DOMAIN_NAME_LEN);
-+	_rtw_memset(pwrpriv->wowlan_war_offload_mdns_mnane, 0, sizeof(pwrpriv->wowlan_war_offload_mdns_mnane));
-+	_rtw_memset(pwrpriv->wowlan_war_offload_mdns_service, 0, sizeof(pwrpriv->wowlan_war_offload_mdns_service));
-+	_rtw_memset(pwrpriv->wowlan_war_offload_mdns_txt_rsp, 0, sizeof(pwrpriv->wowlan_war_offload_mdns_txt_rsp));
-+
-+	pwrpriv->wowlan_war_offload_mdns_domain_name_len = 0;
-+	pwrpriv->wowlan_war_offload_mdns_mnane_num = 0;
-+	pwrpriv->wowlan_war_offload_mdns_service_info_num = 0;
-+	pwrpriv->wowlan_war_offload_mdns_txt_rsp_num = 0;
-+	pwrpriv->wowlan_war_offload_mdns_para_cur_size = 0;
-+	pwrpriv->wowlan_war_offload_mdns_rsp_cur_size = 0;
-+
-+	/* init  ===>  */
-+
-+	if(is_set_default)
-+	{
-+		// domain_name
-+		pwrpriv->wowlan_war_offload_mdns_domain_name_len = strlen(default_domain_name);
-+		_rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_domain_name, default_domain_name, sizeof(default_domain_name));
-+
-+		// machine name
-+		pwrpriv->wowlan_war_offload_mdns_mnane_num = 1;    
-+		pwrpriv->wowlan_war_offload_mdns_mnane[0].name_len = default_machine_name_len;
-+		_rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_mnane[0].name, default_machine_name, default_machine_name_len);
-+
-+		// service info
-+		pwrpriv->wowlan_war_offload_mdns_service_info_num = 8;
-+		_rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_service, default_sinfo, sizeof(default_sinfo));
-+
-+		// type txt rsp 0~5
-+		// 0
-+		for(offset=0, i=0; i<25; i++)
-+		{
-+			pwrpriv->wowlan_war_offload_mdns_txt_rsp[0].txt[offset++] = strlen(default_txt_rsp_0[i]);
-+			_rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_txt_rsp[0].txt + offset, default_txt_rsp_0[i], strlen(default_txt_rsp_0[i]));
-+			offset += strlen(default_txt_rsp_0[i]);
-+			RTW_INFO("==> default_txt_rsp_0[%d]: [%s](%zu), offset(%d)\n", i, default_txt_rsp_0[i], strlen(default_txt_rsp_0[i]), offset);
-+		}	
-+		pwrpriv->wowlan_war_offload_mdns_txt_rsp[0].txt_len = offset;
-+		// RTW_INFO("==> offset = %d\n\n", offset);
-+
-+		
-+		// 1
-+		for(offset=0, i=0; i<13; i++)
-+		{
-+			pwrpriv->wowlan_war_offload_mdns_txt_rsp[1].txt[offset++] = strlen(default_txt_rsp_1[i]);
-+			_rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_txt_rsp[1].txt + offset, default_txt_rsp_1[i], strlen(default_txt_rsp_1[i]));
-+			offset += strlen(default_txt_rsp_1[i]);
-+		}	
-+		pwrpriv->wowlan_war_offload_mdns_txt_rsp[1].txt_len = offset;
-+		// RTW_INFO("==> offset = %d\n\n", offset);
-+		
-+		// 2
-+		for(offset=0, i=0; i<1; i++)
-+		{
-+			pwrpriv->wowlan_war_offload_mdns_txt_rsp[2].txt[offset++] = strlen(default_txt_rsp_2[i]);
-+			_rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_txt_rsp[2].txt + offset, default_txt_rsp_2[i], strlen(default_txt_rsp_2[i]));
-+			offset += strlen(default_txt_rsp_2[i]);
-+		}	
-+		pwrpriv->wowlan_war_offload_mdns_txt_rsp[2].txt_len = offset;
-+		// RTW_INFO("==> offset = %d\n\n", offset);
-+		
-+		// 3
-+		for(offset=0, i=0; i<5; i++)
-+		{
-+			pwrpriv->wowlan_war_offload_mdns_txt_rsp[3].txt[offset++] = strlen(default_txt_rsp_3[i]);
-+			_rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_txt_rsp[3].txt + offset, default_txt_rsp_3[i], strlen(default_txt_rsp_3[i]));
-+			offset += strlen(default_txt_rsp_3[i]);
-+		}	
-+		pwrpriv->wowlan_war_offload_mdns_txt_rsp[3].txt_len = offset;
-+		// RTW_INFO("==> offset = %d\n\n", offset);
-+		
-+		// 4
-+		for(offset=0, i=0; i<11; i++)
-+		{
-+			pwrpriv->wowlan_war_offload_mdns_txt_rsp[4].txt[offset++] = strlen(default_txt_rsp_4[i]);
-+			_rtw_memcpy(pwrpriv->wowlan_war_offload_mdns_txt_rsp[4].txt + offset, default_txt_rsp_4[i], strlen(default_txt_rsp_4[i]));
-+			offset += strlen(default_txt_rsp_4[i]);
-+		}	
-+		pwrpriv->wowlan_war_offload_mdns_txt_rsp[4].txt_len = offset;
-+		// RTW_INFO("==> offset = %d\n\n", offset); 
-+
-+		/* txt_rsp_num is always as MAX_MDNS_TXT_NUM because the input mechanism(new/append) makes the entities are not in order */
-+		pwrpriv->wowlan_war_offload_mdns_txt_rsp_num = MAX_MDNS_TXT_NUM;
-+	}
-+}
-+
-+
-+#endif /* defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) */
-+#endif /* CONFIG_WAR_OFFLOAD */
-+#endif /* CONFIG_WOWLAN */
-+
-+inline bool _rtw_wow_chk_cap(_adapter *adapter, u8 cap)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct wow_ctl_t *wow_ctl = &dvobj->wow_ctl;
-+
-+	if (wow_ctl->wow_cap & cap)
-+		return _TRUE;
-+	return _FALSE;
-+}
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+#define	CSCAN_TLV_TYPE_SSID_IE	'S'
-+#define CIPHER_IE "key_mgmt="
-+#define CIPHER_NONE "NONE"
-+#define CIPHER_WPA_PSK "WPA-PSK"
-+#define CIPHER_WPA_EAP "WPA-EAP IEEE8021X"
-+/*
-+ *  SSIDs list parsing from cscan tlv list
-+ */
-+int rtw_parse_ssid_list_tlv(char **list_str, pno_ssid_t *ssid,
-+			    int max, int *bytes_left)
-+{
-+	char *str;
-+
-+	int idx = 0;
-+
-+	if ((list_str == NULL) || (*list_str == NULL) || (*bytes_left < 0)) {
-+		RTW_INFO("%s error paramters\n", __func__);
-+		return -1;
-+	}
-+
-+	str = *list_str;
-+	while (*bytes_left > 0) {
-+
-+		if (str[0] != CSCAN_TLV_TYPE_SSID_IE) {
-+			*list_str = str;
-+			RTW_INFO("nssid=%d left_parse=%d %d\n", idx, *bytes_left, str[0]);
-+			return idx;
-+		}
-+
-+		/* Get proper CSCAN_TLV_TYPE_SSID_IE */
-+		*bytes_left -= 1;
-+		str += 1;
-+
-+		if (str[0] == 0) {
-+			/* Broadcast SSID */
-+			ssid[idx].SSID_len = 0;
-+			memset((char *)ssid[idx].SSID, 0x0, WLAN_SSID_MAXLEN);
-+			*bytes_left -= 1;
-+			str += 1;
-+
-+			RTW_INFO("BROADCAST SCAN  left=%d\n", *bytes_left);
-+		} else if (str[0] <= WLAN_SSID_MAXLEN) {
-+			/* Get proper SSID size */
-+			ssid[idx].SSID_len = str[0];
-+			*bytes_left -= 1;
-+			str += 1;
-+
-+			/* Get SSID */
-+			if (ssid[idx].SSID_len > *bytes_left) {
-+				RTW_INFO("%s out of memory range len=%d but left=%d\n",
-+					__func__, ssid[idx].SSID_len, *bytes_left);
-+				return -1;
-+			}
-+
-+			memcpy((char *)ssid[idx].SSID, str, ssid[idx].SSID_len);
-+
-+			*bytes_left -= ssid[idx].SSID_len;
-+			str += ssid[idx].SSID_len;
-+
-+			RTW_INFO("%s :size=%d left=%d\n",
-+				(char *)ssid[idx].SSID, ssid[idx].SSID_len, *bytes_left);
-+		} else {
-+			RTW_INFO("### SSID size more that %d\n", str[0]);
-+			return -1;
-+		}
-+
-+		if (idx++ >  max) {
-+			RTW_INFO("%s number of SSIDs more that %d\n", __func__, idx);
-+			return -1;
-+		}
-+	}
-+
-+	*list_str = str;
-+	return idx;
-+}
-+
-+int rtw_parse_cipher_list(struct pno_nlo_info *nlo_info, char *list_str)
-+{
-+
-+	char *pch, *pnext, *pend;
-+	u8 key_len = 0, index = 0;
-+
-+	pch = list_str;
-+
-+	if (nlo_info == NULL || list_str == NULL) {
-+		RTW_INFO("%s error paramters\n", __func__);
-+		return -1;
-+	}
-+
-+	while (strlen(pch) != 0) {
-+		pnext = strstr(pch, "key_mgmt=");
-+		if (pnext != NULL) {
-+			pch = pnext + strlen(CIPHER_IE);
-+			pend = strstr(pch, "}");
-+			if (strncmp(pch, CIPHER_NONE,
-+				    strlen(CIPHER_NONE)) == 0)
-+				nlo_info->ssid_cipher_info[index] = 0x00;
-+			else if (strncmp(pch, CIPHER_WPA_PSK,
-+					 strlen(CIPHER_WPA_PSK)) == 0)
-+				nlo_info->ssid_cipher_info[index] = 0x66;
-+			else if (strncmp(pch, CIPHER_WPA_EAP,
-+					 strlen(CIPHER_WPA_EAP)) == 0)
-+				nlo_info->ssid_cipher_info[index] = 0x01;
-+			index++;
-+			pch = pend + 1;
-+		} else
-+			break;
-+	}
-+	return 0;
-+}
-+
-+int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid,
-+		 int num, int pno_time, int pno_repeat, int pno_freq_expo_max)
-+{
-+
-+	int i = 0;
-+	struct file *fp;
-+	mm_segment_t fs;
-+	loff_t pos = 0;
-+	u8 *source = NULL;
-+	long len = 0;
-+
-+	RTW_INFO("+%s+\n", __func__);
-+
-+	nlo_info->fast_scan_period = pno_time;
-+	nlo_info->ssid_num = num & BIT_LEN_MASK_32(8);
-+	nlo_info->hidden_ssid_num = num & BIT_LEN_MASK_32(8);
-+	nlo_info->slow_scan_period = (pno_time * 2);
-+	nlo_info->fast_scan_iterations = 5;
-+
-+	if (nlo_info->hidden_ssid_num > 8)
-+		nlo_info->hidden_ssid_num = 8;
-+
-+	/* TODO: channel list and probe index is all empty. */
-+	for (i = 0 ; i < num ; i++) {
-+		nlo_info->ssid_length[i]
-+			= ssid[i].SSID_len;
-+	}
-+
-+	/* cipher array */
-+	fp = filp_open("/data/misc/wifi/wpa_supplicant.conf", O_RDONLY,  0644);
-+	if (IS_ERR(fp)) {
-+		RTW_INFO("Error, wpa_supplicant.conf doesn't exist.\n");
-+		RTW_INFO("Error, cipher array using default value.\n");
-+		return 0;
-+	}
-+
-+	len = i_size_read(fp->f_path.dentry->d_inode);
-+	if (len < 0 || len > 2048) {
-+		RTW_INFO("Error, file size is bigger than 2048.\n");
-+		RTW_INFO("Error, cipher array using default value.\n");
-+		return 0;
-+	}
-+
-+	fs = get_fs();
-+	set_fs(KERNEL_DS);
-+
-+	source = rtw_zmalloc(2048);
-+
-+	if (source != NULL) {
-+		len = vfs_read(fp, source, len, &pos);
-+		rtw_parse_cipher_list(nlo_info, source);
-+		rtw_mfree(source, 2048);
-+	}
-+
-+	set_fs(fs);
-+	filp_close(fp, NULL);
-+
-+	RTW_INFO("-%s-\n", __func__);
-+	return 0;
-+}
-+
-+int rtw_dev_ssid_list_set(struct pno_ssid_list *pno_ssid_list,
-+			  pno_ssid_t *ssid, u8 num)
-+{
-+
-+	int i = 0;
-+	if (num > MAX_PNO_LIST_COUNT)
-+		num = MAX_PNO_LIST_COUNT;
-+
-+	for (i = 0 ; i < num ; i++) {
-+		_rtw_memcpy(&pno_ssid_list->node[i].SSID,
-+			    ssid[i].SSID, ssid[i].SSID_len);
-+		pno_ssid_list->node[i].SSID_len = ssid[i].SSID_len;
-+	}
-+	return 0;
-+}
-+
-+int rtw_dev_scan_info_set(_adapter *padapter, pno_ssid_t *ssid,
-+	  unsigned char ch, unsigned char ch_offset, unsigned short bw_mode)
-+{
-+
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
-+	struct pno_scan_info *scan_info = pwrctl->pscan_info;
-+	u8 band = ch <= 14 ? BAND_ON_2_4G : BAND_ON_5G;
-+	int i;
-+
-+	scan_info->channel_num = MAX_SCAN_LIST_COUNT;
-+	scan_info->orig_ch = ch;
-+	scan_info->orig_bw = bw_mode;
-+	scan_info->orig_40_offset = ch_offset;
-+
-+	for (i = 0 ; i < scan_info->channel_num ; i++) {
-+		if (i < 11)
-+			scan_info->ssid_channel_info[i].active = 1;
-+		else
-+			scan_info->ssid_channel_info[i].active = 0;
-+
-+		scan_info->ssid_channel_info[i].timeout = 100;
-+
-+		scan_info->ssid_channel_info[i].tx_power =
-+			phy_get_tx_power_index_ex(padapter, 0, CCK, MGN_1M, bw_mode, band, i + 1, i + 1);
-+
-+		scan_info->ssid_channel_info[i].channel = i + 1;
-+	}
-+
-+	RTW_INFO("%s, channel_num: %d, orig_ch: %d, orig_bw: %d orig_40_offset: %d\n",
-+		 __func__, scan_info->channel_num, scan_info->orig_ch,
-+		 scan_info->orig_bw, scan_info->orig_40_offset);
-+	return 0;
-+}
-+
-+int rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num,
-+		    int pno_time, int pno_repeat, int pno_freq_expo_max)
-+{
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+
-+	int ret = -1;
-+
-+	if (num == 0) {
-+		RTW_INFO("%s, nssid is zero, no need to setup pno ssid list\n", __func__);
-+		return 0;
-+	}
-+
-+	if (pwrctl == NULL) {
-+		RTW_INFO("%s, ERROR: pwrctl is NULL\n", __func__);
-+		return -1;
-+	} else {
-+		pwrctl->pnlo_info =
-+			(pno_nlo_info_t *)rtw_zmalloc(sizeof(pno_nlo_info_t));
-+		pwrctl->pno_ssid_list =
-+			(pno_ssid_list_t *)rtw_zmalloc(sizeof(pno_ssid_list_t));
-+		pwrctl->pscan_info =
-+			(pno_scan_info_t *)rtw_zmalloc(sizeof(pno_scan_info_t));
-+	}
-+
-+	if (pwrctl->pnlo_info == NULL ||
-+	    pwrctl->pscan_info == NULL ||
-+	    pwrctl->pno_ssid_list == NULL) {
-+		RTW_INFO("%s, ERROR: alloc nlo_info, ssid_list, scan_info fail\n", __func__);
-+		goto failing;
-+	}
-+
-+	pwrctl->wowlan_in_resume = _FALSE;
-+
-+	pwrctl->pno_inited = _TRUE;
-+	/* NLO Info */
-+	ret = rtw_dev_nlo_info_set(pwrctl->pnlo_info, ssid, num,
-+				   pno_time, pno_repeat, pno_freq_expo_max);
-+
-+	/* SSID Info */
-+	ret = rtw_dev_ssid_list_set(pwrctl->pno_ssid_list, ssid, num);
-+
-+	/* SCAN Info */
-+	ret = rtw_dev_scan_info_set(padapter, ssid, pmlmeext->cur_channel,
-+			    pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
-+
-+	RTW_INFO("+%s num: %d, pno_time: %d, pno_repeat:%d, pno_freq_expo_max:%d+\n",
-+		 __func__, num, pno_time, pno_repeat, pno_freq_expo_max);
-+
-+	return 0;
-+
-+failing:
-+	if (pwrctl->pnlo_info) {
-+		rtw_mfree((u8 *)pwrctl->pnlo_info, sizeof(pno_nlo_info_t));
-+		pwrctl->pnlo_info = NULL;
-+	}
-+	if (pwrctl->pno_ssid_list) {
-+		rtw_mfree((u8 *)pwrctl->pno_ssid_list, sizeof(pno_ssid_list_t));
-+		pwrctl->pno_ssid_list = NULL;
-+	}
-+	if (pwrctl->pscan_info) {
-+		rtw_mfree((u8 *)pwrctl->pscan_info, sizeof(pno_scan_info_t));
-+		pwrctl->pscan_info = NULL;
-+	}
-+
-+	return -1;
-+}
-+
-+#ifdef CONFIG_PNO_SET_DEBUG
-+void rtw_dev_pno_debug(struct net_device *net)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
-+	int i = 0, j = 0;
-+
-+	RTW_INFO("*******NLO_INFO********\n");
-+	RTW_INFO("ssid_num: %d\n", pwrctl->pnlo_info->ssid_num);
-+	RTW_INFO("fast_scan_iterations: %d\n",
-+		 pwrctl->pnlo_info->fast_scan_iterations);
-+	RTW_INFO("fast_scan_period: %d\n", pwrctl->pnlo_info->fast_scan_period);
-+	RTW_INFO("slow_scan_period: %d\n", pwrctl->pnlo_info->slow_scan_period);
-+
-+
-+
-+	for (i = 0 ; i < MAX_PNO_LIST_COUNT ; i++) {
-+		RTW_INFO("%d SSID (%s) length (%d) cipher(%x) channel(%d)\n",
-+			i, pwrctl->pno_ssid_list->node[i].SSID, pwrctl->pnlo_info->ssid_length[i],
-+			pwrctl->pnlo_info->ssid_cipher_info[i], pwrctl->pnlo_info->ssid_channel_info[i]);
-+	}
-+
-+	RTW_INFO("******SCAN_INFO******\n");
-+	RTW_INFO("ch_num: %d\n", pwrctl->pscan_info->channel_num);
-+	RTW_INFO("orig_ch: %d\n", pwrctl->pscan_info->orig_ch);
-+	RTW_INFO("orig bw: %d\n", pwrctl->pscan_info->orig_bw);
-+	RTW_INFO("orig 40 offset: %d\n", pwrctl->pscan_info->orig_40_offset);
-+	for (i = 0 ; i < MAX_SCAN_LIST_COUNT ; i++) {
-+		RTW_INFO("[%02d] avtive:%d, timeout:%d, tx_power:%d, ch:%02d\n",
-+			 i, pwrctl->pscan_info->ssid_channel_info[i].active,
-+			 pwrctl->pscan_info->ssid_channel_info[i].timeout,
-+			 pwrctl->pscan_info->ssid_channel_info[i].tx_power,
-+			 pwrctl->pscan_info->ssid_channel_info[i].channel);
-+	}
-+	RTW_INFO("*****************\n");
-+}
-+#endif /* CONFIG_PNO_SET_DEBUG */
-+#endif /* CONFIG_PNO_SUPPORT */
-+
-+inline void rtw_collect_bcn_info(_adapter *adapter)
-+{
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+
-+	if (!is_client_associated_to_ap(adapter))
-+		return;
-+
-+	pmlmeext->cur_bcn_cnt = pmlmeext->bcn_cnt - pmlmeext->last_bcn_cnt;
-+	pmlmeext->last_bcn_cnt = pmlmeext->bcn_cnt;
-+	/*TODO get offset of bcn's timestamp*/
-+	/*pmlmeext->bcn_timestamp;*/
-+}
-+
-+static u32 rtw_get_vht_bitrate(u8 mcs, u8 bw, u8 nss, u8 sgi)
-+{
-+	static const u32 base[4][10] = {
-+		{   6500000,
-+		   13000000,
-+		   19500000,
-+		   26000000,
-+		   39000000,
-+		   52000000,
-+		   58500000,
-+		   65000000,
-+		   78000000,
-+		/* not in the spec, but some devices use this: */
-+		   86500000,
-+		},
-+		{  13500000,
-+		   27000000,
-+		   40500000,
-+		   54000000,
-+		   81000000,
-+		  108000000,
-+		  121500000,
-+		  135000000,
-+		  162000000,
-+		  180000000,
-+		},
-+		{  29300000,
-+		   58500000,
-+		   87800000,
-+		  117000000,
-+		  175500000,
-+		  234000000,
-+		  263300000,
-+		  292500000,
-+		  351000000,
-+		  390000000,
-+		},
-+		{  58500000,
-+		  117000000,
-+		  175500000,
-+		  234000000,
-+		  351000000,
-+		  468000000,
-+		  526500000,
-+		  585000000,
-+		  702000000,
-+		  780000000,
-+		},
-+	};
-+	u32 bitrate;
-+	int bw_idx;
-+
-+	if (mcs > 9) {
-+		RTW_INFO("Invalid mcs = %d\n", mcs);
-+		return 0;
-+	}
-+
-+	if (nss > 4 || nss < 1) {
-+		RTW_INFO("Now only support nss = 1, 2, 3, 4\n");
-+	}
-+
-+	switch (bw) {
-+	case CHANNEL_WIDTH_160:
-+		bw_idx = 3;
-+		break;
-+	case CHANNEL_WIDTH_80:
-+		bw_idx = 2;
-+		break;
-+	case CHANNEL_WIDTH_40:
-+		bw_idx = 1;
-+		break;
-+	case CHANNEL_WIDTH_20:
-+		bw_idx = 0;
-+		break;
-+	default:
-+		RTW_INFO("bw = %d currently not supported\n", bw);
-+		return 0;
-+	}
-+
-+	bitrate = base[bw_idx][mcs];
-+	bitrate *= nss;
-+
-+	if (sgi)
-+		bitrate = (bitrate / 9) * 10;
-+
-+	/* do NOT round down here */
-+	return (bitrate + 50000) / 100000;
-+}
-+
-+static u32 rtw_get_ht_bitrate(u8 mcs, u8 bw, u8 sgi)
-+{
-+	int modulation, streams, bitrate;
-+
-+	/* the formula below does only work for MCS values smaller than 32 */
-+	if (mcs >= 32) {
-+		RTW_INFO("Invalid mcs = %d\n", mcs);
-+		return 0;
-+	}
-+
-+	if (bw > 1) {
-+		RTW_INFO("Now HT only support bw = 0(20Mhz), 1(40Mhz)\n");
-+		return 0;
-+	}
-+
-+	modulation = mcs & 7;
-+	streams = (mcs >> 3) + 1;
-+
-+	bitrate = (bw == 1) ? 13500000 : 6500000;
-+
-+	if (modulation < 4)
-+		bitrate *= (modulation + 1);
-+	else if (modulation == 4)
-+		bitrate *= (modulation + 2);
-+	else
-+		bitrate *= (modulation + 3);
-+
-+	bitrate *= streams;
-+
-+	if (sgi)
-+		bitrate = (bitrate / 9) * 10;
-+
-+	return (bitrate + 50000) / 100000;
-+}
-+
-+/**
-+ * @bw: 0(20Mhz), 1(40Mhz), 2(80Mhz), 3(160Mhz)
-+ * @rate_idx: DESC_RATEXXXX & 0x7f
-+ * @sgi: DESC_RATEXXXX >> 7
-+ * Returns: bitrate in 100kbps
-+ */
-+u32 rtw_desc_rate_to_bitrate(u8 bw, u8 rate_idx, u8 sgi)
-+{
-+	u32 bitrate;
-+
-+	if (rate_idx <= DESC_RATE54M){
-+		u16 ofdm_rate[12] = {10, 20, 55, 110,
-+			60, 90, 120, 180, 240, 360, 480, 540};
-+
-+		bitrate = ofdm_rate[rate_idx];
-+	} else if ((DESC_RATEMCS0 <= rate_idx) &&
-+		   (rate_idx <= DESC_RATEMCS31)) {
-+		u8 mcs = rate_idx - DESC_RATEMCS0;
-+
-+		bitrate = rtw_get_ht_bitrate(mcs, bw, sgi);
-+	} else if ((DESC_RATEVHTSS1MCS0 <= rate_idx) &&
-+		   (rate_idx <= DESC_RATEVHTSS4MCS9)) {
-+		u8 mcs = (rate_idx - DESC_RATEVHTSS1MCS0) % 10;
-+		u8 nss = ((rate_idx - DESC_RATEVHTSS1MCS0) / 10) + 1;
-+
-+		bitrate = rtw_get_vht_bitrate(mcs, bw, nss, sgi);
-+	} else {
-+		/* TODO: 60Ghz */
-+		bitrate = 1;
-+	}
-+
-+	return bitrate;
-+}
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+u8 rtw_get_ch_utilization(_adapter *adapter)
-+{
-+	u16 clm = rtw_phydm_clm_ratio(adapter);
-+	u16 nhm = rtw_phydm_nhm_ratio(adapter);
-+	u16 ch_util;
-+
-+	ch_util = clm / 3 + (2 * (nhm / 3));
-+	/* For Multi-AP, scaling 0-100 to 0-255 */
-+	ch_util = 255 * ch_util / 100;
-+
-+	return (u8)ch_util;
-+}
-+
-+void rtw_ch_util_rpt(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	_adapter *iface;
-+	int i, j;
-+	u8 i_rpts = 0;
-+	u8 *ch_util;
-+	u8 **bssid;
-+	u8 threshold = GET_PRIMARY_ADAPTER(adapter)->ch_util_threshold;
-+	u8 need_rpt = 0;
-+
-+	if (threshold == 0)
-+		return;
-+
-+	ch_util = rtw_zmalloc(sizeof(u8) * dvobj->iface_nums);
-+	if (!ch_util)
-+		goto err_out;
-+	bssid = (u8 **) rtw_zmalloc(sizeof(u8 *) * dvobj->iface_nums);
-+	if (!bssid)
-+		goto err_out1;
-+	for (j = 0; j < dvobj->iface_nums; j++) {
-+		*(bssid + j) = (u8 *) rtw_zmalloc(sizeof(u8) * ETH_ALEN);
-+		if (!(*(bssid + j)))
-+			goto err_out2;
-+	}
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if ((iface) && MLME_IS_AP(iface)) {
-+			*(ch_util + i_rpts) = rtw_get_ch_utilization(iface);
-+			_rtw_memcpy(*(bssid + i_rpts), iface->mac_addr, ETH_ALEN);
-+
-+			if (*(ch_util + i_rpts) > threshold)
-+				need_rpt = 1;
-+
-+			i_rpts++;
-+		}
-+	}
-+
-+	if (need_rpt)
-+		rtw_nlrtw_ch_util_rpt(adapter, i_rpts, ch_util, bssid);
-+
-+	rtw_mfree(ch_util, sizeof(u8) * dvobj->iface_nums);
-+	for (i = 0; i < dvobj->iface_nums; i++)
-+		rtw_mfree(*(bssid + i), ETH_ALEN);
-+	rtw_mfree(bssid, sizeof(u8 *) * dvobj->iface_nums);
-+
-+	return;
-+
-+err_out2:
-+	for (i = 0; i < j; i++)
-+		rtw_mfree(*(bssid + i), sizeof(u8) * ETH_ALEN);
-+	rtw_mfree(bssid, sizeof(sizeof(u8 *) * dvobj->iface_nums));
-+err_out1:
-+	rtw_mfree(ch_util, sizeof(u8) * dvobj->iface_nums);
-+err_out:
-+	RTW_INFO("[%s] rtw_zmalloc fail\n", __func__);
-+}
-+#endif
-+
-diff --git a/drivers/staging/rtl8723cs/core/rtw_wnm.c b/drivers/staging/rtl8723cs/core/rtw_wnm.c
-new file mode 100644
-index 000000000000..293eb86b741a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_wnm.c
-@@ -0,0 +1,1098 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#ifndef RTW_WNM_DBG
-+	#define RTW_WNM_DBG	0
-+#endif
-+#if RTW_WNM_DBG
-+	#define RTW_WNM_INFO(fmt, arg...)	\
-+		RTW_INFO(fmt, arg)
-+	#define RTW_WNM_DUMP(str, data, len)	\
-+		RTW_INFO_DUMP(str, data, len)
-+#else
-+	#define RTW_WNM_INFO(fmt, arg...) do {} while (0)
-+	#define RTW_WNM_DUMP(str, data, len) do {} while (0)
-+#endif
-+
-+#ifdef CONFIG_RTW_WNM
-+
-+static u32 wnm_defualt_validity_time = 6000;
-+static u32 wnm_default_disassoc_time = 5000;
-+static u32 wnm_disassoc_wait_time = 500;
-+
-+/* for wifi test, need more validity time to wait scan done */
-+static u32 wnm_ext_validity_time = 4000;
-+
-+static void rtw_wmn_btm_cache_update(_adapter *padapter, struct btm_req_hdr *phdr)
-+{
-+	struct btm_rpt_cache *pcache = &(padapter->mlmepriv.nb_info.btm_cache);
-+
-+	pcache->dialog_token = phdr->dialog_token;
-+	pcache->req_mode = phdr->req_mode;
-+	pcache->disassoc_timer = le16_to_cpu(phdr->disassoc_timer);
-+
-+	if (phdr->validity_interval  > 0)
-+		pcache->validity_interval = phdr->validity_interval;
-+
-+	pcache->term_duration.id = phdr->term_duration.id;
-+	pcache->term_duration.len = phdr->term_duration.len;
-+	pcache->term_duration.tsf = le64_to_cpu(phdr->term_duration.tsf);
-+	pcache->term_duration.duration =  le16_to_cpu(phdr->term_duration.duration);
-+
-+	RTW_WNM_INFO("%s: req_mode(0x%02x), disassoc_timer(0x%04x), "
-+		"validity_interval(0x%02x %s), tsf(0x%llx), duration(0x%02x)\n",
-+		__func__, pcache->req_mode, pcache->disassoc_timer,
-+		pcache->validity_interval, (!phdr->validity_interval)?"default":"",
-+		pcache->term_duration.tsf,
-+		pcache->term_duration.duration);
-+
-+	if (pcache->validity_interval > 0) {
-+		pcache->validity_time = pcache->validity_interval * 100;
-+	#ifdef CONFIG_RTW_MBO
-+		if (rtw_mbo_wifi_logo_test(padapter))
-+			pcache->validity_time += wnm_ext_validity_time;
-+	#endif
-+	}
-+
-+	if (pcache->disassoc_timer > 0) {
-+		pcache->disassoc_time= pcache->disassoc_timer * 100;
-+	#ifdef CONFIG_RTW_MBO
-+		if (rtw_mbo_wifi_logo_test(padapter))
-+			pcache->disassoc_time += wnm_ext_validity_time;
-+	#endif
-+	}
-+
-+	pcache->req_stime = rtw_get_current_time();
-+
-+	RTW_WNM_INFO("%s: validity_time=%u, disassoc_time=%u\n",
-+		__func__, pcache->validity_time, pcache->disassoc_time);
-+}
-+
-+static u8 rtw_wnm_btm_candidate_validity(struct btm_rpt_cache *pcache, u8 flag)
-+{
-+	u8 is_validity =_TRUE;
-+	u32 req_validity_time = rtw_get_passing_time_ms(pcache->req_stime);
-+
-+	if ((flag & BIT(0)) && (req_validity_time > pcache->validity_time))
-+		is_validity = _FALSE;
-+
-+	if ((flag & BIT(1)) && (req_validity_time > pcache->disassoc_time))
-+		is_validity = _FALSE;
-+
-+	RTW_WNM_INFO("%s : validity=%u, rtime=%u, vtime=%u. dtime=%u\n",
-+			__func__, is_validity, req_validity_time,
-+			pcache->validity_time, pcache->disassoc_time);
-+	return is_validity;
-+}
-+
-+u8 rtw_wmn_btm_rsp_reason_decision(_adapter *padapter, u8* req_mode)
-+{
-+	struct recv_priv *precvpriv = &padapter->recvpriv;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	u8 reason = 0;
-+
-+	if (!rtw_wnm_btm_diff_bss(padapter)) {
-+		/* Reject - No suitable BSS transition candidates */
-+		reason = 7;
-+		goto candidate_remove;
-+	}
-+
-+#ifdef CONFIG_RTW_80211R
-+	if (rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM)) {
-+		/* Accept */
-+		reason = 0;
-+		goto under_survey;
-+	}	
-+#endif
-+
-+	if (((*req_mode) & DISASSOC_IMMINENT) == 0) {
-+		/* Reject - Unspecified reject reason */
-+		reason = 1;
-+		goto candidate_remove;
-+	}	
-+
-+	if (precvpriv->signal_strength_data.avg_val >= pmlmepriv->roam_rssi_threshold) {
-+		reason = 1;
-+		RTW_WNM_INFO("%s : Reject - under high roam rssi(%u, %u) \n",
-+			__func__, precvpriv->signal_strength_data.avg_val,
-+			pmlmepriv->roam_rssi_threshold);
-+		goto candidate_remove;
-+	}
-+
-+#ifdef CONFIG_RTW_80211R
-+under_survey:	
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) {
-+		RTW_WNM_INFO("%s reject due to _FW_UNDER_SURVEY\n", __func__);
-+		reason = 1;
-+	}
-+#endif
-+
-+candidate_remove:
-+	if (reason !=0)
-+		rtw_wnm_reset_btm_candidate(&pmlmepriv->nb_info);
-+
-+	return reason;
-+}
-+
-+static u32 rtw_wnm_btm_candidates_offset_get(u8* pframe)
-+{
-+	u32 offset = 0;
-+
-+	if (!pframe)
-+		return 0;
-+
-+	offset += 7;
-+
-+	/* BSS Termination Duration check */
-+	if (wnm_btm_bss_term_inc(pframe))
-+		offset += 12;
-+
-+	/* Session Information URL check*/
-+	if (wnm_btm_ess_disassoc_im(pframe)) {
-+		/*URL length field + URL variable length*/
-+		offset = 1 + *(pframe + offset);
-+	}
-+
-+	RTW_WNM_INFO("%s : hdr offset=%u\n", __func__, offset);
-+	return offset;
-+}
-+
-+static void rtw_wnm_btm_req_hdr_parsing(u8* pframe, struct btm_req_hdr *phdr)
-+{
-+	u8 *pos;
-+	u32 offset = 0;
-+
-+	if (!pframe || !phdr)
-+		return;
-+
-+	_rtw_memset(phdr, 0, sizeof(struct btm_req_hdr));
-+	phdr->dialog_token = wnm_btm_dialog_token(pframe);
-+	phdr->req_mode  = wnm_btm_req_mode(pframe);
-+	phdr->disassoc_timer = wnm_btm_disassoc_timer(pframe);
-+	phdr->validity_interval = wnm_btm_valid_interval(pframe);
-+	if (wnm_btm_bss_term_inc(pframe)) {
-+		pos = wnm_btm_term_duration_offset(pframe);
-+		if (*pos == WNM_BTM_TERM_DUR_SUBEID) {
-+			phdr->term_duration.id = *pos;
-+			phdr->term_duration.len = *(pos + 1);
-+			phdr->term_duration.tsf = *((u64*)(pos + 2));
-+			phdr->term_duration.duration= *((u16*)(pos + 10));
-+		} else
-+			RTW_WNM_INFO("%s : invaild BSS Termination Duration content!\n", __func__);
-+	}
-+
-+	RTW_WNM_INFO("WNM: req_mode(0x%02x), disassoc_timer(0x%04x), validity_interval(0x%02x)\n",
-+		phdr->req_mode, phdr->disassoc_timer, phdr->validity_interval);
-+	if (wnm_btm_bss_term_inc(pframe))
-+		RTW_WNM_INFO("WNM: tsf(0x%llx), duration(0x%4x)\n",
-+			phdr->term_duration.tsf, phdr->term_duration.duration);
-+}
-+
-+u8 rtw_wnm_btm_reassoc_req(_adapter *padapter)
-+{
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct roam_nb_info *pnb = &(pmlmepriv->nb_info);
-+	u8 breassoc = _FALSE;
-+
-+	if (_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)),
-+		pnb->roam_target_addr, ETH_ALEN)) {
-+		RTW_WNM_INFO("%s : bss "MAC_FMT" found in roam_target "MAC_FMT"\n",
-+			__func__, MAC_ARG(get_my_bssid(&(pmlmeinfo->network))),
-+			MAC_ARG(pnb->roam_target_addr));
-+
-+		breassoc = _TRUE;
-+	}
-+
-+	return breassoc;
-+}
-+
-+void rtw_wnm_roam_scan_hdl(void *ctx)
-+{
-+	_adapter *padapter = (_adapter *)ctx;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	if (rtw_is_scan_deny(padapter)) 
-+		RTW_WNM_INFO("%s: roam scan would abort by scan_deny!\n", __func__);
-+
-+#ifdef CONFIG_RTW_80211R
-+	if (rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM)) {
-+		pmlmepriv->need_to_roam = _TRUE;
-+		rtw_set_to_roam(padapter, padapter->registrypriv.max_roaming_times);
-+		RTW_WNM_INFO("%s : enable roaming\n", __func__);
-+	}
-+
-+	rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM);
-+#endif
-+}
-+
-+static void rtw_wnm_roam_scan(_adapter *padapter)
-+{
-+	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
-+
-+	if (rtw_is_scan_deny(padapter)) {
-+		_cancel_timer_ex(&pnb->roam_scan_timer);
-+		_set_timer(&pnb->roam_scan_timer, 1000);
-+	} else
-+		rtw_wnm_roam_scan_hdl((void *)padapter);
-+}
-+
-+void rtw_wnm_disassoc_chk_hdl(void *ctx)
-+{
-+	_adapter *padapter = (_adapter *)ctx;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct roam_nb_info *pnb = &(pmlmepriv->nb_info);
-+
-+	RTW_WNM_INFO("%s : expired\n", __func__);
-+	if (pnb->disassoc_waiting <= 0 ) {
-+		RTW_WNM_INFO("%s : btm roam is interrupted by disassoc\n", __func__);
-+		return;
-+	}
-+
-+	pnb->disassoc_waiting = _FALSE;
-+	rtw_wnm_roam_scan(padapter);
-+}
-+
-+u8 rtw_wnm_try_btm_roam_imnt(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct roam_nb_info *pnb = &(pmlmepriv->nb_info);
-+	struct btm_rpt_cache *pcache = &(pnb->btm_cache);
-+	u8 reason = 0, flag = 0;
-+
-+	if (!rtw_wnm_btm_preference_cap(padapter)) {
-+		RTW_WNM_INFO("%s : no btm candidate can be used!\n", __func__);
-+		return 1;
-+	}
-+
-+	flag = BIT(0) | BIT(1);
-+	if (!rtw_wnm_btm_candidate_validity(pcache, flag))
-+		return 1;
-+
-+#ifdef CONFIG_RTW_MBO
-+	if (!rtw_mbo_wifi_logo_test(padapter)
-+		&& !(pcache->req_mode & DISASSOC_IMMINENT)) {
-+		RTW_WNM_INFO("%s : non-disassoc imminet req\n",  __func__);
-+		return 1;
-+	}
-+#endif
-+
-+	RTW_WNM_INFO("%s : disassoc_waiting(%d)\n", __func__, pnb->disassoc_waiting);
-+	if (pnb->disassoc_waiting) {
-+		_cancel_timer_ex(&pnb->disassoc_chk_timer);
-+		pnb->disassoc_waiting = _FALSE;
-+		rtw_wnm_roam_scan_hdl((void *)padapter);
-+	} else if (!pnb->disassoc_waiting)
-+		RTW_WNM_INFO("%s : waiting for btm roaming start/finish\n", __func__);
-+	else
-+		reason = 1;
-+
-+	return reason;
-+}
-+
-+void rtw_wnm_process_btm_req(_adapter *padapter, u8* pframe, u32 frame_len)
-+{
-+	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
-+	struct btm_req_hdr req_hdr;
-+	u8 *ptr, reason;
-+	u32 elem_len, offset;
-+
-+	rtw_wnm_btm_req_hdr_parsing(pframe, &req_hdr);
-+	offset = rtw_wnm_btm_candidates_offset_get(pframe);
-+	if (offset == 0)
-+		return;
-+
-+	if ((frame_len - offset) <= 15) {
-+		RTW_INFO("WNM : Reject - no suitable BSS transition candidates!\n");
-+		rtw_wnm_issue_action(padapter, 
-+			RTW_WLAN_ACTION_WNM_BTM_RSP, 7, req_hdr.dialog_token);
-+		return;
-+	}
-+
-+	rtw_wmn_btm_cache_update(padapter, &req_hdr);
-+
-+	ptr = (pframe + offset);
-+	elem_len = (frame_len - offset);
-+	rtw_wnm_btm_candidates_survey(padapter, ptr, elem_len, _TRUE);
-+	reason = rtw_wmn_btm_rsp_reason_decision(padapter, &pframe[3]);
-+
-+#ifdef CONFIG_RTW_MBO
-+	/* for wifi-test; AP2 could power-off when BTM-req received */
-+	if ((reason > 0) && (rtw_mbo_wifi_logo_test(padapter))) {
-+		_rtw_memcpy(pnb->roam_target_addr, pnb->nb_rpt[0].bssid, ETH_ALEN);
-+		RTW_WNM_INFO("%s : used report 0 as roam_target_addr(reason=%u)\n",
-+			__func__, reason);
-+		reason = 0;
-+		pnb->preference_en = _TRUE;
-+		pnb->nb_rpt_valid = _FALSE;
-+	}
-+#endif
-+
-+	rtw_wnm_issue_action(padapter, 
-+		RTW_WLAN_ACTION_WNM_BTM_RSP, reason, req_hdr.dialog_token);
-+
-+	if (reason == 0) {
-+		pnb->disassoc_waiting = _TRUE;
-+		_set_timer(&pnb->disassoc_chk_timer, wnm_disassoc_wait_time);
-+	}
-+
-+}
-+
-+void rtw_wnm_reset_btm_candidate(struct roam_nb_info *pnb)
-+{
-+	pnb->preference_en = _FALSE;
-+	_rtw_memset(pnb->roam_target_addr, 0, ETH_ALEN);
-+}
-+
-+void rtw_wnm_reset_btm_cache(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct roam_nb_info *pnb = &(pmlmepriv->nb_info);
-+	struct btm_rpt_cache *pcache = &(pnb->btm_cache);
-+	u8 flag = 0;
-+
-+	flag |= BIT(0);
-+	if (rtw_wnm_btm_candidate_validity(pcache, flag))
-+		return;
-+
-+	rtw_wnm_reset_btm_candidate(pnb);
-+	_rtw_memset(pcache, 0, sizeof(struct btm_rpt_cache));
-+	pcache->validity_time = wnm_defualt_validity_time;
-+	pcache->disassoc_time= wnm_default_disassoc_time;
-+
-+#ifdef CONFIG_RTW_80211R
-+	if (rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM)) {
-+		pmlmepriv->need_to_roam = _FALSE;
-+		rtw_set_to_roam(padapter, 0);
-+		RTW_WNM_INFO("%s : disabled roaming\n", __func__);
-+	}
-+#endif
-+}
-+
-+void rtw_wnm_reset_btm_state(_adapter *padapter)
-+{
-+	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
-+
-+	pnb->last_nb_rpt_entries = 0;
-+	pnb->nb_rpt_is_same = _TRUE;
-+	pnb->nb_rpt_valid = _FALSE;
-+	pnb->nb_rpt_ch_list_num = 0;
-+	pnb->disassoc_waiting = -1;
-+	_rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt));
-+	_rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));
-+	rtw_wnm_reset_btm_cache(padapter);
-+}
-+
-+u32 rtw_wnm_btm_rsp_candidates_sz_get(
-+	_adapter *padapter, u8* pframe, u32 frame_len)
-+{
-+	u32 num = 0, sz = 0;
-+	u8 status;
-+	u8 *ptr;
-+
-+	if (!pframe || (frame_len <= 5))
-+		goto exit;
-+
-+	status = wnm_btm_rsp_status(pframe);
-+	if (((status != 0) && (status != 6)) || (frame_len < 23))
-+		goto exit;
-+
-+	if (status == 0)
-+		num = (frame_len - 5 - ETH_ALEN)/18;
-+	else
-+		num = (frame_len - 5)/18;
-+	sz = sizeof(struct wnm_btm_cant) * num;
-+exit:
-+	RTW_WNM_INFO("WNM: %u candidates(sz=%u) in BTM rsp\n", num, sz);
-+	return sz;
-+}
-+
-+void rtw_wnm_process_btm_rsp(_adapter *padapter,
-+	u8* pframe, u32 frame_len, struct btm_rsp_hdr *prsp)
-+{
-+	prsp->dialog_token = wnm_btm_dialog_token(pframe);
-+	prsp->status = wnm_btm_rsp_status(pframe);
-+	prsp->termination_delay = wnm_btm_rsp_term_delay(pframe);
-+
-+	if ((pframe == NULL) || (frame_len == 0))
-+		return;
-+
-+	prsp->status = *(pframe + 3);
-+	prsp->termination_delay = *(pframe + 4);
-+
-+	/* no Target BSSID & Candidate in frame */
-+	if (frame_len <= 5)
-+		return;
-+
-+	/* accept */
-+	if ((prsp->status == 0) && (frame_len >= 11))
-+		_rtw_memcpy(prsp->bssid, (pframe + 5), ETH_ALEN);
-+
-+	/* STA BSS Transition Candidate List provided,
-+		and at least one NB report exist */
-+	if (((prsp->status == 0) || (prsp->status == 6)) && (frame_len >= 23)) {
-+		struct wnm_btm_cant cant;
-+		u8 *ptr, *pend;
-+		u32 idx = 0;
-+
-+		ptr = pframe + 5;
-+		if (prsp->status == 0)
-+			ptr += ETH_ALEN;
-+
-+		pend = ptr + frame_len;
-+		prsp->candidates_num = 0;
-+		while (ptr < pend) {
-+			if (*ptr != RTW_WLAN_ACTION_WNM_NB_RPT_ELEM)
-+				break;
-+			_rtw_memset(&cant, 0, sizeof(cant));
-+			cant.nb_rpt.id = *ptr;
-+			cant.nb_rpt.len = *(ptr + 1);
-+			_rtw_memcpy(cant.nb_rpt.bssid, (ptr + 2), ETH_ALEN);
-+			cant.nb_rpt.bss_info = *((u32 *)(ptr + 8));
-+			cant.nb_rpt.reg_class = *(ptr + 12);
-+			cant.nb_rpt.ch_num = *(ptr + 13);
-+			cant.nb_rpt.phy_type= *(ptr + 14);
-+
-+			if (*(ptr + 15) == WNM_BTM_CAND_PREF_SUBEID)
-+				cant.preference = *(ptr + 17);
-+			ptr = ptr + cant.nb_rpt.len + 2;
-+			if (prsp->pcandidates) {
-+				prsp->candidates_num++;
-+				_rtw_memcpy((prsp->pcandidates + sizeof(cant) * idx), &cant, sizeof(cant));
-+			}
-+
-+			idx++;
-+			RTW_WNM_INFO("WNM: btm rsp candidate bssid("MAC_FMT
-+				") ,bss_info(0x%04X), reg_class(0x%02X), ch(%d),"
-+				" phy_type(0x%02X), preference(0x%02X)\n",
-+				MAC_ARG(cant.nb_rpt.bssid), cant.nb_rpt.bss_info,
-+				cant.nb_rpt.reg_class, cant.nb_rpt.ch_num,
-+				cant.nb_rpt.phy_type, cant.preference);
-+			if ((prsp->pcandidates) && (prsp->candidates_num > 0))
-+				RTW_WNM_DUMP("WNM candidates: ", prsp->pcandidates,
-+						(sizeof(struct wnm_btm_cant) * prsp->candidates_num));
-+		}
-+	}
-+
-+}
-+
-+void rtw_wnm_hdr_init(_adapter *padapter,
-+	struct xmit_frame *pactionframe, u8 *pmac,
-+	u8 action, u8 **pcontent)
-+{
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct pkt_attrib *pattrib;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	u16 *pfctrl;
-+	u8 category;
-+
-+	pattrib = &(pactionframe->attrib);
-+	update_mgntframe_attrib(padapter, pattrib);
-+	_rtw_memset(pactionframe->buf_addr, 0, (WLANHDR_OFFSET + TXDESC_OFFSET));
-+
-+	*pcontent = (u8 *)(pactionframe->buf_addr + TXDESC_OFFSET);
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)(*pcontent);
-+	pfctrl = &(pwlanhdr->frame_ctl);
-+	*(pfctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, pmac, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(*pcontent, WIFI_ACTION);
-+
-+	*pcontent += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	category = RTW_WLAN_CATEGORY_WNM;
-+	*pcontent = rtw_set_fixed_ie(*pcontent, 1, &(category), &(pattrib->pktlen));
-+	*pcontent = rtw_set_fixed_ie(*pcontent, 1, &(action), &(pattrib->pktlen));
-+}
-+
-+void rtw_wnm_build_btm_req_ies(_adapter *padapter,
-+	u8 **pframe, struct pkt_attrib *pattrib,
-+	struct btm_req_hdr *phdr, u8 *purl, u32 url_len,
-+	u8 *pcandidates, u8 candidate_cnt)
-+{
-+	int i;
-+
-+	*pframe = rtw_set_fixed_ie(*pframe, 1,
-+				&phdr->dialog_token, &(pattrib->pktlen));
-+	*pframe = rtw_set_fixed_ie(*pframe, 1,
-+				&phdr->req_mode, &(pattrib->pktlen));
-+	*pframe = rtw_set_fixed_ie(*pframe, 2,
-+				(u8 *)&phdr->disassoc_timer, &(pattrib->pktlen));
-+	*pframe = rtw_set_fixed_ie(*pframe, 1,
-+				&phdr->validity_interval, &(pattrib->pktlen));
-+
-+	if (phdr->req_mode & BSS_TERMINATION_INCLUDED) {
-+		*pframe = rtw_set_fixed_ie(*pframe, 1,
-+					&phdr->term_duration.id, &(pattrib->pktlen));
-+		*pframe = rtw_set_fixed_ie(*pframe, 1,
-+					&phdr->term_duration.len, &(pattrib->pktlen));
-+		*pframe = rtw_set_fixed_ie(*pframe, 8,
-+					(u8 *)&phdr->term_duration.tsf, &(pattrib->pktlen));
-+		*pframe = rtw_set_fixed_ie(*pframe, 2,
-+					(u8 *)&phdr->term_duration.duration, &(pattrib->pktlen));
-+	}
-+
-+	if ((purl != NULL) && (url_len > 0) &&
-+		(phdr->req_mode & ESS_DISASSOC_IMMINENT)) {
-+		*pframe = rtw_set_fixed_ie(*pframe, 1,
-+					(u8 *)&url_len, &(pattrib->pktlen));
-+		*pframe = rtw_set_fixed_ie(*pframe,
-+					url_len, purl, &(pattrib->pktlen));
-+	}
-+
-+	if ((pcandidates != NULL) && (candidate_cnt > 0)) {
-+		for (i=0; i<candidate_cnt; i++) {
-+			struct wnm_btm_cant *pcandidate = \
-+				((struct wnm_btm_cant *)pcandidates) + i;
-+			struct nb_rpt_hdr *prpt = &(pcandidate->nb_rpt);
-+
-+			*pframe = rtw_set_fixed_ie(*pframe, 1,
-+						&pcandidate->nb_rpt.id, &(pattrib->pktlen));
-+			*pframe = rtw_set_fixed_ie(*pframe, 1,
-+						&pcandidate->nb_rpt.len, &(pattrib->pktlen));
-+			*pframe = rtw_set_fixed_ie(*pframe, ETH_ALEN,
-+						pcandidate->nb_rpt.bssid, &(pattrib->pktlen));
-+			*pframe = rtw_set_fixed_ie(*pframe, 4,
-+						(u8 *)&pcandidate->nb_rpt.bss_info, &(pattrib->pktlen));
-+			*pframe = rtw_set_fixed_ie(*pframe, 1,
-+						&pcandidate->nb_rpt.reg_class, &(pattrib->pktlen));
-+			*pframe = rtw_set_fixed_ie(*pframe, 1,
-+						&pcandidate->nb_rpt.ch_num, &(pattrib->pktlen));
-+			*pframe = rtw_set_fixed_ie(*pframe, 1,
-+						&pcandidate->nb_rpt.phy_type, &(pattrib->pktlen));
-+			*pframe = rtw_set_ie(*pframe, WNM_BTM_CAND_PREF_SUBEID, 1,
-+					(u8 *)&pcandidate->preference, &(pattrib->pktlen));
-+		}
-+	}
-+
-+}
-+
-+void rtw_wnm_issue_btm_req(_adapter *padapter,
-+	u8 *pmac, struct btm_req_hdr *phdr, u8 *purl, u32 url_len,
-+	u8 *pcandidates, u8 candidate_cnt)
-+{
-+	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
-+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
-+	struct xmit_frame *pmgntframe;
-+	struct pkt_attrib *pattrib;
-+	u8 action, *pframe, dialog_token = 0;
-+
-+	if (!pmac || is_zero_mac_addr(pmac)
-+		|| is_broadcast_mac_addr(pmac))
-+		return ;
-+
-+	if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
-+		return ;
-+
-+	rtw_wnm_hdr_init(padapter, pmgntframe, pmac,
-+		RTW_WLAN_ACTION_WNM_BTM_REQ, &pframe);
-+
-+	pattrib = &(pmgntframe->attrib);
-+	rtw_wnm_build_btm_req_ies(padapter, &pframe, pattrib,
-+		phdr, purl, url_len, pcandidates, candidate_cnt);
-+
-+	if (0) {
-+		u8 *__p =  (u8 *)(pmgntframe->buf_addr + TXDESC_OFFSET);
-+		RTW_WNM_DUMP("WNM BTM REQ :", __p, pattrib->pktlen);
-+	}
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+	dump_mgntframe(padapter, pmgntframe);
-+	RTW_INFO("WNM: BSS Transition Management Request sent\n");
-+}
-+
-+void rtw_wnm_issue_action(_adapter *padapter,
-+	u8 action, u8 reason, u8 dialog)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct xmit_frame *pmgntframe;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	struct pkt_attrib *pattrib;
-+	u8 category, termination_delay, *pframe, dialog_token = 0;
-+#ifdef CONFIG_RTW_MBO
-+	u8 mbo_trans_rej_res = 1;  /* Unspecified reason */
-+	u8 mbo_notif_req_type ;
-+#endif
-+	u16 *fctrl;
-+
-+	if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
-+		return ;
-+	
-+	pattrib = &(pmgntframe->attrib);
-+	update_mgntframe_attrib(padapter, pattrib);
-+	_rtw_memset(pmgntframe->buf_addr, 0, (WLANHDR_OFFSET + TXDESC_OFFSET));
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr + TXDESC_OFFSET);
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	category = RTW_WLAN_CATEGORY_WNM;
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+
-+	switch (action) {
-+		case RTW_WLAN_ACTION_WNM_BTM_QUERY:
-+			dialog_token++;
-+			pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen));
-+			pframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen));
-+			RTW_INFO("WNM: BSS Transition Management Query sent\n");
-+			break;
-+		case RTW_WLAN_ACTION_WNM_BTM_RSP:
-+			dialog_token = dialog;
-+			termination_delay = 0;
-+			pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen));
-+			pframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen));
-+			pframe = rtw_set_fixed_ie(pframe, 1, &(termination_delay), &(pattrib->pktlen));
-+			if (!reason && !is_zero_mac_addr(pmlmepriv->nb_info.roam_target_addr)) {
-+				pframe = rtw_set_fixed_ie(pframe, 6, 
-+					pmlmepriv->nb_info.roam_target_addr, &(pattrib->pktlen));
-+			}
-+
-+#ifdef CONFIG_RTW_MBO
-+			rtw_mbo_build_trans_reject_reason_attr(padapter, 
-+				&pframe, pattrib, &mbo_trans_rej_res);
-+#endif
-+
-+			RTW_INFO("WNM: BSS Transition Management Response sent(reason:%d)\n", reason);			
-+			break;
-+		case RTW_WLAN_ACTION_WNM_NOTIF_REQ:
-+#ifdef CONFIG_RTW_MBO			
-+			dialog_token++;
-+			mbo_notif_req_type = WLAN_EID_VENDOR_SPECIFIC;
-+			pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen));
-+			pframe = rtw_set_fixed_ie(pframe, 1, &(mbo_notif_req_type), &(pattrib->pktlen));
-+			rtw_mbo_build_wnm_notification(padapter, &pframe, pattrib);
-+			RTW_INFO("WNM: Notification request sent\n");
-+#endif
-+			break;
-+		default:
-+			goto exit;
-+	}	
-+	
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+exit:	
-+	return;
-+}
-+
-+/* argument req_ie@cfg80211_roamed()/cfg80211_connect_result()
-+	is association request IEs format. if driver used reassoc-req format,
-+	RSN IE could not be parsed @supplicant process */
-+void rtw_wnm_update_reassoc_req_ie(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	u32 dup_len, offset;
-+	u8 *pdup;
-+
-+	if (!pmlmepriv->assoc_req || !pmlmepriv->assoc_req_len)
-+		return;
-+
-+	/* total len is assoc req len without Current AP Field*/
-+	dup_len = pmlmepriv->assoc_req_len - ETH_ALEN;
-+
-+	/* offset is a len of 80211 header +  capability(2B) + listen interval(2B) */
-+	offset =  sizeof(struct rtw_ieee80211_hdr_3addr) + 4;
-+
-+	pdup = rtw_zmalloc(dup_len);
-+	if (pdup) {
-+		/* remove Current AP Field @reassoc req IE */
-+		_rtw_memcpy(pdup, pmlmepriv->assoc_req, offset);
-+		_rtw_memcpy(pdup + offset, pmlmepriv->assoc_req + offset + ETH_ALEN,
-+				pmlmepriv->assoc_req_len - offset);
-+		rtw_buf_update(&pmlmepriv->assoc_req,
-+			&pmlmepriv->assoc_req_len, pdup, dup_len);
-+		rtw_mfree(pdup, dup_len);
-+	}
-+}
-+#endif /* CONFIG_RTW_WNM */
-+
-+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
-+void rtw_roam_nb_info_init(_adapter *padapter)
-+{
-+	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
-+	struct btm_rpt_cache *pcache = &(pnb->btm_cache);
-+	
-+	_rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt));
-+	_rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));
-+	_rtw_memset(&pnb->roam_target_addr, 0, ETH_ALEN);
-+	pnb->nb_rpt_valid = _FALSE;
-+	pnb->nb_rpt_ch_list_num = 0;
-+	pnb->preference_en = _FALSE;
-+	pnb->nb_rpt_is_same = _TRUE;
-+	pnb->last_nb_rpt_entries = 0;
-+	pnb->disassoc_waiting = -1;
-+#ifdef CONFIG_RTW_WNM
-+	pnb->features = 0;
-+	/* pnb->features |= RTW_WNM_FEATURE_BTM_REQ_EN; */
-+
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+	pnb->features |= RTW_WNM_FEATURE_BTM_REQ_EN;
-+#endif
-+
-+	rtw_init_timer(&pnb->roam_scan_timer, 
-+		padapter, rtw_wnm_roam_scan_hdl, 
-+		padapter);
-+	rtw_init_timer(&pnb->disassoc_chk_timer,
-+		padapter, rtw_wnm_disassoc_chk_hdl,
-+		padapter);
-+
-+	_rtw_memset(pcache, 0, sizeof(struct btm_rpt_cache));
-+	pcache->validity_time = wnm_defualt_validity_time;
-+	pcache->disassoc_time= wnm_default_disassoc_time ;
-+#endif
-+}
-+
-+u8 rtw_roam_nb_scan_list_set(
-+	_adapter *padapter, struct sitesurvey_parm *pparm)
-+{
-+	u8 ret = _FALSE;
-+	u32 i;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct roam_nb_info *pnb = &(pmlmepriv->nb_info);
-+
-+#ifdef CONFIG_RTW_80211R
-+	if (!rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)
-+		&& !rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM))
-+		return ret;
-+#endif
-+
-+	if (!pmlmepriv->need_to_roam)
-+		return ret;
-+
-+	if ((!pmlmepriv->nb_info.nb_rpt_valid) || (!pnb->nb_rpt_ch_list_num))
-+		return ret;
-+
-+	if (!pparm)
-+		return ret;
-+
-+	rtw_init_sitesurvey_parm(padapter, pparm);
-+	if (rtw_roam_busy_scan(padapter, pnb)) {
-+		pparm->ch_num = 1;
-+		pparm->ch[pmlmepriv->ch_cnt].hw_value = 
-+			pnb->nb_rpt_ch_list[pmlmepriv->ch_cnt].hw_value;
-+		pmlmepriv->ch_cnt++;
-+		ret = _TRUE;
-+
-+		RTW_WNM_INFO("%s: ch_cnt=%u, (%u)hw_value=%u\n",
-+			__func__, pparm->ch_num, pmlmepriv->ch_cnt,
-+			pparm->ch[pmlmepriv->ch_cnt].hw_value);
-+
-+		if (pmlmepriv->ch_cnt == pnb->nb_rpt_ch_list_num) {
-+			pmlmepriv->nb_info.nb_rpt_valid = _FALSE;
-+			pmlmepriv->ch_cnt = 0;
-+		}
-+		goto set_bssid_list;
-+	}
-+
-+	pparm->ch_num = (pnb->nb_rpt_ch_list_num > RTW_CHANNEL_SCAN_AMOUNT)?
-+		(RTW_CHANNEL_SCAN_AMOUNT):(pnb->nb_rpt_ch_list_num);
-+	for (i=0; i<pparm->ch_num; i++) {
-+		pparm->ch[i].hw_value = pnb->nb_rpt_ch_list[i].hw_value;
-+		pparm->ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN;
-+	}
-+
-+	pmlmepriv->nb_info.nb_rpt_valid = _FALSE;
-+	pmlmepriv->ch_cnt = 0;		
-+	ret = _TRUE;
-+
-+set_bssid_list:
-+	rtw_set_802_11_bssid_list_scan(padapter, pparm);
-+	return ret;
-+}
-+
-+static u8 rtw_wnm_nb_elem_parsing(
-+	u8* pdata, u32 data_len, u8 from_btm, 
-+	u32 *nb_rpt_num, u8 *nb_rpt_is_same,
-+	struct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates)
-+{
-+	u8 bfound = _FALSE, ret = _SUCCESS;
-+	u8 *ptr, *pend, *op;
-+	u32 elem_len, subelem_len, op_len;
-+	u32 i, nb_rpt_entries = 0;
-+	struct nb_rpt_hdr *pie;
-+	struct wnm_btm_cant *pcandidate;
-+
-+	if ((!pdata) || (!pnb))
-+		return _FAIL;
-+
-+	if ((from_btm) && (!pcandidates))
-+		return _FAIL;
-+
-+	ptr = pdata;
-+	pend = ptr + data_len;
-+	elem_len = data_len;
-+	subelem_len = (u32)*(pdata+1);
-+
-+	for (i=0; i < RTW_MAX_NB_RPT_NUM; i++) {
-+		if (((ptr + 7) > pend) || (elem_len < subelem_len)) 
-+			break;
-+
-+		if (*ptr != RTW_WLAN_ACTION_WNM_NB_RPT_ELEM) {
-+			RTW_WNM_INFO("WNM: end of data(0x%2x)!\n", *ptr);
-+			break;
-+		}
-+
-+		pie = (struct nb_rpt_hdr *)ptr;		
-+		if (from_btm) {
-+			op = rtw_get_ie((u8 *)(ptr+15), 
-+				WNM_BTM_CAND_PREF_SUBEID, 
-+				&op_len, (subelem_len - 15));
-+		}
-+
-+		ptr = (u8 *)(ptr + subelem_len + 2);
-+		elem_len -= (subelem_len +2);
-+		subelem_len = *(ptr+1);
-+		if (from_btm) {
-+			pcandidate = (pcandidates + i);
-+			_rtw_memcpy(&pcandidate->nb_rpt, pie, sizeof(struct nb_rpt_hdr));
-+			if (op && (op_len !=0)) {
-+				pcandidate->preference = *(op + 2);
-+				bfound = _TRUE;
-+			} else
-+				pcandidate->preference = 0;
-+
-+			RTW_WNM_INFO("WNM: preference check bssid("MAC_FMT
-+				") ,bss_info(0x%04X), reg_class(0x%02X), ch(%d),"
-+				" phy_type(0x%02X), preference(0x%02X)\n",
-+				MAC_ARG(pcandidate->nb_rpt.bssid), pcandidate->nb_rpt.bss_info, 
-+				pcandidate->nb_rpt.reg_class, pcandidate->nb_rpt.ch_num, 
-+				pcandidate->nb_rpt.phy_type, pcandidate->preference);
-+		} else {
-+			if (_rtw_memcmp(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr)) == _FALSE)
-+				*nb_rpt_is_same = _FALSE;
-+			_rtw_memcpy(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr));
-+		}
-+		nb_rpt_entries++;			
-+	} 
-+
-+	if (from_btm) 
-+		pnb->preference_en = (bfound)?_TRUE:_FALSE; 
-+
-+	*nb_rpt_num = nb_rpt_entries;
-+	return ret;
-+}	
-+
-+/* selection sorting based on preference value
-+ * IN : 		nb_rpt_entries - candidate num
-+ * IN/OUT :	pcandidates	- candidate list
-+ * return : TRUE - means pcandidates is updated.  
-+ */
-+static u8 rtw_wnm_candidates_sorting(
-+	u32 nb_rpt_entries, struct wnm_btm_cant *pcandidates)
-+{
-+	u8 updated = _FALSE;
-+	u32 i, j, pos;
-+	struct wnm_btm_cant swap;
-+	struct wnm_btm_cant *pcant_1, *pcant_2;
-+
-+	if ((!nb_rpt_entries) || (!pcandidates))
-+		return updated;
-+
-+	for (i=0; i < (nb_rpt_entries - 1); i++) {
-+		pos = i;
-+		for (j=(i + 1); j < nb_rpt_entries; j++) {
-+			pcant_1 = pcandidates+pos;
-+			pcant_2 = pcandidates+j;
-+			if ((pcant_1->preference) < (pcant_2->preference))
-+				pos = j;
-+		}
-+
-+		if (pos != i) {
-+			updated = _TRUE;
-+			_rtw_memcpy(&swap, (pcandidates+i), sizeof(struct wnm_btm_cant));
-+			_rtw_memcpy((pcandidates+i), (pcandidates+pos), sizeof(struct wnm_btm_cant));
-+			_rtw_memcpy((pcandidates+pos), &swap, sizeof(struct wnm_btm_cant));
-+		}
-+	}	
-+	return updated;
-+}	
-+
-+static void rtw_wnm_nb_info_update(
-+	u32 nb_rpt_entries, u8 from_btm, 
-+	struct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates, 
-+	u8 *nb_rpt_is_same)
-+{
-+	u8 is_found;
-+	u32 i, j;
-+	struct wnm_btm_cant *pcand;
-+
-+	if (!pnb)
-+		return;
-+
-+	pnb->nb_rpt_ch_list_num = 0;
-+	for (i=0; i<nb_rpt_entries; i++) {
-+		is_found = _FALSE;
-+		if (from_btm) {
-+			pcand = (pcandidates+i);
-+			if (_rtw_memcmp(&pnb->nb_rpt[i], &pcand->nb_rpt,
-+					sizeof(struct nb_rpt_hdr)) == _FALSE)
-+				*nb_rpt_is_same = _FALSE;
-+			_rtw_memcpy(&pnb->nb_rpt[i], &pcand->nb_rpt, sizeof(struct nb_rpt_hdr));
-+		}
-+
-+		RTW_WNM_INFO("WNM: bssid(" MAC_FMT
-+			") , bss_info(0x%04X), reg_class(0x%02X), ch_num(%d), phy_type(0x%02X)\n",
-+			MAC_ARG(pnb->nb_rpt[i].bssid), pnb->nb_rpt[i].bss_info, 
-+			pnb->nb_rpt[i].reg_class, pnb->nb_rpt[i].ch_num, 
-+			pnb->nb_rpt[i].phy_type);
-+
-+		if (pnb->nb_rpt[i].ch_num == 0)
-+			continue;
-+
-+		for (j=0; j<nb_rpt_entries; j++) {
-+			if (pnb->nb_rpt[i].ch_num == pnb->nb_rpt_ch_list[j].hw_value) {
-+				is_found = _TRUE;
-+				break;
-+			}
-+		}
-+							
-+		if (!is_found) {
-+			pnb->nb_rpt_ch_list[pnb->nb_rpt_ch_list_num].hw_value = pnb->nb_rpt[i].ch_num;
-+				pnb->nb_rpt_ch_list_num++;
-+		}
-+	}
-+}
-+
-+static void rtw_wnm_btm_candidate_select(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
-+	struct wlan_network *pnetwork;
-+	u8 bfound = _FALSE;
-+	u8 ignore_currrent = _FALSE;
-+	u32 i;
-+
-+#ifdef CONFIG_RTW_80211R
-+	if (rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM))
-+		ignore_currrent = _TRUE;
-+#endif
-+
-+	for (i = 0; i < pnb->last_nb_rpt_entries; i++) {
-+		if (ignore_currrent &&
-+			(_rtw_memcmp(pnb->nb_rpt[i].bssid,\
-+				padapter->mlmepriv.cur_network.network.MacAddress, ETH_ALEN))) {
-+			RTW_WNM_INFO("WNM : ignore candidate "MAC_FMT" for it's connected(%u)!\n",
-+					MAC_ARG(pnb->nb_rpt[i].bssid), i);	
-+			continue;
-+		}
-+		
-+		pnetwork = rtw_find_network(
-+				&(pmlmepriv->scanned_queue), 
-+				pnb->nb_rpt[i].bssid);
-+
-+		if (pnetwork) {
-+			bfound = _TRUE;
-+			break;
-+		}
-+	}
-+
-+	if (bfound) {
-+		_rtw_memcpy(pnb->roam_target_addr, pnb->nb_rpt[i].bssid, ETH_ALEN);
-+		RTW_INFO("WNM : select btm entry(%d) - %s("MAC_FMT", ch:%u) rssi:%d\n"
-+			, i
-+			, pnetwork->network.Ssid.Ssid
-+			, MAC_ARG(pnetwork->network.MacAddress)
-+			, pnetwork->network.Configuration.DSConfig
-+			, (int)pnetwork->network.Rssi);
-+	} else 
-+		_rtw_memset(pnb->roam_target_addr,0, ETH_ALEN);
-+}
-+
-+u32 rtw_wnm_btm_candidates_survey(
-+	_adapter *padapter, u8* pframe, u32 elem_len, u8 from_btm)
-+{
-+	struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
-+	struct wnm_btm_cant *pcandidate_list = NULL;
-+	u8 nb_rpt_is_same = _TRUE;
-+	u32	ret = _FAIL;
-+	u32 nb_rpt_entries = 0;	
-+
-+	if (from_btm) {
-+		u32 mlen = sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM;
-+		pcandidate_list = (struct wnm_btm_cant *)rtw_malloc(mlen);
-+		if (pcandidate_list == NULL) 
-+			goto exit;				
-+	}
-+
-+	/*clean the status set last time*/
-+	_rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));
-+	pnb->nb_rpt_valid = _FALSE;
-+	if (!rtw_wnm_nb_elem_parsing(
-+			pframe, elem_len, from_btm, 
-+			&nb_rpt_entries, &nb_rpt_is_same,
-+			pnb, pcandidate_list))
-+		goto exit;
-+
-+	if (nb_rpt_entries != 0) {
-+		if ((from_btm) && (rtw_wnm_btm_preference_cap(padapter)))
-+			rtw_wnm_candidates_sorting(nb_rpt_entries, pcandidate_list);
-+
-+		rtw_wnm_nb_info_update(
-+			nb_rpt_entries, from_btm, 
-+			pnb, pcandidate_list, &nb_rpt_is_same);
-+	}
-+
-+	RTW_WNM_INFO("nb_rpt_is_same = %d, nb_rpt_entries = %d, last_nb_rpt_entries = %d\n",
-+		nb_rpt_is_same, nb_rpt_entries, pnb->last_nb_rpt_entries);
-+	if ((nb_rpt_is_same == _TRUE) && (nb_rpt_entries == pnb->last_nb_rpt_entries))
-+		pnb->nb_rpt_is_same = _TRUE;
-+	else {
-+		pnb->nb_rpt_is_same = _FALSE;
-+		pnb->last_nb_rpt_entries = nb_rpt_entries;
-+	}
-+
-+	if ((from_btm) && (nb_rpt_entries != 0))
-+		rtw_wnm_btm_candidate_select(padapter);
-+	
-+	pnb->nb_rpt_valid = _TRUE;
-+	ret = _SUCCESS;
-+
-+exit:
-+	if (from_btm && pcandidate_list)
-+		rtw_mfree((u8 *)pcandidate_list, sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM);
-+	
-+	return ret;
-+}
-+
-+#endif /*defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) */
-+
-diff --git a/drivers/staging/rtl8723cs/core/rtw_xmit.c b/drivers/staging/rtl8723cs/core/rtw_xmit.c
-new file mode 100644
-index 000000000000..10e831db3e99
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/rtw_xmit.c
-@@ -0,0 +1,6638 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_XMIT_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+static u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 };
-+static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 };
-+
-+static void _init_txservq(struct tx_servq *ptxservq)
-+{
-+	_rtw_init_listhead(&ptxservq->tx_pending);
-+	_rtw_init_queue(&ptxservq->sta_pending);
-+	ptxservq->qcnt = 0;
-+}
-+
-+
-+void	_rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv)
-+{
-+
-+
-+	_rtw_memset((unsigned char *)psta_xmitpriv, 0, sizeof(struct sta_xmit_priv));
-+
-+	_rtw_spinlock_init(&psta_xmitpriv->lock);
-+
-+	/* for(i = 0 ; i < MAX_NUMBLKS; i++) */
-+	/*	_init_txservq(&(psta_xmitpriv->blk_q[i])); */
-+
-+	_init_txservq(&psta_xmitpriv->be_q);
-+	_init_txservq(&psta_xmitpriv->bk_q);
-+	_init_txservq(&psta_xmitpriv->vi_q);
-+	_init_txservq(&psta_xmitpriv->vo_q);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	_init_txservq(&psta_xmitpriv->mgmt_q);
-+#endif
-+	_rtw_init_listhead(&psta_xmitpriv->legacy_dz);
-+	_rtw_init_listhead(&psta_xmitpriv->apsd);
-+
-+
-+}
-+
-+void rtw_init_xmit_block(_adapter *padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	_rtw_spinlock_init(&dvobj->xmit_block_lock);
-+	dvobj->xmit_block = XMIT_BLOCK_NONE;
-+
-+}
-+void rtw_free_xmit_block(_adapter *padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	_rtw_spinlock_free(&dvobj->xmit_block_lock);
-+}
-+
-+s32	_rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter)
-+{
-+	int i;
-+	struct xmit_buf *pxmitbuf;
-+	struct xmit_frame *pxframe;
-+	sint	res = _SUCCESS;
-+
-+
-+	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
-+	/* _rtw_memset((unsigned char *)pxmitpriv, 0, sizeof(struct xmit_priv)); */
-+
-+	_rtw_spinlock_init(&pxmitpriv->lock);
-+	_rtw_spinlock_init(&pxmitpriv->lock_sctx);
-+	_rtw_init_sema(&pxmitpriv->xmit_sema, 0);
-+
-+	/*
-+	Please insert all the queue initializaiton using _rtw_init_queue below
-+	*/
-+
-+	pxmitpriv->adapter = padapter;
-+
-+	/* for(i = 0 ; i < MAX_NUMBLKS; i++) */
-+	/*	_rtw_init_queue(&pxmitpriv->blk_strms[i]); */
-+
-+	_rtw_init_queue(&pxmitpriv->be_pending);
-+	_rtw_init_queue(&pxmitpriv->bk_pending);
-+	_rtw_init_queue(&pxmitpriv->vi_pending);
-+	_rtw_init_queue(&pxmitpriv->vo_pending);
-+	_rtw_init_queue(&pxmitpriv->mgmt_pending);
-+
-+	/* _rtw_init_queue(&pxmitpriv->legacy_dz_queue); */
-+	/* _rtw_init_queue(&pxmitpriv->apsd_queue); */
-+
-+	_rtw_init_queue(&pxmitpriv->free_xmit_queue);
-+
-+	/*
-+	Please allocate memory with the sz = (struct xmit_frame) * NR_XMITFRAME,
-+	and initialize free_xmit_frame below.
-+	Please also apply  free_txobj to link_up all the xmit_frames...
-+	*/
-+
-+	pxmitpriv->pallocated_frame_buf = rtw_zvmalloc(NR_XMITFRAME * sizeof(struct xmit_frame) + 4);
-+
-+	if (pxmitpriv->pallocated_frame_buf  == NULL) {
-+		pxmitpriv->pxmit_frame_buf = NULL;
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	pxmitpriv->pxmit_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_frame_buf), 4);
-+	/* pxmitpriv->pxmit_frame_buf = pxmitpriv->pallocated_frame_buf + 4 - */
-+	/*						((SIZE_PTR) (pxmitpriv->pallocated_frame_buf) &3); */
-+
-+	pxframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
-+
-+	for (i = 0; i < NR_XMITFRAME; i++) {
-+		_rtw_init_listhead(&(pxframe->list));
-+
-+		pxframe->padapter = padapter;
-+		pxframe->frame_tag = NULL_FRAMETAG;
-+
-+		pxframe->pkt = NULL;
-+
-+		pxframe->buf_addr = NULL;
-+		pxframe->pxmitbuf = NULL;
-+
-+		rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xmit_queue.queue));
-+
-+		pxframe++;
-+	}
-+
-+	pxmitpriv->free_xmitframe_cnt = NR_XMITFRAME;
-+
-+	pxmitpriv->frag_len = MAX_FRAG_THRESHOLD;
-+
-+
-+	/* init xmit_buf */
-+	_rtw_init_queue(&pxmitpriv->free_xmitbuf_queue);
-+	_rtw_init_queue(&pxmitpriv->pending_xmitbuf_queue);
-+
-+	pxmitpriv->pallocated_xmitbuf = rtw_zvmalloc(NR_XMITBUFF * sizeof(struct xmit_buf) + 4);
-+
-+	if (pxmitpriv->pallocated_xmitbuf  == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pxmitpriv->pxmitbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmitbuf), 4);
-+	/* pxmitpriv->pxmitbuf = pxmitpriv->pallocated_xmitbuf + 4 - */
-+	/*						((SIZE_PTR) (pxmitpriv->pallocated_xmitbuf) &3); */
-+
-+	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
-+
-+	for (i = 0; i < NR_XMITBUFF; i++) {
-+		_rtw_init_listhead(&pxmitbuf->list);
-+
-+		pxmitbuf->priv_data = NULL;
-+		pxmitbuf->padapter = padapter;
-+		pxmitbuf->buf_tag = XMITBUF_DATA;
-+
-+		/* Tx buf allocation may fail sometimes, so sleep and retry. */
-+		res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);
-+		if (res == _FAIL) {
-+			rtw_msleep_os(10);
-+			res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);
-+			if (res == _FAIL)
-+				goto exit;
-+		}
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+		pxmitbuf->phead = pxmitbuf->pbuf;
-+		pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMITBUF_SZ;
-+		pxmitbuf->len = 0;
-+		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
-+#endif
-+
-+		pxmitbuf->flags = XMIT_VO_QUEUE;
-+
-+		rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmitbuf_queue.queue));
-+#ifdef DBG_XMIT_BUF
-+		pxmitbuf->no = i;
-+#endif
-+
-+		pxmitbuf++;
-+
-+	}
-+
-+	pxmitpriv->free_xmitbuf_cnt = NR_XMITBUFF;
-+
-+	/* init xframe_ext queue,  the same count as extbuf */
-+	_rtw_init_queue(&pxmitpriv->free_xframe_ext_queue);
-+
-+	pxmitpriv->xframe_ext_alloc_addr = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4);
-+
-+	if (pxmitpriv->xframe_ext_alloc_addr  == NULL) {
-+		pxmitpriv->xframe_ext = NULL;
-+		res = _FAIL;
-+		goto exit;
-+	}
-+	pxmitpriv->xframe_ext = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->xframe_ext_alloc_addr), 4);
-+	pxframe = (struct xmit_frame *)pxmitpriv->xframe_ext;
-+
-+	for (i = 0; i < NR_XMIT_EXTBUFF; i++) {
-+		_rtw_init_listhead(&(pxframe->list));
-+
-+		pxframe->padapter = padapter;
-+		pxframe->frame_tag = NULL_FRAMETAG;
-+
-+		pxframe->pkt = NULL;
-+
-+		pxframe->buf_addr = NULL;
-+		pxframe->pxmitbuf = NULL;
-+
-+		pxframe->ext_tag = 1;
-+
-+		rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xframe_ext_queue.queue));
-+
-+		pxframe++;
-+	}
-+	pxmitpriv->free_xframe_ext_cnt = NR_XMIT_EXTBUFF;
-+
-+	/* Init xmit extension buff */
-+	_rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);
-+
-+	pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4);
-+
-+	if (pxmitpriv->pallocated_xmit_extbuf  == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);
-+
-+	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
-+
-+	for (i = 0; i < NR_XMIT_EXTBUFF; i++) {
-+		_rtw_init_listhead(&pxmitbuf->list);
-+
-+		pxmitbuf->priv_data = NULL;
-+		pxmitbuf->padapter = padapter;
-+		pxmitbuf->buf_tag = XMITBUF_MGNT;
-+
-+		res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ, _TRUE);
-+		if (res == _FAIL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+		pxmitbuf->phead = pxmitbuf->pbuf;
-+		pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMIT_EXTBUF_SZ;
-+		pxmitbuf->len = 0;
-+		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
-+#endif
-+
-+		rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));
-+#ifdef DBG_XMIT_BUF_EXT
-+		pxmitbuf->no = i;
-+#endif
-+		pxmitbuf++;
-+
-+	}
-+
-+	pxmitpriv->free_xmit_extbuf_cnt = NR_XMIT_EXTBUFF;
-+
-+	for (i = 0; i < CMDBUF_MAX; i++) {
-+		pxmitbuf = &pxmitpriv->pcmd_xmitbuf[i];
-+		if (pxmitbuf) {
-+			_rtw_init_listhead(&pxmitbuf->list);
-+
-+			pxmitbuf->priv_data = NULL;
-+			pxmitbuf->padapter = padapter;
-+			pxmitbuf->buf_tag = XMITBUF_CMD;
-+
-+			res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ, _TRUE);
-+			if (res == _FAIL) {
-+				res = _FAIL;
-+				goto exit;
-+			}
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+			pxmitbuf->phead = pxmitbuf->pbuf;
-+			pxmitbuf->pend = pxmitbuf->pbuf + MAX_CMDBUF_SZ;
-+			pxmitbuf->len = 0;
-+			pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
-+#endif
-+			pxmitbuf->alloc_sz = MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ;
-+		}
-+	}
-+
-+	rtw_alloc_hwxmits(padapter);
-+	rtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
-+
-+	for (i = 0; i < 4; i++)
-+		pxmitpriv->wmm_para_seq[i] = i;
-+
-+#ifdef CONFIG_USB_HCI
-+	pxmitpriv->txirp_cnt = 1;
-+
-+	_rtw_init_sema(&(pxmitpriv->tx_retevt), 0);
-+
-+	/* per AC pending irp */
-+	pxmitpriv->beq_cnt = 0;
-+	pxmitpriv->bkq_cnt = 0;
-+	pxmitpriv->viq_cnt = 0;
-+	pxmitpriv->voq_cnt = 0;
-+#endif
-+
-+
-+#ifdef CONFIG_XMIT_ACK
-+	pxmitpriv->ack_tx = _FALSE;
-+	_rtw_mutex_init(&pxmitpriv->ack_tx_mutex);
-+	rtw_sctx_init(&pxmitpriv->ack_tx_ops, 0);
-+#endif
-+
-+#ifdef CONFIG_TX_AMSDU
-+	rtw_init_timer(&(pxmitpriv->amsdu_vo_timer), padapter,
-+		rtw_amsdu_vo_timeout_handler, padapter);
-+	pxmitpriv->amsdu_vo_timeout = RTW_AMSDU_TIMER_UNSET;
-+
-+	rtw_init_timer(&(pxmitpriv->amsdu_vi_timer), padapter,
-+		rtw_amsdu_vi_timeout_handler, padapter);
-+	pxmitpriv->amsdu_vi_timeout = RTW_AMSDU_TIMER_UNSET;
-+
-+	rtw_init_timer(&(pxmitpriv->amsdu_be_timer), padapter,
-+		rtw_amsdu_be_timeout_handler, padapter);
-+	pxmitpriv->amsdu_be_timeout = RTW_AMSDU_TIMER_UNSET;
-+
-+	rtw_init_timer(&(pxmitpriv->amsdu_bk_timer), padapter,
-+		rtw_amsdu_bk_timeout_handler, padapter);
-+	pxmitpriv->amsdu_bk_timeout = RTW_AMSDU_TIMER_UNSET;
-+
-+	pxmitpriv->amsdu_debug_set_timer = 0;
-+	pxmitpriv->amsdu_debug_timeout = 0;
-+	pxmitpriv->amsdu_debug_coalesce_one = 0;
-+	pxmitpriv->amsdu_debug_coalesce_two = 0;
-+#endif
-+#ifdef DBG_TXBD_DESC_DUMP
-+	pxmitpriv->dump_txbd_desc = 0;
-+#endif
-+	rtw_init_xmit_block(padapter);
-+	rtw_hal_init_xmit_priv(padapter);
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+void  rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv);
-+void  rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv)
-+{
-+	_rtw_spinlock_free(&pxmitpriv->lock);
-+	_rtw_free_sema(&pxmitpriv->xmit_sema);
-+
-+	_rtw_spinlock_free(&pxmitpriv->be_pending.lock);
-+	_rtw_spinlock_free(&pxmitpriv->bk_pending.lock);
-+	_rtw_spinlock_free(&pxmitpriv->vi_pending.lock);
-+	_rtw_spinlock_free(&pxmitpriv->vo_pending.lock);
-+	_rtw_spinlock_free(&pxmitpriv->mgmt_pending.lock);
-+
-+	/* _rtw_spinlock_free(&pxmitpriv->legacy_dz_queue.lock); */
-+	/* _rtw_spinlock_free(&pxmitpriv->apsd_queue.lock); */
-+
-+	_rtw_spinlock_free(&pxmitpriv->free_xmit_queue.lock);
-+	_rtw_spinlock_free(&pxmitpriv->free_xmitbuf_queue.lock);
-+	_rtw_spinlock_free(&pxmitpriv->pending_xmitbuf_queue.lock);
-+}
-+
-+
-+void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv)
-+{
-+	int i;
-+	_adapter *padapter = pxmitpriv->adapter;
-+	struct xmit_frame	*pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
-+	struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
-+
-+
-+	rtw_hal_free_xmit_priv(padapter);
-+
-+	rtw_mfree_xmit_priv_lock(pxmitpriv);
-+
-+	if (pxmitpriv->pxmit_frame_buf == NULL)
-+		goto out;
-+
-+	for (i = 0; i < NR_XMITFRAME; i++) {
-+		rtw_os_xmit_complete(padapter, pxmitframe);
-+
-+		pxmitframe++;
-+	}
-+
-+	for (i = 0; i < NR_XMITBUFF; i++) {
-+		rtw_os_xmit_resource_free(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);
-+
-+		pxmitbuf++;
-+	}
-+
-+	if (pxmitpriv->pallocated_frame_buf)
-+		rtw_vmfree(pxmitpriv->pallocated_frame_buf, NR_XMITFRAME * sizeof(struct xmit_frame) + 4);
-+
-+
-+	if (pxmitpriv->pallocated_xmitbuf)
-+		rtw_vmfree(pxmitpriv->pallocated_xmitbuf, NR_XMITBUFF * sizeof(struct xmit_buf) + 4);
-+
-+	/* free xframe_ext queue,  the same count as extbuf */
-+	if ((pxmitframe = (struct xmit_frame *)pxmitpriv->xframe_ext)) {
-+		for (i = 0; i < NR_XMIT_EXTBUFF; i++) {
-+			rtw_os_xmit_complete(padapter, pxmitframe);
-+			pxmitframe++;
-+		}
-+	}
-+	if (pxmitpriv->xframe_ext_alloc_addr)
-+		rtw_vmfree(pxmitpriv->xframe_ext_alloc_addr, NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4);
-+	_rtw_spinlock_free(&pxmitpriv->free_xframe_ext_queue.lock);
-+
-+	/* free xmit extension buff */
-+	_rtw_spinlock_free(&pxmitpriv->free_xmit_extbuf_queue.lock);
-+
-+	pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
-+	for (i = 0; i < NR_XMIT_EXTBUFF; i++) {
-+		rtw_os_xmit_resource_free(padapter, pxmitbuf, (MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE);
-+
-+		pxmitbuf++;
-+	}
-+
-+	if (pxmitpriv->pallocated_xmit_extbuf)
-+		rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4);
-+
-+	for (i = 0; i < CMDBUF_MAX; i++) {
-+		pxmitbuf = &pxmitpriv->pcmd_xmitbuf[i];
-+		if (pxmitbuf != NULL)
-+			rtw_os_xmit_resource_free(padapter, pxmitbuf, MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ , _TRUE);
-+	}
-+
-+	rtw_free_hwxmits(padapter);
-+
-+#ifdef CONFIG_XMIT_ACK
-+	_rtw_mutex_free(&pxmitpriv->ack_tx_mutex);
-+#endif
-+	rtw_free_xmit_block(padapter);
-+out:
-+	return;
-+}
-+
-+u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta)
-+{
-+	u8 bw;
-+
-+	bw = sta->cmn.bw_mode;
-+	if (MLME_STATE(adapter) & WIFI_ASOC_STATE) {
-+		if (adapter->mlmeextpriv.cur_channel <= 14)
-+			bw = rtw_min(bw, ADAPTER_TX_BW_2G(adapter));
-+		else
-+			bw = rtw_min(bw, ADAPTER_TX_BW_5G(adapter));
-+	}
-+
-+	return bw;
-+}
-+
-+void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u64 *r_bmp_vht)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	u8 fix_bw = 0xFF;
-+	u16 bmp_cck_ofdm = 0;
-+	u32 bmp_ht = 0;
-+	u64 bmp_vht = 0;
-+	int i;
-+
-+	if (adapter->fix_rate != 0xFF && adapter->fix_bw != 0xFF)
-+		fix_bw = adapter->fix_bw;
-+
-+	/* TODO: adapter->fix_rate */
-+
-+	for (i = 0; i < macid_ctl->num; i++) {
-+		if (!rtw_macid_is_used(macid_ctl, i))
-+			continue;
-+		if (!rtw_macid_is_iface_specific(macid_ctl, i, adapter))
-+			continue;
-+
-+		if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */
-+			bmp_cck_ofdm |= macid_ctl->rate_bmp0[i] & 0x00000FFF;
-+
-+		/* bypass mismatch bandwidth for HT, VHT */
-+		if ((fix_bw != 0xFF && fix_bw != bw) || (fix_bw == 0xFF && macid_ctl->bw[i] != bw))
-+			continue;
-+
-+		if (macid_ctl->vht_en[i])
-+			bmp_vht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
-+		else
-+			bmp_ht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
-+	}
-+
-+	/* TODO: mlmeext->tx_rate*/
-+
-+	if (r_bmp_cck_ofdm)
-+		*r_bmp_cck_ofdm = bmp_cck_ofdm;
-+	if (r_bmp_ht)
-+		*r_bmp_ht = bmp_ht;
-+	if (r_bmp_vht)
-+		*r_bmp_vht = bmp_vht;
-+}
-+
-+void rtw_get_shared_macid_tx_rate_bmp_by_bw(struct dvobj_priv *dvobj, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u64 *r_bmp_vht)
-+{
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	u16 bmp_cck_ofdm = 0;
-+	u32 bmp_ht = 0;
-+	u64 bmp_vht = 0;
-+	int i;
-+
-+	for (i = 0; i < macid_ctl->num; i++) {
-+		if (!rtw_macid_is_used(macid_ctl, i))
-+			continue;
-+		if (!rtw_macid_is_iface_shared(macid_ctl, i))
-+			continue;
-+
-+		if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */
-+			bmp_cck_ofdm |= macid_ctl->rate_bmp0[i] & 0x00000FFF;
-+
-+		/* bypass mismatch bandwidth for HT, VHT */
-+		if (macid_ctl->bw[i] != bw)
-+			continue;
-+
-+		if (macid_ctl->vht_en[i])
-+			bmp_vht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
-+		else
-+			bmp_ht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
-+	}
-+
-+	if (r_bmp_cck_ofdm)
-+		*r_bmp_cck_ofdm = bmp_cck_ofdm;
-+	if (r_bmp_ht)
-+		*r_bmp_ht = bmp_ht;
-+	if (r_bmp_vht)
-+		*r_bmp_vht = bmp_vht;
-+}
-+
-+void rtw_get_adapter_tx_rate_bmp(_adapter *adapter, u16 r_bmp_cck_ofdm[], u32 r_bmp_ht[], u64 r_bmp_vht[])
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	u8 bw;
-+	u16 bmp_cck_ofdm, tmp_cck_ofdm;
-+	u32 bmp_ht, tmp_ht;
-+	u64 bmp_vht, tmp_vht;
-+	int i;
-+
-+	for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {
-+		bmp_cck_ofdm = bmp_ht = bmp_vht = 0;
-+		if (hal_is_bw_support(adapter, bw)) {
-+			{
-+				rtw_get_adapter_tx_rate_bmp_by_bw(adapter, bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht);
-+				bmp_cck_ofdm |= tmp_cck_ofdm;
-+				bmp_ht |= tmp_ht;
-+				bmp_vht |= tmp_vht;
-+			}
-+			rtw_get_shared_macid_tx_rate_bmp_by_bw(dvobj, bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht);
-+			bmp_cck_ofdm |= tmp_cck_ofdm;
-+			bmp_ht |= tmp_ht;
-+			bmp_vht |= tmp_vht;
-+		}
-+		if (bw == CHANNEL_WIDTH_20)
-+			r_bmp_cck_ofdm[bw] = bmp_cck_ofdm;
-+		if (bw <= CHANNEL_WIDTH_40)
-+			r_bmp_ht[bw] = bmp_ht;
-+		if (bw <= CHANNEL_WIDTH_160)
-+			r_bmp_vht[bw] = bmp_vht;
-+	}
-+}
-+
-+void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj)
-+{
-+	struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
-+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u8 bw;
-+	u16 bmp_cck_ofdm, tmp_cck_ofdm;
-+	u32 bmp_ht, tmp_ht, ori_bmp_ht[2];
-+	u64 bmp_vht, tmp_vht, ori_bmp_vht[4];
-+	int i;
-+
-+	for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {
-+		/* backup the original ht & vht bmp */
-+		if (bw <= CHANNEL_WIDTH_40)
-+			ori_bmp_ht[bw] = rf_ctl->rate_bmp_ht_by_bw[bw];
-+		if (bw <= CHANNEL_WIDTH_160)
-+			ori_bmp_vht[bw] = rf_ctl->rate_bmp_vht_by_bw[bw];
-+
-+		bmp_cck_ofdm = bmp_ht = bmp_vht = 0;
-+		if (hal_is_bw_support(dvobj_get_primary_adapter(dvobj), bw)) {
-+			for (i = 0; i < dvobj->iface_nums; i++) {
-+				if (!dvobj->padapters[i])
-+					continue;
-+				rtw_get_adapter_tx_rate_bmp_by_bw(dvobj->padapters[i], bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht);
-+				bmp_cck_ofdm |= tmp_cck_ofdm;
-+				bmp_ht |= tmp_ht;
-+				bmp_vht |= tmp_vht;
-+			}
-+			rtw_get_shared_macid_tx_rate_bmp_by_bw(dvobj, bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht);
-+			bmp_cck_ofdm |= tmp_cck_ofdm;
-+			bmp_ht |= tmp_ht;
-+			bmp_vht |= tmp_vht;
-+		}
-+		if (bw == CHANNEL_WIDTH_20)
-+			rf_ctl->rate_bmp_cck_ofdm = bmp_cck_ofdm;
-+		if (bw <= CHANNEL_WIDTH_40)
-+			rf_ctl->rate_bmp_ht_by_bw[bw] = bmp_ht;
-+		if (bw <= CHANNEL_WIDTH_160)
-+			rf_ctl->rate_bmp_vht_by_bw[bw] = bmp_vht;
-+	}
-+
-+#if CONFIG_TXPWR_LIMIT
-+#ifndef DBG_HIGHEST_RATE_BMP_BW_CHANGE
-+#define DBG_HIGHEST_RATE_BMP_BW_CHANGE 0
-+#endif
-+
-+	if (hal_data->txpwr_limit_loaded) {
-+		u8 ori_highest_ht_rate_bw_bmp;
-+		u8 ori_highest_vht_rate_bw_bmp;
-+		u8 highest_rate_bw;
-+		u8 highest_rate_bw_bmp;
-+		u8 update_ht_rs = _FALSE;
-+		u8 update_vht_rs = _FALSE;
-+
-+		/* backup the original ht & vht highest bw bmp */
-+		ori_highest_ht_rate_bw_bmp = rf_ctl->highest_ht_rate_bw_bmp;
-+		ori_highest_vht_rate_bw_bmp = rf_ctl->highest_vht_rate_bw_bmp;
-+
-+		highest_rate_bw_bmp = BW_CAP_20M;
-+		highest_rate_bw = CHANNEL_WIDTH_20;
-+		for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_40; bw++) {
-+			if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw] < rf_ctl->rate_bmp_ht_by_bw[bw]) {
-+				highest_rate_bw_bmp = ch_width_to_bw_cap(bw);
-+				highest_rate_bw = bw;
-+			} else if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw] == rf_ctl->rate_bmp_ht_by_bw[bw])
-+				highest_rate_bw_bmp |= ch_width_to_bw_cap(bw);
-+		}
-+		rf_ctl->highest_ht_rate_bw_bmp = highest_rate_bw_bmp;
-+
-+		if (ori_highest_ht_rate_bw_bmp != rf_ctl->highest_ht_rate_bw_bmp
-+			|| largest_bit(ori_bmp_ht[highest_rate_bw]) != largest_bit(rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw])
-+		) {
-+			if (DBG_HIGHEST_RATE_BMP_BW_CHANGE) {
-+				RTW_INFO("highest_ht_rate_bw_bmp:0x%02x=>0x%02x\n", ori_highest_ht_rate_bw_bmp, rf_ctl->highest_ht_rate_bw_bmp);
-+				RTW_INFO("rate_bmp_ht_by_bw[%u]:0x%08x=>0x%08x\n", highest_rate_bw, ori_bmp_ht[highest_rate_bw], rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw]);
-+			}
-+			if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw])
-+				update_ht_rs = _TRUE;
-+		}
-+
-+		highest_rate_bw_bmp = BW_CAP_20M;
-+		highest_rate_bw = CHANNEL_WIDTH_20;
-+		for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {
-+			if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw] < rf_ctl->rate_bmp_vht_by_bw[bw]) {
-+				highest_rate_bw_bmp = ch_width_to_bw_cap(bw);
-+				highest_rate_bw = bw;
-+			} else if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw] == rf_ctl->rate_bmp_vht_by_bw[bw])
-+				highest_rate_bw_bmp |= ch_width_to_bw_cap(bw);
-+		}
-+		rf_ctl->highest_vht_rate_bw_bmp = highest_rate_bw_bmp;
-+
-+		if (ori_highest_vht_rate_bw_bmp != rf_ctl->highest_vht_rate_bw_bmp
-+			|| largest_bit_64(ori_bmp_vht[highest_rate_bw]) != largest_bit_64(rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw])
-+		) {
-+			if (DBG_HIGHEST_RATE_BMP_BW_CHANGE) {
-+				RTW_INFO("highest_vht_rate_bw_bmp:0x%02x=>0x%02x\n", ori_highest_vht_rate_bw_bmp, rf_ctl->highest_vht_rate_bw_bmp);
-+				RTW_INFO("rate_bmp_vht_by_bw[%u]:0x%016llx=>0x%016llx\n", highest_rate_bw, ori_bmp_vht[highest_rate_bw], rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw]);
-+			}
-+			if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw])
-+				update_vht_rs = _TRUE;
-+		}
-+
-+		/* TODO: per rfpath and rate section handling? */
-+		if (update_ht_rs == _TRUE || update_vht_rs == _TRUE)
-+			rtw_hal_update_txpwr_level(adapter);
-+	}
-+#endif /* CONFIG_TXPWR_LIMIT */
-+}
-+
-+u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw)
-+{
-+	struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
-+	u8 bw;
-+	u8 bw_bmp = 0;
-+	u32 rate_bmp;
-+
-+	if (!IS_HT_RATE(rate)) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	rate_bmp = 1 << (rate - MGN_MCS0);
-+
-+	if (max_bw > CHANNEL_WIDTH_40)
-+		max_bw = CHANNEL_WIDTH_40;
-+
-+	for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {
-+		/* RA may use lower rate for retry */
-+		if (rf_ctl->rate_bmp_ht_by_bw[bw] >= rate_bmp)
-+			bw_bmp |= ch_width_to_bw_cap(bw);
-+	}
-+
-+exit:
-+	return bw_bmp;
-+}
-+
-+u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw)
-+{
-+	struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
-+	u8 bw;
-+	u8 bw_bmp = 0;
-+	u64 rate_bmp;
-+
-+	if (!IS_VHT_RATE(rate)) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	rate_bmp = BIT_ULL(rate - MGN_VHT1SS_MCS0);
-+
-+	if (max_bw > CHANNEL_WIDTH_160)
-+		max_bw = CHANNEL_WIDTH_160;
-+
-+	for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {
-+		/* RA may use lower rate for retry */
-+		if (rf_ctl->rate_bmp_vht_by_bw[bw] >= rate_bmp)
-+			bw_bmp |= ch_width_to_bw_cap(bw);
-+	}
-+
-+exit:
-+	return bw_bmp;
-+}
-+
-+s16 rtw_adapter_get_oper_txpwr_max_mbm(_adapter *adapter, bool eirp)
-+{
-+	s16 mbm = -100 * MBM_PDBM;
-+
-+	if (MLME_IS_ASOC(adapter)) {
-+		struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+		u8 ch = mlmeext->cur_channel;
-+		u8 bw = mlmeext->cur_bwmode;
-+		u8 offset = mlmeext->cur_ch_offset;
-+		u8 cch = rtw_get_center_ch(ch, bw, offset);
-+		u8 hw_rate = MRateToHwRate(mlmeext->tx_rate);
-+		u16 bmp_cck_ofdm_by_bw[1] = {0};
-+		u32 bmp_ht_by_bw[2] = {0};
-+		u64 bmp_vht_by_bw[4] = {0};
-+		u16 bmp_cck_ofdm = 0;
-+		u32 bmp_ht = 0;
-+		u64 bmp_vht = 0;
-+		int i;
-+
-+		rtw_get_adapter_tx_rate_bmp(adapter, bmp_cck_ofdm_by_bw, bmp_ht_by_bw, bmp_vht_by_bw);
-+
-+		bmp_cck_ofdm |= bmp_cck_ofdm_by_bw[0];
-+		for (i = 0; i < 2; i++)
-+			bmp_ht |= bmp_ht_by_bw[i];
-+		for (i = 0; i < 4; i++)
-+			bmp_vht |= bmp_vht_by_bw[i];
-+
-+		if (IS_LEGACY_HRATE(hw_rate))
-+			bmp_cck_ofdm |= BIT(hw_rate);
-+		else if (IS_HT_HRATE(hw_rate))
-+			bmp_ht |= BIT(hw_rate - DESC_RATEMCS0);
-+		else if (IS_VHT_HRATE(hw_rate))
-+			bmp_vht |= BIT(hw_rate - DESC_RATEVHTSS1MCS0);
-+
-+		mbm = phy_get_txpwr_total_max_mbm(adapter
-+			, bw, cch, ch, bmp_cck_ofdm, bmp_ht, bmp_vht, 0, eirp);
-+	}
-+
-+	return mbm;
-+}
-+
-+s16 rtw_rfctl_get_oper_txpwr_max_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u8 ifbmp_mod, u8 if_op, bool eirp)
-+{
-+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
-+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
-+	s16 mbm = -100 * MBM_PDBM;
-+
-+	if (ch) {
-+		u8 cch = rtw_get_center_ch(ch, bw, offset);
-+		u16 bmp_cck_ofdm = 0;
-+		u32 bmp_ht = 0;
-+		u64 bmp_vht = 0;
-+		int i;
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			struct mlme_ext_priv *mlmeext;
-+			u8 hw_rate;
-+
-+			if (!dvobj->padapters[i])
-+				continue;
-+
-+			if (ifbmp_mod & BIT(i)) {
-+				if (!if_op)
-+					continue;
-+			} else if (!MLME_IS_ASOC(dvobj->padapters[i]))
-+				continue;
-+
-+			mlmeext = &(dvobj->padapters[i]->mlmeextpriv);
-+			hw_rate = MRateToHwRate(mlmeext->tx_rate);
-+
-+			if (IS_LEGACY_HRATE(hw_rate))
-+				bmp_cck_ofdm |= BIT(hw_rate);
-+			else if (IS_HT_HRATE(hw_rate))
-+				bmp_ht |= BIT(hw_rate - DESC_RATEMCS0);
-+			else if (IS_VHT_HRATE(hw_rate))
-+				bmp_vht |= BIT(hw_rate - DESC_RATEVHTSS1MCS0);
-+		}
-+
-+		bmp_cck_ofdm |= rfctl->rate_bmp_cck_ofdm;
-+		for (i = 0; i < 2; i++)
-+			bmp_ht |= rfctl->rate_bmp_ht_by_bw[i];
-+		for (i = 0; i < 4; i++)
-+			bmp_vht |= rfctl->rate_bmp_vht_by_bw[i];
-+
-+		mbm = phy_get_txpwr_total_max_mbm(adapter
-+			, bw, cch, ch, bmp_cck_ofdm, bmp_ht, bmp_vht, 0, eirp);
-+	}
-+
-+	return mbm;
-+}
-+
-+s16 rtw_get_oper_txpwr_max_mbm(struct dvobj_priv *dvobj, bool eirp)
-+{
-+	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
-+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
-+	s16 mbm = -100 * MBM_PDBM;
-+	u8 ch = rfctl->op_ch, bw, offset;
-+
-+	if (rtw_get_bw_offset_by_op_class_ch(rfctl->op_class, ch, &bw, &offset))
-+		mbm = rtw_rfctl_get_oper_txpwr_max_mbm(rfctl, ch, bw, offset, 0, 0, eirp);
-+
-+	return mbm;
-+}
-+
-+s16 rtw_rfctl_get_reg_max_txpwr_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool eirp)
-+{
-+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
-+	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
-+	_adapter *adapter = dvobj_get_primary_adapter(dvobj);
-+	s16 mbm = -100 * MBM_PDBM;
-+	u8 cch = rtw_get_center_ch(ch, bw, offset);
-+	u16 bmp_cck_ofdm = 0;
-+	u32 bmp_ht = 0;
-+	u64 bmp_vht = 0;
-+
-+	if (ch <= 14)
-+		bmp_cck_ofdm |= RATE_BMP_CCK;
-+
-+	/* TODO: NO OFDM? */
-+	bmp_cck_ofdm |= RATE_BMP_OFDM;
-+
-+#ifdef CONFIG_80211N_HT
-+	if (regsty->ht_enable && is_supported_ht(regsty->wireless_mode)) {
-+		switch (GET_HAL_TX_NSS(adapter)) {
-+		case 1:
-+			bmp_ht |= RATE_BMP_HT_1SS;
-+			break;
-+		case 2:
-+			bmp_ht |= RATE_BMP_HT_2SS | RATE_BMP_HT_1SS;
-+			break;
-+		case 3:
-+			bmp_ht |= RATE_BMP_HT_3SS | RATE_BMP_HT_2SS | RATE_BMP_HT_1SS;
-+			break;
-+		case 4:
-+			bmp_ht |= RATE_BMP_HT_4SS | RATE_BMP_HT_3SS | RATE_BMP_HT_2SS | RATE_BMP_HT_1SS;
-+			break;
-+		default:
-+			rtw_warn_on(1);
-+		}
-+	}
-+#endif
-+
-+#ifdef CONFIG_80211AC_VHT
-+	if (ch > 14 && REGSTY_IS_11AC_ENABLE(regsty) && is_supported_vht(regsty->wireless_mode)
-+		&& (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
-+	) {
-+		switch (GET_HAL_TX_NSS(adapter)) {
-+		case 1:
-+			bmp_vht |= RATE_BMP_VHT_1SS;
-+			break;
-+		case 2:
-+			bmp_vht |= RATE_BMP_VHT_2SS | RATE_BMP_VHT_1SS;
-+			break;
-+		case 3:
-+			bmp_vht |= RATE_BMP_VHT_3SS | RATE_BMP_VHT_2SS | RATE_BMP_VHT_1SS;
-+			break;
-+		case 4:
-+			bmp_vht |= RATE_BMP_VHT_4SS | RATE_BMP_VHT_3SS | RATE_BMP_VHT_2SS | RATE_BMP_VHT_1SS;
-+			break;
-+		default:
-+			rtw_warn_on(1);
-+		}
-+	}
-+#endif
-+
-+	mbm = phy_get_txpwr_total_max_mbm(adapter
-+			, bw, cch, ch, bmp_cck_ofdm, bmp_ht, bmp_vht, 1, eirp);
-+
-+	return mbm;
-+}
-+
-+u8 query_ra_short_GI(struct sta_info *psta, u8 bw)
-+{
-+	u8	sgi = _FALSE, sgi_20m = _FALSE, sgi_40m = _FALSE, sgi_80m = _FALSE;
-+
-+#ifdef CONFIG_80211N_HT
-+#ifdef CONFIG_80211AC_VHT
-+	if (psta->vhtpriv.vht_option)
-+		sgi_80m = psta->vhtpriv.sgi_80m;
-+#endif
-+	sgi_20m = psta->htpriv.sgi_20m;
-+	sgi_40m = psta->htpriv.sgi_40m;
-+#endif
-+
-+	switch (bw) {
-+	case CHANNEL_WIDTH_80:
-+		sgi = sgi_80m;
-+		break;
-+	case CHANNEL_WIDTH_40:
-+		sgi = sgi_40m;
-+		break;
-+	case CHANNEL_WIDTH_20:
-+	default:
-+		sgi = sgi_20m;
-+		break;
-+	}
-+
-+	return sgi;
-+}
-+
-+/* This function references driver insmond parameters to decide vcs mode. */
-+/* Driver insmond parameters: rtw_vrtl_carrier_sense and rtw_vcs_type */
-+static u8 validate_vcs(_adapter *padapter, u8  mode) {
-+
-+	u8 vcs_mode = NONE_VCS;
-+
-+	switch(padapter->registrypriv.vrtl_carrier_sense) {
-+
-+		case DISABLE_VCS:
-+			vcs_mode = NONE_VCS;
-+			break;
-+
-+		case ENABLE_VCS:
-+			vcs_mode = padapter->registrypriv.vcs_type;
-+			break;
-+
-+		case AUTO_VCS:
-+			vcs_mode = mode;
-+			break;
-+
-+		default:
-+			vcs_mode = NONE_VCS;
-+			break;
-+	}
-+
-+	return vcs_mode;
-+
-+}
-+
-+static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitframe)
-+{
-+	u32	sz;
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	#ifdef RTW_FORCE_CTS_TO_SELF_UNDER_LOW_RSSI
-+	s8	rssi = 0;
-+	struct sta_info	*psta = pattrib->psta;
-+	#endif
-+	/*
-+		if(pattrib->psta)
-+		{
-+			psta = pattrib->psta;
-+		}
-+		else
-+		{
-+			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
-+			psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] );
-+		}
-+
-+		if(psta==NULL)
-+		{
-+			RTW_INFO("%s, psta==NUL\n", __func__);
-+			return;
-+		}
-+
-+		if(!(psta->state &WIFI_ASOC_STATE))
-+		{
-+			RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
-+			return;
-+		}
-+	*/
-+
-+	if (pattrib->nr_frags != 1)
-+		sz = padapter->xmitpriv.frag_len;
-+	else /* no frag */
-+		sz = pattrib->last_txcmdsz;
-+
-+	/* (1) RTS_Threshold is compared to the MPDU, not MSDU. */
-+	/* (2) If there are more than one frag in  this MSDU, only the first frag uses protection frame. */
-+	/*		Other fragments are protected by previous fragment. */
-+	/*		So we only need to check the length of first fragment. */
-+	if (pmlmeext->cur_wireless_mode < WIRELESS_11_24N  || padapter->registrypriv.wifi_spec) {
-+		if (sz > padapter->registrypriv.rts_thresh)
-+			pattrib->vcs_mode = RTS_CTS;
-+		else {
-+			if (pattrib->rtsen)
-+				pattrib->vcs_mode = RTS_CTS;
-+			else if (pattrib->cts2self)
-+				pattrib->vcs_mode = CTS_TO_SELF;
-+			else
-+				pattrib->vcs_mode = NONE_VCS;
-+		}
-+	} else {
-+		while (_TRUE) {
-+#if 0 /* Todo */
-+			/* check IOT action */
-+			if (pHTInfo->IOTAction & HT_IOT_ACT_FORCED_CTS2SELF) {
-+				pattrib->vcs_mode = CTS_TO_SELF;
-+				pattrib->rts_rate = MGN_24M;
-+				break;
-+			} else if (pHTInfo->IOTAction & (HT_IOT_ACT_FORCED_RTS | HT_IOT_ACT_PURE_N_MODE)) {
-+				pattrib->vcs_mode = RTS_CTS;
-+				pattrib->rts_rate = MGN_24M;
-+				break;
-+			}
-+#endif
-+
-+			/* IOT action */
-+			if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS) && (pattrib->ampdu_en == _TRUE) &&
-+			    (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {
-+				pattrib->vcs_mode = CTS_TO_SELF;
-+				break;
-+			}
-+
-+			/* check ERP protection */
-+			if (pattrib->rtsen || pattrib->cts2self) {
-+				if (pattrib->rtsen)
-+					pattrib->vcs_mode = RTS_CTS;
-+				else if (pattrib->cts2self)
-+					pattrib->vcs_mode = CTS_TO_SELF;
-+
-+				break;
-+			}
-+
-+			/* check HT op mode */
-+			if (pattrib->ht_en) {
-+				u8 HTOpMode = pmlmeinfo->HT_protection;
-+				if ((pmlmeext->cur_bwmode && (HTOpMode == 2 || HTOpMode == 3)) ||
-+				    (!pmlmeext->cur_bwmode && HTOpMode == 3)) {
-+					pattrib->vcs_mode = RTS_CTS;
-+					break;
-+				}
-+			}
-+
-+			/* check rts */
-+			if (sz > padapter->registrypriv.rts_thresh) {
-+				pattrib->vcs_mode = RTS_CTS;
-+				break;
-+			}
-+
-+			/* to do list: check MIMO power save condition. */
-+
-+			/* check AMPDU aggregation for TXOP */
-+			if ((pattrib->ampdu_en == _TRUE) && (!IS_HARDWARE_TYPE_8812(padapter))) {
-+				pattrib->vcs_mode = RTS_CTS;
-+				break;
-+			}
-+
-+			pattrib->vcs_mode = NONE_VCS;
-+			break;
-+		}
-+		#ifdef RTW_FORCE_CTS_TO_SELF_UNDER_LOW_RSSI
-+		/*RTStoCTS while let TP degree ,while enable full BW*/
-+		if (psta != NULL) {
-+			rssi = psta->cmn.rssi_stat.rssi;
-+			if ((rssi < 18) && (pattrib->vcs_mode == RTS_CTS))
-+				pattrib->vcs_mode = CTS_TO_SELF;
-+		}
-+		#endif
-+	}
-+
-+	pattrib->vcs_mode = validate_vcs(padapter, pattrib->vcs_mode);
-+
-+	/* for debug : force driver control vrtl_carrier_sense. */
-+	if (padapter->driver_vcs_en == 1) {
-+		/* u8 driver_vcs_en; */ /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */
-+		/* u8 driver_vcs_type; */ /* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */
-+		pattrib->vcs_mode = padapter->driver_vcs_type;
-+	}
-+
-+}
-+
-+#ifdef CONFIG_WMMPS_STA
-+/*
-+ * update_attrib_trigger_frame_info
-+ * For Station mode, if a specific TID of driver setting and an AP support uapsd function, the data 
-+ * frame with corresponding TID will be a trigger frame when driver is in wmm power saving mode.
-+ * 
-+ * Arguments:
-+ * @padapter: _adapter pointer.
-+ * @pattrib: pkt_attrib pointer.
-+ *
-+ * Auther: Arvin Liu
-+ * Date: 2017/06/05
-+ */
-+static void update_attrib_trigger_frame_info(_adapter *padapter, struct pkt_attrib *pattrib) {
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct pwrctrl_priv 	*pwrpriv = adapter_to_pwrctl(padapter); 
-+	struct qos_priv 	*pqospriv = &pmlmepriv->qospriv;
-+	u8 trigger_frame_en = 0;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
-+		if ((pwrpriv->pwr_mode == PS_MODE_MIN) || (pwrpriv->pwr_mode == PS_MODE_MAX)) {
-+			if((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT(pattrib->priority)) == _TRUE)) {
-+				trigger_frame_en = 1;
-+				RTW_INFO("[WMMPS]"FUNC_ADPT_FMT": This is a Trigger Frame\n", FUNC_ADPT_ARG(padapter));
-+			}
-+		}
-+	}
-+
-+	pattrib->trigger_frame = trigger_frame_en;
-+}
-+#endif /* CONFIG_WMMPS_STA */
-+
-+static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta)
-+{
-+	struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;
-+	u8 bw;
-+
-+	pattrib->rtsen = psta->rtsen;
-+	pattrib->cts2self = psta->cts2self;
-+
-+	pattrib->mdata = 0;
-+	pattrib->eosp = 0;
-+	pattrib->triggered = 0;
-+	pattrib->ampdu_spacing = 0;
-+
-+	/* ht_en, init rate, ,bw, ch_offset, sgi */
-+
-+	pattrib->raid = psta->cmn.ra_info.rate_id;
-+
-+	bw = rtw_get_tx_bw_mode(padapter, psta);
-+	pattrib->bwmode = rtw_min(bw, mlmeext->cur_bwmode);
-+	pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode);
-+
-+	pattrib->ldpc = psta->cmn.ldpc_en;
-+	pattrib->stbc = psta->cmn.stbc_en;
-+
-+#ifdef CONFIG_80211N_HT
-+	if(padapter->registrypriv.ht_enable &&
-+		is_supported_ht(padapter->registrypriv.wireless_mode)) {
-+		pattrib->ht_en = psta->htpriv.ht_option;
-+		pattrib->ch_offset = psta->htpriv.ch_offset;
-+		pattrib->ampdu_en = _FALSE;
-+
-+		if (padapter->driver_ampdu_spacing != 0xFF) /* driver control AMPDU Density for peer sta's rx */
-+			pattrib->ampdu_spacing = padapter->driver_ampdu_spacing;
-+		else
-+			pattrib->ampdu_spacing = psta->htpriv.rx_ampdu_min_spacing;
-+
-+		/* check if enable ampdu */
-+		if (pattrib->ht_en && psta->htpriv.ampdu_enable) {
-+			if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) {
-+				pattrib->ampdu_en = _TRUE;
-+				if (psta->htpriv.tx_amsdu_enable == _TRUE)
-+					pattrib->amsdu_ampdu_en = _TRUE;
-+				else
-+					pattrib->amsdu_ampdu_en = _FALSE;
-+			}
-+		}
-+	}
-+#endif /* CONFIG_80211N_HT */
-+	/* if(pattrib->ht_en && psta->htpriv.ampdu_enable) */
-+	/* { */
-+	/*	if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) */
-+	/*		pattrib->ampdu_en = _TRUE; */
-+	/* }	 */
-+
-+#ifdef CONFIG_TDLS
-+	if (pattrib->direct_link == _TRUE) {
-+		psta = pattrib->ptdls_sta;
-+
-+		pattrib->raid = psta->cmn.ra_info.rate_id;
-+#ifdef CONFIG_80211N_HT
-+	if(padapter->registrypriv.ht_enable &&
-+		is_supported_ht(padapter->registrypriv.wireless_mode)) {
-+			pattrib->bwmode = rtw_get_tx_bw_mode(padapter, psta);
-+			pattrib->ht_en = psta->htpriv.ht_option;
-+			pattrib->ch_offset = psta->htpriv.ch_offset;
-+			pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode);
-+	}
-+#endif /* CONFIG_80211N_HT */
-+	}
-+#endif /* CONFIG_TDLS */
-+
-+	pattrib->retry_ctrl = _FALSE;
-+}
-+
-+static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta, enum eap_type eapol_type)
-+{
-+	sint res = _SUCCESS;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	sint bmcast = IS_MCAST(pattrib->ra);
-+
-+	_rtw_memset(pattrib->dot118021x_UncstKey.skey,  0, 16);
-+	_rtw_memset(pattrib->dot11tkiptxmickey.skey,  0, 16);
-+	pattrib->mac_id = psta->cmn.mac_id;
-+
-+	/* Comment by Owen at 2020/05/19
-+	 * Issue: RTK STA sends encrypted 4-way 4/4 when AP thinks the 4-way incomplete
-+	 * In TCL pressure test, AP may resend 4-way 3/4 with new replay counter in 2 ms.
-+	 * In this situation, STA sends unencrypted 4-way 4/4 with old replay counter after more
-+	 * than 2 ms, followed by the encrypted 4-way 4/4 with new replay counter. Because the
-+	 * AP only accepts unencrypted 4-way 4/4 with a new play counter, and the STA encrypts
-+	 * each 4-way 4/4 at this time, the 4-way handshake cannot be completed.
-+	 * So we modified that after STA receives unencrypted 4-way 1/4 and 4-way 3/4,
-+	 * 4-way 2/4 and 4-way 4/4 sent by STA in the next 100 ms are not encrypted.
-+	 */
-+	if (psta->ieee8021x_blocked == _TRUE ||
-+		((eapol_type == EAPOL_2_4 || eapol_type == EAPOL_4_4) &&
-+		rtw_get_passing_time_ms(psta->resp_nonenc_eapol_key_starttime) <= 100)) {
-+
-+		if (eapol_type == EAPOL_2_4 || eapol_type == EAPOL_4_4)
-+			RTW_INFO("Respond unencrypted eapol key\n");
-+
-+		pattrib->encrypt = 0;
-+
-+		if ((pattrib->ether_type != 0x888e) && (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)) {
-+#ifdef DBG_TX_DROP_FRAME
-+			RTW_INFO("DBG_TX_DROP_FRAME %s psta->ieee8021x_blocked == _TRUE,  pattrib->ether_type(%04x) != 0x888e\n", __FUNCTION__, pattrib->ether_type);
-+#endif
-+			res = _FAIL;
-+			goto exit;
-+		}
-+	} else {
-+		GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, bmcast);
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+		if (pattrib->ether_type == 0x88B4)
-+			pattrib->encrypt = _NO_PRIVACY_;
-+#endif
-+
-+		switch (psecuritypriv->dot11AuthAlgrthm) {
-+		case dot11AuthAlgrthm_Open:
-+		case dot11AuthAlgrthm_Shared:
-+		case dot11AuthAlgrthm_Auto:
-+			pattrib->key_idx = (u8)psecuritypriv->dot11PrivacyKeyIndex;
-+			break;
-+		case dot11AuthAlgrthm_8021X:
-+			if (bmcast)
-+				pattrib->key_idx = (u8)psecuritypriv->dot118021XGrpKeyid;
-+			else
-+				pattrib->key_idx = 0;
-+			break;
-+		default:
-+			pattrib->key_idx = 0;
-+			break;
-+		}
-+
-+		/* For WPS 1.0 WEP, driver should not encrypt EAPOL Packet for WPS handshake. */
-+		if (((pattrib->encrypt == _WEP40_) || (pattrib->encrypt == _WEP104_)) && (pattrib->ether_type == 0x888e))
-+			pattrib->encrypt = _NO_PRIVACY_;
-+
-+	}
-+
-+#ifdef CONFIG_TDLS
-+	if (pattrib->direct_link == _TRUE) {
-+		if (pattrib->encrypt > 0)
-+			pattrib->encrypt = _AES_;
-+	}
-+#endif
-+
-+	switch (pattrib->encrypt) {
-+	case _WEP40_:
-+	case _WEP104_:
-+		pattrib->iv_len = 4;
-+		pattrib->icv_len = 4;
-+		WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
-+		break;
-+
-+	case _TKIP_:
-+		pattrib->iv_len = 8;
-+		pattrib->icv_len = 4;
-+
-+		if (psecuritypriv->busetkipkey == _FAIL) {
-+#ifdef DBG_TX_DROP_FRAME
-+			RTW_INFO("DBG_TX_DROP_FRAME %s psecuritypriv->busetkipkey(%d)==_FAIL drop packet\n", __FUNCTION__, psecuritypriv->busetkipkey);
-+#endif
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		if (bmcast)
-+			TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
-+		else
-+			TKIP_IV(pattrib->iv, psta->dot11txpn, 0);
-+
-+
-+		_rtw_memcpy(pattrib->dot11tkiptxmickey.skey, psta->dot11tkiptxmickey.skey, 16);
-+
-+		break;
-+
-+	case _AES_:
-+
-+		pattrib->iv_len = 8;
-+		pattrib->icv_len = 8;
-+
-+		if (bmcast)
-+			AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
-+		else
-+			AES_IV(pattrib->iv, psta->dot11txpn, 0);
-+
-+		break;
-+
-+	case _GCMP_:
-+	case _GCMP_256_:
-+
-+		pattrib->iv_len = 8;
-+		pattrib->icv_len = 16;
-+
-+		if (bmcast)
-+			GCMP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
-+		else
-+			GCMP_IV(pattrib->iv, psta->dot11txpn, 0);
-+
-+		break;
-+
-+	case _CCMP_256_:
-+
-+		pattrib->iv_len = 8;
-+		pattrib->icv_len = 16;
-+
-+		if (bmcast)
-+			GCMP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
-+		else
-+			GCMP_IV(pattrib->iv, psta->dot11txpn, 0);
-+
-+		break;
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	case _SMS4_:
-+		pattrib->iv_len = 18;
-+		pattrib->icv_len = 16;
-+		rtw_wapi_get_iv(padapter, pattrib->ra, pattrib->iv);
-+		break;
-+#endif
-+	default:
-+		pattrib->iv_len = 0;
-+		pattrib->icv_len = 0;
-+		break;
-+	}
-+
-+	if (pattrib->encrypt > 0) {
-+		_rtw_memcpy(pattrib->dot118021x_UncstKey.skey
-+			, psta->dot118021x_UncstKey.skey
-+			, (pattrib->encrypt & _SEC_TYPE_256_) ? 32 : 16);
-+	}
-+
-+
-+	if (pattrib->encrypt &&
-+	    ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE))) {
-+		pattrib->bswenc = _TRUE;
-+	} else {
-+		pattrib->bswenc = _FALSE;
-+	}
-+
-+	pattrib->bmc_camid = padapter->securitypriv.dot118021x_bmc_cam_id;
-+
-+	if (pattrib->encrypt && bmcast && _rtw_camctl_chk_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH))
-+		pattrib->bswenc = _TRUE;
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	if (pattrib->encrypt == _SMS4_)
-+		pattrib->bswenc = _FALSE;
-+#endif
-+
-+exit:
-+
-+	return res;
-+
-+}
-+
-+u8	qos_acm(u8 acm_mask, u8 priority)
-+{
-+	u8	change_priority = priority;
-+
-+	switch (priority) {
-+	case 0:
-+	case 3:
-+		if (acm_mask & BIT(1))
-+			change_priority = 1;
-+		break;
-+	case 1:
-+	case 2:
-+		break;
-+	case 4:
-+	case 5:
-+		if (acm_mask & BIT(2))
-+			change_priority = 0;
-+		break;
-+	case 6:
-+	case 7:
-+		if (acm_mask & BIT(3))
-+			change_priority = 5;
-+		break;
-+	default:
-+		RTW_INFO("qos_acm(): invalid pattrib->priority: %d!!!\n", priority);
-+		break;
-+	}
-+
-+	return change_priority;
-+}
-+
-+/* refer to IEEE802.11-2016 Table R-3; Comply with IETF RFC4594 */
-+static u8 tos_to_up(u8 tos)
-+{
-+	u8 up = 0;
-+	u8 dscp;
-+	u8 mode = CONFIG_RTW_UP_MAPPING_RULE;
-+
-+
-+	/* tos precedence mapping */
-+	if (mode == 0) {
-+		up = tos >> 5;
-+		return up;
-+	}
-+
-+	/* refer to IEEE802.11-2016 Table R-3;
-+	 * DCSP 32(CS4) comply with IETF RFC4594
-+	 */
-+	dscp = (tos >> 2);
-+
-+	if ( dscp == 0 )
-+		up = 0;
-+	else if ( dscp >= 1 && dscp <= 9)
-+		up = 1;
-+	else if ( dscp >= 10 && dscp <= 16)
-+		up = 2;
-+	else if ( dscp >= 17 && dscp <= 23)
-+		up = 3;
-+	else if ( dscp >= 24 && dscp <= 31)
-+		up = 4;
-+	else if ( dscp >= 33 && dscp <= 40)
-+		up = 5;
-+	else if ((dscp >= 41 && dscp <= 47) || (dscp == 32))
-+		up = 6;
-+	else if ( dscp >= 48 && dscp <= 63)
-+		up = 7;
-+
-+	return up;
-+}
-+
-+static void set_qos(_pkt *pkt, struct pkt_attrib *pattrib)
-+{
-+	s32 UserPriority = 0;
-+
-+	if (!pkt)
-+		goto null_pkt;
-+
-+	/* get UserPriority from IP hdr */
-+	if (pattrib->ether_type == 0x0800) {
-+		struct pkt_file ppktfile;
-+		struct ethhdr etherhdr;
-+		struct iphdr ip_hdr;
-+
-+		_rtw_open_pktfile(pkt, &ppktfile);
-+		_rtw_pktfile_read(&ppktfile, (unsigned char *)&etherhdr, ETH_HLEN);
-+		_rtw_pktfile_read(&ppktfile, (u8 *)&ip_hdr, sizeof(ip_hdr));
-+		/*		UserPriority = (ntohs(ip_hdr.tos) >> 5) & 0x3; */
-+		UserPriority = tos_to_up(ip_hdr.tos);
-+	}
-+	/*
-+		else if (pattrib->ether_type == 0x888e) {
-+
-+
-+			UserPriority = 7;
-+		}
-+	*/
-+
-+	#ifdef CONFIG_ICMP_VOQ
-+	if(pattrib->icmp_pkt==1)/*use VO queue to send icmp packet*/
-+		UserPriority = 7;
-+	#endif
-+	#ifdef CONFIG_IP_R_MONITOR
-+	if (pattrib->ether_type == ETH_P_ARP)
-+		UserPriority = 7;
-+	#endif/*CONFIG_IP_R_MONITOR*/
-+
-+null_pkt:
-+	pattrib->priority = UserPriority;
-+	pattrib->hdrlen = XATTRIB_GET_WDS(pattrib) ? WLAN_HDR_A4_QOS_LEN : WLAN_HDR_A3_QOS_LEN;
-+	pattrib->subtype = WIFI_QOS_DATA_TYPE;
-+}
-+
-+#ifdef CONFIG_TDLS
-+u8 rtw_check_tdls_established(_adapter *padapter, struct pkt_attrib *pattrib)
-+{
-+	pattrib->ptdls_sta = NULL;
-+
-+	pattrib->direct_link = _FALSE;
-+	if (padapter->tdlsinfo.link_established == _TRUE) {
-+		pattrib->ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst);
-+#if 1
-+		if ((pattrib->ptdls_sta != NULL) &&
-+		    (pattrib->ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) &&
-+		    (pattrib->ether_type != 0x0806)) {
-+			pattrib->direct_link = _TRUE;
-+			/* RTW_INFO("send ptk to "MAC_FMT" using direct link\n", MAC_ARG(pattrib->dst)); */
-+		}
-+#else
-+		if (pattrib->ptdls_sta != NULL &&
-+		    pattrib->ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
-+			pattrib->direct_link = _TRUE;
-+#if 0
-+			RTW_INFO("send ptk to "MAC_FMT" using direct link\n", MAC_ARG(pattrib->dst));
-+#endif
-+		}
-+
-+		/* ARP frame may be helped by AP*/
-+		if (pattrib->ether_type != 0x0806)
-+			pattrib->direct_link = _FALSE;
-+#endif
-+	}
-+
-+	return pattrib->direct_link;
-+}
-+
-+s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
-+{
-+
-+	struct sta_info *psta = NULL;
-+	struct sta_priv		*pstapriv = &padapter->stapriv;
-+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
-+
-+	s32 res = _SUCCESS;
-+
-+	psta = rtw_get_stainfo(pstapriv, pattrib->ra);
-+	if (psta == NULL)	{
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pattrib->mac_id = psta->cmn.mac_id;
-+	pattrib->psta = psta;
-+	pattrib->ack_policy = 0;
-+	/* get ether_hdr_len */
-+	pattrib->pkt_hdrlen = ETH_HLEN;
-+
-+	pattrib->qos_en = psta->qos_option;
-+
-+	/* [TDLS] TODO: setup req/rsp should be AC_BK */
-+	if (pqospriv->qos_option &&  psta->qos_option) {
-+		pattrib->priority = 4;	/* tdls management frame should be AC_VI */
-+		pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN;
-+		pattrib->subtype = WIFI_QOS_DATA_TYPE;
-+	} else {
-+		pattrib->priority = 0;
-+		pattrib->hdrlen = WLAN_HDR_A3_LEN;
-+		pattrib->subtype = WIFI_DATA_TYPE;
-+	}
-+
-+	/* TODO:_lock */
-+	if (update_attrib_sec_info(padapter, pattrib, psta, NON_EAPOL) == _FAIL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	update_attrib_phy_info(padapter, pattrib, psta);
-+
-+
-+exit:
-+
-+	return res;
-+}
-+
-+#endif /* CONFIG_TDLS */
-+
-+/*get non-qos hw_ssn control register,mapping to REG_HW_SEQ 0,1,2,3*/
-+inline u8 rtw_get_hwseq_no(_adapter *padapter)
-+{
-+	u8 hwseq_num = 0;
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) \
-+	    || defined(CONFIG_RTL8723F)
-+	hwseq_num = padapter->iface_id;
-+	if (hwseq_num > 3)
-+		hwseq_num = 3;
-+	#else
-+	if (!is_primary_adapter(padapter))
-+		hwseq_num = 1;
-+	#endif
-+#endif /* CONFIG_CONCURRENT_MODE */
-+	return hwseq_num;
-+}
-+#ifdef CONFIG_LPS
-+#define LPS_PT_NORMAL	0
-+#define LPS_PT_SP		1/* only DHCP packets is as SPECIAL_PACKET*/
-+#define LPS_PT_ICMP		2
-+
-+/*If EAPOL , ARP , OR DHCP packet, driver must be in active mode.*/
-+static u8 _rtw_lps_chk_packet_type(struct pkt_attrib *pattrib)
-+{
-+	u8 pkt_type = LPS_PT_NORMAL; /*normal data frame*/
-+
-+	#ifdef CONFIG_WAPI_SUPPORT
-+	if ((pattrib->ether_type == 0x88B4) || (pattrib->ether_type == 0x0806) || (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1))
-+		pkt_type = LPS_PT_SP;
-+	#else /* !CONFIG_WAPI_SUPPORT */
-+
-+	#ifndef CONFIG_LPS_NOT_LEAVE_FOR_ICMP
-+	if (pattrib->icmp_pkt == 1)
-+		pkt_type = LPS_PT_ICMP;
-+	else
-+	#endif
-+		if (pattrib->dhcp_pkt == 1)
-+			pkt_type = LPS_PT_SP;
-+	#endif
-+	return pkt_type;
-+}
-+#endif
-+static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattrib)
-+{
-+	uint i;
-+	struct pkt_file pktfile;
-+	struct sta_info *psta = NULL;
-+	struct ethhdr etherhdr;
-+
-+	sint bmcast;
-+	struct sta_priv		*pstapriv = &padapter->stapriv;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
-+	struct xmit_priv		*pxmitpriv = &padapter->xmitpriv;
-+	sint res = _SUCCESS;
-+	enum eap_type eapol_type = NON_EAPOL;
-+#ifdef CONFIG_LPS
-+	u8 pkt_type = 0;
-+#endif
-+
-+	DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib);
-+
-+	_rtw_open_pktfile(pkt, &pktfile);
-+	i = _rtw_pktfile_read(&pktfile, (u8 *)&etherhdr, ETH_HLEN);
-+
-+	pattrib->ether_type = ntohs(etherhdr.h_proto);
-+
-+	if (MLME_STATE(padapter) & (WIFI_AP_STATE | WIFI_MESH_STATE)) /* address resolve is done for ap/mesh */
-+		goto get_sta_info;
-+
-+	_rtw_memcpy(pattrib->dst, &etherhdr.h_dest, ETH_ALEN);
-+	_rtw_memcpy(pattrib->src, &etherhdr.h_source, ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, adapter_mac_addr(padapter), ETH_ALEN);
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||
-+	    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
-+		_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
-+		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_adhoc);
-+	} else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
-+		#ifdef CONFIG_TDLS
-+		if (rtw_check_tdls_established(padapter, pattrib) == _TRUE)
-+			_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);	/* For TDLS direct link Tx, set ra to be same to dst */
-+		else
-+		#endif
-+		{
-+			_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
-+			#ifdef CONFIG_RTW_WDS
-+			if (adapter_use_wds(padapter)
-+				&& _rtw_memcmp(pattrib->src, pattrib->ta, ETH_ALEN) == _FALSE
-+			) {
-+				pattrib->wds = 1;
-+				if (IS_MCAST(pattrib->dst))
-+					rtw_tx_wds_gptr_update(padapter, pattrib->src);
-+			}
-+			#endif
-+		}
-+		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_sta);
-+	} else
-+		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_unknown);
-+
-+get_sta_info:
-+	bmcast = IS_MCAST(pattrib->ra);
-+	if (bmcast) {
-+		psta = rtw_get_bcmc_stainfo(padapter);
-+		if (psta == NULL) { /* if we cannot get psta => drop the pkt */
-+			DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sta);
-+			#ifdef DBG_TX_DROP_FRAME
-+			RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra));
-+			#endif
-+			res = _FAIL;
-+			goto exit;
-+		}
-+	} else {
-+		psta = rtw_get_stainfo(pstapriv, pattrib->ra);
-+		if (psta == NULL) { /* if we cannot get psta => drop the pkt */
-+			DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_sta);
-+			#ifdef DBG_TX_DROP_FRAME
-+			RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra));
-+			#endif
-+			res = _FAIL;
-+			goto exit;
-+		} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && !(psta->state & WIFI_ASOC_STATE)) {
-+			DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_ap_link);
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		#ifdef CONFIG_RTW_WDS
-+		if (XATTRIB_GET_WDS(pattrib) && !(psta->flags & WLAN_STA_WDS))
-+			pattrib->wds = 0;
-+		#endif
-+	}
-+
-+	if (!(psta->state & WIFI_ASOC_STATE)) {
-+		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_link);
-+		RTW_INFO("%s-"ADPT_FMT" psta("MAC_FMT")->state(0x%x) != WIFI_ASOC_STATE\n",
-+			__func__, ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr), psta->state);
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pattrib->pktlen = pktfile.pkt_len;
-+
-+	/* TODO: 802.1Q VLAN header */
-+	/* TODO: IPV6 */
-+
-+	if (ETH_P_IP == pattrib->ether_type) {
-+		u8 ip[20];
-+
-+		_rtw_pktfile_read(&pktfile, ip, 20);
-+
-+		if (GET_IPV4_IHL(ip) * 4 > 20)
-+			_rtw_pktfile_read(&pktfile, NULL, GET_IPV4_IHL(ip) - 20);
-+
-+		pattrib->icmp_pkt = 0;
-+		pattrib->dhcp_pkt = 0;
-+		pattrib->hipriority_pkt = 0;
-+
-+		if (GET_IPV4_PROTOCOL(ip) == 0x01) { /* ICMP */
-+			pattrib->icmp_pkt = 1;
-+			DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_icmp);
-+
-+		} else if (GET_IPV4_PROTOCOL(ip) == 0x11) { /* UDP */
-+			u8 udp[24];
-+
-+			_rtw_pktfile_read(&pktfile, udp, 24);
-+
-+			if ((GET_UDP_SRC(udp) == 68 && GET_UDP_DST(udp) == 67)
-+				|| (GET_UDP_SRC(udp) == 67 && GET_UDP_DST(udp) == 68)
-+			) {
-+				/* 67 : UDP BOOTP server, 68 : UDP BOOTP client */
-+				if (pattrib->pktlen > 282) { /* MINIMUM_DHCP_PACKET_SIZE */
-+					pattrib->dhcp_pkt = 1;
-+					DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_dhcp);
-+					if (0)
-+						RTW_INFO("send DHCP packet\n");
-+				}
-+			}
-+
-+			/* WaveAgent packet, increase priority so that the system can read data in time */
-+			if (((GET_UDP_SIG1(udp) == 0xcc) || (GET_UDP_SIG1(udp) == 0xdd)) &&
-+				(GET_UDP_SIG2(udp) == 0xe2)) {
-+				pattrib->hipriority_pkt = 1;
-+			}
-+
-+		} else if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */
-+			&& rtw_st_ctl_chk_reg_s_proto(&psta->st_ctl, 0x06) == _TRUE
-+		) {
-+			u8 tcp[20];
-+
-+			_rtw_pktfile_read(&pktfile, tcp, 20);
-+
-+			if (rtw_st_ctl_chk_reg_rule(&psta->st_ctl, padapter, IPV4_SRC(ip), TCP_SRC(tcp), IPV4_DST(ip), TCP_DST(tcp)) == _TRUE) {
-+				if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) {
-+					session_tracker_add_cmd(padapter, psta
-+						, IPV4_SRC(ip), TCP_SRC(tcp)
-+						, IPV4_SRC(ip), TCP_DST(tcp));
-+					if (DBG_SESSION_TRACKER)
-+						RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n"
-+							, FUNC_ADPT_ARG(padapter)
-+							, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))
-+							, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)));
-+				}
-+				if (GET_TCP_FIN(tcp)) {
-+					session_tracker_del_cmd(padapter, psta
-+						, IPV4_SRC(ip), TCP_SRC(tcp)
-+						, IPV4_SRC(ip), TCP_DST(tcp));
-+					if (DBG_SESSION_TRACKER)
-+						RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n"
-+							, FUNC_ADPT_ARG(padapter)
-+							, IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))
-+							, IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)));
-+				}
-+			}
-+		}
-+
-+	} else if (0x888e == pattrib->ether_type)
-+		eapol_type = parsing_eapol_packet(padapter, pktfile.cur_addr, psta, 1);
-+#if defined (DBG_ARP_DUMP) || defined (DBG_IP_R_MONITOR)
-+	else if (pattrib->ether_type == ETH_P_ARP) {
-+		u8 arp[28] = {0};
-+
-+		_rtw_pktfile_read(&pktfile, arp, 28);
-+		dump_arp_pkt(RTW_DBGDUMP, etherhdr.h_dest, etherhdr.h_source, arp, 1);
-+	}
-+#endif
-+
-+	if ((pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1))
-+		rtw_mi_set_scan_deny(padapter, 3000);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) &&
-+		pattrib->ether_type == ETH_P_ARP &&
-+		!IS_MCAST(pattrib->dst)) {
-+		rtw_mi_set_scan_deny(padapter, 1000);
-+		rtw_mi_scan_abort(padapter, _FALSE); /*rtw_scan_abort_no_wait*/
-+	}
-+
-+#ifdef CONFIG_LPS
-+	pkt_type = _rtw_lps_chk_packet_type(pattrib);
-+
-+	if (pkt_type == LPS_PT_SP) {/*packet is as SPECIAL_PACKET*/
-+		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_active);
-+		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SPECIAL_PACKET, 0);
-+	} else if (pkt_type == LPS_PT_ICMP)
-+		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0);
-+#endif /* CONFIG_LPS */
-+
-+#ifdef CONFIG_BEAMFORMING
-+	update_attrib_txbf_info(padapter, pattrib, psta);
-+#endif
-+
-+	/* TODO:_lock */
-+	if (update_attrib_sec_info(padapter, pattrib, psta, eapol_type) == _FAIL) {
-+		DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sec);
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	/* get ether_hdr_len */
-+	pattrib->pkt_hdrlen = ETH_HLEN;/* (pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; */ /* vlan tag */
-+
-+	pattrib->hdrlen = XATTRIB_GET_WDS(pattrib) ? WLAN_HDR_A4_LEN : WLAN_HDR_A3_LEN;
-+	pattrib->subtype = WIFI_DATA_TYPE;
-+	pattrib->qos_en = psta->qos_option;
-+	pattrib->priority = 0;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE
-+		| WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)
-+	) {
-+		if (pattrib->qos_en) {
-+			set_qos(pkt, pattrib);
-+			#ifdef CONFIG_RTW_MESH
-+			if (MLME_IS_MESH(padapter))
-+				rtw_mesh_tx_set_whdr_mctrl_len(pattrib->mesh_frame_mode, pattrib);
-+			#endif
-+		}
-+	} else {
-+#ifdef CONFIG_TDLS
-+		if (pattrib->direct_link == _TRUE) {
-+			if (pattrib->qos_en)
-+				set_qos(pkt, pattrib);
-+		} else
-+#endif
-+		{
-+			if (pqospriv->qos_option) {
-+				set_qos(pkt, pattrib);
-+
-+				if (pmlmepriv->acm_mask != 0)
-+					pattrib->priority = qos_acm(pmlmepriv->acm_mask, pattrib->priority);
-+			}
-+		}
-+	}
-+	
-+	update_attrib_phy_info(padapter, pattrib, psta);
-+
-+	/* RTW_INFO("%s ==> mac_id(%d)\n",__FUNCTION__,pattrib->mac_id ); */
-+
-+	pattrib->psta = psta;
-+	/* TODO:_unlock */
-+
-+#ifdef CONFIG_AUTO_AP_MODE
-+	if (psta->isrc && psta->pid > 0)
-+		pattrib->pctrl = _TRUE;
-+	else
-+#endif
-+		pattrib->pctrl = 0;
-+
-+	pattrib->ack_policy = 0;
-+
-+	if (bmcast)
-+		pattrib->rate = psta->init_rate;
-+
-+
-+#ifdef CONFIG_WMMPS_STA
-+	update_attrib_trigger_frame_info(padapter, pattrib);
-+#endif /* CONFIG_WMMPS_STA */	
-+
-+	/* pattrib->priority = 5; */ /* force to used VI queue, for testing */
-+	pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no;
-+	rtw_set_tx_chksum_offload(pkt, pattrib);
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe)
-+{
-+	sint			curfragnum, length;
-+	u8	*pframe, *payload, mic[8];
-+	struct	mic_data		micdata;
-+	/* struct	sta_info		*stainfo; */
-+	struct	pkt_attrib	*pattrib = &pxmitframe->attrib;
-+	struct	security_priv	*psecuritypriv = &padapter->securitypriv;
-+	struct	xmit_priv		*pxmitpriv = &padapter->xmitpriv;
-+	u8 priority[4] = {0x0, 0x0, 0x0, 0x0};
-+	u8 hw_hdr_offset = 0;
-+	sint bmcst = IS_MCAST(pattrib->ra);
-+
-+	/*
-+		if(pattrib->psta)
-+		{
-+			stainfo = pattrib->psta;
-+		}
-+		else
-+		{
-+			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
-+			stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]);
-+		}
-+
-+		if(stainfo==NULL)
-+		{
-+			RTW_INFO("%s, psta==NUL\n", __func__);
-+			return _FAIL;
-+		}
-+
-+		if(!(stainfo->state &WIFI_ASOC_STATE))
-+		{
-+			RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, stainfo->state);
-+			return _FAIL;
-+		}
-+	*/
-+
-+
-+#ifdef CONFIG_USB_TX_AGGREGATION
-+	hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);;
-+#else
-+#ifdef CONFIG_TX_EARLY_MODE
-+	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
-+#else
-+	hw_hdr_offset = TXDESC_OFFSET;
-+#endif
-+#endif
-+
-+	if (pattrib->encrypt == _TKIP_) { /* if(psecuritypriv->dot11PrivacyAlgrthm==_TKIP_PRIVACY_) */
-+		/* encode mic code */
-+		/* if(stainfo!= NULL) */
-+		{
-+			u8 null_key[16] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
-+
-+			pframe = pxmitframe->buf_addr + hw_hdr_offset;
-+
-+			if (bmcst) {
-+				if (_rtw_memcmp(psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey, null_key, 16) == _TRUE) {
-+					/* DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); */
-+					/* rtw_msleep_os(10); */
-+					return _FAIL;
-+				}
-+				/* start to calculate the mic code */
-+				rtw_secmicsetkey(&micdata, psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey);
-+			} else {
-+				if (_rtw_memcmp(&pattrib->dot11tkiptxmickey.skey[0], null_key, 16) == _TRUE) {
-+					/* DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); */
-+					/* rtw_msleep_os(10); */
-+					return _FAIL;
-+				}
-+				/* start to calculate the mic code */
-+				rtw_secmicsetkey(&micdata, &pattrib->dot11tkiptxmickey.skey[0]);
-+			}
-+
-+			if (pframe[1] & 1) { /* ToDS==1 */
-+				rtw_secmicappend(&micdata, &pframe[16], 6);  /* DA */
-+				if (pframe[1] & 2) /* From Ds==1 */
-+					rtw_secmicappend(&micdata, &pframe[24], 6);
-+				else
-+					rtw_secmicappend(&micdata, &pframe[10], 6);
-+			} else {	/* ToDS==0 */
-+				rtw_secmicappend(&micdata, &pframe[4], 6);   /* DA */
-+				if (pframe[1] & 2) /* From Ds==1 */
-+					rtw_secmicappend(&micdata, &pframe[16], 6);
-+				else
-+					rtw_secmicappend(&micdata, &pframe[10], 6);
-+
-+			}
-+
-+			if (pattrib->qos_en)
-+				priority[0] = (u8)pxmitframe->attrib.priority;
-+
-+
-+			rtw_secmicappend(&micdata, &priority[0], 4);
-+
-+			payload = pframe;
-+
-+			for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
-+				payload = (u8 *)RND4((SIZE_PTR)(payload));
-+
-+				payload = payload + pattrib->hdrlen + pattrib->iv_len;
-+				if ((curfragnum + 1) == pattrib->nr_frags) {
-+					length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0);
-+					rtw_secmicappend(&micdata, payload, length);
-+					payload = payload + length;
-+				} else {
-+					length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0);
-+					rtw_secmicappend(&micdata, payload, length);
-+					payload = payload + length + pattrib->icv_len;
-+				}
-+			}
-+			rtw_secgetmic(&micdata, &(mic[0]));
-+			/* add mic code  and add the mic code length in last_txcmdsz */
-+
-+			_rtw_memcpy(payload, &(mic[0]), 8);
-+			pattrib->last_txcmdsz += 8;
-+
-+			payload = payload - pattrib->last_txcmdsz + 8;
-+		}
-+	}
-+
-+
-+	return _SUCCESS;
-+}
-+
-+/*#define DBG_TX_SW_ENCRYPTOR*/
-+
-+static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe)
-+{
-+
-+	struct	pkt_attrib	*pattrib = &pxmitframe->attrib;
-+	/* struct 	security_priv	*psecuritypriv=&padapter->securitypriv; */
-+
-+
-+	/* if((psecuritypriv->sw_encrypt)||(pattrib->bswenc))	 */
-+	if (pattrib->bswenc) {
-+#ifdef DBG_TX_SW_ENCRYPTOR
-+		RTW_INFO(ADPT_FMT" - sec_type:%s DO SW encryption\n",
-+			ADPT_ARG(padapter), security_type_str(pattrib->encrypt));
-+#endif
-+
-+		switch (pattrib->encrypt) {
-+		case _WEP40_:
-+		case _WEP104_:
-+			rtw_wep_encrypt(padapter, (u8 *)pxmitframe);
-+			break;
-+		case _TKIP_:
-+			rtw_tkip_encrypt(padapter, (u8 *)pxmitframe);
-+			break;
-+		case _AES_:
-+		case _CCMP_256_:
-+			rtw_aes_encrypt(padapter, (u8 *)pxmitframe);
-+			break;
-+		case _GCMP_:
-+		case _GCMP_256_:
-+			rtw_gcmp_encrypt(padapter, (u8 *)pxmitframe);
-+			break;
-+#ifdef CONFIG_WAPI_SUPPORT
-+		case _SMS4_:
-+			rtw_sms4_encrypt(padapter, (u8 *)pxmitframe);
-+#endif
-+		default:
-+			break;
-+		}
-+
-+	}
-+
-+
-+	return _SUCCESS;
-+}
-+
-+s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib)
-+{
-+	u16 *qc;
-+
-+	struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct qos_priv *pqospriv = &pmlmepriv->qospriv;
-+	u8 qos_option = _FALSE;
-+	sint res = _SUCCESS;
-+	u16 *fctrl = &pwlanhdr->frame_ctl;
-+
-+	/* struct sta_info *psta; */
-+
-+	/* sint bmcst = IS_MCAST(pattrib->ra); */
-+
-+
-+	/*
-+		psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
-+		if(pattrib->psta != psta)
-+		{
-+			RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
-+			return;
-+		}
-+
-+		if(psta==NULL)
-+		{
-+			RTW_INFO("%s, psta==NUL\n", __func__);
-+			return _FAIL;
-+		}
-+
-+		if(!(psta->state &WIFI_ASOC_STATE))
-+		{
-+			RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
-+			return _FAIL;
-+		}
-+	*/
-+
-+	_rtw_memset(hdr, 0, WLANHDR_OFFSET);
-+
-+	set_frame_sub_type(fctrl, pattrib->subtype);
-+
-+	if (pattrib->subtype & WIFI_DATA_TYPE) {
-+		if ((check_fwstate(pmlmepriv,  WIFI_STATION_STATE) == _TRUE)) {
-+#ifdef CONFIG_TDLS
-+			if (pattrib->direct_link == _TRUE) {
-+				/* TDLS data transfer, ToDS=0, FrDs=0 */
-+				_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
-+				_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
-+				_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
-+
-+				if (pattrib->qos_en)
-+					qos_option = _TRUE;
-+			} else
-+#endif /* CONFIG_TDLS */
-+			{
-+				#ifdef CONFIG_RTW_WDS
-+				if (pattrib->wds) {
-+					SetToDs(fctrl);
-+					SetFrDs(fctrl);
-+					_rtw_memcpy(pwlanhdr->addr1, pattrib->ra, ETH_ALEN);
-+					_rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN);
-+					_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
-+					_rtw_memcpy(pwlanhdr->addr4, pattrib->src, ETH_ALEN);
-+				} else
-+				#endif
-+				{
-+					/* to_ds = 1, fr_ds = 0; */
-+					/* 1.Data transfer to AP */
-+					/* 2.Arp pkt will relayed by AP */
-+					SetToDs(fctrl);
-+					_rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);
-+					_rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN);
-+					_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
-+				}
-+
-+				if (pqospriv->qos_option)
-+					qos_option = _TRUE;
-+			}
-+		} else if ((check_fwstate(pmlmepriv,  WIFI_AP_STATE) == _TRUE)) {
-+			#ifdef CONFIG_RTW_WDS
-+			if (pattrib->wds) {
-+				SetToDs(fctrl);
-+				SetFrDs(fctrl);
-+				_rtw_memcpy(pwlanhdr->addr1, pattrib->ra, ETH_ALEN);
-+				_rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN);
-+				_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
-+				_rtw_memcpy(pwlanhdr->addr4, pattrib->src, ETH_ALEN);
-+			} else
-+			#endif
-+			{
-+				/* to_ds = 0, fr_ds = 1; */
-+				SetFrDs(fctrl);
-+				_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
-+				_rtw_memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN);
-+				_rtw_memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN);
-+			}
-+
-+			if (pattrib->qos_en)
-+				qos_option = _TRUE;
-+		} else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||
-+			(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
-+			_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
-+			_rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN);
-+			_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
-+
-+			if (pattrib->qos_en)
-+				qos_option = _TRUE;
-+#ifdef CONFIG_RTW_MESH
-+		} else if (check_fwstate(pmlmepriv, WIFI_MESH_STATE) == _TRUE) {
-+			rtw_mesh_tx_build_whdr(padapter, pattrib, fctrl, pwlanhdr);
-+			if (pattrib->qos_en)
-+				qos_option = _TRUE;
-+			else {
-+				RTW_WARN("[%s] !qos_en in Mesh\n", __FUNCTION__);
-+				res = _FAIL;
-+				goto exit;
-+			}
-+#endif
-+		} else {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		if (pattrib->mdata)
-+			SetMData(fctrl);
-+
-+		if (pattrib->encrypt)
-+			SetPrivacy(fctrl);
-+
-+		if (qos_option) {
-+			qc = (unsigned short *)(hdr + pattrib->hdrlen - 2);
-+
-+			if (pattrib->priority)
-+				SetPriority(qc, pattrib->priority);
-+
-+			SetEOSP(qc, pattrib->eosp);
-+
-+			SetAckpolicy(qc, pattrib->ack_policy);
-+
-+			if(pattrib->amsdu)
-+				SetAMsdu(qc, pattrib->amsdu);
-+#ifdef CONFIG_RTW_MESH
-+			if (MLME_IS_MESH(padapter)) {
-+				/* active: don't care, light sleep: 0, deep sleep: 1*/
-+				set_mps_lv(qc, 0); //TBD
-+
-+				/* TBD: temporary set (rspi, eosp) = (0, 1) which means End MPSP */
-+				set_rspi(qc, 0);
-+				SetEOSP(qc, 1);
-+				
-+				set_mctrl_present(qc, 1);
-+			}
-+#endif
-+		}
-+
-+		/* TODO: fill HT Control Field */
-+
-+		/* Update Seq Num will be handled by f/w */
-+		{
-+			struct sta_info *psta;
-+			psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
-+			if (pattrib->psta != psta) {
-+				RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
-+				return _FAIL;
-+			}
-+
-+			if (psta == NULL) {
-+				RTW_INFO("%s, psta==NUL\n", __func__);
-+				return _FAIL;
-+			}
-+
-+			if (!(psta->state & WIFI_ASOC_STATE)) {
-+				RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
-+				return _FAIL;
-+			}
-+
-+
-+			if (psta) {
-+				psta->sta_xmitpriv.txseq_tid[pattrib->priority]++;
-+				psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;
-+				pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority];
-+
-+				SetSeqNum(hdr, pattrib->seqnum);
-+
-+#ifdef CONFIG_80211N_HT
-+#if 0 /* move into update_attrib_phy_info(). */
-+				/* check if enable ampdu */
-+				if (pattrib->ht_en && psta->htpriv.ampdu_enable) {
-+					if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority))
-+						pattrib->ampdu_en = _TRUE;
-+				}
-+#endif
-+				/* re-check if enable ampdu by BA_starting_seqctrl */
-+				if (pattrib->ampdu_en == _TRUE) {
-+					u16 tx_seq;
-+
-+					tx_seq = psta->BA_starting_seqctrl[pattrib->priority & 0x0f];
-+
-+					/* check BA_starting_seqctrl */
-+					if (SN_LESS(pattrib->seqnum, tx_seq)) {
-+						/* RTW_INFO("tx ampdu seqnum(%d) < tx_seq(%d)\n", pattrib->seqnum, tx_seq); */
-+						pattrib->ampdu_en = _FALSE;/* AGG BK */
-+					} else if (SN_EQUAL(pattrib->seqnum, tx_seq)) {
-+						psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (tx_seq + 1) & 0xfff;
-+
-+						pattrib->ampdu_en = _TRUE;/* AGG EN */
-+					} else {
-+						/* RTW_INFO("tx ampdu over run\n"); */
-+						psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (pattrib->seqnum + 1) & 0xfff;
-+						pattrib->ampdu_en = _TRUE;/* AGG EN */
-+					}
-+
-+				}
-+#endif /* CONFIG_80211N_HT */
-+			}
-+		}
-+
-+	} else {
-+
-+	}
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+s32 rtw_txframes_pending(_adapter *padapter)
-+{
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+
-+	return ((_rtw_queue_empty(&pxmitpriv->be_pending) == _FALSE) ||
-+		(_rtw_queue_empty(&pxmitpriv->bk_pending) == _FALSE) ||
-+		(_rtw_queue_empty(&pxmitpriv->vi_pending) == _FALSE) ||
-+		(_rtw_queue_empty(&pxmitpriv->vo_pending) == _FALSE)
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+		|| (_rtw_queue_empty(&pxmitpriv->mgmt_pending) == _FALSE)
-+#endif
-+		);
-+}
-+
-+s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib)
-+{
-+	struct sta_info *psta;
-+	struct tx_servq *ptxservq;
-+	int priority = pattrib->priority;
-+	/*
-+		if(pattrib->psta)
-+		{
-+			psta = pattrib->psta;
-+		}
-+		else
-+		{
-+			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
-+			psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]);
-+		}
-+	*/
-+	psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
-+	if (pattrib->psta != psta) {
-+		RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
-+		return 0;
-+	}
-+
-+	if (psta == NULL) {
-+		RTW_INFO("%s, psta==NUL\n", __func__);
-+		return 0;
-+	}
-+
-+	if (!(psta->state & WIFI_ASOC_STATE)) {
-+		RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
-+		return 0;
-+	}
-+
-+	switch (priority) {
-+	case 1:
-+	case 2:
-+		ptxservq = &(psta->sta_xmitpriv.bk_q);
-+		break;
-+	case 4:
-+	case 5:
-+		ptxservq = &(psta->sta_xmitpriv.vi_q);
-+		break;
-+	case 6:
-+	case 7:
-+		ptxservq = &(psta->sta_xmitpriv.vo_q);
-+		break;
-+	case 0:
-+	case 3:
-+	default:
-+		ptxservq = &(psta->sta_xmitpriv.be_q);
-+		break;
-+
-+	}
-+
-+	return ptxservq->qcnt;
-+}
-+
-+#ifdef CONFIG_TDLS
-+
-+int rtw_build_tdls_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
-+{
-+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
-+	struct sta_info *ptdls_sta = NULL;
-+	int res = _SUCCESS;
-+
-+	ptdls_sta = rtw_get_stainfo((&padapter->stapriv), pattrib->dst);
-+	if (ptdls_sta == NULL) {
-+		switch (ptxmgmt->action_code) {
-+		case TDLS_DISCOVERY_REQUEST:
-+		case TUNNELED_PROBE_REQ:
-+		case TUNNELED_PROBE_RSP:
-+			break;
-+		default:
-+			RTW_INFO("[TDLS] %s - Direct Link Peer = "MAC_FMT" not found for action = %d\n", __func__, MAC_ARG(pattrib->dst), ptxmgmt->action_code);
-+			res = _FAIL;
-+			goto exit;
-+		}
-+	}
-+
-+	switch (ptxmgmt->action_code) {
-+	case TDLS_SETUP_REQUEST:
-+		rtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
-+		break;
-+	case TDLS_SETUP_RESPONSE:
-+		rtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
-+		break;
-+	case TDLS_SETUP_CONFIRM:
-+		rtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
-+		break;
-+	case TDLS_TEARDOWN:
-+		rtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
-+		break;
-+	case TDLS_DISCOVERY_REQUEST:
-+		rtw_build_tdls_dis_req_ies(padapter, pxmitframe, pframe, ptxmgmt);
-+		break;
-+	case TDLS_PEER_TRAFFIC_INDICATION:
-+		rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
-+		break;
-+#ifdef CONFIG_TDLS_CH_SW
-+	case TDLS_CHANNEL_SWITCH_REQUEST:
-+		rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
-+		break;
-+	case TDLS_CHANNEL_SWITCH_RESPONSE:
-+		rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
-+		break;
-+#endif
-+	case TDLS_PEER_TRAFFIC_RESPONSE:
-+		rtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
-+		break;
-+#ifdef CONFIG_WFD
-+	case TUNNELED_PROBE_REQ:
-+		rtw_build_tunneled_probe_req_ies(padapter, pxmitframe, pframe);
-+		break;
-+	case TUNNELED_PROBE_RSP:
-+		rtw_build_tunneled_probe_rsp_ies(padapter, pxmitframe, pframe);
-+		break;
-+#endif /* CONFIG_WFD */
-+	default:
-+		res = _FAIL;
-+		break;
-+	}
-+
-+exit:
-+	return res;
-+}
-+
-+s32 rtw_make_tdls_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt)
-+{
-+	u16 *qc;
-+	struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct qos_priv *pqospriv = &pmlmepriv->qospriv;
-+	struct sta_priv	*pstapriv = &padapter->stapriv;
-+	struct sta_info *psta = NULL, *ptdls_sta = NULL;
-+	u8 tdls_seq = 0, baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
-+
-+	sint res = _SUCCESS;
-+	u16 *fctrl = &pwlanhdr->frame_ctl;
-+
-+
-+	_rtw_memset(hdr, 0, WLANHDR_OFFSET);
-+
-+	set_frame_sub_type(fctrl, pattrib->subtype);
-+
-+	switch (ptxmgmt->action_code) {
-+	case TDLS_SETUP_REQUEST:
-+	case TDLS_SETUP_RESPONSE:
-+	case TDLS_SETUP_CONFIRM:
-+	case TDLS_PEER_TRAFFIC_INDICATION:
-+	case TDLS_PEER_PSM_REQUEST:
-+	case TUNNELED_PROBE_REQ:
-+	case TUNNELED_PROBE_RSP:
-+	case TDLS_DISCOVERY_REQUEST:
-+		SetToDs(fctrl);
-+		_rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
-+		break;
-+	case TDLS_CHANNEL_SWITCH_REQUEST:
-+	case TDLS_CHANNEL_SWITCH_RESPONSE:
-+	case TDLS_PEER_PSM_RESPONSE:
-+	case TDLS_PEER_TRAFFIC_RESPONSE:
-+		_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
-+		tdls_seq = 1;
-+		break;
-+	case TDLS_TEARDOWN:
-+		if (ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) {
-+			_rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN);
-+			_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
-+			_rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN);
-+			tdls_seq = 1;
-+		} else {
-+			SetToDs(fctrl);
-+			_rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN);
-+			_rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN);
-+			_rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN);
-+		}
-+		break;
-+	}
-+
-+	if (pattrib->encrypt)
-+		SetPrivacy(fctrl);
-+
-+	if (ptxmgmt->action_code == TDLS_PEER_TRAFFIC_RESPONSE)
-+		SetPwrMgt(fctrl);
-+
-+	if (pqospriv->qos_option) {
-+		qc = (unsigned short *)(hdr + pattrib->hdrlen - 2);
-+		if (pattrib->priority)
-+			SetPriority(qc, pattrib->priority);
-+		SetAckpolicy(qc, pattrib->ack_policy);
-+	}
-+
-+	psta = pattrib->psta;
-+
-+	/* 1. update seq_num per link by sta_info */
-+	/* 2. rewrite encrypt to _AES_, also rewrite iv_len, icv_len */
-+	if (tdls_seq == 1) {
-+		ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
-+		if (ptdls_sta) {
-+			ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]++;
-+			ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;
-+			pattrib->seqnum = ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority];
-+			SetSeqNum(hdr, pattrib->seqnum);
-+
-+			if (pattrib->encrypt) {
-+				pattrib->encrypt = _AES_;
-+				pattrib->iv_len = 8;
-+				pattrib->icv_len = 8;
-+				pattrib->bswenc = _FALSE;
-+			}
-+			pattrib->mac_id = ptdls_sta->cmn.mac_id;
-+		} else {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+	} else if (psta) {
-+		psta->sta_xmitpriv.txseq_tid[pattrib->priority]++;
-+		psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF;
-+		pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority];
-+		SetSeqNum(hdr, pattrib->seqnum);
-+	}
-+
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt)
-+{
-+	s32 llc_sz;
-+
-+	u8 *pframe, *mem_start;
-+
-+	struct sta_info		*psta;
-+	struct sta_priv		*pstapriv = &padapter->stapriv;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+	u8 *pbuf_start;
-+	s32 bmcst = IS_MCAST(pattrib->ra);
-+	s32 res = _SUCCESS;
-+
-+
-+	if (pattrib->psta)
-+		psta = pattrib->psta;
-+	else {
-+		if (bmcst)
-+			psta = rtw_get_bcmc_stainfo(padapter);
-+		else
-+			psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
-+	}
-+
-+	if (psta == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	if (pxmitframe->buf_addr == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pbuf_start = pxmitframe->buf_addr;
-+	mem_start = pbuf_start + TXDESC_OFFSET;
-+
-+	if (rtw_make_tdls_wlanhdr(padapter, mem_start, pattrib, ptxmgmt) == _FAIL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pframe = mem_start;
-+	pframe += pattrib->hdrlen;
-+
-+	/* adding icv, if necessary... */
-+	if (pattrib->iv_len) {
-+		if (psta != NULL) {
-+			switch (pattrib->encrypt) {
-+			case _WEP40_:
-+			case _WEP104_:
-+				WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
-+				break;
-+			case _TKIP_:
-+				if (bmcst)
-+					TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
-+				else
-+					TKIP_IV(pattrib->iv, psta->dot11txpn, 0);
-+				break;
-+			case _AES_:
-+				if (bmcst)
-+					AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
-+				else
-+					AES_IV(pattrib->iv, psta->dot11txpn, 0);
-+				break;
-+			}
-+		}
-+
-+		_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
-+		pframe += pattrib->iv_len;
-+
-+	}
-+
-+	llc_sz = rtw_put_snap(pframe, pattrib->ether_type);
-+	pframe += llc_sz;
-+
-+	/* pattrib->pktlen will be counted in rtw_build_tdls_ies */
-+	pattrib->pktlen = 0;
-+
-+	rtw_build_tdls_ies(padapter, pxmitframe, pframe, ptxmgmt);
-+
-+	if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
-+		pframe += pattrib->pktlen;
-+		_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
-+		pframe += pattrib->icv_len;
-+	}
-+
-+	pattrib->nr_frags = 1;
-+	pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + llc_sz +
-+		((pattrib->bswenc) ? pattrib->icv_len : 0) + pattrib->pktlen;
-+
-+	if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	xmitframe_swencrypt(padapter, pxmitframe);
-+
-+	update_attrib_vcs_info(padapter, pxmitframe);
-+
-+exit:
-+
-+
-+	return res;
-+}
-+#endif /* CONFIG_TDLS */
-+
-+/*
-+ * Calculate wlan 802.11 packet MAX size from pkt_attrib
-+ * This function doesn't consider fragment case
-+ */
-+u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib)
-+{
-+	u32	len = 0;
-+
-+	len = pattrib->hdrlen /* WLAN Header */
-+		+ pattrib->iv_len /* IV */
-+		+ XATTRIB_GET_MCTRL_LEN(pattrib)
-+		+ SNAP_SIZE + sizeof(u16) /* LLC */
-+		+ pattrib->pktlen
-+		+ (pattrib->encrypt == _TKIP_ ? 8 : 0) /* MIC */
-+		+ (pattrib->bswenc ? pattrib->icv_len : 0) /* ICV */
-+		;
-+
-+	return len;
-+}
-+
-+#ifdef CONFIG_TX_AMSDU
-+s32 check_amsdu(struct xmit_frame *pxmitframe)
-+{
-+	struct pkt_attrib *pattrib;
-+	s32 ret = _TRUE;
-+
-+	if (!pxmitframe)
-+		ret = _FALSE;
-+
-+	pattrib = &pxmitframe->attrib;
-+
-+	if (IS_MCAST(pattrib->ra))
-+		ret = _FALSE;
-+
-+	if ((pattrib->ether_type == 0x888e) ||
-+		(pattrib->ether_type == 0x0806) ||
-+		(pattrib->ether_type == 0x88b4) ||
-+		(pattrib->dhcp_pkt == 1))
-+		ret = _FALSE;
-+
-+	if ((pattrib->encrypt == _WEP40_) ||
-+	    (pattrib->encrypt == _WEP104_) ||
-+	    (pattrib->encrypt == _TKIP_))
-+		ret = _FALSE;
-+
-+	if (!pattrib->qos_en)
-+		ret = _FALSE;
-+
-+	if (IS_AMSDU_AMPDU_NOT_VALID(pattrib))
-+		ret = _FALSE;
-+
-+	return ret;
-+}
-+
-+s32 check_amsdu_tx_support(_adapter *padapter)
-+{
-+	struct dvobj_priv *pdvobjpriv;
-+	int tx_amsdu;
-+	int tx_amsdu_rate;
-+	int current_tx_rate;
-+	s32 ret = _FALSE;
-+
-+	pdvobjpriv = adapter_to_dvobj(padapter);
-+	tx_amsdu = padapter->tx_amsdu;
-+	tx_amsdu_rate = padapter->tx_amsdu_rate;
-+	current_tx_rate = pdvobjpriv->traffic_stat.cur_tx_tp;
-+
-+	if (tx_amsdu == 1)
-+		ret = _TRUE;
-+	else if (tx_amsdu == 2 && (tx_amsdu_rate == 0 || current_tx_rate > tx_amsdu_rate))
-+		ret = _TRUE;
-+	else
-+		ret = _FALSE;
-+
-+	return ret;
-+}
-+
-+s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue)
-+{
-+
-+	struct pkt_file pktfile;
-+	struct pkt_attrib *pattrib;
-+	_pkt *pkt;
-+
-+	struct pkt_file pktfile_queue;
-+	struct pkt_attrib *pattrib_queue;
-+	_pkt *pkt_queue;
-+
-+	s32 llc_sz, mem_sz;
-+
-+	s32 padding = 0;
-+
-+	u8 *pframe, *mem_start;
-+	u8 hw_hdr_offset;
-+
-+	u16* len;
-+	u8 *pbuf_start;
-+	s32 res = _SUCCESS;
-+
-+	if (pxmitframe->buf_addr == NULL) {
-+		RTW_INFO("==> %s buf_addr==NULL\n", __FUNCTION__);
-+		return _FAIL;
-+	}
-+
-+
-+	pbuf_start = pxmitframe->buf_addr;
-+
-+#ifdef CONFIG_USB_TX_AGGREGATION
-+	hw_hdr_offset =  TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);
-+#else
-+#ifdef CONFIG_TX_EARLY_MODE /* for SDIO && Tx Agg */
-+	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
-+#else
-+	hw_hdr_offset = TXDESC_OFFSET;
-+#endif
-+#endif
-+
-+	mem_start = pbuf_start + hw_hdr_offset; //for DMA
-+
-+	pattrib = &pxmitframe->attrib;
-+
-+	pattrib->amsdu = 1;
-+
-+	if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) {
-+		RTW_INFO("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n");
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	llc_sz = 0;
-+
-+	pframe = mem_start;
-+
-+	//SetMFrag(mem_start);
-+	ClearMFrag(mem_start);
-+
-+	pframe += pattrib->hdrlen;
-+
-+	/* adding icv, if necessary... */
-+	if (pattrib->iv_len) {
-+		_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); // queue or new?
-+
-+		RTW_DBG("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n",
-+			padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe + 1), *(pframe + 2), *(pframe + 3));
-+
-+		pframe += pattrib->iv_len;
-+	}
-+
-+	pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len;
-+
-+	if(pxmitframe_queue)
-+	{
-+		pattrib_queue = &pxmitframe_queue->attrib;
-+		pkt_queue = pxmitframe_queue->pkt;
-+
-+		_rtw_open_pktfile(pkt_queue, &pktfile_queue);
-+		_rtw_pktfile_read(&pktfile_queue, NULL, pattrib_queue->pkt_hdrlen);
-+
-+		#ifdef CONFIG_RTW_MESH
-+		if (MLME_IS_MESH(padapter)) {
-+			/* mDA(6), mSA(6), len(2), mctrl */
-+			_rtw_memcpy(pframe, pattrib_queue->mda, ETH_ALEN);
-+			pframe += ETH_ALEN;
-+			_rtw_memcpy(pframe, pattrib_queue->msa, ETH_ALEN);
-+			pframe += ETH_ALEN;
-+			len = (u16*)pframe;
-+			pframe += 2;
-+			rtw_mesh_tx_build_mctrl(padapter, pattrib_queue, pframe);
-+			pframe += XATTRIB_GET_MCTRL_LEN(pattrib_queue);
-+		} else
-+		#endif
-+		{
-+			/* 802.3 MAC Header DA(6)  SA(6)  Len(2)*/
-+			_rtw_memcpy(pframe, pattrib_queue->dst, ETH_ALEN);
-+			pframe += ETH_ALEN;
-+			_rtw_memcpy(pframe, pattrib_queue->src, ETH_ALEN);
-+			pframe += ETH_ALEN;
-+			len = (u16*)pframe;
-+			pframe += 2;
-+		}
-+
-+		llc_sz = rtw_put_snap(pframe, pattrib_queue->ether_type);
-+		pframe += llc_sz;
-+
-+		mem_sz = _rtw_pktfile_read(&pktfile_queue, pframe, pattrib_queue->pktlen);
-+		pframe += mem_sz;
-+
-+		*len = htons(XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz);
-+
-+		//calc padding
-+		padding = 4 - ((ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz) & (4-1));
-+		if(padding == 4)
-+			padding = 0;
-+
-+		//_rtw_memset(pframe,0xaa, padding);
-+		pframe += padding;
-+
-+		pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz + padding ;
-+	}
-+
-+	//2nd mpdu
-+
-+	pkt = pxmitframe->pkt;
-+	_rtw_open_pktfile(pkt, &pktfile);
-+	_rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen);
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(padapter)) {
-+		/* mDA(6), mSA(6), len(2), mctrl */
-+		_rtw_memcpy(pframe, pattrib->mda, ETH_ALEN);
-+		pframe += ETH_ALEN;
-+		_rtw_memcpy(pframe, pattrib->msa, ETH_ALEN);
-+		pframe += ETH_ALEN;
-+		len = (u16*)pframe;
-+		pframe += 2;
-+		rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe);
-+		pframe += XATTRIB_GET_MCTRL_LEN(pattrib);
-+	} else
-+#endif
-+	{
-+		/* 802.3 MAC Header  DA(6)  SA(6)  Len(2) */
-+		_rtw_memcpy(pframe, pattrib->dst, ETH_ALEN);
-+		pframe += ETH_ALEN;
-+		_rtw_memcpy(pframe, pattrib->src, ETH_ALEN);
-+		pframe += ETH_ALEN;
-+		len = (u16*)pframe;
-+		pframe += 2;
-+	}
-+
-+	llc_sz = rtw_put_snap(pframe, pattrib->ether_type);
-+	pframe += llc_sz;
-+
-+	mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen);
-+
-+	pframe += mem_sz;
-+
-+	*len = htons(XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz);
-+
-+	//the last ampdu has no padding
-+	padding = 0;
-+
-+	pattrib->nr_frags = 1;
-+
-+	pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz + padding +
-+		((pattrib->bswenc) ? pattrib->icv_len : 0) ;
-+
-+	if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
-+		_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
-+		pframe += pattrib->icv_len;
-+	}
-+
-+	if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) {
-+		RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n");
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	xmitframe_swencrypt(padapter, pxmitframe);
-+
-+	update_attrib_vcs_info(padapter, pxmitframe);
-+
-+exit:
-+	return res;
-+}
-+#endif /* CONFIG_TX_AMSDU */
-+
-+/*
-+
-+This sub-routine will perform all the following:
-+
-+1. remove 802.3 header.
-+2. create wlan_header, based on the info in pxmitframe
-+3. append sta's iv/ext-iv
-+4. append LLC
-+5. move frag chunk from pframe to pxmitframe->mem
-+6. apply sw-encrypt, if necessary.
-+
-+*/
-+s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe)
-+{
-+	struct pkt_file pktfile;
-+
-+	s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz;
-+
-+	SIZE_PTR addr;
-+
-+	u8 *pframe, *mem_start;
-+	u8 hw_hdr_offset;
-+
-+	/* struct sta_info		*psta; */
-+	/* struct sta_priv		*pstapriv = &padapter->stapriv; */
-+	/* struct mlme_priv	*pmlmepriv = &padapter->mlmepriv; */
-+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
-+
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+
-+	u8 *pbuf_start;
-+
-+	s32 bmcst = IS_MCAST(pattrib->ra);
-+	s32 res = _SUCCESS;
-+
-+
-+	/*
-+		if (pattrib->psta)
-+		{
-+			psta = pattrib->psta;
-+		} else
-+		{
-+			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
-+			psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
-+		}
-+
-+		if(psta==NULL)
-+		{
-+
-+			RTW_INFO("%s, psta==NUL\n", __func__);
-+			return _FAIL;
-+		}
-+
-+
-+		if(!(psta->state &WIFI_ASOC_STATE))
-+		{
-+			RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
-+			return _FAIL;
-+		}
-+	*/
-+	if (pxmitframe->buf_addr == NULL) {
-+		RTW_INFO("==> %s buf_addr==NULL\n", __FUNCTION__);
-+		return _FAIL;
-+	}
-+
-+	pbuf_start = pxmitframe->buf_addr;
-+
-+#ifdef CONFIG_USB_TX_AGGREGATION
-+	hw_hdr_offset =  TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);
-+#else
-+#ifdef CONFIG_TX_EARLY_MODE /* for SDIO && Tx Agg */
-+	hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE;
-+#else
-+	hw_hdr_offset = TXDESC_OFFSET;
-+#endif
-+#endif
-+
-+	mem_start = pbuf_start +	hw_hdr_offset;
-+
-+	if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) {
-+		RTW_INFO("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n");
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	_rtw_open_pktfile(pkt, &pktfile);
-+	_rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen);
-+
-+	frg_inx = 0;
-+	frg_len = pxmitpriv->frag_len - 4;/* 2346-4 = 2342 */
-+
-+	while (1) {
-+		llc_sz = 0;
-+
-+		mpdu_len = frg_len;
-+
-+		pframe = mem_start;
-+
-+		SetMFrag(mem_start);
-+
-+		pframe += pattrib->hdrlen;
-+		mpdu_len -= pattrib->hdrlen;
-+
-+		/* adding icv, if necessary... */
-+		if (pattrib->iv_len) {
-+#if 0
-+			/* if (check_fwstate(pmlmepriv, WIFI_MP_STATE)) */
-+			/*	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); */
-+			/* else */
-+			/*	psta = rtw_get_stainfo(pstapriv, pattrib->ra); */
-+
-+			if (psta != NULL) {
-+				switch (pattrib->encrypt) {
-+				case _WEP40_:
-+				case _WEP104_:
-+					WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
-+					break;
-+				case _TKIP_:
-+					if (bmcst)
-+						TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
-+					else
-+						TKIP_IV(pattrib->iv, psta->dot11txpn, 0);
-+					break;
-+				case _AES_:
-+					if (bmcst)
-+						AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx);
-+					else
-+						AES_IV(pattrib->iv, psta->dot11txpn, 0);
-+					break;
-+#ifdef CONFIG_WAPI_SUPPORT
-+				case _SMS4_:
-+					rtw_wapi_get_iv(padapter, pattrib->ra, pattrib->iv);
-+					break;
-+#endif
-+				}
-+			}
-+#endif
-+			_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
-+
-+
-+			pframe += pattrib->iv_len;
-+
-+			mpdu_len -= pattrib->iv_len;
-+		}
-+
-+		if (frg_inx == 0) {
-+			#ifdef CONFIG_RTW_MESH
-+			if (MLME_IS_MESH(padapter)) {
-+				rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe);
-+				pframe += XATTRIB_GET_MCTRL_LEN(pattrib);
-+				mpdu_len -= XATTRIB_GET_MCTRL_LEN(pattrib);
-+			}
-+			#endif
-+
-+			llc_sz = rtw_put_snap(pframe, pattrib->ether_type);
-+			pframe += llc_sz;
-+			mpdu_len -= llc_sz;
-+		}
-+
-+		if ((pattrib->icv_len > 0) && (pattrib->bswenc))
-+			mpdu_len -= pattrib->icv_len;
-+
-+
-+		if (bmcst) {
-+			/* don't do fragment to broadcat/multicast packets */
-+			mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen);
-+		} else
-+			mem_sz = _rtw_pktfile_read(&pktfile, pframe, mpdu_len);
-+
-+		pframe += mem_sz;
-+
-+		if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
-+			_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
-+			pframe += pattrib->icv_len;
-+		}
-+
-+		frg_inx++;
-+
-+		if (bmcst || (rtw_endofpktfile(&pktfile) == _TRUE)) {
-+			pattrib->nr_frags = frg_inx;
-+
-+			pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len +
-+				((pattrib->nr_frags == 1) ? (XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz) : 0) +
-+				((pattrib->bswenc) ? pattrib->icv_len : 0) + mem_sz;
-+
-+			ClearMFrag(mem_start);
-+
-+			break;
-+		}
-+
-+		addr = (SIZE_PTR)(pframe);
-+
-+		mem_start = (unsigned char *)RND4(addr) + hw_hdr_offset;
-+		_rtw_memcpy(mem_start, pbuf_start + hw_hdr_offset, pattrib->hdrlen);
-+
-+	}
-+
-+	if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) {
-+		RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n");
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	xmitframe_swencrypt(padapter, pxmitframe);
-+
-+	if (bmcst == _FALSE)
-+		update_attrib_vcs_info(padapter, pxmitframe);
-+	else
-+		pattrib->vcs_mode = NONE_VCS;
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
-+/*
-+ * CCMP encryption for unicast robust mgmt frame and broadcast group privicy action
-+ * BIP for broadcast robust mgmt frame
-+ */
-+s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe)
-+{
-+#define DBG_MGMT_XMIT_COALESEC_DUMP 0
-+#define DBG_MGMT_XMIT_BIP_DUMP 0
-+#define DBG_MGMT_XMIT_ENC_DUMP 0
-+
-+	struct pkt_file pktfile;
-+	s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz;
-+	SIZE_PTR addr;
-+	u8 *pframe, *mem_start = NULL, *tmp_buf = NULL;
-+	u8 hw_hdr_offset, subtype ;
-+	u8 category = 0xFF;
-+	struct sta_info		*psta = NULL;
-+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+	u8 *pbuf_start;
-+	s32 bmcst = IS_MCAST(pattrib->ra);
-+	s32 res = _FAIL;
-+	u8 *BIP_AAD = NULL;
-+	u8 *MGMT_body = NULL;
-+
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	u8 mme_cont[_MME_IE_LENGTH_ - 2];
-+	u8 mme_clen;
-+
-+	_irqL irqL;
-+	u32	ori_len;
-+	union pn48 *pn = NULL;
-+	enum security_type cipher = _NO_PRIVACY_;
-+	u8 kid;
-+
-+	if (pxmitframe->buf_addr == NULL) {
-+		RTW_WARN(FUNC_ADPT_FMT" pxmitframe->buf_addr\n"
-+			, FUNC_ADPT_ARG(padapter));
-+		return _FAIL;
-+	}
-+
-+	mem_start = pframe = (u8 *)(pxmitframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+	subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */
-+
-+	/* check if robust mgmt frame */
-+	if (subtype != WIFI_DEAUTH && subtype != WIFI_DISASSOC && subtype != WIFI_ACTION)
-+		return _SUCCESS;
-+	if (subtype == WIFI_ACTION) {
-+		category = *(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
-+		if (CATEGORY_IS_NON_ROBUST(category))
-+			return _SUCCESS;
-+	}
-+	if (!bmcst) {
-+		if (pattrib->psta)
-+			psta = pattrib->psta;
-+		else
-+			pattrib->psta = psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
-+		if (psta == NULL) {
-+			RTW_INFO(FUNC_ADPT_FMT" unicast sta == NULL\n", FUNC_ADPT_ARG(padapter));
-+			return _FAIL;
-+		}
-+		if (!(psta->flags & WLAN_STA_MFP)) {
-+			/* peer is not MFP capable, no need to encrypt */
-+			return _SUCCESS;
-+		}
-+		if (psta->bpairwise_key_installed != _TRUE) {
-+			RTW_INFO(FUNC_ADPT_FMT" PTK is not installed\n"
-+				, FUNC_ADPT_ARG(padapter));
-+			return _FAIL;
-+		}
-+	}
-+
-+	ori_len = BIP_AAD_SIZE + pattrib->pktlen + _MME_IE_LENGTH_;
-+	tmp_buf = BIP_AAD = rtw_zmalloc(ori_len);
-+	if (BIP_AAD == NULL)
-+		return _FAIL;
-+
-+	_enter_critical_bh(&padapter->security_key_mutex, &irqL);
-+
-+	if (bmcst) {
-+		if (subtype == WIFI_ACTION && CATEGORY_IS_GROUP_PRIVACY(category)) {
-+			/* broadcast group privacy action frame */
-+			#if DBG_MGMT_XMIT_COALESEC_DUMP
-+			RTW_INFO(FUNC_ADPT_FMT" broadcast gp action(%u)\n"
-+				, FUNC_ADPT_ARG(padapter), category);
-+			#endif
-+
-+			if (pattrib->psta)
-+				psta = pattrib->psta;
-+			else
-+				pattrib->psta = psta = rtw_get_bcmc_stainfo(padapter);
-+			if (psta == NULL) {
-+				RTW_INFO(FUNC_ADPT_FMT" broadcast sta == NULL\n"
-+					, FUNC_ADPT_ARG(padapter));
-+				goto xmitframe_coalesce_fail;
-+			}
-+			if (padapter->securitypriv.binstallGrpkey != _TRUE) {
-+				RTW_INFO(FUNC_ADPT_FMT" GTK is not installed\n"
-+					, FUNC_ADPT_ARG(padapter));
-+				goto xmitframe_coalesce_fail;
-+			}
-+
-+			pn = &psta->dot11txpn;
-+			cipher = padapter->securitypriv.dot118021XGrpPrivacy;
-+			kid = padapter->securitypriv.dot118021XGrpKeyid;
-+		} else {
-+			#ifdef CONFIG_IEEE80211W
-+			/* broadcast robust mgmt frame, using BIP */
-+			int frame_body_len;
-+			u8 mic[16];
-+
-+			/* IGTK key is not install ex: mesh MFP without IGTK */
-+			if (SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) != _TRUE)
-+				goto xmitframe_coalesce_success;
-+
-+			#if DBG_MGMT_XMIT_COALESEC_DUMP
-+			if (subtype == WIFI_DEAUTH)
-+				RTW_INFO(FUNC_ADPT_FMT" braodcast deauth\n", FUNC_ADPT_ARG(padapter));
-+			else if (subtype == WIFI_DISASSOC)
-+				RTW_INFO(FUNC_ADPT_FMT" braodcast disassoc\n", FUNC_ADPT_ARG(padapter));
-+			else if (subtype == WIFI_ACTION) {
-+				RTW_INFO(FUNC_ADPT_FMT" braodcast action(%u)\n"
-+					, FUNC_ADPT_ARG(padapter), category);
-+			}
-+			#endif
-+
-+			_rtw_memset(mme_cont, 0, _MME_IE_LENGTH_ - 2);
-+			mme_clen = padapter->securitypriv.dot11wCipher == _BIP_CMAC_128_ ? 16 : 24;
-+
-+			MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
-+			pframe += pattrib->pktlen;
-+
-+			/* octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0 */
-+			mme_cont[0] = padapter->securitypriv.dot11wBIPKeyid;
-+			/* increase PN and apply to packet */
-+			padapter->securitypriv.dot11wBIPtxpn.val++;
-+			RTW_PUT_LE64(&mme_cont[2], padapter->securitypriv.dot11wBIPtxpn.val);
-+
-+			/* add MME IE with MIC all zero, MME string doesn't include element id and length */
-+			pframe = rtw_set_ie(pframe, _MME_IE_ , mme_clen , mme_cont, &(pattrib->pktlen));
-+			pattrib->last_txcmdsz = pattrib->pktlen;
-+			/* total frame length - header length */
-+			frame_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+			/* conscruct AAD, copy frame control field */
-+			_rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2);
-+			ClearRetry(BIP_AAD);
-+			ClearPwrMgt(BIP_AAD);
-+			ClearMData(BIP_AAD);
-+			/* conscruct AAD, copy address 1 to address 3 */
-+			_rtw_memcpy(BIP_AAD + 2, GetAddr1Ptr((u8 *)pwlanhdr), 18);
-+			/* copy management fram body */
-+			_rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, MGMT_body, frame_body_len);
-+
-+			#if DBG_MGMT_XMIT_BIP_DUMP
-+			/* dump total packet include MME with zero MIC */
-+			{
-+				int i;
-+				printk("Total packet: ");
-+				for (i = 0; i < BIP_AAD_SIZE + frame_body_len; i++)
-+					printk(" %02x ", BIP_AAD[i]);
-+				printk("\n");
-+			}
-+			#endif
-+
-+			/* calculate mic */
-+			if (rtw_calculate_bip_mic(padapter->securitypriv.dot11wCipher,
-+				(u8 *)pwlanhdr, pattrib->pktlen,
-+				padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey, 
-+				BIP_AAD, (BIP_AAD_SIZE + frame_body_len), mic) == _FAIL)
-+				goto xmitframe_coalesce_fail;
-+
-+			#if DBG_MGMT_XMIT_BIP_DUMP
-+			/* dump calculated mic result */
-+			{
-+				int i;
-+				printk("Calculated mic result: ");
-+				for (i = 0; i < 16; i++)
-+					printk(" %02x ", mic[i]);
-+				printk("\n");
-+			}
-+			#endif
-+
-+			/* copy right BIP mic value, total is 128bits, we use the 0~63 bits */
-+			if (padapter->securitypriv.dot11wCipher == _BIP_CMAC_128_)
-+				_rtw_memcpy(pframe - 8, mic, 8);
-+			else
-+				_rtw_memcpy(pframe - 16, mic, 16);
-+
-+			#if DBG_MGMT_XMIT_BIP_DUMP
-+			/*dump all packet after mic ok */
-+			{
-+				int pp;
-+				printk("pattrib->pktlen = %d\n", pattrib->pktlen);
-+				for(pp=0;pp< pattrib->pktlen; pp++)
-+					printk(" %02x ", mem_start[pp]);
-+				printk("\n");
-+			}
-+			#endif
-+
-+			#endif /* CONFIG_IEEE80211W */
-+
-+			goto xmitframe_coalesce_success;
-+		}
-+	}
-+	else {
-+		/* unicast robust mgmt frame */
-+		#if DBG_MGMT_XMIT_COALESEC_DUMP
-+		if (subtype == WIFI_DEAUTH) {
-+			RTW_INFO(FUNC_ADPT_FMT" unicast deauth to "MAC_FMT"\n"
-+				, FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra));
-+		} else if (subtype == WIFI_DISASSOC) {
-+			RTW_INFO(FUNC_ADPT_FMT" unicast disassoc to "MAC_FMT"\n"
-+				, FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra));
-+		} else if (subtype == WIFI_ACTION) {
-+			RTW_INFO(FUNC_ADPT_FMT" unicast action(%u) to "MAC_FMT"\n"
-+				, FUNC_ADPT_ARG(padapter), category, MAC_ARG(pattrib->ra));
-+		}
-+		#endif
-+
-+		pn = &psta->dot11txpn;
-+		cipher = psta->dot118021XPrivacy;
-+		kid = 0;
-+
-+		_rtw_memcpy(pattrib->dot118021x_UncstKey.skey
-+			, psta->dot118021x_UncstKey.skey
-+			, (cipher & _SEC_TYPE_256_) ? 32 : 16);
-+
-+		/* To use wrong key */
-+		if (pattrib->key_type == IEEE80211W_WRONG_KEY) {
-+			RTW_INFO("use wrong key\n");
-+			pattrib->dot118021x_UncstKey.skey[0] = 0xff;
-+		}
-+	}
-+
-+	#if DBG_MGMT_XMIT_ENC_DUMP
-+	/* before encrypt dump the management packet content */
-+	{
-+		int i;
-+		printk("Management pkt: ");
-+		for(i=0; i<pattrib->pktlen; i++)
-+		printk(" %02x ", pframe[i]);
-+		printk("=======\n");
-+	}
-+	#endif
-+
-+	/* bakeup original management packet */
-+	_rtw_memcpy(tmp_buf, pframe, pattrib->pktlen);
-+	/* move to data portion */
-+	pframe += pattrib->hdrlen;
-+
-+	if (pattrib->key_type != IEEE80211W_NO_KEY) {
-+		pattrib->encrypt = cipher;
-+		pattrib->bswenc = _TRUE;
-+	}
-+
-+	/*
-+	* 802.11w encrypted management packet must be:
-+	* _AES_, _CCMP_256_, _GCMP_, _GCMP_256_
-+	*/
-+	switch (pattrib->encrypt) {
-+	case _AES_:
-+		pattrib->iv_len = 8;
-+		pattrib->icv_len = 8;
-+		AES_IV(pattrib->iv, (*pn), kid);
-+		break;
-+	case _CCMP_256_:
-+		pattrib->iv_len = 8;
-+		pattrib->icv_len = 16;
-+		AES_IV(pattrib->iv, (*pn), kid);
-+		break;
-+	case _GCMP_:
-+	case _GCMP_256_:
-+		pattrib->iv_len = 8;
-+		pattrib->icv_len = 16;
-+		GCMP_IV(pattrib->iv, (*pn), kid);
-+		break;
-+	default:
-+		goto xmitframe_coalesce_fail;
-+	}
-+
-+	/* insert iv header into management frame */
-+	_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
-+	pframe += pattrib->iv_len;
-+	/* copy mgmt data portion after CCMP header */
-+	_rtw_memcpy(pframe, tmp_buf + pattrib->hdrlen, pattrib->pktlen - pattrib->hdrlen);
-+	/* move pframe to end of mgmt pkt */
-+	pframe += pattrib->pktlen - pattrib->hdrlen;
-+	/* add 8 bytes CCMP IV header to length */
-+	pattrib->pktlen += pattrib->iv_len;
-+
-+	#if DBG_MGMT_XMIT_ENC_DUMP
-+	/* dump management packet include AES IV header */
-+	{
-+		int i;
-+		printk("Management pkt + IV: ");
-+		/* for(i=0; i<pattrib->pktlen; i++) */
-+
-+		printk("@@@@@@@@@@@@@\n");
-+	}
-+	#endif
-+
-+	if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
-+		_rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
-+		pframe += pattrib->icv_len;
-+	}
-+	/* add 8 bytes MIC */
-+	pattrib->pktlen += pattrib->icv_len;
-+	/* set final tx command size */
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	/* set protected bit must be beofre SW encrypt */
-+	SetPrivacy(mem_start);
-+
-+	#if DBG_MGMT_XMIT_ENC_DUMP
-+	/* dump management packet include AES header */
-+	{
-+		int i;
-+		printk("prepare to enc Management pkt + IV: ");
-+		for (i = 0; i < pattrib->pktlen; i++)
-+			printk(" %02x ", mem_start[i]);
-+		printk("@@@@@@@@@@@@@\n");
-+	}
-+	#endif
-+
-+	/* software encrypt */
-+	xmitframe_swencrypt(padapter, pxmitframe);
-+
-+xmitframe_coalesce_success:
-+	_exit_critical_bh(&padapter->security_key_mutex, &irqL);
-+	rtw_mfree(BIP_AAD, ori_len);
-+	return _SUCCESS;
-+
-+xmitframe_coalesce_fail:
-+	_exit_critical_bh(&padapter->security_key_mutex, &irqL);
-+	rtw_mfree(BIP_AAD, ori_len);
-+
-+	return _FAIL;
-+}
-+#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */
-+
-+/* Logical Link Control(LLC) SubNetwork Attachment Point(SNAP) header
-+ * IEEE LLC/SNAP header contains 8 octets
-+ * First 3 octets comprise the LLC portion
-+ * SNAP portion, 5 octets, is divided into two fields:
-+ *	Organizationally Unique Identifier(OUI), 3 octets,
-+ *	type, defined by that organization, 2 octets.
-+ */
-+s32 rtw_put_snap(u8 *data, u16 h_proto)
-+{
-+	struct ieee80211_snap_hdr *snap;
-+	u8 *oui;
-+
-+
-+	snap = (struct ieee80211_snap_hdr *)data;
-+	snap->dsap = 0xaa;
-+	snap->ssap = 0xaa;
-+	snap->ctrl = 0x03;
-+
-+	if (h_proto == 0x8137 || h_proto == 0x80f3)
-+		oui = P802_1H_OUI;
-+	else
-+		oui = RFC1042_OUI;
-+
-+	snap->oui[0] = oui[0];
-+	snap->oui[1] = oui[1];
-+	snap->oui[2] = oui[2];
-+
-+	*(u16 *)(data + SNAP_SIZE) = htons(h_proto);
-+
-+
-+	return SNAP_SIZE + sizeof(u16);
-+}
-+
-+void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len)
-+{
-+
-+	uint	protection;
-+	u8	*perp;
-+	sint	 erp_len;
-+	struct	xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	struct	registry_priv *pregistrypriv = &padapter->registrypriv;
-+
-+
-+	switch (pxmitpriv->vcs_setting) {
-+	case DISABLE_VCS:
-+		pxmitpriv->vcs = NONE_VCS;
-+		break;
-+
-+	case ENABLE_VCS:
-+		break;
-+
-+	case AUTO_VCS:
-+	default:
-+		perp = rtw_get_ie(ie, _ERPINFO_IE_, &erp_len, ie_len);
-+		if (perp == NULL)
-+			pxmitpriv->vcs = NONE_VCS;
-+		else {
-+			protection = (*(perp + 2)) & BIT(1);
-+			if (protection) {
-+				if (pregistrypriv->vcs_type == RTS_CTS)
-+					pxmitpriv->vcs = RTS_CTS;
-+				else
-+					pxmitpriv->vcs = CTS_TO_SELF;
-+			} else
-+				pxmitpriv->vcs = NONE_VCS;
-+		}
-+
-+		break;
-+
-+	}
-+
-+
-+}
-+
-+void rtw_count_tx_stats(PADAPTER padapter, struct xmit_frame *pxmitframe, int sz)
-+{
-+	struct sta_info *psta = NULL;
-+	struct stainfo_stats *pstats = NULL;
-+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	u8	pkt_num = 1;
-+
-+	if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) {
-+#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+		pkt_num = pxmitframe->agg_num;
-+#endif
-+		pmlmepriv->LinkDetectInfo.NumTxOkInPeriod += pkt_num;
-+
-+		pxmitpriv->tx_pkts += pkt_num;
-+
-+		pxmitpriv->tx_bytes += sz;
-+
-+		psta = pxmitframe->attrib.psta;
-+		if (psta) {
-+			pstats = &psta->sta_stats;
-+
-+			pstats->tx_pkts += pkt_num;
-+
-+			pstats->tx_bytes += sz;
-+			#if defined(CONFIG_CHECK_LEAVE_LPS) && defined(CONFIG_LPS_CHK_BY_TP)
-+			if (adapter_to_pwrctl(padapter)->lps_chk_by_tp)
-+				traffic_check_for_leave_lps_by_tp(padapter, _TRUE, psta);
-+			#endif /* CONFIG_LPS */
-+		}
-+
-+#ifdef CONFIG_CHECK_LEAVE_LPS
-+		/* traffic_check_for_leave_lps(padapter, _TRUE); */
-+#endif /* CONFIG_CHECK_LEAVE_LPS */
-+
-+	}
-+}
-+
-+static struct xmit_buf *__rtw_alloc_cmd_xmitbuf(struct xmit_priv *pxmitpriv,
-+		enum cmdbuf_type buf_type)
-+{
-+	struct xmit_buf *pxmitbuf =  NULL;
-+
-+
-+	pxmitbuf = &pxmitpriv->pcmd_xmitbuf[buf_type];
-+	if (pxmitbuf !=  NULL) {
-+		pxmitbuf->priv_data = NULL;
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+		pxmitbuf->len = 0;
-+		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
-+		pxmitbuf->agg_num = 0;
-+		pxmitbuf->pg_num = 0;
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+		pxmitbuf->len = 0;
-+#ifdef CONFIG_TRX_BD_ARCH
-+		/*pxmitbuf->buf_desc = NULL;*/
-+#else
-+		pxmitbuf->desc = NULL;
-+#endif
-+#endif
-+
-+		if (pxmitbuf->sctx) {
-+			RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__);
-+			rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);
-+		}
-+	} else
-+		RTW_INFO("%s fail, no xmitbuf available !!!\n", __func__);
-+
-+	return pxmitbuf;
-+}
-+
-+struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv,
-+		enum cmdbuf_type buf_type)
-+{
-+	struct xmit_frame		*pcmdframe;
-+	struct xmit_buf		*pxmitbuf;
-+
-+	pcmdframe = rtw_alloc_xmitframe(pxmitpriv, 0);
-+	if (pcmdframe == NULL) {
-+		RTW_INFO("%s, alloc xmitframe fail\n", __FUNCTION__);
-+		return NULL;
-+	}
-+
-+	pxmitbuf = __rtw_alloc_cmd_xmitbuf(pxmitpriv, buf_type);
-+	if (pxmitbuf == NULL) {
-+		RTW_INFO("%s, alloc xmitbuf fail\n", __FUNCTION__);
-+		rtw_free_xmitframe(pxmitpriv, pcmdframe);
-+		return NULL;
-+	}
-+
-+	pcmdframe->frame_tag = MGNT_FRAMETAG;
-+
-+	pcmdframe->pxmitbuf = pxmitbuf;
-+
-+	pcmdframe->buf_addr = pxmitbuf->pbuf;
-+
-+	/* initial memory to zero */
-+	_rtw_memset(pcmdframe->buf_addr, 0, MAX_CMDBUF_SZ);
-+
-+	pxmitbuf->priv_data = pcmdframe;
-+
-+	return pcmdframe;
-+
-+}
-+
-+struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv)
-+{
-+	_irqL irqL;
-+	struct xmit_buf *pxmitbuf =  NULL;
-+	_list *plist, *phead;
-+	_queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue;
-+
-+
-+	_enter_critical(&pfree_queue->lock, &irqL);
-+
-+	if (_rtw_queue_empty(pfree_queue) == _TRUE)
-+		pxmitbuf = NULL;
-+	else {
-+
-+		phead = get_list_head(pfree_queue);
-+
-+		plist = get_next(phead);
-+
-+		pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
-+
-+		rtw_list_delete(&(pxmitbuf->list));
-+	}
-+
-+	if (pxmitbuf !=  NULL) {
-+		pxmitpriv->free_xmit_extbuf_cnt--;
-+#ifdef DBG_XMIT_BUF_EXT
-+		RTW_INFO("DBG_XMIT_BUF_EXT ALLOC no=%d,  free_xmit_extbuf_cnt=%d\n", pxmitbuf->no, pxmitpriv->free_xmit_extbuf_cnt);
-+#endif
-+
-+
-+		pxmitbuf->priv_data = NULL;
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+		pxmitbuf->len = 0;
-+		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
-+		pxmitbuf->agg_num = 1;
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+		pxmitbuf->len = 0;
-+#ifdef CONFIG_TRX_BD_ARCH
-+		/*pxmitbuf->buf_desc = NULL;*/
-+#else
-+		pxmitbuf->desc = NULL;
-+#endif
-+#endif
-+
-+		if (pxmitbuf->sctx) {
-+			RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__);
-+			rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);
-+		}
-+
-+	}
-+
-+	_exit_critical(&pfree_queue->lock, &irqL);
-+
-+
-+	return pxmitbuf;
-+}
-+
-+s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
-+{
-+	_irqL irqL;
-+	_queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue;
-+
-+
-+	if (pxmitbuf == NULL)
-+		return _FAIL;
-+
-+	_enter_critical(&pfree_queue->lock, &irqL);
-+
-+	rtw_list_delete(&pxmitbuf->list);
-+
-+	rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_queue));
-+	pxmitpriv->free_xmit_extbuf_cnt++;
-+#ifdef DBG_XMIT_BUF_EXT
-+	RTW_INFO("DBG_XMIT_BUF_EXT FREE no=%d, free_xmit_extbuf_cnt=%d\n", pxmitbuf->no , pxmitpriv->free_xmit_extbuf_cnt);
-+#endif
-+
-+	_exit_critical(&pfree_queue->lock, &irqL);
-+
-+
-+	return _SUCCESS;
-+}
-+
-+struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv)
-+{
-+	_irqL irqL;
-+	struct xmit_buf *pxmitbuf =  NULL;
-+	_list *plist, *phead;
-+	_queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;
-+
-+
-+	/* RTW_INFO("+rtw_alloc_xmitbuf\n"); */
-+
-+	_enter_critical(&pfree_xmitbuf_queue->lock, &irqL);
-+
-+	if (_rtw_queue_empty(pfree_xmitbuf_queue) == _TRUE)
-+		pxmitbuf = NULL;
-+	else {
-+
-+		phead = get_list_head(pfree_xmitbuf_queue);
-+
-+		plist = get_next(phead);
-+
-+		pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
-+
-+		rtw_list_delete(&(pxmitbuf->list));
-+	}
-+
-+	if (pxmitbuf !=  NULL) {
-+		pxmitpriv->free_xmitbuf_cnt--;
-+#ifdef DBG_XMIT_BUF
-+		RTW_INFO("DBG_XMIT_BUF ALLOC no=%d,  free_xmitbuf_cnt=%d\n", pxmitbuf->no, pxmitpriv->free_xmitbuf_cnt);
-+#endif
-+		/* RTW_INFO("alloc, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); */
-+
-+		pxmitbuf->priv_data = NULL;
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+		pxmitbuf->len = 0;
-+		pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
-+		pxmitbuf->agg_num = 0;
-+		pxmitbuf->pg_num = 0;
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+		pxmitbuf->len = 0;
-+#ifdef CONFIG_TRX_BD_ARCH
-+		/*pxmitbuf->buf_desc = NULL;*/
-+#else
-+		pxmitbuf->desc = NULL;
-+#endif
-+#endif
-+
-+		if (pxmitbuf->sctx) {
-+			RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__);
-+			rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC);
-+		}
-+	}
-+#ifdef DBG_XMIT_BUF
-+	else
-+		RTW_INFO("DBG_XMIT_BUF rtw_alloc_xmitbuf return NULL\n");
-+#endif
-+
-+	_exit_critical(&pfree_xmitbuf_queue->lock, &irqL);
-+
-+
-+	return pxmitbuf;
-+}
-+
-+s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
-+{
-+	_irqL irqL;
-+	_queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;
-+
-+
-+	/* RTW_INFO("+rtw_free_xmitbuf\n"); */
-+
-+	if (pxmitbuf == NULL)
-+		return _FAIL;
-+
-+	if (pxmitbuf->sctx) {
-+		RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__);
-+		rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_FREE);
-+	}
-+
-+	if (pxmitbuf->buf_tag == XMITBUF_CMD) {
-+	} else if (pxmitbuf->buf_tag == XMITBUF_MGNT)
-+		rtw_free_xmitbuf_ext(pxmitpriv, pxmitbuf);
-+	else {
-+		_enter_critical(&pfree_xmitbuf_queue->lock, &irqL);
-+
-+		rtw_list_delete(&pxmitbuf->list);
-+
-+		rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_xmitbuf_queue));
-+
-+		pxmitpriv->free_xmitbuf_cnt++;
-+		/* RTW_INFO("FREE, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); */
-+#ifdef DBG_XMIT_BUF
-+		RTW_INFO("DBG_XMIT_BUF FREE no=%d, free_xmitbuf_cnt=%d\n", pxmitbuf->no , pxmitpriv->free_xmitbuf_cnt);
-+#endif
-+		_exit_critical(&pfree_xmitbuf_queue->lock, &irqL);
-+	}
-+
-+
-+	return _SUCCESS;
-+}
-+
-+void rtw_init_xmitframe(struct xmit_frame *pxframe)
-+{
-+	if (pxframe !=  NULL) { /* default value setting */
-+		pxframe->buf_addr = NULL;
-+		pxframe->pxmitbuf = NULL;
-+
-+		_rtw_memset(&pxframe->attrib, 0, sizeof(struct pkt_attrib));
-+		/* pxframe->attrib.psta = NULL; */
-+
-+		pxframe->frame_tag = DATA_FRAMETAG;
-+
-+#ifdef CONFIG_USB_HCI
-+		pxframe->pkt = NULL;
-+#ifdef USB_PACKET_OFFSET_SZ
-+		pxframe->pkt_offset = (PACKET_OFFSET_SZ / 8);
-+#else
-+		pxframe->pkt_offset = 1;/* default use pkt_offset to fill tx desc */
-+#endif
-+
-+#ifdef CONFIG_USB_TX_AGGREGATION
-+		pxframe->agg_num = 1;
-+#endif
-+
-+#endif /* #ifdef CONFIG_USB_HCI */
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+		pxframe->pg_num = 1;
-+		pxframe->agg_num = 1;
-+#endif
-+
-+#ifdef CONFIG_XMIT_ACK
-+		pxframe->ack_report = 0;
-+#endif
-+
-+	}
-+}
-+
-+/*
-+Calling context:
-+1. OS_TXENTRY
-+2. RXENTRY (rx_thread or RX_ISR/RX_CallBack)
-+
-+If we turn on USE_RXTHREAD, then, no need for critical section.
-+Otherwise, we must use _enter/_exit critical to protect free_xmit_queue...
-+
-+Must be very very cautious...
-+
-+*/
-+struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv, u16 os_qid)
-+{
-+	/*
-+		Please remember to use all the osdep_service api,
-+		and lock/unlock or _enter/_exit critical to protect
-+		pfree_xmit_queue
-+	*/
-+
-+	_irqL irqL;
-+	struct xmit_frame *pxframe = NULL;
-+	_list *plist, *phead;
-+	_queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue;
-+
-+	_enter_critical_bh(&pfree_xmit_queue->lock, &irqL);
-+
-+	if (_rtw_queue_empty(pfree_xmit_queue) == _TRUE) {
-+		pxframe =  NULL;
-+	} else {
-+		phead = get_list_head(pfree_xmit_queue);
-+
-+		plist = get_next(phead);
-+
-+		pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
-+
-+		rtw_list_delete(&(pxframe->list));
-+		pxmitpriv->free_xmitframe_cnt--;
-+		pxframe->os_qid = os_qid;
-+	}
-+
-+	_exit_critical_bh(&pfree_xmit_queue->lock, &irqL);
-+
-+	if (pxframe)
-+		rtw_os_check_stop_queue(pxmitpriv->adapter, os_qid);
-+
-+	rtw_init_xmitframe(pxframe);
-+
-+
-+	return pxframe;
-+}
-+
-+struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv)
-+{
-+	_irqL irqL;
-+	struct xmit_frame *pxframe = NULL;
-+	_list *plist, *phead;
-+	_queue *queue = &pxmitpriv->free_xframe_ext_queue;
-+
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+
-+	if (_rtw_queue_empty(queue) == _TRUE) {
-+		pxframe =  NULL;
-+	} else {
-+		phead = get_list_head(queue);
-+		plist = get_next(phead);
-+		pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
-+
-+		rtw_list_delete(&(pxframe->list));
-+		pxmitpriv->free_xframe_ext_cnt--;
-+	}
-+
-+	_exit_critical_bh(&queue->lock, &irqL);
-+
-+	rtw_init_xmitframe(pxframe);
-+
-+
-+	return pxframe;
-+}
-+
-+struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv)
-+{
-+	struct xmit_frame *pxframe = NULL;
-+	u8 *alloc_addr;
-+
-+	alloc_addr = rtw_zmalloc(sizeof(struct xmit_frame) + 4);
-+
-+	if (alloc_addr == NULL)
-+		goto exit;
-+
-+	pxframe = (struct xmit_frame *)N_BYTE_ALIGMENT((SIZE_PTR)(alloc_addr), 4);
-+	pxframe->alloc_addr = alloc_addr;
-+
-+	pxframe->padapter = pxmitpriv->adapter;
-+	pxframe->frame_tag = NULL_FRAMETAG;
-+
-+	pxframe->pkt = NULL;
-+
-+	pxframe->buf_addr = NULL;
-+	pxframe->pxmitbuf = NULL;
-+
-+	rtw_init_xmitframe(pxframe);
-+
-+	RTW_INFO("################## %s ##################\n", __func__);
-+
-+exit:
-+	return pxframe;
-+}
-+
-+s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe)
-+{
-+	_irqL irqL;
-+	_queue *queue = NULL;
-+	_adapter *padapter = pxmitpriv->adapter;
-+	_pkt *pndis_pkt = NULL;
-+
-+
-+	if (pxmitframe == NULL) {
-+		goto exit;
-+	}
-+
-+	if (pxmitframe->pkt) {
-+		pndis_pkt = pxmitframe->pkt;
-+		pxmitframe->pkt = NULL;
-+	}
-+
-+	if (pxmitframe->alloc_addr) {
-+		RTW_INFO("################## %s with alloc_addr ##################\n", __func__);
-+		rtw_mfree(pxmitframe->alloc_addr, sizeof(struct xmit_frame) + 4);
-+		goto check_pkt_complete;
-+	}
-+
-+	if (pxmitframe->ext_tag == 0)
-+		queue = &pxmitpriv->free_xmit_queue;
-+	else if (pxmitframe->ext_tag == 1)
-+		queue = &pxmitpriv->free_xframe_ext_queue;
-+	else
-+		rtw_warn_on(1);
-+
-+	_enter_critical_bh(&queue->lock, &irqL);
-+
-+	rtw_list_delete(&pxmitframe->list);
-+	rtw_list_insert_tail(&pxmitframe->list, get_list_head(queue));
-+	if (pxmitframe->ext_tag == 0) {
-+		pxmitpriv->free_xmitframe_cnt++;
-+	} else if (pxmitframe->ext_tag == 1) {
-+		pxmitpriv->free_xframe_ext_cnt++;
-+	} else {
-+	}
-+
-+	_exit_critical_bh(&queue->lock, &irqL);
-+
-+	if (queue == &pxmitpriv->free_xmit_queue)
-+		rtw_os_check_wakup_queue(padapter, pxmitframe->os_qid);
-+
-+check_pkt_complete:
-+
-+	if (pndis_pkt)
-+		rtw_os_pkt_complete(padapter, pndis_pkt);
-+
-+exit:
-+
-+
-+	return _SUCCESS;
-+}
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+void rtw_free_mgmt_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *mgmt_queue)
-+{
-+	_irqL irqL;
-+	_list	*plist, *phead;
-+	struct xmit_frame *pxmitframe;
-+
-+	_enter_critical_bh(&(mgmt_queue->lock), &irqL);
-+
-+	phead = get_list_head(mgmt_queue);
-+	plist = get_next(phead);
-+
-+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+
-+		pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
-+		plist = get_next(plist);
-+
-+		#ifdef DBG_MGMT_QUEUE
-+		RTW_INFO("%s seq_num = %u\n", __func__, pxmitframe->attrib.seqnum);
-+		#endif
-+
-+		rtw_free_xmitbuf_ext(pxmitpriv, pxmitframe->pxmitbuf);
-+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
-+	}
-+	_exit_critical_bh(&(mgmt_queue->lock), &irqL);
-+}
-+
-+u8 rtw_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
-+{
-+	struct sta_info *psta;
-+	struct tx_servq *ptxservq;
-+	struct pkt_attrib *pattrib = &(pxmitframe->attrib);
-+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
-+	struct hw_xmit *phwxmits = pxmitpriv->hwxmits;
-+	u8 mgmt_idx = pxmitpriv->hwxmit_entry - 1;
-+
-+	DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class);
-+
-+	psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
-+	if (pattrib->psta != psta) {
-+		DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_sta);
-+		RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
-+		return _FAIL;
-+	}
-+
-+	if (psta == NULL) {
-+		DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_nosta);
-+		RTW_INFO("rtw_xmit_classifier: psta == NULL\n");
-+		return _FAIL;
-+	}
-+
-+	if (!(psta->state & WIFI_ASOC_STATE)) {
-+		DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_fwlink);
-+		RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
-+		return _FAIL;
-+	}
-+
-+	ptxservq = &(psta->sta_xmitpriv.mgmt_q);
-+
-+	if (rtw_is_list_empty(&ptxservq->tx_pending))
-+		rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmits[mgmt_idx].sta_queue));
-+
-+	rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptxservq->sta_pending));
-+	ptxservq->qcnt++;
-+	phwxmits[mgmt_idx].accnt++;
-+
-+	return _SUCCESS;
-+}
-+#endif
-+
-+void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue)
-+{
-+	_irqL irqL;
-+	_list	*plist, *phead;
-+	struct	xmit_frame	*pxmitframe;
-+
-+
-+	_enter_critical_bh(&(pframequeue->lock), &irqL);
-+
-+	phead = get_list_head(pframequeue);
-+	plist = get_next(phead);
-+
-+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+
-+		pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
-+
-+		plist = get_next(plist);
-+
-+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
-+
-+	}
-+	_exit_critical_bh(&(pframequeue->lock), &irqL);
-+
-+}
-+
-+s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
-+{
-+	DBG_COUNTER(padapter->tx_logs.core_tx_enqueue);
-+	if (rtw_xmit_classifier(padapter, pxmitframe) == _FAIL) {
-+		/*		pxmitframe->pkt = NULL; */
-+		return _FAIL;
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+static struct xmit_frame *dequeue_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue)
-+{
-+	_list	*xmitframe_plist, *xmitframe_phead;
-+	struct	xmit_frame	*pxmitframe = NULL;
-+
-+	xmitframe_phead = get_list_head(pframe_queue);
-+	xmitframe_plist = get_next(xmitframe_phead);
-+
-+	while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
-+		pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
-+
-+		/* xmitframe_plist = get_next(xmitframe_plist); */
-+
-+		/*#ifdef RTK_DMP_PLATFORM
-+		#ifdef CONFIG_USB_TX_AGGREGATION
-+				if((ptxservq->qcnt>0) && (ptxservq->qcnt<=2))
-+				{
-+					pxmitframe = NULL;
-+
-+					tasklet_schedule(&pxmitpriv->xmit_tasklet);
-+
-+					break;
-+				}
-+		#endif
-+		#endif*/
-+		rtw_list_delete(&pxmitframe->list);
-+
-+		ptxservq->qcnt--;
-+
-+		/* rtw_list_insert_tail(&pxmitframe->list, &phwxmit->pending); */
-+
-+		/* ptxservq->qcnt--; */
-+
-+		break;
-+
-+		/* pxmitframe = NULL; */
-+
-+	}
-+
-+	return pxmitframe;
-+}
-+
-+static struct xmit_frame *get_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue)
-+{
-+	_list	*xmitframe_plist, *xmitframe_phead;
-+	struct	xmit_frame	*pxmitframe = NULL;
-+
-+	xmitframe_phead = get_list_head(pframe_queue);
-+	xmitframe_plist = get_next(xmitframe_phead);
-+
-+	while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
-+		pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
-+		break;
-+	}
-+
-+	return pxmitframe;
-+}
-+
-+struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame)
-+{
-+	_irqL irqL0;
-+	_list *sta_plist, *sta_phead;
-+	struct hw_xmit *phwxmit_i = pxmitpriv->hwxmits;
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	/* This function gets xmit_frame from AC queue. */
-+	/* When mgmt queue is used, AC queue index is (hwxmit_entry - 1) */
-+	sint entry = pxmitpriv->hwxmit_entry - 1;
-+#else
-+	sint entry = pxmitpriv->hwxmit_entry;
-+#endif
-+	struct hw_xmit *phwxmit;
-+	struct tx_servq *ptxservq = NULL;
-+	_queue *pframe_queue = NULL;
-+	struct xmit_frame *pxmitframe = NULL;
-+	_adapter *padapter = pxmitpriv->adapter;
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+	int i, inx[4];
-+
-+	inx[0] = 0;
-+	inx[1] = 1;
-+	inx[2] = 2;
-+	inx[3] = 3;
-+
-+	*num_frame = 0;
-+
-+	/*No amsdu when wifi_spec on*/
-+	if (pregpriv->wifi_spec == 1) {
-+		return NULL;
-+	}
-+
-+	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
-+
-+	for (i = 0; i < entry; i++) {
-+		phwxmit = phwxmit_i + inx[i];
-+
-+		sta_phead = get_list_head(phwxmit->sta_queue);
-+		sta_plist = get_next(sta_phead);
-+
-+		while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) {
-+
-+			ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending);
-+			pframe_queue = &ptxservq->sta_pending;
-+
-+			if(ptxservq->qcnt)
-+			{
-+				*num_frame = ptxservq->qcnt;
-+				pxmitframe = get_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue);
-+				goto exit;
-+			}
-+			sta_plist = get_next(sta_plist);
-+		}
-+	}
-+
-+exit:
-+
-+	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
-+
-+	return pxmitframe;
-+}
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+struct xmit_frame *rtw_dequeue_mgmt_xframe(struct xmit_priv *pxmitpriv)
-+{
-+	_irqL irqL0;
-+	_list *sta_plist, *sta_phead;
-+	struct hw_xmit *mgmt_hwxmit;
-+	struct tx_servq *ptxservq = NULL;
-+	_queue *pframe_queue = NULL;
-+	struct xmit_frame *pxmitframe = NULL;
-+	u8 mgmt_entry = pxmitpriv->hwxmit_entry - 1;
-+
-+	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
-+
-+	/* management queue */
-+	mgmt_hwxmit = (pxmitpriv->hwxmits) + mgmt_entry;
-+
-+	sta_phead = get_list_head(mgmt_hwxmit->sta_queue);
-+	sta_plist = get_next(sta_phead);
-+
-+	while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) {
-+
-+		ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending);
-+
-+		pframe_queue = &ptxservq->sta_pending;
-+
-+		pxmitframe = dequeue_one_xmitframe(pxmitpriv, mgmt_hwxmit, ptxservq, pframe_queue);
-+
-+		#ifdef DBG_MGMT_QUEUE
-+		RTW_INFO("%s dequeue mgmt frame (seq_num = %u) to TX\n", __func__, pxmitframe->attrib.seqnum);
-+		#endif
-+
-+		if (pxmitframe) {
-+			mgmt_hwxmit->accnt--;
-+
-+			/* Remove sta node when there is no pending packets. */
-+			if (_rtw_queue_empty(pframe_queue)) /* must be done after get_next and before break */
-+				rtw_list_delete(&ptxservq->tx_pending);
-+
-+			goto exit;
-+		}
-+		sta_plist = get_next(sta_plist);
-+	}
-+exit:
-+	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
-+
-+	return pxmitframe;
-+}
-+#endif
-+
-+struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry)
-+{
-+	_irqL irqL0;
-+	_list *sta_plist, *sta_phead;
-+	struct hw_xmit *phwxmit;
-+	struct tx_servq *ptxservq = NULL;
-+	_queue *pframe_queue = NULL;
-+	struct xmit_frame *pxmitframe = NULL;
-+	_adapter *padapter = pxmitpriv->adapter;
-+	struct registry_priv *pregpriv = &padapter->registrypriv;
-+	int i, inx[4];
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	/* This function gets xmit_frame from AC queue. */
-+	/* When mgmt queue is used, AC queue index is (hwxmit_entry - 1) */
-+	entry--;
-+#endif
-+	inx[0] = 0;
-+	inx[1] = 1;
-+	inx[2] = 2;
-+	inx[3] = 3;
-+
-+	if (pregpriv->wifi_spec == 1) {
-+		int j;
-+#if 0
-+		if (flags < XMIT_QUEUE_ENTRY) {
-+			/* priority exchange according to the completed xmitbuf flags. */
-+			inx[flags] = 0;
-+			inx[0] = flags;
-+		}
-+#endif
-+
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI)
-+		for (j = 0; j < 4; j++)
-+			inx[j] = pxmitpriv->wmm_para_seq[j];
-+#endif
-+	}
-+
-+	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
-+
-+	for (i = 0; i < entry; i++) {
-+		phwxmit = phwxmit_i + inx[i];
-+
-+		/* _enter_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */
-+
-+		sta_phead = get_list_head(phwxmit->sta_queue);
-+		sta_plist = get_next(sta_phead);
-+
-+		while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) {
-+
-+			ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending);
-+
-+			pframe_queue = &ptxservq->sta_pending;
-+
-+			pxmitframe = dequeue_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue);
-+
-+			if (pxmitframe) {
-+				phwxmit->accnt--;
-+
-+				/* Remove sta node when there is no pending packets. */
-+				if (_rtw_queue_empty(pframe_queue)) /* must be done after get_next and before break */
-+					rtw_list_delete(&ptxservq->tx_pending);
-+
-+				/* _exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */
-+
-+				goto exit;
-+			}
-+
-+			sta_plist = get_next(sta_plist);
-+
-+		}
-+
-+		/* _exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */
-+
-+	}
-+
-+exit:
-+
-+	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
-+
-+	return pxmitframe;
-+}
-+
-+struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac)
-+{
-+	struct tx_servq *ptxservq = NULL;
-+
-+
-+	switch (up) {
-+	case 1:
-+	case 2:
-+		ptxservq = &(psta->sta_xmitpriv.bk_q);
-+		*(ac) = 3;
-+		break;
-+
-+	case 4:
-+	case 5:
-+		ptxservq = &(psta->sta_xmitpriv.vi_q);
-+		*(ac) = 1;
-+		break;
-+
-+	case 6:
-+	case 7:
-+		ptxservq = &(psta->sta_xmitpriv.vo_q);
-+		*(ac) = 0;
-+		break;
-+
-+	case 0:
-+	case 3:
-+	default:
-+		ptxservq = &(psta->sta_xmitpriv.be_q);
-+		*(ac) = 2;
-+		break;
-+
-+	}
-+
-+
-+	return ptxservq;
-+}
-+
-+/*
-+ * Will enqueue pxmitframe to the proper queue,
-+ * and indicate it to xx_pending list.....
-+ */
-+s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe)
-+{
-+	/* _irqL irqL0; */
-+	u8	ac_index;
-+	struct sta_info	*psta;
-+	struct tx_servq	*ptxservq;
-+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
-+	struct hw_xmit	*phwxmits =  padapter->xmitpriv.hwxmits;
-+	sint res = _SUCCESS;
-+
-+
-+	DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class);
-+
-+	/*
-+		if (pattrib->psta) {
-+			psta = pattrib->psta;
-+		} else {
-+			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
-+			psta = rtw_get_stainfo(pstapriv, pattrib->ra);
-+		}
-+	*/
-+
-+	psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
-+	if (pattrib->psta != psta) {
-+		DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_sta);
-+		RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
-+		return _FAIL;
-+	}
-+
-+	if (psta == NULL) {
-+		DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_nosta);
-+		res = _FAIL;
-+		RTW_INFO("rtw_xmit_classifier: psta == NULL\n");
-+		goto exit;
-+	}
-+
-+	if (!(psta->state & WIFI_ASOC_STATE)) {
-+		DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_fwlink);
-+		RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
-+		return _FAIL;
-+	}
-+
-+	ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index));
-+
-+	/* _enter_critical(&pstapending->lock, &irqL0); */
-+
-+	if (rtw_is_list_empty(&ptxservq->tx_pending))
-+		rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmits[ac_index].sta_queue));
-+
-+	/* _enter_critical(&ptxservq->sta_pending.lock, &irqL1); */
-+
-+	rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptxservq->sta_pending));
-+	ptxservq->qcnt++;
-+	phwxmits[ac_index].accnt++;
-+
-+	/* _exit_critical(&ptxservq->sta_pending.lock, &irqL1); */
-+
-+	/* _exit_critical(&pstapending->lock, &irqL0); */
-+
-+exit:
-+
-+
-+	return res;
-+}
-+
-+void rtw_alloc_hwxmits(_adapter *padapter)
-+{
-+	struct hw_xmit *hwxmits;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+
-+	pxmitpriv->hwxmit_entry = HWXMIT_ENTRY;
-+
-+	pxmitpriv->hwxmits = NULL;
-+
-+	pxmitpriv->hwxmits = (struct hw_xmit *)rtw_zmalloc(sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry);
-+
-+	if (pxmitpriv->hwxmits == NULL) {
-+		RTW_INFO("alloc hwxmits fail!...\n");
-+		return;
-+	}
-+
-+	hwxmits = pxmitpriv->hwxmits;
-+
-+	rtw_warn_on(pxmitpriv->hwxmit_entry < 4);
-+
-+	/* pxmitpriv->vo_txqueue.head = 0; */
-+	/* hwxmits[0] .phwtxqueue = &pxmitpriv->vo_txqueue; */
-+	hwxmits[0].sta_queue = &pxmitpriv->vo_pending;
-+
-+	/* pxmitpriv->vi_txqueue.head = 0; */
-+	/* hwxmits[1] .phwtxqueue = &pxmitpriv->vi_txqueue; */
-+	hwxmits[1].sta_queue = &pxmitpriv->vi_pending;
-+
-+	/* pxmitpriv->be_txqueue.head = 0; */
-+	/* hwxmits[2] .phwtxqueue = &pxmitpriv->be_txqueue; */
-+	hwxmits[2].sta_queue = &pxmitpriv->be_pending;
-+
-+	/* pxmitpriv->bk_txqueue.head = 0; */
-+	/* hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; */
-+	hwxmits[3].sta_queue = &pxmitpriv->bk_pending;
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	hwxmits[4].sta_queue = &pxmitpriv->mgmt_pending;
-+#endif
-+
-+}
-+
-+void rtw_free_hwxmits(_adapter *padapter)
-+{
-+	struct hw_xmit *hwxmits;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+
-+	hwxmits = pxmitpriv->hwxmits;
-+	if (hwxmits)
-+		rtw_mfree((u8 *)hwxmits, (sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry));
-+}
-+
-+void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry)
-+{
-+	sint i;
-+	for (i = 0; i < entry; i++, phwxmit++) {
-+		/* _rtw_spinlock_init(&phwxmit->xmit_lock); */
-+		/* _rtw_init_listhead(&phwxmit->pending);		 */
-+		/* phwxmit->txcmdcnt = 0; */
-+		phwxmit->accnt = 0;
-+	}
-+}
-+
-+#ifdef CONFIG_BR_EXT
-+int rtw_br_client_tx(_adapter *padapter, struct sk_buff **pskb)
-+{
-+	struct sk_buff *skb = *pskb;
-+	_irqL irqL;
-+	/* if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) */
-+	{
-+		void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb);
-+		int res, is_vlan_tag = 0, i, do_nat25 = 1;
-+		unsigned short vlan_hdr = 0;
-+		void *br_port = NULL;
-+
-+		/* mac_clone_handle_frame(priv, skb); */
-+
-+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
-+		br_port = padapter->pnetdev->br_port;
-+#else   /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
-+		rcu_read_lock();
-+		br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
-+		rcu_read_unlock();
-+#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
-+		_enter_critical_bh(&padapter->br_ext_lock, &irqL);
-+		if (!(skb->data[0] & 1) &&
-+		    br_port &&
-+		    memcmp(skb->data + MACADDRLEN, padapter->br_mac, MACADDRLEN) &&
-+		    *((unsigned short *)(skb->data + MACADDRLEN * 2)) != __constant_htons(ETH_P_8021Q) &&
-+		    *((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP) &&
-+		    !memcmp(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN) && padapter->scdb_entry) {
-+			memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
-+			padapter->scdb_entry->ageing_timer = jiffies;
-+			_exit_critical_bh(&padapter->br_ext_lock, &irqL);
-+		} else
-+			/* if (!priv->pmib->ethBrExtInfo.nat25_disable)		 */
-+		{
-+			/*			if (priv->dev->br_port &&
-+			 *				 !memcmp(skb->data+MACADDRLEN, priv->br_mac, MACADDRLEN)) { */
-+#if 1
-+			if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_8021Q)) {
-+				is_vlan_tag = 1;
-+				vlan_hdr = *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2));
-+				for (i = 0; i < 6; i++)
-+					*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + MACADDRLEN * 2 - 2 - i * 2));
-+				skb_pull(skb, 4);
-+			}
-+			/* if SA == br_mac && skb== IP  => copy SIP to br_ip ?? why */
-+			if (!memcmp(skb->data + MACADDRLEN, padapter->br_mac, MACADDRLEN) &&
-+			    (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP)))
-+				memcpy(padapter->br_ip, skb->data + WLAN_ETHHDR_LEN + 12, 4);
-+
-+			if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP)) {
-+				if (memcmp(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN)) {
-+					void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, unsigned char *ipAddr);
-+
-+					padapter->scdb_entry = (struct nat25_network_db_entry *)scdb_findEntry(padapter,
-+						skb->data + MACADDRLEN, skb->data + WLAN_ETHHDR_LEN + 12);
-+					if (padapter->scdb_entry != NULL) {
-+						memcpy(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN);
-+						memcpy(padapter->scdb_ip, skb->data + WLAN_ETHHDR_LEN + 12, 4);
-+						padapter->scdb_entry->ageing_timer = jiffies;
-+						do_nat25 = 0;
-+					}
-+				} else {
-+					if (padapter->scdb_entry) {
-+						padapter->scdb_entry->ageing_timer = jiffies;
-+						do_nat25 = 0;
-+					} else {
-+						memset(padapter->scdb_mac, 0, MACADDRLEN);
-+						memset(padapter->scdb_ip, 0, 4);
-+					}
-+				}
-+			}
-+			_exit_critical_bh(&padapter->br_ext_lock, &irqL);
-+#endif /* 1 */
-+			if (do_nat25) {
-+				int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method);
-+				if (nat25_db_handle(padapter, skb, NAT25_CHECK) == 0) {
-+					struct sk_buff *newskb;
-+
-+					if (is_vlan_tag) {
-+						skb_push(skb, 4);
-+						for (i = 0; i < 6; i++)
-+							*((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2));
-+						*((unsigned short *)(skb->data + MACADDRLEN * 2)) = __constant_htons(ETH_P_8021Q);
-+						*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)) = vlan_hdr;
-+					}
-+
-+					newskb = rtw_skb_copy(skb);
-+					if (newskb == NULL) {
-+						/* priv->ext_stats.tx_drops++; */
-+						DEBUG_ERR("TX DROP: rtw_skb_copy fail!\n");
-+						/* goto stop_proc; */
-+						return -1;
-+					}
-+					rtw_skb_free(skb);
-+
-+					*pskb = skb = newskb;
-+					if (is_vlan_tag) {
-+						vlan_hdr = *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2));
-+						for (i = 0; i < 6; i++)
-+							*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + MACADDRLEN * 2 - 2 - i * 2));
-+						skb_pull(skb, 4);
-+					}
-+				}
-+
-+				if (skb_is_nonlinear(skb))
-+					DEBUG_ERR("%s(): skb_is_nonlinear!!\n", __FUNCTION__);
-+
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
-+				res = skb_linearize(skb, GFP_ATOMIC);
-+#else	/* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) */
-+				res = skb_linearize(skb);
-+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) */
-+				if (res < 0) {
-+					DEBUG_ERR("TX DROP: skb_linearize fail!\n");
-+					/* goto free_and_stop; */
-+					return -1;
-+				}
-+
-+				res = nat25_db_handle(padapter, skb, NAT25_INSERT);
-+				if (res < 0) {
-+					if (res == -2) {
-+						/* priv->ext_stats.tx_drops++; */
-+						DEBUG_ERR("TX DROP: nat25_db_handle fail!\n");
-+						/* goto free_and_stop; */
-+						return -1;
-+
-+					}
-+					/* we just print warning message and let it go */
-+					/* DEBUG_WARN("%s()-%d: nat25_db_handle INSERT Warning!\n", __FUNCTION__, __LINE__); */
-+					/* return -1; */ /* return -1 will cause system crash on 2011/08/30! */
-+					return 0;
-+				}
-+			}
-+
-+			memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
-+
-+			dhcp_flag_bcast(padapter, skb);
-+
-+			if (is_vlan_tag) {
-+				skb_push(skb, 4);
-+				for (i = 0; i < 6; i++)
-+					*((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2));
-+				*((unsigned short *)(skb->data + MACADDRLEN * 2)) = __constant_htons(ETH_P_8021Q);
-+				*((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)) = vlan_hdr;
-+			}
-+		}
-+#if 0
-+		else {
-+			if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_8021Q))
-+				is_vlan_tag = 1;
-+
-+			if (is_vlan_tag) {
-+				if (ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A_VALN(skb->data))
-+					memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
-+			} else {
-+				if (ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A(skb->data))
-+					memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN);
-+			}
-+		}
-+#endif /* 0 */
-+
-+		/* check if SA is equal to our MAC */
-+		if (memcmp(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN)) {
-+			/* priv->ext_stats.tx_drops++; */
-+			DEBUG_ERR("TX DROP: untransformed frame SA:%02X%02X%02X%02X%02X%02X!\n",
-+				skb->data[6], skb->data[7], skb->data[8], skb->data[9], skb->data[10], skb->data[11]);
-+			/* goto free_and_stop; */
-+			return -1;
-+		}
-+	}
-+	return 0;
-+}
-+#endif /* CONFIG_BR_EXT */
-+
-+u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe)
-+{
-+	u32 addr;
-+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
-+
-+	switch (pattrib->qsel) {
-+	case 0:
-+	case 3:
-+		addr = BE_QUEUE_INX;
-+		break;
-+	case 1:
-+	case 2:
-+		addr = BK_QUEUE_INX;
-+		break;
-+	case 4:
-+	case 5:
-+		addr = VI_QUEUE_INX;
-+		break;
-+	case 6:
-+	case 7:
-+		addr = VO_QUEUE_INX;
-+		break;
-+	case 0x10:
-+		addr = BCN_QUEUE_INX;
-+		break;
-+	case 0x11: /* BC/MC in PS (HIQ) */
-+		addr = HIGH_QUEUE_INX;
-+		break;
-+	case 0x13:
-+		addr = TXCMD_QUEUE_INX;
-+		break;
-+	case 0x12:
-+	default:
-+		addr = MGT_QUEUE_INX;
-+		break;
-+
-+	}
-+
-+	return addr;
-+
-+}
-+
-+static void do_queue_select(_adapter	*padapter, struct pkt_attrib *pattrib)
-+{
-+	u8 qsel;
-+
-+	qsel = pattrib->priority;
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(padapter)) {
-+		/* Under MCC */
-+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
-+			if (padapter->mcc_adapterpriv.role == MCC_ROLE_GO
-+			    || padapter->mcc_adapterpriv.role == MCC_ROLE_AP) {
-+				pattrib->qsel = QSLT_VO; /* AP interface VO queue */
-+				pattrib->priority  = QSLT_VO;
-+			} else {
-+				pattrib->qsel = QSLT_BE; /* STA interface BE queue */
-+				pattrib->priority  = QSLT_BE;
-+			}
-+		} else
-+			/* Not Under MCC */
-+			pattrib->qsel = qsel;
-+	} else
-+		/* Not enable MCC */
-+		pattrib->qsel = qsel;
-+#else /* !CONFIG_MCC_MODE */
-+	pattrib->qsel = qsel;
-+#endif /* CONFIG_MCC_MODE */
-+
-+	/* high priority packet */
-+	if (pattrib->hipriority_pkt) {
-+		pattrib->qsel = QSLT_VO;
-+		pattrib->priority  = QSLT_VO;
-+	}
-+}
-+
-+/*
-+ * The main transmit(tx) entry
-+ *
-+ * Return
-+ *	1	enqueue
-+ *	0	success, hardware will handle this xmit frame(packet)
-+ *	<0	fail
-+ */
-+ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
-+s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev)
-+{
-+	u16 frame_ctl;
-+	struct ieee80211_radiotap_header rtap_hdr;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct pkt_file pktfile;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	struct pkt_attrib	*pattrib;
-+	struct xmit_frame		*pmgntframe;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
-+	unsigned char	*pframe;
-+	u8 dummybuf[32];
-+	int len = skb->len, rtap_len;
-+
-+
-+	rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize);
-+
-+#ifndef CONFIG_CUSTOMER_ALIBABA_GENERAL
-+	if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header)))
-+		goto fail;
-+
-+	_rtw_open_pktfile((_pkt *)skb, &pktfile);
-+	_rtw_pktfile_read(&pktfile, (u8 *)(&rtap_hdr), sizeof(struct ieee80211_radiotap_header));
-+	rtap_len = ieee80211_get_radiotap_len((u8 *)(&rtap_hdr));
-+	if (unlikely(rtap_hdr.it_version))
-+		goto fail;
-+
-+	if (unlikely(skb->len < rtap_len))
-+		goto fail;
-+
-+	if (rtap_len != 12) {
-+		RTW_INFO("radiotap len (should be 14): %d\n", rtap_len);
-+		goto fail;
-+	}
-+	_rtw_pktfile_read(&pktfile, dummybuf, rtap_len-sizeof(struct ieee80211_radiotap_header));
-+	len = len - rtap_len;
-+#endif
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL) {
-+		rtw_udelay_os(500);
-+		goto fail;
-+	}
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+//	_rtw_memcpy(pframe, (void *)checking, len);
-+	_rtw_pktfile_read(&pktfile, pframe, len);
-+
-+
-+	/* Check DATA/MGNT frames */
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+	frame_ctl = le16_to_cpu(pwlanhdr->frame_ctl);
-+	if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) {
-+
-+		pattrib = &pmgntframe->attrib;
-+		update_monitor_frame_attrib(padapter, pattrib);
-+
-+		if (is_broadcast_mac_addr(pwlanhdr->addr3) || is_broadcast_mac_addr(pwlanhdr->addr1))
-+			pattrib->rate = MGN_24M;
-+
-+	} else {
-+
-+		pattrib = &pmgntframe->attrib;
-+		update_mgntframe_attrib(padapter, pattrib);
-+
-+	}
-+	pattrib->retry_ctrl = _FALSE;
-+	pattrib->pktlen = len;
-+	pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
-+	pattrib->seqnum = pmlmeext->mgnt_seq;
-+	pmlmeext->mgnt_seq++;
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+fail:
-+	rtw_skb_free(skb);
-+	return 0;
-+}
-+#endif
-+
-+/*
-+ *
-+ * Return _TRUE when frame has been put to queue, otherwise return _FALSE.
-+ */
-+static u8 xmit_enqueue(struct _ADAPTER *a, struct xmit_frame *frame)
-+{
-+	struct sta_info *sta = NULL;
-+	struct pkt_attrib *attrib = NULL;
-+	_irqL irqL;
-+	_list *head;
-+	u8 ret = _TRUE;
-+
-+
-+	attrib = &frame->attrib;
-+	sta = attrib->psta;
-+	if (!sta)
-+		return _FALSE;
-+
-+	_enter_critical_bh(&sta->tx_queue.lock, &irqL);
-+
-+	head = get_list_head(&sta->tx_queue);
-+
-+	if ((rtw_is_list_empty(head) == _TRUE) && (!sta->tx_q_enable)) {
-+		ret = _FALSE;
-+		goto exit;
-+	}
-+
-+	rtw_list_insert_tail(&frame->list, head);
-+	RTW_INFO(FUNC_ADPT_FMT ": en-queue tx pkt for macid=%d\n",
-+		 FUNC_ADPT_ARG(a), sta->cmn.mac_id);
-+
-+exit:
-+	_exit_critical_bh(&sta->tx_queue.lock, &irqL);
-+
-+	return ret;
-+}
-+
-+static void xmit_dequeue(struct sta_info *sta)
-+{
-+	struct _ADAPTER *a;
-+	_irqL irqL;
-+	_list *head, *list;
-+	struct xmit_frame *frame;
-+
-+
-+	a = sta->padapter;
-+
-+	_enter_critical_bh(&sta->tx_queue.lock, &irqL);
-+
-+	head = get_list_head(&sta->tx_queue);
-+
-+	do {
-+		if (rtw_is_list_empty(head) == _TRUE)
-+			break;
-+
-+		list = get_next(head);
-+		rtw_list_delete(list);
-+		frame = LIST_CONTAINOR(list, struct xmit_frame, list);
-+		RTW_INFO(FUNC_ADPT_FMT ": de-queue tx frame of macid=%d\n",
-+			 FUNC_ADPT_ARG(a), sta->cmn.mac_id);
-+
-+		rtw_hal_xmit(a, frame);
-+	} while (1);
-+
-+	_exit_critical_bh(&sta->tx_queue.lock, &irqL);
-+}
-+
-+void rtw_xmit_dequeue_callback(_workitem *work)
-+{
-+	struct sta_info *sta;
-+
-+
-+	sta = container_of(work, struct sta_info, tx_q_work);
-+	xmit_dequeue(sta);
-+}
-+
-+void rtw_xmit_queue_set(struct sta_info *sta)
-+{
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&sta->tx_queue.lock, &irqL);
-+
-+	if (sta->tx_q_enable) {
-+		RTW_WARN(FUNC_ADPT_FMT ": duplicated set!\n",
-+			 FUNC_ADPT_ARG(sta->padapter));
-+		goto exit;
-+	}
-+	sta->tx_q_enable = 1;
-+	RTW_INFO(FUNC_ADPT_FMT ": enable queue TX for macid=%d\n",
-+		 FUNC_ADPT_ARG(sta->padapter), sta->cmn.mac_id);
-+
-+exit:
-+	_exit_critical_bh(&sta->tx_queue.lock, &irqL);
-+}
-+
-+void rtw_xmit_queue_clear(struct sta_info *sta)
-+{
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&sta->tx_queue.lock, &irqL);
-+
-+	if (!sta->tx_q_enable) {
-+		RTW_WARN(FUNC_ADPT_FMT ": tx queue for macid=%d "
-+			 "not be enabled!\n",
-+			 FUNC_ADPT_ARG(sta->padapter), sta->cmn.mac_id);
-+		goto exit;
-+	}
-+
-+	sta->tx_q_enable = 0;
-+	RTW_INFO(FUNC_ADPT_FMT ": disable queue TX for macid=%d\n",
-+		 FUNC_ADPT_ARG(sta->padapter), sta->cmn.mac_id);
-+
-+	_set_workitem(&sta->tx_q_work);
-+
-+exit:
-+	_exit_critical_bh(&sta->tx_queue.lock, &irqL);
-+}
-+
-+/*
-+ * The main transmit(tx) entry post handle
-+ *
-+ * Return
-+ *	1	enqueue
-+ *	0	success, hardware will handle this xmit frame(packet)
-+ *	<0	fail
-+ */
-+s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt)
-+{
-+#ifdef CONFIG_AP_MODE
-+	_irqL irqL0;
-+#endif
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	s32 res;
-+
-+	res = update_attrib(padapter, pkt, &pxmitframe->attrib);
-+
-+#ifdef CONFIG_MCC_MODE
-+	/* record data kernel TX to driver to check MCC concurrent TX */
-+	rtw_hal_mcc_calc_tx_bytes_from_kernel(padapter, pxmitframe->attrib.pktlen);
-+#endif /* CONFIG_MCC_MODE */
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	if (pxmitframe->attrib.ether_type != 0x88B4) {
-+		if (rtw_wapi_drop_for_key_absent(padapter, pxmitframe->attrib.ra)) {
-+			WAPI_TRACE(WAPI_RX, "drop for key absend when tx\n");
-+			res = _FAIL;
-+		}
-+	}
-+#endif
-+	if (res == _FAIL) {
-+		/*RTW_INFO("%s-"ADPT_FMT" update attrib fail\n", __func__, ADPT_ARG(padapter));*/
-+#ifdef DBG_TX_DROP_FRAME
-+		RTW_INFO("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__);
-+#endif
-+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
-+		return -1;
-+	}
-+	pxmitframe->pkt = pkt;
-+
-+	rtw_led_tx_control(padapter, pxmitframe->attrib.dst);
-+
-+	do_queue_select(padapter, &pxmitframe->attrib);
-+
-+#ifdef CONFIG_AP_MODE
-+	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
-+	if (xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) {
-+		_exit_critical_bh(&pxmitpriv->lock, &irqL0);
-+		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue);
-+		return 1;
-+	}
-+	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
-+#endif
-+
-+	if (xmit_enqueue(padapter, pxmitframe) == _TRUE)
-+		return 1;
-+
-+	/* pre_xmitframe */
-+	if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE)
-+		return 1;
-+
-+	return 0;
-+}
-+
-+/*
-+ * The main transmit(tx) entry
-+ *
-+ * Return
-+ *	1	enqueue
-+ *	0	success, hardware will handle this xmit frame(packet)
-+ *	<0	fail
-+ */
-+s32 rtw_xmit(_adapter *padapter, _pkt **ppkt, u16 os_qid)
-+{
-+	static systime start = 0;
-+	static u32 drop_cnt = 0;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	struct xmit_frame *pxmitframe = NULL;
-+	s32 res;
-+
-+	DBG_COUNTER(padapter->tx_logs.core_tx);
-+
-+	if (IS_CH_WAITING(adapter_to_rfctl(padapter)))
-+		return -1;
-+
-+	if (rtw_linked_check(padapter) == _FALSE)
-+		return -1;
-+
-+	if (start == 0)
-+		start = rtw_get_current_time();
-+
-+	pxmitframe = rtw_alloc_xmitframe(pxmitpriv, os_qid);
-+
-+	if (rtw_get_passing_time_ms(start) > 2000) {
-+		if (drop_cnt)
-+			RTW_INFO("DBG_TX_DROP_FRAME %s no more pxmitframe, drop_cnt:%u\n", __FUNCTION__, drop_cnt);
-+		start = rtw_get_current_time();
-+		drop_cnt = 0;
-+	}
-+
-+	if (pxmitframe == NULL) {
-+		drop_cnt++;
-+		/*RTW_INFO("%s-"ADPT_FMT" no more xmitframe\n", __func__, ADPT_ARG(padapter));*/
-+		DBG_COUNTER(padapter->tx_logs.core_tx_err_pxmitframe);
-+		return -1;
-+	}
-+
-+#ifdef CONFIG_BR_EXT
-+	if (!adapter_use_wds(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) {
-+		void *br_port = NULL;
-+
-+		#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
-+		br_port = padapter->pnetdev->br_port;
-+		#else
-+		rcu_read_lock();
-+		br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
-+		rcu_read_unlock();
-+		#endif
-+
-+		if (br_port) {
-+			res = rtw_br_client_tx(padapter, ppkt);
-+			if (res == -1) {
-+				rtw_free_xmitframe(pxmitpriv, pxmitframe);
-+				DBG_COUNTER(padapter->tx_logs.core_tx_err_brtx);
-+				return -1;
-+			}
-+		}
-+	}
-+#endif /* CONFIG_BR_EXT */
-+
-+#if defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH)
-+	if (MLME_STATE(padapter) & (WIFI_AP_STATE | WIFI_MESH_STATE)) {
-+		_list b2u_list;
-+
-+		#ifdef CONFIG_RTW_MESH
-+		if (MLME_IS_MESH(padapter))
-+			res = rtw_mesh_addr_resolve(padapter, os_qid, pxmitframe, *ppkt, &b2u_list);
-+		else
-+		#endif
-+			res = rtw_ap_addr_resolve(padapter, os_qid, pxmitframe, *ppkt, &b2u_list);
-+		if (res == RTW_RA_RESOLVING)
-+			return 1;
-+		if (res == _FAIL)
-+			return -1;
-+
-+		#if CONFIG_RTW_DATA_BMC_TO_UC
-+		if (!rtw_is_list_empty(&b2u_list)) {
-+			_list *list = get_next(&b2u_list);
-+			struct xmit_frame *b2uframe;
-+
-+			while ((rtw_end_of_queue_search(&b2u_list, list)) == _FALSE) {
-+				b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);
-+				list = get_next(list);
-+				rtw_list_delete(&b2uframe->list);
-+
-+				b2uframe->pkt = rtw_os_pkt_copy(*ppkt);
-+				if (!b2uframe->pkt) {
-+					if (res == RTW_BMC_NO_NEED)
-+						res = _SUCCESS;
-+					rtw_free_xmitframe(pxmitpriv, b2uframe);
-+					continue;
-+				}
-+
-+				rtw_xmit_posthandle(padapter, b2uframe, b2uframe->pkt);
-+			}
-+		}
-+		#endif
-+
-+		if (res == RTW_BMC_NO_NEED) {
-+			rtw_free_xmitframe(&padapter->xmitpriv, pxmitframe);
-+			return 0;
-+		}
-+	}
-+#endif /* defined(CONFIG_AP_MODE) || defined(CONFIG_RTW_MESH) */
-+
-+	pxmitframe->pkt = NULL; /* let rtw_xmit_posthandle not to free pkt inside */
-+	res = rtw_xmit_posthandle(padapter, pxmitframe, *ppkt);
-+
-+	return res;
-+}
-+
-+#ifdef CONFIG_TDLS
-+sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe)
-+{
-+	sint ret = _FALSE;
-+
-+	_irqL irqL;
-+	struct sta_info *ptdls_sta = NULL;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	int i;
-+
-+	ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
-+	if (ptdls_sta == NULL)
-+		return ret;
-+	else if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
-+
-+		if (pattrib->triggered == 1) {
-+			ret = _TRUE;
-+			return ret;
-+		}
-+
-+		_enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
-+
-+		if (ptdls_sta->state & WIFI_SLEEP_STATE) {
-+			rtw_list_delete(&pxmitframe->list);
-+
-+			/* _enter_critical_bh(&psta->sleep_q.lock, &irqL);	 */
-+
-+			rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptdls_sta->sleep_q));
-+
-+			ptdls_sta->sleepq_len++;
-+			ptdls_sta->sleepq_ac_len++;
-+
-+			/* indicate 4-AC queue bit in TDLS peer traffic indication */
-+			switch (pattrib->priority) {
-+			case 1:
-+			case 2:
-+				ptdls_sta->uapsd_bk |= BIT(1);
-+				break;
-+			case 4:
-+			case 5:
-+				ptdls_sta->uapsd_vi |= BIT(1);
-+				break;
-+			case 6:
-+			case 7:
-+				ptdls_sta->uapsd_vo |= BIT(1);
-+				break;
-+			case 0:
-+			case 3:
-+			default:
-+				ptdls_sta->uapsd_be |= BIT(1);
-+				break;
-+			}
-+
-+			/* Transmit TDLS PTI via AP */
-+			if (ptdls_sta->sleepq_len == 1)
-+				rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ISSUE_PTI);
-+
-+			ret = _TRUE;
-+		}
-+
-+		_exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL);
-+	}
-+
-+	return ret;
-+
-+}
-+#endif /* CONFIG_TDLS */
-+
-+#define RTW_HIQ_FILTER_ALLOW_ALL 0
-+#define RTW_HIQ_FILTER_ALLOW_SPECIAL 1
-+#define RTW_HIQ_FILTER_DENY_ALL 2
-+
-+inline bool xmitframe_hiq_filter(struct xmit_frame *xmitframe)
-+{
-+	bool allow = _FALSE;
-+	_adapter *adapter = xmitframe->padapter;
-+	struct registry_priv *registry = &adapter->registrypriv;
-+
-+	if (adapter->registrypriv.wifi_spec == 1)
-+		allow = _TRUE;
-+	else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_SPECIAL) {
-+
-+		struct pkt_attrib *attrib = &xmitframe->attrib;
-+
-+		if (attrib->ether_type == 0x0806
-+		    || attrib->ether_type == 0x888e
-+#ifdef CONFIG_WAPI_SUPPORT
-+		    || attrib->ether_type == 0x88B4
-+#endif
-+		    || attrib->dhcp_pkt
-+		   ) {
-+			if (0)
-+				RTW_INFO(FUNC_ADPT_FMT" ether_type:0x%04x%s\n", FUNC_ADPT_ARG(xmitframe->padapter)
-+					, attrib->ether_type, attrib->dhcp_pkt ? " DHCP" : "");
-+			allow = _TRUE;
-+		}
-+	} else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_ALL)
-+		allow = _TRUE;
-+	else if (registry->hiq_filter == RTW_HIQ_FILTER_DENY_ALL)
-+		allow = _FALSE;
-+	else
-+		rtw_warn_on(1);
-+
-+	return allow;
-+}
-+
-+#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS)
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+u8 mgmt_xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe)
-+{
-+	_irqL irqL;
-+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
-+	struct sta_info *psta = pattrib->psta;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	bool update_tim = _FALSE;
-+	u8 ret = _TRUE;
-+
-+	if (is_broadcast_mac_addr(pattrib->ra) || pattrib->ps_dontq)
-+		return _FALSE;
-+
-+	if (psta == NULL) {
-+		RTW_INFO("%s, psta==NUL, pattrib->ra:"MAC_FMT"\n",
-+				    __func__, MAC_ARG(pattrib->ra));
-+		return _FALSE;
-+	}
-+
-+	if (!(psta->state & WIFI_ASOC_STATE)) {
-+		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_link);
-+		RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
-+		return _FALSE;
-+	}
-+
-+	_enter_critical_bh(&psta->mgmt_sleep_q.lock, &irqL);
-+
-+	if (psta->state & WIFI_SLEEP_STATE &&
-+		rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid)) {
-+
-+		rtw_list_delete(&pxmitframe->list);
-+		rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->mgmt_sleep_q));
-+		psta->mgmt_sleepq_len++;
-+
-+		#ifdef DBG_MGMT_QUEUE
-+			RTW_INFO("%s attrib->ra:"MAC_FMT" seq_num = %u, subtype = 0x%x\n",
-+			__func__, MAC_ARG(pattrib->ra), pattrib->seqnum, pattrib->subtype);
-+		#endif
-+
-+		if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)))
-+			update_tim = _TRUE;
-+
-+		rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
-+
-+		/* upate BCN for TIM IE */
-+		if (update_tim == _TRUE)
-+			_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "buffer mgmt frame");
-+
-+		ret = RTW_QUEUE_MGMT;
-+		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_ucast);
-+	}
-+
-+	_exit_critical_bh(&psta->mgmt_sleep_q.lock, &irqL);
-+
-+	return ret;
-+}
-+
-+static void dequeue_mgmt_xmitframe_to_sleepq(_adapter *padapter, struct sta_info *psta, _queue *pframequeue)
-+{
-+	sint ret;
-+	_list	*plist, *phead;
-+	struct tx_servq *ptxservq;
-+	struct pkt_attrib *pattrib;
-+	struct xmit_frame *pxmitframe;
-+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
-+	struct hw_xmit *phwxmits = pxmitpriv->hwxmits;
-+	u8 mgmt_idx = pxmitpriv->hwxmit_entry - 1;
-+
-+	phead = get_list_head(pframequeue);
-+	plist = get_next(phead);
-+
-+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+		pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
-+		plist = get_next(plist);
-+
-+		pattrib = &pxmitframe->attrib;
-+		pattrib->triggered = 0;
-+
-+		ret = mgmt_xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe);
-+
-+		if (ret == RTW_QUEUE_MGMT) {
-+			ptxservq = &(psta->sta_xmitpriv.mgmt_q);
-+			ptxservq->qcnt--;
-+			phwxmits[mgmt_idx].accnt--;
-+		} else {
-+			/* RTW_INFO("xmitframe_enqueue_for_sleeping_sta return _FALSE\n"); */
-+		}
-+	}
-+}
-+#endif
-+
-+sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe)
-+{
-+	_irqL irqL;
-+	sint ret = _FALSE;
-+	struct sta_info *psta = NULL;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
-+	sint bmcst = IS_MCAST(pattrib->ra);
-+	bool update_tim = _FALSE;
-+#ifdef CONFIG_TDLS
-+
-+	if (padapter->tdlsinfo.link_established == _TRUE)
-+		ret = xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pxmitframe);
-+#endif /* CONFIG_TDLS */
-+
-+	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) {
-+		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_fwstate);
-+		return ret;
-+	}
-+	/*
-+		if(pattrib->psta)
-+		{
-+			psta = pattrib->psta;
-+		}
-+		else
-+		{
-+			RTW_INFO("%s, call rtw_get_stainfo()\n", __func__);
-+			psta=rtw_get_stainfo(pstapriv, pattrib->ra);
-+		}
-+	*/
-+	psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
-+	if (pattrib->psta != psta) {
-+		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_sta);
-+		RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta);
-+		return _FALSE;
-+	}
-+
-+	if (psta == NULL) {
-+		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_nosta);
-+		RTW_INFO("%s, psta==NUL\n", __func__);
-+		return _FALSE;
-+	}
-+
-+	if (!(psta->state & WIFI_ASOC_STATE)) {
-+		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_link);
-+		RTW_INFO("%s, psta->state(0x%x) != WIFI_ASOC_STATE\n", __func__, psta->state);
-+		return _FALSE;
-+	}
-+
-+	if (pattrib->triggered == 1) {
-+		DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_trigger);
-+		/* RTW_INFO("directly xmit pspoll_triggered packet\n"); */
-+
-+		/* pattrib->triggered=0; */
-+		if (bmcst && xmitframe_hiq_filter(pxmitframe) == _TRUE)
-+			pattrib->qsel = QSLT_HIGH;/* HIQ */
-+
-+		return ret;
-+	}
-+
-+
-+	if (bmcst) {
-+		_enter_critical_bh(&psta->sleep_q.lock, &irqL);
-+
-+		if (rtw_tim_map_anyone_be_set(padapter, pstapriv->sta_dz_bitmap)) { /* if anyone sta is in ps mode */
-+			/* pattrib->qsel = QSLT_HIGH; */ /* HIQ */
-+
-+			rtw_list_delete(&pxmitframe->list);
-+
-+			/*_enter_critical_bh(&psta->sleep_q.lock, &irqL);*/
-+
-+			rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q));
-+
-+			psta->sleepq_len++;
-+
-+			if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)))
-+				update_tim = _TRUE;
-+
-+			rtw_tim_map_set(padapter, pstapriv->tim_bitmap, 0);
-+			rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, 0);
-+
-+			/* RTW_INFO("enqueue, sq_len=%d\n", psta->sleepq_len); */
-+			/* RTW_INFO_DUMP("enqueue, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
-+			if (update_tim == _TRUE) {
-+				if (is_broadcast_mac_addr(pattrib->ra))
-+					_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "buffer BC");
-+				else
-+					_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "buffer MC");
-+			} else
-+				chk_bmc_sleepq_cmd(padapter);
-+
-+			/*_exit_critical_bh(&psta->sleep_q.lock, &irqL);*/
-+
-+			ret = _TRUE;
-+
-+			DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_mcast);
-+		}
-+
-+		_exit_critical_bh(&psta->sleep_q.lock, &irqL);
-+
-+		return ret;
-+
-+	}
-+
-+
-+	_enter_critical_bh(&psta->sleep_q.lock, &irqL);
-+
-+	if (psta->state & WIFI_SLEEP_STATE) {
-+		u8 wmmps_ac = 0;
-+
-+		if (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid)) {
-+			rtw_list_delete(&pxmitframe->list);
-+
-+			/* _enter_critical_bh(&psta->sleep_q.lock, &irqL);	 */
-+
-+			rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q));
-+
-+			psta->sleepq_len++;
-+
-+			switch (pattrib->priority) {
-+			case 1:
-+			case 2:
-+				wmmps_ac = psta->uapsd_bk & BIT(0);
-+				break;
-+			case 4:
-+			case 5:
-+				wmmps_ac = psta->uapsd_vi & BIT(0);
-+				break;
-+			case 6:
-+			case 7:
-+				wmmps_ac = psta->uapsd_vo & BIT(0);
-+				break;
-+			case 0:
-+			case 3:
-+			default:
-+				wmmps_ac = psta->uapsd_be & BIT(0);
-+				break;
-+			}
-+
-+			if (wmmps_ac)
-+				psta->sleepq_ac_len++;
-+
-+			if (((psta->has_legacy_ac) && (!wmmps_ac)) || ((!psta->has_legacy_ac) && (wmmps_ac))) {
-+				if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)))
-+					update_tim = _TRUE;
-+
-+				rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
-+
-+				/* RTW_INFO("enqueue, sq_len=%d\n", psta->sleepq_len); */
-+				/* RTW_INFO_DUMP("enqueue, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
-+
-+				if (update_tim == _TRUE) {
-+					/* RTW_INFO("sleepq_len==1, update BCNTIM\n"); */
-+					/* upate BCN for TIM IE */
-+					_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "buffer UC");
-+				}
-+			}
-+
-+			/* _exit_critical_bh(&psta->sleep_q.lock, &irqL);			 */
-+
-+			/* if(psta->sleepq_len > (NR_XMITFRAME>>3)) */
-+			/* { */
-+			/*	wakeup_sta_to_xmit(padapter, psta); */
-+			/* }	 */
-+
-+			ret = _TRUE;
-+
-+			DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_ucast);
-+		}
-+
-+	}
-+
-+	_exit_critical_bh(&psta->sleep_q.lock, &irqL);
-+
-+	return ret;
-+
-+}
-+
-+static void dequeue_xmitframes_to_sleeping_queue(_adapter *padapter, struct sta_info *psta, _queue *pframequeue)
-+{
-+	sint ret;
-+	_list	*plist, *phead;
-+	u8	ac_index;
-+	struct tx_servq	*ptxservq;
-+	struct pkt_attrib	*pattrib;
-+	struct xmit_frame	*pxmitframe;
-+	struct hw_xmit *phwxmits =  padapter->xmitpriv.hwxmits;
-+
-+	phead = get_list_head(pframequeue);
-+	plist = get_next(phead);
-+
-+	while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
-+		pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list);
-+
-+		plist = get_next(plist);
-+
-+		pattrib = &pxmitframe->attrib;
-+
-+		pattrib->triggered = 0;
-+
-+		ret = xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe);
-+
-+		if (_TRUE == ret) {
-+			ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index));
-+
-+			ptxservq->qcnt--;
-+			phwxmits[ac_index].accnt--;
-+		} else {
-+			/* RTW_INFO("xmitframe_enqueue_for_sleeping_sta return _FALSE\n"); */
-+		}
-+
-+	}
-+
-+}
-+
-+void stop_sta_xmit(_adapter *padapter, struct sta_info *psta)
-+{
-+	_irqL irqL0;
-+	struct sta_info *psta_bmc;
-+	struct sta_xmit_priv *pstaxmitpriv;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+
-+	pstaxmitpriv = &psta->sta_xmitpriv;
-+
-+	/* for BC/MC Frames */
-+	psta_bmc = rtw_get_bcmc_stainfo(padapter);
-+	if (!psta_bmc)
-+		rtw_warn_on(1);
-+
-+	_enter_critical_bh(&pxmitpriv->lock, &irqL0);
-+
-+	psta->state |= WIFI_SLEEP_STATE;
-+
-+#ifdef CONFIG_TDLS
-+	if (!(psta->tdls_sta_state & TDLS_LINKED_STATE))
-+#endif /* CONFIG_TDLS */
-+		rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	dequeue_mgmt_xmitframe_to_sleepq(padapter, psta, &pstaxmitpriv->mgmt_q.sta_pending);
-+	rtw_list_delete(&(pstaxmitpriv->mgmt_q.tx_pending));
-+#endif
-+
-+	dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vo_q.sta_pending);
-+	rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
-+	dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vi_q.sta_pending);
-+	rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
-+	dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->be_q.sta_pending);
-+	rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
-+	dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->bk_q.sta_pending);
-+	rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
-+
-+	if (psta_bmc != NULL
-+		#ifdef CONFIG_TDLS
-+		&& !(psta->tdls_sta_state & TDLS_LINKED_STATE)
-+		#endif
-+	)
-+	{
-+		/* for BC/MC Frames */
-+		pstaxmitpriv = &psta_bmc->sta_xmitpriv;
-+		dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vo_q.sta_pending);
-+		rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
-+		dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vi_q.sta_pending);
-+		rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
-+		dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->be_q.sta_pending);
-+		rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
-+		dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->bk_q.sta_pending);
-+		rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
-+	}
-+	_exit_critical_bh(&pxmitpriv->lock, &irqL0);
-+
-+
-+}
-+
-+void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta)
-+{
-+	_irqL irqL;
-+	u8 update_mask = 0, wmmps_ac = 0;
-+	struct sta_info *psta_bmc;
-+	_list	*xmitframe_plist, *xmitframe_phead;
-+	struct xmit_frame *pxmitframe = NULL;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+
-+	psta_bmc = rtw_get_bcmc_stainfo(padapter);
-+
-+
-+	/* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */
-+	_enter_critical_bh(&pxmitpriv->lock, &irqL);
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	/* management queue */
-+	xmitframe_phead = get_list_head(&psta->mgmt_sleep_q);
-+	xmitframe_plist = get_next(xmitframe_phead);
-+
-+	while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
-+		pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
-+
-+		xmitframe_plist = get_next(xmitframe_plist);
-+
-+		rtw_list_delete(&pxmitframe->list);
-+
-+		#ifdef DBG_MGMT_QUEUE
-+		RTW_INFO("%s seq_num = %u, subtype = 0x%x\n",
-+				__func__, pxmitframe->attrib.seqnum, pxmitframe->attrib.subtype);
-+		#endif
-+
-+		psta->mgmt_sleepq_len--;
-+
-+		pxmitframe->attrib.triggered = 1;
-+
-+		rtw_hal_mgmt_xmitframe_enqueue(padapter, pxmitframe);
-+	}
-+#endif /* CONFIG_RTW_MGMT_QUEUE */
-+
-+	/* AC queue */
-+	xmitframe_phead = get_list_head(&psta->sleep_q);
-+	xmitframe_plist = get_next(xmitframe_phead);
-+
-+	while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
-+		pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
-+
-+		xmitframe_plist = get_next(xmitframe_plist);
-+
-+		rtw_list_delete(&pxmitframe->list);
-+
-+		switch (pxmitframe->attrib.priority) {
-+		case 1:
-+		case 2:
-+			wmmps_ac = psta->uapsd_bk & BIT(1);
-+			break;
-+		case 4:
-+		case 5:
-+			wmmps_ac = psta->uapsd_vi & BIT(1);
-+			break;
-+		case 6:
-+		case 7:
-+			wmmps_ac = psta->uapsd_vo & BIT(1);
-+			break;
-+		case 0:
-+		case 3:
-+		default:
-+			wmmps_ac = psta->uapsd_be & BIT(1);
-+			break;
-+		}
-+
-+		psta->sleepq_len--;
-+		if (psta->sleepq_len > 0)
-+			pxmitframe->attrib.mdata = 1;
-+		else
-+			pxmitframe->attrib.mdata = 0;
-+
-+		if (wmmps_ac) {
-+			psta->sleepq_ac_len--;
-+			if (psta->sleepq_ac_len > 0) {
-+				pxmitframe->attrib.mdata = 1;
-+				pxmitframe->attrib.eosp = 0;
-+			} else {
-+				pxmitframe->attrib.mdata = 0;
-+				pxmitframe->attrib.eosp = 1;
-+			}
-+		}
-+
-+		pxmitframe->attrib.triggered = 1;
-+
-+		/*
-+				_exit_critical_bh(&psta->sleep_q.lock, &irqL);
-+				if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
-+				{
-+					rtw_os_xmit_complete(padapter, pxmitframe);
-+				}
-+				_enter_critical_bh(&psta->sleep_q.lock, &irqL);
-+		*/
-+		rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
-+
-+
-+	}
-+
-+	if (psta->sleepq_len == 0
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+		&& psta->mgmt_sleepq_len == 0
-+#endif
-+	) {
-+#ifdef CONFIG_TDLS
-+		if (psta->tdls_sta_state & TDLS_LINKED_STATE) {
-+			if (psta->state & WIFI_SLEEP_STATE)
-+				psta->state ^= WIFI_SLEEP_STATE;
-+
-+			_exit_critical_bh(&pxmitpriv->lock, &irqL);
-+			return;
-+		}
-+#endif /* CONFIG_TDLS */
-+
-+		if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {
-+			/* RTW_INFO("wakeup to xmit, qlen==0\n"); */
-+			/* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
-+			/* upate BCN for TIM IE */
-+			/* update_BCNTIM(padapter); */
-+			update_mask = BIT(0);
-+		}
-+
-+		rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
-+
-+		if (psta->state & WIFI_SLEEP_STATE)
-+			psta->state ^= WIFI_SLEEP_STATE;
-+
-+		if (psta->state & WIFI_STA_ALIVE_CHK_STATE) {
-+			RTW_INFO("%s alive check\n", __func__);
-+			psta->expire_to = pstapriv->expire_to;
-+			psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
-+		}
-+
-+		rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);
-+	}
-+
-+	/* for BC/MC Frames */
-+	if (!psta_bmc)
-+		goto _exit;
-+
-+	if (!(rtw_tim_map_anyone_be_set_exclude_aid0(padapter, pstapriv->sta_dz_bitmap))) { /* no any sta in ps mode */
-+		xmitframe_phead = get_list_head(&psta_bmc->sleep_q);
-+		xmitframe_plist = get_next(xmitframe_phead);
-+
-+		while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
-+			pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
-+
-+			xmitframe_plist = get_next(xmitframe_plist);
-+
-+			rtw_list_delete(&pxmitframe->list);
-+
-+			psta_bmc->sleepq_len--;
-+			if (psta_bmc->sleepq_len > 0)
-+				pxmitframe->attrib.mdata = 1;
-+			else
-+				pxmitframe->attrib.mdata = 0;
-+
-+
-+			pxmitframe->attrib.triggered = 1;
-+			/*
-+						_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
-+						if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE)
-+						{
-+							rtw_os_xmit_complete(padapter, pxmitframe);
-+						}
-+						_enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL);
-+
-+			*/
-+			rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
-+
-+		}
-+
-+		if (psta_bmc->sleepq_len == 0) {
-+			if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) {
-+				/* RTW_INFO("wakeup to xmit, qlen==0\n"); */
-+				/* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
-+				/* upate BCN for TIM IE */
-+				/* update_BCNTIM(padapter); */
-+				update_mask |= BIT(1);
-+			}
-+			rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);
-+			rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);
-+		}
-+
-+	}
-+
-+_exit:
-+
-+	/* _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL);	 */
-+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
-+
-+	if (update_mask) {
-+		/* update_BCNTIM(padapter); */
-+		if ((update_mask & (BIT(0) | BIT(1))) == (BIT(0) | BIT(1)))
-+			_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "clear UC&BMC");
-+		else if ((update_mask & BIT(1)) == BIT(1))
-+			_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "clear BMC");
-+		else
-+			_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0, "clear UC");
-+	}
-+}
-+
-+void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta)
-+{
-+	_irqL irqL;
-+	u8 wmmps_ac = 0;
-+	_list	*xmitframe_plist, *xmitframe_phead;
-+	struct xmit_frame *pxmitframe = NULL;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+
-+
-+	/* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */
-+	_enter_critical_bh(&pxmitpriv->lock, &irqL);
-+
-+	xmitframe_phead = get_list_head(&psta->sleep_q);
-+	xmitframe_plist = get_next(xmitframe_phead);
-+
-+	while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) {
-+		pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
-+
-+		xmitframe_plist = get_next(xmitframe_plist);
-+
-+		switch (pxmitframe->attrib.priority) {
-+		case 1:
-+		case 2:
-+			wmmps_ac = psta->uapsd_bk & BIT(1);
-+			break;
-+		case 4:
-+		case 5:
-+			wmmps_ac = psta->uapsd_vi & BIT(1);
-+			break;
-+		case 6:
-+		case 7:
-+			wmmps_ac = psta->uapsd_vo & BIT(1);
-+			break;
-+		case 0:
-+		case 3:
-+		default:
-+			wmmps_ac = psta->uapsd_be & BIT(1);
-+			break;
-+		}
-+
-+		if (!wmmps_ac)
-+			continue;
-+
-+		rtw_list_delete(&pxmitframe->list);
-+
-+		psta->sleepq_len--;
-+		psta->sleepq_ac_len--;
-+
-+		if (psta->sleepq_ac_len > 0) {
-+			pxmitframe->attrib.mdata = 1;
-+			pxmitframe->attrib.eosp = 0;
-+		} else {
-+			pxmitframe->attrib.mdata = 0;
-+			pxmitframe->attrib.eosp = 1;
-+		}
-+
-+		pxmitframe->attrib.triggered = 1;
-+		rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
-+
-+		if ((psta->sleepq_ac_len == 0) && (!psta->has_legacy_ac) && (wmmps_ac)) {
-+#ifdef CONFIG_TDLS
-+			if (psta->tdls_sta_state & TDLS_LINKED_STATE) {
-+				/* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */
-+				goto exit;
-+			}
-+#endif /* CONFIG_TDLS */
-+			rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
-+
-+			/* RTW_INFO("wakeup to xmit, qlen==0\n"); */
-+			/* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
-+			/* upate BCN for TIM IE */
-+			/* update_BCNTIM(padapter); */
-+			update_beacon(padapter, _TIM_IE_, NULL, _TRUE, 0);
-+			/* update_mask = BIT(0); */
-+		}
-+
-+	}
-+
-+#ifdef CONFIG_TDLS
-+exit:
-+#endif
-+	/* _exit_critical_bh(&psta->sleep_q.lock, &irqL);	 */
-+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
-+
-+	return;
-+}
-+
-+#endif /* defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) */
-+
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+void enqueue_pending_xmitbuf(
-+	struct xmit_priv *pxmitpriv,
-+	struct xmit_buf *pxmitbuf)
-+{
-+	_irqL irql;
-+	_queue *pqueue;
-+	_adapter *pri_adapter = pxmitpriv->adapter;
-+
-+	pqueue = &pxmitpriv->pending_xmitbuf_queue;
-+
-+	_enter_critical_bh(&pqueue->lock, &irql);
-+	rtw_list_delete(&pxmitbuf->list);
-+	rtw_list_insert_tail(&pxmitbuf->list, get_list_head(pqueue));
-+	_exit_critical_bh(&pqueue->lock, &irql);
-+
-+#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_CONCURRENT_MODE)
-+	pri_adapter = GET_PRIMARY_ADAPTER(pri_adapter);
-+#endif /*SDIO_HCI + CONCURRENT*/
-+	_rtw_up_sema(&(pri_adapter->xmitpriv.xmit_sema));
-+}
-+
-+void enqueue_pending_xmitbuf_to_head(
-+	struct xmit_priv *pxmitpriv,
-+	struct xmit_buf *pxmitbuf)
-+{
-+	_irqL irql;
-+	_queue *pqueue = &pxmitpriv->pending_xmitbuf_queue;
-+
-+	_enter_critical_bh(&pqueue->lock, &irql);
-+	rtw_list_delete(&pxmitbuf->list);
-+	rtw_list_insert_head(&pxmitbuf->list, get_list_head(pqueue));
-+	_exit_critical_bh(&pqueue->lock, &irql);
-+}
-+
-+struct xmit_buf *dequeue_pending_xmitbuf(
-+	struct xmit_priv *pxmitpriv)
-+{
-+	_irqL irql;
-+	struct xmit_buf *pxmitbuf;
-+	_queue *pqueue;
-+
-+
-+	pxmitbuf = NULL;
-+	pqueue = &pxmitpriv->pending_xmitbuf_queue;
-+
-+	_enter_critical_bh(&pqueue->lock, &irql);
-+
-+	if (_rtw_queue_empty(pqueue) == _FALSE) {
-+		_list *plist, *phead;
-+
-+		phead = get_list_head(pqueue);
-+		plist = get_next(phead);
-+		pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
-+		rtw_list_delete(&pxmitbuf->list);
-+	}
-+
-+	_exit_critical_bh(&pqueue->lock, &irql);
-+
-+	return pxmitbuf;
-+}
-+
-+static struct xmit_buf *dequeue_pending_xmitbuf_ext(
-+	struct xmit_priv *pxmitpriv)
-+{
-+	_irqL irql;
-+	struct xmit_buf *pxmitbuf;
-+	_queue *pqueue;
-+
-+	pxmitbuf = NULL;
-+	pqueue = &pxmitpriv->pending_xmitbuf_queue;
-+
-+	_enter_critical_bh(&pqueue->lock, &irql);
-+
-+	if (_rtw_queue_empty(pqueue) == _FALSE) {
-+		_list *plist, *phead;
-+
-+		phead = get_list_head(pqueue);
-+		plist = phead;
-+		do {
-+			plist = get_next(plist);
-+			if (plist == phead)
-+				break;
-+
-+			pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
-+
-+			if (pxmitbuf->buf_tag == XMITBUF_MGNT) {
-+				rtw_list_delete(&pxmitbuf->list);
-+				break;
-+			}
-+			pxmitbuf = NULL;
-+		} while (1);
-+	}
-+
-+	_exit_critical_bh(&pqueue->lock, &irql);
-+
-+	return pxmitbuf;
-+}
-+
-+struct xmit_buf *select_and_dequeue_pending_xmitbuf(_adapter *padapter)
-+{
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	struct xmit_buf *pxmitbuf = NULL;
-+
-+	if (_TRUE == rtw_is_xmit_blocked(padapter))
-+		return pxmitbuf;
-+
-+	pxmitbuf = dequeue_pending_xmitbuf_ext(pxmitpriv);
-+	if (pxmitbuf == NULL && rtw_xmit_ac_blocked(padapter) != _TRUE)
-+		pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv);
-+
-+	return pxmitbuf;
-+}
-+
-+sint check_pending_xmitbuf(
-+	struct xmit_priv *pxmitpriv)
-+{
-+	_irqL irql;
-+	_queue *pqueue;
-+	sint	ret = _FALSE;
-+
-+	pqueue = &pxmitpriv->pending_xmitbuf_queue;
-+
-+	_enter_critical_bh(&pqueue->lock, &irql);
-+
-+	if (_rtw_queue_empty(pqueue) == _FALSE)
-+		ret = _TRUE;
-+
-+	_exit_critical_bh(&pqueue->lock, &irql);
-+
-+	return ret;
-+}
-+
-+thread_return rtw_xmit_thread(thread_context context)
-+{
-+	s32 err;
-+	PADAPTER padapter;
-+#ifdef RTW_XMIT_THREAD_HIGH_PRIORITY
-+#ifdef PLATFORM_LINUX
-+	struct sched_param param = { .sched_priority = 1 };
-+
-+	sched_setscheduler(current, SCHED_FIFO, &param);
-+#endif /* PLATFORM_LINUX */
-+#endif /* RTW_XMIT_THREAD_HIGH_PRIORITY */
-+
-+	err = _SUCCESS;
-+	padapter = (PADAPTER)context;
-+
-+	thread_enter("RTW_XMIT_THREAD");
-+
-+	do {
-+		err = rtw_hal_xmit_thread_handler(padapter);
-+		flush_signals_thread();
-+	} while (_SUCCESS == err);
-+
-+	RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter));
-+
-+	rtw_thread_wait_stop();
-+
-+	return 0;
-+}
-+#endif
-+
-+#ifdef DBG_XMIT_BLOCK
-+void dump_xmit_block(void *sel, _adapter *padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	RTW_PRINT_SEL(sel, "[XMIT-BLOCK] xmit_block :0x%02x\n", dvobj->xmit_block);
-+	if (dvobj->xmit_block & XMIT_BLOCK_REDLMEM)
-+		RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_REDLMEM");
-+	if (dvobj->xmit_block & XMIT_BLOCK_SUSPEND)
-+		RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_SUSPEND");
-+	if (dvobj->xmit_block == XMIT_BLOCK_NONE)
-+		RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_NONE");
-+}
-+void dump_xmit_block_info(void *sel, const char *fun_name, _adapter *padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	RTW_INFO("\n"ADPT_FMT" call %s\n", ADPT_ARG(padapter), fun_name);
-+	dump_xmit_block(sel, padapter);
-+}
-+#define DBG_XMIT_BLOCK_DUMP(adapter)	dump_xmit_block_info(RTW_DBGDUMP, __func__, adapter)
-+#endif
-+
-+void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason)
-+{
-+	_irqL irqL;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	_enter_critical_bh(&dvobj->xmit_block_lock, &irqL);
-+	dvobj->xmit_block |= reason;
-+	_exit_critical_bh(&dvobj->xmit_block_lock, &irqL);
-+
-+	#ifdef DBG_XMIT_BLOCK
-+	DBG_XMIT_BLOCK_DUMP(padapter);
-+	#endif
-+}
-+
-+void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason)
-+{
-+	_irqL irqL;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	_enter_critical_bh(&dvobj->xmit_block_lock, &irqL);
-+	dvobj->xmit_block &= ~reason;
-+	_exit_critical_bh(&dvobj->xmit_block_lock, &irqL);
-+
-+	#ifdef DBG_XMIT_BLOCK
-+	DBG_XMIT_BLOCK_DUMP(padapter);
-+	#endif
-+}
-+bool rtw_is_xmit_blocked(_adapter *padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	#ifdef DBG_XMIT_BLOCK
-+	DBG_XMIT_BLOCK_DUMP(padapter);
-+	#endif
-+	return ((dvobj->xmit_block) ? _TRUE : _FALSE);
-+}
-+
-+bool rtw_xmit_ac_blocked(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	_adapter *iface;
-+	struct mlme_ext_priv *mlmeext;
-+	bool blocked = _FALSE;
-+	int i;
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+#ifdef DBG_CONFIG_ERROR_RESET
-+#ifdef CONFIG_USB_HCI
-+	if (rtw_hal_sreset_inprogress(adapter) == _TRUE) {
-+		blocked = _TRUE;
-+		goto exit;
-+	}
-+#endif/* #ifdef CONFIG_USB_HCI */
-+#endif/* #ifdef DBG_CONFIG_ERROR_RESET */
-+#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
-+
-+	if (rfctl->offch_state != OFFCHS_NONE
-+		#if CONFIG_DFS
-+		|| IS_RADAR_DETECTED(rfctl) || rfctl->csa_ch
-+		#endif
-+	) {
-+		blocked = _TRUE;
-+		goto exit;
-+	}
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		mlmeext = &iface->mlmeextpriv;
-+
-+		/* check scan state */
-+		if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE
-+			&& mlmeext_scan_state(mlmeext) != SCAN_BACK_OP
-+		) {
-+			blocked = _TRUE;
-+			goto exit;
-+		}
-+
-+		if (mlmeext_scan_state(mlmeext) == SCAN_BACK_OP
-+			&& !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)
-+		) {
-+			blocked = _TRUE;
-+			goto exit;
-+		}
-+	}
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(adapter)) {
-+		if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
-+			if (MCC_STOP(adapter)) {
-+				blocked = _TRUE;
-+				goto exit;
-+			}
-+		}
-+	}
-+#endif /*  CONFIG_MCC_MODE */
-+
-+exit:
-+	return blocked;
-+}
-+
-+#ifdef CONFIG_TX_AMSDU
-+void rtw_amsdu_vo_timeout_handler(void *FunctionContext)
-+{
-+	_adapter *adapter = (_adapter *)FunctionContext;
-+
-+	adapter->xmitpriv.amsdu_vo_timeout = RTW_AMSDU_TIMER_TIMEOUT;
-+
-+	tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
-+}
-+
-+void rtw_amsdu_vi_timeout_handler(void *FunctionContext)
-+{
-+	_adapter *adapter = (_adapter *)FunctionContext;
-+
-+	adapter->xmitpriv.amsdu_vi_timeout = RTW_AMSDU_TIMER_TIMEOUT;
-+
-+	tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
-+}
-+
-+void rtw_amsdu_be_timeout_handler(void *FunctionContext)
-+{
-+	_adapter *adapter = (_adapter *)FunctionContext;
-+
-+	adapter->xmitpriv.amsdu_be_timeout = RTW_AMSDU_TIMER_TIMEOUT;
-+
-+	if (printk_ratelimit())
-+		RTW_INFO("%s Timeout!\n",__FUNCTION__);
-+
-+	tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
-+}
-+
-+void rtw_amsdu_bk_timeout_handler(void *FunctionContext)
-+{
-+	_adapter *adapter = (_adapter *)FunctionContext;
-+
-+	adapter->xmitpriv.amsdu_bk_timeout = RTW_AMSDU_TIMER_TIMEOUT;
-+
-+	tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
-+}
-+
-+u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority)
-+{
-+	struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
-+
-+	u8 status =  RTW_AMSDU_TIMER_UNSET;
-+
-+	switch(priority)
-+	{
-+		case 1:
-+		case 2:
-+			status = pxmitpriv->amsdu_bk_timeout;
-+			break;
-+		case 4:
-+		case 5:
-+			status = pxmitpriv->amsdu_vi_timeout;
-+			break;
-+		case 6:
-+		case 7:
-+			status = pxmitpriv->amsdu_vo_timeout;
-+			break;
-+		case 0:
-+		case 3:
-+		default:
-+			status = pxmitpriv->amsdu_be_timeout;
-+			break;
-+	}
-+	return status;
-+}
-+
-+void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status)
-+{
-+	struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
-+
-+	switch(priority)
-+	{
-+		case 1:
-+		case 2:
-+			pxmitpriv->amsdu_bk_timeout = status;
-+			break;
-+		case 4:
-+		case 5:
-+			pxmitpriv->amsdu_vi_timeout = status;
-+			break;
-+		case 6:
-+		case 7:
-+			pxmitpriv->amsdu_vo_timeout = status;
-+			break;
-+		case 0:
-+		case 3:
-+		default:
-+			pxmitpriv->amsdu_be_timeout = status;
-+			break;
-+	}
-+}
-+
-+void rtw_amsdu_set_timer(_adapter *padapter, u8 priority)
-+{
-+	struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
-+
-+	_timer* amsdu_timer = NULL;
-+
-+	switch(priority)
-+	{
-+		case 1:
-+		case 2:
-+			amsdu_timer = &pxmitpriv->amsdu_bk_timer;
-+			break;
-+		case 4:
-+		case 5:
-+			amsdu_timer = &pxmitpriv->amsdu_vi_timer;
-+			break;
-+		case 6:
-+		case 7:
-+			amsdu_timer = &pxmitpriv->amsdu_vo_timer;
-+			break;
-+		case 0:
-+		case 3:
-+		default:
-+			amsdu_timer = &pxmitpriv->amsdu_be_timer;
-+			break;
-+	}
-+	_set_timer(amsdu_timer, 1);
-+}
-+
-+void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority)
-+{
-+	struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
-+	_timer* amsdu_timer = NULL;
-+
-+	switch(priority)
-+	{
-+		case 1:
-+		case 2:
-+			amsdu_timer = &pxmitpriv->amsdu_bk_timer;
-+			break;
-+		case 4:
-+		case 5:
-+			amsdu_timer = &pxmitpriv->amsdu_vi_timer;
-+			break;
-+		case 6:
-+		case 7:
-+			amsdu_timer = &pxmitpriv->amsdu_vo_timer;
-+			break;
-+		case 0:
-+		case 3:
-+		default:
-+			amsdu_timer = &pxmitpriv->amsdu_be_timer;
-+			break;
-+	}
-+	_cancel_timer_ex(amsdu_timer);
-+}
-+#endif /* CONFIG_TX_AMSDU */
-+
-+#ifdef DBG_TXBD_DESC_DUMP
-+static struct rtw_tx_desc_backup tx_backup[HW_QUEUE_ENTRY][TX_BAK_FRMAE_CNT];
-+static u8 backup_idx[HW_QUEUE_ENTRY];
-+
-+void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq)
-+{
-+	u32 tmp32;
-+	u8 *pxmit_buf;
-+
-+	if (rtw_get_hw_init_completed(padapter) == _FALSE)
-+		return;
-+
-+	pxmit_buf = pxmitframe->pxmitbuf->pbuf;
-+
-+	_rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_desc, pxmit_buf, desc_size);
-+	_rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_data_hdr, pxmit_buf+desc_size, TX_BAK_DATA_LEN);
-+
-+	tmp32 = rtw_read32(padapter, get_txbd_rw_reg(hwq));
-+
-+	tx_backup[hwq][backup_idx[hwq]].tx_bak_rp = (tmp32>>16)&0xfff;
-+	tx_backup[hwq][backup_idx[hwq]].tx_bak_wp = tmp32&0xfff;
-+
-+	tx_backup[hwq][backup_idx[hwq]].tx_desc_size = desc_size;
-+
-+	backup_idx[hwq] = (backup_idx[hwq] + 1) % TX_BAK_FRMAE_CNT;
-+}
-+
-+void rtw_tx_desc_backup_reset(void)
-+{
-+	int i, j;
-+
-+	for (i = 0; i < HW_QUEUE_ENTRY; i++) {
-+		for (j = 0; j < TX_BAK_FRMAE_CNT; j++)
-+			_rtw_memset(&tx_backup[i][j], 0, sizeof(struct rtw_tx_desc_backup));
-+
-+		backup_idx[i] = 0;
-+	}
-+}
-+
-+u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak)
-+{
-+	*pbak = &tx_backup[hwq][0];
-+
-+	return backup_idx[hwq];
-+}
-+#endif
-+
-+#ifdef CONFIG_PCI_TX_POLLING
-+void rtw_tx_poll_init(_adapter *padapter)
-+{
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	_timer* timer = &pxmitpriv->tx_poll_timer;
-+
-+	if (!is_primary_adapter(padapter))
-+		return;
-+
-+	if (timer->function != NULL) {
-+		RTW_INFO("tx polling timer has been init.\n");
-+		return;
-+	}
-+
-+	rtw_init_timer(timer, padapter, rtw_tx_poll_timeout_handler, padapter);
-+	rtw_tx_poll_timer_set(padapter, 1);
-+	RTW_INFO("Tx poll timer init!\n");
-+}
-+
-+void rtw_tx_poll_timeout_handler(void *FunctionContext)
-+{
-+	_adapter *adapter = (_adapter *)FunctionContext;
-+
-+	rtw_tx_poll_timer_set(adapter, 1);
-+
-+	if (adapter->hal_func.tx_poll_handler)
-+		adapter->hal_func.tx_poll_handler(adapter);
-+	else
-+		RTW_WARN("hal ops: tx_poll_handler is NULL\n");
-+}
-+
-+void rtw_tx_poll_timer_set(_adapter *padapter, u32 delay)
-+{
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	_timer* timer = NULL;
-+
-+	timer = &pxmitpriv->tx_poll_timer;
-+	_set_timer(timer, delay);
-+}
-+
-+void rtw_tx_poll_timer_cancel(_adapter *padapter)
-+{
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	_timer* timer = NULL;
-+
-+	if (!is_primary_adapter(padapter))
-+		return;
-+
-+	timer = &pxmitpriv->tx_poll_timer;
-+	_cancel_timer_ex(timer);
-+	timer->function = NULL;
-+	RTW_INFO("Tx poll timer cancel !\n");
-+}
-+#endif /* CONFIG_PCI_TX_POLLING */
-+
-+void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms)
-+{
-+	sctx->timeout_ms = timeout_ms;
-+	sctx->submit_time = rtw_get_current_time();
-+#ifdef PLATFORM_LINUX /* TODO: add condition wating interface for other os */
-+	init_completion(&sctx->done);
-+#endif
-+	sctx->status = RTW_SCTX_SUBMITTED;
-+}
-+
-+int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg)
-+{
-+	int ret = _FAIL;
-+	unsigned long expire;
-+	int status = 0;
-+
-+#ifdef PLATFORM_LINUX
-+	expire = sctx->timeout_ms ? msecs_to_jiffies(sctx->timeout_ms) : MAX_SCHEDULE_TIMEOUT;
-+	if (!wait_for_completion_timeout(&sctx->done, expire)) {
-+		/* timeout, do something?? */
-+		status = RTW_SCTX_DONE_TIMEOUT;
-+		RTW_INFO("%s timeout: %s\n", __func__, msg);
-+	} else
-+		status = sctx->status;
-+#endif
-+
-+	if (status == RTW_SCTX_DONE_SUCCESS)
-+		ret = _SUCCESS;
-+
-+	return ret;
-+}
-+
-+bool rtw_sctx_chk_waring_status(int status)
-+{
-+	switch (status) {
-+	case RTW_SCTX_DONE_UNKNOWN:
-+	case RTW_SCTX_DONE_BUF_ALLOC:
-+	case RTW_SCTX_DONE_BUF_FREE:
-+
-+	case RTW_SCTX_DONE_DRV_STOP:
-+	case RTW_SCTX_DONE_DEV_REMOVE:
-+		return _TRUE;
-+	default:
-+		return _FALSE;
-+	}
-+}
-+
-+void rtw_sctx_done_err(struct submit_ctx **sctx, int status)
-+{
-+	if (*sctx) {
-+		if (rtw_sctx_chk_waring_status(status))
-+			RTW_INFO("%s status:%d\n", __func__, status);
-+		(*sctx)->status = status;
-+#ifdef PLATFORM_LINUX
-+		complete(&((*sctx)->done));
-+#endif
-+		*sctx = NULL;
-+	}
-+}
-+
-+void rtw_sctx_done(struct submit_ctx **sctx)
-+{
-+	rtw_sctx_done_err(sctx, RTW_SCTX_DONE_SUCCESS);
-+}
-+
-+#ifdef CONFIG_XMIT_ACK
-+int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms)
-+{
-+	struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops;
-+
-+	pack_tx_ops->submit_time = rtw_get_current_time();
-+	pack_tx_ops->timeout_ms = timeout_ms;
-+	pack_tx_ops->status = RTW_SCTX_SUBMITTED;
-+
-+	return rtw_sctx_wait(pack_tx_ops, __func__);
-+}
-+
-+void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status)
-+{
-+	struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops;
-+
-+	if (pxmitpriv->ack_tx)
-+		rtw_sctx_done_err(&pack_tx_ops, status);
-+	else
-+		RTW_INFO("%s ack_tx not set\n", __func__);
-+}
-+#endif /* CONFIG_XMIT_ACK */
-diff --git a/drivers/staging/rtl8723cs/core/wds/rtw_wds.c b/drivers/staging/rtl8723cs/core/wds/rtw_wds.c
-new file mode 100644
-index 000000000000..fd88b1c4fdcf
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/wds/rtw_wds.c
-@@ -0,0 +1,786 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_WDS_C_
-+
-+#include <drv_types.h>
-+
-+#if defined(CONFIG_RTW_WDS)
-+#include <linux/jhash.h>
-+
-+#if defined(CONFIG_AP_MODE)
-+
-+#ifdef PLATFORM_LINUX
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+static void rtw_wpath_free_rcu(struct rtw_wds_path *wpath)
-+{
-+	kfree_rcu(wpath, rcu);
-+	rtw_mstat_update(MSTAT_TYPE_PHY, MSTAT_FREE, sizeof(struct rtw_wds_path));
-+}
-+#else
-+static void rtw_wpath_free_rcu_callback(rtw_rcu_head *head)
-+{
-+	struct rtw_wds_path *wpath;
-+
-+	wpath = container_of(head, struct rtw_wds_path, rcu);
-+	rtw_mfree(wpath, sizeof(struct rtw_wds_path));
-+}
-+
-+static void rtw_wpath_free_rcu(struct rtw_wds_path *wpath)
-+{
-+	call_rcu(&wpath->rcu, rtw_wpath_free_rcu_callback);
-+}
-+#endif
-+#endif /* PLATFORM_LINUX */
-+
-+static void rtw_wds_path_free_rcu(struct rtw_wds_table *tbl, struct rtw_wds_path *wpath);
-+
-+static u32 rtw_wds_table_hash(const void *addr, u32 len, u32 seed)
-+{
-+	/* Use last four bytes of hw addr as hash index */
-+	return jhash_1word(*(u32 *)(addr+2), seed);
-+}
-+
-+static const rtw_rhashtable_params rtw_wds_rht_params = {
-+	.nelem_hint = 2,
-+	.automatic_shrinking = true,
-+	.key_len = ETH_ALEN,
-+	.key_offset = offsetof(struct rtw_wds_path, dst),
-+	.head_offset = offsetof(struct rtw_wds_path, rhash),
-+	.hashfn = rtw_wds_table_hash,
-+};
-+
-+static void rtw_wds_path_rht_free(void *ptr, void *tblptr)
-+{
-+	struct rtw_wds_path *wpath = ptr;
-+	struct rtw_wds_table *tbl = tblptr;
-+
-+	rtw_wds_path_free_rcu(tbl, wpath);
-+}
-+
-+static struct rtw_wds_table *rtw_wds_table_alloc(void)
-+{
-+	struct rtw_wds_table *newtbl;
-+
-+	newtbl = rtw_malloc(sizeof(struct rtw_wds_table));
-+	if (!newtbl)
-+		return NULL;
-+
-+	return newtbl;
-+}
-+
-+static void rtw_wds_table_free(struct rtw_wds_table *tbl)
-+{
-+	rtw_rhashtable_free_and_destroy(&tbl->rhead,
-+				    rtw_wds_path_rht_free, tbl);
-+	rtw_mfree(tbl, sizeof(struct rtw_wds_table));
-+}
-+
-+void rtw_wds_path_assign_nexthop(struct rtw_wds_path *wpath, struct sta_info *sta)
-+{
-+	rtw_rcu_assign_pointer(wpath->next_hop, sta);
-+}
-+
-+static struct rtw_wds_path *rtw_wpath_lookup(struct rtw_wds_table *tbl, const u8 *dst)
-+{
-+	struct rtw_wds_path *wpath;
-+
-+	if (!tbl)
-+		return NULL;
-+
-+	wpath = rtw_rhashtable_lookup_fast(&tbl->rhead, dst, rtw_wds_rht_params);
-+
-+	return wpath;
-+}
-+
-+struct rtw_wds_path *rtw_wds_path_lookup(_adapter *adapter, const u8 *dst)
-+{
-+	return rtw_wpath_lookup(adapter->wds_paths, dst);
-+}
-+
-+static struct rtw_wds_path *
-+__rtw_wds_path_lookup_by_idx(struct rtw_wds_table *tbl, int idx)
-+{
-+	int i = 0, ret;
-+	struct rtw_wds_path *wpath = NULL;
-+	rtw_rhashtable_iter iter;
-+
-+	if (!tbl)
-+		return NULL;
-+
-+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
-+	if (ret)
-+		return NULL;
-+
-+	ret = rtw_rhashtable_walk_start(&iter);
-+	if (ret && ret != -EAGAIN)
-+		goto err;
-+
-+	while ((wpath = rtw_rhashtable_walk_next(&iter))) {
-+		if (IS_ERR(wpath) && PTR_ERR(wpath) == -EAGAIN)
-+			continue;
-+		if (IS_ERR(wpath))
-+			break;
-+		if (i++ == idx)
-+			break;
-+	}
-+err:
-+	rtw_rhashtable_walk_stop(&iter);
-+	rtw_rhashtable_walk_exit(&iter);
-+
-+	if (IS_ERR(wpath) || !wpath)
-+		return NULL;
-+
-+	return wpath;
-+}
-+
-+/**
-+ * Locking: must be called within a read rcu section.
-+ */
-+struct rtw_wds_path *
-+rtw_wds_path_lookup_by_idx(_adapter *adapter, int idx)
-+{
-+	return __rtw_wds_path_lookup_by_idx(adapter->wds_paths, idx);
-+}
-+
-+void dump_wpath(void *sel, _adapter *adapter)
-+{
-+	struct rtw_wds_path *wpath;
-+	int idx = 0;
-+	char dst[ETH_ALEN];
-+	char next_hop[ETH_ALEN];
-+	u32 age_ms;
-+
-+	RTW_PRINT_SEL(sel, "num:%d\n", ATOMIC_READ(&adapter->wds_path_num));
-+	RTW_PRINT_SEL(sel, "%-17s %-17s %-6s\n"
-+		, "dst", "next_hop", "age"
-+	);
-+
-+	do {
-+		rtw_rcu_read_lock();
-+
-+		wpath = rtw_wds_path_lookup_by_idx(adapter, idx);
-+		if (wpath) {
-+			_rtw_memcpy(dst, wpath->dst, ETH_ALEN);
-+			_rtw_memcpy(next_hop, wpath->next_hop->cmn.mac_addr, ETH_ALEN);
-+			age_ms = rtw_get_passing_time_ms(wpath->last_update);
-+		}
-+
-+		rtw_rcu_read_unlock();
-+
-+		if (wpath) {
-+			RTW_PRINT_SEL(sel, MAC_FMT" "MAC_FMT" %6u\n"
-+				, MAC_ARG(dst), MAC_ARG(next_hop)
-+				, age_ms < 999999 ? age_ms : 999999
-+			);
-+		}
-+
-+		idx++;
-+	} while (wpath);
-+}
-+
-+static
-+struct rtw_wds_path *rtw_wds_path_new(_adapter *adapter,
-+				const u8 *dst)
-+{
-+	struct rtw_wds_path *new_wpath;
-+
-+	new_wpath = rtw_zmalloc(sizeof(struct rtw_wds_path));
-+	if (!new_wpath)
-+		return NULL;
-+
-+	new_wpath->adapter = adapter;
-+	_rtw_memcpy(new_wpath->dst, dst, ETH_ALEN);
-+	new_wpath->last_update = rtw_get_current_time();
-+
-+	return new_wpath;
-+}
-+
-+/**
-+ * Returns: 0 on success
-+ *
-+ * State: the initial state of the new path is set to 0
-+ */
-+struct rtw_wds_path *rtw_wds_path_add(_adapter *adapter,
-+	const u8 *dst, struct sta_info *next_hop)
-+{
-+	struct rtw_wds_table *tbl = adapter->wds_paths;
-+	struct rtw_wds_path *wpath, *new_wpath;
-+	int ret;
-+
-+	if (!tbl)
-+		return ERR_PTR(-ENOTSUPP);
-+
-+	if (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
-+		/* never add ourselves as neighbours */
-+		return ERR_PTR(-ENOTSUPP);
-+
-+	if (IS_MCAST(dst))
-+		return ERR_PTR(-ENOTSUPP);
-+
-+	if (ATOMIC_INC_UNLESS(&adapter->wds_path_num, RTW_WDS_MAX_PATHS) == 0)
-+		return ERR_PTR(-ENOSPC);
-+
-+	new_wpath = rtw_wds_path_new(adapter, dst);
-+	if (!new_wpath)
-+		return ERR_PTR(-ENOMEM);
-+
-+	do {
-+		ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead,
-+						    &new_wpath->rhash,
-+						    rtw_wds_rht_params);
-+
-+		if (ret == -EEXIST)
-+			wpath = rtw_rhashtable_lookup_fast(&tbl->rhead,
-+						       dst,
-+						       rtw_wds_rht_params);
-+
-+	} while (unlikely(ret == -EEXIST && !wpath));
-+
-+	if (ret && ret != -EEXIST)
-+		return ERR_PTR(ret);
-+
-+	/* At this point either new_wpath was added, or we found a
-+	 * matching entry already in the table; in the latter case
-+	 * free the unnecessary new entry.
-+	 */
-+	if (ret == -EEXIST) {
-+		rtw_mfree(new_wpath, sizeof(struct rtw_wds_path));
-+		new_wpath = wpath;
-+	}
-+	rtw_wds_path_assign_nexthop(new_wpath, next_hop);
-+
-+	return new_wpath;
-+}
-+
-+static void rtw_wds_path_free_rcu(struct rtw_wds_table *tbl,
-+			       struct rtw_wds_path *wpath)
-+{
-+	_adapter *adapter = wpath->adapter;
-+
-+	ATOMIC_DEC(&adapter->wds_path_num);
-+
-+	rtw_wpath_free_rcu(wpath);
-+}
-+
-+static void __rtw_wds_path_del(struct rtw_wds_table *tbl, struct rtw_wds_path *wpath)
-+{
-+	rtw_rhashtable_remove_fast(&tbl->rhead, &wpath->rhash, rtw_wds_rht_params);
-+	rtw_wds_path_free_rcu(tbl, wpath);
-+}
-+
-+void rtw_wds_path_flush_by_nexthop(struct sta_info *sta)
-+{
-+	_adapter *adapter = sta->padapter;
-+	struct rtw_wds_table *tbl = adapter->wds_paths;
-+	struct rtw_wds_path *wpath;
-+	rtw_rhashtable_iter iter;
-+	int ret;
-+
-+	if (!tbl)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
-+	if (ret)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_start(&iter);
-+	if (ret && ret != -EAGAIN)
-+		goto out;
-+
-+	while ((wpath = rtw_rhashtable_walk_next(&iter))) {
-+		if (IS_ERR(wpath) && PTR_ERR(wpath) == -EAGAIN)
-+			continue;
-+		if (IS_ERR(wpath))
-+			break;
-+
-+		if (rtw_rcu_access_pointer(wpath->next_hop) == sta)
-+			__rtw_wds_path_del(tbl, wpath);
-+	}
-+out:
-+	rtw_rhashtable_walk_stop(&iter);
-+	rtw_rhashtable_walk_exit(&iter);
-+}
-+
-+static void rtw_wds_table_flush_by_iface(struct rtw_wds_table *tbl)
-+{
-+	struct rtw_wds_path *wpath;
-+	rtw_rhashtable_iter iter;
-+	int ret;
-+
-+	if (!tbl)
-+		return;
-+	
-+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
-+	if (ret)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_start(&iter);
-+	if (ret && ret != -EAGAIN)
-+		goto out;
-+
-+	while ((wpath = rtw_rhashtable_walk_next(&iter))) {
-+		if (IS_ERR(wpath) && PTR_ERR(wpath) == -EAGAIN)
-+			continue;
-+		if (IS_ERR(wpath))
-+			break;
-+		__rtw_wds_path_del(tbl, wpath);
-+	}
-+out:
-+	rtw_rhashtable_walk_stop(&iter);
-+	rtw_rhashtable_walk_exit(&iter);
-+}
-+
-+void rtw_wds_path_flush_by_iface(_adapter *adapter)
-+{
-+	rtw_wds_table_flush_by_iface(adapter->wds_paths);
-+}
-+
-+static int rtw_wds_table_path_del(struct rtw_wds_table *tbl,
-+			  const u8 *addr)
-+{
-+	struct rtw_wds_path *wpath;
-+
-+	if (!tbl)
-+		return -ENXIO;
-+
-+	rtw_rcu_read_lock();
-+	wpath = rtw_rhashtable_lookup_fast(&tbl->rhead, addr, rtw_wds_rht_params);
-+	if (!wpath) {
-+		rtw_rcu_read_unlock();
-+		return -ENXIO;
-+	}
-+
-+	__rtw_wds_path_del(tbl, wpath);
-+	rtw_rcu_read_unlock();
-+	return 0;
-+}
-+
-+int rtw_wds_path_del(_adapter *adapter, const u8 *addr)
-+{
-+	int err;
-+
-+	err = rtw_wds_table_path_del(adapter->wds_paths, addr);
-+	return err;
-+}
-+
-+int rtw_wds_pathtbl_init(_adapter *adapter)
-+{
-+	struct rtw_wds_table *tbl_path;
-+	int ret;
-+
-+	tbl_path = rtw_wds_table_alloc();
-+	if (!tbl_path)
-+		return -ENOMEM;
-+
-+	rtw_rhashtable_init(&tbl_path->rhead, &rtw_wds_rht_params);
-+
-+	ATOMIC_SET(&adapter->wds_path_num, 0);
-+	adapter->wds_paths = tbl_path;
-+
-+	return 0;
-+}
-+
-+static
-+void rtw_wds_path_tbl_expire(_adapter *adapter,
-+			  struct rtw_wds_table *tbl)
-+{
-+	struct rtw_wds_path *wpath;
-+	rtw_rhashtable_iter iter;
-+	int ret;
-+
-+	if (!tbl)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
-+	if (ret)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_start(&iter);
-+	if (ret && ret != -EAGAIN)
-+		goto out;
-+
-+	while ((wpath = rtw_rhashtable_walk_next(&iter))) {
-+		if (IS_ERR(wpath) && PTR_ERR(wpath) == -EAGAIN)
-+			continue;
-+		if (IS_ERR(wpath))
-+			break;
-+		if (rtw_time_after(rtw_get_current_time(), wpath->last_update + RTW_WDS_PATH_EXPIRE))
-+			__rtw_wds_path_del(tbl, wpath);
-+	}
-+
-+out:
-+	rtw_rhashtable_walk_stop(&iter);
-+	rtw_rhashtable_walk_exit(&iter);
-+}
-+
-+void rtw_wds_path_expire(_adapter *adapter)
-+{
-+	rtw_wds_path_tbl_expire(adapter, adapter->wds_paths);
-+}
-+
-+void rtw_wds_pathtbl_unregister(_adapter *adapter)
-+{
-+	if (adapter->wds_paths) {
-+		rtw_wds_table_free(adapter->wds_paths);
-+		adapter->wds_paths = NULL;
-+	}
-+}
-+
-+int rtw_wds_nexthop_lookup(_adapter *adapter, const u8 *da, u8 *ra)
-+{
-+	struct rtw_wds_path *wpath;
-+	struct sta_info *next_hop;
-+	int err = -ENOENT;
-+
-+	rtw_rcu_read_lock();
-+	wpath = rtw_wds_path_lookup(adapter, da);
-+
-+	if (!wpath)
-+		goto endlookup;
-+
-+	next_hop = rtw_rcu_dereference(wpath->next_hop);
-+	if (next_hop) {
-+		_rtw_memcpy(ra, next_hop->cmn.mac_addr, ETH_ALEN);
-+		err = 0;
-+	}
-+
-+endlookup:
-+	rtw_rcu_read_unlock();
-+	return err;
-+}
-+
-+#endif /* defined(CONFIG_AP_MODE) */
-+
-+/* WDS group adddressed proxy TX record */
-+struct rtw_wds_gptr {
-+	u8 src[ETH_ALEN];
-+	systime last_update;
-+	rtw_rhash_head rhash;
-+	_adapter *adapter;
-+	rtw_rcu_head rcu;
-+};
-+
-+#define RTW_WDS_GPTR_EXPIRE (2 * HZ)
-+
-+/* Maximum number of gptrs per interface */
-+#define RTW_WDS_MAX_GPTRS		1024
-+
-+#ifdef PLATFORM_LINUX
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+static void rtw_wgptr_free_rcu(struct rtw_wds_gptr *wgptr)
-+{
-+	kfree_rcu(wgptr, rcu);
-+	rtw_mstat_update(MSTAT_TYPE_PHY, MSTAT_FREE, sizeof(struct rtw_wds_gptr));
-+}
-+#else
-+static void rtw_wgptr_free_rcu_callback(rtw_rcu_head *head)
-+{
-+	struct rtw_wds_gptr *wgptr;
-+
-+	wgptr = container_of(head, struct rtw_wds_gptr, rcu);
-+	rtw_mfree(wgptr, sizeof(struct rtw_wds_gptr));
-+}
-+
-+static void rtw_wgptr_free_rcu(struct rtw_wds_gptr *wgptr)
-+{
-+	call_rcu(&wgptr->rcu, rtw_wgptr_free_rcu_callback);
-+}
-+#endif
-+#endif /* PLATFORM_LINUX */
-+
-+static void rtw_wds_gptr_free_rcu(struct rtw_wds_gptr_table *tbl, struct rtw_wds_gptr *wgptr)
-+{
-+	_adapter *adapter = wgptr->adapter;
-+
-+	ATOMIC_DEC(&adapter->wds_gpt_record_num);
-+
-+	rtw_wgptr_free_rcu(wgptr);
-+}
-+
-+static u32 rtw_wds_gptr_table_hash(const void *addr, u32 len, u32 seed)
-+{
-+	/* Use last four bytes of hw addr as hash index */
-+	return jhash_1word(*(u32 *)(addr+2), seed);
-+}
-+
-+static const rtw_rhashtable_params rtw_wds_gptr_rht_params = {
-+	.nelem_hint = 2,
-+	.automatic_shrinking = true,
-+	.key_len = ETH_ALEN,
-+	.key_offset = offsetof(struct rtw_wds_gptr, src),
-+	.head_offset = offsetof(struct rtw_wds_gptr, rhash),
-+	.hashfn = rtw_wds_gptr_table_hash,
-+};
-+
-+static void rtw_wds_gptr_rht_free(void *ptr, void *tblptr)
-+{
-+	struct rtw_wds_gptr *wgptr = ptr;
-+	struct rtw_wds_gptr_table *tbl = tblptr;
-+
-+	rtw_wds_gptr_free_rcu(tbl, wgptr);
-+}
-+
-+static struct rtw_wds_gptr_table *rtw_wds_gptr_table_alloc(void)
-+{
-+	struct rtw_wds_gptr_table *newtbl;
-+
-+	newtbl = rtw_malloc(sizeof(struct rtw_wds_gptr_table));
-+	if (!newtbl)
-+		return NULL;
-+
-+	return newtbl;
-+}
-+
-+static void rtw_wds_gptr_table_free(struct rtw_wds_gptr_table *tbl)
-+{
-+	rtw_rhashtable_free_and_destroy(&tbl->rhead,
-+				    rtw_wds_gptr_rht_free, tbl);
-+	rtw_mfree(tbl, sizeof(struct rtw_wds_gptr_table));
-+}
-+
-+static struct rtw_wds_gptr *rtw_wds_gptr_lookup(_adapter *adapter, const u8 *src)
-+{
-+	struct rtw_wds_gptr_table *tbl = adapter->wds_gpt_records;
-+
-+	if (!tbl)
-+		return NULL;
-+
-+	return rtw_rhashtable_lookup_fast(&tbl->rhead, src, rtw_wds_gptr_rht_params);
-+}
-+
-+/**
-+ * Locking: must be called within a read rcu section.
-+ */
-+static struct rtw_wds_gptr *rtw_wds_gptr_lookup_by_idx(_adapter *adapter, int idx)
-+{
-+	int i = 0, ret;
-+	struct rtw_wds_gptr_table *tbl = adapter->wds_gpt_records;
-+	struct rtw_wds_gptr *wgptr = NULL;
-+	rtw_rhashtable_iter iter;
-+
-+	if (!tbl)
-+		return NULL;
-+
-+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
-+	if (ret)
-+		return NULL;
-+
-+	ret = rtw_rhashtable_walk_start(&iter);
-+	if (ret && ret != -EAGAIN)
-+		goto err;
-+
-+	while ((wgptr = rtw_rhashtable_walk_next(&iter))) {
-+		if (IS_ERR(wgptr) && PTR_ERR(wgptr) == -EAGAIN)
-+			continue;
-+		if (IS_ERR(wgptr))
-+			break;
-+		if (i++ == idx)
-+			break;
-+	}
-+err:
-+	rtw_rhashtable_walk_stop(&iter);
-+	rtw_rhashtable_walk_exit(&iter);
-+
-+	if (IS_ERR(wgptr) || !wgptr)
-+		return NULL;
-+
-+	return wgptr;
-+}
-+
-+void dump_wgptr(void *sel, _adapter *adapter)
-+{
-+	struct rtw_wds_gptr *wgptr;
-+	int idx = 0;
-+	char src[ETH_ALEN];
-+	u32 age_ms;
-+
-+	RTW_PRINT_SEL(sel, "num:%d\n", ATOMIC_READ(&adapter->wds_gpt_record_num));
-+	RTW_PRINT_SEL(sel, "%-17s %-6s\n"
-+		, "src", "age"
-+	);
-+
-+	do {
-+		rtw_rcu_read_lock();
-+
-+		wgptr = rtw_wds_gptr_lookup_by_idx(adapter, idx);
-+		if (wgptr) {
-+			_rtw_memcpy(src, wgptr->src, ETH_ALEN);
-+			age_ms = rtw_get_passing_time_ms(wgptr->last_update);
-+		}
-+
-+		rtw_rcu_read_unlock();
-+
-+		if (wgptr) {
-+			RTW_PRINT_SEL(sel, MAC_FMT" %6u\n"
-+				, MAC_ARG(src)
-+				, age_ms < 999999 ? age_ms : 999999
-+			);
-+		}
-+
-+		idx++;
-+	} while (wgptr);
-+}
-+
-+static struct rtw_wds_gptr *rtw_wds_gptr_new(_adapter *adapter, const u8 *src)
-+{
-+	struct rtw_wds_gptr *new_wgptr;
-+
-+	new_wgptr = rtw_zmalloc(sizeof(struct rtw_wds_gptr));
-+	if (!new_wgptr)
-+		return NULL;
-+
-+	new_wgptr->adapter = adapter;
-+	_rtw_memcpy(new_wgptr->src, src, ETH_ALEN);
-+	new_wgptr->last_update = rtw_get_current_time();
-+
-+	return new_wgptr;
-+}
-+
-+static struct rtw_wds_gptr *rtw_wds_gptr_add(_adapter *adapter, const u8 *src)
-+{
-+	struct rtw_wds_gptr_table *tbl = adapter->wds_gpt_records;
-+	struct rtw_wds_gptr *wgptr, *new_wgptr;
-+	int ret;
-+
-+	if (!tbl)
-+		return ERR_PTR(-ENOTSUPP);
-+
-+	if (ATOMIC_INC_UNLESS(&adapter->wds_gpt_record_num, RTW_WDS_MAX_PATHS) == 0)
-+		return ERR_PTR(-ENOSPC);
-+
-+	new_wgptr = rtw_wds_gptr_new(adapter, src);
-+	if (!new_wgptr)
-+		return ERR_PTR(-ENOMEM);
-+
-+	do {
-+		ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead,
-+						    &new_wgptr->rhash,
-+						    rtw_wds_gptr_rht_params);
-+
-+		if (ret == -EEXIST)
-+			wgptr = rtw_rhashtable_lookup_fast(&tbl->rhead,
-+						       src,
-+						       rtw_wds_gptr_rht_params);
-+
-+	} while (unlikely(ret == -EEXIST && !wgptr));
-+
-+	if (ret && ret != -EEXIST)
-+		return ERR_PTR(ret);
-+
-+	/* At this point either new_wgptr was added, or we found a
-+	 * matching entry already in the table; in the latter case
-+	 * free the unnecessary new entry.
-+	 */
-+	if (ret == -EEXIST) {
-+		rtw_mfree(new_wgptr, sizeof(struct rtw_wds_gptr));
-+		new_wgptr = wgptr;
-+	}
-+
-+	return new_wgptr;
-+}
-+
-+bool rtw_rx_wds_gptr_check(_adapter *adapter, const u8 *src)
-+{
-+	struct rtw_wds_gptr *wgptr;
-+	bool ret = 0;
-+
-+	rtw_rcu_read_lock();
-+
-+	wgptr = rtw_wds_gptr_lookup(adapter, src);
-+	if (wgptr)
-+		ret = rtw_time_after(wgptr->last_update + RTW_WDS_GPTR_EXPIRE, rtw_get_current_time());
-+
-+	rtw_rcu_read_unlock();
-+
-+	return ret;
-+}
-+
-+void rtw_tx_wds_gptr_update(_adapter *adapter, const u8 *src)
-+{
-+	struct rtw_wds_gptr *wgptr;
-+
-+	rtw_rcu_read_lock();
-+	wgptr = rtw_wds_gptr_lookup(adapter, src);
-+	if (!wgptr)
-+		rtw_wds_gptr_add(adapter, src);
-+	else
-+		wgptr->last_update = rtw_get_current_time();
-+	rtw_rcu_read_unlock();
-+}
-+
-+static void __rtw_wds_gptr_del(struct rtw_wds_gptr_table *tbl, struct rtw_wds_gptr *wgptr)
-+{
-+	rtw_rhashtable_remove_fast(&tbl->rhead, &wgptr->rhash, rtw_wds_gptr_rht_params);
-+	rtw_wds_gptr_free_rcu(tbl, wgptr);
-+}
-+
-+void rtw_wds_gptr_expire(_adapter *adapter)
-+{
-+	struct rtw_wds_gptr_table *tbl = adapter->wds_gpt_records;
-+	struct rtw_wds_gptr *wgptr;
-+	rtw_rhashtable_iter iter;
-+	int ret;
-+
-+	if (!tbl)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
-+	if (ret)
-+		return;
-+
-+	ret = rtw_rhashtable_walk_start(&iter);
-+	if (ret && ret != -EAGAIN)
-+		goto out;
-+
-+	while ((wgptr = rtw_rhashtable_walk_next(&iter))) {
-+		if (IS_ERR(wgptr) && PTR_ERR(wgptr) == -EAGAIN)
-+			continue;
-+		if (IS_ERR(wgptr))
-+			break;
-+		if (rtw_time_after(rtw_get_current_time(), wgptr->last_update + RTW_WDS_GPTR_EXPIRE))
-+			__rtw_wds_gptr_del(tbl, wgptr);
-+	}
-+
-+out:
-+	rtw_rhashtable_walk_stop(&iter);
-+	rtw_rhashtable_walk_exit(&iter);
-+}
-+
-+int rtw_wds_gptr_tbl_init(_adapter *adapter)
-+{
-+	struct rtw_wds_gptr_table *tbl;
-+	int ret;
-+
-+	tbl = rtw_wds_gptr_table_alloc();
-+	if (!tbl)
-+		return -ENOMEM;
-+
-+	rtw_rhashtable_init(&tbl->rhead, &rtw_wds_gptr_rht_params);
-+
-+	ATOMIC_SET(&adapter->wds_gpt_record_num, 0);
-+	adapter->wds_gpt_records = tbl;
-+
-+	return 0;
-+}
-+
-+void rtw_wds_gptr_tbl_unregister(_adapter *adapter)
-+{
-+	if (adapter->wds_gpt_records) {
-+		rtw_wds_gptr_table_free(adapter->wds_gpt_records);
-+		adapter->wds_gpt_records = NULL;
-+	}
-+}
-+#endif /* defined(CONFIG_RTW_WDS) */
-+
-diff --git a/drivers/staging/rtl8723cs/core/wds/rtw_wds.h b/drivers/staging/rtl8723cs/core/wds/rtw_wds.h
-new file mode 100644
-index 000000000000..f1312c740107
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/core/wds/rtw_wds.h
-@@ -0,0 +1,65 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_WDS_H_
-+#define __RTW_WDS_H_
-+
-+#ifdef CONFIG_AP_MODE
-+struct rtw_wds_path {
-+	u8 dst[ETH_ALEN];
-+	rtw_rhash_head rhash;
-+	_adapter *adapter;
-+	struct sta_info __rcu *next_hop;
-+	rtw_rcu_head rcu;
-+	systime last_update;
-+};
-+
-+struct rtw_wds_table {
-+	rtw_rhashtable rhead;
-+};
-+
-+#define RTW_WDS_PATH_EXPIRE (600 * HZ)
-+
-+/* Maximum number of paths per interface */
-+#define RTW_WDS_MAX_PATHS		1024
-+
-+int rtw_wds_nexthop_lookup(_adapter *adapter, const u8 *da, u8 *ra);
-+
-+struct rtw_wds_path *rtw_wds_path_lookup(_adapter *adapter, const u8 *dst);
-+void dump_wpath(void *sel, _adapter *adapter);
-+
-+void rtw_wds_path_expire(_adapter *adapter);
-+
-+struct rtw_wds_path *rtw_wds_path_add(_adapter *adapter, const u8 *dst, struct sta_info *next_hop);
-+void rtw_wds_path_assign_nexthop(struct rtw_wds_path *path, struct sta_info *sta);
-+
-+int rtw_wds_pathtbl_init(_adapter *adapter);
-+void rtw_wds_pathtbl_unregister(_adapter *adapter);
-+
-+void rtw_wds_path_flush_by_nexthop(struct sta_info *sta);
-+#endif /* CONFIG_AP_MODE */
-+
-+struct rtw_wds_gptr_table {
-+	rtw_rhashtable rhead;
-+};
-+
-+void dump_wgptr(void *sel, _adapter *adapter);
-+bool rtw_rx_wds_gptr_check(_adapter *adapter, const u8 *src);
-+void rtw_tx_wds_gptr_update(_adapter *adapter, const u8 *src);
-+void rtw_wds_gptr_expire(_adapter *adapter);
-+int rtw_wds_gptr_tbl_init(_adapter *adapter);
-+void rtw_wds_gptr_tbl_unregister(_adapter *adapter);
-+
-+#endif /* __RTW_WDSH_ */
-+
-diff --git a/drivers/staging/rtl8723cs/hal/HalPwrSeqCmd.c b/drivers/staging/rtl8723cs/hal/HalPwrSeqCmd.c
-new file mode 100644
-index 000000000000..389785c2bfe4
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/HalPwrSeqCmd.c
-@@ -0,0 +1,185 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*++
-+Copyright (c) Realtek Semiconductor Corp. All rights reserved.
-+
-+Module Name:
-+	HalPwrSeqCmd.c
-+
-+Abstract:
-+	Implement HW Power sequence configuration CMD handling routine for Realtek devices.
-+
-+Major Change History:
-+	When       Who               What
-+	---------- ---------------   -------------------------------
-+	2011-10-26 Lucas            Modify to be compatible with SD4-CE driver.
-+	2011-07-07 Roger            Create.
-+
-+--*/
-+#include <HalPwrSeqCmd.h>
-+
-+
-+/*
-+ *	Description:
-+ *		This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
-+ *
-+ *	Assumption:
-+ *		We should follow specific format which was released from HW SD.
-+ *
-+ *	2011.07.07, added by Roger.
-+ *   */
-+u8 HalPwrSeqCmdParsing(
-+	PADAPTER		padapter,
-+	u8				CutVersion,
-+	u8				FabVersion,
-+	u8				InterfaceType,
-+	WLAN_PWR_CFG	PwrSeqCmd[])
-+{
-+	WLAN_PWR_CFG	PwrCfgCmd = {0};
-+	u8				bPollingBit = _FALSE;
-+	u8				bHWICSupport = _FALSE;
-+	u32				AryIdx = 0;
-+	u8				value = 0;
-+	u32				offset = 0;
-+	u8				flag = 0;
-+	u32				pollingCount = 0; /* polling autoload done. */
-+	u32				maxPollingCnt = 5000;
-+
-+	do {
-+		PwrCfgCmd = PwrSeqCmd[AryIdx];
-+
-+
-+		/* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
-+		if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
-+		    (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
-+		    (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
-+			switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
-+			case PWR_CMD_READ:
-+				break;
-+
-+			case PWR_CMD_WRITE:
-+				offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
-+
-+#ifdef CONFIG_SDIO_HCI
-+				/*  */
-+				/* <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
-+				/* 2011.07.07. */
-+				/*  */
-+				if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
-+					/* Read Back SDIO Local value */
-+					value = SdioLocalCmd52Read1Byte(padapter, offset);
-+
-+					value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
-+					value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
-+
-+					/* Write Back SDIO Local value */
-+					SdioLocalCmd52Write1Byte(padapter, offset, value);
-+				} else
-+#endif
-+				{
-+#ifdef CONFIG_GSPI_HCI
-+					if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
-+						offset = SPI_LOCAL_OFFSET | offset;
-+#endif
-+					/* Read the value from system register */
-+					value = rtw_read8(padapter, offset);
-+
-+					value = value & (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
-+					value = value | (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
-+
-+					/* Write the value back to sytem register */
-+					rtw_write8(padapter, offset, value);
-+				}
-+				break;
-+
-+			case PWR_CMD_POLLING:
-+
-+				bPollingBit = _FALSE;
-+				offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
-+
-+				rtw_hal_get_hwreg(padapter, HW_VAR_PWR_CMD, &bHWICSupport);
-+				if (bHWICSupport && offset == 0x06) {
-+					flag = 0;
-+					maxPollingCnt = 100000;
-+				} else
-+					maxPollingCnt = 5000;
-+
-+#ifdef CONFIG_GSPI_HCI
-+				if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
-+					offset = SPI_LOCAL_OFFSET | offset;
-+#endif
-+				do {
-+#ifdef CONFIG_SDIO_HCI
-+					if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
-+						value = SdioLocalCmd52Read1Byte(padapter, offset);
-+					else
-+#endif
-+						value = rtw_read8(padapter, offset);
-+
-+					value = value & GET_PWR_CFG_MASK(PwrCfgCmd);
-+					if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
-+						bPollingBit = _TRUE;
-+					else
-+						rtw_udelay_os(10);
-+
-+					if (pollingCount++ > maxPollingCnt) {
-+						RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
-+
-+						/* For PCIE + USB package poll power bit timeout issue only modify 8821AE and 8723BE */
-+						if (bHWICSupport && offset == 0x06  && flag == 0) {
-+
-+							RTW_ERR("[WARNING] PCIE polling(0x%X) timeout(%d), Toggle 0x04[3] and try again.\n", offset, maxPollingCnt);
-+							if (IS_HARDWARE_TYPE_8723DE(padapter))
-+								PlatformEFIOWrite1Byte(padapter, 0x40, (PlatformEFIORead1Byte(padapter, 0x40)) & (~BIT3));
-+
-+							PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) | BIT3);
-+							PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) & ~BIT3);
-+
-+							if (IS_HARDWARE_TYPE_8723DE(padapter))
-+								PlatformEFIOWrite1Byte(padapter, 0x40, PlatformEFIORead1Byte(padapter, 0x40)|BIT3);
-+
-+							/* Retry Polling Process one more time */
-+							pollingCount = 0;
-+							flag = 1;
-+						} else {
-+							return _FALSE;
-+						}
-+					}
-+				} while (!bPollingBit);
-+
-+				break;
-+
-+			case PWR_CMD_DELAY:
-+				if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
-+					rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
-+				else
-+					rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000);
-+				break;
-+
-+			case PWR_CMD_END:
-+				/* When this command is parsed, end the process */
-+				return _TRUE;
-+				break;
-+
-+			default:
-+				break;
-+			}
-+		}
-+
-+		AryIdx++;/* Add Array Index */
-+	} while (1);
-+
-+	return _TRUE;
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/btc/btc_basic_types.h b/drivers/staging/rtl8723cs/hal/btc/btc_basic_types.h
-new file mode 100644
-index 000000000000..c2a27a264218
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/btc/btc_basic_types.h
-@@ -0,0 +1,53 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __BTC_BASIC_TYPES_H__
-+#define __BTC_BASIC_TYPES_H__
-+
-+#define IN
-+#define OUT
-+#define VOID void
-+typedef void *PVOID;
-+
-+#define u1Byte		u8
-+#define pu1Byte		u8*
-+
-+#define u2Byte		u16
-+#define pu2Byte		u16*
-+
-+#define u4Byte		u32
-+#define pu4Byte		u32*
-+
-+#define u8Byte		u64
-+#define pu8Byte		u64*
-+
-+#define s1Byte		s8
-+#define ps1Byte		s8*
-+
-+#define s2Byte		s16
-+#define ps2Byte		s16*
-+
-+#define s4Byte		s32
-+#define ps4Byte		s32*
-+
-+#define s8Byte		s64
-+#define ps8Byte		s64*
-+
-+#define UCHAR u8
-+#define USHORT u16
-+#define UINT u32
-+#define ULONG u32
-+#define PULONG u32*
-+
-+#endif /* __BTC_BASIC_TYPES_H__ */
-diff --git a/drivers/staging/rtl8723cs/hal/btc/halbtc8703b1ant.c b/drivers/staging/rtl8723cs/hal/btc/halbtc8703b1ant.c
-new file mode 100644
-index 000000000000..a7334eae6145
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/btc/halbtc8703b1ant.c
-@@ -0,0 +1,4622 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/* ************************************************************
-+ * Description:
-+ *
-+ * This file is for RTL8703B Co-exist mechanism
-+ *
-+ * History
-+ * 2012/11/15 Cosa first check in.
-+ *
-+ * ************************************************************ */
-+
-+/* ************************************************************
-+ * include files
-+ * ************************************************************ */
-+#include "mp_precomp.h"
-+
-+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-+
-+#if (RTL8703B_SUPPORT == 1)
-+/* ************************************************************
-+ * Global variables, these are static variables
-+ * ************************************************************ */
-+static u8	*trace_buf = &gl_btc_trace_buf[0];
-+static struct  coex_dm_8703b_1ant		glcoex_dm_8703b_1ant;
-+static struct  coex_dm_8703b_1ant	*coex_dm = &glcoex_dm_8703b_1ant;
-+static struct  coex_sta_8703b_1ant		glcoex_sta_8703b_1ant;
-+static struct  coex_sta_8703b_1ant	*coex_sta = &glcoex_sta_8703b_1ant;
-+static struct  psdscan_sta_8703b_1ant	gl_psd_scan_8703b_1ant;
-+static struct  psdscan_sta_8703b_1ant *psd_scan = &gl_psd_scan_8703b_1ant;
-+
-+
-+const char *const glbt_info_src_8703b_1ant[] = {
-+	"BT Info[wifi fw]",
-+	"BT Info[bt rsp]",
-+	"BT Info[bt auto report]",
-+};
-+/* ************************************************************
-+ * BtCoex Version Format:
-+ * 1. date :			glcoex_ver_date_XXXXX_1ant
-+ * 2. WifiCoexVersion : glcoex_ver_XXXX_1ant
-+ * 3. BtCoexVersion :	glcoex_ver_btdesired_XXXXX_1ant
-+ * 4. others :			glcoex_ver_XXXXXX_XXXXX_1ant
-+ *
-+ * Variable should be indicated IC and Antenna numbers !!!
-+ * Please strictly follow this order and naming style !!!
-+ *
-+ * ************************************************************ */
-+u32	glcoex_ver_date_8703b_1ant = 20180330;
-+u32	glcoex_ver_8703b_1ant = 0x1e;
-+u32	glcoex_ver_btdesired_8703b_1ant = 0x1c;
-+
-+
-+/* ************************************************************
-+ * local function proto type if needed
-+ * ************************************************************
-+ * ************************************************************
-+ * local function start with halbtc8703b1ant_
-+ * ************************************************************ */
-+u8 halbtc8703b1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
-+{
-+	s32			bt_rssi = 0;
-+	u8			bt_rssi_state = coex_sta->pre_bt_rssi_state;
-+
-+	bt_rssi = coex_sta->bt_rssi;
-+
-+	if (level_num == 2) {
-+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
-+		    (coex_sta->pre_bt_rssi_state ==
-+		     BTC_RSSI_STATE_STAY_LOW)) {
-+			if (bt_rssi >= (rssi_thresh +
-+					BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
-+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
-+			else
-+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
-+		} else {
-+			if (bt_rssi < rssi_thresh)
-+				bt_rssi_state = BTC_RSSI_STATE_LOW;
-+			else
-+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
-+		}
-+	} else if (level_num == 3) {
-+		if (rssi_thresh > rssi_thresh1) {
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				    "[BTCoex], BT Rssi thresh error!!\n");
-+			BTC_TRACE(trace_buf);
-+			return coex_sta->pre_bt_rssi_state;
-+		}
-+
-+		if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
-+		    (coex_sta->pre_bt_rssi_state ==
-+		     BTC_RSSI_STATE_STAY_LOW)) {
-+			if (bt_rssi >= (rssi_thresh +
-+					BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
-+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
-+			else
-+				bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
-+		} else if ((coex_sta->pre_bt_rssi_state ==
-+			    BTC_RSSI_STATE_MEDIUM) ||
-+			   (coex_sta->pre_bt_rssi_state ==
-+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
-+			if (bt_rssi >= (rssi_thresh1 +
-+					BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
-+				bt_rssi_state = BTC_RSSI_STATE_HIGH;
-+			else if (bt_rssi < rssi_thresh)
-+				bt_rssi_state = BTC_RSSI_STATE_LOW;
-+			else
-+				bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
-+		} else {
-+			if (bt_rssi < rssi_thresh1)
-+				bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
-+			else
-+				bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
-+		}
-+	}
-+
-+	coex_sta->pre_bt_rssi_state = bt_rssi_state;
-+
-+	return bt_rssi_state;
-+}
-+
-+u8 halbtc8703b1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
-+	   IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
-+{
-+	s32			wifi_rssi = 0;
-+	u8			wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-+
-+	if (level_num == 2) {
-+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
-+		    ||
-+		    (coex_sta->pre_wifi_rssi_state[index] ==
-+		     BTC_RSSI_STATE_STAY_LOW)) {
-+			if (wifi_rssi >= (rssi_thresh +
-+					  BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
-+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
-+			else
-+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
-+		} else {
-+			if (wifi_rssi < rssi_thresh)
-+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
-+			else
-+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
-+		}
-+	} else if (level_num == 3) {
-+		if (rssi_thresh > rssi_thresh1) {
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				    "[BTCoex], wifi RSSI thresh error!!\n");
-+			BTC_TRACE(trace_buf);
-+			return coex_sta->pre_wifi_rssi_state[index];
-+		}
-+
-+		if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
-+		    ||
-+		    (coex_sta->pre_wifi_rssi_state[index] ==
-+		     BTC_RSSI_STATE_STAY_LOW)) {
-+			if (wifi_rssi >= (rssi_thresh +
-+					  BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
-+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
-+			else
-+				wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
-+		} else if ((coex_sta->pre_wifi_rssi_state[index] ==
-+			    BTC_RSSI_STATE_MEDIUM) ||
-+			   (coex_sta->pre_wifi_rssi_state[index] ==
-+			    BTC_RSSI_STATE_STAY_MEDIUM)) {
-+			if (wifi_rssi >= (rssi_thresh1 +
-+					  BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
-+				wifi_rssi_state = BTC_RSSI_STATE_HIGH;
-+			else if (wifi_rssi < rssi_thresh)
-+				wifi_rssi_state = BTC_RSSI_STATE_LOW;
-+			else
-+				wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
-+		} else {
-+			if (wifi_rssi < rssi_thresh1)
-+				wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
-+			else
-+				wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
-+		}
-+	}
-+
-+	coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
-+
-+	return wifi_rssi_state;
-+}
-+
-+void halbtc8703b1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
-+				    IN boolean force_exec, IN u32 dis_rate_mask)
-+{
-+	coex_dm->cur_ra_mask = dis_rate_mask;
-+
-+	if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
-+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
-+				   &coex_dm->cur_ra_mask);
-+	coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
-+}
-+
-+void halbtc8703b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
-+		IN boolean force_exec, IN u8 type)
-+{
-+	boolean	wifi_under_b_mode = FALSE;
-+
-+	coex_dm->cur_arfr_type = type;
-+
-+	if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
-+		switch (coex_dm->cur_arfr_type) {
-+		case 0:	/* normal mode */
-+			btcoexist->btc_write_4byte(btcoexist, 0x430,
-+						   coex_dm->backup_arfr_cnt1);
-+			btcoexist->btc_write_4byte(btcoexist, 0x434,
-+						   coex_dm->backup_arfr_cnt2);
-+			break;
-+		case 1:
-+			btcoexist->btc_get(btcoexist,
-+					   BTC_GET_BL_WIFI_UNDER_B_MODE,
-+					   &wifi_under_b_mode);
-+			if (wifi_under_b_mode) {
-+				btcoexist->btc_write_4byte(btcoexist,
-+							   0x430, 0x0);
-+				btcoexist->btc_write_4byte(btcoexist,
-+							   0x434, 0x01010101);
-+			} else {
-+				btcoexist->btc_write_4byte(btcoexist,
-+							   0x430, 0x0);
-+				btcoexist->btc_write_4byte(btcoexist,
-+							   0x434, 0x04030201);
-+			}
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
-+}
-+
-+void halbtc8703b1ant_retry_limit(IN struct btc_coexist *btcoexist,
-+				 IN boolean force_exec, IN u8 type)
-+{
-+	coex_dm->cur_retry_limit_type = type;
-+
-+	if (force_exec ||
-+	    (coex_dm->pre_retry_limit_type !=
-+	     coex_dm->cur_retry_limit_type)) {
-+		switch (coex_dm->cur_retry_limit_type) {
-+		case 0:	/* normal mode */
-+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
-+						   coex_dm->backup_retry_limit);
-+			break;
-+		case 1:	/* retry limit=8 */
-+			btcoexist->btc_write_2byte(btcoexist, 0x42a,
-+						   0x0808);
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
-+}
-+
-+void halbtc8703b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
-+				    IN boolean force_exec, IN u8 type)
-+{
-+	coex_dm->cur_ampdu_time_type = type;
-+
-+	if (force_exec ||
-+	    (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
-+		switch (coex_dm->cur_ampdu_time_type) {
-+		case 0:	/* normal mode */
-+			btcoexist->btc_write_1byte(btcoexist, 0x456,
-+					   coex_dm->backup_ampdu_max_time);
-+			break;
-+		case 1:	/* AMPDU timw = 0x38 * 32us */
-+			btcoexist->btc_write_1byte(btcoexist, 0x456,
-+						   0x38);
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
-+}
-+
-+void halbtc8703b1ant_limited_tx(IN struct btc_coexist *btcoexist,
-+		IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
-+				IN u8 retry_limit_type, IN u8 ampdu_time_type)
-+{
-+	switch (ra_mask_type) {
-+	case 0:	/* normal mode */
-+		halbtc8703b1ant_update_ra_mask(btcoexist, force_exec,
-+					       0x0);
-+		break;
-+	case 1:	/* disable cck 1/2 */
-+		halbtc8703b1ant_update_ra_mask(btcoexist, force_exec,
-+					       0x00000003);
-+		break;
-+	case 2:	/* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
-+		halbtc8703b1ant_update_ra_mask(btcoexist, force_exec,
-+					       0x0001f1f7);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	halbtc8703b1ant_auto_rate_fallback_retry(btcoexist, force_exec,
-+			arfr_type);
-+	halbtc8703b1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
-+	halbtc8703b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
-+}
-+
-+void halbtc8703b1ant_limited_rx(IN struct btc_coexist *btcoexist,
-+			IN boolean force_exec, IN boolean rej_ap_agg_pkt,
-+			IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
-+{
-+	boolean	reject_rx_agg = rej_ap_agg_pkt;
-+	boolean	bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
-+	u8	rx_agg_size = agg_buf_size;
-+
-+	/* ============================================ */
-+	/*	Rx Aggregation related setting */
-+	/* ============================================ */
-+	btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
-+			   &reject_rx_agg);
-+	/* decide BT control aggregation buf size or not */
-+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
-+			   &bt_ctrl_rx_agg_size);
-+	/* aggregation buf size, only work when BT control Rx aggregation size. */
-+	btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
-+	/* real update aggregation setting */
-+	btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-+
-+
-+}
-+
-+void halbtc8703b1ant_query_bt_info(IN struct btc_coexist *btcoexist)
-+{
-+	u8			h2c_parameter[1] = {0};
-+
-+
-+	h2c_parameter[0] |= BIT(0);	/* trigger */
-+
-+	btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
-+}
-+
-+void halbtc8703b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
-+{
-+	u32			reg_hp_txrx, reg_lp_txrx, u32tmp;
-+	u32			reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
-+	static u8		num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0,
-+				cnt_autoslot_hang = 0;
-+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-+
-+	/* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */
-+	/* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */
-+
-+	reg_hp_txrx = 0x770;
-+	reg_lp_txrx = 0x774;
-+
-+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
-+	reg_hp_tx = u32tmp & MASKLWORD;
-+	reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-+
-+	u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
-+	reg_lp_tx = u32tmp & MASKLWORD;
-+	reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-+
-+	coex_sta->high_priority_tx = reg_hp_tx;
-+	coex_sta->high_priority_rx = reg_hp_rx;
-+	coex_sta->low_priority_tx = reg_lp_tx;
-+	coex_sta->low_priority_rx = reg_lp_rx;
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
-+				reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
-+
-+	BTC_TRACE(trace_buf);
-+
-+	if (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
-+			coex_dm->bt_status) {
-+
-+			if (coex_sta->high_priority_rx >= 15) {
-+					if (cnt_overhead < 3)
-+						cnt_overhead++;
-+
-+					if (cnt_overhead == 3)
-+						coex_sta->is_hiPri_rx_overhead = TRUE;
-+			} else {
-+					if (cnt_overhead > 0)
-+						cnt_overhead--;
-+
-+					if (cnt_overhead == 0)
-+						coex_sta->is_hiPri_rx_overhead = FALSE;
-+			}
-+	} else
-+		coex_sta->is_hiPri_rx_overhead = FALSE;
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		    "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
-+		    reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
-+
-+	BTC_TRACE(trace_buf);
-+
-+	/* reset counter */
-+	btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-+
-+	if ((coex_sta->low_priority_tx > 1150)  &&
-+	    (!coex_sta->c2h_bt_inquiry_page))
-+		coex_sta->pop_event_cnt++;
-+
-+	if ((coex_sta->low_priority_rx >= 1150) &&
-+	    (coex_sta->low_priority_rx >= coex_sta->low_priority_tx)
-+	    && (!coex_sta->under_ips)  && (!coex_sta->c2h_bt_inquiry_page) &&
-+	    (coex_sta->bt_link_exist))	{
-+		if (cnt_slave >= 3) {
-+			bt_link_info->slave_role = TRUE;
-+			cnt_slave = 3;
-+		} else
-+			cnt_slave++;
-+	} else {
-+		if (cnt_slave == 0)	{
-+			bt_link_info->slave_role = FALSE;
-+			cnt_slave = 0;
-+		} else
-+			cnt_slave--;
-+
-+	}
-+
-+	if (coex_sta->is_tdma_btautoslot) {
-+		if ((coex_sta->low_priority_tx >= 1300) &&
-+			(coex_sta->low_priority_rx <= 150)) {
-+			if (cnt_autoslot_hang >= 2) {
-+				coex_sta->is_tdma_btautoslot_hang = TRUE;
-+				cnt_autoslot_hang = 2;
-+			} else
-+				cnt_autoslot_hang++;
-+		} else {
-+			if (cnt_autoslot_hang == 0) {
-+				coex_sta->is_tdma_btautoslot_hang = FALSE;
-+				cnt_autoslot_hang = 0;
-+			} else
-+				cnt_autoslot_hang--;
-+		}
-+	}
-+
-+	if (bt_link_info->hid_only) {
-+		if (coex_sta->low_priority_rx > 50)
-+			coex_sta->is_hid_low_pri_tx_overhead = true;
-+		else
-+			coex_sta->is_hid_low_pri_tx_overhead = false;
-+	}
-+
-+	if (!coex_sta->bt_disabled) {
-+		if ((coex_sta->high_priority_tx == 0) &&
-+		    (coex_sta->high_priority_rx == 0) &&
-+		    (coex_sta->low_priority_tx == 0) &&
-+		    (coex_sta->low_priority_rx == 0)) {
-+			num_of_bt_counter_chk++;
-+			if (num_of_bt_counter_chk >= 3) {
-+				halbtc8703b1ant_query_bt_info(btcoexist);
-+				num_of_bt_counter_chk = 0;
-+			}
-+		}
-+	}
-+
-+}
-+
-+
-+void halbtc8703b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
-+{
-+	s32 wifi_rssi = 0;
-+	boolean wifi_busy = FALSE, wifi_under_b_mode = FALSE,
-+			wifi_scan = FALSE, wifi_connected = FALSE;
-+	boolean bt_idle = FALSE, wl_idle = FALSE, is_cck_deadlock = FALSE;
-+	static u8 cck_lock_counter = 0, wl_noisy_count0 = 0,
-+		  wl_noisy_count1 = 3, wl_noisy_count2 = 0;
-+	u32 total_cnt, reg_val1, reg_val2, cnt_cck;
-+	u32 cnt_crcok = 0, cnt_crcerr = 0;
-+	static u8 cnt = 0, cnt_ccklocking = 0;
-+	u8	h2c_parameter[1] = {0};
-+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-+
-+	/*send h2c to query WL FW dbg info	*/
-+	if (((coex_dm->cur_ps_tdma_on) && (coex_sta->force_lps_ctrl)) ||
-+		 ((coex_sta->acl_busy) && (bt_link_info->a2dp_exist))) {
-+		h2c_parameter[0] = 0x8;
-+		btcoexist->btc_fill_h2c(btcoexist, 0x69, 1, h2c_parameter);
-+	}
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-+	btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
-+			   &wifi_under_b_mode);
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
-+
-+	coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(
-+						btcoexist,
-+						PHYDM_INFO_CRC32_OK_CCK);
-+	coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(
-+						btcoexist,
-+						PHYDM_INFO_CRC32_OK_LEGACY);
-+	coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(
-+						btcoexist,
-+						PHYDM_INFO_CRC32_OK_HT);
-+	coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter(
-+						btcoexist,
-+						PHYDM_INFO_CRC32_OK_VHT);
-+
-+	coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter(
-+						btcoexist, PHYDM_INFO_CRC32_ERROR_CCK);
-+	coex_sta->crc_err_11g =  btcoexist->btc_phydm_query_PHY_counter(
-+						btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY);
-+	coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter(
-+						btcoexist, PHYDM_INFO_CRC32_ERROR_HT);
-+	coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter(
-+						btcoexist,
-+						PHYDM_INFO_CRC32_ERROR_VHT);
-+
-+	cnt_crcok =  coex_sta->crc_ok_cck + coex_sta->crc_ok_11g
-+				+ coex_sta->crc_ok_11n
-+				+ coex_sta->crc_ok_11n_vht;
-+
-+	cnt_crcerr =  coex_sta->crc_err_cck + coex_sta->crc_err_11g
-+				+ coex_sta->crc_err_11n
-+				+ coex_sta->crc_err_11n_vht;
-+
-+	/*	CCK lock identification	*/
-+	if (coex_sta->cck_lock)
-+		cnt_ccklocking++;
-+	else if (cnt_ccklocking != 0)
-+		cnt_ccklocking--;
-+
-+	if (cnt_ccklocking >= 3) {
-+		cnt_ccklocking = 3;
-+		coex_sta->cck_lock_ever = TRUE;
-+	}
-+
-+	/* WiFi environment noisy identification */
-+	cnt_cck = coex_sta->crc_ok_cck + coex_sta->crc_err_cck;
-+
-+	if ((!wifi_busy) && (!coex_sta->cck_lock)) {
-+		if (cnt_cck > 250) {
-+			if (wl_noisy_count2 < 3)
-+				wl_noisy_count2++;
-+
-+			if (wl_noisy_count2 == 3) {
-+				wl_noisy_count0 = 0;
-+				wl_noisy_count1 = 0;
-+			}
-+
-+		} else if (cnt_cck < 50) {
-+			if (wl_noisy_count0 < 3)
-+				wl_noisy_count0++;
-+
-+			if (wl_noisy_count0 == 3) {
-+				wl_noisy_count1 = 0;
-+				wl_noisy_count2 = 0;
-+			}
-+
-+		} else {
-+			if (wl_noisy_count1 < 3)
-+				wl_noisy_count1++;
-+
-+			if (wl_noisy_count1 == 3) {
-+				wl_noisy_count0 = 0;
-+				wl_noisy_count2 = 0;
-+			}
-+	}
-+
-+		if (wl_noisy_count2 == 3)
-+			coex_sta->wl_noisy_level = 2;
-+		else if (wl_noisy_count1 == 3)
-+			coex_sta->wl_noisy_level = 1;
-+		else
-+			coex_sta->wl_noisy_level = 0;
-+	}
-+
-+}
-+
-+
-+
-+
-+void halbtc8703b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
-+{
-+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
-+	boolean				bt_hs_on = FALSE;
-+	boolean		bt_busy = FALSE;
-+	u32			val = 0;
-+	static	u8		pre_num_of_profile = 0, cur_num_of_profile = 0, cnt = 0;
-+
-+	if (coex_sta->is_ble_scan_toggle) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+					"[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n");
-+		BTC_TRACE(trace_buf);
-+		coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(btcoexist);
-+
-+		if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1)
-+			coex_sta->bt_ble_scan_para[0]  = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x1);
-+		if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2)
-+			coex_sta->bt_ble_scan_para[1]  = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x2);
-+		if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4)
-+			coex_sta->bt_ble_scan_para[2]  = btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, 0x4);
-+	}
-+
-+	coex_sta->num_of_profile = 0;
-+
-+	/* set link exist status */
-+	if (!(coex_sta->bt_info & BT_INFO_8703B_1ANT_B_CONNECTION)) {
-+		coex_sta->bt_link_exist = FALSE;
-+		coex_sta->pan_exist = FALSE;
-+		coex_sta->a2dp_exist = FALSE;
-+		coex_sta->hid_exist = FALSE;
-+		coex_sta->sco_exist = FALSE;
-+	} else {	/* connection exists */
-+		coex_sta->bt_link_exist = TRUE;
-+		if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_FTP) {
-+			coex_sta->pan_exist = TRUE;
-+			coex_sta->num_of_profile++;
-+		} else
-+			coex_sta->pan_exist = FALSE;
-+
-+		if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_A2DP) {
-+			coex_sta->a2dp_exist = TRUE;
-+			coex_sta->num_of_profile++;
-+		} else
-+			coex_sta->a2dp_exist = FALSE;
-+
-+		if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_HID) {
-+			coex_sta->hid_exist = TRUE;
-+			coex_sta->num_of_profile++;
-+		} else
-+			coex_sta->hid_exist = FALSE;
-+
-+		if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) {
-+			coex_sta->sco_exist = TRUE;
-+			coex_sta->num_of_profile++;
-+		} else
-+			coex_sta->sco_exist = FALSE;
-+
-+	}
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-+
-+	bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
-+	bt_link_info->sco_exist = coex_sta->sco_exist;
-+	bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
-+	bt_link_info->pan_exist = coex_sta->pan_exist;
-+	bt_link_info->hid_exist = coex_sta->hid_exist;
-+	bt_link_info->acl_busy = coex_sta->acl_busy;
-+
-+	/* work around for HS mode. */
-+	if (bt_hs_on) {
-+		bt_link_info->pan_exist = TRUE;
-+		bt_link_info->bt_link_exist = TRUE;
-+	}
-+
-+	/* check if Sco only */
-+	if (bt_link_info->sco_exist &&
-+	    !bt_link_info->a2dp_exist &&
-+	    !bt_link_info->pan_exist &&
-+	    !bt_link_info->hid_exist)
-+		bt_link_info->sco_only = TRUE;
-+	else
-+		bt_link_info->sco_only = FALSE;
-+
-+	/* check if A2dp only */
-+	if (!bt_link_info->sco_exist &&
-+	    bt_link_info->a2dp_exist &&
-+	    !bt_link_info->pan_exist &&
-+	    !bt_link_info->hid_exist)
-+		bt_link_info->a2dp_only = TRUE;
-+	else
-+		bt_link_info->a2dp_only = FALSE;
-+
-+	/* check if Pan only */
-+	if (!bt_link_info->sco_exist &&
-+	    !bt_link_info->a2dp_exist &&
-+	    bt_link_info->pan_exist &&
-+	    !bt_link_info->hid_exist)
-+		bt_link_info->pan_only = TRUE;
-+	else
-+		bt_link_info->pan_only = FALSE;
-+
-+	/* check if Hid only */
-+	if (!bt_link_info->sco_exist &&
-+	    !bt_link_info->a2dp_exist &&
-+	    !bt_link_info->pan_exist &&
-+	    bt_link_info->hid_exist)
-+		bt_link_info->hid_only = TRUE;
-+	else
-+		bt_link_info->hid_only = FALSE;
-+
-+	if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_INQ_PAGE) {
-+		coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_INQ_PAGE;
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], BtInfoNotify(), BT Inq/page!!!\n");
-+	} else if (!(coex_sta->bt_info & BT_INFO_8703B_1ANT_B_CONNECTION)) {
-+		coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
-+	} else if (coex_sta->bt_info == BT_INFO_8703B_1ANT_B_CONNECTION) {
-+		/* connection exists but no busy */
-+		coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE;
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
-+	} else if (((coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) ||
-+		    (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_BUSY)) &&
-+		   (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_ACL_BUSY)) {
-+		coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY;
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n");
-+	} else if ((coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) ||
-+		   (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_SCO_BUSY)) {
-+		coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_SCO_BUSY;
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
-+	} else if (coex_sta->bt_info & BT_INFO_8703B_1ANT_B_ACL_BUSY) {
-+		coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_ACL_BUSY;
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
-+	} else {
-+		coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_MAX;
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
-+	}
-+
-+	BTC_TRACE(trace_buf);
-+
-+	if ((BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
-+	    (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
-+	    (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
-+		bt_busy = TRUE;
-+	else
-+		bt_busy = FALSE;
-+
-+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-+
-+	cur_num_of_profile = coex_sta->num_of_profile;
-+
-+	if (cur_num_of_profile != pre_num_of_profile)
-+		cnt = 2;
-+
-+	if (bt_link_info->a2dp_exist) {
-+
-+		if (((coex_sta->bt_a2dp_vendor_id == 0) &&
-+			(coex_sta->bt_a2dp_device_name == 0)) ||
-+			(cur_num_of_profile != pre_num_of_profile)) {
-+
-+			btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_DEVICE_INFO, &val);
-+
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+					"[BTCoex], BtInfoNotify(), get BT DEVICE_INFO = %x\n", val);
-+			BTC_TRACE(trace_buf);
-+
-+			coex_sta->bt_a2dp_vendor_id = (u8)(val & 0xff);
-+			coex_sta->bt_a2dp_device_name = (val & 0xffffff00) >> 8;
-+		}
-+
-+		if (((coex_sta->legacy_forbidden_slot == 0) &&
-+			(coex_sta->le_forbidden_slot == 0)) ||
-+			(cur_num_of_profile != pre_num_of_profile) ||
-+			(cnt > 0)) {
-+
-+			if (cnt > 0)
-+				cnt--;
-+
-+			btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL, &val);
-+
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+					"[BTCoex], BtInfoNotify(), get BT FORBIDDEN_SLOT_VAL = %x\n", val);
-+			BTC_TRACE(trace_buf);
-+
-+			coex_sta->legacy_forbidden_slot = (u16)(val & 0xffff);
-+			coex_sta->le_forbidden_slot = (u16)((val & 0xffff0000) >> 16);
-+		}
-+	}
-+
-+	pre_num_of_profile = coex_sta->num_of_profile;
-+
-+}
-+
-+
-+void halbtc8703b1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
-+		IN u8 type)
-+{
-+	u8			h2c_parameter[3] = {0};
-+	u32			wifi_bw;
-+	u8			wifi_central_chnl;
-+
-+	/* only 2.4G we need to inform bt the chnl mask */
-+	btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
-+			   &wifi_central_chnl);
-+	if ((BTC_MEDIA_CONNECT == type) &&
-+	    (wifi_central_chnl <= 14)) {
-+		h2c_parameter[0] =
-+			0x1;  /* enable BT AFH skip WL channel for 8703b because BT Rx LO interference */
-+		/* h2c_parameter[0] = 0x0; */
-+		h2c_parameter[1] = wifi_central_chnl;
-+		btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-+		if (BTC_WIFI_BW_HT40 == wifi_bw)
-+			h2c_parameter[2] = 0x30;
-+		else
-+			h2c_parameter[2] = 0x20;
-+	}
-+
-+	coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
-+	coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
-+	coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-+
-+	btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
-+
-+}
-+
-+void halbtc8703b1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
-+					IN boolean enable_auto_report)
-+{
-+	u8			h2c_parameter[1] = {0};
-+
-+	h2c_parameter[0] = 0;
-+
-+	if (enable_auto_report)
-+		h2c_parameter[0] |= BIT(0);
-+
-+	btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
-+}
-+
-+void halbtc8703b1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
-+		    IN boolean force_exec, IN boolean enable_auto_report)
-+{
-+	coex_dm->cur_bt_auto_report = enable_auto_report;
-+
-+	if (!force_exec) {
-+		if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
-+			return;
-+	}
-+	halbtc8703b1ant_set_bt_auto_report(btcoexist,
-+					   coex_dm->cur_bt_auto_report);
-+
-+	coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
-+}
-+
-+void halbtc8703b1ant_set_fw_low_penalty_ra(IN struct btc_coexist
-+		*btcoexist, IN boolean low_penalty_ra)
-+{
-+	u8			h2c_parameter[6] = {0};
-+
-+	h2c_parameter[0] = 0x6;	/* op_code, 0x6= Retry_Penalty */
-+
-+	if (low_penalty_ra) {
-+		h2c_parameter[1] |= BIT(0);
-+		h2c_parameter[2] =
-+			0x00;  /* normal rate except MCS7/6/5, OFDM54/48/36 */
-+		h2c_parameter[3] = 0xf7;  /* MCS7 or OFDM54 */
-+		h2c_parameter[4] = 0xf8;  /* MCS6 or OFDM48 */
-+		h2c_parameter[5] = 0xf9;	/* MCS5 or OFDM36	 */
-+	}
-+
-+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
-+}
-+
-+void halbtc8703b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
-+			    IN boolean force_exec, IN boolean low_penalty_ra)
-+{
-+	coex_dm->cur_low_penalty_ra = low_penalty_ra;
-+
-+	if (!force_exec) {
-+		if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
-+			return;
-+	}
-+
-+	halbtc8703b1ant_set_fw_low_penalty_ra(btcoexist,
-+					      coex_dm->cur_low_penalty_ra);
-+
-+	coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-+}
-+
-+void halbtc8703b1ant_write_score_board(
-+	IN	struct  btc_coexist		*btcoexist,
-+	IN	u16				bitpos,
-+	IN	boolean		state
-+)
-+{
-+
-+	static u16 originalval = 0x8002, preval = 0x0;
-+
-+	if (state)
-+		originalval = originalval | bitpos;
-+	else
-+		originalval = originalval & (~bitpos);
-+
-+	coex_sta->score_board_WB = originalval;
-+
-+	if (originalval != preval) {
-+
-+		preval = originalval;
-+	btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
-+	} else {
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		"[BTCoex], halbtc8703b1ant_write_score_board: return for nochange\n");
-+	BTC_TRACE(trace_buf);
-+	}
-+}
-+
-+
-+void halbtc8703b1ant_read_score_board(
-+	IN	struct  btc_coexist		*btcoexist,
-+	IN   u16				*score_board_val
-+)
-+{
-+
-+	*score_board_val = (btcoexist->btc_read_2byte(btcoexist,
-+			    0xaa)) & 0x7fff;
-+}
-+
-+void halbtc8703b1ant_post_state_to_bt(
-+	IN	struct  btc_coexist		*btcoexist,
-+	IN	u16						type,
-+	IN  boolean                 state
-+)
-+{
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		"[BTCoex], halbtc8703b1ant_post_state_to_bt: type = %d, state =%d\n",
-+		type, state);
-+	BTC_TRACE(trace_buf);
-+
-+	halbtc8703b1ant_write_score_board(btcoexist, (u16) type, state);
-+}
-+
-+boolean halbtc8703b1ant_is_wifibt_status_changed(IN struct btc_coexist
-+		*btcoexist)
-+{
-+	static boolean	pre_wifi_busy = FALSE, pre_under_4way = FALSE,
-+			pre_bt_hs_on = FALSE, pre_bt_off = FALSE,
-+			pre_bt_slave = FALSE, pre_hid_low_pri_tx_overhead = FALSE,
-+			pre_wifi_under_lps = FALSE, pre_bt_setup_link = FALSE,
-+			pre_cck_lock = FALSE, pre_cck_lock_warn = FALSE;
-+	static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0;
-+	boolean wifi_busy = FALSE, under_4way = FALSE, bt_hs_on = FALSE;
-+	boolean wifi_connected = FALSE;
-+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
-+			   &wifi_connected);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
-+			   &under_4way);
-+
-+	if (coex_sta->bt_disabled != pre_bt_off) {
-+		pre_bt_off = coex_sta->bt_disabled;
-+
-+		if (coex_sta->bt_disabled)
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+					"[BTCoex], BT is disabled !!\n");
-+		else
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+					"[BTCoex], BT is enabled !!\n");
-+
-+		BTC_TRACE(trace_buf);
-+
-+		coex_sta->bt_coex_supported_feature = 0;
-+		coex_sta->bt_coex_supported_version = 0;
-+		coex_sta->bt_ble_scan_type = 0;
-+		coex_sta->bt_ble_scan_para[0] = 0;
-+		coex_sta->bt_ble_scan_para[1] = 0;
-+		coex_sta->bt_ble_scan_para[2] = 0;
-+		coex_sta->legacy_forbidden_slot = 0;
-+		coex_sta->le_forbidden_slot = 0;
-+		coex_sta->bt_a2dp_vendor_id = 0;
-+		coex_sta->bt_a2dp_device_name = 0;
-+
-+		return TRUE;
-+	}
-+
-+	if (wifi_connected) {
-+		if (wifi_busy != pre_wifi_busy) {
-+			pre_wifi_busy = wifi_busy;
-+
-+			if (wifi_busy)
-+				halbtc8703b1ant_post_state_to_bt(btcoexist,
-+						BT_8703B_1ANT_SCOREBOARD_UNDERTEST, TRUE);
-+			else
-+				halbtc8703b1ant_post_state_to_bt(btcoexist,
-+						BT_8703B_1ANT_SCOREBOARD_UNDERTEST, FALSE);
-+			return TRUE;
-+		}
-+		if (under_4way != pre_under_4way) {
-+			pre_under_4way = under_4way;
-+			return TRUE;
-+		}
-+		if (bt_hs_on != pre_bt_hs_on) {
-+			pre_bt_hs_on = bt_hs_on;
-+			return TRUE;
-+		}
-+		if (coex_sta->wl_noisy_level != pre_wl_noisy_level) {
-+			pre_wl_noisy_level = coex_sta->wl_noisy_level;
-+			return TRUE;
-+		}
-+		if (coex_sta->under_lps != pre_wifi_under_lps) {
-+			pre_wifi_under_lps = coex_sta->under_lps;
-+			if (coex_sta->under_lps == TRUE)
-+				return TRUE;
-+		}
-+		if (coex_sta->cck_lock != pre_cck_lock) {
-+			pre_cck_lock = coex_sta->cck_lock;
-+			return TRUE;
-+		}
-+		if (coex_sta->cck_lock_warn != pre_cck_lock_warn) {
-+			pre_cck_lock_warn = coex_sta->cck_lock_warn;
-+			return TRUE;
-+		}
-+	}
-+
-+	if (!coex_sta->bt_disabled) {
-+		if (coex_sta->hid_busy_num != pre_hid_busy_num) {
-+			pre_hid_busy_num = coex_sta->hid_busy_num;
-+			return TRUE;
-+		}
-+
-+		if (bt_link_info->slave_role != pre_bt_slave) {
-+			pre_bt_slave = bt_link_info->slave_role;
-+			return TRUE;
-+		}
-+
-+		if (pre_hid_low_pri_tx_overhead != coex_sta->is_hid_low_pri_tx_overhead) {
-+			pre_hid_low_pri_tx_overhead = coex_sta->is_hid_low_pri_tx_overhead;
-+			return TRUE;
-+		}
-+
-+		if (pre_bt_setup_link != coex_sta->is_setupLink) {
-+			pre_bt_setup_link = coex_sta->is_setupLink;
-+			return TRUE;
-+		}
-+	}
-+
-+	return FALSE;
-+}
-+
-+
-+void halbtc8703b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
-+{
-+	static u32		bt_disable_cnt = 0;
-+	boolean			bt_active = TRUE, bt_disabled = FALSE;
-+	u16			u16tmp;
-+
-+	/* This function check if bt is disabled */
-+#if 1
-+	if (coex_sta->high_priority_tx == 0 &&
-+	    coex_sta->high_priority_rx == 0 &&
-+	    coex_sta->low_priority_tx == 0 &&
-+	    coex_sta->low_priority_rx == 0)
-+		bt_active = FALSE;
-+	if (coex_sta->high_priority_tx == 0xffff &&
-+	    coex_sta->high_priority_rx == 0xffff &&
-+	    coex_sta->low_priority_tx == 0xffff &&
-+	    coex_sta->low_priority_rx == 0xffff)
-+		bt_active = FALSE;
-+
-+
-+#else   /*  8703b BT can't show correct on/off status in scoreboard[1] 2015/11/26 */
-+
-+	halbtc8703b1ant_read_score_board(btcoexist,	&u16tmp);
-+
-+	bt_active = u16tmp & BIT(1);
-+
-+
-+#endif
-+
-+	if (bt_active) {
-+		bt_disable_cnt = 0;
-+		bt_disabled = FALSE;
-+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
-+				   &bt_disabled);
-+	} else {
-+
-+		bt_disable_cnt++;
-+		if (bt_disable_cnt >= 10) {
-+			bt_disabled = TRUE;
-+			bt_disable_cnt = 10;
-+		}
-+
-+		btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
-+				   &bt_disabled);
-+	}
-+
-+	if (bt_disabled)
-+		halbtc8703b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE);
-+	else
-+		halbtc8703b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, TRUE);
-+
-+	if (coex_sta->bt_disabled != bt_disabled) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], BT is from %s to %s!!\n",
-+			    (coex_sta->bt_disabled ? "disabled" : "enabled"),
-+			    (bt_disabled ? "disabled" : "enabled"));
-+		BTC_TRACE(trace_buf);
-+		coex_sta->bt_disabled = bt_disabled;
-+
-+	}
-+}
-+
-+
-+
-+void halbtc8703b1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
-+					IN boolean isenable)
-+{
-+
-+#if (BT_8703B_1ANT_ENABLE_GNTBT_TO_GPIO14 == 1)
-+	if (isenable) {
-+		/* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
-+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
-+
-+		/* enable GNT_BT debug to GPIO */
-+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0);
-+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0);
-+	} else {
-+		/* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
-+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
-+
-+		/* Disable GNT_BT debug to GPIO, and enable chip_wakeup_host */
-+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x1);
-+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x1);
-+	}
-+#endif
-+}
-+
-+u32 halbtc8703b1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
-+		IN u16 reg_addr)
-+{
-+	u32 j = 0, delay_count = 0;
-+
-+	/* wait for ready bit before access 0x7c0/0x7c4	*/
-+	while (1) {
-+		if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
-+			delay_ms(50);
-+			delay_count++;
-+			if (delay_count >= 10) {
-+				delay_count = 0;
-+				break;
-+			}
-+		} else
-+			break;
-+	}
-+
-+	btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr);
-+
-+	return btcoexist->btc_read_4byte(btcoexist,
-+					 0x7c8);  /* get read data */
-+
-+}
-+
-+void halbtc8703b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist
-+		*btcoexist,
-+		IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value)
-+{
-+	u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0;
-+
-+	if (bit_mask == 0x0)
-+		return;
-+	if (bit_mask == 0xffffffff) {
-+		/* wait for ready bit before access 0x7c0/0x7c4 */
-+		while (1) {
-+			if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
-+				delay_ms(50);
-+				delay_count++;
-+				if (delay_count >= 10) {
-+					delay_count = 0;
-+					break;
-+				}
-+			} else
-+				break;
-+		}
-+
-+		btcoexist->btc_write_4byte(btcoexist, 0x7c4,
-+					   reg_value); /* put write data */
-+
-+		btcoexist->btc_write_4byte(btcoexist, 0x7c0,
-+					   0xc00F0000 | reg_addr);
-+	} else {
-+		for (i = 0; i <= 31; i++) {
-+			if (((bit_mask >> i) & 0x1) == 0x1) {
-+				bitpos = i;
-+				break;
-+			}
-+		}
-+
-+		/* read back register value before write */
-+		val = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
-+				reg_addr);
-+		val = (val & (~bit_mask)) | (reg_value << bitpos);
-+
-+		/* wait for ready bit before access 0x7c0/0x7c4	*/
-+		while (1) {
-+			if ((btcoexist->btc_read_1byte(btcoexist, 0x7c3)&BIT(5)) == 0) {
-+				delay_ms(50);
-+				delay_count++;
-+				if (delay_count >= 10) {
-+					delay_count = 0;
-+					break;
-+				}
-+			} else
-+				break;
-+		}
-+
-+		btcoexist->btc_write_4byte(btcoexist, 0x7c4,
-+					   val); /* put write data */
-+
-+		btcoexist->btc_write_4byte(btcoexist, 0x7c0,
-+					   0xc00F0000 | reg_addr);
-+
-+	}
-+
-+}
-+
-+void halbtc8703b1ant_ltecoex_enable(IN struct btc_coexist *btcoexist,
-+				    IN boolean enable)
-+{
-+	u8 val;
-+
-+	val = (enable) ? 1 : 0;
-+	halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80,
-+			val);  /* 0x38[7] */
-+
-+}
-+
-+void halbtc8703b1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist,
-+		IN boolean wifi_control)
-+{
-+	u8 val;
-+
-+	val = (wifi_control) ? 1 : 0;
-+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4,
-+					   val); /* 0x70[26] */
-+
-+}
-+
-+void halbtc8703b1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
-+			IN u8 control_block, IN boolean sw_control, IN u8 state)
-+{
-+	u32 val = 0, val_orig = 0;
-+
-+	if (!sw_control)
-+		val = 0x0;
-+	else if (state & 0x1)
-+		val = 0x3;
-+	else
-+		val = 0x1;
-+
-+	val_orig = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
-+				0x38);
-+
-+	switch (control_block) {
-+	case BT_8703B_1ANT_GNT_BLOCK_RFC_BB:
-+	default:
-+		val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff);
-+		break;
-+	case BT_8703B_1ANT_GNT_BLOCK_RFC:
-+		val = (val << 14) | (val_orig & 0xffff3fff);
-+		break;
-+	case BT_8703B_1ANT_GNT_BLOCK_BB:
-+		val = (val << 10) | (val_orig & 0xfffff3ff);
-+		break;
-+	}
-+
-+	halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist,
-+			0x38, 0xffffffff, val);
-+}
-+
-+
-+void halbtc8703b1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
-+			IN u8 control_block, IN boolean sw_control, IN u8 state)
-+{
-+	u32 val = 0, val_orig = 0;
-+
-+	if (!sw_control)
-+		val = 0x0;
-+	else if (state & 0x1)
-+		val = 0x3;
-+	else
-+		val = 0x1;
-+
-+	val_orig = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
-+				0x38);
-+
-+	switch (control_block) {
-+	case BT_8703B_1ANT_GNT_BLOCK_RFC_BB:
-+	default:
-+		val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff);
-+		break;
-+	case BT_8703B_1ANT_GNT_BLOCK_RFC:
-+		val = (val << 12) | (val_orig & 0xffffcfff);
-+		break;
-+	case BT_8703B_1ANT_GNT_BLOCK_BB:
-+		val = (val << 8) | (val_orig & 0xfffffcff);
-+		break;
-+	}
-+
-+	halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist,
-+			0x38, 0xffffffff, val);
-+}
-+
-+
-+void halbtc8703b1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
-+		IN u8 table_type, IN u16 table_content)
-+{
-+	u16 reg_addr = 0x0000;
-+
-+	switch (table_type) {
-+	case BT_8703B_1ANT_CTT_WL_VS_LTE:
-+		reg_addr = 0xa0;
-+		break;
-+	case BT_8703B_1ANT_CTT_BT_VS_LTE:
-+		reg_addr = 0xa4;
-+		break;
-+	}
-+
-+	if (reg_addr != 0x0000)
-+		halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
-+			0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
-+
-+
-+}
-+
-+
-+void halbtc8703b1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist,
-+		IN u8 table_type, IN u8 table_content)
-+{
-+	u16 reg_addr = 0x0000;
-+
-+	switch (table_type) {
-+	case BT_8703B_1ANT_LBTT_WL_BREAK_LTE:
-+		reg_addr = 0xa8;
-+		break;
-+	case BT_8703B_1ANT_LBTT_BT_BREAK_LTE:
-+		reg_addr = 0xac;
-+		break;
-+	case BT_8703B_1ANT_LBTT_LTE_BREAK_WL:
-+		reg_addr = 0xb0;
-+		break;
-+	case BT_8703B_1ANT_LBTT_LTE_BREAK_BT:
-+		reg_addr = 0xb4;
-+		break;
-+	}
-+
-+	if (reg_addr != 0x0000)
-+		halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
-+			0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */
-+
-+
-+}
-+
-+void halbtc8703b1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist,
-+		IN boolean force_exec,  IN u8 interval,
-+		IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2,
-+		IN u8 val0x6c4_b3)
-+{
-+	static u8 pre_h2c_parameter[6] = {0};
-+	u8	cur_h2c_parameter[6] = {0};
-+	u8 i, match_cnt = 0;
-+
-+	cur_h2c_parameter[0] = 0x7;	/* op_code, 0x7= wlan toggle slot*/
-+
-+	cur_h2c_parameter[1] = interval;
-+	cur_h2c_parameter[2] = val0x6c4_b0;
-+	cur_h2c_parameter[3] = val0x6c4_b1;
-+	cur_h2c_parameter[4] = val0x6c4_b2;
-+	cur_h2c_parameter[5] = val0x6c4_b3;
-+
-+	if (!force_exec) {
-+		for (i = 1; i <= 5; i++) {
-+			if (cur_h2c_parameter[i] != pre_h2c_parameter[i])
-+				break;
-+
-+			match_cnt++;
-+		}
-+
-+		if (match_cnt == 5)
-+			return;
-+	}
-+
-+	for (i = 1; i <= 5; i++)
-+		pre_h2c_parameter[i] = cur_h2c_parameter[i];
-+
-+	btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter);
-+}
-+
-+
-+void halbtc8703b1ant_set_coex_table(IN struct btc_coexist *btcoexist,
-+	    IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
-+{
-+	btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-+
-+	btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-+
-+	btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-+
-+	btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-+}
-+
-+void halbtc8703b1ant_coex_table(IN struct btc_coexist *btcoexist,
-+			IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
-+				IN u32 val0x6c8, IN u8 val0x6cc)
-+{
-+	coex_dm->cur_val0x6c0 = val0x6c0;
-+	coex_dm->cur_val0x6c4 = val0x6c4;
-+	coex_dm->cur_val0x6c8 = val0x6c8;
-+	coex_dm->cur_val0x6cc = val0x6cc;
-+
-+	if (!force_exec) {
-+		if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
-+		    (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
-+		    (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
-+		    (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
-+			return;
-+	}
-+	halbtc8703b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
-+				       val0x6cc);
-+
-+	coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
-+	coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
-+	coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
-+	coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-+}
-+
-+void halbtc8703b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
-+		IN boolean force_exec, IN u8 type)
-+{
-+	u32	break_table;
-+	u8	select_table;
-+
-+	coex_sta->coex_table_type = type;
-+
-+	if (coex_sta->concurrent_rx_mode_on == TRUE) {
-+		break_table = 0xf0ffffff;  /* set WL hi-pri can break BT */
-+		select_table =
-+			0xb;		/* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
-+	} else {
-+		break_table = 0xffffff;
-+		select_table = 0x3;
-+	}
-+
-+	switch (type) {
-+	case 0:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0x55555555, 0x55555555, break_table,
-+					   select_table);
-+		break;
-+	case 1:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0xa5555555, 0xaa5a5a5a, break_table,
-+					   select_table);
-+		break;
-+	case 2:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0xaa5a5a5a, 0xaa5a5a5a, break_table,
-+					   select_table);
-+		break;
-+	case 3:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0x55555555, 0x5a5a5a5a, break_table,
-+					   select_table);
-+		break;
-+	case 4:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0xa5555555, 0xaa5a5a5a, break_table,
-+					   select_table);
-+		break;
-+	case 5:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0x5a5a5a5a, 0x5a5a5a5a, break_table,
-+					   select_table);
-+		break;
-+	case 6:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0xa5555555, 0xaa5a5a5a, break_table,
-+					   select_table);
-+		break;
-+	case 7:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0xaa555555, 0xaa555555, break_table,
-+					   select_table);
-+		break;
-+	case 8:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0xa5555555, 0xaaaa5aaa, break_table,
-+					   select_table);
-+		break;
-+	case 9:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0x5a5a5a5a, 0xaaaa5aaa, break_table,
-+					   select_table);
-+		break;
-+	case 10:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0xaaaaaaaa, 0xaaaaaaaa, break_table,
-+					   select_table);
-+		break;
-+	case 11:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0xa5a55555, 0xaaaa5a5a, break_table,
-+					   select_table);
-+		break;
-+	case 12:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0xa5555555, 0xaaaa5a5a, break_table,
-+					   select_table);
-+		break;
-+	case 13:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0xaa5555aa, 0xaa5a5a5a, break_table,
-+					   select_table);
-+		break;
-+	case 14:
-+		halbtc8703b1ant_coex_table(btcoexist, force_exec,
-+					   0xaa5555aa, 0x5a5a5a5a, break_table,
-+					   select_table);
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+void halbtc8703b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
-+		IN boolean enable)
-+{
-+	u8			h2c_parameter[1] = {0};
-+
-+	if (enable)
-+		h2c_parameter[0] |= BIT(0);/* function enable */
-+
-+	btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
-+}
-+
-+void halbtc8703b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
-+				     IN boolean force_exec, IN boolean enable)
-+{
-+	coex_dm->cur_ignore_wlan_act = enable;
-+
-+	if (!force_exec) {
-+		if (coex_dm->pre_ignore_wlan_act ==
-+		    coex_dm->cur_ignore_wlan_act)
-+			return;
-+	}
-+	halbtc8703b1ant_set_fw_ignore_wlan_act(btcoexist, enable);
-+
-+	coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-+}
-+
-+void halbtc8703b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
-+				  IN u8 lps_val, IN u8 rpwm_val)
-+{
-+	u8	lps = lps_val;
-+	u8	rpwm = rpwm_val;
-+
-+	btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
-+	btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
-+}
-+
-+void halbtc8703b1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
-+		      IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
-+{
-+	coex_dm->cur_lps = lps_val;
-+	coex_dm->cur_rpwm = rpwm_val;
-+
-+	if (!force_exec) {
-+		if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
-+		    (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
-+			return;
-+	}
-+	halbtc8703b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
-+
-+	coex_dm->pre_lps = coex_dm->cur_lps;
-+	coex_dm->pre_rpwm = coex_dm->cur_rpwm;
-+}
-+
-+void halbtc8703b1ant_ps_tdma_check_for_power_save_state(
-+	IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
-+{
-+	u8	lps_mode = 0x0;
-+	u8	h2c_parameter[5] = {0x8, 0, 0, 0, 0};
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
-+
-+	if (lps_mode) {	/* already under LPS state */
-+		if (new_ps_state) {
-+			/* keep state under LPS, do nothing. */
-+		} else {
-+			/* will leave LPS state, turn off psTdma first */
-+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
-+						h2c_parameter);
-+		}
-+	} else {					/* NO PS state */
-+		if (new_ps_state) {
-+			/* will enter LPS state, turn off psTdma first */
-+			btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
-+						h2c_parameter);
-+		} else {
-+			/* keep state under NO PS state, do nothing. */
-+		}
-+	}
-+}
-+
-+void halbtc8703b1ant_power_save_state(IN struct btc_coexist *btcoexist,
-+			      IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
-+{
-+	boolean		low_pwr_disable = FALSE;
-+
-+	switch (ps_type) {
-+	case BTC_PS_WIFI_NATIVE:
-+		/* recover to original 32k low power setting */
-+		coex_sta->force_lps_ctrl = FALSE;
-+		low_pwr_disable = FALSE;
-+		/* btcoexist->btc_set(btcoexist,
-+				   BTC_SET_ACT_DISABLE_LOW_POWER,
-+				   &low_pwr_disable); */
-+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_PRE_NORMAL_LPS,
-+				   NULL);
-+
-+		break;
-+	case BTC_PS_LPS_ON:
-+		coex_sta->force_lps_ctrl = TRUE;
-+		halbtc8703b1ant_ps_tdma_check_for_power_save_state(
-+			btcoexist, TRUE);
-+		halbtc8703b1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
-+					 lps_val, rpwm_val);
-+		/* when coex force to enter LPS, do not enter 32k low power. */
-+		low_pwr_disable = TRUE;
-+		btcoexist->btc_set(btcoexist,
-+				   BTC_SET_ACT_DISABLE_LOW_POWER,
-+				   &low_pwr_disable);
-+		/* power save must executed before psTdma.			 */
-+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
-+				   NULL);
-+
-+		break;
-+	case BTC_PS_LPS_OFF:
-+		coex_sta->force_lps_ctrl = TRUE;
-+		halbtc8703b1ant_ps_tdma_check_for_power_save_state(
-+			btcoexist, FALSE);
-+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
-+				   NULL);
-+
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+
-+
-+void halbtc8703b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
-+	   IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
-+{
-+	u8			h2c_parameter[5] = {0};
-+	u8			real_byte1 = byte1, real_byte5 = byte5;
-+	boolean			ap_enable = FALSE;
-+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-+	u8		ps_type = BTC_PS_WIFI_NATIVE;
-+
-+	if (byte5 & BIT(2))
-+		coex_sta->is_tdma_btautoslot = TRUE;
-+	else
-+		coex_sta->is_tdma_btautoslot = FALSE;
-+
-+	/* release bt-auto slot for auto-slot hang is detected!! */
-+	if (coex_sta->is_tdma_btautoslot)
-+		if ((coex_sta->is_tdma_btautoslot_hang) ||
-+			(bt_link_info->slave_role))
-+			byte5 = byte5 & 0xfb;
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
-+			   &ap_enable);
-+
-+	if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], FW for AP mode\n");
-+		BTC_TRACE(trace_buf);
-+		real_byte1 &= ~BIT(4);
-+		real_byte1 |= BIT(5);
-+
-+		real_byte5 |= BIT(5);
-+		real_byte5 &= ~BIT(6);
-+
-+		ps_type = BTC_PS_WIFI_NATIVE;
-+		halbtc8703b1ant_power_save_state(btcoexist,
-+					ps_type, 0x0,
-+					0x0);
-+	} else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
-+
-+		ps_type = BTC_PS_LPS_ON;
-+		halbtc8703b1ant_power_save_state(
-+			btcoexist, ps_type, 0x50,
-+			0x4);
-+	} else {
-+		ps_type = BTC_PS_WIFI_NATIVE;
-+		halbtc8703b1ant_power_save_state(btcoexist, ps_type,
-+						 0x0,
-+						 0x0);
-+	}
-+
-+	h2c_parameter[0] = real_byte1;
-+	h2c_parameter[1] = byte2;
-+	h2c_parameter[2] = byte3;
-+	h2c_parameter[3] = byte4;
-+	h2c_parameter[4] = real_byte5;
-+
-+	coex_dm->ps_tdma_para[0] = real_byte1;
-+	coex_dm->ps_tdma_para[1] = byte2;
-+	coex_dm->ps_tdma_para[2] = byte3;
-+	coex_dm->ps_tdma_para[3] = byte4;
-+	coex_dm->ps_tdma_para[4] = real_byte5;
-+
-+	btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
-+
-+	if (ps_type == BTC_PS_WIFI_NATIVE)
-+		btcoexist->btc_set(btcoexist, BTC_SET_ACT_POST_NORMAL_LPS, NULL);
-+}
-+
-+
-+void halbtc8703b1ant_ps_tdma(IN struct btc_coexist *btcoexist,
-+		     IN boolean force_exec, IN boolean turn_on, IN u8 type)
-+{
-+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-+	boolean			wifi_busy = FALSE;
-+	u8			rssi_adjust_val = 0;
-+	static u8			psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0;
-+	static boolean	 pre_wifi_busy = FALSE;
-+
-+	coex_dm->cur_ps_tdma_on = turn_on;
-+	coex_dm->cur_ps_tdma = type;
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-+
-+	if (wifi_busy != pre_wifi_busy) {
-+		force_exec = TRUE;
-+		pre_wifi_busy = wifi_busy;
-+	}
-+
-+	/* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
-+	if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist))
-+		psTdmaByte4Modify = 0x1;
-+	else
-+		psTdmaByte4Modify = 0x0;
-+
-+	if (pre_psTdmaByte4Modify != psTdmaByte4Modify) {
-+
-+		force_exec = TRUE;
-+		pre_psTdmaByte4Modify = psTdmaByte4Modify;
-+	}
-+
-+	if (!force_exec) {
-+		if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
-+		    (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
-+			return;
-+	}
-+
-+	if (coex_dm->cur_ps_tdma_on) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], ********** TDMA(on, %d) **********\n",
-+			    coex_dm->cur_ps_tdma);
-+		BTC_TRACE(trace_buf);
-+	} else {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], ********** TDMA(off, %d) **********\n",
-+			    coex_dm->cur_ps_tdma);
-+		BTC_TRACE(trace_buf);
-+	}
-+
-+	if (turn_on)	{
-+
-+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
-+					   0x1);  /* enable TBTT nterrupt */
-+	}
-+
-+
-+	if (turn_on) {
-+		switch (type) {
-+		default:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x35, 0x03, 0x11, 0x11);
-+			break;
-+		case 3:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x51, 0x30, 0x03, 0x10, 0x50);
-+			break;
-+		case 4:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x51, 0x21, 0x03, 0x10, 0x50);
-+			break;
-+		case 5:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x3a, 0x03, 0x11, 0x11);
-+			break;
-+		case 6:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x20, 0x03, 0x11, 0x11);
-+			break;
-+		case 7:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x51, 0x10, 0x03, 0x10,  0x54 |
-+							psTdmaByte4Modify);
-+			break;
-+		case 8:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x51, 0x10, 0x03, 0x10,  0x54 |
-+							psTdmaByte4Modify);
-+			break;
-+		case 9:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x51, 0x10, 0x03, 0x10,  0x54 |
-+							psTdmaByte4Modify);
-+			break;
-+		case 10:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x30, 0x03, 0x11, 0x10);
-+			break;
-+		case 11:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x25, 0x03, 0x11,  0x11 |
-+							psTdmaByte4Modify);
-+			break;
-+		case 12:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x51, 0x35, 0x03, 0x10,  0x50 |
-+							psTdmaByte4Modify);
-+			break;
-+		case 13:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x51, 0x25, 0x03, 0x10,  0x50 |
-+							psTdmaByte4Modify);
-+			break;
-+		case 14:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x51, 0x15, 0x03, 0x10,  0x50 |
-+							psTdmaByte4Modify);
-+			break;
-+		case 15:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x51, 0x20, 0x03, 0x10,  0x50 |
-+							psTdmaByte4Modify);
-+			break;
-+		case 16:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x10, 0x03, 0x11,  0x15 |
-+							psTdmaByte4Modify);
-+			break;
-+		case 17:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x10, 0x03, 0x11, 0x14);
-+			break;
-+		case 18:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x51, 0x30, 0x03, 0x10,  0x50 |
-+							psTdmaByte4Modify);
-+			break;
-+		case 19:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x15, 0x03, 0x11, 0x10);
-+			break;
-+		case 20:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x30, 0x03, 0x11, 0x10);
-+			break;
-+		case 21:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x30, 0x03, 0x11, 0x10);
-+			break;
-+		case 22:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x25, 0x03, 0x11, 0x10);
-+			break;
-+		case 24:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x51, 0x08, 0x03, 0x10,  0x54 |
-+							psTdmaByte4Modify);
-+			break;
-+		case 27:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x10, 0x03, 0x11, 0x15);
-+			break;
-+		case 28:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x51, 0x10, 0x0b, 0x10,  0x54);
-+			break;
-+		case 32:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x35, 0x03, 0x11, 0x11);
-+			break;
-+		case 33:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x35, 0x03, 0x11, 0x10);
-+			break;
-+		case 36:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x48, 0x03, 0x11, 0x10);
-+			break;
-+		case 57:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x51, 0x10, 0x03, 0x10,  0x50 |
-+							psTdmaByte4Modify);
-+			break;
-+		case 58:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x51, 0x10, 0x03, 0x10,  0x50 |
-+							psTdmaByte4Modify);
-+			break;
-+		case 67:
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist,
-+							0x61, 0x10, 0x03, 0x11,  0x10 |
-+							psTdmaByte4Modify);
-+			break;
-+		}
-+	} else {
-+
-+		/* disable PS tdma */
-+		switch (type) {
-+		case 8: /* PTA Control */
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x8,
-+							0x0, 0x0, 0x0, 0x0);
-+			break;
-+		case 0:
-+		default:  /* Software control, Antenna at BT side */
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x0,
-+							0x0, 0x0, 0x0, 0x0);
-+			break;
-+		case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */
-+			halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x0,
-+							0x0, 0x0, 0x48, 0x0);
-+			break;
-+		}
-+	}
-+
-+	coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
-+	coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
-+
-+}
-+
-+void halbtc8703b1ant_set_ant_path(IN struct btc_coexist *btcoexist,
-+				  IN u8 ant_pos_type, IN boolean force_exec,
-+				  IN u8 phase)
-+{
-+	u32	cnt_bt_cal_chk = 0;
-+	boolean	is_in_mp_mode = FALSE;
-+	u8	u8tmp = 0;
-+	u32	u32tmp1 = 0, u32tmp2 = 0;
-+
-+
-+	u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
-+				0x38);
-+
-+	/* To avoid indirect access fail	*/
-+	if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) {
-+		force_exec = TRUE;
-+		coex_sta->gnt_error_cnt++;
-+	}
-+
-+#if 1
-+	u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
-+			0x54);
-+	u8tmp  = btcoexist->btc_read_1byte(btcoexist, 0x73);
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		"[BTCoex], ********** (Before Ant Setup) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
-+		    u8tmp, u32tmp1, u32tmp2);
-+	BTC_TRACE(trace_buf);
-+#endif
-+
-+	coex_dm->cur_ant_pos_type = ant_pos_type;
-+
-+	if (!force_exec) {
-+		if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) {
-+
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], ********** Skip Antenna Path Setup because no change!!**********\n");
-+			BTC_TRACE(trace_buf);
-+			return;
-+		}
-+	}
-+
-+	coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
-+
-+	switch (phase) {
-+	case BT_8703B_1ANT_PHASE_COEX_INIT:
-+		/* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
-+		halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0);
-+
-+		/* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
-+		halbtc8703b1ant_ltecoex_set_coex_table(
-+			btcoexist,
-+			BT_8703B_1ANT_CTT_WL_VS_LTE,
-+			0xffff);
-+
-+		/* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
-+		halbtc8703b1ant_ltecoex_set_coex_table(
-+			btcoexist,
-+			BT_8703B_1ANT_CTT_BT_VS_LTE,
-+			0xffff);
-+
-+		/* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */
-+		while (cnt_bt_cal_chk <= 20) {
-+			u8tmp = btcoexist->btc_read_1byte(
-+					btcoexist,
-+					0x49d);
-+			cnt_bt_cal_chk++;
-+			if (u8tmp & BIT(0)) {
-+				BTC_SPRINTF(trace_buf,
-+					    BT_TMP_BUF_SIZE,
-+					"[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n",
-+					    cnt_bt_cal_chk);
-+				BTC_TRACE(trace_buf);
-+				delay_ms(50);
-+			} else {
-+				BTC_SPRINTF(trace_buf,
-+					    BT_TMP_BUF_SIZE,
-+					"[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n",
-+					    cnt_bt_cal_chk);
-+				BTC_TRACE(trace_buf);
-+				break;
-+			}
-+		}
-+
-+
-+		/* set Path control owner to WL at initial step */
-+		halbtc8703b1ant_ltecoex_pathcontrol_owner(
-+			btcoexist,
-+			BT_8703B_1ANT_PCO_WLSIDE);
-+
-+		/* set GNT_BT to SW high */
-+		halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
-+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
-+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
-+					   BT_8703B_1ANT_SIG_STA_SET_TO_HIGH);
-+		/* Set GNT_WL to SW low */
-+		halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
-+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
-+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
-+					   BT_8703B_1ANT_SIG_STA_SET_TO_LOW);
-+
-+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
-+			ant_pos_type = BTC_ANT_PATH_BT;
-+
-+		coex_sta->run_time_state = FALSE;
-+		break;
-+	case BT_8703B_1ANT_PHASE_WLANONLY_INIT:
-+		/* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
-+		halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0);
-+
-+		/* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
-+		halbtc8703b1ant_ltecoex_set_coex_table(
-+			btcoexist,
-+			BT_8703B_1ANT_CTT_WL_VS_LTE,
-+			0xffff);
-+
-+		/* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
-+		halbtc8703b1ant_ltecoex_set_coex_table(
-+			btcoexist,
-+			BT_8703B_1ANT_CTT_BT_VS_LTE,
-+			0xffff);
-+
-+		/* set Path control owner to WL at initial step */
-+		halbtc8703b1ant_ltecoex_pathcontrol_owner(
-+			btcoexist,
-+			BT_8703B_1ANT_PCO_WLSIDE);
-+
-+		/* set GNT_BT to SW low */
-+		halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
-+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
-+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
-+					   BT_8703B_1ANT_SIG_STA_SET_TO_LOW);
-+		/* Set GNT_WL to SW high */
-+		halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
-+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
-+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
-+					   BT_8703B_1ANT_SIG_STA_SET_TO_HIGH);
-+
-+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
-+			ant_pos_type =
-+				BTC_ANT_PATH_WIFI;
-+
-+		coex_sta->run_time_state = FALSE;
-+		break;
-+	case BT_8703B_1ANT_PHASE_WLAN_OFF:
-+		/* Disable LTE Coex Function in WiFi side */
-+		halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0);
-+
-+		/* set Path control owner to BT */
-+		halbtc8703b1ant_ltecoex_pathcontrol_owner(
-+			btcoexist,
-+			BT_8703B_1ANT_PCO_BTSIDE);
-+
-+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
-+			ant_pos_type = BTC_ANT_PATH_BT;
-+
-+		coex_sta->run_time_state = FALSE;
-+		break;
-+	case BT_8703B_1ANT_PHASE_2G_RUNTIME:
-+		halbtc8703b1ant_ltecoex_pathcontrol_owner(
-+			btcoexist,
-+			BT_8703B_1ANT_PCO_WLSIDE);
-+
-+		/* set GNT_BT to PTA */
-+		halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
-+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
-+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA,
-+					   BT_8703B_1ANT_SIG_STA_SET_BY_HW);
-+		/* Set GNT_WL to PTA */
-+		halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
-+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
-+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA,
-+					   BT_8703B_1ANT_SIG_STA_SET_BY_HW);
-+
-+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
-+			ant_pos_type = BTC_ANT_PATH_PTA;
-+
-+		coex_sta->run_time_state = TRUE;
-+		break;
-+	case BT_8703B_1ANT_PHASE_BTMPMODE:
-+		halbtc8703b1ant_ltecoex_pathcontrol_owner(
-+			btcoexist,
-+			BT_8703B_1ANT_PCO_WLSIDE);
-+
-+		/* set GNT_BT to high */
-+		halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
-+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
-+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
-+					   BT_8703B_1ANT_SIG_STA_SET_TO_HIGH);
-+		/* Set GNT_WL to low */
-+		halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
-+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
-+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
-+					   BT_8703B_1ANT_SIG_STA_SET_TO_LOW);
-+
-+		if (BTC_ANT_PATH_AUTO == ant_pos_type)
-+			ant_pos_type = BTC_ANT_PATH_BT;
-+
-+		coex_sta->run_time_state = FALSE;
-+		break;
-+	}
-+
-+
-+#if 1
-+	u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
-+	u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-+	u8tmp  = btcoexist->btc_read_1byte(btcoexist, 0x73);
-+
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		"[BTCoex], ********** (After Ant-Setup) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
-+		    u8tmp, u32tmp1, u32tmp2);
-+	BTC_TRACE(trace_buf);
-+
-+#endif
-+}
-+
-+
-+boolean halbtc8703b1ant_is_common_action(IN struct btc_coexist *btcoexist)
-+{
-+	boolean			common = FALSE, wifi_connected = FALSE, wifi_busy = FALSE;
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
-+			   &wifi_connected);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-+
-+	if (!wifi_connected &&
-+	    BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
-+	    coex_dm->bt_status) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
-+		BTC_TRACE(trace_buf);
-+		common = TRUE;
-+	} else if (wifi_connected &&
-+		   (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
-+		    coex_dm->bt_status)) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], Wifi connected + BT non connected-idle!!\n");
-+		BTC_TRACE(trace_buf);
-+		common = TRUE;
-+	} else if (!wifi_connected &&
-+		   (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE ==
-+		    coex_dm->bt_status)) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
-+		BTC_TRACE(trace_buf);
-+		common = TRUE;
-+	} else if (wifi_connected &&
-+		   (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE ==
-+		    coex_dm->bt_status)) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], Wifi connected + BT connected-idle!!\n");
-+		BTC_TRACE(trace_buf);
-+		common = TRUE;
-+	} else if (!wifi_connected &&
-+		   (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE !=
-+		    coex_dm->bt_status)) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
-+		BTC_TRACE(trace_buf);
-+		common = TRUE;
-+	} else {
-+		if (wifi_busy) {
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
-+			BTC_TRACE(trace_buf);
-+		} else {
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
-+			BTC_TRACE(trace_buf);
-+		}
-+
-+		common = FALSE;
-+	}
-+
-+	return common;
-+}
-+
-+
-+/* *********************************************
-+ *
-+ *	Non-Software Coex Mechanism start
-+ *
-+ * ********************************************* */
-+u8 halbtc8703b1ant_action_algorithm(IN struct btc_coexist *btcoexist)
-+{
-+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
-+	boolean	bt_hs_on = FALSE;
-+	u8	algorithm = BT_8703B_1ANT_COEX_ALGO_UNDEFINED;
-+	u8	num_of_diff_profile = 0;
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-+
-+	if (!bt_link_info->bt_link_exist) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], No BT link exists!!!\n");
-+		BTC_TRACE(trace_buf);
-+		return algorithm;
-+	}
-+
-+	if (bt_link_info->sco_exist)
-+		num_of_diff_profile++;
-+	if (bt_link_info->hid_exist)
-+		num_of_diff_profile++;
-+	if (bt_link_info->pan_exist)
-+		num_of_diff_profile++;
-+	if (bt_link_info->a2dp_exist)
-+		num_of_diff_profile++;
-+
-+	if (num_of_diff_profile == 1) {
-+		if (bt_link_info->sco_exist) {
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				    "[BTCoex], BT Profile = SCO only\n");
-+			BTC_TRACE(trace_buf);
-+			algorithm = BT_8703B_1ANT_COEX_ALGO_SCO;
-+		} else {
-+			if (bt_link_info->hid_exist) {
-+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+					"[BTCoex], BT Profile = HID only\n");
-+				BTC_TRACE(trace_buf);
-+				algorithm = BT_8703B_1ANT_COEX_ALGO_HID;
-+			} else if (bt_link_info->a2dp_exist) {
-+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+					"[BTCoex], BT Profile = A2DP only\n");
-+				BTC_TRACE(trace_buf);
-+				algorithm = BT_8703B_1ANT_COEX_ALGO_A2DP;
-+			} else if (bt_link_info->pan_exist) {
-+				if (bt_hs_on) {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = PAN(HS) only\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm =
-+						BT_8703B_1ANT_COEX_ALGO_PANHS;
-+				} else {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = PAN(EDR) only\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm =
-+						BT_8703B_1ANT_COEX_ALGO_PANEDR;
-+				}
-+			}
-+		}
-+	} else if (num_of_diff_profile == 2) {
-+		if (bt_link_info->sco_exist) {
-+			if (bt_link_info->hid_exist) {
-+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+					"[BTCoex], BT Profile = SCO + HID\n");
-+				BTC_TRACE(trace_buf);
-+				algorithm = BT_8703B_1ANT_COEX_ALGO_HID;
-+			} else if (bt_link_info->a2dp_exist) {
-+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+					"[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
-+				BTC_TRACE(trace_buf);
-+				algorithm = BT_8703B_1ANT_COEX_ALGO_SCO;
-+			} else if (bt_link_info->pan_exist) {
-+				if (bt_hs_on) {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = SCO + PAN(HS)\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm = BT_8703B_1ANT_COEX_ALGO_SCO;
-+				} else {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = SCO + PAN(EDR)\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm =
-+						BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
-+				}
-+			}
-+		} else {
-+			if (bt_link_info->hid_exist &&
-+			    bt_link_info->a2dp_exist) {
-+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+					"[BTCoex], BT Profile = HID + A2DP\n");
-+				BTC_TRACE(trace_buf);
-+				algorithm = BT_8703B_1ANT_COEX_ALGO_HID_A2DP;
-+			} else if (bt_link_info->hid_exist &&
-+				   bt_link_info->pan_exist) {
-+				if (bt_hs_on) {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = HID + PAN(HS)\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm =
-+						BT_8703B_1ANT_COEX_ALGO_HID_A2DP;
-+				} else {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = HID + PAN(EDR)\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm =
-+						BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
-+				}
-+			} else if (bt_link_info->pan_exist &&
-+				   bt_link_info->a2dp_exist) {
-+				if (bt_hs_on) {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = A2DP + PAN(HS)\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm =
-+						BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS;
-+				} else {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm =
-+						BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP;
-+				}
-+			}
-+		}
-+	} else if (num_of_diff_profile == 3) {
-+		if (bt_link_info->sco_exist) {
-+			if (bt_link_info->hid_exist &&
-+			    bt_link_info->a2dp_exist) {
-+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+					"[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
-+				BTC_TRACE(trace_buf);
-+				algorithm = BT_8703B_1ANT_COEX_ALGO_HID;
-+			} else if (bt_link_info->hid_exist &&
-+				   bt_link_info->pan_exist) {
-+				if (bt_hs_on) {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm =
-+						BT_8703B_1ANT_COEX_ALGO_HID_A2DP;
-+				} else {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm =
-+						BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
-+				}
-+			} else if (bt_link_info->pan_exist &&
-+				   bt_link_info->a2dp_exist) {
-+				if (bt_hs_on) {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm = BT_8703B_1ANT_COEX_ALGO_SCO;
-+				} else {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm =
-+						BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
-+				}
-+			}
-+		} else {
-+			if (bt_link_info->hid_exist &&
-+			    bt_link_info->pan_exist &&
-+			    bt_link_info->a2dp_exist) {
-+				if (bt_hs_on) {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm =
-+						BT_8703B_1ANT_COEX_ALGO_HID_A2DP;
-+				} else {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm =
-+						BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
-+				}
-+			}
-+		}
-+	} else if (num_of_diff_profile >= 3) {
-+		if (bt_link_info->sco_exist) {
-+			if (bt_link_info->hid_exist &&
-+			    bt_link_info->pan_exist &&
-+			    bt_link_info->a2dp_exist) {
-+				if (bt_hs_on) {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
-+					BTC_TRACE(trace_buf);
-+
-+				} else {
-+					BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+						"[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
-+					BTC_TRACE(trace_buf);
-+					algorithm =
-+						BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
-+				}
-+			}
-+		}
-+	}
-+
-+	return algorithm;
-+}
-+
-+void halbtc8703b1ant_action_bt_whql_test(IN struct btc_coexist *btcoexist)
-+{
-+	halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
-+				     BT_8703B_1ANT_PHASE_2G_RUNTIME);
-+	halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-+	halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
-+}
-+
-+void halbtc8703b1ant_action_bt_hs(IN struct btc_coexist *btcoexist)
-+{
-+	halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-+	halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 5);
-+}
-+
-+void halbtc8703b1ant_action_bt_relink(IN struct btc_coexist *btcoexist)
-+{
-+	if (coex_sta->is_bt_multi_link == TRUE)
-+		return;
-+
-+	halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
-+	halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 5);
-+}
-+
-+void halbtc8703b1ant_action_bt_idle(IN struct btc_coexist *btcoexist)
-+{
-+	boolean wifi_busy = FALSE;
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-+
-+	if (!wifi_busy) {
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 6);
-+	} else {/* if wl busy */
-+
-+	if (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
-+			coex_dm->bt_status) {
-+
-+		if (coex_sta->is_hiPri_rx_overhead)
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
-+		else
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
-+
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33);
-+	} else {
-+
-+	   halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
-+	   halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32);
-+	  }
-+	}
-+}
-+
-+void halbtc8703b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
-+{
-+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-+	boolean			wifi_connected = FALSE, ap_enable = FALSE, wifi_busy = FALSE,
-+				bt_busy = FALSE;
-+	boolean	wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE;
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
-+			   &ap_enable);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
-+			   &wifi_connected);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-+	btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
-+
-+	if ((wifi_link) || (wifi_roam)  || (coex_sta->wifi_is_high_pri_task)) {
-+
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33);
-+	} else if ((wifi_scan) && (coex_sta->bt_create_connection)) {
-+
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33);
-+	} else if ((!wifi_connected) && (!wifi_scan)) {
-+
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
-+	}  else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) {
-+
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 6);
-+	} else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) {
-+
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22);
-+	} else if (bt_link_info->a2dp_exist) {
-+
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32);
-+	} else if (wifi_scan) {
-+
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 20);
-+	} else if (wifi_busy) {
-+
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21);
-+	} else {
-+
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21);
-+	}
-+}
-+
-+void halbtc8703b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
-+		*btcoexist)
-+{
-+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-+	boolean	wifi_connected = FALSE, wifi_busy = FALSE, wifi_cckdeadlock_ap = FALSE;
-+	u32  wifi_bw = 1;
-+	u8	iot_peer = BTC_IOT_PEER_UNKNOWN;
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
-+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-+	btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
-+
-+	if ((iot_peer == BTC_IOT_PEER_ATHEROS) && (coex_sta->cck_lock_ever))
-+		wifi_cckdeadlock_ap = TRUE;
-+
-+	if (bt_link_info->sco_exist) {
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC,	TRUE, 5);
-+	} else if (coex_sta->is_hid_rcu) {
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
-+
-+		if (wifi_busy)
-+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 36);
-+		else
-+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 6);
-+	} else {
-+
-+		if ((wifi_cckdeadlock_ap) && (coex_sta->is_bt_multi_link)) {
-+
-+			if (coex_sta->hid_busy_num < 2)
-+				halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14);
-+			else
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13);
-+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 18);
-+		} else if (coex_sta->is_bt_multi_link) {
-+			if (coex_sta->hid_busy_num < 2)
-+				halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
-+			else
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
-+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 18);
-+		} else if (coex_sta->hid_busy_num < 2) {
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
-+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 11);
-+		} else if (wifi_bw == 0) { /* if 11bg mode */
-+
-+			if (coex_sta->is_bt_multi_link) {
-+				halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
-+							11);
-+				halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 11);
-+			} else {
-+				halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
-+							11);
-+				halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 11);
-+			}
-+		} else {
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
-+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 11);
-+		}
-+	}
-+}
-+
-+
-+void halbtc8703b1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
-+{
-+	halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
-+				     BT_8703B_1ANT_PHASE_2G_RUNTIME);
-+	halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 10);
-+	halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8);
-+}
-+
-+void halbtc8703b1ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist)
-+{
-+	halbtc8703b1ant_coex_table_with_type(btcoexist,
-+					     NORMAL_EXEC, 5);
-+	halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
-+}
-+
-+void halbtc8703b1ant_action_wifi_cck_dead_lock(IN struct btc_coexist *btcoexist)
-+{
-+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-+
-+	if ((bt_link_info->hid_exist) && (bt_link_info->a2dp_exist) &&
-+		(!bt_link_info->pan_exist)) {
-+
-+		if ((coex_sta->cck_lock) || (coex_sta->cck_lock_warn)) {
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13);
-+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 28);
-+		} else {
-+
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13);
-+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 8);
-+		}
-+	}
-+}
-+
-+void halbtc8703b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
-+{
-+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-+
-+	halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC,
-+				     BT_8703B_1ANT_PHASE_2G_RUNTIME);
-+
-+	if ((BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
-+		coex_dm->bt_status) ||
-+		(BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE ==
-+		coex_dm->bt_status))
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
-+	else if (!bt_link_info->pan_exist)
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-+	else
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-+
-+	halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
-+}
-+
-+void halbtc8703b1ant_action_wifi_linkscan_process(IN struct btc_coexist
-+		*btcoexist)
-+{
-+	struct  btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-+
-+	halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-+
-+	if (bt_link_info->pan_exist)
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22);
-+	else if (bt_link_info->a2dp_exist)
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 27);
-+	else
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21);
-+}
-+
-+void halbtc8703b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
-+		*btcoexist)
-+{
-+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-+	boolean wifi_busy = FALSE, wifi_turbo = FALSE, wifi_cckdeadlock_ap = FALSE;
-+	u32  wifi_bw = 1;
-+	u8	iot_peer = BTC_IOT_PEER_UNKNOWN;
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-+	btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num);
-+	btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		"############# [BTCoex],  scan_ap_num = %d, wl_noisy_level = %d\n",
-+			coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
-+	BTC_TRACE(trace_buf);
-+
-+	if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
-+		wifi_turbo = TRUE;
-+
-+	if ((iot_peer == BTC_IOT_PEER_ATHEROS) && (coex_sta->cck_lock_ever))
-+		wifi_cckdeadlock_ap = TRUE;
-+
-+	if ((bt_link_info->a2dp_exist) && (coex_sta->is_bt_a2dp_sink)) {
-+
-+		if (wifi_cckdeadlock_ap)
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13);
-+		else
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
-+
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 12);
-+	} else if (bt_link_info->a2dp_only) { /* A2DP		 */
-+
-+		if (wifi_cckdeadlock_ap)
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13);
-+		else if (wifi_turbo)
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
-+		else
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-+
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 7);
-+	} else if (((bt_link_info->a2dp_exist) &&
-+			(bt_link_info->pan_exist)) ||
-+			(bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
-+		bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
-+
-+		if (wifi_cckdeadlock_ap) {
-+			if ((bt_link_info->hid_exist) && (coex_sta->hid_busy_num < 2))
-+				halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14);
-+			else
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13);
-+		} else if (bt_link_info->hid_exist) {
-+			if (coex_sta->hid_busy_num < 2)
-+				halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
-+			else
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
-+		} else if (wifi_turbo)
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
-+		else
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-+
-+		if (wifi_busy)
-+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 13);
-+		else
-+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 14);
-+	} else if (bt_link_info->hid_exist &&
-+		   bt_link_info->a2dp_exist) { /* HID+A2DP */
-+
-+		if (wifi_cckdeadlock_ap) {
-+#if 1
-+			if (coex_sta->hid_busy_num < 2)
-+				halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14);
-+			else
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13);
-+
-+			if (coex_sta->hid_pair_cnt > 1)
-+				halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 24);
-+			else
-+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 8);
-+#endif
-+
-+#if 0
-+			halbtc8703b1ant_action_wifi_cck_dead_lock(btcoexist);
-+#endif
-+		} else {
-+			if (coex_sta->hid_busy_num < 2) /* 2/18 HID */
-+				halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
-+			else if (wifi_bw == 0)/* if 11bg mode */
-+				halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 12);
-+			else
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
-+
-+			if (coex_sta->hid_pair_cnt > 1)
-+				halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 24);
-+			else
-+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 8);
-+		}
-+	} else if ((bt_link_info->pan_only)
-+		   || (bt_link_info->hid_exist && bt_link_info->pan_exist)) {
-+			/* PAN(OPP,FTP), HID+PAN(OPP,FTP) */
-+
-+		if (wifi_cckdeadlock_ap) {
-+			if ((bt_link_info->hid_exist) && (coex_sta->hid_busy_num < 2))
-+				halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14);
-+			else
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13);
-+		} else if (bt_link_info->hid_exist) {
-+			if (coex_sta->hid_busy_num < 2)
-+				halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
-+			else
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
-+		} else if (wifi_turbo)
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
-+		else
-+			halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-+
-+		if (!wifi_busy)
-+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 4);
-+		else
-+			halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 3);
-+	} else {
-+		/* BT no-profile busy (0x9) */
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33);
-+	}
-+
-+}
-+
-+
-+void halbtc8703b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
-+{
-+	/* tdma and coex table */
-+	halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-+	halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8);
-+}
-+
-+void halbtc8703b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
-+{
-+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-+	boolean wifi_busy = FALSE;
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], CoexForWifiConnect()===>\n");
-+	BTC_TRACE(trace_buf);
-+
-+	halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
-+					NORMAL_EXEC,
-+					BT_8703B_1ANT_PHASE_2G_RUNTIME);
-+
-+	if ((coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_ACL_BUSY) ||
-+		(coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY)) {
-+
-+		if (bt_link_info->hid_only)/* HID only */
-+			halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist);
-+		else
-+			halbtc8703b1ant_action_wifi_connected_bt_acl_busy(btcoexist);
-+
-+	} else if (coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_SCO_BUSY)
-+		halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist);
-+	else
-+		halbtc8703b1ant_action_bt_idle(btcoexist);
-+}
-+
-+
-+void halbtc8703b1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
-+{
-+	u8	algorithm = 0;
-+
-+	algorithm = halbtc8703b1ant_action_algorithm(btcoexist);
-+	coex_dm->cur_algorithm = algorithm;
-+
-+	if (halbtc8703b1ant_is_common_action(btcoexist)) {
-+
-+	} else {
-+		switch (coex_dm->cur_algorithm) {
-+		case BT_8703B_1ANT_COEX_ALGO_SCO:
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				    "[BTCoex], Action algorithm = SCO.\n");
-+			BTC_TRACE(trace_buf);
-+			break;
-+		case BT_8703B_1ANT_COEX_ALGO_HID:
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				    "[BTCoex], Action algorithm = HID.\n");
-+			BTC_TRACE(trace_buf);
-+			break;
-+		case BT_8703B_1ANT_COEX_ALGO_A2DP:
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				    "[BTCoex], Action algorithm = A2DP.\n");
-+			BTC_TRACE(trace_buf);
-+			break;
-+		case BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS:
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
-+			BTC_TRACE(trace_buf);
-+			break;
-+		case BT_8703B_1ANT_COEX_ALGO_PANEDR:
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				    "[BTCoex], Action algorithm = PAN(EDR).\n");
-+			BTC_TRACE(trace_buf);
-+			break;
-+		case BT_8703B_1ANT_COEX_ALGO_PANHS:
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				    "[BTCoex], Action algorithm = HS mode.\n");
-+			BTC_TRACE(trace_buf);
-+			break;
-+		case BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP:
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				    "[BTCoex], Action algorithm = PAN+A2DP.\n");
-+			BTC_TRACE(trace_buf);
-+			break;
-+		case BT_8703B_1ANT_COEX_ALGO_PANEDR_HID:
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
-+			BTC_TRACE(trace_buf);
-+			break;
-+		case BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
-+			BTC_TRACE(trace_buf);
-+			break;
-+		case BT_8703B_1ANT_COEX_ALGO_HID_A2DP:
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				    "[BTCoex], Action algorithm = HID+A2DP.\n");
-+			BTC_TRACE(trace_buf);
-+			break;
-+		default:
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], Action algorithm = coexist All Off!!\n");
-+			BTC_TRACE(trace_buf);
-+			break;
-+		}
-+		coex_dm->pre_algorithm = coex_dm->cur_algorithm;
-+	}
-+}
-+
-+void halbtc8703b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
-+{
-+	struct	btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-+	boolean wifi_connected = FALSE, bt_hs_on = FALSE;
-+	boolean increase_scan_dev_num = FALSE;
-+	boolean bt_ctrl_agg_buf_size = FALSE;
-+	boolean miracast_plus_bt = FALSE, wifi_under_5g = FALSE;
-+	u8	agg_buf_size = 5;
-+	u32 wifi_link_status = 0;
-+	u32 num_of_wifi_link = 0, wifi_bw;
-+	u8	iot_peer = BTC_IOT_PEER_UNKNOWN;
-+	boolean scan = FALSE, link = FALSE, roam = FALSE, under_4way = FALSE;
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], RunCoexistMechanism()===>\n");
-+	BTC_TRACE(trace_buf);
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], under_lps = %d, force_lps_ctrl = %d, acl_busy = %d!!!\n",
-+			coex_sta->under_lps, coex_sta->force_lps_ctrl, coex_sta->acl_busy);
-+	BTC_TRACE(trace_buf);
-+
-+	if (btcoexist->manual_control) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
-+		BTC_TRACE(trace_buf);
-+		return;
-+	}
-+
-+	if (btcoexist->stop_coex_dm) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
-+		BTC_TRACE(trace_buf);
-+		return;
-+	}
-+
-+	if (coex_sta->under_ips) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], wifi is under IPS !!!\n");
-+		BTC_TRACE(trace_buf);
-+		return;
-+	}
-+
-+	if (!coex_sta->run_time_state) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], return for run_time_state = FALSE !!!\n");
-+		BTC_TRACE(trace_buf);
-+		return;
-+	}
-+
-+	if (coex_sta->freeze_coexrun_by_btinfo) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], return for freeze_coexrun_by_btinfo\n");
-+		BTC_TRACE(trace_buf);
-+		return;
-+	}
-+
-+	if ((coex_sta->under_lps) && (!coex_sta->force_lps_ctrl) &&
-+		(!coex_sta->acl_busy)) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n");
-+		BTC_TRACE(trace_buf);
-+		halbtc8703b1ant_action_wifi_native_lps(btcoexist);
-+		return;
-+	}
-+
-+	if (coex_sta->bt_whck_test) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], BT is under WHCK TEST!!!\n");
-+		BTC_TRACE(trace_buf);
-+		halbtc8703b1ant_action_bt_whql_test(btcoexist);
-+		return;
-+	}
-+
-+	if (coex_sta->bt_disabled) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], BT is disabled !!!\n");
-+		halbtc8703b1ant_action_wifi_only(btcoexist);
-+		return;
-+	}
-+
-+	if (coex_sta->c2h_bt_inquiry_page) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], BT is under inquiry/page scan !!\n");
-+		BTC_TRACE(trace_buf);
-+		halbtc8703b1ant_action_bt_inquiry(btcoexist);
-+		return;
-+	}
-+
-+	if ((coex_sta->is_setupLink) &&
-+			(coex_sta->bt_relink_downcount != 0)) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		"[BTCoex], BT is re-link !!!\n");
-+		halbtc8703b1ant_action_bt_relink(btcoexist);
-+		return;
-+	}
-+
-+	if ((BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
-+		(BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
-+		(BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
-+		increase_scan_dev_num = TRUE;
-+
-+	btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
-+				&increase_scan_dev_num);
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
-+				&wifi_link_status);
-+
-+	num_of_wifi_link = wifi_link_status >> 16;
-+
-+	if ((num_of_wifi_link >= 2) ||
-+		(wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"############# [BTCoex],  Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
-+				num_of_wifi_link, wifi_link_status);
-+		BTC_TRACE(trace_buf);
-+
-+		if (bt_link_info->bt_link_exist)
-+			miracast_plus_bt = TRUE;
-+		else
-+			miracast_plus_bt = FALSE;
-+
-+		btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
-+				   &miracast_plus_bt);
-+
-+		halbtc8703b1ant_action_wifi_multi_port(btcoexist);
-+
-+		return;
-+	}
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
-+
-+	if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
-+
-+		btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
-+
-+		if (BTC_IOT_PEER_CISCO == iot_peer) {
-+
-+			if (BTC_WIFI_BW_HT40 == wifi_bw)
-+					halbtc8703b1ant_limited_rx(btcoexist,
-+						NORMAL_EXEC, FALSE, TRUE, 0x10);
-+			else
-+					halbtc8703b1ant_limited_rx(btcoexist,
-+						NORMAL_EXEC, FALSE, TRUE, 0x8);
-+		}
-+	}
-+
-+	halbtc8703b1ant_run_sw_coexist_mechanism(
-+			btcoexist);  /* just print debug message */
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-+
-+	if (bt_hs_on) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"############# [BTCoex],  BT Is hs\n");
-+		BTC_TRACE(trace_buf);
-+		halbtc8703b1ant_action_bt_hs(btcoexist);
-+		return;
-+	}
-+
-+	if ((BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
-+			coex_dm->bt_status) ||
-+		(BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE ==
-+			coex_dm->bt_status)) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"############# [BTCoex],  BT Is idle\n");
-+		BTC_TRACE(trace_buf);
-+		halbtc8703b1ant_action_bt_idle(btcoexist);
-+		return;
-+	}
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
-+			&under_4way);
-+
-+	if (scan || link || roam || under_4way) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n",
-+					scan, link, roam, under_4way);
-+		BTC_TRACE(trace_buf);
-+
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], wifi is under linkscan process!!\n");
-+		BTC_TRACE(trace_buf);
-+
-+		halbtc8703b1ant_action_wifi_linkscan_process(btcoexist);
-+	} else if (wifi_connected) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], wifi is under connected!!\n");
-+		BTC_TRACE(trace_buf);
-+
-+		halbtc8703b1ant_action_wifi_connected(btcoexist);
-+	} else {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], wifi is under not-connected!!\n");
-+		BTC_TRACE(trace_buf);
-+
-+		halbtc8703b1ant_action_wifi_not_connected(btcoexist);
-+	 }
-+}
-+
-+
-+void halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-+{
-+	/* force to reset coex mechanism */
-+
-+	halbtc8703b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE);
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		    "[BTCoex], Coex Mechanism Init!!\n");
-+	BTC_TRACE(trace_buf);
-+
-+	coex_sta->pop_event_cnt = 0;
-+	coex_sta->cnt_RemoteNameReq = 0;
-+	coex_sta->cnt_ReInit = 0;
-+	coex_sta->cnt_setupLink = 0;
-+	coex_sta->cnt_IgnWlanAct = 0;
-+	coex_sta->cnt_Page = 0;
-+	coex_sta->cnt_RoleSwitch = 0;
-+}
-+
-+void halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
-+				    IN boolean back_up, IN boolean wifi_only)
-+{
-+	u32				u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0;
-+	u8 i = 0;
-+
-+	u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70),
-+	u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
-+	u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		"\n [BTCoex], ********** 0x70/ 0x38/ 0x54 (Before Init HW config) = 0x%x/ 0x%x/ 0x%x**********\n",
-+		    u32tmp0,
-+		    u32tmp1, u32tmp2);
-+	BTC_TRACE(trace_buf);
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		    "[BTCoex], 1Ant Init HW Config!!\n");
-+	BTC_TRACE(trace_buf);
-+
-+	coex_sta->bt_coex_supported_feature = 0;
-+	coex_sta->bt_coex_supported_version = 0;
-+	coex_sta->bt_ble_scan_type = 0;
-+	coex_sta->bt_ble_scan_para[0] = 0;
-+	coex_sta->bt_ble_scan_para[1] = 0;
-+	coex_sta->bt_ble_scan_para[2] = 0;
-+	coex_sta->gnt_error_cnt = 0;
-+	coex_sta->bt_relink_downcount = 0;
-+	coex_sta->wl_rx_rate = BTC_UNKNOWN;
-+
-+	for (i = 0; i <= 9; i++)
-+		coex_sta->bt_afh_map[i] = 0;
-+
-+	/* 0xf0[15:12] --> Chip Cut information */
-+	coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
-+				 0xf1) & 0xf0) >> 4;
-+
-+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
-+					   0x1);  /* enable TBTT nterrupt */
-+
-+	/* BT report packet sample rate	 */
-+	btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5);
-+
-+	/* Enable BT counter statistics */
-+	btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
-+
-+	/* Enable PTA (3-wire function form BT side) */
-+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
-+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
-+
-+	/* Enable PTA (tx/rx signal form WiFi side) */
-+	btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
-+
-+	halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, FALSE);
-+
-+#if 0
-+	if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)
-+		halbtc8703b1ant_post_state_to_bt(btcoexist,
-+					 BT_8703B_1ANT_SCOREBOARD_ONOFF, TRUE);
-+#endif
-+
-+	/* Antenna config */
-+	if (coex_sta->is_rf_state_off) {
-+
-+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
-+					     FORCE_EXEC,
-+					     BT_8703B_1ANT_PHASE_WLAN_OFF);
-+
-+		btcoexist->stop_coex_dm = TRUE;
-+
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], **********  halbtc8703b1ant_init_hw_config (RF Off)**********\n");
-+		BTC_TRACE(trace_buf);
-+	} else if (wifi_only) {
-+		coex_sta->concurrent_rx_mode_on = FALSE;
-+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
-+					     FORCE_EXEC,
-+					     BT_8703B_1ANT_PHASE_WLANONLY_INIT);
-+	} else {
-+		coex_sta->concurrent_rx_mode_on = TRUE;
-+		btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1);
-+		/* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */
-+		btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0);
-+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
-+					     FORCE_EXEC,
-+					     BT_8703B_1ANT_PHASE_COEX_INIT);
-+	}
-+
-+	/* PTA parameter */
-+	halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-+	halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8);
-+
-+	u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70),
-+	u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
-+	u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		"[BTCoex], ********** 0x70/ 0x38/ 0x54 (After Init HW config) = 0x%x/ 0x%x/ 0x%x**********\n",
-+		    u32tmp0,
-+		    u32tmp1, u32tmp2);
-+	BTC_TRACE(trace_buf);
-+
-+}
-+
-+
-+
-+/* ************************************************************
-+ * work around function start with wa_halbtc8703b1ant_
-+ * ************************************************************
-+ * ************************************************************
-+ * extern function start with ex_halbtc8703b1ant_
-+ * ************************************************************ */
-+void ex_halbtc8703b1ant_power_on_setting(IN struct btc_coexist *btcoexist)
-+{
-+	struct  btc_board_info	*board_info = &btcoexist->board_info;
-+	u8 u8tmp = 0x0;
-+	u16 u16tmp = 0x0;
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		"xxxxxxxxxxxxxxxx Execute 8703b 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
-+	BTC_TRACE(trace_buf);
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		    "Ant Det Finish = %s, Ant Det Number  = %d\n",
-+		    (board_info->btdm_ant_det_finish ? "Yes" : "No"),
-+		    board_info->btdm_ant_num_by_ant_det);
-+	BTC_TRACE(trace_buf);
-+
-+	btcoexist->stop_coex_dm = TRUE;
-+	coex_sta->is_rf_state_off = FALSE;
-+
-+	/* enable BB, REG_SYS_FUNC_EN such that we can write BB/MAC reg correctly. */
-+	u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
-+	btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
-+
-+	/* set Path control owner to WiFi */
-+	halbtc8703b1ant_ltecoex_pathcontrol_owner(btcoexist,
-+			BT_8703B_1ANT_PCO_WLSIDE);
-+
-+	/* set GNT_BT to high */
-+	halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
-+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
-+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
-+					   BT_8703B_1ANT_SIG_STA_SET_TO_HIGH);
-+	/* Set GNT_WL to low */
-+	halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
-+					   BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
-+					   BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
-+					   BT_8703B_1ANT_SIG_STA_SET_TO_LOW);
-+
-+	/* set WLAN_ACT = 0 */
-+	/*btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);*/
-+
-+	halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, FALSE);
-+
-+	/* */
-+	/* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
-+	/* Local setting bit define */
-+	/*	BIT0: "0" for no antenna inverse; "1" for antenna inverse  */
-+	/*	BIT1: "0" for internal switch; "1" for external switch */
-+	/*	BIT2: "0" for one antenna; "1" for two antenna */
-+	/* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
-+
-+	u8tmp = 0;
-+	board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
-+
-+	if (btcoexist->chip_interface == BTC_INTF_USB)
-+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
-+	else if (btcoexist->chip_interface == BTC_INTF_SDIO)
-+		btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
-+
-+
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		"[BTCoex], **********  0x70(MAC)/0x38/0x54 (Power-On) =0x%x/  0x%x/ 0x%x**********\n",
-+		    btcoexist->btc_read_4byte(btcoexist, 0x70),
-+		    halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38),
-+		    halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54));
-+	BTC_TRACE(trace_buf);
-+
-+
-+}
-+
-+void ex_halbtc8703b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
-+{
-+}
-+
-+void ex_halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
-+				       IN boolean wifi_only)
-+{
-+	halbtc8703b1ant_init_hw_config(btcoexist, TRUE, wifi_only);
-+	btcoexist->stop_coex_dm = FALSE;
-+}
-+
-+void ex_halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-+{
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		    "[BTCoex], Coex Mechanism Init!!\n");
-+	BTC_TRACE(trace_buf);
-+
-+	halbtc8703b1ant_init_coex_dm(btcoexist);
-+}
-+
-+void ex_halbtc8703b1ant_display_coex_info(IN struct btc_coexist *btcoexist)
-+{
-+	struct  btc_board_info		*board_info = &btcoexist->board_info;
-+	struct  btc_stack_info		*stack_info = &btcoexist->stack_info;
-+	struct  btc_bt_link_info	*bt_link_info = &btcoexist->bt_link_info;
-+	u8				*cli_buf = btcoexist->cli_buf;
-+	u8				u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
-+	u16				u16tmp[4];
-+	u32				u32tmp[4];
-+	u32				fa_ofdm, fa_cck, cca_ofdm, cca_cck;
-+	u32				fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
-+	static u8			pop_report_in_10s = 0, cnt = 0;
-+	u32				phyver = 0;
-+	boolean			lte_coex_on = FALSE;
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+		   "\r\n ============[BT Coexist info]============");
-+	CL_PRINTF(cli_buf);
-+
-+	if (btcoexist->manual_control) {
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+			"\r\n ============[Under Manual Control]============");
-+		CL_PRINTF(cli_buf);
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+			   "\r\n ==========================================");
-+		CL_PRINTF(cli_buf);
-+	}
-+	if (btcoexist->stop_coex_dm) {
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+			   "\r\n ============[Coex is STOPPED]============");
-+		CL_PRINTF(cli_buf);
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+			   "\r\n ==========================================");
-+		CL_PRINTF(cli_buf);
-+	}
-+
-+	if (!coex_sta->bt_disabled) {
-+		if (coex_sta->bt_coex_supported_feature == 0)
-+			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE,
-+						&coex_sta->bt_coex_supported_feature);
-+
-+		if ((coex_sta->bt_coex_supported_version == 0) ||
-+			 (coex_sta->bt_coex_supported_version == 0xffff))
-+			btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION,
-+						&coex_sta->bt_coex_supported_version);
-+
-+		btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
-+		btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
-+
-+		if (coex_sta->num_of_profile > 0) {
-+			cnt++;
-+
-+			if (cnt >= 3) {
-+				btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0,
-+					&coex_sta->bt_afh_map[0]);
-+				cnt = 0;
-+			}
-+		}
-+	}
-+
-+	if (psd_scan->ant_det_try_count == 0) {
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
-+			   "Ant PG Num/ Mech/ Pos",
-+			   board_info->pg_ant_num, board_info->btdm_ant_num,
-+			   board_info->btdm_ant_pos);
-+		CL_PRINTF(cli_buf);
-+	} else {
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+			   "\r\n %-35s = %d/ %d/ %d  (%d/%d/%d)",
-+			   "Ant PG Num/ Mech(Ant_Det)/ Pos",
-+			   board_info->pg_ant_num,
-+			   board_info->btdm_ant_num_by_ant_det,
-+			   board_info->btdm_ant_pos,
-+			   psd_scan->ant_det_try_count,
-+			   psd_scan->ant_det_fail_count,
-+			   psd_scan->ant_det_result);
-+		CL_PRINTF(cli_buf);
-+
-+		if (board_info->btdm_ant_det_finish) {
-+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
-+				   "Ant Det PSD Value",
-+				   psd_scan->ant_det_peak_val);
-+			CL_PRINTF(cli_buf);
-+		}
-+	}
-+
-+
-+	/*bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;*/
-+	bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
-+	btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
-+	phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
-+
-+	bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+		   "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
-+		   "CoexVer WL/  BT_Desired/ BT_Report",
-+		   glcoex_ver_date_8703b_1ant, glcoex_ver_8703b_1ant,
-+		   glcoex_ver_btdesired_8703b_1ant,
-+		   bt_coex_ver,
-+		   (bt_coex_ver == 0xff ? "Unknown" :
-+		   (bt_coex_ver >= glcoex_ver_btdesired_8703b_1ant ?
-+		      "Match":"Mis-Match")));
-+	CL_PRINTF(cli_buf);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+		   "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
-+		   "W_FW/ B_FW/ Phy/ Kt",
-+		   fw_ver, bt_patch_ver, phyver,
-+		   coex_sta->cut_version + 65);
-+	CL_PRINTF(cli_buf);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
-+		   "Wifi channel informed to BT",
-+		   coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
-+		   coex_dm->wifi_chnl_info[2]);
-+	CL_PRINTF(cli_buf);
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s",
-+		   "WifibHiPri/ Ccklock/ CckEverLock",
-+		   (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
-+		   (coex_sta->cck_lock ? "Yes" : "No"),
-+		   (coex_sta->cck_lock_ever ? "Yes" : "No"));
-+	CL_PRINTF(cli_buf);
-+
-+	/* wifi status */
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
-+		   "============[Wifi Status]============");
-+	CL_PRINTF(cli_buf);
-+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
-+		   "============[BT Status]============");
-+	CL_PRINTF(cli_buf);
-+
-+	pop_report_in_10s++;
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %ddBm/ %d/ %d",
-+		   "BT status/ rssi/ retryCnt/ popCnt",
-+		   ((coex_sta->bt_disabled) ? ("disabled") :	((
-+			   coex_sta->c2h_bt_inquiry_page) ? ("inquiry-page")
-+			   : ((BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
-+			       coex_dm->bt_status) ? "non-connected-idle" :
-+		((BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
-+				       ? "connected-idle" : "busy")))),
-+		   coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
-+		   coex_sta->pop_event_cnt);
-+	CL_PRINTF(cli_buf);
-+
-+	if (pop_report_in_10s >= 5) {
-+		coex_sta->pop_event_cnt = 0;
-+		pop_report_in_10s = 0;
-+	}
-+
-+	if (coex_sta->num_of_profile != 0)
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+				"\r\n %-35s = %s%s%s%s%s",
-+				"Profiles",
-+				((bt_link_info->a2dp_exist) ?
-+				((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," :
-+				"A2DP,") : ""),
-+				((bt_link_info->sco_exist) ?  "HFP," : ""),
-+				((bt_link_info->hid_exist) ?
-+				((coex_sta->is_hid_rcu) ? "HID(RCU)" :
-+				((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," :
-+				"HID(2/18),")) : ""),
-+				((bt_link_info->pan_exist) ?
-+				((coex_sta->is_bt_opp_exist) ? "OPP," : "PAN,") : ""),
-+				((coex_sta->voice_over_HOGP) ? "Voice" : ""));
-+	else
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+			   "\r\n %-35s = None", "Profiles");
-+
-+	CL_PRINTF(cli_buf);
-+
-+	if (bt_link_info->a2dp_exist) {
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s",
-+			   "A2DP Rate/Bitpool/Auto_Slot",
-+			   ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"),
-+			   coex_sta->a2dp_bit_pool,
-+			   ((coex_sta->is_autoslot) ? "On" : "Off")
-+			  );
-+		CL_PRINTF(cli_buf);
-+
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %d/ %d",
-+			   "V_ID/D_name/FBSlot_Legacy/FBSlot_Le",
-+			   coex_sta->bt_a2dp_vendor_id,
-+			   coex_sta->bt_a2dp_device_name,
-+			   coex_sta->legacy_forbidden_slot,
-+			   coex_sta->le_forbidden_slot
-+			  );
-+		CL_PRINTF(cli_buf);
-+	}
-+
-+	if (bt_link_info->hid_exist) {
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
-+			   "HID PairNum",
-+			   coex_sta->hid_pair_cnt
-+			  );
-+		CL_PRINTF(cli_buf);
-+	}
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x",
-+				"Role/RoleSwCnt/IgnWlact/Feature",
-+				((bt_link_info->slave_role) ? "Slave" : "Master"),
-+				coex_sta->cnt_RoleSwitch,
-+				((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"),
-+				coex_sta->bt_coex_supported_feature);
-+	CL_PRINTF(cli_buf);
-+
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
-+		   "ReInit/ReLink/IgnWlact/Page/NameReq",
-+		   coex_sta->cnt_ReInit,
-+		   coex_sta->cnt_setupLink,
-+		   coex_sta->cnt_IgnWlanAct,
-+		   coex_sta->cnt_Page,
-+		   coex_sta->cnt_RemoteNameReq
-+		  );
-+	CL_PRINTF(cli_buf);
-+
-+	halbtc8703b1ant_read_score_board(btcoexist, &u16tmp[0]);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%04x",
-+		   "ScoreBoard(B->W)", u16tmp[0]);
-+	CL_PRINTF(cli_buf);
-+
-+	if (coex_sta->num_of_profile > 0) {
-+
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+			"\r\n %-35s = %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x",
-+			"AFH MAP",
-+			coex_sta->bt_afh_map[0],
-+			coex_sta->bt_afh_map[1],
-+			coex_sta->bt_afh_map[2],
-+			coex_sta->bt_afh_map[3],
-+			coex_sta->bt_afh_map[4],
-+			coex_sta->bt_afh_map[5],
-+			coex_sta->bt_afh_map[6],
-+			coex_sta->bt_afh_map[7],
-+			coex_sta->bt_afh_map[8],
-+			coex_sta->bt_afh_map[9]
-+			   );
-+		CL_PRINTF(cli_buf);
-+	}
-+
-+	for (i = 0; i < BT_INFO_SRC_8703B_1ANT_MAX; i++) {
-+		if (coex_sta->bt_info_c2h_cnt[i]) {
-+			CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+				"\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)",
-+				   glbt_info_src_8703b_1ant[i],
-+				   coex_sta->bt_info_c2h[i][0],
-+				   coex_sta->bt_info_c2h[i][1],
-+				   coex_sta->bt_info_c2h[i][2],
-+				   coex_sta->bt_info_c2h[i][3],
-+				   coex_sta->bt_info_c2h[i][4],
-+				   coex_sta->bt_info_c2h[i][5],
-+				   coex_sta->bt_info_c2h[i][6],
-+				   coex_sta->bt_info_c2h_cnt[i]);
-+			CL_PRINTF(cli_buf);
-+		}
-+	}
-+
-+	if (btcoexist->manual_control)
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
-+			"============[mechanisms] (before Manual)============");
-+	else
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
-+			   "============[mechanisms]============");
-+	CL_PRINTF(cli_buf);
-+
-+	ps_tdma_case = coex_dm->cur_ps_tdma;
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+		   "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s)",
-+		   "PS TDMA",
-+		   coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
-+		   coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
-+		   coex_dm->ps_tdma_para[4], ps_tdma_case,
-+		   (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"));
-+
-+	CL_PRINTF(cli_buf);
-+
-+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
-+	u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
-+	u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+		   "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x",
-+		   "Table/0x6c0/0x6c4/0x6c8",
-+		   coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]);
-+	CL_PRINTF(cli_buf);
-+
-+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
-+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x",
-+		   "0x778/0x6cc/Scoreboard(W->B)",
-+		   u8tmp[0], u32tmp[0], coex_sta->score_board_WB);
-+	CL_PRINTF(cli_buf);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
-+		   "BtCtrlLPS/LPRA",
-+		   ((coex_sta->force_lps_ctrl) ? "On" : "Off"),
-+		   ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"));
-+	CL_PRINTF(cli_buf);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
-+		   "BT_Empty/BT_Late",
-+		   coex_sta->wl_fw_dbg_info[4],
-+		   coex_sta->wl_fw_dbg_info[5]);
-+	CL_PRINTF(cli_buf);
-+
-+	u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
-+	lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ?  TRUE : FALSE;
-+
-+	if (lte_coex_on) {
-+		u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
-+				0xa0);
-+		u32tmp[1] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
-+				0xa4);
-+
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
-+			   "LTE Coex Table W_L/B_L",
-+			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
-+		CL_PRINTF(cli_buf);
-+
-+		u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
-+				0xa8);
-+		u32tmp[1] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
-+				0xac);
-+		u32tmp[2] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
-+				0xb0);
-+		u32tmp[3] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
-+				0xb4);
-+
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+			   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
-+			   "LTE Break Table W_L/B_L/L_W/L_B",
-+			   u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
-+			   u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
-+		CL_PRINTF(cli_buf);
-+	}
-+	/* Hw setting		 */
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
-+		   "============[Hw setting]============");
-+	CL_PRINTF(cli_buf);
-+
-+	u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
-+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s",
-+		   "LTE CoexOn/Path Ctrl Owner",
-+		   (int)((u32tmp[0] & BIT(7)) >> 7),
-+		   ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
-+	CL_PRINTF(cli_buf);
-+
-+	if (lte_coex_on) {
-+		CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
-+			   "LTE 3Wire/OPMode/UART/UARTMode",
-+			   (int)((u32tmp[0] & BIT(6)) >> 6),
-+			   (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
-+			   (int)((u32tmp[0] & BIT(3)) >> 3),
-+			   (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
-+		CL_PRINTF(cli_buf);
-+	}
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+			   "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s (gnt_err = %d)",
-+			   "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg",
-+			   ((u32tmp[0] & BIT(12)) ? "SW" : "HW"),
-+			   ((u32tmp[0] & BIT(8)) ?	"SW" : "HW"),
-+			   ((u32tmp[0] & BIT(14)) ? "SW" : "HW"),
-+			   ((u32tmp[0] & BIT(10)) ?  "SW" : "HW"),
-+			   ((u8tmp[0] & BIT(3)) ? "On" : "Off"),
-+			   coex_sta->gnt_error_cnt);
-+	CL_PRINTF(cli_buf);
-+
-+	u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
-+		   "GNT_WL/GNT_BT/LTE_Busy/UART_Busy",
-+		   (int)((u32tmp[0] & BIT(2)) >> 2),
-+		   (int)((u32tmp[0] & BIT(3)) >> 3),
-+		   (int)((u32tmp[0] & BIT(1)) >> 1), (int)(u32tmp[0] & BIT(0)));
-+	CL_PRINTF(cli_buf);
-+
-+
-+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
-+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
-+		   "0x4c6[4]/0x40[5] (WL/BT PTA)",
-+		   (int)((u8tmp[0] & BIT(4)) >> 4),
-+		   (int)((u8tmp[1] & BIT(5)) >> 5));
-+	CL_PRINTF(cli_buf);
-+
-+	u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
-+	u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
-+	u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s",
-+		   "0x550(bcn ctrl)/0x522/4-RxAGC",
-+		   u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off");
-+	CL_PRINTF(cli_buf);
-+
-+	fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_OFDM);
-+	fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_FA_CCK);
-+	cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_OFDM);
-+	cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, PHYDM_INFO_CCA_CCK);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
-+		   "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
-+		   "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
-+		   cca_cck, fa_cck, cca_ofdm, fa_ofdm);
-+	CL_PRINTF(cli_buf);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d (Rx_rate Data/RTS= %d/%d)",
-+		   "CRC_OK CCK/11g/11n/11ac",
-+		   coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
-+		   coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht,
-+		   coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate);
-+	CL_PRINTF(cli_buf);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
-+		   "CRC_Err CCK/11g/11n/11n-agg",
-+		   coex_sta->crc_err_cck, coex_sta->crc_err_11g,
-+		   coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
-+	CL_PRINTF(cli_buf);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d",
-+			   "WlHiPri/ Locking/ Locked/ Noisy",
-+			   (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
-+			   (coex_sta->cck_lock ? "Yes" : "No"),
-+			   (coex_sta->cck_lock_ever ? "Yes" : "No"),
-+			   coex_sta->wl_noisy_level);
-+	CL_PRINTF(cli_buf);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
-+		   "0x770(Hi-pri rx/tx)",
-+		   coex_sta->high_priority_rx, coex_sta->high_priority_tx,
-+		   (coex_sta->is_hiPri_rx_overhead ? "(scan overhead!!)" : ""));
-+	CL_PRINTF(cli_buf);
-+
-+	CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
-+		   "0x774(Lo-pri rx/tx)",
-+		   coex_sta->low_priority_rx, coex_sta->low_priority_tx,
-+		   (bt_link_info->slave_role ? "(Slave!!)" : (
-+		   coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : "")));
-+	CL_PRINTF(cli_buf);
-+
-+	btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
-+}
-+
-+
-+void ex_halbtc8703b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-+{
-+	if (btcoexist->manual_control ||	btcoexist->stop_coex_dm)
-+		return;
-+
-+	if (BTC_IPS_ENTER == type) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], IPS ENTER notify\n");
-+		BTC_TRACE(trace_buf);
-+		coex_sta->under_ips = TRUE;
-+		coex_sta->under_lps = FALSE;
-+
-+		/* Write WL "Active" in Score-board for LPS off */
-+		halbtc8703b1ant_post_state_to_bt(btcoexist,
-+				BT_8703B_1ANT_SCOREBOARD_ACTIVE |
-+				BT_8703B_1ANT_SCOREBOARD_ONOFF |
-+				BT_8703B_1ANT_SCOREBOARD_SCAN |
-+				BT_8703B_1ANT_SCOREBOARD_UNDERTEST,
-+				FALSE);
-+
-+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
-+					     FORCE_EXEC,
-+					     BT_8703B_1ANT_PHASE_WLAN_OFF);
-+
-+		halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-+		halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
-+	} else if (BTC_IPS_LEAVE == type) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], IPS LEAVE notify\n");
-+		BTC_TRACE(trace_buf);
-+#if 0
-+		halbtc8703b1ant_post_state_to_bt(btcoexist,
-+				 BT_8703B_1ANT_SCOREBOARD_ACTIVE, TRUE);
-+#endif
-+		halbtc8703b1ant_init_hw_config(btcoexist, FALSE, FALSE);
-+		halbtc8703b1ant_init_coex_dm(btcoexist);
-+		halbtc8703b1ant_query_bt_info(btcoexist);
-+
-+		coex_sta->under_ips = FALSE;
-+	}
-+}
-+
-+void ex_halbtc8703b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-+{
-+	static boolean  pre_force_lps_on = FALSE;
-+
-+	if (btcoexist->manual_control || btcoexist->stop_coex_dm)
-+		return;
-+
-+	if (BTC_LPS_ENABLE == type) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], LPS ENABLE notify\n");
-+		BTC_TRACE(trace_buf);
-+		coex_sta->under_lps = TRUE;
-+		coex_sta->under_ips = FALSE;
-+
-+		if (coex_sta->force_lps_ctrl == TRUE) { /* LPS No-32K */
-+			/* Write WL "Active" in Score-board for PS-TDMA */
-+			pre_force_lps_on = TRUE;
-+			halbtc8703b1ant_post_state_to_bt(btcoexist,
-+				 BT_8703B_1ANT_SCOREBOARD_ACTIVE, TRUE);
-+
-+		} else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */
-+			/* Write WL "Non-Active" in Score-board for Native-PS */
-+			pre_force_lps_on = FALSE;
-+			halbtc8703b1ant_post_state_to_bt(btcoexist,
-+				 BT_8703B_1ANT_SCOREBOARD_ACTIVE, FALSE);
-+
-+			halbtc8703b1ant_action_wifi_native_lps(btcoexist);
-+		}
-+	} else if (BTC_LPS_DISABLE == type) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], LPS DISABLE notify\n");
-+		BTC_TRACE(trace_buf);
-+		coex_sta->under_lps = FALSE;
-+
-+		/* Write WL "Active" in Score-board for LPS off */
-+		halbtc8703b1ant_post_state_to_bt(btcoexist,
-+				 BT_8703B_1ANT_SCOREBOARD_ACTIVE, TRUE);
-+
-+		if ((pre_force_lps_on == FALSE) && (!coex_sta->force_lps_ctrl))
-+			halbtc8703b1ant_query_bt_info(btcoexist);
-+	}
-+}
-+
-+void ex_halbtc8703b1ant_scan_notify(IN struct btc_coexist *btcoexist,
-+				    IN u8 type)
-+{
-+	boolean wifi_connected = FALSE;
-+
-+	if (btcoexist->manual_control ||
-+	    btcoexist->stop_coex_dm)
-+		return;
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
-+			   &wifi_connected);
-+
-+
-+	if (BTC_SCAN_START == type) {
-+
-+		coex_sta->wifi_is_high_pri_task = TRUE;
-+
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], SCAN START notify\n");
-+		BTC_TRACE(trace_buf);
-+
-+		halbtc8703b1ant_post_state_to_bt(btcoexist,
-+					BT_8703B_1ANT_SCOREBOARD_ACTIVE |
-+					BT_8703B_1ANT_SCOREBOARD_SCAN |
-+					BT_8703B_1ANT_SCOREBOARD_ONOFF,
-+					TRUE);
-+
-+		halbtc8703b1ant_query_bt_info(btcoexist);
-+
-+		/* Force antenna setup for no scan result issue */
-+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
-+					     FORCE_EXEC,
-+					     BT_8703B_1ANT_PHASE_2G_RUNTIME);
-+
-+		halbtc8703b1ant_run_coexist_mechanism(btcoexist);
-+
-+	} else {
-+
-+		coex_sta->wifi_is_high_pri_task = FALSE;
-+
-+		btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
-+				   &coex_sta->scan_ap_num);
-+
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], SCAN FINISH notify  (Scan-AP = %d)\n",
-+			    coex_sta->scan_ap_num);
-+		BTC_TRACE(trace_buf);
-+
-+		halbtc8703b1ant_run_coexist_mechanism(btcoexist);
-+	}
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		    "[BTCoex], SCAN START Notify() end\n");
-+	BTC_TRACE(trace_buf);
-+
-+}
-+
-+void ex_halbtc8703b1ant_connect_notify(IN struct btc_coexist *btcoexist,
-+				       IN u8 type)
-+{
-+	boolean	wifi_connected = FALSE;
-+
-+	if (btcoexist->manual_control ||
-+	    btcoexist->stop_coex_dm)
-+		return;
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
-+			   &wifi_connected);
-+
-+	if (BTC_ASSOCIATE_START == type) {
-+		coex_sta->wifi_is_high_pri_task = TRUE;
-+
-+		halbtc8703b1ant_post_state_to_bt(btcoexist,
-+					 BT_8703B_1ANT_SCOREBOARD_ACTIVE |
-+					 BT_8703B_1ANT_SCOREBOARD_SCAN |
-+					 BT_8703B_1ANT_SCOREBOARD_ONOFF,
-+					 TRUE);
-+
-+		/* Force antenna setup for no scan result issue */
-+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
-+						 FORCE_EXEC,
-+						 BT_8703B_1ANT_PHASE_2G_RUNTIME);
-+
-+		/* psd_scan->ant_det_is_ant_det_available = TRUE; */
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], CONNECT START notify\n");
-+		BTC_TRACE(trace_buf);
-+		coex_dm->arp_cnt = 0;
-+
-+		halbtc8703b1ant_run_coexist_mechanism(btcoexist);
-+	} else {
-+		coex_sta->wifi_is_high_pri_task = FALSE;
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], CONNECT FINISH notify\n");
-+		BTC_TRACE(trace_buf);
-+
-+		halbtc8703b1ant_run_coexist_mechanism(btcoexist);
-+	}
-+
-+}
-+
-+void ex_halbtc8703b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
-+		IN u8 type)
-+{
-+	boolean			wifi_under_b_mode = FALSE;
-+
-+	if (btcoexist->manual_control ||
-+	    btcoexist->stop_coex_dm)
-+		return;
-+
-+	if (BTC_MEDIA_CONNECT == type) {
-+
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], MEDIA connect notify\n");
-+		BTC_TRACE(trace_buf);
-+
-+		halbtc8703b1ant_post_state_to_bt(btcoexist,
-+					 BT_8703B_1ANT_SCOREBOARD_ACTIVE |
-+					 BT_8703B_1ANT_SCOREBOARD_ONOFF,
-+					 TRUE);
-+
-+		/* Force antenna setup for no scan result issue */
-+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
-+					     FORCE_EXEC,
-+					     BT_8703B_1ANT_PHASE_2G_RUNTIME);
-+
-+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
-+				   &wifi_under_b_mode);
-+
-+		/* Set CCK Tx/Rx high Pri except 11b mode */
-+		if (wifi_under_b_mode) {
-+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
-+						   0x00); /* CCK Tx */
-+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
-+						   0x00); /* CCK Rx */
-+		} else {
-+			/* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */
-+			/* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */
-+			btcoexist->btc_write_1byte(btcoexist, 0x6cd,
-+						   0x00); /* CCK Tx */
-+			btcoexist->btc_write_1byte(btcoexist, 0x6cf,
-+						   0x10); /* CCK Rx */
-+		}
-+
-+		coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
-+					    0x430);
-+		coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
-+					    0x434);
-+		coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
-+						      btcoexist, 0x42a);
-+		coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
-+				btcoexist, 0x456);
-+	} else {
-+
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], MEDIA disconnect notify\n");
-+		BTC_TRACE(trace_buf);
-+
-+		halbtc8703b1ant_post_state_to_bt(btcoexist,
-+				 BT_8703B_1ANT_SCOREBOARD_ACTIVE, FALSE);
-+
-+		btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
-+		btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
-+
-+		coex_sta->cck_lock_ever = FALSE;
-+	}
-+
-+	halbtc8703b1ant_update_wifi_channel_info(btcoexist, type);
-+
-+}
-+
-+void ex_halbtc8703b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
-+		IN u8 type)
-+{
-+	boolean	under_4way = FALSE;
-+
-+	if (btcoexist->manual_control ||
-+	    btcoexist->stop_coex_dm)
-+		return;
-+
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
-+			   &under_4way);
-+
-+	if (under_4way) {
-+
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], specific Packet ---- under_4way!!\n");
-+		BTC_TRACE(trace_buf);
-+
-+		coex_sta->wifi_is_high_pri_task = TRUE;
-+		coex_sta->specific_pkt_period_cnt = 2;
-+	} else if (BTC_PACKET_ARP == type) {
-+
-+		coex_dm->arp_cnt++;
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], specific Packet ARP notify -cnt = %d\n",
-+			    coex_dm->arp_cnt);
-+		BTC_TRACE(trace_buf);
-+
-+	} else {
-+
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n",
-+			    type);
-+		BTC_TRACE(trace_buf);
-+
-+		coex_sta->wifi_is_high_pri_task = TRUE;
-+		coex_sta->specific_pkt_period_cnt = 2;
-+	}
-+
-+	if (coex_sta->wifi_is_high_pri_task) {
-+		halbtc8703b1ant_post_state_to_bt(btcoexist,
-+					 BT_8703B_1ANT_SCOREBOARD_SCAN, TRUE);
-+		halbtc8703b1ant_run_coexist_mechanism(btcoexist);
-+	}
-+}
-+
-+void ex_halbtc8703b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
-+				       IN u8 *tmp_buf, IN u8 length)
-+{
-+	u8				i, rsp_source = 0;
-+	boolean				wifi_connected = FALSE;
-+	boolean	wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE,
-+		    wifi_busy = FALSE;
-+	static boolean is_scoreboard_scan = FALSE;
-+
-+
-+	rsp_source = tmp_buf[0] & 0xf;
-+	if (rsp_source >= BT_INFO_SRC_8703B_1ANT_MAX)
-+		rsp_source = BT_INFO_SRC_8703B_1ANT_WIFI_FW;
-+	coex_sta->bt_info_c2h_cnt[rsp_source]++;
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		    "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source,
-+		    length);
-+	BTC_TRACE(trace_buf);
-+
-+	for (i = 0; i < length; i++) {
-+		coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
-+
-+		if (i == length - 1) {
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
-+				    tmp_buf[i]);
-+			BTC_TRACE(trace_buf);
-+		} else {
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
-+				    tmp_buf[i]);
-+			BTC_TRACE(trace_buf);
-+		}
-+	}
-+
-+	coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1];
-+	coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4];
-+	coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5];
-+
-+	if (BT_INFO_SRC_8703B_1ANT_WIFI_FW != rsp_source) {
-+
-+		/* if 0xff, it means BT is under WHCK test */
-+		coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? TRUE :
-+					  FALSE);
-+
-+		coex_sta->bt_create_connection = ((
-+			coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? TRUE :
-+						  FALSE);
-+
-+		/* unit: %, value-100 to translate to unit: dBm */
-+		coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 +
-+				    10;
-+
-+		coex_sta->c2h_bt_remote_name_req = ((
-+			coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? TRUE :
-+						    FALSE);
-+
-+		coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] &
-+					 0x10) ? TRUE : FALSE);
-+
-+		coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] &
-+				       0x8) ? TRUE : FALSE);
-+
-+		coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ?
-+					     TRUE : FALSE);
-+
-+		coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info &
-+			  BT_INFO_8703B_1ANT_B_INQ_PAGE) ? TRUE : FALSE);
-+
-+		coex_sta->a2dp_bit_pool = (((
-+			coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ?
-+				   coex_sta->bt_info_c2h[rsp_source][6] : 0);
-+
-+		coex_sta->is_bt_a2dp_sink = (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ?
-+									TRUE : FALSE;
-+
-+		coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] &
-+					 0xf;
-+
-+		coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8;
-+
-+		coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7;
-+
-+		coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4;
-+
-+		coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6;
-+
-+		coex_sta->is_bt_opp_exist = (coex_sta->bt_info_ext2 & 0x1) ? TRUE : FALSE;
-+
-+		if (coex_sta->bt_retry_cnt >= 1)
-+			coex_sta->pop_event_cnt++;
-+
-+		if (coex_sta->c2h_bt_remote_name_req)
-+			coex_sta->cnt_RemoteNameReq++;
-+
-+		if (coex_sta->bt_info_ext & BIT(1))
-+			coex_sta->cnt_ReInit++;
-+
-+		if (coex_sta->bt_info_ext & BIT(2)) {
-+			coex_sta->cnt_setupLink++;
-+			coex_sta->is_setupLink = TRUE;
-+			coex_sta->bt_relink_downcount = 2;
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				    "[BTCoex], Re-Link start in BT info!!\n");
-+			BTC_TRACE(trace_buf);
-+		} else {
-+			coex_sta->is_setupLink = FALSE;
-+			coex_sta->bt_relink_downcount = 0;
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				    "[BTCoex], Re-Link stop in BT info!!\n");
-+			BTC_TRACE(trace_buf);
-+		}
-+
-+		if (coex_sta->bt_info_ext & BIT(3))
-+			coex_sta->cnt_IgnWlanAct++;
-+
-+		if (coex_sta->bt_info_ext & BIT(6))
-+			coex_sta->cnt_RoleSwitch++;
-+
-+		if (coex_sta->bt_info_ext & BIT(7))
-+			coex_sta->is_bt_multi_link = TRUE;
-+		else
-+			coex_sta->is_bt_multi_link = FALSE;
-+
-+		if (coex_sta->bt_info_ext & BIT(0))
-+			coex_sta->is_hid_rcu = TRUE;
-+		else
-+			coex_sta->is_hid_rcu = FALSE;
-+
-+		if (coex_sta->bt_info_ext & BIT(5))
-+			coex_sta->is_ble_scan_toggle = TRUE;
-+		else
-+			coex_sta->is_ble_scan_toggle = FALSE;
-+
-+		if (coex_sta->bt_create_connection) {
-+			coex_sta->cnt_Page++;
-+
-+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY,
-+					   &wifi_busy);
-+
-+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
-+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
-+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
-+
-+			if ((wifi_link) || (wifi_roam) || (wifi_scan) ||
-+			    (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) {
-+
-+				is_scoreboard_scan = TRUE;
-+				halbtc8703b1ant_post_state_to_bt(btcoexist,
-+					 BT_8703B_1ANT_SCOREBOARD_SCAN, TRUE);
-+
-+			} else
-+				halbtc8703b1ant_post_state_to_bt(btcoexist,
-+					 BT_8703B_1ANT_SCOREBOARD_SCAN, FALSE);
-+
-+		} else {
-+				if (is_scoreboard_scan) {
-+					halbtc8703b1ant_post_state_to_bt(btcoexist,
-+						 BT_8703B_1ANT_SCOREBOARD_SCAN, FALSE);
-+					is_scoreboard_scan = FALSE;
-+				}
-+		}
-+
-+		/* Here we need to resend some wifi info to BT */
-+		/* because bt is reset and loss of the info. */
-+
-+		if ((!btcoexist->manual_control) &&
-+		    (!btcoexist->stop_coex_dm)) {
-+
-+			btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
-+					   &wifi_connected);
-+
-+			/*  Re-Init */
-+			if ((coex_sta->bt_info_ext & BIT(1))) {
-+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+					"[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
-+				BTC_TRACE(trace_buf);
-+				if (wifi_connected)
-+					halbtc8703b1ant_update_wifi_channel_info(
-+						btcoexist, BTC_MEDIA_CONNECT);
-+				else
-+					halbtc8703b1ant_update_wifi_channel_info(
-+						btcoexist,
-+						BTC_MEDIA_DISCONNECT);
-+			}
-+
-+
-+			/*  If Ignore_WLanAct && not SetUp_Link */
-+			if ((coex_sta->bt_info_ext & BIT(3)) &&
-+			    (!(coex_sta->bt_info_ext & BIT(2)))) {
-+
-+				BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+					"[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
-+				BTC_TRACE(trace_buf);
-+				halbtc8703b1ant_ignore_wlan_act(btcoexist,
-+							FORCE_EXEC, FALSE);
-+			}
-+		}
-+
-+	}
-+
-+	halbtc8703b1ant_update_bt_link_info(btcoexist);
-+
-+	halbtc8703b1ant_run_coexist_mechanism(btcoexist);
-+}
-+
-+void ex_halbtc8703b1ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist,
-+				       IN u8 *tmp_buf, IN u8 length)
-+{
-+	u8 i = 0;
-+	static u8 tmp_buf_pre[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], WiFi Fw Dbg info = %d %d %d %d %d %d (len = %d)\n",
-+				tmp_buf[0], tmp_buf[1],
-+				tmp_buf[2], tmp_buf[3],
-+				tmp_buf[4], tmp_buf[5], length);
-+	BTC_TRACE(trace_buf);
-+
-+	if (tmp_buf[0] == 0x8) {
-+		for (i = 1; i <= 5; i++) {
-+			coex_sta->wl_fw_dbg_info[i] =
-+				(tmp_buf[i] >= tmp_buf_pre[i]) ?
-+				(tmp_buf[i] - tmp_buf_pre[i]) :
-+				(255 - tmp_buf_pre[i] + tmp_buf[i]);
-+
-+			tmp_buf_pre[i] = tmp_buf[i];
-+		}
-+	}
-+}
-+
-+
-+void ex_halbtc8703b1ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist,
-+		IN BOOLEAN is_data_frame, IN u8 btc_rate_id)
-+{
-+	BOOLEAN wifi_connected = FALSE;
-+
-+	btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
-+			   &wifi_connected);
-+
-+	if (is_data_frame) {
-+		coex_sta->wl_rx_rate = btc_rate_id;
-+
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], rx_rate_change_notify data rate id = %d, RTS_Rate = %d\n",
-+			coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate);
-+		BTC_TRACE(trace_buf);
-+	} else {
-+		coex_sta->wl_rts_rx_rate = btc_rate_id;
-+
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], rts_rate_change_notify RTS rate id = %d, RTS_Rate = %d\n",
-+			coex_sta->wl_rts_rx_rate, coex_sta->wl_rts_rx_rate);
-+		BTC_TRACE(trace_buf);
-+	}
-+
-+	if ((wifi_connected) &&
-+		((coex_dm->bt_status ==
-+		 BT_8703B_1ANT_BT_STATUS_ACL_BUSY) ||
-+		(coex_dm->bt_status ==
-+		 BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
-+		(coex_dm->bt_status ==
-+		 BT_8703B_1ANT_BT_STATUS_SCO_BUSY))) {
-+
-+		if ((coex_sta->wl_rx_rate == BTC_CCK_5_5) ||
-+			(coex_sta->wl_rx_rate == BTC_OFDM_6) ||
-+			(coex_sta->wl_rx_rate == BTC_MCS_0)) {
-+
-+			coex_sta->cck_lock_warn = TRUE;
-+
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], cck lock warning...\n");
-+			BTC_TRACE(trace_buf);
-+		} else if ((coex_sta->wl_rx_rate == BTC_CCK_1) ||
-+			(coex_sta->wl_rx_rate == BTC_CCK_2) ||
-+			(coex_sta->wl_rts_rx_rate == BTC_CCK_1) ||
-+			(coex_sta->wl_rts_rx_rate == BTC_CCK_2)) {
-+
-+			coex_sta->cck_lock = TRUE;
-+			coex_sta->cck_lock_ever = TRUE;
-+
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], cck locking...\n");
-+			BTC_TRACE(trace_buf);
-+		} else {
-+			coex_sta->cck_lock_warn = FALSE;
-+			coex_sta->cck_lock = FALSE;
-+
-+			BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+				"[BTCoex], cck unlock...\n");
-+			BTC_TRACE(trace_buf);
-+		}
-+	} else {
-+		if ((coex_dm->bt_status ==
-+			BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE) ||
-+			(coex_dm->bt_status ==
-+			BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE)) {
-+			coex_sta->cck_lock_warn = FALSE;
-+			coex_sta->cck_lock = FALSE;
-+		}
-+	}
-+
-+}
-+
-+
-+
-+void ex_halbtc8703b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
-+		IN u8 type)
-+{
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
-+	BTC_TRACE(trace_buf);
-+
-+	if (BTC_RF_ON == type) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], RF is turned ON!!\n");
-+		BTC_TRACE(trace_buf);
-+
-+		btcoexist->stop_coex_dm = FALSE;
-+		coex_sta->is_rf_state_off = FALSE;
-+#if 0
-+		halbtc8703b1ant_post_state_to_bt(btcoexist,
-+				 BT_8703B_1ANT_SCOREBOARD_ACTIVE, TRUE);
-+		halbtc8703b1ant_post_state_to_bt(btcoexist,
-+					 BT_8703B_1ANT_SCOREBOARD_ONOFF, TRUE);
-+#endif
-+		/*	halbtc8703b1ant_init_hw_config(btcoexist, FALSE, FALSE); */
-+	} else if (BTC_RF_OFF == type) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], RF is turned OFF!!\n");
-+		BTC_TRACE(trace_buf);
-+		halbtc8703b1ant_post_state_to_bt(btcoexist,
-+				BT_8703B_1ANT_SCOREBOARD_ACTIVE |
-+				BT_8703B_1ANT_SCOREBOARD_ONOFF |
-+				BT_8703B_1ANT_SCOREBOARD_SCAN |
-+				BT_8703B_1ANT_SCOREBOARD_UNDERTEST,
-+				FALSE);
-+
-+		halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
-+					     FORCE_EXEC,
-+					     BT_8703B_1ANT_PHASE_WLAN_OFF);
-+
-+		halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0);
-+
-+		btcoexist->stop_coex_dm = TRUE;
-+		coex_sta->is_rf_state_off = TRUE;
-+	}
-+}
-+
-+void ex_halbtc8703b1ant_halt_notify(IN struct btc_coexist *btcoexist)
-+{
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
-+	BTC_TRACE(trace_buf);
-+
-+	halbtc8703b1ant_post_state_to_bt(btcoexist,
-+				BT_8703B_1ANT_SCOREBOARD_ACTIVE |
-+				BT_8703B_1ANT_SCOREBOARD_ONOFF |
-+				BT_8703B_1ANT_SCOREBOARD_SCAN |
-+				BT_8703B_1ANT_SCOREBOARD_UNDERTEST,
-+				FALSE);
-+
-+	halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
-+				     BT_8703B_1ANT_PHASE_WLAN_OFF);
-+
-+	ex_halbtc8703b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
-+
-+	halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, FALSE);
-+
-+	halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0);
-+
-+	btcoexist->stop_coex_dm = TRUE;
-+}
-+
-+void ex_halbtc8703b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
-+				   IN u8 pnp_state)
-+{
-+	static u8 pre_pnp_state;
-+
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
-+	BTC_TRACE(trace_buf);
-+
-+	if ((BTC_WIFI_PNP_SLEEP == pnp_state) ||
-+	    (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], Pnp notify to SLEEP\n");
-+		BTC_TRACE(trace_buf);
-+
-+		halbtc8703b1ant_post_state_to_bt(btcoexist,
-+				BT_8703B_1ANT_SCOREBOARD_ACTIVE |
-+				BT_8703B_1ANT_SCOREBOARD_ONOFF |
-+				BT_8703B_1ANT_SCOREBOARD_SCAN |
-+				BT_8703B_1ANT_SCOREBOARD_UNDERTEST,
-+				FALSE);
-+
-+		if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) {
-+
-+			halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
-+						     FORCE_EXEC,
-+					     BT_8703B_1ANT_PHASE_2G_RUNTIME);
-+		} else {
-+
-+			halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
-+						     FORCE_EXEC,
-+					     BT_8703B_1ANT_PHASE_WLAN_OFF);
-+		}
-+
-+		btcoexist->stop_coex_dm = TRUE;
-+	} else {
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			    "[BTCoex], Pnp notify to WAKE UP\n");
-+		BTC_TRACE(trace_buf);
-+
-+		if (pre_pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT ||
-+		    pnp_state == BTC_WIFI_PNP_WOWLAN) {
-+			coex_sta->run_time_state = TRUE;
-+			btcoexist->stop_coex_dm = FALSE;
-+			halbtc8703b1ant_run_coexist_mechanism(btcoexist);
-+		}
-+	}
-+	pre_pnp_state = pnp_state;
-+}
-+
-+void ex_halbtc8703b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
-+{
-+	BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+		"[BTCoex], *****************Coex DM Reset*****************\n");
-+	BTC_TRACE(trace_buf);
-+
-+	halbtc8703b1ant_init_hw_config(btcoexist, FALSE, FALSE);
-+	halbtc8703b1ant_init_coex_dm(btcoexist);
-+}
-+
-+void ex_halbtc8703b1ant_periodical(IN struct btc_coexist *btcoexist)
-+{
-+	u32	bt_patch_ver;
-+	boolean wifi_busy = FALSE;
-+	boolean bt_relink_finish = FALSE;
-+
-+#if (BT_AUTO_REPORT_ONLY_8703B_1ANT == 0)
-+	halbtc8703b1ant_query_bt_info(btcoexist);
-+#endif
-+
-+	halbtc8703b1ant_monitor_bt_ctr(btcoexist);
-+	halbtc8703b1ant_monitor_wifi_ctr(btcoexist);
-+
-+	halbtc8703b1ant_monitor_bt_enable_disable(btcoexist);
-+
-+#if 0
-+		btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-+
-+		/* halbtc8703b1ant_read_score_board(btcoexist, &bt_scoreboard_val); */
-+
-+		if (wifi_busy) {
-+			halbtc8703b1ant_post_state_to_bt(btcoexist,
-+					BT_8703B_1ANT_SCOREBOARD_UNDERTEST, TRUE);
-+			/*
-+			halbtc8703b1ant_post_state_to_bt(btcoexist,
-+						 BT_8703B_1ANT_SCOREBOARD_WLBUSY, TRUE);
-+
-+			if (bt_scoreboard_val & BIT(6))
-+				halbtc8703b1ant_query_bt_info(btcoexist); */
-+		} else {
-+			halbtc8703b1ant_post_state_to_bt(btcoexist,
-+						BT_8703B_1ANT_SCOREBOARD_UNDERTEST, FALSE);
-+			/*
-+			halbtc8703b1ant_post_state_to_bt(btcoexist,
-+						BT_8703B_1ANT_SCOREBOARD_WLBUSY,
-+						FALSE);  */
-+		}
-+#endif
-+
-+	if (coex_sta->bt_relink_downcount != 0) {
-+		coex_sta->bt_relink_downcount--;
-+
-+		if (coex_sta->bt_relink_downcount == 0) {
-+			coex_sta->is_setupLink = FALSE;
-+			bt_relink_finish = TRUE;
-+		}
-+	}
-+
-+	/* for 4-way, DHCP, EAPOL packet */
-+	if (coex_sta->specific_pkt_period_cnt > 0) {
-+
-+		coex_sta->specific_pkt_period_cnt--;
-+
-+		if ((coex_sta->specific_pkt_period_cnt == 0) &&
-+		    (coex_sta->wifi_is_high_pri_task))
-+			coex_sta->wifi_is_high_pri_task = FALSE;
-+
-+		BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-+			"[BTCoex], ***************** Hi-Pri Task = %s*****************\n",
-+			    (coex_sta->wifi_is_high_pri_task ? "Yes" :
-+			     "No"));
-+		BTC_TRACE(trace_buf);
-+
-+	}
-+
-+	if (halbtc8703b1ant_is_wifibt_status_changed(btcoexist) || (bt_relink_finish))
-+		halbtc8703b1ant_run_coexist_mechanism(btcoexist);
-+}
-+
-+void ex_halbtc8703b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
-+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-+{
-+	/* No Antenna Detection required because 8730b is only 1-Ant */
-+}
-+
-+void ex_halbtc8703b1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
-+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-+{
-+
-+
-+}
-+
-+void ex_halbtc8703b1ant_psd_scan(IN struct btc_coexist *btcoexist,
-+		 IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-+{
-+
-+
-+}
-+
-+void ex_halbtc8703b1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
-+{
-+
-+}
-+
-+#endif
-+
-+#endif	/* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
-+
-diff --git a/drivers/staging/rtl8723cs/hal/btc/halbtc8703b1ant.h b/drivers/staging/rtl8723cs/hal/btc/halbtc8703b1ant.h
-new file mode 100644
-index 000000000000..fc441ca31c60
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/btc/halbtc8703b1ant.h
-@@ -0,0 +1,445 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-+
-+#if (RTL8703B_SUPPORT == 1)
-+/* *******************************************
-+ * The following is for 8703B 1ANT BT Co-exist definition
-+ * ******************************************* */
-+#define	BT_AUTO_REPORT_ONLY_8703B_1ANT				1
-+#define BT_8703B_1ANT_ENABLE_GNTBT_TO_GPIO14		0
-+
-+#define	BT_INFO_8703B_1ANT_B_FTP						BIT(7)
-+#define	BT_INFO_8703B_1ANT_B_A2DP					BIT(6)
-+#define	BT_INFO_8703B_1ANT_B_HID						BIT(5)
-+#define	BT_INFO_8703B_1ANT_B_SCO_BUSY				BIT(4)
-+#define	BT_INFO_8703B_1ANT_B_ACL_BUSY				BIT(3)
-+#define	BT_INFO_8703B_1ANT_B_INQ_PAGE				BIT(2)
-+#define	BT_INFO_8703B_1ANT_B_SCO_ESCO				BIT(1)
-+#define	BT_INFO_8703B_1ANT_B_CONNECTION				BIT(0)
-+
-+#define	BT_INFO_8703B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_)	\
-+	(((_BT_INFO_EXT_&BIT(0))) ? TRUE : FALSE)
-+
-+#define	BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT		2
-+
-+#define  BT_8703B_1ANT_WIFI_NOISY_THRESH							50   /* max: 255 */
-+
-+/* for Antenna detection */
-+#define	BT_8703B_1ANT_ANTDET_PSDTHRES_BACKGROUND					50
-+#define	BT_8703B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION				70
-+#define	BT_8703B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION			55
-+#define	BT_8703B_1ANT_ANTDET_PSDTHRES_1ANT							35
-+#define	BT_8703B_1ANT_ANTDET_RETRY_INTERVAL							10	/* retry timer if ant det is fail, unit: second */
-+#define	BT_8703B_1ANT_ANTDET_SWEEPPOINT_DELAY							40000
-+#define	BT_8703B_1ANT_ANTDET_ENABLE									0
-+#define	BT_8703B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE				0
-+
-+#define	BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT		30000
-+
-+enum bt_8703b_1ant_signal_state {
-+	BT_8703B_1ANT_SIG_STA_SET_TO_LOW		= 0x0,
-+	BT_8703B_1ANT_SIG_STA_SET_BY_HW		= 0x0,
-+	BT_8703B_1ANT_SIG_STA_SET_TO_HIGH		= 0x1,
-+	BT_8703B_1ANT_SIG_STA_MAX
-+};
-+
-+enum bt_8703b_1ant_path_ctrl_owner {
-+	BT_8703B_1ANT_PCO_BTSIDE		= 0x0,
-+	BT_8703B_1ANT_PCO_WLSIDE	= 0x1,
-+	BT_8703B_1ANT_PCO_MAX
-+};
-+
-+enum bt_8703b_1ant_gnt_ctrl_type {
-+	BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA		= 0x0,
-+	BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW		= 0x1,
-+	BT_8703B_1ANT_GNT_TYPE_MAX
-+};
-+
-+enum bt_8703b_1ant_gnt_ctrl_block {
-+	BT_8703B_1ANT_GNT_BLOCK_RFC_BB		= 0x0,
-+	BT_8703B_1ANT_GNT_BLOCK_RFC			= 0x1,
-+	BT_8703B_1ANT_GNT_BLOCK_BB			= 0x2,
-+	BT_8703B_1ANT_GNT_BLOCK_MAX
-+};
-+
-+enum bt_8703b_1ant_lte_coex_table_type {
-+	BT_8703B_1ANT_CTT_WL_VS_LTE			= 0x0,
-+	BT_8703B_1ANT_CTT_BT_VS_LTE			= 0x1,
-+	BT_8703B_1ANT_CTT_MAX
-+};
-+
-+enum bt_8703b_1ant_lte_break_table_type {
-+	BT_8703B_1ANT_LBTT_WL_BREAK_LTE			= 0x0,
-+	BT_8703B_1ANT_LBTT_BT_BREAK_LTE				= 0x1,
-+	BT_8703B_1ANT_LBTT_LTE_BREAK_WL			= 0x2,
-+	BT_8703B_1ANT_LBTT_LTE_BREAK_BT				= 0x3,
-+	BT_8703B_1ANT_LBTT_MAX
-+};
-+
-+enum bt_info_src_8703b_1ant {
-+	BT_INFO_SRC_8703B_1ANT_WIFI_FW			= 0x0,
-+	BT_INFO_SRC_8703B_1ANT_BT_RSP				= 0x1,
-+	BT_INFO_SRC_8703B_1ANT_BT_ACTIVE_SEND		= 0x2,
-+	BT_INFO_SRC_8703B_1ANT_MAX
-+};
-+
-+enum bt_8703b_1ant_bt_status {
-+	BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE	= 0x0,
-+	BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE		= 0x1,
-+	BT_8703B_1ANT_BT_STATUS_INQ_PAGE				= 0x2,
-+	BT_8703B_1ANT_BT_STATUS_ACL_BUSY				= 0x3,
-+	BT_8703B_1ANT_BT_STATUS_SCO_BUSY				= 0x4,
-+	BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY			= 0x5,
-+	BT_8703B_1ANT_BT_STATUS_MAX
-+};
-+
-+enum bt_8703b_1ant_wifi_status {
-+	BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE				= 0x0,
-+	BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN		= 0x1,
-+	BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SCAN					= 0x2,
-+	BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT				= 0x3,
-+	BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE					= 0x4,
-+	BT_8703B_1ANT_WIFI_STATUS_CONNECTED_BUSY					= 0x5,
-+	BT_8703B_1ANT_WIFI_STATUS_MAX
-+};
-+
-+enum bt_8703b_1ant_coex_algo {
-+	BT_8703B_1ANT_COEX_ALGO_UNDEFINED			= 0x0,
-+	BT_8703B_1ANT_COEX_ALGO_SCO				= 0x1,
-+	BT_8703B_1ANT_COEX_ALGO_HID				= 0x2,
-+	BT_8703B_1ANT_COEX_ALGO_A2DP				= 0x3,
-+	BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS		= 0x4,
-+	BT_8703B_1ANT_COEX_ALGO_PANEDR			= 0x5,
-+	BT_8703B_1ANT_COEX_ALGO_PANHS			= 0x6,
-+	BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP		= 0x7,
-+	BT_8703B_1ANT_COEX_ALGO_PANEDR_HID		= 0x8,
-+	BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR	= 0x9,
-+	BT_8703B_1ANT_COEX_ALGO_HID_A2DP			= 0xa,
-+	BT_8703B_1ANT_COEX_ALGO_MAX				= 0xb,
-+};
-+
-+enum bt_8703b_1ant_phase {
-+	BT_8703B_1ANT_PHASE_COEX_INIT								= 0x0,
-+	BT_8703B_1ANT_PHASE_WLANONLY_INIT							= 0x1,
-+	BT_8703B_1ANT_PHASE_WLAN_OFF								= 0x2,
-+	BT_8703B_1ANT_PHASE_2G_RUNTIME								= 0x3,
-+	BT_8703B_1ANT_PHASE_5G_RUNTIME								= 0x4,
-+	BT_8703B_1ANT_PHASE_BTMPMODE								= 0x5,
-+	BT_8703B_1ANT_PHASE_ANTENNA_DET								= 0x6,
-+	BT_8703B_1ANT_PHASE_MAX
-+};
-+
-+enum bt_8703b_1ant_Scoreboard {
-+	BT_8703B_1ANT_SCOREBOARD_ACTIVE								= BIT(0),
-+	BT_8703B_1ANT_SCOREBOARD_ONOFF								= BIT(1),
-+	BT_8703B_1ANT_SCOREBOARD_SCAN								= BIT(2),
-+	BT_8703B_1ANT_SCOREBOARD_UNDERTEST							= BIT(3),
-+	BT_8703B_1ANT_SCOREBOARD_WLBUSY								= BIT(6)
-+};
-+
-+
-+struct coex_dm_8703b_1ant {
-+	/* hw setting */
-+	u8		pre_ant_pos_type;
-+	u8		cur_ant_pos_type;
-+	/* fw mechanism */
-+	boolean		cur_ignore_wlan_act;
-+	boolean		pre_ignore_wlan_act;
-+	u8		pre_ps_tdma;
-+	u8		cur_ps_tdma;
-+	u8		ps_tdma_para[5];
-+	u8		ps_tdma_du_adj_type;
-+	boolean		auto_tdma_adjust;
-+	boolean		pre_ps_tdma_on;
-+	boolean		cur_ps_tdma_on;
-+	boolean		pre_bt_auto_report;
-+	boolean		cur_bt_auto_report;
-+	u8		pre_lps;
-+	u8		cur_lps;
-+	u8		pre_rpwm;
-+	u8		cur_rpwm;
-+
-+	/* sw mechanism */
-+	boolean	pre_low_penalty_ra;
-+	boolean		cur_low_penalty_ra;
-+	u32		pre_val0x6c0;
-+	u32		cur_val0x6c0;
-+	u32		pre_val0x6c4;
-+	u32		cur_val0x6c4;
-+	u32		pre_val0x6c8;
-+	u32		cur_val0x6c8;
-+	u8		pre_val0x6cc;
-+	u8		cur_val0x6cc;
-+	boolean		limited_dig;
-+
-+	u32		backup_arfr_cnt1;	/* Auto Rate Fallback Retry cnt */
-+	u32		backup_arfr_cnt2;	/* Auto Rate Fallback Retry cnt */
-+	u16		backup_retry_limit;
-+	u8		backup_ampdu_max_time;
-+
-+	/* algorithm related */
-+	u8		pre_algorithm;
-+	u8		cur_algorithm;
-+	u8		bt_status;
-+	u8		wifi_chnl_info[3];
-+
-+	u32		pre_ra_mask;
-+	u32		cur_ra_mask;
-+	u8		pre_arfr_type;
-+	u8		cur_arfr_type;
-+	u8		pre_retry_limit_type;
-+	u8		cur_retry_limit_type;
-+	u8		pre_ampdu_time_type;
-+	u8		cur_ampdu_time_type;
-+	u32		arp_cnt;
-+
-+	u8		error_condition;
-+};
-+
-+struct coex_sta_8703b_1ant {
-+	boolean				bt_disabled;
-+	boolean				bt_link_exist;
-+	boolean				sco_exist;
-+	boolean				a2dp_exist;
-+	boolean				hid_exist;
-+	boolean				pan_exist;
-+	boolean				bt_hi_pri_link_exist;
-+	u8					num_of_profile;
-+
-+	boolean				under_lps;
-+	boolean				under_ips;
-+	u32					specific_pkt_period_cnt;
-+	u32					high_priority_tx;
-+	u32					high_priority_rx;
-+	u32					low_priority_tx;
-+	u32					low_priority_rx;
-+	boolean             is_hiPri_rx_overhead;
-+	s8					bt_rssi;
-+	boolean				bt_tx_rx_mask;
-+	u8					pre_bt_rssi_state;
-+	u8					pre_wifi_rssi_state[4];
-+	u8					bt_info_c2h[BT_INFO_SRC_8703B_1ANT_MAX][10];
-+	u32					bt_info_c2h_cnt[BT_INFO_SRC_8703B_1ANT_MAX];
-+	boolean			    bt_whck_test;
-+	boolean				c2h_bt_inquiry_page;
-+	boolean				c2h_bt_remote_name_req;
-+	boolean				c2h_bt_page;				/* Add for win8.1 page out issue */
-+	boolean				wifi_is_high_pri_task;		/* Add for win8.1 page out issue */
-+	u8					bt_retry_cnt;
-+	u8					bt_info_ext;
-+	u8					bt_info_ext2;
-+	u32					pop_event_cnt;
-+	u8					scan_ap_num;
-+
-+	u32					crc_ok_cck;
-+	u32					crc_ok_11g;
-+	u32					crc_ok_11n;
-+	u32					crc_ok_11n_vht;
-+
-+	u32					crc_err_cck;
-+	u32					crc_err_11g;
-+	u32					crc_err_11n;
-+	u32					crc_err_11n_vht;
-+
-+	boolean				cck_lock;
-+	boolean				cck_lock_ever;
-+	boolean				cck_lock_warn;
-+
-+	u8					coex_table_type;
-+	boolean				force_lps_ctrl;
-+
-+	boolean				concurrent_rx_mode_on;
-+
-+	u16					score_board;
-+	u8					isolation_btween_wb;   /* 0~ 50 */
-+
-+	u8					a2dp_bit_pool;
-+	u8					cut_version;
-+	boolean				acl_busy;
-+	boolean				bt_create_connection;
-+
-+	u32					bt_coex_supported_feature;
-+	u32					bt_coex_supported_version;
-+
-+	u8					bt_ble_scan_type;
-+	u32					bt_ble_scan_para[3];
-+
-+	boolean				run_time_state;
-+	boolean				freeze_coexrun_by_btinfo;
-+
-+	boolean				is_A2DP_3M;
-+	boolean				voice_over_HOGP;
-+	u8                  bt_info;
-+	boolean				is_autoslot;
-+	u8					forbidden_slot;
-+	u8					hid_busy_num;
-+	u8					hid_pair_cnt;
-+
-+	u32					cnt_RemoteNameReq;
-+	u32					cnt_setupLink;
-+	u32					cnt_ReInit;
-+	u32					cnt_IgnWlanAct;
-+	u32					cnt_Page;
-+	u32					cnt_RoleSwitch;
-+
-+	u16					bt_reg_vendor_ac;
-+	u16					bt_reg_vendor_ae;
-+
-+	boolean				is_setupLink;
-+	u8					wl_noisy_level;
-+	u32                 gnt_error_cnt;
-+
-+	u8					bt_afh_map[10];
-+	u8					bt_relink_downcount;
-+	boolean				is_tdma_btautoslot;
-+	boolean				is_tdma_btautoslot_hang;
-+
-+	boolean				is_rf_state_off;
-+
-+	boolean				is_hid_low_pri_tx_overhead;
-+	boolean				is_bt_multi_link;
-+	boolean				is_bt_a2dp_sink;
-+
-+	u8					wl_fw_dbg_info[10];
-+	u8					wl_rx_rate;
-+	u8					wl_rts_rx_rate;
-+
-+	u16					score_board_WB;
-+	boolean				is_hid_rcu;
-+	u16					legacy_forbidden_slot;
-+	u16					le_forbidden_slot;
-+	u8					bt_a2dp_vendor_id;
-+	u32					bt_a2dp_device_name;
-+	boolean				is_ble_scan_toggle;
-+
-+	boolean				is_bt_opp_exist;
-+};
-+
-+#define  BT_8703B_1ANT_ANTDET_PSD_POINTS			256	/* MAX:1024 */
-+#define  BT_8703B_1ANT_ANTDET_PSD_AVGNUM			1	/* MAX:3 */
-+#define	BT_8703B_1ANT_ANTDET_BUF_LEN				16
-+
-+struct psdscan_sta_8703b_1ant {
-+
-+	u32			ant_det_bt_le_channel;  /* BT LE Channel ex:2412 */
-+	u32			ant_det_bt_tx_time;
-+	u32			ant_det_pre_psdscan_peak_val;
-+	boolean			ant_det_is_ant_det_available;
-+	u32			ant_det_psd_scan_peak_val;
-+	boolean			ant_det_is_btreply_available;
-+	u32			ant_det_psd_scan_peak_freq;
-+
-+	u8			ant_det_result;
-+	u8			ant_det_peak_val[BT_8703B_1ANT_ANTDET_BUF_LEN];
-+	u8			ant_det_peak_freq[BT_8703B_1ANT_ANTDET_BUF_LEN];
-+	u32			ant_det_try_count;
-+	u32			ant_det_fail_count;
-+	u32			ant_det_inteval_count;
-+	u32			ant_det_thres_offset;
-+
-+	u32			real_cent_freq;
-+	s32			real_offset;
-+	u32			real_span;
-+
-+	u32			psd_band_width;  /* unit: Hz */
-+	u32			psd_point;		/* 128/256/512/1024 */
-+	u32			psd_report[1024];  /* unit:dB (20logx), 0~255 */
-+	u32			psd_report_max_hold[1024];  /* unit:dB (20logx), 0~255 */
-+	u32			psd_start_point;
-+	u32			psd_stop_point;
-+	u32			psd_max_value_point;
-+	u32			psd_max_value;
-+	u32			psd_start_base;
-+	u32			psd_avg_num;	/* 1/8/16/32 */
-+	u32			psd_gen_count;
-+	boolean			is_psd_running;
-+	boolean			is_psd_show_max_only;
-+};
-+
-+/* *******************************************
-+ * The following is interface which will notify coex module.
-+ * ******************************************* */
-+void ex_halbtc8703b1ant_power_on_setting(IN struct btc_coexist *btcoexist);
-+void ex_halbtc8703b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
-+void ex_halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
-+				       IN boolean wifi_only);
-+void ex_halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
-+void ex_halbtc8703b1ant_ips_notify(IN struct btc_coexist *btcoexist,
-+				   IN u8 type);
-+void ex_halbtc8703b1ant_lps_notify(IN struct btc_coexist *btcoexist,
-+				   IN u8 type);
-+void ex_halbtc8703b1ant_scan_notify(IN struct btc_coexist *btcoexist,
-+				    IN u8 type);
-+void ex_halbtc8703b1ant_connect_notify(IN struct btc_coexist *btcoexist,
-+				       IN u8 type);
-+void ex_halbtc8703b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
-+		IN u8 type);
-+void ex_halbtc8703b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
-+		IN u8 type);
-+void ex_halbtc8703b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
-+				       IN u8 *tmp_buf, IN u8 length);
-+void ex_halbtc8703b1ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist,
-+				       IN u8 *tmp_buf, IN u8 length);
-+void ex_halbtc8703b1ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist,
-+		IN BOOLEAN is_data_frame, IN u8 btc_rate_id);
-+void ex_halbtc8703b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
-+		IN u8 type);
-+void ex_halbtc8703b1ant_halt_notify(IN struct btc_coexist *btcoexist);
-+void ex_halbtc8703b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
-+				   IN u8 pnp_state);
-+void ex_halbtc8703b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
-+void ex_halbtc8703b1ant_periodical(IN struct btc_coexist *btcoexist);
-+void ex_halbtc8703b1ant_display_coex_info(IN struct btc_coexist *btcoexist);
-+void ex_halbtc8703b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
-+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
-+void ex_halbtc8703b1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
-+		IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
-+
-+void ex_halbtc8703b1ant_psd_scan(IN struct btc_coexist *btcoexist,
-+		 IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
-+void ex_halbtc8703b1ant_display_ant_detection(IN struct btc_coexist *btcoexist);
-+
-+#else
-+#define	ex_halbtc8703b1ant_power_on_setting(btcoexist)
-+#define	ex_halbtc8703b1ant_pre_load_firmware(btcoexist)
-+#define	ex_halbtc8703b1ant_init_hw_config(btcoexist, wifi_only)
-+#define	ex_halbtc8703b1ant_init_coex_dm(btcoexist)
-+#define	ex_halbtc8703b1ant_ips_notify(btcoexist, type)
-+#define	ex_halbtc8703b1ant_lps_notify(btcoexist, type)
-+#define	ex_halbtc8703b1ant_scan_notify(btcoexist, type)
-+#define	ex_halbtc8703b1ant_connect_notify(btcoexist, type)
-+#define	ex_halbtc8703b1ant_media_status_notify(btcoexist, type)
-+#define	ex_halbtc8703b1ant_specific_packet_notify(btcoexist, type)
-+#define	ex_halbtc8703b1ant_bt_info_notify(btcoexist, tmp_buf, length)
-+#define ex_halbtc8703b1ant_wl_fwdbginfo_notify(btcoexist, tmp_buf, length)
-+#define	ex_halbtc8703b1ant_rx_rate_change_notify(btcoexist, is_data_frame, btc_rate_id)
-+#define	ex_halbtc8703b1ant_rf_status_notify(btcoexist, type)
-+#define	ex_halbtc8703b1ant_halt_notify(btcoexist)
-+#define	ex_halbtc8703b1ant_pnp_notify(btcoexist, pnp_state)
-+#define	ex_halbtc8703b1ant_coex_dm_reset(btcoexist)
-+#define	ex_halbtc8703b1ant_periodical(btcoexist)
-+#define	ex_halbtc8703b1ant_display_coex_info(btcoexist)
-+#define	ex_halbtc8703b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
-+#define	ex_halbtc8703b1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds)
-+#define	ex_halbtc8703b1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds)
-+#define	ex_halbtc8703b1ant_display_ant_detection(btcoexist)
-+
-+#endif
-+
-+
-+#endif
-+
-diff --git a/drivers/staging/rtl8723cs/hal/btc/halbtcoutsrc.h b/drivers/staging/rtl8723cs/hal/btc/halbtcoutsrc.h
-new file mode 100644
-index 000000000000..28a3c25c2c2e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/btc/halbtcoutsrc.h
-@@ -0,0 +1,2164 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef	__HALBTC_OUT_SRC_H__
-+#define __HALBTC_OUT_SRC_H__
-+
-+enum {
-+	BTC_CCK_1,
-+	BTC_CCK_2,
-+	BTC_CCK_5_5,
-+	BTC_CCK_11,
-+	BTC_OFDM_6,
-+	BTC_OFDM_9,
-+	BTC_OFDM_12,
-+	BTC_OFDM_18,
-+	BTC_OFDM_24,
-+	BTC_OFDM_36,
-+	BTC_OFDM_48,
-+	BTC_OFDM_54,
-+	BTC_MCS_0,
-+	BTC_MCS_1,
-+	BTC_MCS_2,
-+	BTC_MCS_3,
-+	BTC_MCS_4,
-+	BTC_MCS_5,
-+	BTC_MCS_6,
-+	BTC_MCS_7,
-+	BTC_MCS_8,
-+	BTC_MCS_9,
-+	BTC_MCS_10,
-+	BTC_MCS_11,
-+	BTC_MCS_12,
-+	BTC_MCS_13,
-+	BTC_MCS_14,
-+	BTC_MCS_15,
-+	BTC_MCS_16,
-+	BTC_MCS_17,
-+	BTC_MCS_18,
-+	BTC_MCS_19,
-+	BTC_MCS_20,
-+	BTC_MCS_21,
-+	BTC_MCS_22,
-+	BTC_MCS_23,
-+	BTC_MCS_24,
-+	BTC_MCS_25,
-+	BTC_MCS_26,
-+	BTC_MCS_27,
-+	BTC_MCS_28,
-+	BTC_MCS_29,
-+	BTC_MCS_30,
-+	BTC_MCS_31,
-+	BTC_VHT_1SS_MCS_0,
-+	BTC_VHT_1SS_MCS_1,
-+	BTC_VHT_1SS_MCS_2,
-+	BTC_VHT_1SS_MCS_3,
-+	BTC_VHT_1SS_MCS_4,
-+	BTC_VHT_1SS_MCS_5,
-+	BTC_VHT_1SS_MCS_6,
-+	BTC_VHT_1SS_MCS_7,
-+	BTC_VHT_1SS_MCS_8,
-+	BTC_VHT_1SS_MCS_9,
-+	BTC_VHT_2SS_MCS_0,
-+	BTC_VHT_2SS_MCS_1,
-+	BTC_VHT_2SS_MCS_2,
-+	BTC_VHT_2SS_MCS_3,
-+	BTC_VHT_2SS_MCS_4,
-+	BTC_VHT_2SS_MCS_5,
-+	BTC_VHT_2SS_MCS_6,
-+	BTC_VHT_2SS_MCS_7,
-+	BTC_VHT_2SS_MCS_8,
-+	BTC_VHT_2SS_MCS_9,
-+	BTC_VHT_3SS_MCS_0,
-+	BTC_VHT_3SS_MCS_1,
-+	BTC_VHT_3SS_MCS_2,
-+	BTC_VHT_3SS_MCS_3,
-+	BTC_VHT_3SS_MCS_4,
-+	BTC_VHT_3SS_MCS_5,
-+	BTC_VHT_3SS_MCS_6,
-+	BTC_VHT_3SS_MCS_7,
-+	BTC_VHT_3SS_MCS_8,
-+	BTC_VHT_3SS_MCS_9,
-+	BTC_VHT_4SS_MCS_0,
-+	BTC_VHT_4SS_MCS_1,
-+	BTC_VHT_4SS_MCS_2,
-+	BTC_VHT_4SS_MCS_3,
-+	BTC_VHT_4SS_MCS_4,
-+	BTC_VHT_4SS_MCS_5,
-+	BTC_VHT_4SS_MCS_6,
-+	BTC_VHT_4SS_MCS_7,
-+	BTC_VHT_4SS_MCS_8,
-+	BTC_VHT_4SS_MCS_9,
-+	BTC_MCS_32,
-+	BTC_UNKNOWN,
-+	BTC_PKT_MGNT,
-+	BTC_PKT_CTRL,
-+	BTC_PKT_UNKNOWN,
-+	BTC_PKT_NOT_FOR_ME,
-+	BTC_RATE_MAX
-+};
-+
-+enum {
-+	BTC_MULTIPORT_SCC,
-+	BTC_MULTIPORT_MCC_DUAL_CHANNEL,
-+	BTC_MULTIPORT_MCC_DUAL_BAND,
-+	BTC_MULTIPORT_MAX
-+};
-+
-+#define		BTC_COEX_8822B_COMMON_CODE	0
-+#define		BTC_COEX_OFFLOAD			0
-+#define		BTC_TMP_BUF_SHORT		20
-+
-+extern u1Byte	gl_btc_trace_buf[];
-+#define		BTC_SPRINTF			rsprintf
-+#define		BTC_TRACE(_MSG_)\
-+do {\
-+	if (GLBtcDbgType[COMP_COEX] & BIT(DBG_LOUD)) {\
-+		RTW_INFO("%s", _MSG_);\
-+	} \
-+} while (0)
-+#define		BT_PrintData(adapter, _MSG_, len, data)	RTW_DBG_DUMP((_MSG_), data, len)
-+
-+
-+#define		NORMAL_EXEC					FALSE
-+#define		FORCE_EXEC						TRUE
-+
-+#define		NM_EXCU						FALSE
-+#define		FC_EXCU						TRUE
-+
-+#define		BTC_RF_OFF					0x0
-+#define		BTC_RF_ON					0x1
-+
-+#define		BTC_RF_A					0x0
-+#define		BTC_RF_B					0x1
-+#define		BTC_RF_C					0x2
-+#define		BTC_RF_D					0x3
-+
-+#define		BTC_SMSP				SINGLEMAC_SINGLEPHY
-+#define		BTC_DMDP				DUALMAC_DUALPHY
-+#define		BTC_DMSP				DUALMAC_SINGLEPHY
-+#define		BTC_MP_UNKNOWN		0xff
-+
-+#define		BT_COEX_ANT_TYPE_PG			0
-+#define		BT_COEX_ANT_TYPE_ANTDIV		1
-+#define		BT_COEX_ANT_TYPE_DETECTED	2
-+
-+#define		BTC_MIMO_PS_STATIC			0	/* 1ss */
-+#define		BTC_MIMO_PS_DYNAMIC			1	/* 2ss */
-+
-+#define		BTC_RATE_DISABLE			0
-+#define		BTC_RATE_ENABLE				1
-+
-+/* single Antenna definition */
-+#define		BTC_ANT_PATH_WIFI			0
-+#define		BTC_ANT_PATH_BT				1
-+#define		BTC_ANT_PATH_PTA			2
-+#define		BTC_ANT_PATH_WIFI5G			3
-+#define		BTC_ANT_PATH_AUTO			4
-+/* dual Antenna definition */
-+#define		BTC_ANT_WIFI_AT_MAIN		0
-+#define		BTC_ANT_WIFI_AT_AUX			1
-+#define		BTC_ANT_WIFI_AT_DIVERSITY	2
-+/* coupler Antenna definition */
-+#define		BTC_ANT_WIFI_AT_CPL_MAIN	0
-+#define		BTC_ANT_WIFI_AT_CPL_AUX		1
-+
-+/* for common code request */
-+#define REG_LTE_IDR_COEX_CTRL	0x0038
-+#define REG_SYS_SDIO_CTRL		0x0070
-+#define REG_SYS_SDIO_CTRL3		0x0073
-+/* #define REG_RETRY_LIMIT		0x042a */
-+/* #define REG_DARFRC			0x0430 */
-+#define REG_DARFRCH				0x0434
-+#define REG_CCK_CHECK			0x0454
-+#define REG_AMPDU_MAX_TIME_V1	0x0455
-+#define REG_TX_HANG_CTRL		0x045E
-+#define REG_LIFETIME_EN			0x0426
-+#define REG_BT_COEX_TABLE0		0x06C0
-+#define REG_BT_COEX_TABLE1		0x06C4
-+#define REG_BT_COEX_BRK_TABLE	0x06C8
-+#define REG_BT_COEX_TABLE_H		0x06CC
-+#define REG_BT_ACT_STATISTICS	0x0770
-+#define REG_BT_ACT_STATISTICS_1	0x0774
-+#define REG_BT_STAT_CTRL		0x0778
-+
-+#define BIT_EN_GNT_BT_AWAKE	BIT(3)
-+#define BIT_EN_BCN_FUNCTION	BIT(3)
-+#define BIT_EN_BCN_PKT_REL	BIT(6)
-+#define BIT_FEN_BB_GLB_RST	BIT(1)
-+#define BIT_FEN_BB_RSTB		BIT(0)
-+
-+#define TDMA_4SLOT			BIT(8)
-+
-+/* for 2T2R -> 2T1R coex MIMO-PS mechanism tranlation */
-+#define BTC_2GTDD_MAX_TRY		3	/* the max retry count for 1R->2R */
-+#define BTC_2GFDD_MAX_STAY	300	/* the max stay time at 1R if 2R try-able (unit: 2s) */
-+
-+typedef enum _BTC_POWERSAVE_TYPE {
-+	BTC_PS_WIFI_NATIVE			= 0,	/* wifi original power save behavior */
-+	BTC_PS_LPS_ON				= 1,
-+	BTC_PS_LPS_OFF				= 2,
-+	BTC_PS_MAX
-+} BTC_POWERSAVE_TYPE, *PBTC_POWERSAVE_TYPE;
-+
-+typedef enum _BTC_BT_REG_TYPE {
-+	BTC_BT_REG_RF						= 0,
-+	BTC_BT_REG_MODEM					= 1,
-+	BTC_BT_REG_BLUEWIZE					= 2,
-+	BTC_BT_REG_VENDOR					= 3,
-+	BTC_BT_REG_LE						= 4,
-+	BTC_BT_REG_MAX
-+} BTC_BT_REG_TYPE, *PBTC_BT_REG_TYPE;
-+
-+typedef enum _BTC_CHIP_INTERFACE {
-+	BTC_INTF_UNKNOWN	= 0,
-+	BTC_INTF_PCI			= 1,
-+	BTC_INTF_USB			= 2,
-+	BTC_INTF_SDIO		= 3,
-+	BTC_INTF_MAX
-+} BTC_CHIP_INTERFACE, *PBTC_CHIP_INTERFACE;
-+
-+typedef enum _BTC_CHIP_TYPE {
-+	BTC_CHIP_UNDEF		= 0,
-+	BTC_CHIP_CSR_BC4		= 1,
-+	BTC_CHIP_CSR_BC8		= 2,
-+	BTC_CHIP_RTL8723A		= 3,
-+	BTC_CHIP_RTL8821		= 4,
-+	BTC_CHIP_RTL8723B		= 5,
-+	BTC_CHIP_RTL8822B 		= 6,
-+	BTC_CHIP_RTL8822C 		= 7,
-+	BTC_CHIP_RTL8821C 		= 8,
-+	BTC_CHIP_RTL8821A 		= 9,
-+	BTC_CHIP_RTL8723D 		= 10,
-+	BTC_CHIP_RTL8703B 		= 11,
-+	BTC_CHIP_RTL8725A 		= 12,
-+	BTC_CHIP_RTL8723F 		= 13,
-+	BTC_CHIP_MAX
-+} BTC_CHIP_TYPE, *PBTC_CHIP_TYPE;
-+
-+/* following is for wifi link status */
-+#define		WIFI_STA_CONNECTED				BIT0
-+#define		WIFI_AP_CONNECTED				BIT1
-+#define		WIFI_HS_CONNECTED				BIT2
-+#define		WIFI_P2P_GO_CONNECTED			BIT3
-+#define		WIFI_P2P_GC_CONNECTED			BIT4
-+
-+/* following is for command line utility */
-+#define	CL_SPRINTF	rsprintf
-+#define	CL_PRINTF	DCMD_Printf
-+#define CL_STRNCAT(dst, dst_size, src, src_size) rstrncat(dst, src, src_size)
-+
-+static const char *const glbt_info_src[] = {
-+	"BT Info[wifi fw]",
-+	"BT Info[bt rsp]",
-+	"BT Info[bt auto report]",
-+};
-+
-+#define BTC_INFO_FTP		BIT(7)
-+#define BTC_INFO_A2DP		BIT(6)
-+#define BTC_INFO_HID		BIT(5)
-+#define BTC_INFO_SCO_BUSY		BIT(4)
-+#define BTC_INFO_ACL_BUSY		BIT(3)
-+#define BTC_INFO_INQ_PAGE		BIT(2)
-+#define BTC_INFO_SCO_ESCO		BIT(1)
-+#define BTC_INFO_CONNECTION	BIT(0)
-+
-+#define BTC_BTINFO_LENGTH_MAX 10
-+
-+enum btc_gnt_setup_state {
-+	BTC_GNT_SET_SW_LOW	= 0x0,
-+	BTC_GNT_SET_SW_HIGH	= 0x1,
-+	BTC_GNT_SET_HW_PTA	= 0x2,
-+	BTC_GNT_SET_MAX
-+};
-+
-+enum btc_gnt_setup_state_2 {
-+	BTC_GNT_HW_PTA		= 0x0,
-+	BTC_GNT_SW_LOW		= 0x1,
-+	BTC_GNT_SW_HIGH		= 0x3,
-+	BTC_GNT_MAX
-+};
-+
-+enum btc_path_ctrl_owner {
-+	BTC_OWNER_BT		= 0x0,
-+	BTC_OWNER_WL		= 0x1,
-+	BTC_OWNER_MAX
-+};
-+
-+enum btc_gnt_ctrl_type {
-+	BTC_GNT_CTRL_BY_PTA	= 0x0,
-+	BTC_GNT_CTRL_BY_SW	= 0x1,
-+	BTC_GNT_CTRL_MAX
-+};
-+
-+enum btc_gnt_ctrl_block {
-+	BTC_GNT_BLOCK_RFC_BB	= 0x0,
-+	BTC_GNT_BLOCK_RFC	= 0x1,
-+	BTC_GNT_BLOCK_BB	= 0x2,
-+	BTC_GNT_BLOCK_MAX
-+};
-+
-+enum btc_lte_coex_table_type {
-+	BTC_CTT_WL_VS_LTE	= 0x0,
-+	BTC_CTT_BT_VS_LTE	= 0x1,
-+	BTC_CTT_MAX
-+};
-+
-+enum btc_lte_break_table_type {
-+	BTC_LBTT_WL_BREAK_LTE	= 0x0,
-+	BTC_LBTT_BT_BREAK_LTE	= 0x1,
-+	BTC_LBTT_LTE_BREAK_WL	= 0x2,
-+	BTC_LBTT_LTE_BREAK_BT	= 0x3,
-+	BTC_LBTT_MAX
-+};
-+
-+enum btc_btinfo_src {
-+	BTC_BTINFO_SRC_WL_FW	= 0x0,
-+	BTC_BTINFO_SRC_BT_RSP	= 0x1,
-+	BTC_BTINFO_SRC_BT_ACT	= 0x2,
-+	BTC_BTINFO_SRC_BT_IQK	= 0x3,
-+	BTC_BTINFO_SRC_BT_SCBD	= 0x4,
-+	BTC_BTINFO_SRC_H2C60	= 0x5,
-+	BTC_BTINFO_SRC_MAX
-+};
-+
-+enum btc_bt_profile {
-+	BTC_BTPROFILE_NONE		= 0,
-+	BTC_BTPROFILE_HFP		= BIT(0),
-+	BTC_BTPROFILE_HID		= BIT(1),
-+	BTC_BTPROFILE_A2DP		= BIT(2),
-+	BTC_BTPROFILE_PAN		= BIT(3),
-+	BTC_BTPROFILE_MAX		= 0xf
-+};
-+
-+static const char *const bt_profile_string[] = {
-+	"None",
-+	"HFP",
-+	"HID",
-+	"HID + HFP",
-+	"A2DP",
-+	"A2DP + HFP",
-+	"A2DP + HID",
-+	"PAN + HID + HFP",
-+	"PAN",
-+	"PAN + HFP",
-+	"PAN + HID",
-+	"PAN + HID + HFP",
-+	"PAN + A2DP",
-+	"PAN + A2DP + HFP",
-+	"PAN + A2DP + HID",
-+	"PAN + A2DP + HID + HFP"
-+};
-+
-+enum btc_bt_status {
-+	BTC_BTSTATUS_NCON_IDLE		= 0x0,
-+	BTC_BTSTATUS_CON_IDLE		= 0x1,
-+	BTC_BTSTATUS_INQ_PAGE		= 0x2,
-+	BTC_BTSTATUS_ACL_BUSY		= 0x3,
-+	BTC_BTSTATUS_SCO_BUSY		= 0x4,
-+	BTC_BTSTATUS_ACL_SCO_BUSY	= 0x5,
-+	BTC_BTSTATUS_MAX
-+};
-+
-+static const char *const bt_status_string[] = {
-+	"BT Non-Connected-idle",
-+	"BT Connected-idle",
-+	"BT Inq-page",
-+	"BT ACL-busy",
-+	"BT SCO-busy",
-+	"BT ACL-SCO-busy",
-+	"BT Non-Defined-state"
-+};
-+
-+enum btc_coex_algo {
-+	BTC_COEX_NOPROFILE		= 0x0,
-+	BTC_COEX_HFP			= 0x1,
-+	BTC_COEX_HID			= 0x2,
-+	BTC_COEX_A2DP			= 0x3,
-+	BTC_COEX_PAN			= 0x4,
-+	BTC_COEX_A2DP_HID		= 0x5,
-+	BTC_COEX_A2DP_PAN		= 0x6,
-+	BTC_COEX_PAN_HID		= 0x7,
-+	BTC_COEX_A2DP_PAN_HID		= 0x8,
-+	BTC_COEX_MAX
-+};
-+
-+static const char *const coex_algo_string[] = {
-+	"No Profile",
-+	"HFP",
-+	"HID",
-+	"A2DP",
-+	"PAN",
-+	"A2DP + HID",
-+	"A2DP + PAN",
-+	"PAN + HID",
-+	"A2DP + PAN + HID"
-+};
-+
-+enum btc_ext_ant_switch_type {
-+	BTC_SWITCH_NONE	= 0x0,
-+	BTC_SWITCH_SPDT	= 0x1,
-+	BTC_SWITCH_SP3T	= 0x2,
-+	BTC_SWITCH_DPDT = 0x3,
-+	BTC_SWITCH_ANTMAX
-+};
-+
-+enum btc_ext_ant_switch_ctrl_type {
-+	BTC_SWITCH_CTRL_BY_BBSW		= 0x0,
-+	BTC_SWITCH_CTRL_BY_PTA		= 0x1,
-+	BTC_SWITCH_CTRL_BY_ANTDIV	= 0x2,
-+	BTC_SWITCH_CTRL_BY_MAC		= 0x3,
-+	BTC_SWITCH_CTRL_BY_BT		= 0x4,
-+	BTC_SWITCH_CTRL_BY_FW		= 0x5,
-+	BTC_SWITCH_CTRL_MAX
-+};
-+
-+enum btc_ext_ant_switch_pos_type {
-+	BTC_SWITCH_TO_BT		= 0x0,
-+	BTC_SWITCH_TO_WLG		= 0x1,
-+	BTC_SWITCH_TO_WLA		= 0x2,
-+	BTC_SWITCH_TO_NOCARE		= 0x3,
-+	BTC_SWITCH_TO_WLG_BT		= 0x4,
-+	BTC_SWITCH_TO_MAX
-+};
-+
-+enum btx_set_ant_phase {
-+	BTC_ANT_INIT			= 0x0,
-+	BTC_ANT_WONLY			= 0x1,
-+	BTC_ANT_WOFF			= 0x2,
-+	BTC_ANT_2G			= 0x3,
-+	BTC_ANT_5G			= 0x4,
-+	BTC_ANT_BTMP			= 0x5,
-+	BTC_ANT_POWERON			= 0x6,
-+	BTC_ANT_2G_WL			= 0x7,
-+	BTC_ANT_2G_BT			= 0x8,
-+	BTC_ANT_MCC			= 0x9,
-+	BTC_ANT_2G_WLBT			= 0xa,
-+	BTC_ANT_2G_FREERUN		= 0xb,
-+	BTC_ANT_MAX
-+};
-+
-+/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/
-+enum btc_wl2bt_scoreboard {
-+	BTC_SCBD_ACTIVE		= BIT(0),
-+	BTC_SCBD_ON			= BIT(1),
-+	BTC_SCBD_SCAN		= BIT(2),
-+	BTC_SCBD_UNDERTEST	= BIT(3),
-+	BTC_SCBD_RXGAIN		= BIT(4),
-+	BTC_SCBD_WLBUSY		= BIT(7),
-+	BTC_SCBD_EXTFEM		= BIT(8),
-+	BTC_SCBD_TDMA		= BIT(9),
-+	BTC_SCBD_FIX2M		= BIT(10),
-+	BTC_SCBD_MAILBOX_DBG	= BIT(14),
-+	BTC_SCBD_ALL		= 0xffff,
-+	BTC_SCBD_ALL_32BIT	= 0xffffffff
-+};
-+
-+enum btc_bt2wl_scoreboard {
-+	BTC_SCBD_BT_ONOFF	= BIT(1),
-+	BTC_SCBD_BT_LPS		= BIT(7)
-+};
-+enum btc_scoreboard_bit_num {
-+	BTC_SCBD_16_BIT		= BIT(0),
-+	BTC_SCBD_32_BIT		= BIT(1)
-+};
-+
-+enum btc_runreason {
-+	BTC_RSN_2GSCANSTART	= 0x0,
-+	BTC_RSN_5GSCANSTART	= 0x1,
-+	BTC_RSN_SCANFINISH	= 0x2,
-+	BTC_RSN_2GSWITCHBAND	= 0x3,
-+	BTC_RSN_5GSWITCHBAND	= 0x4,
-+	BTC_RSN_2GCONSTART	= 0x5,
-+	BTC_RSN_5GCONSTART	= 0x6,
-+	BTC_RSN_2GCONFINISH	= 0x7,
-+	BTC_RSN_5GCONFINISH	= 0x8,
-+	BTC_RSN_2GMEDIA		= 0x9,
-+	BTC_RSN_5GMEDIA		= 0xa,
-+	BTC_RSN_MEDIADISCON	= 0xb,
-+	BTC_RSN_2GSPECIALPKT	= 0xc,
-+	BTC_RSN_5GSPECIALPKT	= 0xd,
-+	BTC_RSN_BTINFO		= 0xe,
-+	BTC_RSN_PERIODICAL	= 0xf,
-+	BTC_RSN_PNP		= 0x10,
-+	BTC_RSN_LPS		= 0x11,
-+	BTC_RSN_TIMERUP		= 0x12,
-+	BTC_RSN_WLSTATUS	= 0x13,
-+	BTC_RSN_BTCNT		= 0x14,
-+	BTC_RSN_RFK		= 0x15,
-+	BTC_RSN_MAX
-+};
-+
-+static const char *const run_reason_string[] = {
-+	"2G_SCAN_START",
-+	"5G_SCAN_START",
-+	"SCAN_FINISH",
-+	"2G_SWITCH_BAND",
-+	"5G_SWITCH_BAND",
-+	"2G_CONNECT_START",
-+	"5G_CONNECT_START",
-+	"2G_CONNECT_FINISH",
-+	"5G_CONNECT_FINISH",
-+	"2G_MEDIA_STATUS",
-+	"5G_MEDIA_STATUS",
-+	"MEDIA_DISCONNECT",
-+	"2G_SPECIALPKT",
-+	"5G_SPECIALPKT",
-+	"BTINFO",
-+	"PERIODICAL",
-+	"PNPNotify",
-+	"LPSNotify",
-+	"TimerUp",
-+	"WL_STATUS_CHANGE",
-+	"BT_CNT_CHANGE",
-+	"WL_RFK",
-+	"Reason Max"
-+};
-+
-+enum btc_wl_link_mode {
-+	BTC_WLINK_2G1PORT	= 0x0,
-+	BTC_WLINK_2GMPORT	= 0x1,
-+	BTC_WLINK_25GMPORT	= 0x2,
-+	BTC_WLINK_5G		= 0x3,
-+	BTC_WLINK_2GGO		= 0x4,
-+	BTC_WLINK_2GGC		= 0x5,
-+	BTC_WLINK_BTMR		= 0x6,
-+	BTC_WLINK_2GFREE	= 0x7,
-+	BTC_WLINK_MAX
-+};
-+
-+static const char *const coex_mode_string[] = {
-+	"2G-SP",
-+	"2G-MP",
-+	"25G-MP",
-+	"5G",
-+	"2G-P2P-GO",
-+	"2G-P2P-GC",
-+	"BT-MR",
-+	"2G1RFREE",
-+	"unknow"
-+};
-+
-+enum btc_bt_state_cnt {
-+	BTC_CNT_BT_RETRY	= 0x0,
-+	BTC_CNT_BT_REINIT	= 0x1,
-+	BTC_CNT_BT_POPEVENT	= 0x2,
-+	BTC_CNT_BT_SETUPLINK	= 0x3,
-+	BTC_CNT_BT_IGNWLANACT	= 0x4,
-+	BTC_CNT_BT_INQ		= 0x5,
-+	BTC_CNT_BT_PAGE		= 0x6,
-+	BTC_CNT_BT_ROLESWITCH	= 0x7,
-+	BTC_CNT_BT_AFHUPDATE	= 0x8,
-+	BTC_CNT_BT_DISABLE	= 0x9,
-+	BTC_CNT_BT_INFOUPDATE	= 0xa,
-+	BTC_CNT_BT_IQK		= 0xb,
-+	BTC_CNT_BT_IQKFAIL	= 0xc,
-+	BTC_CNT_BT_TRX		= 0xd,
-+	BTC_CNT_BT_MAX
-+};
-+
-+enum btc_wl_state_cnt {
-+	BTC_CNT_WL_SCANAP		= 0x0,
-+	BTC_CNT_WL_ARP			= 0x1,
-+	BTC_CNT_WL_GNTERR		= 0x2,
-+	BTC_CNT_WL_PSFAIL		= 0x3,
-+	BTC_CNT_WL_COEXRUN		= 0x4,
-+	BTC_CNT_WL_COEXINFO1		= 0x5,
-+	BTC_CNT_WL_COEXINFO2		= 0x6,
-+	BTC_CNT_WL_AUTOSLOT_HANG	= 0x7,
-+	BTC_CNT_WL_NOISY0		= 0x8,
-+	BTC_CNT_WL_NOISY1		= 0x9,
-+	BTC_CNT_WL_NOISY2		= 0xa,
-+	BTC_CNT_WL_ACTIVEPORT		= 0xb,
-+	BTC_CNT_WL_LEAKAP_NORX		= 0xc,
-+	BTC_CNT_WL_FW_NOTIFY		= 0xd,
-+	BTC_CNT_WL_2G_TDDTRY		= 0xe,
-+	BTC_CNT_WL_2G_FDDSTAY		= 0xf,
-+	BTC_CNT_WL_MAX
-+};
-+
-+enum btc_wl_crc_cnt {
-+	BTC_WLCRC_11BOK		= 0x0,
-+	BTC_WLCRC_11GOK		= 0x1,
-+	BTC_WLCRC_11NOK		= 0x2,
-+	BTC_WLCRC_11VHTOK	= 0x3,
-+	BTC_WLCRC_11BERR	= 0x4,
-+	BTC_WLCRC_11GERR	= 0x5,
-+	BTC_WLCRC_11NERR	= 0x6,
-+	BTC_WLCRC_11VHTERR	= 0x7,
-+	BTC_WLCRC_MAX
-+};
-+
-+enum btc_timer_cnt {
-+	BTC_TIMER_WL_STAYBUSY	= 0x0,
-+	BTC_TIMER_WL_COEXFREEZE	= 0x1,
-+	BTC_TIMER_WL_SPECPKT	= 0x2,
-+	BTC_TIMER_WL_CONNPKT	= 0x3,
-+	BTC_TIMER_WL_PNPWAKEUP	= 0x4,
-+	BTC_TIMER_WL_CCKLOCK	= 0x5,
-+	BTC_TIMER_WL_FWDBG	= 0x6,
-+	BTC_TIMER_BT_RELINK	= 0x7,
-+	BTC_TIMER_BT_REENABLE	= 0x8,
-+	BTC_TIMER_BT_MULTILINK	= 0x9,
-+	BTC_TIMER_BT_INQPAGE	= 0xa,
-+	BTC_TIMER_BT_A2DP_ACT	= 0xb,
-+	BTC_TIMER_MAX
-+};
-+
-+enum btc_wl_status_change {
-+	BTC_WLSTATUS_CHANGE_TOIDLE	= 0x0,
-+	BTC_WLSTATUS_CHANGE_TOBUSY	= 0x1,
-+	BTC_WLSTATUS_CHANGE_RSSI	= 0x2,
-+	BTC_WLSTATUS_CHANGE_LINKINFO	= 0x3,
-+	BTC_WLSTATUS_CHANGE_DIR	= 0x4,
-+	BTC_WLSTATUS_CHANGE_NOISY	= 0x5,
-+	BTC_WLSTATUS_CHANGE_BTCNT	= 0x6,
-+	BTC_WLSTATUS_CHANGE_LOCKTRY	= 0x7,
-+	BTC_WLSTATUS_CHANGE_MAX
-+};
-+
-+enum btc_commom_chip_setup {
-+	BTC_CSETUP_INIT_HW		= 0x0,
-+	BTC_CSETUP_ANT_SWITCH	= 0x1,
-+	BTC_CSETUP_GNT_FIX		= 0x2,
-+	BTC_CSETUP_GNT_DEBUG	= 0x3,
-+	BTC_CSETUP_RFE_TYPE		= 0x4,
-+	BTC_CSETUP_COEXINFO_HW	= 0x5,
-+	BTC_CSETUP_WL_TX_POWER	= 0x6,
-+	BTC_CSETUP_WL_RX_GAIN	= 0x7,
-+	BTC_CSETUP_WLAN_ACT_IPS = 0x8,
-+	BTC_CSETUP_BT_CTRL_ACT	= 0x9,
-+	BTC_CSETUP_MAX
-+};
-+
-+enum btc_indirect_reg_type {
-+	BTC_INDIRECT_1700	= 0x0,
-+	BTC_INDIRECT_7C0	= 0x1,
-+	BTC_INDIRECT_MAX
-+};
-+
-+enum btc_pstdma_type {
-+	BTC_PSTDMA_FORCE_LPSOFF	= 0x0,
-+	BTC_PSTDMA_FORCE_LPSON	= 0x1,
-+	BTC_PSTDMA_MAX
-+};
-+
-+enum btc_btrssi_type {
-+	BTC_BTRSSI_RATIO	= 0x0,
-+	BTC_BTRSSI_DBM		= 0x1,
-+	BTC_BTRSSI_MAX
-+};
-+
-+enum btc_wl_priority_mask {
-+	BTC_WLPRI_RX_RSP	= 2,
-+	BTC_WLPRI_TX_RSP	= 3,
-+	BTC_WLPRI_TX_BEACON	= 4,
-+	BTC_WLPRI_TX_OFDM	= 11,
-+	BTC_WLPRI_TX_CCK	= 12,
-+	BTC_WLPRI_TX_BEACONQ	= 27,
-+	BTC_WLPRI_RX_CCK	= 28,
-+	BTC_WLPRI_RX_OFDM	= 29,
-+	BTC_WLPRI_MAX
-+};
-+
-+enum btc_ext_chip_id{
-+        BTC_EXT_CHIP_NONE,
-+        BTC_EXT_CHIP_RF4CE,
-+        BTC_EXT_CHIP_MAX
-+};
-+
-+enum btc_ext_chip_mode{
-+        BTC_EXTMODE_NORMAL,
-+        BTC_EXTMODE_VOICE,
-+        BTC_EXTMODE_MAX
-+};
-+
-+enum btc_wl_rfk_type {
-+	BTC_PWR_TRK = 0,
-+	BTC_IQK = 1,
-+	BTC_LCK = 2,
-+	BTC_DPK = 3,
-+	BTC_TXGAPK = 4,
-+	BTC_RFK_TYPE_MAX
-+};
-+
-+enum btc_wl_rfk_state {
-+	BTC_RFK_START = 0,
-+	BTC_RFK_END = 1,
-+	BTC_RFK_STATE_MAX
-+};
-+
-+struct btc_board_info {
-+	/* The following is some board information */
-+	u8				bt_chip_type;
-+	u8				pg_ant_num;	/* pg ant number */
-+	u8				btdm_ant_num;	/* ant number for btdm */
-+	u8				btdm_ant_num_by_ant_det;	/* ant number for btdm after antenna detection */
-+	u8				btdm_ant_pos;		/* Bryant Add to indicate Antenna Position for (pg_ant_num = 2) && (btdm_ant_num =1)  (DPDT+1Ant case) */
-+	u8				single_ant_path;	/* current used for 8723b only, 1=>s0,  0=>s1 */
-+	boolean			tfbga_package;    /* for Antenna detect threshold */
-+	boolean			btdm_ant_det_finish;
-+	boolean			btdm_ant_det_already_init_phydm;
-+	u8				ant_type;
-+	u8				rfe_type;
-+	u8				ant_div_cfg;
-+	boolean			btdm_ant_det_complete_fail;
-+	u8				ant_det_result;
-+	boolean			ant_det_result_five_complete;
-+	u32				antdetval;
-+	u8				customerID;
-+	u8				customer_id;
-+	u8				ant_distance;	/* WL-BT antenna space for non-shared antenna  */
-+	u8				ext_chip_id;
-+};
-+
-+struct btc_coex_dm {
-+	boolean cur_ignore_wlan_act;
-+	boolean cur_ps_tdma_on;
-+	boolean cur_low_penalty_ra;
-+	boolean cur_wl_rx_low_gain_en;
-+
-+	u8	bt_rssi_state[4];
-+	u8	wl_rssi_state[4];
-+	u8	cur_ps_tdma;
-+	u8	ps_tdma_para[5];
-+	u8	fw_tdma_para[5];
-+	u8	cur_lps;
-+	u8	cur_rpwm;
-+	u8	cur_bt_pwr_lvl;
-+	u8	cur_bt_lna_lvl;
-+	u8	cur_wl_pwr_lvl;
-+	u8	cur_algorithm;
-+	u8	bt_status;
-+	u8	wl_chnl_info[3];
-+	u8	cur_toggle_para[6];
-+	u32	cur_ant_pos_type;
-+	u32	cur_switch_status;
-+	u32	setting_tdma;
-+};
-+
-+struct btc_coex_sta {
-+	boolean coex_freeze;
-+	boolean coex_freerun;
-+	boolean rf4ce_en;
-+	boolean force_freerun;
-+	boolean force_tdd;
-+
-+	boolean bt_disabled;
-+	boolean bt_disabled_pre;
-+	boolean bt_link_exist;
-+	boolean bt_whck_test;
-+	boolean bt_inq_page;
-+	boolean bt_inq_page_pre;
-+	boolean bt_inq_page_remain;
-+	boolean bt_inq;
-+	boolean bt_page;
-+	boolean bt_ble_voice;
-+	boolean bt_ble_exist;
-+	boolean bt_hfp_exist;
-+	boolean bt_a2dp_exist;
-+	boolean bt_hid_exist;
-+	boolean bt_pan_exist; // PAN or OPP
-+	boolean bt_opp_exist; //OPP only
-+	boolean bt_msft_mr_exist;
-+	boolean bt_acl_busy;
-+	boolean bt_fix_2M;
-+	boolean bt_setup_link;
-+	boolean bt_multi_link;
-+	boolean bt_multi_link_pre;
-+	boolean bt_multi_link_remain;
-+	boolean bt_a2dp_sink;
-+	boolean bt_reenable;
-+	boolean bt_ble_scan_en;
-+	boolean bt_slave;
-+	boolean bt_a2dp_active;
-+	boolean bt_a2dp_active_pre;
-+	boolean bt_a2dp_active_remain;
-+	boolean bt_slave_latency;
-+	boolean bt_init_scan;
-+	boolean bt_418_hid_exist;
-+	boolean bt_ble_hid_exist;
-+	boolean bt_mesh;
-+	boolean bt_ctr_ok;
-+
-+	boolean wl_under_lps;
-+	boolean wl_under_ips;
-+	boolean wl_under_4way;
-+	boolean	wl_hi_pri_task1;
-+	boolean	wl_hi_pri_task2;
-+	boolean wl_cck_lock;
-+	boolean wl_cck_lock_pre;
-+	boolean wl_cck_lock_ever;
-+	boolean wl_force_lps_ctrl;
-+	boolean wl_busy_pre;
-+	boolean wl_gl_busy;
-+	boolean wl_gl_busy_pre;
-+	boolean wl_linkscan_proc;
-+	boolean wl_mimo_ps;
-+	boolean wl_cck_dead_lock_ap;
-+	boolean wl_tx_limit_en;
-+	boolean wl_ampdu_limit_en;
-+	boolean wl_rxagg_limit_en;
-+	boolean wl_connecting;
-+	boolean wl_pnp_wakeup;
-+	boolean wl_slot_toggle;
-+	boolean wl_slot_toggle_change; /* if toggle to no-toggle */
-+	boolean wl_leak_ap; /* !is_no_wl_5ms_extend  */
-+	boolean wl_blacklist_ap;
-+	boolean wl_rfk;
-+
-+	u8	coex_table_type;
-+	u8 	coex_run_reason;
-+	u8	tdma_byte4_modify_pre;
-+	u8	kt_ver;
-+	u8	gnt_workaround_state;
-+	u8	tdma_timer_base;
-+	u8	bt_rssi;
-+	u8	bt_profile_num;
-+	u8	bt_profile_num_pre;
-+	u8	bt_info_c2h[BTC_BTINFO_SRC_MAX][BTC_BTINFO_LENGTH_MAX];
-+	u8	bt_info_lb2;
-+	u8	bt_info_lb3;
-+	u8	bt_info_hb0;
-+	u8	bt_info_hb1;
-+	u8	bt_info_hb2;
-+	u8	bt_info_hb3;
-+	u8	bt_ble_scan_type;
-+	u8	bt_afh_map[10];
-+	u8	bt_a2dp_vendor_id;
-+	u8	bt_hid_pair_num;
-+	u8	bt_hid_slot;
-+	u8	bt_a2dp_bitpool;
-+	u8	bt_iqk_state;
-+	u8	bt_sut_pwr_lvl[4];
-+	u8	bt_golden_rx_shift[4];
-+	u8	bt_ext_autoslot_thres;
-+	u8	ext_chip_mode;
-+
-+	u8	wl_pnp_state_pre;
-+	u8	wl_noisy_level;
-+	u8	wl_fw_dbg_info[10];
-+	u8	wl_fw_dbg_info_pre[10];
-+	u8	wl_rx_rate;
-+	u8	wl_tx_rate;
-+	u8	wl_rts_rx_rate;
-+	u8	wl_center_ch;
-+	u8	wl_tx_macid;
-+	u8	wl_tx_retry_ratio;
-+	u8	wl_coex_mode;
-+	u8	wl_iot_peer;
-+	u8	wl_ra_thres;
-+	u8	wl_ampdulen;
-+	u8	wl_rxagg_size;
-+	u8	wl_toggle_para[6];
-+	u8	wl_toggle_interval;
-+
-+	u16	score_board_BW;
-+	u32	score_board_WB;
-+	u16	bt_reg_vendor_ac;
-+	u16	bt_reg_vendor_ae;
-+	u32	bt_reg_vendor_dac;
-+	u16	bt_reg_modem_a;
-+	u16	bt_reg_rf_2;
-+	u16	bt_reg_rf_9;
-+	u16	wl_txlimit;
-+
-+	u32	score_board_BW_32bit;
-+	u32	score_board_WB_32bit;
-+	u32	hi_pri_tx;
-+	u32	hi_pri_rx;
-+	u32	lo_pri_tx;
-+	u32	lo_pri_rx;
-+	u32	bt_supported_feature;
-+	u32	bt_supported_version;
-+	u32	bt_ble_scan_para[3];
-+	u32	bt_a2dp_device_name;
-+	u32	bt_a2dp_flush_time;
-+	u32	wl_arfb1;
-+	u32	wl_arfb2;
-+	u32	wl_traffic_dir;
-+	u32	wl_bw;
-+	u32	cnt_bt_info_c2h[BTC_BTINFO_SRC_MAX];
-+	u32	cnt_bt[BTC_CNT_BT_MAX];
-+	u32	cnt_wl[BTC_CNT_WL_MAX];
-+	u32	cnt_timer[BTC_TIMER_MAX];
-+};
-+
-+struct btc_rfe_type {
-+	boolean ant_switch_exist;
-+	boolean ant_switch_diversity; /* If diversity on */
-+	boolean ant_switch_with_bt; /* If WL_2G/BT use ext-switch at shared-ant */
-+	u8	rfe_module_type;
-+	u8	ant_switch_type;
-+	u8	ant_switch_polarity;
-+	
-+	boolean band_switch_exist;
-+	u8	band_switch_type; /* 0:DPDT, 1:SPDT */
-+	u8	band_switch_polarity;
-+
-+	/*  If TRUE:  WLG at BTG, If FALSE: WLG at WLAG */
-+	boolean wlg_at_btg;
-+};
-+
-+
-+struct btc_wifi_link_info_ext {
-+	boolean is_all_under_5g;
-+	boolean is_mcc_25g;
-+	boolean is_p2p_connected;
-+	boolean is_ap_mode;
-+	boolean is_scan;
-+	boolean is_link;
-+	boolean is_roam;
-+	boolean is_4way;
-+	boolean is_32k;
-+	boolean is_connected;
-+	u8	num_of_active_port;
-+	u32	port_connect_status;
-+	u32	traffic_dir;
-+	u32	wifi_bw;
-+};
-+
-+struct btc_coex_table_para {
-+	u32 bt;	//0x6c0
-+	u32 wl;	//0x6c4
-+};
-+
-+struct btc_tdma_para {
-+	u8 para[5];
-+};
-+
-+struct btc_reg_byte_modify {
-+	u32 addr;
-+	u8 bitmask;
-+	u8 val;
-+};
-+
-+struct btc_5g_afh_map {
-+	u32 wl_5g_ch;
-+	u8 bt_skip_ch;
-+	u8 bt_skip_span;
-+};
-+
-+struct btc_rf_para {
-+	u8 wl_pwr_dec_lvl;
-+	u8 bt_pwr_dec_lvl;
-+	boolean wl_low_gain_en;
-+	u8 bt_lna_lvl;
-+};
-+
-+typedef enum _BTC_DBG_OPCODE {
-+	BTC_DBG_SET_COEX_NORMAL				= 0x0,
-+	BTC_DBG_SET_COEX_WIFI_ONLY				= 0x1,
-+	BTC_DBG_SET_COEX_BT_ONLY				= 0x2,
-+	BTC_DBG_SET_COEX_DEC_BT_PWR				= 0x3,
-+	BTC_DBG_SET_COEX_BT_AFH_MAP				= 0x4,
-+	BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT		= 0x5,
-+	BTC_DBG_SET_COEX_MANUAL_CTRL				= 0x6,
-+	BTC_DBG_MAX
-+} BTC_DBG_OPCODE, *PBTC_DBG_OPCODE;
-+
-+typedef enum _BTC_RSSI_STATE {
-+	BTC_RSSI_STATE_HIGH						= 0x0,
-+	BTC_RSSI_STATE_MEDIUM					= 0x1,
-+	BTC_RSSI_STATE_LOW						= 0x2,
-+	BTC_RSSI_STATE_STAY_HIGH					= 0x3,
-+	BTC_RSSI_STATE_STAY_MEDIUM				= 0x4,
-+	BTC_RSSI_STATE_STAY_LOW					= 0x5,
-+	BTC_RSSI_MAX
-+} BTC_RSSI_STATE, *PBTC_RSSI_STATE;
-+#define	BTC_RSSI_HIGH(_rssi_)	((_rssi_ == BTC_RSSI_STATE_HIGH || _rssi_ == BTC_RSSI_STATE_STAY_HIGH) ? TRUE:FALSE)
-+#define	BTC_RSSI_MEDIUM(_rssi_)	((_rssi_ == BTC_RSSI_STATE_MEDIUM || _rssi_ == BTC_RSSI_STATE_STAY_MEDIUM) ? TRUE:FALSE)
-+#define	BTC_RSSI_LOW(_rssi_)	((_rssi_ == BTC_RSSI_STATE_LOW || _rssi_ == BTC_RSSI_STATE_STAY_LOW) ? TRUE:FALSE)
-+
-+typedef enum _BTC_WIFI_ROLE {
-+	BTC_ROLE_STATION						= 0x0,
-+	BTC_ROLE_AP								= 0x1,
-+	BTC_ROLE_IBSS							= 0x2,
-+	BTC_ROLE_HS_MODE						= 0x3,
-+	BTC_ROLE_MAX
-+} BTC_WIFI_ROLE, *PBTC_WIFI_ROLE;
-+
-+typedef enum _BTC_WIRELESS_FREQ {
-+	BTC_FREQ_2_4G					= 0x0,
-+	BTC_FREQ_5G						= 0x1,
-+	BTC_FREQ_25G					= 0x2,
-+	BTC_FREQ_MAX
-+} BTC_WIRELESS_FREQ, *PBTC_WIRELESS_FREQ;
-+
-+typedef enum _BTC_WIFI_BW_MODE {
-+	BTC_WIFI_BW_LEGACY					= 0x0,
-+	BTC_WIFI_BW_HT20					= 0x1,
-+	BTC_WIFI_BW_HT40					= 0x2,
-+	BTC_WIFI_BW_HT80					= 0x3,
-+	BTC_WIFI_BW_HT160					= 0x4,
-+	BTC_WIFI_BW_MAX
-+} BTC_WIFI_BW_MODE, *PBTC_WIFI_BW_MODE;
-+
-+typedef enum _BTC_WIFI_TRAFFIC_DIR {
-+	BTC_WIFI_TRAFFIC_TX					= 0x0,
-+	BTC_WIFI_TRAFFIC_RX					= 0x1,
-+	BTC_WIFI_TRAFFIC_MAX
-+} BTC_WIFI_TRAFFIC_DIR, *PBTC_WIFI_TRAFFIC_DIR;
-+
-+typedef enum _BTC_WIFI_PNP {
-+	BTC_WIFI_PNP_WAKE_UP					= 0x0,
-+	BTC_WIFI_PNP_SLEEP						= 0x1,
-+	BTC_WIFI_PNP_SLEEP_KEEP_ANT				= 0x2,
-+	BTC_WIFI_PNP_WOWLAN					= 0x3,
-+	BTC_WIFI_PNP_MAX
-+} BTC_WIFI_PNP, *PBTC_WIFI_PNP;
-+
-+typedef enum _BTC_IOT_PEER {
-+	BTC_IOT_PEER_UNKNOWN = 0,
-+	BTC_IOT_PEER_REALTEK = 1,
-+	BTC_IOT_PEER_REALTEK_92SE = 2,
-+	BTC_IOT_PEER_BROADCOM = 3,
-+	BTC_IOT_PEER_RALINK = 4,
-+	BTC_IOT_PEER_ATHEROS = 5,
-+	BTC_IOT_PEER_CISCO = 6,
-+	BTC_IOT_PEER_MERU = 7,
-+	BTC_IOT_PEER_MARVELL = 8,
-+	BTC_IOT_PEER_REALTEK_SOFTAP = 9, /* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */
-+	BTC_IOT_PEER_SELF_SOFTAP = 10, /* Self is SoftAP */
-+	BTC_IOT_PEER_AIRGO = 11,
-+	BTC_IOT_PEER_INTEL				= 12,
-+	BTC_IOT_PEER_RTK_APCLIENT		= 13,
-+	BTC_IOT_PEER_REALTEK_81XX		= 14,
-+	BTC_IOT_PEER_REALTEK_WOW		= 15,
-+	BTC_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16,
-+	BTC_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17,
-+	BTC_IOT_PEER_MAX,
-+} BTC_IOT_PEER, *PBTC_IOT_PEER;
-+
-+/* for 8723b-d cut large current issue */
-+typedef enum _BTC_WIFI_COEX_STATE {
-+	BTC_WIFI_STAT_INIT,
-+	BTC_WIFI_STAT_IQK,
-+	BTC_WIFI_STAT_NORMAL_OFF,
-+	BTC_WIFI_STAT_MP_OFF,
-+	BTC_WIFI_STAT_NORMAL,
-+	BTC_WIFI_STAT_ANT_DIV,
-+	BTC_WIFI_STAT_MAX
-+} BTC_WIFI_COEX_STATE, *PBTC_WIFI_COEX_STATE;
-+
-+typedef enum _BTC_ANT_TYPE {
-+	BTC_ANT_TYPE_0,
-+	BTC_ANT_TYPE_1,
-+	BTC_ANT_TYPE_2,
-+	BTC_ANT_TYPE_3,
-+	BTC_ANT_TYPE_4,
-+	BTC_ANT_TYPE_MAX
-+} BTC_ANT_TYPE, *PBTC_ANT_TYPE;
-+
-+typedef enum _BTC_VENDOR {
-+	BTC_VENDOR_LENOVO,
-+	BTC_VENDOR_ASUS,
-+	BTC_VENDOR_OTHER
-+} BTC_VENDOR, *PBTC_VENDOR;
-+
-+
-+/* defined for BFP_BTC_GET */
-+typedef enum _BTC_GET_TYPE {
-+	/* type BOOLEAN */
-+	BTC_GET_BL_HS_OPERATION,
-+	BTC_GET_BL_HS_CONNECTING,
-+	BTC_GET_BL_WIFI_FW_READY,
-+	BTC_GET_BL_WIFI_CONNECTED,
-+	BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED,
-+	BTC_GET_BL_WIFI_LINK_INFO,
-+	BTC_GET_BL_WIFI_BUSY,
-+	BTC_GET_BL_WIFI_SCAN,
-+	BTC_GET_BL_WIFI_LINK,
-+	BTC_GET_BL_WIFI_ROAM,
-+	BTC_GET_BL_WIFI_4_WAY_PROGRESS,
-+	BTC_GET_BL_WIFI_UNDER_5G,
-+	BTC_GET_BL_WIFI_AP_MODE_ENABLE,
-+	BTC_GET_BL_WIFI_ENABLE_ENCRYPTION,
-+	BTC_GET_BL_WIFI_UNDER_B_MODE,
-+	BTC_GET_BL_EXT_SWITCH,
-+	BTC_GET_BL_WIFI_IS_IN_MP_MODE,
-+	BTC_GET_BL_IS_ASUS_8723B,
-+	BTC_GET_BL_RF4CE_CONNECTED,
-+	BTC_GET_BL_WIFI_LW_PWR_STATE,
-+
-+	/* type s4Byte */
-+	BTC_GET_S4_WIFI_RSSI,
-+	BTC_GET_S4_HS_RSSI,
-+
-+	/* type u4Byte */
-+	BTC_GET_U4_WIFI_BW,
-+	BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
-+	BTC_GET_U4_WIFI_TRAFFIC_DIR,
-+	BTC_GET_U4_WIFI_FW_VER,
-+	BTC_GET_U4_WIFI_PHY_VER,
-+	BTC_GET_U4_WIFI_LINK_STATUS,
-+	BTC_GET_U4_BT_PATCH_VER,
-+	BTC_GET_U4_VENDOR,
-+	BTC_GET_U4_SUPPORTED_VERSION,
-+	BTC_GET_U4_SUPPORTED_FEATURE,
-+	BTC_GET_U4_BT_DEVICE_INFO,
-+	BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL,
-+	BTC_GET_U4_BT_A2DP_FLUSH_VAL,
-+	BTC_GET_U4_WIFI_IQK_TOTAL,
-+	BTC_GET_U4_WIFI_IQK_OK,
-+	BTC_GET_U4_WIFI_IQK_FAIL,
-+
-+	/* type u1Byte */
-+	BTC_GET_U1_WIFI_DOT11_CHNL,
-+	BTC_GET_U1_WIFI_CENTRAL_CHNL,
-+	BTC_GET_U1_WIFI_HS_CHNL,
-+	BTC_GET_U1_WIFI_P2P_CHNL,
-+	BTC_GET_U1_MAC_PHY_MODE,
-+	BTC_GET_U1_AP_NUM,
-+	BTC_GET_U1_ANT_TYPE,
-+	BTC_GET_U1_IOT_PEER,
-+	BTC_GET_BL_WIFI_BSSID,
-+
-+	/* type u2Byte */
-+	BTC_GET_U2_BEACON_PERIOD,
-+
-+	/*===== for 1Ant ======*/
-+	BTC_GET_U1_LPS_MODE,
-+
-+	BTC_GET_MAX
-+} BTC_GET_TYPE, *PBTC_GET_TYPE;
-+
-+/* defined for BFP_BTC_SET */
-+typedef enum _BTC_SET_TYPE {
-+	/* type BOOLEAN */
-+	BTC_SET_BL_BT_DISABLE,
-+	BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE,
-+	BTC_SET_BL_BT_TRAFFIC_BUSY,
-+	BTC_SET_BL_BT_LIMITED_DIG,
-+	BTC_SET_BL_FORCE_TO_ROAM,
-+	BTC_SET_BL_TO_REJ_AP_AGG_PKT,
-+	BTC_SET_BL_BT_CTRL_AGG_SIZE,
-+	BTC_SET_BL_INC_SCAN_DEV_NUM,
-+	BTC_SET_BL_BT_TX_RX_MASK,
-+	BTC_SET_BL_MIRACAST_PLUS_BT,
-+	BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL,
-+	BTC_SET_BL_BT_GOLDEN_RX_RANGE,
-+
-+	/* type u1Byte */
-+	BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
-+	BTC_SET_U1_AGG_BUF_SIZE,
-+
-+	/* type trigger some action */
-+	BTC_SET_ACT_GET_BT_RSSI,
-+	BTC_SET_ACT_AGGREGATE_CTRL,
-+	BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
-+
-+	// for mimo ps mode setting
-+	BTC_SET_MIMO_PS_MODE,
-+	/*===== for 1Ant ======*/
-+	/* type BOOLEAN */
-+
-+	/* type u1Byte */
-+	BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE,
-+	BTC_SET_U1_LPS_VAL,
-+	BTC_SET_U1_RPWM_VAL,
-+	/* type trigger some action */
-+	BTC_SET_ACT_LEAVE_LPS,
-+	BTC_SET_ACT_ENTER_LPS,
-+	BTC_SET_ACT_NORMAL_LPS,
-+	BTC_SET_ACT_PRE_NORMAL_LPS,
-+	BTC_SET_ACT_POST_NORMAL_LPS,
-+	BTC_SET_ACT_DISABLE_LOW_POWER,
-+	BTC_SET_ACT_UPDATE_RAMASK,
-+	BTC_SET_ACT_SEND_MIMO_PS,
-+	/* BT Coex related */
-+	BTC_SET_ACT_CTRL_BT_INFO,
-+	BTC_SET_ACT_CTRL_BT_COEX,
-+	BTC_SET_ACT_CTRL_8723B_ANT,
-+	BTC_SET_RESET_COEX_VAR,
-+	/*=================*/
-+	BTC_SET_MAX
-+} BTC_SET_TYPE, *PBTC_SET_TYPE;
-+
-+typedef enum _BTC_DBG_DISP_TYPE {
-+	BTC_DBG_DISP_COEX_STATISTICS				= 0x0,
-+	BTC_DBG_DISP_BT_LINK_INFO				= 0x1,
-+	BTC_DBG_DISP_WIFI_STATUS				= 0x2,
-+	BTC_DBG_DISP_MAX
-+} BTC_DBG_DISP_TYPE, *PBTC_DBG_DISP_TYPE;
-+
-+typedef enum _BTC_NOTIFY_TYPE_IPS {
-+	BTC_IPS_LEAVE							= 0x0,
-+	BTC_IPS_ENTER							= 0x1,
-+	BTC_IPS_MAX
-+} BTC_NOTIFY_TYPE_IPS, *PBTC_NOTIFY_TYPE_IPS;
-+typedef enum _BTC_NOTIFY_TYPE_LPS {
-+	BTC_LPS_DISABLE							= 0x0,
-+	BTC_LPS_ENABLE							= 0x1,
-+	BTC_LPS_MAX
-+} BTC_NOTIFY_TYPE_LPS, *PBTC_NOTIFY_TYPE_LPS;
-+typedef enum _BTC_NOTIFY_TYPE_SCAN {
-+	BTC_SCAN_FINISH							= 0x0,
-+	BTC_SCAN_START							= 0x1,
-+	BTC_SCAN_START_2G						= 0x2,
-+	BTC_SCAN_START_5G						= 0x3,
-+	BTC_SCAN_MAX
-+} BTC_NOTIFY_TYPE_SCAN, *PBTC_NOTIFY_TYPE_SCAN;
-+typedef enum _BTC_NOTIFY_TYPE_SWITCHBAND {
-+	BTC_NOT_SWITCH							= 0x0,
-+	BTC_SWITCH_TO_24G						= 0x1,
-+	BTC_SWITCH_TO_5G						= 0x2,
-+	BTC_SWITCH_TO_24G_NOFORSCAN				= 0x3,
-+	BTC_SWITCH_MAX
-+} BTC_NOTIFY_TYPE_SWITCHBAND, *PBTC_NOTIFY_TYPE_SWITCHBAND;
-+typedef enum _BTC_NOTIFY_TYPE_ASSOCIATE {
-+	BTC_ASSOCIATE_FINISH						= 0x0,
-+	BTC_ASSOCIATE_START						= 0x1,
-+	BTC_ASSOCIATE_5G_FINISH						= 0x2,
-+	BTC_ASSOCIATE_5G_START						= 0x3,
-+	BTC_ASSOCIATE_MAX
-+} BTC_NOTIFY_TYPE_ASSOCIATE, *PBTC_NOTIFY_TYPE_ASSOCIATE;
-+typedef enum _BTC_NOTIFY_TYPE_MEDIA_STATUS {
-+	BTC_MEDIA_DISCONNECT					= 0x0,
-+	BTC_MEDIA_CONNECT						= 0x1,
-+	BTC_MEDIA_CONNECT_5G					= 0x02,
-+	BTC_MEDIA_MAX
-+} BTC_NOTIFY_TYPE_MEDIA_STATUS, *PBTC_NOTIFY_TYPE_MEDIA_STATUS;
-+typedef enum _BTC_NOTIFY_TYPE_SPECIFIC_PACKET {
-+	BTC_PACKET_UNKNOWN					= 0x0,
-+	BTC_PACKET_DHCP							= 0x1,
-+	BTC_PACKET_ARP							= 0x2,
-+	BTC_PACKET_EAPOL						= 0x3,
-+	BTC_PACKET_MAX
-+} BTC_NOTIFY_TYPE_SPECIFIC_PACKET, *PBTC_NOTIFY_TYPE_SPECIFIC_PACKET;
-+typedef enum _BTC_NOTIFY_TYPE_STACK_OPERATION {
-+	BTC_STACK_OP_NONE					= 0x0,
-+	BTC_STACK_OP_INQ_PAGE_PAIR_START		= 0x1,
-+	BTC_STACK_OP_INQ_PAGE_PAIR_FINISH	= 0x2,
-+	BTC_STACK_OP_MAX
-+} BTC_NOTIFY_TYPE_STACK_OPERATION, *PBTC_NOTIFY_TYPE_STACK_OPERATION;
-+
-+typedef enum _BTC_LINK_CHANGE_TYPE{
-+	BTC_LINK_CHANGE_TYPE_NONE			= 0x0,
-+	BTC_LINK_CHANGE_TYPE_ECSA_START		= 0x1,
-+	BTC_LINK_CHANGE_TYPE_ECSA_DONE		= 0x2,
-+	BTC_LINK_CHANGE_TYPE_MAX
-+}BTC_LINK_CHANGE_TYPE,*PBTC_LINK_CHANGE_TYPE;
-+
-+/* Bryant Add */
-+typedef enum _BTC_ANTENNA_POS {
-+	BTC_ANTENNA_AT_MAIN_PORT				= 0x1,
-+	BTC_ANTENNA_AT_AUX_PORT				= 0x2,
-+} BTC_ANTENNA_POS, *PBTC_ANTENNA_POS;
-+
-+/* Bryant Add */
-+typedef enum _BTC_BT_OFFON {
-+	BTC_BT_OFF				= 0x0,
-+	BTC_BT_ON				= 0x1,
-+} BTC_BTOFFON, *PBTC_BT_OFFON;
-+
-+#define BTC_5G_BAND 0x80
-+
-+/*==================================================
-+For following block is for coex offload
-+==================================================*/
-+typedef struct _COL_H2C {
-+	u1Byte	opcode;
-+	u1Byte	opcode_ver:4;
-+	u1Byte	req_num:4;
-+	u1Byte	buf[1];
-+} COL_H2C, *PCOL_H2C;
-+
-+#define	COL_C2H_ACK_HDR_LEN	3
-+typedef struct _COL_C2H_ACK {
-+	u1Byte	status;
-+	u1Byte	opcode_ver:4;
-+	u1Byte	req_num:4;
-+	u1Byte	ret_len;
-+	u1Byte	buf[1];
-+} COL_C2H_ACK, *PCOL_C2H_ACK;
-+
-+#define	COL_C2H_IND_HDR_LEN	3
-+typedef struct _COL_C2H_IND {
-+	u1Byte	type;
-+	u1Byte	version;
-+	u1Byte	length;
-+	u1Byte	data[1];
-+} COL_C2H_IND, *PCOL_C2H_IND;
-+
-+/*============================================
-+NOTE: for debug message, the following define should match
-+the strings in coexH2cResultString.
-+============================================*/
-+typedef enum _COL_H2C_STATUS {
-+	/* c2h status */
-+	COL_STATUS_C2H_OK								= 0x00, /* Wifi received H2C request and check content ok. */
-+	COL_STATUS_C2H_UNKNOWN							= 0x01,	/* Not handled routine */
-+	COL_STATUS_C2H_UNKNOWN_OPCODE					= 0x02,	/* Invalid OP code, It means that wifi firmware received an undefiend OP code. */
-+	COL_STATUS_C2H_OPCODE_VER_MISMATCH			= 0x03, /* Wifi firmware and wifi driver mismatch, need to update wifi driver or wifi or. */
-+	COL_STATUS_C2H_PARAMETER_ERROR				= 0x04, /* Error paraneter.(ex: parameters = NULL but it should have values) */
-+	COL_STATUS_C2H_PARAMETER_OUT_OF_RANGE		= 0x05, /* Wifi firmware needs to check the parameters from H2C request and return the status.(ex: ch = 500, it's wrong) */
-+	/* other COL status start from here */
-+	COL_STATUS_C2H_REQ_NUM_MISMATCH			, /* c2h req_num mismatch, means this c2h is not we expected. */
-+	COL_STATUS_H2C_HALMAC_FAIL					, /* HALMAC return fail. */
-+	COL_STATUS_H2C_TIMTOUT						, /* not received the c2h response from fw */
-+	COL_STATUS_INVALID_C2H_LEN					, /* invalid coex offload c2h ack length, must >= 3 */
-+	COL_STATUS_COEX_DATA_OVERFLOW				, /* coex returned length over the c2h ack length. */
-+	COL_STATUS_MAX
-+} COL_H2C_STATUS, *PCOL_H2C_STATUS;
-+
-+#define	COL_MAX_H2C_REQ_NUM		16
-+
-+#define	COL_H2C_BUF_LEN			20
-+typedef enum _COL_OPCODE {
-+	COL_OP_WIFI_STATUS_NOTIFY					= 0x0,
-+	COL_OP_WIFI_PROGRESS_NOTIFY					= 0x1,
-+	COL_OP_WIFI_INFO_NOTIFY						= 0x2,
-+	COL_OP_WIFI_POWER_STATE_NOTIFY				= 0x3,
-+	COL_OP_SET_CONTROL							= 0x4,
-+	COL_OP_GET_CONTROL							= 0x5,
-+	COL_OP_WIFI_OPCODE_MAX
-+} COL_OPCODE, *PCOL_OPCODE;
-+
-+typedef enum _COL_IND_TYPE {
-+	COL_IND_BT_INFO								= 0x0,
-+	COL_IND_PSTDMA								= 0x1,
-+	COL_IND_LIMITED_TX_RX						= 0x2,
-+	COL_IND_COEX_TABLE							= 0x3,
-+	COL_IND_REQ									= 0x4,
-+	COL_IND_MAX
-+} COL_IND_TYPE, *PCOL_IND_TYPE;
-+
-+typedef struct _COL_SINGLE_H2C_RECORD {
-+	u1Byte					h2c_buf[COL_H2C_BUF_LEN];	/* the latest sent h2c buffer */
-+	u4Byte					h2c_len;
-+	u1Byte					c2h_ack_buf[COL_H2C_BUF_LEN];	/* the latest received c2h buffer */
-+	u4Byte					c2h_ack_len;
-+	u4Byte					count;									/* the total number of the sent h2c command */
-+	u4Byte					status[COL_STATUS_MAX];					/* the c2h status for the sent h2c command */
-+} COL_SINGLE_H2C_RECORD, *PCOL_SINGLE_H2C_RECORD;
-+
-+typedef struct _COL_SINGLE_C2H_IND_RECORD {
-+	u1Byte					ind_buf[COL_H2C_BUF_LEN];	/* the latest received c2h indication buffer */
-+	u4Byte					ind_len;
-+	u4Byte					count;									/* the total number of the rcvd c2h indication */
-+	u4Byte					status[COL_STATUS_MAX];					/* the c2h indication verified status */
-+} COL_SINGLE_C2H_IND_RECORD, *PCOL_SINGLE_C2H_IND_RECORD;
-+
-+typedef struct _BTC_OFFLOAD {
-+	/* H2C command related */
-+	u1Byte					h2c_req_num;
-+	u4Byte					cnt_h2c_sent;
-+	COL_SINGLE_H2C_RECORD	h2c_record[COL_OP_WIFI_OPCODE_MAX];
-+
-+	/* C2H Ack related */
-+	u4Byte					cnt_c2h_ack;
-+	u4Byte					status[COL_STATUS_MAX];
-+	struct completion		c2h_event[COL_MAX_H2C_REQ_NUM];	/* for req_num = 1~COL_MAX_H2C_REQ_NUM */
-+	u1Byte					c2h_ack_buf[COL_MAX_H2C_REQ_NUM][COL_H2C_BUF_LEN];
-+	u1Byte					c2h_ack_len[COL_MAX_H2C_REQ_NUM];
-+
-+	/* C2H Indication related */
-+	u4Byte						cnt_c2h_ind;
-+	COL_SINGLE_C2H_IND_RECORD	c2h_ind_record[COL_IND_MAX];
-+	u4Byte						c2h_ind_status[COL_STATUS_MAX];
-+	u1Byte						c2h_ind_buf[COL_H2C_BUF_LEN];
-+	u1Byte						c2h_ind_len;
-+} BTC_OFFLOAD, *PBTC_OFFLOAD;
-+extern BTC_OFFLOAD				gl_coex_offload;
-+/*==================================================*/
-+
-+/* BTC_LINK_MODE same as WIFI_LINK_MODE */
-+typedef enum _BTC_LINK_MODE{
-+	BTC_LINK_NONE=0,
-+	BTC_LINK_ONLY_GO,
-+	BTC_LINK_ONLY_GC,
-+	BTC_LINK_ONLY_STA,
-+	BTC_LINK_ONLY_AP,
-+	BTC_LINK_2G_MCC_GO_STA,
-+	BTC_LINK_5G_MCC_GO_STA,
-+	BTC_LINK_25G_MCC_GO_STA,
-+	BTC_LINK_2G_MCC_GC_STA,
-+	BTC_LINK_5G_MCC_GC_STA,
-+	BTC_LINK_25G_MCC_GC_STA,
-+	BTC_LINK_2G_SCC_GO_STA,
-+	BTC_LINK_5G_SCC_GO_STA,
-+	BTC_LINK_2G_SCC_GC_STA,
-+	BTC_LINK_5G_SCC_GC_STA,
-+	BTC_LINK_MAX=30
-+}BTC_LINK_MODE, *PBTC_LINK_MODE;
-+
-+
-+struct btc_wifi_link_info {
-+	BTC_LINK_MODE link_mode; /* LinkMode */
-+	u1Byte sta_center_channel; /* StaCenterChannel */
-+	u1Byte p2p_center_channel; /* P2PCenterChannel	*/
-+	BOOLEAN bany_client_join_go;
-+	BOOLEAN benable_noa;
-+	BOOLEAN bhotspot;
-+};
-+
-+#if 0
-+typedef enum _BTC_MULTI_PORT_TDMA_MODE {
-+	BTC_MULTI_PORT_TDMA_MODE_NONE=0,
-+	BTC_MULTI_PORT_TDMA_MODE_2G_SCC_GO,
-+	BTC_MULTI_PORT_TDMA_MODE_2G_P2P_GO,
-+	BTC_MULTI_PORT_TDMA_MODE_2G_HOTSPOT_GO
-+} BTC_MULTI_PORT_TDMA_MODE, *PBTC_MULTI_PORT_TDMA_MODE;
-+
-+typedef struct btc_multi_port_tdma_info {
-+	BTC_MULTI_PORT_TDMA_MODE btc_multi_port_tdma_mode;
-+	u1Byte start_time_from_bcn;
-+	u1Byte bt_time;
-+} BTC_MULTI_PORT_TDMA_INFO, *PBTC_MULTI_PORT_TDMA_INFO;
-+#endif
-+
-+typedef enum _btc_concurrent_mode {
-+	btc_concurrent_mode_none = 0,
-+	btc_concurrent_mode_2g_go_miracast,
-+	btc_concurrent_mode_2g_go_hotspot,
-+	btc_concurrent_mode_2g_scc_go_miracast_sta,
-+	btc_concurrent_mode_2g_scc_go_hotspot_sta,
-+	btc_concurrent_mode_2g_gc,
-+} btc_concurrent_mode, *pbtc_concurrent_mode;
-+
-+struct btc_concurrent_setting {
-+	btc_concurrent_mode btc_concurrent_mode;
-+	u1Byte start_time_from_bcn;
-+	u1Byte bt_time;
-+};
-+
-+typedef u1Byte
-+(*BFP_BTC_R1)(
-+	IN	PVOID			pBtcContext,
-+	IN	u4Byte			RegAddr
-+	);
-+typedef u2Byte
-+(*BFP_BTC_R2)(
-+	IN	PVOID			pBtcContext,
-+	IN	u4Byte			RegAddr
-+	);
-+typedef u4Byte
-+(*BFP_BTC_R4)(
-+	IN	PVOID			pBtcContext,
-+	IN	u4Byte			RegAddr
-+	);
-+typedef VOID
-+(*BFP_BTC_W1)(
-+	IN	PVOID			pBtcContext,
-+	IN	u4Byte			RegAddr,
-+	IN	u1Byte			Data
-+	);
-+typedef VOID
-+(*BFP_BTC_W1_BIT_MASK)(
-+	IN	PVOID			pBtcContext,
-+	IN	u4Byte			regAddr,
-+	IN	u1Byte			bitMask,
-+	IN	u1Byte			data1b
-+	);
-+typedef VOID
-+(*BFP_BTC_W2)(
-+	IN	PVOID			pBtcContext,
-+	IN	u4Byte			RegAddr,
-+	IN	u2Byte			Data
-+	);
-+typedef VOID
-+(*BFP_BTC_W4)(
-+	IN	PVOID			pBtcContext,
-+	IN	u4Byte			RegAddr,
-+	IN	u4Byte			Data
-+	);
-+typedef VOID
-+(*BFP_BTC_LOCAL_REG_W1)(
-+	IN	PVOID			pBtcContext,
-+	IN	u4Byte			RegAddr,
-+	IN	u1Byte			Data
-+	);
-+typedef u4Byte
-+(*BFP_BTC_R_LINDIRECT)(
-+	IN 	PVOID			pBtcContext,
-+	IN	u2Byte			reg_addr
-+	);
-+typedef u2Byte
-+(*BFP_BTC_R_SCBD)(
-+	IN 	PVOID			pBtcContext,
-+	IN	pu2Byte			score_board_val
-+	);
-+typedef u4Byte
-+(*BFP_BTC_R_SCBD_32BIT)(
-+	IN 	PVOID			pBtcContext,
-+	IN	pu4Byte			score_board_val
-+	);
-+typedef VOID
-+(*BFP_BTC_W_SCBD)(
-+	IN 	PVOID			pBtcContext,
-+	IN	u2Byte			bitpos,
-+	IN	BOOLEAN			state
-+	);
-+typedef VOID
-+(*BFP_BTC_W_SCBD_32BIT)(
-+	IN 	PVOID			pBtcContext,
-+	IN	u4Byte			bitpos,
-+	IN	BOOLEAN			state
-+	);
-+typedef VOID
-+(*BFP_BTC_W_LINDIRECT)(
-+	IN 	PVOID			pBtcContext,
-+	IN	u2Byte			reg_addr,
-+	IN	u4Byte			bit_mask,
-+	IN	u4Byte 			reg_value
-+	);
-+typedef VOID
-+(*BFP_BTC_SET_BB_REG)(
-+	IN	PVOID			pBtcContext,
-+	IN	u4Byte			RegAddr,
-+	IN	u4Byte			BitMask,
-+	IN	u4Byte			Data
-+	);
-+typedef u4Byte
-+(*BFP_BTC_GET_BB_REG)(
-+	IN	PVOID			pBtcContext,
-+	IN	u4Byte			RegAddr,
-+	IN	u4Byte			BitMask
-+	);
-+typedef VOID
-+(*BFP_BTC_SET_RF_REG)(
-+	IN	PVOID			pBtcContext,
-+	IN	enum rf_path		eRFPath,
-+	IN	u4Byte			RegAddr,
-+	IN	u4Byte			BitMask,
-+	IN	u4Byte			Data
-+	);
-+typedef u4Byte
-+(*BFP_BTC_GET_RF_REG)(
-+	IN	PVOID			pBtcContext,
-+	IN	enum rf_path		eRFPath,
-+	IN	u4Byte			RegAddr,
-+	IN	u4Byte			BitMask
-+	);
-+typedef VOID
-+(*BFP_BTC_FILL_H2C)(
-+	IN	PVOID			pBtcContext,
-+	IN	u1Byte			elementId,
-+	IN	u4Byte			cmdLen,
-+	IN	pu1Byte			pCmdBuffer
-+	);
-+
-+typedef	BOOLEAN
-+(*BFP_BTC_GET)(
-+	IN	PVOID			pBtCoexist,
-+	IN	u1Byte			getType,
-+	OUT	PVOID			pOutBuf
-+	);
-+
-+typedef	BOOLEAN
-+(*BFP_BTC_SET)(
-+	IN	PVOID			pBtCoexist,
-+	IN	u1Byte			setType,
-+	OUT	PVOID			pInBuf
-+	);
-+typedef u2Byte
-+(*BFP_BTC_SET_BT_REG)(
-+	IN	PVOID			pBtcContext,
-+	IN	u1Byte			regType,
-+	IN	u4Byte			offset,
-+	IN	u4Byte			value
-+	);
-+typedef BOOLEAN
-+(*BFP_BTC_SET_BT_ANT_DETECTION)(
-+	IN	PVOID			pBtcContext,
-+	IN	u1Byte			txTime,
-+	IN	u1Byte			btChnl
-+	);
-+
-+typedef BOOLEAN
-+(*BFP_BTC_SET_BT_TRX_MASK)(
-+	IN	PVOID			pBtcContext,
-+	IN	u1Byte			bt_trx_mask
-+	);
-+
-+typedef u4Byte
-+(*BFP_BTC_GET_BT_REG)(
-+	IN	PVOID			pBtcContext,
-+	IN	u1Byte			regType,
-+	IN	u4Byte			offset
-+	);
-+typedef VOID
-+(*BFP_BTC_DISP_DBG_MSG)(
-+	IN	PVOID			pBtCoexist,
-+	IN	u1Byte			dispType
-+	);
-+
-+typedef COL_H2C_STATUS
-+(*BFP_BTC_COEX_H2C_PROCESS)(
-+	IN	PVOID			pBtCoexist,
-+	IN	u1Byte			opcode,
-+	IN	u1Byte			opcode_ver,
-+	IN	pu1Byte			ph2c_par,
-+	IN	u1Byte			h2c_par_len
-+	);
-+
-+typedef u4Byte
-+(*BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE)(
-+	IN	PVOID			pBtcContext
-+	);
-+
-+typedef u4Byte
-+(*BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION)(
-+	IN	PVOID			pBtcContext
-+	);
-+
-+typedef u4Byte
-+(*BFP_BTC_GET_PHYDM_VERSION)(
-+	IN	PVOID			pBtcContext
-+	);
-+
-+typedef u1Byte
-+(*BFP_BTC_SET_TIMER) 	(
-+	IN	PVOID			pBtcContext,
-+	IN	u4Byte 			type,
-+	IN	u4Byte			val
-+	);
-+
-+typedef u4Byte
-+(*BFP_BTC_SET_ATOMIC) 	(
-+	IN	PVOID			pBtcContext,
-+	IN	pu4Byte 		target,
-+	IN	u4Byte			val
-+	);
-+
-+
-+typedef VOID
-+(*BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD)(
-+	IN	PVOID		pDM_Odm,
-+	IN	u1Byte		RA_offset_direction,
-+	IN	u1Byte		RA_threshold_offset
-+	);
-+
-+typedef u4Byte
-+(*BTC_PHYDM_CMNINFOQUERY)(
-+	IN		PVOID	pDM_Odm,
-+	IN		u1Byte	info_type
-+	);
-+
-+typedef VOID
-+(*BTC_REDUCE_WL_TX_POWER)(
-+	IN		PVOID		pDM_Odm,
-+	IN		s1Byte		tx_power
-+	);
-+
-+typedef VOID
-+(*BTC_PHYDM_MODIFY_ANTDIV_HWSW)(
-+	IN		PVOID	pDM_Odm,
-+	IN		u1Byte	type
-+	);
-+
-+typedef u1Byte
-+(*BFP_BTC_GET_ANT_DET_VAL_FROM_BT)(
-+
-+	IN	PVOID			pBtcContext
-+	);
-+
-+typedef u1Byte
-+(*BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT)(
-+	IN	PVOID			pBtcContext
-+	);
-+
-+typedef u4Byte
-+(*BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT)(
-+	IN	PVOID			pBtcContext,
-+	IN  u1Byte			scanType
-+	);
-+
-+typedef BOOLEAN
-+(*BFP_BTC_GET_BT_AFH_MAP_FROM_BT)(
-+	IN	PVOID			pBtcContext,
-+	IN	u1Byte			mapType,
-+	OUT	pu1Byte			afhMap
-+	);
-+
-+struct  btc_bt_info {
-+	boolean					bt_disabled;
-+	boolean				bt_enable_disable_change;
-+	u8					rssi_adjust_for_agc_table_on;
-+	u8					rssi_adjust_for_1ant_coex_type;
-+	boolean					pre_bt_ctrl_agg_buf_size;
-+	boolean					bt_ctrl_agg_buf_size;
-+	boolean					pre_reject_agg_pkt;
-+	boolean					reject_agg_pkt;
-+	boolean					increase_scan_dev_num;
-+	boolean					bt_tx_rx_mask;
-+	u8					pre_agg_buf_size;
-+	u8					agg_buf_size;
-+	boolean					bt_busy;
-+	boolean					limited_dig;
-+	u16					bt_hci_ver;
-+	u32					bt_real_fw_ver;
-+	u32					get_bt_fw_ver_cnt;
-+	u32					bt_get_fw_ver;
-+	boolean					miracast_plus_bt;
-+
-+	boolean					bt_disable_low_pwr;
-+
-+	boolean					bt_ctrl_lps;
-+	boolean					bt_lps_on;
-+	boolean					force_to_roam;	/* for 1Ant solution */
-+	u8					lps_val;
-+	u8					rpwm_val;
-+	u32					ra_mask;
-+};
-+
-+struct btc_stack_info {
-+	boolean					profile_notified;
-+	u16					hci_version;	/* stack hci version */
-+	u8					num_of_link;
-+	boolean					bt_link_exist;
-+	boolean					sco_exist;
-+	boolean					acl_exist;
-+	boolean					a2dp_exist;
-+	boolean					hid_exist;
-+	u8					num_of_hid;
-+	boolean					pan_exist;
-+	boolean					unknown_acl_exist;
-+	s8					min_bt_rssi;
-+};
-+
-+struct btc_bt_link_info {
-+	boolean					bt_link_exist;
-+	boolean					bt_hi_pri_link_exist;
-+	boolean					sco_exist;
-+	boolean					sco_only;
-+	boolean					a2dp_exist;
-+	boolean					a2dp_only;
-+	boolean					hid_exist;
-+	boolean					hid_only;
-+	boolean					pan_exist;
-+	boolean					pan_only;
-+	boolean					slave_role;
-+	boolean					acl_busy;
-+};
-+
-+#ifdef CONFIG_RF4CE_COEXIST
-+struct btc_rf4ce_info {
-+	u8					link_state;
-+};
-+#endif
-+
-+struct btc_statistics {
-+	u32					cnt_bind;
-+	u32					cnt_power_on;
-+	u32					cnt_pre_load_firmware;
-+	u32					cnt_init_hw_config;
-+	u32					cnt_init_coex_dm;
-+	u32					cnt_ips_notify;
-+	u32					cnt_lps_notify;
-+	u32					cnt_scan_notify;
-+	u32					cnt_connect_notify;
-+	u32					cnt_media_status_notify;
-+	u32					cnt_specific_packet_notify;
-+	u32					cnt_bt_info_notify;
-+	u32					cnt_rf_status_notify;
-+	u32					cnt_periodical;
-+	u32					cnt_coex_dm_switch;
-+	u32					cnt_stack_operation_notify;
-+	u32					cnt_dbg_ctrl;
-+	u32					cnt_rate_id_notify;
-+	u32					cnt_halt_notify;
-+	u32					cnt_pnp_notify;
-+};
-+
-+struct btc_coexist {
-+	BOOLEAN				bBinded;		/*make sure only one adapter can bind the data context*/
-+	PVOID				Adapter;		/*default adapter*/
-+	struct  btc_board_info		board_info;
-+	struct  btc_bt_info			bt_info;		/*some bt info referenced by non-bt module*/
-+	struct  btc_stack_info		stack_info;
-+	struct  btc_bt_link_info		bt_link_info;
-+	struct btc_wifi_link_info	wifi_link_info;
-+	struct btc_wifi_link_info_ext		wifi_link_info_ext;
-+	struct btc_coex_dm			coex_dm;
-+	struct btc_coex_sta			coex_sta;
-+	struct btc_rfe_type			rfe_type;
-+	const struct btc_chip_para		*chip_para;
-+	u8					wifi_black_bssid[6];
-+	u8					wifi_bssid[6];
-+
-+#ifdef CONFIG_RF4CE_COEXIST
-+	struct  btc_rf4ce_info		rf4ce_info;
-+#endif
-+	BTC_CHIP_INTERFACE		chip_interface;
-+	PVOID					odm_priv;
-+
-+	BOOLEAN					initilized;
-+	BOOLEAN					stop_coex_dm;
-+	BOOLEAN					manual_control;
-+	BOOLEAN					bdontenterLPS;
-+	pu1Byte					cli_buf;
-+	struct btc_statistics		statistics;
-+	u1Byte				pwrModeVal[10];
-+	BOOLEAN dbg_mode;
-+	BOOLEAN auto_report;
-+	u8	chip_type;
-+	BOOLEAN wl_rf_state_off;
-+
-+	/* function pointers */
-+	/* io related */
-+	BFP_BTC_R1			btc_read_1byte;
-+	BFP_BTC_W1			btc_write_1byte;
-+	BFP_BTC_W1_BIT_MASK	btc_write_1byte_bitmask;
-+	BFP_BTC_R2			btc_read_2byte;
-+	BFP_BTC_W2			btc_write_2byte;
-+	BFP_BTC_R4			btc_read_4byte;
-+	BFP_BTC_W4			btc_write_4byte;
-+	BFP_BTC_LOCAL_REG_W1	btc_write_local_reg_1byte;
-+	BFP_BTC_R_LINDIRECT		btc_read_linderct;
-+	BFP_BTC_W_LINDIRECT		btc_write_linderct;
-+	BFP_BTC_R_SCBD			btc_read_scbd;
-+	BFP_BTC_R_SCBD_32BIT	btc_read_scbd_32bit;
-+	BFP_BTC_W_SCBD			btc_write_scbd;
-+	BFP_BTC_W_SCBD_32BIT	btc_write_scbd_32bit;
-+
-+	/* read/write bb related */
-+	BFP_BTC_SET_BB_REG	btc_set_bb_reg;
-+	BFP_BTC_GET_BB_REG	btc_get_bb_reg;
-+
-+	/* read/write rf related */
-+	BFP_BTC_SET_RF_REG	btc_set_rf_reg;
-+	BFP_BTC_GET_RF_REG	btc_get_rf_reg;
-+
-+	/* fill h2c related */
-+	BFP_BTC_FILL_H2C		btc_fill_h2c;
-+	/* other */
-+	BFP_BTC_DISP_DBG_MSG	btc_disp_dbg_msg;
-+	/* normal get/set related */
-+	BFP_BTC_GET			btc_get;
-+	BFP_BTC_SET			btc_set;
-+
-+	BFP_BTC_GET_BT_REG	btc_get_bt_reg;
-+	BFP_BTC_SET_BT_REG	btc_set_bt_reg;
-+
-+	BFP_BTC_SET_BT_ANT_DETECTION	btc_set_bt_ant_detection;
-+
-+	BFP_BTC_COEX_H2C_PROCESS	btc_coex_h2c_process;
-+	BFP_BTC_SET_BT_TRX_MASK		btc_set_bt_trx_mask;
-+	BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE btc_get_bt_coex_supported_feature;
-+	BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION btc_get_bt_coex_supported_version;
-+	BFP_BTC_GET_PHYDM_VERSION		btc_get_bt_phydm_version;
-+	BFP_BTC_SET_TIMER				btc_set_timer;
-+	BFP_BTC_SET_ATOMIC			btc_set_atomic;
-+	BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD	btc_phydm_modify_RA_PCR_threshold;
-+	BTC_PHYDM_CMNINFOQUERY				btc_phydm_query_PHY_counter;
-+	BTC_REDUCE_WL_TX_POWER				btc_reduce_wl_tx_power;
-+	BTC_PHYDM_MODIFY_ANTDIV_HWSW		btc_phydm_modify_antdiv_hwsw;
-+	BFP_BTC_GET_ANT_DET_VAL_FROM_BT		btc_get_ant_det_val_from_bt;
-+	BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT	btc_get_ble_scan_type_from_bt;
-+	BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT	btc_get_ble_scan_para_from_bt;
-+	BFP_BTC_GET_BT_AFH_MAP_FROM_BT		btc_get_bt_afh_map_from_bt;
-+
-+	union {
-+		#ifdef CONFIG_RTL8822B
-+		struct coex_dm_8822b_1ant	coex_dm_8822b_1ant;
-+		struct coex_dm_8822b_2ant	coex_dm_8822b_2ant;
-+		#endif /* 8822B */
-+		#ifdef CONFIG_RTL8821C
-+		struct coex_dm_8821c_1ant	coex_dm_8821c_1ant;
-+		struct coex_dm_8821c_2ant	coex_dm_8821c_2ant;
-+		#endif /* 8821C */
-+        #ifdef CONFIG_RTL8723D
-+        struct coex_dm_8723d_1ant   coex_dm_8723d_1ant;
-+        struct coex_dm_8723d_2ant   coex_dm_8723d_2ant;
-+        #endif /* 8723D */
-+	};
-+
-+	union {
-+		#ifdef CONFIG_RTL8822B
-+		struct coex_sta_8822b_1ant	coex_sta_8822b_1ant;
-+		struct coex_sta_8822b_2ant	coex_sta_8822b_2ant;
-+		#endif /* 8822B */
-+		#ifdef CONFIG_RTL8821C
-+		struct coex_sta_8821c_1ant	coex_sta_8821c_1ant;
-+		struct coex_sta_8821c_2ant	coex_sta_8821c_2ant;
-+		#endif /* 8821C */
-+        #ifdef CONFIG_RTL8723D
-+        struct coex_sta_8723d_1ant  coex_sta_8723d_1ant;
-+        struct coex_sta_8723d_2ant  coex_sta_8723d_2ant;
-+        #endif /* 8723D */
-+	};
-+
-+	union {
-+		#ifdef CONFIG_RTL8822B
-+		struct rfe_type_8822b_1ant	rfe_type_8822b_1ant;
-+		struct rfe_type_8822b_2ant	rfe_type_8822b_2ant;
-+		#endif /* 8822B */
-+		#ifdef CONFIG_RTL8821C
-+		struct rfe_type_8821c_1ant	rfe_type_8821c_1ant;
-+		struct rfe_type_8821c_2ant	rfe_type_8821c_2ant;
-+		#endif /* 8821C */
-+	};
-+
-+	union {
-+		#ifdef CONFIG_RTL8822B
-+		struct wifi_link_info_8822b_1ant	wifi_link_info_8822b_1ant;
-+		struct wifi_link_info_8822b_2ant	wifi_link_info_8822b_2ant;
-+		#endif /* 8822B */
-+		#ifdef CONFIG_RTL8821C
-+		struct wifi_link_info_8821c_1ant	wifi_link_info_8821c_1ant;
-+		struct wifi_link_info_8821c_2ant	wifi_link_info_8821c_2ant;
-+		#endif /* 8821C */
-+	};
-+
-+};
-+typedef struct btc_coexist *PBTC_COEXIST;
-+
-+extern struct btc_coexist	GLBtCoexist;
-+
-+typedef	void
-+(*BFP_BTC_CHIP_SETUP)(
-+	IN	PBTC_COEXIST	pBtCoexist,
-+	IN	u1Byte			setType
-+	);
-+
-+struct btc_chip_para {
-+	const char				*chip_name;
-+	u32				para_ver_date;
-+	u32				para_ver;
-+	u32				bt_desired_ver;
-+	boolean			scbd_support;
-+	u32				scbd_reg;
-+	u8				scbd_bit_num;
-+	boolean			mailbox_support;
-+	boolean			lte_indirect_access;
-+	boolean			new_scbd10_def; /* TRUE: 1:fix 2M(8822c) */
-+	u8				indirect_type;	/* 0:17xx, 1:7cx */
-+	u8				pstdma_type; /* 0: LPSoff, 1:LPSon */
-+	u8				bt_rssi_type;
-+	u8				ant_isolation;
-+	u8				rssi_tolerance;
-+	u8				rx_path_num;
-+	u8				wl_rssi_step_num;
-+	const u8				*wl_rssi_step;
-+	u8				bt_rssi_step_num;
-+	const u8				*bt_rssi_step;
-+	u8				table_sant_num;
-+	const struct btc_coex_table_para 	*table_sant;
-+	u8				table_nsant_num;
-+	const struct btc_coex_table_para 	*table_nsant;
-+	u8				tdma_sant_num;
-+	const struct btc_tdma_para 	*tdma_sant;
-+	u8				tdma_nsant_num;
-+	const struct btc_tdma_para 	*tdma_nsant;
-+	u8				wl_rf_para_tx_num;
-+	const struct btc_rf_para		*wl_rf_para_tx;
-+	const struct btc_rf_para		*wl_rf_para_rx;
-+	u8				bt_afh_span_bw20;
-+	u8				bt_afh_span_bw40;
-+	u8				afh_5g_num;
-+	const struct btc_5g_afh_map	*afh_5g;
-+	BFP_BTC_CHIP_SETUP		chip_setup;
-+};
-+
-+BOOLEAN
-+EXhalbtcoutsrc_InitlizeVariables(
-+	IN	PVOID		Adapter
-+	);
-+VOID
-+EXhalbtcoutsrc_PowerOnSetting(
-+	IN	PBTC_COEXIST		pBtCoexist
-+	);
-+VOID
-+EXhalbtcoutsrc_PreLoadFirmware(
-+	IN	PBTC_COEXIST		pBtCoexist
-+	);
-+VOID
-+EXhalbtcoutsrc_InitHwConfig(
-+	IN	PBTC_COEXIST		pBtCoexist,
-+	IN	BOOLEAN				bWifiOnly
-+	);
-+VOID
-+EXhalbtcoutsrc_InitCoexDm(
-+	IN	PBTC_COEXIST		pBtCoexist
-+	);
-+VOID
-+EXhalbtcoutsrc_IpsNotify(
-+	IN	PBTC_COEXIST		pBtCoexist,
-+	IN	u1Byte			type
-+	);
-+VOID
-+EXhalbtcoutsrc_LpsNotify(
-+	IN	PBTC_COEXIST		pBtCoexist,
-+	IN	u1Byte			type
-+	);
-+VOID
-+EXhalbtcoutsrc_ScanNotify(
-+	IN	PBTC_COEXIST		pBtCoexist,
-+	IN	u1Byte			type
-+	);
-+VOID
-+EXhalbtcoutsrc_SetAntennaPathNotify(
-+	IN	PBTC_COEXIST	pBtCoexist,
-+	IN	u1Byte			type
-+	);
-+VOID
-+EXhalbtcoutsrc_ConnectNotify(
-+	IN	PBTC_COEXIST		pBtCoexist,
-+	IN	u1Byte			action
-+	);
-+VOID
-+EXhalbtcoutsrc_MediaStatusNotify(
-+	IN	PBTC_COEXIST		pBtCoexist,
-+	IN	RT_MEDIA_STATUS	mediaStatus
-+	);
-+VOID
-+EXhalbtcoutsrc_SpecificPacketNotify(
-+	IN	PBTC_COEXIST		pBtCoexist,
-+	IN	u1Byte			pktType
-+	);
-+VOID
-+EXhalbtcoutsrc_BtInfoNotify(
-+	IN	PBTC_COEXIST		pBtCoexist,
-+	IN	pu1Byte			tmpBuf,
-+	IN	u1Byte			length
-+	);
-+VOID
-+EXhalbtcoutsrc_RfStatusNotify(
-+	IN	PBTC_COEXIST		pBtCoexist,
-+	IN	u1Byte				type
-+	);
-+u4Byte
-+EXhalbtcoutsrc_CoexTimerCheck(
-+	IN	PBTC_COEXIST		pBtCoexist
-+	);
-+u4Byte
-+EXhalbtcoutsrc_WLStatusCheck(
-+	IN	PBTC_COEXIST		pBtCoexist
-+	);
-+VOID
-+EXhalbtcoutsrc_WlFwDbgInfoNotify(
-+	IN	PBTC_COEXIST		pBtCoexist,
-+	IN	pu1Byte			tmpBuf,
-+	IN	u1Byte			length
-+	);
-+VOID
-+EXhalbtcoutsrc_rx_rate_change_notify(
-+	IN	PBTC_COEXIST	pBtCoexist,
-+	IN 	BOOLEAN			is_data_frame,
-+	IN	u1Byte			btc_rate_id
-+	);
-+VOID
-+EXhalbtcoutsrc_StackOperationNotify(
-+	IN	PBTC_COEXIST		pBtCoexist,
-+	IN	u1Byte			type
-+	);
-+VOID
-+EXhalbtcoutsrc_HaltNotify(
-+	IN	PBTC_COEXIST		pBtCoexist
-+	);
-+VOID
-+EXhalbtcoutsrc_PnpNotify(
-+	IN	PBTC_COEXIST		pBtCoexist,
-+	IN	u1Byte			pnpState
-+	);
-+VOID
-+EXhalbtcoutsrc_TimerNotify(
-+	IN	PBTC_COEXIST		pBtCoexist,
-+	IN	u4Byte timer_type
-+);
-+VOID
-+EXhalbtcoutsrc_WLStatusChangeNotify(
-+	IN	PBTC_COEXIST		pBtCoexist,
-+	IN	u4Byte change_type
-+);
-+VOID
-+EXhalbtcoutsrc_WL_RFK_Notify(
-+	IN	PBTC_COEXIST 		pBtCoexist,
-+	IN	u1Byte			path,
-+	IN	u1Byte			type,
-+	IN	u1Byte			state
-+	);
-+VOID
-+EXhalbtcoutsrc_CoexDmSwitch(
-+	IN	PBTC_COEXIST		pBtCoexist
-+	);
-+VOID
-+EXhalbtcoutsrc_Periodical(
-+	IN	PBTC_COEXIST		pBtCoexist
-+	);
-+VOID
-+EXhalbtcoutsrc_DbgControl(
-+	IN	PBTC_COEXIST			pBtCoexist,
-+	IN	u1Byte				opCode,
-+	IN	u1Byte				opLen,
-+	IN	pu1Byte				pData
-+	);
-+VOID
-+EXhalbtcoutsrc_AntennaDetection(
-+	IN	PBTC_COEXIST			pBtCoexist,
-+	IN	u4Byte					centFreq,
-+	IN	u4Byte					offset,
-+	IN	u4Byte					span,
-+	IN	u4Byte					seconds
-+	);
-+VOID
-+EXhalbtcoutsrc_StackUpdateProfileInfo(
-+	VOID
-+	);
-+VOID
-+EXhalbtcoutsrc_SetHciVersion(
-+	IN	u2Byte	hciVersion
-+	);
-+VOID
-+EXhalbtcoutsrc_SetBtPatchVersion(
-+	IN	u2Byte	btHciVersion,
-+	IN	u2Byte	btPatchVersion
-+	);
-+VOID
-+EXhalbtcoutsrc_UpdateMinBtRssi(
-+	IN	s1Byte	btRssi
-+	);
-+#if 0
-+VOID
-+EXhalbtcoutsrc_SetBtExist(
-+	IN	BOOLEAN		bBtExist
-+	);
-+#endif
-+VOID
-+EXhalbtcoutsrc_SetChipType(
-+	IN	u1Byte		chipType
-+	);
-+VOID
-+EXhalbtcoutsrc_SetAntNum(
-+	IN	u1Byte		type,
-+	IN	u1Byte		antNum
-+	);
-+VOID
-+EXhalbtcoutsrc_SetSingleAntPath(
-+	IN	u1Byte		singleAntPath
-+	);
-+VOID
-+EXhalbtcoutsrc_DisplayBtCoexInfo(
-+	IN	PBTC_COEXIST		pBtCoexist
-+	);
-+VOID
-+EXhalbtcoutsrc_DisplayAntDetection(
-+	IN	PBTC_COEXIST		pBtCoexist
-+	);
-+
-+#define	MASKBYTE0		0xff
-+#define	MASKBYTE1		0xff00
-+#define	MASKBYTE2		0xff0000
-+#define	MASKBYTE3		0xff000000
-+#define	MASKHWORD	0xffff0000
-+#define	MASKLWORD		0x0000ffff
-+#define	MASKDWORD	0xffffffff
-+#define	MASK12BITS		0xfff
-+#define	MASKH4BITS		0xf0000000
-+#define	MASKOFDM_D	0xffc00000
-+#define	MASKCCK		0x3f3f3f3f
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/btc/mp_precomp.h b/drivers/staging/rtl8723cs/hal/btc/mp_precomp.h
-new file mode 100644
-index 000000000000..42645498666d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/btc/mp_precomp.h
-@@ -0,0 +1,168 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __MP_PRECOMP_H__
-+#define __MP_PRECOMP_H__
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+#include "btc_basic_types.h"
-+
-+#define BT_TMP_BUF_SIZE	100
-+
-+#ifdef PLATFORM_LINUX
-+#define rsprintf snprintf
-+#define rstrncat(dst, src, src_size) strncat(dst, src, src_size)
-+#elif defined(PLATFORM_WINDOWS)
-+#define rsprintf sprintf_s
-+#endif
-+
-+#define DCMD_Printf			DBG_BT_INFO
-+
-+#define delay_ms(ms)		rtw_mdelay_os(ms)
-+
-+#ifdef bEnable
-+#undef bEnable
-+#endif
-+
-+#define WPP_SOFTWARE_TRACE 0
-+
-+typedef enum _BTC_MSG_COMP_TYPE {
-+	COMP_COEX		= 0,
-+	COMP_MAX
-+} BTC_MSG_COMP_TYPE;
-+extern u4Byte GLBtcDbgType[];
-+
-+#define DBG_OFF			0
-+#define DBG_SEC			1
-+#define DBG_SERIOUS		2
-+#define DBG_WARNING		3
-+#define DBG_LOUD		4
-+#define DBG_TRACE		5
-+
-+#ifdef CONFIG_BT_COEXIST
-+#define BT_SUPPORT		1
-+#define COEX_SUPPORT	1
-+#define HS_SUPPORT		1
-+#else
-+#define BT_SUPPORT		0
-+#define COEX_SUPPORT	0
-+#define HS_SUPPORT		0
-+#endif
-+
-+/* for wifi only mode */
-+#include "hal_btcoex_wifionly.h"
-+
-+#ifdef CONFIG_BT_COEXIST
-+#define BTC_BTINFO_LENGTH_MAX 10
-+
-+struct wifi_only_cfg;
-+struct btc_coexist;
-+
-+#ifdef CONFIG_RTL8192E
-+#include "halbtc8192e1ant.h"
-+#include "halbtc8192e2ant.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8723B
-+#include "halbtc8723bwifionly.h"
-+#include "halbtc8723b1ant.h"
-+#include "halbtc8723b2ant.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+#include "halbtc8812a1ant.h"
-+#include "halbtc8812a2ant.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8821A
-+#include "halbtc8821a1ant.h"
-+#include "halbtc8821a2ant.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+#include "halbtc8703b1ant.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+#include "halbtc8723d1ant.h"
-+#include "halbtc8723d2ant.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+#include "halbtc8822bwifionly.h"
-+#include "halbtc8822b1ant.h"
-+#include "halbtc8822b2ant.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+#include "halbtc8821cwifionly.h"
-+#include "halbtc8821c1ant.h"
-+#include "halbtc8821c2ant.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+#include "halbtc8814a2ant.h"
-+#endif
-+
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+#include "halbtccommon.h"
-+
-+#ifdef CONFIG_RTL8822C
-+#include "halbtc8822cwifionly.h"
-+#include "halbtc8822c.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8723F
-+#include "halbtc8723fwifionly.h"
-+#include "halbtc8723f.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8192F
-+#include "halbtc8192f.h"
-+#endif
-+
-+#endif
-+
-+#include "halbtcoutsrc.h"
-+
-+#else /* CONFIG_BT_COEXIST */
-+
-+#ifdef CONFIG_RTL8723B
-+#include "halbtc8723bwifionly.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+#include "halbtc8822bwifionly.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+#include "halbtc8821cwifionly.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8822C
-+#include "halbtc8822cwifionly.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8723F
-+#include "halbtc8723fwifionly.h"
-+#endif
-+
-+#ifdef CONFIG_RTL8814B
-+#include "halbtc8814bwifionly.h"
-+#endif
-+
-+#endif /* CONFIG_BT_COEXIST */
-+
-+#endif /*  __MP_PRECOMP_H__ */
-diff --git a/drivers/staging/rtl8723cs/hal/efuse/efuse_mask.h b/drivers/staging/rtl8723cs/hal/efuse/efuse_mask.h
-new file mode 100644
-index 000000000000..dc4fdce2b280
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/efuse/efuse_mask.h
-@@ -0,0 +1,188 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifdef CONFIG_USB_HCI
-+
-+	#if defined(CONFIG_RTL8188E)
-+		#include "rtl8188e/HalEfuseMask8188E_USB.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8812A)
-+		#include "rtl8812a/HalEfuseMask8812A_USB.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8821A)
-+		#include "rtl8812a/HalEfuseMask8821A_USB.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8192E)
-+		#include "rtl8192e/HalEfuseMask8192E_USB.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8723B)
-+		#include "rtl8723b/HalEfuseMask8723B_USB.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8814A)
-+		#include "rtl8814a/HalEfuseMask8814A_USB.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8703B)
-+		#include "rtl8703b/HalEfuseMask8703B_USB.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8723D)
-+		#include "rtl8723d/HalEfuseMask8723D_USB.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8188F)
-+		#include "rtl8188f/HalEfuseMask8188F_USB.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8188GTV)
-+		#include "rtl8188gtv/HalEfuseMask8188GTV_USB.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8822B)
-+		#include "rtl8822b/HalEfuseMask8822B_USB.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8821C)
-+		#include "rtl8821c/HalEfuseMask8821C_USB.h"
-+	#endif
-+	
-+	#if defined(CONFIG_RTL8710B)
-+		#include "rtl8710b/HalEfuseMask8710B_USB.h"
-+	#endif
-+	
-+	#if defined(CONFIG_RTL8192F)
-+		#include "rtl8192f/HalEfuseMask8192F_USB.h"
-+	#endif
-+	#if defined(CONFIG_RTL8822C)
-+		#include "rtl8822c/HalEfuseMask8822C_USB.h"
-+	#endif
-+	#if defined(CONFIG_RTL8814B)
-+		#include "rtl8814b/HalEfuseMask8814B_USB.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8723F)
-+		#include "rtl8723f/HalEfuseMask8723F_USB.h"
-+	#endif
-+#endif /*CONFIG_USB_HCI*/
-+
-+#ifdef CONFIG_PCI_HCI
-+
-+	#if defined(CONFIG_RTL8188E)
-+		#include "rtl8188e/HalEfuseMask8188E_PCIE.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8812A)
-+		#include "rtl8812a/HalEfuseMask8812A_PCIE.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8821A)
-+		#include "rtl8812a/HalEfuseMask8821A_PCIE.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8192E)
-+		#include "rtl8192e/HalEfuseMask8192E_PCIE.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8723B)
-+		#include "rtl8723b/HalEfuseMask8723B_PCIE.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8814A)
-+		#include "rtl8814a/HalEfuseMask8814A_PCIE.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8703B)
-+		#include "rtl8703b/HalEfuseMask8703B_PCIE.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8822B)
-+		#include "rtl8822b/HalEfuseMask8822B_PCIE.h"
-+	#endif
-+	#if defined(CONFIG_RTL8723D)
-+		#include "rtl8723d/HalEfuseMask8723D_PCIE.h"
-+	#endif
-+	#if defined(CONFIG_RTL8821C)
-+		#include "rtl8821c/HalEfuseMask8821C_PCIE.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8192F)
-+		#include "rtl8192f/HalEfuseMask8192F_PCIE.h"
-+	#endif
-+	#if defined(CONFIG_RTL8822C)
-+		#include "rtl8822c/HalEfuseMask8822C_PCIE.h"
-+	#endif
-+	#if defined(CONFIG_RTL8814B)
-+		#include "rtl8814b/HalEfuseMask8814B_PCIE.h"
-+	#endif
-+#endif /*CONFIG_PCI_HCI*/
-+#ifdef CONFIG_SDIO_HCI
-+	#if defined(CONFIG_RTL8723B)
-+		#include "rtl8723b/HalEfuseMask8723B_SDIO.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8188E)
-+		#include "rtl8188e/HalEfuseMask8188E_SDIO.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8703B)
-+		#include "rtl8703b/HalEfuseMask8703B_SDIO.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8188F)
-+		#include "rtl8188f/HalEfuseMask8188F_SDIO.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8188GTV)
-+		#include "rtl8188gtv/HalEfuseMask8188GTV_SDIO.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8723D)
-+		#include "rtl8723d/HalEfuseMask8723D_SDIO.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8192E)
-+		#include "rtl8192e/HalEfuseMask8192E_SDIO.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8821A)
-+		#include "rtl8812a/HalEfuseMask8821A_SDIO.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8821C)
-+		#include "rtl8821c/HalEfuseMask8821C_SDIO.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8822B)
-+		#include "rtl8822b/HalEfuseMask8822B_SDIO.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8192F)
-+		#include "rtl8192f/HalEfuseMask8192F_SDIO.h"
-+	#endif
-+
-+
-+	#if defined(CONFIG_RTL8822C)
-+		#include "rtl8822c/HalEfuseMask8822C_SDIO.h"
-+	#endif
-+
-+	#if defined(CONFIG_RTL8723F)
-+		#include "rtl8723f/HalEfuseMask8723F_SDIO.h"
-+	#endif
-+#endif /*CONFIG_SDIO_HCI*/
-diff --git a/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_PCIE.c b/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_PCIE.c
-new file mode 100644
-index 000000000000..cc62c2236255
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_PCIE.c
-@@ -0,0 +1,94 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/* #include "Mp_Precomp.h" */
-+/* #include "../odm_precomp.h" */
-+
-+#include <drv_types.h>
-+#include "HalEfuseMask8703B_PCIE.h"
-+
-+
-+/******************************************************************************
-+*                           MPCIE.TXT
-+******************************************************************************/
-+
-+u8 Array_MP_8703B_MPCIE[] = {
-+	0xFF,
-+	0xF3,
-+	0x00,
-+	0x0E,
-+	0x70,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x07,
-+	0xF3,
-+	0xFF,
-+	0xFF,
-+	0xFF,
-+	0xFF,
-+	0xFF,
-+	0xF1,
-+	0x00,
-+	0x80,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+
-+};
-+
-+u16
-+EFUSE_GetArrayLen_MP_8703B_MPCIE(void)
-+{
-+	return sizeof(Array_MP_8703B_MPCIE) / sizeof(u8);
-+}
-+
-+void
-+EFUSE_GetMaskArray_MP_8703B_MPCIE(
-+		u8 *Array
-+)
-+{
-+	u16 len = EFUSE_GetArrayLen_MP_8703B_MPCIE(), i = 0;
-+
-+	for (i = 0; i < len; ++i)
-+		Array[i] = Array_MP_8703B_MPCIE[i];
-+}
-+BOOLEAN
-+EFUSE_IsAddressMasked_MP_8703B_MPCIE(
-+		u16 Offset
-+)
-+{
-+	int r = Offset / 16;
-+	int c = (Offset % 16) / 2;
-+	int result = 0;
-+
-+	if (c < 4) /* Upper double word */
-+		result = (Array_MP_8703B_MPCIE[r] & (0x10 << c));
-+	else
-+		result = (Array_MP_8703B_MPCIE[r] & (0x01 << (c - 4)));
-+
-+	return (result > 0) ? 0 : 1;
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_PCIE.h b/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_PCIE.h
-new file mode 100644
-index 000000000000..f7e108c9e61f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_PCIE.h
-@@ -0,0 +1,33 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+/******************************************************************************
-+*                           MPCIE.TXT
-+******************************************************************************/
-+
-+
-+u16
-+EFUSE_GetArrayLen_MP_8703B_MPCIE(void);
-+
-+void
-+EFUSE_GetMaskArray_MP_8703B_MPCIE(
-+		u8 *Array
-+);
-+
-+BOOLEAN
-+EFUSE_IsAddressMasked_MP_8703B_MPCIE(/* TC: Test Chip, MP: MP Chip */
-+		u16 Offset
-+);
-diff --git a/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_SDIO.c b/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_SDIO.c
-new file mode 100644
-index 000000000000..dfe02b37dc83
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_SDIO.c
-@@ -0,0 +1,95 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/* #include "Mp_Precomp.h" */
-+/* #include "../odm_precomp.h" */
-+
-+#include <drv_types.h>
-+#include "HalEfuseMask8703B_SDIO.h"
-+
-+
-+
-+/******************************************************************************
-+*                           MSDIO.TXT
-+******************************************************************************/
-+
-+u8 Array_MP_8703B_MSDIO[] = {
-+	0xFF,
-+	0xF3,
-+	0x00,
-+	0x0E,
-+	0x70,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x07,
-+	0xF3,
-+	0xFF,
-+	0xFF,
-+	0xFF,
-+	0xFF,
-+	0xFF,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+
-+};
-+
-+u16
-+EFUSE_GetArrayLen_MP_8703B_MSDIO(void)
-+{
-+	return sizeof(Array_MP_8703B_MSDIO) / sizeof(u8);
-+}
-+
-+void
-+EFUSE_GetMaskArray_MP_8703B_MSDIO(
-+		u8 *Array
-+)
-+{
-+	u16 len = EFUSE_GetArrayLen_MP_8703B_MSDIO(), i = 0;
-+
-+	for (i = 0; i < len; ++i)
-+		Array[i] = Array_MP_8703B_MSDIO[i];
-+}
-+BOOLEAN
-+EFUSE_IsAddressMasked_MP_8703B_MSDIO(
-+		u16 Offset
-+)
-+{
-+	int r = Offset / 16;
-+	int c = (Offset % 16) / 2;
-+	int result = 0;
-+
-+	if (c < 4) /* Upper double word */
-+		result = (Array_MP_8703B_MSDIO[r] & (0x10 << c));
-+	else
-+		result = (Array_MP_8703B_MSDIO[r] & (0x01 << (c - 4)));
-+
-+	return (result > 0) ? 0 : 1;
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_SDIO.h b/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_SDIO.h
-new file mode 100644
-index 000000000000..cadea4ea1874
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_SDIO.h
-@@ -0,0 +1,34 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+
-+/******************************************************************************
-+*                           MSDIO.TXT
-+******************************************************************************/
-+
-+
-+u16
-+EFUSE_GetArrayLen_MP_8703B_MSDIO(void);
-+
-+void
-+EFUSE_GetMaskArray_MP_8703B_MSDIO(
-+		u8 *Array
-+);
-+
-+BOOLEAN
-+EFUSE_IsAddressMasked_MP_8703B_MSDIO(/* TC: Test Chip, MP: MP Chip */
-+		u16 Offset
-+);
-diff --git a/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_USB.c b/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_USB.c
-new file mode 100644
-index 000000000000..2608d7979494
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_USB.c
-@@ -0,0 +1,92 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/* #include "Mp_Precomp.h" */
-+/* #include "../odm_precomp.h" */
-+
-+#include <drv_types.h>
-+#include "HalEfuseMask8703B_USB.h"
-+/******************************************************************************
-+*                           MUSB.TXT
-+******************************************************************************/
-+
-+u8 Array_MP_8703B_MUSB[] = {
-+	0xFF,
-+	0xF3,
-+	0x00,
-+	0x0E,
-+	0x70,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x07,
-+	0xF3,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0xFF,
-+	0xFF,
-+	0xFF,
-+	0xFF,
-+	0xB0,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+	0x00,
-+
-+};
-+
-+u16
-+EFUSE_GetArrayLen_MP_8703B_MUSB(void)
-+{
-+	return sizeof(Array_MP_8703B_MUSB) / sizeof(u8);
-+}
-+
-+void
-+EFUSE_GetMaskArray_MP_8703B_MUSB(
-+		u8 *Array
-+)
-+{
-+	u16 len = EFUSE_GetArrayLen_MP_8703B_MUSB(), i = 0;
-+
-+	for (i = 0; i < len; ++i)
-+		Array[i] = Array_MP_8703B_MUSB[i];
-+}
-+BOOLEAN
-+EFUSE_IsAddressMasked_MP_8703B_MUSB(
-+		u16 Offset
-+)
-+{
-+	int r = Offset / 16;
-+	int c = (Offset % 16) / 2;
-+	int result = 0;
-+
-+	if (c < 4) /* Upper double word */
-+		result = (Array_MP_8703B_MUSB[r] & (0x10 << c));
-+	else
-+		result = (Array_MP_8703B_MUSB[r] & (0x01 << (c - 4)));
-+
-+	return (result > 0) ? 0 : 1;
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_USB.h b/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_USB.h
-new file mode 100644
-index 000000000000..9644f07cda19
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/efuse/rtl8703b/HalEfuseMask8703B_USB.h
-@@ -0,0 +1,34 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+
-+/******************************************************************************
-+*                           MUSB.TXT
-+******************************************************************************/
-+
-+
-+u16
-+EFUSE_GetArrayLen_MP_8703B_MUSB(void);
-+
-+void
-+EFUSE_GetMaskArray_MP_8703B_MUSB(
-+		u8 *Array
-+);
-+
-+BOOLEAN
-+EFUSE_IsAddressMasked_MP_8703B_MUSB(/* TC: Test Chip, MP: MP Chip */
-+		u16 Offset
-+);
-diff --git a/drivers/staging/rtl8723cs/hal/hal_btcoex.c b/drivers/staging/rtl8723cs/hal/hal_btcoex.c
-new file mode 100644
-index 000000000000..1a5c88ab446f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_btcoex.c
-@@ -0,0 +1,6651 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define __HAL_BTCOEX_C__
-+
-+#ifdef CONFIG_BT_COEXIST
-+
-+#include <hal_data.h>
-+#include <hal_btcoex.h>
-+#include "btc/mp_precomp.h"
-+
-+/* ************************************
-+ *		Global variables
-+ * ************************************ */
-+const char *const BtProfileString[] = {
-+	"NONE",
-+	"A2DP",
-+	"PAN",
-+	"HID",
-+	"SCO",
-+};
-+
-+const char *const BtSpecString[] = {
-+	"1.0b",
-+	"1.1",
-+	"1.2",
-+	"2.0+EDR",
-+	"2.1+EDR",
-+	"3.0+HS",
-+	"4.0",
-+};
-+
-+const char *const BtLinkRoleString[] = {
-+	"Master",
-+	"Slave",
-+};
-+
-+const char *const h2cStaString[] = {
-+	"successful",
-+	"h2c busy",
-+	"rf off",
-+	"fw not read",
-+};
-+
-+const char *const ioStaString[] = {
-+	"success",
-+	"can not IO",
-+	"rf off",
-+	"fw not read",
-+	"wait io timeout",
-+	"invalid len",
-+	"idle Q empty",
-+	"insert waitQ fail",
-+	"unknown fail",
-+	"wrong level",
-+	"h2c stopped",
-+};
-+
-+const char *const GLBtcWifiBwString[] = {
-+	"11bg",
-+	"HT20",
-+	"HT40",
-+	"VHT80",
-+	"VHT160"
-+};
-+
-+const char *const GLBtcWifiFreqString[] = {
-+	"2.4G",
-+	"5G",
-+	"2.4G+5G"
-+};
-+
-+const char *const GLBtcIotPeerString[] = {
-+	"UNKNOWN",
-+	"REALTEK",
-+	"REALTEK_92SE",
-+	"BROADCOM",
-+	"RALINK",
-+	"ATHEROS",
-+	"CISCO",
-+	"MERU",
-+	"MARVELL",
-+	"REALTEK_SOFTAP", /* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */
-+	"SELF_SOFTAP", /* Self is SoftAP */
-+	"AIRGO",
-+	"INTEL",
-+	"RTK_APCLIENT",
-+	"REALTEK_81XX",
-+	"REALTEK_WOW",
-+	"REALTEK_JAGUAR_BCUTAP",
-+	"REALTEK_JAGUAR_CCUTAP"
-+};
-+
-+const char *const coexOpcodeString[] = {
-+	"Wifi status notify",
-+	"Wifi progress",
-+	"Wifi info",
-+	"Power state",
-+	"Set Control",
-+	"Get Control"
-+};
-+
-+const char *const coexIndTypeString[] = {
-+	"bt info",
-+	"pstdma",
-+	"limited tx/rx",
-+	"coex table",
-+	"request"
-+};
-+
-+const char *const coexH2cResultString[] = {
-+	"ok",
-+	"unknown",
-+	"un opcode",
-+	"opVer MM",
-+	"par Err",
-+	"par OoR",
-+	"reqNum MM",
-+	"halMac Fail",
-+	"h2c TimeOut",
-+	"Invalid c2h Len",
-+	"data overflow"
-+};
-+
-+#define HALBTCOUTSRC_AGG_CHK_WINDOW_IN_MS	8000
-+
-+struct btc_coexist GLBtCoexist;
-+BTC_OFFLOAD gl_coex_offload;
-+u8 GLBtcWiFiInScanState;
-+u8 GLBtcWiFiInIQKState;
-+u8 GLBtcWiFiInIPS;
-+u8 GLBtcWiFiInLPS;
-+u8 GLBtcBtCoexAliveRegistered;
-+
-+/*
-+ * BT control H2C/C2H
-+ */
-+/* EXT_EID */
-+typedef enum _bt_ext_eid {
-+	C2H_WIFI_FW_ACTIVE_RSP	= 0,
-+	C2H_TRIG_BY_BT_FW
-+} BT_EXT_EID;
-+
-+/* C2H_STATUS */
-+typedef enum _bt_c2h_status {
-+	BT_STATUS_OK = 0,
-+	BT_STATUS_VERSION_MISMATCH,
-+	BT_STATUS_UNKNOWN_OPCODE,
-+	BT_STATUS_ERROR_PARAMETER
-+} BT_C2H_STATUS;
-+
-+/* C2H BT OP CODES */
-+typedef enum _bt_op_code {
-+	BT_OP_GET_BT_VERSION					= 0x00,
-+	BT_OP_WRITE_REG_ADDR					= 0x0c,
-+	BT_OP_WRITE_REG_VALUE					= 0x0d,
-+
-+	BT_OP_READ_REG							= 0x11,
-+
-+	BT_LO_OP_GET_AFH_MAP_L					= 0x1e,
-+	BT_LO_OP_GET_AFH_MAP_M					= 0x1f,
-+	BT_LO_OP_GET_AFH_MAP_H					= 0x20,
-+
-+	BT_OP_SET_BT_TRX_MASK					= 0x29,
-+	BT_OP_GET_BT_COEX_SUPPORTED_FEATURE		= 0x2a,
-+	BT_OP_GET_BT_COEX_SUPPORTED_VERSION		= 0x2b,
-+	BT_OP_GET_BT_ANT_DET_VAL				= 0x2c,
-+	BT_OP_GET_BT_BLE_SCAN_TYPE				= 0x2d,
-+	BT_OP_GET_BT_BLE_SCAN_PARA				= 0x2e,
-+	BT_OP_GET_BT_DEVICE_INFO				= 0x30,
-+	BT_OP_GET_BT_FORBIDDEN_SLOT_VAL			= 0x31,
-+	BT_OP_SET_BT_LANCONSTRAIN_LEVEL			= 0x32,
-+	BT_OP_SET_BT_TEST_MODE_VAL				= 0x33,
-+	BT_OP_MAX
-+} BT_OP_CODE;
-+
-+#define BTC_MPOPER_TIMEOUT	50	/* unit: ms */
-+
-+#define C2H_MAX_SIZE		16
-+u8 GLBtcBtMpOperSeq;
-+_mutex GLBtcBtMpOperLock;
-+_timer GLBtcBtMpOperTimer;
-+_sema GLBtcBtMpRptSema;
-+u8 GLBtcBtMpRptSeq;
-+u8 GLBtcBtMpRptStatus;
-+u8 GLBtcBtMpRptRsp[C2H_MAX_SIZE];
-+u8 GLBtcBtMpRptRspSize;
-+u8 GLBtcBtMpRptWait;
-+u8 GLBtcBtMpRptWiFiOK;
-+u8 GLBtcBtMpRptBTOK;
-+
-+/*
-+ * Debug
-+ */
-+u32 GLBtcDbgType[COMP_MAX];
-+u8 GLBtcDbgBuf[BT_TMP_BUF_SIZE];
-+u8	gl_btc_trace_buf[BT_TMP_BUF_SIZE];
-+
-+typedef struct _btcoexdbginfo {
-+	u8 *info;
-+	u32 size; /* buffer total size */
-+	u32 len; /* now used length */
-+} BTCDBGINFO, *PBTCDBGINFO;
-+
-+BTCDBGINFO GLBtcDbgInfo;
-+
-+#define	BT_Operation(Adapter)						_FALSE
-+
-+static void DBG_BT_INFO_INIT(PBTCDBGINFO pinfo, u8 *pbuf, u32 size)
-+{
-+	if (NULL == pinfo)
-+		return;
-+
-+	_rtw_memset(pinfo, 0, sizeof(BTCDBGINFO));
-+
-+	if (pbuf && size) {
-+		pinfo->info = pbuf;
-+		pinfo->size = size;
-+	}
-+}
-+
-+void DBG_BT_INFO(u8 *dbgmsg)
-+{
-+	PBTCDBGINFO pinfo;
-+	u32 msglen, buflen;
-+	u8 *pbuf;
-+
-+
-+	pinfo = &GLBtcDbgInfo;
-+
-+	if (NULL == pinfo->info)
-+		return;
-+
-+	msglen = strlen(dbgmsg);
-+	if (pinfo->len + msglen > pinfo->size)
-+		return;
-+
-+	pbuf = pinfo->info + pinfo->len;
-+	_rtw_memcpy(pbuf, dbgmsg, msglen);
-+	pinfo->len += msglen;
-+}
-+
-+/* ************************************
-+ *		Debug related function
-+ * ************************************ */
-+static u8 halbtcoutsrc_IsBtCoexistAvailable(PBTC_COEXIST pBtCoexist)
-+{
-+	if (!pBtCoexist->bBinded ||
-+	    NULL == pBtCoexist->Adapter)
-+		return _FALSE;
-+	return _TRUE;
-+}
-+
-+static void halbtcoutsrc_DbgInit(void)
-+{
-+	u8	i;
-+
-+	for (i = 0; i < COMP_MAX; i++)
-+		GLBtcDbgType[i] = 0;
-+}
-+
-+static void halbtcoutsrc_EnterPwrLock(PBTC_COEXIST pBtCoexist)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj((PADAPTER)pBtCoexist->Adapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+
-+	_enter_pwrlock(&pwrpriv->lock);
-+}
-+
-+static void halbtcoutsrc_ExitPwrLock(PBTC_COEXIST pBtCoexist)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj((PADAPTER)pBtCoexist->Adapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+
-+	_exit_pwrlock(&pwrpriv->lock);
-+}
-+
-+static u8 halbtcoutsrc_IsHwMailboxExist(PBTC_COEXIST pBtCoexist)
-+{
-+	if (pBtCoexist->board_info.bt_chip_type == BTC_CHIP_CSR_BC4
-+	    || pBtCoexist->board_info.bt_chip_type == BTC_CHIP_CSR_BC8
-+	   )
-+		return _FALSE;
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter))
-+		return _FALSE;
-+	else
-+		return _TRUE;
-+}
-+
-+static u8 halbtcoutsrc_LeaveLps(PBTC_COEXIST pBtCoexist)
-+{
-+	PADAPTER padapter;
-+
-+
-+	padapter = pBtCoexist->Adapter;
-+
-+	pBtCoexist->bt_info.bt_ctrl_lps = _TRUE;
-+	pBtCoexist->bt_info.bt_lps_on = _FALSE;
-+
-+	return rtw_btcoex_LPS_Leave(padapter);
-+}
-+
-+void halbtcoutsrc_EnterLps(PBTC_COEXIST pBtCoexist)
-+{
-+	PADAPTER padapter;
-+
-+
-+	padapter = pBtCoexist->Adapter;
-+
-+	if (pBtCoexist->bdontenterLPS == _FALSE) {
-+		pBtCoexist->bt_info.bt_ctrl_lps = _TRUE;
-+		pBtCoexist->bt_info.bt_lps_on = _TRUE;
-+
-+		rtw_btcoex_LPS_Enter(padapter);
-+	}
-+}
-+
-+void halbtcoutsrc_NormalLps(PBTC_COEXIST pBtCoexist)
-+{
-+	PADAPTER padapter;
-+
-+
-+
-+	padapter = pBtCoexist->Adapter;
-+
-+	if (pBtCoexist->bt_info.bt_ctrl_lps) {
-+		pBtCoexist->bt_info.bt_lps_on = _FALSE;
-+		rtw_btcoex_LPS_Leave(padapter);
-+		pBtCoexist->bt_info.bt_ctrl_lps = _FALSE;
-+
-+		/* recover the LPS state to the original */
-+#if 0
-+		padapter->hal_func.UpdateLPSStatusHandler(
-+			padapter,
-+			pPSC->RegLeisurePsMode,
-+			pPSC->RegPowerSaveMode);
-+#endif
-+	}
-+}
-+
-+void halbtcoutsrc_Pre_NormalLps(PBTC_COEXIST pBtCoexist)
-+{
-+	PADAPTER padapter;
-+
-+	padapter = pBtCoexist->Adapter;
-+
-+	if (pBtCoexist->bt_info.bt_ctrl_lps) {
-+		pBtCoexist->bt_info.bt_lps_on = _FALSE;
-+		rtw_btcoex_LPS_Leave(padapter);
-+	}
-+}
-+
-+void halbtcoutsrc_Post_NormalLps(PBTC_COEXIST pBtCoexist)
-+{
-+	if (pBtCoexist->bt_info.bt_ctrl_lps)
-+		pBtCoexist->bt_info.bt_ctrl_lps = _FALSE;
-+}
-+
-+/*
-+ *  Constraint:
-+ *	   1. this function will request pwrctrl->lock
-+ */
-+void halbtcoutsrc_LeaveLowPower(PBTC_COEXIST pBtCoexist)
-+{
-+#ifdef CONFIG_LPS_LCLK
-+	PADAPTER padapter;
-+	PHAL_DATA_TYPE pHalData;
-+	struct pwrctrl_priv *pwrctrl;
-+	s32 ready;
-+	systime stime;
-+	s32 utime;
-+	u32 timeout; /* unit: ms */
-+
-+
-+	padapter = pBtCoexist->Adapter;
-+	pHalData = GET_HAL_DATA(padapter);
-+	pwrctrl = adapter_to_pwrctl(padapter);
-+	ready = _FAIL;
-+#ifdef LPS_RPWM_WAIT_MS
-+	timeout = LPS_RPWM_WAIT_MS;
-+#else /* !LPS_RPWM_WAIT_MS */
-+	timeout = 30;
-+#endif /* !LPS_RPWM_WAIT_MS */
-+
-+	if (GLBtcBtCoexAliveRegistered == _TRUE)
-+		return;
-+
-+	stime = rtw_get_current_time();
-+	do {
-+		ready = rtw_register_task_alive(padapter, BTCOEX_ALIVE);
-+		if (_SUCCESS == ready)
-+			break;
-+
-+		utime = rtw_get_passing_time_ms(stime);
-+		if (utime > timeout)
-+			break;
-+
-+		rtw_msleep_os(1);
-+	} while (1);
-+
-+	GLBtcBtCoexAliveRegistered = _TRUE;
-+#endif /* CONFIG_LPS_LCLK */
-+}
-+
-+/*
-+ *  Constraint:
-+ *	   1. this function will request pwrctrl->lock
-+ */
-+void halbtcoutsrc_NormalLowPower(PBTC_COEXIST pBtCoexist)
-+{
-+#ifdef CONFIG_LPS_LCLK
-+	PADAPTER padapter;
-+
-+	if (GLBtcBtCoexAliveRegistered == _FALSE)
-+		return;
-+
-+	padapter = pBtCoexist->Adapter;
-+	rtw_unregister_task_alive(padapter, BTCOEX_ALIVE);
-+
-+	GLBtcBtCoexAliveRegistered = _FALSE;
-+#endif /* CONFIG_LPS_LCLK */
-+}
-+
-+void halbtcoutsrc_DisableLowPower(PBTC_COEXIST pBtCoexist, u8 bLowPwrDisable)
-+{
-+	pBtCoexist->bt_info.bt_disable_low_pwr = bLowPwrDisable;
-+	if (bLowPwrDisable)
-+		halbtcoutsrc_LeaveLowPower(pBtCoexist);		/* leave 32k low power. */
-+	else
-+		halbtcoutsrc_NormalLowPower(pBtCoexist);	/* original 32k low power behavior. */
-+}
-+
-+void halbtcoutsrc_AggregationCheck(PBTC_COEXIST pBtCoexist)
-+{
-+	PADAPTER padapter;
-+	BOOLEAN bNeedToAct = _FALSE;
-+	static u32 preTime = 0;
-+	u32 curTime = 0;
-+
-+	padapter = pBtCoexist->Adapter;
-+
-+	/* ===================================== */
-+	/* To void continuous deleteBA=>addBA=>deleteBA=>addBA */
-+	/* This function is not allowed to continuous called. */
-+	/* It can only be called after 8 seconds. */
-+	/* ===================================== */
-+
-+	curTime = rtw_systime_to_ms(rtw_get_current_time());
-+	if ((curTime - preTime) < HALBTCOUTSRC_AGG_CHK_WINDOW_IN_MS)	/* over 8 seconds you can execute this function again. */
-+		return;
-+	else
-+		preTime = curTime;
-+
-+	if (pBtCoexist->bt_info.reject_agg_pkt) {
-+		bNeedToAct = _TRUE;
-+		pBtCoexist->bt_info.pre_reject_agg_pkt = pBtCoexist->bt_info.reject_agg_pkt;
-+	} else {
-+		if (pBtCoexist->bt_info.pre_reject_agg_pkt) {
-+			bNeedToAct = _TRUE;
-+			pBtCoexist->bt_info.pre_reject_agg_pkt = pBtCoexist->bt_info.reject_agg_pkt;
-+		}
-+
-+		if (pBtCoexist->bt_info.pre_bt_ctrl_agg_buf_size !=
-+		    pBtCoexist->bt_info.bt_ctrl_agg_buf_size) {
-+			bNeedToAct = _TRUE;
-+			pBtCoexist->bt_info.pre_bt_ctrl_agg_buf_size = pBtCoexist->bt_info.bt_ctrl_agg_buf_size;
-+		}
-+
-+		if (pBtCoexist->bt_info.bt_ctrl_agg_buf_size) {
-+			if (pBtCoexist->bt_info.pre_agg_buf_size !=
-+			    pBtCoexist->bt_info.agg_buf_size)
-+				bNeedToAct = _TRUE;
-+			pBtCoexist->bt_info.pre_agg_buf_size = pBtCoexist->bt_info.agg_buf_size;
-+		}
-+	}
-+
-+	if (bNeedToAct)
-+		rtw_btcoex_rx_ampdu_apply(padapter);
-+}
-+
-+u8 halbtcoutsrc_is_autoload_fail(PBTC_COEXIST pBtCoexist)
-+{
-+	PADAPTER padapter;
-+	PHAL_DATA_TYPE pHalData;
-+
-+	padapter = pBtCoexist->Adapter;
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	return pHalData->bautoload_fail_flag;
-+}
-+
-+u8 halbtcoutsrc_is_fw_ready(PBTC_COEXIST pBtCoexist)
-+{
-+	PADAPTER padapter;
-+
-+	padapter = pBtCoexist->Adapter;
-+
-+	return GET_HAL_DATA(padapter)->bFWReady;
-+}
-+
-+u8 halbtcoutsrc_IsDualBandConnected(PADAPTER padapter)
-+{
-+	u8 ret = BTC_MULTIPORT_SCC;
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(padapter) && (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))) {
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+		struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
-+		u8 band0 = mccobjpriv->iface[0]->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
-+		u8 band1 = mccobjpriv->iface[1]->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
-+
-+		if (band0 != band1)
-+			ret = BTC_MULTIPORT_MCC_DUAL_BAND;
-+		else
-+			ret = BTC_MULTIPORT_MCC_DUAL_CHANNEL;
-+	}
-+#endif
-+
-+	return ret;
-+}
-+
-+u8 halbtcoutsrc_IsWifiBusy(PADAPTER padapter)
-+{
-+	if (rtw_mi_check_status(padapter, MI_AP_ASSOC))
-+		return _TRUE;
-+	if (rtw_mi_busy_traffic_check(padapter))
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+static u32 _halbtcoutsrc_GetWifiLinkStatus(PADAPTER padapter)
-+{
-+	struct mlme_priv *pmlmepriv;
-+	u8 bp2p;
-+	u32 portConnectedStatus;
-+
-+
-+	pmlmepriv = &padapter->mlmepriv;
-+	bp2p = _FALSE;
-+	portConnectedStatus = 0;
-+
-+#ifdef CONFIG_P2P
-+	if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE))
-+		bp2p = _TRUE;
-+#endif /* CONFIG_P2P */
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+		if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
-+			if (_TRUE == bp2p)
-+				portConnectedStatus |= WIFI_P2P_GO_CONNECTED;
-+			else
-+				portConnectedStatus |= WIFI_AP_CONNECTED;
-+		} else {
-+			if (_TRUE == bp2p)
-+				portConnectedStatus |= WIFI_P2P_GC_CONNECTED;
-+			else
-+				portConnectedStatus |= WIFI_STA_CONNECTED;
-+		}
-+	}
-+
-+	return portConnectedStatus;
-+}
-+
-+u32 halbtcoutsrc_GetWifiLinkStatus(PBTC_COEXIST pBtCoexist)
-+{
-+	/* ================================= */
-+	/* return value: */
-+	/* [31:16]=> connected port number */
-+	/* [15:0]=> port connected bit define */
-+	/* ================================ */
-+
-+	PADAPTER padapter;
-+	u32 retVal;
-+	u32 portConnectedStatus, numOfConnectedPort;
-+	struct dvobj_priv *dvobj;
-+	_adapter *iface;
-+	int i;
-+
-+	padapter = pBtCoexist->Adapter;
-+	retVal = 0;
-+	portConnectedStatus = 0;
-+	numOfConnectedPort = 0;
-+	dvobj = adapter_to_dvobj(padapter);
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if ((iface) && rtw_is_adapter_up(iface)) {
-+			retVal = _halbtcoutsrc_GetWifiLinkStatus(iface);
-+			if (retVal) {
-+				portConnectedStatus |= retVal;
-+				numOfConnectedPort++;
-+			}
-+		}
-+	}
-+	retVal = (numOfConnectedPort << 16) | portConnectedStatus;
-+
-+	return retVal;
-+}
-+
-+struct btc_wifi_link_info halbtcoutsrc_getwifilinkinfo(PBTC_COEXIST pBtCoexist)
-+{
-+	u8 n_assoc_iface = 0, i =0, mcc_en = _FALSE;
-+	PADAPTER adapter = NULL;
-+	PADAPTER iface = NULL;
-+	PADAPTER sta_iface = NULL, p2p_iface = NULL, ap_iface = NULL;
-+	BTC_LINK_MODE btc_link_moe = BTC_LINK_MAX;
-+	struct dvobj_priv *dvobj = NULL;
-+	struct mlme_ext_priv *mlmeext = NULL;
-+	struct btc_wifi_link_info wifi_link_info;
-+
-+	adapter = (PADAPTER)pBtCoexist->Adapter;
-+	dvobj = adapter_to_dvobj(adapter);
-+	n_assoc_iface = rtw_mi_get_assoc_if_num(adapter);
-+
-+	/* init value */
-+	wifi_link_info.link_mode = BTC_LINK_NONE;
-+	wifi_link_info.sta_center_channel = 0;
-+	wifi_link_info.p2p_center_channel = 0;
-+	wifi_link_info.bany_client_join_go = _FALSE;
-+	wifi_link_info.benable_noa = _FALSE;
-+	wifi_link_info.bhotspot = _FALSE;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+		
-+		mlmeext = &iface->mlmeextpriv;
-+		if (MLME_IS_GO(iface)) {
-+			wifi_link_info.link_mode = BTC_LINK_ONLY_GO;
-+			wifi_link_info.p2p_center_channel =
-+				rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
-+			p2p_iface	 = iface;
-+			if (rtw_linked_check(iface))
-+				wifi_link_info.bany_client_join_go = _TRUE;
-+		} else if (MLME_IS_GC(iface)) {
-+			wifi_link_info.link_mode = BTC_LINK_ONLY_GC;
-+			wifi_link_info.p2p_center_channel =
-+				rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
-+			p2p_iface = iface;
-+		} else if (MLME_IS_AP(iface)) {
-+			wifi_link_info.link_mode = BTC_LINK_ONLY_AP;
-+			ap_iface = iface;
-+			wifi_link_info.p2p_center_channel =
-+				rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
-+		} else if (MLME_IS_STA(iface) && rtw_linked_check(iface)) {
-+			wifi_link_info.link_mode = BTC_LINK_ONLY_STA;
-+			wifi_link_info.sta_center_channel =
-+				rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
-+			sta_iface = iface;
-+		}
-+	}
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(adapter)) {
-+		if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
-+			mcc_en = _TRUE;
-+	}
-+#endif/* CONFIG_MCC_MODE */
-+
-+	if (n_assoc_iface == 0) {
-+		wifi_link_info.link_mode = BTC_LINK_NONE;
-+	} else if (n_assoc_iface == 1) {
-+		/* by pass */
-+	} else if (n_assoc_iface == 2) {	
-+		if (sta_iface && p2p_iface) {
-+			u8 band_sta = sta_iface->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
-+			u8 band_p2p = p2p_iface->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
-+			if (band_sta == band_p2p) {
-+				switch (band_sta) {
-+				case BAND_ON_2_4G:
-+					if (MLME_IS_GO(p2p_iface)) {
-+						#ifdef CONFIG_MCC_MODE
-+						wifi_link_info.link_mode =
-+							mcc_en == _TRUE ?  BTC_LINK_2G_MCC_GO_STA : BTC_LINK_2G_SCC_GO_STA;
-+						#else /* !CONFIG_MCC_MODE */
-+							wifi_link_info.link_mode = BTC_LINK_2G_SCC_GO_STA;
-+						#endif /* CONFIG_MCC_MODE */
-+					} else if (MLME_IS_GC(p2p_iface)) {
-+						#ifdef CONFIG_MCC_MODE
-+						wifi_link_info.link_mode =
-+							mcc_en == _TRUE ?  BTC_LINK_2G_MCC_GC_STA : BTC_LINK_2G_SCC_GC_STA;
-+						#else /* !CONFIG_MCC_MODE */
-+							wifi_link_info.link_mode = BTC_LINK_2G_SCC_GC_STA;
-+						#endif /* CONFIG_MCC_MODE */
-+					}
-+					break;
-+				case BAND_ON_5G:
-+					if (MLME_IS_GO(p2p_iface)) {
-+						#ifdef CONFIG_MCC_MODE
-+						wifi_link_info.link_mode =
-+							mcc_en == _TRUE ?  BTC_LINK_5G_MCC_GO_STA : BTC_LINK_5G_SCC_GO_STA;
-+						#else /* !CONFIG_MCC_MODE */
-+							wifi_link_info.link_mode = BTC_LINK_5G_SCC_GO_STA;
-+						#endif /* CONFIG_MCC_MODE */
-+					} else if (MLME_IS_GC(p2p_iface)) {
-+						#ifdef CONFIG_MCC_MODE
-+						wifi_link_info.link_mode =
-+							mcc_en == _TRUE ?  BTC_LINK_5G_MCC_GC_STA : BTC_LINK_5G_SCC_GC_STA;
-+						#else /* !CONFIG_MCC_MODE */
-+							wifi_link_info.link_mode = BTC_LINK_5G_SCC_GC_STA;
-+						#endif /* CONFIG_MCC_MODE */
-+					}
-+					break;
-+				}
-+			} else {
-+				if (MLME_IS_GO(p2p_iface))
-+					wifi_link_info.link_mode = BTC_LINK_25G_MCC_GO_STA;
-+				else if (MLME_IS_GC(p2p_iface))
-+					wifi_link_info.link_mode = BTC_LINK_25G_MCC_GC_STA;
-+			}
-+		}
-+
-+		if (sta_iface && ap_iface) {
-+			u8 band_sta = sta_iface->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
-+			u8 band_ap = ap_iface->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
-+
-+			if (band_sta == band_ap) {
-+				switch (band_sta) {
-+				case BAND_ON_2_4G:
-+					#ifdef CONFIG_MCC_MODE
-+					wifi_link_info.link_mode =
-+						mcc_en == _TRUE ?  BTC_LINK_2G_MCC_GO_STA : BTC_LINK_2G_SCC_GO_STA;
-+					#else /* !CONFIG_MCC_MODE */
-+					wifi_link_info.link_mode = BTC_LINK_2G_SCC_GO_STA;
-+					#endif /* CONFIG_MCC_MODE */
-+					break;
-+				case BAND_ON_5G:
-+					#ifdef CONFIG_MCC_MODE
-+					wifi_link_info.link_mode =
-+						mcc_en == _TRUE ?  BTC_LINK_5G_MCC_GO_STA : BTC_LINK_5G_SCC_GO_STA;
-+					#else /* !CONFIG_MCC_MODE */
-+					wifi_link_info.link_mode = BTC_LINK_5G_SCC_GO_STA;
-+					#endif /* CONFIG_MCC_MODE */
-+					break;
-+				}
-+			} else {
-+				wifi_link_info.link_mode = BTC_LINK_25G_MCC_GO_STA;
-+			}
-+		}
-+	} else {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			RTW_ERR("%s do not support n_assoc_iface > 2 (ant_num == 1)", __func__);
-+	}
-+
-+	return wifi_link_info;
-+}
-+
-+
-+static void _btmpoper_timer_hdl(void *p)
-+{
-+	if (GLBtcBtMpRptWait == _TRUE) {
-+		GLBtcBtMpRptWait = _FALSE;
-+		_rtw_up_sema(&GLBtcBtMpRptSema);
-+	}
-+}
-+
-+/*
-+ * !IMPORTANT!
-+ *	Before call this function, caller should acquire "GLBtcBtMpOperLock"!
-+ *	Othrewise there will be racing problem and something may go wrong.
-+ */
-+static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cmd, u8 size)
-+{
-+	PADAPTER padapter;
-+	u8 buf[H2C_BTMP_OPER_LEN] = {0};
-+	u8 buflen;
-+	u8 seq;
-+	s32 ret;
-+
-+
-+	if (!cmd && size)
-+		size = 0;
-+	if ((size + 2) > H2C_BTMP_OPER_LEN)
-+		return BT_STATUS_H2C_LENGTH_EXCEEDED;
-+	buflen = size + 2;
-+
-+	seq = GLBtcBtMpOperSeq & 0xF;
-+	GLBtcBtMpOperSeq++;
-+
-+	buf[0] = (opcodever & 0xF) | (seq << 4);
-+	buf[1] = opcode;
-+	if (cmd && size)
-+		_rtw_memcpy(buf + 2, cmd, size);
-+
-+	GLBtcBtMpRptWait = _TRUE;
-+	GLBtcBtMpRptWiFiOK = _FALSE;
-+	GLBtcBtMpRptBTOK = _FALSE;
-+	GLBtcBtMpRptStatus = 0;
-+	padapter = pBtCoexist->Adapter;
-+	_set_timer(&GLBtcBtMpOperTimer, BTC_MPOPER_TIMEOUT);
-+	if (rtw_hal_fill_h2c_cmd(padapter, H2C_BT_MP_OPER, buflen, buf) == _FAIL) {
-+		_cancel_timer_ex(&GLBtcBtMpOperTimer);
-+		ret = BT_STATUS_H2C_FAIL;
-+		goto exit;
-+	}
-+
-+	_rtw_down_sema(&GLBtcBtMpRptSema);
-+	/* GLBtcBtMpRptWait should be _FALSE here*/
-+
-+	if (GLBtcBtMpRptWiFiOK == _FALSE) {
-+		RTW_DBG("%s: Didn't get H2C Rsp Event!\n", __FUNCTION__);
-+		ret = BT_STATUS_H2C_TIMTOUT;
-+		goto exit;
-+	}
-+	if (GLBtcBtMpRptBTOK == _FALSE) {
-+		RTW_DBG("%s: Didn't get BT response!\n", __FUNCTION__);
-+		ret = BT_STATUS_H2C_BT_NO_RSP;
-+		goto exit;
-+	}
-+
-+	if (seq != GLBtcBtMpRptSeq) {
-+		RTW_ERR("%s: Sequence number not match!(%d!=%d)!\n",
-+			 __FUNCTION__, seq, GLBtcBtMpRptSeq);
-+		ret = BT_STATUS_C2H_REQNUM_MISMATCH;
-+		goto exit;
-+	}
-+
-+	switch (GLBtcBtMpRptStatus) {
-+	/* Examine the status reported from C2H */
-+	case BT_STATUS_OK:
-+		ret = BT_STATUS_BT_OP_SUCCESS;
-+		RTW_DBG("%s: C2H status = BT_STATUS_BT_OP_SUCCESS\n", __FUNCTION__);
-+		break;
-+	case BT_STATUS_VERSION_MISMATCH:
-+		ret = BT_STATUS_OPCODE_L_VERSION_MISMATCH;
-+		RTW_DBG("%s: C2H status = BT_STATUS_OPCODE_L_VERSION_MISMATCH\n", __FUNCTION__);
-+		break;
-+	case BT_STATUS_UNKNOWN_OPCODE:
-+		ret = BT_STATUS_UNKNOWN_OPCODE_L;
-+		RTW_DBG("%s: C2H status = MP_BT_STATUS_UNKNOWN_OPCODE_L\n", __FUNCTION__);
-+		break;
-+	case BT_STATUS_ERROR_PARAMETER:
-+		ret = BT_STATUS_PARAMETER_FORMAT_ERROR_L;
-+		RTW_DBG("%s: C2H status = MP_BT_STATUS_PARAMETER_FORMAT_ERROR_L\n", __FUNCTION__);
-+		break;
-+	default:
-+		ret = BT_STATUS_UNKNOWN_STATUS_L;
-+		RTW_DBG("%s: C2H status = MP_BT_STATUS_UNKNOWN_STATUS_L\n", __FUNCTION__);
-+		break;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+u32 halbtcoutsrc_GetBtPatchVer(PBTC_COEXIST pBtCoexist)
-+{
-+	if (pBtCoexist->bt_info.get_bt_fw_ver_cnt <= 5) {
-+		if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
-+			_irqL irqL;
-+			u8 ret;
-+
-+			_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+			ret = _btmpoper_cmd(pBtCoexist, BT_OP_GET_BT_VERSION, 0, NULL, 0);
-+			if (BT_STATUS_BT_OP_SUCCESS == ret) {
-+				pBtCoexist->bt_info.bt_real_fw_ver = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
-+				pBtCoexist->bt_info.get_bt_fw_ver_cnt++;
-+			}
-+
-+			_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+		} else {
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+			u8 dataLen = 2;
-+			u8 buf[4] = {0};
-+
-+			buf[0] = 0x0;	/* OP_Code */
-+			buf[1] = 0x0;	/* OP_Code_Length */
-+			BT_SendEventExtBtCoexControl(pBtCoexist->Adapter, _FALSE, dataLen, &buf[0]);
-+#endif /* !CONFIG_BT_COEXIST_SOCKET_TRX */
-+		}
-+	}
-+
-+	return pBtCoexist->bt_info.bt_real_fw_ver;
-+}
-+
-+s32 halbtcoutsrc_GetWifiRssi(PADAPTER padapter)
-+{
-+	return rtw_dm_get_min_rssi(padapter);
-+}
-+
-+u32 halbtcoutsrc_GetBtCoexSupportedFeature(void *pBtcContext)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	u32 ret = BT_STATUS_BT_OP_SUCCESS;
-+	u32 data = 0;
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+
-+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
-+		u8 buf[3] = {0};
-+		_irqL irqL;
-+		u8 op_code;
-+		u8 status;
-+
-+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+		op_code = BT_OP_GET_BT_COEX_SUPPORTED_FEATURE;
-+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
-+		if (status == BT_STATUS_BT_OP_SUCCESS)
-+			data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
-+		else
-+			ret = SET_BT_MP_OPER_RET(op_code, status);
-+
-+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+	} else
-+		ret = BT_STATUS_NOT_IMPLEMENT;
-+
-+	return data;
-+}
-+
-+u32 halbtcoutsrc_GetBtCoexSupportedVersion(void *pBtcContext)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	u32 ret = BT_STATUS_BT_OP_SUCCESS;
-+	u32 data = 0xFFFF;
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+
-+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
-+		u8 buf[3] = {0};
-+		_irqL irqL;
-+		u8 op_code;
-+		u8 status;
-+
-+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+		op_code = BT_OP_GET_BT_COEX_SUPPORTED_VERSION;
-+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
-+		if (status == BT_STATUS_BT_OP_SUCCESS)
-+			data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
-+		else
-+			ret = SET_BT_MP_OPER_RET(op_code, status);
-+
-+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+	} else
-+		ret = BT_STATUS_NOT_IMPLEMENT;
-+
-+	return data;
-+}
-+
-+u32 halbtcoutsrc_GetBtDeviceInfo(void *pBtcContext)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	u32 ret = BT_STATUS_BT_OP_SUCCESS;
-+	u32 btDeviceInfo = 0;
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+
-+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
-+		u8 buf[3] = {0};
-+		_irqL irqL;
-+		u8 op_code;
-+		u8 status;
-+
-+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+		op_code = BT_OP_GET_BT_DEVICE_INFO;
-+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
-+		if (status == BT_STATUS_BT_OP_SUCCESS)
-+			btDeviceInfo = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
-+		else
-+			ret = SET_BT_MP_OPER_RET(op_code, status);
-+
-+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+	} else
-+		ret = BT_STATUS_NOT_IMPLEMENT;
-+
-+	return btDeviceInfo;
-+}
-+
-+u32 halbtcoutsrc_GetBtForbiddenSlotVal(void *pBtcContext)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	u32 ret = BT_STATUS_BT_OP_SUCCESS;
-+	u32 btForbiddenSlotVal = 0;
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+
-+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
-+		u8 buf[3] = {0};
-+		_irqL irqL;
-+		u8 op_code;
-+		u8 status;
-+
-+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+		op_code = BT_OP_GET_BT_FORBIDDEN_SLOT_VAL;
-+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
-+		if (status == BT_STATUS_BT_OP_SUCCESS)
-+			btForbiddenSlotVal = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
-+		else
-+			ret = SET_BT_MP_OPER_RET(op_code, status);
-+
-+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+	} else
-+		ret = BT_STATUS_NOT_IMPLEMENT;
-+
-+	return btForbiddenSlotVal;
-+}
-+
-+static u8 halbtcoutsrc_GetWifiScanAPNum(PADAPTER padapter)
-+{
-+	struct mlme_priv *pmlmepriv;
-+	struct mlme_ext_priv *pmlmeext;
-+	static u8 scan_AP_num = 0;
-+
-+
-+	pmlmepriv = &padapter->mlmepriv;
-+	pmlmeext = &padapter->mlmeextpriv;
-+
-+	if (GLBtcWiFiInScanState == _FALSE) {
-+		if (pmlmepriv->num_of_scanned > 0xFF)
-+			scan_AP_num = 0xFF;
-+		else
-+			scan_AP_num = (u8)pmlmepriv->num_of_scanned;
-+	}
-+
-+	return scan_AP_num;
-+}
-+
-+u32 halbtcoutsrc_GetPhydmVersion(void *pBtcContext)
-+{
-+	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
-+	PADAPTER		Adapter = pBtCoexist->Adapter;
-+
-+#ifdef CONFIG_RTL8192E
-+	return RELEASE_VERSION_8192E;
-+#endif
-+
-+#ifdef CONFIG_RTL8821A
-+	return RELEASE_VERSION_8821A;
-+#endif
-+
-+#ifdef CONFIG_RTL8723B
-+	return RELEASE_VERSION_8723B;
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	return RELEASE_VERSION_8812A;
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	return RELEASE_VERSION_8703B;
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	return RELEASE_VERSION_8822B;
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	return RELEASE_VERSION_8723D;
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	return RELEASE_VERSION_8821C;
-+#endif
-+
-+#ifdef CONFIG_RTL8192F
-+	return RELEASE_VERSION_8192F;
-+#endif
-+
-+#ifdef CONFIG_RTL8822C
-+	return RELEASE_VERSION_8822C;
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	return RELEASE_VERSION_8814A;
-+#endif
-+
-+#ifdef CONFIG_RTL8814B
-+	return RELEASE_VERSION_8814B;
-+#endif
-+
-+#ifdef CONFIG_RTL8723F
-+	return RELEASE_VERSION_8723F;
-+#endif
-+
-+}
-+
-+u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	PADAPTER padapter;
-+	PHAL_DATA_TYPE pHalData;
-+	struct mlme_ext_priv *mlmeext;
-+	struct btc_wifi_link_info *wifi_link_info;
-+	u8 bSoftApExist, bVwifiExist;
-+	u8 *pu8;
-+	s32 *pS4Tmp;
-+	u32 *pU4Tmp;
-+	u8 *pU1Tmp;
-+	u16 *pU2Tmp;
-+	u8 ret;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return _FALSE;
-+
-+	padapter = pBtCoexist->Adapter;
-+	pHalData = GET_HAL_DATA(padapter);
-+	mlmeext = &padapter->mlmeextpriv;
-+	bSoftApExist = _FALSE;
-+	bVwifiExist = _FALSE;
-+	pu8 = (u8 *)pOutBuf;
-+	pS4Tmp = (s32 *)pOutBuf;
-+	pU4Tmp = (u32 *)pOutBuf;
-+	pU1Tmp = (u8 *)pOutBuf;
-+	pU2Tmp = (u16*)pOutBuf;
-+	wifi_link_info = (struct btc_wifi_link_info *)pOutBuf;
-+	ret = _TRUE;
-+
-+	switch (getType) {
-+	case BTC_GET_BL_HS_OPERATION:
-+		*pu8 = _FALSE;
-+		ret = _FALSE;
-+		break;
-+
-+	case BTC_GET_BL_HS_CONNECTING:
-+		*pu8 = _FALSE;
-+		ret = _FALSE;
-+		break;
-+
-+	case BTC_GET_BL_WIFI_FW_READY:
-+		*pu8 = halbtcoutsrc_is_fw_ready(pBtCoexist);
-+		break;
-+
-+	case BTC_GET_BL_WIFI_CONNECTED:
-+		*pu8 = (rtw_mi_check_status(padapter, MI_LINKED)) ? _TRUE : _FALSE;
-+		break;
-+
-+	case BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED:
-+		*pu8 = halbtcoutsrc_IsDualBandConnected(padapter);
-+		break;
-+
-+	case BTC_GET_BL_WIFI_BUSY:
-+		*pu8 = halbtcoutsrc_IsWifiBusy(padapter);
-+		break;
-+
-+	case BTC_GET_BL_WIFI_SCAN:
-+#if 0
-+		*pu8 = (rtw_mi_check_fwstate(padapter, WIFI_UNDER_SURVEY)) ? _TRUE : _FALSE;
-+#else
-+		/* Use the value of the new variable GLBtcWiFiInScanState to judge whether WiFi is in scan state or not, since the originally used flag
-+			WIFI_UNDER_SURVEY in fwstate may not be cleared in time */
-+		*pu8 = GLBtcWiFiInScanState;
-+#endif
-+		break;
-+
-+	case BTC_GET_BL_WIFI_LINK:
-+		*pu8 = (rtw_mi_check_status(padapter, MI_STA_LINKING)) ? _TRUE : _FALSE;
-+		break;
-+
-+	case BTC_GET_BL_WIFI_ROAM:
-+		*pu8 = (rtw_mi_check_status(padapter, MI_STA_LINKING)) ? _TRUE : _FALSE;
-+		break;
-+
-+	case BTC_GET_BL_WIFI_4_WAY_PROGRESS:
-+		*pu8 = _FALSE;
-+		break;
-+
-+	case BTC_GET_BL_WIFI_BSSID:
-+		_rtw_memcpy(pu8, get_bssid(&padapter->mlmepriv), ETH_ALEN);
-+		break;
-+
-+	case BTC_GET_BL_WIFI_UNDER_5G:
-+		*pu8 = (pHalData->current_band_type == BAND_ON_5G) ? _TRUE : _FALSE;
-+		break;
-+
-+	case BTC_GET_BL_WIFI_AP_MODE_ENABLE:
-+		*pu8 = (rtw_mi_check_status(padapter, MI_AP_MODE)) ? _TRUE : _FALSE;
-+		break;
-+
-+	case BTC_GET_BL_WIFI_ENABLE_ENCRYPTION:
-+		*pu8 = padapter->securitypriv.dot11PrivacyAlgrthm == 0 ? _FALSE : _TRUE;
-+		break;
-+
-+	case BTC_GET_BL_WIFI_UNDER_B_MODE:
-+		if (mlmeext->cur_wireless_mode == WIRELESS_11B)
-+			*pu8 = _TRUE;
-+		else
-+			*pu8 = _FALSE;
-+		break;
-+
-+	case BTC_GET_BL_WIFI_IS_IN_MP_MODE:
-+		if (padapter->registrypriv.mp_mode == 0)
-+			*pu8 = _FALSE;
-+		else
-+			*pu8 = _TRUE;
-+		break;
-+
-+	case BTC_GET_BL_EXT_SWITCH:
-+		*pu8 = _FALSE;
-+		break;
-+	case BTC_GET_BL_IS_ASUS_8723B:
-+		/* Always return FALSE in linux driver since this case is added only for windows driver */
-+		*pu8 = _FALSE;
-+		break;
-+
-+	case BTC_GET_BL_RF4CE_CONNECTED:
-+#ifdef CONFIG_RF4CE_COEXIST
-+		if (hal_btcoex_get_rf4ce_link_state() == 0)
-+			*pu8 = FALSE;
-+		else
-+			*pu8 = TRUE;
-+#else
-+		*pu8 = FALSE;
-+#endif
-+		break;
-+
-+	case BTC_GET_BL_WIFI_LW_PWR_STATE:
-+		/* return false due to coex do not run during 32K */
-+		*pu8 = FALSE;
-+		break;
-+
-+	case BTC_GET_S4_WIFI_RSSI:
-+		*pS4Tmp = halbtcoutsrc_GetWifiRssi(padapter);
-+		break;
-+
-+	case BTC_GET_S4_HS_RSSI:
-+		*pS4Tmp = 0;
-+		ret = _FALSE;
-+		break;
-+
-+	case BTC_GET_U4_WIFI_BW:
-+		if (IsLegacyOnly(mlmeext->cur_wireless_mode))
-+			*pU4Tmp = BTC_WIFI_BW_LEGACY;
-+		else {
-+			switch (pHalData->current_channel_bw) {
-+			case CHANNEL_WIDTH_20:
-+				*pU4Tmp = BTC_WIFI_BW_HT20;
-+				break;
-+			case CHANNEL_WIDTH_40:
-+				*pU4Tmp = BTC_WIFI_BW_HT40;
-+				break;
-+			case CHANNEL_WIDTH_80:
-+				*pU4Tmp = BTC_WIFI_BW_HT80;
-+				break;
-+			case CHANNEL_WIDTH_160:
-+				*pU4Tmp = BTC_WIFI_BW_HT160;
-+				break;
-+			default:
-+				RTW_INFO("[BTCOEX] unknown bandwidth(%d)\n", pHalData->current_channel_bw);
-+				*pU4Tmp = BTC_WIFI_BW_HT40;
-+				break;
-+			}
-+
-+		}
-+		break;
-+
-+	case BTC_GET_U4_WIFI_TRAFFIC_DIRECTION: 
-+	case BTC_GET_U4_WIFI_TRAFFIC_DIR:
-+		{
-+			PRT_LINK_DETECT_T plinkinfo;
-+			plinkinfo = &padapter->mlmepriv.LinkDetectInfo;
-+
-+			if (plinkinfo->NumTxOkInPeriod > plinkinfo->NumRxOkInPeriod)
-+				*pU4Tmp = BTC_WIFI_TRAFFIC_TX;
-+			else
-+				*pU4Tmp = BTC_WIFI_TRAFFIC_RX;
-+		}
-+		break;
-+
-+	case BTC_GET_U4_WIFI_FW_VER:
-+		*pU4Tmp = pHalData->firmware_version << 16;
-+		*pU4Tmp |= pHalData->firmware_sub_version;
-+		break;
-+
-+	case BTC_GET_U4_WIFI_PHY_VER:
-+		*pU4Tmp = halbtcoutsrc_GetPhydmVersion(pBtCoexist);
-+		break;
-+
-+	case BTC_GET_U4_WIFI_LINK_STATUS:
-+		*pU4Tmp = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist);
-+		break;
-+	case BTC_GET_BL_WIFI_LINK_INFO:
-+		*wifi_link_info = halbtcoutsrc_getwifilinkinfo(pBtCoexist);
-+		break;
-+	case BTC_GET_U4_BT_PATCH_VER:
-+		*pU4Tmp = halbtcoutsrc_GetBtPatchVer(pBtCoexist);
-+		break;
-+
-+	case BTC_GET_U4_VENDOR:
-+		*pU4Tmp = BTC_VENDOR_OTHER;
-+		break;
-+
-+	case BTC_GET_U4_SUPPORTED_VERSION:
-+		*pU4Tmp = halbtcoutsrc_GetBtCoexSupportedVersion(pBtCoexist);
-+		break;
-+	case BTC_GET_U4_SUPPORTED_FEATURE:
-+		*pU4Tmp = halbtcoutsrc_GetBtCoexSupportedFeature(pBtCoexist);
-+		break;
-+
-+	case BTC_GET_U4_BT_DEVICE_INFO:
-+		*pU4Tmp = halbtcoutsrc_GetBtDeviceInfo(pBtCoexist);
-+		break;
-+
-+	case BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL:
-+	case BTC_GET_U4_BT_A2DP_FLUSH_VAL:
-+		*pU4Tmp = halbtcoutsrc_GetBtForbiddenSlotVal(pBtCoexist);
-+		break;
-+
-+	case BTC_GET_U4_WIFI_IQK_TOTAL:
-+		*pU4Tmp = pHalData->odmpriv.n_iqk_cnt;
-+		break;
-+
-+	case BTC_GET_U4_WIFI_IQK_OK:
-+		*pU4Tmp = pHalData->odmpriv.n_iqk_ok_cnt;
-+		break;
-+
-+	case BTC_GET_U4_WIFI_IQK_FAIL:
-+		*pU4Tmp = pHalData->odmpriv.n_iqk_fail_cnt;
-+		break;
-+
-+	case BTC_GET_U1_WIFI_DOT11_CHNL:
-+		*pU1Tmp = padapter->mlmeextpriv.cur_channel;
-+		break;
-+
-+	case BTC_GET_U1_WIFI_CENTRAL_CHNL:
-+		*pU1Tmp = pHalData->current_channel;
-+		break;
-+
-+	case BTC_GET_U1_WIFI_HS_CHNL:
-+		*pU1Tmp = 0;
-+		ret = _FALSE;
-+		break;
-+
-+	case BTC_GET_U1_WIFI_P2P_CHNL:
-+#ifdef CONFIG_P2P
-+		{
-+			struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+			
-+			*pU1Tmp = pwdinfo->operating_channel;
-+		}
-+#else
-+		*pU1Tmp = 0;
-+#endif
-+		break;
-+
-+	case BTC_GET_U1_MAC_PHY_MODE:
-+		/*			*pU1Tmp = BTC_SMSP;
-+		 *			*pU1Tmp = BTC_DMSP;
-+		 *			*pU1Tmp = BTC_DMDP;
-+		 *			*pU1Tmp = BTC_MP_UNKNOWN; */
-+		break;
-+
-+	case BTC_GET_U1_AP_NUM:
-+		*pU1Tmp = halbtcoutsrc_GetWifiScanAPNum(padapter);
-+		break;
-+	case BTC_GET_U1_ANT_TYPE:
-+		switch (pHalData->bt_coexist.btAntisolation) {
-+		case 0:
-+			*pU1Tmp = (u8)BTC_ANT_TYPE_0;
-+			pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_0;
-+			break;
-+		case 1:
-+			*pU1Tmp = (u8)BTC_ANT_TYPE_1;
-+			pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_1;
-+			break;
-+		case 2:
-+			*pU1Tmp = (u8)BTC_ANT_TYPE_2;
-+			pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_2;
-+			break;
-+		case 3:
-+			*pU1Tmp = (u8)BTC_ANT_TYPE_3;
-+			pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_3;
-+			break;
-+		case 4:
-+			*pU1Tmp = (u8)BTC_ANT_TYPE_4;
-+			pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_4;
-+			break;
-+		}
-+		break;
-+	case BTC_GET_U1_IOT_PEER:
-+		*pU1Tmp = mlmeext->mlmext_info.assoc_AP_vendor;
-+		break;
-+
-+	/* =======1Ant=========== */
-+	case BTC_GET_U1_LPS_MODE:
-+		*pU1Tmp = padapter->dvobj->pwrctl_priv.pwr_mode;
-+		break;
-+
-+	case BTC_GET_U2_BEACON_PERIOD:
-+		*pU2Tmp = mlmeext->mlmext_info.bcn_interval;
-+		break;
-+
-+	default:
-+		ret = _FALSE;
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+u16 halbtcoutsrc_LnaConstrainLvl(void *pBtcContext, u8 *lna_constrain_level)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	u16 ret = BT_STATUS_BT_OP_SUCCESS;
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+
-+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
-+		_irqL irqL;
-+		u8 op_code;
-+
-+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+		ret = _btmpoper_cmd(pBtCoexist, BT_OP_SET_BT_LANCONSTRAIN_LEVEL, 0, lna_constrain_level, 1);
-+
-+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+	} else { 
-+		ret = BT_STATUS_NOT_IMPLEMENT;
-+		RTW_INFO("%s halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == FALSE\n", __func__);
-+	}
-+
-+	return ret;
-+}
-+
-+u8 halbtcoutsrc_SetBtGoldenRxRange(void *pBtcContext, u8 profile, u8 range_shift)
-+{
-+	/* wait for implementation if necessary */
-+
-+	return 0;
-+}
-+
-+u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	PADAPTER padapter;
-+	PHAL_DATA_TYPE pHalData;
-+	u8 *pu8;
-+	u8 *pU1Tmp;
-+	u16 *pU2Tmp;
-+	u32	*pU4Tmp;
-+	u8 ret;
-+	u8 result = _TRUE;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return _FALSE;
-+
-+	padapter = pBtCoexist->Adapter;
-+	pHalData = GET_HAL_DATA(padapter);
-+	pu8 = (u8 *)pInBuf;
-+	pU1Tmp = (u8 *)pInBuf;
-+	pU2Tmp = (u16*)pInBuf;
-+	pU4Tmp = (u32 *)pInBuf;
-+	ret = _TRUE;
-+
-+	switch (setType) {
-+	/* set some u8 type variables. */
-+	case BTC_SET_BL_BT_DISABLE:
-+		pBtCoexist->bt_info.bt_disabled = *pu8;
-+		break;
-+
-+	case BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE:
-+		pBtCoexist->bt_info.bt_enable_disable_change = *pu8;
-+		break;
-+
-+	case BTC_SET_BL_BT_TRAFFIC_BUSY:
-+		pBtCoexist->bt_info.bt_busy = *pu8;
-+		break;
-+
-+	case BTC_SET_BL_BT_LIMITED_DIG:
-+		pBtCoexist->bt_info.limited_dig = *pu8;
-+		break;
-+
-+	case BTC_SET_BL_FORCE_TO_ROAM:
-+		pBtCoexist->bt_info.force_to_roam = *pu8;
-+		break;
-+
-+	case BTC_SET_BL_TO_REJ_AP_AGG_PKT:
-+		pBtCoexist->bt_info.reject_agg_pkt = *pu8;
-+		break;
-+
-+	case BTC_SET_BL_BT_CTRL_AGG_SIZE:
-+		pBtCoexist->bt_info.bt_ctrl_agg_buf_size = *pu8;
-+		break;
-+
-+	case BTC_SET_BL_INC_SCAN_DEV_NUM:
-+		pBtCoexist->bt_info.increase_scan_dev_num = *pu8;
-+		break;
-+
-+	case BTC_SET_BL_BT_TX_RX_MASK:
-+		pBtCoexist->bt_info.bt_tx_rx_mask = *pu8;
-+		break;
-+
-+	case BTC_SET_BL_MIRACAST_PLUS_BT:
-+		pBtCoexist->bt_info.miracast_plus_bt = *pu8;
-+		break;
-+
-+	/* set some u8 type variables. */
-+	case BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON:
-+		pBtCoexist->bt_info.rssi_adjust_for_agc_table_on = *pU1Tmp;
-+		break;
-+
-+	case BTC_SET_U1_AGG_BUF_SIZE:
-+		pBtCoexist->bt_info.agg_buf_size = *pU1Tmp;
-+		break;
-+
-+	/* the following are some action which will be triggered */
-+	case BTC_SET_ACT_GET_BT_RSSI:
-+#if 0
-+		BT_SendGetBtRssiEvent(padapter);
-+#else
-+		ret = _FALSE;
-+#endif
-+		break;
-+
-+	case BTC_SET_ACT_AGGREGATE_CTRL:
-+		halbtcoutsrc_AggregationCheck(pBtCoexist);
-+		break;
-+
-+	/* =======1Ant=========== */
-+	/* set some u8 type variables. */
-+	case BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE:
-+		pBtCoexist->bt_info.rssi_adjust_for_1ant_coex_type = *pU1Tmp;
-+		break;
-+
-+	case BTC_SET_U1_LPS_VAL:
-+		pBtCoexist->bt_info.lps_val = *pU1Tmp;
-+		break;
-+
-+	case BTC_SET_U1_RPWM_VAL:
-+		pBtCoexist->bt_info.rpwm_val = *pU1Tmp;
-+		break;
-+
-+	/* the following are some action which will be triggered */
-+	case BTC_SET_ACT_LEAVE_LPS:
-+		result = halbtcoutsrc_LeaveLps(pBtCoexist);
-+		break;
-+
-+	case BTC_SET_ACT_ENTER_LPS:
-+		halbtcoutsrc_EnterLps(pBtCoexist);
-+		break;
-+
-+	case BTC_SET_ACT_NORMAL_LPS:
-+		halbtcoutsrc_NormalLps(pBtCoexist);
-+		break;
-+
-+	case BTC_SET_ACT_PRE_NORMAL_LPS:
-+		halbtcoutsrc_Pre_NormalLps(pBtCoexist);
-+		break;
-+
-+	case BTC_SET_ACT_POST_NORMAL_LPS:
-+		halbtcoutsrc_Post_NormalLps(pBtCoexist);
-+		break;
-+
-+	case BTC_SET_ACT_DISABLE_LOW_POWER:
-+		halbtcoutsrc_DisableLowPower(pBtCoexist, *pu8);
-+		break;
-+
-+	case BTC_SET_ACT_UPDATE_RAMASK:
-+		/*
-+		pBtCoexist->bt_info.ra_mask = *pU4Tmp;
-+
-+		if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+			struct sta_info *psta;
-+			PWLAN_BSSID_EX cur_network;
-+
-+			cur_network = &padapter->mlmeextpriv.mlmext_info.network;
-+			psta = rtw_get_stainfo(&padapter->stapriv, cur_network->MacAddress);
-+			rtw_hal_update_ra_mask(psta);
-+		}
-+		*/
-+		break;
-+
-+	case BTC_SET_ACT_SEND_MIMO_PS: {
-+		u8 newMimoPsMode = 3;
-+		struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+		struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+		/* *pU1Tmp = 0 use SM_PS static type */
-+		/* *pU1Tmp = 1 disable SM_PS */
-+		if (*pU1Tmp == 0)
-+			newMimoPsMode = WLAN_HT_CAP_SM_PS_STATIC;
-+		else if (*pU1Tmp == 1)
-+			newMimoPsMode = WLAN_HT_CAP_SM_PS_DISABLED;
-+
-+		if (check_fwstate(&padapter->mlmepriv , WIFI_ASOC_STATE) == _TRUE) {
-+			/* issue_action_SM_PS(padapter, get_my_bssid(&(pmlmeinfo->network)), newMimoPsMode); */
-+			issue_action_SM_PS_wait_ack(padapter , get_my_bssid(&(pmlmeinfo->network)) , newMimoPsMode, 3 , 1);
-+		}
-+	}
-+	break;
-+
-+	case BTC_SET_ACT_CTRL_BT_INFO:
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+		{
-+			u8 dataLen = *pU1Tmp;
-+			u8 tmpBuf[BTC_TMP_BUF_SHORT];
-+			if (dataLen)
-+				_rtw_memcpy(tmpBuf, pU1Tmp + 1, dataLen);
-+			BT_SendEventExtBtInfoControl(padapter, dataLen, &tmpBuf[0]);
-+		}
-+#else /* !CONFIG_BT_COEXIST_SOCKET_TRX */
-+		ret = _FALSE;
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+		break;
-+
-+	case BTC_SET_ACT_CTRL_BT_COEX:
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+		{
-+			u8 dataLen = *pU1Tmp;
-+			u8 tmpBuf[BTC_TMP_BUF_SHORT];
-+			if (dataLen)
-+				_rtw_memcpy(tmpBuf, pU1Tmp + 1, dataLen);
-+			BT_SendEventExtBtCoexControl(padapter, _FALSE, dataLen, &tmpBuf[0]);
-+		}
-+#else /* !CONFIG_BT_COEXIST_SOCKET_TRX */
-+		ret = _FALSE;
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+		break;
-+	case BTC_SET_ACT_CTRL_8723B_ANT:
-+#if 0
-+		{
-+			u8	dataLen = *pU1Tmp;
-+			u8	tmpBuf[BTC_TMP_BUF_SHORT];
-+			if (dataLen)
-+				PlatformMoveMemory(&tmpBuf[0], pU1Tmp + 1, dataLen);
-+			BT_Set8723bAnt(Adapter, dataLen, &tmpBuf[0]);
-+		}
-+#else
-+		ret = _FALSE;
-+#endif
-+		break;
-+	case BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL:
-+		halbtcoutsrc_LnaConstrainLvl(pBtCoexist, pu8);
-+		break;
-+	case BTC_SET_BL_BT_GOLDEN_RX_RANGE:
-+		halbtcoutsrc_SetBtGoldenRxRange(pBtCoexist, (*pU2Tmp & 0xff00) >> 8, (*pU2Tmp & 0xff));
-+		break;
-+	case BTC_SET_RESET_COEX_VAR:
-+		_rtw_memset(&pBtCoexist->coex_dm, 0x00, sizeof(pBtCoexist->coex_dm));
-+		_rtw_memset(&pBtCoexist->coex_sta, 0x00, sizeof(pBtCoexist->coex_sta));
-+
-+		switch(pBtCoexist->chip_type) {
-+#ifdef CONFIG_RTL8822B
-+		case BTC_CHIP_RTL8822B:
-+			_rtw_memset(&pBtCoexist->coex_dm_8822b_1ant, 0x00, sizeof(pBtCoexist->coex_dm_8822b_1ant));
-+			_rtw_memset(&pBtCoexist->coex_dm_8822b_2ant, 0x00, sizeof(pBtCoexist->coex_dm_8822b_2ant));
-+			_rtw_memset(&pBtCoexist->coex_sta_8822b_1ant, 0x00, sizeof(pBtCoexist->coex_sta_8822b_1ant));
-+			_rtw_memset(&pBtCoexist->coex_sta_8822b_2ant, 0x00, sizeof(pBtCoexist->coex_sta_8822b_2ant));
-+			break;
-+#endif
-+#ifdef CONFIG_RTL8821C
-+		case BTC_CHIP_RTL8821C:
-+			_rtw_memset(&pBtCoexist->coex_dm_8821c_1ant, 0x00, sizeof(pBtCoexist->coex_dm_8821c_1ant));
-+			_rtw_memset(&pBtCoexist->coex_dm_8821c_2ant, 0x00, sizeof(pBtCoexist->coex_dm_8821c_2ant));
-+			_rtw_memset(&pBtCoexist->coex_sta_8821c_1ant, 0x00, sizeof(pBtCoexist->coex_sta_8821c_1ant));
-+			_rtw_memset(&pBtCoexist->coex_sta_8821c_2ant, 0x00, sizeof(pBtCoexist->coex_sta_8821c_2ant));
-+			break;
-+#endif
-+#ifdef CONFIG_RTL8723D
-+		case BTC_CHIP_RTL8723D:
-+			_rtw_memset(&pBtCoexist->coex_dm_8723d_1ant, 0x00, sizeof(pBtCoexist->coex_dm_8723d_1ant));
-+			_rtw_memset(&pBtCoexist->coex_dm_8723d_2ant, 0x00, sizeof(pBtCoexist->coex_dm_8723d_2ant));
-+			_rtw_memset(&pBtCoexist->coex_sta_8723d_1ant, 0x00, sizeof(pBtCoexist->coex_sta_8723d_1ant));
-+			_rtw_memset(&pBtCoexist->coex_sta_8723d_2ant, 0x00, sizeof(pBtCoexist->coex_sta_8723d_2ant));
-+			break;
-+#endif
-+		}
-+		break;
-+	/* ===================== */
-+	default:
-+		ret = _FALSE;
-+		break;
-+	}
-+
-+	return result;
-+}
-+
-+u8 halbtcoutsrc_UnderIps(PBTC_COEXIST pBtCoexist)
-+{
-+	PADAPTER padapter;
-+	struct pwrctrl_priv *pwrpriv;
-+	u8 bMacPwrCtrlOn;
-+
-+	padapter = pBtCoexist->Adapter;
-+	pwrpriv = &padapter->dvobj->pwrctl_priv;
-+	bMacPwrCtrlOn = _FALSE;
-+
-+	if ((_TRUE == pwrpriv->bips_processing)
-+	    && (IPS_NONE != pwrpriv->ips_mode_req)
-+	   )
-+		return _TRUE;
-+
-+	if (rf_off == pwrpriv->rf_pwrstate)
-+		return _TRUE;
-+
-+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+	if (_FALSE == bMacPwrCtrlOn)
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+u8 halbtcoutsrc_UnderLps(PBTC_COEXIST pBtCoexist)
-+{
-+	return GLBtcWiFiInLPS;
-+}
-+
-+u8 halbtcoutsrc_Under32K(PBTC_COEXIST pBtCoexist)
-+{
-+	/* todo: the method to check whether wifi is under 32K or not */
-+	return _FALSE;
-+}
-+
-+void halbtcoutsrc_DisplayCoexStatistics(PBTC_COEXIST pBtCoexist)
-+{
-+#if 0
-+	PADAPTER padapter = (PADAPTER)pBtCoexist->Adapter;
-+	PBT_MGNT pBtMgnt = &padapter->MgntInfo.BtInfo.BtMgnt;
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+	u8 *cliBuf = pBtCoexist->cliBuf;
-+	u8			i, j;
-+	u8			tmpbuf[BTC_TMP_BUF_SHORT];
-+
-+
-+	if (gl_coex_offload.cnt_h2c_sent) {
-+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Coex h2c notify]============");
-+		CL_PRINTF(cliBuf);
-+
-+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = H2c(%d)/Ack(%d)", "Coex h2c/c2h overall statistics",
-+			gl_coex_offload.cnt_h2c_sent, gl_coex_offload.cnt_c2h_ack);
-+		for (j = 0; j < COL_STATUS_MAX; j++) {
-+			if (gl_coex_offload.status[j]) {
-+				CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, ", %s:%d", coexH2cResultString[j], gl_coex_offload.status[j]);
-+				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);
-+			}
-+		}
-+		CL_PRINTF(cliBuf);
-+	}
-+	for (i = 0; i < COL_OP_WIFI_OPCODE_MAX; i++) {
-+		if (gl_coex_offload.h2c_record[i].count) {
-+			/*==========================================*/
-+			/*	H2C result statistics*/
-+			/*==========================================*/
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = total:%d", coexOpcodeString[i], gl_coex_offload.h2c_record[i].count);
-+			for (j = 0; j < COL_STATUS_MAX; j++) {
-+				if (gl_coex_offload.h2c_record[i].status[j]) {
-+					CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, ", %s:%d", coexH2cResultString[j], gl_coex_offload.h2c_record[i].status[j]);
-+					CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);
-+				}
-+			}
-+			CL_PRINTF(cliBuf);
-+			/*==========================================*/
-+			/*	H2C/C2H content*/
-+			/*==========================================*/
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = ", "H2C / C2H content");
-+			for (j = 0; j < gl_coex_offload.h2c_record[i].h2c_len; j++) {
-+				CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, "%02x ", gl_coex_offload.h2c_record[i].h2c_buf[j]);
-+				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, 3);
-+			}
-+			if (gl_coex_offload.h2c_record[i].c2h_ack_len) {
-+				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, "/ ", 2);
-+				for (j = 0; j < gl_coex_offload.h2c_record[i].c2h_ack_len; j++) {
-+					CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, "%02x ", gl_coex_offload.h2c_record[i].c2h_ack_buf[j]);
-+					CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, 3);
-+				}
-+			}
-+			CL_PRINTF(cliBuf);
-+			/*==========================================*/
-+		}
-+	}
-+
-+	if (gl_coex_offload.cnt_c2h_ind) {
-+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Coex c2h indication]============");
-+		CL_PRINTF(cliBuf);
-+
-+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = Ind(%d)", "C2H indication statistics",
-+			   gl_coex_offload.cnt_c2h_ind);
-+		for (j = 0; j < COL_STATUS_MAX; j++) {
-+			if (gl_coex_offload.c2h_ind_status[j]) {
-+				CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, ", %s:%d", coexH2cResultString[j], gl_coex_offload.c2h_ind_status[j]);
-+				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);
-+			}
-+		}
-+		CL_PRINTF(cliBuf);
-+	}
-+	for (i = 0; i < COL_IND_MAX; i++) {
-+		if (gl_coex_offload.c2h_ind_record[i].count) {
-+			/*==========================================*/
-+			/*	H2C result statistics*/
-+			/*==========================================*/
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = total:%d", coexIndTypeString[i], gl_coex_offload.c2h_ind_record[i].count);
-+			for (j = 0; j < COL_STATUS_MAX; j++) {
-+				if (gl_coex_offload.c2h_ind_record[i].status[j]) {
-+					CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, ", %s:%d", coexH2cResultString[j], gl_coex_offload.c2h_ind_record[i].status[j]);
-+					CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, BTC_TMP_BUF_SHORT);
-+				}
-+			}
-+			CL_PRINTF(cliBuf);
-+			/*==========================================*/
-+			/*	content*/
-+			/*==========================================*/
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = ", "C2H indication content");
-+			for (j = 0; j < gl_coex_offload.c2h_ind_record[i].ind_len; j++) {
-+				CL_SPRINTF(tmpbuf, BTC_TMP_BUF_SHORT, "%02x ", gl_coex_offload.c2h_ind_record[i].ind_buf[j]);
-+				CL_STRNCAT(cliBuf, BT_TMP_BUF_SIZE, tmpbuf, 3);
-+			}
-+			CL_PRINTF(cliBuf);
-+			/*==========================================*/
-+		}
-+	}
-+
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Statistics]============");
-+	CL_PRINTF(cliBuf);
-+
-+#if (H2C_USE_IO_THREAD != 1)
-+	for (i = 0; i < H2C_STATUS_MAX; i++) {
-+		if (pHalData->h2cStatistics[i]) {
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s] = %d", "H2C statistics", \
-+				   h2cStaString[i], pHalData->h2cStatistics[i]);
-+			CL_PRINTF(cliBuf);
-+		}
-+	}
-+#else
-+	for (i = 0; i < IO_STATUS_MAX; i++) {
-+		if (Adapter->ioComStr.ioH2cStatistics[i]) {
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s] = %d", "H2C statistics", \
-+				ioStaString[i], Adapter->ioComStr.ioH2cStatistics[i]);
-+			CL_PRINTF(cliBuf);
-+		}
-+	}
-+#endif
-+#if 0
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "lastHMEBoxNum", \
-+		   pHalData->LastHMEBoxNum);
-+	CL_PRINTF(cliBuf);
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x / 0x%x", "LastOkH2c/FirstFailH2c(fwNotRead)", \
-+		   pHalData->lastSuccessH2cEid, pHalData->firstFailedH2cEid);
-+	CL_PRINTF(cliBuf);
-+
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "c2hIsr/c2hIntr/clr1AF/noRdy/noBuf", \
-+		pHalData->InterruptLog.nIMR_C2HCMD, DBG_Var.c2hInterruptCnt, DBG_Var.c2hClrReadC2hCnt,
-+		   DBG_Var.c2hNotReadyCnt, DBG_Var.c2hBufAlloFailCnt);
-+	CL_PRINTF(cliBuf);
-+
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "c2hPacket", \
-+		   DBG_Var.c2hPacketCnt);
-+	CL_PRINTF(cliBuf);
-+#endif
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "Periodical/ DbgCtrl", \
-+		pBtCoexist->statistics.cntPeriodical, pBtCoexist->statistics.cntDbgCtrl);
-+	CL_PRINTF(cliBuf);
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "PowerOn/InitHw/InitCoexDm/RfStatus", \
-+		pBtCoexist->statistics.cntPowerOn, pBtCoexist->statistics.cntInitHwConfig, pBtCoexist->statistics.cntInitCoexDm,
-+		   pBtCoexist->statistics.cntRfStatusNotify);
-+	CL_PRINTF(cliBuf);
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "Ips/Lps/Scan/Connect/Mstatus", \
-+		pBtCoexist->statistics.cntIpsNotify, pBtCoexist->statistics.cntLpsNotify,
-+		pBtCoexist->statistics.cntScanNotify, pBtCoexist->statistics.cntConnectNotify,
-+		   pBtCoexist->statistics.cntMediaStatusNotify);
-+	CL_PRINTF(cliBuf);
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "Special pkt/Bt info/ bind",
-+		pBtCoexist->statistics.cntSpecialPacketNotify, pBtCoexist->statistics.cntBtInfoNotify,
-+		   pBtCoexist->statistics.cntBind);
-+	CL_PRINTF(cliBuf);
-+#endif
-+	PADAPTER		padapter = pBtCoexist->Adapter;
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	u8				*cliBuf = pBtCoexist->cli_buf;
-+
-+	if (pHalData->EEPROMBluetoothCoexist == 1) {
-+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Coex Status]============");
-+		CL_PRINTF(cliBuf);
-+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IsBtDisabled", rtw_btcoex_IsBtDisabled(padapter));
-+		CL_PRINTF(cliBuf);
-+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IsBtControlLps", rtw_btcoex_IsBtControlLps(padapter));
-+		CL_PRINTF(cliBuf);
-+	}
-+}
-+
-+void halbtcoutsrc_DisplayBtLinkInfo(PBTC_COEXIST pBtCoexist)
-+{
-+#if 0
-+	PADAPTER padapter = (PADAPTER)pBtCoexist->Adapter;
-+	PBT_MGNT pBtMgnt = &padapter->MgntInfo.BtInfo.BtMgnt;
-+	u8 *cliBuf = pBtCoexist->cliBuf;
-+	u8 i;
-+
-+
-+	if (pBtCoexist->stack_info.profile_notified) {
-+		for (i = 0; i < pBtMgnt->ExtConfig.NumberOfACL; i++) {
-+			if (pBtMgnt->ExtConfig.HCIExtensionVer >= 1) {
-+				CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", "Bt link type/spec/role", \
-+					BtProfileString[pBtMgnt->ExtConfig.aclLink[i].BTProfile],
-+					BtSpecString[pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec],
-+					BtLinkRoleString[pBtMgnt->ExtConfig.aclLink[i].linkRole]);
-+				CL_PRINTF(cliBuf);
-+			} else {
-+				CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", "Bt link type/spec", \
-+					BtProfileString[pBtMgnt->ExtConfig.aclLink[i].BTProfile],
-+					BtSpecString[pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec]);
-+				CL_PRINTF(cliBuf);
-+			}
-+		}
-+	}
-+#endif
-+}
-+
-+void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist)
-+{
-+	PADAPTER	padapter = pBtCoexist->Adapter;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	u8			*cliBuf = pBtCoexist->cli_buf;
-+	s32			wifiRssi = 0, btHsRssi = 0;
-+	BOOLEAN	bScan = _FALSE, bLink = _FALSE, bRoam = _FALSE, bWifiBusy = _FALSE, bWifiUnderBMode = _FALSE;
-+	u32			wifiBw = BTC_WIFI_BW_HT20, wifiTrafficDir = BTC_WIFI_TRAFFIC_TX, wifiFreq = BTC_FREQ_2_4G;
-+	u32			wifiLinkStatus = 0x0;
-+	BOOLEAN	bBtHsOn = _FALSE, bLowPower = _FALSE;
-+	u8			wifiChnl = 0, wifiP2PChnl = 0, nScanAPNum = 0, FwPSState;
-+	u32			iqk_cnt_total = 0, iqk_cnt_ok = 0, iqk_cnt_fail = 0;
-+	u16			wifiBcnInterval = 0;
-+	PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
-+	struct btc_wifi_link_info wifi_link_info;
-+
-+	wifi_link_info = halbtcoutsrc_getwifilinkinfo(pBtCoexist);
-+
-+	switch (wifi_link_info.link_mode) {
-+		case BTC_LINK_NONE:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"None", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
-+			break;
-+		case BTC_LINK_ONLY_GO:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"ONLY_GO", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
-+			break;
-+		case BTC_LINK_ONLY_GC:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"ONLY_GC", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
-+			break;
-+		case BTC_LINK_ONLY_STA:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"ONLY_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
-+			break;
-+		case BTC_LINK_ONLY_AP:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"ONLY_AP", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
-+			break;
-+		case BTC_LINK_2G_MCC_GO_STA:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"24G_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = BTC_FREQ_2_4G;
-+			break;
-+		case BTC_LINK_5G_MCC_GO_STA:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"5G_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = BTC_FREQ_5G;
-+			break;
-+		case BTC_LINK_25G_MCC_GO_STA:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"2BANDS_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = BTC_FREQ_25G;
-+			break;
-+		case BTC_LINK_2G_MCC_GC_STA:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"24G_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = BTC_FREQ_2_4G;
-+			break;
-+		case BTC_LINK_5G_MCC_GC_STA:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"5G_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = BTC_FREQ_5G;
-+			break;
-+		case BTC_LINK_25G_MCC_GC_STA:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"2BANDS_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = BTC_FREQ_25G;
-+			break;
-+		case BTC_LINK_2G_SCC_GO_STA:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"24G_SCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = BTC_FREQ_2_4G;
-+			break;
-+		case BTC_LINK_5G_SCC_GO_STA:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"5G_SCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = BTC_FREQ_5G;
-+			break;
-+		case BTC_LINK_2G_SCC_GC_STA:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"24G_SCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = BTC_FREQ_2_4G;
-+			break;
-+		case BTC_LINK_5G_SCC_GC_STA:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"5G_SCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = BTC_FREQ_5G;
-+			break;
-+		default:
-+			CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin",
-+					"UNKNOWN", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go);
-+			wifiFreq = hal->current_channel > 14 ?  BTC_FREQ_5G : BTC_FREQ_2_4G;
-+			break;
-+	}
-+
-+	CL_PRINTF(cliBuf);
-+
-+	wifiLinkStatus = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist);
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "STA/vWifi/HS/p2pGo/p2pGc",
-+		((wifiLinkStatus & WIFI_STA_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_AP_CONNECTED) ? 1 : 0),
-+		((wifiLinkStatus & WIFI_HS_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_P2P_GO_CONNECTED) ? 1 : 0),
-+		((wifiLinkStatus & WIFI_P2P_GC_CONNECTED) ? 1 : 0));
-+	CL_PRINTF(cliBuf);
-+
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Link/ Roam/ Scan",
-+		bLink, bRoam, bScan);
-+	CL_PRINTF(cliBuf);
-+
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_TOTAL, &iqk_cnt_total);
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_OK, &iqk_cnt_ok);
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_FAIL, &iqk_cnt_fail);
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d %s %s",
-+		"IQK All/ OK/ Fail/AutoLoad/FWDL", iqk_cnt_total, iqk_cnt_ok, iqk_cnt_fail,
-+		((halbtcoutsrc_is_autoload_fail(pBtCoexist) == _TRUE) ? "fail":"ok"), ((halbtcoutsrc_is_fw_ready(pBtCoexist) == _TRUE) ? "ok":"fail"));
-+	CL_PRINTF(cliBuf);
-+
-+	if (wifiLinkStatus & WIFI_STA_CONNECTED) {
-+		CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ "MAC_FMT"", "IOT Peer/BSSID", GLBtcIotPeerString[padapter->mlmeextpriv.mlmext_info.assoc_AP_vendor], MAC_ARG(get_bssid(&padapter->mlmepriv)));
-+		CL_PRINTF(cliBuf);
-+	}
-+
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U2_BEACON_PERIOD, &wifiBcnInterval);
-+	wifiChnl = wifi_link_info.sta_center_channel;
-+	wifiP2PChnl = wifi_link_info.p2p_center_channel;
-+
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dBm/ %d/ %d/ %d", "RSSI/ STA_Chnl/ P2P_Chnl/ BI",
-+		wifiRssi-100, wifiChnl, wifiP2PChnl, wifiBcnInterval);
-+	CL_PRINTF(cliBuf);
-+
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode);
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_AP_NUM, &nScanAPNum);
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s/ %d ", "Band/ BW/ Traffic/ APCnt",
-+		GLBtcWifiFreqString[wifiFreq], ((bWifiUnderBMode) ? "11b" : GLBtcWifiBwString[wifiBw]),
-+		((!bWifiBusy) ? "idle" : ((BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) ? "uplink" : "downlink")),
-+		   nScanAPNum);
-+	CL_PRINTF(cliBuf);
-+
-+	/* power status */
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s%s%s", "Power Status", \
-+		((halbtcoutsrc_UnderIps(pBtCoexist) == _TRUE) ? "IPS ON" : "IPS OFF"),
-+		((halbtcoutsrc_UnderLps(pBtCoexist) == _TRUE) ? ", LPS ON" : ", LPS OFF"),
-+		((halbtcoutsrc_Under32K(pBtCoexist) == _TRUE) ? ", 32k" : ""));
-+	CL_PRINTF(cliBuf);
-+
-+	CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x (0x%x/0x%x)", "Power mode cmd(lps/rpwm)",
-+		   pBtCoexist->pwrModeVal[0], pBtCoexist->pwrModeVal[1],
-+		   pBtCoexist->pwrModeVal[2], pBtCoexist->pwrModeVal[3],
-+		   pBtCoexist->pwrModeVal[4], pBtCoexist->pwrModeVal[5],
-+		   pBtCoexist->bt_info.lps_val,
-+		   pBtCoexist->bt_info.rpwm_val);
-+	CL_PRINTF(cliBuf);
-+}
-+
-+void halbtcoutsrc_DisplayDbgMsg(void *pBtcContext, u8 dispType)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	switch (dispType) {
-+	case BTC_DBG_DISP_COEX_STATISTICS:
-+		halbtcoutsrc_DisplayCoexStatistics(pBtCoexist);
-+		break;
-+	case BTC_DBG_DISP_BT_LINK_INFO:
-+		halbtcoutsrc_DisplayBtLinkInfo(pBtCoexist);
-+		break;
-+	case BTC_DBG_DISP_WIFI_STATUS:
-+		halbtcoutsrc_DisplayWifiStatus(pBtCoexist);
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+/* ************************************
-+ *		IO related function
-+ * ************************************ */
-+u8 halbtcoutsrc_Read1Byte(void *pBtcContext, u32 RegAddr)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	PADAPTER padapter;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	padapter = pBtCoexist->Adapter;
-+
-+	return rtw_read8(padapter, RegAddr);
-+}
-+
-+u16 halbtcoutsrc_Read2Byte(void *pBtcContext, u32 RegAddr)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	PADAPTER padapter;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	padapter = pBtCoexist->Adapter;
-+
-+	return	rtw_read16(padapter, RegAddr);
-+}
-+
-+u32 halbtcoutsrc_Read4Byte(void *pBtcContext, u32 RegAddr)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	PADAPTER padapter;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	padapter = pBtCoexist->Adapter;
-+
-+	return	rtw_read32(padapter, RegAddr);
-+}
-+
-+void halbtcoutsrc_Write1Byte(void *pBtcContext, u32 RegAddr, u8 Data)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	PADAPTER padapter;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	padapter = pBtCoexist->Adapter;
-+
-+	rtw_write8(padapter, RegAddr, Data);
-+}
-+
-+void halbtcoutsrc_BitMaskWrite1Byte(void *pBtcContext, u32 regAddr, u8 bitMask, u8 data1b)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	PADAPTER padapter;
-+	u8 originalValue, bitShift;
-+	u8 i;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	padapter = pBtCoexist->Adapter;
-+	originalValue = 0;
-+	bitShift = 0;
-+
-+	if (bitMask != 0xff) {
-+		originalValue = rtw_read8(padapter, regAddr);
-+
-+		for (i = 0; i <= 7; i++) {
-+			if ((bitMask >> i) & 0x1)
-+				break;
-+		}
-+		bitShift = i;
-+
-+		data1b = (originalValue & ~bitMask) | ((data1b << bitShift) & bitMask);
-+	}
-+
-+	rtw_write8(padapter, regAddr, data1b);
-+}
-+
-+void halbtcoutsrc_Write2Byte(void *pBtcContext, u32 RegAddr, u16 Data)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	PADAPTER padapter;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	padapter = pBtCoexist->Adapter;
-+
-+	rtw_write16(padapter, RegAddr, Data);
-+}
-+
-+void halbtcoutsrc_Write4Byte(void *pBtcContext, u32 RegAddr, u32 Data)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	PADAPTER padapter;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	padapter = pBtCoexist->Adapter;
-+
-+	rtw_write32(padapter, RegAddr, Data);
-+}
-+
-+void halbtcoutsrc_WriteLocalReg1Byte(void *pBtcContext, u32 RegAddr, u8 Data)
-+{
-+	PBTC_COEXIST		pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	PADAPTER			Adapter = pBtCoexist->Adapter;
-+
-+	if (BTC_INTF_SDIO == pBtCoexist->chip_interface)
-+		rtw_write8(Adapter, SDIO_LOCAL_BASE | RegAddr, Data);
-+	else
-+		rtw_write8(Adapter, RegAddr, Data);
-+}
-+
-+u32 halbtcoutsrc_WaitLIndirectReg_Ready(void *pBtcContext)
-+{
-+	PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
-+	u32 delay_count = 0, reg = 0;
-+
-+	if (!btc->chip_para->lte_indirect_access)
-+		return 0;
-+
-+	switch (btc->chip_para->indirect_type) {
-+	case BTC_INDIRECT_1700:
-+		reg = 0x1703;
-+		break;
-+	case BTC_INDIRECT_7C0:
-+		reg = 0x7C3;
-+		break;
-+	default:
-+		return 0;
-+	}
-+
-+	/* wait for ready bit before access */
-+	while (1) {
-+		if ((halbtcoutsrc_Read1Byte(btc, reg) & BIT(5)) == 0) {
-+			rtw_mdelay_os(10);
-+			if (++delay_count >= 10)
-+				break;
-+		} else {
-+			break;
-+		}
-+	}
-+
-+	return delay_count;
-+}
-+
-+u32 halbtcoutsrc_ReadLIndirectReg(void *pBtcContext, u16 reg_addr)
-+{
-+	PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
-+	u32 val = 0;
-+
-+	if (!btc->chip_para->lte_indirect_access)
-+		return 0;
-+
-+	/* wait for ready bit before access */
-+	halbtcoutsrc_WaitLIndirectReg_Ready(btc);
-+
-+	switch (btc->chip_para->indirect_type) {
-+	case BTC_INDIRECT_1700:
-+		halbtcoutsrc_Write4Byte(btc, 0x1700, 0x800F0000 | reg_addr);
-+		val = halbtcoutsrc_Read4Byte(btc, 0x1708); /* get read data */
-+		break;
-+	case BTC_INDIRECT_7C0:
-+		halbtcoutsrc_Write4Byte(btc, 0x7c0, 0x800F0000 | reg_addr);
-+		val = halbtcoutsrc_Read4Byte(btc, 0x7c8); /* get read data */
-+		break;
-+	}
-+
-+	return val;
-+}
-+
-+void halbtcoutsrc_WriteLIndirectReg(void *pBtcContext, u16 reg_addr, u32 bit_mask, u32 reg_value)
-+{
-+	PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
-+	u32 val, i = 0, bitpos = 0, reg0, reg1;
-+
-+	if (!btc->chip_para->lte_indirect_access)
-+		return;
-+
-+	if (bit_mask == 0x0)
-+		return;
-+
-+	switch (btc->chip_para->indirect_type) {
-+	case BTC_INDIRECT_1700:
-+		reg0 = 0x1700;
-+		reg1 = 0x1704;
-+		break;
-+	case BTC_INDIRECT_7C0:
-+		reg0 = 0x7C0;
-+		reg1 = 0x7C4;
-+		break;
-+	default:
-+		return;
-+	}
-+
-+	if (bit_mask == 0xffffffff) {
-+		/* wait for ready bit before access 0x1700 */
-+		halbtcoutsrc_WaitLIndirectReg_Ready(btc);
-+
-+		/* put write data */
-+		halbtcoutsrc_Write4Byte(btc, reg1, reg_value);
-+		halbtcoutsrc_Write4Byte(btc, reg0, 0xc00F0000 | reg_addr);
-+	} else {
-+		for (i = 0; i <= 31; i++) {
-+			if (((bit_mask >> i) & 0x1) == 0x1) {
-+				bitpos = i;
-+				break;
-+			}
-+		}
-+
-+		/* read back register value before write */
-+		val = halbtcoutsrc_ReadLIndirectReg(btc, reg_addr);
-+		val = (val & (~bit_mask)) | (reg_value << bitpos);
-+
-+		/* wait for ready bit before access 0x1700 */
-+		halbtcoutsrc_WaitLIndirectReg_Ready(btc);
-+
-+		halbtcoutsrc_Write4Byte(btc, reg1, val); /* put write data */
-+		halbtcoutsrc_Write4Byte(btc, reg0, 0xc00F0000 | reg_addr);
-+	}
-+}
-+
-+u16 halbtcoutsrc_Read_scbd(void *pBtcContext, u16* score_board_val)
-+{
-+	PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
-+	struct btc_coex_sta *coex_sta = &btc->coex_sta;
-+	const struct btc_chip_para *chip_para = btc->chip_para;
-+
-+	if (!chip_para->scbd_support)
-+		return 0;
-+
-+	*score_board_val = (btc->btc_read_2byte(btc, chip_para->scbd_reg))
-+								& 0x7fff;
-+	coex_sta->score_board_BW = *score_board_val;
-+
-+	return coex_sta->score_board_BW;
-+}
-+
-+u32 halbtcoutsrc_Read_scbd_32bit(void *pBtcContext, u32* score_board_val)
-+{
-+	PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
-+	struct btc_coex_sta *coex_sta = &btc->coex_sta;
-+	const struct btc_chip_para *chip_para = btc->chip_para;
-+
-+	if (!chip_para->scbd_support)
-+		return 0;
-+
-+	*score_board_val = (btc->btc_read_4byte(btc, chip_para->scbd_reg))
-+								& 0x7fffffff;
-+	coex_sta->score_board_BW_32bit = *score_board_val;
-+
-+	return coex_sta->score_board_BW_32bit;
-+}
-+
-+void halbtcoutsrc_Write_scbd(void *pBtcContext, u16 bitpos, u8 state)
-+{
-+	PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
-+	struct btc_coex_sta *coex_sta = &btc->coex_sta;
-+	const struct btc_chip_para *chip_para = btc->chip_para;
-+	u16 val = 0x2;
-+
-+	if (!chip_para->scbd_support)
-+		return;
-+
-+	val = val | coex_sta->score_board_WB;
-+
-+	/* for 8822b, Scoreboard[10]: 0: CQDDR off, 1: CQDDR on
-+	 * for 8822c, Scoreboard[10]: 0: CQDDR on, 1:CQDDR fix 2M
-+	 */
-+	if (!btc->chip_para->new_scbd10_def && (bitpos & BTC_SCBD_FIX2M)) {
-+		if (state)
-+			val = val & (~BTC_SCBD_FIX2M);
-+		else
-+			val = val | BTC_SCBD_FIX2M;
-+	} else {
-+		if (state)
-+			val = val | bitpos;
-+		else
-+			val = val & (~bitpos);
-+	}
-+
-+	if (val != coex_sta->score_board_WB) {
-+		coex_sta->score_board_WB = val;
-+		val = val | 0x8000;
-+
-+		btc->btc_write_2byte(btc, chip_para->scbd_reg, val);
-+
-+		RTW_DBG("[BTC], write scoreboard 0x%x\n", val);
-+	} else {
-+		RTW_DBG("[BTC], return for nochange\n");
-+	}
-+}
-+
-+void halbtcoutsrc_Write_scbd_32bit(void *pBtcContext, u32 bitpos, u8 state)
-+{
-+	PBTC_COEXIST btc = (PBTC_COEXIST)pBtcContext;
-+	struct btc_coex_sta *coex_sta = &btc->coex_sta;
-+	const struct btc_chip_para *chip_para = btc->chip_para;
-+	u32 val = 0x2;
-+
-+	if (!chip_para->scbd_support)
-+		return;
-+
-+	val = val | coex_sta->score_board_WB;
-+
-+	/* for 8822b, Scoreboard[10]: 0: CQDDR off, 1: CQDDR on
-+	 * for 8822c, Scoreboard[10]: 0: CQDDR on, 1:CQDDR fix 2M
-+	 */
-+	if (!btc->chip_para->new_scbd10_def && (bitpos & BTC_SCBD_FIX2M)) {
-+		if (state)
-+			val = val & (~BTC_SCBD_FIX2M);
-+		else
-+			val = val | BTC_SCBD_FIX2M;
-+	} else {
-+		if (state)
-+			val = val | bitpos;
-+		else
-+			val = val & (~bitpos);
-+	}
-+
-+	if (val != coex_sta->score_board_WB_32bit) {
-+		coex_sta->score_board_WB_32bit = val;
-+		val = val | 0x80000000;
-+
-+		btc->btc_write_4byte(btc, chip_para->scbd_reg, val);
-+
-+		RTW_DBG("[BTC], write scoreboard 0x%x\n", val);
-+	} else {
-+		RTW_DBG("[BTC], return for nochange\n");
-+	}
-+}
-+
-+void halbtcoutsrc_SetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask, u32 Data)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	PADAPTER padapter;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	padapter = pBtCoexist->Adapter;
-+
-+	phy_set_bb_reg(padapter, RegAddr, BitMask, Data);
-+}
-+
-+
-+u32 halbtcoutsrc_GetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	PADAPTER padapter;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	padapter = pBtCoexist->Adapter;
-+
-+	return phy_query_bb_reg(padapter, RegAddr, BitMask);
-+}
-+
-+void halbtcoutsrc_SetRfReg(void *pBtcContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	PADAPTER padapter;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	padapter = pBtCoexist->Adapter;
-+
-+	phy_set_rf_reg(padapter, eRFPath, RegAddr, BitMask, Data);
-+}
-+
-+u32 halbtcoutsrc_GetRfReg(void *pBtcContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	PADAPTER padapter;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	padapter = pBtCoexist->Adapter;
-+
-+	return phy_query_rf_reg(padapter, eRFPath, RegAddr, BitMask);
-+}
-+
-+u16 halbtcoutsrc_SetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr, u32 Data)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	u16 ret = BT_STATUS_BT_OP_SUCCESS;
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+
-+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
-+		u8 buf[3] = {0};
-+		_irqL irqL;
-+		u8 op_code;
-+		u8 status;
-+
-+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+		Data = cpu_to_le32(Data);
-+		op_code = BT_OP_WRITE_REG_VALUE;
-+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, (u8 *)&Data, 3);
-+		if (status != BT_STATUS_BT_OP_SUCCESS)
-+			ret = SET_BT_MP_OPER_RET(op_code, status);
-+		else {
-+			buf[0] = RegType;
-+			*(u16 *)(buf + 1) = cpu_to_le16((u16)RegAddr);
-+			op_code = BT_OP_WRITE_REG_ADDR;
-+			status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 3);
-+			if (status != BT_STATUS_BT_OP_SUCCESS)
-+				ret = SET_BT_MP_OPER_RET(op_code, status);
-+		}
-+
-+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+	} else
-+		ret = BT_STATUS_NOT_IMPLEMENT;
-+
-+	return ret;
-+}
-+
-+u8 halbtcoutsrc_SetBtAntDetection(void *pBtcContext, u8 txTime, u8 btChnl)
-+{
-+	/* Always return _FALSE since we don't implement this yet */
-+#if 0
-+	PBTC_COEXIST		pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	PADAPTER			Adapter = pBtCoexist->Adapter;
-+	u8				btCanTx = 0;
-+	BOOLEAN			bStatus = FALSE;
-+
-+	bStatus = NDBG_SetBtAntDetection(Adapter, txTime, btChnl, &btCanTx);
-+	if (bStatus && btCanTx)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+#else
-+	return _FALSE;
-+#endif
-+}
-+
-+u8 halbtcoutsrc_SetBtTRXMASK(void *pBtcContext, u8 bt_trx_mask)
-+{
-+	PBTC_COEXIST 	pBtCoexist;
-+	u8			bStatus = _FALSE;
-+	u8			btCanTx = 0;
-+	u16 		ret = BT_STATUS_BT_OP_SUCCESS;
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+
-+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter) || IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)
-+			|| IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+
-+		if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
-+			u8 buf[3] = {0};
-+			u8 len = 0;
-+			_irqL irqL;
-+			u8 op_code;
-+			u8 status;
-+
-+			if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+				buf[0] = bt_trx_mask;
-+				len = 1;
-+			} else {
-+				buf[0] = (bt_trx_mask & 0x80) >> 7;
-+				buf[1] = bt_trx_mask & 0x7f;
-+				len = 2;
-+			}
-+
-+			_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+			op_code = BT_OP_SET_BT_TRX_MASK;
-+			status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, len);
-+			if (status != BT_STATUS_BT_OP_SUCCESS)
-+				ret = SET_BT_MP_OPER_RET(op_code, status);
-+
-+			_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+		} else
-+			ret = BT_STATUS_NOT_IMPLEMENT;
-+	}
-+
-+	if (ret == BT_STATUS_BT_OP_SUCCESS)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+u16 halbtcoutsrc_GetBtReg_with_status(void *pBtcContext, u8 RegType, u32 RegAddr, u32 *data)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	u16 ret = BT_STATUS_BT_OP_SUCCESS;
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+
-+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
-+		u8 buf[3] = {0};
-+		_irqL irqL;
-+		u8 op_code;
-+		u8 status;
-+
-+		buf[0] = RegType;
-+		*(u16 *)(buf + 1) = cpu_to_le16((u16)RegAddr);
-+
-+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+		op_code = BT_OP_READ_REG;
-+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 3);
-+		if (status == BT_STATUS_BT_OP_SUCCESS)
-+			*data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
-+		else
-+			ret = SET_BT_MP_OPER_RET(op_code, status);
-+
-+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+	} else
-+		ret = BT_STATUS_NOT_IMPLEMENT;
-+
-+	return ret;
-+}
-+
-+u32 halbtcoutsrc_GetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr)
-+{
-+	u32 regVal;
-+	
-+	return (BT_STATUS_BT_OP_SUCCESS == halbtcoutsrc_GetBtReg_with_status(pBtcContext, RegType, RegAddr, &regVal)) ? regVal : 0xffffffff;
-+}
-+
-+u16 halbtcoutsrc_setbttestmode(void *pBtcContext, u8 Type)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	u16 ret = BT_STATUS_BT_OP_SUCCESS;
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+
-+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
-+		_irqL irqL;
-+		u8 op_code;
-+		u8 status;
-+
-+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+		Type = cpu_to_le32(Type);
-+		op_code = BT_OP_SET_BT_TEST_MODE_VAL;
-+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, (u8 *)&Type, 3);
-+		if (status != BT_STATUS_BT_OP_SUCCESS)
-+			ret = SET_BT_MP_OPER_RET(op_code, status);
-+
-+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+	} else
-+		ret = BT_STATUS_NOT_IMPLEMENT;
-+
-+	return ret;
-+
-+}
-+
-+
-+void halbtcoutsrc_FillH2cCmd(void *pBtcContext, u8 elementId, u32 cmdLen, u8 *pCmdBuffer)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	PADAPTER padapter;
-+	s32 ret = 0;
-+
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+	padapter = pBtCoexist->Adapter;
-+
-+	ret = rtw_hal_fill_h2c_cmd(padapter, elementId, cmdLen, pCmdBuffer);
-+
-+#ifdef CONFIG_RTL8192F
-+	if (ret == _SUCCESS) {
-+		switch (elementId) {
-+		case H2C_BT_INFO:
-+		case H2C_BT_IGNORE_WLANACT:
-+		case H2C_WL_OPMODE:
-+		case H2C_BT_MP_OPER:
-+		case H2C_BT_CONTROL:
-+			rtw_msleep_os(20);
-+			break;
-+		}
-+	}
-+#endif
-+}
-+
-+static void halbtcoutsrc_coex_offload_init(void)
-+{
-+	u8	i;
-+
-+	gl_coex_offload.h2c_req_num = 0;
-+	gl_coex_offload.cnt_h2c_sent = 0;
-+	gl_coex_offload.cnt_c2h_ack = 0;
-+	gl_coex_offload.cnt_c2h_ind = 0;
-+
-+	for (i = 0; i < COL_MAX_H2C_REQ_NUM; i++)
-+		init_completion(&gl_coex_offload.c2h_event[i]);
-+}
-+
-+static COL_H2C_STATUS halbtcoutsrc_send_h2c(PADAPTER Adapter, PCOL_H2C pcol_h2c, u16 h2c_cmd_len)
-+{
-+	COL_H2C_STATUS		h2c_status = COL_STATUS_C2H_OK;
-+	u8				i;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))
-+	reinit_completion(&gl_coex_offload.c2h_event[pcol_h2c->req_num]);		/* set event to un signaled state */
-+#else
-+	INIT_COMPLETION(gl_coex_offload.c2h_event[pcol_h2c->req_num]);
-+#endif
-+
-+	if (TRUE) {
-+#if 0	/*(USE_HAL_MAC_API == 1) */
-+		if (RT_STATUS_SUCCESS == HAL_MAC_Send_BT_COEX(&GET_HAL_MAC_INFO(Adapter), (u8 *)(pcol_h2c), (u32)h2c_cmd_len, 1)) {
-+			if (!wait_for_completion_timeout(&gl_coex_offload.c2h_event[pcol_h2c->req_num], 20)) {
-+				h2c_status = COL_STATUS_H2C_TIMTOUT;
-+			}
-+		} else {
-+			h2c_status = COL_STATUS_H2C_HALMAC_FAIL;
-+		}
-+#endif
-+	}
-+
-+	return h2c_status;
-+}
-+
-+static COL_H2C_STATUS halbtcoutsrc_check_c2h_ack(PADAPTER Adapter, PCOL_SINGLE_H2C_RECORD pH2cRecord)
-+{
-+	COL_H2C_STATUS	c2h_status = COL_STATUS_C2H_OK;
-+	PCOL_H2C		p_h2c_cmd = (PCOL_H2C)&pH2cRecord->h2c_buf[0];
-+	u8			req_num = p_h2c_cmd->req_num;
-+	PCOL_C2H_ACK	p_c2h_ack = (PCOL_C2H_ACK)&gl_coex_offload.c2h_ack_buf[req_num];
-+
-+
-+	if ((COL_C2H_ACK_HDR_LEN + p_c2h_ack->ret_len) > gl_coex_offload.c2h_ack_len[req_num]) {
-+		c2h_status = COL_STATUS_COEX_DATA_OVERFLOW;
-+		return c2h_status;
-+	}
-+	/* else */
-+	{
-+		_rtw_memmove(&pH2cRecord->c2h_ack_buf[0], &gl_coex_offload.c2h_ack_buf[req_num], gl_coex_offload.c2h_ack_len[req_num]);
-+		pH2cRecord->c2h_ack_len = gl_coex_offload.c2h_ack_len[req_num];
-+	}
-+
-+
-+	if (p_c2h_ack->req_num != p_h2c_cmd->req_num) {
-+		c2h_status = COL_STATUS_C2H_REQ_NUM_MISMATCH;
-+	} else if (p_c2h_ack->opcode_ver != p_h2c_cmd->opcode_ver) {
-+		c2h_status = COL_STATUS_C2H_OPCODE_VER_MISMATCH;
-+	} else {
-+		c2h_status = p_c2h_ack->status;
-+	}
-+
-+	return c2h_status;
-+}
-+
-+COL_H2C_STATUS halbtcoutsrc_CoexH2cProcess(void *pBtCoexist,
-+		u8 opcode, u8 opcode_ver, u8 *ph2c_par, u8 h2c_par_len)
-+{
-+	PADAPTER			Adapter = ((struct btc_coexist *)pBtCoexist)->Adapter;
-+	u8				H2C_Parameter[BTC_TMP_BUF_SHORT] = {0};
-+	PCOL_H2C			pcol_h2c = (PCOL_H2C)&H2C_Parameter[0];
-+	u16				paraLen = 0;
-+	COL_H2C_STATUS		h2c_status = COL_STATUS_C2H_OK, c2h_status = COL_STATUS_C2H_OK;
-+	COL_H2C_STATUS		ret_status = COL_STATUS_C2H_OK;
-+	u16				i, col_h2c_len = 0;
-+
-+	pcol_h2c->opcode = opcode;
-+	pcol_h2c->opcode_ver = opcode_ver;
-+	pcol_h2c->req_num = gl_coex_offload.h2c_req_num;
-+	gl_coex_offload.h2c_req_num++;
-+	gl_coex_offload.h2c_req_num %= 16;
-+
-+	_rtw_memmove(&pcol_h2c->buf[0], ph2c_par, h2c_par_len);
-+
-+
-+	col_h2c_len = h2c_par_len + 2;	/* 2=sizeof(OPCode, OPCode_version and  Request number) */
-+	BT_PrintData(Adapter, "[COL], H2C cmd: ", col_h2c_len, H2C_Parameter);
-+
-+	gl_coex_offload.cnt_h2c_sent++;
-+
-+	gl_coex_offload.h2c_record[opcode].count++;
-+	gl_coex_offload.h2c_record[opcode].h2c_len = col_h2c_len;
-+	_rtw_memmove((void *)&gl_coex_offload.h2c_record[opcode].h2c_buf[0], (void *)pcol_h2c, col_h2c_len);
-+
-+	h2c_status = halbtcoutsrc_send_h2c(Adapter, pcol_h2c, col_h2c_len);
-+
-+	gl_coex_offload.h2c_record[opcode].c2h_ack_len = 0;
-+
-+	if (COL_STATUS_C2H_OK == h2c_status) {
-+		/* if reach here, it means H2C get the correct c2h response, */
-+		c2h_status = halbtcoutsrc_check_c2h_ack(Adapter, &gl_coex_offload.h2c_record[opcode]);
-+		ret_status = c2h_status;
-+	} else {
-+		/* check h2c status error, return error status code to upper layer. */
-+		ret_status = h2c_status;
-+	}
-+	gl_coex_offload.h2c_record[opcode].status[ret_status]++;
-+	gl_coex_offload.status[ret_status]++;
-+
-+	return ret_status;
-+}
-+
-+u8 halbtcoutsrc_GetAntDetValFromBt(void *pBtcContext)
-+{
-+	/* Always return 0 since we don't implement this yet */
-+#if 0
-+	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
-+	PADAPTER			Adapter = pBtCoexist->Adapter;
-+	u8				AntDetVal = 0x0;
-+	u8				opcodeVer = 1;
-+	BOOLEAN				status = false;
-+
-+	status = NDBG_GetAntDetValFromBt(Adapter, opcodeVer, &AntDetVal);
-+
-+	RT_TRACE(COMP_DBG, DBG_LOUD, ("$$$ halbtcoutsrc_GetAntDetValFromBt(): status = %d, feature = %x\n", status, AntDetVal));
-+
-+	return AntDetVal;
-+#else
-+	return 0;
-+#endif
-+}
-+
-+u8 halbtcoutsrc_GetBleScanTypeFromBt(void *pBtcContext)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	u32 ret = BT_STATUS_BT_OP_SUCCESS;
-+	u8 data = 0;
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+
-+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
-+		u8 buf[3] = {0};
-+		_irqL irqL;
-+		u8 op_code;
-+		u8 status;
-+
-+
-+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+		op_code = BT_OP_GET_BT_BLE_SCAN_TYPE;
-+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
-+		if (status == BT_STATUS_BT_OP_SUCCESS)
-+			data = *(u8 *)GLBtcBtMpRptRsp;
-+		else
-+			ret = SET_BT_MP_OPER_RET(op_code, status);
-+
-+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+	} else
-+		ret = BT_STATUS_NOT_IMPLEMENT;
-+
-+	return data;
-+}
-+
-+u32 halbtcoutsrc_GetBleScanParaFromBt(void *pBtcContext, u8 scanType)
-+{
-+	PBTC_COEXIST pBtCoexist;
-+	u32 ret = BT_STATUS_BT_OP_SUCCESS;
-+	u32 data = 0;
-+
-+	pBtCoexist = (PBTC_COEXIST)pBtcContext;
-+
-+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
-+		u8 buf[3] = {0};
-+		_irqL irqL;
-+		u8 op_code;
-+		u8 status;
-+		
-+		buf[0] = scanType;
-+
-+		_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+		op_code = BT_OP_GET_BT_BLE_SCAN_PARA;
-+		status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 1);
-+		if (status == BT_STATUS_BT_OP_SUCCESS)
-+			data = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
-+		else
-+			ret = SET_BT_MP_OPER_RET(op_code, status);
-+
-+		_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+	} else
-+		ret = BT_STATUS_NOT_IMPLEMENT;
-+
-+	return data;
-+}
-+
-+u8 halbtcoutsrc_GetBtAFHMapFromBt(void *pBtcContext, u8 mapType, u8 *afhMap)
-+{
-+	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
-+	u8 buf[2] = {0};
-+	_irqL irqL;
-+	u8 op_code;
-+	u32 *AfhMapL = (u32 *)&(afhMap[0]);
-+	u32 *AfhMapM = (u32 *)&(afhMap[4]);
-+	u16 *AfhMapH = (u16 *)&(afhMap[8]);
-+	u8 status;
-+	u32 ret = BT_STATUS_BT_OP_SUCCESS;
-+
-+	if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _FALSE)
-+		return _FALSE;
-+
-+	buf[0] = 0;
-+	buf[1] = mapType;
-+
-+	_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+	op_code = BT_LO_OP_GET_AFH_MAP_L;
-+	status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
-+	if (status == BT_STATUS_BT_OP_SUCCESS)
-+		*AfhMapL = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
-+	else {
-+		ret = SET_BT_MP_OPER_RET(op_code, status);
-+		goto exit;
-+	}
-+
-+	op_code = BT_LO_OP_GET_AFH_MAP_M;
-+	status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
-+	if (status == BT_STATUS_BT_OP_SUCCESS)
-+		*AfhMapM = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
-+	else {
-+		ret = SET_BT_MP_OPER_RET(op_code, status);
-+		goto exit;
-+	}
-+
-+	op_code = BT_LO_OP_GET_AFH_MAP_H;
-+	status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
-+	if (status == BT_STATUS_BT_OP_SUCCESS)
-+		*AfhMapH = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
-+	else {
-+		ret = SET_BT_MP_OPER_RET(op_code, status);
-+		goto exit;
-+	}
-+
-+exit:
-+
-+	_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
-+
-+	return (ret == BT_STATUS_BT_OP_SUCCESS) ? _TRUE : _FALSE;
-+}
-+
-+u8 halbtcoutsrc_SetTimer(void *pBtcContext, u32 type, u32 val)
-+{
-+	struct btc_coexist *pBtCoexist=(struct btc_coexist *)pBtcContext;
-+
-+	if (type >= BTC_TIMER_MAX)
-+		return _FALSE;
-+
-+	pBtCoexist->coex_sta.cnt_timer[type] = val;
-+
-+	RTW_DBG("[BTC], Set Timer: type = %d, val = %d\n", type, val);
-+
-+	return _TRUE;
-+}
-+
-+u32 halbtcoutsrc_SetAtomic (void *btc_ctx, u32 *target, u32 val)
-+{
-+	*target = val;
-+	return _SUCCESS;
-+}
-+
-+void halbtcoutsrc_phydm_modify_AntDiv_HwSw(void *pBtcContext, u8 is_hw)
-+{
-+	/* empty function since we don't need it */
-+}
-+
-+void halbtcoutsrc_phydm_modify_RA_PCR_threshold(void *pBtcContext, u8 RA_offset_direction, u8 RA_threshold_offset)
-+{
-+	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
-+
-+/* switch to #if 0 in case the phydm version does not provide the function */
-+#if 1
-+	phydm_modify_RA_PCR_threshold(pBtCoexist->odm_priv, RA_offset_direction, RA_threshold_offset);
-+#endif
-+}
-+
-+u32 halbtcoutsrc_phydm_query_PHY_counter(void *pBtcContext, u8 info_type)
-+{
-+	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
-+
-+/* switch to #if 0 in case the phydm version does not provide the function */
-+#if 1
-+	return phydm_cmn_info_query((struct dm_struct *)pBtCoexist->odm_priv, (enum phydm_info_query)info_type);
-+#else
-+	return 0;
-+#endif
-+}
-+
-+void halbtcoutsrc_reduce_wl_tx_power(void *pBtcContext, s8 tx_power)
-+{
-+	struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter);
-+
-+	/* The reduction of wl tx pwr should be processed inside the set tx pwr lvl function */
-+	if (IS_HARDWARE_TYPE_8822C(pBtCoexist->Adapter) || IS_HARDWARE_TYPE_8723F(pBtCoexist->Adapter))
-+		rtw_hal_set_tx_power_level(pBtCoexist->Adapter, pHalData->current_channel);
-+}
-+
-+#if 0
-+static void BT_CoexOffloadRecordErrC2hAck(PADAPTER	Adapter)
-+{
-+	PADAPTER		pDefaultAdapter = GetDefaultAdapter(Adapter);
-+
-+	if (pDefaultAdapter != Adapter)
-+		return;
-+
-+	if (!hal_btcoex_IsBtExist(Adapter))
-+		return;
-+
-+	gl_coex_offload.cnt_c2h_ack++;
-+
-+	gl_coex_offload.status[COL_STATUS_INVALID_C2H_LEN]++;
-+}
-+
-+static void BT_CoexOffloadC2hAckCheck(PADAPTER	Adapter, u8 *tmpBuf, u8 length)
-+{
-+	PADAPTER		pDefaultAdapter = GetDefaultAdapter(Adapter);
-+	PCOL_C2H_ACK	p_c2h_ack = NULL;
-+	u8			req_num = 0xff;
-+
-+	if (pDefaultAdapter != Adapter)
-+		return;
-+
-+	if (!hal_btcoex_IsBtExist(Adapter))
-+		return;
-+
-+	gl_coex_offload.cnt_c2h_ack++;
-+
-+	if (length < COL_C2H_ACK_HDR_LEN) {		/* c2h ack length must >= 3 (status, opcode_ver, req_num and ret_len) */
-+		gl_coex_offload.status[COL_STATUS_INVALID_C2H_LEN]++;
-+	} else {
-+		BT_PrintData(Adapter, "[COL], c2h ack:", length, tmpBuf);
-+
-+		p_c2h_ack = (PCOL_C2H_ACK)tmpBuf;
-+		req_num = p_c2h_ack->req_num;
-+
-+		_rtw_memmove(&gl_coex_offload.c2h_ack_buf[req_num][0], tmpBuf, length);
-+		gl_coex_offload.c2h_ack_len[req_num] = length;
-+
-+		complete(&gl_coex_offload.c2h_event[req_num]);
-+	}
-+}
-+
-+static void BT_CoexOffloadC2hIndCheck(PADAPTER Adapter, u8 *tmpBuf, u8 length)
-+{
-+	PADAPTER		pDefaultAdapter = GetDefaultAdapter(Adapter);
-+	PCOL_C2H_IND	p_c2h_ind = NULL;
-+	u8			ind_type = 0, ind_version = 0, ind_length = 0;
-+
-+	if (pDefaultAdapter != Adapter)
-+		return;
-+
-+	if (!hal_btcoex_IsBtExist(Adapter))
-+		return;
-+
-+	gl_coex_offload.cnt_c2h_ind++;
-+
-+	if (length < COL_C2H_IND_HDR_LEN) {		/* c2h indication length must >= 3 (type, version and length) */
-+		gl_coex_offload.c2h_ind_status[COL_STATUS_INVALID_C2H_LEN]++;
-+	} else {
-+		BT_PrintData(Adapter, "[COL], c2h indication:", length, tmpBuf);
-+
-+		p_c2h_ind = (PCOL_C2H_IND)tmpBuf;
-+		ind_type = p_c2h_ind->type;
-+		ind_version = p_c2h_ind->version;
-+		ind_length = p_c2h_ind->length;
-+
-+		_rtw_memmove(&gl_coex_offload.c2h_ind_buf[0], tmpBuf, length);
-+		gl_coex_offload.c2h_ind_len = length;
-+
-+		/* log */
-+		gl_coex_offload.c2h_ind_record[ind_type].count++;
-+		gl_coex_offload.c2h_ind_record[ind_type].status[COL_STATUS_C2H_OK]++;
-+		_rtw_memmove(&gl_coex_offload.c2h_ind_record[ind_type].ind_buf[0], tmpBuf, length);
-+		gl_coex_offload.c2h_ind_record[ind_type].ind_len = length;
-+
-+		gl_coex_offload.c2h_ind_status[COL_STATUS_C2H_OK]++;
-+		/*TODO: need to check c2h indication length*/
-+		/* TODO: Notification */
-+	}
-+}
-+
-+void BT_CoexOffloadC2hCheck(PADAPTER Adapter, u8 *Buffer, u8 Length)
-+{
-+#if 0 /*(USE_HAL_MAC_API == 1)*/
-+	u8	c2hSubCmdId = 0, c2hAckLen = 0, h2cCmdId = 0, h2cSubCmdId = 0, c2hIndLen = 0;
-+
-+	BT_PrintData(Adapter, "[COL], c2h packet:", Length - 2, Buffer + 2);
-+	c2hSubCmdId = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(Buffer);
-+
-+	if (c2hSubCmdId == C2H_SUB_CMD_ID_H2C_ACK_HDR ||
-+	    c2hSubCmdId == C2H_SUB_CMD_ID_BT_COEX_INFO) {
-+		if (c2hSubCmdId == C2H_SUB_CMD_ID_H2C_ACK_HDR) {
-+			/* coex c2h ack */
-+			h2cCmdId = (u8)H2C_ACK_HDR_GET_H2C_CMD_ID(Buffer);
-+			h2cSubCmdId = (u8)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(Buffer);
-+			if (h2cCmdId == 0xff && h2cSubCmdId == 0x60) {
-+				c2hAckLen = (u8)C2H_HDR_GET_LEN(Buffer);
-+				if (c2hAckLen >= 8)
-+					BT_CoexOffloadC2hAckCheck(Adapter, &Buffer[12], (u8)(c2hAckLen - 8));
-+				else
-+					BT_CoexOffloadRecordErrC2hAck(Adapter);
-+			}
-+		} else if (c2hSubCmdId == C2H_SUB_CMD_ID_BT_COEX_INFO) {
-+			/* coex c2h indication */
-+			c2hIndLen = (u8)C2H_HDR_GET_LEN(Buffer);
-+			BT_CoexOffloadC2hIndCheck(Adapter, &Buffer[4], (u8)c2hIndLen);
-+		}
-+	}
-+#endif
-+}
-+#endif
-+
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+static void halbtcoutsrc_wl_noisy_detect(struct btc_coexist *btc)
-+{
-+	struct btc_coex_sta *coex_sta = &btc->coex_sta;
-+	u32 cnt_cck, ok_11b, err_11b;
-+
-+	ok_11b = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_CCK);
-+	err_11b = btc->btc_phydm_query_PHY_counter(btc,
-+						   PHYDM_INFO_CRC32_ERROR_CCK);
-+
-+	/* WiFi environment noisy identification */
-+	cnt_cck = ok_11b + err_11b;
-+
-+	if (!coex_sta->wl_gl_busy && !coex_sta->wl_cck_lock) {
-+		if (cnt_cck > 250) {
-+			if (coex_sta->cnt_wl[BTC_CNT_WL_NOISY2] < 5)
-+				coex_sta->cnt_wl[BTC_CNT_WL_NOISY2]++;
-+
-+			if (coex_sta->cnt_wl[BTC_CNT_WL_NOISY2] == 5) {
-+				coex_sta->cnt_wl[BTC_CNT_WL_NOISY0] = 0;
-+				coex_sta->cnt_wl[BTC_CNT_WL_NOISY1] = 0;
-+			}
-+		} else if (cnt_cck < 100) {
-+			if (coex_sta->cnt_wl[BTC_CNT_WL_NOISY0] < 5)
-+				coex_sta->cnt_wl[BTC_CNT_WL_NOISY0]++;
-+
-+			if (coex_sta->cnt_wl[BTC_CNT_WL_NOISY0] == 5) {
-+				coex_sta->cnt_wl[BTC_CNT_WL_NOISY1] = 0;
-+				coex_sta->cnt_wl[BTC_CNT_WL_NOISY2] = 0;
-+			}
-+		} else {
-+			if (coex_sta->cnt_wl[BTC_CNT_WL_NOISY1] < 5)
-+				coex_sta->cnt_wl[BTC_CNT_WL_NOISY1]++;
-+
-+			if (coex_sta->cnt_wl[BTC_CNT_WL_NOISY1] == 5) {
-+				coex_sta->cnt_wl[BTC_CNT_WL_NOISY0] = 0;
-+				coex_sta->cnt_wl[BTC_CNT_WL_NOISY2] = 0;
-+			}
-+		}
-+
-+		if (coex_sta->cnt_wl[BTC_CNT_WL_NOISY2] == 5)
-+			coex_sta->wl_noisy_level = 2;
-+		else if (coex_sta->cnt_wl[BTC_CNT_WL_NOISY1] == 5)
-+			coex_sta->wl_noisy_level = 1;
-+		else
-+			coex_sta->wl_noisy_level = 0;
-+
-+		RTW_DBG("[BTC], wl_noisy_level = %d\n",
-+			    coex_sta->wl_noisy_level);
-+	}
-+}
-+
-+static boolean halbtcoutsrc_btc_monitor_bt_ctr(struct btc_coexist *btc)
-+{
-+	struct btc_coex_sta *coex_sta = &btc->coex_sta;
-+	struct btc_coex_dm *coex_dm = &btc->coex_dm;
-+	u32 cnt_bt_hi_pri, cnt_bt_lo_pri, cnt_bt_all;
-+	boolean is_run_coex = _FALSE;
-+
-+	cnt_bt_hi_pri = btc->btc_read_4byte(btc, REG_BT_ACT_STATISTICS);
-+	coex_sta->hi_pri_tx = cnt_bt_hi_pri & MASKLWORD;
-+	coex_sta->hi_pri_rx = (cnt_bt_hi_pri & MASKHWORD) >> 16;
-+
-+	cnt_bt_lo_pri = btc->btc_read_4byte(btc, REG_BT_ACT_STATISTICS_1);
-+	coex_sta->lo_pri_tx = cnt_bt_lo_pri & MASKLWORD;
-+	coex_sta->lo_pri_rx = (cnt_bt_lo_pri & MASKHWORD) >> 16;
-+
-+	RTW_DBG("[BTC], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
-+		    coex_sta->hi_pri_rx, coex_sta->hi_pri_tx,
-+		    coex_sta->lo_pri_rx, coex_sta->lo_pri_tx);
-+
-+	/* reset counter */
-+	btc->btc_write_1byte(btc, 0x76e, 0xc);
-+
-+	if (coex_sta->wl_under_lps || coex_sta->wl_under_ips ||
-+	    (coex_sta->hi_pri_rx == 65535 && coex_sta->hi_pri_tx == 65535 &&
-+	    coex_sta->lo_pri_rx == 65535 && coex_sta->lo_pri_tx == 65535))
-+		coex_sta->bt_ctr_ok = _FALSE;
-+	else
-+		coex_sta->bt_ctr_ok = _TRUE;
-+
-+	if (!coex_sta->bt_ctr_ok)
-+		return _FALSE;
-+
-+	if (coex_sta->hi_pri_rx == 0 && coex_sta->hi_pri_tx == 0 &&
-+	    coex_sta->lo_pri_rx == 0 && coex_sta->lo_pri_tx == 0) {
-+		coex_sta->cnt_bt[BTC_CNT_BT_DISABLE]++;
-+
-+		if (coex_sta->cnt_bt[BTC_CNT_BT_DISABLE] > 2)
-+			coex_sta->cnt_bt[BTC_CNT_BT_DISABLE] = 2;
-+	} else {
-+		coex_sta->cnt_bt[BTC_CNT_BT_DISABLE] = 0;
-+	}
-+
-+	cnt_bt_all = coex_sta->hi_pri_rx + coex_sta->hi_pri_tx +
-+		     coex_sta->lo_pri_rx + coex_sta->lo_pri_tx;
-+
-+	if ((coex_sta->cnt_bt[BTC_CNT_BT_TRX] > (cnt_bt_all + 50) ||
-+	    cnt_bt_all > (coex_sta->cnt_bt[BTC_CNT_BT_TRX] + 50)) &&
-+	    coex_dm->bt_status == BTC_BTSTATUS_NCON_IDLE)
-+	    	is_run_coex = _TRUE;
-+
-+	coex_sta->cnt_bt[BTC_CNT_BT_TRX] = cnt_bt_all;
-+
-+	return is_run_coex;
-+}
-+#endif
-+
-+/* ************************************
-+ *		Extern functions called by other module
-+ * ************************************ */
-+u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter)
-+{
-+	PBTC_COEXIST		pBtCoexist = &GLBtCoexist;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA((PADAPTER)padapter);
-+
-+	if (pBtCoexist->bBinded)
-+		return _FALSE;
-+	else
-+		pBtCoexist->bBinded = _TRUE;
-+
-+	pBtCoexist->statistics.cnt_bind++;
-+
-+	pBtCoexist->Adapter = padapter;
-+	pBtCoexist->odm_priv = (void *)&(pHalData->odmpriv);
-+
-+	pBtCoexist->stack_info.profile_notified = _FALSE;
-+
-+	pBtCoexist->bt_info.bt_ctrl_agg_buf_size = _FALSE;
-+	pBtCoexist->bt_info.agg_buf_size = 5;
-+
-+	pBtCoexist->bt_info.increase_scan_dev_num = _FALSE;
-+	pBtCoexist->bt_info.miracast_plus_bt = _FALSE;
-+
-+	/* for btc common architecture, inform chip type to coex. mechanism */
-+	if(IS_HARDWARE_TYPE_8822C(padapter)) {
-+#ifdef CONFIG_RTL8822C
-+		pBtCoexist->chip_type = BTC_CHIP_RTL8822C;
-+		pBtCoexist->chip_para = &btc_chip_para_8822c;
-+#endif
-+	}
-+#ifdef CONFIG_RTL8192F
-+	else if (IS_HARDWARE_TYPE_8192F(padapter)) {
-+		pBtCoexist->chip_type = BTC_CHIP_RTL8725A;
-+		pBtCoexist->chip_para = &btc_chip_para_8192f;
-+	}
-+#endif
-+#ifdef PLATFORM_LINUX
-+#ifdef CONFIG_RTL8723F
-+	else if (IS_HARDWARE_TYPE_8723F(padapter)) {
-+			pBtCoexist->chip_type = BTC_CHIP_RTL8723F;
-+			pBtCoexist->chip_para = &btc_chip_para_8723f;
-+		}
-+#endif
-+#endif
-+	else {
-+		pBtCoexist->chip_type = BTC_CHIP_UNDEF;
-+		pBtCoexist->chip_para = NULL;
-+	}
-+
-+	return _TRUE;
-+}
-+
-+void EXhalbtcoutsrc_AntInfoSetting(void *padapter)
-+{
-+	PBTC_COEXIST		pBtCoexist = &GLBtCoexist;
-+	u8	antNum = 1, singleAntPath = 0;
-+
-+	antNum = rtw_btcoex_get_pg_ant_num((PADAPTER)padapter);
-+	EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_PG, antNum);
-+
-+	if (antNum == 1) {
-+		singleAntPath = rtw_btcoex_get_pg_single_ant_path((PADAPTER)padapter);
-+		EXhalbtcoutsrc_SetSingleAntPath(singleAntPath);
-+	}
-+
-+	pBtCoexist->board_info.customerID = RT_CID_DEFAULT;
-+	pBtCoexist->board_info.customer_id = RT_CID_DEFAULT;
-+
-+	/* set default antenna position to main  port */
-+	pBtCoexist->board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
-+
-+	pBtCoexist->board_info.btdm_ant_det_finish = _FALSE;
-+	pBtCoexist->board_info.btdm_ant_num_by_ant_det = 1;
-+
-+	pBtCoexist->board_info.tfbga_package = rtw_btcoex_is_tfbga_package_type((PADAPTER)padapter);
-+
-+	pBtCoexist->board_info.rfe_type = rtw_btcoex_get_pg_rfe_type((PADAPTER)padapter);
-+
-+	pBtCoexist->board_info.ant_div_cfg = rtw_btcoex_get_ant_div_cfg((PADAPTER)padapter);
-+
-+	pBtCoexist->board_info.ant_distance = 10;
-+}
-+
-+u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter)
-+{
-+	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
-+
-+	/* pBtCoexist->statistics.cntBind++; */
-+
-+	halbtcoutsrc_DbgInit();
-+
-+	halbtcoutsrc_coex_offload_init();
-+
-+#ifdef CONFIG_PCI_HCI
-+	pBtCoexist->chip_interface = BTC_INTF_PCI;
-+#elif defined(CONFIG_USB_HCI)
-+	pBtCoexist->chip_interface = BTC_INTF_USB;
-+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	pBtCoexist->chip_interface = BTC_INTF_SDIO;
-+#else
-+	pBtCoexist->chip_interface = BTC_INTF_UNKNOWN;
-+#endif
-+
-+	EXhalbtcoutsrc_BindBtCoexWithAdapter(padapter);
-+
-+	pBtCoexist->btc_read_1byte = halbtcoutsrc_Read1Byte;
-+	pBtCoexist->btc_write_1byte = halbtcoutsrc_Write1Byte;
-+	pBtCoexist->btc_write_1byte_bitmask = halbtcoutsrc_BitMaskWrite1Byte;
-+	pBtCoexist->btc_read_2byte = halbtcoutsrc_Read2Byte;
-+	pBtCoexist->btc_write_2byte = halbtcoutsrc_Write2Byte;
-+	pBtCoexist->btc_read_4byte = halbtcoutsrc_Read4Byte;
-+	pBtCoexist->btc_write_4byte = halbtcoutsrc_Write4Byte;
-+	pBtCoexist->btc_write_local_reg_1byte = halbtcoutsrc_WriteLocalReg1Byte;
-+
-+	pBtCoexist->btc_read_linderct = halbtcoutsrc_ReadLIndirectReg;
-+	pBtCoexist->btc_write_linderct = halbtcoutsrc_WriteLIndirectReg;
-+
-+	pBtCoexist->btc_read_scbd = halbtcoutsrc_Read_scbd;
-+	pBtCoexist->btc_read_scbd_32bit = halbtcoutsrc_Read_scbd_32bit;
-+	pBtCoexist->btc_write_scbd = halbtcoutsrc_Write_scbd;
-+	pBtCoexist->btc_write_scbd_32bit = halbtcoutsrc_Write_scbd_32bit;
-+
-+	pBtCoexist->btc_set_bb_reg = halbtcoutsrc_SetBbReg;
-+	pBtCoexist->btc_get_bb_reg = halbtcoutsrc_GetBbReg;
-+
-+	pBtCoexist->btc_set_rf_reg = halbtcoutsrc_SetRfReg;
-+	pBtCoexist->btc_get_rf_reg = halbtcoutsrc_GetRfReg;
-+
-+	pBtCoexist->btc_fill_h2c = halbtcoutsrc_FillH2cCmd;
-+	pBtCoexist->btc_disp_dbg_msg = halbtcoutsrc_DisplayDbgMsg;
-+
-+	pBtCoexist->btc_get = halbtcoutsrc_Get;
-+	pBtCoexist->btc_set = halbtcoutsrc_Set;
-+	pBtCoexist->btc_get_bt_reg = halbtcoutsrc_GetBtReg;
-+	pBtCoexist->btc_set_bt_reg = halbtcoutsrc_SetBtReg;
-+	pBtCoexist->btc_set_bt_ant_detection = halbtcoutsrc_SetBtAntDetection;
-+	pBtCoexist->btc_set_bt_trx_mask = halbtcoutsrc_SetBtTRXMASK;
-+	pBtCoexist->btc_coex_h2c_process = halbtcoutsrc_CoexH2cProcess;
-+	pBtCoexist->btc_get_bt_coex_supported_feature = halbtcoutsrc_GetBtCoexSupportedFeature;
-+	pBtCoexist->btc_get_bt_coex_supported_version= halbtcoutsrc_GetBtCoexSupportedVersion;
-+	pBtCoexist->btc_get_ant_det_val_from_bt = halbtcoutsrc_GetAntDetValFromBt;
-+	pBtCoexist->btc_get_ble_scan_type_from_bt = halbtcoutsrc_GetBleScanTypeFromBt;
-+	pBtCoexist->btc_get_ble_scan_para_from_bt = halbtcoutsrc_GetBleScanParaFromBt;
-+	pBtCoexist->btc_get_bt_afh_map_from_bt = halbtcoutsrc_GetBtAFHMapFromBt;
-+	pBtCoexist->btc_get_bt_phydm_version = halbtcoutsrc_GetPhydmVersion;
-+	pBtCoexist->btc_set_timer = halbtcoutsrc_SetTimer;
-+	pBtCoexist->btc_set_atomic= halbtcoutsrc_SetAtomic;
-+	pBtCoexist->btc_phydm_modify_RA_PCR_threshold = halbtcoutsrc_phydm_modify_RA_PCR_threshold;
-+	pBtCoexist->btc_phydm_query_PHY_counter = halbtcoutsrc_phydm_query_PHY_counter;
-+	pBtCoexist->btc_reduce_wl_tx_power = halbtcoutsrc_reduce_wl_tx_power;
-+	pBtCoexist->btc_phydm_modify_antdiv_hwsw = halbtcoutsrc_phydm_modify_AntDiv_HwSw;
-+
-+	pBtCoexist->cli_buf = &GLBtcDbgBuf[0];
-+
-+	GLBtcWiFiInScanState = _FALSE;
-+
-+	GLBtcWiFiInIQKState = _FALSE;
-+
-+	GLBtcWiFiInIPS = _FALSE;
-+
-+	GLBtcWiFiInLPS = _FALSE;
-+
-+	GLBtcBtCoexAliveRegistered = _FALSE;
-+
-+	/* BT Control H2C/C2H*/
-+	GLBtcBtMpOperSeq = 0;
-+	_rtw_mutex_init(&GLBtcBtMpOperLock);
-+	rtw_init_timer(&GLBtcBtMpOperTimer, padapter, _btmpoper_timer_hdl, pBtCoexist);
-+	_rtw_init_sema(&GLBtcBtMpRptSema, 0);
-+	GLBtcBtMpRptSeq = 0;
-+	GLBtcBtMpRptStatus = 0;
-+	_rtw_memset(GLBtcBtMpRptRsp, 0, C2H_MAX_SIZE);
-+	GLBtcBtMpRptRspSize = 0;
-+	GLBtcBtMpRptWait = _FALSE;
-+	GLBtcBtMpRptWiFiOK = _FALSE;
-+	GLBtcBtMpRptBTOK = _FALSE;
-+
-+	return _TRUE;
-+}
-+
-+void EXhalbtcoutsrc_PowerOnSetting(PBTC_COEXIST pBtCoexist)
-+{
-+	HAL_DATA_TYPE	*pHalData = NULL;
-+
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	pHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter);
-+
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_power_on_setting(pBtCoexist);
-+
-+#else
-+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8723B
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_power_on_setting(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_power_on_setting(pBtCoexist);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_power_on_setting(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_power_on_setting(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_power_on_setting(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821A
-+	else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821a1ant_power_on_setting(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821a2ant_power_on_setting(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if ((IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_power_on_setting(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_power_on_setting(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if ((IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_power_on_setting(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_power_on_setting(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_power_on_setting(pBtCoexist);
-+		/* else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8814a1ant_power_on_setting(pBtCoexist); */
-+	}
-+#endif
-+
-+#endif
-+}
-+
-+void EXhalbtcoutsrc_PreLoadFirmware(PBTC_COEXIST pBtCoexist)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	pBtCoexist->statistics.cnt_pre_load_firmware++;
-+
-+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8723B
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_pre_load_firmware(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_pre_load_firmware(pBtCoexist);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_pre_load_firmware(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_pre_load_firmware(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_pre_load_firmware(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_pre_load_firmware(pBtCoexist);
-+	}
-+#endif
-+}
-+
-+void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	pBtCoexist->statistics.cnt_init_hw_config++;
-+
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_init_hw_config(pBtCoexist, bWifiOnly);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8821A
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821a2ant_init_hw_config(pBtCoexist, bWifiOnly);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821a1ant_init_hw_config(pBtCoexist, bWifiOnly);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723B
-+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_init_hw_config(pBtCoexist, bWifiOnly);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_init_hw_config(pBtCoexist, bWifiOnly);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_init_hw_config(pBtCoexist, bWifiOnly);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_init_hw_config(pBtCoexist, bWifiOnly);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_init_hw_config(pBtCoexist, bWifiOnly);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8192e2ant_init_hw_config(pBtCoexist, bWifiOnly);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8192e1ant_init_hw_config(pBtCoexist, bWifiOnly);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8812a2ant_init_hw_config(pBtCoexist, bWifiOnly);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8812a1ant_init_hw_config(pBtCoexist, bWifiOnly);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_init_hw_config(pBtCoexist, bWifiOnly);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_init_hw_config(pBtCoexist, bWifiOnly);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_init_hw_config(pBtCoexist, bWifiOnly);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_init_hw_config(pBtCoexist, bWifiOnly);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_init_hw_config(pBtCoexist, bWifiOnly);
-+	}
-+#endif
-+
-+#endif
-+}
-+
-+void EXhalbtcoutsrc_init_coex_dm(PBTC_COEXIST pBtCoexist)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	pBtCoexist->statistics.cnt_init_coex_dm++;
-+
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_init_coex_dm(pBtCoexist);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8821A
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821a2ant_init_coex_dm(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821a1ant_init_coex_dm(pBtCoexist);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723B
-+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_init_coex_dm(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_init_coex_dm(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_init_coex_dm(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_init_coex_dm(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_init_coex_dm(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8192e2ant_init_coex_dm(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8192e1ant_init_coex_dm(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8812a2ant_init_coex_dm(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8812a1ant_init_coex_dm(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_init_coex_dm(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_init_coex_dm(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_init_coex_dm(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_init_coex_dm(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_init_coex_dm(pBtCoexist);
-+	}
-+#endif
-+
-+#endif
-+
-+	pBtCoexist->initilized = _TRUE;
-+}
-+
-+void EXhalbtcoutsrc_ips_notify(PBTC_COEXIST pBtCoexist, u8 type)
-+{
-+	u8	ipsType;
-+
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	pBtCoexist->statistics.cnt_ips_notify++;
-+	if (pBtCoexist->manual_control)
-+		return;
-+
-+	if (IPS_NONE == type) {
-+		ipsType = BTC_IPS_LEAVE;
-+		GLBtcWiFiInIPS = _FALSE;
-+	} else {
-+		ipsType = BTC_IPS_ENTER;
-+		GLBtcWiFiInIPS = _TRUE;
-+	}
-+
-+	/* All notify is called in cmd thread, don't need to leave low power again
-+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-+
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_ips_notify(pBtCoexist, ipsType);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8821A
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821a2ant_ips_notify(pBtCoexist, ipsType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821a1ant_ips_notify(pBtCoexist, ipsType);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723B
-+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_ips_notify(pBtCoexist, ipsType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_ips_notify(pBtCoexist, ipsType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_ips_notify(pBtCoexist, ipsType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_ips_notify(pBtCoexist, ipsType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_ips_notify(pBtCoexist, ipsType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8192e2ant_ips_notify(pBtCoexist, ipsType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8192e1ant_ips_notify(pBtCoexist, ipsType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8812a2ant_ips_notify(pBtCoexist, ipsType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8812a1ant_ips_notify(pBtCoexist, ipsType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_ips_notify(pBtCoexist, ipsType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_ips_notify(pBtCoexist, ipsType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_ips_notify(pBtCoexist, ipsType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_ips_notify(pBtCoexist, ipsType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_ips_notify(pBtCoexist, ipsType);
-+	}
-+#endif
-+
-+#endif
-+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
-+}
-+
-+void EXhalbtcoutsrc_lps_notify(PBTC_COEXIST pBtCoexist, u8 type)
-+{
-+	u8 lpsType;
-+
-+
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	pBtCoexist->statistics.cnt_lps_notify++;
-+	if (pBtCoexist->manual_control)
-+		return;
-+
-+	if (PS_MODE_ACTIVE == type) {
-+		lpsType = BTC_LPS_DISABLE;
-+		GLBtcWiFiInLPS = _FALSE;
-+	} else {
-+		lpsType = BTC_LPS_ENABLE;
-+		GLBtcWiFiInLPS = _TRUE;
-+	}
-+
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_lps_notify(pBtCoexist, lpsType);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8821A
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821a2ant_lps_notify(pBtCoexist, lpsType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821a1ant_lps_notify(pBtCoexist, lpsType);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723B
-+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_lps_notify(pBtCoexist, lpsType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_lps_notify(pBtCoexist, lpsType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_lps_notify(pBtCoexist, lpsType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_lps_notify(pBtCoexist, lpsType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_lps_notify(pBtCoexist, lpsType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8192e2ant_lps_notify(pBtCoexist, lpsType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8192e1ant_lps_notify(pBtCoexist, lpsType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8812a2ant_lps_notify(pBtCoexist, lpsType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8812a1ant_lps_notify(pBtCoexist, lpsType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_lps_notify(pBtCoexist, lpsType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_lps_notify(pBtCoexist, lpsType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_lps_notify(pBtCoexist, lpsType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_lps_notify(pBtCoexist, lpsType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_lps_notify(pBtCoexist, lpsType);
-+	}
-+#endif
-+
-+#endif
-+}
-+
-+void EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type)
-+{
-+	u8	scanType;
-+
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+	pBtCoexist->statistics.cnt_scan_notify++;
-+	if (pBtCoexist->manual_control)
-+		return;
-+
-+	if (type) {
-+		scanType = BTC_SCAN_START;
-+		GLBtcWiFiInScanState = _TRUE;
-+	} else {
-+		scanType = BTC_SCAN_FINISH;
-+		GLBtcWiFiInScanState = _FALSE;
-+	}
-+
-+	/* All notify is called in cmd thread, don't need to leave low power again
-+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-+
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_scan_notify(pBtCoexist, scanType);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8821A
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821a2ant_scan_notify(pBtCoexist, scanType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821a1ant_scan_notify(pBtCoexist, scanType);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723B
-+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_scan_notify(pBtCoexist, scanType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_scan_notify(pBtCoexist, scanType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_scan_notify(pBtCoexist, scanType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_scan_notify(pBtCoexist, scanType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_scan_notify(pBtCoexist, scanType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8192e2ant_scan_notify(pBtCoexist, scanType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8192e1ant_scan_notify(pBtCoexist, scanType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8812a2ant_scan_notify(pBtCoexist, scanType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8812a1ant_scan_notify(pBtCoexist, scanType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_scan_notify(pBtCoexist, scanType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_scan_notify(pBtCoexist, scanType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_scan_notify(pBtCoexist, scanType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_scan_notify(pBtCoexist, scanType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_scan_notify(pBtCoexist, scanType);
-+	}
-+#endif
-+
-+#endif
-+
-+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
-+}
-+
-+void EXhalbtcoutsrc_SetAntennaPathNotify(PBTC_COEXIST pBtCoexist, u8 type)
-+{
-+#if 0
-+	u8	switchType;
-+
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	if (pBtCoexist->manual_control)
-+		return;
-+
-+	halbtcoutsrc_LeaveLowPower(pBtCoexist);
-+
-+	switchType = type;
-+
-+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_set_antenna_notify(pBtCoexist, type);
-+	}
-+	if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_set_antenna_notify(pBtCoexist, type);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_set_antenna_notify(pBtCoexist, type);
-+	}
-+
-+	halbtcoutsrc_NormalLowPower(pBtCoexist);
-+#endif
-+}
-+
-+void EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 assoType)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+	pBtCoexist->statistics.cnt_connect_notify++;
-+	if (pBtCoexist->manual_control)
-+		return;
-+	
-+	/* All notify is called in cmd thread, don't need to leave low power again
-+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_connect_notify(pBtCoexist, assoType);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8821A
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821a2ant_connect_notify(pBtCoexist, assoType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821a1ant_connect_notify(pBtCoexist, assoType);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723B
-+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_connect_notify(pBtCoexist, assoType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_connect_notify(pBtCoexist, assoType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_connect_notify(pBtCoexist, assoType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_connect_notify(pBtCoexist, assoType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_connect_notify(pBtCoexist, assoType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8192e2ant_connect_notify(pBtCoexist, assoType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8192e1ant_connect_notify(pBtCoexist, assoType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8812a2ant_connect_notify(pBtCoexist, assoType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8812a1ant_connect_notify(pBtCoexist, assoType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_connect_notify(pBtCoexist, assoType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_connect_notify(pBtCoexist, assoType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_connect_notify(pBtCoexist, assoType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_connect_notify(pBtCoexist, assoType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_connect_notify(pBtCoexist, assoType);
-+	}
-+#endif
-+
-+#endif
-+
-+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
-+}
-+
-+void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS mediaStatus)
-+{
-+	u8 mStatus = BTC_MEDIA_MAX;
-+	PADAPTER adapter = NULL;
-+	HAL_DATA_TYPE *hal = NULL;
-+
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	if (pBtCoexist->manual_control)
-+		return;
-+
-+	pBtCoexist->statistics.cnt_media_status_notify++;
-+	adapter = (PADAPTER)pBtCoexist->Adapter;
-+	hal = GET_HAL_DATA(adapter);
-+
-+	if (RT_MEDIA_CONNECT == mediaStatus) {
-+		if (hal->current_band_type == BAND_ON_2_4G)
-+			mStatus = BTC_MEDIA_CONNECT;
-+		else if (hal->current_band_type == BAND_ON_5G)
-+			mStatus = BTC_MEDIA_CONNECT_5G;
-+		else {
-+			mStatus = BTC_MEDIA_CONNECT;
-+			RTW_ERR("%s unknow band type\n", __func__);
-+		}
-+	} else
-+		mStatus = BTC_MEDIA_DISCONNECT;
-+
-+	/* All notify is called in cmd thread, don't need to leave low power again
-+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_media_status_notify(pBtCoexist, mStatus);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8821A
-+		/* compatible for 8821A */
-+		if (mStatus == BTC_MEDIA_CONNECT_5G)
-+			mStatus = BTC_MEDIA_CONNECT;
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821a2ant_media_status_notify(pBtCoexist, mStatus);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821a1ant_media_status_notify(pBtCoexist, mStatus);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723B
-+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_media_status_notify(pBtCoexist, mStatus);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_media_status_notify(pBtCoexist, mStatus);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_media_status_notify(pBtCoexist, mStatus);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_media_status_notify(pBtCoexist, mStatus);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_media_status_notify(pBtCoexist, mStatus);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8192e2ant_media_status_notify(pBtCoexist, mStatus);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8192e1ant_media_status_notify(pBtCoexist, mStatus);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+		/* compatible for 8812A */
-+		if (mStatus == BTC_MEDIA_CONNECT_5G)
-+			mStatus = BTC_MEDIA_CONNECT;
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8812a2ant_media_status_notify(pBtCoexist, mStatus);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8812a1ant_media_status_notify(pBtCoexist, mStatus);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_media_status_notify(pBtCoexist, mStatus);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_media_status_notify(pBtCoexist, mStatus);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_media_status_notify(pBtCoexist, mStatus);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_media_status_notify(pBtCoexist, mStatus);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_media_status_notify(pBtCoexist, mStatus);
-+	}
-+#endif
-+
-+#endif
-+
-+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
-+}
-+
-+void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType)
-+{
-+	u8 packetType;
-+	PADAPTER adapter = NULL;
-+	HAL_DATA_TYPE *hal = NULL;
-+
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+	
-+	if (pBtCoexist->manual_control)
-+		return;
-+
-+	pBtCoexist->statistics.cnt_specific_packet_notify++;
-+	adapter = (PADAPTER)pBtCoexist->Adapter;
-+	hal = GET_HAL_DATA(adapter);
-+
-+	if (PACKET_DHCP == pktType)
-+		packetType = BTC_PACKET_DHCP;
-+	else if (PACKET_EAPOL == pktType)
-+		packetType = BTC_PACKET_EAPOL;
-+	else if (PACKET_ARP == pktType)
-+		packetType = BTC_PACKET_ARP;
-+	else {
-+		packetType = BTC_PACKET_UNKNOWN;
-+		return;
-+	}
-+
-+	if (hal->current_band_type == BAND_ON_5G)
-+		packetType |=  BTC_5G_BAND;
-+
-+	/* All notify is called in cmd thread, don't need to leave low power again
-+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_specific_packet_notify(pBtCoexist, packetType);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8821A
-+		/* compatible for 8821A */
-+		if (hal->current_band_type == BAND_ON_5G)
-+			packetType &= ~BTC_5G_BAND;
-+
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821a2ant_specific_packet_notify(pBtCoexist, packetType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821a1ant_specific_packet_notify(pBtCoexist, packetType);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723B
-+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_specific_packet_notify(pBtCoexist, packetType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_specific_packet_notify(pBtCoexist, packetType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_specific_packet_notify(pBtCoexist, packetType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_specific_packet_notify(pBtCoexist, packetType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_specific_packet_notify(pBtCoexist, packetType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8192e2ant_specific_packet_notify(pBtCoexist, packetType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8192e1ant_specific_packet_notify(pBtCoexist, packetType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+		/* compatible for 8812A */
-+		if (hal->current_band_type == BAND_ON_5G)
-+			packetType &= ~BTC_5G_BAND;
-+		
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8812a2ant_specific_packet_notify(pBtCoexist, packetType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8812a1ant_specific_packet_notify(pBtCoexist, packetType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_specific_packet_notify(pBtCoexist, packetType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_specific_packet_notify(pBtCoexist, packetType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_specific_packet_notify(pBtCoexist, packetType);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_specific_packet_notify(pBtCoexist, packetType);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_specific_packet_notify(pBtCoexist, packetType);
-+	}
-+#endif
-+
-+#endif
-+
-+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
-+}
-+
-+void EXhalbtcoutsrc_bt_info_notify(PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 length)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	pBtCoexist->statistics.cnt_bt_info_notify++;
-+
-+	/* All notify is called in cmd thread, don't need to leave low power again
-+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_bt_info_notify(pBtCoexist, tmpBuf, length);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8821A
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821a2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821a1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723B
-+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8192e2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8192e1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8812a2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8812a1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
-+	}
-+#endif
-+
-+#endif
-+
-+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
-+}
-+
-+void EXhalbtcoutsrc_WlFwDbgInfoNotify(PBTC_COEXIST pBtCoexist, u8* tmpBuf, u8 length)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8703B
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
-+	}
-+#endif
-+
-+#endif
-+}
-+
-+void EXhalbtcoutsrc_rx_rate_change_notify(PBTC_COEXIST pBtCoexist, u8 is_data_frame, u8 btc_rate_id)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	pBtCoexist->statistics.cnt_rate_id_notify++;
-+
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8703B
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
-+	}
-+#endif
-+
-+#endif
-+}
-+
-+void
-+EXhalbtcoutsrc_RfStatusNotify(
-+		PBTC_COEXIST		pBtCoexist,
-+		u8				type
-+)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+	pBtCoexist->statistics.cnt_rf_status_notify++;
-+
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_rf_status_notify(pBtCoexist, type);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8723B
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_rf_status_notify(pBtCoexist, type);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_rf_status_notify(pBtCoexist, type);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_rf_status_notify(pBtCoexist, type);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_rf_status_notify(pBtCoexist, type);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_rf_status_notify(pBtCoexist, type);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_rf_status_notify(pBtCoexist, type);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_rf_status_notify(pBtCoexist, type);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_rf_status_notify(pBtCoexist, type);
-+	}
-+#endif
-+
-+#endif
-+}
-+
-+void EXhalbtcoutsrc_StackOperationNotify(PBTC_COEXIST pBtCoexist, u8 type)
-+{
-+#if 0
-+	u8	stackOpType;
-+
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+	pBtCoexist->statistics.cntStackOperationNotify++;
-+	if (pBtCoexist->manual_control)
-+		return;
-+
-+	if ((HCI_BT_OP_INQUIRY_START == type) ||
-+	    (HCI_BT_OP_PAGING_START == type) ||
-+	    (HCI_BT_OP_PAIRING_START == type))
-+		stackOpType = BTC_STACK_OP_INQ_PAGE_PAIR_START;
-+	else if ((HCI_BT_OP_INQUIRY_FINISH == type) ||
-+		 (HCI_BT_OP_PAGING_SUCCESS == type) ||
-+		 (HCI_BT_OP_PAGING_UNSUCCESS == type) ||
-+		 (HCI_BT_OP_PAIRING_FINISH == type))
-+		stackOpType = BTC_STACK_OP_INQ_PAGE_PAIR_FINISH;
-+	else
-+		stackOpType = BTC_STACK_OP_NONE;
-+
-+#endif
-+}
-+
-+void EXhalbtcoutsrc_halt_notify(PBTC_COEXIST pBtCoexist)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	pBtCoexist->statistics.cnt_halt_notify++;
-+
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_halt_notify(pBtCoexist);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8821A
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821a2ant_halt_notify(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821a1ant_halt_notify(pBtCoexist);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723B
-+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_halt_notify(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_halt_notify(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_halt_notify(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_halt_notify(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_halt_notify(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8192e2ant_halt_notify(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8192e1ant_halt_notify(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8812a2ant_halt_notify(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8812a1ant_halt_notify(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_halt_notify(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_halt_notify(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_halt_notify(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_halt_notify(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_halt_notify(pBtCoexist);
-+	}
-+#endif
-+
-+#endif
-+}
-+
-+void EXhalbtcoutsrc_SwitchBtTRxMask(PBTC_COEXIST pBtCoexist)
-+{
-+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2) {
-+			halbtcoutsrc_SetBtReg(pBtCoexist, 0, 0x3c, 0x01); /* BT goto standby while GNT_BT 1-->0 */
-+		} else if (pBtCoexist->board_info.btdm_ant_num == 1) {
-+			halbtcoutsrc_SetBtReg(pBtCoexist, 0, 0x3c, 0x15); /* BT goto standby while GNT_BT 1-->0 */
-+		}
-+	}
-+}
-+
-+void EXhalbtcoutsrc_pnp_notify(PBTC_COEXIST pBtCoexist, u8 pnpState)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	pBtCoexist->statistics.cnt_pnp_notify++;
-+
-+	/*  */
-+	/* currently only 1ant we have to do the notification, */
-+	/* once pnp is notified to sleep state, we have to leave LPS that we can sleep normally. */
-+	/*  */
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_pnp_notify(pBtCoexist, pnpState);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8723B
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_pnp_notify(pBtCoexist, pnpState);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_pnp_notify(pBtCoexist, pnpState);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_pnp_notify(pBtCoexist, pnpState);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_pnp_notify(pBtCoexist, pnpState);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_pnp_notify(pBtCoexist, pnpState);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821A
-+	else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821a1ant_pnp_notify(pBtCoexist, pnpState);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821a2ant_pnp_notify(pBtCoexist, pnpState);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8192e1ant_pnp_notify(pBtCoexist, pnpState);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8812a1ant_pnp_notify(pBtCoexist, pnpState);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_pnp_notify(pBtCoexist, pnpState);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_pnp_notify(pBtCoexist, pnpState);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_pnp_notify(pBtCoexist, pnpState);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_pnp_notify(pBtCoexist, pnpState);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_pnp_notify(pBtCoexist, pnpState);
-+	}
-+#endif
-+
-+#endif
-+}
-+
-+void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+	pBtCoexist->statistics.cnt_coex_dm_switch++;
-+
-+	halbtcoutsrc_LeaveLowPower(pBtCoexist);
-+
-+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8723B
-+		if (pBtCoexist->board_info.btdm_ant_num == 1) {
-+			pBtCoexist->stop_coex_dm = TRUE;
-+			ex_halbtc8723b1ant_coex_dm_reset(pBtCoexist);
-+			EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_DETECTED, 2);
-+			ex_halbtc8723b2ant_init_hw_config(pBtCoexist, FALSE);
-+			ex_halbtc8723b2ant_init_coex_dm(pBtCoexist);
-+			pBtCoexist->stop_coex_dm = FALSE;
-+		}
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1) {
-+			pBtCoexist->stop_coex_dm = TRUE;
-+			ex_halbtc8723d1ant_coex_dm_reset(pBtCoexist);
-+			EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_DETECTED, 2);
-+			ex_halbtc8723d2ant_init_hw_config(pBtCoexist, FALSE);
-+			ex_halbtc8723d2ant_init_coex_dm(pBtCoexist);
-+			pBtCoexist->stop_coex_dm = FALSE;
-+		}
-+	}
-+#endif
-+
-+	halbtcoutsrc_NormalLowPower(pBtCoexist);
-+}
-+
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+void EXhalbtcoutsrc_TimerNotify(PBTC_COEXIST pBtCoexist, u32 timer_type)
-+{
-+	rtw_btc_ex_timerup_notify(pBtCoexist, timer_type);
-+}
-+
-+void EXhalbtcoutsrc_WLStatusChangeNotify(PBTC_COEXIST pBtCoexist, u32 change_type)
-+{
-+	rtw_btc_ex_wl_status_change_notify(pBtCoexist, change_type);
-+}
-+
-+u32 EXhalbtcoutsrc_CoexTimerCheck(PBTC_COEXIST pBtCoexist)
-+{
-+	u32 i, timer_map = 0;
-+
-+	for (i = 0; i < BTC_TIMER_MAX; i++) {
-+		if (pBtCoexist->coex_sta.cnt_timer[i] > 0) {
-+			if (pBtCoexist->coex_sta.cnt_timer[i] == 1) {
-+				timer_map |= BIT(i);
-+				RTW_DBG("[BTC], %s(): timer_map = 0x%x\n", __func__, timer_map);
-+			}
-+
-+			pBtCoexist->coex_sta.cnt_timer[i]--;
-+		}
-+	}
-+
-+	return timer_map;
-+}
-+
-+u32 EXhalbtcoutsrc_WLStatusCheck(PBTC_COEXIST pBtCoexist)
-+{
-+	struct btc_wifi_link_info link_info;
-+	struct btc_coex_sta *coex_sta = &pBtCoexist->coex_sta;
-+	const struct btc_chip_para *chip_para = pBtCoexist->chip_para;
-+	u32 change_map = 0;
-+	static bool wl_busy_pre;
-+	bool	wl_busy = _FALSE, bt_ctr_change = _FALSE;
-+	s32 wl_rssi;
-+	u32 traffic_dir;
-+	u8 i, tmp;
-+	static u8 rssi_step_pre = 5, wl_noisy_level_pre = 4;
-+
-+	halbtcoutsrc_wl_noisy_detect(pBtCoexist);
-+	bt_ctr_change = halbtcoutsrc_btc_monitor_bt_ctr(pBtCoexist);
-+
-+	/* WL busy to idle or idle to busy */
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &wl_busy);
-+	if (wl_busy != wl_busy_pre) {
-+		if (wl_busy)
-+			change_map |=  BIT(BTC_WLSTATUS_CHANGE_TOBUSY);
-+		else
-+			change_map |=  BIT(BTC_WLSTATUS_CHANGE_TOIDLE);
-+
-+		wl_busy_pre = wl_busy;
-+	}
-+
-+	/* WL RSSI */
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wl_rssi);
-+	tmp = (u8)(wl_rssi & 0xff);
-+	for (i = 0; i < 4; i++) {
-+		if (tmp >= chip_para->wl_rssi_step[i])
-+			break;
-+	}
-+
-+	if (rssi_step_pre != i) {
-+		rssi_step_pre = i;
-+		change_map |=  BIT(BTC_WLSTATUS_CHANGE_RSSI);
-+	}
-+
-+	/* WL Link info */
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK_INFO, &link_info);
-+	if (link_info.link_mode != pBtCoexist->wifi_link_info.link_mode ||
-+	    link_info.sta_center_channel !=
-+	    		pBtCoexist->wifi_link_info.sta_center_channel ||
-+	    link_info.p2p_center_channel !=
-+	    		pBtCoexist->wifi_link_info.p2p_center_channel ||
-+	    link_info.bany_client_join_go !=
-+	    		pBtCoexist->wifi_link_info.bany_client_join_go) {
-+		change_map |=  BIT(BTC_WLSTATUS_CHANGE_LINKINFO);
-+		pBtCoexist->wifi_link_info = link_info;
-+	}
-+
-+	/* WL Traffic Direction */
-+	pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIR, &traffic_dir);
-+	if (wl_busy && traffic_dir != pBtCoexist->wifi_link_info_ext.traffic_dir) {
-+		change_map |=  BIT(BTC_WLSTATUS_CHANGE_DIR);
-+		pBtCoexist->wifi_link_info_ext.traffic_dir = traffic_dir;
-+	}
-+
-+	/* Noisy Detect */
-+	if (coex_sta->wl_noisy_level != wl_noisy_level_pre) {
-+		change_map |=  BIT(BTC_WLSTATUS_CHANGE_NOISY);
-+		wl_noisy_level_pre = coex_sta->wl_noisy_level;
-+	}
-+
-+	/* BT Counter change > 50 */
-+	if (bt_ctr_change)
-+		change_map |=  BIT(BTC_WLSTATUS_CHANGE_BTCNT);
-+
-+	/* CCK Lock Try */
-+	if (coex_sta->wl_coex_mode == BTC_WLINK_2GFREE)
-+		coex_sta->cnt_wl[BTC_CNT_WL_2G_FDDSTAY]++;
-+
-+	if (coex_sta->wl_coex_mode == BTC_WLINK_2GFREE &&
-+	    coex_sta->cnt_wl[BTC_CNT_WL_2G_FDDSTAY] > BTC_2GFDD_MAX_STAY &&
-+	    coex_sta->cnt_wl[BTC_CNT_WL_2G_TDDTRY] < BTC_2GTDD_MAX_TRY) {
-+	    	coex_sta->cnt_wl[BTC_CNT_WL_2G_TDDTRY]++;
-+
-+		RTW_DBG("[BTC], Try 2.4G coex from FDD to TDD (FDD:%d, TRY:%d)\n",
-+			 coex_sta->cnt_wl[BTC_CNT_WL_2G_FDDSTAY],
-+			 coex_sta->cnt_wl[BTC_CNT_WL_2G_TDDTRY]);
-+
-+		coex_sta->cnt_wl[BTC_CNT_WL_2G_FDDSTAY] = 0;
-+		change_map |=  BIT(BTC_WLSTATUS_CHANGE_LOCKTRY);
-+	}
-+
-+	RTW_DBG("[BTC], %s(): change_map = 0x%x\n", __func__, change_map);
-+
-+	return change_map;
-+}
-+
-+void EXhalbtcoutsrc_status_monitor(PBTC_COEXIST pBtCoexist)
-+{
-+	u32 timer_up_type = 0, wl_status_change_type = 0;
-+
-+	timer_up_type = EXhalbtcoutsrc_CoexTimerCheck(pBtCoexist);
-+	if (timer_up_type != 0)
-+		EXhalbtcoutsrc_TimerNotify(pBtCoexist, timer_up_type);
-+
-+	wl_status_change_type =  EXhalbtcoutsrc_WLStatusCheck(pBtCoexist);
-+	if (wl_status_change_type != 0)
-+		EXhalbtcoutsrc_WLStatusChangeNotify(pBtCoexist, wl_status_change_type);
-+
-+	rtw_btc_ex_periodical(pBtCoexist);
-+}
-+#endif
-+
-+void EXhalbtcoutsrc_WL_RFK_Notify(PBTC_COEXIST pBtCoexist, u8 path, u8 type, u8 state)
-+{
-+	#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_wl_rfk_notify(pBtCoexist, path, type, state);
-+	#endif
-+	return;
-+}
-+
-+void EXhalbtcoutsrc_periodical(PBTC_COEXIST pBtCoexist)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+	pBtCoexist->statistics.cnt_periodical++;
-+
-+	/* Periodical should be called in cmd thread, */
-+	/* don't need to leave low power again
-+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	EXhalbtcoutsrc_status_monitor(pBtCoexist);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8821A
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821a2ant_periodical(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1) {
-+			if (!halbtcoutsrc_UnderIps(pBtCoexist))
-+				ex_halbtc8821a1ant_periodical(pBtCoexist);
-+		}
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723B
-+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_periodical(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_periodical(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_periodical(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_periodical(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_periodical(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8192e2ant_periodical(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8192e1ant_periodical(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8812a2ant_periodical(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8812a1ant_periodical(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_periodical(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_periodical(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_periodical(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_periodical(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_periodical(pBtCoexist);
-+	}
-+#endif
-+
-+#endif
-+
-+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
-+}
-+
-+void EXhalbtcoutsrc_dbg_control(PBTC_COEXIST pBtCoexist, u8 opCode, u8 opLen, u8 *pData)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	pBtCoexist->statistics.cnt_dbg_ctrl++;
-+
-+	/* This function doesn't be called yet, */
-+	/* default no need to leave low power to avoid deadlock
-+	*	halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	/* rtw_btc_ex_dbg_control(pBtCoexist, opCode, opLen, pData); */
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8192E
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8192e1ant_dbg_control(pBtCoexist, opCode, opLen, pData);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8812a2ant_dbg_control(pBtCoexist, opCode, opLen, pData);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8812a1ant_dbg_control(pBtCoexist, opCode, opLen, pData);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter))
-+		if(pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_dbg_control(pBtCoexist, opCode, opLen, pData);
-+#endif
-+
-+#endif
-+
-+	/*	halbtcoutsrc_NormalLowPower(pBtCoexist); */
-+}
-+
-+#if 0
-+void
-+EXhalbtcoutsrc_AntennaDetection(
-+		PBTC_COEXIST			pBtCoexist,
-+		u32					centFreq,
-+		u32					offset,
-+		u32					span,
-+		u32					seconds
-+)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	/* Need to refine the following power save operations to enable this function in the future */
-+#if 0
-+	IPSDisable(pBtCoexist->Adapter, FALSE, 0);
-+	LeisurePSLeave(pBtCoexist->Adapter, LPS_DISABLE_BT_COEX);
-+#endif
-+
-+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_AntennaDetection(pBtCoexist, centFreq, offset, span, seconds);
-+	}
-+
-+	/* IPSReturn(pBtCoexist->Adapter, 0xff); */
-+}
-+#endif
-+
-+void EXhalbtcoutsrc_StackUpdateProfileInfo(void)
-+{
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
-+	PADAPTER padapter = NULL;
-+	PBT_MGNT pBtMgnt = NULL;
-+	u8 i;
-+
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	padapter = (PADAPTER)pBtCoexist->Adapter;
-+	pBtMgnt = &padapter->coex_info.BtMgnt;
-+
-+	pBtCoexist->stack_info.profile_notified = _TRUE;
-+
-+	pBtCoexist->stack_info.num_of_link =
-+		pBtMgnt->ExtConfig.NumberOfACL + pBtMgnt->ExtConfig.NumberOfSCO;
-+
-+	/* reset first */
-+	pBtCoexist->stack_info.bt_link_exist = _FALSE;
-+	pBtCoexist->stack_info.sco_exist = _FALSE;
-+	pBtCoexist->stack_info.acl_exist = _FALSE;
-+	pBtCoexist->stack_info.a2dp_exist = _FALSE;
-+	pBtCoexist->stack_info.hid_exist = _FALSE;
-+	pBtCoexist->stack_info.num_of_hid = 0;
-+	pBtCoexist->stack_info.pan_exist = _FALSE;
-+
-+	if (!pBtMgnt->ExtConfig.NumberOfACL)
-+		pBtCoexist->stack_info.min_bt_rssi = 0;
-+
-+	if (pBtCoexist->stack_info.num_of_link) {
-+		pBtCoexist->stack_info.bt_link_exist = _TRUE;
-+		if (pBtMgnt->ExtConfig.NumberOfSCO)
-+			pBtCoexist->stack_info.sco_exist = _TRUE;
-+		if (pBtMgnt->ExtConfig.NumberOfACL)
-+			pBtCoexist->stack_info.acl_exist = _TRUE;
-+	}
-+
-+	for (i = 0; i < pBtMgnt->ExtConfig.NumberOfACL; i++) {
-+		if (BT_PROFILE_A2DP == pBtMgnt->ExtConfig.aclLink[i].BTProfile)
-+			pBtCoexist->stack_info.a2dp_exist = _TRUE;
-+		else if (BT_PROFILE_PAN == pBtMgnt->ExtConfig.aclLink[i].BTProfile)
-+			pBtCoexist->stack_info.pan_exist = _TRUE;
-+		else if (BT_PROFILE_HID == pBtMgnt->ExtConfig.aclLink[i].BTProfile) {
-+			pBtCoexist->stack_info.hid_exist = _TRUE;
-+			pBtCoexist->stack_info.num_of_hid++;
-+		} else
-+			pBtCoexist->stack_info.unknown_acl_exist = _TRUE;
-+	}
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+}
-+
-+void EXhalbtcoutsrc_UpdateMinBtRssi(s8 btRssi)
-+{
-+	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
-+
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	pBtCoexist->stack_info.min_bt_rssi = btRssi;
-+}
-+
-+void EXhalbtcoutsrc_SetHciVersion(u16 hciVersion)
-+{
-+	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
-+
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	pBtCoexist->stack_info.hci_version = hciVersion;
-+}
-+
-+void EXhalbtcoutsrc_SetBtPatchVersion(u16 btHciVersion, u16 btPatchVersion)
-+{
-+	PBTC_COEXIST pBtCoexist = &GLBtCoexist;
-+
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	pBtCoexist->bt_info.bt_real_fw_ver = btPatchVersion;
-+	pBtCoexist->bt_info.bt_hci_ver = btHciVersion;
-+}
-+
-+#if 0
-+void EXhalbtcoutsrc_SetBtExist(u8 bBtExist)
-+{
-+	GLBtCoexist.boardInfo.bBtExist = bBtExist;
-+}
-+#endif
-+void EXhalbtcoutsrc_SetChipType(u8 chipType)
-+{
-+	switch (chipType) {
-+	default:
-+	case BT_2WIRE:
-+	case BT_ISSC_3WIRE:
-+	case BT_ACCEL:
-+	case BT_RTL8756:
-+		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_UNDEF;
-+		break;
-+	case BT_CSR_BC4:
-+		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_CSR_BC4;
-+		break;
-+	case BT_CSR_BC8:
-+		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_CSR_BC8;
-+		break;
-+	case BT_RTL8723A:
-+		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_RTL8723A;
-+		break;
-+	case BT_RTL8821:
-+		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_RTL8821;
-+		break;
-+	case BT_RTL8723B:
-+		GLBtCoexist.board_info.bt_chip_type = BTC_CHIP_RTL8723B;
-+		break;
-+	}
-+}
-+
-+void EXhalbtcoutsrc_SetAntNum(u8 type, u8 antNum)
-+{
-+	if (BT_COEX_ANT_TYPE_PG == type) {
-+		GLBtCoexist.board_info.pg_ant_num = antNum;
-+		GLBtCoexist.board_info.btdm_ant_num = antNum;
-+#if 0
-+		/* The antenna position: Main (default) or Aux for pgAntNum=2 && btdmAntNum =1 */
-+		/* The antenna position should be determined by auto-detect mechanism */
-+		/* The following is assumed to main, and those must be modified if y auto-detect mechanism is ready */
-+		if ((GLBtCoexist.board_info.pg_ant_num == 2) && (GLBtCoexist.board_info.btdm_ant_num == 1))
-+			GLBtCoexist.board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
-+		else
-+			GLBtCoexist.board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
-+#endif
-+	} else if (BT_COEX_ANT_TYPE_ANTDIV == type) {
-+		GLBtCoexist.board_info.btdm_ant_num = antNum;
-+		/* GLBtCoexist.boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT;	 */
-+	} else if (BT_COEX_ANT_TYPE_DETECTED == type) {
-+		GLBtCoexist.board_info.btdm_ant_num = antNum;
-+		/* GLBtCoexist.boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; */
-+	}
-+}
-+
-+/*
-+ * Currently used by 8723b only, S0 or S1
-+ *   */
-+void EXhalbtcoutsrc_SetSingleAntPath(u8 singleAntPath)
-+{
-+	GLBtCoexist.board_info.single_ant_path = singleAntPath;
-+}
-+
-+void EXhalbtcoutsrc_DisplayBtCoexInfo(PBTC_COEXIST pBtCoexist)
-+{
-+	HAL_DATA_TYPE	*pHalData = NULL;
-+
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	halbtcoutsrc_LeaveLowPower(pBtCoexist);
-+
-+	/* To prevent the racing with IPS enter */
-+	halbtcoutsrc_EnterPwrLock(pBtCoexist);
-+
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	pHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter);
-+
-+	if (pHalData->EEPROMBluetoothCoexist == _TRUE)
-+		rtw_btc_ex_display_coex_info(pBtCoexist);
-+#else
-+
-+	if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8821A
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821a2ant_display_coex_info(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821a1ant_display_coex_info(pBtCoexist);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8723B
-+	else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723b2ant_display_coex_info(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_display_coex_info(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8703b1ant_display_coex_info(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8723d2ant_display_coex_info(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723d1ant_display_coex_info(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8192e2ant_display_coex_info(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8192e1ant_display_coex_info(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8812a2ant_display_coex_info(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8812a1ant_display_coex_info(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_display_coex_info(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_display_coex_info(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_display_coex_info(pBtCoexist);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_display_coex_info(pBtCoexist);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_display_coex_info(pBtCoexist);
-+	}
-+#endif
-+
-+#endif
-+
-+	halbtcoutsrc_ExitPwrLock(pBtCoexist);
-+
-+	halbtcoutsrc_NormalLowPower(pBtCoexist);
-+}
-+
-+void EXhalbtcoutsrc_DisplayAntDetection(PBTC_COEXIST pBtCoexist)
-+{
-+	if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+
-+	halbtcoutsrc_LeaveLowPower(pBtCoexist);
-+
-+	if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8723B
-+		if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8723b1ant_display_ant_detection(pBtCoexist);
-+#endif
-+	}
-+
-+	halbtcoutsrc_NormalLowPower(pBtCoexist);
-+}
-+
-+void ex_halbtcoutsrc_pta_off_on_notify(PBTC_COEXIST pBtCoexist, u8 bBTON)
-+{
-+	if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8812A
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8812a2ant_pta_off_on_notify(pBtCoexist, (bBTON == _TRUE) ? BTC_BT_ON : BTC_BT_OFF);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_pta_off_on_notify(pBtCoexist, (bBTON == _TRUE) ? BTC_BT_ON : BTC_BT_OFF);
-+	}
-+#endif
-+}
-+
-+void EXhalbtcoutsrc_set_rfe_type(u8 type)
-+{
-+	GLBtCoexist.board_info.rfe_type= type;
-+}
-+
-+#ifdef CONFIG_RF4CE_COEXIST
-+void EXhalbtcoutsrc_set_rf4ce_link_state(u8 state)
-+{
-+	GLBtCoexist.rf4ce_info.link_state = state;
-+}
-+
-+u8 EXhalbtcoutsrc_get_rf4ce_link_state(void)
-+{
-+	return GLBtCoexist.rf4ce_info.link_state;
-+}
-+#endif
-+
-+void EXhalbtcoutsrc_switchband_notify(struct btc_coexist *pBtCoexist, u8 type)
-+{
-+	if(!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
-+		return;
-+	
-+	if(pBtCoexist->manual_control)
-+		return;
-+
-+	/* Driver should guarantee that the HW status isn't in low power mode */
-+	/* halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-+#if (CONFIG_BTCOEX_SUPPORT_BTC_CMN == 1)
-+	rtw_btc_ex_switchband_notify(pBtCoexist, type);
-+#else
-+
-+	if(IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
-+#ifdef CONFIG_RTL8822B
-+		if(pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8822b1ant_switchband_notify(pBtCoexist, type);
-+		else if(pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8822b2ant_switchband_notify(pBtCoexist, type);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8821c2ant_switchband_notify(pBtCoexist, type);
-+		else if (pBtCoexist->board_info.btdm_ant_num == 1)
-+			ex_halbtc8821c1ant_switchband_notify(pBtCoexist, type);
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	else if (IS_HARDWARE_TYPE_8814A(pBtCoexist->Adapter)) {
-+		if (pBtCoexist->board_info.btdm_ant_num == 2)
-+			ex_halbtc8814a2ant_switchband_notify(pBtCoexist, type);
-+	}
-+#endif
-+
-+#endif
-+
-+	/* halbtcoutsrc_NormalLowPower(pBtCoexist); */
-+}
-+
-+u8 EXhalbtcoutsrc_rate_id_to_btc_rate_id(u8 rate_id)
-+{
-+	u8 btc_rate_id = BTC_UNKNOWN;
-+
-+	switch (rate_id) {
-+		/* CCK rates */
-+		case DESC_RATE1M:
-+			btc_rate_id = BTC_CCK_1;
-+			break;
-+		case DESC_RATE2M:
-+			btc_rate_id = BTC_CCK_2;
-+			break;
-+		case DESC_RATE5_5M:
-+			btc_rate_id = BTC_CCK_5_5;
-+			break;
-+		case DESC_RATE11M:
-+			btc_rate_id = BTC_CCK_11;
-+			break;
-+
-+		/* OFDM rates */
-+		case DESC_RATE6M:
-+			btc_rate_id = BTC_OFDM_6;
-+			break;
-+		case DESC_RATE9M:
-+			btc_rate_id = BTC_OFDM_9;
-+			break;
-+		case DESC_RATE12M:
-+			btc_rate_id = BTC_OFDM_12;
-+			break;
-+		case DESC_RATE18M:
-+			btc_rate_id = BTC_OFDM_18;
-+			break;
-+		case DESC_RATE24M:
-+			btc_rate_id = BTC_OFDM_24;
-+			break;
-+		case DESC_RATE36M:
-+			btc_rate_id = BTC_OFDM_36;
-+			break;
-+		case DESC_RATE48M:
-+			btc_rate_id = BTC_OFDM_48;
-+			break;
-+		case DESC_RATE54M:
-+			btc_rate_id = BTC_OFDM_54;
-+			break;
-+
-+		/* MCS rates */
-+		case DESC_RATEMCS0:
-+			btc_rate_id = BTC_MCS_0;
-+			break;
-+		case DESC_RATEMCS1:
-+			btc_rate_id = BTC_MCS_1;
-+			break;
-+		case DESC_RATEMCS2:
-+			btc_rate_id = BTC_MCS_2;
-+			break;
-+		case DESC_RATEMCS3:
-+			btc_rate_id = BTC_MCS_3;
-+			break;
-+		case DESC_RATEMCS4:
-+			btc_rate_id = BTC_MCS_4;
-+			break;
-+		case DESC_RATEMCS5:
-+			btc_rate_id = BTC_MCS_5;
-+			break;
-+		case DESC_RATEMCS6:
-+			btc_rate_id = BTC_MCS_6;
-+			break;
-+		case DESC_RATEMCS7:
-+			btc_rate_id = BTC_MCS_7;
-+			break;
-+		case DESC_RATEMCS8:
-+			btc_rate_id = BTC_MCS_8;
-+			break;
-+		case DESC_RATEMCS9:
-+			btc_rate_id = BTC_MCS_9;
-+			break;
-+		case DESC_RATEMCS10:
-+			btc_rate_id = BTC_MCS_10;
-+			break;
-+		case DESC_RATEMCS11:
-+			btc_rate_id = BTC_MCS_11;
-+			break;
-+		case DESC_RATEMCS12:
-+			btc_rate_id = BTC_MCS_12;
-+			break;
-+		case DESC_RATEMCS13:
-+			btc_rate_id = BTC_MCS_13;
-+			break;
-+		case DESC_RATEMCS14:
-+			btc_rate_id = BTC_MCS_14;
-+			break;
-+		case DESC_RATEMCS15:
-+			btc_rate_id = BTC_MCS_15;
-+			break;
-+		case DESC_RATEMCS16:
-+			btc_rate_id = BTC_MCS_16;
-+			break;
-+		case DESC_RATEMCS17:
-+			btc_rate_id = BTC_MCS_17;
-+			break;
-+		case DESC_RATEMCS18:
-+			btc_rate_id = BTC_MCS_18;
-+			break;
-+		case DESC_RATEMCS19:
-+			btc_rate_id = BTC_MCS_19;
-+			break;
-+		case DESC_RATEMCS20:
-+			btc_rate_id = BTC_MCS_20;
-+			break;
-+		case DESC_RATEMCS21:
-+			btc_rate_id = BTC_MCS_21;
-+			break;
-+		case DESC_RATEMCS22:
-+			btc_rate_id = BTC_MCS_22;
-+			break;
-+		case DESC_RATEMCS23:
-+			btc_rate_id = BTC_MCS_23;
-+			break;
-+		case DESC_RATEMCS24:
-+			btc_rate_id = BTC_MCS_24;
-+			break;
-+		case DESC_RATEMCS25:
-+			btc_rate_id = BTC_MCS_25;
-+			break;
-+		case DESC_RATEMCS26:
-+			btc_rate_id = BTC_MCS_26;
-+			break;
-+		case DESC_RATEMCS27:
-+			btc_rate_id = BTC_MCS_27;
-+			break;
-+		case DESC_RATEMCS28:
-+			btc_rate_id = BTC_MCS_28;
-+			break;
-+		case DESC_RATEMCS29:
-+			btc_rate_id = BTC_MCS_29;
-+			break;
-+		case DESC_RATEMCS30:
-+			btc_rate_id = BTC_MCS_30;
-+			break;
-+		case DESC_RATEMCS31:
-+			btc_rate_id = BTC_MCS_31;
-+			break;
-+			
-+		case DESC_RATEVHTSS1MCS0:
-+			btc_rate_id = BTC_VHT_1SS_MCS_0;
-+			break;
-+		case DESC_RATEVHTSS1MCS1:
-+			btc_rate_id = BTC_VHT_1SS_MCS_1;
-+			break;
-+		case DESC_RATEVHTSS1MCS2:
-+			btc_rate_id = BTC_VHT_1SS_MCS_2;
-+			break;
-+		case DESC_RATEVHTSS1MCS3:
-+			btc_rate_id = BTC_VHT_1SS_MCS_3;
-+			break;
-+		case DESC_RATEVHTSS1MCS4:
-+			btc_rate_id = BTC_VHT_1SS_MCS_4;
-+			break;
-+		case DESC_RATEVHTSS1MCS5:
-+			btc_rate_id = BTC_VHT_1SS_MCS_5;
-+			break;
-+		case DESC_RATEVHTSS1MCS6:
-+			btc_rate_id = BTC_VHT_1SS_MCS_6;
-+			break;
-+		case DESC_RATEVHTSS1MCS7:
-+			btc_rate_id = BTC_VHT_1SS_MCS_7;
-+			break;
-+		case DESC_RATEVHTSS1MCS8:
-+			btc_rate_id = BTC_VHT_1SS_MCS_8;
-+			break;
-+		case DESC_RATEVHTSS1MCS9:
-+			btc_rate_id = BTC_VHT_1SS_MCS_9;
-+			break;
-+
-+		case DESC_RATEVHTSS2MCS0:
-+			btc_rate_id = BTC_VHT_2SS_MCS_0;
-+			break;
-+		case DESC_RATEVHTSS2MCS1:
-+			btc_rate_id = BTC_VHT_2SS_MCS_1;
-+			break;
-+		case DESC_RATEVHTSS2MCS2:
-+			btc_rate_id = BTC_VHT_2SS_MCS_2;
-+			break;
-+		case DESC_RATEVHTSS2MCS3:
-+			btc_rate_id = BTC_VHT_2SS_MCS_3;
-+			break;
-+		case DESC_RATEVHTSS2MCS4:
-+			btc_rate_id = BTC_VHT_2SS_MCS_4;
-+			break;
-+		case DESC_RATEVHTSS2MCS5:
-+			btc_rate_id = BTC_VHT_2SS_MCS_5;
-+			break;
-+		case DESC_RATEVHTSS2MCS6:
-+			btc_rate_id = BTC_VHT_2SS_MCS_6;
-+			break;
-+		case DESC_RATEVHTSS2MCS7:
-+			btc_rate_id = BTC_VHT_2SS_MCS_7;
-+			break;
-+		case DESC_RATEVHTSS2MCS8:
-+			btc_rate_id = BTC_VHT_2SS_MCS_8;
-+			break;
-+		case DESC_RATEVHTSS2MCS9:
-+			btc_rate_id = BTC_VHT_2SS_MCS_9;
-+			break;
-+
-+		case DESC_RATEVHTSS3MCS0:
-+			btc_rate_id = BTC_VHT_3SS_MCS_0;
-+			break;
-+		case DESC_RATEVHTSS3MCS1:
-+			btc_rate_id = BTC_VHT_3SS_MCS_1;
-+			break;
-+		case DESC_RATEVHTSS3MCS2:
-+			btc_rate_id = BTC_VHT_3SS_MCS_2;
-+			break;
-+		case DESC_RATEVHTSS3MCS3:
-+			btc_rate_id = BTC_VHT_3SS_MCS_3;
-+			break;
-+		case DESC_RATEVHTSS3MCS4:
-+			btc_rate_id = BTC_VHT_3SS_MCS_4;
-+			break;
-+		case DESC_RATEVHTSS3MCS5:
-+			btc_rate_id = BTC_VHT_3SS_MCS_5;
-+			break;
-+		case DESC_RATEVHTSS3MCS6:
-+			btc_rate_id = BTC_VHT_3SS_MCS_6;
-+			break;
-+		case DESC_RATEVHTSS3MCS7:
-+			btc_rate_id = BTC_VHT_3SS_MCS_7;
-+			break;
-+		case DESC_RATEVHTSS3MCS8:
-+			btc_rate_id = BTC_VHT_3SS_MCS_8;
-+			break;
-+		case DESC_RATEVHTSS3MCS9:
-+			btc_rate_id = BTC_VHT_3SS_MCS_9;
-+			break;
-+
-+		case DESC_RATEVHTSS4MCS0:
-+			btc_rate_id = BTC_VHT_4SS_MCS_0;
-+			break;
-+		case DESC_RATEVHTSS4MCS1:
-+			btc_rate_id = BTC_VHT_4SS_MCS_1;
-+			break;
-+		case DESC_RATEVHTSS4MCS2:
-+			btc_rate_id = BTC_VHT_4SS_MCS_2;
-+			break;
-+		case DESC_RATEVHTSS4MCS3:
-+			btc_rate_id = BTC_VHT_4SS_MCS_3;
-+			break;
-+		case DESC_RATEVHTSS4MCS4:
-+			btc_rate_id = BTC_VHT_4SS_MCS_4;
-+			break;
-+		case DESC_RATEVHTSS4MCS5:
-+			btc_rate_id = BTC_VHT_4SS_MCS_5;
-+			break;
-+		case DESC_RATEVHTSS4MCS6:
-+			btc_rate_id = BTC_VHT_4SS_MCS_6;
-+			break;
-+		case DESC_RATEVHTSS4MCS7:
-+			btc_rate_id = BTC_VHT_4SS_MCS_7;
-+			break;
-+		case DESC_RATEVHTSS4MCS8:
-+			btc_rate_id = BTC_VHT_4SS_MCS_8;
-+			break;
-+		case DESC_RATEVHTSS4MCS9:
-+			btc_rate_id = BTC_VHT_4SS_MCS_9;
-+			break;
-+	}
-+	
-+	return btc_rate_id;
-+}
-+
-+/*
-+ * Description:
-+ *	Run BT-Coexist mechansim or not
-+ *
-+ */
-+void hal_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	pHalData->bt_coexist.bBtExist = bBtExist;
-+}
-+
-+/*
-+ * Dewcription:
-+ *	Check is co-exist mechanism enabled or not
-+ *
-+ * Return:
-+ *	_TRUE	Enable BT co-exist mechanism
-+ *	_FALSE	Disable BT co-exist mechanism
-+ */
-+u8 hal_btcoex_IsBtExist(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	return pHalData->bt_coexist.bBtExist;
-+}
-+
-+u8 hal_btcoex_IsBtDisabled(PADAPTER padapter)
-+{
-+	if (!hal_btcoex_IsBtExist(padapter))
-+		return _TRUE;
-+
-+	if (GLBtCoexist.bt_info.bt_disabled)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+void hal_btcoex_SetChipType(PADAPTER padapter, u8 chipType)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	pHalData->bt_coexist.btChipType = chipType;
-+}
-+
-+void hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum)
-+{
-+	PHAL_DATA_TYPE	pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	pHalData->bt_coexist.btTotalAntNum = antNum;
-+}
-+
-+u8 hal_btcoex_Initialize(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	u8 ret;
-+
-+	_rtw_memset(&GLBtCoexist, 0, sizeof(GLBtCoexist));
-+
-+	ret = EXhalbtcoutsrc_InitlizeVariables((void *)padapter);
-+
-+	return ret;
-+}
-+
-+void hal_btcoex_PowerOnSetting(PADAPTER padapter)
-+{
-+	EXhalbtcoutsrc_PowerOnSetting(&GLBtCoexist);
-+}
-+
-+void hal_btcoex_AntInfoSetting(PADAPTER padapter)
-+{
-+	hal_btcoex_SetBTCoexist(padapter, rtw_btcoex_get_bt_coexist(padapter));
-+	hal_btcoex_SetChipType(padapter, rtw_btcoex_get_chip_type(padapter));
-+	hal_btcoex_SetPgAntNum(padapter, rtw_btcoex_get_pg_ant_num(padapter));
-+
-+	EXhalbtcoutsrc_AntInfoSetting(padapter);
-+}
-+
-+void hal_btcoex_PowerOffSetting(PADAPTER padapter)
-+{
-+	/* Clear the WiFi on/off bit in scoreboard reg. if necessary */
-+	if (IS_HARDWARE_TYPE_8703B(padapter) || IS_HARDWARE_TYPE_8723D(padapter)
-+		|| IS_HARDWARE_TYPE_8821C(padapter) || IS_HARDWARE_TYPE_8822B(padapter)
-+		|| IS_HARDWARE_TYPE_8822C(padapter))
-+		rtw_write16(padapter, 0xaa, 0x8000);
-+}
-+
-+void hal_btcoex_PreLoadFirmware(PADAPTER padapter)
-+{
-+	EXhalbtcoutsrc_PreLoadFirmware(&GLBtCoexist);
-+}
-+
-+void hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly)
-+{
-+	if (!hal_btcoex_IsBtExist(padapter))
-+		return;
-+
-+	EXhalbtcoutsrc_init_hw_config(&GLBtCoexist, bWifiOnly);
-+	EXhalbtcoutsrc_init_coex_dm(&GLBtCoexist);
-+}
-+
-+void hal_btcoex_IpsNotify(PADAPTER padapter, u8 type)
-+{
-+	EXhalbtcoutsrc_ips_notify(&GLBtCoexist, type);
-+}
-+
-+void hal_btcoex_LpsNotify(PADAPTER padapter, u8 type)
-+{
-+	EXhalbtcoutsrc_lps_notify(&GLBtCoexist, type);
-+}
-+
-+void hal_btcoex_ScanNotify(PADAPTER padapter, u8 type)
-+{
-+	EXhalbtcoutsrc_scan_notify(&GLBtCoexist, type);
-+}
-+
-+void hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action)
-+{
-+	u8 assoType = 0;
-+	u8 is_5g_band = _FALSE;
-+
-+	is_5g_band = (padapter->mlmeextpriv.cur_channel > 14) ? _TRUE : _FALSE;
-+
-+	if (action == _TRUE) {
-+		if (is_5g_band == _TRUE)
-+			assoType = BTC_ASSOCIATE_5G_START;
-+		else
-+			assoType = BTC_ASSOCIATE_START;
-+	}
-+	else {
-+		if (is_5g_band == _TRUE)
-+			assoType = BTC_ASSOCIATE_5G_FINISH;
-+		else
-+			assoType = BTC_ASSOCIATE_FINISH;
-+	}
-+	
-+	EXhalbtcoutsrc_connect_notify(&GLBtCoexist, assoType);
-+}
-+
-+void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus)
-+{
-+	EXhalbtcoutsrc_media_status_notify(&GLBtCoexist, mediaStatus);
-+}
-+
-+void hal_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType)
-+{
-+	EXhalbtcoutsrc_specific_packet_notify(&GLBtCoexist, pktType);
-+}
-+
-+void hal_btcoex_IQKNotify(PADAPTER padapter, u8 state)
-+{
-+	GLBtcWiFiInIQKState = state;
-+}
-+
-+void hal_btcoex_WLRFKNotify(PADAPTER padapter, u8 path, u8 type, u8 state)
-+{
-+	EXhalbtcoutsrc_WL_RFK_Notify(&GLBtCoexist, path, type, state);
-+}
-+
-+void hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
-+{
-+	if (GLBtcWiFiInIQKState == _TRUE)
-+		return;
-+
-+	EXhalbtcoutsrc_bt_info_notify(&GLBtCoexist, tmpBuf, length);
-+}
-+
-+void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
-+{
-+	u8 extid, status, len, seq;
-+
-+
-+	if (GLBtcBtMpRptWait == _FALSE)
-+		return;
-+
-+	if ((length < 3) || (!tmpBuf))
-+		return;
-+
-+	extid = tmpBuf[0];
-+	/* not response from BT FW then exit*/
-+	switch (extid) {
-+	case C2H_WIFI_FW_ACTIVE_RSP:
-+		GLBtcBtMpRptWiFiOK = _TRUE;
-+		break;
-+
-+	case C2H_TRIG_BY_BT_FW:
-+		GLBtcBtMpRptBTOK = _TRUE;
-+
-+		status = tmpBuf[1] & 0xF;
-+		len = length - 3;
-+		seq = tmpBuf[2] >> 4;
-+
-+		GLBtcBtMpRptSeq = seq;
-+		GLBtcBtMpRptStatus = status;
-+		_rtw_memcpy(GLBtcBtMpRptRsp, tmpBuf + 3, len);
-+		GLBtcBtMpRptRspSize = len;
-+
-+		break;
-+
-+	default:
-+		return;
-+	}
-+
-+	if ((GLBtcBtMpRptWiFiOK == _TRUE) && (GLBtcBtMpRptBTOK == _TRUE)) {
-+		GLBtcBtMpRptWait = _FALSE;
-+		_cancel_timer_ex(&GLBtcBtMpOperTimer);
-+		_rtw_up_sema(&GLBtcBtMpRptSema);
-+	}
-+}
-+
-+void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state)
-+{
-+	switch (state) {
-+	case BTCOEX_SUSPEND_STATE_SUSPEND:
-+		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP);
-+		break;
-+	case BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT:
-+		/* should switch to "#if 1" once all ICs' coex. revision are upgraded to support the KEEP_ANT case */
-+#if 0
-+		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP_KEEP_ANT);
-+#else
-+		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP);
-+		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP_KEEP_ANT);
-+#endif
-+		break;
-+	case BTCOEX_SUSPEND_STATE_RESUME:
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+		/* re-download FW after resume, inform WL FW port number */
-+		rtw_hal_set_wifi_btc_port_id_cmd(GLBtCoexist.Adapter);
-+#endif
-+		EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_WAKE_UP);
-+		break;
-+	}
-+}
-+
-+void hal_btcoex_HaltNotify(PADAPTER padapter, u8 do_halt)
-+{
-+	if (do_halt == 1)
-+		EXhalbtcoutsrc_halt_notify(&GLBtCoexist);
-+
-+	GLBtCoexist.bBinded = _FALSE;
-+	GLBtCoexist.Adapter = NULL;
-+}
-+
-+void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter)
-+{
-+	EXhalbtcoutsrc_SwitchBtTRxMask(&GLBtCoexist);
-+}
-+
-+void hal_btcoex_Hanlder(PADAPTER padapter)
-+{
-+	u32	bt_patch_ver;
-+
-+	EXhalbtcoutsrc_periodical(&GLBtCoexist);
-+
-+	if (GLBtCoexist.bt_info.bt_get_fw_ver == 0) {
-+		GLBtCoexist.btc_get(&GLBtCoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
-+		GLBtCoexist.bt_info.bt_get_fw_ver = bt_patch_ver;
-+	}
-+}
-+
-+s32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter)
-+{
-+	return (s32)GLBtCoexist.bt_info.reject_agg_pkt;
-+}
-+
-+s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter)
-+{
-+	return (s32)GLBtCoexist.bt_info.bt_ctrl_agg_buf_size;
-+}
-+
-+u32 hal_btcoex_GetAMPDUSize(PADAPTER padapter)
-+{
-+	return (u32)GLBtCoexist.bt_info.agg_buf_size;
-+}
-+
-+void hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual)
-+{
-+	GLBtCoexist.manual_control = bmanual;
-+}
-+
-+void hal_btcoex_set_policy_control(PADAPTER padapter, u8 btc_policy)
-+{
-+	switch (btc_policy) {
-+	case BTCOEX_POLICY_CONTROL_AUTO:
-+		GLBtCoexist.coex_sta.force_freerun = _FALSE;
-+		GLBtCoexist.coex_sta.force_tdd = _FALSE;
-+		break;
-+	case BTCOEX_POLICY_CONTROL_FORCE_FREERUN:
-+		GLBtCoexist.coex_sta.force_freerun = _TRUE;
-+		GLBtCoexist.coex_sta.force_tdd = _FALSE;
-+		break;
-+	case BTCOEX_POLICY_CONTROL_FORCE_TDMA:
-+		GLBtCoexist.coex_sta.force_freerun = _FALSE;
-+		GLBtCoexist.coex_sta.force_tdd = _TRUE;
-+		break;
-+	}
-+}
-+
-+u8 hal_btcoex_1Ant(PADAPTER padapter)
-+{
-+	if (hal_btcoex_IsBtExist(padapter) == _FALSE)
-+		return _FALSE;
-+
-+	if (GLBtCoexist.board_info.btdm_ant_num == 1)
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+u8 hal_btcoex_IsBtControlLps(PADAPTER padapter)
-+{
-+	if (GLBtCoexist.bdontenterLPS == _TRUE)
-+		return _TRUE;
-+	
-+	if (hal_btcoex_IsBtExist(padapter) == _FALSE)
-+		return _FALSE;
-+
-+	if (GLBtCoexist.bt_info.bt_disabled)
-+		return _FALSE;
-+
-+	if (GLBtCoexist.bt_info.bt_ctrl_lps)
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+u8 hal_btcoex_IsLpsOn(PADAPTER padapter)
-+{
-+	if (GLBtCoexist.bdontenterLPS == _TRUE)
-+		return _FALSE;
-+	
-+	if (hal_btcoex_IsBtExist(padapter) == _FALSE)
-+		return _FALSE;
-+
-+	if (GLBtCoexist.bt_info.bt_disabled)
-+		return _FALSE;
-+
-+	if (GLBtCoexist.bt_info.bt_lps_on)
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+u8 hal_btcoex_RpwmVal(PADAPTER padapter)
-+{
-+	return GLBtCoexist.bt_info.rpwm_val;
-+}
-+
-+u8 hal_btcoex_LpsVal(PADAPTER padapter)
-+{
-+	return GLBtCoexist.bt_info.lps_val;
-+}
-+
-+u32 hal_btcoex_GetRaMask(PADAPTER padapter)
-+{
-+	if (!hal_btcoex_IsBtExist(padapter))
-+		return 0;
-+
-+	if (GLBtCoexist.bt_info.bt_disabled)
-+		return 0;
-+
-+	/* Modify by YiWei , suggest by Cosa and Jenyu
-+	 * Remove the limit antenna number , because 2 antenna case (ex: 8192eu)also want to get BT coex report rate mask.
-+	 */
-+	/*if (GLBtCoexist.board_info.btdm_ant_num != 1)
-+		return 0;*/
-+
-+	return GLBtCoexist.bt_info.ra_mask;
-+}
-+
-+u8 hal_btcoex_query_reduced_wl_pwr_lvl(PADAPTER padapter)
-+{
-+	return GLBtCoexist.coex_dm.cur_wl_pwr_lvl;
-+}
-+
-+void hal_btcoex_set_reduced_wl_pwr_lvl(PADAPTER padapter, u8 val)
-+{
-+	GLBtCoexist.coex_dm.cur_wl_pwr_lvl = val;
-+}
-+
-+void hal_btcoex_do_reduce_wl_pwr_lvl(PADAPTER padapter)
-+{
-+	halbtcoutsrc_reduce_wl_tx_power(&GLBtCoexist, 0);
-+}
-+
-+void hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen)
-+{
-+
-+	_rtw_memcpy(GLBtCoexist.pwrModeVal, pCmdBuf, cmdLen);
-+}
-+
-+void hal_btcoex_DisplayBtCoexInfo(PADAPTER padapter, u8 *pbuf, u32 bufsize)
-+{
-+	PBTCDBGINFO pinfo;
-+
-+
-+	pinfo = &GLBtcDbgInfo;
-+	DBG_BT_INFO_INIT(pinfo, pbuf, bufsize);
-+	EXhalbtcoutsrc_DisplayBtCoexInfo(&GLBtCoexist);
-+	DBG_BT_INFO_INIT(pinfo, NULL, 0);
-+}
-+
-+void hal_btcoex_SetDBG(PADAPTER padapter, u32 *pDbgModule)
-+{
-+	u32 i;
-+
-+
-+	if (NULL == pDbgModule)
-+		return;
-+
-+	for (i = 0; i < COMP_MAX; i++)
-+		GLBtcDbgType[i] = pDbgModule[i];
-+}
-+
-+u32 hal_btcoex_GetDBG(PADAPTER padapter, u8 *pStrBuf, u32 bufSize)
-+{
-+	s32 count;
-+	u8 *pstr;
-+	u32 leftSize;
-+
-+
-+	if ((NULL == pStrBuf) || (0 == bufSize))
-+		return 0;
-+
-+	count = 0;
-+	pstr = pStrBuf;
-+	leftSize = bufSize;
-+	/*	RTW_INFO(FUNC_ADPT_FMT ": bufsize=%d\n", FUNC_ADPT_ARG(padapter), bufSize); */
-+
-+	count = rtw_sprintf(pstr, leftSize, "#define DBG\t%d\n", DBG);
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+
-+	count = rtw_sprintf(pstr, leftSize, "BTCOEX Debug Setting:\n");
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+
-+	count = rtw_sprintf(pstr, leftSize,
-+			    "COMP_COEX: 0x%08X\n\n",
-+			    GLBtcDbgType[COMP_COEX]);
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+
-+#if 0
-+	count = rtw_sprintf(pstr, leftSize, "INTERFACE Debug Setting Definition:\n");
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+	count = rtw_sprintf(pstr, leftSize, "\tbit[0]=%d for INTF_INIT\n",
-+		    GLBtcDbgType[BTC_MSG_INTERFACE] & INTF_INIT ? 1 : 0);
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+	count = rtw_sprintf(pstr, leftSize, "\tbit[2]=%d for INTF_NOTIFY\n\n",
-+		    GLBtcDbgType[BTC_MSG_INTERFACE] & INTF_NOTIFY ? 1 : 0);
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+
-+	count = rtw_sprintf(pstr, leftSize, "ALGORITHM Debug Setting Definition:\n");
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+	count = rtw_sprintf(pstr, leftSize, "\tbit[0]=%d for BT_RSSI_STATE\n",
-+		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_BT_RSSI_STATE ? 1 : 0);
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+	count = rtw_sprintf(pstr, leftSize, "\tbit[1]=%d for WIFI_RSSI_STATE\n",
-+		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_WIFI_RSSI_STATE ? 1 : 0);
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+	count = rtw_sprintf(pstr, leftSize, "\tbit[2]=%d for BT_MONITOR\n",
-+		    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_BT_MONITOR ? 1 : 0);
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+	count = rtw_sprintf(pstr, leftSize, "\tbit[3]=%d for TRACE\n",
-+		    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE ? 1 : 0);
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+	count = rtw_sprintf(pstr, leftSize, "\tbit[4]=%d for TRACE_FW\n",
-+		    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_FW ? 1 : 0);
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+	count = rtw_sprintf(pstr, leftSize, "\tbit[5]=%d for TRACE_FW_DETAIL\n",
-+		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_FW_DETAIL ? 1 : 0);
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+	count = rtw_sprintf(pstr, leftSize, "\tbit[6]=%d for TRACE_FW_EXEC\n",
-+		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_FW_EXEC ? 1 : 0);
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+	count = rtw_sprintf(pstr, leftSize, "\tbit[7]=%d for TRACE_SW\n",
-+		    GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_SW ? 1 : 0);
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+	count = rtw_sprintf(pstr, leftSize, "\tbit[8]=%d for TRACE_SW_DETAIL\n",
-+		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_SW_DETAIL ? 1 : 0);
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+	count = rtw_sprintf(pstr, leftSize, "\tbit[9]=%d for TRACE_SW_EXEC\n",
-+		GLBtcDbgType[BTC_MSG_ALGORITHM] & ALGO_TRACE_SW_EXEC ? 1 : 0);
-+	if ((count < 0) || (count >= leftSize))
-+		goto exit;
-+	pstr += count;
-+	leftSize -= count;
-+#endif
-+
-+exit:
-+	count = pstr - pStrBuf;
-+	/*	RTW_INFO(FUNC_ADPT_FMT ": usedsize=%d\n", FUNC_ADPT_ARG(padapter), count); */
-+
-+	return count;
-+}
-+
-+u8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER padapter)
-+{
-+	if (!hal_btcoex_IsBtExist(padapter))
-+		return _FALSE;
-+
-+	if (GLBtCoexist.bt_info.increase_scan_dev_num)
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+u8 hal_btcoex_IsBtLinkExist(PADAPTER padapter)
-+{
-+	if (GLBtCoexist.bt_link_info.bt_link_exist)
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+void hal_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer)
-+{
-+	EXhalbtcoutsrc_SetBtPatchVersion(btHciVer, btPatchVer);
-+}
-+
-+void hal_btcoex_SetHciVersion(PADAPTER padapter, u16 hciVersion)
-+{
-+	EXhalbtcoutsrc_SetHciVersion(hciVersion);
-+}
-+
-+void hal_btcoex_StackUpdateProfileInfo(void)
-+{
-+	EXhalbtcoutsrc_StackUpdateProfileInfo();
-+}
-+
-+void hal_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON)
-+{
-+	ex_halbtcoutsrc_pta_off_on_notify(&GLBtCoexist, bBTON);
-+}
-+
-+/*
-+ *	Description:
-+ *	Setting BT coex antenna isolation type .
-+ *	coex mechanisn/ spital stream/ best throughput
-+ *	anttype = 0	,	PSTDMA	/	2SS	/	0.5T	,	bad isolation , WiFi/BT ANT Distance<15cm , (<20dB) for 2,3 antenna
-+ *	anttype = 1	,	PSTDMA	/	1SS	/	0.5T	,	normal isolaiton , 50cm>WiFi/BT ANT Distance>15cm , (>20dB) for 2 antenna
-+ *	anttype = 2	,	TDMA	/	2SS	/	T ,		normal isolaiton , 50cm>WiFi/BT ANT Distance>15cm , (>20dB) for 3 antenna
-+ *	anttype = 3	,	no TDMA	/	1SS	/	0.5T	,	good isolation , WiFi/BT ANT Distance >50cm , (>40dB) for 2 antenna
-+ *	anttype = 4	,	no TDMA	/	2SS	/	T ,		good isolation , WiFi/BT ANT Distance >50cm , (>40dB) for 3 antenna
-+ *	wifi only throughput ~ T
-+ *	wifi/BT share one antenna with SPDT
-+ */
-+void hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+	PBTC_COEXIST	pBtCoexist = &GLBtCoexist;
-+
-+	/*RTW_INFO("####%s , anttype = %d  , %d\n" , __func__ , anttype , __LINE__); */
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+
-+	pHalData->bt_coexist.btAntisolation = anttype;
-+
-+	switch (pHalData->bt_coexist.btAntisolation) {
-+	case 0:
-+		pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_0;
-+		break;
-+	case 1:
-+		pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_1;
-+		break;
-+	case 2:
-+		pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_2;
-+		break;
-+	case 3:
-+		pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_3;
-+		break;
-+	case 4:
-+		pBtCoexist->board_info.ant_type = (u8)BTC_ANT_TYPE_4;
-+		break;
-+	}
-+
-+}
-+
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+int
-+hal_btcoex_ParseAntIsolationConfigFile(
-+	PADAPTER		Adapter,
-+	char			*buffer
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	u32	i = 0 , j = 0;
-+	char	*szLine , *ptmp;
-+	int rtStatus = _SUCCESS;
-+	char param_value_string[10];
-+	u8 param_value;
-+	u8 anttype = 4;
-+
-+	u8 ant_num = 3 , ant_distance = 50 , rfe_type = 1;
-+
-+	typedef struct ant_isolation {
-+		char *param_name;  /* antenna isolation config parameter name */
-+		u8 *value; /* antenna isolation config parameter value */
-+	} ANT_ISOLATION;
-+
-+	ANT_ISOLATION ant_isolation_param[] = {
-+		{"ANT_NUMBER" , &ant_num},
-+		{"ANT_DISTANCE" , &ant_distance},
-+		{"RFE_TYPE" , &rfe_type},
-+		{NULL , 0}
-+	};
-+
-+
-+
-+	/* RTW_INFO("===>Hal_ParseAntIsolationConfigFile()\n" ); */
-+
-+	ptmp = buffer;
-+	for (szLine = GetLineFromBuffer(ptmp) ; szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
-+		/* skip comment */
-+		if (IsCommentString(szLine))
-+			continue;
-+
-+		/* RTW_INFO("%s : szLine = %s , strlen(szLine) = %d\n" , __func__ , szLine , strlen(szLine));*/
-+		for (j = 0 ; ant_isolation_param[j].param_name != NULL ; j++) {
-+			if (strstr(szLine , ant_isolation_param[j].param_name) != NULL) {
-+				i = 0;
-+				while (i < strlen(szLine)) {
-+					if (szLine[i] != '"')
-+						++i;
-+					else {
-+						/* skip only has one " */
-+						if (strpbrk(szLine , "\"") == strrchr(szLine , '"')) {
-+							RTW_INFO("Fail to parse parameters , format error!\n");
-+							break;
-+						}
-+						_rtw_memset((void *)param_value_string , 0 , 10);
-+						if (!ParseQualifiedString(szLine , &i , param_value_string , '"' , '"')) {
-+							RTW_INFO("Fail to parse parameters\n");
-+							return _FAIL;
-+						} else if (!GetU1ByteIntegerFromStringInDecimal(param_value_string , ant_isolation_param[j].value))
-+							RTW_INFO("Fail to GetU1ByteIntegerFromStringInDecimal\n");
-+
-+						break;
-+					}
-+				}
-+			}
-+		}
-+	}
-+
-+	/* YiWei 20140716 , for BT coex antenna isolation control */
-+	/* rfe_type = 0 was SPDT , rfe_type = 1 was coupler */
-+	if (ant_num == 3 && ant_distance >= 50)
-+		anttype = 3;
-+	else if (ant_num == 2 && ant_distance >= 50 && rfe_type == 1)
-+		anttype = 2;
-+	else if (ant_num == 3 && ant_distance >= 15 && ant_distance < 50)
-+		anttype = 2;
-+	else if (ant_num == 2 && ant_distance >= 15 && ant_distance < 50 && rfe_type == 1)
-+		anttype = 2;
-+	else if ((ant_num == 2 && ant_distance < 15 && rfe_type == 1) || (ant_num == 3 && ant_distance < 15))
-+		anttype = 1;
-+	else if (ant_num == 2 && rfe_type == 0)
-+		anttype = 0;
-+	else
-+		anttype = 0;
-+
-+	hal_btcoex_SetAntIsolationType(Adapter, anttype);
-+
-+	RTW_INFO("%s : ant_num = %d\n" , __func__ , ant_num);
-+	RTW_INFO("%s : ant_distance = %d\n" , __func__ , ant_distance);
-+	RTW_INFO("%s : rfe_type = %d\n" , __func__ , rfe_type);
-+	/* RTW_INFO("<===Hal_ParseAntIsolationConfigFile()\n"); */
-+	return rtStatus;
-+}
-+
-+
-+int
-+hal_btcoex_AntIsolationConfig_ParaFile(
-+		PADAPTER	Adapter,
-+		char		*pFileName
-+)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
-+	int	rlen = 0 , rtStatus = _FAIL;
-+
-+	_rtw_memset(pHalData->para_file_buf , 0 , MAX_PARA_FILE_BUF_LEN);
-+
-+	rtw_get_phy_file_path(Adapter, pFileName);
-+	if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
-+		rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
-+		if (rlen > 0)
-+			rtStatus = _SUCCESS;
-+	}
-+
-+
-+	if (rtStatus == _SUCCESS) {
-+		/*RTW_INFO("%s(): read %s ok\n", __func__ , pFileName);*/
-+		rtStatus = hal_btcoex_ParseAntIsolationConfigFile(Adapter , pHalData->para_file_buf);
-+	} else
-+		RTW_INFO("%s(): No File %s, Load from *** Array!\n" , __func__ , pFileName);
-+
-+	return rtStatus;
-+}
-+#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
-+
-+u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data)
-+{
-+	u16 ret = 0;
-+
-+	halbtcoutsrc_LeaveLowPower(&GLBtCoexist);
-+
-+	ret = halbtcoutsrc_GetBtReg_with_status(&GLBtCoexist, type, addr, data);
-+
-+	halbtcoutsrc_NormalLowPower(&GLBtCoexist);
-+
-+	return ret;
-+}
-+
-+u16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val)
-+{
-+	u16 ret = 0;
-+
-+	halbtcoutsrc_LeaveLowPower(&GLBtCoexist);
-+
-+	ret = halbtcoutsrc_SetBtReg(&GLBtCoexist, type, addr, val);
-+
-+	halbtcoutsrc_NormalLowPower(&GLBtCoexist);
-+
-+	return ret;
-+}
-+
-+void hal_btcoex_set_rfe_type(u8 type)
-+{
-+	EXhalbtcoutsrc_set_rfe_type(type);
-+}
-+
-+#ifdef CONFIG_RF4CE_COEXIST
-+void hal_btcoex_set_rf4ce_link_state(u8 state)
-+{
-+	EXhalbtcoutsrc_set_rf4ce_link_state(state);
-+}
-+
-+u8 hal_btcoex_get_rf4ce_link_state(void)
-+{
-+	return EXhalbtcoutsrc_get_rf4ce_link_state();
-+}
-+#endif /* CONFIG_RF4CE_COEXIST */
-+
-+void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type)
-+{
-+	switch (band_type) {
-+	case BAND_ON_2_4G:
-+		if (under_scan)
-+			EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G);
-+		else
-+			EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G_NOFORSCAN);
-+		break;
-+	case BAND_ON_5G:
-+		EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_5G);
-+		break;
-+	default:
-+		RTW_INFO("[BTCOEX] unkown switch band type\n");
-+		break;
-+	}
-+}
-+
-+void hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length)
-+{
-+	EXhalbtcoutsrc_WlFwDbgInfoNotify(&GLBtCoexist, tmpBuf, length);
-+}
-+
-+void hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id)
-+{
-+	EXhalbtcoutsrc_rx_rate_change_notify(&GLBtCoexist, is_data_frame, EXhalbtcoutsrc_rate_id_to_btc_rate_id(rate_id));
-+}
-+
-+u16 hal_btcoex_btset_testode(PADAPTER padapter, u8 type)
-+{
-+	u16 ret = 0;
-+
-+	halbtcoutsrc_LeaveLowPower(&GLBtCoexist);
-+
-+	ret = halbtcoutsrc_setbttestmode(&GLBtCoexist, type);
-+
-+	halbtcoutsrc_NormalLowPower(&GLBtCoexist);
-+
-+	return ret;
-+}
-+
-+#endif /* CONFIG_BT_COEXIST */
-diff --git a/drivers/staging/rtl8723cs/hal/hal_btcoex_wifionly.c b/drivers/staging/rtl8723cs/hal/hal_btcoex_wifionly.c
-new file mode 100644
-index 000000000000..a9ef07f14a31
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_btcoex_wifionly.c
-@@ -0,0 +1,279 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include <hal_btcoex_wifionly.h>
-+
-+#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)
-+
-+#include "btc/mp_precomp.h"
-+
-+struct  wifi_only_cfg GLBtCoexistWifiOnly;
-+
-+void halwifionly_write1byte(void *pwifionlyContext, u32 RegAddr, u8 Data)
-+{
-+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
-+	PADAPTER		Adapter = pwifionlycfg->Adapter;
-+
-+	rtw_write8(Adapter, RegAddr, Data);
-+}
-+
-+void halwifionly_write2byte(void *pwifionlyContext, u32 RegAddr, u16 Data)
-+{
-+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
-+	PADAPTER		Adapter = pwifionlycfg->Adapter;
-+
-+	rtw_write16(Adapter, RegAddr, Data);
-+}
-+
-+void halwifionly_write4byte(void *pwifionlyContext, u32 RegAddr, u32 Data)
-+{
-+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
-+	PADAPTER		Adapter = pwifionlycfg->Adapter;
-+
-+	rtw_write32(Adapter, RegAddr, Data);
-+}
-+
-+u8 halwifionly_read1byte(void *pwifionlyContext, u32 RegAddr)
-+{
-+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
-+	PADAPTER		Adapter = pwifionlycfg->Adapter;
-+
-+	return rtw_read8(Adapter, RegAddr);
-+}
-+
-+u16 halwifionly_read2byte(void * pwifionlyContext, u32 RegAddr)
-+{
-+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
-+	PADAPTER		Adapter = pwifionlycfg->Adapter;
-+
-+	return rtw_read16(Adapter, RegAddr);
-+}
-+
-+u32 halwifionly_read4byte(void *pwifionlyContext, u32 RegAddr)
-+{
-+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
-+	PADAPTER		Adapter = pwifionlycfg->Adapter;
-+
-+	return rtw_read32(Adapter, RegAddr);
-+}
-+
-+void halwifionly_bitmaskwrite1byte(void *pwifionlyContext, u32 regAddr, u8 bitMask, u8 data)
-+{
-+	u8 originalValue, bitShift = 0;
-+	u8 i;
-+
-+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
-+	PADAPTER		Adapter = pwifionlycfg->Adapter;
-+
-+	if (bitMask != 0xff) {
-+		originalValue = rtw_read8(Adapter, regAddr);
-+		for (i = 0; i <= 7; i++) {
-+			if ((bitMask >> i) & 0x1)
-+				break;
-+		}
-+		bitShift = i;
-+		data = ((originalValue) & (~bitMask)) | (((data << bitShift)) & bitMask);
-+	}
-+	rtw_write8(Adapter, regAddr, data);
-+}
-+
-+void halwifionly_phy_set_rf_reg(void *pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
-+{
-+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
-+	PADAPTER		Adapter = pwifionlycfg->Adapter;
-+
-+	phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data);
-+}
-+
-+void halwifionly_phy_set_bb_reg(void *pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data)
-+{
-+	struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
-+	PADAPTER		Adapter = pwifionlycfg->Adapter;
-+
-+	phy_set_bb_reg(Adapter, RegAddr, BitMask, Data);
-+}
-+
-+void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	u8 is_5g = _FALSE;
-+
-+	if (pHalData->current_band_type == BAND_ON_5G)
-+		is_5g = _TRUE;
-+
-+	if (IS_HARDWARE_TYPE_8822B(padapter)) {
-+#ifdef CONFIG_RTL8822B
-+		ex_hal8822b_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(padapter))
-+		ex_hal8821c_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
-+#endif
-+
-+#ifdef CONFIG_RTL8822C
-+	else if (IS_HARDWARE_TYPE_8822C(padapter))
-+		ex_hal8822c_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
-+#endif
-+
-+#ifdef CONFIG_RTL8814B
-+	else if (IS_HARDWARE_TYPE_8814B(padapter))
-+		ex_hal8814b_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
-+#endif
-+
-+#ifdef CONFIG_RTL8723F
-+	else if (IS_HARDWARE_TYPE_8723F(padapter))
-+		ex_hal8723f_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
-+#endif
-+}
-+
-+void hal_btcoex_wifionly_scan_notify(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	u8 is_5g = _FALSE;
-+
-+	if (pHalData->current_band_type == BAND_ON_5G)
-+		is_5g = _TRUE;
-+
-+	if (IS_HARDWARE_TYPE_8822B(padapter)) {
-+#ifdef CONFIG_RTL8822B
-+		ex_hal8822b_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(padapter))
-+		ex_hal8821c_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
-+#endif
-+
-+#ifdef CONFIG_RTL8822C
-+	else if (IS_HARDWARE_TYPE_8822C(padapter))
-+		ex_hal8822c_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
-+#endif
-+
-+#ifdef CONFIG_RTL8814B
-+	else if (IS_HARDWARE_TYPE_8814B(padapter))
-+		ex_hal8814b_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
-+#endif
-+}
-+
-+void hal_btcoex_wifionly_connect_notify(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	u8 is_5g = _FALSE;
-+
-+	if (pHalData->current_band_type == BAND_ON_5G)
-+		is_5g = _TRUE;
-+
-+	if (IS_HARDWARE_TYPE_8822B(padapter)) {
-+#ifdef CONFIG_RTL8822B
-+		ex_hal8822b_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(padapter))
-+		ex_hal8821c_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
-+#endif
-+
-+#ifdef CONFIG_RTL8822C
-+	else if (IS_HARDWARE_TYPE_8822C(padapter))
-+		ex_hal8822c_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
-+#endif
-+
-+#ifdef CONFIG_RTL8814B
-+	else if (IS_HARDWARE_TYPE_8814B(padapter))
-+		ex_hal8814b_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
-+#endif
-+
-+#ifdef CONFIG_RTL8723F
-+	else if (IS_HARDWARE_TYPE_8723F(padapter))
-+		ex_hal8723f_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g);
-+#endif
-+}
-+
-+void hal_btcoex_wifionly_hw_config(PADAPTER padapter)
-+{
-+	struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly;
-+
-+	if (IS_HARDWARE_TYPE_8723B(padapter)) {
-+#ifdef CONFIG_RTL8723B
-+		ex_hal8723b_wifi_only_hw_config(pwifionlycfg);
-+#endif
-+	}
-+
-+#ifdef CONFIG_RTL8822B
-+	else if (IS_HARDWARE_TYPE_8822B(padapter))
-+		ex_hal8822b_wifi_only_hw_config(pwifionlycfg);
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	else if (IS_HARDWARE_TYPE_8821C(padapter))
-+		ex_hal8821c_wifi_only_hw_config(pwifionlycfg);
-+#endif
-+
-+#ifdef CONFIG_RTL8822C
-+	else if (IS_HARDWARE_TYPE_8822C(padapter))
-+		ex_hal8822c_wifi_only_hw_config(pwifionlycfg);
-+#endif
-+
-+#ifdef CONFIG_RTL8814B
-+	else if (IS_HARDWARE_TYPE_8814B(padapter))
-+		ex_hal8814b_wifi_only_hw_config(pwifionlycfg);
-+#endif
-+
-+#ifdef CONFIG_RTL8723F
-+	else if (IS_HARDWARE_TYPE_8723F(padapter))
-+		ex_hal8723f_wifi_only_hw_config(pwifionlycfg);
-+#endif
-+}
-+
-+void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter)
-+{
-+	struct wifi_only_cfg		*pwifionlycfg = &GLBtCoexistWifiOnly;
-+	struct wifi_only_haldata	*pwifionly_haldata = &pwifionlycfg->haldata_info;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	_rtw_memset(&GLBtCoexistWifiOnly, 0, sizeof(GLBtCoexistWifiOnly));
-+
-+	pwifionlycfg->Adapter = padapter;
-+
-+#ifdef CONFIG_PCI_HCI
-+	pwifionlycfg->chip_interface = WIFIONLY_INTF_PCI;
-+#elif defined(CONFIG_USB_HCI)
-+	pwifionlycfg->chip_interface = WIFIONLY_INTF_USB;
-+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	pwifionlycfg->chip_interface = WIFIONLY_INTF_SDIO;
-+#else
-+	pwifionlycfg->chip_interface = WIFIONLY_INTF_UNKNOWN;
-+#endif
-+
-+	pwifionly_haldata->customer_id = CUSTOMER_NORMAL;
-+}
-+
-+void hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter)
-+{
-+	struct wifi_only_cfg		*pwifionlycfg = &GLBtCoexistWifiOnly;
-+	struct wifi_only_haldata	*pwifionly_haldata = &pwifionlycfg->haldata_info;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	pwifionly_haldata->efuse_pg_antnum = pHalData->EEPROMBluetoothAntNum;
-+	pwifionly_haldata->efuse_pg_antpath = pHalData->ant_path;
-+	pwifionly_haldata->rfe_type = pHalData->rfe_type;
-+	pwifionly_haldata->ant_div_cfg = pHalData->AntDivCfg;
-+}
-+
-+#endif
-+
-diff --git a/drivers/staging/rtl8723cs/hal/hal_com.c b/drivers/staging/rtl8723cs/hal/hal_com.c
-new file mode 100644
-index 000000000000..a0f15958a778
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_com.c
-@@ -0,0 +1,16525 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _HAL_COM_C_
-+
-+#include <drv_types.h>
-+#include "hal_com_h2c.h"
-+
-+#include "hal_data.h"
-+
-+#ifdef RTW_HALMAC
-+#include "../../hal/hal_halmac.h"
-+#endif
-+
-+void rtw_dump_fw_info(void *sel, _adapter *adapter)
-+{
-+	HAL_DATA_TYPE	*hal_data = NULL;
-+
-+	if (!adapter)
-+		return;
-+
-+	hal_data = GET_HAL_DATA(adapter);
-+	if (hal_data->bFWReady)
-+		RTW_PRINT_SEL(sel, "FW VER -%d.%d\n", hal_data->firmware_version, hal_data->firmware_sub_version);
-+	else
-+		RTW_PRINT_SEL(sel, "FW not ready\n");
-+}
-+
-+bool rsvd_page_cache_update_all(struct rsvd_page_cache_t *cache, u8 loc
-+	, u8 txdesc_len, u32 page_size, u8 *info, u32 info_len)
-+{
-+	u8 page_num;
-+	bool modified = 0;
-+	bool loc_mod = 0, size_mod = 0, page_num_mod = 0;
-+
-+	page_num = info_len ? (u8)PageNum(txdesc_len + info_len, page_size) : 0;
-+	if (!info_len)
-+		loc = 0;
-+
-+	if (cache->loc != loc) {
-+		RTW_INFO("%s %s loc change (%u -> %u)\n"
-+			, __func__, cache->name, cache->loc, loc);
-+		loc_mod = 1;
-+	}
-+	if (cache->size != info_len) {
-+		RTW_INFO("%s %s size change (%u -> %u)\n"
-+			, __func__, cache->name, cache->size, info_len);
-+		size_mod = 1;
-+	}
-+	if (cache->page_num != page_num) {
-+		RTW_INFO("%s %s page_num change (%u -> %u)\n"
-+			, __func__, cache->name, cache->page_num, page_num);
-+		page_num_mod = 1;
-+	}
-+
-+	if (info && info_len) {
-+		if (cache->data) {
-+			if (cache->size == info_len) {
-+				if (_rtw_memcmp(cache->data, info, info_len) != _TRUE) {
-+					RTW_INFO("%s %s data change\n", __func__, cache->name);
-+					modified = 1;
-+				}
-+			} else
-+				rsvd_page_cache_free_data(cache);
-+		}
-+
-+		if (!cache->data) {
-+			cache->data = rtw_malloc(info_len);
-+			if (!cache->data) {
-+				RTW_ERR("%s %s alloc data with size(%u) fail\n"
-+					, __func__, cache->name, info_len);
-+				rtw_warn_on(1);
-+			} else {
-+				RTW_INFO("%s %s alloc data with size(%u)\n"
-+					, __func__, cache->name, info_len);
-+			}
-+			modified = 1;
-+		}
-+
-+		if (cache->data && modified)
-+			_rtw_memcpy(cache->data, info, info_len);
-+	} else {
-+		if (cache->data && size_mod)
-+			rsvd_page_cache_free_data(cache);
-+	}
-+
-+	cache->loc = loc;
-+	cache->page_num = page_num;
-+	cache->size = info_len;
-+
-+	return modified | loc_mod | size_mod | page_num_mod;
-+}
-+
-+bool rsvd_page_cache_update_data(struct rsvd_page_cache_t *cache, u8 *info, u32 info_len)
-+{
-+	bool modified = 0;
-+
-+	if (!info || !info_len) {
-+		RTW_WARN("%s %s invalid input(info:%p, info_len:%u)\n"
-+			, __func__, cache->name, info, info_len);
-+		goto exit;
-+	}
-+
-+	if (!cache->loc || !cache->page_num || !cache->size) {
-+		RTW_ERR("%s %s layout not ready(loc:%u, page_num:%u, size:%u)\n"
-+			, __func__, cache->name, cache->loc, cache->page_num, cache->size);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (cache->size != info_len) {
-+		RTW_ERR("%s %s size(%u) differ with info_len(%u)\n"
-+			, __func__, cache->name, cache->size, info_len);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (!cache->data) {
-+		cache->data = rtw_zmalloc(cache->size);
-+		if (!cache->data) {
-+			RTW_ERR("%s %s alloc data with size(%u) fail\n"
-+				, __func__, cache->name, cache->size);
-+			rtw_warn_on(1);
-+			goto exit;
-+		} else {
-+			RTW_INFO("%s %s alloc data with size(%u)\n"
-+				, __func__, cache->name, info_len);
-+		}
-+		modified = 1;
-+	}
-+
-+	if (_rtw_memcmp(cache->data, info, cache->size) == _FALSE) {
-+		RTW_INFO("%s %s data change\n", __func__, cache->name);
-+		_rtw_memcpy(cache->data, info, cache->size);
-+		modified = 1;
-+	}
-+
-+exit:
-+	return modified;
-+}
-+
-+void rsvd_page_cache_free_data(struct rsvd_page_cache_t *cache)
-+{
-+	if (cache->data) {
-+		rtw_mfree(cache->data, cache->size);
-+		cache->data = NULL;
-+	}
-+}
-+
-+void rsvd_page_cache_free(struct rsvd_page_cache_t *cache)
-+{
-+	cache->loc = 0;
-+	cache->page_num = 0;
-+	rsvd_page_cache_free_data(cache);
-+	cache->size = 0;
-+}
-+
-+/* #define CONFIG_GTK_OL_DBG */
-+
-+/*#define DBG_SEC_CAM_MOVE*/
-+#ifdef DBG_SEC_CAM_MOVE
-+void rtw_hal_move_sta_gk_to_dk(_adapter *adapter)
-+{
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	int cam_id, index = 0;
-+	u8 *addr = NULL;
-+
-+	if (!MLME_IS_STA(adapter))
-+		return;
-+
-+	addr = get_bssid(pmlmepriv);
-+
-+	if (addr == NULL) {
-+		RTW_INFO("%s: get bssid MAC addr fail!!\n", __func__);
-+		return;
-+	}
-+
-+	rtw_clean_dk_section(adapter);
-+
-+	do {
-+		cam_id = rtw_camid_search(adapter, addr, index, 1);
-+
-+		if (cam_id == -1)
-+			RTW_INFO("%s: cam_id: %d, key_id:%d\n", __func__, cam_id, index);
-+		else
-+			rtw_sec_cam_swap(adapter, cam_id, index);
-+
-+		index++;
-+	} while (index < 4);
-+
-+}
-+
-+void rtw_hal_read_sta_dk_key(_adapter *adapter, u8 key_id)
-+{
-+	struct security_priv *psecuritypriv = &adapter->securitypriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	_irqL irqL;
-+	u8 get_key[16];
-+
-+	_rtw_memset(get_key, 0, sizeof(get_key));
-+
-+	if (key_id > 4) {
-+		RTW_INFO("%s [ERROR] gtk_keyindex:%d invalid\n", __func__, key_id);
-+		rtw_warn_on(1);
-+		return;
-+	}
-+	rtw_sec_read_cam_ent(adapter, key_id, NULL, NULL, get_key);
-+
-+	/*update key into related sw variable*/
-+	_enter_critical_bh(&cam_ctl->lock, &irqL);
-+	if (_rtw_camid_is_gk(adapter, key_id)) {
-+		RTW_INFO("[HW KEY] -Key-id:%d "KEY_FMT"\n", key_id, KEY_ARG(get_key));
-+		RTW_INFO("[cam_cache KEY] - Key-id:%d "KEY_FMT"\n", key_id, KEY_ARG(&dvobj->cam_cache[key_id].key));
-+	}
-+	_exit_critical_bh(&cam_ctl->lock, &irqL);
-+
-+}
-+#endif
-+
-+
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+	char	rtw_phy_para_file_path[PATH_LENGTH_MAX];
-+#endif
-+
-+void dump_chip_info(HAL_VERSION	ChipVersion)
-+{
-+	int cnt = 0;
-+	u8 buf[128] = {0};
-+
-+	if (IS_8188E(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188E_");
-+	else if (IS_8188F(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188F_");
-+	else if (IS_8188GTV(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188GTV_");
-+	else if (IS_8812_SERIES(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8812_");
-+	else if (IS_8192E(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8192E_");
-+	else if (IS_8821_SERIES(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8821_");
-+	else if (IS_8723B_SERIES(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8723B_");
-+	else if (IS_8703B_SERIES(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8703B_");
-+	else if (IS_8723D_SERIES(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8723D_");
-+	else if (IS_8814A_SERIES(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8814A_");
-+	else if (IS_8822B_SERIES(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8822B_");
-+	else if (IS_8821C_SERIES(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8821C_");
-+	else if (IS_8710B_SERIES(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8710B_");
-+	else if (IS_8192F_SERIES(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8192F_");
-+	else if (IS_8822C_SERIES(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8822C_");
-+	else if (IS_8814B_SERIES(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8814B_");
-+	else if (IS_8723F_SERIES(ChipVersion))
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8723F_");
-+	else
-+		cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_UNKNOWN_");
-+
-+	cnt += sprintf((buf + cnt), "%s", IS_NORMAL_CHIP(ChipVersion) ? "" : "T_");
-+	
-+	if (IS_CHIP_VENDOR_TSMC(ChipVersion))
-+		cnt += sprintf((buf + cnt), "%s", "T");
-+	else if (IS_CHIP_VENDOR_UMC(ChipVersion))
-+		cnt += sprintf((buf + cnt), "%s", "U");
-+	else if (IS_CHIP_VENDOR_SMIC(ChipVersion))
-+		cnt += sprintf((buf + cnt), "%s", "S");
-+
-+	if (IS_A_CUT(ChipVersion))
-+		cnt += sprintf((buf + cnt), "1_");
-+	else if (IS_B_CUT(ChipVersion))
-+		cnt += sprintf((buf + cnt), "2_");
-+	else if (IS_C_CUT(ChipVersion))
-+		cnt += sprintf((buf + cnt), "3_");
-+	else if (IS_D_CUT(ChipVersion))
-+		cnt += sprintf((buf + cnt), "4_");
-+	else if (IS_E_CUT(ChipVersion))
-+		cnt += sprintf((buf + cnt), "5_");
-+	else if (IS_F_CUT(ChipVersion))
-+		cnt += sprintf((buf + cnt), "6_");
-+	else if (IS_I_CUT(ChipVersion))
-+		cnt += sprintf((buf + cnt), "9_");
-+	else if (IS_J_CUT(ChipVersion))
-+		cnt += sprintf((buf + cnt), "10_");
-+	else if (IS_K_CUT(ChipVersion))
-+		cnt += sprintf((buf + cnt), "11_");
-+	else
-+		cnt += sprintf((buf + cnt), "UNKNOWN_Cv(%d)_", ChipVersion.CUTVersion);
-+
-+	if (IS_1T1R(ChipVersion))
-+		cnt += sprintf((buf + cnt), "1T1R_");
-+	else if (IS_1T2R(ChipVersion))
-+		cnt += sprintf((buf + cnt), "1T2R_");
-+	else if (IS_2T2R(ChipVersion))
-+		cnt += sprintf((buf + cnt), "2T2R_");
-+	else if (IS_3T3R(ChipVersion))
-+		cnt += sprintf((buf + cnt), "3T3R_");
-+	else if (IS_3T4R(ChipVersion))
-+		cnt += sprintf((buf + cnt), "3T4R_");
-+	else if (IS_4T4R(ChipVersion))
-+		cnt += sprintf((buf + cnt), "4T4R_");
-+	else
-+		cnt += sprintf((buf + cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType);
-+
-+	cnt += sprintf((buf + cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
-+
-+	RTW_INFO("%s", buf);
-+}
-+
-+u8 rtw_hal_get_port(_adapter *adapter)
-+{
-+	u8 hw_port = get_hw_port(adapter);
-+#ifdef CONFIG_CLIENT_PORT_CFG
-+	u8 clt_port = get_clt_port(adapter);
-+
-+	if (clt_port)
-+		hw_port = clt_port;
-+
-+#ifdef DBG_HW_PORT
-+	if (MLME_IS_STA(adapter) && (adapter->client_id != MAX_CLIENT_PORT_NUM)) {
-+		if(hw_port == CLT_PORT_INVALID) {
-+			RTW_ERR(ADPT_FMT" @@@@@ Client port == 0 @@@@@\n", ADPT_ARG(adapter));
-+			rtw_warn_on(1);
-+		}
-+	}
-+	#ifdef CONFIG_AP_MODE
-+	else if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
-+		if (hw_port != HW_PORT0) {
-+			RTW_ERR(ADPT_FMT" @@@@@ AP / MESH port != 0 @@@@@\n", ADPT_ARG(adapter));
-+			rtw_warn_on(1);
-+		}
-+	}
-+	#endif
-+	if (0)
-+		RTW_INFO(ADPT_FMT" - HP:%d,CP:%d\n", ADPT_ARG(adapter), get_hw_port(adapter), get_clt_port(adapter));
-+#endif /*DBG_HW_PORT*/
-+
-+#endif/*CONFIG_CLIENT_PORT_CFG*/
-+
-+	return hw_port;
-+}
-+
-+#define	EEPROM_CHANNEL_PLAN_BY_HW_MASK	0x80
-+
-+/*
-+ * Description:
-+ *	Use hardware(efuse), driver parameter(registry) and default channel plan
-+ *	to decide which one should be used.
-+ *
-+ * Parameters:
-+ *	padapter			pointer of adapter
-+ *	hw_alpha2		country code from HW (efuse/eeprom/mapfile)
-+ *	hw_chplan		channel plan from HW (efuse/eeprom/mapfile)
-+ *						BIT[7] software configure mode; 0:Enable, 1:disable
-+ *						BIT[6:0] Channel Plan
-+ *	sw_alpha2		country code from HW (registry/module param)
-+ *	sw_chplan		channel plan from SW (registry/module param)
-+ *	AutoLoadFail		efuse autoload fail or not
-+ *
-+ */
-+void hal_com_config_channel_plan(
-+		PADAPTER padapter,
-+		char *hw_alpha2,
-+		u8 hw_chplan,
-+		char *sw_alpha2,
-+		u8 sw_chplan,
-+		BOOLEAN AutoLoadFail
-+)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	PHAL_DATA_TYPE	pHalData;
-+	u8 force_hw_chplan = _FALSE;
-+	int chplan = -1;
-+	const struct country_chplan *country_ent = NULL, *ent;
-+	u8 def_chplan = 0x7F; /* Realtek define,  used when HW, SW both invalid */
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	/* treat 0xFF as invalid value, bypass hw_chplan & force_hw_chplan parsing */
-+	if (hw_chplan == 0xFF)
-+		goto chk_hw_country_code;
-+
-+	if (AutoLoadFail == _TRUE)
-+		goto chk_sw_config;
-+
-+#ifndef CONFIG_FORCE_SW_CHANNEL_PLAN
-+	if (hw_chplan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
-+		force_hw_chplan = _TRUE;
-+#endif
-+
-+	hw_chplan &= (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
-+
-+chk_hw_country_code:
-+	if (hw_alpha2 && !IS_ALPHA2_NO_SPECIFIED(hw_alpha2)) {
-+		ent = rtw_get_chplan_from_country(hw_alpha2);
-+		if (ent) {
-+			/* get chplan from hw country code, by pass hw chplan setting */
-+			country_ent = ent;
-+			chplan = ent->chplan;
-+			goto chk_sw_config;
-+		} else
-+			RTW_PRINT("%s unsupported hw_alpha2:\"%c%c\"\n", __func__, hw_alpha2[0], hw_alpha2[1]);
-+	}
-+
-+	if (rtw_is_channel_plan_valid(hw_chplan))
-+		chplan = hw_chplan;
-+	else if (force_hw_chplan == _TRUE) {
-+		RTW_PRINT("%s unsupported hw_chplan:0x%02X\n", __func__, hw_chplan);
-+		/* hw infomaton invalid, refer to sw information */
-+		force_hw_chplan = _FALSE;
-+	}
-+
-+chk_sw_config:
-+	if (force_hw_chplan == _TRUE)
-+		goto done;
-+
-+	if (sw_alpha2 && !IS_ALPHA2_NO_SPECIFIED(sw_alpha2)) {
-+		ent = rtw_get_chplan_from_country(sw_alpha2);
-+		if (ent) {
-+			/* get chplan from sw country code, by pass sw chplan setting */
-+			country_ent = ent;
-+			chplan = ent->chplan;
-+			goto done;
-+		} else
-+			RTW_PRINT("%s unsupported sw_alpha2:\"%c%c\"\n", __func__, sw_alpha2[0], sw_alpha2[1]);
-+	}
-+
-+	if (rtw_is_channel_plan_valid(sw_chplan)) {
-+		/* cancel hw_alpha2 because chplan is specified by sw_chplan*/
-+		country_ent = NULL;
-+		chplan = sw_chplan;
-+	} else if (sw_chplan != RTW_CHPLAN_UNSPECIFIED)
-+		RTW_PRINT("%s unsupported sw_chplan:0x%02X\n", __func__, sw_chplan);
-+
-+done:
-+	if (chplan == -1) {
-+		RTW_PRINT("%s use def_chplan:0x%02X\n", __func__, def_chplan);
-+		chplan = def_chplan;
-+	} else if (country_ent) {
-+		RTW_PRINT("%s country code:\"%c%c\" with chplan:0x%02X\n", __func__
-+			, country_ent->alpha2[0], country_ent->alpha2[1], country_ent->chplan);
-+	} else
-+		RTW_PRINT("%s chplan:0x%02X\n", __func__, chplan);
-+
-+	rfctl->country_ent = country_ent;
-+	rfctl->ChannelPlan = chplan;
-+	pHalData->bDisableSWChannelPlan = force_hw_chplan;
-+}
-+
-+BOOLEAN
-+HAL_IsLegalChannel(
-+		PADAPTER	Adapter,
-+		u32			Channel
-+)
-+{
-+	BOOLEAN bLegalChannel = _TRUE;
-+
-+	if (Channel > 14) {
-+		if (is_supported_5g(Adapter->registrypriv.wireless_mode) == _FALSE) {
-+			bLegalChannel = _FALSE;
-+			RTW_INFO("Channel > 14 but wireless_mode do not support 5G\n");
-+		}
-+	} else if ((Channel <= 14) && (Channel >= 1)) {
-+		if (IsSupported24G(Adapter->registrypriv.wireless_mode) == _FALSE) {
-+			bLegalChannel = _FALSE;
-+			RTW_INFO("(Channel <= 14) && (Channel >=1) but wireless_mode do not support 2.4G\n");
-+		}
-+	} else {
-+		bLegalChannel = _FALSE;
-+		RTW_INFO("Channel is Invalid !!!\n");
-+	}
-+
-+	return bLegalChannel;
-+}
-+
-+static const u8 _MRateToHwRate[MGN_UNKNOWN] = {
-+	[MGN_1M] = DESC_RATE1M,
-+	[MGN_2M] = DESC_RATE2M,
-+	[MGN_5_5M] = DESC_RATE5_5M,
-+	[MGN_11M] = DESC_RATE11M,
-+	[MGN_6M] = DESC_RATE6M,
-+	[MGN_9M] = DESC_RATE9M,
-+	[MGN_12M] = DESC_RATE12M,
-+	[MGN_18M] = DESC_RATE18M,
-+	[MGN_24M] = DESC_RATE24M,
-+	[MGN_36M] = DESC_RATE36M,
-+	[MGN_48M] = DESC_RATE48M,
-+	[MGN_54M] = DESC_RATE54M,
-+	[MGN_MCS0] = DESC_RATEMCS0,
-+	[MGN_MCS1] = DESC_RATEMCS1,
-+	[MGN_MCS2] = DESC_RATEMCS2,
-+	[MGN_MCS3] = DESC_RATEMCS3,
-+	[MGN_MCS4] = DESC_RATEMCS4,
-+	[MGN_MCS5] = DESC_RATEMCS5,
-+	[MGN_MCS6] = DESC_RATEMCS6,
-+	[MGN_MCS7] = DESC_RATEMCS7,
-+	[MGN_MCS8] = DESC_RATEMCS8,
-+	[MGN_MCS9] = DESC_RATEMCS9,
-+	[MGN_MCS10] = DESC_RATEMCS10,
-+	[MGN_MCS11] = DESC_RATEMCS11,
-+	[MGN_MCS12] = DESC_RATEMCS12,
-+	[MGN_MCS13] = DESC_RATEMCS13,
-+	[MGN_MCS14] = DESC_RATEMCS14,
-+	[MGN_MCS15] = DESC_RATEMCS15,
-+	[MGN_MCS16] = DESC_RATEMCS16,
-+	[MGN_MCS17] = DESC_RATEMCS17,
-+	[MGN_MCS18] = DESC_RATEMCS18,
-+	[MGN_MCS19] = DESC_RATEMCS19,
-+	[MGN_MCS20] = DESC_RATEMCS20,
-+	[MGN_MCS21] = DESC_RATEMCS21,
-+	[MGN_MCS22] = DESC_RATEMCS22,
-+	[MGN_MCS23] = DESC_RATEMCS23,
-+	[MGN_MCS24] = DESC_RATEMCS24,
-+	[MGN_MCS25] = DESC_RATEMCS25,
-+	[MGN_MCS26] = DESC_RATEMCS26,
-+	[MGN_MCS27] = DESC_RATEMCS27,
-+	[MGN_MCS28] = DESC_RATEMCS28,
-+	[MGN_MCS29] = DESC_RATEMCS29,
-+	[MGN_MCS30] = DESC_RATEMCS30,
-+	[MGN_MCS31] = DESC_RATEMCS31,
-+	[MGN_VHT1SS_MCS0] = DESC_RATEVHTSS1MCS0,
-+	[MGN_VHT1SS_MCS1] = DESC_RATEVHTSS1MCS1,
-+	[MGN_VHT1SS_MCS2] = DESC_RATEVHTSS1MCS2,
-+	[MGN_VHT1SS_MCS3] = DESC_RATEVHTSS1MCS3,
-+	[MGN_VHT1SS_MCS4] = DESC_RATEVHTSS1MCS4,
-+	[MGN_VHT1SS_MCS5] = DESC_RATEVHTSS1MCS5,
-+	[MGN_VHT1SS_MCS6] = DESC_RATEVHTSS1MCS6,
-+	[MGN_VHT1SS_MCS7] = DESC_RATEVHTSS1MCS7,
-+	[MGN_VHT1SS_MCS8] = DESC_RATEVHTSS1MCS8,
-+	[MGN_VHT1SS_MCS9] = DESC_RATEVHTSS1MCS9,
-+	[MGN_VHT2SS_MCS0] = DESC_RATEVHTSS2MCS0,
-+	[MGN_VHT2SS_MCS1] = DESC_RATEVHTSS2MCS1,
-+	[MGN_VHT2SS_MCS2] = DESC_RATEVHTSS2MCS2,
-+	[MGN_VHT2SS_MCS3] = DESC_RATEVHTSS2MCS3,
-+	[MGN_VHT2SS_MCS4] = DESC_RATEVHTSS2MCS4,
-+	[MGN_VHT2SS_MCS5] = DESC_RATEVHTSS2MCS5,
-+	[MGN_VHT2SS_MCS6] = DESC_RATEVHTSS2MCS6,
-+	[MGN_VHT2SS_MCS7] = DESC_RATEVHTSS2MCS7,
-+	[MGN_VHT2SS_MCS8] = DESC_RATEVHTSS2MCS8,
-+	[MGN_VHT2SS_MCS9] = DESC_RATEVHTSS2MCS9,
-+	[MGN_VHT3SS_MCS0] = DESC_RATEVHTSS3MCS0,
-+	[MGN_VHT3SS_MCS1] = DESC_RATEVHTSS3MCS1,
-+	[MGN_VHT3SS_MCS2] = DESC_RATEVHTSS3MCS2,
-+	[MGN_VHT3SS_MCS3] = DESC_RATEVHTSS3MCS3,
-+	[MGN_VHT3SS_MCS4] = DESC_RATEVHTSS3MCS4,
-+	[MGN_VHT3SS_MCS5] = DESC_RATEVHTSS3MCS5,
-+	[MGN_VHT3SS_MCS6] = DESC_RATEVHTSS3MCS6,
-+	[MGN_VHT3SS_MCS7] = DESC_RATEVHTSS3MCS7,
-+	[MGN_VHT3SS_MCS8] = DESC_RATEVHTSS3MCS8,
-+	[MGN_VHT3SS_MCS9] = DESC_RATEVHTSS3MCS9,
-+	[MGN_VHT4SS_MCS0] = DESC_RATEVHTSS4MCS0,
-+	[MGN_VHT4SS_MCS1] = DESC_RATEVHTSS4MCS1,
-+	[MGN_VHT4SS_MCS2] = DESC_RATEVHTSS4MCS2,
-+	[MGN_VHT4SS_MCS3] = DESC_RATEVHTSS4MCS3,
-+	[MGN_VHT4SS_MCS4] = DESC_RATEVHTSS4MCS4,
-+	[MGN_VHT4SS_MCS5] = DESC_RATEVHTSS4MCS5,
-+	[MGN_VHT4SS_MCS6] = DESC_RATEVHTSS4MCS6,
-+	[MGN_VHT4SS_MCS7] = DESC_RATEVHTSS4MCS7,
-+	[MGN_VHT4SS_MCS8] = DESC_RATEVHTSS4MCS8,
-+	[MGN_VHT4SS_MCS9] = DESC_RATEVHTSS4MCS9,
-+};
-+
-+u8 MRateToHwRate(enum MGN_RATE rate)
-+{
-+	u8 hw_rate = DESC_RATE1M; /* default value, also is zero */
-+
-+	if (rate < MGN_UNKNOWN)
-+		hw_rate = _MRateToHwRate[rate];
-+
-+	if (rate != MGN_1M && hw_rate == DESC_RATE1M)
-+		RTW_WARN("Invalid rate 0x%x in %s\n", rate, __FUNCTION__);
-+
-+	return hw_rate;
-+}
-+
-+const char * const _HDATA_RATE[DESC_RATE_NUM + 1] = {
-+	[DESC_RATE1M] = "CCK_1M",
-+	[DESC_RATE2M] = "CCK_2M",
-+	[DESC_RATE5_5M] = "CCK5_5M",
-+	[DESC_RATE11M] = "CCK_11M",
-+	[DESC_RATE6M] = "OFDM_6M",
-+	[DESC_RATE9M] = "OFDM_9M",
-+	[DESC_RATE12M] = "OFDM_12M",
-+	[DESC_RATE18M] = "OFDM_18M",
-+	[DESC_RATE24M] = "OFDM_24M",
-+	[DESC_RATE36M] = "OFDM_36M",
-+	[DESC_RATE48M] = "OFDM_48M",
-+	[DESC_RATE54M] = "OFDM_54M",
-+	[DESC_RATEMCS0] = "MCS0",
-+	[DESC_RATEMCS1] = "MCS1",
-+	[DESC_RATEMCS2] = "MCS2",
-+	[DESC_RATEMCS3] = "MCS3",
-+	[DESC_RATEMCS4] = "MCS4",
-+	[DESC_RATEMCS5] = "MCS5",
-+	[DESC_RATEMCS6] = "MCS6",
-+	[DESC_RATEMCS7] = "MCS7",
-+	[DESC_RATEMCS8] = "MCS8",
-+	[DESC_RATEMCS9] = "MCS9",
-+	[DESC_RATEMCS10] = "MCS10",
-+	[DESC_RATEMCS11] = "MCS11",
-+	[DESC_RATEMCS12] = "MCS12",
-+	[DESC_RATEMCS13] = "MCS13",
-+	[DESC_RATEMCS14] = "MCS14",
-+	[DESC_RATEMCS15] = "MCS15",
-+	[DESC_RATEMCS16] = "MCS16",
-+	[DESC_RATEMCS17] = "MCS17",
-+	[DESC_RATEMCS18] = "MCS18",
-+	[DESC_RATEMCS19] = "MCS19",
-+	[DESC_RATEMCS20] = "MCS20",
-+	[DESC_RATEMCS21] = "MCS21",
-+	[DESC_RATEMCS22] = "MCS22",
-+	[DESC_RATEMCS23] = "MCS23",
-+	[DESC_RATEMCS24] = "MCS24",
-+	[DESC_RATEMCS25] = "MCS25",
-+	[DESC_RATEMCS26] = "MCS26",
-+	[DESC_RATEMCS27] = "MCS27",
-+	[DESC_RATEMCS28] = "MCS28",
-+	[DESC_RATEMCS29] = "MCS29",
-+	[DESC_RATEMCS30] = "MCS30",
-+	[DESC_RATEMCS31] = "MCS31",
-+	[DESC_RATEVHTSS1MCS0] = "VHT1SMCS0",
-+	[DESC_RATEVHTSS1MCS1] = "VHT1SMCS1",
-+	[DESC_RATEVHTSS1MCS2] = "VHT1SMCS2",
-+	[DESC_RATEVHTSS1MCS3] = "VHT1SMCS3",
-+	[DESC_RATEVHTSS1MCS4] = "VHT1SMCS4",
-+	[DESC_RATEVHTSS1MCS5] = "VHT1SMCS5",
-+	[DESC_RATEVHTSS1MCS6] = "VHT1SMCS6",
-+	[DESC_RATEVHTSS1MCS7] = "VHT1SMCS7",
-+	[DESC_RATEVHTSS1MCS8] = "VHT1SMCS8",
-+	[DESC_RATEVHTSS1MCS9] = "VHT1SMCS9",
-+	[DESC_RATEVHTSS2MCS0] = "VHT2SMCS0",
-+	[DESC_RATEVHTSS2MCS1] = "VHT2SMCS1",
-+	[DESC_RATEVHTSS2MCS2] = "VHT2SMCS2",
-+	[DESC_RATEVHTSS2MCS3] = "VHT2SMCS3",
-+	[DESC_RATEVHTSS2MCS4] = "VHT2SMCS4",
-+	[DESC_RATEVHTSS2MCS5] = "VHT2SMCS5",
-+	[DESC_RATEVHTSS2MCS6] = "VHT2SMCS6",
-+	[DESC_RATEVHTSS2MCS7] = "VHT2SMCS7",
-+	[DESC_RATEVHTSS2MCS8] = "VHT2SMCS8",
-+	[DESC_RATEVHTSS2MCS9] = "VHT2SMCS9",
-+	[DESC_RATEVHTSS3MCS0] = "VHT3SMCS0",
-+	[DESC_RATEVHTSS3MCS1] = "VHT3SMCS1",
-+	[DESC_RATEVHTSS3MCS2] = "VHT3SMCS2",
-+	[DESC_RATEVHTSS3MCS3] = "VHT3SMCS3",
-+	[DESC_RATEVHTSS3MCS4] = "VHT3SMCS4",
-+	[DESC_RATEVHTSS3MCS5] = "VHT3SMCS5",
-+	[DESC_RATEVHTSS3MCS6] = "VHT3SMCS6",
-+	[DESC_RATEVHTSS3MCS7] = "VHT3SMCS7",
-+	[DESC_RATEVHTSS3MCS8] = "VHT3SMCS8",
-+	[DESC_RATEVHTSS3MCS9] = "VHT3SMCS9",
-+	[DESC_RATEVHTSS4MCS0] = "VHT4SMCS0",
-+	[DESC_RATEVHTSS4MCS1] = "VHT4SMCS1",
-+	[DESC_RATEVHTSS4MCS2] = "VHT4SMCS2",
-+	[DESC_RATEVHTSS4MCS3] = "VHT4SMCS3",
-+	[DESC_RATEVHTSS4MCS4] = "VHT4SMCS4",
-+	[DESC_RATEVHTSS4MCS5] = "VHT4SMCS5",
-+	[DESC_RATEVHTSS4MCS6] = "VHT4SMCS6",
-+	[DESC_RATEVHTSS4MCS7] = "VHT4SMCS7",
-+	[DESC_RATEVHTSS4MCS8] = "VHT4SMCS8",
-+	[DESC_RATEVHTSS4MCS9] = "VHT4SMCS9",
-+	[DESC_RATE_NUM] = "UNKNOWN",
-+};
-+
-+static const u8 _hw_rate_to_m_rate[DESC_RATE_NUM] = {
-+	[DESC_RATE1M] = MGN_1M,
-+	[DESC_RATE2M] = MGN_2M,
-+	[DESC_RATE5_5M] = MGN_5_5M,
-+	[DESC_RATE11M] = MGN_11M,
-+	[DESC_RATE6M] = MGN_6M,
-+	[DESC_RATE9M] = MGN_9M,
-+	[DESC_RATE12M] = MGN_12M,
-+	[DESC_RATE18M] = MGN_18M,
-+	[DESC_RATE24M] = MGN_24M,
-+	[DESC_RATE36M] = MGN_36M,
-+	[DESC_RATE48M] = MGN_48M,
-+	[DESC_RATE54M] = MGN_54M,
-+	[DESC_RATEMCS0] = MGN_MCS0,
-+	[DESC_RATEMCS1] = MGN_MCS1,
-+	[DESC_RATEMCS2] = MGN_MCS2,
-+	[DESC_RATEMCS3] = MGN_MCS3,
-+	[DESC_RATEMCS4] = MGN_MCS4,
-+	[DESC_RATEMCS5] = MGN_MCS5,
-+	[DESC_RATEMCS6] = MGN_MCS6,
-+	[DESC_RATEMCS7] = MGN_MCS7,
-+	[DESC_RATEMCS8] = MGN_MCS8,
-+	[DESC_RATEMCS9] = MGN_MCS9,
-+	[DESC_RATEMCS10] = MGN_MCS10,
-+	[DESC_RATEMCS11] = MGN_MCS11,
-+	[DESC_RATEMCS12] = MGN_MCS12,
-+	[DESC_RATEMCS13] = MGN_MCS13,
-+	[DESC_RATEMCS14] = MGN_MCS14,
-+	[DESC_RATEMCS15] = MGN_MCS15,
-+	[DESC_RATEMCS16] = MGN_MCS16,
-+	[DESC_RATEMCS17] = MGN_MCS17,
-+	[DESC_RATEMCS18] = MGN_MCS18,
-+	[DESC_RATEMCS19] = MGN_MCS19,
-+	[DESC_RATEMCS20] = MGN_MCS20,
-+	[DESC_RATEMCS21] = MGN_MCS21,
-+	[DESC_RATEMCS22] = MGN_MCS22,
-+	[DESC_RATEMCS23] = MGN_MCS23,
-+	[DESC_RATEMCS24] = MGN_MCS24,
-+	[DESC_RATEMCS25] = MGN_MCS25,
-+	[DESC_RATEMCS26] = MGN_MCS26,
-+	[DESC_RATEMCS27] = MGN_MCS27,
-+	[DESC_RATEMCS28] = MGN_MCS28,
-+	[DESC_RATEMCS29] = MGN_MCS29,
-+	[DESC_RATEMCS30] = MGN_MCS30,
-+	[DESC_RATEMCS31] = MGN_MCS31,
-+	[DESC_RATEVHTSS1MCS0] = MGN_VHT1SS_MCS0,
-+	[DESC_RATEVHTSS1MCS1] = MGN_VHT1SS_MCS1,
-+	[DESC_RATEVHTSS1MCS2] = MGN_VHT1SS_MCS2,
-+	[DESC_RATEVHTSS1MCS3] = MGN_VHT1SS_MCS3,
-+	[DESC_RATEVHTSS1MCS4] = MGN_VHT1SS_MCS4,
-+	[DESC_RATEVHTSS1MCS5] = MGN_VHT1SS_MCS5,
-+	[DESC_RATEVHTSS1MCS6] = MGN_VHT1SS_MCS6,
-+	[DESC_RATEVHTSS1MCS7] = MGN_VHT1SS_MCS7,
-+	[DESC_RATEVHTSS1MCS8] = MGN_VHT1SS_MCS8,
-+	[DESC_RATEVHTSS1MCS9] = MGN_VHT1SS_MCS9,
-+	[DESC_RATEVHTSS2MCS0] = MGN_VHT2SS_MCS0,
-+	[DESC_RATEVHTSS2MCS1] = MGN_VHT2SS_MCS1,
-+	[DESC_RATEVHTSS2MCS2] = MGN_VHT2SS_MCS2,
-+	[DESC_RATEVHTSS2MCS3] = MGN_VHT2SS_MCS3,
-+	[DESC_RATEVHTSS2MCS4] = MGN_VHT2SS_MCS4,
-+	[DESC_RATEVHTSS2MCS5] = MGN_VHT2SS_MCS5,
-+	[DESC_RATEVHTSS2MCS6] = MGN_VHT2SS_MCS6,
-+	[DESC_RATEVHTSS2MCS7] = MGN_VHT2SS_MCS7,
-+	[DESC_RATEVHTSS2MCS8] = MGN_VHT2SS_MCS8,
-+	[DESC_RATEVHTSS2MCS9] = MGN_VHT2SS_MCS9,
-+	[DESC_RATEVHTSS3MCS0] = MGN_VHT3SS_MCS0,
-+	[DESC_RATEVHTSS3MCS1] = MGN_VHT3SS_MCS1,
-+	[DESC_RATEVHTSS3MCS2] = MGN_VHT3SS_MCS2,
-+	[DESC_RATEVHTSS3MCS3] = MGN_VHT3SS_MCS3,
-+	[DESC_RATEVHTSS3MCS4] = MGN_VHT3SS_MCS4,
-+	[DESC_RATEVHTSS3MCS5] = MGN_VHT3SS_MCS5,
-+	[DESC_RATEVHTSS3MCS6] = MGN_VHT3SS_MCS6,
-+	[DESC_RATEVHTSS3MCS7] = MGN_VHT3SS_MCS7,
-+	[DESC_RATEVHTSS3MCS8] = MGN_VHT3SS_MCS8,
-+	[DESC_RATEVHTSS3MCS9] = MGN_VHT3SS_MCS9,
-+	[DESC_RATEVHTSS4MCS0] = MGN_VHT4SS_MCS0,
-+	[DESC_RATEVHTSS4MCS1] = MGN_VHT4SS_MCS1,
-+	[DESC_RATEVHTSS4MCS2] = MGN_VHT4SS_MCS2,
-+	[DESC_RATEVHTSS4MCS3] = MGN_VHT4SS_MCS3,
-+	[DESC_RATEVHTSS4MCS4] = MGN_VHT4SS_MCS4,
-+	[DESC_RATEVHTSS4MCS5] = MGN_VHT4SS_MCS5,
-+	[DESC_RATEVHTSS4MCS6] = MGN_VHT4SS_MCS6,
-+	[DESC_RATEVHTSS4MCS7] = MGN_VHT4SS_MCS7,
-+	[DESC_RATEVHTSS4MCS8] = MGN_VHT4SS_MCS8,
-+	[DESC_RATEVHTSS4MCS9] = MGN_VHT4SS_MCS9,
-+};
-+
-+u8 hw_rate_to_m_rate(u8 hw_rate)
-+{
-+	u8 rate = MGN_1M; /* default value */
-+
-+	if (hw_rate < DESC_RATE_NUM)
-+		rate = _hw_rate_to_m_rate[hw_rate];
-+	else
-+		RTW_WARN("Invalid hw_rate 0x%x in %s\n", hw_rate, __FUNCTION__);
-+
-+	return rate;
-+}
-+
-+#ifdef CONFIG_RTW_DEBUG
-+void dump_hw_rate_map_test(void *sel)
-+{
-+	RATE_SECTION rs;
-+	u8 hw_rate;
-+	enum MGN_RATE m_rate;
-+	int i;
-+
-+	for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
-+		for (i = 0; i < rates_by_sections[rs].rate_num; i++) {
-+			hw_rate = MRateToHwRate(rates_by_sections[rs].rates[i]);
-+			RTW_PRINT_SEL(sel, "m_rate:%s(%d) to hw_rate:%s(%d)\n"
-+				, MGN_RATE_STR(rates_by_sections[rs].rates[i]), rates_by_sections[rs].rates[i]
-+				, HDATA_RATE(hw_rate), hw_rate
-+			);
-+		}
-+		if (rs == HT_4SS) { /* show MCS32 after MCS31 */
-+			hw_rate = MRateToHwRate(MGN_MCS32);
-+			RTW_PRINT_SEL(sel, "m_rate:%s(%d) to hw_rate:%s(%d)\n"
-+				, MGN_RATE_STR(MGN_MCS32), MGN_MCS32
-+				, HDATA_RATE(hw_rate), hw_rate
-+			);
-+		}
-+	}
-+	hw_rate = MRateToHwRate(MGN_UNKNOWN);
-+	RTW_PRINT_SEL(sel, "m_rate:%s(%d) to hw_rate:%s(%d)\n"
-+		, MGN_RATE_STR(MGN_UNKNOWN), MGN_UNKNOWN
-+		, HDATA_RATE(hw_rate), hw_rate
-+	);
-+
-+	for (i = DESC_RATE1M; i <= DESC_RATE_NUM; i++) {
-+		m_rate = hw_rate_to_m_rate(i);
-+		RTW_PRINT_SEL(sel, "hw_rate:%s(%d) to m_rate:%s(%d)\n"
-+			, HDATA_RATE(i), i
-+			, MGN_RATE_STR(m_rate), m_rate
-+		);
-+	}
-+}
-+#endif /* CONFIG_RTW_DEBUG */
-+
-+void	HalSetBrateCfg(
-+	PADAPTER		Adapter,
-+	u8			*mBratesOS,
-+	u16			*pBrateCfg)
-+{
-+	u8	i, is_brate, brate;
-+
-+	for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
-+		is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
-+		brate = mBratesOS[i] & 0x7f;
-+
-+		if (is_brate) {
-+			switch (brate) {
-+			case IEEE80211_CCK_RATE_1MB:
-+				*pBrateCfg |= RATE_1M;
-+				break;
-+			case IEEE80211_CCK_RATE_2MB:
-+				*pBrateCfg |= RATE_2M;
-+				break;
-+			case IEEE80211_CCK_RATE_5MB:
-+				*pBrateCfg |= RATE_5_5M;
-+				break;
-+			case IEEE80211_CCK_RATE_11MB:
-+				*pBrateCfg |= RATE_11M;
-+				break;
-+			case IEEE80211_OFDM_RATE_6MB:
-+				*pBrateCfg |= RATE_6M;
-+				break;
-+			case IEEE80211_OFDM_RATE_9MB:
-+				*pBrateCfg |= RATE_9M;
-+				break;
-+			case IEEE80211_OFDM_RATE_12MB:
-+				*pBrateCfg |= RATE_12M;
-+				break;
-+			case IEEE80211_OFDM_RATE_18MB:
-+				*pBrateCfg |= RATE_18M;
-+				break;
-+			case IEEE80211_OFDM_RATE_24MB:
-+				*pBrateCfg |= RATE_24M;
-+				break;
-+			case IEEE80211_OFDM_RATE_36MB:
-+				*pBrateCfg |= RATE_36M;
-+				break;
-+			case IEEE80211_OFDM_RATE_48MB:
-+				*pBrateCfg |= RATE_48M;
-+				break;
-+			case IEEE80211_OFDM_RATE_54MB:
-+				*pBrateCfg |= RATE_54M;
-+				break;
-+			}
-+		}
-+	}
-+}
-+
-+static void
-+_OneOutPipeMapping(
-+		PADAPTER	pAdapter
-+)
-+{
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
-+
-+	pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
-+	pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
-+	pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */
-+	pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
-+
-+	pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
-+	pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
-+	pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
-+	pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
-+}
-+
-+static void
-+_TwoOutPipeMapping(
-+		PADAPTER	pAdapter,
-+		BOOLEAN		bWIFICfg
-+)
-+{
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
-+
-+	if (bWIFICfg) { /* WMM */
-+
-+		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
-+		/* {  0, 	1, 	0, 	1, 	0, 	0, 	0, 	0, 		0	}; */
-+		/* 0:ep_0 num, 1:ep_1 num */
-+
-+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */
-+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
-+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
-+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
-+
-+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
-+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
-+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
-+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
-+
-+	} else { /* typical setting */
-+
-+
-+		/* BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA */
-+		/* {  1, 	1, 	0, 	0, 	0, 	0, 	0, 	0, 		0	};			 */
-+		/* 0:ep_0 num, 1:ep_1 num */
-+
-+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
-+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
-+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
-+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
-+
-+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
-+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
-+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
-+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD	 */
-+
-+	}
-+
-+}
-+
-+static void _ThreeOutPipeMapping(
-+		PADAPTER	pAdapter,
-+		BOOLEAN		bWIFICfg
-+)
-+{
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
-+
-+	if (bWIFICfg) { /* for WMM */
-+
-+		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
-+		/* {  1, 	2, 	1, 	0, 	0, 	0, 	0, 	0, 		0	}; */
-+		/* 0:H, 1:N, 2:L */
-+
-+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
-+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
-+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
-+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
-+
-+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
-+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
-+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
-+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
-+
-+	} else { /* typical setting */
-+
-+
-+		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
-+		/* {  2, 	2, 	1, 	0, 	0, 	0, 	0, 	0, 		0	};			 */
-+		/* 0:H, 1:N, 2:L */
-+
-+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
-+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
-+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
-+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
-+
-+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
-+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
-+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
-+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD	 */
-+	}
-+
-+}
-+#if 0
-+static void _FourOutPipeMapping(
-+		PADAPTER	pAdapter,
-+		BOOLEAN		bWIFICfg
-+)
-+{
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(pAdapter);
-+
-+	if (bWIFICfg) { /* for WMM */
-+
-+		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
-+		/* {  1, 	2, 	1, 	0, 	0, 	0, 	0, 	0, 		0	}; */
-+		/* 0:H, 1:N, 2:L ,3:E */
-+
-+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
-+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
-+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
-+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
-+
-+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
-+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
-+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[3];/* HIGH */
-+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
-+
-+	} else { /* typical setting */
-+
-+
-+		/*	BK, 	BE, 	VI, 	VO, 	BCN,	CMD,MGT,HIGH,HCCA  */
-+		/* {  2, 	2, 	1, 	0, 	0, 	0, 	0, 	0, 		0	};			 */
-+		/* 0:H, 1:N, 2:L */
-+
-+		pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
-+		pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
-+		pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
-+		pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
-+
-+		pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
-+		pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
-+		pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[3];/* HIGH */
-+		pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD	 */
-+	}
-+
-+}
-+#endif
-+BOOLEAN
-+Hal_MappingOutPipe(
-+		PADAPTER	pAdapter,
-+		u8		NumOutPipe
-+)
-+{
-+	struct registry_priv *pregistrypriv = &pAdapter->registrypriv;
-+
-+	BOOLEAN	 bWIFICfg = (pregistrypriv->wifi_spec) ? _TRUE : _FALSE;
-+
-+	BOOLEAN result = _TRUE;
-+
-+	switch (NumOutPipe) {
-+	case 2:
-+		_TwoOutPipeMapping(pAdapter, bWIFICfg);
-+		break;
-+	case 3:
-+	case 4:
-+	case 5:
-+	case 6:
-+		_ThreeOutPipeMapping(pAdapter, bWIFICfg);
-+		break;
-+	case 1:
-+		_OneOutPipeMapping(pAdapter);
-+		break;
-+	default:
-+		result = _FALSE;
-+		break;
-+	}
-+
-+	return result;
-+
-+}
-+
-+void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid)
-+{
-+	if (padapter->hal_func.reqtxrpt)
-+		padapter->hal_func.reqtxrpt(padapter, macid);
-+}
-+
-+void rtw_hal_dump_macaddr(void *sel, _adapter *adapter)
-+{
-+	int i;
-+	_adapter *iface;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	u8 mac_addr[ETH_ALEN];
-+
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+	rtw_mbid_cam_dump(sel, __func__, adapter);
-+#else
-+	rtw_mi_hal_dump_macaddr(sel, adapter);
-+#endif
-+}
-+
-+#ifdef RTW_HALMAC
-+void rtw_hal_hw_port_enable(_adapter *adapter)
-+{
-+#if 1
-+	u8 port_enable = _TRUE;
-+
-+	rtw_hal_set_hwreg(adapter, HW_VAR_PORT_CFG, &port_enable);
-+#else
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct rtw_halmac_bcn_ctrl bcn_ctrl;
-+
-+	_rtw_memset(&bcn_ctrl, 0, sizeof(struct rtw_halmac_bcn_ctrl));
-+	bcn_ctrl.enable_bcn = 1;
-+	bcn_ctrl.rx_bssid_fit = 1;
-+	bcn_ctrl.rxbcn_rpt = 1;
-+
-+	/*rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,
-+				struct rtw_halmac_bcn_ctrl *bcn_ctrl)*/
-+	if (rtw_halmac_set_bcn_ctrl(dvobj, get_hw_port(adapter), &bcn_ctrl) == -1) {
-+		RTW_ERR(ADPT_FMT" - hw port(%d) enable fail!!\n", ADPT_ARG(adapter), get_hw_port(adapter));
-+		rtw_warn_on(1);
-+	}
-+#endif
-+}
-+void rtw_hal_hw_port_disable(_adapter *adapter)
-+{
-+	u8 port_enable = _FALSE;
-+
-+	rtw_hal_set_hwreg(adapter, HW_VAR_PORT_CFG, &port_enable);
-+}
-+
-+void rtw_restore_hw_port_cfg(_adapter *adapter)
-+{
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+
-+#else
-+	int i;
-+	_adapter *iface;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface)
-+			rtw_hal_hw_port_enable(iface);
-+	}
-+#endif
-+}
-+#endif
-+
-+void rtw_mi_set_mac_addr(_adapter *adapter)
-+{
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+	rtw_mi_set_mbid_cam(adapter);
-+#else
-+	int i;
-+	_adapter *iface;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface)
-+			rtw_hal_set_hwreg(iface, HW_VAR_MAC_ADDR, adapter_mac_addr(iface));
-+	}
-+#endif
-+	if (0)
-+		rtw_hal_dump_macaddr(RTW_DBGDUMP, adapter);
-+}
-+
-+void rtw_init_hal_com_default_value(PADAPTER Adapter)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+	struct registry_priv *regsty = adapter_to_regsty(Adapter);
-+
-+	pHalData->AntDetection = 1;
-+	pHalData->antenna_test = _FALSE;
-+	pHalData->RegIQKFWOffload = regsty->iqk_fw_offload;
-+	pHalData->ch_switch_offload = regsty->ch_switch_offload;
-+	pHalData->multi_ch_switch_mode = 0;
-+#ifdef RTW_REDUCE_SCAN_SWITCH_CH_TIME
-+	if (pHalData->ch_switch_offload == 0)
-+		pHalData->ch_switch_offload = 1;
-+#endif
-+}
-+
-+#ifdef CONFIG_FW_C2H_REG
-+void c2h_evt_clear(_adapter *adapter)
-+{
-+	rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
-+}
-+
-+s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf)
-+{
-+	s32 ret = _FAIL;
-+	int i;
-+	u8 trigger;
-+
-+	if (buf == NULL)
-+		goto exit;
-+
-+	trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
-+
-+	if (trigger == C2H_EVT_HOST_CLOSE) {
-+		goto exit; /* Not ready */
-+	} else if (trigger != C2H_EVT_FW_CLOSE) {
-+		goto clear_evt; /* Not a valid value */
-+	}
-+
-+	_rtw_memset(buf, 0, C2H_REG_LEN);
-+
-+	/* Read ID, LEN, SEQ */
-+	SET_C2H_ID_88XX(buf, rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL));
-+	SET_C2H_SEQ_88XX(buf, rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX));
-+	SET_C2H_PLEN_88XX(buf, rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX));
-+
-+	if (0) {
-+		RTW_INFO("%s id=0x%02x, seq=%u, plen=%u, trigger=0x%02x\n", __func__
-+			, C2H_ID_88XX(buf), C2H_SEQ_88XX(buf), C2H_PLEN_88XX(buf), trigger);
-+	}
-+
-+	/* Read the content */
-+	for (i = 0; i < C2H_PLEN_88XX(buf); i++)
-+		*(C2H_PAYLOAD_88XX(buf) + i) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
-+
-+	RTW_DBG_DUMP("payload: ", C2H_PAYLOAD_88XX(buf), C2H_PLEN_88XX(buf));
-+
-+	ret = _SUCCESS;
-+
-+clear_evt:
-+	/*
-+	* Clear event to notify FW we have read the command.
-+	* If this field isn't clear, the FW won't update the next command message.
-+	*/
-+	c2h_evt_clear(adapter);
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_FW_C2H_REG */
-+
-+#ifdef CONFIG_FW_C2H_PKT
-+#ifndef DBG_C2H_PKT_PRE_HDL
-+#define DBG_C2H_PKT_PRE_HDL 0
-+#endif
-+#ifndef DBG_C2H_PKT_HDL
-+#define DBG_C2H_PKT_HDL 0
-+#endif
-+void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len)
-+{
-+#ifdef RTW_HALMAC
-+	/* TODO: extract hal_mac IC's code here*/
-+#else
-+	u8 parse_fail = 0;
-+	u8 hdl_here = 0;
-+	s32 ret = _FAIL;
-+	u8 id, seq, plen;
-+	u8 *payload;
-+
-+	if (rtw_hal_c2h_pkt_hdr_parse(adapter, buf, len, &id, &seq, &plen, &payload) != _SUCCESS) {
-+		parse_fail = 1;
-+		goto exit;
-+	}
-+
-+	hdl_here = rtw_hal_c2h_id_handle_directly(adapter, id, seq, plen, payload) == _TRUE ? 1 : 0;
-+	if (hdl_here) 
-+		ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
-+	else
-+		ret = rtw_c2h_packet_wk_cmd(adapter, buf, len);
-+
-+exit:
-+	if (parse_fail)
-+		RTW_ERR("%s parse fail, buf=%p, len=:%u\n", __func__, buf, len);
-+	else if (ret != _SUCCESS || DBG_C2H_PKT_PRE_HDL > 0) {
-+		RTW_PRINT("%s: id=0x%02x, seq=%u, plen=%u, %s %s\n", __func__, id, seq, plen
-+			, hdl_here ? "handle" : "enqueue"
-+			, ret == _SUCCESS ? "ok" : "fail"
-+		);
-+		if (DBG_C2H_PKT_PRE_HDL >= 2)
-+			RTW_PRINT_DUMP("dump: ", buf, len);
-+	}
-+#endif
-+}
-+
-+void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len)
-+{
-+#ifdef RTW_HALMAC
-+	adapter->hal_func.hal_mac_c2h_handler(adapter, buf, len);
-+#else
-+	u8 parse_fail = 0;
-+	u8 bypass = 0;
-+	s32 ret = _FAIL;
-+	u8 id, seq, plen;
-+	u8 *payload;
-+
-+	if (rtw_hal_c2h_pkt_hdr_parse(adapter, buf, len, &id, &seq, &plen, &payload) != _SUCCESS) {
-+		parse_fail = 1;
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_WOWLAN
-+	if (adapter_to_pwrctl(adapter)->wowlan_mode == _TRUE) {
-+		bypass = 1;
-+		ret = _SUCCESS;
-+		goto exit;
-+	}
-+#endif
-+
-+	ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
-+
-+exit:
-+	if (parse_fail)
-+		RTW_ERR("%s parse fail, buf=%p, len=:%u\n", __func__, buf, len);
-+	else if (ret != _SUCCESS || bypass || DBG_C2H_PKT_HDL > 0) {
-+		RTW_PRINT("%s: id=0x%02x, seq=%u, plen=%u, %s %s\n", __func__, id, seq, plen
-+			, !bypass ? "handle" : "bypass"
-+			, ret == _SUCCESS ? "ok" : "fail"
-+		);
-+		if (DBG_C2H_PKT_HDL >= 2)
-+			RTW_PRINT_DUMP("dump: ", buf, len);
-+	}
-+#endif
-+}
-+#endif /* CONFIG_FW_C2H_PKT */
-+
-+void c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct submit_ctx *iqk_sctx = &hal_data->iqk_sctx;
-+
-+	RTW_INFO("IQK offload finish in %dms\n", rtw_get_passing_time_ms(iqk_sctx->submit_time));
-+	if (0)
-+		RTW_INFO_DUMP("C2H_IQK_FINISH: ", data, len);
-+
-+	rtw_sctx_done(&iqk_sctx);
-+}
-+
-+int c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct submit_ctx *iqk_sctx = &hal_data->iqk_sctx;
-+
-+	iqk_sctx->submit_time = rtw_get_current_time();
-+	iqk_sctx->timeout_ms = timeout_ms;
-+	iqk_sctx->status = RTW_SCTX_SUBMITTED;
-+
-+	return rtw_sctx_wait(iqk_sctx, __func__);
-+}
-+
-+#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
-+void c2h_txpwr_idx_offload_done(_adapter *adapter, u8 *data, u8 len)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct submit_ctx *sctx = &hal_data->txpwr_idx_offload_sctx;
-+
-+	if (0)
-+		RTW_INFO("txpwr_idx offload finish in %dms\n", rtw_get_passing_time_ms(sctx->submit_time));
-+	rtw_sctx_done(&sctx);
-+}
-+
-+int c2h_txpwr_idx_offload_wait(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct submit_ctx *sctx = &hal_data->txpwr_idx_offload_sctx;
-+
-+	return rtw_sctx_wait(sctx, __func__);
-+}
-+#endif
-+
-+#define	GET_C2H_MAC_HIDDEN_RPT_UUID_X(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 8)
-+#define	GET_C2H_MAC_HIDDEN_RPT_UUID_Y(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)
-+#define	GET_C2H_MAC_HIDDEN_RPT_UUID_Z(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 5)
-+#define	GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(_data)			LE_BITS_TO_2BYTE(((u8 *)(_data)) + 2, 5, 11)
-+#define	GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 4)
-+#define	GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 4, 3)
-+#define	GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 7, 1)
-+#define	GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 4)
-+#define	GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 4, 4)
-+#define	GET_C2H_MAC_HIDDEN_RPT_BW(_data)				LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 3)
-+#define	GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(_data)			LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 5, 3)
-+#define	GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 2, 2)
-+#define	GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 6, 2)
-+
-+#ifndef DBG_C2H_MAC_HIDDEN_RPT_HANDLE
-+#define DBG_C2H_MAC_HIDDEN_RPT_HANDLE 0
-+#endif
-+
-+#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
-+int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
-+{
-+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	enum rf_type rf_type;
-+	u8 tx_path_num, rx_path_num;
-+	int ret = _FAIL;
-+
-+	u8 uuid_x;
-+	u8 uuid_y;
-+	u8 uuid_z;
-+	u16 uuid_crc;
-+
-+	u8 hci_type;
-+	u8 package_type;
-+	u8 tr_switch;
-+	u8 wl_func;
-+	u8 hw_stype;
-+	u8 bw;
-+	u8 ss_num = 4;
-+	u8 ant_num;
-+	u8 protocol;
-+	u8 nic;
-+
-+	int i;
-+
-+	if (len < MAC_HIDDEN_RPT_LEN) {
-+		RTW_WARN("%s len(%u) < %d\n", __func__, len, MAC_HIDDEN_RPT_LEN);
-+		goto exit;
-+	}
-+
-+	uuid_x = GET_C2H_MAC_HIDDEN_RPT_UUID_X(data);
-+	uuid_y = GET_C2H_MAC_HIDDEN_RPT_UUID_Y(data);
-+	uuid_z = GET_C2H_MAC_HIDDEN_RPT_UUID_Z(data);
-+	uuid_crc = GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(data);
-+
-+	hci_type = GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(data);
-+	package_type = GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(data);
-+
-+	tr_switch = GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(data);
-+
-+	wl_func = GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(data);
-+	hw_stype = GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(data);
-+
-+	bw = GET_C2H_MAC_HIDDEN_RPT_BW(data);
-+	ant_num = GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(data);
-+
-+	protocol = GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(data);
-+	nic = GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(data);
-+
-+	if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) {
-+		for (i = 0; i < len; i++)
-+			RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
-+
-+		RTW_PRINT("uuid x:0x%02x y:0x%02x z:0x%x crc:0x%x\n", uuid_x, uuid_y, uuid_z, uuid_crc);
-+		RTW_PRINT("hci_type:0x%x\n", hci_type);
-+		RTW_PRINT("package_type:0x%x\n", package_type);
-+		RTW_PRINT("tr_switch:0x%x\n", tr_switch);
-+		RTW_PRINT("wl_func:0x%x\n", wl_func);
-+		RTW_PRINT("hw_stype:0x%x\n", hw_stype);
-+		RTW_PRINT("bw:0x%x\n", bw);
-+		RTW_PRINT("ant_num:0x%x\n", ant_num);
-+		RTW_PRINT("protocol:0x%x\n", protocol);
-+		RTW_PRINT("nic:0x%x\n", nic);
-+	}
-+
-+#if defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
-+	if (IS_8822C_SERIES(hal_data->version_id) || IS_8814B_SERIES(hal_data->version_id)) {
-+		#define GET_C2H_MAC_HIDDEN_RPT_SS_NUM(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 3, 2)
-+		ss_num = GET_C2H_MAC_HIDDEN_RPT_SS_NUM(data);
-+
-+		if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE)
-+			RTW_PRINT("ss_num:0x%x\n", ss_num);
-+
-+		if (ss_num == 0x03)
-+			ss_num = 4;
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8822C)
-+	if (IS_8822C_SERIES(hal_data->version_id)) {
-+		if (ant_num == 1)
-+			hal_spec->rf_reg_trx_path_bmp = 0x22; /* 1T1R pathB */
-+		if (hw_stype == 0xE)
-+			hal_spec->max_tx_cnt = rtw_min(hal_spec->max_tx_cnt, 1); /* limit 1TX only */
-+	}
-+#endif
-+	hal_data->PackageType = package_type;
-+	hal_spec->hci_type = hci_type;
-+	hal_spec->wl_func &= mac_hidden_wl_func_to_hal_wl_func(wl_func);
-+	hal_spec->bw_cap &= mac_hidden_max_bw_to_hal_bw_cap(bw);
-+	hal_spec->proto_cap &= mac_hidden_proto_to_hal_proto_cap(protocol);
-+
-+	rf_type = rtw_chip_rftype_to_hal_rftype(adapter, 0);
-+	if (!RF_TYPE_VALID(rf_type)) {
-+		RTW_ERR("%s rtw_chip_rftype_to_hal_rftype failed\n", __func__);
-+		goto exit;
-+	}
-+	hal_spec->rf_reg_path_avail_num = rtw_min(hal_spec->rf_reg_path_num, ant_num);
-+	tx_path_num = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->rf_reg_path_avail_num);
-+	rx_path_num = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rf_reg_path_avail_num);
-+	hal_spec->rf_reg_trx_path_bmp = rtw_restrict_trx_path_bmp_by_trx_num_lmt(
-+		hal_spec->rf_reg_trx_path_bmp, tx_path_num, rx_path_num, &tx_path_num, &rx_path_num);
-+	if (!hal_spec->rf_reg_trx_path_bmp) {
-+		RTW_ERR("%s rtw_restrict_trx_path_bmp_by_trx_num_lmt(0x%x, %u, %u) failed\n"
-+			, __func__, hal_spec->rf_reg_trx_path_bmp, tx_path_num, rx_path_num);
-+		goto exit;
-+	}
-+	hal_spec->rf_reg_path_avail_num = rtw_max(tx_path_num, rx_path_num);
-+
-+	/*
-+	* RF TX path num >= max_tx_cnt >= tx_nss_num
-+	* ex: RF TX path num(4) >= max_tx_cnt(2) >= tx_nss_num(1)
-+	* Select at most 2 out of 4 TX RF path to do 1SS 2TX
-+	*/
-+	hal_spec->max_tx_cnt = rtw_min(hal_spec->max_tx_cnt, tx_path_num);
-+	hal_spec->tx_nss_num = rtw_min(hal_spec->tx_nss_num, hal_spec->max_tx_cnt);
-+	hal_spec->tx_nss_num = rtw_min(hal_spec->tx_nss_num, ss_num);
-+
-+	hal_spec->rx_nss_num = rtw_min(hal_spec->rx_nss_num, rx_path_num);
-+	hal_spec->rx_nss_num = rtw_min(hal_spec->rx_nss_num, ss_num);
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len)
-+{
-+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(adapter);
-+	int ret = _FAIL;
-+
-+	int i;
-+
-+	if (len < MAC_HIDDEN_RPT_2_LEN) {
-+		RTW_WARN("%s len(%u) < %d\n", __func__, len, MAC_HIDDEN_RPT_2_LEN);
-+		goto exit;
-+	}
-+
-+	if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) {
-+		for (i = 0; i < len; i++)
-+			RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
-+	}
-+
-+	#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
-+	if (IS_8188F(hal_data->version_id) || IS_8188GTV(hal_data->version_id)) {
-+		#define GET_C2H_MAC_HIDDEN_RPT_IRV(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 4)
-+		u8 irv = GET_C2H_MAC_HIDDEN_RPT_IRV(data);
-+
-+		if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE)
-+			RTW_PRINT("irv:0x%x\n", irv);
-+
-+		if(irv != 0xf)
-+			hal_data->version_id.CUTVersion = irv;
-+	}
-+	#endif
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+int hal_read_mac_hidden_rpt(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(adapter);
-+	int ret = _FAIL;
-+	int ret_fwdl;
-+	u8 mac_hidden_rpt[MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN] = {0};
-+	systime start = rtw_get_current_time();
-+	u32 cnt = 0;
-+	u32 timeout_ms = 800;
-+	u32 min_cnt = 10;
-+	u8 id = C2H_DEFEATURE_RSVD;
-+	int i;
-+
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
-+	u8 hci_type = rtw_get_intf_type(adapter);
-+
-+	if ((hci_type == RTW_USB || hci_type == RTW_PCIE)
-+		&& !rtw_is_hw_init_completed(adapter))
-+		rtw_hal_power_on(adapter);
-+#endif
-+
-+	/* inform FW mac hidden rpt from reg is needed */
-+	rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DEFEATURE_RSVD);
-+
-+	/* download FW */
-+	pHalData->not_xmitframe_fw_dl = 1;
-+	ret_fwdl = rtw_hal_fw_dl(adapter, _FALSE);
-+	pHalData->not_xmitframe_fw_dl = 0;
-+	if (ret_fwdl != _SUCCESS)
-+		goto mac_hidden_rpt_hdl;
-+
-+	/* polling for data ready */
-+	start = rtw_get_current_time();
-+	do {
-+		cnt++;
-+		id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
-+		if (id == C2H_MAC_HIDDEN_RPT || RTW_CANNOT_IO(adapter))
-+			break;
-+		rtw_msleep_os(10);
-+	} while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
-+
-+	if (id == C2H_MAC_HIDDEN_RPT) {
-+		/* read data */
-+		for (i = 0; i < MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN; i++)
-+			mac_hidden_rpt[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
-+	}
-+
-+	/* inform FW mac hidden rpt has read */
-+	rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DBG);
-+
-+mac_hidden_rpt_hdl:
-+	c2h_mac_hidden_rpt_hdl(adapter, mac_hidden_rpt, MAC_HIDDEN_RPT_LEN);
-+	c2h_mac_hidden_rpt_2_hdl(adapter, mac_hidden_rpt + MAC_HIDDEN_RPT_LEN, MAC_HIDDEN_RPT_2_LEN);
-+
-+	if (ret_fwdl == _SUCCESS && id == C2H_MAC_HIDDEN_RPT)
-+		ret = _SUCCESS;
-+
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
-+	if ((hci_type == RTW_USB || hci_type == RTW_PCIE)
-+		&& !rtw_is_hw_init_completed(adapter))
-+		rtw_hal_power_off(adapter);
-+#endif
-+
-+	RTW_INFO("%s %s! (%u, %dms), fwdl:%d, id:0x%02x\n", __func__
-+		, (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), ret_fwdl, id);
-+
-+	return ret;
-+}
-+#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
-+
-+int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len)
-+{
-+	int ret = _FAIL;
-+
-+	int i;
-+
-+	if (len < DEFEATURE_DBG_LEN) {
-+		RTW_WARN("%s len(%u) < %d\n", __func__, len, DEFEATURE_DBG_LEN);
-+		goto exit;
-+	}
-+
-+	for (i = 0; i < len; i++)
-+		RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
-+
-+	ret = _SUCCESS;
-+	
-+exit:
-+	return ret;
-+}
-+
-+#ifndef DBG_CUSTOMER_STR_RPT_HANDLE
-+#define DBG_CUSTOMER_STR_RPT_HANDLE 0
-+#endif
-+
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+s32 rtw_hal_h2c_customer_str_req(_adapter *adapter)
-+{
-+	u8 h2c_data[H2C_CUSTOMER_STR_REQ_LEN] = {0};
-+
-+	SET_H2CCMD_CUSTOMER_STR_REQ_EN(h2c_data, 1);
-+	return rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_REQ, H2C_CUSTOMER_STR_REQ_LEN, h2c_data);
-+}
-+
-+#define	C2H_CUSTOMER_STR_RPT_BYTE0(_data)		((u8 *)(_data))
-+#define	C2H_CUSTOMER_STR_RPT_2_BYTE8(_data)		((u8 *)(_data))
-+
-+int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	int ret = _FAIL;
-+	int i;
-+
-+	if (len < CUSTOMER_STR_RPT_LEN) {
-+		RTW_WARN("%s len(%u) < %d\n", __func__, len, CUSTOMER_STR_RPT_LEN);
-+		goto exit;
-+	}
-+
-+	if (DBG_CUSTOMER_STR_RPT_HANDLE)
-+		RTW_PRINT_DUMP("customer_str_rpt: ", data, CUSTOMER_STR_RPT_LEN);
-+
-+	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+
-+	if (dvobj->customer_str_sctx != NULL) {
-+		if (dvobj->customer_str_sctx->status != RTW_SCTX_SUBMITTED)
-+			RTW_WARN("%s invalid sctx.status:%d\n", __func__, dvobj->customer_str_sctx->status);
-+		_rtw_memcpy(dvobj->customer_str,  C2H_CUSTOMER_STR_RPT_BYTE0(data), CUSTOMER_STR_RPT_LEN);
-+		dvobj->customer_str_sctx->status = RTX_SCTX_CSTR_WAIT_RPT2;
-+	} else
-+		RTW_WARN("%s sctx not set\n", __func__);
-+
-+	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	int ret = _FAIL;
-+	int i;
-+
-+	if (len < CUSTOMER_STR_RPT_2_LEN) {
-+		RTW_WARN("%s len(%u) < %d\n", __func__, len, CUSTOMER_STR_RPT_2_LEN);
-+		goto exit;
-+	}
-+
-+	if (DBG_CUSTOMER_STR_RPT_HANDLE)
-+		RTW_PRINT_DUMP("customer_str_rpt_2: ", data, CUSTOMER_STR_RPT_2_LEN);
-+
-+	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+
-+	if (dvobj->customer_str_sctx != NULL) {
-+		if (dvobj->customer_str_sctx->status != RTX_SCTX_CSTR_WAIT_RPT2)
-+			RTW_WARN("%s rpt not ready\n", __func__);
-+		_rtw_memcpy(dvobj->customer_str + CUSTOMER_STR_RPT_LEN,  C2H_CUSTOMER_STR_RPT_2_BYTE8(data), CUSTOMER_STR_RPT_2_LEN);
-+		rtw_sctx_done(&dvobj->customer_str_sctx);
-+	} else
-+		RTW_WARN("%s sctx not set\n", __func__);
-+
-+	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+/* read customer str */
-+s32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct submit_ctx sctx;
-+	s32 ret = _SUCCESS;
-+
-+	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+	if (dvobj->customer_str_sctx != NULL)
-+		ret = _FAIL;
-+	else {
-+		rtw_sctx_init(&sctx, 2 * 1000);
-+		dvobj->customer_str_sctx = &sctx;
-+	}
-+	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+
-+	if (ret == _FAIL) {
-+		RTW_WARN("%s another handle ongoing\n", __func__);
-+		goto exit;
-+	}
-+
-+	ret = rtw_customer_str_req_cmd(adapter);
-+	if (ret != _SUCCESS) {
-+		RTW_WARN("%s read cmd fail\n", __func__);
-+		_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+		dvobj->customer_str_sctx = NULL;
-+		_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+		goto exit;
-+	}
-+
-+	/* wait till rpt done or timeout */
-+	rtw_sctx_wait(&sctx, __func__);
-+
-+	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+	dvobj->customer_str_sctx = NULL;
-+	if (sctx.status == RTW_SCTX_DONE_SUCCESS)
-+		_rtw_memcpy(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN);
-+	else
-+		ret = _FAIL;
-+	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+
-+exit:
-+	return ret;
-+}
-+
-+s32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs)
-+{
-+	u8 h2c_data_w1[H2C_CUSTOMER_STR_W1_LEN] = {0};
-+	u8 h2c_data_w2[H2C_CUSTOMER_STR_W2_LEN] = {0};
-+	u8 h2c_data_w3[H2C_CUSTOMER_STR_W3_LEN] = {0};
-+	s32 ret;
-+
-+	SET_H2CCMD_CUSTOMER_STR_W1_EN(h2c_data_w1, 1);
-+	_rtw_memcpy(H2CCMD_CUSTOMER_STR_W1_BYTE0(h2c_data_w1), cs, 6);
-+
-+	SET_H2CCMD_CUSTOMER_STR_W2_EN(h2c_data_w2, 1);
-+	_rtw_memcpy(H2CCMD_CUSTOMER_STR_W2_BYTE6(h2c_data_w2), cs + 6, 6);
-+
-+	SET_H2CCMD_CUSTOMER_STR_W3_EN(h2c_data_w3, 1);
-+	_rtw_memcpy(H2CCMD_CUSTOMER_STR_W3_BYTE12(h2c_data_w3), cs + 6 + 6, 4);
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W1, H2C_CUSTOMER_STR_W1_LEN, h2c_data_w1);
-+	if (ret != _SUCCESS) {
-+		RTW_WARN("%s w1 fail\n", __func__);
-+		goto exit;
-+	}
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W2, H2C_CUSTOMER_STR_W2_LEN, h2c_data_w2);
-+	if (ret != _SUCCESS) {
-+		RTW_WARN("%s w2 fail\n", __func__);
-+		goto exit;
-+	}
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W3, H2C_CUSTOMER_STR_W3_LEN, h2c_data_w3);
-+	if (ret != _SUCCESS) {
-+		RTW_WARN("%s w3 fail\n", __func__);
-+		goto exit;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+/* write customer str and check if value reported is the same as requested */
-+s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct submit_ctx sctx;
-+	s32 ret = _SUCCESS;
-+
-+	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+	if (dvobj->customer_str_sctx != NULL)
-+		ret = _FAIL;
-+	else {
-+		rtw_sctx_init(&sctx, 2 * 1000);
-+		dvobj->customer_str_sctx = &sctx;
-+	}
-+	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+
-+	if (ret == _FAIL) {
-+		RTW_WARN("%s another handle ongoing\n", __func__);
-+		goto exit;
-+	}
-+
-+	ret = rtw_customer_str_write_cmd(adapter, cs);
-+	if (ret != _SUCCESS) {
-+		RTW_WARN("%s write cmd fail\n", __func__);
-+		_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+		dvobj->customer_str_sctx = NULL;
-+		_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+		goto exit;
-+	}
-+
-+	ret = rtw_customer_str_req_cmd(adapter);
-+	if (ret != _SUCCESS) {
-+		RTW_WARN("%s read cmd fail\n", __func__);
-+		_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+		dvobj->customer_str_sctx = NULL;
-+		_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+		goto exit;
-+	}
-+
-+	/* wait till rpt done or timeout */
-+	rtw_sctx_wait(&sctx, __func__);
-+
-+	_enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+	dvobj->customer_str_sctx = NULL;
-+	if (sctx.status == RTW_SCTX_DONE_SUCCESS) {
-+		if (_rtw_memcmp(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN) != _TRUE) {
-+			RTW_WARN("%s read back check fail\n", __func__);
-+			RTW_INFO_DUMP("write req: ", cs, RTW_CUSTOMER_STR_LEN);
-+			RTW_INFO_DUMP("read back: ", dvobj->customer_str, RTW_CUSTOMER_STR_LEN);
-+			ret = _FAIL;
-+		}
-+	} else
-+		ret = _FAIL;
-+	_exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_RTW_CUSTOMER_STR */
-+
-+#ifdef RTW_PER_CMD_SUPPORT_FW
-+#define H2C_REQ_PER_RPT_LEN 5
-+#define SET_H2CCMD_REQ_PER_RPT_GROUP_MACID(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
-+#define SET_H2CCMD_REQ_PER_RPT_RPT_TYPE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
-+#define SET_H2CCMD_REQ_PER_RPT_MACID_BMAP(__pH2CCmd, __Value)	SET_BITS_TO_LE_4BYTE(__pH2CCmd + 1, 0, 32, __Value)
-+
-+u8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid,
-+				      u8 rpt_type, u32 macid_bitmap)
-+{
-+	u8 ret = _FAIL;
-+	u8 cmd_buf[H2C_REQ_PER_RPT_LEN] = {0};
-+
-+	SET_H2CCMD_REQ_PER_RPT_GROUP_MACID(cmd_buf, group_macid);
-+	SET_H2CCMD_REQ_PER_RPT_RPT_TYPE(cmd_buf, rpt_type);
-+	SET_H2CCMD_REQ_PER_RPT_MACID_BMAP(cmd_buf, macid_bitmap);
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter, 
-+				   H2C_REQ_PER_RPT, 
-+				   H2C_REQ_PER_RPT_LEN, 
-+				   cmd_buf);
-+	return ret;
-+}
-+
-+#define	GET_C2H_PER_RATE_RPT_TYPE0_MACID0(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE0_PER0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE0_RATE0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE0_BW0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 3, 0, 2)
-+#define	GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT0(_data)	LE_BITS_TO_2BYTE(((u8 *)(_data)) + 4, 0, 16)
-+#define	GET_C2H_PER_RATE_RPT_TYPE0_MACID1(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE0_PER1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE0_RATE1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 8, 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE0_BW1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 9, 0, 2)
-+#define	GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT1(_data)	LE_BITS_TO_2BYTE(((u8 *)(_data)) + 10, 0, 16)
-+
-+#define	GET_C2H_PER_RATE_RPT_TYPE1_MACID0(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE1_PER0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE1_RATE0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE1_BW0(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 3, 0, 2)
-+#define	GET_C2H_PER_RATE_RPT_TYPE1_MACID1(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE1_PER1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE1_RATE1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE1_BW1(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 0, 2)
-+#define	GET_C2H_PER_RATE_RPT_TYPE1_MACID2(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)) + 8, 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE1_PER2(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 9, 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE1_RATE2(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 10, 0, 8)
-+#define	GET_C2H_PER_RATE_RPT_TYPE1_BW2(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 11, 0, 2)
-+
-+static void per_rate_rpt_update(_adapter *adapter, u8 mac_id,
-+				u8 per, u8 rate,
-+				u8 bw, u8 total_pkt)
-+{
-+#ifdef CONFIG_RTW_MESH
-+	rtw_ieee80211s_update_metric(adapter, mac_id,
-+				     per, rate,
-+				     bw, total_pkt);
-+#endif
-+}
-+
-+int c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
-+{
-+	/* Now only consider type0, since it covers all params in type1
-+	 * type0: mac_id, per, rate, bw, total_pkt
-+	 * type1: mac_id, per, rate, bw
-+	 */
-+	u8 mac_id[2] = {0}, per[2] = {0}, rate[2] = {0}, bw[2] = {0};
-+	u16 total_pkt[2] = {0};
-+	int ret = _FAIL, i, macid_cnt = 0;
-+
-+	/* type0:
-+	 * 1 macid includes   6 bytes info + 1 byte 0xff
-+	 * 2 macid includes 2*6 bytes info
-+	 */
-+	if (!(len == 7 || len == 12)) {
-+		RTW_WARN("%s len(%u) != 7 or 12\n", __FUNCTION__, len);
-+		goto exit;
-+	}
-+
-+	macid_cnt++;
-+	mac_id[0] = GET_C2H_PER_RATE_RPT_TYPE0_MACID0(data);
-+	per[0] = GET_C2H_PER_RATE_RPT_TYPE0_PER0(data);
-+	rate[0] = GET_C2H_PER_RATE_RPT_TYPE0_RATE0(data);
-+	bw[0] = GET_C2H_PER_RATE_RPT_TYPE0_BW0(data);
-+	total_pkt[0] = GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT0(data);
-+
-+	mac_id[1] = GET_C2H_PER_RATE_RPT_TYPE0_MACID1(data);
-+	/* 0xff means no report anymore */
-+	if (mac_id[1] == 0xff)
-+		goto update_per;
-+	if (len != 12) {
-+		RTW_WARN("%s incorrect format\n", __FUNCTION__);
-+		goto exit;
-+	}
-+	macid_cnt++;
-+	per[1] = GET_C2H_PER_RATE_RPT_TYPE0_PER1(data);
-+	rate[1] = GET_C2H_PER_RATE_RPT_TYPE0_RATE1(data);
-+	bw[1] = GET_C2H_PER_RATE_RPT_TYPE0_BW1(data);
-+	total_pkt[1] = GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT1(data);
-+
-+update_per:
-+	for (i = 0; i < macid_cnt; i++) {
-+		RTW_DBG("[%s] type0 rpt[%d]: macid = %u, per = %u, "
-+			"rate = %u, bw = %u, total_pkt = %u\n",
-+			__FUNCTION__, i, mac_id[i], per[i],
-+			rate[i], bw[i], total_pkt[i]);
-+		per_rate_rpt_update(adapter, mac_id[i],
-+				    per[i], rate[i],
-+				    bw[i], total_pkt[i]);
-+	}
-+	ret = _SUCCESS;
-+exit:
-+	return ret;
-+}
-+#endif /* RTW_PER_CMD_SUPPORT_FW */
-+
-+#ifdef CONFIG_LPS_ACK
-+#define	GET_C2H_LPS_STATUS_RPT_GET_ACTION(_data)	LE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8)
-+#define	GET_C2H_LPS_STATUS_RPT_GET_STATUS_CODE(_data)		LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)
-+#define DBG_LPS_STATUS_RPT 0
-+
-+int c2h_lps_status_rpt(PADAPTER adapter, u8 *data, u8 len)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	struct submit_ctx *lps_sctx = &pwrpriv->lps_ack_sctx;
-+	u8 action = 0;
-+	s8 status_code = 0;
-+	int ret = _FAIL;
-+
-+	if (len < LPS_STATUS_RPT_LEN) {
-+		RTW_WARN("%s len(%u) < %d\n", __func__, len, LPS_STATUS_RPT_LEN);
-+		goto exit;
-+	}
-+
-+	action = GET_C2H_LPS_STATUS_RPT_GET_ACTION(data);
-+	status_code = GET_C2H_LPS_STATUS_RPT_GET_STATUS_CODE(data);
-+
-+	/* action=0: report force leave null data status */
-+	/* action=1: report Rf on status when receiving a SetPwrMode H2C with PwrState = RFON */
-+	switch (action) {
-+		case 0: 
-+			/* status code 0: success, 1: no ack, 2: timeout, 3: cancel */
-+		case 1: 
-+			/* status code 0: FW has already turn to RFON */
-+			pwrpriv->lps_ack_status = status_code;
-+
-+			if (DBG_LPS_STATUS_RPT)
-+				RTW_INFO("=== [C2H LPS Action(%d)] LPS Status Code:%d ===\n", action, status_code);
-+			
-+			break;
-+		default:
-+			RTW_INFO("UnKnown Action(%d) for C2H LPS RPT\n", action);
-+			break;
-+	}
-+
-+	rtw_sctx_done(&lps_sctx);
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_LPS_ACK */
-+
-+void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta)
-+{
-+	u8 w_set = 0;
-+
-+	if (psta->wireless_mode & WIRELESS_11B)
-+		w_set |= WIRELESS_CCK;
-+
-+	if ((psta->wireless_mode & WIRELESS_11G) || (psta->wireless_mode & WIRELESS_11A))
-+		w_set |= WIRELESS_OFDM;
-+
-+	if (psta->wireless_mode & WIRELESS_11_24N)
-+		w_set |= WIRELESS_HT;
-+
-+	if ((psta->wireless_mode & WIRELESS_11AC) || (psta->wireless_mode & WIRELESS_11_5N))
-+		w_set |= WIRELESS_VHT;
-+
-+	psta->cmn.support_wireless_set = w_set;
-+}
-+
-+void rtw_hal_update_sta_mimo_type(_adapter *adapter, struct sta_info *psta)
-+{
-+	s8 tx_nss, rx_nss;
-+
-+	tx_nss = rtw_get_sta_tx_nss(adapter, psta);
-+	rx_nss =  rtw_get_sta_rx_nss(adapter, psta);
-+	if ((tx_nss == 1) && (rx_nss == 1))
-+		psta->cmn.mimo_type = RF_1T1R;
-+	else if ((tx_nss == 1) && (rx_nss == 2))
-+		psta->cmn.mimo_type = RF_1T2R;
-+	else if ((tx_nss == 2) && (rx_nss == 2))
-+		psta->cmn.mimo_type = RF_2T2R;
-+	else if ((tx_nss == 2) && (rx_nss == 3))
-+		psta->cmn.mimo_type = RF_2T3R;
-+	else if ((tx_nss == 2) && (rx_nss == 4))
-+		psta->cmn.mimo_type = RF_2T4R;
-+	else if ((tx_nss == 3) && (rx_nss == 3))
-+		psta->cmn.mimo_type = RF_3T3R;
-+	else if ((tx_nss == 3) && (rx_nss == 4))
-+		psta->cmn.mimo_type = RF_3T4R;
-+	else if ((tx_nss == 4) && (rx_nss == 4))
-+		psta->cmn.mimo_type = RF_4T4R;
-+	else
-+		rtw_warn_on(1);
-+
-+#ifdef CONFIG_CTRL_TXSS_BY_TP
-+	rtw_ctrl_txss_update_mimo_type(adapter, psta);
-+#endif
-+
-+	RTW_INFO("STA - MAC_ID:%d, Tx - %d SS, Rx - %d SS\n",
-+			psta->cmn.mac_id, tx_nss, rx_nss);
-+}
-+
-+void rtw_hal_update_sta_smps_cap(_adapter *adapter, struct sta_info *psta)
-+{
-+	/*Spatial Multiplexing Power Save*/
-+#if 0
-+	if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {
-+		#ifdef CONFIG_80211N_HT
-+		if (psta->htpriv.ht_option) {
-+			if (psta->htpriv.smps_cap == 0)
-+				psta->cmn.sm_ps = SM_PS_STATIC;
-+			else if (psta->htpriv.smps_cap == 1)
-+				psta->cmn.sm_ps = SM_PS_DYNAMIC;
-+			else
-+				psta->cmn.sm_ps = SM_PS_DISABLE;
-+		}
-+		#endif /* CONFIG_80211N_HT */
-+	} else
-+#endif
-+		psta->cmn.sm_ps = SM_PS_DISABLE;
-+
-+	RTW_INFO("STA - MAC_ID:%d, SM_PS %d\n",
-+			psta->cmn.mac_id, psta->cmn.sm_ps);
-+}
-+
-+u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type)
-+{
-+
-+	u8 raid;
-+	if (IS_NEW_GENERATION_IC(adapter)) {
-+
-+		raid = (network_type & WIRELESS_11B)	? RATEID_IDX_B
-+		       : RATEID_IDX_G;
-+	} else {
-+		raid = (network_type & WIRELESS_11B)	? RATR_INX_WIRELESS_B
-+		       : RATR_INX_WIRELESS_G;
-+	}
-+	return raid;
-+}
-+
-+void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta)
-+{
-+	u8 i, tx_nss;
-+	u64 tx_ra_bitmap = 0, tmp64=0;
-+
-+	if (psta == NULL)
-+		return;
-+
-+	/* b/g mode ra_bitmap  */
-+	for (i = 0; i < sizeof(psta->bssrateset); i++) {
-+		if (psta->bssrateset[i])
-+			tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i] & 0x7f);
-+	}
-+
-+#ifdef CONFIG_80211N_HT
-+if (padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) {
-+	tx_nss = GET_HAL_TX_NSS(padapter);
-+#ifdef CONFIG_80211AC_VHT
-+	if (psta->vhtpriv.vht_option) {
-+		/* AC mode ra_bitmap */
-+		tx_ra_bitmap |= (rtw_vht_mcs_map_to_bitmap(psta->vhtpriv.vht_mcs_map, tx_nss) << 12);
-+	} else
-+#endif /* CONFIG_80211AC_VHT */
-+	if (psta->htpriv.ht_option) {
-+		/* n mode ra_bitmap */
-+
-+		/* Handling SMPS mode for AP MODE only*/
-+		if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {
-+			/*0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/
-+			if (psta->htpriv.smps_cap == 0 || psta->htpriv.smps_cap == 1) {
-+				/*operate with only one active receive chain // 11n-MCS rate <= MSC7*/
-+				tx_nss = rtw_min(tx_nss, 1);
-+			}
-+		}
-+
-+		tmp64 = rtw_ht_mcs_set_to_bitmap(psta->htpriv.ht_cap.supp_mcs_set, tx_nss);
-+		tx_ra_bitmap |= (tmp64 << 12);
-+	}
-+}
-+#endif /* CONFIG_80211N_HT */
-+	psta->cmn.ra_info.ramask = tx_ra_bitmap;
-+	psta->init_rate = get_highest_rate_idx(tx_ra_bitmap) & 0x3f;
-+}
-+
-+void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta)
-+{
-+	rtw_hal_update_sta_mimo_type(padapter, psta);
-+	rtw_hal_update_sta_smps_cap(padapter, psta);
-+	rtw_hal_update_sta_rate_mask(padapter, psta);
-+}
-+
-+#ifndef CONFIG_HAS_HW_VAR_BCN_CTRL_ADDR
-+static u32 hw_bcn_ctrl_addr(_adapter *adapter, u8 hw_port)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+
-+	if (hw_port >= hal_spec->port_num) {
-+		RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port);
-+		rtw_warn_on(1);
-+		return 0;
-+	}
-+
-+	switch (hw_port) {
-+	case HW_PORT0:
-+		return REG_BCN_CTRL;
-+	case HW_PORT1:
-+		return REG_BCN_CTRL_1;
-+	}
-+
-+	return 0;
-+}
-+#endif
-+
-+static void rtw_hal_get_msr(_adapter *adapter, u8 *net_type)
-+{
-+#ifdef RTW_HALMAC
-+	rtw_halmac_get_network_type(adapter_to_dvobj(adapter),
-+				adapter->hw_port, net_type);
-+#else /* !RTW_HALMAC */
-+	switch (adapter->hw_port) {
-+	case HW_PORT0:
-+		/*REG_CR - BIT[17:16]-Network Type for port 1*/
-+		*net_type = rtw_read8(adapter, MSR) & 0x03;
-+		break;
-+	case HW_PORT1:
-+		/*REG_CR - BIT[19:18]-Network Type for port 1*/
-+		*net_type = (rtw_read8(adapter, MSR) & 0x0C) >> 2;
-+		break;
-+#if defined(CONFIG_RTL8814A)
-+	case HW_PORT2:
-+		/*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/
-+		*net_type = rtw_read8(adapter, MSR1) & 0x03;
-+		break;
-+	case HW_PORT3:
-+		/*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/
-+		*net_type = (rtw_read8(adapter, MSR1) & 0x0C) >> 2;
-+		break;
-+	case HW_PORT4:
-+		/*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/
-+		*net_type = (rtw_read8(adapter, MSR1) & 0x30) >> 4;
-+		break;
-+#endif /*#if defined(CONFIG_RTL8814A)*/
-+	default:
-+		RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n",
-+			 ADPT_ARG(adapter), adapter->hw_port);
-+		rtw_warn_on(1);
-+		break;
-+	}
-+#endif /* !RTW_HALMAC */
-+}
-+
-+#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) /*For 2 hw ports - 88E/92E/8812/8821/8723B*/
-+static u8 rtw_hal_net_type_decision(_adapter *adapter, u8 net_type)
-+{
-+	if ((adapter->hw_port == HW_PORT0) && (rtw_get_mbid_cam_entry_num(adapter))) {
-+		if (net_type != _HW_STATE_NOLINK_)
-+			return _HW_STATE_AP_;
-+	}
-+	return net_type;
-+}
-+#endif
-+static void rtw_hal_set_msr(_adapter *adapter, u8 net_type)
-+{
-+#ifdef RTW_HALMAC
-+	#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM)
-+	net_type = rtw_hal_net_type_decision(adapter, net_type);
-+	#endif
-+	rtw_halmac_set_network_type(adapter_to_dvobj(adapter),
-+				adapter->hw_port, net_type);
-+#else /* !RTW_HALMAC */
-+	u8 val8 = 0;
-+
-+	switch (adapter->hw_port) {
-+	case HW_PORT0:
-+		#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM)
-+		net_type = rtw_hal_net_type_decision(adapter, net_type);
-+		#endif
-+		/*REG_CR - BIT[17:16]-Network Type for port 0*/
-+		val8 = rtw_read8(adapter, MSR) & 0x0C;
-+		val8 |= net_type;
-+		rtw_write8(adapter, MSR, val8);
-+		break;
-+	case HW_PORT1:
-+		/*REG_CR - BIT[19:18]-Network Type for port 1*/
-+		val8 = rtw_read8(adapter, MSR) & 0x03;
-+		val8 |= net_type << 2;
-+		rtw_write8(adapter, MSR, val8);
-+		break;
-+#if defined(CONFIG_RTL8814A)
-+	case HW_PORT2:
-+		/*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/
-+		val8 = rtw_read8(adapter, MSR1) & 0xFC;
-+		val8 |= net_type;
-+		rtw_write8(adapter, MSR1, val8);
-+		break;
-+	case HW_PORT3:
-+		/*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/
-+		val8 = rtw_read8(adapter, MSR1) & 0xF3;
-+		val8 |= net_type << 2;
-+		rtw_write8(adapter, MSR1, val8);
-+		break;
-+	case HW_PORT4:
-+		/*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/
-+		val8 = rtw_read8(adapter, MSR1) & 0xCF;
-+		val8 |= net_type << 4;
-+		rtw_write8(adapter, MSR1, val8);
-+		break;
-+#endif /* CONFIG_RTL8814A */
-+	default:
-+		RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n",
-+			 ADPT_ARG(adapter), adapter->hw_port);
-+		rtw_warn_on(1);
-+		break;
-+	}
-+#endif /* !RTW_HALMAC */
-+}
-+
-+#ifndef SEC_CAM_ACCESS_TIMEOUT_MS
-+	#define SEC_CAM_ACCESS_TIMEOUT_MS 200
-+#endif
-+
-+#ifndef DBG_SEC_CAM_ACCESS
-+	#define DBG_SEC_CAM_ACCESS 0
-+#endif
-+
-+u32 rtw_sec_read_cam(_adapter *adapter, u8 addr)
-+{
-+	_mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex;
-+	u32 rdata;
-+	u32 cnt = 0;
-+	systime start = 0, end = 0;
-+	u8 timeout = 0;
-+	u8 sr = 0;
-+
-+	_enter_critical_mutex(mutex, NULL);
-+
-+	rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | addr);
-+
-+	start = rtw_get_current_time();
-+	while (1) {
-+		if (rtw_is_surprise_removed(adapter)) {
-+			sr = 1;
-+			break;
-+		}
-+
-+		cnt++;
-+		if (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG))
-+			break;
-+
-+		if (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) {
-+			timeout = 1;
-+			break;
-+		}
-+	}
-+	end = rtw_get_current_time();
-+
-+	rdata = rtw_read32(adapter, REG_CAMREAD);
-+
-+	_exit_critical_mutex(mutex, NULL);
-+
-+	if (DBG_SEC_CAM_ACCESS || timeout) {
-+		RTW_INFO(FUNC_ADPT_FMT" addr:0x%02x, rdata:0x%08x, to:%u, polling:%u, %d ms\n"
-+			, FUNC_ADPT_ARG(adapter), addr, rdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
-+	}
-+
-+	return rdata;
-+}
-+
-+void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata)
-+{
-+	_mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex;
-+	u32 cnt = 0;
-+	systime start = 0, end = 0;
-+	u8 timeout = 0;
-+	u8 sr = 0;
-+
-+	_enter_critical_mutex(mutex, NULL);
-+
-+	rtw_write32(adapter, REG_CAMWRITE, wdata);
-+	rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | CAM_WRITE | addr);
-+
-+	start = rtw_get_current_time();
-+	while (1) {
-+		if (rtw_is_surprise_removed(adapter)) {
-+			sr = 1;
-+			break;
-+		}
-+
-+		cnt++;
-+		if (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG))
-+			break;
-+
-+		if (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) {
-+			timeout = 1;
-+			break;
-+		}
-+	}
-+	end = rtw_get_current_time();
-+
-+	_exit_critical_mutex(mutex, NULL);
-+
-+	if (DBG_SEC_CAM_ACCESS || timeout) {
-+		RTW_INFO(FUNC_ADPT_FMT" addr:0x%02x, wdata:0x%08x, to:%u, polling:%u, %d ms\n"
-+			, FUNC_ADPT_ARG(adapter), addr, wdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
-+	}
-+}
-+
-+void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key)
-+{
-+	u8 i;
-+	u32 rdata;
-+	u8 begin = 0;
-+	u8 end = 5; /* TODO: consider other key length accordingly */
-+
-+	if (!ctrl && !mac && !key) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	/* TODO: check id range */
-+
-+	if (!ctrl && !mac)
-+		begin = 2; /* read from key */
-+
-+	if (!key && !mac)
-+		end = 0; /* read to ctrl */
-+	else if (!key)
-+		end = 2; /* read to mac */
-+
-+	for (i = begin; i <= end; i++) {
-+		rdata = rtw_sec_read_cam(adapter, (id << 3) | i);
-+
-+		switch (i) {
-+		case 0:
-+			if (ctrl)
-+				_rtw_memcpy(ctrl, (u8 *)(&rdata), 2);
-+			if (mac)
-+				_rtw_memcpy(mac, ((u8 *)(&rdata)) + 2, 2);
-+			break;
-+		case 1:
-+			if (mac)
-+				_rtw_memcpy(mac + 2, (u8 *)(&rdata), 4);
-+			break;
-+		default:
-+			if (key)
-+				_rtw_memcpy(key + (i - 2) * 4, (u8 *)(&rdata), 4);
-+			break;
-+		}
-+	}
-+
-+exit:
-+	return;
-+}
-+
-+
-+void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
-+{
-+	unsigned int i;
-+	int j;
-+	u8 addr, addr1 = 0;
-+	u32 wdata, wdata1 = 0;
-+
-+	/* TODO: consider other key length accordingly */
-+#if 0
-+	switch ((ctrl & 0x1c) >> 2) {
-+	case _WEP40_:
-+	case _TKIP_:
-+	case _AES_:
-+	case _WEP104_:
-+
-+	}
-+#else
-+	j = 7;
-+#endif
-+
-+	for (; j >= 0; j--) {
-+		switch (j) {
-+		case 0:
-+			wdata = (ctrl | (mac[0] << 16) | (mac[1] << 24));
-+			break;
-+		case 1:
-+			wdata = (mac[2] | (mac[3] << 8) | (mac[4] << 16) | (mac[5] << 24));
-+			break;
-+		case 6:
-+		case 7:
-+			wdata = 0;
-+			break;
-+		default:
-+			i = (j - 2) << 2;
-+			wdata = (key[i] | (key[i + 1] << 8) | (key[i + 2] << 16) | (key[i + 3] << 24));
-+			break;
-+		}
-+
-+		addr = (id << 3) + j;
-+
-+#if defined(CONFIG_RTL8192F)
-+		if(j == 1) {
-+			wdata1 = wdata;
-+			addr1 = addr;
-+			continue;
-+		}
-+#endif
-+
-+		rtw_sec_write_cam(adapter, addr, wdata);
-+	}
-+
-+#if defined(CONFIG_RTL8192F)
-+	rtw_sec_write_cam(adapter, addr1, wdata1);
-+#endif
-+}
-+
-+void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id)
-+{
-+	u8 addr;
-+
-+	addr = (id << 3);
-+	rtw_sec_write_cam(adapter, addr, 0);
-+}
-+
-+bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id)
-+{
-+	bool res;
-+	u16 ctrl;
-+
-+	rtw_sec_read_cam_ent(adapter, id, (u8 *)&ctrl, NULL, NULL);
-+
-+	res = (ctrl & BIT6) ? _TRUE : _FALSE;
-+	return res;
-+}
-+#ifdef CONFIG_MBSSID_CAM
-+void rtw_mbid_cam_init(struct dvobj_priv *dvobj)
-+{
-+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
-+
-+	_rtw_spinlock_init(&mbid_cam_ctl->lock);
-+	mbid_cam_ctl->bitmap = 0;
-+	ATOMIC_SET(&mbid_cam_ctl->mbid_entry_num, 0);
-+	_rtw_memset(&dvobj->mbid_cam_cache, 0, sizeof(dvobj->mbid_cam_cache));
-+}
-+
-+void rtw_mbid_cam_deinit(struct dvobj_priv *dvobj)
-+{
-+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
-+
-+	_rtw_spinlock_free(&mbid_cam_ctl->lock);
-+}
-+
-+void rtw_mbid_cam_reset(_adapter *adapter)
-+{
-+	_irqL irqL;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
-+
-+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+	mbid_cam_ctl->bitmap = 0;
-+	_rtw_memset(&dvobj->mbid_cam_cache, 0, sizeof(dvobj->mbid_cam_cache));
-+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+
-+	ATOMIC_SET(&mbid_cam_ctl->mbid_entry_num, 0);
-+}
-+static u8 _rtw_mbid_cam_search_by_macaddr(_adapter *adapter, u8 *mac_addr)
-+{
-+	u8 i;
-+	u8 cam_id = INVALID_CAM_ID;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
-+		if (mac_addr && _rtw_memcmp(dvobj->mbid_cam_cache[i].mac_addr, mac_addr, ETH_ALEN) == _TRUE) {
-+			cam_id = i;
-+			break;
-+		}
-+	}
-+
-+	RTW_INFO("%s mac:"MAC_FMT" - cam_id:%d\n", __func__, MAC_ARG(mac_addr), cam_id);
-+	return cam_id;
-+}
-+
-+u8 rtw_mbid_cam_search_by_macaddr(_adapter *adapter, u8 *mac_addr)
-+{
-+	_irqL irqL;
-+
-+	u8 cam_id = INVALID_CAM_ID;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
-+
-+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+	cam_id = _rtw_mbid_cam_search_by_macaddr(adapter, mac_addr);
-+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+
-+	return cam_id;
-+}
-+static u8 _rtw_mbid_cam_search_by_ifaceid(_adapter *adapter, u8 iface_id)
-+{
-+	u8 i;
-+	u8 cam_id = INVALID_CAM_ID;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
-+		if (iface_id == dvobj->mbid_cam_cache[i].iface_id) {
-+			cam_id = i;
-+			break;
-+		}
-+	}
-+	if (cam_id != INVALID_CAM_ID)
-+		RTW_INFO("%s iface_id:%d mac:"MAC_FMT" - cam_id:%d\n",
-+			__func__, iface_id, MAC_ARG(dvobj->mbid_cam_cache[cam_id].mac_addr), cam_id);
-+
-+	return cam_id;
-+}
-+
-+u8 rtw_mbid_cam_search_by_ifaceid(_adapter *adapter, u8 iface_id)
-+{
-+	_irqL irqL;
-+	u8 cam_id = INVALID_CAM_ID;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
-+
-+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+	cam_id = _rtw_mbid_cam_search_by_ifaceid(adapter, iface_id);
-+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+
-+	return cam_id;
-+}
-+u8 rtw_get_max_mbid_cam_id(_adapter *adapter)
-+{
-+	_irqL irqL;
-+	s8 i;
-+	u8 cam_id = INVALID_CAM_ID;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
-+
-+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+	for (i = (TOTAL_MBID_CAM_NUM - 1); i >= 0; i--) {
-+		if (mbid_cam_ctl->bitmap & BIT(i)) {
-+			cam_id = i;
-+			break;
-+		}
-+	}
-+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+	/*RTW_INFO("%s max cam_id:%d\n", __func__, cam_id);*/
-+	return cam_id;
-+}
-+
-+inline u8 rtw_get_mbid_cam_entry_num(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
-+
-+	return ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);
-+}
-+
-+static inline void mbid_cam_cache_init(_adapter *adapter, struct mbid_cam_cache *pmbid_cam, u8 *mac_addr)
-+{
-+	if (adapter && pmbid_cam && mac_addr) {
-+		_rtw_memcpy(pmbid_cam->mac_addr, mac_addr, ETH_ALEN);
-+		pmbid_cam->iface_id = adapter->iface_id;
-+	}
-+}
-+static inline void mbid_cam_cache_clr(struct mbid_cam_cache *pmbid_cam)
-+{
-+	if (pmbid_cam) {
-+		_rtw_memset(pmbid_cam->mac_addr, 0, ETH_ALEN);
-+		pmbid_cam->iface_id = CONFIG_IFACE_NUMBER;
-+	}
-+}
-+
-+u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr)
-+{
-+	_irqL irqL;
-+	u8 cam_id = INVALID_CAM_ID, i;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
-+	u8 entry_num = ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);
-+
-+	if (INVALID_CAM_ID != rtw_mbid_cam_search_by_macaddr(adapter, mac_addr))
-+		goto exit;
-+
-+	if (entry_num >= TOTAL_MBID_CAM_NUM) {
-+		RTW_INFO(FUNC_ADPT_FMT" failed !! MBSSID number :%d over TOTAL_CAM_ENTRY(8)\n", FUNC_ADPT_ARG(adapter), entry_num);
-+		rtw_warn_on(1);
-+	}
-+
-+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
-+		if (!(mbid_cam_ctl->bitmap & BIT(i))) {
-+			mbid_cam_ctl->bitmap |= BIT(i);
-+			cam_id = i;
-+			break;
-+		}
-+	}
-+	if ((cam_id != INVALID_CAM_ID) && (mac_addr))
-+		mbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[cam_id], mac_addr);
-+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+
-+	if (cam_id != INVALID_CAM_ID) {
-+		ATOMIC_INC(&mbid_cam_ctl->mbid_entry_num);
-+		RTW_INFO("%s mac:"MAC_FMT" - cam_id:%d\n", __func__, MAC_ARG(mac_addr), cam_id);
-+#ifdef DBG_MBID_CAM_DUMP
-+		rtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);
-+#endif
-+	} else
-+		RTW_INFO("%s [WARN] "MAC_FMT" - invalid cam_id:%d\n", __func__, MAC_ARG(mac_addr), cam_id);
-+exit:
-+	return cam_id;
-+}
-+
-+u8 rtw_mbid_cam_info_change(_adapter *adapter, u8 *mac_addr)
-+{
-+	_irqL irqL;
-+	u8 entry_id = INVALID_CAM_ID;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
-+
-+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+	entry_id = _rtw_mbid_cam_search_by_ifaceid(adapter, adapter->iface_id);
-+	if (entry_id != INVALID_CAM_ID)
-+		mbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[entry_id], mac_addr);
-+
-+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+
-+	return entry_id;
-+}
-+
-+u8 rtw_mbid_cam_assign(_adapter *adapter, u8 *mac_addr, u8 camid)
-+{
-+	_irqL irqL;
-+	u8 ret = _FALSE;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
-+
-+	if ((camid >= TOTAL_MBID_CAM_NUM) || (camid == INVALID_CAM_ID)) {
-+		RTW_INFO(FUNC_ADPT_FMT" failed !! invlaid mbid_canid :%d\n", FUNC_ADPT_ARG(adapter), camid);
-+		rtw_warn_on(1);
-+	}
-+	if (INVALID_CAM_ID != rtw_mbid_cam_search_by_macaddr(adapter, mac_addr))
-+		goto exit;
-+
-+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+	if (!(mbid_cam_ctl->bitmap & BIT(camid))) {
-+		if (mac_addr) {
-+			mbid_cam_ctl->bitmap |= BIT(camid);
-+			mbid_cam_cache_init(adapter, &dvobj->mbid_cam_cache[camid], mac_addr);
-+			ret = _TRUE;
-+		}
-+	}
-+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+
-+	if (ret == _TRUE) {
-+		ATOMIC_INC(&mbid_cam_ctl->mbid_entry_num);
-+		RTW_INFO("%s mac:"MAC_FMT" - cam_id:%d\n", __func__, MAC_ARG(mac_addr), camid);
-+#ifdef DBG_MBID_CAM_DUMP
-+		rtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);
-+#endif
-+	} else
-+		RTW_INFO("%s  [WARN] mac:"MAC_FMT" - cam_id:%d assigned failed\n", __func__, MAC_ARG(mac_addr), camid);
-+
-+exit:
-+	return ret;
-+}
-+
-+void rtw_mbid_camid_clean(_adapter *adapter, u8 mbss_canid)
-+{
-+	_irqL irqL;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
-+
-+	if ((mbss_canid >= TOTAL_MBID_CAM_NUM) || (mbss_canid == INVALID_CAM_ID)) {
-+		RTW_INFO(FUNC_ADPT_FMT" failed !! invlaid mbid_canid :%d\n", FUNC_ADPT_ARG(adapter), mbss_canid);
-+		rtw_warn_on(1);
-+	}
-+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+	mbid_cam_cache_clr(&dvobj->mbid_cam_cache[mbss_canid]);
-+	mbid_cam_ctl->bitmap &= (~BIT(mbss_canid));
-+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+	ATOMIC_DEC(&mbid_cam_ctl->mbid_entry_num);
-+	RTW_INFO("%s - cam_id:%d\n", __func__, mbss_canid);
-+}
-+int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name, _adapter *adapter)
-+{
-+	_irqL irqL;
-+	u8 i;
-+	_adapter *iface;
-+	u8 iface_id;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
-+	u8 entry_num = ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num);
-+	u8 max_cam_id = rtw_get_max_mbid_cam_id(adapter);
-+
-+	RTW_PRINT_SEL(sel, "== MBSSID CAM DUMP (%s)==\n", fun_name);
-+
-+	_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+	RTW_PRINT_SEL(sel, "Entry numbers:%d, max_camid:%d, bitmap:0x%08x\n", entry_num, max_cam_id, mbid_cam_ctl->bitmap);
-+	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
-+		RTW_PRINT_SEL(sel, "CAM_ID = %d\t", i);
-+
-+		if (mbid_cam_ctl->bitmap & BIT(i)) {
-+			iface_id = dvobj->mbid_cam_cache[i].iface_id;
-+			_RTW_PRINT_SEL(sel, "IF_ID:%d\t", iface_id);
-+			_RTW_PRINT_SEL(sel, "MAC Addr:"MAC_FMT"\t", MAC_ARG(dvobj->mbid_cam_cache[i].mac_addr));
-+
-+			iface = dvobj->padapters[iface_id];
-+			if (iface) {
-+				if (MLME_IS_STA(iface))
-+					_RTW_PRINT_SEL(sel, "ROLE:%s\n", "STA");
-+				else if (MLME_IS_AP(iface))
-+					_RTW_PRINT_SEL(sel, "ROLE:%s\n", "AP");
-+				else if (MLME_IS_MESH(iface))
-+					_RTW_PRINT_SEL(sel, "ROLE:%s\n", "MESH");
-+				else
-+					_RTW_PRINT_SEL(sel, "ROLE:%s\n", "NONE");
-+			}
-+
-+		} else
-+			_RTW_PRINT_SEL(sel, "N/A\n");
-+	}
-+	_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);
-+	return 0;
-+}
-+
-+static void read_mbssid_cam(_adapter *padapter, u8 cam_addr, u8 *mac)
-+{
-+	u8 poll = 1;
-+	u8 cam_ready = _FALSE;
-+	u32 cam_data1 = 0;
-+	u16 cam_data2 = 0;
-+
-+	if (RTW_CANNOT_RUN(padapter))
-+		return;
-+
-+	rtw_write32(padapter, REG_MBIDCAMCFG_2, BIT_MBIDCAM_POLL | ((cam_addr & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT));
-+
-+	do {
-+		if (0 == (rtw_read32(padapter, REG_MBIDCAMCFG_2) & BIT_MBIDCAM_POLL)) {
-+			cam_ready = _TRUE;
-+			break;
-+		}
-+		poll++;
-+	} while ((poll % 10) != 0 && !RTW_CANNOT_RUN(padapter));
-+
-+	if (cam_ready) {
-+		cam_data1 = rtw_read32(padapter, REG_MBIDCAMCFG_1);
-+		mac[0] = cam_data1 & 0xFF;
-+		mac[1] = (cam_data1 >> 8) & 0xFF;
-+		mac[2] = (cam_data1 >> 16) & 0xFF;
-+		mac[3] = (cam_data1 >> 24) & 0xFF;
-+
-+		cam_data2 = rtw_read16(padapter, REG_MBIDCAMCFG_2);
-+		mac[4] = cam_data2 & 0xFF;
-+		mac[5] = (cam_data2 >> 8) & 0xFF;
-+	}
-+
-+}
-+int rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter)
-+{
-+	/*_irqL irqL;*/
-+	u8 i;
-+	u8 mac_addr[ETH_ALEN];
-+
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
-+
-+	RTW_PRINT_SEL(sel, "\n== MBSSID HW-CAM DUMP (%s)==\n", fun_name);
-+
-+	/*_enter_critical_bh(&mbid_cam_ctl->lock, &irqL);*/
-+	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
-+		RTW_PRINT_SEL(sel, "CAM_ID = %d\t", i);
-+		_rtw_memset(mac_addr, 0, ETH_ALEN);
-+		read_mbssid_cam(adapter, i, mac_addr);
-+		_RTW_PRINT_SEL(sel, "MAC Addr:"MAC_FMT"\n", MAC_ARG(mac_addr));
-+	}
-+	/*_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);*/
-+	return 0;
-+}
-+
-+static void write_mbssid_cam(_adapter *padapter, u8 cam_addr, u8 *mac)
-+{
-+	u32	cam_val[2] = {0};
-+
-+	cam_val[0] = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0];
-+	cam_val[1] = ((cam_addr & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT)  | (mac[5] << 8) | mac[4];
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_MBSSID_CAM_WRITE, (u8 *)cam_val);
-+}
-+
-+/*
-+static void clear_mbssid_cam(_adapter *padapter, u8 cam_addr)
-+{
-+	rtw_hal_set_hwreg(padapter, HW_VAR_MBSSID_CAM_CLEAR, &cam_addr);
-+}
-+*/
-+
-+void rtw_ap_set_mbid_num(_adapter *adapter, u8 ap_num)
-+{
-+	rtw_write8(adapter, REG_MBID_NUM,
-+		((rtw_read8(adapter, REG_MBID_NUM) & 0xF8) | ((ap_num -1) & 0x07)));
-+
-+}
-+void rtw_mbid_cam_enable(_adapter *adapter)
-+{
-+	/*enable MBSSID*/
-+	rtw_hal_rcr_add(adapter, RCR_ENMBID);
-+}
-+void rtw_mi_set_mbid_cam(_adapter *adapter)
-+{
-+	u8 i;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl;
-+
-+#ifdef DBG_MBID_CAM_DUMP
-+	rtw_mbid_cam_cache_dump(RTW_DBGDUMP, __func__, adapter);
-+#endif
-+
-+	for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) {
-+		if (mbid_cam_ctl->bitmap & BIT(i)) {
-+			write_mbssid_cam(adapter, i, dvobj->mbid_cam_cache[i].mac_addr);
-+			RTW_INFO("%s - cam_id:%d => mac:"MAC_FMT"\n", __func__, i, MAC_ARG(dvobj->mbid_cam_cache[i].mac_addr));
-+		}
-+	}
-+	rtw_mbid_cam_enable(adapter);
-+}
-+#endif /*CONFIG_MBSSID_CAM*/
-+
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+#define H2C_BCN_OFFLOAD_LEN	1
-+
-+#define SET_H2CCMD_BCN_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_H2CCMD_BCN_ROOT_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_H2CCMD_BCN_VAP1_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_H2CCMD_BCN_VAP2_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
-+#define SET_H2CCMD_BCN_VAP3_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
-+#define SET_H2CCMD_BCN_VAP4_TBTT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
-+
-+void rtw_hal_set_fw_ap_bcn_offload_cmd(_adapter *adapter, bool fw_bcn_en, u8 tbtt_rpt_map)
-+{
-+	u8 fw_bcn_offload[1] = {0};
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	if (fw_bcn_en)
-+		SET_H2CCMD_BCN_OFFLOAD_EN(fw_bcn_offload, 1);
-+
-+	if (tbtt_rpt_map & BIT(0))
-+		SET_H2CCMD_BCN_ROOT_TBTT_RPT(fw_bcn_offload, 1);
-+	if (tbtt_rpt_map & BIT(1))
-+		SET_H2CCMD_BCN_VAP1_TBTT_RPT(fw_bcn_offload, 1);
-+	if (tbtt_rpt_map & BIT(2))
-+		SET_H2CCMD_BCN_VAP2_TBTT_RPT(fw_bcn_offload, 1);
-+	if (tbtt_rpt_map & BIT(3))
-+			SET_H2CCMD_BCN_VAP3_TBTT_RPT(fw_bcn_offload, 1);
-+
-+	dvobj->vap_tbtt_rpt_map = tbtt_rpt_map;
-+	dvobj->fw_bcn_offload = fw_bcn_en;
-+	RTW_INFO("[FW BCN] Offload : %s\n", (dvobj->fw_bcn_offload) ? "EN" : "DIS");
-+	RTW_INFO("[FW BCN] TBTT RPT map : 0x%02x\n", dvobj->vap_tbtt_rpt_map);
-+
-+	rtw_hal_fill_h2c_cmd(adapter, H2C_FW_BCN_OFFLOAD,
-+					H2C_BCN_OFFLOAD_LEN, fw_bcn_offload);
-+}
-+
-+void rtw_hal_set_bcn_rsvdpage_loc_cmd(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	u8 ret, vap_id;
-+	u32 page_size = 0;
-+	u8 bcn_rsvdpage[H2C_BCN_RSVDPAGE_LEN] = {0};
-+
-+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&page_size);
-+	#if 1
-+	for (vap_id = 0; vap_id < CONFIG_LIMITED_AP_NUM; vap_id++) {
-+		if (dvobj->vap_map & BIT(vap_id))
-+			bcn_rsvdpage[vap_id] = vap_id * (MAX_BEACON_LEN / page_size);
-+	}
-+	#else
-+#define SET_H2CCMD_BCN_RSVDPAGE_LOC_ROOT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP1(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 8, __Value)
-+#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP2(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 8, __Value)
-+#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP3(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 8, __Value)
-+#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP4(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 8, __Value)
-+
-+	if (dvobj->vap_map & BIT(0))
-+ 		SET_H2CCMD_BCN_RSVDPAGE_LOC_ROOT(bcn_rsvdpage, 0);
-+	if (dvobj->vap_map & BIT(1))
-+		SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP1(bcn_rsvdpage,
-+					1 * (MAX_BEACON_LEN / page_size));
-+	if (dvobj->vap_map & BIT(2))
-+		SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP2(bcn_rsvdpage,
-+					2 * (MAX_BEACON_LEN / page_size));
-+	if (dvobj->vap_map & BIT(3))
-+		SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP3(bcn_rsvdpage,
-+					3 * (MAX_BEACON_LEN / page_size));
-+	if (dvobj->vap_map & BIT(4))
-+		SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP4(bcn_rsvdpage,
-+					4 * (MAX_BEACON_LEN / page_size));
-+	#endif
-+	if (1) {
-+		RTW_INFO("[BCN_LOC] vap_map : 0x%02x\n", dvobj->vap_map);
-+		RTW_INFO("[BCN_LOC] page_size :%d, @bcn_page_num :%d\n"
-+			, page_size, (MAX_BEACON_LEN / page_size));
-+		RTW_INFO("[BCN_LOC] root ap : 0x%02x\n", *bcn_rsvdpage);
-+		RTW_INFO("[BCN_LOC] vap_1 : 0x%02x\n", *(bcn_rsvdpage + 1));
-+		RTW_INFO("[BCN_LOC] vap_2 : 0x%02x\n", *(bcn_rsvdpage + 2));
-+		RTW_INFO("[BCN_LOC] vap_3 : 0x%02x\n", *(bcn_rsvdpage + 3));
-+		RTW_INFO("[BCN_LOC] vap_4 : 0x%02x\n", *(bcn_rsvdpage + 4));
-+	}
-+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_BCN_RSVDPAGE,
-+					H2C_BCN_RSVDPAGE_LEN, bcn_rsvdpage);
-+}
-+
-+void rtw_ap_multi_bcn_cfg(_adapter *adapter)
-+{
-+	u8 dft_bcn_space = DEFAULT_BCN_INTERVAL;
-+	u8 sub_bcn_space = (DEFAULT_BCN_INTERVAL / CONFIG_LIMITED_AP_NUM);
-+
-+	/*enable to rx data frame*/
-+	rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
-+
-+	/*Disable Port0's beacon function*/
-+	rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL) & ~BIT_EN_BCN_FUNCTION);
-+	/*Reset Port0's TSF*/
-+	rtw_write8(adapter, REG_DUAL_TSF_RST, BIT_TSFTR_RST);
-+
-+	rtw_ap_set_mbid_num(adapter, CONFIG_LIMITED_AP_NUM);
-+
-+	/*BCN space & BCN sub-space 0x554[15:0] = 0x64,0x5BC[23:16] = 0x21*/
-+	rtw_halmac_set_bcn_interval(adapter_to_dvobj(adapter), HW_PORT0, dft_bcn_space);
-+	rtw_write8(adapter, REG_MBSSID_BCN_SPACE3 + 2, sub_bcn_space);
-+
-+	#if 0 /*setting in hw_var_set_opmode_mbid - ResumeTxBeacon*/
-+	/*BCN hold time  0x540[19:8] = 0x80*/
-+	rtw_write8(adapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME & 0xFF);
-+	rtw_write8(adapter, REG_TBTT_PROHIBIT + 2,
-+		(rtw_read8(adapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME >> 8));
-+	#endif
-+
-+	/*ATIM window -0x55A = 0x32, reg 0x570 = 0x32, reg 0x5A0 = 0x32 */
-+	rtw_write8(adapter, REG_ATIMWND, 0x32);
-+	rtw_write8(adapter, REG_ATIMWND1_V1, 0x32);
-+	rtw_write8(adapter, REG_ATIMWND2, 0x32);
-+	rtw_write8(adapter, REG_ATIMWND3, 0x32);
-+	/*
-+	rtw_write8(adapter, REG_ATIMWND4, 0x32);
-+	rtw_write8(adapter, REG_ATIMWND5, 0x32);
-+	rtw_write8(adapter, REG_ATIMWND6, 0x32);
-+	rtw_write8(adapter, REG_ATIMWND7, 0x32);*/
-+
-+	/*no limit setting - 0x5A7 = 0xFF - Packet in Hi Queue Tx immediately*/
-+	rtw_write8(adapter, REG_HIQ_NO_LMT_EN, 0xFF);
-+
-+	/*Mask all beacon*/
-+	rtw_write8(adapter, REG_MBSSID_CTRL, 0);
-+
-+	/*BCN invalid bit setting 0x454[6] = 1*/
-+	/*rtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) | BIT_EN_BCN_PKT_REL);*/
-+
-+	/*Enable Port0's beacon function*/
-+	rtw_write8(adapter, REG_BCN_CTRL,
-+	rtw_read8(adapter, REG_BCN_CTRL) | BIT_DIS_RX_BSSID_FIT | BIT_P0_EN_TXBCN_RPT | BIT_DIS_TSF_UDT  | BIT_EN_BCN_FUNCTION);
-+
-+	/* Enable HW seq for BCN
-+	* 0x4FC[0]: EN_HWSEQ / 0x4FC[1]: EN_HWSEQEXT  */
-+	 #ifdef CONFIG_RTL8822B
-+	if (IS_HARDWARE_TYPE_8822B(adapter))
-+		rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822B, 0x01);
-+	#endif
-+
-+	 #ifdef CONFIG_RTL8822C
-+	if (IS_HARDWARE_TYPE_8822C(adapter))
-+		rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822C, 0x01);
-+	#endif
-+}
-+static void _rtw_mbid_bcn_cfg(_adapter *adapter, bool mbcnq_en, u8 mbcnq_id)
-+{
-+	if (mbcnq_id >= CONFIG_LIMITED_AP_NUM) {
-+		RTW_ERR(FUNC_ADPT_FMT"- mbid bcnq_id(%d) invalid\n", FUNC_ADPT_ARG(adapter), mbcnq_id);
-+		rtw_warn_on(1);
-+	}
-+
-+	if (mbcnq_en) {
-+		rtw_write8(adapter, REG_MBSSID_CTRL,
-+			rtw_read8(adapter, REG_MBSSID_CTRL) | BIT(mbcnq_id));
-+		RTW_INFO(FUNC_ADPT_FMT"- mbid bcnq_id(%d) enabled\n", FUNC_ADPT_ARG(adapter), mbcnq_id);
-+	} else {
-+		rtw_write8(adapter, REG_MBSSID_CTRL,
-+			rtw_read8(adapter, REG_MBSSID_CTRL) & (~BIT(mbcnq_id)));
-+		RTW_INFO(FUNC_ADPT_FMT"- mbid bcnq_id(%d) disabled\n", FUNC_ADPT_ARG(adapter), mbcnq_id);
-+	}
-+}
-+/*#define CONFIG_FW_TBTT_RPT*/
-+void rtw_ap_mbid_bcn_en(_adapter *adapter, u8 ap_id)
-+{
-+	RTW_INFO(FUNC_ADPT_FMT"- ap_id(%d)\n", FUNC_ADPT_ARG(adapter), ap_id);
-+
-+	#ifdef CONFIG_FW_TBTT_RPT
-+	if (rtw_ap_get_nums(adapter) >= 1) {
-+		u8 tbtt_rpt_map = adapter_to_dvobj(adapter)->vap_tbtt_rpt_map;
-+
-+		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE,
-+			tbtt_rpt_map | BIT(ap_id));/*H2C-0xBA*/
-+	}
-+	#else
-+	if (rtw_ap_get_nums(adapter) == 1)
-+		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE, 0);/*H2C-0xBA*/
-+	#endif
-+
-+	rtw_hal_set_bcn_rsvdpage_loc_cmd(adapter);/*H2C-0x09*/
-+
-+	_rtw_mbid_bcn_cfg(adapter, _TRUE, ap_id);
-+}
-+void rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 ap_id)
-+{
-+	RTW_INFO(FUNC_ADPT_FMT"- ap_id(%d)\n", FUNC_ADPT_ARG(adapter), ap_id);
-+	_rtw_mbid_bcn_cfg(adapter, _FALSE, ap_id);
-+
-+	if (rtw_ap_get_nums(adapter) == 0)
-+		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _FALSE, 0);
-+	#ifdef CONFIG_FW_TBTT_RPT
-+	else if (rtw_ap_get_nums(adapter) >= 1) {
-+		u8 tbtt_rpt_map = adapter_to_dvobj(adapter)->vap_tbtt_rpt_map;
-+
-+		rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE,
-+			tbtt_rpt_map & ~BIT(ap_id));/*H2C-0xBA*/
-+	}
-+	#endif
-+}
-+#endif
-+#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+void rtw_ap_multi_bcn_cfg(_adapter *adapter)
-+{
-+	#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
-+	rtw_write8(adapter, REG_BCN_CTRL, DIS_TSF_UDT);
-+	#else
-+	rtw_write8(adapter, REG_BCN_CTRL, DIS_TSF_UDT | DIS_BCNQ_SUB);
-+	#endif
-+	/*enable to rx data frame*/
-+	rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
-+
-+	/*Beacon Control related register for first time*/
-+	rtw_write8(adapter, REG_BCNDMATIM, 0x02); /* 2ms */
-+
-+	/*rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);*/
-+	rtw_write8(adapter, REG_ATIMWND, 0x0c); /* 12ms */
-+
-+	#ifndef CONFIG_HW_P0_TSF_SYNC
-+	rtw_write16(adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
-+	#endif
-+
-+	/*reset TSF*/
-+	rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(0));
-+
-+	/*enable BCN0 Function for if1*/
-+	/*don't enable update TSF0 for if1 (due to TSF update when beacon,probe rsp are received)*/
-+	#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
-+	rtw_write8(adapter, REG_BCN_CTRL, BIT_DIS_RX_BSSID_FIT | BIT_P0_EN_TXBCN_RPT | BIT_DIS_TSF_UDT |BIT_EN_BCN_FUNCTION);
-+	#else
-+	rtw_write8(adapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
-+	#endif
-+	#ifdef CONFIG_BCN_XMIT_PROTECT
-+	rtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) | BIT_EN_BCN_PKT_REL);
-+	#endif
-+
-+	if (IS_HARDWARE_TYPE_8821(adapter) || IS_HARDWARE_TYPE_8192E(adapter))/* select BCN on port 0 for DualBeacon*/
-+		rtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) & (~BIT_BCN_PORT_SEL));
-+
-+	/* Enable HW seq for BCN 
-+	 * 0x4FC[0]: EN_HWSEQ / 0x4FC[1]: EN_HWSEQEXT  */
-+	#ifdef CONFIG_RTL8822B
-+	if (IS_HARDWARE_TYPE_8822B(adapter))
-+		rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822B, 0x01);
-+	#endif
-+
-+	#ifdef CONFIG_RTL8822C
-+	if (IS_HARDWARE_TYPE_8822C(adapter))
-+		rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822C, 0x01);
-+	#endif
-+}
-+#endif
-+
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr)
-+{
-+
-+#if 0 /*TODO - modify for more flexible*/
-+	u8 idx = 0;
-+
-+	if ((check_fwstate(&adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) &&
-+	    (DEV_STA_NUM(adapter_to_dvobj(adapter)) == 1)) {
-+		for (idx = 0; idx < 6; idx++)
-+			rtw_write8(GET_PRIMARY_ADAPTER(adapter), (REG_MACID + idx), val[idx]);
-+	}  else {
-+		/*MBID entry_id = 0~7 ,0 for root AP, 1~7 for VAP*/
-+		u8 entry_id;
-+
-+		if ((check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) &&
-+		    (DEV_AP_NUM(adapter_to_dvobj(adapter)) == 1)) {
-+			entry_id = 0;
-+			if (rtw_mbid_cam_assign(adapter, val, entry_id)) {
-+				RTW_INFO(FUNC_ADPT_FMT" Root AP assigned success\n", FUNC_ADPT_ARG(adapter));
-+				write_mbssid_cam(adapter, entry_id, val);
-+			}
-+		} else {
-+			entry_id = rtw_mbid_camid_alloc(adapter, val);
-+			if (entry_id != INVALID_CAM_ID)
-+				write_mbssid_cam(adapter, entry_id, val);
-+		}
-+	}
-+#else
-+	{
-+		/*
-+			MBID entry_id = 0~7 ,for IFACE_ID0 ~ IFACE_IDx
-+		*/
-+		u8 entry_id = rtw_mbid_camid_alloc(adapter, mac_addr);
-+
-+
-+		if (entry_id != INVALID_CAM_ID) {
-+			write_mbssid_cam(adapter, entry_id, mac_addr);
-+			RTW_INFO("%s "ADPT_FMT"- mbid(%d) mac_addr ="MAC_FMT"\n", __func__,
-+				ADPT_ARG(adapter), entry_id, MAC_ARG(mac_addr));
-+		}
-+	}
-+#endif
-+}
-+
-+void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr)
-+{
-+	u8 idx = 0;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	u8 entry_id;
-+
-+	if (!mac_addr) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+
-+	entry_id = rtw_mbid_cam_info_change(adapter, mac_addr);
-+
-+	if (entry_id != INVALID_CAM_ID)
-+		write_mbssid_cam(adapter, entry_id, mac_addr);
-+}
-+
-+#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval)
-+{
-+	if (adapter_to_dvobj(adapter)->inter_bcn_space != bcn_interval)
-+		return adapter_to_dvobj(adapter)->inter_bcn_space;
-+	else
-+		return bcn_interval;
-+}
-+#endif/*CONFIG_SWTIMER_BASED_TXBCN*/
-+
-+#else
-+
-+#ifndef RTW_HALMAC
-+static u32 _get_macaddr_reg(enum _hw_port hwport)
-+{
-+	u32 reg_macaddr = REG_MACID;
-+
-+	#ifdef CONFIG_CONCURRENT_MODE
-+	if (hwport == HW_PORT1)
-+		reg_macaddr = REG_MACID1;
-+	#if defined(CONFIG_RTL8814A)
-+	else if (hwport == HW_PORT2)
-+		reg_macaddr = REG_MACID2;
-+	else if (hwport == HW_PORT3)
-+		reg_macaddr = REG_MACID3;
-+	else if (hwport == HW_PORT4)
-+		reg_macaddr = REG_MACID4;
-+	#endif /*CONFIG_RTL8814A*/
-+	#endif /*CONFIG_CONCURRENT_MODE*/
-+
-+	return reg_macaddr;
-+}
-+#endif /*!RTW_HALMAC*/
-+
-+static void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *mac_addr)
-+{
-+	enum _hw_port hwport;
-+
-+	if (mac_addr == NULL)
-+		return;
-+	hwport = get_hw_port(adapter);
-+
-+	RTW_INFO("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n",  __func__,
-+		 ADPT_ARG(adapter), hwport, MAC_ARG(mac_addr));
-+
-+#ifdef RTW_HALMAC /*8822B ~ 8814B*/
-+	rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), hwport, mac_addr);
-+#else /* !RTW_HALMAC */
-+	{
-+		u8 idx = 0;
-+		u32 reg_macaddr = _get_macaddr_reg(hwport);
-+
-+		for (idx = 0; idx < ETH_ALEN; idx++)
-+			rtw_write8(GET_PRIMARY_ADAPTER(adapter), (reg_macaddr + idx), mac_addr[idx]);
-+	}
-+#endif /* !RTW_HALMAC */
-+}
-+
-+static void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr)
-+{
-+	enum _hw_port hwport;
-+
-+	if (mac_addr == NULL)
-+		return;
-+	hwport = get_hw_port(adapter);
-+
-+	_rtw_memset(mac_addr, 0, ETH_ALEN);
-+#ifdef RTW_HALMAC /*8822B ~ 8814B*/
-+	rtw_halmac_get_mac_address(adapter_to_dvobj(adapter), hwport, mac_addr);
-+#else /* !RTW_HALMAC */
-+	{
-+		u8 idx = 0;
-+		u32 reg_macaddr = _get_macaddr_reg(hwport);
-+
-+		for (idx = 0; idx < ETH_ALEN; idx++)
-+			mac_addr[idx] = rtw_read8(GET_PRIMARY_ADAPTER(adapter), (reg_macaddr + idx));
-+	}
-+#endif /* !RTW_HALMAC */
-+
-+	RTW_DBG("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n",  __func__,
-+		 ADPT_ARG(adapter), hwport, MAC_ARG(mac_addr));
-+}
-+#endif/*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/
-+
-+#ifndef RTW_HALMAC
-+static u32 _get_bssid_reg(enum _hw_port hw_port)
-+{
-+	u32 reg_bssid = REG_BSSID;
-+
-+	#ifdef CONFIG_CONCURRENT_MODE
-+	if (hw_port == HW_PORT1)
-+		reg_bssid = REG_BSSID1;
-+	#if defined(CONFIG_RTL8814A)
-+	else if (hw_port == HW_PORT2)
-+		reg_bssid = REG_BSSID2;
-+	else if (hw_port == HW_PORT3)
-+		reg_bssid = REG_BSSID3;
-+	else if (hw_port == HW_PORT4)
-+		reg_bssid = REG_BSSID4;
-+	#endif /*CONFIG_RTL8814A*/
-+	#endif /*CONFIG_CONCURRENT_MODE*/
-+
-+	return reg_bssid;
-+}
-+#endif /*!RTW_HALMAC*/
-+static void rtw_hal_set_bssid(_adapter *adapter, u8 *val)
-+{
-+	enum _hw_port hw_port = rtw_hal_get_port(adapter);
-+#ifdef RTW_HALMAC
-+
-+	rtw_halmac_set_bssid(adapter_to_dvobj(adapter), hw_port, val);
-+#else /* !RTW_HALMAC */
-+	u8 idx = 0;
-+	u32 reg_bssid = _get_bssid_reg(hw_port);
-+
-+	for (idx = 0 ; idx < ETH_ALEN; idx++)
-+		rtw_write8(adapter, (reg_bssid + idx), val[idx]);
-+#endif /* !RTW_HALMAC */
-+
-+	RTW_INFO("%s "ADPT_FMT"- hw port -%d BSSID: "MAC_FMT"\n",
-+		__func__, ADPT_ARG(adapter), hw_port, MAC_ARG(val));
-+}
-+
-+#ifndef CONFIG_MI_WITH_MBSSID_CAM
-+static void rtw_hal_set_tsf_update(_adapter *adapter, u8 en)
-+{
-+	u32 addr = 0;
-+	u8 val8;
-+
-+	rtw_hal_get_hwreg(adapter, HW_VAR_BCN_CTRL_ADDR, (u8 *)&addr);
-+	if (addr) {
-+		rtw_enter_protsel_port(adapter, get_hw_port(adapter));
-+		val8 = rtw_read8(adapter, addr);
-+		if (en && (val8 & DIS_TSF_UDT)) {
-+			rtw_write8(adapter, addr, val8 & ~DIS_TSF_UDT);
-+			#ifdef DBG_TSF_UPDATE
-+			RTW_INFO("port%u("ADPT_FMT") enable TSF update\n", adapter->hw_port, ADPT_ARG(adapter));
-+			#endif
-+		}
-+		if (!en && !(val8 & DIS_TSF_UDT)) {
-+			rtw_write8(adapter, addr, val8 | DIS_TSF_UDT);
-+			#ifdef DBG_TSF_UPDATE
-+			RTW_INFO("port%u("ADPT_FMT") disable TSF update\n", adapter->hw_port, ADPT_ARG(adapter));
-+			#endif
-+		}
-+		rtw_leave_protsel_port(adapter);
-+	} else {
-+		RTW_WARN("unknown port%d("ADPT_FMT") %s TSF update\n"
-+			, adapter->hw_port, ADPT_ARG(adapter), en ? "enable" : "disable");
-+		rtw_warn_on(1);
-+	}
-+}
-+#endif /*CONFIG_MI_WITH_MBSSID_CAM*/
-+static void rtw_hal_set_hw_update_tsf(PADAPTER padapter)
-+{
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+
-+#else
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+
-+	if (!pmlmeext->en_hw_update_tsf)
-+		return;
-+
-+	/* check RCR */
-+	if (!rtw_hal_rcr_check(padapter, RCR_CBSSID_BCN))
-+		return;
-+
-+	if (pmlmeext->tsf_update_required) {
-+		pmlmeext->tsf_update_pause_stime = 0;
-+		rtw_hal_set_tsf_update(padapter, 1);
-+	}
-+
-+	pmlmeext->en_hw_update_tsf = 0;
-+#endif
-+}
-+
-+void rtw_iface_enable_tsf_update(_adapter *adapter)
-+{
-+	adapter->mlmeextpriv.tsf_update_pause_stime = 0;
-+	adapter->mlmeextpriv.tsf_update_required = 1;
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+
-+#else
-+	rtw_hal_set_tsf_update(adapter, 1);
-+#endif
-+}
-+
-+void rtw_iface_disable_tsf_update(_adapter *adapter)
-+{
-+	adapter->mlmeextpriv.tsf_update_required = 0;
-+	adapter->mlmeextpriv.tsf_update_pause_stime = 0;
-+	adapter->mlmeextpriv.en_hw_update_tsf = 0;
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+
-+#else
-+	rtw_hal_set_tsf_update(adapter, 0);
-+#endif
-+}
-+
-+static void rtw_hal_tsf_update_pause(_adapter *adapter)
-+{
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+
-+#else
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	_adapter *iface;
-+	int i;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+
-+		rtw_hal_set_tsf_update(iface, 0);
-+		if (iface->mlmeextpriv.tsf_update_required) {
-+			iface->mlmeextpriv.tsf_update_pause_stime = rtw_get_current_time();
-+			if (!iface->mlmeextpriv.tsf_update_pause_stime)
-+				iface->mlmeextpriv.tsf_update_pause_stime++;
-+		}
-+		iface->mlmeextpriv.en_hw_update_tsf = 0;
-+	}
-+#endif
-+}
-+
-+static void rtw_hal_tsf_update_restore(_adapter *adapter)
-+{
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+
-+#else
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	_adapter *iface;
-+	int i;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+
-+		if (iface->mlmeextpriv.tsf_update_required) {
-+			/* enable HW TSF update when recive beacon*/
-+			iface->mlmeextpriv.en_hw_update_tsf = 1;
-+			#ifdef DBG_TSF_UPDATE
-+			RTW_INFO("port%d("ADPT_FMT") enabling TSF update...\n"
-+				, iface->hw_port, ADPT_ARG(iface));
-+			#endif
-+		}
-+	}
-+#endif
-+}
-+
-+void rtw_hal_periodic_tsf_update_chk(_adapter *adapter)
-+{
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+
-+#else
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	_adapter *iface;
-+	struct mlme_ext_priv *mlmeext;
-+	int i;
-+	u32 restore_ms = 0;
-+
-+	if (dvobj->periodic_tsf_update_etime) {
-+		if (rtw_time_after(rtw_get_current_time(), dvobj->periodic_tsf_update_etime)) {
-+			/* end for restore status */
-+			dvobj->periodic_tsf_update_etime = 0;
-+			rtw_hal_rcr_set_chk_bssid(adapter, MLME_ACTION_NONE);
-+		}
-+		return;
-+	}
-+
-+	if (dvobj->rf_ctl.offch_state != OFFCHS_NONE)
-+		return;
-+
-+	/*
-+	* all required ifaces can switch to restore status together
-+	* loop all pause iface to get largest restore time required
-+	*/
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+
-+		mlmeext = &iface->mlmeextpriv;
-+
-+		if (mlmeext->tsf_update_required
-+			&& mlmeext->tsf_update_pause_stime
-+			&& rtw_get_passing_time_ms(mlmeext->tsf_update_pause_stime)
-+				> mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_pause_factor
-+		) {
-+			if (restore_ms < mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_restore_factor)
-+				restore_ms = mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_restore_factor;
-+		}
-+	}
-+
-+	if (!restore_ms)
-+		return;
-+
-+	dvobj->periodic_tsf_update_etime = rtw_get_current_time() + rtw_ms_to_systime(restore_ms);
-+	if (!dvobj->periodic_tsf_update_etime)
-+		dvobj->periodic_tsf_update_etime++;
-+
-+	rtw_hal_rcr_set_chk_bssid(adapter, MLME_ACTION_NONE);
-+
-+	/* set timer to end restore status */
-+	_set_timer(&dvobj->periodic_tsf_update_end_timer, restore_ms);
-+#endif
-+}
-+
-+void rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx)
-+{
-+	struct dvobj_priv *dvobj = (struct dvobj_priv *)ctx;
-+
-+	if (dev_is_surprise_removed(dvobj) || dev_is_drv_stopped(dvobj))
-+		return;
-+
-+	rtw_periodic_tsf_update_end_cmd(dvobj_get_primary_adapter(dvobj));
-+}
-+
-+static inline u8 hw_var_rcr_config(_adapter *adapter, u32 rcr)
-+{
-+	int err;
-+
-+#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
-+	rcr = RCR_AAP | RCR_APM | RCR_AM | RCR_AB | RCR_APWRMGT | RCR_ADF | RCR_AMF | RCR_APP_PHYST_RXFF | RCR_APP_MIC | RCR_APP_ICV;
-+#endif
-+	err = rtw_write32(adapter, REG_RCR, rcr);
-+	if (err == _SUCCESS)
-+		GET_HAL_DATA(adapter)->ReceiveConfig = rcr;
-+	return err;
-+}
-+
-+static inline u8 hw_var_rcr_get(_adapter *adapter, u32 *rcr)
-+{
-+	u32 v32;
-+
-+	v32 = rtw_read32(adapter, REG_RCR);
-+	if (rcr)
-+		*rcr = v32;
-+	GET_HAL_DATA(adapter)->ReceiveConfig = v32;
-+	return _SUCCESS;
-+}
-+
-+/* only check SW RCR variable */
-+inline u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit)
-+{
-+	PHAL_DATA_TYPE hal;
-+	u32 rcr;
-+
-+	hal = GET_HAL_DATA(adapter);
-+
-+	rcr = hal->ReceiveConfig;
-+	if ((rcr & check_bit) == check_bit)
-+		return 1;
-+
-+	return 0;
-+}
-+
-+inline u8 rtw_hal_rcr_add(_adapter *adapter, u32 add)
-+{
-+	PHAL_DATA_TYPE hal;
-+	u32 rcr;
-+	u8 ret = _SUCCESS;
-+
-+	hal = GET_HAL_DATA(adapter);
-+
-+	rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
-+	rcr |= add;
-+	if (rcr != hal->ReceiveConfig)
-+		ret = rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
-+
-+	return ret;
-+}
-+
-+inline u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear)
-+{
-+	PHAL_DATA_TYPE hal;
-+	u32 rcr;
-+	u8 ret = _SUCCESS;
-+
-+	hal = GET_HAL_DATA(adapter);
-+
-+	rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
-+	rcr &= ~clear;
-+	if (rcr != hal->ReceiveConfig)
-+		ret = rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
-+
-+	return ret;
-+}
-+
-+void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u32 rcr, rcr_new;
-+	struct mi_state mstate, mstate_s;
-+
-+	rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
-+	rcr_new = rcr;
-+
-+#if defined(CONFIG_MI_WITH_MBSSID_CAM) && !defined(CONFIG_CLIENT_PORT_CFG)
-+	rcr_new &= ~(RCR_CBSSID_BCN | RCR_CBSSID_DATA);
-+#else
-+	rtw_mi_status_no_self(adapter, &mstate);
-+	rtw_mi_status_no_others(adapter, &mstate_s);
-+
-+	/* only adjust parameters interested */
-+	switch (self_action) {
-+	case MLME_SCAN_ENTER:
-+		mstate_s.scan_num = 1;
-+		mstate_s.scan_enter_num = 1;
-+		break;
-+	case MLME_SCAN_DONE:
-+		mstate_s.scan_enter_num = 0;
-+		break;
-+	case MLME_STA_CONNECTING:
-+		mstate_s.lg_sta_num = 1;
-+		mstate_s.ld_sta_num = 0;
-+		break;
-+	case MLME_STA_CONNECTED:
-+		mstate_s.lg_sta_num = 0;
-+		mstate_s.ld_sta_num = 1;
-+		break;
-+	case MLME_STA_DISCONNECTED:
-+		mstate_s.lg_sta_num = 0;
-+		mstate_s.ld_sta_num = 0;
-+		break;
-+#ifdef CONFIG_TDLS
-+	case MLME_TDLS_LINKED:
-+		mstate_s.ld_tdls_num = 1;
-+		break;
-+	case MLME_TDLS_NOLINK:
-+		mstate_s.ld_tdls_num = 0;
-+		break;
-+#endif
-+#ifdef CONFIG_AP_MODE
-+	case MLME_AP_STARTED:
-+		mstate_s.ap_num = 1;
-+		break;
-+	case MLME_AP_STOPPED:
-+		mstate_s.ap_num = 0;
-+		mstate_s.ld_ap_num = 0;
-+		break;
-+#endif
-+#ifdef CONFIG_RTW_MESH
-+	case MLME_MESH_STARTED:
-+		mstate_s.mesh_num = 1;
-+		break;
-+	case MLME_MESH_STOPPED:
-+		mstate_s.mesh_num = 0;
-+		mstate_s.ld_mesh_num = 0;
-+		break;
-+#endif
-+	case MLME_ACTION_NONE:
-+	case MLME_ADHOC_STARTED:
-+		/* caller without effect of decision */
-+		break;
-+	default:
-+		rtw_warn_on(1);
-+	};
-+
-+	rtw_mi_status_merge(&mstate, &mstate_s);
-+
-+	if (MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate) || MSTATE_TDLS_LD_NUM(&mstate)
-+		#ifdef CONFIG_FIND_BEST_CHANNEL
-+		|| MSTATE_SCAN_ENTER_NUM(&mstate)
-+		#endif
-+		|| hal_data->in_cta_test
-+	)
-+		rcr_new &= ~RCR_CBSSID_DATA;
-+	else
-+		rcr_new |= RCR_CBSSID_DATA;
-+
-+	if (MSTATE_SCAN_ENTER_NUM(&mstate) || hal_data->in_cta_test)
-+		rcr_new &= ~RCR_CBSSID_BCN;
-+	else if (MSTATE_STA_LG_NUM(&mstate)
-+		|| adapter_to_dvobj(adapter)->periodic_tsf_update_etime
-+	)
-+		rcr_new |= RCR_CBSSID_BCN;
-+	else if ((MSTATE_AP_NUM(&mstate) && adapter->registrypriv.wifi_spec) /* for 11n Logo 4.2.31/4.2.32 */
-+		|| MSTATE_MESH_NUM(&mstate)
-+	)
-+		rcr_new &= ~RCR_CBSSID_BCN;	
-+	else
-+		rcr_new |= RCR_CBSSID_BCN;
-+
-+	#ifdef CONFIG_CLIENT_PORT_CFG
-+	if (get_clt_num(adapter) > MAX_CLIENT_PORT_NUM)
-+		rcr_new &= ~RCR_CBSSID_BCN;
-+	#endif
-+#endif /* CONFIG_MI_WITH_MBSSID_CAM */
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+	if (MSTATE_AP_NUM(&mstate)
-+		&& rtw_unassoc_sta_src_chk(adapter, UNASOC_STA_SRC_RX_NMY_UC)
-+	) {
-+		rcr_new |= RCR_AAP;
-+	} else
-+		rcr_new &= ~RCR_AAP;
-+#endif
-+
-+	if (rcr == rcr_new)
-+		return;
-+
-+	if (!hal_spec->rx_tsf_filter
-+		&& (rcr & RCR_CBSSID_BCN) && !(rcr_new & RCR_CBSSID_BCN))
-+		rtw_hal_tsf_update_pause(adapter);
-+
-+	rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr_new);
-+
-+	if (!hal_spec->rx_tsf_filter
-+		&& !(rcr & RCR_CBSSID_BCN) && (rcr_new & RCR_CBSSID_BCN)
-+		&& self_action != MLME_STA_CONNECTING)
-+		rtw_hal_tsf_update_restore(adapter);
-+}
-+
-+void rtw_hal_rcr_set_chk_bssid_act_non(_adapter *adapter)
-+{
-+	rtw_hal_rcr_set_chk_bssid(adapter, MLME_ACTION_NONE);
-+}
-+
-+static void hw_var_set_rcr_am(_adapter *adapter, u8 enable)
-+{
-+	u32 rcr = RCR_AM;
-+
-+	if (enable)
-+		rtw_hal_rcr_add(adapter, rcr);
-+	else
-+		rtw_hal_rcr_clear(adapter, rcr);
-+}
-+
-+static void hw_var_set_bcn_interval(_adapter *adapter, u16 interval)
-+{
-+#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+	interval = rtw_hal_bcn_interval_adjust(adapter, interval);
-+#endif
-+
-+#ifdef RTW_HALMAC
-+	rtw_halmac_set_bcn_interval(adapter_to_dvobj(adapter), adapter->hw_port, interval);
-+#else
-+	rtw_write16(adapter, REG_MBSSID_BCN_SPACE, interval);
-+#endif
-+
-+#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
-+	{
-+		struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
-+		struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+		if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
-+			RTW_INFO("%s==> bcn_interval:%d, eraly_int:%d\n", __func__, interval, interval >> 1);
-+			rtw_write8(adapter, REG_DRVERLYINT, interval >> 1);
-+		}
-+	}
-+#endif
-+}
-+
-+#if CONFIG_TX_AC_LIFETIME
-+const char *const _tx_aclt_conf_str[] = {
-+	"DEFAULT",
-+	"AP_M2U",
-+	"MESH",
-+	"INVALID",
-+};
-+
-+void dump_tx_aclt_force_val(void *sel, struct dvobj_priv *dvobj)
-+{
-+#define TX_ACLT_FORCE_MSG_LEN 64
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj_get_primary_adapter(dvobj));
-+	struct tx_aclt_conf_t *conf = &dvobj->tx_aclt_force_val;
-+	char buf[TX_ACLT_FORCE_MSG_LEN];
-+	int cnt = 0;
-+
-+	RTW_PRINT_SEL(sel, "unit:%uus, maximum:%uus\n"
-+		, hal_spec->tx_aclt_unit_factor * 32
-+		, 0xFFFF * hal_spec->tx_aclt_unit_factor * 32);
-+
-+	RTW_PRINT_SEL(sel, "%-5s %-12s %-12s\n", "en", "vo_vi(us)", "be_bk(us)");
-+	RTW_PRINT_SEL(sel, " 0x%02x %12u %12u\n"
-+		, conf->en
-+		, conf->vo_vi * hal_spec->tx_aclt_unit_factor * 32
-+		, conf->be_bk * hal_spec->tx_aclt_unit_factor * 32
-+	);
-+
-+	cnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, "%5s", conf->en == 0xFF ? "AUTO" : "FORCE");
-+	if (cnt >= TX_ACLT_FORCE_MSG_LEN - 1)
-+		goto exit;
-+
-+	if (conf->vo_vi)
-+		cnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, " FORCE:0x%04x", conf->vo_vi);
-+	else
-+		cnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, "         AUTO");
-+	if (cnt >= TX_ACLT_FORCE_MSG_LEN - 1)
-+		goto exit;
-+
-+
-+	if (conf->be_bk)
-+		cnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, " FORCE:0x%04x", conf->be_bk);
-+	else
-+		cnt += snprintf(buf + cnt, TX_ACLT_FORCE_MSG_LEN - cnt - 1, "         AUTO");
-+	if (cnt >= TX_ACLT_FORCE_MSG_LEN - 1)
-+		goto exit;
-+
-+	RTW_PRINT_SEL(sel, "%s\n", buf);
-+
-+exit:
-+	return;
-+}
-+
-+void rtw_hal_set_tx_aclt_force_val(_adapter *adapter, struct tx_aclt_conf_t *input, u8 arg_num)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct tx_aclt_conf_t *conf = &dvobj->tx_aclt_force_val;
-+
-+	if (arg_num >= 1) {
-+		if (input->en == 0xFF)
-+			conf->en = input->en;
-+		else
-+			conf->en = input->en & 0xF;
-+	}
-+	if (arg_num >= 2) {
-+		conf->vo_vi = input->vo_vi / (hal_spec->tx_aclt_unit_factor * 32);
-+		if (conf->vo_vi > 0xFFFF)
-+			conf->vo_vi = 0xFFFF;
-+	}
-+	if (arg_num >= 3) {
-+		conf->be_bk = input->be_bk / (hal_spec->tx_aclt_unit_factor * 32);
-+		if (conf->be_bk > 0xFFFF)
-+			conf->be_bk = 0xFFFF;
-+	}
-+}
-+
-+void dump_tx_aclt_confs(void *sel, struct dvobj_priv *dvobj)
-+{
-+#define TX_ACLT_CONF_MSG_LEN 32
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj_get_primary_adapter(dvobj));
-+	struct tx_aclt_conf_t *conf;
-+	char buf[TX_ACLT_CONF_MSG_LEN];
-+	int cnt;
-+	int i;
-+
-+	RTW_PRINT_SEL(sel, "unit:%uus, maximum:%uus\n"
-+		, hal_spec->tx_aclt_unit_factor * 32
-+		, 0xFFFF * hal_spec->tx_aclt_unit_factor * 32);
-+
-+	RTW_PRINT_SEL(sel, "%-7s %-1s %-3s %-9s %-9s %-10s %-10s\n"
-+		, "name", "#", "en", "vo_vi(us)", "be_bk(us)", "vo_vi(reg)", "be_bk(reg)");
-+
-+	for (i = 0; i < TX_ACLT_CONF_NUM; i++) {
-+		conf = &dvobj->tx_aclt_confs[i];
-+		cnt = 0;
-+
-+		if (conf->vo_vi)
-+			cnt += snprintf(buf + cnt, TX_ACLT_CONF_MSG_LEN - cnt - 1, "     0x%04x", conf->vo_vi);
-+		else
-+			cnt += snprintf(buf + cnt, TX_ACLT_CONF_MSG_LEN - cnt - 1, "        N/A");
-+		if (cnt >= TX_ACLT_CONF_MSG_LEN - 1)
-+			continue;
-+		
-+		if (conf->be_bk)
-+			cnt += snprintf(buf + cnt, TX_ACLT_CONF_MSG_LEN - cnt - 1, "     0x%04x", conf->be_bk);
-+		else
-+			cnt += snprintf(buf + cnt, TX_ACLT_CONF_MSG_LEN - cnt - 1, "        N/A");
-+		if (cnt >= TX_ACLT_CONF_MSG_LEN - 1)
-+			continue;
-+
-+		RTW_PRINT_SEL(sel, "%7s %1u 0x%x %9u %9u%s\n"
-+			, tx_aclt_conf_str(i), i
-+			, conf->en
-+			, conf->vo_vi * hal_spec->tx_aclt_unit_factor * 32
-+			, conf->be_bk * hal_spec->tx_aclt_unit_factor * 32
-+			, buf
-+		);
-+	}
-+}
-+
-+void rtw_hal_set_tx_aclt_conf(_adapter *adapter, u8 conf_idx, struct tx_aclt_conf_t *input, u8 arg_num)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct tx_aclt_conf_t *conf;
-+
-+	if (conf_idx >= TX_ACLT_CONF_NUM)
-+		return;
-+
-+	conf = &dvobj->tx_aclt_confs[conf_idx];
-+
-+	if (arg_num >= 1) {
-+		if (input->en != 0xFF)
-+			conf->en = input->en & 0xF;
-+	}
-+	if (arg_num >= 2) {
-+		conf->vo_vi = input->vo_vi / (hal_spec->tx_aclt_unit_factor * 32);
-+		if (conf->vo_vi > 0xFFFF)
-+			conf->vo_vi = 0xFFFF;
-+	}
-+	if (arg_num >= 3) {
-+		conf->be_bk = input->be_bk / (hal_spec->tx_aclt_unit_factor * 32);
-+		if (conf->be_bk > 0xFFFF)
-+			conf->be_bk = 0xFFFF;
-+	}
-+}
-+
-+void rtw_hal_update_tx_aclt(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
-+	u8 lt_en = 0, lt_en_ori;
-+	u16 lt_vo_vi = 0xFFFF, lt_be_bk = 0xFFFF;
-+	u32 lt, lt_ori;
-+	struct tx_aclt_conf_t *conf;
-+	int i;
-+#ifdef CONFIG_AP_MODE
-+#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+	_adapter *iface;
-+	u8 ap_m2u_num = 0;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+		
-+		if (MLME_IS_AP(iface)
-+			&& ((iface->b2u_flags_ap_src & RTW_AP_B2U_IP_MCAST)
-+				|| (iface->b2u_flags_ap_fwd & RTW_AP_B2U_IP_MCAST))
-+		)
-+			ap_m2u_num++;
-+	}
-+#endif
-+#endif /* CONFIG_AP_MODE */
-+
-+	lt_en_ori = rtw_read8(adapter, REG_LIFETIME_EN);
-+	lt_ori = rtw_read32(adapter, REG_PKT_LIFE_TIME);
-+
-+	for (i = 0; i < TX_ACLT_CONF_NUM; i++) {
-+		if (!(dvobj->tx_aclt_flags & BIT(i)))
-+			continue;
-+
-+		conf = &dvobj->tx_aclt_confs[i];
-+
-+		if (i == TX_ACLT_CONF_DEFAULT) {
-+			/* first and default status, assign directly */
-+			lt_en = conf->en;
-+			if (conf->vo_vi)
-+				lt_vo_vi = conf->vo_vi;
-+			if (conf->be_bk)
-+				lt_be_bk = conf->be_bk;
-+		}
-+		#ifdef CONFIG_AP_MODE
-+		#if CONFIG_RTW_AP_DATA_BMC_TO_UC || defined(CONFIG_RTW_MESH)
-+		else if (0
-+			#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+			|| (i == TX_ACLT_CONF_AP_M2U
-+				&& ap_m2u_num
-+				&& macid_ctl->op_num[H2C_MSR_ROLE_STA] /* having AP mode with STA connected */)
-+			#endif
-+			#ifdef CONFIG_RTW_MESH
-+			|| (i == TX_ACLT_CONF_MESH
-+				&& macid_ctl->op_num[H2C_MSR_ROLE_MESH] > 1 /* implies only 1 MESH mode supported */)
-+			#endif
-+		) {
-+			/* long term status, OR en and MIN lifetime */
-+			lt_en |= conf->en;
-+			if (conf->vo_vi && lt_vo_vi > conf->vo_vi)
-+				lt_vo_vi = conf->vo_vi;
-+			if (conf->be_bk && lt_be_bk > conf->be_bk)
-+				lt_be_bk = conf->be_bk;
-+		}
-+		#endif
-+		#endif /* CONFIG_AP_MODE */
-+	}
-+
-+	if (dvobj->tx_aclt_force_val.en != 0xFF)
-+		lt_en = dvobj->tx_aclt_force_val.en;
-+	if (dvobj->tx_aclt_force_val.vo_vi)
-+		lt_vo_vi = dvobj->tx_aclt_force_val.vo_vi;
-+	if (dvobj->tx_aclt_force_val.be_bk)
-+		lt_be_bk = dvobj->tx_aclt_force_val.be_bk;
-+
-+	lt_en = (lt_en_ori & 0xF0) | (lt_en & 0x0F);
-+	lt = (lt_be_bk << 16) | lt_vo_vi;
-+
-+	if (0)
-+		RTW_INFO("lt_en:0x%x(0x%x), lt:0x%08x(0x%08x)\n", lt_en, lt_en_ori, lt, lt_ori);
-+
-+	if (lt_en != lt_en_ori)
-+		rtw_write8(adapter, REG_LIFETIME_EN, lt_en);
-+	if (lt != lt_ori)
-+		rtw_write32(adapter, REG_PKT_LIFE_TIME, lt);
-+}
-+#endif /* CONFIG_TX_AC_LIFETIME */
-+
-+void hw_var_port_switch(_adapter *adapter)
-+{
-+#ifdef CONFIG_CONCURRENT_MODE
-+#ifdef CONFIG_RUNTIME_PORT_SWITCH
-+	/*
-+	0x102: MSR
-+	0x550: REG_BCN_CTRL
-+	0x551: REG_BCN_CTRL_1
-+	0x55A: REG_ATIMWND
-+	0x560: REG_TSFTR
-+	0x568: REG_TSFTR1
-+	0x570: REG_ATIMWND_1
-+	0x610: REG_MACID
-+	0x618: REG_BSSID
-+	0x700: REG_MACID1
-+	0x708: REG_BSSID1
-+	*/
-+
-+	int i;
-+	u8 msr;
-+	u8 bcn_ctrl;
-+	u8 bcn_ctrl_1;
-+	u8 atimwnd[2];
-+	u8 atimwnd_1[2];
-+	u8 tsftr[8];
-+	u8 tsftr_1[8];
-+	u8 macid[6];
-+	u8 bssid[6];
-+	u8 macid_1[6];
-+	u8 bssid_1[6];
-+#if defined(CONFIG_RTL8192F)
-+	u16 wlan_act_mask_ctrl = 0;
-+	u16 en_port_mask = EN_PORT_0_FUNCTION | EN_PORT_1_FUNCTION;
-+#endif
-+
-+	u8 hw_port;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	_adapter *iface = NULL;
-+
-+	msr = rtw_read8(adapter, MSR);
-+	bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL);
-+	bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1);
-+#if defined(CONFIG_RTL8192F)
-+	wlan_act_mask_ctrl = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1);
-+#endif
-+
-+	for (i = 0; i < 2; i++)
-+		atimwnd[i] = rtw_read8(adapter, REG_ATIMWND + i);
-+	for (i = 0; i < 2; i++)
-+		atimwnd_1[i] = rtw_read8(adapter, REG_ATIMWND_1 + i);
-+
-+	for (i = 0; i < 8; i++)
-+		tsftr[i] = rtw_read8(adapter, REG_TSFTR + i);
-+	for (i = 0; i < 8; i++)
-+		tsftr_1[i] = rtw_read8(adapter, REG_TSFTR1 + i);
-+
-+	for (i = 0; i < 6; i++)
-+		macid[i] = rtw_read8(adapter, REG_MACID + i);
-+
-+	for (i = 0; i < 6; i++)
-+		bssid[i] = rtw_read8(adapter, REG_BSSID + i);
-+
-+	for (i = 0; i < 6; i++)
-+		macid_1[i] = rtw_read8(adapter, REG_MACID1 + i);
-+
-+	for (i = 0; i < 6; i++)
-+		bssid_1[i] = rtw_read8(adapter, REG_BSSID1 + i);
-+
-+#ifdef DBG_RUNTIME_PORT_SWITCH
-+	RTW_INFO(FUNC_ADPT_FMT" before switch\n"
-+		 "msr:0x%02x\n"
-+		 "bcn_ctrl:0x%02x\n"
-+		 "bcn_ctrl_1:0x%02x\n"
-+#if defined(CONFIG_RTL8192F)
-+		 "wlan_act_mask_ctrl:0x%02x\n"
-+#endif
-+		 "atimwnd:0x%04x\n"
-+		 "atimwnd_1:0x%04x\n"
-+		 "tsftr:%llu\n"
-+		 "tsftr1:%llu\n"
-+		 "macid:"MAC_FMT"\n"
-+		 "bssid:"MAC_FMT"\n"
-+		 "macid_1:"MAC_FMT"\n"
-+		 "bssid_1:"MAC_FMT"\n"
-+		 , FUNC_ADPT_ARG(adapter)
-+		 , msr
-+		 , bcn_ctrl
-+		 , bcn_ctrl_1
-+#if defined(CONFIG_RTL8192F)
-+		 , wlan_act_mask_ctrl
-+#endif
-+		 , *((u16 *)atimwnd)
-+		 , *((u16 *)atimwnd_1)
-+		 , *((u64 *)tsftr)
-+		 , *((u64 *)tsftr_1)
-+		 , MAC_ARG(macid)
-+		 , MAC_ARG(bssid)
-+		 , MAC_ARG(macid_1)
-+		 , MAC_ARG(bssid_1)
-+		);
-+#endif /* DBG_RUNTIME_PORT_SWITCH */
-+
-+	/* disable bcn function, disable update TSF */
-+	rtw_write8(adapter, REG_BCN_CTRL, (bcn_ctrl & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);
-+	rtw_write8(adapter, REG_BCN_CTRL_1, (bcn_ctrl_1 & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);
-+
-+#if defined(CONFIG_RTL8192F)
-+	rtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1, wlan_act_mask_ctrl & ~en_port_mask);
-+#endif
-+
-+	/* switch msr */
-+	msr = (msr & 0xf0) | ((msr & 0x03) << 2) | ((msr & 0x0c) >> 2);
-+	rtw_write8(adapter, MSR, msr);
-+
-+	/* write port0 */
-+	rtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1 & ~EN_BCN_FUNCTION);
-+	for (i = 0; i < 2; i++)
-+		rtw_write8(adapter, REG_ATIMWND + i, atimwnd_1[i]);
-+	for (i = 0; i < 8; i++)
-+		rtw_write8(adapter, REG_TSFTR + i, tsftr_1[i]);
-+	for (i = 0; i < 6; i++)
-+		rtw_write8(adapter, REG_MACID + i, macid_1[i]);
-+	for (i = 0; i < 6; i++)
-+		rtw_write8(adapter, REG_BSSID + i, bssid_1[i]);
-+
-+	/* write port1 */
-+	rtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl & ~EN_BCN_FUNCTION);
-+	for (i = 0; i < 2; i++)
-+		rtw_write8(adapter, REG_ATIMWND_1 + i, atimwnd[i]);
-+	for (i = 0; i < 8; i++)
-+		rtw_write8(adapter, REG_TSFTR1 + i, tsftr[i]);
-+	for (i = 0; i < 6; i++)
-+		rtw_write8(adapter, REG_MACID1 + i, macid[i]);
-+	for (i = 0; i < 6; i++)
-+		rtw_write8(adapter, REG_BSSID1 + i, bssid[i]);
-+
-+	/* write bcn ctl */
-+#ifdef CONFIG_BT_COEXIST
-+	/* always enable port0 beacon function for PSTDMA */
-+	if (IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
-+	    || IS_HARDWARE_TYPE_8723D(adapter))
-+		bcn_ctrl_1 |= EN_BCN_FUNCTION;
-+	/* always disable port1 beacon function for PSTDMA */
-+	if (IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8703B(adapter))
-+		bcn_ctrl &= ~EN_BCN_FUNCTION;
-+#endif
-+	rtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1);
-+	rtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl);
-+
-+#if defined(CONFIG_RTL8192F)
-+	/* if the setting of port0 and port1 are the same, it does not need to switch port setting*/
-+	if(((wlan_act_mask_ctrl & en_port_mask) != 0) && ((wlan_act_mask_ctrl & en_port_mask)
-+		!= (EN_PORT_0_FUNCTION | EN_PORT_1_FUNCTION)))
-+		wlan_act_mask_ctrl ^= en_port_mask;
-+	rtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1, wlan_act_mask_ctrl);
-+#endif
-+
-+	if (adapter->iface_id == IFACE_ID0)
-+		iface = dvobj->padapters[IFACE_ID1];
-+	else if (adapter->iface_id == IFACE_ID1)
-+		iface = dvobj->padapters[IFACE_ID0];
-+
-+
-+	if (adapter->hw_port == HW_PORT0) {
-+		adapter->hw_port = HW_PORT1;
-+		iface->hw_port = HW_PORT0;
-+		RTW_PRINT("port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n",
-+			  ADPT_ARG(iface), ADPT_ARG(adapter));
-+	} else {
-+		adapter->hw_port = HW_PORT0;
-+		iface->hw_port = HW_PORT1;
-+		RTW_PRINT("port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n",
-+			  ADPT_ARG(adapter), ADPT_ARG(iface));
-+	}
-+
-+#ifdef DBG_RUNTIME_PORT_SWITCH
-+	msr = rtw_read8(adapter, MSR);
-+	bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL);
-+	bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1);
-+#if defined(CONFIG_RTL8192F)
-+	wlan_act_mask_ctrl = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1);
-+#endif
-+
-+	for (i = 0; i < 2; i++)
-+		atimwnd[i] = rtw_read8(adapter, REG_ATIMWND + i);
-+	for (i = 0; i < 2; i++)
-+		atimwnd_1[i] = rtw_read8(adapter, REG_ATIMWND_1 + i);
-+
-+	for (i = 0; i < 8; i++)
-+		tsftr[i] = rtw_read8(adapter, REG_TSFTR + i);
-+	for (i = 0; i < 8; i++)
-+		tsftr_1[i] = rtw_read8(adapter, REG_TSFTR1 + i);
-+
-+	for (i = 0; i < 6; i++)
-+		macid[i] = rtw_read8(adapter, REG_MACID + i);
-+
-+	for (i = 0; i < 6; i++)
-+		bssid[i] = rtw_read8(adapter, REG_BSSID + i);
-+
-+	for (i = 0; i < 6; i++)
-+		macid_1[i] = rtw_read8(adapter, REG_MACID1 + i);
-+
-+	for (i = 0; i < 6; i++)
-+		bssid_1[i] = rtw_read8(adapter, REG_BSSID1 + i);
-+
-+	RTW_INFO(FUNC_ADPT_FMT" after switch\n"
-+		 "msr:0x%02x\n"
-+		 "bcn_ctrl:0x%02x\n"
-+		 "bcn_ctrl_1:0x%02x\n"
-+#if defined(CONFIG_RTL8192F)
-+		 "wlan_act_mask_ctrl:0x%02x\n"
-+#endif
-+		 "atimwnd:%u\n"
-+		 "atimwnd_1:%u\n"
-+		 "tsftr:%llu\n"
-+		 "tsftr1:%llu\n"
-+		 "macid:"MAC_FMT"\n"
-+		 "bssid:"MAC_FMT"\n"
-+		 "macid_1:"MAC_FMT"\n"
-+		 "bssid_1:"MAC_FMT"\n"
-+		 , FUNC_ADPT_ARG(adapter)
-+		 , msr
-+		 , bcn_ctrl
-+		 , bcn_ctrl_1
-+#if defined(CONFIG_RTL8192F)
-+		 , wlan_act_mask_ctrl
-+#endif
-+		 , *((u16 *)atimwnd)
-+		 , *((u16 *)atimwnd_1)
-+		 , *((u64 *)tsftr)
-+		 , *((u64 *)tsftr_1)
-+		 , MAC_ARG(macid)
-+		 , MAC_ARG(bssid)
-+		 , MAC_ARG(macid_1)
-+		 , MAC_ARG(bssid_1)
-+		);
-+#endif /* DBG_RUNTIME_PORT_SWITCH */
-+
-+#endif /* CONFIG_RUNTIME_PORT_SWITCH */
-+#endif /* CONFIG_CONCURRENT_MODE */
-+}
-+
-+const char *const _h2c_msr_role_str[] = {
-+	"RSVD",
-+	"STA",
-+	"AP",
-+	"GC",
-+	"GO",
-+	"TDLS",
-+	"ADHOC",
-+	"MESH",
-+	"INVALID",
-+};
-+
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id)
-+{
-+	s32 ret = _SUCCESS;
-+	u8 parm[H2C_DEFAULT_PORT_ID_LEN] = {0};
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	u8 port_id = rtw_hal_get_port(adapter);
-+
-+	if ((dvobj->dft.port_id == port_id) && (dvobj->dft.mac_id == mac_id))
-+		return ret;
-+
-+	SET_H2CCMD_DFTPID_PORT_ID(parm, port_id);
-+	SET_H2CCMD_DFTPID_MAC_ID(parm, mac_id);
-+
-+	RTW_DBG_DUMP("DFT port id parm:", parm, H2C_DEFAULT_PORT_ID_LEN);
-+	RTW_INFO("%s ("ADPT_FMT") port_id :%d, mad_id:%d\n",
-+		__func__, ADPT_ARG(adapter), port_id, mac_id);
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_DEFAULT_PORT_ID, H2C_DEFAULT_PORT_ID_LEN, parm);
-+	dvobj->dft.port_id = port_id;
-+	dvobj->dft.mac_id = mac_id;
-+
-+	return ret;
-+}
-+s32 rtw_set_default_port_id(_adapter *adapter)
-+{
-+	s32 ret = _SUCCESS;
-+	struct sta_info		*psta;
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+
-+	if (is_client_associated_to_ap(adapter)) {
-+		psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
-+		if (psta)
-+			ret = rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);
-+	} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
-+
-+	} else {
-+	}
-+
-+	return ret;
-+}
-+s32 rtw_set_ps_rsvd_page(_adapter *adapter)
-+{
-+	s32 ret = _SUCCESS;
-+	u16 media_status_rpt = RT_MEDIA_CONNECT;
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+
-+	if (adapter->iface_id == pwrctl->fw_psmode_iface_id)
-+		return ret;
-+
-+	rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
-+			  (u8 *)&media_status_rpt);
-+
-+	return ret;
-+}
-+
-+#if 0
-+_adapter * _rtw_search_dp_iface(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	_adapter *iface;
-+	_adapter *target_iface = NULL;
-+	int i;
-+	u8 sta_num = 0, tdls_num = 0, ap_num = 0, mesh_num = 0, adhoc_num = 0;
-+	u8 p2p_go_num = 0, p2p_gc_num = 0;
-+	_adapter *sta_ifs[8];
-+	_adapter *ap_ifs[8];
-+	_adapter *mesh_ifs[8];
-+	_adapter *gc_ifs[8];
-+	_adapter *go_ifs[8];
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+
-+		if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) {
-+			if (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+				sta_ifs[sta_num++] = iface;
-+
-+				#ifdef CONFIG_TDLS
-+				if (iface->tdlsinfo.link_established == _TRUE)
-+					tdls_num++;
-+				#endif
-+				#ifdef CONFIG_P2P
-+				if (MLME_IS_GC(iface))
-+					gc_ifs[p2p_gc_num++] = iface;
-+				#endif
-+			}
-+#ifdef CONFIG_AP_MODE
-+		} else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) {
-+			if (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+				ap_ifs[ap_num++] = iface;
-+				#ifdef CONFIG_P2P
-+				if (MLME_IS_GO(iface))
-+					go_ifs[p2p_go_num++] = iface;
-+				#endif
-+			}
-+#endif
-+		} else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE
-+			&& check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE
-+		) {
-+			adhoc_num++;
-+
-+#ifdef CONFIG_RTW_MESH
-+		} else if (check_fwstate(&iface->mlmepriv, WIFI_MESH_STATE) == _TRUE
-+			&& check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE
-+		) {
-+			mesh_ifs[mesh_num++] = iface;
-+#endif
-+		}
-+	}
-+
-+	if (p2p_gc_num) {
-+		target_iface = gc_ifs[0];
-+	}
-+	else if (sta_num) {
-+		if(sta_num == 1) {
-+			target_iface = sta_ifs[0];
-+		} else if (sta_num >= 2) {
-+			/*TODO get target_iface by timestamp*/
-+			target_iface = sta_ifs[0];
-+		}
-+	} else if (ap_num) {
-+		target_iface = ap_ifs[0];
-+	}
-+
-+	RTW_INFO("[IFS_ASSOC_STATUS] - STA :%d", sta_num);
-+	RTW_INFO("[IFS_ASSOC_STATUS] - TDLS :%d", tdls_num);
-+	RTW_INFO("[IFS_ASSOC_STATUS] - AP:%d", ap_num);
-+	RTW_INFO("[IFS_ASSOC_STATUS] - MESH :%d", mesh_num);
-+	RTW_INFO("[IFS_ASSOC_STATUS] - ADHOC :%d", adhoc_num);
-+	RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GC :%d", p2p_gc_num);
-+	RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GO :%d", p2p_go_num);
-+
-+	if (target_iface)
-+		RTW_INFO("%s => target_iface ("ADPT_FMT")\n",
-+			__func__, ADPT_ARG(target_iface));
-+	else
-+		RTW_INFO("%s => target_iface NULL\n", __func__);
-+
-+	return target_iface;
-+}
-+
-+void rtw_search_default_port(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	_adapter *adp_iface = NULL;
-+#ifdef CONFIG_WOWLAN
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+
-+	if (pwrpriv->wowlan_mode == _TRUE) {
-+		adp_iface = adapter;
-+		goto exit;
-+	}
-+#endif
-+	adp_iface = _rtw_search_dp_iface(adapter);
-+
-+exit :
-+	if ((adp_iface != NULL) && (MLME_IS_STA(adp_iface)))
-+		rtw_set_default_port_id(adp_iface);
-+	else
-+		rtw_hal_set_default_port_id_cmd(adapter, 0);
-+
-+	if (1) {
-+		_adapter *tmp_adp;
-+
-+		tmp_adp = (adp_iface) ? adp_iface : adapter;
-+
-+		RTW_INFO("%s ("ADPT_FMT")=> hw_port :%d, default_port(%d)\n",
-+			__func__, ADPT_ARG(adapter), get_hw_port(tmp_adp), get_dft_portid(tmp_adp));
-+	}
-+}
-+#endif
-+#endif /*CONFIG_FW_MULTI_PORT_SUPPORT*/
-+
-+#ifdef CONFIG_P2P_PS
-+#ifdef RTW_HALMAC
-+void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state)
-+{
-+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
-+	struct wifidirect_info *pwdinfo = &adapter->wdinfo;
-+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
-+	struct sta_priv		*pstapriv = &adapter->stapriv;
-+	struct sta_info		*psta;
-+	HAL_P2P_PS_PARA p2p_ps_para;
-+	int status = -1;
-+	u8 i;
-+	u8 hw_port = rtw_hal_get_port(adapter);
-+
-+	_rtw_memset(&p2p_ps_para, 0, sizeof(HAL_P2P_PS_PARA));
-+	_rtw_memcpy((&p2p_ps_para) , &hal->p2p_ps_offload , sizeof(hal->p2p_ps_offload));
-+
-+	(&p2p_ps_para)->p2p_port_id = hw_port;
-+	(&p2p_ps_para)->p2p_group = 0;
-+	psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
-+	if (psta) {
-+		(&p2p_ps_para)->p2p_macid = psta->cmn.mac_id;
-+	} else {
-+		if (p2p_ps_state != P2P_PS_DISABLE) {
-+			RTW_ERR("%s , psta was NULL\n", __func__);
-+			return;
-+		}
-+	}
-+
-+
-+	switch (p2p_ps_state) {
-+	case P2P_PS_DISABLE:
-+		RTW_INFO("P2P_PS_DISABLE\n");
-+		_rtw_memset(&p2p_ps_para , 0, sizeof(HAL_P2P_PS_PARA));
-+		break;
-+
-+	case P2P_PS_ENABLE:
-+		RTW_INFO("P2P_PS_ENABLE\n");
-+		/* update CTWindow value. */
-+		if (pwdinfo->ctwindow > 0) {
-+			(&p2p_ps_para)->ctwindow_en = 1;
-+			(&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
-+			/*RTW_INFO("%s , ctwindow_length = %d\n" , __func__ , (&p2p_ps_para)->ctwindow_length);*/
-+		}
-+
-+
-+		if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) {
-+			(&p2p_ps_para)->offload_en = 1;
-+			if (pwdinfo->role == P2P_ROLE_GO) {
-+				(&p2p_ps_para)->role = 1;
-+				(&p2p_ps_para)->all_sta_sleep = 0;
-+			} else
-+				(&p2p_ps_para)->role = 0;
-+
-+			(&p2p_ps_para)->discovery = 0;
-+		}
-+		/* hw only support 2 set of NoA */
-+		for (i = 0; i < pwdinfo->noa_num; i++) {
-+			/* To control the register setting for which NOA */
-+			(&p2p_ps_para)->noa_sel = i;
-+			(&p2p_ps_para)->noa_en = 1;
-+			(&p2p_ps_para)->disable_close_rf = 0;
-+#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
-+#ifdef CONFIG_CONCURRENT_MODE
-+			if (rtw_mi_buddy_check_fwstate(adapter, WIFI_ASOC_STATE))
-+#endif /* CONFIG_CONCURRENT_MODE */
-+				(&p2p_ps_para)->disable_close_rf = 1;
-+#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */
-+			/* config P2P NoA Descriptor Register */
-+			/* config NOA duration */
-+			(&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[i];
-+			/* config NOA interval */
-+			(&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[i];
-+			/* config NOA start time */
-+			(&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[i];
-+			/* config NOA count */
-+			(&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[i];
-+			/*RTW_INFO("%s , noa_duration_para = %d , noa_interval_para = %d , noa_start_time_para = %d , noa_count_para = %d\n" , __func__ ,
-+				(&p2p_ps_para)->noa_duration_para , (&p2p_ps_para)->noa_interval_para ,
-+				(&p2p_ps_para)->noa_start_time_para , (&p2p_ps_para)->noa_count_para);*/
-+			status = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para));
-+			if (status == -1)
-+				RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__);
-+		}
-+
-+		break;
-+
-+	case P2P_PS_SCAN:
-+		/*This feature FW not ready 20161116 YiWei*/
-+		return;
-+		/*
-+		RTW_INFO("P2P_PS_SCAN\n");
-+		(&p2p_ps_para)->discovery = 1;
-+		(&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
-+		(&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0];
-+		(&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0];
-+		(&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0];
-+		(&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0];
-+		*/
-+		break;
-+
-+	case P2P_PS_SCAN_DONE:
-+		/*This feature FW not ready 20161116 YiWei*/
-+		return;
-+		/*
-+		RTW_INFO("P2P_PS_SCAN_DONE\n");
-+		(&p2p_ps_para)->discovery = 0;
-+		pwdinfo->p2p_ps_state = P2P_PS_ENABLE;
-+		(&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
-+		(&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0];
-+		(&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0];
-+		(&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0];
-+		(&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0];
-+		*/
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	if (p2p_ps_state != P2P_PS_ENABLE || (&p2p_ps_para)->noa_en == 0) {
-+		status = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para));
-+		if (status == -1)
-+			RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__);
-+	}
-+	_rtw_memcpy(&hal->p2p_ps_offload , (&p2p_ps_para) , sizeof(hal->p2p_ps_offload));
-+
-+}
-+#endif /* RTW_HALMAC */
-+#endif /* CONFIG_P2P */
-+
-+#if defined(CONFIG_RTL8822C) && defined(CONFIG_SUPPORT_DYNAMIC_TXPWR)
-+static void _rtw_hal_dtp_macid_set(
-+	_adapter *padapter, u8 opmode, u8 mac_id)
-+{
-+	struct macid_ctl_t *macid_ctl = &(padapter->dvobj->macid_ctl);
-+	struct sta_info *psta;
-+	u8 h2c_cmd[H2C_FW_CRC5_SEARCH_LEN] = {0};
-+	u8 mac_addr[ETH_ALEN] = {0};
-+
-+	if (opmode) {
-+		psta = macid_ctl->sta[mac_id];
-+		if (psta)
-+			_rtw_memcpy(mac_addr, psta->cmn.mac_addr, ETH_ALEN);
-+
-+		if (rtw_check_invalid_mac_address(mac_addr, _FALSE))
-+			return;
-+	}
-+	/* else DON'T CARE H2C_FW_CRC5_SEARCH mac addr in disconnected case */
-+
-+	if (rtw_get_chip_type(padapter) == RTL8822C) {
-+		SET_H2CCMD_FW_CRC5_SEARCH_EN(h2c_cmd, opmode);
-+		SET_H2CCMD_FW_CRC5_SEARCH_MACID(h2c_cmd, mac_id);
-+		SET_H2CCMD_FW_CRC5_SEARCH_MAC(&h2c_cmd[1], mac_addr);
-+		if (rtw_hal_fill_h2c_cmd(padapter, H2C_FW_CRC5_SEARCH,
-+						H2C_FW_CRC5_SEARCH_LEN, h2c_cmd) != _SUCCESS)
-+			RTW_WARN("%s : set h2c - 0x%02x fail!\n", __func__, H2C_FW_CRC5_SEARCH);
-+	}
-+}
-+
-+static void rtw_hal_dtp_macid_set(_adapter *padapter, u8 opmode,
-+	bool macid_ind, u8 mac_id, u8 macid_end)
-+{
-+	int i;
-+
-+	if (macid_ind == 0) {
-+		_rtw_hal_dtp_macid_set(padapter, opmode, mac_id);
-+	} else {
-+		for (i = mac_id; i <= macid_end; i++)
-+			_rtw_hal_dtp_macid_set(padapter, opmode, i);
-+	}
-+}
-+#endif
-+
-+/*
-+* rtw_hal_set_FwMediaStatusRpt_cmd -
-+*
-+* @adapter:
-+* @opmode:  0:disconnect, 1:connect
-+* @miracast: 0:it's not in miracast scenario. 1:it's in miracast scenario
-+* @miracast_sink: 0:source. 1:sink
-+* @role: The role of this macid. 0:rsvd. 1:STA. 2:AP. 3:GC. 4:GO. 5:TDLS
-+* @macid:
-+* @macid_ind:  0:update Media Status to macid.  1:update Media Status from macid to macid_end
-+* @macid_end:
-+*/
-+s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end)
-+{
-+	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
-+	u8 parm[H2C_MEDIA_STATUS_RPT_LEN] = {0};
-+	int i;
-+	s32 ret;
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+	u8 hw_port = rtw_hal_get_port(adapter);
-+#endif
-+	u8 op_num_change_bmp = 0;
-+
-+#if defined(CONFIG_RTL8822C) && defined(CONFIG_SUPPORT_DYNAMIC_TXPWR)
-+	rtw_hal_dtp_macid_set(adapter, opmode, macid_ind, macid, macid_end);
-+#endif
-+
-+	SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, opmode);
-+	SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, macid_ind);
-+	SET_H2CCMD_MSRRPT_PARM_MIRACAST(parm, miracast);
-+	SET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(parm, miracast_sink);
-+	SET_H2CCMD_MSRRPT_PARM_ROLE(parm, role);
-+	SET_H2CCMD_MSRRPT_PARM_MACID(parm, macid);
-+	SET_H2CCMD_MSRRPT_PARM_MACID_END(parm, macid_end);
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+	SET_H2CCMD_MSRRPT_PARM_PORT_NUM(parm, hw_port);
-+#endif
-+	RTW_DBG_DUMP("MediaStatusRpt parm:", parm, H2C_MEDIA_STATUS_RPT_LEN);
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_MEDIA_STATUS_RPT, H2C_MEDIA_STATUS_RPT_LEN, parm);
-+	if (ret != _SUCCESS)
-+		goto exit;
-+
-+#if defined(CONFIG_RTL8188E)
-+	if (rtw_get_chip_type(adapter) == RTL8188E) {
-+		HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+		/* 8188E FW doesn't set macid no link, driver does it by self */
-+		if (opmode)
-+			rtw_hal_set_hwreg(adapter, HW_VAR_MACID_LINK, &macid);
-+		else
-+			rtw_hal_set_hwreg(adapter, HW_VAR_MACID_NOLINK, &macid);
-+
-+		/* for 8188E RA */
-+#if (RATE_ADAPTIVE_SUPPORT == 1)
-+		if (hal_data->fw_ractrl == _FALSE) {
-+			u8 max_macid;
-+
-+			max_macid = rtw_search_max_mac_id(adapter);
-+			rtw_hal_set_hwreg(adapter, HW_VAR_TX_RPT_MAX_MACID, &max_macid);
-+		}
-+#endif
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+	/* TODO: this should move to IOT issue area */
-+	if (rtw_get_chip_type(adapter) == RTL8812
-+		|| rtw_get_chip_type(adapter) == RTL8821
-+	) {
-+		if (MLME_IS_STA(adapter))
-+			Hal_PatchwithJaguar_8812(adapter, opmode);
-+	}
-+#endif
-+
-+	SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0);
-+	if (macid_ind == 0)
-+		macid_end = macid;
-+
-+	for (i = macid; macid <= macid_end; macid++) {
-+		op_num_change_bmp |= rtw_macid_ctl_set_h2c_msr(macid_ctl, macid, parm[0]);
-+		if (!opmode) {
-+			rtw_macid_ctl_set_bw(macid_ctl, macid, CHANNEL_WIDTH_20);
-+			rtw_macid_ctl_set_vht_en(macid_ctl, macid, 0);
-+			rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, 0);
-+			rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, 0);
-+		}
-+	}
-+
-+#if CONFIG_TX_AC_LIFETIME
-+	if (op_num_change_bmp)
-+		rtw_hal_update_tx_aclt(adapter);
-+#endif
-+
-+	if (!opmode)
-+		rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
-+
-+exit:
-+	return ret;
-+}
-+
-+inline s32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid)
-+{
-+	return rtw_hal_set_FwMediaStatusRpt_cmd(adapter, opmode, miracast, miracast_sink, role, macid, 0, 0);
-+}
-+
-+inline s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, u8 macid_end)
-+{
-+	return rtw_hal_set_FwMediaStatusRpt_cmd(adapter, opmode, miracast, miracast_sink, role, macid, 1, macid_end);
-+}
-+
-+void rtw_hal_set_FwRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
-+{
-+	u8	u1H2CRsvdPageParm[H2C_RSVDPAGE_LOC_LEN] = {0};
-+	u8	ret = 0;
-+
-+	RTW_INFO("RsvdPageLoc: ProbeRsp=%d PsPoll=%d Null=%d QoSNull=%d BTNull=%d\n",
-+		 rsvdpageloc->LocProbeRsp, rsvdpageloc->LocPsPoll,
-+		 rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull,
-+		 rsvdpageloc->LocBTQosNull);
-+
-+	SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1H2CRsvdPageParm, rsvdpageloc->LocProbeRsp);
-+	SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1H2CRsvdPageParm, rsvdpageloc->LocPsPoll);
-+	SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocNullData);
-+	SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocQosNull);
-+	SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocBTQosNull);
-+
-+	ret = rtw_hal_fill_h2c_cmd(padapter,
-+				   H2C_RSVD_PAGE,
-+				   H2C_RSVDPAGE_LOC_LEN,
-+				   u1H2CRsvdPageParm);
-+
-+}
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+
-+	if (IS_8723D_SERIES(pHalData->version_id) || IS_8192F_SERIES(pHalData->version_id)
-+		|| IS_8822B_SERIES(pHalData->version_id) || IS_8821C_SERIES(pHalData->version_id)
-+		|| IS_8822C_SERIES(pHalData->version_id))
-+		rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable));
-+	/*
-+	* Switch GPIO_13, GPIO_14 to wlan control, or pull GPIO_13,14 MUST fail.
-+	* It happended at 8723B/8192E/8821A. New IC will check multi function GPIO,
-+	* and implement HAL function.
-+	* TODO: GPIO_8 multi function?
-+	*/
-+
-+	if ((index == 13 || index == 14)
-+		#if defined(CONFIG_RTL8821A) && defined(CONFIG_SDIO_HCI)
-+		/* 8821A's LED2 circuit(used by HW_LED strategy) needs enable WL GPIO control of GPIO[14:13], can't disable */
-+		&& (!IS_HW_LED_STRATEGY(rtw_led_get_strategy(padapter)) || enable)
-+		#endif
-+	)
-+		rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable));
-+}
-+
-+void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval)
-+{
-+#if defined(CONFIG_RTL8192F)
-+	rtw_hal_set_hwreg(padapter, HW_VAR_WOW_OUTPUT_GPIO, (u8 *)(&outputval));
-+#else
-+	if (index <= 7) {
-+		/* config GPIO mode */
-+		rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3,
-+			rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));
-+
-+		/* config GPIO Sel */
-+		/* 0: input */
-+		/* 1: output */
-+		rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2,
-+			rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index));
-+
-+		/* set output value */
-+		if (outputval) {
-+			rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1,
-+				rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index));
-+		} else {
-+			rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1,
-+				rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index));
-+		}
-+	} else if (index <= 15) {
-+		/* 88C Series: */
-+		/* index: 11~8 transform to 3~0 */
-+		/* 8723 Series: */
-+		/* index: 12~8 transform to 4~0 */
-+
-+		index -= 8;
-+
-+		/* config GPIO mode */
-+		rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3,
-+			rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));
-+
-+		/* config GPIO Sel */
-+		/* 0: input */
-+		/* 1: output */
-+		rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2,
-+			rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index));
-+
-+		/* set output value */
-+		if (outputval) {
-+			rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1,
-+				rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index));
-+		} else {
-+			rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1,
-+				rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index));
-+		}
-+	} else {
-+		RTW_INFO("%s: invalid GPIO%d=%d\n",
-+			 __FUNCTION__, index, outputval);
-+	}
-+#endif
-+}
-+void rtw_hal_set_input_gpio(_adapter *padapter, u8 index)
-+{
-+#if defined(CONFIG_RTL8192F)
-+	rtw_hal_set_hwreg(padapter, HW_VAR_WOW_INPUT_GPIO, (u8 *)(&index));
-+#else
-+	if (index <= 7) {
-+		/* config GPIO mode */
-+		rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3,
-+			rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));
-+
-+		/* config GPIO Sel */
-+		/* 0: input */
-+		/* 1: output */
-+		rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2,
-+			rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) & ~BIT(index));
-+
-+	} else if (index <= 15) {
-+		/* 88C Series: */
-+		/* index: 11~8 transform to 3~0 */
-+		/* 8723 Series: */
-+		/* index: 12~8 transform to 4~0 */
-+
-+		index -= 8;
-+
-+		/* config GPIO mode */
-+		rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3,
-+			rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));
-+
-+		/* config GPIO Sel */
-+		/* 0: input */
-+		/* 1: output */
-+		rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2,
-+			rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) & ~BIT(index));
-+	} else
-+		RTW_INFO("%s: invalid GPIO%d\n", __func__, index);
-+#endif
-+}
-+
-+#endif
-+
-+void rtw_hal_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
-+{
-+	struct	pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	u8 ret = 0;
-+#ifdef CONFIG_WOWLAN
-+	u8 u1H2CAoacRsvdPageParm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0};
-+
-+	RTW_INFO("%s: RWC: %d ArpRsp: %d NbrAdv: %d LocNDPInfo: %d\n",
-+		 __func__, rsvdpageloc->LocRemoteCtrlInfo,
-+		 rsvdpageloc->LocArpRsp, rsvdpageloc->LocNbrAdv,
-+		 rsvdpageloc->LocNDPInfo);
-+	RTW_INFO("%s:GtkRsp: %d GtkInfo: %d ProbeReq: %d NetworkList: %d\n",
-+		 __func__, rsvdpageloc->LocGTKRsp, rsvdpageloc->LocGTKInfo,
-+		 rsvdpageloc->LocProbeReq, rsvdpageloc->LocNetList);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
-+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocRemoteCtrlInfo);
-+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocArpRsp);
-+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(u1H2CAoacRsvdPageParm,
-+							rsvdpageloc->LocNbrAdv);
-+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_NDP_INFO(u1H2CAoacRsvdPageParm,
-+						      rsvdpageloc->LocNDPInfo);
-+#ifdef CONFIG_GTK_OL
-+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKRsp);
-+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKInfo);
-+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKEXTMEM);
-+#endif /* CONFIG_GTK_OL */
-+		ret = rtw_hal_fill_h2c_cmd(padapter,
-+					   H2C_AOAC_RSVD_PAGE,
-+					   H2C_AOAC_RSVDPAGE_LOC_LEN,
-+					   u1H2CAoacRsvdPageParm);
-+
-+		RTW_INFO("AOAC Report=%d\n", rsvdpageloc->LocAOACReport);
-+		_rtw_memset(&u1H2CAoacRsvdPageParm, 0, sizeof(u1H2CAoacRsvdPageParm));
-+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_AOAC_REPORT(u1H2CAoacRsvdPageParm,
-+					 rsvdpageloc->LocAOACReport);
-+		ret = rtw_hal_fill_h2c_cmd(padapter,
-+				   H2C_AOAC_RSVDPAGE3,
-+				   H2C_AOAC_RSVDPAGE_LOC_LEN,
-+				   u1H2CAoacRsvdPageParm);
-+		pwrpriv->wowlan_aoac_rpt_loc = rsvdpageloc->LocAOACReport;
-+	}
-+#ifdef CONFIG_PNO_SUPPORT
-+	else {
-+
-+		if (!pwrpriv->wowlan_in_resume) {
-+			RTW_INFO("NLO_INFO=%d\n", rsvdpageloc->LocPNOInfo);
-+			_rtw_memset(&u1H2CAoacRsvdPageParm, 0,
-+				    sizeof(u1H2CAoacRsvdPageParm));
-+			SET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(u1H2CAoacRsvdPageParm,
-+						      rsvdpageloc->LocPNOInfo);
-+			ret = rtw_hal_fill_h2c_cmd(padapter,
-+						   H2C_AOAC_RSVDPAGE3,
-+						   H2C_AOAC_RSVDPAGE_LOC_LEN,
-+						   u1H2CAoacRsvdPageParm);
-+		}
-+	}
-+#endif /* CONFIG_PNO_SUPPORT */
-+#endif /* CONFIG_WOWLAN */
-+}
-+
-+#ifdef DBG_FW_DEBUG_MSG_PKT
-+void rtw_hal_set_fw_dbg_msg_pkt_rsvd_page_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
-+{
-+	struct	hal_ops *pHalFunc = &padapter->hal_func;
-+	u8	u1H2C_fw_dbg_msg_pkt_parm[H2C_FW_DBG_MSG_PKT_LEN] = {0};
-+	u8	ret = 0;
-+
-+
-+	RTW_INFO("RsvdPageLoc: loc_fw_dbg_msg_pkt =%d\n", rsvdpageloc->loc_fw_dbg_msg_pkt);
-+
-+	SET_H2CCMD_FW_DBG_MSG_PKT_EN(u1H2C_fw_dbg_msg_pkt_parm, 1);
-+	SET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(u1H2C_fw_dbg_msg_pkt_parm, rsvdpageloc->loc_fw_dbg_msg_pkt);
-+	ret = rtw_hal_fill_h2c_cmd(padapter,
-+				   H2C_FW_DBG_MSG_PKT,
-+				   H2C_FW_DBG_MSG_PKT_LEN,
-+				   u1H2C_fw_dbg_msg_pkt_parm);
-+
-+}
-+#endif /*DBG_FW_DEBUG_MSG_PKT*/
-+
-+/*#define DBG_GET_RSVD_PAGE*/
-+int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset,
-+	u32 page_num, u8 *buffer, u32 buffer_size)
-+{
-+	u32 addr = 0, size = 0, count = 0;
-+	u32 page_size = 0, data_low = 0, data_high = 0;
-+	u16 txbndy = 0, offset = 0;
-+	u8 i = 0;
-+	bool rst = _FALSE;
-+
-+#ifdef DBG_LA_MODE
-+	struct registry_priv *registry_par = &adapter->registrypriv;
-+
-+	if(registry_par->la_mode_en == 1) {
-+		RTW_INFO("%s LA debug mode can't dump rsvd pg \n", __func__);
-+		return rst;
-+	}
-+#endif
-+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
-+
-+	addr = page_offset * page_size;
-+	size = page_num * page_size;
-+
-+	if (buffer_size < size) {
-+		RTW_ERR("%s buffer_size(%d) < get page total size(%d)\n",
-+			__func__, buffer_size, size);
-+		return rst;
-+	}
-+#ifdef RTW_HALMAC
-+	if (rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), 2, addr, size, buffer) < 0)
-+		rst = _FALSE;
-+	else
-+		rst = _TRUE;
-+#else
-+	txbndy = rtw_read8(adapter, REG_TDECTRL + 1);
-+
-+	offset = (txbndy + page_offset) * page_size / 8;
-+	count = (buffer_size / 8) + 1;
-+
-+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x69);
-+
-+	for (i = 0 ; i < count ; i++) {
-+		rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, offset + i);
-+		data_low = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
-+		data_high = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
-+		_rtw_memcpy(buffer + (i * 8),
-+			&data_low, sizeof(data_low));
-+		_rtw_memcpy(buffer + ((i * 8) + 4),
-+			&data_high, sizeof(data_high));
-+	}
-+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x0);
-+	rst = _TRUE;
-+#endif /*RTW_HALMAC*/
-+
-+#ifdef DBG_GET_RSVD_PAGE
-+	RTW_INFO("%s [page_offset:%d , page_num:%d][start_addr:0x%04x , size:%d]\n",
-+		 __func__, page_offset, page_num, addr, size);
-+	RTW_INFO_DUMP("\n", buffer, size);
-+	RTW_INFO(" ==================================================\n");
-+#endif
-+	return rst;
-+}
-+
-+void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num)
-+{
-+#if defined(CONFIG_RTW_DEBUG) || defined(CONFIG_PROC_DEBUG)
-+	u32 page_size = 0;
-+	u8 *buffer = NULL;
-+	u32 buf_size = 0;
-+
-+	if (page_num == 0)
-+		return;
-+
-+	RTW_PRINT_SEL(sel, "======= RSVD PAGE DUMP =======\n");
-+	RTW_PRINT_SEL(sel, "page_offset:%d, page_num:%d\n", page_offset, page_num);
-+
-+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
-+	if (page_size) {
-+		buf_size = page_size * page_num;
-+		buffer = rtw_zvmalloc(buf_size);
-+
-+		if (buffer) {
-+			rtw_hal_get_rsvd_page(adapter, page_offset, page_num, buffer, buf_size);
-+			RTW_DUMP_SEL(sel, buffer, buf_size);
-+			rtw_vmfree(buffer, buf_size);
-+		} else
-+			RTW_PRINT_SEL(sel, "ERROR - rsvd_buf mem allocate failed\n");
-+	} else
-+			RTW_PRINT_SEL(sel, "ERROR - Tx page size is zero ??\n");
-+
-+	RTW_PRINT_SEL(sel, "==========================\n");
-+#endif
-+}
-+
-+#ifdef CONFIG_SUPPORT_FIFO_DUMP
-+void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size)
-+{
-+	u8 *buffer = NULL;
-+	u32 buff_size = 0;
-+	static const char * const fifo_sel_str[] = {
-+		"TX", "RX", "RSVD_PAGE", "REPORT", "LLT", "RXBUF_FW"
-+	};
-+
-+	if (fifo_sel > 5) {
-+		RTW_ERR("fifo_sel:%d invalid\n", fifo_sel);
-+		return;
-+	}
-+
-+	RTW_PRINT_SEL(sel, "========= FIFO DUMP =========\n");
-+	RTW_PRINT_SEL(sel, "%s FIFO DUMP [start_addr:0x%04x , size:%d]\n", fifo_sel_str[fifo_sel], fifo_addr, fifo_size);
-+
-+	if (fifo_size) {
-+		buff_size = RND4(fifo_size);
-+		buffer = rtw_zvmalloc(buff_size);
-+		if (buffer == NULL)
-+			buff_size = 0;
-+	}
-+
-+	rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), fifo_sel, fifo_addr, buff_size, buffer);
-+
-+	if (buffer) {
-+		RTW_DUMP_SEL(sel, buffer, fifo_size);
-+		rtw_vmfree(buffer, buff_size);
-+	}
-+
-+	RTW_PRINT_SEL(sel, "==========================\n");
-+}
-+#endif
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+static void rtw_hal_force_enable_rxdma(_adapter *adapter)
-+{
-+	RTW_INFO("%s: Set 0x690=0x00\n", __func__);
-+	rtw_write8(adapter, REG_WOW_CTRL,
-+		   (rtw_read8(adapter, REG_WOW_CTRL) & 0xf0));
-+	RTW_PRINT("%s: Release RXDMA\n", __func__);
-+	rtw_write32(adapter, REG_RXPKT_NUM,
-+		    (rtw_read32(adapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN)));
-+}
-+#if defined(CONFIG_RTL8188E)
-+static void rtw_hal_disable_tx_report(_adapter *adapter)
-+{
-+	rtw_write8(adapter, REG_TX_RPT_CTRL,
-+		   ((rtw_read8(adapter, REG_TX_RPT_CTRL) & ~BIT(1))) & ~BIT(5));
-+	RTW_INFO("disable TXRPT:0x%02x\n", rtw_read8(adapter, REG_TX_RPT_CTRL));
-+}
-+
-+static void rtw_hal_enable_tx_report(_adapter *adapter)
-+{
-+	rtw_write8(adapter, REG_TX_RPT_CTRL,
-+		   ((rtw_read8(adapter, REG_TX_RPT_CTRL) | BIT(1))) | BIT(5));
-+	RTW_INFO("enable TX_RPT:0x%02x\n", rtw_read8(adapter, REG_TX_RPT_CTRL));
-+}
-+#endif
-+static void rtw_hal_release_rx_dma(_adapter *adapter)
-+{
-+	u32 val32 = 0;
-+
-+	val32 = rtw_read32(adapter, REG_RXPKT_NUM);
-+
-+	rtw_write32(adapter, REG_RXPKT_NUM, (val32 & (~RW_RELEASE_EN)));
-+
-+	RTW_INFO("%s, [0x%04x]: 0x%08x\n",
-+		 __func__, REG_RXPKT_NUM, (u32)(val32 & (~RW_RELEASE_EN)));
-+}
-+
-+static u8 rtw_hal_pause_rx_dma(_adapter *adapter)
-+{
-+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
-+	u8 ret = 0;
-+	s8 trycnt = 100;
-+	u32 tmp = 0;
-+	int res = 0;
-+	/* RX DMA stop */
-+	RTW_PRINT("Pause DMA\n");
-+	rtw_write32(adapter, REG_RXPKT_NUM,
-+		    (rtw_read32(adapter, REG_RXPKT_NUM) | RW_RELEASE_EN));
-+	do {
-+		if ((rtw_read32(adapter, REG_RXPKT_NUM) & RXDMA_IDLE)) {
-+#ifdef CONFIG_USB_HCI
-+			/* stop interface before leave */
-+			if (_TRUE == hal->usb_intf_start) {
-+				rtw_intf_stop(adapter);
-+				RTW_ENABLE_FUNC(adapter, DF_RX_BIT);
-+				RTW_ENABLE_FUNC(adapter, DF_TX_BIT);
-+			}
-+#endif /* CONFIG_USB_HCI */
-+
-+			RTW_PRINT("RX_DMA_IDLE is true\n");
-+			ret = _SUCCESS;
-+			break;
-+		}
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+		else {
-+			res = RecvOnePkt(adapter);
-+			RTW_PRINT("RecvOnePkt Result: %d\n", res);
-+		}
-+#endif /* CONFIG_SDIO_HCI || CONFIG_GSPI_HCI */
-+
-+#ifdef CONFIG_USB_HCI
-+		else {
-+			/* to avoid interface start repeatedly  */
-+			if (_FALSE == hal->usb_intf_start)
-+				rtw_intf_start(adapter);
-+		}
-+#endif /* CONFIG_USB_HCI */
-+	} while (trycnt--);
-+
-+	if (trycnt < 0) {
-+		tmp = rtw_read16(adapter, REG_RXPKT_NUM + 2);
-+
-+		RTW_PRINT("Stop RX DMA failed......\n");
-+#if defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B)
-+		RTW_PRINT("%s, RXPKT_NUM: 0x%04x\n",
-+			  __func__, rtw_read16(adapter, REG_RXPKTNUM));
-+#else
-+		RTW_PRINT("%s, RXPKT_NUM: 0x%02x\n",
-+			  __func__, ((tmp & 0xFF00) >> 8));
-+#endif
-+		if (tmp & BIT(3))
-+			RTW_PRINT("%s, RX DMA has req\n",
-+				  __func__);
-+		else
-+			RTW_PRINT("%s, RX DMA no req\n",
-+				  __func__);
-+		ret = _FAIL;
-+	}
-+
-+	return ret;
-+}
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+#ifndef RTW_HALMAC
-+static u8 rtw_hal_enable_cpwm2(_adapter *adapter)
-+{
-+	u8 ret = 0;
-+	int res = 0;
-+	u32 tmp = 0;
-+#ifdef CONFIG_GPIO_WAKEUP
-+	return _SUCCESS;
-+#else
-+	RTW_PRINT("%s\n", __func__);
-+
-+	res = sdio_local_read(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
-+	if (!res)
-+		RTW_INFO("read SDIO_REG_HIMR: 0x%08x\n", tmp);
-+	else
-+		RTW_INFO("sdio_local_read fail\n");
-+
-+	tmp = SDIO_HIMR_CPWM2_MSK;
-+
-+	res = sdio_local_write(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
-+
-+	if (!res) {
-+		res = sdio_local_read(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
-+		RTW_INFO("read again SDIO_REG_HIMR: 0x%08x\n", tmp);
-+		ret = _SUCCESS;
-+	} else {
-+		RTW_INFO("sdio_local_write fail\n");
-+		ret = _FAIL;
-+	}
-+	return ret;
-+#endif /* CONFIG_CPIO_WAKEUP */
-+}
-+#endif
-+#endif /* CONFIG_SDIO_HCI, CONFIG_GSPI_HCI */
-+#endif /* CONFIG_WOWLAN || CONFIG_AP_WOWLAN */
-+
-+#ifdef CONFIG_WOWLAN
-+/*
-+ * rtw_hal_check_wow_ctrl
-+ * chk_type: _TRUE means to check enable, if 0x690 & bit1 (for 8051), WOW enable successful.
-+ *									If 0x1C7 == 0 (for 3081), WOW enable successful.
-+ *		     _FALSE means to check disable, if 0x690 & bit1 (for 8051), WOW disable fail.
-+ *									If 0x120 & bit16 || 0x284 & bit18 (for 3081), WOW disable fail.
-+ */
-+static u8 rtw_hal_check_wow_ctrl(_adapter *adapter, u8 chk_type)
-+{
-+	u32 fe1_imr = 0xFF, rxpkt_num = 0xFF;
-+	u8 mstatus = 0;
-+	u8 reason = 0xFF;
-+	u8 trycnt = 25;
-+	u8 res = _FALSE;
-+
-+	if (IS_HARDWARE_TYPE_JAGUAR2(adapter) || IS_HARDWARE_TYPE_JAGUAR3(adapter)) {
-+		if (chk_type) {
-+			reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
-+			RTW_INFO("%s reason:0x%02x\n", __func__, reason);
-+
-+			while (reason && trycnt > 1) {
-+				reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
-+				RTW_PRINT("Loop index: %d :0x%02x\n",
-+					  trycnt, reason);
-+				trycnt--;
-+				rtw_msleep_os(20);
-+			}
-+			if (!reason)
-+				res = _TRUE;
-+			else
-+				res = _FALSE;
-+		} else {
-+			/* Wait FW to cleare 0x120 bit16, 0x284 bit18 to 0 */
-+			fe1_imr = rtw_read32(adapter, REG_FE1IMR); /* RxDone IMR for 3081 */
-+			rxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM); /* Release RXDMA */
-+			RTW_PRINT("%s REG_FE1IMR (reg120): 0x%x, REG_RXPKT_NUM(reg284): 0x%x\n", __func__, fe1_imr, rxpkt_num);
-+
-+			while (((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN)) && trycnt > 1) {
-+				rtw_msleep_os(20);
-+				fe1_imr = rtw_read32(adapter, REG_FE1IMR);
-+				rxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM);
-+				RTW_PRINT("Loop index: %d :0x%x, 0x%x\n",
-+					  trycnt, fe1_imr, rxpkt_num);
-+				trycnt--;
-+			}
-+
-+			if ((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN))
-+				res = _FALSE;
-+			else
-+				res = _TRUE;
-+		}
-+	} else {
-+		mstatus = rtw_read8(adapter, REG_WOW_CTRL);
-+		RTW_INFO("%s mstatus:0x%02x\n", __func__, mstatus);
-+
-+
-+		if (chk_type) {
-+			while (!(mstatus & BIT1) && trycnt > 1) {
-+				mstatus = rtw_read8(adapter, REG_WOW_CTRL);
-+				RTW_PRINT("Loop index: %d :0x%02x\n",
-+					  trycnt, mstatus);
-+				trycnt--;
-+				rtw_msleep_os(20);
-+			}
-+			if (mstatus & BIT1)
-+				res = _TRUE;
-+			else
-+				res = _FALSE;
-+		} else {
-+			while (mstatus & BIT1 && trycnt > 1) {
-+				mstatus = rtw_read8(adapter, REG_WOW_CTRL);
-+				RTW_PRINT("Loop index: %d :0x%02x\n",
-+					  trycnt, mstatus);
-+				trycnt--;
-+				rtw_msleep_os(20);
-+			}
-+
-+			if (mstatus & BIT1)
-+				res = _FALSE;
-+			else
-+				res = _TRUE;
-+		}
-+	}
-+
-+	RTW_PRINT("%s check_type: %d res: %d trycnt: %d\n",
-+		  __func__, chk_type, res, (25 - trycnt));
-+	return res;
-+}
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+static u8 rtw_hal_check_pno_enabled(_adapter *adapter)
-+{
-+	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
-+	u8 res = 0, count = 0;
-+	u8 ret = _FALSE;
-+
-+	if (ppwrpriv->wowlan_pno_enable && ppwrpriv->wowlan_in_resume == _FALSE) {
-+		res = rtw_read8(adapter, REG_PNO_STATUS);
-+		while (!(res & BIT(7)) && count < 25) {
-+			RTW_INFO("[%d] cmd: 0x81 REG_PNO_STATUS: 0x%02x\n",
-+				 count, res);
-+			res = rtw_read8(adapter, REG_PNO_STATUS);
-+			count++;
-+			rtw_msleep_os(2);
-+		}
-+		if (res & BIT(7))
-+			ret = _TRUE;
-+		else
-+			ret = _FALSE;
-+		RTW_INFO("cmd: 0x81 REG_PNO_STATUS: ret(%d)\n", ret);
-+	}
-+	return ret;
-+}
-+#endif
-+
-+static void rtw_hal_backup_rate(_adapter *adapter)
-+{
-+	RTW_INFO("%s\n", __func__);
-+	/* backup data rate to register 0x8b for wowlan FW */
-+	rtw_write8(adapter, 0x8d, 1);
-+	rtw_write8(adapter, 0x8c, 0);
-+	rtw_write8(adapter, 0x8f, 0x40);
-+	rtw_write8(adapter, 0x8b, rtw_read8(adapter, 0x2f0));
-+}
-+
-+#ifdef CONFIG_GTK_OL
-+static void rtw_hal_fw_sync_cam_id(_adapter *adapter)
-+{
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	int cam_id, index = 0;
-+	u8 *addr = NULL;
-+
-+	if (!MLME_IS_STA(adapter))
-+		return;
-+
-+	addr = get_bssid(pmlmepriv);
-+
-+	if (addr == NULL) {
-+		RTW_INFO("%s: get bssid MAC addr fail!!\n", __func__);
-+		return;
-+	}
-+
-+	rtw_clean_dk_section(adapter);
-+
-+	do {
-+		cam_id = rtw_camid_search(adapter, addr, index, 1);
-+
-+		if (cam_id == -1)
-+			RTW_INFO("%s: cam_id: %d, key_id:%d\n", __func__, cam_id, index);
-+		else
-+			rtw_sec_cam_swap(adapter, cam_id, index);
-+
-+		index++;
-+	} while (index < 4);
-+
-+	rtw_write8(adapter, REG_SECCFG, 0xcc);
-+}
-+
-+static void rtw_hal_update_gtk_offload_info(_adapter *adapter)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+	struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct security_priv *psecuritypriv = &adapter->securitypriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	_irqL irqL;
-+	u8 get_key[16];
-+	u8 gtk_id = 0, offset = 0, i = 0, sz = 0, aoac_rpt_ver = 0, has_rekey = _FALSE;
-+	u64 replay_count = 0, tmp_iv_hdr = 0, pkt_pn = 0;
-+
-+	if (!MLME_IS_STA(adapter))
-+		return;
-+
-+	_rtw_memset(get_key, 0, sizeof(get_key));
-+	_rtw_memcpy(&replay_count,
-+		paoac_rpt->replay_counter_eapol_key, 8);
-+
-+	/*read gtk key index*/
-+	gtk_id = paoac_rpt->key_index;
-+	aoac_rpt_ver = paoac_rpt->version_info;
-+
-+	if (aoac_rpt_ver == 0) {
-+		/* initial verison */
-+		if (gtk_id == 5)
-+			has_rekey = _FALSE;
-+		else
-+			has_rekey = _TRUE;
-+	} else if (aoac_rpt_ver >= 1) {
-+		/* Add krack patch */
-+		if (gtk_id == 5)
-+			RTW_WARN("%s FW check iv fail\n", __func__);
-+
-+		if (aoac_rpt_ver == 1)
-+			RTW_WARN("%s aoac report version should be update to v2\n", __func__);
-+
-+		/* Fix key id mismatch */
-+		if (aoac_rpt_ver == 2)
-+			has_rekey = paoac_rpt->rekey_ok == 1 ? _TRUE : _FALSE;
-+	}
-+
-+	if (has_rekey == _FALSE) {
-+		RTW_INFO("%s no rekey event happened.\n", __func__);
-+	} else if (has_rekey == _TRUE) {
-+		RTW_INFO("%s update security key.\n", __func__);
-+		/*read key from sec-cam,for DK ,keyindex is equal to cam-id*/
-+		rtw_sec_read_cam_ent(adapter, gtk_id,
-+				     NULL, NULL, get_key);
-+		rtw_clean_hw_dk_cam(adapter);
-+
-+		if (_rtw_camid_is_gk(adapter, gtk_id)) {
-+			_enter_critical_bh(&cam_ctl->lock, &irqL);
-+			_rtw_memcpy(&dvobj->cam_cache[gtk_id].key,
-+				    get_key, 16);
-+			_exit_critical_bh(&cam_ctl->lock, &irqL);
-+		} else {
-+			struct setkey_parm parm_gtk;
-+
-+			parm_gtk.algorithm = paoac_rpt->security_type;
-+			parm_gtk.keyid = gtk_id;
-+			_rtw_memcpy(parm_gtk.key, get_key, 16);
-+			setkey_hdl(adapter, (u8 *)&parm_gtk);
-+		}
-+
-+		/*update key into related sw variable and sec-cam cache*/
-+		psecuritypriv->dot118021XGrpKeyid = gtk_id;
-+		_rtw_memcpy(&psecuritypriv->dot118021XGrpKey[gtk_id],
-+				get_key, 16);
-+		/* update SW TKIP TX/RX MIC value */
-+		if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_) {
-+			offset = RTW_KEK_LEN + RTW_TKIP_MIC_LEN;
-+			_rtw_memcpy(
-+				&psecuritypriv->dot118021XGrptxmickey[gtk_id],
-+				&(paoac_rpt->group_key[offset]),
-+				RTW_TKIP_MIC_LEN);
-+
-+			offset = RTW_KEK_LEN;
-+			_rtw_memcpy(
-+				&psecuritypriv->dot118021XGrprxmickey[gtk_id],
-+				&(paoac_rpt->group_key[offset]),
-+				RTW_TKIP_MIC_LEN);
-+		}
-+		RTW_PRINT("GTK (%d) "KEY_FMT"\n", gtk_id,
-+			KEY_ARG(psecuritypriv->dot118021XGrpKey[gtk_id].skey));
-+	}
-+
-+	/* Update broadcast RX IV */
-+	if (psecuritypriv->dot118021XGrpPrivacy == _AES_) {
-+		sz = sizeof(psecuritypriv->iv_seq[0]);
-+		for (i = 0 ; i < 4 ; i++) {
-+			_rtw_memcpy(&tmp_iv_hdr, paoac_rpt->rxgtk_iv[i], sz);
-+			tmp_iv_hdr = le64_to_cpu(tmp_iv_hdr);
-+			pkt_pn = CCMPH_2_PN(tmp_iv_hdr);
-+			_rtw_memcpy(psecuritypriv->iv_seq[i], &pkt_pn, sz);
-+		}
-+	}
-+
-+	rtw_clean_dk_section(adapter);
-+
-+	rtw_write8(adapter, REG_SECCFG, 0x0c);
-+
-+	#ifdef CONFIG_GTK_OL_DBG
-+	/* if (gtk_keyindex != 5) */
-+	dump_sec_cam(RTW_DBGDUMP, adapter);
-+	dump_sec_cam_cache(RTW_DBGDUMP, adapter);
-+	#endif
-+}
-+#endif /*CONFIG_GTK_OL*/
-+
-+static void rtw_dump_aoac_rpt(_adapter *adapter)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+	struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
-+	int i = 0;
-+
-+	RTW_INFO_DUMP("[AOAC-RPT] IV -", paoac_rpt->iv, 8);
-+	RTW_INFO_DUMP("[AOAC-RPT] Replay counter of EAPOL key - ",
-+		paoac_rpt->replay_counter_eapol_key, 8);
-+	RTW_INFO_DUMP("[AOAC-RPT] Group key - ", paoac_rpt->group_key, 32);
-+	RTW_INFO("[AOAC-RPT] Key Index - %d\n", paoac_rpt->key_index);
-+	RTW_INFO("[AOAC-RPT] Security Type - %d\n", paoac_rpt->security_type);
-+	RTW_INFO("[AOAC-RPT] wow_pattern_idx - %d\n",
-+		 paoac_rpt->wow_pattern_idx);
-+	RTW_INFO("[AOAC-RPT] version_info - %d\n", paoac_rpt->version_info);
-+	RTW_INFO("[AOAC-RPT] rekey_ok - %d\n", paoac_rpt->rekey_ok);
-+	RTW_INFO_DUMP("[AOAC-RPT] RX PTK IV-", paoac_rpt->rxptk_iv, 8);
-+	RTW_INFO_DUMP("[AOAC-RPT] RX GTK[0] IV-", paoac_rpt->rxgtk_iv[0], 8);
-+	RTW_INFO_DUMP("[AOAC-RPT] RX GTK[1] IV-", paoac_rpt->rxgtk_iv[1], 8);
-+	RTW_INFO_DUMP("[AOAC-RPT] RX GTK[2] IV-", paoac_rpt->rxgtk_iv[2], 8);
-+	RTW_INFO_DUMP("[AOAC-RPT] RX GTK[3] IV-", paoac_rpt->rxgtk_iv[3], 8);
-+}
-+
-+static void rtw_hal_get_aoac_rpt(_adapter *adapter)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+	struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
-+	u32 page_offset = 0, page_number = 0;
-+	u32 page_size = 0, buf_size = 0;
-+	u8 *buffer = NULL;
-+	u8 i = 0, tmp = 0;
-+	int ret = -1;
-+
-+	/* read aoac report from rsvd page */
-+	page_offset = pwrctl->wowlan_aoac_rpt_loc;
-+	page_number = 1;
-+
-+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
-+	buf_size = page_size * page_number;
-+
-+	buffer = rtw_zvmalloc(buf_size);
-+
-+	if (buffer == NULL) {
-+		RTW_ERR("%s buffer allocate failed size(%d)\n",
-+			__func__, buf_size);
-+		return;
-+	}
-+
-+	RTW_INFO("Get AOAC Report from rsvd page_offset:%d\n", page_offset);
-+
-+	ret = rtw_hal_get_rsvd_page(adapter, page_offset,
-+		page_number, buffer, buf_size);
-+
-+	if (ret == _FALSE) {
-+		RTW_ERR("%s get aoac report failed\n", __func__);
-+		rtw_warn_on(1);
-+		goto _exit;
-+	}
-+
-+	_rtw_memset(paoac_rpt, 0, sizeof(struct aoac_report));
-+	_rtw_memcpy(paoac_rpt, buffer, sizeof(struct aoac_report));
-+
-+	for (i = 0 ; i < 4 ; i++) {
-+		tmp = paoac_rpt->replay_counter_eapol_key[i];
-+		paoac_rpt->replay_counter_eapol_key[i] =
-+			paoac_rpt->replay_counter_eapol_key[7 - i];
-+		paoac_rpt->replay_counter_eapol_key[7 - i] = tmp;
-+	}
-+
-+	rtw_dump_aoac_rpt(adapter);
-+
-+_exit:
-+	if (buffer)
-+		rtw_vmfree(buffer, buf_size);
-+}
-+
-+static void rtw_hal_update_tx_iv(_adapter *adapter)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+	struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
-+	struct sta_info	*psta;
-+	struct mlme_ext_priv	*pmlmeext = &(adapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct security_priv	*psecpriv = &adapter->securitypriv;
-+
-+	u16 val16 = 0;
-+	u32 val32 = 0;
-+	u64 txiv = 0;
-+	u8 *pval = NULL;
-+
-+	psta = rtw_get_stainfo(&adapter->stapriv,
-+			       get_my_bssid(&pmlmeinfo->network));
-+
-+	/* Update TX iv data. */
-+	pval = (u8 *)&paoac_rpt->iv;
-+
-+	if (psecpriv->dot11PrivacyAlgrthm == _TKIP_) {
-+		val16 = ((u16)(paoac_rpt->iv[2]) << 0) +
-+			((u16)(paoac_rpt->iv[0]) << 8);
-+		val32 = ((u32)(paoac_rpt->iv[4]) << 0) +
-+			((u32)(paoac_rpt->iv[5]) << 8) +
-+			((u32)(paoac_rpt->iv[6]) << 16) +
-+			((u32)(paoac_rpt->iv[7]) << 24);
-+	} else if (psecpriv->dot11PrivacyAlgrthm == _AES_) {
-+		val16 = ((u16)(paoac_rpt->iv[0]) << 0) +
-+			((u16)(paoac_rpt->iv[1]) << 8);
-+		val32 = ((u32)(paoac_rpt->iv[4]) << 0) +
-+			((u32)(paoac_rpt->iv[5]) << 8) +
-+			((u32)(paoac_rpt->iv[6]) << 16) +
-+			((u32)(paoac_rpt->iv[7]) << 24);
-+	}
-+
-+	if (psta) {
-+		txiv = val16 + ((u64)val32 << 16);
-+		if (txiv != 0)
-+			psta->dot11txpn.val = txiv;
-+	}
-+}
-+
-+static void rtw_hal_update_sw_security_info(_adapter *adapter)
-+{
-+	struct security_priv *psecpriv = &adapter->securitypriv;
-+	u8 sz = sizeof (psecpriv->iv_seq);
-+
-+	rtw_hal_update_tx_iv(adapter);
-+#ifdef CONFIG_GTK_OL
-+	if (psecpriv->binstallKCK_KEK == _TRUE &&
-+		(psecpriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK || _rtw_wow_chk_cap(adapter, WOW_CAP_TKIP_OL)))
-+		rtw_hal_update_gtk_offload_info(adapter);
-+#else
-+	_rtw_memset(psecpriv->iv_seq, 0, sz);
-+#endif
-+}
-+#ifdef CONFIG_CUSTOM_PULSE
-+static u8 rtw_hal_set_gpio_custom_cmd(_adapter *adapter, u8 enable)
-+{
-+	u8 H2CGpioCustomParm[H2C_GPIO_CUSTOM_LEN] = {0};
-+	u8 customid = 0x2, special_wakeup_reason = RX_MAGIC_PKT, custom_for_wakeup_reason=0x1;
-+	u8 ret = _FAIL;
-+
-+	RTW_INFO("%s(): enable = %d\n", __func__, enable);
-+
-+	if(enable) {
-+		SET_H2CCMD_CUSTOMERID(H2CGpioCustomParm, customid);
-+		SET_H2CCMD_SPECIAL_WAKE_REASON(H2CGpioCustomParm, special_wakeup_reason);
-+		SET_H2CCMD_CUSTOM_WAKE_REASON(H2CGpioCustomParm, custom_for_wakeup_reason);
-+
-+		ret = rtw_hal_fill_h2c_cmd(adapter,
-+						H2C_GPIO_CUSTOM,
-+						H2C_GPIO_CUSTOM_LEN,
-+						H2CGpioCustomParm);
-+		RTW_DBG("%s(): H2C_cmd=%x, cmd=%02x, %02x, %02x\n", __func__, H2C_GPIO_CUSTOM,
-+		H2CGpioCustomParm[0], H2CGpioCustomParm[1], H2CGpioCustomParm[2]);
-+	}
-+
-+	return ret;
-+}
-+#endif /* CONFIG_CUSTOM_PULSE */
-+static u8 rtw_hal_set_keep_alive_cmd(_adapter *adapter, u8 enable, u8 pkt_type)
-+{
-+	u8 u1H2CKeepAliveParm[H2C_KEEP_ALIVE_CTRL_LEN] = {0};
-+	u8 adopt = 1, check_period = 5;
-+	u8 ret = _FAIL;
-+	u8 hw_port = rtw_hal_get_port(adapter);
-+
-+	SET_H2CCMD_KEEPALIVE_PARM_ENABLE(u1H2CKeepAliveParm, enable);
-+	SET_H2CCMD_KEEPALIVE_PARM_ADOPT(u1H2CKeepAliveParm, adopt);
-+	SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(u1H2CKeepAliveParm, pkt_type);
-+	SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(u1H2CKeepAliveParm, check_period);
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+	SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(u1H2CKeepAliveParm, hw_port);
-+	RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, hw_port);
-+#else
-+	RTW_INFO("%s(): enable = %d\n", __func__, enable);
-+#endif
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+				   H2C_KEEP_ALIVE,
-+				   H2C_KEEP_ALIVE_CTRL_LEN,
-+				   u1H2CKeepAliveParm);
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+static u8 rtw_hal_set_keep_alive_pattern_cmd(PADAPTER adapter, u8 enable)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+	u8 u1H2CKeepAliveParm[H2C_KEEP_ALIVE_PATTERN_LEN] = {0};
-+	u8 ret = _FAIL;
-+	int i;
-+
-+	/* If keep alive pattern is set, FW will use pattern for keep alive action */
-+	if(enable == 0 || (pwrctl->wowlan_keep_alive_mode == wow_keep_alive_pattern_disable)) {
-+		SET_H2CCMD_UDP_KEEP_ALIVE_EN(u1H2CKeepAliveParm, _FALSE);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_ACK_PATTERN_EN(u1H2CKeepAliveParm, _FALSE);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_WAKE_EN(u1H2CKeepAliveParm, _FALSE);
-+		return ret;
-+	}
-+	/*step1:set keep alive period*/
-+	SET_H2CCMD_UDP_KEEP_ALIVE_PERIOD_LOW_BIT(u1H2CKeepAliveParm, pwrctl->wowlan_keep_alive_period & 0x00FF);
-+	SET_H2CCMD_UDP_KEEP_ALIVE_PERIOD_HI_BIT(u1H2CKeepAliveParm, ((pwrctl->wowlan_keep_alive_period & 0xFF00)>> 8));
-+
-+	if (pwrctl->wowlan_keep_alive_mode == wow_keep_alive_pattern_tx) {
-+		SET_H2CCMD_UDP_KEEP_ALIVE_EN(u1H2CKeepAliveParm, _TRUE);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_ACK_PATTERN_EN(u1H2CKeepAliveParm, _FALSE);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_WAKE_EN(u1H2CKeepAliveParm, _FALSE);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_PACKET_LOC(u1H2CKeepAliveParm, pwrctl->keep_alive_pattern_loc);
-+		goto exit;
-+	}
-+	if (pwrctl->wowlan_keep_alive_mode == wow_keep_alive_pattern_trx) {
-+		SET_H2CCMD_UDP_KEEP_ALIVE_EN(u1H2CKeepAliveParm, _TRUE);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_ACK_PATTERN_EN(u1H2CKeepAliveParm, _TRUE);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_WAKE_EN(u1H2CKeepAliveParm, _FALSE);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_PACKET_LOC(u1H2CKeepAliveParm, pwrctl->keep_alive_pattern_loc);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_ACK_PATTERN_idx(u1H2CKeepAliveParm, pwrctl->wowlan_keep_alive_ack_index);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_RETRY_INTERVAL(u1H2CKeepAliveParm, pwrctl->wowlan_keep_alive_retry_interval);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_RETRY_LIMIT(u1H2CKeepAliveParm, pwrctl->wowlan_keep_alive_retry_counter);
-+		goto exit;
-+	}
-+	if (pwrctl->wowlan_keep_alive_mode == wow_keep_alive_pattern_trx_with_ack) {
-+		SET_H2CCMD_UDP_KEEP_ALIVE_EN(u1H2CKeepAliveParm, _TRUE);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_ACK_PATTERN_EN(u1H2CKeepAliveParm, _TRUE);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_WAKE_EN(u1H2CKeepAliveParm, _TRUE);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_PACKET_LOC(u1H2CKeepAliveParm, pwrctl->keep_alive_pattern_loc);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_ACK_PATTERN_idx(u1H2CKeepAliveParm, pwrctl->wowlan_keep_alive_ack_index);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_WAKE_PATTERN_idx(u1H2CKeepAliveParm, pwrctl->wowlan_wake_pattern_index);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_RETRY_INTERVAL(u1H2CKeepAliveParm, pwrctl->wowlan_keep_alive_retry_interval);
-+		SET_H2CCMD_UDP_KEEP_ALIVE_RETRY_LIMIT(u1H2CKeepAliveParm, pwrctl->wowlan_keep_alive_retry_counter);
-+		goto exit;
-+	}
-+exit:
-+	for(i=0; i<H2C_KEEP_ALIVE_PATTERN_LEN; i++) {
-+		RTW_INFO("u1H2CKeepAliveParm[%d]= x%0x\n", i, u1H2CKeepAliveParm[i]);
-+	}
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+				   H2C_UDP_KEEPALIVE,
-+				   H2C_KEEP_ALIVE_PATTERN_LEN,
-+				   u1H2CKeepAliveParm);
-+
-+	return ret;
-+}
-+#endif/*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+
-+static u8 rtw_hal_set_disconnect_decision_cmd(_adapter *adapter, u8 enable)
-+{
-+	u8 u1H2CDisconDecisionParm[H2C_DISCON_DECISION_LEN] = {0};
-+	u8 adopt = 1, check_period = 100, trypkt_num = 5;
-+	u8 ret = _FAIL;
-+	struct registry_priv *pregistry = &adapter->registrypriv;
-+	u8 hw_port = rtw_hal_get_port(adapter);
-+
-+	SET_H2CCMD_DISCONDECISION_PARM_ENABLE(u1H2CDisconDecisionParm, enable);
-+	SET_H2CCMD_DISCONDECISION_PARM_ADOPT(u1H2CDisconDecisionParm, adopt);
-+	if (!(pregistry->wakeup_event & BIT(2)))
-+		SET_H2CCMD_DISCONDECISION_PARM_DISCONNECT_EN(u1H2CDisconDecisionParm, adopt);
-+	SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(u1H2CDisconDecisionParm, check_period);
-+	SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(u1H2CDisconDecisionParm, trypkt_num);
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+	SET_H2CCMD_DISCONDECISION_PORT_NUM(u1H2CDisconDecisionParm, hw_port);
-+	RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, hw_port);
-+#else
-+	RTW_INFO("%s(): enable = %d\n", __func__, enable);
-+#endif
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+				   H2C_DISCON_DECISION,
-+				   H2C_DISCON_DECISION_LEN,
-+				   u1H2CDisconDecisionParm);
-+	return ret;
-+}
-+
-+static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_unit)
-+{
-+	struct registry_priv  *registry_par = &adapter->registrypriv;
-+	struct security_priv *psecpriv = &adapter->securitypriv;
-+	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
-+	struct mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
-+
-+	u8 u1H2CWoWlanCtrlParm[H2C_WOWLAN_LEN] = {0};
-+	u8 discont_wake = 0, gpionum = 0, gpio_dur = 0, no_wake = 0;
-+	u8 hw_unicast = 0, gpio_pulse_cnt = 0, gpio_pulse_en = 0;
-+	u8 sdio_wakeup_enable = 1;
-+	u8 gpio_high_active = 0;
-+	u8 magic_pkt = 0;
-+	u8 gpio_unit = 0; /*0: 64ns, 1: 8ms*/
-+	u8 ret = _FAIL;
-+#ifdef CONFIG_DIS_UPHY
-+	u8 dis_uphy = 0, dis_uphy_unit = 0, dis_uphy_time = 0;
-+#endif /* CONFIG_DIS_UPHY */
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+	gpio_high_active = ppwrpriv->is_high_active;
-+	gpionum = ppwrpriv->wowlan_gpio_index;
-+	sdio_wakeup_enable = 0;
-+#endif /* CONFIG_GPIO_WAKEUP */
-+	
-+	if(registry_par->suspend_type == FW_IPS_DISABLE_BBRF &&
-+	!check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
-+		no_wake = 1;
-+		
-+	if (!ppwrpriv->wowlan_pno_enable &&
-+		registry_par->wakeup_event & BIT(0) && !no_wake)
-+		magic_pkt = enable;
-+
-+	if ((registry_par->wakeup_event & BIT(1)) &&
-+		(psecpriv->dot11PrivacyAlgrthm == _WEP40_ ||
-+		psecpriv->dot11PrivacyAlgrthm == _WEP104_) && !no_wake)
-+			hw_unicast = 1;
-+
-+	if (registry_par->wakeup_event & BIT(2) && !no_wake)
-+		discont_wake = enable;
-+
-+	RTW_INFO("%s(): enable=%d change_unit=%d\n", __func__,
-+		 enable, change_unit);
-+
-+	/* time = (gpio_dur/2) * gpio_unit, default:256 ms */
-+	if (enable && change_unit) {
-+		gpio_dur = 0x40;
-+		gpio_unit = 1;
-+		gpio_pulse_en = 1;
-+	}
-+
-+#ifdef CONFIG_PLATFORM_ARM_RK3188
-+	if (enable) {
-+		gpio_pulse_en = 1;
-+		gpio_pulse_cnt = 0x04;
-+	}
-+#endif
-+
-+	SET_H2CCMD_WOWLAN_FUNC_ENABLE(u1H2CWoWlanCtrlParm, enable);
-+	if(!no_wake)
-+		SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(u1H2CWoWlanCtrlParm, enable);
-+	SET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(u1H2CWoWlanCtrlParm, magic_pkt);
-+	SET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(u1H2CWoWlanCtrlParm, hw_unicast);
-+	SET_H2CCMD_WOWLAN_ALL_PKT_DROP(u1H2CWoWlanCtrlParm, 0);
-+	SET_H2CCMD_WOWLAN_GPIO_ACTIVE(u1H2CWoWlanCtrlParm, gpio_high_active);
-+
-+#ifdef CONFIG_GTK_OL
-+	if (psecpriv->binstallKCK_KEK == _TRUE &&
-+		(psecpriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK || _rtw_wow_chk_cap(adapter, WOW_CAP_TKIP_OL)))
-+		SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 0);
-+	else
-+		SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 1);
-+#else
-+	SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, enable);
-+#endif
-+	SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(u1H2CWoWlanCtrlParm, discont_wake);
-+	SET_H2CCMD_WOWLAN_GPIONUM(u1H2CWoWlanCtrlParm, gpionum);
-+	SET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(u1H2CWoWlanCtrlParm, sdio_wakeup_enable);
-+
-+	SET_H2CCMD_WOWLAN_GPIO_DURATION(u1H2CWoWlanCtrlParm, gpio_dur);
-+	SET_H2CCMD_WOWLAN_CHANGE_UNIT(u1H2CWoWlanCtrlParm, gpio_unit);
-+
-+	SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(u1H2CWoWlanCtrlParm, gpio_pulse_en);
-+	SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(u1H2CWoWlanCtrlParm, gpio_pulse_cnt);
-+
-+#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
-+	if (enable)
-+		SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(u1H2CWoWlanCtrlParm, 1);
-+#endif
-+
-+#ifdef CONFIG_DIS_UPHY
-+	if (enable) {
-+		dis_uphy = 1;
-+		/* time unit: 0 -> ms, 1 -> 256 ms*/
-+		dis_uphy_unit = 1;
-+		dis_uphy_time = 0x4;
-+	}
-+
-+	SET_H2CCMD_WOWLAN_DISABLE_UPHY(u1H2CWoWlanCtrlParm, dis_uphy);
-+	SET_H2CCMD_WOWLAN_UNIT_FOR_UPHY_DISABLE(u1H2CWoWlanCtrlParm, dis_uphy_unit);
-+	SET_H2CCMD_WOWLAN_TIME_FOR_UPHY_DISABLE(u1H2CWoWlanCtrlParm, dis_uphy_time);
-+	if (ppwrpriv->hst2dev_high_active == 1)
-+		SET_H2CCMD_WOWLAN_RISE_HST2DEV(u1H2CWoWlanCtrlParm, 1);
-+#ifdef CONFIG_RTW_ONE_PIN_GPIO
-+	SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(u1H2CWoWlanCtrlParm, 1);
-+	SET_H2CCMD_WOWLAN_DEV2HST_EN(u1H2CWoWlanCtrlParm, 1);
-+	SET_H2CCMD_WOWLAN_HST2DEV_EN(u1H2CWoWlanCtrlParm, 0);
-+#else
-+	SET_H2CCMD_WOWLAN_HST2DEV_EN(u1H2CWoWlanCtrlParm, 1);
-+#endif /* CONFIG_RTW_ONE_PIN_GPIO */
-+#endif /* CONFIG_DIS_UPHY */
-+
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+				   H2C_WOWLAN,
-+				   H2C_WOWLAN_LEN,
-+				   u1H2CWoWlanCtrlParm);
-+	return ret;
-+}
-+
-+static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable)
-+{
-+	struct security_priv *psecuritypriv = &(adapter->securitypriv);
-+	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
-+	struct registry_priv *pregistrypriv = &adapter->registrypriv;
-+	u8 arp_en = pregistrypriv->wakeup_event & BIT(3);
-+	u8 u1H2CRemoteWakeCtrlParm[H2C_REMOTE_WAKE_CTRL_LEN] = {0};
-+	u8 ret = _FAIL, count = 0, no_wake = 0;
-+	struct mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
-+
-+	RTW_INFO("%s(): enable=%d\n", __func__, enable);
-+
-+	if(pregistrypriv->suspend_type == FW_IPS_DISABLE_BBRF &&
-+	!check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
-+		no_wake = 1;
-+	if(no_wake) {
-+		SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(
-+			u1H2CRemoteWakeCtrlParm, enable);
-+	} else {
-+		if (!ppwrpriv->wowlan_pno_enable) {
-+			SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(
-+				u1H2CRemoteWakeCtrlParm, enable);
-+			if (arp_en)
-+				SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(
-+					u1H2CRemoteWakeCtrlParm, 1);
-+			else
-+				SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(
-+					u1H2CRemoteWakeCtrlParm, 0);
-+	#ifdef CONFIG_GTK_OL
-+			if (psecuritypriv->binstallKCK_KEK == _TRUE &&
-+				(psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK || _rtw_wow_chk_cap(adapter, WOW_CAP_TKIP_OL))) {
-+				SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(
-+					u1H2CRemoteWakeCtrlParm, 1);
-+			} else {
-+				RTW_INFO("no kck kek\n");
-+				SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(
-+					u1H2CRemoteWakeCtrlParm, 0);
-+			}
-+	#endif /* CONFIG_GTK_OL */
-+	
-+	#ifdef CONFIG_IPV6
-+			if (ppwrpriv->wowlan_ns_offload_en == _TRUE) {
-+				RTW_INFO("enable NS offload\n");
-+				SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(
-+					u1H2CRemoteWakeCtrlParm, enable);
-+			}
-+	
-+			/*
-+			 * filter NetBios name service pkt to avoid being waked-up
-+			 * by this kind of unicast pkt this exceptional modification
-+			 * is used for match competitor's behavior
-+			 */
-+	
-+			SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(
-+				u1H2CRemoteWakeCtrlParm, enable);
-+	#endif /*CONFIG_IPV6*/
-+#if 0 /* replaced by WOWLAN pattern match */
-+	#ifdef CONFIG_RTL8192F
-+			if (IS_HARDWARE_TYPE_8192F(adapter)){
-+				SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(
-+					u1H2CRemoteWakeCtrlParm, enable);
-+			}
-+	#endif /* CONFIG_RTL8192F */
-+#endif
-+			if ((psecuritypriv->dot11PrivacyAlgrthm == _AES_) ||
-+				(psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) ||
-+				(psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_)) {
-+				SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
-+					u1H2CRemoteWakeCtrlParm, 0);
-+			} else { /* WEP etc. */
-+				if (arp_en)
-+					SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
-+						u1H2CRemoteWakeCtrlParm, 1);
-+			}
-+	
-+			if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
-+#ifdef CONFIG_GTK_OL
-+				if(_rtw_wow_chk_cap(adapter, WOW_CAP_TKIP_OL))
-+					SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(
-+						u1H2CRemoteWakeCtrlParm, enable);
-+#endif /* CONFIG_GTK_OL */
-+				if (IS_HARDWARE_TYPE_8188E(adapter) ||
-+				    IS_HARDWARE_TYPE_8812(adapter)) {
-+					SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(
-+						u1H2CRemoteWakeCtrlParm, 0);
-+					if (arp_en)
-+						SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
-+							u1H2CRemoteWakeCtrlParm, 1);
-+				}
-+			}
-+	
-+			SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(
-+				u1H2CRemoteWakeCtrlParm, 1);
-+		}
-+	#ifdef CONFIG_PNO_SUPPORT
-+		else {
-+			SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(
-+				u1H2CRemoteWakeCtrlParm, enable);
-+			SET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(
-+				u1H2CRemoteWakeCtrlParm, enable);
-+		}
-+	#endif
-+	
-+	#ifdef CONFIG_P2P_WOWLAN
-+		if (_TRUE == ppwrpriv->wowlan_p2p_mode) {
-+			RTW_INFO("P2P OFFLOAD ENABLE\n");
-+			SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(u1H2CRemoteWakeCtrlParm, 1);
-+		} else {
-+			RTW_INFO("P2P OFFLOAD DISABLE\n");
-+			SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(u1H2CRemoteWakeCtrlParm, 0);
-+		}
-+	#endif /* CONFIG_P2P_WOWLAN */
-+	}
-+
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+				   H2C_REMOTE_WAKE_CTRL,
-+				   H2C_REMOTE_WAKE_CTRL_LEN,
-+				   u1H2CRemoteWakeCtrlParm);
-+	return ret;
-+}
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+static u8 rtw_hal_set_war_offload_ctrl_cmd(_adapter *adapter, u8 enable)
-+{
-+	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
-+	u8 u1H2CWarOffloadParm[H2C_WAR_OFFLOAD_LEN] = {0};
-+	u8 ret = _FAIL;
-+
-+	RTW_INFO("%s(): enable=%d\n", __func__, enable);
-+
-+	if (_TRUE == ppwrpriv->wowlan_war_offload_mode) {
-+		SET_H2CCMD_WAR_CFG_EN(u1H2CWarOffloadParm, enable);
-+		SET_H2CCMD_WAR_CFG_ARP_RSP_EN(u1H2CWarOffloadParm, 1);
-+
-+#ifdef CONFIG_OFFLOAD_MDNS_V4
-+		if (WAR_MDNS_V4_RSP_EN & ppwrpriv->wowlan_war_offload_ctrl) {
-+			SET_H2CCMD_WAR_CFG_MDNSV4_RSP_EN(u1H2CWarOffloadParm, 1);
-+		}
-+		if (WAR_MDNS_V4_WAKEUP_EN& ppwrpriv->wowlan_war_offload_ctrl) {
-+			SET_H2CCMD_WAR_CFG_MDNSV4_WAKE_EN(u1H2CWarOffloadParm, 1);
-+		}
-+#endif /* CONFIG_OFFLOAD_MDNS_V4 */
-+
-+#ifdef CONFIG_OFFLOAD_MDNS_V6
-+		if (WAR_MDNS_V6_RSP_EN & ppwrpriv->wowlan_war_offload_ctrl) {
-+			SET_H2CCMD_WAR_CFG_MDNSV6_RSP_EN(u1H2CWarOffloadParm, 1);
-+		}
-+		if (WAR_MDNS_V6_WAKEUP_EN & ppwrpriv->wowlan_war_offload_ctrl) {
-+			SET_H2CCMD_WAR_CFG_MDNSV6_WAKE_EN(u1H2CWarOffloadParm, 1);
-+		}
-+#endif /* CONFIG_OFFLOAD_MDNS_V6 */
-+
-+	}
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+					H2C_WAR_OFFLOAD,
-+					H2C_WAR_OFFLOAD_LEN,
-+					u1H2CWarOffloadParm);
-+	return ret;
-+}
-+
-+static u8 rtw_hal_set_war_offload_parm(_adapter *adapter, PRSVDPAGE_LOC rsvdpageloc)
-+{
-+	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
-+	u8 u1H2CWarOfldParm[H2C_WAROFLD_RSVDPAGE1_LEN] = {0};
-+	u8 ret = _FAIL;
-+
-+	SET_H2CCMD_WAROFLD_RSVDPAGE1_LOC_PARM(u1H2CWarOfldParm, rsvdpageloc->LocIpParm);
-+	RTW_INFO("%s(): LocIpParm = %d\n", __func__, rsvdpageloc->LocIpParm);
-+
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+					H2C_WAROFLD_RSVDPAGE1,
-+					H2C_WAROFLD_RSVDPAGE1_LEN,
-+					u1H2CWarOfldParm);
-+
-+	return ret;
-+}
-+#endif /* CONFIG_WAR_OFFLOAD */
-+
-+
-+
-+static u8 rtw_hal_set_global_info_cmd(_adapter *adapter, u8 group_alg, u8 pairwise_alg)
-+{
-+	u8 ret = _FAIL;
-+	u8 u1H2CAOACGlobalInfoParm[H2C_AOAC_GLOBAL_INFO_LEN] = {0};
-+
-+	RTW_INFO("%s(): group_alg=%d pairwise_alg=%d\n",
-+		 __func__, group_alg, pairwise_alg);
-+	SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(u1H2CAOACGlobalInfoParm,
-+			pairwise_alg);
-+	SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(u1H2CAOACGlobalInfoParm,
-+			group_alg);
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+				   H2C_AOAC_GLOBAL_INFO,
-+				   H2C_AOAC_GLOBAL_INFO_LEN,
-+				   u1H2CAOACGlobalInfoParm);
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+static u8 rtw_hal_set_scan_offload_info_cmd(_adapter *adapter,
-+		PRSVDPAGE_LOC rsvdpageloc, u8 enable)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	u8 u1H2CScanOffloadInfoParm[H2C_SCAN_OFFLOAD_CTRL_LEN] = {0};
-+	u8 res = 0, count = 0, ret = _FAIL;
-+
-+	RTW_INFO("%s: loc_probe_packet:%d, loc_scan_info: %d loc_ssid_info:%d\n",
-+		 __func__, rsvdpageloc->LocProbePacket,
-+		 rsvdpageloc->LocScanInfo, rsvdpageloc->LocSSIDInfo);
-+
-+	SET_H2CCMD_AOAC_NLO_FUN_EN(u1H2CScanOffloadInfoParm, enable);
-+	SET_H2CCMD_AOAC_NLO_IPS_EN(u1H2CScanOffloadInfoParm, enable);
-+	SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(u1H2CScanOffloadInfoParm,
-+					       rsvdpageloc->LocScanInfo);
-+	SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(u1H2CScanOffloadInfoParm,
-+			rsvdpageloc->LocProbePacket);
-+	/*
-+		SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(u1H2CScanOffloadInfoParm,
-+				rsvdpageloc->LocSSIDInfo);
-+	*/
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+				   H2C_D0_SCAN_OFFLOAD_INFO,
-+				   H2C_SCAN_OFFLOAD_CTRL_LEN,
-+				   u1H2CScanOffloadInfoParm);
-+	return ret;
-+}
-+#endif /* CONFIG_PNO_SUPPORT */
-+
-+void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable)
-+{
-+	struct security_priv *psecpriv = &padapter->securitypriv;
-+	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(padapter);
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct registry_priv *pregistry = &padapter->registrypriv;
-+	u8	pkt_type = 0, no_wake = 0;
-+	
-+	if(pregistry->suspend_type == FW_IPS_DISABLE_BBRF &&
-+	!check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
-+		no_wake = 1;
-+
-+	RTW_PRINT("+%s()+: enable=%d\n", __func__, enable);
-+
-+	rtw_hal_set_wowlan_ctrl_cmd(padapter, enable, _FALSE);
-+
-+	if (enable) {
-+		if(!no_wake)
-+			rtw_hal_set_global_info_cmd(padapter,
-+					    psecpriv->dot118021XGrpPrivacy,
-+					    psecpriv->dot11PrivacyAlgrthm);
-+
-+		if (!(ppwrpriv->wowlan_pno_enable)) {
-+			if (!no_wake)
-+				rtw_hal_set_disconnect_decision_cmd(padapter,
-+								    enable);
-+#ifdef CONFIG_ARP_KEEP_ALIVE
-+			if ((psecpriv->dot11PrivacyAlgrthm == _WEP40_) ||
-+			    (psecpriv->dot11PrivacyAlgrthm == _WEP104_))
-+				pkt_type = 0;
-+			else
-+				pkt_type = 1;
-+#else
-+			pkt_type = 0;
-+#endif /* CONFIG_ARP_KEEP_ALIVE */
-+			if(!no_wake) {
-+				#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+				rtw_hal_set_keep_alive_pattern_cmd(padapter,enable);
-+				#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+				rtw_hal_set_keep_alive_cmd(padapter, enable, pkt_type);
-+                        }
-+		}
-+#ifdef CONFIG_PNO_SUPPORT
-+		rtw_hal_check_pno_enabled(padapter);
-+#endif /* CONFIG_PNO_SUPPORT */
-+#ifdef CONFIG_WAR_OFFLOAD
-+		rtw_hal_set_war_offload_ctrl_cmd(padapter, enable);
-+#endif /* CONFIG_WAR_OFFLOAD */
-+
-+	} else {
-+#if 0
-+		{
-+			u32 PageSize = 0;
-+			rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&PageSize);
-+			dump_TX_FIFO(padapter, 4, PageSize);
-+		}
-+#endif
-+	}
-+#ifdef CONFIG_CUSTOM_PULSE
-+	rtw_hal_set_gpio_custom_cmd(padapter, enable);
-+#endif /* CONFIG_CUSTOM_PULSE */
-+	rtw_hal_set_remote_wake_ctrl_cmd(padapter, enable);
-+	RTW_PRINT("-%s()-\n", __func__);
-+}
-+#endif /* CONFIG_WOWLAN */
-+
-+#ifdef CONFIG_AP_WOWLAN
-+static u8 rtw_hal_set_ap_wowlan_ctrl_cmd(_adapter *adapter, u8 enable)
-+{
-+	struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
-+
-+	u8 u1H2CAPWoWlanCtrlParm[H2C_AP_WOW_GPIO_CTRL_LEN] = {0};
-+	u8 gpionum = 0, gpio_dur = 0;
-+	u8 gpio_pulse = enable;
-+	u8 sdio_wakeup_enable = 1;
-+	u8 gpio_high_active = 0;
-+	u8 ret = _FAIL;
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+	gpio_high_active = ppwrpriv->is_high_active;
-+	gpionum = ppwrpriv->wowlan_gpio_index;
-+	sdio_wakeup_enable = 0;
-+#endif /*CONFIG_GPIO_WAKEUP*/
-+
-+	RTW_INFO("%s(): enable=%d\n", __func__, enable);
-+
-+	SET_H2CCMD_AP_WOW_GPIO_CTRL_INDEX(u1H2CAPWoWlanCtrlParm,
-+					  gpionum);
-+	SET_H2CCMD_AP_WOW_GPIO_CTRL_PLUS(u1H2CAPWoWlanCtrlParm,
-+					 gpio_pulse);
-+	SET_H2CCMD_AP_WOW_GPIO_CTRL_HIGH_ACTIVE(u1H2CAPWoWlanCtrlParm,
-+						gpio_high_active);
-+	SET_H2CCMD_AP_WOW_GPIO_CTRL_EN(u1H2CAPWoWlanCtrlParm,
-+				       enable);
-+	SET_H2CCMD_AP_WOW_GPIO_CTRL_DURATION(u1H2CAPWoWlanCtrlParm,
-+					     gpio_dur);
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+				   H2C_AP_WOW_GPIO_CTRL,
-+				   H2C_AP_WOW_GPIO_CTRL_LEN,
-+				   u1H2CAPWoWlanCtrlParm);
-+
-+	return ret;
-+}
-+
-+static u8 rtw_hal_set_ap_offload_ctrl_cmd(_adapter *adapter, u8 enable)
-+{
-+	u8 u1H2CAPOffloadCtrlParm[H2C_WOWLAN_LEN] = {0};
-+	u8 ret = _FAIL;
-+
-+	RTW_INFO("%s(): bFuncEn=%d\n", __func__, enable);
-+
-+	SET_H2CCMD_AP_WOWLAN_EN(u1H2CAPOffloadCtrlParm, enable);
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+				   H2C_AP_OFFLOAD,
-+				   H2C_AP_OFFLOAD_LEN,
-+				   u1H2CAPOffloadCtrlParm);
-+
-+	return ret;
-+}
-+
-+static u8 rtw_hal_set_ap_ps_cmd(_adapter *adapter, u8 enable)
-+{
-+	u8 ap_ps_parm[H2C_AP_PS_LEN] = {0};
-+	u8 ret = _FAIL;
-+
-+	RTW_INFO("%s(): enable=%d\n" , __func__ , enable);
-+
-+	SET_H2CCMD_AP_WOW_PS_EN(ap_ps_parm, enable);
-+#ifndef CONFIG_USB_HCI
-+	SET_H2CCMD_AP_WOW_PS_32K_EN(ap_ps_parm, enable);
-+#endif /*CONFIG_USB_HCI*/
-+	SET_H2CCMD_AP_WOW_PS_RF(ap_ps_parm, enable);
-+
-+	if (enable)
-+		SET_H2CCMD_AP_WOW_PS_DURATION(ap_ps_parm, 0x32);
-+	else
-+		SET_H2CCMD_AP_WOW_PS_DURATION(ap_ps_parm, 0x0);
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_SAP_PS_,
-+				   H2C_AP_PS_LEN, ap_ps_parm);
-+
-+	return ret;
-+}
-+
-+static void rtw_hal_set_ap_rsvdpage_loc_cmd(PADAPTER padapter,
-+		PRSVDPAGE_LOC rsvdpageloc)
-+{
-+	struct hal_ops *pHalFunc = &padapter->hal_func;
-+	u8 rsvdparm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0};
-+	u8 ret = _FAIL, header = 0;
-+
-+	if (pHalFunc->fill_h2c_cmd == NULL) {
-+		RTW_INFO("%s: Please hook fill_h2c_cmd first!\n", __func__);
-+		return;
-+	}
-+
-+	header = rtw_read8(padapter, REG_BCNQ_BDNY);
-+
-+	RTW_INFO("%s: beacon: %d, probeRsp: %d, header:0x%02x\n", __func__,
-+		 rsvdpageloc->LocApOffloadBCN,
-+		 rsvdpageloc->LocProbeRsp,
-+		 header);
-+
-+	SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_BCN(rsvdparm,
-+				      rsvdpageloc->LocApOffloadBCN + header);
-+
-+	ret = rtw_hal_fill_h2c_cmd(padapter, H2C_BCN_RSVDPAGE,
-+				   H2C_BCN_RSVDPAGE_LEN, rsvdparm);
-+
-+	if (ret == _FAIL)
-+		RTW_INFO("%s: H2C_BCN_RSVDPAGE cmd fail\n", __func__);
-+
-+	rtw_msleep_os(10);
-+
-+	_rtw_memset(&rsvdparm, 0, sizeof(rsvdparm));
-+
-+	SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_ProbeRsp(rsvdparm,
-+			rsvdpageloc->LocProbeRsp + header);
-+
-+	ret = rtw_hal_fill_h2c_cmd(padapter, H2C_PROBERSP_RSVDPAGE,
-+				   H2C_PROBERSP_RSVDPAGE_LEN, rsvdparm);
-+
-+	if (ret == _FAIL)
-+		RTW_INFO("%s: H2C_PROBERSP_RSVDPAGE cmd fail\n", __func__);
-+
-+	rtw_msleep_os(10);
-+}
-+
-+static void rtw_hal_set_fw_ap_wow_related_cmd(_adapter *padapter, u8 enable)
-+{
-+	rtw_hal_set_ap_offload_ctrl_cmd(padapter, enable);
-+	rtw_hal_set_ap_wowlan_ctrl_cmd(padapter, enable);
-+	rtw_hal_set_ap_ps_cmd(padapter, enable);
-+}
-+
-+static void rtw_hal_ap_wow_enable(_adapter *padapter)
-+{
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct sta_info *psta = NULL;
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+#ifdef DBG_CHECK_FW_PS_STATE
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+#endif /*DBG_CHECK_FW_PS_STATE*/
-+	int res;
-+	u16 media_status_rpt;
-+#ifdef CONFIG_GPIO_WAKEUP
-+	u8 val8 = 0;
-+#endif
-+
-+	RTW_INFO("%s, WOWLAN_AP_ENABLE\n", __func__);
-+#ifdef DBG_CHECK_FW_PS_STATE
-+	if (rtw_fw_ps_state(padapter) == _FAIL) {
-+		pdbgpriv->dbg_enwow_dload_fw_fail_cnt++;
-+		RTW_PRINT("wowlan enable no leave 32k\n");
-+	}
-+#endif /*DBG_CHECK_FW_PS_STATE*/
-+
-+	/* 1. Download WOWLAN FW*/
-+	rtw_hal_fw_dl(padapter, _TRUE);
-+
-+	media_status_rpt = RT_MEDIA_CONNECT;
-+	rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT,
-+			  (u8 *)&media_status_rpt);
-+
-+	issue_beacon(padapter, 0);
-+
-+	rtw_msleep_os(2);
-+	#if defined(CONFIG_RTL8188E)
-+	if (IS_HARDWARE_TYPE_8188E(padapter))
-+		rtw_hal_disable_tx_report(padapter);
-+	#endif
-+	/* RX DMA stop */
-+	res = rtw_hal_pause_rx_dma(padapter);
-+	if (res == _FAIL)
-+		RTW_PRINT("[WARNING] pause RX DMA fail\n");
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	/* Enable CPWM2 only. */
-+	res = rtw_hal_enable_cpwm2(padapter);
-+	if (res == _FAIL)
-+		RTW_PRINT("[WARNING] enable cpwm2 fail\n");
-+#endif
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+#ifdef CONFIG_RTW_ONE_PIN_GPIO
-+	rtw_hal_switch_gpio_wl_ctrl(padapter, pwrpriv->wowlan_gpio_index, _TRUE);
-+	rtw_hal_set_input_gpio(padapter, pwrpriv->wowlan_gpio_index);
-+#else
-+#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
-+	if (pwrctrlpriv->is_high_active == 0)
-+		rtw_hal_set_input_gpio(padapter, pwrpriv->wowlan_gpio_index);
-+	else
-+		rtw_hal_set_output_gpio(padapter, pwrpriv->wowlan_gpio_index,
-+			GPIO_OUTPUT_LOW);
-+#else
-+	val8 = (pwrpriv->is_high_active == 0) ? 1 : 0;
-+	rtw_hal_set_output_gpio(padapter, pwrpriv->wowlan_gpio_index, val8);
-+	rtw_hal_switch_gpio_wl_ctrl(padapter, pwrpriv->wowlan_gpio_index, _TRUE);
-+	RTW_INFO("%s: set GPIO_%d to OUTPUT %s state in ap wow suspend and %s_ACTIVE.\n",
-+		 __func__, pwrpriv->wowlan_gpio_index, 
-+		 pwrpriv->wowlan_gpio_output_state ? "HIGH" : "LOW",
-+		 pwrpriv->is_high_active ? "HIGI" : "LOW");
-+#endif /* CONFIG_WAKEUP_GPIO_INPUT_MODE */
-+#endif /* CONFIG_RTW_ONE_PIN_GPIO */
-+#endif /* CONFIG_GPIO_WAKEUP */
-+
-+	/* 5. Set Enable WOWLAN H2C command. */
-+	RTW_PRINT("Set Enable AP WOWLan cmd\n");
-+	rtw_hal_set_fw_ap_wow_related_cmd(padapter, 1);
-+
-+	rtw_write8(padapter, REG_MCUTST_WOWLAN, 0);
-+#ifdef CONFIG_USB_HCI
-+	rtw_mi_intf_stop(padapter);
-+#endif
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
-+	/* Invoid SE0 reset signal during suspending*/
-+	rtw_write8(padapter, REG_RSV_CTRL, 0x20);
-+	if (IS_8188F(pHalData->version_id) == FALSE
-+		&& IS_8188GTV(pHalData->version_id) == FALSE)
-+		rtw_write8(padapter, REG_RSV_CTRL, 0x60);
-+#endif
-+}
-+
-+static void rtw_hal_ap_wow_disable(_adapter *padapter)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
-+#ifdef DBG_CHECK_FW_PS_STATE
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+#endif /*DBG_CHECK_FW_PS_STATE*/
-+	u16 media_status_rpt;
-+
-+	RTW_INFO("%s, WOWLAN_AP_DISABLE\n", __func__);
-+	/* 1. Read wakeup reason*/
-+	pwrctl->wowlan_wake_reason = rtw_read8(padapter, REG_MCUTST_WOWLAN);
-+
-+	RTW_PRINT("wakeup_reason: 0x%02x\n",
-+		  pwrctl->wowlan_wake_reason);
-+
-+	rtw_hal_set_fw_ap_wow_related_cmd(padapter, 0);
-+
-+	rtw_msleep_os(2);
-+#ifdef DBG_CHECK_FW_PS_STATE
-+	if (rtw_fw_ps_state(padapter) == _FAIL) {
-+		pdbgpriv->dbg_diswow_dload_fw_fail_cnt++;
-+		RTW_PRINT("wowlan enable no leave 32k\n");
-+	}
-+#endif /*DBG_CHECK_FW_PS_STATE*/
-+
-+	#if defined(CONFIG_RTL8188E)
-+	if (IS_HARDWARE_TYPE_8188E(padapter))
-+		rtw_hal_enable_tx_report(padapter);
-+	#endif
-+
-+	rtw_hal_force_enable_rxdma(padapter);
-+
-+	rtw_hal_fw_dl(padapter, _FALSE);
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+#ifdef CONFIG_RTW_ONE_PIN_GPIO
-+	rtw_hal_set_input_gpio(padapter, pwrctl->wowlan_gpio_index);
-+#else
-+#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
-+	if (pwrctl->is_high_active == 0)
-+		rtw_hal_set_input_gpio(padapter, pwrctl->wowlan_gpio_index);
-+	else
-+		rtw_hal_set_output_gpio(padapter, pwrctl->wowlan_gpio_index
-+			, GPIO_OUTPUT_LOW);
-+#else
-+	rtw_hal_set_output_gpio(padapter, pwrctl->wowlan_gpio_index, 
-+		pwrctl->wowlan_gpio_output_state);
-+	RTW_INFO("%s: set GPIO_%d to OUTPUT %s state in ap wow resume and %s_ACTIVE.\n",
-+		 __func__, pwrctl->wowlan_gpio_index, 
-+		 pwrctl->wowlan_gpio_output_state ? "HIGH" : "LOW",
-+		 pwrctl->is_high_active ? "HIGI" : "LOW");
-+#endif /*CONFIG_WAKEUP_GPIO_INPUT_MODE*/
-+#endif /* CONFIG_RTW_ONE_PIN_GPIO */
-+#endif /* CONFIG_GPIO_WAKEUP */
-+	media_status_rpt = RT_MEDIA_CONNECT;
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT,
-+			  (u8 *)&media_status_rpt);
-+
-+	issue_beacon(padapter, 0);
-+}
-+#endif /*CONFIG_AP_WOWLAN*/
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+static int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode)
-+{
-+	u8 *ssid_ie;
-+	sint ssid_len_ori;
-+	int len_diff = 0;
-+
-+	ssid_ie = rtw_get_ie(ies,  WLAN_EID_SSID, &ssid_len_ori, ies_len);
-+
-+	/* RTW_INFO("%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\n", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); */
-+
-+	if (ssid_ie && ssid_len_ori > 0) {
-+		switch (hidden_ssid_mode) {
-+		case 1: {
-+			u8 *next_ie = ssid_ie + 2 + ssid_len_ori;
-+			u32 remain_len = 0;
-+
-+			remain_len = ies_len - (next_ie - ies);
-+
-+			ssid_ie[1] = 0;
-+			_rtw_memcpy(ssid_ie + 2, next_ie, remain_len);
-+			len_diff -= ssid_len_ori;
-+
-+			break;
-+		}
-+		case 2:
-+			_rtw_memset(&ssid_ie[2], 0, ssid_len_ori);
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	return len_diff;
-+}
-+
-+static void rtw_hal_construct_P2PBeacon(_adapter *padapter, u8 *pframe, u32 *pLength)
-+{
-+	/* struct xmit_frame	*pmgntframe; */
-+	/* struct pkt_attrib	*pattrib; */
-+	/* unsigned char	*pframe; */
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	unsigned short *fctrl;
-+	unsigned int	rate_len;
-+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
-+	u32	pktlen;
-+	/* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
-+	/*	_irqL irqL;
-+	 *	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	 * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
-+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+#endif /* CONFIG_P2P */
-+
-+	/* for debug */
-+	u8 *dbgbuf = pframe;
-+	u8 dbgbufLen = 0, index = 0;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+	/* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
-+	/*	_enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
-+	 * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
-+	/* pmlmeext->mgnt_seq++; */
-+	set_frame_sub_type(pframe, WIFI_BEACON);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
-+		/* RTW_INFO("ie len=%d\n", cur_network->IELength); */
-+#ifdef CONFIG_P2P
-+		/* for P2P : Primary Device Type & Device Name */
-+		u32 wpsielen = 0, insert_len = 0;
-+		u8 *wpsie = NULL;
-+		wpsie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen);
-+
-+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen > 0) {
-+			uint wps_offset, remainder_ielen;
-+			u8 *premainder_ie, *pframe_wscie;
-+
-+			wps_offset = (uint)(wpsie - cur_network->IEs);
-+
-+			premainder_ie = wpsie + wpsielen;
-+
-+			remainder_ielen = cur_network->IELength - wps_offset - wpsielen;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+			if (pwdinfo->driver_interface == DRIVER_CFG80211) {
-+				if (pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len > 0) {
-+					_rtw_memcpy(pframe, cur_network->IEs, wps_offset);
-+					pframe += wps_offset;
-+					pktlen += wps_offset;
-+
-+					_rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);
-+					pframe += pmlmepriv->wps_beacon_ie_len;
-+					pktlen += pmlmepriv->wps_beacon_ie_len;
-+
-+					/* copy remainder_ie to pframe */
-+					_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
-+					pframe += remainder_ielen;
-+					pktlen += remainder_ielen;
-+				} else {
-+					_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
-+					pframe += cur_network->IELength;
-+					pktlen += cur_network->IELength;
-+				}
-+			} else
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+			{
-+				pframe_wscie = pframe + wps_offset;
-+				_rtw_memcpy(pframe, cur_network->IEs, wps_offset + wpsielen);
-+				pframe += (wps_offset + wpsielen);
-+				pktlen += (wps_offset + wpsielen);
-+
-+				/* now pframe is end of wsc ie, insert Primary Device Type & Device Name */
-+				/*	Primary Device Type */
-+				/*	Type: */
-+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
-+				insert_len += 2;
-+
-+				/*	Length: */
-+				*(u16 *)(pframe + insert_len) = cpu_to_be16(0x0008);
-+				insert_len += 2;
-+
-+				/*	Value: */
-+				/*	Category ID */
-+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
-+				insert_len += 2;
-+
-+				/*	OUI */
-+				*(u32 *)(pframe + insert_len) = cpu_to_be32(WPSOUI);
-+				insert_len += 4;
-+
-+				/*	Sub Category ID */
-+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
-+				insert_len += 2;
-+
-+
-+				/*	Device Name */
-+				/*	Type: */
-+				*(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
-+				insert_len += 2;
-+
-+				/*	Length: */
-+				*(u16 *)(pframe + insert_len) = cpu_to_be16(pwdinfo->device_name_len);
-+				insert_len += 2;
-+
-+				/*	Value: */
-+				_rtw_memcpy(pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len);
-+				insert_len += pwdinfo->device_name_len;
-+
-+
-+				/* update wsc ie length */
-+				*(pframe_wscie + 1) = (wpsielen - 2) + insert_len;
-+
-+				/* pframe move to end */
-+				pframe += insert_len;
-+				pktlen += insert_len;
-+
-+				/* copy remainder_ie to pframe */
-+				_rtw_memcpy(pframe, premainder_ie, remainder_ielen);
-+				pframe += remainder_ielen;
-+				pktlen += remainder_ielen;
-+			}
-+		} else
-+#endif /* CONFIG_P2P */
-+		{
-+			int len_diff;
-+			_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
-+			len_diff = update_hidden_ssid(
-+					   pframe + _BEACON_IE_OFFSET_
-+				   , cur_network->IELength - _BEACON_IE_OFFSET_
-+					   , pmlmeinfo->hidden_ssid_mode
-+				   );
-+			pframe += (cur_network->IELength + len_diff);
-+			pktlen += (cur_network->IELength + len_diff);
-+		}
-+#if 0
-+		{
-+			u8 *wps_ie;
-+			uint wps_ielen;
-+			u8 sr = 0;
-+			wps_ie = rtw_get_wps_ie(pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_,
-+				pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_, NULL, &wps_ielen);
-+			if (wps_ie && wps_ielen > 0)
-+				rtw_get_wps_attr_content(wps_ie,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);
-+			if (sr != 0)
-+				set_fwstate(pmlmepriv, WIFI_UNDER_WPS);
-+			else
-+				_clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS);
-+		}
-+#endif
-+#ifdef CONFIG_P2P
-+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+			u32 len;
-+#ifdef CONFIG_IOCTL_CFG80211
-+			if (pwdinfo->driver_interface == DRIVER_CFG80211) {
-+				len = pmlmepriv->p2p_beacon_ie_len;
-+				if (pmlmepriv->p2p_beacon_ie && len > 0)
-+					_rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len);
-+			} else
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+			{
-+				len = build_beacon_p2p_ie(pwdinfo, pframe);
-+			}
-+
-+			pframe += len;
-+			pktlen += len;
-+
-+			#ifdef CONFIG_WFD
-+			len = rtw_append_beacon_wfd_ie(padapter, pframe);
-+			pframe += len;
-+			pktlen += len;
-+			#endif
-+
-+		}
-+#endif /* CONFIG_P2P */
-+
-+		goto _issue_bcn;
-+
-+	}
-+
-+	/* below for ad-hoc mode */
-+
-+	/* timestamp will be inserted by hardware */
-+	pframe += 8;
-+	pktlen += 8;
-+
-+	/* beacon interval: 2 bytes */
-+
-+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
-+
-+	pframe += 2;
-+	pktlen += 2;
-+
-+	/* capability info: 2 bytes */
-+
-+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
-+
-+	pframe += 2;
-+	pktlen += 2;
-+
-+	/* SSID */
-+	pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);
-+
-+	/* supported rates... */
-+	rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
-+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen);
-+
-+	/* DS parameter set */
-+	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);
-+
-+	/* if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) */
-+	{
-+		u8 erpinfo = 0;
-+		u32 ATIMWindow;
-+		/* IBSS Parameter Set... */
-+		/* ATIMWindow = cur->Configuration.ATIMWindow; */
-+		ATIMWindow = 0;
-+		pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);
-+
-+		/* ERP IE */
-+		pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pktlen);
-+	}
-+
-+
-+	/* EXTERNDED SUPPORTED RATE */
-+	if (rate_len > 8)
-+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);
-+
-+
-+	/* todo:HT for adhoc */
-+
-+_issue_bcn:
-+
-+	/* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
-+	/*	pmlmepriv->update_bcn = _FALSE;
-+	 *
-+	 *	_exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
-+	 * #endif */ /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
-+
-+	*pLength = pktlen;
-+#if 0
-+	/* printf dbg msg */
-+	dbgbufLen = pktlen;
-+	RTW_INFO("======> DBG MSG FOR CONSTRAUCT P2P BEACON\n");
-+
-+	for (index = 0; index < dbgbufLen; index++)
-+		printk("%x ", *(dbgbuf + index));
-+
-+	printk("\n");
-+	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT P2P BEACON\n");
-+
-+#endif
-+}
-+
-+static void rtw_hal_construct_P2PProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
-+{
-+	/* struct xmit_frame			*pmgntframe; */
-+	/* struct pkt_attrib			*pattrib; */
-+	/* unsigned char					*pframe; */
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	unsigned char					*mac;
-+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	/* WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network); */
-+	u16					beacon_interval = 100;
-+	u16					capInfo = 0;
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	u8					wpsie[255] = { 0x00 };
-+	u32					wpsielen = 0, p2pielen = 0;
-+	u32					pktlen;
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+	/* for debug */
-+	u8 *dbgbuf = pframe;
-+	u8 dbgbufLen = 0, index = 0;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	mac = adapter_mac_addr(padapter);
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	/* DA filled by FW */
-+	_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
-+
-+	/*	Use the device address for BSSID field.	 */
-+	_rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0);
-+	set_frame_sub_type(fctrl, WIFI_PROBERSP);
-+
-+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pframe += pktlen;
-+
-+
-+	/* timestamp will be inserted by hardware */
-+	pframe += 8;
-+	pktlen += 8;
-+
-+	/* beacon interval: 2 bytes */
-+	_rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2);
-+	pframe += 2;
-+	pktlen += 2;
-+
-+	/*	capability info: 2 bytes */
-+	/*	ESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) */
-+	capInfo |= cap_ShortPremble;
-+	capInfo |= cap_ShortSlot;
-+
-+	_rtw_memcpy(pframe, (unsigned char *) &capInfo, 2);
-+	pframe += 2;
-+	pktlen += 2;
-+
-+
-+	/* SSID */
-+	pframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pktlen);
-+
-+	/* supported rates... */
-+	/*	Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) */
-+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pktlen);
-+
-+	/* DS parameter set */
-+	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pktlen);
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
-+		if (pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL) {
-+			/* WPS IE */
-+			_rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);
-+			pktlen += pmlmepriv->wps_probe_resp_ie_len;
-+			pframe += pmlmepriv->wps_probe_resp_ie_len;
-+
-+			/* P2P IE */
-+			_rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len);
-+			pktlen += pmlmepriv->p2p_probe_resp_ie_len;
-+			pframe += pmlmepriv->p2p_probe_resp_ie_len;
-+		}
-+	} else
-+#endif /* CONFIG_IOCTL_CFG80211		 */
-+	{
-+
-+		/*	Todo: WPS IE */
-+		/*	Noted by Albert 20100907 */
-+		/*	According to the WPS specification, all the WPS attribute is presented by Big Endian. */
-+
-+		wpsielen = 0;
-+		/*	WPS OUI */
-+		*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
-+		wpsielen += 4;
-+
-+		/*	WPS version */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
-+
-+		/*	WiFi Simple Config State */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SIMPLE_CONF_STATE);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		wpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG;	/*	Not Configured. */
-+
-+		/*	Response Type */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_RESP_TYPE);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		wpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X;
-+
-+		/*	UUID-E */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		if (pwdinfo->external_uuid == 0) {
-+			_rtw_memset(wpsie + wpsielen, 0x0, 16);
-+			_rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN);
-+		} else
-+			_rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10);
-+		wpsielen += 0x10;
-+
-+		/*	Manufacturer */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MANUFACTURER);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0007);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		_rtw_memcpy(wpsie + wpsielen, "Realtek", 7);
-+		wpsielen += 7;
-+
-+		/*	Model Name */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NAME);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0006);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		_rtw_memcpy(wpsie + wpsielen, "8192CU", 6);
-+		wpsielen += 6;
-+
-+		/*	Model Number */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NUMBER);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		wpsie[wpsielen++] = 0x31;		/*	character 1 */
-+
-+		/*	Serial Number */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SERIAL_NUMBER);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(ETH_ALEN);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		_rtw_memcpy(wpsie + wpsielen, "123456" , ETH_ALEN);
-+		wpsielen += ETH_ALEN;
-+
-+		/*	Primary Device Type */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		/*	Category ID */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
-+		wpsielen += 2;
-+
-+		/*	OUI */
-+		*(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI);
-+		wpsielen += 4;
-+
-+		/*	Sub Category ID */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
-+		wpsielen += 2;
-+
-+		/*	Device Name */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		_rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len);
-+		wpsielen += pwdinfo->device_name_len;
-+
-+		/*	Config Method */
-+		/*	Type: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
-+		wpsielen += 2;
-+
-+		/*	Length: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
-+		wpsielen += 2;
-+
-+		/*	Value: */
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
-+		wpsielen += 2;
-+
-+
-+		pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);
-+
-+
-+		p2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe);
-+		pframe += p2pielen;
-+		pktlen += p2pielen;
-+	}
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = rtw_append_probe_resp_wfd_ie(padapter, pframe);
-+	pframe += wfdielen;
-+	pktlen += wfdielen;
-+#endif
-+
-+	*pLength = pktlen;
-+
-+#if 0
-+	/* printf dbg msg */
-+	dbgbufLen = pktlen;
-+	RTW_INFO("======> DBG MSG FOR CONSTRAUCT P2P Probe Rsp\n");
-+
-+	for (index = 0; index < dbgbufLen; index++)
-+		printk("%x ", *(dbgbuf + index));
-+
-+	printk("\n");
-+	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT P2P Probe Rsp\n");
-+#endif
-+}
-+static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
-+{
-+	struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
-+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
-+	u8			action = P2P_PUB_ACTION_ACTION;
-+	u32			p2poui = cpu_to_be32(P2POUI);
-+	u8			oui_subtype = P2P_GO_NEGO_RESP;
-+	u8			wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 };
-+	u8			p2pielen = 0, i;
-+	uint			wpsielen = 0;
-+	u16			wps_devicepassword_id = 0x0000;
-+	uint			wps_devicepassword_id_len = 0;
-+	u8			channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh;
-+	u16			len_channellist_attr = 0;
-+	u32			pktlen;
-+	u8			dialogToken = 0;
-+
-+	/* struct xmit_frame			*pmgntframe; */
-+	/* struct pkt_attrib			*pattrib; */
-+	/* unsigned char					*pframe; */
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	/* WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network); */
-+
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+	/* for debug */
-+	u8 *dbgbuf = pframe;
-+	u8 dbgbufLen = 0, index = 0;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	/* RA, filled by FW */
-+	_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0);
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pframe += pktlen;
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));
-+
-+	/* dialog token, filled by FW */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));
-+
-+	_rtw_memset(wpsie, 0x00, 255);
-+	wpsielen = 0;
-+
-+	/*	WPS Section */
-+	wpsielen = 0;
-+	/*	WPS OUI */
-+	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
-+	wpsielen += 4;
-+
-+	/*	WPS version */
-+	/*	Type: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
-+	wpsielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+	wpsielen += 2;
-+
-+	/*	Value: */
-+	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
-+
-+	/*	Device Password ID */
-+	/*	Type: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID);
-+	wpsielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
-+	wpsielen += 2;
-+
-+	/*	Value: */
-+	if (wps_devicepassword_id == WPS_DPID_USER_SPEC)
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC);
-+	else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC)
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC);
-+	else
-+		*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC);
-+	wpsielen += 2;
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);
-+
-+
-+	/*	P2P IE Section. */
-+
-+	/*	P2P OUI */
-+	p2pielen = 0;
-+	p2pie[p2pielen++] = 0x50;
-+	p2pie[p2pielen++] = 0x6F;
-+	p2pie[p2pielen++] = 0x9A;
-+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+	/*	Commented by Albert 20100908 */
-+	/*	According to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes */
-+	/*	1. Status */
-+	/*	2. P2P Capability */
-+	/*	3. Group Owner Intent */
-+	/*	4. Configuration Timeout */
-+	/*	5. Operating Channel */
-+	/*	6. Intended P2P Interface Address */
-+	/*	7. Channel List */
-+	/*	8. Device Info */
-+	/*	9. Group ID	( Only GO ) */
-+
-+
-+	/*	ToDo: */
-+
-+	/*	P2P Status */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_STATUS;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
-+	p2pielen += 2;
-+
-+	/*	Value, filled by FW */
-+	p2pie[p2pielen++] = 1;
-+
-+	/*	P2P Capability */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CAPABILITY;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Device Capability Bitmap, 1 byte */
-+
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
-+		/*	Commented by Albert 2011/03/08 */
-+		/*	According to the P2P specification */
-+		/*	if the sending device will be client, the P2P Capability should be reserved of group negotation response frame */
-+		p2pie[p2pielen++] = 0;
-+	} else {
-+		/*	Be group owner or meet the error case */
-+		p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT;
-+	}
-+
-+	/*	Group Capability Bitmap, 1 byte */
-+	if (pwdinfo->persistent_supported)
-+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP;
-+	else
-+		p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN;
-+
-+	/*	Group Owner Intent */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_GO_INTENT;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	if (pwdinfo->peer_intent & 0x01) {
-+		/*	Peer's tie breaker bit is 1, our tie breaker bit should be 0 */
-+		p2pie[p2pielen++] = (pwdinfo->intent << 1);
-+	} else {
-+		/*	Peer's tie breaker bit is 0, our tie breaker bit should be 1 */
-+		p2pie[p2pielen++] = ((pwdinfo->intent << 1) | BIT(0));
-+	}
-+
-+
-+	/*	Configuration Timeout */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
-+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
-+
-+	/*	Operating Channel */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Country String */
-+	p2pie[p2pielen++] = 'X';
-+	p2pie[p2pielen++] = 'X';
-+
-+	/*	The third byte should be set to 0x04. */
-+	/*	Described in the "Operating Channel Attribute" section. */
-+	p2pie[p2pielen++] = 0x04;
-+
-+	/*	Operating Class */
-+	if (pwdinfo->operating_channel <= 14) {
-+		/*	Operating Class */
-+		p2pie[p2pielen++] = 0x51;
-+	} else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) {
-+		/*	Operating Class */
-+		p2pie[p2pielen++] = 0x73;
-+	} else {
-+		/*	Operating Class */
-+		p2pie[p2pielen++] = 0x7c;
-+	}
-+
-+	/*	Channel Number */
-+	p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
-+
-+	/*	Intended P2P Interface Address	 */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
-+	p2pielen += ETH_ALEN;
-+
-+	/*	Channel List */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
-+
-+	/* Country String(3) */
-+	/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
-+	/* + number of channels in all classes */
-+	len_channellist_attr = 3
-+		       + (1 + 1) * (u16)ch_list->reg_classes
-+		       + get_reg_classes_full_count(ch_list);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_buddy_check_fwstate(padapter, WIFI_ASOC_STATE))
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
-+	else
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
-+
-+#else
-+
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
-+
-+#endif
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Country String */
-+	p2pie[p2pielen++] = 'X';
-+	p2pie[p2pielen++] = 'X';
-+
-+	/*	The third byte should be set to 0x04. */
-+	/*	Described in the "Operating Channel Attribute" section. */
-+	p2pie[p2pielen++] = 0x04;
-+
-+	/*	Channel Entry List */
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_check_status(padapter, MI_LINKED)) {
-+		u8 union_ch = rtw_mi_get_union_chan(padapter);
-+
-+		/*	Operating Class */
-+		if (union_ch > 14) {
-+			if (union_ch >= 149)
-+				p2pie[p2pielen++] = 0x7c;
-+			else
-+				p2pie[p2pielen++] = 0x73;
-+		} else
-+			p2pie[p2pielen++] = 0x51;
-+
-+
-+		/*	Number of Channels */
-+		/*	Just support 1 channel and this channel is AP's channel */
-+		p2pie[p2pielen++] = 1;
-+
-+		/*	Channel List */
-+		p2pie[p2pielen++] = union_ch;
-+	} else
-+#endif /* CONFIG_CONCURRENT_MODE */
-+	{
-+		int i, j;
-+		for (j = 0; j < ch_list->reg_classes; j++) {
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
-+
-+			/*	Number of Channels */
-+			p2pie[p2pielen++] = ch_list->reg_class[j].channels;
-+
-+			/*	Channel List */
-+			for (i = 0; i < ch_list->reg_class[j].channels; i++)
-+				p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
-+		}
-+	}
-+
-+	/*	Device Info */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
-+	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	P2P Device Address */
-+	_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
-+	p2pielen += ETH_ALEN;
-+
-+	/*	Config Method */
-+	/*	This field should be big endian. Noted by P2P specification. */
-+
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm);
-+
-+	p2pielen += 2;
-+
-+	/*	Primary Device Type */
-+	/*	Category ID */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA);
-+	p2pielen += 2;
-+
-+	/*	OUI */
-+	*(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI);
-+	p2pielen += 4;
-+
-+	/*	Sub Category ID */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER);
-+	p2pielen += 2;
-+
-+	/*	Number of Secondary Device Types */
-+	p2pie[p2pielen++] = 0x00;	/*	No Secondary Device Type List */
-+
-+	/*	Device Name */
-+	/*	Type: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME);
-+	p2pielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	_rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len);
-+	p2pielen += pwdinfo->device_name_len;
-+
-+	if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+		/*	Group ID Attribute */
-+		/*	Type: */
-+		p2pie[p2pielen++] = P2P_ATTR_GROUP_ID;
-+
-+		/*	Length: */
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen);
-+		p2pielen += 2;
-+
-+		/*	Value: */
-+		/*	p2P Device Address */
-+		_rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN);
-+		p2pielen += ETH_ALEN;
-+
-+		/*	SSID */
-+		_rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen);
-+		p2pielen += pwdinfo->nego_ssidlen;
-+
-+	}
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pktlen);
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe);
-+	pframe += wfdielen;
-+	pktlen += wfdielen;
-+#endif
-+
-+	*pLength = pktlen;
-+#if 0
-+	/* printf dbg msg */
-+	dbgbufLen = pktlen;
-+	RTW_INFO("======> DBG MSG FOR CONSTRAUCT Nego Rsp\n");
-+
-+	for (index = 0; index < dbgbufLen; index++)
-+		printk("%x ", *(dbgbuf + index));
-+
-+	printk("\n");
-+	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT Nego Rsp\n");
-+#endif
-+}
-+
-+static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
-+{
-+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
-+	u8			action = P2P_PUB_ACTION_ACTION;
-+	u32			p2poui = cpu_to_be32(P2POUI);
-+	u8			oui_subtype = P2P_INVIT_RESP;
-+	u8			p2pie[255] = { 0x00 };
-+	u8			p2pielen = 0, i;
-+	u8			channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0;
-+	u16			len_channellist_attr = 0;
-+	u32			pktlen;
-+	u8			dialogToken = 0;
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+	/* struct xmit_frame			*pmgntframe; */
-+	/* struct pkt_attrib			*pattrib; */
-+	/* unsigned char					*pframe; */
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+	/* for debug */
-+	u8 *dbgbuf = pframe;
-+	u8 dbgbufLen = 0, index = 0;
-+
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	/* RA fill by FW */
-+	_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+
-+	/* BSSID fill by FW */
-+	_rtw_memset(pwlanhdr->addr3, 0, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0);
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));
-+
-+	/* dialog token, filled by FW */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));
-+
-+	/*	P2P IE Section. */
-+
-+	/*	P2P OUI */
-+	p2pielen = 0;
-+	p2pie[p2pielen++] = 0x50;
-+	p2pie[p2pielen++] = 0x6F;
-+	p2pie[p2pielen++] = 0x9A;
-+	p2pie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+	/*	Commented by Albert 20101005 */
-+	/*	According to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes */
-+	/*	1. Status */
-+	/*	2. Configuration Timeout */
-+	/*	3. Operating Channel	( Only GO ) */
-+	/*	4. P2P Group BSSID	( Only GO ) */
-+	/*	5. Channel List */
-+
-+	/*	P2P Status */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_STATUS;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001);
-+	p2pielen += 2;
-+
-+	/*	Value: filled by FW, defult value is FAIL INFO UNAVAILABLE */
-+	p2pie[p2pielen++] = P2P_STATUS_FAIL_INFO_UNAVAILABLE;
-+
-+	/*	Configuration Timeout */
-+	/*	Type: */
-+	p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT;
-+
-+	/*	Length: */
-+	*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P GO */
-+	p2pie[p2pielen++] = 200;	/*	2 seconds needed to be the P2P Client */
-+
-+	/* due to defult value is FAIL INFO UNAVAILABLE, so the following IE is not needed */
-+#if 0
-+	if (status_code == P2P_STATUS_SUCCESS) {
-+		struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
-+
-+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+			/*	The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO */
-+			/*	In this case, the P2P Invitation response frame should carry the two more P2P attributes. */
-+			/*	First one is operating channel attribute. */
-+			/*	Second one is P2P Group BSSID attribute. */
-+
-+			/*	Operating Channel */
-+			/*	Type: */
-+			p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH;
-+
-+			/*	Length: */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005);
-+			p2pielen += 2;
-+
-+			/*	Value: */
-+			/*	Country String */
-+			p2pie[p2pielen++] = 'X';
-+			p2pie[p2pielen++] = 'X';
-+
-+			/*	The third byte should be set to 0x04. */
-+			/*	Described in the "Operating Channel Attribute" section. */
-+			p2pie[p2pielen++] = 0x04;
-+
-+			/*	Operating Class */
-+			p2pie[p2pielen++] = 0x51;	/*	Copy from SD7 */
-+
-+			/*	Channel Number */
-+			p2pie[p2pielen++] = pwdinfo->operating_channel;	/*	operating channel number */
-+
-+
-+			/*	P2P Group BSSID */
-+			/*	Type: */
-+			p2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID;
-+
-+			/*	Length: */
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
-+			p2pielen += 2;
-+
-+			/*	Value: */
-+			/*	P2P Device Address for GO */
-+			_rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN);
-+			p2pielen += ETH_ALEN;
-+
-+		}
-+
-+		/*	Channel List */
-+		/*	Type: */
-+		p2pie[p2pielen++] = P2P_ATTR_CH_LIST;
-+
-+		/*	Length: */
-+		/* Country String(3) */
-+		/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
-+		/* + number of channels in all classes */
-+		len_channellist_attr = 3
-+			+ (1 + 1) * (u16)ch_list->reg_classes
-+			+ get_reg_classes_full_count(ch_list);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED))
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(5 + 1);
-+		else
-+			*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
-+
-+#else
-+
-+		*(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr);
-+
-+#endif
-+		p2pielen += 2;
-+
-+		/*	Value: */
-+		/*	Country String */
-+		p2pie[p2pielen++] = 'X';
-+		p2pie[p2pielen++] = 'X';
-+
-+		/*	The third byte should be set to 0x04. */
-+		/*	Described in the "Operating Channel Attribute" section. */
-+		p2pie[p2pielen++] = 0x04;
-+
-+		/*	Channel Entry List */
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED)) {
-+			u8 union_ch = rtw_mi_get_union_chan(padapter);
-+
-+			/*	Operating Class */
-+			if (union_ch > 14) {
-+				if (union_ch >= 149)
-+					p2pie[p2pielen++] = 0x7c;
-+				else
-+					p2pie[p2pielen++] = 0x73;
-+
-+			} else
-+				p2pie[p2pielen++] = 0x51;
-+
-+
-+			/*	Number of Channels */
-+			/*	Just support 1 channel and this channel is AP's channel */
-+			p2pie[p2pielen++] = 1;
-+
-+			/*	Channel List */
-+			p2pie[p2pielen++] = union_ch;
-+		} else
-+#endif /* CONFIG_CONCURRENT_MODE */
-+		{
-+			int i, j;
-+			for (j = 0; j < ch_list->reg_classes; j++) {
-+				/*	Operating Class */
-+				p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
-+
-+				/*	Number of Channels */
-+				p2pie[p2pielen++] = ch_list->reg_class[j].channels;
-+
-+				/*	Channel List */
-+				for (i = 0; i < ch_list->reg_class[j].channels; i++)
-+					p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
-+			}
-+		}
-+	}
-+#endif
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pktlen);
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = build_invitation_resp_wfd_ie(pwdinfo, pframe);
-+	pframe += wfdielen;
-+	pktlen += wfdielen;
-+#endif
-+
-+	*pLength = pktlen;
-+
-+#if 0
-+	/* printf dbg msg */
-+	dbgbufLen = pktlen;
-+	RTW_INFO("======> DBG MSG FOR CONSTRAUCT Invite Rsp\n");
-+
-+	for (index = 0; index < dbgbufLen; index++)
-+		printk("%x ", *(dbgbuf + index));
-+
-+	printk("\n");
-+	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT Invite Rsp\n");
-+#endif
-+}
-+
-+
-+static void rtw_hal_construct_P2PProvisionDisRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
-+{
-+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
-+	u8			action = P2P_PUB_ACTION_ACTION;
-+	u8			dialogToken = 0;
-+	u32			p2poui = cpu_to_be32(P2POUI);
-+	u8			oui_subtype = P2P_PROVISION_DISC_RESP;
-+	u8			wpsie[100] = { 0x00 };
-+	u8			wpsielen = 0;
-+	u32			pktlen;
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+	/* struct xmit_frame			*pmgntframe; */
-+	/* struct pkt_attrib			*pattrib; */
-+	/* unsigned char					*pframe; */
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+	/* for debug */
-+	u8 *dbgbuf = pframe;
-+	u8 dbgbufLen = 0, index = 0;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	/* RA filled by FW */
-+	_rtw_memset(pwlanhdr->addr1, 0, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0);
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pktlen));
-+	/* dialog token, filled by FW */
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pktlen));
-+
-+	wpsielen = 0;
-+	/*	WPS OUI */
-+	/* *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); */
-+	RTW_PUT_BE32(wpsie, WPSOUI);
-+	wpsielen += 4;
-+
-+#if 0
-+	/*	WPS version */
-+	/*	Type: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
-+	wpsielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+	wpsielen += 2;
-+
-+	/*	Value: */
-+	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
-+#endif
-+
-+	/*	Config Method */
-+	/*	Type: */
-+	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); */
-+	RTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD);
-+	wpsielen += 2;
-+
-+	/*	Length: */
-+	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); */
-+	RTW_PUT_BE16(wpsie + wpsielen, 0x0002);
-+	wpsielen += 2;
-+
-+	/*	Value: filled by FW, default value is PBC */
-+	/* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method ); */
-+	RTW_PUT_BE16(wpsie + wpsielen, WPS_CM_PUSH_BUTTON);
-+	wpsielen += 2;
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pktlen);
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe);
-+	pframe += wfdielen;
-+	pktlen += wfdielen;
-+#endif
-+
-+	*pLength = pktlen;
-+
-+	/* printf dbg msg */
-+#if 0
-+	dbgbufLen = pktlen;
-+	RTW_INFO("======> DBG MSG FOR CONSTRAUCT  ProvisionDis Rsp\n");
-+
-+	for (index = 0; index < dbgbufLen; index++)
-+		printk("%x ", *(dbgbuf + index));
-+
-+	printk("\n");
-+	RTW_INFO("<====== DBG MSG FOR CONSTRAUCT ProvisionDis Rsp\n");
-+#endif
-+}
-+
-+u8 rtw_hal_set_FwP2PRsvdPage_cmd(_adapter *adapter, PRSVDPAGE_LOC rsvdpageloc)
-+{
-+	u8 u1H2CP2PRsvdPageParm[H2C_P2PRSVDPAGE_LOC_LEN] = {0};
-+	struct hal_ops *pHalFunc = &adapter->hal_func;
-+	u8 ret = _FAIL;
-+
-+	RTW_INFO("P2PRsvdPageLoc: P2PBeacon=%d P2PProbeRsp=%d NegoRsp=%d InviteRsp=%d PDRsp=%d\n",
-+		 rsvdpageloc->LocP2PBeacon, rsvdpageloc->LocP2PProbeRsp,
-+		 rsvdpageloc->LocNegoRsp, rsvdpageloc->LocInviteRsp,
-+		 rsvdpageloc->LocPDRsp);
-+
-+	SET_H2CCMD_RSVDPAGE_LOC_P2P_BCN(u1H2CP2PRsvdPageParm, rsvdpageloc->LocProbeRsp);
-+	SET_H2CCMD_RSVDPAGE_LOC_P2P_PROBE_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocPsPoll);
-+	SET_H2CCMD_RSVDPAGE_LOC_P2P_NEGO_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocNullData);
-+	SET_H2CCMD_RSVDPAGE_LOC_P2P_INVITE_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocQosNull);
-+	SET_H2CCMD_RSVDPAGE_LOC_P2P_PD_RSP(u1H2CP2PRsvdPageParm, rsvdpageloc->LocBTQosNull);
-+
-+	/* FillH2CCmd8723B(padapter, H2C_8723B_P2P_OFFLOAD_RSVD_PAGE, H2C_P2PRSVDPAGE_LOC_LEN, u1H2CP2PRsvdPageParm); */
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+				   H2C_P2P_OFFLOAD_RSVD_PAGE,
-+				   H2C_P2PRSVDPAGE_LOC_LEN,
-+				   u1H2CP2PRsvdPageParm);
-+
-+	return ret;
-+}
-+
-+u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter)
-+{
-+
-+	u8 offload_cmd[H2C_P2P_OFFLOAD_LEN] = {0};
-+	struct wifidirect_info	*pwdinfo = &(adapter->wdinfo);
-+	struct P2P_WoWlan_Offload_t *p2p_wowlan_offload = (struct P2P_WoWlan_Offload_t *)offload_cmd;
-+	struct hal_ops *pHalFunc = &adapter->hal_func;
-+	u8 ret = _FAIL;
-+
-+	_rtw_memset(p2p_wowlan_offload, 0 , sizeof(struct P2P_WoWlan_Offload_t));
-+	RTW_INFO("%s\n", __func__);
-+	switch (pwdinfo->role) {
-+	case P2P_ROLE_DEVICE:
-+		RTW_INFO("P2P_ROLE_DEVICE\n");
-+		p2p_wowlan_offload->role = 0;
-+		break;
-+	case P2P_ROLE_CLIENT:
-+		RTW_INFO("P2P_ROLE_CLIENT\n");
-+		p2p_wowlan_offload->role = 1;
-+		break;
-+	case P2P_ROLE_GO:
-+		RTW_INFO("P2P_ROLE_GO\n");
-+		p2p_wowlan_offload->role = 2;
-+		break;
-+	default:
-+		RTW_INFO("P2P_ROLE_DISABLE\n");
-+		break;
-+	}
-+	p2p_wowlan_offload->Wps_Config[0] = pwdinfo->supported_wps_cm >> 8;
-+	p2p_wowlan_offload->Wps_Config[1] = pwdinfo->supported_wps_cm;
-+	offload_cmd = (u8 *)p2p_wowlan_offload;
-+	RTW_INFO("p2p_wowlan_offload: %x:%x:%x\n", offload_cmd[0], offload_cmd[1], offload_cmd[2]);
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+				   H2C_P2P_OFFLOAD,
-+				   H2C_P2P_OFFLOAD_LEN,
-+				   offload_cmd);
-+	return ret;
-+
-+	/* FillH2CCmd8723B(adapter, H2C_8723B_P2P_OFFLOAD, sizeof(struct P2P_WoWlan_Offload_t), (u8 *)p2p_wowlan_offload); */
-+}
-+#endif /* CONFIG_P2P_WOWLAN */
-+
-+void rtw_hal_construct_beacon(_adapter *padapter,
-+				     u8 *pframe, u32 *pLength)
-+{
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	u16					*fctrl;
-+	u32					pktlen;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*cur_network = &(pmlmeinfo->network);
-+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+
-+
-+	/* RTW_INFO("%s\n", __FUNCTION__); */
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
-+	/* pmlmeext->mgnt_seq++; */
-+	set_frame_sub_type(pframe, WIFI_BEACON);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	/* timestamp will be inserted by hardware */
-+	pframe += 8;
-+	pktlen += 8;
-+
-+	/* beacon interval: 2 bytes */
-+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
-+
-+	pframe += 2;
-+	pktlen += 2;
-+
-+#if 0
-+	/* capability info: 2 bytes */
-+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
-+
-+	pframe += 2;
-+	pktlen += 2;
-+
-+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
-+		/* RTW_INFO("ie len=%d\n", cur_network->IELength); */
-+		pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs);
-+		_rtw_memcpy(pframe, cur_network->IEs + sizeof(NDIS_802_11_FIXED_IEs), pktlen);
-+
-+		goto _ConstructBeacon;
-+	}
-+
-+	/* below for ad-hoc mode */
-+
-+	/* SSID */
-+	pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);
-+
-+	/* supported rates... */
-+	rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
-+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen);
-+
-+	/* DS parameter set */
-+	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);
-+
-+	if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
-+		u32 ATIMWindow;
-+		/* IBSS Parameter Set... */
-+		/* ATIMWindow = cur->Configuration.ATIMWindow; */
-+		ATIMWindow = 0;
-+		pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);
-+	}
-+
-+
-+	/* todo: ERP IE */
-+
-+
-+	/* EXTERNDED SUPPORTED RATE */
-+	if (rate_len > 8)
-+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);
-+
-+	/* todo:HT for adhoc */
-+
-+_ConstructBeacon:
-+#endif
-+
-+	if ((pktlen + TXDESC_SIZE) > MAX_BEACON_LEN) {
-+		RTW_ERR("beacon frame too large ,len(%d,%d)\n",
-+			(pktlen + TXDESC_SIZE), MAX_BEACON_LEN);
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	*pLength = pktlen;
-+
-+	/* RTW_INFO("%s bcn_sz=%d\n", __FUNCTION__, pktlen); */
-+
-+}
-+
-+static void rtw_hal_construct_PSPoll(_adapter *padapter,
-+				     u8 *pframe, u32 *pLength)
-+{
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	u16					*fctrl;
-+	u32					pktlen;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	/* RTW_INFO("%s\n", __FUNCTION__); */
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	/* Frame control. */
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+	SetPwrMgt(fctrl);
-+	set_frame_sub_type(pframe, WIFI_PSPOLL);
-+
-+	/* AID. */
-+	set_duration(pframe, (pmlmeinfo->aid | 0xc000));
-+
-+	/* BSSID. */
-+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	/* TA. */
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+
-+	*pLength = 16;
-+}
-+
-+
-+#ifdef DBG_FW_DEBUG_MSG_PKT
-+void rtw_hal_construct_fw_dbg_msg_pkt(
-+	PADAPTER padapter,
-+	u8		*pframe,
-+	u32		*plength)
-+{
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	u16						*fctrl;
-+	u32						pktlen;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct wlan_network		*cur_network = &pmlmepriv->cur_network;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+
-+
-+	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &pwlanhdr->frame_ctl;
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0);
-+
-+	set_frame_sub_type(pframe, WIFI_DATA);
-+
-+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	*plength = pktlen;
-+}
-+#endif /*DBG_FW_DEBUG_MSG_PKT*/
-+
-+void rtw_hal_construct_NullFunctionData(
-+	PADAPTER padapter,
-+	u8		*pframe,
-+	u32		*pLength,
-+	u8		bQoS,
-+	u8		AC,
-+	u8		bEosp,
-+	u8		bForcePowerSave)
-+{
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	u16						*fctrl;
-+	u32						pktlen;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	struct wlan_network		*cur_network = &pmlmepriv->cur_network;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 *sta_addr = NULL;
-+	u8 bssid[ETH_ALEN] = {0};
-+
-+	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &pwlanhdr->frame_ctl;
-+	*(fctrl) = 0;
-+	if (bForcePowerSave)
-+		SetPwrMgt(fctrl);
-+
-+	sta_addr = get_my_bssid(&pmlmeinfo->network);
-+	if (NULL == sta_addr) {
-+		_rtw_memcpy(bssid, adapter_mac_addr(padapter), ETH_ALEN);
-+		sta_addr = bssid;
-+	}
-+
-+	switch (cur_network->network.InfrastructureMode) {
-+	case Ndis802_11Infrastructure:
-+		SetToDs(fctrl);
-+		_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr3, sta_addr, ETH_ALEN);
-+		break;
-+	case Ndis802_11APMode:
-+		SetFrDs(fctrl);
-+		_rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
-+		break;
-+	case Ndis802_11IBSS:
-+	default:
-+		_rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+		_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+		break;
-+	}
-+
-+	SetSeqNum(pwlanhdr, 0);
-+	set_duration(pwlanhdr, 0);
-+
-+	if (bQoS == _TRUE) {
-+		struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr;
-+
-+		set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);
-+
-+		pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe;
-+		SetPriority(&pwlanqoshdr->qc, AC);
-+		SetEOSP(&pwlanqoshdr->qc, bEosp);
-+
-+		pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);
-+	} else {
-+		set_frame_sub_type(pframe, WIFI_DATA_NULL);
-+
-+		pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+	}
-+
-+	*pLength = pktlen;
-+}
-+
-+void rtw_hal_construct_ProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength,
-+				BOOLEAN bHideSSID)
-+{
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	u16					*fctrl;
-+	u8					*mac, *bssid, *sta_addr;
-+	u32					pktlen;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX  *cur_network = &(pmlmeinfo->network);
-+
-+	/*RTW_INFO("%s\n", __FUNCTION__);*/
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	mac = adapter_mac_addr(padapter);
-+	bssid = cur_network->MacAddress;
-+	sta_addr = get_my_bssid(&pmlmeinfo->network);
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+	_rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0);
-+	set_frame_sub_type(fctrl, WIFI_PROBERSP);
-+
-+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pframe += pktlen;
-+
-+	if (cur_network->IELength > MAX_IE_SZ)
-+		return;
-+
-+	_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
-+	pframe += cur_network->IELength;
-+	pktlen += cur_network->IELength;
-+
-+	*pLength = pktlen;
-+}
-+
-+#ifdef CONFIG_WOWLAN
-+static void rtw_hal_append_tkip_mic(PADAPTER padapter,
-+				    u8 *pframe, u32 offset)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	struct mic_data	micdata;
-+	struct sta_info	*psta = NULL;
-+	int res = 0;
-+
-+	u8	*payload = (u8 *)(pframe + offset);
-+
-+	u8	mic[8];
-+	u8	priority[4] = {0x0};
-+	u8	null_key[16] = {0x0};
-+
-+	RTW_INFO("%s(): Add MIC, offset: %d\n", __func__, offset);
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	psta = rtw_get_stainfo(&padapter->stapriv,
-+			get_my_bssid(&(pmlmeinfo->network)));
-+	if (psta != NULL) {
-+		res = _rtw_memcmp(&psta->dot11tkiptxmickey.skey[0],
-+				  null_key, 16);
-+		if (res == _TRUE)
-+			RTW_INFO("%s(): STA dot11tkiptxmickey==0\n", __func__);
-+		rtw_secmicsetkey(&micdata, &psta->dot11tkiptxmickey.skey[0]);
-+	}
-+
-+	rtw_secmicappend(&micdata, pwlanhdr->addr3, 6);  /* DA */
-+
-+	rtw_secmicappend(&micdata, pwlanhdr->addr2, 6); /* SA */
-+
-+	priority[0] = 0;
-+
-+	rtw_secmicappend(&micdata, &priority[0], 4);
-+
-+	rtw_secmicappend(&micdata, payload, 36); /* payload length = 8 + 28 */
-+
-+	rtw_secgetmic(&micdata, &(mic[0]));
-+
-+	payload += 36;
-+
-+	_rtw_memcpy(payload, &(mic[0]), 8);
-+}
-+/*
-+ * Description:
-+ *	Construct the ARP response packet to support ARP offload.
-+ *   */
-+static void rtw_hal_construct_ARPRsp(
-+	PADAPTER padapter,
-+	u8			*pframe,
-+	u32			*pLength,
-+	u8			*pIPAddress
-+)
-+{
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	u16	*fctrl;
-+	u32	pktlen;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
-+	static u8	ARPLLCHeader[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x08, 0x06};
-+	u8	*pARPRspPkt = pframe;
-+	/* for TKIP Cal MIC */
-+	u8	*payload = pframe;
-+	u8	EncryptionHeadOverhead = 0, arp_offset = 0;
-+	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &pwlanhdr->frame_ctl;
-+	*(fctrl) = 0;
-+
-+	/* ------------------------------------------------------------------------- */
-+	/* MAC Header. */
-+	/* ------------------------------------------------------------------------- */
-+	SetFrameType(fctrl, WIFI_DATA);
-+	/* set_frame_sub_type(fctrl, 0); */
-+	SetToDs(fctrl);
-+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0);
-+	set_duration(pwlanhdr, 0);
-+	/* SET_80211_HDR_FRAME_CONTROL(pARPRspPkt, 0); */
-+	/* SET_80211_HDR_TYPE_AND_SUBTYPE(pARPRspPkt, Type_Data); */
-+	/* SET_80211_HDR_TO_DS(pARPRspPkt, 1); */
-+	/* SET_80211_HDR_ADDRESS1(pARPRspPkt, pMgntInfo->Bssid); */
-+	/* SET_80211_HDR_ADDRESS2(pARPRspPkt, Adapter->CurrentAddress); */
-+	/* SET_80211_HDR_ADDRESS3(pARPRspPkt, pMgntInfo->Bssid); */
-+
-+	/* SET_80211_HDR_DURATION(pARPRspPkt, 0); */
-+	/* SET_80211_HDR_FRAGMENT_SEQUENCE(pARPRspPkt, 0); */
-+#ifdef CONFIG_WAPI_SUPPORT
-+	*pLength = sMacHdrLng;
-+#else
-+	*pLength = 24;
-+#endif
-+	switch (psecuritypriv->dot11PrivacyAlgrthm) {
-+	case _WEP40_:
-+	case _WEP104_:
-+		EncryptionHeadOverhead = 4;
-+		break;
-+	case _TKIP_:
-+		EncryptionHeadOverhead = 8;
-+		break;
-+	case _AES_:
-+		EncryptionHeadOverhead = 8;
-+		break;
-+#ifdef CONFIG_WAPI_SUPPORT
-+	case _SMS4_:
-+		EncryptionHeadOverhead = 18;
-+		break;
-+#endif
-+	default:
-+		EncryptionHeadOverhead = 0;
-+	}
-+
-+	if (EncryptionHeadOverhead > 0) {
-+		_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
-+		*pLength += EncryptionHeadOverhead;
-+		/* SET_80211_HDR_WEP(pARPRspPkt, 1);  */ /* Suggested by CCW. */
-+		SetPrivacy(fctrl);
-+	}
-+
-+	/* ------------------------------------------------------------------------- */
-+	/* Frame Body. */
-+	/* ------------------------------------------------------------------------- */
-+	arp_offset = *pLength;
-+	pARPRspPkt = (u8 *)(pframe + arp_offset);
-+	payload = pARPRspPkt; /* Get Payload pointer */
-+	/* LLC header */
-+	_rtw_memcpy(pARPRspPkt, ARPLLCHeader, 8);
-+	*pLength += 8;
-+
-+	/* ARP element */
-+	pARPRspPkt += 8;
-+	SET_ARP_HTYPE(pARPRspPkt, 1);
-+	SET_ARP_PTYPE(pARPRspPkt, ETH_P_IP);	/* IP protocol */
-+	SET_ARP_HLEN(pARPRspPkt, ETH_ALEN);
-+	SET_ARP_PLEN(pARPRspPkt, RTW_IP_ADDR_LEN);
-+	SET_ARP_OPER(pARPRspPkt, 2);	/* ARP response */
-+	SET_ARP_SENDER_MAC_ADDR(pARPRspPkt, adapter_mac_addr(padapter));
-+	SET_ARP_SENDER_IP_ADDR(pARPRspPkt, pIPAddress);
-+#ifdef CONFIG_ARP_KEEP_ALIVE
-+	if (!is_zero_mac_addr(pmlmepriv->gw_mac_addr)) {
-+		SET_ARP_TARGET_MAC_ADDR(pARPRspPkt, pmlmepriv->gw_mac_addr);
-+		SET_ARP_TARGET_IP_ADDR(pARPRspPkt, pmlmepriv->gw_ip);
-+	} else
-+#endif
-+	{
-+		SET_ARP_TARGET_MAC_ADDR(pARPRspPkt,
-+				    get_my_bssid(&(pmlmeinfo->network)));
-+		SET_ARP_TARGET_IP_ADDR(pARPRspPkt,
-+					   pIPAddress);
-+		RTW_INFO("%s Target Mac Addr:" MAC_FMT "\n", __FUNCTION__,
-+			 MAC_ARG(get_my_bssid(&(pmlmeinfo->network))));
-+		RTW_INFO("%s Target IP Addr" IP_FMT "\n", __FUNCTION__,
-+			 IP_ARG(pIPAddress));
-+	}
-+
-+	*pLength += 28;
-+
-+	if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
-+		if (IS_HARDWARE_TYPE_8188E(padapter) ||
-+		    IS_HARDWARE_TYPE_8812(padapter)) {
-+			rtw_hal_append_tkip_mic(padapter, pframe, arp_offset);
-+		}
-+		*pLength += 8;
-+	}
-+}
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+/*
-+ * Description:
-+ *	Construct the Keep Alive packet to support specific Keep Alive packet.
-+ *   */
-+static void rtw_hal_construct_keepalive(	PADAPTER padapter,
-+	u8			*pframe,
-+	u32			*pLength
-+){
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	u16	*fctrl;
-+	u32	pktlen;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	static u8	LLCHeader[6] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00};
-+	u8	*pKeepAlivePkt = pframe;
-+	/* for TKIP Cal MIC */
-+	u8	*payload = pframe;
-+	u8	EncryptionHeadOverhead = 0, frame_offset = 0;
-+	int i;
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &pwlanhdr->frame_ctl;
-+	*(fctrl) = 0;
-+
-+	RTW_INFO("%s======>\n", __func__);
-+
-+
-+	/* ------------------------------------------------------------------------- */
-+	/* MAC Header. */
-+	/* ------------------------------------------------------------------------- */
-+	SetFrameType(fctrl, WIFI_DATA);
-+	/* set_frame_sub_type(fctrl, 0); */
-+	SetToDs(fctrl);
-+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, pwrpriv->keep_alive_pattern+6, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3,pwrpriv->keep_alive_pattern, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0);
-+	set_duration(pwlanhdr, 0);
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	*pLength = sMacHdrLng;
-+#else
-+	*pLength = 24;
-+#endif
-+	switch (psecuritypriv->dot11PrivacyAlgrthm) {
-+	case _WEP40_:
-+	case _WEP104_:
-+		EncryptionHeadOverhead = 4;
-+		break;
-+	case _TKIP_:
-+		EncryptionHeadOverhead = 8;
-+		break;
-+	case _AES_:
-+		EncryptionHeadOverhead = 8;
-+		break;
-+#ifdef CONFIG_WAPI_SUPPORT
-+	case _SMS4_:
-+		EncryptionHeadOverhead = 18;
-+		break;
-+#endif
-+	default:
-+		EncryptionHeadOverhead = 0;
-+	}
-+
-+	if (EncryptionHeadOverhead > 0) {
-+		_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
-+		*pLength += EncryptionHeadOverhead;
-+		/* SET_80211_HDR_WEP(pARPRspPkt, 1);  */ /* Suggested by CCW. */
-+		SetPrivacy(fctrl);
-+	}
-+
-+	/* ------------------------------------------------------------------------- */
-+	/* Frame Body. */
-+	/* ------------------------------------------------------------------------- */
-+	frame_offset = *pLength;
-+	pKeepAlivePkt = (u8 *)(pframe + frame_offset);
-+	payload = pKeepAlivePkt; /* Get Payload pointer */
-+	/* LLC header */
-+	_rtw_memcpy(pKeepAlivePkt, LLCHeader, 6);
-+	*pLength += 6;
-+	
-+	/*From  protocol type*/
-+	pKeepAlivePkt+=6;
-+
-+	_rtw_memcpy(pKeepAlivePkt,pwrpriv->keep_alive_pattern+12,pwrpriv->keep_alive_pattern_len-12);
-+
-+	*pLength+=pwrpriv->keep_alive_pattern_len-12;
-+	
-+	if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
-+		*pLength += 8;
-+	}
-+
-+	/* for debug
-+	for (i=0; i< (*pLength) ;i++) {
-+		RTW_INFO("KA_Pkt[0x%x]=x%0x", i,pKeepAlivePkt[i]);
-+		if((i%8) == 7)
-+			RTW_INFO("\n");
-+	}
-+	*/
-+	
-+	RTW_INFO("%s <======\n", __func__);
-+}
-+
-+#endif/*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+
-+#ifdef CONFIG_IPV6
-+/*
-+ * Description: Neighbor Discovery Offload.
-+ */
-+static void rtw_hal_construct_na_message(_adapter *padapter,
-+				     u8 *pframe, u32 *pLength)
-+{
-+	struct rtw_ieee80211_hdr *pwlanhdr = NULL;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &pmlmeext->mlmext_info;
-+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
-+
-+	u32 pktlen = 0;
-+	u16 *fctrl = NULL;
-+
-+	u8 ns_hdr[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x86, 0xDD};
-+	u8 ipv6_info[4] = {0x60, 0x00, 0x00, 0x00};
-+	u8 ipv6_contx[4] = {0x00, 0x20, 0x3a, 0xff};
-+	u8 icmpv6_hdr[8] = {0x88, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00};
-+	u8 val8 = 0;
-+
-+	u8 *p_na_msg = pframe;
-+	/* for TKIP Cal MIC */
-+	u8 *payload = pframe;
-+	u8 EncryptionHeadOverhead = 0, na_msg_offset = 0;
-+	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &pwlanhdr->frame_ctl;
-+	*(fctrl) = 0;
-+
-+	/* ------------------------------------------------------------------------- */
-+	/* MAC Header. */
-+	/* ------------------------------------------------------------------------- */
-+	SetFrameType(fctrl, WIFI_DATA);
-+	SetToDs(fctrl);
-+	_rtw_memcpy(pwlanhdr->addr1,
-+		    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2,
-+		    adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3,
-+		    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0);
-+	set_duration(pwlanhdr, 0);
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	*pLength = sMacHdrLng;
-+#else
-+	*pLength = 24;
-+#endif
-+	switch (psecuritypriv->dot11PrivacyAlgrthm) {
-+	case _WEP40_:
-+	case _WEP104_:
-+		EncryptionHeadOverhead = 4;
-+		break;
-+	case _TKIP_:
-+		EncryptionHeadOverhead = 8;
-+		break;
-+	case _AES_:
-+		EncryptionHeadOverhead = 8;
-+		break;
-+#ifdef CONFIG_WAPI_SUPPORT
-+	case _SMS4_:
-+		EncryptionHeadOverhead = 18;
-+		break;
-+#endif
-+	default:
-+		EncryptionHeadOverhead = 0;
-+	}
-+
-+	if (EncryptionHeadOverhead > 0) {
-+		_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
-+		*pLength += EncryptionHeadOverhead;
-+		/* SET_80211_HDR_WEP(pARPRspPkt, 1);  */ /* Suggested by CCW. */
-+		SetPrivacy(fctrl);
-+	}
-+
-+	/* ------------------------------------------------------------------------- */
-+	/* Frame Body. */
-+	/* ------------------------------------------------------------------------- */
-+	na_msg_offset = *pLength;
-+	p_na_msg = (u8 *)(pframe + na_msg_offset);
-+	payload = p_na_msg; /* Get Payload pointer */
-+
-+	/* LLC header */
-+	val8 = sizeof(ns_hdr);
-+	_rtw_memcpy(p_na_msg, ns_hdr, val8);
-+	*pLength += val8;
-+	p_na_msg += val8;
-+
-+	/* IPv6 Header */
-+	/* 1 . Information (4 bytes): 0x60 0x00 0x00 0x00 */
-+	val8 = sizeof(ipv6_info);
-+	_rtw_memcpy(p_na_msg, ipv6_info, val8);
-+	*pLength += val8;
-+	p_na_msg += val8;
-+
-+	/* 2 . playload : 0x00 0x20 , NextProt : 0x3a (ICMPv6) HopLim : 0xff */
-+	val8 = sizeof(ipv6_contx);
-+	_rtw_memcpy(p_na_msg, ipv6_contx, val8);
-+	*pLength += val8;
-+	p_na_msg += val8;
-+
-+	/* 3 . SA : 16 bytes , DA : 16 bytes ( Fw will filled ) */
-+	_rtw_memset(&(p_na_msg[*pLength]), 0, 32);
-+	*pLength += 32;
-+	p_na_msg += 32;
-+
-+	/* ICMPv6 */
-+	/* 1. Type : 0x88 (NA)
-+	 * 2. Code : 0x00
-+	 * 3. ChechSum : 0x00 0x00 (RSvd)
-+	 * 4. NAFlag: 0x60 0x00 0x00 0x00 ( Solicited , Override)
-+	 */
-+	val8 = sizeof(icmpv6_hdr);
-+	_rtw_memcpy(p_na_msg, icmpv6_hdr, val8);
-+	*pLength += val8;
-+	p_na_msg += val8;
-+
-+	/* TA: 16 bytes*/
-+	_rtw_memset(&(p_na_msg[*pLength]), 0, 16);
-+	*pLength += 16;
-+	p_na_msg += 16;
-+
-+	/* ICMPv6 Target Link Layer Address */
-+	p_na_msg[0] = 0x02; /* type */
-+	p_na_msg[1] = 0x01; /* len 1 unit of 8 octes */
-+	*pLength += 2;
-+	p_na_msg += 2;
-+
-+	_rtw_memset(&(p_na_msg[*pLength]), 0, 6);
-+	*pLength += 6;
-+	p_na_msg += 6;
-+
-+	if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
-+		if (IS_HARDWARE_TYPE_8188E(padapter) ||
-+		    IS_HARDWARE_TYPE_8812(padapter)) {
-+			rtw_hal_append_tkip_mic(padapter, pframe,
-+						na_msg_offset);
-+		}
-+		*pLength += 8;
-+	}
-+}
-+/*
-+ * Description: Neighbor Discovery Protocol Information.
-+ */
-+static void rtw_hal_construct_ndp_info(_adapter *padapter,
-+				     u8 *pframe, u32 *pLength)
-+{
-+	struct mlme_ext_priv *pmlmeext = NULL;
-+	struct mlme_ext_info *pmlmeinfo = NULL;
-+	struct rtw_ndp_info ndp_info;
-+	u8	*pndp_info = pframe;
-+	u8	len = sizeof(struct rtw_ndp_info);
-+
-+	RTW_INFO("%s: len: %d\n", __func__, len);
-+
-+	pmlmeext =  &padapter->mlmeextpriv;
-+	pmlmeinfo = &pmlmeext->mlmext_info;
-+
-+	_rtw_memset(pframe, 0, len);
-+	_rtw_memset(&ndp_info, 0, len);
-+
-+	ndp_info.enable = 1;
-+	ndp_info.check_remote_ip = 0;
-+	ndp_info.num_of_target_ip = 1;
-+
-+	_rtw_memcpy(&ndp_info.target_link_addr, adapter_mac_addr(padapter),
-+		    ETH_ALEN);
-+	_rtw_memcpy(&ndp_info.target_ipv6_addr, pmlmeinfo->ip6_addr,
-+		    RTW_IPv6_ADDR_LEN);
-+
-+	_rtw_memcpy(pndp_info, &ndp_info, len);
-+}
-+#endif /* CONFIG_IPV6 */
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+static void rtw_hal_construct_ProbeReq(_adapter *padapter, u8 *pframe,
-+				       u32 *pLength, pno_ssid_t *ssid)
-+{
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	u16				*fctrl;
-+	u32				pktlen;
-+	unsigned char			*mac;
-+	unsigned char			bssrate[NumRates];
-+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	int	bssrate_len = 0;
-+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+	mac = adapter_mac_addr(padapter);
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN);
-+
-+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0);
-+	set_frame_sub_type(pframe, WIFI_PROBEREQ);
-+
-+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pframe += pktlen;
-+
-+	if (ssid == NULL)
-+		pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &pktlen);
-+	else {
-+		/* RTW_INFO("%s len:%d\n", ssid->SSID, ssid->SSID_len); */
-+		pframe = rtw_set_ie(pframe, _SSID_IE_, ssid->SSID_len, ssid->SSID, &pktlen);
-+	}
-+
-+	get_rate_set(padapter, bssrate, &bssrate_len);
-+
-+	if (bssrate_len > 8) {
-+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &pktlen);
-+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &pktlen);
-+	} else
-+		pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &pktlen);
-+
-+	*pLength = pktlen;
-+}
-+
-+static void rtw_hal_construct_PNO_info(_adapter *padapter,
-+				       u8 *pframe, u32 *pLength)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
-+	int i;
-+
-+	u8	*pPnoInfoPkt = pframe;
-+	pPnoInfoPkt = (u8 *)(pframe + *pLength);
-+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_num, 1);
-+
-+	pPnoInfoPkt += 1;
-+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->hidden_ssid_num, 1);
-+
-+	pPnoInfoPkt += 3;
-+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->fast_scan_period, 1);
-+
-+	pPnoInfoPkt += 4;
-+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->fast_scan_iterations, 4);
-+
-+	pPnoInfoPkt += 4;
-+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->slow_scan_period, 4);
-+
-+	pPnoInfoPkt += 4;
-+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_length, MAX_PNO_LIST_COUNT);
-+
-+	pPnoInfoPkt += MAX_PNO_LIST_COUNT;
-+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_cipher_info, MAX_PNO_LIST_COUNT);
-+
-+	pPnoInfoPkt += MAX_PNO_LIST_COUNT;
-+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->ssid_channel_info, MAX_PNO_LIST_COUNT);
-+
-+	pPnoInfoPkt += MAX_PNO_LIST_COUNT;
-+	_rtw_memcpy(pPnoInfoPkt, &pwrctl->pnlo_info->loc_probe_req, MAX_HIDDEN_AP);
-+
-+	pPnoInfoPkt += MAX_HIDDEN_AP;
-+
-+	/*
-+	SSID is located at 128th Byte in NLO info Page
-+	*/
-+
-+	*pLength += 128;
-+	pPnoInfoPkt = pframe + 128;
-+
-+	for (i = 0; i < pwrctl->pnlo_info->ssid_num ; i++) {
-+		_rtw_memcpy(pPnoInfoPkt, &pwrctl->pno_ssid_list->node[i].SSID,
-+			    pwrctl->pnlo_info->ssid_length[i]);
-+		*pLength += WLAN_SSID_MAXLEN;
-+		pPnoInfoPkt += WLAN_SSID_MAXLEN;
-+	}
-+}
-+
-+static void rtw_hal_construct_ssid_list(_adapter *padapter,
-+					u8 *pframe, u32 *pLength)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
-+	u8 *pSSIDListPkt = pframe;
-+	int i;
-+
-+	pSSIDListPkt = (u8 *)(pframe + *pLength);
-+
-+	for (i = 0; i < pwrctl->pnlo_info->ssid_num ; i++) {
-+		_rtw_memcpy(pSSIDListPkt, &pwrctl->pno_ssid_list->node[i].SSID,
-+			    pwrctl->pnlo_info->ssid_length[i]);
-+
-+		*pLength += WLAN_SSID_MAXLEN;
-+		pSSIDListPkt += WLAN_SSID_MAXLEN;
-+	}
-+}
-+
-+static void rtw_hal_construct_scan_info(_adapter *padapter,
-+					u8 *pframe, u32 *pLength)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
-+	u8 *pScanInfoPkt = pframe;
-+	int i;
-+
-+	pScanInfoPkt = (u8 *)(pframe + *pLength);
-+
-+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->channel_num, 1);
-+
-+	*pLength += 1;
-+	pScanInfoPkt += 1;
-+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_ch, 1);
-+
-+
-+	*pLength += 1;
-+	pScanInfoPkt += 1;
-+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_bw, 1);
-+
-+
-+	*pLength += 1;
-+	pScanInfoPkt += 1;
-+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_40_offset, 1);
-+
-+	*pLength += 1;
-+	pScanInfoPkt += 1;
-+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->orig_80_offset, 1);
-+
-+	*pLength += 1;
-+	pScanInfoPkt += 1;
-+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->periodScan, 1);
-+
-+	*pLength += 1;
-+	pScanInfoPkt += 1;
-+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->period_scan_time, 1);
-+
-+	*pLength += 1;
-+	pScanInfoPkt += 1;
-+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->enableRFE, 1);
-+
-+	*pLength += 1;
-+	pScanInfoPkt += 1;
-+	_rtw_memcpy(pScanInfoPkt, &pwrctl->pscan_info->rfe_type, 8);
-+
-+	*pLength += 8;
-+	pScanInfoPkt += 8;
-+
-+	for (i = 0 ; i < MAX_SCAN_LIST_COUNT ; i++) {
-+		_rtw_memcpy(pScanInfoPkt,
-+			    &pwrctl->pscan_info->ssid_channel_info[i], 4);
-+		*pLength += 4;
-+		pScanInfoPkt += 4;
-+	}
-+}
-+#endif /* CONFIG_PNO_SUPPORT */
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+#ifdef CONFIG_OFFLOAD_MDNS_V4
-+
-+/*
-+ * Description:
-+ *	Construct the MDNS V4 response packet to support MDNS offload.
-+ *
-+ */
-+static void rtw_hal_construct_mdns_rsp_v4(
-+	PADAPTER 	padapter,
-+	u8			*pframe,
-+	u32			*pLength,
-+	u8			*pIPAddress
-+)
-+{
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	u16	*fctrl;
-+	u32	pktlen;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct wlan_network	*cur_network = &pmlmepriv->cur_network;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
-+	static u8	ICMPLLCHeader[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00};
-+	u8	mulicast_ipv4_addr[4] = {0xe0, 0x00, 0x00, 0xfb};
-+	u8	mulicast_mac_addr_for_mdns[6] = {0x01, 0x00, 0x5e, 0x00, 0x00, 0xfb};
-+	u8	*pMdnsRspPkt = pframe;
-+	/* for TKIP Cal MIC */
-+	u8	EncryptionHeadOverhead = 0, mdns_offset = 0;
-+
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &pwlanhdr->frame_ctl;
-+	*(fctrl) = 0;
-+
-+	/* ------------------------------------------------------------------------- */
-+	/* MAC Header. */
-+	/* ------------------------------------------------------------------------- */
-+	SetFrameType(fctrl, WIFI_DATA);
-+	/* set_frame_sub_type(fctrl, 0); */
-+	SetToDs(fctrl);
-+	//_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, mulicast_mac_addr_for_mdns, ETH_ALEN );
-+
-+	SetSeqNum(pwlanhdr, 0);
-+	set_duration(pwlanhdr, 0);
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	*pLength = sMacHdrLng;
-+#else
-+	*pLength = 24;
-+#endif
-+	switch (psecuritypriv->dot11PrivacyAlgrthm) {
-+	case _WEP40_:
-+	case _WEP104_:
-+		EncryptionHeadOverhead = 4;
-+		break;
-+	case _TKIP_:
-+		EncryptionHeadOverhead = 8;
-+		break;
-+	case _AES_:
-+		EncryptionHeadOverhead = 8;
-+		break;
-+#ifdef CONFIG_WAPI_SUPPORT
-+	case _SMS4_:
-+		EncryptionHeadOverhead = 18;
-+		break;
-+#endif
-+	default:
-+		EncryptionHeadOverhead = 0;
-+	}
-+
-+	if (EncryptionHeadOverhead > 0) {
-+		_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
-+		*pLength += EncryptionHeadOverhead;
-+		/* SET_80211_HDR_WEP(pARPRspPkt, 1);  */ /* Suggested by CCW. */
-+		SetPrivacy(fctrl);
-+	}
-+
-+	/* ------------------------------------------------------------------------- */
-+	/* Frame Body. */
-+	/* ------------------------------------------------------------------------- */
-+	mdns_offset = *pLength;
-+	pMdnsRspPkt = (u8 *)(pframe + mdns_offset);
-+	/* LLC header */
-+	_rtw_memcpy(pMdnsRspPkt, ICMPLLCHeader, 8);
-+	*pLength += 8;
-+
-+	/* IP element */
-+	pMdnsRspPkt += 8;
-+	SET_IPHDR_VERSION(pMdnsRspPkt, 0x45);
-+	SET_IPHDR_DSCP(pMdnsRspPkt, 0);
-+	SET_IPHDR_TOTAL_LEN(pMdnsRspPkt, 0);  // filled by fw
-+	SET_IPHDR_IDENTIFIER(pMdnsRspPkt, 0);  // filled by fw
-+	SET_IPHDR_FLAGS(pMdnsRspPkt, 0x40);
-+	SET_IPHDR_FRAG_OFFSET(pMdnsRspPkt, 0);
-+	SET_IPHDR_TTL(pMdnsRspPkt, 0x40);
-+	SET_IPHDR_PROTOCOL(pMdnsRspPkt, 0x11);  // ICMP-UDP
-+	SET_IPHDR_HDR_CHECKSUM(pMdnsRspPkt, 0);  // filled by fw
-+	SET_IPHDR_SRC_IP_ADDR(pMdnsRspPkt, pIPAddress);
-+	SET_IPHDR_DST_IP_ADDR(pMdnsRspPkt, mulicast_ipv4_addr);  // filled by fw
-+
-+	*pLength += 20;
-+
-+	if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
-+		if (IS_HARDWARE_TYPE_8188E(padapter) ||
-+			IS_HARDWARE_TYPE_8812(padapter)) {
-+			rtw_hal_append_tkip_mic(padapter, pframe, mdns_offset);
-+		}
-+		*pLength += 8;
-+	}
-+
-+	/* UDP element */
-+	pMdnsRspPkt += 20;
-+	SET_UDP_SRC_PORT(pMdnsRspPkt, 0xe914); // MDNS
-+	SET_UDP_DST_PORT(pMdnsRspPkt, 0xe914); // MDNS
-+	SET_UDP_LEN(pMdnsRspPkt, 0);      //  filled by fw
-+	SET_UDP_CHECKSUM(pMdnsRspPkt, 0);     // filled by fw
-+	*pLength += 8;
-+
-+	/* MDNS Header */
-+	pMdnsRspPkt += 8;
-+	SET_MDNS_HDR_FLAG(pMdnsRspPkt, 0x84);
-+	*pLength += 12;
-+
-+}
-+
-+#endif /* CONFIG_OFFLOAD_MDNS_V4 */
-+
-+#ifdef CONFIG_OFFLOAD_MDNS_V6
-+
-+/*
-+ * Description:
-+ *	Construct the MDNS response V6 packet to support MDNS offload.
-+ *
-+ */
-+static void rtw_hal_construct_mdns_rsp_v6(
-+	PADAPTER 	padapter,
-+	u8			*pframe,
-+	u32			*pLength,
-+	u8			*pIPAddress
-+)
-+{
-+	struct rtw_ieee80211_hdr        *pwlanhdr;
-+	u16     *fctrl;
-+	u32     pktlen;
-+	struct mlme_priv        *pmlmepriv = &padapter->mlmepriv;
-+	struct wlan_network     *cur_network = &pmlmepriv->cur_network;
-+	struct mlme_ext_priv    *pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct security_priv    *psecuritypriv = &padapter->securitypriv;
-+	static u8       ICMPLLCHeader[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x86, 0xDD};	
-+	u8	mulicast_ipv6_addr[16] = {0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfb};
-+	u8	mulicast_mac_addr_for_mdns[6] = {0x33, 0x33, 0x00, 0x00, 0x00, 0xfb}; /* could be revise by fw */
-+	u8      *pMdnsRspPkt = pframe;
-+	/* for TKIP Cal MIC */
-+	u8      EncryptionHeadOverhead = 0, mdns_offset = 0;
-+	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
-+
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &pwlanhdr->frame_ctl;
-+	*(fctrl) = 0;
-+
-+	/* ------------------------------------------------------------------------- */
-+	/* MAC Header. */
-+	/* ------------------------------------------------------------------------- */
-+	SetFrameType(fctrl, WIFI_DATA);
-+	/* set_frame_sub_type(fctrl, 0); */
-+	SetToDs(fctrl);
-+	//_rtw_memcpy(pwlanhdr->addr1, mulicast_mac_addr_for_mdns, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	//_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, mulicast_mac_addr_for_mdns, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0);
-+	set_duration(pwlanhdr, 0);
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	*pLength = sMacHdrLng;
-+#else
-+	*pLength = 24;
-+#endif
-+	switch (psecuritypriv->dot11PrivacyAlgrthm) {
-+	case _WEP40_:
-+	case _WEP104_:
-+		EncryptionHeadOverhead = 4;
-+		break;
-+	case _TKIP_:
-+		EncryptionHeadOverhead = 8;
-+		break;
-+	case _AES_:
-+		EncryptionHeadOverhead = 8;
-+		break;
-+#ifdef CONFIG_WAPI_SUPPORT
-+	case _SMS4_:
-+		EncryptionHeadOverhead = 18;
-+		break;
-+#endif
-+	default:
-+		EncryptionHeadOverhead = 0;
-+	}
-+
-+	if (EncryptionHeadOverhead > 0) {
-+		_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
-+		*pLength += EncryptionHeadOverhead;
-+		SetPrivacy(fctrl);
-+	}
-+
-+	/* ------------------------------------------------------------------------- */
-+	/* Frame Body. */
-+	/* ------------------------------------------------------------------------- */
-+	mdns_offset = *pLength;
-+	pMdnsRspPkt = (u8 *)(pframe + mdns_offset);
-+	/* LLC header */
-+	_rtw_memcpy(pMdnsRspPkt, ICMPLLCHeader, 8);
-+	*pLength += 8;
-+
-+	/* ICMP element */
-+	pMdnsRspPkt += 8;
-+	SET_IPHDRV6_VERSION(pMdnsRspPkt, 0x06);
-+	SET_IPHDRV6_PAYLOAD_LENGTH(pMdnsRspPkt, 0); // filled by fw
-+	SET_IPHDRV6_NEXT_HEADER(pMdnsRspPkt, 0x3A);
-+	SET_IPHDRV6_HOP_LIMIT(pMdnsRspPkt, 0xFF);
-+	SET_IPHDRV6_SRC_IP_ADDR(pMdnsRspPkt, pIPAddress);  // filled by fw
-+	SET_IPHDRV6_DST_IP_ADDR(pMdnsRspPkt, mulicast_ipv6_addr);  // filled by fw
-+
-+	*pLength += 40;
-+
-+	if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
-+		if (IS_HARDWARE_TYPE_8188E(padapter) ||
-+			IS_HARDWARE_TYPE_8812(padapter)) {
-+				rtw_hal_append_tkip_mic(padapter, pframe, mdns_offset);
-+		}
-+		*pLength += 8;
-+	}
-+
-+	/* UDP element */
-+	pMdnsRspPkt += 40;
-+	SET_UDP_SRC_PORT(pMdnsRspPkt, 0xe914); // SNMP
-+	SET_UDP_DST_PORT(pMdnsRspPkt, 0xe914); // SNMP
-+	SET_UDP_LEN(pMdnsRspPkt, 0);      //  filled by fw
-+	SET_UDP_CHECKSUM(pMdnsRspPkt, 0);     // filled by fw
-+	*pLength += 8;
-+
-+	/* MDNS Header */
-+	pMdnsRspPkt += 8;
-+	SET_MDNS_HDR_FLAG(pMdnsRspPkt, 0x84);
-+	*pLength += 12;
-+
-+}
-+
-+#endif /* CONFIG_OFFLOAD_MDNS_V6 */
-+#endif
-+
-+#ifdef CONFIG_GTK_OL
-+static void rtw_hal_construct_GTKRsp(
-+	PADAPTER	padapter,
-+	u8		*pframe,
-+	u32		*pLength
-+)
-+{
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	u16	*fctrl;
-+	u32	pktlen;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct wlan_network	*cur_network = &pmlmepriv->cur_network;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
-+	static u8	LLCHeader[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x88, 0x8E};
-+	static u8	GTKbody_a[11] = {0x01, 0x03, 0x00, 0x5F, 0x02, 0x03, 0x12, 0x00, 0x10, 0x42, 0x0B};
-+	u8	*pGTKRspPkt = pframe;
-+	u8	EncryptionHeadOverhead = 0;
-+	/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &pwlanhdr->frame_ctl;
-+	*(fctrl) = 0;
-+
-+	/* ------------------------------------------------------------------------- */
-+	/* MAC Header. */
-+	/* ------------------------------------------------------------------------- */
-+	SetFrameType(fctrl, WIFI_DATA);
-+	/* set_frame_sub_type(fctrl, 0); */
-+	SetToDs(fctrl);
-+
-+	_rtw_memcpy(pwlanhdr->addr1,
-+		    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	_rtw_memcpy(pwlanhdr->addr2,
-+		    adapter_mac_addr(padapter), ETH_ALEN);
-+
-+	_rtw_memcpy(pwlanhdr->addr3,
-+		    get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, 0);
-+	set_duration(pwlanhdr, 0);
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	*pLength = sMacHdrLng;
-+#else
-+	*pLength = 24;
-+#endif /* CONFIG_WAPI_SUPPORT */
-+
-+	/* ------------------------------------------------------------------------- */
-+	/* Security Header: leave space for it if necessary. */
-+	/* ------------------------------------------------------------------------- */
-+	switch (psecuritypriv->dot11PrivacyAlgrthm) {
-+	case _WEP40_:
-+	case _WEP104_:
-+		EncryptionHeadOverhead = 4;
-+		break;
-+	case _TKIP_:
-+		EncryptionHeadOverhead = 8;
-+		break;
-+	case _AES_:
-+		EncryptionHeadOverhead = 8;
-+		break;
-+#ifdef CONFIG_WAPI_SUPPORT
-+	case _SMS4_:
-+		EncryptionHeadOverhead = 18;
-+		break;
-+#endif /* CONFIG_WAPI_SUPPORT */
-+	default:
-+		EncryptionHeadOverhead = 0;
-+	}
-+
-+	if (EncryptionHeadOverhead > 0) {
-+		_rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
-+		*pLength += EncryptionHeadOverhead;
-+		/* SET_80211_HDR_WEP(pGTKRspPkt, 1);  */ /* Suggested by CCW. */
-+		/* GTK's privacy bit is done by FW */
-+		/* SetPrivacy(fctrl); */
-+	}
-+	/* ------------------------------------------------------------------------- */
-+	/* Frame Body. */
-+	/* ------------------------------------------------------------------------- */
-+	pGTKRspPkt = (u8 *)(pframe + *pLength);
-+	/* LLC header */
-+	_rtw_memcpy(pGTKRspPkt, LLCHeader, 8);
-+	*pLength += 8;
-+
-+	/* GTK element */
-+	pGTKRspPkt += 8;
-+
-+	/* GTK frame body after LLC, part 1 */
-+	/* TKIP key_length = 32, AES key_length = 16 */
-+	if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_)
-+		GTKbody_a[8] = 0x20;
-+
-+	/* GTK frame body after LLC, part 1 */
-+	_rtw_memcpy(pGTKRspPkt, GTKbody_a, 11);
-+	*pLength += 11;
-+	pGTKRspPkt += 11;
-+	/* GTK frame body after LLC, part 2 */
-+	_rtw_memset(&(pframe[*pLength]), 0, 88);
-+	*pLength += 88;
-+	pGTKRspPkt += 88;
-+
-+	if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_)
-+		*pLength += 8;
-+}
-+#endif /* CONFIG_GTK_OL */
-+
-+#define PN_2_CCMPH(ch,key_id)	((ch) & 0x000000000000ffff) \
-+				| (((ch) & 0x0000ffffffff0000) << 16) \
-+				| (((key_id) << 30)) \
-+				| BIT(29)
-+static void rtw_hal_construct_remote_control_info(_adapter *adapter,
-+						  u8 *pframe, u32 *pLength)
-+{
-+	struct mlme_priv   *pmlmepriv = &adapter->mlmepriv;
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+	struct security_priv *psecuritypriv = &adapter->securitypriv;
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
-+	struct sta_info *psta;
-+	struct stainfo_rxcache *prxcache;
-+	u8 cur_dot11rxiv[8], id = 0, tid_id = 0, i = 0;
-+	size_t sz = 0, total = 0;
-+	u64 ccmp_hdr = 0, tmp_key = 0;
-+
-+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
-+
-+	if (psta == NULL) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	prxcache = &psta->sta_recvpriv.rxcache;
-+	sz = sizeof(cur_dot11rxiv);
-+
-+	/* 3 SEC IV * 1 page */
-+	rtw_get_sec_iv(adapter, cur_dot11rxiv,
-+		       get_my_bssid(&pmlmeinfo->network));
-+
-+	_rtw_memcpy(pframe, cur_dot11rxiv, sz);
-+	*pLength += sz;
-+	pframe += sz;
-+
-+	_rtw_memset(&cur_dot11rxiv, 0, sz);
-+
-+	if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {
-+		id = psecuritypriv->dot118021XGrpKeyid;
-+		tid_id = prxcache->last_tid;
-+		REMOTE_INFO_CTRL_SET_VALD_EN(cur_dot11rxiv, 0xdd);
-+		REMOTE_INFO_CTRL_SET_PTK_EN(cur_dot11rxiv, 1);
-+		REMOTE_INFO_CTRL_SET_GTK_EN(cur_dot11rxiv, 1);
-+		REMOTE_INFO_CTRL_SET_GTK_IDX(cur_dot11rxiv, id);
-+		_rtw_memcpy(pframe, cur_dot11rxiv, sz);
-+		*pLength += sz;
-+		pframe += sz;
-+
-+		_rtw_memcpy(pframe, prxcache->iv[tid_id], sz);
-+		*pLength += sz;
-+		pframe += sz;
-+
-+		total = sizeof(psecuritypriv->iv_seq);
-+		total /= sizeof(psecuritypriv->iv_seq[0]);
-+
-+		for (i = 0 ; i < total ; i ++) {
-+			ccmp_hdr =
-+				le64_to_cpu(*(u64*)psecuritypriv->iv_seq[i]);
-+			_rtw_memset(&cur_dot11rxiv, 0, sz);
-+			if (ccmp_hdr != 0) {
-+				tmp_key = i;
-+				ccmp_hdr = PN_2_CCMPH(ccmp_hdr, tmp_key);
-+				*(u64*)cur_dot11rxiv = cpu_to_le64(ccmp_hdr);
-+				_rtw_memcpy(pframe, cur_dot11rxiv, sz);
-+			}
-+			*pLength += sz;
-+			pframe += sz;
-+		}
-+	}
-+}
-+
-+void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
-+		  u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len,
-+				  RSVDPAGE_LOC *rsvd_page_loc)
-+{
-+	struct security_priv *psecuritypriv = &adapter->securitypriv;
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+	struct mlme_ext_priv	*pmlmeext;
-+	struct mlme_ext_info	*pmlmeinfo;
-+	u32	ARPLength = 0, GTKLength = 0, PNOLength = 0, ScanInfoLength = 0;
-+	u32 ProbeReqLength = 0, ns_len = 0, rc_len = 0;
-+	u8 CurtPktPageNum = 0;
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+	u32 keep_alive_len=0;
-+	int i;
-+#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN */
-+#ifdef CONFIG_WAR_OFFLOAD
-+	u16 tmp_idx = 0;
-+	u32	buf_len = 0;
-+#endif
-+
-+#ifdef CONFIG_GTK_OL
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+	struct sta_info *psta;
-+	struct security_priv *psecpriv = &adapter->securitypriv;
-+	u8 kek[RTW_KEK_LEN];
-+	u8 kck[RTW_KCK_LEN];
-+#endif /* CONFIG_GTK_OL */
-+#ifdef CONFIG_PNO_SUPPORT
-+	int pno_index;
-+	u8 ssid_num;
-+#endif /* CONFIG_PNO_SUPPORT */
-+
-+	pmlmeext = &adapter->mlmeextpriv;
-+	pmlmeinfo = &pmlmeext->mlmext_info;
-+
-+	if (pwrctl->wowlan_pno_enable == _FALSE) {
-+		/* ARP RSP * 1 page */
-+
-+		rsvd_page_loc->LocArpRsp = *page_num;
-+
-+		RTW_INFO("LocArpRsp: %d\n", rsvd_page_loc->LocArpRsp);
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+		if ((0 != pwrctl->wowlan_war_offload_ipv4.ip_addr[0]) &&
-+			(_FALSE == _rtw_memcmp(&pwrctl->wowlan_war_offload_ipv4.ip_addr[0], pmlmeinfo->ip_addr, 4))) {
-+			_rtw_memcpy(pmlmeinfo->ip_addr, &pwrctl->wowlan_war_offload_ipv4.ip_addr[0], 4);
-+			RTW_INFO("Update IP(%d.%d.%d.%d) to arp rsvd page\n", 
-+			pmlmeinfo->ip_addr[0], pmlmeinfo->ip_addr[1],
-+			pmlmeinfo->ip_addr[2], pmlmeinfo->ip_addr[3]);
-+		}
-+#endif /* CONFIG_WAR_OFFLOAD */
-+
-+
-+		rtw_hal_construct_ARPRsp(adapter, &pframe[index],
-+					 &ARPLength, pmlmeinfo->ip_addr);
-+
-+		rtw_hal_fill_fake_txdesc(adapter,
-+					 &pframe[index - tx_desc],
-+					 ARPLength, _FALSE, _FALSE, _TRUE);
-+
-+		CurtPktPageNum = (u8)PageNum(tx_desc + ARPLength, page_size);
-+
-+		*page_num += CurtPktPageNum;
-+
-+		index += (CurtPktPageNum * page_size);
-+		RSVD_PAGE_CFG("WOW-ARPRsp", CurtPktPageNum, *page_num, 0);
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+		/* Keep Alive * ? page*/
-+		if(pwrctl->keep_alive_pattern_len){
-+			rsvd_page_loc->LocKeepAlive = *page_num;
-+			pwrctl->keep_alive_pattern_loc = rsvd_page_loc->LocKeepAlive;
-+			RTW_INFO("pwrctl->keep_alive_pattern_loc: %d\n", pwrctl->keep_alive_pattern_loc);
-+			rtw_hal_construct_keepalive(adapter,&pframe[index],&keep_alive_len);
-+			rtw_hal_fill_fake_txdesc(adapter,
-+					 &pframe[index - tx_desc],
-+					 keep_alive_len, _FALSE, _FALSE, _TRUE);
-+			CurtPktPageNum = (u8)PageNum(tx_desc + keep_alive_len, page_size);
-+			*page_num += CurtPktPageNum;
-+			index += (CurtPktPageNum * page_size);
-+			RSVD_PAGE_CFG("WOW-KeepAlive:", CurtPktPageNum, *page_num, 0);
-+		}
-+#endif /* CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+
-+#ifdef CONFIG_IPV6
-+		/* 2 NS offload and NDP Info*/
-+		if (pwrctl->wowlan_ns_offload_en == _TRUE) {
-+			rsvd_page_loc->LocNbrAdv = *page_num;
-+			RTW_INFO("LocNbrAdv: %d\n", rsvd_page_loc->LocNbrAdv);
-+			rtw_hal_construct_na_message(adapter,
-+						     &pframe[index], &ns_len);
-+			rtw_hal_fill_fake_txdesc(adapter,
-+						 &pframe[index - tx_desc],
-+						 ns_len, _FALSE,
-+						 _FALSE, _TRUE);
-+			CurtPktPageNum = (u8)PageNum(tx_desc + ns_len,
-+						      page_size);
-+			*page_num += CurtPktPageNum;
-+			index += (CurtPktPageNum * page_size);
-+			RSVD_PAGE_CFG("WOW-NbrAdv", CurtPktPageNum, *page_num, 0);
-+
-+			rsvd_page_loc->LocNDPInfo = *page_num;
-+			RTW_INFO("LocNDPInfo: %d\n",
-+				 rsvd_page_loc->LocNDPInfo);
-+
-+			rtw_hal_construct_ndp_info(adapter,
-+						   &pframe[index - tx_desc],
-+						   &ns_len);
-+			CurtPktPageNum =
-+				(u8)PageNum(tx_desc + ns_len, page_size);
-+			*page_num += CurtPktPageNum;
-+			index += (CurtPktPageNum * page_size);
-+			RSVD_PAGE_CFG("WOW-NDPInfo", CurtPktPageNum, *page_num, 0);
-+
-+		}
-+#endif /*CONFIG_IPV6*/
-+		/* 3 Remote Control Info. * 1 page */
-+		rsvd_page_loc->LocRemoteCtrlInfo = *page_num;
-+		RTW_INFO("LocRemoteCtrlInfo: %d\n", rsvd_page_loc->LocRemoteCtrlInfo);
-+		rtw_hal_construct_remote_control_info(adapter,
-+						      &pframe[index - tx_desc],
-+						      &rc_len);
-+		CurtPktPageNum = (u8)PageNum(rc_len, page_size);
-+		*page_num += CurtPktPageNum;
-+		*total_pkt_len = index + rc_len;
-+		RSVD_PAGE_CFG("WOW-RCI", CurtPktPageNum, *page_num, *total_pkt_len);
-+#ifdef CONFIG_GTK_OL
-+		index += (CurtPktPageNum * page_size);
-+
-+		/* if the ap staion info. exists, get the kek, kck from staion info. */
-+		psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
-+		if (psta == NULL) {
-+			_rtw_memset(kek, 0, RTW_KEK_LEN);
-+			_rtw_memset(kck, 0, RTW_KCK_LEN);
-+			RTW_INFO("%s, KEK, KCK download rsvd page all zero\n",
-+				 __func__);
-+		} else {
-+			_rtw_memcpy(kek, psta->kek, RTW_KEK_LEN);
-+			_rtw_memcpy(kck, psta->kck, RTW_KCK_LEN);
-+		}
-+
-+		/* 3 KEK, KCK */
-+		rsvd_page_loc->LocGTKInfo = *page_num;
-+		RTW_INFO("LocGTKInfo: %d\n", rsvd_page_loc->LocGTKInfo);
-+
-+		if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8812(adapter)) {
-+			struct security_priv *psecpriv = NULL;
-+
-+			psecpriv = &adapter->securitypriv;
-+			_rtw_memcpy(pframe + index - tx_desc,
-+				    &psecpriv->dot11PrivacyAlgrthm, 1);
-+			_rtw_memcpy(pframe + index - tx_desc + 1,
-+				    &psecpriv->dot118021XGrpPrivacy, 1);
-+			_rtw_memcpy(pframe + index - tx_desc + 2,
-+				    kck, RTW_KCK_LEN);
-+			_rtw_memcpy(pframe + index - tx_desc + 2 + RTW_KCK_LEN,
-+				    kek, RTW_KEK_LEN);
-+			CurtPktPageNum = (u8)PageNum(tx_desc + 2 + RTW_KCK_LEN + RTW_KEK_LEN, page_size);
-+		} else {
-+
-+			_rtw_memcpy(pframe + index - tx_desc, kck, RTW_KCK_LEN);
-+			_rtw_memcpy(pframe + index - tx_desc + RTW_KCK_LEN,
-+				    kek, RTW_KEK_LEN);
-+			GTKLength = tx_desc + RTW_KCK_LEN + RTW_KEK_LEN;
-+
-+			if (psta != NULL &&
-+				psecuritypriv->dot118021XGrpPrivacy == _TKIP_) {
-+				_rtw_memcpy(pframe + index - tx_desc + 56,
-+					&psta->dot11tkiptxmickey, RTW_TKIP_MIC_LEN);
-+				GTKLength += RTW_TKIP_MIC_LEN;
-+			}
-+			CurtPktPageNum = (u8)PageNum(GTKLength, page_size);
-+		}
-+#if 0
-+		{
-+			int i;
-+			printk("\ntoFW KCK: ");
-+			for (i = 0; i < 16; i++)
-+				printk(" %02x ", kck[i]);
-+			printk("\ntoFW KEK: ");
-+			for (i = 0; i < 16; i++)
-+				printk(" %02x ", kek[i]);
-+			printk("\n");
-+		}
-+
-+		RTW_INFO("%s(): HW_VAR_SET_TX_CMD: KEK KCK %p %d\n",
-+			 __FUNCTION__, &pframe[index - tx_desc],
-+			 (tx_desc + RTW_KCK_LEN + RTW_KEK_LEN));
-+#endif
-+
-+		*page_num += CurtPktPageNum;
-+
-+		index += (CurtPktPageNum * page_size);
-+		RSVD_PAGE_CFG("WOW-GTKInfo", CurtPktPageNum, *page_num, 0);
-+
-+		/* 3 GTK Response */
-+		rsvd_page_loc->LocGTKRsp = *page_num;
-+		RTW_INFO("LocGTKRsp: %d\n", rsvd_page_loc->LocGTKRsp);
-+		rtw_hal_construct_GTKRsp(adapter, &pframe[index], &GTKLength);
-+
-+		rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
-+					 GTKLength, _FALSE, _FALSE, _TRUE);
-+#if 0
-+		{
-+			int gj;
-+			printk("123GTK pkt=>\n");
-+			for (gj = 0; gj < GTKLength + tx_desc; gj++) {
-+				printk(" %02x ", pframe[index - tx_desc + gj]);
-+				if ((gj + 1) % 16 == 0)
-+					printk("\n");
-+			}
-+			printk(" <=end\n");
-+		}
-+
-+		RTW_INFO("%s(): HW_VAR_SET_TX_CMD: GTK RSP %p %d\n",
-+			 __FUNCTION__, &pframe[index - tx_desc],
-+			 (tx_desc + GTKLength));
-+#endif
-+
-+		CurtPktPageNum = (u8)PageNum(tx_desc + GTKLength, page_size);
-+
-+		*page_num += CurtPktPageNum;
-+
-+		index += (CurtPktPageNum * page_size);
-+		RSVD_PAGE_CFG("WOW-GTKRsp", CurtPktPageNum, *page_num, 0);
-+
-+		/* below page is empty for GTK extension memory */
-+		/* 3(11) GTK EXT MEM */
-+		rsvd_page_loc->LocGTKEXTMEM = *page_num;
-+		RTW_INFO("LocGTKEXTMEM: %d\n", rsvd_page_loc->LocGTKEXTMEM);
-+		CurtPktPageNum = 2;
-+
-+		if (page_size >= 256)
-+			CurtPktPageNum = 1;
-+
-+		*page_num += CurtPktPageNum;
-+		/* extension memory for FW */
-+		*total_pkt_len = index + (page_size * CurtPktPageNum);
-+		RSVD_PAGE_CFG("WOW-GTKEXTMEM", CurtPktPageNum, *page_num, *total_pkt_len);
-+#endif /* CONFIG_GTK_OL */
-+
-+		index += (CurtPktPageNum * page_size);
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+		if(_TRUE == pwrctl->wowlan_war_offload_mode) {
-+			u8 zero_ary[16] = {0x00};
-+			u8 war_tmp_cnt = 0;
-+	
-+			/* Reserve 2 page for Ip parameters */
-+			/* First page
-+			   | Byte 15 -----------Byte 0 |
-+			   | IP-4 | IP-3 | IP-2 | IP-1 |
-+			   | location of each feature | mac addr |
-+			   | NetBIOS name			   |
-+			   | location of each feature  |
-+			Second page
-+			   | IPv6 - 1				   |
-+			   | IPv6 - 2				   |
-+			   | IPv6 - 3				   |
-+			   | IPv6 - 4				   |
-+			   | IPv6 - 5				   |
-+			   | IPv6 - 6				   |
-+			   | IPv6 - 7				   |
-+			   | IPv6 - 8				   |
-+			*/
-+	
-+			/* location of each feature : Byte 22 ~ Byte 31
-+			 * Byte22 : location of SNMP RX
-+			 * Byte23 : location of SNMP V4
-+			 * Byte24 : location of SNMP V6
-+			 * Byte25 : location of MDNS Param
-+			 * Byte26 : location of MDNS V4  
-+			 * Byte27 : location of MDNS V6
-+			 * Byte28 : location of SSDP pattern
-+			 * Byte29 : location of WSD pattern  
-+			 * Byte30 : location of SLP pattern
-+			 * Byte31 : location of LLMNR
-+			 */
-+	
-+			/* ipv4 : 4 */
-+			if (0 == pwrctl->wowlan_war_offload_ipv4.ip_addr[0])
-+				_rtw_memcpy(&pwrctl->wowlan_war_offload_ipv4.ip_addr[0], pmlmeinfo->ip_addr, 4);
-+			for(war_tmp_cnt=0; war_tmp_cnt<4 ;war_tmp_cnt++)
-+				_rtw_memcpy(pframe + index - tx_desc + (war_tmp_cnt*4), &pwrctl->wowlan_war_offload_ipv4.ip_addr[war_tmp_cnt], 4);
-+	
-+			if (is_zero_mac_addr(pwrctl->wowlan_war_offload_mac)) {
-+				_rtw_memcpy(pwrctl->wowlan_war_offload_mac, adapter_mac_addr(adapter), 6);
-+			}
-+			_rtw_memcpy(pframe + index + 16 - tx_desc, pwrctl->wowlan_war_offload_mac, 6);
-+	
-+	
-+			/* ipv6 : 8 */
-+			if (_TRUE == _rtw_memcmp(pwrctl->wowlan_war_offload_ipv6.ipv6_addr[0], zero_ary, RTW_IPv6_ADDR_LEN))
-+				_rtw_memcpy(pwrctl->wowlan_war_offload_ipv6.ipv6_addr[0], pmlmeinfo->ip6_addr, RTW_IPv6_ADDR_LEN);
-+	
-+			for(war_tmp_cnt=0; war_tmp_cnt<8 ;war_tmp_cnt++)
-+				_rtw_memcpy(pframe + index + page_size - tx_desc + (war_tmp_cnt*16), pwrctl->wowlan_war_offload_ipv6.ipv6_addr[war_tmp_cnt], 16);
-+	
-+			rsvd_page_loc->LocIpParm = *page_num;
-+	
-+			tmp_idx = index;
-+			CurtPktPageNum = 2;
-+			*page_num += CurtPktPageNum;
-+			*total_pkt_len = index + (page_size * CurtPktPageNum);
-+			index += (CurtPktPageNum * page_size);
-+	
-+		
-+#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
-+			if ( (WAR_MDNS_V4_RSP_EN & pwrctl->wowlan_war_offload_ctrl) || 
-+				 (WAR_MDNS_V6_RSP_EN & pwrctl->wowlan_war_offload_ctrl) || 
-+				 (WAR_MDNS_V4_WAKEUP_EN & pwrctl->wowlan_war_offload_ctrl) || 
-+				 (WAR_MDNS_V6_WAKEUP_EN & pwrctl->wowlan_war_offload_ctrl)) {
-+	
-+				struct war_mdns_service_info *psinfo = pwrctl->wowlan_war_offload_mdns_service;
-+				u8 txt_in_ptr[31]={ 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 
-+									 0x00, 0x13, 0x09, 0x74, 0x78, 0x74, 0x76, 0x65, 0x72, 0x73, 
-+									 0x3d, 0x31, 0x08, 0x71, 0x74, 0x6f, 0x74, 0x61, 0x6c, 0x3d, 0x31};
-+				u16 mdns_offset = index - tx_desc;
-+				u8 i = 0;
-+				
-+				rsvd_page_loc->LocMdnsPara = *page_num;
-+				RTW_INFO("LocMdnsPara : %d\n", rsvd_page_loc->LocMdnsPara);
-+	
-+				/* 1. service info */
-+				pframe[mdns_offset] = 0x01;  // TLV(T)
-+				mdns_offset += 1;
-+				_rtw_memcpy(pframe + mdns_offset, &pwrctl->wowlan_war_offload_mdns_service_info_num, 1);
-+				mdns_offset += 1;
-+	
-+				for(i=0; i<pwrctl->wowlan_war_offload_mdns_service_info_num ;i++)
-+				{
-+					u16 srv_rsp_len = 0;
-+					
-+					// 1.1 : construct service name string
-+					//	   : length of total service name string (service+transport+domain)
-+					pframe[mdns_offset] = psinfo[i].service_len + psinfo[i].transport_len + psinfo[i].domain_len + 4;
-+					mdns_offset += 1;
-+	
-+					//	   :  service name
-+					pframe[mdns_offset] = psinfo[i].service_len;
-+					mdns_offset += 1;
-+					_rtw_memcpy(pframe + mdns_offset, &psinfo[i].service, psinfo[i].service_len);
-+					mdns_offset += psinfo[i].service_len;
-+	
-+					//	   : transport name
-+					pframe[mdns_offset] = psinfo[i].transport_len;
-+					mdns_offset += 1;
-+					_rtw_memcpy(pframe + mdns_offset, &psinfo[i].transport, psinfo[i].transport_len);
-+					mdns_offset += psinfo[i].transport_len;
-+	
-+					//	   : domain name
-+					pframe[mdns_offset] = psinfo[i].domain_len;
-+					mdns_offset += 1;
-+					_rtw_memcpy(pframe + mdns_offset, &psinfo[i].domain, psinfo[i].domain_len);
-+					mdns_offset += psinfo[i].domain_len;
-+	
-+					//	   : delimiter
-+					mdns_offset += 1;
-+	
-+					// 1.2 : construct type srv rsp
-+					pframe[mdns_offset] = psinfo[i].target_len + 19; // length
-+					pframe[mdns_offset + 2] = 0x21; // rsp type (srv)
-+					pframe[mdns_offset + 4] = 0x01; // cache flush + class
-+					_rtw_memcpy(pframe + mdns_offset + 5, &psinfo[i].ttl, 4); // ttl
-+					pframe[mdns_offset + 5] = (u8) ( (psinfo[i].ttl & 0xff000000) >> 24);	// ttl - byte0
-+					pframe[mdns_offset + 6] = (u8) ( (psinfo[i].ttl & 0x00ff0000) >> 16);	// ttl - byte1
-+					pframe[mdns_offset + 7] = (u8) ( (psinfo[i].ttl & 0x0000ff00) >> 8 );		// ttl - byte2
-+					pframe[mdns_offset + 8] = (u8) (psinfo[i].ttl & 0x000000ff);			// ttl - byte3
-+					pframe[mdns_offset + 10] = psinfo[i].target_len + 9;	  // data length
-+					_rtw_memcpy(pframe + mdns_offset + 15, &psinfo[i].port, 2); // port
-+					_rtw_memcpy(pframe + mdns_offset + 17, &psinfo[i].target_len, 1); // target len
-+					_rtw_memcpy(pframe + mdns_offset + 18, &psinfo[i].target, psinfo[i].target_len); // target
-+					pframe[mdns_offset + 18 + psinfo[i].target_len] = 0xc0; // message compresion, offset will be filled by fw.
-+					mdns_offset += (1 + psinfo[i].target_len + 19);
-+	
-+					// 1.3 : set the idx of txt rsp
-+					pframe[mdns_offset] = psinfo[i].txt_rsp_idx;
-+					mdns_offset += 1;
-+				}
-+				
-+				/* 2. machine name */
-+				pframe[mdns_offset] = 0x02; // TLV(T)
-+				mdns_offset += 1;
-+				_rtw_memcpy(pframe + mdns_offset, &pwrctl->wowlan_war_offload_mdns_mnane_num, 1); // NUM
-+				mdns_offset += 1;
-+	
-+				for(i=0; i<pwrctl->wowlan_war_offload_mdns_mnane_num; i++)
-+				{
-+					pframe[mdns_offset] = pwrctl->wowlan_war_offload_mdns_mnane[i].name_len;
-+					_rtw_memcpy(pframe + mdns_offset + 1, pwrctl->wowlan_war_offload_mdns_mnane[i].name, 
-+						pwrctl->wowlan_war_offload_mdns_mnane[i].name_len); // machine name
-+					mdns_offset += (1+pwrctl->wowlan_war_offload_mdns_mnane[i].name_len);
-+				}
-+				
-+				/* 3. A rsp */
-+				pframe[mdns_offset] = 0x03; // TLV(T)
-+				pframe[mdns_offset + 1] = 14;	// TLV(L)
-+				pframe[mdns_offset + 3] = 0x01; // rsp type (a)
-+				pframe[mdns_offset + 5] = 0x01; // cache flush + class
-+				pframe[mdns_offset + 9] = 0xf0; // ttl (240 sec)
-+				pframe[mdns_offset + 11] = 4;	// length of ipv4 addr.
-+				_rtw_memcpy(pframe + mdns_offset + 12, &pwrctl->wowlan_war_offload_ipv4.ip_addr[0], 4);
-+				mdns_offset += (2 + 14);
-+				
-+				/* 4. AAAA rsp */
-+				pframe[mdns_offset] = 0x04; // TLV(T)
-+				pframe[mdns_offset + 1] = 26;	// TLV(L)
-+				pframe[mdns_offset + 3] = 0x1c; // rsp type (aaaa)
-+				pframe[mdns_offset + 5] = 0x01; // cache flush + class
-+				pframe[mdns_offset + 9] = 0xf0; // ttl (240 sec)
-+				pframe[mdns_offset + 11] = 16;	// length of ipv6 addr.
-+				_rtw_memcpy(pframe + mdns_offset + 12, &pwrctl->wowlan_war_offload_ipv6.ipv6_addr[0], 16);
-+				mdns_offset += (2 + 26);
-+				
-+				/* 5. PTR rsp */
-+				pframe[mdns_offset] = 0x05; // TLV(T)
-+				pframe[mdns_offset + 1] = 13 + pwrctl->wowlan_war_offload_mdns_domain_name_len; // TLV(L)
-+				pframe[mdns_offset + 3] = 0x0c; // rsp type (aaaa)
-+				pframe[mdns_offset + 5] = 0x01; // cache flush + class
-+				pframe[mdns_offset + 8] = 0x1c; // ttl 
-+				pframe[mdns_offset + 9] = 0x20; // ttl (7200 sec)
-+				pframe[mdns_offset + 11] = 3 + pwrctl->wowlan_war_offload_mdns_domain_name_len; // data length 
-+				pframe[mdns_offset + 12] = pwrctl->wowlan_war_offload_mdns_domain_name_len; // domain name length 
-+				_rtw_memcpy(pframe + mdns_offset + 13, &pwrctl->wowlan_war_offload_mdns_domain_name, 
-+					pwrctl->wowlan_war_offload_mdns_domain_name_len);
-+				pframe[mdns_offset + 13 + pwrctl->wowlan_war_offload_mdns_domain_name_len] = 0xc0; // message compression
-+				mdns_offset += (2 + 13 + pwrctl->wowlan_war_offload_mdns_domain_name_len);
-+				
-+				/* 6. TXT in PTR rsp */
-+				pframe[mdns_offset] = 0x06; 		// TLV(T)
-+				pframe[mdns_offset + 1] = 31;	// TLV(L)
-+				_rtw_memcpy(pframe + mdns_offset + 2, &txt_in_ptr, 31);
-+				mdns_offset += (2 + 31);
-+				
-+				/* 7. TXT rsp */
-+				pframe[mdns_offset] = 0x07; // TLV(T)
-+				mdns_offset += 1;
-+				_rtw_memcpy(pframe + mdns_offset, &pwrctl->wowlan_war_offload_mdns_txt_rsp_num, 1); // NUM
-+				mdns_offset += 1;
-+	
-+				for(i=0; i<pwrctl->wowlan_war_offload_mdns_txt_rsp_num; i++)
-+				{
-+					u16 txt_rsp_len = pwrctl->wowlan_war_offload_mdns_txt_rsp[i].txt_len;
-+	
-+					if(pwrctl->wowlan_war_offload_mdns_txt_rsp[i].txt_len==0)
-+					{
-+						_rtw_memcpy(pframe + mdns_offset, &txt_rsp_len,  2);
-+						mdns_offset += ( 2 + txt_rsp_len );
-+						continue;
-+					}
-+	
-+					txt_rsp_len += 10;
-+					_rtw_memcpy(pframe + mdns_offset, &txt_rsp_len,  2);
-+					pframe[mdns_offset + 3] = 0x10; // rsp type (txt)
-+					pframe[mdns_offset + 5] = 0x01; // cache flush + class
-+					pframe[mdns_offset + 8] = 0x1c; // ttl 
-+					pframe[mdns_offset + 9] = 0x20; // ttl (7200 sec)
-+					pframe[mdns_offset + 10] = (u8) ((pwrctl->wowlan_war_offload_mdns_txt_rsp[i].txt_len & 0xff00) >> 8);	
-+					pframe[mdns_offset + 11] = (u8) (pwrctl->wowlan_war_offload_mdns_txt_rsp[i].txt_len & 0x00ff);
-+						_rtw_memcpy(pframe + mdns_offset + 12, &pwrctl->wowlan_war_offload_mdns_txt_rsp[i].txt, 
-+							pwrctl->wowlan_war_offload_mdns_txt_rsp[i].txt_len);
-+					mdns_offset  += ( 2 + txt_rsp_len );
-+				}
-+				
-+				CurtPktPageNum = (u8)PageNum(mdns_offset - index, page_size)+1;
-+				*page_num += CurtPktPageNum;
-+				*total_pkt_len = index + (page_size * CurtPktPageNum);
-+				index += (CurtPktPageNum * page_size);
-+			}
-+#endif /* defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) */
-+	
-+#ifdef CONFIG_OFFLOAD_MDNS_V4
-+			if (WAR_MDNS_V4_RSP_EN & pwrctl->wowlan_war_offload_ctrl) {
-+				rsvd_page_loc->LocMdnsv4 = *page_num;
-+				RTW_INFO("LocMdnsv4: %d\n", rsvd_page_loc->LocMdnsv4);
-+				
-+				rtw_hal_construct_mdns_rsp_v4(adapter, &pframe[index], &buf_len, pmlmeinfo->ip_addr);
-+				rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc], buf_len, _FALSE, _FALSE, _TRUE);
-+				CurtPktPageNum = 16;
-+				*page_num += CurtPktPageNum;
-+				index += (CurtPktPageNum * page_size);			
-+			}
-+#endif /* CONFIG_OFFLOAD_MDNS_V4 */
-+	
-+#ifdef CONFIG_OFFLOAD_MDNS_V6
-+			if (WAR_MDNS_V6_RSP_EN & pwrctl->wowlan_war_offload_ctrl) {
-+				rsvd_page_loc->LocMdnsv6 = *page_num;
-+				RTW_INFO("LocMdnsv6: %d\n", rsvd_page_loc->LocMdnsv6);
-+				
-+				rtw_hal_construct_mdns_rsp_v6(adapter, &pframe[index], &buf_len, pmlmeinfo->ip_addr);
-+				rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc], buf_len, _FALSE, _FALSE, _TRUE);
-+				CurtPktPageNum = 16;
-+				*page_num += CurtPktPageNum;
-+				index += (CurtPktPageNum * page_size);			
-+			}
-+#endif /* CONFIG_OFFLOAD_MDNS_V6 */
-+	
-+#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
-+			*(pframe+tmp_idx+25-tx_desc) = rsvd_page_loc->LocMdnsPara;
-+			*(pframe+tmp_idx+26-tx_desc) = rsvd_page_loc->LocMdnsv4;
-+			*(pframe+tmp_idx+27-tx_desc) = rsvd_page_loc->LocMdnsv6;
-+#endif /* defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) */
-+	
-+			}
-+			//rtw_dump_rsvd_page(RTW_DBGDUMP, adapter, rsvd_page_loc->LocIpParm, 46);
-+#endif /* CONFIG_WAR_OFFLOAD */
-+
-+
-+		/*Reserve 1 page for AOAC report*/
-+		rsvd_page_loc->LocAOACReport = *page_num;
-+		RTW_INFO("LocAOACReport: %d\n", rsvd_page_loc->LocAOACReport);
-+		*page_num += 1;
-+		*total_pkt_len = index + (page_size * 1);
-+		RSVD_PAGE_CFG("WOW-AOAC", 1, *page_num, *total_pkt_len);
-+	} else {
-+#ifdef CONFIG_PNO_SUPPORT
-+		if (pwrctl->wowlan_in_resume == _FALSE &&
-+		    pwrctl->pno_inited == _TRUE) {
-+
-+			/* Broadcast Probe Request */
-+			rsvd_page_loc->LocProbePacket = *page_num;
-+
-+			RTW_INFO("loc_probe_req: %d\n",
-+				 rsvd_page_loc->LocProbePacket);
-+
-+			rtw_hal_construct_ProbeReq(
-+				adapter,
-+				&pframe[index],
-+				&ProbeReqLength,
-+				NULL);
-+
-+			rtw_hal_fill_fake_txdesc(adapter,
-+						 &pframe[index - tx_desc],
-+				 ProbeReqLength, _FALSE, _FALSE, _FALSE);
-+
-+			CurtPktPageNum =
-+				(u8)PageNum(tx_desc + ProbeReqLength, page_size);
-+
-+			*page_num += CurtPktPageNum;
-+
-+			index += (CurtPktPageNum * page_size);
-+			RSVD_PAGE_CFG("WOW-ProbeReq", CurtPktPageNum, *page_num, 0);
-+
-+			/* Hidden SSID Probe Request */
-+			ssid_num = pwrctl->pnlo_info->hidden_ssid_num;
-+
-+			for (pno_index = 0 ; pno_index < ssid_num ; pno_index++) {
-+				pwrctl->pnlo_info->loc_probe_req[pno_index] =
-+					*page_num;
-+
-+				rtw_hal_construct_ProbeReq(
-+					adapter,
-+					&pframe[index],
-+					&ProbeReqLength,
-+					&pwrctl->pno_ssid_list->node[pno_index]);
-+
-+				rtw_hal_fill_fake_txdesc(adapter,
-+						 &pframe[index - tx_desc],
-+					ProbeReqLength, _FALSE, _FALSE, _FALSE);
-+
-+				CurtPktPageNum =
-+					(u8)PageNum(tx_desc + ProbeReqLength, page_size);
-+
-+				*page_num += CurtPktPageNum;
-+
-+				index += (CurtPktPageNum * page_size);
-+				RSVD_PAGE_CFG("WOW-ProbeReq", CurtPktPageNum, *page_num, 0);
-+			}
-+
-+			/* PNO INFO Page */
-+			rsvd_page_loc->LocPNOInfo = *page_num;
-+			RTW_INFO("LocPNOInfo: %d\n", rsvd_page_loc->LocPNOInfo);
-+			rtw_hal_construct_PNO_info(adapter,
-+						   &pframe[index - tx_desc],
-+						   &PNOLength);
-+
-+			CurtPktPageNum = (u8)PageNum(PNOLength, page_size);
-+			*page_num += CurtPktPageNum;
-+			index += (CurtPktPageNum * page_size);
-+			RSVD_PAGE_CFG("WOW-PNOInfo", CurtPktPageNum, *page_num, 0);
-+
-+			/* Scan Info Page */
-+			rsvd_page_loc->LocScanInfo = *page_num;
-+			RTW_INFO("LocScanInfo: %d\n", rsvd_page_loc->LocScanInfo);
-+			rtw_hal_construct_scan_info(adapter,
-+						    &pframe[index - tx_desc],
-+						    &ScanInfoLength);
-+
-+			CurtPktPageNum = (u8)PageNum(ScanInfoLength, page_size);
-+			*page_num += CurtPktPageNum;
-+			*total_pkt_len = index + ScanInfoLength;
-+			index += (CurtPktPageNum * page_size);
-+			RSVD_PAGE_CFG("WOW-ScanInfo", CurtPktPageNum, *page_num, *total_pkt_len);
-+		}
-+#endif /* CONFIG_PNO_SUPPORT */
-+	}
-+}
-+
-+static void rtw_hal_gate_bb(_adapter *adapter, bool stop)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	u8 i = 0, val8 = 0, empty = _FAIL;
-+
-+	if (stop) {
-+		/* checking TX queue status */
-+		for (i = 0 ; i < 5 ; i++) {
-+			rtw_hal_get_hwreg(adapter, HW_VAR_CHK_MGQ_CPU_EMPTY, &empty);
-+			if (empty) {
-+				break;
-+			} else {
-+				RTW_WARN("%s: MGQ_CPU is busy(%d)!\n",
-+					 __func__, i);
-+				rtw_mdelay_os(10);
-+			}
-+		}
-+
-+		if (val8 == 5)
-+			RTW_ERR("%s: Polling MGQ_CPU empty fail!\n", __func__);
-+
-+		/* Pause TX*/
-+		pwrpriv->wowlan_txpause_status = rtw_read8(adapter, REG_TXPAUSE);
-+		rtw_write8(adapter, REG_TXPAUSE, 0xff);
-+		val8 = rtw_read8(adapter, REG_SYS_FUNC_EN);
-+		val8 &= ~BIT(0);
-+		rtw_write8(adapter, REG_SYS_FUNC_EN, val8);
-+		RTW_INFO("%s: BB gated: 0x%02x, store TXPAUSE: %02x\n",
-+			 __func__,
-+			 rtw_read8(adapter, REG_SYS_FUNC_EN),
-+			 pwrpriv->wowlan_txpause_status);
-+	} else {
-+		val8 = rtw_read8(adapter, REG_SYS_FUNC_EN);
-+		val8 |= BIT(0);
-+		rtw_write8(adapter, REG_SYS_FUNC_EN, val8);
-+		RTW_INFO("%s: BB release: 0x%02x, recover TXPAUSE:%02x\n",
-+			 __func__, rtw_read8(adapter, REG_SYS_FUNC_EN),
-+			 pwrpriv->wowlan_txpause_status);
-+		/* release TX*/
-+		rtw_write8(adapter, REG_TXPAUSE, pwrpriv->wowlan_txpause_status);
-+	}
-+}
-+
-+static u8 rtw_hal_wow_pattern_generate(_adapter *adapter, u8 idx, struct rtl_wow_pattern *pwow_pattern)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+	 u8 *pattern;
-+	 u8 len = 0;
-+	 u8 *mask;
-+
-+	u8 mask_hw[MAX_WKFM_SIZE] = {0};
-+	u8 content[MAX_WKFM_PATTERN_SIZE] = {0};
-+	u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	u8 multicast_addr1[2] = {0x33, 0x33};
-+	u8 multicast_addr2[3] = {0x01, 0x00, 0x5e};
-+	u8 mask_len = 0;
-+	u8 mac_addr[ETH_ALEN] = {0};
-+	u16 count = 0;
-+	int i;
-+
-+	if (pwrctl->wowlan_pattern_idx > MAX_WKFM_CAM_NUM) {
-+		RTW_INFO("%s pattern_idx is more than MAX_FMC_NUM: %d\n",
-+			 __func__, MAX_WKFM_CAM_NUM);
-+		return _FAIL;
-+	}
-+
-+	pattern = pwrctl->patterns[idx].content;
-+	len = pwrctl->patterns[idx].len;
-+	mask = pwrctl->patterns[idx].mask;
-+
-+	_rtw_memcpy(mac_addr, adapter_mac_addr(adapter), ETH_ALEN);
-+	_rtw_memset(pwow_pattern, 0, sizeof(struct rtl_wow_pattern));
-+
-+	mask_len = DIV_ROUND_UP(len, 8);
-+
-+	/* 1. setup A1 table */
-+	if (memcmp(pattern, broadcast_addr, ETH_ALEN) == 0)
-+		pwow_pattern->type = PATTERN_BROADCAST;
-+	else if (memcmp(pattern, multicast_addr1, 2) == 0)
-+		pwow_pattern->type = PATTERN_MULTICAST;
-+	else if (memcmp(pattern, multicast_addr2, 3) == 0)
-+		pwow_pattern->type = PATTERN_MULTICAST;
-+	else if (memcmp(pattern, mac_addr, ETH_ALEN) == 0)
-+		pwow_pattern->type = PATTERN_UNICAST;
-+	else
-+		pwow_pattern->type = PATTERN_INVALID;
-+
-+	/* translate mask from os to mask for hw */
-+
-+	/******************************************************************************
-+	 * pattern from OS uses 'ethenet frame', like this:
-+
-+		|    6   |    6   |   2  |     20    |  Variable  |  4  |
-+		|--------+--------+------+-----------+------------+-----|
-+		|    802.3 Mac Header    | IP Header | TCP Packet | FCS |
-+		|   DA   |   SA   | Type |
-+
-+	 * BUT, packet catched by our HW is in '802.11 frame', begin from LLC,
-+
-+		|     24 or 30      |    6   |   2  |     20    |  Variable  |  4  |
-+		|-------------------+--------+------+-----------+------------+-----|
-+		| 802.11 MAC Header |       LLC     | IP Header | TCP Packet | FCS |
-+				    | Others | Tpye |
-+
-+	 * Therefore, we need translate mask_from_OS to mask_to_hw.
-+	 * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0,
-+	 * because new mask[0~5] means 'SA', but our HW packet begins from LLC,
-+	 * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match.
-+	 ******************************************************************************/
-+	/* Shift 6 bits */
-+	for (i = 0; i < mask_len - 1; i++) {
-+		mask_hw[i] = mask[i] >> 6;
-+		mask_hw[i] |= (mask[i + 1] & 0x3F) << 2;
-+	}
-+
-+	mask_hw[i] = (mask[i] >> 6) & 0x3F;
-+	/* Set bit 0-5 to zero */
-+	mask_hw[0] &= 0xC0;
-+
-+	for (i = 0; i < (MAX_WKFM_SIZE / 4); i++) {
-+		pwow_pattern->mask[i] = mask_hw[i * 4];
-+		pwow_pattern->mask[i] |= (mask_hw[i * 4 + 1] << 8);
-+		pwow_pattern->mask[i] |= (mask_hw[i * 4 + 2] << 16);
-+		pwow_pattern->mask[i] |= (mask_hw[i * 4 + 3] << 24);
-+	}
-+
-+	/* To get the wake up pattern from the mask.
-+	 * We do not count first 12 bits which means
-+	 * DA[6] and SA[6] in the pattern to match HW design. */
-+	count = 0;
-+	for (i = 12; i < len; i++) {
-+		if ((mask[i / 8] >> (i % 8)) & 0x01) {
-+			content[count] = pattern[i];
-+			count++;
-+		}
-+	}
-+
-+	pwow_pattern->crc = rtw_calc_crc(content, count);
-+
-+	if (pwow_pattern->crc != 0) {
-+		if (pwow_pattern->type == PATTERN_INVALID)
-+			pwow_pattern->type = PATTERN_VALID;
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx)
-+{
-+	int j;
-+
-+	RTW_PRINT_SEL(sel, "=======WOW CAM-ID[%d]=======\n", idx);
-+	RTW_PRINT_SEL(sel, "[WOW CAM] type:%d\n", pwow_pattern->type);
-+	RTW_PRINT_SEL(sel, "[WOW CAM] crc:0x%04x\n", pwow_pattern->crc);
-+	for (j = 0; j < 4; j++)
-+		RTW_PRINT_SEL(sel, "[WOW CAM] Mask:0x%08x\n", pwow_pattern->mask[j]);
-+}
-+/*bit definition of pattern match format*/
-+#define WOW_VALID_BIT	BIT31
-+#ifndef CONFIG_WOW_PATTERN_IN_TXFIFO
-+#define WOW_BC_BIT		BIT26
-+#define WOW_MC_BIT		BIT25
-+#define WOW_UC_BIT		BIT24
-+#else
-+#define WOW_BC_BIT		BIT18
-+#define WOW_UC_BIT		BIT17
-+#define WOW_MC_BIT		BIT16
-+#endif /*CONFIG_WOW_PATTERN_IN_TXFIFO*/
-+
-+#ifndef CONFIG_WOW_PATTERN_HW_CAM
-+#ifndef CONFIG_WOW_PATTERN_IN_TXFIFO
-+static void rtw_hal_reset_mac_rx(_adapter *adapter)
-+{
-+	u8 val8 = 0;
-+	/* Set REG_CR bit1, bit3, bit7 to 0*/
-+	val8 = rtw_read8(adapter, REG_CR);
-+	val8 &= 0x75;
-+	rtw_write8(adapter, REG_CR, val8);
-+	val8 = rtw_read8(adapter, REG_CR);
-+	/* Set REG_CR bit1, bit3, bit7 to 1*/
-+	val8 |= 0x8a;
-+	rtw_write8(adapter, REG_CR, val8);
-+	RTW_INFO("0x%04x: %02x\n", REG_CR, rtw_read8(adapter, REG_CR));
-+}
-+static void rtw_hal_set_wow_rxff_boundary(_adapter *adapter, bool wow_mode)
-+{
-+	u8 val8 = 0;
-+	u16 rxff_bndy = 0;
-+	u32 rx_dma_buff_sz = 0;
-+
-+	val8 = rtw_read8(adapter, REG_FIFOPAGE + 3);
-+	if (val8 != 0)
-+		RTW_INFO("%s:[%04x]some PKTs in TXPKTBUF\n",
-+			 __func__, (REG_FIFOPAGE + 3));
-+
-+	rtw_hal_reset_mac_rx(adapter);
-+
-+	if (wow_mode) {
-+		rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
-+				    (u8 *)&rx_dma_buff_sz);
-+		rxff_bndy = rx_dma_buff_sz - 1;
-+
-+		rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
-+		RTW_INFO("%s: wow mode, 0x%04x: 0x%04x\n", __func__,
-+			 REG_TRXFF_BNDY + 2,
-+			 rtw_read16(adapter, (REG_TRXFF_BNDY + 2)));
-+	} else {
-+		rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ,
-+				    (u8 *)&rx_dma_buff_sz);
-+		rxff_bndy = rx_dma_buff_sz - 1;
-+		rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
-+		RTW_INFO("%s: normal mode, 0x%04x: 0x%04x\n", __func__,
-+			 REG_TRXFF_BNDY + 2,
-+			 rtw_read16(adapter, (REG_TRXFF_BNDY + 2)));
-+	}
-+}
-+#endif /* CONFIG_WOW_PATTERN_IN_TXFIFO*/
-+#ifndef CONFIG_WOW_PATTERN_IN_TXFIFO
-+bool rtw_read_from_frame_mask(_adapter *adapter, u8 idx)
-+{
-+	u32 data_l = 0, data_h = 0, rx_dma_buff_sz = 0, page_sz = 0;
-+	u16 offset, rx_buf_ptr = 0;
-+	u16 cam_start_offset = 0;
-+	u16 ctrl_l = 0, ctrl_h = 0;
-+	u8 count = 0, tmp = 0;
-+	int i = 0;
-+	bool res = _TRUE;
-+
-+	if (idx > MAX_WKFM_CAM_NUM) {
-+		RTW_INFO("[Error]: %s, pattern index is out of range\n",
-+			 __func__);
-+		return _FALSE;
-+	}
-+
-+	rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
-+			    (u8 *)&rx_dma_buff_sz);
-+
-+	if (rx_dma_buff_sz == 0) {
-+		RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__);
-+		return _FALSE;
-+	}
-+
-+	rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz);
-+
-+	if (page_sz == 0) {
-+		RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
-+		return _FALSE;
-+	}
-+
-+	offset = (u16)PageNum(rx_dma_buff_sz, page_sz);
-+	cam_start_offset = offset * page_sz;
-+
-+	ctrl_l = 0x0;
-+	ctrl_h = 0x0;
-+
-+	/* Enable RX packet buffer access */
-+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
-+
-+	/* Read the WKFM CAM */
-+	for (i = 0; i < (WKFMCAM_ADDR_NUM / 2); i++) {
-+		/*
-+		 * Set Rx packet buffer offset.
-+		 * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.
-+		 * CAM start offset (unit: 1 byte) =  Index*WKFMCAM_SIZE
-+		 * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
-+		 * * Index: The index of the wake up frame mask
-+		 * * WKFMCAM_SIZE: the total size of one WKFM CAM
-+		 * * per entry offset of a WKFM CAM: Addr i * 4 bytes
-+		 */
-+		rx_buf_ptr =
-+			(cam_start_offset + idx * WKFMCAM_SIZE + i * 8) >> 3;
-+		rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr);
-+
-+		rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
-+		data_l = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
-+		data_h = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
-+
-+		RTW_INFO("[%d]: %08x %08x\n", i, data_h, data_l);
-+
-+		count = 0;
-+
-+		do {
-+			tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);
-+			rtw_udelay_os(2);
-+			count++;
-+		} while (!tmp && count < 100);
-+
-+		if (count >= 100) {
-+			RTW_INFO("%s count:%d\n", __func__, count);
-+			res = _FALSE;
-+		}
-+	}
-+
-+	/* Disable RX packet buffer access */
-+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,
-+		   DISABLE_TRXPKT_BUF_ACCESS);
-+	return res;
-+}
-+
-+bool rtw_write_to_frame_mask(_adapter *adapter, u8 idx,
-+			     struct  rtl_wow_pattern *context)
-+{
-+	u32 data = 0, rx_dma_buff_sz = 0, page_sz = 0;
-+	u16 offset, rx_buf_ptr = 0;
-+	u16 cam_start_offset = 0;
-+	u16 ctrl_l = 0, ctrl_h = 0;
-+	u8 count = 0, tmp = 0;
-+	int res = 0, i = 0;
-+
-+	if (idx > MAX_WKFM_CAM_NUM) {
-+		RTW_INFO("[Error]: %s, pattern index is out of range\n",
-+			 __func__);
-+		return _FALSE;
-+	}
-+
-+	rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
-+			    (u8 *)&rx_dma_buff_sz);
-+
-+	if (rx_dma_buff_sz == 0) {
-+		RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__);
-+		return _FALSE;
-+	}
-+
-+	rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz);
-+
-+	if (page_sz == 0) {
-+		RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
-+		return _FALSE;
-+	}
-+
-+	offset = (u16)PageNum(rx_dma_buff_sz, page_sz);
-+
-+	cam_start_offset = offset * page_sz;
-+
-+	if (IS_HARDWARE_TYPE_8188E(adapter)) {
-+		ctrl_l = 0x0001;
-+		ctrl_h = 0x0001;
-+	} else {
-+		ctrl_l = 0x0f01;
-+		ctrl_h = 0xf001;
-+	}
-+
-+	/* Enable RX packet buffer access */
-+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
-+
-+	/* Write the WKFM CAM */
-+	for (i = 0; i < WKFMCAM_ADDR_NUM; i++) {
-+		/*
-+		 * Set Rx packet buffer offset.
-+		 * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.
-+		 * CAM start offset (unit: 1 byte) =  Index*WKFMCAM_SIZE
-+		 * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
-+		 * * Index: The index of the wake up frame mask
-+		 * * WKFMCAM_SIZE: the total size of one WKFM CAM
-+		 * * per entry offset of a WKFM CAM: Addr i * 4 bytes
-+		 */
-+		rx_buf_ptr =
-+			(cam_start_offset + idx * WKFMCAM_SIZE + i * 4) >> 3;
-+		rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr);
-+
-+		if (i == 0) {
-+			if (context->type == PATTERN_VALID)
-+				data = WOW_VALID_BIT;
-+			else if (context->type == PATTERN_BROADCAST)
-+				data = WOW_VALID_BIT | WOW_BC_BIT;
-+			else if (context->type == PATTERN_MULTICAST)
-+				data = WOW_VALID_BIT | WOW_MC_BIT;
-+			else if (context->type == PATTERN_UNICAST)
-+				data = WOW_VALID_BIT | WOW_UC_BIT;
-+
-+			if (context->crc != 0)
-+				data |= context->crc;
-+
-+			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data);
-+			rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
-+		} else if (i == 1) {
-+			data = 0;
-+			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data);
-+			rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h);
-+		} else if (i == 2 || i == 4) {
-+			data = context->mask[i - 2];
-+			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data);
-+			/* write to RX packet buffer*/
-+			rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
-+		} else if (i == 3 || i == 5) {
-+			data = context->mask[i - 2];
-+			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data);
-+			/* write to RX packet buffer*/
-+			rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h);
-+		}
-+
-+		count = 0;
-+		do {
-+			tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);
-+			rtw_udelay_os(2);
-+			count++;
-+		} while (tmp && count < 100);
-+
-+		if (count >= 100)
-+			res = _FALSE;
-+		else
-+			res = _TRUE;
-+	}
-+
-+	/* Disable RX packet buffer access */
-+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,
-+		   DISABLE_TRXPKT_BUF_ACCESS);
-+
-+	return res;
-+}
-+#else /* CONFIG_WOW_PATTERN_IN_TXFIFO */
-+bool rtw_read_from_frame_mask(_adapter *adapter, u8 idx)
-+{
-+	u32 data_l = 0, data_h = 0, rx_dma_buff_sz = 0, page_sz = 0;
-+	u16 tx_page_start, tx_buf_ptr = 0;
-+	u16 cam_start_offset = 0;
-+	u16 ctrl_l = 0, ctrl_h = 0;
-+	u8 count = 0, tmp = 0, last_entry = 0;
-+	int i = 0;
-+	bool res = _TRUE;
-+
-+	if (idx > MAX_WKFM_CAM_NUM) {
-+		RTW_INFO("[Error]: %s, pattern index is out of range\n",
-+			 __func__);
-+		return _FALSE;
-+	}
-+
-+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&page_sz);
-+	if (page_sz == 0) {
-+		RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
-+		return _FALSE;
-+	}
-+
-+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_BUFFER_LAST_ENTRY, (u8 *)&last_entry);
-+	if (last_entry == 0) {
-+		RTW_INFO("[Error]: %s, last entry of tx buffer is 0!!\n", __func__);
-+		return _FALSE;
-+	}
-+
-+	/* use the last 2 pages for wow pattern e.g. 0xfe and 0xff */
-+	tx_page_start = last_entry - 1;
-+	cam_start_offset = tx_page_start * page_sz / 8;
-+	ctrl_l = 0x0;
-+	ctrl_h = 0x0;
-+
-+	/* Enable TX packet buffer access */
-+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
-+
-+	/* Read the WKFM CAM */
-+	for (i = 0; i < (WKFMCAM_ADDR_NUM / 2); i++) {
-+		/*
-+		 * Set Tx packet buffer offset.
-+		 * TxBufer pointer increases 1, we can access 8 bytes in Tx packet buffer.
-+		 * CAM start offset (unit: 1 byte) =  Index*WKFMCAM_SIZE
-+		 * TxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
-+		 * * Index: The index of the wake up frame mask
-+		 * * WKFMCAM_SIZE: the total size of one WKFM CAM
-+		 * * per entry offset of a WKFM CAM: Addr i * 4 bytes
-+		 */
-+		tx_buf_ptr =
-+			(cam_start_offset + idx * WKFMCAM_SIZE + i * 8) >> 3;
-+		rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, tx_buf_ptr);
-+		rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
-+		data_l = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
-+		data_h = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
-+
-+		RTW_INFO("[%d]: %08x %08x\n", i, data_h, data_l);
-+
-+		count = 0;
-+
-+		do {
-+			tmp = rtw_read32(adapter, REG_PKTBUF_DBG_CTRL) & BIT23;
-+			rtw_udelay_os(2);
-+			count++;
-+		} while (!tmp && count < 100);
-+
-+		if (count >= 100) {
-+			RTW_INFO("%s count:%d\n", __func__, count);
-+			res = _FALSE;
-+		}
-+	}
-+
-+	/* Disable RX packet buffer access */
-+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,
-+		   DISABLE_TRXPKT_BUF_ACCESS);
-+	return res;
-+}
-+
-+bool rtw_write_to_frame_mask(_adapter *adapter, u8 idx,
-+			     struct  rtl_wow_pattern *context)
-+{
-+	u32 tx_page_start = 0, page_sz = 0;
-+	u16 tx_buf_ptr = 0;
-+	u16 cam_start_offset = 0;
-+	u32 data_l = 0, data_h = 0;
-+	u8 count = 0, tmp = 0, last_entry = 0;
-+	int res = 0, i = 0;
-+
-+	if (idx > MAX_WKFM_CAM_NUM) {
-+		RTW_INFO("[Error]: %s, pattern index is out of range\n",
-+			 __func__);
-+		return _FALSE;
-+	}
-+
-+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&page_sz);
-+	if (page_sz == 0) {
-+		RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
-+		return _FALSE;
-+	}
-+
-+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_BUFFER_LAST_ENTRY, (u8 *)&last_entry);
-+	if (last_entry == 0) {
-+		RTW_INFO("[Error]: %s, last entry of tx buffer is 0!!\n", __func__);
-+		return _FALSE;
-+	}
-+
-+	/* use the last 2 pages for wow pattern e.g. 0xfe and 0xff */
-+	tx_page_start = last_entry - 1;
-+	cam_start_offset = tx_page_start * page_sz / 8;
-+
-+	/* Write the PATTERN location to BIT_TXBUF_WKCAM_OFFSET */
-+	rtw_write8(adapter, REG_TXBUF_WKCAM_OFFSET, cam_start_offset & 0xFF);
-+	rtw_write8(adapter, REG_TXBUF_WKCAM_OFFSET + 1, (cam_start_offset >> 8) & 0xFF);
-+	/* Enable TX packet buffer access */
-+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
-+
-+	/* Write the WKFM CAM */
-+	for (i = 0; i < WKFMCAM_ADDR_NUM / 2; i++) {
-+		/*
-+		 * Set Tx packet buffer offset.
-+		 * TxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.
-+		 * CAM start offset (unit: 1 byte) =  Index*WKFMCAM_SIZE
-+		 * TxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
-+		 * * Index: The index of the wake up frame mask
-+		 * * WKFMCAM_SIZE: the total size of one WKFM CAM
-+		 * * per entry offset of a WKFM CAM: Addr i * 4 bytes
-+		 */
-+		tx_buf_ptr = cam_start_offset + ((idx * WKFMCAM_SIZE + i * 8) >> 3);
-+
-+		if (i == 0) {
-+			if (context->type == PATTERN_VALID)
-+				data_l = WOW_VALID_BIT;
-+			else if (context->type == PATTERN_BROADCAST)
-+				data_l = WOW_VALID_BIT | WOW_BC_BIT;
-+			else if (context->type == PATTERN_MULTICAST)
-+				data_l = WOW_VALID_BIT | WOW_MC_BIT;
-+			else if (context->type == PATTERN_UNICAST)
-+				data_l = WOW_VALID_BIT | WOW_UC_BIT;
-+
-+			if (context->crc != 0)
-+				data_l |= context->crc;
-+
-+			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data_l);
-+		} else {
-+			data_l = context->mask[i * 2 - 2];
-+			data_h = context->mask[i * 2 - 1];
-+			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data_l);
-+			rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data_h);
-+		}
-+
-+		rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, (tx_buf_ptr & 0x1FFF) | BIT23 | (0xff <<24));
-+		count = 0;
-+		do {
-+			tmp = rtw_read32(adapter, REG_PKTBUF_DBG_CTRL) & BIT23;
-+			rtw_udelay_os(2);
-+			count++;
-+		} while (tmp && count < 100);
-+
-+		if (count >= 100) {
-+			res = _FALSE;
-+			RTW_INFO("%s write failed\n", __func__);
-+		} else {
-+			res = _TRUE;
-+			RTW_INFO("%s write OK\n", __func__);
-+		}
-+	}
-+
-+	/* Disable TX packet buffer access */
-+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, DISABLE_TRXPKT_BUF_ACCESS);
-+	return res;
-+}
-+#endif /* CONFIG_WOW_PATTERN_IN_TXFIFO */
-+
-+void rtw_clean_pattern(_adapter *adapter)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+	struct rtl_wow_pattern zero_pattern;
-+	int i = 0;
-+
-+	_rtw_memset(&zero_pattern, 0, sizeof(struct rtl_wow_pattern));
-+
-+	zero_pattern.type = PATTERN_INVALID;
-+
-+	for (i = 0; i < MAX_WKFM_CAM_NUM; i++)
-+		rtw_write_to_frame_mask(adapter, i, &zero_pattern);
-+
-+	rtw_write8(adapter, REG_WKFMCAM_NUM, 0);
-+}
-+#if 0
-+static int rtw_hal_set_pattern(_adapter *adapter, u8 *pattern,
-+			       u8 len, u8 *mask, u8 idx)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+	struct mlme_ext_priv *pmlmeext = NULL;
-+	struct mlme_ext_info *pmlmeinfo = NULL;
-+	struct rtl_wow_pattern wow_pattern;
-+	u8 mask_hw[MAX_WKFM_SIZE] = {0};
-+	u8 content[MAX_WKFM_PATTERN_SIZE] = {0};
-+	u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	u8 multicast_addr1[2] = {0x33, 0x33};
-+	u8 multicast_addr2[3] = {0x01, 0x00, 0x5e};
-+	u8 res = _FALSE, index = 0, mask_len = 0;
-+	u8 mac_addr[ETH_ALEN] = {0};
-+	u16 count = 0;
-+	int i, j;
-+
-+	if (pwrctl->wowlan_pattern_idx > MAX_WKFM_CAM_NUM) {
-+		RTW_INFO("%s pattern_idx is more than MAX_FMC_NUM: %d\n",
-+			 __func__, MAX_WKFM_CAM_NUM);
-+		return _FALSE;
-+	}
-+
-+	pmlmeext = &adapter->mlmeextpriv;
-+	pmlmeinfo = &pmlmeext->mlmext_info;
-+	_rtw_memcpy(mac_addr, adapter_mac_addr(adapter), ETH_ALEN);
-+	_rtw_memset(&wow_pattern, 0, sizeof(struct rtl_wow_pattern));
-+
-+	mask_len = DIV_ROUND_UP(len, 8);
-+
-+	/* 1. setup A1 table */
-+	if (memcmp(pattern, broadcast_addr, ETH_ALEN) == 0)
-+		wow_pattern.type = PATTERN_BROADCAST;
-+	else if (memcmp(pattern, multicast_addr1, 2) == 0)
-+		wow_pattern.type = PATTERN_MULTICAST;
-+	else if (memcmp(pattern, multicast_addr2, 3) == 0)
-+		wow_pattern.type = PATTERN_MULTICAST;
-+	else if (memcmp(pattern, mac_addr, ETH_ALEN) == 0)
-+		wow_pattern.type = PATTERN_UNICAST;
-+	else
-+		wow_pattern.type = PATTERN_INVALID;
-+
-+	/* translate mask from os to mask for hw */
-+
-+/******************************************************************************
-+ * pattern from OS uses 'ethenet frame', like this:
-+
-+	|    6   |    6   |   2  |     20    |  Variable  |  4  |
-+	|--------+--------+------+-----------+------------+-----|
-+	|    802.3 Mac Header    | IP Header | TCP Packet | FCS |
-+	|   DA   |   SA   | Type |
-+
-+ * BUT, packet catched by our HW is in '802.11 frame', begin from LLC,
-+
-+	|     24 or 30      |    6   |   2  |     20    |  Variable  |  4  |
-+	|-------------------+--------+------+-----------+------------+-----|
-+	| 802.11 MAC Header |       LLC     | IP Header | TCP Packet | FCS |
-+			    | Others | Tpye |
-+
-+ * Therefore, we need translate mask_from_OS to mask_to_hw.
-+ * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0,
-+ * because new mask[0~5] means 'SA', but our HW packet begins from LLC,
-+ * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match.
-+ ******************************************************************************/
-+	/* Shift 6 bits */
-+	for (i = 0; i < mask_len - 1; i++) {
-+		mask_hw[i] = mask[i] >> 6;
-+		mask_hw[i] |= (mask[i + 1] & 0x3F) << 2;
-+	}
-+
-+	mask_hw[i] = (mask[i] >> 6) & 0x3F;
-+	/* Set bit 0-5 to zero */
-+	mask_hw[0] &= 0xC0;
-+
-+	for (i = 0; i < (MAX_WKFM_SIZE / 4); i++) {
-+		wow_pattern.mask[i] = mask_hw[i * 4];
-+		wow_pattern.mask[i] |= (mask_hw[i * 4 + 1] << 8);
-+		wow_pattern.mask[i] |= (mask_hw[i * 4 + 2] << 16);
-+		wow_pattern.mask[i] |= (mask_hw[i * 4 + 3] << 24);
-+	}
-+
-+	/* To get the wake up pattern from the mask.
-+	 * We do not count first 12 bits which means
-+	 * DA[6] and SA[6] in the pattern to match HW design. */
-+	count = 0;
-+	for (i = 12; i < len; i++) {
-+		if ((mask[i / 8] >> (i % 8)) & 0x01) {
-+			content[count] = pattern[i];
-+			count++;
-+		}
-+	}
-+
-+	wow_pattern.crc = rtw_calc_crc(content, count);
-+
-+	if (wow_pattern.crc != 0) {
-+		if (wow_pattern.type == PATTERN_INVALID)
-+			wow_pattern.type = PATTERN_VALID;
-+	}
-+
-+	index = idx;
-+
-+	if (!pwrctl->bInSuspend)
-+		index += 2;
-+
-+	/* write pattern */
-+	res = rtw_write_to_frame_mask(adapter, index, &wow_pattern);
-+
-+	if (res == _FALSE)
-+		RTW_INFO("%s: ERROR!! idx: %d write_to_frame_mask_cam fail\n",
-+			 __func__, idx);
-+
-+	return res;
-+}
-+#endif
-+
-+void rtw_fill_pattern(_adapter *adapter)
-+{
-+	int i = 0, total = 0, index;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	struct rtl_wow_pattern wow_pattern;
-+
-+	total = pwrpriv->wowlan_pattern_idx;
-+
-+	if (total > MAX_WKFM_CAM_NUM)
-+		total = MAX_WKFM_CAM_NUM;
-+
-+	for (i = 0 ; i < total ; i++) {
-+		if (_SUCCESS == rtw_hal_wow_pattern_generate(adapter, i, &wow_pattern)) {
-+
-+			index = i;
-+			if (!pwrpriv->bInSuspend)
-+				index += 2;
-+			rtw_dump_wow_pattern(RTW_DBGDUMP, &wow_pattern, i);
-+			if (rtw_write_to_frame_mask(adapter, index, &wow_pattern) == _FALSE)
-+				RTW_INFO("%s: ERROR!! idx: %d write_to_frame_mask_cam fail\n", __func__, i);
-+		}
-+
-+	}
-+	rtw_write8(adapter, REG_WKFMCAM_NUM, total);
-+
-+}
-+
-+#else /*CONFIG_WOW_PATTERN_HW_CAM*/
-+
-+#define WOW_CAM_ACCESS_TIMEOUT_MS	200
-+static u32 _rtw_wow_pattern_read_cam(_adapter *adapter, u8 addr)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	_mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
-+
-+	u32 rdata = 0;
-+	u32 cnt = 0;
-+	systime start = 0;
-+	u8 timeout = 0;
-+	u8 rst = _FALSE;
-+
-+	_enter_critical_mutex(mutex, NULL);
-+
-+	rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_ADDR_V2(addr));
-+
-+	start = rtw_get_current_time();
-+	while (1) {
-+		if (rtw_is_surprise_removed(adapter))
-+			break;
-+
-+		cnt++;
-+		if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) {
-+			rst = _SUCCESS;
-+			break;
-+		}
-+		if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
-+			timeout = 1;
-+			break;
-+		}
-+	}
-+
-+	rdata = rtw_read32(adapter, REG_WKFMCAM_RWD);
-+
-+	_exit_critical_mutex(mutex, NULL);
-+
-+	/*RTW_INFO("%s ==> addr:0x%02x , rdata:0x%08x\n", __func__, addr, rdata);*/
-+
-+	if (timeout)
-+		RTW_ERR(FUNC_ADPT_FMT" failed due to polling timeout\n", FUNC_ADPT_ARG(adapter));
-+
-+	return rdata;
-+}
-+void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct  rtl_wow_pattern *context)
-+{
-+	int i;
-+	u32 rdata;
-+
-+	_rtw_memset(context, 0, sizeof(struct  rtl_wow_pattern));
-+
-+	for (i = 4; i >= 0; i--) {
-+		rdata = _rtw_wow_pattern_read_cam(adapter, (id << 3) | i);
-+
-+		switch (i) {
-+		case 4:
-+			if (rdata & WOW_BC_BIT)
-+				context->type = PATTERN_BROADCAST;
-+			else if (rdata & WOW_MC_BIT)
-+				context->type = PATTERN_MULTICAST;
-+			else if (rdata & WOW_UC_BIT)
-+				context->type = PATTERN_UNICAST;
-+			else
-+				context->type = PATTERN_INVALID;
-+
-+			context->crc = rdata & 0xFFFF;
-+			break;
-+		default:
-+			_rtw_memcpy(&context->mask[i], (u8 *)(&rdata), 4);
-+			break;
-+		}
-+	}
-+}
-+
-+static void _rtw_wow_pattern_write_cam(_adapter *adapter, u8 addr, u32 wdata)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	_mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
-+	u32 cnt = 0;
-+	systime start = 0, end = 0;
-+	u8 timeout = 0;
-+
-+	/*RTW_INFO("%s ==> addr:0x%02x , wdata:0x%08x\n", __func__, addr, wdata);*/
-+	_enter_critical_mutex(mutex, NULL);
-+
-+	rtw_write32(adapter, REG_WKFMCAM_RWD, wdata);
-+	rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_WE | BIT_WKFCAM_ADDR_V2(addr));
-+
-+	start = rtw_get_current_time();
-+	while (1) {
-+		if (rtw_is_surprise_removed(adapter))
-+			break;
-+
-+		cnt++;
-+		if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1))
-+			break;
-+
-+		if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
-+			timeout = 1;
-+			break;
-+		}
-+	}
-+	end = rtw_get_current_time();
-+
-+	_exit_critical_mutex(mutex, NULL);
-+
-+	if (timeout) {
-+		RTW_ERR(FUNC_ADPT_FMT" addr:0x%02x, wdata:0x%08x, to:%u, polling:%u, %d ms\n"
-+			, FUNC_ADPT_ARG(adapter), addr, wdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
-+	}
-+}
-+
-+void rtw_wow_pattern_write_cam_ent(_adapter *adapter, u8 id, struct  rtl_wow_pattern *context)
-+{
-+	int j;
-+	u8 addr;
-+	u32 wdata = 0;
-+
-+	for (j = 4; j >= 0; j--) {
-+		switch (j) {
-+		case 4:
-+			wdata = context->crc;
-+
-+			if (PATTERN_BROADCAST == context->type)
-+				wdata |= WOW_BC_BIT;
-+			if (PATTERN_MULTICAST == context->type)
-+				wdata |= WOW_MC_BIT;
-+			if (PATTERN_UNICAST == context->type)
-+				wdata |= WOW_UC_BIT;
-+			if (PATTERN_INVALID != context->type)
-+				wdata |= WOW_VALID_BIT;
-+			break;
-+		default:
-+			wdata = context->mask[j];
-+			break;
-+		}
-+
-+		addr = (id << 3) + j;
-+
-+		_rtw_wow_pattern_write_cam(adapter, addr, wdata);
-+	}
-+}
-+
-+static u8 _rtw_wow_pattern_clean_cam(_adapter *adapter)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	_mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
-+	u32 cnt = 0;
-+	systime start = 0;
-+	u8 timeout = 0;
-+	u8 rst = _FAIL;
-+
-+	_enter_critical_mutex(mutex, NULL);
-+	rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_CLR_V1);
-+
-+	start = rtw_get_current_time();
-+	while (1) {
-+		if (rtw_is_surprise_removed(adapter))
-+			break;
-+
-+		cnt++;
-+		if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) {
-+			rst = _SUCCESS;
-+			break;
-+		}
-+		if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
-+			timeout = 1;
-+			break;
-+		}
-+	}
-+	_exit_critical_mutex(mutex, NULL);
-+
-+	if (timeout)
-+		RTW_ERR(FUNC_ADPT_FMT" falied ,polling timeout\n", FUNC_ADPT_ARG(adapter));
-+
-+	return rst;
-+}
-+
-+void rtw_clean_pattern(_adapter *adapter)
-+{
-+	if (_FAIL == _rtw_wow_pattern_clean_cam(adapter))
-+		RTW_ERR("rtw_clean_pattern failed\n");
-+}
-+void rtw_fill_pattern(_adapter *adapter)
-+{
-+	int i = 0, total = 0;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	struct rtl_wow_pattern wow_pattern;
-+
-+	total = pwrpriv->wowlan_pattern_idx;
-+
-+	if (total > MAX_WKFM_CAM_NUM)
-+		total = MAX_WKFM_CAM_NUM;
-+
-+	for (i = 0 ; i < total ; i++) {
-+		if (_SUCCESS == rtw_hal_wow_pattern_generate(adapter, i, &wow_pattern)) {
-+			rtw_dump_wow_pattern(RTW_DBGDUMP, &wow_pattern, i);
-+			rtw_wow_pattern_write_cam_ent(adapter, i, &wow_pattern);
-+		}
-+	}
-+}
-+
-+#endif
-+void rtw_wow_pattern_cam_dump(_adapter *adapter)
-+{
-+
-+#ifndef CONFIG_WOW_PATTERN_HW_CAM
-+	int i;
-+
-+	for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {
-+		RTW_INFO("=======[%d]=======\n", i);
-+		rtw_read_from_frame_mask(adapter, i);
-+	}
-+#else
-+	struct  rtl_wow_pattern context;
-+	int i;
-+
-+	for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {
-+		rtw_wow_pattern_read_cam_ent(adapter, i, &context);
-+		rtw_dump_wow_pattern(RTW_DBGDUMP, &context, i);
-+	}
-+
-+#endif
-+}
-+
-+
-+static void rtw_hal_dl_pattern(_adapter *adapter, u8 mode)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+
-+	switch (mode) {
-+	case 0:
-+		rtw_clean_pattern(adapter);
-+		RTW_INFO("%s: total patterns: %d\n", __func__, pwrpriv->wowlan_pattern_idx);
-+		break;
-+	case 1:
-+		rtw_set_default_pattern(adapter);
-+		rtw_fill_pattern(adapter);
-+		RTW_INFO("%s: pattern total: %d downloaded\n", __func__, pwrpriv->wowlan_pattern_idx);
-+		break;
-+	case 2:
-+		rtw_clean_pattern(adapter);
-+		rtw_wow_pattern_sw_reset(adapter);
-+		RTW_INFO("%s: clean patterns\n", __func__);
-+		break;
-+	default:
-+		RTW_INFO("%s: unknown mode\n", __func__);
-+		break;
-+	}
-+}
-+
-+static void rtw_hal_wow_enable(_adapter *adapter)
-+{
-+	struct registry_priv  *registry_par = &adapter->registrypriv;
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+	struct security_priv *psecuritypriv = &adapter->securitypriv;
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct sta_info *psta = NULL;
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
-+	int res;
-+	u16 media_status_rpt;
-+	u8 no_wake = 0, i;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	_adapter *iface;
-+#ifdef CONFIG_GPIO_WAKEUP
-+	u8 val8 = 0;
-+#endif
-+
-+#ifdef CONFIG_LPS_PG
-+	u8 lps_pg_hdl_id = 0;
-+#endif
-+
-+
-+
-+	if(registry_par->suspend_type == FW_IPS_DISABLE_BBRF &&
-+	!check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
-+		no_wake = 1;
-+
-+	RTW_PRINT(FUNC_ADPT_FMT " WOWLAN_ENABLE\n", FUNC_ADPT_ARG(adapter));
-+	rtw_hal_gate_bb(adapter, _TRUE);
-+	
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		/* Start Usb TxDMA */
-+		if(iface) {
-+			RTW_INFO(ADPT_FMT "enable TX\n", ADPT_ARG(iface));
-+			RTW_ENABLE_FUNC(iface, DF_TX_BIT);
-+		}
-+	}
-+	
-+#ifdef CONFIG_GTK_OL
-+	if (psecuritypriv->binstallKCK_KEK == _TRUE)
-+		rtw_hal_fw_sync_cam_id(adapter);
-+#endif
-+	if (IS_HARDWARE_TYPE_8723B(adapter))
-+		rtw_hal_backup_rate(adapter);
-+
-+	rtw_hal_fw_dl(adapter, _TRUE);
-+	if(no_wake)
-+		media_status_rpt = RT_MEDIA_DISCONNECT;
-+	else
-+		media_status_rpt = RT_MEDIA_CONNECT;
-+	rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
-+			  (u8 *)&media_status_rpt);
-+
-+	/* RX DMA stop */
-+	#if defined(CONFIG_RTL8188E)
-+	if (IS_HARDWARE_TYPE_8188E(adapter))
-+		rtw_hal_disable_tx_report(adapter);
-+	#endif
-+
-+	res = rtw_hal_pause_rx_dma(adapter);
-+	if (res == _FAIL)
-+		RTW_PRINT("[WARNING] pause RX DMA fail\n");
-+
-+	#ifndef CONFIG_WOW_PATTERN_HW_CAM
-+	/* Reconfig RX_FF Boundary */
-+	#ifndef CONFIG_WOW_PATTERN_IN_TXFIFO
-+	rtw_hal_set_wow_rxff_boundary(adapter, _TRUE);
-+	#endif /*CONFIG_WOW_PATTERN_IN_TXFIFO*/
-+	#endif
-+
-+	/* redownload wow pattern */
-+	if(!no_wake)
-+		rtw_hal_dl_pattern(adapter, 1);
-+
-+	if (!pwrctl->wowlan_pno_enable) {
-+		psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
-+
-+		if (psta != NULL) {
-+			#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+			adapter_to_dvobj(adapter)->dft.port_id = 0xFF;
-+			adapter_to_dvobj(adapter)->dft.mac_id = 0xFF;
-+			rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);
-+			#endif
-+			if(!no_wake)
-+				rtw_sta_media_status_rpt(adapter, psta, 1);
-+		}
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+		else {
-+			if(registry_par->suspend_type == FW_IPS_WRC) {
-+				adapter_to_dvobj(adapter)->dft.port_id = 0xFF;
-+				adapter_to_dvobj(adapter)->dft.mac_id = 0xFF;
-+				rtw_hal_set_default_port_id_cmd(adapter, 0);
-+			}
-+		}
-+#endif /* CONFIG_FW_MULTI_PORT_SUPPORT */
-+	}
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	/* Enable CPWM2 only. */
-+	res = rtw_hal_enable_cpwm2(adapter);
-+	if (res == _FAIL)
-+		RTW_PRINT("[WARNING] enable cpwm2 fail\n");
-+#endif
-+#ifdef CONFIG_GPIO_WAKEUP
-+#ifdef CONFIG_RTW_ONE_PIN_GPIO
-+	rtw_hal_switch_gpio_wl_ctrl(adapter, pwrctl->wowlan_gpio_index, _TRUE);
-+	rtw_hal_set_input_gpio(adapter, pwrctl->wowlan_gpio_index);
-+#else
-+#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
-+	if (pwrctl->is_high_active == 0)
-+		rtw_hal_set_input_gpio(adapter, pwrctl->wowlan_gpio_index);
-+	else
-+		rtw_hal_set_output_gpio(adapter, pwrctl->wowlan_gpio_index,
-+			GPIO_OUTPUT_LOW);
-+#else
-+	val8 = (pwrctl->is_high_active == 0) ? 1 : 0;
-+	rtw_hal_set_output_gpio(adapter, pwrctl->wowlan_gpio_index, val8);
-+	rtw_hal_switch_gpio_wl_ctrl(adapter, pwrctl->wowlan_gpio_index, _TRUE);
-+	RTW_INFO("%s: set GPIO_%d to OUTPUT %s state in wow suspend and %s_ACTIVE.\n",
-+		 __func__, pwrctl->wowlan_gpio_index, 
-+		 pwrctl->wowlan_gpio_output_state ? "HIGH" : "LOW",
-+		 pwrctl->is_high_active ? "HIGI" : "LOW");
-+#endif /* CONFIG_WAKEUP_GPIO_INPUT_MODE */
-+#endif /* CONFIG_RTW_ONE_PIN_GPIO */
-+#endif /* CONFIG_GPIO_WAKEUP */
-+	/* Set WOWLAN H2C command. */
-+	RTW_PRINT("Set WOWLan cmd\n");
-+	rtw_hal_set_fw_wow_related_cmd(adapter, 1);
-+
-+	res = rtw_hal_check_wow_ctrl(adapter, _TRUE);
-+
-+	if (res == _FALSE)
-+		RTW_INFO("[Error]%s: set wowlan CMD fail!!\n", __func__);
-+
-+	pwrctl->wowlan_wake_reason =
-+		rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
-+
-+	RTW_PRINT("wowlan_wake_reason: 0x%02x\n",
-+		  pwrctl->wowlan_wake_reason);
-+#ifdef CONFIG_GTK_OL_DBG
-+	dump_sec_cam(RTW_DBGDUMP, adapter);
-+	dump_sec_cam_cache(RTW_DBGDUMP, adapter);
-+#endif
-+
-+#ifdef CONFIG_LPS_PG
-+	if (pwrctl->lps_level == LPS_PG) {
-+		lps_pg_hdl_id = LPS_PG_INFO_CFG;
-+		rtw_hal_set_hwreg(adapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
-+	}
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	/* free adapter's resource */
-+	rtw_mi_intf_stop(adapter);
-+
-+#endif
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
-+	/* Invoid SE0 reset signal during suspending*/
-+	rtw_write8(adapter, REG_RSV_CTRL, 0x20);
-+	if (IS_8188F(pHalData->version_id) == FALSE
-+		&& IS_8188GTV(pHalData->version_id) == FALSE)
-+		rtw_write8(adapter, REG_RSV_CTRL, 0x60);
-+#endif
-+
-+	rtw_hal_gate_bb(adapter, _FALSE);
-+}
-+
-+#define DBG_WAKEUP_REASON
-+#ifdef DBG_WAKEUP_REASON
-+void _dbg_wake_up_reason_string(_adapter *adapter, const char *srt_res)
-+{
-+	RTW_INFO(ADPT_FMT "- wake up reason - %s\n", ADPT_ARG(adapter), srt_res);
-+}
-+void _dbg_rtw_wake_up_reason(_adapter *adapter, u8 reason)
-+{
-+	if (RX_PAIRWISEKEY == reason)
-+		_dbg_wake_up_reason_string(adapter, "Rx pairwise key");
-+	else if (RX_GTK == reason)
-+		_dbg_wake_up_reason_string(adapter, "Rx GTK");
-+	else if (RX_FOURWAY_HANDSHAKE == reason)
-+		_dbg_wake_up_reason_string(adapter, "Rx four way handshake");
-+	else if (RX_DISASSOC == reason)
-+		_dbg_wake_up_reason_string(adapter, "Rx disassoc");
-+	else if (RX_DEAUTH == reason)
-+		_dbg_wake_up_reason_string(adapter, "Rx deauth");
-+	else if (RX_ARP_REQUEST == reason)
-+		_dbg_wake_up_reason_string(adapter, "Rx ARP request");
-+	else if (FW_DECISION_DISCONNECT == reason)
-+		_dbg_wake_up_reason_string(adapter, "FW detect disconnect");
-+	else if (RX_MAGIC_PKT == reason)
-+		_dbg_wake_up_reason_string(adapter, "Rx magic packet");
-+	else if (RX_UNICAST_PKT == reason)
-+		_dbg_wake_up_reason_string(adapter, "Rx unicast packet");
-+	else if (RX_PATTERN_PKT == reason)
-+		_dbg_wake_up_reason_string(adapter, "Rx pattern packet");
-+	else if (RTD3_SSID_MATCH == reason)
-+		_dbg_wake_up_reason_string(adapter, "RTD3 SSID match");
-+	else if (RX_REALWOW_V2_WAKEUP_PKT == reason)
-+		_dbg_wake_up_reason_string(adapter, "Rx real WOW V2 wakeup packet");
-+	else if (RX_REALWOW_V2_ACK_LOST == reason)
-+		_dbg_wake_up_reason_string(adapter, "Rx real WOW V2 ack lost");
-+	else if (ENABLE_FAIL_DMA_IDLE == reason)
-+		_dbg_wake_up_reason_string(adapter, "enable fail DMA idle");
-+	else if (ENABLE_FAIL_DMA_PAUSE == reason)
-+		_dbg_wake_up_reason_string(adapter, "enable fail DMA pause");
-+	else if (AP_OFFLOAD_WAKEUP == reason)
-+		_dbg_wake_up_reason_string(adapter, "AP offload wakeup");
-+	else if (CLK_32K_UNLOCK == reason)
-+		_dbg_wake_up_reason_string(adapter, "clk 32k unlock");
-+	else if (RTIME_FAIL_DMA_IDLE == reason)
-+		_dbg_wake_up_reason_string(adapter, "RTIME fail DMA idle");
-+	else if (CLK_32K_LOCK == reason)
-+		_dbg_wake_up_reason_string(adapter, "clk 32k lock");
-+	#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+	else if (WOW_KEEPALIVE_ACK_TIMEOUT == reason)
-+		_dbg_wake_up_reason_string(adapter, "rx keep alive ack timeout");
-+	else if (WOW_KEEPALIVE_WAKE == reason)
-+		_dbg_wake_up_reason_string(adapter, "rx keep alive wake pattern");
-+	#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+	else
-+		_dbg_wake_up_reason_string(adapter, "unknown reasoen");
-+}
-+#endif
-+
-+static void rtw_hal_wow_disable(_adapter *adapter)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+	struct security_priv *psecuritypriv = &adapter->securitypriv;
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct sta_info *psta = NULL;
-+	struct registry_priv  *registry_par = &adapter->registrypriv;
-+	int res;
-+	u16 media_status_rpt;
-+
-+	RTW_PRINT("%s, WOWLAN_DISABLE\n", __func__);
-+	
-+	if(registry_par->suspend_type == FW_IPS_DISABLE_BBRF && !check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
-+		RTW_INFO("FW_IPS_DISABLE_BBRF resume\n");
-+		return;
-+	}
-+	
-+	if (!pwrctl->wowlan_pno_enable) {
-+		psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
-+		if (psta != NULL)
-+			rtw_sta_media_status_rpt(adapter, psta, 0);
-+		else
-+			RTW_INFO("%s: psta is null\n", __func__);
-+	}
-+
-+	if (0) {
-+		RTW_INFO("0x630:0x%02x\n", rtw_read8(adapter, 0x630));
-+		RTW_INFO("0x631:0x%02x\n", rtw_read8(adapter, 0x631));
-+		RTW_INFO("0x634:0x%02x\n", rtw_read8(adapter, 0x634));
-+		RTW_INFO("0x1c7:0x%02x\n", rtw_read8(adapter, 0x1c7));
-+	}
-+
-+	pwrctl->wowlan_wake_reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
-+
-+	RTW_PRINT("wakeup_reason: 0x%02x\n",
-+		  pwrctl->wowlan_wake_reason);
-+	#ifdef DBG_WAKEUP_REASON
-+	_dbg_rtw_wake_up_reason(adapter, pwrctl->wowlan_wake_reason);
-+	#endif
-+
-+	rtw_hal_set_fw_wow_related_cmd(adapter, 0);
-+
-+	res = rtw_hal_check_wow_ctrl(adapter, _FALSE);
-+
-+	#if defined(CONFIG_RTL8188E)
-+	if (IS_HARDWARE_TYPE_8188E(adapter))
-+		rtw_hal_enable_tx_report(adapter);
-+	#endif
-+
-+	if ((pwrctl->wowlan_wake_reason != RX_DISASSOC) &&
-+		(pwrctl->wowlan_wake_reason != RX_DEAUTH) &&
-+		(pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT)) {
-+		rtw_hal_get_aoac_rpt(adapter);
-+		rtw_hal_update_sw_security_info(adapter);
-+	}
-+
-+	if (res == _FALSE) {
-+		RTW_INFO("[Error]%s: disable WOW cmd fail\n!!", __func__);
-+		rtw_hal_force_enable_rxdma(adapter);
-+	}
-+
-+	rtw_hal_gate_bb(adapter, _TRUE);
-+
-+	res = rtw_hal_pause_rx_dma(adapter);
-+	if (res == _FAIL)
-+		RTW_PRINT("[WARNING] pause RX DMA fail\n");
-+
-+	/* clean HW pattern match */
-+	rtw_hal_dl_pattern(adapter, 0);
-+
-+	#ifndef CONFIG_WOW_PATTERN_HW_CAM
-+	/* config RXFF boundary to original */
-+	#ifndef CONFIG_WOW_PATTERN_IN_TXFIFO
-+	rtw_hal_set_wow_rxff_boundary(adapter, _FALSE);
-+	#endif /*CONFIG_WOW_PATTERN_IN_TXFIFO*/
-+	#endif
-+	rtw_hal_release_rx_dma(adapter);
-+
-+	rtw_hal_fw_dl(adapter, _FALSE);
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+
-+#ifdef CONFIG_RTW_ONE_PIN_GPIO
-+	rtw_hal_set_input_gpio(adapter, pwrctl->wowlan_gpio_index);
-+#else
-+#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
-+	if (pwrctl->is_high_active == 0)
-+		rtw_hal_set_input_gpio(adapter, pwrctl->wowlan_gpio_index);
-+	else
-+		rtw_hal_set_output_gpio(adapter, pwrctl->wowlan_gpio_index,
-+			GPIO_OUTPUT_LOW);
-+#else
-+	rtw_hal_set_output_gpio(adapter, pwrctl->wowlan_gpio_index
-+		, pwrctl->wowlan_gpio_output_state);
-+	RTW_INFO("%s: set GPIO_%d to OUTPUT %s state in wow resume and %s_ACTIVE.\n",
-+		 __func__, pwrctl->wowlan_gpio_index, 
-+		 pwrctl->wowlan_gpio_output_state ? "HIGH" : "LOW",
-+		 pwrctl->is_high_active ? "HIGI" : "LOW");
-+#endif /* CONFIG_WAKEUP_GPIO_INPUT_MODE */
-+#endif /* CONFIG_RTW_ONE_PIN_GPIO */
-+#endif /* CONFIG_GPIO_WAKEUP */
-+	if ((pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT) &&
-+	    (pwrctl->wowlan_wake_reason != RX_PAIRWISEKEY) &&
-+	    (pwrctl->wowlan_wake_reason != RX_DISASSOC) &&
-+	    (pwrctl->wowlan_wake_reason != RX_DEAUTH)) {
-+
-+		media_status_rpt = RT_MEDIA_CONNECT;
-+		rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
-+				  (u8 *)&media_status_rpt);
-+
-+		if (psta != NULL) {
-+			#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+			adapter_to_dvobj(adapter)->dft.port_id = 0xFF;
-+			adapter_to_dvobj(adapter)->dft.mac_id = 0xFF;
-+			rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);
-+			#endif
-+			rtw_sta_media_status_rpt(adapter, psta, 1);
-+		}
-+	}
-+	rtw_hal_gate_bb(adapter, _FALSE);
-+}
-+#endif /*CONFIG_WOWLAN*/
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
-+	      u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len,
-+				      RSVDPAGE_LOC *rsvd_page_loc)
-+{
-+	u32 P2PNegoRspLength = 0, P2PInviteRspLength = 0;
-+	u32 P2PPDRspLength = 0, P2PProbeRspLength = 0, P2PBCNLength = 0;
-+	u8 CurtPktPageNum = 0;
-+
-+	/* P2P Beacon */
-+	rsvd_page_loc->LocP2PBeacon = *page_num;
-+	rtw_hal_construct_P2PBeacon(adapter, &pframe[index], &P2PBCNLength);
-+	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
-+				 P2PBCNLength, _FALSE, _FALSE, _FALSE);
-+
-+#if 0
-+	RTW_INFO("%s(): HW_VAR_SET_TX_CMD: PROBE RSP %p %d\n",
-+		__FUNCTION__, &pframe[index - tx_desc], (P2PBCNLength + tx_desc));
-+#endif
-+
-+	CurtPktPageNum = (u8)PageNum(tx_desc + P2PBCNLength, page_size);
-+
-+	*page_num += CurtPktPageNum;
-+
-+	index += (CurtPktPageNum * page_size);
-+	RSVD_PAGE_CFG("WOW-P2P-Beacon", CurtPktPageNum, *page_num, 0);
-+
-+	/* P2P Probe rsp */
-+	rsvd_page_loc->LocP2PProbeRsp = *page_num;
-+	rtw_hal_construct_P2PProbeRsp(adapter, &pframe[index],
-+				      &P2PProbeRspLength);
-+	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
-+				 P2PProbeRspLength, _FALSE, _FALSE, _FALSE);
-+
-+	/* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: PROBE RSP %p %d\n",  */
-+	/*	__FUNCTION__, &pframe[index-tx_desc], (P2PProbeRspLength+tx_desc)); */
-+
-+	CurtPktPageNum = (u8)PageNum(tx_desc + P2PProbeRspLength, page_size);
-+
-+	*page_num += CurtPktPageNum;
-+
-+	index += (CurtPktPageNum * page_size);
-+	RSVD_PAGE_CFG("WOW-P2P-ProbeRsp", CurtPktPageNum, *page_num, 0);
-+
-+	/* P2P nego rsp */
-+	rsvd_page_loc->LocNegoRsp = *page_num;
-+	rtw_hal_construct_P2PNegoRsp(adapter, &pframe[index],
-+				     &P2PNegoRspLength);
-+	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
-+				 P2PNegoRspLength, _FALSE, _FALSE, _FALSE);
-+
-+	/* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\n",  */
-+	/*	__FUNCTION__, &pframe[index-tx_desc], (NegoRspLength+tx_desc)); */
-+
-+	CurtPktPageNum = (u8)PageNum(tx_desc + P2PNegoRspLength, page_size);
-+
-+	*page_num += CurtPktPageNum;
-+
-+	index += (CurtPktPageNum * page_size);
-+	RSVD_PAGE_CFG("WOW-P2P-NegoRsp", CurtPktPageNum, *page_num, 0);
-+
-+	/* P2P invite rsp */
-+	rsvd_page_loc->LocInviteRsp = *page_num;
-+	rtw_hal_construct_P2PInviteRsp(adapter, &pframe[index],
-+				       &P2PInviteRspLength);
-+	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
-+				 P2PInviteRspLength, _FALSE, _FALSE, _FALSE);
-+
-+	/* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\n",  */
-+	/* __FUNCTION__, &pframe[index-tx_desc], (InviteRspLength+tx_desc)); */
-+
-+	CurtPktPageNum = (u8)PageNum(tx_desc + P2PInviteRspLength, page_size);
-+
-+	*page_num += CurtPktPageNum;
-+
-+	index += (CurtPktPageNum * page_size);
-+	RSVD_PAGE_CFG("WOW-P2P-InviteRsp", CurtPktPageNum, *page_num, 0);
-+
-+	/* P2P provision discovery rsp */
-+	rsvd_page_loc->LocPDRsp = *page_num;
-+	rtw_hal_construct_P2PProvisionDisRsp(adapter,
-+					     &pframe[index], &P2PPDRspLength);
-+
-+	rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
-+				 P2PPDRspLength, _FALSE, _FALSE, _FALSE);
-+
-+	/* RTW_INFO("%s(): HW_VAR_SET_TX_CMD: QOS NULL DATA %p %d\n",  */
-+	/*	__FUNCTION__, &pframe[index-tx_desc], (PDRspLength+tx_desc)); */
-+
-+	CurtPktPageNum = (u8)PageNum(tx_desc + P2PPDRspLength, page_size);
-+
-+	*page_num += CurtPktPageNum;
-+
-+	*total_pkt_len = index + P2PPDRspLength;
-+	RSVD_PAGE_CFG("WOW-P2P-PDR", CurtPktPageNum, *page_num, *total_pkt_len);
-+
-+	index += (CurtPktPageNum * page_size);
-+
-+
-+}
-+#endif /* CONFIG_P2P_WOWLAN */
-+
-+#ifdef CONFIG_LPS_PG
-+#ifndef DBG_LPSPG_INFO_DUMP
-+#define DBG_LPSPG_INFO_DUMP 1
-+#endif
-+
-+#include "hal_halmac.h"
-+
-+#ifdef CONFIG_RTL8822C
-+static int rtw_lps_pg_set_dpk_info_rsvd_page(_adapter *adapter)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct dm_struct *dm = adapter_to_phydm(adapter);
-+	struct rsvd_page_cache_t *cache = &pwrpriv->lpspg_dpk_info;
-+	u8 *info = NULL;
-+	u32 info_len;
-+	int ret = _FAIL;
-+
-+	/* get length */
-+	halrf_dpk_info_rsvd_page(dm, NULL, &info_len);
-+	if (!info_len) {
-+		RTW_ERR("get %s length fail\n", cache->name);
-+		goto exit;
-+	}
-+
-+	/* allocate buf */
-+	info = rtw_zmalloc(info_len);
-+	if (!info) {
-+		RTW_ERR("alloc %s buffer fail(len=%d)\n", cache->name, info_len);
-+		goto exit;
-+	}
-+
-+	/* get content */
-+	halrf_dpk_info_rsvd_page(dm, info, NULL);
-+
-+	if (rsvd_page_cache_update_data(cache, info, info_len)) {
-+
-+		#if (DBG_LPSPG_INFO_DUMP >= 1)
-+		RTW_INFO_DUMP(cache->name, info, info_len);
-+		#endif
-+
-+		ret = rtw_halmac_download_rsvd_page(dvobj, cache->loc, info, info_len);
-+		ret = !ret ? _SUCCESS : _FAIL;
-+		if (ret != _SUCCESS) {
-+			RTW_ERR("download %s rsvd page to offset:%u fail\n", cache->name, cache->loc);
-+			goto free_mem;
-+		}
-+
-+		#if (DBG_LPSPG_INFO_DUMP >= 2)
-+		RTW_INFO("get %s from rsvd page offset:%d\n", cache->name, cache->loc);
-+		rtw_dump_rsvd_page(RTW_DBGDUMP, adapter, cache->loc, cache->page_num);
-+		#endif
-+	}
-+
-+free_mem:
-+	rtw_mfree(info, info_len);
-+
-+exit:
-+	return ret;
-+}
-+
-+static int rtw_lps_pg_set_iqk_info_rsvd_page(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct dm_struct *dm = adapter_to_phydm(adapter);
-+	struct rsvd_page_cache_t *cache = &pwrpriv->lpspg_iqk_info;
-+	u8 *info = NULL;
-+	u32 info_len = 0;
-+	int ret = _FAIL;
-+
-+	if (hal_data->RegIQKFWOffload) {
-+		rsvd_page_cache_free_data(cache);
-+		ret = _SUCCESS;
-+		goto exit;
-+	}
-+
-+	/* get length */
-+	halrf_iqk_info_rsvd_page(dm, NULL, &info_len);
-+	if (!info_len) {
-+		RTW_ERR("get %s length fail\n", cache->name);
-+		goto exit;
-+	}
-+
-+	/* allocate buf */
-+	info = rtw_zmalloc(info_len);
-+	if (!info) {
-+		RTW_ERR("alloc %s buffer fail(len=%d)\n", cache->name, info_len);
-+		goto exit;
-+	}
-+
-+	/* get content */
-+	halrf_iqk_info_rsvd_page(dm, info, NULL);
-+
-+	if (rsvd_page_cache_update_data(cache, info, info_len)) {
-+
-+		#if (DBG_LPSPG_INFO_DUMP >= 1)
-+		RTW_INFO_DUMP(cache->name, info, info_len);
-+		#endif
-+
-+		ret = rtw_halmac_download_rsvd_page(dvobj, cache->loc, info, info_len);
-+		ret = !ret ? _SUCCESS : _FAIL;
-+		if (ret != _SUCCESS) {
-+			RTW_ERR("download %s rsvd page to offset:%u fail\n", cache->name, cache->loc);
-+			goto free_mem;
-+		}
-+
-+		#if (DBG_LPSPG_INFO_DUMP >= 2)
-+		RTW_INFO("get %s from rsvd page offset:%d\n", cache->name, cache->loc);
-+		rtw_dump_rsvd_page(RTW_DBGDUMP, adapter, cache->loc, cache->page_num);
-+		#endif
-+	}
-+
-+free_mem:
-+	rtw_mfree(info, info_len);
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_RTL8822C */
-+
-+static void rtw_hal_build_lps_pg_info_rsvd_page(struct dvobj_priv *dvobj, _adapter *ld_sta_iface, u8 *buf, u32 *buf_size)
-+{
-+#define LPS_PG_INFO_RSVD_LEN	16
-+
-+	if (buf) {
-+		_adapter *adapter = dvobj_get_primary_adapter(dvobj);
-+		struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+		struct sta_info *psta;
-+#ifdef CONFIG_MBSSID_CAM
-+		u8 cam_id = INVALID_CAM_ID;
-+#endif
-+		u8 *psec_cam_id = buf + 8;
-+		u8 sec_cam_num = 0;
-+		u8 drv_rsvdpage_num = 0;
-+
-+		if (ld_sta_iface) {
-+			psta = rtw_get_stainfo(&ld_sta_iface->stapriv, get_bssid(&ld_sta_iface->mlmepriv));
-+			if (!psta) {
-+				RTW_ERR("%s [ERROR] sta is NULL\n", __func__);
-+				rtw_warn_on(1);
-+				goto size_chk;
-+			}
-+			/*Byte 0 - used macid*/
-+			LPSPG_RSVD_PAGE_SET_MACID(buf, psta->cmn.mac_id);
-+			RTW_INFO("[LPSPG-INFO] mac_id:%d\n", psta->cmn.mac_id);
-+		}
-+
-+#ifdef CONFIG_MBSSID_CAM
-+		/*Byte 1 - used BSSID CAM entry*/
-+		cam_id = rtw_mbid_cam_search_by_ifaceid(adapter, adapter->iface_id);
-+		if (cam_id != INVALID_CAM_ID)
-+			LPSPG_RSVD_PAGE_SET_MBSSCAMID(buf, cam_id);
-+		RTW_INFO("[LPSPG-INFO] mbss_cam_id:%d\n", cam_id);
-+#endif
-+
-+#ifdef CONFIG_WOWLAN /*&& pattern match cam used*/
-+		/*Btye 2 - Max used Pattern Match CAM entry*/
-+		if (pwrpriv->wowlan_mode == _TRUE
-+			&& ld_sta_iface && check_fwstate(&ld_sta_iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+			LPSPG_RSVD_PAGE_SET_PMC_NUM(buf, pwrpriv->wowlan_pattern_idx);
-+			RTW_INFO("[LPSPG-INFO] Max Pattern Match CAM entry :%d\n", pwrpriv->wowlan_pattern_idx);
-+		}
-+#endif
-+#ifdef CONFIG_BEAMFORMING  /*&& MU BF*/
-+		/*Btye 3 - Max MU rate table Group ID*/
-+		LPSPG_RSVD_PAGE_SET_MU_RAID_GID(buf, 0);
-+		RTW_INFO("[LPSPG-INFO] Max MU rate table Group ID :%d\n", 0);
-+#endif
-+
-+		/*Btye 8 ~15 - used Security CAM entry */
-+		sec_cam_num = rtw_get_sec_camid(adapter, 8, psec_cam_id);
-+
-+		/*Btye 4 - used Security CAM entry number*/
-+		if (sec_cam_num < 8)
-+			LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(buf, sec_cam_num);
-+		RTW_INFO("[LPSPG-INFO] Security CAM entry number :%d\n", sec_cam_num);
-+
-+		/*Btye 5 - Txbuf used page number for fw offload*/
-+		if (pwrpriv->wowlan_mode == _TRUE || pwrpriv->wowlan_ap_mode == _TRUE)
-+			drv_rsvdpage_num = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE);
-+		else
-+			drv_rsvdpage_num = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE);
-+		LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(buf, drv_rsvdpage_num);
-+		RTW_INFO("[LPSPG-INFO] DRV's rsvd page numbers :%d\n", drv_rsvdpage_num);
-+	}
-+
-+size_chk:
-+	if (buf_size)
-+		*buf_size = LPS_PG_INFO_RSVD_LEN;
-+}
-+
-+static int rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct rsvd_page_cache_t *cache = &pwrpriv->lpspg_info;
-+	u8 *info = NULL;
-+	u32 info_len = 0;
-+	int ret = _FAIL;
-+
-+	/* get length */
-+	rtw_hal_build_lps_pg_info_rsvd_page(dvobj, adapter, NULL, &info_len);
-+	if (!info_len) {
-+		RTW_ERR("get %s length fail\n", cache->name);
-+		goto exit;
-+	}
-+
-+	/* allocate buf */
-+	info = rtw_zmalloc(info_len);
-+	if (!info) {
-+		RTW_ERR("alloc %s buffer fail(len=%d)\n", cache->name, info_len);
-+		goto exit;
-+	}
-+
-+	/* get content */
-+	rtw_hal_build_lps_pg_info_rsvd_page(dvobj, adapter, info, NULL);
-+
-+	if (rsvd_page_cache_update_data(cache, info, info_len)) {
-+
-+		#if (DBG_LPSPG_INFO_DUMP >= 1)
-+		RTW_INFO_DUMP(cache->name, info, info_len);
-+		#endif
-+
-+		ret = rtw_halmac_download_rsvd_page(dvobj, cache->loc, info, info_len);
-+		ret = !ret ? _SUCCESS : _FAIL;
-+		if (ret != _SUCCESS) {
-+			RTW_ERR("download %s rsvd page to offset:%u fail\n", cache->name, cache->loc);
-+			goto free_mem;
-+		}
-+
-+		#if (DBG_LPSPG_INFO_DUMP >= 2)
-+		RTW_INFO("get %s from rsvd page offset:%d\n", cache->name, cache->loc);
-+		rtw_dump_rsvd_page(RTW_DBGDUMP, adapter, cache->loc, cache->page_num);
-+		#endif
-+	}
-+
-+free_mem:
-+	rtw_mfree(info, info_len);
-+
-+exit:
-+	return ret;
-+}
-+
-+static void rtw_lps_pg_set_rsvd_page(_adapter *adapter, u8 *frame, u16 *index
-+	, u8 txdesc_size, u32 page_size, u8 *total_page_num
-+	, bool is_wow_mode, _adapter *ld_sta_iface, bool only_get_page_num)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+	struct rsvd_page_cache_t *cache;
-+	bool rsvd = 1;
-+	u8 *pos;
-+	u32 len;
-+
-+	if (is_wow_mode) {
-+		/* lps_level will not change when enter wow_mode */
-+		if (pwrctl->lps_level != LPS_PG)
-+			rsvd = 0;
-+	} else {
-+		if (!only_get_page_num && !ld_sta_iface)
-+			rsvd = 0;
-+	}
-+
-+	pos = only_get_page_num ? NULL : frame + *index;
-+
-+#ifdef CONFIG_RTL8822C
-+	if (IS_8822C_SERIES(hal_data->version_id)) {
-+		/* LPSPG_DPK_INFO */
-+		cache = &pwrctl->lpspg_dpk_info;
-+		if (rsvd) {
-+			if (pwrctl->lps_level != LPS_PG)
-+				pos = NULL;
-+			len = 0;
-+			halrf_dpk_info_rsvd_page(adapter_to_phydm(adapter), pos, &len);
-+			#if (DBG_LPSPG_INFO_DUMP >= 1)
-+			if (pos)
-+				RTW_INFO_DUMP(cache->name, pos, len);
-+			#endif
-+			rsvd_page_cache_update_all(cache, *total_page_num, txdesc_size, page_size, pos, len);
-+			*total_page_num += cache->page_num;
-+			*index += page_size * cache->page_num;
-+			pos = only_get_page_num ? NULL : frame + *index;
-+			RSVD_PAGE_CFG(cache->name, cache->page_num, *total_page_num, *index);
-+		} else
-+			rsvd_page_cache_free(cache);
-+
-+		/* LPSPG_IQK_INFO */
-+		cache = &pwrctl->lpspg_iqk_info;
-+		if (rsvd
-+			/* RegIQKFWOffload will not change when enter wow_mode */
-+			&& !(is_wow_mode && hal_data->RegIQKFWOffload)
-+		) {
-+			if (pwrctl->lps_level != LPS_PG || hal_data->RegIQKFWOffload)
-+				pos = NULL;
-+			len = 0;
-+			halrf_iqk_info_rsvd_page(adapter_to_phydm(adapter), pos, &len);
-+			#if (DBG_LPSPG_INFO_DUMP >= 1)
-+			if (pos)
-+				RTW_INFO_DUMP(cache->name, pos, len);
-+			#endif
-+			rsvd_page_cache_update_all(cache, *total_page_num, txdesc_size, page_size, pos, len);
-+			*total_page_num += cache->page_num;
-+			*index += page_size * cache->page_num;
-+			pos = only_get_page_num ? NULL : frame + *index;
-+			RSVD_PAGE_CFG(cache->name, cache->page_num, *total_page_num, *index);
-+		} else
-+			rsvd_page_cache_free(cache);
-+	}
-+#endif
-+
-+	/* LPSPG_INFO */
-+	cache = &pwrctl->lpspg_info;
-+	if (rsvd) {
-+		if (pwrctl->lps_level != LPS_PG)
-+			pos = NULL;
-+		rtw_hal_build_lps_pg_info_rsvd_page(adapter_to_dvobj(adapter), ld_sta_iface, pos, &len);
-+		#if (DBG_LPSPG_INFO_DUMP >= 1)
-+		if (pos)
-+			RTW_INFO_DUMP(cache->name, pos, len);
-+		#endif
-+		rsvd_page_cache_update_all(cache, *total_page_num, txdesc_size, page_size, pos, len);
-+		*total_page_num += cache->page_num;
-+		*index += page_size * cache->page_num;
-+		pos = only_get_page_num ? NULL : frame + *index;
-+		RSVD_PAGE_CFG(cache->name, cache->page_num, *total_page_num, *index);
-+	} else
-+		rsvd_page_cache_free(cache);
-+}
-+
-+u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+
-+	u8 lpspg_info[H2C_LPS_PG_INFO_LEN] = {0};
-+	u8 ret = _FAIL;
-+
-+	if (_NO_PRIVACY_ != adapter->securitypriv.dot11PrivacyAlgrthm)
-+		SET_H2CCMD_LPSPG_SEC_CAM_EN(lpspg_info, 1);	/*SecurityCAM_En*/
-+
-+#ifdef CONFIG_MBSSID_CAM
-+	SET_H2CCMD_LPSPG_MBID_CAM_EN(lpspg_info, 1);		/*BSSIDCAM_En*/
-+#endif
-+
-+#if defined(CONFIG_WOWLAN) && defined(CONFIG_WOW_PATTERN_HW_CAM)
-+	if (pwrpriv->wowlan_mode == _TRUE &&
-+	    check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+
-+		SET_H2CCMD_LPSPG_PMC_CAM_EN(lpspg_info, 1);	/*PatternMatchCAM_En*/
-+	}
-+#endif
-+
-+#ifdef CONFIG_MACID_SEARCH
-+	SET_H2CCMD_LPSPG_MACID_SEARCH_EN(lpspg_info, 1);	/*MACIDSearch_En*/
-+#endif
-+
-+#ifdef CONFIG_TX_SC
-+	SET_H2CCMD_LPSPG_TXSC_EN(lpspg_info, 1);	/*TXSC_En*/
-+#endif
-+
-+#ifdef CONFIG_BEAMFORMING  /*&& MU BF*/
-+	SET_H2CCMD_LPSPG_MU_RATE_TB_EN(lpspg_info, 1);	/*MURateTable_En*/
-+#endif
-+
-+	SET_H2CCMD_LPSPG_LOC(lpspg_info, pwrpriv->lpspg_info.loc);
-+
-+#ifdef CONFIG_RTL8822C
-+	if (pwrpriv->bFwCurrentInPSMode == _FALSE) {
-+		SET_H2CCMD_LPSPG_DPK_INFO_LOC(lpspg_info, pwrpriv->lpspg_dpk_info.loc);
-+		if (!GET_HAL_DATA(adapter)->RegIQKFWOffload)
-+			SET_H2CCMD_LPSPG_IQK_INFO_LOC(lpspg_info, pwrpriv->lpspg_iqk_info.loc);
-+	} else {
-+		SET_H2CCMD_LPSPG_DPK_INFO_LOC(lpspg_info, 0);
-+		if (!GET_HAL_DATA(adapter)->RegIQKFWOffload)
-+			SET_H2CCMD_LPSPG_IQK_INFO_LOC(lpspg_info, 0);
-+	}
-+#endif
-+
-+#if (DBG_LPSPG_INFO_DUMP >= 1)
-+	RTW_INFO_DUMP("H2C_LPS_PG_INFO: ", lpspg_info, H2C_LPS_PG_INFO_LEN);
-+#endif
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+				   H2C_LPS_PG_INFO,
-+				   H2C_LPS_PG_INFO_LEN,
-+				   lpspg_info);
-+	return ret;
-+}
-+u8 rtw_hal_set_lps_pg_info(_adapter *adapter)
-+{
-+	u8 ret = _FAIL;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+
-+	if (pwrpriv->lpspg_info.loc == 0) {
-+		RTW_ERR("%s lpspg_info.loc = 0\n", __func__);
-+		rtw_warn_on(1);
-+		return ret;
-+	}
-+	#ifdef CONFIG_RTL8822C
-+	rtw_lps_pg_set_dpk_info_rsvd_page(adapter);
-+	rtw_lps_pg_set_iqk_info_rsvd_page(adapter);
-+	#endif
-+	rtw_hal_set_lps_pg_info_rsvd_page(adapter);
-+
-+	ret = rtw_hal_set_lps_pg_info_cmd(adapter);
-+
-+	return ret;
-+}
-+
-+void rtw_hal_lps_pg_rssi_lv_decide(_adapter *adapter, struct sta_info *sta)
-+{
-+#if 0
-+	if (sta->cmn.ra_info.rssi_level >= 4)
-+		sta->lps_pg_rssi_lv = 3;	/*RSSI High - 1SS_VHT_MCS7*/
-+	else if (sta->cmn.ra_info.rssi_level >=  2)
-+		sta->lps_pg_rssi_lv = 2;	/*RSSI Middle - 1SS_VHT_MCS3*/
-+	else
-+		sta->lps_pg_rssi_lv = 1;	/*RSSI Lower - Lowest_rate*/
-+#else
-+	sta->lps_pg_rssi_lv = 0;
-+#endif
-+	RTW_INFO("%s mac-id:%d, rssi:%d, rssi_level:%d, lps_pg_rssi_lv:%d\n",
-+		__func__, sta->cmn.mac_id, sta->cmn.rssi_stat.rssi, sta->cmn.ra_info.rssi_level, sta->lps_pg_rssi_lv);
-+}
-+
-+void rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id)
-+{
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+	struct sta_info *sta;
-+
-+	sta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
-+
-+	switch (hdl_id) {
-+	case LPS_PG_INFO_CFG:
-+		rtw_hal_set_lps_pg_info(adapter);
-+		break;
-+	case LPS_PG_REDLEMEM:
-+		if (IS_8822C_SERIES(GET_HAL_DATA(adapter)->version_id))
-+			break;
-+
-+		/*set xmit_block*/
-+		rtw_set_xmit_block(adapter, XMIT_BLOCK_REDLMEM);
-+		if (_FAIL == rtw_hal_fw_mem_dl(adapter, FW_EMEM))
-+			rtw_warn_on(1);
-+		/*clearn xmit_block*/
-+		rtw_clr_xmit_block(adapter, XMIT_BLOCK_REDLMEM);
-+		break;
-+	case LPS_PG_PHYDM_DIS:/*Disable RA and PT by H2C*/
-+		if (IS_8822C_SERIES(GET_HAL_DATA(adapter)->version_id))
-+			break;
-+
-+		if (sta)
-+			rtw_phydm_lps_pg_hdl(adapter, sta, _TRUE);
-+		break;
-+	case LPS_PG_PHYDM_EN:/*Enable RA and PT by H2C*/
-+		if (IS_8822C_SERIES(GET_HAL_DATA(adapter)->version_id))
-+			break;
-+
-+		if (sta) {
-+			rtw_hal_lps_pg_rssi_lv_decide(adapter, sta);
-+			rtw_phydm_lps_pg_hdl(adapter, sta, _FALSE);
-+			sta->lps_pg_rssi_lv = 0;
-+		}
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+#endif /*CONFIG_LPS_PG*/
-+
-+static u8 _rtw_mi_assoc_if_num(_adapter *adapter)
-+{
-+	u8 mi_iface_num = 0;
-+
-+	if (0) {
-+		RTW_INFO("[IFS_ASSOC_STATUS] - STA :%d", DEV_STA_LD_NUM(adapter_to_dvobj(adapter)));
-+		RTW_INFO("[IFS_ASSOC_STATUS] - AP:%d", DEV_AP_NUM(adapter_to_dvobj(adapter)));
-+		RTW_INFO("[IFS_ASSOC_STATUS] - AP starting :%d", DEV_AP_STARTING_NUM(adapter_to_dvobj(adapter)));
-+		RTW_INFO("[IFS_ASSOC_STATUS] - MESH :%d", DEV_MESH_NUM(adapter_to_dvobj(adapter)));
-+		RTW_INFO("[IFS_ASSOC_STATUS] - ADHOC :%d", DEV_ADHOC_NUM(adapter_to_dvobj(adapter)));
-+		/*RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GC :%d", DEV_P2P_GC_NUM(adapter_to_dvobj(adapter)));*/
-+		/*RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GO :%d", DEV_P2P_GO_NUM(adapter_to_dvobj(adapter)));*/
-+	}
-+
-+	mi_iface_num = (DEV_STA_LD_NUM(adapter_to_dvobj(adapter)) +
-+		DEV_AP_NUM(adapter_to_dvobj(adapter)) +
-+		DEV_AP_STARTING_NUM(adapter_to_dvobj(adapter)));
-+	return mi_iface_num;
-+}
-+#ifdef CONFIG_CONCURRENT_MODE
-+static _adapter *_rtw_search_sta_iface(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	_adapter *iface = NULL;
-+	_adapter *sta_iface = NULL;
-+	int i;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) {
-+			if (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+				sta_iface = iface;
-+				break;
-+			}
-+		}
-+	}
-+	return sta_iface;
-+}
-+#if defined(CONFIG_AP_MODE) && defined(CONFIG_BT_COEXIST)
-+static _adapter *_rtw_search_ap_iface(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	_adapter *iface = NULL;
-+	_adapter *ap_iface = NULL;
-+	int i;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) {
-+			ap_iface = iface;
-+			break;
-+		}
-+	}
-+	return ap_iface;
-+}
-+#endif/*CONFIG_AP_MODE*/
-+#endif/*CONFIG_CONCURRENT_MODE*/
-+
-+#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
-+void rtw_hal_set_pathb_phase(_adapter *adapter, u8 phase_idx)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(adapter);
-+	struct PHY_DM_STRUCT		*pDM_Odm = &pHalData->odmpriv;
-+
-+	return phydm_pathb_q_matrix_rotate(pDM_Odm, phase_idx);
-+}
-+#endif
-+
-+/*
-+ * Description: Fill the reserved packets that FW will use to RSVD page.
-+ *			Now we just send 4 types packet to rsvd page.
-+ *			(1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp.
-+ * Input:
-+ * finished - FALSE:At the first time we will send all the packets as a large packet to Hw,
-+ *		    so we need to set the packet length to total lengh.
-+ *	      TRUE: At the second time, we should send the first packet (default:beacon)
-+ *		    to Hw again and set the lengh in descriptor to the real beacon lengh.
-+ * page_num - The amount of reserved page which driver need.
-+ *	      If this is not NULL, this function doesn't real download reserved
-+ *	      page, but just count the number of reserved page.
-+ *
-+ * 2009.10.15 by tynli.
-+ * 2017.06.20 modified by Lucas.
-+ *
-+ * Page Size = 128: 8188e, 8723a/b, 8192c/d,
-+ * Page Size = 256: 8192e, 8821a
-+ * Page Size = 512: 8812a
-+ */
-+
-+/*#define DBG_DUMP_SET_RSVD_PAGE*/
-+static void _rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished, u8 *page_num)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+	struct xmit_frame	*pcmdframe = NULL;
-+	struct pkt_attrib	*pattrib;
-+	struct xmit_priv	*pxmitpriv;
-+	struct pwrctrl_priv *pwrctl;
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	u32	BeaconLength = 0, ProbeRspLength = 0, PSPollLength = 0;
-+	u32	NullDataLength = 0, QosNullLength = 0, BTQosNullLength = 0;
-+	u32	ProbeReqLength = 0, NullFunctionDataLength = 0;
-+	u8	TxDescLen = TXDESC_SIZE, TxDescOffset = TXDESC_OFFSET;
-+	u8	TotalPageNum = 0 , CurtPktPageNum = 0 , RsvdPageNum = 0;
-+	u8	*ReservedPagePacket;
-+	u16	BufIndex = 0;
-+	u32	TotalPacketLen = 0, MaxRsvdPageBufSize = 0, PageSize = 0;
-+	RSVDPAGE_LOC	RsvdPageLoc;
-+	struct registry_priv  *registry_par = &adapter->registrypriv;
-+
-+#ifdef DBG_FW_DEBUG_MSG_PKT
-+	u32	fw_dbg_msg_pkt_len = 0;
-+#endif /*DBG_FW_DEBUG_MSG_PKT*/
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	struct sreset_priv *psrtpriv;
-+#endif /* DBG_CONFIG_ERROR_DETECT */
-+
-+#ifdef CONFIG_MCC_MODE
-+	u8 dl_mcc_page = _FAIL;
-+#endif /* CONFIG_MCC_MODE */
-+	u8 nr_assoc_if;
-+
-+	_adapter *sta_iface = NULL;
-+	_adapter *ap_iface = NULL;
-+
-+	bool is_wow_mode = _FALSE;
-+
-+	pHalData = GET_HAL_DATA(adapter);
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	psrtpriv = &pHalData->srestpriv;
-+#endif
-+	pxmitpriv = &adapter->xmitpriv;
-+	pwrctl = adapter_to_pwrctl(adapter);
-+
-+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&PageSize);
-+
-+	if (PageSize == 0) {
-+		RTW_ERR("[Error]: %s, PageSize is zero!!\n", __func__);
-+		return;
-+	}
-+	nr_assoc_if = _rtw_mi_assoc_if_num(adapter);
-+
-+	if ((pwrctl->wowlan_mode == _TRUE && pwrctl->wowlan_in_resume == _FALSE) ||
-+		pwrctl->wowlan_ap_mode == _TRUE ||
-+		pwrctl->wowlan_p2p_mode == _TRUE)
-+		is_wow_mode = _TRUE;
-+
-+	/*page_num for init time to get rsvd page number*/
-+	/* Prepare ReservedPagePacket */
-+	if (page_num) {
-+		ReservedPagePacket = rtw_zmalloc(MAX_CMDBUF_SZ);
-+		if (!ReservedPagePacket) {
-+			RTW_WARN("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);
-+			*page_num = 0xFF;
-+			return;
-+		}
-+		RTW_INFO(FUNC_ADPT_FMT" Get [ %s ] RsvdPageNUm  ==>\n",
-+			FUNC_ADPT_ARG(adapter), (is_wow_mode) ? "WOW" : "NOR");
-+
-+	} else {
-+		if (is_wow_mode)
-+			RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE);
-+		else
-+			RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE);
-+
-+		RTW_INFO(FUNC_ADPT_FMT" PageSize: %d, [ %s ]-RsvdPageNUm: %d\n",
-+			FUNC_ADPT_ARG(adapter), PageSize, (is_wow_mode) ? "WOW" : "NOR", RsvdPageNum);
-+
-+		MaxRsvdPageBufSize = RsvdPageNum * PageSize;
-+		if (MaxRsvdPageBufSize > MAX_CMDBUF_SZ) {
-+			RTW_ERR("%s MaxRsvdPageBufSize(%d) is larger than MAX_CMDBUF_SZ(%d)",
-+				 __func__, MaxRsvdPageBufSize, MAX_CMDBUF_SZ);
-+			rtw_warn_on(1);
-+			return;
-+		}
-+
-+		pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv);
-+		if (pcmdframe == NULL) {
-+			RTW_ERR("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);
-+			return;
-+		}
-+
-+		ReservedPagePacket = pcmdframe->buf_addr;
-+	}
-+
-+	_rtw_memset(&RsvdPageLoc, 0, sizeof(RSVDPAGE_LOC));
-+
-+	BufIndex = TxDescOffset;
-+
-+	/*======== beacon content =======*/
-+	rtw_hal_construct_beacon(adapter,
-+				 &ReservedPagePacket[BufIndex], &BeaconLength);
-+
-+	/*
-+	* When we count the first page size, we need to reserve description size for the RSVD
-+	* packet, it will be filled in front of the packet in TXPKTBUF.
-+	*/
-+	BeaconLength = MAX_BEACON_LEN - TxDescLen;
-+	CurtPktPageNum = (u8)PageNum((TxDescLen + BeaconLength), PageSize);
-+
-+#if defined(CONFIG_FW_HANDLE_TXBCN) || defined(CONFIG_PORT_BASED_TXBCN)
-+	CurtPktPageNum = CurtPktPageNum * CONFIG_LIMITED_AP_NUM;
-+#endif
-+	TotalPageNum += CurtPktPageNum;
-+
-+	BufIndex += (CurtPktPageNum * PageSize);
-+
-+	RSVD_PAGE_CFG("Beacon", CurtPktPageNum, TotalPageNum, TotalPacketLen);
-+
-+	/*======== probe response content ========*/
-+	if (pwrctl->wowlan_ap_mode == _TRUE) {/*WOW mode*/
-+		#ifdef CONFIG_CONCURRENT_MODE
-+		if (nr_assoc_if >= 2)
-+			RTW_ERR("Not support > 2 net-interface in WOW\n");
-+		#endif
-+		/* (4) probe response*/
-+		RsvdPageLoc.LocProbeRsp = TotalPageNum;
-+		rtw_hal_construct_ProbeRsp(
-+			adapter, &ReservedPagePacket[BufIndex],
-+			&ProbeRspLength,
-+			_FALSE);
-+		rtw_hal_fill_fake_txdesc(adapter,
-+				 &ReservedPagePacket[BufIndex - TxDescLen],
-+				 ProbeRspLength, _FALSE, _FALSE, _FALSE);
-+
-+		CurtPktPageNum = (u8)PageNum(TxDescLen + ProbeRspLength, PageSize);
-+		TotalPageNum += CurtPktPageNum;
-+		TotalPacketLen = BufIndex + ProbeRspLength;
-+		BufIndex += (CurtPktPageNum * PageSize);
-+		RSVD_PAGE_CFG("ProbeRsp", CurtPktPageNum, TotalPageNum, TotalPacketLen);
-+		goto download_page;
-+	}
-+
-+	/*======== ps-poll content * 1 page ========*/
-+	sta_iface = adapter;
-+	#ifdef CONFIG_CONCURRENT_MODE
-+	if (!MLME_IS_STA(sta_iface) && DEV_STA_LD_NUM(adapter_to_dvobj(sta_iface))) {
-+		sta_iface = _rtw_search_sta_iface(adapter);
-+		RTW_INFO("get ("ADPT_FMT") to create PS-Poll/Null/QosNull\n", ADPT_ARG(sta_iface));
-+	}
-+	#endif
-+
-+	if (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) {
-+		RsvdPageLoc.LocPsPoll = TotalPageNum;
-+		RTW_INFO("LocPsPoll: %d\n", RsvdPageLoc.LocPsPoll);
-+		rtw_hal_construct_PSPoll(sta_iface,
-+					 &ReservedPagePacket[BufIndex], &PSPollLength);
-+		rtw_hal_fill_fake_txdesc(sta_iface,
-+					 &ReservedPagePacket[BufIndex - TxDescLen],
-+					 PSPollLength, _TRUE, _FALSE, _FALSE);
-+
-+		CurtPktPageNum = (u8)PageNum((TxDescLen + PSPollLength), PageSize);
-+
-+		TotalPageNum += CurtPktPageNum;
-+
-+		BufIndex += (CurtPktPageNum * PageSize);
-+		RSVD_PAGE_CFG("PSPoll", CurtPktPageNum, TotalPageNum, TotalPacketLen);
-+	}
-+
-+#ifdef CONFIG_MCC_MODE
-+	/*======== MCC * n page ======== */
-+	if (MCC_EN(adapter)) {/*Normal mode*/
-+		dl_mcc_page = rtw_hal_dl_mcc_fw_rsvd_page(adapter, ReservedPagePacket,
-+				&BufIndex, TxDescLen, PageSize, &TotalPageNum, &RsvdPageLoc, page_num);
-+	} else {
-+		dl_mcc_page = _FAIL;
-+	}
-+
-+	if (dl_mcc_page == _FAIL)
-+#endif /* CONFIG_MCC_MODE */
-+	{	/*======== null data * 1 page ======== */
-+		if (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) {
-+			RsvdPageLoc.LocNullData = TotalPageNum;
-+			RTW_INFO("LocNullData: %d\n", RsvdPageLoc.LocNullData);
-+			rtw_hal_construct_NullFunctionData(
-+				sta_iface,
-+				&ReservedPagePacket[BufIndex],
-+				&NullDataLength,
-+				_FALSE, 0, 0, _FALSE);
-+			rtw_hal_fill_fake_txdesc(sta_iface,
-+				 &ReservedPagePacket[BufIndex - TxDescLen],
-+				 NullDataLength, _FALSE, _FALSE, _FALSE);
-+
-+			CurtPktPageNum = (u8)PageNum(TxDescLen + NullDataLength, PageSize);
-+
-+			TotalPageNum += CurtPktPageNum;
-+
-+			BufIndex += (CurtPktPageNum * PageSize);
-+			RSVD_PAGE_CFG("NullData", CurtPktPageNum, TotalPageNum, TotalPacketLen);
-+		}
-+	}
-+
-+	/*======== Qos null data * 1 page ======== */
-+	if (pwrctl->wowlan_mode == _FALSE ||
-+		pwrctl->wowlan_in_resume == _TRUE) {/*Normal mode*/	
-+		if (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) {
-+			RsvdPageLoc.LocQosNull = TotalPageNum;
-+			RTW_INFO("LocQosNull: %d\n", RsvdPageLoc.LocQosNull);
-+			rtw_hal_construct_NullFunctionData(sta_iface,
-+						&ReservedPagePacket[BufIndex],
-+						&QosNullLength,
-+						_TRUE, 0, 0, _FALSE);
-+			rtw_hal_fill_fake_txdesc(sta_iface,
-+					 &ReservedPagePacket[BufIndex - TxDescLen],
-+					 QosNullLength, _FALSE, _FALSE, _FALSE);
-+
-+			CurtPktPageNum = (u8)PageNum(TxDescLen + QosNullLength,
-+						     PageSize);
-+
-+			TotalPageNum += CurtPktPageNum;
-+
-+			BufIndex += (CurtPktPageNum * PageSize);
-+			RSVD_PAGE_CFG("QosNull", CurtPktPageNum, TotalPageNum, TotalPacketLen);
-+		}
-+	}
-+
-+#ifdef CONFIG_BT_COEXIST
-+	/*======== BT Qos null data * 1 page ======== */
-+	if (pwrctl->wowlan_mode == _FALSE ||
-+		pwrctl->wowlan_in_resume == _TRUE) {/*Normal mode*/
-+
-+		ap_iface = adapter;
-+		#if defined (CONFIG_CONCURRENT_MODE) && defined(CONFIG_AP_MODE)
-+		if (!MLME_IS_AP(ap_iface) && DEV_AP_NUM(adapter_to_dvobj(ap_iface))) {	/*DEV_AP_STARTING_NUM*/
-+			ap_iface = _rtw_search_ap_iface(adapter);
-+			RTW_INFO("get ("ADPT_FMT") to create BTQoSNull\n", ADPT_ARG(ap_iface));
-+		}
-+		#endif
-+
-+		if (MLME_IS_AP(ap_iface) || (nr_assoc_if == 0)) {
-+			RsvdPageLoc.LocBTQosNull = TotalPageNum;
-+
-+			RTW_INFO("LocBTQosNull: %d\n", RsvdPageLoc.LocBTQosNull);
-+
-+			rtw_hal_construct_NullFunctionData(ap_iface,
-+						&ReservedPagePacket[BufIndex],
-+						&BTQosNullLength,
-+						_TRUE, 0, 0, _FALSE);
-+
-+			rtw_hal_fill_fake_txdesc(ap_iface,
-+					&ReservedPagePacket[BufIndex - TxDescLen],
-+					BTQosNullLength, _FALSE, _TRUE, _FALSE);
-+
-+			CurtPktPageNum = (u8)PageNum(TxDescLen + BTQosNullLength,
-+							 PageSize);
-+
-+			TotalPageNum += CurtPktPageNum;
-+			BufIndex += (CurtPktPageNum * PageSize);
-+
-+			RSVD_PAGE_CFG("BTQosNull", CurtPktPageNum, TotalPageNum, TotalPacketLen);
-+		}
-+	}
-+#endif /* CONFIG_BT_COEXIT */
-+
-+	TotalPacketLen = BufIndex;
-+
-+#ifdef DBG_FW_DEBUG_MSG_PKT
-+		/*======== FW DEBUG MSG * n page ======== */
-+		RsvdPageLoc.loc_fw_dbg_msg_pkt = TotalPageNum;
-+		RTW_INFO("loc_fw_dbg_msg_pkt: %d\n", RsvdPageLoc.loc_fw_dbg_msg_pkt);
-+		rtw_hal_construct_fw_dbg_msg_pkt(
-+			adapter,
-+			&ReservedPagePacket[BufIndex],
-+			&fw_dbg_msg_pkt_len);
-+
-+		rtw_hal_fill_fake_txdesc(adapter,
-+				 &ReservedPagePacket[BufIndex - TxDescLen],
-+				 fw_dbg_msg_pkt_len, _FALSE, _FALSE, _FALSE);
-+
-+		CurtPktPageNum = (u8)PageNum(TxDescLen + fw_dbg_msg_pkt_len, PageSize);
-+
-+		if (CurtPktPageNum < 2)
-+			CurtPktPageNum = 2; /*Need at least 2 rsvd page*/
-+		TotalPageNum += CurtPktPageNum;
-+
-+		TotalPacketLen = BufIndex + fw_dbg_msg_pkt_len;
-+		BufIndex += (CurtPktPageNum * PageSize);
-+#endif /*DBG_FW_DEBUG_MSG_PKT*/
-+
-+#ifdef CONFIG_LPS_PG
-+	rtw_lps_pg_set_rsvd_page(adapter, ReservedPagePacket, &BufIndex
-+		, TxDescLen, PageSize, &TotalPageNum, is_wow_mode
-+		, (sta_iface && MLME_IS_STA(sta_iface) && MLME_IS_ASOC(sta_iface)) ? sta_iface : NULL
-+		, page_num ? 1 : 0
-+	);
-+	TotalPacketLen = BufIndex;
-+#endif
-+
-+#ifdef CONFIG_WOWLAN
-+	/*======== WOW * n page ======== */
-+	if (pwrctl->wowlan_mode == _TRUE &&
-+		pwrctl->wowlan_in_resume == _FALSE &&
-+		check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {/*WOW mode*/
-+		rtw_hal_set_wow_fw_rsvd_page(adapter, ReservedPagePacket,
-+					     BufIndex, TxDescLen, PageSize,
-+			     &TotalPageNum, &TotalPacketLen, &RsvdPageLoc);
-+#ifdef CONFIG_WAR_OFFLOAD
-+		rtw_hal_set_war_offload_parm(adapter, &RsvdPageLoc);
-+#endif /* CONFIG_WAR_OFFLOAD */
-+	}
-+#endif /* CONFIG_WOWLAN */
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+	/*======== P2P WOW * n page ======== */
-+	if (_TRUE == pwrctl->wowlan_p2p_mode) {/*WOW mode*/
-+		rtw_hal_set_p2p_wow_fw_rsvd_page(adapter, ReservedPagePacket,
-+						 BufIndex, TxDescLen, PageSize,
-+				 &TotalPageNum, &TotalPacketLen, &RsvdPageLoc);
-+	}
-+#endif /* CONFIG_P2P_WOWLAN */
-+
-+	/*Note:  BufIndex already add a TxDescOffset offset in first Beacon page
-+	* The "TotalPacketLen" is calculate by BufIndex.
-+	* We need to decrease TxDescOffset before doing length check. by yiwei
-+	*/
-+	TotalPacketLen = TotalPacketLen - TxDescOffset;
-+
-+download_page:
-+	if (page_num) {
-+		*page_num = TotalPageNum;
-+		rtw_mfree(ReservedPagePacket, MAX_CMDBUF_SZ);
-+		ReservedPagePacket = NULL;
-+		RTW_INFO(FUNC_ADPT_FMT" Get [ %s ] RsvdPageNUm <==\n",
-+			FUNC_ADPT_ARG(adapter), (is_wow_mode) ? "WOW" : "NOR");
-+		return;
-+	}
-+
-+	/* RTW_INFO("%s BufIndex(%d), TxDescLen(%d), PageSize(%d)\n",__func__, BufIndex, TxDescLen, PageSize);*/
-+	RTW_INFO("%s PageNum(%d), pktlen(%d)\n",
-+		 __func__, TotalPageNum, TotalPacketLen);
-+
-+	if (TotalPacketLen > MaxRsvdPageBufSize) {
-+		RTW_ERR("%s : rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n",
-+			 __FUNCTION__, TotalPacketLen, MaxRsvdPageBufSize);
-+		rtw_warn_on(1);
-+		goto error;
-+	} else {
-+		/* update attribute */
-+		pattrib = &pcmdframe->attrib;
-+		update_mgntframe_attrib(adapter, pattrib);
-+		pattrib->qsel = QSLT_BEACON;
-+		pattrib->pktlen = TotalPacketLen;
-+		pattrib->last_txcmdsz = TotalPacketLen;
-+#ifdef CONFIG_PCI_HCI
-+		dump_mgntframe(adapter, pcmdframe);
-+#else
-+		dump_mgntframe_and_wait(adapter, pcmdframe, 100);
-+#endif
-+	}
-+
-+	RTW_INFO("%s: Set RSVD page location to Fw ,TotalPacketLen(%d), TotalPageNum(%d)\n",
-+		 __func__, TotalPacketLen, TotalPageNum);
-+#ifdef DBG_DUMP_SET_RSVD_PAGE
-+	RTW_INFO(" ==================================================\n");
-+	RTW_INFO_DUMP("\n", ReservedPagePacket, TotalPacketLen);
-+	RTW_INFO(" ==================================================\n");
-+#endif
-+
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE)
-+		|| MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)){
-+		rtw_hal_set_FwRsvdPage_cmd(adapter, &RsvdPageLoc);
-+#ifdef DBG_FW_DEBUG_MSG_PKT
-+		rtw_hal_set_fw_dbg_msg_pkt_rsvd_page_cmd(adapter, &RsvdPageLoc);
-+#endif /*DBG_FW_DEBUG_MSG_PKT*/
-+#ifdef CONFIG_WOWLAN
-+		if (pwrctl->wowlan_mode == _TRUE &&
-+			pwrctl->wowlan_in_resume == _FALSE)
-+			rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc);
-+#endif /* CONFIG_WOWLAN */
-+#ifdef CONFIG_AP_WOWLAN
-+		if (pwrctl->wowlan_ap_mode == _TRUE)
-+			rtw_hal_set_ap_rsvdpage_loc_cmd(adapter, &RsvdPageLoc);
-+#endif /* CONFIG_AP_WOWLAN */
-+	} else if (pwrctl->wowlan_pno_enable) {
-+#ifdef CONFIG_PNO_SUPPORT
-+		rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc);
-+		if (pwrctl->wowlan_in_resume)
-+			rtw_hal_set_scan_offload_info_cmd(adapter,
-+							  &RsvdPageLoc, 0);
-+		else
-+			rtw_hal_set_scan_offload_info_cmd(adapter,
-+							  &RsvdPageLoc, 1);
-+#endif /* CONFIG_PNO_SUPPORT */
-+	}
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+	if (_TRUE == pwrctl->wowlan_p2p_mode)
-+		rtw_hal_set_FwP2PRsvdPage_cmd(adapter, &RsvdPageLoc);
-+#endif /* CONFIG_P2P_WOWLAN */
-+
-+	return;
-+error:
-+	rtw_free_xmitframe(pxmitpriv, pcmdframe);
-+}
-+
-+void rtw_hal_set_fw_rsvd_page(struct _ADAPTER *adapter, bool finished)
-+{
-+#ifdef CONFIG_AP_MODE
-+	if (finished)
-+		rtw_mi_tx_beacon_hdl(adapter);
-+	else
-+#endif
-+		_rtw_hal_set_fw_rsvd_page(adapter, finished, NULL);
-+}
-+
-+static u8 rtw_hal_set_fw_bcn_early_c2h_rpt_cmd(struct _ADAPTER *adapter, u8 enable)
-+{
-+	u8	u1H2CSetPwrMode[H2C_PWRMODE_LEN] = {0};
-+	u8	ret = _FAIL;
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_TDLS_CH_SW
-+	if (ATOMIC_READ(&adapter->tdlsinfo.chsw_info.chsw_on) == _TRUE)
-+	{
-+		SET_H2CCMD_PWRMODE_PARM_RLBM(u1H2CSetPwrMode, 1);
-+		SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1H2CSetPwrMode, 0);
-+	}
-+#endif
-+#endif
-+
-+	SET_H2CCMD_PWRMODE_PARM_MODE(u1H2CSetPwrMode, 0);
-+	SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1H2CSetPwrMode, 0x0C);
-+	SET_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(u1H2CSetPwrMode, enable);
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter,
-+					H2C_SET_PWR_MODE,
-+					H2C_PWRMODE_LEN,
-+					u1H2CSetPwrMode);
-+
-+	RTW_PRINT("-%s()-\n", __func__);
-+
-+	return ret;
-+}
-+
-+/**
-+ * rtw_hal_get_rsvd_page_num() - Get needed reserved page number
-+ * @adapter:	struct _ADAPTER*
-+ *
-+ * Caculate needed reserved page number.
-+ * In different state would get different number, for example normal mode and
-+ * WOW mode would need different reserved page size.
-+ *
-+ * Return the number of reserved page which driver need.
-+ */
-+u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter)
-+{
-+	u8 num = 0;
-+
-+
-+	_rtw_hal_set_fw_rsvd_page(adapter, _FALSE, &num);
-+
-+	return num;
-+}
-+
-+#ifndef CONFIG_HAS_HW_VAR_BCN_FUNC
-+static void hw_var_set_bcn_func(_adapter *adapter, u8 enable)
-+{
-+	u32 bcn_ctrl_reg;
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (adapter->hw_port == HW_PORT1)
-+		bcn_ctrl_reg = REG_BCN_CTRL_1;
-+	else
-+#endif
-+		bcn_ctrl_reg = REG_BCN_CTRL;
-+
-+	if (enable)
-+		rtw_write8(adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
-+	else {
-+		u8 val8;
-+
-+		val8 = rtw_read8(adapter, bcn_ctrl_reg);
-+		val8 &= ~(EN_BCN_FUNCTION | EN_TXBCN_RPT);
-+
-+#ifdef CONFIG_BT_COEXIST
-+		if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist == 1) {
-+			/* Always enable port0 beacon function for PSTDMA */
-+			if (REG_BCN_CTRL == bcn_ctrl_reg)
-+				val8 |= EN_BCN_FUNCTION;
-+		}
-+#endif
-+
-+		rtw_write8(adapter, bcn_ctrl_reg, val8);
-+	}
-+
-+#ifdef CONFIG_RTL8192F
-+	if (IS_HARDWARE_TYPE_8192F(adapter)) {
-+		u16 val16, val16_ori;
-+
-+		val16_ori = val16 = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1);
-+
-+		#ifdef CONFIG_CONCURRENT_MODE
-+		if (adapter->hw_port == HW_PORT1) {
-+			if (enable)
-+				val16 |= EN_PORT_1_FUNCTION;
-+			else
-+				val16 &= ~EN_PORT_1_FUNCTION;
-+		} else
-+		#endif
-+		{
-+			if (enable)
-+				val16 |= EN_PORT_0_FUNCTION;
-+			else
-+				val16 &= ~EN_PORT_0_FUNCTION;
-+
-+			#ifdef CONFIG_BT_COEXIST
-+			if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist == 1)
-+				val16 |= EN_PORT_0_FUNCTION;
-+			#endif
-+		}
-+
-+		if (val16 != val16_ori)
-+			rtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1,  val16);
-+	}
-+#endif
-+}
-+#endif
-+
-+#ifndef CONFIG_HAS_HW_VAR_MLME_DISCONNECT
-+static void hw_var_set_mlme_disconnect(_adapter *adapter)
-+{
-+	u8 val8;
-+
-+	/* reject all data frames */
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)
-+#endif
-+		rtw_write16(adapter, REG_RXFLTMAP2, 0x0000);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (adapter->hw_port == HW_PORT1) {
-+		/* reset TSF1 */
-+		rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1));
-+
-+		/* disable update TSF1 */
-+		rtw_iface_disable_tsf_update(adapter);
-+
-+		if (!IS_HARDWARE_TYPE_8723D(adapter)
-+			&& !IS_HARDWARE_TYPE_8192F(adapter)
-+			&& !IS_HARDWARE_TYPE_8710B(adapter)
-+		) {
-+			/* disable Port1's beacon function */
-+			val8 = rtw_read8(adapter, REG_BCN_CTRL_1);
-+			val8 &= ~EN_BCN_FUNCTION;
-+			rtw_write8(adapter, REG_BCN_CTRL_1, val8);
-+		}
-+	} else
-+#endif
-+	{
-+		/* reset TSF */
-+		rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(0));
-+
-+		/* disable update TSF */
-+		rtw_iface_disable_tsf_update(adapter);
-+	}
-+}
-+#endif
-+
-+static void hw_var_set_mlme_sitesurvey(_adapter *adapter, u8 enable)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u16 value_rxfltmap2;
-+
-+#ifdef DBG_IFACE_STATUS
-+	DBG_IFACE_STATUS_DUMP(adapter);
-+#endif
-+
-+#ifdef CONFIG_FIND_BEST_CHANNEL
-+	/* Receive all data frames */
-+	value_rxfltmap2 = 0xFFFF;
-+#else
-+	/* not to receive data frame */
-+	value_rxfltmap2 = 0;
-+#endif
-+
-+	if (enable) { /* under sitesurvey */
-+		/*
-+		* 1. configure REG_RXFLTMAP2
-+		* 2. disable TSF update &  buddy TSF update to avoid updating wrong TSF due to clear RCR_CBSSID_BCN
-+		* 3. config RCR to receive different BSSID BCN or probe rsp
-+		*/
-+		rtw_write16(adapter, REG_RXFLTMAP2, value_rxfltmap2);
-+
-+		rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_ENTER);
-+
-+		/* Save orignal RRSR setting, only 8812 set RRSR after set ch/bw/band */
-+		#if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+		hal_data->RegRRSR = rtw_read32(adapter, REG_RRSR);
-+		hal_data->RegRRSR &= 0x000FFFFF;
-+		#endif
-+
-+		#if defined(CONFIG_BEAMFORMING) && (defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A))
-+		if (IS_8812_SERIES(hal_data->version_id) || IS_8821_SERIES(hal_data->version_id)) {
-+			/* set 718[1:0]=2'b00 to avoid BF scan hang */
-+			hal_data->backup_snd_ptcl_ctrl = rtw_read8(adapter, REG_SND_PTCL_CTRL_8812A);
-+			rtw_write8(adapter, REG_SND_PTCL_CTRL_8812A, (hal_data->backup_snd_ptcl_ctrl & 0xfc));
-+		}
-+		#endif
-+
-+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
-+			StopTxBeacon(adapter);
-+	} else { /* sitesurvey done */
-+		/*
-+		* 1. enable rx data frame
-+		* 2. config RCR not to receive different BSSID BCN or probe rsp
-+		* 3. doesn't enable TSF update &  buddy TSF right now to avoid HW conflict
-+		*	 so, we enable TSF update when rx first BCN after sitesurvey done
-+		*/
-+		if (rtw_mi_check_fwstate(adapter, WIFI_ASOC_STATE | WIFI_AP_STATE | WIFI_MESH_STATE)) {
-+			/* enable to rx data frame */
-+			rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
-+		}
-+
-+		rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_DONE);
-+
-+		/* Restore orignal RRSR setting,only 8812 set RRSR after set ch/bw/band */
-+		#if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+			rtw_phydm_set_rrsr(adapter, hal_data->RegRRSR, TRUE);
-+		#endif
-+
-+		#if defined(CONFIG_BEAMFORMING) && (defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A))
-+		if (IS_8812_SERIES(hal_data->version_id) || IS_8821_SERIES(hal_data->version_id)) {
-+			/* Restore orignal 0x718 setting*/
-+			rtw_write8(adapter, REG_SND_PTCL_CTRL_8812A, hal_data->backup_snd_ptcl_ctrl);
-+		}
-+		#endif
-+
-+		#ifdef CONFIG_AP_MODE
-+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
-+			ResumeTxBeacon(adapter);
-+			rtw_mi_tx_beacon_hdl(adapter);
-+		}
-+		#endif
-+	}
-+}
-+
-+#ifndef CONFIG_HAS_HW_VAR_MLME_JOIN
-+static void hw_var_set_mlme_join(_adapter *adapter, u8 type)
-+{
-+	u8 val8;
-+	u16 val16;
-+	u32 val32;
-+	u8 RetryLimit = RL_VAL_STA;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (type == 0) {
-+		/* prepare to join */
-+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
-+			StopTxBeacon(adapter);
-+
-+		/* enable to rx data frame.Accept all data frame */
-+		rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
-+
-+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
-+			RetryLimit = (hal_data->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA;
-+		else /* Ad-hoc Mode */
-+			RetryLimit = RL_VAL_AP;
-+
-+		rtw_iface_enable_tsf_update(adapter);
-+
-+	} else if (type == 1) {
-+		/* joinbss_event call back when join res < 0 */
-+		if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)
-+			rtw_write16(adapter, REG_RXFLTMAP2, 0x00);
-+
-+		rtw_iface_disable_tsf_update(adapter);
-+
-+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
-+			ResumeTxBeacon(adapter);
-+
-+			/* reset TSF 1/2 after ResumeTxBeacon */
-+			rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1) | BIT(0));
-+		}
-+
-+	} else if (type == 2) {
-+		/* sta add event call back */
-+		if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
-+			/* fixed beacon issue for 8191su........... */
-+			rtw_write8(adapter, 0x542 , 0x02);
-+			RetryLimit = RL_VAL_AP;
-+		}
-+
-+		if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
-+			ResumeTxBeacon(adapter);
-+
-+			/* reset TSF 1/2 after ResumeTxBeacon */
-+			rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1) | BIT(0));
-+		}
-+	}
-+
-+	val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);
-+	rtw_write16(adapter, REG_RETRY_LIMIT, val16);
-+#else /* !CONFIG_CONCURRENT_MODE */
-+	if (type == 0) { /* prepare to join */
-+		/* enable to rx data frame.Accept all data frame */
-+		rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
-+
-+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
-+			RetryLimit = (hal_data->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA;
-+		else /* Ad-hoc Mode */
-+			RetryLimit = RL_VAL_AP;
-+
-+		rtw_iface_enable_tsf_update(adapter);
-+
-+	} else if (type == 1) { /* joinbss_event call back when join res < 0 */
-+		rtw_write16(adapter, REG_RXFLTMAP2, 0x00);
-+
-+		rtw_iface_disable_tsf_update(adapter);
-+
-+	} else if (type == 2) { /* sta add event call back */
-+		if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE))
-+			RetryLimit = RL_VAL_AP;
-+	}
-+
-+	val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);
-+	rtw_write16(adapter, REG_RETRY_LIMIT, val16);
-+#endif /* !CONFIG_CONCURRENT_MODE */
-+}
-+#endif
-+
-+#ifdef CONFIG_TSF_RESET_OFFLOAD
-+static int rtw_hal_h2c_reset_tsf(_adapter *adapter, u8 reset_port)
-+{
-+	u8 buf[2];
-+	int ret;
-+
-+	if (reset_port == HW_PORT0) {
-+		buf[0] = 0x1;
-+		buf[1] = 0;
-+	} else {
-+		buf[0] = 0x0;
-+		buf[1] = 0x1;
-+	}
-+
-+	ret = rtw_hal_fill_h2c_cmd(adapter, H2C_RESET_TSF, 2, buf);
-+
-+	return ret;
-+}
-+
-+int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port)
-+{
-+	u8 reset_cnt_before = 0, reset_cnt_after = 0, loop_cnt = 0;
-+	u32 reg_reset_tsf_cnt = (reset_port == HW_PORT0) ?
-+				REG_FW_RESET_TSF_CNT_0 : REG_FW_RESET_TSF_CNT_1;
-+	int ret;
-+
-+	/* site survey will cause reset tsf fail */
-+	rtw_mi_buddy_scan_abort(adapter, _FALSE);
-+	reset_cnt_after = reset_cnt_before = rtw_read8(adapter, reg_reset_tsf_cnt);
-+	ret = rtw_hal_h2c_reset_tsf(adapter, reset_port);
-+	if (ret != _SUCCESS)
-+		return ret;
-+
-+	while ((reset_cnt_after == reset_cnt_before) && (loop_cnt < 10)) {
-+		rtw_msleep_os(100);
-+		loop_cnt++;
-+		reset_cnt_after = rtw_read8(adapter, reg_reset_tsf_cnt);
-+	}
-+
-+	return (loop_cnt >= 10) ? _FAIL : _SUCCESS;
-+}
-+#endif /* CONFIG_TSF_RESET_OFFLOAD */
-+
-+#ifndef CONFIG_HAS_HW_VAR_CORRECT_TSF
-+#ifdef CONFIG_HW_P0_TSF_SYNC
-+#ifdef CONFIG_CONCURRENT_MODE
-+static void hw_port0_tsf_sync_sel(_adapter *adapter, u8 benable, u8 hw_port, u16 tr_offset)
-+{
-+	u8 val8;
-+	u8 client_id = 0;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(adapter) && (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))) {
-+		RTW_INFO("[MCC] do not set HW TSF sync\n");
-+		return;
-+	}
-+#endif
-+	/* check if port0 is already synced */
-+	if (benable && dvobj->p0_tsf.sync_port != MAX_HW_PORT && dvobj->p0_tsf.sync_port == hw_port) {
-+		RTW_WARN(FUNC_ADPT_FMT ": port0 already enable TSF sync(%d)\n",
-+			FUNC_ADPT_ARG(adapter), dvobj->p0_tsf.sync_port);
-+		return;
-+	}
-+
-+	/* check if port0 already disable sync */
-+	if (!benable && dvobj->p0_tsf.sync_port == MAX_HW_PORT) {
-+		RTW_WARN(FUNC_ADPT_FMT ": port0 already disable TSF sync\n", FUNC_ADPT_ARG(adapter));
-+		return;
-+	}
-+
-+	/* check if port0 sync to port0 */
-+	if (benable && hw_port == HW_PORT0) {
-+		RTW_ERR(FUNC_ADPT_FMT ": hw_port is port0 under enable\n", FUNC_ADPT_ARG(adapter));
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	/*0x5B4 [6:4] :SYNC_CLI_SEL - The selector for the CLINT port of sync tsft source for port 0*/
-+	/*	Bit[5:4] : 0 for clint0, 1 for clint1, 2 for clint2, 3 for clint3.
-+		Bit6 : 1= enable sync to port 0. 0=disable sync to port 0.*/
-+
-+	val8 = rtw_read8(adapter, REG_TIMER0_SRC_SEL);
-+
-+	if (benable) {
-+		/*Disable Port0's beacon function*/
-+		rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL) & ~BIT_EN_BCN_FUNCTION);
-+
-+		/*Reg 0x518[15:0]: TSFTR_SYN_OFFSET*/
-+		if (tr_offset)
-+			rtw_write16(adapter, REG_TSFTR_SYN_OFFSET, tr_offset);
-+
-+		/*reg 0x577[6]=1*/	/*auto sync by tbtt*/
-+		rtw_write8(adapter, REG_MISC_CTRL, rtw_read8(adapter, REG_MISC_CTRL) | BIT_AUTO_SYNC_BY_TBTT);
-+
-+		if (HW_PORT1 == hw_port)
-+			client_id = 0;
-+		else if (HW_PORT2 == hw_port)
-+			client_id = 1;
-+		else if (HW_PORT3 == hw_port)
-+			client_id = 2;
-+		else if (HW_PORT4 == hw_port)
-+			client_id = 3;
-+
-+		val8 &= 0x8F;
-+		val8 |= (BIT(6) | (client_id << 4));
-+
-+		dvobj->p0_tsf.sync_port = hw_port;
-+		dvobj->p0_tsf.offset = tr_offset;
-+		rtw_write8(adapter, REG_TIMER0_SRC_SEL, val8);
-+
-+		/*Enable Port0's beacon function*/
-+		rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL)  | BIT_EN_BCN_FUNCTION);
-+		RTW_INFO("%s Port_%d TSF sync to P0, timer offset :%d\n", __func__, hw_port, tr_offset);
-+	} else {
-+		val8 &= ~BIT(6);
-+
-+		dvobj->p0_tsf.sync_port = MAX_HW_PORT;
-+		dvobj->p0_tsf.offset = 0;
-+		rtw_write8(adapter, REG_TIMER0_SRC_SEL, val8);
-+		RTW_INFO("%s P0 TSF sync disable\n", __func__);
-+	}
-+}
-+static _adapter * _search_ld_sta(_adapter *adapter, u8 include_self)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	u8 i;
-+	_adapter *iface = NULL;
-+
-+	if (rtw_mi_get_assoced_sta_num(adapter) == 0) {
-+		RTW_ERR("STA_LD_NUM == 0\n");
-+		rtw_warn_on(1);
-+	}
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+		if (include_self == _FALSE && adapter == iface)
-+			continue;
-+		if (is_client_associated_to_ap(iface))
-+			break;
-+	}
-+	if (iface)
-+		RTW_INFO("search STA iface -"ADPT_FMT"\n", ADPT_ARG(iface));
-+	return iface;
-+}
-+#endif /*CONFIG_CONCURRENT_MODE*/
-+/*Correct port0's TSF*/
-+/*#define DBG_P0_TSF_SYNC*/
-+void hw_var_set_correct_tsf(PADAPTER adapter, u8 mlme_state)
-+{
-+#ifdef CONFIG_CONCURRENT_MODE
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	_adapter *sta_if = NULL;
-+	u8 hw_port;
-+
-+	RTW_INFO(FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(adapter));
-+	#ifdef DBG_P0_TSF_SYNC
-+	RTW_INFO("[TSF_SYNC] AP_NUM = %d\n", rtw_mi_get_ap_num(adapter));
-+	RTW_INFO("[TSF_SYNC] MESH_NUM = %d\n", rtw_mi_get_mesh_num(adapter));
-+	RTW_INFO("[TSF_SYNC] LD_STA_NUM = %d\n", rtw_mi_get_assoced_sta_num(adapter));
-+	if (dvobj->p0_tsf.sync_port == MAX_HW_PORT)
-+		RTW_INFO("[TSF_SYNC] org p0 sync port = N/A\n");
-+	else
-+		RTW_INFO("[TSF_SYNC] org p0 sync port = %d\n", dvobj->p0_tsf.sync_port);
-+	RTW_INFO("[TSF_SYNC] timer offset = %d\n", dvobj->p0_tsf.offset);
-+	#endif
-+	switch (mlme_state) {
-+		case MLME_STA_CONNECTED :
-+			{
-+				hw_port = rtw_hal_get_port(adapter);
-+
-+				if (!MLME_IS_STA(adapter)) {
-+					RTW_ERR("STA CON state,but iface("ADPT_FMT") is not STA\n", ADPT_ARG(adapter));
-+					rtw_warn_on(1);
-+				}
-+
-+				if ((dvobj->p0_tsf.sync_port != MAX_HW_PORT) && (hw_port == HW_PORT0)) {
-+					RTW_ERR(ADPT_FMT" is STA with P0 connected => DIS P0_TSF_SYNC\n", ADPT_ARG(adapter));
-+					rtw_warn_on(1);
-+					hw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0);
-+				}
-+
-+				if ((dvobj->p0_tsf.sync_port == MAX_HW_PORT) &&
-+					(rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))) {
-+					hw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/
-+					#ifdef DBG_P0_TSF_SYNC
-+					RTW_INFO("[TSF_SYNC] STA_LINKED => EN P0_TSF_SYNC\n");
-+					#endif
-+				}
-+			}
-+			break;
-+		case MLME_STA_DISCONNECTED :
-+			{
-+				hw_port = rtw_hal_get_port(adapter);
-+
-+				if (!MLME_IS_STA(adapter)) {
-+					RTW_ERR("STA DIS_CON state,but iface("ADPT_FMT") is not STA\n", ADPT_ARG(adapter));
-+					rtw_warn_on(1);
-+				}
-+
-+				if (dvobj->p0_tsf.sync_port == hw_port) {
-+					if (rtw_mi_get_assoced_sta_num(adapter) >= 2) {
-+						/* search next appropriate sta*/
-+						sta_if = _search_ld_sta(adapter, _FALSE);
-+						if (sta_if) {
-+							hw_port = rtw_hal_get_port(sta_if);
-+							hw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/
-+							#ifdef DBG_P0_TSF_SYNC
-+							RTW_INFO("[TSF_SYNC] STA_DIS_CON => CHANGE P0_TSF_SYNC\n");
-+							#endif
-+						}
-+					} else if (rtw_mi_get_assoced_sta_num(adapter) == 1) {
-+						hw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0);
-+						#ifdef DBG_P0_TSF_SYNC
-+						RTW_INFO("[TSF_SYNC] STA_DIS_CON => DIS P0_TSF_SYNC\n");
-+						#endif
-+					}
-+				}
-+			}
-+			break;
-+#ifdef CONFIG_AP_MODE
-+		case MLME_AP_STARTED :
-+		case MLME_MESH_STARTED :
-+			{
-+				if (!(MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))) {
-+					RTW_ERR("AP START state,but iface("ADPT_FMT") is not AP\n", ADPT_ARG(adapter));
-+					rtw_warn_on(1);
-+				}
-+
-+				if ((dvobj->p0_tsf.sync_port == MAX_HW_PORT) &&
-+					rtw_mi_get_assoced_sta_num(adapter)) {
-+					/* get port of sta */
-+					sta_if = _search_ld_sta(adapter, _FALSE);
-+					if (sta_if) {
-+						hw_port = rtw_hal_get_port(sta_if);
-+						hw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/
-+						#ifdef DBG_P0_TSF_SYNC
-+						RTW_INFO("[TSF_SYNC] AP_START => EN P0_TSF_SYNC\n");
-+						#endif
-+					}
-+				}
-+			}
-+			break;
-+		case MLME_AP_STOPPED :
-+		case MLME_MESH_STOPPED :
-+			{
-+				if (!(MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))) {
-+					RTW_ERR("AP START state,but iface("ADPT_FMT") is not AP\n", ADPT_ARG(adapter));
-+					rtw_warn_on(1);
-+				}
-+				/*stop ap mode*/
-+				if ((rtw_mi_get_ap_num(adapter) + rtw_mi_get_mesh_num(adapter) == 1) &&
-+					(dvobj->p0_tsf.sync_port != MAX_HW_PORT)) {
-+					hw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0);
-+					#ifdef DBG_P0_TSF_SYNC
-+					RTW_INFO("[TSF_SYNC] AP_STOP => DIS P0_TSF_SYNC\n");
-+					#endif
-+				}
-+			}
-+			break;
-+#endif /* CONFIG_AP_MODE */
-+		default :
-+			RTW_ERR(FUNC_ADPT_FMT" unknow state(0x%02x)\n", FUNC_ADPT_ARG(adapter), mlme_state);
-+			break;
-+	}
-+
-+	/*#ifdef DBG_P0_TSF_SYNC*/
-+	#if 1
-+	if (dvobj->p0_tsf.sync_port == MAX_HW_PORT)
-+		RTW_INFO("[TSF_SYNC] p0 sync port = N/A\n");
-+	else
-+		RTW_INFO("[TSF_SYNC] p0 sync port = %d\n", dvobj->p0_tsf.sync_port);
-+	RTW_INFO("[TSF_SYNC] timer offset = %d\n", dvobj->p0_tsf.offset);
-+	#endif
-+#endif /*CONFIG_CONCURRENT_MODE*/
-+}
-+
-+#else /*! CONFIG_HW_P0_TSF_SYNC*/
-+
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+static void hw_var_set_correct_tsf(_adapter *adapter, u8 mlme_state)
-+{
-+	/*do nothing*/
-+}
-+#else /* !CONFIG_MI_WITH_MBSSID_CAM*/
-+static void rtw_hal_correct_tsf(_adapter *padapter, u8 hw_port, u64 tsf)
-+{
-+	if (hw_port == HW_PORT0) {
-+		/*disable related TSF function*/
-+		rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) & (~EN_BCN_FUNCTION));
-+#if defined(CONFIG_RTL8192F)
-+		rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,
-+					REG_WLAN_ACT_MASK_CTRL_1) & ~EN_PORT_0_FUNCTION);
-+#endif
-+
-+		rtw_write32(padapter, REG_TSFTR, tsf);
-+		rtw_write32(padapter, REG_TSFTR + 4, tsf >> 32);
-+
-+		/*enable related TSF function*/
-+		rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) | EN_BCN_FUNCTION);
-+#if defined(CONFIG_RTL8192F)
-+		rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,
-+					REG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_0_FUNCTION);
-+#endif
-+	} else if (hw_port == HW_PORT1) {
-+		/*disable related TSF function*/
-+		rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) & (~EN_BCN_FUNCTION));
-+#if defined(CONFIG_RTL8192F)
-+		rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,
-+					REG_WLAN_ACT_MASK_CTRL_1) & ~EN_PORT_1_FUNCTION);
-+#endif
-+
-+		rtw_write32(padapter, REG_TSFTR1, tsf);
-+		rtw_write32(padapter, REG_TSFTR1 + 4, tsf >> 32);
-+
-+		/*enable related TSF function*/
-+		rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) | EN_BCN_FUNCTION);
-+#if defined(CONFIG_RTL8192F)
-+		rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter,
-+					REG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_1_FUNCTION);
-+#endif
-+	} else
-+		RTW_INFO("%s-[WARN] "ADPT_FMT" invalid hw_port:%d\n", __func__, ADPT_ARG(padapter), hw_port);
-+}
-+static void hw_var_set_correct_tsf(_adapter *adapter, u8 mlme_state)
-+{
-+	u64 tsf;
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);
-+
-+	tsf = mlmeext->TSFValue - rtw_modular64(mlmeext->TSFValue, (mlmeinfo->bcn_interval * 1024)) - 1024; /*us*/
-+
-+	if ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE
-+		|| (mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)
-+		StopTxBeacon(adapter);
-+
-+	rtw_hal_correct_tsf(adapter, adapter->hw_port, tsf);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	/* Update buddy port's TSF if it is SoftAP/Mesh for beacon TX issue! */
-+	if ((mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE
-+		&& (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
-+	) {
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+		int i;
-+		_adapter *iface;
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			if (!iface)
-+				continue;
-+			if (iface == adapter)
-+				continue;
-+
-+			#ifdef CONFIG_AP_MODE
-+			if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
-+				&& check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE
-+			) {
-+				rtw_hal_correct_tsf(iface, iface->hw_port, tsf);
-+				#ifdef CONFIG_TSF_RESET_OFFLOAD
-+				if (rtw_hal_reset_tsf(iface, iface->hw_port) == _FAIL)
-+					RTW_INFO("%s-[ERROR] "ADPT_FMT" Reset port%d TSF fail\n"
-+						, __func__, ADPT_ARG(iface), iface->hw_port);
-+				#endif	/* CONFIG_TSF_RESET_OFFLOAD*/
-+			}
-+			#endif /* CONFIG_AP_MODE */
-+		}
-+	}
-+#endif /* CONFIG_CONCURRENT_MODE */
-+	if ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE
-+		|| (mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)
-+		ResumeTxBeacon(adapter);
-+}
-+#endif /*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/
-+#endif /*#ifdef CONFIG_HW_P0_TSF_SYNC*/
-+#endif /*#ifndef CONFIG_HAS_HW_VAR_CORRECT_TSF*/
-+
-+u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u64 tsftr = 0;
-+
-+	if (port >= hal_spec->port_num) {
-+		RTW_ERR("%s invalid port(%d) \n", __func__, port);
-+		goto exit;
-+	}
-+
-+	switch (rtw_get_chip_type(adapter)) {
-+#if defined(CONFIG_RTL8814B)
-+	case RTL8814B:
-+	{
-+		u8 val8;
-+
-+		/* 0x1500[6:4] - BIT_BCN_TIMER_SEL_FWRD_V1 */
-+		val8 = rtw_read8(adapter, REG_PORT_CTRL_SEL);
-+		val8 &= ~0x70;
-+		val8 |= port << 4;
-+		rtw_write8(adapter, REG_PORT_CTRL_SEL, val8);
-+
-+		tsftr = rtw_read32(adapter, REG_TSFTR_HIGH);
-+		tsftr = tsftr << 32;
-+		tsftr |= rtw_read32(adapter, REG_TSFTR_LOW);
-+
-+		break;
-+	}
-+#endif
-+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)
-+	case RTL8814A:
-+	case RTL8822B:
-+	case RTL8821C:
-+	case RTL8822C:		
-+	{
-+		u8 val8;
-+
-+		/* 0x554[30:28] - BIT_BCN_TIMER_SEL_FWRD */
-+		val8 = rtw_read8(adapter, REG_MBSSID_BCN_SPACE + 3);
-+		val8 &= 0x8F;
-+		val8 |= port << 4;
-+		rtw_write8(adapter, REG_MBSSID_BCN_SPACE + 3, val8);
-+
-+		tsftr = rtw_read32(adapter, REG_TSFTR + 4);
-+		tsftr = tsftr << 32;
-+		tsftr |= rtw_read32(adapter, REG_TSFTR);
-+
-+		break;
-+	}
-+#endif
-+#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) \
-+		|| defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8192F) \
-+		|| defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D) \
-+		|| defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) \
-+		|| defined(CONFIG_RTL8710B)
-+	case RTL8188E:
-+	case RTL8188F:
-+	case RTL8188GTV:
-+	case RTL8192E:
-+	case RTL8192F:
-+	case RTL8723B:
-+	case RTL8703B:
-+	case RTL8723D:
-+	case RTL8812:
-+	case RTL8821:
-+	case RTL8710B:
-+	{
-+		u32 addr;
-+
-+		if (port == HW_PORT0)
-+			addr = REG_TSFTR;
-+		else if (port == HW_PORT1)
-+			addr = REG_TSFTR1;
-+		else {
-+			RTW_ERR("%s unknown port(%d) \n", __func__, port);
-+			goto exit;
-+		}
-+
-+		tsftr = rtw_read32(adapter, addr + 4);
-+		tsftr = tsftr << 32;
-+		tsftr |= rtw_read32(adapter, addr);
-+
-+		break;
-+	}
-+#endif
-+	default:
-+		RTW_ERR("%s unknow chip type\n", __func__);
-+	}
-+
-+exit:
-+	return tsftr;
-+}
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_TDLS_CH_SW
-+s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode)
-+{
-+	PHAL_DATA_TYPE	pHalData =  GET_HAL_DATA(padapter);
-+	u8 ch_sw_h2c_buf[4] = {0x00, 0x00, 0x00, 0x00};
-+
-+
-+	SET_H2CCMD_CH_SW_OPER_OFFLOAD_CH_NUM(ch_sw_h2c_buf, channel);
-+	SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_MODE(ch_sw_h2c_buf, bwmode);
-+	switch (bwmode) {
-+	case CHANNEL_WIDTH_40:
-+		SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_40M_SC(ch_sw_h2c_buf, channel_offset);
-+		break;
-+	case CHANNEL_WIDTH_80:
-+		SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(ch_sw_h2c_buf, channel_offset);
-+		break;
-+	case CHANNEL_WIDTH_20:
-+	default:
-+		break;
-+	}
-+	SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(ch_sw_h2c_buf, pHalData->rfe_type);
-+
-+	return rtw_hal_fill_h2c_cmd(padapter, H2C_CHNL_SWITCH_OPER_OFFLOAD, sizeof(ch_sw_h2c_buf), ch_sw_h2c_buf);
-+}
-+#endif
-+#endif
-+
-+#ifdef CONFIG_WMMPS_STA
-+void rtw_hal_update_uapsd_tid(_adapter *adapter)
-+{
-+	struct mlme_priv		*pmlmepriv = &adapter->mlmepriv;
-+	struct qos_priv		*pqospriv = &pmlmepriv->qospriv;
-+
-+	/* write complement of pqospriv->uapsd_tid to mac register 0x693 because 
-+	    it's designed  for "0" represents "enable" and "1" represents "disable" */
-+	rtw_write8(adapter, REG_WMMPS_UAPSD_TID, (u8)(~pqospriv->uapsd_tid));
-+}
-+#endif /* CONFIG_WMMPS_STA */
-+
-+#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
-+/* For multi-port support, driver needs to inform the port ID to FW for btc operations */
-+s32 rtw_hal_set_wifi_btc_port_id_cmd(_adapter *adapter)
-+{
-+	u8 h2c_buf[H2C_BTC_WL_PORT_ID_LEN] = {0};
-+	u8 hw_port = rtw_hal_get_port(adapter);
-+
-+	SET_H2CCMD_BTC_WL_PORT_ID(h2c_buf, hw_port);
-+	RTW_INFO("%s ("ADPT_FMT") - hw_port :%d\n", __func__, ADPT_ARG(adapter), hw_port);
-+	return rtw_hal_fill_h2c_cmd(adapter, H2C_BTC_WL_PORT_ID, H2C_BTC_WL_PORT_ID_LEN, h2c_buf);
-+}
-+#endif
-+
-+#define LPS_ACTIVE_TIMEOUT	50 /*number of times*/
-+void rtw_lps_state_chk(_adapter *adapter, u8 ps_mode)
-+{
-+	struct pwrctrl_priv 		*pwrpriv = adapter_to_pwrctl(adapter);
-+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct sta_priv		*pstapriv = &adapter->stapriv;
-+	struct sta_info		*psta = NULL;
-+	u8 ps_ready = _FALSE;
-+	s8 leave_wait_count = LPS_ACTIVE_TIMEOUT;
-+
-+	if (ps_mode == PS_MODE_ACTIVE) {
-+#ifdef CONFIG_LPS_ACK
-+		if (rtw_sctx_wait(&pwrpriv->lps_ack_sctx, __func__)) {
-+			if (pwrpriv->lps_ack_status > 0) {
-+				psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
-+				if (psta != NULL) {
-+					if(issue_nulldata(adapter, psta->cmn.mac_addr, PS_MODE_ACTIVE, 3, 1) == _FAIL)
-+						RTW_INFO(FUNC_ADPT_FMT" LPS state sync not yet finished.\n", FUNC_ADPT_ARG(adapter));
-+				}
-+			}
-+		} else {
-+			RTW_WARN("LPS sctx query timeout, operation abort!!\n");
-+			return;
-+		}
-+		pwrpriv->lps_ack_status = -1;
-+#else
-+		do {
-+			if ((rtw_read8(adapter, REG_TCR) & BIT_PWRBIT_OW_EN) == 0) {
-+				ps_ready = _TRUE;
-+				break;
-+			}
-+			rtw_msleep_os(1);
-+		} while (leave_wait_count--);
-+
-+		if (ps_ready == _FALSE) {
-+			RTW_WARN(FUNC_ADPT_FMT" Power Bit Control is still in HW!\n", FUNC_ADPT_ARG(adapter));
-+			return;
-+		}
-+#endif /* CONFIG_LPS_ACK */
-+		}
-+	}
-+
-+void rtw_var_set_basic_rate(PADAPTER padapter, u8 *val) {
-+
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	struct mlme_ext_info *mlmext_info = &padapter->mlmeextpriv.mlmext_info;
-+	u16 input_b = 0, masked = 0, ioted = 0, BrateCfg = 0;
-+	u16 rrsr_2g_force_mask = RRSR_CCK_RATES;
-+	u16 rrsr_2g_allow_mask = (RRSR_24M | RRSR_12M | RRSR_6M | RRSR_CCK_RATES);
-+	#if CONFIG_IEEE80211_BAND_5GHZ
-+	u16 rrsr_5g_force_mask = (RRSR_6M);
-+	u16 rrsr_5g_allow_mask = (RRSR_OFDM_RATES);
-+	#endif
-+	u32 temp_RRSR;
-+
-+	HalSetBrateCfg(padapter, val, &BrateCfg);
-+	input_b = BrateCfg;
-+
-+	/* apply force and allow mask */
-+	#if CONFIG_IEEE80211_BAND_5GHZ
-+	if (pHalData->current_band_type != BAND_ON_2_4G) {
-+		BrateCfg |= rrsr_5g_force_mask;
-+		BrateCfg &= rrsr_5g_allow_mask;
-+	} else
-+	#endif
-+	{ /* 2.4G */
-+		BrateCfg |= rrsr_2g_force_mask;
-+		BrateCfg &= rrsr_2g_allow_mask;
-+	}
-+	masked = BrateCfg;
-+
-+#ifdef CONFIG_CMCC_TEST
-+	BrateCfg |= (RRSR_11M | RRSR_5_5M | RRSR_1M); /* use 11M to send ACK */
-+	BrateCfg |= (RRSR_24M | RRSR_18M | RRSR_12M); /*CMCC_OFDM_ACK 12/18/24M */
-+#endif
-+
-+	/* IOT consideration */
-+	if (mlmext_info->assoc_AP_vendor == HT_IOT_PEER_CISCO) {
-+		/* if peer is cisco and didn't use ofdm rate, we enable 6M ack */
-+		if ((BrateCfg & (RRSR_24M | RRSR_12M | RRSR_6M)) == 0)
-+			BrateCfg |= RRSR_6M;
-+	}
-+		ioted = BrateCfg;
-+
-+#ifdef CONFIG_NARROWBAND_SUPPORTING
-+	if ((padapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_10)
-+		|| (padapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_5)) {
-+		BrateCfg &= ~RRSR_CCK_RATES;
-+		BrateCfg |= RRSR_6M;
-+	}
-+#endif
-+	pHalData->BasicRateSet = BrateCfg;
-+
-+	RTW_INFO("HW_VAR_BASIC_RATE: %#x->%#x->%#x\n", input_b, masked, ioted);
-+
-+	/* Set RRSR rate table. */
-+		temp_RRSR = rtw_read32(padapter, REG_RRSR);
-+		temp_RRSR &=0xFFFF0000;
-+		temp_RRSR |=BrateCfg;
-+		rtw_phydm_set_rrsr(padapter, temp_RRSR, TRUE);
-+
-+	rtw_write8(padapter, REG_RRSR + 2, rtw_read8(padapter, REG_RRSR + 2) & 0xf0);
-+
-+	#if defined(CONFIG_RTL8188E)
-+	rtw_hal_set_hwreg(padapter, HW_VAR_INIT_RTS_RATE, (u8 *)&BrateCfg);
-+	#endif
-+}
-+
-+u8 SetHwReg(_adapter *adapter, u8 variable, u8 *val)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u8 ret = _SUCCESS;
-+
-+	switch (variable) {
-+	case HW_VAR_MEDIA_STATUS: {
-+		u8 net_type = *((u8 *)val);
-+
-+		rtw_hal_set_msr(adapter, net_type);
-+	}
-+	break;
-+	case HW_VAR_DO_IQK:
-+		if (*val)
-+			hal_data->bNeedIQK = _TRUE;
-+		else
-+			hal_data->bNeedIQK = _FALSE;
-+		break;
-+	case HW_VAR_MAC_ADDR:
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+		rtw_hal_set_macaddr_mbid(adapter, val);
-+#else
-+		rtw_hal_set_macaddr_port(adapter, val);
-+#endif
-+		break;
-+	case HW_VAR_BSSID:
-+		rtw_hal_set_bssid(adapter, val);
-+		break;
-+	case HW_VAR_RCR:
-+		ret = hw_var_rcr_config(adapter, *((u32 *)val));
-+		break;
-+	case HW_VAR_ON_RCR_AM:
-+		hw_var_set_rcr_am(adapter, 1);
-+		break;
-+	case HW_VAR_OFF_RCR_AM:
-+		hw_var_set_rcr_am(adapter, 0);
-+		break;
-+	case HW_VAR_BEACON_INTERVAL:
-+		hw_var_set_bcn_interval(adapter, *(u16 *)val);
-+		break;
-+#ifdef CONFIG_MBSSID_CAM
-+	case HW_VAR_MBSSID_CAM_WRITE: {
-+		u32	cmd = 0;
-+		u32	*cam_val = (u32 *)val;
-+
-+		rtw_write32(adapter, REG_MBIDCAMCFG_1, cam_val[0]);
-+		cmd = BIT_MBIDCAM_POLL | BIT_MBIDCAM_WT_EN | BIT_MBIDCAM_VALID | cam_val[1];
-+		rtw_write32(adapter, REG_MBIDCAMCFG_2, cmd);
-+	}
-+		break;
-+	case HW_VAR_MBSSID_CAM_CLEAR: {
-+		u32 cmd;
-+		u8 entry_id = *(u8 *)val;
-+
-+		rtw_write32(adapter, REG_MBIDCAMCFG_1, 0);
-+
-+		cmd = BIT_MBIDCAM_POLL | BIT_MBIDCAM_WT_EN | ((entry_id & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT);
-+		rtw_write32(adapter, REG_MBIDCAMCFG_2, cmd);
-+	}
-+		break;
-+	case HW_VAR_RCR_MBSSID_EN:
-+		if (*((u8 *)val))
-+			rtw_hal_rcr_add(adapter, RCR_ENMBID);
-+		else
-+			rtw_hal_rcr_clear(adapter, RCR_ENMBID);
-+		break;
-+#endif
-+	case HW_VAR_PORT_SWITCH:
-+		hw_var_port_switch(adapter);
-+		break;
-+	case HW_VAR_INIT_RTS_RATE: {
-+		u16 brate_cfg = *((u16 *)val);
-+		u8 rate_index = 0;
-+		HAL_VERSION *hal_ver = &hal_data->version_id;
-+
-+		if (IS_8188E(*hal_ver)) {
-+
-+			while (brate_cfg > 0x1) {
-+				brate_cfg = (brate_cfg >> 1);
-+				rate_index++;
-+			}
-+			rtw_write8(adapter, REG_INIRTS_RATE_SEL, rate_index);
-+		} else
-+			rtw_warn_on(1);
-+	}
-+		break;
-+	case HW_VAR_SEC_CFG: {
-+		u16 reg_scr_ori;
-+		u16 reg_scr;
-+
-+		reg_scr = reg_scr_ori = rtw_read16(adapter, REG_SECCFG);
-+		reg_scr |= (SCR_CHK_KEYID | SCR_RxDecEnable | SCR_TxEncEnable);
-+
-+		if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC))
-+			reg_scr |= SCR_CHK_BMC;
-+
-+		if (_rtw_camctl_chk_flags(adapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH))
-+			reg_scr |= SCR_NoSKMC;
-+
-+		if (reg_scr != reg_scr_ori)
-+			rtw_write16(adapter, REG_SECCFG, reg_scr);
-+	}
-+		break;
-+	case HW_VAR_SEC_DK_CFG: {
-+		struct security_priv *sec = &adapter->securitypriv;
-+		u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
-+
-+		if (val) { /* Enable default key related setting */
-+			reg_scr |= SCR_TXBCUSEDK;
-+			if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
-+				reg_scr |= (SCR_RxUseDK | SCR_TxUseDK);
-+		} else /* Disable default key related setting */
-+			reg_scr &= ~(SCR_RXBCUSEDK | SCR_TXBCUSEDK | SCR_RxUseDK | SCR_TxUseDK);
-+
-+		rtw_write8(adapter, REG_SECCFG, reg_scr);
-+	}
-+		break;
-+
-+	case HW_VAR_ASIX_IOT:
-+		/* enable  ASIX IOT function */
-+		if (*((u8 *)val) == _TRUE) {
-+			/* 0xa2e[0]=0 (disable rake receiver) */
-+			rtw_write8(adapter, rCCK0_FalseAlarmReport + 2,
-+				rtw_read8(adapter, rCCK0_FalseAlarmReport + 2) & ~(BIT0));
-+			/* 0xa1c=0xa0 (reset channel estimation if signal quality is bad) */
-+			rtw_write8(adapter, rCCK0_DSPParameter2, 0xa0);
-+		} else {
-+			/* restore reg:0xa2e,   reg:0xa1c */
-+			rtw_write8(adapter, rCCK0_FalseAlarmReport + 2,
-+				rtw_read8(adapter, rCCK0_FalseAlarmReport + 2) | (BIT0));
-+			rtw_write8(adapter, rCCK0_DSPParameter2, 0x00);
-+		}
-+		break;
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+	case HW_VAR_WOWLAN: {
-+		struct wowlan_ioctl_param *poidparam;
-+
-+		poidparam = (struct wowlan_ioctl_param *)val;
-+		switch (poidparam->subcode) {
-+#ifdef CONFIG_WOWLAN
-+		case WOWLAN_PATTERN_CLEAN:
-+			rtw_hal_dl_pattern(adapter, 2);
-+			break;
-+		case WOWLAN_ENABLE:
-+			rtw_hal_wow_enable(adapter);
-+			break;
-+		case WOWLAN_DISABLE:
-+			rtw_hal_wow_disable(adapter);
-+			break;
-+#endif /*CONFIG_WOWLAN*/
-+#ifdef CONFIG_AP_WOWLAN
-+		case WOWLAN_AP_ENABLE:
-+			rtw_hal_ap_wow_enable(adapter);
-+			break;
-+		case WOWLAN_AP_DISABLE:
-+			rtw_hal_ap_wow_disable(adapter);
-+			break;
-+#endif /*CONFIG_AP_WOWLAN*/
-+		default:
-+			break;
-+		}
-+	}
-+		break;
-+#endif /*defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)*/
-+
-+#ifndef CONFIG_HAS_HW_VAR_BCN_FUNC
-+	case HW_VAR_BCN_FUNC:
-+		hw_var_set_bcn_func(adapter, *val);
-+		break;
-+#endif
-+
-+#ifndef CONFIG_HAS_HW_VAR_MLME_DISCONNECT
-+	case HW_VAR_MLME_DISCONNECT:
-+		hw_var_set_mlme_disconnect(adapter);
-+		break;
-+#endif
-+
-+	case HW_VAR_MLME_SITESURVEY:
-+		hw_var_set_mlme_sitesurvey(adapter, *val);
-+		#ifdef CONFIG_BT_COEXIST
-+		if (hal_data->EEPROMBluetoothCoexist == 1)
-+			rtw_btcoex_ScanNotify(adapter, *val ? _TRUE : _FALSE);
-+		#endif
-+		break;
-+
-+#ifndef CONFIG_HAS_HW_VAR_MLME_JOIN
-+	case HW_VAR_MLME_JOIN:
-+		hw_var_set_mlme_join(adapter, *val);
-+		break;
-+#endif
-+
-+	case HW_VAR_EN_HW_UPDATE_TSF:
-+		rtw_hal_set_hw_update_tsf(adapter);
-+		break;
-+#ifndef CONFIG_HAS_HW_VAR_CORRECT_TSF
-+	case HW_VAR_CORRECT_TSF:
-+		hw_var_set_correct_tsf(adapter, *val);
-+		break;
-+#endif
-+
-+#if defined(CONFIG_HW_P0_TSF_SYNC) && defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_MCC_MODE)
-+	case HW_VAR_TSF_AUTO_SYNC:
-+		if (*val == _TRUE)
-+			hw_port0_tsf_sync_sel(adapter, _TRUE, adapter->hw_port, 50);
-+		else
-+			hw_port0_tsf_sync_sel(adapter, _FALSE, adapter->hw_port, 50);
-+		break;
-+#endif
-+	case HW_VAR_APFM_ON_MAC:
-+		hal_data->bMacPwrCtrlOn = *val;
-+		RTW_INFO("%s: bMacPwrCtrlOn=%d\n", __func__, hal_data->bMacPwrCtrlOn);
-+		break;
-+#ifdef CONFIG_WMMPS_STA
-+	case  HW_VAR_UAPSD_TID:
-+		rtw_hal_update_uapsd_tid(adapter);
-+		break;
-+#endif /* CONFIG_WMMPS_STA */
-+#ifdef CONFIG_LPS_PG
-+	case HW_VAR_LPS_PG_HANDLE:
-+		rtw_hal_lps_pg_handler(adapter, *val);
-+		break;
-+#endif
-+#ifdef CONFIG_LPS_LCLK_WD_TIMER
-+	case HW_VAR_DM_IN_LPS_LCLK:
-+		rtw_phydm_wd_lps_lclk_hdl(adapter);
-+		break;
-+#endif
-+	case HW_VAR_ENABLE_RX_BAR:
-+		if (*val == _TRUE) {
-+			/* enable RX BAR */
-+			u16 val16 = rtw_read16(adapter, REG_RXFLTMAP1);
-+
-+			val16 |= BIT(8);
-+			rtw_write16(adapter, REG_RXFLTMAP1, val16);
-+		} else {
-+			/* disable RX BAR */
-+			u16 val16 = rtw_read16(adapter, REG_RXFLTMAP1);
-+
-+			val16 &= (~BIT(8));
-+			rtw_write16(adapter, REG_RXFLTMAP1, val16);
-+		}
-+		RTW_INFO("[HW_VAR_ENABLE_RX_BAR] 0x%02X=0x%02X\n",
-+			REG_RXFLTMAP1, rtw_read16(adapter, REG_RXFLTMAP1));
-+		break;
-+	case HW_VAR_HCI_SUS_STATE:
-+		hal_data->hci_sus_state = *(u8 *)val;
-+		RTW_INFO("%s: hci_sus_state=%u\n", __func__, hal_data->hci_sus_state);
-+		break;
-+#if defined(CONFIG_AP_MODE) && defined(CONFIG_FW_HANDLE_TXBCN) && defined(CONFIG_SUPPORT_MULTI_BCN)
-+		case HW_VAR_BCN_HEAD_SEL:
-+		{
-+			u8 vap_id = *(u8 *)val;
-+
-+			if ((vap_id >= CONFIG_LIMITED_AP_NUM) && (vap_id != 0xFF)) {
-+				RTW_ERR(ADPT_FMT " vap_id(%d:%d) is invalid\n", ADPT_ARG(adapter),vap_id, adapter->vap_id);
-+				rtw_warn_on(1);
-+			}
-+			if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
-+				u16 drv_pg_bndy = 0, bcn_addr = 0;
-+				u32 page_size = 0;
-+
-+				/*rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_BOUNDARY, &drv_pg_bndy);*/
-+				rtw_halmac_get_rsvd_drv_pg_bndy(adapter_to_dvobj(adapter), &drv_pg_bndy);
-+				rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&page_size);
-+
-+				if (vap_id != 0xFF)
-+					bcn_addr = drv_pg_bndy + (vap_id * (MAX_BEACON_LEN / page_size));
-+				else
-+					bcn_addr = drv_pg_bndy;
-+				RTW_INFO(ADPT_FMT" vap_id(%d) change BCN HEAD to 0x%04x\n",
-+					ADPT_ARG(adapter), vap_id, bcn_addr);
-+				rtw_write16(adapter, REG_FIFOPAGE_CTRL_2,
-+					(bcn_addr & BIT_MASK_BCN_HEAD_1_V1) | BIT_BCN_VALID_V1);
-+			}
-+		}
-+		break;
-+#endif
-+	case HW_VAR_LPS_STATE_CHK :
-+		rtw_lps_state_chk(adapter, *(u8 *)val);
-+		break;
-+
-+#ifdef CONFIG_RTS_FULL_BW
-+	case HW_VAR_SET_RTS_BW:
-+	{
-+		#ifdef RTW_HALMAC
-+			rtw_halmac_set_rts_full_bw(adapter_to_dvobj(adapter), (*val));
-+		#else
-+			u8 temp;
-+			if(*val)
-+				temp = (( rtw_read8(adapter, REG_INIRTS_RATE_SEL)) | BIT5 );
-+			else
-+				temp = (( rtw_read8(adapter, REG_INIRTS_RATE_SEL)) & (~BIT5));
-+			rtw_write8(adapter, REG_INIRTS_RATE_SEL, temp);
-+			/*RTW_INFO("HW_VAR_SET_RTS_BW	val=%u REG480=0x%x\n", *val, rtw_read8(adapter, REG_INIRTS_RATE_SEL));*/
-+		#endif
-+	}
-+	break;
-+#endif/*CONFIG_RTS_FULL_BW*/
-+#if defined(CONFIG_PCI_HCI)
-+	case HW_VAR_ENSWBCN: 
-+	if (*val == _TRUE) {
-+		rtw_write8(adapter, REG_CR + 1,
-+			   rtw_read8(adapter, REG_CR + 1) | BIT(0));
-+	} else
-+		rtw_write8(adapter, REG_CR + 1,
-+			   rtw_read8(adapter, REG_CR + 1) & ~BIT(0));
-+	break;
-+#endif
-+	case HW_VAR_BCN_EARLY_C2H_RPT:
-+		rtw_hal_set_fw_bcn_early_c2h_rpt_cmd(adapter, *(u8 *)val);
-+		break;
-+	default:
-+		if (0)
-+			RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n",
-+				  FUNC_ADPT_ARG(adapter), variable);
-+		ret = _FAIL;
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+void GetHwReg(_adapter *adapter, u8 variable, u8 *val)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u64 val64;
-+
-+
-+	switch (variable) {
-+	case HW_VAR_MAC_ADDR:
-+		#ifndef CONFIG_MI_WITH_MBSSID_CAM
-+		rtw_hal_get_macaddr_port(adapter, val);
-+		#endif
-+		break;
-+	case HW_VAR_BASIC_RATE:
-+		*((u16 *)val) = hal_data->BasicRateSet;
-+		break;
-+	case HW_VAR_MEDIA_STATUS:
-+		rtw_hal_get_msr(adapter, val);
-+		break;
-+	case HW_VAR_DO_IQK:
-+		*val = hal_data->bNeedIQK;
-+		break;
-+	case HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO:
-+		if (hal_is_band_support(adapter, BAND_ON_5G))
-+			*val = _TRUE;
-+		else
-+			*val = _FALSE;
-+		break;
-+	case HW_VAR_APFM_ON_MAC:
-+		*val = hal_data->bMacPwrCtrlOn;
-+		break;
-+	case HW_VAR_RCR:
-+		hw_var_rcr_get(adapter, (u32 *)val);
-+		break;
-+	case HW_VAR_FWLPS_RF_ON:
-+		/* When we halt NIC, we should check if FW LPS is leave. */
-+		if (rtw_is_surprise_removed(adapter)
-+			|| (adapter_to_pwrctl(adapter)->rf_pwrstate == rf_off)
-+		) {
-+			/*
-+			 * If it is in HW/SW Radio OFF or IPS state,
-+			 * we do not check Fw LPS Leave,
-+			 * because Fw is unload.
-+			 */
-+			*val = _TRUE;
-+		} else {
-+			u32 rcr = 0;
-+
-+			rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
-+			if (rcr & (RCR_UC_MD_EN | RCR_BC_MD_EN | RCR_TIM_PARSER_EN))
-+				*val = _FALSE;
-+			else
-+				*val = _TRUE;
-+		}
-+		break;
-+
-+	case HW_VAR_HCI_SUS_STATE:
-+		*((u8 *)val) = hal_data->hci_sus_state;
-+		break;
-+
-+#ifndef CONFIG_HAS_HW_VAR_BCN_CTRL_ADDR
-+	case HW_VAR_BCN_CTRL_ADDR:
-+		*((u32 *)val) = hw_bcn_ctrl_addr(adapter, adapter->hw_port);
-+		break;
-+#endif
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	case HW_VAR_CAM_EMPTY_ENTRY: {
-+		u8	ucIndex = *((u8 *)val);
-+		u8	i;
-+		u32	ulCommand = 0;
-+		u32	ulContent = 0;
-+		u32	ulEncAlgo = CAM_AES;
-+
-+		for (i = 0; i < CAM_CONTENT_COUNT; i++) {
-+			/* filled id in CAM config 2 byte */
-+			if (i == 0)
-+				ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo) << 2);
-+			else
-+				ulContent = 0;
-+			/* polling bit, and No Write enable, and address */
-+			ulCommand = CAM_CONTENT_COUNT * ucIndex + i;
-+			ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE;
-+			/* write content 0 is equall to mark invalid */
-+			rtw_write32(adapter, REG_CAMWRITE, ulContent);  /* delay_ms(40); */
-+			rtw_write32(adapter, REG_CAMCMD, ulCommand);  /* delay_ms(40); */
-+		}
-+	}
-+#endif
-+
-+	default:
-+		if (0)
-+			RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n",
-+				  FUNC_ADPT_ARG(adapter), variable);
-+		break;
-+	}
-+
-+}
-+
-+static u32 _get_page_size(struct _ADAPTER *a)
-+{
-+#ifdef RTW_HALMAC
-+	struct dvobj_priv *d;
-+	u32 size = 0;
-+	int err = 0;
-+
-+
-+	d = adapter_to_dvobj(a);
-+
-+	err = rtw_halmac_get_page_size(d, &size);
-+	if (!err)
-+		return size;
-+
-+	RTW_WARN(FUNC_ADPT_FMT ": Fail to get Page size!!(err=%d)\n",
-+		 FUNC_ADPT_ARG(a), err);
-+#endif /* RTW_HALMAC */
-+
-+	return PAGE_SIZE_128;
-+}
-+
-+u8
-+SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u8 bResult = _SUCCESS;
-+
-+	switch (variable) {
-+
-+	case HAL_DEF_DBG_DUMP_RXPKT:
-+		hal_data->bDumpRxPkt = *((u8 *)value);
-+		break;
-+	case HAL_DEF_DBG_DUMP_TXPKT:
-+		hal_data->bDumpTxPkt = *((u8 *)value);
-+		break;
-+	case HAL_DEF_ANT_DETECT:
-+		hal_data->AntDetection = *((u8 *)value);
-+		break;
-+	default:
-+		RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
-+		bResult = _FAIL;
-+		break;
-+	}
-+
-+	return bResult;
-+}
-+
-+#ifdef CONFIG_BEAMFORMING
-+u8 rtw_hal_query_txbfer_rf_num(_adapter *adapter)
-+{
-+	struct registry_priv	*pregistrypriv = &adapter->registrypriv;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+	if ((pregistrypriv->beamformer_rf_num) && (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter) || IS_HARDWARE_TYPE_8822BU(adapter) || IS_HARDWARE_TYPE_8821C(adapter)))
-+		return pregistrypriv->beamformer_rf_num;
-+	else if (IS_HARDWARE_TYPE_8814AE(adapter)
-+#if 0
-+#if defined(CONFIG_USB_HCI)
-+		|| (IS_HARDWARE_TYPE_8814AU(adapter) && (pUsbModeMech->CurUsbMode == 2 || pUsbModeMech->HubUsbMode == 2))  /* for USB3.0 */
-+#endif
-+#endif
-+		) {
-+		/*BF cap provided by Yu Chen, Sean, 2015, 01 */
-+		if (hal_data->rf_type == RF_3T3R)
-+			return 2;
-+		else if (hal_data->rf_type == RF_4T4R)
-+			return 3;
-+		else
-+			return 1;
-+	} else
-+		return 1;
-+
-+}
-+u8 rtw_hal_query_txbfee_rf_num(_adapter *adapter)
-+{
-+	struct registry_priv		*pregistrypriv = &adapter->registrypriv;
-+	struct mlme_ext_priv	*pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+	if ((pregistrypriv->beamformee_rf_num) && (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter) || IS_HARDWARE_TYPE_8822BU(adapter) || IS_HARDWARE_TYPE_8821C(adapter)))
-+		return pregistrypriv->beamformee_rf_num;
-+	else if (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter)) {
-+		if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM)
-+			return 2;
-+		else
-+			return 2;/*TODO: May be 3 in the future, by ChenYu. */
-+	} else
-+		return 1;
-+
-+}
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+void rtw_hal_beamforming_config_csirate(PADAPTER adapter)
-+{
-+	struct dm_struct *p_dm_odm;
-+	struct beamforming_info *bf_info;
-+	u8 fix_rate_enable = 0;
-+	u8 new_csi_rate_idx;
-+	u8 rrsr_54_en;
-+	u32 temp_rrsr;
-+
-+	/* Acting as BFee */
-+	if (IS_BEAMFORMEE(adapter)) {
-+	#if 0
-+		/* Do not enable now because it will affect MU performance and CTS/BA rate. 2016.07.19. by tynli. [PCIE-1660] */
-+		if (IS_HARDWARE_TYPE_8821C(Adapter))
-+			FixRateEnable = 1;	/* Support after 8821C */
-+	#endif
-+
-+		p_dm_odm = adapter_to_phydm(adapter);
-+		bf_info = GET_BEAMFORM_INFO(adapter);
-+
-+		rtw_halmac_bf_cfg_csi_rate(adapter_to_dvobj(adapter),
-+				p_dm_odm->rssi_min,
-+				bf_info->cur_csi_rpt_rate,
-+				fix_rate_enable, &new_csi_rate_idx, &rrsr_54_en);
-+
-+		temp_rrsr = rtw_read32(adapter, REG_RRSR);
-+		if (rrsr_54_en == 1)
-+			temp_rrsr |= RRSR_54M;
-+		else if (rrsr_54_en == 0)
-+			temp_rrsr &= ~RRSR_54M;
-+		rtw_phydm_set_rrsr(adapter, temp_rrsr, FALSE);
-+
-+		if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
-+			bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
-+	}
-+}
-+#endif
-+#endif
-+
-+u8
-+GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u8 bResult = _SUCCESS;
-+
-+	switch (variable) {
-+	case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: {
-+		struct mlme_priv *pmlmepriv;
-+		struct sta_priv *pstapriv;
-+		struct sta_info *psta;
-+
-+		pmlmepriv = &adapter->mlmepriv;
-+		pstapriv = &adapter->stapriv;
-+		psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
-+		if (psta)
-+			*((int *)value) = psta->cmn.rssi_stat.rssi;
-+	}
-+	break;
-+	case HAL_DEF_DBG_DUMP_RXPKT:
-+		*((u8 *)value) = hal_data->bDumpRxPkt;
-+		break;
-+	case HAL_DEF_DBG_DUMP_TXPKT:
-+		*((u8 *)value) = hal_data->bDumpTxPkt;
-+		break;
-+	case HAL_DEF_ANT_DETECT:
-+		*((u8 *)value) = hal_data->AntDetection;
-+		break;
-+	case HAL_DEF_TX_PAGE_SIZE:
-+		*((u32 *)value) = _get_page_size(adapter);
-+		break;
-+	case HAL_DEF_TX_STBC:
-+		#ifdef CONFIG_ALPHA_SMART_ANTENNA 
-+		*(u8 *)value = 0;
-+		#else
-+		*(u8 *)value = hal_data->max_tx_cnt > 1 ? 1 : 0;
-+		#endif
-+		break;
-+	case HAL_DEF_EXPLICIT_BEAMFORMER:
-+	case HAL_DEF_EXPLICIT_BEAMFORMEE:
-+	case HAL_DEF_VHT_MU_BEAMFORMER:
-+	case HAL_DEF_VHT_MU_BEAMFORMEE:
-+		*(u8 *)value = _FALSE;
-+		break;
-+#ifdef CONFIG_BEAMFORMING
-+	case HAL_DEF_BEAMFORMER_CAP:
-+		*(u8 *)value = rtw_hal_query_txbfer_rf_num(adapter);
-+		break;
-+	case HAL_DEF_BEAMFORMEE_CAP:
-+		*(u8 *)value = rtw_hal_query_txbfee_rf_num(adapter);
-+		break;
-+#endif
-+	default:
-+		RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
-+		bResult = _FAIL;
-+		break;
-+	}
-+
-+	return bResult;
-+}
-+
-+/*
-+ *	Description:
-+ *		Translate a character to hex digit.
-+ *   */
-+u32
-+MapCharToHexDigit(
-+			char		chTmp
-+)
-+{
-+	if (chTmp >= '0' && chTmp <= '9')
-+		return chTmp - '0';
-+	else if (chTmp >= 'a' && chTmp <= 'f')
-+		return 10 + (chTmp - 'a');
-+	else if (chTmp >= 'A' && chTmp <= 'F')
-+		return 10 + (chTmp - 'A');
-+	else
-+		return 0;
-+}
-+
-+
-+
-+/*
-+ *	Description:
-+ *		Parse hex number from the string pucStr.
-+ *   */
-+BOOLEAN
-+GetHexValueFromString(
-+		char			*szStr,
-+		u32			*pu4bVal,
-+		u32			*pu4bMove
-+)
-+{
-+	char		*szScan = szStr;
-+
-+	/* Check input parameter. */
-+	if (szStr == NULL || pu4bVal == NULL || pu4bMove == NULL) {
-+		RTW_INFO("GetHexValueFromString(): Invalid inpur argumetns! szStr: %p, pu4bVal: %p, pu4bMove: %p\n", szStr, pu4bVal, pu4bMove);
-+		return _FALSE;
-+	}
-+
-+	/* Initialize output. */
-+	*pu4bMove = 0;
-+	*pu4bVal = 0;
-+
-+	/* Skip leading space. */
-+	while (*szScan != '\0' &&
-+	       (*szScan == ' ' || *szScan == '\t')) {
-+		szScan++;
-+		(*pu4bMove)++;
-+	}
-+
-+	/* Skip leading '0x' or '0X'. */
-+	if (*szScan == '0' && (*(szScan + 1) == 'x' || *(szScan + 1) == 'X')) {
-+		szScan += 2;
-+		(*pu4bMove) += 2;
-+	}
-+
-+	/* Check if szScan is now pointer to a character for hex digit, */
-+	/* if not, it means this is not a valid hex number. */
-+	if (!IsHexDigit(*szScan))
-+		return _FALSE;
-+
-+	/* Parse each digit. */
-+	do {
-+		(*pu4bVal) <<= 4;
-+		*pu4bVal += MapCharToHexDigit(*szScan);
-+
-+		szScan++;
-+		(*pu4bMove)++;
-+	} while (IsHexDigit(*szScan));
-+
-+	return _TRUE;
-+}
-+
-+BOOLEAN
-+GetFractionValueFromString(
-+		char			*szStr,
-+		u8				*pInteger,
-+		u8				*pFraction,
-+		u32			*pu4bMove
-+)
-+{
-+	char	*szScan = szStr;
-+
-+	/* Initialize output. */
-+	*pu4bMove = 0;
-+	*pInteger = 0;
-+	*pFraction = 0;
-+
-+	/* Skip leading space. */
-+	while (*szScan != '\0' &&	(*szScan == ' ' || *szScan == '\t')) {
-+		++szScan;
-+		++(*pu4bMove);
-+	}
-+
-+	if (*szScan < '0' || *szScan > '9')
-+		return _FALSE;
-+
-+	/* Parse each digit. */
-+	do {
-+		(*pInteger) *= 10;
-+		*pInteger += (*szScan - '0');
-+
-+		++szScan;
-+		++(*pu4bMove);
-+
-+		if (*szScan == '.') {
-+			++szScan;
-+			++(*pu4bMove);
-+
-+			if (*szScan < '0' || *szScan > '9')
-+				return _FALSE;
-+
-+			*pFraction += (*szScan - '0') * 10;
-+			++szScan;
-+			++(*pu4bMove);
-+
-+			if (*szScan >= '0' && *szScan <= '9') {
-+				*pFraction += *szScan - '0';
-+				++szScan;
-+				++(*pu4bMove);
-+			}
-+			return _TRUE;
-+		}
-+	} while (*szScan >= '0' && *szScan <= '9');
-+
-+	return _TRUE;
-+}
-+
-+/*
-+ *	Description:
-+ * Return TRUE if szStr is comment out with leading " */ /* ".
-+ *   */
-+BOOLEAN
-+IsCommentString(
-+		char			*szStr
-+)
-+{
-+	if (*szStr == '/' && *(szStr + 1) == '/')
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+BOOLEAN
-+GetU1ByteIntegerFromStringInDecimal(
-+		char	*Str,
-+		u8		*pInt
-+)
-+{
-+	u16 i = 0;
-+	*pInt = 0;
-+
-+	while (Str[i] != '\0') {
-+		if (Str[i] >= '0' && Str[i] <= '9') {
-+			*pInt *= 10;
-+			*pInt += (Str[i] - '0');
-+		} else
-+			return _FALSE;
-+		++i;
-+	}
-+
-+	return _TRUE;
-+}
-+
-+/* <20121004, Kordan> For example,
-+ * ParseQualifiedString(inString, 0, outString, '[', ']') gets "Kordan" from a string "Hello [Kordan]".
-+ * If RightQualifier does not exist, it will hang on in the while loop */
-+BOOLEAN
-+ParseQualifiedString(
-+			char	*In,
-+			u32	*Start,
-+			char	*Out,
-+			char		LeftQualifier,
-+			char		RightQualifier
-+)
-+{
-+	u32	i = 0, j = 0;
-+	char	c = In[(*Start)++];
-+
-+	if (c != LeftQualifier)
-+		return _FALSE;
-+
-+	i = (*Start);
-+	c = In[(*Start)++];
-+	while (c != RightQualifier && c != '\0')
-+		c = In[(*Start)++];
-+
-+	if (c == '\0')
-+		return _FALSE;
-+
-+	j = (*Start) - 2;
-+	strncpy((char *)Out, (const char *)(In + i), j - i + 1);
-+
-+	return _TRUE;
-+}
-+
-+BOOLEAN
-+isAllSpaceOrTab(
-+	u8	*data,
-+	u8	size
-+)
-+{
-+	u8	cnt = 0, NumOfSpaceAndTab = 0;
-+
-+	while (size > cnt) {
-+		if (data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0')
-+			++NumOfSpaceAndTab;
-+
-+		++cnt;
-+	}
-+
-+	return size == NumOfSpaceAndTab;
-+}
-+
-+
-+void rtw_hal_check_rxfifo_full(_adapter *adapter)
-+{
-+	struct dvobj_priv *psdpriv = adapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
-+	struct registry_priv *regsty = &adapter->registrypriv;
-+	int save_cnt = _FALSE;
-+
-+	if (regsty->check_hw_status == 1) {
-+		/* switch counter to RX fifo */
-+		if (IS_8188E(pHalData->version_id) ||
-+		    IS_8188F(pHalData->version_id) ||
-+		    IS_8188GTV(pHalData->version_id) ||
-+		    IS_8812_SERIES(pHalData->version_id) ||
-+		    IS_8821_SERIES(pHalData->version_id) ||
-+		    IS_8723B_SERIES(pHalData->version_id) ||
-+		    IS_8192E(pHalData->version_id) ||
-+		    IS_8703B_SERIES(pHalData->version_id) ||
-+		    IS_8723D_SERIES(pHalData->version_id) ||
-+		    IS_8192F_SERIES(pHalData->version_id)) {
-+			rtw_write8(adapter, REG_RXERR_RPT + 3, rtw_read8(adapter, REG_RXERR_RPT + 3) | 0xa0);
-+			save_cnt = _TRUE;
-+		} else {
-+			/* todo: other chips */
-+		}
-+
-+
-+		if (save_cnt) {
-+			pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
-+			pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);
-+			pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow - pdbgpriv->dbg_rx_fifo_last_overflow;
-+		} else {
-+			/* special value to indicate no implementation */
-+			pdbgpriv->dbg_rx_fifo_last_overflow = 1;
-+			pdbgpriv->dbg_rx_fifo_curr_overflow = 1;
-+			pdbgpriv->dbg_rx_fifo_diff_overflow = 1;
-+		}
-+	}
-+}
-+
-+void linked_info_dump(_adapter *padapter, u8 benable)
-+{
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+
-+	if (padapter->bLinkInfoDump == benable)
-+		return;
-+
-+	RTW_INFO("%s %s\n", __FUNCTION__, (benable) ? "enable" : "disable");
-+
-+	if (benable) {
-+#ifdef CONFIG_LPS
-+		pwrctrlpriv->org_power_mgnt = pwrctrlpriv->power_mgnt;/* keep org value */
-+		rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
-+#endif
-+
-+#ifdef CONFIG_IPS
-+		pwrctrlpriv->ips_org_mode = pwrctrlpriv->ips_mode;/* keep org value */
-+		rtw_pm_set_ips(padapter, IPS_NONE);
-+#endif
-+	} else {
-+#ifdef CONFIG_IPS
-+		rtw_pm_set_ips(padapter, pwrctrlpriv->ips_org_mode);
-+#endif /* CONFIG_IPS */
-+
-+#ifdef CONFIG_LPS
-+		rtw_pm_set_lps(padapter, pwrctrlpriv->org_power_mgnt);
-+#endif /* CONFIG_LPS */
-+	}
-+	padapter->bLinkInfoDump = benable ;
-+}
-+
-+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
-+void rtw_get_raw_rssi_info(void *sel, _adapter *padapter)
-+{
-+	u8 isCCKrate, rf_path;
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
-+	RTW_PRINT_SEL(sel, "RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
-+		HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
-+	isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
-+
-+	if (isCCKrate)
-+		psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;
-+
-+	for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++) {
-+		if (!(GET_HAL_RX_PATH_BMP(padapter) & BIT(rf_path)))
-+			continue;
-+		RTW_PRINT_SEL(sel, "RF_PATH_%d=>signal_strength:%d(%%),signal_quality:%d(%%)\n"
-+			, rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]);
-+
-+		if (!isCCKrate) {
-+			RTW_PRINT_SEL(sel, "\trx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\n",
-+				psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
-+		}
-+	}
-+}
-+
-+void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel)
-+{
-+	u8 isCCKrate, rf_path;
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
-+	_RTW_PRINT_SEL(sel, "============ RAW Rx Info dump ===================\n");
-+	_RTW_PRINT_SEL(sel, "RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n", HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
-+
-+	isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
-+
-+	if (isCCKrate)
-+		psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball;
-+
-+	for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++) {
-+		if (!(GET_HAL_RX_PATH_BMP(padapter) & BIT(rf_path)))
-+			continue;
-+		_RTW_PRINT_SEL(sel , "RF_PATH_%d=>signal_strength:%d(%%),signal_quality:%d(%%)"
-+			, rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]);
-+
-+		if (!isCCKrate)
-+			_RTW_PRINT_SEL(sel , ",rx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\n", psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
-+		else
-+			_RTW_PRINT_SEL(sel , "\n");
-+
-+	}
-+}
-+#endif
-+
-+#ifdef DBG_RX_DFRAME_RAW_DATA
-+void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel)
-+{
-+#define DBG_RX_DFRAME_RAW_DATA_UC		0
-+#define DBG_RX_DFRAME_RAW_DATA_BMC		1
-+#define DBG_RX_DFRAME_RAW_DATA_TYPES	2
-+
-+	_irqL irqL;
-+	u8 isCCKrate, rf_path;
-+	struct recv_priv *precvpriv = &(padapter->recvpriv);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *psta;
-+	struct sta_recv_dframe_info *psta_dframe_info;
-+	int i, j;
-+	_list	*plist, *phead;
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
-+
-+	if (precvpriv->store_law_data_flag) {
-+
-+		_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+		for (i = 0; i < NUM_STA; i++) {
-+			phead = &(pstapriv->sta_hash[i]);
-+			plist = get_next(phead);
-+
-+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+
-+				psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+				plist = get_next(plist);
-+
-+				if (psta) {
-+					if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)  !=   _TRUE)
-+					    && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN)  !=  _TRUE)
-+					    && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)  !=  _TRUE)) {
-+
-+						RTW_PRINT_SEL(sel, "==============================\n");
-+						RTW_PRINT_SEL(sel, "macaddr =" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
-+
-+						for (j = 0; j < DBG_RX_DFRAME_RAW_DATA_TYPES; j++) {
-+							if (j == DBG_RX_DFRAME_RAW_DATA_UC) {
-+								psta_dframe_info = &psta->sta_dframe_info;
-+								RTW_PRINT_SEL(sel, "\n");
-+								RTW_PRINT_SEL(sel, "Unicast:\n");
-+							} else if (j == DBG_RX_DFRAME_RAW_DATA_BMC) {
-+								psta_dframe_info = &psta->sta_dframe_info_bmc;
-+								RTW_PRINT_SEL(sel, "\n");
-+								RTW_PRINT_SEL(sel, "Broadcast/Multicast:\n");
-+							}
-+
-+							isCCKrate = (psta_dframe_info->sta_data_rate <= DESC_RATE11M) ? TRUE : FALSE;
-+
-+							RTW_PRINT_SEL(sel, "BW=%s, sgi =%d\n", ch_width_str(psta_dframe_info->sta_bw_mode), psta_dframe_info->sta_sgi);
-+							RTW_PRINT_SEL(sel, "Rx_Data_Rate = %s\n", HDATA_RATE(psta_dframe_info->sta_data_rate));
-+
-+							for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++) {
-+								if (!(GET_HAL_RX_PATH_BMP(padapter) & BIT(rf_path)))
-+									continue;
-+								if (!isCCKrate) {
-+									RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)", rf_path, psta_dframe_info->sta_RxPwr[rf_path]);
-+									_RTW_PRINT_SEL(sel , ",rx_ofdm_snr:%d(dB)\n", psta_dframe_info->sta_ofdm_snr[rf_path]);
-+								} else
-+									RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)\n", rf_path, (psta_dframe_info->sta_mimo_signal_strength[rf_path]) - 100);
-+							}
-+						}
-+
-+					}
-+				}
-+			}
-+		}
-+		_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+	}
-+}
-+#endif
-+void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe)
-+{
-+	u8 isCCKrate, rf_path , dframe_type;
-+	u8 *ptr;
-+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+#ifdef DBG_RX_DFRAME_RAW_DATA
-+	struct sta_recv_dframe_info *psta_dframe_info;
-+#endif
-+	struct recv_priv *precvpriv = &(padapter->recvpriv);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
-+	struct sta_info *psta = prframe->u.hdr.psta;
-+	struct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info;
-+	struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
-+	psample_pkt_rssi->data_rate = pattrib->data_rate;
-+	ptr = prframe->u.hdr.rx_data;
-+	dframe_type = GetFrameType(ptr);
-+	/*RTW_INFO("=>%s\n", __FUNCTION__);*/
-+
-+
-+	if (precvpriv->store_law_data_flag) {
-+		isCCKrate = (pattrib->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
-+
-+		psample_pkt_rssi->pwdball = p_phy_info->rx_pwdb_all;
-+		psample_pkt_rssi->pwr_all = p_phy_info->recv_signal_power;
-+
-+		for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++) {
-+			psample_pkt_rssi->mimo_signal_strength[rf_path] = p_phy_info->rx_mimo_signal_strength[rf_path];
-+			psample_pkt_rssi->mimo_signal_quality[rf_path] = p_phy_info->rx_mimo_signal_quality[rf_path];
-+			if (!isCCKrate) {
-+				psample_pkt_rssi->ofdm_pwr[rf_path] = p_phy_info->rx_pwr[rf_path];
-+				psample_pkt_rssi->ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path];
-+			}
-+		}
-+#ifdef DBG_RX_DFRAME_RAW_DATA
-+		if ((dframe_type == WIFI_DATA_TYPE) || (dframe_type == WIFI_QOS_DATA_TYPE) || (padapter->registrypriv.mp_mode == 1)) {
-+
-+			/*RTW_INFO("=>%s WIFI_DATA_TYPE or WIFI_QOS_DATA_TYPE\n", __FUNCTION__);*/
-+			if (psta) {
-+				if (IS_MCAST(get_ra(get_recvframe_data(prframe))))
-+					psta_dframe_info = &psta->sta_dframe_info_bmc;
-+				else
-+					psta_dframe_info = &psta->sta_dframe_info;
-+				/*RTW_INFO("=>%s psta->cmn.mac_addr="MAC_FMT" !\n",
-+					__FUNCTION__, MAC_ARG(psta->cmn.mac_addr));*/
-+				if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) || (padapter->registrypriv.mp_mode == 1)) {
-+					psta_dframe_info->sta_data_rate = pattrib->data_rate;
-+					psta_dframe_info->sta_sgi = pattrib->sgi;
-+					psta_dframe_info->sta_bw_mode = pattrib->bw;
-+					for (rf_path = 0; rf_path < hal_spec->rf_reg_path_num; rf_path++) {
-+
-+						psta_dframe_info->sta_mimo_signal_strength[rf_path] = (p_phy_info->rx_mimo_signal_strength[rf_path]);/*Percentage to dbm*/
-+
-+						if (!isCCKrate) {
-+							psta_dframe_info->sta_ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path];
-+							psta_dframe_info->sta_RxPwr[rf_path] = p_phy_info->rx_pwr[rf_path];
-+						}
-+					}
-+				}
-+			}
-+		}
-+#endif
-+	}
-+
-+}
-+
-+int hal_efuse_macaddr_offset(_adapter *adapter)
-+{
-+	u8 interface_type = 0;
-+	int addr_offset = -1;
-+
-+	interface_type = rtw_get_intf_type(adapter);
-+
-+	switch (rtw_get_chip_type(adapter)) {
-+#ifdef CONFIG_RTL8723B
-+	case RTL8723B:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8723BU;
-+		else if (interface_type == RTW_SDIO)
-+			addr_offset = EEPROM_MAC_ADDR_8723BS;
-+		else if (interface_type == RTW_PCIE)
-+			addr_offset = EEPROM_MAC_ADDR_8723BE;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8703B
-+	case RTL8703B:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8703BU;
-+		else if (interface_type == RTW_SDIO)
-+			addr_offset = EEPROM_MAC_ADDR_8703BS;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8723D
-+	case RTL8723D:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8723DU;
-+		else if (interface_type == RTW_SDIO)
-+			addr_offset = EEPROM_MAC_ADDR_8723DS;
-+		else if (interface_type == RTW_PCIE)
-+			addr_offset = EEPROM_MAC_ADDR_8723DE;
-+		break;
-+#endif
-+
-+#ifdef CONFIG_RTL8188E
-+	case RTL8188E:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_88EU;
-+		else if (interface_type == RTW_SDIO)
-+			addr_offset = EEPROM_MAC_ADDR_88ES;
-+		else if (interface_type == RTW_PCIE)
-+			addr_offset = EEPROM_MAC_ADDR_88EE;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8188F
-+	case RTL8188F:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8188FU;
-+		else if (interface_type == RTW_SDIO)
-+			addr_offset = EEPROM_MAC_ADDR_8188FS;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8188GTV
-+	case RTL8188GTV:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8188GTVU;
-+		else if (interface_type == RTW_SDIO)
-+			addr_offset = EEPROM_MAC_ADDR_8188GTVS;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8812A
-+	case RTL8812:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8812AU;
-+		else if (interface_type == RTW_PCIE)
-+			addr_offset = EEPROM_MAC_ADDR_8812AE;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8821A
-+	case RTL8821:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8821AU;
-+		else if (interface_type == RTW_SDIO)
-+			addr_offset = EEPROM_MAC_ADDR_8821AS;
-+		else if (interface_type == RTW_PCIE)
-+			addr_offset = EEPROM_MAC_ADDR_8821AE;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8192E
-+	case RTL8192E:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8192EU;
-+		else if (interface_type == RTW_SDIO)
-+			addr_offset = EEPROM_MAC_ADDR_8192ES;
-+		else if (interface_type == RTW_PCIE)
-+			addr_offset = EEPROM_MAC_ADDR_8192EE;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8814A
-+	case RTL8814A:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8814AU;
-+		else if (interface_type == RTW_PCIE)
-+			addr_offset = EEPROM_MAC_ADDR_8814AE;
-+		break;
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	case RTL8822B:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8822BU;
-+		else if (interface_type == RTW_SDIO)
-+			addr_offset = EEPROM_MAC_ADDR_8822BS;
-+		else if (interface_type == RTW_PCIE)
-+			addr_offset = EEPROM_MAC_ADDR_8822BE;
-+		break;
-+#endif /* CONFIG_RTL8822B */
-+
-+#ifdef CONFIG_RTL8821C
-+	case RTL8821C:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8821CU;
-+		else if (interface_type == RTW_SDIO)
-+			addr_offset = EEPROM_MAC_ADDR_8821CS;
-+		else if (interface_type == RTW_PCIE)
-+			addr_offset = EEPROM_MAC_ADDR_8821CE;
-+		break;
-+#endif /* CONFIG_RTL8821C */
-+
-+#ifdef CONFIG_RTL8710B
-+	case RTL8710B:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8710B;
-+		break;
-+#endif
-+
-+#ifdef CONFIG_RTL8192F
-+	case RTL8192F:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8192FU;
-+		else if (interface_type == RTW_SDIO)
-+			addr_offset = EEPROM_MAC_ADDR_8192FS;
-+		else if (interface_type == RTW_PCIE)
-+			addr_offset = EEPROM_MAC_ADDR_8192FE;
-+		break;
-+#endif /* CONFIG_RTL8192F */
-+
-+#ifdef CONFIG_RTL8822C
-+	case RTL8822C:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8822CU;
-+		else if (interface_type == RTW_SDIO)
-+			addr_offset = EEPROM_MAC_ADDR_8822CS;
-+		else if (interface_type == RTW_PCIE)
-+			addr_offset = EEPROM_MAC_ADDR_8822CE;
-+		break;
-+#endif /* CONFIG_RTL8822C */
-+
-+#ifdef CONFIG_RTL8814B
-+	case RTL8814B:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8814BU;
-+		else if (interface_type == RTW_PCIE)
-+			addr_offset = EEPROM_MAC_ADDR_8814BE;
-+		break;
-+#endif /* CONFIG_RTL8814B */
-+
-+#ifdef CONFIG_RTL8723F
-+	case RTL8723F:
-+		if (interface_type == RTW_USB)
-+			addr_offset = EEPROM_MAC_ADDR_8723FU;
-+		else if (interface_type == RTW_SDIO)
-+			addr_offset = EEPROM_MAC_ADDR_8723FS;
-+		break;
-+#endif /* CONFIG_RTL8723F */
-+	}
-+
-+	if (addr_offset == -1) {
-+		RTW_ERR("%s: unknown combination - chip_type:%u, interface:%u\n"
-+			, __func__, rtw_get_chip_type(adapter), rtw_get_intf_type(adapter));
-+	}
-+
-+	return addr_offset;
-+}
-+
-+int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr)
-+{
-+	int ret = _FAIL;
-+	int addr_offset;
-+
-+	addr_offset = hal_efuse_macaddr_offset(padapter);
-+	if (addr_offset == -1)
-+		goto exit;
-+
-+	ret = rtw_efuse_map_read(padapter, addr_offset, ETH_ALEN, mac_addr);
-+
-+exit:
-+	return ret;
-+}
-+
-+void rtw_dump_cur_efuse(PADAPTER padapter)
-+{
-+	int mapsize =0;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
-+
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapsize, _FALSE);
-+
-+	if (mapsize <= 0 || mapsize > EEPROM_MAX_SIZE) {
-+		RTW_ERR("wrong map size %d\n", mapsize);
-+		return;
-+	}
-+
-+#ifdef CONFIG_RTW_DEBUG
-+	if (hal_data->efuse_file_status == EFUSE_FILE_LOADED)
-+		RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "EFUSE FILE", hal_data->efuse_eeprom_data, mapsize);
-+	else
-+		RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "HW EFUSE", hal_data->efuse_eeprom_data, mapsize);
-+#endif
-+}
-+
-+
-+#ifdef CONFIG_EFUSE_CONFIG_FILE
-+u32 Hal_readPGDataFromConfigFile(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
-+	u32 ret = _FALSE;
-+	u32 maplen = 0;
-+#ifdef CONFIG_MP_INCLUDED
-+		struct mp_priv *pmp_priv = &padapter->mppriv;
-+#endif
-+
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&maplen, _FALSE);
-+
-+	if (maplen < 256 || maplen > EEPROM_MAX_SIZE) {
-+		RTW_ERR("eFuse length error :%d\n", maplen);
-+		return _FALSE;
-+	}	
-+#ifdef CONFIG_MP_INCLUDED
-+	if (pmp_priv->efuse_update_file == _TRUE && (rtw_mp_mode_check(padapter))) {
-+		RTW_INFO("%s, eFuse read from file :%s\n", __func__, pmp_priv->efuse_file_path);
-+		ret = rtw_read_efuse_from_file(pmp_priv->efuse_file_path, hal_data->efuse_eeprom_data, maplen);
-+		pmp_priv->efuse_update_file = _FALSE;
-+	} else
-+#endif
-+	{
-+		ret = rtw_read_efuse_from_file(EFUSE_MAP_PATH, hal_data->efuse_eeprom_data, maplen);
-+	}
-+
-+	hal_data->efuse_file_status = ((ret == _FAIL) ? EFUSE_FILE_FAILED : EFUSE_FILE_LOADED);
-+
-+	if (hal_data->efuse_file_status == EFUSE_FILE_LOADED)
-+		rtw_dump_cur_efuse(padapter);
-+
-+	return ret;
-+}
-+
-+u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
-+	u32 ret = _FAIL;
-+
-+	if (rtw_read_macaddr_from_file(WIFIMAC_PATH, mac_addr) == _SUCCESS
-+		&& rtw_check_invalid_mac_address(mac_addr, _TRUE) == _FALSE
-+	) {
-+		hal_data->macaddr_file_status = MACADDR_FILE_LOADED;
-+		ret = _SUCCESS;
-+	} else
-+		hal_data->macaddr_file_status = MACADDR_FILE_FAILED;
-+
-+	return ret;
-+}
-+#endif /* CONFIG_EFUSE_CONFIG_FILE */
-+
-+int hal_config_macaddr(_adapter *adapter, bool autoload_fail)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u8 addr[ETH_ALEN];
-+	int addr_offset = hal_efuse_macaddr_offset(adapter);
-+	u8 *hw_addr = NULL;
-+	int ret = _SUCCESS;
-+#if defined(CONFIG_RTL8822B) && defined(CONFIG_USB_HCI)
-+	u8 ft_mac_addr[ETH_ALEN] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff}; /* FT USB2 for 8822B */
-+#endif
-+
-+	if (autoload_fail)
-+		goto bypass_hw_pg;
-+
-+	if (addr_offset != -1)
-+		hw_addr = &hal_data->efuse_eeprom_data[addr_offset];
-+
-+#ifdef CONFIG_EFUSE_CONFIG_FILE
-+	/* if the hw_addr is written by efuse file, set to NULL */
-+	if (hal_data->efuse_file_status == EFUSE_FILE_LOADED)
-+		hw_addr = NULL;
-+#endif
-+
-+	if (!hw_addr) {
-+		/* try getting hw pg data */
-+		if (Hal_GetPhyEfuseMACAddr(adapter, addr) == _SUCCESS)
-+			hw_addr = addr;
-+	}
-+
-+#if defined(CONFIG_RTL8822B) && defined(CONFIG_USB_HCI)
-+	if (_rtw_memcmp(hw_addr, ft_mac_addr, ETH_ALEN))
-+		hw_addr[0] = 0xff;
-+#endif
-+
-+	/* check hw pg data */
-+	if (hw_addr && rtw_check_invalid_mac_address(hw_addr, _TRUE) == _FALSE) {
-+		_rtw_memcpy(hal_data->EEPROMMACAddr, hw_addr, ETH_ALEN);
-+		goto exit;
-+	}
-+
-+bypass_hw_pg:
-+
-+#ifdef CONFIG_EFUSE_CONFIG_FILE
-+	/* check wifi mac file */
-+	if (Hal_ReadMACAddrFromFile(adapter, addr) == _SUCCESS) {
-+		_rtw_memcpy(hal_data->EEPROMMACAddr, addr, ETH_ALEN);
-+		goto exit;
-+	}
-+#endif
-+
-+	_rtw_memset(hal_data->EEPROMMACAddr, 0, ETH_ALEN);
-+	ret = _FAIL;
-+
-+exit:
-+	return ret;
-+}
-+
-+#ifdef CONFIG_RF_POWER_TRIM
-+u32 Array_kfreemap[] = {
-+	0x08, 0xe,
-+	0x06, 0xc,
-+	0x04, 0xa,
-+	0x02, 0x8,
-+	0x00, 0x6,
-+	0x03, 0x4,
-+	0x05, 0x2,
-+	0x07, 0x0,
-+	0x09, 0x0,
-+	0x0c, 0x0,
-+};
-+
-+void rtw_bb_rf_gain_offset(_adapter *padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct registry_priv  *registry_par = &padapter->registrypriv;
-+	struct kfree_data_t *kfree_data = &pHalData->kfree_data;
-+	u8		value = pHalData->EEPROMRFGainOffset;
-+	u8		tmp = 0x3e;
-+	u32		res, i = 0;
-+	u32		ArrayLen	= sizeof(Array_kfreemap) / sizeof(u32);
-+	u32		*Array = Array_kfreemap;
-+	u32		v1 = 0, v2 = 0, GainValue = 0, target = 0;
-+
-+	if (registry_par->RegPwrTrimEnable == 2) {
-+		RTW_INFO("Registry kfree default force disable.\n");
-+		return;
-+	}
-+
-+#if defined(CONFIG_RTL8723B)
-+	if (value & BIT4 && (registry_par->RegPwrTrimEnable == 1)) {
-+		RTW_INFO("Offset RF Gain.\n");
-+		RTW_INFO("Offset RF Gain.  pHalData->EEPROMRFGainVal=0x%x\n", pHalData->EEPROMRFGainVal);
-+
-+		if (pHalData->EEPROMRFGainVal != 0xff) {
-+
-+			if (pHalData->ant_path == RF_PATH_A)
-+				GainValue = (pHalData->EEPROMRFGainVal & 0x0f);
-+
-+			else
-+				GainValue = (pHalData->EEPROMRFGainVal & 0xf0) >> 4;
-+			RTW_INFO("Ant PATH_%d GainValue Offset = 0x%x\n", (pHalData->ant_path == RF_PATH_A) ? (RF_PATH_A) : (RF_PATH_B), GainValue);
-+
-+			for (i = 0; i < ArrayLen; i += 2) {
-+				/* RTW_INFO("ArrayLen in =%d ,Array 1 =0x%x ,Array2 =0x%x\n",i,Array[i],Array[i]+1); */
-+				v1 = Array[i];
-+				v2 = Array[i + 1];
-+				if (v1 == GainValue) {
-+					RTW_INFO("Offset RF Gain. got v1 =0x%x ,v2 =0x%x\n", v1, v2);
-+					target = v2;
-+					break;
-+				}
-+			}
-+			RTW_INFO("pHalData->EEPROMRFGainVal=0x%x ,Gain offset Target Value=0x%x\n", pHalData->EEPROMRFGainVal, target);
-+
-+			res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
-+			RTW_INFO("Offset RF Gain. before reg 0x7f=0x%08x\n", res);
-+			phy_set_rf_reg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18 | BIT17 | BIT16 | BIT15, target);
-+			res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
-+
-+			RTW_INFO("Offset RF Gain. After reg 0x7f=0x%08x\n", res);
-+
-+		} else
-+
-+			RTW_INFO("Offset RF Gain.  pHalData->EEPROMRFGainVal=0x%x	!= 0xff, didn't run Kfree\n", pHalData->EEPROMRFGainVal);
-+	} else
-+		RTW_INFO("Using the default RF gain.\n");
-+
-+#elif defined(CONFIG_RTL8188E)
-+	if (value & BIT4 && (registry_par->RegPwrTrimEnable == 1)) {
-+		RTW_INFO("8188ES Offset RF Gain.\n");
-+		RTW_INFO("8188ES Offset RF Gain. EEPROMRFGainVal=0x%x\n",
-+			 pHalData->EEPROMRFGainVal);
-+
-+		if (pHalData->EEPROMRFGainVal != 0xff) {
-+			res = rtw_hal_read_rfreg(padapter, RF_PATH_A,
-+					 REG_RF_BB_GAIN_OFFSET, 0xffffffff);
-+
-+			RTW_INFO("Offset RF Gain. reg 0x55=0x%x\n", res);
-+			res &= 0xfff87fff;
-+
-+			res |= (pHalData->EEPROMRFGainVal & 0x0f) << 15;
-+			RTW_INFO("Offset RF Gain. res=0x%x\n", res);
-+
-+			rtw_hal_write_rfreg(padapter, RF_PATH_A,
-+					    REG_RF_BB_GAIN_OFFSET,
-+					    RF_GAIN_OFFSET_MASK, res);
-+		} else {
-+			RTW_INFO("Offset RF Gain. EEPROMRFGainVal=0x%x == 0xff, didn't run Kfree\n",
-+				 pHalData->EEPROMRFGainVal);
-+		}
-+	} else
-+		RTW_INFO("Using the default RF gain.\n");
-+#else
-+	/* TODO: call this when channel switch */
-+	if (kfree_data->flag & KFREE_FLAG_ON)
-+		rtw_rf_apply_tx_gain_offset(padapter, 6); /* input ch6 to select BB_GAIN_2G */
-+#endif
-+
-+}
-+#endif /*CONFIG_RF_POWER_TRIM */
-+
-+bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data)
-+{
-+#ifdef CONFIG_RF_POWER_TRIM
-+	int i, j;
-+
-+	for (i = 0; i < BB_GAIN_NUM; i++)
-+		for (j = 0; j < RF_PATH_MAX; j++)
-+			if (data->bb_gain[i][j] != 0)
-+				return 0;
-+#endif
-+	return 1;
-+}
-+
-+#ifdef CONFIG_USB_RX_AGGREGATION
-+void rtw_set_usb_agg_by_mode_normal(_adapter *padapter, u8 cur_wireless_mode)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	if (cur_wireless_mode < WIRELESS_11_24N
-+	    && cur_wireless_mode > 0) { /* ABG mode */
-+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
-+		u32 remainder = 0;
-+		u8 quotient = 0;
-+
-+		remainder = MAX_RECVBUF_SZ % (4 * 1024);
-+		quotient = (u8)(MAX_RECVBUF_SZ >> 12);
-+
-+		if (quotient > 5) {
-+			pHalData->rxagg_usb_size = 0x6;
-+			pHalData->rxagg_usb_timeout = 0x10;
-+		} else {
-+			if (remainder >= 2048) {
-+				pHalData->rxagg_usb_size = quotient;
-+				pHalData->rxagg_usb_timeout = 0x10;
-+			} else {
-+				pHalData->rxagg_usb_size = (quotient - 1);
-+				pHalData->rxagg_usb_timeout = 0x10;
-+			}
-+		}
-+#else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */
-+		if (0x6 != pHalData->rxagg_usb_size || 0x10 != pHalData->rxagg_usb_timeout) {
-+			pHalData->rxagg_usb_size = 0x6;
-+			pHalData->rxagg_usb_timeout = 0x10;
-+			rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
-+				pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
-+		}
-+#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
-+
-+	} else if (cur_wireless_mode >= WIRELESS_11_24N
-+		   && cur_wireless_mode <= WIRELESS_MODE_MAX) { /* N AC mode */
-+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
-+		u32 remainder = 0;
-+		u8 quotient = 0;
-+
-+		remainder = MAX_RECVBUF_SZ % (4 * 1024);
-+		quotient = (u8)(MAX_RECVBUF_SZ >> 12);
-+
-+		if (quotient > 5) {
-+			pHalData->rxagg_usb_size = 0x5;
-+			pHalData->rxagg_usb_timeout = 0x20;
-+		} else {
-+			if (remainder >= 2048) {
-+				pHalData->rxagg_usb_size = quotient;
-+				pHalData->rxagg_usb_timeout = 0x10;
-+			} else {
-+				pHalData->rxagg_usb_size = (quotient - 1);
-+				pHalData->rxagg_usb_timeout = 0x10;
-+			}
-+		}
-+#else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */
-+		if ((0x5 != pHalData->rxagg_usb_size) || (0x20 != pHalData->rxagg_usb_timeout)) {
-+			pHalData->rxagg_usb_size = 0x5;
-+			pHalData->rxagg_usb_timeout = 0x20;
-+			rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
-+				pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
-+		}
-+#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
-+
-+	} else {
-+		/* RTW_INFO("%s: Unknow wireless mode(0x%x)\n",__func__,padapter->mlmeextpriv.cur_wireless_mode); */
-+	}
-+}
-+
-+void rtw_set_usb_agg_by_mode_customer(_adapter *padapter, u8 cur_wireless_mode, u8 UsbDmaSize, u8 Legacy_UsbDmaSize)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	if (cur_wireless_mode < WIRELESS_11_24N
-+	    && cur_wireless_mode > 0) { /* ABG mode */
-+		if (Legacy_UsbDmaSize != pHalData->rxagg_usb_size
-+		    || 0x10 != pHalData->rxagg_usb_timeout) {
-+			pHalData->rxagg_usb_size = Legacy_UsbDmaSize;
-+			pHalData->rxagg_usb_timeout = 0x10;
-+			rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
-+				pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
-+		}
-+	} else if (cur_wireless_mode >= WIRELESS_11_24N
-+		   && cur_wireless_mode <= WIRELESS_MODE_MAX) { /* N AC mode */
-+		if (UsbDmaSize != pHalData->rxagg_usb_size
-+		    || 0x20 != pHalData->rxagg_usb_timeout) {
-+			pHalData->rxagg_usb_size = UsbDmaSize;
-+			pHalData->rxagg_usb_timeout = 0x20;
-+			rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
-+				pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
-+		}
-+	} else {
-+		/* RTW_INFO("%s: Unknown wireless mode(0x%x)\n",__func__,padapter->mlmeextpriv.cur_wireless_mode); */
-+	}
-+}
-+
-+void rtw_set_usb_agg_by_mode(_adapter *padapter, u8 cur_wireless_mode)
-+{
-+#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
-+	rtw_set_usb_agg_by_mode_customer(padapter, cur_wireless_mode, 0x3, 0x3);
-+	return;
-+#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
-+
-+	rtw_set_usb_agg_by_mode_normal(padapter, cur_wireless_mode);
-+}
-+#endif /* CONFIG_USB_RX_AGGREGATION */
-+
-+/* To avoid RX affect TX throughput */
-+void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer)
-+{
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct mlme_priv		*pmlmepriv = &(padapter->mlmepriv);
-+	struct registry_priv *registry_par = &padapter->registrypriv;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	u8 cur_wireless_mode = WIRELESS_INVALID;
-+
-+#ifdef CONFIG_USB_RX_AGGREGATION
-+	if (!registry_par->dynamic_agg_enable)
-+		return;
-+
-+#ifdef RTW_HALMAC
-+	if (IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8821CU(padapter) 
-+		|| IS_HARDWARE_TYPE_8822CU(padapter) || IS_HARDWARE_TYPE_8814BU(padapter)
-+		|| IS_HARDWARE_TYPE_8723FU(padapter))
-+		rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, NULL);
-+#else /* !RTW_HALMAC */
-+	if (IS_HARDWARE_TYPE_8821U(padapter)) { /* || IS_HARDWARE_TYPE_8192EU(padapter)) */
-+		/* This AGG_PH_TH only for UsbRxAggMode == USB_RX_AGG_USB */
-+		if ((pHalData->rxagg_mode == RX_AGG_USB) && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
-+			if (pdvobjpriv->traffic_stat.cur_tx_tp > 2 && pdvobjpriv->traffic_stat.cur_rx_tp < 30)
-+				rtw_write16(padapter , REG_RXDMA_AGG_PG_TH , 0x1010);
-+			else if (pdvobjpriv->traffic_stat.last_tx_bytes > 220000 && pdvobjpriv->traffic_stat.cur_rx_tp < 30)
-+				rtw_write16(padapter , REG_RXDMA_AGG_PG_TH , 0x1006);
-+			else
-+				rtw_write16(padapter, REG_RXDMA_AGG_PG_TH, 0x2005); /* dmc agg th 20K */
-+
-+			/* RTW_INFO("TX_TP=%u, RX_TP=%u\n", pdvobjpriv->traffic_stat.cur_tx_tp, pdvobjpriv->traffic_stat.cur_rx_tp); */
-+		}
-+	} else if (IS_HARDWARE_TYPE_8812(padapter)) {
-+#ifdef CONFIG_CONCURRENT_MODE
-+		u8 i;
-+		_adapter *iface;
-+		u8 bassocaed = _FALSE;
-+		struct mlme_ext_priv *mlmeext;
-+
-+		for (i = 0; i < pdvobjpriv->iface_nums; i++) {
-+			iface = pdvobjpriv->padapters[i];
-+			mlmeext = &iface->mlmeextpriv;
-+			if (rtw_linked_check(iface) == _TRUE) {
-+				if (mlmeext->cur_wireless_mode >= cur_wireless_mode)
-+					cur_wireless_mode = mlmeext->cur_wireless_mode;
-+				bassocaed = _TRUE;
-+			}
-+		}
-+		if (bassocaed)
-+#endif
-+			rtw_set_usb_agg_by_mode(padapter, cur_wireless_mode);
-+#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
-+	} else {
-+		rtw_set_usb_agg_by_mode(padapter, cur_wireless_mode);
-+#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
-+	}
-+#endif /* RTW_HALMAC */
-+#endif /* CONFIG_USB_RX_AGGREGATION */
-+
-+}
-+
-+/* bus-agg check for SoftAP mode */
-+inline u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel)
-+{
-+#ifdef CONFIG_AP_MODE
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	u8 chk_rst = _SUCCESS;
-+
-+	if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
-+		return chk_rst;
-+
-+	/* if((pre_qsel == 0xFF)||(next_qsel== 0xFF)) */
-+	/*	return chk_rst; */
-+
-+	if (((pre_qsel == QSLT_HIGH) || ((next_qsel == QSLT_HIGH)))
-+	    && (pre_qsel != next_qsel)) {
-+		/* RTW_INFO("### bus-agg break cause of qsel misatch, pre_qsel=0x%02x,next_qsel=0x%02x ###\n", */
-+		/*	pre_qsel,next_qsel); */
-+		chk_rst = _FAIL;
-+	}
-+	return chk_rst;
-+#else
-+	return _SUCCESS;
-+#endif /* CONFIG_AP_MODE */
-+}
-+
-+#ifdef CONFIG_WOWLAN
-+/*
-+ * Description:
-+ * dump_TX_FIFO: This is only used to dump TX_FIFO for debug WoW mode offload
-+ * contant.
-+ *
-+ * Input:
-+ * adapter: adapter pointer.
-+ * page_num: The max. page number that user want to dump.
-+ * page_size: page size of each page. eg. 128 bytes, 256 bytes, 512byte.
-+ */
-+void dump_TX_FIFO(_adapter *padapter, u8 page_num, u16 page_size)
-+{
-+
-+	int i;
-+	u8 val = 0;
-+	u8 base = 0;
-+	u32 addr = 0;
-+	u32 count = (page_size / 8);
-+
-+	if (page_num <= 0) {
-+		RTW_INFO("!!%s: incorrect input page_num paramter!\n", __func__);
-+		return;
-+	}
-+
-+	if (page_size < 128 || page_size > 512) {
-+		RTW_INFO("!!%s: incorrect input page_size paramter!\n", __func__);
-+		return;
-+	}
-+
-+	RTW_INFO("+%s+\n", __func__);
-+	val = rtw_read8(padapter, 0x106);
-+	rtw_write8(padapter, 0x106, 0x69);
-+	RTW_INFO("0x106: 0x%02x\n", val);
-+	base = rtw_read8(padapter, 0x209);
-+	RTW_INFO("0x209: 0x%02x\n", base);
-+
-+	addr = ((base)*page_size) / 8;
-+	for (i = 0 ; i < page_num * count ; i += 2) {
-+		rtw_write32(padapter, 0x140, addr + i);
-+		printk(" %08x %08x ", rtw_read32(padapter, 0x144), rtw_read32(padapter, 0x148));
-+		rtw_write32(padapter, 0x140, addr + i + 1);
-+		printk(" %08x %08x\n", rtw_read32(padapter, 0x144), rtw_read32(padapter, 0x148));
-+	}
-+}
-+#endif
-+
-+#ifdef CONFIG_GPIO_API
-+u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num)
-+{
-+	u8 value = 0;
-+	u8 direction = 0;
-+	u32 gpio_pin_input_val = REG_GPIO_PIN_CTRL;
-+	u32 gpio_pin_output_val = REG_GPIO_PIN_CTRL + 1;
-+	u32 gpio_pin_output_en = REG_GPIO_PIN_CTRL + 2;
-+	u8 gpio_num_to_set = gpio_num;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+
-+	if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)
-+		return value;
-+
-+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
-+
-+	RTW_INFO("rf_pwrstate=0x%02x\n", pwrpriv->rf_pwrstate);
-+	LeaveAllPowerSaveModeDirect(adapter);
-+
-+	if (gpio_num > 7) {
-+		gpio_pin_input_val = REG_GPIO_PIN_CTRL_2;
-+		gpio_pin_output_val = REG_GPIO_PIN_CTRL_2 + 1;
-+		gpio_pin_output_en = REG_GPIO_PIN_CTRL_2 + 2;
-+		gpio_num_to_set = gpio_num - 8;
-+	}
-+
-+	/* Read GPIO Direction */
-+	direction = (rtw_read8(adapter, gpio_pin_output_en) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
-+
-+	/* According the direction to read register value */
-+	if (direction)
-+		value =  (rtw_read8(adapter, gpio_pin_output_val) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
-+	else
-+		value =  (rtw_read8(adapter, gpio_pin_input_val) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
-+
-+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
-+	RTW_INFO("%s direction=%d value=%d\n", __FUNCTION__, direction, value);
-+
-+	return value;
-+}
-+
-+int  rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh)
-+{
-+	u8 direction = 0;
-+	u8 res = -1;
-+	u32 gpio_pin_output_val = REG_GPIO_PIN_CTRL + 1;
-+	u32 gpio_pin_output_en = REG_GPIO_PIN_CTRL + 2;
-+	u8 gpio_num_to_set = gpio_num;
-+
-+	if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)
-+		return -1;
-+
-+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
-+
-+	LeaveAllPowerSaveModeDirect(adapter);
-+
-+	if (gpio_num > 7) {
-+		gpio_pin_output_val = REG_GPIO_PIN_CTRL_2 + 1;
-+		gpio_pin_output_en = REG_GPIO_PIN_CTRL_2 + 2;
-+		gpio_num_to_set = gpio_num - 8;
-+	}
-+
-+	/* Read GPIO direction */
-+	direction = (rtw_read8(adapter, gpio_pin_output_en) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
-+
-+	/* If GPIO is output direction, setting value. */
-+	if (direction) {
-+		if (isHigh)
-+			rtw_write8(adapter, gpio_pin_output_val, rtw_read8(adapter, gpio_pin_output_val) | BIT(gpio_num_to_set));
-+		else
-+			rtw_write8(adapter, gpio_pin_output_val, rtw_read8(adapter, gpio_pin_output_val) & ~BIT(gpio_num_to_set));
-+
-+		RTW_INFO("%s Set gpio %x[%d]=%d\n", __FUNCTION__, REG_GPIO_PIN_CTRL + 1, gpio_num, isHigh);
-+		res = 0;
-+	} else {
-+		RTW_INFO("%s The gpio is input,not be set!\n", __FUNCTION__);
-+		res = -1;
-+	}
-+
-+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
-+	return res;
-+}
-+
-+int rtw_hal_config_gpio(_adapter *adapter, u8 gpio_num, bool isOutput)
-+{
-+	u32 gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL + 2;
-+	u8 gpio_num_to_set = gpio_num;
-+
-+	if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)
-+		return -1;
-+
-+	RTW_INFO("%s gpio_num =%d direction=%d\n", __FUNCTION__, gpio_num, isOutput);
-+
-+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
-+
-+	LeaveAllPowerSaveModeDirect(adapter);
-+
-+	rtw_hal_gpio_multi_func_reset(adapter, gpio_num);
-+
-+	if (gpio_num > 7) {
-+		gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL_2 + 2;
-+		gpio_num_to_set = gpio_num - 8;
-+	}
-+
-+	if (isOutput)
-+		rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) | BIT(gpio_num_to_set));
-+	else
-+		rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) & ~BIT(gpio_num_to_set));
-+
-+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
-+
-+	return 0;
-+}
-+int rtw_hal_register_gpio_interrupt(_adapter *adapter, int gpio_num, void(*callback)(u8 level))
-+{
-+	u8 value;
-+	u8 direction;
-+	PHAL_DATA_TYPE phal = GET_HAL_DATA(adapter);
-+
-+	if (IS_HARDWARE_TYPE_8188E(adapter)) {
-+		if (gpio_num > 7 || gpio_num < 4) {
-+			RTW_PRINT("%s The gpio number does not included 4~7.\n", __FUNCTION__);
-+			return -1;
-+		}
-+	}
-+
-+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
-+
-+	LeaveAllPowerSaveModeDirect(adapter);
-+
-+	/* Read GPIO direction */
-+	direction = (rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) & BIT(gpio_num)) >> gpio_num;
-+	if (direction) {
-+		RTW_PRINT("%s Can't register output gpio as interrupt.\n", __FUNCTION__);
-+		return -1;
-+	}
-+
-+	/* Config GPIO Mode */
-+	rtw_write8(adapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 3) | BIT(gpio_num));
-+
-+	/* Register GPIO interrupt handler*/
-+	adapter->gpiointpriv.callback[gpio_num] = callback;
-+
-+	/* Set GPIO interrupt mode, 0:positive edge, 1:negative edge */
-+	value = rtw_read8(adapter, REG_GPIO_PIN_CTRL) & BIT(gpio_num);
-+	adapter->gpiointpriv.interrupt_mode = rtw_read8(adapter, REG_HSIMR + 2) ^ value;
-+	rtw_write8(adapter, REG_GPIO_INTM, adapter->gpiointpriv.interrupt_mode);
-+
-+	/* Enable GPIO interrupt */
-+	adapter->gpiointpriv.interrupt_enable_mask = rtw_read8(adapter, REG_HSIMR + 2) | BIT(gpio_num);
-+	rtw_write8(adapter, REG_HSIMR + 2, adapter->gpiointpriv.interrupt_enable_mask);
-+
-+	rtw_hal_update_hisr_hsisr_ind(adapter, 1);
-+
-+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
-+
-+	return 0;
-+}
-+int rtw_hal_disable_gpio_interrupt(_adapter *adapter, int gpio_num)
-+{
-+	u8 value;
-+	u8 direction;
-+	PHAL_DATA_TYPE phal = GET_HAL_DATA(adapter);
-+
-+	if (IS_HARDWARE_TYPE_8188E(adapter)) {
-+		if (gpio_num > 7 || gpio_num < 4) {
-+			RTW_INFO("%s The gpio number does not included 4~7.\n", __FUNCTION__);
-+			return -1;
-+		}
-+	}
-+
-+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
-+
-+	LeaveAllPowerSaveModeDirect(adapter);
-+
-+	/* Config GPIO Mode */
-+	rtw_write8(adapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(gpio_num));
-+
-+	/* Unregister GPIO interrupt handler*/
-+	adapter->gpiointpriv.callback[gpio_num] = NULL;
-+
-+	/* Reset GPIO interrupt mode, 0:positive edge, 1:negative edge */
-+	adapter->gpiointpriv.interrupt_mode = rtw_read8(adapter, REG_GPIO_INTM) & ~BIT(gpio_num);
-+	rtw_write8(adapter, REG_GPIO_INTM, 0x00);
-+
-+	/* Disable GPIO interrupt */
-+	adapter->gpiointpriv.interrupt_enable_mask = rtw_read8(adapter, REG_HSIMR + 2) & ~BIT(gpio_num);
-+	rtw_write8(adapter, REG_HSIMR + 2, adapter->gpiointpriv.interrupt_enable_mask);
-+
-+	if (!adapter->gpiointpriv.interrupt_enable_mask)
-+		rtw_hal_update_hisr_hsisr_ind(adapter, 0);
-+
-+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
-+
-+	return 0;
-+}
-+#endif
-+
-+s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+	u8 i;
-+
-+	for (i = 0; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++) {
-+		if ((pHalData->iqk_reg_backup[i].central_chnl != 0)) {
-+			if ((pHalData->iqk_reg_backup[i].central_chnl == central_chnl)
-+			    && (pHalData->iqk_reg_backup[i].bw_mode == bw_mode))
-+				return i;
-+		}
-+	}
-+
-+	return -1;
-+}
-+
-+void rtw_hal_ch_sw_iqk_info_backup(_adapter *padapter)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+	s8 res;
-+	u8 i;
-+
-+	/* If it's an existed record, overwrite it */
-+	res = rtw_hal_ch_sw_iqk_info_search(padapter, pHalData->current_channel, pHalData->current_channel_bw);
-+	if ((res >= 0) && (res < MAX_IQK_INFO_BACKUP_CHNL_NUM)) {
-+		rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[res]));
-+		return;
-+	}
-+
-+	/* Search for the empty record to use */
-+	for (i = 0; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++) {
-+		if (pHalData->iqk_reg_backup[i].central_chnl == 0) {
-+			rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[i]));
-+			return;
-+		}
-+	}
-+
-+	/* Else, overwrite the oldest record */
-+	for (i = 1; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++)
-+		_rtw_memcpy(&(pHalData->iqk_reg_backup[i - 1]), &(pHalData->iqk_reg_backup[i]), sizeof(struct hal_iqk_reg_backup));
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM - 1]));
-+}
-+
-+void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case)
-+{
-+	rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_RESTORE, &ch_sw_use_case);
-+}
-+
-+void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)
-+{
-+	u32	mac_cck_ok = 0, mac_ofdm_ok = 0, mac_ht_ok = 0, mac_vht_ok = 0;
-+	u32	mac_cck_err = 0, mac_ofdm_err = 0, mac_ht_err = 0, mac_vht_err = 0;
-+	u32	mac_cck_fa = 0, mac_ofdm_fa = 0, mac_ht_fa = 0;
-+	u32	DropPacket = 0;
-+
-+	if (!rx_counter) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter))
-+		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
-+
-+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x3);
-+	mac_cck_ok	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	  */
-+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);
-+	mac_ofdm_ok	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
-+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x6);
-+	mac_ht_ok	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
-+	mac_vht_ok	= 0;
-+	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
-+		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);
-+		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1);
-+		mac_vht_ok	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/
-+		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
-+	}
-+
-+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x4);
-+	mac_cck_err	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
-+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);
-+	mac_ofdm_err	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
-+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x7);
-+	mac_ht_err	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]		 */
-+	mac_vht_err	= 0;
-+	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
-+		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);
-+		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1);
-+		mac_vht_err	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/
-+		phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
-+	}
-+
-+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x5);
-+	mac_cck_fa	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
-+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x2);
-+	mac_ofdm_fa	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]	 */
-+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x9);
-+	mac_ht_fa	= phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]		 */
-+
-+	/* Mac_DropPacket */
-+	rtw_write32(padapter, REG_RXERR_RPT, (rtw_read32(padapter, REG_RXERR_RPT) & 0x0FFFFFFF) | Mac_DropPacket);
-+	DropPacket = rtw_read32(padapter, REG_RXERR_RPT) & 0x0000FFFF;
-+
-+	rx_counter->rx_pkt_ok = mac_cck_ok + mac_ofdm_ok + mac_ht_ok + mac_vht_ok;
-+	rx_counter->rx_pkt_crc_error = mac_cck_err + mac_ofdm_err + mac_ht_err + mac_vht_err;
-+	rx_counter->rx_cck_fa = mac_cck_fa;
-+	rx_counter->rx_ofdm_fa = mac_ofdm_fa;
-+	rx_counter->rx_ht_fa = mac_ht_fa;
-+	rx_counter->rx_pkt_drop = DropPacket;
-+}
-+void rtw_reset_mac_rx_counters(_adapter *padapter)
-+{
-+
-+	/* If no packet rx, MaxRx clock be gating ,BIT_DISGCLK bit19 set 1 for fix*/
-+	if (IS_HARDWARE_TYPE_8703B(padapter) ||
-+		IS_HARDWARE_TYPE_8723D(padapter) ||
-+		IS_HARDWARE_TYPE_8188F(padapter) ||
-+		IS_HARDWARE_TYPE_8188GTV(padapter) ||
-+		IS_HARDWARE_TYPE_8192F(padapter) ||
-+		IS_HARDWARE_TYPE_8822C(padapter))
-+		phy_set_mac_reg(padapter, REG_RCR, BIT19, 0x1);
-+
-+	/* reset mac counter */
-+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x1);
-+	phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x0);
-+}
-+
-+void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)
-+{
-+	u32 cckok = 0, cckcrc = 0, ofdmok = 0, ofdmcrc = 0, htok = 0, htcrc = 0, OFDM_FA = 0, CCK_FA = 0, vht_ok = 0, vht_err = 0;
-+	if (!rx_counter) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
-+		cckok	= phy_query_bb_reg(padapter, 0xF04, 0x3FFF);	     /* [13:0] */
-+		ofdmok	= phy_query_bb_reg(padapter, 0xF14, 0x3FFF);	     /* [13:0] */
-+		htok		= phy_query_bb_reg(padapter, 0xF10, 0x3FFF);     /* [13:0] */
-+		vht_ok	= phy_query_bb_reg(padapter, 0xF0C, 0x3FFF);     /* [13:0] */
-+		cckcrc	= phy_query_bb_reg(padapter, 0xF04, 0x3FFF0000); /* [29:16]	 */
-+		ofdmcrc	= phy_query_bb_reg(padapter, 0xF14, 0x3FFF0000); /* [29:16] */
-+		htcrc	= phy_query_bb_reg(padapter, 0xF10, 0x3FFF0000); /* [29:16] */
-+		vht_err	= phy_query_bb_reg(padapter, 0xF0C, 0x3FFF0000); /* [29:16] */
-+		CCK_FA	= phy_query_bb_reg(padapter, 0xA5C, bMaskLWord);
-+		OFDM_FA	= phy_query_bb_reg(padapter, 0xF48, bMaskLWord);
-+	} else if(IS_HARDWARE_TYPE_JAGUAR3(padapter)){
-+		cckok = phy_query_bb_reg(padapter, 0x2c04, 0xffff);
-+		ofdmok = phy_query_bb_reg(padapter, 0x2c14, 0xffff);
-+		htok = phy_query_bb_reg(padapter, 0x2c10, 0xffff);
-+		vht_ok = phy_query_bb_reg(padapter, 0x2c0c, 0xffff);
-+		cckcrc = phy_query_bb_reg(padapter, 0x2c04, 0xffff0000);
-+		ofdmcrc = phy_query_bb_reg(padapter, 0x2c14, 0xffff0000);
-+		htcrc = phy_query_bb_reg(padapter, 0x2c10, 0xffff0000);
-+		vht_err = phy_query_bb_reg(padapter, 0x2c0c, 0xffff0000);
-+		CCK_FA	= phy_query_bb_reg(padapter, 0x1a5c, bMaskLWord);
-+		OFDM_FA = phy_query_bb_reg(padapter, 0x2d00, bMaskLWord) - phy_query_bb_reg(padapter, 0x2de0, bMaskLWord);
-+	} else if(IS_HARDWARE_TYPE_JAGUAR3_11N(padapter)){
-+		cckok = phy_query_bb_reg(padapter, 0x2aac, 0xffff);
-+		ofdmok = phy_query_bb_reg(padapter, 0x2c14, 0xffff);
-+		htok = phy_query_bb_reg(padapter, 0x2c10, 0xffff);
-+		cckcrc = phy_query_bb_reg(padapter, 0x2aac, 0xffff0000);
-+		ofdmcrc = phy_query_bb_reg(padapter, 0x2c14, 0xffff0000);
-+		htcrc = phy_query_bb_reg(padapter, 0x2c10, 0xffff0000);
-+		CCK_FA	= phy_query_bb_reg(padapter, 0x2aa8, 0xffff0000) + phy_query_bb_reg(padapter, 0x2aa8, 0x0000ffff);
-+		OFDM_FA = phy_query_bb_reg(padapter, 0x2d00, bMaskLWord) - phy_query_bb_reg(padapter, 0x2de0, bMaskLWord);
-+	} else {
-+		cckok	= phy_query_bb_reg(padapter, 0xF88, bMaskDWord);
-+		ofdmok	= phy_query_bb_reg(padapter, 0xF94, bMaskLWord);
-+		htok		= phy_query_bb_reg(padapter, 0xF90, bMaskLWord);
-+		vht_ok	= 0;
-+		cckcrc	= phy_query_bb_reg(padapter, 0xF84, bMaskDWord);
-+		ofdmcrc	= phy_query_bb_reg(padapter, 0xF94, bMaskHWord);
-+		htcrc	= phy_query_bb_reg(padapter, 0xF90, bMaskHWord);
-+		vht_err	= 0;
-+		OFDM_FA = phy_query_bb_reg(padapter, 0xCF0, bMaskLWord) + phy_query_bb_reg(padapter, 0xCF2, bMaskLWord) +
-+			phy_query_bb_reg(padapter, 0xDA2, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA4, bMaskLWord) +
-+			phy_query_bb_reg(padapter, 0xDA6, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA8, bMaskLWord);
-+
-+		CCK_FA = (rtw_read8(padapter, 0xA5B) << 8) | (rtw_read8(padapter, 0xA5C));
-+	}
-+
-+	rx_counter->rx_pkt_ok = cckok + ofdmok + htok + vht_ok;
-+	rx_counter->rx_pkt_crc_error = cckcrc + ofdmcrc + htcrc + vht_err;
-+	rx_counter->rx_ofdm_fa = OFDM_FA;
-+	rx_counter->rx_cck_fa = CCK_FA;
-+
-+}
-+
-+void rtw_reset_phy_trx_ok_counters(_adapter *padapter)
-+{
-+	if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
-+		phy_set_bb_reg(padapter, 0xB58, BIT0, 0x1);
-+		phy_set_bb_reg(padapter, 0xB58, BIT0, 0x0);
-+	} else if(IS_HARDWARE_TYPE_JAGUAR3(padapter) || IS_HARDWARE_TYPE_JAGUAR3_11N(padapter)) {
-+		phy_set_bb_reg(padapter, 0x1EB4, BIT25, 0x1);
-+		phy_set_bb_reg(padapter, 0x1EB4, BIT25, 0x0);
-+	} else {
-+		phy_set_bb_reg(padapter, 0xF14, BIT16, 0x1);
-+		phy_set_bb_reg(padapter, 0xF14, BIT16, 0x0);
-+	}
-+}
-+
-+void rtw_reset_phy_rx_counters(_adapter *padapter)
-+{
-+	/* reset phy counter */
-+	if (IS_HARDWARE_TYPE_JAGUAR3(padapter)) {
-+		/* reset CCK FA counter */
-+		phy_set_bb_reg(padapter, 0x1a2c, BIT(15) | BIT(14), 0);
-+		phy_set_bb_reg(padapter, 0x1a2c, BIT(15) | BIT(14), 2);
-+
-+		/* reset CCK CCA counter */
-+		phy_set_bb_reg(padapter, 0x1a2c, BIT(13) | BIT(12), 0);
-+		phy_set_bb_reg(padapter, 0x1a2c, BIT(13) | BIT(12), 2);
-+
-+	} else if (IS_HARDWARE_TYPE_JAGUAR3_11N(padapter)) {
-+		/* reset CCK FA and CCK CCA counter */
-+		phy_set_bb_reg(padapter, 0x2a44, BIT21, 0);
-+		phy_set_bb_reg(padapter, 0x2a44, BIT21, 1);
-+		rtw_reset_phy_trx_ok_counters(padapter);
-+
-+	} else if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
-+		rtw_reset_phy_trx_ok_counters(padapter);
-+
-+		phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x1);/* reset  OFDA FA counter */
-+		phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x0);
-+
-+		phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset  CCK FA counter */
-+		phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1);
-+	} else {
-+		phy_set_bb_reg(padapter, 0xF14, BIT16, 0x1);
-+		rtw_msleep_os(10);
-+		phy_set_bb_reg(padapter, 0xF14, BIT16, 0x0);
-+
-+		phy_set_bb_reg(padapter, 0xD00, BIT27, 0x1);/* reset  OFDA FA counter */
-+		phy_set_bb_reg(padapter, 0xC0C, BIT31, 0x1);/* reset  OFDA FA counter */
-+		phy_set_bb_reg(padapter, 0xD00, BIT27, 0x0);
-+		phy_set_bb_reg(padapter, 0xC0C, BIT31, 0x0);
-+
-+		phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset  CCK FA counter */
-+		phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1);
-+	}
-+}
-+#ifdef DBG_RX_COUNTER_DUMP
-+void rtw_dump_drv_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)
-+{
-+	struct recv_priv *precvpriv = &padapter->recvpriv;
-+	if (!rx_counter) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+	rx_counter->rx_pkt_ok = padapter->drv_rx_cnt_ok;
-+	rx_counter->rx_pkt_crc_error = padapter->drv_rx_cnt_crcerror;
-+	rx_counter->rx_pkt_drop = precvpriv->rx_drop - padapter->drv_rx_cnt_drop;
-+}
-+void rtw_reset_drv_rx_counters(_adapter *padapter)
-+{
-+	struct recv_priv *precvpriv = &padapter->recvpriv;
-+	padapter->drv_rx_cnt_ok = 0;
-+	padapter->drv_rx_cnt_crcerror = 0;
-+	padapter->drv_rx_cnt_drop = precvpriv->rx_drop;
-+}
-+void rtw_dump_phy_rxcnts_preprocess(_adapter *padapter, u8 rx_cnt_mode)
-+{
-+	u8 initialgain;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
-+
-+	if ((!(padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER)) && (rx_cnt_mode & DUMP_PHY_RX_COUNTER)) {
-+		rtw_hal_get_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, NULL);
-+		RTW_INFO("%s CurIGValue:0x%02x\n", __FUNCTION__, initialgain);
-+		rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);
-+		/*disable dynamic functions, such as high power, DIG*/
-+		rtw_phydm_ability_backup(padapter);
-+		rtw_phydm_func_clr(padapter, (ODM_BB_DIG | ODM_BB_FA_CNT));
-+	} else if ((padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER) && (!(rx_cnt_mode & DUMP_PHY_RX_COUNTER))) {
-+		/* turn on phy-dynamic functions */
-+		rtw_phydm_ability_restore(padapter);
-+		initialgain = 0xff; /* restore RX GAIN */
-+		rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);
-+
-+	}
-+}
-+
-+void rtw_dump_rx_counters(_adapter *padapter)
-+{
-+	struct dbg_rx_counter rx_counter;
-+
-+	if (padapter->dump_rx_cnt_mode & DUMP_DRV_RX_COUNTER) {
-+		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
-+		rtw_dump_drv_rx_counters(padapter, &rx_counter);
-+		RTW_INFO("Drv Received packet OK:%d CRC error:%d Drop Packets: %d\n",
-+			rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_pkt_drop);
-+		rtw_reset_drv_rx_counters(padapter);
-+	}
-+
-+	if (padapter->dump_rx_cnt_mode & DUMP_MAC_RX_COUNTER) {
-+		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
-+		rtw_dump_mac_rx_counters(padapter, &rx_counter);
-+		RTW_INFO("Mac Received packet OK:%d CRC error:%d FA Counter: %d Drop Packets: %d\n",
-+			 rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error,
-+			rx_counter.rx_cck_fa + rx_counter.rx_ofdm_fa + rx_counter.rx_ht_fa,
-+			 rx_counter.rx_pkt_drop);
-+		rtw_reset_mac_rx_counters(padapter);
-+	}
-+
-+	if (padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER) {
-+		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
-+		rtw_dump_phy_rx_counters(padapter, &rx_counter);
-+		/* RTW_INFO("%s: OFDM_FA =%d\n", __FUNCTION__, rx_counter.rx_ofdm_fa); */
-+		/* RTW_INFO("%s: CCK_FA =%d\n", __FUNCTION__, rx_counter.rx_cck_fa); */
-+		RTW_INFO("Phy Received packet OK:%d CRC error:%d FA Counter: %d\n", rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error,
-+			 rx_counter.rx_ofdm_fa + rx_counter.rx_cck_fa);
-+		rtw_reset_phy_rx_counters(padapter);
-+	}
-+}
-+#endif
-+u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
-+	u8 curr_tx_sgi = 0;
-+	struct ra_sta_info *ra_info;
-+
-+	if (!psta)
-+		return curr_tx_sgi;
-+
-+	if (padapter->fix_rate == 0xff) {
-+#if defined(CONFIG_RTL8188E)
-+#if (RATE_ADAPTIVE_SUPPORT == 1)
-+		curr_tx_sgi = hal_data->odmpriv.ra_info[psta->cmn.mac_id].rate_sgi;
-+#endif /* (RATE_ADAPTIVE_SUPPORT == 1)*/
-+#else
-+		ra_info = &psta->cmn.ra_info;
-+		curr_tx_sgi = ((ra_info->curr_tx_rate) & 0x80) >> 7;
-+#endif
-+	} else {
-+		curr_tx_sgi = ((padapter->fix_rate) & 0x80) >> 7;
-+	}
-+
-+	return curr_tx_sgi;
-+}
-+
-+u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
-+	u8 rate_id = 0;
-+	struct ra_sta_info *ra_info;
-+
-+	if (!psta)
-+		return rate_id;
-+
-+	if (padapter->fix_rate == 0xff) {
-+#if defined(CONFIG_RTL8188E)
-+#if (RATE_ADAPTIVE_SUPPORT == 1)
-+		rate_id = hal_data->odmpriv.ra_info[psta->cmn.mac_id].decision_rate;
-+#endif /* (RATE_ADAPTIVE_SUPPORT == 1)*/
-+#else
-+		ra_info = &psta->cmn.ra_info;
-+		rate_id = ra_info->curr_tx_rate & 0x7f;
-+#endif
-+	} else {
-+		rate_id = padapter->fix_rate & 0x7f;
-+	}
-+
-+	return rate_id;
-+}
-+
-+void update_IOT_info(_adapter *padapter)
-+{
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	switch (pmlmeinfo->assoc_AP_vendor) {
-+	case HT_IOT_PEER_MARVELL:
-+		pmlmeinfo->turboMode_cts2self = 1;
-+		pmlmeinfo->turboMode_rtsen = 0;
-+		break;
-+
-+	case HT_IOT_PEER_RALINK:
-+		pmlmeinfo->turboMode_cts2self = 0;
-+		pmlmeinfo->turboMode_rtsen = 1;
-+		break;
-+	case HT_IOT_PEER_REALTEK:
-+		/* rtw_write16(padapter, 0x4cc, 0xffff); */
-+		/* rtw_write16(padapter, 0x546, 0x01c0); */
-+		break;
-+	default:
-+		pmlmeinfo->turboMode_cts2self = 0;
-+		pmlmeinfo->turboMode_rtsen = 1;
-+		break;
-+	}
-+
-+}
-+#ifdef CONFIG_RTS_FULL_BW 
-+/*
-+8188E: not support full RTS BW feature(mac REG no define 480[5])
-+*/
-+void rtw_set_rts_bw(_adapter *padapter) {
-+	int i;
-+	u8 enable = 1;
-+	bool connect_to_8812 = _FALSE;
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	struct sta_info *station = NULL;
-+
-+	for (i = 0; i < macid_ctl->num; i++) {
-+		if (rtw_macid_is_used(macid_ctl, i)) {
-+
-+			station = NULL;
-+			station = macid_ctl->sta[i];
-+			if(station) {
-+				
-+				 _adapter *sta_adapter =station->padapter;
-+				struct mlme_ext_priv	*pmlmeext = &(sta_adapter->mlmeextpriv);
-+				struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+				
-+				if ( pmlmeinfo->state != WIFI_FW_NULL_STATE) {
-+					if(_rtw_memcmp(macid_ctl->sta[i]->cmn.mac_addr, bc_addr, ETH_ALEN) !=  _TRUE) {
-+						if (  macid_ctl->sta[i]->vendor_8812) {
-+							connect_to_8812 = _TRUE;
-+							enable = 0;
-+						}	
-+					}	
-+				}
-+			}
-+		}
-+
-+		if(connect_to_8812)
-+			break;
-+	}
-+	
-+		RTW_INFO("%s connect_to_8812=%d,enable=%u\n", __FUNCTION__,connect_to_8812,enable);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_SET_RTS_BW, &enable);
-+}
-+#endif/*CONFIG_RTS_FULL_BW*/
-+
-+int hal_spec_init(_adapter *adapter)
-+{
-+	u8 interface_type = 0;
-+	int ret = _SUCCESS;
-+
-+	interface_type = rtw_get_intf_type(adapter);
-+
-+	switch (rtw_get_chip_type(adapter)) {
-+#ifdef CONFIG_RTL8723B
-+	case RTL8723B:
-+		init_hal_spec_8723b(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8703B
-+	case RTL8703B:
-+		init_hal_spec_8703b(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8723D
-+	case RTL8723D:
-+		init_hal_spec_8723d(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8188E
-+	case RTL8188E:
-+		init_hal_spec_8188e(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8188F
-+	case RTL8188F:
-+		init_hal_spec_8188f(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8188GTV
-+	case RTL8188GTV:
-+		init_hal_spec_8188gtv(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8812A
-+	case RTL8812:
-+		init_hal_spec_8812a(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8821A
-+	case RTL8821:
-+		init_hal_spec_8821a(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8192E
-+	case RTL8192E:
-+		init_hal_spec_8192e(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8814A
-+	case RTL8814A:
-+		init_hal_spec_8814a(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8822B
-+	case RTL8822B:
-+		rtl8822b_init_hal_spec(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8821C
-+	case RTL8821C:
-+		init_hal_spec_rtl8821c(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8710B
-+	case RTL8710B:
-+		init_hal_spec_8710b(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8192F
-+	case RTL8192F:
-+		init_hal_spec_8192f(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8822C
-+	case RTL8822C:
-+		rtl8822c_init_hal_spec(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8814B
-+	case RTL8814B:
-+		rtl8814b_init_hal_spec(adapter);
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8723F
-+	case RTL8723F:
-+		rtl8723f_init_hal_spec(adapter);
-+		break;
-+#endif
-+	default:
-+		RTW_ERR("%s: unknown chip_type:%u\n"
-+			, __func__, rtw_get_chip_type(adapter));
-+		ret = _FAIL;
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+static const char *const _band_cap_str[] = {
-+	/* BIT0 */"2G",
-+	/* BIT1 */"5G",
-+};
-+
-+static const char *const _bw_cap_str[] = {
-+	/* BIT0 */"5M",
-+	/* BIT1 */"10M",
-+	/* BIT2 */"20M",
-+	/* BIT3 */"40M",
-+	/* BIT4 */"80M",
-+	/* BIT5 */"160M",
-+	/* BIT6 */"80_80M",
-+};
-+
-+static const char *const _proto_cap_str[] = {
-+	/* BIT0 */"b",
-+	/* BIT1 */"g",
-+	/* BIT2 */"n",
-+	/* BIT3 */"ac",
-+};
-+
-+static const char *const _wl_func_str[] = {
-+	/* BIT0 */"P2P",
-+	/* BIT1 */"MIRACAST",
-+	/* BIT2 */"TDLS",
-+	/* BIT3 */"FTM",
-+};
-+
-+void dump_hal_spec(void *sel, _adapter *adapter)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	int i;
-+
-+	RTW_PRINT_SEL(sel, "macid_num:%u\n", hal_spec->macid_num);
-+	RTW_PRINT_SEL(sel, "macid_cap:%u\n", hal_spec->macid_cap);
-+	RTW_PRINT_SEL(sel, "sec_cap:0x%02x\n", hal_spec->sec_cap);
-+	RTW_PRINT_SEL(sel, "sec_cam_ent_num:%u\n", hal_spec->sec_cam_ent_num);
-+
-+	RTW_PRINT_SEL(sel, "rfpath_num_2g:%u\n", hal_spec->rfpath_num_2g);
-+	RTW_PRINT_SEL(sel, "rfpath_num_5g:%u\n", hal_spec->rfpath_num_5g);
-+	RTW_PRINT_SEL(sel, "rf_reg_path_num:%u\n", hal_spec->rf_reg_path_num);
-+	RTW_PRINT_SEL(sel, "rf_reg_path_avail_num:%u\n", hal_spec->rf_reg_path_avail_num);
-+	RTW_PRINT_SEL(sel, "rf_reg_trx_path_bmp:0x%02x\n", hal_spec->rf_reg_trx_path_bmp);
-+	RTW_PRINT_SEL(sel, "max_tx_cnt:%u\n", hal_spec->max_tx_cnt);
-+
-+	RTW_PRINT_SEL(sel, "tx_nss_num:%u\n", hal_spec->tx_nss_num);
-+	RTW_PRINT_SEL(sel, "rx_nss_num:%u\n", hal_spec->rx_nss_num);
-+
-+	RTW_PRINT_SEL(sel, "band_cap:");
-+	for (i = 0; i < BAND_CAP_BIT_NUM; i++) {
-+		if (((hal_spec->band_cap) >> i) & BIT0 && _band_cap_str[i])
-+			_RTW_PRINT_SEL(sel, "%s ", _band_cap_str[i]);
-+	}
-+	_RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "bw_cap:");
-+	for (i = 0; i < BW_CAP_BIT_NUM; i++) {
-+		if (((hal_spec->bw_cap) >> i) & BIT0 && _bw_cap_str[i])
-+			_RTW_PRINT_SEL(sel, "%s ", _bw_cap_str[i]);
-+	}
-+	_RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "proto_cap:");
-+	for (i = 0; i < PROTO_CAP_BIT_NUM; i++) {
-+		if (((hal_spec->proto_cap) >> i) & BIT0 && _proto_cap_str[i])
-+			_RTW_PRINT_SEL(sel, "%s ", _proto_cap_str[i]);
-+	}
-+	_RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "txgi_max:%u\n", hal_spec->txgi_max);
-+	RTW_PRINT_SEL(sel, "txgi_pdbm:%u\n", hal_spec->txgi_pdbm);
-+
-+	RTW_PRINT_SEL(sel, "wl_func:");
-+	for (i = 0; i < WL_FUNC_BIT_NUM; i++) {
-+		if (((hal_spec->wl_func) >> i) & BIT0 && _wl_func_str[i])
-+			_RTW_PRINT_SEL(sel, "%s ", _wl_func_str[i]);
-+	}
-+	_RTW_PRINT_SEL(sel, "\n");
-+
-+#if CONFIG_TX_AC_LIFETIME
-+	RTW_PRINT_SEL(sel, "tx_aclt_unit_factor:%u (unit:%uus)\n"
-+		, hal_spec->tx_aclt_unit_factor, hal_spec->tx_aclt_unit_factor * 32);
-+#endif
-+
-+	RTW_PRINT_SEL(sel, "rx_tsf_filter:%u\n", hal_spec->rx_tsf_filter);
-+
-+	RTW_PRINT_SEL(sel, "pg_txpwr_saddr:0x%X\n", hal_spec->pg_txpwr_saddr);
-+	RTW_PRINT_SEL(sel, "pg_txgi_diff_factor:%u\n", hal_spec->pg_txgi_diff_factor);
-+}
-+
-+inline bool hal_chk_band_cap(_adapter *adapter, u8 cap)
-+{
-+	return GET_HAL_SPEC(adapter)->band_cap & cap;
-+}
-+
-+inline bool hal_chk_bw_cap(_adapter *adapter, u8 cap)
-+{
-+	return GET_HAL_SPEC(adapter)->bw_cap & cap;
-+}
-+
-+inline bool hal_chk_proto_cap(_adapter *adapter, u8 cap)
-+{
-+	return GET_HAL_SPEC(adapter)->proto_cap & cap;
-+}
-+
-+inline bool hal_chk_wl_func(_adapter *adapter, u8 func)
-+{
-+	return GET_HAL_SPEC(adapter)->wl_func & func;
-+}
-+
-+inline bool hal_is_band_support(_adapter *adapter, u8 band)
-+{
-+	return GET_HAL_SPEC(adapter)->band_cap & band_to_band_cap(band);
-+}
-+
-+inline bool hal_is_bw_support(_adapter *adapter, u8 bw)
-+{
-+	return GET_HAL_SPEC(adapter)->bw_cap & ch_width_to_bw_cap(bw);
-+}
-+
-+inline bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode)
-+{
-+	u8 proto_cap = GET_HAL_SPEC(adapter)->proto_cap;
-+
-+	if (mode == WIRELESS_11B)
-+		if ((proto_cap & PROTO_CAP_11B) && hal_chk_band_cap(adapter, BAND_CAP_2G))
-+			return 1;
-+
-+	if (mode == WIRELESS_11G)
-+		if ((proto_cap & PROTO_CAP_11G) && hal_chk_band_cap(adapter, BAND_CAP_2G))
-+			return 1;
-+
-+	if (mode == WIRELESS_11A)
-+		if ((proto_cap & PROTO_CAP_11G) && hal_chk_band_cap(adapter, BAND_CAP_5G))
-+			return 1;
-+
-+	if (mode == WIRELESS_11_24N)
-+		if ((proto_cap & PROTO_CAP_11N) && hal_chk_band_cap(adapter, BAND_CAP_2G))
-+			return 1;
-+
-+	if (mode == WIRELESS_11_5N)
-+		if ((proto_cap & PROTO_CAP_11N) && hal_chk_band_cap(adapter, BAND_CAP_5G))
-+			return 1;
-+
-+	if (mode == WIRELESS_11AC)
-+		if ((proto_cap & PROTO_CAP_11AC) && hal_chk_band_cap(adapter, BAND_CAP_5G))
-+			return 1;
-+
-+	return 0;
-+}
-+inline bool hal_is_mimo_support(_adapter *adapter)
-+{
-+	if ((GET_HAL_TX_NSS(adapter) == 1) &&
-+		(GET_HAL_RX_NSS(adapter) == 1))
-+		return 0;
-+	return 1;
-+}
-+
-+/*
-+* hal_largest_bw - starting from in_bw, get largest bw supported by HAL
-+* @adapter:
-+* @in_bw: starting bw, value of enum channel_width
-+*
-+* Returns: value of enum channel_width
-+*/
-+u8 hal_largest_bw(_adapter *adapter, u8 in_bw)
-+{
-+	for (; in_bw > CHANNEL_WIDTH_20; in_bw--) {
-+		if (hal_is_bw_support(adapter, in_bw))
-+			break;
-+	}
-+
-+	if (!hal_is_bw_support(adapter, in_bw))
-+		rtw_warn_on(1);
-+
-+	return in_bw;
-+}
-+
-+#ifndef CONFIG_HAS_TX_BEACON_PAUSE
-+void ResumeTxBeacon(_adapter *padapter)
-+{
-+	RTW_DBG("ResumeTxBeacon\n");
-+	#ifdef CONFIG_STOP_RESUME_BCN_BY_TXPAUSE
-+	rtw_write8(padapter, REG_TXPAUSE,
-+		rtw_read8(padapter, REG_TXPAUSE) & (~BIT6));
-+	#else
-+	rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
-+		rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) | BIT(6));
-+	#endif
-+
-+#ifdef RTW_HALMAC
-+	/* Add this for driver using HALMAC because driver doesn't have setup time init by self */
-+	/* TBTT setup time */
-+	rtw_write8(padapter, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME);
-+#endif
-+
-+	/* TBTT hold time: 0x540[19:8] */
-+	rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME & 0xFF);
-+	rtw_write8(padapter, REG_TBTT_PROHIBIT + 2,
-+		(rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME >> 8));
-+}
-+
-+void StopTxBeacon(_adapter *padapter)
-+{
-+	RTW_DBG("StopTxBeacon\n");
-+	#ifdef CONFIG_STOP_RESUME_BCN_BY_TXPAUSE
-+	rtw_write8(padapter, REG_TXPAUSE,
-+	rtw_read8(padapter, REG_TXPAUSE) | BIT6);
-+	#else
-+	rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
-+		rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) & (~BIT6));
-+	#endif
-+
-+	/* TBTT hold time: 0x540[19:8] */
-+	rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);
-+	rtw_write8(padapter, REG_TBTT_PROHIBIT + 2,
-+		(rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));
-+}
-+#endif /* CONFIG_HAS_TX_BEACON_PAUSE */
-+
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM /*HW port0 - MBSS*/
-+
-+#ifdef CONFIG_CLIENT_PORT_CFG
-+const u8 _clt_port_id[MAX_CLIENT_PORT_NUM] = {
-+	CLT_PORT0,
-+	CLT_PORT1,
-+	CLT_PORT2,
-+	CLT_PORT3
-+};
-+
-+void rtw_clt_port_init(struct clt_port_t  *cltp)
-+{
-+	cltp->bmp = 0;
-+	cltp->num = 0;
-+	_rtw_spinlock_init(&cltp->lock);
-+}
-+void rtw_clt_port_deinit(struct clt_port_t *cltp)
-+{
-+	_rtw_spinlock_free(&cltp->lock);
-+}
-+static void _hw_client_port_alloc(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct clt_port_t  *cltp = &dvobj->clt_port;
-+	_irqL irql;
-+	int i;
-+
-+	#if 0
-+	if (cltp->num > MAX_CLIENT_PORT_NUM) {
-+		RTW_ERR(ADPT_FMT" cann't  alloc client (%d)\n", ADPT_ARG(adapter), cltp->num);
-+		rtw_warn_on(1);
-+		return;
-+	}
-+	#endif
-+
-+	if (adapter->client_id !=  MAX_CLIENT_PORT_NUM) {
-+		RTW_INFO(ADPT_FMT" client_id %d has allocated port:%d\n",
-+			ADPT_ARG(adapter), adapter->client_id, adapter->client_port);
-+		return;
-+	}
-+	_enter_critical_bh(&cltp->lock, &irql);
-+	for (i = 0; i < MAX_CLIENT_PORT_NUM; i++) {
-+		if (!(cltp->bmp & BIT(i)))
-+			break;
-+	}
-+
-+	if (i < MAX_CLIENT_PORT_NUM) {
-+		adapter->client_id = i;
-+		cltp->bmp |= BIT(i);
-+		adapter->client_port = _clt_port_id[i];
-+	}
-+	cltp->num++;
-+	_exit_critical_bh(&cltp->lock, &irql);
-+	RTW_INFO("%s("ADPT_FMT")id:%d, port:%d clt_num:%d\n",
-+		__func__, ADPT_ARG(adapter), adapter->client_id, adapter->client_port, cltp->num);
-+}
-+static void _hw_client_port_free(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct clt_port_t  *cltp = &dvobj->clt_port;
-+	_irqL irql;
-+
-+	#if 0
-+	if (adapter->client_id >=  MAX_CLIENT_PORT_NUM) {
-+		RTW_ERR(ADPT_FMT" client_id %d is invalid\n", ADPT_ARG(adapter), adapter->client_id);
-+		/*rtw_warn_on(1);*/
-+	}
-+	#endif
-+
-+	RTW_INFO("%s ("ADPT_FMT") id:%d, port:%d clt_num:%d\n",
-+		__func__, ADPT_ARG(adapter), adapter->client_id, adapter->client_port, cltp->num);
-+
-+	_enter_critical_bh(&cltp->lock, &irql);
-+	if (adapter->client_id !=  MAX_CLIENT_PORT_NUM) {
-+		cltp->bmp &= ~ BIT(adapter->client_id);
-+		adapter->client_id = MAX_CLIENT_PORT_NUM;
-+		adapter->client_port = CLT_PORT_INVALID;
-+	}
-+	cltp->num--;
-+	if (cltp->num < 0)
-+		cltp->num = 0;
-+	_exit_critical_bh(&cltp->lock, &irql);
-+}
-+void rtw_hw_client_port_allocate(_adapter *adapter)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+
-+	if (hal_spec->port_num != 5)
-+		return;
-+
-+	_hw_client_port_alloc(adapter);
-+}
-+void rtw_hw_client_port_release(_adapter *adapter)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+
-+	if (hal_spec->port_num != 5)
-+		return;
-+
-+	_hw_client_port_free(adapter);
-+}
-+#endif /*CONFIG_CLIENT_PORT_CFG*/
-+
-+void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode)
-+{
-+	RTW_INFO("%s()-"ADPT_FMT" mode = %d\n", __func__, ADPT_ARG(Adapter), mode);
-+
-+	rtw_hal_rcr_set_chk_bssid(Adapter, MLME_ACTION_NONE);
-+
-+	/* set net_type */
-+	Set_MSR(Adapter, mode);
-+
-+	if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
-+		if (!rtw_mi_get_ap_num(Adapter) && !rtw_mi_get_mesh_num(Adapter))
-+			StopTxBeacon(Adapter);
-+	} else if (mode == _HW_STATE_ADHOC_)
-+		ResumeTxBeacon(Adapter);
-+	else if (mode == _HW_STATE_AP_)
-+		/* enable rx ps-poll */
-+		rtw_write16(Adapter, REG_RXFLTMAP1, rtw_read16(Adapter, REG_RXFLTMAP1) | BIT_CTRLFLT10EN);
-+
-+	/* enable rx data frame */
-+	rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
-+
-+#ifdef CONFIG_CLIENT_PORT_CFG
-+	if (mode == _HW_STATE_STATION_)
-+		rtw_hw_client_port_allocate(Adapter);
-+	else
-+		rtw_hw_client_port_release(Adapter);
-+#endif
-+#if defined(CONFIG_RTL8192F)
-+		rtw_write16(Adapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(Adapter, 
-+					REG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_0_FUNCTION);	
-+#endif
-+}
-+#endif
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+u8	rtw_hal_antdiv_before_linked(_adapter *padapter)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+	u8 cur_ant, change_ant;
-+
-+	if (!pHalData->AntDivCfg)
-+		return _FALSE;
-+
-+	if (pHalData->sw_antdiv_bl_state == 0) {
-+		pHalData->sw_antdiv_bl_state = 1;
-+
-+		rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);
-+		change_ant = (cur_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
-+
-+		return rtw_antenna_select_cmd(padapter, change_ant, _FALSE);
-+	}
-+
-+	pHalData->sw_antdiv_bl_state = 0;
-+	return _FALSE;
-+}
-+
-+void	rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+
-+	if (pHalData->AntDivCfg) {
-+		/*RTW_INFO("update_network=> org-RSSI(%d), new-RSSI(%d)\n", dst->Rssi, src->Rssi);*/
-+		/*select optimum_antenna for before linked =>For antenna diversity*/
-+		if (dst->Rssi >=  src->Rssi) {/*keep org parameter*/
-+			src->Rssi = dst->Rssi;
-+			src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;
-+		}
-+	}
-+}
-+#endif
-+
-+#ifdef CONFIG_PROC_DEBUG
-+#ifdef CONFIG_PHY_CAPABILITY_QUERY
-+void rtw_dump_phy_cap_by_phydmapi(void *sel, _adapter *adapter)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
-+	struct phy_spec_t *phy_spec = &pHalData->phy_spec;
-+
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] TRx Capability : 0x%08x\n", phy_spec->trx_cap);
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] Tx Stream Num Index : %d\n", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] Rx Stream Num Index : %d\n", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] Tx Path Num Index : %d\n", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index	[15:8]*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] Rx Path Num Index : %d\n\n", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index	[7:0]*/
-+
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] STBC Capability : 0x%08x\n", phy_spec->stbc_cap);
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT STBC Tx : %s\n", ((phy_spec->stbc_cap >> 24) & 0xFF) ? "Supported" : "N/A"); /*VHT STBC Tx [31:24]*/
-+	/*VHT STBC Rx [23:16]
-+	0 = not support
-+	1 = support for 1 spatial stream
-+	2 = support for 1 or 2 spatial streams
-+	3 = support for 1 or 2 or 3 spatial streams
-+	4 = support for 1 or 2 or 3 or 4 spatial streams*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT STBC Rx :%d\n", ((phy_spec->stbc_cap >> 16) & 0xFF));
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT STBC Tx : %s\n", ((phy_spec->stbc_cap >> 8) & 0xFF) ? "Supported" : "N/A"); /*HT STBC Tx [15:8]*/
-+	/*HT STBC Rx [7:0]
-+	0 = not support
-+	1 = support for 1 spatial stream
-+	2 = support for 1 or 2 spatial streams
-+	3 = support for 1 or 2 or 3 spatial streams*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT STBC Rx : %d\n\n", (phy_spec->stbc_cap & 0xFF));
-+
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] LDPC Capability : 0x%08x\n", phy_spec->ldpc_cap);
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT LDPC Tx : %s\n", ((phy_spec->ldpc_cap >> 24) & 0xFF) ? "Supported" : "N/A"); /*VHT LDPC Tx [31:24]*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT LDPC Rx : %s\n", ((phy_spec->ldpc_cap >> 16) & 0xFF) ? "Supported" : "N/A"); /*VHT LDPC Rx [23:16]*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT LDPC Tx : %s\n", ((phy_spec->ldpc_cap >> 8) & 0xFF) ? "Supported" : "N/A"); /*HT LDPC Tx [15:8]*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT LDPC Rx : %s\n\n", (phy_spec->ldpc_cap & 0xFF) ? "Supported" : "N/A"); /*HT LDPC Rx [7:0]*/
-+	#ifdef CONFIG_BEAMFORMING
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] TxBF Capability : 0x%08x\n", phy_spec->txbf_cap);
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT MU Bfer : %s\n", ((phy_spec->txbf_cap >> 28) & 0xF) ? "Supported" : "N/A"); /*VHT MU Bfer [31:28]*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT MU Bfee : %s\n", ((phy_spec->txbf_cap >> 24) & 0xF) ? "Supported" : "N/A"); /*VHT MU Bfee [27:24]*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT SU Bfer : %s\n", ((phy_spec->txbf_cap >> 20) & 0xF) ? "Supported" : "N/A"); /*VHT SU Bfer [23:20]*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT SU Bfee : %s\n", ((phy_spec->txbf_cap >> 16) & 0xF) ? "Supported" : "N/A"); /*VHT SU Bfee [19:16]*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT Bfer : %s\n", ((phy_spec->txbf_cap >> 4) & 0xF)  ? "Supported" : "N/A"); /*HT Bfer [7:4]*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT Bfee : %s\n\n", (phy_spec->txbf_cap & 0xF) ? "Supported" : "N/A"); /*HT Bfee [3:0]*/
-+
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] TxBF parameter : 0x%08x\n", phy_spec->txbf_param);
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT Sounding Dim : %d\n", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] VHT Steering Ant : %d\n", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT Sounding Dim : %d\n", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/
-+	RTW_PRINT_SEL(sel, "[PHY SPEC] HT Steering Ant : %d\n", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/
-+	#endif
-+}
-+#else
-+void rtw_dump_phy_cap_by_hal(void *sel, _adapter *adapter)
-+{
-+	u8 phy_cap = _FALSE;
-+
-+	/* STBC */
-+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_STBC, (u8 *)&phy_cap);
-+	RTW_PRINT_SEL(sel, "[HAL] STBC Tx : %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
-+
-+	phy_cap = _FALSE;
-+	rtw_hal_get_def_var(adapter, HAL_DEF_RX_STBC, (u8 *)&phy_cap);
-+	RTW_PRINT_SEL(sel, "[HAL] STBC Rx : %s\n\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
-+
-+	/* LDPC support */
-+	phy_cap = _FALSE;
-+	rtw_hal_get_def_var(adapter, HAL_DEF_TX_LDPC, (u8 *)&phy_cap);
-+	RTW_PRINT_SEL(sel, "[HAL] LDPC Tx : %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
-+
-+	phy_cap = _FALSE;
-+	rtw_hal_get_def_var(adapter, HAL_DEF_RX_LDPC, (u8 *)&phy_cap);
-+	RTW_PRINT_SEL(sel, "[HAL] LDPC Rx : %s\n\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
-+	
-+	#ifdef CONFIG_BEAMFORMING
-+	phy_cap = _FALSE;
-+	rtw_hal_get_def_var(adapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&phy_cap);
-+	RTW_PRINT_SEL(sel, "[HAL] Beamformer: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
-+
-+	phy_cap = _FALSE;
-+	rtw_hal_get_def_var(adapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&phy_cap);
-+	RTW_PRINT_SEL(sel, "[HAL] Beamformee: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
-+
-+	phy_cap = _FALSE;
-+	rtw_hal_get_def_var(adapter, HAL_DEF_VHT_MU_BEAMFORMER, &phy_cap);
-+	RTW_PRINT_SEL(sel, "[HAL] VHT MU Beamformer: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
-+
-+	phy_cap = _FALSE;
-+	rtw_hal_get_def_var(adapter, HAL_DEF_VHT_MU_BEAMFORMEE, &phy_cap);
-+	RTW_PRINT_SEL(sel, "[HAL] VHT MU Beamformee: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
-+	#endif
-+}
-+#endif
-+void rtw_dump_phy_cap(void *sel, _adapter *adapter)
-+{
-+	RTW_PRINT_SEL(sel, "\n ======== PHY Capability ========\n");
-+#ifdef CONFIG_PHY_CAPABILITY_QUERY
-+	rtw_dump_phy_cap_by_phydmapi(sel, adapter);
-+#else
-+	rtw_dump_phy_cap_by_hal(sel, adapter);
-+#endif
-+}
-+#endif
-+
-+inline s16 translate_dbm_to_percentage(s16 signal)
-+{
-+	if ((signal <= -100) || (signal >= 20))
-+		return	0;
-+	else if (signal >= 0)
-+		return	100;
-+	else
-+		return 100 + signal;
-+}
-+
-+#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+#ifdef CONFIG_BCN_RECOVERY
-+#define REG_CPU_MGQ_INFO	0x041C
-+#define BIT_BCN_POLL			BIT(28)
-+u8 rtw_ap_bcn_recovery(_adapter *padapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
-+
-+	if (hal_data->issue_bcn_fail >= 2) {
-+		RTW_ERR("%s ISSUE BCN Fail\n", __func__);
-+		rtw_write8(padapter, REG_CPU_MGQ_INFO + 3, 0x10);
-+		hal_data->issue_bcn_fail = 0;
-+	}
-+	return _SUCCESS;
-+}
-+#endif /*CONFIG_BCN_RECOVERY*/
-+
-+#ifdef CONFIG_BCN_XMIT_PROTECT
-+u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms)
-+{
-+	u32 start_time = rtw_get_current_time();
-+	u8 bcn_queue_empty = _FALSE;
-+
-+	do {
-+		if (rtw_read16(padapter, REG_TXPKT_EMPTY) & BIT(11)) {
-+			bcn_queue_empty = _TRUE;
-+			break;
-+		}
-+	} while (rtw_get_passing_time_ms(start_time) <= (txbcn_timer_ms + 10));
-+
-+	if (bcn_queue_empty == _FALSE)
-+		RTW_ERR("%s BCN queue not empty\n", __func__);
-+
-+	return bcn_queue_empty;
-+}
-+#endif /*CONFIG_BCN_XMIT_PROTECT*/
-+#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
-+
-+/**
-+ * rtw_hal_get_trx_path() - Get RF path related information
-+ * @d:		struct dvobj_priv*
-+ * @type:	RF type, nTnR
-+ * @tx:		Tx path
-+ * @rx:		Rx path
-+ *
-+ * Get RF type, TX path and RX path information.
-+ */
-+void rtw_hal_get_trx_path(struct dvobj_priv *d, enum rf_type *type,
-+			 enum bb_path *tx, enum bb_path *rx)
-+{
-+	struct _ADAPTER *a = dvobj_get_primary_adapter(d);
-+	enum rf_type t = GET_HAL_RFPATH(a);
-+
-+	if (type)
-+		*type = t;
-+
-+	if (tx || rx) {
-+		u8 tx_bmp = GET_HAL_TX_PATH_BMP(a);
-+		u8 rx_bmp = GET_HAL_RX_PATH_BMP(a);
-+
-+		if (!tx_bmp && !rx_bmp)
-+			rf_type_to_default_trx_bmp(t, tx, rx);
-+		else {
-+			if (tx)
-+				*tx = GET_HAL_TX_PATH_BMP(a);
-+			if (rx)
-+				*rx = GET_HAL_RX_PATH_BMP(a);
-+		}
-+	}
-+}
-+
-+#ifdef RTW_CHANNEL_SWITCH_OFFLOAD
-+void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw)
-+{
-+	u8 h2c[H2C_SINGLE_CHANNELSWITCH_V2_LEN] = {0};
-+	PHAL_DATA_TYPE hal;
-+	struct submit_ctx *chsw_sctx;
-+
-+	hal = GET_HAL_DATA(adapter);
-+	chsw_sctx = &hal->chsw_sctx;
-+
-+	SET_H2CCMD_SINGLE_CH_SWITCH_V2_CENTRAL_CH_NUM(h2c, central_ch);
-+	SET_H2CCMD_SINGLE_CH_SWITCH_V2_PRIMARY_CH_IDX(h2c, pri_ch_idx);
-+	SET_H2CCMD_SINGLE_CH_SWITCH_V2_BW(h2c, bw);
-+	SET_H2CCMD_SINGLE_CH_SWITCH_V2_IQK_UPDATE_EN(h2c, 1);
-+
-+	rtw_sctx_init(chsw_sctx, 10);
-+	rtw_hal_fill_h2c_cmd(adapter, H2C_SINGLE_CHANNELSWITCH_V2, H2C_SINGLE_CHANNELSWITCH_V2_LEN, h2c);
-+	rtw_sctx_wait(chsw_sctx, __func__);
-+}
-+#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
-+
-+u8 phy_get_capable_tx_num(_adapter *adapter, enum MGN_RATE rate)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u8 tx_num = 0;
-+
-+	if (IS_1T_RATE(rate))
-+		tx_num = hal_data->txpath_cap_num_nss[0];
-+	else if (IS_2T_RATE(rate))
-+		tx_num = hal_data->txpath_cap_num_nss[1];
-+	else if (IS_3T_RATE(rate))
-+		tx_num = hal_data->txpath_cap_num_nss[2];
-+	else if (IS_4T_RATE(rate))
-+		tx_num = hal_data->txpath_cap_num_nss[3];
-+	else
-+		rtw_warn_on(1);
-+
-+	return tx_num == 0 ? RF_1TX : tx_num - 1;
-+}
-+
-+u8 phy_get_current_tx_num(_adapter *adapter, enum MGN_RATE rate)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u8 tx_num = 0;
-+
-+	if (IS_1T_RATE(rate))
-+		tx_num = hal_data->txpath_num_nss[0];
-+	else if (IS_2T_RATE(rate))
-+		tx_num = hal_data->txpath_num_nss[1];
-+	else if (IS_3T_RATE(rate))
-+		tx_num = hal_data->txpath_num_nss[2];
-+	else if (IS_4T_RATE(rate))
-+		tx_num = hal_data->txpath_num_nss[3];
-+	else
-+		rtw_warn_on(1);
-+
-+	return tx_num == 0 ? RF_1TX : tx_num - 1;
-+}
-+
-+#ifdef CONFIG_RTL8812A
-+u8 * rtw_hal_set_8812a_vendor_ie(_adapter *padapter , u8 *pframe ,uint *frlen ) {
-+	int vender_len = 7;
-+	unsigned char	vendor_info[vender_len];
-+	unsigned char REALTEK_OUI[] = {0x00, 0xe0, 0x4c};
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	if( !IS_HARDWARE_TYPE_8812(padapter) )
-+		return pframe;
-+
-+	_rtw_memset(vendor_info,0,vender_len);
-+	_rtw_memcpy(vendor_info, REALTEK_OUI, 3);
-+	vendor_info[4] =2;
-+	if(pHalData->version_id.CUTVersion > B_CUT_VERSION )
-+		vendor_info[6] = RT_HT_CAP_USE_JAGUAR_CCUT;
-+	else
-+		vendor_info[6] = RT_HT_CAP_USE_JAGUAR_BCUT;
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_,vender_len,vendor_info , frlen);
-+	
-+	return pframe;
-+}
-+#endif /*CONFIG_RTL8812A*/
-+
-+static inline void rtw_enter_protsel(struct protsel *protsel, u32 sel)
-+{
-+	int refcnt;
-+
-+	_enter_critical_mutex(&protsel->mutex, NULL);
-+
-+	refcnt = ATOMIC_INC_RETURN(&protsel->refcnt);
-+
-+	WARN_ON(refcnt > 1 && protsel->sel != sel);
-+
-+	protsel->sel = sel;
-+
-+	_exit_critical_mutex(&protsel->mutex, NULL);
-+}
-+
-+static inline void rtw_leave_protsel(struct protsel *protsel)
-+{
-+	int refcnt;
-+
-+	_enter_critical_mutex(&protsel->mutex, NULL);
-+
-+	refcnt = ATOMIC_DEC_RETURN(&protsel->refcnt);
-+
-+	_exit_critical_mutex(&protsel->mutex, NULL);
-+
-+	WARN_ON(refcnt < 0);
-+}
-+
-+static inline bool rtw_assert_protsel(struct protsel *protsel)
-+{
-+	int refcnt = ATOMIC_READ(&protsel->refcnt);
-+
-+	if (refcnt > 0)
-+		return true;
-+
-+	return false;
-+}
-+
-+#ifdef CONFIG_PROTSEL_PORT
-+void rtw_enter_protsel_port(_adapter *padapter, u8 port_sel)
-+{
-+	u8 val8;
-+
-+	rtw_enter_protsel(&padapter->dvobj->protsel_port, port_sel);
-+
-+	val8 = rtw_read8(padapter, REG_PORT_CTRL_SEL);
-+	val8 &= ~BIT_MASK_PORT_CTRL_SEL;
-+	val8 |= BIT_PORT_CTRL_SEL(port_sel);
-+	rtw_write8(padapter, REG_PORT_CTRL_SEL, val8);
-+}
-+
-+bool rtw_assert_protsel_port(_adapter *padapter, u32 addr, u8 len)
-+{
-+	if (!padapter->bup)	/* don't assert before IF up */
-+		return true;
-+
-+	return rtw_assert_protsel(&padapter->dvobj->protsel_port);
-+}
-+
-+void rtw_leave_protsel_port(_adapter *padapter)
-+{
-+	rtw_leave_protsel(&padapter->dvobj->protsel_port);
-+}
-+#endif
-+
-+#ifdef CONFIG_PROTSEL_ATIMDTIM
-+void rtw_enter_protsel_atimdtim(_adapter *padapter, u8 port_sel)
-+{
-+	/* 0~15 is for port 0 MBSSID setting
-+	 * 16 is for port 1 setting
-+	 * 17 is for port 2 setting
-+	 * 18 is for port 3 setting
-+	 * 19 is for port 4 setting
-+	 */
-+	u8 val8;
-+
-+	if (port_sel >= 1 && port_sel <= 4)
-+		port_sel += 15;
-+
-+	rtw_enter_protsel(&padapter->dvobj->protsel_atimdtim, port_sel);
-+
-+	val8 = rtw_read8(padapter, REG_ATIM_DTIM_CTRL_SEL);
-+	val8 &= ~BIT_MASK_ATIM_DTIM_SEL;
-+	val8 |= BIT_ATIM_DTIM_SEL(port_sel);
-+	rtw_write8(padapter, REG_ATIM_DTIM_CTRL_SEL, val8);
-+}
-+
-+bool rtw_assert_protsel_atimdtim(_adapter *padapter, u32 addr, u8 len)
-+{
-+	return rtw_assert_protsel(&padapter->dvobj->protsel_atimdtim);
-+}
-+
-+void rtw_leave_protsel_atimdtim(_adapter *padapter)
-+{
-+	rtw_leave_protsel(&padapter->dvobj->protsel_atimdtim);
-+}
-+#endif
-+
-+#ifdef CONFIG_PROTSEL_MACSLEEP
-+void rtw_enter_protsel_macsleep(_adapter *padapter, u8 sel)
-+{
-+	u32 val32;
-+
-+	rtw_enter_protsel(&padapter->dvobj->protsel_macsleep, sel);
-+
-+	val32 = rtw_read32(padapter, REG_MACID_SLEEP_CTRL);
-+	val32 &= ~BIT_MASK_MACID_SLEEP_SEL;
-+	val32 |= BIT_MACID_SLEEP_SEL(sel);
-+	rtw_write32(padapter, REG_MACID_SLEEP_CTRL, val32);
-+}
-+
-+bool rtw_assert_protsel_macsleep(_adapter *padapter, u32 addr, u8 len)
-+{
-+	return rtw_assert_protsel(&padapter->dvobj->protsel_macsleep);
-+}
-+
-+void rtw_leave_protsel_macsleep(_adapter *padapter)
-+{
-+	rtw_leave_protsel(&padapter->dvobj->protsel_macsleep);
-+}
-+#endif
-+
-+void rtw_hal_bcn_early_rpt_c2h_handler(_adapter *padapter)
-+{
-+
-+	if(0)
-+		RTW_INFO("Recv Bcn Early report!!\n");
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_TDLS_CH_SW
-+	if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) == _TRUE)
-+		rtw_tdls_ch_sw_back_to_base_chnl(padapter);
-+#endif
-+#endif
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/hal_com_c2h.h b/drivers/staging/rtl8723cs/hal/hal_com_c2h.h
-new file mode 100644
-index 000000000000..b9aa9ffc7565
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_com_c2h.h
-@@ -0,0 +1,142 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __COMMON_C2H_H__
-+#define __COMMON_C2H_H__
-+
-+#define C2H_TYPE_REG 0
-+#define C2H_TYPE_PKT 1
-+
-+/* 
-+* C2H event format:
-+* Fields    TRIGGER    PAYLOAD    SEQ    PLEN    ID
-+* BITS     [127:120]    [119:16]   [15:8]  [7:4]  [3:0]
-+*/
-+#define C2H_ID(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 4)
-+#define C2H_PLEN(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)), 4, 4)
-+#define C2H_SEQ(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8)
-+#define C2H_PAYLOAD(_c2h)	(((u8*)(_c2h)) + 2)
-+
-+#define SET_C2H_ID(_c2h, _val)		SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 4, _val)
-+#define SET_C2H_PLEN(_c2h, _val)	SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 4, 4, _val)
-+#define SET_C2H_SEQ(_c2h, _val)		SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1 , 0, 8, _val)
-+
-+/* 
-+* C2H event format:
-+* Fields    TRIGGER     PLEN      PAYLOAD    SEQ      ID
-+* BITS    [127:120]  [119:112]  [111:16]   [15:8]   [7:0]
-+*/
-+#define C2H_ID_88XX(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 8)
-+#define C2H_SEQ_88XX(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8)
-+#define C2H_PAYLOAD_88XX(_c2h)	(((u8*)(_c2h)) + 2)
-+#define C2H_PLEN_88XX(_c2h)		LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 14, 0, 8)
-+#define C2H_TRIGGER_88XX(_c2h)	LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 15, 0, 8)
-+
-+#define SET_C2H_ID_88XX(_c2h, _val)		SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 8, _val)
-+#define SET_C2H_SEQ_88XX(_c2h, _val)	SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1, 0, 8, _val)
-+#define SET_C2H_PLEN_88XX(_c2h, _val)	SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 14, 0, 8, _val)
-+
-+typedef enum _C2H_EVT {
-+	C2H_DBG = 0x00,
-+	C2H_LB = 0x01,
-+	C2H_TXBF = 0x02,
-+	C2H_CCX_TX_RPT = 0x03,
-+	C2H_AP_REQ_TXRPT = 0x04,
-+	C2H_FW_SCAN_COMPLETE = 0x7,
-+	C2H_BT_INFO = 0x09,
-+	C2H_BT_MP_INFO = 0x0B,
-+	C2H_RA_RPT = 0x0C,
-+	C2H_SPC_STAT = 0x0D,
-+	C2H_RA_PARA_RPT = 0x0E,
-+	C2H_FW_CHNL_SWITCH_COMPLETE = 0x10,
-+	C2H_IQK_FINISH = 0x11,
-+	C2H_MAILBOX_STATUS = 0x15,
-+	C2H_P2P_RPORT = 0x16,
-+	C2H_MCC = 0x17,
-+	C2H_MAC_HIDDEN_RPT = 0x19,
-+	C2H_MAC_HIDDEN_RPT_2 = 0x1A,
-+	C2H_BCN_EARLY_RPT = 0x1E,
-+	C2H_DEFEATURE_DBG = 0x22,
-+	C2H_CUSTOMER_STR_RPT = 0x24,
-+	C2H_CUSTOMER_STR_RPT_2 = 0x25,
-+	C2H_WLAN_INFO = 0x27,
-+#ifdef RTW_PER_CMD_SUPPORT_FW
-+	C2H_PER_RATE_RPT = 0x2c,
-+#endif
-+	C2H_LPS_STATUS_RPT = 0x32,
-+	C2H_SET_TXPWR_FINISH = 0x70,
-+	C2H_DEFEATURE_RSVD = 0xFD,
-+	C2H_EXTEND = 0xff,
-+} C2H_EVT;
-+
-+typedef enum _EXTEND_C2H_EVT {
-+	EXTEND_C2H_DBG_PRINT = 0
-+} EXTEND_C2H_EVT;
-+
-+#define C2H_REG_LEN 16
-+
-+/* C2H_IQK_FINISH, 0x11 */
-+#define IQK_OFFLOAD_LEN 1
-+void c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len);
-+int	c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms);
-+#define rtl8812_iqk_wait c2h_iqk_offload_wait /* TODO: remove this after phydm call c2h_iqk_offload_wait instead */
-+
-+#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
-+/* C2H_MAC_HIDDEN_RPT, 0x19 */
-+#define MAC_HIDDEN_RPT_LEN 8
-+int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len);
-+
-+/* C2H_MAC_HIDDEN_RPT_2, 0x1A */
-+#define MAC_HIDDEN_RPT_2_LEN 5
-+int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len);
-+int hal_read_mac_hidden_rpt(_adapter *adapter);
-+#else
-+#define hal_read_mac_hidden_rpt(adapter) _SUCCESS
-+#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
-+
-+/* C2H_DEFEATURE_DBG, 0x22 */
-+#define DEFEATURE_DBG_LEN 1
-+int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len);
-+
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+/* C2H_CUSTOMER_STR_RPT, 0x24 */
-+#define CUSTOMER_STR_RPT_LEN 8
-+int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len);
-+
-+/* C2H_CUSTOMER_STR_RPT_2, 0x25 */
-+#define CUSTOMER_STR_RPT_2_LEN 8
-+int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len);
-+#endif /* CONFIG_RTW_CUSTOMER_STR */
-+
-+#ifdef RTW_PER_CMD_SUPPORT_FW
-+/* C2H_PER_RATE_RPT, 0x2c */
-+int c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len);
-+#endif
-+
-+#ifdef CONFIG_LPS_ACK
-+/* C2H_LPS_STATUS_RPT, 0x32 */
-+#define LPS_STATUS_RPT_LEN 2
-+int c2h_lps_status_rpt(PADAPTER adapter, u8 *data, u8 len);
-+#endif /* CONFIG_LPS_ACK */
-+
-+#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
-+/* C2H_SET_TXPWR_FINISH, 0x70 */
-+#define SET_TXPWR_FINISH_LEN 1
-+void c2h_txpwr_idx_offload_done(_adapter *adapter, u8 *data, u8 len);
-+int c2h_txpwr_idx_offload_wait(_adapter *adapter);
-+#endif
-+
-+void rtw_hal_bcn_early_rpt_c2h_handler(_adapter *adapter);
-+
-+#endif /* __COMMON_C2H_H__ */
-diff --git a/drivers/staging/rtl8723cs/hal/hal_com_phycfg.c b/drivers/staging/rtl8723cs/hal/hal_com_phycfg.c
-new file mode 100644
-index 000000000000..0e0da62a887b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_com_phycfg.c
-@@ -0,0 +1,6275 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _HAL_COM_PHYCFG_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#define PG_TXPWR_1PATH_BYTE_NUM_2G 18
-+#define PG_TXPWR_BASE_BYTE_NUM_2G 11
-+
-+#define PG_TXPWR_1PATH_BYTE_NUM_5G 24
-+#define PG_TXPWR_BASE_BYTE_NUM_5G 14
-+
-+#define PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) (((_pg_v) & 0xf0) >> 4)
-+#define PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) ((_pg_v) & 0x0f)
-+#define PG_TXPWR_MSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_MSB_DIFF_S4BIT(_pg_v))
-+#define PG_TXPWR_LSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_LSB_DIFF_S4BIT(_pg_v))
-+#define IS_PG_TXPWR_BASE_INVALID(hal_spec, _base) ((_base) > hal_spec->txgi_max)
-+#define IS_PG_TXPWR_DIFF_INVALID(_diff) ((_diff) > 7 || (_diff) < -8)
-+#define PG_TXPWR_INVALID_BASE 255
-+#define PG_TXPWR_INVALID_DIFF 8
-+
-+#if !IS_PG_TXPWR_DIFF_INVALID(PG_TXPWR_INVALID_DIFF)
-+#error "PG_TXPWR_DIFF definition has problem"
-+#endif
-+
-+#define PG_TXPWR_SRC_PG_DATA	0
-+#define PG_TXPWR_SRC_IC_DEF		1
-+#define PG_TXPWR_SRC_DEF		2
-+#define PG_TXPWR_SRC_NUM		3
-+
-+const char *const _pg_txpwr_src_str[] = {
-+	"PG_DATA",
-+	"IC_DEF",
-+	"DEF",
-+	"UNKNOWN"
-+};
-+
-+#define pg_txpwr_src_str(src) (((src) >= PG_TXPWR_SRC_NUM) ? _pg_txpwr_src_str[PG_TXPWR_SRC_NUM] : _pg_txpwr_src_str[(src)])
-+
-+const char *const _txpwr_pg_mode_str[] = {
-+	"PWR_IDX",
-+	"TSSI_OFFSET",
-+	"UNKNOWN",
-+};
-+
-+static const u8 rate_sec_base[RATE_SECTION_NUM] = {
-+	MGN_11M,
-+	MGN_54M,
-+	MGN_MCS7,
-+	MGN_MCS15,
-+	MGN_MCS23,
-+	MGN_MCS31,
-+	MGN_VHT1SS_MCS7,
-+	MGN_VHT2SS_MCS7,
-+	MGN_VHT3SS_MCS7,
-+	MGN_VHT4SS_MCS7,
-+};
-+
-+#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+typedef struct _TxPowerInfo24G {
-+	u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
-+	u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
-+	/* If only one tx, only BW20 and OFDM are used. */
-+	s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+	s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+	s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+	s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+} TxPowerInfo24G;
-+
-+typedef struct _TxPowerInfo5G {
-+	u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
-+	/* If only one tx, only BW20, OFDM, BW80 and BW160 are used. */
-+	s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+	s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+	s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+	s8 BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+	s8 BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+} TxPowerInfo5G;
-+
-+#ifndef DBG_PG_TXPWR_READ
-+#define DBG_PG_TXPWR_READ 0
-+#endif
-+
-+#if DBG_PG_TXPWR_READ
-+static void dump_pg_txpwr_info_2g(void *sel, TxPowerInfo24G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt)
-+{
-+	int path, group, tx_idx;
-+
-+	RTW_PRINT_SEL(sel, "2.4G\n");
-+	RTW_PRINT_SEL(sel, "CCK-1T base:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (group = 0; group < MAX_CHNL_GROUP_24G; group++)
-+		_RTW_PRINT_SEL(sel, "G%02d ", group);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (group = 0; group < MAX_CHNL_GROUP_24G; group++)
-+			_RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexCCK_Base[path][group]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "CCK diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
-+		_RTW_PRINT_SEL(sel, "%dT ", path + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->CCK_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "BW40-1S base:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++)
-+		_RTW_PRINT_SEL(sel, "G%02d ", group);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++)
-+			_RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "OFDM diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
-+		_RTW_PRINT_SEL(sel, "%dT ", path + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "BW20 diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
-+		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "BW40 diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
-+		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+}
-+
-+static void dump_pg_txpwr_info_5g(void *sel, TxPowerInfo5G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt)
-+{
-+	int path, group, tx_idx;
-+
-+	RTW_PRINT_SEL(sel, "5G\n");
-+	RTW_PRINT_SEL(sel, "BW40-1S base:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
-+		_RTW_PRINT_SEL(sel, "G%02d ", group);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
-+			_RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "OFDM diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
-+		_RTW_PRINT_SEL(sel, "%dT ", path + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "BW20 diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
-+		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "BW40 diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
-+		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "BW80 diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
-+		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW80_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "BW160 diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
-+		_RTW_PRINT_SEL(sel, "%dS ", path + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW160_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+}
-+#endif /* DBG_PG_TXPWR_READ */
-+
-+const struct map_t pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 1, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 168,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE,
-+			0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
-+			0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A,
-+			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
-+			0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24,
-+			0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
-+			0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
-+			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE,
-+			0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE)
-+	);
-+
-+#ifdef CONFIG_RTL8188E
-+static const struct map_t rtl8188e_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 1, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 12,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8188F
-+static const struct map_t rtl8188f_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 1, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 12,
-+			0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8188GTV
-+static const struct map_t rtl8188gtv_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 1, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 12,
-+			0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8723B
-+static const struct map_t rtl8723b_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 2, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 12,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0)
-+		, MAPSEG_ARRAY_ENT(0x3A, 12,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+static const struct map_t rtl8703b_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 1, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 12,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+static const struct map_t rtl8723d_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 2, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 12,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
-+		, MAPSEG_ARRAY_ENT(0x3A, 12,
-+			0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x02)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+static const struct map_t rtl8192e_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 2, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 14,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
-+		, MAPSEG_ARRAY_ENT(0x3A, 14,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8821A
-+static const struct map_t rtl8821a_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 1, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 39,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xFF, 0xFF, 0xFF, 0xFF,
-+			0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
-+			0x04, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+static const struct map_t rtl8821c_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 1, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 54,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xFF, 0xFF, 0xFF, 0xFF,
-+			0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
-+			0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xEC, 0xFF, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8710B
-+static const struct map_t rtl8710b_pg_txpwr_def_info =
-+	MAP_ENT(0xC8, 1, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x20, 12,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x20)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+static const struct map_t rtl8812a_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 1, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 82,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF,
-+			0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
-+			0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0x00, 0xEE, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A,
-+			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF,
-+			0x00, 0xEE)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+static const struct map_t rtl8822b_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 1, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 82,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF,
-+			0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
-+			0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0xEC, 0xEC, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A,
-+			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF,
-+			0xEC, 0xEC)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8822C
-+static const struct map_t rtl8822c_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 1, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 82,
-+			0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0x00, 0xFF, 0xFF,
-+			0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,
-+			0x02, 0x00, 0xFF, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,
-+			0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33,
-+			0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0xFF, 0xFF, 0x00, 0xFF,
-+			0x00, 0x00)
-+	);
-+#endif
-+
-+/* todo : 8723f don't know default power */
-+#ifdef CONFIG_RTL8723F
-+static const struct map_t rtl8723f_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 1, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 82,
-+			0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0x00, 0xFF, 0xFF,
-+			0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,
-+			0x02, 0x00, 0xFF, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33,
-+			0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x33, 0x33, 0x33, 0x33,
-+			0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x02, 0x00, 0xFF, 0xFF, 0x00, 0xFF,
-+			0x00, 0x00)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+static const struct map_t rtl8814a_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 1, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 168,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE,
-+			0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
-+			0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A,
-+			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
-+			0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02,
-+			0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
-+			0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
-+			0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE,
-+			0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8192F/*use 8192F default,no document*/
-+static const struct map_t rtl8192f_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 2, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 14,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
-+		, MAPSEG_ARRAY_ENT(0x3A, 14,
-+			0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
-+	);
-+#endif
-+
-+#ifdef CONFIG_RTL8814B
-+static const struct map_t rtl8814b_pg_txpwr_def_info =
-+	MAP_ENT(0xB8, 1, 0xFF
-+		, MAPSEG_ARRAY_ENT(0x10, 168,
-+			0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x02, 0xFF, 0xFF, 0xFF, 0xFF,
-+			0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
-+			0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xEC, 0xFF, 0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
-+			0x28, 0x28, 0x28, 0x28, 0x28, 0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-+			0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-+			0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-+			0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-+			0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-+			0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-+			0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-+			0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF)
-+	);
-+#endif
-+
-+const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter)
-+{
-+	u8 interface_type = 0;
-+	const struct map_t *map = NULL;
-+
-+	interface_type = rtw_get_intf_type(adapter);
-+
-+	switch (rtw_get_chip_type(adapter)) {
-+#ifdef CONFIG_RTL8723B
-+	case RTL8723B:
-+		map = &rtl8723b_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8703B
-+	case RTL8703B:
-+		map = &rtl8703b_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8723D
-+	case RTL8723D:
-+		map = &rtl8723d_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8188E
-+	case RTL8188E:
-+		map = &rtl8188e_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8188F
-+	case RTL8188F:
-+		map = &rtl8188f_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8188GTV
-+	case RTL8188GTV:
-+		map = &rtl8188gtv_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8812A
-+	case RTL8812:
-+		map = &rtl8812a_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8821A
-+	case RTL8821:
-+		map = &rtl8821a_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8192E
-+	case RTL8192E:
-+		map = &rtl8192e_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8814A
-+	case RTL8814A:
-+		map = &rtl8814a_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8822B
-+	case RTL8822B:
-+		map = &rtl8822b_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8821C
-+	case RTL8821C:
-+		map = &rtl8821c_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8710B
-+	case RTL8710B:
-+		map = &rtl8710b_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8192F
-+	case RTL8192F:
-+		map = &rtl8192f_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8822C
-+	case RTL8822C:
-+		map = &rtl8822c_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8814B
-+	case RTL8814B:
-+		map = &rtl8814b_pg_txpwr_def_info;
-+		break;
-+#endif
-+#ifdef CONFIG_RTL8723F
-+	case RTL8723F:
-+		map = &rtl8723f_pg_txpwr_def_info;
-+		break;
-+#endif
-+	}
-+
-+	if (map == NULL) {
-+		RTW_ERR("%s: unknown chip_type:%u\n"
-+			, __func__, rtw_get_chip_type(adapter));
-+		rtw_warn_on(1);
-+	}
-+
-+	return map;
-+}
-+
-+static u8 hal_chk_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u8 path, group, tx_idx;
-+
-+	if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G))
-+		return _SUCCESS;
-+
-+	for (path = 0; path < MAX_RF_PATH; path++) {
-+		if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path))
-+			continue;
-+		for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
-+			if (IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexCCK_Base[path][group])
-+				|| IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group]))
-+				return _FAIL;
-+		}
-+		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
-+			if (tx_idx + 1 > hal_data->max_tx_cnt)
-+				continue;
-+			if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx])
-+				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
-+				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
-+				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx]))
-+				return _FAIL;
-+		}
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+static u8 hal_chk_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info)
-+{
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u8 path, group, tx_idx;
-+
-+	if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G))
-+		return _SUCCESS;
-+
-+	for (path = 0; path < MAX_RF_PATH; path++) {
-+		if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
-+			continue;
-+		for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
-+			if (IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group]))
-+				return _FAIL;
-+		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
-+			if (tx_idx + 1 > hal_data->max_tx_cnt)
-+				continue;
-+			if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
-+				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
-+				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
-+				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx])
-+				|| IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx]))
-+				return _FAIL;
-+		}
-+	}
-+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-+	return _SUCCESS;
-+}
-+
-+static inline void hal_init_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u8 path, group, tx_idx;
-+
-+	if (pwr_info == NULL)
-+		return;
-+
-+	_rtw_memset(pwr_info, 0, sizeof(TxPowerInfo24G));
-+
-+	/* init with invalid value */
-+	for (path = 0; path < MAX_RF_PATH; path++) {
-+		for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
-+			pwr_info->IndexCCK_Base[path][group] = PG_TXPWR_INVALID_BASE;
-+			pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE;
-+		}
-+		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
-+			pwr_info->CCK_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
-+			pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
-+			pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
-+			pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
-+		}
-+	}
-+
-+	/* init for dummy base and diff */
-+	for (path = 0; path < MAX_RF_PATH; path++) {
-+		if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path))
-+			break;
-+		/* 2.4G BW40 base has 1 less group than CCK base*/
-+		pwr_info->IndexBW40_Base[path][MAX_CHNL_GROUP_24G - 1] = 0;
-+
-+		/* dummy diff */
-+		pwr_info->CCK_Diff[path][0] = 0; /* 2.4G CCK-1TX */
-+		pwr_info->BW40_Diff[path][0] = 0; /* 2.4G BW40-1S */
-+	}
-+}
-+
-+static inline void hal_init_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info)
-+{
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u8 path, group, tx_idx;
-+
-+	if (pwr_info == NULL)
-+		return;
-+
-+	_rtw_memset(pwr_info, 0, sizeof(TxPowerInfo5G));
-+
-+	/* init with invalid value */
-+	for (path = 0; path < MAX_RF_PATH; path++) {
-+		for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
-+			pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE;
-+		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
-+			pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
-+			pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
-+			pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
-+			pwr_info->BW80_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
-+			pwr_info->BW160_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
-+		}
-+	}
-+
-+	for (path = 0; path < MAX_RF_PATH; path++) {
-+		if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
-+			break;
-+		/* dummy diff */
-+		pwr_info->BW40_Diff[path][0] = 0; /* 5G BW40-1S */
-+	}
-+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-+}
-+
-+#if DBG_PG_TXPWR_READ
-+#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) 1
-+#else
-+#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) (_txpwr_src > PG_TXPWR_SRC_PG_DATA)
-+#endif
-+
-+u16 hal_load_pg_txpwr_info_path_2g(
-+	_adapter *adapter,
-+	TxPowerInfo24G	*pwr_info,
-+	u32 path,
-+	u8 txpwr_src,
-+	const struct map_t *txpwr_map,
-+	u16 pg_offset)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u16 offset = pg_offset;
-+	u8 group, tx_idx;
-+	u8 val;
-+	u8 tmp_base;
-+	s8 tmp_diff;
-+
-+	if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G)) {
-+		offset += PG_TXPWR_1PATH_BYTE_NUM_2G;
-+		goto exit;
-+	}
-+
-+	if (DBG_PG_TXPWR_READ)
-+		RTW_INFO("%s [%c] offset:0x%03x\n", __func__, rf_path_char(path), offset);
-+
-+	for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
-+		if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
-+			tmp_base = map_read8(txpwr_map, offset);
-+			if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
-+				&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexCCK_Base[path][group])
-+			) {
-+				pwr_info->IndexCCK_Base[path][group] = tmp_base;
-+				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+					RTW_INFO("[%c] 2G G%02d CCK-1T base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
-+			}
-+		}
-+		offset++;
-+	}
-+
-+	for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
-+		if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
-+			tmp_base = map_read8(txpwr_map, offset);
-+			if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
-+				&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group])
-+			) {
-+				pwr_info->IndexBW40_Base[path][group] =	tmp_base;
-+				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+					RTW_INFO("[%c] 2G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
-+			}
-+		}
-+		offset++;
-+	}
-+
-+	for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
-+		if (tx_idx == 0) {
-+			if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
-+				val = map_read8(txpwr_map, offset);
-+				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
-+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
-+				) {
-+					pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
-+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+						RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+				}
-+				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
-+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
-+				) {
-+					pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
-+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+						RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+				}
-+			}
-+			offset++;
-+		} else {
-+			if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && tx_idx + 1 <= hal_data->max_tx_cnt) {
-+				val = map_read8(txpwr_map, offset);
-+				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
-+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
-+				) {
-+					pwr_info->BW40_Diff[path][tx_idx] = tmp_diff;
-+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+						RTW_INFO("[%c] 2G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+
-+				}
-+				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
-+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
-+				) {
-+					pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
-+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+						RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+				}
-+			}
-+			offset++;
-+
-+			if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && tx_idx + 1 <= hal_data->max_tx_cnt) {
-+				val = map_read8(txpwr_map, offset);
-+				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
-+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
-+				) {
-+					pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
-+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+						RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+				}
-+				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
-+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx])
-+				) {
-+					pwr_info->CCK_Diff[path][tx_idx] =	tmp_diff;
-+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+						RTW_INFO("[%c] 2G CCK-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+				}
-+			}
-+			offset++;
-+		}
-+	}
-+
-+	if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_2G) {
-+		RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_2G);
-+		rtw_warn_on(1);
-+	}
-+
-+exit:
-+	return offset;
-+}
-+
-+u16 hal_load_pg_txpwr_info_path_5g(
-+	_adapter *adapter,
-+	TxPowerInfo5G	*pwr_info,
-+	u32 path,
-+	u8 txpwr_src,
-+	const struct map_t *txpwr_map,
-+	u16 pg_offset)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u16 offset = pg_offset;
-+	u8 group, tx_idx;
-+	u8 val;
-+	u8 tmp_base;
-+	s8 tmp_diff;
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G))
-+#endif
-+	{
-+		offset += PG_TXPWR_1PATH_BYTE_NUM_5G;
-+		goto exit;
-+	}
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	if (DBG_PG_TXPWR_READ)
-+		RTW_INFO("%s[%c] eaddr:0x%03x\n", __func__, rf_path_char(path), offset);
-+
-+	for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
-+		if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
-+			tmp_base = map_read8(txpwr_map, offset);
-+			if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base)
-+				&& IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group])
-+			) {
-+				pwr_info->IndexBW40_Base[path][group] = tmp_base;
-+				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+					RTW_INFO("[%c] 5G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
-+			}
-+		}
-+		offset++;
-+	}
-+
-+	for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
-+		if (tx_idx == 0) {
-+			if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
-+				val = map_read8(txpwr_map, offset);
-+				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
-+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
-+				) {
-+					pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
-+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+						RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+				}
-+				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
-+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
-+				) {
-+					pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
-+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+						RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+				}
-+			}
-+			offset++;
-+		} else {
-+			if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && tx_idx + 1 <= hal_data->max_tx_cnt) {
-+				val = map_read8(txpwr_map, offset);
-+				tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
-+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
-+				) {
-+					pwr_info->BW40_Diff[path][tx_idx] = tmp_diff;
-+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+						RTW_INFO("[%c] 5G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+				}
-+				tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
-+				if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+					&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
-+				) {
-+					pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
-+					if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+						RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+				}
-+			}
-+			offset++;
-+		}
-+	}
-+
-+	/* OFDM diff 2T ~ 3T */
-+	if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && hal_data->max_tx_cnt > 1) {
-+		val = map_read8(txpwr_map, offset);
-+		tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
-+		if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+			&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][1])
-+		) {
-+			pwr_info->OFDM_Diff[path][1] = tmp_diff;
-+			if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+				RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 2, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+		}
-+		if (hal_data->max_tx_cnt > 2) {
-+			tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
-+			if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+				&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][2])
-+			) {
-+				pwr_info->OFDM_Diff[path][2] = tmp_diff;
-+				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+					RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 3, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+			}
-+		}
-+	}
-+	offset++;
-+
-+	/* OFDM diff 4T */
-+	if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && hal_data->max_tx_cnt > 3) {
-+		val = map_read8(txpwr_map, offset);
-+		tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
-+		if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+			&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][3])
-+		) {
-+			pwr_info->OFDM_Diff[path][3] = tmp_diff;
-+			if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+				RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 4, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+		}
-+	}
-+	offset++;
-+
-+	for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
-+		if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && tx_idx + 1 <= hal_data->max_tx_cnt) {
-+			val = map_read8(txpwr_map, offset);
-+			tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
-+			if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+				&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx])
-+			) {
-+				pwr_info->BW80_Diff[path][tx_idx] = tmp_diff;
-+				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+					RTW_INFO("[%c] 5G BW80-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+			}
-+			tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
-+			if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
-+				&& IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx])
-+			) {
-+				pwr_info->BW160_Diff[path][tx_idx] = tmp_diff;
-+				if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
-+					RTW_INFO("[%c] 5G BW160-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
-+			}
-+		}
-+		offset++;
-+	}
-+
-+	if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_5G) {
-+		RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_5G);
-+		rtw_warn_on(1);
-+	}
-+
-+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-+
-+exit:
-+	return offset;
-+}
-+
-+void hal_load_pg_txpwr_info(
-+	_adapter *adapter,
-+	TxPowerInfo24G *pwr_info_2g,
-+	TxPowerInfo5G *pwr_info_5g,
-+	u8 *pg_data,
-+	BOOLEAN AutoLoadFail
-+)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u8 path;
-+	u16 pg_offset;
-+	u8 txpwr_src = PG_TXPWR_SRC_PG_DATA;
-+	struct map_t pg_data_map = MAP_ENT(184, 1, 0xFF, MAPSEG_PTR_ENT(0x00, 184, pg_data));
-+	const struct map_t *txpwr_map = NULL;
-+
-+	/* init with invalid value and some dummy base and diff */
-+	hal_init_pg_txpwr_info_2g(adapter, pwr_info_2g);
-+	hal_init_pg_txpwr_info_5g(adapter, pwr_info_5g);
-+
-+select_src:
-+	pg_offset = hal_spec->pg_txpwr_saddr;
-+
-+	switch (txpwr_src) {
-+	case PG_TXPWR_SRC_PG_DATA:
-+		txpwr_map = &pg_data_map;
-+		break;
-+	case PG_TXPWR_SRC_IC_DEF:
-+		txpwr_map = hal_pg_txpwr_def_info(adapter);
-+		break;
-+	case PG_TXPWR_SRC_DEF:
-+	default:
-+		txpwr_map = &pg_txpwr_def_info;
-+		break;
-+	};
-+
-+	if (txpwr_map == NULL)
-+		goto end_parse;
-+
-+	for (path = 0; path < MAX_RF_PATH ; path++) {
-+		if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
-+			break;
-+		pg_offset = hal_load_pg_txpwr_info_path_2g(adapter, pwr_info_2g, path, txpwr_src, txpwr_map, pg_offset);
-+		pg_offset = hal_load_pg_txpwr_info_path_5g(adapter, pwr_info_5g, path, txpwr_src, txpwr_map, pg_offset);
-+	}
-+
-+	if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) == _SUCCESS
-+		&& hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) == _SUCCESS)
-+		goto exit;
-+
-+end_parse:
-+	txpwr_src++;
-+	if (txpwr_src < PG_TXPWR_SRC_NUM)
-+		goto select_src;
-+
-+	if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) != _SUCCESS
-+		|| hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) != _SUCCESS)
-+		rtw_warn_on(1);
-+
-+exit:
-+	#if DBG_PG_TXPWR_READ
-+	if (pwr_info_2g)
-+		dump_pg_txpwr_info_2g(RTW_DBGDUMP, pwr_info_2g, 4, 4);
-+	if (pwr_info_5g)
-+		dump_pg_txpwr_info_5g(RTW_DBGDUMP, pwr_info_5g, 4, 4);
-+	#endif
-+
-+	return;
-+}
-+#endif /* CONFIG_TXPWR_PG_WITH_PWR_IDX */
-+
-+#ifdef CONFIG_EFUSE_CONFIG_FILE
-+
-+#define EFUSE_POWER_INDEX_INVALID 0xFF
-+
-+static u8 _check_phy_efuse_tx_power_info_valid(u8 *pg_data, int chk_len, u16 pg_offset)
-+{
-+	int ff_cnt = 0;
-+	int i;
-+
-+	for (i = 0; i < chk_len; i++) {
-+		if (*(pg_data + pg_offset + i) == 0xFF)
-+			ff_cnt++;
-+	}
-+
-+	if (ff_cnt == 0)
-+		return _TRUE;
-+	else if (ff_cnt == chk_len)
-+		return _FALSE;
-+	else
-+		return EFUSE_POWER_INDEX_INVALID;
-+}
-+
-+int check_phy_efuse_tx_power_info_valid(_adapter *adapter)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u8 *pg_data = hal_data->efuse_eeprom_data;
-+	u16 pg_offset = hal_spec->pg_txpwr_saddr;
-+	u8 path;
-+	u8 valid_2g_path_bmp = 0;
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	u8 valid_5g_path_bmp = 0;
-+#endif
-+#ifdef CONFIG_MP_INCLUDED
-+	struct mp_priv *pmp_priv = &adapter->mppriv;
-+
-+
-+	if (pmp_priv->efuse_update_file == _TRUE && (rtw_mp_mode_check(adapter))) {
-+		RTW_INFO("%s: To use efuse_update_file !!!\n", __func__);
-+		return _FALSE;
-+	}
-+#endif
-+	/* NOTE: TSSI offset use the same layout as TXPWR base */
-+
-+	for (path = 0; path < MAX_RF_PATH; path++) {
-+		u8 ret = _FALSE;
-+
-+		if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
-+			break;
-+
-+		if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
-+			ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_2G, pg_offset);
-+			if (ret == _TRUE)
-+				valid_2g_path_bmp |= BIT(path);
-+			else if (ret == EFUSE_POWER_INDEX_INVALID)
-+				return _FALSE;
-+		}
-+		pg_offset += PG_TXPWR_1PATH_BYTE_NUM_2G;
-+
-+		#if CONFIG_IEEE80211_BAND_5GHZ
-+		if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
-+			ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_5G, pg_offset);
-+			if (ret == _TRUE)
-+				valid_5g_path_bmp |= BIT(path);
-+			else if (ret == EFUSE_POWER_INDEX_INVALID)
-+				return _FALSE;
-+		}
-+		#endif
-+		pg_offset += PG_TXPWR_1PATH_BYTE_NUM_5G;
-+	}
-+
-+	if ((hal_chk_band_cap(adapter, BAND_CAP_2G) && valid_2g_path_bmp)
-+		#if CONFIG_IEEE80211_BAND_5GHZ
-+		|| (hal_chk_band_cap(adapter, BAND_CAP_5G) && valid_5g_path_bmp)
-+		#endif
-+	)
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+#endif /* CONFIG_EFUSE_CONFIG_FILE */
-+
-+#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+void hal_load_txpwr_info(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u8 max_tx_cnt = hal_data->max_tx_cnt;
-+	u8 *pg_data = hal_data->efuse_eeprom_data;
-+	TxPowerInfo24G *pwr_info_2g = NULL;
-+	TxPowerInfo5G *pwr_info_5g = NULL;
-+	u8 rfpath, ch_idx, group, tx_idx;
-+
-+	if (hal_chk_band_cap(adapter, BAND_CAP_2G))
-+		pwr_info_2g = rtw_vmalloc(sizeof(TxPowerInfo24G));
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	if (hal_chk_band_cap(adapter, BAND_CAP_5G))
-+		pwr_info_5g = rtw_vmalloc(sizeof(TxPowerInfo5G));
-+#endif
-+
-+	/* load from pg data (or default value) */
-+	hal_load_pg_txpwr_info(adapter, pwr_info_2g, pwr_info_5g, pg_data, _FALSE);
-+
-+	/* transform to hal_data */
-+	for (rfpath = 0; rfpath < MAX_RF_PATH; rfpath++) {
-+
-+		if (!pwr_info_2g || !HAL_SPEC_CHK_RF_PATH_2G(hal_spec, rfpath))
-+			goto bypass_2g;
-+
-+		/* 2.4G base */
-+		for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++) {
-+			u8 cck_group;
-+
-+			if (rtw_get_ch_group(ch_idx + 1, &group, &cck_group) != BAND_ON_2_4G)
-+				continue;
-+
-+			hal_data->Index24G_CCK_Base[rfpath][ch_idx] = pwr_info_2g->IndexCCK_Base[rfpath][cck_group];
-+			hal_data->Index24G_BW40_Base[rfpath][ch_idx] = pwr_info_2g->IndexBW40_Base[rfpath][group];
-+		}
-+
-+		/* 2.4G diff */
-+		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
-+			if (tx_idx + 1 > max_tx_cnt)
-+				break;
-+
-+			hal_data->CCK_24G_Diff[rfpath][tx_idx] = pwr_info_2g->CCK_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
-+			hal_data->OFDM_24G_Diff[rfpath][tx_idx] = pwr_info_2g->OFDM_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
-+			hal_data->BW20_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW20_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
-+			hal_data->BW40_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW40_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
-+		}
-+bypass_2g:
-+		;
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+		if (!pwr_info_5g || !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, rfpath))
-+			goto bypass_5g;
-+
-+		/* 5G base */
-+		for (ch_idx = 0; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
-+			if (rtw_get_ch_group(center_ch_5g_all[ch_idx], &group, NULL) != BAND_ON_5G)
-+				continue;
-+			hal_data->Index5G_BW40_Base[rfpath][ch_idx] = pwr_info_5g->IndexBW40_Base[rfpath][group];
-+		}
-+
-+		for (ch_idx = 0 ; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++) {
-+			u8 upper, lower;
-+
-+			if (rtw_get_ch_group(center_ch_5g_80m[ch_idx], &group, NULL) != BAND_ON_5G)
-+				continue;
-+
-+			upper = pwr_info_5g->IndexBW40_Base[rfpath][group];
-+			lower = pwr_info_5g->IndexBW40_Base[rfpath][group + 1];
-+			hal_data->Index5G_BW80_Base[rfpath][ch_idx] = (upper + lower) / 2;
-+		}
-+
-+		/* 5G diff */
-+		for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
-+			if (tx_idx + 1 > max_tx_cnt)
-+				break;
-+
-+			hal_data->OFDM_5G_Diff[rfpath][tx_idx] = pwr_info_5g->OFDM_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
-+			hal_data->BW20_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW20_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
-+			hal_data->BW40_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW40_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
-+			hal_data->BW80_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW80_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor;
-+		}
-+bypass_5g:
-+		;
-+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-+	}
-+
-+	if (pwr_info_2g)
-+		rtw_vmfree(pwr_info_2g, sizeof(TxPowerInfo24G));
-+	if (pwr_info_5g)
-+		rtw_vmfree(pwr_info_5g, sizeof(TxPowerInfo5G));
-+}
-+
-+void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	int path, ch_idx, tx_idx;
-+
-+	RTW_PRINT_SEL(sel, "2.4G\n");
-+	RTW_PRINT_SEL(sel, "CCK-1T base:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
-+		_RTW_PRINT_SEL(sel, "%3d ", center_ch_2g[ch_idx]);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
-+			_RTW_PRINT_SEL(sel, "%3u ", hal_data->Index24G_CCK_Base[path][ch_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "CCK diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+		_RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->CCK_24G_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "BW40-1S base:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
-+		_RTW_PRINT_SEL(sel, "%3d ", center_ch_2g[ch_idx]);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
-+			_RTW_PRINT_SEL(sel, "%3u ", hal_data->Index24G_BW40_Base[path][ch_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "OFDM diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+		_RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->OFDM_24G_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "BW20 diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW20_24G_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "BW40 diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW40_24G_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+}
-+
-+void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt)
-+{
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	int path, ch_idx, tx_idx;
-+	u8 dump_section = 0;
-+	u8 ch_idx_s = 0;
-+
-+	RTW_PRINT_SEL(sel, "5G\n");
-+	RTW_PRINT_SEL(sel, "BW40-1S base:\n");
-+	do {
-+		#define DUMP_5G_BW40_BASE_SECTION_NUM 3
-+		u8 end[DUMP_5G_BW40_BASE_SECTION_NUM] = {64, 144, 177};
-+
-+		RTW_PRINT_SEL(sel, "%4s ", "");
-+		for (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
-+			_RTW_PRINT_SEL(sel, "%3d ", center_ch_5g_all[ch_idx]);
-+			if (end[dump_section] == center_ch_5g_all[ch_idx])
-+				break;
-+		}
-+		_RTW_PRINT_SEL(sel, "\n");
-+		for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+			RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+			for (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
-+				_RTW_PRINT_SEL(sel, "%3u ", hal_data->Index5G_BW40_Base[path][ch_idx]);
-+				if (end[dump_section] == center_ch_5g_all[ch_idx])
-+					break;
-+			}
-+			_RTW_PRINT_SEL(sel, "\n");
-+		}
-+		RTW_PRINT_SEL(sel, "\n");
-+
-+		ch_idx_s = ch_idx + 1;
-+		dump_section++;
-+		if (dump_section >= DUMP_5G_BW40_BASE_SECTION_NUM)
-+			break;
-+	} while (1);
-+
-+	RTW_PRINT_SEL(sel, "BW80-1S base:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++)
-+		_RTW_PRINT_SEL(sel, "%3d ", center_ch_5g_80m[ch_idx]);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++)
-+			_RTW_PRINT_SEL(sel, "%3u ", hal_data->Index5G_BW80_Base[path][ch_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "OFDM diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+		_RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->OFDM_5G_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "BW20 diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW20_5G_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "BW40 diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW40_5G_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "BW80 diff:\n");
-+	RTW_PRINT_SEL(sel, "%4s ", "");
-+	for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+		_RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
-+	_RTW_PRINT_SEL(sel, "\n");
-+	for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
-+		RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
-+		for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
-+			_RTW_PRINT_SEL(sel, "%2d ", hal_data->BW80_5G_Diff[path][tx_idx]);
-+		_RTW_PRINT_SEL(sel, "\n");
-+	}
-+	RTW_PRINT_SEL(sel, "\n");
-+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-+}
-+#endif /* CONFIG_TXPWR_PG_WITH_PWR_IDX */
-+
-+/*
-+* rtw_regsty_get_target_tx_power -
-+*
-+* Return dBm or -1 for undefined
-+*/
-+s8 rtw_regsty_get_target_tx_power(
-+		PADAPTER		Adapter,
-+		u8				Band,
-+		u8				RfPath,
-+		RATE_SECTION	RateSection
-+)
-+{
-+	struct registry_priv *regsty = adapter_to_regsty(Adapter);
-+	s8 value = 0;
-+
-+	if (RfPath > RF_PATH_D) {
-+		RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
-+		return -1;
-+	}
-+
-+	if (Band != BAND_ON_2_4G
-+		#if CONFIG_IEEE80211_BAND_5GHZ
-+		&& Band != BAND_ON_5G
-+		#endif
-+	) {
-+		RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
-+		return -1;
-+	}
-+
-+	if (RateSection >= RATE_SECTION_NUM
-+		#if CONFIG_IEEE80211_BAND_5GHZ
-+		|| (Band == BAND_ON_5G && RateSection == CCK)
-+		#endif
-+	) {
-+		RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__
-+			, RateSection, Band, RfPath);
-+		return -1;
-+	}
-+
-+	if (Band == BAND_ON_2_4G)
-+		value = regsty->target_tx_pwr_2g[RfPath][RateSection];
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	else /* BAND_ON_5G */
-+		value = regsty->target_tx_pwr_5g[RfPath][RateSection - 1];
-+#endif
-+
-+	return value;
-+}
-+
-+bool rtw_regsty_chk_target_tx_power_valid(_adapter *adapter)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	int path, tx_num, band, rs;
-+	s8 target;
-+
-+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
-+		if (!hal_is_band_support(adapter, band))
-+			continue;
-+
-+		for (path = 0; path < RF_PATH_MAX; path++) {
-+			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
-+				break;
-+
-+			for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
-+				tx_num = rate_section_to_tx_num(rs);
-+				if (tx_num + 1 > GET_HAL_TX_NSS(adapter))
-+					continue;
-+
-+				if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
-+					continue;
-+
-+				if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
-+					continue;
-+
-+				target = rtw_regsty_get_target_tx_power(adapter, band, path, rs);
-+				if (target == -1) {
-+					RTW_PRINT("%s return _FALSE for band:%d, path:%d, rs:%d, t:%d\n", __func__, band, path, rs, target);
-+					return _FALSE;
-+				}
-+			}
-+		}
-+	}
-+
-+	return _TRUE;
-+}
-+
-+/*
-+* phy_get_target_txpwr -
-+*
-+* Return value in unit of TX Gain Index
-+*/
-+u8 phy_get_target_txpwr(
-+		PADAPTER		Adapter,
-+		u8				Band,
-+		u8				RfPath,
-+		RATE_SECTION	RateSection
-+)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
-+	u8 value = 0;
-+
-+	if (RfPath > RF_PATH_D) {
-+		RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
-+		return 0;
-+	}
-+
-+	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
-+		RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
-+		return 0;
-+	}
-+
-+	if (RateSection >= RATE_SECTION_NUM
-+		|| (Band == BAND_ON_5G && RateSection == CCK)
-+	) {
-+		RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__
-+			, RateSection, Band, RfPath);
-+		return 0;
-+	}
-+
-+	if (Band == BAND_ON_2_4G)
-+		value = pHalData->target_txpwr_2g[RfPath][RateSection];
-+	else if (Band == BAND_ON_5G)
-+		value = pHalData->target_txpwr_5g[RfPath][RateSection - 1];
-+
-+	return value;
-+}
-+
-+static void phy_set_target_txpwr(
-+		PADAPTER		Adapter,
-+		u8				Band,
-+		u8				RfPath,
-+		RATE_SECTION	RateSection,
-+		u8				Value
-+)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
-+
-+	if (RfPath > RF_PATH_D) {
-+		RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
-+		return;
-+	}
-+
-+	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
-+		RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
-+		return;
-+	}
-+
-+	if (RateSection >= RATE_SECTION_NUM
-+		|| (Band == BAND_ON_5G && RateSection == CCK)
-+	) {
-+		RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d\n", __func__
-+			, RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath);
-+		return;
-+	}
-+
-+	if (Band == BAND_ON_2_4G)
-+		pHalData->target_txpwr_2g[RfPath][RateSection] = Value;
-+	else /* BAND_ON_5G */
-+		pHalData->target_txpwr_5g[RfPath][RateSection - 1] = Value;
-+}
-+
-+static inline BOOLEAN phy_is_txpwr_by_rate_undefined_of_band_path(_adapter *adapter, u8 band, u8 path)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u8 rate_idx = 0;
-+
-+	for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) {
-+		if (hal_data->TxPwrByRate[band][path][rate_idx] != hal_spec->txgi_max)
-+			goto exit;
-+	}
-+
-+exit:
-+	return rate_idx >= TX_PWR_BY_RATE_NUM_RATE ? _TRUE : _FALSE;
-+}
-+
-+static inline void phy_txpwr_by_rate_duplicate_band_path(_adapter *adapter, u8 band, u8 s_path, u8 t_path)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u8 rate_idx = 0;
-+
-+	for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++)
-+		hal_data->TxPwrByRate[band][t_path][rate_idx] = hal_data->TxPwrByRate[band][s_path][rate_idx];
-+}
-+
-+static void phy_txpwr_by_rate_chk_for_path_dup(_adapter *adapter)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u8 band, path;
-+	s8 src_path;
-+
-+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++)
-+		for (path = RF_PATH_A; path < RF_PATH_MAX; path++)
-+			hal_data->txpwr_by_rate_undefined_band_path[band][path] = 0;
-+
-+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
-+		if (!hal_is_band_support(adapter, band))
-+			continue;
-+
-+		for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
-+			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
-+				continue;
-+
-+			if (phy_is_txpwr_by_rate_undefined_of_band_path(adapter, band, path))
-+				hal_data->txpwr_by_rate_undefined_band_path[band][path] = 1;
-+		}
-+	}
-+
-+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
-+		if (!hal_is_band_support(adapter, band))
-+			continue;
-+
-+		src_path = -1;
-+		for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
-+			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
-+				continue;
-+
-+			/* find src */
-+			if (src_path == -1 && hal_data->txpwr_by_rate_undefined_band_path[band][path] == 0)
-+				src_path = path;
-+		}
-+
-+		if (src_path == -1) {
-+			RTW_ERR("%s all power by rate undefined\n", __func__);
-+			continue;
-+		}
-+
-+		for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
-+			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
-+				continue;
-+
-+			/* duplicate src to undefined one */
-+			if (hal_data->txpwr_by_rate_undefined_band_path[band][path] == 1) {
-+				RTW_INFO("%s duplicate %s [%c] to [%c]\n", __func__
-+					, band_str(band), rf_path_char(src_path), rf_path_char(path));
-+				phy_txpwr_by_rate_duplicate_band_path(adapter, band, src_path, path);
-+			}
-+		}
-+	}
-+}
-+
-+static s8 _phy_get_txpwr_by_rate(_adapter *adapter
-+	, BAND_TYPE band, enum rf_path rfpath, enum MGN_RATE rate);
-+
-+void phy_store_target_tx_power(PADAPTER	pAdapter)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
-+	struct registry_priv *regsty = adapter_to_regsty(pAdapter);
-+
-+	u8 band, path, rs, tx_num, base;
-+
-+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
-+		if (!hal_is_band_support(pAdapter, band))
-+			continue;
-+
-+		for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
-+			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
-+				break;
-+
-+			for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
-+				tx_num = rate_section_to_tx_num(rs);
-+				if (tx_num + 1 > GET_HAL_TX_NSS(pAdapter))
-+					continue;
-+
-+				if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
-+					continue;
-+
-+				if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
-+					continue;
-+
-+				if (regsty->target_tx_pwr_valid == _TRUE)
-+					base = hal_spec->txgi_pdbm * rtw_regsty_get_target_tx_power(pAdapter, band, path, rs);
-+				else
-+					base = _phy_get_txpwr_by_rate(pAdapter, band, path, rate_sec_base[rs]);
-+				phy_set_target_txpwr(pAdapter, band, path, rs, base);
-+			}
-+		}
-+	}
-+}
-+
-+static u8 get_val_from_dhex(u32 dhex, u8 i)
-+{
-+	return (((dhex >> (i * 8 + 4)) & 0xF)) * 10 + ((dhex >> (i * 8)) & 0xF);
-+}
-+
-+static u8 get_val_from_hex(u32 hex, u8 i)
-+{
-+	return (hex >> (i * 8)) & 0xFF;
-+}
-+
-+void
-+PHY_GetRateValuesOfTxPowerByRate(
-+		PADAPTER pAdapter,
-+		u32 RegAddr,
-+		u32 BitMask,
-+		u32 Value,
-+		u8 *Rate,
-+		s8 *PwrByRateVal,
-+		u8 *RateNum
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
-+	u8 i = 0;
-+	u8 (*get_val)(u32, u8);
-+
-+	if (pDM_Odm->phy_reg_pg_version == 1)
-+		get_val = get_val_from_dhex;
-+	else
-+		get_val = get_val_from_hex;
-+
-+	switch (RegAddr) {
-+	case rTxAGC_A_Rate18_06:
-+	case rTxAGC_B_Rate18_06:
-+		Rate[0] = MGN_6M;
-+		Rate[1] = MGN_9M;
-+		Rate[2] = MGN_12M;
-+		Rate[3] = MGN_18M;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case rTxAGC_A_Rate54_24:
-+	case rTxAGC_B_Rate54_24:
-+		Rate[0] = MGN_24M;
-+		Rate[1] = MGN_36M;
-+		Rate[2] = MGN_48M;
-+		Rate[3] = MGN_54M;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case rTxAGC_A_CCK1_Mcs32:
-+		Rate[0] = MGN_1M;
-+		PwrByRateVal[0] = (s8)get_val(Value, 1);
-+		*RateNum = 1;
-+		break;
-+
-+	case rTxAGC_B_CCK11_A_CCK2_11:
-+		if (BitMask == 0xffffff00) {
-+			Rate[0] = MGN_2M;
-+			Rate[1] = MGN_5_5M;
-+			Rate[2] = MGN_11M;
-+			for (i = 1; i < 4; ++i)
-+				PwrByRateVal[i - 1] = (s8)get_val(Value, i);
-+			*RateNum = 3;
-+		} else if (BitMask == 0x000000ff) {
-+			Rate[0] = MGN_11M;
-+			PwrByRateVal[0] = (s8)get_val(Value, 0);
-+			*RateNum = 1;
-+		}
-+		break;
-+
-+	case rTxAGC_A_Mcs03_Mcs00:
-+	case rTxAGC_B_Mcs03_Mcs00:
-+		Rate[0] = MGN_MCS0;
-+		Rate[1] = MGN_MCS1;
-+		Rate[2] = MGN_MCS2;
-+		Rate[3] = MGN_MCS3;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case rTxAGC_A_Mcs07_Mcs04:
-+	case rTxAGC_B_Mcs07_Mcs04:
-+		Rate[0] = MGN_MCS4;
-+		Rate[1] = MGN_MCS5;
-+		Rate[2] = MGN_MCS6;
-+		Rate[3] = MGN_MCS7;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case rTxAGC_A_Mcs11_Mcs08:
-+	case rTxAGC_B_Mcs11_Mcs08:
-+		Rate[0] = MGN_MCS8;
-+		Rate[1] = MGN_MCS9;
-+		Rate[2] = MGN_MCS10;
-+		Rate[3] = MGN_MCS11;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case rTxAGC_A_Mcs15_Mcs12:
-+	case rTxAGC_B_Mcs15_Mcs12:
-+		Rate[0] = MGN_MCS12;
-+		Rate[1] = MGN_MCS13;
-+		Rate[2] = MGN_MCS14;
-+		Rate[3] = MGN_MCS15;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case rTxAGC_B_CCK1_55_Mcs32:
-+		Rate[0] = MGN_1M;
-+		Rate[1] = MGN_2M;
-+		Rate[2] = MGN_5_5M;
-+		for (i = 1; i < 4; ++i)
-+			PwrByRateVal[i - 1] = (s8)get_val(Value, i);
-+		*RateNum = 3;
-+		break;
-+
-+	case 0xC20:
-+	case 0xE20:
-+	case 0x1820:
-+	case 0x1a20:
-+		Rate[0] = MGN_1M;
-+		Rate[1] = MGN_2M;
-+		Rate[2] = MGN_5_5M;
-+		Rate[3] = MGN_11M;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xC24:
-+	case 0xE24:
-+	case 0x1824:
-+	case 0x1a24:
-+		Rate[0] = MGN_6M;
-+		Rate[1] = MGN_9M;
-+		Rate[2] = MGN_12M;
-+		Rate[3] = MGN_18M;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xC28:
-+	case 0xE28:
-+	case 0x1828:
-+	case 0x1a28:
-+		Rate[0] = MGN_24M;
-+		Rate[1] = MGN_36M;
-+		Rate[2] = MGN_48M;
-+		Rate[3] = MGN_54M;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xC2C:
-+	case 0xE2C:
-+	case 0x182C:
-+	case 0x1a2C:
-+		Rate[0] = MGN_MCS0;
-+		Rate[1] = MGN_MCS1;
-+		Rate[2] = MGN_MCS2;
-+		Rate[3] = MGN_MCS3;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xC30:
-+	case 0xE30:
-+	case 0x1830:
-+	case 0x1a30:
-+		Rate[0] = MGN_MCS4;
-+		Rate[1] = MGN_MCS5;
-+		Rate[2] = MGN_MCS6;
-+		Rate[3] = MGN_MCS7;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xC34:
-+	case 0xE34:
-+	case 0x1834:
-+	case 0x1a34:
-+		Rate[0] = MGN_MCS8;
-+		Rate[1] = MGN_MCS9;
-+		Rate[2] = MGN_MCS10;
-+		Rate[3] = MGN_MCS11;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xC38:
-+	case 0xE38:
-+	case 0x1838:
-+	case 0x1a38:
-+		Rate[0] = MGN_MCS12;
-+		Rate[1] = MGN_MCS13;
-+		Rate[2] = MGN_MCS14;
-+		Rate[3] = MGN_MCS15;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xC3C:
-+	case 0xE3C:
-+	case 0x183C:
-+	case 0x1a3C:
-+		Rate[0] = MGN_VHT1SS_MCS0;
-+		Rate[1] = MGN_VHT1SS_MCS1;
-+		Rate[2] = MGN_VHT1SS_MCS2;
-+		Rate[3] = MGN_VHT1SS_MCS3;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xC40:
-+	case 0xE40:
-+	case 0x1840:
-+	case 0x1a40:
-+		Rate[0] = MGN_VHT1SS_MCS4;
-+		Rate[1] = MGN_VHT1SS_MCS5;
-+		Rate[2] = MGN_VHT1SS_MCS6;
-+		Rate[3] = MGN_VHT1SS_MCS7;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xC44:
-+	case 0xE44:
-+	case 0x1844:
-+	case 0x1a44:
-+		Rate[0] = MGN_VHT1SS_MCS8;
-+		Rate[1] = MGN_VHT1SS_MCS9;
-+		Rate[2] = MGN_VHT2SS_MCS0;
-+		Rate[3] = MGN_VHT2SS_MCS1;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xC48:
-+	case 0xE48:
-+	case 0x1848:
-+	case 0x1a48:
-+		Rate[0] = MGN_VHT2SS_MCS2;
-+		Rate[1] = MGN_VHT2SS_MCS3;
-+		Rate[2] = MGN_VHT2SS_MCS4;
-+		Rate[3] = MGN_VHT2SS_MCS5;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xC4C:
-+	case 0xE4C:
-+	case 0x184C:
-+	case 0x1a4C:
-+		Rate[0] = MGN_VHT2SS_MCS6;
-+		Rate[1] = MGN_VHT2SS_MCS7;
-+		Rate[2] = MGN_VHT2SS_MCS8;
-+		Rate[3] = MGN_VHT2SS_MCS9;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xCD8:
-+	case 0xED8:
-+	case 0x18D8:
-+	case 0x1aD8:
-+		Rate[0] = MGN_MCS16;
-+		Rate[1] = MGN_MCS17;
-+		Rate[2] = MGN_MCS18;
-+		Rate[3] = MGN_MCS19;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xCDC:
-+	case 0xEDC:
-+	case 0x18DC:
-+	case 0x1aDC:
-+		Rate[0] = MGN_MCS20;
-+		Rate[1] = MGN_MCS21;
-+		Rate[2] = MGN_MCS22;
-+		Rate[3] = MGN_MCS23;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0x3a24: /* HT MCS24-27 */
-+		Rate[0] = MGN_MCS24;
-+		Rate[1] = MGN_MCS25;
-+		Rate[2] = MGN_MCS26;
-+		Rate[3] = MGN_MCS27;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0x3a28: /* HT MCS28-31 */
-+		Rate[0] = MGN_MCS28;
-+		Rate[1] = MGN_MCS29;
-+		Rate[2] = MGN_MCS30;
-+		Rate[3] = MGN_MCS31;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xCE0:
-+	case 0xEE0:
-+	case 0x18E0:
-+	case 0x1aE0:
-+		Rate[0] = MGN_VHT3SS_MCS0;
-+		Rate[1] = MGN_VHT3SS_MCS1;
-+		Rate[2] = MGN_VHT3SS_MCS2;
-+		Rate[3] = MGN_VHT3SS_MCS3;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xCE4:
-+	case 0xEE4:
-+	case 0x18E4:
-+	case 0x1aE4:
-+		Rate[0] = MGN_VHT3SS_MCS4;
-+		Rate[1] = MGN_VHT3SS_MCS5;
-+		Rate[2] = MGN_VHT3SS_MCS6;
-+		Rate[3] = MGN_VHT3SS_MCS7;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0xCE8:
-+	case 0xEE8:
-+	case 0x18E8:
-+	case 0x1aE8:
-+	case 0x3a48:
-+		Rate[0] = MGN_VHT3SS_MCS8;
-+		Rate[1] = MGN_VHT3SS_MCS9;
-+		Rate[2] = MGN_VHT4SS_MCS0;
-+		Rate[3] = MGN_VHT4SS_MCS1;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0x3a4c:
-+		Rate[0] = MGN_VHT4SS_MCS2;
-+		Rate[1] = MGN_VHT4SS_MCS3;
-+		Rate[2] = MGN_VHT4SS_MCS4;
-+		Rate[3] = MGN_VHT4SS_MCS5;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	case 0x3a50:
-+		Rate[0] = MGN_VHT4SS_MCS6;
-+		Rate[1] = MGN_VHT4SS_MCS7;
-+		Rate[2] = MGN_VHT4SS_MCS8;
-+		Rate[3] = MGN_VHT4SS_MCS9;
-+		for (i = 0; i < 4; ++i)
-+			PwrByRateVal[i] = (s8)get_val(Value, i);
-+		*RateNum = 4;
-+		break;
-+
-+	default:
-+		RTW_PRINT("Invalid RegAddr 0x%x in %s()\n", RegAddr, __func__);
-+		break;
-+	};
-+}
-+
-+void
-+PHY_StoreTxPowerByRateNew(
-+		PADAPTER	pAdapter,
-+		u32			Band,
-+		u32			RfPath,
-+		u32			RegAddr,
-+		u32			BitMask,
-+		u32			Data
-+)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
-+	u8	i = 0, rates[4] = {0}, rateNum = 0;
-+	s8	PwrByRateVal[4] = {0};
-+
-+	PHY_GetRateValuesOfTxPowerByRate(pAdapter, RegAddr, BitMask, Data, rates, PwrByRateVal, &rateNum);
-+
-+	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
-+		RTW_PRINT("Invalid Band %d\n", Band);
-+		return;
-+	}
-+
-+	if (RfPath > RF_PATH_D) {
-+		RTW_PRINT("Invalid RfPath %d\n", RfPath);
-+		return;
-+	}
-+
-+	for (i = 0; i < rateNum; ++i) {
-+		u8 rate_idx = phy_get_rate_idx_of_txpwr_by_rate(rates[i]);
-+
-+		pHalData->TxPwrByRate[Band][RfPath][rate_idx] = PwrByRateVal[i];
-+	}
-+}
-+
-+void
-+PHY_InitTxPowerByRate(
-+		PADAPTER	pAdapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
-+	u8	band = 0, rfPath = 0, rate = 0;
-+
-+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
-+		for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath)
-+				for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)
-+					pHalData->TxPwrByRate[band][rfPath][rate] = hal_spec->txgi_max;
-+}
-+
-+void
-+phy_store_tx_power_by_rate(
-+		PADAPTER	pAdapter,
-+		u32			Band,
-+		u32			RfPath,
-+		u32			TxNum,
-+		u32			RegAddr,
-+		u32			BitMask,
-+		u32			Data
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
-+
-+	if (pDM_Odm->phy_reg_pg_version > 0)
-+		PHY_StoreTxPowerByRateNew(pAdapter, Band, RfPath, RegAddr, BitMask, Data);
-+	else
-+		RTW_INFO("Invalid PHY_REG_PG.txt version %d\n",  pDM_Odm->phy_reg_pg_version);
-+
-+}
-+
-+/*
-+  * This function must be called if the value in the PHY_REG_PG.txt(or header)
-+  * is exact dBm values
-+  */
-+void
-+PHY_TxPowerByRateConfiguration(
-+		PADAPTER			pAdapter
-+)
-+{
-+	phy_txpwr_by_rate_chk_for_path_dup(pAdapter);
-+	phy_store_target_tx_power(pAdapter);
-+}
-+
-+#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
-+extern bool phy_set_txpwr_idx_offload(_adapter *adapter);
-+#endif
-+
-+void
-+phy_set_tx_power_index_by_rate_section(
-+		PADAPTER		pAdapter,
-+		enum rf_path		RFPath,
-+		u8				Channel,
-+		u8				rs
-+)
-+{
-+	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA(pAdapter);
-+	u8 band = hal_data->current_band_type;
-+	u8 bw = hal_data->current_channel_bw;
-+	u32	powerIndex = 0;
-+	int	i = 0;
-+
-+	if (rs >= RATE_SECTION_NUM) {
-+		RTW_INFO("Invalid RateSection %d in %s", rs, __func__);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (rs == CCK && bw != BAND_ON_2_4G)
-+		goto exit;
-+
-+	for (i = 0; i < rates_by_sections[rs].rate_num; ++i) {
-+#if DBG_TX_POWER_IDX
-+		struct txpwr_idx_comp tic;
-+
-+		powerIndex = rtw_hal_get_tx_power_index(pAdapter, RFPath
-+			, rs, rates_by_sections[rs].rates[i], bw, band, Channel, 0, &tic);
-+		dump_tx_power_index_inline(RTW_DBGDUMP, pAdapter, RFPath, bw, Channel
-+			, rates_by_sections[rs].rates[i], powerIndex, &tic);
-+#else
-+		powerIndex = phy_get_tx_power_index_ex(pAdapter, RFPath
-+			, rs, rates_by_sections[rs].rates[i], bw, band, Channel, 0);
-+#endif
-+		PHY_SetTxPowerIndex(pAdapter, powerIndex, RFPath, rates_by_sections[rs].rates[i]);
-+	}
-+
-+#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
-+	if (!hal_data->set_entire_txpwr
-+		&& phy_set_txpwr_idx_offload(pAdapter))
-+		rtw_hal_set_txpwr_done(pAdapter);
-+#endif
-+
-+exit:
-+	return;
-+}
-+
-+bool phy_get_ch_idx(u8 ch, u8 *ch_idx)
-+{
-+	u8  i = 0;
-+	BOOLEAN bIn24G = _TRUE;
-+
-+	if (ch > 0 && ch <= 14) {
-+		bIn24G = _TRUE;
-+		*ch_idx = ch - 1;
-+	} else {
-+		bIn24G = _FALSE;
-+
-+		for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) {
-+			if (center_ch_5g_all[i] == ch) {
-+				*ch_idx = i;
-+				break;
-+			}
-+		}
-+	}
-+
-+	return bIn24G;
-+}
-+
-+bool phy_chk_ch_setting_consistency(_adapter *adapter, u8 ch)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u8 ch_idx = 0xFF;
-+	u8 ret = _FAIL;
-+
-+	phy_get_ch_idx(ch, &ch_idx);
-+	if (ch_idx == 0xFF) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (ch != hal_data->current_channel) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (ch <= 14) {
-+		if (hal_data->current_band_type != BAND_ON_2_4G) {
-+			rtw_warn_on(1);
-+			goto exit;
-+		}
-+		if (hal_data->current_channel_bw > CHANNEL_WIDTH_40) {
-+			rtw_warn_on(1);
-+			goto exit;
-+		}
-+	}
-+	if (ch > 14) {
-+		if (hal_data->current_band_type != BAND_ON_5G) {
-+			rtw_warn_on(1);
-+			goto exit;
-+		}
-+		if (hal_data->current_channel_bw > CHANNEL_WIDTH_160) {
-+			rtw_warn_on(1);
-+			goto exit;
-+		}
-+	}
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	if (ret != _SUCCESS)
-+		RTW_WARN("ch:%u, hal band:%u, ch:%u, bw:%u\n", ch
-+			, hal_data->current_band_type, hal_data->current_channel, hal_data->current_channel_bw);
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+u8 phy_get_pg_txpwr_idx(_adapter *pAdapter
-+	, enum rf_path RFPath, RATE_SECTION rs, u8 ntx_idx
-+	, enum channel_width BandWidth, u8 band, u8 Channel)
-+{
-+	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(pAdapter);
-+	u8					i;
-+	u8					txPower = 0;
-+	u8					chnlIdx = (Channel - 1);
-+
-+	if (HAL_IsLegalChannel(pAdapter, Channel) == _FALSE) {
-+		chnlIdx = 0;
-+		RTW_INFO("Illegal channel!!\n");
-+	}
-+
-+	phy_get_ch_idx(Channel, &chnlIdx);
-+
-+	if (0)
-+		RTW_INFO("[%s] Channel Index: %d\n", band_str(band), chnlIdx);
-+
-+	if (band == BAND_ON_2_4G) {
-+		if (IS_CCK_RATE_SECTION(rs)) {
-+			/* CCK-nTX */
-+			txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx];
-+			txPower += pHalData->CCK_24G_Diff[RFPath][RF_1TX];
-+			if (ntx_idx >= RF_2TX)
-+				txPower += pHalData->CCK_24G_Diff[RFPath][RF_2TX];
-+			if (ntx_idx >= RF_3TX)
-+				txPower += pHalData->CCK_24G_Diff[RFPath][RF_3TX];
-+			if (ntx_idx >= RF_4TX)
-+				txPower += pHalData->CCK_24G_Diff[RFPath][RF_4TX];
-+			goto exit;
-+		}
-+
-+		txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx];
-+
-+		/* OFDM-nTX */
-+		if (IS_OFDM_RATE_SECTION(rs)) {
-+			txPower += pHalData->OFDM_24G_Diff[RFPath][RF_1TX];
-+			if (ntx_idx >= RF_2TX)
-+				txPower += pHalData->OFDM_24G_Diff[RFPath][RF_2TX];
-+			if (ntx_idx >= RF_3TX)
-+				txPower += pHalData->OFDM_24G_Diff[RFPath][RF_3TX];
-+			if (ntx_idx >= RF_4TX)
-+				txPower += pHalData->OFDM_24G_Diff[RFPath][RF_4TX];
-+			goto exit;
-+		}
-+
-+		/* BW20-nS */
-+		if (BandWidth == CHANNEL_WIDTH_20) {
-+			txPower += pHalData->BW20_24G_Diff[RFPath][RF_1TX];
-+			if (rate_section_to_tx_num(rs) >= RF_2TX)
-+				txPower += pHalData->BW20_24G_Diff[RFPath][RF_2TX];
-+			if (rate_section_to_tx_num(rs) >= RF_3TX)
-+				txPower += pHalData->BW20_24G_Diff[RFPath][RF_3TX];
-+			if (rate_section_to_tx_num(rs) >= RF_4TX)
-+				txPower += pHalData->BW20_24G_Diff[RFPath][RF_4TX];
-+			goto exit;
-+		}
-+
-+		/* BW40-nS */
-+		if (BandWidth == CHANNEL_WIDTH_40
-+			/* Willis suggest adopt BW 40M power index while in BW 80 mode */
-+			|| BandWidth == CHANNEL_WIDTH_80
-+		) {
-+			txPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX];
-+			if (rate_section_to_tx_num(rs) >= RF_2TX)
-+				txPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX];
-+			if (rate_section_to_tx_num(rs) >= RF_3TX)
-+				txPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX];
-+			if (rate_section_to_tx_num(rs) >= RF_4TX)
-+				txPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX];
-+			goto exit;
-+		}
-+	}
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	else if (band == BAND_ON_5G) {
-+		if (IS_CCK_RATE_SECTION(rs)) {
-+			RTW_WARN("===>%s: INVALID, CCK on 5G\n", __func__);
-+			goto exit;
-+		}
-+
-+		txPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx];
-+
-+		/* OFDM-nTX */
-+		if (IS_OFDM_RATE_SECTION(rs)) {
-+			txPower += pHalData->OFDM_5G_Diff[RFPath][RF_1TX];
-+			if (ntx_idx >= RF_2TX)
-+				txPower += pHalData->OFDM_5G_Diff[RFPath][RF_2TX];
-+			if (ntx_idx >= RF_3TX)
-+				txPower += pHalData->OFDM_5G_Diff[RFPath][RF_3TX];
-+			if (ntx_idx >= RF_4TX)
-+				txPower += pHalData->OFDM_5G_Diff[RFPath][RF_4TX];
-+			goto exit;
-+		}
-+
-+		/* BW20-nS */
-+		if (BandWidth == CHANNEL_WIDTH_20) {
-+			txPower += pHalData->BW20_5G_Diff[RFPath][RF_1TX];
-+			if (rate_section_to_tx_num(rs) >= RF_2TX)
-+				txPower += pHalData->BW20_5G_Diff[RFPath][RF_2TX];
-+			if (rate_section_to_tx_num(rs) >= RF_3TX)
-+				txPower += pHalData->BW20_5G_Diff[RFPath][RF_3TX];
-+			if (rate_section_to_tx_num(rs) >= RF_4TX)
-+				txPower += pHalData->BW20_5G_Diff[RFPath][RF_4TX];
-+			goto exit;
-+		}
-+
-+		/* BW40-nS */
-+		if (BandWidth == CHANNEL_WIDTH_40) {
-+			txPower += pHalData->BW40_5G_Diff[RFPath][RF_1TX];
-+			if (rate_section_to_tx_num(rs) >= RF_2TX)
-+				txPower += pHalData->BW40_5G_Diff[RFPath][RF_2TX];
-+			if (rate_section_to_tx_num(rs) >= RF_3TX)
-+				txPower += pHalData->BW40_5G_Diff[RFPath][RF_3TX];
-+			if (rate_section_to_tx_num(rs) >= RF_4TX)
-+				txPower += pHalData->BW40_5G_Diff[RFPath][RF_4TX];
-+			goto exit;
-+		}
-+
-+		/* BW80-nS */
-+		if (BandWidth == CHANNEL_WIDTH_80) {
-+			/* get 80MHz cch index */
-+			for (i = 0; i < CENTER_CH_5G_80M_NUM; ++i) {
-+				if (center_ch_5g_80m[i] == Channel) {
-+					chnlIdx = i;
-+					break;
-+				}
-+			}
-+			if (i >= CENTER_CH_5G_80M_NUM) {
-+			#ifdef CONFIG_MP_INCLUDED
-+				if (rtw_mp_mode_check(pAdapter) == _FALSE)
-+			#endif
-+					rtw_warn_on(1);
-+				txPower = 0;
-+				goto exit;
-+			}
-+
-+			txPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx];
-+
-+			txPower += + pHalData->BW80_5G_Diff[RFPath][RF_1TX];
-+			if (rate_section_to_tx_num(rs) >= RF_2TX)
-+				txPower += pHalData->BW80_5G_Diff[RFPath][RF_2TX];
-+			if (rate_section_to_tx_num(rs) >= RF_3TX)
-+				txPower += pHalData->BW80_5G_Diff[RFPath][RF_3TX];
-+			if (rate_section_to_tx_num(rs) >= RF_4TX)
-+				txPower += pHalData->BW80_5G_Diff[RFPath][RF_4TX];
-+			goto exit;
-+		}
-+
-+		/* TODO: BW160-nS */
-+		rtw_warn_on(1);
-+	}
-+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-+
-+exit:
-+	return txPower;
-+}
-+#endif /* CONFIG_TXPWR_PG_WITH_PWR_IDX */
-+
-+s8
-+PHY_GetTxPowerTrackingOffset(
-+	PADAPTER	pAdapter,
-+	enum rf_path	RFPath,
-+	u8			Rate
-+)
-+{
-+	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(pAdapter);
-+	struct dm_struct			*pDM_Odm = &pHalData->odmpriv;
-+	s8	offset = 0;
-+
-+	if (pDM_Odm->rf_calibrate_info.txpowertrack_control  == _FALSE)
-+		return offset;
-+
-+	if ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M)) {
-+		offset = pDM_Odm->rf_calibrate_info.remnant_cck_swing_idx;
-+		/*RTW_INFO("+Remnant_CCKSwingIdx = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_CCKSwingIdx);*/
-+	} else {
-+		offset = pDM_Odm->rf_calibrate_info.remnant_ofdm_swing_idx[RFPath];
-+		/*RTW_INFO("+Remanant_OFDMSwingIdx[RFPath %u][Rate 0x%x] = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]);	*/
-+
-+	}
-+
-+	return offset;
-+}
-+
-+static const u8 _phy_get_rate_idx_of_txpwr_by_rate[MGN_UNKNOWN] = {
-+	[MGN_1M] = 0,
-+	[MGN_2M] = 1,
-+	[MGN_5_5M] = 2,
-+	[MGN_11M] = 3,
-+	[MGN_6M] = 4,
-+	[MGN_9M] = 5,
-+	[MGN_12M] = 6,
-+	[MGN_18M] = 7,
-+	[MGN_24M] = 8,
-+	[MGN_36M] = 9,
-+	[MGN_48M] = 10,
-+	[MGN_54M] = 11,
-+	[MGN_MCS0] = 12,
-+	[MGN_MCS1] = 13,
-+	[MGN_MCS2] = 14,
-+	[MGN_MCS3] = 15,
-+	[MGN_MCS4] = 16,
-+	[MGN_MCS5] = 17,
-+	[MGN_MCS6] = 18,
-+	[MGN_MCS7] = 19,
-+	[MGN_MCS8] = 20,
-+	[MGN_MCS9] = 21,
-+	[MGN_MCS10] = 22,
-+	[MGN_MCS11] = 23,
-+	[MGN_MCS12] = 24,
-+	[MGN_MCS13] = 25,
-+	[MGN_MCS14] = 26,
-+	[MGN_MCS15] = 27,
-+	[MGN_MCS16] = 28,
-+	[MGN_MCS17] = 29,
-+	[MGN_MCS18] = 30,
-+	[MGN_MCS19] = 31,
-+	[MGN_MCS20] = 32,
-+	[MGN_MCS21] = 33,
-+	[MGN_MCS22] = 34,
-+	[MGN_MCS23] = 35,
-+	[MGN_MCS24] = 36,
-+	[MGN_MCS25] = 37,
-+	[MGN_MCS26] = 38,
-+	[MGN_MCS27] = 39,
-+	[MGN_MCS28] = 40,
-+	[MGN_MCS29] = 41,
-+	[MGN_MCS30] = 42,
-+	[MGN_MCS31] = 43,
-+	[MGN_VHT1SS_MCS0] = 44,
-+	[MGN_VHT1SS_MCS1] = 45,
-+	[MGN_VHT1SS_MCS2] = 46,
-+	[MGN_VHT1SS_MCS3] = 47,
-+	[MGN_VHT1SS_MCS4] = 48,
-+	[MGN_VHT1SS_MCS5] = 49,
-+	[MGN_VHT1SS_MCS6] = 50,
-+	[MGN_VHT1SS_MCS7] = 51,
-+	[MGN_VHT1SS_MCS8] = 52,
-+	[MGN_VHT1SS_MCS9] = 53,
-+	[MGN_VHT2SS_MCS0] = 54,
-+	[MGN_VHT2SS_MCS1] = 55,
-+	[MGN_VHT2SS_MCS2] = 56,
-+	[MGN_VHT2SS_MCS3] = 57,
-+	[MGN_VHT2SS_MCS4] = 58,
-+	[MGN_VHT2SS_MCS5] = 59,
-+	[MGN_VHT2SS_MCS6] = 60,
-+	[MGN_VHT2SS_MCS7] = 61,
-+	[MGN_VHT2SS_MCS8] = 62,
-+	[MGN_VHT2SS_MCS9] = 63,
-+	[MGN_VHT3SS_MCS0] = 64,
-+	[MGN_VHT3SS_MCS1] = 65,
-+	[MGN_VHT3SS_MCS2] = 66,
-+	[MGN_VHT3SS_MCS3] = 67,
-+	[MGN_VHT3SS_MCS4] = 68,
-+	[MGN_VHT3SS_MCS5] = 69,
-+	[MGN_VHT3SS_MCS6] = 70,
-+	[MGN_VHT3SS_MCS7] = 71,
-+	[MGN_VHT3SS_MCS8] = 72,
-+	[MGN_VHT3SS_MCS9] = 73,
-+	[MGN_VHT4SS_MCS0] = 74,
-+	[MGN_VHT4SS_MCS1] = 75,
-+	[MGN_VHT4SS_MCS2] = 76,
-+	[MGN_VHT4SS_MCS3] = 77,
-+	[MGN_VHT4SS_MCS4] = 78,
-+	[MGN_VHT4SS_MCS5] = 79,
-+	[MGN_VHT4SS_MCS6] = 80,
-+	[MGN_VHT4SS_MCS7] = 81,
-+	[MGN_VHT4SS_MCS8] = 82,
-+	[MGN_VHT4SS_MCS9] = 83,
-+};
-+
-+/*The same as MRateToHwRate in hal_com.c*/
-+u8 phy_get_rate_idx_of_txpwr_by_rate(enum MGN_RATE rate)
-+{
-+	u8 index = 0;
-+
-+	if (rate < MGN_UNKNOWN)
-+		index = _phy_get_rate_idx_of_txpwr_by_rate[rate];
-+
-+	if (rate != MGN_1M && index == 0)
-+		RTW_WARN("Invalid rate 0x%x in %s\n", rate, __FUNCTION__);
-+
-+	return index;
-+}
-+
-+static s8 _phy_get_txpwr_by_rate(_adapter *adapter
-+	, BAND_TYPE band, enum rf_path rfpath, enum MGN_RATE rate)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
-+	s8 value = 0;
-+	u8 rate_idx = phy_get_rate_idx_of_txpwr_by_rate(rate);
-+
-+	if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
-+		RTW_INFO("Invalid band %d in %s\n", band, __func__);
-+		goto exit;
-+	}
-+	if (rfpath > RF_PATH_D) {
-+		RTW_INFO("Invalid RfPath %d in %s\n", rfpath, __func__);
-+		goto exit;
-+	}
-+	if (rate_idx >= TX_PWR_BY_RATE_NUM_RATE) {
-+		RTW_INFO("Invalid RateIndex %d in %s\n", rate_idx, __func__);
-+		goto exit;
-+	}
-+
-+	value = pHalData->TxPwrByRate[band][rfpath][rate_idx];
-+
-+exit:
-+	return value;
-+}
-+
-+/*
-+* Return value in unit of TX Gain Index
-+*/
-+s8 phy_get_txpwr_by_rate(_adapter *adapter
-+	, BAND_TYPE band, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate)
-+{
-+	if (phy_is_tx_power_by_rate_needed(adapter))
-+		return _phy_get_txpwr_by_rate(adapter, band, rfpath, rate);
-+	return phy_get_target_txpwr(adapter, band, rfpath, rs);
-+}
-+
-+/* get txpowr in mBm for single path */
-+s16 phy_get_txpwr_by_rate_single_mbm(_adapter *adapter
-+	, BAND_TYPE band, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate, bool eirp)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	s16 val;
-+
-+	val = phy_get_txpwr_by_rate(adapter, band, rfpath, rs, rate);
-+	if (val == hal_spec->txgi_max)
-+		val = UNSPECIFIED_MBM;
-+	else {
-+		val = (val * MBM_PDBM) / hal_spec->txgi_pdbm;
-+		if (eirp)
-+			val += rfctl->antenna_gain;
-+	}
-+
-+	return val;
-+}
-+
-+/* get txpowr in mBm with effect of N-TX */
-+s16 phy_get_txpwr_by_rate_total_mbm(_adapter *adapter
-+	, BAND_TYPE band, RATE_SECTION rs, enum MGN_RATE rate, bool cap, bool eirp)
-+{
-+	s16 val;
-+	u8 tx_num;
-+
-+	if (cap)
-+		tx_num = phy_get_capable_tx_num(adapter, rate) + 1;
-+	else
-+		tx_num = phy_get_current_tx_num(adapter, rate) + 1;
-+
-+	/* assume all path have same txpower target */
-+	val = phy_get_txpwr_by_rate_single_mbm(adapter, band, RF_PATH_A, rs, rate, eirp);
-+	if (val != UNSPECIFIED_MBM)
-+		val += mb_of_ntx(tx_num);
-+
-+	return val;
-+}
-+
-+static s16 _phy_get_txpwr_by_rate_max_mbm(_adapter *adapter, BAND_TYPE band, s8 rfpath, bool cap, bool eirp)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u8 tx_num;
-+	RATE_SECTION rs;
-+	int i;
-+	s16 max = UNSPECIFIED_MBM, mbm;
-+
-+	for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
-+		tx_num = rate_section_to_tx_num(rs);
-+		if (tx_num + 1 > hal_data->tx_nss)
-+			continue;
-+
-+		if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
-+			continue;
-+
-+		if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
-+			continue;
-+
-+		for (i = 0; i < rates_by_sections[rs].rate_num; i++) {
-+			if (rfpath < 0) /* total */
-+				mbm = phy_get_txpwr_by_rate_total_mbm(adapter, band, rs, rates_by_sections[rs].rates[i], cap, eirp);
-+			else
-+				mbm = phy_get_txpwr_by_rate_single_mbm(adapter, band, rfpath, rs, rates_by_sections[rs].rates[i], eirp);
-+			if (mbm == UNSPECIFIED_MBM)
-+				continue;
-+			if (max == UNSPECIFIED_MBM || mbm > max)
-+				max = mbm;
-+		}
-+	}
-+
-+	return max;
-+}
-+
-+/* get txpowr in mBm for single path */
-+s16 phy_get_txpwr_by_rate_single_max_mbm(_adapter *adapter, BAND_TYPE band, enum rf_path rfpath, bool eirp)
-+{
-+	return _phy_get_txpwr_by_rate_max_mbm(adapter, band, rfpath, 0 /* single don't care */, eirp);
-+}
-+
-+/* get txpowr in mBm with effect of N-TX */
-+s16 phy_get_txpwr_by_rate_total_max_mbm(_adapter *adapter, BAND_TYPE band, bool cap, bool eirp)
-+{
-+	return _phy_get_txpwr_by_rate_max_mbm(adapter, band, -1, cap, eirp);
-+}
-+
-+u8 phy_check_under_survey_ch(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	_adapter *iface;
-+	struct mlme_ext_priv *mlmeext;
-+	u8 ret = _FALSE;
-+	int i;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+		mlmeext = &iface->mlmeextpriv;
-+
-+		/* check scan state */
-+		if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE
-+			&& mlmeext_scan_state(mlmeext) != SCAN_COMPLETE
-+				&& mlmeext_scan_state(mlmeext) != SCAN_BACKING_OP) {
-+			ret = _TRUE;
-+		} else if (mlmeext_scan_state(mlmeext) == SCAN_BACKING_OP
-+			&& !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)) {
-+			ret = _TRUE;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+void
-+phy_set_tx_power_level_by_path(
-+		PADAPTER	Adapter,
-+		u8			channel,
-+		u8			path
-+)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+	BOOLEAN bIsIn24G = (pHalData->current_band_type == BAND_ON_2_4G);
-+	u8 under_survey_ch = phy_check_under_survey_ch(Adapter);
-+
-+
-+	/* if ( pMgntInfo->RegNByteAccess == 0 ) */
-+	{
-+		if (bIsIn24G)
-+			phy_set_tx_power_index_by_rate_section(Adapter, path, channel, CCK);
-+
-+		phy_set_tx_power_index_by_rate_section(Adapter, path, channel, OFDM);
-+
-+		if (!under_survey_ch) {
-+			phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS0_MCS7);
-+
-+			if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
-+				phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_1SSMCS0_1SSMCS9);
-+
-+			if (pHalData->tx_nss >= 2) {
-+				phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS8_MCS15);
-+
-+				if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
-+					phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_2SSMCS0_2SSMCS9);
-+
-+				if (IS_HARDWARE_TYPE_8814A(Adapter)) {
-+					phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS16_MCS23);
-+					phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_3SSMCS0_3SSMCS9);
-+				}
-+			}
-+		}
-+	}
-+}
-+
-+#if CONFIG_TXPWR_LIMIT
-+const char *const _txpwr_lmt_rs_str[] = {
-+	"CCK",
-+	"OFDM",
-+	"HT",
-+	"VHT",
-+	"UNKNOWN",
-+};
-+
-+static s8
-+phy_GetChannelIndexOfTxPowerLimit(
-+		u8			Band,
-+		u8			Channel
-+)
-+{
-+	s8	channelIndex = -1;
-+	u8	i = 0;
-+
-+	if (Band == BAND_ON_2_4G)
-+		channelIndex = Channel - 1;
-+	else if (Band == BAND_ON_5G) {
-+		for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) {
-+			if (center_ch_5g_all[i] == Channel)
-+				channelIndex = i;
-+		}
-+	} else
-+		RTW_PRINT("Invalid Band %d in %s\n", Band, __func__);
-+
-+	if (channelIndex == -1)
-+		RTW_PRINT("Invalid Channel %d of Band %d in %s\n", Channel, Band, __func__);
-+
-+	return channelIndex;
-+}
-+
-+static s8 phy_txpwr_ww_lmt_value(_adapter *adapter)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+
-+	if (hal_spec->txgi_max == 63)
-+		return -63;
-+	else if (hal_spec->txgi_max == 127)
-+		return -128;
-+
-+	rtw_warn_on(1);
-+	return -128;
-+}
-+
-+/*
-+* return txpwr limit in unit of TX Gain Index
-+* hsl_spec->txgi_max is returned when NO limit
-+*/
-+s8 phy_get_txpwr_lmt(
-+		PADAPTER			Adapter,
-+		const char			*regd_name,
-+		BAND_TYPE			Band,
-+		enum channel_width		bw,
-+	u8 tlrs,
-+	u8 ntx_idx,
-+	u8 cch,
-+	u8 lock
-+)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(Adapter);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(Adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
-+	struct txpwr_lmt_ent *ent = NULL;
-+	_irqL irqL;
-+	_list *cur, *head;
-+	s8 ch_idx;
-+	u8 is_ww_regd = 0;
-+	s8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter);
-+	s8 lmt = hal_spec->txgi_max;
-+
-+	if ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory != 1) ||
-+		Adapter->registrypriv.RegEnableTxPowerLimit == 0)
-+		goto exit;
-+
-+	if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
-+		RTW_ERR("%s invalid band:%u\n", __func__, Band);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (Band == BAND_ON_5G  && tlrs == TXPWR_LMT_RS_CCK) {
-+		RTW_ERR("5G has no CCK\n");
-+		goto exit;
-+	}
-+
-+	if (lock)
-+		_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+	if (!regd_name) /* no regd_name specified, use currnet */
-+		regd_name = rfctl->regd_name;
-+
-+	if (rfctl->txpwr_regd_num == 0
-+		|| strcmp(regd_name, regd_str(TXPWR_LMT_NONE)) == 0)
-+		goto release_lock;
-+
-+	if (strcmp(regd_name, regd_str(TXPWR_LMT_WW)) == 0)
-+		is_ww_regd = 1;
-+
-+	if (!is_ww_regd) {
-+		ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name);
-+		if (!ent)
-+			goto release_lock;
-+	}
-+
-+	ch_idx = phy_GetChannelIndexOfTxPowerLimit(Band, cch);
-+	if (ch_idx == -1)
-+		goto release_lock;
-+
-+	if (Band == BAND_ON_2_4G) {
-+		if (!is_ww_regd) {
-+			lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx];
-+			if (lmt != ww_lmt_val)
-+				goto release_lock;
-+		}
-+
-+		/* search for min value for WW regd or WW limit */
-+		lmt = hal_spec->txgi_max;
-+		head = &rfctl->txpwr_lmt_list;
-+		cur = get_next(head);
-+		while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+			ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
-+			cur = get_next(cur);
-+			if (ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] != ww_lmt_val)
-+				lmt = rtw_min(lmt, ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]);
-+		}
-+	}
-+	#if CONFIG_IEEE80211_BAND_5GHZ
-+	else if (Band == BAND_ON_5G) {
-+		if (!is_ww_regd) {
-+			lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx];
-+			if (lmt != ww_lmt_val)
-+				goto release_lock;
-+		}
-+
-+		/* search for min value for WW regd or WW limit */
-+		lmt = hal_spec->txgi_max;
-+		head = &rfctl->txpwr_lmt_list;
-+		cur = get_next(head);
-+		while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+			ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
-+			cur = get_next(cur);
-+			if (ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] != ww_lmt_val)
-+				lmt = rtw_min(lmt, ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]);
-+		}
-+	}
-+	#endif
-+
-+release_lock:
-+	if (lock)
-+		_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+exit:
-+	return lmt;
-+}
-+
-+/*
-+* return txpwr limit diff value to target of its rate section in unit of TX Gain Index
-+* hal_spec->txgi_max is returned when NO limit
-+*/
-+inline s8 phy_get_txpwr_lmt_diff(_adapter *adapter
-+	, const char *regd_name
-+	, BAND_TYPE band, enum channel_width bw
-+	, u8 rfpath, u8 rs, u8 tlrs, u8 ntx_idx, u8 cch, u8 lock
-+)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	s8 lmt = phy_get_txpwr_lmt(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock);
-+
-+	if (lmt != hal_spec->txgi_max) {
-+		/* return diff value */
-+		lmt = lmt - phy_get_target_txpwr(adapter, band, rfpath, rs);
-+	}
-+
-+	return lmt;
-+}
-+
-+/*
-+* May search for secondary channels for max/min limit
-+* @opch: used to specify operating channel position to get
-+* cch of every bandwidths which differ from current hal_data.cch20, 40, 80...
-+*
-+* return txpwr limit in unit of TX Gain Index
-+* hsl_spec->txgi_max is returned when NO limit
-+*/
-+s8 phy_get_txpwr_lmt_sub_chs(_adapter *adapter
-+	, const char *regd_name
-+	, BAND_TYPE band, enum channel_width bw
-+	, u8 rfpath, u8 rate, u8 ntx_idx, u8 cch, u8 opch, bool reg_max)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	BOOLEAN no_sc = _FALSE;
-+	u8 cch_20 = hal_data->cch_20, cch_40 = hal_data->cch_40, cch_80 = hal_data->cch_80;
-+	s8 tlrs = -1;
-+	s8 lmt = hal_spec->txgi_max;
-+	u8 tmp_cch = 0;
-+	u8 tmp_bw;
-+	u8 bw_bmp = 0;
-+	s8 final_lmt = reg_max ? 0 : hal_spec->txgi_max;
-+	u8 final_bw = CHANNEL_WIDTH_MAX, final_cch = cch;
-+	_irqL irqL;
-+
-+	if ((adapter->registrypriv.RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory != 1) ||
-+		adapter->registrypriv.RegEnableTxPowerLimit == 0
-+	) {
-+		final_lmt = hal_spec->txgi_max;
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	/* MP mode channel don't use secondary channel */
-+	if (rtw_mp_mode_check(adapter) == _TRUE)
-+		no_sc = _TRUE;
-+#endif
-+	if (IS_CCK_RATE(rate))
-+		tlrs = TXPWR_LMT_RS_CCK;
-+	else if (IS_OFDM_RATE(rate))
-+		tlrs = TXPWR_LMT_RS_OFDM;
-+	else if (IS_HT_RATE(rate))
-+		tlrs = TXPWR_LMT_RS_HT;
-+	else if (IS_VHT_RATE(rate))
-+		tlrs = TXPWR_LMT_RS_VHT;
-+	else {
-+		RTW_ERR("%s invalid rate 0x%x\n", __func__, rate);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (no_sc == _TRUE) {
-+		/* use the input center channel and bandwidth directly */
-+		tmp_cch = cch;
-+		bw_bmp = ch_width_to_bw_cap(bw);
-+	} else {
-+		/* decide center channel of each bandwidth */
-+		if (opch != 0) {
-+			cch_80 = bw == CHANNEL_WIDTH_80 ? cch : 0;
-+			cch_40 = bw == CHANNEL_WIDTH_40 ? cch : 0;
-+			cch_20 = bw == CHANNEL_WIDTH_20 ? cch : 0;
-+			if (cch_80 != 0)
-+				cch_40 = rtw_get_scch_by_cch_opch(cch_80, CHANNEL_WIDTH_80, opch);
-+			if (cch_40 != 0)
-+				cch_20 = rtw_get_scch_by_cch_opch(cch_40, CHANNEL_WIDTH_40, opch);
-+		}
-+
-+		/*
-+		* reg_max:
-+		* get valid full bandwidth bmp up to @bw
-+		*
-+		* !reg_max:
-+		* find the possible tx bandwidth bmp for this rate
-+		* if no possible tx bandwidth bmp, select valid bandwidth bmp up to @bw
-+		*/
-+		if (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM)
-+			bw_bmp = BW_CAP_20M; /* CCK, OFDM only BW 20M */
-+		else if (tlrs == TXPWR_LMT_RS_HT) {
-+			if (reg_max)
-+				bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_40 ? CHANNEL_WIDTH_40 + 1 : bw + 1) - 1;
-+			else {
-+				bw_bmp = rtw_get_tx_bw_bmp_of_ht_rate(dvobj, rate, bw);
-+				if (bw_bmp == 0)
-+					bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_40 ? CHANNEL_WIDTH_40 : bw);
-+			}
-+		} else if (tlrs == TXPWR_LMT_RS_VHT) {
-+			if (reg_max)
-+				bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_160 ? CHANNEL_WIDTH_160 + 1 : bw + 1) - 1;
-+			else {
-+				bw_bmp = rtw_get_tx_bw_bmp_of_vht_rate(dvobj, rate, bw);
-+				if (bw_bmp == 0)
-+					bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_160 ? CHANNEL_WIDTH_160 : bw);
-+			}
-+		} else
-+			rtw_warn_on(1);
-+	}
-+
-+	if (bw_bmp == 0)
-+		goto exit;
-+
-+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+	/* loop for each possible tx bandwidth to find final limit */
-+	for (tmp_bw = CHANNEL_WIDTH_20; tmp_bw <= bw; tmp_bw++) {
-+		if (!(ch_width_to_bw_cap(tmp_bw) & bw_bmp))
-+			continue;
-+
-+		if (no_sc == _FALSE) {
-+			/* get center channel for each bandwidth */
-+			if (tmp_bw == CHANNEL_WIDTH_20)
-+				tmp_cch = cch_20;
-+			else if (tmp_bw == CHANNEL_WIDTH_40)
-+				tmp_cch = cch_40;
-+			else if (tmp_bw == CHANNEL_WIDTH_80)
-+				tmp_cch = cch_80;
-+			else {
-+				tmp_cch = 0;
-+				rtw_warn_on(1);
-+			}
-+		}
-+
-+		lmt = phy_get_txpwr_lmt(adapter, regd_name, band, tmp_bw, tlrs, ntx_idx, tmp_cch, 0);
-+
-+		if (final_lmt > lmt) {
-+			if (reg_max)
-+				continue;
-+		} else if (final_lmt < lmt) {
-+			if (!reg_max)
-+				continue;
-+		} else { /* equal */
-+			if (final_bw == bw)
-+				continue;
-+		}
-+
-+		final_lmt = lmt;
-+		final_cch = tmp_cch;
-+		final_bw = tmp_bw;
-+	}
-+
-+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+	if (0) {
-+		if (final_bw != bw && (IS_HT_RATE(rate) || IS_VHT_RATE(rate)))
-+			RTW_INFO("%s final_lmt: %s ch%u -> %s ch%u\n"
-+				, MGN_RATE_STR(rate)
-+				, ch_width_str(bw), cch
-+				, ch_width_str(final_bw), final_cch);
-+	}
-+
-+exit:
-+	return final_lmt;
-+}
-+
-+static void phy_txpwr_lmt_cck_ofdm_mt_chk(_adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	struct txpwr_lmt_ent *ent;
-+	_list *cur, *head;
-+	u8 channel, tlrs, ntx_idx;
-+
-+	rfctl->txpwr_lmt_2g_cck_ofdm_state = 0;
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	rfctl->txpwr_lmt_5g_cck_ofdm_state = 0;
-+#endif
-+
-+	head = &rfctl->txpwr_lmt_list;
-+	cur = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
-+		cur = get_next(cur);
-+
-+		/* check 2G CCK, OFDM state*/
-+		for (tlrs = TXPWR_LMT_RS_CCK; tlrs <= TXPWR_LMT_RS_OFDM; tlrs++) {
-+			for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
-+				for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {
-+					if (ent->lmt_2g[CHANNEL_WIDTH_20][tlrs][channel][ntx_idx] != hal_spec->txgi_max) {
-+						if (tlrs == TXPWR_LMT_RS_CCK)
-+							rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_CCK_1T << ntx_idx;
-+						else
-+							rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx;
-+						break;
-+					}
-+				}
-+			}
-+		}
-+
-+		/* if 2G OFDM multi-TX is not defined, reference HT20 */
-+		for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {
-+			for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
-+				if (rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))
-+					continue;
-+				ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM][channel][ntx_idx] =
-+					ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT][channel][ntx_idx];
-+			}
-+		}
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+		/* check 5G OFDM state*/
-+		for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
-+			for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
-+				if (ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] != hal_spec->txgi_max) {
-+					rfctl->txpwr_lmt_5g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx;
-+					break;
-+				}
-+			}
-+		}
-+
-+		for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
-+			for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
-+				if (rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))
-+					continue;
-+				/* if 5G OFDM multi-TX is not defined, reference HT20 */
-+				ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] =
-+					ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT - 1][channel][ntx_idx];
-+			}
-+		}
-+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-+	}
-+}
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+static void phy_txpwr_lmt_cross_ref_ht_vht(_adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	struct txpwr_lmt_ent *ent;
-+	_list *cur, *head;
-+	u8 bw, channel, tlrs, ref_tlrs, ntx_idx;
-+	int ht_ref_vht_5g_20_40 = 0;
-+	int vht_ref_ht_5g_20_40 = 0;
-+	int ht_has_ref_5g_20_40 = 0;
-+	int vht_has_ref_5g_20_40 = 0;
-+
-+	rfctl->txpwr_lmt_5g_20_40_ref = 0;
-+
-+	head = &rfctl->txpwr_lmt_list;
-+	cur = get_next(head);
-+
-+	while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+		ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
-+		cur = get_next(cur);
-+
-+		for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
-+
-+			for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
-+
-+				for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; ++tlrs) {
-+
-+					/* 5G 20M 40M VHT and HT can cross reference */
-+					if (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40) {
-+						if (tlrs == TXPWR_LMT_RS_HT)
-+							ref_tlrs = TXPWR_LMT_RS_VHT;
-+						else if (tlrs == TXPWR_LMT_RS_VHT)
-+							ref_tlrs = TXPWR_LMT_RS_HT;
-+						else
-+							continue;
-+
-+						for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
-+
-+							if (ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx] == hal_spec->txgi_max)
-+								continue;
-+
-+							if (tlrs == TXPWR_LMT_RS_HT)
-+								ht_has_ref_5g_20_40++;
-+							else if (tlrs == TXPWR_LMT_RS_VHT)
-+								vht_has_ref_5g_20_40++;
-+							else
-+								continue;
-+
-+							if (ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] != hal_spec->txgi_max)
-+								continue;
-+
-+							if (tlrs == TXPWR_LMT_RS_HT && ref_tlrs == TXPWR_LMT_RS_VHT)
-+								ht_ref_vht_5g_20_40++;
-+							else if (tlrs == TXPWR_LMT_RS_VHT && ref_tlrs == TXPWR_LMT_RS_HT)
-+								vht_ref_ht_5g_20_40++;
-+
-+							if (0)
-+								RTW_INFO("reg:%s, bw:%u, ch:%u, %s-%uT ref %s-%uT\n"
-+									, ent->regd_name, bw, channel
-+									, txpwr_lmt_rs_str(tlrs), ntx_idx + 1
-+									, txpwr_lmt_rs_str(ref_tlrs), ntx_idx + 1);
-+
-+							ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] =
-+								ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx];
-+						}
-+					}
-+
-+				}
-+			}
-+		}
-+	}
-+
-+	if (0) {
-+		RTW_INFO("ht_ref_vht_5g_20_40:%d, ht_has_ref_5g_20_40:%d\n", ht_ref_vht_5g_20_40, ht_has_ref_5g_20_40);
-+		RTW_INFO("vht_ref_ht_5g_20_40:%d, vht_has_ref_5g_20_40:%d\n", vht_ref_ht_5g_20_40, vht_has_ref_5g_20_40);
-+	}
-+
-+	/* 5G 20M&40M HT all come from VHT*/
-+	if (ht_ref_vht_5g_20_40 && ht_has_ref_5g_20_40 == ht_ref_vht_5g_20_40)
-+		rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_HT_FROM_VHT;
-+
-+	/* 5G 20M&40M VHT all come from HT*/
-+	if (vht_ref_ht_5g_20_40 && vht_has_ref_5g_20_40 == vht_ref_ht_5g_20_40)
-+		rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_VHT_FROM_HT;
-+}
-+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-+
-+#ifndef DBG_TXPWR_LMT_BAND_CHK
-+#define DBG_TXPWR_LMT_BAND_CHK 0
-+#endif
-+
-+#if DBG_TXPWR_LMT_BAND_CHK
-+/* check if larger bandwidth limit is less than smaller bandwidth for HT & VHT rate */
-+void phy_txpwr_limit_bandwidth_chk(_adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u8 band, bw, path, tlrs, ntx_idx, cch, offset, scch;
-+	u8 ch_num, n, i;
-+
-+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
-+		if (!hal_is_band_support(adapter, band))
-+			continue;
-+
-+		for (bw = CHANNEL_WIDTH_40; bw <= CHANNEL_WIDTH_80; bw++) {
-+			if (bw >= CHANNEL_WIDTH_160)
-+				continue;
-+			if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80)
-+				continue;
-+
-+			if (band == BAND_ON_2_4G)
-+				ch_num = center_chs_2g_num(bw);
-+			else
-+				ch_num = center_chs_5g_num(bw);
-+
-+			if (ch_num == 0) {
-+				rtw_warn_on(1);
-+				break;
-+			}
-+
-+			for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; tlrs++) {
-+
-+				if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT)
-+					continue;
-+				if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK)
-+					continue;
-+				if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM))
-+					continue;
-+				if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT)
-+					continue;
-+				if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
-+					continue;
-+
-+				for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
-+					struct txpwr_lmt_ent *ent;
-+					_list *cur, *head;
-+
-+					if (ntx_idx + 1 > hal_data->max_tx_cnt)
-+						continue;
-+
-+					/* bypass CCK multi-TX is not defined */
-+					if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) {
-+						if (band == BAND_ON_2_4G
-+							&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx)))
-+							continue;
-+					}
-+
-+					/* bypass OFDM multi-TX is not defined */
-+					if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) {
-+						if (band == BAND_ON_2_4G
-+							&& !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
-+							continue;
-+						#if CONFIG_IEEE80211_BAND_5GHZ
-+						if (band == BAND_ON_5G
-+							&& !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
-+							continue;
-+						#endif
-+					}
-+
-+					/* bypass 5G 20M, 40M pure reference */
-+					#if CONFIG_IEEE80211_BAND_5GHZ
-+					if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) {
-+						if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) {
-+							if (tlrs == TXPWR_LMT_RS_HT)
-+								continue;
-+						} else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) {
-+							if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40)
-+								continue;
-+						}
-+					}
-+					#endif
-+
-+					for (n = 0; n < ch_num; n++) {
-+						u8 cch_by_bw[3];
-+						u8 offset_by_bw; /* bitmap, 0 for lower, 1 for upper */
-+						u8 bw_pos;
-+						s8 lmt[3];
-+
-+						if (band == BAND_ON_2_4G)
-+							cch = center_chs_2g(bw, n);
-+						else
-+							cch = center_chs_5g(bw, n);
-+
-+						if (cch == 0) {
-+							rtw_warn_on(1);
-+							break;
-+						}
-+
-+						_rtw_memset(cch_by_bw, 0, 3);
-+						cch_by_bw[bw] = cch;
-+						offset_by_bw = 0x01;
-+
-+						do {
-+							for (bw_pos = bw; bw_pos >= CHANNEL_WIDTH_40; bw_pos--)
-+								cch_by_bw[bw_pos - 1] = rtw_get_scch_by_cch_offset(cch_by_bw[bw_pos], bw_pos, offset_by_bw & BIT(bw_pos) ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER);
-+
-+							head = &rfctl->txpwr_lmt_list;
-+							cur = get_next(head);
-+							while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
-+								ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
-+								cur = get_next(cur);
-+
-+								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
-+									lmt[bw_pos] = phy_get_txpwr_lmt(adapter, ent->regd_name, band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0);
-+
-+								for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--)
-+									if (lmt[bw_pos] > lmt[bw_pos - 1])
-+										break;
-+								if (bw_pos == CHANNEL_WIDTH_20)
-+									continue;
-+
-+								RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:"
-+									, band_str(band)
-+									, ch_width_str(bw)
-+									, txpwr_lmt_rs_str(tlrs)
-+									, ntx_idx + 1
-+									, ent->regd_name
-+								);
-+								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
-+									_RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]);
-+								_RTW_PRINT_SEL(RTW_DBGDUMP, "limit:");
-+								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) {
-+									if (lmt[bw_pos] == hal_spec->txgi_max)
-+										_RTW_PRINT_SEL(RTW_DBGDUMP, "N/A ");
-+									else if (lmt[bw_pos] > -hal_spec->txgi_pdbm && lmt[bw_pos] < 0) /* -1 < value < 0 */
-+										_RTW_PRINT_SEL(RTW_DBGDUMP, "-0.%d", (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
-+									else if (lmt[bw_pos] % hal_spec->txgi_pdbm)
-+										_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d.%d ", lmt[bw_pos] / hal_spec->txgi_pdbm, (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
-+									else
-+										_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d ", lmt[bw_pos] / hal_spec->txgi_pdbm);
-+								}
-+								_RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
-+							}
-+							for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
-+								lmt[bw_pos] = phy_get_txpwr_lmt(adapter, regd_str(TXPWR_LMT_WW), band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0);
-+
-+							for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--)
-+								if (lmt[bw_pos] > lmt[bw_pos - 1])
-+									break;
-+							if (bw_pos != CHANNEL_WIDTH_20) {
-+								RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:"
-+									, band_str(band)
-+									, ch_width_str(bw)
-+									, txpwr_lmt_rs_str(tlrs)
-+									, ntx_idx + 1
-+									, regd_str(TXPWR_LMT_WW)
-+								);
-+								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
-+									_RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]);
-+								_RTW_PRINT_SEL(RTW_DBGDUMP, "limit:");
-+								for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) {
-+									if (lmt[bw_pos] == hal_spec->txgi_max)
-+										_RTW_PRINT_SEL(RTW_DBGDUMP, "N/A ");
-+									else if (lmt[bw_pos] > -hal_spec->txgi_pdbm && lmt[bw_pos] < 0) /* -1 < value < 0 */
-+										_RTW_PRINT_SEL(RTW_DBGDUMP, "-0.%d", (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
-+									else if (lmt[bw_pos] % hal_spec->txgi_pdbm)
-+										_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d.%d ", lmt[bw_pos] / hal_spec->txgi_pdbm, (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
-+									else
-+										_RTW_PRINT_SEL(RTW_DBGDUMP, "%2d ", lmt[bw_pos] / hal_spec->txgi_pdbm);
-+								}
-+								_RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
-+							}
-+
-+							offset_by_bw += 2;
-+							if (offset_by_bw & BIT(bw + 1))
-+								break;
-+						} while (1); /* loop for all ch combinations */
-+					} /* loop for center channels */
-+				} /* loop fo each ntx_idx */
-+			} /* loop for tlrs */
-+		} /* loop for bandwidth */
-+	} /* loop for band */
-+}
-+#endif /* DBG_TXPWR_LMT_BAND_CHK */
-+
-+static void phy_txpwr_lmt_post_hdl(_adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	_irqL irqL;
-+
-+	_enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	if (IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
-+		phy_txpwr_lmt_cross_ref_ht_vht(adapter);
-+#endif
-+	phy_txpwr_lmt_cck_ofdm_mt_chk(adapter);
-+
-+#if DBG_TXPWR_LMT_BAND_CHK
-+	phy_txpwr_limit_bandwidth_chk(adapter);
-+#endif
-+
-+	_exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
-+}
-+
-+BOOLEAN
-+GetS1ByteIntegerFromStringInDecimal(
-+			char	*str,
-+			s8		*val
-+)
-+{
-+	u8 negative = 0;
-+	u16 i = 0;
-+
-+	*val = 0;
-+
-+	while (str[i] != '\0') {
-+		if (i == 0 && (str[i] == '+' || str[i] == '-')) {
-+			if (str[i] == '-')
-+				negative = 1;
-+		} else if (str[i] >= '0' && str[i] <= '9') {
-+			*val *= 10;
-+			*val += (str[i] - '0');
-+		} else
-+			return _FALSE;
-+		++i;
-+	}
-+
-+	if (negative)
-+		*val = -*val;
-+
-+	return _TRUE;
-+}
-+#endif /* CONFIG_TXPWR_LIMIT */
-+
-+/*
-+* phy_set_tx_power_limit - Parsing TX power limit from phydm array, called by odm_ConfigBB_TXPWR_LMT_XXX in phydm
-+*/
-+void
-+phy_set_tx_power_limit(
-+		struct dm_struct		*pDM_Odm,
-+		u8				*Regulation,
-+		u8				*Band,
-+		u8				*Bandwidth,
-+		u8				*RateSection,
-+		u8				*ntx,
-+		u8				*Channel,
-+		u8				*PowerLimit
-+)
-+{
-+#if CONFIG_TXPWR_LIMIT
-+	PADAPTER Adapter = pDM_Odm->adapter;
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
-+	u8 band = 0, bandwidth = 0, tlrs = 0, channel;
-+	u8 ntx_idx;
-+	s8 powerLimit = 0, prevPowerLimit, channelIndex;
-+	s8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter);
-+
-+	if (0)
-+		RTW_INFO("Index of power limit table [regulation %s][band %s][bw %s][rate section %s][ntx %s][chnl %s][val %s]\n"
-+			, Regulation, Band, Bandwidth, RateSection, ntx, Channel, PowerLimit);
-+
-+	if (GetU1ByteIntegerFromStringInDecimal((char *)Channel, &channel) == _FALSE
-+		|| GetS1ByteIntegerFromStringInDecimal((char *)PowerLimit, &powerLimit) == _FALSE
-+	) {
-+		RTW_PRINT("Illegal index of power limit table [ch %s][val %s]\n", Channel, PowerLimit);
-+		return;
-+	}
-+
-+	if (powerLimit != ww_lmt_val) {
-+		if (powerLimit < -hal_spec->txgi_max || powerLimit > hal_spec->txgi_max)
-+			RTW_PRINT("Illegal power limit value [ch %s][val %s]\n", Channel, PowerLimit);
-+
-+		if (powerLimit > hal_spec->txgi_max)
-+			powerLimit = hal_spec->txgi_max;
-+		else if (powerLimit < -hal_spec->txgi_max)
-+			powerLimit =  ww_lmt_val + 1;
-+	}
-+
-+	if (strncmp(RateSection, "CCK", 3) == 0)
-+		tlrs = TXPWR_LMT_RS_CCK;
-+	else if (strncmp(RateSection, "OFDM", 4) == 0)
-+		tlrs = TXPWR_LMT_RS_OFDM;
-+	else if (strncmp(RateSection, "HT", 2) == 0)
-+		tlrs = TXPWR_LMT_RS_HT;
-+	else if (strncmp(RateSection, "VHT", 3) == 0)
-+		tlrs = TXPWR_LMT_RS_VHT;
-+	else {
-+		RTW_PRINT("Wrong rate section:%s\n", RateSection);
-+		return;
-+	}
-+
-+	if (strncmp(ntx, "1T", 2) == 0)
-+		ntx_idx = RF_1TX;
-+	else if (strncmp(ntx, "2T", 2) == 0)
-+		ntx_idx = RF_2TX;
-+	else if (strncmp(ntx, "3T", 2) == 0)
-+		ntx_idx = RF_3TX;
-+	else if (strncmp(ntx, "4T", 2) == 0)
-+		ntx_idx = RF_4TX;
-+	else {
-+		RTW_PRINT("Wrong tx num:%s\n", ntx);
-+		return;
-+	}
-+
-+	if (strncmp(Bandwidth, "20M", 3) == 0)
-+		bandwidth = CHANNEL_WIDTH_20;
-+	else if (strncmp(Bandwidth, "40M", 3) == 0)
-+		bandwidth = CHANNEL_WIDTH_40;
-+	else if (strncmp(Bandwidth, "80M", 3) == 0)
-+		bandwidth = CHANNEL_WIDTH_80;
-+	else if (strncmp(Bandwidth, "160M", 4) == 0)
-+		bandwidth = CHANNEL_WIDTH_160;
-+	else {
-+		RTW_PRINT("unknown bandwidth: %s\n", Bandwidth);
-+		return;
-+	}
-+
-+	if (strncmp(Band, "2.4G", 4) == 0) {
-+		band = BAND_ON_2_4G;
-+		channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, channel);
-+
-+		if (channelIndex == -1) {
-+			RTW_PRINT("unsupported channel: %d at 2.4G\n", channel);
-+			return;
-+		}
-+
-+		if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM) {
-+			RTW_PRINT("unsupported bandwidth: %s at 2.4G\n", Bandwidth);
-+			return;
-+		}
-+
-+		rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
-+	}
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	else if (strncmp(Band, "5G", 2) == 0) {
-+		band = BAND_ON_5G;
-+		channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, channel);
-+
-+		if (channelIndex == -1) {
-+			RTW_PRINT("unsupported channel: %d at 5G\n", channel);
-+			return;
-+		}
-+
-+		rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
-+	}
-+#endif
-+	else {
-+		RTW_PRINT("unknown/unsupported band:%s\n", Band);
-+		return;
-+	}
-+#endif
-+}
-+
-+void
-+phy_set_tx_power_limit_ex(
-+		struct dm_struct		*pDM_Odm,
-+		u8				Regulation,
-+		u8				Band,
-+		u8				Bandwidth,
-+		u8				RateSection,
-+		u8				ntx,
-+		u8				channel,
-+		s8				powerLimit
-+)
-+{
-+#if CONFIG_TXPWR_LIMIT
-+	PADAPTER Adapter = pDM_Odm->adapter;
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
-+	u8 regd;
-+	u8 band = 0, bandwidth = 0, tlrs = 0;
-+	u8 ntx_idx;
-+	s8 prevPowerLimit, channelIndex;
-+	s8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter);
-+
-+	if (0)
-+		RTW_INFO("Index of power limit table [regulation %d][band %d][bw %d][rate section %d][ntx %d][chnl %d][val %d]\n"
-+			, Regulation, Band, Bandwidth, RateSection, ntx, channel, powerLimit);
-+
-+	if (powerLimit != ww_lmt_val) {
-+		if (powerLimit < -hal_spec->txgi_max || powerLimit > hal_spec->txgi_max)
-+			RTW_PRINT("Illegal power limit value [ch %d][val %d]\n", channel, powerLimit);
-+
-+		if (powerLimit > hal_spec->txgi_max)
-+			powerLimit = hal_spec->txgi_max;
-+		else if (powerLimit < -hal_spec->txgi_max)
-+			powerLimit =  ww_lmt_val + 1;
-+	}
-+
-+	switch (Regulation) {
-+	case PW_LMT_REGU_FCC:
-+		regd = TXPWR_LMT_FCC;
-+		break;
-+	case PW_LMT_REGU_ETSI:
-+		regd = TXPWR_LMT_ETSI;
-+		break;
-+	case PW_LMT_REGU_MKK:
-+		regd = TXPWR_LMT_MKK;
-+		break;
-+	case PW_LMT_REGU_IC:
-+		regd = TXPWR_LMT_IC;
-+		break;
-+	case PW_LMT_REGU_KCC:
-+		regd = TXPWR_LMT_KCC;
-+		break;
-+	case PW_LMT_REGU_ACMA:
-+		regd = TXPWR_LMT_ACMA;
-+		break;
-+	case PW_LMT_REGU_CHILE:
-+		regd = TXPWR_LMT_CHILE;
-+		break;
-+	case PW_LMT_REGU_UKRAINE:
-+		regd = TXPWR_LMT_UKRAINE;
-+		break;
-+	case PW_LMT_REGU_MEXICO:
-+		regd = TXPWR_LMT_MEXICO;
-+		break;
-+	case PW_LMT_REGU_CN:
-+		regd = TXPWR_LMT_CN;
-+		break;
-+	case PW_LMT_REGU_WW13:
-+	default:	
-+		RTW_PRINT("Wrong regulation:%d\n", Regulation);
-+		return;		
-+	}
-+
-+	switch (RateSection) {
-+	case PW_LMT_RS_CCK:
-+		tlrs = TXPWR_LMT_RS_CCK;
-+		break;
-+	case PW_LMT_RS_OFDM:
-+		tlrs = TXPWR_LMT_RS_OFDM;
-+		break;
-+	case PW_LMT_RS_HT:
-+		tlrs = TXPWR_LMT_RS_HT;
-+		break;
-+	case PW_LMT_RS_VHT:
-+		tlrs = TXPWR_LMT_RS_VHT;
-+		break;
-+	default:
-+		RTW_PRINT("Wrong rate section:%d\n", RateSection);
-+		return;
-+	}
-+
-+	switch (ntx) {
-+	case PW_LMT_PH_1T:
-+		ntx_idx = RF_1TX;
-+		break;
-+	case PW_LMT_PH_2T:
-+		ntx_idx = RF_2TX;
-+		break;
-+	case PW_LMT_PH_3T:
-+		ntx_idx = RF_3TX;
-+		break;
-+	case PW_LMT_PH_4T:
-+		ntx_idx = RF_4TX;
-+		break;
-+	default:
-+		RTW_PRINT("Wrong tx num:%d\n", ntx);
-+		return;
-+	}
-+
-+	switch (Bandwidth) {
-+	case PW_LMT_BW_20M:
-+		bandwidth = CHANNEL_WIDTH_20;
-+		break;
-+	case PW_LMT_BW_40M:
-+		bandwidth = CHANNEL_WIDTH_40;
-+		break;
-+	case PW_LMT_BW_80M:
-+		bandwidth = CHANNEL_WIDTH_80;
-+		break;
-+	case PW_LMT_BW_160M:
-+		bandwidth = CHANNEL_WIDTH_160;
-+		break;
-+	default:
-+		RTW_PRINT("unknown bandwidth: %d\n", Bandwidth);
-+		return;
-+	}
-+
-+	if (Band == PW_LMT_BAND_2_4G) {
-+		band = BAND_ON_2_4G;
-+		channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, channel);
-+
-+		if (channelIndex == -1) {
-+			RTW_PRINT("unsupported channel: %d at 2.4G\n", channel);
-+			return;
-+		}
-+
-+		if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM) {
-+			RTW_PRINT("unsupported bandwidth: %s at 2.4G\n", ch_width_str(bandwidth));
-+			return;
-+		}
-+
-+		rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), regd_str(regd), band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
-+	}
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	else if (Band == PW_LMT_BAND_5G) {
-+		band = BAND_ON_5G;
-+		channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, channel);
-+
-+		if (channelIndex == -1) {
-+			RTW_PRINT("unsupported channel: %d at 5G\n", channel);
-+			return;
-+		}
-+
-+		rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), regd_str(regd), band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
-+	}
-+#endif
-+	else {
-+		RTW_PRINT("unknown/unsupported band:%d\n", Band);
-+		return;
-+	}
-+#endif
-+}
-+
-+u8 phy_get_tx_power_index_ex(_adapter *adapter
-+	, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate
-+	, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch)
-+{
-+	return rtw_hal_get_tx_power_index(adapter, rfpath, rs, rate, bw, band, cch, opch, NULL);
-+}
-+
-+u8 phy_get_tx_power_index(
-+		PADAPTER			pAdapter,
-+		enum rf_path		RFPath,
-+		u8					Rate,
-+		enum channel_width	BandWidth,
-+		u8					Channel
-+)
-+{
-+	RATE_SECTION rs = mgn_rate_to_rs(Rate);
-+	BAND_TYPE band = Channel <= 14 ? BAND_ON_2_4G : BAND_ON_5G;
-+
-+	return rtw_hal_get_tx_power_index(pAdapter, RFPath, rs, Rate, BandWidth, band, Channel, 0, NULL);
-+}
-+
-+void
-+PHY_SetTxPowerIndex(
-+		PADAPTER		pAdapter,
-+		u32				PowerIndex,
-+		enum rf_path		RFPath,
-+		u8				Rate
-+)
-+{
-+	rtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate);
-+}
-+
-+void dump_tx_power_index_inline(void *sel, _adapter *adapter, u8 rfpath, enum channel_width bw, u8 cch, enum MGN_RATE rate, u8 pwr_idx, struct txpwr_idx_comp *tic)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+
-+	if (tic->utarget == hal_spec->txgi_max) {
-+		RTW_PRINT_SEL(sel, "TXPWR: [%c][%s]cch:%u, %s %uT, idx:%u(0x%02x) = base(%d) + min((byr(%d) + btc(%d) + extra(%d)), rlmt(%d), lmt(%d), ulmt(%d)) + tpc(%d) + tpt(%d) + dpd(%d)\n"
-+			, rf_path_char(rfpath), ch_width_str(bw), cch
-+			, MGN_RATE_STR(rate), tic->ntx_idx + 1
-+			, pwr_idx, pwr_idx, tic->base
-+			, tic->by_rate, tic->btc, tic->extra, tic->rlimit, tic->limit, tic->ulimit
-+			, tic->tpc
-+			, tic->tpt, tic->dpd);
-+	} else {
-+		RTW_PRINT_SEL(sel, "TXPWR: [%c][%s]cch:%u, %s %uT, idx:%u(0x%02x) = base(%d) + min(utgt(%d), rlmt(%d), lmt(%d), ulmt(%d)) + tpc(%d) + tpt(%d) + dpd(%d)\n"
-+			, rf_path_char(rfpath), ch_width_str(bw), cch
-+			, MGN_RATE_STR(rate), tic->ntx_idx + 1
-+			, pwr_idx, pwr_idx, tic->base
-+			, tic->utarget, tic->rlimit, tic->limit, tic->ulimit
-+			, tic->tpc
-+			, tic->tpt, tic->dpd);
-+	}
-+}
-+
-+#ifdef CONFIG_PROC_DEBUG
-+void dump_tx_power_idx_value(void *sel, _adapter *adapter, u8 rfpath, enum MGN_RATE rate, u8 pwr_idx, struct txpwr_idx_comp *tic)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	char tmp_str[8];
-+
-+	txpwr_idx_get_dbm_str(tic->target, hal_spec->txgi_max, hal_spec->txgi_pdbm, 0, tmp_str, 8);
-+
-+	if (tic->utarget == hal_spec->txgi_max) {
-+		RTW_PRINT_SEL(sel, "%4c %9s %uT %s %3u(0x%02x)"
-+			"   %4d      ((%4d   %3d   %5d)  %4d  %4d  %4d)   %3d   %3d   %3d\n"
-+			, rf_path_char(rfpath), MGN_RATE_STR(rate), tic->ntx_idx + 1
-+			, tmp_str, pwr_idx, pwr_idx
-+			, tic->base, tic->by_rate, tic->btc, tic->extra, tic->rlimit, tic->limit, tic->ulimit
-+			, tic->tpc
-+			, tic->tpt, tic->dpd);
-+	} else {
-+		RTW_PRINT_SEL(sel, "%4c %9s %uT %s %3u(0x%02x)"
-+			"   %4d      (%4d  %4d  %4d  %4d)   %3d   %3d   %3d\n"
-+			, rf_path_char(rfpath), MGN_RATE_STR(rate), tic->ntx_idx + 1
-+			, tmp_str, pwr_idx, pwr_idx
-+			, tic->base, tic->utarget, tic->rlimit, tic->limit, tic->ulimit
-+			, tic->tpc
-+			, tic->tpt, tic->dpd);
-+	}
-+}
-+
-+void dump_tx_power_idx_title(void *sel, _adapter *adapter, enum channel_width bw, u8 cch, u8 opch)
-+{
-+	u8 cch_20, cch_40, cch_80;
-+
-+	cch_80 = bw == CHANNEL_WIDTH_80 ? cch : 0;
-+	cch_40 = bw == CHANNEL_WIDTH_40 ? cch : 0;
-+	cch_20 = bw == CHANNEL_WIDTH_20 ? cch : 0;
-+	if (cch_80 != 0)
-+		cch_40 = rtw_get_scch_by_cch_opch(cch_80, CHANNEL_WIDTH_80, opch);
-+	if (cch_40 != 0)
-+		cch_20 = rtw_get_scch_by_cch_opch(cch_40, CHANNEL_WIDTH_40, opch);
-+
-+	RTW_PRINT_SEL(sel, "%s", ch_width_str(bw));
-+	if (bw >= CHANNEL_WIDTH_80)
-+		_RTW_PRINT_SEL(sel, ", cch80:%u", cch_80);
-+	if (bw >= CHANNEL_WIDTH_40)
-+		_RTW_PRINT_SEL(sel, ", cch40:%u", cch_40);
-+	_RTW_PRINT_SEL(sel, ", cch20:%u\n", cch_20);
-+
-+	if (!phy_is_txpwr_user_target_specified(adapter)) {
-+		RTW_PRINT_SEL(sel, "%-4s %-9s %2s %-6s %-3s%6s"
-+			" = %-4s + min((%-4s + %-3s + %-5s), %-4s, %-4s, %-4s) + %-3s + %-3s + %-3s\n"
-+			, "path", "rate", "", "dBm", "idx", ""
-+			, "base", "byr", "btc", "extra", "rlmt", "lmt", "ulmt"
-+			, "tpc"
-+			, "tpt", "dpd");
-+	} else {
-+		RTW_PRINT_SEL(sel, "%-4s %-9s %2s %-6s %-3s%6s"
-+			" = %-4s + min(%-4s, %-4s, %-4s, %-4s) + %-3s + %-3s + %-3s\n"
-+			, "path", "rate", "", "dBm", "idx", ""
-+			, "base", "utgt", "rlmt", "lmt", "ulmt"
-+			, "tpc"
-+			, "tpt", "dpd");
-+	}
-+}
-+
-+void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath
-+	, RATE_SECTION rs, enum channel_width bw, u8 cch, u8 opch)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u8 power_idx;
-+	struct txpwr_idx_comp tic;
-+	u8 tx_num, i;
-+	u8 band = cch > 14 ? BAND_ON_5G : BAND_ON_2_4G;
-+
-+	if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, rfpath))
-+		return;
-+
-+	if (rs >= RATE_SECTION_NUM)
-+		return;
-+
-+	tx_num = rate_section_to_tx_num(rs);
-+	if (tx_num + 1 > hal_data->tx_nss)
-+		return;
-+
-+	if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
-+		return;
-+
-+	if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
-+		return;
-+
-+	for (i = 0; i < rates_by_sections[rs].rate_num; i++) {
-+		power_idx = rtw_hal_get_tx_power_index(adapter, rfpath, rs, rates_by_sections[rs].rates[i], bw, band, cch, opch, &tic);
-+		dump_tx_power_idx_value(sel, adapter, rfpath, rates_by_sections[rs].rates[i], power_idx, &tic);
-+	}
-+}
-+
-+void dump_tx_power_idx(void *sel, _adapter *adapter, enum channel_width bw, u8 cch, u8 opch)
-+{
-+	u8 rfpath, rs;
-+
-+	dump_tx_power_idx_title(sel, adapter, bw, cch, opch);
-+	for (rfpath = RF_PATH_A; rfpath < RF_PATH_MAX; rfpath++)
-+		for (rs = CCK; rs < RATE_SECTION_NUM; rs++)
-+			dump_tx_power_idx_by_path_rs(sel, adapter, rfpath, rs, bw, cch, opch);
-+}
-+
-+void dump_txpwr_total_dbm_value(void *sel, _adapter *adapter, enum MGN_RATE rate, u8 ntx_idx
-+	, s16 target, s16 byr, s16 btc, s16 extra, s16 rlmt, s16 lmt, s16 ulmt, s16 tpc)
-+{
-+	char target_str[8];
-+	char byr_str[8];
-+	char btc_str[8];
-+	char extra_str[8];
-+	char rlmt_str[8];
-+	char lmt_str[8];
-+	char ulmt_str[8];
-+	char tpc_str[8];
-+
-+	txpwr_mbm_get_dbm_str(target, 0, target_str, 8);
-+	txpwr_mbm_get_dbm_str(byr, 0, byr_str, 8);
-+	txpwr_mbm_get_dbm_str(btc, 0, btc_str, 8);
-+	txpwr_mbm_get_dbm_str(extra, 0, extra_str, 8);
-+	txpwr_mbm_get_dbm_str(rlmt, 0, rlmt_str, 8);
-+	txpwr_mbm_get_dbm_str(lmt, 0, lmt_str, 8);
-+	txpwr_mbm_get_dbm_str(ulmt, 0, ulmt_str, 8);
-+	txpwr_mbm_get_dbm_str(tpc, 0, tpc_str, 8);
-+
-+	RTW_PRINT_SEL(sel, "%9s %uT %s =    ((%s   %s   %s), %s, %s, %s)   %s\n"
-+		, MGN_RATE_STR(rate), ntx_idx + 1
-+		, target_str, byr_str, btc_str, extra_str, rlmt_str, lmt_str, ulmt_str, tpc_str);
-+}
-+
-+void dump_txpwr_total_dbm_value_utgt(void *sel, _adapter *adapter, enum MGN_RATE rate, u8 ntx_idx
-+	, s16 target, s16 utgt, s16 rlmt, s16 lmt, s16 ulmt, s16 tpc)
-+{
-+	char target_str[8];
-+	char utgt_str[8];
-+	char rlmt_str[8];
-+	char lmt_str[8];
-+	char ulmt_str[8];
-+	char tpc_str[8];
-+
-+	txpwr_mbm_get_dbm_str(target, 0, target_str, 8);
-+	txpwr_mbm_get_dbm_str(utgt, 0, utgt_str, 8);
-+	txpwr_mbm_get_dbm_str(rlmt, 0, rlmt_str, 8);
-+	txpwr_mbm_get_dbm_str(lmt, 0, lmt_str, 8);
-+	txpwr_mbm_get_dbm_str(ulmt, 0, ulmt_str, 8);
-+	txpwr_mbm_get_dbm_str(tpc, 0, tpc_str, 8);
-+
-+	RTW_PRINT_SEL(sel, "%9s %uT %s =    (%s, %s, %s, %s)   %s\n"
-+		, MGN_RATE_STR(rate), ntx_idx + 1
-+		, target_str, utgt_str, rlmt_str, lmt_str, ulmt_str, tpc_str);
-+}
-+
-+void dump_txpwr_total_dbm_title(void *sel, _adapter *adapter, enum channel_width bw, u8 cch, u8 opch)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	char antenna_gain_str[8];
-+	u8 cch_20, cch_40, cch_80;
-+
-+	txpwr_mbm_get_dbm_str(rfctl->antenna_gain, 0, antenna_gain_str, 8);
-+	RTW_PRINT_SEL(sel, "antenna_gain:%s\n", antenna_gain_str);
-+
-+	cch_80 = bw == CHANNEL_WIDTH_80 ? cch : 0;
-+	cch_40 = bw == CHANNEL_WIDTH_40 ? cch : 0;
-+	cch_20 = bw == CHANNEL_WIDTH_20 ? cch : 0;
-+	if (cch_80 != 0)
-+		cch_40 = rtw_get_scch_by_cch_opch(cch_80, CHANNEL_WIDTH_80, opch);
-+	if (cch_40 != 0)
-+		cch_20 = rtw_get_scch_by_cch_opch(cch_40, CHANNEL_WIDTH_40, opch);
-+
-+	RTW_PRINT_SEL(sel, "%s", ch_width_str(bw));
-+	if (bw >= CHANNEL_WIDTH_80)
-+		_RTW_PRINT_SEL(sel, ", cch80:%u", cch_80);
-+	if (bw >= CHANNEL_WIDTH_40)
-+		_RTW_PRINT_SEL(sel, ", cch40:%u", cch_40);
-+	_RTW_PRINT_SEL(sel, ", cch20:%u\n", cch_20);
-+
-+	if (!phy_is_txpwr_user_target_specified(adapter)) {
-+		RTW_PRINT_SEL(sel, "%-9s %2s %-6s = min((%-6s + %-6s + %-6s), %-6s, %-6s, %-6s) + %-6s\n"
-+			, "rate", "", "target", "byr", "btc", "extra", "rlmt", "lmt", "ulmt", "tpc");
-+	} else {
-+		RTW_PRINT_SEL(sel, "%-9s %2s %-6s = min(%-6s, %-6s, %-6s, %-6s) + %-6s\n"
-+			, "rate", "", "target", "utgt", "rlmt", "lmt", "ulmt", "tpc");
-+	}
-+}
-+
-+void dump_txpwr_total_dbm_by_rs(void *sel, _adapter *adapter, u8 rs, enum channel_width bw, u8 cch, u8 opch)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u8 i;
-+	u8 band = cch > 14 ? BAND_ON_5G : BAND_ON_2_4G;
-+
-+	if (rs >= RATE_SECTION_NUM)
-+		return;
-+
-+	if (rate_section_to_tx_num(rs) + 1 > hal_data->tx_nss)
-+		return;
-+
-+	if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
-+		return;
-+
-+	if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
-+		return;
-+
-+	for (i = 0; i < rates_by_sections[rs].rate_num; i++) {
-+		struct txpwr_idx_comp tic;
-+		s16 target, byr, tpc, btc, extra, utgt, rlmt, lmt, ulmt;
-+		u8 tx_num;
-+
-+		target = phy_get_txpwr_total_mbm(adapter, rs, rates_by_sections[rs].rates[i], bw, cch, opch, 0, 0, &tic);
-+		tx_num = tic.ntx_idx + 1;
-+		if (tic.rlimit == hal_spec->txgi_max)
-+			rlmt = UNSPECIFIED_MBM;
-+		else
-+			rlmt = ((tic.rlimit * MBM_PDBM) / hal_spec->txgi_pdbm) + mb_of_ntx(tx_num);
-+		if (tic.limit == hal_spec->txgi_max)
-+			lmt = UNSPECIFIED_MBM;
-+		else
-+			lmt = ((tic.limit * MBM_PDBM) / hal_spec->txgi_pdbm) + mb_of_ntx(tx_num);
-+		if (tic.ulimit == hal_spec->txgi_max)
-+			ulmt = UNSPECIFIED_MBM;
-+		else
-+			ulmt = ((tic.ulimit * MBM_PDBM) / hal_spec->txgi_pdbm) + mb_of_ntx(tx_num);
-+		tpc = (tic.tpc * MBM_PDBM) / hal_spec->txgi_pdbm;
-+
-+		if (tic.utarget == hal_spec->txgi_max) {
-+			byr = ((tic.by_rate * MBM_PDBM) / hal_spec->txgi_pdbm) + mb_of_ntx(tx_num);
-+			btc = (tic.btc * MBM_PDBM) / hal_spec->txgi_pdbm;
-+			extra = (tic.extra * MBM_PDBM) / hal_spec->txgi_pdbm;
-+			dump_txpwr_total_dbm_value(sel, adapter, rates_by_sections[rs].rates[i], tic.ntx_idx
-+				, target, byr, btc, extra, rlmt, lmt, ulmt, tpc);
-+		} else {
-+			utgt = ((tic.utarget * MBM_PDBM) / hal_spec->txgi_pdbm) + mb_of_ntx(tx_num);
-+			dump_txpwr_total_dbm_value_utgt(sel, adapter, rates_by_sections[rs].rates[i], tic.ntx_idx
-+				, target, utgt, rlmt, lmt, ulmt, tpc);
-+		}
-+	}
-+}
-+
-+/* dump txpowr in dBm with effect of N-TX */
-+void dump_txpwr_total_dbm(void *sel, _adapter *adapter, enum channel_width bw, u8 cch, u8 opch)
-+{
-+	u8 rs;
-+
-+	dump_txpwr_total_dbm_title(sel, adapter, bw, cch, opch);
-+	for (rs = CCK; rs < RATE_SECTION_NUM; rs++)
-+		dump_txpwr_total_dbm_by_rs(sel, adapter, rs, bw, cch, opch);
-+}
-+#endif
-+
-+bool phy_is_tx_power_limit_needed(_adapter *adapter)
-+{
-+#if CONFIG_TXPWR_LIMIT
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
-+
-+	if (regsty->RegEnableTxPowerLimit == 1
-+		|| (regsty->RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory == 1))
-+		return _TRUE;
-+#endif
-+
-+	return _FALSE;
-+}
-+
-+bool phy_is_tx_power_by_rate_needed(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
-+
-+	if (regsty->RegEnableTxPowerByRate == 1
-+		|| (regsty->RegEnableTxPowerByRate == 2 && hal_data->EEPROMRegulatory != 2))
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	int ret = _FAIL;
-+
-+	hal_data->txpwr_by_rate_loaded = 0;
-+	PHY_InitTxPowerByRate(adapter);
-+
-+	/* tx power limit is based on tx power by rate */
-+	hal_data->txpwr_limit_loaded = 0;
-+
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+	if (chk_file
-+		&& phy_ConfigBBWithPgParaFile(adapter, PHY_FILE_PHY_REG_PG) == _SUCCESS
-+	) {
-+		hal_data->txpwr_by_rate_from_file = 1;
-+		goto post_hdl;
-+	}
-+#endif
-+
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+	if (HAL_STATUS_SUCCESS == odm_config_bb_with_header_file(&hal_data->odmpriv, CONFIG_BB_PHY_REG_PG)) {
-+		RTW_INFO("default power by rate loaded\n");
-+		hal_data->txpwr_by_rate_from_file = 0;
-+		goto post_hdl;
-+	}
-+#endif
-+
-+	RTW_ERR("%s():Read Tx power by rate fail\n", __func__);
-+	goto exit;
-+
-+post_hdl:
-+	if (hal_data->odmpriv.phy_reg_pg_value_type != PHY_REG_PG_EXACT_VALUE) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	PHY_TxPowerByRateConfiguration(adapter);
-+	hal_data->txpwr_by_rate_loaded = 1;
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+#if CONFIG_TXPWR_LIMIT
-+int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	int ret = _FAIL;
-+
-+	hal_data->txpwr_limit_loaded = 0;
-+	rtw_regd_exc_list_free(rfctl);
-+	rtw_txpwr_lmt_list_free(rfctl);
-+
-+	if (!hal_data->txpwr_by_rate_loaded && regsty->target_tx_pwr_valid != _TRUE) {
-+		RTW_ERR("%s():Read Tx power limit before target tx power is specify\n", __func__);
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+	if (chk_file
-+		&& PHY_ConfigRFWithPowerLimitTableParaFile(adapter, PHY_FILE_TXPWR_LMT) == _SUCCESS
-+	) {
-+		hal_data->txpwr_limit_from_file = 1;
-+		goto post_hdl;
-+	}
-+#endif
-+
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+	if (odm_config_rf_with_header_file(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, RF_PATH_A) == HAL_STATUS_SUCCESS) {
-+		RTW_INFO("default power limit loaded\n");
-+		hal_data->txpwr_limit_from_file = 0;
-+		goto post_hdl;
-+	}
-+#endif
-+
-+	RTW_ERR("%s():Read Tx power limit fail\n", __func__);
-+	goto exit;
-+
-+post_hdl:
-+	phy_txpwr_lmt_post_hdl(adapter);
-+	rtw_txpwr_init_regd(rfctl);
-+	hal_data->txpwr_limit_loaded = 1;
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_TXPWR_LIMIT */
-+
-+void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file)
-+{
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+
-+	/* check registy target tx power */
-+	regsty->target_tx_pwr_valid = rtw_regsty_chk_target_tx_power_valid(adapter);
-+
-+	/* power by rate */
-+	if (phy_is_tx_power_by_rate_needed(adapter)
-+		|| regsty->target_tx_pwr_valid != _TRUE /* need target tx power from by rate table */
-+	)
-+		phy_load_tx_power_by_rate(adapter, chk_file);
-+
-+	/* power limit */
-+#if CONFIG_TXPWR_LIMIT
-+	if (phy_is_tx_power_limit_needed(adapter))
-+		phy_load_tx_power_limit(adapter, chk_file);
-+#endif
-+}
-+
-+inline void phy_reload_tx_power_ext_info(_adapter *adapter)
-+{
-+	phy_load_tx_power_ext_info(adapter, 1);
-+	op_class_pref_apply_regulatory(adapter, REG_TXPWR_CHANGE);
-+}
-+
-+inline void phy_reload_default_tx_power_ext_info(_adapter *adapter)
-+{
-+	phy_load_tx_power_ext_info(adapter, 0);
-+	op_class_pref_apply_regulatory(adapter, REG_TXPWR_CHANGE);
-+}
-+
-+#ifdef CONFIG_PROC_DEBUG
-+void dump_tx_power_ext_info(void *sel, _adapter *adapter)
-+{
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+	RTW_PRINT_SEL(sel, "txpwr_pg_mode: %s\n", txpwr_pg_mode_str(hal_data->txpwr_pg_mode));
-+
-+	if (regsty->target_tx_pwr_valid == _TRUE)
-+		RTW_PRINT_SEL(sel, "target_tx_power: from registry\n");
-+	else if (hal_data->txpwr_by_rate_loaded)
-+		RTW_PRINT_SEL(sel, "target_tx_power: from power by rate\n");
-+	else
-+		RTW_PRINT_SEL(sel, "target_tx_power: unavailable\n");
-+
-+	RTW_PRINT_SEL(sel, "tx_power_by_rate: %s, %s, %s\n"
-+		, phy_is_tx_power_by_rate_needed(adapter) ? "enabled" : "disabled"
-+		, hal_data->txpwr_by_rate_loaded ? "loaded" : "unloaded"
-+		, hal_data->txpwr_by_rate_from_file ? "file" : "default"
-+	);
-+
-+	RTW_PRINT_SEL(sel, "tx_power_limit: %s, %s, %s\n"
-+		, phy_is_tx_power_limit_needed(adapter) ? "enabled" : "disabled"
-+		, hal_data->txpwr_limit_loaded ? "loaded" : "unloaded"
-+		, hal_data->txpwr_limit_from_file ? "file" : "default"
-+	);
-+}
-+
-+void dump_target_tx_power(void *sel, _adapter *adapter)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+	int path, tx_num, band, rs;
-+	u8 target;
-+
-+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
-+		if (!hal_is_band_support(adapter, band))
-+			continue;
-+
-+		for (path = 0; path < RF_PATH_MAX; path++) {
-+			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
-+				break;
-+
-+			RTW_PRINT_SEL(sel, "[%s][%c]%s\n", band_str(band), rf_path_char(path)
-+				, (regsty->target_tx_pwr_valid == _FALSE && hal_data->txpwr_by_rate_undefined_band_path[band][path]) ? "(dup)" : "");
-+
-+			for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
-+				tx_num = rate_section_to_tx_num(rs);
-+				if (tx_num + 1 > hal_data->tx_nss)
-+					continue;
-+
-+				if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
-+					continue;
-+
-+				if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
-+					continue;
-+
-+				target = phy_get_target_txpwr(adapter, band, path, rs);
-+
-+				if (target % hal_spec->txgi_pdbm) {
-+					_RTW_PRINT_SEL(sel, "%7s: %2d.%d\n", rate_section_str(rs)
-+						, target / hal_spec->txgi_pdbm, (target % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
-+				} else {
-+					_RTW_PRINT_SEL(sel, "%7s: %5d\n", rate_section_str(rs)
-+						, target / hal_spec->txgi_pdbm);
-+				}
-+			}
-+		}
-+	}
-+
-+	return;
-+}
-+
-+void dump_tx_power_by_rate(void *sel, _adapter *adapter)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	int path, tx_num, band, n, rs;
-+	u8 rate_num, max_rate_num, base;
-+	s8 by_rate;
-+
-+	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
-+		if (!hal_is_band_support(adapter, band))
-+			continue;
-+
-+		for (path = 0; path < RF_PATH_MAX; path++) {
-+			if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
-+				break;
-+
-+			RTW_PRINT_SEL(sel, "[%s][%c]%s\n", band_str(band), rf_path_char(path)
-+				, hal_data->txpwr_by_rate_undefined_band_path[band][path] ? "(dup)" : "");
-+
-+			for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
-+				tx_num = rate_section_to_tx_num(rs);
-+				if (tx_num + 1 > hal_data->tx_nss)
-+					continue;
-+
-+				if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
-+					continue;
-+
-+				if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
-+					continue;
-+
-+				if (IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
-+					max_rate_num = 10;
-+				else
-+					max_rate_num = 8;
-+				rate_num = rate_section_rate_num(rs);
-+
-+				RTW_PRINT_SEL(sel, "%7s: ", rate_section_str(rs));
-+
-+				/* dump power by rate in db */
-+				for (n = rate_num - 1; n >= 0; n--) {
-+					by_rate = phy_get_txpwr_by_rate(adapter, band, path, rs, rates_by_sections[rs].rates[n]);
-+					if (by_rate % hal_spec->txgi_pdbm) {
-+						_RTW_PRINT_SEL(sel, "%2d.%d ", by_rate / hal_spec->txgi_pdbm
-+							, (by_rate % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm);
-+					} else
-+						_RTW_PRINT_SEL(sel, "%5d ", by_rate / hal_spec->txgi_pdbm);
-+				}
-+				for (n = 0; n < max_rate_num - rate_num; n++)
-+					_RTW_PRINT_SEL(sel, "%5s ", "");
-+
-+				_RTW_PRINT_SEL(sel, "|");
-+
-+				/* dump power by rate in offset */
-+				for (n = rate_num - 1; n >= 0; n--) {
-+					by_rate = phy_get_txpwr_by_rate(adapter, band, path, rs, rates_by_sections[rs].rates[n]);
-+					base = phy_get_target_txpwr(adapter, band, path, rs);
-+					_RTW_PRINT_SEL(sel, "%3d ", by_rate - base);
-+				}
-+				RTW_PRINT_SEL(sel, "\n");
-+
-+			}
-+		}
-+	}
-+}
-+#endif
-+/*
-+ * phy file path is stored in global char array rtw_phy_para_file_path
-+ * need to care about racing
-+ */
-+int rtw_get_phy_file_path(_adapter *adapter, const char *file_name)
-+{
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	int len = 0;
-+
-+	if (file_name) {
-+		len += snprintf(rtw_phy_para_file_path, PATH_LENGTH_MAX, "%s", rtw_phy_file_path);
-+		#if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER)
-+		len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s/", hal_spec->ic_name);
-+		#endif
-+		len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s", file_name);
-+
-+		return _TRUE;
-+	}
-+#endif
-+	return _FALSE;
-+}
-+
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+int
-+phy_ConfigMACWithParaFile(
-+		PADAPTER	Adapter,
-+		char		*pFileName
-+)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+	int	rlen = 0, rtStatus = _FAIL;
-+	char	*szLine, *ptmp;
-+	u32	u4bRegOffset, u4bRegValue, u4bMove;
-+
-+	if (!(Adapter->registrypriv.load_phy_file & LOAD_MAC_PARA_FILE))
-+		return rtStatus;
-+
-+	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
-+
-+	if ((pHalData->mac_reg_len == 0) && (pHalData->mac_reg == NULL)) {
-+		rtw_get_phy_file_path(Adapter, pFileName);
-+		if (rtw_readable_file_sz_chk(rtw_phy_para_file_path, 
-+			MAX_PARA_FILE_BUF_LEN) == _TRUE) {
-+			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
-+			if (rlen > 0) {
-+				rtStatus = _SUCCESS;
-+				pHalData->mac_reg = rtw_zvmalloc(rlen);
-+				if (pHalData->mac_reg) {
-+					_rtw_memcpy(pHalData->mac_reg, pHalData->para_file_buf, rlen);
-+					pHalData->mac_reg_len = rlen;
-+				} else
-+					RTW_INFO("%s mac_reg alloc fail !\n", __FUNCTION__);
-+			}
-+		}
-+	} else {
-+		if ((pHalData->mac_reg_len != 0) && (pHalData->mac_reg != NULL)) {
-+			_rtw_memcpy(pHalData->para_file_buf, pHalData->mac_reg, pHalData->mac_reg_len);
-+			rtStatus = _SUCCESS;
-+		} else
-+			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
-+	}
-+
-+	if (rtStatus == _SUCCESS) {
-+		ptmp = pHalData->para_file_buf;
-+		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
-+			if (!IsCommentString(szLine)) {
-+				/* Get 1st hex value as register offset */
-+				if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
-+					if (u4bRegOffset == 0xffff) {
-+						/* Ending. */
-+						break;
-+					}
-+
-+					/* Get 2nd hex value as register value. */
-+					szLine += u4bMove;
-+					if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove))
-+						rtw_write8(Adapter, u4bRegOffset, (u8)u4bRegValue);
-+				}
-+			}
-+		}
-+	} else
-+		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
-+
-+	return rtStatus;
-+}
-+
-+int
-+phy_ConfigBBWithParaFile(
-+		PADAPTER	Adapter,
-+		char		*pFileName,
-+		u32			ConfigType
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	int	rlen = 0, rtStatus = _FAIL;
-+	char	*szLine, *ptmp;
-+	u32	u4bRegOffset, u4bRegValue, u4bMove;
-+	char	*pBuf = NULL;
-+	u32	*pBufLen = NULL;
-+
-+	if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_PARA_FILE))
-+		return rtStatus;
-+
-+	switch (ConfigType) {
-+	case CONFIG_BB_PHY_REG:
-+		pBuf = pHalData->bb_phy_reg;
-+		pBufLen = &pHalData->bb_phy_reg_len;
-+		break;
-+	case CONFIG_BB_AGC_TAB:
-+		pBuf = pHalData->bb_agc_tab;
-+		pBufLen = &pHalData->bb_agc_tab_len;
-+		break;
-+	default:
-+		RTW_INFO("Unknown ConfigType!! %d\r\n", ConfigType);
-+		break;
-+	}
-+
-+	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
-+
-+	if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) {
-+		rtw_get_phy_file_path(Adapter, pFileName);
-+		if (rtw_readable_file_sz_chk(rtw_phy_para_file_path, 
-+			MAX_PARA_FILE_BUF_LEN) == _TRUE) {
-+			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
-+			if (rlen > 0) {
-+				rtStatus = _SUCCESS;
-+				pBuf = rtw_zvmalloc(rlen);
-+				if (pBuf) {
-+					_rtw_memcpy(pBuf, pHalData->para_file_buf, rlen);
-+					*pBufLen = rlen;
-+
-+					switch (ConfigType) {
-+					case CONFIG_BB_PHY_REG:
-+						pHalData->bb_phy_reg = pBuf;
-+						break;
-+					case CONFIG_BB_AGC_TAB:
-+						pHalData->bb_agc_tab = pBuf;
-+						break;
-+					}
-+				} else
-+					RTW_INFO("%s(): ConfigType %d  alloc fail !\n", __FUNCTION__, ConfigType);
-+			}
-+		}
-+	} else {
-+		if ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) {
-+			_rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen);
-+			rtStatus = _SUCCESS;
-+		} else
-+			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
-+	}
-+
-+	if (rtStatus == _SUCCESS) {
-+		ptmp = pHalData->para_file_buf;
-+		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
-+			if (!IsCommentString(szLine)) {
-+				/* Get 1st hex value as register offset. */
-+				if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
-+					if (u4bRegOffset == 0xffff) {
-+						/* Ending. */
-+						break;
-+					} else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
-+#ifdef CONFIG_LONG_DELAY_ISSUE
-+						rtw_msleep_os(50);
-+#else
-+						rtw_mdelay_os(50);
-+#endif
-+					} else if (u4bRegOffset == 0xfd)
-+						rtw_mdelay_os(5);
-+					else if (u4bRegOffset == 0xfc)
-+						rtw_mdelay_os(1);
-+					else if (u4bRegOffset == 0xfb)
-+						rtw_udelay_os(50);
-+					else if (u4bRegOffset == 0xfa)
-+						rtw_udelay_os(5);
-+					else if (u4bRegOffset == 0xf9)
-+						rtw_udelay_os(1);
-+
-+					/* Get 2nd hex value as register value. */
-+					szLine += u4bMove;
-+					if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
-+						/* RTW_INFO("[BB-ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */
-+						phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
-+
-+						if (u4bRegOffset == 0xa24)
-+							pHalData->odmpriv.rf_calibrate_info.rega24 = u4bRegValue;
-+
-+						/* Add 1us delay between BB/RF register setting. */
-+						rtw_udelay_os(1);
-+					}
-+				}
-+			}
-+		}
-+	} else
-+		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
-+
-+	return rtStatus;
-+}
-+
-+void
-+phy_DecryptBBPgParaFile(
-+	PADAPTER		Adapter,
-+	char			*buffer
-+)
-+{
-+	u32	i = 0, j = 0;
-+	u8	map[95] = {0};
-+	u8	currentChar;
-+	char	*BufOfLines, *ptmp;
-+
-+	/* RTW_INFO("=====>phy_DecryptBBPgParaFile()\n"); */
-+	/* 32 the ascii code of the first visable char, 126 the last one */
-+	for (i = 0; i < 95; ++i)
-+		map[i] = (u8)(94 - i);
-+
-+	ptmp = buffer;
-+	i = 0;
-+	for (BufOfLines = GetLineFromBuffer(ptmp); BufOfLines != NULL; BufOfLines = GetLineFromBuffer(ptmp)) {
-+		/* RTW_INFO("Encrypted Line: %s\n", BufOfLines); */
-+
-+		for (j = 0; j < strlen(BufOfLines); ++j) {
-+			currentChar = BufOfLines[j];
-+
-+			if (currentChar == '\0')
-+				break;
-+
-+			currentChar -= (u8)((((i + j) * 3) % 128));
-+
-+			BufOfLines[j] = map[currentChar - 32] + 32;
-+		}
-+		/* RTW_INFO("Decrypted Line: %s\n", BufOfLines ); */
-+		if (strlen(BufOfLines) != 0)
-+			i++;
-+		BufOfLines[strlen(BufOfLines)] = '\n';
-+	}
-+}
-+
-+#ifndef DBG_TXPWR_BY_RATE_FILE_PARSE
-+#define DBG_TXPWR_BY_RATE_FILE_PARSE 0
-+#endif
-+
-+int
-+phy_ParseBBPgParaFile(
-+	PADAPTER		Adapter,
-+	char			*buffer
-+)
-+{
-+	int	rtStatus = _FAIL;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
-+	char	*szLine, *ptmp;
-+	u32	u4bRegOffset, u4bRegMask;
-+	u32	u4bMove;
-+	BOOLEAN firstLine = _TRUE;
-+	u8	tx_num = 0;
-+	u8	band = 0, rf_path = 0;
-+
-+	if (Adapter->registrypriv.RegDecryptCustomFile == 1)
-+		phy_DecryptBBPgParaFile(Adapter, buffer);
-+
-+	ptmp = buffer;
-+	for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
-+		if (isAllSpaceOrTab(szLine, sizeof(*szLine)))
-+			continue;
-+
-+		if (!IsCommentString(szLine)) {
-+			/* Get header info (relative value or exact value) */
-+			if (firstLine) {
-+				if (strncmp(szLine, "#[v1]", 5) == 0
-+					|| strncmp(szLine, "#[v2]", 5) == 0)
-+					pHalData->odmpriv.phy_reg_pg_version = szLine[3] - '0';
-+				else {
-+					RTW_ERR("The format in PHY_REG_PG are invalid %s\n", szLine);
-+					goto exit;
-+				}
-+
-+				if (strncmp(szLine + 5, "[Exact]#", 8) == 0) {
-+					pHalData->odmpriv.phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
-+					firstLine = _FALSE;
-+					continue;
-+				} else {
-+					RTW_ERR("The values in PHY_REG_PG are invalid %s\n", szLine);
-+					goto exit;
-+				}
-+			}
-+
-+			if (pHalData->odmpriv.phy_reg_pg_version > 0) {
-+				u32	index = 0;
-+
-+				if (strncmp(szLine, "0xffff", 6) == 0)
-+					break;
-+
-+				if (strncmp(szLine, "#[END]#", 7)) {
-+					/* load the table label info */
-+					if (szLine[0] == '#') {
-+						index = 0;
-+						if (strncmp(szLine, "#[2.4G]", 7) == 0) {
-+							band = BAND_ON_2_4G;
-+							index += 8;
-+						} else if (strncmp(szLine, "#[5G]", 5) == 0) {
-+							band = BAND_ON_5G;
-+							index += 6;
-+						} else {
-+							RTW_ERR("Invalid band %s in PHY_REG_PG.txt\n", szLine);
-+							goto exit;
-+						}
-+
-+						rf_path = szLine[index] - 'A';
-+						if (DBG_TXPWR_BY_RATE_FILE_PARSE)
-+							RTW_INFO(" Table label Band %d, RfPath %d\n", band, rf_path );
-+					} else { /* load rows of tables */
-+						if (szLine[1] == '1')
-+							tx_num = RF_1TX;
-+						else if (szLine[1] == '2')
-+							tx_num = RF_2TX;
-+						else if (szLine[1] == '3')
-+							tx_num = RF_3TX;
-+						else if (szLine[1] == '4')
-+							tx_num = RF_4TX;
-+						else {
-+							RTW_ERR("Invalid row in PHY_REG_PG.txt '%c'(%d)\n", szLine[1], szLine[1]);
-+							goto exit;
-+						}
-+
-+						while (szLine[index] != ']')
-+							++index;
-+						++index;/* skip ] */
-+
-+						/* Get 2nd hex value as register offset. */
-+						szLine += index;
-+						if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove))
-+							szLine += u4bMove;
-+						else
-+							goto exit;
-+
-+						/* Get 2nd hex value as register mask. */
-+						if (GetHexValueFromString(szLine, &u4bRegMask, &u4bMove))
-+							szLine += u4bMove;
-+						else
-+							goto exit;
-+
-+						if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) {
-+							u32	combineValue = 0;
-+							u8	integer = 0, fraction = 0;
-+
-+							if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
-+								szLine += u4bMove;
-+							else
-+								goto exit;
-+
-+							integer *= hal_spec->txgi_pdbm;
-+							integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
-+							if (pHalData->odmpriv.phy_reg_pg_version == 1)
-+								combineValue |= (((integer / 10) << 4) + (integer % 10));
-+							else
-+								combineValue |= integer;
-+
-+							if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
-+								szLine += u4bMove;
-+							else
-+								goto exit;
-+
-+							integer *= hal_spec->txgi_pdbm;
-+							integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
-+							combineValue <<= 8;
-+							if (pHalData->odmpriv.phy_reg_pg_version == 1)
-+								combineValue |= (((integer / 10) << 4) + (integer % 10));
-+							else
-+								combineValue |= integer;
-+
-+							if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
-+								szLine += u4bMove;
-+							else
-+								goto exit;
-+
-+							integer *= hal_spec->txgi_pdbm;
-+							integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
-+							combineValue <<= 8;
-+							if (pHalData->odmpriv.phy_reg_pg_version == 1)
-+								combineValue |= (((integer / 10) << 4) + (integer % 10));
-+							else
-+								combineValue |= integer;
-+
-+							if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove))
-+								szLine += u4bMove;
-+							else
-+								goto exit;
-+
-+							integer *= hal_spec->txgi_pdbm;
-+							integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
-+							combineValue <<= 8;
-+							if (pHalData->odmpriv.phy_reg_pg_version == 1)
-+								combineValue |= (((integer / 10) << 4) + (integer % 10));
-+							else
-+								combineValue |= integer;
-+
-+							phy_store_tx_power_by_rate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, combineValue);
-+
-+							if (DBG_TXPWR_BY_RATE_FILE_PARSE)
-+								RTW_INFO("addr:0x%3x mask:0x%08x %dTx = 0x%08x\n", u4bRegOffset, u4bRegMask, tx_num + 1, combineValue);
-+						}
-+					}
-+				}
-+			}
-+		}
-+	}
-+
-+	rtStatus = _SUCCESS;
-+
-+exit:
-+	RTW_INFO("%s return %d\n", __func__, rtStatus);
-+	return rtStatus;
-+}
-+
-+int
-+phy_ConfigBBWithPgParaFile(
-+		PADAPTER	Adapter,
-+		const char	*pFileName)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	int	rlen = 0, rtStatus = _FAIL;
-+
-+	if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_PG_PARA_FILE))
-+		return rtStatus;
-+
-+	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
-+
-+	if (pHalData->bb_phy_reg_pg == NULL) {
-+		rtw_get_phy_file_path(Adapter, pFileName);
-+		if (rtw_readable_file_sz_chk(rtw_phy_para_file_path, 
-+			MAX_PARA_FILE_BUF_LEN) == _TRUE) {
-+			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
-+			if (rlen > 0) {
-+				rtStatus = _SUCCESS;
-+				pHalData->bb_phy_reg_pg = rtw_zvmalloc(rlen);
-+				if (pHalData->bb_phy_reg_pg) {
-+					_rtw_memcpy(pHalData->bb_phy_reg_pg, pHalData->para_file_buf, rlen);
-+					pHalData->bb_phy_reg_pg_len = rlen;
-+				} else
-+					RTW_INFO("%s bb_phy_reg_pg alloc fail !\n", __FUNCTION__);
-+			}
-+		}
-+	} else {
-+		if ((pHalData->bb_phy_reg_pg_len != 0) && (pHalData->bb_phy_reg_pg != NULL)) {
-+			_rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len);
-+			rtStatus = _SUCCESS;
-+		} else
-+			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
-+	}
-+
-+	if (rtStatus == _SUCCESS) {
-+		/* RTW_INFO("phy_ConfigBBWithPgParaFile(): read %s ok\n", pFileName); */
-+		rtStatus = phy_ParseBBPgParaFile(Adapter, pHalData->para_file_buf);
-+	} else
-+		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
-+
-+	return rtStatus;
-+}
-+
-+#if (MP_DRIVER == 1)
-+
-+int
-+phy_ConfigBBWithMpParaFile(
-+		PADAPTER	Adapter,
-+		char		*pFileName
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	int	rlen = 0, rtStatus = _FAIL;
-+	char	*szLine, *ptmp;
-+	u32	u4bRegOffset, u4bRegValue, u4bMove;
-+
-+	if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_MP_PARA_FILE))
-+		return rtStatus;
-+
-+	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
-+
-+	if ((pHalData->bb_phy_reg_mp_len == 0) && (pHalData->bb_phy_reg_mp == NULL)) {
-+		rtw_get_phy_file_path(Adapter, pFileName);
-+		if (rtw_readable_file_sz_chk(rtw_phy_para_file_path, 
-+			MAX_PARA_FILE_BUF_LEN) == _TRUE) {
-+			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
-+			if (rlen > 0) {
-+				rtStatus = _SUCCESS;
-+				pHalData->bb_phy_reg_mp = rtw_zvmalloc(rlen);
-+				if (pHalData->bb_phy_reg_mp) {
-+					_rtw_memcpy(pHalData->bb_phy_reg_mp, pHalData->para_file_buf, rlen);
-+					pHalData->bb_phy_reg_mp_len = rlen;
-+				} else
-+					RTW_INFO("%s bb_phy_reg_mp alloc fail !\n", __FUNCTION__);
-+			}
-+		}
-+	} else {
-+		if ((pHalData->bb_phy_reg_mp_len != 0) && (pHalData->bb_phy_reg_mp != NULL)) {
-+			_rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len);
-+			rtStatus = _SUCCESS;
-+		} else
-+			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
-+	}
-+
-+	if (rtStatus == _SUCCESS) {
-+		/* RTW_INFO("phy_ConfigBBWithMpParaFile(): read %s ok\n", pFileName); */
-+
-+		ptmp = pHalData->para_file_buf;
-+		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
-+			if (!IsCommentString(szLine)) {
-+				/* Get 1st hex value as register offset. */
-+				if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
-+					if (u4bRegOffset == 0xffff) {
-+						/* Ending. */
-+						break;
-+					} else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
-+#ifdef CONFIG_LONG_DELAY_ISSUE
-+						rtw_msleep_os(50);
-+#else
-+						rtw_mdelay_os(50);
-+#endif
-+					} else if (u4bRegOffset == 0xfd)
-+						rtw_mdelay_os(5);
-+					else if (u4bRegOffset == 0xfc)
-+						rtw_mdelay_os(1);
-+					else if (u4bRegOffset == 0xfb)
-+						rtw_udelay_os(50);
-+					else if (u4bRegOffset == 0xfa)
-+						rtw_udelay_os(5);
-+					else if (u4bRegOffset == 0xf9)
-+						rtw_udelay_os(1);
-+
-+					/* Get 2nd hex value as register value. */
-+					szLine += u4bMove;
-+					if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
-+						/* RTW_INFO("[ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */
-+						phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
-+
-+						/* Add 1us delay between BB/RF register setting. */
-+						rtw_udelay_os(1);
-+					}
-+				}
-+			}
-+		}
-+	} else
-+		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
-+
-+	return rtStatus;
-+}
-+
-+#endif
-+
-+int
-+PHY_ConfigRFWithParaFile(
-+		PADAPTER	Adapter,
-+		char		*pFileName,
-+		enum rf_path		eRFPath
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	int	rlen = 0, rtStatus = _FAIL;
-+	char	*szLine, *ptmp;
-+	u32	u4bRegOffset, u4bRegValue, u4bMove;
-+	u16	i;
-+	char	*pBuf = NULL;
-+	u32	*pBufLen = NULL;
-+
-+	if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_PARA_FILE))
-+		return rtStatus;
-+
-+	switch (eRFPath) {
-+	case RF_PATH_A:
-+		pBuf = pHalData->rf_radio_a;
-+		pBufLen = &pHalData->rf_radio_a_len;
-+		break;
-+	case RF_PATH_B:
-+		pBuf = pHalData->rf_radio_b;
-+		pBufLen = &pHalData->rf_radio_b_len;
-+		break;
-+	default:
-+		RTW_INFO("Unknown RF path!! %d\r\n", eRFPath);
-+		break;
-+	}
-+
-+	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
-+
-+	if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) {
-+		rtw_get_phy_file_path(Adapter, pFileName);
-+		if (rtw_readable_file_sz_chk(rtw_phy_para_file_path, 
-+			MAX_PARA_FILE_BUF_LEN) == _TRUE) {
-+			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
-+			if (rlen > 0) {
-+				rtStatus = _SUCCESS;
-+				pBuf = rtw_zvmalloc(rlen);
-+				if (pBuf) {
-+					_rtw_memcpy(pBuf, pHalData->para_file_buf, rlen);
-+					*pBufLen = rlen;
-+
-+					switch (eRFPath) {
-+					case RF_PATH_A:
-+						pHalData->rf_radio_a = pBuf;
-+						break;
-+					case RF_PATH_B:
-+						pHalData->rf_radio_b = pBuf;
-+						break;
-+					default:
-+						RTW_INFO("Unknown RF path!! %d\r\n", eRFPath);
-+						break;
-+					}
-+				} else
-+					RTW_INFO("%s(): eRFPath=%d  alloc fail !\n", __FUNCTION__, eRFPath);
-+			}
-+		}
-+	} else {
-+		if ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) {
-+			_rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen);
-+			rtStatus = _SUCCESS;
-+		} else
-+			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
-+	}
-+
-+	if (rtStatus == _SUCCESS) {
-+		/* RTW_INFO("%s(): read %s successfully\n", __FUNCTION__, pFileName); */
-+
-+		ptmp = pHalData->para_file_buf;
-+		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
-+			if (!IsCommentString(szLine)) {
-+				/* Get 1st hex value as register offset. */
-+				if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
-+					if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) {
-+						/* Deay specific ms. Only RF configuration require delay.												 */
-+#ifdef CONFIG_LONG_DELAY_ISSUE
-+						rtw_msleep_os(50);
-+#else
-+						rtw_mdelay_os(50);
-+#endif
-+					} else if (u4bRegOffset == 0xfd) {
-+						/* delay_ms(5); */
-+						for (i = 0; i < 100; i++)
-+							rtw_udelay_os(MAX_STALL_TIME);
-+					} else if (u4bRegOffset == 0xfc) {
-+						/* delay_ms(1); */
-+						for (i = 0; i < 20; i++)
-+							rtw_udelay_os(MAX_STALL_TIME);
-+					} else if (u4bRegOffset == 0xfb)
-+						rtw_udelay_os(50);
-+					else if (u4bRegOffset == 0xfa)
-+						rtw_udelay_os(5);
-+					else if (u4bRegOffset == 0xf9)
-+						rtw_udelay_os(1);
-+					else if (u4bRegOffset == 0xffff)
-+						break;
-+
-+					/* Get 2nd hex value as register value. */
-+					szLine += u4bMove;
-+					if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
-+						phy_set_rf_reg(Adapter, eRFPath, u4bRegOffset, bRFRegOffsetMask, u4bRegValue);
-+
-+						/* Temp add, for frequency lock, if no delay, that may cause */
-+						/* frequency shift, ex: 2412MHz => 2417MHz */
-+						/* If frequency shift, the following action may works. */
-+						/* Fractional-N table in radio_a.txt */
-+						/* 0x2a 0x00001		 */ /* channel 1 */
-+						/* 0x2b 0x00808		frequency divider. */
-+						/* 0x2b 0x53333 */
-+						/* 0x2c 0x0000c */
-+						rtw_udelay_os(1);
-+					}
-+				}
-+			}
-+		}
-+	} else
-+		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
-+
-+	return rtStatus;
-+}
-+
-+void
-+initDeltaSwingIndexTables(
-+	PADAPTER	Adapter,
-+	char		*Band,
-+	char		*Path,
-+	char		*Sign,
-+	char		*Channel,
-+	char		*Rate,
-+	char		*Data
-+)
-+{
-+#define STR_EQUAL_5G(_band, _path, _sign, _rate, _chnl) \
-+	((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\
-+	 (strcmp(Rate, _rate) == 0) && (strcmp(Channel, _chnl) == 0)\
-+	)
-+#define STR_EQUAL_2G(_band, _path, _sign, _rate) \
-+	((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\
-+	 (strcmp(Rate, _rate) == 0)\
-+	)
-+
-+#define STORE_SWING_TABLE(_array, _iteratedIdx) \
-+	do {	\
-+	for (token = strsep(&Data, delim); token != NULL; token = strsep(&Data, delim)) {\
-+		sscanf(token, "%d", &idx);\
-+		_array[_iteratedIdx++] = (u8)idx;\
-+	} } while (0)\
-+
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
-+	struct dm_rf_calibration_struct	*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
-+	u32	j = 0;
-+	char	*token;
-+	char	delim[] = ",";
-+	u32	idx = 0;
-+
-+	/* RTW_INFO("===>initDeltaSwingIndexTables(): Band: %s;\nPath: %s;\nSign: %s;\nChannel: %s;\nRate: %s;\n, Data: %s;\n",  */
-+	/*	Band, Path, Sign, Channel, Rate, Data); */
-+
-+	if (STR_EQUAL_2G("2G", "A", "+", "CCK"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p, j);
-+	else if (STR_EQUAL_2G("2G", "A", "-", "CCK"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n, j);
-+	else if (STR_EQUAL_2G("2G", "B", "+", "CCK"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p, j);
-+	else if (STR_EQUAL_2G("2G", "B", "-", "CCK"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n, j);
-+	else if (STR_EQUAL_2G("2G", "A", "+", "ALL"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_p, j);
-+	else if (STR_EQUAL_2G("2G", "A", "-", "ALL"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_n, j);
-+	else if (STR_EQUAL_2G("2G", "B", "+", "ALL"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_p, j);
-+	else if (STR_EQUAL_2G("2G", "B", "-", "ALL"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_n, j);
-+	else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "0"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[0], j);
-+	else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "0"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[0], j);
-+	else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "0"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[0], j);
-+	else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "0"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[0], j);
-+	else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "1"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[1], j);
-+	else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "1"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[1], j);
-+	else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "1"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[1], j);
-+	else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "1"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[1], j);
-+	else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "2"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[2], j);
-+	else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "2"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[2], j);
-+	else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "2"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[2], j);
-+	else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "2"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[2], j);
-+	else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "3"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[3], j);
-+	else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "3"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[3], j);
-+	else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "3"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[3], j);
-+	else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "3"))
-+		STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[3], j);
-+	else
-+		RTW_INFO("===>initDeltaSwingIndexTables(): The input is invalid!!\n");
-+}
-+
-+int
-+PHY_ConfigRFWithTxPwrTrackParaFile(
-+		PADAPTER		Adapter,
-+		char			*pFileName
-+)
-+{
-+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
-+	struct dm_struct			*pDM_Odm = &pHalData->odmpriv;
-+	int	rlen = 0, rtStatus = _FAIL;
-+	char	*szLine, *ptmp;
-+	u32	i = 0;
-+
-+	if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_TRACK_PARA_FILE))
-+		return rtStatus;
-+
-+	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
-+
-+	if ((pHalData->rf_tx_pwr_track_len == 0) && (pHalData->rf_tx_pwr_track == NULL)) {
-+		rtw_get_phy_file_path(Adapter, pFileName);
-+		if (rtw_readable_file_sz_chk(rtw_phy_para_file_path, 
-+			MAX_PARA_FILE_BUF_LEN) == _TRUE) {
-+			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
-+			if (rlen > 0) {
-+				rtStatus = _SUCCESS;
-+				pHalData->rf_tx_pwr_track = rtw_zvmalloc(rlen);
-+				if (pHalData->rf_tx_pwr_track) {
-+					_rtw_memcpy(pHalData->rf_tx_pwr_track, pHalData->para_file_buf, rlen);
-+					pHalData->rf_tx_pwr_track_len = rlen;
-+				} else
-+					RTW_INFO("%s rf_tx_pwr_track alloc fail !\n", __FUNCTION__);
-+			}
-+		}
-+	} else {
-+		if ((pHalData->rf_tx_pwr_track_len != 0) && (pHalData->rf_tx_pwr_track != NULL)) {
-+			_rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len);
-+			rtStatus = _SUCCESS;
-+		} else
-+			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
-+	}
-+
-+	if (rtStatus == _SUCCESS) {
-+		/* RTW_INFO("%s(): read %s successfully\n", __FUNCTION__, pFileName); */
-+
-+		ptmp = pHalData->para_file_buf;
-+		for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
-+			if (!IsCommentString(szLine)) {
-+				char	band[5] = "", path[5] = "", sign[5]  = "";
-+				char	chnl[5] = "", rate[10] = "";
-+				char	data[300] = ""; /* 100 is too small */
-+
-+				if (strlen(szLine) < 10 || szLine[0] != '[')
-+					continue;
-+
-+				strncpy(band, szLine + 1, 2);
-+				strncpy(path, szLine + 5, 1);
-+				strncpy(sign, szLine + 8, 1);
-+
-+				i = 10; /* szLine+10 */
-+				if (!ParseQualifiedString(szLine, &i, rate, '[', ']')) {
-+					/* RTW_INFO("Fail to parse rate!\n"); */
-+				}
-+				if (!ParseQualifiedString(szLine, &i, chnl, '[', ']')) {
-+					/* RTW_INFO("Fail to parse channel group!\n"); */
-+				}
-+				while (szLine[i] != '{' && i < strlen(szLine))
-+					i++;
-+				if (!ParseQualifiedString(szLine, &i, data, '{', '}')) {
-+					/* RTW_INFO("Fail to parse data!\n"); */
-+				}
-+
-+				initDeltaSwingIndexTables(Adapter, band, path, sign, chnl, rate, data);
-+			}
-+		}
-+	} else
-+		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
-+#if 0
-+	for (i = 0; i < DELTA_SWINGIDX_SIZE; ++i) {
-+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2ga_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_p[i]);
-+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2ga_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_n[i]);
-+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2gb_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_p[i]);
-+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2gb_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_n[i]);
-+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[i]);
-+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[i]);
-+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[i]);
-+		RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[i]);
-+
-+		for (j = 0; j < 3; ++j) {
-+			RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5ga_p[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_p[j][i]);
-+			RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5ga_n[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_n[j][i]);
-+			RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5gb_p[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_p[j][i]);
-+			RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5gb_n[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_n[j][i]);
-+		}
-+	}
-+#endif
-+	return rtStatus;
-+}
-+
-+#if CONFIG_TXPWR_LIMIT
-+
-+#ifndef DBG_TXPWR_LMT_FILE_PARSE
-+#define DBG_TXPWR_LMT_FILE_PARSE 0
-+#endif
-+
-+#define PARSE_RET_NO_HDL	0
-+#define PARSE_RET_SUCCESS	1
-+#define PARSE_RET_FAIL		2
-+
-+/*
-+* @@Ver=2.0
-+* or
-+* @@DomainCode=0x28, Regulation=C6
-+* or
-+* @@CountryCode=GB, Regulation=C7
-+*/
-+static u8 parse_reg_exc_config(_adapter *adapter, char *szLine)
-+{
-+#define VER_PREFIX "Ver="
-+#define DOMAIN_PREFIX "DomainCode=0x"
-+#define COUNTRY_PREFIX "CountryCode="
-+#define REG_PREFIX "Regulation="
-+
-+	const u8 ver_prefix_len = strlen(VER_PREFIX);
-+	const u8 domain_prefix_len = strlen(DOMAIN_PREFIX);
-+	const u8 country_prefix_len = strlen(COUNTRY_PREFIX);
-+	const u8 reg_prefix_len = strlen(REG_PREFIX);
-+	u32 i, i_val_s, i_val_e;
-+	u32 j;
-+	u8 domain = 0xFF;
-+	char *country = NULL;
-+	u8 parse_reg = 0;
-+
-+	if (szLine[0] != '@' || szLine[1] != '@')
-+		return PARSE_RET_NO_HDL;
-+
-+	i = 2;
-+	if (strncmp(szLine + i, VER_PREFIX, ver_prefix_len) == 0)
-+		; /* nothing to do */
-+	else if (strncmp(szLine + i, DOMAIN_PREFIX, domain_prefix_len) == 0) {
-+		/* get string after domain prefix to ',' */
-+		i += domain_prefix_len;
-+		i_val_s = i;
-+		while (szLine[i] != ',') {
-+			if (szLine[i] == '\0')
-+				return PARSE_RET_FAIL;
-+			i++;
-+		}
-+		i_val_e = i;
-+
-+		/* check if all hex */
-+		for (j = i_val_s; j < i_val_e; j++)
-+			if (IsHexDigit(szLine[j]) == _FALSE)
-+				return PARSE_RET_FAIL;
-+
-+		/* get value from hex string */
-+		if (sscanf(szLine + i_val_s, "%hhx", &domain) != 1)
-+			return PARSE_RET_FAIL;
-+
-+		parse_reg = 1;
-+	} else if (strncmp(szLine + i, COUNTRY_PREFIX, country_prefix_len) == 0) {
-+		/* get string after country prefix to ',' */
-+		i += country_prefix_len;
-+		i_val_s = i;
-+		while (szLine[i] != ',') {
-+			if (szLine[i] == '\0')
-+				return PARSE_RET_FAIL;
-+			i++;
-+		}
-+		i_val_e = i;
-+
-+		if (i_val_e - i_val_s != 2)
-+			return PARSE_RET_FAIL;
-+
-+		/* check if all alpha */
-+		for (j = i_val_s; j < i_val_e; j++)
-+			if (is_alpha(szLine[j]) == _FALSE)
-+				return PARSE_RET_FAIL;
-+
-+		country = szLine + i_val_s;
-+
-+		parse_reg = 1;
-+
-+	} else
-+		return PARSE_RET_FAIL;
-+
-+	if (parse_reg) {
-+		/* move to 'R' */
-+		while (szLine[i] != 'R') {
-+			if (szLine[i] == '\0')
-+				return PARSE_RET_FAIL;
-+			i++;
-+		}
-+
-+		/* check if matching regulation prefix */
-+		if (strncmp(szLine + i, REG_PREFIX, reg_prefix_len) != 0)
-+			return PARSE_RET_FAIL;
-+
-+		/* get string after regulation prefix ending with space */
-+		i += reg_prefix_len;
-+		i_val_s = i;
-+		while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0')
-+			i++;
-+
-+		if (i == i_val_s)
-+			return PARSE_RET_FAIL;
-+
-+		rtw_regd_exc_add_with_nlen(adapter_to_rfctl(adapter), country, domain, szLine + i_val_s, i - i_val_s);
-+	}
-+
-+	return PARSE_RET_SUCCESS;
-+}
-+
-+static int
-+phy_ParsePowerLimitTableFile(
-+	PADAPTER		Adapter,
-+	char			*buffer
-+)
-+{
-+#define LD_STAGE_EXC_MAPPING	0
-+#define LD_STAGE_TAB_DEFINE		1
-+#define LD_STAGE_TAB_START		2
-+#define LD_STAGE_COLUMN_DEFINE	3
-+#define LD_STAGE_CH_ROW			4
-+
-+	int	rtStatus = _FAIL;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
-+	struct dm_struct	*pDM_Odm = &(pHalData->odmpriv);
-+	u8	loadingStage = LD_STAGE_EXC_MAPPING;
-+	u32	i = 0, forCnt = 0;
-+	char	*szLine, *ptmp;
-+	char band[10], bandwidth[10], rateSection[10], ntx[10], colNumBuf[10];
-+	char **regulation = NULL;
-+	u8	colNum = 0;
-+
-+	if (Adapter->registrypriv.RegDecryptCustomFile == 1)
-+		phy_DecryptBBPgParaFile(Adapter, buffer);
-+
-+	ptmp = buffer;
-+	for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
-+		if (isAllSpaceOrTab(szLine, sizeof(*szLine)))
-+			continue;
-+		if (IsCommentString(szLine))
-+			continue;
-+
-+		if (loadingStage == LD_STAGE_EXC_MAPPING) {
-+			if (szLine[0] == '#' || szLine[1] == '#') {
-+				loadingStage = LD_STAGE_TAB_DEFINE;
-+				if (DBG_TXPWR_LMT_FILE_PARSE)
-+					dump_regd_exc_list(RTW_DBGDUMP, adapter_to_rfctl(Adapter));
-+			} else {
-+				if (parse_reg_exc_config(Adapter, szLine) == PARSE_RET_FAIL) {
-+					RTW_ERR("Fail to parse regulation exception ruls!\n");
-+					goto exit;
-+				}
-+				continue;
-+			}
-+		}
-+
-+		if (loadingStage == LD_STAGE_TAB_DEFINE) {
-+			/* read "##	2.4G, 20M, 1T, CCK" */
-+			if (szLine[0] != '#' || szLine[1] != '#')
-+				continue;
-+
-+			/* skip the space */
-+			i = 2;
-+			while (szLine[i] == ' ' || szLine[i] == '\t')
-+				++i;
-+
-+			szLine[--i] = ' '; /* return the space in front of the regulation info */
-+
-+			/* Parse the label of the table */
-+			_rtw_memset((void *) band, 0, 10);
-+			_rtw_memset((void *) bandwidth, 0, 10);
-+			_rtw_memset((void *) ntx, 0, 10);
-+			_rtw_memset((void *) rateSection, 0, 10);
-+			if (!ParseQualifiedString(szLine, &i, band, ' ', ',')) {
-+				RTW_ERR("Fail to parse band!\n");
-+				goto exit;
-+			}
-+			if (!ParseQualifiedString(szLine, &i, bandwidth, ' ', ',')) {
-+				RTW_ERR("Fail to parse bandwidth!\n");
-+				goto exit;
-+			}
-+			if (!ParseQualifiedString(szLine, &i, ntx, ' ', ',')) {
-+				RTW_ERR("Fail to parse ntx!\n");
-+				goto exit;
-+			}
-+			if (!ParseQualifiedString(szLine, &i, rateSection, ' ', ',')) {
-+				RTW_ERR("Fail to parse rate!\n");
-+				goto exit;
-+			}
-+
-+			loadingStage = LD_STAGE_TAB_START;
-+		} else if (loadingStage == LD_STAGE_TAB_START) {
-+			/* read "##	START" */
-+			if (szLine[0] != '#' || szLine[1] != '#')
-+				continue;
-+
-+			/* skip the space */
-+			i = 2;
-+			while (szLine[i] == ' ' || szLine[i] == '\t')
-+				++i;
-+
-+			if (strncmp((u8 *)(szLine + i), "START", 5)) {
-+				RTW_ERR("Missing \"##   START\" label\n");
-+				goto exit;
-+			}
-+
-+			loadingStage = LD_STAGE_COLUMN_DEFINE;
-+		} else if (loadingStage == LD_STAGE_COLUMN_DEFINE) {
-+			/* read "##	#5#	FCC	ETSI	MKK	IC	KCC" */
-+			if (szLine[0] != '#' || szLine[1] != '#')
-+				continue;
-+
-+			/* skip the space */
-+			i = 2;
-+			while (szLine[i] == ' ' || szLine[i] == '\t')
-+				++i;
-+
-+			_rtw_memset((void *) colNumBuf, 0, 10);
-+			if (!ParseQualifiedString(szLine, &i, colNumBuf, '#', '#')) {
-+				RTW_ERR("Fail to parse column number!\n");
-+				goto exit;
-+			}
-+			if (!GetU1ByteIntegerFromStringInDecimal(colNumBuf, &colNum)) {
-+				RTW_ERR("Column number \"%s\" is not unsigned decimal\n", colNumBuf);
-+				goto exit;
-+			}
-+			if (colNum == 0) {
-+				RTW_ERR("Column number is 0\n");
-+				goto exit;
-+			}
-+
-+			if (DBG_TXPWR_LMT_FILE_PARSE)
-+				RTW_PRINT("[%s][%s][%s][%s] column num:%d\n", band, bandwidth, rateSection, ntx, colNum);
-+
-+			regulation = (char **)rtw_zmalloc(sizeof(char *) * colNum);
-+			if (!regulation) {
-+				RTW_ERR("Regulation alloc fail\n");
-+				goto exit;
-+			}
-+
-+			for (forCnt = 0; forCnt < colNum; ++forCnt) {
-+				u32 i_ns;
-+
-+				/* skip the space */
-+				while (szLine[i] == ' ' || szLine[i] == '\t')
-+					i++;
-+				i_ns = i;
-+
-+				while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0')
-+					i++;
-+
-+				regulation[forCnt] = (char *)rtw_malloc(i - i_ns + 1);
-+				if (!regulation[forCnt]) {
-+					RTW_ERR("Regulation alloc fail\n");
-+					goto exit;
-+				}
-+
-+				_rtw_memcpy(regulation[forCnt], szLine + i_ns, i - i_ns);
-+				regulation[forCnt][i - i_ns] = '\0';
-+			}
-+
-+			if (DBG_TXPWR_LMT_FILE_PARSE) {
-+				RTW_PRINT("column name:");
-+				for (forCnt = 0; forCnt < colNum; ++forCnt)
-+					_RTW_PRINT(" %s", regulation[forCnt]);
-+				_RTW_PRINT("\n");
-+			}
-+
-+			loadingStage = LD_STAGE_CH_ROW;
-+		} else if (loadingStage == LD_STAGE_CH_ROW) {
-+			char	channel[10] = {0}, powerLimit[10] = {0};
-+			u8	cnt = 0;
-+
-+			/* the table ends */
-+			if (szLine[0] == '#' && szLine[1] == '#') {
-+				i = 2;
-+				while (szLine[i] == ' ' || szLine[i] == '\t')
-+					++i;
-+
-+				if (strncmp((u8 *)(szLine + i), "END", 3) == 0) {
-+					loadingStage = LD_STAGE_TAB_DEFINE;
-+					if (regulation) {
-+						for (forCnt = 0; forCnt < colNum; ++forCnt) {
-+							if (regulation[forCnt]) {
-+								rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1);
-+								regulation[forCnt] = NULL;
-+							}
-+						}
-+						rtw_mfree((u8 *)regulation, sizeof(char *) * colNum);
-+						regulation = NULL;
-+					}
-+					colNum = 0;
-+					continue;
-+				} else {
-+					RTW_ERR("Missing \"##   END\" label\n");
-+					goto exit;
-+				}
-+			}
-+
-+			if ((szLine[0] != 'c' && szLine[0] != 'C') ||
-+				(szLine[1] != 'h' && szLine[1] != 'H')
-+			) {
-+				RTW_WARN("Wrong channel prefix: '%c','%c'(%d,%d)\n", szLine[0], szLine[1], szLine[0], szLine[1]);
-+				continue;
-+			}
-+			i = 2;/* move to the  location behind 'h' */
-+
-+			/* load the channel number */
-+			cnt = 0;
-+			while (szLine[i] >= '0' && szLine[i] <= '9') {
-+				channel[cnt] = szLine[i];
-+				++cnt;
-+				++i;
-+			}
-+			/* RTW_INFO("chnl %s!\n", channel); */
-+
-+			for (forCnt = 0; forCnt < colNum; ++forCnt) {
-+				/* skip the space between channel number and the power limit value */
-+				while (szLine[i] == ' ' || szLine[i] == '\t')
-+					++i;
-+
-+				/* load the power limit value */
-+				_rtw_memset((void *) powerLimit, 0, 10);
-+
-+				if (szLine[i] == 'W' && szLine[i + 1] == 'W') {
-+					/*
-+					* case "WW" assign special ww value
-+					* means to get minimal limit in other regulations at same channel
-+					*/
-+					s8 ww_value = phy_txpwr_ww_lmt_value(Adapter);
-+
-+					sprintf(powerLimit, "%d", ww_value);
-+					i += 2;
-+
-+				} else if (szLine[i] == 'N' && szLine[i + 1] == 'A') {
-+					/*
-+					* case "NA" assign max txgi value
-+					* means no limitation
-+					*/
-+					sprintf(powerLimit, "%d", hal_spec->txgi_max);
-+					i += 2;
-+
-+				} else if ((szLine[i] >= '0' && szLine[i] <= '9') || szLine[i] == '.'
-+					|| szLine[i] == '+' || szLine[i] == '-'
-+				){
-+					/* case of dBm value */
-+					u8 integer = 0, fraction = 0, negative = 0;
-+					u32 u4bMove;
-+					s8 lmt = 0;
-+
-+					if (szLine[i] == '+' || szLine[i] == '-') {
-+						if (szLine[i] == '-')
-+							negative = 1;
-+						i++;
-+					}
-+
-+					if (GetFractionValueFromString(&szLine[i], &integer, &fraction, &u4bMove))
-+						i += u4bMove;
-+					else {
-+						RTW_ERR("Limit \"%s\" is not valid decimal\n", &szLine[i]);
-+						goto exit;
-+					}
-+
-+					/* transform to string of value in unit of txgi */
-+					lmt = integer * hal_spec->txgi_pdbm + ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100;
-+					if (negative)
-+						lmt = -lmt;
-+					sprintf(powerLimit, "%d", lmt);
-+
-+				} else {
-+					RTW_ERR("Wrong limit expression \"%c%c\"(%d, %d)\n"
-+						, szLine[i], szLine[i + 1], szLine[i], szLine[i + 1]);
-+					goto exit;
-+				}
-+
-+				/* store the power limit value */
-+				phy_set_tx_power_limit(pDM_Odm, (u8 *)regulation[forCnt], (u8 *)band,
-+					(u8 *)bandwidth, (u8 *)rateSection, (u8 *)ntx, (u8 *)channel, (u8 *)powerLimit);
-+
-+			}
-+		}
-+	}
-+
-+	rtStatus = _SUCCESS;
-+
-+exit:
-+	if (regulation) {
-+		for (forCnt = 0; forCnt < colNum; ++forCnt) {
-+			if (regulation[forCnt]) {
-+				rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1);
-+				regulation[forCnt] = NULL;
-+			}
-+		}
-+		rtw_mfree((u8 *)regulation, sizeof(char *) * colNum);
-+		regulation = NULL;
-+	}
-+
-+	RTW_INFO("%s return %d\n", __func__, rtStatus);
-+	return rtStatus;
-+}
-+
-+int
-+PHY_ConfigRFWithPowerLimitTableParaFile(
-+		PADAPTER	Adapter,
-+		const char	*pFileName
-+)
-+{
-+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
-+	int	rlen = 0, rtStatus = _FAIL;
-+
-+	if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_LMT_PARA_FILE))
-+		return rtStatus;
-+
-+	_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
-+
-+	if (pHalData->rf_tx_pwr_lmt == NULL) {
-+		rtw_get_phy_file_path(Adapter, pFileName);
-+		if (rtw_readable_file_sz_chk(rtw_phy_para_file_path, 
-+			MAX_PARA_FILE_BUF_LEN) == _TRUE) {
-+			rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
-+			if (rlen > 0) {
-+				rtStatus = _SUCCESS;
-+				pHalData->rf_tx_pwr_lmt = rtw_zvmalloc(rlen);
-+				if (pHalData->rf_tx_pwr_lmt) {
-+					_rtw_memcpy(pHalData->rf_tx_pwr_lmt, pHalData->para_file_buf, rlen);
-+					pHalData->rf_tx_pwr_lmt_len = rlen;
-+				} else
-+					RTW_INFO("%s rf_tx_pwr_lmt alloc fail !\n", __FUNCTION__);
-+			}
-+		}
-+	} else {
-+		if ((pHalData->rf_tx_pwr_lmt_len != 0) && (pHalData->rf_tx_pwr_lmt != NULL)) {
-+			_rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len);
-+			rtStatus = _SUCCESS;
-+		} else
-+			RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__);
-+	}
-+
-+	if (rtStatus == _SUCCESS) {
-+		/* RTW_INFO("%s(): read %s ok\n", __FUNCTION__, pFileName); */
-+		rtStatus = phy_ParsePowerLimitTableFile(Adapter, pHalData->para_file_buf);
-+	} else
-+		RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
-+
-+	return rtStatus;
-+}
-+#endif /* CONFIG_TXPWR_LIMIT */
-+
-+void phy_free_filebuf_mask(_adapter *padapter, u8 mask)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+
-+	if (pHalData->mac_reg && (mask & LOAD_MAC_PARA_FILE)) {
-+		rtw_vmfree(pHalData->mac_reg, pHalData->mac_reg_len);
-+		pHalData->mac_reg = NULL;
-+	}
-+	if (mask & LOAD_BB_PARA_FILE) {
-+		if (pHalData->bb_phy_reg) {
-+			rtw_vmfree(pHalData->bb_phy_reg, pHalData->bb_phy_reg_len);
-+			pHalData->bb_phy_reg = NULL;
-+		}
-+		if (pHalData->bb_agc_tab) {
-+			rtw_vmfree(pHalData->bb_agc_tab, pHalData->bb_agc_tab_len);
-+			pHalData->bb_agc_tab = NULL;
-+		}
-+	}
-+	if (pHalData->bb_phy_reg_pg && (mask & LOAD_BB_PG_PARA_FILE)) {
-+		rtw_vmfree(pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len);
-+		pHalData->bb_phy_reg_pg = NULL;
-+	}
-+	if (pHalData->bb_phy_reg_mp && (mask & LOAD_BB_MP_PARA_FILE)) {
-+		rtw_vmfree(pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len);
-+		pHalData->bb_phy_reg_mp = NULL;
-+	}
-+	if (mask & LOAD_RF_PARA_FILE) {
-+		if (pHalData->rf_radio_a) {
-+			rtw_vmfree(pHalData->rf_radio_a, pHalData->rf_radio_a_len);
-+			pHalData->rf_radio_a = NULL;
-+		}
-+		if (pHalData->rf_radio_b) {
-+			rtw_vmfree(pHalData->rf_radio_b, pHalData->rf_radio_b_len);
-+			pHalData->rf_radio_b = NULL;
-+		}
-+	}
-+	if (pHalData->rf_tx_pwr_track && (mask & LOAD_RF_TXPWR_TRACK_PARA_FILE)) {
-+		rtw_vmfree(pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len);
-+		pHalData->rf_tx_pwr_track = NULL;
-+	}
-+	if (pHalData->rf_tx_pwr_lmt && (mask & LOAD_RF_TXPWR_LMT_PARA_FILE)) {
-+		rtw_vmfree(pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len);
-+		pHalData->rf_tx_pwr_lmt = NULL;
-+	}
-+}
-+
-+inline void phy_free_filebuf(_adapter *padapter)
-+{
-+	phy_free_filebuf_mask(padapter, 0xFF);
-+}
-+
-+#endif
-+
-+/*
-+* TX power limit of regulatory without HAL consideration
-+* Return value in unit of TX Gain Index
-+* hal_spec.txgi_max means unspecified
-+*/
-+s8 phy_get_txpwr_regd_lmt(_adapter *adapter, struct hal_spec_t *hal_spec, u8 cch, enum channel_width bw, u8 ntx_idx)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	s16 total_mbm = UNSPECIFIED_MBM;
-+	s8 lmt;
-+
-+	if ((adapter->registrypriv.RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory != 1) ||
-+		adapter->registrypriv.RegEnableTxPowerLimit == 0)
-+		goto exit;
-+
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+	if (rfctl->regd_src == REGD_SRC_OS)
-+		total_mbm = rtw_os_get_total_txpwr_regd_lmt_mbm(adapter, cch, bw);
-+#endif
-+
-+exit:
-+	if (total_mbm != UNSPECIFIED_MBM)
-+		lmt = (total_mbm - mb_of_ntx(ntx_idx + 1) - rfctl->antenna_gain) * hal_spec->txgi_pdbm / MBM_PDBM;
-+	else
-+		lmt = hal_spec->txgi_max;
-+
-+	return lmt;
-+}
-+
-+/*
-+* check if user specified mbm is valid
-+*/
-+bool phy_is_txpwr_user_mbm_valid(_adapter *adapter, s16 mbm)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+
-+	/* 1T upper bound check */
-+	if (hal_spec->txgi_max <= mbm * hal_spec->txgi_pdbm / MBM_PDBM)
-+		return 0;
-+
-+	return 1;
-+}
-+
-+bool phy_is_txpwr_user_target_specified(_adapter *adapter)
-+{
-+	s16 total_mbm = UNSPECIFIED_MBM;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	total_mbm = rtw_cfg80211_dev_get_total_txpwr_target_mbm(adapter_to_dvobj(adapter));
-+#endif
-+
-+	return total_mbm != UNSPECIFIED_MBM;
-+}
-+
-+/*
-+* Return value in unit of TX Gain Index
-+* hal_spec.txgi_max means unspecified
-+*/
-+s8 phy_get_txpwr_user_target(_adapter *adapter, struct hal_spec_t *hal_spec, u8 ntx_idx)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	s16 total_mbm = UNSPECIFIED_MBM;
-+	s8 target;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	total_mbm = rtw_cfg80211_dev_get_total_txpwr_target_mbm(adapter_to_dvobj(adapter));
-+#endif
-+	if (total_mbm != UNSPECIFIED_MBM)
-+		target = (total_mbm - mb_of_ntx(ntx_idx + 1) - rfctl->antenna_gain) * hal_spec->txgi_pdbm / MBM_PDBM;
-+	else
-+		target = hal_spec->txgi_max;
-+
-+	return target;
-+}
-+
-+/*
-+* Return value in unit of TX Gain Index
-+* hal_spec.txgi_max means unspecified
-+*/
-+s8 phy_get_txpwr_user_lmt(_adapter *adapter, struct hal_spec_t *hal_spec, u8 ntx_idx)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	s16 total_mbm = UNSPECIFIED_MBM;
-+	s8 lmt;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	total_mbm = rtw_cfg80211_dev_get_total_txpwr_lmt_mbm(adapter_to_dvobj(adapter));
-+#endif
-+	if (total_mbm != UNSPECIFIED_MBM)
-+		lmt = (total_mbm - mb_of_ntx(ntx_idx + 1) - rfctl->antenna_gain) * hal_spec->txgi_pdbm / MBM_PDBM;
-+	else
-+		lmt = hal_spec->txgi_max;
-+
-+	return lmt;
-+}
-+
-+/*
-+* Return value in unit of TX Gain Index
-+* 0 means unspecified
-+*/
-+s8 phy_get_txpwr_tpc(_adapter *adapter, struct hal_spec_t *hal_spec)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	u16 cnst = 0;
-+
-+	if (rfctl->tpc_mode == TPC_MODE_MANUAL)
-+		cnst = rfctl->tpc_manual_constraint * hal_spec->txgi_pdbm / MBM_PDBM;
-+
-+	return -cnst;
-+}
-+
-+void dump_txpwr_tpc_settings(void *sel, _adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	if (rfctl->tpc_mode == TPC_MODE_DISABLE)
-+		RTW_PRINT_SEL(sel, "mode:DISABLE(%d)\n", rfctl->tpc_mode);
-+	else if (rfctl->tpc_mode == TPC_MODE_MANUAL) {
-+		RTW_PRINT_SEL(sel, "mode:MANUAL(%d)\n", rfctl->tpc_mode);
-+		RTW_PRINT_SEL(sel, "constraint:%d (mB)\n", rfctl->tpc_manual_constraint);
-+	}
-+}
-+
-+void dump_txpwr_antenna_gain(void *sel, _adapter *adapter)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	RTW_PRINT_SEL(sel, "%d (mBi)\n", rfctl->antenna_gain);
-+}
-+
-+/*
-+* Return value in unit of TX Gain Index
-+*/
-+s8 phy_get_txpwr_target(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate, u8 ntx_idx
-+	, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch, bool reg_max, struct txpwr_idx_comp *tic)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	s8 target, by_rate = 0, btc_diff = 0, extra = 0;
-+	s8 lmt, rlmt, utgt, ulmt;
-+	s8 tpc = 0;
-+
-+	rlmt = lmt = utgt = ulmt = hal_spec->txgi_max;
-+
-+	if (band != BAND_ON_2_4G && IS_CCK_RATE(rate))
-+		goto exit;
-+
-+	if (!reg_max) {
-+		utgt = phy_get_txpwr_user_target(adapter, hal_spec, ntx_idx);
-+		if (utgt != hal_spec->txgi_max)
-+			goto get_lmt;
-+	}
-+
-+#ifdef CONFIG_RTL8812A
-+	if (IS_HARDWARE_TYPE_8812(adapter)
-+		&& phy_get_txpwr_target_skip_by_rate_8812a(adapter, rate))
-+		by_rate = phy_get_target_txpwr(adapter, band, rfpath, rs);
-+	else
-+#endif
-+		by_rate = phy_get_txpwr_by_rate(adapter, band, rfpath, rs, rate);
-+	if (by_rate == hal_spec->txgi_max)
-+		by_rate = 0;
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if (!reg_max) {
-+		if (hal_data->EEPROMBluetoothCoexist == _TRUE)
-+			btc_diff = -(rtw_btcoex_query_reduced_wl_pwr_lvl(adapter) * hal_spec->txgi_pdbm);
-+	}
-+#endif
-+
-+	extra = rtw_hal_get_txpwr_target_extra_bias(adapter, rfpath, rs, rate, bw, band, cch);
-+
-+get_lmt:
-+	rlmt = phy_get_txpwr_regd_lmt(adapter, hal_spec, cch, bw, ntx_idx);
-+	lmt = phy_get_txpwr_lmt_sub_chs(adapter, NULL, band, bw, rfpath, rate, ntx_idx, cch, opch, reg_max);
-+	if (!reg_max)
-+		ulmt = phy_get_txpwr_user_lmt(adapter, hal_spec, ntx_idx);
-+	/* TODO: limit from outer source, ex: 11d */
-+
-+	if (!reg_max)
-+		tpc = phy_get_txpwr_tpc(adapter, hal_spec);
-+
-+exit:
-+	if (utgt != hal_spec->txgi_max)
-+		target = utgt;
-+	else
-+		target = by_rate + btc_diff + extra;
-+
-+	if (target > rlmt)
-+		target = rlmt;
-+	if (target > lmt)
-+		target = lmt;
-+	if (target > ulmt)
-+		target = ulmt;
-+
-+	target += tpc;
-+
-+	if (tic) {
-+		tic->target = target;
-+		if (utgt == hal_spec->txgi_max) {
-+			tic->by_rate = by_rate;
-+			tic->btc = btc_diff;
-+			tic->extra = extra;
-+		}
-+		tic->utarget = utgt;
-+		tic->rlimit = rlmt;
-+		tic->limit = lmt;
-+		tic->ulimit = ulmt;
-+		tic->tpc = tpc;
-+	}
-+
-+	return target;
-+}
-+
-+/* TODO: common dpd_diff getting API from phydm */
-+#ifdef CONFIG_RTL8822C
-+#include "./rtl8822c/rtl8822c.h"
-+#endif
-+
-+/*
-+* Return in unit of TX Gain Index
-+*/
-+s8 phy_get_txpwr_amends(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate, u8 ntx_idx
-+	, enum channel_width bw, BAND_TYPE band, u8 cch, struct txpwr_idx_comp *tic)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	s8 tpt_diff = 0, dpd_diff = 0, val = 0;
-+
-+	if (band != BAND_ON_2_4G && IS_CCK_RATE(rate))
-+		goto exit;
-+
-+	if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8188GTV(adapter)
-+		|| IS_HARDWARE_TYPE_8192E(adapter) || IS_HARDWARE_TYPE_8192F(adapter)
-+		|| IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8703B(adapter) || IS_HARDWARE_TYPE_8723D(adapter)
-+		|| IS_HARDWARE_TYPE_8710B(adapter)
-+		|| IS_HARDWARE_TYPE_8821(adapter) || IS_HARDWARE_TYPE_8812(adapter)
-+	)
-+		tpt_diff = PHY_GetTxPowerTrackingOffset(adapter, rfpath, rate);
-+
-+#ifdef CONFIG_RTL8822C
-+	if (IS_HARDWARE_TYPE_8822C(adapter))
-+		dpd_diff = -(rtl8822c_get_dis_dpd_by_rate_diff(adapter, rate) * hal_spec->txgi_pdbm);
-+#endif
-+
-+exit:
-+	if (tic) {
-+		tic->tpt = tpt_diff;
-+		tic->dpd = dpd_diff;
-+	}
-+
-+	return tpt_diff + dpd_diff;
-+}
-+
-+#ifdef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
-+s8 phy_get_tssi_txpwr_by_rate_ref(_adapter *adapter, enum rf_path path
-+	, enum channel_width bw, u8 cch, u8 opch)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u8 ntx_idx = phy_get_current_tx_num(adapter, MGN_MCS7);
-+	BAND_TYPE band = cch > 14 ? BAND_ON_5G : BAND_ON_2_4G;
-+	s8 pwr_idx;
-+
-+	pwr_idx = phy_get_txpwr_target(adapter, path, HT_1SS, MGN_MCS7
-+		, ntx_idx, bw, band, cch, opch, 0, NULL);
-+	pwr_idx += phy_get_txpwr_amends(adapter, path, HT_1SS, MGN_MCS7
-+		, ntx_idx, bw, band, cch, NULL);
-+
-+	return pwr_idx;
-+}
-+#endif
-+
-+/*
-+ * Rteurn tx power index for rate
-+ */
-+u8 hal_com_get_txpwr_idx(_adapter *adapter, enum rf_path rfpath
-+	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
-+	, struct txpwr_idx_comp *tic)
-+{
-+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	s16 power_idx = 0;
-+	s8 base = 0;
-+	s8 rate_target, rate_amends;
-+	u8 ntx_idx = phy_get_current_tx_num(adapter, rate);
-+
-+	/* target */
-+	rate_target = phy_get_txpwr_target(adapter, rfpath, rs, rate, ntx_idx, bw, band, cch, opch, 0, tic);
-+
-+	/* amends */
-+	rate_amends = phy_get_txpwr_amends(adapter, rfpath, rs, rate, ntx_idx, bw, band, cch, tic);
-+
-+	switch (hal->txpwr_pg_mode) {
-+#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	case TXPWR_PG_WITH_PWR_IDX: {
-+		/*
-+		* power index = 
-+		* 1. pg base (per rate section) +
-+		* 2. target diff (per rate) to target of its rate section +
-+		* 3. amends diff (per rate)
-+		*/
-+		u8 rs_target;
-+
-+		base = phy_get_pg_txpwr_idx(adapter, rfpath, rs, ntx_idx, bw, band, cch);
-+		rs_target = phy_get_target_txpwr(adapter, band, rfpath, rs);
-+		power_idx = base + (rate_target - rs_target) + (rate_amends);
-+
-+		if (tic) {
-+			if (tic->utarget == hal_spec->txgi_max)
-+				tic->by_rate -= rs_target;
-+			else
-+				tic->utarget -= rs_target;
-+			if (tic->rlimit != hal_spec->txgi_max)
-+				tic->rlimit -= rs_target;
-+			if (tic->limit != hal_spec->txgi_max)
-+				tic->limit -= rs_target;
-+			if (tic->ulimit != hal_spec->txgi_max)
-+				tic->ulimit -= rs_target;
-+		}
-+	}
-+		break;
-+#endif
-+#ifdef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
-+	case TXPWR_PG_WITH_TSSI_OFFSET: {
-+		/*
-+		* power index = 
-+		* 1. base (fixed) +
-+		* 2. target (per rate) +
-+		* 3. amends diff (per rate)
-+		* base is selected that power index of MCS7 ==  halrf_get_tssi_codeword_for_txindex()
-+		*/
-+		s8 mcs7_idx;
-+
-+		mcs7_idx = phy_get_tssi_txpwr_by_rate_ref(adapter, rfpath, bw, cch, opch);
-+		base = halrf_get_tssi_codeword_for_txindex(adapter_to_phydm(adapter)) - mcs7_idx;
-+		power_idx = base + rate_target + rate_amends;
-+	}
-+		break;
-+#endif
-+	}
-+
-+	if (tic) {
-+		tic->ntx_idx = ntx_idx;
-+		tic->base = base;
-+	}
-+
-+	if (power_idx < 0)
-+		power_idx = 0;
-+	else if (power_idx > hal_spec->txgi_max)
-+		power_idx = hal_spec->txgi_max;
-+
-+#if defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8812A)
-+	if ((IS_HARDWARE_TYPE_8821(adapter) || IS_HARDWARE_TYPE_8812(adapter))
-+		&& power_idx % 2 == 1 && !IS_NORMAL_CHIP(hal->version_id))
-+		--power_idx;
-+#endif
-+
-+	return power_idx;
-+}
-+
-+static s16 phy_get_txpwr_mbm(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate
-+	, enum channel_width bw, u8 cch, u8 opch, bool total, bool reg_max, bool eirp, struct txpwr_idx_comp *tic)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	BAND_TYPE band = cch <= 14 ? BAND_ON_2_4G : BAND_ON_5G;
-+	u8 ntx_idx_max, ntx_idx, i;
-+	s16 val, max = UNSPECIFIED_MBM;
-+
-+	if (reg_max) {
-+		ntx_idx_max = phy_get_capable_tx_num(adapter, rate);
-+		ntx_idx = rate_section_to_tx_num(rs);
-+		if (ntx_idx > ntx_idx_max) {
-+			rtw_warn_on(1);
-+			return 0;
-+		}
-+	} else
-+		ntx_idx_max = ntx_idx = phy_get_current_tx_num(adapter, rate);
-+
-+	for (i = 0; ntx_idx + i <= ntx_idx_max; i++) {
-+		val = phy_get_txpwr_target(adapter, rfpath, rs, rate, ntx_idx, bw, band, cch, opch, reg_max, tic);
-+		val = (val * MBM_PDBM) / hal_spec->txgi_pdbm;
-+		if (total)
-+			val += mb_of_ntx(ntx_idx + 1);
-+		if (eirp)
-+			val += rfctl->antenna_gain;
-+
-+		if (max == UNSPECIFIED_MBM || max < val)
-+			max = val;
-+	}
-+
-+	if (tic)
-+		tic->ntx_idx = ntx_idx;
-+
-+	if (max == UNSPECIFIED_MBM) {
-+		rtw_warn_on(1);
-+		max = 0;
-+	}
-+	return max;
-+}
-+
-+/* get txpowr in mBm for single path */
-+s16 phy_get_txpwr_single_mbm(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate
-+	, enum channel_width bw, u8 cch, u8 opch, bool reg_max, bool eirp, struct txpwr_idx_comp *tic)
-+{
-+	return phy_get_txpwr_mbm(adapter, rfpath, rs, rate, bw, cch, opch, 0, reg_max, eirp, tic);
-+}
-+
-+/* get txpowr in mBm with effect of N-TX */
-+s16 phy_get_txpwr_total_mbm(_adapter *adapter, RATE_SECTION rs, u8 rate
-+	, enum channel_width bw, u8 cch, u8 opch, bool reg_max, bool eirp, struct txpwr_idx_comp *tic)
-+{
-+	/* assume all path have same txpower target */
-+	return phy_get_txpwr_mbm(adapter, RF_PATH_A, rs, rate, bw, cch, opch, 1, reg_max, eirp, tic);
-+}
-+
-+static s16 _phy_get_txpwr_max_mbm(_adapter *adapter, s8 rfpath
-+	, enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht, bool reg_max, bool eirp)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	BAND_TYPE band = cch <= 14 ? BAND_ON_2_4G : BAND_ON_5G;
-+	u8 tx_num;
-+	RATE_SECTION rs;
-+	u8 hw_rate;
-+	int i;
-+	s16 max = UNSPECIFIED_MBM, mbm;
-+
-+	if (0)
-+		RTW_INFO("cck_ofdm:0x%04x, ht:0x%08x, vht:0x%016llx\n", bmp_cck_ofdm, bmp_ht, bmp_vht);
-+
-+	for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
-+		tx_num = rate_section_to_tx_num(rs);
-+		if (tx_num + 1 > hal_data->tx_nss)
-+			continue;
-+		
-+		if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
-+			continue;
-+		
-+		if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_ALL(adapter))
-+			continue;
-+		
-+		for (i = 0; i < rates_by_sections[rs].rate_num; i++) {
-+			hw_rate = MRateToHwRate(rates_by_sections[rs].rates[i]);
-+			if (IS_LEGACY_HRATE(hw_rate)) {
-+				if (!(bmp_cck_ofdm & BIT(hw_rate)))
-+					continue;
-+			} else if (IS_HT_HRATE(hw_rate)) {
-+				if (!(bmp_ht & BIT(hw_rate - DESC_RATEMCS0)))
-+					continue;
-+			} else if (IS_VHT_HRATE(hw_rate)) {
-+				if (!(bmp_vht & BIT(hw_rate - DESC_RATEVHTSS1MCS0)))
-+					continue;
-+			}
-+
-+			if (rfpath < 0) /* total */
-+				mbm = phy_get_txpwr_total_mbm(adapter, rs, rates_by_sections[rs].rates[i], bw, cch, opch, reg_max, eirp, NULL);
-+			else
-+				mbm = phy_get_txpwr_single_mbm(adapter, rfpath, rs, rates_by_sections[rs].rates[i], bw, cch, opch, reg_max, eirp, NULL);
-+
-+			if (max == UNSPECIFIED_MBM || mbm > max)
-+				max = mbm;
-+		}
-+	}
-+
-+	return max;
-+}
-+
-+s16 phy_get_txpwr_single_max_mbm(_adapter *adapter, u8 rfpath
-+	, enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht, bool reg_max, bool eirp)
-+{
-+	return _phy_get_txpwr_max_mbm(adapter, rfpath, bw, cch, opch, bmp_cck_ofdm, bmp_ht, bmp_vht, reg_max, eirp);
-+}
-+
-+s16 phy_get_txpwr_total_max_mbm(_adapter *adapter
-+	, enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht, bool reg_max, bool eirp)
-+{
-+	return _phy_get_txpwr_max_mbm(adapter, -1, bw, cch, opch, bmp_cck_ofdm, bmp_ht, bmp_vht, reg_max, eirp);
-+}
-+
-+s8
-+phy_get_tx_power_final_absolute_value(_adapter *adapter, u8 rfpath, u8 rate,
-+				      enum channel_width bw, u8 cch)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	RATE_SECTION rs = mgn_rate_to_rs(rate);
-+	BAND_TYPE band = cch <= 14 ? BAND_ON_2_4G : BAND_ON_5G;
-+	s8 val;
-+
-+	val = phy_get_txpwr_target(adapter, rfpath
-+		, rs, rate, phy_get_current_tx_num(adapter, rate), bw, band, cch, 0, 0, NULL);
-+
-+	val /= hal_spec->txgi_pdbm;
-+
-+	return val;
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/hal_dm.c b/drivers/staging/rtl8723cs/hal/hal_dm.c
-new file mode 100644
-index 000000000000..b42235a179dd
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_dm.c
-@@ -0,0 +1,1937 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2014 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+/* A mapping from HalData to ODM. */
-+enum odm_board_type boardType(u8 InterfaceSel)
-+{
-+	enum odm_board_type        board	= ODM_BOARD_DEFAULT;
-+
-+#ifdef CONFIG_PCI_HCI
-+	INTERFACE_SELECT_PCIE   pcie	= (INTERFACE_SELECT_PCIE)InterfaceSel;
-+	switch (pcie) {
-+	case INTF_SEL0_SOLO_MINICARD:
-+		board |= ODM_BOARD_MINICARD;
-+		break;
-+	case INTF_SEL1_BT_COMBO_MINICARD:
-+		board |= ODM_BOARD_BT;
-+		board |= ODM_BOARD_MINICARD;
-+		break;
-+	default:
-+		board = ODM_BOARD_DEFAULT;
-+		break;
-+	}
-+
-+#elif defined(CONFIG_USB_HCI)
-+	INTERFACE_SELECT_USB    usb	= (INTERFACE_SELECT_USB)InterfaceSel;
-+	switch (usb) {
-+	case INTF_SEL1_USB_High_Power:
-+		board |= ODM_BOARD_EXT_LNA;
-+		board |= ODM_BOARD_EXT_PA;
-+		break;
-+	case INTF_SEL2_MINICARD:
-+		board |= ODM_BOARD_MINICARD;
-+		break;
-+	case INTF_SEL4_USB_Combo:
-+		board |= ODM_BOARD_BT;
-+		break;
-+	case INTF_SEL5_USB_Combo_MF:
-+		board |= ODM_BOARD_BT;
-+		break;
-+	case INTF_SEL0_USB:
-+	case INTF_SEL3_USB_Solo:
-+	default:
-+		board = ODM_BOARD_DEFAULT;
-+		break;
-+	}
-+
-+#endif
-+	/* RTW_INFO("===> boardType(): (pHalData->InterfaceSel, pDM_Odm->BoardType) = (%d, %d)\n", InterfaceSel, board); */
-+
-+	return board;
-+}
-+
-+void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter)
-+{
-+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
-+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
-+
-+	if (hal->RegIQKFWOffload) {
-+		rtw_sctx_init(&hal->iqk_sctx, 0);
-+		phydm_fwoffload_ability_init(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
-+	} else
-+		phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
-+
-+	RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload ? "enable" : "disable");
-+
-+	if (rtw_mi_check_status(adapter, MI_LINKED)) {
-+		#ifdef CONFIG_LPS
-+		LPS_Leave(adapter, "SWITCH_IQK_OFFLOAD");
-+		#endif
-+		halrf_iqk_trigger(p_dm_odm, _FALSE);
-+	}
-+}
-+
-+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1) \
-+	|| (RTL8723F_SUPPORT == 1))
-+void rtw_phydm_iqk_trigger(_adapter *adapter)
-+{
-+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
-+	u8 clear = _TRUE;
-+	u8 segment = _FALSE;
-+	u8 rfk_forbidden = _FALSE;
-+
-+	halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
-+#if (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8723F_SUPPORT == 1)
-+	/* halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); to do */
-+	halrf_rf_k_connect_trigger(p_dm_odm, _TRUE, SEGMENT_FREE);
-+#else
-+	/*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
-+	halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
-+	halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
-+#endif
-+}
-+#endif
-+
-+void rtw_phydm_iqk_trigger_all(_adapter *adapter)
-+{
-+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
-+	u8 clear = _TRUE;
-+	u8 segment = _FALSE;
-+	u8 rfk_forbidden = _FALSE;
-+
-+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1) \
-+	|| (RTL8723F_SUPPORT == 1))
-+	halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
-+#if (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8723F_SUPPORT == 1)
-+	/* halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); to do */
-+	halrf_rf_k_connect_trigger(p_dm_odm, _TRUE, SEGMENT_FREE);
-+#else
-+	/*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
-+	halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
-+	halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
-+#endif /* (RTL8822C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) (RTL8723F_SUPPORT == 1) */
-+#else
-+	halrf_iqk_trigger(p_dm_odm, _FALSE);
-+#endif /* ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
-+			(RTL8723F_SUPPORT == 1) */
-+}
-+
-+void rtw_phydm_iqk_trigger_dbg(_adapter *adapter, bool recovery, bool clear, bool segment)
-+{
-+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
-+
-+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
-+		halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
-+#else
-+		halrf_iqk_trigger(p_dm_odm, recovery);
-+#endif
-+}
-+void rtw_phydm_lck_trigger(_adapter *adapter)
-+{
-+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
-+
-+	halrf_lck_trigger(p_dm_odm);
-+}
-+
-+void rtw_hal_phydm_cal_trigger(_adapter *adapter)
-+{
-+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
-+
-+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
-+	LeaveAllPowerSaveModeDirect(adapter);
-+
-+	rtw_phydm_iqk_trigger_all(adapter);
-+
-+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
-+}
-+
-+#ifdef CONFIG_DBG_RF_CAL
-+void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment)
-+{
-+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
-+
-+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
-+	LeaveAllPowerSaveModeDirect(adapter);
-+
-+	rtw_phydm_ability_backup(adapter);
-+	rtw_phydm_func_disable_all(adapter);
-+
-+	halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_IQK);
-+
-+	rtw_phydm_iqk_trigger_dbg(adapter, recovery, clear, segment);
-+	rtw_phydm_ability_restore(adapter);
-+
-+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
-+}
-+
-+void rtw_hal_lck_test(_adapter *adapter)
-+{
-+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
-+
-+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
-+	LeaveAllPowerSaveModeDirect(adapter);
-+
-+	rtw_phydm_ability_backup(adapter);
-+	rtw_phydm_func_disable_all(adapter);
-+
-+	halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_LCK);
-+
-+	rtw_phydm_lck_trigger(adapter);
-+
-+	rtw_phydm_ability_restore(adapter);
-+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
-+}
-+#endif
-+
-+#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
-+void rtw_hal_update_param_init_fw_offload_cap(_adapter *adapter)
-+{
-+	struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
-+
-+	if (adapter->registrypriv.fw_param_init)
-+		phydm_fwoffload_ability_init(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
-+	else
-+		phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
-+
-+	RTW_INFO("Init-Parameter FW offload:%s\n", adapter->registrypriv.fw_param_init ? "enable" : "disable");
-+}
-+#endif
-+
-+void record_ra_info(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask)
-+{
-+	struct dm_struct *p_dm = (struct dm_struct *)p_dm_void;
-+	_adapter *adapter = p_dm->adapter;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+
-+	if (p_sta) {
-+		rtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode);
-+		rtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable);
-+		rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask);
-+		rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32);
-+
-+		rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
-+	}
-+}
-+
-+#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
-+void rtw_phydm_fill_desc_dpt(void *dm, u8 *desc, u8 dpt_lv)
-+{
-+	struct dm_struct *p_dm = (struct dm_struct *)dm;
-+	_adapter *adapter = p_dm->adapter;
-+
-+	switch (rtw_get_chip_type(adapter)) {
-+/*
-+	#ifdef CONFIG_RTL8188F
-+	case RTL8188F:
-+		break;
-+	#endif
-+
-+	#ifdef CONFIG_RTL8723B
-+	case RTL8723B :
-+		break;
-+	#endif
-+
-+	#ifdef CONFIG_RTL8703B
-+	case RTL8703B :
-+		break;
-+	#endif
-+
-+	#ifdef CONFIG_RTL8812A
-+	case RTL8812 :
-+		break;
-+	#endif
-+
-+	#ifdef CONFIG_RTL8821A
-+	case RTL8821:
-+		break;
-+	#endif
-+
-+	#ifdef CONFIG_RTL8814A
-+	case RTL8814A :
-+		break;
-+	#endif
-+
-+	#ifdef CONFIG_RTL8192F
-+	case RTL8192F :
-+		break;
-+	#endif
-+*/
-+/*
-+	#ifdef CONFIG_RTL8192E
-+	case RTL8192E :
-+		SET_TX_DESC_TX_POWER_0_PSET_92E(desc, dpt_lv);
-+		break;
-+	#endif
-+*/
-+	#ifdef CONFIG_RTL8822B
-+	case RTL8822B :
-+		SET_TX_DESC_TXPWR_OFSET_8822B(desc, dpt_lv);
-+	break;
-+	#endif
-+
-+	#ifdef CONFIG_RTL8821C
-+	case RTL8821C :
-+		SET_TX_DESC_TXPWR_OFSET_8821C(desc, dpt_lv);
-+	break;
-+	#endif
-+
-+	default :
-+		RTW_ERR("%s IC not support dynamic tx power\n", __func__);
-+		break;
-+	}
-+}
-+void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id)
-+{
-+	struct dm_struct *dm = adapter_to_phydm(adapter);
-+
-+	odm_set_dyntxpwr(dm, desc, mac_id);
-+}
-+#endif
-+
-+#ifdef CONFIG_TDMADIG
-+void rtw_phydm_tdmadig(_adapter *adapter, u8 state)
-+{
-+	struct registry_priv	*pregistrypriv = &adapter->registrypriv;
-+	struct mlme_priv		*pmlmepriv = &(adapter->mlmepriv);
-+	struct dm_struct *dm = adapter_to_phydm(adapter);
-+	u8 tdma_dig_en;
-+
-+	switch (state) {
-+	case TDMADIG_INIT:
-+		phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, pregistrypriv->tdmadig_en);
-+		phydm_tdma_dig_para_upd(dm, MODE_DECISION, pregistrypriv->tdmadig_mode);
-+		break;
-+	case TDMADIG_NON_INIT:
-+		if(pregistrypriv->tdmadig_dynamic) {
-+			if(pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)
-+				tdma_dig_en = 0;
-+			else
-+				tdma_dig_en = pregistrypriv->tdmadig_en;
-+			phydm_tdma_dig_para_upd(dm, ENABLE_TDMA, tdma_dig_en);
-+		}
-+		break;
-+	default:
-+		break;
-+
-+	}
-+}
-+#endif/*CONFIG_TDMADIG*/
-+void rtw_phydm_ops_func_init(struct dm_struct *p_phydm)
-+{
-+	struct ra_table *p_ra_t = &p_phydm->dm_ra_table;
-+
-+	p_ra_t->record_ra_info = record_ra_info;
-+	#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
-+	p_phydm->fill_desc_dyntxpwr = rtw_phydm_fill_desc_dpt;
-+	#endif
-+}
-+void rtw_phydm_priv_init(_adapter *adapter)
-+{
-+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
-+	struct dm_struct *phydm = &(hal->odmpriv);
-+
-+	phydm->adapter = adapter;
-+	odm_cmn_info_init(phydm, ODM_CMNINFO_PLATFORM, ODM_CE);
-+}
-+
-+void Init_ODM_ComInfo(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
-+	struct dm_struct	*pDM_Odm = &(pHalData->odmpriv);
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
-+	int i;
-+
-+	/*phydm_op_mode could be change for different scenarios: ex: SoftAP - PHYDM_BALANCE_MODE*/
-+	pHalData->phydm_op_mode = PHYDM_PERFORMANCE_MODE;/*Service one device*/
-+	rtw_odm_init_ic_type(adapter);
-+
-+	if (rtw_get_intf_type(adapter) == RTW_GSPI)
-+		odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO);
-+	else
-+		odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter));
-+
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->version_id));
-+
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID);
-+
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec);
-+
-+#ifdef CONFIG_ADVANCE_OTA
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ADVANCE_OTA, adapter->registrypriv.adv_ota);
-+#endif
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, pHalData->rf_type);
-+
-+	{
-+		/* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */
-+		u8 odm_board_type = ODM_BOARD_DEFAULT;
-+
-+		if (pHalData->ExternalLNA_2G != 0) {
-+			odm_board_type |= ODM_BOARD_EXT_LNA;
-+			odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1);
-+		}
-+		if (pHalData->external_lna_5g != 0) {
-+			odm_board_type |= ODM_BOARD_EXT_LNA_5G;
-+			odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1);
-+		}
-+		if (pHalData->ExternalPA_2G != 0) {
-+			odm_board_type |= ODM_BOARD_EXT_PA;
-+			odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_PA, 1);
-+		}
-+		if (pHalData->external_pa_5g != 0) {
-+			odm_board_type |= ODM_BOARD_EXT_PA_5G;
-+			odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1);
-+		}
-+		if (pHalData->EEPROMBluetoothCoexist)
-+			odm_board_type |= ODM_BOARD_BT;
-+
-+		odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type);
-+		/* 1 ============== End of BoardType ============== */
-+	}
-+
-+	rtw_hal_set_odm_var(adapter, HAL_ODM_REGULATION, NULL, _TRUE);
-+
-+#ifdef CONFIG_DFS_MASTER
-+	rtw_odm_update_dfs_region(dvobj);
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->radar_detect_enabled));
-+#endif
-+
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA);
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA);
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA);
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA);
-+
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type);
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_X_CAP_SETTING, pHalData->crystal_cap);
-+
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0);
-+
-+	/*Add by YuChen for kfree init*/
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable);
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable);
-+
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant);
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch);
-+
-+	/* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D7, pHalData->efuse0x3d7);
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D8, pHalData->efuse0x3d8);
-+
-+	/* waiting for PhyDMV034 support*/
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MANUAL_SUPPORTABILITY, &(adapter->registrypriv.phydm_ability)); 
-+	/*Add by YuChen for adaptivity init*/
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en));
-+	phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE);
-+	phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini);
-+	phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff);
-+
-+	/*halrf info init*/
-+	halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_EEPROM_THERMAL_VALUE, pHalData->eeprom_thermal_meter);
-+	halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_PWT_TYPE, 0);
-+	halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_MP_POWER_TRACKING_TYPE, pHalData->txpwr_pg_mode);
-+
-+	if (rtw_odm_adaptivity_needed(adapter) == _TRUE)
-+		rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter);
-+
-+#ifdef CONFIG_IQK_PA_OFF
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1);
-+#endif
-+	rtw_hal_update_iqk_fw_offload_cap(adapter);
-+	#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
-+	rtw_hal_update_param_init_fw_offload_cap(adapter);
-+	#endif
-+
-+	/* Pointer reference */
-+	/*Antenna diversity relative parameters*/
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg));
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode));
-+
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BB_OPERATION_MODE, &(pHalData->phydm_op_mode));
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes));
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes));
-+
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type));
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate));
-+
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC));
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm));
-+#ifdef CONFIG_NARROWBAND_SUPPORTING
-+	if ((adapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_10)
-+		|| (adapter->registrypriv.rtw_nb_config == RTW_NB_CONFIG_WIDTH_5)) {
-+		odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(adapter->registrypriv.rtw_nb_config));
-+	}
-+	else
-+#endif
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw));
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel));
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed));
-+
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pHalData->bScanInProcess));
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving));
-+	/*Add by Yuchen for phydm beamforming*/
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp));
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp));
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test));
-+#ifdef CONFIG_RTL8723B
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_IS1ANTENNA, &pHalData->EEPROMBluetoothAntNum);
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RFDEFAULTPATH, &pHalData->ant_path);
-+#endif /*CONFIG_RTL8723B*/
-+#ifdef CONFIG_USB_HCI
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed));
-+#endif
-+
-+#ifdef CONFIG_DYNAMIC_SOML
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVE_SOML, &(adapter->registrypriv.dyn_soml_en));
-+#endif
-+#ifdef CONFIG_RTW_PATH_DIV
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_PATH_DIV, &(adapter->registrypriv.path_div));
-+#endif
-+	odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FCS_MODE, &(pHalData->multi_ch_switch_mode));
-+
-+	/*halrf info hook*/
-+	/* waiting for PhyDMV034 support*/
-+	halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY, &(adapter->registrypriv.halrf_ability));
-+#ifdef CONFIG_MP_INCLUDED
-+	halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CON_TX, &(adapter->mppriv.mpt_ctx.is_start_cont_tx));
-+	halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_SINGLE_TONE, &(adapter->mppriv.mpt_ctx.is_single_tone));
-+	halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CARRIER_SUPPRESSION, &(adapter->mppriv.mpt_ctx.is_carrier_suppression));
-+	halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MP_RATE_INDEX, &(adapter->mppriv.mpt_ctx.mpt_rate_index));
-+#endif/*CONFIG_MP_INCLUDED*/
-+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
-+		phydm_cmn_sta_info_hook(pDM_Odm, i, NULL);
-+
-+	rtw_phydm_ops_func_init(pDM_Odm);
-+	phydm_dm_early_init(pDM_Odm);
-+	/* TODO */
-+	/* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */
-+	/* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */
-+}
-+
-+
-+static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
-+/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
-+/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx) */
-+{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
-+
-+static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
-+/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
-+/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)*/
-+{ 0xa44f, 0x5ea44f,	 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
-+
-+static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
-+/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
-+/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP */
-+{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322,	 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
-+
-+
-+struct turbo_edca_setting{
-+	u32 edca_ul; /* uplink, tx */
-+	u32 edca_dl; /* downlink, rx */
-+};
-+
-+#define TURBO_EDCA_ENT(UL, DL) {UL, DL}
-+
-+#if 0
-+#define TURBO_EDCA_MODE_NUM 18
-+static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
-+	TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 0 */
-+	TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */
-+	TURBO_EDCA_ENT(0x4319, 0x4319), /* mode 2 */	
-+	
-+	TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
-+	TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 4 */
-+	TURBO_EDCA_ENT(0x5e4319, 0x5e4319), /* mode 5 */	
-+	
-+	TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 6 */
-+	TURBO_EDCA_ENT(0x6e431c, 0x6e431c), /* mode 7 */
-+	TURBO_EDCA_ENT(0x6e4319, 0x6e4319), /* mode 8 */
-+	
-+	TURBO_EDCA_ENT(0x5ea42b, 0xa42b), /* mode 9 */
-+	TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 10 */
-+	TURBO_EDCA_ENT(0x5e4319, 0x4319), /* mode 11 */
-+	
-+	TURBO_EDCA_ENT(0x6ea42b, 0xa42b), /* mode 12 */
-+	TURBO_EDCA_ENT(0x6e431c, 0x431c), /* mode 13 */
-+	TURBO_EDCA_ENT(0x6e4319, 0x4319), /* mode 14 */
-+
-+	TURBO_EDCA_ENT(0x431c, 0x5e431c), /* mode 15 */
-+
-+	TURBO_EDCA_ENT(0xa42b, 0x5ea42b), /* mode 16 */
-+
-+	TURBO_EDCA_ENT(0x138642b, 0x431c), /* mode 17 */
-+};
-+#else
-+#define TURBO_EDCA_MODE_NUM 8
-+static struct turbo_edca_setting rtw_turbo_edca[TURBO_EDCA_MODE_NUM] = {
-+	/* { UL, DL } */
-+	TURBO_EDCA_ENT(0x5e431c, 0x431c), /* mode 0 */
-+
-+	TURBO_EDCA_ENT(0x431c, 0x431c), /* mode 1 */	
-+	
-+	TURBO_EDCA_ENT(0x5e431c, 0x5e431c), /* mode 2 */
-+
-+	TURBO_EDCA_ENT(0x5ea42b, 0x5ea42b), /* mode 3 */
-+	
-+	TURBO_EDCA_ENT(0x5ea42b, 0x431c), /* mode 4 */
-+	
-+	TURBO_EDCA_ENT(0x6ea42b, 0x6ea42b), /* mode 5 */
-+
-+	TURBO_EDCA_ENT(0xa42b, 0xa42b), /* mode 6 */
-+	
-+	TURBO_EDCA_ENT(0x5e431c, 0xa42b), /* mode 7 */
-+};
-+#endif
-+
-+void rtw_hal_turbo_edca(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE		*hal_data = GET_HAL_DATA(adapter);
-+	struct dvobj_priv		*dvobj = adapter_to_dvobj(adapter);
-+	struct recv_priv		*precvpriv = &(adapter->recvpriv);
-+	struct registry_priv		*pregpriv = &adapter->registrypriv;
-+	struct mlme_ext_priv	*pmlmeext = &(adapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	/* Parameter suggested by Scott  */
-+#if 0
-+	u32	EDCA_BE_UL = edca_setting_UL[p_mgnt_info->iot_peer];
-+	u32	EDCA_BE_DL = edca_setting_DL[p_mgnt_info->iot_peer];
-+#endif
-+	u32	EDCA_BE_UL = 0x5ea42b;
-+	u32	EDCA_BE_DL = 0x00a42b;
-+	u8	ic_type = rtw_get_chip_type(adapter);
-+
-+	u8	iot_peer = 0;
-+	u8	wireless_mode = 0xFF;                 /* invalid value */
-+	u8	traffic_index;
-+	u32	edca_param;
-+	u64	cur_tx_bytes = 0;
-+	u64	cur_rx_bytes = 0;
-+	u8	bbtchange = _TRUE;
-+	u8	is_bias_on_rx = _FALSE;
-+	u8	is_linked = _FALSE;
-+	u8	interface_type;
-+
-+	if (hal_data->dis_turboedca == 1)
-+		return;
-+
-+	if (rtw_mi_check_status(adapter, MI_ASSOC))
-+		is_linked = _TRUE;
-+
-+	if (is_linked != _TRUE) {
-+		precvpriv->is_any_non_be_pkts = _FALSE;
-+		return;
-+	}
-+
-+	if (pregpriv->wifi_spec == 1) { /* || (pmlmeinfo->HT_enable == 0)) */
-+		precvpriv->is_any_non_be_pkts = _FALSE;
-+		return;
-+	}
-+
-+	interface_type = rtw_get_intf_type(adapter);
-+	wireless_mode = pmlmeext->cur_wireless_mode;
-+
-+	iot_peer = pmlmeinfo->assoc_AP_vendor;
-+
-+	if (iot_peer >=  HT_IOT_PEER_MAX) {
-+		precvpriv->is_any_non_be_pkts = _FALSE;
-+		return;
-+	}
-+
-+	if (ic_type == RTL8188E) {
-+		if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))
-+			is_bias_on_rx = _TRUE;
-+	}
-+
-+	/* Check if the status needs to be changed. */
-+	if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {
-+		cur_tx_bytes = dvobj->traffic_stat.cur_tx_bytes;
-+		cur_rx_bytes = dvobj->traffic_stat.cur_rx_bytes;
-+
-+		/* traffic, TX or RX */
-+		if (is_bias_on_rx) {
-+			if (cur_tx_bytes > (cur_rx_bytes << 2)) {
-+				/* Uplink TP is present. */
-+				traffic_index = UP_LINK;
-+			} else {
-+				/* Balance TP is present. */
-+				traffic_index = DOWN_LINK;
-+			}
-+		} else {
-+			if (cur_rx_bytes > (cur_tx_bytes << 2)) {
-+				/* Downlink TP is present. */
-+				traffic_index = DOWN_LINK;
-+			} else {
-+				/* Balance TP is present. */
-+				traffic_index = UP_LINK;
-+			}
-+		}
-+#if 0
-+		if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index)
-+			|| (!p_dm_odm->dm_edca_table.is_current_turbo_edca))
-+#endif
-+		{
-+			if (interface_type == RTW_PCIE) {
-+				EDCA_BE_UL = 0x6ea42b;
-+				EDCA_BE_DL = 0x6ea42b;
-+			}
-+
-+			/* 92D txop can't be set to 0x3e for cisco1250 */
-+			if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
-+				EDCA_BE_DL = edca_setting_DL[iot_peer];
-+				EDCA_BE_UL = edca_setting_UL[iot_peer];
-+			}
-+			/* merge from 92s_92c_merge temp*/
-+			else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
-+				EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];
-+			else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
-+				EDCA_BE_DL = 0xa630;
-+			else if (iot_peer == HT_IOT_PEER_MARVELL) {
-+				EDCA_BE_DL = edca_setting_DL[iot_peer];
-+				EDCA_BE_UL = edca_setting_UL[iot_peer];
-+			} else if (iot_peer == HT_IOT_PEER_ATHEROS) {
-+				/* Set DL EDCA for Atheros peer to 0x3ea42b.*/
-+				/* Suggested by SD3 Wilson for ASUS TP issue.*/
-+				EDCA_BE_DL = edca_setting_DL[iot_peer];
-+			}
-+
-+			if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E) || (ic_type == RTL8192F)) { /* add 8812AU/8812AE */
-+				EDCA_BE_UL = 0x5ea42b;
-+				EDCA_BE_DL = 0x5ea42b;
-+
-+				RTW_DBG("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x\n", EDCA_BE_UL, EDCA_BE_DL);
-+			}
-+
-+			if (interface_type == RTW_PCIE &&
-+				((ic_type == RTL8822B)
-+				|| (ic_type == RTL8822C)
-+				|| (ic_type == RTL8814A) || (ic_type == RTL8814B))) {
-+				EDCA_BE_UL = 0x6ea42b;
-+				EDCA_BE_DL = 0x6ea42b;
-+			}
-+
-+			if ((ic_type == RTL8822B)
-+			    && (interface_type == RTW_SDIO))
-+				EDCA_BE_DL = 0x00431c;
-+
-+#ifdef CONFIG_RTW_TPT_MODE
-+			if ( dvobj->tpt_mode > 0 ) {				
-+				EDCA_BE_UL = dvobj->edca_be_ul;
-+				EDCA_BE_DL = dvobj->edca_be_dl;
-+			}
-+#endif /* CONFIG_RTW_TPT_MODE */
-+
-+			/* keep this condition at last check */
-+			if (hal_data->dis_turboedca == 2) {					
-+				
-+					if (hal_data->edca_param_mode < TURBO_EDCA_MODE_NUM) {
-+
-+						struct turbo_edca_setting param;
-+
-+						param = rtw_turbo_edca[hal_data->edca_param_mode];
-+
-+						EDCA_BE_UL = param.edca_ul;
-+						EDCA_BE_DL = param.edca_dl;
-+						
-+					} else {
-+					
-+						EDCA_BE_UL = hal_data->edca_param_mode;
-+						EDCA_BE_DL = hal_data->edca_param_mode;
-+					}				
-+			}
-+
-+			if (traffic_index == DOWN_LINK)
-+				edca_param = EDCA_BE_DL;
-+			else
-+				edca_param = EDCA_BE_UL;
-+
-+#ifdef CONFIG_EXTEND_LOWRATE_TXOP
-+#define TXOP_CCK1M			0x01A6
-+#define TXOP_CCK2M			0x00E6
-+#define TXOP_CCK5M			0x006B
-+#define TXOP_OFD6M			0x0066
-+#define TXOP_MCS6M			0x0061
-+{
-+			struct sta_info *psta;
-+			struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+			u8 mac_id, role, current_rate_id;
-+			
-+			/*	search all used & connect2AP macid	*/
-+			for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {
-+				if (rtw_macid_is_used(macid_ctl, mac_id))  {
-+					role = GET_H2CCMD_MSRRPT_PARM_ROLE(&(macid_ctl->h2c_msr[mac_id]));
-+					if (role != H2C_MSR_ROLE_AP)
-+						continue;
-+
-+					psta = macid_ctl->sta[mac_id];
-+					current_rate_id = rtw_get_current_tx_rate(adapter, psta);
-+					/*  Check init tx_rate==1M and set 0x508[31:16]==0x019B(unit 32us) if it is 	*/
-+					switch (current_rate_id) {
-+						case DESC_RATE1M:
-+							edca_param &= 0x0000FFFF;
-+							edca_param |= (TXOP_CCK1M<<16);
-+							break;
-+						case DESC_RATE2M:
-+							edca_param &= 0x0000FFFF;
-+							edca_param |= (TXOP_CCK2M<<16);
-+							break;
-+						case DESC_RATE5_5M:
-+							edca_param &= 0x0000FFFF;
-+							edca_param |= (TXOP_CCK5M<<16);
-+							break;
-+						case DESC_RATE6M:
-+							edca_param &= 0x0000FFFF;
-+							edca_param |= (TXOP_OFD6M<<16);
-+							break;
-+						case DESC_RATEMCS0:
-+							edca_param &= 0x0000FFFF;
-+							edca_param |= (TXOP_MCS6M<<16);
-+							break;
-+						default:
-+							break;
-+					}
-+				}
-+			}
-+}
-+#endif /* CONFIG_EXTEND_LOWRATE_TXOP */
-+
-+#ifdef 	CONFIG_RTW_CUSTOMIZE_BEEDCA
-+			edca_param = CONFIG_RTW_CUSTOMIZE_BEEDCA;
-+#endif
-+
-+			if ( edca_param != hal_data->ac_param_be) {
-+				
-+				rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
-+
-+				RTW_INFO("Turbo EDCA =0x%x\n", edca_param);
-+			}
-+
-+			hal_data->prv_traffic_idx = traffic_index;
-+		}
-+
-+		hal_data->is_turbo_edca = _TRUE;
-+	} else {
-+		/*  */
-+		/* Turn Off EDCA turbo here. */
-+		/* Restore original EDCA according to the declaration of AP. */
-+		/*  */
-+		if (hal_data->is_turbo_edca) {
-+			edca_param = hal_data->ac_param_be;
-+			rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
-+			hal_data->is_turbo_edca = _FALSE;
-+		}
-+	}
-+
-+}
-+
-+s8 rtw_dm_get_min_rssi(_adapter *adapter)
-+{
-+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
-+	struct sta_info *sta;
-+	s8 min_rssi = 127, rssi;
-+	int i;
-+
-+	for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
-+		sta = macid_ctl->sta[i];
-+		if (!sta || !GET_H2CCMD_MSRRPT_PARM_OPMODE(macid_ctl->h2c_msr + i)
-+			|| is_broadcast_mac_addr(sta->cmn.mac_addr))
-+			continue;
-+		rssi = sta->cmn.rssi_stat.rssi;
-+		if (rssi >= 0 && min_rssi > rssi)
-+			min_rssi = rssi;
-+	}
-+
-+	return min_rssi == 127 ? 0 : min_rssi;
-+}
-+
-+s8 rtw_phydm_get_min_rssi(_adapter *adapter)
-+{
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+	s8 rssi_min = 0;
-+
-+	rssi_min = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_RSSI_MIN);
-+	return rssi_min;
-+}
-+
-+u8 rtw_phydm_get_cur_igi(_adapter *adapter)
-+{
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+	u8 cur_igi = 0;
-+
-+	cur_igi = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CURR_IGI);
-+	return cur_igi;
-+}
-+
-+bool rtw_phydm_get_edcca_flag(_adapter *adapter)
-+{
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+	bool cur_edcca_flag = 0;
-+
-+	cur_edcca_flag = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_EDCCA_FLAG);
-+	return cur_edcca_flag;
-+}
-+
-+u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt)
-+{
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+
-+	if (cnt == FA_OFDM)
-+		return  phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_OFDM);
-+	else if (cnt == FA_CCK)
-+		return  phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_CCK);
-+	else if (cnt == FA_TOTAL)
-+		return  phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_TOTAL);
-+	else if (cnt == CCA_OFDM)
-+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_OFDM);
-+	else if (cnt == CCA_CCK)
-+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_CCK);
-+	else if (cnt == CCA_ALL)
-+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_ALL);
-+	else if (cnt == CRC32_OK_VHT)
-+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_VHT);
-+	else if (cnt == CRC32_OK_HT)
-+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_HT);
-+	else if (cnt == CRC32_OK_LEGACY)
-+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_LEGACY);
-+	else if (cnt == CRC32_OK_CCK)
-+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_CCK);
-+	else if (cnt == CRC32_ERROR_VHT)
-+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_VHT);
-+	else if (cnt == CRC32_ERROR_HT)
-+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_HT);
-+	else if (cnt == CRC32_ERROR_LEGACY)
-+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_LEGACY);
-+	else if (cnt == CRC32_ERROR_CCK)
-+		return	phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_CCK);
-+	else
-+		return 0;
-+}
-+
-+u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter)
-+{
-+	u8 rts = _FALSE;
-+	struct dm_struct *podmpriv = adapter_to_phydm(adapter);
-+
-+	odm_acquire_spin_lock(podmpriv, RT_IQK_SPINLOCK);
-+	if (podmpriv->rf_calibrate_info.is_iqk_in_progress == _TRUE) {
-+		RTW_ERR("IQK InProgress\n");
-+		rts = _TRUE;
-+	}
-+	odm_release_spin_lock(podmpriv, RT_IQK_SPINLOCK);
-+
-+	return rts;
-+}
-+
-+void SetHalODMVar(
-+	PADAPTER				Adapter,
-+	HAL_ODM_VARIABLE		eVariable,
-+	void						*pValue1,
-+	BOOLEAN					bSet)
-+{
-+	struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
-+	/* _irqL irqL; */
-+	switch (eVariable) {
-+	case HAL_ODM_STA_INFO: {
-+		struct sta_info *psta = (struct sta_info *)pValue1;
-+
-+		if (bSet) {
-+			RTW_INFO("### Set STA_(%d) info ###\n", psta->cmn.mac_id);
-+			psta->cmn.dm_ctrl = STA_DM_CTRL_ACTIVE;
-+			phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, &(psta->cmn));
-+		} else {
-+			RTW_INFO("### Clean STA_(%d) info ###\n", psta->cmn.mac_id);
-+			/* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
-+			psta->cmn.dm_ctrl = 0;
-+			phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, NULL);
-+
-+			/* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
-+		}
-+	}
-+		break;
-+	case HAL_ODM_P2P_STATE:
-+		odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
-+		break;
-+	case HAL_ODM_WIFI_DISPLAY_STATE:
-+		odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
-+		break;
-+	case HAL_ODM_REGULATION:
-+		/* used to auto enable/disable adaptivity by SD7 */
-+		phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_2G, 0);
-+		phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_5G, 0);
-+		break;
-+	case HAL_ODM_INITIAL_GAIN: {
-+		u8 rx_gain = *((u8 *)(pValue1));
-+		/*printk("rx_gain:%x\n",rx_gain);*/
-+		if (rx_gain == 0xff) {/*restore rx gain*/
-+			/*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/
-+			odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain);
-+		} else {
-+			/*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/
-+			/*odm_write_dig(podmpriv,rx_gain);*/
-+			odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain);
-+		}
-+	}
-+	break;
-+	case HAL_ODM_RX_INFO_DUMP: {
-+		u8 cur_igi = 0;
-+		s8 rssi_min;
-+		void *sel;
-+
-+		sel = pValue1;
-+		cur_igi = rtw_phydm_get_cur_igi(Adapter);
-+		rssi_min = rtw_phydm_get_min_rssi(Adapter);
-+
-+		_RTW_PRINT_SEL(sel, "============ Rx Info dump ===================\n");
-+		_RTW_PRINT_SEL(sel, "is_linked = %d, rssi_min = %d(%%)(%d(%%)), current_igi = 0x%x\n"
-+			, podmpriv->is_linked, rssi_min, rtw_dm_get_min_rssi(Adapter), cur_igi);
-+		_RTW_PRINT_SEL(sel, "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n",
-+			rtw_phydm_get_phy_cnt(Adapter, FA_CCK),
-+			rtw_phydm_get_phy_cnt(Adapter, FA_OFDM),
-+			rtw_phydm_get_phy_cnt(Adapter, FA_TOTAL));
-+
-+		if (podmpriv->is_linked) {
-+			_RTW_PRINT_SEL(sel, "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate));
-+			if (IS_HARDWARE_TYPE_8814A(Adapter))
-+				_RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%), rssi_c = %d(%%), rssi_d = %d(%%)\n",
-+					podmpriv->rssi_a, podmpriv->rssi_b, podmpriv->rssi_c, podmpriv->rssi_d);
-+			else
-+				_RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%)\n", podmpriv->rssi_a, podmpriv->rssi_b);
-+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
-+			rtw_dump_raw_rssi_info(Adapter, sel);
-+#endif
-+		}
-+	}
-+		break;
-+	case HAL_ODM_RX_Dframe_INFO: {
-+		void *sel;
-+
-+		sel = pValue1;
-+
-+		/*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/
-+#ifdef DBG_RX_DFRAME_RAW_DATA
-+		rtw_dump_rx_dframe_info(Adapter, sel);
-+#endif
-+	}
-+		break;
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	case HAL_ODM_ANTDIV_SELECT: {
-+		u8	antenna = (*(u8 *)pValue1);
-+		HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+		/*switch antenna*/
-+		odm_update_rx_idle_ant(&pHalData->odmpriv, antenna);
-+		/*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/
-+
-+	}
-+		break;
-+#endif
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+void GetHalODMVar(
-+	PADAPTER				Adapter,
-+	HAL_ODM_VARIABLE		eVariable,
-+	void						*pValue1,
-+	void						*pValue2)
-+{
-+	struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
-+
-+	switch (eVariable) {
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	case HAL_ODM_ANTDIV_SELECT: {
-+		struct phydm_fat_struct	*pDM_FatTable = &podmpriv->dm_fat_table;
-+		*((u8 *)pValue1) = pDM_FatTable->rx_idle_ant;
-+	}
-+		break;
-+#endif
-+	case HAL_ODM_INITIAL_GAIN:
-+		*((u8 *)pValue1) = rtw_phydm_get_cur_igi(Adapter);
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+#ifdef RTW_HALMAC
-+#include "../hal_halmac.h"
-+#endif
-+bool rtw_phydm_rfe_ctrl_gpio(
-+	_adapter *adapter,
-+	u8 gpio_num
-+)
-+{
-+	#ifdef RTW_HALMAC
-+	if(rtw_halmac_rfe_ctrl_cfg(adapter_to_dvobj(adapter), gpio_num))
-+		return _TRUE;
-+	else
-+	#endif/*RTW_HALMAC*/
-+		return _FALSE;
-+}
-+
-+enum hal_status
-+rtw_phydm_fw_iqk(
-+	struct dm_struct	*p_dm_odm,
-+	u8 clear,
-+	u8 segment
-+)
-+{
-+	#ifdef RTW_HALMAC
-+	struct _ADAPTER *adapter = p_dm_odm->adapter;
-+
-+	if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0)
-+		return HAL_STATUS_SUCCESS;
-+	#endif
-+	return HAL_STATUS_FAILURE;
-+}
-+
-+enum hal_status
-+rtw_phydm_cfg_phy_para(
-+	struct dm_struct	*p_dm_odm,
-+	enum phydm_halmac_param config_type,
-+	u32 offset,
-+	u32 data,
-+	u32 mask,
-+	enum rf_path e_rf_path,
-+	u32 delay_time)
-+{
-+	#ifdef RTW_HALMAC
-+	struct _ADAPTER *adapter = p_dm_odm->adapter;
-+	struct rtw_phy_parameter para;
-+
-+	switch (config_type) {
-+	case PHYDM_HALMAC_CMD_MAC_W8:
-+		para.cmd = 0; /* MAC register */
-+		para.data.mac.offset = offset;
-+		para.data.mac.value = data;
-+		para.data.mac.msk = mask;
-+		para.data.mac.msk_en = (mask) ? 1 : 0;
-+		para.data.mac.size = 1;
-+	break;
-+	case PHYDM_HALMAC_CMD_MAC_W16:
-+		para.cmd = 0; /* MAC register */
-+		para.data.mac.offset = offset;
-+		para.data.mac.value = data;
-+		para.data.mac.msk = mask;
-+		para.data.mac.msk_en = (mask) ? 1 : 0;
-+		para.data.mac.size = 2;
-+	break;
-+	case PHYDM_HALMAC_CMD_MAC_W32:
-+		para.cmd = 0; /* MAC register */
-+		para.data.mac.offset = offset;
-+		para.data.mac.value = data;
-+		para.data.mac.msk = mask;
-+		para.data.mac.msk_en = (mask) ? 1 : 0;
-+		para.data.mac.size = 4;
-+	break;
-+	case PHYDM_HALMAC_CMD_BB_W8:
-+		para.cmd = 1; /* BB register */
-+		para.data.bb.offset = offset;
-+		para.data.bb.value = data;
-+		para.data.bb.msk = mask;
-+		para.data.bb.msk_en = (mask) ? 1 : 0;
-+		para.data.bb.size = 1;
-+	break;
-+	case PHYDM_HALMAC_CMD_BB_W16:
-+		para.cmd = 1; /* BB register */
-+		para.data.bb.offset = offset;
-+		para.data.bb.value = data;
-+		para.data.bb.msk = mask;
-+		para.data.bb.msk_en = (mask) ? 1 : 0;
-+		para.data.bb.size = 2;
-+	break;
-+	case PHYDM_HALMAC_CMD_BB_W32:
-+		para.cmd = 1; /* BB register */
-+		para.data.bb.offset = offset;
-+		para.data.bb.value = data;
-+		para.data.bb.msk = mask;
-+		para.data.bb.msk_en = (mask) ? 1 : 0;
-+		para.data.bb.size = 4;
-+	break;
-+	case PHYDM_HALMAC_CMD_RF_W:
-+		para.cmd = 2; /* RF register */
-+		para.data.rf.offset = offset;
-+		para.data.rf.value = data;
-+		para.data.rf.msk = mask;
-+		para.data.rf.msk_en = (mask) ? 1 : 0;
-+		if (e_rf_path == RF_PATH_A)
-+			para.data.rf.path = 0;
-+		else if (e_rf_path == RF_PATH_B)
-+			para.data.rf.path = 1;
-+		else if (e_rf_path == RF_PATH_C)
-+			para.data.rf.path = 2;
-+		else if (e_rf_path == RF_PATH_D)
-+			para.data.rf.path = 3;
-+		else
-+			para.data.rf.path = 0;
-+	break;
-+	case PHYDM_HALMAC_CMD_DELAY_US:
-+		para.cmd = 3; /* Delay */
-+		para.data.delay.unit = 0; /* microsecond */
-+		para.data.delay.value = delay_time;
-+	break;
-+	case PHYDM_HALMAC_CMD_DELAY_MS:
-+		para.cmd = 3; /* Delay */
-+		para.data.delay.unit = 1; /* millisecond */
-+		para.data.delay.value = delay_time;
-+	break;
-+	case PHYDM_HALMAC_CMD_END:
-+		para.cmd = 0xFF; /* End command */
-+	break;
-+	default:
-+		return HAL_STATUS_FAILURE;
-+	}
-+
-+	if (rtw_halmac_cfg_phy_para(adapter_to_dvobj(adapter), &para))
-+		return HAL_STATUS_FAILURE;
-+	#endif /*RTW_HALMAC*/
-+	return HAL_STATUS_SUCCESS;
-+}
-+
-+
-+#ifdef CONFIG_LPS_LCLK_WD_TIMER
-+void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter)
-+{
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+	struct sta_info *psta = NULL;
-+	bool is_linked = _FALSE;
-+
-+	if (!rtw_is_hw_init_completed(adapter))
-+		return;
-+
-+	if (rtw_mi_check_status(adapter, MI_ASSOC))
-+		is_linked = _TRUE;
-+
-+	if (is_linked == _FALSE)
-+		return;
-+
-+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
-+	if (psta == NULL)
-+		return;
-+
-+	odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, is_linked);
-+
-+	phydm_watchdog_lps_32k(&pHalData->odmpriv);
-+
-+#ifdef CONFIG_LPS_PG
-+	if (pwrpriv->lps_level == LPS_PG) {
-+		 if (rtw_hal_set_lps_pg_info_cmd(adapter) == _FAIL)
-+		 	RTW_INFO(FUNC_ADPT_FMT": Send PG H2C command Fail! \n", 
-+		 			 FUNC_ADPT_ARG(adapter));
-+	}
-+#endif /* CONFIG_LPS_PG */
-+}
-+
-+void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter)
-+{
-+	struct mlme_priv	*pmlmepriv = &adapter->mlmepriv;
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+	u8 cur_igi = 0;
-+	s8 min_rssi = 0;
-+
-+	if (!rtw_is_hw_init_completed(adapter))
-+		return;
-+
-+	cur_igi = rtw_phydm_get_cur_igi(adapter);
-+	min_rssi = rtw_dm_get_min_rssi(adapter);
-+	/*RTW_INFO("%s "ADPT_FMT" cur_ig_value=%d, min_rssi = %d\n", __func__,  ADPT_ARG(adapter), cur_igi, min_rssi);*/
-+
-+	if (min_rssi <= 0)
-+		return;
-+
-+	if ((cur_igi > min_rssi + 5) ||
-+		(cur_igi < min_rssi - 5)) {
-+#ifdef CONFIG_LPS
-+		rtw_dm_in_lps_wk_cmd(adapter);
-+#endif
-+	}
-+}
-+#endif /*CONFIG_LPS_LCLK_WD_TIMER*/
-+
-+void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta)
-+{
-+	struct ra_sta_info *ra_info;
-+	u8 curr_sgi = _FALSE;
-+	u32 tx_tp_mbips, rx_tp_mbips, bi_tp_mbips;
-+
-+	if (!psta)
-+		return;
-+	RTW_PRINT_SEL(sel, "\n");
-+	RTW_PRINT_SEL(sel, "====== mac_id : %d [" MAC_FMT "] ======\n",
-+		psta->cmn.mac_id, MAC_ARG(psta->cmn.mac_addr));
-+
-+	if (is_client_associated_to_ap(psta->padapter))
-+		RTW_PRINT_SEL(sel, "BCN counts : %d (per-%d second), DTIM Period:%d\n",
-+		rtw_get_bcn_cnt(psta->padapter) / 2, 1, rtw_get_bcn_dtim_period(psta->padapter));
-+
-+	ra_info = &psta->cmn.ra_info;
-+	curr_sgi = rtw_get_current_tx_sgi(adapter, psta);
-+	RTW_PRINT_SEL(sel, "tx_rate : %s(%s)  rx_rate : %s, rx_rate_bmc : %s, rssi : %d %%\n"
-+		, HDATA_RATE(rtw_get_current_tx_rate(adapter, psta)), (curr_sgi) ? "S" : "L"
-+		, HDATA_RATE((psta->curr_rx_rate & 0x7F)), HDATA_RATE((psta->curr_rx_rate_bmc & 0x7F)), psta->cmn.rssi_stat.rssi
-+	);
-+
-+	if (0) {
-+		RTW_PRINT_SEL(sel, "tx_bytes:%llu(%llu - %llu)\n"
-+			, psta->sta_stats.tx_bytes - psta->sta_stats.last_tx_bytes
-+			, psta->sta_stats.tx_bytes, psta->sta_stats.last_tx_bytes
-+		);
-+		RTW_PRINT_SEL(sel, "rx_uc_bytes:%llu(%llu - %llu)\n"
-+			, sta_rx_uc_bytes(psta) - sta_last_rx_uc_bytes(psta)
-+			, sta_rx_uc_bytes(psta), sta_last_rx_uc_bytes(psta)
-+		);
-+		RTW_PRINT_SEL(sel, "rx_mc_bytes:%llu(%llu - %llu)\n"
-+			, psta->sta_stats.rx_mc_bytes - psta->sta_stats.last_rx_mc_bytes
-+			, psta->sta_stats.rx_mc_bytes, psta->sta_stats.last_rx_mc_bytes
-+		);
-+		RTW_PRINT_SEL(sel, "rx_bc_bytes:%llu(%llu - %llu)\n"
-+			, psta->sta_stats.rx_bc_bytes - psta->sta_stats.last_rx_bc_bytes
-+			, psta->sta_stats.rx_bc_bytes, psta->sta_stats.last_rx_bc_bytes
-+		);
-+	}
-+
-+	_RTW_PRINT_SEL(sel, "RTW: [TP] ");
-+	tx_tp_mbips = psta->sta_stats.tx_tp_kbits >> 10;
-+	rx_tp_mbips = psta->sta_stats.rx_tp_kbits >> 10;
-+	bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
-+
-+	if (tx_tp_mbips)
-+		_RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
-+	else
-+		_RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.tx_tp_kbits);
-+
-+	if (rx_tp_mbips) 
-+		_RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
-+	else
-+		_RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.rx_tp_kbits);
-+
-+	if (bi_tp_mbips)
-+		_RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
-+	else
-+		_RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
-+
-+
-+	_RTW_PRINT_SEL(sel, "RTW: [Smooth TP] ");
-+	tx_tp_mbips = psta->sta_stats.smooth_tx_tp_kbits >> 10;
-+	rx_tp_mbips = psta->sta_stats.smooth_rx_tp_kbits >> 10;
-+	bi_tp_mbips = tx_tp_mbips + rx_tp_mbips;
-+	if (tx_tp_mbips)
-+		_RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips);
-+	else
-+		_RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.smooth_tx_tp_kbits);
-+
-+	if (rx_tp_mbips) 
-+		_RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips);
-+	else
-+		_RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.smooth_rx_tp_kbits);
-+
-+	if (bi_tp_mbips)
-+		_RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips);
-+	else
-+		_RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.smooth_tx_tp_kbits + psta->sta_stats.rx_tp_kbits);
-+
-+	#if 0
-+	RTW_PRINT_SEL(sel, "Moving-AVG TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n\n",
-+		(psta->cmn.tx_moving_average_tp << 3), (psta->cmn.rx_moving_average_tp << 3),
-+		(psta->cmn.tx_moving_average_tp + psta->cmn.rx_moving_average_tp) << 3);
-+	#endif
-+}
-+
-+void dump_sta_info(void *sel, struct sta_info *psta)
-+{
-+	struct ra_sta_info *ra_info;
-+	u8 curr_tx_sgi = _FALSE;
-+	u8 curr_tx_rate = 0;
-+
-+	if (!psta)
-+		return;
-+
-+	ra_info = &psta->cmn.ra_info;
-+
-+	RTW_PRINT_SEL(sel, "============ STA [" MAC_FMT "]  ===================\n",
-+		MAC_ARG(psta->cmn.mac_addr));
-+	RTW_PRINT_SEL(sel, "mac_id : %d\n", psta->cmn.mac_id);
-+	RTW_PRINT_SEL(sel, "wireless_mode : 0x%02x\n", psta->wireless_mode);
-+	RTW_PRINT_SEL(sel, "mimo_type : %d\n", psta->cmn.mimo_type);
-+	RTW_PRINT_SEL(sel, "static smps : %s\n", (psta->cmn.sm_ps == SM_PS_STATIC) ? "Y" : "N");
-+	RTW_PRINT_SEL(sel, "bw_mode : %s, ra_bw_mode : %s\n",
-+			ch_width_str(psta->cmn.bw_mode), ch_width_str(ra_info->ra_bw_mode));
-+	RTW_PRINT_SEL(sel, "rate_id : %d\n", ra_info->rate_id);
-+	RTW_PRINT_SEL(sel, "rssi : %d (%%), rssi_level : %d\n", psta->cmn.rssi_stat.rssi, ra_info->rssi_level);
-+	RTW_PRINT_SEL(sel, "is_support_sgi : %s, is_vht_enable : %s\n",
-+			(ra_info->is_support_sgi) ? "Y" : "N", (ra_info->is_vht_enable) ? "Y" : "N");
-+	RTW_PRINT_SEL(sel, "disable_ra : %s, disable_pt : %s\n",
-+				(ra_info->disable_ra) ? "Y" : "N", (ra_info->disable_pt) ? "Y" : "N");
-+	RTW_PRINT_SEL(sel, "is_noisy : %s\n", (ra_info->is_noisy) ? "Y" : "N");
-+	RTW_PRINT_SEL(sel, "txrx_state : %d\n", ra_info->txrx_state);/*0: uplink, 1:downlink, 2:bi-direction*/
-+
-+	curr_tx_sgi = rtw_get_current_tx_sgi(psta->padapter, psta);
-+	curr_tx_rate = rtw_get_current_tx_rate(psta->padapter, psta);
-+	RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n",
-+			HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L");
-+	RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw));
-+	RTW_PRINT_SEL(sel, "curr_retry_ratio : %d\n", ra_info->curr_retry_ratio);
-+	RTW_PRINT_SEL(sel, "ra_mask : 0x%016llx\n\n", ra_info->ramask);
-+}
-+
-+void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+
-+	if (psta == NULL) {
-+		RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(adapter));
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	if (psta->cmn.mac_id >= macid_ctl->num)
-+		return;
-+
-+	phydm_ra_registed(&hal_data->odmpriv, psta->cmn.mac_id, psta->cmn.rssi_stat.rssi);
-+	dump_sta_info(RTW_DBGDUMP, psta);
-+}
-+
-+static void init_phydm_info(_adapter *adapter)
-+{
-+	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA(adapter);
-+	struct dm_struct *phydm = &(hal_data->odmpriv);
-+
-+	odm_cmn_info_init(phydm, ODM_CMNINFO_FW_VER, hal_data->firmware_version);
-+	odm_cmn_info_init(phydm, ODM_CMNINFO_FW_SUB_VER, hal_data->firmware_sub_version);
-+}
-+
-+#ifdef CONFIG_CTRL_TXSS_BY_TP
-+void rtw_phydm_trx_cfg(_adapter *adapter, bool tx_1ss)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	enum bb_path txpath = BB_PATH_AB;
-+	enum bb_path rxpath = BB_PATH_AB;
-+	/*is_2tx = _FALSE for 8822B, or BB_PATH_AUTO for PATH_DIVERSITY for 8822B*/
-+	enum bb_path txpath_1ss = BB_PATH_A;
-+
-+	rtw_hal_get_trx_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
-+	txpath = (tx_1ss) ? BB_PATH_A : txpath;
-+
-+	if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE)
-+		RTW_ERR("%s failed\n", __func__);
-+}
-+#endif
-+
-+u8 rtw_hal_runtime_trx_path_decision(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	enum bb_path txpath;
-+	enum bb_path rxpath;
-+	int i;
-+	u8 rst = _FAIL;
-+
-+	rtw_hal_get_trx_path(adapter_to_dvobj(adapter), NULL, &txpath, &rxpath);
-+	if (!txpath) {
-+		RTW_ERR("%s tx_path_bmp is empty\n", __func__);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+	if (!rxpath) {
-+		RTW_ERR("%s rx_path_bmp is empty\n", __func__);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	tx_path_nss_set_default(hal_data->txpath_nss, hal_data->txpath_num_nss
-+		, GET_HAL_TX_PATH_BMP(adapter));
-+
-+#if defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B) ||defined(CONFIG_RTL8822C)
-+{
-+	enum bb_path txpath_1ss;
-+
-+	if (txpath == BB_PATH_AB) {
-+		switch (hal_data->max_tx_cnt) {
-+		case 2:
-+			#ifdef CONFIG_RTW_TX_NPATH_EN
-+			if (adapter->registrypriv.tx_npath == 1)
-+				txpath_1ss = BB_PATH_AB;
-+			else
-+			#endif
-+			#ifdef CONFIG_RTW_PATH_DIV
-+			if (adapter->registrypriv.path_div == 1) /* path diversity, support 2sts TX */
-+				txpath_1ss = BB_PATH_AUTO;
-+			else
-+			#endif
-+				txpath_1ss = BB_PATH_A;
-+			break;
-+		case 1:
-+			#ifdef CONFIG_RTW_PATH_DIV
-+			if (adapter->registrypriv.path_div == 1) /* path diversity, no support 2sts TX */
-+				txpath = txpath_1ss = BB_PATH_AUTO;
-+			else
-+			#endif
-+				txpath = txpath_1ss = BB_PATH_A;
-+			break;
-+		default:
-+			RTW_ERR("%s invalid max_tx_cnt:%u\n", __func__
-+				, hal_data->max_tx_cnt);
-+			rtw_warn_on(1);
-+			goto exit;
-+		}
-+	} else 
-+		txpath_1ss = txpath;
-+
-+	if (hal_data->txpath_nss[0] != txpath_1ss) {
-+		hal_data->txpath_nss[0] = txpath_1ss;
-+		if (txpath_1ss == BB_PATH_AUTO)
-+			hal_data->txpath_num_nss[0] = 1;
-+		else {
-+			hal_data->txpath_num_nss[0] = 0;
-+			for (i = 0; i < RF_PATH_MAX; i++) {
-+				if (txpath_1ss & BIT(i))
-+					hal_data->txpath_num_nss[0]++;
-+			}
-+		}
-+	}
-+}
-+#elif defined(CONFIG_RTL8814B)
-+{
-+	/* 8814B is always full-TX */
-+	tx_path_nss_set_full_tx(hal_data->txpath_nss, hal_data->txpath_num_nss, txpath);
-+}
-+#elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8192E)
-+{
-+	#ifdef CONFIG_RTW_TX_NPATH_EN
-+	if (adapter->registrypriv.tx_npath == 1)
-+		tx_path_nss_set_full_tx(hal_data->txpath_nss, hal_data->txpath_num_nss, txpath);
-+	#endif
-+}
-+#endif
-+
-+	hal_data->txpath = txpath;
-+	hal_data->rxpath = rxpath;
-+	dump_hal_runtime_trx_mode(RTW_DBGDUMP, adapter);
-+	rst = _SUCCESS;
-+
-+exit:
-+	return rst;
-+}
-+
-+/*
-+* trx_mode init - 8822B / 8822C / 8192F
-+* 1ssNTx - 8192E / 8812A / 8822B / 8822C / 8192F
-+* Path-diversity - 8822B / 8822C / 8192F
-+* PHYDM API - phydm_api_trx_mode
-+*/
-+static u8 rtw_phydm_config_trx_path(_adapter *adapter)
-+{
-+	u8 rst = _SUCCESS;
-+
-+#if defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B) ||defined(CONFIG_RTL8822C)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	enum bb_path txpath = hal_data->txpath;
-+	enum bb_path rxpath = hal_data->rxpath;
-+	enum bb_path txpath_1ss = hal_data->txpath_nss[0];
-+
-+	if (phydm_api_trx_mode(adapter_to_phydm(adapter), txpath, rxpath, txpath_1ss) == FALSE) {
-+		RTW_ERR("%s txpath=0x%x, rxpath=0x%x, txpath_1ss=0x%x fail\n", __func__
-+			, txpath, rxpath, txpath_1ss);
-+		rtw_warn_on(1);
-+		rst = _FAIL;
-+	}
-+}
-+#elif defined(CONFIG_RTL8814B)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	enum bb_path txpath = hal_data->txpath;
-+	enum bb_path rxpath = hal_data->rxpath;
-+
-+	if (txpath == BB_PATH_ABCD && rxpath == BB_PATH_ABCD)
-+		rst = config_phydm_trx_mode_8814b(adapter_to_phydm(adapter), txpath, rxpath);
-+	else
-+		rst = config_phydm_trx_mode_ext_8814b(adapter_to_phydm(adapter), txpath,
-+						      rxpath,
-+						      txpath, txpath, txpath);
-+	if (rst == FALSE) {
-+		RTW_ERR("%s txpath=0x%x, rxpath=0x%x fail\n", __func__
-+			, txpath, rxpath);
-+		rtw_warn_on(1);
-+		rst = _FAIL;
-+	}
-+}
-+#elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8192E)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+	if (hal_data->txpath_num_nss[0] == 2)
-+		phydm_tx_2path(adapter_to_phydm(adapter));
-+}
-+#endif
-+
-+	return rst;
-+}
-+
-+void rtw_phydm_init(_adapter *adapter)
-+{
-+	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA(adapter);
-+	struct dm_struct	*phydm = &(hal_data->odmpriv);
-+
-+	rtw_phydm_config_trx_path(adapter);
-+	init_phydm_info(adapter);
-+	hal_data->phydm_init_result = odm_dm_init(phydm);
-+
-+#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
-+	phydm_pathb_q_matrix_rotate_en(phydm);
-+#endif
-+}
-+
-+bool rtw_phydm_set_crystal_cap(_adapter *adapter, u8 crystal_cap)
-+{
-+	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA(adapter);
-+	struct dm_struct	*phydm = &(hal_data->odmpriv);
-+
-+	return phydm_set_crystal_cap_reg(phydm, crystal_cap);
-+}
-+
-+#ifdef CONFIG_LPS_PG
-+/*
-+static void _lps_pg_state_update(_adapter *adapter)
-+{
-+	u8	is_in_lpspg = _FALSE;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct sta_priv *pstapriv = &adapter->stapriv;
-+	struct sta_info *psta = NULL;
-+
-+	if ((pwrpriv->lps_level == LPS_PG) && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) && (pwrpriv->rpwm <= PS_STATE_S2))
-+		is_in_lpspg = _TRUE;
-+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
-+
-+	if (psta)
-+		psta->cmn.ra_info.disable_ra = (is_in_lpspg) ? _TRUE : _FALSE;
-+}
-+*/
-+void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg)
-+{
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+	/*u8 rate_id;*/
-+
-+	if(sta == NULL) {
-+		RTW_ERR("%s sta is null\n", __func__);
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	if (in_lpspg) {
-+		sta->cmn.ra_info.disable_ra = _TRUE;
-+		sta->cmn.ra_info.disable_pt = _TRUE;
-+		/*TODO : DRV fix tx rate*/
-+		/*rate_id = phydm_get_rate_from_rssi_lv(phydm, sta->cmn.mac_id);*/
-+	} else {
-+		sta->cmn.ra_info.disable_ra = _FALSE;
-+		sta->cmn.ra_info.disable_pt = _FALSE;
-+	}
-+
-+	rtw_phydm_ra_registed(adapter, sta);
-+}
-+#endif
-+
-+/*#define DBG_PHYDM_STATE_CHK*/
-+
-+
-+static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter, u8 is_scaning, u8 ifs_linked)
-+{
-+	u8 rfk_allowed = _TRUE;
-+
-+	#ifdef CONFIG_SKIP_RFK_IN_DM
-+	rfk_allowed = _FALSE;
-+	if (0)
-+		RTW_ERR("[RFK-CHK] RF-K not allowed due to CONFIG_SKIP_RFK_IN_DM\n");
-+	return rfk_allowed;
-+	#endif
-+
-+	#ifdef CONFIG_MCC_MODE
-+	/*not in MCC State*/
-+	if (MCC_EN(adapter) && 
-+		rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
-+		rfk_allowed = _FALSE;
-+		if (0)
-+			RTW_INFO("[RFK-CHK] RF-K not allowed due to doing MCC\n");
-+		return rfk_allowed;
-+	}
-+	#endif
-+
-+	#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
-+
-+	#endif
-+
-+	if (ifs_linked) {
-+		if (is_scaning) {
-+			rfk_allowed = _FALSE;
-+			RTW_DBG("[RFK-CHK] RF-K not allowed due to ifaces under site-survey\n");
-+		}
-+		else {
-+			rfk_allowed = rtw_mi_stayin_union_ch_chk(adapter) ? _TRUE : _FALSE;
-+			if (rfk_allowed == _FALSE)
-+				RTW_ERR("[RFK-CHK] RF-K not allowed due to ld_iface not stayin union ch\n");
-+		}
-+	}
-+
-+	return rfk_allowed;
-+}
-+
-+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
-+static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter, u8 ifs_linked)
-+{
-+	u8 iqk_sgt = _FALSE;
-+
-+#if 0
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	if (ifs_linked && (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2))
-+		rst = _TRUE;
-+#else
-+	if (ifs_linked)
-+		iqk_sgt = _TRUE;
-+#endif
-+	return iqk_sgt;
-+}
-+#endif
-+
-+/*check the tx low rate while unlinked to any AP;for pwr tracking */
-+static u8 _rtw_phydm_pwr_tracking_rate_check(_adapter *adapter)
-+{
-+	int i;
-+	_adapter *iface;
-+	u8		if_tx_rate = 0xFF;
-+	u8		tx_rate = 0xFF;
-+	struct mlme_ext_priv	*pmlmeext = NULL;
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		pmlmeext = &(iface->mlmeextpriv);
-+		if ((iface) && rtw_is_adapter_up(iface)) {
-+#ifdef CONFIG_P2P
-+			if (!rtw_p2p_chk_role(&(iface)->wdinfo, P2P_ROLE_DISABLE))
-+				if_tx_rate = IEEE80211_OFDM_RATE_6MB;
-+			else
-+#endif
-+				if_tx_rate = pmlmeext->tx_rate;
-+
-+			if (if_tx_rate < tx_rate) {
-+				/*5G limit ofdm rate*/
-+				if (pHalData->current_channel > 14) {
-+					if (!IS_CCK_RATE(if_tx_rate))
-+						tx_rate = if_tx_rate;
-+				} else {
-+					tx_rate = if_tx_rate;
-+				}
-+			}
-+			RTW_DBG("%s i=%d if_tx_rate =0x%x\n", __func__, i, if_tx_rate);
-+		}
-+	}
-+
-+	/*suggest by RF James,unlinked setting ofdm rate*/
-+	if (tx_rate == 0xFF)
-+		tx_rate = IEEE80211_OFDM_RATE_6MB;
-+
-+	RTW_DBG("%s tx_low_rate (unlinked to any AP)=0x%x\n", __func__, tx_rate);
-+	return tx_rate;
-+}
-+
-+#ifdef CONFIG_DYNAMIC_SOML
-+void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size)
-+{
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+
-+	phydm_soml_bytes_acq(phydm, data_rate, size);
-+}
-+
-+void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
-+			u8 period, u8 delay)
-+{
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+
-+	phydm_adaptive_soml_para_set(phydm, train_num, intvl, period, delay);
-+	RTW_INFO("%s.\n", __func__);
-+}
-+
-+void rtw_dyn_soml_config(_adapter *adapter)
-+{
-+	RTW_INFO("%s.\n", __func__);
-+
-+	if (adapter->registrypriv.dyn_soml_en == 1) {
-+		/* Must after phydm_adaptive_soml_init() */
-+		rtw_hal_set_hwreg(adapter , HW_VAR_SET_SOML_PARAM , NULL);
-+		RTW_INFO("dyn_soml_en = 1\n");
-+	} else {
-+		if (adapter->registrypriv.dyn_soml_en == 2) {
-+			rtw_dyn_soml_para_set(adapter, 
-+				adapter->registrypriv.dyn_soml_train_num, 
-+				adapter->registrypriv.dyn_soml_interval, 
-+				adapter->registrypriv.dyn_soml_period,
-+				adapter->registrypriv.dyn_soml_delay);
-+			RTW_INFO("dyn_soml_en = 2\n");
-+			RTW_INFO("dyn_soml_en, param = %d, %d, %d, %d\n",
-+				adapter->registrypriv.dyn_soml_train_num,
-+				adapter->registrypriv.dyn_soml_interval, 
-+				adapter->registrypriv.dyn_soml_period,
-+				adapter->registrypriv.dyn_soml_delay);
-+		} else if (adapter->registrypriv.dyn_soml_en == 0) {
-+			RTW_INFO("dyn_soml_en = 0\n");
-+		} else
-+			RTW_ERR("%s, wrong setting: dyn_soml_en = %d\n", __func__,
-+				adapter->registrypriv.dyn_soml_en);
-+	}
-+}
-+#endif
-+
-+void rtw_phydm_set_rrsr(_adapter *adapter, u32 rrsr_value, bool write_rrsr)
-+{
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+	u32 temp_rrsr =0xFFFFFFFF;
-+
-+	if (adapter->registrypriv.set_rrsr_value != 0xFFFFFFFF)
-+		temp_rrsr = adapter->registrypriv.set_rrsr_value;
-+	else
-+		temp_rrsr = rrsr_value;
-+
-+	odm_cmn_info_update(phydm, ODM_CMNINFO_RRSR_VAL, temp_rrsr);
-+	if(write_rrsr)
-+		phydm_rrsr_set_register(phydm, temp_rrsr);
-+}
-+void rtw_phydm_dyn_rrsr_en(_adapter *adapter, bool en_rrsr)
-+{
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+
-+	phydm_rrsr_en(phydm, en_rrsr);
-+}
-+void rtw_phydm_read_efuse(_adapter *adapter)
-+{
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
-+	struct dm_struct *phydm = &(hal_data->odmpriv);
-+
-+	/*PHYDM API - thermal trim*/
-+	phydm_get_thermal_trim_offset(phydm);
-+	/*PHYDM API - power trim*/
-+	phydm_get_power_trim_offset(phydm);
-+}
-+
-+#ifdef CONFIG_LPS_PWR_TRACKING
-+void rtw_phydm_pwr_tracking_directly(_adapter *adapter)
-+{
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
-+	u8 rfk_forbidden = _TRUE;
-+	u8 is_linked = _FALSE;
-+
-+	if (rtw_mi_check_status(adapter, MI_ASSOC))
-+		is_linked = _TRUE;
-+
-+	rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, hal_data->bScanInProcess, is_linked) == _TRUE) ? _FALSE : _TRUE;
-+	halrf_cmn_info_set(&hal_data->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
-+
-+	odm_txpowertracking_direct_ce(&hal_data->odmpriv);
-+}
-+#endif
-+
-+void rtw_phydm_watchdog(_adapter *adapter, bool in_lps)
-+{
-+	u8	bLinked = _FALSE;
-+	u8	bsta_state = _FALSE;
-+	u8	bBtDisabled = _TRUE;
-+	u8	rfk_forbidden = _FALSE;
-+	#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
-+	u8	segment_iqk = _FALSE;
-+	#endif
-+	u8	tx_unlinked_low_rate = 0xFF;
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(adapter);
-+
-+	if (!rtw_is_hw_init_completed(adapter)) {
-+		RTW_DBG("%s skip due to hw_init_completed == FALSE\n", __func__);
-+		return;
-+	}
-+	if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_SURVEY))
-+		pHalData->bScanInProcess = _TRUE;
-+	else
-+		pHalData->bScanInProcess = _FALSE;
-+
-+	if (rtw_mi_check_status(adapter, MI_ASSOC)) {
-+		bLinked = _TRUE;
-+		if (rtw_mi_check_status(adapter, MI_STA_LINKED))
-+		bsta_state = _TRUE;
-+	}
-+
-+	odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked);
-+	odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state);
-+
-+	#ifdef CONFIG_BT_COEXIST
-+	bBtDisabled = rtw_btcoex_IsBtDisabled(adapter);
-+	odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED,
-+				(bBtDisabled == _TRUE) ? _FALSE : _TRUE);
-+	#else
-+	odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, _FALSE);
-+	#endif /* CONFIG_BT_COEXIST */
-+
-+	rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, pHalData->bScanInProcess, bLinked) == _TRUE) ? _FALSE : _TRUE;
-+	halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
-+
-+	#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
-+	segment_iqk = _rtw_phydm_iqk_segment_chk(adapter, bLinked);
-+	halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk);
-+	#endif
-+	#ifdef DBG_PHYDM_STATE_CHK
-+	RTW_INFO("%s rfk_forbidden = %s, segment_iqk = %s\n",
-+			__func__, (rfk_forbidden) ? "Y" : "N", (segment_iqk) ? "Y" : "N");
-+	#endif
-+
-+	if (bLinked == _FALSE) {
-+		tx_unlinked_low_rate = _rtw_phydm_pwr_tracking_rate_check(adapter);
-+		halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RATE_INDEX, tx_unlinked_low_rate);
-+	}
-+
-+	/*if (!rtw_mi_stayin_union_band_chk(adapter)) {
-+		#ifdef DBG_PHYDM_STATE_CHK
-+		RTW_ERR("Not stay in union band, skip phydm\n");
-+		#endif
-+		goto _exit;
-+	}*/
-+
-+	#ifdef CONFIG_TDMADIG
-+	rtw_phydm_tdmadig(adapter, TDMADIG_NON_INIT);
-+	#endif/*CONFIG_TDMADIG*/
-+
-+	if (in_lps)
-+		phydm_watchdog_lps(&pHalData->odmpriv);
-+	else
-+		phydm_watchdog(&pHalData->odmpriv);
-+
-+	#ifdef CONFIG_RTW_ACS
-+	rtw_acs_update_current_info(adapter);
-+	#endif
-+
-+	return;
-+}
-+
-+
-diff --git a/drivers/staging/rtl8723cs/hal/hal_dm.h b/drivers/staging/rtl8723cs/hal/hal_dm.h
-new file mode 100644
-index 000000000000..863ffb7be99c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_dm.h
-@@ -0,0 +1,121 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_DM_H__
-+#define __HAL_DM_H__
-+
-+#define adapter_to_phydm(adapter) (&(GET_HAL_DATA(adapter)->odmpriv))
-+#define dvobj_to_phydm(dvobj) adapter_to_phydm(dvobj_get_primary_adapter(dvobj))
-+#ifdef CONFIG_TDMADIG
-+void rtw_phydm_tdmadig(_adapter *adapter, u8 state);
-+#endif
-+void rtw_phydm_priv_init(_adapter *adapter);
-+void Init_ODM_ComInfo(_adapter *adapter);
-+void rtw_phydm_init(_adapter *adapter);
-+
-+void rtw_hal_turbo_edca(_adapter *adapter);
-+u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter);
-+
-+void GetHalODMVar(
-+	PADAPTER				Adapter,
-+	HAL_ODM_VARIABLE		eVariable,
-+	void						*pValue1,
-+	void						*pValue2);
-+void SetHalODMVar(
-+	PADAPTER				Adapter,
-+	HAL_ODM_VARIABLE		eVariable,
-+	void						*pValue1,
-+	BOOLEAN					bSet);
-+
-+void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta);
-+
-+#ifdef CONFIG_DYNAMIC_SOML
-+void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size);
-+void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
-+			u8 period, u8 delay);
-+void rtw_dyn_soml_config(_adapter *adapter);
-+#endif
-+void rtw_phydm_set_rrsr(_adapter *adapter, u32 rrsr_value, bool write_rrsr);
-+void rtw_phydm_dyn_rrsr_en(_adapter *adapter, bool en_rrsr);
-+void rtw_phydm_watchdog(_adapter *adapter, bool in_lps);
-+
-+void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter);
-+void dump_sta_info(void *sel, struct sta_info *psta);
-+void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta);
-+
-+void rtw_hal_phydm_cal_trigger(_adapter *adapter);
-+#ifdef CONFIG_DBG_RF_CAL
-+void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment);
-+void rtw_hal_lck_test(_adapter *adapter);
-+#endif
-+
-+s8 rtw_dm_get_min_rssi(_adapter *adapter);
-+s8 rtw_phydm_get_min_rssi(_adapter *adapter);
-+u8 rtw_phydm_get_cur_igi(_adapter *adapter);
-+bool rtw_phydm_get_edcca_flag(_adapter *adapter);
-+
-+
-+#ifdef CONFIG_LPS_LCLK_WD_TIMER
-+extern void phydm_rssi_monitor_check(void *p_dm_void);
-+
-+void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter);
-+void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter);
-+#endif
-+#ifdef CONFIG_TDMADIG
-+enum rtw_tdmadig_state{
-+	TDMADIG_INIT,
-+	TDMADIG_NON_INIT,
-+};
-+#endif
-+enum phy_cnt {
-+	FA_OFDM,
-+	FA_CCK,
-+	FA_TOTAL,
-+	CCA_OFDM,
-+	CCA_CCK,
-+	CCA_ALL,
-+	CRC32_OK_VHT,
-+	CRC32_OK_HT,
-+	CRC32_OK_LEGACY,
-+	CRC32_OK_CCK,
-+	CRC32_ERROR_VHT,
-+	CRC32_ERROR_HT,
-+	CRC32_ERROR_LEGACY,
-+	CRC32_ERROR_CCK,
-+};
-+u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt);
-+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1) \
-+	|| (RTL8723F_SUPPORT == 1))
-+void rtw_phydm_iqk_trigger(_adapter *adapter);
-+#endif
-+void rtw_phydm_read_efuse(_adapter *adapter);
-+bool rtw_phydm_set_crystal_cap(_adapter *adapter, u8 crystal_cap);
-+
-+#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
-+void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id);
-+#endif
-+
-+#ifdef CONFIG_LPS_PG
-+void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg);
-+#endif
-+#ifdef CONFIG_LPS_PWR_TRACKING
-+void rtw_phydm_pwr_tracking_directly(_adapter *adapter);
-+#endif
-+
-+#ifdef CONFIG_CTRL_TXSS_BY_TP
-+void rtw_phydm_trx_cfg(_adapter *adapter, bool tx_1ss);
-+#endif
-+u8 rtw_hal_runtime_trx_path_decision(_adapter *adapter);
-+bool rtw_phydm_rfe_ctrl_gpio(_adapter *adapter, u8 gpio_num);
-+#endif /* __HAL_DM_H__ */
-diff --git a/drivers/staging/rtl8723cs/hal/hal_dm_acs.c b/drivers/staging/rtl8723cs/hal/hal_dm_acs.c
-new file mode 100644
-index 000000000000..c6196127d0b1
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_dm_acs.c
-@@ -0,0 +1,577 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2014 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+
-+#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)
-+static void _rtw_bss_nums_count(_adapter *adapter, u8 *pbss_nums)
-+{
-+	struct mlme_priv	*pmlmepriv = &(adapter->mlmepriv);
-+	_queue *queue = &(pmlmepriv->scanned_queue);
-+	struct wlan_network *pnetwork = NULL;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+	_list	*plist, *phead;
-+	_irqL irqL;
-+	int chan_idx = -1;
-+
-+	if (pbss_nums == NULL) {
-+		RTW_ERR("%s pbss_nums is null pointer\n", __func__);
-+		return;
-+	}
-+	_rtw_memset(pbss_nums, 0, MAX_CHANNEL_NUM);
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+		if (!pnetwork)
-+			break;
-+		chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), pnetwork->network.Configuration.DSConfig);
-+		if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
-+			RTW_ERR("%s can't get chan_idx(CH:%d)\n",
-+				__func__, pnetwork->network.Configuration.DSConfig);
-+			chan_idx = 0;
-+		}
-+		/*if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ)*/
-+
-+		pbss_nums[chan_idx]++;
-+
-+		plist = get_next(plist);
-+	}
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+}
-+
-+u8 rtw_get_ch_num_by_idx(_adapter *adapter, u8 idx)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	RT_CHANNEL_INFO *pch_set = rfctl->channel_set;
-+	u8 max_chan_nums = rfctl->max_chan_nums;
-+
-+	if (idx >= max_chan_nums)
-+		return 0;
-+	return pch_set[idx].ChannelNum;
-+}
-+#endif /*defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)*/
-+
-+
-+#ifdef CONFIG_RTW_ACS
-+void rtw_acs_version_dump(void *sel, _adapter *adapter)
-+{
-+	_RTW_PRINT_SEL(sel, "RTK_ACS VER_%d\n", RTK_ACS_VERSION);
-+}
-+u8 rtw_phydm_clm_ratio(_adapter *adapter)
-+{
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+
-+	return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CLM_RATIO);
-+}
-+u8 rtw_phydm_nhm_ratio(_adapter *adapter)
-+{
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+
-+	return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_NHM_ENV_RATIO);
-+}
-+
-+u8 rtw_phydm_nhm_noise_pwr(_adapter *adapter)
-+{
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+
-+	return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_NHM_PWR);
-+}
-+
-+void rtw_acs_reset(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct auto_chan_sel *pacs = &hal_data->acs;
-+
-+	_rtw_memset(pacs, 0, sizeof(struct auto_chan_sel));
-+	#ifdef CONFIG_RTW_ACS_DBG
-+	rtw_acs_adv_reset(adapter);
-+	#endif /*CONFIG_RTW_ACS_DBG*/
-+}
-+
-+#ifdef CONFIG_RTW_ACS_DBG
-+u8 rtw_is_acs_igi_valid(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct auto_chan_sel *pacs = &hal_data->acs;
-+
-+	if ((pacs->igi) && ((pacs->igi >= 0x1E) || (pacs->igi < 0x60)))
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct auto_chan_sel *pacs = &hal_data->acs;
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
-+
-+	pacs->scan_type = scan_type;
-+	pacs->scan_time = scan_time;
-+	pacs->igi = igi;
-+	pacs->bw = bw;
-+	RTW_INFO("[ACS] ADV setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n",
-+		pacs->scan_type ? 'A' : 'P', pacs->scan_time, pacs->igi, pacs->bw);
-+}
-+void rtw_acs_adv_reset(_adapter *adapter)
-+{
-+	rtw_acs_adv_setting(adapter, SCAN_ACTIVE, 0, 0, 0);
-+}
-+#endif /*CONFIG_RTW_ACS_DBG*/
-+
-+void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+#if (RTK_ACS_VERSION == 3)
-+	struct clm_para_info clm_para;
-+	struct nhm_para_info nhm_para;
-+	struct env_trig_rpt trig_rpt;
-+
-+	scan_time_ms -= 10;
-+
-+	init_acs_clm(clm_para, scan_time_ms);
-+
-+	if (pid == NHM_PID_IEEE_11K_HIGH)
-+		init_11K_high_nhm(nhm_para, scan_time_ms);
-+	else if (pid == NHM_PID_IEEE_11K_LOW)
-+		init_11K_low_nhm(nhm_para, scan_time_ms);
-+	else
-+		init_acs_nhm(nhm_para, scan_time_ms);
-+
-+	hal_data->acs.trig_rst = phydm_env_mntr_trigger(phydm, &nhm_para, &clm_para, &trig_rpt);
-+	if (hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS)) {
-+		hal_data->acs.trig_rpt.clm_rpt_stamp = trig_rpt.clm_rpt_stamp;
-+		hal_data->acs.trig_rpt.nhm_rpt_stamp = trig_rpt.nhm_rpt_stamp;
-+		/*RTW_INFO("[ACS] trigger success (rst = 0x%02x, clm_stamp:%d, nhm_stamp:%d)\n",
-+			hal_data->acs.trig_rst, hal_data->acs.trig_rpt.clm_rpt_stamp, hal_data->acs.trig_rpt.nhm_rpt_stamp);*/
-+	} else
-+		RTW_ERR("[ACS] trigger failed (rst = 0x%02x)\n", hal_data->acs.trig_rst);
-+#else
-+	phydm_ccx_monitor_trigger(phydm, scan_time_ms);
-+#endif
-+
-+	hal_data->acs.trigger_ch = scan_chan;
-+	hal_data->acs.triggered = _TRUE;
-+
-+	#ifdef CONFIG_RTW_ACS_DBG
-+	RTW_INFO("[ACS] Trigger CH:%d, Times:%d\n", hal_data->acs.trigger_ch, scan_time_ms);
-+	#endif
-+}
-+void rtw_acs_get_rst(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+	int chan_idx = -1;
-+	u8 cur_chan = hal_data->acs.trigger_ch;
-+
-+	if (cur_chan == 0)
-+		return;
-+
-+	if (!hal_data->acs.triggered)
-+		return;
-+
-+	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), cur_chan);
-+	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
-+		RTW_ERR("[ACS] %s can't get chan_idx(CH:%d)\n", __func__, cur_chan);
-+		return;
-+	}
-+#if (RTK_ACS_VERSION == 3)
-+	if (!(hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS))) {
-+		RTW_ERR("[ACS] get_rst return, due to acs trigger failed\n");
-+		return;
-+	}
-+
-+	{
-+		struct env_mntr_rpt rpt = {0};
-+		u8 rst;
-+
-+		rst = phydm_env_mntr_result(phydm, &rpt);
-+		if ((rst == (NHM_SUCCESS | CLM_SUCCESS)) &&
-+			(rpt.clm_rpt_stamp == hal_data->acs.trig_rpt.clm_rpt_stamp) &&
-+			(rpt.nhm_rpt_stamp == hal_data->acs.trig_rpt.nhm_rpt_stamp)){
-+			hal_data->acs.clm_ratio[chan_idx] = rpt.clm_ratio;
-+			hal_data->acs.nhm_ratio[chan_idx] =  rpt.nhm_env_ratio;
-+			hal_data->acs.env_mntr_rpt[chan_idx] = (rpt.nhm_noise_pwr -100);
-+			_rtw_memcpy(&hal_data->acs.nhm[chan_idx][0], rpt.nhm_result, NHM_RPT_NUM);
-+
-+			/*RTW_INFO("[ACS] get_rst success (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n",
-+			rst,
-+			hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp,
-+			hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);*/
-+		} else {
-+			RTW_ERR("[ACS] get_rst failed (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n",
-+			rst,
-+			hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp,
-+			hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);
-+		}
-+	}
-+
-+#else
-+	phydm_ccx_monitor_result(phydm);
-+
-+	hal_data->acs.clm_ratio[chan_idx] = rtw_phydm_clm_ratio(adapter);
-+	hal_data->acs.nhm_ratio[chan_idx] = rtw_phydm_nhm_ratio(adapter);
-+#endif
-+	hal_data->acs.triggered = _FALSE;
-+	#ifdef CONFIG_RTW_ACS_DBG
-+	RTW_INFO("[ACS] Result CH:%d, CLM:%d NHM:%d\n",
-+		cur_chan, hal_data->acs.clm_ratio[chan_idx], hal_data->acs.nhm_ratio[chan_idx]);
-+	RTW_INFO("[ACS] Result NHM(dBm):%d\n",
-+		hal_data->acs.env_mntr_rpt[chan_idx] );
-+	#endif
-+}
-+
-+void _rtw_phydm_acs_select_best_chan(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	u8 ch_idx;
-+	u8 ch_idx_24g = 0xFF, ch_idx_5g = 0xFF;
-+	u8 min_itf_24g = 0xFF,  min_itf_5g = 0xFF;
-+	u8 *pbss_nums = hal_data->acs.bss_nums;
-+	u8 *pclm_ratio = hal_data->acs.clm_ratio;
-+	u8 *pnhm_ratio = hal_data->acs.nhm_ratio;
-+	u8 *pinterference_time = hal_data->acs.interference_time;
-+	u8 max_chan_nums = rfctl->max_chan_nums;
-+
-+	for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
-+		if (pbss_nums[ch_idx])
-+			pinterference_time[ch_idx] = (pclm_ratio[ch_idx] / 2) + (pnhm_ratio[ch_idx] / 2);
-+		else
-+			pinterference_time[ch_idx] = (pclm_ratio[ch_idx] / 3) + ((pnhm_ratio[ch_idx] * 2) / 3);
-+
-+		if (rtw_get_ch_num_by_idx(adapter, ch_idx) < 14) {
-+			if (pinterference_time[ch_idx] < min_itf_24g) {
-+				min_itf_24g = pinterference_time[ch_idx];
-+				ch_idx_24g = ch_idx;
-+			}
-+		} else {
-+			if (pinterference_time[ch_idx] < min_itf_5g) {
-+				min_itf_5g = pinterference_time[ch_idx];
-+				ch_idx_5g = ch_idx;
-+			}
-+		}
-+	}
-+	if (ch_idx_24g != 0xFF)
-+		hal_data->acs.best_chan_24g = rtw_get_ch_num_by_idx(adapter, ch_idx_24g);
-+
-+	if (ch_idx_5g != 0xFF)
-+		hal_data->acs.best_chan_5g = rtw_get_ch_num_by_idx(adapter, ch_idx_5g);
-+
-+	hal_data->acs.trigger_ch = 0;
-+}
-+
-+void rtw_acs_info_dump(void *sel, _adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	u8 max_chan_nums = rfctl->max_chan_nums;
-+	u8 ch_idx, ch_num;
-+
-+	_RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION);
-+	_RTW_PRINT_SEL(sel, "Best 24G Channel:%d\n", hal_data->acs.best_chan_24g);
-+	_RTW_PRINT_SEL(sel, "Best 5G Channel:%d\n\n", hal_data->acs.best_chan_5g);
-+
-+	#ifdef CONFIG_RTW_ACS_DBG
-+	_RTW_PRINT_SEL(sel, "Advanced setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n",
-+		hal_data->acs.scan_type ? 'A' : 'P', hal_data->acs.scan_time, hal_data->acs.igi, hal_data->acs.bw);
-+
-+	_RTW_PRINT_SEL(sel, "BW  20MHz\n");
-+	_RTW_PRINT_SEL(sel, "%5s  %3s  %3s  %3s(%%)  %3s(%%)  %3s\n",
-+						"Index", "CH", "BSS", "CLM", "NHM", "ITF");
-+
-+	for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
-+		ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
-+		_RTW_PRINT_SEL(sel, "%5d  %3d  %3d  %6d  %6d  %3d\n",
-+						ch_idx, ch_num, hal_data->acs.bss_nums[ch_idx],
-+						hal_data->acs.clm_ratio[ch_idx],
-+						hal_data->acs.nhm_ratio[ch_idx],
-+						hal_data->acs.interference_time[ch_idx]);
-+	}
-+	#endif
-+}
-+void rtw_acs_select_best_chan(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+	_rtw_bss_nums_count(adapter, hal_data->acs.bss_nums);
-+	_rtw_phydm_acs_select_best_chan(adapter);
-+	rtw_acs_info_dump(RTW_DBGDUMP, adapter);
-+}
-+
-+void rtw_acs_start(_adapter *adapter)
-+{
-+	rtw_acs_reset(adapter);
-+	if (GET_ACS_STATE(adapter) != ACS_ENABLE)
-+		SET_ACS_STATE(adapter, ACS_ENABLE);
-+}
-+void rtw_acs_stop(_adapter *adapter)
-+{
-+	SET_ACS_STATE(adapter, ACS_DISABLE);
-+}
-+
-+
-+u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	int chan_idx = -1;
-+
-+	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
-+	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
-+		RTW_ERR("[ACS] Get CLM fail, can't get chan_idx(CH:%d)\n", chan);
-+		return 0;
-+	}
-+
-+	return hal_data->acs.clm_ratio[chan_idx];
-+}
-+u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+	if (ch_idx >= MAX_CHANNEL_NUM) {
-+		RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx);
-+		return 0;
-+	}
-+
-+	return hal_data->acs.clm_ratio[ch_idx];
-+}
-+u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	int chan_idx = -1;
-+
-+	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
-+	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
-+		RTW_ERR("[ACS] Get NHM fail, can't get chan_idx(CH:%d)\n", chan);
-+		return 0;
-+	}
-+
-+	return hal_data->acs.nhm_ratio[chan_idx];
-+}
-+u8 rtw_acs_get_nhm_noise_pwr_by_ch_idx(_adapter *adapter, u8 ch_idx)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+	if (ch_idx >= MAX_CHANNEL_NUM) {
-+		RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx);
-+		return 0;
-+	}
-+
-+	return hal_data->acs.env_mntr_rpt[ch_idx];
-+}
-+
-+u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+	if (ch_idx >= MAX_CHANNEL_NUM) {
-+		RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx);
-+		return 0;
-+	}
-+
-+	return hal_data->acs.nhm_ratio[ch_idx];
-+}
-+void rtw_acs_chan_info_dump(void *sel, _adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	u8 max_chan_nums = rfctl->max_chan_nums;
-+	u8 ch_idx, ch_num;
-+	u8 utilization;
-+
-+	_RTW_PRINT_SEL(sel, "BW  20MHz\n");
-+	_RTW_PRINT_SEL(sel, "%5s  %3s  %7s(%%)  %12s(%%)  %11s(%%)  %9s(%%)  %8s(%%)\n",
-+						"Index", "CH", "Quality", "Availability", "Utilization",
-+						"WIFI Util", "Interference Util");
-+
-+	for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
-+		ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
-+		utilization = hal_data->acs.clm_ratio[ch_idx] + hal_data->acs.nhm_ratio[ch_idx];
-+		_RTW_PRINT_SEL(sel, "%5d  %3d  %7d   %12d   %12d   %12d   %12d\n",
-+						ch_idx, ch_num,
-+						(100-hal_data->acs.interference_time[ch_idx]),
-+						(100-utilization),
-+						utilization,
-+						hal_data->acs.clm_ratio[ch_idx],
-+						hal_data->acs.nhm_ratio[ch_idx]);
-+	}
-+}
-+void rtw_acs_current_info_dump(void *sel, _adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u8 ch, cen_ch, bw, offset;
-+
-+	_RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION);
-+
-+	ch = rtw_get_oper_ch(adapter);
-+	bw = rtw_get_oper_bw(adapter);
-+	offset = rtw_get_oper_choffset(adapter);
-+
-+	_RTW_PRINT_SEL(sel, "Current Channel:%d\n", ch);
-+	if ((bw == CHANNEL_WIDTH_80) ||(bw == CHANNEL_WIDTH_40)) {
-+		cen_ch = rtw_get_center_ch(ch, bw, offset);
-+		_RTW_PRINT_SEL(sel, "Center Channel:%d\n", cen_ch);
-+	}
-+
-+	_RTW_PRINT_SEL(sel, "Current BW %s\n", ch_width_str(bw));
-+	if (0)
-+		_RTW_PRINT_SEL(sel, "Current IGI 0x%02x\n", rtw_phydm_get_cur_igi(adapter));
-+	_RTW_PRINT_SEL(sel, "CLM:%d, NHM:%d\n\n",
-+		hal_data->acs.cur_ch_clm_ratio, hal_data->acs.cur_ch_nhm_ratio);
-+}
-+
-+void rtw_acs_update_current_info(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+	hal_data->acs.cur_ch_clm_ratio = rtw_phydm_clm_ratio(adapter);
-+	hal_data->acs.cur_ch_nhm_ratio = rtw_phydm_nhm_ratio(adapter);
-+
-+	#ifdef CONFIG_RTW_ACS_DBG
-+	rtw_acs_current_info_dump(RTW_DBGDUMP, adapter);
-+	#endif
-+}
-+#endif /*CONFIG_RTW_ACS*/
-+
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+void rtw_noise_monitor_version_dump(void *sel, _adapter *adapter)
-+{
-+	_RTW_PRINT_SEL(sel, "RTK_NOISE_MONITOR VER_%d\n", RTK_NOISE_MONITOR_VERSION);
-+}
-+void rtw_nm_enable(_adapter *adapter)
-+{
-+	SET_NM_STATE(adapter, NM_ENABLE);
-+}
-+void rtw_nm_disable(_adapter *adapter)
-+{
-+	SET_NM_STATE(adapter, NM_DISABLE);
-+}
-+void rtw_noise_info_dump(void *sel, _adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	u8 max_chan_nums = rfctl->max_chan_nums;
-+	u8 ch_idx, ch_num;
-+
-+	_RTW_PRINT_SEL(sel, "========== NM (VER-%d) ==========\n", RTK_NOISE_MONITOR_VERSION);
-+
-+	_RTW_PRINT_SEL(sel, "%5s  %3s  %3s  %10s", "Index", "CH", "BSS", "Noise(dBm)\n");
-+
-+	_rtw_bss_nums_count(adapter, hal_data->nm.bss_nums);
-+
-+	for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
-+		ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
-+		_RTW_PRINT_SEL(sel, "%5d  %3d  %3d  %10d\n",
-+						ch_idx, ch_num, hal_data->nm.bss_nums[ch_idx],
-+						hal_data->nm.noise[ch_idx]);
-+	}
-+}
-+
-+void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct dm_struct *phydm = &hal_data->odmpriv;
-+	int chan_idx = -1;
-+	s16 noise = 0;
-+
-+	#ifdef DBG_NOISE_MONITOR
-+	RTW_INFO("[NM] chan(%d)-PauseDIG:%s,  IGIValue:0x%02x, max_time:%d (ms)\n",
-+		chan, (is_pause_dig) ? "Y" : "N", igi_value, max_time);
-+	#endif
-+
-+	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
-+	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
-+		RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan);
-+		return;
-+	}
-+	noise = odm_inband_noise_monitor(phydm, is_pause_dig, igi_value, max_time); /*dBm*/
-+
-+	hal_data->nm.noise[chan_idx] = noise;
-+
-+	#ifdef DBG_NOISE_MONITOR
-+	RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, hal_data->nm.noise[chan_idx]);
-+
-+	RTW_INFO("[NM] noise_a = %d, noise_b = %d  noise_all:%d\n",
-+			 phydm->noise_level.noise[RF_PATH_A],
-+			 phydm->noise_level.noise[RF_PATH_B],
-+			 phydm->noise_level.noise_all);
-+	#endif /*DBG_NOISE_MONITOR*/
-+}
-+
-+s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	s16 noise = 0;
-+	int chan_idx = -1;
-+
-+	chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
-+	if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
-+		RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan);
-+		return noise;
-+	}
-+	noise = hal_data->nm.noise[chan_idx];
-+
-+	#ifdef DBG_NOISE_MONITOR
-+	RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, noise);
-+	#endif/*DBG_NOISE_MONITOR*/
-+	return noise;
-+}
-+s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	s16 noise = 0;
-+
-+	if (ch_idx >= MAX_CHANNEL_NUM) {
-+		RTW_ERR("[NM] %s ch_idx(%d) is invalid\n", __func__, ch_idx);
-+		return noise;
-+	}
-+	noise = hal_data->nm.noise[ch_idx];
-+
-+	#ifdef DBG_NOISE_MONITOR
-+	RTW_INFO("[NM] %s ch_idx %d, noise = %d (dBm)\n", __func__, ch_idx, noise);
-+	#endif/*DBG_NOISE_MONITOR*/
-+	return noise;
-+}
-+
-+s16 rtw_noise_measure_curchan(_adapter *padapter)
-+{
-+	s16 noise = 0;
-+	u8 igi_value = 0x1E;
-+	u32 max_time = 100;/* ms */
-+	u8 is_pause_dig = _TRUE;
-+	u8 cur_chan = rtw_get_oper_ch(padapter);
-+
-+	if (rtw_linked_check(padapter) == _FALSE)
-+		return noise;
-+
-+	rtw_ps_deny(padapter, PS_DENY_IOCTL);
-+	LeaveAllPowerSaveModeDirect(padapter);
-+	rtw_noise_measure(padapter, cur_chan, is_pause_dig, igi_value, max_time);
-+	noise = rtw_noise_query_by_chan_num(padapter, cur_chan);
-+	rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
-+
-+	return noise;
-+}
-+#endif /*CONFIG_BACKGROUND_NOISE_MONITOR*/
-+
-diff --git a/drivers/staging/rtl8723cs/hal/hal_dm_acs.h b/drivers/staging/rtl8723cs/hal/hal_dm_acs.h
-new file mode 100644
-index 000000000000..ba6e136bd524
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_dm_acs.h
-@@ -0,0 +1,173 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_DM_ACS_H__
-+#define __HAL_DM_ACS_H__
-+#ifdef CONFIG_RTW_ACS
-+#define RTK_ACS_VERSION	3
-+
-+#if (RTK_ACS_VERSION == 3)
-+enum NHM_PID {
-+	NHM_PID_ACS,
-+	NHM_PID_IEEE_11K_HIGH,
-+	NHM_PID_IEEE_11K_LOW,
-+};
-+
-+#define init_clm_param(clm, app, lv, time) \
-+	do {\
-+		clm.clm_app = app;\
-+		clm.clm_lv = lv;\
-+		clm.mntr_time = time;\
-+	} while (0)
-+
-+#define init_nhm_param(nhm, txon, cca, cnt_opt, app, lv, time) \
-+	do {\
-+		nhm.incld_txon = txon;\
-+		nhm.incld_cca = cca;\
-+		nhm.div_opt = cnt_opt;\
-+		nhm.nhm_app = app;\
-+		nhm.nhm_lv = lv;\
-+		nhm.mntr_time = time;\
-+	} while (0)
-+
-+	
-+#define init_acs_clm(clm, time) \
-+	init_clm_param(clm, CLM_ACS, CLM_LV_2, time)
-+
-+#define init_acs_nhm(nhm, time) \
-+	init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, NHM_ACS, NHM_LV_2, time)
-+
-+#define init_11K_high_nhm(nhm, time) \
-+	init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_HIGH, NHM_LV_2, time)
-+	
-+#define init_11K_low_nhm(nhm, time) \
-+		init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_LOW, NHM_LV_2, time)
-+
-+
-+#endif /*(RTK_ACS_VERSION == 3)*/
-+void rtw_acs_version_dump(void *sel, _adapter *adapter);
-+extern void phydm_ccx_monitor_trigger(void *p_dm_void, u16 monitor_time);
-+extern void phydm_ccx_monitor_result(void *p_dm_void);
-+
-+#define GET_ACS_STATE(padapter)					(ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state))
-+#define SET_ACS_STATE(padapter, set_state)			(ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state))
-+#define IS_ACS_ENABLE(padapter)					((GET_ACS_STATE(padapter) == ACS_ENABLE) ? _TRUE : _FALSE)
-+
-+enum ACS_STATE {
-+	ACS_DISABLE,
-+	ACS_ENABLE,
-+};
-+
-+#define ACS_BW_20M	BIT(0)
-+#define ACS_BW_40M	BIT(1)
-+#define ACS_BW_80M	BIT(2)
-+#define ACS_BW_160M	BIT(3)
-+
-+struct auto_chan_sel {
-+	ATOMIC_T state;
-+	u8 trigger_ch;
-+	bool triggered;
-+	u8 clm_ratio[MAX_CHANNEL_NUM];
-+	u8 nhm_ratio[MAX_CHANNEL_NUM];
-+	s8 env_mntr_rpt[MAX_CHANNEL_NUM];
-+	#if (RTK_ACS_VERSION == 3)
-+	u8 nhm[MAX_CHANNEL_NUM][NHM_RPT_NUM];
-+	#endif
-+	u8 bss_nums[MAX_CHANNEL_NUM];
-+	u8 interference_time[MAX_CHANNEL_NUM];
-+	u8 cur_ch_clm_ratio;
-+	u8 cur_ch_nhm_ratio;
-+	u8 best_chan_5g;
-+	u8 best_chan_24g;
-+
-+	#if (RTK_ACS_VERSION == 3)
-+	u8 trig_rst;
-+	struct env_trig_rpt	trig_rpt;
-+	#endif
-+
-+	#ifdef CONFIG_RTW_ACS_DBG
-+	RT_SCAN_TYPE scan_type;
-+	u16 scan_time;
-+	u8 igi;
-+	u8 bw;
-+	#endif
-+};
-+
-+#define rtw_acs_get_best_chan_24g(adapter)		(GET_HAL_DATA(adapter)->acs.best_chan_24g)
-+#define rtw_acs_get_best_chan_5g(adapter)		(GET_HAL_DATA(adapter)->acs.best_chan_5g)
-+
-+#ifdef CONFIG_RTW_ACS_DBG
-+#define rtw_is_acs_passiv_scan(adapter)	(((GET_HAL_DATA(adapter)->acs.scan_type) == SCAN_PASSIVE) ? _TRUE : _FALSE)
-+
-+#define rtw_acs_get_adv_st(adapter)	(GET_HAL_DATA(adapter)->acs.scan_time)
-+#define rtw_is_acs_st_valid(adapter)	((GET_HAL_DATA(adapter)->acs.scan_time) ? _TRUE : _FALSE)
-+
-+#define rtw_acs_get_adv_igi(adapter)	(GET_HAL_DATA(adapter)->acs.igi)
-+u8 rtw_is_acs_igi_valid(_adapter *adapter);
-+
-+#define rtw_acs_get_adv_bw(adapter)	(GET_HAL_DATA(adapter)->acs.bw)
-+
-+void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw);
-+void rtw_acs_adv_reset(_adapter *adapter);
-+#endif
-+
-+u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan);
-+u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx);
-+u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan);
-+u8 rtw_acs_get_nhm_noise_pwr_by_ch_idx(_adapter *adapter, u8 ch_idx);
-+u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx);
-+
-+u8 rtw_phydm_clm_ratio(_adapter *adapter);
-+u8 rtw_phydm_nhm_ratio(_adapter *adapter);
-+u8 rtw_phydm_nhm_noise_pwr(_adapter *adapter);
-+
-+void rtw_acs_reset(_adapter *adapter);
-+void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid);
-+void rtw_acs_get_rst(_adapter *adapter);
-+void rtw_acs_select_best_chan(_adapter *adapter);
-+void rtw_acs_info_dump(void *sel, _adapter *adapter);
-+void rtw_acs_update_current_info(_adapter *adapter);
-+void rtw_acs_chan_info_dump(void *sel, _adapter *adapter);
-+void rtw_acs_current_info_dump(void *sel, _adapter *adapter);
-+
-+void rtw_acs_start(_adapter *adapter);
-+void rtw_acs_stop(_adapter *adapter);
-+
-+#endif /*CONFIG_RTW_ACS*/
-+
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+#define RTK_NOISE_MONITOR_VERSION	3
-+#define GET_NM_STATE(padapter)					(ATOMIC_READ(&GET_HAL_DATA(padapter)->nm.state))
-+#define SET_NM_STATE(padapter, set_state)			(ATOMIC_SET(&GET_HAL_DATA(padapter)->nm.state, set_state))
-+#define IS_NM_ENABLE(padapter)					((GET_NM_STATE(padapter) == NM_ENABLE) ? _TRUE : _FALSE)
-+
-+enum NM_STATE {
-+	NM_DISABLE,
-+	NM_ENABLE,
-+};
-+
-+struct noise_monitor {
-+	ATOMIC_T state;
-+	s16 noise[MAX_CHANNEL_NUM];
-+	u8 bss_nums[MAX_CHANNEL_NUM];
-+};
-+void rtw_nm_enable(_adapter *adapter);
-+void rtw_nm_disable(_adapter *adapter);
-+void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time);
-+s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan);
-+s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx);
-+s16 rtw_noise_measure_curchan(_adapter *padapter);
-+void rtw_noise_info_dump(void *sel, _adapter *adapter);
-+#endif
-+#endif /* __HAL_DM_ACS_H__ */
-diff --git a/drivers/staging/rtl8723cs/hal/hal_halmac.c b/drivers/staging/rtl8723cs/hal/hal_halmac.c
-new file mode 100644
-index 000000000000..aa1bbf90d9e9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_halmac.c
-@@ -0,0 +1,5927 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _HAL_HALMAC_C_
-+
-+#include <drv_types.h>		/* PADAPTER, struct dvobj_priv, SDIO_ERR_VAL8 and etc. */
-+#include <hal_data.h>		/* efuse, PHAL_DATA_TYPE and etc. */
-+#include "hal_halmac.h"		/* dvobj_to_halmac() and ect. */
-+
-+/*
-+ * HALMAC take return value 0 for fail and 1 for success to replace
-+ * _FALSE/_TRUE after V1_04_09
-+ */
-+#define RTW_HALMAC_FAIL			0
-+#define RTW_HALMAC_SUCCESS		1
-+
-+#define DEFAULT_INDICATOR_TIMELMT	1000	/* ms */
-+#define MSG_PREFIX			"[HALMAC]"
-+
-+#define RTW_HALMAC_DLFW_MEM_NO_STOP_TX
-+#define RTW_HALMAC_FILTER_DRV_C2H	/* Block C2H owner=driver */
-+
-+/*
-+ * Driver API for HALMAC operations
-+ */
-+
-+#ifdef CONFIG_SDIO_HCI
-+#include <rtw_sdio.h>
-+
-+static u8 _halmac_mac_reg_page0_chk(const char *func, struct dvobj_priv *dvobj, u32 offset)
-+{
-+#if defined(CONFIG_IO_CHECK_IN_ANA_LOW_CLK) && defined(CONFIG_LPS_LCLK)
-+	struct pwrctrl_priv *pwrpriv = &dvobj->pwrctl_priv;
-+	u32 mac_reg_offset = 0;
-+
-+	if (pwrpriv->pwr_mode == PS_MODE_ACTIVE)
-+		return _TRUE;
-+
-+	if (pwrpriv->lps_level == LPS_NORMAL)
-+		return _TRUE;
-+
-+	if (pwrpriv->rpwm >= PS_STATE_S2)
-+		return _TRUE;
-+
-+	if (offset & (WLAN_IOREG_DEVICE_ID << 13))  { /*WLAN_IOREG_OFFSET*/
-+		mac_reg_offset = offset & HALMAC_WLAN_MAC_REG_MSK;
-+		if (mac_reg_offset < 0x100) {
-+			RTW_ERR(FUNC_ADPT_FMT
-+				"access MAC REG -0x%04x in PS-mode:0x%02x (rpwm:0x%02x, lps_level:0x%02x)\n",
-+				FUNC_ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mac_reg_offset,
-+				pwrpriv->pwr_mode, pwrpriv->rpwm, pwrpriv->lps_level);
-+			rtw_warn_on(1);
-+			return _FALSE;
-+		}
-+	}
-+#endif
-+	return _TRUE;
-+}
-+
-+static u8 _halmac_sdio_cmd52_read(void *p, u32 offset)
-+{
-+	struct dvobj_priv *d;
-+	u8 val;
-+	u8 ret;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	_halmac_mac_reg_page0_chk(__func__, d, offset);
-+	ret = rtw_sdio_read_cmd52(d, offset, &val, 1);
-+	if (_FAIL == ret) {
-+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
-+		return SDIO_ERR_VAL8;
-+	}
-+
-+	return val;
-+}
-+
-+static void _halmac_sdio_cmd52_write(void *p, u32 offset, u8 val)
-+{
-+	struct dvobj_priv *d;
-+	u8 ret;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	_halmac_mac_reg_page0_chk(__func__, d, offset);
-+	ret = rtw_sdio_write_cmd52(d, offset, &val, 1);
-+	if (_FAIL == ret)
-+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
-+}
-+
-+static u8 _halmac_sdio_reg_read_8(void *p, u32 offset)
-+{
-+	struct dvobj_priv *d;
-+	u8 *pbuf;
-+	u8 val;
-+	u8 ret;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	val = SDIO_ERR_VAL8;
-+	_halmac_mac_reg_page0_chk(__func__, d, offset);
-+	pbuf = rtw_zmalloc(1);
-+	if (!pbuf)
-+		return val;
-+
-+	ret = rtw_sdio_read_cmd53(d, offset, pbuf, 1);
-+	if (ret == _FAIL) {
-+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
-+		goto exit;
-+	}
-+
-+	val = *pbuf;
-+
-+exit:
-+	rtw_mfree(pbuf, 1);
-+
-+	return val;
-+}
-+
-+static u16 _halmac_sdio_reg_read_16(void *p, u32 offset)
-+{
-+	struct dvobj_priv *d;
-+	u8 *pbuf;
-+	u16 val;
-+	u8 ret;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	val = SDIO_ERR_VAL16;
-+	_halmac_mac_reg_page0_chk(__func__, d, offset);
-+	pbuf = rtw_zmalloc(2);
-+	if (!pbuf)
-+		return val;
-+
-+	ret = rtw_sdio_read_cmd53(d, offset, pbuf, 2);
-+	if (ret == _FAIL) {
-+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
-+		goto exit;
-+	}
-+
-+	val = le16_to_cpu(*(u16 *)pbuf);
-+
-+exit:
-+	rtw_mfree(pbuf, 2);
-+
-+	return val;
-+}
-+
-+static u32 _halmac_sdio_reg_read_32(void *p, u32 offset)
-+{
-+	struct dvobj_priv *d;
-+	u8 *pbuf;
-+	u32 val;
-+	u8 ret;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	val = SDIO_ERR_VAL32;
-+	_halmac_mac_reg_page0_chk(__func__, d, offset);
-+	pbuf = rtw_zmalloc(4);
-+	if (!pbuf)
-+		return val;
-+
-+	ret = rtw_sdio_read_cmd53(d, offset, pbuf, 4);
-+	if (ret == _FAIL) {
-+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
-+		goto exit;
-+	}
-+
-+	val = le32_to_cpu(*(u32 *)pbuf);
-+
-+exit:
-+	rtw_mfree(pbuf, 4);
-+
-+	return val;
-+}
-+
-+static u8 _halmac_sdio_reg_read_n(void *p, u32 offset, u32 size, u8 *data)
-+{
-+	struct dvobj_priv *d = (struct dvobj_priv *)p;
-+	u8 *pbuf;
-+	u8 ret;
-+	u8 rst = RTW_HALMAC_FAIL;
-+	u32 sdio_read_size;
-+
-+
-+	if (!data)
-+		return rst;
-+
-+	sdio_read_size = RND4(size);
-+	sdio_read_size = rtw_sdio_cmd53_align_size(d, sdio_read_size);
-+
-+	pbuf = rtw_zmalloc(sdio_read_size);
-+	if (!pbuf)
-+		return rst;
-+
-+	ret = rtw_sdio_read_cmd53(d, offset, pbuf, sdio_read_size);
-+	if (ret == _FAIL) {
-+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
-+		goto exit;
-+	}
-+
-+	_rtw_memcpy(data, pbuf, size);
-+	rst = RTW_HALMAC_SUCCESS;
-+exit:
-+	rtw_mfree(pbuf, sdio_read_size);
-+
-+	return rst;
-+}
-+
-+static void _halmac_sdio_reg_write_8(void *p, u32 offset, u8 val)
-+{
-+	struct dvobj_priv *d;
-+	u8 *pbuf;
-+	u8 ret;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	_halmac_mac_reg_page0_chk(__func__, d, offset);
-+	pbuf = rtw_zmalloc(1);
-+	if (!pbuf)
-+		return;
-+	_rtw_memcpy(pbuf, &val, 1);
-+
-+	ret = rtw_sdio_write_cmd53(d, offset, pbuf, 1);
-+	if (ret == _FAIL)
-+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
-+
-+	rtw_mfree(pbuf, 1);
-+}
-+
-+static void _halmac_sdio_reg_write_16(void *p, u32 offset, u16 val)
-+{
-+	struct dvobj_priv *d;
-+	u8 *pbuf;
-+	u8 ret;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	_halmac_mac_reg_page0_chk(__func__, d, offset);
-+	val = cpu_to_le16(val);
-+	pbuf = rtw_zmalloc(2);
-+	if (!pbuf)
-+		return;
-+	_rtw_memcpy(pbuf, &val, 2);
-+
-+	ret = rtw_sdio_write_cmd53(d, offset, pbuf, 2);
-+	if (ret == _FAIL)
-+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
-+
-+	rtw_mfree(pbuf, 2);
-+}
-+
-+static void _halmac_sdio_reg_write_32(void *p, u32 offset, u32 val)
-+{
-+	struct dvobj_priv *d;
-+	u8 *pbuf;
-+	u8 ret;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	_halmac_mac_reg_page0_chk(__func__, d, offset);
-+	val = cpu_to_le32(val);
-+	pbuf = rtw_zmalloc(4);
-+	if (!pbuf)
-+		return;
-+	_rtw_memcpy(pbuf, &val, 4);
-+
-+	ret = rtw_sdio_write_cmd53(d, offset, pbuf, 4);
-+	if (ret == _FAIL)
-+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
-+
-+	rtw_mfree(pbuf, 4);
-+}
-+
-+static u8 _halmac_sdio_read_cia(void *p, u32 offset)
-+{
-+	struct dvobj_priv *d;
-+	u8 data = 0;
-+	u8 ret;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+
-+	ret = rtw_sdio_f0_read(d, offset, &data, 1);
-+	if (ret == _FAIL)
-+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
-+
-+	return data;
-+}
-+
-+#else /* !CONFIG_SDIO_HCI */
-+
-+static u8 _halmac_reg_read_8(void *p, u32 offset)
-+{
-+	struct dvobj_priv *d;
-+	PADAPTER adapter;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	adapter = dvobj_get_primary_adapter(d);
-+
-+	return _rtw_read8(adapter, offset);
-+}
-+
-+static u16 _halmac_reg_read_16(void *p, u32 offset)
-+{
-+	struct dvobj_priv *d;
-+	PADAPTER adapter;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	adapter = dvobj_get_primary_adapter(d);
-+
-+	return _rtw_read16(adapter, offset);
-+}
-+
-+static u32 _halmac_reg_read_32(void *p, u32 offset)
-+{
-+	struct dvobj_priv *d;
-+	PADAPTER adapter;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	adapter = dvobj_get_primary_adapter(d);
-+
-+	return _rtw_read32(adapter, offset);
-+}
-+
-+static void _halmac_reg_write_8(void *p, u32 offset, u8 val)
-+{
-+	struct dvobj_priv *d;
-+	PADAPTER adapter;
-+	int err;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	adapter = dvobj_get_primary_adapter(d);
-+
-+	err = _rtw_write8(adapter, offset, val);
-+	if (err == _FAIL)
-+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
-+}
-+
-+static void _halmac_reg_write_16(void *p, u32 offset, u16 val)
-+{
-+	struct dvobj_priv *d;
-+	PADAPTER adapter;
-+	int err;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	adapter = dvobj_get_primary_adapter(d);
-+
-+	err = _rtw_write16(adapter, offset, val);
-+	if (err == _FAIL)
-+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
-+}
-+
-+static void _halmac_reg_write_32(void *p, u32 offset, u32 val)
-+{
-+	struct dvobj_priv *d;
-+	PADAPTER adapter;
-+	int err;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	adapter = dvobj_get_primary_adapter(d);
-+
-+	err = _rtw_write32(adapter, offset, val);
-+	if (err == _FAIL)
-+		RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
-+}
-+#endif /* !CONFIG_SDIO_HCI */
-+
-+#ifdef DBG_IO
-+static void _halmac_reg_read_monitor(void *p, u32 addr, u32 len, u32 val
-+	, const char *caller, const u32 line)
-+{
-+	struct dvobj_priv *d = (struct dvobj_priv *)p;
-+	_adapter *adapter = dvobj_get_primary_adapter(d);
-+
-+	dbg_rtw_reg_read_monitor(adapter, addr, len, val, caller, line);
-+}
-+
-+static void _halmac_reg_write_monitor(void *p, u32 addr, u32 len, u32 val
-+	, const char *caller, const u32 line)
-+{
-+	struct dvobj_priv *d = (struct dvobj_priv *)p;
-+	_adapter *adapter = dvobj_get_primary_adapter(d);
-+
-+	dbg_rtw_reg_write_monitor(adapter, addr, len, val, caller, line);
-+}
-+#endif
-+
-+static u8 _halmac_mfree(void *p, void *buffer, u32 size)
-+{
-+	rtw_mfree(buffer, size);
-+	return RTW_HALMAC_SUCCESS;
-+}
-+
-+static void *_halmac_malloc(void *p, u32 size)
-+{
-+	return rtw_zmalloc(size);
-+}
-+
-+static u8 _halmac_memcpy(void *p, void *dest, void *src, u32 size)
-+{
-+	_rtw_memcpy(dest, src, size);
-+	return RTW_HALMAC_SUCCESS;
-+}
-+
-+static u8 _halmac_memset(void *p, void *addr, u8 value, u32 size)
-+{
-+	_rtw_memset(addr, value, size);
-+	return RTW_HALMAC_SUCCESS;
-+}
-+
-+static void _halmac_udelay(void *p, u32 us)
-+{
-+	/* Most hardware polling wait time < 50us) */
-+	if (us <= 50)
-+		rtw_udelay_os(us);
-+	else if (us <= 1000)
-+		rtw_usleep_os(us);
-+	else
-+		rtw_msleep_os(RTW_DIV_ROUND_UP(us, 1000));
-+}
-+
-+static u8 _halmac_mutex_init(void *p, HALMAC_MUTEX *pMutex)
-+{
-+	_rtw_mutex_init(pMutex);
-+	return RTW_HALMAC_SUCCESS;
-+}
-+
-+static u8 _halmac_mutex_deinit(void *p, HALMAC_MUTEX *pMutex)
-+{
-+	_rtw_mutex_free(pMutex);
-+	return RTW_HALMAC_SUCCESS;
-+}
-+
-+static u8 _halmac_mutex_lock(void *p, HALMAC_MUTEX *pMutex)
-+{
-+	int err;
-+
-+	err = _enter_critical_mutex(pMutex, NULL);
-+	if (err)
-+		return RTW_HALMAC_FAIL;
-+
-+	return RTW_HALMAC_SUCCESS;
-+}
-+
-+static u8 _halmac_mutex_unlock(void *p, HALMAC_MUTEX *pMutex)
-+{
-+	_exit_critical_mutex(pMutex, NULL);
-+	return RTW_HALMAC_SUCCESS;
-+}
-+
-+#ifndef CONFIG_SDIO_HCI
-+#define DBG_MSG_FILTER
-+#endif
-+
-+#ifdef DBG_MSG_FILTER
-+static u8 is_msg_allowed(uint drv_lv, u8 msg_lv)
-+{
-+	switch (drv_lv) {
-+	case _DRV_NONE_:
-+		return _FALSE;
-+
-+	case _DRV_ALWAYS_:
-+		if (msg_lv > HALMAC_DBG_ALWAYS)
-+			return _FALSE;
-+		break;
-+	case _DRV_ERR_:
-+		if (msg_lv > HALMAC_DBG_ERR)
-+			return _FALSE;
-+		break;
-+	case _DRV_WARNING_:
-+		if (msg_lv > HALMAC_DBG_WARN)
-+			return _FALSE;
-+		break;
-+	case _DRV_INFO_:
-+		if (msg_lv >= HALMAC_DBG_TRACE)
-+			return _FALSE;
-+		break;
-+	}
-+
-+	return _TRUE;
-+}
-+#endif /* DBG_MSG_FILTER */
-+
-+static u8 _halmac_msg_print(void *p, u32 msg_type, u8 msg_level, s8 *fmt, ...)
-+{
-+#define MSG_LEN		100
-+	va_list args;
-+	u8 str[MSG_LEN] = {0};
-+#ifdef DBG_MSG_FILTER
-+	uint drv_level = _DRV_NONE_;
-+#endif
-+	int err;
-+	u8 ret = RTW_HALMAC_SUCCESS;
-+
-+
-+#ifdef DBG_MSG_FILTER
-+#ifdef CONFIG_RTW_DEBUG
-+	drv_level = rtw_drv_log_level;
-+#endif
-+	if (is_msg_allowed(drv_level, msg_level) == _FALSE)
-+		return ret;
-+#endif
-+
-+	str[0] = '\n';
-+	va_start(args, fmt);
-+	err = vsnprintf(str, MSG_LEN, fmt, args);
-+	va_end(args);
-+
-+	/* An output error is encountered */
-+	if (err < 0)
-+		return RTW_HALMAC_FAIL;
-+	/* Output may be truncated due to size limit */
-+	if ((err == (MSG_LEN - 1)) && (str[MSG_LEN - 2] != '\n'))
-+		ret = RTW_HALMAC_FAIL;
-+
-+	if (msg_level == HALMAC_DBG_ALWAYS)
-+		RTW_PRINT(MSG_PREFIX "%s", str);
-+	else if (msg_level <= HALMAC_DBG_ERR)
-+		RTW_ERR(MSG_PREFIX "%s", str);
-+	else if (msg_level <= HALMAC_DBG_WARN)
-+		RTW_WARN(MSG_PREFIX "%s", str);
-+	else
-+		RTW_DBG(MSG_PREFIX "%s", str);
-+
-+	return ret;
-+}
-+
-+static u8 _halmac_buff_print(void *p, u32 msg_type, u8 msg_level, s8 *buf, u32 size)
-+{
-+	if (msg_level <= HALMAC_DBG_WARN)
-+		RTW_INFO_DUMP(MSG_PREFIX, buf, size);
-+	else
-+		RTW_DBG_DUMP(MSG_PREFIX, buf, size);
-+
-+	return RTW_HALMAC_SUCCESS;
-+}
-+
-+
-+const char *const RTW_HALMAC_FEATURE_NAME[] = {
-+	"HALMAC_FEATURE_CFG_PARA",
-+	"HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE",
-+	"HALMAC_FEATURE_DUMP_LOGICAL_EFUSE",
-+	"HALMAC_FEATURE_DUMP_LOGICAL_EFUSE_MASK",
-+	"HALMAC_FEATURE_UPDATE_PACKET",
-+	"HALMAC_FEATURE_SEND_SCAN_PACKET",
-+	"HALMAC_FEATURE_DROP_SCAN_PACKET",
-+	"HALMAC_FEATURE_UPDATE_DATAPACK",
-+	"HALMAC_FEATURE_RUN_DATAPACK",
-+	"HALMAC_FEATURE_CHANNEL_SWITCH",
-+	"HALMAC_FEATURE_IQK",
-+	"HALMAC_FEATURE_POWER_TRACKING",
-+	"HALMAC_FEATURE_PSD",
-+	"HALMAC_FEATURE_FW_SNDING",
-+	"HALMAC_FEATURE_DPK",
-+	"HALMAC_FEATURE_ALL"
-+};
-+
-+static inline u8 is_valid_id_status(enum halmac_feature_id id, enum halmac_cmd_process_status status)
-+{
-+	switch (id) {
-+	case HALMAC_FEATURE_CFG_PARA:
-+		RTW_DBG("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
-+		break;
-+	case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
-+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
-+		if (HALMAC_CMD_PROCESS_DONE != status)
-+			RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
-+				 __FUNCTION__, id, status);
-+		break;
-+	case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
-+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
-+		if (HALMAC_CMD_PROCESS_DONE != status)
-+			RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
-+				 __FUNCTION__, id, status);
-+		break;
-+	case HALMAC_FEATURE_UPDATE_PACKET:
-+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
-+		if (status != HALMAC_CMD_PROCESS_DONE)
-+			RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
-+				 __FUNCTION__, id, status);
-+		break;
-+	case HALMAC_FEATURE_UPDATE_DATAPACK:
-+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
-+		break;
-+	case HALMAC_FEATURE_RUN_DATAPACK:
-+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
-+		break;
-+	case HALMAC_FEATURE_CHANNEL_SWITCH:
-+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
-+		if ((status != HALMAC_CMD_PROCESS_DONE) && (status != HALMAC_CMD_PROCESS_RCVD))
-+			RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
-+				 __FUNCTION__, id, status);
-+		if (status == HALMAC_CMD_PROCESS_DONE)
-+			return _FALSE;
-+		break;
-+	case HALMAC_FEATURE_IQK:
-+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
-+		break;
-+	case HALMAC_FEATURE_POWER_TRACKING:
-+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
-+		break;
-+	case HALMAC_FEATURE_PSD:
-+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
-+		break;
-+	case HALMAC_FEATURE_FW_SNDING:
-+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
-+		break;
-+	case HALMAC_FEATURE_DPK:
-+		if (status == HALMAC_CMD_PROCESS_RCVD)
-+			return _FALSE;
-+		if ((status != HALMAC_CMD_PROCESS_DONE)
-+		    || (status != HALMAC_CMD_PROCESS_ERROR))
-+			RTW_WARN("%s: %s unexpected status(0x%x)!\n",
-+				 __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id],
-+				 status);
-+		break;
-+	case HALMAC_FEATURE_ALL:
-+		RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
-+		break;
-+	default:
-+		RTW_ERR("%s: unknown feature id(%d)\n", __FUNCTION__, id);
-+		return _FALSE;
-+	}
-+
-+	return _TRUE;
-+}
-+
-+static int init_halmac_event_with_waittime(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size, u32 time)
-+{
-+	struct submit_ctx *sctx;
-+
-+
-+	if (!d->hmpriv.indicator[id].sctx) {
-+		sctx = (struct submit_ctx *)rtw_zmalloc(sizeof(*sctx));
-+		if (!sctx)
-+			return -1;
-+	} else {
-+		RTW_WARN("%s: id(%d) sctx is not NULL!!\n", __FUNCTION__, id);
-+		sctx = d->hmpriv.indicator[id].sctx;
-+		d->hmpriv.indicator[id].sctx = NULL;
-+	}
-+
-+	rtw_sctx_init(sctx, time);
-+	d->hmpriv.indicator[id].buffer = buf;
-+	d->hmpriv.indicator[id].buf_size = size;
-+	d->hmpriv.indicator[id].ret_size = 0;
-+	d->hmpriv.indicator[id].status = 0;
-+	/* fill sctx at least to sure other variables are all ready! */
-+	d->hmpriv.indicator[id].sctx = sctx;
-+
-+	return 0;
-+}
-+
-+static inline int init_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size)
-+{
-+	return init_halmac_event_with_waittime(d, id, buf, size, DEFAULT_INDICATOR_TIMELMT);
-+}
-+
-+static void free_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id)
-+{
-+	struct submit_ctx *sctx;
-+
-+
-+	if (!d->hmpriv.indicator[id].sctx)
-+		return;
-+
-+	sctx = d->hmpriv.indicator[id].sctx;
-+	d->hmpriv.indicator[id].sctx = NULL;
-+	rtw_mfree((u8 *)sctx, sizeof(*sctx));
-+}
-+
-+static int wait_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	struct submit_ctx *sctx;
-+	int status;
-+	int ret;
-+
-+
-+	sctx = d->hmpriv.indicator[id].sctx;
-+	if (!sctx)
-+		return -1;
-+
-+	ret = rtw_sctx_wait(sctx, RTW_HALMAC_FEATURE_NAME[id]);
-+	status = sctx->status;
-+	free_halmac_event(d, id);
-+	if (_SUCCESS == ret)
-+		return 0;
-+
-+	/* If no one change sctx->status, it is timeout case */
-+	if (status == 0)
-+		status = RTW_SCTX_DONE_TIMEOUT;
-+	RTW_ERR("%s: id(%d, %s) status=0x%x ! Reset HALMAC state!\n",
-+		__FUNCTION__, id, RTW_HALMAC_FEATURE_NAME[id], status);
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+	api->halmac_reset_feature(mac, id);
-+
-+	return -1;
-+}
-+
-+/*
-+ * Return:
-+ *	Always return RTW_HALMAC_SUCCESS, HALMAC don't care the return value.
-+ */
-+static u8 _halmac_event_indication(void *p, enum halmac_feature_id feature_id,
-+				enum halmac_cmd_process_status process_status,
-+				u8 *buf, u32 size)
-+{
-+	struct dvobj_priv *d;
-+	PADAPTER adapter;
-+	PHAL_DATA_TYPE hal;
-+	struct halmac_indicator *tbl, *indicator;
-+	struct submit_ctx *sctx;
-+	u32 cpsz;
-+	u8 ret;
-+
-+
-+	d = (struct dvobj_priv *)p;
-+	adapter = dvobj_get_primary_adapter(d);
-+	hal = GET_HAL_DATA(adapter);
-+	tbl = d->hmpriv.indicator;
-+
-+	/* Filter(Skip) middle status indication */
-+	ret = is_valid_id_status(feature_id, process_status);
-+	if (_FALSE == ret)
-+		goto exit;
-+
-+	indicator = &tbl[feature_id];
-+	indicator->status = process_status;
-+	indicator->ret_size = size;
-+	if (!indicator->sctx) {
-+		RTW_WARN("%s: id(%d, %s) is not waiting!!\n", __FUNCTION__,
-+			 feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]);
-+		goto exit;
-+	}
-+	sctx = indicator->sctx;
-+
-+	if (HALMAC_CMD_PROCESS_ERROR == process_status) {
-+		RTW_ERR("%s: id(%d, %s) Something wrong!!\n", __FUNCTION__,
-+			feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]);
-+		if ((size == 1) && buf)
-+			RTW_ERR("%s: error code=0x%x\n", __FUNCTION__, *buf);
-+		rtw_sctx_done_err(&sctx, RTW_SCTX_DONE_UNKNOWN);
-+		goto exit;
-+	}
-+
-+	if (size > indicator->buf_size) {
-+		RTW_WARN("%s: id(%d, %s) buffer is not enough(%d<%d), "
-+			 "and data will be truncated!\n",
-+			 __FUNCTION__,
-+			 feature_id, RTW_HALMAC_FEATURE_NAME[feature_id],
-+			 indicator->buf_size, size);
-+		cpsz = indicator->buf_size;
-+	} else {
-+		cpsz = size;
-+	}
-+	if (cpsz && indicator->buffer)
-+		_rtw_memcpy(indicator->buffer, buf, cpsz);
-+
-+	rtw_sctx_done(&sctx);
-+
-+exit:
-+	return RTW_HALMAC_SUCCESS;
-+}
-+
-+struct halmac_platform_api rtw_halmac_platform_api = {
-+	/* R/W register */
-+#ifdef CONFIG_SDIO_HCI
-+	.SDIO_CMD52_READ = _halmac_sdio_cmd52_read,
-+	.SDIO_CMD53_READ_8 = _halmac_sdio_reg_read_8,
-+	.SDIO_CMD53_READ_16 = _halmac_sdio_reg_read_16,
-+	.SDIO_CMD53_READ_32 = _halmac_sdio_reg_read_32,
-+	.SDIO_CMD53_READ_N = _halmac_sdio_reg_read_n,
-+	.SDIO_CMD52_WRITE = _halmac_sdio_cmd52_write,
-+	.SDIO_CMD53_WRITE_8 = _halmac_sdio_reg_write_8,
-+	.SDIO_CMD53_WRITE_16 = _halmac_sdio_reg_write_16,
-+	.SDIO_CMD53_WRITE_32 = _halmac_sdio_reg_write_32,
-+	.SDIO_CMD52_CIA_READ = _halmac_sdio_read_cia,
-+#endif /* CONFIG_SDIO_HCI */
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
-+	.REG_READ_8 = _halmac_reg_read_8,
-+	.REG_READ_16 = _halmac_reg_read_16,
-+	.REG_READ_32 = _halmac_reg_read_32,
-+	.REG_WRITE_8 = _halmac_reg_write_8,
-+	.REG_WRITE_16 = _halmac_reg_write_16,
-+	.REG_WRITE_32 = _halmac_reg_write_32,
-+#endif /* CONFIG_USB_HCI || CONFIG_PCI_HCI */
-+
-+#ifdef DBG_IO
-+	.READ_MONITOR = _halmac_reg_read_monitor,
-+	.WRITE_MONITOR = _halmac_reg_write_monitor,
-+#endif
-+
-+	/* Write data */
-+#if 0
-+	/* impletement in HAL-IC level */
-+	.SEND_RSVD_PAGE = sdio_write_data_rsvd_page,
-+	.SEND_H2C_PKT = sdio_write_data_h2c,
-+#endif
-+	/* Memory allocate */
-+	.RTL_FREE = _halmac_mfree,
-+	.RTL_MALLOC = _halmac_malloc,
-+	.RTL_MEMCPY = _halmac_memcpy,
-+	.RTL_MEMSET = _halmac_memset,
-+
-+	/* Sleep */
-+	.RTL_DELAY_US = _halmac_udelay,
-+
-+	/* Process Synchronization */
-+	.MUTEX_INIT = _halmac_mutex_init,
-+	.MUTEX_DEINIT = _halmac_mutex_deinit,
-+	.MUTEX_LOCK = _halmac_mutex_lock,
-+	.MUTEX_UNLOCK = _halmac_mutex_unlock,
-+
-+	.MSG_PRINT = _halmac_msg_print,
-+	.BUFF_PRINT = _halmac_buff_print,
-+	.EVENT_INDICATION = _halmac_event_indication,
-+};
-+
-+u8 rtw_halmac_read8(struct intf_hdl *pintfhdl, u32 addr)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+
-+
-+	/* WARNING: pintf_dev should not be null! */
-+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
-+	api = HALMAC_GET_API(mac);
-+
-+	return api->halmac_reg_read_8(mac, addr);
-+}
-+
-+u16 rtw_halmac_read16(struct intf_hdl *pintfhdl, u32 addr)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+
-+
-+	/* WARNING: pintf_dev should not be null! */
-+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
-+	api = HALMAC_GET_API(mac);
-+
-+	return api->halmac_reg_read_16(mac, addr);
-+}
-+
-+u32 rtw_halmac_read32(struct intf_hdl *pintfhdl, u32 addr)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+
-+
-+	/* WARNING: pintf_dev should not be null! */
-+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
-+	api = HALMAC_GET_API(mac);
-+
-+	return api->halmac_reg_read_32(mac, addr);
-+}
-+
-+static void _read_register(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf)
-+{
-+#if 1
-+	struct _ADAPTER *a;
-+	u32 i, n;
-+	u16 val16;
-+	u32 val32;
-+
-+
-+	a = dvobj_get_primary_adapter(d);
-+
-+	i = addr & 0x3;
-+	/* Handle address not start from 4 bytes alignment case */
-+	if (i) {
-+		val32 = cpu_to_le32(rtw_read32(a, addr & ~0x3));
-+		n = 4 - i;
-+		_rtw_memcpy(buf, ((u8 *)&val32) + i, n);
-+		i = n;
-+		cnt -= n;
-+	}
-+
-+	while (cnt) {
-+		if (cnt >= 4)
-+			n = 4;
-+		else if (cnt >= 2)
-+			n = 2;
-+		else
-+			n = 1;
-+		cnt -= n;
-+
-+		switch (n) {
-+		case 1:
-+			buf[i] = rtw_read8(a, addr+i);
-+			i++;
-+			break;
-+		case 2:
-+			val16 = cpu_to_le16(rtw_read16(a, addr+i));
-+			_rtw_memcpy(&buf[i], &val16, 2);
-+			i += 2;
-+			break;
-+		case 4:
-+			val32 = cpu_to_le32(rtw_read32(a, addr+i));
-+			_rtw_memcpy(&buf[i], &val32, 4);
-+			i += 4;
-+			break;
-+		}
-+	}
-+#else
-+	struct _ADAPTER *a;
-+	u32 i;
-+
-+
-+	a = dvobj_get_primary_adapter(d);
-+	for (i = 0; i < cnt; i++)
-+		buf[i] = rtw_read8(a, addr + i);
-+#endif
-+}
-+
-+#ifdef CONFIG_SDIO_HCI
-+static int _sdio_read_local(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+
-+
-+	if (buf == NULL)
-+		return -1;
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_reg_sdio_cmd53_read_n(mac, addr, cnt, buf);
-+	if (status != HALMAC_RET_SUCCESS) {
-+		RTW_ERR("%s: addr=0x%08x cnt=%d err=%d\n",
-+			__FUNCTION__, addr, cnt, status);
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+#endif /* CONFIG_SDIO_HCI */
-+
-+void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem)
-+{
-+	struct dvobj_priv *d;
-+
-+
-+	if (pmem == NULL) {
-+		RTW_ERR("pmem is NULL\n");
-+		return;
-+	}
-+
-+	d = pintfhdl->pintf_dev;
-+
-+#ifdef CONFIG_SDIO_HCI
-+	if (addr & 0xFFFF0000) {
-+		int err = 0;
-+
-+		err = _sdio_read_local(d, addr, cnt, pmem);
-+		if (!err)
-+			return;
-+	}
-+#endif /* CONFIG_SDIO_HCI */
-+
-+	_read_register(d, addr, cnt, pmem);
-+}
-+
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+
-+	/* WARNING: pintf_dev should not be null! */
-+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
-+	api = HALMAC_GET_API(mac);
-+
-+	/*return api->halmac_reg_read_indirect_8(mac, addr);*/
-+	return api->halmac_reg_read_8(mac, addr);
-+}
-+
-+u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	u16 val16 = 0;
-+
-+	/* WARNING: pintf_dev should not be null! */
-+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
-+	api = HALMAC_GET_API(mac);
-+
-+	/*return api->halmac_reg_read_indirect_16(mac, addr);*/
-+	return api->halmac_reg_read_16(mac, addr);
-+}
-+
-+u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+
-+
-+	/* WARNING: pintf_dev should not be null! */
-+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
-+	api = HALMAC_GET_API(mac);
-+
-+	return api->halmac_reg_read_indirect_32(mac, addr);
-+}
-+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
-+
-+int rtw_halmac_write8(struct intf_hdl *pintfhdl, u32 addr, u8 value)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+
-+
-+	/* WARNING: pintf_dev should not be null! */
-+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_reg_write_8(mac, addr, value);
-+
-+	if (status == HALMAC_RET_SUCCESS)
-+		return 0;
-+
-+	return -1;
-+}
-+
-+int rtw_halmac_write16(struct intf_hdl *pintfhdl, u32 addr, u16 value)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+
-+
-+	/* WARNING: pintf_dev should not be null! */
-+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_reg_write_16(mac, addr, value);
-+
-+	if (status == HALMAC_RET_SUCCESS)
-+		return 0;
-+
-+	return -1;
-+}
-+
-+int rtw_halmac_write32(struct intf_hdl *pintfhdl, u32 addr, u32 value)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+
-+
-+	/* WARNING: pintf_dev should not be null! */
-+	mac = dvobj_to_halmac(pintfhdl->pintf_dev);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_reg_write_32(mac, addr, value);
-+
-+	if (status == HALMAC_RET_SUCCESS)
-+		return 0;
-+
-+	return -1;
-+}
-+
-+static int init_write_rsvd_page_size(struct dvobj_priv *d)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	u32 size = 0;
-+	struct halmac_ofld_func_info ofld_info;
-+	enum halmac_ret_status status;
-+	int err = 0;
-+
-+
-+#ifdef CONFIG_USB_HCI
-+	/* for USB do not exceed MAX_CMDBUF_SZ */
-+	size = 0x1000;
-+#elif defined(CONFIG_PCI_HCI)
-+	size = MAX_CMDBUF_SZ - TXDESC_OFFSET;
-+#elif defined(CONFIG_SDIO_HCI)
-+	size = 0x7000; /* 28KB */
-+#else
-+	/* Use HALMAC default setting and don't call any function */
-+	return 0;
-+#endif
-+#if 0	/* Fail to pass coverity DEADCODE check */
-+	/* If size==0, use HALMAC default setting and don't call any function */
-+	if (!size)
-+		return 0;
-+#endif
-+	err = rtw_halmac_set_max_dl_fw_size(d, size);
-+	if (err) {
-+		RTW_ERR("%s: Fail to set max download fw size!\n", __FUNCTION__);
-+		return -1;
-+	}
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	_rtw_memset(&ofld_info, 0, sizeof(ofld_info));
-+	ofld_info.halmac_malloc_max_sz = 0xFFFFFFFF;
-+	ofld_info.rsvd_pg_drv_buf_max_sz = size;
-+	status = api->halmac_ofld_func_cfg(mac, &ofld_info);
-+	if (status != HALMAC_RET_SUCCESS) {
-+		RTW_ERR("%s: Fail to config offload parameters!\n", __FUNCTION__);
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+static int init_priv(struct halmacpriv *priv)
-+{
-+	struct halmac_indicator *indicator;
-+	u32 count, size;
-+
-+
-+	if (priv->indicator)
-+		RTW_WARN("%s: HALMAC private data is not CLEAR!\n", __FUNCTION__);
-+	count = HALMAC_FEATURE_ALL + 1;
-+	size = sizeof(*indicator) * count;
-+	indicator = (struct halmac_indicator *)rtw_zmalloc(size);
-+	if (!indicator)
-+		return -1;
-+	priv->indicator = indicator;
-+
-+	return 0;
-+}
-+
-+static void deinit_priv(struct halmacpriv *priv)
-+{
-+	struct halmac_indicator *indicator;
-+
-+
-+	indicator = priv->indicator;
-+	priv->indicator = NULL;
-+	if (indicator) {
-+		u32 count, size;
-+
-+		count = HALMAC_FEATURE_ALL + 1;
-+#ifdef CONFIG_RTW_DEBUG
-+		{
-+			struct submit_ctx *sctx;
-+			u32 i;
-+
-+			for (i = 0; i < count; i++) {
-+				if (!indicator[i].sctx)
-+					continue;
-+
-+				RTW_WARN("%s: %s id(%d) sctx still exist!!\n",
-+					__FUNCTION__, RTW_HALMAC_FEATURE_NAME[i], i);
-+				sctx = indicator[i].sctx;
-+				indicator[i].sctx = NULL;
-+				rtw_mfree((u8 *)sctx, sizeof(*sctx));
-+			}
-+		}
-+#endif /* !CONFIG_RTW_DEBUG */
-+		size = sizeof(*indicator) * count;
-+		rtw_mfree((u8 *)indicator, size);
-+	}
-+}
-+
-+#ifdef CONFIG_SDIO_HCI
-+static enum halmac_sdio_spec_ver _sdio_ver_drv2halmac(struct dvobj_priv *d)
-+{
-+	bool v3;
-+	enum halmac_sdio_spec_ver ver;
-+
-+
-+	v3 = rtw_is_sdio30(dvobj_get_primary_adapter(d));
-+	if (v3)
-+		ver = HALMAC_SDIO_SPEC_VER_3_00;
-+	else
-+		ver = HALMAC_SDIO_SPEC_VER_2_00;
-+
-+	return ver;
-+}
-+#endif /* CONFIG_SDIO_HCI */
-+
-+void rtw_halmac_get_version(char *str, u32 len)
-+{
-+	enum halmac_ret_status status;
-+	struct halmac_ver ver;
-+
-+
-+	status = halmac_get_version(&ver);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return;
-+
-+	rtw_sprintf(str, len, "V%d_%02d_%02d",
-+		    ver.major_ver, ver.prototype_ver, ver.minor_ver);
-+}
-+
-+int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_interface intf;
-+	enum halmac_intf_phy_platform pltfm = HALMAC_INTF_PHY_PLATFORM_ALL;
-+	enum halmac_ret_status status;
-+	int err = 0;
-+#ifdef CONFIG_SDIO_HCI
-+	struct halmac_sdio_hw_info info;
-+#endif /* CONFIG_SDIO_HCI */
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	if (halmac) {
-+		RTW_WARN("%s: initialize already completed!\n", __FUNCTION__);
-+		goto error;
-+	}
-+
-+	err = init_priv(&d->hmpriv);
-+	if (err)
-+		goto error;
-+
-+#ifdef CONFIG_SDIO_HCI
-+	intf = HALMAC_INTERFACE_SDIO;
-+#elif defined(CONFIG_USB_HCI)
-+	intf = HALMAC_INTERFACE_USB;
-+#elif defined(CONFIG_PCI_HCI)
-+	intf = HALMAC_INTERFACE_PCIE;
-+#else
-+#warning "INTERFACE(CONFIG_XXX_HCI) not be defined!!"
-+	intf = HALMAC_INTERFACE_UNDEFINE;
-+#endif
-+	status = halmac_init_adapter(d, pf_api, intf, &halmac, &api);
-+	if (HALMAC_RET_SUCCESS != status) {
-+		RTW_ERR("%s: halmac_init_adapter fail!(status=%d)\n", __FUNCTION__, status);
-+		err = -1;
-+		if (halmac)
-+			goto deinit;
-+		goto free;
-+	}
-+
-+	dvobj_set_halmac(d, halmac);
-+
-+	status = api->halmac_interface_integration_tuning(halmac);
-+	if (status != HALMAC_RET_SUCCESS) {
-+		RTW_ERR("%s: halmac_interface_integration_tuning fail!(status=%d)\n", __FUNCTION__, status);
-+		err = -1;
-+		goto deinit;
-+	}
-+
-+#ifdef CONFIG_PLATFORM_RTK1319
-+	pltfm = HALMAC_INTF_PHY_PLATFORM_DHC;
-+#endif /* CONFIG_PLATFORM_RTK1319 */
-+	status = api->halmac_phy_cfg(halmac, pltfm);
-+	if (status != HALMAC_RET_SUCCESS) {
-+		RTW_ERR("%s: halmac_phy_cfg fail! (platform=%d, status=%d)\n",
-+			__FUNCTION__, pltfm, status);
-+		err = -1;
-+		goto deinit;
-+	}
-+
-+	init_write_rsvd_page_size(d);
-+
-+#ifdef CONFIG_SDIO_HCI
-+	_rtw_memset(&info, 0, sizeof(info));
-+	info.spec_ver = _sdio_ver_drv2halmac(d);
-+	/* Convert clock speed unit to MHz from Hz */
-+	info.clock_speed = RTW_DIV_ROUND_UP(rtw_sdio_get_clock(d), 1000000);
-+	info.block_size = rtw_sdio_get_block_size(d);
-+	if (d->hmpriv.sdio_io_indir == 2)
-+		info.io_indir_flag = 0;
-+	else
-+		info.io_indir_flag = 1; /* Default enable indirect I/O */
-+	RTW_DBG("%s: SDIO ver=%u clock=%uMHz blk_size=%u bytes, io_indir=%u\n",
-+		__FUNCTION__, info.spec_ver+2, info.clock_speed,
-+		info.block_size, info.io_indir_flag);
-+	status = api->halmac_sdio_hw_info(halmac, &info);
-+	if (status != HALMAC_RET_SUCCESS) {
-+		RTW_ERR("%s: halmac_sdio_hw_info fail!(status=%d)\n",
-+			__FUNCTION__, status);
-+		err = -1;
-+		goto deinit;
-+	}
-+#endif /* CONFIG_SDIO_HCI */
-+
-+	return 0;
-+
-+deinit:
-+	status = halmac_deinit_adapter(halmac);
-+	dvobj_set_halmac(d, NULL);
-+	if (status != HALMAC_RET_SUCCESS)
-+		RTW_ERR("%s: halmac_deinit_adapter fail!(status=%d)\n",
-+			__FUNCTION__, status);
-+
-+free:
-+	deinit_priv(&d->hmpriv);
-+
-+error:
-+	return err;
-+}
-+
-+int rtw_halmac_deinit_adapter(struct dvobj_priv *d)
-+{
-+	struct halmac_adapter *halmac;
-+	enum halmac_ret_status status;
-+	int err = 0;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	if (halmac) {
-+		status = halmac_deinit_adapter(halmac);
-+		dvobj_set_halmac(d, NULL);
-+		if (status != HALMAC_RET_SUCCESS)
-+			err = -1;
-+	}
-+
-+	deinit_priv(&d->hmpriv);
-+
-+	return err;
-+}
-+
-+static inline enum halmac_portid _hw_port_drv2halmac(enum _hw_port hwport)
-+{
-+	enum halmac_portid port = HALMAC_PORTID_NUM;
-+
-+
-+	switch (hwport) {
-+	case HW_PORT0:
-+		port = HALMAC_PORTID0;
-+		break;
-+	case HW_PORT1:
-+		port = HALMAC_PORTID1;
-+		break;
-+	case HW_PORT2:
-+		port = HALMAC_PORTID2;
-+		break;
-+	case HW_PORT3:
-+		port = HALMAC_PORTID3;
-+		break;
-+	case HW_PORT4:
-+		port = HALMAC_PORTID4;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return port;
-+}
-+
-+static enum halmac_network_type_select _network_type_drv2halmac(u8 type)
-+{
-+	enum halmac_network_type_select network = HALMAC_NETWORK_UNDEFINE;
-+
-+
-+	switch (type) {
-+	case _HW_STATE_NOLINK_:
-+	case _HW_STATE_MONITOR_:
-+		network = HALMAC_NETWORK_NO_LINK;
-+		break;
-+
-+	case _HW_STATE_ADHOC_:
-+		network = HALMAC_NETWORK_ADHOC;
-+		break;
-+
-+	case _HW_STATE_STATION_:
-+		network = HALMAC_NETWORK_INFRASTRUCTURE;
-+		break;
-+
-+	case _HW_STATE_AP_:
-+		network = HALMAC_NETWORK_AP;
-+		break;
-+	}
-+
-+	return network;
-+}
-+
-+static u8 _network_type_halmac2drv(enum halmac_network_type_select network)
-+{
-+	u8 type = _HW_STATE_NOLINK_;
-+
-+
-+	switch (network) {
-+	case HALMAC_NETWORK_NO_LINK:
-+	case HALMAC_NETWORK_UNDEFINE:
-+		type = _HW_STATE_NOLINK_;
-+		break;
-+
-+	case HALMAC_NETWORK_ADHOC:
-+		type = _HW_STATE_ADHOC_;
-+		break;
-+
-+	case HALMAC_NETWORK_INFRASTRUCTURE:
-+		type = _HW_STATE_STATION_;
-+		break;
-+
-+	case HALMAC_NETWORK_AP:
-+		type = _HW_STATE_AP_;
-+		break;
-+	}
-+
-+	return type;
-+}
-+
-+static void _beacon_ctrl_halmac2drv(struct halmac_bcn_ctrl *ctrl,
-+				struct rtw_halmac_bcn_ctrl *drv_ctrl)
-+{
-+	drv_ctrl->rx_bssid_fit = ctrl->dis_rx_bssid_fit ? 0 : 1;
-+	drv_ctrl->txbcn_rpt = ctrl->en_txbcn_rpt ? 1 : 0;
-+	drv_ctrl->tsf_update = ctrl->dis_tsf_udt ? 0 : 1;
-+	drv_ctrl->enable_bcn = ctrl->en_bcn ? 1 : 0;
-+	drv_ctrl->rxbcn_rpt = ctrl->en_rxbcn_rpt ? 1 : 0;
-+	drv_ctrl->p2p_ctwin = ctrl->en_p2p_ctwin ? 1 : 0;
-+	drv_ctrl->p2p_bcn_area = ctrl->en_p2p_bcn_area ? 1 : 0;
-+}
-+
-+static void _beacon_ctrl_drv2halmac(struct rtw_halmac_bcn_ctrl *drv_ctrl,
-+				struct halmac_bcn_ctrl *ctrl)
-+{
-+	ctrl->dis_rx_bssid_fit = drv_ctrl->rx_bssid_fit ? 0 : 1;
-+	ctrl->en_txbcn_rpt = drv_ctrl->txbcn_rpt ? 1 : 0;
-+	ctrl->dis_tsf_udt = drv_ctrl->tsf_update ? 0 : 1;
-+	ctrl->en_bcn = drv_ctrl->enable_bcn ? 1 : 0;
-+	ctrl->en_rxbcn_rpt = drv_ctrl->rxbcn_rpt ? 1 : 0;
-+	ctrl->en_p2p_ctwin = drv_ctrl->p2p_ctwin ? 1 : 0;
-+	ctrl->en_p2p_bcn_area = drv_ctrl->p2p_bcn_area ? 1 : 0;
-+}
-+
-+int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_get_hw_value(mac, hw_id, pvalue);
-+	if (HALMAC_RET_SUCCESS != status)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_get_tx_fifo_size() - TX FIFO size
-+ * @d:		struct dvobj_priv*
-+ * @size:	TX FIFO size, unit is byte.
-+ *
-+ * Get TX FIFO size(byte) from HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 val = 0;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_TXFIFO_SIZE, &val);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	*size = val;
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_get_rx_fifo_size() - RX FIFO size
-+ * @d:		struct dvobj_priv*
-+ * @size:	RX FIFO size, unit is byte
-+ *
-+ * Get RX FIFO size(byte) from HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 val = 0;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RXFIFO_SIZE, &val);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	*size = val;
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_get_rsvd_drv_pg_bndy() - Reserve page boundary of driver
-+ * @d:		struct dvobj_priv*
-+ * @size:	Page size, unit is byte
-+ *
-+ * Get reserve page boundary of driver from HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u16 val = 0;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY, &val);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	*bndy = val;
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_get_page_size() - Page size
-+ * @d:		struct dvobj_priv*
-+ * @size:	Page size, unit is byte
-+ *
-+ * Get TX/RX page size(byte) from HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 val = 0;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_PAGE_SIZE, &val);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	*size = val;
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_get_tx_agg_align_size() - TX aggregation align size
-+ * @d:		struct dvobj_priv*
-+ * @size:	TX aggregation align size, unit is byte
-+ *
-+ * Get TX aggregation align size(byte) from HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u16 val = 0;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_TX_AGG_ALIGN_SIZE, &val);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	*size = val;
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_get_rx_agg_align_size() - RX aggregation align size
-+ * @d:		struct dvobj_priv*
-+ * @size:	RX aggregation align size, unit is byte
-+ *
-+ * Get RX aggregation align size(byte) from HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u8 val = 0;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_AGG_ALIGN_SIZE, &val);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	*size = val;
-+
-+	return 0;
-+}
-+
-+/*
-+ * Description:
-+ *	Get RX driver info size. RX driver info is a small memory space between
-+ *	scriptor and RX payload.
-+ *
-+ *	+-------------------------+
-+ *	| RX descriptor           |
-+ *	| usually 24 bytes        |
-+ *	+-------------------------+
-+ *	| RX driver info          |
-+ *	| depends on driver cfg   |
-+ *	+-------------------------+
-+ *	| RX paylad               |
-+ *	|                         |
-+ *	+-------------------------+
-+ *
-+ * Parameter:
-+ *	d	pointer to struct dvobj_priv of driver
-+ *	sz	rx driver info size in bytes.
-+ *
-+ * Return:
-+ *	0	Success
-+ *	other	Fail
-+ */
-+int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *d, u8 *sz)
-+{
-+	enum halmac_ret_status status;
-+	struct halmac_adapter *halmac = dvobj_to_halmac(d);
-+	struct halmac_api *api = HALMAC_GET_API(halmac);
-+	u8 dw = 0;
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_DRV_INFO_SIZE, &dw);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	*sz = dw * 8;
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_get_tx_desc_size() - TX descriptor size
-+ * @d:		struct dvobj_priv*
-+ * @size:	TX descriptor size, unit is byte.
-+ *
-+ * Get TX descriptor size(byte) from HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 val = 0;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_TX_DESC_SIZE, &val);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	*size = val;
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_get_rx_desc_size() - RX descriptor size
-+ * @d:		struct dvobj_priv*
-+ * @size:	RX descriptor size, unit is byte.
-+ *
-+ * Get RX descriptor size(byte) from HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 val = 0;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_DESC_SIZE, &val);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	*size = val;
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_get_tx_dma_ch_map() - Get TX DMA channel Map for tx desc
-+ * @d:		struct dvobj_priv*
-+ * @dma_ch_map:	return map of QSEL to DMA channel
-+ * @map_size:	size of dma_ch_map
-+ *		Suggest size to be last valid QSEL(QSLT_CMD)+1 or full QSLT
-+ *		size(0x20)
-+ *
-+ * 8814B would need this to get mapping of QSEL to DMA channel for TX desc.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_get_tx_dma_ch_map(struct dvobj_priv *d, u8 *dma_ch_map, u8 map_size)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	struct halmac_rqpn_ch_map map;
-+	enum halmac_dma_ch channel = HALMAC_DMA_CH_UNDEFINE;
-+	u8 qsel;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RQPN_CH_MAPPING, &map);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	for (qsel = 0; qsel < map_size; qsel++) {
-+		switch (qsel) {
-+		/*case QSLT_VO:*/
-+		case 0x06:
-+		case 0x07:
-+			channel = map.dma_map_vo;
-+			break;
-+		/*case QSLT_VI:*/
-+		case 0x04:
-+		case 0x05:
-+			channel = map.dma_map_vi;
-+			break;
-+		/*case QSLT_BE:*/
-+		case 0x00:
-+		case 0x03:
-+			channel = map.dma_map_be;
-+			break;
-+		/*case QSLT_BK:*/
-+		case 0x01:
-+		case 0x02:
-+			channel = map.dma_map_bk;
-+			break;
-+		/*case QSLT_BEACON:*/
-+		case 0x10:
-+			channel = HALMAC_DMA_CH_BCN;
-+			break;
-+		/*case QSLT_HIGH:*/
-+		case 0x11:
-+			channel = map.dma_map_hi;
-+			break;
-+		/*case QSLT_MGNT:*/
-+		case 0x12:
-+			channel = map.dma_map_mg;
-+			break;
-+		/*case QSLT_CMD:*/
-+		case 0x13:
-+			channel = HALMAC_DMA_CH_H2C;
-+			break;
-+		default:
-+			/*RTW_ERR("%s: invalid qsel=0x%x\n", __FUNCTION__, qsel);*/
-+			channel = HALMAC_DMA_CH_UNDEFINE;
-+			break;
-+		}
-+		dma_ch_map[qsel] = (u8)channel;
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_get_fw_max_size() - Firmware MAX size
-+ * @d:		struct dvobj_priv*
-+ * @size:	MAX Firmware size, unit is byte.
-+ *
-+ * Get Firmware MAX size(byte) from HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+static int rtw_halmac_get_fw_max_size(struct dvobj_priv *d, u32 *size)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 val = 0;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_FW_MAX_SIZE, &val);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	*size = val;
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_get_ori_h2c_size() - Original H2C MAX size
-+ * @d:		struct dvobj_priv*
-+ * @size:	H2C MAX size, unit is byte.
-+ *
-+ * Get original H2C MAX size(byte) from HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 val = 0;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_ORI_H2C_SIZE, &val);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	*size = val;
-+
-+	return 0;
-+}
-+
-+int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size)
-+{
-+	enum halmac_ret_status status;
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	u8 val;
-+
-+
-+	if (!size)
-+		return -1;
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_OQT_SIZE, &val);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	*size = val;
-+	return 0;
-+}
-+
-+int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num)
-+{
-+	enum halmac_ret_status status;
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	u8 val;
-+
-+
-+	if (!num)
-+		return -1;
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_QUEUE_NUM, &val);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	*num = val;
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_get_mac_address() - Get MAC address of specific port
-+ * @d:		struct dvobj_priv*
-+ * @hwport:	port
-+ * @addr:	buffer for storing MAC address
-+ *
-+ * Get MAC address of specific port from HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_portid port;
-+	union halmac_wlan_addr hwa;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	if (!addr)
-+		goto out;
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+	port = _hw_port_drv2halmac(hwport);
-+	_rtw_memset(&hwa, 0, sizeof(hwa));
-+
-+	status = api->halmac_get_mac_addr(halmac, port, &hwa);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	_rtw_memcpy(addr, hwa.addr, 6);
-+
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+/**
-+ * rtw_halmac_get_network_type() - Get network type of specific port
-+ * @d:		struct dvobj_priv*
-+ * @hwport:	port
-+ * @type:	buffer to put network type (_HW_STATE_*)
-+ *
-+ * Get network type of specific port from HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type)
-+{
-+#if 0
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_portid port;
-+	enum halmac_network_type_select network;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+	port = _hw_port_drv2halmac(hwport);
-+	network = HALMAC_NETWORK_UNDEFINE;
-+
-+	status = api->halmac_get_net_type(halmac, port, &network);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	*type = _network_type_halmac2drv(network);
-+
-+	err = 0;
-+out:
-+	return err;
-+#else
-+	struct _ADAPTER *a;
-+	enum halmac_portid port;
-+	enum halmac_network_type_select network;
-+	u32 val;
-+	int err = -1;
-+
-+
-+	a = dvobj_get_primary_adapter(d);
-+	port = _hw_port_drv2halmac(hwport);
-+	network = HALMAC_NETWORK_UNDEFINE;
-+
-+	switch (port) {
-+	case HALMAC_PORTID0:
-+		val = rtw_read32(a, REG_CR);
-+		network = BIT_GET_NETYPE0(val);
-+		break;
-+
-+	case HALMAC_PORTID1:
-+		val = rtw_read32(a, REG_CR);
-+		network = BIT_GET_NETYPE1(val);
-+		break;
-+
-+	case HALMAC_PORTID2:
-+		val = rtw_read32(a, REG_CR_EXT);
-+		network = BIT_GET_NETYPE2(val);
-+		break;
-+
-+	case HALMAC_PORTID3:
-+		val = rtw_read32(a, REG_CR_EXT);
-+		network = BIT_GET_NETYPE3(val);
-+		break;
-+
-+	case HALMAC_PORTID4:
-+		val = rtw_read32(a, REG_CR_EXT);
-+		network = BIT_GET_NETYPE4(val);
-+		break;
-+
-+	default:
-+		goto out;
-+	}
-+
-+	*type = _network_type_halmac2drv(network);
-+
-+	err = 0;
-+out:
-+	return err;
-+#endif
-+}
-+
-+/**
-+ * rtw_halmac_get_bcn_ctrl() - Get beacon control setting of specific port
-+ * @d:		struct dvobj_priv*
-+ * @hwport:	port
-+ * @bcn_ctrl:	setting of beacon control
-+ *
-+ * Get beacon control setting of specific port from HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,
-+			struct rtw_halmac_bcn_ctrl *bcn_ctrl)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_portid port;
-+	struct halmac_bcn_ctrl ctrl;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+	port = _hw_port_drv2halmac(hwport);
-+	_rtw_memset(&ctrl, 0, sizeof(ctrl));
-+
-+	status = api->halmac_rw_bcn_ctrl(halmac, port, 0, &ctrl);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+	_beacon_ctrl_halmac2drv(&ctrl, bcn_ctrl);
-+
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+/*
-+ * Note:
-+ *	When this function return, the register REG_RCR may be changed.
-+ */
-+int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_cfg_drv_info(halmac, info);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	err = 0;
-+out:
-+	/* Sync driver RCR cache with register setting */
-+	rtw_hal_get_hwreg(dvobj_get_primary_adapter(d), HW_VAR_RCR, NULL);
-+
-+	return err;
-+}
-+
-+/**
-+ * rtw_halmac_set_max_dl_fw_size() - Set the MAX download firmware size
-+ * @d:		struct dvobj_priv*
-+ * @size:	the max download firmware size in one I/O
-+ *
-+ * Set the max download firmware size in one I/O.
-+ * Please also consider the max size of the callback function "SEND_RSVD_PAGE"
-+ * could accept, because download firmware would call "SEND_RSVD_PAGE" to send
-+ * firmware to IC.
-+ *
-+ * If the value of "size" is not even, it would be rounded down to nearest
-+ * even, and 0 and 1 are both invalid value.
-+ *
-+ * Return 0 for setting OK, otherwise fail.
-+ */
-+int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+
-+
-+	if (!size || (size == 1))
-+		return -1;
-+
-+	mac = dvobj_to_halmac(d);
-+	if (!mac) {
-+		RTW_ERR("%s: HALMAC is not ready!!\n", __FUNCTION__);
-+		return -1;
-+	}
-+	api = HALMAC_GET_API(mac);
-+
-+	size &= ~1; /* round down to even */
-+	status = api->halmac_cfg_max_dl_size(mac, size);
-+	if (status != HALMAC_RET_SUCCESS) {
-+		RTW_WARN("%s: Fail to cfg_max_dl_size(%d), err=%d!!\n",
-+			 __FUNCTION__, size, status);
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_set_mac_address() - Set mac address of specific port
-+ * @d:		struct dvobj_priv*
-+ * @hwport:	port
-+ * @addr:	mac address
-+ *
-+ * Set self mac address of specific port to HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_portid port;
-+	union halmac_wlan_addr hwa;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	port = _hw_port_drv2halmac(hwport);
-+	_rtw_memset(&hwa, 0, sizeof(hwa));
-+	_rtw_memcpy(hwa.addr, addr, 6);
-+
-+	status = api->halmac_cfg_mac_addr(halmac, port, &hwa);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+/**
-+ * rtw_halmac_set_bssid() - Set BSSID of specific port
-+ * @d:		struct dvobj_priv*
-+ * @hwport:	port
-+ * @addr:	BSSID, mac address of AP
-+ *
-+ * Set BSSID of specific port to HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_portid port;
-+	union halmac_wlan_addr hwa;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+	port = _hw_port_drv2halmac(hwport);
-+
-+	_rtw_memset(&hwa, 0, sizeof(hwa));
-+	_rtw_memcpy(hwa.addr, addr, 6);
-+	status = api->halmac_cfg_bssid(halmac, port, &hwa);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+/**
-+ * rtw_halmac_set_tx_address() - Set transmitter address of specific port
-+ * @d:		struct dvobj_priv*
-+ * @hwport:	port
-+ * @addr:	transmitter address
-+ *
-+ * Set transmitter address of specific port to HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_portid port;
-+	union halmac_wlan_addr hwa;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+	port = _hw_port_drv2halmac(hwport);
-+	_rtw_memset(&hwa, 0, sizeof(hwa));
-+	_rtw_memcpy(hwa.addr, addr, 6);
-+
-+	status = api->halmac_cfg_transmitter_addr(halmac, port, &hwa);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+/**
-+ * rtw_halmac_set_network_type() - Set network type of specific port
-+ * @d:		struct dvobj_priv*
-+ * @hwport:	port
-+ * @type:	network type (_HW_STATE_*)
-+ *
-+ * Set network type of specific port to HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_portid port;
-+	enum halmac_network_type_select network;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+	port = _hw_port_drv2halmac(hwport);
-+	network = _network_type_drv2halmac(type);
-+
-+	status = api->halmac_cfg_net_type(halmac, port, network);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+/**
-+ * rtw_halmac_reset_tsf() - Reset TSF timer of specific port
-+ * @d:		struct dvobj_priv*
-+ * @hwport:	port
-+ *
-+ * Notice HALMAC to reset timing synchronization function(TSF) timer of
-+ * specific port.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_portid port;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+	port = _hw_port_drv2halmac(hwport);
-+
-+	status = api->halmac_cfg_tsf_rst(halmac, port);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+/**
-+ * rtw_halmac_set_bcn_interval() - Set beacon interval of each port
-+ * @d:		struct dvobj_priv*
-+ * @hwport:	port
-+ * @space:	beacon interval, unit is ms
-+ *
-+ * Set beacon interval of specific port to HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport,
-+				u32 interval)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_portid port;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+	port = _hw_port_drv2halmac(hwport);
-+
-+	status = api->halmac_cfg_bcn_space(halmac, port, interval);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+/**
-+ * rtw_halmac_set_bcn_ctrl() - Set beacon control setting of each port
-+ * @d:		struct dvobj_priv*
-+ * @hwport:	port
-+ * @bcn_ctrl:	setting of beacon control
-+ *
-+ * Set beacon control setting of specific port to HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,
-+			struct rtw_halmac_bcn_ctrl *bcn_ctrl)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_portid port;
-+	struct halmac_bcn_ctrl ctrl;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+	port = _hw_port_drv2halmac(hwport);
-+	_rtw_memset(&ctrl, 0, sizeof(ctrl));
-+	_beacon_ctrl_drv2halmac(bcn_ctrl, &ctrl);
-+
-+	status = api->halmac_rw_bcn_ctrl(halmac, port, 1, &ctrl);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+/**
-+ * rtw_halmac_set_aid() - Set association identifier(AID) of specific port
-+ * @d:		struct dvobj_priv*
-+ * @hwport:	port
-+ * @aid:	Association identifier
-+ *
-+ * Set association identifier(AID) of specific port to HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_portid port;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+	port = _hw_port_drv2halmac(hwport);
-+
-+#if 0
-+	status = api->halmac_cfg_aid(halmac, port, aid);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+#else
-+{
-+	struct _ADAPTER *a;
-+	u32 addr;
-+	u16 val;
-+
-+	a = dvobj_get_primary_adapter(d);
-+
-+	switch (port) {
-+	case 0:
-+		addr = REG_BCN_PSR_RPT;
-+		val = rtw_read16(a, addr);
-+		val = BIT_SET_PS_AID_0(val, aid);
-+		rtw_write16(a, addr, val);
-+		break;
-+
-+	case 1:
-+		addr = REG_BCN_PSR_RPT1;
-+		val = rtw_read16(a, addr);
-+		val = BIT_SET_PS_AID_1(val, aid);
-+		rtw_write16(a, addr, val);
-+		break;
-+
-+	case 2:
-+		addr = REG_BCN_PSR_RPT2;
-+		val = rtw_read16(a, addr);
-+		val = BIT_SET_PS_AID_2(val, aid);
-+		rtw_write16(a, addr, val);
-+		break;
-+
-+	case 3:
-+		addr = REG_BCN_PSR_RPT3;
-+		val = rtw_read16(a, addr);
-+		val = BIT_SET_PS_AID_3(val, aid);
-+		rtw_write16(a, addr, val);
-+		break;
-+
-+	case 4:
-+		addr = REG_BCN_PSR_RPT4;
-+		val = rtw_read16(a, addr);
-+		val = BIT_SET_PS_AID_4(val, aid);
-+		rtw_write16(a, addr, val);
-+		break;
-+
-+	default:
-+		goto out;
-+	}
-+}
-+#endif
-+
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_cfg_ch_bw(mac, channel, pri_ch_idx, bw);
-+	if (HALMAC_RET_SUCCESS != status)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_set_edca() - config edca parameter
-+ * @d:		struct dvobj_priv*
-+ * @queue:	XMIT_[VO/VI/BE/BK]_QUEUE
-+ * @aifs:	Arbitration inter-frame space(AIFS)
-+ * @cw:		Contention window(CW)
-+ * @txop:	MAX Transmit Opportunity(TXOP)
-+ *
-+ * Return: 0 if process OK, otherwise -1.
-+ */
-+int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_acq_id ac;
-+	struct halmac_edca_para edca;
-+	enum halmac_ret_status status;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	switch (queue) {
-+	case XMIT_VO_QUEUE:
-+		ac = HALMAC_ACQ_ID_VO;
-+		break;
-+	case XMIT_VI_QUEUE:
-+		ac = HALMAC_ACQ_ID_VI;
-+		break;
-+	case XMIT_BE_QUEUE:
-+		ac = HALMAC_ACQ_ID_BE;
-+		break;
-+	case XMIT_BK_QUEUE:
-+		ac = HALMAC_ACQ_ID_BK;
-+		break;
-+	default:
-+		return -1;
-+	}
-+
-+	edca.aifs = aifs;
-+	edca.cw = cw;
-+	edca.txop_limit = txop;
-+
-+	status = api->halmac_cfg_edca_para(mac, ac, &edca);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_set_rts_full_bw() - Send RTS to all covered channels
-+ * @d:		struct dvobj_priv*
-+ * @enable:	_TRUE(enable), _FALSE(disable)
-+ *
-+ * Hradware will duplicate RTS packet to all channels which are covered in used
-+ * bandwidth.
-+ *
-+ * Return 0 if process OK, otherwise -1.
-+ */
-+int rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u8 full;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+	full = (enable == _TRUE) ? 1 : 0;
-+
-+	status = api->halmac_set_hw_value(mac, HALMAC_HW_RTS_FULL_BW, &full);
-+	if (HALMAC_RET_SUCCESS != status)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+#ifdef RTW_HALMAC_DBG_POWER_SWITCH
-+static void _dump_mac_reg(struct dvobj_priv *d, u32 start, u32 end)
-+{
-+	struct _ADAPTER *adapter;
-+	int i, j = 1;
-+
-+
-+	adapter = dvobj_get_primary_adapter(d);
-+	for (i = start; i < end; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT("0x%04x", i);
-+		_RTW_PRINT(" 0x%08x ", rtw_read32(adapter, i));
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT("\n");
-+	}
-+}
-+
-+void dump_dbg_val(struct _ADAPTER *a, u32 reg)
-+{
-+	u32 v32;
-+
-+
-+	rtw_write8(a, 0x3A, reg);
-+	v32 = rtw_read32(a, 0xC0);
-+	RTW_PRINT("0x3A = %02x, 0xC0 = 0x%08x\n",reg, v32);
-+}
-+
-+#ifdef CONFIG_PCI_HCI
-+static void _dump_pcie_cfg_space(struct dvobj_priv *d)
-+{
-+	struct _ADAPTER *padapter = dvobj_get_primary_adapter(d);
-+	struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct pci_dev  *pdev = pdvobjpriv->ppcidev;
-+	struct pci_dev  *bridge_pdev = pdev->bus->self;
-+
-+        u32 tmp[4] = { 0 };
-+        u32 i, j;
-+
-+	RTW_PRINT("\n*****  PCI Device Configuration Space *****\n\n");
-+
-+        for(i = 0; i < 0x100; i += 0x10)
-+        {
-+                for (j = 0 ; j < 4 ; j++)
-+                        pci_read_config_dword(pdev, i + j * 4, tmp+j);
-+
-+        	RTW_PRINT("%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
-+                        i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,
-+                        tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,
-+                        tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,
-+                        tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);
-+        }
-+
-+	RTW_PRINT("\n*****  PCI Host Device Configuration Space*****\n\n");
-+
-+        for(i = 0; i < 0x100; i += 0x10)
-+        {
-+                for (j = 0 ; j < 4 ; j++)
-+                        pci_read_config_dword(bridge_pdev, i + j * 4, tmp+j);
-+
-+        	RTW_PRINT("%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
-+                        i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF,
-+                        tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF,
-+                        tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF,
-+                        tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF);
-+        }
-+}
-+#endif
-+
-+static void _dump_mac_reg_for_power_switch(struct dvobj_priv *d,
-+					   const char* caller, char* desc)
-+{
-+	struct _ADAPTER *a;
-+	u8 v8;
-+
-+
-+	RTW_PRINT("%s: %s\n", caller, desc);
-+	RTW_PRINT("======= MAC REG =======\n");
-+	/* page 0/1 */
-+	_dump_mac_reg(d, 0x0, 0x200);
-+	_dump_mac_reg(d, 0x300, 0x400); /* also dump page 3 */
-+
-+	/* dump debug register */
-+	a = dvobj_get_primary_adapter(d);
-+
-+#ifdef CONFIG_PCI_HCI
-+	_dump_pcie_cfg_space(d);
-+
-+	v8 = rtw_read8(a, 0xF6) | 0x01;
-+	rtw_write8(a, 0xF6, v8);
-+	RTW_PRINT("0xF6 = %02x\n", v8);
-+
-+	dump_dbg_val(a, 0x63);
-+	dump_dbg_val(a, 0x64);
-+	dump_dbg_val(a, 0x68);
-+	dump_dbg_val(a, 0x69);
-+	dump_dbg_val(a, 0x6a);
-+	dump_dbg_val(a, 0x6b);
-+	dump_dbg_val(a, 0x71);
-+	dump_dbg_val(a, 0x72);
-+#endif
-+}
-+
-+static enum halmac_ret_status _power_switch(struct halmac_adapter *halmac,
-+					    struct halmac_api *api,
-+					    enum halmac_mac_power pwr)
-+{
-+	enum halmac_ret_status status;
-+	char desc[80] = {0};
-+
-+
-+	rtw_sprintf(desc, 80, "before calling power %s",
-+				(pwr==HALMAC_MAC_POWER_ON)?"on":"off");
-+	_dump_mac_reg_for_power_switch((struct dvobj_priv *)halmac->drv_adapter,
-+			__FUNCTION__, desc);
-+
-+	status = api->halmac_mac_power_switch(halmac, pwr);
-+	RTW_PRINT("%s: status=%d\n", __FUNCTION__, status);
-+
-+	rtw_sprintf(desc, 80, "after calling power %s",
-+				(pwr==HALMAC_MAC_POWER_ON)?"on":"off");
-+	_dump_mac_reg_for_power_switch((struct dvobj_priv *)halmac->drv_adapter,
-+			__FUNCTION__, desc);
-+
-+	return status;
-+}
-+#else /* !RTW_HALMAC_DBG_POWER_SWITCH */
-+#define _power_switch(mac, api, pwr)	(api)->halmac_mac_power_switch(mac, pwr)
-+#endif /* !RTW_HALMAC_DBG_POWER_SWITCH */
-+
-+/*
-+ * Description:
-+ *	Power on device hardware.
-+ *	[Notice!] If device's power state is on before,
-+ *	it would be power off first and turn on power again.
-+ *
-+ * Return:
-+ *	0	power on success
-+ *	-1	power on fail
-+ *	-2	power state unchange
-+ */
-+int rtw_halmac_poweron(struct dvobj_priv *d)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)
-+	struct _ADAPTER *a;
-+	u8 v8;
-+	u32 addr;
-+
-+	a = dvobj_get_primary_adapter(d);
-+#endif
-+
-+	halmac = dvobj_to_halmac(d);
-+	if (!halmac)
-+		goto out;
-+
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_pre_init_system_cfg(halmac);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+#ifdef CONFIG_SDIO_HCI
-+	status = api->halmac_sdio_cmd53_4byte(halmac, HALMAC_SDIO_CMD53_4BYTE_MODE_RW);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+#endif /* CONFIG_SDIO_HCI */
-+
-+#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)
-+	addr = 0x3F3;
-+	v8 = rtw_read8(a, addr);
-+	RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
-+	/* are we in pcie debug mode? */
-+	if (!(v8 & BIT(2))) {
-+		RTW_PRINT("%s: Enable pcie debug mode\n", __FUNCTION__);
-+		v8 |= BIT(2);
-+		v8 = rtw_write8(a, addr, v8);
-+	}
-+#endif
-+
-+	status = _power_switch(halmac, api, HALMAC_MAC_POWER_ON);
-+	if (HALMAC_RET_PWR_UNCHANGE == status) {
-+
-+#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B)
-+		addr = 0x3F3;
-+		v8 = rtw_read8(a, addr);
-+		RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
-+		
-+		/* are we in pcie debug mode? */
-+		if (!(v8 & BIT(2))) {
-+			RTW_PRINT("%s: Enable pcie debug mode\n", __FUNCTION__);
-+			v8 |= BIT(2);
-+			v8 = rtw_write8(a, addr, v8);
-+		} else if (v8 & BIT(0)) {
-+			/* DMA stuck */
-+			addr = 0x1350;
-+			v8 = rtw_read8(a, addr);
-+			RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
-+			RTW_PRINT("%s: recover DMA stuck\n", __FUNCTION__);
-+			v8 |= BIT(6);
-+			v8 = rtw_write8(a, addr, v8);
-+			RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8);
-+		}
-+#endif
-+		/*
-+		 * Work around for warm reboot but device not power off,
-+		 * but it would also fall into this case when auto power on is enabled.
-+		 */
-+		_power_switch(halmac, api, HALMAC_MAC_POWER_OFF);
-+		status = _power_switch(halmac, api, HALMAC_MAC_POWER_ON);
-+		RTW_WARN("%s: Power state abnormal, try to recover...%s\n",
-+			 __FUNCTION__, (HALMAC_RET_SUCCESS == status)?"OK":"FAIL!");
-+	}
-+	if (HALMAC_RET_SUCCESS != status) {
-+		if (HALMAC_RET_PWR_UNCHANGE == status)
-+			err = -2;
-+		goto out;
-+	}
-+
-+	status = api->halmac_init_system_cfg(halmac);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+/*
-+ * Description:
-+ *	Power off device hardware.
-+ *
-+ * Return:
-+ *	0	Power off success
-+ *	-1	Power off fail
-+ */
-+int rtw_halmac_poweroff(struct dvobj_priv *d)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	if (!halmac)
-+		goto out;
-+
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = _power_switch(halmac, api, HALMAC_MAC_POWER_OFF);
-+	if ((HALMAC_RET_SUCCESS != status)
-+	    && (HALMAC_RET_PWR_UNCHANGE != status))
-+		goto out;
-+
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+#ifdef CONFIG_SUPPORT_TRX_SHARED
-+static inline enum halmac_rx_fifo_expanding_mode _trx_share_mode_drv2halmac(u8 trx_share_mode)
-+{
-+	if (0 == trx_share_mode)
-+		return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;
-+	else if (1 == trx_share_mode)
-+		return HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK;
-+	else if (2 == trx_share_mode)
-+		return HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK;
-+	else if (3 == trx_share_mode)
-+		return HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK;
-+	else
-+		return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;
-+}
-+
-+static enum halmac_rx_fifo_expanding_mode _rtw_get_trx_share_mode(struct _ADAPTER *adapter)
-+{
-+	struct registry_priv *registry_par = &adapter->registrypriv;
-+
-+	return _trx_share_mode_drv2halmac(registry_par->trx_share_mode);
-+}
-+
-+void dump_trx_share_mode(void *sel, struct _ADAPTER *adapter)
-+{
-+	struct registry_priv  *registry_par = &adapter->registrypriv;
-+	u8 mode = _trx_share_mode_drv2halmac(registry_par->trx_share_mode);
-+
-+	if (HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK == mode)
-+		RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_1");
-+	else if (HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK == mode)
-+		RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_2");
-+	else if (HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK == mode)
-+		RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_3");
-+	else
-+		RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "DISABLE");
-+}
-+#endif
-+
-+static enum halmac_drv_rsvd_pg_num _rsvd_page_num_drv2halmac(u16 num)
-+{
-+	if (num <= 8)
-+		return HALMAC_RSVD_PG_NUM8;
-+	if (num <= 16)
-+		return HALMAC_RSVD_PG_NUM16;
-+	if (num <= 24)
-+		return HALMAC_RSVD_PG_NUM24;
-+	if (num <= 32)
-+		return HALMAC_RSVD_PG_NUM32;
-+	if (num <= 64)
-+		return HALMAC_RSVD_PG_NUM64;
-+	if (num <= 128)
-+		return HALMAC_RSVD_PG_NUM128;
-+
-+	if (num > 256)
-+		RTW_WARN("%s: Fail to allocate RSVD page(%d)!!"
-+			 " The MAX RSVD page number is 256...\n",
-+			 __FUNCTION__, num);
-+
-+	return HALMAC_RSVD_PG_NUM256;
-+}
-+
-+static u16 _rsvd_page_num_halmac2drv(enum halmac_drv_rsvd_pg_num rsvd_page_number)
-+{
-+	u16 num = 0;
-+
-+
-+	switch (rsvd_page_number) {
-+	case HALMAC_RSVD_PG_NUM8:
-+		num = 8;
-+		break;
-+
-+	case HALMAC_RSVD_PG_NUM16:
-+		num = 16;
-+		break;
-+
-+	case HALMAC_RSVD_PG_NUM24:
-+		num = 24;
-+		break;
-+
-+	case HALMAC_RSVD_PG_NUM32:
-+		num = 32;
-+		break;
-+
-+	case HALMAC_RSVD_PG_NUM64:
-+		num = 64;
-+		break;
-+
-+	case HALMAC_RSVD_PG_NUM128:
-+		num = 128;
-+		break;
-+
-+	case HALMAC_RSVD_PG_NUM256:
-+		num = 256;
-+		break;
-+	}
-+
-+	return num;
-+}
-+
-+static enum halmac_trx_mode _choose_trx_mode(struct dvobj_priv *d)
-+{
-+	PADAPTER p;
-+
-+
-+	p = dvobj_get_primary_adapter(d);
-+
-+	if (p->registrypriv.wifi_spec)
-+		return HALMAC_TRX_MODE_WMM;
-+
-+#ifdef CONFIG_SUPPORT_TRX_SHARED
-+	if (_rtw_get_trx_share_mode(p))
-+		return HALMAC_TRX_MODE_TRXSHARE;
-+#endif
-+
-+	return HALMAC_TRX_MODE_NORMAL;
-+}
-+
-+static inline enum halmac_rf_type _rf_type_drv2halmac(enum rf_type rf_drv)
-+{
-+	enum halmac_rf_type rf_mac;
-+
-+
-+	switch (rf_drv) {
-+	case RF_1T1R:
-+		rf_mac = HALMAC_RF_1T1R;
-+		break;
-+	case RF_1T2R:
-+		rf_mac = HALMAC_RF_1T2R;
-+		break;
-+	case RF_2T2R:
-+		rf_mac = HALMAC_RF_2T2R;
-+		break;
-+	case RF_2T3R:
-+		rf_mac = HALMAC_RF_2T3R;
-+		break;
-+	case RF_2T4R:
-+		rf_mac = HALMAC_RF_2T4R;
-+		break;
-+	case RF_3T3R:
-+		rf_mac = HALMAC_RF_3T3R;
-+		break;
-+	case RF_3T4R:
-+		rf_mac = HALMAC_RF_3T4R;
-+		break;
-+	case RF_4T4R:
-+		rf_mac = HALMAC_RF_4T4R;
-+		break;
-+	default:
-+		rf_mac = HALMAC_RF_MAX_TYPE;
-+		RTW_ERR("%s: Invalid RF type(0x%x)!\n", __FUNCTION__, rf_drv);
-+		break;
-+	}
-+
-+	return rf_mac;
-+}
-+
-+static inline enum rf_type _rf_type_halmac2drv(enum halmac_rf_type rf_mac)
-+{
-+	enum rf_type rf_drv;
-+
-+
-+	switch (rf_mac) {
-+	case HALMAC_RF_1T2R:
-+		rf_drv = RF_1T2R;
-+		break;
-+	case HALMAC_RF_2T4R:
-+		rf_drv = RF_2T4R;
-+		break;
-+	case HALMAC_RF_2T2R:
-+	case HALMAC_RF_2T2R_GREEN:
-+		rf_drv = RF_2T2R;
-+		break;
-+	case HALMAC_RF_2T3R:
-+		rf_drv = RF_2T3R;
-+		break;
-+	case HALMAC_RF_1T1R:
-+		rf_drv = RF_1T1R;
-+		break;
-+	case HALMAC_RF_3T3R:
-+		rf_drv = RF_3T3R;
-+		break;
-+	case HALMAC_RF_3T4R:
-+		rf_drv = RF_3T4R;
-+		break;
-+	case HALMAC_RF_4T4R:
-+		rf_drv = RF_4T4R;
-+		break;
-+	default:
-+		rf_drv = RF_TYPE_MAX;
-+		RTW_ERR("%s: Invalid RF type(0x%x)!\n", __FUNCTION__, rf_mac);
-+		break;
-+	}
-+
-+	return rf_drv;
-+}
-+
-+static enum odm_cut_version _cut_version_drv2phydm(
-+				enum tag_HAL_Cut_Version_Definition cut_drv)
-+{
-+	enum odm_cut_version cut_phydm = ODM_CUT_A;
-+	u32 diff;
-+
-+
-+	if (cut_drv > K_CUT_VERSION)
-+		RTW_WARN("%s: unknown cut_ver=%d !!\n", __FUNCTION__, cut_drv);
-+
-+	diff = cut_drv - A_CUT_VERSION;
-+	cut_phydm += diff;
-+
-+	return cut_phydm;
-+}
-+
-+static int _send_general_info_by_reg(struct dvobj_priv *d,
-+				     struct halmac_general_info *info)
-+{
-+	struct _ADAPTER *a;
-+	struct hal_com_data *hal;
-+	enum tag_HAL_Cut_Version_Definition cut_drv;
-+	enum rf_type rftype;
-+	enum odm_cut_version cut_phydm;
-+	u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0};
-+
-+
-+	a = dvobj_get_primary_adapter(d);
-+	hal = GET_HAL_DATA(a);
-+	rftype = _rf_type_halmac2drv(info->rf_type);
-+	cut_drv = GET_CVID_CUT_VERSION(hal->version_id);
-+	cut_phydm = _cut_version_drv2phydm(cut_drv);
-+
-+#define CLASS_GENERAL_INFO_REG				0x02
-+#define CMD_ID_GENERAL_INFO_REG				0x0C
-+#define GENERAL_INFO_REG_SET_CMD_ID(buf, v)		SET_BITS_TO_LE_4BYTE(buf, 0, 5, v)
-+#define GENERAL_INFO_REG_SET_CLASS(buf, v)		SET_BITS_TO_LE_4BYTE(buf, 5, 3, v)
-+#define GENERAL_INFO_REG_SET_RFE_TYPE(buf, v)		SET_BITS_TO_LE_4BYTE(buf, 8, 8, v)
-+#define GENERAL_INFO_REG_SET_RF_TYPE(buf, v)		SET_BITS_TO_LE_4BYTE(buf, 16, 8, v)
-+#define GENERAL_INFO_REG_SET_CUT_VERSION(buf, v)	SET_BITS_TO_LE_4BYTE(buf, 24, 8, v)
-+#define GENERAL_INFO_REG_SET_RX_ANT_STATUS(buf, v)	SET_BITS_TO_LE_1BYTE(buf+4, 0, 4, v)
-+#define GENERAL_INFO_REG_SET_TX_ANT_STATUS(buf, v)	SET_BITS_TO_LE_1BYTE(buf+4, 4, 4, v)
-+
-+	GENERAL_INFO_REG_SET_CMD_ID(h2c, CMD_ID_GENERAL_INFO_REG);
-+	GENERAL_INFO_REG_SET_CLASS(h2c, CLASS_GENERAL_INFO_REG);
-+	GENERAL_INFO_REG_SET_RFE_TYPE(h2c, info->rfe_type);
-+	GENERAL_INFO_REG_SET_RF_TYPE(h2c, rftype);
-+	GENERAL_INFO_REG_SET_CUT_VERSION(h2c, cut_phydm);
-+	GENERAL_INFO_REG_SET_RX_ANT_STATUS(h2c, info->rx_ant_status);
-+	GENERAL_INFO_REG_SET_TX_ANT_STATUS(h2c, info->tx_ant_status);
-+
-+	return rtw_halmac_send_h2c(d, h2c);
-+}
-+
-+static int _send_general_info(struct dvobj_priv *d)
-+{
-+	struct _ADAPTER *adapter;
-+	struct hal_com_data *hal;
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	struct halmac_general_info info;
-+	enum halmac_ret_status status;
-+	enum rf_type rf = RF_1T1R;
-+	enum bb_path txpath = BB_PATH_A;
-+	enum bb_path rxpath = BB_PATH_A;
-+	int err;
-+
-+
-+	adapter = dvobj_get_primary_adapter(d);
-+	hal = GET_HAL_DATA(adapter);
-+	halmac = dvobj_to_halmac(d);
-+	if (!halmac)
-+		return -1;
-+	api = HALMAC_GET_API(halmac);
-+
-+	_rtw_memset(&info, 0, sizeof(info));
-+	info.rfe_type = (u8)hal->rfe_type;
-+	rtw_hal_get_trx_path(d, &rf, &txpath, &rxpath);
-+	info.rf_type = _rf_type_drv2halmac(rf);
-+	info.tx_ant_status = (u8)txpath;
-+	info.rx_ant_status = (u8)rxpath;
-+	info.ext_pa = 0;	/* 2.4G or 5G? format not known */
-+	info.package_type = hal->PackageType;
-+	info.mp_mode = adapter->registrypriv.mp_mode;
-+
-+	status = api->halmac_send_general_info(halmac, &info);
-+	switch (status) {
-+	case HALMAC_RET_SUCCESS:
-+		break;
-+	case HALMAC_RET_NO_DLFW:
-+		RTW_WARN("%s: halmac_send_general_info() fail because fw not dl!\n",
-+			 __FUNCTION__);
-+		/* fall through */
-+	default:
-+		return -1;
-+	}
-+
-+	err = _send_general_info_by_reg(d, &info);
-+	if (err) {
-+		RTW_ERR("%s: Fail to send general info by register!\n",
-+			 __FUNCTION__);
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+static int _cfg_drv_rsvd_pg_num(struct dvobj_priv *d)
-+{
-+	struct _ADAPTER *a;
-+	struct hal_com_data *hal;
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_drv_rsvd_pg_num rsvd_page_number;
-+	enum halmac_ret_status status;
-+	u16 drv_rsvd_num;
-+	int ret = 0;
-+
-+
-+	a = dvobj_get_primary_adapter(d);
-+	hal = GET_HAL_DATA(a);
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	drv_rsvd_num = rtw_hal_get_rsvd_page_num(a);
-+	rsvd_page_number = _rsvd_page_num_drv2halmac(drv_rsvd_num);
-+	status = api->halmac_cfg_drv_rsvd_pg_num(halmac, rsvd_page_number);
-+	if (status != HALMAC_RET_SUCCESS) {
-+		ret = -1;
-+		goto exit;
-+	}
-+	hal->drv_rsvd_page_number = _rsvd_page_num_halmac2drv(rsvd_page_number);
-+
-+exit:
-+#ifndef DBG_RSVD_PAGE_CFG
-+	if (drv_rsvd_num != _rsvd_page_num_halmac2drv(rsvd_page_number))
-+#endif
-+		RTW_INFO("%s: request %d pages => halmac %d pages %s\n"
-+			, __FUNCTION__, drv_rsvd_num, _rsvd_page_num_halmac2drv(rsvd_page_number)
-+			, ret ? "fail" : "success");
-+
-+	return ret;
-+}
-+
-+static void _debug_dlfw_fail(struct dvobj_priv *d)
-+{
-+	struct _ADAPTER *a;
-+	u32 addr;
-+	u32 v32, i, n;
-+
-+
-+	a = dvobj_get_primary_adapter(d);
-+
-+	/* read 0x80[15:0], 0x10F8[31:0] once */
-+	addr = 0x80;
-+	v32 = rtw_read16(a, addr);
-+	RTW_PRINT("%s: 0x%X = 0x%04x\n", __FUNCTION__, addr, v32);
-+
-+	addr = 0x10F8;
-+	v32 = rtw_read32(a, addr);
-+	RTW_PRINT("%s: 0x%X = 0x%08x\n", __FUNCTION__, addr, v32);
-+
-+	/* read 0x10FC[31:0], 5 times */
-+	addr = 0x10FC;
-+	n = 5;
-+	for (i = 0; i < n; i++) {
-+		v32 = rtw_read32(a, addr);
-+		RTW_PRINT("%s: 0x%X = 0x%08x (%u/%u)\n",
-+			  __FUNCTION__, addr, v32, i, n);
-+	}
-+
-+	/*
-+	 * write 0x3A[7:0]=0x28 and 0xF6[7:0]=0x01
-+	 * and then read 0xC0[31:0] 5 times
-+	 */
-+	addr = 0x3A;
-+	v32 = 0x28;
-+	rtw_write8(a, addr, (u8)v32);
-+	v32 = rtw_read8(a, addr);
-+	RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v32);
-+
-+	addr = 0xF6;
-+	v32 = 0x1;
-+	rtw_write8(a, addr, (u8)v32);
-+	v32 = rtw_read8(a, addr);
-+	RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v32);
-+
-+	addr = 0xC0;
-+	n = 5;
-+	for (i = 0; i < n; i++) {
-+		v32 = rtw_read32(a, addr);
-+		RTW_PRINT("%s: 0x%X = 0x%08x (%u/%u)\n",
-+			  __FUNCTION__, addr, v32, i, n);
-+	}
-+
-+	mac_reg_dump(NULL, a);
-+#ifdef CONFIG_SDIO_HCI
-+	RTW_PRINT("======= SDIO Local REG =======\n");
-+	sdio_local_reg_dump(NULL, a);
-+	RTW_PRINT("======= SDIO CCCR REG =======\n");
-+	sd_f0_reg_dump(NULL, a);
-+#endif /* CONFIG_SDIO_HCI */
-+
-+	/* read 0x80 after 10 secs */
-+	rtw_msleep_os(10000);
-+	addr = 0x80;
-+	v32 = rtw_read16(a, addr);
-+	RTW_PRINT("%s: 0x%X = 0x%04x (after 10 secs)\n",
-+		  __FUNCTION__, addr, v32);
-+}
-+
-+static enum halmac_ret_status _enter_cpu_sleep_mode(struct dvobj_priv *d)
-+{
-+	struct hal_com_data *hal;
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+
-+
-+	hal = GET_HAL_DATA(dvobj_get_primary_adapter(d));
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+#ifdef CONFIG_RTL8822B
-+	/* Support after firmware version 21 */
-+	if (hal->firmware_version < 21)
-+		return HALMAC_RET_NOT_SUPPORT;
-+#elif defined(CONFIG_RTL8821C)
-+	/* Support after firmware version 13.6 or 16 */
-+	if (hal->firmware_version == 13) {
-+		if (hal->firmware_sub_version < 6)
-+			return HALMAC_RET_NOT_SUPPORT;
-+	} else if (hal->firmware_version < 16) {
-+		return HALMAC_RET_NOT_SUPPORT;
-+	}
-+#endif
-+
-+	return api->halmac_enter_cpu_sleep_mode(mac);
-+}
-+
-+/*
-+ * _cpu_sleep() - Let IC CPU enter sleep mode
-+ * @d:		struct dvobj_priv*
-+ * @timeout:	time limit of wait, unit is ms
-+ *		0 for no limit
-+ *
-+ * Return 0 for CPU in sleep mode, otherwise fail to enter sleep mode.
-+ * Error codes definition are as follow:
-+ * 	-1	HALMAC enter sleep return fail
-+ *	-2	HALMAC get CPU mode return fail
-+ *	-110	timeout
-+ */
-+static int _cpu_sleep(struct dvobj_priv *d, u32 timeout)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	enum halmac_wlcpu_mode mode = HALMAC_WLCPU_UNDEFINE;
-+	systime start_t;
-+	s32 period = 0;
-+	u32 cnt = 0;
-+	int err = 0;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	start_t = rtw_get_current_time();
-+
-+	status = _enter_cpu_sleep_mode(d);
-+	if (status != HALMAC_RET_SUCCESS) {
-+		if (status != HALMAC_RET_NOT_SUPPORT)
-+			err = -1;
-+		goto exit;
-+	}
-+
-+	do {
-+		cnt++;
-+
-+		mode = HALMAC_WLCPU_UNDEFINE;
-+		status = api->halmac_get_cpu_mode(mac, &mode);
-+
-+		period = rtw_get_passing_time_ms(start_t);
-+
-+		if (status != HALMAC_RET_SUCCESS) {
-+			err = -2;
-+			break;
-+		}
-+		if (mode == HALMAC_WLCPU_SLEEP)
-+			break;
-+		if (period > timeout) {
-+			err = -110;
-+			break;
-+		}
-+
-+		rtw_msleep_os(1);
-+	} while (1);
-+
-+exit:
-+	if (err)
-+		RTW_ERR("%s: Fail to enter sleep mode! (%d, %d)\n",
-+			__FUNCTION__, status, mode);
-+
-+	RTW_INFO("%s: Cost %dms to polling %u times. (err=%d)\n",
-+		__FUNCTION__, period, cnt, err);
-+
-+	return err;
-+}
-+
-+static void _init_trx_cfg_drv(struct dvobj_priv *d)
-+{
-+#ifdef CONFIG_PCI_HCI
-+	rtw_hal_irp_reset(dvobj_get_primary_adapter(d));
-+#endif
-+}
-+
-+/*
-+ * Description:
-+ *	Downlaod Firmware Flow
-+ *
-+ * Parameters:
-+ *	d	pointer of struct dvobj_priv
-+ *	fw	firmware array
-+ *	fwsize	firmware size
-+ *	re_dl	re-download firmware or not
-+ *		0: run in init hal flow, not re-download
-+ *		1: it is a stand alone operation, not in init hal flow
-+ *
-+ * Return:
-+ *	0	Success
-+ *	others	Fail
-+ */
-+static int download_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize, u8 re_dl)
-+{
-+	PHAL_DATA_TYPE hal;
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	struct halmac_fw_version fw_vesion;
-+	enum halmac_ret_status status;
-+	int err = 0;
-+
-+
-+	hal = GET_HAL_DATA(dvobj_get_primary_adapter(d));
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	if ((!fw) || (!fwsize))
-+		return -1;
-+
-+	/* 1. Driver Stop Tx */
-+	/* ToDo */
-+
-+	/* 2. Driver Check Tx FIFO is empty */
-+	err = rtw_halmac_txfifo_wait_empty(d, 2000); /* wait 2s */
-+	if (err) {
-+		err = -1;
-+		goto resume_tx;
-+	}
-+
-+	/* 3. Config MAX download size */
-+	/*
-+	 * Already done in rtw_halmac_init_adapter() or
-+	 * somewhere calling rtw_halmac_set_max_dl_fw_size().
-+	 */
-+
-+	if (re_dl) {
-+		/* 4. Enter IC CPU sleep mode */
-+		err = _cpu_sleep(d, 2000);
-+		if (err) {
-+			RTW_ERR("%s: IC CPU fail to enter sleep mode!(%d)\n",
-+				__FUNCTION__, err);
-+			/* skip this error */
-+			err = 0;
-+		}
-+	}
-+
-+	/* 5. Download Firmware */
-+	status = api->halmac_download_firmware(mac, fw, fwsize);
-+	if (status != HALMAC_RET_SUCCESS) {
-+		RTW_ERR("%s: download firmware FAIL! status=0x%02x\n",
-+			__FUNCTION__, status);
-+		_debug_dlfw_fail(d);
-+		err = -1;
-+		goto resume_tx;
-+	}
-+
-+	/* 5.1. (Driver) Reset driver variables if needed */
-+	hal->LastHMEBoxNum = 0;
-+
-+	/* 5.2. (Driver) Get FW version */
-+	status = api->halmac_get_fw_version(mac, &fw_vesion);
-+	if (status == HALMAC_RET_SUCCESS) {
-+		hal->firmware_version = fw_vesion.version;
-+		hal->firmware_sub_version = fw_vesion.sub_version;
-+		hal->firmware_size = fwsize;
-+	}
-+
-+resume_tx:
-+	/* 6. Driver resume TX if needed */
-+	/* ToDo */
-+
-+	if (err)
-+		goto exit;
-+
-+	if (re_dl) {
-+		enum halmac_trx_mode mode;
-+
-+		/* 7. Change reserved page size */
-+		err = _cfg_drv_rsvd_pg_num(d);
-+		if (err)
-+			return -1;
-+
-+		/* 8. Init TRX Configuration */
-+		mode = _choose_trx_mode(d);
-+		status = api->halmac_init_trx_cfg(mac, mode);
-+		if (HALMAC_RET_SUCCESS != status)
-+			return -1;
-+		_init_trx_cfg_drv(d);
-+
-+		/* 9. Config RX Aggregation */
-+		err = rtw_halmac_rx_agg_switch(d, _TRUE);
-+		if (err)
-+			return -1;
-+
-+		/* 10. Send General Info */
-+		err = _send_general_info(d);
-+		if (err)
-+			return -1;
-+	}
-+
-+exit:
-+	return err;
-+}
-+
-+static int init_mac_flow(struct dvobj_priv *d)
-+{
-+	PADAPTER p;
-+	struct hal_com_data *hal;
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_drv_rsvd_pg_num rsvd_page_number;
-+	union halmac_wlan_addr hwa;
-+	enum halmac_trx_mode trx_mode;
-+	enum halmac_ret_status status;
-+	u8 drv_rsvd_num;
-+	u8 nettype;
-+	int err, err_ret = -1;
-+
-+
-+	p = dvobj_get_primary_adapter(d);
-+	hal = GET_HAL_DATA(p);
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+#ifdef CONFIG_SUPPORT_TRX_SHARED
-+	status = api->halmac_cfg_rxff_expand_mode(halmac,
-+						  _rtw_get_trx_share_mode(p));
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+#endif
-+
-+#ifdef DBG_LA_MODE
-+	if (dvobj_to_regsty(d)->la_mode_en) {
-+		status = api->halmac_cfg_la_mode(halmac, HALMAC_LA_MODE_PARTIAL);
-+		if (status != HALMAC_RET_SUCCESS) {
-+			RTW_ERR("%s: Fail to enable LA mode!\n", __FUNCTION__);
-+			goto out;
-+		}
-+		RTW_PRINT("%s: Enable LA mode OK.\n", __FUNCTION__);
-+	}
-+#endif
-+
-+	err = _cfg_drv_rsvd_pg_num(d);
-+	if (err)
-+		goto out;
-+
-+#ifdef CONFIG_USB_HCI
-+	status = api->halmac_set_bulkout_num(halmac, d->RtNumOutPipes);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+#endif /* CONFIG_USB_HCI */
-+
-+	trx_mode = _choose_trx_mode(d);
-+	status = api->halmac_init_mac_cfg(halmac, trx_mode);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	/* Driver insert flow: Sync driver setting with register */
-+	/* Sync driver RCR cache with register setting */
-+	rtw_hal_get_hwreg(dvobj_get_primary_adapter(d), HW_VAR_RCR, NULL);
-+
-+#ifdef CONFIG_RTS_FULL_BW
-+	err = rtw_halmac_set_rts_full_bw(d, _TRUE);
-+	if (err)
-+		RTW_WARN("%s: Fail to set RTS FULL BW mode\n", __FUNCTION__);
-+#else
-+	err = rtw_halmac_set_rts_full_bw(d, _FALSE);
-+	if (err)
-+		RTW_WARN("%s: Fail to disable RTS FULL BW mode\n", __FUNCTION__);
-+#endif /* CONFIG_RTS_FULL_BW */
-+
-+	_init_trx_cfg_drv(d);
-+	/* Driver inser flow end */
-+
-+	err = rtw_halmac_rx_agg_switch(d, _TRUE);
-+	if (err)
-+		goto out;
-+
-+	nettype = dvobj_to_regsty(d)->wireless_mode;
-+	if (is_supported_vht(nettype) == _TRUE)
-+		status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_AC);
-+	else if (is_supported_ht(nettype) == _TRUE)
-+		status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_N);
-+	else if (IsSupportedTxOFDM(nettype) == _TRUE)
-+		status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_G);
-+	else
-+		status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_B);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	err_ret = 0;
-+out:
-+	return err_ret;
-+}
-+
-+static int _drv_enable_trx(struct dvobj_priv *d)
-+{
-+	struct _ADAPTER *adapter;
-+	u32 status;
-+
-+
-+	adapter = dvobj_get_primary_adapter(d);
-+	if (adapter->bup == _FALSE) {
-+#ifdef CONFIG_NEW_NETDEV_HDL
-+		status = rtw_mi_start_drv_threads(adapter);
-+#else
-+		status = rtw_start_drv_threads(adapter);
-+#endif
-+		if (status == _FAIL) {
-+			RTW_ERR("%s: Start threads Failed!\n", __FUNCTION__);
-+			return -1;
-+		}
-+	}
-+
-+	rtw_intf_start(adapter);
-+
-+	return 0;
-+}
-+
-+/*
-+ * Notices:
-+ *	Make sure following information
-+ *	1. GET_HAL_RFPATH
-+ *	2. GET_HAL_DATA(dvobj_get_primary_adapter(d))->rfe_type
-+ *	3. GET_HAL_DATA(dvobj_get_primary_adapter(d))->PackageType
-+ *	4. dvobj_get_primary_adapter(d)->registrypriv.mp_mode
-+ *	are all ready before calling this function.
-+ */
-+static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize)
-+{
-+	PADAPTER adapter;
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 ok;
-+	u8 fw_ok = _FALSE;
-+	int err, err_ret = -1;
-+
-+
-+	adapter = dvobj_get_primary_adapter(d);
-+	halmac = dvobj_to_halmac(d);
-+	if (!halmac)
-+		goto out;
-+	api = HALMAC_GET_API(halmac);
-+
-+	/* StatePowerOff */
-+
-+	/* SKIP: halmac_init_adapter (Already done before) */
-+
-+	/* halmac_pre_Init_system_cfg */
-+	/* halmac_mac_power_switch(on) */
-+	/* halmac_Init_system_cfg */
-+	ok = rtw_hal_power_on(adapter);
-+	if (_FAIL == ok)
-+		goto out;
-+
-+	/* StatePowerOn */
-+
-+	/* DownloadFW */
-+	if (fw && fwsize) {
-+		err = download_fw(d, fw, fwsize, 0);
-+		if (err)
-+			goto out;
-+		fw_ok = _TRUE;
-+	}
-+
-+	/* InitMACFlow */
-+	err = init_mac_flow(d);
-+	if (err)
-+		goto out;
-+
-+	/* Driver insert flow: Enable TR/RX */
-+	err = _drv_enable_trx(d);
-+	if (err)
-+		goto out;
-+
-+	/* halmac_send_general_info */
-+	if (_TRUE == fw_ok) {
-+		err = _send_general_info(d);
-+		if (err)
-+			goto out;
-+	}
-+
-+	/* Init Phy parameter-MAC */
-+	ok = rtw_hal_init_mac_register(adapter);
-+	if (_FALSE == ok)
-+		goto out;
-+
-+	/* StateMacInitialized */
-+
-+	/* halmac_cfg_drv_info */
-+	err = rtw_halmac_config_rx_info(d, HALMAC_DRV_INFO_PHY_STATUS);
-+	if (err)
-+		goto out;
-+
-+	/* halmac_set_hw_value(HALMAC_HW_EN_BB_RF) */
-+	/* Init BB, RF */
-+	ok = rtw_hal_init_phy(adapter);
-+	if (_FALSE == ok)
-+		goto out;
-+
-+	status = api->halmac_init_interface_cfg(halmac);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	/* SKIP: halmac_verify_platform_api */
-+	/* SKIP: halmac_h2c_lb */
-+
-+	/* StateRxIdle */
-+
-+	err_ret = 0;
-+out:
-+	return err_ret;
-+}
-+
-+int rtw_halmac_init_hal(struct dvobj_priv *d)
-+{
-+	return _halmac_init_hal(d, NULL, 0);
-+}
-+
-+/*
-+ * Notices:
-+ *	Make sure following information
-+ *	1. GET_HAL_RFPATH
-+ *	2. GET_HAL_DATA(dvobj_get_primary_adapter(d))->rfe_type
-+ *	3. GET_HAL_DATA(dvobj_get_primary_adapter(d))->PackageType
-+ *	4. dvobj_get_primary_adapter(d)->registrypriv.mp_mode
-+ *	are all ready before calling this function.
-+ */
-+int rtw_halmac_init_hal_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize)
-+{
-+	return _halmac_init_hal(d, fw, fwsize);
-+}
-+
-+/*
-+ * Notices:
-+ *	Make sure following information
-+ *	1. GET_HAL_RFPATH
-+ *	2. GET_HAL_DATA(dvobj_get_primary_adapter(d))->rfe_type
-+ *	3. GET_HAL_DATA(dvobj_get_primary_adapter(d))->PackageType
-+ *	4. dvobj_get_primary_adapter(d)->registrypriv.mp_mode
-+ *	are all ready before calling this function.
-+ */
-+int rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath)
-+{
-+	u8 *fw = NULL;
-+	u32 fwmaxsize = 0, size = 0;
-+	int err = 0;
-+
-+
-+	err = rtw_halmac_get_fw_max_size(d, &fwmaxsize);
-+	if (err) {
-+		RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err);
-+		return -1;
-+	}
-+
-+	fw = rtw_zmalloc(fwmaxsize);
-+	if (!fw)
-+		return -1;
-+
-+	size = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);
-+	if (!size) {
-+		err = -1;
-+		goto exit;
-+	}
-+
-+	err = _halmac_init_hal(d, fw, size);
-+
-+exit:
-+	rtw_mfree(fw, fwmaxsize);
-+	/*fw = NULL;*/
-+
-+	return err;
-+}
-+
-+int rtw_halmac_deinit_hal(struct dvobj_priv *d)
-+{
-+	PADAPTER adapter;
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	adapter = dvobj_get_primary_adapter(d);
-+	halmac = dvobj_to_halmac(d);
-+	if (!halmac)
-+		goto out;
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_deinit_interface_cfg(halmac);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	rtw_hal_power_off(adapter);
-+
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+int rtw_halmac_self_verify(struct dvobj_priv *d)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	int err = -1;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_verify_platform_api(mac);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	status = api->halmac_h2c_lb(mac);
-+	if (status != HALMAC_RET_SUCCESS)
-+		goto out;
-+
-+	err = 0;
-+out:
-+	return err;
-+}
-+
-+static u8 rtw_halmac_txfifo_is_empty(struct dvobj_priv *d)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 chk_num = 10;
-+	u8 rst = _FALSE;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_txfifo_is_empty(mac, chk_num);
-+	if (status == HALMAC_RET_SUCCESS)
-+		rst = _TRUE;
-+
-+	return rst;
-+}
-+
-+/**
-+ * rtw_halmac_txfifo_wait_empty() - Wait TX FIFO to be emtpy
-+ * @d:		struct dvobj_priv*
-+ * @timeout:	time limit of wait, unit is ms
-+ *		0 for no limit
-+ *
-+ * Wait TX FIFO to be emtpy.
-+ *
-+ * Return 0 for TX FIFO is empty, otherwise not empty.
-+ */
-+int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout)
-+{
-+	struct _ADAPTER *a;
-+	u8 empty = _FALSE;
-+	u32 cnt = 0;
-+	systime start_time = 0;
-+	u32 pass_time; /* ms */
-+
-+
-+	a = dvobj_get_primary_adapter(d);
-+	start_time = rtw_get_current_time();
-+
-+	do {
-+		cnt++;
-+		empty = rtw_halmac_txfifo_is_empty(d);
-+		if (empty == _TRUE)
-+			break;
-+
-+		if (timeout) {
-+			pass_time = rtw_get_passing_time_ms(start_time);
-+			if (pass_time > timeout)
-+				break;
-+		}
-+		if (RTW_CANNOT_IO(a)) {
-+			RTW_WARN("%s: Interrupted by I/O forbiden!\n", __FUNCTION__);
-+			break;
-+		}
-+
-+		rtw_msleep_os(2);
-+	} while (1);
-+
-+	if (empty == _FALSE) {
-+#ifdef CONFIG_RTW_DEBUG
-+		u16 dbg_reg[] = {0x210, 0x230, 0x234, 0x238, 0x23C, 0x240,
-+				 0x418, 0x10FC, 0x10F8, 0x11F4, 0x11F8};
-+		u8 i;
-+		u32 val;
-+
-+		if (!RTW_CANNOT_IO(a)) {
-+			for (i = 0; i < ARRAY_SIZE(dbg_reg); i++) {
-+				val = rtw_read32(a, dbg_reg[i]);
-+				RTW_ERR("REG_%X:0x%08x\n", dbg_reg[i], val);
-+			}
-+		}
-+#endif /* CONFIG_RTW_DEBUG */
-+
-+		RTW_ERR("%s: Fail to wait txfifo empty!(cnt=%d)\n",
-+			__FUNCTION__, cnt);
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+static enum halmac_dlfw_mem _fw_mem_drv2halmac(enum fw_mem mem, u8 tx_stop)
-+{
-+	enum halmac_dlfw_mem mem_halmac = HALMAC_DLFW_MEM_UNDEFINE;
-+
-+
-+	switch (mem) {
-+	case FW_EMEM:
-+		if (tx_stop == _FALSE)
-+			mem_halmac = HALMAC_DLFW_MEM_EMEM_RSVD_PG;
-+		else
-+			mem_halmac = HALMAC_DLFW_MEM_EMEM;
-+		break;
-+
-+	case FW_IMEM:
-+	case FW_DMEM:
-+		mem_halmac = HALMAC_DLFW_MEM_UNDEFINE;
-+		break;
-+	}
-+
-+	return mem_halmac;
-+}
-+
-+int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	enum halmac_dlfw_mem dlfw_mem;
-+	u8 tx_stop = _FALSE;
-+	u32 chk_timeout = 2000; /* unit: ms */
-+	int err = 0;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	if ((!fw) || (!fwsize))
-+		return -1;
-+
-+#ifndef RTW_HALMAC_DLFW_MEM_NO_STOP_TX
-+	/* 1. Driver Stop Tx */
-+	/* ToDo */
-+
-+	/* 2. Driver Check Tx FIFO is empty */
-+	err = rtw_halmac_txfifo_wait_empty(d, chk_timeout);
-+	if (err)
-+		tx_stop = _FALSE;
-+	else
-+		tx_stop = _TRUE;
-+#endif /* !RTW_HALMAC_DLFW_MEM_NO_STOP_TX */
-+
-+	/* 3. Download Firmware MEM */
-+	dlfw_mem = _fw_mem_drv2halmac(mem, tx_stop);
-+	if (dlfw_mem == HALMAC_DLFW_MEM_UNDEFINE) {
-+		err = -1;
-+		goto resume_tx;
-+	}
-+	status = api->halmac_free_download_firmware(mac, dlfw_mem, fw, fwsize);
-+	if (status != HALMAC_RET_SUCCESS) {
-+		RTW_ERR("%s: halmac_free_download_firmware fail(err=0x%x)\n",
-+			__FUNCTION__, status);
-+		err = -1;
-+		goto resume_tx;
-+	}
-+
-+resume_tx:
-+#ifndef RTW_HALMAC_DLFW_MEM_NO_STOP_TX
-+	/* 4. Driver resume TX if needed */
-+	/* ToDo */
-+#endif /* !RTW_HALMAC_DLFW_MEM_NO_STOP_TX */
-+
-+	return err;
-+}
-+
-+int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem)
-+{
-+	u8 *fw = NULL;
-+	u32 fwmaxsize = 0, size = 0;
-+	int err = 0;
-+
-+
-+	err = rtw_halmac_get_fw_max_size(d, &fwmaxsize);
-+	if (err) {
-+		RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err);
-+		return -1;
-+	}
-+
-+	fw = rtw_zmalloc(fwmaxsize);
-+	if (!fw)
-+		return -1;
-+
-+	size = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);
-+	if (size)
-+		err = rtw_halmac_dlfw_mem(d, fw, size, mem);
-+	else
-+		err = -1;
-+
-+	rtw_mfree(fw, fwmaxsize);
-+	/*fw = NULL;*/
-+
-+	return err;
-+}
-+
-+/*
-+ * Return:
-+ *	0	Success
-+ *	-22	Invalid arguemnt
-+ */
-+int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize)
-+{
-+	PADAPTER adapter;
-+	enum halmac_ret_status status;
-+	u32 ok;
-+	int err, err_ret = -1;
-+
-+
-+	if (!fw || !fwsize)
-+		return -22;
-+
-+	adapter = dvobj_get_primary_adapter(d);
-+
-+	/* re-download firmware */
-+	if (rtw_is_hw_init_completed(adapter))
-+		return download_fw(d, fw, fwsize, 1);
-+
-+	/* Download firmware before hal init */
-+	/* Power on, download firmware and init mac */
-+	ok = rtw_hal_power_on(adapter);
-+	if (_FAIL == ok)
-+		goto out;
-+
-+	err = download_fw(d, fw, fwsize, 0);
-+	if (err) {
-+		err_ret = err;
-+		goto out;
-+	}
-+
-+	err = init_mac_flow(d);
-+	if (err)
-+		goto out;
-+
-+	err = _send_general_info(d);
-+	if (err)
-+		goto out;
-+
-+	err_ret = 0;
-+
-+out:
-+	return err_ret;
-+}
-+
-+int rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath)
-+{
-+	u8 *fw = NULL;
-+	u32 fwmaxsize = 0, size = 0;
-+	int err = 0;
-+
-+
-+	err = rtw_halmac_get_fw_max_size(d, &fwmaxsize);
-+	if (err) {
-+		RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err);
-+		return -1;
-+	}
-+
-+	fw = rtw_zmalloc(fwmaxsize);
-+	if (!fw)
-+		return -1;
-+
-+	size = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);
-+	if (size)
-+		err = rtw_halmac_dlfw(d, fw, size);
-+	else
-+		err = -1;
-+
-+	rtw_mfree(fw, fwmaxsize);
-+	/*fw = NULL;*/
-+
-+	return err;
-+}
-+
-+/*
-+ * Description:
-+ *	Power on/off BB/RF domain.
-+ *
-+ * Parameters:
-+ *	enable	_TRUE/_FALSE for power on/off
-+ *
-+ * Return:
-+ *	0	Success
-+ *	others	Fail
-+ */
-+int rtw_halmac_phy_power_switch(struct dvobj_priv *d, u8 enable)
-+{
-+	PADAPTER adapter;
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u8 on;
-+
-+
-+	adapter = dvobj_get_primary_adapter(d);
-+	halmac = dvobj_to_halmac(d);
-+	if (!halmac)
-+		return -1;
-+	api = HALMAC_GET_API(halmac);
-+	on = (enable == _TRUE) ? 1 : 0;
-+
-+	status = api->halmac_set_hw_value(halmac, HALMAC_HW_EN_BB_RF, &on);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+static u8 _is_fw_read_cmd_down(PADAPTER adapter, u8 msgbox_num)
-+{
-+	u8 read_down = _FALSE;
-+	int retry_cnts = 100;
-+	u8 valid;
-+
-+	do {
-+		valid = rtw_read8(adapter, REG_HMETFR) & BIT(msgbox_num);
-+		if (0 == valid)
-+			read_down = _TRUE;
-+		else
-+			rtw_msleep_os(1);
-+	} while ((!read_down) && (retry_cnts--));
-+
-+	if (_FALSE == read_down)
-+		RTW_WARN("%s, reg_1cc(%x), msg_box(%d)...\n", __func__, rtw_read8(adapter, REG_HMETFR), msgbox_num);
-+
-+	return read_down;
-+}
-+
-+/**
-+ * rtw_halmac_send_h2c() - Send H2C to firmware
-+ * @d:		struct dvobj_priv*
-+ * @h2c:	H2C data buffer, suppose to be 8 bytes
-+ *
-+ * Send H2C to firmware by message box register(0x1D0~0x1D3 & 0x1F0~0x1F3).
-+ *
-+ * Assume firmware be ready to accept H2C here, please check
-+ * (hal->bFWReady == _TRUE) before call this function or make sure firmware is
-+ * ready.
-+ *
-+ * Return: 0 if process OK, otherwise fail to send this H2C.
-+ */
-+int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c)
-+{
-+	PADAPTER adapter = dvobj_get_primary_adapter(d);
-+	PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
-+	u8 h2c_box_num = 0;
-+	u32 msgbox_addr = 0;
-+	u32 msgbox_ex_addr = 0;
-+	u32 h2c_cmd = 0;
-+	u32 h2c_cmd_ex = 0;
-+	int err = -1;
-+
-+
-+	if (!h2c) {
-+		RTW_WARN("%s: pbuf is NULL\n", __FUNCTION__);
-+		return err;
-+	}
-+
-+	if (rtw_is_surprise_removed(adapter)) {
-+		RTW_WARN("%s: surprise removed\n", __FUNCTION__);
-+		return err;
-+	}
-+
-+	_enter_critical_mutex(&d->h2c_fwcmd_mutex, NULL);
-+
-+	/* pay attention to if race condition happened in H2C cmd setting */
-+	h2c_box_num = hal->LastHMEBoxNum;
-+
-+	if (!_is_fw_read_cmd_down(adapter, h2c_box_num)) {
-+		RTW_WARN(" fw read cmd failed...\n");
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+		hal->srestpriv.self_dect_fw = _TRUE;
-+		hal->srestpriv.self_dect_fw_cnt++;
-+#endif /* DBG_CONFIG_ERROR_DETECT */
-+		goto exit;
-+	}
-+
-+	/* Write Ext command (byte 4~7) */
-+	msgbox_ex_addr = REG_HMEBOX_E0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE);
-+	_rtw_memcpy((u8 *)(&h2c_cmd_ex), h2c + 4, EX_MESSAGE_BOX_SIZE);
-+	h2c_cmd_ex = le32_to_cpu(h2c_cmd_ex);
-+	rtw_write32(adapter, msgbox_ex_addr, h2c_cmd_ex);
-+
-+	/* Write command (byte 0~3) */
-+	msgbox_addr = REG_HMEBOX0 + (h2c_box_num * MESSAGE_BOX_SIZE);
-+	_rtw_memcpy((u8 *)(&h2c_cmd), h2c, 4);
-+	h2c_cmd = le32_to_cpu(h2c_cmd);
-+	rtw_write32(adapter, msgbox_addr, h2c_cmd);
-+
-+	/* update last msg box number */
-+	hal->LastHMEBoxNum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS;
-+	err = 0;
-+
-+#ifdef DBG_H2C_CONTENT
-+	RTW_INFO_DUMP("[H2C] - ", h2c, RTW_HALMAC_H2C_MAX_SIZE);
-+#endif
-+exit:
-+	_exit_critical_mutex(&d->h2c_fwcmd_mutex, NULL);
-+	return err;
-+}
-+
-+/**
-+ * rtw_halmac_c2h_handle() - Handle C2H for HALMAC
-+ * @d:		struct dvobj_priv*
-+ * @c2h:	Full C2H packet, including RX description and payload
-+ * @size:	Size(byte) of c2h
-+ *
-+ * Send C2H packet to HALMAC to process C2H packets, and the expected C2H ID is
-+ * 0xFF. This function won't have any I/O, so caller doesn't have to call it in
-+ * I/O safe place(ex. command thread).
-+ *
-+ * Please sure doesn't call this function in the same thread as someone is
-+ * waiting HALMAC C2H ack, otherwise there is a deadlock happen.
-+ *
-+ * Return: 0 if process OK, otherwise no action for this C2H.
-+ */
-+int rtw_halmac_c2h_handle(struct dvobj_priv *d, u8 *c2h, u32 size)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+#ifdef RTW_HALMAC_FILTER_DRV_C2H
-+	u32 desc_size = 0;
-+	u8 *c2h_data;
-+	u8 sub;
-+#endif /* RTW_HALMAC_FILTER_DRV_C2H */
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+#ifdef RTW_HALMAC_FILTER_DRV_C2H
-+	status = api->halmac_get_hw_value(mac, HALMAC_HW_RX_DESC_SIZE,
-+					  &desc_size);
-+	if (status != HALMAC_RET_SUCCESS) {
-+		RTW_ERR("%s: fail to get rx desc size!\n", __FUNCTION__);
-+		goto skip_filter;
-+	}
-+
-+	c2h_data = c2h + desc_size;
-+	sub = C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_data);
-+	switch (sub) {
-+	case C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG:
-+	case C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG:
-+	case C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG:
-+	case C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG:
-+	case C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG:
-+	case C2H_SUB_CMD_ID_FTMC2H_RPT:
-+	case C2H_SUB_CMD_ID_DRVFTMC2H_RPT:
-+	case C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG:
-+	case C2H_SUB_CMD_ID_CCX_RPT:
-+	case C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT:
-+	case C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT:
-+	case C2H_SUB_CMD_ID_C2H_PKT_SCC_CSA_RPT:
-+	case C2H_SUB_CMD_ID_C2H_PKT_FW_STATUS_NOTIFY:
-+	case C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END:
-+	case C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL:
-+	case C2H_SUB_CMD_ID_FW_FWCTRL_RPT:
-+	case C2H_SUB_CMD_ID_SCAN_CH_NOTIFY:
-+	case C2H_SUB_CMD_ID_FW_TBTT_RPT:
-+	case C2H_SUB_CMD_ID_BCN_OFFLOAD:
-+	case C2H_SUB_CMD_ID_FW_DBG_MSG:
-+		RTW_PRINT("%s: unhandled C2H, id=0xFF subid=0x%x len=%u\n",
-+			  __FUNCTION__, sub, C2H_HDR_GET_LEN(c2h_data));
-+		RTW_PRINT_DUMP("C2H: ", c2h_data, size - desc_size);
-+		return 0;
-+	}
-+
-+skip_filter:
-+#endif /* RTW_HALMAC_FILTER_DRV_C2H */
-+
-+	status = api->halmac_get_c2h_info(mac, c2h, size);
-+	if (HALMAC_RET_SUCCESS != status)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 val;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_get_efuse_available_size(mac, &val);
-+	if (HALMAC_RET_SUCCESS != status)
-+		return -1;
-+
-+	*size = val;
-+	return 0;
-+}
-+
-+int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *d, u32 *size)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 val;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_get_efuse_size(mac, &val);
-+	if (HALMAC_RET_SUCCESS != status)
-+		return -1;
-+
-+	*size = val;
-+	return 0;
-+}
-+
-+int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	enum halmac_feature_id id;
-+	int ret;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+	id = HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE;
-+
-+	ret = init_halmac_event(d, id, map, size);
-+	if (ret)
-+		return -1;
-+
-+	status = api->halmac_dump_efuse_map(mac, HALMAC_EFUSE_R_DRV);
-+	if (HALMAC_RET_SUCCESS != status) {
-+		free_halmac_event(d, id);
-+		return -1;
-+	}
-+
-+	ret = wait_halmac_event(d, id);
-+	if (ret)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+int rtw_halmac_read_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u8 v;
-+	u32 i;
-+	u8 *efuse = NULL;
-+	u32 size = 0;
-+	int err = 0;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	if (api->halmac_read_efuse) {
-+		for (i = 0; i < cnt; i++) {
-+			status = api->halmac_read_efuse(mac, offset + i, &v);
-+			if (HALMAC_RET_SUCCESS != status)
-+				return -1;
-+			data[i] = v;
-+		}
-+	} else {
-+		err = rtw_halmac_get_physical_efuse_size(d, &size);
-+		if (err)
-+			return -1;
-+
-+		efuse = rtw_zmalloc(size);
-+		if (!efuse)
-+			return -1;
-+
-+		err = rtw_halmac_read_physical_efuse_map(d, efuse, size);
-+		if (err)
-+			err = -1;
-+		else
-+			_rtw_memcpy(data, efuse + offset, cnt);
-+
-+		rtw_mfree(efuse, size);
-+	}
-+
-+	return err;
-+}
-+
-+int rtw_halmac_write_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 i;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	if (api->halmac_write_efuse == NULL)
-+		return -1;
-+
-+	for (i = 0; i < cnt; i++) {
-+		status = api->halmac_write_efuse(mac, offset + i, data[i]);
-+		if (HALMAC_RET_SUCCESS != status)
-+			return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *d, u32 *size)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 val;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_get_logical_efuse_size(mac, &val);
-+	if (HALMAC_RET_SUCCESS != status)
-+		return -1;
-+
-+	*size = val;
-+	return 0;
-+}
-+
-+int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	enum halmac_feature_id id;
-+	int ret;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+	id = HALMAC_FEATURE_DUMP_LOGICAL_EFUSE;
-+
-+	ret = init_halmac_event(d, id, map, size);
-+	if (ret)
-+		return -1;
-+
-+	status = api->halmac_dump_logical_efuse_map(mac, HALMAC_EFUSE_R_DRV);
-+	if (HALMAC_RET_SUCCESS != status) {
-+		free_halmac_event(d, id);
-+		return -1;
-+	}
-+
-+	ret = wait_halmac_event(d, id);
-+	if (ret)
-+		return -1;
-+
-+	if (maskmap && masksize) {
-+		struct halmac_pg_efuse_info pginfo;
-+
-+		pginfo.efuse_map = map;
-+		pginfo.efuse_map_size = size;
-+		pginfo.efuse_mask = maskmap;
-+		pginfo.efuse_mask_size = masksize;
-+
-+		status = api->halmac_mask_logical_efuse(mac, &pginfo);
-+		if (status != HALMAC_RET_SUCCESS)
-+			RTW_WARN("%s: mask logical efuse FAIL!\n", __FUNCTION__);
-+	}
-+
-+	return 0;
-+}
-+
-+int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	struct halmac_pg_efuse_info pginfo;
-+	enum halmac_ret_status status;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	pginfo.efuse_map = map;
-+	pginfo.efuse_map_size = size;
-+	pginfo.efuse_mask = maskmap;
-+	pginfo.efuse_mask_size = masksize;
-+
-+	status = api->halmac_pg_efuse_by_map(mac, &pginfo, HALMAC_EFUSE_R_AUTO);
-+	if (HALMAC_RET_SUCCESS != status)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+int rtw_halmac_read_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u8 v;
-+	u32 i;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	for (i = 0; i < cnt; i++) {
-+		status = api->halmac_read_logical_efuse(mac, offset + i, &v);
-+		if (HALMAC_RET_SUCCESS != status)
-+			return -1;
-+		data[i] = v;
-+	}
-+
-+	return 0;
-+}
-+
-+int rtw_halmac_write_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 i;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	for (i = 0; i < cnt; i++) {
-+		status = api->halmac_write_logical_efuse(mac, offset + i, data[i]);
-+		if (HALMAC_RET_SUCCESS != status)
-+			return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 i;
-+	u8 bank = 1;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	for (i = 0; i < cnt; i++) {
-+		status = api->halmac_write_efuse_bt(mac, offset + i, data[i], bank);
-+		if (HALMAC_RET_SUCCESS != status) {
-+			printk("%s: halmac_write_efuse_bt status = %d\n", __FUNCTION__, status);
-+			return -1;
-+		}
-+	}
-+	printk("%s: halmac_write_efuse_bt status = HALMAC_RET_SUCCESS %d\n", __FUNCTION__, status);
-+	return 0;
-+}
-+
-+
-+int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	int bank = 1;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_dump_efuse_map_bt(mac, bank, size, map);
-+	if (HALMAC_RET_SUCCESS != status) {
-+		printk("%s: halmac_dump_efuse_map_bt fail!\n", __FUNCTION__);
-+		return -1;
-+	}
-+
-+	printk("%s: OK!\n", __FUNCTION__);
-+
-+	return 0;
-+}
-+
-+static enum hal_fifo_sel _fifo_sel_drv2halmac(u8 fifo_sel)
-+{
-+	switch (fifo_sel) {
-+	case 0:
-+		return HAL_FIFO_SEL_TX;
-+	case 1:
-+		return HAL_FIFO_SEL_RX;
-+	case 2:
-+		return HAL_FIFO_SEL_RSVD_PAGE;
-+	case 3:
-+		return HAL_FIFO_SEL_REPORT;
-+	case 4:
-+		return HAL_FIFO_SEL_LLT;
-+	case 5:
-+		return HAL_FIFO_SEL_RXBUF_FW;
-+	}
-+
-+	return HAL_FIFO_SEL_RSVD_PAGE;
-+}
-+
-+/*#define CONFIG_HALMAC_FIFO_DUMP*/
-+int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum hal_fifo_sel halmac_fifo_sel;
-+	enum halmac_ret_status status;
-+	u8 *pfifo_map = NULL;
-+	u32 fifo_size = 0;
-+	s8 ret = 0;/* 0:success, -1:error */
-+	u8 mem_created = _FALSE;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	if ((size != 0) && (buffer == NULL))
-+		return -1;
-+
-+	halmac_fifo_sel = _fifo_sel_drv2halmac(fifo_sel);
-+
-+	if ((size) && (buffer)) {
-+		pfifo_map = buffer;
-+		fifo_size = size;
-+	} else {
-+		fifo_size = api->halmac_get_fifo_size(mac, halmac_fifo_sel);
-+
-+		if (fifo_size)
-+			pfifo_map = rtw_zvmalloc(fifo_size);
-+		if (pfifo_map == NULL)
-+			return -1;
-+		mem_created = _TRUE;
-+	}
-+
-+	status = api->halmac_dump_fifo(mac, halmac_fifo_sel, addr, fifo_size, pfifo_map);
-+	if (HALMAC_RET_SUCCESS != status) {
-+		ret = -1;
-+		goto _exit;
-+	}
-+
-+#ifdef CONFIG_HALMAC_FIFO_DUMP
-+	{
-+		static const char * const fifo_sel_str[] = {
-+			"TX", "RX", "RSVD_PAGE", "REPORT", "LLT", "RXBUF_FW"
-+		};
-+
-+		RTW_INFO("%s FIFO DUMP [start_addr:0x%04x , size:%d]\n", fifo_sel_str[halmac_fifo_sel], addr, fifo_size);
-+		RTW_INFO_DUMP("\n", pfifo_map, fifo_size);
-+		RTW_INFO(" ==================================================\n");
-+	}
-+#endif /* CONFIG_HALMAC_FIFO_DUMP */
-+
-+_exit:
-+	if ((mem_created == _TRUE) && pfifo_map)
-+		rtw_vmfree(pfifo_map, fifo_size);
-+
-+	return ret;
-+}
-+
-+/*
-+ * rtw_halmac_rx_agg_switch() - Switch RX aggregation function and setting
-+ * @d		struct dvobj_priv *
-+ * @enable	_FALSE/_TRUE for disable/enable RX aggregation function
-+ *
-+ * This function could help to on/off bus RX aggregation function, and is only
-+ * useful for SDIO and USB interface. Although only "enable" flag is brough in,
-+ * some setting would be taken from other places, and they are from:
-+ * [DMA aggregation]
-+ *	struct hal_com_data.rxagg_dma_size
-+ *	struct hal_com_data.rxagg_dma_timeout
-+ * [USB aggregation] (only use for USB interface)
-+ *	struct hal_com_data.rxagg_usb_size
-+ *	struct hal_com_data.rxagg_usb_timeout
-+ * If above values of size and timeout are both 0 means driver would not
-+ * control the threshold setting and leave it to HALMAC handle.
-+ *
-+ * From HALMAC V1_04_04, driver force the size threshold be hard limit, and the
-+ * rx size can not exceed the setting.
-+ *
-+ * Return 0 for success, otherwise fail.
-+ */
-+int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable)
-+{
-+	struct _ADAPTER *adapter;
-+	struct hal_com_data *hal;
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	struct halmac_rxagg_cfg rxaggcfg;
-+	enum halmac_ret_status status;
-+
-+
-+	adapter = dvobj_get_primary_adapter(d);
-+	hal = GET_HAL_DATA(adapter);
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+	_rtw_memset((void *)&rxaggcfg, 0, sizeof(rxaggcfg));
-+	rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;
-+	/*
-+	 * Always enable size limit to avoid rx size exceed
-+	 * driver defined size.
-+	 */
-+	rxaggcfg.threshold.size_limit_en = 1;
-+
-+#ifdef RTW_RX_AGGREGATION
-+	if (_TRUE == enable) {
-+#ifdef CONFIG_SDIO_HCI
-+		rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA;
-+		rxaggcfg.threshold.drv_define = 0;
-+		if (hal->rxagg_dma_size || hal->rxagg_dma_timeout) {
-+			rxaggcfg.threshold.drv_define = 1;
-+			rxaggcfg.threshold.timeout = hal->rxagg_dma_timeout;
-+			rxaggcfg.threshold.size = hal->rxagg_dma_size;
-+			RTW_INFO("%s: RX aggregation threshold: "
-+				 "timeout=%u size=%u\n",
-+				 __FUNCTION__,
-+				 hal->rxagg_dma_timeout,
-+				 hal->rxagg_dma_size);
-+		}
-+#elif defined(CONFIG_USB_HCI)
-+		switch (hal->rxagg_mode) {
-+		case RX_AGG_DISABLE:
-+			rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;
-+			break;
-+
-+		case RX_AGG_DMA:
-+			rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA;
-+			if (hal->rxagg_dma_size || hal->rxagg_dma_timeout) {
-+				rxaggcfg.threshold.drv_define = 1;
-+				rxaggcfg.threshold.timeout = hal->rxagg_dma_timeout;
-+				rxaggcfg.threshold.size = hal->rxagg_dma_size;
-+			}
-+			break;
-+
-+		case RX_AGG_USB:
-+		case RX_AGG_MIX:
-+			rxaggcfg.mode = HALMAC_RX_AGG_MODE_USB;
-+			if (hal->rxagg_usb_size || hal->rxagg_usb_timeout) {
-+				rxaggcfg.threshold.drv_define = 1;
-+				rxaggcfg.threshold.timeout = hal->rxagg_usb_timeout;
-+				rxaggcfg.threshold.size = hal->rxagg_usb_size;
-+			}
-+			break;
-+		}
-+#endif /* CONFIG_USB_HCI */
-+	}
-+#endif /* RTW_RX_AGGREGATION */
-+
-+	status = api->halmac_cfg_rx_aggregation(halmac, &rxaggcfg);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size)
-+{
-+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-+	struct halmac_adapter *halmac = dvobj_to_halmac(dvobj);
-+	struct halmac_api *api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_dl_drv_rsvd_page(halmac, pg_offset, pbuf, size);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+/*
-+ * Description
-+ *	Fill following spec info from HALMAC API:
-+ *	sec_cam_ent_num
-+ *
-+ * Return
-+ *	0	Success
-+ *	others	Fail
-+ */
-+int rtw_halmac_fill_hal_spec(struct dvobj_priv *dvobj, struct hal_spec_t *spec)
-+{
-+	enum halmac_ret_status status;
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	u8 cam = 0;	/* Security Cam Entry Number */
-+
-+
-+	halmac = dvobj_to_halmac(dvobj);
-+	api = HALMAC_GET_API(halmac);
-+
-+	/* Prepare data from HALMAC */
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_CAM_ENTRY_NUM, &cam);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	/* Fill data to hal_spec_t */
-+	spec->sec_cam_ent_num = cam;
-+
-+	return 0;
-+}
-+
-+int rtw_halmac_p2pps(struct dvobj_priv *dvobj, struct hal_p2p_ps_para *pp2p_ps_para)
-+{
-+	enum halmac_ret_status status = HALMAC_RET_SUCCESS;
-+	struct halmac_adapter *halmac = dvobj_to_halmac(dvobj);
-+	struct halmac_api *api = HALMAC_GET_API(halmac);
-+	struct halmac_p2pps halmac_p2p_ps;
-+
-+	(&halmac_p2p_ps)->offload_en = pp2p_ps_para->offload_en;
-+	(&halmac_p2p_ps)->role = pp2p_ps_para->role;
-+	(&halmac_p2p_ps)->ctwindow_en = pp2p_ps_para->ctwindow_en;
-+	(&halmac_p2p_ps)->noa_en = pp2p_ps_para->noa_en;
-+	(&halmac_p2p_ps)->noa_sel = pp2p_ps_para->noa_sel;
-+	(&halmac_p2p_ps)->all_sta_sleep = pp2p_ps_para->all_sta_sleep;
-+	(&halmac_p2p_ps)->discovery = pp2p_ps_para->discovery;
-+	(&halmac_p2p_ps)->disable_close_rf = pp2p_ps_para->disable_close_rf;
-+	(&halmac_p2p_ps)->p2p_port_id = _hw_port_drv2halmac(pp2p_ps_para->p2p_port_id);
-+	(&halmac_p2p_ps)->p2p_group = pp2p_ps_para->p2p_group;
-+	(&halmac_p2p_ps)->p2p_macid = pp2p_ps_para->p2p_macid;
-+	(&halmac_p2p_ps)->ctwindow_length = pp2p_ps_para->ctwindow_length;
-+	(&halmac_p2p_ps)->noa_duration_para = pp2p_ps_para->noa_duration_para;
-+	(&halmac_p2p_ps)->noa_interval_para = pp2p_ps_para->noa_interval_para;
-+	(&halmac_p2p_ps)->noa_start_time_para = pp2p_ps_para->noa_start_time_para;
-+	(&halmac_p2p_ps)->noa_count_para = pp2p_ps_para->noa_count_para;
-+
-+	status = api->halmac_p2pps(halmac, (&halmac_p2p_ps));
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	return 0;
-+
-+}
-+
-+/**
-+ * rtw_halmac_iqk() - Run IQ Calibration
-+ * @d:		struct dvobj_priv*
-+ * @clear:	IQK parameters
-+ * @segment:	IQK parameters
-+ *
-+ * Process IQ Calibration(IQK).
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	enum halmac_feature_id id;
-+	struct halmac_iqk_para para;
-+	int ret;
-+	u8 retry = 3;
-+	u8 delay = 1; /* ms */
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+	id = HALMAC_FEATURE_IQK;
-+
-+	ret = init_halmac_event(d, id, NULL, 0);
-+	if (ret)
-+		return -1;
-+
-+	para.clear = clear;
-+	para.segment_iqk = segment;
-+
-+	do {
-+		status = api->halmac_start_iqk(mac, &para);
-+		if (status != HALMAC_RET_BUSY_STATE)
-+			break;
-+		RTW_WARN("%s: Fail to start IQK, status is BUSY! retry=%d\n", __FUNCTION__, retry);
-+		if (!retry)
-+			break;
-+		retry--;
-+		rtw_msleep_os(delay);
-+	} while (1);
-+	if (status != HALMAC_RET_SUCCESS) {
-+		free_halmac_event(d, id);
-+		return -1;
-+	}
-+
-+	ret = wait_halmac_event(d, id);
-+	if (ret)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_dpk() - Run DP Calibration
-+ * @d:		struct dvobj_priv*
-+ * @buf:	buffer for store return value
-+ * @bufsz:	size of buffer
-+ *
-+ * Process DP Calibration(DPK).
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_dpk(struct dvobj_priv *d, u8 *buf, u32 bufsz)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	enum halmac_feature_id id;
-+	int ret;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+	id = HALMAC_FEATURE_DPK;
-+
-+	ret = init_halmac_event(d, id, buf, bufsz);
-+	if (ret)
-+		return -1;
-+
-+	status = api->halmac_start_dpk(mac);
-+	if (status != HALMAC_RET_SUCCESS) {
-+		free_halmac_event(d, id);
-+		RTW_ERR("%s: Fail to start DPK (0x%x)!\n",
-+			__FUNCTION__, status);
-+		return -1;
-+	}
-+
-+	ret = wait_halmac_event(d, id);
-+	if (ret)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+static inline u32 _phy_parameter_val_drv2halmac(u32 val, u8 msk_en, u32 msk)
-+{
-+	if (!msk_en)
-+		return val;
-+
-+	return (val << bitshift(msk));
-+}
-+
-+static int _phy_parameter_drv2halmac(struct rtw_phy_parameter *para, struct halmac_phy_parameter_info *info)
-+{
-+	if (!para || !info)
-+		return -1;
-+
-+	_rtw_memset(info, 0, sizeof(*info));
-+
-+	switch (para->cmd) {
-+	case 0:
-+		/* MAC register */
-+		switch (para->data.mac.size) {
-+		case 1:
-+			info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W8;
-+			break;
-+		case 2:
-+			info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W16;
-+			break;
-+		default:
-+			info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W32;
-+			break;
-+		}
-+		info->content.MAC_REG_W.value = _phy_parameter_val_drv2halmac(
-+							para->data.mac.value,
-+							para->data.mac.msk_en,
-+							para->data.mac.msk);
-+		info->content.MAC_REG_W.msk = para->data.mac.msk;
-+		info->content.MAC_REG_W.offset = para->data.mac.offset;
-+		info->content.MAC_REG_W.msk_en = para->data.mac.msk_en;
-+		break;
-+
-+	case 1:
-+		/* BB register */
-+		switch (para->data.bb.size) {
-+		case 1:
-+			info->cmd_id = HALMAC_PARAMETER_CMD_BB_W8;
-+			break;
-+		case 2:
-+			info->cmd_id = HALMAC_PARAMETER_CMD_BB_W16;
-+			break;
-+		default:
-+			info->cmd_id = HALMAC_PARAMETER_CMD_BB_W32;
-+			break;
-+		}
-+		info->content.BB_REG_W.value = _phy_parameter_val_drv2halmac(
-+							para->data.bb.value,
-+							para->data.bb.msk_en,
-+							para->data.bb.msk);
-+		info->content.BB_REG_W.msk = para->data.bb.msk;
-+		info->content.BB_REG_W.offset = para->data.bb.offset;
-+		info->content.BB_REG_W.msk_en = para->data.bb.msk_en;
-+		break;
-+
-+	case 2:
-+		/* RF register */
-+		info->cmd_id = HALMAC_PARAMETER_CMD_RF_W;
-+		info->content.RF_REG_W.value = _phy_parameter_val_drv2halmac(
-+							para->data.rf.value,
-+							para->data.rf.msk_en,
-+							para->data.rf.msk);
-+		info->content.RF_REG_W.msk = para->data.rf.msk;
-+		info->content.RF_REG_W.offset = para->data.rf.offset;
-+		info->content.RF_REG_W.msk_en = para->data.rf.msk_en;
-+		info->content.RF_REG_W.rf_path = para->data.rf.path;
-+		break;
-+
-+	case 3:
-+		/* Delay register */
-+		if (para->data.delay.unit == 0)
-+			info->cmd_id = HALMAC_PARAMETER_CMD_DELAY_US;
-+		else
-+			info->cmd_id = HALMAC_PARAMETER_CMD_DELAY_MS;
-+		info->content.DELAY_TIME.delay_time = para->data.delay.value;
-+		break;
-+
-+	case 0xFF:
-+		/* Latest(End) command */
-+		info->cmd_id = HALMAC_PARAMETER_CMD_END;
-+		break;
-+
-+	default:
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_cfg_phy_para() - Register(Phy parameter) configuration
-+ * @d:		struct dvobj_priv*
-+ * @para:	phy parameter
-+ *
-+ * Configure registers by firmware using H2C/C2H mechanism.
-+ * The latest command should be para->cmd==0xFF(End command) to finish all
-+ * processes.
-+ *
-+ * Return: 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	enum halmac_feature_id id;
-+	struct halmac_phy_parameter_info info;
-+	u8 full_fifo;
-+	int err, ret;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+	id = HALMAC_FEATURE_CFG_PARA;
-+	full_fifo = 1; /* ToDo: How to deciede? */
-+	ret = 0;
-+
-+	err = _phy_parameter_drv2halmac(para, &info);
-+	if (err)
-+		return -1;
-+
-+	err = init_halmac_event(d, id, NULL, 0);
-+	if (err)
-+		return -1;
-+
-+	status = api->halmac_cfg_parameter(mac, &info, full_fifo);
-+	if (info.cmd_id == HALMAC_PARAMETER_CMD_END) {
-+		if (status == HALMAC_RET_SUCCESS) {
-+			err = wait_halmac_event(d, id);
-+			if (err)
-+				ret = -1;
-+		} else {
-+			free_halmac_event(d, id);
-+			ret = -1;
-+			RTW_ERR("%s: Fail to send END of cfg parameter, status is 0x%x!\n", __FUNCTION__, status);
-+		}
-+	} else {
-+		if (status == HALMAC_RET_PARA_SENDING) {
-+			err = wait_halmac_event(d, id);
-+			if (err)
-+				ret = -1;
-+		} else {
-+			free_halmac_event(d, id);
-+			if (status != HALMAC_RET_SUCCESS) {
-+				ret = -1;
-+				RTW_ERR("%s: Fail to cfg parameter, status is 0x%x!\n", __FUNCTION__, status);
-+			}
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+static enum halmac_wlled_mode _led_mode_drv2halmac(u8 drv_mode)
-+{
-+	enum halmac_wlled_mode halmac_mode;
-+
-+
-+	switch (drv_mode) {
-+	case 1:
-+		halmac_mode = HALMAC_WLLED_MODE_TX;
-+		break;
-+	case 2:
-+		halmac_mode = HALMAC_WLLED_MODE_RX;
-+		break;
-+	case 3:
-+		halmac_mode = HALMAC_WLLED_MODE_SW_CTRL;
-+		break;
-+	case 0:
-+	default:
-+		halmac_mode = HALMAC_WLLED_MODE_TRX;
-+		break;
-+	}
-+
-+	return halmac_mode;
-+}
-+
-+/**
-+ * rtw_halmac_led_cfg() - Configure Hardware LED Mode
-+ * @d:		struct dvobj_priv*
-+ * @enable:	enable or disable LED function
-+ *		0: disable
-+ *		1: enable
-+ * @mode:	WLan LED mode (valid when enable==1)
-+ *		0: Blink when TX(transmit packet) and RX(receive packet)
-+ *		1: Blink when TX only
-+ *		2: Blink when RX only
-+ *		3: Software control
-+ *
-+ * Configure hardware WLan LED mode.
-+ * If want to change LED mode after enabled, need to disable LED first and
-+ * enable again to set new mode.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_wlled_mode led_mode;
-+	enum halmac_ret_status status;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	if (enable) {
-+		status = api->halmac_pinmux_set_func(halmac,
-+						     HALMAC_GPIO_FUNC_WL_LED);
-+		if (status != HALMAC_RET_SUCCESS) {
-+			RTW_ERR("%s: pinmux set fail!(0x%x)\n",
-+				__FUNCTION__, status);
-+			return -1;
-+		}
-+
-+		led_mode = _led_mode_drv2halmac(mode);
-+		status = api->halmac_pinmux_wl_led_mode(halmac, led_mode);
-+		if (status != HALMAC_RET_SUCCESS) {
-+			RTW_ERR("%s: mode set fail!(0x%x)\n",
-+				__FUNCTION__, status);
-+			return -1;
-+		}
-+	} else {
-+		/* Change LED to software control and turn off */
-+		api->halmac_pinmux_wl_led_mode(halmac,
-+					       HALMAC_WLLED_MODE_SW_CTRL);
-+		api->halmac_pinmux_wl_led_sw_ctrl(halmac, 0);
-+
-+		status = api->halmac_pinmux_free_func(halmac,
-+						      HALMAC_GPIO_FUNC_WL_LED);
-+		if (status != HALMAC_RET_SUCCESS) {
-+			RTW_ERR("%s: pinmux free fail!(0x%x)\n",
-+				__FUNCTION__, status);
-+			return -1;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_led_switch() - Turn Hardware LED on/off
-+ * @d:		struct dvobj_priv*
-+ * @on:		LED light or not
-+ *		0: Off
-+ *		1: On(Light)
-+ *
-+ * Turn Hardware WLan LED On/Off.
-+ * Before use this function, user should call rtw_halmac_led_ctrl() to switch
-+ * mode to "software control(3)" first, otherwise control would fail.
-+ * The interval between on and off must be longer than 1 ms, or the LED would
-+ * keep light or dark only.
-+ * Ex. Turn off LED at first, turn on after 0.5ms and turn off again after
-+ * 0.5ms. The LED during this flow will only keep dark, and miss the turn on
-+ * operation between two turn off operations.
-+ */
-+void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	api->halmac_pinmux_wl_led_sw_ctrl(halmac, on);
-+}
-+
-+static int _gpio_cfg(struct dvobj_priv *d, enum halmac_gpio_func gpio, u8 enable)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	if (enable) {
-+		status = api->halmac_pinmux_set_func(halmac, gpio);
-+		if (status != HALMAC_RET_SUCCESS) {
-+			RTW_ERR("%s: pinmux set GPIO(%d) fail!(0x%x)\n",
-+				__FUNCTION__, gpio, status);
-+			return -1;
-+		}
-+	} else {
-+ 		status = api->halmac_pinmux_free_func(halmac, gpio);
-+		if (status != HALMAC_RET_SUCCESS) {
-+			RTW_ERR("%s: pinmux free GPIO(%d) fail!(0x%x)\n",
-+				__FUNCTION__, gpio, status);
-+			return -1;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_bt_wake_cfg() - Configure BT wake host function
-+ * @d:		struct dvobj_priv*
-+ * @enable:	enable or disable BT wake host function
-+ *		0: disable
-+ *		1: enable
-+ *
-+ * Configure pinmux to allow BT to control BT wake host pin.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_bt_wake_cfg(struct dvobj_priv *d, u8 enable)
-+{
-+	return _gpio_cfg(d, HALMAC_GPIO_FUNC_BT_HOST_WAKE1, enable);
-+}
-+
-+static enum halmac_gpio_func _gpio_to_func_for_rfe_ctrl(u8 gpio)
-+{
-+	enum halmac_gpio_func f = HALMAC_GPIO_FUNC_UNDEFINE;
-+
-+
-+#ifdef CONFIG_RTL8822C
-+	switch (gpio) {
-+	case 1:
-+		f = HALMAC_GPIO_FUNC_ANTSWB;
-+		break;
-+	case 2:
-+		f = HALMAC_GPIO_FUNC_S1_TRSW;
-+		break;
-+	case 3:
-+		f = HALMAC_GPIO_FUNC_S0_TRSW;
-+		break;
-+	case 6:
-+		f = HALMAC_GPIO_FUNC_S0_PAPE;
-+		break;
-+	case 7:
-+		f = HALMAC_GPIO_FUNC_S0_TRSWB;
-+		break;
-+	case 13:
-+		f = HALMAC_GPIO_FUNC_ANTSW;
-+		break;
-+	}
-+#endif /* CONFIG_RTL8822C */
-+
-+	return f;
-+}
-+
-+/**
-+ * rtw_halmac_rfe_ctrl_cfg() - Configure RFE control GPIO
-+ * @d:		struct dvobj_priv*
-+ * @gpio:	gpio number
-+ *
-+ * Configure pinmux to enable RFE control GPIO.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_rfe_ctrl_cfg(struct dvobj_priv *d, u8 gpio)
-+{
-+	enum halmac_gpio_func f;
-+
-+
-+	f = _gpio_to_func_for_rfe_ctrl(gpio);
-+	if (f == HALMAC_GPIO_FUNC_UNDEFINE)
-+		return -1;
-+	return _gpio_cfg(d, f, 1);
-+}
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+/**
-+ * _halmac_scanoffload() - Switch channel by firmware during scanning
-+ * @d:		struct dvobj_priv*
-+ * @enable:	1: enable, 0: disable
-+ * @nlo:	1: nlo mode (no c2h event), 0: normal mode
-+ * @ssid:	ssid of probe request
-+ * @ssid_len:	ssid length
-+ *
-+ * Switch Channel and Send Porbe Request Offloaded by FW
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+static int _halmac_scanoffload(struct dvobj_priv *d, u32 enable, u8 nlo,
-+			       u8 *ssid, u8 ssid_len)
-+{
-+	struct _ADAPTER *adapter;
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	struct halmac_ch_info ch_info;
-+	struct halmac_ch_switch_option cs_option;
-+	struct mlme_ext_priv *pmlmeext;
-+	enum halmac_feature_id id_update, id_ch_sw;
-+	struct halmac_indicator *indicator, *tbl;
-+
-+	int err = 0;
-+	u8 probereq[64];
-+	u32 len = 0;
-+	int i = 0;
-+	struct pno_ssid pnossid;
-+	struct rf_ctl_t *rfctl = NULL;
-+	struct _RT_CHANNEL_INFO *ch_set;
-+
-+
-+	tbl = d->hmpriv.indicator;
-+	adapter = dvobj_get_primary_adapter(d);
-+	mac = dvobj_to_halmac(d);
-+	if (!mac)
-+		return -1;
-+	api = HALMAC_GET_API(mac);
-+	id_update = HALMAC_FEATURE_UPDATE_PACKET;
-+	id_ch_sw = HALMAC_FEATURE_CHANNEL_SWITCH;
-+	pmlmeext = &(adapter->mlmeextpriv);
-+	rfctl = adapter_to_rfctl(adapter);
-+	ch_set = rfctl->channel_set;
-+
-+	RTW_INFO("%s: %s scanoffload, mode: %s\n",
-+		 __FUNCTION__, enable?"Enable":"Disable",
-+		 nlo?"PNO/NLO":"Normal");
-+
-+	if (enable) {
-+		_rtw_memset(probereq, 0, sizeof(probereq));
-+
-+		_rtw_memset(&pnossid, 0, sizeof(pnossid));
-+		if (ssid) {
-+			if (ssid_len > sizeof(pnossid.SSID)) {
-+				RTW_ERR("%s: SSID length(%d) is too long(>%d)!!\n",
-+					__FUNCTION__, ssid_len, sizeof(pnossid.SSID));
-+				return -1;
-+			}
-+
-+			pnossid.SSID_len = ssid_len;
-+			_rtw_memcpy(pnossid.SSID, ssid, ssid_len);
-+		}
-+
-+		rtw_hal_construct_ProbeReq(adapter, probereq, &len, &pnossid);
-+
-+		if (!nlo) {
-+			err = init_halmac_event(d, id_update, NULL, 0);
-+			if (err)
-+				return -1;
-+		}
-+
-+		status = api->halmac_update_packet(mac, HALMAC_PACKET_PROBE_REQ,
-+						   probereq, len);
-+		if (status != HALMAC_RET_SUCCESS) {
-+			if (!nlo)
-+				free_halmac_event(d, id_update);
-+			RTW_ERR("%s: halmac_update_packet FAIL(%d)!!\n",
-+				__FUNCTION__, status);
-+			return -1;
-+		}
-+
-+		if (!nlo) {
-+			err = wait_halmac_event(d, id_update);
-+			if (err)
-+				RTW_ERR("%s: wait update packet FAIL(%d)!!\n",
-+					__FUNCTION__, err);
-+		}
-+
-+		api->halmac_clear_ch_info(mac);
-+
-+		for (i = 0; i < rfctl->max_chan_nums && ch_set[i].ChannelNum != 0; i++) {
-+			_rtw_memset(&ch_info, 0, sizeof(ch_info));
-+			ch_info.extra_info = 0;
-+			ch_info.channel = ch_set[i].ChannelNum;
-+			ch_info.bw = HALMAC_BW_20;
-+			ch_info.pri_ch_idx = HALMAC_CH_IDX_1;
-+			ch_info.action_id = HALMAC_CS_ACTIVE_SCAN;
-+			ch_info.timeout = 1;
-+			status = api->halmac_add_ch_info(mac, &ch_info);
-+			if (status != HALMAC_RET_SUCCESS) {
-+				RTW_ERR("%s: add_ch_info FAIL(%d)!!\n",
-+					__FUNCTION__, status);
-+				return -1;
-+			}
-+		}
-+
-+		/* set channel switch option */
-+		_rtw_memset(&cs_option, 0, sizeof(cs_option));
-+		cs_option.dest_bw = HALMAC_BW_20;
-+		cs_option.periodic_option = HALMAC_CS_PERIODIC_2_PHASE;
-+		cs_option.dest_pri_ch_idx = HALMAC_CH_IDX_UNDEFINE;
-+		cs_option.tsf_low = 0;
-+		cs_option.switch_en = 1;
-+		cs_option.dest_ch_en = 1;
-+		cs_option.absolute_time_en = 0;
-+		cs_option.dest_ch = 1;
-+
-+		cs_option.normal_period = 5;
-+		cs_option.normal_period_sel = 0;
-+		cs_option.normal_cycle = 10;
-+
-+		cs_option.phase_2_period = 1;
-+		cs_option.phase_2_period_sel = 1;
-+
-+		/* nlo is for wow fw,  1: no c2h response */
-+		cs_option.nlo_en = nlo;
-+
-+		if (!nlo) {
-+			err = init_halmac_event(d, id_ch_sw, NULL, 0);
-+			if (err)
-+				return -1;
-+		}
-+
-+		status = api->halmac_ctrl_ch_switch(mac, &cs_option);
-+		if (status != HALMAC_RET_SUCCESS) {
-+			if (!nlo)
-+				free_halmac_event(d, id_ch_sw);
-+			RTW_ERR("%s: halmac_ctrl_ch_switch FAIL(%d)!!\n",
-+				__FUNCTION__, status);
-+			return -1;
-+		}
-+
-+		if (!nlo) {
-+			err = wait_halmac_event(d, id_ch_sw);
-+			if (err)
-+				RTW_ERR("%s: wait ctrl_ch_switch FAIL(%d)!!\n",
-+					__FUNCTION__, err);
-+		}
-+	} else {
-+		api->halmac_clear_ch_info(mac);
-+
-+		_rtw_memset(&cs_option, 0, sizeof(cs_option));
-+		cs_option.switch_en = 0;
-+
-+		if (!nlo) {
-+			err = init_halmac_event(d, id_ch_sw, NULL, 0);
-+			if (err)
-+				return -1;
-+		}
-+
-+		status = api->halmac_ctrl_ch_switch(mac, &cs_option);
-+		if (status != HALMAC_RET_SUCCESS) {
-+			if (!nlo)
-+				free_halmac_event(d, id_ch_sw);
-+			RTW_ERR("%s: halmac_ctrl_ch_switch FAIL(%d)!!\n",
-+				__FUNCTION__, status);
-+			return -1;
-+		}
-+
-+		if (!nlo) {
-+			err = wait_halmac_event(d, id_ch_sw);
-+			if (err)
-+				RTW_ERR("%s: wait ctrl_ch_switch FAIL(%d)!!\n",
-+					__FUNCTION__, err);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_pno_scanoffload() - Control firmware scan AP function for PNO
-+ * @d:		struct dvobj_priv*
-+ * @enable:	1: enable, 0: disable
-+ *
-+ * Switch firmware scan AP function for PNO(prefer network offload) or
-+ * NLO(network list offload).
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_pno_scanoffload(struct dvobj_priv *d, u32 enable)
-+{
-+	return _halmac_scanoffload(d, enable, 1, NULL, 0);
-+}
-+#endif /* CONFIG_PNO_SUPPORT */
-+
-+#ifdef CONFIG_SDIO_HCI
-+
-+/**
-+ * rtw_halmac_preinit_sdio_io_indirect() - Enable indirect I/O or not
-+ * @d:		struct dvobj_priv*
-+ * @enable:	true: enable, false: disable
-+ *
-+ * Enable register access using direct I/O or indirect. This function should be
-+ * called before rtw_halmac_init_adapter(), and the life cycle is the same as
-+ * driver until removing driver.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_preinit_sdio_io_indirect(struct dvobj_priv *d, bool enable)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmacpriv *priv;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	if (halmac) {
-+		RTW_WARN("%s: illegal operation! "
-+			 "preinit function only could be called before init!\n",
-+			 __FUNCTION__);
-+		return -1;
-+	}
-+
-+	priv = &d->hmpriv;
-+	priv->sdio_io_indir = (enable ? 1 : 2);
-+
-+	return 0;
-+}
-+
-+/*
-+ * Description:
-+ *	Update queue allocated page number to driver
-+ *
-+ * Parameter:
-+ *	d	pointer to struct dvobj_priv of driver
-+ *
-+ * Return:
-+ *	0	Success, "page" is valid.
-+ *	others	Fail, "page" is invalid.
-+ */
-+int rtw_halmac_query_tx_page_num(struct dvobj_priv *d)
-+{
-+	PADAPTER adapter;
-+	struct halmacpriv *hmpriv;
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	struct halmac_rqpn_map rqpn;
-+	enum halmac_dma_mapping dmaqueue;
-+	struct halmac_txff_allocation fifosize;
-+	enum halmac_ret_status status;
-+	u8 i;
-+
-+
-+	adapter = dvobj_get_primary_adapter(d);
-+	hmpriv = &d->hmpriv;
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+	_rtw_memset((void *)&rqpn, 0, sizeof(rqpn));
-+	_rtw_memset((void *)&fifosize, 0, sizeof(fifosize));
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_RQPN_MAPPING, &rqpn);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_TXFF_ALLOCATION, &fifosize);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	for (i = 0; i < HW_QUEUE_ENTRY; i++) {
-+		hmpriv->txpage[i] = 0;
-+
-+		/* Driver index mapping to HALMAC DMA queue */
-+		dmaqueue = HALMAC_DMA_MAPPING_UNDEFINE;
-+		switch (i) {
-+		case VO_QUEUE_INX:
-+			dmaqueue = rqpn.dma_map_vo;
-+			break;
-+		case VI_QUEUE_INX:
-+			dmaqueue = rqpn.dma_map_vi;
-+			break;
-+		case BE_QUEUE_INX:
-+			dmaqueue = rqpn.dma_map_be;
-+			break;
-+		case BK_QUEUE_INX:
-+			dmaqueue = rqpn.dma_map_bk;
-+			break;
-+		case MGT_QUEUE_INX:
-+			dmaqueue = rqpn.dma_map_mg;
-+			break;
-+		case HIGH_QUEUE_INX:
-+			dmaqueue = rqpn.dma_map_hi;
-+			break;
-+		case BCN_QUEUE_INX:
-+		case TXCMD_QUEUE_INX:
-+			/* Unlimited */
-+			hmpriv->txpage[i] = 0xFFFF;
-+			continue;
-+		}
-+
-+		switch (dmaqueue) {
-+		case HALMAC_DMA_MAPPING_EXTRA:
-+			hmpriv->txpage[i] = fifosize.extra_queue_pg_num;
-+			break;
-+		case HALMAC_DMA_MAPPING_LOW:
-+			hmpriv->txpage[i] = fifosize.low_queue_pg_num;
-+			break;
-+		case HALMAC_DMA_MAPPING_NORMAL:
-+			hmpriv->txpage[i] = fifosize.normal_queue_pg_num;
-+			break;
-+		case HALMAC_DMA_MAPPING_HIGH:
-+			hmpriv->txpage[i] = fifosize.high_queue_pg_num;
-+			break;
-+		case HALMAC_DMA_MAPPING_UNDEFINE:
-+			break;
-+		}
-+		hmpriv->txpage[i] += fifosize.pub_queue_pg_num;
-+	}
-+
-+	return 0;
-+}
-+
-+/*
-+ * Description:
-+ *	Get specific queue allocated page number
-+ *
-+ * Parameter:
-+ *	d	pointer to struct dvobj_priv of driver
-+ *	queue	target queue to query, VO/VI/BE/BK/.../TXCMD_QUEUE_INX
-+ *	page	return allocated page number
-+ *
-+ * Return:
-+ *	0	Success, "page" is valid.
-+ *	others	Fail, "page" is invalid.
-+ */
-+int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *d, u8 queue, u32 *page)
-+{
-+	*page = 0;
-+	if (queue < HW_QUEUE_ENTRY)
-+		*page = d->hmpriv.txpage[queue];
-+
-+	return 0;
-+}
-+
-+/*
-+ * Return:
-+ *	address for SDIO command
-+ */
-+u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *d, u8 *desc, u32 size)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u32 addr;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_get_sdio_tx_addr(mac, desc, size, &addr);
-+	if (HALMAC_RET_SUCCESS != status)
-+		return 0;
-+
-+	return addr;
-+}
-+
-+int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *d, u8 *buf, u32 size)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_tx_allowed_sdio(mac, buf, size);
-+	if (HALMAC_RET_SUCCESS != status)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *d, u8 *seq)
-+{
-+	u8 id;
-+
-+#define RTW_SDIO_ADDR_RX_RX0FF_PRFIX	0x0E000
-+#define RTW_SDIO_ADDR_RX_RX0FF_GEN(a)	(RTW_SDIO_ADDR_RX_RX0FF_PRFIX|(a&0x3))
-+
-+	id = *seq;
-+	(*seq)++;
-+	return RTW_SDIO_ADDR_RX_RX0FF_GEN(id);
-+}
-+
-+int rtw_halmac_sdio_set_tx_format(struct dvobj_priv *d, enum halmac_sdio_tx_format format)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_set_hw_value(mac, HALMAC_HW_SDIO_TX_FORMAT, &format);
-+	if (HALMAC_RET_SUCCESS != status)
-+		return -1;
-+
-+	return 0;
-+}
-+#endif /* CONFIG_SDIO_HCI */
-+
-+#ifdef CONFIG_USB_HCI
-+u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *d, u8 *buf, u32 size)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u8 bulkout_id;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_get_usb_bulkout_id(mac, buf, size, &bulkout_id);
-+	if (HALMAC_RET_SUCCESS != status)
-+		return 0;
-+
-+	return bulkout_id;
-+}
-+
-+/**
-+ * rtw_halmac_usb_get_txagg_desc_num() - MAX descriptor number in one bulk for TX
-+ * @d:		struct dvobj_priv*
-+ * @size:	TX FIFO size, unit is byte.
-+ *
-+ * Get MAX descriptor number in one bulk out from HALMAC.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num)
-+{
-+	struct halmac_adapter *halmac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	u8 val = 0;
-+
-+
-+	halmac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(halmac);
-+
-+	status = api->halmac_get_hw_value(halmac, HALMAC_HW_USB_TXAGG_DESC_NUM, &val);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	*num = val;
-+
-+	return 0;
-+}
-+
-+static inline enum halmac_usb_mode _usb_mode_drv2halmac(enum RTW_USB_SPEED usb_mode)
-+{
-+	enum halmac_usb_mode halmac_usb_mode = HALMAC_USB_MODE_U2;
-+
-+	switch (usb_mode) {
-+	case RTW_USB_SPEED_2:
-+		halmac_usb_mode = HALMAC_USB_MODE_U2;
-+		break;
-+	case RTW_USB_SPEED_3:
-+		halmac_usb_mode = HALMAC_USB_MODE_U3;
-+		break;
-+	default:
-+		halmac_usb_mode = HALMAC_USB_MODE_U2;
-+		break;
-+	}
-+
-+	return halmac_usb_mode;
-+}
-+
-+u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode)
-+{
-+	PADAPTER adapter;
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	enum halmac_usb_mode halmac_usb_mode;
-+
-+	adapter = dvobj_get_primary_adapter(d);
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+	halmac_usb_mode = _usb_mode_drv2halmac(usb_mode);
-+	status = api->halmac_set_hw_value(mac, HALMAC_HW_USB_MODE, (void *)&halmac_usb_mode);
-+
-+	if (HALMAC_RET_SUCCESS != status)
-+		return _FAIL;
-+
-+	return _SUCCESS;
-+}
-+#endif /* CONFIG_USB_HCI */
-+
-+#ifdef CONFIG_BEAMFORMING
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para,
-+		u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	struct halmac_mu_bfer_init_para param;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	_rtw_memset(&param, 0, sizeof(param));
-+	param.paid = paid;
-+	param.csi_para = csi_para;
-+	param.my_aid = my_aid;
-+	param.csi_length_sel = sel;
-+	_rtw_memcpy(param.bfer_address.addr, addr, 6);
-+
-+	status = api->halmac_mu_bfer_entry_init(mac, &param);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_mu_bfer_entry_del(mac);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+
-+int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d,
-+		enum halmac_snd_role role, enum halmac_data_rate rate)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_cfg_sounding(mac, role, rate);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+int rtw_halmac_bf_del_sounding(struct dvobj_priv *d,
-+		enum halmac_snd_role role)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_del_sounding(mac, role);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+/**
-+ * rtw_halmac_bf_cfg_csi_rate() - Config data rate for CSI report frame by RSSI
-+ * @d:		struct dvobj_priv*
-+ * @rssi:	RSSI vlaue, unit is percentage (0~100).
-+ * @current_rate:	Current CSI frame rate
-+ *			Valid value example
-+ *			0	CCK 1M
-+ *			3	CCK 11M
-+ *			4	OFDM 6M
-+ *			and so on
-+ * @fixrate_en:	Enable to fix CSI frame in VHT rate, otherwise legacy OFDM rate.
-+ *		The value "0" for disable, otheriwse enable.
-+ * @new_rate:	Return new data rate, and value range is the same as
-+ *		current_rate
-+ * @bmp_ofdm54: Return to suggest enabling OFDM 54M for CSI report frame or not,
-+ *		The valid values and meanings are:
-+ *		0x00	disable
-+ *		0x01	enable
-+ *		0xFF	Keep current setting
-+ *
-+ * According RSSI to config data rate for CSI report frame of Beamforming.
-+ *
-+ * Return 0 for OK, otherwise fail.
-+ */
-+int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi,
-+			       u8 current_rate, u8 fixrate_en, u8 *new_rate,
-+			       u8 *bmp_ofdm54)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	status = api->halmac_cfg_csi_rate(mac,
-+			rssi, current_rate, fixrate_en, new_rate,
-+			bmp_ofdm54);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role,
-+		u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en,
-+		u32 *given_gid_tab, u32 *given_user_pos)
-+{
-+	struct halmac_adapter *mac;
-+	struct halmac_api *api;
-+	enum halmac_ret_status status;
-+	struct halmac_cfg_mumimo_para param;
-+
-+
-+	mac = dvobj_to_halmac(d);
-+	api = HALMAC_GET_API(mac);
-+
-+	_rtw_memset(&param, 0, sizeof(param));
-+
-+	param.role = role;
-+	param.grouping_bitmap = grouping_bitmap;
-+	param.mu_tx_en = mu_tx_en;
-+
-+	if (sounding_sts)
-+		_rtw_memcpy(param.sounding_sts, sounding_sts, 6);
-+
-+	if (given_gid_tab)
-+		_rtw_memcpy(param.given_gid_tab, given_gid_tab, 8);
-+
-+	if (given_user_pos)
-+		_rtw_memcpy(param.given_user_pos, given_user_pos, 16);
-+
-+	status = api->halmac_cfg_mumimo(mac, &param);
-+	if (status != HALMAC_RET_SUCCESS)
-+		return -1;
-+
-+	return 0;
-+}
-+
-+#endif /* RTW_BEAMFORMING_VERSION_2 */
-+#endif /* CONFIG_BEAMFORMING */
-diff --git a/drivers/staging/rtl8723cs/hal/hal_halmac.h b/drivers/staging/rtl8723cs/hal/hal_halmac.h
-new file mode 100644
-index 000000000000..73882267aa9b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_halmac.h
-@@ -0,0 +1,252 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _HAL_HALMAC_H_
-+#define _HAL_HALMAC_H_
-+
-+#include <drv_types.h>		/* adapter_to_dvobj(), struct intf_hdl and etc. */
-+#include <hal_data.h>		/* struct hal_spec_t */
-+#include "halmac/halmac_api.h"	/* struct halmac_adapter* and etc. */
-+
-+/* HALMAC Definition for Driver */
-+#define RTW_HALMAC_H2C_MAX_SIZE		8
-+#define RTW_HALMAC_BA_SSN_RPT_SIZE	4
-+
-+#define dvobj_set_halmac(d, mac)	((d)->halmac = (mac))
-+#define dvobj_to_halmac(d)		((struct halmac_adapter *)((d)->halmac))
-+#define adapter_to_halmac(p)		dvobj_to_halmac(adapter_to_dvobj(p))
-+
-+/* for H2C cmd */
-+#define MAX_H2C_BOX_NUMS 4
-+#define MESSAGE_BOX_SIZE 4
-+#define EX_MESSAGE_BOX_SIZE 4
-+
-+typedef enum _RTW_HALMAC_MODE {
-+	RTW_HALMAC_MODE_NORMAL,
-+	RTW_HALMAC_MODE_WIFI_TEST,
-+} RTW_HALMAC_MODE;
-+
-+union rtw_phy_para_data {
-+	struct _mac {
-+		u32	value;	/* value to be set in bit mask(msk) */
-+		u32	msk;	/* bit mask */
-+		u16	offset; /* address */
-+		u8	msk_en;	/* 0/1 for msk invalid/valid */
-+		u8	size;	/* Unit is bytes, and value should be 1/2/4 */
-+	} mac;
-+	struct _bb {
-+		u32	value;
-+		u32	msk;
-+		u16	offset;
-+		u8	msk_en;
-+		u8	size;
-+	} bb;
-+	struct _rf {
-+		u32	value;
-+		u32	msk;
-+		u8	offset;
-+		u8	msk_en;
-+		/*
-+		 * 0: path A
-+		 * 1: path B
-+		 * 2: path C
-+		 * 3: path D
-+		 */
-+		u8	path;
-+	} rf;
-+	struct _delay {
-+		/*
-+		 * 0: microsecond (us)
-+		 * 1: millisecond (ms)
-+		 */
-+		u8	unit;
-+		u16	value;
-+	} delay;
-+};
-+
-+struct rtw_phy_parameter {
-+	/*
-+	 * 0: MAC register
-+	 * 1: BB register
-+	 * 2: RF register
-+	 * 3: Delay
-+	 * 0xFF: Latest(End) command
-+	 */
-+	u8 cmd;
-+	union rtw_phy_para_data data;
-+};
-+
-+struct rtw_halmac_bcn_ctrl {
-+	u8 rx_bssid_fit:1;	/* 0:HW handle beacon, 1:ignore */
-+	u8 txbcn_rpt:1;		/* Enable TXBCN report in ad hoc and AP mode */
-+	u8 tsf_update:1;	/* Update TSF when beacon or probe response */
-+	u8 enable_bcn:1;	/* Enable beacon related functions */
-+	u8 rxbcn_rpt:1;		/* Enable RXBCNOK report */
-+	u8 p2p_ctwin:1;		/* Enable P2P CTN WINDOWS function */
-+	u8 p2p_bcn_area:1;	/* Enable P2P BCN area on function */
-+};
-+
-+extern struct halmac_platform_api rtw_halmac_platform_api;
-+
-+/* HALMAC API for Driver(HAL) */
-+u8 rtw_halmac_read8(struct intf_hdl *, u32 addr);
-+u16 rtw_halmac_read16(struct intf_hdl *, u32 addr);
-+u32 rtw_halmac_read32(struct intf_hdl *, u32 addr);
-+void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr);
-+u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr);
-+u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr);
-+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
-+int rtw_halmac_write8(struct intf_hdl *, u32 addr, u8 value);
-+int rtw_halmac_write16(struct intf_hdl *, u32 addr, u16 value);
-+int rtw_halmac_write32(struct intf_hdl *, u32 addr, u32 value);
-+
-+/* Software Information */
-+void rtw_halmac_get_version(char *str, u32 len);
-+
-+/* Software setting before Initialization */
-+int rtw_halmac_preinit_sdio_io_indirect(struct dvobj_priv *d, bool enable);
-+
-+/* Software Initialization */
-+int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api);
-+int rtw_halmac_deinit_adapter(struct dvobj_priv *);
-+
-+/* Get operations */
-+int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue);
-+int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size);
-+int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size);
-+int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy);
-+int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size);
-+int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size);
-+int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size);
-+int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *, u8 *sz);
-+int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size);
-+int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size);
-+int rtw_halmac_get_tx_dma_ch_map(struct dvobj_priv *d, u8 *dma_ch_map, u8 map_size);
-+int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size);
-+int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size);
-+int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num);
-+int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
-+int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type);
-+int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl);
-+/*int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason);*/
-+
-+/* Set operations */
-+int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info);
-+int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size);
-+int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
-+int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
-+int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
-+int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type);
-+int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport);
-+int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport, u32 space);
-+int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl);
-+int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid);
-+int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw);
-+int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop);
-+int rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable);
-+
-+/* Functions */
-+int rtw_halmac_poweron(struct dvobj_priv *);
-+int rtw_halmac_poweroff(struct dvobj_priv *);
-+int rtw_halmac_init_hal(struct dvobj_priv *);
-+int rtw_halmac_init_hal_fw(struct dvobj_priv *, u8 *fw, u32 fwsize);
-+int rtw_halmac_init_hal_fw_file(struct dvobj_priv *, u8 *fwpath);
-+int rtw_halmac_deinit_hal(struct dvobj_priv *);
-+int rtw_halmac_self_verify(struct dvobj_priv *);
-+int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout);
-+int rtw_halmac_dlfw(struct dvobj_priv *, u8 *fw, u32 fwsize);
-+int rtw_halmac_dlfw_from_file(struct dvobj_priv *, u8 *fwpath);
-+int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem);
-+int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem);
-+int rtw_halmac_phy_power_switch(struct dvobj_priv *, u8 enable);
-+int rtw_halmac_send_h2c(struct dvobj_priv *, u8 *h2c);
-+int rtw_halmac_c2h_handle(struct dvobj_priv *, u8 *c2h, u32 size);
-+
-+/* eFuse */
-+int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size);
-+int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *, u32 *size);
-+int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size);
-+int rtw_halmac_read_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
-+int rtw_halmac_write_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
-+int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *, u32 *size);
-+int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize);
-+int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize);
-+int rtw_halmac_read_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
-+int rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
-+
-+int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
-+int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size);
-+
-+int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer);
-+int rtw_halmac_rx_agg_switch(struct dvobj_priv *, u8 enable);
-+
-+/* Specific function APIs*/
-+int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size);
-+int rtw_halmac_fill_hal_spec(struct dvobj_priv *, struct hal_spec_t *);
-+int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para);
-+int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment);
-+int rtw_halmac_dpk(struct dvobj_priv *d, u8 *buf, u32 bufsz);
-+int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para);
-+int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode);
-+void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on);
-+int rtw_halmac_bt_wake_cfg(struct dvobj_priv *d, u8 enable);
-+int rtw_halmac_rfe_ctrl_cfg(struct dvobj_priv *d, u8 gpio);
-+#ifdef CONFIG_PNO_SUPPORT
-+int rtw_halmac_pno_scanoffload(struct dvobj_priv *d, u32 enable);
-+#endif
-+
-+#ifdef CONFIG_SDIO_HCI
-+int rtw_halmac_query_tx_page_num(struct dvobj_priv *);
-+int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *, u8 queue, u32 *page);
-+u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *, u8 *desc, u32 size);
-+int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *, u8 *buf, u32 size);
-+u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *, u8 *seq);
-+int rtw_halmac_sdio_set_tx_format(struct dvobj_priv *d, enum halmac_sdio_tx_format format);
-+#endif /* CONFIG_SDIO_HCI */
-+
-+#ifdef CONFIG_USB_HCI
-+u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *, u8 *buf, u32 size);
-+int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num);
-+u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode);
-+#endif /* CONFIG_USB_HCI */
-+
-+#ifdef CONFIG_SUPPORT_TRX_SHARED
-+void dump_trx_share_mode(void *sel, _adapter *adapter);
-+#endif
-+
-+#ifdef CONFIG_BEAMFORMING
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para,
-+		u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr);
-+int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d);
-+
-+int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, enum halmac_snd_role role,
-+		enum halmac_data_rate rate);
-+int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, enum halmac_snd_role role);
-+
-+int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi, u8 current_rate,
-+		u8 fixrate_en, u8 *new_rate, u8 *bmp_ofdm54);
-+
-+int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role,
-+		u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en,
-+		u32 *given_gid_tab, u32 *given_user_pos);
-+#define rtw_halmac_bf_cfg_mu_bfee(d, gid_tab, user_pos) \
-+	rtw_halmac_bf_cfg_mu_mimo(d, HAL_BFEE, NULL, 0, 0, gid_tab, user_pos)
-+
-+#endif /* RTW_BEAMFORMING_VERSION_2 */
-+#endif /* CONFIG_BEAMFORMING */
-+
-+#endif /* _HAL_HALMAC_H_ */
-diff --git a/drivers/staging/rtl8723cs/hal/hal_hci/hal_sdio.c b/drivers/staging/rtl8723cs/hal/hal_hci/hal_sdio.c
-new file mode 100644
-index 000000000000..3e8be28d0436
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_hci/hal_sdio.c
-@@ -0,0 +1,885 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _HAL_SDIO_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#ifndef RTW_HALMAC
-+const char *_sdio_tx_queue_str[] = {
-+	"H",
-+	"M",
-+	"L",
-+};
-+
-+static void dump_mac_page0(PADAPTER padapter)
-+{
-+	char str_out[128];
-+	char str_val[8];
-+	char *p = NULL;
-+	int index = 0, i = 0;
-+	u8 val8 = 0, len = 0;
-+
-+	RTW_ERR("Dump MAC Page0 register:\n");
-+	for (index = 0 ; index < 0x100 ; index += 16) {
-+		p = &str_out[0];
-+		len = snprintf(str_val, sizeof(str_val),
-+			       "0x%02x: ", index);
-+		strncpy(str_out, str_val, len);
-+		p += len;
-+
-+		for (i = 0 ; i < 16 ; i++) {
-+			len = snprintf(str_val, sizeof(str_val), "%02x ",
-+				       rtw_read8(padapter, index + i));
-+			strncpy(p, str_val, len);
-+			p += len;
-+		}
-+		RTW_INFO("%s\n", str_out);
-+		_rtw_memset(&str_out, '\0', sizeof(str_out));
-+	}
-+}
-+
-+/*
-+ * Description:
-+ *	Call this function to make sure power on successfully
-+ *
-+ * Return:
-+ *	_SUCCESS	enable success
-+ *	_FAIL	enable fail
-+ */
-+bool sdio_power_on_check(PADAPTER padapter) {
-+	u32 val_offset0, val_offset1, val_offset2, val_offset3;
-+	u32 val_mix = 0;
-+	u32 res = 0;
-+	bool ret = _FAIL;
-+	int index = 0;
-+
-+	val_offset0 = rtw_read8(padapter, REG_CR);
-+	val_offset1 = rtw_read8(padapter, REG_CR + 1);
-+	val_offset2 = rtw_read8(padapter, REG_CR + 2);
-+	val_offset3 = rtw_read8(padapter, REG_CR + 3);
-+
-+	if (val_offset0 == 0xEA || val_offset1 == 0xEA ||
-+	    val_offset2 == 0xEA || val_offset3 == 0xEA) {
-+		RTW_INFO("%s: power on fail, do Power on again\n", __func__);
-+		return ret;
-+	}
-+
-+	val_mix = val_offset3 << 24 | val_mix;
-+	val_mix = val_offset2 << 16 | val_mix;
-+	val_mix = val_offset1 << 8 | val_mix;
-+	val_mix = val_offset0 | val_mix;
-+
-+	res = rtw_read32(padapter, REG_CR);
-+
-+	RTW_INFO("%s: val_mix:0x%08x, res:0x%08x\n", __func__, val_mix, res);
-+
-+	while (index < 100) {
-+		if (res == val_mix) {
-+			RTW_INFO("%s: 0x100 the result of cmd52 and cmd53 is the same.\n", __func__);
-+			ret = _SUCCESS;
-+			break;
-+		} else {
-+			RTW_INFO("%s: 0x100 cmd52 and cmd53 is not the same(index:%d).\n", __func__, index);
-+			res = rtw_read32(padapter, REG_CR);
-+			index++;
-+			ret = _FAIL;
-+		}
-+	}
-+
-+	if (ret) {
-+		index = 0;
-+		while (index < 100) {
-+			rtw_write32(padapter, 0x1B8, 0x12345678);
-+			res = rtw_read32(padapter, 0x1B8);
-+			if (res == 0x12345678) {
-+				RTW_INFO("%s: 0x1B8 test Pass.\n", __func__);
-+				ret = _SUCCESS;
-+				break;
-+			} else {
-+				index++;
-+				RTW_INFO("%s: 0x1B8 test Fail(index: %d).\n", __func__, index);
-+				ret = _FAIL;
-+			}
-+		}
-+	} else
-+		RTW_INFO("%s: fail at cmd52, cmd53.\n", __func__);
-+
-+	if (ret == _FAIL)
-+		dump_mac_page0(padapter);
-+
-+	return ret;
-+}
-+
-+u8 rtw_hal_sdio_max_txoqt_free_space(_adapter *padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	if (pHalData->SdioTxOQTMaxFreeSpace < 8)
-+		pHalData->SdioTxOQTMaxFreeSpace = 8;
-+
-+	return pHalData->SdioTxOQTMaxFreeSpace;
-+}
-+
-+u8 rtw_hal_sdio_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	if ((pHalData->SdioTxFIFOFreePage[PageIdx] + pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]) >= (RequiredPageNum))
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+void rtw_hal_sdio_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	u8	DedicatedPgNum = 0;
-+	u8	RequiredPublicFreePgNum = 0;
-+	/* _irqL irql; */
-+
-+	/* _enter_critical_bh(&pHalData->SdioTxFIFOFreePageLock, &irql); */
-+
-+	DedicatedPgNum = pHalData->SdioTxFIFOFreePage[PageIdx];
-+	if (RequiredPageNum <= DedicatedPgNum)
-+		pHalData->SdioTxFIFOFreePage[PageIdx] -= RequiredPageNum;
-+	else {
-+		pHalData->SdioTxFIFOFreePage[PageIdx] = 0;
-+		RequiredPublicFreePgNum = RequiredPageNum - DedicatedPgNum;
-+		pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] -= RequiredPublicFreePgNum;
-+	}
-+
-+	/* _exit_critical_bh(&pHalData->SdioTxFIFOFreePageLock, &irql); */
-+}
-+
-+void rtw_hal_set_sdio_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ, u8 div_num)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	u32	page_size;
-+	u32	lenHQ, lenNQ, lenLQ;
-+
-+	rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
-+
-+	lenHQ = ((numHQ + numPubQ) / div_num) * page_size;
-+	lenNQ = ((numNQ + numPubQ) / div_num) * page_size;
-+	lenLQ = ((numLQ + numPubQ) / div_num) * page_size;
-+
-+	pHalData->sdio_tx_max_len[HI_QUEUE_IDX] = (lenHQ > MAX_XMITBUF_SZ) ? MAX_XMITBUF_SZ : lenHQ;
-+	pHalData->sdio_tx_max_len[MID_QUEUE_IDX] = (lenNQ > MAX_XMITBUF_SZ) ? MAX_XMITBUF_SZ : lenNQ;
-+	pHalData->sdio_tx_max_len[LOW_QUEUE_IDX] = (lenLQ > MAX_XMITBUF_SZ) ? MAX_XMITBUF_SZ : lenLQ;
-+	#ifdef DBG_TX_FREE_PAGE
-+	RTW_INFO("rtw_hal_set_sdio_tx_max_length div_num :%u  numHQ=%u numNQ=%u numLQ=%u numPubQ=%u\n",div_num ,numHQ,numNQ,numLQ,numPubQ);
-+	RTW_INFO("pHalData->sdio_tx_max_len[HI_QUEUE_IDX] :%u\n",pHalData->sdio_tx_max_len[HI_QUEUE_IDX] );
-+	RTW_INFO("pHalData->sdio_tx_max_len[MID_QUEUE_IDX] :%u\n",pHalData->sdio_tx_max_len[MID_QUEUE_IDX] );
-+	RTW_INFO("rtw_hal_set_sdio_tx_max_length pHalData->sdio_tx_max_len[LOW_QUEUE_IDX] :%u\n",pHalData->sdio_tx_max_len[LOW_QUEUE_IDX] );
-+	#endif
-+}
-+
-+u32 rtw_hal_get_sdio_tx_max_length(PADAPTER padapter, u8 queue_idx)
-+{
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	u32	deviceId, max_len;
-+
-+
-+	deviceId = ffaddr2deviceId(pdvobjpriv, queue_idx);
-+	switch (deviceId) {
-+	case WLAN_TX_HIQ_DEVICE_ID:
-+		max_len = pHalData->sdio_tx_max_len[HI_QUEUE_IDX];
-+		break;
-+
-+	case WLAN_TX_MIQ_DEVICE_ID:
-+		max_len = pHalData->sdio_tx_max_len[MID_QUEUE_IDX];
-+		break;
-+
-+	case WLAN_TX_LOQ_DEVICE_ID:
-+		max_len = pHalData->sdio_tx_max_len[LOW_QUEUE_IDX];
-+		break;
-+
-+	default:
-+		max_len = pHalData->sdio_tx_max_len[MID_QUEUE_IDX];
-+		break;
-+	}
-+
-+	return max_len;
-+}
-+
-+#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) ||defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8192F)|| defined(CONFIG_RTL8723D)
-+void rtw_hal_sdio_avail_page_threshold_init(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+	hal_data->sdio_avail_int_en_q = 0xFF;
-+	rtw_write32(adapter, REG_TQPNT1, 0xFFFFFFFF);
-+	rtw_write32(adapter, REG_TQPNT2, 0xFFFFFFFF);
-+	#ifdef CONFIG_RTL8192F
-+	rtw_write32(adapter, REG_TQPNT3_V1_8192F, 0xFFFFFFFF);
-+	#endif
-+}
-+
-+void rtw_hal_sdio_avail_page_threshold_en(_adapter *adapter, u8 qidx, u8 page)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	if (hal_data->sdio_avail_int_en_q != qidx) {
-+		u32 page_size;
-+		u32 tx_max_len;
-+		u32 threshold_reg[] = {REG_TQPNT1, REG_TQPNT1 + 2, REG_TQPNT2, REG_TQPNT2 + 2}; /* H, M, L, E */
-+		u8 dw_shift[] = {0, 16, 0, 16}; /* H, M, L, E */
-+		u32 threshold = 0;
-+
-+		/* use same low-high threshold as page num from tx_max_len */
-+		if(dvobj->tx_aval_int_thr_mode == 0) /*default setting by requirement*/
-+			threshold = page;
-+		else if (dvobj->tx_aval_int_thr_mode == 1 && dvobj->tx_aval_int_thr_value)
-+			threshold = dvobj->tx_aval_int_thr_value;
-+		else {
-+			rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
-+			tx_max_len = hal_data->sdio_tx_max_len[qidx];
-+			threshold = PageNum(tx_max_len, page_size);
-+		}
-+		threshold |= (threshold) << 8;
-+
-+		if (hal_data->sdio_avail_int_en_q == 0xFF)
-+			rtw_write16(adapter, threshold_reg[qidx], threshold);
-+		else if (hal_data->sdio_avail_int_en_q >> 1 == qidx >> 1) {/* same dword */
-+			rtw_write16(adapter, threshold_reg[hal_data->sdio_avail_int_en_q], 0);
-+			rtw_write32(adapter, threshold_reg[qidx & 0xFE]
-+				, (0xFFFF << dw_shift[hal_data->sdio_avail_int_en_q]) | (threshold << dw_shift[qidx]));
-+		} else {
-+			rtw_write16(adapter, threshold_reg[hal_data->sdio_avail_int_en_q], 0);
-+			rtw_write16(adapter, threshold_reg[hal_data->sdio_avail_int_en_q], 0xFFFF);
-+			rtw_write16(adapter, threshold_reg[qidx], threshold);
-+		}
-+
-+		hal_data->sdio_avail_int_en_q = qidx;
-+
-+		#ifdef DBG_TX_FREE_PAGE
-+		RTW_INFO("DWQP enable avail page threshold %s:%u-%u\n", sdio_tx_queue_str(qidx)
-+			, threshold & 0xFF, threshold >> 8);
-+		#endif
-+	}
-+}
-+#endif
-+#endif /* CONFIG_SDIO_TX_ENABLE_AVAL_INT */
-+
-+#ifdef CONFIG_FW_C2H_REG
-+void sd_c2h_hisr_hdl(_adapter *adapter)
-+{
-+	u8 c2h_evt[C2H_REG_LEN] = {0};
-+	u8 id, seq, plen;
-+	u8 *payload;
-+
-+	if (rtw_hal_c2h_evt_read(adapter, c2h_evt) != _SUCCESS)
-+		goto exit;
-+
-+	if (rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload) != _SUCCESS)
-+		goto exit;
-+		
-+	if (rtw_hal_c2h_id_handle_directly(adapter, id, seq, plen, payload)) {
-+		/* Handle directly */
-+		rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
-+		goto exit;
-+	}
-+
-+	if (rtw_c2h_reg_wk_cmd(adapter, c2h_evt) != _SUCCESS)
-+		RTW_ERR("%s rtw_c2h_reg_wk_cmd fail\n", __func__);
-+
-+exit:
-+	return;
-+}
-+#endif
-+
-+#ifdef CONFIG_SDIO_CHK_HCI_RESUME
-+
-+#ifndef SDIO_HCI_RESUME_PWR_RDY_TIMEOUT_MS
-+	#define SDIO_HCI_RESUME_PWR_RDY_TIMEOUT_MS 200
-+#endif
-+#ifndef DBG_SDIO_CHK_HCI_RESUME
-+	#define DBG_SDIO_CHK_HCI_RESUME 0
-+#endif
-+
-+bool sdio_chk_hci_resume(struct intf_hdl *pintfhdl)
-+{
-+	_adapter *adapter = pintfhdl->padapter;
-+	u8 hci_sus_state;
-+	u8 sus_ctl, sus_ctl_ori = 0xEA;
-+	u8 do_leave = 0;
-+	systime start = 0, end = 0;
-+	u32 poll_cnt = 0;
-+	u8 timeout = 0;
-+	u8 sr = 0;
-+	s32 err = 0;
-+
-+	rtw_hal_get_hwreg(adapter, HW_VAR_HCI_SUS_STATE, &hci_sus_state);
-+	if (hci_sus_state == HCI_SUS_LEAVE || hci_sus_state == HCI_SUS_ERR)
-+		goto no_hdl;
-+
-+	err = sd_cmd52_read(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_HSUS_CTRL), 1, &sus_ctl);
-+	if (err)
-+		goto exit;
-+	sus_ctl_ori = sus_ctl;
-+
-+	if ((sus_ctl & HCI_RESUME_PWR_RDY) && !(sus_ctl & HCI_SUS_CTRL))
-+		goto exit;
-+
-+	if (sus_ctl & HCI_SUS_CTRL) {
-+		sus_ctl &= ~(HCI_SUS_CTRL);
-+		err = sd_cmd52_write(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_HSUS_CTRL), 1, &sus_ctl);
-+		if (err)
-+			goto exit;
-+	}
-+
-+	do_leave = 1;
-+
-+	/* polling for HCI_RESUME_PWR_RDY && !HCI_SUS_CTRL */
-+	start = rtw_get_current_time();
-+	while (1) {
-+		if (rtw_is_surprise_removed(adapter)) {
-+			sr = 1;
-+			break;
-+		}
-+
-+		err = sd_cmd52_read(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_HSUS_CTRL), 1, &sus_ctl);
-+		poll_cnt++;
-+
-+		if (!err && (sus_ctl & HCI_RESUME_PWR_RDY) && !(sus_ctl & HCI_SUS_CTRL))
-+			break;
-+
-+		if (rtw_get_passing_time_ms(start) > SDIO_HCI_RESUME_PWR_RDY_TIMEOUT_MS) {
-+			timeout = 1;
-+			break;
-+		}
-+	}
-+	end = rtw_get_current_time();
-+
-+exit:
-+
-+	if (DBG_SDIO_CHK_HCI_RESUME) {
-+		RTW_INFO(FUNC_ADPT_FMT" hci_sus_state:%u, sus_ctl:0x%02x(0x%02x), do_leave:%u, to:%u, err:%u\n"
-+			, FUNC_ADPT_ARG(adapter), hci_sus_state, sus_ctl, sus_ctl_ori, do_leave, timeout, err);
-+		if (start != 0 || end != 0) {
-+			RTW_INFO(FUNC_ADPT_FMT" polling %d ms, cnt:%u\n"
-+				, FUNC_ADPT_ARG(adapter), rtw_get_time_interval_ms(start, end), poll_cnt);
-+		}
-+	}
-+
-+	if (timeout) {
-+		RTW_ERR(FUNC_ADPT_FMT" timeout(err:%d) sus_ctl:0x%02x\n"
-+			, FUNC_ADPT_ARG(adapter), err, sus_ctl);
-+	} else if (err) {
-+		RTW_ERR(FUNC_ADPT_FMT" err:%d\n"
-+			, FUNC_ADPT_ARG(adapter), err);
-+	}
-+
-+no_hdl:
-+	return do_leave ? _TRUE : _FALSE;
-+}
-+
-+void sdio_chk_hci_suspend(struct intf_hdl *pintfhdl)
-+{
-+#define SDIO_CHK_HCI_SUSPEND_POLLING 0
-+
-+	_adapter *adapter = pintfhdl->padapter;
-+	u8 hci_sus_state;
-+	u8 sus_ctl, sus_ctl_ori = 0xEA;
-+	systime start = 0, end = 0;
-+	u32 poll_cnt = 0;
-+	u8 timeout = 0;
-+	u8 sr = 0;
-+	s32 err = 0;
-+	u8 device_id;
-+	u16 offset;
-+
-+	rtw_hal_get_hwreg(adapter, HW_VAR_HCI_SUS_STATE, &hci_sus_state);
-+	if (hci_sus_state == HCI_SUS_LEAVE || hci_sus_state == HCI_SUS_LEAVING || hci_sus_state == HCI_SUS_ERR)
-+		goto no_hdl;
-+
-+	err = sd_cmd52_read(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_HSUS_CTRL), 1, &sus_ctl);
-+	if (err)
-+		goto exit;
-+	sus_ctl_ori = sus_ctl;
-+
-+	if (!(sus_ctl & HCI_RESUME_PWR_RDY))
-+		goto exit;
-+
-+	sus_ctl |= HCI_SUS_CTRL;
-+	err = sd_cmd52_write(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_HSUS_CTRL), 1, &sus_ctl);
-+	if (err)
-+		goto exit;
-+
-+#if SDIO_CHK_HCI_SUSPEND_POLLING
-+	/* polling for HCI_RESUME_PWR_RDY cleared */
-+	start = rtw_get_current_time();
-+	while (1) {
-+		if (rtw_is_surprise_removed(adapter)) {
-+			sr = 1;
-+			break;
-+		}
-+
-+		err = sd_cmd52_read(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_HSUS_CTRL), 1, &sus_ctl);
-+		poll_cnt++;
-+
-+		if (!err && !(sus_ctl & HCI_RESUME_PWR_RDY))
-+			break;
-+
-+		if (rtw_get_passing_time_ms(start) > SDIO_HCI_RESUME_PWR_RDY_TIMEOUT_MS) {
-+			timeout = 1;
-+			break;
-+		}
-+	}
-+	end = rtw_get_current_time();
-+#endif /* SDIO_CHK_HCI_SUSPEND_POLLING */
-+
-+exit:
-+
-+	if (DBG_SDIO_CHK_HCI_RESUME) {
-+		RTW_INFO(FUNC_ADPT_FMT" hci_sus_state:%u, sus_ctl:0x%02x(0x%02x), to:%u, err:%u\n"
-+			, FUNC_ADPT_ARG(adapter), hci_sus_state, sus_ctl, sus_ctl_ori, timeout, err);
-+		if (start != 0 || end != 0) {
-+			RTW_INFO(FUNC_ADPT_FMT" polling %d ms, cnt:%u\n"
-+				, FUNC_ADPT_ARG(adapter), rtw_get_time_interval_ms(start, end), poll_cnt);
-+		}
-+	}
-+
-+#if SDIO_CHK_HCI_SUSPEND_POLLING
-+	if (timeout) {
-+		RTW_ERR(FUNC_ADPT_FMT" timeout(err:%d) sus_ctl:0x%02x\n"
-+			, FUNC_ADPT_ARG(adapter), err, sus_ctl);
-+	} else
-+#endif
-+		if (err) {
-+			RTW_ERR(FUNC_ADPT_FMT" err:%d\n"
-+				, FUNC_ADPT_ARG(adapter), err);
-+		}
-+
-+no_hdl:
-+	return;
-+}
-+#endif /* CONFIG_SDIO_CHK_HCI_RESUME */
-+
-+
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+
-+/* program indirect access register in sdio local to read/write page0 registers */
-+#ifndef INDIRECT_ACCESS_TIMEOUT_MS
-+	#define INDIRECT_ACCESS_TIMEOUT_MS 200
-+#endif
-+#ifndef DBG_SDIO_INDIRECT_ACCESS
-+	#define DBG_SDIO_INDIRECT_ACCESS 0
-+#endif
-+
-+s32 sdio_iread(PADAPTER padapter, u32 addr, u8 size, u8 *v)
-+{
-+	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
-+	_mutex *mutex = &adapter_to_dvobj(padapter)->sd_indirect_access_mutex;
-+
-+	u8 val[4] = {0};
-+	u8 cmd[4] = {0}; /* mapping to indirect access register, little endien */
-+	systime start = 0, end = 0;
-+	u8 timeout = 0;
-+	u8 sr = 0;
-+	s32 err = 0;
-+
-+	if (size == 1)
-+		SET_INDIRECT_REG_SIZE_1BYTE(cmd);
-+	else if (size == 2)
-+		SET_INDIRECT_REG_SIZE_2BYTE(cmd);
-+	else if (size == 4)
-+		SET_INDIRECT_REG_SIZE_4BYTE(cmd);
-+
-+	SET_INDIRECT_REG_ADDR(cmd, addr);
-+
-+	/* acquire indirect access lock */
-+	_enter_critical_mutex(mutex, NULL);
-+
-+	if (DBG_SDIO_INDIRECT_ACCESS)
-+		RTW_INFO(FUNC_ADPT_FMT" cmd:%02x %02x %02x %02x\n", FUNC_ADPT_ARG(padapter), cmd[0], cmd[1], cmd[2], cmd[3]);
-+
-+	err = sd_cmd52_write(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_CFG), 3, cmd);
-+	if (err)
-+		goto exit;
-+
-+	/* trigger */
-+	SET_INDIRECT_REG_READ(cmd);
-+
-+	if (DBG_SDIO_INDIRECT_ACCESS)
-+		RTW_INFO(FUNC_ADPT_FMT" cmd:%02x %02x %02x %02x\n", FUNC_ADPT_ARG(padapter), cmd[0], cmd[1], cmd[2], cmd[3]);
-+
-+	err = sd_cmd52_write(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_CFG + 2), 1, cmd + 2);
-+	if (err)
-+		goto exit;
-+
-+	/* polling for indirect access done */
-+	start = rtw_get_current_time();
-+	while (1) {
-+		if (rtw_is_surprise_removed(padapter)) {
-+			sr = 1;
-+			break;
-+		}
-+
-+		err = sd_cmd52_read(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_CFG + 2), 1, cmd + 2);
-+
-+		if (!err && GET_INDIRECT_REG_RDY(cmd))
-+			break;
-+
-+		if (rtw_get_passing_time_ms(start) > INDIRECT_ACCESS_TIMEOUT_MS) {
-+			timeout = 1;
-+			break;
-+		}
-+	}
-+	end = rtw_get_current_time();
-+
-+	if (timeout || sr)
-+		goto exit;
-+
-+	/* read result */
-+	err = sd_cmd52_read(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_DATA), size, val);
-+	if (size == 2)
-+		*((u16 *)(val)) = le16_to_cpu(*((u16 *)(val)));
-+	else if (size == 4)
-+		*((u32 *)(val)) = le32_to_cpu(*((u32 *)(val)));
-+
-+	if (DBG_SDIO_INDIRECT_ACCESS) {
-+		if (size == 1)
-+			RTW_INFO(FUNC_ADPT_FMT" val:0x%02x\n", FUNC_ADPT_ARG(padapter), *((u8 *)(val)));
-+		else if (size == 2)
-+			RTW_INFO(FUNC_ADPT_FMT" val:0x%04x\n", FUNC_ADPT_ARG(padapter), *((u16 *)(val)));
-+		else if (size == 4)
-+			RTW_INFO(FUNC_ADPT_FMT" val:0x%08x\n", FUNC_ADPT_ARG(padapter), *((u32 *)(val)));
-+	}
-+
-+exit:
-+	/* release indirect access lock */
-+	_exit_critical_mutex(mutex, NULL);
-+
-+	if (DBG_SDIO_INDIRECT_ACCESS) {
-+		RTW_INFO(FUNC_ADPT_FMT" addr:0x%0x size:%u, cmd:%02x %02x %02x %02x, to:%u, err:%u\n"
-+			, FUNC_ADPT_ARG(padapter), addr, size, cmd[0], cmd[1], cmd[2], cmd[3], timeout, err);
-+		if (start != 0 || end != 0) {
-+			RTW_INFO(FUNC_ADPT_FMT" polling %d ms\n"
-+				, FUNC_ADPT_ARG(padapter), rtw_get_time_interval_ms(start, end));
-+		}
-+	}
-+
-+	if (timeout) {
-+		RTW_ERR(FUNC_ADPT_FMT" addr:0x%0x timeout(err:%d), cmd\n"
-+			, FUNC_ADPT_ARG(padapter), addr, err);
-+		if (!err)
-+			err = -1; /* just for return value */
-+	} else if (err) {
-+		RTW_ERR(FUNC_ADPT_FMT" addr:0x%0x err:%d\n"
-+			, FUNC_ADPT_ARG(padapter), addr, err);
-+	} else if (sr) {
-+		/* just for return value */
-+		err = -1;
-+	}
-+
-+	if (!err && !timeout && !sr)
-+		_rtw_memcpy(v, val, size);
-+
-+	return err;
-+}
-+
-+s32 sdio_iwrite(PADAPTER padapter, u32 addr, u8 size, u8 *v)
-+{
-+	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
-+	_mutex *mutex = &adapter_to_dvobj(padapter)->sd_indirect_access_mutex;
-+
-+	u8 val[4] = {0};
-+	u8 cmd[4] = {0}; /* mapping to indirect access register, little endien */
-+	systime start = 0, end = 0;
-+	u8 timeout = 0;
-+	u8 sr = 0;
-+	s32 err = 0;
-+
-+	if (size == 1)
-+		SET_INDIRECT_REG_SIZE_1BYTE(cmd);
-+	else if (size == 2)
-+		SET_INDIRECT_REG_SIZE_2BYTE(cmd);
-+	else if (size == 4)
-+		SET_INDIRECT_REG_SIZE_4BYTE(cmd);
-+
-+	SET_INDIRECT_REG_ADDR(cmd, addr);
-+
-+	/* acquire indirect access lock */
-+	_enter_critical_mutex(mutex, NULL);
-+
-+	if (DBG_SDIO_INDIRECT_ACCESS)
-+		RTW_INFO(FUNC_ADPT_FMT" cmd:%02x %02x %02x %02x\n", FUNC_ADPT_ARG(padapter), cmd[0], cmd[1], cmd[2], cmd[3]);
-+
-+	err = sd_cmd52_write(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_CFG), 3, cmd);
-+	if (err)
-+		goto exit;
-+
-+	/* data to write */
-+	_rtw_memcpy(val, v, size);
-+
-+	if (DBG_SDIO_INDIRECT_ACCESS) {
-+		if (size == 1)
-+			RTW_INFO(FUNC_ADPT_FMT" val:0x%02x\n", FUNC_ADPT_ARG(padapter), *((u8 *)(val)));
-+		else if (size == 2)
-+			RTW_INFO(FUNC_ADPT_FMT" val:0x%04x\n", FUNC_ADPT_ARG(padapter), *((u16 *)(val)));
-+		else if (size == 4)
-+			RTW_INFO(FUNC_ADPT_FMT" val:0x%08x\n", FUNC_ADPT_ARG(padapter), *((u32 *)(val)));
-+	}
-+
-+	if (size == 2)
-+		*((u16 *)(val)) = cpu_to_le16(*((u16 *)(val)));
-+	else if (size == 4)
-+		*((u32 *)(val)) = cpu_to_le32(*((u32 *)(val)));
-+
-+	err = sd_cmd52_write(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_DATA), size, val);
-+	if (err)
-+		goto exit;
-+
-+	/* trigger */
-+	SET_INDIRECT_REG_WRITE(cmd);
-+
-+	if (DBG_SDIO_INDIRECT_ACCESS)
-+		RTW_INFO(FUNC_ADPT_FMT" cmd:%02x %02x %02x %02x\n", FUNC_ADPT_ARG(padapter), cmd[0], cmd[1], cmd[2], cmd[3]);
-+
-+	err = sd_cmd52_write(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_CFG + 2), 1, cmd + 2);
-+	if (err)
-+		goto exit;
-+
-+	/* polling for indirect access done */
-+	start = rtw_get_current_time();
-+	while (1) {
-+		if (rtw_is_surprise_removed(padapter)) {
-+			sr = 1;
-+			break;
-+		}
-+
-+		err = sd_cmd52_read(pintfhdl, SDIO_LOCAL_CMD_ADDR(SDIO_REG_INDIRECT_REG_CFG + 2), 1, cmd + 2);
-+
-+		if (!err && GET_INDIRECT_REG_RDY(cmd))
-+			break;
-+
-+		if (rtw_get_passing_time_ms(start) > INDIRECT_ACCESS_TIMEOUT_MS) {
-+			timeout = 1;
-+			break;
-+		}
-+	}
-+	end = rtw_get_current_time();
-+
-+	if (timeout || sr)
-+		goto exit;
-+
-+exit:
-+	/* release indirect access lock */
-+	_exit_critical_mutex(mutex, NULL);
-+
-+	if (DBG_SDIO_INDIRECT_ACCESS) {
-+		RTW_INFO(FUNC_ADPT_FMT" addr:0x%0x size:%u, cmd:%02x %02x %02x %02x, to:%u, err:%u\n"
-+			, FUNC_ADPT_ARG(padapter), addr, size, cmd[0], cmd[1], cmd[2], cmd[3], timeout, err);
-+		if (start != 0 || end != 0) {
-+			RTW_INFO(FUNC_ADPT_FMT" polling %d ms\n"
-+				, FUNC_ADPT_ARG(padapter), rtw_get_time_interval_ms(start, end));
-+		}
-+	}
-+
-+	if (timeout) {
-+		RTW_ERR(FUNC_ADPT_FMT" addr:0x%0x timeout(err:%d), cmd\n"
-+			, FUNC_ADPT_ARG(padapter), addr, err);
-+		if (!err)
-+			err = -1; /* just for return value */
-+	} else if (err) {
-+		RTW_ERR(FUNC_ADPT_FMT" addr:0x%0x err:%d\n"
-+			, FUNC_ADPT_ARG(padapter), addr, err);
-+	} else if (sr) {
-+		/* just for return value */
-+		err = -1;
-+	}
-+
-+	return err;
-+}
-+
-+u8 sdio_iread8(struct intf_hdl *pintfhdl, u32 addr)
-+{
-+	u8 val;
-+
-+	if (sdio_iread(pintfhdl->padapter, addr, 1, (u8 *)&val) != 0)
-+		val = SDIO_ERR_VAL8;
-+
-+	return val;
-+}
-+
-+u16 sdio_iread16(struct intf_hdl *pintfhdl, u32 addr)
-+{
-+	u16 val;
-+
-+	if (sdio_iread(pintfhdl->padapter, addr, 2, (u8 *)&val) != 0)
-+		val = SDIO_ERR_VAL16;
-+
-+	return val;
-+}
-+
-+u32 sdio_iread32(struct intf_hdl *pintfhdl, u32 addr)
-+{
-+	u32 val;
-+
-+	if (sdio_iread(pintfhdl->padapter, addr, 4, (u8 *)&val) != 0)
-+		val = SDIO_ERR_VAL32;
-+
-+	return val;
-+}
-+
-+s32 sdio_iwrite8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
-+{
-+	return sdio_iwrite(pintfhdl->padapter, addr, 1, (u8 *)&val);
-+}
-+
-+s32 sdio_iwrite16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
-+{
-+	return sdio_iwrite(pintfhdl->padapter, addr, 2, (u8 *)&val);
-+}
-+
-+s32 sdio_iwrite32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
-+{
-+	return sdio_iwrite(pintfhdl->padapter, addr, 4, (u8 *)&val);
-+}
-+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
-+u32 cmd53_4byte_alignment(struct intf_hdl *pintfhdl, u32 addr)
-+{
-+	u32 addr_rdr;
-+	u32 value;
-+
-+	value = 0;
-+	addr_rdr = addr % 4;
-+
-+	if (addr_rdr) {
-+		u8 shift_bit;
-+
-+		shift_bit = addr_rdr * 8;
-+		value = (sd_read32(pintfhdl, (addr - addr_rdr), NULL)) >> shift_bit;
-+	} else
-+		value = sd_read32(pintfhdl, addr, NULL);
-+	
-+	return value;
-+}
-+
-+#endif /* !RTW_HALMAC */
-+
-+#ifndef CONFIG_SDIO_TX_TASKLET
-+#ifdef SDIO_FREE_XMIT_BUF_SEMA
-+void _rtw_sdio_free_xmitbuf_sema_up(struct xmit_priv *xmit)
-+{
-+	_rtw_up_sema(&xmit->sdio_free_xmitbuf_sema);
-+}
-+
-+void _rtw_sdio_free_xmitbuf_sema_down(struct xmit_priv *xmit)
-+{
-+	_rtw_down_sema(&xmit->sdio_free_xmitbuf_sema);
-+}
-+
-+#ifdef DBG_SDIO_FREE_XMIT_BUF_SEMA
-+void dbg_rtw_sdio_free_xmitbuf_sema_up(struct xmit_priv *xmit, const char *caller)
-+{
-+	/* just for debug usage only, pleae take care for the different of count implementaton */
-+	RTW_INFO("%s("ADPT_FMT") before up sdio_free_xmitbuf_sema, count:%u\n"
-+		, caller, ADPT_ARG(xmit->adapter), xmit->sdio_free_xmitbuf_sema.count);
-+	_rtw_sdio_free_xmitbuf_sema_up(xmit);
-+}
-+
-+void dbg_rtw_sdio_free_xmitbuf_sema_down(struct xmit_priv *xmit, const char *caller)
-+{
-+	/* just for debug usage only, pleae take care for the different of count implementaton */
-+	RTW_INFO("%s("ADPT_FMT") before down sdio_free_xmitbuf_sema, count:%u\n"
-+		, caller, ADPT_ARG(xmit->adapter), xmit->sdio_free_xmitbuf_sema.count);
-+	_rtw_sdio_free_xmitbuf_sema_down(xmit);
-+}
-+#endif /* DBG_SDIO_FREE_XMIT_BUF_SEMA */
-+
-+#endif /* SDIO_FREE_XMIT_BUF_SEMA */
-+#endif /* !CONFIG_SDIO_TX_TASKLET */
-+
-+s32 sdio_initrecvbuf(struct recv_buf *recvbuf, _adapter *adapter)
-+{
-+	_rtw_init_listhead(&recvbuf->list);
-+#ifdef PLATFORM_WINDOWS
-+	_rtw_spinlock_init(&recvbuf->recvbuf_lock);
-+#endif
-+	recvbuf->adapter = adapter;
-+
-+	return _SUCCESS;
-+}
-+
-+void sdio_freerecvbuf(struct recv_buf *recvbuf)
-+{
-+#ifdef PLATFORM_WINDOWS
-+	_rtw_spinlock_free(&recvbuf->recvbuf_lock);
-+#endif
-+}
-+
-+#ifdef CONFIG_SDIO_RECVBUF_PWAIT
-+void dump_recvbuf_pwait_conf(void *sel, struct recv_priv *recvpriv)
-+{
-+	struct rtw_pwait_conf *conf = &recvpriv->recvbuf_pwait.conf;
-+
-+	RTW_PRINT_SEL(sel, "%-4s %-10s %-10s\n"
-+		, "type", "time", "cnt_lmt");
-+	RTW_PRINT_SEL(sel, "%4s %10d %10d\n"
-+		, rtw_pwait_type_str(conf->type), conf->wait_time, conf->wait_cnt_lmt);
-+}
-+
-+#ifdef CONFIG_SDIO_RECVBUF_PWAIT_RUNTIME_ADJUST
-+int recvbuf_pwait_config_req(struct recv_priv *recvpriv, enum rtw_pwait_type type, s32 time, s32 cnt_lmt)
-+{
-+	struct recv_buf *rbuf;
-+	struct rtw_pwait_conf *conf;
-+	int ret = _FAIL;
-+
-+	rbuf = rtw_malloc(sizeof(*rbuf) + sizeof(struct rtw_pwait_conf));
-+	if (!rbuf)
-+		goto exit;
-+
-+	sdio_initrecvbuf(rbuf, recvpriv->adapter);
-+	rbuf->type = RBUF_TYPE_PWAIT_ADJ;
-+	rbuf->pbuf = ((u8*)rbuf) + sizeof(*rbuf);
-+	conf = (struct rtw_pwait_conf *)rbuf->pbuf;
-+	conf->type = type;
-+	conf->wait_time = time;
-+	conf->wait_cnt_lmt = cnt_lmt;
-+
-+	ret = rtw_enqueue_recvbuf(rbuf, &recvpriv->free_recv_buf_queue);
-+	if (0 && ret == _SUCCESS) {
-+		RTW_INFO("request recvbuf_pwait with type=%s time=%d cnt_lmt=%d\n"
-+			, rtw_pwait_type_str(type), time, cnt_lmt);
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+int recvbuf_pwait_config_hdl(struct recv_priv *recvpriv, struct recv_buf *rbuf)
-+{
-+	struct rtw_pwait_conf *conf = (struct rtw_pwait_conf *)rbuf->pbuf;
-+	int ret = rtw_pwctx_config(&recvpriv->recvbuf_pwait, conf->type, conf->wait_time, conf->wait_cnt_lmt);
-+
-+	if (0 && ret == _SUCCESS) {
-+		RTW_INFO("config recvbuf_pwait with type=%s time=%d cnt_lmt=%d\n"
-+			, rtw_pwait_type_str(conf->type), conf->wait_time, conf->wait_cnt_lmt);
-+	}
-+	sdio_freerecvbuf(rbuf);
-+	rtw_mfree(rbuf, sizeof(*rbuf) + sizeof(*conf));
-+
-+	return ret;
-+}
-+#endif /* CONFIG_SDIO_RECVBUF_PWAIT_RUNTIME_ADJUST */
-+#endif /* CONFIG_SDIO_RECVBUF_PWAIT */
-+
-diff --git a/drivers/staging/rtl8723cs/hal/hal_hci/hal_sdio_coex.c b/drivers/staging/rtl8723cs/hal/hal_hci/hal_sdio_coex.c
-new file mode 100644
-index 000000000000..564e4089a737
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_hci/hal_sdio_coex.c
-@@ -0,0 +1,35 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 Realtek Corporation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
-+ *
-+ *
-+ ******************************************************************************/
-+
-+#include <drv_types.h>
-+#include <hal_data.h>	/* HAL_DATA_TYPE */
-+
-+#ifdef CONFIG_SDIO_MULTI_FUNCTION_COEX
-+
-+int rtw_sdio_multi_state = SDIO_MULTI_WIFI;
-+EXPORT_SYMBOL(rtw_sdio_multi_state);
-+
-+bool ex_hal_sdio_multi_if_bus_available(PADAPTER adapter)
-+{
-+	return rtw_sdio_multi_state == SDIO_MULTI_WIFI;
-+}
-+
-+#endif  /* CONFIG_SDIO_MULTI_FUNCTION_COEX */
-+
-diff --git a/drivers/staging/rtl8723cs/hal/hal_intf.c b/drivers/staging/rtl8723cs/hal/hal_intf.c
-new file mode 100644
-index 000000000000..c39b37b773a7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_intf.c
-@@ -0,0 +1,2350 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#define _HAL_INTF_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+const u32 _chip_type_to_odm_ic_type[] = {
-+	0,
-+	ODM_RTL8188E,
-+	ODM_RTL8192E,
-+	ODM_RTL8812,
-+	ODM_RTL8821,
-+	ODM_RTL8723B,
-+	ODM_RTL8814A,
-+	ODM_RTL8703B,
-+	ODM_RTL8188F,
-+	ODM_RTL8188F,
-+	ODM_RTL8822B,
-+	ODM_RTL8723D,
-+	ODM_RTL8821C,
-+	ODM_RTL8710B,
-+	ODM_RTL8192F,
-+	ODM_RTL8822C,
-+	ODM_RTL8814B,
-+	ODM_RTL8723F,
-+	0,
-+};
-+
-+void rtw_hal_chip_configure(_adapter *padapter)
-+{
-+	padapter->hal_func.intf_chip_configure(padapter);
-+}
-+
-+/*
-+ * Description:
-+ *	Read chip internal ROM data
-+ *
-+ * Return:
-+ *	_SUCCESS success
-+ *	_FAIL	 fail
-+ */
-+u8 rtw_hal_read_chip_info(_adapter *padapter)
-+{
-+	u8 rtn = _SUCCESS;
-+	u8 hci_type = rtw_get_intf_type(padapter);
-+	systime start = rtw_get_current_time();
-+
-+	/*  before access eFuse, make sure card enable has been called */
-+	if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
-+	    && !rtw_is_hw_init_completed(padapter))
-+		rtw_hal_power_on(padapter);
-+
-+	rtn = padapter->hal_func.read_adapter_info(padapter);
-+
-+	if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
-+	    && !rtw_is_hw_init_completed(padapter))
-+		rtw_hal_power_off(padapter);
-+
-+	RTW_INFO("%s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
-+
-+	return rtn;
-+}
-+
-+void rtw_hal_read_chip_version(_adapter *padapter)
-+{
-+	padapter->hal_func.read_chip_version(padapter);
-+	rtw_odm_init_ic_type(padapter);
-+}
-+
-+static void rtw_init_wireless_mode(_adapter *padapter)
-+{
-+	u8 proto_wireless_mode = 0;
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+	if(hal_spec->proto_cap & PROTO_CAP_11B)
-+		proto_wireless_mode |= WIRELESS_11B;
-+	
-+	if(hal_spec->proto_cap & PROTO_CAP_11G)
-+		proto_wireless_mode |= WIRELESS_11G;
-+#ifdef CONFIG_80211AC_VHT
-+	if(hal_spec->band_cap & BAND_CAP_5G)
-+		proto_wireless_mode |= WIRELESS_11A;
-+#endif
-+
-+#ifdef CONFIG_80211N_HT
-+	if(hal_spec->proto_cap & PROTO_CAP_11N) {
-+
-+		if(hal_spec->band_cap & BAND_CAP_2G)
-+			proto_wireless_mode |= WIRELESS_11_24N;
-+		if(hal_spec->band_cap & BAND_CAP_5G)
-+			proto_wireless_mode |= WIRELESS_11_5N;
-+	}
-+#endif
-+
-+#ifdef CONFIG_80211AC_VHT
-+	if(hal_spec->proto_cap & PROTO_CAP_11AC) 
-+		proto_wireless_mode |= WIRELESS_11AC;
-+#endif
-+	padapter->registrypriv.wireless_mode &= proto_wireless_mode;
-+}
-+
-+void rtw_hal_def_value_init(_adapter *padapter)
-+{
-+	if (is_primary_adapter(padapter)) {
-+		/*init fw_psmode_iface_id*/
-+		adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff;
-+		/*wireless_mode*/
-+		rtw_init_wireless_mode(padapter);
-+		padapter->hal_func.init_default_value(padapter);
-+
-+		rtw_init_hal_com_default_value(padapter);
-+		
-+		#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+		adapter_to_dvobj(padapter)->dft.port_id = 0xFF;
-+		adapter_to_dvobj(padapter)->dft.mac_id = 0xFF;
-+		#endif
-+		#ifdef CONFIG_HW_P0_TSF_SYNC
-+		adapter_to_dvobj(padapter)->p0_tsf.sync_port = MAX_HW_PORT;
-+		adapter_to_dvobj(padapter)->p0_tsf.offset = 0;
-+		#endif
-+
-+		GET_HAL_DATA(padapter)->rx_tsf_addr_filter_config = 0;
-+	}
-+}
-+
-+u8 rtw_hal_data_init(_adapter *padapter)
-+{
-+	if (is_primary_adapter(padapter)) {
-+		padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
-+		padapter->HalData = rtw_zvmalloc(padapter->hal_data_sz);
-+		if (padapter->HalData == NULL) {
-+			RTW_INFO("cant not alloc memory for HAL DATA\n");
-+			return _FAIL;
-+		}
-+		rtw_phydm_priv_init(padapter);
-+	}
-+	return _SUCCESS;
-+}
-+
-+void rtw_hal_data_deinit(_adapter *padapter)
-+{
-+	if (is_primary_adapter(padapter)) {
-+		if (padapter->HalData) {
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+			phy_free_filebuf(padapter);
-+#endif
-+			rtw_vmfree(padapter->HalData, padapter->hal_data_sz);
-+			padapter->HalData = NULL;
-+			padapter->hal_data_sz = 0;
-+		}
-+	}
-+}
-+
-+void	rtw_hal_free_data(_adapter *padapter)
-+{
-+	/* free HAL Data	 */
-+	rtw_hal_data_deinit(padapter);
-+}
-+void rtw_hal_dm_init(_adapter *padapter)
-+{
-+	if (is_primary_adapter(padapter)) {
-+		PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+
-+		padapter->hal_func.dm_init(padapter);
-+
-+		_rtw_spinlock_init(&pHalData->IQKSpinLock);
-+
-+		#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+		if (pHalData->txpwr_pg_mode == TXPWR_PG_WITH_PWR_IDX)
-+			hal_load_txpwr_info(padapter);
-+		#endif
-+		phy_load_tx_power_ext_info(padapter, 1);
-+	}
-+}
-+void rtw_hal_dm_deinit(_adapter *padapter)
-+{
-+	if (is_primary_adapter(padapter)) {
-+		PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+
-+		padapter->hal_func.dm_deinit(padapter);
-+
-+		_rtw_spinlock_free(&pHalData->IQKSpinLock);
-+	}
-+}
-+
-+enum rf_type rtw_chip_rftype_to_hal_rftype(_adapter *adapter, u8 limit)
-+{
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
-+	u8 tx_num = 0, rx_num = 0;
-+
-+	/*get RF PATH from version_id.RF_TYPE */
-+	if (IS_1T1R(hal_data->version_id)) {
-+		tx_num = 1;
-+		rx_num = 1;
-+	} else if (IS_1T2R(hal_data->version_id)) {
-+		tx_num = 1;
-+		rx_num = 2;
-+	} else if (IS_2T2R(hal_data->version_id)) {
-+		tx_num = 2;
-+		rx_num = 2;
-+	} else if (IS_2T3R(hal_data->version_id)) {
-+		tx_num = 2;
-+		rx_num = 3;
-+	} else if (IS_2T4R(hal_data->version_id)) {
-+		tx_num = 2;
-+		rx_num = 4;
-+	} else if (IS_3T3R(hal_data->version_id)) {
-+		tx_num = 3;
-+		rx_num = 3;
-+	} else if (IS_3T4R(hal_data->version_id)) {
-+		tx_num = 3;
-+		rx_num = 4;
-+	} else if (IS_4T4R(hal_data->version_id)) {
-+		tx_num = 4;
-+		rx_num = 4;
-+	}
-+
-+	if (limit) {
-+		tx_num = rtw_min(tx_num, limit);
-+		rx_num = rtw_min(rx_num, limit);
-+	}
-+
-+	return trx_num_to_rf_type(tx_num, rx_num);
-+}
-+
-+void dump_hal_runtime_trx_mode(void *sel, _adapter *adapter)
-+{
-+	struct registry_priv *regpriv = &adapter->registrypriv;
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
-+	int i;
-+
-+	RTW_PRINT_SEL(sel, "txpath=0x%x, rxpath=0x%x\n", hal_data->txpath, hal_data->rxpath);
-+	for (i = 0; i < hal_data->tx_nss; i++)
-+		RTW_PRINT_SEL(sel, "txpath_%uss:0x%x, num:%u\n"
-+			, i + 1, hal_data->txpath_nss[i]
-+			, hal_data->txpath_num_nss[i]);
-+}
-+
-+void dump_hal_trx_mode(void *sel, _adapter *adapter)
-+{
-+	struct registry_priv *regpriv = &adapter->registrypriv;
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
-+	int i;
-+
-+	RTW_PRINT_SEL(sel, "trx_path_bmp:0x%02x(%s), NumTotalRFPath:%u, max_tx_cnt:%u\n"
-+		, hal_data->trx_path_bmp
-+		, rf_type_to_rfpath_str(hal_data->rf_type)
-+		, hal_data->NumTotalRFPath
-+		, hal_data->max_tx_cnt
-+	);
-+	RTW_PRINT_SEL(sel, "tx_nss:%u, rx_nss:%u\n"
-+		, hal_data->tx_nss, hal_data->rx_nss);
-+	for (i = 0; i < hal_data->tx_nss; i++)
-+		RTW_PRINT_SEL(sel, "txpath_cap_num_%uss:%u\n"
-+			, i + 1, hal_data->txpath_cap_num_nss[i]);
-+	RTW_PRINT_SEL(sel, "\n");
-+
-+	dump_hal_runtime_trx_mode(sel, adapter);
-+}
-+
-+void _dump_rf_path(void *sel, _adapter *adapter)
-+{
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+
-+	RTW_PRINT_SEL(sel, "[RF_PATH] ver_id.RF_TYPE:%s\n"
-+		, rf_type_to_rfpath_str(rtw_chip_rftype_to_hal_rftype(adapter, 0)));
-+	RTW_PRINT_SEL(sel, "[RF_PATH] HALSPEC's rf_reg_trx_path_bmp:0x%02x, rf_reg_path_avail_num:%u, max_tx_cnt:%u\n"
-+		, hal_spec->rf_reg_trx_path_bmp, hal_spec->rf_reg_path_avail_num, hal_spec->max_tx_cnt);
-+	RTW_PRINT_SEL(sel, "[RF_PATH] PG's trx_path_bmp:0x%02x, max_tx_cnt:%u\n"
-+		, hal_data->eeprom_trx_path_bmp, hal_data->eeprom_max_tx_cnt);
-+	RTW_PRINT_SEL(sel, "[RF_PATH] Registry's trx_path_bmp:0x%02x, tx_path_lmt:%u, rx_path_lmt:%u\n"
-+		, regsty->trx_path_bmp, regsty->tx_path_lmt, regsty->rx_path_lmt);
-+	RTW_PRINT_SEL(sel, "[RF_PATH] HALDATA's trx_path_bmp:0x%02x, max_tx_cnt:%u\n"
-+		, hal_data->trx_path_bmp, hal_data->max_tx_cnt);
-+	RTW_PRINT_SEL(sel, "[RF_PATH] HALDATA's rf_type:%s, NumTotalRFPath:%d\n"
-+		, rf_type_to_rfpath_str(hal_data->rf_type), hal_data->NumTotalRFPath);
-+}
-+
-+#ifdef CONFIG_RTL8814A
-+extern enum rf_type rtl8814a_rfpath_decision(_adapter *adapter);
-+#endif
-+
-+u8 rtw_hal_rfpath_init(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+
-+#ifdef CONFIG_RTL8814A
-+if (IS_HARDWARE_TYPE_8814A(adapter)) {
-+	enum bb_path tx_bmp, rx_bmp;
-+	hal_data->rf_type = rtl8814a_rfpath_decision(adapter);
-+	rf_type_to_default_trx_bmp(hal_data->rf_type, &tx_bmp, &rx_bmp);
-+	hal_data->trx_path_bmp = (tx_bmp << 4) | rx_bmp;
-+	hal_data->NumTotalRFPath = 4;
-+	hal_data->max_tx_cnt = hal_spec->max_tx_cnt;
-+	hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, rf_type_to_rf_tx_cnt(hal_data->rf_type));
-+} else
-+#endif
-+{
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+	u8 trx_path_bmp;
-+	u8 tx_path_num;
-+	u8 rx_path_num;
-+	int i;
-+
-+	trx_path_bmp = hal_spec->rf_reg_trx_path_bmp;
-+	
-+	if (regsty->trx_path_bmp != 0x00) {
-+		/* restrict trx_path_bmp with regsty.trx_path_bmp */
-+		trx_path_bmp &= regsty->trx_path_bmp;
-+		if (!trx_path_bmp) {
-+			RTW_ERR("%s hal_spec.rf_reg_trx_path_bmp:0x%02x, regsty->trx_path_bmp:0x%02x no intersection\n"
-+				, __func__, hal_spec->rf_reg_trx_path_bmp, regsty->trx_path_bmp);
-+			return _FAIL;
-+		}
-+	} else if (hal_data->eeprom_trx_path_bmp != 0x00) {
-+		/* restrict trx_path_bmp with eeprom_trx_path_bmp */
-+		trx_path_bmp &= hal_data->eeprom_trx_path_bmp;
-+		if (!trx_path_bmp) {
-+			RTW_ERR("%s hal_spec.rf_reg_trx_path_bmp:0x%02x, hal_data->eeprom_trx_path_bmp:0x%02x no intersection\n"
-+				, __func__, hal_spec->rf_reg_trx_path_bmp, hal_data->eeprom_trx_path_bmp);
-+			return _FAIL;
-+		}
-+	}
-+
-+	/* restrict trx_path_bmp with TX and RX num limit */
-+	trx_path_bmp = rtw_restrict_trx_path_bmp_by_trx_num_lmt(trx_path_bmp
-+		, regsty->tx_path_lmt, regsty->rx_path_lmt, &tx_path_num, &rx_path_num);
-+	if (!trx_path_bmp) {
-+		RTW_ERR("%s rtw_restrict_trx_path_bmp_by_trx_num_lmt(0x%02x, %u, %u) failed\n"
-+			, __func__, trx_path_bmp, regsty->tx_path_lmt, regsty->rx_path_lmt);
-+		return _FAIL;
-+	}
-+	hal_data->trx_path_bmp = trx_path_bmp;
-+	hal_data->rf_type = trx_bmp_to_rf_type((trx_path_bmp & 0xF0) >> 4, trx_path_bmp & 0x0F);
-+	hal_data->NumTotalRFPath = rtw_max(tx_path_num, rx_path_num);
-+
-+	hal_data->max_tx_cnt = hal_spec->max_tx_cnt;
-+	hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, tx_path_num);
-+	if (hal_data->eeprom_max_tx_cnt)
-+		hal_data->max_tx_cnt = rtw_min(hal_data->max_tx_cnt, hal_data->eeprom_max_tx_cnt);
-+
-+	if (1)
-+		_dump_rf_path(RTW_DBGDUMP, adapter);
-+}
-+
-+	RTW_INFO("%s trx_path_bmp:0x%02x(%s), NumTotalRFPath:%u, max_tx_cnt:%u\n"
-+		, __func__
-+		, hal_data->trx_path_bmp
-+		, rf_type_to_rfpath_str(hal_data->rf_type)
-+		, hal_data->NumTotalRFPath
-+		, hal_data->max_tx_cnt);
-+
-+	return _SUCCESS;
-+}
-+
-+void _dump_trx_nss(void *sel, _adapter *adapter)
-+{
-+	struct registry_priv *regpriv = &adapter->registrypriv;
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+
-+	RTW_PRINT_SEL(sel, "[TRX_Nss] HALSPEC - tx_nss:%d, rx_nss:%d\n", hal_spec->tx_nss_num, hal_spec->rx_nss_num);
-+	RTW_PRINT_SEL(sel, "[TRX_Nss] Registry - tx_nss:%d, rx_nss:%d\n", regpriv->tx_nss, regpriv->rx_nss);
-+	RTW_PRINT_SEL(sel, "[TRX_Nss] HALDATA - tx_nss:%d, rx_nss:%d\n", GET_HAL_TX_NSS(adapter), GET_HAL_RX_NSS(adapter));
-+
-+}
-+#define NSS_VALID(nss) (nss > 0)
-+
-+u8 rtw_hal_trxnss_init(_adapter *adapter)
-+{
-+	struct registry_priv *regpriv = &adapter->registrypriv;
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
-+	enum rf_type rf_path = GET_HAL_RFPATH(adapter);
-+	int i;
-+
-+	hal_data->tx_nss = hal_spec->tx_nss_num;
-+	hal_data->rx_nss = hal_spec->rx_nss_num;
-+
-+	if (NSS_VALID(regpriv->tx_nss))
-+		hal_data->tx_nss = rtw_min(hal_data->tx_nss, regpriv->tx_nss);
-+	hal_data->tx_nss = rtw_min(hal_data->tx_nss, hal_data->max_tx_cnt);
-+	if (NSS_VALID(regpriv->rx_nss))
-+		hal_data->rx_nss = rtw_min(hal_data->rx_nss, regpriv->rx_nss);
-+	hal_data->rx_nss = rtw_min(hal_data->rx_nss, rf_type_to_rf_rx_cnt(rf_path));
-+
-+	for (i = 0; i < 4; i++) {
-+		if (hal_data->tx_nss < i + 1)
-+			break;
-+
-+		if (IS_HARDWARE_TYPE_8814B(adapter) /* 8814B is always full-TX */
-+			#ifdef CONFIG_RTW_TX_NPATH_EN
-+			/* these IC is capable of full-TX when macro defined */
-+			|| IS_HARDWARE_TYPE_8192E(adapter) || IS_HARDWARE_TYPE_8192F(adapter)
-+			|| IS_HARDWARE_TYPE_8812(adapter) || IS_HARDWARE_TYPE_8822B(adapter)
-+			|| IS_HARDWARE_TYPE_8822C(adapter)
-+			#endif
-+		)
-+			hal_data->txpath_cap_num_nss[i] = hal_data->max_tx_cnt;
-+		else
-+			hal_data->txpath_cap_num_nss[i] = i + 1;
-+	}
-+
-+	if (1)
-+		_dump_trx_nss(RTW_DBGDUMP, adapter);
-+
-+	RTW_INFO("%s tx_nss:%u, rx_nss:%u\n", __func__
-+		, hal_data->tx_nss, hal_data->rx_nss);
-+
-+	return _SUCCESS;
-+}
-+
-+#ifdef CONFIG_RTW_SW_LED
-+void rtw_hal_sw_led_init(_adapter *padapter)
-+{
-+	struct led_priv *ledpriv = adapter_to_led(padapter);
-+
-+	if (ledpriv->bRegUseLed == _FALSE)
-+		return;
-+
-+	if (!is_primary_adapter(padapter))
-+		return;
-+
-+	if (padapter->hal_func.InitSwLeds) {
-+		padapter->hal_func.InitSwLeds(padapter);
-+		rtw_led_set_ctl_en_mask_primary(padapter);
-+		rtw_led_set_iface_en(padapter, 1);
-+	}
-+}
-+
-+void rtw_hal_sw_led_deinit(_adapter *padapter)
-+{
-+	struct led_priv *ledpriv = adapter_to_led(padapter);
-+
-+	if (ledpriv->bRegUseLed == _FALSE)
-+		return;
-+
-+	if (!is_primary_adapter(padapter))
-+		return;
-+
-+	if (padapter->hal_func.DeInitSwLeds)
-+		padapter->hal_func.DeInitSwLeds(padapter);
-+}
-+#endif
-+
-+u32 rtw_hal_power_on(_adapter *padapter)
-+{
-+	u32 ret = 0;
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+
-+	ret = padapter->hal_func.hal_power_on(padapter);
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if ((ret == _SUCCESS) && (pHalData->EEPROMBluetoothCoexist == _TRUE))
-+		rtw_btcoex_PowerOnSetting(padapter);
-+#endif
-+
-+	return ret;
-+}
-+void rtw_hal_power_off(_adapter *padapter)
-+{
-+	struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl;
-+
-+	_rtw_memset(macid_ctl->h2c_msr, 0, MACID_NUM_SW_LIMIT);
-+	_rtw_memset(macid_ctl->op_num, 0, H2C_MSR_ROLE_MAX);
-+
-+#ifdef CONFIG_LPS_1T1R
-+	GET_HAL_DATA(padapter)->lps_1t1r = 0;
-+#endif
-+
-+#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_PowerOffSetting(padapter);
-+#endif
-+
-+	padapter->hal_func.hal_power_off(padapter);
-+}
-+
-+
-+void rtw_hal_init_opmode(_adapter *padapter)
-+{
-+	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType = Ndis802_11InfrastructureMax;
-+	struct  mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	sint fw_state;
-+
-+	fw_state = get_fwstate(pmlmepriv);
-+
-+	if (fw_state & WIFI_ADHOC_STATE)
-+		networkType = Ndis802_11IBSS;
-+	else if (fw_state & WIFI_STATION_STATE)
-+		networkType = Ndis802_11Infrastructure;
-+#ifdef CONFIG_AP_MODE
-+	else if (fw_state & WIFI_AP_STATE)
-+		networkType = Ndis802_11APMode;
-+#endif
-+#ifdef CONFIG_RTW_MESH
-+	else if (fw_state & WIFI_MESH_STATE)
-+		networkType = Ndis802_11_mesh;
-+#endif
-+	else
-+		return;
-+
-+	rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_DIRECTLY);
-+}
-+
-+#ifdef CONFIG_NEW_NETDEV_HDL
-+uint rtw_hal_iface_init(_adapter *adapter)
-+{
-+	uint status = _SUCCESS;
-+
-+	rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(adapter));
-+	#ifdef RTW_HALMAC
-+	rtw_hal_hw_port_enable(adapter);
-+	#endif
-+	rtw_sec_restore_wep_key(adapter);
-+	rtw_hal_init_opmode(adapter);
-+	rtw_hal_start_thread(adapter);
-+	return status;
-+}
-+uint rtw_hal_init(_adapter *padapter)
-+{
-+	uint status = _SUCCESS;
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+
-+	halrf_set_rfsupportability(adapter_to_phydm(padapter));
-+
-+	status = padapter->hal_func.hal_init(padapter);
-+
-+	if(pHalData ->phydm_init_result) {
-+
-+		status = _FAIL;
-+		RTW_ERR("%s phydm init fail reason=%u \n",
-+			__func__,
-+			pHalData ->phydm_init_result);
-+	}
-+
-+	if (status == _SUCCESS) {
-+		rtw_set_hw_init_completed(padapter, _TRUE);
-+		if (padapter->registrypriv.notch_filter == 1)
-+			rtw_hal_notch_filter(padapter, 1);
-+		rtw_led_control(padapter, LED_CTL_POWER_ON);
-+		init_hw_mlme_ext(padapter);
-+		#ifdef CONFIG_RF_POWER_TRIM
-+		rtw_bb_rf_gain_offset(padapter);
-+		#endif /*CONFIG_RF_POWER_TRIM*/
-+		GET_PRIMARY_ADAPTER(padapter)->bup = _TRUE; /*temporary*/
-+		#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+		rtw_mi_set_mbid_cam(padapter);
-+		#endif
-+		#ifdef CONFIG_SUPPORT_MULTI_BCN
-+		rtw_ap_multi_bcn_cfg(padapter);
-+		#endif
-+		#if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
-+		#ifdef CONFIG_DYNAMIC_SOML
-+		rtw_dyn_soml_config(padapter);
-+		#endif
-+		#endif
-+		#ifdef CONFIG_TDMADIG
-+		rtw_phydm_tdmadig(padapter, TDMADIG_INIT);
-+		#endif/*CONFIG_TDMADIG*/
-+		rtw_phydm_dyn_rrsr_en(padapter,padapter->registrypriv.en_dyn_rrsr);
-+		#ifdef RTW_HALMAC
-+		RTW_INFO("%s: padapter->registrypriv.set_rrsr_value=0x%x\n", __func__,padapter->registrypriv.set_rrsr_value);
-+		if(padapter->registrypriv.set_rrsr_value != 0xFFFFFFFF)
-+			rtw_phydm_set_rrsr(padapter, padapter->registrypriv.set_rrsr_value, TRUE);
-+		#endif
-+	} else {
-+		rtw_set_hw_init_completed(padapter, _FALSE);
-+		RTW_ERR("%s: hal_init fail\n", __func__);
-+	}
-+	return status;
-+}
-+#else
-+uint	 rtw_hal_init(_adapter *padapter)
-+{
-+	uint	status = _SUCCESS;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+	int i;
-+
-+	halrf_set_rfsupportability(adapter_to_phydm(padapter));
-+
-+	status = padapter->hal_func.hal_init(padapter);
-+
-+	if(pHalData ->phydm_init_result) {
-+
-+		status = _FAIL;
-+		RTW_ERR("%s phydm init fail reason=%u \n",
-+				__func__,
-+				pHalData->phydm_init_result);
-+	}
-+
-+	if (status == _SUCCESS) {
-+		rtw_set_hw_init_completed(padapter, _TRUE);
-+		rtw_mi_set_mac_addr(padapter);/*set mac addr of all ifaces*/
-+		#ifdef RTW_HALMAC
-+		rtw_restore_hw_port_cfg(padapter);
-+		#endif
-+		if (padapter->registrypriv.notch_filter == 1)
-+			rtw_hal_notch_filter(padapter, 1);
-+
-+		for (i = 0; i < dvobj->iface_nums; i++)
-+			rtw_sec_restore_wep_key(dvobj->padapters[i]);
-+
-+		rtw_led_control(padapter, LED_CTL_POWER_ON);
-+
-+		init_hw_mlme_ext(padapter);
-+
-+		rtw_hal_init_opmode(padapter);
-+
-+		#ifdef CONFIG_RF_POWER_TRIM
-+		rtw_bb_rf_gain_offset(padapter);
-+		#endif /*CONFIG_RF_POWER_TRIM*/
-+
-+		#ifdef CONFIG_SUPPORT_MULTI_BCN
-+		rtw_ap_multi_bcn_cfg(padapter);
-+		#endif
-+
-+#if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
-+#ifdef CONFIG_DYNAMIC_SOML
-+		rtw_dyn_soml_config(padapter);
-+#endif
-+#endif
-+		#ifdef CONFIG_TDMADIG
-+		rtw_phydm_tdmadig(padapter, TDMADIG_INIT);
-+		#endif/*CONFIG_TDMADIG*/
-+
-+		rtw_phydm_dyn_rrsr_en(padapter,padapter->registrypriv.en_dyn_rrsr);
-+		#ifdef RTW_HALMAC
-+		RTW_INFO("%s: padapter->registrypriv.set_rrsr_value=0x%x\n", __func__,padapter->registrypriv.set_rrsr_value);
-+		if(padapter->registrypriv.set_rrsr_value != 0xFFFFFFFF)
-+			rtw_phydm_set_rrsr(padapter, padapter->registrypriv.set_rrsr_value, TRUE);
-+		#endif
-+
-+	} else {
-+		rtw_set_hw_init_completed(padapter, _FALSE);
-+		RTW_ERR("%s: fail\n", __func__);
-+	}
-+
-+
-+	return status;
-+
-+}
-+#endif
-+
-+uint rtw_hal_deinit(_adapter *padapter)
-+{
-+	uint	status = _SUCCESS;
-+
-+	status = padapter->hal_func.hal_deinit(padapter);
-+
-+	if (status == _SUCCESS) {
-+		rtw_led_control(padapter, LED_CTL_POWER_OFF);
-+		rtw_set_hw_init_completed(padapter, _FALSE);
-+	} else
-+		RTW_INFO("\n rtw_hal_deinit: hal_init fail\n");
-+
-+
-+	return status;
-+}
-+
-+u8 rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val)
-+{
-+	return padapter->hal_func.set_hw_reg_handler(padapter, variable, val);
-+}
-+
-+void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val)
-+{
-+	padapter->hal_func.GetHwRegHandler(padapter, variable, val);
-+}
-+
-+u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)
-+{
-+	return padapter->hal_func.SetHalDefVarHandler(padapter, eVariable, pValue);
-+}
-+u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue)
-+{
-+	return padapter->hal_func.get_hal_def_var_handler(padapter, eVariable, pValue);
-+}
-+
-+void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet)
-+{
-+	padapter->hal_func.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet);
-+}
-+void	rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2)
-+{
-+	padapter->hal_func.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2);
-+}
-+
-+/* FOR SDIO & PCIE */
-+void rtw_hal_enable_interrupt(_adapter *padapter)
-+{
-+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
-+	padapter->hal_func.enable_interrupt(padapter);
-+#endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
-+}
-+
-+/* FOR SDIO & PCIE */
-+void rtw_hal_disable_interrupt(_adapter *padapter)
-+{
-+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
-+	padapter->hal_func.disable_interrupt(padapter);
-+#endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
-+}
-+
-+
-+u8 rtw_hal_check_ips_status(_adapter *padapter)
-+{
-+	u8 val = _FALSE;
-+	if (padapter->hal_func.check_ips_status)
-+		val = padapter->hal_func.check_ips_status(padapter);
-+	else
-+		RTW_INFO("%s: hal_func.check_ips_status is NULL!\n", __FUNCTION__);
-+
-+	return val;
-+}
-+
-+s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan)
-+{
-+	s32 ret;
-+
-+	ret = padapter->hal_func.fw_dl(padapter, wowlan);
-+
-+#ifdef CONFIG_LPS_1T1R
-+	GET_HAL_DATA(padapter)->lps_1t1r = 0;
-+#endif
-+
-+	return ret;
-+}
-+
-+#ifdef RTW_HALMAC
-+s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem)
-+{
-+	systime dlfw_start_time = rtw_get_current_time();
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
-+	s32 rst = _FALSE;
-+
-+	rst = padapter->hal_func.fw_mem_dl(padapter, mem);
-+	RTW_INFO("%s in %dms\n", __func__, rtw_get_passing_time_ms(dlfw_start_time));
-+
-+	if (rst == _FALSE)
-+		pdbgpriv->dbg_fw_mem_dl_error_cnt++;
-+	if (1)
-+		RTW_INFO("%s dbg_fw_mem_dl_error_cnt:%d\n", __func__, pdbgpriv->dbg_fw_mem_dl_error_cnt);
-+	return rst;
-+}
-+#endif
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+void rtw_hal_clear_interrupt(_adapter *padapter)
-+{
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	padapter->hal_func.clear_interrupt(padapter);
-+#endif
-+}
-+#endif
-+
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
-+u32	rtw_hal_inirp_init(_adapter *padapter)
-+{
-+	if (is_primary_adapter(padapter))
-+		return padapter->hal_func.inirp_init(padapter);
-+	return _SUCCESS;
-+}
-+u32	rtw_hal_inirp_deinit(_adapter *padapter)
-+{
-+
-+	if (is_primary_adapter(padapter))
-+		return padapter->hal_func.inirp_deinit(padapter);
-+
-+	return _SUCCESS;
-+}
-+#endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
-+
-+#if defined(CONFIG_PCI_HCI)
-+void	rtw_hal_irp_reset(_adapter *padapter)
-+{
-+	padapter->hal_func.irp_reset(GET_PRIMARY_ADAPTER(padapter));
-+}
-+
-+void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data)
-+{
-+	u16 cmd[2];
-+
-+	cmd[0] = addr;
-+	cmd[1] = data;
-+
-+	padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_DBI, (u8 *) cmd);
-+}
-+
-+u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr)
-+{
-+	padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_DBI, (u8 *)(&addr));
-+
-+	return (u8)addr;
-+}
-+
-+void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data)
-+{
-+	u16 cmd[2];
-+
-+	cmd[0] = (u16)addr;
-+	cmd[1] = data;
-+
-+	padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_MDIO, (u8 *) cmd);
-+}
-+
-+u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr)
-+{
-+	padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_MDIO, &addr);
-+
-+	return (u8)addr;
-+}
-+
-+u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter)
-+{
-+	u8 l1off;
-+
-+	padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_NIC_SUPPORT, &l1off);
-+	return l1off;
-+}
-+
-+u8 rtw_hal_pci_l1off_capability(_adapter *padapter)
-+{
-+	u8 l1off;
-+
-+	padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_CAPABILITY, &l1off);
-+	return l1off;
-+}
-+
-+
-+#endif /* #if defined(CONFIG_PCI_HCI) */
-+
-+/* for USB Auto-suspend */
-+u8	rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)
-+{
-+	if (padapter->hal_func.interface_ps_func)
-+		return padapter->hal_func.interface_ps_func(padapter, efunc_id, val);
-+	return _FAIL;
-+}
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+s32	rtw_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
-+{
-+	return padapter->hal_func.hal_mgmt_xmitframe_enqueue(padapter, pxmitframe);
-+}
-+#endif
-+
-+s32	rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
-+{
-+	return padapter->hal_func.hal_xmitframe_enqueue(padapter, pxmitframe);
-+}
-+
-+s32	rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
-+{
-+	return padapter->hal_func.hal_xmit(padapter, pxmitframe);
-+}
-+
-+/*
-+ * [IMPORTANT] This function would be run in interrupt context.
-+ */
-+s32	rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
-+{
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	_irqL irqL;
-+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
-+#endif
-+	s32 ret = _FAIL;
-+
-+	update_mgntframe_attrib_addr(padapter, pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	update_mgntframe_subtype(padapter, pmgntframe);
-+#endif
-+
-+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
-+	if ((!MLME_IS_MESH(padapter) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE)
-+		#ifdef CONFIG_RTW_MESH
-+		|| (MLME_IS_MESH(padapter) && padapter->mesh_info.mesh_auth_id)
-+		#endif
-+	)
-+		rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
-+#endif
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
-+		_enter_critical_bh(&pxmitpriv->lock, &irqL);
-+		ret = mgmt_xmitframe_enqueue_for_sleeping_sta(padapter, pmgntframe);
-+		_exit_critical_bh(&pxmitpriv->lock, &irqL);
-+
-+		#ifdef DBG_MGMT_QUEUE
-+		if (ret == _TRUE)
-+			RTW_INFO("%s doesn't be queued, dattrib->ra:"MAC_FMT" seq_num = %u, subtype = 0x%x\n",
-+			__func__, MAC_ARG(pmgntframe->attrib.ra), pmgntframe->attrib.seqnum, pmgntframe->attrib.subtype);
-+		#endif
-+
-+		if (ret == RTW_QUEUE_MGMT)
-+			return ret;
-+	}
-+#endif
-+
-+	ret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe);
-+	return ret;
-+}
-+
-+s32	rtw_hal_init_xmit_priv(_adapter *padapter)
-+{
-+	return padapter->hal_func.init_xmit_priv(padapter);
-+}
-+void	rtw_hal_free_xmit_priv(_adapter *padapter)
-+{
-+	padapter->hal_func.free_xmit_priv(padapter);
-+}
-+
-+s32	rtw_hal_init_recv_priv(_adapter *padapter)
-+{
-+	return padapter->hal_func.init_recv_priv(padapter);
-+}
-+void	rtw_hal_free_recv_priv(_adapter *padapter)
-+{
-+	padapter->hal_func.free_recv_priv(padapter);
-+}
-+
-+void rtw_sta_ra_registed(_adapter *padapter, struct sta_info *psta)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
-+
-+	if (psta == NULL) {
-+		RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(padapter));
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+#ifdef CONFIG_AP_MODE
-+	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
-+		if (psta->cmn.aid > padapter->stapriv.max_aid) {
-+			RTW_ERR("station aid %d exceed the max number\n", psta->cmn.aid);
-+			rtw_warn_on(1);
-+			return;
-+		}
-+		rtw_ap_update_sta_ra_info(padapter, psta);
-+	}
-+#endif
-+
-+	psta->cmn.ra_info.ra_bw_mode = rtw_get_tx_bw_mode(padapter, psta);
-+	/*set correct initial date rate for each mac_id */
-+	hal_data->INIDATA_RATE[psta->cmn.mac_id] = psta->init_rate;
-+
-+	rtw_phydm_ra_registed(padapter, psta);
-+}
-+
-+void rtw_hal_update_ra_mask(struct sta_info *psta)
-+{
-+	_adapter *padapter;
-+
-+	if (!psta)
-+		return;
-+
-+	padapter = psta->padapter;
-+	rtw_sta_ra_registed(padapter, psta);
-+}
-+
-+/*	Start specifical interface thread		*/
-+void	rtw_hal_start_thread(_adapter *padapter)
-+{
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+#ifndef CONFIG_SDIO_TX_TASKLET
-+	padapter->hal_func.run_thread(padapter);
-+#endif
-+#endif
-+}
-+/*	Start specifical interface thread		*/
-+void	rtw_hal_stop_thread(_adapter *padapter)
-+{
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+#ifndef CONFIG_SDIO_TX_TASKLET
-+
-+	padapter->hal_func.cancel_thread(padapter);
-+
-+#endif
-+#endif
-+}
-+
-+u32	rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask)
-+{
-+	u32 data = 0;
-+	if (padapter->hal_func.read_bbreg)
-+		data = padapter->hal_func.read_bbreg(padapter, RegAddr, BitMask);
-+	return data;
-+}
-+void	rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
-+{
-+	if (padapter->hal_func.write_bbreg)
-+		padapter->hal_func.write_bbreg(padapter, RegAddr, BitMask, Data);
-+}
-+
-+u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask)
-+{
-+	u32 data = 0;
-+
-+	if (padapter->hal_func.read_rfreg) {
-+		data = padapter->hal_func.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
-+
-+		#ifdef DBG_IO
-+		if (match_rf_read_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
-+			RTW_INFO("DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n"
-+				, eRFPath, RegAddr, BitMask, (data << PHY_CalculateBitShift(BitMask)), data);
-+		}
-+		#endif
-+	}
-+
-+	return data;
-+}
-+
-+void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
-+{
-+	if (padapter->hal_func.write_rfreg) {
-+
-+		#ifdef DBG_IO
-+		if (match_rf_write_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) {
-+			RTW_INFO("DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n"
-+				, eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data);
-+		}
-+		#endif
-+
-+		padapter->hal_func.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
-+
-+#ifdef CONFIG_PCI_HCI
-+		if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/
-+			rtw_udelay_os(2);
-+#endif
-+	}
-+}
-+
-+#ifdef CONFIG_SYSON_INDIRECT_ACCESS
-+u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask)
-+{
-+	u32 data = 0;
-+	if (padapter->hal_func.read_syson_reg)
-+		data = padapter->hal_func.read_syson_reg(padapter, RegAddr, BitMask);
-+
-+	return data;
-+}
-+
-+void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
-+{
-+	if (padapter->hal_func.write_syson_reg)
-+		padapter->hal_func.write_syson_reg(padapter, RegAddr, BitMask, Data);
-+}
-+#endif
-+
-+#if defined(CONFIG_PCI_HCI)
-+s32	rtw_hal_interrupt_handler(_adapter *padapter)
-+{
-+	s32 ret = _FAIL;
-+	ret = padapter->hal_func.interrupt_handler(padapter);
-+	return ret;
-+}
-+
-+void	rtw_hal_unmap_beacon_icf(_adapter *padapter)
-+{
-+	padapter->hal_func.unmap_beacon_icf(padapter);
-+}
-+#endif
-+#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
-+void	rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf)
-+{
-+	padapter->hal_func.interrupt_handler(padapter, pkt_len, pbuf);
-+}
-+#endif
-+
-+void	rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	/*u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0;*/
-+	u8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0;
-+	u8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0;
-+	u8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0;
-+
-+	if (rtw_phydm_is_iqk_in_progress(padapter))
-+		RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__);
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	/* MP mode channel don't use secondary channel */
-+	if (rtw_mp_mode_check(padapter) == _FALSE)
-+#endif
-+	{
-+		#if 0
-+		if (cch_160 != 0)
-+			cch_80 = rtw_get_scch_by_cch_offset(cch_160, CHANNEL_WIDTH_160, Offset80);
-+		#endif
-+		if (cch_80 != 0)
-+			cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, Offset80);
-+		if (cch_40 != 0)
-+			cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, Offset40);
-+	}
-+
-+	pHalData->cch_80 = cch_80;
-+	pHalData->cch_40 = cch_40;
-+	pHalData->cch_20 = cch_20;
-+
-+	if (0)
-+		RTW_INFO("%s cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u)\n", __func__
-+			, channel, ch_width_str(Bandwidth), Offset40, Offset80
-+			, pHalData->cch_80, pHalData->cch_40, pHalData->cch_20);
-+
-+	padapter->hal_func.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80);
-+}
-+
-+void	rtw_hal_dm_watchdog(_adapter *padapter)
-+{
-+
-+	rtw_hal_turbo_edca(padapter);
-+	padapter->hal_func.hal_dm_watchdog(padapter);
-+}
-+
-+#ifdef CONFIG_LPS_LCLK_WD_TIMER
-+void	rtw_hal_dm_watchdog_in_lps(_adapter *padapter)
-+{
-+#if defined(CONFIG_CONCURRENT_MODE)
-+#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
-+	if (padapter->hw_port != HW_PORT0)
-+		return;
-+#endif
-+#endif
-+
-+	if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)
-+		rtw_phydm_watchdog_in_lps_lclk(padapter);/* this function caller is in interrupt context */
-+}
-+#endif /*CONFIG_LPS_LCLK_WD_TIMER*/
-+
-+void rtw_hal_bcn_related_reg_setting(_adapter *padapter)
-+{
-+	padapter->hal_func.SetBeaconRelatedRegistersHandler(padapter);
-+}
-+
-+#ifdef CONFIG_HOSTAPD_MLME
-+s32	rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
-+{
-+	if (padapter->hal_func.hostap_mgnt_xmit_entry)
-+		return padapter->hal_func.hostap_mgnt_xmit_entry(padapter, pkt);
-+	return _FAIL;
-+}
-+#endif /* CONFIG_HOSTAPD_MLME */
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+void	rtw_hal_sreset_init(_adapter *padapter)
-+{
-+	padapter->hal_func.sreset_init_value(padapter);
-+}
-+void rtw_hal_sreset_reset(_adapter *padapter)
-+{
-+	padapter = GET_PRIMARY_ADAPTER(padapter);
-+	padapter->hal_func.silentreset(padapter);
-+}
-+
-+void rtw_hal_sreset_reset_value(_adapter *padapter)
-+{
-+	padapter->hal_func.sreset_reset_value(padapter);
-+}
-+
-+void rtw_hal_sreset_xmit_status_check(_adapter *padapter)
-+{
-+	padapter->hal_func.sreset_xmit_status_check(padapter);
-+}
-+void rtw_hal_sreset_linked_status_check(_adapter *padapter)
-+{
-+	padapter->hal_func.sreset_linked_status_check(padapter);
-+}
-+u8   rtw_hal_sreset_get_wifi_status(_adapter *padapter)
-+{
-+	return padapter->hal_func.sreset_get_wifi_status(padapter);
-+}
-+
-+bool rtw_hal_sreset_inprogress(_adapter *padapter)
-+{
-+	padapter = GET_PRIMARY_ADAPTER(padapter);
-+	return padapter->hal_func.sreset_inprogress(padapter);
-+}
-+#endif /* DBG_CONFIG_ERROR_DETECT */
-+
-+#ifdef CONFIG_IOL
-+int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_waiting_ms, u32 bndy_cnt)
-+{
-+	if (adapter->hal_func.IOL_exec_cmds_sync)
-+		return adapter->hal_func.IOL_exec_cmds_sync(adapter, xmit_frame, max_waiting_ms, bndy_cnt);
-+	return _FAIL;
-+}
-+#endif
-+
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+s32 rtw_hal_xmit_thread_handler(_adapter *padapter)
-+{
-+	return padapter->hal_func.xmit_thread_handler(padapter);
-+}
-+#endif
-+
-+#ifdef CONFIG_RECV_THREAD_MODE
-+s32 rtw_hal_recv_hdl(_adapter *adapter)
-+{
-+	return adapter->hal_func.recv_hdl(adapter);
-+}
-+#endif
-+
-+void rtw_hal_notch_filter(_adapter *adapter, bool enable)
-+{
-+	if (adapter->hal_func.hal_notch_filter)
-+		adapter->hal_func.hal_notch_filter(adapter, enable);
-+}
-+
-+#ifdef CONFIG_FW_C2H_REG
-+inline bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf)
-+{
-+	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
-+	bool ret = _FAIL;
-+
-+	ret = C2H_ID_88XX(buf) || C2H_PLEN_88XX(buf);
-+
-+	return ret;
-+}
-+
-+inline s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf)
-+{
-+	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
-+	s32 ret = _FAIL;
-+
-+	ret = c2h_evt_read_88xx(adapter, buf);
-+
-+	return ret;
-+}
-+
-+bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload)
-+{
-+	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
-+	bool ret = _FAIL;
-+
-+	*id = C2H_ID_88XX(buf);
-+	*seq = C2H_SEQ_88XX(buf);
-+	*plen = C2H_PLEN_88XX(buf);
-+	*payload = C2H_PAYLOAD_88XX(buf);
-+	ret = _SUCCESS;
-+
-+	return ret;
-+}
-+#endif /* CONFIG_FW_C2H_REG */
-+
-+#ifdef CONFIG_FW_C2H_PKT
-+bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload)
-+{
-+	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
-+	bool ret = _FAIL;
-+
-+	if (!buf || len > 256 || len < 3)
-+		goto exit;
-+
-+	*id = C2H_ID_88XX(buf);
-+	*seq = C2H_SEQ_88XX(buf);
-+	*plen = len - 2;
-+	*payload = C2H_PAYLOAD_88XX(buf);
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_FW_C2H_PKT */
-+
-+#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
-+#include <rtw_bt_mp.h> /* for MPTBT_FwC2hBtMpCtrl */
-+#endif
-+s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
-+{
-+	u8 sub_id = 0;
-+	s32 ret = _SUCCESS;
-+
-+	switch (id) {
-+	case C2H_FW_SCAN_COMPLETE:
-+		RTW_INFO("[C2H], FW Scan Complete\n");
-+		break;
-+
-+#ifdef CONFIG_BT_COEXIST
-+	case C2H_BT_INFO:
-+		rtw_btcoex_BtInfoNotify(adapter, plen, payload);
-+		break;
-+	case C2H_BT_MP_INFO:
-+		#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
-+		MPTBT_FwC2hBtMpCtrl(adapter, payload, plen);
-+		#endif
-+		rtw_btcoex_BtMpRptNotify(adapter, plen, payload);
-+		break;
-+	case C2H_MAILBOX_STATUS:
-+		RTW_DBG_DUMP("C2H_MAILBOX_STATUS: ", payload, plen);
-+		break;
-+	case C2H_WLAN_INFO:
-+		rtw_btcoex_WlFwDbgInfoNotify(adapter, payload, plen);
-+		break;
-+#endif /* CONFIG_BT_COEXIST */
-+
-+	case C2H_IQK_FINISH:
-+		c2h_iqk_offload(adapter, payload, plen);
-+		break;
-+
-+#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
-+	case C2H_FW_CHNL_SWITCH_COMPLETE:
-+#ifndef CONFIG_TDLS_CH_SW_V2
-+		rtw_tdls_chsw_oper_done(adapter);
-+#endif
-+		break;
-+#endif
-+
-+	case C2H_BCN_EARLY_RPT:
-+		rtw_hal_bcn_early_rpt_c2h_handler(adapter);
-+		break;
-+
-+#ifdef CONFIG_MCC_MODE
-+	case C2H_MCC:
-+		rtw_hal_mcc_c2h_handler(adapter, plen, payload);
-+		break;
-+#endif
-+
-+#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
-+	case C2H_MAC_HIDDEN_RPT:
-+		c2h_mac_hidden_rpt_hdl(adapter, payload, plen);
-+		break;
-+	case C2H_MAC_HIDDEN_RPT_2:
-+		c2h_mac_hidden_rpt_2_hdl(adapter, payload, plen);
-+		break;
-+#endif
-+
-+	case C2H_DEFEATURE_DBG:
-+		c2h_defeature_dbg_hdl(adapter, payload, plen);
-+		break;
-+
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+	case C2H_CUSTOMER_STR_RPT:
-+		c2h_customer_str_rpt_hdl(adapter, payload, plen);
-+		break;
-+	case C2H_CUSTOMER_STR_RPT_2:
-+		c2h_customer_str_rpt_2_hdl(adapter, payload, plen);
-+		break;
-+#endif
-+#ifdef RTW_PER_CMD_SUPPORT_FW
-+	case C2H_PER_RATE_RPT:
-+		c2h_per_rate_rpt_hdl(adapter, payload, plen);
-+		break;
-+#endif
-+#ifdef CONFIG_LPS_ACK
-+	case C2H_LPS_STATUS_RPT:
-+		c2h_lps_status_rpt(adapter, payload, plen);
-+		break;
-+#endif	
-+#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
-+	case C2H_SET_TXPWR_FINISH:
-+		c2h_txpwr_idx_offload_done(adapter, payload, plen);
-+		break;
-+#endif
-+	case C2H_EXTEND:
-+		sub_id = payload[0];
-+		/* no handle, goto default */
-+		fallthrough;
-+
-+	default:
-+		if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE)
-+			ret = _FAIL;
-+		break;
-+	}
-+
-+	if (ret != _SUCCESS) {
-+		if (id == C2H_EXTEND)
-+			RTW_WARN("%s: unknown C2H(0x%02x, 0x%02x)\n", __func__, id, sub_id);
-+		else
-+			RTW_WARN("%s: unknown C2H(0x%02x)\n", __func__, id);
-+	}
-+
-+	return ret;
-+}
-+
-+#ifndef RTW_HALMAC
-+s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
-+{
-+	s32 ret = _FAIL;
-+
-+	ret = adapter->hal_func.c2h_handler(adapter, id, seq, plen, payload);
-+	if (ret != _SUCCESS)
-+		ret = c2h_handler(adapter, id, seq, plen, payload);
-+
-+	return ret;
-+}
-+
-+s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
-+{
-+	switch (id) {
-+	case C2H_CCX_TX_RPT:
-+	case C2H_BT_MP_INFO:
-+	case C2H_FW_CHNL_SWITCH_COMPLETE:
-+	case C2H_IQK_FINISH:
-+	case C2H_MCC:
-+	case C2H_BCN_EARLY_RPT:
-+	case C2H_AP_REQ_TXRPT:
-+	case C2H_SPC_STAT:
-+	case C2H_SET_TXPWR_FINISH:
-+		return _TRUE;
-+	default:
-+		return _FALSE;
-+	}
-+}
-+#endif /* !RTW_HALMAC */
-+
-+s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)
-+{
-+	return GET_HAL_DATA(padapter)->bDisableSWChannelPlan;
-+}
-+
-+#ifdef CONFIG_PROTSEL_MACSLEEP
-+static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
-+{
-+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
-+	u16 reg_sleep_info = macid_ctl->reg_sleep_info;
-+	u16 reg_sleep_ctrl = macid_ctl->reg_sleep_ctrl;
-+	const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
-+	u8 bit_shift;
-+	u32 val32;
-+	s32 ret = _FAIL;
-+
-+	if (macid >= macid_ctl->num) {
-+		RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
-+			, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid);
-+		goto exit;
-+	}
-+
-+	if (macid < 32) {
-+		bit_shift = macid;
-+	#if (MACID_NUM_SW_LIMIT > 32)
-+	} else if (macid < 64) {
-+		bit_shift = macid - 32;
-+	#endif
-+	#if (MACID_NUM_SW_LIMIT > 64)
-+	} else if (macid < 96) {
-+		bit_shift = macid - 64;
-+	#endif
-+	#if (MACID_NUM_SW_LIMIT > 96)
-+	} else if (macid < 128) {
-+		bit_shift = macid - 96;
-+	#endif
-+	} else {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (!reg_sleep_ctrl || !reg_sleep_info) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	val32 = rtw_read32(adapter, reg_sleep_ctrl);
-+	val32 = (val32 &~sel_mask_sel) | ((macid / 32) & sel_mask_sel);
-+	rtw_write32(adapter, reg_sleep_ctrl, val32);
-+
-+	val32 = rtw_read32(adapter, reg_sleep_info);
-+	RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
-+		, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
-+		, macid, reg_sleep_info, val32);
-+
-+	ret = _SUCCESS;
-+
-+	if (sleep) {
-+		if (val32 & BIT(bit_shift))
-+			goto exit;
-+		val32 |= BIT(bit_shift);
-+	} else {
-+		if (!(val32 & BIT(bit_shift)))
-+			goto exit;
-+		val32 &= ~BIT(bit_shift);
-+	}
-+
-+	rtw_write32(adapter, reg_sleep_info, val32);
-+
-+exit:
-+	return ret;
-+}
-+#else
-+static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
-+{
-+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
-+	u16 reg_sleep;
-+	u8 bit_shift;
-+	u32 val32;
-+	s32 ret = _FAIL;
-+
-+	if (macid >= macid_ctl->num) {
-+		RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
-+			, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid);
-+		goto exit;
-+	}
-+
-+	if (macid < 32) {
-+		reg_sleep = macid_ctl->reg_sleep_m0;
-+		bit_shift = macid;
-+	#if (MACID_NUM_SW_LIMIT > 32)
-+	} else if (macid < 64) {
-+		reg_sleep = macid_ctl->reg_sleep_m1;
-+		bit_shift = macid - 32;
-+	#endif
-+	#if (MACID_NUM_SW_LIMIT > 64)
-+	} else if (macid < 96) {
-+		reg_sleep = macid_ctl->reg_sleep_m2;
-+		bit_shift = macid - 64;
-+	#endif
-+	#if (MACID_NUM_SW_LIMIT > 96)
-+	} else if (macid < 128) {
-+		reg_sleep = macid_ctl->reg_sleep_m3;
-+		bit_shift = macid - 96;
-+	#endif
-+	} else {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (!reg_sleep) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	val32 = rtw_read32(adapter, reg_sleep);
-+	RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
-+		, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
-+		, macid, reg_sleep, val32);
-+
-+	ret = _SUCCESS;
-+
-+	if (sleep) {
-+		if (val32 & BIT(bit_shift))
-+			goto exit;
-+		val32 |= BIT(bit_shift);
-+	} else {
-+		if (!(val32 & BIT(bit_shift)))
-+			goto exit;
-+		val32 &= ~BIT(bit_shift);
-+	}
-+
-+	rtw_write32(adapter, reg_sleep, val32);
-+
-+exit:
-+	return ret;
-+}
-+#endif
-+
-+inline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid)
-+{
-+	return _rtw_hal_macid_sleep(adapter, macid, 1);
-+}
-+
-+inline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid)
-+{
-+	return _rtw_hal_macid_sleep(adapter, macid, 0);
-+}
-+
-+#ifdef CONFIG_PROTSEL_MACSLEEP
-+static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)
-+{
-+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
-+	u16 reg_sleep_info = macid_ctl->reg_sleep_info;
-+	u16 reg_sleep_ctrl = macid_ctl->reg_sleep_ctrl;
-+	const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
-+	u32 m;
-+	u8 mid = 0;
-+	u32 val32;
-+
-+	do {
-+		if (mid == 0) {
-+			m = bmp->m0;
-+		#if (MACID_NUM_SW_LIMIT > 32)
-+		} else if (mid == 1) {
-+			m = bmp->m1;
-+		#endif
-+		#if (MACID_NUM_SW_LIMIT > 64)
-+		} else if (mid == 2) {
-+			m = bmp->m2;
-+		#endif
-+		#if (MACID_NUM_SW_LIMIT > 96)
-+		} else if (mid == 3) {
-+			m = bmp->m3;
-+		#endif
-+		} else {
-+			rtw_warn_on(1);
-+			break;
-+		}
-+
-+		if (m == 0)
-+			goto move_next;
-+
-+		if (!reg_sleep_ctrl || !reg_sleep_info) {
-+			rtw_warn_on(1);
-+			break;
-+		}
-+
-+		val32 = rtw_read32(adapter, reg_sleep_ctrl);
-+		val32 = (val32 &~sel_mask_sel) | (mid & sel_mask_sel);
-+		rtw_write32(adapter, reg_sleep_ctrl, val32);
-+
-+		val32 = rtw_read32(adapter, reg_sleep_info);
-+		RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n"
-+			, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
-+			, mid, m, reg_sleep_info, val32);
-+
-+		if (sleep) {
-+			if ((val32 & m) == m)
-+				goto move_next;
-+			val32 |= m;
-+		} else {
-+			if ((val32 & m) == 0)
-+				goto move_next;
-+			val32 &= ~m;
-+		}
-+
-+		rtw_write32(adapter, reg_sleep_info, val32);
-+
-+move_next:
-+		mid++;
-+	} while (mid * 32 < MACID_NUM_SW_LIMIT);
-+
-+	return _SUCCESS;
-+}
-+#else
-+static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)
-+{
-+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
-+	u16 reg_sleep;
-+	u32 m;
-+	u8 mid = 0;
-+	u32 val32;
-+
-+	do {
-+		if (mid == 0) {
-+			m = bmp->m0;
-+			reg_sleep = macid_ctl->reg_sleep_m0;
-+		#if (MACID_NUM_SW_LIMIT > 32)
-+		} else if (mid == 1) {
-+			m = bmp->m1;
-+			reg_sleep = macid_ctl->reg_sleep_m1;
-+		#endif
-+		#if (MACID_NUM_SW_LIMIT > 64)
-+		} else if (mid == 2) {
-+			m = bmp->m2;
-+			reg_sleep = macid_ctl->reg_sleep_m2;
-+		#endif
-+		#if (MACID_NUM_SW_LIMIT > 96)
-+		} else if (mid == 3) {
-+			m = bmp->m3;
-+			reg_sleep = macid_ctl->reg_sleep_m3;
-+		#endif
-+		} else {
-+			rtw_warn_on(1);
-+			break;
-+		}
-+
-+		if (m == 0)
-+			goto move_next;
-+
-+		if (!reg_sleep) {
-+			rtw_warn_on(1);
-+			break;
-+		}
-+
-+		val32 = rtw_read32(adapter, reg_sleep);
-+		RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n"
-+			, ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
-+			, mid, m, reg_sleep, val32);
-+
-+		if (sleep) {
-+			if ((val32 & m) == m)
-+				goto move_next;
-+			val32 |= m;
-+		} else {
-+			if ((val32 & m) == 0)
-+				goto move_next;
-+			val32 &= ~m;
-+		}
-+
-+		rtw_write32(adapter, reg_sleep, val32);
-+
-+move_next:
-+		mid++;
-+	} while (mid * 32 < MACID_NUM_SW_LIMIT);
-+
-+	return _SUCCESS;
-+}
-+#endif
-+
-+inline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter)
-+{
-+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
-+
-+	return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 1);
-+}
-+
-+inline s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter)
-+{
-+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
-+
-+	return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 0);
-+}
-+
-+static s32 _rtw_hal_macid_drop(_adapter *adapter, u8 macid, u8 drop)
-+{
-+	struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
-+#ifndef CONFIG_PROTSEL_MACSLEEP
-+	u16 reg_drop = 0;
-+#else
-+	u16 reg_drop_info = macid_ctl->reg_drop_info;
-+	u16 reg_drop_ctrl = macid_ctl->reg_drop_ctrl;
-+	const u32 sel_mask_sel = BIT(0) | BIT(1) | BIT(2);
-+#endif /* CONFIG_PROTSEL_MACSLEEP */
-+	u8 bit_shift;
-+	u32 val32;
-+	s32 ret = _FAIL;
-+/* some IC doesn't have this register */
-+#ifndef REG_PKT_BUFF_ACCESS_CTRL
-+#define REG_PKT_BUFF_ACCESS_CTRL 0
-+#endif
-+
-+	if (macid >= macid_ctl->num) {
-+		RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
-+			, ADPT_ARG(adapter), drop ? "drop" : "undrop" , macid);
-+		goto exit;
-+	}
-+	
-+	if(_rtw_macid_ctl_chk_cap(adapter, MACID_DROP)) {
-+		if (macid < 32) {
-+#ifndef CONFIG_PROTSEL_MACSLEEP
-+			reg_drop = macid_ctl->reg_drop_m0;
-+#endif /* CONFIG_PROTSEL_MACSLEEP */
-+			bit_shift = macid;
-+		#if (MACID_NUM_SW_LIMIT > 32)
-+		} else if (macid < 64) {
-+#ifndef CONFIG_PROTSEL_MACSLEEP
-+			reg_drop = macid_ctl->reg_drop_m1;
-+#endif /* CONFIG_PROTSEL_MACSLEEP */
-+			bit_shift = macid - 32;
-+		#endif
-+		#if (MACID_NUM_SW_LIMIT > 64)
-+		} else if (macid < 96) {
-+#ifndef CONFIG_PROTSEL_MACSLEEP
-+			reg_drop = macid_ctl->reg_drop_m2;
-+#endif /* CONFIG_PROTSEL_MACSLEEP */
-+			bit_shift = macid - 64;
-+		#endif
-+		#if (MACID_NUM_SW_LIMIT > 96)
-+		} else if (macid < 128) {
-+#ifndef CONFIG_PROTSEL_MACSLEEP
-+			reg_drop = macid_ctl->reg_drop_m3;
-+#endif /* CONFIG_PROTSEL_MACSLEEP */
-+			bit_shift = macid - 96;
-+		#endif
-+		} else {
-+			rtw_warn_on(1);
-+			goto exit;
-+		}
-+
-+#ifndef CONFIG_PROTSEL_MACSLEEP
-+		if (!reg_drop) {
-+			rtw_warn_on(1);
-+			goto exit;
-+		}
-+		val32 = rtw_read32(adapter, reg_drop);
-+		/*RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x \n"
-+			, ADPT_ARG(adapter), drop ? "drop" : "undrop"
-+			, macid, reg_drop, val32);*/
-+#else
-+		if (!reg_drop_ctrl || !reg_drop_info) {
-+			rtw_warn_on(1);
-+			goto exit;
-+		}
-+
-+		val32 = rtw_read32(adapter, reg_drop_ctrl);
-+		val32 = (val32 &~sel_mask_sel) | ((macid / 32) & sel_mask_sel);
-+		rtw_write32(adapter, reg_drop_ctrl, val32);
-+
-+		val32 = rtw_read32(adapter, reg_drop_info);
-+		/*RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
-+			, ADPT_ARG(adapter), drop ? "drop" : "undrop"
-+			, macid, reg_drop_info, val32);*/
-+#endif /* CONFIG_PROTSEL_MACSLEEP */
-+		ret = _SUCCESS;
-+
-+		if (drop) {
-+			if (val32 & BIT(bit_shift))
-+				goto exit;
-+			val32 |= BIT(bit_shift);
-+		} else {
-+			if (!(val32 & BIT(bit_shift)))
-+				goto exit;
-+			val32 &= ~BIT(bit_shift);
-+		}
-+
-+#ifndef CONFIG_PROTSEL_MACSLEEP
-+		rtw_write32(adapter, reg_drop, val32);
-+		RTW_INFO(ADPT_FMT" %s macid=%d, done reg_0x%03x=0x%08x\n"
-+			, ADPT_ARG(adapter), drop ? "drop" : "undrop"
-+			, macid, reg_drop, val32);
-+#else
-+		rtw_write32(adapter, reg_drop_info, val32);
-+		RTW_INFO(ADPT_FMT" %s macid=%d, done reg_0x%03x=0x%08x\n"
-+			, ADPT_ARG(adapter), drop ? "drop" : "undrop"
-+			, macid, reg_drop_info, val32);
-+#endif /* CONFIG_PROTSEL_MACSLEEP */
-+		
-+		
-+	} else if(_rtw_macid_ctl_chk_cap(adapter, MACID_DROP_INDIRECT)) {
-+		u16 start_addr = macid_ctl->macid_txrpt/8;
-+		u32 txrpt_h4b = 0;
-+		u8 i;
-+		
-+		/* each address means 1 byte */
-+		start_addr += macid*(macid_ctl->macid_txrpt_pgsz/8);
-+		/* select tx report buffer */
-+		rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXREPORT_BUF_SELECT);
-+		/* set tx report buffer start address for reading */
-+		rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, start_addr);
-+		txrpt_h4b = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
-+		/* OFFSET5 BIT2 is BIT10 of high 4 bytes */
-+		if (drop) {
-+			if (txrpt_h4b & BIT(10))
-+				goto exit;
-+			txrpt_h4b |= BIT(10);
-+		} else {
-+			if (!(txrpt_h4b & BIT(10)))
-+				goto exit;
-+			txrpt_h4b &= ~BIT(10);
-+		}
-+		/* set to macid drop field */
-+		rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, txrpt_h4b);
-+		/* 0x20800000 only write BIT10 of tx report buf */
-+		rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, 0x20800000 | start_addr);
-+#if 0 /* some ICs doesn't clear the write done bit */
-+		/* checking TX queue status */
-+		for (i = 0 ; i < 50 ; i++) {
-+			txrpt_h4b = rtw_read32(adapter, REG_PKTBUF_DBG_CTRL);
-+			if (txrpt_h4b & BIT(23)) {
-+				RTW_INFO("%s: wait to write TX RTP buf (%d)!\n", __func__, i);
-+				rtw_mdelay_os(10);
-+			} else {
-+				RTW_INFO("%s: wait to write TX RTP buf done (%d)!\n", __func__, i);
-+				break;
-+			}
-+		}
-+#endif
-+		rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, start_addr);
-+		RTW_INFO("start_addr=%x, data_H:%08x, data_L:%08x, macid=%d, txrpt_h4b=%x\n", start_addr
-+		,rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H), rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L), macid, txrpt_h4b);
-+	} else {
-+		RTW_INFO("There is no definition for camctl cap , please correct it\n");
-+	}
-+exit:
-+	return ret;
-+}
-+
-+inline s32 rtw_hal_macid_drop(_adapter *adapter, u8 macid)
-+{
-+	return _rtw_hal_macid_drop(adapter, macid, 1);
-+}
-+
-+inline s32 rtw_hal_macid_undrop(_adapter *adapter, u8 macid)
-+{
-+	return _rtw_hal_macid_drop(adapter, macid, 0);
-+}
-+
-+s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
-+{
-+	_adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter);
-+
-+	if (GET_HAL_DATA(pri_adapter)->bFWReady == _TRUE)
-+		return padapter->hal_func.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer);
-+	else if (padapter->registrypriv.mp_mode == 0)
-+		RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n"
-+			  , FUNC_ADPT_ARG(padapter), ElementID);
-+	return _FAIL;
-+}
-+
-+void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,
-+			      u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame)
-+{
-+	padapter->hal_func.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame);
-+
-+}
-+
-+u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan)
-+{
-+	u8 num = 0;
-+
-+
-+	if (adapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
-+		num = adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan);
-+	} else {
-+#ifdef RTW_HALMAC
-+		num = GET_HAL_DATA(adapter)->drv_rsvd_page_number;
-+#endif /* RTW_HALMAC */
-+	}
-+
-+	return num;
-+}
-+
-+#ifdef CONFIG_GPIO_API
-+void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag)
-+{
-+	if (padapter->hal_func.update_hisr_hsisr_ind)
-+		padapter->hal_func.update_hisr_hsisr_ind(padapter, flag);
-+}
-+
-+int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num)
-+{
-+	int ret = _SUCCESS;
-+
-+	if (padapter->hal_func.hal_gpio_func_check)
-+		ret = padapter->hal_func.hal_gpio_func_check(padapter, gpio_num);
-+
-+	return ret;
-+}
-+
-+void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num)
-+{
-+	if (padapter->hal_func.hal_gpio_multi_func_reset)
-+		padapter->hal_func.hal_gpio_multi_func_reset(padapter, gpio_num);
-+}
-+#endif
-+
-+#ifdef CONFIG_FW_CORRECT_BCN
-+void rtw_hal_fw_correct_bcn(_adapter *padapter)
-+{
-+	if (padapter->hal_func.fw_correct_bcn)
-+		padapter->hal_func.fw_correct_bcn(padapter);
-+}
-+#endif
-+
-+void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+	if (phy_chk_ch_setting_consistency(adapter, channel) != _SUCCESS)
-+		return;
-+
-+	hal_data->set_entire_txpwr = 1;
-+
-+	adapter->hal_func.set_tx_power_level_handler(adapter, channel);
-+	rtw_hal_set_txpwr_done(adapter);
-+
-+	hal_data->set_entire_txpwr = 0;
-+}
-+
-+void rtw_hal_update_txpwr_level(_adapter *adapter)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+
-+	rtw_hal_set_tx_power_level(adapter, hal_data->current_channel);
-+	rtw_rfctl_update_op_mode(adapter_to_rfctl(adapter), 0, 0);
-+}
-+
-+void rtw_hal_set_txpwr_done(_adapter *adapter)
-+{
-+	if (adapter->hal_func.set_txpwr_done)
-+		adapter->hal_func.set_txpwr_done(adapter);
-+}
-+
-+void rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex
-+	, enum rf_path rfpath, u8 rate)
-+{
-+	adapter->hal_func.set_tx_power_index_handler(adapter, powerindex, rfpath, rate);
-+}
-+
-+u8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath
-+	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
-+	, struct txpwr_idx_comp *tic)
-+{
-+	return adapter->hal_func.get_tx_power_index_handler(adapter, rfpath
-+		, rs, rate, bw, band, cch, opch, tic);
-+}
-+
-+s8 rtw_hal_get_txpwr_target_extra_bias(_adapter *adapter, enum rf_path rfpath
-+	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch)
-+{
-+	s8 val = 0;
-+
-+	if (adapter->hal_func.get_txpwr_target_extra_bias) {
-+		val = adapter->hal_func.get_txpwr_target_extra_bias(adapter
-+				, rfpath, rs, rate, bw, band, cch);
-+	}
-+
-+	return val;
-+}
-+
-+#ifdef RTW_HALMAC
-+/*
-+ * Description:
-+ *	Initialize MAC registers
-+ *
-+ * Return:
-+ *	_TRUE	success
-+ *	_FALSE	fail
-+ */
-+u8 rtw_hal_init_mac_register(PADAPTER adapter)
-+{
-+	return adapter->hal_func.init_mac_register(adapter);
-+}
-+
-+/*
-+ * Description:
-+ *	Initialize PHY(BB/RF) related functions
-+ *
-+ * Return:
-+ *	_TRUE	success
-+ *	_FALSE	fail
-+ */
-+u8 rtw_hal_init_phy(PADAPTER adapter)
-+{
-+	return adapter->hal_func.init_phy(adapter);
-+}
-+#endif /* RTW_HALMAC */
-+
-+#ifdef CONFIG_RFKILL_POLL
-+bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid)
-+{
-+	bool ret;
-+
-+	if (adapter->hal_func.hal_radio_onoff_check)
-+		ret = adapter->hal_func.hal_radio_onoff_check(adapter, valid);
-+	else {
-+		*valid = 0;
-+		ret = _FALSE;
-+	}
-+	return ret;
-+}
-+#endif
-+
-+#define rtw_hal_error_msg(ops_fun)		\
-+	RTW_PRINT("### %s - Error : Please hook hal_func.%s ###\n", __FUNCTION__, ops_fun)
-+
-+u8 rtw_hal_ops_check(_adapter *padapter)
-+{
-+	u8 ret = _SUCCESS;
-+#if 1
-+	/*** initialize section ***/
-+	if (NULL == padapter->hal_func.read_chip_version) {
-+		rtw_hal_error_msg("read_chip_version");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.init_default_value) {
-+		rtw_hal_error_msg("init_default_value");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.intf_chip_configure) {
-+		rtw_hal_error_msg("intf_chip_configure");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.read_adapter_info) {
-+		rtw_hal_error_msg("read_adapter_info");
-+		ret = _FAIL;
-+	}
-+
-+	if (NULL == padapter->hal_func.hal_power_on) {
-+		rtw_hal_error_msg("hal_power_on");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.hal_power_off) {
-+		rtw_hal_error_msg("hal_power_off");
-+		ret = _FAIL;
-+	}
-+
-+	if (NULL == padapter->hal_func.hal_init) {
-+		rtw_hal_error_msg("hal_init");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.hal_deinit) {
-+		rtw_hal_error_msg("hal_deinit");
-+		ret = _FAIL;
-+	}
-+
-+	/*** xmit section ***/
-+	if (NULL == padapter->hal_func.init_xmit_priv) {
-+		rtw_hal_error_msg("init_xmit_priv");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.free_xmit_priv) {
-+		rtw_hal_error_msg("free_xmit_priv");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.hal_xmit) {
-+		rtw_hal_error_msg("hal_xmit");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.mgnt_xmit) {
-+		rtw_hal_error_msg("mgnt_xmit");
-+		ret = _FAIL;
-+	}
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+	if (NULL == padapter->hal_func.xmit_thread_handler) {
-+		rtw_hal_error_msg("xmit_thread_handler");
-+		ret = _FAIL;
-+	}
-+#endif
-+	if (NULL == padapter->hal_func.hal_xmitframe_enqueue) {
-+		rtw_hal_error_msg("hal_xmitframe_enqueue");
-+		ret = _FAIL;
-+	}
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+#ifndef CONFIG_SDIO_TX_TASKLET
-+	if (NULL == padapter->hal_func.run_thread) {
-+		rtw_hal_error_msg("run_thread");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.cancel_thread) {
-+		rtw_hal_error_msg("cancel_thread");
-+		ret = _FAIL;
-+	}
-+#endif
-+#endif
-+
-+	/*** recv section ***/
-+	if (NULL == padapter->hal_func.init_recv_priv) {
-+		rtw_hal_error_msg("init_recv_priv");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.free_recv_priv) {
-+		rtw_hal_error_msg("free_recv_priv");
-+		ret = _FAIL;
-+	}
-+#ifdef CONFIG_RECV_THREAD_MODE
-+	if (NULL == padapter->hal_func.recv_hdl) {
-+		rtw_hal_error_msg("recv_hdl");
-+		ret = _FAIL;
-+	}
-+#endif
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
-+	if (NULL == padapter->hal_func.inirp_init) {
-+		rtw_hal_error_msg("inirp_init");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.inirp_deinit) {
-+		rtw_hal_error_msg("inirp_deinit");
-+		ret = _FAIL;
-+	}
-+#endif /* #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) */
-+
-+
-+	/*** interrupt hdl section ***/
-+#if defined(CONFIG_PCI_HCI)
-+	if (NULL == padapter->hal_func.irp_reset) {
-+		rtw_hal_error_msg("irp_reset");
-+		ret = _FAIL;
-+	}
-+#endif/*#if defined(CONFIG_PCI_HCI)*/
-+#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))
-+	if (NULL == padapter->hal_func.interrupt_handler) {
-+		rtw_hal_error_msg("interrupt_handler");
-+		ret = _FAIL;
-+	}
-+#endif /*#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))*/
-+
-+#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
-+	if (NULL == padapter->hal_func.enable_interrupt) {
-+		rtw_hal_error_msg("enable_interrupt");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.disable_interrupt) {
-+		rtw_hal_error_msg("disable_interrupt");
-+		ret = _FAIL;
-+	}
-+#endif /* defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
-+
-+
-+	/*** DM section ***/
-+	if (NULL == padapter->hal_func.dm_init) {
-+		rtw_hal_error_msg("dm_init");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.dm_deinit) {
-+		rtw_hal_error_msg("dm_deinit");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.hal_dm_watchdog) {
-+		rtw_hal_error_msg("hal_dm_watchdog");
-+		ret = _FAIL;
-+	}
-+
-+	/*** xxx section ***/
-+	if (NULL == padapter->hal_func.set_chnl_bw_handler) {
-+		rtw_hal_error_msg("set_chnl_bw_handler");
-+		ret = _FAIL;
-+	}
-+
-+	if (NULL == padapter->hal_func.set_hw_reg_handler) {
-+		rtw_hal_error_msg("set_hw_reg_handler");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.GetHwRegHandler) {
-+		rtw_hal_error_msg("GetHwRegHandler");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.get_hal_def_var_handler) {
-+		rtw_hal_error_msg("get_hal_def_var_handler");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.SetHalDefVarHandler) {
-+		rtw_hal_error_msg("SetHalDefVarHandler");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.GetHalODMVarHandler) {
-+		rtw_hal_error_msg("GetHalODMVarHandler");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.SetHalODMVarHandler) {
-+		rtw_hal_error_msg("SetHalODMVarHandler");
-+		ret = _FAIL;
-+	}
-+
-+	if (NULL == padapter->hal_func.SetBeaconRelatedRegistersHandler) {
-+		rtw_hal_error_msg("SetBeaconRelatedRegistersHandler");
-+		ret = _FAIL;
-+	}
-+
-+	if (NULL == padapter->hal_func.fill_h2c_cmd) {
-+		rtw_hal_error_msg("fill_h2c_cmd");
-+		ret = _FAIL;
-+	}
-+
-+#ifdef RTW_HALMAC
-+	if (NULL == padapter->hal_func.hal_mac_c2h_handler) {
-+		rtw_hal_error_msg("hal_mac_c2h_handler");
-+		ret = _FAIL;
-+	}
-+#elif !defined(CONFIG_RTL8188E)
-+	if (NULL == padapter->hal_func.c2h_handler) {
-+		rtw_hal_error_msg("c2h_handler");
-+		ret = _FAIL;
-+	}
-+#endif
-+
-+#if defined(CONFIG_LPS) || defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+	if (NULL == padapter->hal_func.fill_fake_txdesc) {
-+		rtw_hal_error_msg("fill_fake_txdesc");
-+		ret = _FAIL;
-+	}
-+#endif
-+
-+#ifndef RTW_HALMAC
-+	if (NULL == padapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
-+		rtw_hal_error_msg("hal_get_tx_buff_rsvd_page_num");
-+		ret = _FAIL;
-+	}
-+#endif /* !RTW_HALMAC */
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	if (NULL == padapter->hal_func.clear_interrupt) {
-+		rtw_hal_error_msg("clear_interrupt");
-+		ret = _FAIL;
-+	}
-+#endif
-+#endif /* CONFIG_WOWLAN */
-+
-+	if (NULL == padapter->hal_func.fw_dl) {
-+		rtw_hal_error_msg("fw_dl");
-+		ret = _FAIL;
-+	}
-+
-+	#ifdef CONFIG_FW_CORRECT_BCN
-+	if (IS_HARDWARE_TYPE_8814A(padapter)
-+	    && NULL == padapter->hal_func.fw_correct_bcn) {
-+		rtw_hal_error_msg("fw_correct_bcn");
-+		ret = _FAIL;
-+	}
-+	#endif
-+
-+	if (!padapter->hal_func.set_tx_power_level_handler) {
-+		rtw_hal_error_msg("set_tx_power_level_handler");
-+		ret = _FAIL;
-+	}
-+	if (!padapter->hal_func.set_tx_power_index_handler) {
-+		rtw_hal_error_msg("set_tx_power_index_handler");
-+		ret = _FAIL;
-+	}
-+	if (!padapter->hal_func.get_tx_power_index_handler) {
-+		rtw_hal_error_msg("get_tx_power_index_handler");
-+		ret = _FAIL;
-+	}
-+
-+	/*** SReset section ***/
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	if (NULL == padapter->hal_func.sreset_init_value) {
-+		rtw_hal_error_msg("sreset_init_value");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.sreset_reset_value) {
-+		rtw_hal_error_msg("sreset_reset_value");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.silentreset) {
-+		rtw_hal_error_msg("silentreset");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.sreset_xmit_status_check) {
-+		rtw_hal_error_msg("sreset_xmit_status_check");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.sreset_linked_status_check) {
-+		rtw_hal_error_msg("sreset_linked_status_check");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.sreset_get_wifi_status) {
-+		rtw_hal_error_msg("sreset_get_wifi_status");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.sreset_inprogress) {
-+		rtw_hal_error_msg("sreset_inprogress");
-+		ret = _FAIL;
-+	}
-+#endif  /* #ifdef DBG_CONFIG_ERROR_DETECT */
-+
-+#ifdef RTW_HALMAC
-+	if (NULL == padapter->hal_func.init_mac_register) {
-+		rtw_hal_error_msg("init_mac_register");
-+		ret = _FAIL;
-+	}
-+	if (NULL == padapter->hal_func.init_phy) {
-+		rtw_hal_error_msg("init_phy");
-+		ret = _FAIL;
-+	}
-+#endif /* RTW_HALMAC */
-+
-+#ifdef CONFIG_RFKILL_POLL
-+	if (padapter->hal_func.hal_radio_onoff_check == NULL) {
-+		rtw_hal_error_msg("hal_radio_onoff_check");
-+		ret = _FAIL;
-+	}
-+#endif
-+#endif
-+	return  ret;
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/hal_mcc.c b/drivers/staging/rtl8723cs/hal/hal_mcc.c
-new file mode 100644
-index 000000000000..904321817e41
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_mcc.c
-@@ -0,0 +1,4078 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifdef CONFIG_MCC_MODE
-+#define _HAL_MCC_C_
-+
-+#include <drv_types.h> /* PADAPTER */
-+#include <rtw_mcc.h> /* mcc structure */
-+#include <hal_data.h> /* HAL_DATA */
-+#include <rtw_pwrctrl.h> /* power control */
-+
-+/*  use for AP/GO + STA/GC case */
-+#define MCC_DURATION_IDX 0 /* druration for station side */
-+#define MCC_TSF_SYNC_OFFSET_IDX 1
-+#define MCC_START_TIME_OFFSET_IDX 2
-+#define MCC_INTERVAL_IDX 3
-+#define MCC_GUARD_OFFSET0_IDX 4
-+#define MCC_GUARD_OFFSET1_IDX 5
-+#define MCC_STOP_THRESHOLD 6
-+#define TU 1024 /* 1 TU equals 1024 microseconds */
-+/* druration, TSF sync offset, start time offset, interval (unit:TU (1024 microseconds))*/
-+u8 mcc_switch_channel_policy_table[][7]={
-+	{20, 50, 40, 100, 0, 0, 30},
-+	{80, 50, 10, 100, 0, 0, 30},
-+	{36, 50, 32, 100, 0, 0, 30},
-+	{30, 50, 35, 100, 0, 0, 30},
-+};
-+
-+const int mcc_max_policy_num = sizeof(mcc_switch_channel_policy_table) /sizeof(u8) /7;
-+
-+static void dump_iqk_val_table(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+	struct hal_iqk_reg_backup *iqk_reg_backup = pHalData->iqk_reg_backup;
-+	u8 total_rf_path = hal_spec->rf_reg_path_num;
-+	u8 rf_path_idx = 0;
-+	u8 backup_chan_idx = 0;
-+	u8 backup_reg_idx = 0;
-+
-+#ifdef CONFIG_MCC_MODE_V2
-+#else
-+
-+	RTW_INFO("=============dump IQK backup table================\n");
-+	for (backup_chan_idx = 0; backup_chan_idx < MAX_IQK_INFO_BACKUP_CHNL_NUM; backup_chan_idx++) {
-+		for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx++) {
-+			for(backup_reg_idx = 0; backup_reg_idx < MAX_IQK_INFO_BACKUP_REG_NUM; backup_reg_idx++) {
-+				RTW_INFO("ch:%d. bw:%d. rf path:%d. reg[%d] = 0x%02x \n"
-+						, iqk_reg_backup[backup_chan_idx].central_chnl
-+						, iqk_reg_backup[backup_chan_idx].bw_mode
-+						, rf_path_idx
-+						, backup_reg_idx
-+						, iqk_reg_backup[backup_chan_idx].reg_backup[rf_path_idx][backup_reg_idx]
-+						);
-+			}
-+		}
-+	}	
-+	RTW_INFO("=============================================\n");
-+
-+#endif
-+}
-+
-+static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_len)
-+{
-+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
-+	u8 p2p_noa_attr_ie[MAX_P2P_IE_LEN] = {0x00};
-+	u32 p2p_noa_attr_len = 0;
-+	u8 noa_desc_num = 1;
-+	u8 opp_ps = 0; /* Disable OppPS */
-+	u8 noa_count = 255;
-+	u32 noa_duration;
-+	u32 noa_interval;
-+	u8 noa_index = 0;
-+	u8 mcc_policy_idx = 0;
-+
-+	mcc_policy_idx = pmccobjpriv->policy_index;
-+	noa_duration = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX] * TU;
-+	noa_interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX] * TU;
-+
-+	/* P2P OUI(4 bytes) */
-+	_rtw_memcpy(p2p_noa_attr_ie, P2P_OUI, 4);
-+	p2p_noa_attr_len = p2p_noa_attr_len + 4;
-+
-+	/* attrute ID(1 byte) */
-+	p2p_noa_attr_ie[p2p_noa_attr_len] = P2P_ATTR_NOA;
-+	p2p_noa_attr_len = p2p_noa_attr_len + 1;
-+	
-+	/* attrute length(2 bytes) length = noa_desc_num*13 + 2 */
-+	RTW_PUT_LE16(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_desc_num * 13 + 2));
-+	p2p_noa_attr_len = p2p_noa_attr_len + 2;
-+
-+	/* Index (1 byte) */
-+	p2p_noa_attr_ie[p2p_noa_attr_len] = noa_index;
-+	p2p_noa_attr_len = p2p_noa_attr_len + 1;
-+
-+	/* CTWindow and OppPS Parameters (1 byte) */
-+	p2p_noa_attr_ie[p2p_noa_attr_len] = opp_ps;
-+	p2p_noa_attr_len = p2p_noa_attr_len+ 1;
-+
-+	/* NoA Count (1 byte) */
-+	p2p_noa_attr_ie[p2p_noa_attr_len] = noa_count;
-+	p2p_noa_attr_len = p2p_noa_attr_len + 1;
-+
-+	/* NoA Duration (4 bytes) unit: microseconds */
-+	RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_duration);
-+	p2p_noa_attr_len = p2p_noa_attr_len + 4;
-+
-+	/* NoA Interval (4 bytes) unit: microseconds */
-+	RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_interval);
-+	p2p_noa_attr_len = p2p_noa_attr_len + 4;
-+
-+	/* NoA Start Time (4 bytes) unit: microseconds */
-+	RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, pmccadapriv->noa_start_time);
-+	if (0)
-+		RTW_INFO("indxe:%d, start_time=0x%02x:0x%02x:0x%02x:0x%02x\n"
-+		, noa_index
-+		, p2p_noa_attr_ie[p2p_noa_attr_len]
-+		, p2p_noa_attr_ie[p2p_noa_attr_len + 1]
-+		, p2p_noa_attr_ie[p2p_noa_attr_len + 2]
-+		, p2p_noa_attr_ie[p2p_noa_attr_len + 3]);
-+
-+	p2p_noa_attr_len = p2p_noa_attr_len + 4;
-+	rtw_set_ie(ie, _VENDOR_SPECIFIC_IE_, p2p_noa_attr_len, (u8 *)p2p_noa_attr_ie, ie_len);
-+}
-+
-+
-+/**
-+ * rtw_hal_mcc_update_go_p2p_ie - update go p2p ie(add NoA attribute)
-+ * @padapter: the adapter to be update go p2p ie
-+ */
-+static void rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter)
-+{
-+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
-+	struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+	u8 *pos = NULL;
-+
-+
-+	/* no noa attribute, build it */
-+	if (pmccadapriv->p2p_go_noa_ie_len == 0)
-+		rtw_hal_mcc_build_p2p_noa_attr(padapter, pmccadapriv->p2p_go_noa_ie, &pmccadapriv->p2p_go_noa_ie_len);
-+	else {
-+		/* has noa attribut, modify it */
-+		u32 noa_duration = 0;
-+		
-+		/* update index */
-+		pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 15;
-+		/* 0~255 */
-+		(*pos) = ((*pos) + 1) % 256;
-+		if (0)
-+			RTW_INFO("indxe:%d\n", (*pos));
-+
-+
-+		/* update duration */
-+		noa_duration = mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX] * TU;
-+		pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 12;
-+		RTW_PUT_LE32(pos, noa_duration);
-+
-+		/* update start time */
-+		pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 4;
-+		RTW_PUT_LE32(pos, pmccadapriv->noa_start_time);
-+		if (0)
-+			RTW_INFO("start_time=0x%02x:0x%02x:0x%02x:0x%02x\n"
-+			, ((u8*)(pos))[0]
-+			, ((u8*)(pos))[1]
-+			, ((u8*)(pos))[2]
-+			, ((u8*)(pos))[3]);
-+
-+	}
-+
-+	if (0) {
-+		RTW_INFO("p2p_go_noa_ie_len:%d\n", pmccadapriv->p2p_go_noa_ie_len);
-+		RTW_INFO_DUMP("\n", pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len);
-+	}
-+	update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE, 0);
-+}
-+
-+/**
-+ * rtw_hal_mcc_remove_go_p2p_ie - remove go p2p ie(add NoA attribute)
-+ * @padapter: the adapter to be update go p2p ie
-+ */
-+static void rtw_hal_mcc_remove_go_p2p_ie(PADAPTER padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
-+
-+	/* chech has noa ie or not */
-+	if (pmccadapriv->p2p_go_noa_ie_len == 0)
-+		return;
-+
-+	pmccadapriv->p2p_go_noa_ie_len = 0;
-+	update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE, 0);
-+}
-+
-+/* restore IQK value for all interface */
-+void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter)
-+{
-+	u8 take_care_iqk = _FALSE;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	_adapter *iface = NULL;
-+	struct mcc_adapter_priv *mccadapriv = NULL;
-+	u8 i = 0;
-+
-+	rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
-+	if (take_care_iqk == _TRUE && MCC_EN(padapter)) {
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			if (iface == NULL)
-+				continue;
-+
-+			mccadapriv = &iface->mcc_adapterpriv;
-+			if (mccadapriv->role == MCC_ROLE_MAX)
-+				continue;
-+
-+			rtw_hal_ch_sw_iqk_info_restore(iface, CH_SW_USE_CASE_MCC);
-+		}
-+	}
-+
-+	if (0)
-+		dump_iqk_val_table(padapter);
-+}
-+
-+u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status)
-+{
-+	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+
-+	if (pmccobjpriv->mcc_status & (mcc_status))
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+void rtw_hal_set_mcc_status(PADAPTER padapter, u8 mcc_status)
-+{
-+	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+
-+	pmccobjpriv->mcc_status |= (mcc_status);
-+}
-+
-+void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status)
-+{
-+	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+
-+	pmccobjpriv->mcc_status &= (~mcc_status);
-+}
-+
-+static void rtw_hal_mcc_update_policy_table(PADAPTER adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
-+	u8 mcc_duration = mccobjpriv->duration;
-+	s8 mcc_policy_idx = mccobjpriv->policy_index;
-+	u8 interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX];
-+	u8 new_mcc_duration_time = 0;
-+	u8 new_starttime_offset = 0;
-+
-+	/* convert % to ms */
-+	new_mcc_duration_time = mcc_duration * interval / 100;
-+
-+	/* start time offset = (interval - duration time)/2 */
-+	new_starttime_offset = (interval - new_mcc_duration_time) >> 1;
-+
-+	/* update modified parameters */
-+	mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX]
-+		= new_mcc_duration_time;
-+
-+	mcc_switch_channel_policy_table[mcc_policy_idx][MCC_START_TIME_OFFSET_IDX]
-+		= new_starttime_offset;
-+	
-+
-+}
-+
-+static void rtw_hal_config_mcc_switch_channel_setting(PADAPTER padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
-+	struct registry_priv *registry_par = &padapter->registrypriv;
-+	u8 mcc_duration = 0;
-+	s8 mcc_policy_idx = 0;
-+
-+	mcc_policy_idx = registry_par->rtw_mcc_policy_table_idx;
-+	mcc_duration = mccobjpriv->duration;
-+
-+	if (mcc_policy_idx < 0 || mcc_policy_idx >= mcc_max_policy_num) {
-+		mccobjpriv->policy_index = 0;
-+		RTW_INFO("[MCC] can't find table(%d), use default policy(%d)\n",
-+			mcc_policy_idx, mccobjpriv->policy_index);
-+	} else
-+		mccobjpriv->policy_index = mcc_policy_idx;
-+
-+	/* convert % to time */
-+	if (mcc_duration != 0)
-+		rtw_hal_mcc_update_policy_table(padapter);
-+
-+	RTW_INFO("[MCC] policy(%d): %d,%d,%d,%d,%d,%d\n"
-+		, mccobjpriv->policy_index
-+		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX]
-+		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_TSF_SYNC_OFFSET_IDX]
-+		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_START_TIME_OFFSET_IDX]
-+		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_INTERVAL_IDX]
-+		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX]
-+		, mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]);
-+
-+}
-+
-+static void rtw_hal_mcc_assign_tx_threshold(PADAPTER padapter) 
-+{
-+	struct registry_priv *preg = &padapter->registrypriv;
-+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+
-+	switch (pmccadapriv->role) {
-+	case MCC_ROLE_STA:
-+	case MCC_ROLE_GC:
-+		switch (pmlmeext->cur_bwmode) {
-+		case CHANNEL_WIDTH_20:
-+			/*
-+			* target tx byte(bytes) = target tx tp(Mbits/sec) * 1024 * 1024 / 8 * (duration(ms) / 1024)
-+			*					= target tx tp(Mbits/sec) * 128 * duration(ms)
-+			* note:
-+			* target tx tp(Mbits/sec) * 1024 * 1024 / 8 ==> Mbits to bytes
-+			* duration(ms) / 1024 ==> msec to sec
-+			*/
-+			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration;
-+			break;
-+		case CHANNEL_WIDTH_40:
-+			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw40_target_tx_tp * 128 * pmccadapriv->mcc_duration;
-+			break;
-+		case CHANNEL_WIDTH_80:
-+			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_sta_bw80_target_tx_tp * 128 * pmccadapriv->mcc_duration;
-+			break;
-+		case CHANNEL_WIDTH_160:
-+		case CHANNEL_WIDTH_80_80:
-+			RTW_INFO(FUNC_ADPT_FMT": not support bwmode = %d\n"
-+				, FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode);
-+			break;
-+		}
-+		break;
-+	case MCC_ROLE_AP:
-+	case MCC_ROLE_GO:
-+		switch (pmlmeext->cur_bwmode) {
-+		case CHANNEL_WIDTH_20:
-+			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration;
-+			break;
-+		case CHANNEL_WIDTH_40:
-+			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw40_target_tx_tp * 128 * pmccadapriv->mcc_duration;
-+			break;
-+		case CHANNEL_WIDTH_80:
-+			pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw80_target_tx_tp * 128 * pmccadapriv->mcc_duration;
-+			break;
-+		case CHANNEL_WIDTH_160:
-+		case CHANNEL_WIDTH_80_80:
-+			RTW_INFO(FUNC_ADPT_FMT": not support bwmode = %d\n"
-+				, FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode);
-+			break;
-+		}
-+		break;
-+	default:
-+		RTW_INFO(FUNC_ADPT_FMT": unknown role = %d\n"
-+			, FUNC_ADPT_ARG(padapter), pmccadapriv->role);
-+		break;
-+	}
-+}
-+
-+#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+static void mcc_cfg_phdym_rf_ch (_adapter *adapter)
-+{
-+		struct mcc_adapter_priv *mccadapriv = &adapter->mcc_adapterpriv;
-+		struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+		HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
-+		struct dm_struct *dm = &hal->odmpriv;
-+		struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
-+		u8 order = 0;
-+
-+		set_channel_bwmode(adapter, mlmeext->cur_channel, mlmeext->cur_ch_offset, mlmeext->cur_bwmode);
-+		order = mccadapriv->order;
-+		mcc_dm->mcc_rf_ch[order] = phy_query_rf_reg(adapter, RF_PATH_A, 0x18, 0x03ff);
-+}
-+
-+static void mcc_cfg_phdym_update_macid (_adapter *adapter, u8 add, u8 mac_id)
-+{
-+		struct mcc_adapter_priv *mccadapriv = &adapter->mcc_adapterpriv;
-+		struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+		HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
-+		struct dm_struct *dm = &hal->odmpriv;
-+		struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
-+		u8 order = 0, i = 0;
-+
-+		order = mccadapriv->order;
-+		if (add) {
-+			for (i = 0; i < NUM_STA; i++) {
-+				if (mcc_dm->sta_macid[order][i] == 0xff) {
-+					mcc_dm->sta_macid[order][i] = mac_id;
-+					break;
-+				}
-+			}
-+		} else {
-+			for (i = 0; i < NUM_STA; i++) {
-+				if (mcc_dm->sta_macid[order][i] == mac_id) {
-+					mcc_dm->sta_macid[order][i] = 0xff;
-+					break;
-+				}
-+			}
-+		}
-+
-+		
-+}
-+
-+static void mcc_cfg_phdym_start(_adapter *adapter, u8 start)
-+{
-+	struct dvobj_priv *dvobj;
-+	struct mcc_obj_priv *mccobjpriv;
-+	HAL_DATA_TYPE *hal;
-+	struct dm_struct *dm;
-+	struct _phydm_mcc_dm_ *mcc_dm;
-+	u8 rfk_forbidden = _TRUE;
-+	u8 i = 0, j = 0;
-+
-+	dvobj = adapter_to_dvobj(adapter);
-+	mccobjpriv = adapter_to_mccobjpriv(adapter);
-+	hal = GET_HAL_DATA(adapter);
-+	dm = &hal->odmpriv;
-+	mcc_dm = &dm->mcc_dm;
-+
-+	if (start) {
-+		#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+		mcc_dm->mcc_status = mccobjpriv->mcc_phydm_offload;
-+		#endif
-+
-+		rfk_forbidden = _TRUE;
-+		halrf_cmn_info_set(dm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
-+	} else {
-+		rfk_forbidden = _FALSE;
-+		halrf_cmn_info_set(dm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
-+
-+		#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+		for(i = 0; i < MAX_MCC_NUM; i ++) {
-+			for(j = 0; j < NUM_STA; j ++) {
-+				if (mcc_dm->sta_macid[i][j] != 0xff)
-+					/* clear all used value for mcc stop */
-+					/* do nothing for mcc start due to phydm will init to 0xff */
-+					mcc_dm->sta_macid[i][j] = 0xff;
-+			}
-+			mcc_dm->mcc_rf_ch[i] = 0xff;
-+		}
-+		mcc_dm->mcc_status = 0;
-+		#endif
-+	}
-+}
-+
-+static void mcc_cfg_phdym_dump(_adapter *adapter, void *sel)
-+{
-+	HAL_DATA_TYPE *hal;
-+	struct dm_struct *dm;
-+	struct _phydm_mcc_dm_ *mcc_dm;
-+	u8 rfk_forbidden = _TRUE;
-+	u8 i = 0, j = 0;
-+
-+
-+	hal = GET_HAL_DATA(adapter);
-+	dm = &hal->odmpriv;
-+	mcc_dm = &dm->mcc_dm;
-+
-+	rfk_forbidden = halrf_cmn_info_get(dm, HALRF_CMNINFO_RFK_FORBIDDEN);
-+	RTW_PRINT_SEL(sel, "dump mcc dm info\n");
-+	RTW_PRINT_SEL(sel, "mcc_status=%d\n", mcc_dm->mcc_status);
-+	RTW_PRINT_SEL(sel, "rfk_forbidden=%d\n", rfk_forbidden);
-+	for(i = 0; i < MAX_MCC_NUM; i ++) {
-+
-+		if (mcc_dm->mcc_rf_ch[i] != 0xff)
-+			RTW_PRINT_SEL(sel, "mcc_dm->mcc_rf_ch[%d] = 0x%02x\n", i, mcc_dm->mcc_rf_ch[i]);
-+		
-+		for(j = 0; j < NUM_STA; j ++) {
-+			if (mcc_dm->sta_macid[i][j] != 0xff)
-+				RTW_PRINT_SEL(sel, "mcc_dm->sta_macid[%d][%d] = %d\n", i, j, mcc_dm->sta_macid[i][j]);
-+		}
-+	}
-+}
-+
-+static void mcc_cfg_phdym_offload(_adapter *adapter, u8 enable)
-+{
-+	struct mcc_obj_priv *mccobjpriv = adapter_to_mccobjpriv(adapter);
-+	_adapter *iface = NULL;
-+	struct mcc_adapter_priv *mccadapriv = NULL;
-+	HAL_DATA_TYPE *hal = NULL;
-+	struct dm_struct *dm = NULL;
-+	struct _phydm_mcc_dm_ *mcc_dm = NULL;
-+	struct sta_priv *stapriv = NULL;
-+	struct sta_info *sta = NULL;
-+	struct wlan_network *cur_network = NULL;
-+	_irqL irqL;
-+	_list	*head = NULL, *list = NULL;
-+	u8 i = 0;
-+
-+
-+	hal = GET_HAL_DATA(adapter);
-+	dm = &hal->odmpriv;
-+	mcc_dm = &dm->mcc_dm;
-+
-+	/* due to phydm will rst related date, driver must set related data */
-+	if (enable) {
-+		for (i = 0; i < MAX_MCC_NUM; i++) {
-+			iface = mccobjpriv->iface[i];
-+			if (!iface)
-+				continue;
-+			stapriv = &iface->stapriv;
-+			mccadapriv = &iface->mcc_adapterpriv;
-+			switch (mccadapriv->role) {
-+			case MCC_ROLE_STA:
-+			case MCC_ROLE_GC:
-+				cur_network = &iface->mlmepriv.cur_network;
-+				sta = rtw_get_stainfo(stapriv, cur_network->network.MacAddress);
-+				if (sta)
-+					mcc_cfg_phdym_update_macid(iface, _TRUE, sta->cmn.mac_id);
-+				break;
-+			case MCC_ROLE_AP:
-+			case MCC_ROLE_GO:
-+				_enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+
-+				head = &stapriv->asoc_list;
-+				list = get_next(head);
-+		
-+				while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
-+					sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
-+					list = get_next(list);
-+					mcc_cfg_phdym_update_macid(iface, _TRUE, sta->cmn.mac_id);
-+				}
-+
-+				_exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
-+				break;
-+			default:
-+				RTW_INFO("Unknown role\n");
-+				rtw_warn_on(1);
-+				break;
-+			}
-+			
-+		}
-+	}
-+
-+	mcc_dm->mcc_status = enable;
-+}
-+
-+static void rtw_hal_mcc_cfg_phydm (_adapter *adapter, enum mcc_cfg_phydm_ops ops, void *data)
-+{
-+	switch (ops) {
-+	case MCC_CFG_PHYDM_OFFLOAD:
-+		mcc_cfg_phdym_offload(adapter, *(u8 *)data);
-+		break;
-+	case MCC_CFG_PHYDM_RF_CH:
-+		mcc_cfg_phdym_rf_ch(adapter);
-+		break;
-+	case MCC_CFG_PHYDM_ADD_CLIENT:
-+		mcc_cfg_phdym_update_macid(adapter, _TRUE, *(u8 *)data);
-+		break;
-+	case MCC_CFG_PHYDM_REMOVE_CLIENT:
-+		mcc_cfg_phdym_update_macid(adapter, _FALSE, *(u8 *)data);
-+		break;
-+	case MCC_CFG_PHYDM_START:
-+		mcc_cfg_phdym_start(adapter, _TRUE);
-+		break;
-+	case MCC_CFG_PHYDM_STOP:
-+		mcc_cfg_phdym_start(adapter, _FALSE);
-+		break;
-+	case MCC_CFG_PHYDM_DUMP:
-+		mcc_cfg_phdym_dump(adapter, data);
-+		break;
-+	case MCC_CFG_PHYDM_MAX:
-+	default:
-+		RTW_ERR("[MCC] rtw_hal_mcc_cfg_phydm ops error (%d)\n", ops);
-+		break;
-+
-+	}
-+}
-+#endif
-+
-+static void rtw_hal_config_mcc_role_setting(PADAPTER padapter, u8 order)
-+{
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
-+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *psta = NULL;
-+	struct registry_priv *preg = &padapter->registrypriv;
-+	_irqL irqL;
-+	_list	*phead =NULL, *plist = NULL;
-+	u8 policy_index = 0;
-+	u8 mcc_duration = 0;
-+	u8 mcc_interval = 0;
-+	u8 starting_ap_num = DEV_AP_STARTING_NUM(pdvobjpriv);
-+	u8 ap_num = DEV_AP_NUM(pdvobjpriv);
-+
-+	policy_index = pmccobjpriv->policy_index;
-+	mcc_duration = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX]
-+		- mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX]
-+			- mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX];
-+	mcc_interval = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX];
-+
-+	if (starting_ap_num == 0 && ap_num == 0) {
-+		pmccadapriv->order = order;
-+
-+		if (pmccadapriv->order == 0) {
-+			/* setting is smiliar to GO/AP */
-+			/* pmccadapriv->mcc_duration = mcc_interval - mcc_duration;*/
-+			pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;
-+		} else if (pmccadapriv->order == 1) {
-+			/* pmccadapriv->mcc_duration = mcc_duration; */
-+			pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;
-+		} else {
-+			RTW_INFO("[MCC] not support >= 3 interface\n");
-+			rtw_warn_on(1);
-+		}
-+
-+		rtw_hal_mcc_assign_tx_threshold(padapter);
-+
-+		psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
-+		if (psta) {
-+			/* combine AP/GO macid and mgmt queue macid to bitmap */
-+			pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid);
-+			#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+			rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &psta->cmn.mac_id);
-+			#endif
-+		} else {
-+			RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter));
-+			rtw_warn_on(1);
-+		}
-+	} else {
-+		/* GO/AP is 1nd order  GC/STA is 2nd order */
-+		switch (pmccadapriv->role) {
-+		case MCC_ROLE_STA:
-+		case MCC_ROLE_GC:
-+			pmccadapriv->order = 1;
-+			pmccadapriv->mcc_duration = mcc_duration;
-+
-+			rtw_hal_mcc_assign_tx_threshold(padapter);
-+			/* assign used mac to avoid affecting RA */
-+			pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;
-+
-+			psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
-+			if (psta) {
-+				/* combine AP/GO macid and mgmt queue macid to bitmap */
-+				pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid);
-+				#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+				rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &psta->cmn.mac_id);
-+				#endif
-+			} else {
-+				RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter));
-+				rtw_warn_on(1);
-+			}
-+			break;
-+		case MCC_ROLE_AP:
-+		case MCC_ROLE_GO:
-+			pmccadapriv->order = 0;
-+			/* total druation value equals interval */
-+			pmccadapriv->mcc_duration = mcc_interval - mcc_duration;
-+			pmccadapriv->p2p_go_noa_ie_len = 0; /* not NoA attribute at init time */
-+
-+			rtw_hal_mcc_assign_tx_threshold(padapter);
-+
-+			_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+			phead = &pstapriv->asoc_list;
-+			plist = get_next(phead);
-+			pmccadapriv->mcc_macid_bitmap = 0;
-+	
-+			while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+				psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+				plist = get_next(plist);
-+				pmccadapriv->mcc_macid_bitmap |= BIT(psta->cmn.mac_id);
-+				#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+				rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &psta->cmn.mac_id);
-+				#endif
-+			}
-+
-+			_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+			psta = rtw_get_bcmc_stainfo(padapter);
-+
-+			if (psta != NULL)
-+				pmccadapriv->mgmt_queue_macid = psta->cmn.mac_id;
-+			else {
-+				pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;
-+				RTW_INFO(FUNC_ADPT_FMT":bcmc station is NULL, use macid %d\n"
-+					, FUNC_ADPT_ARG(padapter), pmccadapriv->mgmt_queue_macid);
-+			}
-+
-+			/* combine client macid and mgmt queue macid to bitmap */
-+			pmccadapriv->mcc_macid_bitmap |= BIT(pmccadapriv->mgmt_queue_macid);
-+			break;
-+		default:
-+			RTW_INFO("Unknown role\n");
-+			rtw_warn_on(1);
-+			break;
-+		}
-+
-+	}
-+
-+	/* setting Null data parameters */
-+	if (pmccadapriv->role == MCC_ROLE_STA) {
-+			pmccadapriv->null_early = 3;
-+			pmccadapriv->null_rty_num= 5;
-+	} else if (pmccadapriv->role == MCC_ROLE_GC) {
-+			pmccadapriv->null_early = 2;
-+			pmccadapriv->null_rty_num= 5;
-+	} else {
-+			pmccadapriv->null_early = 0;
-+			pmccadapriv->null_rty_num= 0;
-+	}
-+
-+	RTW_INFO("********* "FUNC_ADPT_FMT" *********\n", FUNC_ADPT_ARG(padapter));
-+	RTW_INFO("order:%d\n", pmccadapriv->order);
-+	RTW_INFO("role:%d\n", pmccadapriv->role);
-+	RTW_INFO("mcc duration:%d\n", pmccadapriv->mcc_duration);
-+	RTW_INFO("null_early:%d\n", pmccadapriv->null_early);
-+	RTW_INFO("null_rty_num:%d\n", pmccadapriv->null_rty_num);
-+	RTW_INFO("mgmt queue macid:%d\n", pmccadapriv->mgmt_queue_macid);
-+	RTW_INFO("bitmap:0x%02x\n", pmccadapriv->mcc_macid_bitmap);
-+	RTW_INFO("target tx bytes:%d\n", pmccadapriv->mcc_target_tx_bytes_to_port);
-+	RTW_INFO("**********************************\n");
-+
-+	pmccobjpriv->iface[pmccadapriv->order] = padapter;
-+	#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+	rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_RF_CH, NULL);
-+	#endif
-+
-+}
-+
-+static void rtw_hal_mcc_rqt_tsf(PADAPTER padapter, u64 *out_tsf)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
-+	PADAPTER order0_iface = NULL;
-+	PADAPTER order1_iface = NULL;
-+	struct submit_ctx *tsf_req_sctx = NULL;
-+	enum _hw_port tsfx = MAX_HW_PORT;
-+	enum _hw_port tsfy = MAX_HW_PORT;
-+	u8 cmd[H2C_MCC_RQT_TSF_LEN] = {0};
-+
-+	_enter_critical_mutex(&mccobjpriv->mcc_tsf_req_mutex, NULL);
-+
-+	order0_iface = mccobjpriv->iface[0];
-+	order1_iface = mccobjpriv->iface[1];
-+
-+	tsf_req_sctx = &mccobjpriv->mcc_tsf_req_sctx;
-+	rtw_sctx_init(tsf_req_sctx, MCC_EXPIRE_TIME);
-+	mccobjpriv->mcc_tsf_req_sctx_order = 0;
-+	tsfx = rtw_hal_get_port(order0_iface);
-+	tsfy = rtw_hal_get_port(order1_iface);
-+
-+	SET_H2CCMD_MCC_RQT_TSFX(cmd, tsfx);
-+	SET_H2CCMD_MCC_RQT_TSFY(cmd, tsfy);
-+
-+	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_RQT_TSF, H2C_MCC_RQT_TSF_LEN, cmd);
-+
-+	if (!rtw_sctx_wait(tsf_req_sctx, __func__))
-+		RTW_INFO(FUNC_ADPT_FMT": wait for mcc tsf req C2H time out\n", FUNC_ADPT_ARG(padapter));
-+
-+	if (tsf_req_sctx->status  == RTW_SCTX_DONE_SUCCESS && out_tsf != NULL) {
-+		out_tsf[0] = order0_iface->mcc_adapterpriv.tsf;
-+		out_tsf[1] = order1_iface->mcc_adapterpriv.tsf;
-+	}
-+
-+
-+	_exit_critical_mutex(&mccobjpriv->mcc_tsf_req_mutex, NULL);
-+}
-+
-+static u8 rtw_hal_mcc_check_start_time_is_valid(PADAPTER padapter, u8 case_num,
-+	u32 tsfdiff, s8 *upper_bound_0, s8 *lower_bound_0, s8 *upper_bound_1, s8 *lower_bound_1)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
-+	u8 duration_0 = 0, duration_1 = 0;
-+	s8 final_upper_bound = 0, final_lower_bound = 0;
-+	u8 intersection =  _FALSE;
-+	u8 min_start_time = 5;
-+	u8 max_start_time = 95;
-+	
-+	duration_0 = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration;
-+	duration_1 = mccobjpriv->iface[1]->mcc_adapterpriv.mcc_duration;
-+
-+	switch(case_num) {
-+	case 1:
-+		*upper_bound_0 = tsfdiff;
-+		*lower_bound_0 = tsfdiff - duration_1;
-+		*upper_bound_1 = 150 - duration_1;
-+		*lower_bound_1= 0;
-+		break;
-+	case 2:
-+		*upper_bound_0 = tsfdiff + 100;
-+		*lower_bound_0 = tsfdiff + 100 - duration_1;
-+		*upper_bound_1 = 150 - duration_1;
-+		*lower_bound_1= 0;
-+		break;
-+	case 3:
-+		*upper_bound_0 = tsfdiff + 50;
-+		*lower_bound_0 = tsfdiff + 50 - duration_1;
-+		*upper_bound_1 = 150 - duration_1;
-+		*lower_bound_1= 0;
-+		break;
-+	case 4:
-+		*upper_bound_0 = tsfdiff;
-+		*lower_bound_0 = tsfdiff - duration_1;
-+		*upper_bound_1 = 150 - duration_1;
-+		*lower_bound_1= 0;
-+		break;
-+	case 5:
-+		*upper_bound_0 = 200 - tsfdiff;
-+		*lower_bound_0 = 200 - tsfdiff - duration_1;
-+		*upper_bound_1 = 150 - duration_1;
-+		*lower_bound_1= 0;
-+		break;
-+	case 6:
-+		*upper_bound_0 = tsfdiff - 50;
-+		*lower_bound_0 = tsfdiff - 50 - duration_1;
-+		*upper_bound_1 = 150 - duration_1;
-+		*lower_bound_1= 0;
-+		break;
-+	default:
-+		RTW_ERR("[MCC] %s: error case number(%d\n)", __func__, case_num);
-+	}
-+
-+
-+	/* check Intersection or not */
-+	if ((*lower_bound_1 >= *upper_bound_0) ||
-+		(*lower_bound_0 >= *upper_bound_1))
-+		intersection = _FALSE;
-+	else
-+		intersection = _TRUE;
-+
-+	if (intersection) {
-+		if (*upper_bound_0 > *upper_bound_1)
-+			final_upper_bound = *upper_bound_1;
-+		else
-+			final_upper_bound = *upper_bound_0;
-+
-+		if (*lower_bound_0 > *lower_bound_1)
-+			final_lower_bound = *lower_bound_0;
-+		else
-+			final_lower_bound = *lower_bound_1;
-+
-+		mccobjpriv->start_time = (final_lower_bound + final_upper_bound) / 2;
-+
-+		/* check start time less than 5ms, request by Pablo@SD1 */
-+		if (mccobjpriv->start_time <= min_start_time) {
-+			mccobjpriv->start_time = 6;
-+			if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) {
-+				intersection = _FALSE;
-+				goto exit;
-+			}
-+		}
-+
-+		/* check start time less than 95ms */
-+		if (mccobjpriv->start_time >= max_start_time) {
-+			mccobjpriv->start_time = 90;
-+			if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) {
-+				intersection = _FALSE;
-+				goto exit;
-+			}
-+		}
-+	}
-+
-+exit:
-+	return intersection;
-+}
-+
-+static void rtw_hal_mcc_decide_duration(PADAPTER padapter)
-+{
-+	struct registry_priv *registry_par = &padapter->registrypriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
-+	struct mcc_adapter_priv *mccadapriv = NULL, *mccadapriv_order0 = NULL, *mccadapriv_order1 = NULL;
-+	_adapter *iface = NULL, *iface_order0 = NULL,  *iface_order1 = NULL;
-+	u8 duration = 0, i = 0, duration_time;
-+	u8 mcc_interval = 150;
-+
-+	iface_order0 = mccobjpriv->iface[0];
-+	iface_order1 = mccobjpriv->iface[1];
-+	mccadapriv_order0 = &iface_order0->mcc_adapterpriv;
-+	mccadapriv_order1 = &iface_order1->mcc_adapterpriv;
-+	
-+	if (mccobjpriv->duration == 0) {
-+		/* default */
-+		duration = 30;/*(%)*/
-+		RTW_INFO("%s: mccobjpriv->duration=0, use default value(%d)\n",
-+			__FUNCTION__, duration);
-+	} else {
-+		duration = mccobjpriv->duration;/*(%)*/
-+		RTW_INFO("%s: mccobjpriv->duration=%d\n",
-+			__FUNCTION__, duration);
-+	}
-+
-+	mccobjpriv->interval = mcc_interval;
-+	mccobjpriv->mcc_stop_threshold = 2000 * 4 / 300 - 6;
-+	/* convert % to ms, for primary adapter */
-+	duration_time = mccobjpriv->interval * duration / 100;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+
-+		if (!iface)
-+			continue;
-+
-+		mccadapriv = &iface->mcc_adapterpriv;
-+		if (mccadapriv->role == MCC_ROLE_MAX)
-+			continue;
-+
-+		if (is_primary_adapter(iface))
-+			mccadapriv->mcc_duration = duration_time;
-+		else
-+			mccadapriv->mcc_duration = mccobjpriv->interval - duration_time;
-+	}
-+
-+	RTW_INFO("[MCC]"  FUNC_ADPT_FMT " order 0 duration=%d\n", FUNC_ADPT_ARG(iface_order0), mccadapriv_order0->mcc_duration);
-+	RTW_INFO("[MCC]"  FUNC_ADPT_FMT " order 1 duration=%d\n", FUNC_ADPT_ARG(iface_order1), mccadapriv_order1->mcc_duration);
-+}
-+
-+static u8 rtw_hal_mcc_update_timing_parameters(PADAPTER padapter, u8 force_update)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	u8 need_update = _FALSE;
-+	u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
-+	u8 ap_num = DEV_AP_NUM(dvobj);
-+
-+
-+	/* for STA+STA, modify policy table */
-+	if (starting_ap_num == 0 && ap_num == 0) {
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+		struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
-+		struct mcc_adapter_priv *pmccadapriv = NULL;
-+		_adapter *iface = NULL;
-+		u64 tsf[MAX_MCC_NUM] = {0};
-+		u64 tsf0 = 0, tsf1 = 0;
-+		u32 beaconperiod_0 = 0, beaconperiod_1 = 0, tsfdiff = 0;
-+		s8 upper_bound_0 = 0, lower_bound_0 = 0;
-+		s8 upper_bound_1 = 0, lower_bound_1 = 0;
-+		u8 valid = _FALSE;
-+		u8 case_num = 1;
-+		u8 i = 0;
-+		
-+		/* query TSF */
-+		rtw_hal_mcc_rqt_tsf(padapter, tsf);
-+
-+		/* selecet policy table according TSF diff */
-+		tsf0 = tsf[0];
-+		beaconperiod_0 = pmccobjpriv->iface[0]->mlmepriv.cur_network.network.Configuration.BeaconPeriod;
-+		tsf0 = rtw_modular64(tsf0, (beaconperiod_0 * TU));
-+
-+		tsf1 = tsf[1];
-+		beaconperiod_1 = pmccobjpriv->iface[1]->mlmepriv.cur_network.network.Configuration.BeaconPeriod;
-+		tsf1 = rtw_modular64(tsf1, (beaconperiod_1 * TU));
-+
-+		if (tsf0 > tsf1)
-+			tsfdiff = tsf0- tsf1;
-+		else
-+			tsfdiff = (tsf0 +  beaconperiod_0 * TU) - tsf1;
-+
-+		/* convert to ms */
-+		tsfdiff = (tsfdiff / TU);
-+
-+		/* force update*/
-+		if (force_update) {
-+			RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
-+				pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
-+			RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
-+			RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
-+				__func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
-+			pmccobjpriv->last_tsfdiff = tsfdiff;
-+			need_update = _TRUE;
-+		} else {
-+			if (pmccobjpriv->last_tsfdiff > tsfdiff) {
-+				/* last tsfdiff - current tsfdiff > THRESHOLD, update parameters */
-+				if (pmccobjpriv->last_tsfdiff > (tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) {
-+					RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
-+						pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
-+					RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
-+					RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
-+						__func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
-+
-+					pmccobjpriv->last_tsfdiff = tsfdiff;
-+					need_update = _TRUE;
-+				} else {
-+					need_update = _FALSE;
-+				}
-+			} else if (tsfdiff > pmccobjpriv->last_tsfdiff){
-+				/* current tsfdiff - last tsfdiff > THRESHOLD, update parameters */
-+				if (tsfdiff > (pmccobjpriv->last_tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) {
-+					RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
-+						pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
-+					RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
-+					RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
-+						__func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
-+
-+					pmccobjpriv->last_tsfdiff = tsfdiff;
-+					need_update = _TRUE;
-+				} else {
-+					need_update = _FALSE;
-+				}
-+			} else {
-+				need_update = _FALSE;
-+			}
-+		}
-+
-+		if (need_update == _FALSE)
-+			goto exit;
-+
-+		rtw_hal_mcc_decide_duration(padapter);
-+
-+		if (tsfdiff <= 50) {
-+	
-+			/* RX TBTT 0 */
-+			case_num = 1;
-+			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
-+				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
-+
-+			if (valid)
-+				goto valid_result;
-+	
-+			/* RX TBTT 1 */
-+			case_num = 2;
-+			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
-+				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
-+
-+			if (valid)
-+				goto valid_result;
-+			
-+			/* RX TBTT 2 */
-+			case_num = 3;
-+			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
-+				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
-+
-+			if (valid)
-+				goto valid_result;
-+
-+			if (valid == _FALSE) {
-+				RTW_INFO("[MCC] do not find fit start time\n");
-+				RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n",
-+					tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval);
-+
-+			}
-+
-+		} else {
-+
-+			/* RX TBTT 0 */
-+			case_num = 4;
-+			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
-+				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
-+
-+			if (valid)
-+				goto valid_result;
-+			
-+			
-+			/* RX TBTT 1 */
-+			case_num = 5;
-+			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
-+				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
-+
-+			if (valid)
-+				goto valid_result;
-+
-+			
-+			/* RX TBTT 2 */
-+			case_num = 6;
-+			valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
-+				&upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
-+
-+			if (valid)
-+				goto valid_result;
-+
-+			if (valid == _FALSE) {
-+				RTW_INFO("[MCC] do not find fit start time\n");
-+				RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n",
-+					tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval);
-+			}
-+		}
-+
-+		
-+
-+	valid_result:
-+		RTW_INFO("********************\n");
-+		RTW_INFO("%s: case_num:%d, start time:%d\n",
-+				__func__, case_num, pmccobjpriv->start_time);
-+		RTW_INFO("%s: upper_bound_0:%d, lower_bound_0:%d\n",
-+				__func__, upper_bound_0, lower_bound_0);
-+		RTW_INFO("%s: upper_bound_1:%d, lower_bound_1:%d\n",
-+				__func__, upper_bound_1, lower_bound_1);
-+		
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			if (iface == NULL)
-+				continue;
-+
-+			pmccadapriv = &iface->mcc_adapterpriv;
-+			pmccadapriv = &iface->mcc_adapterpriv;
-+			if (pmccadapriv->role == MCC_ROLE_MAX)
-+				continue;
-+#if 0
-+			if (pmccadapriv->order == 0) {
-+				pmccadapriv->mcc_duration = mcc_duration;
-+			} else if (pmccadapriv->order == 1) {
-+				pmccadapriv->mcc_duration = mcc_interval - mcc_duration;
-+			} else {
-+				RTW_INFO("[MCC] not support >= 3 interface\n");
-+				rtw_warn_on(1);
-+			}
-+#endif
-+			RTW_INFO("********************\n");
-+			RTW_INFO(FUNC_ADPT_FMT": order:%d, role:%d\n",
-+				FUNC_ADPT_ARG(iface), pmccadapriv->order, pmccadapriv->role);
-+			RTW_INFO(FUNC_ADPT_FMT": mcc duration:%d, target tx bytes:%d\n",
-+				FUNC_ADPT_ARG(iface), pmccadapriv->mcc_duration, pmccadapriv->mcc_target_tx_bytes_to_port);
-+			RTW_INFO(FUNC_ADPT_FMT": mgmt queue macid:%d, bitmap:0x%02x\n",
-+				FUNC_ADPT_ARG(iface), pmccadapriv->mgmt_queue_macid, pmccadapriv->mcc_macid_bitmap);
-+			RTW_INFO("********************\n");
-+		}
-+		
-+	}
-+exit:
-+	return need_update;
-+}
-+
-+static u8 rtw_hal_decide_mcc_role(PADAPTER padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	_adapter *iface = NULL;
-+	struct mcc_adapter_priv *pmccadapriv = NULL;
-+	struct wifidirect_info *pwdinfo = NULL;
-+	struct mlme_priv *pmlmepriv = NULL;
-+	u8 ret = _SUCCESS, i = 0;
-+	u8 order = 1;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface == NULL)
-+			continue;
-+
-+		pmccadapriv = &iface->mcc_adapterpriv;
-+		pwdinfo = &iface->wdinfo;
-+
-+		if (MLME_IS_GO(iface))
-+			pmccadapriv->role = MCC_ROLE_GO;
-+		else if (MLME_IS_AP(iface))
-+			pmccadapriv->role = MCC_ROLE_AP;
-+		else if (MLME_IS_GC(iface))
-+			pmccadapriv->role = MCC_ROLE_GC;
-+		else if (MLME_IS_STA(iface)) {
-+			if (MLME_IS_LINKING(iface) || MLME_IS_ASOC(iface))
-+				pmccadapriv->role = MCC_ROLE_STA;
-+			else {
-+				/* bypass non-linked/non-linking interface */
-+				RTW_INFO(FUNC_ADPT_FMT" mlme state:0x%2x\n",
-+					FUNC_ADPT_ARG(iface), MLME_STATE(iface));
-+				continue;
-+			}
-+		} else {
-+			/* bypass non-linked/non-linking interface */
-+			RTW_INFO(FUNC_ADPT_FMT" P2P Role:%d, mlme state:0x%2x\n",
-+				FUNC_ADPT_ARG(iface), pwdinfo->role, MLME_STATE(iface));
-+			continue;
-+		}
-+
-+		if (padapter == iface) {
-+			/* current adapter is order 0 */
-+			rtw_hal_config_mcc_role_setting(iface, 0);
-+		} else {
-+			rtw_hal_config_mcc_role_setting(iface, order);
-+			order ++;
-+		}
-+	}
-+
-+	rtw_hal_mcc_update_timing_parameters(padapter, _TRUE);
-+
-+	return ret;
-+}
-+
-+static void rtw_hal_construct_CTS(PADAPTER padapter, u8 *pframe, u32 *pLength)
-+{
-+	u8 broadcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+
-+	/* frame type, length = 1*/
-+	set_frame_sub_type(pframe, WIFI_RTS);
-+
-+	/* frame control flag, length = 1 */
-+	*(pframe + 1) = 0;
-+
-+	/* frame duration, length = 2 */
-+	*(pframe + 2) = 0x00;
-+	*(pframe + 3) = 0x78;
-+
-+	/* frame recvaddr, length = 6 */
-+	_rtw_memcpy((pframe + 4), broadcast_addr, ETH_ALEN);
-+	_rtw_memcpy((pframe + 4 + ETH_ALEN), adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy((pframe + 4 + ETH_ALEN*2), adapter_mac_addr(padapter), ETH_ALEN);
-+	*pLength = 22;
-+}
-+
-+/* avoid wrong information for power limit */
-+void rtw_hal_mcc_upadate_chnl_bw(_adapter *padapter, u8 ch, u8 ch_offset, u8 bw, u8 print)
-+{
-+
-+	u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	PHAL_DATA_TYPE	hal = GET_HAL_DATA(padapter);
-+	u8 cch_160, cch_80, cch_40, cch_20;
-+
-+	center_ch = rtw_get_center_ch(ch, bw, ch_offset);
-+
-+	if (bw == CHANNEL_WIDTH_80) {
-+		if (center_ch > ch)
-+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
-+		else if (center_ch < ch)
-+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
-+		else
-+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	}
-+
-+	/* set Channel */
-+	/* saved channel/bw info */
-+	rtw_set_oper_ch(padapter, ch);
-+	rtw_set_oper_bw(padapter, bw);
-+	rtw_set_oper_choffset(padapter, ch_offset);
-+
-+	cch_80 = bw == CHANNEL_WIDTH_80 ? center_ch : 0;
-+	cch_40 = bw == CHANNEL_WIDTH_40 ? center_ch : 0;
-+	cch_20 = bw == CHANNEL_WIDTH_20 ? center_ch : 0;
-+
-+	if (cch_80 != 0)
-+		cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, chnl_offset80);
-+	if (cch_40 != 0)
-+		cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, ch_offset);
-+
-+
-+	hal->cch_80 = cch_80;
-+	hal->cch_40 = cch_40;
-+	hal->cch_20 = cch_20;
-+	hal->current_channel = center_ch;
-+	hal->CurrentCenterFrequencyIndex1 = center_ch;
-+	hal->current_channel_bw = bw;
-+	hal->nCur40MhzPrimeSC = ch_offset;
-+	hal->nCur80MhzPrimeSC = chnl_offset80;
-+	hal->current_band_type = ch > 14 ? BAND_ON_5G:BAND_ON_2_4G;
-+
-+	if (print) {
-+		RTW_INFO(FUNC_ADPT_FMT" cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u), band:%s\n"
-+			, FUNC_ADPT_ARG(padapter), center_ch, ch_width_str(bw)
-+			, ch_offset, chnl_offset80
-+			, hal->cch_80, hal->cch_40, hal->cch_20
-+			, band_str(hal->current_band_type));
-+	}
-+}
-+
-+u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index,
-+	u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num)
-+{
-+	u32 len = 0;
-+	_adapter *iface = NULL;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
-+	struct mlme_ext_info *pmlmeinfo = NULL;
-+	struct mlme_ext_priv *pmlmeext = NULL;
-+	struct hal_com_data *hal = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	struct mcc_adapter_priv *mccadapriv = NULL;
-+#if defined(CONFIG_RTL8822C)
-+	struct dm_struct *phydm = adapter_to_phydm(adapter);
-+	struct txagc_table_8822c tab;
-+	u8 agc_buff[2][NUM_RATE_AC_2SS]; /* tatol 0x40 rate index for PATH A/B */
-+#endif
-+	
-+	u8 ret = _SUCCESS, i = 0, j  =0, order = 0, CurtPktPageNum = 0;
-+	u8 *start = NULL;
-+	u8 path = RF_PATH_A;
-+
-+	if (page_num) {
-+#ifdef CONFIG_MCC_MODE_V2
-+		if (!hal->RegIQKFWOffload)
-+			RTW_WARN("[MCC] must enable FW IQK for New IC\n");
-+#endif /* CONFIG_MCC_MODE_V2 */
-+		*total_page_num += (2 * MAX_MCC_NUM+ 1);
-+		RTW_INFO("[MCC] allocate mcc rsvd page num = %d\n", *total_page_num);
-+		goto exit;
-+	}
-+
-+	/* check proccess mcc start setting */
-+	if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_PROCESS_MCC_START_SETTING)) {
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface == NULL)
-+			continue;
-+
-+		mccadapriv = &iface->mcc_adapterpriv;
-+		if (mccadapriv->role == MCC_ROLE_MAX)
-+			continue;
-+
-+		order = mccadapriv->order;
-+		pmccobjpriv->mcc_loc_rsvd_paga[order] = *total_page_num;
-+
-+		switch (mccadapriv->role) {
-+		case MCC_ROLE_STA:
-+		case MCC_ROLE_GC:
-+			/* Build NULL DATA */
-+			RTW_INFO("LocNull(order:%d): %d\n"
-+				, order, pmccobjpriv->mcc_loc_rsvd_paga[order]);
-+			len = 0;
-+
-+			rtw_hal_construct_NullFunctionData(iface
-+				, &pframe[*index], &len, _FALSE, 0, 0, _FALSE);
-+			rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc],
-+				len, _FALSE, _FALSE, _FALSE);
-+
-+			CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size);
-+			*total_page_num += CurtPktPageNum;
-+			*index += (CurtPktPageNum * page_size);
-+			RSVD_PAGE_CFG("LocNull", CurtPktPageNum, *total_page_num, *index);
-+			break;
-+		case MCC_ROLE_AP:
-+			/* Bulid CTS */
-+			RTW_INFO("LocCTS(order:%d): %d\n"
-+				, order, pmccobjpriv->mcc_loc_rsvd_paga[order]);
-+
-+			len = 0;
-+			rtw_hal_construct_CTS(iface, &pframe[*index], &len);
-+			rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc],
-+				len, _FALSE, _FALSE, _FALSE);
-+
-+			CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size);
-+			*total_page_num += CurtPktPageNum;
-+			*index += (CurtPktPageNum * page_size);
-+			RSVD_PAGE_CFG("LocCTS", CurtPktPageNum, *total_page_num, *index);
-+			break;
-+		case MCC_ROLE_GO:
-+		/* To DO */
-+			break;
-+		default:
-+			RTW_INFO(FUNC_ADPT_FMT": unknown role = %d\n"
-+				, FUNC_ADPT_ARG(iface), mccadapriv->role);
-+			break;
-+		}
-+	}
-+
-+	for (i = 0; i < MAX_MCC_NUM; i++) {
-+		u8 center_ch = 0, ch = 0, bw = 0, bw_offset = 0;
-+		BAND_TYPE band = BAND_MAX;
-+		u8 power_index = 0;
-+		u8 rate_array_sz = 0;
-+		u8 *rates = NULL;
-+		u8 rate = 0;
-+		u8 shift = 0;
-+		u32 power_index_4bytes = 0;
-+		u8 total_rate = 0;
-+		u8 *total_rate_offset = NULL;
-+
-+		iface = pmccobjpriv->iface[i];
-+		pmlmeext = &iface->mlmeextpriv;
-+		ch = pmlmeext->cur_channel;
-+		bw = pmlmeext->cur_bwmode;
-+		bw_offset = pmlmeext->cur_ch_offset;
-+		center_ch = rtw_get_center_ch(ch, bw, bw_offset);
-+		band = center_ch <= 14 ? BAND_ON_2_4G : BAND_ON_5G;
-+		rtw_hal_mcc_upadate_chnl_bw(iface, ch, bw_offset, bw, _TRUE);
-+
-+		start = &pframe[*index - tx_desc];
-+		_rtw_memset(start, 0, page_size);
-+		pmccobjpriv->mcc_pwr_idx_rsvd_page[i] = *total_page_num;
-+		RTW_INFO(ADPT_FMT" order:%d, pwr_idx_rsvd_page location[%d]: %d\n",
-+			ADPT_ARG(iface), mccadapriv->order,
-+			i, pmccobjpriv->mcc_pwr_idx_rsvd_page[i]);
-+
-+		total_rate_offset = start;
-+#if !defined(CONFIG_RTL8822C)			
-+		for (path = RF_PATH_A; path < hal_spec->rf_reg_path_num; ++path) {
-+			total_rate = 0;
-+			/* PATH A for 0~63 byte, PATH B for 64~127 byte*/
-+			if (path == RF_PATH_A)
-+				start = total_rate_offset + 1;
-+			else if (path == RF_PATH_B)
-+				start = total_rate_offset + 64;
-+			else {
-+				RTW_INFO("[MCC] %s: unknow RF PATH(%d)\n", __func__, path);
-+				break;
-+			}
-+
-+			/* CCK */
-+			if (ch <= 14) {
-+				rate_array_sz = rates_by_sections[CCK].rate_num;
-+				rates = rates_by_sections[CCK].rates;
-+				for (j = 0; j < rate_array_sz; ++j) {
-+					power_index = phy_get_tx_power_index_ex(iface, path, CCK, rates[j], bw, band, center_ch, ch);
-+					rate = phy_get_rate_idx_of_txpwr_by_rate(rates[j]);
-+
-+					shift = rate % 4;
-+					if (shift == 0) {
-+						*start = rate;
-+						start++;
-+						total_rate++;
-+
-+						#ifdef DBG_PWR_IDX_RSVD_PAGE
-+						RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
-+							ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
-+							center_ch, MGN_RATE_STR(rates[j]), power_index);
-+						#endif
-+					}
-+
-+					*start = power_index;
-+					start++;
-+
-+					#ifdef DBG_PWR_IDX_RSVD_PAGE
-+					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
-+						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
-+						center_ch, MGN_RATE_STR(rates[j]), power_index);
-+
-+					
-+					shift = rate % 4;
-+					power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
-+					if (shift == 3) {
-+						rate = rate - 3;
-+						RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
-+						power_index_4bytes = 0;
-+						total_rate++;
-+					}
-+					#endif
-+						
-+				}
-+			}
-+
-+			/* OFDM */
-+			rate_array_sz = rates_by_sections[OFDM].rate_num;
-+			rates = rates_by_sections[OFDM].rates;
-+			for (j = 0; j < rate_array_sz; ++j) {
-+				power_index = phy_get_tx_power_index_ex(iface, path, OFDM, rates[j], bw, band, center_ch, ch);
-+				rate = phy_get_rate_idx_of_txpwr_by_rate(rates[j]);
-+
-+				shift = rate % 4;
-+				if (shift == 0) {
-+					*start = rate;
-+					start++;
-+					total_rate++;
-+
-+					#ifdef DBG_PWR_IDX_RSVD_PAGE
-+					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
-+						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
-+						center_ch, MGN_RATE_STR(rates[j]), power_index);
-+					#endif
-+
-+				}
-+
-+				*start = power_index;
-+				start++;
-+
-+				#ifdef DBG_PWR_IDX_RSVD_PAGE
-+				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
-+					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
-+					center_ch, MGN_RATE_STR(rates[j]), power_index);
-+
-+				shift = rate % 4;
-+				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
-+				if (shift == 3) {
-+					rate = rate - 3;
-+					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
-+					power_index_4bytes = 0;
-+					total_rate++;
-+				}
-+				#endif
-+			}
-+
-+			/* HT_MCS0_MCS7 */
-+			rate_array_sz = rates_by_sections[HT_MCS0_MCS7].rate_num;
-+			rates = rates_by_sections[HT_MCS0_MCS7].rates;
-+			for (j = 0; j < rate_array_sz; ++j) {
-+				power_index = phy_get_tx_power_index_ex(iface, path, HT_1SS, rates[j], bw, band, center_ch, ch);
-+				rate = phy_get_rate_idx_of_txpwr_by_rate(rates[j]);
-+
-+				shift = rate % 4;
-+				if (shift == 0) {
-+					*start = rate;
-+					start++;
-+					total_rate++;
-+
-+					#ifdef DBG_PWR_IDX_RSVD_PAGE
-+					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
-+						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
-+						center_ch, MGN_RATE_STR(rates[j]), power_index);
-+					#endif
-+
-+				}
-+
-+				*start = power_index;
-+				start++;
-+
-+				#ifdef DBG_PWR_IDX_RSVD_PAGE
-+				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
-+					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
-+					center_ch, MGN_RATE_STR(rates[j]), power_index);
-+
-+				shift = rate % 4;
-+				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
-+				if (shift == 3) {
-+					rate = rate - 3;
-+					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
-+					power_index_4bytes = 0;
-+					total_rate++;
-+				}
-+				#endif
-+			}
-+
-+			/* HT_MCS8_MCS15 */
-+			rate_array_sz = rates_by_sections[HT_MCS8_MCS15].rate_num;
-+			rates = rates_by_sections[HT_MCS8_MCS15].rates;
-+			for (j = 0; j < rate_array_sz; ++j) {
-+				power_index = phy_get_tx_power_index_ex(iface, path, HT_2SS, rates[j], bw, band, center_ch, ch);
-+				rate = phy_get_rate_idx_of_txpwr_by_rate(rates[j]);
-+
-+				shift = rate % 4;
-+				if (shift == 0) {
-+					*start = rate;
-+					start++;
-+					total_rate++;
-+
-+					#ifdef DBG_PWR_IDX_RSVD_PAGE
-+					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
-+						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
-+						center_ch, MGN_RATE_STR(rates[j]), power_index);
-+					#endif
-+				}
-+
-+				*start = power_index;
-+				start++;
-+
-+				#ifdef DBG_PWR_IDX_RSVD_PAGE
-+				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
-+					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
-+					center_ch, MGN_RATE_STR(rates[j]), power_index);
-+				
-+				shift = rate % 4;
-+				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
-+				if (shift == 3) {
-+					rate = rate - 3;
-+					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
-+					power_index_4bytes = 0;
-+					total_rate++;
-+				}
-+				#endif
-+			}
-+
-+			/* VHT_1SSMCS0_1SSMCS9 */
-+			rate_array_sz = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rate_num;
-+			rates = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rates;
-+			for (j = 0; j < rate_array_sz; ++j) {
-+				power_index = phy_get_tx_power_index_ex(iface, path, VHT_1SS, rates[j], bw, band, center_ch, ch);
-+				rate = phy_get_rate_idx_of_txpwr_by_rate(rates[j]);
-+
-+				shift = rate % 4;
-+				if (shift == 0) {
-+					*start = rate;
-+					start++;
-+					total_rate++;
-+					#ifdef DBG_PWR_IDX_RSVD_PAGE
-+					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:0x%02x\n",
-+						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
-+						center_ch, MGN_RATE_STR(rates[j]), power_index);
-+					#endif
-+				}
-+				*start = power_index;
-+				start++;
-+				#ifdef DBG_PWR_IDX_RSVD_PAGE
-+				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
-+					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
-+					center_ch, MGN_RATE_STR(rates[j]), power_index);
-+
-+				shift = rate % 4;
-+				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
-+				if (shift == 3) {
-+					rate = rate - 3;
-+					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
-+					power_index_4bytes = 0;
-+					total_rate++;
-+				}
-+				#endif
-+			}
-+
-+			/* VHT_2SSMCS0_2SSMCS9 */
-+			rate_array_sz = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rate_num;
-+			rates = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rates;
-+			for (j = 0; j < rate_array_sz; ++j) {
-+				power_index = phy_get_tx_power_index_ex(iface, path, VHT_2SS, rates[j], bw, band, center_ch, ch);
-+				rate = phy_get_rate_idx_of_txpwr_by_rate(rates[j]);
-+
-+				shift = rate % 4;
-+				if (shift == 0) {
-+					*start = rate;
-+					start++;
-+					total_rate++;
-+					#ifdef DBG_PWR_IDX_RSVD_PAGE
-+					RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
-+						ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
-+						center_ch, MGN_RATE_STR(rates[j]), power_index);
-+					#endif
-+				}
-+				*start = power_index;
-+				start++;
-+				#ifdef DBG_PWR_IDX_RSVD_PAGE
-+				RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
-+					ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
-+					center_ch, MGN_RATE_STR(rates[j]), power_index);
-+
-+				shift = rate % 4;
-+				power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
-+				if (shift == 3) {
-+					rate = rate - 3;
-+					RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
-+					power_index_4bytes = 0;
-+						total_rate++;
-+				}
-+				#endif
-+			}
-+				
-+		}
-+		/*  total rate store in offset 0 */
-+		*total_rate_offset = total_rate;
-+
-+#ifdef DBG_PWR_IDX_RSVD_PAGE
-+			RTW_INFO("total_rate=%d\n", total_rate);
-+			RTW_INFO(" ======================="ADPT_FMT"===========================\n", ADPT_ARG(iface));
-+			RTW_INFO_DUMP("\n", total_rate_offset, 128);
-+			RTW_INFO(" ==================================================\n");
-+#endif
-+
-+			CurtPktPageNum = 1;
-+			*total_page_num += CurtPktPageNum;
-+			*index += (CurtPktPageNum * page_size);
-+			RSVD_PAGE_CFG("mcc_pwr_idx_rsvd_page", CurtPktPageNum, *total_page_num, *index);
-+#else /* 8822C */
-+			for (path = RF_PATH_A; path < hal_spec->rf_reg_path_num; ++path) {
-+				/* CCK */
-+				if (ch <= 14) {
-+					rate_array_sz = rates_by_sections[CCK].rate_num;
-+					rates = rates_by_sections[CCK].rates;
-+					for (j = 0; j < rate_array_sz; ++j) {
-+						power_index = phy_get_tx_power_index_ex(iface, path, CCK, rates[j], bw, band, center_ch, ch);
-+						rate = phy_get_rate_idx_of_txpwr_by_rate(rates[j]);
-+						agc_buff[path][rate] = power_index;
-+					}
-+				}
-+
-+				/* OFDM */
-+				rate_array_sz = rates_by_sections[OFDM].rate_num;
-+				rates = rates_by_sections[OFDM].rates;
-+				for (j = 0; j < rate_array_sz; ++j) {
-+					power_index = phy_get_tx_power_index_ex(iface, path, OFDM, rates[j], bw, band, center_ch, ch);
-+					rate = phy_get_rate_idx_of_txpwr_by_rate(rates[j]);
-+					agc_buff[path][rate] = power_index;
-+				}
-+				/* HT */
-+				rate_array_sz = rates_by_sections[HT_MCS0_MCS7].rate_num;
-+				rates = rates_by_sections[HT_MCS0_MCS7].rates;
-+				for (j = 0; j < rate_array_sz; ++j) {
-+					power_index = phy_get_tx_power_index_ex(iface, path, HT_1SS, rates[j], bw, band, center_ch, ch);
-+					rate = phy_get_rate_idx_of_txpwr_by_rate(rates[j]);
-+					agc_buff[path][rate] = power_index;
-+				}
-+
-+				rate_array_sz = rates_by_sections[HT_MCS8_MCS15].rate_num;
-+				rates = rates_by_sections[HT_MCS8_MCS15].rates;
-+				for (j = 0; j < rate_array_sz; ++j) {
-+					power_index = phy_get_tx_power_index_ex(iface, path, HT_2SS, rates[j], bw, band, center_ch, ch);
-+					rate = phy_get_rate_idx_of_txpwr_by_rate(rates[j]);
-+					agc_buff[path][rate] = power_index;
-+				}
-+				/* VHT */
-+				rate_array_sz = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rate_num;
-+				rates = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rates;
-+				for (j = 0; j < rate_array_sz; ++j) {
-+					power_index = phy_get_tx_power_index_ex(iface, path, VHT_1SS, rates[j], bw, band, center_ch, ch);
-+					rate = phy_get_rate_idx_of_txpwr_by_rate(rates[j]);
-+					agc_buff[path][rate] = power_index;
-+				}
-+
-+				rate_array_sz = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rate_num;
-+				rates = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rates;
-+				for (j = 0; j < rate_array_sz; ++j) {
-+					power_index = phy_get_tx_power_index_ex(iface, path, VHT_2SS, rates[j], bw, band, center_ch, ch);
-+					rate = phy_get_rate_idx_of_txpwr_by_rate(rates[j]);
-+					agc_buff[path][rate] = power_index;
-+				}
-+			}
-+			phydm_get_txagc_ref_and_diff_8822c(phydm, agc_buff, NUM_RATE_AC_2SS, &tab);
-+			*start = tab.ref_pow_cck[0];
-+			start++;
-+			*start = tab.ref_pow_cck[1];
-+			start++;
-+			*start = tab.ref_pow_ofdm[0];
-+			start++;
-+			*start = tab.ref_pow_ofdm[1];
-+			start++;
-+			_rtw_memcpy(start, tab.diff_t, sizeof(tab.diff_t));
-+			CurtPktPageNum = 1;
-+			*total_page_num += CurtPktPageNum;
-+			*index += (CurtPktPageNum * page_size);
-+			RSVD_PAGE_CFG("mcc_pwr_idx_rsvd_page", CurtPktPageNum, *total_page_num, *index);
-+			#ifdef DBG_PWR_IDX_RSVD_PAGE
-+			if (1) {
-+				u8 path_idx;
-+				for (path_idx = 0; path_idx < 2; path_idx++) {
-+					for (j = 0; j < NUM_RATE_AC_2SS; j++) 
-+						RTW_INFO("agc_buff[%d][%d]=%x\n", i, j, agc_buff[i][j]);
-+				}
-+				RTW_INFO("tab->ref_pow_cck[0]=%x\n", tab.ref_pow_cck[0]);
-+				RTW_INFO("tab->ref_pow_cck[1]=%x\n", tab.ref_pow_cck[1]);
-+				RTW_INFO("tab->ref_pow_ofdm[0]=%x\n", tab.ref_pow_ofdm[0]);
-+				RTW_INFO("tab->ref_pow_ofdm[1]=%x\n", tab.ref_pow_ofdm[1]);
-+				RTW_INFO_DUMP("diff_t ", tab.diff_t, NUM_RATE_AC_2SS);
-+				RTW_INFO_DUMP("tab ", (u8 *)&tab, sizeof(tab));
-+			}
-+			#endif
-+			
-+#endif
-+		}
-+
-+exit:
-+	return ret;
-+}
-+
-+/*
-+* 1. Download MCC rsvd page
-+* 2. Re-Download beacon after download rsvd page
-+*/
-+static void rtw_hal_set_fw_mcc_rsvd_page(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	PADAPTER port0_iface = dvobj_get_port0_adapter(dvobj);
-+	PADAPTER iface = NULL;
-+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
-+	u8 mstatus = RT_MEDIA_CONNECT, i = 0;
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+
-+	rtw_hal_set_hwreg(port0_iface, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus));
-+
-+#ifdef CONFIG_AP_MODE
-+	/* Re-Download beacon */
-+	for (i = 0; i < MAX_MCC_NUM; i++) {
-+		iface = pmccobjpriv->iface[i];
-+		if (iface == NULL)
-+			continue;
-+
-+		pmccadapriv = &iface->mcc_adapterpriv;
-+
-+		if (pmccadapriv->role == MCC_ROLE_AP
-+			|| pmccadapriv->role == MCC_ROLE_GO) {
-+			tx_beacon_hdl(iface, NULL);
-+		}
-+	}
-+#endif
-+}
-+
-+static void rtw_hal_set_mcc_rsvdpage_cmd(_adapter *padapter)
-+{
-+	u8 cmd[H2C_MCC_LOCATION_LEN] = {0}, i = 0, order = 0;
-+	_adapter *iface = NULL;
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
-+
-+	SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(cmd, _TRUE);
-+	SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(cmd, hal_spec->rf_reg_path_num);
-+	for (order = 0; order < MAX_MCC_NUM; order++) {
-+		iface = pmccobjpriv->iface[i];
-+
-+		SET_H2CCMD_MCC_RSVDPAGE_LOC((cmd + order), pmccobjpriv->mcc_loc_rsvd_paga[order]);
-+		SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC ((cmd + order), pmccobjpriv->mcc_pwr_idx_rsvd_page[order]);
-+	}
-+
-+#ifdef CONFIG_MCC_MODE_DEBUG
-+	RTW_INFO("=========================\n");
-+	RTW_INFO("MCC RSVD PAGE LOC:\n");
-+	for (i = 0; i < H2C_MCC_LOCATION_LEN; i++)
-+		pr_dbg("0x%x ", cmd[i]);
-+	pr_dbg("\n");
-+	RTW_INFO("=========================\n");
-+#endif /* CONFIG_MCC_MODE_DEBUG */
-+
-+	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_LOCATION, H2C_MCC_LOCATION_LEN, cmd);
-+}
-+
-+static void rtw_hal_set_mcc_time_setting_cmd(PADAPTER padapter)
-+{
-+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
-+	u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0};
-+	u8 fw_eable = 1;
-+	u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME;
-+	u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
-+	u8 ap_num = DEV_AP_NUM(dvobj);	
-+
-+	if (starting_ap_num == 0 && ap_num == 0)
-+		/* For STA+GC/STA+STA, TSF of GC/STA does not need to sync from TSF of other STA/GC */
-+		fw_eable = 0;
-+	else
-+		/* Only for STA+GO/STA+AP, TSF of AP/GO need to sync from TSF of STA */
-+		fw_eable = 1;
-+
-+	if (fw_eable == 1) {
-+		PADAPTER order0_iface = NULL;
-+		PADAPTER order1_iface = NULL;
-+		u8 policy_idx = mccobjpriv->policy_index;
-+		u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
-+		u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
-+		u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX];
-+		u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX];
-+		u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX];
-+		enum _hw_port tsf_bsae_port = MAX_HW_PORT;
-+		enum _hw_port tsf_sync_port = MAX_HW_PORT;
-+		order0_iface = mccobjpriv->iface[0];
-+		order1_iface = mccobjpriv->iface[1];
-+
-+		tsf_bsae_port = rtw_hal_get_port(order1_iface);
-+		tsf_sync_port = rtw_hal_get_port(order0_iface);
-+		
-+		/* FW set enable */
-+		SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, fw_eable);
-+		/* TSF Sync offset */
-+		SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset);
-+		/* start time offset */
-+		SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0));
-+		/* interval */
-+		SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
-+		/* Early time to inform driver by C2H before switch channel */
-+		SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
-+		/* Port0 sync from Port1, not support multi-port */
-+		SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, tsf_bsae_port);
-+		SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, tsf_sync_port);
-+	} else {
-+		/* start time offset */
-+		SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, mccobjpriv->start_time);
-+		/* interval */
-+		SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, mccobjpriv->interval);
-+		/* Early time to inform driver by C2H before switch channel */
-+		SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
-+	}
-+
-+#ifdef CONFIG_MCC_MODE_DEBUG
-+	{
-+		u8 i = 0;
-+
-+		RTW_INFO("=========================\n");
-+		RTW_INFO("NoA:\n");
-+		for (i = 0; i < H2C_MCC_TIME_SETTING_LEN; i++)
-+			pr_dbg("0x%x ", cmd[i]);
-+		pr_dbg("\n");
-+		RTW_INFO("=========================\n");
-+	}
-+#endif /* CONFIG_MCC_MODE_DEBUG */
-+
-+	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd);
-+}
-+
-+#ifndef CONFIG_MCC_MODE_V2
-+static void rtw_hal_set_mcc_IQK_offload_cmd(PADAPTER padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
-+	struct mcc_adapter_priv *pmccadapriv = NULL;
-+	_adapter *iface = NULL;
-+	u8 cmd[H2C_MCC_IQK_PARAM_LEN] = {0}, bready = 0, i = 0, order = 0;
-+	u16 TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0;
-+	u8 total_rf_path = GET_HAL_SPEC(padapter)->rf_reg_path_num;
-+	u8 rf_path_idx = 0, last_order = MAX_MCC_NUM - 1, last_rf_path_index = total_rf_path - 1;
-+
-+	/* by order, last order & last_rf_path_index must set ready bit = 1 */
-+	for (i = 0; i < MAX_MCC_NUM; i++) {
-+		iface = pmccobjpriv->iface[i];
-+		if (iface == NULL)
-+			continue;
-+
-+		pmccadapriv = &iface->mcc_adapterpriv;
-+		order = pmccadapriv->order;
-+
-+		for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx ++) {
-+
-+			_rtw_memset(cmd, 0, H2C_MCC_IQK_PARAM_LEN);
-+			TX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_X & 0x7ff;/* [10:0]  */
-+			TX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_Y & 0x7ff;/* [10:0]  */
-+			RX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_X & 0x3ff;/* [9:0]  */
-+			RX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_Y & 0x3ff;/* [9:0]  */
-+
-+			/* ready or not */
-+			if (order == last_order && rf_path_idx == last_rf_path_index)
-+				bready = 1;
-+			else
-+				bready = 0;
-+
-+			SET_H2CCMD_MCC_IQK_READY(cmd, bready);
-+			SET_H2CCMD_MCC_IQK_ORDER(cmd, order);
-+			SET_H2CCMD_MCC_IQK_PATH(cmd, rf_path_idx);
-+
-+			/* fill RX_X[7:0] to (cmd+1)[7:0] bitlen=8 */
-+			SET_H2CCMD_MCC_IQK_RX_L(cmd, (u8)(RX_X & 0xff));
-+			/* fill RX_X[9:8] to (cmd+2)[1:0] bitlen=2 */
-+			SET_H2CCMD_MCC_IQK_RX_M1(cmd, (u8)((RX_X >> 8) & 0x03));
-+			/* fill RX_Y[5:0] to (cmd+2)[7:2] bitlen=6 */
-+			SET_H2CCMD_MCC_IQK_RX_M2(cmd, (u8)(RX_Y & 0x3f));
-+			/* fill RX_Y[9:6] to (cmd+3)[3:0] bitlen=4 */
-+			SET_H2CCMD_MCC_IQK_RX_H(cmd, (u8)((RX_Y >> 6) & 0x0f));
-+
-+
-+			/* fill TX_X[7:0] to (cmd+4)[7:0] bitlen=8 */
-+			SET_H2CCMD_MCC_IQK_TX_L(cmd, (u8)(TX_X & 0xff));
-+			/* fill TX_X[10:8] to (cmd+5)[2:0] bitlen=3 */
-+			SET_H2CCMD_MCC_IQK_TX_M1(cmd, (u8)((TX_X >> 8) & 0x07));
-+			/* fill TX_Y[4:0] to (cmd+5)[7:3] bitlen=5 */
-+			SET_H2CCMD_MCC_IQK_TX_M2(cmd, (u8)(TX_Y & 0x1f));
-+			/* fill TX_Y[10:5] to (cmd+6)[5:0] bitlen=6 */
-+			SET_H2CCMD_MCC_IQK_TX_H(cmd, (u8)((TX_Y >> 5) & 0x3f));
-+
-+#ifdef CONFIG_MCC_MODE_DEBUG
-+			RTW_INFO("=========================\n");
-+			RTW_INFO(FUNC_ADPT_FMT" IQK:\n", FUNC_ADPT_ARG(iface));
-+			RTW_INFO("TX_X: 0x%02x\n", TX_X);
-+			RTW_INFO("TX_Y: 0x%02x\n", TX_Y);
-+			RTW_INFO("RX_X: 0x%02x\n", RX_X);
-+			RTW_INFO("RX_Y: 0x%02x\n", RX_Y);
-+			RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
-+			RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
-+			RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
-+			RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
-+			RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
-+			RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
-+			RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
-+			RTW_INFO("=========================\n");
-+#endif /* CONFIG_MCC_MODE_DEBUG */
-+
-+			rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_IQK_PARAM, H2C_MCC_IQK_PARAM_LEN, cmd);
-+		}
-+	}
-+}
-+#endif
-+
-+
-+static void rtw_hal_set_mcc_macid_cmd(PADAPTER padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_adapter_priv *pmccadapriv = NULL;
-+	_adapter *iface = NULL;
-+	u8 cmd[H2C_MCC_MACID_BITMAP_LEN] = {0}, i = 0, order = 0;
-+	u16 bitmap = 0;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface == NULL)
-+			continue;
-+
-+		pmccadapriv = &iface->mcc_adapterpriv;
-+		if (pmccadapriv->role == MCC_ROLE_MAX)
-+			continue;
-+		
-+		order = pmccadapriv->order;
-+		bitmap = pmccadapriv->mcc_macid_bitmap;
-+
-+		if (order >= (H2C_MCC_MACID_BITMAP_LEN/2)) {
-+			RTW_INFO(FUNC_ADPT_FMT" only support 3 interface at most(%d)\n"
-+				, FUNC_ADPT_ARG(padapter), order);
-+			continue;
-+		}
-+		SET_H2CCMD_MCC_MACID_BITMAP_L((cmd + order * 2), (u8)(bitmap & 0xff));
-+		SET_H2CCMD_MCC_MACID_BITMAP_H((cmd + order * 2), (u8)((bitmap >> 8) & 0xff));
-+	}
-+
-+#ifdef CONFIG_MCC_MODE_DEBUG
-+	RTW_INFO("=========================\n");
-+	RTW_INFO("MACID BITMAP: ");
-+	for (i = 0; i < H2C_MCC_MACID_BITMAP_LEN; i++)
-+		printk("0x%x ", cmd[i]);
-+	printk("\n");
-+	RTW_INFO("=========================\n");
-+#endif /* CONFIG_MCC_MODE_DEBUG */
-+	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_MACID_BITMAP, H2C_MCC_MACID_BITMAP_LEN, cmd);
-+}
-+
-+#ifdef CONFIG_MCC_MODE_V2
-+static u8 get_pri_ch_idx_by_adapter(u8 center_ch, u8 channel, u8 bw, u8 ch_offset40)
-+{
-+	u8 pri_ch_idx = 0, chnl_offset80 = 0;
-+
-+	if (bw == CHANNEL_WIDTH_80) {
-+		if (center_ch > channel)
-+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
-+		else if (center_ch < channel)
-+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
-+		else
-+			chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	}
-+
-+	if (bw == CHANNEL_WIDTH_80) {
-+		/* primary channel is at lower subband of 80MHz & 40MHz */
-+		if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER))
-+			pri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
-+		/* primary channel is at lower subband of 80MHz & upper subband of 40MHz */
-+		else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER))
-+			pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
-+		/* primary channel is at upper subband of 80MHz & lower subband of 40MHz */
-+		else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER))
-+			pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
-+		/* primary channel is at upper subband of 80MHz & upper subband of 40MHz */
-+		else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER))
-+			pri_ch_idx = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
-+		else {
-+			if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER)
-+				pri_ch_idx = VHT_DATA_SC_40_LOWER_OF_80MHZ;
-+			else if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER)
-+				pri_ch_idx = VHT_DATA_SC_40_UPPER_OF_80MHZ;
-+			else
-+				RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
-+		}
-+	} else if (bw == CHANNEL_WIDTH_40) {
-+		/* primary channel is at upper subband of 40MHz */
-+		if (ch_offset40== HAL_PRIME_CHNL_OFFSET_UPPER)
-+			pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
-+		/* primary channel is at lower subband of 40MHz */
-+		else if (ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER)
-+			pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
-+		else
-+			RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
-+	}
-+
-+	return  pri_ch_idx;
-+}
-+
-+static void rtw_hal_set_mcc_ctrl_cmd_v2(PADAPTER padapter, u8 stop)
-+{
-+	u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0;
-+	u8 order = 0, totalnum = 0;
-+	u8 center_ch = 0, pri_ch_idx = 0, bw = 0;
-+	u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0;
-+	u8 dis_sw_retry = 0, null_early_time=2, tsfx = 0, update_parm = 0;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
-+	struct mcc_adapter_priv *mccadapriv = NULL;
-+	struct mlme_ext_priv *pmlmeext = NULL;
-+	struct mlme_ext_info *pmlmeinfo = NULL;
-+	_adapter *iface = NULL;
-+
-+	RTW_INFO(FUNC_ADPT_FMT": stop=%d\n", FUNC_ADPT_ARG(padapter), stop);
-+
-+	for (i = 0; i < MAX_MCC_NUM; i++) {
-+		iface = pmccobjpriv->iface[i];
-+		if (iface == NULL)
-+			continue;
-+
-+		if (stop) {
-+			if (iface != padapter)
-+				continue;
-+		}
-+
-+		mccadapriv = &iface->mcc_adapterpriv;
-+		order = mccadapriv->order;
-+
-+		if (!stop)
-+			totalnum = MAX_MCC_NUM;
-+		else
-+			totalnum = 0xff; /* 0xff means stop */
-+
-+		pmlmeext = &iface->mlmeextpriv;
-+		center_ch = rtw_get_center_ch(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
-+		pri_ch_idx = get_pri_ch_idx_by_adapter(center_ch, pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
-+		bw = pmlmeext->cur_bwmode;
-+		duration = mccadapriv->mcc_duration;
-+		role = mccadapriv->role;
-+
-+		incurch = _FALSE;
-+		dis_sw_retry = _TRUE;
-+
-+		/* STA/GC TX NULL data to inform AP/GC for ps mode */
-+		switch (role) {
-+		case MCC_ROLE_GO:
-+		case MCC_ROLE_AP:
-+			distxnull = MCC_DISABLE_TX_NULL;
-+			break;
-+		case MCC_ROLE_GC:
-+			set_channel_bwmode(iface, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
-+			distxnull = MCC_ENABLE_TX_NULL;
-+			break;
-+		case MCC_ROLE_STA:
-+			distxnull = MCC_ENABLE_TX_NULL;
-+			break;
-+		}
-+
-+		null_early_time = mccadapriv->null_early;
-+
-+		c2hrpt = MCC_C2H_REPORT_ALL_STATUS;
-+		tsfx = rtw_hal_get_port(iface);
-+		update_parm = 0;
-+
-+		SET_H2CCMD_MCC_CTRL_V2_ORDER(cmd, order);
-+		SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(cmd, totalnum);
-+		SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(cmd, center_ch);
-+		SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(cmd, pri_ch_idx);
-+		SET_H2CCMD_MCC_CTRL_V2_BW(cmd, bw);
-+		SET_H2CCMD_MCC_CTRL_V2_DURATION(cmd, duration);
-+		SET_H2CCMD_MCC_CTRL_V2_ROLE(cmd, role);
-+		SET_H2CCMD_MCC_CTRL_V2_INCURCH(cmd, incurch);
-+		SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(cmd, dis_sw_retry);
-+		SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(cmd, distxnull);
-+		SET_H2CCMD_MCC_CTRL_V2_C2HRPT(cmd, c2hrpt);
-+		SET_H2CCMD_MCC_CTRL_V2_TSFX(cmd, tsfx);
-+		SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(cmd, null_early_time);
-+		SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(cmd, update_parm);
-+
-+#ifdef CONFIG_MCC_MODE_DEBUG
-+		RTW_INFO("=========================\n");
-+		RTW_INFO(FUNC_ADPT_FMT" MCC INFO:\n", FUNC_ADPT_ARG(iface));
-+		RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
-+		RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
-+		RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
-+		RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
-+		RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
-+		RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
-+		RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
-+		RTW_INFO("=========================\n");
-+#endif /* CONFIG_MCC_MODE_DEBUG */
-+
-+		rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL_V2, H2C_MCC_CTRL_LEN, cmd);
-+	}
-+}
-+
-+#else
-+static void rtw_hal_set_mcc_ctrl_cmd_v1(PADAPTER padapter, u8 stop)
-+{
-+	u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0;
-+	u8 order = 0, totalnum = 0, chidx = 0, bw = 0, bw40sc = 0, bw80sc = 0;
-+	u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0, chscan = 0;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
-+	struct mcc_adapter_priv *mccadapriv = NULL;
-+	struct mlme_ext_priv *pmlmeext = NULL;
-+	struct mlme_ext_info *pmlmeinfo = NULL;
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+	_adapter *iface = NULL;
-+
-+	RTW_INFO(FUNC_ADPT_FMT": stop=%d\n", FUNC_ADPT_ARG(padapter), stop);
-+
-+	for (i = 0; i < MAX_MCC_NUM; i++) {
-+		iface = pmccobjpriv->iface[i];
-+		if (iface == NULL)
-+			continue;
-+
-+		if (stop) {
-+			if (iface != padapter)
-+				continue;
-+		}
-+
-+		mccadapriv = &iface->mcc_adapterpriv;
-+		order = mccadapriv->order;
-+
-+		if (!stop)
-+			totalnum = MAX_MCC_NUM;
-+		else
-+			totalnum = 0xff; /* 0xff means stop */
-+
-+		pmlmeext = &iface->mlmeextpriv;
-+		chidx = pmlmeext->cur_channel;
-+		bw = pmlmeext->cur_bwmode;
-+		bw40sc = pmlmeext->cur_ch_offset;
-+
-+		/* decide 80 band width offset */
-+		if (bw == CHANNEL_WIDTH_80) {
-+			u8 center_ch = rtw_get_center_ch(chidx, bw, bw40sc);
-+
-+			if (center_ch > chidx)
-+				bw80sc = HAL_PRIME_CHNL_OFFSET_LOWER;
-+			else if (center_ch < chidx)
-+				bw80sc = HAL_PRIME_CHNL_OFFSET_UPPER;
-+			else
-+				bw80sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		} else
-+			bw80sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+
-+		duration = mccadapriv->mcc_duration;
-+		role = mccadapriv->role;
-+
-+		incurch = _FALSE;
-+
-+		if (IS_HARDWARE_TYPE_8812(padapter))
-+			rfetype = pHalData->rfe_type; /* RFETYPE (only for 8812)*/
-+		else
-+			rfetype = 0;
-+
-+		/* STA/GC TX NULL data to inform AP/GC for ps mode */
-+		switch (role) {
-+		case MCC_ROLE_GO:
-+		case MCC_ROLE_AP:
-+			distxnull = MCC_DISABLE_TX_NULL;
-+			break;
-+		case MCC_ROLE_GC:
-+		case MCC_ROLE_STA:
-+			distxnull = MCC_ENABLE_TX_NULL;
-+			break;
-+		}
-+
-+		c2hrpt = MCC_C2H_REPORT_ALL_STATUS;
-+		chscan = MCC_CHIDX;
-+
-+		SET_H2CCMD_MCC_CTRL_ORDER(cmd, order);
-+		SET_H2CCMD_MCC_CTRL_TOTALNUM(cmd, totalnum);
-+		SET_H2CCMD_MCC_CTRL_CHIDX(cmd, chidx);
-+		SET_H2CCMD_MCC_CTRL_BW(cmd, bw);
-+		SET_H2CCMD_MCC_CTRL_BW40SC(cmd, bw40sc);
-+		SET_H2CCMD_MCC_CTRL_BW80SC(cmd, bw80sc);
-+		SET_H2CCMD_MCC_CTRL_DURATION(cmd, duration);
-+		SET_H2CCMD_MCC_CTRL_ROLE(cmd, role);
-+		SET_H2CCMD_MCC_CTRL_INCURCH(cmd, incurch);
-+		SET_H2CCMD_MCC_CTRL_RFETYPE(cmd, rfetype);
-+		SET_H2CCMD_MCC_CTRL_DISTXNULL(cmd, distxnull);
-+		SET_H2CCMD_MCC_CTRL_C2HRPT(cmd, c2hrpt);
-+		SET_H2CCMD_MCC_CTRL_CHSCAN(cmd, chscan);
-+
-+#ifdef CONFIG_MCC_MODE_DEBUG
-+		RTW_INFO("=========================\n");
-+		RTW_INFO(FUNC_ADPT_FMT" MCC INFO:\n", FUNC_ADPT_ARG(iface));
-+		RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
-+		RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
-+		RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
-+		RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
-+		RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
-+		RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
-+		RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
-+		RTW_INFO("=========================\n");
-+#endif /* CONFIG_MCC_MODE_DEBUG */
-+
-+		rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL, H2C_MCC_CTRL_LEN, cmd);
-+	}
-+}
-+#endif
-+
-+static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop)
-+{
-+	#ifdef CONFIG_MCC_MODE_V2
-+		/* new cmd 0x17 */
-+		rtw_hal_set_mcc_ctrl_cmd_v2(padapter, stop);
-+	#else
-+		/* old cmd 0x18 */
-+		rtw_hal_set_mcc_ctrl_cmd_v1(padapter, stop);
-+	#endif
-+}
-+
-+static u8 check_mcc_support(PADAPTER adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	u8 sta_linked_num = DEV_STA_LD_NUM(dvobj);
-+	u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj);
-+	u8 ap_num = DEV_AP_NUM(dvobj);
-+	u8 ret = _FAIL;
-+
-+	RTW_INFO("[MCC] sta_linked_num=%d, starting_ap_num=%d,ap_num=%d\n",
-+		sta_linked_num, starting_ap_num, ap_num);
-+
-+	/* case for sta + sta case  */
-+	if (sta_linked_num == MAX_MCC_NUM) {
-+		ret = _SUCCESS;
-+		goto exit;
-+	}
-+
-+	/* case for starting AP + linked sta */
-+	if ((starting_ap_num + sta_linked_num) == MAX_MCC_NUM) {
-+		ret = _SUCCESS;
-+		goto exit;
-+	}
-+
-+	/* case for started AP + linked sta */
-+	if ((ap_num + sta_linked_num) == MAX_MCC_NUM) {
-+		ret = _SUCCESS;
-+		goto exit;
-+	}
-+
-+exit:
-+		return ret;
-+}
-+
-+static void rtw_hal_mcc_start_prehdl(PADAPTER padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	_adapter *iface = NULL;
-+	struct mcc_adapter_priv *mccadapriv = NULL;
-+	u8 i = 1;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface == NULL)
-+			continue;
-+
-+		mccadapriv = &iface->mcc_adapterpriv;
-+		mccadapriv->role = MCC_ROLE_MAX;
-+	}
-+
-+#ifdef CONFIG_RTL8822C
-+	if (IS_HARDWARE_TYPE_8822C(padapter)) {
-+		HAL_DATA_TYPE *hal = GET_HAL_DATA(padapter);
-+		struct dm_struct *dm = &hal->odmpriv;
-+		
-+		odm_cmn_info_update(dm, ODM_CMNINFO_IS_DOWNLOAD_FW, hal->bFWReady);
-+	}
-+#endif
-+}
-+
-+static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status)
-+{
-+	u8 ret = _SUCCESS, enable_tsf_auto_sync = _FALSE;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+
-+	if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
-+		rtw_warn_on(1);
-+		RTW_INFO("PS mode is not active before start mcc, force exit ps mode\n");
-+		LeaveAllPowerSaveModeDirect(padapter);
-+	}
-+
-+	if (check_mcc_support(padapter) == _FAIL) {
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	rtw_hal_mcc_start_prehdl(padapter);
-+
-+	/* configure mcc switch channel setting */
-+	rtw_hal_config_mcc_switch_channel_setting(padapter);
-+
-+	if (rtw_hal_decide_mcc_role(padapter) == _FAIL) {
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	/* set mcc status to indicate process mcc start setting */
-+	rtw_hal_set_mcc_status(padapter, MCC_STATUS_PROCESS_MCC_START_SETTING);
-+
-+	/* only download rsvd page for connect */
-+	if (status == MCC_SETCMD_STATUS_START_CONNECT) {
-+		/* download mcc rsvd page */
-+		rtw_hal_set_fw_mcc_rsvd_page(padapter);
-+		rtw_hal_set_mcc_rsvdpage_cmd(padapter);
-+	}
-+
-+	/* configure time setting */
-+	rtw_hal_set_mcc_time_setting_cmd(padapter);
-+
-+#ifndef CONFIG_MCC_MODE_V2
-+	/* IQK value offload */
-+	rtw_hal_set_mcc_IQK_offload_cmd(padapter);
-+#endif
-+
-+	/* set mac id to fw */
-+	rtw_hal_set_mcc_macid_cmd(padapter);
-+#ifdef CONFIG_HW_P0_TSF_SYNC
-+	if (dvobj->p0_tsf.sync_port != MAX_HW_PORT ) {
-+		/* disable tsf auto sync */
-+		RTW_INFO("[MCC] disable HW TSF sync\n");
-+		rtw_hal_set_hwreg(padapter, HW_VAR_TSF_AUTO_SYNC, &enable_tsf_auto_sync);
-+	} else {
-+		RTW_INFO("[MCC] already disable HW TSF sync\n");
-+	}
-+#endif
-+	/* set mcc parameter  */
-+	rtw_hal_set_mcc_ctrl_cmd(padapter, _FALSE);
-+
-+exit:
-+	return ret;
-+}
-+
-+static void rtw_hal_set_mcc_stop_setting(PADAPTER padapter, u8 status)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *mccobjpriv = &dvobj->mcc_objpriv;
-+	_adapter *iface = NULL;
-+	struct mcc_adapter_priv *mccadapriv = NULL;
-+	u8 i = 0;
-+	/*
-+	 * when adapter disconnect, stop mcc mod
-+	 * total=0xf means stop mcc mode
-+	 */
-+
-+	switch (status) {
-+	default:
-+		/* let fw switch to other interface channel */
-+		for (i = 0; i < MAX_MCC_NUM; i++) {
-+			iface = mccobjpriv->iface[i];
-+			if (iface == NULL)
-+				continue;
-+
-+			mccadapriv = &iface->mcc_adapterpriv;
-+
-+			/* use other interface to set cmd */
-+			if (iface != padapter) {
-+				rtw_hal_set_mcc_ctrl_cmd(iface, _TRUE);
-+				break;
-+			}
-+		}
-+		break;
-+	}
-+}
-+
-+static void rtw_hal_mcc_status_hdl(PADAPTER padapter, u8 status)
-+{
-+	switch (status) {
-+	case MCC_SETCMD_STATUS_STOP_DISCONNECT:
-+		rtw_hal_clear_mcc_status(padapter, MCC_STATUS_NEED_MCC | MCC_STATUS_DOING_MCC);
-+		break;
-+	case MCC_SETCMD_STATUS_STOP_SCAN_START:
-+		rtw_hal_set_mcc_status(padapter, MCC_STATUS_NEED_MCC);
-+		rtw_hal_clear_mcc_status(padapter, MCC_STATUS_DOING_MCC);
-+		break;
-+
-+	case MCC_SETCMD_STATUS_START_CONNECT:
-+	case MCC_SETCMD_STATUS_START_SCAN_DONE:
-+		rtw_hal_set_mcc_status(padapter, MCC_STATUS_NEED_MCC | MCC_STATUS_DOING_MCC);
-+		break;
-+	default:
-+		RTW_INFO(FUNC_ADPT_FMT" error status(%d)\n", FUNC_ADPT_ARG(padapter), status);
-+		break;
-+	}
-+}
-+
-+static void rtw_hal_mcc_stop_posthdl(PADAPTER padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+	struct mcc_adapter_priv *mccadapriv = NULL;
-+	_adapter *iface = NULL;
-+	PHAL_DATA_TYPE hal;
-+	u8 i = 0;
-+	u8 enable_rx_bar = _FALSE;
-+
-+	hal = GET_HAL_DATA(padapter);
-+
-+	for (i = 0; i < MAX_MCC_NUM; i++) {
-+		iface = mccobjpriv->iface[i];
-+		if (iface == NULL)
-+			continue;
-+
-+		/* release network queue */
-+		rtw_netif_wake_queue(iface->pnetdev);
-+		mccadapriv = &iface->mcc_adapterpriv;
-+		mccadapriv->mcc_tx_bytes_from_kernel = 0;
-+		mccadapriv->mcc_last_tx_bytes_from_kernel = 0;
-+		mccadapriv->mcc_tx_bytes_to_port = 0;
-+
-+		if (mccadapriv->role == MCC_ROLE_GO)
-+			rtw_hal_mcc_remove_go_p2p_ie(iface);
-+
-+#ifdef CONFIG_TDLS
-+		if (MLME_IS_STA(iface)) {
-+			if (mccadapriv->backup_tdls_en) {
-+				rtw_enable_tdls_func(iface);
-+				RTW_INFO("%s: Disable MCC, Enable TDLS\n", __func__);
-+				mccadapriv->backup_tdls_en = _FALSE;
-+			}
-+		}
-+#endif /* CONFIG_TDLS */
-+
-+		mccadapriv->role = MCC_ROLE_MAX;
-+		mccobjpriv->iface[i] = NULL;
-+	}
-+
-+	/* force switch channel */
-+	hal->current_channel = 0;
-+	hal->current_channel_bw = CHANNEL_WIDTH_MAX;
-+	#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+	rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_STOP, NULL);
-+	#endif
-+
-+#ifdef CONFIG_RTL8822C
-+	if (IS_HARDWARE_TYPE_8822C(padapter)) {
-+		HAL_DATA_TYPE *hal = GET_HAL_DATA(padapter);
-+		struct dm_struct *dm = &hal->odmpriv;
-+		
-+		odm_cmn_info_update(dm, ODM_CMNINFO_IS_DOWNLOAD_FW, _FALSE);
-+	}
-+#endif
-+}
-+
-+static void rtw_hal_mcc_start_posthdl(PADAPTER padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+	struct mcc_adapter_priv *mccadapriv = NULL;
-+	struct pwrctrl_priv	*pwrpriv = adapter_to_pwrctl(padapter);
-+	_adapter *iface = NULL;
-+	u8 i = 0, order = 0;
-+	u8 enable_rx_bar = _TRUE;
-+
-+	for (i = 0; i < MAX_MCC_NUM; i++) {
-+		iface = mccobjpriv->iface[i];
-+		if (iface == NULL)
-+			continue;
-+
-+		mccadapriv = &iface->mcc_adapterpriv;
-+		if (mccadapriv->role == MCC_ROLE_MAX)
-+			continue;
-+		
-+		mccadapriv->mcc_tx_bytes_from_kernel = 0;
-+		mccadapriv->mcc_last_tx_bytes_from_kernel = 0;
-+		mccadapriv->mcc_tx_bytes_to_port = 0;
-+
-+#ifdef CONFIG_TDLS
-+		if (MLME_IS_STA(iface)) {
-+			if (rtw_is_tdls_enabled(iface)) {
-+				mccadapriv->backup_tdls_en = _TRUE;
-+				rtw_disable_tdls_func(iface, _TRUE);
-+				RTW_INFO("%s: Enable MCC, Disable TDLS\n", __func__);
-+			}
-+		}
-+#endif /* CONFIG_TDLS */
-+	}
-+	#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+	rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_START, NULL);
-+	#endif
-+}
-+
-+/*
-+ * rtw_hal_set_mcc_setting - set mcc setting
-+ * @padapter: currnet padapter to stop/start MCC
-+ * @stop: stop mcc or not
-+ * @return val: 1 for SUCCESS, 0 for fail
-+ */
-+static u8 rtw_hal_set_mcc_setting(PADAPTER padapter, u8 status)
-+{
-+	u8 ret = _FAIL;
-+	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+	u8 stop = (status < MCC_SETCMD_STATUS_START_CONNECT) ? _TRUE : _FALSE;
-+	systime start_time = rtw_get_current_time();
-+
-+	RTW_INFO("===> "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+
-+	rtw_sctx_init(&pmccobjpriv->mcc_sctx, MCC_EXPIRE_TIME);
-+	pmccobjpriv->mcc_c2h_status = MCC_RPT_MAX;
-+
-+	if (stop == _FALSE) {
-+		/* handle mcc start */
-+		if (rtw_hal_set_mcc_start_setting(padapter, status) == _FAIL)
-+			goto exit;
-+
-+		/* wait for C2H */
-+		if (!rtw_sctx_wait(&pmccobjpriv->mcc_sctx, __func__))
-+			RTW_INFO(FUNC_ADPT_FMT": wait for mcc start C2H time out\n", FUNC_ADPT_ARG(padapter));
-+		else
-+			ret = _SUCCESS;
-+
-+		if (ret == _SUCCESS) {
-+			RTW_INFO(FUNC_ADPT_FMT": mcc start sucecssfully\n", FUNC_ADPT_ARG(padapter));
-+			rtw_hal_mcc_status_hdl(padapter, status);
-+			rtw_hal_mcc_start_posthdl(padapter);
-+		}
-+	} else {
-+
-+		/* set mcc status to indicate process mcc start setting */
-+		rtw_hal_set_mcc_status(padapter, MCC_STATUS_PROCESS_MCC_STOP_SETTING);
-+
-+		/* handle mcc stop */
-+		rtw_hal_set_mcc_stop_setting(padapter, status);
-+
-+		/* wait for C2H */
-+		if (!rtw_sctx_wait(&pmccobjpriv->mcc_sctx, __func__))
-+			RTW_INFO(FUNC_ADPT_FMT": wait for mcc stop C2H time out\n", FUNC_ADPT_ARG(padapter));
-+		else {
-+			ret = _SUCCESS;
-+			rtw_hal_mcc_status_hdl(padapter, status);
-+			rtw_hal_mcc_stop_posthdl(padapter);
-+		}
-+	}
-+
-+exit:
-+	/* clear mcc status */
-+	rtw_hal_clear_mcc_status(padapter
-+		, MCC_STATUS_PROCESS_MCC_START_SETTING | MCC_STATUS_PROCESS_MCC_STOP_SETTING);
-+
-+	RTW_INFO(FUNC_ADPT_FMT" in %dms <===\n"
-+		, FUNC_ADPT_ARG(padapter), rtw_get_passing_time_ms(start_time));
-+	return ret;
-+}
-+
-+/**
-+ * rtw_hal_mcc_check_case_not_limit_traffic - handler flow ctrl for special case
-+ * @cur_iface: fw stay channel setting of this iface
-+ * @next_iface: fw will swich channel setting of this iface
-+ */
-+static void rtw_hal_mcc_check_case_not_limit_traffic(PADAPTER cur_iface, PADAPTER next_iface)
-+{
-+	u8 cur_bw = cur_iface->mlmeextpriv.cur_bwmode;
-+	u8 next_bw = next_iface->mlmeextpriv.cur_bwmode;
-+
-+	/* for both interface are VHT80, doesn't limit_traffic according to iperf results */
-+	if (cur_bw == CHANNEL_WIDTH_80 && next_bw == CHANNEL_WIDTH_80) {
-+		cur_iface->mcc_adapterpriv.mcc_tp_limit = _FALSE;
-+		next_iface->mcc_adapterpriv.mcc_tp_limit = _FALSE;
-+	}
-+}
-+
-+
-+/**
-+ * rtw_hal_mcc_sw_ch_fw_notify_hdl - handler flow ctrl
-+ */
-+static void rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter)
-+{
-+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
-+	struct mcc_adapter_priv *cur_mccadapriv = NULL, *next_mccadapriv = NULL;
-+	_adapter *iface = NULL, *cur_iface = NULL, *next_iface = NULL;
-+	struct registry_priv *preg = &padapter->registrypriv;
-+	u8 cur_op_ch = pdvobjpriv->oper_channel;
-+	u8 i = 0, iface_num = pdvobjpriv->iface_nums, cur_order = 0, next_order = 0;
-+	static u8 cnt = 1;
-+	u32 single_tx_cri = preg->rtw_mcc_single_tx_cri;
-+
-+	for (i = 0; i < iface_num; i++) {
-+		iface = pdvobjpriv->padapters[i];
-+		if (iface == NULL)
-+			continue;
-+
-+		if (cur_op_ch == iface->mlmeextpriv.cur_channel) {
-+			cur_iface = iface;
-+			cur_mccadapriv = &cur_iface->mcc_adapterpriv;
-+			cur_order = cur_mccadapriv->order;
-+			next_order = (cur_order + 1) % iface_num;
-+			next_iface = pmccobjpriv->iface[next_order];
-+			next_mccadapriv = &next_iface->mcc_adapterpriv;
-+			break;
-+		}
-+	}
-+
-+	if (cur_iface == NULL || next_iface == NULL) {
-+		RTW_ERR("cur_iface=%p,next_iface=%p\n", cur_iface, next_iface);
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	/* check other interface tx busy traffic or not under every 2 switch channel notify(Mbits/100ms) */
-+	if (cnt == 2) {
-+		cur_mccadapriv->mcc_tp = (cur_mccadapriv->mcc_tx_bytes_from_kernel
-+			- cur_mccadapriv->mcc_last_tx_bytes_from_kernel) * 10 * 8 / 1024 / 1024;
-+		cur_mccadapriv->mcc_last_tx_bytes_from_kernel = cur_mccadapriv->mcc_tx_bytes_from_kernel;
-+
-+		next_mccadapriv->mcc_tp = (next_mccadapriv->mcc_tx_bytes_from_kernel
-+			- next_mccadapriv->mcc_last_tx_bytes_from_kernel) * 10 * 8 / 1024 / 1024;
-+		next_mccadapriv->mcc_last_tx_bytes_from_kernel = next_mccadapriv->mcc_tx_bytes_from_kernel;
-+
-+		cnt = 1;
-+	} else
-+		cnt = 2;
-+
-+	/* check single TX or cuncurrnet TX */
-+	if (next_mccadapriv->mcc_tp < single_tx_cri) {
-+		/* single TX, does not stop */
-+		cur_mccadapriv->mcc_tx_stop = _FALSE;
-+		cur_mccadapriv->mcc_tp_limit = _FALSE;
-+	} else {
-+		/* concurrent TX, stop */
-+		cur_mccadapriv->mcc_tx_stop = _TRUE;
-+		cur_mccadapriv->mcc_tp_limit = _TRUE;
-+	}
-+
-+	if (cur_mccadapriv->mcc_tp < single_tx_cri) {
-+		next_mccadapriv->mcc_tx_stop  = _FALSE;
-+		next_mccadapriv->mcc_tp_limit = _FALSE;
-+	} else {
-+		next_mccadapriv->mcc_tx_stop = _FALSE;
-+		next_mccadapriv->mcc_tp_limit = _TRUE;
-+		next_mccadapriv->mcc_tx_bytes_to_port = 0;
-+	}
-+
-+	/* stop current iface kernel queue or not */
-+	if (cur_mccadapriv->mcc_tx_stop)
-+		rtw_netif_stop_queue(cur_iface->pnetdev);
-+	else
-+		rtw_netif_wake_queue(cur_iface->pnetdev);
-+
-+	/* stop next iface kernel queue or not */
-+	if (next_mccadapriv->mcc_tx_stop)
-+		rtw_netif_stop_queue(next_iface->pnetdev);
-+	else
-+		rtw_netif_wake_queue(next_iface->pnetdev);
-+
-+	/* start xmit tasklet */
-+	rtw_os_xmit_schedule(next_iface);
-+
-+	rtw_hal_mcc_check_case_not_limit_traffic(cur_iface, next_iface);
-+
-+	if (0) {
-+		RTW_INFO("order:%d, mcc_tx_stop:%d, mcc_tp:%d\n",
-+			cur_mccadapriv->order, cur_mccadapriv->mcc_tx_stop, cur_mccadapriv->mcc_tp);
-+		dump_os_queue(0, cur_iface);
-+		RTW_INFO("order:%d, mcc_tx_stop:%d, mcc_tp:%d\n",
-+			next_mccadapriv->order, next_mccadapriv->mcc_tx_stop, next_mccadapriv->mcc_tp);
-+		dump_os_queue(0, next_iface);
-+	}
-+}
-+
-+static void rtw_hal_mcc_update_noa_start_time_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
-+{
-+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
-+	struct mcc_adapter_priv *pmccadapriv = NULL;
-+	PADAPTER iface = NULL;
-+	u8 i = 0;
-+	u8 policy_idx = pmccobjpriv->policy_index;
-+	u8 noa_tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
-+	u8 noa_start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
-+	
-+	for (i = 0; i < pdvobjpriv->iface_nums; i++) {
-+		iface = pdvobjpriv->padapters[i];
-+		if (iface == NULL)
-+			continue;
-+		
-+		pmccadapriv = &iface->mcc_adapterpriv;
-+		if (pmccadapriv->role == MCC_ROLE_MAX)
-+			continue;
-+
-+		/* GO & channel match */
-+		if (pmccadapriv->role == MCC_ROLE_GO) {
-+			/* convert GO TBTT from FW to noa_start_time(TU convert to mircosecond) */
-+			pmccadapriv->noa_start_time = RTW_GET_LE32(tmpBuf + 2) + noa_start_time_offset * TU;
-+
-+			if (0) {
-+				RTW_INFO("TBTT:0x%02x\n", RTW_GET_LE32(tmpBuf + 2));
-+				RTW_INFO("noa_tsf_sync_offset:%d, noa_start_time_offset:%d\n", noa_tsf_sync_offset, noa_start_time_offset);
-+				RTW_INFO(FUNC_ADPT_FMT"buf=0x%02x:0x%02x:0x%02x:0x%02x, noa_start_time=0x%02x\n"
-+					, FUNC_ADPT_ARG(iface)
-+					, tmpBuf[2]
-+					, tmpBuf[3]
-+					, tmpBuf[4]
-+					, tmpBuf[5]
-+					,pmccadapriv->noa_start_time);
-+				}
-+
-+			rtw_hal_mcc_update_go_p2p_ie(iface);
-+
-+			break;
-+		}
-+	}
-+
-+}
-+
-+static u8 mcc_get_reg_hdl(PADAPTER adapter, const u8 *val)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
-+	_adapter *cur_iface = NULL;
-+	u8 ret = _SUCCESS;
-+	u8 cur_order = 0;
-+	#ifdef CONFIG_RTL8822C
-+	u16 dbg_reg[DBG_MCC_REG_NUM] = {0x4d4,0x522,0x1d70};
-+	#else
-+	u16 dbg_reg[DBG_MCC_REG_NUM] = {0x4d4,0x522,0xc50,0xe50};
-+	#endif
-+	u16 dbg_rf_reg[DBG_MCC_RF_REG_NUM] = {0x18};
-+	u8 i;
-+	u32 reg_val;
-+	u8 path = 0, path_nums = 0;
-+
-+	if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	if (!val)
-+		cur_order = 0xff;
-+	else
-+		cur_order = *val;
-+
-+	if (cur_order >= MAX_MCC_NUM && cur_order != 0xff) {
-+		RTW_ERR("%s: cur_order=%d\n", __func__, cur_order);
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	path_nums = hal_spec->rf_reg_path_num;
-+	if (cur_order == 0xff)
-+		cur_iface = adapter;
-+	else
-+		cur_iface = mccobjpriv->iface[cur_order];
-+
-+	if (!cur_iface) {
-+		RTW_ERR("%s: cur_iface = NULL,  cur_order=%d\n", __func__, cur_order);
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	_enter_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);
-+	if (!RTW_CANNOT_IO(adapter)) {
-+		/* RTW_INFO("=================================\n");
-+		RTW_INFO(ADPT_FMT": cur_order:%d\n", ADPT_ARG(cur_iface), cur_order); */
-+		
-+		for (i = 0; i < ARRAY_SIZE(dbg_reg); i++) {
-+			reg_val = rtw_read32(adapter, dbg_reg[i]);
-+			mccobjpriv->dbg_reg[i] = dbg_reg[i];
-+			mccobjpriv->dbg_reg_val[i] = reg_val;
-+			/* RTW_PRINT("REG_%X:0x%08x\n", dbg_reg[i], reg_val); */
-+		}
-+		for (i = 0; i < ARRAY_SIZE(dbg_rf_reg); i++) {
-+			for (path = 0; path < path_nums; path++) {
-+				reg_val = rtw_hal_read_rfreg(adapter, path, dbg_rf_reg[i], 0xffffffff);
-+				/* RTW_PRINT("RF_PATH_%d_REG_%X:0x%08x\n",
-+					path, dbg_rf_reg[i], reg_val); */
-+				mccobjpriv->dbg_rf_reg[i] = dbg_rf_reg[i];
-+				mccobjpriv->dbg_rf_reg_val[i][path] = reg_val;
-+			}
-+		}
-+	}
-+	_exit_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);
-+
-+exit:
-+	return ret;
-+}
-+
-+static u8 mcc_get_reg_cmd(_adapter *adapter, u8 cur_order)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	u8 *mcc_cur_order = NULL;
-+	u8 res = _SUCCESS;
-+
-+	
-+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (cmdobj == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	mcc_cur_order = rtw_zmalloc(sizeof(u8));
-+	if (mcc_cur_order == NULL) {
-+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = MCC_CMD_WK_CID;
-+	pdrvextra_cmd_parm->type = MCC_GET_DBG_REG_WK_CID;
-+	pdrvextra_cmd_parm->size = 1;
-+	pdrvextra_cmd_parm->pbuf = mcc_cur_order;
-+
-+	_rtw_memcpy(mcc_cur_order, &cur_order, 1);
-+
-+	init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+	res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+
-+exit:
-+	return res;
-+}
-+
-+static void rtw_hal_mcc_rpt_tsf_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
-+{
-+	struct dvobj_priv *dvobjpriv = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+	struct submit_ctx *mcc_tsf_req_sctx = &mccobjpriv->mcc_tsf_req_sctx;
-+	struct mcc_adapter_priv *mccadapriv = NULL;
-+	_adapter *iface = NULL;
-+	u8 order = 0;
-+
-+	order = mccobjpriv->mcc_tsf_req_sctx_order;
-+	iface = mccobjpriv->iface[order];
-+	mccadapriv = &iface->mcc_adapterpriv;
-+	mccadapriv->tsf = RTW_GET_LE64(tmpBuf + 2);
-+
-+
-+	if (0)
-+		RTW_INFO(FUNC_ADPT_FMT" TSF(order:%d):0x%02llx\n", FUNC_ADPT_ARG(iface), mccadapriv->order, mccadapriv->tsf);
-+
-+	if (mccadapriv->order == (MAX_MCC_NUM - 1))
-+		rtw_sctx_done(&mcc_tsf_req_sctx);
-+	else
-+		mccobjpriv->mcc_tsf_req_sctx_order ++;
-+
-+}
-+
-+/**
-+ * rtw_hal_mcc_c2h_handler - mcc c2h handler
-+ */
-+void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
-+{
-+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
-+	struct submit_ctx *mcc_sctx = &pmccobjpriv->mcc_sctx;
-+	_adapter *cur_adapter = NULL;
-+	u8 cur_ch = 0, cur_bw = 0, cur_ch_offset = 0;
-+	_irqL irqL;
-+
-+	/* RTW_INFO("[length]=%d, [C2H data]="MAC_FMT"\n", buflen, MAC_ARG(tmpBuf)); */
-+	/* To avoid reg is set, but driver recive c2h to set wrong oper_channel */
-+	if (MCC_RPT_STOPMCC == pmccobjpriv->mcc_c2h_status) {
-+		RTW_INFO(FUNC_ADPT_FMT" MCC alread stops return\n", FUNC_ADPT_ARG(padapter));
-+		return;
-+	}
-+
-+	_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
-+	pmccobjpriv->mcc_c2h_status = tmpBuf[0];
-+	pmccobjpriv->current_order = tmpBuf[1];
-+	cur_adapter = pmccobjpriv->iface[pmccobjpriv->current_order];
-+	cur_ch = cur_adapter->mlmeextpriv.cur_channel;
-+	cur_bw = cur_adapter->mlmeextpriv.cur_bwmode;
-+	cur_ch_offset = cur_adapter->mlmeextpriv.cur_ch_offset;
-+	rtw_set_oper_ch(cur_adapter, cur_ch);
-+	rtw_set_oper_bw(cur_adapter, cur_bw);
-+	rtw_set_oper_choffset(cur_adapter, cur_ch_offset);
-+	_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
-+
-+	if (0)
-+		RTW_INFO("%d,order:%d,TSF:0x%llx\n", tmpBuf[0], tmpBuf[1], RTW_GET_LE64(tmpBuf + 2));
-+	
-+	switch (pmccobjpriv->mcc_c2h_status) {
-+	case MCC_RPT_SUCCESS:
-+		_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
-+		pmccobjpriv->cur_mcc_success_cnt++;
-+		rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _FALSE);
-+		mcc_get_reg_cmd(padapter, pmccobjpriv->current_order);
-+		_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
-+		break;
-+	case MCC_RPT_TXNULL_FAIL:
-+		RTW_INFO("[MCC] TXNULL FAIL\n");
-+		break;
-+	case MCC_RPT_STOPMCC:
-+		RTW_INFO("[MCC] MCC stop\n");
-+		pmccobjpriv->mcc_c2h_status = MCC_RPT_STOPMCC;
-+		rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _TRUE);
-+		rtw_sctx_done(&mcc_sctx);
-+		break;
-+	case MCC_RPT_READY:
-+		_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
-+		/* initialize counter & time */
-+		pmccobjpriv->mcc_launch_time = rtw_get_current_time();
-+		pmccobjpriv->mcc_c2h_status = MCC_RPT_READY;
-+		pmccobjpriv->cur_mcc_success_cnt = 0;
-+		pmccobjpriv->prev_mcc_success_cnt = 0;
-+		pmccobjpriv->mcc_tolerance_time = MCC_TOLERANCE_TIME;
-+		_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
-+
-+		RTW_INFO("[MCC] MCC ready\n");
-+		rtw_sctx_done(&mcc_sctx);
-+		break;
-+	case MCC_RPT_SWICH_CHANNEL_NOTIFY:
-+		rtw_hal_mcc_sw_ch_fw_notify_hdl(padapter);
-+		break;
-+	case MCC_RPT_UPDATE_NOA_START_TIME:
-+		rtw_hal_mcc_update_noa_start_time_hdl(padapter, buflen, tmpBuf);
-+		break;
-+	case MCC_RPT_TSF:
-+		_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
-+		rtw_hal_mcc_rpt_tsf_hdl(padapter, buflen, tmpBuf);
-+		_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
-+		break;
-+	default:
-+		/* RTW_INFO("[MCC] Other MCC status(%d)\n", pmccobjpriv->mcc_c2h_status); */
-+		break;
-+	}
-+}
-+
-+void rtw_hal_mcc_update_parameter(PADAPTER padapter, u8 force_update)
-+{	
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
-+	u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0};
-+	u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME;
-+	u8 ap_num = DEV_AP_NUM(dvobj);	
-+
-+	if (ap_num == 0) {
-+		u8 need_update = _FALSE;
-+		u8 start_time_offset = 0, interval = 0, duration = 0;
-+
-+		need_update = rtw_hal_mcc_update_timing_parameters(padapter, force_update);
-+
-+		if (need_update == _FALSE)
-+			return;
-+		
-+		start_time_offset = mccobjpriv->start_time;
-+		interval = mccobjpriv->interval;
-+		duration = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration;
-+
-+		SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, start_time_offset);
-+		SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
-+		SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
-+		SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE);
-+		SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, duration);
-+	} else {
-+		PADAPTER order0_iface = NULL;
-+		PADAPTER order1_iface = NULL;
-+		u8 policy_idx = mccobjpriv->policy_index;
-+		u8 duration = mcc_switch_channel_policy_table[policy_idx][MCC_DURATION_IDX];
-+		u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
-+		u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
-+		u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX];
-+		u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX];
-+		u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX];
-+		u8 order0_duration = 0;
-+		u8 i = 0;
-+		enum _hw_port tsf_bsae_port = MAX_HW_PORT;
-+		enum _hw_port tsf_sync_port = MAX_HW_PORT;
-+
-+		RTW_INFO("%s: policy_idx=%d\n", __func__, policy_idx);
-+
-+		order0_iface = mccobjpriv->iface[0];
-+		order1_iface = mccobjpriv->iface[1];
-+
-+		/* GO/AP is order 0, GC/STA is order 1 */
-+		order0_duration = order0_iface->mcc_adapterpriv.mcc_duration = interval - duration;
-+		order0_iface->mcc_adapterpriv.mcc_duration = duration;
-+
-+		tsf_bsae_port = rtw_hal_get_port(order1_iface);
-+		tsf_sync_port = rtw_hal_get_port(order0_iface);
-+
-+		/* update IE */
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			PADAPTER iface = NULL;
-+			struct mcc_adapter_priv *mccadapriv = NULL;
-+
-+			iface = dvobj->padapters[i];
-+			if (iface == NULL)
-+				continue;
-+		
-+			mccadapriv = &iface->mcc_adapterpriv;
-+			if (mccadapriv->role == MCC_ROLE_MAX)
-+				continue;
-+			
-+			if (mccadapriv->role == MCC_ROLE_GO)
-+				rtw_hal_mcc_update_go_p2p_ie(iface);
-+		}
-+
-+		/* update H2C cmd */
-+		/* FW set enable */
-+		SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, _TRUE);
-+		/* TSF Sync offset */
-+		SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset);
-+		/* start time offset */
-+		SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0));
-+		/* interval */
-+		SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
-+		/* Early time to inform driver by C2H before switch channel */
-+		SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
-+		/* Port0 sync from Port1, not support multi-port */
-+		SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, tsf_bsae_port);
-+		SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, tsf_sync_port);
-+		SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE);
-+		SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, order0_duration);
-+	}
-+
-+	rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd);
-+}
-+
-+/**
-+ * rtw_hal_mcc_sw_status_check - check mcc swich channel status
-+ * @padapter: primary adapter
-+ */
-+void rtw_hal_mcc_sw_status_check(PADAPTER padapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
-+	struct pwrctrl_priv	*pwrpriv = dvobj_to_pwrctl(dvobj);
-+	struct mcc_adapter_priv *mccadapriv = NULL;
-+	_adapter *iface = NULL;
-+	u8 cur_cnt = 0, prev_cnt = 0, diff_cnt = 0, check_ret = _FAIL, threshold = 0;
-+	u8 policy_idx = pmccobjpriv->policy_index;
-+	u8 noa_enable = _FALSE;
-+	u8 i = 0;
-+	_irqL irqL;
-+	u8 ap_num = DEV_AP_NUM(dvobj);	
-+
-+/* #define MCC_RESTART 1 */
-+
-+	if (!MCC_EN(padapter))
-+		return;
-+
-+	_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
-+
-+	if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
-+
-+		/* check noa enable or not */
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			if (iface == NULL)
-+				continue;
-+
-+			mccadapriv = &iface->mcc_adapterpriv;
-+			if (mccadapriv->role == MCC_ROLE_MAX)
-+				continue;
-+			
-+			if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
-+				noa_enable = _TRUE;
-+				break;
-+			}
-+		}		
-+
-+		if (!noa_enable && ap_num == 0)
-+			rtw_hal_mcc_update_parameter(padapter, _FALSE);
-+
-+		threshold = pmccobjpriv->mcc_stop_threshold;
-+
-+		if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
-+			rtw_warn_on(1);
-+			RTW_INFO("PS mode is not active under mcc, force exit ps mode\n");
-+			LeaveAllPowerSaveModeDirect(padapter);
-+		}
-+
-+		if (rtw_get_passing_time_ms(pmccobjpriv->mcc_launch_time) > 2000) {
-+			_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
-+
-+			cur_cnt = pmccobjpriv->cur_mcc_success_cnt;
-+			prev_cnt = pmccobjpriv->prev_mcc_success_cnt;
-+			if (cur_cnt < prev_cnt)
-+				diff_cnt = (cur_cnt + 255) - prev_cnt;
-+			else
-+				diff_cnt = cur_cnt - prev_cnt;
-+
-+			if (diff_cnt < threshold) {
-+				pmccobjpriv->mcc_tolerance_time--;
-+				RTW_INFO("%s: diff_cnt:%d, tolerance_time:%d\n",
-+					__func__, diff_cnt, pmccobjpriv->mcc_tolerance_time);
-+			} else
-+				pmccobjpriv->mcc_tolerance_time = MCC_TOLERANCE_TIME;
-+
-+			pmccobjpriv->prev_mcc_success_cnt = pmccobjpriv->cur_mcc_success_cnt;
-+
-+			if (pmccobjpriv->mcc_tolerance_time != 0)
-+				check_ret = _SUCCESS;
-+
-+			_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
-+
-+			if (check_ret != _SUCCESS) {
-+				RTW_INFO("============ MCC swich channel check fail (%d)=============\n", diff_cnt);
-+				/* restart MCC */
-+				#ifdef MCC_RESTART
-+					rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_DISCONNECT);
-+					rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
-+				#endif /* MCC_RESTART */
-+			}
-+		} else {
-+			_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
-+			pmccobjpriv->prev_mcc_success_cnt = pmccobjpriv->cur_mcc_success_cnt;
-+			_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
-+		}
-+
-+	}
-+	_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
-+}
-+
-+/**
-+ * rtw_hal_mcc_change_scan_flag - change scan flag under mcc
-+ *
-+ * MCC mode under sitesurvey goto AP channel to tx bcn & data
-+ * MCC mode under sitesurvey doesn't support TX data for station mode (FW not support)
-+ *
-+ * @padapter: the adapter to be change scan flag
-+ * @ch: pointer to rerurn ch
-+ * @bw: pointer to rerurn bw
-+ * @offset: pointer to rerurn offset
-+ */
-+u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset)
-+{
-+	u8 need_ch_setting_union = _TRUE, i = 0, flags = 0, back_op = _FALSE;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_adapter_priv *mccadapriv = NULL;
-+	struct mlme_ext_priv *mlmeext = NULL;
-+	_adapter *iface = NULL;
-+
-+	if (!MCC_EN(padapter))
-+		goto exit;
-+
-+	if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC))
-+		goto exit;
-+
-+	/* disable PS_ANNC & TX_RESUME for all interface */
-+	/* ToDo: TX_RESUME by interface in SCAN_BACKING_OP */
-+	mlmeext = &padapter->mlmeextpriv;
-+	
-+	flags = mlmeext_scan_backop_flags(mlmeext);
-+	if (mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_PS_ANNC))
-+		flags &= ~SS_BACKOP_PS_ANNC;
-+
-+	if (mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME))
-+		flags &= ~SS_BACKOP_TX_RESUME;
-+
-+	mlmeext_assign_scan_backop_flags(mlmeext, flags);
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (!iface)
-+			continue;
-+
-+		mlmeext = &iface->mlmeextpriv;
-+
-+		if (MLME_IS_GO(iface) || MLME_IS_AP(iface))
-+			back_op = _TRUE;
-+		else if (MLME_IS_GC(iface) && (iface != padapter))
-+			/* switch to another linked interface(GO) to receive beacon to avoid no beacon disconnect */
-+			back_op = _TRUE;
-+		else if (MLME_IS_STA(iface) && MLME_IS_ASOC(iface) && (iface != padapter))
-+			/* switch to another linked interface(STA) to receive beacon to avoid no beacon disconnect  */
-+			back_op = _TRUE;
-+		else {
-+			/* bypass non-linked/non-linking interface/scan interface */
-+			continue;
-+		}
-+		
-+		if (back_op) {
-+			*ch = mlmeext->cur_channel;
-+			*bw = mlmeext->cur_bwmode;
-+			*offset = mlmeext->cur_ch_offset;
-+			need_ch_setting_union = _FALSE;
-+		}
-+	}
-+exit:
-+	return need_ch_setting_union;
-+}
-+
-+/**
-+ * rtw_hal_mcc_calc_tx_bytes_from_kernel - calculte tx bytes from kernel to check concurrent tx or not
-+ * @padapter: the adapter to be record tx bytes
-+ * @len: data len
-+ */
-+inline void rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len)
-+{
-+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
-+
-+	if (MCC_EN(padapter)) {
-+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
-+			pmccadapriv->mcc_tx_bytes_from_kernel += len;
-+			if (0)
-+				RTW_INFO("%s(order:%d): mcc tx bytes from kernel:%lld\n"
-+					, __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_from_kernel);
-+		}
-+	}
-+}
-+
-+/**
-+ * rtw_hal_mcc_calc_tx_bytes_to_port - calculte tx bytes to write port in order to flow crtl
-+ * @padapter: the adapter to be record tx bytes
-+ * @len: data len
-+ */
-+inline void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len)
-+{
-+	if (MCC_EN(padapter)) {
-+		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+		struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
-+
-+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
-+			pmccadapriv->mcc_tx_bytes_to_port += len;
-+			if (0)
-+				RTW_INFO("%s(order:%d): mcc tx bytes to port:%d, mcc target tx bytes to port:%d\n"
-+					, __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_to_port
-+					, pmccadapriv->mcc_target_tx_bytes_to_port);
-+		}
-+	}
-+}
-+
-+/**
-+ * rtw_hal_mcc_stop_tx_bytes_to_port - stop write port to hw or not
-+ * @padapter: the adapter to be stopped
-+ */
-+inline u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter)
-+{
-+	if (MCC_EN(padapter)) {
-+		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+		struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
-+
-+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
-+			if (pmccadapriv->mcc_tp_limit) {
-+				if (pmccadapriv->mcc_tx_bytes_to_port >= pmccadapriv->mcc_target_tx_bytes_to_port) {
-+					pmccadapriv->mcc_tx_stop = _TRUE;
-+					rtw_netif_stop_queue(padapter->pnetdev);
-+					return _TRUE;
-+				}
-+			}
-+		}
-+	}
-+
-+	return _FALSE;
-+}
-+
-+static void rtw_hal_mcc_assign_scan_flag(PADAPTER padapter, u8 scan_done)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_adapter_priv *mccadapriv = NULL;
-+	_adapter *iface = NULL;
-+	struct mlme_ext_priv *pmlmeext = NULL;
-+	u8 i = 0, flags;
-+
-+	if (!MCC_EN(padapter))
-+		return;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface == NULL)
-+			continue;
-+
-+		mccadapriv = &iface->mcc_adapterpriv;
-+		if (mccadapriv->role == MCC_ROLE_MAX)
-+			continue;
-+
-+		pmlmeext = &iface->mlmeextpriv;
-+		if (is_client_associated_to_ap(iface)) {
-+			flags = mlmeext_scan_backop_flags_sta(pmlmeext);
-+			if (scan_done) {
-+				if (mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) {
-+					flags &= ~SS_BACKOP_EN;
-+					mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags);
-+				}
-+			} else {
-+				if (!mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) {
-+					flags |= SS_BACKOP_EN;
-+					mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags);
-+				}
-+			}
-+
-+		}
-+	}
-+}
-+
-+/**
-+ * rtw_hal_set_mcc_setting_scan_start - setting mcc under scan start
-+ * @padapter: the adapter to be setted
-+ * @ch_setting_changed: softap channel setting to be changed or not
-+ */
-+u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter)
-+{
-+	u8 ret = _FAIL;
-+
-+	if (MCC_EN(padapter)) {
-+		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+
-+		_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
-+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
-+			if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
-+				ret = rtw_hal_set_mcc_setting(padapter,  MCC_SETCMD_STATUS_STOP_SCAN_START);
-+				rtw_hal_mcc_assign_scan_flag(padapter, 0);
-+			}
-+		}
-+		_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
-+	}
-+
-+	return ret;
-+}
-+
-+/**
-+ * rtw_hal_set_mcc_setting_scan_complete - setting mcc after scan commplete
-+ * @padapter: the adapter to be setted
-+ * @ch_setting_changed: softap channel setting to be changed or not
-+ */
-+u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter)
-+{
-+	u8 ret = _FAIL;
-+
-+	if (MCC_EN(padapter)) {
-+		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+
-+		_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
-+
-+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
-+				rtw_hal_mcc_assign_scan_flag(padapter, 1);
-+				ret = rtw_hal_set_mcc_setting(padapter,  MCC_SETCMD_STATUS_START_SCAN_DONE);	
-+		}
-+		_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
-+	}
-+
-+	return ret;
-+}
-+
-+
-+/**
-+ * rtw_hal_set_mcc_setting_start_bss_network - setting mcc under softap start
-+ * @padapter: the adapter to be setted
-+ * @chbw_grouped: channel bw offset can not be allowed or not
-+ */
-+u8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_allow)
-+{
-+	u8 ret = _FAIL;
-+
-+	if (MCC_EN(padapter)) {
-+		/* channel bw offset can not be allowed, start MCC */
-+		if (chbw_allow == _FALSE) {
-+			struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+
-+			//rtw_hal_mcc_restore_iqk_val(padapter);
-+			_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
-+			ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
-+			_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
-+
-+			if (ret == _FAIL) { /* MCC Start fail, AP/GO switch to buddy's channel */
-+				u8 ch_to_set = 0, bw_to_set, offset_to_set;
-+
-+				rtw_hal_set_mcc_status(padapter, MCC_STATUS_NEED_MCC | MCC_STATUS_DOING_MCC);
-+				rtw_hal_set_mcc_setting_disconnect(padapter);
-+				if (rtw_mi_get_ch_setting_union_no_self(
-+						padapter, &ch_to_set, &bw_to_set,
-+						&offset_to_set) != 0) {
-+					PHAL_DATA_TYPE  hal = GET_HAL_DATA(padapter);
-+					u8 doiqk = _TRUE;
-+
-+					rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk);
-+					hal->current_channel = 0;
-+					hal->current_channel_bw = CHANNEL_WIDTH_MAX;
-+					set_channel_bwmode(padapter, ch_to_set, offset_to_set, bw_to_set);
-+					doiqk = _FALSE;
-+					rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk);
-+				}
-+			}
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+/**
-+ * rtw_hal_set_mcc_setting_disconnect - setting mcc under mlme disconnect(stop softap/disconnect from AP)
-+ * @padapter: the adapter to be setted
-+ */
-+u8 rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter)
-+{
-+	u8 ret = _FAIL;
-+
-+	if (MCC_EN(padapter)) {
-+		struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
-+
-+		_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
-+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
-+			if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
-+				ret = rtw_hal_set_mcc_setting(padapter,  MCC_SETCMD_STATUS_STOP_DISCONNECT);
-+		}
-+		_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
-+	}
-+
-+	return ret;
-+}
-+
-+/**
-+ * rtw_hal_set_mcc_setting_join_done_chk_ch - setting mcc under join done
-+ * @padapter: the adapter to be checked
-+ */
-+u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter)
-+{
-+	u8 ret = _FAIL;
-+
-+	if (MCC_EN(padapter)) {
-+		struct mi_state mstate;
-+
-+		rtw_mi_status_no_self(padapter, &mstate);
-+
-+		if (MSTATE_STA_LD_NUM(&mstate) || MSTATE_STA_LG_NUM(&mstate) || MSTATE_AP_NUM(&mstate)) {
-+			bool chbw_allow = _TRUE;
-+			u8 u_ch, u_offset, u_bw;
-+			struct mlme_ext_priv *cur_mlmeext = &padapter->mlmeextpriv;
-+			struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+			if (rtw_mi_get_ch_setting_union_no_self(padapter, &u_ch, &u_bw, &u_offset) <= 0) {
-+				dump_adapters_status(RTW_DBGDUMP , dvobj);
-+				rtw_warn_on(1);
-+			}
-+
-+			RTW_INFO(FUNC_ADPT_FMT" union no self: %u,%u,%u\n"
-+				, FUNC_ADPT_ARG(padapter), u_ch, u_bw, u_offset);
-+
-+			/* chbw_allow? */
-+			chbw_allow = rtw_is_chbw_grouped(cur_mlmeext->cur_channel
-+				, cur_mlmeext->cur_bwmode, cur_mlmeext->cur_ch_offset
-+					, u_ch, u_bw, u_offset);
-+
-+			RTW_INFO(FUNC_ADPT_FMT" chbw_allow:%d\n"
-+				, FUNC_ADPT_ARG(padapter), chbw_allow);
-+
-+			/* if chbw_allow = false, start MCC setting */
-+			if (chbw_allow == _FALSE) {
-+				struct mcc_obj_priv *pmccobjpriv = &dvobj->mcc_objpriv;
-+
-+				rtw_hal_mcc_restore_iqk_val(padapter);
-+				_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
-+				ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
-+				_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
-+
-+				if (ret == _FAIL) { /* MCC Start Fail, then disconenct client join */
-+					rtw_hal_set_mcc_status(padapter, MCC_STATUS_NEED_MCC | MCC_STATUS_DOING_MCC);
-+					rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY);
-+					rtw_indicate_disconnect(padapter, 0, _FALSE);
-+					rtw_free_assoc_resources(padapter, _TRUE);
-+					rtw_free_network_queue(padapter, _TRUE);
-+				}
-+			}
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+/**
-+ * rtw_hal_set_mcc_setting_chk_start_clnt_join - check change channel under start clnt join
-+ * @padapter: the adapter to be checked
-+ * @ch: pointer to rerurn ch
-+ * @bw: pointer to rerurn bw
-+ * @offset: pointer to rerurn offset
-+ * @chbw_allow: allow to use adapter's channel setting
-+ */
-+u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset, u8 chbw_allow)
-+{
-+	u8 ret = _FAIL;
-+
-+	/* if chbw_allow = false under en_mcc = TRUE, we do not change channel related setting  */
-+	if (MCC_EN(padapter)) {
-+		/* restore union channel related setting to current channel related setting */
-+		if (chbw_allow == _FALSE) {
-+			struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+
-+			/* issue null data to other interface connected to AP */
-+			rtw_hal_mcc_issue_null_data(padapter, chbw_allow, _TRUE);
-+
-+			*ch = pmlmeext->cur_channel;
-+			*bw = pmlmeext->cur_bwmode;
-+			*offset = pmlmeext->cur_ch_offset;
-+
-+			RTW_INFO(FUNC_ADPT_FMT" en_mcc:%d(%d,%d,%d,)\n"
-+				, FUNC_ADPT_ARG(padapter), MCC_EN(padapter)
-+				, *ch, *bw, *offset);
-+			ret = _SUCCESS;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+static void rtw_hal_mcc_dump_noa_content(void *sel, PADAPTER padapter)
-+{
-+	struct mcc_adapter_priv *pmccadapriv = NULL;
-+	u8 *pos = NULL;
-+	pmccadapriv = &padapter->mcc_adapterpriv;
-+	/* last position for NoA attribute */
-+	pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len;
-+
-+
-+	RTW_PRINT_SEL(sel, "\nStart to dump NoA Content\n");
-+	RTW_PRINT_SEL(sel, "NoA Counts:%d\n", *(pos - 13));
-+	RTW_PRINT_SEL(sel, "NoA Duration(TU):%d\n", (RTW_GET_LE32(pos - 12))/TU);
-+	RTW_PRINT_SEL(sel, "NoA Interval(TU):%d\n", (RTW_GET_LE32(pos - 8))/TU);
-+	RTW_PRINT_SEL(sel, "NoA Start time(microseconds):0x%02x\n", RTW_GET_LE32(pos - 4));
-+	RTW_PRINT_SEL(sel, "End to dump NoA Content\n");
-+}
-+
-+static void mcc_dump_dbg_reg(void *sel, _adapter *adapter)
-+{
-+	struct mcc_obj_priv *mccobjpriv = adapter_to_mccobjpriv(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	u8 i,j;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&mccobjpriv->mcc_lock, &irqL);
-+	RTW_PRINT_SEL(sel, "current order=%d\n", mccobjpriv->current_order);
-+	_exit_critical_bh(&mccobjpriv->mcc_lock, &irqL);
-+
-+	_enter_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);
-+	for (i = 0; i < ARRAY_SIZE(mccobjpriv->dbg_reg); i++)
-+			RTW_PRINT_SEL(sel, "REG_0x%X:0x%08x\n", mccobjpriv->dbg_reg[i], mccobjpriv->dbg_reg_val[i]);
-+
-+	for (i = 0; i < ARRAY_SIZE(mccobjpriv->dbg_rf_reg); i++) {
-+		for (j = 0; j < hal_spec->rf_reg_path_num; j++)
-+			RTW_PRINT_SEL(sel, "RF_PATH_%d_REG_0x%X:0x%08x\n",
-+				j, mccobjpriv->dbg_rf_reg[i], mccobjpriv->dbg_rf_reg_val[i][j]);
-+	}
-+	_exit_critical_mutex(&mccobjpriv->mcc_dbg_reg_mutex, NULL);
-+}
-+
-+
-+void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj)
-+{
-+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
-+	struct mcc_adapter_priv *mccadapriv = NULL;
-+	_adapter *iface = NULL, *pri_adapter = NULL;
-+	struct registry_priv *regpriv = NULL;
-+	HAL_DATA_TYPE *hal = NULL;
-+	u8 i = 0, j = 0;
-+	u64 tsf[MAX_MCC_NUM] = {0};
-+
-+	/* regpriv is common for all adapter */
-+	pri_adapter = dvobj_get_primary_adapter(dvobj);
-+	hal = GET_HAL_DATA(pri_adapter);
-+
-+	RTW_PRINT_SEL(sel, "**********************************************\n");
-+	RTW_PRINT_SEL(sel, "en_mcc:%d\n", MCC_EN(pri_adapter));
-+	RTW_PRINT_SEL(sel, "primary adapter("ADPT_FMT") duration:%d%c\n",
-+		ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mccobjpriv->duration, 37);
-+	RTW_PRINT_SEL(sel, "runtime duration:%s\n", mccobjpriv->enable_runtime_duration ? "enable":"disable");
-+	RTW_PRINT_SEL(sel, "phydm offload:%s\n", mccobjpriv->mcc_phydm_offload ? "enable":"disable");
-+
-+	if (rtw_hal_check_mcc_status(pri_adapter, MCC_STATUS_DOING_MCC)) {
-+		rtw_hal_mcc_rqt_tsf(pri_adapter, tsf);
-+
-+		for (i = 0; i < MAX_MCC_NUM; i++) {
-+			iface = mccobjpriv->iface[i];
-+			if (!iface)
-+				continue;
-+
-+			regpriv = &iface->registrypriv;
-+			mccadapriv = &iface->mcc_adapterpriv;
-+
-+			if (mccadapriv) {
-+				u8 p2p_ps_mode = iface->wdinfo.p2p_ps_mode;
-+
-+				RTW_PRINT_SEL(sel, "adapter mcc info:\n");
-+				RTW_PRINT_SEL(sel, "ifname:%s\n", ADPT_ARG(iface));
-+				RTW_PRINT_SEL(sel, "order:%d\n", mccadapriv->order);
-+				RTW_PRINT_SEL(sel, "duration:%d\n", mccadapriv->mcc_duration);
-+				RTW_PRINT_SEL(sel, "target tx bytes:%d\n", mccadapriv->mcc_target_tx_bytes_to_port);
-+				RTW_PRINT_SEL(sel, "current TP:%d\n", mccadapriv->mcc_tp);
-+				RTW_PRINT_SEL(sel, "mgmt queue macid:%d\n", mccadapriv->mgmt_queue_macid);
-+				RTW_PRINT_SEL(sel, "macid bitmap:0x%02x\n", mccadapriv->mcc_macid_bitmap);
-+				RTW_PRINT_SEL(sel, "P2P NoA:%s\n\n", p2p_ps_mode == P2P_PS_NOA ? "enable":"disable");
-+				RTW_PRINT_SEL(sel, "registry data:\n");
-+				RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", regpriv->rtw_mcc_ap_bw20_target_tx_tp);
-+				RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", regpriv->rtw_mcc_ap_bw40_target_tx_tp);
-+				RTW_PRINT_SEL(sel, "ap target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_ap_bw80_target_tx_tp);
-+				RTW_PRINT_SEL(sel, "sta target tx TP(BW:20M):%d Mbps\n", regpriv->rtw_mcc_sta_bw20_target_tx_tp);
-+				RTW_PRINT_SEL(sel, "sta target tx TP(BW:40M ):%d Mbps\n", regpriv->rtw_mcc_sta_bw40_target_tx_tp);
-+				RTW_PRINT_SEL(sel, "sta target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_sta_bw80_target_tx_tp);
-+				RTW_PRINT_SEL(sel, "single tx criteria:%d Mbps\n", regpriv->rtw_mcc_single_tx_cri);
-+				RTW_PRINT_SEL(sel, "HW TSF=0x%llx\n", tsf[mccadapriv->order]);
-+				if (MLME_IS_GO(iface))
-+					rtw_hal_mcc_dump_noa_content(sel, iface);
-+				RTW_PRINT_SEL(sel, "**********************************************\n");
-+			}
-+		}
-+
-+		mcc_dump_dbg_reg(sel, pri_adapter);
-+	}
-+
-+	#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+	RTW_PRINT_SEL(sel, "@@@@@@@@@@@@@@@@@@@@\n");
-+	rtw_hal_mcc_cfg_phydm(pri_adapter, MCC_CFG_PHYDM_DUMP, sel);
-+	RTW_PRINT_SEL(sel, "@@@@@@@@@@@@@@@@@@@@\n");
-+	#endif
-+	
-+	RTW_PRINT_SEL(sel, "------------------------------------------\n");
-+	RTW_PRINT_SEL(sel, "policy index:%d\n", mccobjpriv->policy_index);	
-+	RTW_PRINT_SEL(sel, "------------------------------------------\n");
-+	RTW_PRINT_SEL(sel, "define data:\n");
-+	RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", MCC_AP_BW20_TARGET_TX_TP);
-+	RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", MCC_AP_BW40_TARGET_TX_TP);
-+	RTW_PRINT_SEL(sel, "ap target tx TP(BW:80M):%d Mbps\n", MCC_AP_BW80_TARGET_TX_TP);
-+	RTW_PRINT_SEL(sel, "sta target tx TP(BW:20M):%d Mbps\n", MCC_STA_BW20_TARGET_TX_TP);
-+	RTW_PRINT_SEL(sel, "sta target tx TP(BW:40M):%d Mbps\n", MCC_STA_BW40_TARGET_TX_TP);
-+	RTW_PRINT_SEL(sel, "sta target tx TP(BW:80M):%d Mbps\n", MCC_STA_BW80_TARGET_TX_TP);
-+	RTW_PRINT_SEL(sel, "single tx criteria:%d Mbps\n", MCC_SINGLE_TX_CRITERIA);
-+	RTW_PRINT_SEL(sel, "------------------------------------------\n");
-+}
-+
-+inline void update_mcc_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
-+{
-+	if (MCC_EN(padapter)) {
-+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
-+			/* use QSLT_MGNT to check mgnt queue or bcn queue */
-+			if (pattrib->qsel == QSLT_MGNT) {
-+				pattrib->mac_id = padapter->mcc_adapterpriv.mgmt_queue_macid;
-+				pattrib->qsel = QSLT_VO;
-+			}
-+		}
-+	}
-+}
-+
-+inline u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg)
-+{
-+	u8 ret = _TRUE, i = 0;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	_adapter *iface;
-+	struct mlme_ext_priv *mlmeext;
-+
-+	if (MCC_EN(padapter)) {
-+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
-+			for (i = 0; i < dvobj->iface_nums; i++) {
-+				iface = dvobj->padapters[i];
-+				mlmeext = &iface->mlmeextpriv;
-+				if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE) {
-+					#ifdef DBG_EXPIRATION_CHK
-+						RTW_INFO(FUNC_ADPT_FMT" don't enter %s under scan for MCC mode\n", FUNC_ADPT_ARG(padapter), msg);
-+					#endif
-+					ret = _FALSE;
-+					goto exit;
-+				}
-+			}
-+		}
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	_adapter *iface = NULL;
-+	systime start = rtw_get_current_time();
-+	u8 i = 0;
-+
-+	if (!MCC_EN(padapter))
-+		return;
-+
-+	if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
-+		return;
-+
-+	if (chbw_allow == _TRUE)
-+		return;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		/* issue null data to inform ap station will leave */
-+		if (is_client_associated_to_ap(iface)) {
-+			struct mlme_ext_priv *mlmeext = &iface->mlmeextpriv;
-+			struct mlme_ext_info *mlmeextinfo = &mlmeext->mlmext_info;
-+			u8 ch = mlmeext->cur_channel;
-+			u8 bw = mlmeext->cur_bwmode;
-+			u8 offset = mlmeext->cur_ch_offset;
-+			struct sta_info *sta = rtw_get_stainfo(&iface->stapriv, get_my_bssid(&(mlmeextinfo->network)));
-+
-+			if (!sta)
-+				continue;
-+
-+			set_channel_bwmode(iface, ch, offset, bw);
-+
-+			if (ps_mode)
-+				rtw_hal_macid_sleep(iface, sta->cmn.mac_id);
-+			else
-+				rtw_hal_macid_wakeup(iface, sta->cmn.mac_id);
-+
-+			issue_nulldata(iface, NULL, ps_mode, 3, 50);
-+		}
-+	}
-+	RTW_INFO("%s(%d ms)\n", __func__, rtw_get_passing_time_ms(start));
-+}
-+
-+u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len)
-+{
-+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
-+
-+	if (!MCC_EN(padapter))
-+		return pframe;
-+	
-+	if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
-+		return pframe;
-+
-+	if (pmccadapriv->p2p_go_noa_ie_len == 0)
-+		return pframe;
-+
-+	_rtw_memcpy(pframe, pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len);
-+	*len = *len + pmccadapriv->p2p_go_noa_ie_len;
-+
-+	return pframe + pmccadapriv->p2p_go_noa_ie_len;
-+}
-+
-+void rtw_hal_dump_mcc_policy_table(void *sel)
-+{
-+	u8 idx = 0;
-+	RTW_PRINT_SEL(sel, "duration\t,tsf sync offset\t,start time offset\t,interval\t,guard offset0\t,guard offset1\n");
-+
-+	for (idx = 0; idx < mcc_max_policy_num; idx ++) {
-+		RTW_PRINT_SEL(sel, "%d\t\t,%d\t\t\t,%d\t\t\t,%d\t\t,%d\t\t,%d\n"
-+			, mcc_switch_channel_policy_table[idx][MCC_DURATION_IDX]
-+			, mcc_switch_channel_policy_table[idx][MCC_TSF_SYNC_OFFSET_IDX]
-+			, mcc_switch_channel_policy_table[idx][MCC_START_TIME_OFFSET_IDX]
-+			, mcc_switch_channel_policy_table[idx][MCC_INTERVAL_IDX]
-+			, mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET0_IDX]
-+			, mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET1_IDX]);
-+	}
-+}
-+
-+void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add)
-+{
-+	struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
-+
-+	if (!MCC_EN(padapter))
-+		return;
-+
-+	if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
-+		return;
-+
-+	if (pmccadapriv->role == MCC_ROLE_GC || pmccadapriv->role == MCC_ROLE_STA)
-+		return;
-+
-+	if (mac_id < 0) {
-+		RTW_WARN("%s: mac_id < 0(%d)\n", __func__, mac_id);
-+		return;
-+	}
-+
-+	RTW_INFO(ADPT_FMT" %s macid=%d, ori mcc_macid_bitmap=0x%08x\n"
-+		, ADPT_ARG(padapter), add ? "add" : "clear"
-+		, mac_id, pmccadapriv->mcc_macid_bitmap);
-+
-+	if (add) {
-+		#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+		rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_ADD_CLIENT, &mac_id);
-+		#endif
-+		pmccadapriv->mcc_macid_bitmap |= BIT(mac_id);
-+	} else {
-+		#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+		rtw_hal_mcc_cfg_phydm(padapter, MCC_CFG_PHYDM_REMOVE_CLIENT, &mac_id);
-+		#endif
-+		pmccadapriv->mcc_macid_bitmap &= ~(BIT(mac_id));
-+	}
-+	rtw_hal_set_mcc_macid_cmd(padapter);
-+}
-+
-+void rtw_hal_mcc_process_noa(PADAPTER padapter)
-+{
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
-+
-+	if (!MCC_EN(padapter))
-+		return;
-+
-+	if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
-+		return;
-+
-+	if (!MLME_IS_GC(padapter))
-+		return;
-+
-+	switch(pwdinfo->p2p_ps_mode) {
-+	case P2P_PS_NONE:
-+		RTW_INFO("[MCC] Disable NoA under MCC\n");
-+		rtw_hal_mcc_update_parameter(padapter, _TRUE);
-+		break;
-+	case P2P_PS_NOA:
-+		RTW_INFO("[MCC] Enable NoA under MCC\n");
-+		break;
-+	default:
-+		break;
-+
-+	}
-+}
-+
-+void rtw_hal_mcc_parameter_init(PADAPTER padapter)
-+{
-+	if (!padapter->registrypriv.en_mcc)
-+		return;
-+
-+	if (is_primary_adapter(padapter)) {
-+		SET_MCC_EN_FLAG(padapter, padapter->registrypriv.en_mcc);
-+		SET_MCC_DURATION(padapter, padapter->registrypriv.rtw_mcc_duration);
-+		SET_MCC_RUNTIME_DURATION(padapter, padapter->registrypriv.rtw_mcc_enable_runtime_duration);
-+		SET_MCC_PHYDM_OFFLOAD(padapter, padapter->registrypriv.rtw_mcc_phydm_offload);
-+	}
-+}
-+
-+
-+static u8 set_mcc_duration_hdl(PADAPTER adapter, const u8 *val)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
-+	_adapter *iface = NULL;
-+	u8 duration = 50;
-+	u8 ret = _SUCCESS, noa_enable = _FALSE, i = 0;
-+	enum mcc_duration_setting type;
-+
-+	if (!mccobjpriv->enable_runtime_duration)
-+		goto exit;
-+
-+#ifdef CONFIG_P2P_PS
-+	/* check noa enable or not */
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
-+			noa_enable = _TRUE;
-+			break;
-+		}
-+	}
-+#endif /* CONFIG_P2P_PS */
-+
-+	type = val[0];
-+	duration = val[1];
-+
-+	if (type == MCC_DURATION_MAPPING) {
-+		switch (duration) {
-+			/* 0 = fair scheduling */
-+			case 0:
-+				mccobjpriv->duration= 40;
-+				mccobjpriv->policy_index = 2;
-+				mccobjpriv->mchan_sched_mode = MCC_FAIR_SCHEDULE;
-+				break;
-+			/* 1 = favor STA */
-+			case 1:
-+				mccobjpriv->duration= 70;
-+				mccobjpriv->policy_index = 1;
-+				mccobjpriv->mchan_sched_mode = MCC_FAVOR_STA;
-+				break;
-+			/* 2 = favor P2P*/
-+			case 2:
-+			default:
-+				mccobjpriv->duration= 30;
-+				mccobjpriv->policy_index = 0;
-+				mccobjpriv->mchan_sched_mode = MCC_FAVOR_P2P;
-+				break;
-+		}
-+	} else {
-+		mccobjpriv->duration = duration;
-+		rtw_hal_mcc_update_policy_table(adapter);
-+	}
-+
-+	/* only update sw parameter under MCC 
-+	    it will be force update during */
-+	if (noa_enable)
-+		goto exit;
-+
-+	if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
-+		rtw_hal_mcc_update_parameter(adapter, _TRUE);
-+exit:
-+	return ret;
-+}
-+
-+u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val)
-+{
-+	struct cmd_obj *cmdobj;
-+	struct drvextra_cmd_parm *pdrvextra_cmd_parm;
-+	struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+	u8 *buf = NULL;
-+	u8 sz = 2;
-+	u8 res = _SUCCESS;
-+
-+	
-+	cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+	if (cmdobj == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+	if (pdrvextra_cmd_parm == NULL) {
-+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	buf = rtw_zmalloc(sizeof(u8) * sz);
-+	if (buf == NULL) {
-+		rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+		rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	pdrvextra_cmd_parm->ec_id = MCC_CMD_WK_CID;
-+	pdrvextra_cmd_parm->type = MCC_SET_DURATION_WK_CID;
-+	pdrvextra_cmd_parm->size = sz;
-+	pdrvextra_cmd_parm->pbuf = buf;
-+
-+	_rtw_memcpy(buf, &type, 1);
-+	_rtw_memcpy(buf + 1, &val, 1);
-+
-+	init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+	res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+
-+exit:
-+	return res;
-+}
-+
-+#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+static u8 mcc_phydm_offload_enable_hdl(_adapter *adapter, const u8 *val)
-+{
-+	struct mcc_obj_priv *mccobjpriv =  adapter_to_mccobjpriv(adapter);
-+	u8 ret = _SUCCESS;
-+	u8 enable = *val;
-+
-+	/*only modify driver parameter during non-mcc status */
-+	if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
-+		mccobjpriv->mcc_phydm_offload = enable;
-+	} else {
-+		/*modify both driver & phydm parameter during mcc status */
-+		mccobjpriv->mcc_phydm_offload = enable;
-+		rtw_hal_mcc_cfg_phydm(adapter, MCC_CFG_PHYDM_OFFLOAD, &mccobjpriv->mcc_phydm_offload);
-+	}
-+
-+	RTW_INFO("[MCC] phydm offload enable hdl(%d)\n", mccobjpriv->mcc_phydm_offload);
-+
-+	return ret;
-+}
-+
-+u8 rtw_set_mcc_phydm_offload_enable_cmd(_adapter *adapter, u8 enable, u8 enqueue)
-+{
-+	u8 res = _SUCCESS;
-+
-+	if (enqueue) {
-+		struct cmd_obj *cmdobj;
-+		struct drvextra_cmd_parm *pdrvextra_cmd_parm;
-+		struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
-+		u8 *mcc_phydm_offload_enable = NULL;
-+
-+		
-+		cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
-+		if (cmdobj == NULL) {
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
-+		if (pdrvextra_cmd_parm == NULL) {
-+			rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		mcc_phydm_offload_enable = rtw_zmalloc(sizeof(u8));
-+		if (mcc_phydm_offload_enable == NULL) {
-+			rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
-+			rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
-+			res = _FAIL;
-+			goto exit;
-+		}
-+
-+		pdrvextra_cmd_parm->ec_id = MCC_CMD_WK_CID;
-+		pdrvextra_cmd_parm->type = MCC_SET_PHYDM_OFFLOAD_WK_CID;
-+		pdrvextra_cmd_parm->size = 1;
-+		pdrvextra_cmd_parm->pbuf = mcc_phydm_offload_enable;
-+
-+		_rtw_memcpy(mcc_phydm_offload_enable, &enable, 1);
-+		init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, CMD_SET_DRV_EXTRA);
-+		res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
-+	} else {
-+		mcc_phydm_offload_enable_hdl(adapter, &enable);
-+	}
-+
-+exit:
-+	return res;
-+}
-+#endif
-+
-+u8 rtw_mcc_cmd_hdl(_adapter *adapter, u8 type, const u8 *val)
-+{
-+	struct mcc_obj_priv *mccobjpriv =  adapter_to_mccobjpriv(adapter);
-+	u8 ret = _SUCCESS;
-+
-+	switch (type) {
-+	case MCC_SET_DURATION_WK_CID:
-+		set_mcc_duration_hdl(adapter, val);
-+		break;
-+	case MCC_GET_DBG_REG_WK_CID:
-+		mcc_get_reg_hdl(adapter, val);
-+		break;
-+	#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+	case MCC_SET_PHYDM_OFFLOAD_WK_CID:
-+		mcc_phydm_offload_enable_hdl(adapter, val);
-+		break;
-+	#endif
-+	default:
-+		RTW_ERR("[MCC] rtw_mcc_cmd_hdl fail(%d)\n", type);
-+		break;
-+	}
-+
-+
-+
-+	return ret;
-+}
-+
-+#endif /* CONFIG_MCC_MODE */
-diff --git a/drivers/staging/rtl8723cs/hal/hal_mp.c b/drivers/staging/rtl8723cs/hal/hal_mp.c
-new file mode 100644
-index 000000000000..63febafcfeda
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_mp.c
-@@ -0,0 +1,2642 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _HAL_MP_C_
-+
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_MP_INCLUDED
-+
-+#ifdef RTW_HALMAC
-+	#include <hal_data.h>		/* struct HAL_DATA_TYPE, RF register definition and etc. */
-+#else /* !RTW_HALMAC */
-+	#ifdef CONFIG_RTL8188E
-+		#include <rtl8188e_hal.h>
-+	#endif
-+	#ifdef CONFIG_RTL8723B
-+		#include <rtl8723b_hal.h>
-+	#endif
-+	#ifdef CONFIG_RTL8192E
-+		#include <rtl8192e_hal.h>
-+	#endif
-+	#ifdef CONFIG_RTL8814A
-+		#include <rtl8814a_hal.h>
-+	#endif
-+	#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+		#include <rtl8812a_hal.h>
-+	#endif
-+	#ifdef CONFIG_RTL8703B
-+		#include <rtl8703b_hal.h>
-+	#endif
-+	#ifdef CONFIG_RTL8723D
-+		#include <rtl8723d_hal.h>
-+	#endif
-+	#ifdef CONFIG_RTL8710B
-+		#include <rtl8710b_hal.h>
-+	#endif
-+	#ifdef CONFIG_RTL8188F
-+		#include <rtl8188f_hal.h>
-+	#endif
-+	#ifdef CONFIG_RTL8188GTV
-+		#include <rtl8188gtv_hal.h>
-+	#endif
-+	#ifdef CONFIG_RTL8192F
-+		#include <rtl8192f_hal.h>
-+	#endif
-+#endif /* !RTW_HALMAC */
-+
-+
-+u8 MgntQuery_NssTxRate(u16 Rate)
-+{
-+	u8	NssNum = RF_TX_NUM_NONIMPLEMENT;
-+
-+	if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) ||
-+	    (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9))
-+		NssNum = RF_2TX;
-+	else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) ||
-+		 (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9))
-+		NssNum = RF_3TX;
-+	else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) ||
-+		 (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9))
-+		NssNum = RF_4TX;
-+	else
-+		NssNum = RF_1TX;
-+
-+	return NssNum;
-+}
-+
-+void hal_mpt_SwitchRfSetting(PADAPTER	pAdapter)
-+{
-+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+	u8				ChannelToSw = pMptCtx->MptChannelToSw;
-+	u32				ulRateIdx = pMptCtx->mpt_rate_index;
-+	u32				ulbandwidth = pMptCtx->MptBandWidth;
-+
-+	/* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
-+	if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
-+	    (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
-+		pMptCtx->backup0x52_RF_A = (u8)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
-+		pMptCtx->backup0x52_RF_B = (u8)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
-+
-+		if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
-+			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
-+			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);
-+		} else {
-+			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
-+			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
-+		}
-+	} else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
-+		if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
-+			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
-+			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
-+		} else {
-+			phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
-+			phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
-+		}
-+	} else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
-+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
-+	}
-+}
-+
-+s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
-+
-+
-+	if (!netif_running(padapter->pnetdev)) {
-+		return _FAIL;
-+	}
-+
-+	if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
-+		return _FAIL;
-+	}
-+	if (enable)
-+		pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
-+	else
-+		pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
-+
-+	return _SUCCESS;
-+}
-+
-+void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
-+
-+
-+	*enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;
-+}
-+
-+
-+void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
-+{
-+	u32		TempVal = 0, TempVal2 = 0, TempVal3 = 0;
-+	u32		CurrCCKSwingVal = 0, CCKSwingIndex = 12;
-+	u8		i;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	PMPT_CONTEXT		pMptCtx = &(Adapter->mppriv.mpt_ctx);
-+	u8				u1Channel = pHalData->current_channel;
-+	u32				ulRateIdx = pMptCtx->mpt_rate_index;
-+	u8				DataRate = 0xFF;
-+
-+	/* Do not modify CCK TX filter parameters for 8822B*/
-+	if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) ||
-+		IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter) || IS_HARDWARE_TYPE_8822C(Adapter))
-+		return;
-+
-+	DataRate = mpt_to_mgnt_rate(ulRateIdx);
-+
-+	if (u1Channel == 14 && IS_CCK_RATE(DataRate))
-+		pHalData->bCCKinCH14 = TRUE;
-+	else
-+		pHalData->bCCKinCH14 = FALSE;
-+
-+	if (IS_HARDWARE_TYPE_8703B(Adapter)) {
-+		if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
-+			/* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
-+			phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
-+			phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
-+
-+		} else {
-+			/* Normal setting for 8703B, just recover to the default setting. */
-+			/* This hardcore values reference from the parameter which BB team gave. */
-+			for (i = 0 ; i < 2 ; ++i)
-+				phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
-+
-+		}
-+	} else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
-+		/* 2.4G CCK TX DFIR */
-+		/* 2016.01.20 Suggest from RS BB mingzhi*/
-+		if (u1Channel == 14) {
-+			phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
-+			phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
-+			phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
-+		} else {
-+			for (i = 0 ; i < 3 ; ++i) {
-+				phy_set_bb_reg(Adapter,
-+					     pHalData->RegForRecover[i].offset,
-+					     bMaskDWord,
-+					     pHalData->RegForRecover[i].value);
-+			}
-+		}
-+	} else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
-+		/* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
-+		CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
-+		CCKSwingIndex = 20; /* default index */
-+
-+		if (!pHalData->bCCKinCH14) {
-+			/* Readback the current bb cck swing value and compare with the table to */
-+			/* get the current swing index */
-+			for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
-+				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
-+				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
-+					CCKSwingIndex = i;
-+					break;
-+				}
-+			}
-+			write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
-+			write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
-+			write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
-+			write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
-+			write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
-+			write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
-+			write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
-+			write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
-+			write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
-+			write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
-+			write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
-+			write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
-+			write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
-+			write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
-+			write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
-+			write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
-+			RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
-+		}  else {
-+			for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
-+				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
-+				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
-+					CCKSwingIndex = i;
-+					break;
-+				}
-+			}
-+			write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
-+			write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
-+			write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
-+			write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
-+			write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
-+			write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
-+			write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
-+			write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
-+			write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
-+			write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
-+			write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
-+			write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
-+			write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
-+			write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
-+			write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
-+			write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
-+			RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
-+		}
-+	} else {
-+
-+		/* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
-+		CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
-+
-+		if (!pHalData->bCCKinCH14) {
-+			/* Readback the current bb cck swing value and compare with the table to */
-+			/* get the current swing index */
-+			for (i = 0; i < CCK_TABLE_SIZE; i++) {
-+				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&
-+				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {
-+					CCKSwingIndex = i;
-+					break;
-+				}
-+			}
-+
-+			/*Write 0xa22 0xa23*/
-+			TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +
-+				(cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);
-+
-+
-+			/*Write 0xa24 ~ 0xa27*/
-+			TempVal2 = 0;
-+			TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +
-+				(cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +
-+				(cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +
-+				(cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);
-+
-+			/*Write 0xa28  0xa29*/
-+			TempVal3 = 0;
-+			TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +
-+				(cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);
-+		}  else {
-+			for (i = 0; i < CCK_TABLE_SIZE; i++) {
-+				if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&
-+				    (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {
-+					CCKSwingIndex = i;
-+					break;
-+				}
-+			}
-+
-+			/*Write 0xa22 0xa23*/
-+			TempVal = cck_swing_table_ch14[CCKSwingIndex][0] +
-+				  (cck_swing_table_ch14[CCKSwingIndex][1] << 8);
-+
-+			/*Write 0xa24 ~ 0xa27*/
-+			TempVal2 = 0;
-+			TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +
-+				   (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +
-+				(cck_swing_table_ch14[CCKSwingIndex][4] << 16) +
-+				   (cck_swing_table_ch14[CCKSwingIndex][5] << 24);
-+
-+			/*Write 0xa28  0xa29*/
-+			TempVal3 = 0;
-+			TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +
-+				   (cck_swing_table_ch14[CCKSwingIndex][7] << 8);
-+		}
-+
-+		write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
-+		write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
-+		write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
-+	}
-+
-+}
-+
-+void hal_mpt_SetChannel(PADAPTER pAdapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	struct mp_priv	*pmp = &pAdapter->mppriv;
-+	u8		channel = pmp->channel;
-+	u8		bandwidth = pmp->bandwidth;
-+
-+	hal_mpt_SwitchRfSetting(pAdapter);
-+
-+	pHalData->bSwChnl = _TRUE;
-+	pHalData->bSetChnlBW = _TRUE;
-+
-+	if (bandwidth == 2) {
-+		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
-+	} else if (bandwidth == 1) {
-+		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
-+	} else
-+		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
-+
-+	hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
-+	rtw_btcoex_wifionly_scan_notify(pAdapter);
-+
-+}
-+
-+/*
-+ * Notice
-+ *	Switch bandwitdth may change center frequency(channel)
-+ */
-+void hal_mpt_SetBandwidth(PADAPTER pAdapter)
-+{
-+	struct mp_priv *pmp = &pAdapter->mppriv;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+
-+	u8		channel = pmp->channel;
-+	u8		bandwidth = pmp->bandwidth;
-+
-+	pHalData->bSwChnl = _TRUE;
-+	pHalData->bSetChnlBW = _TRUE;
-+
-+	if (bandwidth == 2) {
-+		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER);
-+	} else if (bandwidth == 1) {
-+		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0);
-+	} else
-+		rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0);
-+
-+	hal_mpt_SwitchRfSetting(pAdapter);
-+	rtw_btcoex_wifionly_scan_notify(pAdapter);
-+
-+}
-+
-+void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
-+{
-+	switch (Rate) {
-+	case MPT_CCK: {
-+		u32	TxAGC = 0, pwr = 0;
-+
-+		pwr = pTxPower[RF_PATH_A];
-+		if (pwr < 0x3f) {
-+			TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
-+			phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]);
-+			phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
-+		}
-+		pwr = pTxPower[RF_PATH_B];
-+		if (pwr < 0x3f) {
-+			TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
-+			phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]);
-+			phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
-+		}
-+	}
-+	break;
-+
-+	case MPT_OFDM_AND_HT: {
-+		u32	TxAGC = 0;
-+		u8	pwr = 0;
-+
-+		pwr = pTxPower[0];
-+		if (pwr < 0x3f) {
-+			TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
-+			RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
-+			phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
-+			phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
-+			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
-+			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
-+			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
-+			phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
-+		}
-+		TxAGC = 0;
-+		pwr = pTxPower[1];
-+		if (pwr < 0x3f) {
-+			TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
-+			RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
-+			phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
-+			phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
-+			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
-+			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
-+			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
-+			phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
-+		}
-+	}
-+	break;
-+
-+	default:
-+		break;
-+	}
-+	RTW_INFO("<===mpt_SetTxPower_Old()\n");
-+}
-+
-+void
-+mpt_SetTxPower(
-+	PADAPTER		pAdapter,
-+	MPT_TXPWR_DEF	Rate,
-+	u8 *pTxPower
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+
-+	u8 path = 0 , i = 0, MaxRate = MGN_6M;
-+	u8 StartPath = RF_PATH_A, EndPath = RF_PATH_B;
-+	u8 tx_nss = 2;
-+
-+	if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8814B(pAdapter)) {
-+		EndPath = RF_PATH_D;
-+		tx_nss = 4;
-+	} else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)
-+		|| IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
-+		EndPath = RF_PATH_A;
-+		tx_nss = 1;
-+	}
-+
-+	switch (Rate) {
-+	case MPT_CCK: {
-+		u8 rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
-+
-+		for (path = StartPath; path <= EndPath; path++)
-+			for (i = 0; i < sizeof(rate); ++i)
-+				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
-+	}
-+	break;
-+	case MPT_OFDM: {
-+		u8 rate[] = {
-+			MGN_6M, MGN_9M, MGN_12M, MGN_18M,
-+			MGN_24M, MGN_36M, MGN_48M, MGN_54M,
-+		};
-+
-+		for (path = StartPath; path <= EndPath; path++)
-+			for (i = 0; i < sizeof(rate); ++i)
-+				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
-+	}
-+	break;
-+	case MPT_HT: {
-+		u8 rate[] = {
-+			MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4,
-+			MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9,
-+			MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14,
-+			MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19,
-+			MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24,
-+			MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29,
-+			MGN_MCS30, MGN_MCS31,
-+		};
-+		if (tx_nss == 4)
-+			MaxRate = MGN_MCS31;
-+		else if (tx_nss == 3)
-+			MaxRate = MGN_MCS23;
-+		else if (tx_nss == 2)
-+			MaxRate = MGN_MCS15;
-+		else
-+			MaxRate = MGN_MCS7;
-+
-+		for (path = StartPath; path <= EndPath; path++) {
-+			for (i = 0; i < sizeof(rate); ++i) {
-+				if (rate[i] > MaxRate)
-+					break;
-+				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
-+			}
-+		}
-+	}
-+	break;
-+	case MPT_VHT: {
-+		u8 rate[] = {
-+			MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
-+			MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9,
-+			MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
-+			MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9,
-+			MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
-+			MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9,
-+			MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
-+			MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9,
-+		};
-+		if (tx_nss == 4)
-+			MaxRate = MGN_VHT4SS_MCS9;
-+		else if (tx_nss == 3)
-+			MaxRate = MGN_VHT3SS_MCS9;
-+		else if (tx_nss == 2)
-+			MaxRate = MGN_VHT2SS_MCS9;
-+		else
-+			MaxRate = MGN_VHT1SS_MCS9;
-+
-+		for (path = StartPath; path <= EndPath; path++) {
-+			for (i = 0; i < sizeof(rate); ++i) {
-+				if (rate[i] > MaxRate)
-+					break;
-+				PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]);
-+			}
-+		}
-+	}
-+	break;
-+	default:
-+		RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n");
-+		break;
-+	}
-+}
-+
-+void hal_mpt_SetTxPower(PADAPTER pAdapter)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
-+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
-+
-+	if (pHalData->rf_chip < RF_CHIP_MAX) {
-+		if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
-+		    IS_HARDWARE_TYPE_8723B(pAdapter) ||
-+		    IS_HARDWARE_TYPE_8192E(pAdapter) ||
-+		    IS_HARDWARE_TYPE_8703B(pAdapter) ||
-+		    IS_HARDWARE_TYPE_8188F(pAdapter) ||
-+		    IS_HARDWARE_TYPE_8188GTV(pAdapter)
-+		) {
-+
-+			RTW_INFO("===> MPT_ProSetTxPower: Old\n");
-+
-+			mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
-+			mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
-+
-+		} else {
-+
-+			mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
-+			mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel);
-+			mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel);
-+			if(IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
-+				RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n");
-+				mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel);
-+			}
-+		}
-+
-+		rtw_hal_set_txpwr_done(pAdapter);
-+	} else
-+		RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
-+
-+	odm_clear_txpowertracking_state(pDM_Odm);
-+}
-+
-+void hal_mpt_SetDataRate(PADAPTER pAdapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+	u32 DataRate;
-+
-+	DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
-+
-+	hal_mpt_SwitchRfSetting(pAdapter);
-+
-+	hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
-+#ifdef CONFIG_RTL8723B
-+	if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
-+		if (IS_CCK_RATE(DataRate)) {
-+			if (pMptCtx->mpt_rf_path == RF_PATH_A)
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);
-+			else
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6);
-+		} else {
-+			if (pMptCtx->mpt_rf_path == RF_PATH_A)
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
-+			else
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
-+		}
-+	}
-+
-+	if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
-+	     ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
-+		if (pMptCtx->mpt_rf_path == RF_PATH_A)
-+			phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
-+		else
-+			phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
-+	}
-+#endif
-+}
-+
-+#define RF_PATH_AB	22
-+
-+#ifdef CONFIG_RTL8814A
-+void mpt_ToggleIG_8814A(PADAPTER	pAdapter)
-+{
-+	u8 Path;
-+	u32 IGReg = rA_IGI_Jaguar, IGvalue = 0;
-+
-+	for (Path = 0; Path <= RF_PATH_D; Path++) {
-+		switch (Path) {
-+		case RF_PATH_B:
-+			IGReg = rB_IGI_Jaguar;
-+			break;
-+		case RF_PATH_C:
-+			IGReg = rC_IGI_Jaguar2;
-+			break;
-+		case RF_PATH_D:
-+			IGReg = rD_IGI_Jaguar2;
-+			break;
-+		default:
-+			IGReg = rA_IGI_Jaguar;
-+			break;
-+		}
-+
-+		IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);
-+		phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
-+		phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);
-+	}
-+}
-+
-+void mpt_SetRFPath_8814A(PADAPTER	pAdapter)
-+{
-+
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	PMPT_CONTEXT	pMptCtx = &pAdapter->mppriv.mpt_ctx;
-+	R_ANTENNA_SELECT_OFDM	*p_ofdm_tx;	/* OFDM Tx register */
-+	R_ANTENNA_SELECT_CCK	*p_cck_txrx;
-+	u8	ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
-+	/*/PRT_HIGH_THROUGHPUT		pHTInfo = GET_HT_INFO(pMgntInfo);*/
-+	/*/PRT_VERY_HIGH_THROUGHPUT	pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
-+
-+	u32	ulAntennaTx = pHalData->antenna_tx_path;
-+	u32	ulAntennaRx = pHalData->AntennaRxPath;
-+	u8	NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
-+
-+	if (NssforRate == RF_3TX) {
-+		RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
-+
-+		switch (ulAntennaTx) {
-+		case ANTENNA_BCD:
-+			pMptCtx->mpt_rf_path = RF_PATH_BCD;
-+			/*pHalData->ValidTxPath = 0x0e;*/
-+			phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e);	/*/ 0x940[27:16]=12'b0010_0100_0111*/
-+			break;
-+
-+		case ANTENNA_ABC:
-+		default:
-+			pMptCtx->mpt_rf_path = RF_PATH_ABC;
-+			/*pHalData->ValidTxPath = 0x0d;*/
-+			phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247);	/*/ 0x940[27:16]=12'b0010_0100_0111*/
-+			break;
-+		}
-+
-+	} else { /*/if(NssforRate == RF_1TX)*/
-+		RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
-+		switch (ulAntennaTx) {
-+		case ANTENNA_BCD:
-+			pMptCtx->mpt_rf_path = RF_PATH_BCD;
-+			/*pHalData->ValidTxPath = 0x0e;*/
-+			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
-+			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
-+			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
-+			break;
-+
-+		case ANTENNA_BC:
-+			pMptCtx->mpt_rf_path = RF_PATH_BC;
-+			/*pHalData->ValidTxPath = 0x06;*/
-+			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
-+			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
-+			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
-+			break;
-+		case ANTENNA_B:
-+			pMptCtx->mpt_rf_path = RF_PATH_B;
-+			/*pHalData->ValidTxPath = 0x02;*/
-+			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4);			/*/ 0xa07[7:4] = 4'b0100*/
-+			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002);	/*/ 0x93C[31:20]=12'b0000_0000_0010*/
-+			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2);					/* 0x80C[7:4] = 4'b0010*/
-+			break;
-+
-+		case ANTENNA_C:
-+			pMptCtx->mpt_rf_path = RF_PATH_C;
-+			/*pHalData->ValidTxPath = 0x04;*/
-+			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2);			/*/ 0xa07[7:4] = 4'b0010*/
-+			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004);	/*/ 0x93C[31:20]=12'b0000_0000_0100*/
-+			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4);					/*/ 0x80C[7:4] = 4'b0100*/
-+			break;
-+
-+		case ANTENNA_D:
-+			pMptCtx->mpt_rf_path = RF_PATH_D;
-+			/*pHalData->ValidTxPath = 0x08;*/
-+			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1);			/*/ 0xa07[7:4] = 4'b0001*/
-+			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008);	/*/ 0x93C[31:20]=12'b0000_0000_1000*/
-+			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8);					/*/ 0x80C[7:4] = 4'b1000*/
-+			break;
-+
-+		case ANTENNA_A:
-+		default:
-+			pMptCtx->mpt_rf_path = RF_PATH_A;
-+			/*pHalData->ValidTxPath = 0x01;*/
-+			phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8);			/*/ 0xa07[7:4] = 4'b1000*/
-+			phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001);	/*/ 0x93C[31:20]=12'b0000_0000_0001*/
-+			phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1);					/*/ 0x80C[7:4] = 4'b0001*/
-+			break;
-+		}
-+	}
-+
-+	switch (ulAntennaRx) {
-+	case ANTENNA_A:
-+		/*pHalData->ValidRxPath = 0x01;*/
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
-+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
-+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
-+		/*/ CCA related PD_delay_th*/
-+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
-+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
-+		break;
-+
-+	case ANTENNA_B:
-+		/*pHalData->ValidRxPath = 0x02;*/
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
-+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
-+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
-+		/*/ CCA related PD_delay_th*/
-+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
-+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
-+		break;
-+
-+	case ANTENNA_C:
-+		/*pHalData->ValidRxPath = 0x04;*/
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
-+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
-+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
-+		/*/ CCA related PD_delay_th*/
-+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
-+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
-+		break;
-+
-+	case ANTENNA_D:
-+		/*pHalData->ValidRxPath = 0x08;*/
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
-+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
-+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
-+		/*/ CCA related PD_delay_th*/
-+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
-+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
-+		break;
-+
-+	case ANTENNA_BC:
-+		/*pHalData->ValidRxPath = 0x06;*/
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
-+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
-+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
-+		/*/ CCA related PD_delay_th*/
-+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
-+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
-+		break;
-+
-+	case ANTENNA_CD:
-+		/*pHalData->ValidRxPath = 0x0C;*/
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
-+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
-+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
-+		/*/ CCA related PD_delay_th*/
-+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
-+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
-+		break;
-+
-+	case ANTENNA_BCD:
-+		/*pHalData->ValidRxPath = 0x0e;*/
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
-+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
-+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
-+		/*/ CCA related PD_delay_th*/
-+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
-+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
-+		break;
-+
-+	case ANTENNA_ABCD:
-+		/*pHalData->ValidRxPath = 0x0f;*/
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
-+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
-+		phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
-+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
-+		phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
-+		/*/ CCA related PD_delay_th*/
-+		phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
-+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
-+
-+	mpt_ToggleIG_8814A(pAdapter);
-+}
-+
-+#endif /* CONFIG_RTL8814A */
-+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) \
-+	|| defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) || defined(CONFIG_RTL8723F)
-+void
-+mpt_SetSingleTone_8814A(
-+		PADAPTER	pAdapter,
-+		BOOLEAN	bSingleTone,
-+		BOOLEAN	bEnPMacTx)
-+{
-+
-+	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+	u8 StartPath = RF_PATH_A,  EndPath = RF_PATH_A, path;
-+	static u32		regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
-+
-+	if (bSingleTone) {
-+		regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord);		/*/ 0xC1C[31:21]*/
-+		regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord);		/*/ 0xE1C[31:21]*/
-+		regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord);	/*/ 0x181C[31:21]*/
-+		regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord);	/*/ 0x1A1C[31:21]*/
-+
-+		switch (pMptCtx->mpt_rf_path) {
-+		case RF_PATH_A:
-+		case RF_PATH_B:
-+		case RF_PATH_C:
-+		case RF_PATH_D:
-+			StartPath = pMptCtx->mpt_rf_path;
-+			EndPath = pMptCtx->mpt_rf_path;
-+			break;
-+		case RF_PATH_AB:
-+			EndPath = RF_PATH_B;
-+			break;
-+		case RF_PATH_BC:
-+			StartPath = RF_PATH_B;
-+			EndPath = RF_PATH_C;
-+			break;
-+		case RF_PATH_ABC:
-+			EndPath = RF_PATH_C;
-+			break;
-+		case RF_PATH_BCD:
-+			StartPath = RF_PATH_B;
-+			EndPath = RF_PATH_D;
-+			break;
-+		case RF_PATH_ABCD:
-+			EndPath = RF_PATH_D;
-+			break;
-+		}
-+
-+		if (bEnPMacTx == FALSE) {
-+			hal_mpt_SetContinuousTx(pAdapter, _TRUE);
-+			issue_nulldata(pAdapter, NULL, 1, 3, 500);
-+		}
-+
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
-+
-+		for (path = StartPath; path <= EndPath; path++) {
-+			phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
-+			phy_set_rf_reg(pAdapter, path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
-+
-+			phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
-+		}
-+
-+		phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
-+		phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
-+		phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
-+		phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
-+	} else {
-+		switch (pMptCtx->mpt_rf_path) {
-+		case RF_PATH_A:
-+		case RF_PATH_B:
-+		case RF_PATH_C:
-+		case RF_PATH_D:
-+			StartPath = pMptCtx->mpt_rf_path;
-+			EndPath = pMptCtx->mpt_rf_path;
-+			break;
-+		case RF_PATH_AB:
-+			EndPath = RF_PATH_B;
-+			break;
-+		case RF_PATH_BC:
-+			StartPath = RF_PATH_B;
-+			EndPath = RF_PATH_C;
-+			break;
-+		case RF_PATH_ABC:
-+			EndPath = RF_PATH_C;
-+			break;
-+		case RF_PATH_BCD:
-+			StartPath = RF_PATH_B;
-+			EndPath = RF_PATH_D;
-+			break;
-+		case RF_PATH_ABCD:
-+			EndPath = RF_PATH_D;
-+			break;
-+		}
-+		for (path = StartPath; path <= EndPath; path++)
-+			phy_set_rf_reg(pAdapter, path, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
-+
-+		phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
-+
-+		if (bEnPMacTx == FALSE) {
-+			if(IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
-+#ifdef	PHYDM_MP_SUPPORT
-+					phydm_stop_ofdm_cont_tx(pAdapter);
-+					pMptCtx->bCckContTx = FALSE;
-+					pMptCtx->bOfdmContTx = FALSE;
-+#endif
-+			} else
-+					hal_mpt_SetContinuousTx(pAdapter, _FALSE);
-+		}
-+
-+		phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
-+		phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
-+		phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
-+		phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
-+	}
-+}
-+
-+#endif
-+
-+#if	defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+void mpt_SetRFPath_8812A(PADAPTER pAdapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	PMPT_CONTEXT	pMptCtx = &pAdapter->mppriv.mpt_ctx;
-+	struct mp_priv *pmp = &pAdapter->mppriv;
-+	u8		channel = pmp->channel;
-+	u8		bandwidth = pmp->bandwidth;
-+	u8		eLNA_2g = pHalData->ExternalLNA_2G;
-+	u32		ulAntennaTx, ulAntennaRx;
-+	u32 reg0xC50 = 0;
-+
-+	ulAntennaTx = pHalData->antenna_tx_path;
-+	ulAntennaRx = pHalData->AntennaRxPath;
-+
-+	switch (ulAntennaTx) {
-+	case ANTENNA_A:
-+		pMptCtx->mpt_rf_path = RF_PATH_A;
-+		phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
-+		if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
-+			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
-+		break;
-+	case ANTENNA_B:
-+		pMptCtx->mpt_rf_path = RF_PATH_B;
-+		phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
-+		if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
-+			phy_set_bb_reg(pAdapter,	r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
-+		break;
-+	case ANTENNA_AB:
-+		pMptCtx->mpt_rf_path = RF_PATH_AB;
-+		phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
-+		if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
-+			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
-+		break;
-+	default:
-+		pMptCtx->mpt_rf_path = RF_PATH_AB;
-+		RTW_INFO("Unknown Tx antenna.\n");
-+		break;
-+	}
-+
-+	switch (ulAntennaRx) {
-+	case ANTENNA_A:
-+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
-+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
-+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
-+
-+		/*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
-+		reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
-+		phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
-+		phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
-+
-+		/* set PWED_TH for BB Yn user guide R29 */
-+		if (IS_HARDWARE_TYPE_8812(pAdapter)) {
-+			if (channel <= 14) { /* 2.4G */
-+				if (bandwidth == CHANNEL_WIDTH_20
-+				    && eLNA_2g == 0) {
-+					/* 0x830[3:1]=3'b010 */
-+					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
-+				} else
-+					/* 0x830[3:1]=3'b100 */
-+					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
-+			} else
-+				/* 0x830[3:1]=3'b100 for 5G */
-+				phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
-+		}
-+		break;
-+	case ANTENNA_B:
-+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
-+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
-+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
-+
-+		/*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
-+		reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
-+		phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
-+		phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
-+
-+		/* set PWED_TH for BB Yn user guide R29 */
-+		if (IS_HARDWARE_TYPE_8812(pAdapter)) {
-+			if (channel <= 14) {
-+				if (bandwidth == CHANNEL_WIDTH_20
-+				    && eLNA_2g == 0) {
-+					/* 0x830[3:1]=3'b010 */
-+					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
-+				} else
-+					/* 0x830[3:1]=3'b100 */
-+					phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
-+			} else
-+				/* 0x830[3:1]=3'b100 for 5G */
-+				phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
-+		}
-+		break;
-+	case ANTENNA_AB:
-+		phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
-+		phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
-+		phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
-+		/* set PWED_TH for BB Yn user guide R29 */
-+		phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
-+		break;
-+	default:
-+		RTW_INFO("Unknown Rx antenna.\n");
-+		break;
-+	}
-+
-+	if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) {
-+		if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) {
-+			/* WiFi */
-+			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2);
-+			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
-+		} else {
-+			/* BT */
-+			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1);
-+			phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
-+		}
-+	}
-+}
-+#endif
-+
-+#ifdef CONFIG_RTL8723B
-+void mpt_SetRFPath_8723B(PADAPTER pAdapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	u32		ulAntennaTx, ulAntennaRx;
-+	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+	struct dm_struct	*pDM_Odm = &pHalData->odmpriv;
-+	struct dm_rf_calibration_struct	*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
-+	u8 i;
-+
-+	ulAntennaTx = pHalData->antenna_tx_path;
-+	ulAntennaRx = pHalData->AntennaRxPath;
-+
-+	if (pHalData->rf_chip >= RF_CHIP_MAX) {
-+		RTW_INFO("This RF chip ID is not supported\n");
-+		return;
-+	}
-+
-+	switch (pAdapter->mppriv.antenna_tx) {
-+	case ANTENNA_A: { /*/ Actually path S1  (Wi-Fi)*/
-+		pMptCtx->mpt_rf_path = RF_PATH_A;
-+		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
-+		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
-+
-+		for (i = 0; i < 3; ++i) {
-+			u32 offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
-+			u32 data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
-+
-+			if (offset != 0) {
-+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
-+				RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
-+			}
-+		}
-+		for (i = 0; i < 2; ++i) {
-+			u32 offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
-+			u32 data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
-+
-+			if (offset != 0) {
-+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
-+				RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
-+			}
-+		}
-+	}
-+	break;
-+	case ANTENNA_B: { /*/ Actually path S0 (BT)*/
-+		u32 offset;
-+		u32 data;
-+
-+		pMptCtx->mpt_rf_path = RF_PATH_B;
-+		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
-+		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
-+
-+		for (i = 0; i < 3; ++i) {
-+			/*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC  to S1 instead of S0.*/
-+			offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
-+			data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1];
-+			if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) {
-+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
-+				RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
-+			}
-+		}
-+		/*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
-+		for (i = 0; i < 2; ++i) {
-+			offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
-+			data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1];
-+			if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) {
-+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
-+				RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
-+			}
-+		}
-+	}
-+	break;
-+	default:
-+		pMptCtx->mpt_rf_path = RF_PATH_AB;
-+		break;
-+	}
-+}
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+void mpt_SetRFPath_8703B(PADAPTER pAdapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	u32					ulAntennaTx, ulAntennaRx;
-+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
-+	struct dm_rf_calibration_struct			*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
-+	u8 i;
-+
-+	ulAntennaTx = pHalData->antenna_tx_path;
-+	ulAntennaRx = pHalData->AntennaRxPath;
-+
-+	if (pHalData->rf_chip >= RF_CHIP_MAX) {
-+		RTW_INFO("This RF chip ID is not supported\n");
-+		return;
-+	}
-+
-+	switch (pAdapter->mppriv.antenna_tx) {
-+	case ANTENNA_A: { /* Actually path S1  (Wi-Fi) */
-+		pMptCtx->mpt_rf_path = RF_PATH_A;
-+		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
-+		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
-+
-+		for (i = 0; i < 3; ++i) {
-+			u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
-+			u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
-+
-+			if (offset != 0) {
-+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
-+				RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
-+			}
-+
-+		}
-+		for (i = 0; i < 2; ++i) {
-+			u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
-+			u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
-+
-+			if (offset != 0) {
-+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
-+				RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
-+			}
-+		}
-+	}
-+	break;
-+	case ANTENNA_B: { /* Actually path S0 (BT)*/
-+		pMptCtx->mpt_rf_path = RF_PATH_B;
-+		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
-+		phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
-+
-+		for (i = 0; i < 3; ++i) {
-+			u32 offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
-+			u32 data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
-+
-+			if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
-+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
-+				RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
-+			}
-+		}
-+		for (i = 0; i < 2; ++i) {
-+			u32 offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
-+			u32 data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
-+
-+			if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
-+				phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
-+				RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
-+			}
-+		}
-+	}
-+	break;
-+	default:
-+		pMptCtx->mpt_rf_path = RF_PATH_AB;
-+		break;
-+	}
-+
-+}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+void mpt_SetRFPath_8723D(PADAPTER pAdapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	u8	p = 0, i = 0;
-+	u32	ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
-+	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+	struct dm_struct	*pDM_Odm = &pHalData->odmpriv;
-+	struct dm_rf_calibration_struct	*pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
-+
-+	ulAntennaTx = pHalData->antenna_tx_path;
-+	ulAntennaRx = pHalData->AntennaRxPath;
-+
-+	if (pHalData->rf_chip >= RF_CHIP_MAX) {
-+		RTW_INFO("This RF chip ID is not supported\n");
-+		return;
-+	}
-+
-+	switch (pAdapter->mppriv.antenna_tx) {
-+	/* Actually path S1  (Wi-Fi) */
-+	case ANTENNA_A: {
-+		pMptCtx->mpt_rf_path = RF_PATH_A;
-+		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
-+	}
-+	break;
-+	/* Actually path S0 (BT) */
-+	case ANTENNA_B: {
-+		pMptCtx->mpt_rf_path = RF_PATH_B;
-+		phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
-+
-+	}
-+	break;
-+	default:
-+		pMptCtx->mpt_rf_path = RF_PATH_AB;
-+		break;
-+	}
-+}
-+#endif
-+
-+void mpt_SetRFPath_819X(PADAPTER	pAdapter)
-+{
-+	HAL_DATA_TYPE			*pHalData	= GET_HAL_DATA(pAdapter);
-+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+	u32			ulAntennaTx, ulAntennaRx;
-+	R_ANTENNA_SELECT_OFDM	*p_ofdm_tx;	/* OFDM Tx register */
-+	R_ANTENNA_SELECT_CCK	*p_cck_txrx;
-+	u8		r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
-+	u8		chgTx = 0, chgRx = 0;
-+	u32		r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
-+
-+	ulAntennaTx = pHalData->antenna_tx_path;
-+	ulAntennaRx = pHalData->AntennaRxPath;
-+
-+	p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
-+	p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
-+
-+	p_ofdm_tx->r_ant_ht1			= 0x1;
-+	p_ofdm_tx->r_ant_ht2			= 0x2;/*Second TX RF path is A*/
-+	p_ofdm_tx->r_ant_non_ht			= 0x3;/*/ 0x1+0x2=0x3 */
-+
-+	switch (ulAntennaTx) {
-+	case ANTENNA_A:
-+		p_ofdm_tx->r_tx_antenna		= 0x1;
-+		r_ofdm_tx_en_val		= 0x1;
-+		p_ofdm_tx->r_ant_l		= 0x1;
-+		p_ofdm_tx->r_ant_ht_s1		= 0x1;
-+		p_ofdm_tx->r_ant_non_ht_s1	= 0x1;
-+		p_cck_txrx->r_ccktx_enable	= 0x8;
-+		chgTx = 1;
-+		/*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
-+		/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
-+		{
-+			phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
-+			phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
-+			r_ofdm_tx_en_val			= 0x3;
-+			/*/ Power save*/
-+			/*/cosa r_ant_select_ofdm_val = 0x11111111;*/
-+			/*/ We need to close RFB by SW control*/
-+			if (pHalData->rf_type == RF_2T2R) {
-+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
-+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
-+				phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
-+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
-+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
-+			}
-+		}
-+		pMptCtx->mpt_rf_path = RF_PATH_A;
-+		break;
-+	case ANTENNA_B:
-+		p_ofdm_tx->r_tx_antenna		= 0x2;
-+		r_ofdm_tx_en_val		= 0x2;
-+		p_ofdm_tx->r_ant_l		= 0x2;
-+		p_ofdm_tx->r_ant_ht_s1		= 0x2;
-+		p_ofdm_tx->r_ant_non_ht_s1	= 0x2;
-+		p_cck_txrx->r_ccktx_enable	= 0x4;
-+		chgTx = 1;
-+		/*/ From SD3 Willis suggestion !!! Set RF A as standby*/
-+		/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
-+		{
-+			phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
-+			phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
-+
-+			/*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
-+			/*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
-+			if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
-+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
-+				phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
-+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
-+				/*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
-+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
-+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
-+			}
-+		}
-+		pMptCtx->mpt_rf_path = RF_PATH_B;
-+		break;
-+	case ANTENNA_AB:/*/ For 8192S*/
-+		p_ofdm_tx->r_tx_antenna		= 0x3;
-+		r_ofdm_tx_en_val		= 0x3;
-+		p_ofdm_tx->r_ant_l		= 0x3;
-+		p_ofdm_tx->r_ant_ht_s1		= 0x3;
-+		p_ofdm_tx->r_ant_non_ht_s1	= 0x3;
-+		p_cck_txrx->r_ccktx_enable	= 0xC;
-+		chgTx = 1;
-+		/*/ From SD3Willis suggestion !!! Set RF B as standby*/
-+		/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
-+		{
-+			phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
-+			phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
-+			/* Disable Power save*/
-+			/*cosa r_ant_select_ofdm_val = 0x3321333;*/
-+			/* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
-+			if (pHalData->rf_type == RF_2T2R) {
-+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
-+
-+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
-+				/*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
-+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
-+				phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
-+			}
-+		}
-+		pMptCtx->mpt_rf_path = RF_PATH_AB;
-+		break;
-+	default:
-+		break;
-+	}
-+#if 0
-+	/*  r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
-+	/*  r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
-+	/* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D	 */
-+#endif
-+	switch (ulAntennaRx) {
-+	case ANTENNA_A:
-+		r_rx_antenna_ofdm		= 0x1;	/* A*/
-+		p_cck_txrx->r_cckrx_enable	= 0x0;	/* default: A*/
-+		p_cck_txrx->r_cckrx_enable_2	= 0x0;	/* option: A*/
-+		chgRx = 1;
-+		break;
-+	case ANTENNA_B:
-+		r_rx_antenna_ofdm			= 0x2;	/*/ B*/
-+		p_cck_txrx->r_cckrx_enable	= 0x1;	/*/ default: B*/
-+		p_cck_txrx->r_cckrx_enable_2	= 0x1;	/*/ option: B*/
-+		chgRx = 1;
-+		break;
-+	case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/
-+		r_rx_antenna_ofdm		= 0x3;/*/ AB*/
-+		p_cck_txrx->r_cckrx_enable	= 0x0;/*/ default:A*/
-+		p_cck_txrx->r_cckrx_enable_2	= 0x1;/*/ option:B*/
-+		chgRx = 1;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+
-+	if (chgTx && chgRx) {
-+		switch (pHalData->rf_chip) {
-+		case RF_8225:
-+		case RF_8256:
-+		case RF_6052:
-+			/*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
-+			phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val);		/*/OFDM Tx*/
-+			phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val);		/*/OFDM Tx*/
-+			phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);	/*/OFDM Rx*/
-+			phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);	/*/OFDM Rx*/
-+			if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
-+				phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm);	/*/OFDM Rx*/
-+				phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm);	/*/OFDM Rx*/
-+			}
-+			phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
-+			break;
-+
-+		default:
-+			RTW_INFO("Unsupported RFChipID for switching antenna.\n");
-+			break;
-+		}
-+	}
-+}	/* MPT_ProSetRFPath */
-+
-+#ifdef CONFIG_RTL8192F
-+
-+void mpt_set_rfpath_8192f(PADAPTER	pAdapter)
-+{
-+	HAL_DATA_TYPE			*pHalData	= GET_HAL_DATA(pAdapter);
-+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+
-+	u16		ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
-+	u8				NssforRate, odmNssforRate;
-+	u32				ulAntennaTx, ulAntennaRx;
-+	enum bb_path	RxAntToPhyDm;
-+	enum bb_path	TxAntToPhyDm;
-+
-+	ulAntennaTx = pHalData->antenna_tx_path;
-+	ulAntennaRx = pHalData->AntennaRxPath;
-+	NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
-+
-+	if (pHalData->rf_chip >= RF_TYPE_MAX)
-+		RTW_INFO("This RF chip ID is not supported\n");
-+
-+	switch (ulAntennaTx) {
-+	case ANTENNA_A:
-+			pMptCtx->mpt_rf_path = RF_PATH_A;
-+			TxAntToPhyDm = BB_PATH_A;
-+			break;
-+	case ANTENNA_B:
-+			pMptCtx->mpt_rf_path = RF_PATH_B;
-+			TxAntToPhyDm = BB_PATH_B;
-+			break;
-+	case ANTENNA_AB:
-+			pMptCtx->mpt_rf_path = RF_PATH_AB;
-+			TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
-+			break;
-+	default:
-+			pMptCtx->mpt_rf_path = RF_PATH_AB;
-+			TxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
-+			break;
-+	}
-+
-+	switch (ulAntennaRx) {
-+	case ANTENNA_A:
-+			RxAntToPhyDm = BB_PATH_A;
-+			break;
-+	case ANTENNA_B:
-+			RxAntToPhyDm = BB_PATH_B;
-+			break;
-+	case ANTENNA_AB:
-+			RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
-+			break;
-+	default:
-+			RxAntToPhyDm = (BB_PATH_A|BB_PATH_B);
-+			break;
-+	}
-+
-+	phydm_api_trx_mode(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, TxAntToPhyDm);
-+
-+}
-+
-+#endif
-+
-+void hal_mpt_SetAntenna(PADAPTER	pAdapter)
-+{
-+	PHAL_DATA_TYPE hal;
-+	ANTENNA_PATH anttx;
-+	enum bb_path bb_tx = 0;
-+
-+
-+	hal = GET_HAL_DATA(pAdapter);
-+	anttx = hal->antenna_tx_path;
-+
-+	switch (anttx) {
-+	case ANTENNA_A:
-+		bb_tx = BB_PATH_A;
-+		break;
-+	case ANTENNA_B:
-+		bb_tx = BB_PATH_B;
-+		break;
-+	case ANTENNA_C:
-+		bb_tx = BB_PATH_C;
-+		break;
-+	case ANTENNA_D:
-+		bb_tx = BB_PATH_D;
-+		break;
-+	case ANTENNA_AB:
-+		bb_tx = BB_PATH_AB;
-+		break;
-+	case ANTENNA_AC:
-+		bb_tx = BB_PATH_AC;
-+		break;
-+	case ANTENNA_AD:
-+		bb_tx = BB_PATH_AD;
-+		break;
-+	case ANTENNA_BC:
-+		bb_tx = BB_PATH_BC;
-+		break;
-+	case ANTENNA_BD:
-+		bb_tx = BB_PATH_BD;
-+		break;
-+	case ANTENNA_CD:
-+		bb_tx = BB_PATH_CD;
-+		break;
-+	case ANTENNA_ABC:
-+		bb_tx = BB_PATH_ABC;
-+		break;
-+	case ANTENNA_BCD:
-+		bb_tx = BB_PATH_BCD;
-+		break;
-+	case ANTENNA_ABD:
-+		bb_tx = BB_PATH_ABD;
-+		break;
-+	case ANTENNA_ACD:
-+		bb_tx = BB_PATH_ACD;
-+		break;
-+	case ANTENNA_ABCD:
-+		bb_tx = BB_PATH_ABCD;
-+		break;
-+	default:
-+		bb_tx = BB_PATH_A;
-+		break;
-+	}
-+	tx_path_nss_set_full_tx(hal->txpath_nss, hal->txpath_num_nss, bb_tx);
-+	RTW_INFO("%s ,ant idx %d, tx path_num_nss = %d\n", __func__, anttx, hal->txpath_num_nss[0]);
-+
-+#ifdef CONFIG_RTL8822C
-+	if (IS_HARDWARE_TYPE_8822C(pAdapter)) {
-+		rtl8822c_mp_config_rfpath(pAdapter);
-+		return;
-+	}
-+#endif
-+#ifdef CONFIG_RTL8814A
-+	if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
-+		mpt_SetRFPath_8814A(pAdapter);
-+		return;
-+	}
-+#endif
-+#ifdef CONFIG_RTL8822B
-+	if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
-+		rtl8822b_mp_config_rfpath(pAdapter);
-+		return;
-+	}
-+#endif
-+#ifdef CONFIG_RTL8821C
-+	if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
-+		rtl8821c_mp_config_rfpath(pAdapter);
-+		return;
-+	}
-+#endif
-+#if	defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+	if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
-+		mpt_SetRFPath_8812A(pAdapter);
-+		return;
-+	}
-+#endif
-+#ifdef CONFIG_RTL8723B
-+	if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
-+		mpt_SetRFPath_8723B(pAdapter);
-+		return;
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
-+		mpt_SetRFPath_8703B(pAdapter);
-+		return;
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
-+		mpt_SetRFPath_8723D(pAdapter);
-+		return;
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTL8192F
-+		if (IS_HARDWARE_TYPE_8192F(pAdapter)) {
-+			mpt_set_rfpath_8192f(pAdapter);
-+			return;
-+		}
-+#endif
-+
-+#ifdef CONFIG_RTL8814B
-+	if (IS_HARDWARE_TYPE_8814B(pAdapter)) {
-+		rtl8814b_mp_config_rfpath(pAdapter);
-+		return;
-+	}
-+#endif
-+
-+	/*	else if (IS_HARDWARE_TYPE_8821B(pAdapter))
-+			mpt_SetRFPath_8821B(pAdapter);
-+		Prepare for 8822B
-+		else if (IS_HARDWARE_TYPE_8822B(Context))
-+			mpt_SetRFPath_8822B(Context);
-+	*/
-+	mpt_SetRFPath_819X(pAdapter);
-+	RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__);
-+}
-+
-+s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
-+
-+	if (!netif_running(pAdapter->pnetdev)) {
-+		return _FAIL;
-+	}
-+
-+
-+	if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
-+		return _FAIL;
-+	}
-+
-+	target_ther &= 0xff;
-+
-+	pHalData->eeprom_thermal_meter = target_ther;
-+
-+	return _SUCCESS;
-+}
-+
-+
-+void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
-+{
-+	if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x0);
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT19, 0x1);
-+	} else
-+		phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
-+
-+}
-+
-+
-+u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path)
-+
-+{
-+	struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter);
-+
-+	u32 ThermalValue = 0;
-+	s32 thermal_value_temp = 0;
-+	s8 thermal_offset = 0;
-+	u32 thermal_reg_mask = 0;
-+
-+	if (IS_8822C_SERIES(GET_HAL_DATA(pAdapter)->version_id))
-+			thermal_reg_mask = 0x007e; 	/*0x42: RF Reg[6:1], 35332(themal K  & bias k & power trim) & 35325(tssi )*/
-+	else
-+			thermal_reg_mask = 0xfc00;	/*0x42: RF Reg[15:10]*/
-+
-+	ThermalValue = (u8)phy_query_rf_reg(pAdapter, rf_path, 0x42, thermal_reg_mask);
-+
-+	thermal_offset = phydm_get_thermal_offset(p_dm_odm);
-+
-+	thermal_value_temp = ThermalValue + thermal_offset;
-+
-+	if (thermal_value_temp > 63)
-+		ThermalValue = 63;
-+	else if (thermal_value_temp < 0)
-+		ThermalValue = 0;
-+	else
-+		ThermalValue = thermal_value_temp;
-+
-+	return (u8)ThermalValue;
-+}
-+
-+
-+void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value)
-+{
-+#if 0
-+	fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
-+	rtw_msleep_os(1000);
-+	fw_cmd_data(pAdapter, value, 1);
-+	*value &= 0xFF;
-+#else
-+	hal_mpt_TriggerRFThermalMeter(pAdapter);
-+	rtw_msleep_os(1000);
-+	*value = hal_mpt_ReadRFThermalMeter(pAdapter, rfpath);
-+#endif
-+
-+}
-+
-+
-+void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
-+
-+	pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;
-+
-+	if (bStart) {/*/ Start Single Carrier.*/
-+		/*/ Start Single Carrier.*/
-+		/*/ 1. if OFDM block on?*/
-+		if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
-+			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
-+
-+		/*/ 2. set CCK test mode off, set to CCK normal mode*/
-+		phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
-+
-+		/*/ 3. turn on scramble setting*/
-+		phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
-+
-+		/*/ 4. Turn On Continue Tx and turn off the other test modes.*/
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
-+		if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
-+			phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
-+		else
-+#endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
-+			phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
-+
-+	} else {
-+		/*/ Stop Single Carrier.*/
-+		/*/ Stop Single Carrier.*/
-+		/*/ Turn off all test modes.*/
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
-+		if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
-+			phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
-+		else
-+#endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
-+			phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
-+
-+		rtw_msleep_os(10);
-+		/*/BB Reset*/
-+		phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
-+		phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
-+	}
-+}
-+
-+
-+void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	PMPT_CONTEXT		pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
-+	u32			ulAntennaTx = pHalData->antenna_tx_path;
-+	static u32		regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
-+	u8 rfPath;
-+
-+	if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
-+#ifdef	PHYDM_MP_SUPPORT
-+#ifdef CONFIG_RTL8814B
-+		if(pHalData->current_channel_bw == CHANNEL_WIDTH_80_80)
-+		{
-+			/* @Tx mode: RF0x00[19:16]=4'b0010 */
-+			config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0xF0000, 0x2);
-+			/* @Lowest RF gain index: RF_0x0[4:0] = 0*/
-+			config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x0, 0x1F, 0x0);
-+			/* @RF LO enabled */
-+			config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN0, RF_0x58, BIT(1), 0x1);
-+			/* @SYN1 */
-+			config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0xF0000, 0x2);
-+			config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x0, 0x1F, 0x0);
-+			config_phydm_write_rf_syn_8814b(pDM_Odm, RF_SYN1, RF_0x58, BIT(1), 0x1);
-+		}
-+#endif
-+		phydm_mp_set_single_tone(pDM_Odm, bStart, pMptCtx->mpt_rf_path);
-+#endif
-+		return;
-+	}
-+
-+	switch (ulAntennaTx) {
-+	case ANTENNA_B:
-+		rfPath = RF_PATH_B;
-+		break;
-+	case ANTENNA_C:
-+		rfPath = RF_PATH_C;
-+		break;
-+	case ANTENNA_D:
-+		rfPath = RF_PATH_D;
-+		break;
-+	case ANTENNA_A:
-+	default:
-+		rfPath = RF_PATH_A;
-+		break;
-+	}
-+
-+	pAdapter->mppriv.mpt_ctx.is_single_tone = bStart;
-+	if (bStart) {
-+		/*/ Start Single Tone.*/
-+		/*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
-+		if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
-+			regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);
-+			phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
-+			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
-+			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
-+		} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
-+			/*/Set MAC REG 88C: Prevent SingleTone Fail*/
-+			phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
-+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
-+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
-+		}	else if (IS_HARDWARE_TYPE_8192F(pAdapter)) { /* USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
-+ #ifdef CONFIG_RTL8192F
-+			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x1);
-+			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x1);
-+			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x1);
-+			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x1);
-+			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x1);
-+			phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x1);
-+			phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0xF);
-+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x1); /* RF LO disabled*/
-+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /* Tx mode*/
-+#endif
-+		} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
-+			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
-+			} else {
-+				/*/ S0/S1 both use PATH A to configure*/
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
-+			}
-+		} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
-+			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
-+			}
-+		} else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
-+			/*Set BB REG 88C: Prevent SingleTone Fail*/
-+			phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
-+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
-+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
-+
-+		} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
-+			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
-+				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1);
-+			} else {/* S0/S1 both use PATH A to configure */
-+				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1);
-+			}
-+		} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
-+			u8 p = RF_PATH_A;
-+
-+			regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
-+			regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
-+			regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
-+			regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
-+			regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
-+
-+			phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
-+
-+			if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
-+				for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
-+					phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
-+					phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
-+					phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
-+				}
-+			} else {
-+				phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
-+				phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
-+#ifdef CONFIG_RTL8821C
-+				if (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG)
-+					phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */
-+				else
-+#endif
-+					phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
-+			}
-+			if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
-+					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777);  /* 0xCB0=0x77777777*/
-+					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777);  /* 0xEB0=0x77777777*/
-+					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777);  /* 0xCB4[15:0] = 0x7777*/
-+					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777);  /* 0xEB4[15:0] = 0x7777*/
-+					phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/
-+					phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/
-+			} else if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
-+				phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707);  /* 0xCB0[[15:12, 7:4] = 0x707*/
-+
-+				if (pHalData->external_pa_5g)
-+				{
-+					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
-+				}
-+				else if (pHalData->ExternalPA_2G)
-+				{
-+					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
-+				}
-+			} else {
-+				phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
-+				phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007);  /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
-+
-+				if (pHalData->external_pa_5g) {
-+					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
-+					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
-+				} else if (pHalData->ExternalPA_2G) {
-+					phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
-+					phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
-+				}
-+			}
-+#endif
-+		}
-+#if defined(CONFIG_RTL8814A)
-+				else if (IS_HARDWARE_TYPE_8814A(pAdapter))
-+						mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
-+#endif
-+		else	/*/ Turn On SingleTone and turn off the other test modes.*/
-+			phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
-+
-+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
-+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
-+
-+	} else {/*/ Stop Single Ton e.*/
-+
-+		if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
-+			phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
-+			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
-+			phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
-+		} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
-+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
-+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
-+			/*/ RESTORE MAC REG 88C: Enable RF Functions*/
-+			phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
-+		} else if (IS_HARDWARE_TYPE_8192F(pAdapter)){
-+#ifdef CONFIG_RTL8192F
-+			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x0);
-+			phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x0);
-+			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x0);
-+			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x0);
-+			phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x0);
-+			phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x0);
-+			phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0x0);
-+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x0); /* RF LO disabled*/
-+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /* Rx mode*/
-+#endif
-+		} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
-+			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
-+			} else {
-+				/*/ S0/S1 both use PATH A to configure*/
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
-+			}
-+		} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
-+			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
-+			}
-+		} else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
-+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
-+			phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
-+			/*Set BB REG 88C: Prevent SingleTone Fail*/
-+			phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
-+		} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
-+			if (pMptCtx->mpt_rf_path == RF_PATH_A) {
-+				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0);
-+			} else {	/* S0/S1 both use PATH A to configure */
-+				phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
-+				phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0);
-+			}
-+		} else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
-+			u8 p = RF_PATH_A;
-+
-+			phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
-+
-+			if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
-+				for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
-+					phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
-+					phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
-+				}
-+			} else {
-+				p = pMptCtx->mpt_rf_path;
-+				phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
-+
-+				if (IS_HARDWARE_TYPE_8821C(pAdapter))
-+					phy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */
-+
-+				phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
-+			}
-+
-+			phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
-+			phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
-+			phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
-+			phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
-+
-+			if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
-+				RTW_INFO("Restore RFE control Pin cbc\n");
-+				phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0);
-+				phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0);
-+			}
-+#endif
-+		}
-+#if defined(CONFIG_RTL8814A)
-+		else if (IS_HARDWARE_TYPE_8814A(pAdapter))
-+			mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
-+
-+		else/*/ Turn off all test modes.*/
-+			phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
-+#endif
-+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
-+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
-+
-+	}
-+}
-+
-+void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	struct dm_struct		*pdm_odm = &pHalData->odmpriv;
-+	u8 Rate;
-+
-+	pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
-+
-+	if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
-+#ifdef PHYDM_MP_SUPPORT
-+		phydm_mp_set_carrier_supp(pdm_odm, bStart, pAdapter->mppriv.rateidx);
-+#endif
-+		return;
-+	}
-+
-+	Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
-+	if (bStart) {/* Start Carrier Suppression.*/
-+		if (Rate <= MPT_RATE_11M) {
-+			/*/ 1. if CCK block on?*/
-+			if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
-+				write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
-+
-+			/*/Turn Off All Test Mode*/
-+			if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
-+				phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
-+			else
-+				phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
-+
-+			write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);    /*/transmit mode*/
-+			write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0);  /*/turn off scramble setting*/
-+
-+			/*/Set CCK Tx Test Rate*/
-+			write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);    /*/Set FTxRate to 1Mbps*/
-+		}
-+
-+		/*Set for dynamic set Power index*/
-+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
-+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
-+
-+	} else {/* Stop Carrier Suppression.*/
-+
-+		if (Rate <= MPT_RATE_11M) {
-+			write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);    /*normal mode*/
-+			write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1);  /*turn on scramble setting*/
-+
-+			/*BB Reset*/
-+			write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
-+			write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
-+		}
-+		/*Stop for dynamic set Power index*/
-+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
-+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
-+	}
-+	RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
-+}
-+
-+u32 hal_mpt_query_phytxok(PADAPTER	pAdapter)
-+{
-+	PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+	RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
-+	HAL_DATA_TYPE			*pHalData	= GET_HAL_DATA(pAdapter);
-+	u16 count = 0;
-+
-+#ifdef PHYDM_MP_SUPPORT
-+	struct dm_struct *dm = (struct dm_struct *)&pHalData->odmpriv;
-+	struct phydm_mp *mp = &dm->dm_mp_table;
-+
-+	if (IS_HARDWARE_TYPE_JAGUAR3(pAdapter)) {
-+		phydm_mp_get_tx_ok(&pHalData->odmpriv, pAdapter->mppriv.rateidx);
-+		count = mp->tx_phy_ok_cnt;
-+
-+	} else
-+#endif
-+	{
-+
-+	if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
-+		count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
-+	else
-+		count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
-+	}
-+
-+	if (count > 50000) {
-+		rtw_reset_phy_trx_ok_counters(pAdapter);
-+		pAdapter->mppriv.tx.sended += count;
-+		count = 0;
-+	}
-+
-+	return pAdapter->mppriv.tx.sended + count;
-+
-+}
-+
-+static	void mpt_StopCckContTx(
-+	PADAPTER	pAdapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
-+	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+	u8			u1bReg;
-+
-+	pMptCtx->bCckContTx = FALSE;
-+	pMptCtx->bOfdmContTx = FALSE;
-+
-+	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);	/*normal mode*/
-+	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1);	/*turn on scramble setting*/
-+
-+	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
-+		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0);			/* 0xa15[1:0] = 2b00*/
-+		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);		/* 0xc08[16] = 0*/
-+
-+		phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
-+		phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
-+		phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
-+	}
-+
-+	/*BB Reset*/
-+	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
-+	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
-+
-+	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
-+	phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
-+	phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
-+	}
-+
-+	if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
-+		IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
-+		IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
-+		IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
-+		phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);/* patch Count CCK adjust Rate*/
-+	}
-+
-+}	/* mpt_StopCckContTx */
-+
-+
-+static	void mpt_StopOfdmContTx(
-+	PADAPTER	pAdapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
-+	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+	u8			u1bReg;
-+	u32			data;
-+
-+	pMptCtx->bCckContTx = FALSE;
-+	pMptCtx->bOfdmContTx = FALSE;
-+
-+	if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
-+		phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
-+	else
-+		phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
-+
-+	rtw_mdelay_os(10);
-+
-+	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)){
-+		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0);			/* 0xa15[1:0] = 0*/
-+		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);		/* 0xc08[16] = 0*/
-+	}
-+
-+	/*BB Reset*/
-+	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
-+	phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
-+
-+	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
-+	phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
-+	phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
-+	}
-+}	/* mpt_StopOfdmContTx */
-+
-+
-+static	void mpt_StartCckContTx(
-+	PADAPTER		pAdapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
-+	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+	u32			cckrate;
-+
-+	/* 1. if CCK block on */
-+	if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
-+		phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
-+
-+	/*Turn Off All Test Mode*/
-+	if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
-+		phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
-+	else
-+		phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
-+
-+	cckrate  = pAdapter->mppriv.rateidx;
-+
-+	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
-+
-+	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);	/*transmit mode*/
-+	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1);	/*turn on scramble setting*/
-+
-+	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
-+		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3);			/* 0xa15[1:0] = 11 force cck rxiq = 0*/
-+		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);		/* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
-+		phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
-+		phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
-+		phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
-+	}
-+
-+	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
-+		phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
-+		phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
-+	}
-+
-+	if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) ||
-+		IS_HARDWARE_TYPE_8703B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter) ||
-+		IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8192F(pAdapter) ||
-+		IS_HARDWARE_TYPE_8821C(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) {
-+		if (pAdapter->mppriv.rateidx == MPT_RATE_1M) /* patch Count CCK adjust Rate*/
-+			phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bDisable);
-+		else
-+			phy_set_bb_reg(pAdapter, 0xA70, BIT(14), bEnable);
-+	}
-+
-+	pMptCtx->bCckContTx = TRUE;
-+	pMptCtx->bOfdmContTx = FALSE;
-+
-+}	/* mpt_StartCckContTx */
-+
-+
-+static	void mpt_StartOfdmContTx(
-+	PADAPTER		pAdapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
-+	PMPT_CONTEXT	pMptCtx = &(pAdapter->mppriv.mpt_ctx);
-+
-+	/* 1. if OFDM block on?*/
-+	if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
-+		phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
-+
-+	/* 2. set CCK test mode off, set to CCK normal mode*/
-+	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
-+
-+	/* 3. turn on scramble setting*/
-+	phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
-+
-+	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
-+		phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3);			/* 0xa15[1:0] = 2b'11*/
-+		phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1);		/* 0xc08[16] = 1*/
-+	}
-+
-+	/* 4. Turn On Continue Tx and turn off the other test modes.*/
-+	if (IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter))
-+		phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
-+	else
-+		phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
-+
-+	if (!IS_HARDWARE_TYPE_JAGUAR_ALL(pAdapter)) {
-+		phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
-+		phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
-+	}
-+
-+	pMptCtx->bCckContTx = FALSE;
-+	pMptCtx->bOfdmContTx = TRUE;
-+}	/* mpt_StartOfdmContTx */
-+
-+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) \
-+	|| defined(CONFIG_RTL8821C)  || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) \
-+	|| defined(CONFIG_RTL8723F)
-+#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
-+static void mpt_convert_phydm_txinfo_for_jaguar3(
-+	RT_PMAC_TX_INFO	*pMacTxInfo, struct phydm_pmac_info *phydmtxinfo)
-+{
-+	phydmtxinfo->en_pmac_tx = pMacTxInfo->bEnPMacTx;
-+	phydmtxinfo->mode = pMacTxInfo->Mode;
-+	phydmtxinfo->tx_rate = MRateToHwRate(mpt_to_mgnt_rate(pMacTxInfo->TX_RATE));
-+	phydmtxinfo->tx_sc = pMacTxInfo->TX_SC;
-+	phydmtxinfo->is_short_preamble = pMacTxInfo->bSPreamble;
-+	phydmtxinfo->ndp_sound = pMacTxInfo->NDP_sound;
-+	phydmtxinfo->bw = pMacTxInfo->BandWidth;
-+	phydmtxinfo->m_stbc = pMacTxInfo->m_STBC;
-+	phydmtxinfo->packet_period = pMacTxInfo->PacketPeriod;
-+	phydmtxinfo->packet_count = pMacTxInfo->PacketCount;
-+	phydmtxinfo->packet_pattern = pMacTxInfo->PacketPattern;
-+	phydmtxinfo->sfd = pMacTxInfo->SFD;
-+	phydmtxinfo->signal_field = pMacTxInfo->SignalField;
-+	phydmtxinfo->service_field = pMacTxInfo->ServiceField;
-+	phydmtxinfo->length = pMacTxInfo->LENGTH;
-+	_rtw_memcpy(&phydmtxinfo->crc16,pMacTxInfo->CRC16, 2);
-+	_rtw_memcpy(&phydmtxinfo->lsig , pMacTxInfo->LSIG,3);
-+	_rtw_memcpy(&phydmtxinfo->ht_sig , pMacTxInfo->HT_SIG,6);
-+	_rtw_memcpy(&phydmtxinfo->vht_sig_a , pMacTxInfo->VHT_SIG_A,6);
-+	_rtw_memcpy(&phydmtxinfo->vht_sig_b , pMacTxInfo->VHT_SIG_B,4);
-+	phydmtxinfo->vht_sig_b_crc = pMacTxInfo->VHT_SIG_B_CRC;
-+	_rtw_memcpy(&phydmtxinfo->vht_delimiter,pMacTxInfo->VHT_Delimiter,4);
-+}
-+#endif
-+
-+/* for HW TX mode */
-+u8 mpt_ProSetPMacTx(PADAPTER	Adapter)
-+{
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
-+	PMPT_CONTEXT	pMptCtx		=	&(Adapter->mppriv.mpt_ctx);
-+	struct mp_priv *pmppriv = &Adapter->mppriv;
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
-+	RT_PMAC_TX_INFO	PMacTxInfo	=	pMptCtx->PMacTxInfo;
-+	struct dm_struct *p_dm_odm;
-+	u32			u4bTmp;
-+	u8 status = _TRUE;
-+
-+	p_dm_odm = &pHalData->odmpriv;
-+
-+#if 0
-+	PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
-+	PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
-+	PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
-+	PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
-+	dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
-+	PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
-+
-+	PRINT_DATA("Src Address", Adapter->mac_addr, ETH_ALEN);
-+	PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, ETH_ALEN);
-+#endif
-+	if (pmppriv->pktInterval != 0)
-+		PMacTxInfo.PacketPeriod = pmppriv->pktInterval;
-+
-+    	if (pmppriv->tx.count != 0)
-+        	PMacTxInfo.PacketCount = pmppriv->tx.count;
-+
-+	RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
-+	RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
-+		 PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
-+
-+	if (hal_spec->tx_nss_num < 2 && MPT_IS_2SS_RATE(PMacTxInfo.TX_RATE))
-+		return _FALSE;
-+	if (hal_spec->tx_nss_num < 3 && MPT_IS_3SS_RATE(PMacTxInfo.TX_RATE))
-+		return _FALSE;
-+	if (hal_spec->tx_nss_num < 4 && MPT_IS_4SS_RATE(PMacTxInfo.TX_RATE))
-+		return _FALSE;
-+	if (!is_supported_vht(Adapter->registrypriv.wireless_mode) && MPT_IS_VHT_RATE(PMacTxInfo.TX_RATE))
-+		return _FALSE;
-+	if (!is_supported_ht(Adapter->registrypriv.wireless_mode) && MPT_IS_HT_RATE(PMacTxInfo.TX_RATE))
-+		return _FALSE;
-+
-+	if (PMacTxInfo.BandWidth == 1 && hal_chk_bw_cap(Adapter, BW_CAP_40M))
-+		PMacTxInfo.BandWidth = CHANNEL_WIDTH_40;
-+	else if (PMacTxInfo.BandWidth == 2 && hal_chk_bw_cap(Adapter, BW_CAP_80M))
-+		PMacTxInfo.BandWidth = CHANNEL_WIDTH_80;
-+	else
-+		PMacTxInfo.BandWidth = CHANNEL_WIDTH_20;
-+
-+	if (IS_HARDWARE_TYPE_JAGUAR3(Adapter)) {
-+#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
-+		struct phydm_pmac_info phydm_mactxinfo;
-+
-+		if (PMacTxInfo.bEnPMacTx == TRUE) {
-+			pMptCtx->HWTxmode = PMacTxInfo.Mode;
-+			pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
-+			if (PMacTxInfo.Mode == CONTINUOUS_TX)
-+				hal_mpt_SetTxPower(Adapter);
-+		} else {
-+			PMacTxInfo.Mode = pMptCtx->HWTxmode;
-+			PMacTxInfo.TX_RATE = pMptCtx->mpt_rate_index;
-+			pMptCtx->HWTxmode = TEST_NONE;
-+		}
-+		mpt_convert_phydm_txinfo_for_jaguar3(&PMacTxInfo, &phydm_mactxinfo);
-+		phydm_set_pmac_tx(p_dm_odm, &phydm_mactxinfo, pMptCtx->mpt_rf_path);
-+#endif
-+		return status;
-+	}
-+
-+	if (PMacTxInfo.bEnPMacTx == FALSE) {
-+		if (pMptCtx->HWTxmode == CONTINUOUS_TX) {
-+			phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);			/*	TX Stop*/
-+			if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
-+				mpt_StopCckContTx(Adapter);
-+			else
-+				mpt_StopOfdmContTx(Adapter);
-+		} else if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) {
-+			u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
-+			phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
-+			phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);		/*TX Stop*/
-+		} else
-+			phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);		/*	TX Stop*/
-+
-+		if (pMptCtx->HWTxmode == OFDM_Single_Tone_TX) {
-+			/* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
-+			if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index))
-+				mpt_StopCckContTx(Adapter);
-+			else
-+				mpt_StopOfdmContTx(Adapter);
-+
-+			mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE);
-+		}
-+		pMptCtx->HWTxmode = TEST_NONE;
-+		return status;
-+	}
-+
-+    	pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE;
-+
-+	if (PMacTxInfo.Mode == CONTINUOUS_TX) {
-+		pMptCtx->HWTxmode = CONTINUOUS_TX;
-+		PMacTxInfo.PacketCount = 1;
-+
-+        	hal_mpt_SetTxPower(Adapter);
-+
-+		if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
-+			mpt_StartCckContTx(Adapter);
-+		else
-+			mpt_StartOfdmContTx(Adapter);
-+	} else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
-+		/* Continuous TX -> HW TX -> RF Setting */
-+		pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
-+		PMacTxInfo.PacketCount = 1;
-+
-+		if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
-+			mpt_StartCckContTx(Adapter);
-+		else
-+			mpt_StartOfdmContTx(Adapter);
-+	} else if (PMacTxInfo.Mode == PACKETS_TX) {
-+		pMptCtx->HWTxmode = PACKETS_TX;
-+		if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
-+			PMacTxInfo.PacketCount = 0xffff;
-+	}
-+
-+	if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
-+		/* 0xb1c[0:15] TX packet count 0xb1C[31:16]	SFD*/
-+		u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
-+		phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
-+		/* 0xb40 7:0 SIGNAL	15:8 SERVICE	31:16 LENGTH*/
-+		u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
-+		phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);
-+		u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
-+		phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);
-+
-+		if (PMacTxInfo.bSPreamble)
-+			phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);
-+		else
-+			phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);
-+	} else {
-+		phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
-+
-+		u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
-+		phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp);	/*	Set 0xb08[23:0] = LSIG, 0xb08[31:24] =  Data init octet*/
-+
-+		if (PMacTxInfo.PacketPattern == 0x12)
-+			u4bTmp = 0x3000000;
-+		else
-+			u4bTmp = 0;
-+	}
-+
-+	if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
-+		u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
-+		phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
-+		u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
-+		phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
-+	} else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
-+		u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
-+		phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
-+		u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
-+		phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
-+
-+		_rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
-+		phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);
-+	}
-+
-+	if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
-+		u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod;	/* for TX interval */
-+		phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);
-+
-+		_rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
-+		phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);
-+
-+		/* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
-+		/*& Duration & Frame control*/
-+		phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);
-+
-+		/* Address1 [0:3]*/
-+		u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
-+		phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
-+
-+		/* Address3 [3:0]*/
-+		phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
-+
-+		/* Address2[0:1] & Address1 [5:4]*/
-+		u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
-+		phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
-+
-+		/* Address2 [5:2]*/
-+		u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
-+		phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
-+
-+		/* Sequence Control & Address3 [5:4]*/
-+		/*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
-+		/*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
-+	} else {
-+		phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod);	/* for TX interval*/
-+		/* & Duration & Frame control */
-+		phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);
-+
-+		/* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
-+		/* Address1 [0:3]*/
-+		u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
-+		phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);
-+
-+		/* Address3 [3:0]*/
-+		phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
-+
-+		/* Address2[0:1] & Address1 [5:4]*/
-+		u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
-+		phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
-+
-+		/* Address2 [5:2] */
-+		u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
-+		phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
-+
-+		/* Sequence Control & Address3 [5:4]*/
-+		u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
-+		phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
-+	}
-+
-+	phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
-+
-+	/* 0xb4c 3:0 TXSC	5:4	BW	7:6 m_STBC	8 NDP_Sound*/
-+	u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
-+	phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
-+
-+	if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) {
-+		u32 offset = 0xb44;
-+
-+		if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
-+			phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
-+		else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
-+			phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
-+		else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
-+			phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
-+
-+	} else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) {
-+		u32 offset = 0xb4c;
-+
-+		if(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
-+			phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
-+		else if(IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
-+			phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
-+		else if(IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
-+			phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
-+	}
-+
-+	phy_set_bb_reg(Adapter, 0xb00, BIT8, 1);		/*	Turn on PMAC*/
-+	/* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2);				 */ /* TX Stop */
-+	if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
-+		phy_set_bb_reg(Adapter, 0xb04, 0xf, 8);		/*TX CCK ON*/
-+		phy_set_bb_reg(Adapter, 0xA84, BIT31, 0);
-+	} else
-+		phy_set_bb_reg(Adapter, 0xb04, 0xf, 4);		/*	TX Ofdm ON	*/
-+
-+	if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
-+		mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
-+
-+	return status;
-+}
-+
-+#endif
-+
-+void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
-+{
-+	u8 Rate;
-+
-+	RTW_INFO("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx);
-+	Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
-+	pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;
-+
-+	if (Rate <= MPT_RATE_11M) {
-+		if (bStart)
-+			mpt_StartCckContTx(pAdapter);
-+		else
-+			mpt_StopCckContTx(pAdapter);
-+
-+	} else if (Rate >= MPT_RATE_6M) {
-+		if (bStart)
-+			mpt_StartOfdmContTx(pAdapter);
-+		else
-+			mpt_StopOfdmContTx(pAdapter);
-+	}
-+}
-+
-+void mpt_trigger_tssi_tracking(PADAPTER pAdapter, u8 rf_path)
-+{
-+#ifdef CONFIG_RTL8814B
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
-+
-+	halrf_do_tssi_8814b(pDM_Odm, rf_path);
-+#endif
-+}
-+
-+#endif /* CONFIG_MP_INCLUDE*/
-diff --git a/drivers/staging/rtl8723cs/hal/hal_phy.c b/drivers/staging/rtl8723cs/hal/hal_phy.c
-new file mode 100644
-index 000000000000..cf5cb3b5470f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/hal_phy.c
-@@ -0,0 +1,257 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _HAL_PHY_C_
-+
-+#include <drv_types.h>
-+
-+/**
-+* Function:	PHY_CalculateBitShift
-+*
-+* OverView:	Get shifted position of the BitMask
-+*
-+* Input:
-+*			u32		BitMask,
-+*
-+* Output:	none
-+* Return:		u32		Return the shift bit bit position of the mask
-+*/
-+u32
-+PHY_CalculateBitShift(
-+	u32 BitMask
-+)
-+{
-+	u32 i;
-+
-+	for (i = 0; i <= 31; i++) {
-+		if (((BitMask >> i) &  0x1) == 1)
-+			break;
-+	}
-+
-+	return i;
-+}
-+
-+
-+#ifdef CONFIG_RF_SHADOW_RW
-+/* ********************************************************************************
-+ *	Constant.
-+ * ********************************************************************************
-+ * 2008/11/20 MH For Debug only, RF */
-+static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
-+
-+/*
-+ * ==> RF shadow Operation API Code Section!!!
-+ *
-+ *-----------------------------------------------------------------------------
-+ * Function:	PHY_RFShadowRead
-+ *				PHY_RFShadowWrite
-+ *				PHY_RFShadowCompare
-+ *				PHY_RFShadowRecorver
-+ *				PHY_RFShadowCompareAll
-+ *				PHY_RFShadowRecorverAll
-+ *				PHY_RFShadowCompareFlagSet
-+ *				PHY_RFShadowRecorverFlagSet
-+ *
-+ * Overview:	When we set RF register, we must write shadow at first.
-+ *			When we are running, we must compare shadow abd locate error addr.
-+ *			Decide to recorver or not.
-+ *
-+ * Input:       NONE
-+ *
-+ * Output:      NONE
-+ *
-+ * Return:      NONE
-+ *
-+ * Revised History:
-+ * When			Who		Remark
-+ * 11/20/2008	MHC		Create Version 0.
-+ *
-+ *---------------------------------------------------------------------------*/
-+u32
-+PHY_RFShadowRead(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				Offset)
-+{
-+	return	RF_Shadow[eRFPath][Offset].Value;
-+
-+}	/* PHY_RFShadowRead */
-+
-+
-+void
-+PHY_RFShadowWrite(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				Offset,
-+		u32				Data)
-+{
-+	RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);
-+	RF_Shadow[eRFPath][Offset].Driver_Write = _TRUE;
-+
-+}	/* PHY_RFShadowWrite */
-+
-+
-+BOOLEAN
-+PHY_RFShadowCompare(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				Offset)
-+{
-+	u32	reg;
-+	/* Check if we need to check the register */
-+	if (RF_Shadow[eRFPath][Offset].Compare == _TRUE) {
-+		reg = rtw_hal_read_rfreg(Adapter, eRFPath, Offset, bRFRegOffsetMask);
-+		/* Compare shadow and real rf register for 20bits!! */
-+		if (RF_Shadow[eRFPath][Offset].Value != reg) {
-+			/* Locate error position. */
-+			RF_Shadow[eRFPath][Offset].ErrorOrNot = _TRUE;
-+		}
-+		return RF_Shadow[eRFPath][Offset].ErrorOrNot ;
-+	}
-+	return _FALSE;
-+}	/* PHY_RFShadowCompare */
-+
-+
-+void
-+PHY_RFShadowRecorver(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				Offset)
-+{
-+	/* Check if the address is error */
-+	if (RF_Shadow[eRFPath][Offset].ErrorOrNot == _TRUE) {
-+		/* Check if we need to recorver the register. */
-+		if (RF_Shadow[eRFPath][Offset].Recorver == _TRUE) {
-+			rtw_hal_write_rfreg(Adapter, eRFPath, Offset, bRFRegOffsetMask,
-+					    RF_Shadow[eRFPath][Offset].Value);
-+		}
-+	}
-+
-+}	/* PHY_RFShadowRecorver */
-+
-+
-+void
-+PHY_RFShadowCompareAll(
-+		PADAPTER			Adapter)
-+{
-+	enum rf_path	eRFPath = RF_PATH_A;
-+	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
-+
-+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
-+		for (Offset = 0; Offset < maxReg; Offset++)
-+			PHY_RFShadowCompare(Adapter, eRFPath, Offset);
-+	}
-+
-+}	/* PHY_RFShadowCompareAll */
-+
-+
-+void
-+PHY_RFShadowRecorverAll(
-+		PADAPTER			Adapter)
-+{
-+	enum rf_path		eRFPath = RF_PATH_A;
-+	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
-+
-+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
-+		for (Offset = 0; Offset < maxReg; Offset++)
-+			PHY_RFShadowRecorver(Adapter, eRFPath, Offset);
-+	}
-+
-+}	/* PHY_RFShadowRecorverAll */
-+
-+
-+void
-+PHY_RFShadowCompareFlagSet(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				Offset,
-+		u8				Type)
-+{
-+	/* Set True or False!!! */
-+	RF_Shadow[eRFPath][Offset].Compare = Type;
-+
-+}	/* PHY_RFShadowCompareFlagSet */
-+
-+
-+void
-+PHY_RFShadowRecorverFlagSet(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				Offset,
-+		u8				Type)
-+{
-+	/* Set True or False!!! */
-+	RF_Shadow[eRFPath][Offset].Recorver = Type;
-+
-+}	/* PHY_RFShadowRecorverFlagSet */
-+
-+
-+void
-+PHY_RFShadowCompareFlagSetAll(
-+		PADAPTER			Adapter)
-+{
-+	enum rf_path	eRFPath = RF_PATH_A;
-+	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
-+
-+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
-+		for (Offset = 0; Offset < maxReg; Offset++) {
-+			/* 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! */
-+			if (Offset != 0x26 && Offset != 0x27)
-+				PHY_RFShadowCompareFlagSet(Adapter, eRFPath, Offset, _FALSE);
-+			else
-+				PHY_RFShadowCompareFlagSet(Adapter, eRFPath, Offset, _TRUE);
-+		}
-+	}
-+
-+}	/* PHY_RFShadowCompareFlagSetAll */
-+
-+
-+void
-+PHY_RFShadowRecorverFlagSetAll(
-+		PADAPTER			Adapter)
-+{
-+	enum rf_path		eRFPath = RF_PATH_A;
-+	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
-+
-+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
-+		for (Offset = 0; Offset < maxReg; Offset++) {
-+			/* 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! */
-+			if (Offset != 0x26 && Offset != 0x27)
-+				PHY_RFShadowRecorverFlagSet(Adapter, eRFPath, Offset, _FALSE);
-+			else
-+				PHY_RFShadowRecorverFlagSet(Adapter, eRFPath, Offset, _TRUE);
-+		}
-+	}
-+
-+}	/* PHY_RFShadowCompareFlagSetAll */
-+
-+void
-+PHY_RFShadowRefresh(
-+		PADAPTER			Adapter)
-+{
-+	enum rf_path		eRFPath = RF_PATH_A;
-+	u32		Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
-+
-+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
-+		for (Offset = 0; Offset < maxReg; Offset++) {
-+			RF_Shadow[eRFPath][Offset].Value = 0;
-+			RF_Shadow[eRFPath][Offset].Compare = _FALSE;
-+			RF_Shadow[eRFPath][Offset].Recorver  = _FALSE;
-+			RF_Shadow[eRFPath][Offset].ErrorOrNot = _FALSE;
-+			RF_Shadow[eRFPath][Offset].Driver_Write = _FALSE;
-+		}
-+	}
-+
-+}	/* PHY_RFShadowRead */
-+#endif /*CONFIG_RF_SHADOW_RW*/
-diff --git a/drivers/staging/rtl8723cs/hal/led/hal_led.c b/drivers/staging/rtl8723cs/hal/led/hal_led.c
-new file mode 100644
-index 000000000000..95d3daa24315
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/led/hal_led.c
-@@ -0,0 +1,254 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#ifdef CONFIG_RTW_LED
-+void dump_led_config(void *sel, _adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct led_priv	*ledpriv = adapter_to_led(adapter);
-+	int i;
-+
-+	RTW_PRINT_SEL(sel, "strategy:%u\n", ledpriv->LedStrategy);
-+#ifdef CONFIG_RTW_SW_LED
-+	RTW_PRINT_SEL(sel, "bRegUseLed:%u\n", ledpriv->bRegUseLed);
-+	RTW_PRINT_SEL(sel, "iface_en_mask:0x%02X\n", ledpriv->iface_en_mask);
-+	for (i = 0; i < dvobj->iface_nums; i++)
-+		RTW_PRINT_SEL(sel, "ctl_en_mask[%d]:0x%08X\n", i, ledpriv->ctl_en_mask[i]);
-+#endif
-+}
-+
-+void rtw_led_set_strategy(_adapter *adapter, u8 strategy)
-+{
-+	struct led_priv *ledpriv = adapter_to_led(adapter);
-+	_adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter);
-+
-+#ifndef CONFIG_RTW_SW_LED
-+	if (IS_SW_LED_STRATEGY(strategy)) {
-+		RTW_WARN("CONFIG_RTW_SW_LED is not defined\n");
-+		return;
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTW_SW_LED
-+	if (!ledpriv->bRegUseLed)
-+		return;
-+#endif
-+
-+	if (ledpriv->LedStrategy == strategy)
-+		return;
-+
-+	if (IS_HW_LED_STRATEGY(strategy) || IS_HW_LED_STRATEGY(ledpriv->LedStrategy)) {
-+		RTW_WARN("switching on/off HW_LED strategy is not supported\n");
-+		return;
-+	}
-+
-+	ledpriv->LedStrategy = strategy;
-+
-+#ifdef CONFIG_RTW_SW_LED
-+	rtw_hal_sw_led_deinit(pri_adapter);
-+#endif
-+
-+	rtw_led_control(pri_adapter, RTW_LED_OFF);
-+}
-+
-+#ifdef CONFIG_RTW_SW_LED
-+#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
-+void rtw_sw_led_blink_uc_trx_only(LED_DATA *led)
-+{
-+	_adapter *adapter = led->padapter;
-+	BOOLEAN bStopBlinking = _FALSE;
-+
-+	if (led->BlinkingLedState == RTW_LED_ON)
-+		SwLedOn(adapter, led);
-+	else
-+		SwLedOff(adapter, led);
-+
-+	switch (led->CurrLedState) {
-+	case RTW_LED_ON:
-+		SwLedOn(adapter, led);
-+		break;
-+
-+	case RTW_LED_OFF:
-+		SwLedOff(adapter, led);
-+		break;
-+
-+	case LED_BLINK_TXRX:
-+		led->BlinkTimes--;
-+		if (led->BlinkTimes == 0)
-+			bStopBlinking = _TRUE;
-+
-+		if (adapter_to_pwrctl(adapter)->rf_pwrstate != rf_on
-+			&& adapter_to_pwrctl(adapter)->rfoff_reason > RF_CHANGE_BY_PS
-+		) {
-+			SwLedOff(adapter, led);
-+			led->bLedBlinkInProgress = _FALSE;
-+		} else {
-+			if (led->bLedOn)
-+				led->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				led->BlinkingLedState = RTW_LED_ON;
-+			
-+			if (bStopBlinking) {
-+				led->CurrLedState = RTW_LED_OFF;
-+				led->bLedBlinkInProgress = _FALSE;
-+			}
-+			_set_timer(&(led->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl)
-+{
-+	struct led_priv	*ledpriv = adapter_to_led(adapter);
-+	LED_DATA *led = &(ledpriv->SwLed0);
-+	LED_DATA *led1 = &(ledpriv->SwLed1);
-+	LED_DATA *led2 = &(ledpriv->SwLed2);
-+
-+	switch (ctl) {
-+	case LED_CTL_UC_TX:
-+	case LED_CTL_UC_RX:
-+		if (led->bLedBlinkInProgress == _FALSE) {
-+			led->bLedBlinkInProgress = _TRUE;
-+			led->CurrLedState = LED_BLINK_TXRX;
-+			led->BlinkTimes = 2;
-+			if (led->bLedOn)
-+				led->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				led->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(led->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	case LED_CTL_POWER_OFF:
-+		led->CurrLedState = RTW_LED_OFF;
-+		led->BlinkingLedState = RTW_LED_OFF;
-+
-+		if (led->bLedBlinkInProgress) {
-+			_cancel_timer_ex(&(led->BlinkTimer));
-+			led->bLedBlinkInProgress = _FALSE;
-+		}
-+
-+		SwLedOff(adapter, led);
-+		SwLedOff(adapter, led1);
-+		SwLedOff(adapter, led2);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+#endif /* CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY */
-+
-+void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl)
-+{
-+	struct led_priv	*ledpriv = adapter_to_led(adapter);
-+
-+	if (ledpriv->LedControlHandler) {
-+		#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
-+		if (ledpriv->LedStrategy != SW_LED_MODE_UC_TRX_ONLY) {
-+			if (ctl == LED_CTL_UC_TX || ctl == LED_CTL_BMC_TX) {
-+				if (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(LED_CTL_TX))
-+					ctl = LED_CTL_TX; /* transform specific TX ctl to general TX ctl */
-+			} else if (ctl == LED_CTL_UC_RX || ctl == LED_CTL_BMC_RX) {
-+				if (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(LED_CTL_RX))
-+					ctl = LED_CTL_RX; /* transform specific RX ctl to general RX ctl */
-+			}
-+		}
-+		#endif
-+
-+		if ((ledpriv->iface_en_mask & BIT(adapter->iface_id))
-+			&& (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(ctl)))
-+			ledpriv->LedControlHandler(adapter, ctl);
-+	}
-+}
-+
-+void rtw_led_tx_control(_adapter *adapter, const u8 *da)
-+{
-+#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
-+	if (IS_MCAST(da))
-+		rtw_led_control(adapter, LED_CTL_BMC_TX);
-+	else
-+		rtw_led_control(adapter, LED_CTL_UC_TX);
-+#else
-+	rtw_led_control(adapter, LED_CTL_TX);
-+#endif
-+}
-+
-+void rtw_led_rx_control(_adapter *adapter, const u8 *da)
-+{
-+#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
-+	if (IS_MCAST(da))
-+		rtw_led_control(adapter, LED_CTL_BMC_RX);
-+	else
-+		rtw_led_control(adapter, LED_CTL_UC_RX);
-+#else
-+	rtw_led_control(adapter, LED_CTL_RX);
-+#endif
-+}
-+
-+void rtw_led_set_iface_en(_adapter *adapter, u8 en)
-+{
-+	struct led_priv *ledpriv = adapter_to_led(adapter);
-+
-+	if (en)
-+		ledpriv->iface_en_mask |= BIT(adapter->iface_id);
-+	else
-+		ledpriv->iface_en_mask &= ~BIT(adapter->iface_id);
-+}
-+
-+void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask)
-+{
-+	struct led_priv *ledpriv = adapter_to_led(adapter);
-+
-+	ledpriv->iface_en_mask = mask;
-+}
-+
-+void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask)
-+{
-+	struct led_priv *ledpriv = adapter_to_led(adapter);
-+	
-+#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
-+	if (ctl_mask & BIT(LED_CTL_TX))
-+		ctl_mask |= BIT(LED_CTL_UC_TX) | BIT(LED_CTL_BMC_TX);
-+	if (ctl_mask & BIT(LED_CTL_RX))
-+		ctl_mask |= BIT(LED_CTL_UC_RX) | BIT(LED_CTL_BMC_RX);
-+#endif
-+
-+	ledpriv->ctl_en_mask[adapter->iface_id] = ctl_mask;
-+}
-+
-+void rtw_led_set_ctl_en_mask_primary(_adapter *adapter)
-+{
-+	rtw_led_set_ctl_en_mask(adapter, 0xFFFFFFFF);
-+}
-+
-+void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter)
-+{
-+	rtw_led_set_ctl_en_mask(adapter
-+		, BIT(LED_CTL_POWER_ON) | BIT(LED_CTL_POWER_OFF)
-+		| BIT(LED_CTL_TX) | BIT(LED_CTL_RX)
-+	);
-+}
-+#endif /* CONFIG_RTW_SW_LED */
-+
-+#endif /* CONFIG_RTW_LED */
-+
-diff --git a/drivers/staging/rtl8723cs/hal/led/hal_sdio_led.c b/drivers/staging/rtl8723cs/hal/led/hal_sdio_led.c
-new file mode 100644
-index 000000000000..506d17d7b3b6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/led/hal_sdio_led.c
-@@ -0,0 +1,2014 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+#ifdef CONFIG_RTW_SW_LED
-+
-+/*
-+ *	Description:
-+ *		Implementation of LED blinking behavior.
-+ *		It toggle off LED and schedule corresponding timer if necessary.
-+ *   */
-+void
-+SwLedBlink(
-+	PLED_SDIO			pLed
-+)
-+{
-+	_adapter			*padapter = pLed->padapter;
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	u8				bStopBlinking = _FALSE;
-+
-+	/* Change LED according to BlinkingLedState specified. */
-+	if (pLed->BlinkingLedState == RTW_LED_ON) {
-+		SwLedOn(padapter, pLed);
-+	} else {
-+		SwLedOff(padapter, pLed);
-+	}
-+
-+	/* Determine if we shall change LED state again. */
-+	pLed->BlinkTimes--;
-+	switch (pLed->CurrLedState) {
-+
-+	case LED_BLINK_NORMAL:
-+		if (pLed->BlinkTimes == 0)
-+			bStopBlinking = _TRUE;
-+		break;
-+
-+	case LED_BLINK_StartToBlink:
-+		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) && check_fwstate(pmlmepriv, WIFI_STATION_STATE))
-+			bStopBlinking = _TRUE;
-+		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) &&
-+		    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)))
-+			bStopBlinking = _TRUE;
-+		else if (pLed->BlinkTimes == 0)
-+			bStopBlinking = _TRUE;
-+		break;
-+
-+	case LED_BLINK_WPS:
-+		if (pLed->BlinkTimes == 0)
-+			bStopBlinking = _TRUE;
-+		break;
-+
-+
-+	default:
-+		bStopBlinking = _TRUE;
-+		break;
-+
-+	}
-+
-+	if (bStopBlinking) {
-+		if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+			SwLedOff(padapter, pLed);
-+		else if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) && (pLed->bLedOn == _FALSE))
-+			SwLedOn(padapter, pLed);
-+		else if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) &&  pLed->bLedOn == _TRUE)
-+			SwLedOff(padapter, pLed);
-+
-+		pLed->BlinkTimes = 0;
-+		pLed->bLedBlinkInProgress = _FALSE;
-+	} else {
-+		/* Assign LED state to toggle. */
-+		if (pLed->BlinkingLedState == RTW_LED_ON)
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+		else
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+
-+		/* Schedule a timer to toggle LED state. */
-+		switch (pLed->CurrLedState) {
-+		case LED_BLINK_NORMAL:
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
-+			break;
-+
-+		case LED_BLINK_SLOWLY:
-+		case LED_BLINK_StartToBlink:
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
-+			break;
-+
-+		case LED_BLINK_WPS:
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL);
-+		        break;
-+
-+		default:
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
-+			break;
-+		}
-+	}
-+}
-+
-+void
-+SwLedBlink1(
-+	PLED_SDIO			pLed
-+)
-+{
-+	_adapter				*padapter = pLed->padapter;
-+	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(padapter);
-+	struct led_priv		*ledpriv = adapter_to_led(padapter);
-+	struct mlme_priv		*pmlmepriv = &(padapter->mlmepriv);
-+	PLED_SDIO			pLed1 = &(ledpriv->SwLed1);
-+	u8					bStopBlinking = _FALSE;
-+
-+	if (pHalData->CustomerID == RT_CID_819x_CAMEO)
-+		pLed = &(ledpriv->SwLed1);
-+
-+	/* Change LED according to BlinkingLedState specified. */
-+	if (pLed->BlinkingLedState == RTW_LED_ON) {
-+		SwLedOn(padapter, pLed);
-+	} else {
-+		SwLedOff(padapter, pLed);
-+	}
-+
-+
-+	if (pHalData->CustomerID == RT_CID_DEFAULT) {
-+		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+			if (!pLed1->bSWLedCtrl) {
-+				SwLedOn(padapter, pLed1);
-+				pLed1->bSWLedCtrl = _TRUE;
-+			} else if (!pLed1->bLedOn)
-+				SwLedOn(padapter, pLed1);
-+		} else {
-+			if (!pLed1->bSWLedCtrl) {
-+				SwLedOff(padapter, pLed1);
-+				pLed1->bSWLedCtrl = _TRUE;
-+			} else if (pLed1->bLedOn)
-+				SwLedOff(padapter, pLed1);
-+		}
-+	}
-+
-+	switch (pLed->CurrLedState) {
-+	case LED_BLINK_SLOWLY:
-+		if (pLed->bLedOn)
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+		else
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
-+		break;
-+
-+	case LED_BLINK_NORMAL:
-+		if (pLed->bLedOn)
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+		else
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+		_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
-+		break;
-+
-+	case LED_BLINK_SCAN:
-+		pLed->BlinkTimes--;
-+		if (pLed->BlinkTimes == 0)
-+			bStopBlinking = _TRUE;
-+
-+		if (bStopBlinking) {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+				SwLedOff(padapter, pLed);
-+			else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+				pLed->bLedLinkBlinkInProgress = _TRUE;
-+				pLed->CurrLedState = LED_BLINK_NORMAL;
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
-+
-+			} else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) {
-+				pLed->bLedNoLinkBlinkInProgress = _TRUE;
-+				pLed->CurrLedState = LED_BLINK_SLOWLY;
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
-+			}
-+			pLed->bLedScanBlinkInProgress = _FALSE;
-+		} else {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+				SwLedOff(padapter, pLed);
-+			else {
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
-+			}
-+		}
-+		break;
-+
-+	case LED_BLINK_TXRX:
-+		pLed->BlinkTimes--;
-+		if (pLed->BlinkTimes == 0)
-+			bStopBlinking = _TRUE;
-+		if (bStopBlinking) {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+				SwLedOff(padapter, pLed);
-+			else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+				pLed->bLedLinkBlinkInProgress = _TRUE;
-+				pLed->CurrLedState = LED_BLINK_NORMAL;
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
-+			} else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) {
-+				pLed->bLedNoLinkBlinkInProgress = _TRUE;
-+				pLed->CurrLedState = LED_BLINK_SLOWLY;
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
-+			}
-+			pLed->BlinkTimes = 0;
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		} else {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+				SwLedOff(padapter, pLed);
-+			else {
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
-+			}
-+		}
-+		break;
-+
-+	case LED_BLINK_WPS:
-+		if (pLed->bLedOn)
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+		else
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+		_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
-+		break;
-+
-+	case LED_BLINK_WPS_STOP:	/* WPS success */
-+		if (pLed->BlinkingLedState == RTW_LED_ON) {
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA);
-+			bStopBlinking = _FALSE;
-+		} else
-+			bStopBlinking = _TRUE;
-+
-+		if (bStopBlinking) {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+				SwLedOff(padapter, pLed);
-+			else {
-+				pLed->bLedLinkBlinkInProgress = _TRUE;
-+				pLed->CurrLedState = LED_BLINK_NORMAL;
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
-+			}
-+			pLed->bLedWPSBlinkInProgress = _FALSE;
-+		}
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+}
-+
-+void
-+SwLedBlink2(
-+	PLED_SDIO			pLed
-+)
-+{
-+	_adapter				*padapter = pLed->padapter;
-+	struct mlme_priv		*pmlmepriv = &(padapter->mlmepriv);
-+	u8					bStopBlinking = _FALSE;
-+
-+	/* Change LED according to BlinkingLedState specified. */
-+	if (pLed->BlinkingLedState == RTW_LED_ON) {
-+		SwLedOn(padapter, pLed);
-+	} else {
-+		SwLedOff(padapter, pLed);
-+	}
-+
-+	switch (pLed->CurrLedState) {
-+	case LED_BLINK_SCAN:
-+		pLed->BlinkTimes--;
-+		if (pLed->BlinkTimes == 0)
-+			bStopBlinking = _TRUE;
-+
-+		if (bStopBlinking) {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+				SwLedOff(padapter, pLed);
-+			else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+				pLed->CurrLedState = RTW_LED_ON;
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+				SwLedOn(padapter, pLed);
-+
-+			} else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) {
-+				pLed->CurrLedState = RTW_LED_OFF;
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+				SwLedOff(padapter, pLed);
-+			}
-+			pLed->bLedScanBlinkInProgress = _FALSE;
-+		} else {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+				SwLedOff(padapter, pLed);
-+			else {
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
-+			}
-+		}
-+		break;
-+
-+	case LED_BLINK_TXRX:
-+		pLed->BlinkTimes--;
-+		if (pLed->BlinkTimes == 0)
-+			bStopBlinking = _TRUE;
-+		if (bStopBlinking) {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+				SwLedOff(padapter, pLed);
-+			else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+				pLed->CurrLedState = RTW_LED_ON;
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+				SwLedOn(padapter, pLed);
-+
-+			} else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) {
-+				pLed->CurrLedState = RTW_LED_OFF;
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+				SwLedOff(padapter, pLed);
-+			}
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		} else {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+				SwLedOff(padapter, pLed);
-+			else {
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
-+			}
-+		}
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+}
-+
-+void
-+SwLedBlink3(
-+	PLED_SDIO			pLed
-+)
-+{
-+	_adapter			*padapter = pLed->padapter;
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	u8				bStopBlinking = _FALSE;
-+
-+	/* Change LED according to BlinkingLedState specified. */
-+	if (pLed->BlinkingLedState == RTW_LED_ON) {
-+		SwLedOn(padapter, pLed);
-+	} else {
-+		if (pLed->CurrLedState != LED_BLINK_WPS_STOP)
-+			SwLedOff(padapter, pLed);
-+	}
-+
-+	switch (pLed->CurrLedState) {
-+	case LED_BLINK_SCAN:
-+		pLed->BlinkTimes--;
-+		if (pLed->BlinkTimes == 0)
-+			bStopBlinking = _TRUE;
-+
-+		if (bStopBlinking) {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+				SwLedOff(padapter, pLed);
-+			else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+				pLed->CurrLedState = RTW_LED_ON;
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+				if (!pLed->bLedOn)
-+					SwLedOn(padapter, pLed);
-+
-+			} else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) {
-+				pLed->CurrLedState = RTW_LED_OFF;
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+				if (pLed->bLedOn)
-+					SwLedOff(padapter, pLed);
-+
-+			}
-+			pLed->bLedScanBlinkInProgress = _FALSE;
-+		} else {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+				SwLedOff(padapter, pLed);
-+			else {
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
-+			}
-+		}
-+		break;
-+
-+	case LED_BLINK_TXRX:
-+		pLed->BlinkTimes--;
-+		if (pLed->BlinkTimes == 0)
-+			bStopBlinking = _TRUE;
-+		if (bStopBlinking) {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+				SwLedOff(padapter, pLed);
-+			else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+				pLed->CurrLedState = RTW_LED_ON;
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+
-+				if (!pLed->bLedOn)
-+					SwLedOn(padapter, pLed);
-+
-+			} else if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE) {
-+				pLed->CurrLedState = RTW_LED_OFF;
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+
-+				if (pLed->bLedOn)
-+					SwLedOff(padapter, pLed);
-+
-+
-+			}
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		} else {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+				SwLedOff(padapter, pLed);
-+			else {
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
-+			}
-+		}
-+		break;
-+
-+	case LED_BLINK_WPS:
-+		if (pLed->bLedOn)
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+		else
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+		_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
-+		break;
-+
-+	case LED_BLINK_WPS_STOP:	/* WPS success */
-+		if (pLed->BlinkingLedState == RTW_LED_ON) {
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA);
-+			bStopBlinking = _FALSE;
-+		} else
-+			bStopBlinking = _TRUE;
-+
-+		if (bStopBlinking) {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on)
-+				SwLedOff(padapter, pLed);
-+			else {
-+				pLed->CurrLedState = RTW_LED_ON;
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+				SwLedOn(padapter, pLed);
-+			}
-+			pLed->bLedWPSBlinkInProgress = _FALSE;
-+		}
-+		break;
-+
-+
-+	default:
-+		break;
-+	}
-+
-+}
-+
-+
-+void
-+SwLedBlink4(
-+	PLED_SDIO			pLed
-+)
-+{
-+	_adapter			*padapter = pLed->padapter;
-+	struct led_priv	*ledpriv = adapter_to_led(padapter);
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	PLED_SDIO		pLed1 = &(ledpriv->SwLed1);
-+	u8				bStopBlinking = _FALSE;
-+
-+	/* Change LED according to BlinkingLedState specified. */
-+	if (pLed->BlinkingLedState == RTW_LED_ON) {
-+		SwLedOn(padapter, pLed);
-+	} else {
-+		SwLedOff(padapter, pLed);
-+	}
-+
-+	if (!pLed1->bLedWPSBlinkInProgress && pLed1->BlinkingLedState == LED_UNKNOWN) {
-+		pLed1->BlinkingLedState = RTW_LED_OFF;
-+		pLed1->CurrLedState = RTW_LED_OFF;
-+		SwLedOff(padapter, pLed1);
-+	}
-+
-+	switch (pLed->CurrLedState) {
-+	case LED_BLINK_SLOWLY:
-+		if (pLed->bLedOn)
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+		else
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
-+		break;
-+
-+	case LED_BLINK_StartToBlink:
-+		if (pLed->bLedOn) {
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
-+		} else {
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
-+		}
-+		break;
-+
-+	case LED_BLINK_SCAN:
-+		pLed->BlinkTimes--;
-+		if (pLed->BlinkTimes == 0)
-+			bStopBlinking = _FALSE;
-+
-+		if (bStopBlinking) {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS)
-+				SwLedOff(padapter, pLed);
-+			else {
-+				pLed->bLedNoLinkBlinkInProgress = _FALSE;
-+				pLed->CurrLedState = LED_BLINK_SLOWLY;
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
-+			}
-+			pLed->bLedScanBlinkInProgress = _FALSE;
-+		} else {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS)
-+				SwLedOff(padapter, pLed);
-+			else {
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
-+			}
-+		}
-+		break;
-+
-+	case LED_BLINK_TXRX:
-+		pLed->BlinkTimes--;
-+		if (pLed->BlinkTimes == 0)
-+			bStopBlinking = _TRUE;
-+		if (bStopBlinking) {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS)
-+				SwLedOff(padapter, pLed);
-+			else {
-+				pLed->bLedNoLinkBlinkInProgress = _TRUE;
-+				pLed->CurrLedState = LED_BLINK_SLOWLY;
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
-+			}
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		} else {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS)
-+				SwLedOff(padapter, pLed);
-+			else {
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
-+			}
-+		}
-+		break;
-+
-+	case LED_BLINK_WPS:
-+		if (pLed->bLedOn) {
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
-+		} else {
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
-+		}
-+		break;
-+
-+	case LED_BLINK_WPS_STOP:	/* WPS authentication fail */
-+		if (pLed->bLedOn)
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+		else
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+
-+		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
-+		break;
-+
-+	case LED_BLINK_WPS_STOP_OVERLAP:	/* WPS session overlap */
-+		pLed->BlinkTimes--;
-+		if (pLed->BlinkTimes == 0) {
-+			if (pLed->bLedOn)
-+				pLed->BlinkTimes = 1;
-+			else
-+				bStopBlinking = _TRUE;
-+		}
-+
-+		if (bStopBlinking) {
-+			pLed->BlinkTimes = 10;
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
-+		} else {
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
-+		}
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+
-+
-+}
-+
-+void
-+SwLedBlink5(
-+	PLED_SDIO			pLed
-+)
-+{
-+	_adapter			*padapter = pLed->padapter;
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	u8				bStopBlinking = _FALSE;
-+
-+	/* Change LED according to BlinkingLedState specified. */
-+	if (pLed->BlinkingLedState == RTW_LED_ON) {
-+		SwLedOn(padapter, pLed);
-+	} else {
-+		SwLedOff(padapter, pLed);
-+	}
-+
-+	switch (pLed->CurrLedState) {
-+	case LED_BLINK_SCAN:
-+		pLed->BlinkTimes--;
-+		if (pLed->BlinkTimes == 0)
-+			bStopBlinking = _TRUE;
-+
-+		if (bStopBlinking) {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) {
-+				pLed->CurrLedState = RTW_LED_OFF;
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+				if (pLed->bLedOn)
-+					SwLedOff(padapter, pLed);
-+			} else {
-+				pLed->CurrLedState = RTW_LED_ON;
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+				if (!pLed->bLedOn)
-+					_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
-+			}
-+
-+			pLed->bLedScanBlinkInProgress = _FALSE;
-+		} else {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS)
-+				SwLedOff(padapter, pLed);
-+			else {
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
-+			}
-+		}
-+		break;
-+
-+
-+	case LED_BLINK_TXRX:
-+		pLed->BlinkTimes--;
-+		if (pLed->BlinkTimes == 0)
-+			bStopBlinking = _TRUE;
-+
-+		if (bStopBlinking) {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) {
-+				pLed->CurrLedState = RTW_LED_OFF;
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+				if (pLed->bLedOn)
-+					SwLedOff(padapter, pLed);
-+			} else {
-+				pLed->CurrLedState = RTW_LED_ON;
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+				if (!pLed->bLedOn)
-+					_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
-+			}
-+
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		} else {
-+			if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS)
-+				SwLedOff(padapter, pLed);
-+			else {
-+				if (pLed->bLedOn)
-+					pLed->BlinkingLedState = RTW_LED_OFF;
-+				else
-+					pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
-+			}
-+		}
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+
-+
-+}
-+
-+void
-+SwLedBlink6(
-+	PLED_SDIO			pLed
-+)
-+{
-+	_adapter			*padapter = pLed->padapter;
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	u8				bStopBlinking = _FALSE;
-+
-+	/* Change LED according to BlinkingLedState specified. */
-+	if (pLed->BlinkingLedState == RTW_LED_ON) {
-+		SwLedOn(padapter, pLed);
-+	} else {
-+		SwLedOff(padapter, pLed);
-+	}
-+
-+}
-+
-+/*
-+ *	Description:
-+ *		Handler function of LED Blinking.
-+ *		We dispatch acture LED blink action according to LedStrategy.
-+ *   */
-+void BlinkHandler(PLED_SDIO	pLed)
-+{
-+	_adapter		*padapter = pLed->padapter;
-+	struct led_priv	*ledpriv = adapter_to_led(padapter);
-+
-+	/* RTW_INFO("%s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); */
-+	if (RTW_CANNOT_RUN(padapter) || (!rtw_is_hw_init_completed(padapter))) {
-+		RTW_INFO("%s bDriverStopped:%s, bSurpriseRemoved:%s\n"
-+			 , __func__
-+			 , rtw_is_drv_stopped(padapter) ? "True" : "False"
-+			, rtw_is_surprise_removed(padapter) ? "True" : "False");
-+
-+		return;
-+	}
-+
-+	switch (ledpriv->LedStrategy) {
-+	#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
-+	case SW_LED_MODE_UC_TRX_ONLY:
-+		rtw_sw_led_blink_uc_trx_only(pLed);
-+		break;
-+	#endif
-+
-+	case SW_LED_MODE0:
-+		SwLedBlink(pLed);
-+		break;
-+
-+	case SW_LED_MODE1:
-+		SwLedBlink1(pLed);
-+		break;
-+
-+	case SW_LED_MODE2:
-+		SwLedBlink2(pLed);
-+		break;
-+
-+	case SW_LED_MODE3:
-+		SwLedBlink3(pLed);
-+		break;
-+
-+	case SW_LED_MODE4:
-+		SwLedBlink4(pLed);
-+		break;
-+
-+	case SW_LED_MODE5:
-+		SwLedBlink5(pLed);
-+		break;
-+
-+	case SW_LED_MODE6:
-+		SwLedBlink6(pLed);
-+		break;
-+
-+	default:
-+		/* SwLedBlink(pLed); */
-+		break;
-+	}
-+}
-+
-+/*
-+ *	Description:
-+ *		Callback function of LED BlinkTimer,
-+ *		it just schedules to corresponding BlinkWorkItem/led_blink_hdl
-+ *   */
-+void BlinkTimerCallback(void *data)
-+{
-+	PLED_SDIO	 pLed = (PLED_SDIO)data;
-+	_adapter		*padapter = pLed->padapter;
-+
-+	/* RTW_INFO("%s\n", __FUNCTION__); */
-+
-+	if (RTW_CANNOT_RUN(padapter) || (!rtw_is_hw_init_completed(padapter))) {
-+		/*RTW_INFO("%s bDriverStopped:%s, bSurpriseRemoved:%s\n"
-+			, __func__
-+			, rtw_is_drv_stopped(padapter)?"True":"False"
-+			, rtw_is_surprise_removed(padapter)?"True":"False" );*/
-+		return;
-+	}
-+
-+#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD
-+	rtw_led_blink_cmd(padapter, pLed);
-+#else
-+	_set_workitem(&(pLed->BlinkWorkItem));
-+#endif
-+}
-+
-+/*
-+ *	Description:
-+ *		Callback function of LED BlinkWorkItem.
-+ *		We dispatch acture LED blink action according to LedStrategy.
-+ *   */
-+void BlinkWorkItemCallback(_workitem *work)
-+{
-+	PLED_SDIO	 pLed = container_of(work, LED_SDIO, BlinkWorkItem);
-+	BlinkHandler(pLed);
-+}
-+
-+static void
-+SwLedControlMode0(
-+	_adapter		*padapter,
-+	LED_CTL_MODE		LedAction
-+)
-+{
-+	struct led_priv	*ledpriv = adapter_to_led(padapter);
-+	PLED_SDIO	pLed = &(ledpriv->SwLed1);
-+
-+	/* Decide led state */
-+	switch (LedAction) {
-+	case LED_CTL_TX:
-+	case LED_CTL_RX:
-+		if (pLed->bLedBlinkInProgress == _FALSE) {
-+			pLed->bLedBlinkInProgress = _TRUE;
-+
-+			pLed->CurrLedState = LED_BLINK_NORMAL;
-+			pLed->BlinkTimes = 2;
-+
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
-+		}
-+		break;
-+
-+	case LED_CTL_START_TO_LINK:
-+		if (pLed->bLedBlinkInProgress == _FALSE) {
-+			pLed->bLedBlinkInProgress = _TRUE;
-+
-+			pLed->CurrLedState = LED_BLINK_StartToBlink;
-+			pLed->BlinkTimes = 24;
-+
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
-+		} else
-+			pLed->CurrLedState = LED_BLINK_StartToBlink;
-+		break;
-+
-+	case LED_CTL_LINK:
-+		pLed->CurrLedState = RTW_LED_ON;
-+		if (pLed->bLedBlinkInProgress == _FALSE) {
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), 0);
-+		}
-+		break;
-+
-+	case LED_CTL_NO_LINK:
-+		pLed->CurrLedState = RTW_LED_OFF;
-+		if (pLed->bLedBlinkInProgress == _FALSE) {
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+			_set_timer(&(pLed->BlinkTimer), 0);
-+		}
-+		break;
-+
-+	case LED_CTL_POWER_OFF:
-+		pLed->CurrLedState = RTW_LED_OFF;
-+		if (pLed->bLedBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		}
-+		SwLedOff(padapter, pLed);
-+		break;
-+
-+	case LED_CTL_START_WPS:
-+		if (pLed->bLedBlinkInProgress == _FALSE || pLed->CurrLedState == RTW_LED_ON) {
-+			pLed->bLedBlinkInProgress = _TRUE;
-+
-+			pLed->CurrLedState = LED_BLINK_WPS;
-+			pLed->BlinkTimes = 20;
-+
-+			if (pLed->bLedOn) {
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL);
-+			} else {
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL);
-+			}
-+		}
-+		break;
-+
-+	case LED_CTL_STOP_WPS:
-+		if (pLed->bLedBlinkInProgress) {
-+			pLed->CurrLedState = RTW_LED_OFF;
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		}
-+		break;
-+
-+
-+	default:
-+		break;
-+	}
-+
-+
-+}
-+
-+/* ALPHA, added by chiyoko, 20090106 */
-+static void
-+SwLedControlMode1(
-+	_adapter		*padapter,
-+	LED_CTL_MODE		LedAction
-+)
-+{
-+	struct led_priv		*ledpriv = adapter_to_led(padapter);
-+	PLED_SDIO			pLed = &(ledpriv->SwLed0);
-+	struct mlme_priv		*pmlmepriv = &(padapter->mlmepriv);
-+	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(padapter);
-+
-+	if (pHalData->CustomerID == RT_CID_819x_CAMEO)
-+		pLed = &(ledpriv->SwLed1);
-+
-+	switch (LedAction) {
-+	case LED_CTL_POWER_ON:
-+	case LED_CTL_START_TO_LINK:
-+	case LED_CTL_NO_LINK:
-+		if (pLed->bLedNoLinkBlinkInProgress == _FALSE) {
-+			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
-+				return;
-+			if (pLed->bLedLinkBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedLinkBlinkInProgress = _FALSE;
-+			}
-+			if (pLed->bLedBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedBlinkInProgress = _FALSE;
-+			}
-+
-+			pLed->bLedNoLinkBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_SLOWLY;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	case LED_CTL_LINK:
-+		if (pLed->bLedLinkBlinkInProgress == _FALSE) {
-+			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
-+				return;
-+			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedNoLinkBlinkInProgress = _FALSE;
-+			}
-+			if (pLed->bLedBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedBlinkInProgress = _FALSE;
-+			}
-+			pLed->bLedLinkBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_NORMAL;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	case LED_CTL_SITE_SURVEY:
-+		if ((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE))
-+			;
-+		else if (pLed->bLedScanBlinkInProgress == _FALSE) {
-+			if (IS_LED_WPS_BLINKING(pLed))
-+				return;
-+
-+			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedNoLinkBlinkInProgress = _FALSE;
-+			}
-+			if (pLed->bLedLinkBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedLinkBlinkInProgress = _FALSE;
-+			}
-+			if (pLed->bLedBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedBlinkInProgress = _FALSE;
-+			}
-+			pLed->bLedScanBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_SCAN;
-+			pLed->BlinkTimes = 24;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
-+
-+		}
-+		break;
-+
-+	case LED_CTL_TX:
-+	case LED_CTL_RX:
-+		if (pLed->bLedBlinkInProgress == _FALSE) {
-+			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
-+				return;
-+			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedNoLinkBlinkInProgress = _FALSE;
-+			}
-+			if (pLed->bLedLinkBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedLinkBlinkInProgress = _FALSE;
-+			}
-+			pLed->bLedBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_TXRX;
-+			pLed->BlinkTimes = 2;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	case LED_CTL_START_WPS: /* wait until xinpin finish */
-+	case LED_CTL_START_WPS_BOTTON:
-+		if (pLed->bLedWPSBlinkInProgress == _FALSE) {
-+			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedNoLinkBlinkInProgress = _FALSE;
-+			}
-+			if (pLed->bLedLinkBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedLinkBlinkInProgress = _FALSE;
-+			}
-+			if (pLed->bLedBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedBlinkInProgress = _FALSE;
-+			}
-+			if (pLed->bLedScanBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedScanBlinkInProgress = _FALSE;
-+			}
-+			pLed->bLedWPSBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_WPS;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+
-+	case LED_CTL_STOP_WPS:
-+		if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedNoLinkBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedLinkBlinkInProgress == _TRUE) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedLinkBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedBlinkInProgress == _TRUE) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedScanBlinkInProgress == _TRUE) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedScanBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedWPSBlinkInProgress)
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+		else
-+			pLed->bLedWPSBlinkInProgress = _TRUE;
-+
-+		pLed->CurrLedState = LED_BLINK_WPS_STOP;
-+		if (pLed->bLedOn) {
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA);
-+		} else {
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), 0);
-+		}
-+		break;
-+
-+	case LED_CTL_STOP_WPS_FAIL:
-+		if (pLed->bLedWPSBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedWPSBlinkInProgress = _FALSE;
-+		}
-+
-+		pLed->bLedNoLinkBlinkInProgress = _TRUE;
-+		pLed->CurrLedState = LED_BLINK_SLOWLY;
-+		if (pLed->bLedOn)
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+		else
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
-+		break;
-+
-+	case LED_CTL_POWER_OFF:
-+		pLed->CurrLedState = RTW_LED_OFF;
-+		pLed->BlinkingLedState = RTW_LED_OFF;
-+		if (pLed->bLedNoLinkBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedNoLinkBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedLinkBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedLinkBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedWPSBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedWPSBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedScanBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedScanBlinkInProgress = _FALSE;
-+		}
-+
-+		SwLedOff(padapter, pLed);
-+		break;
-+
-+	default:
-+		break;
-+
-+	}
-+
-+}
-+
-+/* Arcadyan/Sitecom , added by chiyoko, 20090216 */
-+static void
-+SwLedControlMode2(
-+	_adapter				*padapter,
-+	LED_CTL_MODE		LedAction
-+)
-+{
-+	struct led_priv	*ledpriv = adapter_to_led(padapter);
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	PLED_SDIO		pLed = &(ledpriv->SwLed0);
-+
-+	switch (LedAction) {
-+	case LED_CTL_SITE_SURVEY:
-+		if (pmlmepriv->LinkDetectInfo.bBusyTraffic)
-+			;
-+		else if (pLed->bLedScanBlinkInProgress == _FALSE) {
-+			if (IS_LED_WPS_BLINKING(pLed))
-+				return;
-+
-+			if (pLed->bLedBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedBlinkInProgress = _FALSE;
-+			}
-+			pLed->bLedScanBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_SCAN;
-+			pLed->BlinkTimes = 24;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	case LED_CTL_TX:
-+	case LED_CTL_RX:
-+		if ((pLed->bLedBlinkInProgress == _FALSE) && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
-+			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
-+				return;
-+
-+			pLed->bLedBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_TXRX;
-+			pLed->BlinkTimes = 2;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	case LED_CTL_LINK:
-+		pLed->CurrLedState = RTW_LED_ON;
-+		pLed->BlinkingLedState = RTW_LED_ON;
-+		if (pLed->bLedBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedScanBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedScanBlinkInProgress = _FALSE;
-+		}
-+
-+		_set_timer(&(pLed->BlinkTimer), 0);
-+		break;
-+
-+	case LED_CTL_START_WPS: /* wait until xinpin finish */
-+	case LED_CTL_START_WPS_BOTTON:
-+		if (pLed->bLedWPSBlinkInProgress == _FALSE) {
-+			if (pLed->bLedBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedBlinkInProgress = _FALSE;
-+			}
-+			if (pLed->bLedScanBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedScanBlinkInProgress = _FALSE;
-+			}
-+			pLed->bLedWPSBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = RTW_LED_ON;
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), 0);
-+		}
-+		break;
-+
-+	case LED_CTL_STOP_WPS:
-+		pLed->bLedWPSBlinkInProgress = _FALSE;
-+		if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on) {
-+			pLed->CurrLedState = RTW_LED_OFF;
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+			_set_timer(&(pLed->BlinkTimer), 0);
-+		} else {
-+			pLed->CurrLedState = RTW_LED_ON;
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), 0);
-+		}
-+		break;
-+
-+	case LED_CTL_STOP_WPS_FAIL:
-+		pLed->bLedWPSBlinkInProgress = _FALSE;
-+		pLed->CurrLedState = RTW_LED_OFF;
-+		pLed->BlinkingLedState = RTW_LED_OFF;
-+		_set_timer(&(pLed->BlinkTimer), 0);
-+		break;
-+
-+	case LED_CTL_START_TO_LINK:
-+	case LED_CTL_NO_LINK:
-+		if (!IS_LED_BLINKING(pLed)) {
-+			pLed->CurrLedState = RTW_LED_OFF;
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+			_set_timer(&(pLed->BlinkTimer), 0);
-+		}
-+		break;
-+
-+	case LED_CTL_POWER_OFF:
-+		pLed->CurrLedState = RTW_LED_OFF;
-+		pLed->BlinkingLedState = RTW_LED_OFF;
-+		if (pLed->bLedBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedScanBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedScanBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedWPSBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedWPSBlinkInProgress = _FALSE;
-+		}
-+
-+		SwLedOff(padapter, pLed);
-+		break;
-+
-+	default:
-+		break;
-+
-+	}
-+
-+}
-+
-+/* COREGA, added by chiyoko, 20090316 */
-+static void
-+SwLedControlMode3(
-+	_adapter				*padapter,
-+	LED_CTL_MODE		LedAction
-+)
-+{
-+	struct led_priv	*ledpriv = adapter_to_led(padapter);
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	PLED_SDIO		pLed = &(ledpriv->SwLed0);
-+
-+	switch (LedAction) {
-+	case LED_CTL_SITE_SURVEY:
-+		if (pmlmepriv->LinkDetectInfo.bBusyTraffic)
-+			;
-+		else if (pLed->bLedScanBlinkInProgress == _FALSE) {
-+			if (IS_LED_WPS_BLINKING(pLed))
-+				return;
-+
-+			if (pLed->bLedBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedBlinkInProgress = _FALSE;
-+			}
-+			pLed->bLedScanBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_SCAN;
-+			pLed->BlinkTimes = 24;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	case LED_CTL_TX:
-+	case LED_CTL_RX:
-+		if ((pLed->bLedBlinkInProgress == _FALSE) && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
-+			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
-+				return;
-+
-+			pLed->bLedBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_TXRX;
-+			pLed->BlinkTimes = 2;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	case LED_CTL_LINK:
-+		if (IS_LED_WPS_BLINKING(pLed))
-+			return;
-+
-+		pLed->CurrLedState = RTW_LED_ON;
-+		pLed->BlinkingLedState = RTW_LED_ON;
-+		if (pLed->bLedBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedScanBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedScanBlinkInProgress = _FALSE;
-+		}
-+
-+		_set_timer(&(pLed->BlinkTimer), 0);
-+		break;
-+
-+	case LED_CTL_START_WPS: /* wait until xinpin finish */
-+	case LED_CTL_START_WPS_BOTTON:
-+		if (pLed->bLedWPSBlinkInProgress == _FALSE) {
-+			if (pLed->bLedBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedBlinkInProgress = _FALSE;
-+			}
-+			if (pLed->bLedScanBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedScanBlinkInProgress = _FALSE;
-+			}
-+			pLed->bLedWPSBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_WPS;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	case LED_CTL_STOP_WPS:
-+		if (pLed->bLedWPSBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedWPSBlinkInProgress = _FALSE;
-+		} else
-+			pLed->bLedWPSBlinkInProgress = _TRUE;
-+
-+		pLed->CurrLedState = LED_BLINK_WPS_STOP;
-+		if (pLed->bLedOn) {
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA);
-+		} else {
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), 0);
-+		}
-+
-+		break;
-+
-+	case LED_CTL_STOP_WPS_FAIL:
-+		if (pLed->bLedWPSBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedWPSBlinkInProgress = _FALSE;
-+		}
-+
-+		pLed->CurrLedState = RTW_LED_OFF;
-+		pLed->BlinkingLedState = RTW_LED_OFF;
-+		_set_timer(&(pLed->BlinkTimer), 0);
-+		break;
-+
-+	case LED_CTL_START_TO_LINK:
-+	case LED_CTL_NO_LINK:
-+		if (!IS_LED_BLINKING(pLed)) {
-+			pLed->CurrLedState = RTW_LED_OFF;
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+			_set_timer(&(pLed->BlinkTimer), 0);
-+		}
-+		break;
-+
-+	case LED_CTL_POWER_OFF:
-+		pLed->CurrLedState = RTW_LED_OFF;
-+		pLed->BlinkingLedState = RTW_LED_OFF;
-+		if (pLed->bLedBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedScanBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedScanBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedWPSBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedWPSBlinkInProgress = _FALSE;
-+		}
-+
-+		SwLedOff(padapter, pLed);
-+		break;
-+
-+	default:
-+		break;
-+
-+	}
-+
-+}
-+
-+
-+/* Edimax-Belkin, added by chiyoko, 20090413 */
-+static void
-+SwLedControlMode4(
-+	_adapter				*padapter,
-+	LED_CTL_MODE		LedAction
-+)
-+{
-+	struct led_priv	*ledpriv = adapter_to_led(padapter);
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	PLED_SDIO		pLed = &(ledpriv->SwLed0);
-+	PLED_SDIO		pLed1 = &(ledpriv->SwLed1);
-+
-+	switch (LedAction) {
-+	case LED_CTL_START_TO_LINK:
-+		if (pLed1->bLedWPSBlinkInProgress) {
-+			pLed1->bLedWPSBlinkInProgress = _FALSE;
-+			_cancel_timer_ex(&(pLed1->BlinkTimer));
-+
-+			pLed1->BlinkingLedState = RTW_LED_OFF;
-+			pLed1->CurrLedState = RTW_LED_OFF;
-+
-+			if (pLed1->bLedOn)
-+				_set_timer(&(pLed->BlinkTimer), 0);
-+		}
-+
-+		if (pLed->bLedStartToLinkBlinkInProgress == _FALSE) {
-+			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
-+				return;
-+			if (pLed->bLedBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedBlinkInProgress = _FALSE;
-+			}
-+			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedNoLinkBlinkInProgress = _FALSE;
-+			}
-+
-+			pLed->bLedStartToLinkBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_StartToBlink;
-+			if (pLed->bLedOn) {
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
-+			} else {
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
-+			}
-+		}
-+		break;
-+
-+	case LED_CTL_LINK:
-+	case LED_CTL_NO_LINK:
-+		/* LED1 settings */
-+		if (LedAction == LED_CTL_LINK) {
-+			if (pLed1->bLedWPSBlinkInProgress) {
-+				pLed1->bLedWPSBlinkInProgress = _FALSE;
-+				_cancel_timer_ex(&(pLed1->BlinkTimer));
-+
-+				pLed1->BlinkingLedState = RTW_LED_OFF;
-+				pLed1->CurrLedState = RTW_LED_OFF;
-+
-+				if (pLed1->bLedOn)
-+					_set_timer(&(pLed->BlinkTimer), 0);
-+			}
-+		}
-+
-+		if (pLed->bLedNoLinkBlinkInProgress == _FALSE) {
-+			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
-+				return;
-+			if (pLed->bLedBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedBlinkInProgress = _FALSE;
-+			}
-+
-+			pLed->bLedNoLinkBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_SLOWLY;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	case LED_CTL_SITE_SURVEY:
-+		if ((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE))
-+			;
-+		else if (pLed->bLedScanBlinkInProgress == _FALSE) {
-+			if (IS_LED_WPS_BLINKING(pLed))
-+				return;
-+
-+			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedNoLinkBlinkInProgress = _FALSE;
-+			}
-+			if (pLed->bLedBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedBlinkInProgress = _FALSE;
-+			}
-+			pLed->bLedScanBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_SCAN;
-+			pLed->BlinkTimes = 24;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	case LED_CTL_TX:
-+	case LED_CTL_RX:
-+		if (pLed->bLedBlinkInProgress == _FALSE) {
-+			if (pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed))
-+				return;
-+			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedNoLinkBlinkInProgress = _FALSE;
-+			}
-+			pLed->bLedBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_TXRX;
-+			pLed->BlinkTimes = 2;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	case LED_CTL_START_WPS: /* wait until xinpin finish */
-+	case LED_CTL_START_WPS_BOTTON:
-+		if (pLed1->bLedWPSBlinkInProgress) {
-+			pLed1->bLedWPSBlinkInProgress = _FALSE;
-+			_cancel_timer_ex(&(pLed1->BlinkTimer));
-+
-+			pLed1->BlinkingLedState = RTW_LED_OFF;
-+			pLed1->CurrLedState = RTW_LED_OFF;
-+
-+			if (pLed1->bLedOn)
-+				_set_timer(&(pLed->BlinkTimer), 0);
-+		}
-+
-+		if (pLed->bLedWPSBlinkInProgress == _FALSE) {
-+			if (pLed->bLedNoLinkBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedNoLinkBlinkInProgress = _FALSE;
-+			}
-+			if (pLed->bLedBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedBlinkInProgress = _FALSE;
-+			}
-+			if (pLed->bLedScanBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedScanBlinkInProgress = _FALSE;
-+			}
-+			pLed->bLedWPSBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_WPS;
-+			if (pLed->bLedOn) {
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL);
-+			} else {
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+				_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
-+			}
-+		}
-+		break;
-+
-+	case LED_CTL_STOP_WPS:	/* WPS connect success */
-+		if (pLed->bLedWPSBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedWPSBlinkInProgress = _FALSE;
-+		}
-+
-+		pLed->bLedNoLinkBlinkInProgress = _TRUE;
-+		pLed->CurrLedState = LED_BLINK_SLOWLY;
-+		if (pLed->bLedOn)
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+		else
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
-+
-+		break;
-+
-+	case LED_CTL_STOP_WPS_FAIL:		/* WPS authentication fail */
-+		if (pLed->bLedWPSBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedWPSBlinkInProgress = _FALSE;
-+		}
-+
-+		pLed->bLedNoLinkBlinkInProgress = _TRUE;
-+		pLed->CurrLedState = LED_BLINK_SLOWLY;
-+		if (pLed->bLedOn)
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+		else
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
-+
-+		/* LED1 settings */
-+		if (pLed1->bLedWPSBlinkInProgress)
-+			_cancel_timer_ex(&(pLed1->BlinkTimer));
-+		else
-+			pLed1->bLedWPSBlinkInProgress = _TRUE;
-+
-+		pLed1->CurrLedState = LED_BLINK_WPS_STOP;
-+		if (pLed1->bLedOn)
-+			pLed1->BlinkingLedState = RTW_LED_OFF;
-+		else
-+			pLed1->BlinkingLedState = RTW_LED_ON;
-+		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
-+
-+		break;
-+
-+	case LED_CTL_STOP_WPS_FAIL_OVERLAP:	/* WPS session overlap */
-+		if (pLed->bLedWPSBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedWPSBlinkInProgress = _FALSE;
-+		}
-+
-+		pLed->bLedNoLinkBlinkInProgress = _TRUE;
-+		pLed->CurrLedState = LED_BLINK_SLOWLY;
-+		if (pLed->bLedOn)
-+			pLed->BlinkingLedState = RTW_LED_OFF;
-+		else
-+			pLed->BlinkingLedState = RTW_LED_ON;
-+		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
-+
-+		/* LED1 settings */
-+		if (pLed1->bLedWPSBlinkInProgress)
-+			_cancel_timer_ex(&(pLed1->BlinkTimer));
-+		else
-+			pLed1->bLedWPSBlinkInProgress = _TRUE;
-+
-+		pLed1->CurrLedState = LED_BLINK_WPS_STOP_OVERLAP;
-+		pLed1->BlinkTimes = 10;
-+		if (pLed1->bLedOn)
-+			pLed1->BlinkingLedState = RTW_LED_OFF;
-+		else
-+			pLed1->BlinkingLedState = RTW_LED_ON;
-+		_set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL);
-+
-+		break;
-+
-+	case LED_CTL_POWER_OFF:
-+		pLed->CurrLedState = RTW_LED_OFF;
-+		pLed->BlinkingLedState = RTW_LED_OFF;
-+
-+		if (pLed->bLedNoLinkBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedNoLinkBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedLinkBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedLinkBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedWPSBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedWPSBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedScanBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedScanBlinkInProgress = _FALSE;
-+		}
-+		if (pLed->bLedStartToLinkBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedStartToLinkBlinkInProgress = _FALSE;
-+		}
-+
-+		if (pLed1->bLedWPSBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed1->BlinkTimer));
-+			pLed1->bLedWPSBlinkInProgress = _FALSE;
-+		}
-+
-+		pLed1->BlinkingLedState = LED_UNKNOWN;
-+		SwLedOff(padapter, pLed);
-+		SwLedOff(padapter, pLed1);
-+		break;
-+
-+	default:
-+		break;
-+
-+	}
-+
-+}
-+
-+
-+
-+/* Sercomm-Belkin, added by chiyoko, 20090415 */
-+static void
-+SwLedControlMode5(
-+	_adapter				*padapter,
-+	LED_CTL_MODE		LedAction
-+)
-+{
-+	struct led_priv	*ledpriv = adapter_to_led(padapter);
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	PLED_SDIO		pLed = &(ledpriv->SwLed0);
-+
-+	if (pHalData->CustomerID == RT_CID_819x_CAMEO)
-+		pLed = &(ledpriv->SwLed1);
-+
-+	switch (LedAction) {
-+	case LED_CTL_POWER_ON:
-+	case LED_CTL_NO_LINK:
-+	case LED_CTL_LINK:	/* solid blue */
-+		pLed->CurrLedState = RTW_LED_ON;
-+		pLed->BlinkingLedState = RTW_LED_ON;
-+
-+		_set_timer(&(pLed->BlinkTimer), 0);
-+		break;
-+
-+	case LED_CTL_SITE_SURVEY:
-+		if ((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE))
-+			;
-+		else if (pLed->bLedScanBlinkInProgress == _FALSE) {
-+			if (pLed->bLedBlinkInProgress == _TRUE) {
-+				_cancel_timer_ex(&(pLed->BlinkTimer));
-+				pLed->bLedBlinkInProgress = _FALSE;
-+			}
-+			pLed->bLedScanBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_SCAN;
-+			pLed->BlinkTimes = 24;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	case LED_CTL_TX:
-+	case LED_CTL_RX:
-+		if (pLed->bLedBlinkInProgress == _FALSE) {
-+			if (pLed->CurrLedState == LED_BLINK_SCAN)
-+				return;
-+			pLed->bLedBlinkInProgress = _TRUE;
-+			pLed->CurrLedState = LED_BLINK_TXRX;
-+			pLed->BlinkTimes = 2;
-+			if (pLed->bLedOn)
-+				pLed->BlinkingLedState = RTW_LED_OFF;
-+			else
-+				pLed->BlinkingLedState = RTW_LED_ON;
-+			_set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
-+		}
-+		break;
-+
-+	case LED_CTL_POWER_OFF:
-+		pLed->CurrLedState = RTW_LED_OFF;
-+		pLed->BlinkingLedState = RTW_LED_OFF;
-+
-+		if (pLed->bLedBlinkInProgress) {
-+			_cancel_timer_ex(&(pLed->BlinkTimer));
-+			pLed->bLedBlinkInProgress = _FALSE;
-+		}
-+
-+		SwLedOff(padapter, pLed);
-+		break;
-+
-+	default:
-+		break;
-+
-+	}
-+
-+}
-+
-+/* WNC-Corega, added by chiyoko, 20090902 */
-+static void
-+SwLedControlMode6(
-+	_adapter				*padapter,
-+	LED_CTL_MODE		LedAction
-+)
-+{
-+	struct led_priv	*ledpriv = adapter_to_led(padapter);
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	PLED_SDIO pLed0 = &(ledpriv->SwLed0);
-+
-+	switch (LedAction) {
-+	case LED_CTL_POWER_ON:
-+	case LED_CTL_LINK:
-+	case LED_CTL_NO_LINK:
-+		_cancel_timer_ex(&(pLed0->BlinkTimer));
-+		pLed0->CurrLedState = RTW_LED_ON;
-+		pLed0->BlinkingLedState = RTW_LED_ON;
-+		_set_timer(&(pLed0->BlinkTimer), 0);
-+		break;
-+
-+	case LED_CTL_POWER_OFF:
-+		SwLedOff(padapter, pLed0);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+}
-+
-+void
-+LedControlSDIO(
-+	_adapter				*padapter,
-+	LED_CTL_MODE		LedAction
-+)
-+{
-+	struct led_priv	*ledpriv = adapter_to_led(padapter);
-+
-+#if (MP_DRIVER == 1)
-+	if (padapter->registrypriv.mp_mode == 1)
-+		return;
-+#endif
-+
-+	if (RTW_CANNOT_RUN(padapter) || (!rtw_is_hw_init_completed(padapter))) {
-+		/*RTW_INFO("%s bDriverStopped:%s, bSurpriseRemoved:%s\n"
-+		, __func__
-+		, rtw_is_drv_stopped(padapter)?"True":"False"
-+		, rtw_is_surprise_removed(padapter)?"True":"False");*/
-+		return;
-+	}
-+
-+	if (ledpriv->bRegUseLed == _FALSE)
-+		return;
-+
-+	/* if(priv->bInHctTest) */
-+	/*	return; */
-+
-+	if ((adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on &&
-+	     adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) &&
-+	    (LedAction == LED_CTL_TX || LedAction == LED_CTL_RX ||
-+	     LedAction == LED_CTL_SITE_SURVEY ||
-+	     LedAction == LED_CTL_LINK ||
-+	     LedAction == LED_CTL_NO_LINK ||
-+	     LedAction == LED_CTL_POWER_ON))
-+		return;
-+
-+	switch (ledpriv->LedStrategy) {
-+	#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
-+	case SW_LED_MODE_UC_TRX_ONLY:
-+		rtw_sw_led_ctl_mode_uc_trx_only(padapter, LedAction);
-+		break;
-+	#endif
-+
-+	case SW_LED_MODE0:
-+		SwLedControlMode0(padapter, LedAction);
-+		break;
-+
-+	case SW_LED_MODE1:
-+		SwLedControlMode1(padapter, LedAction);
-+		break;
-+	case SW_LED_MODE2:
-+		SwLedControlMode2(padapter, LedAction);
-+		break;
-+
-+	case SW_LED_MODE3:
-+		SwLedControlMode3(padapter, LedAction);
-+		break;
-+
-+	case SW_LED_MODE4:
-+		SwLedControlMode4(padapter, LedAction);
-+		break;
-+
-+	case SW_LED_MODE5:
-+		SwLedControlMode5(padapter, LedAction);
-+		break;
-+
-+	case SW_LED_MODE6:
-+		SwLedControlMode6(padapter, LedAction);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+}
-+
-+/*
-+ *	Description:
-+ *		Reset status of LED_871x object.
-+ *   */
-+void ResetLedStatus(PLED_SDIO pLed)
-+{
-+
-+	pLed->CurrLedState = RTW_LED_OFF; /* Current LED state. */
-+	pLed->bLedOn = _FALSE; /* true if LED is ON, false if LED is OFF. */
-+
-+	pLed->bLedBlinkInProgress = _FALSE; /* true if it is blinking, false o.w.. */
-+	pLed->bLedWPSBlinkInProgress = _FALSE;
-+
-+	pLed->BlinkTimes = 0; /* Number of times to toggle led state for blinking. */
-+	pLed->BlinkingLedState = LED_UNKNOWN; /* Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are. */
-+
-+	pLed->bLedNoLinkBlinkInProgress = _FALSE;
-+	pLed->bLedLinkBlinkInProgress = _FALSE;
-+	pLed->bLedStartToLinkBlinkInProgress = _FALSE;
-+	pLed->bLedScanBlinkInProgress = _FALSE;
-+}
-+
-+/*
-+*	Description:
-+*		Initialize an LED_871x object.
-+*   */
-+void
-+InitLed(
-+	_adapter			*padapter,
-+	PLED_SDIO		pLed,
-+	LED_PIN			LedPin
-+)
-+{
-+	pLed->padapter = padapter;
-+	pLed->LedPin = LedPin;
-+
-+	ResetLedStatus(pLed);
-+
-+	rtw_init_timer(&(pLed->BlinkTimer), padapter, BlinkTimerCallback, pLed);
-+
-+	_init_workitem(&(pLed->BlinkWorkItem), BlinkWorkItemCallback, pLed);
-+}
-+
-+
-+/*
-+ *	Description:
-+ *		DeInitialize an LED_871x object.
-+ *   */
-+void
-+DeInitLed(
-+	PLED_SDIO		pLed
-+)
-+{
-+	_cancel_workitem_sync(&(pLed->BlinkWorkItem));
-+	_cancel_timer_ex(&(pLed->BlinkTimer));
-+	ResetLedStatus(pLed);
-+}
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/ap_makefile.mk b/drivers/staging/rtl8723cs/hal/phydm/ap_makefile.mk
-new file mode 100644
-index 000000000000..120fc3d8ff63
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/ap_makefile.mk
-@@ -0,0 +1,237 @@
-+
-+_PHYDM_FILES :=\
-+	phydm/phydm.o \
-+	phydm/phydm_dig.o\
-+	phydm/phydm_antdiv.o\
-+	phydm/phydm_soml.o\
-+	phydm/phydm_smt_ant.o\
-+	phydm/phydm_pathdiv.o\
-+	phydm/phydm_rainfo.o\
-+	phydm/phydm_dynamictxpower.o\
-+	phydm/phydm_adaptivity.o\
-+	phydm/phydm_debug.o\
-+	phydm/phydm_interface.o\
-+	phydm/phydm_phystatus.o\
-+	phydm/phydm_hwconfig.o\
-+	phydm/phydm_dfs.o\
-+	phydm/phydm_cfotracking.o\
-+	phydm/phydm_adc_sampling.o\
-+	phydm/phydm_ccx.o\
-+	phydm/phydm_primary_cca.o\
-+	phydm/phydm_cck_pd.o\
-+	phydm/phydm_rssi_monitor.o\
-+	phydm/phydm_auto_dbg.o\
-+	phydm/phydm_math_lib.o\
-+	phydm/phydm_noisemonitor.o\
-+	phydm/phydm_api.o\
-+	phydm/phydm_pow_train.o\
-+	phydm/phydm_lna_sat.o\
-+	phydm/phydm_pmac_tx_setting.o\
-+	phydm/phydm_mp.o\
-+	phydm/phydm_cck_rx_pathdiv.o\
-+	phydm/phydm_direct_bf.o\
-+	phydm/txbf/phydm_hal_txbf_api.o\
-+	EdcaTurboCheck.o\
-+	phydm/halrf/halrf.o\
-+	phydm/halrf/halrf_debug.o\
-+	phydm/halrf/halphyrf_ap.o\
-+	phydm/halrf/halrf_powertracking_ap.o\
-+	phydm/halrf/halrf_powertracking.o\
-+	phydm/halrf/halrf_kfree.o\
-+	phydm/halrf/halrf_psd.o
-+
-+ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
-+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
-+		_PHYDM_FILES += \
-+		phydm/rtl8188e/halhwimg8188e_bb.o\
-+		phydm/rtl8188e/halhwimg8188e_mac.o\
-+		phydm/rtl8188e/halhwimg8188e_rf.o\
-+		phydm/rtl8188e/phydm_regconfig8188e.o\
-+		phydm/rtl8188e/hal8188erateadaptive.o\
-+		phydm/rtl8188e/phydm_rtl8188e.o\
-+		phydm/halrf/rtl8188e/halrf_8188e_ap.o
-+	endif
-+endif
-+
-+ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
-+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
-+		_PHYDM_FILES += ./phydm/halrf/rtl8812a/halrf_8812a_ap.o
-+	endif
-+	_PHYDM_FILES += phydm/rtl8812a/phydm_rtl8812a.o
-+endif
-+
-+ifeq ($(CONFIG_WLAN_HAL_8881A),y)
-+	_PHYDM_FILES += phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.o
-+endif
-+
-+ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
-+	_PHYDM_FILES += \
-+	phydm/halrf/rtl8192e/halrf_8192e_ap.o\
-+	phydm/rtl8192e/phydm_rtl8192e.o
-+endif
-+
-+ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
-+	rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o
-+	rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o
-+	rtl8192cd-objs += phydm/halrf/rtl8814a/halhwimg8814a_rf.o
-+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
-+		rtl8192cd-objs += \
-+		phydm/rtl8814a/halhwimg8814a_bb.o\
-+		phydm/rtl8814a/halhwimg8814a_mac.o\
-+		phydm/rtl8814a/phydm_regconfig8814a.o\
-+		phydm/rtl8814a/phydm_rtl8814a.o
-+	endif
-+endif
-+
-+ifeq ($(CONFIG_WLAN_HAL_8822BE),y)
-+	_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o
-+	_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o
-+	_PHYDM_FILES += phydm/halrf/rtl8822b/halhwimg8822b_rf.o
-+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
-+		_PHYDM_FILES += \
-+		phydm/rtl8822b/halhwimg8822b_bb.o\
-+		phydm/rtl8822b/halhwimg8822b_mac.o\
-+		phydm/rtl8822b/phydm_regconfig8822b.o\
-+		phydm/rtl8822b/phydm_hal_api8822b.o\
-+		phydm/rtl8822b/phydm_rtl8822b.o
-+	endif
-+endif
-+
-+ifeq ($(CONFIG_WLAN_HAL_8822CE),y)
-+	_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_8822c.o
-+	_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_iqk_8822c.o
-+	_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_dpk_8822c.o
-+	_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_rfk_init_8822c.o
-+	_PHYDM_FILES += phydm/halrf/rtl8822c/halhwimg8822c_rf.o
-+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
-+		_PHYDM_FILES += \
-+		phydm/rtl8822c/halhwimg8822c_bb.o\
-+		phydm/rtl8822c/phydm_regconfig8822c.o\
-+		phydm/rtl8822c/phydm_hal_api8822c.o
-+	endif
-+endif
-+
-+ifeq ($(CONFIG_WLAN_HAL_8812FE),y)
-+	_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_8812f.o
-+	_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_iqk_8812f.o
-+	_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_dpk_8812f.o
-+	_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_tssi_8812f.o
-+	_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_rfk_init_8812f.o
-+	_PHYDM_FILES += phydm/halrf/rtl8812f/halhwimg8812f_rf.o
-+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
-+		_PHYDM_FILES += \
-+		phydm/rtl8812f/halhwimg8812f_bb.o\
-+		phydm/rtl8812f/phydm_regconfig8812f.o\
-+		phydm/rtl8812f/phydm_hal_api8812f.o\
-+		phydm/rtl8812f/phydm_rtl8812f.o
-+	endif
-+endif
-+
-+ifeq ($(CONFIG_WLAN_HAL_8821CE),y)
-+	_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o
-+	_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o
-+	_PHYDM_FILES += phydm/halrf/rtl8821c/halhwimg8821c_rf.o
-+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
-+		_PHYDM_FILES += \
-+		phydm/rtl8821c/halhwimg8821c_bb.o\
-+		phydm/rtl8821c/halhwimg8821c_mac.o\
-+		phydm/rtl8821c/phydm_regconfig8821c.o\
-+		phydm/rtl8821c/phydm_hal_api8821c.o\
-+		phydm/rtl8821c/phydm_rtl8821c.o
-+	endif
-+endif
-+
-+ifeq ($(CONFIG_WLAN_HAL_8197F),y)
-+		_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o
-+		_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o
-+		_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_dpk_8197f.o
-+		_PHYDM_FILES += phydm/halrf/rtl8197f/halhwimg8197f_rf.o
-+		_PHYDM_FILES += efuse_97f/efuse.o
-+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
-+		_PHYDM_FILES += \
-+		phydm/rtl8197f/halhwimg8197f_bb.o\
-+		phydm/rtl8197f/halhwimg8197f_mac.o\
-+		phydm/rtl8197f/phydm_hal_api8197f.o\
-+		phydm/rtl8197f/phydm_regconfig8197f.o\
-+		phydm/rtl8197f/phydm_rtl8197f.o
-+	endif
-+endif
-+
-+
-+ifeq ($(CONFIG_WLAN_HAL_8192FE),y)
-+		_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_8192f.o
-+		_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_dpk_8192f.o
-+		_PHYDM_FILES += phydm/halrf/rtl8192f/halhwimg8192f_rf.o
-+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
-+		_PHYDM_FILES += \
-+		phydm/rtl8192f/halhwimg8192f_bb.o\
-+		phydm/rtl8192f/halhwimg8192f_mac.o\
-+		phydm/rtl8192f/phydm_hal_api8192f.o\
-+		phydm/rtl8192f/phydm_regconfig8192f.o\
-+		phydm/rtl8192f/phydm_rtl8192f.o
-+	endif
-+endif
-+
-+ifeq ($(CONFIG_WLAN_HAL_8198F),y)
-+		_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_8198f.o
-+		_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_iqk_8198f.o
-+		_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_dpk_8198f.o
-+		_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_rfk_init_8198f.o
-+		_PHYDM_FILES += phydm/halrf/rtl8198f/halhwimg8198f_rf.o
-+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
-+		_PHYDM_FILES += \
-+		phydm/rtl8198f/phydm_hal_api8198f.o\
-+		phydm/rtl8198f/halhwimg8198f_bb.o\
-+		phydm/rtl8198f/halhwimg8198f_mac.o\
-+		phydm/rtl8198f/phydm_regconfig8198f.o \
-+		phydm/halrf/rtl8198f/halrf_8198f.o
-+	endif
-+endif
-+
-+ifeq ($(CONFIG_WLAN_HAL_8814BE),y)
-+		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_8814b.o
-+		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_iqk_8814b.o
-+		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_dpk_8814b.o
-+		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_txgapk_8814b.o
-+		_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_rfk_init_8814b.o
-+		_PHYDM_FILES += phydm/halrf/rtl8814b/halhwimg8814b_rf.o
-+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
-+		_PHYDM_FILES += \
-+		phydm/rtl8814b/phydm_hal_api8814b.o\
-+		phydm/rtl8814b/halhwimg8814b_bb.o\
-+		phydm/rtl8814b/phydm_regconfig8814b.o \
-+		phydm/rtl8814b/phydm_extraagc8814b.o \
-+		phydm/halrf/rtl8814b/halrf_8814b.o
-+	endif
-+endif
-+
-+ifeq ($(CONFIG_WLAN_HAL_8197G),y)
-+		_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_8197g.o
-+		_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_iqk_8197g.o
-+		_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_dpk_8197g.o
-+		_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_tssi_8197g.o
-+		_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_rfk_init_8197g.o
-+		_PHYDM_FILES += phydm/halrf/rtl8197g/halhwimg8197g_rf.o
-+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
-+		_PHYDM_FILES += \
-+		phydm/rtl8197g/phydm_hal_api8197g.o\
-+		phydm/rtl8197g/halhwimg8197g_bb.o\
-+		phydm/rtl8197g/halhwimg8197g_mac.o\
-+		phydm/rtl8197g/phydm_regconfig8197g.o \
-+		phydm/rtl8197g/phydm_rtl8197g.o \
-+		phydm/halrf/rtl8197g/halrf_8197g.o
-+	endif
-+endif
-+ifeq ($(CONFIG_WLAN_HAL_8723FE),y)
-+	_PHYDM_FILES += phydm/halrf/rtl8723f/halrf_8723f.o
-+	_PHYDM_FILES += phydm/halrf/rtl8723f/halrf_iqk_8723f.o
-+	_PHYDM_FILES += phydm/halrf/rtl8723f/halrf_dpk_8723f.o
-+	_PHYDM_FILES += phydm/halrf/rtl8723f/halrf_rfk_init_8723f.o
-+	_PHYDM_FILES += phydm/halrf/rtl8723f/halhwimg8723f_rf.o
-+	ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
-+		_PHYDM_FILES += \
-+		phydm/rtl8723f/halhwimg8723f_bb.o\
-+		phydm/rtl8723f/phydm_regconfig8723f.o\
-+		phydm/rtl8723f/phydm_hal_api8723f.o
-+	endif
-+endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halhwimg.h b/drivers/staging/rtl8723cs/hal/phydm/halhwimg.h
-new file mode 100644
-index 000000000000..6d658b3935ed
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halhwimg.h
-@@ -0,0 +1,137 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#pragma once
-+#ifndef __INC_HW_IMG_H
-+#define __INC_HW_IMG_H
-+
-+/*@
-+ * 2011/03/15 MH Add for different IC HW image file selection. code size consideration.
-+ *   */
-+#if RT_PLATFORM == PLATFORM_LINUX
-+
-+	#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
-+		/* @For 92C */
-+		#define		RTL8192CE_HWIMG_SUPPORT					1
-+		#define		RTL8192CE_TEST_HWIMG_SUPPORT			0
-+		#define		RTL8192CU_HWIMG_SUPPORT					0
-+		#define		RTL8192CU_TEST_HWIMG_SUPPORT			0
-+
-+		/* @For 92D */
-+		#define		RTL8192DE_HWIMG_SUPPORT					1
-+		#define		RTL8192DE_TEST_HWIMG_SUPPORT			0
-+		#define		RTL8192DU_HWIMG_SUPPORT					0
-+		#define		RTL8192DU_TEST_HWIMG_SUPPORT			0
-+
-+		/* @For 8723 */
-+		#define		RTL8723E_HWIMG_SUPPORT					1
-+		#define		RTL8723U_HWIMG_SUPPORT					0
-+		#define		RTL8723S_HWIMG_SUPPORT					0
-+
-+		/* @For 88E */
-+		#define		RTL8188EE_HWIMG_SUPPORT					0
-+		#define		RTL8188EU_HWIMG_SUPPORT					0
-+		#define		RTL8188ES_HWIMG_SUPPORT					0
-+
-+	#elif (DEV_BUS_TYPE == RT_USB_INTERFACE)
-+		/* @For 92C */
-+		#define	RTL8192CE_HWIMG_SUPPORT				0
-+		#define	RTL8192CE_TEST_HWIMG_SUPPORT			0
-+		#define	RTL8192CU_HWIMG_SUPPORT				1
-+		#define	RTL8192CU_TEST_HWIMG_SUPPORT			0
-+
-+		/* @For 92D */
-+		#define	RTL8192DE_HWIMG_SUPPORT				0
-+		#define	RTL8192DE_TEST_HWIMG_SUPPORT			0
-+		#define	RTL8192DU_HWIMG_SUPPORT				1
-+		#define	RTL8192DU_TEST_HWIMG_SUPPORT			0
-+
-+		/* @For 8723 */
-+		#define	RTL8723E_HWIMG_SUPPORT					0
-+		#define	RTL8723U_HWIMG_SUPPORT					1
-+		#define	RTL8723S_HWIMG_SUPPORT					0
-+
-+		/* @For 88E */
-+		#define		RTL8188EE_HWIMG_SUPPORT					0
-+		#define		RTL8188EU_HWIMG_SUPPORT					0
-+		#define		RTL8188ES_HWIMG_SUPPORT					0
-+
-+	#elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
-+		/* @For 92C */
-+		#define	RTL8192CE_HWIMG_SUPPORT				0
-+		#define	RTL8192CE_TEST_HWIMG_SUPPORT			0
-+		#define	RTL8192CU_HWIMG_SUPPORT				1
-+		#define	RTL8192CU_TEST_HWIMG_SUPPORT			0
-+
-+		/* @For 92D */
-+		#define	RTL8192DE_HWIMG_SUPPORT				0
-+		#define	RTL8192DE_TEST_HWIMG_SUPPORT			0
-+		#define	RTL8192DU_HWIMG_SUPPORT				1
-+		#define	RTL8192DU_TEST_HWIMG_SUPPORT			0
-+
-+		/* @For 8723 */
-+		#define	RTL8723E_HWIMG_SUPPORT					0
-+		#define	RTL8723U_HWIMG_SUPPORT					0
-+		#define	RTL8723S_HWIMG_SUPPORT					1
-+
-+		/* @For 88E */
-+		#define		RTL8188EE_HWIMG_SUPPORT					0
-+		#define		RTL8188EU_HWIMG_SUPPORT					0
-+		#define		RTL8188ES_HWIMG_SUPPORT					0
-+	#endif
-+
-+#else	/* PLATFORM_WINDOWS & MacOSX */
-+
-+	/* @For 92C */
-+	#define		RTL8192CE_HWIMG_SUPPORT						1
-+	#define		RTL8192CE_TEST_HWIMG_SUPPORT				1
-+	#define		RTL8192CU_HWIMG_SUPPORT						1
-+	#define		RTL8192CU_TEST_HWIMG_SUPPORT				1
-+
-+	/* @For 92D */
-+	#define		RTL8192DE_HWIMG_SUPPORT					1
-+	#define		RTL8192DE_TEST_HWIMG_SUPPORT				1
-+	#define		RTL8192DU_HWIMG_SUPPORT					1
-+	#define		RTL8192DU_TEST_HWIMG_SUPPORT				1
-+
-+	#if defined(UNDER_CE)
-+		/* @For 8723 */
-+		#define		RTL8723E_HWIMG_SUPPORT					0
-+		#define		RTL8723U_HWIMG_SUPPORT					0
-+		#define		RTL8723S_HWIMG_SUPPORT					1
-+
-+		/* @For 88E */
-+		#define		RTL8188EE_HWIMG_SUPPORT					0
-+		#define		RTL8188EU_HWIMG_SUPPORT					0
-+		#define		RTL8188ES_HWIMG_SUPPORT					0
-+
-+	#else
-+
-+		/* @For 8723 */
-+		#define		RTL8723E_HWIMG_SUPPORT					1
-+		/* @#define		RTL_8723E_TEST_HWIMG_SUPPORT			1 */
-+		#define		RTL8723U_HWIMG_SUPPORT					1
-+		/* @#define		RTL_8723U_TEST_HWIMG_SUPPORT			1 */
-+		#define		RTL8723S_HWIMG_SUPPORT					1
-+		/* @#define		RTL_8723S_TEST_HWIMG_SUPPORT			1 */
-+
-+		/* @For 88E */
-+		#define		RTL8188EE_HWIMG_SUPPORT					1
-+		#define		RTL8188EU_HWIMG_SUPPORT					1
-+		#define		RTL8188ES_HWIMG_SUPPORT					1
-+	#endif
-+
-+#endif
-+
-+#endif /* @__INC_HW_IMG_H */
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_ap.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_ap.c
-new file mode 100644
-index 000000000000..857f01946842
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_ap.c
-@@ -0,0 +1,1674 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifndef index_mapping_NUM_88E
-+	#define	index_mapping_NUM_88E	15
-+#endif
-+
-+/* #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) */
-+
-+#define	CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
-+	do {\
-+		for (_offset = 0; _offset < _size; _offset++) { \
-+			\
-+			if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
-+				\
-+				if (_offset != 0)\
-+					_offset--;\
-+				break;\
-+			} \
-+		}			\
-+		if (_offset >= _size)\
-+			_offset = _size-1;\
-+	} while (0)
-+
-+void odm_clear_txpowertracking_state(	
-+	void *dm_void
-+)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
-+	struct rtl8192cd_priv *priv = dm->priv;
-+
-+	u8 i;
-+	
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>%s\n", __func__);
-+
-+	for (i = 0; i < MAX_RF_PATH; i++) {
-+		cali_info->absolute_ofdm_swing_idx[i] = 0;
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "cali_info->absolute_ofdm_swing_idx[%d]=%d\n",
-+			i, cali_info->absolute_ofdm_swing_idx[i]);
-+	}
-+
-+ 	dm->rf_calibrate_info.thermal_value = 0;
-+	dm->rf_calibrate_info.thermal_value_lck = 0;
-+	dm->rf_calibrate_info.thermal_value_iqk = 0;
-+}
-+
-+void configure_txpower_track(
-+	void		*dm_void,
-+	struct txpwrtrack_cfg	*config
-+)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+#if RTL8812A_SUPPORT
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	/* if (IS_HARDWARE_TYPE_8812(dm->adapter)) */
-+	if (dm->support_ic_type == ODM_RTL8812)
-+		configure_txpower_track_8812a(config);
-+	/* else */
-+#endif
-+#endif
-+
-+#if RTL8814A_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8814A)
-+		configure_txpower_track_8814a(config);
-+#endif
-+
-+
-+#if RTL8188E_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8188E)
-+		configure_txpower_track_8188e(config);
-+#endif
-+
-+#if RTL8197F_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8197F)
-+		configure_txpower_track_8197f(config);
-+#endif
-+
-+#if RTL8822B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8822B)
-+		configure_txpower_track_8822b(config);
-+#endif
-+
-+#if RTL8192F_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8192F)
-+		configure_txpower_track_8192f(config);
-+#endif
-+
-+#if RTL8198F_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8198F)
-+		configure_txpower_track_8198f(config);
-+#endif
-+
-+#if RTL8814B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8814B)
-+		configure_txpower_track_8814b(config);
-+#endif
-+
-+#if RTL8812F_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8812F)
-+		configure_txpower_track_8812f(config);
-+#endif
-+
-+#if RTL8197G_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8197G)
-+		configure_txpower_track_8197g(config);
-+#endif
-+
-+}
-+
-+#if (RTL8192E_SUPPORT == 1)
-+void
-+odm_txpowertracking_callback_thermal_meter_92e(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
-+	u8	thermal_value = 0, delta, delta_IQK, delta_LCK, channel, is_decrease, rf_mimo_mode;
-+	u8	thermal_value_avg_count = 0;
-+	u8     OFDM_min_index = 10; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur */
-+	s8	OFDM_index[2], index ;
-+	u32	thermal_value_avg = 0, reg0x18;
-+	u32	i = 0, j = 0, rf;
-+	s32	value32, CCK_index = 0, ele_A, ele_D, ele_C, X, Y;
-+	struct rtl8192cd_priv	*priv = dm->priv;
-+
-+	rf_mimo_mode = dm->rf_type;
-+	/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode); */
-+
-+#ifdef MP_TEST
-+	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
-+		channel = priv->pshare->working_channel;
-+		if (priv->pshare->mp_txpwr_tracking == false)
-+			return;
-+	} else
-+#endif
-+	{
-+		channel = (priv->pmib->dot11RFEntry.dot11channel);
-+	}
-+
-+	thermal_value = (unsigned char)odm_get_rf_reg(dm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
-+
-+
-+	switch (rf_mimo_mode) {
-+	case RF_1T1R:
-+		rf = 1;
-+		break;
-+	case RF_2T2R:
-+		rf = 2;
-+		break;
-+	default:
-+		rf = 2;
-+		break;
-+	}
-+
-+	/* Query OFDM path A default setting 	Bit[31:21] */
-+	ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);
-+	for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
-+		if (ele_D == (ofdm_swing_table_92e[i] >> 22)) {
-+			OFDM_index[0] = (unsigned char)i;
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0]);
-+			break;
-+		}
-+	}
-+
-+	/* Query OFDM path B default setting */
-+	if (rf_mimo_mode == RF_2T2R) {
-+		ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKOFDM_D);
-+		for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
-+			if (ele_D == (ofdm_swing_table_92e[i] >> 22)) {
-+				OFDM_index[1] = (unsigned char)i;
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]);
-+				break;
-+			}
-+		}
-+	}
-+
-+	/* calculate average thermal meter */
-+	{
-+		priv->pshare->thermal_value_avg_88xx[priv->pshare->thermal_value_avg_index_88xx] = thermal_value;
-+		priv->pshare->thermal_value_avg_index_88xx++;
-+		if (priv->pshare->thermal_value_avg_index_88xx == AVG_THERMAL_NUM_88XX)
-+			priv->pshare->thermal_value_avg_index_88xx = 0;
-+
-+		for (i = 0; i < AVG_THERMAL_NUM_88XX; i++) {
-+			if (priv->pshare->thermal_value_avg_88xx[i]) {
-+				thermal_value_avg += priv->pshare->thermal_value_avg_88xx[i];
-+				thermal_value_avg_count++;
-+			}
-+		}
-+
-+		if (thermal_value_avg_count) {
-+			thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count);
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
-+		}
-+	}
-+
-+	/* Initialize */
-+	if (!priv->pshare->thermal_value) {
-+		priv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther;
-+		priv->pshare->thermal_value_iqk = thermal_value;
-+		priv->pshare->thermal_value_lck = thermal_value;
-+	}
-+
-+	if (thermal_value != priv->pshare->thermal_value) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
-+
-+		delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
-+		delta_IQK = RTL_ABS(thermal_value, priv->pshare->thermal_value_iqk);
-+		delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck);
-+		is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0);
-+
-+#ifdef _TRACKING_TABLE_FILE
-+		if (priv->pshare->rf_ft_var.pwr_track_file) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
-+
-+			if (is_decrease) {
-+				for (i = 0; i < rf; i++) {
-+					OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
-+					OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]);
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
-+					CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
-+					CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index);
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n",  CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
-+				}
-+			} else {
-+				for (i = 0; i < rf; i++) {
-+					OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
-+					OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ?  OFDM_min_index : OFDM_index[i]);
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
-+					CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
-+					CCK_index = ((CCK_index < 0) ? 0 : CCK_index);
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
-+				}
-+			}
-+		}
-+#endif /* CFG_TRACKING_TABLE_FILE */
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);
-+
-+		/* Adujst OFDM Ant_A according to IQK result */
-+		ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22;
-+		X = priv->pshare->rege94;
-+		Y = priv->pshare->rege9c;
-+
-+		if (X != 0) {
-+			if ((X & 0x00000200) != 0)
-+				X = X | 0xFFFFFC00;
-+			ele_A = ((X * ele_D) >> 8) & 0x000003FF;
-+
-+			/* new element C = element D x Y */
-+			if ((Y & 0x00000200) != 0)
-+				Y = Y | 0xFFFFFC00;
-+			ele_C = ((Y * ele_D) >> 8) & 0x000003FF;
-+
-+			/* wirte new elements A, C, D to regC80 and regC94, element B is always 0 */
-+			value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
-+			phy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, value32);
-+
-+			value32 = (ele_C & 0x000003C0) >> 6;
-+			phy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, value32);
-+
-+			value32 = ((X * ele_D) >> 7) & 0x01;
-+			phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), value32);
-+		} else {
-+			phy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);
-+			phy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, 0x00);
-+			phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), 0x00);
-+		}
-+
-+		set_CCK_swing_index(priv, CCK_index);
-+
-+		if (rf == 2) {
-+			ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22;
-+			X = priv->pshare->regeb4;
-+			Y = priv->pshare->regebc;
-+
-+			if (X != 0) {
-+				if ((X & 0x00000200) != 0)	/* consider minus */
-+					X = X | 0xFFFFFC00;
-+				ele_A = ((X * ele_D) >> 8) & 0x000003FF;
-+
-+				/* new element C = element D x Y */
-+				if ((Y & 0x00000200) != 0)
-+					Y = Y | 0xFFFFFC00;
-+				ele_C = ((Y * ele_D) >> 8) & 0x00003FF;
-+
-+				/* wirte new elements A, C, D to regC88 and regC9C, element B is always 0 */
-+				value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
-+				phy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, value32);
-+
-+				value32 = (ele_C & 0x000003C0) >> 6;
-+				phy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, value32);
-+
-+				value32 = ((X * ele_D) >> 7) & 0x01;
-+				phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), value32);
-+			} else {
-+				phy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);
-+				phy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, 0x00);
-+				phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), 0x00);
-+			}
-+
-+		}
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc80 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD));
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc88 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD));
-+
-+		if ((delta_IQK > 3) && (!iqk_info->rfk_forbidden)) {
-+			priv->pshare->thermal_value_iqk = thermal_value;
-+#ifdef MP_TEST
-+#endif			if (!(*(dm->mp_mode) && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET))))
-+
-+				halrf_iqk_trigger(dm, false);
-+		}
-+
-+		if ((delta_LCK > 8)  && (!iqk_info->rfk_forbidden)) {
-+			RTL_W8(0x522, 0xff);
-+			reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1);
-+			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1);
-+			phy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1);
-+			delay_ms(1);
-+			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0);
-+			phy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18);
-+			RTL_W8(0x522, 0x0);
-+			priv->pshare->thermal_value_lck = thermal_value;
-+		}
-+	}
-+
-+	/* update thermal meter value */
-+	priv->pshare->thermal_value = thermal_value;
-+	for (i = 0 ; i < rf ; i++)
-+		priv->pshare->OFDM_index[i] = OFDM_index[i];
-+	priv->pshare->CCK_index = CCK_index;
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
-+}
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
-+void
-+odm_txpowertracking_callback_thermal_meter_jaguar_series4(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
-+ 	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
-+	struct rtl8192cd_priv *priv = dm->priv;
-+	struct txpwrtrack_cfg c;
-+
-+	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
-+		return;
-+
-+	u8 thermal_value[MAX_RF_PATH] = {0}, delta[MAX_RF_PATH] = {0};
-+	u8 delta_swing_table_idx_tup[DELTA_SWINGIDX_SIZE] = {0};
-+	u8 delta_swing_table_idx_tdown[DELTA_SWINGIDX_SIZE] = {0};
-+	u8 delta_LCK = 0, delta_IQK = 0, i = 0, j = 0, p;
-+	u8 thermal_value_avg_count[MAX_RF_PATH] = {0};
-+	u32 thermal_value_avg[MAX_RF_PATH] = {0};
-+	s8 thermal_value_temp[MAX_RF_PATH] = {0};
-+
-+	u8 *pwrtrk_tab_up_a = NULL;
-+	u8 *pwrtrk_tab_down_a = NULL;
-+	u8 *pwrtrk_tab_up_b = NULL;
-+	u8 *pwrtrk_tab_down_b = NULL;
-+	u8 *pwrtrk_tab_up_c = NULL;
-+	u8 *pwrtrk_tab_down_c = NULL;
-+	u8 *pwrtrk_tab_up_d = NULL;
-+	u8 *pwrtrk_tab_down_d = NULL;
-+	u8 tracking_method = MIX_MODE;
-+
-+	configure_txpower_track(dm, &c);
-+
-+	(*c.get_delta_swing_table)(dm,
-+		(u8 **)&pwrtrk_tab_up_a, (u8 **)&pwrtrk_tab_down_a,
-+		(u8 **)&pwrtrk_tab_up_b, (u8 **)&pwrtrk_tab_down_b);
-+
-+	if (GET_CHIP_VER(priv) == VERSION_8814B) {
-+		(*c.get_delta_swing_table8814only)(dm,
-+			(u8 **)&pwrtrk_tab_up_c, (u8 **)&pwrtrk_tab_down_c,
-+			(u8 **)&pwrtrk_tab_up_d, (u8 **)&pwrtrk_tab_down_d);
-+	}
-+
-+	cali_info->txpowertracking_callback_cnt++;
-+	cali_info->is_txpowertracking_init = true;
-+
-+	/* Initialize */
-+	if (!dm->rf_calibrate_info.thermal_value)
-+		dm->rf_calibrate_info.thermal_value =
-+			priv->pmib->dot11RFEntry.thermal[RF_PATH_A];
-+
-+	if (!dm->rf_calibrate_info.thermal_value_lck)
-+		dm->rf_calibrate_info.thermal_value_lck =
-+			priv->pmib->dot11RFEntry.thermal[RF_PATH_A];
-+
-+	if (!dm->rf_calibrate_info.thermal_value_iqk)
-+		dm->rf_calibrate_info.thermal_value_iqk =
-+			priv->pmib->dot11RFEntry.thermal[RF_PATH_A];
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
-+		cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base_path[RF_PATH_A], cali_info->default_ofdm_index);
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		"cali_info->txpowertrack_control=%d\n", cali_info->txpowertrack_control);
-+
-+	for (i = 0; i < c.rf_path_count; i++) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			"PGthermal[%d]=0x%x(%d)\n", i, 
-+			priv->pmib->dot11RFEntry.thermal[i],
-+			priv->pmib->dot11RFEntry.thermal[i]);
-+
-+		if (priv->pmib->dot11RFEntry.thermal[i] == 0xff ||
-+			priv->pmib->dot11RFEntry.thermal[i] == 0x0)
-+			return;
-+	}
-+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
-+		for (i = 0; i < c.rf_path_count; i++)
-+			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0x7e); /* 0x42: RF Reg[6:1] Thermal Trim*/
-+	} else if (dm->support_ic_type == ODM_RTL8197G) {
-+		for (i = 0; i < c.rf_path_count; i++)
-+			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, RF_0xf6, 0x7E000);
-+	} else {
-+		for (i = 0; i < c.rf_path_count; i++) {
-+			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
-+
-+			if (dm->support_ic_type == ODM_RTL8814B) {
-+				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_multi_thermal_offset(dm, i);
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + multi_thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_multi_thermal_offset(dm, i));
-+			} else {
-+				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
-+			}
-+
-+			if (thermal_value_temp[i] > 63)
-+				thermal_value[i] = 63;
-+			else if (thermal_value_temp[i] < 0)
-+				thermal_value[i] = 0;
-+			else
-+				thermal_value[i] = thermal_value_temp[i];
-+		}
-+	}
-+
-+	for (j = 0; j < c.rf_path_count; j++) {
-+		cali_info->thermal_value_avg_path[j][cali_info->thermal_value_avg_index_path[j]] = thermal_value[j];
-+		cali_info->thermal_value_avg_index_path[j]++;
-+		if (cali_info->thermal_value_avg_index_path[j] == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
-+			cali_info->thermal_value_avg_index_path[j] = 0;
-+
-+
-+		for (i = 0; i < c.average_thermal_num; i++) {
-+			if (cali_info->thermal_value_avg_path[j][i]) {
-+				thermal_value_avg[j] += cali_info->thermal_value_avg_path[j][i];
-+				thermal_value_avg_count[j]++;
-+			}
-+		}
-+
-+		if (thermal_value_avg_count[j]) {            /* Calculate Average thermal_value after average enough times */
-+			thermal_value[j] = (u8)(thermal_value_avg[j] / thermal_value_avg_count[j]);
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"PGthermal[%d] = 0x%x(%d),   AVG Thermal Meter = 0x%x(%d)\n", j,
-+				priv->pmib->dot11RFEntry.thermal[j],
-+				priv->pmib->dot11RFEntry.thermal[j],
-+				thermal_value[j],
-+				thermal_value[j]);
-+		}
-+		/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
-+
-+		/* "delta" here is used to determine whether thermal value changes or not. */
-+		delta[j] = RTL_ABS(thermal_value[j], priv->pmib->dot11RFEntry.thermal[j]);
-+		delta_LCK = RTL_ABS(thermal_value[RF_PATH_A], dm->rf_calibrate_info.thermal_value_lck);
-+		delta_IQK = RTL_ABS(thermal_value[RF_PATH_A], dm->rf_calibrate_info.thermal_value_iqk);
-+	}
-+
-+	/*4 6. If necessary, do LCK.*/
-+	for (i = 0; i < c.rf_path_count; i++)
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\n", i, delta[i], delta_LCK, delta_IQK);
-+
-+	/* Wait sacn to do LCK by RF Jenyu*/
-+	if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
-+		/* Delta temperature is equal to or larger than 20 centigrade.*/
-+		if (delta_LCK >= c.threshold_iqk) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
-+			cali_info->thermal_value_lck = thermal_value[RF_PATH_A];
-+
-+			/*Use RTLCK, so close power tracking driver LCK*/
-+			if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
-+				if (c.phy_lc_calibrate)
-+					(*c.phy_lc_calibrate)(dm);
-+			} else
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do not do LCK\n");
-+		}
-+	}
-+
-+	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
-+#ifdef _TRACKING_TABLE_FILE
-+	for (i = 0; i < c.rf_path_count; i++) {
-+		if (i == RF_PATH_B) {
-+			odm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_b, DELTA_SWINGIDX_SIZE);
-+			odm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_b, DELTA_SWINGIDX_SIZE);
-+		} else if (i == RF_PATH_C) {
-+			odm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_c, DELTA_SWINGIDX_SIZE);
-+			odm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_c, DELTA_SWINGIDX_SIZE);
-+		} else if (i == RF_PATH_D) {
-+			odm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_d, DELTA_SWINGIDX_SIZE);
-+			odm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_d, DELTA_SWINGIDX_SIZE);
-+		} else {
-+			odm_move_memory(dm, delta_swing_table_idx_tup, pwrtrk_tab_up_a, DELTA_SWINGIDX_SIZE);
-+			odm_move_memory(dm, delta_swing_table_idx_tdown, pwrtrk_tab_down_a, DELTA_SWINGIDX_SIZE);
-+		}
-+
-+		cali_info->delta_power_index_last_path[i] = cali_info->delta_power_index_path[i];	/*recording poer index offset*/
-+		delta[i] = thermal_value[i] > priv->pmib->dot11RFEntry.thermal[i] ? (thermal_value[i] - priv->pmib->dot11RFEntry.thermal[i]) : (priv->pmib->dot11RFEntry.thermal[i] - thermal_value[i]);
-+				
-+		if (delta[i] >= TXPWR_TRACK_TABLE_SIZE)
-+			delta[i] = TXPWR_TRACK_TABLE_SIZE - 1;
-+
-+		if (thermal_value[i] > priv->pmib->dot11RFEntry.thermal[i]) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"delta_swing_table_idx_tup[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tup[delta[i]], i);
-+				
-+			cali_info->delta_power_index_path[i] = delta_swing_table_idx_tup[delta[i]];
-+			cali_info->absolute_ofdm_swing_idx[i] =  delta_swing_table_idx_tup[delta[i]];	    /*Record delta swing for mix mode power tracking*/
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"******Temp is higher and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
-+		} else {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"delta_swing_table_idx_tdown[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tdown[delta[i]], i);
-+			cali_info->delta_power_index_path[i] = -1 * delta_swing_table_idx_tdown[delta[i]];
-+			cali_info->absolute_ofdm_swing_idx[i] = -1 * delta_swing_table_idx_tdown[delta[i]];        /*Record delta swing for mix mode power tracking*/
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"******Temp is lower and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
-+		}
-+	}
-+
-+#endif
-+
-+	for (p = RF_PATH_A; p < c.rf_path_count; p++) {	
-+		if (cali_info->delta_power_index_path[p] == cali_info->delta_power_index_last_path[p])	     /*If Thermal value changes but lookup table value still the same*/
-+			cali_info->power_index_offset_path[p] = 0;
-+		else
-+			cali_info->power_index_offset_path[p] = cali_info->delta_power_index_path[p] - cali_info->delta_power_index_last_path[p];	/*Power index diff between 2 times Power Tracking*/
-+	}
-+
-+#if 0
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+	} else {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
-+	}
-+#else
-+	if (*dm->mp_mode == 1) {
-+		if (cali_info->txpowertrack_control == 1) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
-+			tracking_method = MIX_MODE;
-+		} else if (cali_info->txpowertrack_control == 3) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
-+			tracking_method = TSSI_MODE;
-+		}
-+	} else {
-+		if (dm->priv->pmib->dot11RFEntry.tssi_enable == 0) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
-+			tracking_method = MIX_MODE;
-+		} else if (dm->priv->pmib->dot11RFEntry.tssi_enable == 1) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
-+			tracking_method = TSSI_MODE;
-+		}
-+	}
-+
-+	if (dm->support_ic_type == ODM_RTL8822C || dm->support_ic_type == ODM_RTL8812F ||
-+		dm->support_ic_type == ODM_RTL8814B || dm->support_ic_type == ODM_RTL8197G)
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, tracking_method, p, 0);
-+
-+#endif
-+	/* Wait sacn to do IQK by RF Jenyu*/
-+	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden) && (dm->is_linked || *dm->mp_mode)) {
-+		/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
-+		if (delta_IQK >= c.threshold_iqk) {
-+			cali_info->thermal_value_iqk = thermal_value[RF_PATH_A];
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
-+
-+			/*if (!cali_info->is_iqk_in_progress)*/
-+			/* 	(*c.do_iqk)(dm, delta_IQK, thermal_value[RF_PATH_A], 8);*/
-+			/*RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do IQK\n");*/
-+
-+			/*if (!cali_info->is_iqk_in_progress)*/
-+			/*	(*c.do_tssi_dck)(dm, true);*/
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do TSSI DCK\n");
-+		}
-+	}
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===%s\n", __func__);
-+
-+	cali_info->tx_powercount = 0;
-+}
-+#endif
-+
-+#if (RTL8197F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
-+	RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
-+void
-+odm_txpowertracking_callback_thermal_meter_jaguar_series3(
-+	void		*dm_void
-+)
-+{
-+#if 1
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
-+	u8 thermal_value_avg_count = 0, p = 0, i = 0;
-+	u32 thermal_value_avg = 0;
-+	struct rtl8192cd_priv *priv = dm->priv;
-+	struct txpwrtrack_cfg c;
-+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	/*The following tables decide the final index of OFDM/CCK swing table.*/
-+	u8 *pwrtrk_tab_up_a = NULL, *pwrtrk_tab_down_a = NULL;
-+	u8 *pwrtrk_tab_up_b = NULL, *pwrtrk_tab_down_b = NULL;
-+	u8 *pwrtrk_tab_up_cck_a = NULL, *pwrtrk_tab_down_cck_a = NULL;
-+	u8 *pwrtrk_tab_up_cck_b = NULL, *pwrtrk_tab_down_cck_b = NULL;
-+	/*for 8814 add by Yu Chen*/
-+	u8 *pwrtrk_tab_up_c = NULL, *pwrtrk_tab_down_c = NULL;
-+	u8 *pwrtrk_tab_up_d = NULL, *pwrtrk_tab_down_d = NULL;
-+	u8 *pwrtrk_tab_up_cck_c = NULL, *pwrtrk_tab_down_cck_c = NULL;
-+	u8 *pwrtrk_tab_up_cck_d = NULL, *pwrtrk_tab_down_cck_d = NULL;
-+	s8 thermal_value_temp = 0;
-+
-+#ifdef MP_TEST
-+	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
-+		channel = priv->pshare->working_channel;
-+		if (priv->pshare->mp_txpwr_tracking == false)
-+			return;
-+	} else
-+#endif
-+	{
-+		channel = (priv->pmib->dot11RFEntry.dot11channel);
-+	}
-+
-+	configure_txpower_track(dm, &c);
-+
-+	(*c.get_delta_all_swing_table)(dm,
-+		(u8 **)&pwrtrk_tab_up_a, (u8 **)&pwrtrk_tab_down_a,
-+		(u8 **)&pwrtrk_tab_up_b, (u8 **)&pwrtrk_tab_down_b,
-+		(u8 **)&pwrtrk_tab_up_cck_a, (u8 **)&pwrtrk_tab_down_cck_a,
-+		(u8 **)&pwrtrk_tab_up_cck_b, (u8 **)&pwrtrk_tab_down_cck_b);
-+
-+	if (GET_CHIP_VER(priv) == VERSION_8198F) {
-+		(*c.get_delta_all_swing_table_ex)(dm,
-+			(u8 **)&pwrtrk_tab_up_c, (u8 **)&pwrtrk_tab_down_c,
-+			(u8 **)&pwrtrk_tab_up_d, (u8 **)&pwrtrk_tab_down_d,
-+			(u8 **)&pwrtrk_tab_up_cck_c, (u8 **)&pwrtrk_tab_down_cck_c,
-+			(u8 **)&pwrtrk_tab_up_cck_d, (u8 **)&pwrtrk_tab_down_cck_d);
-+	}
-+	/*0x42: RF Reg[15:10] 88E*/
-+	thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);
-+#ifdef THER_TRIM
-+	if (GET_CHIP_VER(priv) == VERSION_8197F) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"orig thermal_value=%d, ther_trim_val=%d\n", thermal_value, priv->pshare->rf_ft_var.ther_trim_val);
-+
-+		thermal_value += priv->pshare->rf_ft_var.ther_trim_val;
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"after thermal trim, thermal_value=%d\n", thermal_value);
-+	}
-+
-+	if (GET_CHIP_VER(priv) == VERSION_8198F) {
-+		thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "thermal_value_temp(%d) = ther_value(%d) + ther_trim_ther(%d)\n",
-+		       thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
-+
-+		if (thermal_value_temp > 63)
-+			thermal_value = 63;
-+		else if (thermal_value_temp < 0)
-+			thermal_value = 0;
-+		else
-+			thermal_value = thermal_value_temp;
-+	}
-+#endif
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\n\n\nCurrent Thermal = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n"
-+		, thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);
-+
-+	/* Initialize */
-+	if (!dm->rf_calibrate_info.thermal_value)
-+		dm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther;
-+
-+	if (!dm->rf_calibrate_info.thermal_value_lck)
-+		dm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther;
-+
-+	if (!dm->rf_calibrate_info.thermal_value_iqk)
-+		dm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther;
-+
-+	/* calculate average thermal meter */
-+	dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
-+	dm->rf_calibrate_info.thermal_value_avg_index++;
-+
-+	if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
-+		dm->rf_calibrate_info.thermal_value_avg_index = 0;
-+
-+	for (i = 0; i < c.average_thermal_num; i++) {
-+		if (dm->rf_calibrate_info.thermal_value_avg[i]) {
-+			thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];
-+			thermal_value_avg_count++;
-+		}
-+	}
-+
-+	if (thermal_value_avg_count) {/*Calculate Average thermal_value after average enough times*/
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"thermal_value_avg=0x%x(%d)  thermal_value_avg_count = %d\n"
-+			, thermal_value_avg, thermal_value_avg, thermal_value_avg_count);
-+
-+		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);
-+	}
-+
-+	/*4 Calculate delta, delta_LCK, delta_IQK.*/
-+	delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
-+	delta_LCK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_lck);
-+	delta_IQK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_iqk);
-+	is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1);
-+
-+	if (delta > 29) { /* power track table index(thermal diff.) upper bound*/
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta(%d) > 29, set delta to 29\n", delta);
-+		delta = 29;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
-+
-+	/*4 if necessary, do LCK.*/
-+	if ((delta_LCK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
-+		dm->rf_calibrate_info.thermal_value_lck = thermal_value;
-+#if (RTL8822B_SUPPORT != 1)
-+		if (!(dm->support_ic_type & ODM_RTL8822B)) {
-+			if (c.phy_lc_calibrate)
-+				(*c.phy_lc_calibrate)(dm);
-+		}
-+#endif
-+	}
-+
-+	if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
-+		return;
-+
-+	/*4 Do Power Tracking*/
-+
-+	if (thermal_value != dm->rf_calibrate_info.thermal_value) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******** START POWER TRACKING ********\n");
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n",
-+		       thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
-+
-+#ifdef _TRACKING_TABLE_FILE
-+		if (priv->pshare->rf_ft_var.pwr_track_file) {
-+			if (is_increase) { /*thermal is higher than base*/
-+				for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+					switch (p) {
-+					case RF_PATH_B:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_b[%d] = %d pwrtrk_tab_up_cck_b[%d] = %d\n", delta, pwrtrk_tab_up_b[delta], delta, pwrtrk_tab_up_cck_b[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_b[delta];
-+						cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_b[delta];
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
-+						break;
-+
-+					case RF_PATH_C:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_c[%d] = %d pwrtrk_tab_up_cck_c[%d] = %d\n", delta, pwrtrk_tab_up_c[delta], delta, pwrtrk_tab_up_cck_c[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_c[delta];
-+						cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_c[delta];
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
-+						break;
-+
-+					case RF_PATH_D:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_d[%d] = %d pwrtrk_tab_up_cck_d[%d] = %d\n", delta, pwrtrk_tab_up_d[delta], delta, pwrtrk_tab_up_cck_d[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_d[delta];
-+						cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_d[delta];
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
-+						break;
-+					default:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_a[%d] = %d pwrtrk_tab_up_cck_a[%d] = %d\n", delta, pwrtrk_tab_up_a[delta], delta, pwrtrk_tab_up_cck_a[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_a[delta];
-+						cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_a[delta];
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
-+						break;
-+					}
-+				}
-+			} else { /* thermal is lower than base*/
-+				for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+					switch (p) {
-+					case RF_PATH_B:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_b[%d] = %d   pwrtrk_tab_down_cck_b[%d] = %d\n", delta, pwrtrk_tab_down_b[delta], delta, pwrtrk_tab_down_cck_b[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_b[delta];
-+						cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_b[delta];
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d   pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
-+						break;
-+
-+					case RF_PATH_C:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_c[%d] = %d   pwrtrk_tab_down_cck_c[%d] = %d\n", delta, pwrtrk_tab_down_c[delta], delta, pwrtrk_tab_down_cck_c[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_c[delta];
-+						cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_c[delta];
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d   pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
-+						break;
-+
-+					case RF_PATH_D:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_d[%d] = %d   pwrtrk_tab_down_cck_d[%d] = %d\n", delta, pwrtrk_tab_down_d[delta], delta, pwrtrk_tab_down_cck_d[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_d[delta];
-+						cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_d[delta];
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d   pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
-+						break;
-+
-+					default:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_a[%d] = %d   pwrtrk_tab_down_cck_a[%d] = %d\n", delta, pwrtrk_tab_down_a[delta], delta, pwrtrk_tab_down_cck_a[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_a[delta];
-+						cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_a[delta];
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d   pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
-+						break;
-+					}
-+				}
-+			}
-+
-+			if (is_increase) {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power --->\n");
-+				if (GET_CHIP_VER(priv) == VERSION_8197F) {
-+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+						(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
-+				} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
-+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+				} else if (GET_CHIP_VER(priv) == VERSION_8822B) {
-+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+				} else if (GET_CHIP_VER(priv) == VERSION_8821C) {
-+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+				}  else if (GET_CHIP_VER(priv) == VERSION_8198F) {
-+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+				} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
-+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+				}
-+			} else {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power --->\n");
-+				if (GET_CHIP_VER(priv) == VERSION_8197F) {
-+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+						(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
-+				} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
-+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+				} else if (GET_CHIP_VER(priv) == VERSION_8822B) {
-+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+				} else if (GET_CHIP_VER(priv) == VERSION_8821C) {
-+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+				} else if (GET_CHIP_VER(priv) == VERSION_8198F) {
-+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+				} else if (GET_CHIP_VER(priv) == VERSION_8192F) {
-+					for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+						(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+				}
-+			}
-+		}
-+#endif
-+
-+		if (GET_CHIP_VER(priv) != VERSION_8198F) {
-+			if ((delta_IQK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden) && dm->is_linked) {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
-+				dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
-+				if (!(dm->support_ic_type & ODM_RTL8197F)) {
-+					if (c.do_iqk)
-+						(*c.do_iqk)(dm, false, thermal_value, 0);
-+				}
-+			}
-+		}
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n\n", __func__);
-+		/*update thermal meter value*/
-+		dm->rf_calibrate_info.thermal_value =  thermal_value;
-+
-+	}
-+
-+#endif
-+}
-+#endif
-+
-+/*#if (RTL8814A_SUPPORT == 1)*/
-+#if (RTL8814A_SUPPORT == 1)
-+
-+void
-+odm_txpowertracking_callback_thermal_meter_jaguar_series2(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	u8			thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
-+	u8			thermal_value_avg_count = 0, p = 0, i = 0;
-+	u32			thermal_value_avg = 0, reg0x18;
-+	u32			bb_swing_reg[4] = {REG_A_TX_SCALE_JAGUAR, REG_B_TX_SCALE_JAGUAR, REG_C_TX_SCALE_JAGUAR2, REG_D_TX_SCALE_JAGUAR2};
-+	s32			ele_D;
-+	u32			bb_swing_idx;
-+	struct rtl8192cd_priv	*priv = dm->priv;
-+	struct txpwrtrack_cfg	c;
-+	boolean			is_tssi_enable = false;
-+	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
-+	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
-+
-+	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
-+	u8			*delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL;
-+	u8			*delta_swing_table_idx_tup_b = NULL, *delta_swing_table_idx_tdown_b = NULL;
-+	/* for 8814 add by Yu Chen */
-+	u8			*delta_swing_table_idx_tup_c = NULL, *delta_swing_table_idx_tdown_c = NULL;
-+	u8			*delta_swing_table_idx_tup_d = NULL, *delta_swing_table_idx_tdown_d = NULL;
-+
-+#ifdef MP_TEST
-+	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
-+		channel = priv->pshare->working_channel;
-+		if (priv->pshare->mp_txpwr_tracking == false)
-+			return;
-+	} else
-+#endif
-+	{
-+		channel = (priv->pmib->dot11RFEntry.dot11channel);
-+	}
-+
-+	configure_txpower_track(dm, &c);
-+	cali_info->default_ofdm_index = priv->pshare->OFDM_index0[RF_PATH_A];
-+
-+	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
-+		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
-+
-+	if (dm->support_ic_type & ODM_RTL8814A)	/* for 8814 path C & D */
-+		(*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
-+			(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
-+
-+	thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
-+
-+	/* Initialize */
-+	if (!dm->rf_calibrate_info.thermal_value)
-+		dm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther;
-+
-+	if (!dm->rf_calibrate_info.thermal_value_lck)
-+		dm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther;
-+
-+	if (!dm->rf_calibrate_info.thermal_value_iqk)
-+		dm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther;
-+
-+	is_tssi_enable = (boolean)odm_get_rf_reg(dm, RF_PATH_A, REG_RF_TX_GAIN_OFFSET, BIT(7));	/* check TSSI enable */
-+
-+	/* 4 Query OFDM BB swing default setting 	Bit[31:21] */
-+	for (p = RF_PATH_A ; p < c.rf_path_count ; p++) {
-+		ele_D = odm_get_bb_reg(dm, bb_swing_reg[p], 0xffe00000);
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[p], odm_get_bb_reg(dm, bb_swing_reg[p], MASKDWORD), ele_D);
-+
-+		for (bb_swing_idx = 0; bb_swing_idx < TXSCALE_TABLE_SIZE; bb_swing_idx++) {/* 4 */
-+			if (ele_D == tx_scaling_table_jaguar[bb_swing_idx]) {
-+				dm->rf_calibrate_info.OFDM_index[p] = (u8)bb_swing_idx;
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"OFDM_index[%d]=%d\n", p, dm->rf_calibrate_info.OFDM_index[p]);
-+				break;
-+			}
-+		}
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "kfree_offset[%d]=%d\n", p, cali_info->kfree_offset[p]);
-+
-+	}
-+
-+	/* calculate average thermal meter */
-+	dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
-+	dm->rf_calibrate_info.thermal_value_avg_index++;
-+	if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)  /* Average times =  c.average_thermal_num */
-+		dm->rf_calibrate_info.thermal_value_avg_index = 0;
-+
-+	for (i = 0; i < c.average_thermal_num; i++) {
-+		if (dm->rf_calibrate_info.thermal_value_avg[i]) {
-+			thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];
-+			thermal_value_avg_count++;
-+		}
-+	}
-+
-+	if (thermal_value_avg_count) {            /* Calculate Average thermal_value after average enough times */
-+		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", thermal_value, priv->pmib->dot11RFEntry.ther);
-+	}
-+
-+	/* 4 Calculate delta, delta_LCK, delta_IQK. */
-+	delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
-+	delta_LCK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_lck);
-+	delta_IQK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_iqk);
-+	is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1);
-+
-+	/* 4 if necessary, do LCK. */
-+	if (!(dm->support_ic_type & ODM_RTL8821)) {
-+		if ((delta_LCK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
-+			dm->rf_calibrate_info.thermal_value_lck = thermal_value;
-+
-+			/*Use RTLCK, so close power tracking driver LCK*/
-+#if (RTL8814A_SUPPORT != 1)
-+			if (!(dm->support_ic_type & ODM_RTL8814A)) {
-+				if (c.phy_lc_calibrate)
-+					(*c.phy_lc_calibrate)(dm);
-+			}
-+#endif
-+		}
-+	}
-+
-+	if ((delta_IQK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
-+		panic_printk("%s(%d)\n", __FUNCTION__, __LINE__);
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
-+		dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
-+		if (c.do_iqk)
-+			(*c.do_iqk)(dm, true, 0, 0);
-+	}
-+
-+	if (!priv->pmib->dot11RFEntry.ther)	/*Don't do power tracking since no calibrated thermal value*/
-+		return;
-+
-+	/* 4 Do Power Tracking */
-+
-+	if (is_tssi_enable == true) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter PURE TSSI MODE**********\n");
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
-+	} else if (thermal_value != dm->rf_calibrate_info.thermal_value) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\n******** START POWER TRACKING ********\n");
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
-+
-+#ifdef _TRACKING_TABLE_FILE
-+		if (priv->pshare->rf_ft_var.pwr_track_file) {
-+			if (is_increase) {		/* thermal is higher than base */
-+				for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+					switch (p) {
-+					case RF_PATH_B:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta];       /* Record delta swing for mix mode power tracking */
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+						break;
-+
-+					case RF_PATH_C:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta];       /* Record delta swing for mix mode power tracking */
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+						break;
-+
-+					case RF_PATH_D:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta];       /* Record delta swing for mix mode power tracking */
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+						break;
-+
-+					default:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta];        /* Record delta swing for mix mode power tracking */
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+						break;
-+					}
-+				}
-+			} else {				/* thermal is lower than base */
-+				for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+					switch (p) {
-+					case RF_PATH_B:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta];        /* Record delta swing for mix mode power tracking */
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+						break;
-+
-+					case RF_PATH_C:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta];        /* Record delta swing for mix mode power tracking */
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+						break;
-+
-+					case RF_PATH_D:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta];        /* Record delta swing for mix mode power tracking */
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+						break;
-+
-+					default:
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
-+						cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta];        /* Record delta swing for mix mode power tracking */
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+						break;
-+					}
-+				}
-+			}
-+
-+			if (is_increase) {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power --->\n");
-+				for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+					(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+			} else {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power --->\n");
-+				for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+					(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+			}
-+		}
-+#endif
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
-+		/* update thermal meter value */
-+		dm->rf_calibrate_info.thermal_value =  thermal_value;
-+
-+	}
-+}
-+#endif
-+
-+#if (RTL8812A_SUPPORT == 1 || RTL8881A_SUPPORT == 1)
-+void
-+odm_txpowertracking_callback_thermal_meter_jaguar_series(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	unsigned char			thermal_value = 0, delta, delta_LCK, channel, is_decrease;
-+	unsigned char			thermal_value_avg_count = 0;
-+	unsigned int			thermal_value_avg = 0, reg0x18;
-+	unsigned int			bb_swing_reg[4] = {0xc1c, 0xe1c, 0x181c, 0x1a1c};
-+	int					ele_D, value32;
-+	char					OFDM_index[2], index;
-+	unsigned int			i = 0, j = 0, rf_path, max_rf_path = 2, rf;
-+	struct rtl8192cd_priv		*priv = dm->priv;
-+	unsigned char			OFDM_min_index = 7; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur and Mimic */
-+	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
-+
-+
-+#ifdef MP_TEST
-+	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
-+		channel = priv->pshare->working_channel;
-+		if (priv->pshare->mp_txpwr_tracking == false)
-+			return;
-+	} else
-+#endif
-+	{
-+		channel = (priv->pmib->dot11RFEntry.dot11channel);
-+	}
-+
-+#if RTL8881A_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8881A) {
-+		max_rf_path = 1;
-+		if ((get_bonding_type_8881A() == BOND_8881AM || get_bonding_type_8881A() == BOND_8881AN)
-+		    && priv->pshare->rf_ft_var.use_intpa8881A && (*dm->band_type == ODM_BAND_2_4G))
-+			OFDM_min_index = 6;		/* intPA - upper bond set to +3 dB (base: -2 dB)ot11RFEntry.phy_band_select == PHY_BAND_2G)) */
-+		else
-+			OFDM_min_index = 10;		/* OFDM BB Swing should be less than +1dB, which is required by Arthur and Mimic */
-+	}
-+#endif
-+
-+
-+	thermal_value = (unsigned char)phy_query_rf_reg(priv, RF_PATH_A, 0x42, 0xfc00, 1); /* 0x42: RF Reg[15:10] 88E */
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
-+
-+
-+	/* 4 Query OFDM BB swing default setting 	Bit[31:21] */
-+	for (rf_path = 0 ; rf_path < max_rf_path ; rf_path++) {
-+		ele_D = phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000);
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], MASKDWORD), ele_D);
-+		for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */
-+			if (ele_D == ofdm_swing_table_8812[i]) {
-+				OFDM_index[rf_path] = (unsigned char)i;
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[%d]=%d\n", rf_path, OFDM_index[rf_path]);
-+				break;
-+			}
-+		}
-+	}
-+#if 0
-+	/* Query OFDM path A default setting 	Bit[31:21] */
-+	ele_D = phy_query_bb_reg(priv, 0xc1c, 0xffe00000);
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc1c:0x%x ([31:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xc1c, MASKDWORD), ele_D);
-+	for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */
-+		if (ele_D == ofdm_swing_table_8812[i]) {
-+			OFDM_index[0] = (unsigned char)i;
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[0]=%d\n", OFDM_index[0]);
-+			break;
-+		}
-+	}
-+	/* Query OFDM path B default setting */
-+	if (rf == 2) {
-+		ele_D = phy_query_bb_reg(priv, 0xe1c, 0xffe00000);
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xe1c:0x%x ([32:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xe1c, MASKDWORD), ele_D);
-+		for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {
-+			if (ele_D == ofdm_swing_table_8812[i]) {
-+				OFDM_index[1] = (unsigned char)i;
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[1]=%d\n", OFDM_index[1]);
-+				break;
-+			}
-+		}
-+	}
-+#endif
-+	/* Initialize */
-+	if (!priv->pshare->thermal_value) {
-+		priv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther;
-+		priv->pshare->thermal_value_lck = thermal_value;
-+	}
-+
-+	/* calculate average thermal meter */
-+	{
-+		priv->pshare->thermal_value_avg_8812[priv->pshare->thermal_value_avg_index_8812] = thermal_value;
-+		priv->pshare->thermal_value_avg_index_8812++;
-+		if (priv->pshare->thermal_value_avg_index_8812 == AVG_THERMAL_NUM_8812)
-+			priv->pshare->thermal_value_avg_index_8812 = 0;
-+
-+		for (i = 0; i < AVG_THERMAL_NUM_8812; i++) {
-+			if (priv->pshare->thermal_value_avg_8812[i]) {
-+				thermal_value_avg += priv->pshare->thermal_value_avg_8812[i];
-+				thermal_value_avg_count++;
-+			}
-+		}
-+
-+		if (thermal_value_avg_count) {
-+			thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count);
-+			/* printk("AVG Thermal Meter = 0x%x\n", thermal_value); */
-+		}
-+	}
-+
-+
-+	/* 4 If necessary,  do power tracking */
-+
-+	if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
-+		return;
-+
-+	if (thermal_value != priv->pshare->thermal_value) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
-+		delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
-+		delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck);
-+		is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0);
-+		/* if (*dm->band_type == ODM_BAND_5G) */
-+		{
-+#ifdef _TRACKING_TABLE_FILE
-+			if (priv->pshare->rf_ft_var.pwr_track_file) {
-+				for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
-+					if (is_decrease) {
-+						OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);
-+						OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]);
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
-+#if 0/* RTL8881A_SUPPORT */
-+						if (dm->support_ic_type == ODM_RTL8881A) {
-+							if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) {
-+								if (priv->pshare->add_tx_agc) { /* tx_agc has been added */
-+									add_tx_power88xx_ac(priv, 0);
-+									priv->pshare->add_tx_agc = 0;
-+									priv->pshare->add_tx_agc_index = 0;
-+								}
-+							}
-+						}
-+#endif
-+					} else {
-+
-+						OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] - get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);
-+#if 0/* RTL8881A_SUPPORT */
-+						if (dm->support_ic_type == ODM_RTL8881A) {
-+							if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) {
-+								if (OFDM_index[i] < OFDM_min_index) {
-+									priv->pshare->add_tx_agc_index = (OFDM_min_index - OFDM_index[i]) / 2; /* Calculate Remnant tx_agc value,  2 index for 1 tx_agc */
-+									add_tx_power88xx_ac(priv, priv->pshare->add_tx_agc_index);
-+									priv->pshare->add_tx_agc = 1;     /* add_tx_agc Flag = 1 */
-+									OFDM_index[i] = OFDM_min_index;
-+								} else {
-+									if (priv->pshare->add_tx_agc) { /* tx_agc been added */
-+										priv->pshare->add_tx_agc = 0;
-+										priv->pshare->add_tx_agc_index = 0;
-+										add_tx_power88xx_ac(priv, 0); /* minus the added TPI */
-+									}
-+								}
-+							}
-+						}
-+#else
-+						OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ?  OFDM_min_index : OFDM_index[rf_path]);
-+#endif
-+						RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
-+					}
-+				}
-+			}
-+#endif
-+			/* 4 Set new BB swing index */
-+			for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
-+				phy_set_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000, ofdm_swing_table_8812[(unsigned int)OFDM_index[rf_path]]);
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000), OFDM_index[rf_path]);
-+			}
-+
-+		}
-+		if ((delta_LCK > 8) && (!iqk_info->rfk_forbidden)) {
-+			RTL_W8(0x522, 0xff);
-+			reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1);
-+			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1);
-+			phy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1);
-+			delay_ms(200); /* frequency deviation */
-+			phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0);
-+			phy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18);
-+#ifdef CONFIG_RTL_8812_SUPPORT
-+			if (GET_CHIP_VER(priv) == VERSION_8812E)
-+				update_bbrf_val8812(priv, priv->pmib->dot11RFEntry.dot11channel);
-+#endif
-+			RTL_W8(0x522, 0x0);
-+			priv->pshare->thermal_value_lck = thermal_value;
-+		}
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
-+
-+		/* update thermal meter value */
-+		priv->pshare->thermal_value = thermal_value;
-+		for (rf_path = 0; rf_path < max_rf_path; rf_path++)
-+			priv->pshare->OFDM_index[rf_path] = OFDM_index[rf_path];
-+	}
-+}
-+
-+#endif
-+
-+
-+void
-+odm_txpowertracking_callback_thermal_meter(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
-+	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
-+
-+	
-+#if (RTL8814B_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
-+	if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8822C | ODM_RTL8197G)) {
-+		odm_txpowertracking_callback_thermal_meter_jaguar_series4(dm);
-+		return;
-+	}
-+#endif
-+#if (RTL8197F_SUPPORT == 1 ||RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8197F || dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8822B
-+		|| dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8198F) {
-+		odm_txpowertracking_callback_thermal_meter_jaguar_series3(dm);
-+		return;
-+	}
-+#endif
-+#if (RTL8814A_SUPPORT == 1)		/*use this function to do power tracking after 8814 by YuChen*/
-+	if (dm->support_ic_type & ODM_RTL8814A) {
-+		odm_txpowertracking_callback_thermal_meter_jaguar_series2(dm);
-+		return;
-+	}
-+#endif
-+#if (RTL8881A_SUPPORT || RTL8812A_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8812 || dm->support_ic_type & ODM_RTL8881A) {
-+		odm_txpowertracking_callback_thermal_meter_jaguar_series(dm);
-+		return;
-+	}
-+#endif
-+
-+#if (RTL8192E_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8192E) {
-+		odm_txpowertracking_callback_thermal_meter_92e(dm);
-+		return;
-+	}
-+#endif
-+
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	/* PMGNT_INFO      		mgnt_info = &adapter->mgnt_info; */
-+#endif
-+
-+
-+	u8			thermal_value = 0, delta, delta_LCK, delta_IQK, offset;
-+	u8			thermal_value_avg_count = 0;
-+	u32			thermal_value_avg = 0;
-+	/*	s32			ele_A=0, ele_D, TempCCk, X, value32;
-+	 *	s32			Y, ele_C=0;
-+	 *	s8			OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index;
-+	 *	s8			deltaPowerIndex = 0; */
-+	u32			i = 0;/* , j = 0; */
-+	boolean		is2T = false;
-+	/*	bool 		bInteralPA = false; */
-+
-+	u8			OFDM_max_index = 34, rf = (is2T) ? 2 : 1; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
-+	u8			indexforchannel = 0;/*get_right_chnl_place_for_iqk(hal_data->current_channel)*/
-+	enum            _POWER_DEC_INC { POWER_DEC, POWER_INC };
-+
-+	struct txpwrtrack_cfg	c;
-+
-+
-+	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
-+	s8			delta_swing_table_idx[2][index_mapping_NUM_88E] = {
-+		/* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */
-+		{0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11}, {0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 7, 8, 9, 9, 10}
-+	};
-+	u8			thermal_threshold[2][index_mapping_NUM_88E] = {
-+		/* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */
-+		{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27}, {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25}
-+	};
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	struct rtl8192cd_priv	*priv = dm->priv;
-+#endif
-+
-+	/* 4 2. Initilization ( 7 steps in total ) */
-+
-+	configure_txpower_track(dm, &c);
-+
-+	dm->rf_calibrate_info.txpowertracking_callback_cnt++; /* cosa add for debug */
-+	dm->rf_calibrate_info.is_txpowertracking_init = true;
-+
-+#if (MP_DRIVER == 1)
-+	dm->rf_calibrate_info.txpowertrack_control = hal_data->txpowertrack_control; /* <Kordan> We should keep updating the control variable according to HalData.
-+     * <Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
-+	dm->rf_calibrate_info.rega24 = 0x090e1317;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(MP_TEST)
-+	if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
-+		if (dm->priv->pshare->mp_txpwr_tracking == false)
-+			return;
-+	}
-+#endif
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>odm_txpowertracking_callback_thermal_meter_8188e, dm->bb_swing_idx_cck_base: %d, dm->bb_swing_idx_ofdm_base: %d\n", cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base);
-+	/*
-+		if (!dm->rf_calibrate_info.tm_trigger) {
-+			odm_set_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, BIT(17) | BIT(16), 0x3);
-+			dm->rf_calibrate_info.tm_trigger = 1;
-+			return;
-+		}
-+	*/
-+	thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	if (!thermal_value || !dm->rf_calibrate_info.txpowertrack_control)
-+#else
-+	if (!dm->rf_calibrate_info.txpowertrack_control)
-+#endif
-+		return;
-+
-+	/* 4 3. Initialize ThermalValues of rf_calibrate_info */
-+
-+	if (!dm->rf_calibrate_info.thermal_value) {
-+		dm->rf_calibrate_info.thermal_value_lck = thermal_value;
-+		dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
-+	}
-+
-+	if (dm->rf_calibrate_info.is_reloadtxpowerindex)
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
-+
-+	/* 4 4. Calculate average thermal meter */
-+
-+	dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
-+	dm->rf_calibrate_info.thermal_value_avg_index++;
-+	if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)
-+		dm->rf_calibrate_info.thermal_value_avg_index = 0;
-+
-+	for (i = 0; i < c.average_thermal_num; i++) {
-+		if (dm->rf_calibrate_info.thermal_value_avg[i]) {
-+			thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];
-+			thermal_value_avg_count++;
-+		}
-+	}
-+
-+	if (thermal_value_avg_count) {
-+		/* Give the new thermo value a weighting */
-+		thermal_value_avg += (thermal_value * 4);
-+
-+		thermal_value = (u8)(thermal_value_avg / (thermal_value_avg_count + 4));
-+		cali_info->thermal_value_delta = thermal_value - priv->pmib->dot11RFEntry.ther;
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
-+	}
-+
-+	/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
-+
-+	delta	  = (thermal_value > dm->rf_calibrate_info.thermal_value) ? (thermal_value - dm->rf_calibrate_info.thermal_value) : (dm->rf_calibrate_info.thermal_value - thermal_value);
-+	delta_LCK = (thermal_value > dm->rf_calibrate_info.thermal_value_lck) ? (thermal_value - dm->rf_calibrate_info.thermal_value_lck) : (dm->rf_calibrate_info.thermal_value_lck - thermal_value);
-+	delta_IQK = (thermal_value > dm->rf_calibrate_info.thermal_value_iqk) ? (thermal_value - dm->rf_calibrate_info.thermal_value_iqk) : (dm->rf_calibrate_info.thermal_value_iqk - thermal_value);
-+
-+	/* 4 6. If necessary, do LCK. */
-+	if (!(dm->support_ic_type & ODM_RTL8821)) {
-+		/*if((delta_LCK > hal_data->delta_lck) && (hal_data->delta_lck != 0))*/
-+		if ((delta_LCK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
-+			/*Delta temperature is equal to or larger than 20 centigrade.*/
-+			dm->rf_calibrate_info.thermal_value_lck = thermal_value;
-+			(*c.phy_lc_calibrate)(dm);
-+		}
-+	}
-+
-+	/* 3 7. If necessary, move the index of swing table to adjust Tx power. */
-+
-+	if (delta > 0 && dm->rf_calibrate_info.txpowertrack_control) {
-+
-+		delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value);
-+
-+		/* 4 7.1 The Final Power index = BaseIndex + power_index_offset */
-+
-+		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
-+			CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta);
-+			dm->rf_calibrate_info.delta_power_index_last = dm->rf_calibrate_info.delta_power_index;
-+			dm->rf_calibrate_info.delta_power_index =  delta_swing_table_idx[POWER_INC][offset];
-+
-+		} else {
-+
-+			CALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta);
-+			dm->rf_calibrate_info.delta_power_index_last = dm->rf_calibrate_info.delta_power_index;
-+			dm->rf_calibrate_info.delta_power_index = (-1) * delta_swing_table_idx[POWER_DEC][offset];
-+		}
-+
-+		if (dm->rf_calibrate_info.delta_power_index == dm->rf_calibrate_info.delta_power_index_last)
-+			dm->rf_calibrate_info.power_index_offset = 0;
-+		else
-+			dm->rf_calibrate_info.power_index_offset = dm->rf_calibrate_info.delta_power_index - dm->rf_calibrate_info.delta_power_index_last;
-+
-+		for (i = 0; i < rf; i++)
-+			dm->rf_calibrate_info.OFDM_index[i] = cali_info->bb_swing_idx_ofdm_base + dm->rf_calibrate_info.power_index_offset;
-+		dm->rf_calibrate_info.CCK_index = cali_info->bb_swing_idx_cck_base + dm->rf_calibrate_info.power_index_offset;
-+
-+		cali_info->bb_swing_idx_cck = dm->rf_calibrate_info.CCK_index;
-+		cali_info->bb_swing_idx_ofdm[RF_PATH_A] = dm->rf_calibrate_info.OFDM_index[RF_PATH_A];
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, dm->rf_calibrate_info.power_index_offset);
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "The 'OFDM' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base, dm->rf_calibrate_info.power_index_offset);
-+
-+		/* 4 7.1 Handle boundary conditions of index. */
-+
-+
-+		for (i = 0; i < rf; i++) {
-+			if (dm->rf_calibrate_info.OFDM_index[i] > OFDM_max_index)
-+				dm->rf_calibrate_info.OFDM_index[i] = OFDM_max_index;
-+			else if (dm->rf_calibrate_info.OFDM_index[i] < 0)
-+				dm->rf_calibrate_info.OFDM_index[i] = 0;
-+		}
-+
-+		if (dm->rf_calibrate_info.CCK_index > c.swing_table_size_cck - 1)
-+			dm->rf_calibrate_info.CCK_index = c.swing_table_size_cck - 1;
-+		else if (dm->rf_calibrate_info.CCK_index < 0)
-+			dm->rf_calibrate_info.CCK_index = 0;
-+	} else {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"The thermal meter is unchanged or TxPowerTracking OFF: thermal_value: %d, dm->rf_calibrate_info.thermal_value: %d)\n", thermal_value, dm->rf_calibrate_info.thermal_value);
-+		dm->rf_calibrate_info.power_index_offset = 0;
-+	}
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.CCK_index, cali_info->bb_swing_idx_cck_base);
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.OFDM_index[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base);
-+
-+	if (dm->rf_calibrate_info.power_index_offset != 0 && dm->rf_calibrate_info.txpowertrack_control) {
-+		/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
-+
-+		dm->rf_calibrate_info.is_tx_power_changed = true; /* Always true after Tx Power is adjusted by power tracking. */
-+		/*  */
-+		/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
-+		/* to increase TX power. Otherwise, EVM will be bad. */
-+		/*  */
-+		/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
-+		if (thermal_value > dm->rf_calibrate_info.thermal_value) {
-+			/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK, */
-+			/*	"Temperature Increasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */
-+			/*	dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */
-+		} else if (thermal_value < dm->rf_calibrate_info.thermal_value) { /* Low temperature */
-+			/* RF_DBG(dm,DBG_RF_TX_PWR_TRACK, */
-+			/*	"Temperature Decreasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */
-+			/*		dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */
-+		}
-+		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
-+		{
-+			/*				RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"Temperature(%d) hugher than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, TXAGC, 0, 0);
-+		} else {
-+			/*			RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"Temperature(%d) lower than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_A, indexforchannel);
-+			if (is2T)
-+				(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_B, indexforchannel);
-+		}
-+
-+		cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;
-+		cali_info->bb_swing_idx_ofdm_base = cali_info->bb_swing_idx_ofdm[RF_PATH_A];
-+		dm->rf_calibrate_info.thermal_value = thermal_value;
-+
-+	}
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n");
-+
-+	dm->rf_calibrate_info.tx_powercount = 0;
-+}
-+
-+/* 3============================================================
-+ * 3 IQ Calibration
-+ * 3============================================================ */
-+
-+void
-+odm_reset_iqk_result(
-+	void		*dm_void
-+)
-+{
-+	return;
-+}
-+#if 1/* !(DM_ODM_SUPPORT_TYPE & ODM_AP) */
-+u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
-+{
-+	u8	channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
-+		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
-+	};
-+	u8	place = chnl;
-+
-+
-+	if (chnl > 14) {
-+		for (place = 14; place < sizeof(channel_all); place++) {
-+			if (channel_all[place] == chnl)
-+				return place - 13;
-+		}
-+	}
-+	return 0;
-+
-+}
-+#endif
-+
-+void
-+odm_iq_calibrate(
-+	struct dm_struct	*dm
-+)
-+{
-+	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
-+
-+	if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {
-+		if ((*dm->channel != dm->pre_channel) && (!*dm->is_scan_in_process)) {
-+			dm->pre_channel = *dm->channel;
-+			dm->linked_interval = 0;
-+		}
-+
-+		if (dm->linked_interval < 3)
-+			dm->linked_interval++;
-+
-+		if (dm->linked_interval == 2)
-+			halrf_iqk_trigger(dm, false);
-+	} else
-+		dm->linked_interval = 0;
-+
-+}
-+
-+void phydm_rf_init(void		*dm_void)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	odm_txpowertracking_init(dm);
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+#if (RTL8814A_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814A)
-+		phy_iq_calibrate_8814a_init(dm);
-+#endif
-+#endif
-+
-+}
-+
-+void phydm_rf_watchdog(void		*dm_void)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+
-+	odm_txpowertracking_check(dm);
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-+		odm_iq_calibrate(dm);
-+#endif
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_ap.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_ap.h
-new file mode 100644
-index 000000000000..8cc2797bc58c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_ap.h
-@@ -0,0 +1,170 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALPHYRF_H__
-+#define __HALPHYRF_H__
-+
-+#include "halrf/halrf_powertracking_ap.h"
-+#include "halrf/halrf_kfree.h"
-+
-+#if (RTL8814A_SUPPORT == 1)
-+	#include "halrf/rtl8814a/halrf_iqk_8814a.h"
-+#endif
-+
-+#if (RTL8822B_SUPPORT == 1)
-+	#include "halrf/rtl8822b/halrf_iqk_8822b.h"
-+#endif
-+
-+#if (RTL8821C_SUPPORT == 1)
-+	#include "halrf/rtl8821c/halrf_iqk_8821c.h"
-+#endif
-+
-+#if (RTL8195B_SUPPORT == 1)
-+//	#include "halrf/rtl8195b/halrf.h"
-+	#include "halrf/rtl8195b/halrf_iqk_8195b.h"
-+	#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
-+	#include "halrf/rtl8195b/halrf_dpk_8195b.h"
-+#endif
-+
-+#if (RTL8198F_SUPPORT == 1)
-+	#include "halrf/rtl8198f/halrf_iqk_8198f.h"
-+	#include "halrf/rtl8198f/halrf_dpk_8198f.h"
-+#endif
-+
-+#if (RTL8812F_SUPPORT == 1)
-+	#include "halrf/rtl8812f/halrf_iqk_8812f.h"
-+	#include "halrf/rtl8812f/halrf_dpk_8812f.h"
-+	#include "halrf/rtl8812f/halrf_tssi_8812f.h"
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	#include "halrf/rtl8814b/halrf_iqk_8814b.h"
-+	#include "halrf/rtl8814b/halrf_dpk_8814b.h"
-+	#include "halrf/rtl8814b/halrf_txgapk_8814b.h"
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	#include "halrf/rtl8197g/halrf_iqk_8197g.h"
-+	#include "halrf/rtl8197g/halrf_dpk_8197g.h"
-+	#include "halrf/rtl8197g/halrf_tssi_8197g.h"
-+#endif
-+
-+enum pwrtrack_method {
-+	BBSWING,
-+	TXAGC,
-+	MIX_MODE,
-+	TSSI_MODE,
-+	MIX_2G_TSSI_5G_MODE,
-+	MIX_5G_TSSI_2G_MODE,
-+	CLEAN_MODE
-+};
-+
-+typedef void	(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
-+typedef void(*func_iqk)(void *, u8, u8, u8);
-+typedef void	(*func_lck)(void *);
-+typedef void	(*func_tssi_dck)(void *, u8);
-+/* refine by YuChen for 8814A */
-+typedef void	(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
-+typedef void	(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
-+typedef void	(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
-+typedef void	(*func_all_swing_ex)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
-+
-+struct txpwrtrack_cfg {
-+	u8		swing_table_size_cck;
-+	u8		swing_table_size_ofdm;
-+	u8		threshold_iqk;
-+	u8		threshold_dpk;
-+	u8		average_thermal_num;
-+	u8		rf_path_count;
-+	u32		thermal_reg_addr;
-+	func_set_pwr	odm_tx_pwr_track_set_pwr;
-+	func_iqk	do_iqk;
-+	func_lck		phy_lc_calibrate;
-+	func_tssi_dck	do_tssi_dck;
-+	func_swing	get_delta_swing_table;
-+	func_swing8814only	get_delta_swing_table8814only;
-+	func_all_swing		get_delta_all_swing_table;
-+	func_all_swing_ex	get_delta_all_swing_table_ex;
-+};
-+
-+void
-+odm_clear_txpowertracking_state(
-+	void *dm_void
-+);
-+
-+void
-+configure_txpower_track(
-+	void		*dm_void,
-+	struct txpwrtrack_cfg	*config
-+);
-+
-+
-+void
-+odm_txpowertracking_callback_thermal_meter(
-+	void		*dm_void
-+);
-+
-+#if (RTL8192E_SUPPORT == 1)
-+void
-+odm_txpowertracking_callback_thermal_meter_92e(
-+	void		*dm_void
-+);
-+#endif
-+
-+#if (RTL8814A_SUPPORT == 1)
-+void
-+odm_txpowertracking_callback_thermal_meter_jaguar_series2(
-+	void		*dm_void
-+);
-+
-+#elif ODM_IC_11AC_SERIES_SUPPORT
-+void
-+odm_txpowertracking_callback_thermal_meter_jaguar_series(
-+	void		*dm_void
-+);
-+
-+#elif (RTL8197F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
-+	RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
-+void
-+odm_txpowertracking_callback_thermal_meter_jaguar_series3(
-+	void		*dm_void
-+);
-+
-+#elif (RTL8814B_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
-+void
-+odm_txpowertracking_callback_thermal_meter_jaguar_series4(
-+	void		*dm_void
-+);
-+
-+#endif
-+
-+#define IS_CCK_RATE(_rate)				(ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M)
-+
-+#define ODM_TARGET_CHNL_NUM_2G_5G	59
-+
-+
-+void
-+odm_reset_iqk_result(
-+	void		*dm_void
-+);
-+u8
-+odm_get_right_chnl_place_for_iqk(
-+	u8 chnl
-+);
-+
-+void phydm_rf_init(void		*dm_void);
-+void phydm_rf_watchdog(void		*dm_void);
-+
-+#endif	/*#ifndef __HALPHYRF_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_ce.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_ce.c
-new file mode 100644
-index 000000000000..1cfb95d36b9c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_ce.c
-@@ -0,0 +1,1180 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal)\
-+	do {                                                                   \
-+		u32 __offset = (u32)_offset;                                   \
-+		u32 __size = (u32)_size;                                       \
-+		for (__offset = 0; __offset < __size; __offset++) {            \
-+			if (_delta_thermal <                                   \
-+				thermal_threshold[_direction][__offset]) {     \
-+				if (__offset != 0)                             \
-+					__offset--;                            \
-+				break;                                         \
-+			}                                                      \
-+		}                                                              \
-+		if (__offset >= __size)                                        \
-+			__offset = __size - 1;                                 \
-+	} while (0)
-+
-+void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if RTL8192E_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8192E)
-+		configure_txpower_track_8192e(config);
-+#endif
-+#if RTL8821A_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8821)
-+		configure_txpower_track_8821a(config);
-+#endif
-+#if RTL8812A_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8812)
-+		configure_txpower_track_8812a(config);
-+#endif
-+#if RTL8188E_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8188E)
-+		configure_txpower_track_8188e(config);
-+#endif
-+
-+#if RTL8723B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8723B)
-+		configure_txpower_track_8723b(config);
-+#endif
-+
-+#if RTL8814A_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8814A)
-+		configure_txpower_track_8814a(config);
-+#endif
-+
-+#if RTL8703B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8703B)
-+		configure_txpower_track_8703b(config);
-+#endif
-+
-+#if RTL8188F_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8188F)
-+		configure_txpower_track_8188f(config);
-+#endif
-+#if RTL8723D_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8723D)
-+		configure_txpower_track_8723d(config);
-+#endif
-+/*@ JJ ADD 20161014 */
-+#if RTL8710B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8710B)
-+		configure_txpower_track_8710b(config);
-+#endif
-+#if RTL8822B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8822B)
-+		configure_txpower_track_8822b(config);
-+#endif
-+#if RTL8821C_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8821C)
-+		configure_txpower_track_8821c(config);
-+#endif
-+
-+#if RTL8192F_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8192F)
-+		configure_txpower_track_8192f(config);
-+#endif
-+
-+#if RTL8822C_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8822C)
-+		configure_txpower_track_8822c(config);
-+#endif
-+
-+#if RTL8814B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8814B)
-+		configure_txpower_track_8814b(config);
-+#endif
-+
-+#if RTL8723F_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8723F)
-+		configure_txpower_track_8723f(config);
-+#endif
-+
-+}
-+
-+/*@ **********************************************************************
-+ * <20121113, Kordan> This function should be called when tx_agc changed.
-+ * Otherwise the previous compensation is gone, because we record the
-+ * delta of temperature between two TxPowerTracking watch dogs.
-+ *
-+ * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
-+ * need to call this function.
-+ * **********************************************************************
-+ */
-+void odm_clear_txpowertracking_state(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	u8 p = 0;
-+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-+
-+	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
-+	cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
-+	dm->rf_calibrate_info.CCK_index = 0;
-+
-+	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
-+		cali_info->bb_swing_idx_ofdm_base[p]
-+						= cali_info->default_ofdm_index;
-+		cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
-+		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
-+
-+		cali_info->power_index_offset[p] = 0;
-+		cali_info->delta_power_index[p] = 0;
-+		cali_info->delta_power_index_last[p] = 0;
-+
-+		/* Initial Mix mode power tracking*/
-+		cali_info->absolute_ofdm_swing_idx[p] = 0;
-+		cali_info->remnant_ofdm_swing_idx[p] = 0;
-+		cali_info->kfree_offset[p] = 0;
-+	}
-+	/* Initial Mix mode power tracking*/
-+	cali_info->modify_tx_agc_flag_path_a = false;
-+	cali_info->modify_tx_agc_flag_path_b = false;
-+	cali_info->modify_tx_agc_flag_path_c = false;
-+	cali_info->modify_tx_agc_flag_path_d = false;
-+	cali_info->remnant_cck_swing_idx = 0;
-+	cali_info->thermal_value = rf->eeprom_thermal;
-+	cali_info->modify_tx_agc_value_cck = 0;
-+	cali_info->modify_tx_agc_value_ofdm = 0;
-+}
-+
-+void odm_get_tracking_table(void *dm_void, u8 thermal_value, u8 delta)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct txpwrtrack_cfg c = {0};
-+
-+	u8 p;
-+	/* 4 1. TWO tables decide the final index of OFDM/CCK swing table. */
-+	u8 *pwrtrk_tab_up_a = NULL;
-+	u8 *pwrtrk_tab_down_a = NULL;
-+	u8 *pwrtrk_tab_up_b = NULL;
-+	u8 *pwrtrk_tab_down_b = NULL;
-+	/*for 8814 add by Yu Chen*/
-+	u8 *pwrtrk_tab_up_c = NULL;
-+	u8 *pwrtrk_tab_down_c = NULL;
-+	u8 *pwrtrk_tab_up_d = NULL;
-+	u8 *pwrtrk_tab_down_d = NULL;
-+	/*for Xtal Offset by James.Tung*/
-+	s8 *xtal_tab_up = NULL;
-+	s8 *xtal_tab_down = NULL;
-+
-+	configure_txpower_track(dm, &c);
-+
-+	(*c.get_delta_swing_table)(dm,
-+				   (u8 **)&pwrtrk_tab_up_a,
-+				   (u8 **)&pwrtrk_tab_down_a,
-+				   (u8 **)&pwrtrk_tab_up_b,
-+				   (u8 **)&pwrtrk_tab_down_b);
-+
-+	if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/
-+		(*c.get_delta_swing_table8814only)(dm,
-+						   (u8 **)&pwrtrk_tab_up_c,
-+						   (u8 **)&pwrtrk_tab_down_c,
-+						   (u8 **)&pwrtrk_tab_up_d,
-+						   (u8 **)&pwrtrk_tab_down_d);
-+	/*for Xtal Offset*/
-+	if (dm->support_ic_type &
-+	    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F))
-+		(*c.get_delta_swing_xtal_table)(dm,
-+						(s8 **)&xtal_tab_up,
-+						(s8 **)&xtal_tab_down);
-+
-+	if (thermal_value > rf->eeprom_thermal) {
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+			/*recording power index offset*/
-+			cali_info->delta_power_index_last[p] =
-+					cali_info->delta_power_index[p];
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "******Temp is higher******\n");
-+			switch (p) {
-+			case RF_PATH_B:
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "pwrtrk_tab_up_b[%d] = %d\n", delta,
-+				       pwrtrk_tab_up_b[delta]);
-+
-+				cali_info->delta_power_index[p] =
-+							pwrtrk_tab_up_b[delta];
-+				cali_info->absolute_ofdm_swing_idx[p] =
-+							pwrtrk_tab_up_b[delta];
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "absolute_ofdm_swing_idx[PATH_B] = %d\n",
-+				       cali_info->absolute_ofdm_swing_idx[p]);
-+				break;
-+
-+			case RF_PATH_C:
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "pwrtrk_tab_up_c[%d] = %d\n", delta,
-+				       pwrtrk_tab_up_c[delta]);
-+
-+				cali_info->delta_power_index[p] =
-+							pwrtrk_tab_up_c[delta];
-+				cali_info->absolute_ofdm_swing_idx[p] =
-+							pwrtrk_tab_up_c[delta];
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "absolute_ofdm_swing_idx[PATH_C] = %d\n",
-+				       cali_info->absolute_ofdm_swing_idx[p]);
-+				break;
-+
-+			case RF_PATH_D:
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "pwrtrk_tab_up_d[%d] = %d\n", delta,
-+				       pwrtrk_tab_up_d[delta]);
-+
-+				cali_info->delta_power_index[p] =
-+							pwrtrk_tab_up_d[delta];
-+				cali_info->absolute_ofdm_swing_idx[p] =
-+							pwrtrk_tab_up_d[delta];
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "absolute_ofdm_swing_idx[PATH_D] = %d\n",
-+				       cali_info->absolute_ofdm_swing_idx[p]);
-+				break;
-+
-+			default:
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "pwrtrk_tab_up_a[%d] = %d\n", delta,
-+				       pwrtrk_tab_up_a[delta]);
-+
-+				cali_info->delta_power_index[p] =
-+							pwrtrk_tab_up_a[delta];
-+				cali_info->absolute_ofdm_swing_idx[p] =
-+							pwrtrk_tab_up_a[delta];
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "absolute_ofdm_swing_idx[PATH_A] = %d\n",
-+				       cali_info->absolute_ofdm_swing_idx[p]);
-+				break;
-+			}
-+		}
-+		/* @JJ ADD 20161014 */
-+		/*Save xtal_offset from Xtal table*/
-+		if (dm->support_ic_type &
-+		    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B |
-+		    ODM_RTL8192F)) {
-+			/*recording last Xtal offset*/
-+			cali_info->xtal_offset_last = cali_info->xtal_offset;
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "[Xtal] xtal_tab_up[%d] = %d\n",
-+			       delta, xtal_tab_up[delta]);
-+			cali_info->xtal_offset = xtal_tab_up[delta];
-+			if (cali_info->xtal_offset_last != xtal_tab_up[delta])
-+				cali_info->xtal_offset_eanble = 1;
-+		}
-+	} else {
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+			/*recording power index offset*/
-+			cali_info->delta_power_index_last[p] =
-+						cali_info->delta_power_index[p];
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "******Temp is lower******\n");
-+			switch (p) {
-+			case RF_PATH_B:
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "pwrtrk_tab_down_b[%d] = %d\n", delta,
-+				       pwrtrk_tab_down_b[delta]);
-+				cali_info->delta_power_index[p] =
-+						-1 * pwrtrk_tab_down_b[delta];
-+				cali_info->absolute_ofdm_swing_idx[p] =
-+						-1 * pwrtrk_tab_down_b[delta];
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "absolute_ofdm_swing_idx[PATH_B] = %d\n",
-+				       cali_info->absolute_ofdm_swing_idx[p]);
-+				break;
-+
-+			case RF_PATH_C:
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "pwrtrk_tab_down_c[%d] = %d\n", delta,
-+				       pwrtrk_tab_down_c[delta]);
-+				cali_info->delta_power_index[p] =
-+						-1 * pwrtrk_tab_down_c[delta];
-+				cali_info->absolute_ofdm_swing_idx[p] =
-+						-1 * pwrtrk_tab_down_c[delta];
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "absolute_ofdm_swing_idx[PATH_C] = %d\n",
-+				       cali_info->absolute_ofdm_swing_idx[p]);
-+				break;
-+
-+			case RF_PATH_D:
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "pwrtrk_tab_down_d[%d] = %d\n", delta,
-+				       pwrtrk_tab_down_d[delta]);
-+				cali_info->delta_power_index[p] =
-+						-1 * pwrtrk_tab_down_d[delta];
-+				cali_info->absolute_ofdm_swing_idx[p] =
-+						-1 * pwrtrk_tab_down_d[delta];
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "absolute_ofdm_swing_idx[PATH_D] = %d\n",
-+				       cali_info->absolute_ofdm_swing_idx[p]);
-+				break;
-+
-+			default:
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "pwrtrk_tab_down_a[%d] = %d\n", delta,
-+				       pwrtrk_tab_down_a[delta]);
-+				cali_info->delta_power_index[p] =
-+						-1 * pwrtrk_tab_down_a[delta];
-+				cali_info->absolute_ofdm_swing_idx[p] =
-+						-1 * pwrtrk_tab_down_a[delta];
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "absolute_ofdm_swing_idx[PATH_A] = %d\n",
-+				       cali_info->absolute_ofdm_swing_idx[p]);
-+				break;
-+			}
-+		}
-+		/* @JJ ADD 20161014 */
-+		if (dm->support_ic_type &
-+		    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B |
-+		    ODM_RTL8192F)) {
-+			/*recording last Xtal offset*/
-+			cali_info->xtal_offset_last = cali_info->xtal_offset;
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "[Xtal] xtal_tab_down[%d] = %d\n", delta,
-+			       xtal_tab_down[delta]);
-+			/*Save xtal_offset from Xtal table*/
-+			cali_info->xtal_offset = xtal_tab_down[delta];
-+			if (cali_info->xtal_offset_last != xtal_tab_down[delta])
-+				cali_info->xtal_offset_eanble = 1;
-+		}
-+	}
-+}
-+
-+void odm_pwrtrk_method(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 p, idxforchnl = 0;
-+
-+	struct txpwrtrack_cfg c = {0};
-+
-+	configure_txpower_track(dm, &c);
-+
-+	if (dm->support_ic_type &
-+		(ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8821 | ODM_RTL8812 |
-+		ODM_RTL8723B | ODM_RTL8814A | ODM_RTL8703B | ODM_RTL8188F |
-+		ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8710B |
-+		ODM_RTL8192F)) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "***Enter PwrTrk MIX_MODE***\n");
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+	} else if (dm->support_ic_type & ODM_RTL8723D) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "***Enter PwrTrk MIX_MODE***\n");
-+		p = (u8)odm_get_bb_reg(dm, R_0x948, 0x00000080);
-+		(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+		/*if open ant_div 0x948=140,do 2 path pwr_track*/
-+		if (odm_get_bb_reg(dm, R_0x948, 0x00000040))
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, 1, 0);
-+	} else {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "***Enter PwrTrk BBSWING_MODE***\n");
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			(*c.odm_tx_pwr_track_set_pwr)
-+				(dm, BBSWING, p, idxforchnl);
-+	}
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+void odm_txpowertracking_callback_thermal_meter(struct dm_struct *dm)
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+void odm_txpowertracking_callback_thermal_meter(void *dm_void)
-+#else
-+void odm_txpowertracking_callback_thermal_meter(void *adapter)
-+#endif
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#endif
-+
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+
-+	u8 thermal_value = 0, delta, delta_lck, delta_iqk, p = 0, i = 0;
-+	u8 thermal_value_avg_count = 0;
-+	u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
-+
-+	/* OFDM BB Swing should be less than +3.0dB, required by Arthur */
-+#if 0
-+	u8 OFDM_min_index = 0;
-+#endif
-+#if 0
-+	/* get_right_chnl_place_for_iqk(hal_data->current_channel) */
-+#endif
-+	u8 power_tracking_type = rf->pwt_type;
-+	s8 thermal_value_temp = 0;
-+
-+	struct txpwrtrack_cfg c = {0};
-+
-+	/* @4 2. Initialization ( 7 steps in total ) */
-+
-+	configure_txpower_track(dm, &c);
-+
-+	cali_info->txpowertracking_callback_cnt++;
-+	cali_info->is_txpowertracking_init = true;
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+	       "\n\n\n===>%s bbsw_idx_cck_base=%d\n",
-+	       __func__, cali_info->bb_swing_idx_cck_base);
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+	       "bbsw_idx_ofdm_base[A]=%d default_ofdm_idx=%d\n",
-+	       cali_info->bb_swing_idx_ofdm_base[RF_PATH_A],
-+	       cali_info->default_ofdm_index);
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+	       "cali_info->txpowertrack_control=%d, rf->eeprom_thermal %d\n",
-+	       cali_info->txpowertrack_control, rf->eeprom_thermal);
-+
-+	 /* 0x42: RF Reg[15:10] 88E */
-+	thermal_value =
-+		(u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);
-+
-+	thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+	       "thermal_value_temp(%d) = ther_value(%d) + pwr_trim_ther(%d)\n",
-+	       thermal_value_temp, thermal_value,
-+	       phydm_get_thermal_offset(dm));
-+
-+	if (thermal_value_temp > 63)
-+		thermal_value = 63;
-+	else if (thermal_value_temp < 0)
-+		thermal_value = 0;
-+	else
-+		thermal_value = thermal_value_temp;
-+
-+	/*@add log by zhao he, check c80/c94/c14/ca0 value*/
-+	if (dm->support_ic_type &
-+	    (ODM_RTL8723D | ODM_RTL8710B)) {
-+		regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
-+		regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
-+		regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
-+		regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);
-+		RF_DBG(dm, DBG_RF_IQK,
-+		       "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n",
-+		       regc80, regcd0, regcd4, regab4);
-+	}
-+
-+	if (!cali_info->txpowertrack_control)
-+		return;
-+
-+	if (rf->eeprom_thermal == 0xff) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "no pg, hal_data->eeprom_thermal_meter = 0x%x\n",
-+		       rf->eeprom_thermal);
-+		return;
-+	}
-+
-+	/*@4 3. Initialize ThermalValues of rf_calibrate_info*/
-+
-+	if (cali_info->is_reloadtxpowerindex)
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "reload ofdm index for band switch\n");
-+
-+	/*@4 4. Calculate average thermal meter*/
-+
-+	cali_info->thermal_value_avg[cali_info->thermal_value_avg_index]
-+		= thermal_value;
-+
-+	cali_info->thermal_value_avg_index++;
-+	/*Average times =  c.average_thermal_num*/
-+	if (cali_info->thermal_value_avg_index == c.average_thermal_num)
-+		cali_info->thermal_value_avg_index = 0;
-+
-+	for (i = 0; i < c.average_thermal_num; i++) {
-+		if (cali_info->thermal_value_avg[i]) {
-+			thermal_value_avg += cali_info->thermal_value_avg[i];
-+			thermal_value_avg_count++;
-+		}
-+	}
-+
-+	/* Calculate Average thermal_value after average enough times */
-+	if (thermal_value_avg_count) {
-+		thermal_value =
-+			(u8)(thermal_value_avg / thermal_value_avg_count);
-+		cali_info->thermal_value_delta
-+			= thermal_value - rf->eeprom_thermal;
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n",
-+		       thermal_value, rf->eeprom_thermal);
-+	}
-+
-+	/* @4 5. Calculate delta, delta_lck, delta_iqk. */
-+	/* "delta" here is used to determine thermal value changes or not. */
-+	if (thermal_value > cali_info->thermal_value)
-+		delta = thermal_value - cali_info->thermal_value;
-+	else
-+		delta = cali_info->thermal_value - thermal_value;
-+
-+	if (thermal_value > cali_info->thermal_value_lck)
-+		delta_lck = thermal_value - cali_info->thermal_value_lck;
-+	else
-+		delta_lck = cali_info->thermal_value_lck - thermal_value;
-+
-+	if (thermal_value > cali_info->thermal_value_iqk)
-+		delta_iqk = thermal_value - cali_info->thermal_value_iqk;
-+	else
-+		delta_iqk = cali_info->thermal_value_iqk - thermal_value;
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+	       "(delta, delta_lck, delta_iqk) = (%d, %d, %d)\n", delta,
-+	       delta_lck, delta_iqk);
-+
-+	/*@4 6. If necessary, do LCK.*/
-+	/* Wait sacn to do LCK by RF Jenyu*/
-+	if (!(*dm->is_scan_in_process) && !iqk_info->rfk_forbidden) {
-+		/* Delta temperature is equal to or larger than 20 centigrade.*/
-+		if (delta_lck >= c.threshold_iqk) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "delta_lck(%d) >= threshold_iqk(%d)\n",
-+			       delta_lck, c.threshold_iqk);
-+			cali_info->thermal_value_lck = thermal_value;
-+
-+			/*Use RTLCK, close power tracking driver LCK*/
-+			/*8821 don't do LCK*/
-+			if (!(dm->support_ic_type &
-+				(ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B)) &&
-+				c.phy_lc_calibrate) {
-+				(*c.phy_lc_calibrate)(dm);
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "do pwrtrk lck\n");
-+			}
-+		}
-+	}
-+
-+	/*@3 7. If necessary, move the index of swing table to adjust Tx power.*/
-+	/* "delta" here is used to record the absolute value of difference. */
-+	if (delta > 0 && cali_info->txpowertrack_control) {
-+		if (thermal_value > rf->eeprom_thermal)
-+			delta = thermal_value - rf->eeprom_thermal;
-+		else
-+			delta = rf->eeprom_thermal - thermal_value;
-+
-+		if (delta >= TXPWR_TRACK_TABLE_SIZE)
-+			delta = TXPWR_TRACK_TABLE_SIZE - 1;
-+
-+		odm_get_tracking_table(dm, thermal_value, delta);
-+
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "\n[path-%d] Calculate pwr_idx_offset\n", p);
-+
-+			/*If Thermal value changes but table value is the same*/
-+			if (cali_info->delta_power_index[p] ==
-+				cali_info->delta_power_index_last[p])
-+				cali_info->power_index_offset[p] = 0;
-+			else
-+				cali_info->power_index_offset[p] =
-+				cali_info->delta_power_index[p] -
-+				cali_info->delta_power_index_last[p];
-+
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "path-%d pwridx_diff%d=pwr_idx%d - last_idx%d\n",
-+			       p, cali_info->power_index_offset[p],
-+			       cali_info->delta_power_index[p],
-+			       cali_info->delta_power_index_last[p]);
-+#if 0
-+
-+			cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
-+			cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
-+
-+			cali_info->bb_swing_idx_cck = cali_info->CCK_index;
-+			cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
-+
-+			/*************Print BB Swing base and index Offset*************/
-+
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n",
-+			       cali_info->bb_swing_idx_cck,
-+			       cali_info->bb_swing_idx_cck_base,
-+			       cali_info->power_index_offset[p]);
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n",
-+			       cali_info->bb_swing_idx_ofdm[p], p,
-+			       cali_info->bb_swing_idx_ofdm_base[p],
-+			       cali_info->power_index_offset[p]);
-+
-+			/*4 7.1 Handle boundary conditions of index.*/
-+
-+			if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
-+				cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
-+			else if (cali_info->OFDM_index[p] <= OFDM_min_index)
-+				cali_info->OFDM_index[p] = OFDM_min_index;
-+#endif
-+		}
-+#if 0
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "\n\n========================================================================================================\n");
-+
-+		if (cali_info->CCK_index > c.swing_table_size_cck - 1)
-+			cali_info->CCK_index = c.swing_table_size_cck - 1;
-+		else if (cali_info->CCK_index <= 0)
-+			cali_info->CCK_index = 0;
-+#endif
-+	} else {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "Thermal is unchanged thermal=%d last_thermal=%d\n",
-+		       thermal_value,
-+		       cali_info->thermal_value);
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			cali_info->power_index_offset[p] = 0;
-+	}
-+
-+#if 0
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+	       "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
-+	       cali_info->CCK_index,
-+	       cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/
-+
-+	for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
-+		       cali_info->OFDM_index[p], p,
-+		       cali_info->bb_swing_idx_ofdm_base[p]);
-+	}
-+#endif
-+
-+	if ((dm->support_ic_type & ODM_RTL8814A)) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "power_tracking_type=%d\n",
-+		       power_tracking_type);
-+
-+		if (power_tracking_type == 0) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "***Enter PwrTrk MIX_MODE***\n");
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+				(*c.odm_tx_pwr_track_set_pwr)
-+					(dm, MIX_MODE, p, 0);
-+		} else if (power_tracking_type == 1) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "***Enter PwrTrk MIX(2G) TSSI(5G) MODE***\n");
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+				(*c.odm_tx_pwr_track_set_pwr)
-+					(dm, MIX_2G_TSSI_5G_MODE, p, 0);
-+		} else if (power_tracking_type == 2) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "***Enter PwrTrk MIX(5G) TSSI(2G)MODE***\n");
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+				(*c.odm_tx_pwr_track_set_pwr)
-+					(dm, MIX_5G_TSSI_2G_MODE, p, 0);
-+		} else if (power_tracking_type == 3) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "***Enter PwrTrk TSSI MODE***\n");
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+				(*c.odm_tx_pwr_track_set_pwr)
-+					(dm, TSSI_MODE, p, 0);
-+		}
-+	} else if ((cali_info->power_index_offset[RF_PATH_A] != 0 ||
-+		    cali_info->power_index_offset[RF_PATH_B] != 0 ||
-+		    cali_info->power_index_offset[RF_PATH_C] != 0 ||
-+		    cali_info->power_index_offset[RF_PATH_D] != 0)) {
-+#if 0
-+		/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
-+		/*Always true after Tx Power is adjusted by power tracking.*/
-+
-+		cali_info->is_tx_power_changed = true;
-+		/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
-+		 * to increase TX power. Otherwise, EVM will be bad.
-+		 *
-+		 * 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.
-+		 */
-+		if (thermal_value > cali_info->thermal_value) {
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
-+				       p, cali_info->power_index_offset[p],
-+				       delta, thermal_value, rf->eeprom_thermal,
-+				       cali_info->thermal_value);
-+			}
-+		} else if (thermal_value < cali_info->thermal_value) { /*Low temperature*/
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
-+				       p, cali_info->power_index_offset[p],
-+				       delta, thermal_value, rf->eeprom_thermal,
-+				       cali_info->thermal_value);
-+			}
-+		}
-+#endif
-+
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+		if (thermal_value > rf->eeprom_thermal) {
-+#else
-+		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
-+#endif
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "Temperature(%d) higher than PG value(%d)\n",
-+			       thermal_value, rf->eeprom_thermal);
-+
-+			odm_pwrtrk_method(dm);
-+		} else {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "Temperature(%d) lower than PG value(%d)\n",
-+			       thermal_value, rf->eeprom_thermal);
-+
-+			odm_pwrtrk_method(dm);
-+		}
-+
-+#if 0
-+		/*Record last time Power Tracking result as base.*/
-+		cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
-+#endif
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "cali_info->thermal_value = %d thermal_value= %d\n",
-+		       cali_info->thermal_value, thermal_value);
-+	}
-+	/*Record last Power Tracking Thermal value*/
-+	cali_info->thermal_value = thermal_value;
-+
-+	if (dm->support_ic_type &
-+		(ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8192F | ODM_RTL8710B)) {
-+		if (cali_info->xtal_offset_eanble != 0 &&
-+		    cali_info->txpowertrack_control &&
-+		    rf->eeprom_thermal != 0xff) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "**********Enter Xtal Tracking**********\n");
-+
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+			if (thermal_value > rf->eeprom_thermal) {
-+#else
-+			if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
-+#endif
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "Temperature(%d) higher than PG (%d)\n",
-+				       thermal_value, rf->eeprom_thermal);
-+				(*c.odm_txxtaltrack_set_xtal)(dm);
-+			} else {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "Temperature(%d) lower than PG (%d)\n",
-+				       thermal_value, rf->eeprom_thermal);
-+				(*c.odm_txxtaltrack_set_xtal)(dm);
-+			}
-+		}
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "**********End Xtal Tracking**********\n");
-+	}
-+
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+
-+	/* Wait sacn to do IQK by RF Jenyu*/
-+	if (!(*dm->is_scan_in_process) && !iqk_info->rfk_forbidden &&
-+	    !cali_info->is_iqk_in_progress && dm->is_linked) {
-+		if (!(dm->support_ic_type & ODM_RTL8723B)) {
-+			/*Delta temperature is equal or larger than 20 Celsius*/
-+			/*When threshold is 8*/
-+			if (delta_iqk >= c.threshold_iqk) {
-+				cali_info->thermal_value_iqk = thermal_value;
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "delta_iqk(%d) >= threshold_iqk(%d)\n",
-+				       delta_iqk, c.threshold_iqk);
-+				(*c.do_iqk)(dm, delta_iqk, thermal_value, 8);
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "do pwrtrk iqk\n");
-+			}
-+		}
-+	}
-+
-+#if 0
-+	if (cali_info->dpk_thermal[RF_PATH_A] != 0) {
-+		if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) {
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
-+			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
-+		} else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) {
-+			s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk);
-+
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
-+			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
-+		} else {
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
-+			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
-+		}
-+	}
-+	if (cali_info->dpk_thermal[RF_PATH_B] != 0) {
-+		if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) {
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
-+			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
-+		} else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) {
-+			s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk);
-+
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
-+			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
-+		} else {
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
-+			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
-+		}
-+	}
-+#endif
-+
-+#endif
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===%s\n", __func__);
-+
-+	cali_info->tx_powercount = 0;
-+}
-+
-+#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-+void
-+odm_txpowertracking_new_callback_thermal_meter(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
-+ 	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
-+	u8 thermal_value[MAX_RF_PATH] = {0}, delta[MAX_RF_PATH] = {0};
-+	u8 delta_swing_table_idx_tup[DELTA_SWINGIDX_SIZE] = {0};
-+	u8 delta_swing_table_idx_tdown[DELTA_SWINGIDX_SIZE] = {0};
-+	u8 delta_LCK = 0, delta_IQK = 0, i = 0, j = 0, p;
-+	u8 thermal_value_avg_count[MAX_RF_PATH] = {0};
-+	u32 thermal_value_avg[MAX_RF_PATH] = {0};
-+	s8 thermal_value_temp[MAX_RF_PATH] = {0};
-+	u8 tracking_method = MIX_MODE;
-+
-+	struct txpwrtrack_cfg c;
-+
-+	u8 *delta_swing_table_idx_tup_a = NULL;
-+	u8 *delta_swing_table_idx_tdown_a = NULL;
-+	u8 *delta_swing_table_idx_tup_b = NULL;
-+	u8 *delta_swing_table_idx_tdown_b = NULL;
-+	u8 *delta_swing_table_idx_tup_c = NULL;
-+	u8 *delta_swing_table_idx_tdown_c = NULL;
-+	u8 *delta_swing_table_idx_tup_d = NULL;
-+	u8 *delta_swing_table_idx_tdown_d = NULL;
-+
-+	configure_txpower_track(dm, &c);
-+
-+	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
-+		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
-+
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
-+			(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
-+	}
-+
-+	cali_info->txpowertracking_callback_cnt++;
-+	cali_info->is_txpowertracking_init = true;
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
-+		cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		"cali_info->txpowertrack_control=%d, tssi->thermal[RF_PATH_A]=%d tssi->thermal[RF_PATH_B]=%d\n",
-+		cali_info->txpowertrack_control,  tssi->thermal[RF_PATH_A], tssi->thermal[RF_PATH_B]);
-+
-+	if (dm->support_ic_type == ODM_RTL8822C) {
-+		for (i = 0; i < c.rf_path_count; i++)
-+			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0x7e); /* 0x42: RF Reg[6:1] Thermal Trim*/
-+	} else {
-+		for (i = 0; i < c.rf_path_count; i++) {
-+			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
-+
-+			if (dm->support_ic_type == ODM_RTL8814B) {
-+				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_multi_thermal_offset(dm, i);
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + multi_thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_multi_thermal_offset(dm, i));
-+			} else {
-+				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
-+			}
-+
-+			if (thermal_value_temp[i] > 63)
-+				thermal_value[i] = 63;
-+			else if (thermal_value_temp[i] < 0)
-+				thermal_value[i] = 0;
-+			else
-+				thermal_value[i] = thermal_value_temp[i];
-+		}
-+	}
-+
-+	if ((tssi->thermal[RF_PATH_A] == 0xff || tssi->thermal[RF_PATH_B] == 0xff) &&
-+		cali_info->txpowertrack_control != 3) {
-+		for (i = 0; i < c.rf_path_count; i++)
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, tssi->thermal[%d] = 0x%x\n",
-+				i, tssi->thermal[i]);
-+		return;
-+	}
-+
-+	for (j = 0; j < c.rf_path_count; j++) {
-+		cali_info->thermal_value_avg_path[j][cali_info->thermal_value_avg_index_path[j]] = thermal_value[j];
-+		cali_info->thermal_value_avg_index_path[j]++;
-+		if (cali_info->thermal_value_avg_index_path[j] == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
-+			cali_info->thermal_value_avg_index_path[j] = 0;
-+
-+
-+		for (i = 0; i < c.average_thermal_num; i++) {
-+			if (cali_info->thermal_value_avg_path[j][i]) {
-+				thermal_value_avg[j] += cali_info->thermal_value_avg_path[j][i];
-+				thermal_value_avg_count[j]++;
-+			}
-+		}
-+
-+		if (thermal_value_avg_count[j]) {            /* Calculate Average thermal_value after average enough times */
-+			thermal_value[j] = (u8)(thermal_value_avg[j] / thermal_value_avg_count[j]);
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"AVG Thermal Meter = 0x%X, tssi->thermal[%d] = 0x%x\n",
-+				thermal_value[j], j, tssi->thermal[j]);
-+		}
-+		/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
-+
-+		/* "delta" here is used to determine whether thermal value changes or not. */
-+		delta[j] = (thermal_value[j] > cali_info->thermal_value_path[j]) ? (thermal_value[j] - cali_info->thermal_value_path[j]) : (cali_info->thermal_value_path[j] - thermal_value[j]);
-+		delta_LCK = (thermal_value[0] > cali_info->thermal_value_lck) ? (thermal_value[0] - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value[0]);
-+		delta_IQK = (thermal_value[0] > cali_info->thermal_value_iqk) ? (thermal_value[0] - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value[0]);
-+	}
-+
-+	/*4 6. If necessary, do LCK.*/
-+
-+	for (i = 0; i < c.rf_path_count; i++)
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\n", i, delta[i], delta_LCK, delta_IQK);
-+
-+	/* Wait sacn to do LCK by RF Jenyu*/
-+	if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
-+		/* Delta temperature is equal to or larger than 20 centigrade.*/
-+		if (delta_LCK >= c.threshold_iqk) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
-+			cali_info->thermal_value_lck = thermal_value[RF_PATH_A];
-+
-+			/*Use RTLCK, so close power tracking driver LCK*/
-+			if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
-+				if (c.phy_lc_calibrate)
-+					(*c.phy_lc_calibrate)(dm);
-+			} else
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do not do LCK\n");
-+		}
-+	}
-+
-+	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
-+	for (i = 0; i < c.rf_path_count; i++) {
-+		if (i == RF_PATH_B) {
-+			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_b, DELTA_SWINGIDX_SIZE);
-+			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_b, DELTA_SWINGIDX_SIZE);
-+		} else if (i == RF_PATH_C) {
-+			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_c, DELTA_SWINGIDX_SIZE);
-+			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_c, DELTA_SWINGIDX_SIZE);
-+		} else if (i == RF_PATH_D) {
-+			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_d, DELTA_SWINGIDX_SIZE);
-+			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_d, DELTA_SWINGIDX_SIZE);
-+		} else {
-+			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_a, DELTA_SWINGIDX_SIZE);
-+			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_a, DELTA_SWINGIDX_SIZE);
-+		}
-+
-+		cali_info->delta_power_index_last[i] = cali_info->delta_power_index[i];	/*recording poer index offset*/
-+		delta[i] = thermal_value[i] > tssi->thermal[i] ? (thermal_value[i] - tssi->thermal[i]) : (tssi->thermal[i] - thermal_value[i]);
-+				
-+		if (delta[i] >= TXPWR_TRACK_TABLE_SIZE)
-+			delta[i] = TXPWR_TRACK_TABLE_SIZE - 1;
-+
-+		if (thermal_value[i] > tssi->thermal[i]) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"delta_swing_table_idx_tup[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tup[delta[i]], i);
-+				
-+			cali_info->delta_power_index[i] = delta_swing_table_idx_tup[delta[i]];
-+			cali_info->absolute_ofdm_swing_idx[i] =  delta_swing_table_idx_tup[delta[i]];	    /*Record delta swing for mix mode power tracking*/
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"******Temp is higher and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
-+		} else {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"delta_swing_table_idx_tdown[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tdown[delta[i]], i);
-+			cali_info->delta_power_index[i] = -1 * delta_swing_table_idx_tdown[delta[i]];
-+			cali_info->absolute_ofdm_swing_idx[i] = -1 * delta_swing_table_idx_tdown[delta[i]];        /*Record delta swing for mix mode power tracking*/
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"******Temp is lower and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
-+		}
-+	}
-+
-+	for (p = RF_PATH_A; p < c.rf_path_count; p++) {	
-+		if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p])	     /*If Thermal value changes but lookup table value still the same*/
-+			cali_info->power_index_offset[p] = 0;
-+		else
-+			cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p];	/*Power index diff between 2 times Power Tracking*/
-+	}
-+
-+#if 0
-+	if (dm->support_ic_type == ODM_RTL8822C) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+	} else {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
-+	}
-+#endif
-+	if (*dm->mp_mode == 1) {
-+		if (cali_info->txpowertrack_control == 1) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
-+			tracking_method = MIX_MODE;
-+		} else if (cali_info->txpowertrack_control == 3) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
-+			tracking_method = TSSI_MODE;
-+		}
-+	} else {
-+		if (rf->power_track_type >= 0 && rf->power_track_type <= 3) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
-+			tracking_method = MIX_MODE;
-+		} else if (rf->power_track_type >= 4 && rf->power_track_type <= 7) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
-+			tracking_method = TSSI_MODE;
-+		}
-+	}
-+
-+	if (dm->support_ic_type == ODM_RTL8822C || dm->support_ic_type == ODM_RTL8814B)
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, tracking_method, p, 0);
-+
-+	/* Wait sacn to do IQK by RF Jenyu*/
-+	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden) && (dm->is_linked || *dm->mp_mode)) {
-+		/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
-+		if (delta_IQK >= c.threshold_iqk) {
-+			cali_info->thermal_value_iqk = thermal_value[RF_PATH_A];
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
-+			/*if (!cali_info->is_iqk_in_progress)*/
-+			/*	(*c.do_iqk)(dm, delta_IQK, thermal_value[RF_PATH_A], 8);*/
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do IQK\n");
-+
-+			/*if (!cali_info->is_iqk_in_progress)*/
-+			/*	(*c.do_tssi_dck)(dm, true);*/
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do TSSI DCK\n");
-+		}
-+	}
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===%s\n", __func__);
-+
-+	cali_info->tx_powercount = 0;
-+}
-+#endif
-+
-+/*@3============================================================
-+ * 3 IQ Calibration
-+ * 3============================================================
-+ */
-+
-+void odm_reset_iqk_result(void *dm_void)
-+{
-+}
-+
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
-+{
-+	u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
-+		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
-+		36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,
-+		100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,
-+		124, 126, 128, 130, 132, 134, 136, 138, 140,
-+		149, 151, 153, 155, 157, 159, 161, 163, 165};
-+	u8 place = chnl;
-+
-+	if (chnl > 14) {
-+		for (place = 14; place < sizeof(channel_all); place++) {
-+			if (channel_all[place] == chnl)
-+				return place - 13;
-+		}
-+	}
-+	return 0;
-+}
-+#endif
-+
-+void odm_iq_calibrate(struct dm_struct *dm)
-+{
-+	void *adapter = dm->adapter;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	if (*dm->is_fcs_mode_enable)
-+		return;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+	if (IS_HARDWARE_TYPE_8812AU(adapter))
-+		return;
-+#endif
-+
-+	if (dm->is_linked && !iqk_info->rfk_forbidden) {
-+		if ((*dm->channel != dm->pre_channel) &&
-+		    (!*dm->is_scan_in_process)) {
-+			dm->pre_channel = *dm->channel;
-+			dm->linked_interval = 0;
-+		}
-+
-+		if (dm->linked_interval < 3)
-+			dm->linked_interval++;
-+
-+		if (dm->linked_interval == 2)
-+			halrf_iqk_trigger(dm, false);
-+	} else {
-+		dm->linked_interval = 0;
-+	}
-+}
-+
-+void phydm_rf_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	odm_txpowertracking_init(dm);
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	odm_clear_txpowertracking_state(dm);
-+#endif
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+#if (RTL8814A_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814A)
-+		phy_iq_calibrate_8814a_init(dm);
-+#endif
-+#endif
-+}
-+
-+void phydm_rf_watchdog(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	odm_txpowertracking_check(dm);
-+#if 0
-+/*if (dm->support_ic_type & ODM_IC_11AC_SERIES)*/
-+/*odm_iq_calibrate(dm);*/
-+#endif
-+#endif
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_ce.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_ce.h
-new file mode 100644
-index 000000000000..dcded1e0acb5
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_ce.h
-@@ -0,0 +1,123 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALPHYRF_H__
-+#define __HALPHYRF_H__
-+
-+#include "halrf/halrf_kfree.h"
-+#if (RTL8814A_SUPPORT == 1)
-+#include "halrf/rtl8814a/halrf_iqk_8814a.h"
-+#endif
-+
-+#if (RTL8822B_SUPPORT == 1)
-+#include "halrf/rtl8822b/halrf_iqk_8822b.h"
-+#endif
-+
-+#if (RTL8821C_SUPPORT == 1)
-+#include "halrf/rtl8821c/halrf_iqk_8821c.h"
-+#endif
-+
-+#if (RTL8195B_SUPPORT == 1)
-+/* #include "halrf/rtl8195b/halrf.h" */
-+#include "halrf/rtl8195b/halrf_iqk_8195b.h"
-+#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
-+#include "halrf/rtl8195b/halrf_dpk_8195b.h"
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	#include "halrf/rtl8814b/halrf_iqk_8814b.h"	
-+	#include "halrf/rtl8814b/halrf_dpk_8814b.h"
-+	#include "halrf/rtl8814b/halrf_txgapk_8814b.h"
-+#endif
-+
-+#include "halrf/halrf_powertracking_ce.h"
-+
-+enum spur_cal_method {
-+	PLL_RESET,
-+	AFE_PHASE_SEL
-+};
-+
-+enum pwrtrack_method {
-+	BBSWING,
-+	TXAGC,
-+	MIX_MODE,
-+	TSSI_MODE,
-+	MIX_2G_TSSI_5G_MODE,
-+	MIX_5G_TSSI_2G_MODE,
-+	CLEAN_MODE
-+};
-+
-+typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
-+typedef void (*func_iqk)(void *, u8, u8, u8);
-+typedef void (*func_lck)(void *);
-+typedef void (*func_tssi_dck)(void *, u8);
-+typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
-+typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
-+typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
-+typedef void (*func_set_xtal)(void *);
-+
-+struct txpwrtrack_cfg {
-+	u8 swing_table_size_cck;
-+	u8 swing_table_size_ofdm;
-+	u8 threshold_iqk;
-+	u8 threshold_dpk;
-+	u8 average_thermal_num;
-+	u8 rf_path_count;
-+	u32 thermal_reg_addr;
-+	func_set_pwr odm_tx_pwr_track_set_pwr;
-+	func_iqk do_iqk;
-+	func_lck phy_lc_calibrate;
-+	func_tssi_dck do_tssi_dck;
-+	func_swing get_delta_swing_table;
-+	func_swing8814only get_delta_swing_table8814only;
-+	func_swing_xtal get_delta_swing_xtal_table;
-+	func_set_xtal odm_txxtaltrack_set_xtal;
-+};
-+
-+void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config);
-+
-+void odm_clear_txpowertracking_state(void *dm_void);
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+void odm_txpowertracking_callback_thermal_meter(void *dm_void);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+void odm_txpowertracking_callback_thermal_meter(void *dm);
-+#else
-+void odm_txpowertracking_callback_thermal_meter(void *adapter);
-+#endif
-+
-+#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-+void odm_txpowertracking_new_callback_thermal_meter(void *dm_void);
-+#endif
-+
-+#define ODM_TARGET_CHNL_NUM_2G_5G 59
-+
-+void odm_reset_iqk_result(void *dm_void);
-+u8 odm_get_right_chnl_place_for_iqk(u8 chnl);
-+
-+void phydm_rf_init(void *dm_void);
-+void phydm_rf_watchdog(void *dm_void);
-+
-+#endif /*__HALPHYRF_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_iot.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_iot.c
-new file mode 100644
-index 000000000000..16d9084db881
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_iot.c
-@@ -0,0 +1,664 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#define	CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
-+	do {\
-+		for (_offset = 0; _offset < _size; _offset++) { \
-+			if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
-+				if (_offset != 0)\
-+					_offset--;\
-+				break;\
-+			} \
-+		}			\
-+		if (_offset >= _size)\
-+			_offset = _size-1;\
-+	} while (0)
-+
-+void configure_txpower_track(
-+	void					*dm_void,
-+	struct txpwrtrack_cfg	*config
-+)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if RTL8195B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8195B)
-+		configure_txpower_track_8195b(config);
-+#endif
-+#if RTL8710C_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8710C)
-+		configure_txpower_track_8710c(config);
-+#endif
-+#if RTL8721D_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8721D)
-+		configure_txpower_track_8721d(config);
-+#endif
-+
-+}
-+
-+/* **********************************************************************
-+ * <20121113, Kordan> This function should be called when tx_agc changed.
-+ * Otherwise the previous compensation is gone, because we record the
-+ * delta of temperature between two TxPowerTracking watch dogs.
-+ *
-+ * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
-+ * need to call this function.
-+ * ********************************************************************** */
-+void
-+odm_clear_txpowertracking_state(
-+	void					*dm_void
-+)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	u8			p = 0;
-+	struct dm_rf_calibration_struct	*cali_info = &dm->rf_calibrate_info;
-+
-+	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
-+	cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
-+	dm->rf_calibrate_info.CCK_index = 0;
-+
-+	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
-+		cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
-+		cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
-+		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
-+
-+		cali_info->power_index_offset[p] = 0;
-+		cali_info->delta_power_index[p] = 0;
-+		cali_info->delta_power_index_last[p] = 0;
-+
-+		cali_info->absolute_ofdm_swing_idx[p] = 0;
-+		cali_info->remnant_ofdm_swing_idx[p] = 0;
-+		cali_info->kfree_offset[p] = 0;
-+	}
-+
-+	cali_info->modify_tx_agc_flag_path_a = false;
-+	cali_info->modify_tx_agc_flag_path_b = false;
-+	cali_info->modify_tx_agc_flag_path_c = false;
-+	cali_info->modify_tx_agc_flag_path_d = false;
-+	cali_info->remnant_cck_swing_idx = 0;
-+	cali_info->thermal_value = rf->eeprom_thermal;
-+	cali_info->modify_tx_agc_value_cck = 0;
-+	cali_info->modify_tx_agc_value_ofdm = 0;
-+}
-+
-+void
-+odm_txpowertracking_callback_thermal_meter(
-+	void	*dm_void
-+)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-+	struct	dm_iqk_info *iqk_info = &dm->IQK_info;
-+
-+	u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
-+	u8 thermal_value_avg_count = 0;
-+	u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
-+
-+	u8 OFDM_min_index = 0;  /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
-+	u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
-+	u8 power_tracking_type = rf->pwt_type;
-+	u8 xtal_offset_eanble = 0;
-+	s8 thermal_value_temp = 0;
-+	u8 xtal_track_efuse = 0;
-+
-+	struct txpwrtrack_cfg	c = {0};
-+
-+	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
-+	u8 *delta_swing_table_idx_tup_a = NULL;
-+	u8 *delta_swing_table_idx_tdown_a = NULL;
-+	u8 *delta_swing_table_idx_tup_b = NULL;
-+	u8 *delta_swing_table_idx_tdown_b = NULL;
-+#if (RTL8721D_SUPPORT == 1)
-+	u8 *delta_swing_table_idx_tup_a_cck = NULL;
-+	u8 *delta_swing_table_idx_tdown_a_cck = NULL;
-+	u8 *delta_swing_table_idx_tup_b_cck = NULL;
-+	u8 *delta_swing_table_idx_tdown_b_cck = NULL;
-+#endif
-+	/*for Xtal Offset by James.Tung*/
-+	s8 *delta_swing_table_xtal_up = NULL;
-+	s8 *delta_swing_table_xtal_down = NULL;
-+
-+	/* 4 2. Initialization ( 7 steps in total ) */
-+	indexforchannel = odm_get_right_chnl_place_for_iqk(*dm->channel);
-+	configure_txpower_track(dm, &c);
-+#if (RTL8721D_SUPPORT == 1)
-+	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
-+		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b,
-+		(u8 **)&delta_swing_table_idx_tup_a_cck, (u8 **)&delta_swing_table_idx_tdown_a_cck,
-+		(u8 **)&delta_swing_table_idx_tup_b_cck, (u8 **)&delta_swing_table_idx_tdown_b_cck);
-+#else
-+	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
-+		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
-+#endif
-+
-+	/*for Xtal Offset*/
-+	odm_efuse_one_byte_read(dm, 0xf7, &xtal_track_efuse, false);
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Read efuse 0xf7=0x%x\n", xtal_track_efuse);
-+	xtal_track_efuse = xtal_track_efuse & 0x3;
-+	if (dm->support_ic_type == ODM_RTL8195B ||
-+	    dm->support_ic_type == ODM_RTL8721D ||
-+	    (dm->support_ic_type == ODM_RTL8710C && xtal_track_efuse == 0x2))
-+		(*c.get_delta_swing_xtal_table)(dm,
-+		 (s8 **)&delta_swing_table_xtal_up,
-+		 (s8 **)&delta_swing_table_xtal_down);
-+
-+	cali_info->txpowertracking_callback_cnt++;	/*cosa add for debug*/
-+	cali_info->is_txpowertracking_init = true;
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+	       "===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
-+	       cali_info->bb_swing_idx_cck_base,
-+	       cali_info->bb_swing_idx_ofdm_base[RF_PATH_A],
-+	       cali_info->default_ofdm_index);
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+	       "cali_info->txpowertrack_control = %d, hal_data->eeprom_thermal_meter %d\n",
-+	       cali_info->txpowertrack_control, rf->eeprom_thermal);
-+
-+	if (dm->support_ic_type == ODM_RTL8721D
-+		|| dm->support_ic_type == ODM_RTL8710C)
-+		thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A,
-+						   c.thermal_reg_addr, 0x7e0);
-+		/* 0x42: RF Reg[10:5] 8721D */
-+	else
-+		thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A,
-+						   c.thermal_reg_addr, 0xfc00);
-+		/* 0x42: RF Reg[15:10] 88E */
-+
-+	thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+	       "thermal_value_temp(%d) = thermal_value(%d) + power_trim_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
-+
-+	if (thermal_value_temp > 63)
-+		thermal_value = 63;
-+	else if (thermal_value_temp < 0)
-+		thermal_value = 0;
-+	else
-+		thermal_value = thermal_value_temp;
-+
-+	if (!cali_info->txpowertrack_control)
-+		return;
-+
-+	if (rf->eeprom_thermal == 0xff) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", rf->eeprom_thermal);
-+		return;
-+	}
-+#if 0
-+	/*4 3. Initialize ThermalValues of rf_calibrate_info*/
-+	//if (cali_info->is_reloadtxpowerindex)
-+	//	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
-+#endif
-+	/*4 4. Calculate average thermal meter*/
-+
-+	cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value;
-+	cali_info->thermal_value_avg_index++;
-+	if (cali_info->thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
-+		cali_info->thermal_value_avg_index = 0;
-+
-+	for (i = 0; i < c.average_thermal_num; i++) {
-+		if (cali_info->thermal_value_avg[i]) {
-+			thermal_value_avg += cali_info->thermal_value_avg[i];
-+			thermal_value_avg_count++;
-+		}
-+	}
-+
-+	if (thermal_value_avg_count) {			  /* Calculate Average thermal_value after average enough times */
-+		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
-+		cali_info->thermal_value_delta = thermal_value - rf->eeprom_thermal;
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, rf->eeprom_thermal);
-+	}
-+
-+	/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
-+	/* "delta" here is used to determine whether thermal value changes or not. */
-+	delta	= (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value);
-+	delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
-+	delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
-+
-+	/*4 6. If necessary, do LCK.*/
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
-+
-+	/* Wait sacn to do LCK by RF Jenyu*/
-+	if ((!*dm->is_scan_in_process) && !iqk_info->rfk_forbidden &&
-+	    (!*dm->is_tdma)) {
-+		/* Delta temperature is equal to or larger than 20 centigrade.*/
-+		if (delta_LCK >= c.threshold_iqk) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
-+			cali_info->thermal_value_lck = thermal_value;
-+
-+			/*Use RTLCK, so close power tracking driver LCK*/
-+			(*c.phy_lc_calibrate)(dm);
-+		}
-+	}
-+
-+	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
-+	if (delta > 0 && cali_info->txpowertrack_control) {
-+		/* "delta" here is used to record the absolute value of difference. */
-+		delta = thermal_value > rf->eeprom_thermal ? (thermal_value - rf->eeprom_thermal) : (rf->eeprom_thermal - thermal_value);
-+
-+		if (delta >= TXPWR_TRACK_TABLE_SIZE)
-+			delta = TXPWR_TRACK_TABLE_SIZE - 1;
-+
-+		/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
-+		if (thermal_value > rf->eeprom_thermal) {
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+				cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
-+				switch (p) {
-+				case RF_PATH_B:
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
-+#if (RTL8721D_SUPPORT == 1)
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "delta_swing_table_idx_tup_b_cck[%d] = %d\n", delta, delta_swing_table_idx_tup_b_cck[delta]);
-+
-+					cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_b_cck[delta];
-+
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "******Temp is higher and cali_info->absolute_cck_swing_idx[RF_PATH_B] = %d\n",
-+					       cali_info->absolute_cck_swing_idx[p]);
-+#endif
-+					cali_info->delta_power_index[p] =
-+						delta_swing_table_idx_tup_b
-+						[delta];
-+					cali_info->absolute_ofdm_swing_idx[p] =
-+						delta_swing_table_idx_tup_b
-+						[delta];
-+					/*Record delta swing for mix mode*/
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+					break;
-+
-+				default:
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
-+#if (RTL8721D_SUPPORT == 1)
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "delta_swing_table_idx_tup_a_cck[%d] = %d\n", delta, delta_swing_table_idx_tup_a_cck[delta]);
-+
-+					cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_a_cck[delta];
-+
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "******Temp is higher and cali_info->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_cck_swing_idx[p]);
-+#endif
-+					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
-+					cali_info->absolute_ofdm_swing_idx[p] =
-+					delta_swing_table_idx_tup_a[delta];
-+					/*Record delta swing*/
-+					/*for mix mode power tracking*/
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+					break;
-+				}
-+			}
-+			/* JJ ADD 20161014 */
-+			if (dm->support_ic_type == ODM_RTL8195B ||
-+			    dm->support_ic_type == ODM_RTL8721D ||
-+			    (dm->support_ic_type == ODM_RTL8710C && xtal_track_efuse == 0x2)) {
-+				/*Save xtal_offset from Xtal table*/
-+				cali_info->xtal_offset_last = cali_info->xtal_offset;	/*recording last Xtal offset*/
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]);
-+				cali_info->xtal_offset = delta_swing_table_xtal_up[delta];
-+				xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);
-+			}
-+
-+		} else {
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+				cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
-+
-+				switch (p) {
-+				case RF_PATH_B:
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
-+#if (RTL8721D_SUPPORT == 1)
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "delta_swing_table_idx_tdown_b_cck[%d] = %d\n", delta, delta_swing_table_idx_tdown_b_cck[delta]);
-+
-+					cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b_cck[delta];
-+
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "******Temp is lower and cali_info->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_cck_swing_idx[p]);
-+#endif
-+					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
-+					cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+					break;
-+
-+				default:
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
-+#if (RTL8721D_SUPPORT == 1)
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "delta_swing_table_idx_tdown_a_cck[%d] = %d\n", delta, delta_swing_table_idx_tdown_a_cck[delta]);
-+
-+					cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a_cck[delta];
-+
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "******Temp is lower and cali_info->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_cck_swing_idx[p]);
-+#endif
-+					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
-+					cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					       "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+					break;
-+				}
-+			}
-+			/* JJ ADD 20161014 */
-+
-+			if (dm->support_ic_type == ODM_RTL8195B ||
-+			    dm->support_ic_type == ODM_RTL8721D ||
-+			    (dm->support_ic_type == ODM_RTL8710C && xtal_track_efuse == 0x2)) {
-+				/*Save xtal_offset from Xtal table*/
-+				cali_info->xtal_offset_last = cali_info->xtal_offset;	/*recording last Xtal offset*/
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]);
-+				cali_info->xtal_offset = delta_swing_table_xtal_down[delta];
-+				xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);
-+			}
-+		}
-+#if 0
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p);
-+
-+			if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p])		 /*If Thermal value changes but lookup table value still the same*/
-+				cali_info->power_index_offset[p] = 0;
-+			else
-+				cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p];		/*Power index diff between 2 times Power Tracking*/
-+
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);
-+
-+			cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
-+			cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
-+
-+			cali_info->bb_swing_idx_cck = cali_info->CCK_index;
-+			cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
-+
-+			/*************Print BB Swing base and index Offset*************/
-+
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);
-+
-+			/*4 7.1 Handle boundary conditions of index.*/
-+
-+			if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
-+				cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
-+			else if (cali_info->OFDM_index[p] <= OFDM_min_index)
-+				cali_info->OFDM_index[p] = OFDM_min_index;
-+		}
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "\n\n========================================================================================================\n");
-+
-+		if (cali_info->CCK_index > c.swing_table_size_cck - 1)
-+			cali_info->CCK_index = c.swing_table_size_cck - 1;
-+		else if (cali_info->CCK_index <= 0)
-+			cali_info->CCK_index = 0;
-+#endif
-+	} else {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
-+		       cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);
-+
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			cali_info->power_index_offset[p] = 0;
-+	}
-+#if 0
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+	       "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
-+	       cali_info->CCK_index, cali_info->bb_swing_idx_cck_base);	   /*Print Swing base & current*/
-+
-+	for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
-+		       cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
-+	}
-+#endif
-+
-+#if (RTL8721D_SUPPORT == 1)
-+	if (thermal_value != cali_info->thermal_value) {
-+		if (thermal_value > rf->eeprom_thermal)
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "Temperature(%d) higher than PG value(%d)\n",
-+			       thermal_value, rf->eeprom_thermal);
-+		else if (thermal_value < rf->eeprom_thermal)
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "Temperature(%d) lower than PG value(%d)\n",
-+			       thermal_value, rf->eeprom_thermal);
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "**********Enter POWER Tracking MIX_MODE**********\n");
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p,
-+						      indexforchannel);
-+
-+		/*Record last time Power Tracking result as base.*/
-+		cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			cali_info->bb_swing_idx_ofdm_base[p] =
-+			cali_info->bb_swing_idx_ofdm[p];
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "cali_info->thermal_value = %d thermal_value= %d\n",
-+		       cali_info->thermal_value, thermal_value);
-+		/*Record last Power Tracking Thermal value*/
-+		cali_info->thermal_value = thermal_value;
-+	}
-+
-+#else
-+	if (thermal_value > rf->eeprom_thermal) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "Temperature(%d) higher than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
-+
-+		if (dm->support_ic_type == ODM_RTL8188E ||
-+		    dm->support_ic_type == ODM_RTL8192E ||
-+		    dm->support_ic_type == ODM_RTL8821 ||
-+		    dm->support_ic_type == ODM_RTL8812 ||
-+		    dm->support_ic_type == ODM_RTL8723B ||
-+		    dm->support_ic_type == ODM_RTL8814A ||
-+		    dm->support_ic_type == ODM_RTL8703B ||
-+		    dm->support_ic_type == ODM_RTL8188F ||
-+		    dm->support_ic_type == ODM_RTL8822B ||
-+		    dm->support_ic_type == ODM_RTL8723D ||
-+		    dm->support_ic_type == ODM_RTL8821C ||
-+		    dm->support_ic_type == ODM_RTL8710B ||
-+		    dm->support_ic_type == ODM_RTL8192F ||
-+		    dm->support_ic_type == ODM_RTL8195B ||
-+		    dm->support_ic_type == ODM_RTL8710C){
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+		} else {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+				(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
-+		}
-+	} else {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "Temperature(%d) lower than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
-+
-+		if (dm->support_ic_type == ODM_RTL8188E ||
-+		    dm->support_ic_type == ODM_RTL8192E ||
-+		    dm->support_ic_type == ODM_RTL8821 ||
-+		    dm->support_ic_type == ODM_RTL8812 ||
-+		    dm->support_ic_type == ODM_RTL8723B ||
-+		    dm->support_ic_type == ODM_RTL8814A ||
-+		    dm->support_ic_type == ODM_RTL8703B ||
-+		    dm->support_ic_type == ODM_RTL8188F ||
-+		    dm->support_ic_type == ODM_RTL8822B ||
-+		    dm->support_ic_type == ODM_RTL8723D ||
-+		    dm->support_ic_type == ODM_RTL8821C ||
-+		    dm->support_ic_type == ODM_RTL8710B ||
-+		    dm->support_ic_type == ODM_RTL8192F ||
-+		    dm->support_ic_type == ODM_RTL8195B ||
-+		    dm->support_ic_type == ODM_RTL8710C) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
-+		} else {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+				(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
-+		}
-+
-+		cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;    /*Record last time Power Tracking result as base.*/
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value);
-+
-+		cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
-+	}
-+#endif
-+	/* JJ ADD 20161014 */
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			"cali_info->xtal_offset_last=%d   cali_info->xtal_offset=%d\n",
-+			cali_info->xtal_offset_last, cali_info->xtal_offset);
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			"xtal_offset_eanble=%d   cali_info->txpowertrack_control=%d   rf->eeprom_thermal=%d xtal_track_efuse=%d\n",
-+			xtal_offset_eanble, cali_info->txpowertrack_control, rf->eeprom_thermal, xtal_track_efuse);
-+
-+	if (dm->support_ic_type == ODM_RTL8195B ||
-+	    dm->support_ic_type == ODM_RTL8721D ||
-+	    (dm->support_ic_type == ODM_RTL8710C && xtal_track_efuse == 0x2)) {
-+		if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (rf->eeprom_thermal != 0xff)) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
-+
-+			if (thermal_value > rf->eeprom_thermal) {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "Temperature(%d) higher than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
-+				(*c.odm_txxtaltrack_set_xtal)(dm);
-+			} else {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       "Temperature(%d) lower than PG value(%d)\n", thermal_value, rf->eeprom_thermal);
-+				(*c.odm_txxtaltrack_set_xtal)(dm);
-+			}
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
-+		}
-+	}
-+#if (!RTL8721D_SUPPORT)
-+	/* Wait sacn to do IQK by RF Jenyu*/
-+	if ((!*dm->is_scan_in_process) && (!iqk_info->rfk_forbidden) && (dm->is_linked || *dm->mp_mode)) {
-+		/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
-+		if (delta_IQK >= c.threshold_iqk) {
-+			cali_info->thermal_value_iqk = thermal_value;
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
-+			if (!cali_info->is_iqk_in_progress)
-+				(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
-+		}
-+	}
-+#endif
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
-+
-+	cali_info->tx_powercount = 0;
-+}
-+
-+/* 3============================================================
-+ * 3 IQ Calibration
-+ * 3============================================================
-+ */
-+
-+void
-+odm_reset_iqk_result(
-+	void					*dm_void
-+)
-+{
-+	return;
-+}
-+
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
-+{
-+	u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
-+		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
-+		36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,
-+		100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,
-+		124, 126, 128, 130, 132, 134, 136, 138, 140,
-+		149, 151, 153, 155, 157, 159, 161, 163, 165};
-+	u8 place = chnl;
-+
-+	if (chnl > 14) {
-+		for (place = 14; place < sizeof(channel_all); place++) {
-+			if (channel_all[place] == chnl)
-+				return place - 13;
-+		}
-+	}
-+	return 0;
-+}
-+#endif
-+
-+void
-+odm_rf_calibrate(struct dm_struct *dm)
-+{
-+#if (RTL8721D_SUPPORT == 1)
-+	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
-+
-+	if (dm->is_linked && !iqk_info->rfk_forbidden) {
-+		if ((*dm->channel != dm->pre_channel) &&
-+		    (!*dm->is_scan_in_process)) {
-+			dm->pre_channel = *dm->channel;
-+			dm->linked_interval = 0;
-+		}
-+
-+		if (dm->linked_interval < 3)
-+			dm->linked_interval++;
-+
-+		if (dm->linked_interval == 2)
-+			halrf_rf_k_connect_trigger(dm, 0, SEGMENT_FREE);
-+	} else {
-+		dm->linked_interval = 0;
-+	}
-+#endif
-+}
-+
-+void phydm_rf_init(void		*dm_void)
-+{
-+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
-+
-+	odm_txpowertracking_init(dm);
-+	
-+	odm_clear_txpowertracking_state(dm);
-+}
-+
-+void phydm_rf_watchdog(void		*dm_void)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+
-+	odm_txpowertracking_check(dm);
-+#if (RTL8721D_SUPPORT == 1)
-+	odm_rf_calibrate(dm);
-+#endif
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_iot.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_iot.h
-new file mode 100644
-index 000000000000..8d4395a1f74d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_iot.h
-@@ -0,0 +1,137 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALPHYRF_H__
-+#define __HALPHYRF_H__
-+
-+#include "halrf/halrf_kfree.h"
-+
-+#if (RTL8821C_SUPPORT == 1)
-+	#include "halrf/rtl8821c/halrf_iqk_8821c.h"
-+#endif
-+
-+#if (RTL8195B_SUPPORT == 1)
-+//	#include "halrf/rtl8195b/halrf.h"
-+	#include "halrf/rtl8195b/halrf_iqk_8195b.h"
-+	#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
-+	#include "halrf/rtl8195b/halrf_dpk_8195b.h"
-+#endif
-+
-+#if (RTL8710C_SUPPORT == 1)
-+//	#include "halrf/rtl8710c/halrf.h"
-+	#include "halrf/rtl8710c/halrf_iqk_8710c.h"
-+//	#include "halrf/rtl8710c/halrf_txgapk_8710c.h"
-+//	#include "halrf/rtl8710c/halrf_dpk_8710c.h"
-+#endif
-+
-+#include "halrf/halrf_powertracking_iot.h"
-+
-+
-+enum spur_cal_method {
-+	PLL_RESET,
-+	AFE_PHASE_SEL
-+};
-+
-+enum pwrtrack_method {
-+	BBSWING,
-+	TXAGC,
-+	MIX_MODE,
-+	TSSI_MODE,
-+	MIX_2G_TSSI_5G_MODE,
-+	MIX_5G_TSSI_2G_MODE,
-+	CLEAN_MODE
-+};
-+
-+typedef void	(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
-+typedef void(*func_iqk)(void *, u8, u8, u8);
-+typedef void	(*func_lck)(void *);
-+#if (RTL8721D_SUPPORT == 1)
-+	typedef void	(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **,
-+				      u8 **, u8 **, u8 **, u8 **);
-+#else
-+	typedef void	(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
-+#endif
-+typedef void	(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
-+typedef void(*func_swing_xtal)(void *, s8 **, s8 **);
-+typedef void(*func_set_xtal)(void *);
-+
-+struct txpwrtrack_cfg {
-+	u8		swing_table_size_cck;
-+	u8		swing_table_size_ofdm;
-+	u8		threshold_iqk;
-+	u8		threshold_dpk;
-+	u8		average_thermal_num;
-+	u8		rf_path_count;
-+	u32		thermal_reg_addr;
-+	func_set_pwr	odm_tx_pwr_track_set_pwr;
-+	func_iqk	do_iqk;
-+	func_lck		phy_lc_calibrate;
-+	func_swing	get_delta_swing_table;
-+	func_swing8814only	get_delta_swing_table8814only;
-+	func_swing_xtal			get_delta_swing_xtal_table;
-+	func_set_xtal			odm_txxtaltrack_set_xtal;
-+};
-+
-+void
-+configure_txpower_track(
-+	void					*dm_void,
-+	struct txpwrtrack_cfg	*config
-+);
-+
-+
-+void
-+odm_clear_txpowertracking_state(
-+	void					*dm_void
-+);
-+
-+void
-+odm_txpowertracking_callback_thermal_meter(
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	void					*dm_void
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	void	*dm
-+#else
-+	void	*adapter
-+#endif
-+);
-+
-+
-+
-+#define ODM_TARGET_CHNL_NUM_2G_5G	59
-+
-+
-+void
-+odm_reset_iqk_result(
-+	void					*dm_void
-+);
-+u8
-+odm_get_right_chnl_place_for_iqk(
-+	u8 chnl
-+);
-+
-+void phydm_rf_init(void					*dm_void);
-+void phydm_rf_watchdog(void					*dm_void);
-+
-+#endif	/*#ifndef __HALPHYRF_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_win.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_win.c
-new file mode 100644
-index 000000000000..679d5e094da0
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_win.c
-@@ -0,0 +1,1108 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#define	CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
-+	do {\
-+		for (_offset = 0; _offset < _size; _offset++) { \
-+			\
-+			if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
-+				\
-+				if (_offset != 0)\
-+					_offset--;\
-+				break;\
-+			} \
-+		}			\
-+		if (_offset >= _size)\
-+			_offset = _size-1;\
-+	} while (0)
-+
-+void configure_txpower_track(
-+	struct dm_struct		*dm,
-+	struct txpwrtrack_cfg	*config
-+)
-+{
-+#if RTL8192E_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8192E)
-+		configure_txpower_track_8192e(config);
-+#endif
-+#if RTL8821A_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8821)
-+		configure_txpower_track_8821a(config);
-+#endif
-+#if RTL8812A_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8812)
-+		configure_txpower_track_8812a(config);
-+#endif
-+#if RTL8188E_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8188E)
-+		configure_txpower_track_8188e(config);
-+#endif
-+
-+#if RTL8188F_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8188F)
-+		configure_txpower_track_8188f(config);
-+#endif
-+
-+#if RTL8723B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8723B)
-+		configure_txpower_track_8723b(config);
-+#endif
-+
-+#if RTL8814A_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8814A)
-+		configure_txpower_track_8814a(config);
-+#endif
-+
-+#if RTL8703B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8703B)
-+		configure_txpower_track_8703b(config);
-+#endif
-+
-+#if RTL8822B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8822B)
-+		configure_txpower_track_8822b(config);
-+#endif
-+
-+#if RTL8723D_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8723D)
-+		configure_txpower_track_8723d(config);
-+#endif
-+
-+/* JJ ADD 20161014 */
-+#if RTL8710B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8710B)
-+		configure_txpower_track_8710b(config);
-+#endif
-+
-+#if RTL8821C_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8821C)
-+		configure_txpower_track_8821c(config);
-+#endif
-+
-+#if RTL8192F_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8192F)
-+		configure_txpower_track_8192f(config);
-+#endif
-+
-+#if RTL8822C_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8822C)
-+		configure_txpower_track_8822c(config);
-+#endif
-+
-+#if RTL8814B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8814B)
-+		configure_txpower_track_8814b(config);
-+#endif
-+
-+#if RTL8723F_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8723F)
-+		configure_txpower_track_8723f(config);
-+#endif
-+
-+}
-+
-+/* **********************************************************************
-+ * <20121113, Kordan> This function should be called when tx_agc changed.
-+ * Otherwise the previous compensation is gone, because we record the
-+ * delta of temperature between two TxPowerTracking watch dogs.
-+ *
-+ * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
-+ * need to call this function.
-+ * ********************************************************************** */
-+void
-+odm_clear_txpowertracking_state(
-+	struct dm_struct		*dm
-+)
-+{
-+	PHAL_DATA_TYPE	hal_data = GET_HAL_DATA((PADAPTER)(dm->adapter));
-+	u8			p = 0;
-+	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
-+
-+	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
-+	cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
-+	cali_info->CCK_index = 0;
-+
-+	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
-+		cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
-+		cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
-+		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
-+
-+		cali_info->power_index_offset[p] = 0;
-+		cali_info->delta_power_index[p] = 0;
-+		cali_info->delta_power_index_last[p] = 0;
-+
-+		cali_info->absolute_ofdm_swing_idx[p] = 0;    /* Initial Mix mode power tracking*/
-+		cali_info->remnant_ofdm_swing_idx[p] = 0;
-+		cali_info->kfree_offset[p] = 0;
-+	}
-+
-+	cali_info->modify_tx_agc_flag_path_a = false;       /*Initial at Modify Tx Scaling mode*/
-+	cali_info->modify_tx_agc_flag_path_b = false;       /*Initial at Modify Tx Scaling mode*/
-+	cali_info->modify_tx_agc_flag_path_c = false;       /*Initial at Modify Tx Scaling mode*/
-+	cali_info->modify_tx_agc_flag_path_d = false;       /*Initial at Modify Tx Scaling mode*/
-+	cali_info->remnant_cck_swing_idx = 0;
-+	cali_info->thermal_value = hal_data->eeprom_thermal_meter;
-+
-+	cali_info->modify_tx_agc_value_cck = 0;			/* modify by Mingzhi.Guo */
-+	cali_info->modify_tx_agc_value_ofdm = 0;		/* modify by Mingzhi.Guo */
-+
-+}
-+
-+void
-+odm_txpowertracking_callback_thermal_meter(
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	struct dm_struct		*dm
-+#else
-+	void	*adapter
-+#endif
-+)
-+{
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct dm_struct		*dm = &hal_data->DM_OutSrc;
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	struct dm_struct		*dm = &hal_data->odmpriv;
-+#endif
-+#endif
-+
-+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
-+ 	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+	u8			thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
-+	s8			diff_DPK[4] = {0};
-+	u8			thermal_value_avg_count = 0;
-+	u32			thermal_value_avg = 0, regc80, regcd0, regcd4, regab4, regc88, rege14, reg848,reg838, reg86c;
-+
-+	u8			OFDM_min_index = 0;  /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
-+	u8			indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
-+	u8			power_tracking_type = hal_data->RfPowerTrackingType;
-+	u8			xtal_offset_eanble = 0;
-+	s8			thermal_value_temp = 0;
-+
-+	struct txpwrtrack_cfg	c;
-+
-+	/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
-+	u8			*delta_swing_table_idx_tup_a = NULL;
-+	u8			*delta_swing_table_idx_tdown_a = NULL;
-+	u8			*delta_swing_table_idx_tup_b = NULL;
-+	u8			*delta_swing_table_idx_tdown_b = NULL;
-+	/*for 8814 add by Yu Chen*/
-+	u8			*delta_swing_table_idx_tup_c = NULL;
-+	u8			*delta_swing_table_idx_tdown_c = NULL;
-+	u8			*delta_swing_table_idx_tup_d = NULL;
-+	u8			*delta_swing_table_idx_tdown_d = NULL;
-+	/*for Xtal Offset by James.Tung*/
-+	s8			*delta_swing_table_xtal_up = NULL;
-+	s8			*delta_swing_table_xtal_down = NULL;
-+
-+	/* 4 2. Initilization ( 7 steps in total ) */
-+
-+	configure_txpower_track(dm, &c);
-+
-+	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
-+		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
-+
-+	if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8814B))	/*for 8814 path C & D*/
-+		(*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
-+			(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
-+	/* JJ ADD 20161014 */
-+	if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F))	/*for Xtal Offset*/
-+		(*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
-+
-+
-+	cali_info->txpowertracking_callback_cnt++;	/*cosa add for debug*/
-+	cali_info->is_txpowertracking_init = true;
-+
-+	/*cali_info->txpowertrack_control = hal_data->txpowertrack_control;
-+	<Kordan> We should keep updating the control variable according to HalData.
-+	<Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+#if (MP_DRIVER == 1)
-+	cali_info->rega24 = 0x090e1317;
-+#endif
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	if (*(dm->mp_mode) == true)
-+		cali_info->rega24 = 0x090e1317;
-+#endif
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
-+		cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		"cali_info->txpowertrack_control=%d,  hal_data->eeprom_thermal_meter %d\n", cali_info->txpowertrack_control,  hal_data->eeprom_thermal_meter);
-+	thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
-+
-+	thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		"thermal_value_temp(%d) = thermal_value(%d) + power_time_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
-+
-+	if (thermal_value_temp > 63)
-+		thermal_value = 63;
-+	else if (thermal_value_temp < 0)
-+		thermal_value = 0;
-+	else
-+		thermal_value = thermal_value_temp;
-+
-+	/*add log by zhao he, check c80/c94/c14/ca0 value*/
-+	if (dm->support_ic_type == ODM_RTL8723D) {
-+		regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
-+		regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
-+		regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
-+		regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);
-+		RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
-+	}
-+
-+	/* JJ ADD 20161014 */
-+	if (dm->support_ic_type == ODM_RTL8710B) {
-+		regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
-+		regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD);
-+		regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD);
-+		regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF);
-+		RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
-+	}
-+	/* Winnita add 20171205 */
-+	if (dm->support_ic_type == ODM_RTL8192F) {
-+		regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD);
-+		regc88 = odm_get_bb_reg(dm, R_0xc88, MASKDWORD);
-+		regab4 = odm_get_bb_reg(dm, R_0xab4, MASKDWORD);
-+		rege14 = odm_get_bb_reg(dm, R_0xe14, MASKDWORD);
-+		reg848 = odm_get_bb_reg(dm, R_0x848, MASKDWORD);
-+		reg838 = odm_get_bb_reg(dm, R_0x838, MASKDWORD);
-+		reg86c = odm_get_bb_reg(dm, R_0x86c, MASKDWORD);
-+		RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xc88 = 0x%x 0xab4 = 0x%x 0xe14 = 0x%x\n", regc80, regc88, regab4, rege14);
-+		RF_DBG(dm, DBG_RF_IQK, "0x848 = 0x%x 0x838 = 0x%x 0x86c = 0x%x\n", reg848, reg838, reg86c);
-+	}
-+
-+	if (!cali_info->txpowertrack_control)
-+		return;
-+
-+	if (hal_data->eeprom_thermal_meter == 0xff) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", hal_data->eeprom_thermal_meter);
-+		return;
-+	}
-+
-+	/*4 3. Initialize ThermalValues of rf_calibrate_info*/
-+
-+	if (cali_info->is_reloadtxpowerindex)
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n");
-+
-+	/*4 4. Calculate average thermal meter*/
-+
-+	cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value;
-+	cali_info->thermal_value_avg_index++;
-+	if (cali_info->thermal_value_avg_index == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
-+		cali_info->thermal_value_avg_index = 0;
-+
-+	for (i = 0; i < c.average_thermal_num; i++) {
-+		if (cali_info->thermal_value_avg[i]) {
-+			thermal_value_avg += cali_info->thermal_value_avg[i];
-+			thermal_value_avg_count++;
-+		}
-+	}
-+
-+	if (thermal_value_avg_count) {            /* Calculate Average thermal_value after average enough times */
-+		thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
-+		cali_info->thermal_value_delta = thermal_value - hal_data->eeprom_thermal_meter;
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			"AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, hal_data->eeprom_thermal_meter);
-+	}
-+
-+	/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
-+
-+	/* "delta" here is used to determine whether thermal value changes or not. */
-+	delta	= (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value);
-+	delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
-+	delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
-+
-+	if (cali_info->thermal_value_iqk == 0xff) {	/*no PG, use thermal value for IQK*/
-+		cali_info->thermal_value_iqk = thermal_value;
-+		delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no PG, use thermal_value for IQK\n");
-+	}
-+
-+	for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+		diff_DPK[p] = (s8)thermal_value - (s8)cali_info->dpk_thermal[p];
-+
-+	/*4 6. If necessary, do LCK.*/
-+
-+	if (!(dm->support_ic_type & ODM_RTL8821)) {	/*no PG, do LCK at initial status*/
-+		if (cali_info->thermal_value_lck == 0xff) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no PG, do LCK\n");
-+			cali_info->thermal_value_lck = thermal_value;
-+
-+			/*Use RTLCK, so close power tracking driver LCK*/
-+			if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
-+				if (c.phy_lc_calibrate)
-+					(*c.phy_lc_calibrate)(dm);
-+			}
-+
-+			delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
-+		}
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
-+
-+		/* Wait sacn to do LCK by RF Jenyu*/
-+		if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
-+			/* Delta temperature is equal to or larger than 20 centigrade.*/
-+			if (delta_LCK >= c.threshold_iqk) {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
-+				cali_info->thermal_value_lck = thermal_value;
-+
-+				/*Use RTLCK, so close power tracking driver LCK*/
-+				if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
-+					if (c.phy_lc_calibrate)
-+						(*c.phy_lc_calibrate)(dm);
-+				}
-+			}
-+		}
-+	}
-+
-+	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
-+
-+	if (delta > 0 && cali_info->txpowertrack_control) {
-+		/* "delta" here is used to record the absolute value of differrence. */
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+		delta = thermal_value > hal_data->eeprom_thermal_meter ? (thermal_value - hal_data->eeprom_thermal_meter) : (hal_data->eeprom_thermal_meter - thermal_value);
-+#else
-+		delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value);
-+#endif
-+		if (delta >= TXPWR_TRACK_TABLE_SIZE)
-+			delta = TXPWR_TRACK_TABLE_SIZE - 1;
-+
-+		/*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+		if (thermal_value > hal_data->eeprom_thermal_meter) {
-+#else
-+		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
-+#endif
-+
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+				cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p];	/*recording poer index offset*/
-+				switch (p) {
-+				case RF_PATH_B:
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
-+
-+					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
-+					cali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_b[delta];       /*Record delta swing for mix mode power tracking*/
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+					break;
-+
-+				case RF_PATH_C:
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
-+
-+					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];
-+					cali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_c[delta];       /*Record delta swing for mix mode power tracking*/
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+					break;
-+
-+				case RF_PATH_D:
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
-+
-+					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];
-+					cali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_d[delta];       /*Record delta swing for mix mode power tracking*/
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+					break;
-+
-+				default:
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
-+
-+					cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
-+					cali_info->absolute_ofdm_swing_idx[p] =  delta_swing_table_idx_tup_a[delta];        /*Record delta swing for mix mode power tracking*/
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+					break;
-+				}
-+			}
-+			/* JJ ADD 20161014 */
-+			if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) {
-+				/*Save xtal_offset from Xtal table*/
-+				cali_info->xtal_offset_last = cali_info->xtal_offset;	/*recording last Xtal offset*/
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					"[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]);
-+				cali_info->xtal_offset = delta_swing_table_xtal_up[delta];
-+
-+				if (cali_info->xtal_offset_last == cali_info->xtal_offset)
-+					xtal_offset_eanble = 0;
-+				else
-+					xtal_offset_eanble = 1;
-+			}
-+
-+		} else {
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+				cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p];	/*recording poer index offset*/
-+
-+				switch (p) {
-+				case RF_PATH_B:
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
-+					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
-+					cali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_b[delta];        /*Record delta swing for mix mode power tracking*/
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+					break;
-+
-+				case RF_PATH_C:
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
-+					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];
-+					cali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_c[delta];        /*Record delta swing for mix mode power tracking*/
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+					break;
-+
-+				case RF_PATH_D:
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
-+					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];
-+					cali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_d[delta];        /*Record delta swing for mix mode power tracking*/
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+					break;
-+
-+				default:
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
-+					cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
-+					cali_info->absolute_ofdm_swing_idx[p] =  -1 * delta_swing_table_idx_tdown_a[delta];        /*Record delta swing for mix mode power tracking*/
-+					RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+						"******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
-+					break;
-+				}
-+			}
-+			/* JJ ADD 20161014 */
-+			if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) {
-+				/*Save xtal_offset from Xtal table*/
-+				cali_info->xtal_offset_last = cali_info->xtal_offset;	/*recording last Xtal offset*/
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					"[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]);
-+				cali_info->xtal_offset = delta_swing_table_xtal_down[delta];
-+
-+				if (cali_info->xtal_offset_last == cali_info->xtal_offset)
-+					xtal_offset_eanble = 0;
-+				else
-+					xtal_offset_eanble = 1;
-+			}
-+
-+		}
-+
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p);
-+
-+			if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p])         /*If Thermal value changes but lookup table value still the same*/
-+				cali_info->power_index_offset[p] = 0;
-+			else
-+				cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p];      /*Power index diff between 2 times Power Tracking*/
-+
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);
-+
-+			cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
-+			cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
-+
-+			cali_info->bb_swing_idx_cck = cali_info->CCK_index;
-+			cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
-+
-+			/*************Print BB Swing base and index Offset*************/
-+
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);
-+
-+			/*4 7.1 Handle boundary conditions of index.*/
-+
-+			if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
-+				cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
-+			else if (cali_info->OFDM_index[p] <= OFDM_min_index)
-+				cali_info->OFDM_index[p] = OFDM_min_index;
-+		}
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			"\n\n========================================================================================================\n");
-+
-+		if (cali_info->CCK_index > c.swing_table_size_cck - 1)
-+			cali_info->CCK_index = c.swing_table_size_cck - 1;
-+		else if (cali_info->CCK_index <= 0)
-+			cali_info->CCK_index = 0;
-+	} else {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			"The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
-+			cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);
-+
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			cali_info->power_index_offset[p] = 0;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
-+		cali_info->CCK_index, cali_info->bb_swing_idx_cck_base);       /*Print Swing base & current*/
-+
-+	for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
-+			cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
-+	}
-+
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		power_tracking_type = TSSI_MODE;
-+
-+	if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8814B)) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type);
-+
-+		if (power_tracking_type == 0) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+		} else if (power_tracking_type == 1) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n");
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_2G_TSSI_5G_MODE, p, 0);
-+		} else if (power_tracking_type == 2) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n");
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+				(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_5G_TSSI_2G_MODE, p, 0);
-+		} else if (power_tracking_type == 3) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI MODE**********\n");
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+				(*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
-+		}
-+		cali_info->thermal_value = thermal_value;         /*Record last Power Tracking Thermal value*/
-+
-+	} else if ((cali_info->power_index_offset[RF_PATH_A] != 0 ||
-+		cali_info->power_index_offset[RF_PATH_B] != 0 ||
-+		cali_info->power_index_offset[RF_PATH_C] != 0 ||
-+		cali_info->power_index_offset[RF_PATH_D] != 0) &&
-+		cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
-+		/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
-+
-+		cali_info->is_tx_power_changed = true;	/*Always true after Tx Power is adjusted by power tracking.*/
-+		/*  */
-+		/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
-+		/* to increase TX power. Otherwise, EVM will be bad. */
-+		/*  */
-+		/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
-+		if (thermal_value > cali_info->thermal_value) {
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					"Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
-+					p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
-+			}
-+		} else if (thermal_value < cali_info->thermal_value) {	/*Low temperature*/
-+			for (p = RF_PATH_A; p < c.rf_path_count; p++) {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					"Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
-+					p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
-+			}
-+		}
-+
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+		if (thermal_value > hal_data->eeprom_thermal_meter)
-+#else
-+		if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
-+#endif
-+		{
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
-+
-+			if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
-+			    dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
-+			    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
-+			    dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B ||
-+			    dm->support_ic_type == ODM_RTL8192F) {
-+
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
-+				for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+					(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+			} else {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
-+				for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+					(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
-+			}
-+		} else {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
-+
-+			if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
-+			    dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
-+			    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
-+			    dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B ||
-+				dm->support_ic_type == ODM_RTL8192F) {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
-+				for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+					(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
-+			} else {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
-+				for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+					(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
-+			}
-+
-+		}
-+
-+		cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;    /*Record last time Power Tracking result as base.*/
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			"cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value);
-+
-+		cali_info->thermal_value = thermal_value;         /*Record last Power Tracking Thermal value*/
-+
-+	}
-+
-+
-+	if (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D ||
-+		dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
-+
-+		if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
-+
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
-+
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+			if (thermal_value > hal_data->eeprom_thermal_meter) {
-+#else
-+			if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
-+#endif
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					"Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
-+				(*c.odm_txxtaltrack_set_xtal)(dm);
-+			} else {
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					"Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
-+				(*c.odm_txxtaltrack_set_xtal)(dm);
-+			}
-+		}
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
-+	}
-+
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+
-+	/* Wait sacn to do IQK by RF Jenyu*/
-+	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden) && dm->is_linked) {
-+		if (!IS_HARDWARE_TYPE_8723B(adapter)) {
-+			/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
-+			if (delta_IQK >= c.threshold_iqk) {
-+				cali_info->thermal_value_iqk = thermal_value;
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
-+				if (!cali_info->is_iqk_in_progress)
-+					(*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
-+			}
-+		}
-+	}
-+	if (cali_info->dpk_thermal[RF_PATH_A] != 0) {
-+		if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) {
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
-+			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
-+		} else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) {
-+			s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk);
-+
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
-+			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
-+		} else {
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
-+			odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
-+		}
-+	}
-+	if (cali_info->dpk_thermal[RF_PATH_B] != 0) {
-+		if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) {
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
-+			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
-+		} else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) {
-+			s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk);
-+
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
-+			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
-+		} else {
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1);
-+			odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
-+			odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0);
-+		}
-+	}
-+
-+#endif
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
-+
-+	cali_info->tx_powercount = 0;
-+}
-+
-+#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-+void
-+odm_txpowertracking_new_callback_thermal_meter(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
-+ 	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
-+	u8 thermal_value[MAX_RF_PATH] = {0}, delta[MAX_RF_PATH] = {0};
-+	u8 delta_swing_table_idx_tup[DELTA_SWINGIDX_SIZE] = {0};
-+	u8 delta_swing_table_idx_tdown[DELTA_SWINGIDX_SIZE] = {0};
-+	u8 delta_LCK = 0, delta_IQK = 0, i = 0, j = 0, p;
-+	u8 thermal_value_avg_count[MAX_RF_PATH] = {0};
-+	u32 thermal_value_avg[MAX_RF_PATH] = {0};
-+	s8 thermal_value_temp[MAX_RF_PATH] = {0};
-+	u8 tracking_method = MIX_MODE;
-+
-+	struct txpwrtrack_cfg c;
-+
-+	u8 *delta_swing_table_idx_tup_a = NULL;
-+	u8 *delta_swing_table_idx_tdown_a = NULL;
-+	u8 *delta_swing_table_idx_tup_b = NULL;
-+	u8 *delta_swing_table_idx_tdown_b = NULL;
-+	u8 *delta_swing_table_idx_tup_c = NULL;
-+	u8 *delta_swing_table_idx_tdown_c = NULL;
-+	u8 *delta_swing_table_idx_tup_d = NULL;
-+	u8 *delta_swing_table_idx_tdown_d = NULL;
-+
-+	configure_txpower_track(dm, &c);
-+
-+	(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
-+		(u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
-+
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		(*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
-+			(u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
-+	}
-+
-+	cali_info->txpowertracking_callback_cnt++;
-+	cali_info->is_txpowertracking_init = true;
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		"===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
-+		cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		"cali_info->txpowertrack_control=%d, tssi->thermal[RF_PATH_A]=%d tssi->thermal[RF_PATH_B]=%d\n",
-+		cali_info->txpowertrack_control,  tssi->thermal[RF_PATH_A], tssi->thermal[RF_PATH_B]);
-+
-+	if (dm->support_ic_type == ODM_RTL8822C) {
-+		for (i = 0; i < c.rf_path_count; i++)
-+			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0x7e);	/* 0x42: RF Reg[6:1] Thermal Trim*/
-+	} else {
-+		for (i = 0; i < c.rf_path_count; i++) {
-+			thermal_value[i] = (u8)odm_get_rf_reg(dm, i, c.thermal_reg_addr, 0xfc00);	/* 0x42: RF Reg[15:10] 88E */
-+
-+			if (dm->support_ic_type == ODM_RTL8814B) {
-+				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_multi_thermal_offset(dm, i);
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + multi_thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_multi_thermal_offset(dm, i));
-+			} else {
-+				thermal_value_temp[i] = (s8)thermal_value[i] + phydm_get_thermal_offset(dm);
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+					"thermal_value_temp[%d](%d) = thermal_value[%d](%d) + thermal_trim(%d)\n", i, thermal_value_temp[i], i, thermal_value[i], phydm_get_thermal_offset(dm));
-+			}
-+
-+			if (thermal_value_temp[i] > 63)
-+				thermal_value[i] = 63;
-+			else if (thermal_value_temp[i] < 0)
-+				thermal_value[i] = 0;
-+			else
-+				thermal_value[i] = thermal_value_temp[i];
-+		}
-+	}
-+
-+	if ((tssi->thermal[RF_PATH_A] == 0xff || tssi->thermal[RF_PATH_B] == 0xff)) {
-+		for (i = 0; i < c.rf_path_count; i++)
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, tssi->thermal[%d] = 0x%x\n",
-+				i, tssi->thermal[i]);
-+		return;
-+	}
-+
-+	for (j = 0; j < c.rf_path_count; j++) {
-+		cali_info->thermal_value_avg_path[j][cali_info->thermal_value_avg_index_path[j]] = thermal_value[j];
-+		cali_info->thermal_value_avg_index_path[j]++;
-+		if (cali_info->thermal_value_avg_index_path[j] == c.average_thermal_num)   /*Average times =  c.average_thermal_num*/
-+			cali_info->thermal_value_avg_index_path[j] = 0;
-+
-+
-+		for (i = 0; i < c.average_thermal_num; i++) {
-+			if (cali_info->thermal_value_avg_path[j][i]) {
-+				thermal_value_avg[j] += cali_info->thermal_value_avg_path[j][i];
-+				thermal_value_avg_count[j]++;
-+			}
-+		}
-+
-+		if (thermal_value_avg_count[j]) {            /* Calculate Average thermal_value after average enough times */
-+			thermal_value[j] = (u8)(thermal_value_avg[j] / thermal_value_avg_count[j]);
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"AVG Thermal Meter = 0x%X, tssi->thermal[%d] = 0x%x\n",
-+				thermal_value[j], j, tssi->thermal[j]);
-+		}
-+		/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
-+
-+		/* "delta" here is used to determine whether thermal value changes or not. */
-+		delta[j] = (thermal_value[j] > cali_info->thermal_value_path[j]) ? (thermal_value[j] - cali_info->thermal_value_path[j]) : (cali_info->thermal_value_path[j] - thermal_value[j]);
-+		delta_LCK = (thermal_value[0] > cali_info->thermal_value_lck) ? (thermal_value[0] - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value[0]);
-+		delta_IQK = (thermal_value[0] > cali_info->thermal_value_iqk) ? (thermal_value[0] - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value[0]);
-+	}
-+
-+	/*4 6. If necessary, do LCK.*/
-+
-+	for (i = 0; i < c.rf_path_count; i++)
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta[%d], delta_LCK, delta_IQK) = (%d, %d, %d)\n", i, delta[i], delta_LCK, delta_IQK);
-+
-+	/* Wait sacn to do LCK by RF Jenyu*/
-+	if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
-+		/* Delta temperature is equal to or larger than 20 centigrade.*/
-+		if (delta_LCK >= c.threshold_iqk) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
-+			cali_info->thermal_value_lck = thermal_value[RF_PATH_A];
-+
-+			/*Use RTLCK, so close power tracking driver LCK*/
-+			if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
-+				if (c.phy_lc_calibrate)
-+					(*c.phy_lc_calibrate)(dm);
-+			} else
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do not do LCK\n");
-+		}
-+	}
-+
-+	/*3 7. If necessary, move the index of swing table to adjust Tx power.*/
-+	for (i = 0; i < c.rf_path_count; i++) {
-+		if (i == RF_PATH_B) {
-+			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_b, DELTA_SWINGIDX_SIZE);
-+			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_b, DELTA_SWINGIDX_SIZE);
-+		} else if (i == RF_PATH_C) {
-+			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_c, DELTA_SWINGIDX_SIZE);
-+			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_c, DELTA_SWINGIDX_SIZE);
-+		} else if (i == RF_PATH_D) {
-+			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_d, DELTA_SWINGIDX_SIZE);
-+			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_d, DELTA_SWINGIDX_SIZE);
-+		} else {
-+			odm_move_memory(dm, delta_swing_table_idx_tup, delta_swing_table_idx_tup_a, DELTA_SWINGIDX_SIZE);
-+			odm_move_memory(dm, delta_swing_table_idx_tdown, delta_swing_table_idx_tdown_a, DELTA_SWINGIDX_SIZE);
-+		}
-+
-+		cali_info->delta_power_index_last[i] = cali_info->delta_power_index[i];	/*recording poer index offset*/
-+		delta[i] = thermal_value[i] > tssi->thermal[i] ? (thermal_value[i] - tssi->thermal[i]) : (tssi->thermal[i] - thermal_value[i]);
-+				
-+		if (delta[i] >= TXPWR_TRACK_TABLE_SIZE)
-+			delta[i] = TXPWR_TRACK_TABLE_SIZE - 1;
-+
-+		if (thermal_value[i] > tssi->thermal[i]) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"delta_swing_table_idx_tup[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tup[delta[i]], i);
-+				
-+			cali_info->delta_power_index[i] = delta_swing_table_idx_tup[delta[i]];
-+			cali_info->absolute_ofdm_swing_idx[i] =  delta_swing_table_idx_tup[delta[i]];	    /*Record delta swing for mix mode power tracking*/
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"******Temp is higher and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
-+		} else {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"delta_swing_table_idx_tdown[%d]=%d Path=%d\n", delta[i], delta_swing_table_idx_tdown[delta[i]], i);
-+			cali_info->delta_power_index[i] = -1 * delta_swing_table_idx_tdown[delta[i]];
-+			cali_info->absolute_ofdm_swing_idx[i] = -1 * delta_swing_table_idx_tdown[delta[i]];        /*Record delta swing for mix mode power tracking*/
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"******Temp is lower and cali_info->absolute_ofdm_swing_idx[%d]=%d Path=%d\n", delta[i], cali_info->absolute_ofdm_swing_idx[i], i);
-+		}
-+	}
-+
-+	for (p = RF_PATH_A; p < c.rf_path_count; p++) {	
-+		if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p])	     /*If Thermal value changes but lookup table value still the same*/
-+			cali_info->power_index_offset[p] = 0;
-+		else
-+			cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p];	/*Power index diff between 2 times Power Tracking*/
-+	}
-+
-+#if 0
-+	if (dm->support_ic_type == ODM_RTL8822C) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
-+	} else {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
-+	}
-+#endif
-+	if (*dm->mp_mode == 1) {
-+		if (cali_info->txpowertrack_control == 1) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
-+			tracking_method = MIX_MODE;
-+		} else if (cali_info->txpowertrack_control == 3) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
-+			tracking_method = TSSI_MODE;
-+		}	
-+	} else {
-+		if (rf->power_track_type >= 0 && rf->power_track_type <= 3) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
-+			tracking_method = MIX_MODE;
-+		} else if (rf->power_track_type >= 4 && rf->power_track_type <= 7) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI_MODE**********\n");
-+			tracking_method = TSSI_MODE;
-+		}	
-+	}
-+
-+	if (dm->support_ic_type == ODM_RTL8822C || dm->support_ic_type == ODM_RTL8814B)
-+		for (p = RF_PATH_A; p < c.rf_path_count; p++)
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, tracking_method, p, 0);
-+
-+	/* Wait sacn to do IQK by RF Jenyu*/
-+	if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden) && (dm->is_linked || *dm->mp_mode)) {
-+		/*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
-+		if (delta_IQK >= c.threshold_iqk) {
-+			cali_info->thermal_value_iqk = thermal_value[RF_PATH_A];
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
-+			/*if (!cali_info->is_iqk_in_progress)*/
-+			/*	(*c.do_iqk)(dm, delta_IQK, thermal_value[RF_PATH_A], 8);*/
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do IQK\n");
-+
-+			/*if (!cali_info->is_iqk_in_progress)*/
-+			/*	(*c.do_tssi_dck)(dm, true);*/
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Do TSSI DCK\n");
-+		}
-+	}
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===%s\n", __func__);
-+
-+	cali_info->tx_powercount = 0;
-+}
-+#endif
-+
-+/* 3============================================================
-+ * 3 IQ Calibration
-+ * 3============================================================ */
-+
-+void
-+odm_reset_iqk_result(
-+	struct dm_struct	*dm
-+)
-+{
-+	return;
-+}
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
-+{
-+	u8	channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
-+		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
-+	};
-+	u8	place = chnl;
-+
-+
-+	if (chnl > 14) {
-+		for (place = 14; place < sizeof(channel_all); place++) {
-+			if (channel_all[place] == chnl)
-+				return place - 13;
-+		}
-+	}
-+	return 0;
-+
-+}
-+#endif
-+
-+void
-+odm_iq_calibrate(
-+	struct dm_struct	*dm
-+)
-+{
-+	void	*adapter = dm->adapter;
-+	struct dm_iqk_info	*iqk_info = &dm->IQK_info;
-+	
-+	RF_DBG(dm, DBG_RF_IQK, "=>%s\n",__FUNCTION__);
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	if (*dm->is_fcs_mode_enable)
-+		return;
-+#endif
-+	if (dm->is_linked) {
-+		RF_DBG(dm, DBG_RF_IQK,
-+		       "interval=%d ch=%d prech=%d scan=%s rfk_f =%s\n",
-+		       dm->linked_interval, *dm->channel,  dm->pre_channel,
-+		       *dm->is_scan_in_process == TRUE ? "TRUE":"FALSE",
-+		       iqk_info->rfk_forbidden == TRUE ? "TRUE":"FALSE");
-+
-+		if (iqk_info->rfk_forbidden)	{
-+			RF_DBG(dm, DBG_RF_IQK, "return by rfk_forbidden\n");
-+			return;
-+		}
-+
-+		if (*dm->is_scan_in_process)	{
-+			RF_DBG(dm, DBG_RF_IQK, "return by is_scan_in_process\n");
-+			return;
-+		}
-+
-+		if (*dm->channel != dm->pre_channel) {
-+			dm->pre_channel = *dm->channel;
-+			dm->linked_interval = 0;
-+		}
-+
-+		if (dm->linked_interval < 3)
-+			dm->linked_interval++;
-+
-+		if (dm->linked_interval == 2)
-+			PHY_IQCalibrate(adapter, false);
-+	} else {
-+		dm->linked_interval = 0;
-+		RF_DBG(dm, DBG_RF_IQK, "is_linked =%s, interval =%d\n",
-+		       dm->is_linked == TRUE ? "TRUE":"FALSE",
-+		       dm->linked_interval);		
-+	}
-+}
-+
-+void phydm_rf_init(struct dm_struct		*dm)
-+{
-+
-+	odm_txpowertracking_init(dm);
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	odm_clear_txpowertracking_state(dm);
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+#if (RTL8814A_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814A)
-+		phy_iq_calibrate_8814a_init(dm);
-+#endif
-+#endif
-+
-+}
-+
-+void phydm_rf_watchdog(struct dm_struct *dm)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	FunctionIn(COMP_MLME);
-+
-+	if (*dm->mp_mode == 1) {
-+#if (MP_DRIVER == 1)
-+		odm_txpowertracking_check(dm);
-+#endif
-+	} else {
-+		odm_txpowertracking_check(dm);
-+
-+		if (dm->support_ic_type & (ODM_IC_11AC_SERIES |  ODM_IC_JGR3_SERIES))
-+			odm_iq_calibrate(dm);
-+	}
-+#endif
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_win.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_win.h
-new file mode 100644
-index 000000000000..3769d60a9126
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halphyrf_win.h
-@@ -0,0 +1,132 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALPHYRF_H__
-+#define __HALPHYRF_H__
-+
-+#if (RTL8814A_SUPPORT == 1)
-+	#include "halrf/rtl8814a/halrf_iqk_8814a.h"
-+#endif
-+
-+#if (RTL8822B_SUPPORT == 1)
-+	#include "halrf/rtl8822b/halrf_iqk_8822b.h"
-+	#include "../mac/Halmac_type.h"
-+#endif
-+#include "halrf/halrf_powertracking_win.h"
-+#include "halrf/halrf_kfree.h"
-+#include "halrf/halrf_txgapcal.h"
-+#if (RTL8821C_SUPPORT == 1)
-+	#include "halrf/rtl8821c/halrf_iqk_8821c.h"
-+#endif
-+
-+#if (RTL8195B_SUPPORT == 1)
-+//	#include "halrf/rtl8195b/halrf.h"
-+	#include "halrf/rtl8195b/halrf_iqk_8195b.h"
-+	#include "halrf/rtl8195b/halrf_txgapk_8195b.h"
-+	#include "halrf/rtl8195b/halrf_dpk_8195b.h"
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	#include "halrf/rtl8814b/halrf_iqk_8814b.h"
-+	#include "halrf/rtl8814b/halrf_txgapk_8814b.h"
-+#endif
-+
-+enum spur_cal_method {
-+	PLL_RESET,
-+	AFE_PHASE_SEL
-+};
-+
-+enum pwrtrack_method {
-+	BBSWING,
-+	TXAGC,
-+	MIX_MODE,
-+	TSSI_MODE,
-+	MIX_2G_TSSI_5G_MODE,
-+	MIX_5G_TSSI_2G_MODE,
-+	CLEAN_MODE
-+};
-+
-+typedef void(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
-+typedef void(*func_iqk)(void *, u8, u8, u8);
-+typedef void(*func_lck)(void *);
-+typedef void(*func_tssi_dck)(void *, u8);
-+typedef void(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
-+typedef void(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
-+typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
-+typedef void (*func_set_xtal)(void *);
-+typedef void(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
-+
-+struct txpwrtrack_cfg {
-+	u8		swing_table_size_cck;
-+	u8		swing_table_size_ofdm;
-+	u8		threshold_iqk;
-+	u8		threshold_dpk;
-+	u8		average_thermal_num;
-+	u8		rf_path_count;
-+	u32		thermal_reg_addr;
-+	func_set_pwr	odm_tx_pwr_track_set_pwr;
-+	func_iqk	do_iqk;
-+	func_lck	phy_lc_calibrate;
-+	func_tssi_dck	do_tssi_dck;
-+	func_swing	get_delta_swing_table;
-+	func_swing8814only	get_delta_swing_table8814only;
-+	func_swing_xtal			get_delta_swing_xtal_table;
-+	func_set_xtal			odm_txxtaltrack_set_xtal;
-+	func_all_swing	get_delta_all_swing_table;
-+};
-+
-+void
-+configure_txpower_track(
-+	struct dm_struct		*dm,
-+	struct txpwrtrack_cfg	*config
-+);
-+
-+
-+void
-+odm_clear_txpowertracking_state(
-+	struct dm_struct		*dm
-+);
-+
-+void
-+odm_txpowertracking_callback_thermal_meter(
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	struct dm_struct		*dm
-+#else
-+	void	*adapter
-+#endif
-+);
-+
-+#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-+void
-+odm_txpowertracking_new_callback_thermal_meter(void *dm_void);
-+#endif
-+
-+#define ODM_TARGET_CHNL_NUM_2G_5G	59
-+
-+
-+void
-+odm_reset_iqk_result(
-+	struct dm_struct	*dm
-+);
-+u8
-+odm_get_right_chnl_place_for_iqk(
-+	u8 chnl
-+);
-+
-+void odm_iq_calibrate(struct dm_struct	*dm);
-+void phydm_rf_init(struct dm_struct		*dm);
-+void phydm_rf_watchdog(struct dm_struct		*dm);
-+
-+#endif	/*#ifndef __HALPHYRF_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf.c
-new file mode 100644
-index 000000000000..c1bf2cc1d03b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf.c
-@@ -0,0 +1,4230 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ * ************************************************************
-+ */
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
-+	RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
-+	RTL8812F_SUPPORT == 1 || RTL8710C_SUPPORT == 1 ||\
-+	RTL8197G_SUPPORT == 1)
-+
-+void _iqk_check_if_reload(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+
-+	iqk_info->is_reload = (boolean)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));
-+}
-+
-+void _iqk_page_switch(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type == ODM_RTL8821C)
-+		odm_write_4byte(dm, 0x1b00, 0xf8000008);
-+	else
-+		odm_write_4byte(dm, 0x1b00, 0xf800000a);
-+}
-+
-+u32 halrf_psd_log2base(u32 val)
-+{
-+	u8 j;
-+	u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
-+	u32 result, val_fractiond_b = 0;
-+	u32 table_fraction[21] = {
-+		0, 432, 332, 274, 232, 200, 174, 151, 132, 115,
-+		100, 86, 74, 62, 51, 42, 32, 23, 15, 7, 0};
-+
-+	if (val == 0)
-+		return 0;
-+
-+	tmp = val;
-+
-+	while (1) {
-+		if (tmp == 1)
-+			break;
-+
-+		tmp = (tmp >> 1);
-+		shiftcount++;
-+	}
-+
-+	val_integerd_b = shiftcount + 1;
-+
-+	tmp2 = 1;
-+	for (j = 1; j <= val_integerd_b; j++)
-+		tmp2 = tmp2 * 2;
-+
-+	tmp = (val * 100) / tmp2;
-+	tindex = tmp / 5;
-+
-+	if (tindex > 20)
-+		tindex = 20;
-+
-+	val_fractiond_b = table_fraction[tindex];
-+
-+	result = val_integerd_b * 100 - val_fractiond_b;
-+
-+	return result;
-+}
-+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
-+void halrf_iqk_xym_enable(struct dm_struct *dm, u8 xym_enable)
-+{
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+
-+	if (xym_enable == 0)
-+		iqk_info->xym_read = false;
-+	else
-+		iqk_info->xym_read = true;
-+
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s %s\n", "xym_read = ",
-+	       (iqk_info->xym_read ? "true" : "false"));
-+}
-+
-+/*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
-+void halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	u8 i, start, num;
-+	u32 tmp1, tmp2;
-+
-+	if (!iqk_info->xym_read)
-+		return;
-+
-+	if (*dm->band_width == 0) {
-+		start = 3;
-+		num = 4;
-+	} else if (*dm->band_width == 1) {
-+		start = 2;
-+		num = 6;
-+	} else {
-+		start = 0;
-+		num = 10;
-+	}
-+
-+	odm_write_4byte(dm, 0x1b00, 0xf8000008);
-+	tmp1 = odm_read_4byte(dm, 0x1b1c);
-+	odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
-+
-+	odm_write_4byte(dm, 0x1b00, 0xf800000a);
-+	tmp2 = odm_read_4byte(dm, 0x1b1c);
-+	odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
-+
-+	for (path = 0; path < 2; path++) {
-+		odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
-+		switch (xym_type) {
-+		case 0:
-+			for (i = 0; i < num; i++) {
-+				odm_write_4byte(dm, 0x1b14, 0xe6 + start + i);
-+				odm_write_4byte(dm, 0x1b14, 0x0);
-+				iqk_info->rx_xym[path][i] =
-+						odm_read_4byte(dm, 0x1b38);
-+			}
-+			break;
-+		case 1:
-+			for (i = 0; i < num; i++) {
-+				odm_write_4byte(dm, 0x1b14, 0xe6 + start + i);
-+				odm_write_4byte(dm, 0x1b14, 0x0);
-+				iqk_info->tx_xym[path][i] =
-+						odm_read_4byte(dm, 0x1b38);
-+			}
-+			break;
-+		case 2:
-+			for (i = 0; i < 6; i++) {
-+				odm_write_4byte(dm, 0x1b14, 0xe0 + i);
-+				odm_write_4byte(dm, 0x1b14, 0x0);
-+				iqk_info->gs1_xym[path][i] =
-+						odm_read_4byte(dm, 0x1b38);
-+			}
-+			break;
-+		case 3:
-+			for (i = 0; i < 6; i++) {
-+				odm_write_4byte(dm, 0x1b14, 0xe0 + i);
-+				odm_write_4byte(dm, 0x1b14, 0x0);
-+				iqk_info->gs2_xym[path][i] =
-+						odm_read_4byte(dm, 0x1b38);
-+			}
-+			break;
-+		case 4:
-+			for (i = 0; i < 6; i++) {
-+				odm_write_4byte(dm, 0x1b14, 0xe0 + i);
-+				odm_write_4byte(dm, 0x1b14, 0x0);
-+				iqk_info->rxk1_xym[path][i] =
-+						odm_read_4byte(dm, 0x1b38);
-+			}
-+			break;
-+		}
-+		odm_write_4byte(dm, 0x1b38, 0x20000000);
-+		odm_write_4byte(dm, 0x1b00, 0xf8000008);
-+		odm_write_4byte(dm, 0x1b1c, tmp1);
-+		odm_write_4byte(dm, 0x1b00, 0xf800000a);
-+		odm_write_4byte(dm, 0x1b1c, tmp2);
-+		_iqk_page_switch(dm);
-+	}
-+}
-+
-+/*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
-+void halrf_iqk_xym_show(struct dm_struct *dm, u8 xym_type)
-+{
-+	u8 num, path, path_num, i;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+
-+	if (dm->rf_type == RF_1T1R)
-+		path_num = 0x1;
-+	else if (dm->rf_type == RF_2T2R)
-+		path_num = 0x2;
-+	else
-+		path_num = 0x4;
-+
-+	if (*dm->band_width == CHANNEL_WIDTH_20)
-+		num = 4;
-+	else if (*dm->band_width == CHANNEL_WIDTH_40)
-+		num = 6;
-+	else
-+		num = 10;
-+
-+	for (path = 0; path < path_num; path++) {
-+		switch (xym_type) {
-+		case 0:
-+			for (i = 0; i < num; i++)
-+				RF_DBG(dm, DBG_RF_IQK,
-+				       "[IQK]%-20s %-2d: 0x%x\n",
-+				       (path == 0) ? "PATH A RX-XYM " :
-+				       "PATH B RX-XYM", i,
-+				       iqk_info->rx_xym[path][i]);
-+			break;
-+		case 1:
-+			for (i = 0; i < num; i++)
-+				RF_DBG(dm, DBG_RF_IQK,
-+				       "[IQK]%-20s %-2d: 0x%x\n",
-+				       (path == 0) ? "PATH A TX-XYM " :
-+				       "PATH B TX-XYM", i,
-+				       iqk_info->tx_xym[path][i]);
-+			break;
-+		case 2:
-+			for (i = 0; i < 6; i++)
-+				RF_DBG(dm, DBG_RF_IQK,
-+				       "[IQK]%-20s %-2d: 0x%x\n",
-+				       (path == 0) ? "PATH A GS1-XYM " :
-+				       "PATH B GS1-XYM", i,
-+				       iqk_info->gs1_xym[path][i]);
-+			break;
-+		case 3:
-+			for (i = 0; i < 6; i++)
-+				RF_DBG(dm, DBG_RF_IQK,
-+				       "[IQK]%-20s %-2d: 0x%x\n",
-+				       (path == 0) ? "PATH A GS2-XYM " :
-+				       "PATH B GS2-XYM", i,
-+				       iqk_info->gs2_xym[path][i]);
-+			break;
-+		case 4:
-+			for (i = 0; i < 6; i++)
-+				RF_DBG(dm, DBG_RF_IQK,
-+				       "[IQK]%-20s %-2d: 0x%x\n",
-+				       (path == 0) ? "PATH A RXK1-XYM " :
-+				       "PATH B RXK1-XYM", i,
-+				       iqk_info->rxk1_xym[path][i]);
-+			break;
-+		}
-+	}
-+}
-+
-+void halrf_iqk_xym_dump(void *dm_void)
-+{
-+	u32 tmp1, tmp2;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	odm_write_4byte(dm, 0x1b00, 0xf8000008);
-+	tmp1 = odm_read_4byte(dm, 0x1b1c);
-+	odm_write_4byte(dm, 0x1b00, 0xf800000a);
-+	tmp2 = odm_read_4byte(dm, 0x1b1c);
-+#if 0
-+	/*halrf_iqk_xym_read(dm, xym_type);*/
-+#endif
-+	odm_write_4byte(dm, 0x1b00, 0xf8000008);
-+	odm_write_4byte(dm, 0x1b1c, tmp1);
-+	odm_write_4byte(dm, 0x1b00, 0xf800000a);
-+	odm_write_4byte(dm, 0x1b1c, tmp2);
-+	_iqk_page_switch(dm);
-+}
-+#endif
-+void halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 rf_path, j, reload_iqk = 0;
-+	u32 tmp;
-+	/*two channel, PATH, TX/RX, 0:pass 1 :fail*/
-+	boolean iqk_result[2][NUM][2];
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+
-+	if (!(dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)))
-+		return;
-+
-+	/* IQK INFO */
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n",
-+		 "% IQK Info %");
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n",
-+		 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" :
-+		 "Driver-IQK");
-+
-+	reload_iqk = (u8)odm_get_bb_reg(dm, R_0x1bf0, BIT(16));
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
-+		 "reload", (reload_iqk) ? "True" : "False");
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
-+		 "rfk_forbidden", (iqk_info->rfk_forbidden) ? "True" : "False");
-+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
-+	RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
-+		 "segment_iqk", (iqk_info->segment_iqk) ? "True" : "False");
-+#endif
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s:%d %d\n",
-+		 "iqk count / fail count", dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %d\n",
-+		 "channel", *dm->channel);
-+
-+	if (*dm->band_width == CHANNEL_WIDTH_20)
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "%-20s: %s\n", "bandwidth", "BW_20");
-+	else if (*dm->band_width == CHANNEL_WIDTH_40)
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "%-20s: %s\n", "bandwidth", "BW_40");
-+	else if (*dm->band_width == CHANNEL_WIDTH_80)
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "%-20s: %s\n", "bandwidth", "BW_80");
-+	else if (*dm->band_width == CHANNEL_WIDTH_160)
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "%-20s: %s\n", "bandwidth", "BW_160");
-+	else if (*dm->band_width == CHANNEL_WIDTH_80_80)
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "%-20s: %s\n", "bandwidth", "BW_80_80");
-+	else
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "%-20s: %s\n", "bandwidth", "BW_UNKNOWN");
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "%-20s: %llu %s\n", "progressing_time",
-+		 dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
-+
-+	tmp = odm_read_4byte(dm, 0x1bf0);
-+	for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
-+		for (j = 0; j < 2; j++)
-+			iqk_result[0][rf_path][j] = (boolean)
-+			(tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
-+		 "PATH_A-Tx result",
-+		 (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
-+		 "PATH_A-Rx result",
-+		 (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
-+#if (RTL8822B_SUPPORT == 1)
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
-+		 "PATH_B-Tx result",
-+		 (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n",
-+		 "PATH_B-Rx result",
-+		 (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
-+#endif
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void halrf_get_fw_version(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	rf->fw_ver = (dm->fw_version << 16) | dm->fw_sub_version;
-+}
-+
-+void halrf_iqk_dbg(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 rf_path, j;
-+	u32 tmp;
-+	/*two channel, PATH, TX/RX, 0:pass 1 :fail*/
-+	boolean iqk_result[2][NUM][2];
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	/* IQK INFO */
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== IQK Info ======");
-+
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s\n",
-+	       (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" :
-+	       "Driver-IQK");
-+
-+	if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {
-+		halrf_get_fw_version(dm);
-+		RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%x\n", "FW_VER", rf->fw_ver);
-+	} else {
-+		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "IQK_VER", HALRF_IQK_VER);
-+	}
-+
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "reload",
-+	       (iqk_info->is_reload) ? "True" : "False");
-+
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %d %d\n", "iqk count / fail count",
-+	       dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
-+
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %d\n", "channel", *dm->channel);
-+
-+	if (*dm->band_width == CHANNEL_WIDTH_20)
-+		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_20");
-+	else if (*dm->band_width == CHANNEL_WIDTH_40)
-+		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_40");
-+	else if (*dm->band_width == CHANNEL_WIDTH_80)
-+		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_80");
-+	else if (*dm->band_width == CHANNEL_WIDTH_160)
-+		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_160");
-+	else if (*dm->band_width == CHANNEL_WIDTH_80_80)
-+		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_80_80");
-+	else
-+		RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth",
-+		       "BW_UNKNOWN");
-+#if 0
-+/*
-+ *	RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n",
-+ *	       "progressing_time",
-+ *	       dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
-+ */
-+#endif
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "rfk_forbidden",
-+	       (iqk_info->rfk_forbidden) ? "True" : "False");
-+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
-+	RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "segment_iqk",
-+	       (iqk_info->segment_iqk) ? "True" : "False");
-+#endif
-+
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time",
-+	       dm->rf_calibrate_info.iqk_progressing_time, "(ms)");
-+
-+	tmp = odm_read_4byte(dm, 0x1bf0);
-+	for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
-+		for (j = 0; j < 2; j++)
-+			iqk_result[0][rf_path][j] = (boolean)
-+			(tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4))));
-+
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1be8",
-+	       odm_read_4byte(dm, 0x1be8));
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Tx result",
-+	       (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Rx result",
-+	       (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
-+#if (RTL8822B_SUPPORT == 1)
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Tx result",
-+	       (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Rx result",
-+	       (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
-+#endif
-+}
-+
-+void halrf_lck_dbg(struct dm_struct *dm)
-+{
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== LCK Info ======");
-+#if 0
-+	/*RF_DBG(dm, DBG_RF_IQK, "%-20s\n",
-+	 *	 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "LCK" : "RTK"));
-+	 */
-+#endif
-+	RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time",
-+	       dm->rf_calibrate_info.lck_progressing_time, "(ms)");
-+}
-+void phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822B_SUPPORT == 1)
-+	case ODM_RTL8822B:
-+		phy_get_iqk_cfir_8822b(dm, idx, path, debug);
-+	break;
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:		
-+		phy_get_iqk_cfir_8822c(dm, idx, path, debug);
-+	break;
-+#endif
-+#if (RTL8814B_SUPPORT == 1)
-+	case ODM_RTL8814B:		
-+		phy_get_iqk_cfir_8814b(dm, idx, path, debug);
-+	break;
-+#endif
-+	default:
-+	break;
-+	}
-+}
-+
-+
-+void halrf_iqk_dbg_cfir_backup(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	u8 path, idx, i;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822B_SUPPORT == 1)
-+		case ODM_RTL8822B:
-+			phy_iqk_dbg_cfir_backup_8822b(dm);
-+				break;
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+		case ODM_RTL8822C:			
-+			phy_iqk_dbg_cfir_backup_8822c(dm);
-+				break;
-+#endif
-+#if (RTL8814B_SUPPORT == 1)
-+		case ODM_RTL8814B:			
-+			phy_iqk_dbg_cfir_backup_8814b(dm);
-+				break;
-+#endif
-+	default:
-+	break;
-+	}
-+
-+}
-+
-+void halrf_iqk_dbg_cfir_backup_update(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_iqk_info *iqk = &dm->IQK_info;
-+	u8 i, path, idx;
-+	u32 bmask13_12 = BIT(13) | BIT(12);
-+	u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
-+	u32 data;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822B_SUPPORT == 1)
-+	case ODM_RTL8822B:
-+		phy_iqk_dbg_cfir_backup_update_8822b(dm);
-+		break;
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:		
-+		phy_iqk_dbg_cfir_backup_update_8822c(dm);
-+		break;
-+#endif
-+	default:
-+	break;
-+	}
-+}
-+
-+void halrf_iqk_dbg_cfir_reload(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_iqk_info *iqk = &dm->IQK_info;
-+	u8 i, path, idx;
-+	u32 bmask13_12 = BIT(13) | BIT(12);
-+	u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
-+	u32 data;
-+	
-+	switch (dm->support_ic_type) {
-+#if (RTL8822B_SUPPORT == 1)
-+	case ODM_RTL8822B:
-+		phy_iqk_dbg_cfir_reload_8822b(dm);
-+	break;
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:		
-+		phy_iqk_dbg_cfir_reload_8822c(dm);
-+		break;
-+#endif
-+	default:
-+	break;
-+	}
-+}
-+
-+void halrf_iqk_dbg_cfir_write(void *dm_void, u8 type, u32 path, u32 idx,
-+			      u32 i, u32 data)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822B_SUPPORT == 1)
-+	case ODM_RTL8822B:
-+		phy_iqk_dbg_cfir_write_8822b(dm, type, path, idx, i, data);
-+	break;
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:		
-+		phy_iqk_dbg_cfir_write_8822c(dm, type, path, idx, i, data);
-+		break;
-+#endif
-+	default:
-+	break;
-+	}
-+}
-+
-+void halrf_iqk_dbg_cfir_backup_show(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	u8 path, idx, i;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822B_SUPPORT == 1)
-+	case ODM_RTL8822B:
-+		phy_iqk_dbg_cfir_backup_8822b(dm);
-+	break;
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:		
-+		phy_iqk_dbg_cfir_backup_8822c(dm);
-+		break;
-+#endif
-+	default:
-+	break;
-+	}
-+}
-+
-+void halrf_do_imr_test(void *dm_void, u8 flag_imr_test)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (flag_imr_test != 0x0)
-+		switch (dm->support_ic_type) {
-+#if (RTL8822B_SUPPORT == 1)
-+		case ODM_RTL8822B:
-+			do_imr_test_8822b(dm);
-+			break;
-+#endif
-+#if (RTL8821C_SUPPORT == 1)
-+		case ODM_RTL8821C:
-+			do_imr_test_8821c(dm);
-+			break;
-+#endif
-+		default:
-+			break;
-+		}
-+}
-+
-+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-+void halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used,
-+		     char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if 0
-+	/*dm_value[0]=0x0: backup from SRAM & show*/
-+	/*dm_value[0]=0x1: write backup CFIR to SRAM*/
-+	/*dm_value[0]=0x2: reload default CFIR to SRAM*/
-+	/*dm_value[0]=0x3: show backup*/
-+	/*dm_value[0]=0x10: write backup CFIR real part*/
-+	/*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
-+	/*dm_value[0]=0x11: write backup CFIR imag*/
-+	/*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
-+	/*dm_value[0]=0x20 :xym_read enable*/
-+	/*--> dm_value[1]:0:disable, 1:enable*/
-+	/*if dm_value[0]=0x20 = enable, */
-+	/*0x1:show rx_sym; 0x2: tx_xym; 0x3:gs1_xym; 0x4:gs2_sym; 0x5:rxk1_xym*/
-+#endif
-+	if (dm_value[0] == 0x0)
-+		halrf_iqk_dbg_cfir_backup(dm);
-+	else if (dm_value[0] == 0x1)
-+		halrf_iqk_dbg_cfir_backup_update(dm);
-+	else if (dm_value[0] == 0x2)
-+		halrf_iqk_dbg_cfir_reload(dm);
-+	else if (dm_value[0] == 0x3)
-+		halrf_iqk_dbg_cfir_backup_show(dm);
-+	else if (dm_value[0] == 0x10)
-+		halrf_iqk_dbg_cfir_write(dm, 0, dm_value[1], dm_value[2],
-+					 dm_value[3], dm_value[4]);
-+	else if (dm_value[0] == 0x11)
-+		halrf_iqk_dbg_cfir_write(dm, 1, dm_value[1], dm_value[2],
-+					 dm_value[3], dm_value[4]);
-+	else if (dm_value[0] == 0x20)
-+		halrf_iqk_xym_enable(dm, (u8)dm_value[1]);
-+	else if (dm_value[0] == 0x21)
-+		halrf_iqk_xym_show(dm, (u8)dm_value[1]);
-+	else if (dm_value[0] == 0x30)
-+		halrf_do_imr_test(dm, (u8)dm_value[1]);
-+}
-+#endif
-+
-+void halrf_iqk_hwtx_check(void *dm_void, boolean is_check)
-+{
-+#if 0
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	u32 tmp_b04;
-+
-+	if (is_check) {
-+		iqk_info->is_hwtx = (boolean)odm_get_bb_reg(dm, R_0xb00, BIT(8));
-+	} else {
-+		if (iqk_info->is_hwtx) {
-+			tmp_b04 = odm_read_4byte(dm, 0xb04);
-+			odm_set_bb_reg(dm, R_0xb04, BIT(3) | BIT(2), 0x0);
-+			odm_write_4byte(dm, 0xb04, tmp_b04);
-+		}
-+	}
-+#endif
-+}
-+#endif
-+
-+u8 halrf_match_iqk_version(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	u32 iqk_version = 0;
-+	char temp[10] = {0};
-+
-+	odm_move_memory(dm, temp, HALRF_IQK_VER, sizeof(temp));
-+	PHYDM_SSCANF(temp + 2, DCMD_HEX, &iqk_version);
-+
-+	if (dm->support_ic_type == ODM_RTL8822B) {
-+		if (iqk_version >= 0x24 && (odm_get_hw_img_version(dm) >= 72))
-+			return 1;
-+		else if ((iqk_version <= 0x23) &&
-+			 (odm_get_hw_img_version(dm) <= 71))
-+			return 1;
-+		else
-+			return 0;
-+	}
-+
-+	if (dm->support_ic_type == ODM_RTL8821C) {
-+		if (iqk_version >= 0x18 && (odm_get_hw_img_version(dm) >= 37))
-+			return 1;
-+		else
-+			return 0;
-+	}
-+
-+	return 1;
-+}
-+
-+void halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8188E_SUPPORT == 1)
-+	case ODM_RTL8188E:
-+		halrf_rf_lna_setting_8188e(dm, type);
-+		break;
-+#endif
-+#if (RTL8192E_SUPPORT == 1)
-+	case ODM_RTL8192E:
-+		halrf_rf_lna_setting_8192e(dm, type);
-+		break;
-+#endif
-+#if (RTL8192F_SUPPORT == 1)
-+	case ODM_RTL8192F:
-+		halrf_rf_lna_setting_8192f(dm, type);
-+		break;
-+#endif
-+
-+#if (RTL8723B_SUPPORT == 1)
-+	case ODM_RTL8723B:
-+		halrf_rf_lna_setting_8723b(dm, type);
-+		break;
-+#endif
-+#if (RTL8812A_SUPPORT == 1)
-+	case ODM_RTL8812:
-+		halrf_rf_lna_setting_8812a(dm, type);
-+		break;
-+#endif
-+#if ((RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1))
-+	case ODM_RTL8881A:
-+	case ODM_RTL8821:
-+		halrf_rf_lna_setting_8821a(dm, type);
-+		break;
-+#endif
-+#if (RTL8822B_SUPPORT == 1)
-+	case ODM_RTL8822B:
-+		halrf_rf_lna_setting_8822b(dm_void, type);
-+		break;
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		halrf_rf_lna_setting_8822c(dm_void, type);
-+		break;
-+#endif
-+#if (RTL8812F_SUPPORT == 1)
-+	case ODM_RTL8812F:
-+		halrf_rf_lna_setting_8812f(dm_void, type);
-+		break;
-+#endif
-+#if (RTL8821C_SUPPORT == 1)
-+	case ODM_RTL8821C:
-+		halrf_rf_lna_setting_8821c(dm_void, type);
-+		break;
-+#endif
-+#if (RTL8710C_SUPPORT == 1)
-+	case ODM_RTL8710C:
-+		halrf_rf_lna_setting_8710c(dm_void, type);
-+		break;
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+	case ODM_RTL8721D:
-+		halrf_rf_lna_setting_8721d(dm, type);
-+		break;
-+#endif
-+#if (RTL8814B_SUPPORT == 1)
-+		case ODM_RTL8814B:
-+			break;
-+#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+void halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used,
-+				 char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	u32 dm_value[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i;
-+
-+	for (i = 0; i < 5; i++)
-+		if (input[i + 1])
-+			PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
-+
-+	if (dm_value[0] == 100) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\n[RF Supportability]\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "00. (( %s ))Power Tracking\n",
-+			 ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) ?
-+			 ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "01. (( %s ))IQK\n",
-+			 ((rf->rf_supportability & HAL_RF_IQK) ? ("V") :
-+			 (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "02. (( %s ))LCK\n",
-+			 ((rf->rf_supportability & HAL_RF_LCK) ? ("V") :
-+			 (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "03. (( %s ))DPK\n",
-+			 ((rf->rf_supportability & HAL_RF_DPK) ? ("V") :
-+			 (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "04. (( %s ))HAL_RF_TXGAPK\n",
-+			 ((rf->rf_supportability & HAL_RF_TXGAPK) ? ("V") :
-+			 (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "05. (( %s ))HAL_RF_DACK\n",
-+			 ((rf->rf_supportability & HAL_RF_DACK) ? ("V") :
-+			 (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "06. (( %s ))DPK_TRACK\n",
-+			 ((rf->rf_supportability & HAL_RF_DPK_TRACK) ? ("V") :
-+			 (".")));
-+#ifdef CONFIG_2G_BAND_SHIFT
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "07. (( %s ))HAL_2GBAND_SHIFT\n",
-+			 ((rf->rf_supportability & HAL_2GBAND_SHIFT) ? ("V") :
-+			 (".")));
-+#endif
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "08. (( %s ))HAL_RF_RXDCK\n",
-+			 ((rf->rf_supportability & HAL_RF_RXDCK) ? ("V") :
-+			 (".")));
-+
-+	} else {
-+		if (dm_value[1] == 1) /* enable */
-+			rf->rf_supportability |= BIT(dm_value[0]);
-+		else if (dm_value[1] == 2) /* disable */
-+			rf->rf_supportability &= ~(BIT(dm_value[0]));
-+		else
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[Warning!!!]  1:enable,  2:disable\n");
-+	}
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\nCurr-RF_supportability =  0x%x\n\n", rf->rf_supportability);
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#ifdef CONFIG_2G_BAND_SHIFT
-+void halrf_support_band_shift_debug(void *dm_void, char input[][16], u32 *_used,
-+				    char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	//u32 band_value[2] = {00};
-+	u32 dm_value[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i;
-+
-+#if (RTL8192F_SUPPORT == 1)
-+	for (i = 0; i < 7; i++)
-+		if (input[i + 1])
-+			PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
-+
-+	if (!(rf->rf_supportability & HAL_2GBAND_SHIFT)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\nCurr-RF_supportability[07. (( . ))HAL_2GBAND_SHIFT]\nNo RF Band Shift,default: 2.4G!\n");
-+	} else {
-+		if (dm_value[0] == 01) {
-+			rf->rf_shift_band = HAL_RF_2P3;
-+			halrf_lck_trigger(dm);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n[rf_shift_band] = %d\nRF Band Shift to 2.3G!\n",
-+				 rf->rf_shift_band);
-+		} else if (dm_value[0] == 02) {
-+			rf->rf_shift_band = HAL_RF_2P5;
-+			halrf_lck_trigger(dm);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n[rf_shift_band] = %d\nRF Band Shift to 2.5G!\n",
-+				 rf->rf_shift_band);
-+		} else {
-+			rf->rf_shift_band = HAL_RF_2P4;
-+			halrf_lck_trigger(dm);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n[rf_shift_band] = %d\nNo RF Band Shift,default: 2.4G!\n",
-+				 rf->rf_shift_band);
-+		}
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+#endif
-+}
-+#endif
-+
-+void halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info,
-+			 u32 value)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	switch (cmn_info) {
-+	case HALRF_CMNINFO_EEPROM_THERMAL_VALUE:
-+		rf->eeprom_thermal = (u8)value;
-+		break;
-+	case HALRF_CMNINFO_PWT_TYPE:
-+		rf->pwt_type = (u8)value;
-+		break;
-+	case HALRF_CMNINFO_MP_POWER_TRACKING_TYPE:
-+		rf->mp_pwt_type = (u8)value;
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+void halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info,
-+			 void *value)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	switch (cmn_info) {
-+	case HALRF_CMNINFO_CON_TX:
-+		rf->is_con_tx = (boolean *)value;
-+		break;
-+	case HALRF_CMNINFO_SINGLE_TONE:
-+		rf->is_single_tone = (boolean *)value;
-+		break;
-+	case HALRF_CMNINFO_CARRIER_SUPPRESSION:
-+		rf->is_carrier_suppresion = (boolean *)value;
-+		break;
-+	case HALRF_CMNINFO_MP_RATE_INDEX:
-+		rf->mp_rate_index = (u8 *)value;
-+		break;
-+	case HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY:
-+		rf->manual_rf_supportability = (u32 *)value;
-+		break;
-+	default:
-+		/*do nothing*/
-+		break;
-+	}
-+}
-+
-+void halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value)
-+{
-+	/* This init variable may be changed in run time. */
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	switch (cmn_info) {
-+	case HALRF_CMNINFO_ABILITY:
-+		rf->rf_supportability = (u32)value;
-+		break;
-+
-+	case HALRF_CMNINFO_DPK_EN:
-+		rf->dpk_en = (u8)value;
-+		break;
-+	case HALRF_CMNINFO_RFK_FORBIDDEN:
-+		dm->IQK_info.rfk_forbidden = (boolean)value;
-+		break;
-+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
-+	RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
-+	case HALRF_CMNINFO_IQK_SEGMENT:
-+		dm->IQK_info.segment_iqk = (boolean)value;
-+		break;
-+#endif
-+	case HALRF_CMNINFO_RATE_INDEX:
-+		rf->p_rate_index = (u32)value;
-+		break;
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	case HALRF_CMNINFO_MP_PSD_POINT:
-+		rf->halrf_psd_data.point = (u32)value;
-+		break;
-+	case HALRF_CMNINFO_MP_PSD_START_POINT:
-+		rf->halrf_psd_data.start_point = (u32)value;
-+		break;
-+	case HALRF_CMNINFO_MP_PSD_STOP_POINT:
-+		rf->halrf_psd_data.stop_point = (u32)value;
-+		break;
-+	case HALRF_CMNINFO_MP_PSD_AVERAGE:
-+		rf->halrf_psd_data.average = (u32)value;
-+		break;
-+#endif
-+	case HALRF_CMNINFO_POWER_TRACK_CONTROL:
-+		cali_info->txpowertrack_control = (u8)value;
-+		break;
-+	default:
-+		/* do nothing */
-+		break;
-+	}
-+}
-+
-+u64 halrf_cmn_info_get(void *dm_void, u32 cmn_info)
-+{
-+	/* This init variable may be changed in run time. */
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	u64 return_value = 0;
-+
-+	switch (cmn_info) {
-+	case HALRF_CMNINFO_ABILITY:
-+		return_value = (u32)rf->rf_supportability;
-+		break;
-+	case HALRF_CMNINFO_RFK_FORBIDDEN:
-+		return_value = dm->IQK_info.rfk_forbidden;
-+		break;
-+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \
-+	RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT == 1  || RTL8822C_SUPPORT == 1)
-+	case HALRF_CMNINFO_IQK_SEGMENT:
-+		return_value = dm->IQK_info.segment_iqk;
-+		break;
-+	case HALRF_CMNINFO_IQK_TIMES:
-+		return_value = dm->IQK_info.iqk_times;
-+		break;
-+#endif
-+	default:
-+		/* do nothing */
-+		break;
-+	}
-+
-+	return return_value;
-+}
-+
-+void halrf_supportability_init_mp(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	switch (dm->support_ic_type) {
-+	case ODM_RTL8814B:
-+#if (RTL8814B_SUPPORT == 1)
-+		rf->rf_supportability =
-+			/*HAL_RF_TX_PWR_TRACK |*/
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			HAL_RF_DPK |
-+			HAL_RF_DACK |
-+			/*HAL_RF_TXGAPK |*/
-+			HAL_RF_DPK_TRACK |
-+			0;
-+#endif
-+		break;
-+#if (RTL8822B_SUPPORT == 1)
-+	case ODM_RTL8822B:
-+		rf->rf_supportability =
-+			/*HAL_RF_TX_PWR_TRACK |*/
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			/*@HAL_RF_DPK |*/
-+			0;
-+		break;
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		rf->rf_supportability =
-+			/*HAL_RF_TX_PWR_TRACK |*/
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			HAL_RF_DPK |
-+			HAL_RF_DACK |
-+			HAL_RF_DPK_TRACK |
-+			HAL_RF_RXDCK |
-+			HAL_RF_TXGAPK |
-+			0;
-+		break;
-+#endif
-+#if (RTL8821C_SUPPORT == 1)
-+	case ODM_RTL8821C:
-+		rf->rf_supportability =
-+			/*HAL_RF_TX_PWR_TRACK |*/
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			/*@HAL_RF_DPK |*/
-+			/*@HAL_RF_TXGAPK |*/
-+			0;
-+		break;
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+	case ODM_RTL8195B:
-+		rf->rf_supportability =
-+			/*HAL_RF_TX_PWR_TRACK |*/
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			HAL_RF_DPK |
-+			/*HAL_RF_TXGAPK |*/
-+			HAL_RF_DPK_TRACK |
-+			0;
-+		break;
-+#endif
-+#if (RTL8812F_SUPPORT == 1)
-+	case ODM_RTL8812F:
-+		rf->rf_supportability =
-+			/*HAL_RF_TX_PWR_TRACK |*/
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			HAL_RF_DPK |
-+			HAL_RF_DACK |
-+			HAL_RF_DPK_TRACK |
-+			0;
-+		break;
-+#endif
-+
-+#if (RTL8198F_SUPPORT == 1)
-+	case ODM_RTL8198F:
-+		rf->rf_supportability =
-+			/*HAL_RF_TX_PWR_TRACK |*/
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			HAL_RF_DPK |
-+			/*@HAL_RF_TXGAPK |*/
-+			0;
-+		break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT == 1)
-+	case ODM_RTL8192F:
-+		rf->rf_supportability =
-+			/*HAL_RF_TX_PWR_TRACK |*/
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			HAL_RF_DPK |
-+			/*@HAL_RF_TXGAPK |*/
-+#ifdef CONFIG_2G_BAND_SHIFT
-+			/*@HAL_2GBAND_SHIFT |*/
-+#endif
-+			0;
-+		break;
-+#endif
-+
-+#if (RTL8197F_SUPPORT == 1)
-+	case ODM_RTL8197F:
-+		rf->rf_supportability =
-+			/*HAL_RF_TX_PWR_TRACK |*/
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			HAL_RF_DPK |
-+			/*@HAL_RF_TXGAPK |*/
-+			0;
-+		break;
-+#endif
-+#if (RTL8197G_SUPPORT == 1)
-+	case ODM_RTL8197G:
-+		rf->rf_supportability =
-+			/*HAL_RF_TX_PWR_TRACK |*/
-+			HAL_RF_IQK |
-+			/*HAL_RF_LCK |*/
-+			HAL_RF_DPK |
-+			/*@HAL_RF_TXGAPK |*/
-+			HAL_RF_DPK_TRACK |
-+			0;
-+		break;
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+	case ODM_RTL8721D:
-+		rf->rf_supportability =
-+			HAL_RF_TX_PWR_TRACK |
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			HAL_RF_DPK |
-+			HAL_RF_DPK_TRACK |
-+			/*@HAL_RF_TXGAPK |*/
-+			0;
-+		break;
-+#endif
-+#if (RTL8723F_SUPPORT == 1)
-+	case ODM_RTL8723F:
-+		rf->rf_supportability =
-+			/*@HAL_RF_TX_PWR_TRACK |*/
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			HAL_RF_DPK |
-+			HAL_RF_DPK_TRACK |
-+			0;
-+		break;
-+#endif
-+
-+	default:
-+		rf->rf_supportability =
-+			/*HAL_RF_TX_PWR_TRACK |*/
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			/*@HAL_RF_DPK |*/
-+			/*@HAL_RF_TXGAPK |*/
-+			0;
-+		break;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_INIT,
-+	       "IC = ((0x%x)), RF_Supportability Init MP = ((0x%x))\n",
-+	       dm->support_ic_type, rf->rf_supportability);
-+}
-+
-+void halrf_supportability_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	switch (dm->support_ic_type) {
-+	case ODM_RTL8814B:
-+#if (RTL8814B_SUPPORT == 1)
-+		rf->rf_supportability =
-+			HAL_RF_TX_PWR_TRACK |
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			HAL_RF_DPK |
-+			HAL_RF_DACK |
-+			HAL_RF_DPK_TRACK |
-+			0;
-+#endif
-+		break;
-+#if (RTL8822B_SUPPORT == 1)
-+	case ODM_RTL8822B:
-+		rf->rf_supportability =
-+			HAL_RF_TX_PWR_TRACK |
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			/*@HAL_RF_DPK |*/
-+			0;
-+		break;
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		rf->rf_supportability =
-+			HAL_RF_TX_PWR_TRACK |
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			HAL_RF_DPK |
-+			HAL_RF_DACK |
-+			HAL_RF_DPK_TRACK |
-+			HAL_RF_RXDCK |
-+			HAL_RF_TXGAPK |
-+			0;
-+		break;
-+#endif
-+#if (RTL8821C_SUPPORT == 1)
-+	case ODM_RTL8821C:
-+		rf->rf_supportability =
-+			HAL_RF_TX_PWR_TRACK |
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			/*@HAL_RF_DPK |*/
-+			/*@HAL_RF_TXGAPK |*/
-+			0;
-+		break;
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+	case ODM_RTL8195B:
-+		rf->rf_supportability =
-+			HAL_RF_TX_PWR_TRACK |
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			HAL_RF_DPK |
-+			/*HAL_RF_TXGAPK |*/
-+			HAL_RF_DPK_TRACK |
-+			0;
-+		break;
-+#endif
-+#if (RTL8812F_SUPPORT == 1)
-+		case ODM_RTL8812F:
-+			rf->rf_supportability =
-+				HAL_RF_TX_PWR_TRACK |
-+				HAL_RF_IQK |
-+				HAL_RF_LCK |
-+				HAL_RF_DPK |
-+				HAL_RF_DACK |
-+				HAL_RF_DPK_TRACK |
-+				0;
-+			break;
-+#endif
-+
-+#if (RTL8198F_SUPPORT == 1)
-+		case ODM_RTL8198F:
-+			rf->rf_supportability =
-+				HAL_RF_TX_PWR_TRACK |
-+				HAL_RF_IQK |
-+				HAL_RF_LCK |
-+				HAL_RF_DPK |
-+				/*@HAL_RF_TXGAPK |*/
-+				0;
-+			break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT == 1)
-+		case ODM_RTL8192F:
-+			rf->rf_supportability =
-+				HAL_RF_TX_PWR_TRACK |
-+				HAL_RF_IQK |
-+				HAL_RF_LCK |
-+				HAL_RF_DPK |
-+				/*@HAL_RF_TXGAPK |*/
-+#ifdef CONFIG_2G_BAND_SHIFT
-+				/*@HAL_2GBAND_SHIFT |*/
-+#endif
-+				0;
-+			break;
-+#endif
-+
-+#if (RTL8197F_SUPPORT == 1)
-+		case ODM_RTL8197F:
-+			rf->rf_supportability =
-+				HAL_RF_TX_PWR_TRACK |
-+				HAL_RF_IQK |
-+				HAL_RF_LCK |
-+				HAL_RF_DPK |
-+				/*@HAL_RF_TXGAPK |*/
-+				0;
-+			break;
-+#endif
-+#if (RTL8197G_SUPPORT == 1)
-+		case ODM_RTL8197G:
-+			rf->rf_supportability =
-+				HAL_RF_TX_PWR_TRACK |
-+				HAL_RF_IQK |
-+				/*HAL_RF_LCK |*/
-+				HAL_RF_DPK |
-+				/*@HAL_RF_TXGAPK |*/
-+				HAL_RF_DPK_TRACK |
-+#ifdef CONFIG_2G_BAND_SHIFT
-+				HAL_2GBAND_SHIFT |
-+#endif
-+			0;
-+		break;
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+		case ODM_RTL8721D:
-+			rf->rf_supportability =
-+				HAL_RF_TX_PWR_TRACK |
-+				HAL_RF_IQK |
-+				HAL_RF_LCK |
-+				HAL_RF_DPK |
-+				HAL_RF_DPK_TRACK |
-+				/*@HAL_RF_TXGAPK |*/
-+				0;
-+			break;
-+#endif
-+#if (RTL8723F_SUPPORT == 1)
-+		case ODM_RTL8723F:
-+			rf->rf_supportability =
-+				/*@HAL_RF_TX_PWR_TRACK |*/
-+				HAL_RF_IQK |
-+				HAL_RF_LCK |
-+				HAL_RF_DPK |
-+				HAL_RF_DPK_TRACK |
-+				0;
-+			break;
-+#endif
-+
-+	default:
-+		rf->rf_supportability =
-+			HAL_RF_TX_PWR_TRACK |
-+			HAL_RF_IQK |
-+			HAL_RF_LCK |
-+			/*@HAL_RF_DPK |*/
-+			0;
-+		break;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_INIT,
-+	       "IC = ((0x%x)), RF_Supportability Init = ((0x%x))\n",
-+	       dm->support_ic_type, rf->rf_supportability);
-+}
-+
-+void halrf_watchdog(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+#if 0
-+	/*RF_DBG(dm, DBG_RF_TMP, "%s\n", __func__);*/
-+#endif
-+
-+	if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
-+		rf->is_tssi_in_progress)
-+		return;
-+
-+	phydm_rf_watchdog(dm);
-+	halrf_dpk_track(dm);
-+}
-+
-+#if 0
-+void
-+halrf_iqk_init(
-+	void			*dm_void
-+)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8814B_SUPPORT == 1)
-+	case ODM_RTL8814B:
-+		break;
-+#endif
-+#if (RTL8822B_SUPPORT == 1)
-+	case ODM_RTL8822B:
-+		_iq_calibrate_8822b_init(dm);
-+		break;
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		_iq_calibrate_8822c_init(dm);
-+		break;
-+#endif
-+#if (RTL8821C_SUPPORT == 1)
-+	case ODM_RTL8821C:
-+		break;
-+#endif
-+
-+	default:
-+		break;
-+	}
-+}
-+#endif
-+
-+void halrf_rfk_power_save(void *dm_void, boolean is_power_save)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:		
-+		halrf_rfk_power_save_8822c(dm, is_power_save);
-+	break;
-+#endif
-+	default:
-+	break;
-+	}
-+}
-+
-+
-+
-+void halrf_reload_iqk(void *dm_void, boolean reset)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	u8 i, ch;
-+	u32 tmp;
-+	u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16);
-+
-+	halrf_rfk_power_save(dm, false);
-+	switch (dm->support_ic_type) {
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		iqk_reload_iqk_8822c(dm, reset);
-+	break;
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+	case ODM_RTL8195B:
-+		iqk_reload_iqk_8195b(dm, reset);
-+	break;
-+#endif
-+
-+	default:
-+	break;
-+	}
-+	halrf_rfk_power_save(dm, true);
-+}
-+
-+void halrf_rfk_handshake(void *dm_void, boolean is_before_k)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!dm->mp_mode)
-+		return;
-+
-+	if (*dm->mp_mode)
-+		return;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822C_SUPPORT == 1)
-+		case ODM_RTL8822C:
-+			halrf_rfk_handshake_8822c(dm, is_before_k);
-+			break;
-+#endif
-+#if (RTL8710C_SUPPORT == 1)
-+		case ODM_RTL8710C:
-+			halrf_rfk_handshake_8710c(dm, is_before_k);
-+			break;
-+#endif
-+		default:
-+			break;
-+	}
-+}
-+
-+void halrf_bbreset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8814B_SUPPORT == 1)
-+		case ODM_RTL8814B:
-+			phydm_bb_reset_8814b(dm);
-+			break;
-+#endif
-+		default:
-+			break;
-+	}
-+}
-+
-+void halrf_rf_k_connect_trigger(void *dm_void, boolean is_recovery,
-+				enum halrf_k_segment_time seg_time)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;	
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	if (!dm->mp_mode)
-+		return;
-+
-+	if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
-+		rf->is_carrier_suppresion) {
-+		if (*dm->mp_mode & 
-+			(*rf->is_con_tx || *rf->is_single_tone ||
-+			*rf->is_carrier_suppresion))
-+			return;
-+	}
-+
-+	/*[TX GAP K]*/
-+	halrf_txgapk_trigger(dm);
-+
-+	/*[LOK, IQK]*/
-+	halrf_segment_iqk_trigger(dm, true, seg_time);
-+
-+	/*[TSSI Trk]*/
-+	halrf_tssi_trigger(dm);
-+	/*[DPK]*/
-+	if(dpk_info->is_dpk_by_channel == true)
-+		halrf_dpk_trigger(dm);
-+	else
-+		halrf_dpk_reload(dm);
-+	//ADDA restore to MP_UI setting;
-+	config_halrf_path_adda_setting_trigger(dm);
-+
-+	halrf_bbreset(dm);
-+}
-+
-+void config_halrf_path_adda_setting_trigger(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		config_phydm_path_adda_setting_8814b(dm);
-+#endif
-+	
-+}
-+
-+void halrf_dack_restore(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	if (!(rf->rf_supportability & HAL_RF_DACK))
-+		return;
-+	switch (dm->support_ic_type) {
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		halrf_dack_restore_8822c(dm);
-+		break;
-+#endif
-+	default:
-+		break;
-+	}
-+}
-+void halrf_dack_trigger(void *dm_void, boolean force)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	u64 start_time;
-+
-+	if (!(rf->rf_supportability & HAL_RF_DACK))
-+		return;
-+
-+	start_time = odm_get_current_time(dm);
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		halrf_dac_cal_8822c(dm, force);
-+		break;
-+#endif
-+#if (RTL8812F_SUPPORT == 1)
-+	case ODM_RTL8812F:
-+		halrf_dac_cal_8812f(dm);
-+		break;
-+#endif
-+#if (RTL8814B_SUPPORT == 1)
-+	case ODM_RTL8814B:
-+		halrf_dac_cal_8814b(dm);
-+		break;
-+#endif
-+	default:
-+		break;
-+	}
-+	rf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);
-+	RF_DBG(dm, DBG_RF_DACK, "[DACK]DACK progressing_time = %lld ms\n",
-+	       rf->dpk_progressing_time);
-+}
-+
-+
-+void halrf_dack_dbg(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	u64 start_time;
-+
-+	if (!(rf->rf_supportability & HAL_RF_DACK))
-+		return;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		halrf_dack_dbg_8822c(dm);
-+		break;
-+#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+
-+void halrf_segment_iqk_trigger(void *dm_void, boolean clear,
-+			       boolean segment_iqk)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	u64 start_time;
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+	if (odm_check_power_status(dm) == false)
-+		return;
-+#endif
-+
-+	if (!dm->mp_mode)
-+		return;
-+
-+	if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
-+		rf->is_carrier_suppresion) {
-+		if (*dm->mp_mode & 
-+			(*rf->is_con_tx || *rf->is_single_tone ||
-+			*rf->is_carrier_suppresion))
-+			return;
-+	}
-+
-+	if (!(rf->rf_supportability & HAL_RF_IQK))
-+		return;
-+
-+#if DISABLE_BB_RF
-+	return;
-+#endif
-+	if (iqk_info->rfk_forbidden)
-+		return;
-+
-+	halrf_rfk_handshake(dm, true);
-+
-+	if (!dm->rf_calibrate_info.is_iqk_in_progress) {
-+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
-+		dm->rf_calibrate_info.is_iqk_in_progress = true;
-+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
-+		start_time = odm_get_current_time(dm);
-+		dm->IQK_info.segment_iqk = segment_iqk;
-+
-+		halrf_rfk_power_save(dm, false);
-+		switch (dm->support_ic_type) {
-+#if (RTL8822B_SUPPORT == 1)
-+		case ODM_RTL8822B:
-+			phy_iq_calibrate_8822b(dm, clear, segment_iqk);
-+			break;
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+		case ODM_RTL8822C:
-+			phy_iq_calibrate_8822c(dm, clear, segment_iqk);
-+			break;
-+#endif
-+#if (RTL8821C_SUPPORT == 1)
-+		case ODM_RTL8821C:
-+			phy_iq_calibrate_8821c(dm, clear, segment_iqk);
-+			break;
-+#endif
-+#if (RTL8814B_SUPPORT == 1)
-+		case ODM_RTL8814B:
-+			phy_iq_calibrate_8814b(dm, clear, segment_iqk);
-+			break;
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+		case ODM_RTL8195B:
-+			phy_iq_calibrate_8195b(dm, clear, segment_iqk);
-+			break;
-+#endif
-+#if (RTL8710C_SUPPORT == 1)
-+		case ODM_RTL8710C:
-+			phy_iq_calibrate_8710c(dm, clear, segment_iqk);
-+			break;
-+#endif
-+#if (RTL8198F_SUPPORT == 1)
-+		case ODM_RTL8198F:
-+			phy_iq_calibrate_8198f(dm, clear, segment_iqk);
-+			break;
-+#endif
-+#if (RTL8812F_SUPPORT == 1)
-+		case ODM_RTL8812F:
-+			phy_iq_calibrate_8812f(dm, clear, segment_iqk);
-+			break;
-+#endif
-+#if (RTL8197G_SUPPORT == 1)
-+		case ODM_RTL8197G:
-+			phy_iq_calibrate_8197g(dm, clear, segment_iqk);
-+			break;
-+#endif
-+#if (RTL8188E_SUPPORT == 1)
-+		case ODM_RTL8188E:
-+			phy_iq_calibrate_8188e(dm, false);
-+			break;
-+#endif
-+#if (RTL8188F_SUPPORT == 1)
-+		case ODM_RTL8188F:
-+			phy_iq_calibrate_8188f(dm, false);
-+			break;
-+#endif
-+#if (RTL8192E_SUPPORT == 1)
-+		case ODM_RTL8192E:
-+			phy_iq_calibrate_8192e(dm, false);
-+			break;
-+#endif
-+#if (RTL8197F_SUPPORT == 1)
-+		case ODM_RTL8197F:
-+			phy_iq_calibrate_8197f(dm, false);
-+			break;
-+#endif
-+#if (RTL8192F_SUPPORT == 1)
-+		case ODM_RTL8192F:
-+			phy_iq_calibrate_8192f(dm, false);
-+			break;
-+#endif
-+#if (RTL8703B_SUPPORT == 1)
-+		case ODM_RTL8703B:
-+			phy_iq_calibrate_8703b(dm, false);
-+			break;
-+#endif
-+#if (RTL8710B_SUPPORT == 1)
-+		case ODM_RTL8710B:
-+			phy_iq_calibrate_8710b(dm, false);
-+			break;
-+#endif
-+#if (RTL8723B_SUPPORT == 1)
-+		case ODM_RTL8723B:
-+			phy_iq_calibrate_8723b(dm, false);
-+			break;
-+#endif
-+#if (RTL8723D_SUPPORT == 1)
-+		case ODM_RTL8723D:
-+			phy_iq_calibrate_8723d(dm, false);
-+			break;
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+		case ODM_RTL8721D:
-+			phy_iq_calibrate_8721d(dm, false);
-+			break;
-+#endif
-+#if (RTL8812A_SUPPORT == 1)
-+		case ODM_RTL8812:
-+			phy_iq_calibrate_8812a(dm, false);
-+			break;
-+#endif
-+#if (RTL8821A_SUPPORT == 1)
-+		case ODM_RTL8821:
-+			phy_iq_calibrate_8821a(dm, false);
-+			break;
-+#endif
-+#if (RTL8814A_SUPPORT == 1)
-+		case ODM_RTL8814A:
-+			phy_iq_calibrate_8814a(dm, false);
-+			break;
-+#endif
-+		default:
-+			break;
-+		}
-+		
-+		halrf_rfk_power_save(dm, true);
-+		dm->rf_calibrate_info.iqk_progressing_time =
-+				odm_get_progressing_time(dm, start_time);
-+		RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK progressing_time = %lld ms\n",
-+		       dm->rf_calibrate_info.iqk_progressing_time);
-+
-+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
-+		dm->rf_calibrate_info.is_iqk_in_progress = false;
-+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
-+
-+		halrf_rfk_handshake(dm, false);
-+	} else {
-+		RF_DBG(dm, DBG_RF_IQK,
-+		       "== Return the IQK CMD, because RFKs in Progress ==\n");
-+	}
-+}
-+
-+
-+void halrf_iqk_trigger(void *dm_void, boolean is_recovery)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	u64 start_time;
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+	if (odm_check_power_status(dm) == false)
-+		return;
-+#endif
-+
-+	if (!dm->mp_mode)
-+		return;
-+
-+	if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
-+		rf->is_carrier_suppresion) {
-+		if (*dm->mp_mode & 
-+			(*rf->is_con_tx || *rf->is_single_tone ||
-+			*rf->is_carrier_suppresion))
-+			return;
-+	}
-+
-+	if (!(rf->rf_supportability & HAL_RF_IQK))
-+		return;
-+
-+#if DISABLE_BB_RF
-+	return;
-+#endif
-+
-+	if (iqk_info->rfk_forbidden)
-+		return;
-+
-+	halrf_rfk_handshake(dm, true);
-+
-+	if (!dm->rf_calibrate_info.is_iqk_in_progress) {
-+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
-+		dm->rf_calibrate_info.is_iqk_in_progress = true;
-+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
-+		start_time = odm_get_current_time(dm);
-+		halrf_rfk_power_save(dm, false);
-+		switch (dm->support_ic_type) {
-+#if (RTL8188E_SUPPORT == 1)
-+		case ODM_RTL8188E:
-+			phy_iq_calibrate_8188e(dm, is_recovery);
-+			break;
-+#endif
-+#if (RTL8188F_SUPPORT == 1)
-+		case ODM_RTL8188F:
-+			phy_iq_calibrate_8188f(dm, is_recovery);
-+			break;
-+#endif
-+#if (RTL8192E_SUPPORT == 1)
-+		case ODM_RTL8192E:
-+			phy_iq_calibrate_8192e(dm, is_recovery);
-+			break;
-+#endif
-+#if (RTL8197F_SUPPORT == 1)
-+		case ODM_RTL8197F:
-+			phy_iq_calibrate_8197f(dm, is_recovery);
-+			break;
-+#endif
-+#if (RTL8192F_SUPPORT == 1)
-+		case ODM_RTL8192F:
-+			phy_iq_calibrate_8192f(dm, is_recovery);
-+			break;
-+#endif
-+#if (RTL8703B_SUPPORT == 1)
-+		case ODM_RTL8703B:
-+			phy_iq_calibrate_8703b(dm, is_recovery);
-+			break;
-+#endif
-+#if (RTL8710B_SUPPORT == 1)
-+		case ODM_RTL8710B:
-+			phy_iq_calibrate_8710b(dm, is_recovery);
-+			break;
-+#endif
-+#if (RTL8723B_SUPPORT == 1)
-+		case ODM_RTL8723B:
-+			phy_iq_calibrate_8723b(dm, is_recovery);
-+			break;
-+#endif
-+#if (RTL8723D_SUPPORT == 1)
-+		case ODM_RTL8723D:
-+			phy_iq_calibrate_8723d(dm, is_recovery);
-+			break;
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+		case ODM_RTL8721D:
-+			phy_iq_calibrate_8721d(dm, is_recovery);
-+			break;
-+#endif
-+#if (RTL8812A_SUPPORT == 1)
-+		case ODM_RTL8812:
-+			phy_iq_calibrate_8812a(dm, is_recovery);
-+			break;
-+#endif
-+#if (RTL8821A_SUPPORT == 1)
-+		case ODM_RTL8821:
-+			phy_iq_calibrate_8821a(dm, is_recovery);
-+			break;
-+#endif
-+#if (RTL8814A_SUPPORT == 1)
-+		case ODM_RTL8814A:
-+			phy_iq_calibrate_8814a(dm, is_recovery);
-+			break;
-+#endif
-+#if (RTL8822B_SUPPORT == 1)
-+		case ODM_RTL8822B:
-+			phy_iq_calibrate_8822b(dm, false, false);
-+			break;
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+		case ODM_RTL8822C:
-+			phy_iq_calibrate_8822c(dm, false, false);
-+			break;
-+#endif
-+#if (RTL8821C_SUPPORT == 1)
-+		case ODM_RTL8821C:
-+			phy_iq_calibrate_8821c(dm, false, false);
-+			break;
-+#endif
-+#if (RTL8814B_SUPPORT == 1)
-+		case ODM_RTL8814B:
-+			phy_iq_calibrate_8814b(dm, false, false);
-+			break;
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+		case ODM_RTL8195B:
-+			phy_iq_calibrate_8195b(dm, false, false);
-+			break;
-+#endif
-+#if (RTL8710C_SUPPORT == 1)
-+		case ODM_RTL8710C:
-+			phy_iq_calibrate_8710c(dm, false, false);
-+			break;
-+#endif
-+#if (RTL8198F_SUPPORT == 1)
-+		case ODM_RTL8198F:
-+			phy_iq_calibrate_8198f(dm, false, false);
-+			break;
-+#endif
-+#if (RTL8812F_SUPPORT == 1)
-+		case ODM_RTL8812F:
-+			phy_iq_calibrate_8812f(dm, false, false);
-+			break;
-+#endif
-+#if (RTL8197G_SUPPORT == 1)
-+		case ODM_RTL8197G:
-+			phy_iq_calibrate_8197g(dm, false, false);
-+			break;
-+#endif
-+#if (RTL8723F_SUPPORT == 1)
-+		case ODM_RTL8723F:
-+			phy_iq_calibrate_8723f(dm, false, false);
-+			break;
-+#endif
-+
-+		default:
-+			break;
-+		}
-+
-+	halrf_rfk_power_save(dm, true);
-+	rf->iqk_progressing_time = odm_get_progressing_time(dm, start_time);
-+	RF_DBG(dm, DBG_RF_LCK, "[IQK]Trigger IQK progressing_time = %lld ms\n",
-+	       rf->iqk_progressing_time);
-+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
-+		dm->rf_calibrate_info.is_iqk_in_progress = false;
-+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
-+
-+		halrf_rfk_handshake(dm, false);
-+	} else {
-+		RF_DBG(dm, DBG_RF_IQK,
-+		       "== Return the IQK CMD, because RFKs in Progress ==\n");
-+	}
-+}
-+
-+void halrf_lck_trigger(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	u64 start_time;
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+	if (odm_check_power_status(dm) == false)
-+		return;
-+#endif
-+
-+	if (!dm->mp_mode)
-+		return;
-+
-+	if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
-+		rf->is_carrier_suppresion) {
-+		if (*dm->mp_mode & 
-+			(*rf->is_con_tx || *rf->is_single_tone ||
-+			*rf->is_carrier_suppresion))
-+			return;
-+	}
-+
-+	if (!(rf->rf_supportability & HAL_RF_LCK))
-+		return;
-+
-+#if DISABLE_BB_RF
-+	return;
-+#endif
-+	if (iqk_info->rfk_forbidden)
-+		return;
-+	while (*dm->is_scan_in_process) {
-+		RF_DBG(dm, DBG_RF_LCK, "[LCK]scan is in process, bypass LCK\n");
-+		return;
-+	}
-+
-+	if (!dm->rf_calibrate_info.is_lck_in_progress) {
-+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
-+		dm->rf_calibrate_info.is_lck_in_progress = true;
-+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
-+		start_time = odm_get_current_time(dm);
-+		switch (dm->support_ic_type) {
-+#if (RTL8188E_SUPPORT == 1)
-+		case ODM_RTL8188E:
-+			phy_lc_calibrate_8188e(dm);
-+			break;
-+#endif
-+#if (RTL8188F_SUPPORT == 1)
-+		case ODM_RTL8188F:
-+			phy_lc_calibrate_8188f(dm);
-+			break;
-+#endif
-+#if (RTL8192E_SUPPORT == 1)
-+		case ODM_RTL8192E:
-+			phy_lc_calibrate_8192e(dm);
-+			break;
-+#endif
-+#if (RTL8197F_SUPPORT == 1)
-+		case ODM_RTL8197F:
-+			phy_lc_calibrate_8197f(dm);
-+			break;
-+#endif
-+#if (RTL8192F_SUPPORT == 1)
-+		case ODM_RTL8192F:
-+			phy_lc_calibrate_8192f(dm);
-+			break;
-+#endif
-+#if (RTL8703B_SUPPORT == 1)
-+		case ODM_RTL8703B:
-+			phy_lc_calibrate_8703b(dm);
-+			break;
-+#endif
-+#if (RTL8710B_SUPPORT == 1)
-+		case ODM_RTL8710B:
-+			phy_lc_calibrate_8710b(dm);
-+			break;
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+		case ODM_RTL8721D:
-+			phy_lc_calibrate_8721d(dm);
-+			break;
-+#endif
-+#if (RTL8723B_SUPPORT == 1)
-+		case ODM_RTL8723B:
-+			phy_lc_calibrate_8723b(dm);
-+			break;
-+#endif
-+#if (RTL8723D_SUPPORT == 1)
-+		case ODM_RTL8723D:
-+			phy_lc_calibrate_8723d(dm);
-+			break;
-+#endif
-+#if (RTL8812A_SUPPORT == 1)
-+		case ODM_RTL8812:
-+			phy_lc_calibrate_8812a(dm);
-+			break;
-+#endif
-+#if (RTL8821A_SUPPORT == 1)
-+		case ODM_RTL8821:
-+			phy_lc_calibrate_8821a(dm);
-+			break;
-+#endif
-+#if (RTL8814A_SUPPORT == 1)
-+		case ODM_RTL8814A:
-+			phy_lc_calibrate_8814a(dm);
-+			break;
-+#endif
-+#if (RTL8822B_SUPPORT == 1)
-+		case ODM_RTL8822B:
-+			phy_lc_calibrate_8822b(dm);
-+			break;
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+		case ODM_RTL8822C:
-+			phy_lc_calibrate_8822c(dm);
-+			break;
-+#endif
-+#if (RTL8812F_SUPPORT == 1)
-+		case ODM_RTL8812F:
-+			phy_lc_calibrate_8812f(dm);
-+			break;
-+#endif
-+#if (RTL8821C_SUPPORT == 1)
-+		case ODM_RTL8821C:
-+			phy_lc_calibrate_8821c(dm);
-+			break;
-+#endif
-+#if (RTL8814B_SUPPORT == 1)
-+		case ODM_RTL8814B:
-+			phy_lc_calibrate_8814b(dm);
-+			break;
-+#endif
-+#if (RTL8197G_SUPPORT == 1)
-+		case ODM_RTL8197G:
-+			phy_lc_calibrate_8197g(dm);
-+			break;
-+#endif
-+#if (RTL8198F_SUPPORT == 1)
-+		case ODM_RTL8198F:
-+			phy_lc_calibrate_8198f(dm);
-+			break;
-+#endif
-+#if (RTL8710C_SUPPORT == 1)
-+		case ODM_RTL8710C:
-+			phy_lc_calibrate_8710c(dm);
-+			break;
-+#endif
-+#if (RTL8723F_SUPPORT == 1)
-+		case ODM_RTL8723F:
-+			phy_lc_calibrate_8723f(dm);
-+			break;
-+#endif
-+
-+		default:
-+			break;
-+		}
-+		dm->rf_calibrate_info.lck_progressing_time =
-+				odm_get_progressing_time(dm, start_time);
-+		RF_DBG(dm, DBG_RF_LCK, "[LCK]LCK progressing_time = %lld ms\n",
-+		       dm->rf_calibrate_info.lck_progressing_time);
-+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
-+		halrf_lck_dbg(dm);
-+#endif
-+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
-+		dm->rf_calibrate_info.is_lck_in_progress = false;
-+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
-+	} else {
-+		RF_DBG(dm, DBG_RF_LCK,
-+		       "[LCK]= Return the LCK CMD, because RFK is in Progress =\n");
-+	}
-+}
-+
-+void halrf_aac_check(struct dm_struct *dm)
-+{
-+	switch (dm->support_ic_type) {
-+#if (RTL8821C_SUPPORT == 1)
-+	case ODM_RTL8821C:
-+#if 0
-+		aac_check_8821c(dm);
-+#endif
-+		break;
-+#endif
-+#if (RTL8822B_SUPPORT == 1)
-+	case ODM_RTL8822B:
-+#if 1
-+		aac_check_8822b(dm);
-+#endif
-+		break;
-+#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+void halrf_rxdck(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	if (!(rf->rf_supportability & HAL_RF_RXDCK))
-+		return;
-+
-+	switch (dm->support_ic_type) {
-+	case ODM_RTL8822C:
-+#if (RTL8822C_SUPPORT == 1)
-+		halrf_rxdck_8822c(dm);
-+		break;
-+#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+void halrf_x2k_check(struct dm_struct *dm)
-+{
-+
-+	switch (dm->support_ic_type) {
-+	case ODM_RTL8821C:
-+#if (RTL8821C_SUPPORT == 1)
-+#endif
-+		break;
-+	case ODM_RTL8822C:
-+#if (RTL8822C_SUPPORT == 1)
-+		phy_x2_check_8822c(dm);
-+		break;
-+#endif
-+	case ODM_RTL8812F:
-+#if (RTL8812F_SUPPORT == 1)
-+		phy_x2_check_8812f(dm);
-+		break;
-+#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+void halrf_set_rfsupportability(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	if (!dm->mp_mode)
-+		return;
-+
-+	if (rf->manual_rf_supportability &&
-+	    *rf->manual_rf_supportability != 0xffffffff) {
-+		rf->rf_supportability = *rf->manual_rf_supportability;
-+	} else if (*dm->mp_mode) {
-+		halrf_supportability_init_mp(dm);
-+	} else {
-+		halrf_supportability_init(dm);
-+	}
-+}
-+
-+void halrf_rfe_definition(struct dm_struct *dm)
-+{
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	switch (dm->support_ic_type) {
-+	case ODM_RTL8822C:
-+#if (RTL8822C_SUPPORT == 1)
-+		if (dm->rfe_type == 21 || dm->rfe_type == 22) {
-+			rf->ext_pa_5g = 1;
-+			rf->ext_lna_5g = 1;
-+			}
-+		break;
-+#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+void halrf_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	RF_DBG(dm, DBG_RF_INIT, "HALRF_Init\n");
-+	rf->aac_checked = false;
-+	halrf_init_debug_setting(dm);
-+	halrf_set_rfsupportability(dm);
-+	halrf_rfe_definition(dm);
-+#if 1
-+	/*Init all RF funciton*/
-+	halrf_aac_check(dm);
-+	halrf_dack_trigger(dm, false);
-+	halrf_x2k_check(dm);
-+#endif
-+
-+	/*power trim, thrmal trim, pa bias*/
-+	phydm_config_new_kfree(dm);
-+
-+	/*TSSI Init*/
-+	halrf_tssi_dck(dm, true);
-+	halrf_tssi_get_efuse(dm);
-+	halrf_tssi_set_de(dm);
-+
-+	/*TX Gap K*/
-+	halrf_txgapk_write_gain_table(dm);
-+}
-+
-+void halrf_dpk_trigger(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+
-+	u64 start_time;
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+	if (odm_check_power_status(dm) == false)
-+		return;
-+#endif
-+
-+	if (!dm->mp_mode)
-+		return;
-+
-+	if (dm->mp_mode && rf->is_con_tx && rf->is_single_tone &&
-+		rf->is_carrier_suppresion) {
-+		if (*dm->mp_mode &
-+			(*rf->is_con_tx || *rf->is_single_tone ||
-+			*rf->is_carrier_suppresion))
-+			return;
-+	}
-+
-+	if (!(rf->rf_supportability & HAL_RF_DPK))
-+		return;
-+
-+#if DISABLE_BB_RF
-+	return;
-+#endif
-+
-+	if (iqk_info->rfk_forbidden)
-+		return;
-+
-+	halrf_rfk_handshake(dm, true);
-+
-+	if (!rf->is_dpk_in_progress) {
-+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
-+		rf->is_dpk_in_progress = true;
-+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
-+		start_time = odm_get_current_time(dm);
-+		halrf_rfk_power_save(dm, false);
-+		switch (dm->support_ic_type) {
-+#if (RTL8822C_SUPPORT == 1)
-+		case ODM_RTL8822C:
-+			do_dpk_8822c(dm);
-+			break;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+#if (RTL8197F_SUPPORT == 1)
-+		case ODM_RTL8197F:
-+			do_dpk_8197f(dm);
-+			break;
-+#endif
-+#if (RTL8192F_SUPPORT == 1)
-+		case ODM_RTL8192F:
-+			do_dpk_8192f(dm);
-+			break;
-+#endif
-+
-+#if (RTL8198F_SUPPORT == 1)
-+		case ODM_RTL8198F:
-+			do_dpk_8198f(dm);
-+			break;
-+#endif
-+#if (RTL8812F_SUPPORT == 1)
-+		case ODM_RTL8812F:
-+			do_dpk_8812f(dm);
-+			break;
-+#endif
-+#if (RTL8197G_SUPPORT == 1)
-+		case ODM_RTL8197G:
-+			do_dpk_8197g(dm);
-+			break;
-+#endif
-+
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+		case ODM_RTL8814B:
-+			do_dpk_8814b(dm);
-+			break;
-+#endif
-+#if (RTL8723F_SUPPORT == 1)
-+		case ODM_RTL8723F:
-+			do_dpk_8723f(dm);
-+			break;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+#if (RTL8195B_SUPPORT == 1)
-+		case ODM_RTL8195B:
-+			do_dpk_8195b(dm);
-+		break;
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+		case ODM_RTL8721D:
-+			do_dpk_8721d(dm);
-+			break;
-+#endif
-+#endif
-+		default:
-+			break;
-+	}
-+	halrf_rfk_power_save(dm, true);
-+	rf->dpk_progressing_time = odm_get_progressing_time(dm, start_time);
-+	RF_DBG(dm, DBG_RF_DPK, "[DPK]DPK progressing_time = %lld ms\n",
-+	       rf->dpk_progressing_time);
-+
-+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
-+		rf->is_dpk_in_progress = false;
-+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
-+
-+		halrf_rfk_handshake(dm, false);
-+	} else {
-+		RF_DBG(dm, DBG_RF_DPK,
-+		       "== Return the DPK CMD, because RFKs in Progress ==\n");
-+	}
-+}
-+
-+void halrf_set_dpkbychannel(void *dm_void, boolean dpk_by_ch)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+
-+	
-+	switch (dm->support_ic_type) {
-+#if (RTL8814B_SUPPORT == 1)
-+		case ODM_RTL8814B:
-+			dpk_set_dpkbychannel_8814b(dm, dpk_by_ch);
-+		break;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+#if (RTL8195B_SUPPORT == 1)
-+		case ODM_RTL8195B:
-+			dpk_set_dpkbychannel_8195b(dm,dpk_by_ch);
-+		break;
-+#endif
-+#endif
-+		default:
-+			if (dpk_by_ch)
-+				dpk_info->is_dpk_by_channel = 1;
-+			else
-+				dpk_info->is_dpk_by_channel = 0;
-+		break;
-+	}
-+
-+}
-+
-+void halrf_set_dpkenable(void *dm_void, boolean is_dpk_enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+
-+	
-+	switch (dm->support_ic_type) {
-+#if (RTL8814B_SUPPORT == 1)
-+		case ODM_RTL8814B:
-+			dpk_set_is_dpk_enable_8814b(dm, is_dpk_enable);
-+		break;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+#if (RTL8195B_SUPPORT == 1)
-+		case ODM_RTL8195B:
-+			dpk_set_is_dpk_enable_8195b(dm, is_dpk_enable);
-+	break;
-+#endif
-+
-+#if (RTL8721D_SUPPORT == 1)
-+	case ODM_RTL8721D:
-+		dpk_set_is_dpk_enable_8721d(dm, is_dpk_enable);
-+	break;
-+#endif
-+
-+#endif
-+	default:
-+	break;
-+	}
-+
-+}
-+boolean halrf_get_dpkbychannel(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	boolean is_dpk_by_channel = true;
-+	
-+	switch (dm->support_ic_type) {
-+#if (RTL8814B_SUPPORT == 1)
-+		case ODM_RTL8814B:
-+			is_dpk_by_channel = dpk_get_dpkbychannel_8814b(dm);
-+		break;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+#if (RTL8195B_SUPPORT == 1)
-+		case ODM_RTL8195B:
-+			is_dpk_by_channel = dpk_get_dpkbychannel_8195b(dm);
-+		break;
-+#endif
-+#endif
-+
-+	default:
-+	break;
-+	}
-+	return is_dpk_by_channel;
-+
-+}
-+
-+
-+boolean halrf_get_dpkenable(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+	struct dm_iqk_info *iqk_info = &dm->IQK_info;
-+	boolean is_dpk_enable = true;
-+
-+	
-+	switch (dm->support_ic_type) {
-+#if (RTL8814B_SUPPORT == 1)
-+		case ODM_RTL8814B:
-+			is_dpk_enable = dpk_get_is_dpk_enable_8814b(dm);
-+		break;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+#if (RTL8195B_SUPPORT == 1)
-+		case ODM_RTL8195B:
-+			is_dpk_enable = dpk_get_is_dpk_enable_8195b(dm);
-+		break;
-+#endif
-+#endif
-+		default:
-+		break;
-+	}
-+	return is_dpk_enable;
-+
-+}
-+
-+u8 halrf_dpk_result_check(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+
-+	u8 result = 0;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		if (dpk_info->dpk_path_ok == 0x3)
-+			result = 1;
-+		else
-+			result = 0;
-+		break;
-+#endif
-+
-+#if (RTL8195B_SUPPORT == 1)
-+	case ODM_RTL8195B:
-+		if (dpk_info->dpk_path_ok == 0x1)
-+			result = 1;
-+		else
-+			result = 0;
-+		break;
-+#endif
-+
-+#if (RTL8721D_SUPPORT == 1)
-+	case ODM_RTL8721D:
-+		if (dpk_info->dpk_path_ok == 0x1)
-+			result = 1;
-+		else
-+			result = 0;
-+		break;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#if (RTL8197F_SUPPORT == 1)
-+	case ODM_RTL8197F:
-+		if (dpk_info->dpk_path_ok == 0x3)
-+			result = 1;
-+		else
-+			result = 0;
-+		break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT == 1)
-+	case ODM_RTL8192F:
-+		if (dpk_info->dpk_path_ok == 0x3)
-+			result = 1;
-+		else
-+			result = 0;
-+		break;
-+#endif
-+
-+#if (RTL8198F_SUPPORT == 1)
-+	case ODM_RTL8198F:
-+		if (dpk_info->dpk_path_ok == 0xf)
-+			result = 1;
-+		else
-+			result = 0;
-+		break;
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	case ODM_RTL8814B:
-+		if (dpk_info->dpk_path_ok == 0xf)
-+			result = 1;
-+		else
-+			result = 0;
-+		break;
-+#endif
-+
-+#if (RTL8812F_SUPPORT == 1)
-+	case ODM_RTL8812F:
-+		if (dpk_info->dpk_path_ok == 0x3)
-+			result = 1;
-+		else
-+			result = 0;
-+		break;
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	case ODM_RTL8197G:
-+		if (dpk_info->dpk_path_ok == 0x3)
-+			result = 1;
-+		else
-+			result = 0;
-+		break;
-+#endif
-+
-+#endif
-+	default:
-+		break;
-+	}
-+	return result;
-+}
-+
-+void halrf_dpk_sram_read(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	u8 path, group;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		dpk_coef_read_8822c(dm);
-+		break;
-+#endif
-+
-+#if (RTL8195B_SUPPORT == 1)
-+	case ODM_RTL8195B:
-+		dpk_sram_read_8195b(dm);
-+		break;
-+#endif
-+
-+#if (RTL8721D_SUPPORT == 1)
-+	case ODM_RTL8721D:
-+		dpk_sram_read_8721d(dm);
-+		break;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#if (RTL8197F_SUPPORT == 1)
-+	case ODM_RTL8197F:
-+		dpk_sram_read_8197f(dm);
-+		break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT == 1)
-+	case ODM_RTL8192F:
-+		dpk_sram_read_8192f(dm);
-+		break;
-+#endif
-+
-+#if (RTL8198F_SUPPORT == 1)
-+	case ODM_RTL8198F:
-+		dpk_sram_read_8198f(dm);
-+		break;
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	case ODM_RTL8814B:
-+		dpk_sram_read_8814b(dm);
-+		break;
-+#endif
-+
-+#if (RTL8812F_SUPPORT == 1)
-+	case ODM_RTL8812F:
-+		dpk_coef_read_8812f(dm);
-+		break;
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	case ODM_RTL8197G:
-+		dpk_sram_read_8197g(dm);
-+		break;
-+#endif
-+
-+#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+void halrf_dpk_enable_disable(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	if (!(rf->rf_supportability & HAL_RF_DPK))
-+		return;
-+
-+	if (!rf->is_dpk_in_progress) {
-+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
-+		rf->is_dpk_in_progress = true;
-+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		dpk_enable_disable_8822c(dm);
-+		break;
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+	case ODM_RTL8195B:
-+		dpk_enable_disable_8195b(dm);
-+		break;
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+		case ODM_RTL8721D:
-+			phy_dpk_enable_disable_8721d(dm);
-+		break;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#if (RTL8197F_SUPPORT == 1)
-+	case ODM_RTL8197F:
-+		phy_dpk_enable_disable_8197f(dm);
-+		break;
-+#endif
-+#if (RTL8192F_SUPPORT == 1)
-+	case ODM_RTL8192F:
-+		phy_dpk_enable_disable_8192f(dm);
-+		break;
-+#endif
-+
-+#if (RTL8198F_SUPPORT == 1)
-+	case ODM_RTL8198F:
-+		dpk_enable_disable_8198f(dm);
-+		break;
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	case ODM_RTL8814B:
-+		dpk_enable_disable_8814b(dm);
-+		break;
-+#endif
-+
-+#if (RTL8812F_SUPPORT == 1)
-+	case ODM_RTL8812F:
-+		dpk_enable_disable_8812f(dm);
-+		break;
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	case ODM_RTL8197G:
-+		dpk_enable_disable_8197g(dm);
-+		break;
-+#endif
-+
-+#endif
-+	default:
-+		break;
-+	}
-+
-+		odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
-+		rf->is_dpk_in_progress = false;
-+		odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
-+	} else {
-+		RF_DBG(dm, DBG_RF_DPK,
-+		       "== Return the DPK CMD, because RFKs in Progress ==\n");
-+	}
-+}
-+
-+void halrf_dpk_track(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
-+	    dm->is_psd_in_process || (dpk_info->dpk_path_ok == 0) ||
-+	    !(rf->rf_supportability & HAL_RF_DPK_TRACK) || rf->is_tssi_in_progress
-+	    || rf->is_txgapk_in_progress)
-+		return;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	if (*dm->is_fcs_mode_enable)
-+		return;
-+#endif
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8814B_SUPPORT == 1)
-+	case ODM_RTL8814B:
-+		dpk_track_8814b(dm);
-+		break;
-+#endif
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		dpk_track_8822c(dm);
-+		break;
-+#endif
-+
-+#if (RTL8195B_SUPPORT == 1)
-+	case ODM_RTL8195B:
-+		dpk_track_8195b(dm);
-+		break;
-+#endif
-+
-+#if (RTL8721D_SUPPORT == 1)
-+	case ODM_RTL8721D:
-+		phy_dpk_track_8721d(dm);
-+		break;
-+#endif
-+
-+#if (RTL8723F_SUPPORT == 1)
-+	case ODM_RTL8723F:
-+		dpk_track_8723f(dm);
-+		break;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#if (RTL8197F_SUPPORT == 1)
-+	case ODM_RTL8197F:
-+		phy_dpk_track_8197f(dm);
-+		break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT == 1)
-+	case ODM_RTL8192F:
-+		phy_dpk_track_8192f(dm);
-+		break;
-+#endif
-+
-+#if (RTL8198F_SUPPORT == 1)
-+	case ODM_RTL8198F:
-+		dpk_track_8198f(dm);
-+		break;
-+#endif
-+
-+#if (RTL8812F_SUPPORT == 1)
-+	case ODM_RTL8812F:
-+		dpk_track_8812f(dm);
-+		break;
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	case ODM_RTL8197G:
-+		dpk_track_8197g(dm);
-+		break;
-+#endif
-+
-+#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+void halrf_set_dpk_track(void *dm_void, u8 enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+
-+	if (enable)
-+		rf->rf_supportability = rf->rf_supportability | HAL_RF_DPK_TRACK;
-+	else
-+		rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK_TRACK;
-+}
-+
-+void halrf_dpk_reload(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8195B_SUPPORT == 1)
-+	case ODM_RTL8195B:
-+		if (dpk_info->dpk_path_ok > 0)
-+			dpk_reload_8195b(dm);
-+		break;
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+	case ODM_RTL8721D:
-+		if (dpk_info->dpk_path_ok > 0)
-+			dpk_reload_8721d(dm);
-+		break;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#if (RTL8197F_SUPPORT == 1)
-+	case ODM_RTL8197F:
-+		if (dpk_info->dpk_path_ok > 0)
-+			dpk_reload_8197f(dm);
-+		break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT == 1)
-+	case ODM_RTL8192F:
-+		if (dpk_info->dpk_path_ok > 0)
-+			dpk_reload_8192f(dm);
-+
-+		break;
-+#endif
-+
-+#if (RTL8198F_SUPPORT == 1)
-+	case ODM_RTL8198F:
-+		if (dpk_info->dpk_path_ok > 0)
-+			dpk_reload_8198f(dm);
-+		break;		
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	case ODM_RTL8814B:
-+		if (dpk_info->dpk_path_ok > 0)
-+			dpk_reload_8814b(dm);
-+		break;		
-+#endif
-+
-+#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+void halrf_dpk_switch(void *dm_void, u8 enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	if (enable) {
-+		rf->rf_supportability = rf->rf_supportability | HAL_RF_DPK;
-+		dpk_info->is_dpk_enable = true;
-+		halrf_dpk_enable_disable(dm);
-+		halrf_dpk_trigger(dm);
-+		halrf_set_dpk_track(dm, 1);
-+	} else {
-+		halrf_set_dpk_track(dm, 0);
-+		dpk_info->is_dpk_enable = false;
-+		halrf_dpk_enable_disable(dm);
-+		rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK;
-+	}
-+}
-+
-+void _halrf_dpk_info_by_chip(void *dm_void, u32 *_used, char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		dpk_info_by_8822c(dm, &used, output, &out_len);
-+		break;
-+#endif
-+
-+#if (RTL8812F_SUPPORT == 1)
-+	case ODM_RTL8812F:
-+		dpk_info_by_8812f(dm, &used, output, &out_len);
-+		break;
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	case ODM_RTL8197G:
-+		dpk_info_by_8197g(dm, &used, output, &out_len);
-+		break;
-+#endif
-+
-+	default:
-+		break;
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void _halrf_display_dpk_info(void *dm_void, u32 *_used, char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	char *ic_name = NULL;
-+	u8 path;
-+
-+	switch (dm->support_ic_type) {
-+
-+#if (RTL8822C_SUPPORT)
-+	case ODM_RTL8822C:
-+		ic_name = "8822C";
-+		break;
-+#endif
-+
-+#if (RTL8814B_SUPPORT)
-+	case ODM_RTL8814B:
-+		ic_name = "8814B";
-+		break;
-+#endif
-+
-+#if (RTL8812F_SUPPORT)
-+	case ODM_RTL8812F:
-+		ic_name = "8812F";
-+		break;
-+#endif
-+
-+#if (RTL8198F_SUPPORT)
-+	case ODM_RTL8198F:
-+		ic_name = "8198F";
-+		break;
-+#endif
-+
-+#if (RTL8197F_SUPPORT)
-+	case ODM_RTL8197F:
-+		ic_name = "8197F";
-+		break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT)
-+	case ODM_RTL8192F:
-+		ic_name = "8192F";
-+		break;
-+#endif
-+
-+#if (RTL8197G_SUPPORT)
-+	case ODM_RTL8197G:
-+		ic_name = "8197G";
-+		break;
-+#endif
-+
-+#if (RTL8710B_SUPPORT)
-+	case ODM_RTL8721D:
-+		ic_name = "8721D";
-+		break;
-+#endif
-+
-+#if (RTL8195B_SUPPORT)
-+	case ODM_RTL8195B:
-+		ic_name = "8195B";
-+		break;
-+#endif
-+	}
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\n===============[ DPK info %s ]===============\n", ic_name);
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s %s\n",
-+		 "DPK type", (dm->fw_offload_ability & PHYDM_RF_DPK_OFFLOAD) ? "FW" : "Driver",
-+		 (dpk_info->is_dpk_by_channel) ? "(By channel)" : "(By group)");
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d (%d)\n",
-+		 "FW Ver (Sub Ver)", dm->fw_version, dm->fw_sub_version);
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
-+		 "DPK Ver", HALRF_DPK_VER);
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
-+		 "RFK init ver", HALRF_RFK_INIT_VER);
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d (RFE type:%d)\n",
-+		 "Ext_PA 2G / 5G", dm->ext_pa, dm->ext_pa_5g, dm->rfe_type);
-+
-+	if ((dpk_info->dpk_ch == 0) && (dpk_info->thermal_dpk[0] == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used, "\n %-25s\n",
-+			 "No DPK had been done before!!!");
-+		return;
-+	}
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d\n",
-+		 "DPK Cal / OK / Reload", dpk_info->dpk_cal_cnt, dpk_info->dpk_ok_cnt,
-+		 dpk_info->dpk_reload_cnt);
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
-+		 "RFK H2C timeout", (rf->is_rfk_h2c_timeout) ? "Yes" : "No");
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
-+		 "DPD Reload", (dpk_info->dpk_status & BIT(0)) ? "Yes" : "No");
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
-+		 "DPD status", dpk_info->is_dpk_enable ? "Enable" : "Disable");
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s\n",
-+		 "DPD track status", (rf->rf_supportability & HAL_RF_DPK_TRACK) ? "Enable" : "Disable");
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s / %s / %d / %s\n",
-+		 "TSSI / Band / CH / BW", dpk_info->is_tssi_mode == 1 ? "On" : "Off",
-+		 dpk_info->dpk_band == 0 ? "2G" : "5G", dpk_info->dpk_ch,
-+		 dpk_info->dpk_bw == 3 ? "20M" : (dpk_info->dpk_bw == 2 ? "40M" : "80M"));
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %s / %s / %s / %s\n",
-+		 "DPK result (path)", dpk_info->dpk_path_ok & BIT(0) ? "OK" : "Fail",
-+		 (dm->support_ic_type & ODM_IC_2SS) ? ((dpk_info->dpk_path_ok & BIT(1)) >> 1 ? "OK" : "Fail") : "NA",
-+		 (dm->support_ic_type & ODM_IC_3SS) ? ((dpk_info->dpk_path_ok & BIT(2)) >> 2 ? "OK" : "Fail") : "NA",
-+		 (dm->support_ic_type & ODM_IC_4SS) ? ((dpk_info->dpk_path_ok & BIT(3)) >> 3 ? "OK" : "Fail") : "NA");
-+#if 0
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = %d / %d / %d / %d\n",
-+		 "DPK thermal (path)", dpk_info->thermal_dpk[0], dpk_info->thermal_dpk[1],
-+		 dpk_info->thermal_dpk[2], dpk_info->thermal_dpk[3]);
-+#endif
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = ",
-+		 "DPK thermal (path)");
-+	for (path = 0; path < KPATH; path++) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 path == (KPATH - 1) ? "%d\n" : "%d / ",
-+			 dpk_info->thermal_dpk[path]);
-+	}
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
-+		 "DPK bkup GNT control", dpk_info->gnt_control);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used, " %-25s = 0x%x\n",
-+		 "DPK bkup GNT value", dpk_info->gnt_value);
-+
-+	_halrf_dpk_info_by_chip(dm, &used, output, &out_len);
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void halrf_dpk_debug_cmd(void *dm_void, char input[][16], u32 *_used,
-+				char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+
-+	char *cmd[5] = {"-h", "on", "off", "info", "switch"};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i;
-+
-+	if ((strcmp(input[2], cmd[4]) != 0)) {
-+		if (!(rf->rf_supportability & HAL_RF_DPK)) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "DPK is Unsupported!!!\n");
-+			return;
-+		}
-+	}
-+
-+	if ((strcmp(input[2], cmd[0]) == 0)) {
-+		for (i = 1; i < 4; i++) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "  %s\n", cmd[i]);
-+		}
-+	} else if ((strcmp(input[2], cmd[1]) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "DPK is Enabled!!\n");
-+		dpk_info->is_dpk_enable = true;
-+		halrf_dpk_enable_disable(dm);
-+	} else if ((strcmp(input[2], cmd[2]) == 0)){
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "DPK is Disabled!!\n");
-+		dpk_info->is_dpk_enable = false;
-+		halrf_dpk_enable_disable(dm);
-+	} else if ((strcmp(input[2], cmd[3]) == 0))
-+		_halrf_display_dpk_info(dm, &used, output, &out_len);
-+	else if ((strcmp(input[2], cmd[4]) == 0) && (strcmp(input[3], cmd[1]) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "DPK Switch on!!\n");
-+		halrf_dpk_switch(dm, 1);
-+	} else if ((strcmp(input[2], cmd[4]) == 0) && (strcmp(input[3], cmd[2]) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "DPK Switch off!!\n");
-+		halrf_dpk_switch(dm, 0);
-+	} else {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "DPK Trigger start!!\n");
-+		halrf_dpk_trigger(dm);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "DPK Trigger finish!!\n");
-+	}
-+}
-+
-+void halrf_dpk_c2h_report_transfer(void	*dm_void, boolean is_ok, u8 *buf, u8 buf_size)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+
-+	if (!(rf->rf_supportability & HAL_RF_DPK))
-+		return;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		dpk_c2h_report_transfer_8822c(dm, is_ok, buf, buf_size);
-+		break;
-+#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+void halrf_dpk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct dm_dpk_info *dpk_info = &dm->dpk_info;
-+
-+	if (!(rf->rf_supportability & HAL_RF_DPK) || rf->is_dpk_in_progress)
-+		return;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		dpk_info_rsvd_page_8822c(dm, buf, buf_size);
-+		break;
-+#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+void halrf_iqk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	if (!(rf->rf_supportability & HAL_RF_IQK))
-+		return;
-+
-+	if (dm->rf_calibrate_info.is_iqk_in_progress)
-+		return;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		iqk_info_rsvd_page_8822c(dm, buf, buf_size);
-+		break;
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+	case ODM_RTL8195B:
-+		iqk_info_rsvd_page_8195b(dm, buf, buf_size);
-+		break;
-+#endif
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+enum hal_status
-+halrf_config_rfk_with_header_file(void *dm_void, u32 config_type)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	enum hal_status result = HAL_STATUS_SUCCESS;
-+#if 0
-+#if (RTL8822B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8822B) {
-+		if (config_type == CONFIG_BB_RF_CAL_INIT)
-+			odm_read_and_config_mp_8822b_cal_init(dm);
-+	}
-+#endif
-+#endif
-+#if (RTL8197G_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8197G) {
-+		if (config_type == CONFIG_BB_RF_CAL_INIT)
-+			odm_read_and_config_mp_8197g_cal_init(dm);
-+	}
-+#endif
-+#if (RTL8198F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8198F) {
-+		if (config_type == CONFIG_BB_RF_CAL_INIT)
-+			odm_read_and_config_mp_8198f_cal_init(dm);
-+	}
-+#endif
-+#if (RTL8812F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8812F) {
-+		if (config_type == CONFIG_BB_RF_CAL_INIT)
-+			odm_read_and_config_mp_8812f_cal_init(dm);
-+	}
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8822C) {
-+		if (config_type == CONFIG_BB_RF_CAL_INIT)
-+			odm_read_and_config_mp_8822c_cal_init(dm);
-+	}
-+#endif
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		if (config_type == CONFIG_BB_RF_CAL_INIT)
-+			odm_read_and_config_mp_8814b_cal_init(dm);
-+	}
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8195B) {
-+		if (config_type == CONFIG_BB_RF_CAL_INIT)
-+			odm_read_and_config_mp_8195b_cal_init(dm);
-+	}
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8721D) {
-+		if (config_type == CONFIG_BB_RF_CAL_INIT)
-+			odm_read_and_config_mp_8721d_cal_init(dm);
-+	}
-+#endif
-+#if (RTL8723F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8723F) {
-+		if (config_type == CONFIG_BB_RF_CAL_INIT)
-+			odm_read_and_config_mp_8723f_cal_init(dm);
-+	}
-+#endif
-+
-+#if 1
-+	if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
-+		result = phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_END, 0, 0, 0, (enum rf_path)0, 0);
-+		RF_DBG(dm, DBG_RF_IQK,"phy param offload end!result = %d", result);
-+	}
-+#endif
-+	return result;
-+}
-+
-+void halrf_txgapk_trigger(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	u64 start_time = 0x0;
-+
-+	if (!(rf->rf_supportability & HAL_RF_TXGAPK))
-+		return;
-+
-+	halrf_rfk_handshake(dm, true);
-+
-+	start_time = odm_get_current_time(dm);
-+	rf->is_txgapk_in_progress = true;
-+	halrf_rfk_power_save(dm, false);
-+
-+	switch (dm->support_ic_type) {
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+#if (RTL8195B_SUPPORT == 1)
-+	case ODM_RTL8195B:
-+		/*phy_txgap_calibrate_8195b(dm, false);*/
-+	break;
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+	case ODM_RTL8721D:
-+		/*phy_txgap_calibrate_8721d(dm, false);*/
-+	break;
-+#endif
-+
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	case ODM_RTL8814B:
-+		/*phy_txgap_calibrate_8814b(dm, false);*/
-+	break;
-+#endif
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	case ODM_RTL8822C:
-+		halrf_txgapk_8822c(dm);
-+	break;
-+#endif
-+
-+	default:
-+		break;
-+	}	
-+	halrf_rfk_power_save(dm, true);
-+	rf->is_txgapk_in_progress = false;
-+
-+	halrf_rfk_handshake(dm, false);
-+
-+	rf->dpk_progressing_time =
-+		odm_get_progressing_time(dm_void, start_time);
-+	RF_DBG(dm, DBG_RF_TXGAPK, "[TGGC]TXGAPK progressing_time = %lld ms\n",
-+	       rf->dpk_progressing_time);
-+}
-+
-+void halrf_tssi_get_efuse(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8822C) {
-+		halrf_tssi_get_efuse_8822c(dm);
-+		halrf_get_efuse_thermal_pwrtype_8822c(dm);
-+	}
-+#endif
-+
-+#if (RTL8812F_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8812F) {
-+		halrf_tssi_get_efuse_8812f(dm);
-+	}
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814B) {
-+		halrf_tssi_get_efuse_8814b(dm);
-+		halrf_get_efuse_thermal_pwrtype_8814b(dm);
-+	}
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8197G) {
-+		halrf_tssi_get_efuse_8197g(dm);
-+	}
-+#endif
-+
-+}
-+
-+void halrf_do_rxbb_dck(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8814B)
-+		halrf_do_rxbb_dck_8814b(dm);
-+#endif
-+
-+}
-+
-+void halrf_do_tssi(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8822C)
-+		halrf_do_tssi_8822c(dm);
-+#endif
-+
-+#if (RTL8812F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8812F)
-+		halrf_do_tssi_8812f(dm);
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8197G)
-+		halrf_do_tssi_8197g(dm);
-+#endif
-+
-+}
-+
-+void halrf_set_tssi_enable(void *dm_void, boolean enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+
-+	if (enable == 1) {
-+		rf->power_track_type = 4;
-+		odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x1);
-+	} else {
-+		rf->power_track_type = 0;
-+		odm_set_bb_reg(dm, R_0x1e7c, 0x40000000, 0x0);
-+	}
-+}
-+
-+
-+void halrf_do_thermal(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		halrf_do_thermal_8822c(dm);
-+#endif
-+}
-+
-+
-+
-+u32 halrf_set_tssi_value(void *dm_void, u32 tssi_value)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		return halrf_set_tssi_value_8822c(dm, tssi_value);
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		return halrf_set_tssi_value_8814b(dm, tssi_value);
-+#endif
-+
-+	return 0;
-+}
-+
-+void halrf_set_tssi_power(void *dm_void, s8 power)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	/*halrf_set_tssi_poewr_8822c(dm, power);*/
-+#endif
-+}
-+
-+void halrf_tssi_set_de_for_tx_verify(void *dm_void, u32 tssi_de, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		halrf_tssi_set_de_for_tx_verify_8822c(dm, tssi_de, path);
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		halrf_tssi_set_de_for_tx_verify_8814b(dm, tssi_de, path);
-+#endif
-+
-+#if (RTL8812F_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8812F)
-+		halrf_tssi_set_de_for_tx_verify_8812f(dm, tssi_de, path);
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8197G)
-+		halrf_tssi_set_de_for_tx_verify_8197g(dm, tssi_de, path);
-+#endif
-+
-+}
-+
-+u32 halrf_query_tssi_value(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		return halrf_query_tssi_value_8822c(dm);
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		return halrf_query_tssi_value_8814b(dm);
-+#endif
-+	return 0;
-+}
-+
-+void halrf_tssi_cck(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	/*halrf_tssi_cck_8822c(dm);*/
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		halrf_thermal_cck_8822c(dm);
-+#endif
-+
-+}
-+
-+void halrf_thermal_cck(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		halrf_thermal_cck_8822c(dm);
-+#endif
-+
-+}
-+
-+void halrf_tssi_set_de(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		halrf_tssi_set_de_8814b(dm);
-+#endif
-+}
-+
-+void halrf_tssi_dck(void *dm_void, u8 direct_do)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	
-+	halrf_rfk_handshake(dm, true);
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814B) {
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+		if (dm->rfe_type == 1 || dm->rfe_type == 4 || dm->rfe_type == 5)
-+			return;
-+#else
-+		if (dm->rfe_type == 1 || dm->rfe_type == 6)
-+			return;
-+#endif
-+		halrf_tssi_dck_8814b(dm, direct_do);
-+	}
-+#endif
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		halrf_tssi_dck_8822c(dm);
-+#endif
-+
-+#if (RTL8812F_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8812F)
-+		halrf_tssi_dck_8812f(dm);
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8197G)
-+		halrf_tssi_dck_8197g(dm);
-+#endif
-+
-+	halrf_rfk_handshake(dm, false);
-+
-+}
-+
-+void halrf_calculate_tssi_codeword(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		halrf_calculate_tssi_codeword_8814b(dm, RF_PATH_A);
-+#endif
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		halrf_calculate_tssi_codeword_8822c(dm);
-+#endif	
-+}
-+
-+void halrf_set_tssi_codeword(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
-+#endif
-+	
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		halrf_set_tssi_codeword_8814b(dm, tssi->tssi_codeword);
-+#endif
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		halrf_set_tssi_codeword_8822c(dm, tssi->tssi_codeword);
-+#endif	
-+
-+}
-+
-+u8 halrf_get_tssi_codeword_for_txindex(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814B) {
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+		return 80;
-+#else
-+		return 60;
-+#endif
-+	}
-+#endif
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		return 64;
-+#endif
-+
-+#if (RTL8812F_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8812F)
-+		return 100;
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8197G)
-+		return 100;
-+#endif
-+
-+	return 60;
-+}
-+
-+void halrf_tssi_clean_de(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8812F_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8812F)
-+		halrf_tssi_clean_de_8812f(dm);
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		halrf_tssi_clean_de_8814b(dm);
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8197G)
-+		halrf_tssi_clean_de_8197g(dm);
-+#endif
-+
-+}
-+
-+u32 halrf_tssi_trigger_de(void *dm_void, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8812F_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8812F)
-+		return halrf_tssi_trigger_de_8812f(dm, path);
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		return halrf_tssi_trigger_de_8814b(dm, path);
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8197G)
-+		return halrf_tssi_trigger_de_8197g(dm, path);
-+#endif
-+	return 0;
-+}
-+
-+u32 halrf_tssi_get_de(void *dm_void, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		return halrf_tssi_get_de_8822c(dm, path);
-+#endif
-+	
-+#if (RTL8812F_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8812F)
-+		return halrf_tssi_get_de_8812f(dm, path);
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		return halrf_tssi_get_de_8814b(dm, path);
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8197G)
-+		return halrf_tssi_get_de_8197g(dm, path);
-+#endif
-+	return 0;
-+}
-+
-+void halrf_tssi_trigger(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	if (*dm->mp_mode == 1) {
-+		if (cali_info->txpowertrack_control == 0 ||
-+			cali_info->txpowertrack_control == 1) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"[TSSI]======>%s MP Mode UI chose thermal tracking. return !!!\n", __func__);
-+			return;
-+		}
-+	} else {
-+		if (rf->power_track_type >= 0 && rf->power_track_type <= 3) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				"[TSSI]======>%s Normal Mode efues is thermal tracking. return !!!\n", __func__);
-+			return;
-+		}	
-+	}
-+#endif
-+
-+	halrf_calculate_tssi_codeword(dm);
-+	halrf_set_tssi_codeword(dm);
-+	halrf_tssi_dck(dm, false);
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	halrf_tssi_get_efuse(dm);
-+#endif
-+	halrf_tssi_set_de(dm);
-+	halrf_do_tssi(dm);
-+}
-+
-+void halrf_txgapk_write_gain_table(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		halrf_txgapk_save_all_tx_gain_table_8822c(dm);
-+#endif
-+}
-+
-+void halrf_txgapk_reload_tx_gain(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8822C_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		halrf_txgapk_reload_tx_gain_8822c(dm);
-+#endif
-+}
-+
-+void halrf_txgap_enable_disable(void *dm_void, u8 enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+
-+	if (enable) {
-+		rf->rf_supportability = rf->rf_supportability | HAL_RF_TXGAPK;
-+		halrf_txgapk_trigger(dm);
-+	} else {
-+		rf->rf_supportability = rf->rf_supportability & ~HAL_RF_TXGAPK;
-+		halrf_txgapk_reload_tx_gain(dm);
-+	}
-+}
-+
-+void _halrf_dump_subpage(void *dm_void, u32 *_used, char *output, u32 *_out_len, u8 page)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 addr;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\n===============[ Subpage_%d start]===============\n", page);
-+
-+	RF_DBG(dm, DBG_RF_RFK, " ===============[ Subpage_%d start]===============\n", page);
-+
-+	odm_set_bb_reg(dm, R_0x1b00, BIT(2) | BIT(1), page);
-+
-+	for (addr = 0x1b00; addr < 0x1c00; addr += 0x10) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 " 0x%x : 0x%08x  0x%08x  0x%08x  0x%08x\n", addr,
-+			odm_get_bb_reg(dm, addr, MASKDWORD),
-+		 	odm_get_bb_reg(dm, addr + 0x4, MASKDWORD),
-+		 	odm_get_bb_reg(dm, addr + 0x8, MASKDWORD),
-+		 	odm_get_bb_reg(dm, addr + 0xc, MASKDWORD));
-+		RF_DBG(dm, DBG_RF_RFK, " 0x%x : 0x%08x  0x%08x  0x%08x  0x%08x\n", addr,
-+		       odm_get_bb_reg(dm, addr, MASKDWORD),
-+		       odm_get_bb_reg(dm, addr + 0x4, MASKDWORD),
-+		       odm_get_bb_reg(dm, addr + 0x8, MASKDWORD),
-+		       odm_get_bb_reg(dm, addr + 0xc, MASKDWORD));
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void halrf_dump_rfk_reg(void *dm_void, char input[][16], u32 *_used,
-+			      char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 reg_1b00, supportability;
-+	u8 page;
-+
-+	if (!(dm->support_ic_type & (ODM_IC_11AC_SERIES |  ODM_IC_JGR3_SERIES))) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "CMD is Unsupported due to IC type!!!\n");
-+		RF_DBG(dm, DBG_RF_RFK, "[RFK] CMD is Unsupported due to IC type!!!\n");
-+		return;
-+	} else if (rf->is_dpk_in_progress || dm->rf_calibrate_info.is_iqk_in_progress ||
-+	    dm->is_psd_in_process || rf->is_tssi_in_progress || rf->is_txgapk_in_progress) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Bypass CMD due to RFK is doing!!!\n");
-+		RF_DBG(dm, DBG_RF_RFK, "[RFK] Bypass CMD due to RFK is doing!!!\n");
-+		return;
-+	}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	if (*dm->is_fcs_mode_enable) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Bypass CMD due to FCS mode!!!\n");
-+		RF_DBG(dm, DBG_RF_RFK, "[RFK] Bypass CMD due to FCS mode!!!\n");
-+		return;
-+	}
-+#endif
-+	supportability = rf->rf_supportability;
-+
-+	/*to avoid DPK track interruption*/
-+	rf->rf_supportability = rf->rf_supportability & ~HAL_RF_DPK_TRACK;
-+
-+	reg_1b00 = odm_get_bb_reg(dm, R_0x1b00, MASKDWORD);
-+
-+	if (input[2])
-+		PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[0]);
-+
-+	if ((strcmp(input[2], help) == 0))
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "dump subpage {0:Page0, 1:Page1, 2:Page2, 3:Page3, 4:all}\n");
-+	else if (var1[0] > 4)
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Wrong subpage number!!\n");
-+	else if (var1[0] == 4) {
-+		for (page = 0; page < 4; page++)
-+			_halrf_dump_subpage(dm, &used, output, &out_len, page);
-+	} else
-+		_halrf_dump_subpage(dm, &used, output, &out_len, (u8)var1[0]);
-+
-+	odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, reg_1b00);
-+
-+	rf->rf_supportability = supportability;
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+/*Golbal function*/
-+void halrf_reload_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 i;
-+
-+	for (i = 0; i < num; i++)
-+		odm_write_4byte(dm, bp_reg[i], bp[i]);
-+}
-+
-+void halrf_reload_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num,
-+		       u8 ss)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 i, path;
-+
-+	for (i = 0; i < num; i++) {
-+		for (path = 0; path < ss; path++)
-+			odm_set_rf_reg(dm, (enum rf_path)path, bp_reg[i],
-+				       MASK20BITS, bp[i][path]);
-+	}
-+}
-+
-+void halrf_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 i;
-+
-+	for (i = 0; i < num; i++)
-+		bp[i] = odm_read_4byte(dm, bp_reg[i]);
-+}
-+
-+void halrf_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num, u8 ss)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 i, path;
-+
-+	for (i = 0; i < num; i++) {
-+		for (path = 0; path < ss; path++) {
-+			bp[i][path] =
-+				odm_get_rf_reg(dm, (enum rf_path)path,
-+					       bp_reg[i], MASK20BITS);
-+		}
-+	}
-+}
-+
-+void halrf_swap(void *dm_void, u32 *v1, u32 *v2)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 temp;
-+
-+	temp = *v1;
-+	*v1 = *v2;
-+	*v2 = temp;
-+}
-+
-+void halrf_bubble(void *dm_void, u32 *v1, u32 *v2)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 temp;
-+
-+	if (*v1 >= 0x200 && *v2 >= 0x200) {
-+		if (*v1 > *v2)
-+			halrf_swap(dm, v1, v2);
-+	} else if (*v1 < 0x200 && *v2 < 0x200) {
-+		if (*v1 > *v2)
-+			halrf_swap(dm, v1, v2);
-+	} else if (*v1 < 0x200 && *v2 >= 0x200) {
-+		halrf_swap(dm, v1, v2);
-+	}
-+}
-+
-+void halrf_b_sort(void *dm_void, u32 *iv, u32 *qv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 temp;
-+	u32 i, j;
-+
-+	RF_DBG(dm, DBG_RF_DACK, "[DACK]bubble!!!!!!!!!!!!");
-+	for (i = 0; i < SN - 1; i++) {
-+		for (j = 0; j < (SN - 1 - i) ; j++) {
-+			halrf_bubble(dm, &iv[j], &iv[j + 1]);
-+			halrf_bubble(dm, &qv[j], &qv[j + 1]);
-+		}
-+	}
-+}
-+
-+void halrf_minmax_compare(void *dm_void, u32 value, u32 *min,
-+			  u32 *max)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (value >= 0x200) {
-+		if (*min >= 0x200) {
-+			if (*min > value)
-+				*min = value;
-+		} else {
-+			*min = value;
-+		}
-+		if (*max >= 0x200) {
-+			if (*max < value)
-+				*max = value;
-+		}
-+	} else {
-+		if (*min < 0x200) {
-+			if (*min > value)
-+				*min = value;
-+		}
-+
-+		if (*max  >= 0x200) {
-+			*max = value;
-+		} else {
-+			if (*max < value)
-+				*max = value;
-+		}
-+	}
-+}
-+
-+u32 halrf_delta(void *dm_void, u32 v1, u32 v2)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (v1 >= 0x200 && v2 >= 0x200) {
-+		if (v1 > v2)
-+			return v1 - v2;
-+		else
-+			return v2 - v1;
-+	} else if (v1 >= 0x200 && v2 < 0x200) {
-+		return v2 + (0x400 - v1);
-+	} else if (v1 < 0x200 && v2 >= 0x200) {
-+		return v1 + (0x400 - v2);
-+	}
-+
-+	if (v1 > v2)
-+		return v1 - v2;
-+	else
-+		return v2 - v1;
-+}
-+
-+boolean halrf_compare(void *dm_void, u32 value)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	boolean fail = false;
-+
-+	if (value >= 0x200 && (0x400 - value) > 0x64)
-+		fail = true;
-+	else if (value < 0x200 && value > 0x64)
-+		fail = true;
-+
-+	if (fail)
-+		RF_DBG(dm, DBG_RF_DACK, "[DACK]overflow!!!!!!!!!!!!!!!");
-+	return fail;
-+}
-+
-+void halrf_mode(void *dm_void, u32 *i_value, u32 *q_value)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 iv[SN], qv[SN], im[SN], qm[SN], temp, temp1, temp2;
-+	u32 p, m, t;
-+	u32 i_max = 0, q_max = 0, i_min = 0x0, q_min = 0x0, c = 0x0;
-+	u32 i_delta, q_delta;
-+	u8 i, j, ii = 0, qi = 0;
-+	boolean fail = false;
-+
-+	ODM_delay_ms(10);
-+	for (i = 0; i < SN; i++) {
-+		im[i] = 0;
-+		qm[i] = 0;
-+	}
-+	i = 0;
-+	c = 0;
-+	while (i < SN && c < 1000) {
-+		c++;
-+		temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
-+		iv[i] = (temp & 0x3ff000) >> 12;
-+		qv[i] = temp & 0x3ff;
-+
-+		fail = false;
-+		if (halrf_compare(dm, iv[i]))
-+			fail = true;
-+		if (halrf_compare(dm, qv[i]))
-+			fail = true;
-+		if (!fail)
-+			i++;
-+	}
-+	c = 0;
-+	do {
-+		c++;
-+		i_min = iv[0];
-+		i_max = iv[0];
-+		q_min = qv[0];
-+		q_max = qv[0];
-+		for (i = 0; i < SN; i++) {
-+			halrf_minmax_compare(dm, iv[i], &i_min, &i_max);
-+			halrf_minmax_compare(dm, qv[i], &q_min, &q_max);
-+		}
-+		RF_DBG(dm, DBG_RF_DACK, "[DACK]i_min=0x%x, i_max=0x%x",
-+		       i_min, i_max);
-+		RF_DBG(dm, DBG_RF_DACK, "[DACK]q_min=0x%x, q_max=0x%x",
-+		       q_min, q_max);
-+		if (i_max < 0x200 && i_min < 0x200)
-+			i_delta = i_max - i_min;
-+		else if (i_max >= 0x200 && i_min >= 0x200)
-+			i_delta = i_max - i_min;
-+		else
-+			i_delta = i_max + (0x400 - i_min);
-+
-+		if (q_max < 0x200 && q_min < 0x200)
-+			q_delta = q_max - q_min;
-+		else if (q_max >= 0x200 && q_min >= 0x200)
-+			q_delta = q_max - q_min;
-+		else
-+			q_delta = q_max + (0x400 - q_min);
-+		RF_DBG(dm, DBG_RF_DACK, "[DACK]i_delta=0x%x, q_delta=0x%x",
-+		       i_delta, q_delta);
-+		halrf_b_sort(dm, iv, qv);
-+		if (i_delta > 5 || q_delta > 5) {
-+			temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
-+			iv[0] = (temp & 0x3ff000) >> 12;
-+			qv[0] = temp & 0x3ff;
-+			temp = odm_get_bb_reg(dm, 0x2dbc, 0x3fffff);
-+			iv[SN - 1] = (temp & 0x3ff000) >> 12;
-+			qv[SN - 1] = temp & 0x3ff;
-+		} else {
-+			break;
-+		}
-+	} while (c < 100);
-+#if 1
-+#if 0
-+	for (i = 0; i < SN; i++)
-+		RF_DBG(dm, DBG_RF_DACK, "[DACK]iv[%d] = 0x%x\n", i, iv[i]);
-+	for (i = 0; i < SN; i++)
-+		RF_DBG(dm, DBG_RF_DACK, "[DACK]qv[%d] = 0x%x\n", i, qv[i]);
-+#endif
-+	/*i*/
-+	m = 0;
-+	p = 0;
-+	for (i = 10; i < SN - 10; i++) {
-+		if (iv[i] > 0x200)
-+			m = (0x400 - iv[i]) + m;
-+		else
-+			p = iv[i] + p;
-+	}
-+
-+	if (p > m) {
-+		t = p - m;
-+		t = t / (SN - 20);
-+	} else {
-+		t = m - p;
-+		t = t / (SN - 20);
-+		if (t != 0x0)
-+			t = 0x400 - t;
-+	}
-+	*i_value = t;
-+	/*q*/
-+	m = 0;
-+	p = 0;
-+	for (i = 10; i < SN - 10; i++) {
-+		if (qv[i] > 0x200)
-+			m = (0x400 - qv[i]) + m;
-+		else
-+			p = qv[i] + p;
-+	}
-+	if (p > m) {
-+		t = p - m;
-+		t = t / (SN - 20);
-+	} else {
-+		t = m - p;
-+		t = t / (SN - 20);
-+		if (t != 0x0)
-+			t = 0x400 - t;
-+	}
-+	*q_value = t;
-+#endif
-+}
-+void halrf_delay_10us(u16 v1)
-+{	
-+	u16 i = 0;
-+	
-+	for (i = 0; i < v1; i++)
-+		ODM_delay_us(10);
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf.h
-new file mode 100644
-index 000000000000..560b1fd10671
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf.h
-@@ -0,0 +1,802 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_H__
-+#define __HALRF_H__
-+
-+/*@============================================================*/
-+/*@include files*/
-+/*@============================================================*/
-+#include "halrf/halrf_psd.h"
-+#if (RTL8822B_SUPPORT == 1)
-+#include "halrf/rtl8822b/halrf_rfk_init_8822b.h"
-+#endif
-+#if (RTL8822C_SUPPORT == 1)
-+#include "halrf/rtl8822c/halrf_rfk_init_8822c.h"
-+#include "halrf/rtl8822c/halrf_iqk_8822c.h"
-+#include "halrf/rtl8822c/halrf_tssi_8822c.h"
-+#include "halrf/rtl8822c/halrf_dpk_8822c.h"
-+#include "halrf/rtl8822c/halrf_txgapk_8822c.h"
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+#if (RTL8197G_SUPPORT == 1)
-+#include "halrf/rtl8197g/halrf_rfk_init_8197g.h"
-+#endif
-+#if (RTL8198F_SUPPORT == 1)
-+#include "halrf/rtl8198f/halrf_rfk_init_8198f.h"
-+#endif
-+#if (RTL8812F_SUPPORT == 1)
-+#include "halrf/rtl8812f/halrf_rfk_init_8812f.h"
-+#endif
-+
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+#include "halrf/rtl8814b/halrf_rfk_init_8814b.h"
-+#include "halrf/rtl8814b/halrf_iqk_8814b.h"
-+#include "halrf/rtl8814b/halrf_dpk_8814b.h"
-+#include "halrf/rtl8814b/halrf_txgapk_8814b.h"
-+#endif
-+
-+/*@============================================================*/
-+/*@Definition */
-+/*@============================================================*/
-+/*IQK version*/
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+#define IQK_VER_8188E "0x14"
-+#define IQK_VER_8192E "0x01"
-+#define IQK_VER_8192F "0x01"
-+#define IQK_VER_8723B "0x1e"
-+#define IQK_VER_8812A "0x02"
-+#define IQK_VER_8821A "0x02"
-+#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+#define IQK_VER_8188E "0x01"
-+#define IQK_VER_8192E "0x01"
-+#define IQK_VER_8192F "0x01"
-+#define IQK_VER_8723B "0x1f"
-+#define IQK_VER_8812A "0x01"
-+#define IQK_VER_8821A "0x01"
-+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+#define IQK_VER_8188E "0x01"
-+#define IQK_VER_8192E "0x01"
-+#define IQK_VER_8192F "0x01"
-+#define IQK_VER_8723B "0x1e"
-+#define IQK_VER_8812A "0x01"
-+#define IQK_VER_8821A "0x01"
-+#elif (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+#define IQK_VER_8188E "0x01"
-+#define IQK_VER_8192E "0x01"
-+#define IQK_VER_8192F "0x01"
-+#define IQK_VER_8723B "0x1e"
-+#define IQK_VER_8812A "0x01"
-+#define IQK_VER_8821A "0x01"
-+#endif
-+#define IQK_VER_8814A "0x0f"
-+#define IQK_VER_8188F "0x01"
-+#define IQK_VER_8197F "0x1d"
-+#define IQK_VER_8703B "0x05"
-+#define IQK_VER_8710B "0x01"
-+#define IQK_VER_8723D "0x02"
-+#define IQK_VER_8822B "0x32"
-+#define IQK_VER_8822C "0x14"
-+#define IQK_VER_8821C "0x23"
-+#define IQK_VER_8198F "0x0b"
-+#define IQK_VER_8814B "0x15"
-+#define IQK_VER_8812F "0x0c"
-+#define IQK_VER_8710C "0x0a"
-+#define IQK_VER_8197G "0x03"
-+
-+/*LCK version*/
-+#define LCK_VER_8188E "0x02"
-+#define LCK_VER_8192E "0x02"
-+#define LCK_VER_8192F "0x01"
-+#define LCK_VER_8723B "0x02"
-+#define LCK_VER_8812A "0x01"
-+#define LCK_VER_8821A "0x01"
-+#define LCK_VER_8814A "0x01"
-+#define LCK_VER_8188F "0x01"
-+#define LCK_VER_8197F "0x01"
-+#define LCK_VER_8703B "0x01"
-+#define LCK_VER_8710B "0x01"
-+#define LCK_VER_8723D "0x01"
-+#define LCK_VER_8822B "0x02"
-+#define LCK_VER_8822C "0x00"
-+#define LCK_VER_8821C "0x02"
-+#define LCK_VER_8814B "0x02"
-+#define LCK_VER_8195B "0x02"
-+#define LCK_VER_8710C "0x02"
-+#define LCK_VER_8197G "0x01"
-+#define LCK_VER_8198F "0x01"
-+
-+/*power tracking version*/
-+#define PWRTRK_VER_8188E "0x01"
-+#define PWRTRK_VER_8192E "0x01"
-+#define PWRTRK_VER_8192F "0x01"
-+#define PWRTRK_VER_8723B "0x01"
-+#define PWRTRK_VER_8812A "0x01"
-+#define PWRTRK_VER_8821A "0x01"
-+#define PWRTRK_VER_8814A "0x01"
-+#define PWRTRK_VER_8188F "0x01"
-+#define PWRTRK_VER_8197F "0x01"
-+#define PWRTRK_VER_8703B "0x01"
-+#define PWRTRK_VER_8710B "0x01"
-+#define PWRTRK_VER_8723D "0x01"
-+#define PWRTRK_VER_8822B "0x01"
-+#define PWRTRK_VER_8822C "0x00"
-+#define PWRTRK_VER_8821C "0x01"
-+#define PWRTRK_VER_8814B "0x00"
-+#define PWRTRK_VER_8197G "0x00"
-+
-+/*DPK version*/
-+#define DPK_VER_8188E "NONE"
-+#define DPK_VER_8192E "NONE"
-+#define DPK_VER_8723B "NONE"
-+#define DPK_VER_8812A "NONE"
-+#define DPK_VER_8821A "NONE"
-+#define DPK_VER_8814A "NONE"
-+#define DPK_VER_8188F "NONE"
-+#define DPK_VER_8197F "0x08"
-+#define DPK_VER_8703B "NONE"
-+#define DPK_VER_8710B "NONE"
-+#define DPK_VER_8723D "NONE"
-+#define DPK_VER_8822B "NONE"
-+#define DPK_VER_8822C "0x20"
-+#define DPK_VER_8821C "NONE"
-+#define DPK_VER_8192F "0x0e"
-+#define DPK_VER_8198F "0x0e"
-+#define DPK_VER_8814B "0x0f"
-+#define DPK_VER_8195B "0x0c"
-+#define DPK_VER_8812F "0x0a"
-+#define DPK_VER_8197G "0x09"
-+
-+/*RFK_INIT version*/
-+#define RFK_INIT_VER_8822B "0x8"
-+#define RFK_INIT_VER_8822C "0x8"
-+#define RFK_INIT_VER_8195B "0x1"
-+#define RFK_INIT_VER_8198F "0x8"
-+#define RFK_INIT_VER_8814B "0xa"
-+#define RFK_INIT_VER_8812F "0x4"
-+#define RFK_INIT_VER_8197G "0x4"
-+
-+/*DACK version*/
-+#define DACK_VER_8822C "0xa"
-+#define DACK_VER_8814B "0x4"
-+
-+/*TXGAPK version*/
-+#define TXGAPK_VER_8814B "0x1"
-+#define TXGAPK_VER_8195B "0x2"
-+
-+/*Kfree tracking version*/
-+#define KFREE_VER_8188E \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8192E \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8192F \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8723B \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8812A \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8821A \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8814A \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8188F \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8197F \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8703B \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8710B \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8723D \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8822B \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8822C \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8821C \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8814B \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+#define KFREE_VER_8197G \
-+		(dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE"
-+
-+#define TSSI_VER_8812F "0x1"
-+#define TSSI_VER_8822C "0x1"
-+#define TSSI_VER_8821C "0x1"
-+#define TSSI_VER_8814B "0x1"
-+#define TSSI_VER_8197G "0x1"
-+
-+/*PA Bias Calibration version*/
-+#define PABIASK_VER_8188E \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8192E \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8192F \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8723B \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8812A \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8821A \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8814A \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8188F \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8197F \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8703B \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8710B \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8723D \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8822B \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8822C \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8821C \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8814B \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+#define PABIASK_VER_8197G \
-+	(dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE"
-+
-+#define HALRF_IQK_VER \
-+	(dm->support_ic_type == ODM_RTL8188E) ? IQK_VER_8188E : \
-+	(dm->support_ic_type == ODM_RTL8192E) ? IQK_VER_8192E : \
-+	(dm->support_ic_type == ODM_RTL8192F) ? IQK_VER_8192F : \
-+	(dm->support_ic_type == ODM_RTL8723B) ? IQK_VER_8723B : \
-+	(dm->support_ic_type == ODM_RTL8812) ? IQK_VER_8812A : \
-+	(dm->support_ic_type == ODM_RTL8821) ? IQK_VER_8821A : \
-+	(dm->support_ic_type == ODM_RTL8814A) ? IQK_VER_8814A : \
-+	(dm->support_ic_type == ODM_RTL8188F) ? IQK_VER_8188F : \
-+	(dm->support_ic_type == ODM_RTL8197F) ? IQK_VER_8197F : \
-+	(dm->support_ic_type == ODM_RTL8703B) ? IQK_VER_8703B : \
-+	(dm->support_ic_type == ODM_RTL8710B) ? IQK_VER_8710B : \
-+	(dm->support_ic_type == ODM_RTL8723D) ? IQK_VER_8723D : \
-+	(dm->support_ic_type == ODM_RTL8822B) ? IQK_VER_8822B : \
-+	(dm->support_ic_type == ODM_RTL8822C) ? IQK_VER_8822C : \
-+	(dm->support_ic_type == ODM_RTL8821C) ? IQK_VER_8821C : \
-+	(dm->support_ic_type == ODM_RTL8814B) ? IQK_VER_8814B : \
-+	(dm->support_ic_type == ODM_RTL8710C) ? IQK_VER_8710C : \
-+	(dm->support_ic_type == ODM_RTL8197G) ? IQK_VER_8197G : "unknown"
-+
-+#define HALRF_LCK_VER \
-+	(dm->support_ic_type == ODM_RTL8188E) ? LCK_VER_8188E : \
-+	(dm->support_ic_type == ODM_RTL8192E) ? LCK_VER_8192E : \
-+	(dm->support_ic_type == ODM_RTL8192F) ? LCK_VER_8192F : \
-+	(dm->support_ic_type == ODM_RTL8723B) ? LCK_VER_8723B : \
-+	(dm->support_ic_type == ODM_RTL8812) ? LCK_VER_8812A : \
-+	(dm->support_ic_type == ODM_RTL8821) ? LCK_VER_8821A : \
-+	(dm->support_ic_type == ODM_RTL8814A) ? LCK_VER_8814A : \
-+	(dm->support_ic_type == ODM_RTL8188F) ? LCK_VER_8188F : \
-+	(dm->support_ic_type == ODM_RTL8197F) ? LCK_VER_8197F : \
-+	(dm->support_ic_type == ODM_RTL8703B) ? LCK_VER_8703B : \
-+	(dm->support_ic_type == ODM_RTL8710B) ? LCK_VER_8710B : \
-+	(dm->support_ic_type == ODM_RTL8723D) ? LCK_VER_8723D : \
-+	(dm->support_ic_type == ODM_RTL8822B) ? LCK_VER_8822B : \
-+	(dm->support_ic_type == ODM_RTL8822C) ? LCK_VER_8822C : \
-+	(dm->support_ic_type == ODM_RTL8821C) ? LCK_VER_8821C : \
-+	(dm->support_ic_type == ODM_RTL8814B) ? LCK_VER_8814B : \
-+	(dm->support_ic_type == ODM_RTL8710C) ? LCK_VER_8710C : \
-+	(dm->support_ic_type == ODM_RTL8710C) ? LCK_VER_8710C : "unknown"
-+#define HALRF_POWRTRACKING_VER \
-+	(dm->support_ic_type == ODM_RTL8188E) ? PWRTRK_VER_8188E : \
-+	(dm->support_ic_type == ODM_RTL8192E) ? PWRTRK_VER_8192E : \
-+	(dm->support_ic_type == ODM_RTL8192F) ? PWRTRK_VER_8192F : \
-+	(dm->support_ic_type == ODM_RTL8723B) ? PWRTRK_VER_8723B : \
-+	(dm->support_ic_type == ODM_RTL8812) ? PWRTRK_VER_8812A : \
-+	(dm->support_ic_type == ODM_RTL8821) ? PWRTRK_VER_8821A : \
-+	(dm->support_ic_type == ODM_RTL8814A) ? PWRTRK_VER_8814A : \
-+	(dm->support_ic_type == ODM_RTL8188F) ? PWRTRK_VER_8188F : \
-+	(dm->support_ic_type == ODM_RTL8197F) ? PWRTRK_VER_8197F : \
-+	(dm->support_ic_type == ODM_RTL8703B) ? PWRTRK_VER_8703B : \
-+	(dm->support_ic_type == ODM_RTL8710B) ? PWRTRK_VER_8710B : \
-+	(dm->support_ic_type == ODM_RTL8723D) ? PWRTRK_VER_8723D : \
-+	(dm->support_ic_type == ODM_RTL8822B) ? PWRTRK_VER_8822B : \
-+	(dm->support_ic_type == ODM_RTL8822C) ? PWRTRK_VER_8822C : \
-+	(dm->support_ic_type == ODM_RTL8821C) ? PWRTRK_VER_8821C : \
-+	(dm->support_ic_type == ODM_RTL8197G) ? PWRTRK_VER_8197G : "unknown"
-+
-+#define HALRF_DPK_VER \
-+	(dm->support_ic_type == ODM_RTL8188E) ? DPK_VER_8188E : \
-+	(dm->support_ic_type == ODM_RTL8192E) ? DPK_VER_8192E : \
-+	(dm->support_ic_type == ODM_RTL8192F) ? DPK_VER_8192F : \
-+	(dm->support_ic_type == ODM_RTL8723B) ? DPK_VER_8723B : \
-+	(dm->support_ic_type == ODM_RTL8812) ? DPK_VER_8812A : \
-+	(dm->support_ic_type == ODM_RTL8821) ? DPK_VER_8821A : \
-+	(dm->support_ic_type == ODM_RTL8814A) ? DPK_VER_8814A : \
-+	(dm->support_ic_type == ODM_RTL8188F) ? DPK_VER_8188F : \
-+	(dm->support_ic_type == ODM_RTL8197F) ? DPK_VER_8197F : \
-+	(dm->support_ic_type == ODM_RTL8198F) ? DPK_VER_8198F : \
-+	(dm->support_ic_type == ODM_RTL8703B) ? DPK_VER_8703B : \
-+	(dm->support_ic_type == ODM_RTL8710B) ? DPK_VER_8710B : \
-+	(dm->support_ic_type == ODM_RTL8723D) ? DPK_VER_8723D : \
-+	(dm->support_ic_type == ODM_RTL8822B) ? DPK_VER_8822B : \
-+	(dm->support_ic_type == ODM_RTL8822C) ? DPK_VER_8822C : \
-+	(dm->support_ic_type == ODM_RTL8812F) ? DPK_VER_8812F : \
-+	(dm->support_ic_type == ODM_RTL8821C) ? DPK_VER_8821C : \
-+	(dm->support_ic_type == ODM_RTL8814B) ? DPK_VER_8814B : \
-+	(dm->support_ic_type == ODM_RTL8197G) ? DPK_VER_8197G : "unknown"
-+
-+#define HALRF_KFREE_VER \
-+	(dm->support_ic_type == ODM_RTL8188E) ? KFREE_VER_8188E : \
-+	(dm->support_ic_type == ODM_RTL8192E) ? KFREE_VER_8192E : \
-+	(dm->support_ic_type == ODM_RTL8192F) ? KFREE_VER_8192F : \
-+	(dm->support_ic_type == ODM_RTL8723B) ? KFREE_VER_8723B : \
-+	(dm->support_ic_type == ODM_RTL8812) ? KFREE_VER_8812A : \
-+	(dm->support_ic_type == ODM_RTL8821) ? KFREE_VER_8821A : \
-+	(dm->support_ic_type == ODM_RTL8814A) ? KFREE_VER_8814A : \
-+	(dm->support_ic_type == ODM_RTL8188F) ? KFREE_VER_8188F : \
-+	(dm->support_ic_type == ODM_RTL8197F) ? KFREE_VER_8197F : \
-+	(dm->support_ic_type == ODM_RTL8703B) ? KFREE_VER_8703B : \
-+	(dm->support_ic_type == ODM_RTL8710B) ? KFREE_VER_8710B : \
-+	(dm->support_ic_type == ODM_RTL8723D) ? KFREE_VER_8723D : \
-+	(dm->support_ic_type == ODM_RTL8822B) ? KFREE_VER_8822B : \
-+	(dm->support_ic_type == ODM_RTL8822C) ? KFREE_VER_8822C : \
-+	(dm->support_ic_type == ODM_RTL8821C) ? KFREE_VER_8821C : \
-+	(dm->support_ic_type == ODM_RTL8814B) ? KFREE_VER_8814B : \
-+	(dm->support_ic_type == ODM_RTL8197G) ? KFREE_VER_8197G : "unknown"
-+
-+#define HALRF_TSSI_VER \
-+	(dm->support_ic_type == ODM_RTL8812F) ? TSSI_VER_8812F : \
-+	(dm->support_ic_type == ODM_RTL8822C) ? TSSI_VER_8822C : \
-+	(dm->support_ic_type == ODM_RTL8821C) ? TSSI_VER_8821C : \
-+	(dm->support_ic_type == ODM_RTL8814B) ? TSSI_VER_8814B : \
-+	(dm->support_ic_type == ODM_RTL8197G) ? TSSI_VER_8197G : "unknown"
-+
-+#define HALRF_PABIASK_VER \
-+	(dm->support_ic_type == ODM_RTL8188E) ? PABIASK_VER_8188E : \
-+	(dm->support_ic_type == ODM_RTL8192E) ? PABIASK_VER_8192E : \
-+	(dm->support_ic_type == ODM_RTL8192F) ? PABIASK_VER_8192F : \
-+	(dm->support_ic_type == ODM_RTL8723B) ? PABIASK_VER_8723B : \
-+	(dm->support_ic_type == ODM_RTL8812) ? PABIASK_VER_8812A : \
-+	(dm->support_ic_type == ODM_RTL8821) ? PABIASK_VER_8821A : \
-+	(dm->support_ic_type == ODM_RTL8814A) ? PABIASK_VER_8814A : \
-+	(dm->support_ic_type == ODM_RTL8188F) ? PABIASK_VER_8188F : \
-+	(dm->support_ic_type == ODM_RTL8197F) ? PABIASK_VER_8197F : \
-+	(dm->support_ic_type == ODM_RTL8703B) ? PABIASK_VER_8703B : \
-+	(dm->support_ic_type == ODM_RTL8710B) ? PABIASK_VER_8710B : \
-+	(dm->support_ic_type == ODM_RTL8723D) ? PABIASK_VER_8723D : \
-+	(dm->support_ic_type == ODM_RTL8822B) ? PABIASK_VER_8822B : \
-+	(dm->support_ic_type == ODM_RTL8822C) ? PABIASK_VER_8822C : \
-+	(dm->support_ic_type == ODM_RTL8821C) ? PABIASK_VER_8821C : \
-+	(dm->support_ic_type == ODM_RTL8814B) ? PABIASK_VER_8814B : \
-+	(dm->support_ic_type == ODM_RTL8197G) ? PABIASK_VER_8197G : "unknown"
-+
-+#define HALRF_RFK_INIT_VER \
-+	(dm->support_ic_type == ODM_RTL8822B) ? RFK_INIT_VER_8822B : \
-+	(dm->support_ic_type == ODM_RTL8822C) ? RFK_INIT_VER_8822C : \
-+	(dm->support_ic_type == ODM_RTL8812F) ? RFK_INIT_VER_8812F : \
-+	(dm->support_ic_type == ODM_RTL8198F) ? RFK_INIT_VER_8198F : \
-+	(dm->support_ic_type == ODM_RTL8814B) ? RFK_INIT_VER_8814B : \
-+	(dm->support_ic_type == ODM_RTL8197G) ? RFK_INIT_VER_8197G : "unknown"
-+
-+#define HALRF_DACK_VER \
-+	(dm->support_ic_type == ODM_RTL8822C) ? DACK_VER_8822C : \
-+	(dm->support_ic_type == ODM_RTL8814B) ? DACK_VER_8814B : "unknown"
-+
-+#define IQK_THRESHOLD 8
-+#define DPK_THRESHOLD 4
-+#define HALRF_ABS(a,b) ((a>b) ? (a-b) : (b-a))
-+#define SN 100
-+
-+#define CCK_TSSI_NUM 6
-+#define OFDM_2G_TSSI_NUM 5
-+#define OFDM_5G_TSSI_NUM 14
-+
-+
-+
-+/*@===========================================================*/
-+/*AGC RX High Power mode*/
-+/*@===========================================================*/
-+#define lna_low_gain_1 0x64
-+#define lna_low_gain_2 0x5A
-+#define lna_low_gain_3 0x58
-+
-+/*@============================================================*/
-+/*@ enumeration */
-+/*@============================================================*/
-+
-+enum halrf_func_idx { /*F_XXX = PHYDM XXX function*/
-+	RF00_PWR_TRK = 0, /*Pow_trk, TSSI_trk*/
-+	RF01_IQK = 1,	  /*LOK, IQK*/
-+	RF02_LCK = 2,
-+	RF03_DPK = 3,
-+	RF04_TXGAPK = 4,
-+	RF05_DACK = 5,
-+	RF06_DPK_TRK = 6,
-+	RF07_2GBAND_SHIFT = 7,
-+	RF08_RXDCK = 8,
-+	RF09_RFK = 9
-+};
-+
-+enum halrf_ability {
-+	HAL_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
-+	HAL_RF_IQK = BIT(RF01_IQK),
-+	HAL_RF_LCK = BIT(RF02_LCK),
-+	HAL_RF_DPK = BIT(RF03_DPK),
-+	HAL_RF_TXGAPK = BIT(RF04_TXGAPK),
-+	HAL_RF_DACK = BIT(RF05_DACK),
-+	HAL_RF_DPK_TRACK = BIT(RF06_DPK_TRK),
-+	HAL_2GBAND_SHIFT = BIT(RF07_2GBAND_SHIFT),
-+	HAL_RF_RXDCK = BIT(RF08_RXDCK)
-+};
-+
-+enum halrf_shift_band {
-+	HAL_RF_2P4 = 0,
-+	HAL_RF_2P3 = 1,
-+	HAL_RF_2P5 = 2
-+};
-+
-+enum halrf_dbg_comp {
-+	DBG_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
-+	DBG_RF_IQK = BIT(RF01_IQK),
-+	DBG_RF_LCK = BIT(RF02_LCK),
-+	DBG_RF_DPK = BIT(RF03_DPK),
-+	DBG_RF_TXGAPK = BIT(RF04_TXGAPK),
-+	DBG_RF_DACK = BIT(RF05_DACK),
-+	DBG_RF_DPK_TRACK = BIT(RF06_DPK_TRK),
-+	DBG_RF_RFK = BIT(RF09_RFK),
-+	DBG_RF_MP = BIT(29),
-+	DBG_RF_TMP = BIT(30),
-+	DBG_RF_INIT = BIT(31)
-+};
-+
-+enum halrf_cmninfo_init {
-+	HALRF_CMNINFO_ABILITY = 0,
-+	HALRF_CMNINFO_DPK_EN = 1,
-+	HALRF_CMNINFO_EEPROM_THERMAL_VALUE,
-+	HALRF_CMNINFO_RFK_FORBIDDEN,
-+	HALRF_CMNINFO_IQK_SEGMENT,
-+	HALRF_CMNINFO_RATE_INDEX,
-+	HALRF_CMNINFO_PWT_TYPE,
-+	HALRF_CMNINFO_MP_PSD_POINT,
-+	HALRF_CMNINFO_MP_PSD_START_POINT,
-+	HALRF_CMNINFO_MP_PSD_STOP_POINT,
-+	HALRF_CMNINFO_MP_PSD_AVERAGE,
-+	HALRF_CMNINFO_IQK_TIMES,
-+	HALRF_CMNINFO_MP_POWER_TRACKING_TYPE,
-+	HALRF_CMNINFO_POWER_TRACK_CONTROL
-+};
-+
-+enum halrf_cmninfo_hook {
-+	HALRF_CMNINFO_CON_TX,
-+	HALRF_CMNINFO_SINGLE_TONE,
-+	HALRF_CMNINFO_CARRIER_SUPPRESSION,
-+	HALRF_CMNINFO_MP_RATE_INDEX,
-+	HALRF_CMNINFO_MANUAL_RF_SUPPORTABILITY
-+};
-+
-+enum halrf_lna_set {
-+	HALRF_LNA_DISABLE = 0,
-+	HALRF_LNA_ENABLE = 1,
-+};
-+
-+enum halrf_k_segment_time {
-+	SEGMENT_FREE = 0,
-+	SEGMENT_10MS = 10, /*10ms*/
-+	SEGMENT_30MS = 30, /*30ms*/
-+	SEGMENT_50MS = 50, /*50ms*/
-+};
-+
-+#define POWER_INDEX_DIFF 4
-+#define TSSI_TXAGC_DIFF 2
-+
-+#define TSSI_CODE_NUM 84
-+
-+#define TSSI_SLOPE_2G 8
-+#define TSSI_SLOPE_5G 5
-+
-+#define TSSI_EFUSE_NUM 25
-+#define TSSI_EFUSE_KFREE_NUM 4
-+#define TSSI_DE_DIFF_EFUSE_NUM 10
-+
-+struct _halrf_tssi_data {
-+	s32 cck_offset_patha;
-+	s32 cck_offset_pathb;
-+	s32 tssi_trk_txagc_offset[PHYDM_MAX_RF_PATH];
-+	s32 delta_tssi_txagc_offset[PHYDM_MAX_RF_PATH];
-+	s16 txagc_codeword[TSSI_CODE_NUM];
-+	u16 tssi_codeword[TSSI_CODE_NUM];
-+	s8 tssi_efuse[PHYDM_MAX_RF_PATH][TSSI_EFUSE_NUM];
-+	s8 tssi_de_diff_efuse[PHYDM_MAX_RF_PATH][TSSI_DE_DIFF_EFUSE_NUM];
-+	s8 tssi_kfree_efuse[PHYDM_MAX_RF_PATH][TSSI_EFUSE_KFREE_NUM];
-+	u8 thermal[PHYDM_MAX_RF_PATH];
-+	u32 index[PHYDM_MAX_RF_PATH][14];
-+	u8 do_tssi;
-+	u8 get_thermal;
-+	u8 tssi_finish_bit[PHYDM_MAX_RF_PATH];
-+	u8 thermal_trigger;
-+};
-+
-+struct _halrf_txgapk_info {
-+	u32 txgapk_rf3f_bp[5][12][PHYDM_MAX_RF_PATH]; /* band(2Gcck/2GOFDM/5GL/5GM/5GH)/idx/path */
-+	boolean txgapk_bp_done;
-+	s8 offset[12][PHYDM_MAX_RF_PATH];
-+	s8 fianl_offset[12][PHYDM_MAX_RF_PATH];
-+	u8 read_txgain;
-+};
-+
-+
-+/*@============================================================*/
-+/*@ structure */
-+/*@============================================================*/
-+
-+struct _hal_rf_ {
-+	/*hook*/
-+	u8 *test1;
-+
-+	/*update*/
-+	u32 rf_supportability;
-+	u8 rf_shift_band;
-+	/*u32 halrf_tssi_data;*/
-+
-+	u8 eeprom_thermal;
-+	u8 dpk_en; /*Enable Function DPK OFF/ON = 0/1*/
-+	boolean dpk_done;
-+	u64 dpk_progressing_time;
-+	u64 iqk_progressing_time;
-+	u32 fw_ver;
-+
-+	boolean *is_con_tx;
-+	boolean *is_single_tone;
-+	boolean *is_carrier_suppresion;
-+	boolean is_dpk_in_progress;
-+	boolean is_tssi_in_progress;
-+	boolean is_bt_iqk_timeout;
-+	boolean is_rfk_h2c_timeout;
-+	boolean aac_checked;
-+	boolean is_txgapk_in_progress;
-+
-+	u8 *mp_rate_index;
-+	u32 *manual_rf_supportability;
-+	u32 p_rate_index;
-+	u8 pwt_type;
-+	u32 rf_dbg_comp;
-+
-+	u8 ext_lna;		/*@with 2G external LNA  NO/Yes = 0/1*/
-+	u8 ext_lna_5g;		/*@with 5G external LNA  NO/Yes = 0/1*/
-+	u8 ext_pa;		/*@with 2G external PNA  NO/Yes = 0/1*/
-+	u8 ext_pa_5g;		/*@with 5G external PNA  NO/Yes = 0/1*/
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	struct _halrf_psd_data halrf_psd_data;
-+	struct _halrf_tssi_data halrf_tssi_data;
-+#endif
-+	struct _halrf_txgapk_info halrf_txgapk_info;
-+	u8 power_track_type;
-+	u8 mp_pwt_type;
-+	u8 pre_band_type;
-+};
-+
-+/*@============================================================*/
-+/*@ function prototype */
-+/*@============================================================*/
-+
-+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
-+	RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
-+	RTL8812F_SUPPORT == 1 || RTL8710C_SUPPORT == 1 ||\
-+	RTL8197G_SUPPORT == 1)
-+void halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output,
-+			 u32 *_out_len);
-+
-+void halrf_iqk_hwtx_check(void *dm_void, boolean is_check);
-+#endif
-+
-+u8 halrf_match_iqk_version(void *dm_void);
-+
-+void halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used,
-+				 char *output, u32 *_out_len);
-+#ifdef CONFIG_2G_BAND_SHIFT
-+void halrf_support_band_shift_debug(void *dm_void, char input[][16], u32 *_used,
-+				    char *output, u32 *_out_len);
-+#endif
-+void halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info,
-+			 u32 value);
-+
-+void halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info,
-+			 void *value);
-+
-+void halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value);
-+
-+u64 halrf_cmn_info_get(void *dm_void, u32 cmn_info);
-+
-+void halrf_watchdog(void *dm_void);
-+
-+void halrf_supportability_init(void *dm_void);
-+
-+void halrf_init(void *dm_void);
-+
-+void halrf_iqk_trigger(void *dm_void, boolean is_recovery);
-+
-+void halrf_rfk_handshake(void *dm_void, boolean is_before_k);
-+
-+void halrf_rf_k_connect_trigger(void *dm_void, boolean is_recovery,
-+				enum halrf_k_segment_time seg_time);
-+
-+void halrf_segment_iqk_trigger(void *dm_void, boolean clear,
-+			       boolean segment_iqk);
-+
-+void halrf_lck_trigger(void *dm_void);
-+
-+void halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used,
-+		     char *output, u32 *_out_len);
-+
-+void phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug);
-+
-+void halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type);
-+
-+void halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type);
-+
-+void halrf_do_imr_test(void *dm_void, u8 data);
-+
-+u32 halrf_psd_log2base(u32 val);
-+
-+void halrf_dpk_trigger(void *dm_void);
-+
-+void halrf_txgapk_trigger(void *dm_void);
-+
-+u8 halrf_dpk_result_check(void *dm_void);
-+
-+void halrf_dpk_sram_read(void *dm_void);
-+
-+void halrf_dpk_enable_disable(void *dm_void);
-+
-+void halrf_dpk_track(void *dm_void);
-+
-+void halrf_dpk_reload(void *dm_void);
-+
-+void halrf_dpk_switch(void *dm_void, u8 enable);
-+
-+void halrf_dpk_debug_cmd(void *dm_void, char input[][16], u32 *_used,
-+			 char *output, u32 *_out_len);
-+
-+void halrf_dpk_c2h_report_transfer(void	*dm_void, boolean is_ok, u8 *buf, u8 buf_size);
-+
-+void halrf_dpk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size);
-+
-+/*Global function*/
-+
-+void halrf_reload_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num);
-+
-+void halrf_reload_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num,
-+		       u8 ss);
-+
-+void halrf_bp(void *dm_void, u32 *bp_reg, u32 *bp, u32 num);
-+
-+void halrf_bprf(void *dm_void, u32 *bp_reg, u32 bp[][4], u32 num, u8 ss);
-+
-+void halrf_mode(void *dm_void, u32 *i_value, u32 *q_value);
-+
-+boolean halrf_compare(void *dm_void, u32 value);
-+
-+u32 halrf_delta(void *dm_void, u32 v1, u32 v2);
-+
-+void halrf_minmax_compare(void *dm_void, u32 value, u32 *min, u32 *max);
-+
-+void halrf_b_sort(void *dm_void, u32 *iv, u32 *qv);
-+
-+void halrf_bubble(void *dm_void, u32 *v1, u32 *v2);
-+
-+void halrf_swap(void *dm_void, u32 *v1, u32 *v2);
-+
-+enum hal_status
-+halrf_config_rfk_with_header_file(void *dm_void, u32 config_type);
-+
-+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
-+	RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT == 1  || RTL8822C_SUPPORT == 1 ||\
-+	RTL8812F_SUPPORT == 1 || RTL8710C_SUPPORT == 1 ||\
-+	RTL8197G_SUPPORT == 1)
-+void halrf_iqk_dbg(void *dm_void);
-+#endif
-+
-+void halrf_tssi_get_efuse(void *dm_void);
-+
-+void halrf_do_tssi(void *dm_void);
-+
-+void halrf_set_tssi_enable(void *dm_void, boolean enable);
-+
-+void halrf_do_thermal(void *dm_void);
-+
-+u32 halrf_set_tssi_value(void *dm_void, u32 tssi_value);
-+
-+void halrf_set_tssi_power(void *dm_void, s8 power);
-+
-+void halrf_tssi_set_de_for_tx_verify(void *dm_void, u32 tssi_de, u8 path);
-+
-+u32 halrf_query_tssi_value(void *dm_void);
-+
-+void halrf_tssi_cck(void *dm_void);
-+
-+void halrf_thermal_cck(void *dm_void);
-+
-+void halrf_tssi_set_de(void *dm_void);
-+
-+void halrf_tssi_dck(void *dm_void, u8 direct_do);
-+
-+void halrf_calculate_tssi_codeword(void *dm_void);
-+
-+void halrf_set_tssi_codeword(void *dm_void);
-+
-+u8 halrf_get_tssi_codeword_for_txindex(void *dm_void);
-+
-+void halrf_tssi_clean_de(void *dm_void);
-+
-+u32 halrf_tssi_trigger_de(void *dm_void, u8 path);
-+
-+u32 halrf_tssi_get_de(void *dm_void, u8 path);
-+
-+void halrf_tssi_trigger(void *dm_void);
-+
-+void halrf_txgapk_write_gain_table(void *dm_void);
-+
-+void halrf_txgapk_reload_tx_gain(void *dm_void);
-+
-+void halrf_txgap_enable_disable(void *dm_void, u8 enable);
-+
-+void halrf_set_dpk_track(void *dm_void, u8 enable);
-+
-+void halrf_set_dpkbychannel(void *dm_void, boolean dpk_by_ch);
-+
-+void halrf_set_dpkenable(void *dm_void, boolean is_dpk_enable);
-+
-+boolean halrf_get_dpkbychannel(void *dm_void);
-+
-+boolean halrf_get_dpkenable(void *dm_void);
-+
-+void _iqk_check_if_reload(void *dm_void);
-+
-+void halrf_do_rxbb_dck(void *dm_void);
-+
-+void config_halrf_path_adda_setting_trigger(void *dm_void);
-+
-+void halrf_reload_iqk(void *dm_void, boolean reset);
-+
-+void halrf_dack_dbg(void *dm_void);
-+
-+void halrf_dack_trigger(void *dm_void, boolean force);
-+
-+void halrf_dack_restore(void *dm_void);
-+
-+void halrf_iqk_info_rsvd_page(void *dm_void, u8 *buf, u32 *buf_size);
-+
-+void halrf_set_rfsupportability(void *dm_void);
-+
-+void halrf_rxdck(void *dm_void);
-+
-+void halrf_delay_10us(u16 v1);
-+
-+void halrf_dump_rfk_reg(void *dm_void, char input[][16], u32 *_used,
-+			      char *output, u32 *_out_len);
-+
-+void halrf_rfk_power_save(void *dm_void, boolean is_power_save);
-+
-+#endif /*__HALRF_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_debug.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_debug.c
-new file mode 100644
-index 000000000000..692c6f1fc764
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_debug.c
-@@ -0,0 +1,395 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ * ************************************************************
-+ */
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+void halrf_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
-+{
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 rf_release_ver = 0;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8814A_SUPPORT)
-+	case ODM_RTL8814A:
-+		rf_release_ver = RF_RELEASE_VERSION_8814A;
-+		break;
-+#endif
-+
-+#if (RTL8821C_SUPPORT)
-+	case ODM_RTL8821C:
-+		rf_release_ver = RF_RELEASE_VERSION_8821C;
-+		break;
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+	case ODM_RTL8822B:
-+		rf_release_ver = RF_RELEASE_VERSION_8822B;
-+		break;
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	case ODM_RTL8822C:
-+		rf_release_ver = RF_RELEASE_VERSION_8822C;
-+		break;
-+#endif
-+
-+#if (RTL8814B_SUPPORT)
-+	case ODM_RTL8814B:
-+		rf_release_ver = RF_RELEASE_VERSION_8814B;
-+		break;
-+#endif
-+
-+#if (RTL8812F_SUPPORT)
-+	case ODM_RTL8812F:
-+		rf_release_ver = RF_RELEASE_VERSION_8812F;
-+		break;
-+#endif
-+
-+#if (RTL8198F_SUPPORT)
-+	case ODM_RTL8198F:
-+		rf_release_ver = RF_RELEASE_VERSION_8198F;
-+		break;
-+#endif
-+
-+#if (RTL8197F_SUPPORT)
-+	case ODM_RTL8197F:
-+		rf_release_ver = RF_RELEASE_VERSION_8197F;
-+		break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT)
-+	case ODM_RTL8192F:
-+		rf_release_ver = RF_RELEASE_VERSION_8192F;
-+		break;
-+#endif
-+
-+#if (RTL8710B_SUPPORT)
-+	case ODM_RTL8710B:
-+		rf_release_ver = RF_RELEASE_VERSION_8710B;
-+		break;
-+#endif
-+
-+#if (RTL8195B_SUPPORT)
-+	case ODM_RTL8195B:
-+		rf_release_ver = RF_RELEASE_VERSION_8195B;
-+		break;
-+#endif
-+	}
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %d\n",
-+		 "RF Para Release Ver", rf_release_ver);
-+
-+	/* HAL RF version List */
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
-+		 "% HAL RF version %");
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "Power Tracking", HALRF_POWRTRACKING_VER);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "  %-35s: %s %s\n", "IQK",
-+		 (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW" :
-+		 HALRF_IQK_VER,
-+		 (halrf_match_iqk_version(dm_void)) ? "(match)" : "(mismatch)");
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "LCK", HALRF_LCK_VER);
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "DPK", HALRF_DPK_VER);
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "TSSI", HALRF_TSSI_VER);
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "KFREE", HALRF_KFREE_VER);
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "TX 2G Current Calibration", HALRF_PABIASK_VER);
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "RFK Init. Parameter", HALRF_RFK_INIT_VER);
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+#endif
-+}
-+
-+void halrf_debug_trace(void *dm_void, char input[][16], u32 *_used,
-+		       char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	u32 one = 1;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 rf_var[10] = {0};
-+	u8 i;
-+
-+	for (i = 0; i < 5; i++)
-+		if (input[i + 1])
-+			PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &rf_var[i]);
-+
-+	if (rf_var[0] == 100) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\n[DBG MSG] RF Selection\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "00. (( %s ))TX_PWR_TRACK\n",
-+			 ((rf->rf_dbg_comp & DBG_RF_TX_PWR_TRACK) ? ("V") :
-+			 (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "01. (( %s ))IQK\n",
-+			 ((rf->rf_dbg_comp & DBG_RF_IQK) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "02. (( %s ))LCK\n",
-+			 ((rf->rf_dbg_comp & DBG_RF_LCK) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "03. (( %s ))DPK\n",
-+			 ((rf->rf_dbg_comp & DBG_RF_DPK) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "04. (( %s ))TXGAPK\n",
-+			 ((rf->rf_dbg_comp & DBG_RF_TXGAPK) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "06. (( %s ))DPK_TRACK\n",
-+			 ((rf->rf_dbg_comp & DBG_RF_DPK_TRACK) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "29. (( %s ))MP\n",
-+			 ((rf->rf_dbg_comp & DBG_RF_MP) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "30. (( %s ))TMP\n",
-+			 ((rf->rf_dbg_comp & DBG_RF_TMP) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "31. (( %s ))INIT\n",
-+			 ((rf->rf_dbg_comp & DBG_RF_INIT) ? ("V") : (".")));
-+
-+	} else if (rf_var[0] == 101) {
-+		rf->rf_dbg_comp = 0;
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Disable all DBG COMP\n");
-+	} else {
-+		if (rf_var[1] == 1) /*enable*/
-+			rf->rf_dbg_comp |= (one << rf_var[0]);
-+		else if (rf_var[1] == 2) /*disable*/
-+			rf->rf_dbg_comp &= ~(one << rf_var[0]);
-+	}
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\nCurr-RF_Dbg_Comp = 0x%x\n", rf->rf_dbg_comp);
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void halrf_dack_debug_cmd(void *dm_void, char input[][16])
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	u32 dm_value[10] = {0};
-+	u8 i;
-+
-+	for (i = 0; i < 7; i++)
-+		if (input[i + 1])
-+			PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]);
-+
-+	if (dm_value[0] == 1)
-+		halrf_dack_trigger(dm, true);
-+	else			
-+		halrf_dack_trigger(dm, false);	
-+}
-+
-+struct halrf_command {
-+	char name[16];
-+	u8 id;
-+};
-+
-+enum halrf_CMD_ID {
-+	HALRF_HELP,
-+	HALRF_SUPPORTABILITY,
-+	HALRF_DBG_COMP,
-+	HALRF_PROFILE,
-+	HALRF_IQK_INFO,
-+	HALRF_IQK,
-+	HALRF_IQK_DEBUG,
-+	HALRF_DPK,
-+	HALRF_DACK,
-+	HALRF_DACK_DEBUG,
-+	HALRF_DUMP_RFK_REG,
-+#ifdef CONFIG_2G_BAND_SHIFT
-+	HAL_BAND_SHIFT,
-+#endif
-+};
-+
-+struct halrf_command halrf_cmd_ary[] = {
-+	{"-h", HALRF_HELP},
-+	{"ability", HALRF_SUPPORTABILITY},
-+	{"dbg", HALRF_DBG_COMP},
-+	{"profile", HALRF_PROFILE},
-+	{"iqk_info", HALRF_IQK_INFO},
-+	{"iqk", HALRF_IQK},
-+	{"iqk_dbg", HALRF_IQK_DEBUG},
-+	{"dpk", HALRF_DPK},
-+	{"dack", HALRF_DACK},
-+	{"dack_dbg", HALRF_DACK_DEBUG},
-+	{"dump_rfk_reg", HALRF_DUMP_RFK_REG},
-+#ifdef CONFIG_2G_BAND_SHIFT
-+	{"band_shift", HAL_BAND_SHIFT},
-+#endif
-+};
-+
-+void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
-+		      u32 *_out_len, u32 input_num)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+	u8 id = 0;
-+	u32 rf_var[10] = {0};
-+	u32 i, input_idx = 0;
-+	u32 halrf_ary_size =
-+			sizeof(halrf_cmd_ary) / sizeof(struct halrf_command);
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	/* Parsing Cmd ID */
-+	for (i = 0; i < halrf_ary_size; i++) {
-+		if (strcmp(halrf_cmd_ary[i].name, input[1]) == 0) {
-+			id = halrf_cmd_ary[i].id;
-+			break;
-+		}
-+	}
-+
-+	if (i == halrf_ary_size) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "RF Cmd not found\n");
-+		return;
-+	}
-+
-+	switch (id) {
-+	case HALRF_HELP:
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "RF cmd ==>\n");
-+
-+		for (i = 0; i < halrf_ary_size - 1; i++) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "  %-5d: %s\n", i, halrf_cmd_ary[i + 1].name);
-+		}
-+		break;
-+	case HALRF_SUPPORTABILITY:
-+		halrf_support_ability_debug(dm, &input[0], &used, output,
-+					    &out_len);
-+		break;
-+#ifdef CONFIG_2G_BAND_SHIFT
-+	case HAL_BAND_SHIFT:
-+		halrf_support_band_shift_debug(dm, &input[0], &used, output,
-+					       &out_len);
-+		break;
-+#endif
-+	case HALRF_DBG_COMP:
-+		halrf_debug_trace(dm, &input[0], &used, output, &out_len);
-+		break;
-+	case HALRF_PROFILE:
-+		halrf_basic_profile(dm, &used, output, &out_len);
-+		break;
-+	case HALRF_IQK_INFO:
-+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
-+		halrf_iqk_info_dump(dm, &used, output, &out_len);
-+#endif
-+		break;
-+	case HALRF_IQK:
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "TRX IQK Trigger\n");
-+		halrf_iqk_trigger(dm, false);
-+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
-+		halrf_iqk_info_dump(dm, &used, output, &out_len);
-+#endif
-+		break;
-+	case HALRF_IQK_DEBUG:
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "IQK DEBUG!!!!!\n");
-+		for (i = 0; i < 5; i++) {
-+			if (input[i + 1]) {
-+				PHYDM_SSCANF(input[i + 2], DCMD_HEX,
-+					     &rf_var[i]);
-+				input_idx++;
-+			}
-+		}
-+
-+		if (input_idx >= 1) {
-+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-+			if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8822C | ODM_RTL8814B))
-+				halrf_iqk_debug(dm, (u32 *)rf_var, &used,
-+						output, &out_len);
-+#endif
-+		}
-+		break;
-+	case HALRF_DPK:
-+		halrf_dpk_debug_cmd(dm, input, &used, output, &out_len);
-+		break;
-+	case HALRF_DACK:
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "DACK Trigger\n");
-+		halrf_dack_debug_cmd(dm, &input[0]);
-+		break;
-+	case HALRF_DACK_DEBUG:
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "DACK DEBUG\n");
-+		halrf_dack_dbg(dm);
-+		break;
-+	case HALRF_DUMP_RFK_REG:
-+		halrf_dump_rfk_reg(dm, input, &used, output, &out_len);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+#endif
-+}
-+
-+void halrf_init_debug_setting(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	rf->rf_dbg_comp =
-+
-+	DBG_RF_RFK		|
-+#if DBG
-+#if 0
-+	/*DBG_RF_TX_PWR_TRACK	| */
-+	/*DBG_RF_IQK		| */
-+	/*DBG_RF_LCK		| */
-+	/*DBG_RF_DPK		| */
-+	/*DBG_RF_TXGAPK		| */
-+	/*DBG_RF_DACK		| */
-+	/*DBG_RF_DPK_TRACK	| */ 
-+	/*DBG_RF_MP		| */
-+	/*DBG_RF_TMP		| */
-+	/*DBG_RF_INIT		| */
-+#endif
-+#endif
-+	0;
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_debug.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_debug.h
-new file mode 100644
-index 000000000000..c13f3c5677f2
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_debug.h
-@@ -0,0 +1,140 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_DEBUG_H__
-+#define __HALRF_DEBUG_H__
-+
-+/*@============================================================*/
-+/*@include files*/
-+/*@============================================================*/
-+
-+/*@============================================================*/
-+/*@Definition */
-+/*@============================================================*/
-+
-+#if DBG
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+#define RF_DBG(dm, comp, fmt, args...)                     \
-+	do {                                               \
-+		if ((comp) & dm->rf_table.rf_dbg_comp) { \
-+			pr_debug("[RF] ");                 \
-+			RT_PRINTK(fmt, ##args);            \
-+		}                                          \
-+	} while (0)
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+static __inline void RF_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
-+{
-+	RT_STATUS rt_status;
-+	va_list args;
-+	char buf[PRINT_MAX_SIZE] = {0};
-+
-+	if ((comp & dm->rf_table.rf_dbg_comp) == 0)
-+		return;
-+
-+	if (fmt == NULL)
-+		return;
-+
-+	va_start(args, fmt);
-+	rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
-+	va_end(args);
-+
-+	if (rt_status != RT_STATUS_SUCCESS) {
-+		DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
-+		return;
-+	}
-+
-+	DbgPrint("[RF] %s", buf);
-+}
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+
-+#define RF_DBG(dm, comp, fmt, args...)                     \
-+	do {                                               \
-+		if ((comp) & dm->rf_table.rf_dbg_comp) { \
-+			RT_DEBUG(COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args);  \
-+		}                                          \
-+	} while (0)
-+
-+#else
-+#define RF_DBG(dm, comp, fmt, args...)                                         \
-+	do {                                                                   \
-+		struct dm_struct *__dm = dm;                                   \
-+		if ((comp) & __dm->rf_table.rf_dbg_comp) {                     \
-+			RT_TRACE(((struct rtl_priv *)__dm->adapter),           \
-+				 COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args);  \
-+		}                                                              \
-+	} while (0)
-+#endif
-+
-+#else /*#if DBG*/
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+static __inline void RF_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
-+{
-+#if 0
-+	RT_STATUS rt_status;
-+	va_list args;
-+	char buf[128] = {0};/*PRINT_MAX_SIZE*/
-+
-+	if ((comp & dm->rf_table.rf_dbg_comp) == 0)
-+		return;
-+
-+	if (NULL != fmt) {
-+		va_start(args, fmt);
-+		rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, sizeof(buf), fmt, args);
-+		va_end(args);
-+		if (rt_status == RT_STATUS_SUCCESS) {
-+			halrf_rt_trace(buf);
-+		}
-+	}
-+#endif
-+}
-+#else
-+#define RF_DBG(dm, comp, fmt, args...)
-+#endif
-+
-+#endif /*#if DBG*/
-+
-+/*@============================================================*/
-+/*@ enumeration */
-+/*@============================================================*/
-+
-+/*@============================================================*/
-+/*@ structure */
-+/*@============================================================*/
-+
-+/*@============================================================*/
-+/*@ function prototype */
-+/*@============================================================*/
-+
-+void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output,
-+		      u32 *_out_len, u32 input_num);
-+
-+void halrf_init_debug_setting(void *dm_void);
-+
-+#endif /*__HALRF_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_dpk.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_dpk.h
-new file mode 100644
-index 000000000000..44e15ab3ac13
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_dpk.h
-@@ -0,0 +1,150 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_DPK_H__
-+#define __HALRF_DPK_H__
-+
-+/*@--------------------------Define Parameters-------------------------------*/
-+#define GAIN_LOSS 1
-+#define DO_DPK 2
-+#define DPK_ON 3
-+#define GAIN_LOSS_PULSE 4
-+#define DPK_PAS 5
-+#define DPK_LMS 6
-+#define DPK_LOK 4
-+#define DPK_TXK 5
-+#define DAGC 4
-+#define LOSS_CHK 0
-+#define GAIN_CHK 1
-+#define PAS_READ 2
-+#define AVG_THERMAL_NUM 8
-+#define AVG_THERMAL_NUM_DPK 8
-+#define THERMAL_DPK_AVG_NUM 4
-+
-+/*define RF path numer*/
-+#if (RTL8198F_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-+#define KPATH 4
-+#elif (RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1 ||RTL8197G_SUPPORT == 1 ||\
-+	RTL8822C_SUPPORT == 1 || RTL8812F_SUPPORT == 1)
-+#define KPATH 2
-+#else
-+#define KPATH 1
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1 || RTL8721D_SUPPORT == 1)
-+#define GROUP_5G 6
-+#elif (RTL8195B_SUPPORT == 1)
-+#define GROUP_5G 13
-+#endif
-+
-+/*@---------------------------End Define Parameters---------------------------*/
-+
-+struct dm_dpk_info {
-+
-+	boolean	is_dpk_enable;
-+	boolean	is_dpk_pwr_on;
-+	boolean	is_dpk_by_channel;
-+	boolean is_tssi_mode;
-+	u8	dpk_status;			/*bit[0]:reload;bit[1]:cal;bit[2]:cal_ok*/
-+	u16	dpk_path_ok;
-+	/*@BIT(15)~BIT(12) : 5G reserved, BIT(11)~BIT(8) 5G_S3~5G_S0*/
-+	/*@BIT(7)~BIT(4) : 2G reserved, BIT(3)~BIT(0) 2G_S3~2G_S0*/
-+	u8	thermal_dpk[KPATH];					/*path*/	
-+	u8	thermal_dpk_avg[KPATH][AVG_THERMAL_NUM_DPK];	/*path*/
-+	u8	pre_pwsf[KPATH];
-+	u8	thermal_dpk_avg_index;
-+	u32	gnt_control;
-+	u32	gnt_value;
-+	u8	dpk_ch;
-+	u8	dpk_band;
-+	u8	dpk_bw;
-+	u32	dpk_rf18[2];
-+	u32	dpk_cal_cnt;
-+	u32	dpk_ok_cnt;
-+	u32	dpk_reload_cnt;
-+
-+#if (RTL8822C_SUPPORT == 1 || RTL8812F_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
-+	u16	dc_i[2];			/*MDPD DC I path*/
-+	u16	dc_q[2];			/*MDPD DC Q path*/
-+	u8	corr_val[2];			/*Corr value path*/
-+	u8	corr_idx[2];			/*Corr index path*/
-+#endif
-+
-+#if (RTL8822C_SUPPORT == 1 || RTL8812F_SUPPORT == 1)
-+	u8	result[2];			/*path*/
-+	u8	dpk_txagc[2];			/*path*/
-+	u32	coef[2][20];			/*path/MDPD coefficient*/
-+	u16	dpk_gs[2];			/*MDPD coef gs*/
-+	u8	thermal_dpk_delta[2];		/*path*/
-+#endif
-+
-+#if (RTL8198F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT == 1 || RTL8197G_SUPPORT == 1)
-+	/*2G DPK data*/
-+	u8 	dpk_result[KPATH][3];			/*path/group*/
-+	u8 	pwsf_2g[KPATH][3];			/*path/group*/	
-+	u32	lut_2g_even[KPATH][3][64];		/*path/group/LUT data*/
-+	u32	lut_2g_odd[KPATH][3][64];		/*path/group/LUT data*/
-+	s16	tmp_pas_i[32];			/*PAScan I data*/
-+	s16	tmp_pas_q[32];			/*PAScan Q data*/
-+#endif
-+
-+#if (RTL8814B_SUPPORT == 1)
-+	/*5G DPK data*/
-+	u8	dpk_5g_result[KPATH][GROUP_5G];			/*path/group*/
-+	u8	pwsf_5g[KPATH][GROUP_5G];			/*path/group*/
-+	u32	lut_5g[KPATH][GROUP_5G][64];			/*path/group/LUT data*/
-+	u32	lut_2g[KPATH][3][64];			/*path/group/LUT data*/
-+	u8	rxbb[4];			/*path/group*/
-+	u8	txbb[4];			/*path/group*/
-+	u8	tx_gain;
-+#endif
-+
-+#if (RTL8195B_SUPPORT == 1 || RTL8721D_SUPPORT == 1)
-+		u8	dpk_txagc;
-+		/*2G DPK data*/
-+	u8	dpk_2g_result[KPATH][3];			/*path/group*/
-+	u8	pwsf_2g[KPATH][3];			/*path/group*/
-+	u32	lut_2g_even[KPATH][3][16];		/*path/group/LUT data*/
-+	u32	lut_2g_odd[KPATH][3][16];		/*path/group/LUT data*/
-+		/*5G DPK data*/
-+	u8	dpk_5g_result[KPATH][GROUP_5G];			/*path/group*/
-+	u8	pwsf_5g[KPATH][GROUP_5G];			/*path/group*/
-+	u32	lut_5g_even[KPATH][GROUP_5G][16];		/*path/group/LUT data*/
-+	u32	lut_5g_odd[KPATH][GROUP_5G][16];		/*path/group/LUT data*/
-+#endif
-+};
-+
-+#if (RTL8822C_SUPPORT == 1)
-+struct dm_dpk_c2h_report {
-+	u8	result[2];		/*ch0_result/ch1_result*/
-+	u8	therm[2][2];		/*therm0_s0/therm0_s1/therm1_s0/therm1_s1*/
-+	u8	therm_delta[2][2];	/*therm_delta0_s0/therm_delta0_s1/therm_delta1_s0/therm_delta1_s1*/
-+	u32	dpk_rf18[2];		/*dpk_ch0/dpk_ch1*/
-+	u8	dpk_status;		/*dpk_status*/
-+};
-+#endif
-+
-+#endif /*__HALRF_DPK_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_features.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_features.h
-new file mode 100644
-index 000000000000..da97614be1e9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_features.h
-@@ -0,0 +1,43 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_FEATURES_H__
-+#define __HALRF_FEATURES_H__
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+#define CONFIG_HALRF_POWERTRACKING 1
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+
-+#define CONFIG_HALRF_POWERTRACKING 1
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+
-+#define CONFIG_HALRF_POWERTRACKING 1
-+
-+#endif
-+
-+#endif /*#ifndef __HALRF_FEATURES_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_iqk.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_iqk.h
-new file mode 100644
-index 000000000000..eb6579ed2cdc
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_iqk.h
-@@ -0,0 +1,151 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_IQK_H__
-+#define __HALRF_IQK_H__
-+
-+/*@--------------------------Define Parameters-------------------------------*/
-+#define LOK_delay 1
-+#define WBIQK_delay 10
-+#define TX_IQK 0
-+#define RX_IQK 1
-+#define TXIQK 0
-+#define RXIQK1 1
-+#define RXIQK2 2
-+#define kcount_limit_80m 2
-+#define kcount_limit_others 4
-+#define rxiqk_gs_limit 6
-+#define TXWBIQK_EN 1
-+#define RXWBIQK_EN 1
-+#if (RTL8814A_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT)
-+#define NUM 4
-+#elif (RTL8822B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
-+	RTL8812F_SUPPORT == 1 ||	RTL8197G_SUPPORT == 1)
-+#define NUM 2
-+#else
-+#define NUM 1
-+#endif
-+
-+/*@-----------------------End Define Parameters-----------------------*/
-+
-+struct dm_dack_info {
-+	boolean dack_en;
-+	u16 msbk_d[2][2][15];
-+	u8 dck_d[2][2][2];
-+	u16 biask_d[2][2];
-+};
-+
-+struct dm_iqk_info {
-+	boolean lok_fail[NUM];
-+	boolean iqk_fail[2][NUM];
-+	u32 iqc_matrix[2][NUM];
-+	u8 iqk_times;
-+	u32 rf_reg18;
-+	u32 rf_reg08;
-+	u32 lna_idx;
-+	u8 iqk_step;
-+	u8 rxiqk_step;
-+	u8 tmp1bcc;
-+	u8 txgain;
-+	u32 txgain56;
-+	u8 kcount;
-+	u8 rfk_ing; /*bit0:IQKing, bit1:LCKing, bit2:DPKing*/
-+	boolean rfk_forbidden;
-+	u8 rxbb;
-+	u32 rf_reg58;
-+	boolean segment_iqk;
-+	boolean is_tssi_mode;
-+	u8 iqk_band;
-+	u8 iqk_ch;
-+	u8 iqk_bw;
-+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
-+	RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 ||\
-+	RTL8812F_SUPPORT == 1 || RTL8197G_SUPPORT == 1 ||\
-+	RTL8710C_SUPPORT == 1 || RTL8723F_SUPPORT == 1)
-+	u32 iqk_channel[2];
-+	boolean iqk_fail_report[2][NUM][2]; /*channel/path/TRX(TX:0, RX:1) */
-+	/*channel / path / TRX(TX:0, RX:1) / CFIR_real*/
-+	/*channel index = 2 is just for debug*/
-+#if (RTL8814B_SUPPORT == 1)
-+	u16 iqk_cfir_real[3][NUM][2][19];
-+	u16 iqk_cfir_imag[3][NUM][2][19];
-+#elif (RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 )
-+	u16 iqk_cfir_real[3][2][2][17];
-+	/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
-+	/*channel index = 2 is just for debug*/
-+	u16 iqk_cfir_imag[3][2][2][17];
-+	/*times/path*/
-+#elif (RTL8195B_SUPPORT == 1)
-+	u32 iqk_cfir_real[3][NUM][2][9];
-+	u32 iqk_cfir_imag[3][NUM][2][9];
-+	/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
-+	/*channel index = 2 is just for debug*/
-+#else
-+	u32 iqk_cfir_real[3][NUM][2][8];
-+	/*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
-+	/*channel index = 2 is just for debug*/
-+	u32 iqk_cfir_imag[3][NUM][2][8];
-+#endif
-+
-+#if (RTL8812F_SUPPORT == 1 || RTL8822C_SUPPORT == 1 )
-+	u32 rx_cfir_real[2][2][17];
-+	u32 rx_cfir_imag[2][2][17];
-+	u32 rx_cfir[2][2];
-+#endif
-+	u8 retry_count[2][NUM][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
-+	u8 gs_retry_count[2][NUM][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
-+	/* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */
-+	u8 rxiqk_fail_code[2][NUM];
-+	u32 lok_idac[2][NUM]; /*channel / path*/
-+	u16 rxiqk_agc[2][NUM]; /*channel / path*/
-+	u32 bypass_iqk[2][NUM]; /*channel / 0xc94/0xe94*/
-+	u32 txgap_result[8]; /*txagpK result  */
-+	u32 tmp_gntwl;
-+	boolean is_btg;
-+	boolean isbnd;
-+	boolean is_reload;
-+	boolean is_hwtx;
-+	boolean xym_read;
-+	boolean trximr_enable;
-+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT == 1 || RTL8822C_SUPPORT == 1)
-+	u32 rx_xym[2][10];
-+	u32 tx_xym[2][10];
-+	u32 gs1_xym[2][6];
-+	u32 gs2_xym[2][6];
-+	u32 rxk1_xym[2][6];
-+	u32 nbtxk_1b38[2];
-+	u32 nbrxk_1b3c[2];
-+#endif
-+#if (RTL8710C_SUPPORT == 1 || RTL8197G_SUPPORT == 1 )
-+	u32 txxy[2][2];
-+	u32 rxxy[2][2];
-+#endif
-+#endif
-+};
-+
-+#endif /*__HALRF_IQK_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_kfree.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_kfree.c
-new file mode 100644
-index 000000000000..bb18026466d5
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_kfree.c
-@@ -0,0 +1,3705 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@============================================================*/
-+/*@include files*/
-+/*@============================================================*/
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+/*@<YuChen, 150720> Add for KFree Feature Requested by RF David.*/
-+/*@This is a phydm API*/
-+
-+void phydm_set_kfree_to_rf_8814a(void *dm_void, u8 e_rf_path, u8 data)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-+	boolean is_odd;
-+	u32 tx_gain_bitmask = (BIT(17) | BIT(16) | BIT(15));
-+
-+	if ((data % 2) != 0) { /*odd->positive*/
-+		data = data - 1;
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), 1);
-+		is_odd = true;
-+	} else { /*even->negative*/
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), 0);
-+		is_odd = false;
-+	}
-+	RF_DBG(dm, DBG_RF_MP, "phy_ConfigKFree8814A(): RF_0x55[19]= %d\n",
-+	       is_odd);
-+	switch (data) {
-+	case 0:
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0);
-+		cali_info->kfree_offset[e_rf_path] = 0;
-+		break;
-+	case 2:
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0);
-+		cali_info->kfree_offset[e_rf_path] = 0;
-+		break;
-+	case 4:
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 1);
-+		cali_info->kfree_offset[e_rf_path] = 1;
-+		break;
-+	case 6:
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 1);
-+		cali_info->kfree_offset[e_rf_path] = 1;
-+		break;
-+	case 8:
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 2);
-+		cali_info->kfree_offset[e_rf_path] = 2;
-+		break;
-+	case 10:
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 2);
-+		cali_info->kfree_offset[e_rf_path] = 2;
-+		break;
-+	case 12:
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 3);
-+		cali_info->kfree_offset[e_rf_path] = 3;
-+		break;
-+	case 14:
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 3);
-+		cali_info->kfree_offset[e_rf_path] = 3;
-+		break;
-+	case 16:
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 4);
-+		cali_info->kfree_offset[e_rf_path] = 4;
-+		break;
-+	case 18:
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 4);
-+		cali_info->kfree_offset[e_rf_path] = 4;
-+		break;
-+	case 20:
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 5);
-+		cali_info->kfree_offset[e_rf_path] = 5;
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	if (!is_odd) {
-+		/*that means Kfree offset is negative, we need to record it.*/
-+		cali_info->kfree_offset[e_rf_path] =
-+				(-1) * cali_info->kfree_offset[e_rf_path];
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "phy_ConfigKFree8814A(): kfree_offset = %d\n",
-+		       cali_info->kfree_offset[e_rf_path]);
-+	} else {
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "phy_ConfigKFree8814A(): kfree_offset = %d\n",
-+		       cali_info->kfree_offset[e_rf_path]);
-+	}
-+}
-+
-+void phydm_get_thermal_trim_offset_8821c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_therm = 0xff;
-+
-+	odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_21C, &pg_therm, false);
-+
-+	if (pg_therm != 0xff) {
-+		pg_therm = pg_therm & 0x1f;
-+		if ((pg_therm & BIT(0)) == 0)
-+			power_trim_info->thermal = (-1 * (pg_therm >> 1));
-+		else
-+			power_trim_info->thermal = (pg_therm >> 1);
-+
-+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c thermal trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c thermal:%d\n",
-+		       power_trim_info->thermal);
-+}
-+
-+void phydm_get_power_trim_offset_8821c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_power = 0xff, i;
-+
-+	odm_efuse_one_byte_read(dm, PPG_2G_TXAB_21C, &pg_power, false);
-+
-+	if (pg_power != 0xff) {
-+		power_trim_info->bb_gain[0][0] = pg_power;
-+		odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_21C, &pg_power, false);
-+		power_trim_info->bb_gain[1][0] = pg_power;
-+		odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_21C, &pg_power, false);
-+		power_trim_info->bb_gain[2][0] = pg_power;
-+		odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_21C, &pg_power, false);
-+		power_trim_info->bb_gain[3][0] = pg_power;
-+		odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_21C, &pg_power, false);
-+		power_trim_info->bb_gain[4][0] = pg_power;
-+		odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_21C, &pg_power, false);
-+		power_trim_info->bb_gain[5][0] = pg_power;
-+		power_trim_info->flag =
-+			power_trim_info->flag | KFREE_FLAG_ON |
-+			KFREE_FLAG_ON_2G | KFREE_FLAG_ON_5G;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c power trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_ON) {
-+		for (i = 0; i < KFREE_BAND_NUM; i++)
-+			RF_DBG(dm, DBG_RF_MP,
-+			       "[kfree] 8821c pwr_trim->bb_gain[%d][0]=0x%X\n",
-+			       i, power_trim_info->bb_gain[i][0]);
-+	}
-+}
-+
-+void phydm_set_kfree_to_rf_8821c(void *dm_void, u8 e_rf_path, boolean wlg_btg,
-+				 u8 data)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 wlg, btg;
-+	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
-+	u32 s_gain_bmask = (BIT(19) | BIT(18) | BIT(17) |
-+			    BIT(16) | BIT(15) | BIT(14));
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 1);
-+
-+	if (wlg_btg) {
-+		wlg = data & 0xf;
-+		btg = (data & 0xf0) >> 4;
-+
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (wlg & BIT(0)));
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, (wlg >> 1));
-+
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(19), (btg & BIT(0)));
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x65, gain_bmask, (btg >> 1));
-+	} else {
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), data & BIT(0));
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
-+			       ((data & 0x1f) >> 1));
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP,
-+	       "[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n",
-+	       odm_get_rf_reg(dm, e_rf_path, RF_0x55, s_gain_bmask),
-+	       odm_get_rf_reg(dm, e_rf_path, RF_0x65, s_gain_bmask));
-+}
-+
-+void phydm_clear_kfree_to_rf_8821c(void *dm_void, u8 e_rf_path, u8 data)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
-+	u32 s_gain_bmask = (BIT(19) | BIT(18) | BIT(17) |
-+			    BIT(16) | BIT(15) | BIT(14));
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 1);
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, (data >> 1));
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(19), (data & BIT(0)));
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, gain_bmask, (data >> 1));
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 0);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 0);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 0);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 0);
-+
-+	RF_DBG(dm, DBG_RF_MP,
-+	       "[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n",
-+	       odm_get_rf_reg(dm, e_rf_path, RF_0x55, s_gain_bmask),
-+	       odm_get_rf_reg(dm, e_rf_path, RF_0x65, s_gain_bmask));
-+}
-+
-+void phydm_get_thermal_trim_offset_8822b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_therm = 0xff;
-+
-+	odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_22B, &pg_therm, false);
-+
-+	if (pg_therm != 0xff) {
-+		pg_therm = pg_therm & 0x1f;
-+		if ((pg_therm & BIT(0)) == 0)
-+			power_trim_info->thermal = (-1 * (pg_therm >> 1));
-+		else
-+			power_trim_info->thermal = (pg_therm >> 1);
-+
-+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b thermal trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b thermal:%d\n",
-+		       power_trim_info->thermal);
-+}
-+
-+void phydm_get_power_trim_offset_8822b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_power = 0xff, i, j;
-+
-+	odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);
-+
-+	if (pg_power != 0xff) {
-+		/*Path A*/
-+		odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);
-+		power_trim_info->bb_gain[0][0] = (pg_power & 0xf);
-+
-+		/*Path B*/
-+		odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false);
-+		power_trim_info->bb_gain[0][1] = ((pg_power & 0xf0) >> 4);
-+
-+		power_trim_info->flag |= KFREE_FLAG_ON_2G;
-+		power_trim_info->flag |= KFREE_FLAG_ON;
-+	}
-+
-+	odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22B, &pg_power, false);
-+
-+	if (pg_power != 0xff) {
-+		/*Path A*/
-+		odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22B, &pg_power, false);
-+		power_trim_info->bb_gain[1][0] = pg_power;
-+		odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22B, &pg_power, false);
-+		power_trim_info->bb_gain[2][0] = pg_power;
-+		odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22B, &pg_power, false);
-+		power_trim_info->bb_gain[3][0] = pg_power;
-+		odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_22B, &pg_power, false);
-+		power_trim_info->bb_gain[4][0] = pg_power;
-+		odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_22B, &pg_power, false);
-+		power_trim_info->bb_gain[5][0] = pg_power;
-+
-+		/*Path B*/
-+		odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22B, &pg_power, false);
-+		power_trim_info->bb_gain[1][1] = pg_power;
-+		odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22B, &pg_power, false);
-+		power_trim_info->bb_gain[2][1] = pg_power;
-+		odm_efuse_one_byte_read(dm, PPG_5GM1_TXB_22B, &pg_power, false);
-+		power_trim_info->bb_gain[3][1] = pg_power;
-+		odm_efuse_one_byte_read(dm, PPG_5GM2_TXB_22B, &pg_power, false);
-+		power_trim_info->bb_gain[4][1] = pg_power;
-+		odm_efuse_one_byte_read(dm, PPG_5GH1_TXB_22B, &pg_power, false);
-+		power_trim_info->bb_gain[5][1] = pg_power;
-+
-+		power_trim_info->flag |= KFREE_FLAG_ON_5G;
-+		power_trim_info->flag |= KFREE_FLAG_ON;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b power trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (!(power_trim_info->flag & KFREE_FLAG_ON))
-+		return;
-+
-+	for (i = 0; i < KFREE_BAND_NUM; i++) {
-+		for (j = 0; j < 2; j++)
-+			RF_DBG(dm, DBG_RF_MP,
-+			       "[kfree] 8822b PwrTrim->bb_gain[%d][%d]=0x%X\n",
-+			       i, j, power_trim_info->bb_gain[i][j]);
-+	}
-+}
-+
-+void phydm_set_pa_bias_to_rf_8822b(void *dm_void, u8 e_rf_path, s8 tx_pa_bias)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 rf_reg_51 = 0, rf_reg_52 = 0, rf_reg_3f = 0;
-+	u32 tx_pa_bias_bmask = (BIT(12) | BIT(11) | BIT(10) | BIT(9));
-+
-+	rf_reg_51 = odm_get_rf_reg(dm, e_rf_path, RF_0x51, RFREGOFFSETMASK);
-+	rf_reg_52 = odm_get_rf_reg(dm, e_rf_path, RF_0x52, RFREGOFFSETMASK);
-+
-+	RF_DBG(dm, DBG_RF_MP,
-+	       "[kfree] 8822b 2g rf(0x51)=0x%X rf(0x52)=0x%X path=%d\n",
-+	       rf_reg_51, rf_reg_52, e_rf_path);
-+
-+#if 0
-+	/*rf3f => rf52[19:17] = rf3f[2:0] rf52[16:15] = rf3f[4:3] rf52[3:0] = rf3f[8:5]*/
-+	/*rf3f => rf51[6:3] = rf3f[12:9] rf52[13] = rf3f[13]*/
-+#endif
-+	rf_reg_3f = ((rf_reg_52 & 0xe0000) >> 17) |
-+		    (((rf_reg_52 & 0x18000) >> 15) << 3) |
-+		    ((rf_reg_52 & 0xf) << 5) |
-+		    (((rf_reg_51 & 0x78) >> 3) << 9) |
-+		    (((rf_reg_52 & 0x2000) >> 13) << 13);
-+
-+	RF_DBG(dm, DBG_RF_MP,
-+	       "[kfree] 8822b 2g original pa_bias=%d rf_reg_3f=0x%X path=%d\n",
-+	       tx_pa_bias, rf_reg_3f, e_rf_path);
-+
-+	tx_pa_bias = (s8)((rf_reg_3f & tx_pa_bias_bmask) >> 9) + tx_pa_bias;
-+
-+	if (tx_pa_bias < 0)
-+		tx_pa_bias = 0;
-+	else if (tx_pa_bias > 7)
-+		tx_pa_bias = 7;
-+
-+	rf_reg_3f = ((rf_reg_3f & 0xfe1ff) | (tx_pa_bias << 9));
-+
-+	RF_DBG(dm, DBG_RF_MP,
-+	       "[kfree] 8822b 2g 0x%X 0x%X pa_bias=%d rfreg_3f=0x%X path=%d\n",
-+	       PPG_PABIAS_2GA_22B, PPG_PABIAS_2GB_22B,
-+	       tx_pa_bias, rf_reg_3f, e_rf_path);
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(10), 0x1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, BIT(0), 0x1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, BIT(1), 0x1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, (BIT(1) | BIT(0)), 0x3);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(10), 0x0);
-+
-+	RF_DBG(dm, DBG_RF_MP,
-+	       "[kfree] 8822b 2g tx pa bias rf_0x3f(0x%X) path=%d\n",
-+	       odm_get_rf_reg(dm, e_rf_path, RF_0x3f,
-+			      (BIT(12) | BIT(11) | BIT(10) | BIT(9))),
-+			      e_rf_path);
-+}
-+
-+void phydm_get_pa_bias_offset_8822b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_pa_bias = 0xff, e_rf_path = 0;
-+	s8 tx_pa_bias[2] = {0};
-+
-+	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22B, &pg_pa_bias, false);
-+
-+	if (pg_pa_bias != 0xff) {
-+		/*paht a*/
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22B,
-+					&pg_pa_bias, false);
-+		pg_pa_bias = pg_pa_bias & 0xf;
-+
-+		if ((pg_pa_bias & BIT(0)) == 0)
-+			tx_pa_bias[0] = (-1 * (pg_pa_bias >> 1));
-+		else
-+			tx_pa_bias[0] = (pg_pa_bias >> 1);
-+
-+		/*paht b*/
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GB_22B,
-+					&pg_pa_bias, false);
-+		pg_pa_bias = pg_pa_bias & 0xf;
-+
-+		if ((pg_pa_bias & BIT(0)) == 0)
-+			tx_pa_bias[1] = (-1 * (pg_pa_bias >> 1));
-+		else
-+			tx_pa_bias[1] = (pg_pa_bias >> 1);
-+
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] 8822b 2g PathA_pa_bias:%d PathB_pa_bias:%d\n",
-+		       tx_pa_bias[0], tx_pa_bias[1]);
-+
-+		for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
-+			phydm_set_pa_bias_to_rf_8822b(dm, e_rf_path,
-+						      tx_pa_bias[e_rf_path]);
-+
-+		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
-+	} else {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b 2g tx pa bias no pg\n");
-+	}
-+}
-+
-+void phydm_set_kfree_to_rf_8822b(void *dm_void, u8 e_rf_path, u8 data)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
-+		       ((data & 0x1f) >> 1));
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b 0x55[19:14]=0x%X path=%d\n",
-+	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
-+			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
-+			      BIT(15) | BIT(14))), e_rf_path);
-+}
-+
-+void phydm_clear_kfree_to_rf_8822b(void *dm_void, u8 e_rf_path, u8 data)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
-+		       ((data & 0x1f) >> 1));
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 0);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 0);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(7), 0);
-+
-+	RF_DBG(dm, DBG_RF_MP,
-+	       "[kfree] 8822b clear power trim 0x55[19:14]=0x%X path=%d\n",
-+	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
-+			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
-+			      BIT(15) | BIT(14))), e_rf_path);
-+}
-+
-+void phydm_get_thermal_trim_offset_8710b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_therm = 0xff;
-+
-+	odm_efuse_one_byte_read(dm, 0x0EF, &pg_therm, false);
-+
-+	if (pg_therm != 0xff) {
-+		pg_therm = pg_therm & 0x1f;
-+		if ((pg_therm & BIT(0)) == 0)
-+			power_trim_info->thermal = (-1 * (pg_therm >> 1));
-+		else
-+			power_trim_info->thermal = (pg_therm >> 1);
-+
-+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b thermal trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b thermal:%d\n",
-+		       power_trim_info->thermal);
-+}
-+
-+void phydm_get_power_trim_offset_8710b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_power = 0xff;
-+
-+	odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false);
-+
-+	if (pg_power != 0xff) {
-+		/*Path A*/
-+		odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false);
-+		power_trim_info->bb_gain[0][0] = (pg_power & 0xf);
-+
-+		power_trim_info->flag |= KFREE_FLAG_ON_2G;
-+		power_trim_info->flag |= KFREE_FLAG_ON;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b power trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_ON)
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] 8710b power_trim_data->bb_gain[0][0]=0x%X\n",
-+		       power_trim_info->bb_gain[0][0]);
-+}
-+
-+void phydm_set_kfree_to_rf_8710b(void *dm_void, u8 e_rf_path, u8 data)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15));
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, ((data & 0xf) >> 1));
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b 0x55[19:14]=0x%X path=%d\n",
-+	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
-+			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
-+			      BIT(15) | BIT(14))), e_rf_path);
-+}
-+
-+void phydm_clear_kfree_to_rf_8710b(void *dm_void, u8 e_rf_path, u8 data)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14));
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask,
-+		       ((data & 0x1f) >> 1));
-+
-+	RF_DBG(dm, DBG_RF_MP,
-+	       "[kfree] 8710b clear power trim 0x55[19:14]=0x%X path=%d\n",
-+	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
-+			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
-+			      BIT(15) | BIT(14))), e_rf_path);
-+}
-+
-+void phydm_get_thermal_trim_offset_8192f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_therm = 0xff;
-+
-+	odm_efuse_one_byte_read(dm, 0x1EF, &pg_therm, false);
-+
-+	if (pg_therm != 0xff) {
-+		pg_therm = pg_therm & 0x1f;
-+		if ((pg_therm & BIT(0)) == 0)
-+			power_trim_info->thermal = (-1 * (pg_therm >> 1));
-+		else
-+			power_trim_info->thermal = (pg_therm >> 1);
-+
-+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8192f thermal trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8192f thermal:%d\n",
-+		       power_trim_info->thermal);
-+}
-+
-+void phydm_get_power_trim_offset_8192f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_power1 = 0xff, pg_power2 = 0xff, pg_power3 = 0xff, i, j;
-+
-+	odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false); /*CH4-9*/
-+
-+	if (pg_power1 != 0xff) {
-+		/*Path A*/
-+		odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false);
-+		power_trim_info->bb_gain[1][0] = (pg_power1 & 0xf);
-+		/*Path B*/
-+		odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false);
-+		power_trim_info->bb_gain[1][1] = ((pg_power1 & 0xf0) >> 4);
-+
-+		power_trim_info->flag |= KFREE_FLAG_ON_2G;
-+		power_trim_info->flag |= KFREE_FLAG_ON;
-+	}
-+
-+	odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false); /*CH1-3*/
-+
-+	if (pg_power2 != 0xff) {
-+		/*Path A*/
-+		odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false);
-+		power_trim_info->bb_gain[0][0] = (pg_power2 & 0xf);
-+		/*Path B*/
-+		odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false);
-+		power_trim_info->bb_gain[0][1] = ((pg_power2 & 0xf0) >> 4);
-+
-+		power_trim_info->flag |= KFREE_FLAG_ON_2G;
-+		power_trim_info->flag |= KFREE_FLAG_ON;
-+	} else {
-+		power_trim_info->bb_gain[0][0] = (pg_power1 & 0xf);
-+		power_trim_info->bb_gain[0][1] = ((pg_power1 & 0xf0) >> 4);
-+	}
-+
-+	odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false); /*CH10-14*/
-+
-+	if (pg_power3 != 0xff) {
-+		/*Path A*/
-+		odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false);
-+		power_trim_info->bb_gain[2][0] = (pg_power3 & 0xf);
-+		/*Path B*/
-+		odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false);
-+		power_trim_info->bb_gain[2][1] = ((pg_power3 & 0xf0) >> 4);
-+
-+		power_trim_info->flag |= KFREE_FLAG_ON_2G;
-+		power_trim_info->flag |= KFREE_FLAG_ON;
-+	} else {
-+		power_trim_info->bb_gain[2][0] = (pg_power1 & 0xf);
-+		power_trim_info->bb_gain[2][1] = ((pg_power1 & 0xf0) >> 4);
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8192F power trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (!(power_trim_info->flag & KFREE_FLAG_ON))
-+		return;
-+
-+	for (i = 0; i < KFREE_CH_NUM; i++) {
-+		for (j = 0; j < 2; j++)
-+			RF_DBG(dm, DBG_RF_MP,
-+			       "[kfree] 8192F PwrTrim->bb_gain[%d][%d]=0x%X\n",
-+			       i, j, power_trim_info->bb_gain[i][j]);
-+	}
-+}
-+
-+void phydm_set_kfree_to_rf_8192f(void *dm_void, u8 e_rf_path, u8 channel_idx,
-+				 u8 data)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	/*power_trim based on 55[19:14]*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
-+	/*enable 55[14] for 0.5db step*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 1);
-+	/*enter power_trim debug mode*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 1);
-+	/*write enable*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);
-+
-+	if (e_rf_path == 0) {
-+		if (channel_idx == 0) {
-+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);
-+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
-+
-+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);
-+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
-+
-+		} else if (channel_idx == 1) {
-+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);
-+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
-+
-+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);
-+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
-+		} else if (channel_idx == 2) {
-+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);
-+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
-+
-+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);
-+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
-+		}
-+	} else if (e_rf_path == 1) {
-+		if (channel_idx == 0) {
-+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);
-+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
-+
-+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);
-+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
-+		} else if (channel_idx == 1) {
-+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);
-+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
-+
-+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);
-+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
-+		} else if (channel_idx == 2) {
-+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);
-+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
-+
-+			odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);
-+			odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data);
-+		}
-+	}
-+
-+	/*leave power_trim debug mode*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);
-+	/*write disable*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);
-+
-+	RF_DBG(dm, DBG_RF_MP,
-+	       "[kfree] 8192F 0x55[19:14]=0x%X path=%d channel=%d\n",
-+	       odm_get_rf_reg(dm, e_rf_path, RF_0x55,
-+			      (BIT(19) | BIT(18) | BIT(17) | BIT(16) |
-+			      BIT(15) | BIT(14))), e_rf_path, channel_idx);
-+}
-+
-+#if 0
-+/*
-+void phydm_clear_kfree_to_rf_8192f(void *dm_void, u8 e_rf_path, u8 data)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct	*cali_info = &dm->rf_calibrate_info;
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0)));
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1));
-+
-+	RF_DBG(dm, DBG_RF_MP,
-+		"[kfree] 8192F clear power trim 0x55[19:14]=0x%X path=%d\n",
-+		odm_get_rf_reg(dm, e_rf_path, RF_0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
-+		e_rf_path
-+		);
-+}
-+*/
-+#endif
-+
-+void phydm_get_thermal_trim_offset_8198f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_therm = 0;
-+
-+	odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_98F, &pg_therm, false);
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f efuse thermal trim 0x%X=0x%X\n",
-+		PPG_THERMAL_OFFSET_98F, pg_therm);
-+
-+	if (pg_therm != 0) {
-+		pg_therm = pg_therm & 0x1f;
-+		if ((pg_therm & BIT(0)) == 0)
-+			power_trim_info->thermal = (-1 * (pg_therm >> 1));
-+		else
-+			power_trim_info->thermal = (pg_therm >> 1);
-+
-+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f thermal trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f thermal:%d\n",
-+		       power_trim_info->thermal);
-+}
-+
-+void phydm_get_power_trim_offset_8198f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 i, j;
-+	u8 power_trim[6] = {0};
-+
-+	odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_98F, &power_trim[0], false);
-+	odm_efuse_one_byte_read(dm, PPG_2GL_TXCD_98F, &power_trim[1], false);
-+	odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_98F, &power_trim[2], false);
-+	odm_efuse_one_byte_read(dm, PPG_2GM_TXCD_98F, &power_trim[3], false);
-+	odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_98F, &power_trim[4], false);
-+	odm_efuse_one_byte_read(dm, PPG_2GH_TXCD_98F, &power_trim[5], false);
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f efuse Power Trim 0x%X=0x%X 0x%X=0x%X 0x%X=0x%X 0x%X=0x%X 0x%X=0x%X 0x%X=0x%X\n",
-+		PPG_2GL_TXAB_98F, power_trim[0],
-+		PPG_2GL_TXCD_98F, power_trim[1],
-+		PPG_2GM_TXAB_98F, power_trim[2],
-+		PPG_2GM_TXCD_98F, power_trim[3],
-+		PPG_2GH_TXAB_98F, power_trim[4],
-+		PPG_2GH_TXCD_98F, power_trim[5]
-+		);
-+
-+	j = 0;
-+	for (i = 0; i < 6; i++) {
-+		if (power_trim[i] == 0x0)
-+			j++;
-+	}
-+
-+	if (j == 6) {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f Power Trim no pg\n");
-+	} else {
-+		power_trim_info->bb_gain[0][0] = power_trim[0] & 0xf;
-+		power_trim_info->bb_gain[0][1] = (power_trim[0] & 0xf0) >> 4;
-+
-+		power_trim_info->bb_gain[0][2] = power_trim[1] & 0xf;
-+		power_trim_info->bb_gain[0][3] = (power_trim[1] & 0xf0) >> 4;
-+
-+		power_trim_info->bb_gain[1][0] = power_trim[2] & 0xf;
-+		power_trim_info->bb_gain[1][1] = (power_trim[2] & 0xf0) >> 4;
-+
-+		power_trim_info->bb_gain[1][2] = power_trim[3] & 0xf;
-+		power_trim_info->bb_gain[1][3] = (power_trim[3] & 0xf0) >> 4;
-+
-+		power_trim_info->bb_gain[2][0] = power_trim[4] & 0xf;
-+		power_trim_info->bb_gain[2][1] = (power_trim[4] & 0xf0) >> 4;
-+
-+		power_trim_info->bb_gain[2][2] = power_trim[5] & 0xf;
-+		power_trim_info->bb_gain[2][3] = (power_trim[5] & 0xf0) >> 4;
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f power trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_ON) {
-+		for (i = 0; i < KFREE_BAND_NUM; i++) {
-+			for (j = 0; j < MAX_RF_PATH; j++) {
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 8198f pwr_trim->bb_gain[%d][%d]=0x%X\n",
-+				       i, j, power_trim_info->bb_gain[i][j]);
-+			}
-+		}
-+	}
-+}
-+
-+void phydm_get_pa_bias_offset_8198f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 i, j;
-+	u8 pa_bias[2] = {0};
-+	u8 tx_pa_bias[4] = {0};
-+
-+	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GAB_98F, &pa_bias[0], false);
-+	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GCD_98F, &pa_bias[1], false);
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f efuse Tx PA Bias 0x%X=0x%X 0x%X=0x%X\n",
-+		PPG_PABIAS_2GAB_98F, pa_bias[0], PPG_PABIAS_2GCD_98F, pa_bias[1]);
-+
-+	j = 0;
-+	for (i = 0; i < 2; i++) {
-+		if (pa_bias[i] == 0x0)
-+			j++;
-+	}
-+
-+	if (j == 2) {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f Tx PA Bias no pg\n");
-+	} else {
-+		/*paht ab*/
-+		tx_pa_bias[0] = pa_bias[0] & 0xf;
-+		tx_pa_bias[1] = ((pa_bias[0] & 0xf0) >> 4);
-+
-+		/*paht cd*/
-+		tx_pa_bias[2] = pa_bias[1] & 0xf;
-+		tx_pa_bias[3] = ((pa_bias[1] & 0xf0) >> 4);
-+
-+		for (i = RF_PATH_A; i < 4; i++) {
-+			if ((tx_pa_bias[i] & 0x1) == 1)
-+				tx_pa_bias[i] = tx_pa_bias[i] & 0xe;
-+			else
-+				tx_pa_bias[i] = tx_pa_bias[i] | 0x1;
-+		}
-+
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] 8198f PathA_pa_bias:0x%x PathB_pa_bias:0x%x\n",
-+		       tx_pa_bias[0], tx_pa_bias[1]);
-+
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] 8198f PathC_pa_bias:0x%x PathD_pa_bias:0x%x\n",
-+		       tx_pa_bias[2], tx_pa_bias[3]);
-+
-+		for (i = RF_PATH_A; i < 4; i++)
-+			odm_set_rf_reg(dm, i, 0x60, 0x0000f000, tx_pa_bias[i]);
-+
-+		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
-+	}
-+}
-+
-+void phydm_get_set_lna_offset_8198f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 i, j;
-+	u8 lna_trim[4] = {0};
-+	u8 cg[4] = {0}, cs[4] = {0};
-+	u32 rf_reg;
-+
-+	odm_efuse_one_byte_read(dm, PPG_LNA_2GA_98F, &lna_trim[0], false);
-+	odm_efuse_one_byte_read(dm, PPG_LNA_2GB_98F, &lna_trim[1], false);
-+	odm_efuse_one_byte_read(dm, PPG_LNA_2GC_98F, &lna_trim[2], false);
-+	odm_efuse_one_byte_read(dm, PPG_LNA_2GD_98F, &lna_trim[3], false);
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f efuse LNA Trim 0x%X=0x%X 0x%X=0x%X 0x%X=0x%X 0x%X=0x%X\n",
-+		PPG_LNA_2GA_98F, lna_trim[0],
-+		PPG_LNA_2GB_98F, lna_trim[1],
-+		PPG_LNA_2GC_98F, lna_trim[2],
-+		PPG_LNA_2GD_98F, lna_trim[3]
-+		);
-+
-+	j = 0;
-+	for (i = 0; i < 4; i++) {
-+		if (lna_trim[i] == 0x0)
-+			j++;
-+	}
-+
-+	if (j == 4) {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8198f LNA no pg\n");
-+	} else {
-+
-+		for (i = 0; i < 4; i++) {
-+			cg[i] = (lna_trim[i] & 0xc) >> 2;
-+			cs[i] = lna_trim[i] & 0x3;
-+		}
-+
-+		for (i = RF_PATH_A; i <= RF_PATH_D; i++) {
-+			RF_DBG(dm, DBG_RF_MP,
-+				"[kfree] 8198f lna cg[%d]=0x%x cs[%d]=0x%x\n",
-+				i, cg[i], i, cs[i]);
-+			odm_set_rf_reg(dm, i, 0xdf, RFREGOFFSETMASK, 0x2);
-+
-+			if (cg[i] == 0x3) {
-+				rf_reg = odm_get_rf_reg(dm, i, 0x86, (BIT(19) | BIT(18)));
-+				rf_reg = rf_reg + 1;
-+				if (rf_reg >= 0x3)
-+					rf_reg = 0x3;
-+				odm_set_rf_reg(dm, i, 0x86, (BIT(19) | BIT(18)), rf_reg);
-+				RF_DBG(dm, DBG_RF_MP,
-+					"[kfree] 8198f lna CG set rf 0x86 [19:18]=0x%x path=%d\n", rf_reg, i);
-+			}
-+			if (cs[i] == 0x3) {
-+				rf_reg = odm_get_rf_reg(dm, i, 0x86, (BIT(17) | BIT(16)));
-+				rf_reg = rf_reg + 1;
-+				if (rf_reg >= 0x3)
-+					rf_reg = 0x3;
-+				odm_set_rf_reg(dm, i, 0x86, (BIT(17) | BIT(16)), rf_reg);
-+				RF_DBG(dm, DBG_RF_MP,
-+					"[kfree] 8198f lna CS set rf 0x86 [17:16]=0x%x path=%d\n", rf_reg, i);
-+			}	
-+		}
-+
-+		power_trim_info->lna_flag |= LNA_FLAG_ON;
-+	}
-+}
-+
-+
-+void phydm_set_kfree_to_rf_8198f(void *dm_void, u8 e_rf_path, u8 data)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+	u32 i;
-+	s8 pwr_offset[3];
-+
-+	RF_DBG(dm, DBG_RF_MP,
-+		   "[kfree] %s:Set kfree to rf 0x33\n", __func__);
-+
-+	/*power_trim based on 55[19:14]*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
-+	/*enable 55[14] for 0.5db step*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 1);
-+	/*enter power_trim debug mode*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);
-+	/*write enable*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);
-+
-+	for (i =0; i < 3; i++)
-+		pwr_offset[i] = power_trim_info->bb_gain[i][e_rf_path];
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[0]);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[0]);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[1]);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[1]);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[2]);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, pwr_offset[2]);
-+
-+	/*leave power_trim debug mode*/
-+	/*odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);*/
-+	/*write disable*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);
-+
-+}
-+
-+void phydm_clear_kfree_to_rf_8198f(void *dm_void, u8 e_rf_path, u8 data)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if 0
-+
-+	RF_DBG(dm, DBG_RF_MP,
-+		   "[kfree] %s:Clear kfree to rf 0x55\n", __func__);
-+
-+	/*power_trim based on 55[19:14]*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1);
-+	/*enable 55[14] for 0.5db step*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 1);
-+	/*enter power_trim debug mode*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);
-+	/*write enable*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5);
-+	odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, data);
-+
-+	/*leave power_trim debug mode*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0);
-+	/*enable 55[14] for 0.5db step*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 0);
-+	/*write disable*/
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);
-+
-+	odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 1);
-+	/*odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 0);*/
-+
-+#endif
-+
-+}
-+
-+void phydm_get_set_thermal_trim_offset_8822c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_therm = 0xff, thermal[2] = {0};
-+
-+	odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_22C, &pg_therm, false);
-+
-+	if (pg_therm != 0xff) {
-+		/*s0*/
-+		pg_therm = pg_therm & 0x1f;
-+
-+		thermal[RF_PATH_A] =
-+			((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);
-+
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x43, 0x000f0000, thermal[RF_PATH_A]);
-+
-+		/*s1*/
-+		odm_efuse_one_byte_read(dm, PPG_THERMAL_B_OFFSET_22C, &pg_therm, false);
-+
-+		pg_therm = pg_therm & 0x1f;
-+
-+		thermal[RF_PATH_B] = ((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);
-+
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x43, 0x000f0000, thermal[RF_PATH_B]);
-+
-+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
-+
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c thermal trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c thermalA:%d thermalB:%d\n",
-+			thermal[RF_PATH_A],
-+			thermal[RF_PATH_B]);	
-+}
-+
-+void phydm_set_power_trim_offset_8822c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+	u8 e_rf_path;
-+
-+	for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
-+	{
-+		odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 1);
-+
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[0][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x1);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[1][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x2);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[2][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x3);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[2][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x4);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[3][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x5);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[4][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x6);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[5][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x7);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[6][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x8);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[7][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x9);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[3][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xa);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[4][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xb);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[5][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xc);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[6][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xd);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[7][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xe);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[7][e_rf_path]);
-+
-+		odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 0);
-+	}
-+}
-+
-+void phydm_get_set_power_trim_offset_8822c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_power = 0xff, i, j;
-+	u8 pg_power1, pg_power2 , pg_power3, pg_power4, pg_power5;
-+
-+	odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_22C, &pg_power1, false);
-+	odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_22C, &pg_power2, false);
-+	odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_22C, &pg_power3, false);
-+	odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power4, false);
-+	odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power5, false);
-+
-+	if (pg_power1 != 0xff || pg_power2 != 0xff || pg_power3 != 0xff ||
-+		pg_power4 != 0xff || pg_power5 != 0xff) {
-+		odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[0][0] = pg_power & 0xf;
-+		power_trim_info->bb_gain[0][1] = (pg_power & 0xf0) >> 4;
-+
-+		odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[1][0] = pg_power & 0xf;
-+		power_trim_info->bb_gain[1][1] = (pg_power & 0xf0) >> 4;
-+
-+		odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[2][0] = pg_power & 0xf;
-+		power_trim_info->bb_gain[2][1] = (pg_power & 0xf0) >> 4;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[3][0] = pg_power & 0x1f;
-+		odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[3][1] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[4][0] = pg_power & 0x1f;
-+		odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[4][1] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[5][0] = pg_power & 0x1f;
-+		odm_efuse_one_byte_read(dm, PPG_5GM1_TXB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[5][1] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[6][0] = pg_power & 0x1f;
-+		odm_efuse_one_byte_read(dm, PPG_5GM2_TXB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[6][1] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[7][0] = pg_power & 0x1f;
-+		odm_efuse_one_byte_read(dm, PPG_5GH1_TXB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[7][1] = pg_power & 0x1f;
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | KFREE_FLAG_ON |
-+						KFREE_FLAG_ON_2G |
-+						KFREE_FLAG_ON_5G;
-+
-+		phydm_set_power_trim_offset_8822c(dm);
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c power trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_ON) {
-+		for (i = 0; i < KFREE_BAND_NUM; i++) {
-+			for (j = 0; j < 2; j++) {
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 8822c pwr_trim->bb_gain[%d][%d]=0x%X\n",
-+				       i, j, power_trim_info->bb_gain[i][j]);
-+			}
-+		}
-+	}
-+}
-+
-+void phydm_get_tssi_trim_offset_8822c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 i, j;
-+	u8 pg_power[16] = {0};
-+
-+	odm_efuse_one_byte_read(dm, TSSI_2GM_TXA_22C, &pg_power[0], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GM_TXB_22C, &pg_power[1], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GH_TXA_22C, &pg_power[2], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GH_TXB_22C, &pg_power[3], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GL1_TXA_22C, &pg_power[4], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GL1_TXB_22C, &pg_power[5], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GL2_TXA_22C, &pg_power[6], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GL2_TXB_22C, &pg_power[7], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM1_TXA_22C, &pg_power[8], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM1_TXB_22C, &pg_power[9], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM2_TXA_22C, &pg_power[10], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM2_TXB_22C, &pg_power[11], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH1_TXA_22C, &pg_power[12], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH1_TXB_22C, &pg_power[13], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH2_TXA_22C, &pg_power[14], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH2_TXB_22C, &pg_power[15], false);
-+
-+	j = 0;
-+	for (i = 0; i < 16; i++) {
-+		if (pg_power[i] == 0xff)
-+			j++;
-+	}
-+
-+	if (j == 16) {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c tssi trim no PG\n");
-+	} else {
-+		power_trim_info->tssi_trim[0][0] = (s8)pg_power[0];
-+		power_trim_info->tssi_trim[0][1] = (s8)pg_power[1];
-+		power_trim_info->tssi_trim[1][0] = (s8)pg_power[0];
-+		power_trim_info->tssi_trim[1][1] = (s8)pg_power[1];
-+		power_trim_info->tssi_trim[2][0] = (s8)pg_power[2];
-+		power_trim_info->tssi_trim[2][1] = (s8)pg_power[3];
-+		power_trim_info->tssi_trim[3][0] = (s8)pg_power[4];
-+		power_trim_info->tssi_trim[3][1] = (s8)pg_power[5];
-+		power_trim_info->tssi_trim[4][0] = (s8)pg_power[6];
-+		power_trim_info->tssi_trim[4][1] = (s8)pg_power[7];
-+		power_trim_info->tssi_trim[5][0] = (s8)pg_power[8];
-+		power_trim_info->tssi_trim[5][1] = (s8)pg_power[9];
-+		power_trim_info->tssi_trim[6][0] = (s8)pg_power[10];
-+		power_trim_info->tssi_trim[6][1] = (s8)pg_power[11];
-+		power_trim_info->tssi_trim[7][0] = (s8)pg_power[12];
-+		power_trim_info->tssi_trim[7][1] = (s8)pg_power[13];
-+		power_trim_info->tssi_trim[8][0] = (s8)pg_power[14];
-+		power_trim_info->tssi_trim[8][1] = (s8)pg_power[15];
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | TSSI_TRIM_FLAG_ON;
-+
-+		if (power_trim_info->flag & TSSI_TRIM_FLAG_ON) {
-+			for (i = 0; i < KFREE_BAND_NUM; i++) {
-+				for (j = 0; j < 2; j++) {
-+					RF_DBG(dm, DBG_RF_MP,
-+					       "[kfree] 8822c tssi_trim[%d][%d]=0x%X\n",
-+					       i, j, power_trim_info->tssi_trim[i][j]);
-+				}
-+			}
-+		}
-+	}
-+}
-+
-+s8 phydm_get_tssi_trim_de_8822c(void *dm_void, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 channel = *dm->channel, group = 0;
-+
-+	if (channel >= 1 && channel <= 3)
-+		group = 0;
-+	else if (channel >= 4 && channel <= 9)
-+		group = 1;
-+	else if (channel >= 10 && channel <= 14)
-+		group = 2;
-+	else if (channel >= 36 && channel <= 50)
-+		group = 3;
-+	else if (channel >= 52 && channel <= 64)
-+		group = 4;
-+	else if (channel >= 100 && channel <= 118)
-+		group = 5;
-+	else if (channel >= 120 && channel <= 144)
-+		group = 6;
-+	else if (channel >= 149 && channel <= 165)
-+		group = 7;
-+	else if (channel >= 167 && channel <= 177)
-+		group = 8;
-+	else {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] Channel(%d) is not exist in Group\n",
-+			channel);
-+		return 0;
-+	}
-+
-+	return power_trim_info->tssi_trim[group][path];
-+}
-+
-+
-+
-+void phydm_get_set_pa_bias_offset_8822c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_pa_bias = 0xff;
-+
-+	RF_DBG(dm, DBG_RF_MP, "======>%s\n", __func__);
-+
-+	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22C, &pg_pa_bias, false);
-+
-+	if (pg_pa_bias != 0xff) {
-+		/*2G s0*/
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22C,
-+					&pg_pa_bias, false);
-+		pg_pa_bias = pg_pa_bias & 0xf;
-+
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 2G s0 pa_bias=0x%x\n", pg_pa_bias);
-+
-+		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, pg_pa_bias);
-+
-+		/*2G s1*/
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GB_22C,
-+					&pg_pa_bias, false);
-+		pg_pa_bias = pg_pa_bias & 0xf;
-+
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 2G s1 pa_bias=0x%x\n", pg_pa_bias);
-+
-+		odm_set_rf_reg(dm, RF_PATH_B, 0x60, 0x0000f000, pg_pa_bias);
-+
-+		/*5G s0*/
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_22C,
-+					&pg_pa_bias, false);
-+		pg_pa_bias = pg_pa_bias & 0xf;
-+
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 5G s0 pa_bias=0x%x\n", pg_pa_bias);
-+
-+		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x000f0000, pg_pa_bias);
-+
-+		/*5G s1*/
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_5GB_22C,
-+					&pg_pa_bias, false);
-+		pg_pa_bias = pg_pa_bias & 0xf;
-+
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 5G s1 pa_bias=0x%x\n", pg_pa_bias);
-+
-+		odm_set_rf_reg(dm, RF_PATH_B, 0x60, 0x000f0000, pg_pa_bias);
-+
-+		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
-+	} else {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8822c tx pa bias no pg\n");
-+	}
-+
-+}
-+
-+void phydm_get_set_thermal_trim_offset_8812f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_therm = 0xff, thermal[2] = {0};
-+
-+	odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_22C, &pg_therm, false);
-+
-+	if (pg_therm != 0xff && pg_therm != 0x0) {
-+		/*s0*/
-+		pg_therm = pg_therm & 0x1f;
-+
-+		thermal[RF_PATH_A] =
-+			((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);
-+
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x43, 0x000f0000, thermal[RF_PATH_A]);
-+
-+		/*s1*/
-+		odm_efuse_one_byte_read(dm, PPG_THERMAL_B_OFFSET_22C, &pg_therm, false);
-+
-+		pg_therm = pg_therm & 0x1f;
-+
-+		thermal[RF_PATH_B] = ((pg_therm & 0x1) << 3) | ((pg_therm >> 1) & 0x7);
-+
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x43, 0x000f0000, thermal[RF_PATH_B]);
-+
-+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
-+
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f thermal trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f thermalA:%d thermalB:%d\n",
-+			thermal[RF_PATH_A],
-+			thermal[RF_PATH_B]);	
-+}
-+
-+void phydm_set_power_trim_offset_8812f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+	u8 e_rf_path;
-+
-+	for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
-+	{
-+		odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 1);
-+
-+#if 0
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[0][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x1);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[1][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x2);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[2][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x3);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[2][e_rf_path]);
-+#endif
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x4);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[3][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x5);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[4][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x6);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[5][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x7);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[6][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x8);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[7][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x9);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[3][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xa);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[4][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xb);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[5][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xc);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[6][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xd);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[7][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xe);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK,
-+			power_trim_info->bb_gain[7][e_rf_path]);
-+
-+		odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 0);
-+	}
-+}
-+
-+void phydm_get_set_power_trim_offset_8812f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_power = 0xff, i, j;
-+	u8 pg_power1 = 0, pg_power2 = 0, pg_power3 = 0;
-+	u8 pg_power4 = 0, pg_power5 = 0;
-+
-+	odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power1, false);
-+	odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power2, false);
-+	odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22C, &pg_power3, false);
-+	odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22C, &pg_power4, false);
-+	odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22C, &pg_power5, false);
-+
-+	if ((pg_power1 != 0xff || pg_power2 != 0xff || pg_power3 != 0xff ||
-+		pg_power4 != 0xff || pg_power5 != 0xff) &&
-+		(pg_power1 != 0x0 || pg_power2 != 0x0 || pg_power3 != 0x0 ||
-+		pg_power4 != 0x0 || pg_power5 != 0x0)) {
-+#if 0
-+		odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[0][0] = pg_power & 0xf;
-+		power_trim_info->bb_gain[0][1] = (pg_power & 0xf0) >> 4;
-+
-+		odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[1][0] = pg_power & 0xf;
-+		power_trim_info->bb_gain[1][1] = (pg_power & 0xf0) >> 4;
-+
-+		odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[2][0] = pg_power & 0xf;
-+		power_trim_info->bb_gain[2][1] = (pg_power & 0xf0) >> 4;
-+#endif
-+		odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[3][0] = pg_power & 0x1f;
-+		odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[3][1] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[4][0] = pg_power & 0x1f;
-+		odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[4][1] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[5][0] = pg_power & 0x1f;
-+		odm_efuse_one_byte_read(dm, PPG_5GM1_TXB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[5][1] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[6][0] = pg_power & 0x1f;
-+		odm_efuse_one_byte_read(dm, PPG_5GM2_TXB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[6][1] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[7][0] = pg_power & 0x1f;
-+		odm_efuse_one_byte_read(dm, PPG_5GH1_TXB_22C, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[7][1] = pg_power & 0x1f;
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_5G;
-+
-+		phydm_set_power_trim_offset_8812f(dm);
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f power trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_ON) {
-+		for (i = 0; i < KFREE_BAND_NUM; i++) {
-+			for (j = 0; j < 2; j++) {
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 8812f pwr_trim->bb_gain[%d][%d]=0x%X\n",
-+				       i, j, power_trim_info->bb_gain[i][j]);
-+			}
-+		}
-+	}
-+}
-+
-+void phydm_get_tssi_trim_offset_8812f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 i, j ;
-+	u8 pg_power[16] = {0};
-+
-+#if 0
-+	odm_efuse_one_byte_read(dm, TSSI_2GM_TXA_22C, &pg_power[0], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GM_TXB_22C, &pg_power[1], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GH_TXA_22C, &pg_power[2], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GH_TXB_22C, &pg_power[3], false);
-+#endif
-+	odm_efuse_one_byte_read(dm, TSSI_5GL1_TXA_22C, &pg_power[4], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GL1_TXB_22C, &pg_power[5], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GL2_TXA_22C, &pg_power[6], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GL2_TXB_22C, &pg_power[7], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM1_TXA_22C, &pg_power[8], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM1_TXB_22C, &pg_power[9], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM2_TXA_22C, &pg_power[10], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM2_TXB_22C, &pg_power[11], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH1_TXA_22C, &pg_power[12], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH1_TXB_22C, &pg_power[13], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH2_TXA_22C, &pg_power[14], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH2_TXB_22C, &pg_power[15], false);
-+
-+	j = 0;
-+	for (i = 4; i < 16; i++) {
-+		if (pg_power[i] == 0xff || pg_power[i] == 0x0)
-+			j++;
-+	}
-+
-+	if (j == 12) {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f tssi trim no PG\n");
-+	} else {
-+#if 0
-+		power_trim_info->tssi_trim[0][0] = (s8)pg_power[0];
-+		power_trim_info->tssi_trim[0][1] = (s8)pg_power[1];
-+		power_trim_info->tssi_trim[1][0] = (s8)pg_power[0];
-+		power_trim_info->tssi_trim[1][1] = (s8)pg_power[1];
-+		power_trim_info->tssi_trim[2][0] = (s8)pg_power[2];
-+		power_trim_info->tssi_trim[2][1] = (s8)pg_power[3];
-+#endif
-+		power_trim_info->tssi_trim[3][0] = (s8)pg_power[4];
-+		power_trim_info->tssi_trim[3][1] = (s8)pg_power[5];
-+		power_trim_info->tssi_trim[4][0] = (s8)pg_power[6];
-+		power_trim_info->tssi_trim[4][1] = (s8)pg_power[7];
-+		power_trim_info->tssi_trim[5][0] = (s8)pg_power[8];
-+		power_trim_info->tssi_trim[5][1] = (s8)pg_power[9];
-+		power_trim_info->tssi_trim[6][0] = (s8)pg_power[10];
-+		power_trim_info->tssi_trim[6][1] = (s8)pg_power[11];
-+		power_trim_info->tssi_trim[7][0] = (s8)pg_power[12];
-+		power_trim_info->tssi_trim[7][1] = (s8)pg_power[13];
-+		power_trim_info->tssi_trim[8][0] = (s8)pg_power[14];
-+		power_trim_info->tssi_trim[8][1] = (s8)pg_power[15];
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | TSSI_TRIM_FLAG_ON;
-+
-+		if (power_trim_info->flag & TSSI_TRIM_FLAG_ON) {
-+			for (i = 0; i < KFREE_BAND_NUM; i++) {
-+				for (j = 0; j < 2; j++) {
-+					RF_DBG(dm, DBG_RF_MP,
-+					       "[kfree] 8812f tssi_trim[%d][%d]=0x%X\n",
-+					       i, j, power_trim_info->tssi_trim[i][j]);
-+				}
-+			}
-+		}
-+	}
-+}
-+
-+s8 phydm_get_tssi_trim_de_8812f(void *dm_void, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 channel = *dm->channel, group = 0;
-+
-+	if (channel >= 1 && channel <= 3)
-+		group = 0;
-+	else if (channel >= 4 && channel <= 9)
-+		group = 1;
-+	else if (channel >= 10 && channel <= 14)
-+		group = 2;
-+	else if (channel >= 36 && channel <= 50)
-+		group = 3;
-+	else if (channel >= 52 && channel <= 64)
-+		group = 4;
-+	else if (channel >= 100 && channel <= 118)
-+		group = 5;
-+	else if (channel >= 120 && channel <= 144)
-+		group = 6;
-+	else if (channel >= 149 && channel <= 165)
-+		group = 7;
-+	else if (channel >= 167 && channel <= 177)
-+		group = 8;
-+	else {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] Channel(%d) is not exist in Group\n",
-+			channel);
-+		return 0;
-+	}
-+
-+	return power_trim_info->tssi_trim[group][path];
-+}
-+
-+void phydm_get_set_pa_bias_offset_8812f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_pa_bias = 0xff;
-+
-+	RF_DBG(dm, DBG_RF_MP, "======>%s\n", __func__);
-+
-+	odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_22C, &pg_pa_bias, false);
-+
-+	if (pg_pa_bias != 0xff && pg_pa_bias != 0x0) {
-+#if 0
-+		/*2G s0*/
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22C,
-+					&pg_pa_bias, false);
-+		pg_pa_bias = pg_pa_bias & 0xf;
-+
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 2G s0 pa_bias=0x%x\n", pg_pa_bias);
-+
-+		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, pg_pa_bias);
-+
-+		/*2G s1*/
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GB_22C,
-+					&pg_pa_bias, false);
-+		pg_pa_bias = pg_pa_bias & 0xf;
-+
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 2G s1 pa_bias=0x%x\n", pg_pa_bias);
-+
-+		odm_set_rf_reg(dm, RF_PATH_B, 0x60, 0x0000f000, pg_pa_bias);
-+#endif
-+
-+		/*5G s0*/
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_22C,
-+					&pg_pa_bias, false);
-+		pg_pa_bias = pg_pa_bias & 0xf;
-+
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 5G s0 pa_bias=0x%x\n", pg_pa_bias);
-+
-+		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x000f0000, pg_pa_bias);
-+
-+		/*5G s1*/
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_5GB_22C,
-+					&pg_pa_bias, false);
-+		pg_pa_bias = pg_pa_bias & 0xf;
-+
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 5G s1 pa_bias=0x%x\n", pg_pa_bias);
-+
-+		odm_set_rf_reg(dm, RF_PATH_B, 0x60, 0x000f0000, pg_pa_bias);
-+
-+		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
-+	} else {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8812f tx pa bias no pg\n");
-+	}
-+
-+}
-+
-+void phydm_get_thermal_trim_offset_8195b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_therm = 0xff;
-+
-+	odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_95B, &pg_therm, false);
-+
-+	if (pg_therm != 0xff) {
-+		pg_therm = pg_therm & 0x1f;
-+		if ((pg_therm & BIT(0)) == 0)
-+			power_trim_info->thermal = (-1 * (pg_therm >> 1));
-+		else
-+			power_trim_info->thermal = (pg_therm >> 1);
-+
-+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b thermal trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b thermal:%d\n",
-+		       power_trim_info->thermal);
-+}
-+
-+void phydm_set_power_trim_rf_8195b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	RF_DBG(dm, DBG_RF_MP,
-+		   "[kfree] %s:Set kfree to rf 0x33\n", __func__);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_ON) { 
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(19), 1);
-+
-+		if (power_trim_info->flag & KFREE_FLAG_ON_2G) {
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x0);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+				power_trim_info->bb_gain[0][RF_PATH_A]);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x1);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+				power_trim_info->bb_gain[1][RF_PATH_A]);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x2);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+				power_trim_info->bb_gain[2][RF_PATH_A]);
-+		}
-+
-+		if (power_trim_info->flag & KFREE_FLAG_ON_5G) {
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x4);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+				power_trim_info->bb_gain[3][RF_PATH_A]);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x5);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+				power_trim_info->bb_gain[4][RF_PATH_A]);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x6);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+				power_trim_info->bb_gain[5][RF_PATH_A]);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x7);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+				power_trim_info->bb_gain[6][RF_PATH_A]);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x8);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+				power_trim_info->bb_gain[7][RF_PATH_A]);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xe);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+				power_trim_info->bb_gain[7][RF_PATH_A]);
-+		}
-+
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(19), 0);
-+	}
-+
-+}
-+
-+void phydm_get_set_power_trim_offset_8195b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_power = 0xff, i, j;
-+
-+	odm_efuse_one_byte_read(dm, PPG_2GL_TXA_95B, &pg_power, false);
-+
-+	if (pg_power != 0xff) {
-+		odm_efuse_one_byte_read(dm, PPG_2GL_TXA_95B, &pg_power, false);
-+		power_trim_info->bb_gain[0][0] = pg_power & 0xf;
-+
-+		odm_efuse_one_byte_read(dm, PPG_2GM_TXA_95B, &pg_power, false);
-+		power_trim_info->bb_gain[1][0] = pg_power & 0xf;
-+
-+		odm_efuse_one_byte_read(dm, PPG_2GH_TXA_95B, &pg_power, false);
-+		power_trim_info->bb_gain[2][0] = pg_power & 0xf;
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;
-+	}
-+
-+	pg_power = 0xff;
-+
-+	odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_95B, &pg_power, false);
-+
-+	if (pg_power != 0xff) {
-+		odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_95B, &pg_power, false);
-+		power_trim_info->bb_gain[3][0] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_95B, &pg_power, false);
-+		power_trim_info->bb_gain[4][0] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_95B, &pg_power, false);
-+		power_trim_info->bb_gain[5][0] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_95B, &pg_power, false);
-+		power_trim_info->bb_gain[6][0] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_95B, &pg_power, false);
-+		power_trim_info->bb_gain[7][0] = pg_power & 0x1f;
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_5G;
-+	}
-+
-+	phydm_set_power_trim_rf_8195b(dm);
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b power trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_ON) {
-+		for (i = 0; i < KFREE_BAND_NUM; i++) {
-+			for (j = 0; j < 1; j++) {
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 8195b pwr_trim->bb_gain[%d][%d]=0x%X\n",
-+				       i, j, power_trim_info->bb_gain[i][j]);
-+			}
-+		}
-+	}
-+}
-+
-+void phydm_get_set_pa_bias_offset_8195b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_pa_bias = 0xff;
-+
-+	RF_DBG(dm, DBG_RF_MP, "======>%s\n", __func__);
-+
-+	/*2G*/
-+	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_95B, &pg_pa_bias, false);
-+
-+	if (pg_pa_bias != 0xff) {
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_95B,
-+					&pg_pa_bias, false);
-+		pg_pa_bias = pg_pa_bias & 0xf;
-+
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 2G pa_bias=0x%x\n", pg_pa_bias);
-+
-+		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, pg_pa_bias);
-+	} else {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b 2G tx pa bias no pg\n");
-+	}
-+
-+	/*5G*/
-+	pg_pa_bias = 0xff;
-+
-+	odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_95B, &pg_pa_bias, false);
-+
-+	if (pg_pa_bias != 0xff) {
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_95B,
-+					&pg_pa_bias, false);
-+		pg_pa_bias = pg_pa_bias & 0xf;
-+
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 5G pa_bias=0x%x\n", pg_pa_bias);
-+
-+		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x000f0000, pg_pa_bias);
-+
-+		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
-+	} else {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8195b 5G tx pa bias no pg\n");
-+	}
-+}
-+
-+void phydm_get_thermal_trim_offset_8721d(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_therm = 0xff;
-+
-+	odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_8721D, &pg_therm, false);
-+
-+	if (pg_therm != 0xff) {
-+		pg_therm = pg_therm & 0x1f;
-+		if ((pg_therm & BIT(0)) == 0)
-+			power_trim_info->thermal = (-1 * (pg_therm >> 1));
-+		else
-+			power_trim_info->thermal = (pg_therm >> 1);
-+
-+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8721d thermal trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8721d thermal:%d\n",
-+		       power_trim_info->thermal);
-+}
-+
-+void phydm_set_power_trim_rf_8721d(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] %s:Set kfree to rf 0x33\n", __func__);
-+
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(19), 1);
-+
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x0);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+		       power_trim_info->bb_gain[0][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x1);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+		       power_trim_info->bb_gain[1][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x2);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+		       power_trim_info->bb_gain[2][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x3);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+		       power_trim_info->bb_gain[2][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x4);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+		       power_trim_info->bb_gain[3][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x5);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+		       power_trim_info->bb_gain[4][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x6);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+		       power_trim_info->bb_gain[5][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x7);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+		       power_trim_info->bb_gain[6][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x8);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x0000003f,
-+		       power_trim_info->bb_gain[7][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x9);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
-+		       power_trim_info->bb_gain[3][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xa);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
-+		       power_trim_info->bb_gain[4][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xb);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
-+		       power_trim_info->bb_gain[5][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xc);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
-+		       power_trim_info->bb_gain[6][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xd);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
-+		       power_trim_info->bb_gain[7][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0xe);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK,
-+		       power_trim_info->bb_gain[7][RF_PATH_A]);
-+
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(19), 0);
-+}
-+
-+void phydm_get_set_power_trim_offset_8721d(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_power = 0xff, i, j;
-+	u8 pg_power1, pg_power2, pg_power3, pg_power4, pg_power5, pg_power6;
-+
-+	odm_efuse_one_byte_read(dm, PPG_2G_TXA_8721D, &pg_power1, false);
-+	odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_8721D, &pg_power2, false);
-+	odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_8721D, &pg_power3, false);
-+	odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_8721D, &pg_power4, false);
-+	odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_8721D, &pg_power5, false);
-+	odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_8721D, &pg_power6, false);
-+
-+	if (pg_power1 != 0xff || pg_power2 != 0xff || pg_power3 != 0xff ||
-+	    pg_power4 != 0xff || pg_power5 != 0xff || pg_power6 != 0xff) {
-+		odm_efuse_one_byte_read(dm, PPG_2G_TXA_8721D, &pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[0][0] = pg_power & 0xf;
-+		power_trim_info->bb_gain[1][0] = pg_power & 0xf;
-+		power_trim_info->bb_gain[2][0] = pg_power & 0xf;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_8721D,
-+					&pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[3][0] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_8721D,
-+					&pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[4][0] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_8721D,
-+					&pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[5][0] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_8721D,
-+					&pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[6][0] = pg_power & 0x1f;
-+
-+		odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_8721D,
-+					&pg_power, false);
-+		if (pg_power == 0xff)
-+			pg_power = 0;
-+		power_trim_info->bb_gain[7][0] = pg_power & 0x1f;
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | KFREE_FLAG_ON |
-+						KFREE_FLAG_ON_2G |
-+						KFREE_FLAG_ON_5G;
-+
-+		phydm_set_power_trim_rf_8721d(dm);
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8721d power trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_ON) {
-+		for (i = 0; i < KFREE_BAND_NUM; i++) {
-+			for (j = 0; j < 1; j++) {
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 8721d pwr_trim->bb_gain[%d][%d]=0x%X\n",
-+				       i, j, power_trim_info->bb_gain[i][j]);
-+			}
-+		}
-+	}
-+}
-+
-+void phydm_get_set_pa_bias_offset_8721d(void *dm_void)
-+{
-+#if 0
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_pa_bias = 0xff;
-+
-+	RF_DBG(dm, DBG_RF_MP, "======>%s\n", __func__);
-+
-+	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_95B, &pg_pa_bias, false);
-+
-+	if (pg_pa_bias != 0xff) {
-+		/*2G*/
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_95B,
-+					&pg_pa_bias, false);
-+		pg_pa_bias = pg_pa_bias & 0xf;
-+
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 2G pa_bias=0x%x\n", pg_pa_bias);
-+
-+		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, pg_pa_bias);
-+
-+		/*5G*/
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_5GA_95B,
-+					&pg_pa_bias, false);
-+		pg_pa_bias = pg_pa_bias & 0xf;
-+
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 5G pa_bias=0x%x\n", pg_pa_bias);
-+
-+		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x000f0000, pg_pa_bias);
-+
-+		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
-+	} else {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8721d tx pa bias no pg\n");
-+	}
-+#endif
-+}
-+
-+void phydm_get_thermal_trim_offset_8197g(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_therm = 0xff, i;
-+
-+	odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_97G, &pg_therm, false);
-+
-+	if (pg_therm != 0x0) {
-+		for (i = 0; i < 2; i++) {
-+			if (i == 0)
-+				odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_97G, &pg_therm, false);
-+			else if (i == 1)
-+				odm_efuse_one_byte_read(dm, PPG_THERMAL_B_OFFSET_97G, &pg_therm, false);
-+
-+			RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g Efuse thermal S%d:0x%x\n", i, pg_therm);
-+
-+			pg_therm = pg_therm & 0x1f;
-+			if ((pg_therm & BIT(0)) == 0)
-+				power_trim_info->multi_thermal[i] = (-1 * (pg_therm >> 1));
-+			else
-+				power_trim_info->multi_thermal[i] = (pg_therm >> 1);
-+		}
-+
-+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g thermal trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	for (i = 0; i < 2; i++) {
-+		if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
-+			RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g thermal S%d:%d\n",
-+			       i ,power_trim_info->multi_thermal[i]);
-+	}
-+}
-+
-+void phydm_set_power_trim_offset_8197g(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+	u8 e_rf_path;
-+
-+	for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
-+	{
-+		odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1);
-+
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 0);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F,
-+			power_trim_info->bb_gain[0][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 1);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F,
-+			power_trim_info->bb_gain[0][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 2);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, 
-+			power_trim_info->bb_gain[1][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 3);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, 
-+			power_trim_info->bb_gain[1][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 4);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, 
-+			power_trim_info->bb_gain[2][e_rf_path]);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x1c000, 5);
-+		odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x3F, 
-+			power_trim_info->bb_gain[2][e_rf_path]);
-+
-+		odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0);
-+	}
-+
-+}
-+
-+void phydm_get_set_power_trim_offset_8197g(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_power = 0, i, j;
-+
-+	odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_97G, &pg_power, false);
-+
-+	if (pg_power != 0) {
-+		power_trim_info->bb_gain[0][0] = pg_power & 0xf;
-+		power_trim_info->bb_gain[0][1] = (pg_power & 0xf0) >> 4;
-+
-+		odm_efuse_one_byte_read(dm, PPG_2GM_TXAB_97G, &pg_power, false);
-+		power_trim_info->bb_gain[1][0] = pg_power & 0xf;
-+		power_trim_info->bb_gain[1][1] = (pg_power & 0xf0) >> 4;
-+
-+		odm_efuse_one_byte_read(dm, PPG_2GH_TXAB_97G, &pg_power, false);
-+		power_trim_info->bb_gain[2][0] = pg_power & 0xf;
-+		power_trim_info->bb_gain[2][1] = (pg_power & 0xf0) >> 4;
-+
-+		phydm_set_power_trim_offset_8197g(dm);
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g power trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_ON) {
-+		for (i = 0; i < KFREE_BAND_NUM; i++) {
-+			for (j = 0; j < MAX_RF_PATH; j++) {
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 8197g pwr_trim->bb_gain[%d][%d]=0x%X\n",
-+				       i, j, power_trim_info->bb_gain[i][j]);
-+			}
-+		}
-+	}
-+}
-+
-+void phydm_get_tssi_trim_offset_8197g(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 i, j;
-+	u8 pg_power[4] = {0};
-+
-+	odm_efuse_one_byte_read(dm, TSSI_2GL_TXA_97G, &pg_power[0], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GL_TXB_97G, &pg_power[1], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GH_TXA_97G, &pg_power[2], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GH_TXB_97G, &pg_power[3], false);
-+
-+	j = 0;
-+	for (i = 0; i < 4; i++) {
-+		if (pg_power[i] == 0x0)
-+			j++;
-+	}
-+
-+	if (j == 4) {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g tssi trim no PG\n");
-+	} else {
-+		power_trim_info->tssi_trim[0][0] = (s8)pg_power[0];
-+		power_trim_info->tssi_trim[0][1] = (s8)pg_power[1];
-+		power_trim_info->tssi_trim[1][0] = (s8)pg_power[0];
-+		power_trim_info->tssi_trim[1][1] = (s8)pg_power[1];
-+		power_trim_info->tssi_trim[2][0] = (s8)pg_power[2];
-+		power_trim_info->tssi_trim[2][1] = (s8)pg_power[3];
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | TSSI_TRIM_FLAG_ON;
-+
-+		for (i = 0; i < KFREE_BAND_NUM; i++) {
-+			for (j = 0; j < MAX_PATH_NUM_8197G; j++) {
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 8197g tssi_trim[%d][%d]=0x%X\n",
-+				       i, j, power_trim_info->tssi_trim[i][j]);
-+			}
-+		}
-+	}
-+}
-+
-+s8 phydm_get_tssi_trim_de_8197g(void *dm_void, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 channel = *dm->channel, group = 0;
-+
-+	if (channel >= 1 && channel <= 3)
-+		group = 0;
-+	else if (channel >= 4 && channel <= 9)
-+		group = 1;
-+	else if (channel >= 10 && channel <= 14)
-+		group = 2;
-+	else {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] Channel(%d) is not exist in Group\n",
-+			channel);
-+		return 0;
-+	}
-+
-+	return power_trim_info->tssi_trim[group][path];
-+}
-+
-+void phydm_get_set_pa_bias_offset_8197g(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_pa_bias = 0xff, i;
-+	u8 tx_pa_bias[4] = {0};
-+
-+	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GAB_97G, &pg_pa_bias, false);
-+
-+	if (pg_pa_bias != 0x0) {
-+		/*paht ab*/
-+		odm_efuse_one_byte_read(dm, PPG_PABIAS_2GAB_97G,
-+					&pg_pa_bias, false);
-+		tx_pa_bias[0] = pg_pa_bias & 0xf;
-+		tx_pa_bias[1] = ((pg_pa_bias & 0xf0) >> 4);
-+
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] 8197g PathA_pa_bias:0x%x PathB_pa_bias:0x%x\n",
-+		       tx_pa_bias[0], tx_pa_bias[1]);
-+
-+		for (i = RF_PATH_A; i < 2; i++)
-+			odm_set_rf_reg(dm, i, 0x60, 0x0000f000, tx_pa_bias[i]);
-+
-+		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
-+	} else {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g tx pa bias no pg\n");
-+	}
-+}
-+
-+void phydm_get_set_lna_offset_8197g(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_lna[2] = {0}, i, pg_lna_tmp = 0;
-+	u32 lna_trim_addr[2] = {0x1884, 0x4184};
-+
-+	odm_efuse_one_byte_read(dm, PPG_LNA_2GA_97G, &pg_lna_tmp, false);
-+
-+	if (pg_lna_tmp != 0) {
-+		odm_efuse_one_byte_read(dm, PPG_LNA_2GA_97G,
-+					&pg_lna[RF_PATH_A], false);
-+		power_trim_info->lna_trim[RF_PATH_A] = (s8)pg_lna[RF_PATH_A];
-+
-+		odm_efuse_one_byte_read(dm, PPG_LNA_2GB_97G,
-+					&pg_lna[RF_PATH_B], false);
-+		power_trim_info->lna_trim[RF_PATH_B] = (s8)pg_lna[RF_PATH_B];
-+
-+		for (i = RF_PATH_A; i < 2; i++) {
-+			if (odm_get_bb_reg(dm, lna_trim_addr[i], 0x00c00000) == 0x2) {
-+				odm_set_rf_reg(dm, i, 0x88, 0x00000f00, (pg_lna[i] & 0xf));
-+				RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g lna trim CG 0x%x path=%d\n", (pg_lna[i] & 0xf), i);
-+			} else if (odm_get_bb_reg(dm, lna_trim_addr[i], 0x00c00000) == 0x3) {
-+				odm_set_rf_reg(dm, i, 0x88, 0x00000f00, ((pg_lna[i] & 0xf0) >> 4));
-+				RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g lna trim CS 0x%x path=%d\n", ((pg_lna[i] & 0xf0) >> 4), i);
-+			}
-+		}
-+
-+		power_trim_info->lna_flag |= LNA_FLAG_ON;
-+	} else {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g lna trim no pg\n");
-+	}
-+}
-+
-+void phydm_set_lna_trim_offset_8197g(void *dm_void, u8 path, u8 cg_cs, u8 enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *trim = &dm->power_trim_data;
-+
-+	u8 i;
-+
-+	if (enable == 0) {
-+		for (i = RF_PATH_A; i < 2; i++) {
-+			odm_set_rf_reg(dm, i, 0x88, 0x00000f00, 0x0);
-+			RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g diversity lna trim disable\n");
-+		}
-+		return;
-+	}
-+
-+	/*cg*/
-+	if (cg_cs == 0) {
-+		odm_set_rf_reg(dm, path, 0x88, 0x00000f00, (trim->lna_trim[path] & 0xf));
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g diversity lna trim CG 0x%x path=%d\n",
-+			(trim->lna_trim[path] & 0xf), path);
-+	} else if (cg_cs == 1) {	/*cs*/
-+		odm_set_rf_reg(dm, path, 0x88, 0x00000f00, ((trim->lna_trim[path] & 0xf0) >> 4));
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8197g diversity lna trim CS 0x%x path=%d\n",
-+			((trim->lna_trim[path] & 0xf0) >> 4), path);
-+	}
-+}
-+
-+
-+void phydm_get_thermal_trim_offset_8710c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_therm = 0;
-+
-+	odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_10C, &pg_therm, false);
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c Efuse thermal:0x%x\n", pg_therm);
-+
-+	if (pg_therm != 0xff) {
-+		pg_therm = pg_therm & 0x1f;
-+		if ((pg_therm & BIT(0)) == 0)
-+			power_trim_info->thermal = (-1 * (pg_therm >> 1));
-+		else
-+			power_trim_info->thermal = (pg_therm >> 1);
-+
-+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c thermal trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c thermal:%d\n",
-+		       power_trim_info->thermal);
-+}
-+
-+void phydm_set_power_trim_offset_8710c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(18), 1);
-+
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x3f,
-+		power_trim_info->bb_gain[0][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 1);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x3f,
-+		power_trim_info->bb_gain[1][RF_PATH_A]);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 2);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0x3f, 
-+		power_trim_info->bb_gain[2][RF_PATH_A]);
-+
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(18), 0);
-+}
-+
-+void phydm_get_set_power_trim_offset_8710c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_power = 0, i, j;
-+
-+	odm_efuse_one_byte_read(dm, PPG_2GL_TX_10C, &pg_power, false);
-+
-+	if (pg_power != 0xff) {
-+		power_trim_info->bb_gain[0][RF_PATH_A] = pg_power & 0xf;
-+
-+		odm_efuse_one_byte_read(dm, PPG_2GM_TX_10C, &pg_power, false);
-+		power_trim_info->bb_gain[1][RF_PATH_A] = pg_power & 0xf;
-+
-+		odm_efuse_one_byte_read(dm, PPG_2GH_TX_10C, &pg_power, false);
-+		power_trim_info->bb_gain[2][RF_PATH_A] = pg_power & 0xf;
-+
-+		phydm_set_power_trim_offset_8710c(dm);
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c power trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_ON) {
-+		for (i = 0; i < KFREE_BAND_NUM; i++) {
-+			for (j = 0; j < MAX_RF_PATH; j++) {
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 8710c pwr_trim->bb_gain[%d][%d]=0x%X\n",
-+				       i, j, power_trim_info->bb_gain[i][j]);
-+			}
-+		}
-+	}
-+}
-+
-+void phydm_get_set_pa_bias_offset_8710c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_pa_bias = 0xff;
-+	u8 tx_pa_bias = 0;
-+
-+	odm_efuse_one_byte_read(dm, PPG_PABIAS_10C, &pg_pa_bias, false);
-+
-+	if (pg_pa_bias != 0xff) {
-+		tx_pa_bias = pg_pa_bias & 0xf;
-+
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] 8710c PathA_pa_bias:0x%x\n", tx_pa_bias);
-+
-+		odm_set_rf_reg(dm, RF_PATH_A, 0x60, 0x0000f000, tx_pa_bias);
-+
-+		power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
-+	} else {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8710c tx pa bias no pg\n");
-+	}
-+}
-+
-+void phydm_set_power_trim_offset_8814b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+	u8 e_rf_path;
-+
-+	for (e_rf_path = RF_PATH_A; e_rf_path < MAX_PATH_NUM_8814B; e_rf_path++)
-+	{
-+		if (power_trim_info->flag & KFREE_FLAG_ON) {
-+			odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 1);
-+
-+			if (power_trim_info->flag & KFREE_FLAG_ON_2G) {
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[0][e_rf_path]);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x1);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[0][e_rf_path]);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x2);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[0][e_rf_path]);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x3);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[0][e_rf_path]);
-+			}
-+
-+			if (power_trim_info->flag & KFREE_FLAG_ON_5G) {
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x4);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[3][e_rf_path]);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x5);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[4][e_rf_path]);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x6);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[5][e_rf_path]);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x7);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[6][e_rf_path]);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x8);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[7][e_rf_path]);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x9);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[3][e_rf_path]);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xa);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[4][e_rf_path]);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xb);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[5][e_rf_path]);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xc);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[6][e_rf_path]);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xd);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[7][e_rf_path]);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0xe);
-+				odm_set_rf_reg(dm, e_rf_path, RF_0x30, RFREGOFFSETMASK,
-+					power_trim_info->bb_gain[7][e_rf_path]);
-+			}
-+
-+			odm_set_rf_reg(dm, e_rf_path, RF_0xee, BIT(19), 0);
-+		}
-+	}
-+}
-+
-+void phydm_get_set_power_trim_offset_8814b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 i, j;
-+	u8 pg_power1, pg_power2;
-+	u8 pg_power_2g[2] = {0}, pg_power_5g[20] = {0};
-+
-+	odm_efuse_one_byte_read(dm, PPG_2GL_TXAB_14B, &pg_power_2g[0], false);
-+	odm_efuse_one_byte_read(dm, PPG_2GL_TXCD_14B, &pg_power_2g[1], false);
-+
-+	j = 0;
-+	for (i = 0; i < 2; i++) {
-+		if (pg_power_2g[i] == 0xff)
-+			j++;
-+	}
-+
-+	if (j == 2) {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 2G power trim no PG\n");
-+	} else {
-+		power_trim_info->bb_gain[0][RF_PATH_A] = pg_power_2g[0] & 0xf;
-+		power_trim_info->bb_gain[0][RF_PATH_B] = (pg_power_2g[0] & 0xf0) >> 4;
-+
-+		power_trim_info->bb_gain[0][RF_PATH_C] = pg_power_2g[1] & 0xf;
-+		power_trim_info->bb_gain[0][RF_PATH_D] = (pg_power_2g[1] & 0xf0) >> 4;
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G;
-+	}
-+
-+	odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_14B, &pg_power_5g[0], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_14B, &pg_power_5g[1], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GL1_TXC_14B, &pg_power_5g[2], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GL1_TXD_14B, &pg_power_5g[3], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_14B, &pg_power_5g[4], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_14B, &pg_power_5g[5], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GL2_TXC_14B, &pg_power_5g[6], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GL2_TXD_14B, &pg_power_5g[7], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_14B, &pg_power_5g[8], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GM1_TXB_14B, &pg_power_5g[9], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GM1_TXC_14B, &pg_power_5g[10], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GM1_TXD_14B, &pg_power_5g[11], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_14B, &pg_power_5g[12], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GM2_TXB_14B, &pg_power_5g[13], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GM2_TXC_14B, &pg_power_5g[14], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GM2_TXD_14B, &pg_power_5g[15], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_14B, &pg_power_5g[16], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GH1_TXB_14B, &pg_power_5g[17], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GH1_TXC_14B, &pg_power_5g[18], false);
-+	odm_efuse_one_byte_read(dm, PPG_5GH1_TXD_14B, &pg_power_5g[19], false);
-+
-+	j = 0;
-+	for (i = 0; i < 20; i++) {
-+		if (pg_power_5g[i] == 0xff)
-+			j++;
-+	}
-+
-+	if (j == 20) {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 5G power trim no PG\n");
-+	} else {
-+		power_trim_info->bb_gain[3][RF_PATH_A] = pg_power_5g[0] & 0x1f;
-+		power_trim_info->bb_gain[3][RF_PATH_B] = pg_power_5g[1] & 0x1f;
-+		power_trim_info->bb_gain[3][RF_PATH_C] = pg_power_5g[2] & 0x1f;
-+		power_trim_info->bb_gain[3][RF_PATH_D] = pg_power_5g[3] & 0x1f;
-+
-+		power_trim_info->bb_gain[4][RF_PATH_A] = pg_power_5g[4] & 0x1f;
-+		power_trim_info->bb_gain[4][RF_PATH_B] = pg_power_5g[5] & 0x1f;
-+		power_trim_info->bb_gain[4][RF_PATH_C] = pg_power_5g[6] & 0x1f;
-+		power_trim_info->bb_gain[4][RF_PATH_D] = pg_power_5g[7] & 0x1f;
-+
-+		power_trim_info->bb_gain[5][RF_PATH_A] = pg_power_5g[8] & 0x1f;
-+		power_trim_info->bb_gain[5][RF_PATH_B] = pg_power_5g[9] & 0x1f;
-+		power_trim_info->bb_gain[5][RF_PATH_C] = pg_power_5g[10] & 0x1f;
-+		power_trim_info->bb_gain[5][RF_PATH_D] = pg_power_5g[11] & 0x1f;
-+
-+		power_trim_info->bb_gain[6][RF_PATH_A] = pg_power_5g[12] & 0x1f;
-+		power_trim_info->bb_gain[6][RF_PATH_B] = pg_power_5g[13] & 0x1f;
-+		power_trim_info->bb_gain[6][RF_PATH_C] = pg_power_5g[14] & 0x1f;
-+		power_trim_info->bb_gain[6][RF_PATH_D] = pg_power_5g[15] & 0x1f;
-+
-+		power_trim_info->bb_gain[7][RF_PATH_A] = pg_power_5g[16] & 0x1f;
-+		power_trim_info->bb_gain[7][RF_PATH_B] = pg_power_5g[17] & 0x1f;
-+		power_trim_info->bb_gain[7][RF_PATH_C] = pg_power_5g[18] & 0x1f;
-+		power_trim_info->bb_gain[7][RF_PATH_D] = pg_power_5g[19] & 0x1f;
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_5G;
-+
-+	}
-+
-+	phydm_set_power_trim_offset_8814b(dm);
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b power trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	if (power_trim_info->flag & KFREE_FLAG_ON) {
-+		for (i = 0; i < KFREE_BAND_NUM; i++) {
-+			for (j = 0; j < MAX_PATH_NUM_8814B; j++) {
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 8814b pwr_trim->bb_gain[%d][%d]=0x%X\n",
-+				       i, j, power_trim_info->bb_gain[i][j]);
-+			}
-+		}
-+	}
-+}
-+
-+void phydm_get_tssi_trim_offset_8814b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 i, j;
-+	u8 tssi_trim_2g[8] = {0}, tssi_trim_5g[24] = {0};
-+
-+	odm_efuse_one_byte_read(dm, TSSI_2GM_TXA_14B, &tssi_trim_2g[0], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GM_TXB_14B, &tssi_trim_2g[1], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GM_TXC_14B, &tssi_trim_2g[2], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GM_TXD_14B, &tssi_trim_2g[3], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GH_TXA_14B, &tssi_trim_2g[4], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GH_TXB_14B, &tssi_trim_2g[5], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GH_TXC_14B, &tssi_trim_2g[6], false);
-+	odm_efuse_one_byte_read(dm, TSSI_2GH_TXD_14B, &tssi_trim_2g[7], false);
-+
-+	j = 0;
-+	for (i = 0; i < 8; i++) {
-+		if (tssi_trim_2g[i] == 0xff)
-+			j++;
-+	}
-+
-+	if (j == 8) {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 2g tssi trim no PG\n");
-+	} else {
-+		power_trim_info->tssi_trim[0][RF_PATH_A] = (s8)tssi_trim_2g[0];
-+		power_trim_info->tssi_trim[0][RF_PATH_B] = (s8)tssi_trim_2g[1];
-+		power_trim_info->tssi_trim[0][RF_PATH_C] = (s8)tssi_trim_2g[2];
-+		power_trim_info->tssi_trim[0][RF_PATH_D] = (s8)tssi_trim_2g[3];
-+		power_trim_info->tssi_trim[1][RF_PATH_A] = (s8)tssi_trim_2g[0];
-+		power_trim_info->tssi_trim[1][RF_PATH_B] = (s8)tssi_trim_2g[1];
-+		power_trim_info->tssi_trim[1][RF_PATH_C] = (s8)tssi_trim_2g[2];
-+		power_trim_info->tssi_trim[1][RF_PATH_D] = (s8)tssi_trim_2g[3];
-+		power_trim_info->tssi_trim[2][RF_PATH_A] = (s8)tssi_trim_2g[4];
-+		power_trim_info->tssi_trim[2][RF_PATH_B] = (s8)tssi_trim_2g[5];
-+		power_trim_info->tssi_trim[2][RF_PATH_C] = (s8)tssi_trim_2g[6];
-+		power_trim_info->tssi_trim[2][RF_PATH_D] = (s8)tssi_trim_2g[7];
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | TSSI_TRIM_FLAG_ON | KFREE_FLAG_ON_2G;
-+
-+		for (i = 0; i < KFREE_BAND_NUM; i++) {
-+			for (j = 0; j < MAX_PATH_NUM_8814B; j++) {
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 8814b 2g tssi_trim[%d][%d]=0x%X\n",
-+				       i, j, power_trim_info->tssi_trim[i][j]);
-+			}
-+		}
-+	}
-+
-+	odm_efuse_one_byte_read(dm, TSSI_5GL1_TXA_14B, &tssi_trim_5g[0], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GL1_TXB_14B, &tssi_trim_5g[1], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GL1_TXC_14B, &tssi_trim_5g[2], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GL1_TXD_14B, &tssi_trim_5g[3], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GL2_TXA_14B, &tssi_trim_5g[4], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GL2_TXB_14B, &tssi_trim_5g[5], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GL2_TXC_14B, &tssi_trim_5g[6], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GL2_TXD_14B, &tssi_trim_5g[7], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM1_TXA_14B, &tssi_trim_5g[8], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM1_TXB_14B, &tssi_trim_5g[9], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM1_TXC_14B, &tssi_trim_5g[10], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM1_TXD_14B, &tssi_trim_5g[11], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM2_TXA_14B, &tssi_trim_5g[12], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM2_TXB_14B, &tssi_trim_5g[13], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM2_TXC_14B, &tssi_trim_5g[14], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GM2_TXD_14B, &tssi_trim_5g[15], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH1_TXA_14B, &tssi_trim_5g[16], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH1_TXB_14B, &tssi_trim_5g[17], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH1_TXC_14B, &tssi_trim_5g[18], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH1_TXD_14B, &tssi_trim_5g[19], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH2_TXA_14B, &tssi_trim_5g[20], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH2_TXB_14B, &tssi_trim_5g[21], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH2_TXC_14B, &tssi_trim_5g[22], false);
-+	odm_efuse_one_byte_read(dm, TSSI_5GH2_TXD_14B, &tssi_trim_5g[23], false);
-+
-+	j = 0;
-+	for (i = 0; i < 24; i++) {
-+		if (tssi_trim_5g[i] == 0xff)
-+			j++;
-+	}
-+	
-+	if (j == 24) {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 5g tssi trim no PG\n");
-+	} else {
-+		power_trim_info->tssi_trim[3][RF_PATH_A] = (s8)tssi_trim_5g[0];
-+		power_trim_info->tssi_trim[3][RF_PATH_B] = (s8)tssi_trim_5g[1];
-+		power_trim_info->tssi_trim[3][RF_PATH_C] = (s8)tssi_trim_5g[2];
-+		power_trim_info->tssi_trim[3][RF_PATH_D] = (s8)tssi_trim_5g[3];
-+		power_trim_info->tssi_trim[4][RF_PATH_A] = (s8)tssi_trim_5g[4];
-+		power_trim_info->tssi_trim[4][RF_PATH_B] = (s8)tssi_trim_5g[5];
-+		power_trim_info->tssi_trim[4][RF_PATH_C] = (s8)tssi_trim_5g[6];
-+		power_trim_info->tssi_trim[4][RF_PATH_D] = (s8)tssi_trim_5g[7];
-+		power_trim_info->tssi_trim[5][RF_PATH_A] = (s8)tssi_trim_5g[8];
-+		power_trim_info->tssi_trim[5][RF_PATH_B] = (s8)tssi_trim_5g[9];
-+		power_trim_info->tssi_trim[5][RF_PATH_C] = (s8)tssi_trim_5g[10];
-+		power_trim_info->tssi_trim[5][RF_PATH_D] = (s8)tssi_trim_5g[11];
-+		power_trim_info->tssi_trim[6][RF_PATH_A] = (s8)tssi_trim_5g[12];
-+		power_trim_info->tssi_trim[6][RF_PATH_B] = (s8)tssi_trim_5g[13];
-+		power_trim_info->tssi_trim[6][RF_PATH_C] = (s8)tssi_trim_5g[14];
-+		power_trim_info->tssi_trim[6][RF_PATH_D] = (s8)tssi_trim_5g[15];
-+		power_trim_info->tssi_trim[7][RF_PATH_A] = (s8)tssi_trim_5g[16];
-+		power_trim_info->tssi_trim[7][RF_PATH_B] = (s8)tssi_trim_5g[17];
-+		power_trim_info->tssi_trim[7][RF_PATH_C] = (s8)tssi_trim_5g[18];
-+		power_trim_info->tssi_trim[7][RF_PATH_D] = (s8)tssi_trim_5g[19];
-+		power_trim_info->tssi_trim[8][RF_PATH_A] = (s8)tssi_trim_5g[20];
-+		power_trim_info->tssi_trim[8][RF_PATH_B] = (s8)tssi_trim_5g[21];
-+		power_trim_info->tssi_trim[8][RF_PATH_C] = (s8)tssi_trim_5g[22];
-+		power_trim_info->tssi_trim[8][RF_PATH_D] = (s8)tssi_trim_5g[23];
-+
-+		power_trim_info->flag =
-+			power_trim_info->flag | TSSI_TRIM_FLAG_ON | KFREE_FLAG_ON_5G;
-+
-+		for (i = 0; i < KFREE_BAND_NUM; i++) {
-+			for (j = 0; j < MAX_PATH_NUM_8814B; j++) {
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 8814b 5g tssi_trim[%d][%d]=0x%X\n",
-+				       i, j, power_trim_info->tssi_trim[i][j]);
-+			}
-+		}
-+	}
-+}
-+
-+s8 phydm_get_tssi_trim_de_8814b(void *dm_void, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 channel = *dm->channel, group = 0;
-+
-+	if (channel >= 1 && channel <= 3)
-+		group = 0;
-+	else if (channel >= 4 && channel <= 9)
-+		group = 1;
-+	else if (channel >= 10 && channel <= 14)
-+		group = 2;
-+	else if (channel >= 36 && channel <= 50)
-+		group = 3;
-+	else if (channel >= 52 && channel <= 64)
-+		group = 4;
-+	else if (channel >= 100 && channel <= 118)
-+		group = 5;
-+	else if (channel >= 120 && channel <= 144)
-+		group = 6;
-+	else if (channel >= 149 && channel <= 165)
-+		group = 7;
-+	else if (channel >= 167 && channel <= 177)
-+		group = 8;
-+	else {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] Channel(%d) is not exist in Group\n",
-+			channel);
-+		return 0;
-+	}
-+
-+	return power_trim_info->tssi_trim[group][path];
-+}
-+
-+void phydm_set_pabias_bandedge_2g_rf_8814b(void *dm_void)
-+{
-+#if 0
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u32 rf_reg_51 = 0, rf_reg_52 = 0, rf_reg_53 = 0, rf_reg_3f = 0;
-+	u8 i, j;
-+	s32 pa_bias_tmp, bandedge_tmp, reg_tmp;
-+
-+#if 0
-+	/*2.4G bias*/
-+	/*rf3f == rf53*/
-+#endif
-+	for (i = 0; i < MAX_PATH_NUM_8814B; i++) {
-+		rf_reg_51 = odm_get_rf_reg(dm, i, RF_0x51, RFREGOFFSETMASK);
-+		rf_reg_52 = odm_get_rf_reg(dm, i, RF_0x52, RFREGOFFSETMASK);
-+		rf_reg_53 = odm_get_rf_reg(dm, i, RF_0x53, RFREGOFFSETMASK);
-+
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] 8814b 2g rf(0x51)=0x%X rf(0x52)=0x%X rf(0x53)=0x%X path=%d\n",
-+		       rf_reg_51, rf_reg_52, rf_reg_53, i);
-+
-+		/*2.4G bias*/
-+		rf_reg_3f = rf_reg_53;
-+		pa_bias_tmp = rf_reg_3f & 0xf;
-+
-+		reg_tmp = pa_bias_tmp + power_trim_info->pa_bias_trim[0][i];
-+
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] 8814b 2g pa bias reg_tmp(%d) = pa_bias_tmp(%d) + power_trim_info->pa_bias_trim[0][%d](%d)\n",
-+		       reg_tmp, pa_bias_tmp, i, power_trim_info->pa_bias_trim[0][i]);
-+
-+#if 0
-+		if (reg_tmp < 0) {
-+			reg_tmp = 0;
-+			RF_DBG(dm, DBG_RF_MP,
-+			       "[kfree] 2g pa bias reg_tmp < 0. Set 0 path=%d\n", i);
-+		} else if (reg_tmp > 7) {
-+			reg_tmp = 7;
-+			RF_DBG(dm, DBG_RF_MP,
-+			       "[kfree] 2g pa bias reg_tmp > 7. Set 7 path=%d\n", i);
-+		}
-+#endif
-+
-+		rf_reg_3f = ((rf_reg_3f & 0xffff0) | reg_tmp);
-+		rf_reg_3f = ((rf_reg_3f & 0x0ffff) | 0x10000);
-+
-+		odm_set_rf_reg(dm, i, RF_0xef, BIT(10), 0x1);
-+		for (j = 0; j <= 0xf; j++) {
-+			odm_set_rf_reg(dm, i, RF_0x30, RFREGOFFSETMASK, (j << 16));
-+			odm_set_rf_reg(dm, i, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
-+			RF_DBG(dm, DBG_RF_MP,
-+			       "[kfree] 8814b 2G pa bias write RF_0x30=0x%05x  RF_0x3f=0x%x path=%d\n",
-+			       (j << 16), rf_reg_3f, i);
-+		}
-+		odm_set_rf_reg(dm, i, RF_0xef, BIT(10), 0x0);
-+
-+#if 0
-+		/*2.4G bandedge*/
-+		/*rf3f =>*/
-+		/*rf51[3:1] = rf3f[17:15]*/
-+		/*rf52[2:0] = rf3f[14:12]*/
-+		/*rf52[18] = rf3f[11]*/
-+		/*rf51[6:4] = rf3f[10:8]*/
-+		/*rf51[11:8] = rf3f[7:4]*/
-+		/*rf51[16:13] = rf3f[3:0]*/
-+#endif
-+		/*2.4G bandedge*/
-+		rf_reg_3f = (((rf_reg_51 & 0xe) >> 1) << 15) |
-+			    ((rf_reg_52 & 0x7) << 12) |
-+			    (((rf_reg_52 & 0x40000) >> 18) << 11) |
-+			    (((rf_reg_51 & 0x70) >> 4) << 8) |
-+			    (((rf_reg_51 & 0xf00) >> 8) << 4) |
-+			    ((rf_reg_51 & 0x1e000) >> 13);
-+
-+		bandedge_tmp = rf_reg_3f & 0xf;
-+
-+		reg_tmp = bandedge_tmp + power_trim_info->pa_bias_trim[0][i];
-+
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] 8814b 2g bandedge reg_tmp(%d) = bandedge_tmp(%d) + power_trim_info->pa_bias_trim[0][%d](%d)\n",
-+		       reg_tmp, bandedge_tmp, i, power_trim_info->pa_bias_trim[0][i]);
-+
-+#if 0
-+		if (reg_tmp < 0) {
-+			reg_tmp = 0;
-+			RF_DBG(dm, DBG_RF_MP,
-+			       "[kfree] 2g bandedge reg_tmp < 0. Set 0 path=%d\n", i);
-+		} else if (reg_tmp > 7) {
-+			reg_tmp = 7;
-+			RF_DBG(dm, DBG_RF_MP,
-+			       "[kfree] 2g bandedge reg_tmp > 7. Set 7 path=%d\n", i);
-+		}
-+#endif
-+
-+		rf_reg_3f = ((rf_reg_3f & 0xffff0) | reg_tmp);
-+
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] 8814b 2G bandedge RF_0x30=0x%05X  RF_0x3f=0x%x path=%d\n",
-+		       0x00001, rf_reg_3f, i);
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] 8814b 2G bandedge RF_0x30=0x%05X  RF_0x3f=0x%x path=%d\n",
-+		       0x0000b, rf_reg_3f, i);
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] 8814b 2G bandedge RF_0x30=0x%05X  RF_0x3f=0x%x path=%d\n",
-+		       0x00023, rf_reg_3f, i);
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] 8814b 2G bandedge RF_0x30=0x%05X  RF_0x3f=0x%x path=%d\n",
-+		       0x00029, rf_reg_3f, i);
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] 8814b 2G bandedge RF_0x30=0x%05X  RF_0x3f=0x%x path=%d\n",
-+		       0x0002a, rf_reg_3f, i);
-+
-+		odm_set_rf_reg(dm, i, RF_0xef, BIT(8), 0x1);
-+		odm_set_rf_reg(dm, i, RF_0x33, RFREGOFFSETMASK, 0x00001);
-+		odm_set_rf_reg(dm, i, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
-+		odm_set_rf_reg(dm, i, RF_0x33, RFREGOFFSETMASK, 0x0000b);
-+		odm_set_rf_reg(dm, i, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
-+		odm_set_rf_reg(dm, i, RF_0x33, RFREGOFFSETMASK, 0x00023);
-+		odm_set_rf_reg(dm, i, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
-+		odm_set_rf_reg(dm, i, RF_0x33, RFREGOFFSETMASK, 0x00029);
-+		odm_set_rf_reg(dm, i, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
-+		odm_set_rf_reg(dm, i, RF_0x33, RFREGOFFSETMASK, 0x0002a);
-+		odm_set_rf_reg(dm, i, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f);
-+		odm_set_rf_reg(dm, i, RF_0xef, BIT(8), 0x0);
-+
-+	}
-+#endif
-+}
-+
-+void phydm_set_pabias_bandedge_5g_rf_8814b(void *dm_void)
-+{
-+#if 0
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u32 rf_reg_18[MAX_PATH_NUM_8814B] = {0},
-+		rf_reg_61[15][MAX_PATH_NUM_8814B] = {0},
-+		rf_reg_62[3][MAX_PATH_NUM_8814B] = {0};
-+	u8 i, j;
-+	u32 bandedge[15][MAX_PATH_NUM_8814B] = {0},
-+		pa_bias[3][MAX_PATH_NUM_8814B] = {0};
-+		
-+	s32 pa_bias_tmp, reg_tmp;
-+
-+
-+	for (i = 0; i < MAX_PATH_NUM_8814B; i++) {
-+		rf_reg_18[i] = odm_get_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK);
-+
-+		for (j = 0; j < 3; j++) {
-+			if (j == 0)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x10d24);
-+			else if (j == 1)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x30d64);
-+			else if (j == 2)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x50da9);
-+
-+			rf_reg_62[j][i] = odm_get_rf_reg(dm, i, 0x62, RFREGOFFSETMASK);
-+
-+#if 0
-+			/*5G bias*/
-+			/*rf62[19:16] == rf30[11:8]*/
-+			/*rf62[15:12] == rf30[7:4]*/
-+			/*rf62[11:8] == rf3030[3:0]*/
-+#endif
-+			pa_bias[j][i] = (((rf_reg_62[j][i] & 0xf0000) >> 16) << 8) |
-+					(((rf_reg_62[j][i] & 0xf000) >> 12) << 4) |
-+					((rf_reg_62[j][i] & 0xf00) >> 8);
-+		}
-+
-+		for (j = 0; j < 15; j++) {
-+			if (j == 0)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x10d24);/*ch36*/
-+			else if (j == 1)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x11926);/*ch38*/
-+			else if (j == 2)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x1252a);/*ch42*/
-+			else if (j == 3)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x1253a);/*ch58*/
-+			else if (j == 4)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x1193e);/*ch62*/
-+			else if (j == 5)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x10d40);/*ch64*/
-+			else if (j == 6)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x30d64);/*ch100*/
-+			else if (j == 7)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x31966);/*ch102*/
-+			else if (j == 8)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x3256a);/*ch106*/
-+			else if (j == 9)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x3257a);/*ch122*/
-+			else if (j == 10)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x31986);/*ch134*/
-+			else if (j == 11)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x30d8c);/*ch140*/
-+			else if (j == 12)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x50d95);/*ch149*/
-+			else if (j == 13)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x51997);/*ch151*/
-+			else if (j == 14)
-+				odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, 0x5259b);/*ch155*/
-+				
-+
-+			rf_reg_61[j][i] = odm_get_rf_reg(dm, i, RF_0x61, RFREGOFFSETMASK);
-+#if 0
-+			/*5G bandedge*/
-+			/*rf61[11:8] == rf30[11:8]*/
-+			/*rf61[7:4] == rf30[7:4]*/
-+			/*rf61[3:0] == rf3030[3:0]*/
-+#endif
-+			bandedge[j][i] = rf_reg_61[j][i] & 0xfff;
-+		}
-+
-+		odm_set_rf_reg(dm, i, RF_0x18, RFREGOFFSETMASK, rf_reg_18[i]);
-+	}
-+
-+	for (i = 0; i < MAX_PATH_NUM_8814B; i++) {
-+		for (j = 0; j < 3; j++) {
-+			RF_DBG(dm, DBG_RF_MP,
-+			       "[kfree] pa_bias[%d][%d]=0x%x\n", j, i, pa_bias[j][i]);
-+		}
-+	}
-+
-+	for (i = 0; i < MAX_PATH_NUM_8814B; i++) {
-+		for (j = 0; j < 15; j++) {
-+			RF_DBG(dm, DBG_RF_MP,
-+			       "[kfree] bandedge[%d][%d]=0x%x\n", j, i, bandedge[j][i]);
-+		}
-+	}
-+
-+	/*5G bias*/
-+	for (i = 0; i < MAX_PATH_NUM_8814B; i++) {
-+		odm_set_rf_reg(dm, i, RF_0xee, BIT(8), 0x1);
-+		for (j = 0; j <= 0xb; j++) {
-+			
-+			if (j >= 0 && j <= 3)
-+				pa_bias_tmp = pa_bias[0][i] & 0xf;
-+			else if (j >= 4 && j <= 0x7)
-+				pa_bias_tmp = pa_bias[1][i] & 0xf;
-+			else if (j >= 0x8 && j <= 0xb)
-+				pa_bias_tmp = pa_bias[2][i] & 0xf;
-+
-+			reg_tmp = pa_bias_tmp + power_trim_info->pa_bias_trim[1][i];
-+
-+			RF_DBG(dm, DBG_RF_MP,
-+			       "[kfree] 8814b 5g pa bias reg_tmp(%d) = pa_bias_tmp(%d) + power_trim_info->pa_bias_trim[1][%d](%d)\n",
-+			       reg_tmp, pa_bias_tmp, i, power_trim_info->pa_bias_trim[1][i]);
-+#if 0
-+			if (reg_tmp < 0) {
-+				reg_tmp = 0;
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 5g pa bias reg_tmp < 0. Set 0 path=%d\n", i);
-+			} else if (reg_tmp > 7) {
-+				reg_tmp = 7;
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 5g pa bias reg_tmp > 7. Set 7 path=%d\n", i);
-+			}
-+#endif
-+			if (j >= 0 && j <= 3)
-+				reg_tmp = ((pa_bias[0][i] & 0xffff0) | reg_tmp | (j << 12));
-+			else if (j >= 4 && j <= 0x7)
-+				reg_tmp = ((pa_bias[1][i] & 0xffff0) | reg_tmp | (j << 12));
-+			else if (j >= 0x8 && j <= 0xb)
-+				reg_tmp = ((pa_bias[2][i] & 0xffff0) | reg_tmp | (j << 12));
-+
-+			RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 8814b write RF_0x30=0x%05x path=%d\n",
-+				       reg_tmp, i);
-+
-+			odm_set_rf_reg(dm, i, RF_0x30, RFREGOFFSETMASK, reg_tmp);
-+		}
-+		odm_set_rf_reg(dm, i, RF_0xee, BIT(8), 0x0);
-+	}
-+
-+	/*5G bandedge*/
-+	for (i = 0; i < MAX_PATH_NUM_8814B; i++) {
-+		odm_set_rf_reg(dm, i, RF_0xee, BIT(9), 0x1);
-+		for (j = 0; j <= 0xe; j++) {
-+			reg_tmp = bandedge[j][i] + power_trim_info->pa_bias_trim[1][i];
-+
-+			RF_DBG(dm, DBG_RF_MP,
-+			       "[kfree] 8814b 5g bandedge reg_tmp(%d)(0x%X) = bandedge_org(%d) + power_trim_info->pa_bias_trim[1][%d](%d)\n",
-+			       reg_tmp, reg_tmp, bandedge[j][i], i, power_trim_info->pa_bias_trim[1][i]);
-+#if 0
-+			if (reg_tmp < 0) {
-+				reg_tmp = 0;
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 5g bandedge reg_tmp < 0. Set 0 path=%d\n", i);
-+			} else if (reg_tmp > 7) {
-+				reg_tmp = 7;
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 5g bandedge reg_tmp > 7. Set 7 path=%d\n", i);
-+			}
-+#endif
-+
-+			reg_tmp = ((bandedge[j][i] & 0xffff0) | reg_tmp | (j << 12));
-+
-+			RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] 8814b write RF_0x30=0x%05x path=%d\n",
-+				       reg_tmp, i);
-+
-+			odm_set_rf_reg(dm, i, RF_0x30, RFREGOFFSETMASK, reg_tmp);
-+		}
-+		odm_set_rf_reg(dm, i, RF_0xee, BIT(9), 0x0);
-+	}
-+
-+#endif
-+}
-+
-+
-+void phydm_get_pa_bias_offset_8814b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 i, j, k;
-+	u8 tssi_pa_bias_2g[2] = {0}, tssi_pa_bias_5g[2] = {0};
-+
-+	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GAC_14B, &tssi_pa_bias_2g[0], false);
-+	odm_efuse_one_byte_read(dm, PPG_PABIAS_2GBD_14B, &tssi_pa_bias_2g[1], false);
-+
-+	j = 0;
-+	for (i = 0; i < 2; i++) {
-+		if (tssi_pa_bias_2g[i] == 0xff)
-+			j++;
-+	}
-+
-+	if (j == 2) {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 2g PA Bias K no PG\n");
-+	} else {
-+		power_trim_info->pa_bias_trim[0][RF_PATH_A] = tssi_pa_bias_2g[0] & 0xf;
-+		power_trim_info->pa_bias_trim[0][RF_PATH_C] = (tssi_pa_bias_2g[0] & 0xf0) >> 4;
-+		power_trim_info->pa_bias_trim[0][RF_PATH_B] = tssi_pa_bias_2g[1] & 0xf;
-+		power_trim_info->pa_bias_trim[0][RF_PATH_D] = (tssi_pa_bias_2g[1] & 0xf0) >> 4;
-+
-+		for (k = 0; k < MAX_PATH_NUM_8814B; k++) {
-+			RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 2g PA Bias K efuse:0x%x path=%d\n",
-+				power_trim_info->pa_bias_trim[0][k], k);
-+			odm_set_rf_reg(dm, k, 0x60, 0x0000f000, power_trim_info->pa_bias_trim[0][k]);
-+		}
-+
-+#if 0
-+		for (k = 0; k < MAX_PATH_NUM_8814B; k++) {
-+			if ((power_trim_info->pa_bias_trim[0][k] & BIT(0)) == 0)
-+				power_trim_info->pa_bias_trim[0][k] = (-1 * (power_trim_info->pa_bias_trim[0][k] >> 1));
-+			else
-+				power_trim_info->pa_bias_trim[0][k] = (power_trim_info->pa_bias_trim[0][k] >> 1);
-+
-+			RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 2g PA Bias K power_trim_info->pa_bias_trim[0][%d]=0x%x\n",
-+				k, power_trim_info->pa_bias_trim[0][k]);
-+		}
-+
-+		phydm_set_pabias_bandedge_2g_rf_8814b(dm);
-+#endif	
-+	}
-+	
-+	odm_efuse_one_byte_read(dm, PPG_PABIAS_5GAC_14B, &tssi_pa_bias_5g[0], false);
-+	odm_efuse_one_byte_read(dm, PPG_PABIAS_5GBD_14B, &tssi_pa_bias_5g[1], false);
-+
-+	j = 0;
-+	for (i = 0; i < 2; i++) {
-+		if (tssi_pa_bias_5g[i] == 0xff)
-+			j++;
-+	}
-+
-+	if (j == 2) {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 5g PA Bias K no PG\n");
-+	} else {
-+		power_trim_info->pa_bias_trim[1][RF_PATH_A] = tssi_pa_bias_5g[0] & 0xf;
-+		power_trim_info->pa_bias_trim[1][RF_PATH_C] = (tssi_pa_bias_5g[0] & 0xf0) >> 4;
-+		power_trim_info->pa_bias_trim[1][RF_PATH_B] = tssi_pa_bias_5g[1] & 0xf;
-+		power_trim_info->pa_bias_trim[1][RF_PATH_D] = (tssi_pa_bias_5g[1] & 0xf0) >> 4;
-+
-+		for (k = 0; k < MAX_PATH_NUM_8814B; k++) {
-+			RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 5g PA Bias K efuse:0x%x path=%d\n",
-+				power_trim_info->pa_bias_trim[1][k], k);
-+
-+			odm_set_rf_reg(dm, k, 0x60, 0x000f0000, power_trim_info->pa_bias_trim[1][k]);
-+		}
-+#if 0
-+		for (k = 0; k < MAX_PATH_NUM_8814B; k++) {
-+			if ((power_trim_info->pa_bias_trim[1][k] & BIT(0)) == 0)
-+				power_trim_info->pa_bias_trim[1][k] = (-1 * (power_trim_info->pa_bias_trim[1][k] >> 1));
-+			else
-+				power_trim_info->pa_bias_trim[1][k] = (power_trim_info->pa_bias_trim[1][k] >> 1);
-+
-+			RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b 5g PA Bias K power_trim_info->pa_bias_trim[1][%d]=0x%x\n",
-+				k, power_trim_info->pa_bias_trim[1][k]);
-+ 		}
-+
-+		phydm_set_pabias_bandedge_5g_rf_8814b(dm);
-+#endif
-+	}
-+
-+	
-+}
-+
-+void phydm_get_thermal_trim_offset_8814b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	u8 pg_therm = 0xff, i;
-+
-+	odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_14B, &pg_therm, false);
-+
-+	if (pg_therm != 0xff) {
-+		for (i = 0; i < MAX_PATH_NUM_8814B; i++) {
-+			if (i == 0)
-+				odm_efuse_one_byte_read(dm, PPG_THERMAL_A_OFFSET_14B, &pg_therm, false);
-+			else if (i == 1)
-+				odm_efuse_one_byte_read(dm, PPG_THERMAL_B_OFFSET_14B, &pg_therm, false);
-+			else if (i == 2)
-+				odm_efuse_one_byte_read(dm, PPG_THERMAL_C_OFFSET_14B, &pg_therm, false);
-+			else if (i == 3)
-+				odm_efuse_one_byte_read(dm, PPG_THERMAL_D_OFFSET_14B, &pg_therm, false);
-+
-+			RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b Efuse thermal S%d:0x%x\n", i, pg_therm);
-+			pg_therm = pg_therm & 0x1f;
-+			if ((pg_therm & BIT(0)) == 0)
-+				power_trim_info->multi_thermal[i] = (-1 * (pg_therm >> 1));
-+			else
-+				power_trim_info->multi_thermal[i] = (pg_therm >> 1);
-+		}
-+
-+		power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b thermal trim flag:0x%02x\n",
-+	       power_trim_info->flag);
-+
-+	for (i = 0; i < MAX_RF_PATH; i++) {
-+		if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
-+			RF_DBG(dm, DBG_RF_MP, "[kfree] 8814b thermal S%d:%d\n",
-+			       i ,power_trim_info->multi_thermal[i]);
-+	}
-+}
-+
-+s8 phydm_get_tssi_trim_de(void *dm_void, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		return phydm_get_tssi_trim_de_8822c(dm, path);
-+	else if (dm->support_ic_type & ODM_RTL8812F)
-+		return phydm_get_tssi_trim_de_8812f(dm, path);
-+	else if (dm->support_ic_type & ODM_RTL8197G)
-+		return phydm_get_tssi_trim_de_8197g(dm, path);
-+	else if (dm->support_ic_type & ODM_RTL8814B)
-+		return phydm_get_tssi_trim_de_8814b(dm, path);
-+	else
-+		return 0;	
-+}
-+
-+void phydm_do_new_kfree(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_RTL8822C) {
-+		phydm_get_set_thermal_trim_offset_8822c(dm);
-+		phydm_get_set_power_trim_offset_8822c(dm);
-+		phydm_get_set_pa_bias_offset_8822c(dm);
-+		phydm_get_tssi_trim_offset_8822c(dm);
-+	}
-+
-+	if (dm->support_ic_type & ODM_RTL8812F) {
-+		phydm_get_set_thermal_trim_offset_8812f(dm);
-+		phydm_get_set_power_trim_offset_8812f(dm);
-+		phydm_get_set_pa_bias_offset_8812f(dm);
-+		phydm_get_tssi_trim_offset_8812f(dm);
-+	}
-+
-+	if (dm->support_ic_type & ODM_RTL8195B) {
-+		phydm_get_thermal_trim_offset_8195b(dm);
-+		phydm_get_set_power_trim_offset_8195b(dm);
-+		phydm_get_set_pa_bias_offset_8195b(dm);
-+	}
-+
-+	if (dm->support_ic_type & ODM_RTL8721D) {
-+		phydm_get_thermal_trim_offset_8721d(dm);
-+		phydm_get_set_power_trim_offset_8721d(dm);
-+		/*phydm_get_set_pa_bias_offset_8721d(dm);*/
-+	}
-+
-+	if (dm->support_ic_type & ODM_RTL8198F) {
-+		phydm_get_pa_bias_offset_8198f(dm);
-+		phydm_get_set_lna_offset_8198f(dm);
-+	}
-+
-+	if (dm->support_ic_type & ODM_RTL8197G) {
-+		phydm_get_thermal_trim_offset_8197g(dm);
-+		phydm_get_set_power_trim_offset_8197g(dm);
-+		phydm_get_set_pa_bias_offset_8197g(dm);
-+		phydm_get_tssi_trim_offset_8197g(dm);
-+		phydm_get_set_lna_offset_8197g(dm);
-+	}
-+
-+	if (dm->support_ic_type & ODM_RTL8710C) {
-+		phydm_get_thermal_trim_offset_8710c(dm);
-+		phydm_get_set_power_trim_offset_8710c(dm);
-+		phydm_get_set_pa_bias_offset_8710c(dm);
-+	}
-+
-+	if (dm->support_ic_type & ODM_RTL8814B) {
-+		phydm_get_thermal_trim_offset_8814b(dm);
-+		phydm_get_set_power_trim_offset_8814b(dm);
-+		phydm_get_pa_bias_offset_8814b(dm);
-+		phydm_get_tssi_trim_offset_8814b(dm);
-+	}
-+}
-+
-+void phydm_set_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_RTL8814A)
-+		phydm_set_kfree_to_rf_8814a(dm, e_rf_path, data);
-+
-+	if ((dm->support_ic_type & ODM_RTL8821C) &&
-+	    (*dm->band_type == ODM_BAND_2_4G))
-+		phydm_set_kfree_to_rf_8821c(dm, e_rf_path, true, data);
-+	else if (dm->support_ic_type & ODM_RTL8821C)
-+		phydm_set_kfree_to_rf_8821c(dm, e_rf_path, false, data);
-+
-+	if (dm->support_ic_type & ODM_RTL8822B)
-+		phydm_set_kfree_to_rf_8822b(dm, e_rf_path, data);
-+
-+	if (dm->support_ic_type & ODM_RTL8710B)
-+		phydm_set_kfree_to_rf_8710b(dm, e_rf_path, data);
-+
-+	if (dm->support_ic_type & ODM_RTL8198F)
-+		phydm_set_kfree_to_rf_8198f(dm, e_rf_path, data);
-+}
-+
-+void phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_RTL8822B)
-+		phydm_clear_kfree_to_rf_8822b(dm, e_rf_path, 1);
-+
-+	if (dm->support_ic_type & ODM_RTL8821C)
-+		phydm_clear_kfree_to_rf_8821c(dm, e_rf_path, 1);
-+
-+	if (dm->support_ic_type & ODM_RTL8198F)
-+		phydm_clear_kfree_to_rf_8198f(dm, e_rf_path, 0);
-+}
-+
-+void phydm_get_thermal_trim_offset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
-+	u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
-+
-+	if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n");
-+#endif
-+
-+	if (dm->support_ic_type & ODM_RTL8821C)
-+		phydm_get_thermal_trim_offset_8821c(dm_void);
-+	else if (dm->support_ic_type & ODM_RTL8822B)
-+		phydm_get_thermal_trim_offset_8822b(dm_void);
-+	else if (dm->support_ic_type & ODM_RTL8710B)
-+		phydm_get_thermal_trim_offset_8710b(dm_void);
-+	else if (dm->support_ic_type & ODM_RTL8192F)
-+		phydm_get_thermal_trim_offset_8192f(dm_void);
-+	else if (dm->support_ic_type & ODM_RTL8198F)
-+		phydm_get_thermal_trim_offset_8198f(dm_void);
-+}
-+
-+void phydm_get_power_trim_offset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if 0 //(DM_ODM_SUPPORT_TYPE & ODM_WIN)	// 2017 MH DM Should use the same code.s
-+	void		*adapter = dm->adapter;
-+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	PEFUSE_HAL		pEfuseHal = &hal_data->EfuseHal;
-+	u1Byte			eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
-+
-+	if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n");
-+#endif
-+
-+	if (dm->support_ic_type & ODM_RTL8821C)
-+		phydm_get_power_trim_offset_8821c(dm_void);
-+	else if (dm->support_ic_type & ODM_RTL8822B)
-+		phydm_get_power_trim_offset_8822b(dm_void);
-+	else if (dm->support_ic_type & ODM_RTL8710B)
-+		phydm_get_power_trim_offset_8710b(dm_void);
-+	else if (dm->support_ic_type & ODM_RTL8192F)
-+		phydm_get_power_trim_offset_8192f(dm_void);
-+	else if (dm->support_ic_type & ODM_RTL8198F)
-+		phydm_get_power_trim_offset_8198f(dm_void);
-+}
-+
-+void phydm_get_pa_bias_offset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
-+	u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
-+
-+	if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n");
-+#endif
-+
-+	if (dm->support_ic_type & ODM_RTL8822B)
-+		phydm_get_pa_bias_offset_8822b(dm_void);
-+}
-+
-+s8 phydm_get_thermal_offset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
-+		return power_trim_info->thermal;
-+	else
-+		return 0;
-+}
-+
-+s8 phydm_get_multi_thermal_offset(void *dm_void, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
-+
-+	if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
-+		return power_trim_info->multi_thermal[path];
-+	else
-+		return 0;
-+}
-+
-+void phydm_do_kfree(void *dm_void, u8 channel_to_sw)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_power_trim_data *pwrtrim = &dm->power_trim_data;
-+	u8 channel_idx = 0, rfpath = 0, max_path = 0, kfree_band_num = 0;
-+	u8 i, j;
-+	s8 bb_gain;
-+
-+	if (dm->support_ic_type & ODM_RTL8814A)
-+		max_path = 4; /*0~3*/
-+	else if (dm->support_ic_type &
-+		 (ODM_RTL8812 | ODM_RTL8822B | ODM_RTL8192F)) {
-+		max_path = 2; /*0~1*/
-+		kfree_band_num = KFREE_BAND_NUM;
-+	} else if (dm->support_ic_type & ODM_RTL8821C) {
-+		max_path = 1;
-+		kfree_band_num = KFREE_BAND_NUM;
-+	} else if (dm->support_ic_type & ODM_RTL8710B) {
-+		max_path = 1;
-+		kfree_band_num = 1;
-+	} else if (dm->support_ic_type & ODM_RTL8198F) {
-+		max_path = 4;
-+		kfree_band_num = 3;
-+	}
-+
-+	if (dm->support_ic_type &
-+	    (ODM_RTL8192F | ODM_RTL8822B | ODM_RTL8821C |
-+	    ODM_RTL8814A | ODM_RTL8710B)) {
-+		for (i = 0; i < kfree_band_num; i++) {
-+			for (j = 0; j < max_path; j++)
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] PwrTrim->gain[%d][%d]=0x%X\n",
-+				       i, j, pwrtrim->bb_gain[i][j]);
-+		}
-+	}
-+	if (*dm->band_type == ODM_BAND_2_4G &&
-+	    pwrtrim->flag & KFREE_FLAG_ON_2G) {
-+		if (!(dm->support_ic_type & ODM_RTL8192F)) {
-+			if (channel_to_sw >= 1 && channel_to_sw <= 14)
-+				channel_idx = PHYDM_2G;
-+			for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] %s:chnl=%d PATH=%d gain:0x%X\n",
-+				       __func__, channel_to_sw, rfpath,
-+				       pwrtrim->bb_gain[channel_idx][rfpath]);
-+				bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
-+				phydm_set_kfree_to_rf(dm, rfpath, bb_gain);
-+			}
-+		} else if (dm->support_ic_type & ODM_RTL8192F) {
-+			if (channel_to_sw >= 1 && channel_to_sw <= 3)
-+				channel_idx = 0;
-+			if (channel_to_sw >= 4 && channel_to_sw <= 9)
-+				channel_idx = 1;
-+			if (channel_to_sw >= 10 && channel_to_sw <= 14)
-+				channel_idx = 2;
-+			for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
-+				RF_DBG(dm, DBG_RF_MP,
-+				       "[kfree] %s:chnl=%d PATH=%d gain:0x%X\n",
-+				       __func__, channel_to_sw, rfpath,
-+				       pwrtrim->bb_gain[channel_idx][rfpath]);
-+				bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
-+				phydm_set_kfree_to_rf_8192f(dm, rfpath,
-+							    channel_idx,
-+							    bb_gain);
-+			}
-+		}
-+	} else if (*dm->band_type == ODM_BAND_5G &&
-+		   pwrtrim->flag & KFREE_FLAG_ON_5G) {
-+		if (channel_to_sw >= 36 && channel_to_sw <= 48)
-+			channel_idx = PHYDM_5GLB1;
-+		if (channel_to_sw >= 52 && channel_to_sw <= 64)
-+			channel_idx = PHYDM_5GLB2;
-+		if (channel_to_sw >= 100 && channel_to_sw <= 120)
-+			channel_idx = PHYDM_5GMB1;
-+		if (channel_to_sw >= 122 && channel_to_sw <= 144)
-+			channel_idx = PHYDM_5GMB2;
-+		if (channel_to_sw >= 149 && channel_to_sw <= 177)
-+			channel_idx = PHYDM_5GHB;
-+
-+		for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
-+			RF_DBG(dm, DBG_RF_MP,
-+			       "[kfree] %s: channel=%d PATH=%d bb_gain:0x%X\n",
-+			       __func__, channel_to_sw, rfpath,
-+			       pwrtrim->bb_gain[channel_idx][rfpath]);
-+			bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
-+			phydm_set_kfree_to_rf(dm, rfpath, bb_gain);
-+		}
-+	} else {
-+		RF_DBG(dm, DBG_RF_MP, "[kfree] Set default Register\n");
-+		if (!(dm->support_ic_type & ODM_RTL8192F)) {
-+			for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) {
-+				bb_gain = pwrtrim->bb_gain[channel_idx][rfpath];
-+				phydm_clear_kfree_to_rf(dm, rfpath, bb_gain);
-+			}
-+		}
-+#if 0
-+		/*else if(dm->support_ic_type & ODM_RTL8192F){
-+			if (channel_to_sw >= 1 && channel_to_sw <= 3)
-+				channel_idx = 0;
-+			if (channel_to_sw >= 4 && channel_to_sw <= 9)
-+				channel_idx = 1;
-+			if (channel_to_sw >= 9 && channel_to_sw <= 14)
-+				channel_idx = 2;
-+			for (rfpath = RF_PATH_A;  rfpath < max_path; rfpath++)
-+				phydm_clear_kfree_to_rf_8192f(dm, rfpath, pwrtrim->bb_gain[channel_idx][rfpath]);
-+		}*/
-+#endif
-+	}
-+}
-+
-+void phydm_config_new_kfree(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-+
-+	if (cali_info->reg_rf_kfree_enable == 2) {
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] %s: reg_rf_kfree_enable == 2, Disable\n",
-+		       __func__);
-+		return;
-+	} else if (cali_info->reg_rf_kfree_enable == 1 ||
-+			cali_info->reg_rf_kfree_enable == 0) {
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] %s: reg_rf_kfree_enable == true\n", __func__);
-+	
-+		phydm_do_new_kfree(dm);
-+	}
-+}
-+
-+void phydm_config_kfree(void *dm_void, u8 channel_to_sw)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-+	struct odm_power_trim_data *pwrtrim = &dm->power_trim_data;
-+
-+	RF_DBG(dm, DBG_RF_MP, "===>[kfree] phy_ConfigKFree()\n");
-+
-+	if (cali_info->reg_rf_kfree_enable == 2) {
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] %s: reg_rf_kfree_enable == 2, Disable\n",
-+		       __func__);
-+		return;
-+	} else if (cali_info->reg_rf_kfree_enable == 1 ||
-+			cali_info->reg_rf_kfree_enable == 0) {
-+		RF_DBG(dm, DBG_RF_MP,
-+		       "[kfree] %s: reg_rf_kfree_enable == true\n", __func__);
-+		/*Make sure the targetval is defined*/
-+		if (!(pwrtrim->flag & KFREE_FLAG_ON)) {
-+			RF_DBG(dm, DBG_RF_MP,
-+			       "[kfree] %s: efuse is 0xff, KFree not work\n",
-+			       __func__);
-+			return;
-+		}
-+#if 0
-+		/*if kfree_table[0] == 0xff, means no Kfree*/
-+#endif
-+		phydm_do_kfree(dm, channel_to_sw);
-+	}
-+	RF_DBG(dm, DBG_RF_MP, "<===[kfree] phy_ConfigKFree()\n");
-+}
-+
-+void phydm_set_lna_trim_offset (void *dm_void, u8 path, u8 cg_cs, u8 enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_RTL8197G)
-+		phydm_set_lna_trim_offset_8197g(dm, path, cg_cs, enable);
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_kfree.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_kfree.h
-new file mode 100644
-index 000000000000..2de6b6bb9d63
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_kfree.h
-@@ -0,0 +1,296 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_KFREE_H__
-+#define __HALRF_KFREE_H__
-+
-+#define KFREE_VERSION "1.0"
-+
-+#define KFREE_BAND_NUM 9
-+#define KFREE_CH_NUM 3
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
-+
-+#define BB_GAIN_NUM 6
-+
-+#endif
-+
-+#define KFREE_FLAG_ON BIT(0)
-+#define KFREE_FLAG_THERMAL_K_ON BIT(1)
-+
-+#define KFREE_FLAG_ON_2G BIT(2)
-+#define KFREE_FLAG_ON_5G BIT(3)
-+
-+#define PA_BIAS_FLAG_ON BIT(4)
-+
-+#define TSSI_TRIM_FLAG_ON BIT(5)
-+
-+#define LNA_FLAG_ON BIT(6)
-+
-+
-+#define PPG_THERMAL_OFFSET_98F 0x50
-+#define PPG_2GM_TXAB_98F 0x51
-+#define PPG_2GM_TXCD_98F 0x52
-+#define PPG_2GL_TXAB_98F 0x53
-+#define PPG_2GL_TXCD_98F 0x54
-+#define PPG_2GH_TXAB_98F 0x55
-+#define PPG_2GH_TXCD_98F 0x56
-+
-+#define PPG_PABIAS_2GAB_98F 0x57
-+#define PPG_PABIAS_2GCD_98F 0x58
-+
-+#define PPG_LNA_2GA_98F 0x59
-+#define PPG_LNA_2GB_98F 0x5a
-+#define PPG_LNA_2GC_98F 0x5b
-+#define PPG_LNA_2GD_98F 0x5c
-+
-+#define PPG_THERMAL_OFFSET_21C 0x1EF
-+#define PPG_2G_TXAB_21C 0x1EE
-+#define PPG_5GL1_TXA_21C 0x1EC
-+#define PPG_5GL2_TXA_21C 0x1E8
-+#define PPG_5GM1_TXA_21C 0x1E4
-+#define PPG_5GM2_TXA_21C 0x1E0
-+#define PPG_5GH1_TXA_21C 0x1DC
-+
-+#define PPG_THERMAL_OFFSET_22B 0x3EF
-+#define PPG_2G_TXAB_22B 0x3EE
-+#define PPG_2G_TXCD_22B 0x3ED
-+#define PPG_5GL1_TXA_22B 0x3EC
-+#define PPG_5GL1_TXB_22B 0x3EB
-+#define PPG_5GL1_TXC_22B 0x3EA
-+#define PPG_5GL1_TXD_22B 0x3E9
-+#define PPG_5GL2_TXA_22B 0x3E8
-+#define PPG_5GL2_TXB_22B 0x3E7
-+#define PPG_5GL2_TXC_22B 0x3E6
-+#define PPG_5GL2_TXD_22B 0x3E5
-+#define PPG_5GM1_TXA_22B 0x3E4
-+#define PPG_5GM1_TXB_22B 0x3E3
-+#define PPG_5GM1_TXC_22B 0x3E2
-+#define PPG_5GM1_TXD_22B 0x3E1
-+#define PPG_5GM2_TXA_22B 0x3E0
-+#define PPG_5GM2_TXB_22B 0x3DF
-+#define PPG_5GM2_TXC_22B 0x3DE
-+#define PPG_5GM2_TXD_22B 0x3DD
-+#define PPG_5GH1_TXA_22B 0x3DC
-+#define PPG_5GH1_TXB_22B 0x3DB
-+#define PPG_5GH1_TXC_22B 0x3DA
-+#define PPG_5GH1_TXD_22B 0x3D9
-+
-+#define PPG_PABIAS_2GA_22B 0x3D5
-+#define PPG_PABIAS_2GB_22B 0x3D6
-+
-+#define PPG_THERMAL_A_OFFSET_22C 0x1ef
-+#define PPG_THERMAL_B_OFFSET_22C 0x1b0
-+#define PPG_2GL_TXAB_22C 0x1d4
-+#define PPG_2GM_TXAB_22C 0x1ee
-+#define PPG_2GH_TXAB_22C 0x1d2
-+#define PPG_5GL1_TXA_22C 0x1ec
-+#define PPG_5GL1_TXB_22C 0x1eb
-+#define PPG_5GL2_TXA_22C 0x1e8
-+#define PPG_5GL2_TXB_22C 0x1e7
-+#define PPG_5GM1_TXA_22C 0x1e4
-+#define PPG_5GM1_TXB_22C 0x1e3
-+#define PPG_5GM2_TXA_22C 0x1e0
-+#define PPG_5GM2_TXB_22C 0x1df
-+#define PPG_5GH1_TXA_22C 0x1dc
-+#define PPG_5GH1_TXB_22C 0x1db
-+
-+#define PPG_PABIAS_2GA_22C 0x1d6
-+#define PPG_PABIAS_2GB_22C 0x1d5
-+#define PPG_PABIAS_5GA_22C 0x1d8
-+#define PPG_PABIAS_5GB_22C 0x1d7
-+
-+#define TSSI_2GM_TXA_22C 0x1c0
-+#define TSSI_2GM_TXB_22C 0x1bf
-+#define TSSI_2GH_TXA_22C 0x1be
-+#define TSSI_2GH_TXB_22C 0x1bd
-+#define TSSI_5GL1_TXA_22C 0x1bc
-+#define TSSI_5GL1_TXB_22C 0x1bb
-+#define TSSI_5GL2_TXA_22C 0x1ba
-+#define TSSI_5GL2_TXB_22C 0x1b9
-+#define TSSI_5GM1_TXA_22C 0x1b8
-+#define TSSI_5GM1_TXB_22C 0x1b7
-+#define TSSI_5GM2_TXA_22C 0x1b6
-+#define TSSI_5GM2_TXB_22C 0x1b5
-+#define TSSI_5GH1_TXA_22C 0x1b4
-+#define TSSI_5GH1_TXB_22C 0x1b3
-+#define TSSI_5GH2_TXA_22C 0x1b2
-+#define TSSI_5GH2_TXB_22C 0x1b1
-+ 
-+/*8195B*/
-+#define PPG_THERMAL_OFFSET_95B 0x1ef
-+#define PPG_2GL_TXA_95B 0x1d4
-+#define PPG_2GM_TXA_95B 0x1ee
-+#define PPG_2GH_TXA_95B 0x1d2
-+#define PPG_5GL1_TXA_95B 0x1ec
-+#define PPG_5GL2_TXA_95B 0x1e8
-+#define PPG_5GM1_TXA_95B 0x1e4
-+#define PPG_5GM2_TXA_95B 0x1e0
-+#define PPG_5GH1_TXA_95B 0x1dc
-+
-+#define PPG_PABIAS_2GA_95B 0x1d6
-+#define PPG_PABIAS_5GA_95B 0x1d8
-+
-+/*8721D*/
-+/*#define KFREE_BAND_NUM_8721D 6*/
-+#define PPG_THERMAL_OFFSET_8721D 0x1EF
-+#define PPG_2G_TXA_8721D 0x1EE
-+#define PPG_5GL1_TXA_8721D 0x1ED
-+#define PPG_5GL2_TXA_8721D 0x1EC
-+#define PPG_5GM1_TXA_8721D 0x1EB
-+#define PPG_5GM2_TXA_8721D 0x1EA
-+#define PPG_5GH1_TXA_8721D 0x1E9
-+
-+/*8197G*/
-+#define PPG_THERMAL_A_OFFSET_97G 0x50
-+#define PPG_THERMAL_B_OFFSET_97G 0x27
-+#define PPG_2GM_TXAB_97G 0x51
-+#define PPG_2GL_TXAB_97G 0x53
-+#define PPG_2GH_TXAB_97G 0x55
-+#define TSSI_2GL_TXA_97G 0x1c
-+#define TSSI_2GL_TXB_97G 0x1d
-+#define TSSI_2GH_TXA_97G 0x1e
-+#define TSSI_2GH_TXB_97G 0x1f
-+#define PPG_PABIAS_2GAB_97G 0x57
-+#define PPG_LNA_2GA_97G 0x21
-+#define PPG_LNA_2GB_97G 0x22
-+
-+/*8710C Ameba Z2*/
-+#define PPG_THERMAL_OFFSET_10C 0x1EF
-+#define PPG_2GL_TX_10C 0x1D4
-+#define PPG_2GM_TX_10C 0x1EE
-+#define PPG_2GH_TX_10C 0x1D2
-+#define PPG_PABIAS_10C 0x1D6
-+#define PPG_LNA_10C 0x1D0
-+
-+/*8814B*/
-+#define PPG_2GL_TXAB_14B 0x3ee
-+#define PPG_2GL_TXCD_14B 0x3ed
-+#define PPG_5GL1_TXA_14B 0x3ec
-+#define PPG_5GL1_TXB_14B 0x3eb
-+#define PPG_5GL1_TXC_14B 0x3ea
-+#define PPG_5GL1_TXD_14B 0x3e9
-+#define PPG_5GL2_TXA_14B 0x3e8
-+#define PPG_5GL2_TXB_14B 0x3e7
-+#define PPG_5GL2_TXC_14B 0x3e6
-+#define PPG_5GL2_TXD_14B 0x3e5
-+#define PPG_5GM1_TXA_14B 0x3e4
-+#define PPG_5GM1_TXB_14B 0x3e3
-+#define PPG_5GM1_TXC_14B 0x3e2
-+#define PPG_5GM1_TXD_14B 0x3e1
-+#define PPG_5GM2_TXA_14B 0x3e0
-+#define PPG_5GM2_TXB_14B 0x3df
-+#define PPG_5GM2_TXC_14B 0x3de
-+#define PPG_5GM2_TXD_14B 0x3dd
-+#define PPG_5GH1_TXA_14B 0x3dc
-+#define PPG_5GH1_TXB_14B 0x3db
-+#define PPG_5GH1_TXC_14B 0x3da
-+#define PPG_5GH1_TXD_14B 0x3d9
-+#define PPG_PABIAS_5GAC_14B 0x3d8
-+#define PPG_PABIAS_5GBD_14B 0x3d7
-+#define PPG_PABIAS_2GAC_14B 0x3d6
-+#define PPG_PABIAS_2GBD_14B 0x3d5
-+
-+#define PPG_THERMAL_A_OFFSET_14B 0x3D4
-+#define PPG_THERMAL_B_OFFSET_14B 0x3D3
-+#define PPG_THERMAL_C_OFFSET_14B 0x3D2
-+#define PPG_THERMAL_D_OFFSET_14B 0x3D1
-+
-+#define TSSI_2GM_TXA_14B 0x3c0
-+#define TSSI_2GM_TXB_14B 0x3bf
-+#define TSSI_2GM_TXC_14B 0x3be
-+#define TSSI_2GM_TXD_14B 0x3bd
-+#define TSSI_2GH_TXA_14B 0x3bc
-+#define TSSI_2GH_TXB_14B 0x3bb
-+#define TSSI_2GH_TXC_14B 0x3ba
-+#define TSSI_2GH_TXD_14B 0x3b9
-+#define TSSI_5GL1_TXA_14B 0x3b8
-+#define TSSI_5GL1_TXB_14B 0x3b7
-+#define TSSI_5GL1_TXC_14B 0x3b6
-+#define TSSI_5GL1_TXD_14B 0x3b5
-+#define TSSI_5GL2_TXA_14B 0x3b4
-+#define TSSI_5GL2_TXB_14B 0x3b3
-+#define TSSI_5GL2_TXC_14B 0x3b2
-+#define TSSI_5GL2_TXD_14B 0x3b1
-+#define TSSI_5GM1_TXA_14B 0x3b0
-+#define TSSI_5GM1_TXB_14B 0x3af
-+#define TSSI_5GM1_TXC_14B 0x3ae
-+#define TSSI_5GM1_TXD_14B 0x3ad
-+#define TSSI_5GM2_TXA_14B 0x3ac
-+#define TSSI_5GM2_TXB_14B 0x3ab
-+#define TSSI_5GM2_TXC_14B 0x3aa
-+#define TSSI_5GM2_TXD_14B 0x3a9
-+#define TSSI_5GH1_TXA_14B 0x3a8
-+#define TSSI_5GH1_TXB_14B 0x3a7
-+#define TSSI_5GH1_TXC_14B 0x3a6
-+#define TSSI_5GH1_TXD_14B 0x3a5
-+#define TSSI_5GH2_TXA_14B 0x3a4
-+#define TSSI_5GH2_TXB_14B 0x3a3
-+#define TSSI_5GH2_TXC_14B 0x3a2
-+#define TSSI_5GH2_TXD_14B 0x3a1
-+
-+
-+struct odm_power_trim_data {
-+	u8 flag;
-+	u8 pa_bias_flag;
-+	u8 lna_flag;
-+	s8 bb_gain[KFREE_BAND_NUM][MAX_RF_PATH];
-+	s8 tssi_trim[KFREE_BAND_NUM][MAX_RF_PATH];
-+	s8 pa_bias_trim[KFREE_BAND_NUM][MAX_RF_PATH];
-+	s8 lna_trim[MAX_RF_PATH];
-+	s8 thermal;
-+	s8 multi_thermal[MAX_RF_PATH];
-+};
-+
-+enum phydm_kfree_channeltosw {
-+	PHYDM_2G = 0,
-+	PHYDM_5GLB1 = 1,
-+	PHYDM_5GLB2 = 2,
-+	PHYDM_5GMB1 = 3,
-+	PHYDM_5GMB2 = 4,
-+	PHYDM_5GHB = 5,
-+};
-+
-+void phydm_get_thermal_trim_offset(void *dm_void);
-+
-+void phydm_get_power_trim_offset(void *dm_void);
-+
-+void phydm_get_pa_bias_offset(void *dm_void);
-+
-+s8 phydm_get_thermal_offset(void *dm_void);
-+
-+s8 phydm_get_multi_thermal_offset(void *dm_void, u8 path);
-+
-+void phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data);
-+
-+void phydm_config_new_kfree(void *dm_void);
-+
-+s8 phydm_get_tssi_trim_de(void *dm_void, u8 path);
-+
-+void phydm_config_kfree(void *dm_void, u8 channel_to_sw);
-+
-+void phydm_set_lna_trim_offset (void *dm_void, u8 path, u8 cg_cs, u8 enable);
-+
-+#endif /*__HALRF_KFREE_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking.c
-new file mode 100644
-index 000000000000..a1db18f95e8c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking.c
-@@ -0,0 +1,186 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ * ************************************************************
-+ */
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+boolean
-+odm_check_power_status(void *dm_void)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	PADAPTER *adapter = dm->adapter;
-+
-+	RT_RF_POWER_STATE rt_state;
-+	MGNT_INFO *mgnt_info = &((PADAPTER)adapter)->MgntInfo;
-+
-+	/* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
-+	if (mgnt_info->init_adpt_in_progress == true) {
-+		RF_DBG(dm, DBG_RF_INIT,
-+		       "check_pow_status Return true, due to initadapter\n");
-+		return true;
-+	}
-+
-+	/*
-+	 *	2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
-+	 */
-+	((PADAPTER)adapter)->HalFunc.GetHwRegHandler((PADAPTER)adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state));
-+	if (((PADAPTER)adapter)->bDriverStopped || ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) {
-+		RF_DBG(dm, DBG_RF_INIT,
-+		       "check_pow_status Return false, due to %d/%d/%d\n",
-+		       ((PADAPTER)adapter)->bDriverStopped,
-+		       ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep,
-+		       rt_state);
-+		return false;
-+	}
-+#endif
-+	return true;
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+void halrf_update_pwr_track(void *dm_void, u8 rate)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	u8 path_idx = 0;
-+#endif
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n", rate);
-+
-+	dm->tx_rate = rate;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+#if USE_WORKITEM
-+	odm_schedule_work_item(&dm->ra_rpt_workitem);
-+#else
-+	if (dm->support_ic_type == ODM_RTL8821) {
-+#if (RTL8821A_SUPPORT == 1)
-+		odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
-+#endif
-+	} else if (dm->support_ic_type == ODM_RTL8812) {
-+		for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) {
-+#if (RTL8812A_SUPPORT == 1)
-+			odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, path_idx, 0);
-+#endif
-+		}
-+	} else if (dm->support_ic_type == ODM_RTL8723B) {
-+#if (RTL8723B_SUPPORT == 1)
-+		odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
-+#endif
-+	} else if (dm->support_ic_type == ODM_RTL8192E) {
-+		for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) {
-+#if (RTL8192E_SUPPORT == 1)
-+			odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, path_idx, 0);
-+#endif
-+		}
-+	} else if (dm->support_ic_type == ODM_RTL8188E) {
-+#if (RTL8188E_SUPPORT == 1)
-+		odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
-+#endif
-+	}
-+#endif
-+#else
-+	odm_schedule_work_item(&dm->ra_rpt_workitem);
-+#endif
-+#endif
-+}
-+
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void halrf_update_init_rate_work_item_callback(
-+	void *context)
-+{
-+	void *adapter = (void *)context;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+	u8 p = 0;
-+
-+	if (dm->support_ic_type == ODM_RTL8821) {
-+#if (RTL8821A_SUPPORT == 1)
-+		odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
-+#endif
-+	} else if (dm->support_ic_type == ODM_RTL8812) {
-+#if (RTL8812A_SUPPORT == 1)
-+		/*Don't know how to include &c*/
-+		for (p = RF_PATH_A; p < MAX_PATH_NUM_8812A; p++)
-+			odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, p, 0);
-+#endif
-+	} else if (dm->support_ic_type == ODM_RTL8723B) {
-+#if (RTL8723B_SUPPORT == 1)
-+		odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
-+#endif
-+	} else if (dm->support_ic_type == ODM_RTL8192E) {
-+#if (RTL8192E_SUPPORT == 1)
-+		/*Don't know how to include &c*/
-+		for (p = RF_PATH_A; p < MAX_PATH_NUM_8192E; p++)
-+			odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, p, 0);
-+#endif
-+	} else if (dm->support_ic_type == ODM_RTL8188E) {
-+#if (RTL8188E_SUPPORT == 1)
-+		odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
-+#endif
-+	}
-+}
-+#endif
-+
-+void halrf_set_pwr_track(void *dm_void, u8 enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+	struct txpwrtrack_cfg c;
-+	u8 i;
-+
-+	configure_txpower_track(dm, &c);
-+	if (enable) {
-+		rf->rf_supportability = rf->rf_supportability | HAL_RF_TX_PWR_TRACK;
-+		if (cali_info->txpowertrack_control == 1 || cali_info->txpowertrack_control == 3)
-+			halrf_do_tssi(dm);
-+	} else {
-+		rf->rf_supportability = rf->rf_supportability & ~HAL_RF_TX_PWR_TRACK;
-+		odm_clear_txpowertracking_state(dm);
-+		halrf_do_tssi(dm);
-+		halrf_calculate_tssi_codeword(dm);
-+		halrf_set_tssi_codeword(dm);
-+		
-+#if !(RTL8723F_SUPPORT == 1)
-+		for (i = 0; i < c.rf_path_count; i++)
-+			(*c.odm_tx_pwr_track_set_pwr)(dm, CLEAN_MODE, i, 0);
-+#endif
-+	}
-+
-+	if (cali_info->txpowertrack_control == 2 ||
-+		cali_info->txpowertrack_control == 3 ||
-+		cali_info->txpowertrack_control == 4 ||
-+		cali_info->txpowertrack_control == 5)
-+		halrf_txgapk_reload_tx_gain(dm);
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking.h
-new file mode 100644
-index 000000000000..c81f25225d7a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking.h
-@@ -0,0 +1,43 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_POWER_TRACKING_H__
-+#define __HALRF_POWER_TRACKING_H__
-+
-+boolean
-+odm_check_power_status(void *dm_void);
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+void halrf_update_pwr_track(void *dm_void, u8 rate);
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void halrf_update_init_rate_work_item_callback(
-+	void *context);
-+#endif
-+
-+void halrf_set_pwr_track(void *dm_void, u8 enable);
-+
-+#endif /*#ifndef __HALRF_POWERTRACKING_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_ap.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_ap.c
-new file mode 100644
-index 000000000000..28a8091fa402
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_ap.c
-@@ -0,0 +1,1290 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/* ************************************************************
-+ * include files
-+ * ************************************************************ */
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#if !defined(_OUTSRC_COEXIST)
-+/* ************************************************************
-+ * Global var
-+ * ************************************************************ */
-+
-+
-+u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D] = {
-+	0x0b40002d, /* 0,  -15.0dB */
-+	0x0c000030, /* 1,  -14.5dB */
-+	0x0cc00033, /* 2,  -14.0dB */
-+	0x0d800036, /* 3,  -13.5dB */
-+	0x0e400039, /* 4,  -13.0dB */
-+	0x0f00003c, /* 5,  -12.5dB */
-+	0x10000040, /* 6,  -12.0dB */
-+	0x11000044, /* 7,  -11.5dB */
-+	0x12000048, /* 8,  -11.0dB */
-+	0x1300004c, /* 9,  -10.5dB */
-+	0x14400051, /* 10, -10.0dB */
-+	0x15800056, /* 11, -9.5dB */
-+	0x16c0005b, /* 12, -9.0dB */
-+	0x18000060, /* 13, -8.5dB */
-+	0x19800066, /* 14, -8.0dB */
-+	0x1b00006c, /* 15, -7.5dB */
-+	0x1c800072, /* 16, -7.0dB */
-+	0x1e400079, /* 17, -6.5dB */
-+	0x20000080, /* 18, -6.0dB */
-+	0x22000088, /* 19, -5.5dB */
-+	0x24000090, /* 20, -5.0dB */
-+	0x26000098, /* 21, -4.5dB */
-+	0x288000a2, /* 22, -4.0dB */
-+	0x2ac000ab, /* 23, -3.5dB */
-+	0x2d4000b5, /* 24, -3.0dB */
-+	0x300000c0, /* 25, -2.5dB */
-+	0x32c000cb, /* 26, -2.0dB */
-+	0x35c000d7, /* 27, -1.5dB */
-+	0x390000e4, /* 28, -1.0dB */
-+	0x3c8000f2, /* 29, -0.5dB */
-+	0x40000100, /* 30, +0dB */
-+	0x43c0010f, /* 31, +0.5dB */
-+	0x47c0011f, /* 32, +1.0dB */
-+	0x4c000130, /* 33, +1.5dB */
-+	0x50800142, /* 34, +2.0dB */
-+	0x55400155, /* 35, +2.5dB */
-+	0x5a400169, /* 36, +3.0dB */
-+	0x5fc0017f, /* 37, +3.5dB */
-+	0x65400195, /* 38, +4.0dB */
-+	0x6b8001ae, /* 39, +4.5dB */
-+	0x71c001c7, /* 40, +5.0dB */
-+	0x788001e2, /* 41, +5.5dB */
-+	0x7f8001fe  /* 42, +6.0dB */
-+};
-+
-+u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
-+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/* 0, -16.0dB */
-+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 1, -15.5dB */
-+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 2, -15.0dB */
-+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 3, -14.5dB */
-+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 4, -14.0dB */
-+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 5, -13.5dB */
-+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 6, -13.0dB */
-+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 7, -12.5dB */
-+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 8, -12.0dB */
-+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 9, -11.5dB */
-+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 10, -11.0dB */
-+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 11, -10.5dB */
-+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 12, -10.0dB */
-+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 13, -9.5dB */
-+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 14, -9.0dB */
-+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 15, -8.5dB */
-+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
-+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 17, -7.5dB */
-+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 18, -7.0dB */
-+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 19, -6.5dB */
-+	{0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02},	/* 20, -6.0dB */
-+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 21, -5.5dB */
-+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
-+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 23, -4.5dB */
-+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 24, -4.0dB */
-+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 25, -3.5dB */
-+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 26, -3.0dB */
-+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 27, -2.5dB */
-+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 28, -2.0dB */
-+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 29, -1.5dB */
-+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 30, -1.0dB */
-+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 31, -0.5dB */
-+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/* 32, +0dB */
-+};
-+
-+
-+u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
-+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/* 0, -16.0dB */
-+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB */
-+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 2, -15.0dB */
-+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB */
-+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 4, -14.0dB */
-+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 5, -13.5dB */
-+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB */
-+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 7, -12.5dB */
-+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB */
-+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB */
-+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB */
-+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 11, -10.5dB */
-+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB */
-+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB */
-+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 14, -9.0dB */
-+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB */
-+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
-+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB */
-+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
-+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
-+	{0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
-+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB */
-+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
-+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 23, -4.5dB */
-+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
-+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
-+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
-+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 27, -2.5dB */
-+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
-+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 29, -1.5dB */
-+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
-+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
-+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB */
-+};
-+
-+u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D] = {
-+	0x0b40002d, /* 0,  -15.0dB */
-+	0x0c000030, /* 1,  -14.5dB */
-+	0x0cc00033, /* 2,  -14.0dB */
-+	0x0d800036, /* 3,  -13.5dB */
-+	0x0e400039, /* 4,  -13.0dB */
-+	0x0f00003c, /* 5,  -12.5dB */
-+	0x10000040, /* 6,  -12.0dB */
-+	0x11000044, /* 7,  -11.5dB */
-+	0x12000048, /* 8,  -11.0dB */
-+	0x1300004c, /* 9,  -10.5dB */
-+	0x14400051, /* 10, -10.0dB */
-+	0x15800056, /* 11, -9.5dB */
-+	0x16c0005b, /* 12, -9.0dB */
-+	0x18000060, /* 13, -8.5dB */
-+	0x19800066, /* 14, -8.0dB */
-+	0x1b00006c, /* 15, -7.5dB */
-+	0x1c800072, /* 16, -7.0dB */
-+	0x1e400079, /* 17, -6.5dB */
-+	0x20000080, /* 18, -6.0dB */
-+	0x22000088, /* 19, -5.5dB */
-+	0x24000090, /* 20, -5.0dB */
-+	0x26000098, /* 21, -4.5dB */
-+	0x288000a2, /* 22, -4.0dB */
-+	0x2ac000ab, /* 23, -3.5dB */
-+	0x2d4000b5, /* 24, -3.0dB */
-+	0x300000c0, /* 25, -2.5dB */
-+	0x32c000cb, /* 26, -2.0dB */
-+	0x35c000d7, /* 27, -1.5dB */
-+	0x390000e4, /* 28, -1.0dB */
-+	0x3c8000f2, /* 29, -0.5dB */
-+	0x40000100, /* 30, +0dB */
-+	0x43c0010f, /* 31, +0.5dB */
-+	0x47c0011f, /* 32, +1.0dB */
-+	0x4c000130, /* 33, +1.5dB */
-+	0x50800142, /* 34, +2.0dB */
-+	0x55400155, /* 35, +2.5dB */
-+	0x5a400169, /* 36, +3.0dB */
-+	0x5fc0017f, /* 37, +3.5dB */
-+	0x65400195, /* 38, +4.0dB */
-+	0x6b8001ae, /* 39, +4.5dB */
-+	0x71c001c7, /* 40, +5.0dB */
-+	0x788001e2, /* 41, +5.5dB */
-+	0x7f8001fe  /* 42, +6.0dB */
-+};
-+
-+
-+u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
-+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/* 0, -16.0dB */
-+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 1, -15.5dB */
-+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 2, -15.0dB */
-+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 3, -14.5dB */
-+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 4, -14.0dB */
-+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 5, -13.5dB */
-+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 6, -13.0dB */
-+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 7, -12.5dB */
-+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 8, -12.0dB */
-+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 9, -11.5dB */
-+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 10, -11.0dB */
-+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 11, -10.5dB */
-+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 12, -10.0dB */
-+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 13, -9.5dB */
-+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 14, -9.0dB */
-+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 15, -8.5dB */
-+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
-+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 17, -7.5dB */
-+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 18, -7.0dB */
-+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 19, -6.5dB */
-+	{0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02},	/* 20, -6.0dB */
-+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 21, -5.5dB */
-+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
-+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 23, -4.5dB */
-+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 24, -4.0dB */
-+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 25, -3.5dB */
-+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 26, -3.0dB */
-+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 27, -2.5dB */
-+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 28, -2.0dB */
-+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 29, -1.5dB */
-+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 30, -1.0dB */
-+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 31, -0.5dB */
-+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/* 32, +0dB */
-+};
-+
-+
-+u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
-+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/* 0, -16.0dB */
-+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB */
-+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 2, -15.0dB */
-+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB */
-+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 4, -14.0dB */
-+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 5, -13.5dB */
-+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB */
-+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 7, -12.5dB */
-+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB */
-+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB */
-+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB */
-+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 11, -10.5dB */
-+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB */
-+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB */
-+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 14, -9.0dB */
-+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB */
-+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
-+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB */
-+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
-+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
-+	{0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
-+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB */
-+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
-+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 23, -4.5dB */
-+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
-+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
-+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
-+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 27, -2.5dB */
-+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
-+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 29, -1.5dB */
-+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
-+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
-+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB */
-+};
-+
-+u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
-+	{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 0  -16dB */
-+	{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 1  -15.5dB */
-+	{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 2  -15dB */
-+	{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 3  -14.5dB */
-+	{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 4  -14dB */
-+	{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 5  -13.5dB */
-+	{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 6  -13dB */
-+	{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 7  -12.5dB */
-+	{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 8  -12dB */
-+	{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 9  -11.5dB */
-+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 10  -11dB */
-+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 11  -10.5dB */
-+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 12  -10dB */
-+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 13  -9.5dB */
-+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 14  -9dB */
-+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 15  -8.5dB */
-+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 16  -8dB */
-+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 17  -7.5dB */
-+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 18  -7dB */
-+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 19  -6.5dB */
-+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}      /* 20  -6dB */
-+};
-+
-+
-+u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
-+	{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 0  -16dB */
-+	{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 1  -15.5dB */
-+	{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 2  -15dB */
-+	{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 3  -14.5dB */
-+	{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 4  -14dB */
-+	{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 5  -13.5dB */
-+	{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 6  -13dB */
-+	{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 7  -12.5dB */
-+	{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 8  -12dB */
-+	{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 9  -11.5dB */
-+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 10  -11dB */
-+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 11  -10.5dB */
-+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 12  -10dB */
-+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 13  -9.5dB */
-+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 14  -9dB */
-+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 15  -8.5dB */
-+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 16  -8dB */
-+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 17  -7.5dB */
-+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 18  -7dB */
-+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},        /* 19  -6.5dB */
-+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}      /* 20  -6dB */
-+};
-+
-+
-+u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
-+	{0x44,	 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
-+	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
-+	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
-+	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	    /*-14.5dB*/
-+	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
-+	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
-+	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
-+	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
-+	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
-+	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
-+	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
-+	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
-+	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
-+	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
-+	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
-+	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
-+	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
-+	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
-+	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
-+	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
-+	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
-+};
-+
-+/* Winnita ADD 20171113 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
-+u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
-+	0x0CD,			 /*0 ,    -20dB*/
-+	0x0D9,
-+	0x0E6,
-+	0x0F3,
-+	0x102,
-+	0x111,
-+	0x121,
-+	0x132,
-+	0x144,
-+	0x158,
-+	0x16C,
-+	0x182,
-+	0x198,
-+	0x1B1,
-+	0x1CA,
-+	0x1E5,
-+	0x202,
-+	0x221,
-+	0x241,
-+	0x263,		/*19*/
-+	0x287,		/*20*/
-+	0x2AE,		/*21*/
-+	0x2D6,		/*22*/
-+	0x301,		/*23*/
-+	0x32F,		/*24*/
-+	0x35F,		/*25*/
-+	0x392,		/*26*/
-+	0x3C9,		/*27*/
-+	0x402,		/*28*/
-+	0x43F,		/*29*/
-+	0x47F,		/*30*/
-+	0x4C3,		/*31*/
-+	0x50C,		/*32*/
-+	0x558,		/*33*/
-+	0x5A9,		/*34*/
-+	0x5FF,		/*35*/
-+	0x65A,		/*36*/
-+	0x6BA,
-+	0x720,
-+	0x78C,
-+	0x7FF,
-+};
-+
-+
-+#if 0
-+u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = {
-+	/* Index0   6  dB */ 0x7fc001ff,
-+	/* Index1   5.7dB */ 0x7b4001ed,
-+	/* Index2   5.4dB */ 0x774001dd,
-+	/* Index3   5.1dB */ 0x734001cd,
-+	/* Index4   4.8dB */ 0x6f4001bd,
-+	/* Index5   4.5dB */ 0x6b8001ae,
-+	/* Index6   4.2dB */ 0x67c0019f,
-+	/* Index7   3.9dB */ 0x64400191,
-+	/* Index8   3.6dB */ 0x60c00183,
-+	/* Index9   3.3dB */ 0x5d800176,
-+	/* Index10  3  dB */ 0x5a80016a,
-+	/* Index11  2.7dB */ 0x5740015d,
-+	/* Index12  2.4dB */ 0x54400151,
-+	/* Index13  2.1dB */ 0x51800146,
-+	/* Index14  1.8dB */ 0x4ec0013b,
-+	/* Index15  1.5dB */ 0x4c000130,
-+	/* Index16  1.2dB */ 0x49800126,
-+	/* Index17  0.9dB */ 0x4700011c,
-+	/* Index18  0.6dB */ 0x44800112,
-+	/* Index19  0.3dB */ 0x42000108,
-+	/* Index20  0  dB */ 0x40000100, /* 20 This is OFDM base index */
-+	/* Index21 -0.3dB */ 0x3dc000f7,
-+	/* Index22 -0.6dB */ 0x3bc000ef,
-+	/* Index23 -0.9dB */ 0x39c000e7,
-+	/* Index24 -1.2dB */ 0x37c000df,
-+	/* Index25 -1.5dB */ 0x35c000d7,
-+	/* Index26 -1.8dB */ 0x340000d0,
-+	/* Index27 -2.1dB */ 0x324000c9,
-+	/* Index28 -2.4dB */ 0x308000c2,
-+	/* Index29 -2.7dB */ 0x2f0000bc,
-+	/* Index30 -3  dB */ 0x2d4000b5,
-+	/* Index31 -3.3dB */ 0x2bc000af,
-+	/* Index32 -3.6dB */ 0x2a4000a9,
-+	/* Index33 -3.9dB */ 0x28c000a3,
-+	/* Index34 -4.2dB */ 0x2780009e,
-+	/* Index35 -4.5dB */ 0x26000098,
-+	/* Index36 -4.8dB */ 0x24c00093,
-+	/* Index37 -5.1dB */ 0x2380008e,
-+	/* Index38 -5.4dB */ 0x22400089,
-+	/* Index39 -5.7dB */ 0x21400085,
-+	/* Index40 -6  dB */ 0x20000080,
-+	/* Index41 -6.3dB */ 0x1f00007c,
-+	/* Index42 -6.6dB */ 0x1e000078,
-+	/* Index43 -6.9dB */ 0x1d000074,
-+	/* Index44 -7.2dB */ 0x1c000070,
-+	/* Index45 -7.5dB */ 0x1b00006c,
-+	/* Index46 -7.8dB */ 0x1a000068,
-+	/* Index47 -8.1dB */ 0x19400065,
-+	/* Index48 -8.4dB */ 0x18400061,
-+	/* Index49 -8.7dB */ 0x1780005e,
-+	/* Index50 -9  dB */ 0x16c0005b,
-+	/* Index51 -9.3dB */ 0x16000058,
-+	/* Index52 -9.6dB */ 0x15400055,
-+	/* Index53 -9.9dB */ 0x14800052
-+};
-+u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = {
-+	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04},
-+	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04},
-+	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04},
-+	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04},
-+	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03},
-+	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03},
-+	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03},
-+	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03},
-+	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03},
-+	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03},
-+	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03},
-+	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03},
-+	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03},
-+	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03},
-+	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02},
-+	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02},
-+	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02},
-+	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02},
-+	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02},
-+	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02},
-+	/* Index20  -6.0dB */    {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */
-+	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02},
-+	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02},
-+	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02},
-+	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02},
-+	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02},
-+	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02},
-+	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02},
-+	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02},
-+	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01},
-+	/* Index30  -9.0dB */    {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */
-+	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01},
-+	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01},
-+	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01},
-+	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01},
-+	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01},
-+	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01},
-+	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01},
-+	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
-+	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
-+	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
-+	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
-+	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
-+	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01},
-+	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
-+	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
-+	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
-+	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01},
-+	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
-+	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
-+	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
-+	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
-+	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
-+	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
-+};
-+u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = {
-+	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00},
-+	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00},
-+	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00},
-+	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00},
-+	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00},
-+	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00},
-+	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00},
-+	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00},
-+	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00},
-+	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00},
-+	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00},
-+	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00},
-+	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00},
-+	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00},
-+	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00},
-+	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00},
-+	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00},
-+	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00},
-+	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00},
-+	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00},
-+	/* Index20  -6  dB */     {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00},
-+	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00},
-+	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00},
-+	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00},
-+	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00},
-+	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00},
-+	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00},
-+	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00},
-+	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
-+	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
-+	/* Index30  -9  dB */    {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00},
-+	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
-+	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
-+	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00},
-+	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00},
-+	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00},
-+	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00},
-+	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00},
-+	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
-+	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
-+	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
-+	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
-+	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
-+	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00},
-+	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
-+	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
-+	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00},
-+	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
-+	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
-+	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
-+	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
-+	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
-+	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
-+	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00}
-+};
-+#endif
-+#endif
-+
-+
-+u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3
-+	, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9
-+							      };
-+u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4
-+	, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11
-+							      };
-+
-+
-+#ifdef CONFIG_WLAN_HAL_8192EE
-+u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = {
-+	/* Index0   6  dB */ 0x7fc001ff,
-+	/* Index1   5.7dB */ 0x7b4001ed,
-+	/* Index2   5.4dB */ 0x774001dd,
-+	/* Index3   5.1dB */ 0x734001cd,
-+	/* Index4   4.8dB */ 0x6f4001bd,
-+	/* Index5   4.5dB */ 0x6b8001ae,
-+	/* Index6   4.2dB */ 0x67c0019f,
-+	/* Index7   3.9dB */ 0x64400191,
-+	/* Index8   3.6dB */ 0x60c00183,
-+	/* Index9   3.3dB */ 0x5d800176,
-+	/* Index10  3  dB */ 0x5a80016a,
-+	/* Index11  2.7dB */ 0x5740015d,
-+	/* Index12  2.4dB */ 0x54400151,
-+	/* Index13  2.1dB */ 0x51800146,
-+	/* Index14  1.8dB */ 0x4ec0013b,
-+	/* Index15  1.5dB */ 0x4c000130,
-+	/* Index16  1.2dB */ 0x49800126,
-+	/* Index17  0.9dB */ 0x4700011c,
-+	/* Index18  0.6dB */ 0x44800112,
-+	/* Index19  0.3dB */ 0x42000108,
-+	/* Index20  0  dB */ 0x40000100, /* 20 This is OFDM base index */
-+	/* Index21 -0.3dB */ 0x3dc000f7,
-+	/* Index22 -0.6dB */ 0x3bc000ef,
-+	/* Index23 -0.9dB */ 0x39c000e7,
-+	/* Index24 -1.2dB */ 0x37c000df,
-+	/* Index25 -1.5dB */ 0x35c000d7,
-+	/* Index26 -1.8dB */ 0x340000d0,
-+	/* Index27 -2.1dB */ 0x324000c9,
-+	/* Index28 -2.4dB */ 0x308000c2,
-+	/* Index29 -2.7dB */ 0x2f0000bc,
-+	/* Index30 -3  dB */ 0x2d4000b5,
-+	/* Index31 -3.3dB */ 0x2bc000af,
-+	/* Index32 -3.6dB */ 0x2a4000a9,
-+	/* Index33 -3.9dB */ 0x28c000a3,
-+	/* Index34 -4.2dB */ 0x2780009e,
-+	/* Index35 -4.5dB */ 0x26000098,
-+	/* Index36 -4.8dB */ 0x24c00093,
-+	/* Index37 -5.1dB */ 0x2380008e,
-+	/* Index38 -5.4dB */ 0x22400089,
-+	/* Index39 -5.7dB */ 0x21400085,
-+	/* Index40 -6  dB */ 0x20000080,
-+	/* Index41 -6.3dB */ 0x1f00007c,
-+	/* Index42 -6.6dB */ 0x1e000078,
-+	/* Index43 -6.9dB */ 0x1d000074,
-+	/* Index44 -7.2dB */ 0x1c000070,
-+	/* Index45 -7.5dB */ 0x1b00006c,
-+	/* Index46 -7.8dB */ 0x1a000068,
-+	/* Index47 -8.1dB */ 0x19400065,
-+	/* Index48 -8.4dB */ 0x18400061,
-+	/* Index49 -8.7dB */ 0x1780005e,
-+	/* Index50 -9  dB */ 0x16c0005b,
-+	/* Index51 -9.3dB */ 0x16000058,
-+	/* Index52 -9.6dB */ 0x15400055,
-+	/* Index53 -9.9dB */ 0x14800052
-+};
-+u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = {
-+	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04},
-+	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04},
-+	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04},
-+	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04},
-+	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03},
-+	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03},
-+	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03},
-+	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03},
-+	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03},
-+	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03},
-+	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03},
-+	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03},
-+	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03},
-+	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03},
-+	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02},
-+	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02},
-+	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02},
-+	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02},
-+	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02},
-+	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02},
-+	/* Index20  -6.0dB */    {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */
-+	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02},
-+	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02},
-+	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02},
-+	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02},
-+	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02},
-+	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02},
-+	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02},
-+	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02},
-+	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01},
-+	/* Index30  -9.0dB */    {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */
-+	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01},
-+	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01},
-+	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01},
-+	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01},
-+	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01},
-+	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01},
-+	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01},
-+	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
-+	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
-+	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
-+	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
-+	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
-+	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01},
-+	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
-+	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
-+	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
-+	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01},
-+	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
-+	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
-+	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
-+	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
-+	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
-+	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
-+};
-+u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = {
-+	/* Index0    0  dB */    {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00},
-+	/* Index1   -0.3dB */    {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00},
-+	/* Index2   -0.6dB */    {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00},
-+	/* Index3   -0.9dB */    {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00},
-+	/* Index4   -1.2dB */    {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00},
-+	/* Index5   -1.5dB */    {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00},
-+	/* Index6   -1.8dB */    {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00},
-+	/* Index7   -2.1dB */    {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00},
-+	/* Index8   -2.4dB */    {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00},
-+	/* Index9   -2.7dB */    {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00},
-+	/* Index10  -3  dB */    {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00},
-+	/* Index11  -3.3dB */    {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00},
-+	/* Index12  -3.6dB */    {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00},
-+	/* Index13  -3.9dB */    {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00},
-+	/* Index14  -4.2dB */    {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00},
-+	/* Index15  -4.5dB */    {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00},
-+	/* Index16  -4.8dB */    {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00},
-+	/* Index17  -5.1dB */    {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00},
-+	/* Index18  -5.4dB */    {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00},
-+	/* Index19  -5.7dB */    {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00},
-+	/* Index20  -6  dB */     {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00},
-+	/* Index21  -6.3dB */    {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00},
-+	/* Index22  -6.6dB */    {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00},
-+	/* Index23  -6.9dB */    {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00},
-+	/* Index24  -7.2dB */    {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00},
-+	/* Index25  -7.5dB */    {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00},
-+	/* Index26  -7.8dB */    {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00},
-+	/* Index27  -8.1dB */    {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00},
-+	/* Index28  -8.4dB */    {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
-+	/* Index29  -8.7dB */    {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
-+	/* Index30  -9  dB */    {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00},
-+	/* Index31  -9.3dB */    {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
-+	/* Index32  -9.6dB */    {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
-+	/* Index33  -9.9dB */    {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00},
-+	/* Index34 -10.2dB */    {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00},
-+	/* Index35 -10.5dB */    {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00},
-+	/* Index36 -10.8dB */    {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00},
-+	/* Index37 -11.1dB */    {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00},
-+	/* Index38 -11.4dB */    {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
-+	/* Index39 -11.7dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
-+	/* Index40 -12  dB */    {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
-+	/* Index41 -12.3dB */    {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
-+	/* Index42 -12.6dB */    {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
-+	/* Index43 -12.9dB */    {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00},
-+	/* Index44 -13.2dB */    {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
-+	/* Index45 -13.5dB */    {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
-+	/* Index46 -13.8dB */    {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00},
-+	/* Index47 -14.1dB */    {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
-+	/* Index48 -14.4dB */    {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
-+	/* Index49 -14.7dB */    {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
-+	/* Index50 -15  dB */    {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
-+	/* Index51 -15.3dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
-+	/* Index52 -15.6dB */    {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
-+	/* Index53 -15.9dB */    {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00}
-+};
-+#endif
-+
-+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
-+	RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT == 1)
-+u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
-+	0x081, /* 0,  -12.0dB */
-+	0x088, /* 1,  -11.5dB */
-+	0x090, /* 2,  -11.0dB */
-+	0x099, /* 3,  -10.5dB */
-+	0x0A2, /* 4,  -10.0dB */
-+	0x0AC, /* 5,  -9.5dB */
-+	0x0B6, /* 6,  -9.0dB */
-+	0x0C0, /* 7,  -8.5dB */
-+	0x0CC, /* 8,  -8.0dB */
-+	0x0D8, /* 9,  -7.5dB */
-+	0x0E5, /* 10, -7.0dB */
-+	0x0F2, /* 11, -6.5dB */
-+	0x101, /* 12, -6.0dB */
-+	0x110, /* 13, -5.5dB */
-+	0x120, /* 14, -5.0dB */
-+	0x131, /* 15, -4.5dB */
-+	0x143, /* 16, -4.0dB */
-+	0x156, /* 17, -3.5dB */
-+	0x16A, /* 18, -3.0dB */
-+	0x180, /* 19, -2.5dB */
-+	0x197, /* 20, -2.0dB */
-+	0x1AF, /* 21, -1.5dB */
-+	0x1C8, /* 22, -1.0dB */
-+	0x1E3, /* 23, -0.5dB */
-+	0x200, /* 24, +0  dB */
-+	0x21E, /* 25, +0.5dB */
-+	0x23E, /* 26, +1.0dB */
-+	0x261, /* 27, +1.5dB */
-+	0x285, /* 28, +2.0dB */
-+	0x2AB, /* 29, +2.5dB */
-+	0x2D3, /* 30, +3.0dB */
-+	0x2FE, /* 31, +3.5dB */
-+	0x32B, /* 32, +4.0dB */
-+	0x35C, /* 33, +4.5dB */
-+	0x38E, /* 34, +5.0dB */
-+	0x3C4, /* 35, +5.5dB */
-+	0x3FE  /* 36, +6.0dB */
-+};
-+#elif(ODM_IC_11AC_SERIES_SUPPORT)
-+u32 ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812] = {
-+	0x3FE, /* 0,  (6dB) */
-+	0x3C4, /* 1,  (5.5dB) */
-+	0x38E, /* 2,  (5dB) */
-+	0x35C, /* 3,  (4.5dB) */
-+	0x32B, /* 4,  (4dB) */
-+	0x2FE, /* 5,  (3.5dB) */
-+	0x2D3, /* 6,  (3dB) */
-+	0x2AB, /* 7,  (2.5dB) */
-+	0x285, /* 8,  (2dB) */
-+	0x261, /* 9,  (1.5dB */
-+	0x23E, /* 10, (1dB) */
-+	0x21E, /* 11, (0.5dB) */
-+	0x200, /* 12, (0dB)		8814 int PA 2G default */
-+	0x1E3, /* 13, (-0.5dB) */
-+	0x1C8, /* 14, (-1dB) */
-+	0x1AF, /* 15, (-1.5dB) */
-+	0x197, /* 16, (-2dB) */
-+	0x180, /* 17, (-2.5dB) */
-+	0x16A, /* 18, (-3dB)		8812 / 8814 int PA 5G / 8814 ext PA 2G5G default */
-+	0x156, /* 19, (-3.5dB) */
-+	0x143, /* 20, (-4dB)		8812 HP default */
-+	0x131, /* 21, (-4.5dB) */
-+	0x120, /* 22, (-5dB) */
-+	0x110, /* 23, (-5.5dB) */
-+	0x101, /* 24, (-6dB) */
-+	0x0F2, /* 25, (-6.5dB) */
-+	0x0E5, /* 26, (-7dB) */
-+	0x0D8, /* 27, (-7.5dB) */
-+	0x0CC, /* 28, (-8dB) */
-+	0x0C0, /* 29, (-8.5dB) */
-+	0x0B6, /* 30, (-9dB) */
-+	0x0AC, /* 31, (-9.5dB) */
-+	0x0A2, /* 32, (-10dB) */
-+	0x099, /* 33, (-10.5dB) */
-+	0x090, /* 34, (-11dB) */
-+	0x088, /* 35, (-11.5dB) */
-+	0x081, /* 36, (-12dB) */
-+	0x079, /* 37, (-12.5dB) */
-+	0x072, /* 38, (-13dB) */
-+	0x06c, /* 39, (-13.5dB) */
-+	0x066, /* 40, (-14dB) */
-+	0x060, /* 41, (-14.5dB) */
-+	0x05B  /* 42, (-15dB) */
-+};
-+#endif
-+
-+u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
-+	0x0CD,
-+	0x0D9,
-+	0x0E6,
-+	0x0F3,
-+	0x102,
-+	0x111,
-+	0x121,
-+	0x132,
-+	0x144,
-+	0x158,
-+	0x16C,
-+	0x182,
-+	0x198,
-+	0x1B1,
-+	0x1CA,
-+	0x1E5,
-+	0x202,
-+	0x221,
-+	0x241,
-+	0x263,
-+	0x287,
-+	0x2AE,
-+	0x2D6,
-+	0x301,
-+	0x32F,
-+	0x35F,
-+	0x392,
-+	0x3C9,
-+	0x402,
-+	0x43F,
-+	0x47F,
-+	0x4C3,
-+	0x50C,
-+	0x558,
-+	0x5A9,
-+	0x5FF,
-+	0x65A,
-+	0x6BA,
-+	0x720,
-+	0x78C,
-+	0x7FF,
-+};
-+/* JJ ADD 20161014 */
-+u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
-+	0x0CD,
-+	0x0D9,
-+	0x0E6,
-+	0x0F3,
-+	0x102,
-+	0x111,
-+	0x121,
-+	0x132,
-+	0x144,
-+	0x158,
-+	0x16C,
-+	0x182,
-+	0x198,
-+	0x1B1,
-+	0x1CA,
-+	0x1E5,
-+	0x202,
-+	0x221,
-+	0x241,
-+	0x263,
-+	0x287,
-+	0x2AE,
-+	0x2D6,
-+	0x301,
-+	0x32F,
-+	0x35F,
-+	0x392,
-+	0x3C9,
-+	0x402,
-+	0x43F,
-+	0x47F,
-+	0x4C3,
-+	0x50C,
-+	0x558,
-+	0x5A9,
-+	0x5FF,
-+	0x65A,
-+	0x6BA,
-+	0x720,
-+	0x78C,
-+	0x7FF,
-+};
-+
-+
-+/* #endif */
-+/* 3============================================================
-+ * 3 Tx Power Tracking
-+ * 3============================================================ */
-+
-+void
-+odm_txpowertracking_init(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8814B | ODM_IC_11N_SERIES)))
-+		return;
-+#endif
-+
-+	odm_txpowertracking_thermal_meter_init(dm);
-+}
-+
-+
-+u8
-+get_swing_index(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	u8			i = 0, bb_swing_mask = 0;
-+	u32			bb_swing = 0;
-+	u32			swing_table_size = 0;
-+	u32			*swing_table = 0;
-+	struct rtl8192cd_priv	*priv = dm->priv;
-+
-+#if (RTL8197F_SUPPORT == 1)
-+	if (GET_CHIP_VER(priv) == VERSION_8197F) {
-+		bb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);
-+		swing_table = ofdm_swing_table_new;
-+		swing_table_size = OFDM_TABLE_SIZE_92D;
-+		bb_swing_mask = 22;
-+	}
-+#endif
-+
-+#if (RTL8192F_SUPPORT == 1)
-+	if (GET_CHIP_VER(priv) == VERSION_8192F) {
-+		bb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);
-+		swing_table = ofdm_swing_table_new;
-+		swing_table_size = OFDM_TABLE_SIZE_92D;
-+		bb_swing_mask = 22;
-+	}
-+#endif
-+
-+#if (RTL8822B_SUPPORT == 1)
-+	if (GET_CHIP_VER(priv) == VERSION_8822B) {
-+		bb_swing = phy_query_bb_reg(priv, REG_A_TX_SCALE_JAGUAR, 0xFFE00000);
-+		swing_table = tx_scaling_table_jaguar;
-+		swing_table_size = TXSCALE_TABLE_SIZE;
-+		bb_swing_mask = 0;
-+	}
-+#endif
-+
-+	for (i = 0; i < swing_table_size - 1; i++) {
-+		u32 table_value = swing_table[i] >> bb_swing_mask;
-+
-+		if (bb_swing == table_value)
-+			break;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "bb_swing=0x%x bbswing_index=%d\n", bb_swing, i);
-+
-+
-+	return i;
-+}
-+
-+s8
-+get_txagc_default_index(
-+	void *dm_void
-+)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	s8 tmp;
-+
-+#if RTL8814B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		tmp = (s8)(odm_get_bb_reg(dm, R_0x18a0, 0x7f) & 0xff);
-+		if (tmp & BIT(6))
-+			tmp = tmp | 0x80;
-+		return tmp;
-+	} else
-+		return 0;
-+#endif
-+}
-+
-+void
-+odm_txpowertracking_thermal_meter_init(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
-+	struct rtl8192cd_priv		*priv = dm->priv;
-+	u8 p;
-+	u8 default_swing_index;
-+	u8 i;
-+#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1)
-+	if ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B) ||(GET_CHIP_VER(priv) == VERSION_8192F))
-+		default_swing_index = get_swing_index(dm);
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void		*adapter = dm->adapter;
-+	PMGNT_INFO	mgnt_info = &adapter->MgntInfo;
-+	HAL_DATA_TYPE		*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+
-+	mgnt_info->is_txpowertracking = true;
-+	hal_data->tx_powercount       = 0;
-+	hal_data->is_txpowertracking_init = false;
-+
-+	if (*(dm->mp_mode) == false)
-+		hal_data->txpowertrack_control = true;
-+	RF_DBG(dm, COMP_POWER_TRACKING, "mgnt_info->is_txpowertracking = %d\n", mgnt_info->is_txpowertracking);
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+#ifdef CONFIG_RTL8188E
-+	{
-+		dm->rf_calibrate_info.is_txpowertracking = true;
-+		dm->rf_calibrate_info.tx_powercount = 0;
-+		dm->rf_calibrate_info.is_txpowertracking_init = false;
-+
-+		if (*(dm->mp_mode) == false)
-+			dm->rf_calibrate_info.txpowertrack_control = true;
-+
-+		MSG_8192C("dm txpowertrack_control = %d\n", dm->rf_calibrate_info.txpowertrack_control);
-+	}
-+#else
-+	{
-+		void		*adapter = dm->adapter;
-+		HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+		struct dm_priv	*pdmpriv = &hal_data->dmpriv;
-+		
-+		pdmpriv->is_txpowertracking = true;
-+		pdmpriv->tx_powercount = 0;
-+		pdmpriv->is_txpowertracking_init = false;
-+
-+		if (*(dm->mp_mode) == false)		/* for mp driver, turn off txpwrtracking as default */
-+			pdmpriv->txpowertrack_control = true;
-+
-+		MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control);
-+
-+	}
-+#endif/* endif (CONFIG_RTL8188E==1) */
-+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#ifdef RTL8188E_SUPPORT
-+	{
-+		dm->rf_calibrate_info.is_txpowertracking = true;
-+		dm->rf_calibrate_info.tx_powercount = 0;
-+		dm->rf_calibrate_info.is_txpowertracking_init = false;
-+		dm->rf_calibrate_info.txpowertrack_control = true;
-+		dm->rf_calibrate_info.tm_trigger = 0;
-+	}
-+#endif
-+#endif
-+
-+	dm->rf_calibrate_info.txpowertrack_control = true;
-+	dm->rf_calibrate_info.delta_power_index = 0;
-+	dm->rf_calibrate_info.delta_power_index_last = 0;
-+	dm->rf_calibrate_info.power_index_offset = 0;
-+	dm->rf_calibrate_info.thermal_value = 0;
-+	cali_info->default_ofdm_index = 28;
-+
-+#if (RTL8197F_SUPPORT == 1)
-+	if (GET_CHIP_VER(priv) == VERSION_8197F) {
-+		cali_info->default_ofdm_index = (default_swing_index >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : default_swing_index;
-+		cali_info->default_cck_index = 28;
-+	}
-+#endif
-+
-+#if (RTL8192F_SUPPORT == 1)
-+	if (GET_CHIP_VER(priv) == VERSION_8192F) {
-+		cali_info->default_ofdm_index = (default_swing_index >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : default_swing_index;
-+		cali_info->default_cck_index = 28;
-+	}
-+#endif
-+
-+#if (RTL8822B_SUPPORT == 1)
-+	if (GET_CHIP_VER(priv) == VERSION_8822B) {
-+		cali_info->default_ofdm_index = (default_swing_index >= (TXSCALE_TABLE_SIZE - 1)) ? 24 : default_swing_index;
-+		cali_info->default_cck_index = 20;
-+	}
-+#endif
-+
-+
-+#if RTL8188E_SUPPORT
-+	if (GET_CHIP_VER(priv) == VERSION_8188E) {
-+		cali_info->default_cck_index = 20;	/* -6 dB */
-+	}
-+#endif
-+
-+#if RTL8192E_SUPPORT
-+	if (GET_CHIP_VER(priv) == VERSION_8192E) {
-+		cali_info->default_cck_index = 8;	/* -12 dB */
-+	}
-+#endif
-+
-+#if RTL8814B_SUPPORT
-+	if (GET_CHIP_VER(priv) == VERSION_8814B) {
-+		cali_info->default_txagc_index = get_txagc_default_index(dm);
-+
-+		for (i = 0; i < MAX_PATH_NUM_8814B; i++)
-+			tssi->tssi_trk_txagc_offset[i] =
-+				cali_info->default_txagc_index;
-+	}
-+#endif
-+
-+	cali_info->bb_swing_idx_ofdm_base = cali_info->default_ofdm_index;
-+	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
-+	dm->rf_calibrate_info.CCK_index = cali_info->default_cck_index;
-+
-+	for (p = 0; p < MAX_RF_PATH; p++) {
-+		dm->rf_calibrate_info.OFDM_index[p] = cali_info->default_ofdm_index;
-+		cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
-+		cali_info->kfree_offset[p] = 0;	/* for 8814 kfree*/
-+	}
-+	cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "cali_info->default_ofdm_index=%d cali_info->default_cck_index=%d\n", cali_info->default_ofdm_index, cali_info->default_cck_index);
-+
-+	cali_info->tm_trigger = 0;
-+}
-+
-+
-+void
-+odm_txpowertracking_check(
-+	void		*dm_void
-+)
-+{
-+	/*  */
-+	/* For AP/ADSL use struct rtl8192cd_priv* */
-+	/* For CE/NIC use struct void* */
-+	/*  */
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_				*rf = &(dm->rf_table);
-+
-+	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
-+		return;
-+
-+	/*  */
-+	/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
-+	/* at the same time. In the stage2/3, we need to prive universal interface and merge all */
-+	/* HW dynamic mechanism. */
-+	/*  */
-+	switch	(dm->support_platform) {
-+	case	ODM_WIN:
-+		odm_txpowertracking_check_mp(dm);
-+		break;
-+
-+	case	ODM_CE:
-+		odm_txpowertracking_check_ce(dm);
-+		break;
-+
-+	case	ODM_AP:
-+		odm_txpowertracking_check_ap(dm);
-+		break;
-+	}
-+
-+}
-+
-+void
-+odm_txpowertracking_check_ce(
-+	void		*dm_void
-+)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	void	*adapter = dm->adapter;
-+	struct _hal_rf_				*rf = &(dm->rf_table);
-+
-+#if (RTL8188E_SUPPORT == 1)
-+
-+	/* if(!mgnt_info->is_txpowertracking || (!pdmpriv->txpowertrack_control && pdmpriv->is_ap_kdone)) */
-+
-+	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
-+		return;
-+
-+	if (!dm->rf_calibrate_info.tm_trigger) {	/* at least delay 1 sec */
-+		/* hal_data->TxPowerCheckCnt++;	 */ /* cosa add for debug */
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
-+		/* DBG_8192C("Trigger 92C Thermal Meter!!\n"); */
-+
-+		dm->rf_calibrate_info.tm_trigger = 1;
-+		return;
-+
-+	} else {
-+		/* DBG_8192C("Schedule TxPowerTracking direct call!!\n"); */
-+		odm_txpowertracking_callback_thermal_meter_8188e(adapter);
-+		dm->rf_calibrate_info.tm_trigger = 0;
-+	}
-+#endif
-+
-+#endif
-+}
-+
-+void
-+odm_txpowertracking_check_mp(
-+	void		*dm_void
-+)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	void	*adapter = dm->adapter;
-+
-+	if (odm_check_power_status(adapter) == false)
-+		return;
-+
-+	if (!adapter->is_slave_of_dmsp || adapter->dual_mac_smart_concurrent == false)
-+		odm_txpowertracking_thermal_meter_check(adapter);
-+#endif
-+
-+}
-+
-+
-+void
-+odm_txpowertracking_check_ap(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
-+
-+#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) || (RTL8198F_SUPPORT == 1) || (RTL8814B_SUPPORT == 1) || (RTL8812F_SUPPORT == 1) || (RTL8197G_SUPPORT == 1))
-+	if (!dm->rf_calibrate_info.tm_trigger) {
-+		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8192F | ODM_RTL8198F)) {
-+			odm_set_rf_reg(dm, RF_PATH_A, 0x42, (BIT(17) | BIT(16)), 0x3);
-+		} else if (dm->support_ic_type & ODM_RTL8812F) {
-+			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
-+			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);
-+			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
-+			
-+			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
-+			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);
-+			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
-+		} else if (dm->support_ic_type & ODM_RTL8814B) {
-+			odm_set_rf_reg(dm, RF_PATH_A, 0x42, BIT(17), 0x1);
-+			odm_set_rf_reg(dm, RF_PATH_B, 0x42, BIT(17), 0x1);
-+			odm_set_rf_reg(dm, RF_PATH_C, 0x42, BIT(17), 0x1);
-+			odm_set_rf_reg(dm, RF_PATH_D, 0x42, BIT(17), 0x1);
-+		} else if (dm->support_ic_type & ODM_RTL8197G) {
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, BIT(17), 0x1);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, BIT(17), 0x0);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, BIT(17), 0x1);
-+
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x42, BIT(17), 0x1);
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x42, BIT(17), 0x0);
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x42, BIT(17), 0x1);
-+		}
-+
-+		if (dm->support_ic_type & ODM_RTL8814B) {
-+			ODM_delay_us(300);
-+			odm_txpowertracking_callback_thermal_meter(dm);
-+			tssi->thermal_trigger = 1;
-+		}
-+
-+		dm->rf_calibrate_info.tm_trigger = 1;
-+	} else {
-+		odm_txpowertracking_callback_thermal_meter(dm);
-+		if (dm->support_ic_type & ODM_RTL8814B)
-+			tssi->thermal_trigger = 0;
-+		dm->rf_calibrate_info.tm_trigger = 0;
-+	}
-+#endif
-+
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_ap.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_ap.h
-new file mode 100644
-index 000000000000..098e2845067c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_ap.h
-@@ -0,0 +1,407 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_POWERTRACKING_H__
-+#define __HALRF_POWERTRACKING_H__
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	#ifdef RTK_AC_SUPPORT
-+		#define ODM_IC_11AC_SERIES_SUPPORT		1
-+	#else
-+		#define ODM_IC_11AC_SERIES_SUPPORT		0
-+	#endif
-+#else
-+	#define ODM_IC_11AC_SERIES_SUPPORT		1
-+#endif
-+
-+#define		DPK_DELTA_MAPPING_NUM	13
-+#define		index_mapping_HP_NUM	15
-+#define		DELTA_SWINGIDX_SIZE     30
-+#define		DELTA_SWINTSSI_SIZE     61
-+#define		BAND_NUM				3
-+#define		MAX_RF_PATH	4
-+#define		TXSCALE_TABLE_SIZE		37
-+#define		CCK_TABLE_SIZE_8723D		41
-+/* JJ ADD 20161014 */
-+#define		CCK_TABLE_SIZE_8710B		41
-+
-+#define IQK_MAC_REG_NUM		4
-+#define IQK_ADDA_REG_NUM		16
-+#define IQK_BB_REG_NUM_MAX	10
-+
-+#define IQK_BB_REG_NUM		9
-+
-+#define AVG_THERMAL_NUM		8
-+#define AVG_THERMAL_NUM_DPK		8
-+#define THERMAL_DPK_AVG_NUM		4
-+
-+#define iqk_matrix_reg_num	8
-+/* #define IQK_MATRIX_SETTINGS_NUM	1+24+21 */
-+#define IQK_MATRIX_SETTINGS_NUM	(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
-+
-+#if !defined(_OUTSRC_COEXIST)
-+	#define	OFDM_TABLE_SIZE_92D	43
-+	#define	OFDM_TABLE_SIZE	37
-+	#define	CCK_TABLE_SIZE		33
-+	#define	CCK_TABLE_SIZE_88F	21
-+	#define	CCK_TABLE_SIZE_8192F	41
-+
-+
-+
-+	/* #define	OFDM_TABLE_SIZE_92E	54 */
-+	/* #define	CCK_TABLE_SIZE_92E	54 */
-+	extern	u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D];
-+	extern	u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
-+	extern	u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
-+
-+
-+	extern	u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D];
-+	extern	u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
-+	extern	u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
-+	extern	u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
-+	extern	u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
-+	extern	u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
-+	extern	u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
-+
-+#endif
-+
-+#define	ODM_OFDM_TABLE_SIZE	37
-+#define	ODM_CCK_TABLE_SIZE		33
-+#define TXPWR_TRACK_TABLE_SIZE 30
-+/* <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
-+extern u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE];
-+extern u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE];
-+
-+static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};
-+static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};
-+
-+/* extern	u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
-+ * extern	u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
-+ * extern	u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; */
-+
-+#ifdef CONFIG_WLAN_HAL_8192EE
-+	#define	OFDM_TABLE_SIZE_92E	54
-+	#define	CCK_TABLE_SIZE_92E	54
-+	extern	u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
-+	extern	u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
-+	extern	u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8];
-+#endif
-+
-+#define	OFDM_TABLE_SIZE_8812	43
-+#define	AVG_THERMAL_NUM_8812	4
-+
-+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\
-+	RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT == 1)
-+	extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
-+	#elif(ODM_IC_11AC_SERIES_SUPPORT)
-+	extern unsigned int ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812];
-+#endif
-+
-+extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
-+/* JJ ADD 20161014 */
-+extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
-+
-+#define dm_check_txpowertracking	odm_txpowertracking_check
-+
-+struct iqk_matrix_regs_setting {
-+	boolean	is_iqk_done;
-+	s32		value[1][iqk_matrix_reg_num];
-+};
-+
-+struct dm_rf_calibration_struct {
-+	/* for tx power tracking */
-+
-+	u32	rega24; /* for TempCCK */
-+	s32	rege94;
-+	s32	rege9c;
-+	s32	regeb4;
-+	s32	regebc;
-+
-+	/* u8 is_txpowertracking; */
-+	u8	tx_powercount;
-+	boolean is_txpowertracking_init;
-+	boolean is_txpowertracking;
-+	u8  	txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
-+	u8	tm_trigger;
-+	u8  	internal_pa_5g[2];	/* pathA / pathB */
-+
-+	u8  	thermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
-+	u8	thermal_value;
-+	u8	thermal_value_path[MAX_RF_PATH];
-+	u8	thermal_value_lck;
-+	u8	thermal_value_iqk;
-+	s8  	thermal_value_delta; /* delta of thermal_value and efuse thermal */
-+	u8	thermal_value_avg[AVG_THERMAL_NUM];
-+	u8	thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];
-+	u8	thermal_value_avg_index;
-+	u8	thermal_value_avg_index_path[MAX_RF_PATH];
-+	s8	power_index_offset_path[MAX_RF_PATH];
-+
-+	u8	thermal_value_rx_gain;
-+	u8	thermal_value_crystal;
-+	u8	thermal_value_dpk_store;
-+	u8	thermal_value_dpk_track;
-+	boolean	txpowertracking_in_progress;
-+
-+
-+	boolean	is_reloadtxpowerindex;
-+	u8	is_rf_pi_enable;
-+	u32 	txpowertracking_callback_cnt; /* cosa add for debug */
-+
-+	u8	is_cck_in_ch14;
-+	u8	CCK_index;
-+	u8	OFDM_index[MAX_RF_PATH];
-+	s8	power_index_offset;
-+	s8	delta_power_index;
-+	s8	delta_power_index_path[MAX_RF_PATH];
-+	s8	delta_power_index_last;
-+	s8	delta_power_index_last_path[MAX_RF_PATH];
-+	boolean is_tx_power_changed;
-+
-+	struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
-+	u8	delta_lck;
-+	u8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	s8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
-+	s8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
-+
-+	u8			bb_swing_idx_ofdm[MAX_RF_PATH];
-+	u8			bb_swing_idx_ofdm_current;
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	u8			bb_swing_idx_ofdm_base[MAX_RF_PATH];
-+#else
-+	u8			bb_swing_idx_ofdm_base;
-+	u8			bb_swing_idx_ofdm_base_path[MAX_RF_PATH];
-+#endif
-+	boolean			bb_swing_flag_ofdm;
-+	u8			bb_swing_idx_cck;
-+	u8			bb_swing_idx_cck_current;
-+	u8			bb_swing_idx_cck_base;
-+	u8			default_ofdm_index;
-+	u8			default_cck_index;
-+	s8			default_txagc_index;
-+	boolean			bb_swing_flag_cck;
-+
-+	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
-+	s8			remnant_ofdm_swing_idx[MAX_RF_PATH];
-+	s8			absolute_cck_swing_idx[MAX_RF_PATH];
-+	s8			remnant_cck_swing_idx;
-+	s8			modify_tx_agc_value;       /*Remnat compensate value at tx_agc */
-+	boolean			modify_tx_agc_flag_path_a;
-+	boolean			modify_tx_agc_flag_path_b;
-+	boolean			modify_tx_agc_flag_path_c;
-+	boolean			modify_tx_agc_flag_path_d;
-+	boolean			modify_tx_agc_flag_path_a_cck;
-+	boolean			modify_tx_agc_flag_path_b_cck;
-+
-+	s8			kfree_offset[MAX_RF_PATH];
-+
-+	/* -------------------------------------------------------------------- */
-+
-+	/* for IQK */
-+	u32	regc04;
-+	u32	reg874;
-+	u32	regc08;
-+	u32	regb68;
-+	u32	regb6c;
-+	u32	reg870;
-+	u32	reg860;
-+	u32	reg864;
-+
-+	boolean	is_iqk_initialized;
-+	boolean is_lck_in_progress;
-+	boolean	is_antenna_detected;
-+	boolean	is_need_iqk;
-+	boolean	is_iqk_in_progress;
-+	boolean	is_iqk_pa_off;
-+	u8	delta_iqk;
-+	u32	ADDA_backup[IQK_ADDA_REG_NUM];
-+	u32	IQK_MAC_backup[IQK_MAC_REG_NUM];
-+	u32	IQK_BB_backup_recover[9];
-+	u32	IQK_BB_backup[IQK_BB_REG_NUM];
-+	u32	tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
-+	u32	rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
-+	u32	tx_iqc_8703b[3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
-+	u32	rx_iqc_8703b[2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
-+
-+	u64	iqk_start_time;
-+	u64	iqk_total_progressing_time;
-+	u64	iqk_progressing_time;
-+	u64	lck_progressing_time;
-+	u32  lok_result;
-+	u8	iqk_step;
-+	u8	kcount;
-+	u8	retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
-+	boolean	is_mp_mode;
-+
-+	/* for APK */
-+	u32 	ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
-+	u8	is_ap_kdone;
-+	u8	is_apk_thermal_meter_ignore;
-+	u8	is_dp_done;
-+#if 0 /*move below members to halrf_dpk.h*/
-+	u8	is_dp_path_aok;
-+	u8	is_dp_path_bok;
-+	u8	is_dp_path_cok;
-+	u8	is_dp_path_dok;
-+	u8 	dp_path_a_result[3];
-+	u8 	dp_path_b_result[3];
-+	u8 	dp_path_c_result[3];
-+	u8 	dp_path_d_result[3];
-+	boolean	is_dpk_enable;
-+	u32	txrate[11];
-+	u8 	pwsf_2g_a[3];
-+	u8 	pwsf_2g_b[3];
-+	u8 	pwsf_2g_c[3];
-+	u8 	pwsf_2g_d[3];
-+	u32	lut_2g_even_a[3][64];
-+	u32	lut_2g_odd_a[3][64];
-+	u32	lut_2g_even_b[3][64];
-+	u32	lut_2g_odd_b[3][64];
-+	u32	lut_2g_even_c[3][64];
-+	u32	lut_2g_odd_c[3][64];
-+	u32	lut_2g_even_d[3][64];
-+	u32	lut_2g_odd_d[3][64];
-+	u1Byte 	is_5g_pdk_a_ok;
-+	u1Byte 	is_5g_pdk_b_ok;
-+	u1Byte 	is_5g_pdk_c_ok;
-+	u1Byte 	is_5g_pdk_d_ok;
-+	u1Byte 	pwsf_5g_a[9];
-+	u1Byte 	pwsf_5g_b[9];
-+	u1Byte 	pwsf_5g_c[9];
-+	u1Byte 	pwsf_5g_d[9];
-+	u4Byte	lut_5g_even_a[9][16];
-+	u4Byte	lut_5g_odd_a[9][16];
-+	u4Byte	lut_5g_even_b[9][16];
-+	u4Byte	lut_5g_odd_b[9][16];
-+	u4Byte	lut_5g_even_c[9][16];
-+	u4Byte	lut_5g_odd_c[9][16];
-+	u4Byte	lut_5g_even_d[9][16];
-+	u4Byte	lut_5g_odd_d[9][16];
-+	u8	thermal_value_dpk;
-+	u8	thermal_value_dpk_avg[AVG_THERMAL_NUM_DPK];
-+	u8	thermal_value_dpk_avg_index;
-+#endif
-+	s8  modify_tx_agc_value_ofdm;
-+	s8  modify_tx_agc_value_cck;
-+
-+	/*Add by Yuchen for Kfree Phydm*/
-+	u8			reg_rf_kfree_enable;	/*for registry*/
-+	u8			rf_kfree_enable;		/*for efuse enable check*/
-+	u32	tx_lok[2];
-+};
-+
-+void
-+odm_txpowertracking_check_ap(
-+	void		*dm_void
-+);
-+
-+void
-+odm_txpowertracking_check(
-+	void		*dm_void
-+);
-+
-+
-+void
-+odm_txpowertracking_thermal_meter_init(
-+	void		*dm_void
-+);
-+
-+void
-+odm_txpowertracking_init(
-+	void		*dm_void
-+);
-+
-+void
-+odm_txpowertracking_check_mp(
-+	void		*dm_void
-+);
-+
-+
-+void
-+odm_txpowertracking_check_ce(
-+	void		*dm_void
-+);
-+
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+
-+void
-+odm_txpowertracking_callback_thermal_meter92c(
-+	void	*adapter
-+);
-+
-+void
-+odm_txpowertracking_callback_rx_gain_thermal_meter92d(
-+	void	*adapter
-+);
-+
-+void
-+odm_txpowertracking_callback_thermal_meter92d(
-+	void	*adapter
-+);
-+
-+void
-+odm_txpowertracking_direct_call92c(
-+	void		*adapter
-+);
-+
-+void
-+odm_txpowertracking_thermal_meter_check(
-+	void		*adapter
-+);
-+
-+#endif
-+
-+
-+
-+#endif	/*#ifndef __HALRF_POWER_TRACKING_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_ce.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_ce.c
-new file mode 100644
-index 000000000000..6607991766f3
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_ce.c
-@@ -0,0 +1,955 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@===========================================================
-+ * include files
-+ *============================================================
-+ */
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+/*@************************************************************
-+ * Global var
-+ * ************************************************************
-+ */
-+
-+u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
-+	0x7f8001fe, /* 0, +6.0dB */
-+	0x788001e2, /* 1, +5.5dB */
-+	0x71c001c7, /* 2, +5.0dB*/
-+	0x6b8001ae, /* 3, +4.5dB*/
-+	0x65400195, /* 4, +4.0dB*/
-+	0x5fc0017f, /* 5, +3.5dB*/
-+	0x5a400169, /* 6, +3.0dB*/
-+	0x55400155, /* 7, +2.5dB*/
-+	0x50800142, /* 8, +2.0dB*/
-+	0x4c000130, /* 9, +1.5dB*/
-+	0x47c0011f, /* 10, +1.0dB*/
-+	0x43c0010f, /* 11, +0.5dB*/
-+	0x40000100, /* 12, +0dB*/
-+	0x3c8000f2, /* 13, -0.5dB*/
-+	0x390000e4, /* 14, -1.0dB*/
-+	0x35c000d7, /* 15, -1.5dB*/
-+	0x32c000cb, /* 16, -2.0dB*/
-+	0x300000c0, /* 17, -2.5dB*/
-+	0x2d4000b5, /* 18, -3.0dB*/
-+	0x2ac000ab, /* 19, -3.5dB*/
-+	0x288000a2, /* 20, -4.0dB*/
-+	0x26000098, /* 21, -4.5dB*/
-+	0x24000090, /* 22, -5.0dB*/
-+	0x22000088, /* 23, -5.5dB*/
-+	0x20000080, /* 24, -6.0dB*/
-+	0x1e400079, /* 25, -6.5dB*/
-+	0x1c800072, /* 26, -7.0dB*/
-+	0x1b00006c, /* 27. -7.5dB*/
-+	0x19800066, /* 28, -8.0dB*/
-+	0x18000060, /* 29, -8.5dB*/
-+	0x16c0005b, /* 30, -9.0dB*/
-+	0x15800056, /* 31, -9.5dB*/
-+	0x14400051, /* 32, -10.0dB*/
-+	0x1300004c, /* 33, -10.5dB*/
-+	0x12000048, /* 34, -11.0dB*/
-+	0x11000044, /* 35, -11.5dB*/
-+	0x10000040, /* 36, -12.0dB*/
-+};
-+
-+u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
-+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
-+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
-+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
-+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
-+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
-+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
-+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
-+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
-+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
-+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
-+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
-+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
-+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0 default*/
-+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
-+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
-+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
-+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
-+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
-+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
-+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
-+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
-+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
-+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
-+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
-+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
-+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
-+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
-+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
-+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
-+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
-+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
-+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
-+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
-+};
-+
-+u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
-+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
-+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
-+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
-+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
-+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
-+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
-+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
-+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
-+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
-+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
-+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
-+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
-+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0 default*/
-+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
-+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
-+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
-+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
-+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
-+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
-+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
-+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
-+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
-+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
-+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
-+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
-+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
-+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
-+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
-+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
-+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
-+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
-+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
-+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
-+};
-+
-+u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
-+	0x0b40002d, /* 0,  -15.0dB */
-+	0x0c000030, /* 1,  -14.5dB */
-+	0x0cc00033, /* 2,  -14.0dB */
-+	0x0d800036, /* 3,  -13.5dB */
-+	0x0e400039, /* 4,  -13.0dB */
-+	0x0f00003c, /* 5,  -12.5dB */
-+	0x10000040, /* 6,  -12.0dB */
-+	0x11000044, /* 7,  -11.5dB */
-+	0x12000048, /* 8,  -11.0dB */
-+	0x1300004c, /* 9,  -10.5dB */
-+	0x14400051, /* 10, -10.0dB */
-+	0x15800056, /* 11, -9.5dB */
-+	0x16c0005b, /* 12, -9.0dB */
-+	0x18000060, /* 13, -8.5dB */
-+	0x19800066, /* 14, -8.0dB */
-+	0x1b00006c, /* 15, -7.5dB */
-+	0x1c800072, /* 16, -7.0dB */
-+	0x1e400079, /* 17, -6.5dB */
-+	0x20000080, /* 18, -6.0dB */
-+	0x22000088, /* 19, -5.5dB */
-+	0x24000090, /* 20, -5.0dB */
-+	0x26000098, /* 21, -4.5dB */
-+	0x288000a2, /* 22, -4.0dB */
-+	0x2ac000ab, /* 23, -3.5dB */
-+	0x2d4000b5, /* 24, -3.0dB */
-+	0x300000c0, /* 25, -2.5dB */
-+	0x32c000cb, /* 26, -2.0dB */
-+	0x35c000d7, /* 27, -1.5dB */
-+	0x390000e4, /* 28, -1.0dB */
-+	0x3c8000f2, /* 29, -0.5dB */
-+	0x40000100, /* 30, +0dB */
-+	0x43c0010f, /* 31, +0.5dB */
-+	0x47c0011f, /* 32, +1.0dB */
-+	0x4c000130, /* 33, +1.5dB */
-+	0x50800142, /* 34, +2.0dB */
-+	0x55400155, /* 35, +2.5dB */
-+	0x5a400169, /* 36, +3.0dB */
-+	0x5fc0017f, /* 37, +3.5dB */
-+	0x65400195, /* 38, +4.0dB */
-+	0x6b8001ae, /* 39, +4.5dB */
-+	0x71c001c7, /* 40, +5.0dB */
-+	0x788001e2, /* 41, +5.5dB */
-+	0x7f8001fe /* 42, +6.0dB */
-+};
-+
-+u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
-+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
-+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
-+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
-+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
-+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
-+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
-+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
-+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
-+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
-+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
-+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
-+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
-+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
-+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
-+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
-+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
-+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
-+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
-+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
-+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
-+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
-+};
-+
-+u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
-+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
-+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
-+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
-+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
-+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
-+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
-+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
-+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
-+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
-+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
-+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
-+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
-+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
-+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
-+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
-+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
-+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
-+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
-+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
-+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
-+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
-+};
-+
-+u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
-+	{0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
-+	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
-+	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
-+	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
-+	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
-+	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
-+	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
-+	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
-+	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
-+	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
-+	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
-+	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
-+	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
-+	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
-+	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
-+	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
-+	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
-+	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
-+	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
-+	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
-+	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
-+};
-+
-+u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
-+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /*   0, -16.0dB*/
-+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /*   1, -15.5dB*/
-+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /*   2, -15.0dB*/
-+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /*   3, -14.5dB*/
-+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /*   4, -14.0dB*/
-+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /*   5, -13.5dB*/
-+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /*   6, -13.0dB*/
-+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /*   7, -12.5dB*/
-+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /*   8, -12.0dB*/
-+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /*   9, -11.5dB*/
-+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  10, -11.0dB*/
-+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  11, -10.5dB*/
-+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  12, -10.0dB*/
-+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  13, -9.5dB*/
-+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /*  14, -9.0dB */
-+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /*  15, -8.5dB*/
-+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /*  16, -8.0dB */
-+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /*  17, -7.5dB*/
-+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /*  18, -7.0dB */
-+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /*  19, -6.5dB*/
-+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*  20, -6.0dB */
-+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /*  21, -5.5dB*/
-+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /*  22, -5.0dB */
-+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /*  23, -4.5dB*/
-+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /*  24, -4.0dB */
-+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /*  25, -3.5dB*/
-+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /*  26, -3.0dB*/
-+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /*  27, -2.5dB*/
-+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /*  28, -2.0dB */
-+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /*  29, -1.5dB*/
-+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /*  30, -1.0dB*/
-+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /*  31, -0.5dB*/
-+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /*   32, +0dB*/
-+};
-+
-+u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
-+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /*  0, -16.0dB*/
-+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/
-+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  2, -15.0dB*/
-+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/
-+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  4, -14.0dB*/
-+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/
-+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/
-+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  7, -12.5dB*/
-+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/
-+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/
-+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/
-+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/
-+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/
-+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/
-+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */
-+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/
-+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
-+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/
-+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
-+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
-+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
-+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/
-+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
-+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/
-+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
-+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
-+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
-+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/
-+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
-+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/
-+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
-+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
-+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB	*/
-+};
-+
-+u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
-+	0x0CD, /*0 ,    -20dB*/
-+	0x0D9,
-+	0x0E6,
-+	0x0F3,
-+	0x102,
-+	0x111,
-+	0x121,
-+	0x132,
-+	0x144,
-+	0x158,
-+	0x16C,
-+	0x182,
-+	0x198,
-+	0x1B1,
-+	0x1CA,
-+	0x1E5,
-+	0x202,
-+	0x221,
-+	0x241,
-+	0x263,
-+	0x287,
-+	0x2AE,
-+	0x2D6,
-+	0x301,
-+	0x32F,
-+	0x35F,
-+	0x392,
-+	0x3C9,
-+	0x402,
-+	0x43F,
-+	0x47F,
-+	0x4C3,
-+	0x50C,
-+	0x558,
-+	0x5A9,
-+	0x5FF,
-+	0x65A,
-+	0x6BA,
-+	0x720,
-+	0x78C,
-+	0x7FF,
-+};
-+
-+/*@JJ ADD 20161014 */
-+u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
-+	0x0CD, /*0 ,    -20dB*/
-+	0x0D9,
-+	0x0E6,
-+	0x0F3,
-+	0x102,
-+	0x111,
-+	0x121,
-+	0x132,
-+	0x144,
-+	0x158,
-+	0x16C,
-+	0x182,
-+	0x198,
-+	0x1B1,
-+	0x1CA,
-+	0x1E5,
-+	0x202,
-+	0x221,
-+	0x241,
-+	0x263,
-+	0x287,
-+	0x2AE,
-+	0x2D6,
-+	0x301,
-+	0x32F,
-+	0x35F,
-+	0x392,
-+	0x3C9,
-+	0x402,
-+	0x43F,
-+	0x47F,
-+	0x4C3,
-+	0x50C,
-+	0x558,
-+	0x5A9,
-+	0x5FF,
-+	0x65A,
-+	0x6BA,
-+	0x720,
-+	0x78C,
-+	0x7FF,
-+};
-+
-+/*@Winnita ADD 20171116 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
-+u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
-+	0x0CD, /*0 ,    -20dB*/
-+	0x0D9,
-+	0x0E6,
-+	0x0F3,
-+	0x102,
-+	0x111,
-+	0x121,
-+	0x132,
-+	0x144,
-+	0x158,
-+	0x16C,
-+	0x182,
-+	0x198,
-+	0x1B1,
-+	0x1CA,
-+	0x1E5,
-+	0x202,
-+	0x221,
-+	0x241,
-+	0x263, /*19*/
-+	0x287, /*20*/
-+	0x2AE, /*21*/
-+	0x2D6, /*22*/
-+	0x301, /*23*/
-+	0x32F, /*24*/
-+	0x35F, /*25*/
-+	0x392, /*26*/
-+	0x3C9, /*27*/
-+	0x402, /*28*/
-+	0x43F, /*29*/
-+	0x47F, /*30*/
-+	0x4C3, /*31*/
-+	0x50C, /*32*/
-+	0x558, /*33*/
-+	0x5A9, /*34*/
-+	0x5FF, /*35*/
-+	0x65A, /*36*/
-+	0x6BA,
-+	0x720,
-+	0x78C,
-+	0x7FF,
-+};
-+
-+u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
-+	0x081, /* 0,  -12.0dB*/
-+	0x088, /* 1,  -11.5dB*/
-+	0x090, /* 2,  -11.0dB*/
-+	0x099, /* 3,  -10.5dB*/
-+	0x0A2, /* 4,  -10.0dB*/
-+	0x0AC, /* 5,  -9.5dB*/
-+	0x0B6, /* 6,  -9.0dB*/
-+	0x0C0, /*7,  -8.5dB*/
-+	0x0CC, /* 8,  -8.0dB*/
-+	0x0D8, /* 9,  -7.5dB*/
-+	0x0E5, /* 10, -7.0dB*/
-+	0x0F2, /* 11, -6.5dB*/
-+	0x101, /* 12, -6.0dB*/
-+	0x110, /* 13, -5.5dB*/
-+	0x120, /* 14, -5.0dB*/
-+	0x131, /* 15, -4.5dB*/
-+	0x143, /* 16, -4.0dB*/
-+	0x156, /* 17, -3.5dB*/
-+	0x16A, /* 18, -3.0dB*/
-+	0x180, /* 19, -2.5dB*/
-+	0x197, /* 20, -2.0dB*/
-+	0x1AF, /* 21, -1.5dB*/
-+	0x1C8, /* 22, -1.0dB*/
-+	0x1E3, /* 23, -0.5dB*/
-+	0x200, /* 24, +0  dB*/
-+	0x21E, /* 25, +0.5dB*/
-+	0x23E, /* 26, +1.0dB*/
-+	0x261, /* 27, +1.5dB*/
-+	0x285, /* 28, +2.0dB*/
-+	0x2AB, /* 29, +2.5dB*/
-+	0x2D3, /*30, +3.0dB*/
-+	0x2FE, /* 31, +3.5dB*/
-+	0x32B, /* 32, +4.0dB*/
-+	0x35C, /* 33, +4.5dB*/
-+	0x38E, /* 34, +5.0dB*/
-+	0x3C4, /* 35, +5.5dB*/
-+	0x3FE /* 36, +6.0dB	*/
-+};
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+#else
-+u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3,
-+					  4, 4, 4, 4, 4, 4, 4, 4, 5, 5,
-+					  7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
-+u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4,
-+					  4, 5, 5, 6, 6, 7, 7, 7, 7, 8,
-+					  8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
-+#endif
-+
-+void odm_txpowertracking_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	odm_txpowertracking_thermal_meter_init(dm);
-+}
-+
-+u8 get_swing_index(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
-+	void *adapter = dm->adapter;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+#endif
-+	u8 i = 0;
-+	u32 bb_swing, table_value;
-+
-+	if (dm->support_ic_type &
-+		(ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |
-+		ODM_RTL8188F | ODM_RTL8703B | ODM_RTL8723D |
-+		ODM_RTL8710B)) {
-+
-+		bb_swing = odm_get_bb_reg(dm, R_0xc80, 0xFFC00000);
-+
-+		for (i = 0; i < OFDM_TABLE_SIZE; i++) {
-+			table_value = ofdm_swing_table_new[i];
-+
-+			if (table_value >= 0x100000)
-+				table_value >>= 22;
-+			if (bb_swing == table_value)
-+				break;
-+		}
-+	} else {
-+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
-+		bb_swing =
-+		phy_get_tx_bb_swing_8812a(adapter,
-+					  hal_data->current_band_type,
-+					  RF_PATH_A);
-+#else
-+		bb_swing = odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000);
-+#endif
-+		for (i = 0; i < TXSCALE_TABLE_SIZE; i++) {
-+			table_value = tx_scaling_table_jaguar[i];
-+
-+			if (bb_swing == table_value)
-+				break;
-+		}
-+	}
-+
-+	return i;
-+}
-+
-+u8 get_cck_swing_index(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	u8 i = 0;
-+	u32 bb_cck_swing;
-+
-+	if (dm->support_ic_type &
-+		(ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E)) {
-+		bb_cck_swing = odm_read_1byte(dm, 0xa22);
-+
-+		for (i = 0; i < CCK_TABLE_SIZE; i++) {
-+			if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
-+				break;
-+		}
-+	} else if (dm->support_ic_type & ODM_RTL8703B) {
-+		bb_cck_swing = odm_read_1byte(dm, 0xa22);
-+
-+		for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
-+			if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
-+				break;
-+		}
-+	}
-+
-+	return i;
-+}
-+
-+s8
-+get_txagc_default_index(
-+	void *dm_void
-+)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	s8 tmp;
-+
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		tmp = (s8)(odm_get_bb_reg(dm, R_0x18a0, 0x7f) & 0xff);
-+		if (tmp & BIT(6))
-+			tmp = tmp | 0x80;
-+		return tmp;
-+	} else
-+		return 0;
-+}
-+
-+void odm_txpowertracking_thermal_meter_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
-+
-+	u8 swing_idx = get_swing_index(dm);
-+	u8 cckswing_idx = get_cck_swing_index(dm);
-+	u8 p = 0;
-+
-+	cali_info->is_txpowertracking = true;
-+	cali_info->tx_powercount = 0;
-+	cali_info->is_txpowertracking_init = false;
-+
-+	if (!(*dm->mp_mode))
-+		cali_info->txpowertrack_control = true;
-+	else
-+		cali_info->txpowertrack_control = false;
-+
-+	if (!(*dm->mp_mode))
-+		cali_info->txpowertrack_control = true;
-+
-+	RF_DBG(dm, DBG_RF_IQK, "dm txpowertrack_control = %d\n",
-+	       cali_info->txpowertrack_control);
-+#if 0
-+	/* dm->rf_calibrate_info.txpowertrack_control = true; */
-+#endif
-+	cali_info->thermal_value = rf->eeprom_thermal;
-+	cali_info->thermal_value_iqk = rf->eeprom_thermal;
-+	cali_info->thermal_value_lck = rf->eeprom_thermal;
-+
-+#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8822C) {
-+		cali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];
-+		cali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];
-+		cali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];
-+		cali_info->thermal_value_lck = tssi->thermal[RF_PATH_A];
-+	}
-+	
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		cali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];
-+		cali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];
-+		cali_info->thermal_value_path[RF_PATH_C] = tssi->thermal[RF_PATH_C];
-+		cali_info->thermal_value_path[RF_PATH_D] = tssi->thermal[RF_PATH_D];
-+		cali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];
-+		cali_info->thermal_value_lck = tssi->thermal[RF_PATH_A];
-+	}
-+#endif
-+
-+	if (!cali_info->default_bb_swing_index_flag) {
-+		if (dm->support_ic_type &
-+			(ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |
-+			ODM_RTL8703B | ODM_RTL8821)) {
-+			if (swing_idx >= OFDM_TABLE_SIZE)
-+				cali_info->default_ofdm_index = 30;
-+			else
-+				cali_info->default_ofdm_index = swing_idx;
-+
-+			if (cckswing_idx >= CCK_TABLE_SIZE)
-+				cali_info->default_cck_index = 20;
-+			else
-+				cali_info->default_cck_index = cckswing_idx;
-+		/*@add by Mingzhi.Guo  2015-03-23*/
-+		} else if (dm->support_ic_type == ODM_RTL8188F) {
-+			cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
-+			cali_info->default_cck_index = 20; /*CCK:-6dB*/
-+		/*@add by zhaohe  2015-10-27*/
-+		} else if (dm->support_ic_type == ODM_RTL8723D) {
-+			cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
-+			cali_info->default_cck_index = 28; /*CCK:   -6dB*/
-+		/*@JJ ADD 20161014 */
-+		} else if (dm->support_ic_type == ODM_RTL8710B) {
-+			cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
-+			cali_info->default_cck_index = 28; /*CCK:   -6dB*/
-+		} else if (dm->support_ic_type == ODM_RTL8192F) {
-+			cali_info->default_ofdm_index = 30;/*OFDM: 0dB*/
-+			cali_info->default_cck_index = 28; /*CCK:   -6dB*/
-+		} else {
-+			if (swing_idx >= TXSCALE_TABLE_SIZE)
-+				cali_info->default_ofdm_index = 24;
-+			else
-+				cali_info->default_ofdm_index = swing_idx;
-+
-+			cali_info->default_txagc_index = get_txagc_default_index(dm);
-+
-+			cali_info->default_cck_index = 24;
-+		}
-+		cali_info->default_bb_swing_index_flag = true;
-+	}
-+
-+	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
-+	cali_info->CCK_index = cali_info->default_cck_index;
-+
-+	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
-+		cali_info->bb_swing_idx_ofdm_base[p] =
-+						cali_info->default_ofdm_index;
-+		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
-+		cali_info->delta_power_index[p] = 0;
-+		cali_info->delta_power_index_last[p] = 0;
-+		cali_info->power_index_offset[p] = 0;
-+	}
-+	cali_info->modify_tx_agc_value_ofdm = 0;
-+	cali_info->modify_tx_agc_value_cck = 0;
-+	cali_info->tm_trigger = 0;
-+}
-+
-+void odm_txpowertracking_check(void *dm_void)
-+{
-+	/*@2011/09/29 MH In HW integration first stage
-+	 * we provide 4 different handle to operate at the same time.
-+	 * In the stage2/3, we need to prive universal interface and merge all
-+	 * HW dynamic mechanism.
-+	 */
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	switch (dm->support_platform) {
-+	case ODM_WIN:
-+		odm_txpowertracking_check_mp(dm);
-+		break;
-+
-+	case ODM_CE:
-+		odm_txpowertracking_check_ce(dm);
-+		break;
-+
-+	case ODM_AP:
-+		odm_txpowertracking_check_ap(dm);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+void odm_txpowertracking_check_ce(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
-+		return;
-+
-+	if ((rf->power_track_type & 0xf0) >> 4 != 0) {
-+		if (dm->support_ic_type & ODM_RTL8822C) {
-+			/*halrf_tssi_cck(dm);*/
-+			/*halrf_thermal_cck(dm);*/
-+			return;
-+		}
-+	}
-+
-+	if (!dm->rf_calibrate_info.tm_trigger) {
-+		if (dm->support_ic_type &
-+			(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8192E |
-+			ODM_RTL8723B | ODM_RTL8812 | ODM_RTL8821 |
-+			ODM_RTL8814A | ODM_RTL8703B | ODM_RTL8723D |
-+			ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8710B |
-+			ODM_RTL8192F))
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW,
-+				       (BIT(17) | BIT(16)), 0x03);
-+		else if (dm->support_ic_type & ODM_RTL8822C) {
-+			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
-+			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);
-+			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
-+			
-+			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
-+			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);
-+			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
-+		} else if (dm->support_ic_type & ODM_RTL8814B) {
-+			odm_set_rf_reg(dm, RF_PATH_A, 0x42, BIT(17), 0x1);
-+			odm_set_rf_reg(dm, RF_PATH_B, 0x42, BIT(17), 0x1);
-+			odm_set_rf_reg(dm, RF_PATH_C, 0x42, BIT(17), 0x1);
-+			odm_set_rf_reg(dm, RF_PATH_D, 0x42, BIT(17), 0x1);
-+		} else
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_OLD,
-+				       RFREGOFFSETMASK, 0x60);
-+
-+#if (RTL8814B_SUPPORT == 1)
-+		if (dm->support_ic_type & ODM_RTL8814B) {
-+			ODM_delay_us(300);
-+			odm_txpowertracking_new_callback_thermal_meter(dm);
-+			tssi->thermal_trigger = 1;
-+		}
-+#endif
-+		dm->rf_calibrate_info.tm_trigger = 1;
-+		return;
-+	}
-+	
-+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) {
-+#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-+		odm_txpowertracking_new_callback_thermal_meter(dm);
-+		if (dm->support_ic_type & ODM_RTL8814B)
-+			tssi->thermal_trigger = 0;
-+#endif
-+	} else
-+		odm_txpowertracking_callback_thermal_meter(dm);
-+	dm->rf_calibrate_info.tm_trigger = 0;
-+#endif
-+}
-+
-+void
-+odm_txpowertracking_direct_ce(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+
-+	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
-+		return;
-+
-+	if (dm->support_ic_type & ODM_RTL8822C) {
-+		/*halrf_tssi_cck(dm);*/
-+		/*halrf_thermal_cck(dm);*/
-+		return;
-+	}
-+
-+	if (dm->support_ic_type &
-+		(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8192E |
-+		ODM_RTL8723B | ODM_RTL8812 | ODM_RTL8821 |
-+		ODM_RTL8814A | ODM_RTL8703B | ODM_RTL8723D |
-+		ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8710B |
-+		ODM_RTL8192F | ODM_RTL8814B))
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);
-+	else if (dm->support_ic_type & ODM_RTL8822C) {
-+		odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
-+		odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);
-+		odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
-+			
-+		odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
-+		odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);
-+		odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
-+	} else
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_OLD, RFREGOFFSETMASK, 0x60);
-+
-+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) {
-+#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-+		odm_txpowertracking_new_callback_thermal_meter(dm);
-+#endif
-+	} else
-+		odm_txpowertracking_callback_thermal_meter(dm);
-+#endif
-+
-+}
-+
-+
-+void odm_txpowertracking_check_mp(void *dm_void)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	void *adapter = dm->adapter;
-+
-+	if (odm_check_power_status(adapter) == false) {
-+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
-+			 ("check_pow_status, return false\n"));
-+		return;
-+	}
-+
-+	odm_txpowertracking_thermal_meter_check(adapter);
-+#endif
-+}
-+
-+void odm_txpowertracking_check_ap(void *dm_void)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rtl8192cd_priv *priv = dm->priv;
-+
-+	return;
-+
-+#endif
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_ce.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_ce.h
-new file mode 100644
-index 000000000000..3fec1abf799f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_ce.h
-@@ -0,0 +1,331 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_POWERTRACKING_H__
-+#define __HALRF_POWERTRACKING_H__
-+
-+#define DPK_DELTA_MAPPING_NUM 13
-+#define index_mapping_HP_NUM 15
-+#define OFDM_TABLE_SIZE 43
-+#define CCK_TABLE_SIZE 33
-+#define CCK_TABLE_SIZE_88F 21
-+#define TXSCALE_TABLE_SIZE 37
-+#define CCK_TABLE_SIZE_8723D 41
-+/*@JJ ADD 20161014 */
-+#define CCK_TABLE_SIZE_8710B 41
-+#define CCK_TABLE_SIZE_8192F 41
-+
-+#define TXPWR_TRACK_TABLE_SIZE 30
-+#define DELTA_SWINGIDX_SIZE 30
-+#define DELTA_SWINTSSI_SIZE 61
-+#define BAND_NUM 4
-+
-+#define AVG_THERMAL_NUM 8
-+#define IQK_MAC_REG_NUM 4
-+#define IQK_ADDA_REG_NUM 16
-+#define IQK_BB_REG_NUM_MAX 10
-+
-+#define IQK_BB_REG_NUM 9
-+
-+#define iqk_matrix_reg_num 8
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+#else
-+/* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
-+#define IQK_MATRIX_SETTINGS_NUM (14 + 24 + 21)
-+#endif
-+
-+extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
-+extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
-+extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
-+
-+extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
-+extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
-+extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
-+extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
-+extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
-+extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
-+extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
-+/*@JJ ADD 20161014 */
-+extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
-+extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
-+
-+extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
-+
-+/*@<20121018, Kordan> In case fail to read TxPowerTrack.txt */
-+/* we use the table of 88E as the default table. */
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+#else
-+extern u8 delta_swing_table_idx_2ga_p_8188e[];
-+extern u8 delta_swing_table_idx_2ga_n_8188e[];
-+#endif
-+
-+#define dm_check_txpowertracking odm_txpowertracking_check
-+
-+struct iqk_matrix_regs_setting {
-+	boolean is_iqk_done;
-+	s32 value[3][iqk_matrix_reg_num];
-+	boolean is_bw_iqk_result_saved[3];
-+};
-+
-+struct dm_rf_calibration_struct {
-+	/* for tx power tracking */
-+
-+	u32 rega24; /* for TempCCK */
-+	s32 rege94;
-+	s32 rege9c;
-+	s32 regeb4;
-+	s32 regebc;
-+
-+	u8 tx_powercount;
-+	boolean is_txpowertracking_init;
-+	boolean is_txpowertracking;
-+	/* for mp mode, turn off txpwrtracking as default */
-+	u8 txpowertrack_control;
-+	u8 tm_trigger;
-+	u8 internal_pa_5g[2]; /* pathA / pathB */
-+
-+	/* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
-+	u8 thermal_meter[2];
-+	u8 thermal_value;
-+	u8 thermal_value_path[MAX_RF_PATH];
-+	u8 thermal_value_lck;
-+	u8 thermal_value_iqk;
-+	s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
-+	u8 thermal_value_dpk;
-+	u8 thermal_value_avg[AVG_THERMAL_NUM];
-+	u8 thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];
-+	u8 thermal_value_avg_index;
-+	u8 thermal_value_avg_index_path[MAX_RF_PATH];
-+	u8 thermal_value_rx_gain;
-+	u8 thermal_value_crystal;
-+	u8 thermal_value_dpk_store;
-+	u8 thermal_value_dpk_track;
-+	boolean txpowertracking_in_progress;
-+
-+	boolean is_reloadtxpowerindex;
-+	u8 is_rf_pi_enable;
-+	u32 txpowertracking_callback_cnt; /* cosa add for debug */
-+
-+	/*@---------------------- Tx power Tracking ---------------------- */
-+	u8 is_cck_in_ch14;
-+	u8 CCK_index;
-+	u8 OFDM_index[MAX_RF_PATH];
-+	s8 power_index_offset[MAX_RF_PATH];
-+	s8 delta_power_index[MAX_RF_PATH];
-+	s8 delta_power_index_last[MAX_RF_PATH];
-+	boolean is_tx_power_changed;
-+	s8 xtal_offset;
-+	s8 xtal_offset_last;
-+	u8 xtal_offset_eanble;
-+
-+	struct iqk_matrix_regs_setting
-+				iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
-+	u8 delta_lck;
-+	s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
-+	u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
-+	u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
-+	u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
-+	u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
-+	u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
-+	u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
-+	u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
-+	u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
-+	u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
-+	s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
-+	u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
-+
-+	u8 bb_swing_idx_ofdm[MAX_RF_PATH];
-+	u8 bb_swing_idx_ofdm_current;
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
-+#else
-+	u8 bb_swing_idx_ofdm_base;
-+#endif
-+	boolean default_bb_swing_index_flag;
-+	boolean bb_swing_flag_ofdm;
-+	u8 bb_swing_idx_cck;
-+	u8 bb_swing_idx_cck_current;
-+	u8 bb_swing_idx_cck_base;
-+	u8 default_ofdm_index;
-+	u8 default_cck_index;
-+	s8 default_txagc_index;
-+	boolean bb_swing_flag_cck;
-+
-+	s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
-+	s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
-+	s8 absolute_cck_swing_idx[MAX_RF_PATH];
-+	s8 remnant_cck_swing_idx;
-+	s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
-+	boolean modify_tx_agc_flag_path_a;
-+	boolean modify_tx_agc_flag_path_b;
-+	boolean modify_tx_agc_flag_path_c;
-+	boolean modify_tx_agc_flag_path_d;
-+	boolean modify_tx_agc_flag_path_a_cck;
-+	boolean modify_tx_agc_flag_path_b_cck;
-+
-+	s8 kfree_offset[MAX_RF_PATH];
-+
-+	/*@----------------------------------------------------------------- */
-+
-+	/* for IQK */
-+	u32 regc04;
-+	u32 reg874;
-+	u32 regc08;
-+	u32 regb68;
-+	u32 regb6c;
-+	u32 reg870;
-+	u32 reg860;
-+	u32 reg864;
-+
-+	boolean is_iqk_initialized;
-+	boolean is_lck_in_progress;
-+	boolean is_antenna_detected;
-+	boolean is_need_iqk;
-+	boolean is_iqk_in_progress;
-+	boolean is_iqk_pa_off;
-+	u8 delta_iqk;
-+	u32 ADDA_backup[IQK_ADDA_REG_NUM];
-+	u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
-+	u32 IQK_BB_backup_recover[9];
-+	u32 IQK_BB_backup[IQK_BB_REG_NUM];
-+	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
-+	u32 tx_iqc_8723b[2][3][2];
-+	/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
-+	u32 rx_iqc_8723b[2][2][2];
-+	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
-+	u32 tx_iqc_8703b[3][2];
-+	/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
-+	u32 rx_iqc_8703b[2][2];
-+	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
-+	u32 tx_iqc_8723d[2][3][2];
-+	/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
-+	u32 rx_iqc_8723d[2][2][2];
-+	/* JJ ADD 20161014 */
-+	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
-+	u32 tx_iqc_8710b[2][3][2];
-+	/* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
-+	u32 rx_iqc_8710b[2][2][2];
-+
-+	u8 iqk_step;
-+	u8 kcount;
-+	u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
-+	boolean is_mp_mode;
-+
-+	/*@<James> IQK time measurement */
-+	u64 iqk_start_time;
-+	u64 iqk_progressing_time;
-+	u64 iqk_total_progressing_time;
-+	u64 lck_progressing_time;
-+
-+	u32 lok_result;
-+
-+	/* for APK */
-+	u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
-+	u8 is_ap_kdone;
-+	u8 is_apk_thermal_meter_ignore;
-+
-+	/* DPK */
-+	boolean is_dpk_fail;
-+	u8 is_dp_done;
-+	u8 is_dp_path_aok;
-+	u8 is_dp_path_bok;
-+
-+	u32 tx_lok[2];
-+	u32 dpk_tx_agc;
-+	s32 dpk_gain;
-+	u32 dpk_thermal[4];
-+	s8 modify_tx_agc_value_ofdm;
-+	s8 modify_tx_agc_value_cck;
-+
-+	/*@Add by Yuchen for Kfree Phydm*/
-+	u8 reg_rf_kfree_enable; /*for registry*/
-+	u8 rf_kfree_enable; /*for efuse enable check*/
-+};
-+
-+void odm_txpowertracking_check(void *dm_void);
-+
-+void odm_txpowertracking_init(void *dm_void);
-+
-+void odm_txpowertracking_check_ap(void *dm_void);
-+
-+void odm_txpowertracking_thermal_meter_init(void *dm_void);
-+
-+void odm_txpowertracking_init(void *dm_void);
-+
-+void odm_txpowertracking_check_mp(void *dm_void);
-+
-+void odm_txpowertracking_check_ce(void *dm_void);
-+
-+void odm_txpowertracking_direct_ce(void *dm_void);
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+
-+void odm_txpowertracking_callback_thermal_meter92c(
-+	void *adapter);
-+
-+void odm_txpowertracking_callback_rx_gain_thermal_meter92d(
-+	void *adapter);
-+
-+void odm_txpowertracking_callback_thermal_meter92d(
-+	void *adapter);
-+
-+void odm_txpowertracking_direct_call92c(
-+	void *adapter);
-+
-+void odm_txpowertracking_thermal_meter_check(
-+	void *adapter);
-+
-+#endif
-+
-+#endif /*__HALRF_POWER_TRACKING_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_iot.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_iot.c
-new file mode 100644
-index 000000000000..494fdec37a46
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_iot.c
-@@ -0,0 +1,1004 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*============================================================	*/
-+/* include files												*/
-+/*============================================================	*/
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+/* ************************************************************
-+ * Global var
-+ * ************************************************************
-+ */
-+
-+const u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
-+	0x7f8001fe,	/* 0, +6.0dB */
-+	0x788001e2,	/* 1, +5.5dB */
-+	0x71c001c7,	/* 2, +5.0dB*/
-+	0x6b8001ae,	/* 3, +4.5dB*/
-+	0x65400195,	/* 4, +4.0dB*/
-+	0x5fc0017f,	/* 5, +3.5dB*/
-+	0x5a400169,	/* 6, +3.0dB*/
-+	0x55400155,	/* 7, +2.5dB*/
-+	0x50800142,	/* 8, +2.0dB*/
-+	0x4c000130,	/* 9, +1.5dB*/
-+	0x47c0011f,	/* 10, +1.0dB*/
-+	0x43c0010f,	/* 11, +0.5dB*/
-+	0x40000100,	/* 12, +0dB*/
-+	0x3c8000f2,	/* 13, -0.5dB*/
-+	0x390000e4,	/* 14, -1.0dB*/
-+	0x35c000d7,	/* 15, -1.5dB*/
-+	0x32c000cb,	/* 16, -2.0dB*/
-+	0x300000c0,	/* 17, -2.5dB*/
-+	0x2d4000b5,	/* 18, -3.0dB*/
-+	0x2ac000ab,	/* 19, -3.5dB*/
-+	0x288000a2,	/* 20, -4.0dB*/
-+	0x26000098,	/* 21, -4.5dB*/
-+	0x24000090,	/* 22, -5.0dB*/
-+	0x22000088,	/* 23, -5.5dB*/
-+	0x20000080,	/* 24, -6.0dB*/
-+	0x1e400079,	/* 25, -6.5dB*/
-+	0x1c800072,	/* 26, -7.0dB*/
-+	0x1b00006c,	/* 27. -7.5dB*/
-+	0x19800066,	/* 28, -8.0dB*/
-+	0x18000060,	/* 29, -8.5dB*/
-+	0x16c0005b,	/* 30, -9.0dB*/
-+	0x15800056,	/* 31, -9.5dB*/
-+	0x14400051,	/* 32, -10.0dB*/
-+	0x1300004c,	/* 33, -10.5dB*/
-+	0x12000048,	/* 34, -11.0dB*/
-+	0x11000044,	/* 35, -11.5dB*/
-+	0x10000040,	/* 36, -12.0dB*/
-+};
-+
-+const u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
-+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},	/* 0, +0dB */
-+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 1, -0.5dB */
-+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 2, -1.0dB*/
-+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 3, -1.5dB*/
-+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 4, -2.0dB */
-+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 5, -2.5dB*/
-+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 6, -3.0dB*/
-+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 7, -3.5dB*/
-+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 8, -4.0dB */
-+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 9, -4.5dB*/
-+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 10, -5.0dB */
-+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 11, -5.5dB*/
-+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/* 12, -6.0dB <== default */
-+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 13, -6.5dB*/
-+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 14, -7.0dB */
-+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 15, -7.5dB*/
-+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
-+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 17, -8.5dB*/
-+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 18, -9.0dB */
-+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 19, -9.5dB*/
-+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 20, -10.0dB*/
-+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 21, -10.5dB*/
-+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 22, -11.0dB*/
-+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 23, -11.5dB*/
-+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 24, -12.0dB*/
-+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 25, -12.5dB*/
-+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 26, -13.0dB*/
-+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 27, -13.5dB*/
-+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 28, -14.0dB*/
-+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 29, -14.5dB*/
-+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 30, -15.0dB*/
-+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 31, -15.5dB*/
-+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}	/* 32, -16.0dB*/
-+};
-+
-+const u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
-+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},	/* 0, +0dB */
-+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 1, -0.5dB */
-+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 2, -1.0dB */
-+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 3, -1.5dB*/
-+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 4, -2.0dB */
-+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 5, -2.5dB*/
-+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 6, -3.0dB */
-+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 7, -3.5dB */
-+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 8, -4.0dB */
-+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 9, -4.5dB*/
-+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 10, -5.0dB */
-+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 11, -5.5dB*/
-+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 12, -6.0dB  <== default*/
-+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 13, -6.5dB */
-+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 14, -7.0dB */
-+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 15, -7.5dB*/
-+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
-+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 17, -8.5dB*/
-+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 18, -9.0dB */
-+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 19, -9.5dB*/
-+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 20, -10.0dB*/
-+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 21, -10.5dB*/
-+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 22, -11.0dB*/
-+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 23, -11.5dB*/
-+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 24, -12.0dB*/
-+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 25, -12.5dB*/
-+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 26, -13.0dB*/
-+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 27, -13.5dB*/
-+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 28, -14.0dB*/
-+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 29, -14.5dB*/
-+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 30, -15.0dB*/
-+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 31, -15.5dB*/
-+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}	/* 32, -16.0dB*/
-+};
-+
-+const u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
-+	0x0b40002d, /* 0,  -15.0dB	*/
-+	0x0c000030, /* 1,  -14.5dB*/
-+	0x0cc00033, /* 2,  -14.0dB*/
-+	0x0d800036, /* 3,  -13.5dB*/
-+	0x0e400039, /* 4,  -13.0dB */
-+	0x0f00003c, /* 5,  -12.5dB*/
-+	0x10000040, /* 6,  -12.0dB*/
-+	0x11000044, /* 7,  -11.5dB*/
-+	0x12000048, /* 8,  -11.0dB*/
-+	0x1300004c, /* 9,  -10.5dB*/
-+	0x14400051, /* 10, -10.0dB*/
-+	0x15800056, /* 11, -9.5dB*/
-+	0x16c0005b, /* 12, -9.0dB*/
-+	0x18000060, /* 13, -8.5dB*/
-+	0x19800066, /* 14, -8.0dB*/
-+	0x1b00006c, /* 15, -7.5dB*/
-+	0x1c800072, /* 16, -7.0dB*/
-+	0x1e400079, /* 17, -6.5dB*/
-+	0x20000080, /* 18, -6.0dB*/
-+	0x22000088, /* 19, -5.5dB*/
-+	0x24000090, /* 20, -5.0dB*/
-+	0x26000098, /* 21, -4.5dB*/
-+	0x288000a2, /* 22, -4.0dB*/
-+	0x2ac000ab, /* 23, -3.5dB*/
-+	0x2d4000b5, /* 24, -3.0dB*/
-+	0x300000c0, /* 25, -2.5dB*/
-+	0x32c000cb, /* 26, -2.0dB*/
-+	0x35c000d7, /* 27, -1.5dB*/
-+	0x390000e4, /* 28, -1.0dB*/
-+	0x3c8000f2, /* 29, -0.5dB*/
-+	0x40000100, /* 30, +0dB*/
-+	0x43c0010f, /* 31, +0.5dB*/
-+	0x47c0011f, /* 32, +1.0dB*/
-+	0x4c000130, /* 33, +1.5dB*/
-+	0x50800142, /* 34, +2.0dB*/
-+	0x55400155, /* 35, +2.5dB*/
-+	0x5a400169, /* 36, +3.0dB*/
-+	0x5fc0017f, /* 37, +3.5dB*/
-+	0x65400195, /* 38, +4.0dB*/
-+	0x6b8001ae, /* 39, +4.5dB*/
-+	0x71c001c7, /* 40, +5.0dB*/
-+	0x788001e2, /* 41, +5.5dB*/
-+	0x7f8001fe  /* 42, +6.0dB*/
-+};
-+
-+const u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
-+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
-+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
-+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
-+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
-+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
-+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
-+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
-+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
-+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
-+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
-+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
-+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
-+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
-+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
-+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
-+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
-+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
-+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
-+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
-+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
-+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
-+};
-+
-+const u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
-+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
-+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
-+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
-+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
-+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
-+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
-+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
-+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
-+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
-+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
-+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
-+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
-+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
-+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
-+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
-+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
-+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
-+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
-+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
-+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
-+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
-+};
-+
-+const u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
-+	{0x44,	 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
-+	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
-+	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
-+	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	    /*-14.5dB*/
-+	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
-+	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
-+	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
-+	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
-+	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
-+	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
-+	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
-+	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
-+	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
-+	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
-+	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
-+	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
-+	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
-+	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
-+	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
-+	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
-+	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
-+};
-+
-+const u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
-+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/*  0, -16.0dB*/
-+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/*   1, -15.5dB*/
-+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/*  2, -15.0dB*/
-+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/*   3, -14.5dB*/
-+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/*   4, -14.0dB*/
-+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/*   5, -13.5dB*/
-+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/*   6, -13.0dB*/
-+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/*   7, -12.5dB*/
-+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/*  8, -12.0dB*/
-+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/*   9, -11.5dB*/
-+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/*  10, -11.0dB*/
-+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/*  11, -10.5dB*/
-+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/*  12, -10.0dB*/
-+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/*  13, -9.5dB*/
-+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/*  14, -9.0dB */
-+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/*  15, -8.5dB*/
-+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/*  16, -8.0dB */
-+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/*  17, -7.5dB*/
-+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/*  18, -7.0dB */
-+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/*  19, -6.5dB*/
-+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/*20, -6.0dB */
-+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/*  21, -5.5dB*/
-+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
-+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/*  23, -4.5dB*/
-+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/*  24, -4.0dB */
-+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/*  25, -3.5dB*/
-+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/*  26, -3.0dB*/
-+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/*  27, -2.5dB*/
-+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/*  28, -2.0dB */
-+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/*  29, -1.5dB*/
-+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/*  30, -1.0dB*/
-+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/*  31, -0.5dB*/
-+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/*  32, +0dB*/
-+};
-+
-+const u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
-+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/*  0, -16.0dB*/
-+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB*/
-+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/*  2, -15.0dB*/
-+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB*/
-+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/*  4, -14.0dB*/
-+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/*5, -13.5dB*/
-+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB*/
-+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/*  7, -12.5dB*/
-+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB*/
-+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB*/
-+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB*/
-+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/*11, -10.5dB*/
-+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB*/
-+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB*/
-+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/*14, -9.0dB */
-+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB*/
-+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
-+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB*/
-+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
-+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
-+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
-+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB*/
-+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
-+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/*23, -4.5dB*/
-+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
-+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
-+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
-+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/*27, -2.5dB*/
-+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
-+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/*29, -1.5dB*/
-+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
-+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
-+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB	*/
-+};
-+
-+const u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
-+	0x0CD,          /*0 ,    -20dB*/
-+	0x0D9,
-+	0x0E6,
-+	0x0F3,
-+	0x102,
-+	0x111,
-+	0x121,
-+	0x132,
-+	0x144,
-+	0x158,
-+	0x16C,
-+	0x182,
-+	0x198,
-+	0x1B1,
-+	0x1CA,
-+	0x1E5,
-+	0x202,
-+	0x221,
-+	0x241,
-+	0x263,
-+	0x287,
-+	0x2AE,
-+	0x2D6,
-+	0x301,
-+	0x32F,
-+	0x35F,
-+	0x392,
-+	0x3C9,
-+	0x402,
-+	0x43F,
-+	0x47F,
-+	0x4C3,
-+	0x50C,
-+	0x558,
-+	0x5A9,
-+	0x5FF,
-+	0x65A,
-+	0x6BA,
-+	0x720,
-+	0x78C,
-+	0x7FF,
-+};
-+
-+/* JJ ADD 20161014 */
-+const u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
-+	0x0CD,          /*0 ,    -20dB*/
-+	0x0D9,
-+	0x0E6,
-+	0x0F3,
-+	0x102,
-+	0x111,
-+	0x121,
-+	0x132,
-+	0x144,
-+	0x158,
-+	0x16C,
-+	0x182,
-+	0x198,
-+	0x1B1,
-+	0x1CA,
-+	0x1E5,
-+	0x202,
-+	0x221,
-+	0x241,
-+	0x263,
-+	0x287,
-+	0x2AE,
-+	0x2D6,
-+	0x301,
-+	0x32F,
-+	0x35F,
-+	0x392,
-+	0x3C9,
-+	0x402,
-+	0x43F,
-+	0x47F,
-+	0x4C3,
-+	0x50C,
-+	0x558,
-+	0x5A9,
-+	0x5FF,
-+	0x65A,
-+	0x6BA,
-+	0x720,
-+	0x78C,
-+	0x7FF,
-+};
-+
-+/* Winnita ADD 20171116 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
-+const u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
-+	0x0CD,			 /*0 ,    -20dB*/
-+	0x0D9,
-+	0x0E6,
-+	0x0F3,
-+	0x102,
-+	0x111,
-+	0x121,
-+	0x132,
-+	0x144,
-+	0x158,
-+	0x16C,
-+	0x182,
-+	0x198,
-+	0x1B1,
-+	0x1CA,
-+	0x1E5,
-+	0x202,
-+	0x221,
-+	0x241,
-+	0x263,		/*19*/
-+	0x287,		/*20*/
-+	0x2AE,		/*21*/
-+	0x2D6,		/*22*/
-+	0x301,		/*23*/
-+	0x32F,		/*24*/
-+	0x35F,		/*25*/
-+	0x392,		/*26*/
-+	0x3C9,		/*27*/
-+	0x402,		/*28*/
-+	0x43F,		/*29*/
-+	0x47F,		/*30*/
-+	0x4C3,		/*31*/
-+	0x50C,		/*32*/
-+	0x558,		/*33*/
-+	0x5A9,		/*34*/
-+	0x5FF,		/*35*/
-+	0x65A,		/*36*/
-+	0x6BA,
-+	0x720,
-+	0x78C,
-+	0x7FF,
-+};
-+
-+/* Winnita ADD 201805 PathA 0xAB4[10:0]*/
-+const u32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D] = {
-+	0x0CD,			 /*0 ,    -20dB*/
-+	0x0D9,
-+	0x0E6,
-+	0x0F3,
-+	0x102,
-+	0x111,
-+	0x121,
-+	0x132,
-+	0x144,
-+	0x158,
-+	0x16C,
-+	0x182,
-+	0x198,
-+	0x1B1,
-+	0x1CA,
-+	0x1E5,
-+	0x202,
-+	0x221,
-+	0x241,
-+	0x263,		/*19*/
-+	0x287,		/*20*/
-+	0x2AE,		/*21*/
-+	0x2D6,		/*22*/
-+	0x301,		/*23*/
-+	0x32F,		/*24*/
-+	0x35F,		/*25*/
-+	0x392,		/*26*/
-+	0x3C9,		/*27*/
-+	0x402,		/*28*/
-+	0x43F,		/*29*/
-+	0x47F,		/*30*/
-+	0x4C3,		/*31*/
-+	0x50C,		/*32*/
-+	0x558,		/*33*/
-+	0x5A9,		/*34*/
-+	0x5FF,		/*35*/
-+	0x65A,		/*36*/
-+	0x6BA,
-+	0x720,
-+	0x78C,
-+	0x7FF,
-+};
-+
-+const u32 cck_swing_table_ch1_ch14_8710c[CCK_TABLE_SIZE_8710C] = {
-+	0x0CD,          /*0 ,    -20dB*/
-+	0x0D9,
-+	0x0E6,
-+	0x0F3,
-+	0x102,
-+	0x111,
-+	0x121,
-+	0x132,
-+	0x144,
-+	0x158,
-+	0x16C,
-+	0x182,
-+	0x198,
-+	0x1B1,
-+	0x1CA,
-+	0x1E5,
-+	0x202,
-+	0x221,
-+	0x241,
-+	0x263,
-+	0x287,
-+	0x2AE,
-+	0x2D6,
-+	0x301,
-+	0x32F,
-+	0x35F,
-+	0x392,
-+	0x3C9,
-+	0x402,
-+	0x43F,
-+	0x47F,
-+	0x4C3,
-+	0x50C,
-+	0x558,
-+	0x5A9,
-+	0x5FF,
-+	0x65A,
-+	0x6BA,
-+	0x720,
-+	0x78C,
-+	0x7FF,
-+};
-+
-+const u32 cck_swing_table_03db_ch1_ch14_8710c[CCK_03DB_TABLE_SIZE_8710C] = {
-+	0x143,		/*0 ,    -4dB*/
-+	0x14C,		/*1 ,    -3.75dB*/
-+	0x156,		/*2 ,    -3.5dB*/
-+	0x160,
-+	0x16A,
-+	0x175,
-+	0x17F,
-+	0x18B,
-+	0x196,
-+	0x1A2,
-+	0x1AE,
-+	0x1BB,
-+	0x1C8,
-+	0x1D5,
-+	0x1E3,
-+	0x1F1,
-+	0x200,
-+	0x20F,
-+	0x21E,
-+	0x22F,
-+	0x23F,
-+	0x250,
-+	0x261,
-+	0x273,
-+	0x285,
-+	0x298,
-+	0x2AB,
-+	0x2BF,
-+	0x2D6,
-+	0x2E9,
-+	0x2FF,
-+	0x315,
-+	0x32C,
-+	0x344,
-+	0x35C,
-+	0x375,
-+	0x390,
-+	0x3AA,
-+	0x3C5,
-+	0x3E1,
-+	0x402,		/*40 ,    +6dB	default*/
-+	0x41C,
-+	0x43B,
-+	0x45A,
-+	0x47C,
-+	0x49C,
-+	0x4BF,
-+	0x4E2,
-+	0x510,
-+	0x52C,
-+	0x553,
-+	0x57B,
-+	0x5A5,
-+	0x5CE,
-+	0x5F9,
-+	0x626,
-+	0x655,
-+	0x683,
-+	0x6B5,
-+	0x6E6,
-+	0x71E,
-+	0x74E,
-+	0x786,
-+	0x7BD,
-+	0x7F9,
-+	0x832,
-+	0x871,
-+	0x8AF,
-+	0x8F2,
-+	0x932,
-+	0x977,
-+	0x9BE,
-+	0xA0E,
-+	0xA52,
-+	0xAA1,
-+	0xAEE,
-+	0xB54,
-+	0xB95,
-+	0xBEB,
-+	0xC43,
-+	0xCA3		/*80 ,    +16dB*/
-+};
-+
-+const u32 ofdm_swing_table_03DB_8710c[OFDM_03DB_TABLE_SIZE_8710C] = {
-+	0xE4,		/*0 ,    -7dB*/
-+	0xEB,		/*1 ,    -6.75dB*/
-+	0xF2,		/*2 ,    -6.5dB*/
-+	0xF9,
-+	0x100,
-+	0x108,
-+	0x110,
-+	0x118,
-+	0x11F,
-+	0x128,
-+	0x131,
-+	0x13A,
-+	0x143,
-+	0x14C,
-+	0x156,
-+	0x160,
-+	0x16A,
-+	0x175,
-+	0x180,
-+	0x18B,
-+	0x196,
-+	0x1A2,
-+	0x1AE,
-+	0x1BB,
-+	0x1C8,
-+	0x1D5,
-+	0x1E3,
-+	0x1F1,
-+	0x200,
-+	0x20F,
-+	0x21F,
-+	0x22F,
-+	0x23F,
-+	0x250,
-+	0x261,
-+	0x273,
-+	0x286,
-+	0x298,
-+	0x2AB,
-+	0x2BF,
-+	0x2D6,		/*40 ,    +3dB default*/
-+	0x2E9,
-+	0x2FF,
-+	0x315,
-+	0x32C,
-+	0x344,
-+	0x35C,
-+	0x375,
-+	0x390,
-+	0x3AA,
-+	0x3C5,
-+	0x3E1,
-+	0x3FF,
-+	0x41C,
-+	0x43B,
-+	0x45A,
-+	0x47B,
-+	0x49C,
-+	0x4BF,
-+	0x4E2,
-+	0x507,
-+	0x52C,
-+	0x553,
-+	0x57B,
-+	0x5A4,
-+	0x5CE,
-+	0x5F9,
-+	0x626,
-+	0x654,
-+	0x683,
-+	0x6B4,
-+	0x6E6,
-+	0x71B,
-+	0x74E,
-+	0x785,
-+	0x7BD,
-+	0x7F7,
-+	0x832,
-+	0x870,
-+	0x8AF,
-+	0x8F0		/*80 ,    +13dB*/
-+};
-+
-+
-+
-+const u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
-+	0x081, /* 0,  -12.0dB*/
-+	0x088, /* 1,  -11.5dB*/
-+	0x090, /* 2,  -11.0dB*/
-+	0x099, /* 3,  -10.5dB*/
-+	0x0A2, /* 4,  -10.0dB*/
-+	0x0AC, /* 5,  -9.5dB*/
-+	0x0B6, /* 6,  -9.0dB*/
-+	0x0C0, /*7,  -8.5dB*/
-+	0x0CC, /* 8,  -8.0dB*/
-+	0x0D8, /* 9,  -7.5dB*/
-+	0x0E5, /* 10, -7.0dB*/
-+	0x0F2, /* 11, -6.5dB*/
-+	0x101, /* 12, -6.0dB*/
-+	0x110, /* 13, -5.5dB*/
-+	0x120, /* 14, -5.0dB*/
-+	0x131, /* 15, -4.5dB*/
-+	0x143, /* 16, -4.0dB*/
-+	0x156, /* 17, -3.5dB*/
-+	0x16A, /* 18, -3.0dB*/
-+	0x180, /* 19, -2.5dB*/
-+	0x197, /* 20, -2.0dB*/
-+	0x1AF, /* 21, -1.5dB*/
-+	0x1C8, /* 22, -1.0dB*/
-+	0x1E3, /* 23, -0.5dB*/
-+	0x200, /* 24, +0  dB*/
-+	0x21E, /* 25, +0.5dB*/
-+	0x23E, /* 26, +1.0dB*/
-+	0x261, /* 27, +1.5dB*/
-+	0x285,/* 28, +2.0dB*/
-+	0x2AB, /* 29, +2.5dB*/
-+	0x2D3, /*30, +3.0dB*/
-+	0x2FE, /* 31, +3.5dB*/
-+	0x32B, /* 32, +4.0dB*/
-+	0x35C, /* 33, +4.5dB*/
-+	0x38E, /* 34, +5.0dB*/
-+	0x3C4, /* 35, +5.5dB*/
-+	0x3FE  /* 36, +6.0dB	*/
-+};
-+
-+void
-+odm_txpowertracking_init(
-+	void	*dm_void
-+)
-+{
-+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
-+
-+	odm_txpowertracking_thermal_meter_init(dm);
-+}
-+
-+u8
-+get_swing_index(
-+	void	*dm_void
-+)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	u8 i = 0;
-+	u32 bb_swing;
-+	u32 swing_table_size;
-+	u32 *swing_table;
-+	u32 table_value;
-+
-+#if (RTL8710C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8710C) {
-+		bb_swing = odm_get_bb_reg(dm, R_0xcc8, 0x000007ff);
-+
-+		for (i = 0; i < OFDM_03DB_TABLE_SIZE_8710C; i++) {
-+			if (bb_swing == ofdm_swing_table_03DB_8710c[i])
-+				break;
-+		}
-+	}
-+#elif (RTL8195B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8195B) {
-+		bb_swing = odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000);
-+		swing_table = (u32*)tx_scaling_table_jaguar;
-+		swing_table_size = TXSCALE_TABLE_SIZE;
-+
-+		for (i = 0; i < swing_table_size; i++) {
-+			table_value = swing_table[i];
-+
-+			table_value = table_value;
-+			if (bb_swing == table_value)
-+				break;
-+		}
-+	}
-+#endif
-+	return i;
-+}
-+
-+u8
-+get_cck_swing_index(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	u8 i = 0;
-+	u32 bb_cck_swing;
-+
-+#if (RTL8188E_SUPPORT == 1 || RTL8723B_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
-+	    dm->support_ic_type == ODM_RTL8192E) {
-+		bb_cck_swing = odm_read_1byte(dm, 0xa22);
-+
-+		for (i = 0; i < CCK_TABLE_SIZE; i++) {
-+			if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
-+				break;
-+		}
-+	}
-+#elif (RTL8703B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8703B) {
-+		bb_cck_swing = odm_read_1byte(dm, 0xa22);
-+
-+		for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
-+			if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
-+				break;
-+		}
-+	}
-+#elif (RTL8710C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8710C) {
-+		bb_cck_swing = odm_get_bb_reg(dm, R_0xab4, 0x7ff);
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "bb_cck_swing = 0x%x\n", bb_cck_swing);
-+
-+		for (i = 0; i < CCK_03DB_TABLE_SIZE_8710C; i++) {
-+			if (bb_cck_swing == cck_swing_table_03db_ch1_ch14_8710c[i])
-+				break;
-+		}
-+	}
-+#endif
-+
-+	return i;
-+}
-+
-+s8
-+get_txagc_default_index(
-+	void *dm_void
-+)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	s8 tmp;
-+
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		tmp = (s8)(odm_get_bb_reg(dm, R_0x18a0, 0x7f) & 0xff);
-+		if (tmp & BIT(6))
-+			tmp = tmp | 0x80;
-+		return tmp;
-+	} else
-+		return 0;
-+}
-+
-+void
-+odm_txpowertracking_thermal_meter_init(
-+	void	*dm_void
-+)
-+{
-+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
-+	u8 default_swing_index;
-+	u8 p = 0;
-+	struct dm_rf_calibration_struct	*cali_info = &dm->rf_calibrate_info;
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+
-+	if (!(*dm->mp_mode))
-+		cali_info->txpowertrack_control = true;
-+	else
-+		cali_info->txpowertrack_control = false;
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "dm txpowertrack_control = %d\n", cali_info->txpowertrack_control);
-+
-+	/* dm->rf_calibrate_info.txpowertrack_control = true; */
-+	cali_info->thermal_value = rf->eeprom_thermal;
-+	cali_info->thermal_value_iqk = rf->eeprom_thermal;
-+	cali_info->thermal_value_lck = rf->eeprom_thermal;
-+
-+	if (!cali_info->default_bb_swing_index_flag) {
-+		if (dm->support_ic_type == ODM_RTL8195B) {
-+			default_swing_index = get_swing_index(dm);
-+			cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
-+			cali_info->default_cck_index = 24;
-+		} else if (dm->support_ic_type == ODM_RTL8721D) {
-+			cali_info->default_ofdm_index = 28;	/*OFDM: -1dB*/
-+			cali_info->default_cck_index = 28;	/*CCK: -6dB*/
-+		} else if (dm->support_ic_type == ODM_RTL8710C) {
-+			cali_info->default_ofdm_index = get_swing_index(dm);
-+			cali_info->default_cck_index = get_cck_swing_index(dm);
-+		}
-+		cali_info->default_bb_swing_index_flag = true;
-+	}
-+
-+	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
-+	cali_info->CCK_index = cali_info->default_cck_index;
-+
-+	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
-+		cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
-+		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
-+		cali_info->delta_power_index[p] = 0;
-+		cali_info->delta_power_index_last[p] = 0;
-+		cali_info->power_index_offset[p] = 0;
-+	}
-+	cali_info->modify_tx_agc_value_ofdm = 0;
-+	cali_info->modify_tx_agc_value_cck = 0;
-+	cali_info->tm_trigger = 0;
-+}
-+
-+void
-+odm_txpowertracking_check(
-+	void	*dm_void
-+)
-+{
-+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
-+
-+	odm_txpowertracking_check_iot(dm);
-+}
-+
-+void
-+odm_txpowertracking_check_iot(
-+	void	*dm_void
-+)
-+{
-+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_		*rf = &dm->rf_table;
-+
-+	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
-+		return;
-+
-+	if (!dm->rf_calibrate_info.tm_trigger) {
-+		if (dm->support_ic_type == ODM_RTL8195B)
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);
-+		else if (dm->support_ic_type == ODM_RTL8721D ||
-+			dm->support_ic_type == ODM_RTL8710C)
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW,
-+				       (BIT(12) | BIT(11)), 0x03);
-+
-+		dm->rf_calibrate_info.tm_trigger = 1;
-+		return;
-+	}
-+	odm_txpowertracking_callback_thermal_meter(dm);
-+	dm->rf_calibrate_info.tm_trigger = 0;
-+}
-+
-+void
-+odm_txpowertracking_check_mp(
-+	void	*dm_void
-+)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	void	*adapter = dm->adapter;
-+
-+	if (odm_check_power_status(adapter) == false) {
-+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status, return false\n"));
-+		return;
-+	}
-+
-+	odm_txpowertracking_thermal_meter_check(adapter);
-+#endif
-+}
-+
-+void
-+odm_txpowertracking_check_ap(
-+	void	*dm_void
-+)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	struct rtl8192cd_priv	*priv		= dm->priv;
-+
-+	return;
-+
-+#endif
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_iot.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_iot.h
-new file mode 100644
-index 000000000000..431890bb8cea
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_iot.h
-@@ -0,0 +1,372 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_POWERTRACKING_H__
-+#define __HALRF_POWERTRACKING_H__
-+
-+#define		DPK_DELTA_MAPPING_NUM	13
-+#define		index_mapping_HP_NUM	15
-+#define	OFDM_TABLE_SIZE	43
-+#define	CCK_TABLE_SIZE			33
-+#define	CCK_TABLE_SIZE_88F	21
-+#define TXSCALE_TABLE_SIZE		37
-+#define CCK_TABLE_SIZE_8723D	41
-+/* JJ ADD 20161014 */
-+#define CCK_TABLE_SIZE_8710B	41
-+#define	CCK_TABLE_SIZE_8192F   41
-+#define	CCK_TABLE_SIZE_8721D   41
-+#define	CCK_TABLE_SIZE_8710C   41
-+#define	CCK_03DB_TABLE_SIZE_8710C   81
-+#define	OFDM_03DB_TABLE_SIZE_8710C	81
-+
-+
-+#define TXPWR_TRACK_TABLE_SIZE	30
-+#define DELTA_SWINGIDX_SIZE     30
-+#define DELTA_SWINTSSI_SIZE     61
-+#define BAND_NUM				4
-+
-+#define AVG_THERMAL_NUM		8
-+#define IQK_MAC_REG_NUM		4
-+#define IQK_ADDA_REG_NUM		16
-+#define IQK_BB_REG_NUM_MAX	10
-+
-+#define IQK_BB_REG_NUM		9
-+
-+
-+
-+#define iqk_matrix_reg_num	8
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+#else
-+#define IQK_MATRIX_SETTINGS_NUM	(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
-+#endif
-+
-+extern const u32 ofdm_swing_table[OFDM_TABLE_SIZE];
-+extern const u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
-+extern const u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
-+
-+extern const u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
-+extern const u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
-+extern const u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
-+extern const u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
-+extern const u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
-+extern const u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
-+extern const u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
-+/* JJ ADD 20161014 */
-+extern const u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
-+extern const u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
-+extern const u32 cck_swing_table_ch1_ch14_8721d[CCK_TABLE_SIZE_8721D];
-+extern const u32 cck_swing_table_ch1_ch14_8710c[CCK_TABLE_SIZE_8710C];
-+extern const u32 cck_swing_table_03db_ch1_ch14_8710c[CCK_03DB_TABLE_SIZE_8710C];
-+extern const u32 ofdm_swing_table_03DB_8710c[OFDM_03DB_TABLE_SIZE_8710C];
-+
-+extern const u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
-+
-+/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+#else
-+static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};
-+static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};
-+#endif
-+
-+void
-+odm_txpowertracking_init(
-+	void		*dm_void
-+);
-+
-+#define dm_check_txpowertracking	odm_txpowertracking_check
-+
-+struct iqk_matrix_regs_setting {
-+	boolean	is_iqk_done;
-+	s32		value[3][iqk_matrix_reg_num];
-+	boolean	is_bw_iqk_result_saved[3];
-+};
-+
-+struct dm_rf_calibration_struct {
-+	/* for tx power tracking */
-+
-+	u32	rega24; /* for TempCCK */
-+	s32	rege94;
-+	s32	rege9c;
-+	s32	regeb4;
-+	s32	regebc;
-+
-+	u8	tx_powercount;
-+	boolean is_txpowertracking_init;
-+	boolean is_txpowertracking;
-+	u8  	txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
-+	u8	tm_trigger;
-+	u8  	internal_pa_5g[2];	/* pathA / pathB */
-+
-+	u8  	thermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
-+	u8	thermal_value;
-+	u8	thermal_value_lck;
-+	u8	thermal_value_iqk;
-+	s8  	thermal_value_delta; /* delta of thermal_value and efuse thermal */
-+	u8	thermal_value_dpk;
-+	u8	thermal_value_avg[AVG_THERMAL_NUM];
-+	u8	thermal_value_avg_index;
-+	u8	thermal_value_rx_gain;
-+	u8	thermal_value_crystal;
-+	u8	thermal_value_dpk_store;
-+	u8	thermal_value_dpk_track;
-+	boolean	txpowertracking_in_progress;
-+
-+	boolean	is_reloadtxpowerindex;
-+	u8	is_rf_pi_enable;
-+	u32 	txpowertracking_callback_cnt; /* cosa add for debug */
-+
-+
-+	/* ------------------------- Tx power Tracking ------------------------- */
-+	u8	is_cck_in_ch14;
-+	u8	CCK_index;
-+	u8	OFDM_index[MAX_RF_PATH];
-+	s8	power_index_offset[MAX_RF_PATH];
-+	s8	delta_power_index[MAX_RF_PATH];
-+	s8	delta_power_index_last[MAX_RF_PATH];
-+	boolean is_tx_power_changed;
-+	s8	xtal_offset;
-+	s8	xtal_offset_last;
-+
-+#if (RTL8710B_SUPPORT == 1 || RTL8721D_SUPPORT == 1)
-+	struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
-+#endif
-+	u8	delta_lck;
-+	s8  bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
-+	u8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	u8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
-+#endif
-+	u8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	u8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
-+#endif
-+
-+#if (RTL8195B_SUPPORT == 1)
-+	u8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+#endif
-+
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	u8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+#endif
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	u8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+#endif
-+	s8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
-+	s8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
-+
-+	u8			bb_swing_idx_ofdm[MAX_RF_PATH];
-+	u8			bb_swing_idx_ofdm_current;
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
-+	u8			bb_swing_idx_ofdm_base[MAX_RF_PATH];
-+#else
-+	u8			bb_swing_idx_ofdm_base;
-+#endif
-+	boolean		default_bb_swing_index_flag;
-+	boolean			bb_swing_flag_ofdm;
-+	u8			bb_swing_idx_cck;
-+	u8			bb_swing_idx_cck_current;
-+	u8			bb_swing_idx_cck_base;
-+	u8			default_ofdm_index;
-+	u8			default_cck_index;
-+	s8			default_txagc_index;
-+	boolean			bb_swing_flag_cck;
-+
-+	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
-+	s8			remnant_ofdm_swing_idx[MAX_RF_PATH];
-+	s8			absolute_cck_swing_idx[MAX_RF_PATH];
-+	s8			remnant_cck_swing_idx;
-+	s8			modify_tx_agc_value;       /*Remnat compensate value at tx_agc */
-+	boolean			modify_tx_agc_flag_path_a;
-+	boolean			modify_tx_agc_flag_path_b;
-+	boolean			modify_tx_agc_flag_path_c;
-+	boolean			modify_tx_agc_flag_path_d;
-+	boolean			modify_tx_agc_flag_path_a_cck;
-+	boolean			modify_tx_agc_flag_path_b_cck;
-+
-+	s8			kfree_offset[MAX_RF_PATH];
-+
-+	/* -------------------------------------------------------------------- */
-+
-+	/* for IQK */
-+	u32	regc04;
-+	u32	reg874;
-+	u32	regc08;
-+	u32	regb68;
-+	u32	regb6c;
-+	u32	reg870;
-+	u32	reg860;
-+	u32	reg864;
-+
-+	boolean	is_iqk_initialized;
-+	boolean is_lck_in_progress;
-+	boolean	is_antenna_detected;
-+	boolean	is_need_iqk;
-+	boolean	is_iqk_in_progress;
-+	boolean is_iqk_pa_off;
-+	u8	delta_iqk;
-+	u32	ADDA_backup[IQK_ADDA_REG_NUM];
-+	u32	IQK_MAC_backup[IQK_MAC_REG_NUM];
-+	u32	IQK_BB_backup_recover[9];
-+	u32	IQK_BB_backup[IQK_BB_REG_NUM];
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	u32 	tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
-+	u32 	rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
-+	u32	tx_iqc_8703b[3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
-+	u32	rx_iqc_8703b[2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
-+	u32	tx_iqc_8723d[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
-+	u32	rx_iqc_8723d[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
-+#endif
-+	/* JJ ADD 20161014 */
-+	u32	tx_iqc_8710b[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
-+	u32	rx_iqc_8710b[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
-+
-+	u8	iqk_step;
-+	u8	kcount;
-+	u8	retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
-+	boolean	is_mp_mode;
-+
-+
-+
-+	/* <James> IQK time measurement */
-+	u32	iqk_start_time;
-+	u32	iqk_progressing_time;
-+	u32	iqk_total_progressing_time;
-+	u32	lck_progressing_time;
-+
-+	u32  lok_result;
-+
-+	/* for APK */
-+	u32 	ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
-+	u8	is_ap_kdone;
-+	u8	is_apk_thermal_meter_ignore;
-+
-+	/* DPK */
-+	boolean is_dpk_fail;
-+	u8	is_dp_done;
-+	u8	is_dp_path_aok;
-+	u8	is_dp_path_bok;
-+
-+	u32	tx_lok[2];
-+	u32  dpk_tx_agc;
-+	s32  dpk_gain;
-+	u32  dpk_thermal[4];
-+	s8 modify_tx_agc_value_ofdm;
-+	s8 modify_tx_agc_value_cck;
-+
-+	/*Add by Yuchen for Kfree Phydm*/
-+	u8			reg_rf_kfree_enable;	/*for registry*/
-+	u8			rf_kfree_enable;		/*for efuse enable check*/
-+
-+};
-+
-+
-+void
-+odm_txpowertracking_check(
-+	void		*dm_void
-+);
-+
-+void
-+odm_txpowertracking_check_ap(
-+	void		*dm_void
-+);
-+
-+void
-+odm_txpowertracking_thermal_meter_init(
-+	void		*dm_void
-+);
-+
-+
-+void
-+odm_txpowertracking_check_mp(
-+	void		*dm_void
-+);
-+
-+
-+void
-+odm_txpowertracking_check_iot(
-+	void		*dm_void
-+);
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+
-+void
-+odm_txpowertracking_callback_thermal_meter92c(
-+	void	*adapter
-+);
-+
-+void
-+odm_txpowertracking_callback_rx_gain_thermal_meter92d(
-+	void	*adapter
-+);
-+
-+void
-+odm_txpowertracking_callback_thermal_meter92d(
-+	void	*adapter
-+);
-+
-+void
-+odm_txpowertracking_direct_call92c(
-+	void		*adapter
-+);
-+
-+void
-+odm_txpowertracking_thermal_meter_check(
-+	void		*adapter
-+);
-+
-+#endif
-+
-+#endif	/*#ifndef __HALRF_POWER_TRACKING_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_win.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_win.c
-new file mode 100644
-index 000000000000..5cb9542574e7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_win.c
-@@ -0,0 +1,924 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/*============================================================	*/
-+/* include files												*/
-+/*============================================================	*/
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+/* ************************************************************
-+ * Global var
-+ * ************************************************************ */
-+
-+u32	ofdm_swing_table[OFDM_TABLE_SIZE] = {
-+	0x7f8001fe,	/* 0, +6.0dB */
-+	0x788001e2,	/* 1, +5.5dB */
-+	0x71c001c7,	/* 2, +5.0dB */
-+	0x6b8001ae,	/* 3, +4.5dB */
-+	0x65400195,	/* 4, +4.0dB */
-+	0x5fc0017f,	/* 5, +3.5dB */
-+	0x5a400169,	/* 6, +3.0dB */
-+	0x55400155,	/* 7, +2.5dB */
-+	0x50800142,	/* 8, +2.0dB */
-+	0x4c000130,	/* 9, +1.5dB */
-+	0x47c0011f,	/* 10, +1.0dB */
-+	0x43c0010f,	/* 11, +0.5dB */
-+	0x40000100,	/* 12, +0dB */
-+	0x3c8000f2,	/* 13, -0.5dB */
-+	0x390000e4,	/* 14, -1.0dB */
-+	0x35c000d7,	/* 15, -1.5dB */
-+	0x32c000cb,	/* 16, -2.0dB */
-+	0x300000c0,	/* 17, -2.5dB */
-+	0x2d4000b5,	/* 18, -3.0dB */
-+	0x2ac000ab,	/* 19, -3.5dB */
-+	0x288000a2,	/* 20, -4.0dB */
-+	0x26000098,	/* 21, -4.5dB */
-+	0x24000090,	/* 22, -5.0dB */
-+	0x22000088,	/* 23, -5.5dB */
-+	0x20000080,	/* 24, -6.0dB */
-+	0x1e400079,	/* 25, -6.5dB */
-+	0x1c800072,	/* 26, -7.0dB */
-+	0x1b00006c,	/* 27. -7.5dB */
-+	0x19800066,	/* 28, -8.0dB */
-+	0x18000060,	/* 29, -8.5dB */
-+	0x16c0005b,	/* 30, -9.0dB */
-+	0x15800056,	/* 31, -9.5dB */
-+	0x14400051,	/* 32, -10.0dB */
-+	0x1300004c,	/* 33, -10.5dB */
-+	0x12000048,	/* 34, -11.0dB */
-+	0x11000044,	/* 35, -11.5dB */
-+	0x10000040,	/* 36, -12.0dB */
-+};
-+
-+u8	cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
-+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},	/* 0, +0dB */
-+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 1, -0.5dB */
-+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 2, -1.0dB */
-+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 3, -1.5dB */
-+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 4, -2.0dB */
-+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 5, -2.5dB */
-+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 6, -3.0dB */
-+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 7, -3.5dB */
-+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 8, -4.0dB */
-+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 9, -4.5dB */
-+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 10, -5.0dB */
-+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 11, -5.5dB */
-+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/* 12, -6.0dB <== default */
-+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 13, -6.5dB */
-+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 14, -7.0dB */
-+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 15, -7.5dB */
-+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
-+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 17, -8.5dB */
-+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 18, -9.0dB */
-+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 19, -9.5dB */
-+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 20, -10.0dB */
-+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 21, -10.5dB */
-+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 22, -11.0dB */
-+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 23, -11.5dB */
-+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 24, -12.0dB */
-+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 25, -12.5dB */
-+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 26, -13.0dB */
-+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 27, -13.5dB */
-+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 28, -14.0dB */
-+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 29, -14.5dB */
-+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 30, -15.0dB */
-+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 31, -15.5dB */
-+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}	/* 32, -16.0dB */
-+};
-+
-+
-+u8	cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
-+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},	/* 0, +0dB */
-+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 1, -0.5dB */
-+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 2, -1.0dB */
-+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 3, -1.5dB */
-+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 4, -2.0dB */
-+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 5, -2.5dB */
-+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 6, -3.0dB */
-+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 7, -3.5dB */
-+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 8, -4.0dB */
-+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 9, -4.5dB */
-+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 10, -5.0dB */
-+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 11, -5.5dB */
-+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 12, -6.0dB  <== default */
-+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 13, -6.5dB */
-+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 14, -7.0dB */
-+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 15, -7.5dB */
-+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
-+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 17, -8.5dB */
-+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 18, -9.0dB */
-+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 19, -9.5dB */
-+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 20, -10.0dB */
-+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 21, -10.5dB */
-+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 22, -11.0dB */
-+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 23, -11.5dB */
-+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 24, -12.0dB */
-+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 25, -12.5dB */
-+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 26, -13.0dB */
-+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 27, -13.5dB */
-+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 28, -14.0dB */
-+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 29, -14.5dB */
-+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 30, -15.0dB */
-+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 31, -15.5dB */
-+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}	/* 32, -16.0dB */
-+};
-+
-+
-+u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
-+	0x0b40002d, /* 0,  -15.0dB */
-+	0x0c000030, /* 1,  -14.5dB */
-+	0x0cc00033, /* 2,  -14.0dB */
-+	0x0d800036, /* 3,  -13.5dB */
-+	0x0e400039, /* 4,  -13.0dB */
-+	0x0f00003c, /* 5,  -12.5dB */
-+	0x10000040, /* 6,  -12.0dB */
-+	0x11000044, /* 7,  -11.5dB */
-+	0x12000048, /* 8,  -11.0dB */
-+	0x1300004c, /* 9,  -10.5dB */
-+	0x14400051, /* 10, -10.0dB */
-+	0x15800056, /* 11, -9.5dB */
-+	0x16c0005b, /* 12, -9.0dB */
-+	0x18000060, /* 13, -8.5dB */
-+	0x19800066, /* 14, -8.0dB */
-+	0x1b00006c, /* 15, -7.5dB */
-+	0x1c800072, /* 16, -7.0dB */
-+	0x1e400079, /* 17, -6.5dB */
-+	0x20000080, /* 18, -6.0dB */
-+	0x22000088, /* 19, -5.5dB */
-+	0x24000090, /* 20, -5.0dB */
-+	0x26000098, /* 21, -4.5dB */
-+	0x288000a2, /* 22, -4.0dB */
-+	0x2ac000ab, /* 23, -3.5dB */
-+	0x2d4000b5, /* 24, -3.0dB */
-+	0x300000c0, /* 25, -2.5dB */
-+	0x32c000cb, /* 26, -2.0dB */
-+	0x35c000d7, /* 27, -1.5dB */
-+	0x390000e4, /* 28, -1.0dB */
-+	0x3c8000f2, /* 29, -0.5dB */
-+	0x40000100, /* 30, +0dB */
-+	0x43c0010f, /* 31, +0.5dB */
-+	0x47c0011f, /* 32, +1.0dB */
-+	0x4c000130, /* 33, +1.5dB */
-+	0x50800142, /* 34, +2.0dB */
-+	0x55400155, /* 35, +2.5dB */
-+	0x5a400169, /* 36, +3.0dB */
-+	0x5fc0017f, /* 37, +3.5dB */
-+	0x65400195, /* 38, +4.0dB */
-+	0x6b8001ae, /* 39, +4.5dB */
-+	0x71c001c7, /* 40, +5.0dB */
-+	0x788001e2, /* 41, +5.5dB */
-+	0x7f8001fe  /* 42, +6.0dB */
-+};
-+
-+
-+u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
-+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
-+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
-+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
-+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
-+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
-+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
-+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
-+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
-+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
-+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
-+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
-+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
-+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
-+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
-+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
-+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
-+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
-+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
-+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
-+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
-+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
-+};
-+
-+
-+u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
-+	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
-+	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
-+	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
-+	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14.5dB*/
-+	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
-+	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
-+	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
-+	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
-+	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
-+	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
-+	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
-+	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
-+	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
-+	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
-+	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
-+	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
-+	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
-+	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
-+	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
-+	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
-+	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
-+};
-+
-+
-+u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
-+	{0x44,	 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-16dB*/
-+	{0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15.5dB*/
-+	{0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-15dB*/
-+	{0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},	    /*-14.5dB*/
-+	{0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-14dB*/
-+	{0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13.5dB*/
-+	{0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-13dB*/
-+	{0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12.5dB*/
-+	{0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-12dB*/
-+	{0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11.5dB*/
-+	{0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-11dB*/
-+	{0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10.5dB*/
-+	{0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-10dB*/
-+	{0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9.5dB*/
-+	{0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-9dB*/
-+	{0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8.5dB*/
-+	{0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-8dB*/
-+	{0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7.5dB*/
-+	{0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-7dB*/
-+	{0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    /*-6.5dB*/
-+	{0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}     /*-6dB*/
-+};
-+
-+
-+u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
-+	{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},	/* 0, -16.0dB */
-+	{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},	/* 1, -15.5dB */
-+	{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 2, -15.0dB */
-+	{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},	/* 3, -14.5dB */
-+	{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 4, -14.0dB */
-+	{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},	/* 5, -13.5dB */
-+	{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},	/* 6, -13.0dB */
-+	{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},	/* 7, -12.5dB */
-+	{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},	/* 8, -12.0dB */
-+	{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},	/* 9, -11.5dB */
-+	{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 10, -11.0dB */
-+	{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},	/* 11, -10.5dB */
-+	{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 12, -10.0dB */
-+	{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},	/* 13, -9.5dB */
-+	{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},	/* 14, -9.0dB */
-+	{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},	/* 15, -8.5dB */
-+	{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},	/* 16, -8.0dB */
-+	{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},	/* 17, -7.5dB */
-+	{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},	/* 18, -7.0dB */
-+	{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},	/* 19, -6.5dB */
-+	{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},	/* 20, -6.0dB */
-+	{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},	/* 21, -5.5dB */
-+	{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},	/* 22, -5.0dB */
-+	{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},	/* 23, -4.5dB */
-+	{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},	/* 24, -4.0dB */
-+	{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},	/* 25, -3.5dB */
-+	{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},	/* 26, -3.0dB */
-+	{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},	/* 27, -2.5dB */
-+	{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},	/* 28, -2.0dB */
-+	{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},	/* 29, -1.5dB */
-+	{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},	/* 30, -1.0dB */
-+	{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},	/* 31, -0.5dB */
-+	{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}	/* 32, +0dB */
-+};
-+
-+
-+u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
-+	{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},	/* 0, -16.0dB */
-+	{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 1, -15.5dB */
-+	{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 2, -15.0dB */
-+	{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 3, -14.5dB */
-+	{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},	/* 4, -14.0dB */
-+	{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 5, -13.5dB */
-+	{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 6, -13.0dB */
-+	{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},	/* 7, -12.5dB */
-+	{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 8, -12.0dB */
-+	{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},	/* 9, -11.5dB */
-+	{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 10, -11.0dB */
-+	{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},	/* 11, -10.5dB */
-+	{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 12, -10.0dB */
-+	{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},	/* 13, -9.5dB */
-+	{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 14, -9.0dB */
-+	{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},	/* 15, -8.5dB */
-+	{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 16, -8.0dB */
-+	{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},	/* 17, -7.5dB */
-+	{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},	/* 18, -7.0dB */
-+	{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},	/* 19, -6.5dB */
-+	{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 20, -6.0dB */
-+	{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},	/* 21, -5.5dB */
-+	{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},	/* 22, -5.0dB */
-+	{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},	/* 23, -4.5dB */
-+	{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},	/* 24, -4.0dB */
-+	{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},	/* 25, -3.5dB */
-+	{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},	/* 26, -3.0dB */
-+	{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},	/* 27, -2.5dB */
-+	{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},	/* 28, -2.0dB */
-+	{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},	/* 29, -1.5dB */
-+	{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},	/* 30, -1.0dB */
-+	{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},	/* 31, -0.5dB */
-+	{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}	/* 32, +0dB */
-+};
-+u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
-+	0x0CD,
-+	0x0D9,
-+	0x0E6,
-+	0x0F3,
-+	0x102,
-+	0x111,
-+	0x121,
-+	0x132,
-+	0x144,
-+	0x158,
-+	0x16C,
-+	0x182,
-+	0x198,
-+	0x1B1,
-+	0x1CA,
-+	0x1E5,
-+	0x202,
-+	0x221,
-+	0x241,
-+	0x263,
-+	0x287,
-+	0x2AE,
-+	0x2D6,
-+	0x301,
-+	0x32F,
-+	0x35F,
-+	0x392,
-+	0x3C9,
-+	0x402,
-+	0x43F,
-+	0x47F,
-+	0x4C3,
-+	0x50C,
-+	0x558,
-+	0x5A9,
-+	0x5FF,
-+	0x65A,
-+	0x6BA,
-+	0x720,
-+	0x78C,
-+	0x7FF,
-+};
-+/* JJ ADD 20161014 */
-+u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
-+	0x0CD,			 /*0 ,    -20dB*/
-+	0x0D9,
-+	0x0E6,
-+	0x0F3,
-+	0x102,
-+	0x111,
-+	0x121,
-+	0x132,
-+	0x144,
-+	0x158,
-+	0x16C,
-+	0x182,
-+	0x198,
-+	0x1B1,
-+	0x1CA,
-+	0x1E5,
-+	0x202,
-+	0x221,
-+	0x241,
-+	0x263,		/*19*/
-+	0x287,		/*20*/
-+	0x2AE,		/*21*/
-+	0x2D6,		/*22*/
-+	0x301,		/*23*/
-+	0x32F,		/*24*/
-+	0x35F,		/*25*/
-+	0x392,		/*26*/
-+	0x3C9,		/*27*/
-+	0x402,		/*28*/
-+	0x43F,		/*29*/
-+	0x47F,		/*30*/
-+	0x4C3,		/*31*/
-+	0x50C,		/*32*/
-+	0x558,		/*33*/
-+	0x5A9,		/*34*/
-+	0x5FF,		/*35*/
-+	0x65A,		/*36*/
-+	0x6BA,
-+	0x720,
-+	0x78C,
-+	0x7FF,
-+};
-+
-+/* Winnita ADD 20170828 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/
-+u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = {
-+	0x0CD,			 /*0 ,    -20dB*/
-+	0x0D9,
-+	0x0E6,
-+	0x0F3,
-+	0x102,
-+	0x111,
-+	0x121,
-+	0x132,
-+	0x144,
-+	0x158,
-+	0x16C,
-+	0x182,
-+	0x198,
-+	0x1B1,
-+	0x1CA,
-+	0x1E5,
-+	0x202,
-+	0x221,
-+	0x241,
-+	0x263,		/*19*/
-+	0x287,		/*20*/
-+	0x2AE,		/*21*/
-+	0x2D6,		/*22*/
-+	0x301,		/*23*/
-+	0x32F,		/*24*/
-+	0x35F,		/*25*/
-+	0x392,		/*26*/
-+	0x3C9,		/*27*/
-+	0x402,		/*28*/
-+	0x43F,		/*29*/
-+	0x47F,		/*30*/
-+	0x4C3,		/*31*/
-+	0x50C,		/*32*/
-+	0x558,		/*33*/
-+	0x5A9,		/*34*/
-+	0x5FF,		/*35*/
-+	0x65A,		/*36*/
-+	0x6BA,
-+	0x720,
-+	0x78C,
-+	0x7FF,
-+};
-+
-+u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
-+	0x081, /* 0,  -12.0dB */
-+	0x088, /* 1,  -11.5dB */
-+	0x090, /* 2,  -11.0dB */
-+	0x099, /* 3,  -10.5dB */
-+	0x0A2, /* 4,  -10.0dB */
-+	0x0AC, /* 5,  -9.5dB */
-+	0x0B6, /* 6,  -9.0dB */
-+	0x0C0, /* 7,  -8.5dB */
-+	0x0CC, /* 8,  -8.0dB */
-+	0x0D8, /* 9,  -7.5dB */
-+	0x0E5, /* 10, -7.0dB */
-+	0x0F2, /* 11, -6.5dB */
-+	0x101, /* 12, -6.0dB */
-+	0x110, /* 13, -5.5dB */
-+	0x120, /* 14, -5.0dB */
-+	0x131, /* 15, -4.5dB */
-+	0x143, /* 16, -4.0dB */
-+	0x156, /* 17, -3.5dB */
-+	0x16A, /* 18, -3.0dB */
-+	0x180, /* 19, -2.5dB */
-+	0x197, /* 20, -2.0dB */
-+	0x1AF, /* 21, -1.5dB */
-+	0x1C8, /* 22, -1.0dB */
-+	0x1E3, /* 23, -0.5dB */
-+	0x200, /* 24, +0  dB */
-+	0x21E, /* 25, +0.5dB */
-+	0x23E, /* 26, +1.0dB */
-+	0x261, /* 27, +1.5dB */
-+	0x285, /* 28, +2.0dB */
-+	0x2AB, /* 29, +2.5dB */
-+	0x2D3, /* 30, +3.0dB */
-+	0x2FE, /* 31, +3.5dB */
-+	0x32B, /* 32, +4.0dB */
-+	0x35C, /* 33, +4.5dB */
-+	0x38E, /* 34, +5.0dB */
-+	0x3C4, /* 35, +5.5dB */
-+	0x3FE  /* 36, +6.0dB */
-+};
-+
-+void
-+odm_txpowertracking_init(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))
-+		return;
-+#endif
-+
-+	odm_txpowertracking_thermal_meter_init(dm);
-+}
-+
-+u8
-+get_swing_index(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	void		*adapter = dm->adapter;
-+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	u8			i = 0;
-+	u32			bb_swing, table_value;
-+
-+	if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
-+	    dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8188F || 
-+	    dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || 
-+	    dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B) {
-+		bb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
-+
-+		for (i = 0; i < OFDM_TABLE_SIZE; i++) {
-+			table_value = ofdm_swing_table_new[i];
-+
-+			if (table_value >= 0x100000)
-+				table_value >>= 22;
-+			if (bb_swing == table_value)
-+				break;
-+		}
-+	} else {
-+		bb_swing = PHY_GetTxBBSwing_8812A(adapter, hal_data->CurrentBandType, RF_PATH_A);
-+
-+		for (i = 0; i < TXSCALE_TABLE_SIZE; i++) {
-+			table_value = tx_scaling_table_jaguar[i];
-+
-+			if (bb_swing == table_value)
-+				break;
-+		}
-+	}
-+
-+	return i;
-+}
-+
-+u8
-+get_cck_swing_index(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+
-+	u8			i = 0;
-+	u32			bb_cck_swing;
-+
-+	if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
-+	    dm->support_ic_type == ODM_RTL8192E) {
-+		bb_cck_swing = odm_read_1byte(dm, 0xa22);
-+
-+		for (i = 0; i < CCK_TABLE_SIZE; i++) {
-+			if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
-+				break;
-+		}
-+	} else if (dm->support_ic_type == ODM_RTL8703B) {
-+		bb_cck_swing = odm_read_1byte(dm, 0xa22);
-+
-+		for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
-+			if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
-+				break;
-+		}
-+	}
-+
-+	return i;
-+}
-+
-+s8
-+get_txagc_default_index(
-+	void *dm_void
-+)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	s8 tmp;
-+
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		tmp = (s8)(odm_get_bb_reg(dm, R_0x18a0, 0x7f) & 0xff);
-+		if (tmp & BIT(6))
-+			tmp = tmp | 0x80;
-+		return tmp;
-+	} else
-+		return 0;
-+}
-+
-+void
-+odm_txpowertracking_thermal_meter_init(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	u8 default_swing_index = get_swing_index(dm);
-+	u8 default_cck_swing_index = get_cck_swing_index(dm);
-+	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void		*adapter = dm->adapter;
-+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	u8			p = 0;
-+
-+	if (*(dm->mp_mode) == false)
-+		cali_info->txpowertrack_control = true;
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+#ifdef CONFIG_RTL8188E
-+	{
-+		cali_info->is_txpowertracking = true;
-+		cali_info->tx_powercount = 0;
-+		cali_info->is_txpowertracking_init = false;
-+
-+		if (*(dm->mp_mode) == false)
-+			cali_info->txpowertrack_control = true;
-+
-+		MSG_8192C("dm txpowertrack_control = %d\n", cali_info->txpowertrack_control);
-+	}
-+#else
-+	{
-+		void		*adapter = dm->adapter;
-+		HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+		struct dm_priv	*pdmpriv = &hal_data->dmpriv;
-+
-+		pdmpriv->is_txpowertracking = true;
-+		pdmpriv->tx_powercount = 0;
-+		pdmpriv->is_txpowertracking_init = false;
-+
-+		if (*(dm->mp_mode) == false)
-+			pdmpriv->txpowertrack_control = true;
-+
-+		MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control);
-+
-+	}
-+#endif
-+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+#ifdef RTL8188E_SUPPORT
-+	{
-+		cali_info->is_txpowertracking = true;
-+		cali_info->tx_powercount = 0;
-+		cali_info->is_txpowertracking_init = false;
-+		cali_info->txpowertrack_control = true;
-+	}
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#if (MP_DRIVER == 1)
-+	cali_info->txpowertrack_control = false;
-+#else
-+	cali_info->txpowertrack_control = true;
-+#endif
-+#else
-+	cali_info->txpowertrack_control = true;
-+#endif
-+
-+	cali_info->thermal_value	= hal_data->eeprom_thermal_meter;
-+	cali_info->thermal_value_iqk	= hal_data->eeprom_thermal_meter;
-+	cali_info->thermal_value_lck	= hal_data->eeprom_thermal_meter;
-+
-+#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8822C) {
-+		cali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];
-+		cali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];
-+		cali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];
-+		cali_info->thermal_value_lck = tssi->thermal[RF_PATH_A];
-+	}
-+
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		cali_info->thermal_value_path[RF_PATH_A] = tssi->thermal[RF_PATH_A];
-+		cali_info->thermal_value_path[RF_PATH_B] = tssi->thermal[RF_PATH_B];
-+		cali_info->thermal_value_path[RF_PATH_C] = tssi->thermal[RF_PATH_C];
-+		cali_info->thermal_value_path[RF_PATH_D] = tssi->thermal[RF_PATH_D];
-+		cali_info->thermal_value_iqk = tssi->thermal[RF_PATH_A];
-+		cali_info->thermal_value_lck = tssi->thermal[RF_PATH_A];
-+	}
-+#endif
-+
-+	if (cali_info->default_bb_swing_index_flag != true) {
-+		/*The index of "0 dB" in SwingTable.*/
-+		if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
-+		    dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B) {
-+			cali_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
-+			cali_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index;
-+		} else if (dm->support_ic_type == ODM_RTL8188F) {          /*add by Mingzhi.Guo  2015-03-23*/
-+			cali_info->default_ofdm_index = 28;							/*OFDM: -1dB*/
-+			cali_info->default_cck_index = 20;							/*CCK:-6dB*/
-+		} else if (dm->support_ic_type == ODM_RTL8723D) {			 /*add by zhaohe  2015-10-27*/
-+			cali_info->default_ofdm_index = 28;						 	   /*OFDM: -1dB*/
-+			cali_info->default_cck_index = 28;							/*CCK:   -6dB*/
-+			/* JJ ADD 20161014 */
-+		} else if (dm->support_ic_type == ODM_RTL8710B) {			
-+			cali_info->default_ofdm_index = 28;					/*OFDM: -1dB*/
-+			cali_info->default_cck_index = 28;					/*CCK:   -6dB*/
-+		/*Winnita add 20170828*/
-+		} else if (dm->support_ic_type == ODM_RTL8192F) {			
-+			cali_info->default_ofdm_index = 30;					/*OFDM: 0dB*/
-+			cali_info->default_cck_index = 28;					/*CCK:   -6dB*/
-+		} else {
-+			cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
-+			cali_info->default_cck_index = 24;
-+			cali_info->default_txagc_index = get_txagc_default_index(dm);
-+		}
-+		cali_info->default_bb_swing_index_flag = true;
-+	}
-+
-+	cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
-+	cali_info->CCK_index = cali_info->default_cck_index;
-+
-+	for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
-+		cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
-+		cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
-+		cali_info->delta_power_index[p] = 0;
-+		cali_info->delta_power_index_last[p] = 0;
-+		cali_info->power_index_offset[p] = 0;
-+		cali_info->kfree_offset[p] = 0;
-+	}
-+	cali_info->modify_tx_agc_value_ofdm = 0;
-+	cali_info->modify_tx_agc_value_cck = 0;
-+	cali_info->tm_trigger = 0;
-+}
-+
-+
-+void
-+odm_txpowertracking_check(
-+	void		*dm_void
-+)
-+{
-+
-+#if 0
-+	/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
-+	/*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
-+	/* HW dynamic mechanism. */
-+#endif
-+
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	switch	(dm->support_platform) {
-+	case	ODM_WIN:
-+		odm_txpowertracking_check_mp(dm);
-+		break;
-+
-+	case	ODM_CE:
-+		odm_txpowertracking_check_ce(dm);
-+		break;
-+
-+	case	ODM_AP:
-+		odm_txpowertracking_check_ap(dm);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+}
-+
-+void
-+odm_txpowertracking_check_ce(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_				*rf = &(dm->rf_table);
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	void	*adapter = dm->adapter;
-+#if ((RTL8188F_SUPPORT == 1))
-+	rtl8192c_odm_check_txpowertracking(adapter);
-+#endif
-+
-+#if (RTL8188E_SUPPORT == 1)
-+
-+	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
-+		return;
-+
-+	if (!cali_info->tm_trigger) {
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
-+		/*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/
-+
-+		cali_info->tm_trigger = 1;
-+		return;
-+
-+	} else {
-+		/*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/
-+		odm_txpowertracking_callback_thermal_meter_8188e(adapter);
-+		cali_info->tm_trigger = 0;
-+	}
-+#endif
-+#endif
-+}
-+
-+void
-+odm_txpowertracking_check_mp(
-+	void		*dm_void
-+)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void	*adapter = dm->adapter;
-+
-+	if (*dm->is_fcs_mode_enable)
-+		return;
-+
-+	if (odm_check_power_status(dm) == false) {
-+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status return false\n"));
-+		return;
-+	}
-+
-+	if (IS_HARDWARE_TYPE_8821B(adapter)) /* TODO: Don't Do PowerTracking*/
-+		return;
-+
-+	odm_txpowertracking_thermal_meter_check(adapter);
-+
-+
-+#endif
-+
-+}
-+
-+
-+void
-+odm_txpowertracking_check_ap(
-+	void		*dm_void
-+)
-+{
-+	return;
-+
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+void
-+odm_txpowertracking_direct_call(
-+	void		*adapter
-+)
-+{
-+	HAL_DATA_TYPE		*hal_data	= GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct			*dm = &hal_data->DM_OutSrc;
-+
-+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) {
-+#if (RTL8822C_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-+		odm_txpowertracking_new_callback_thermal_meter(dm);
-+#endif
-+	} else
-+		odm_txpowertracking_callback_thermal_meter(adapter);
-+}
-+
-+void
-+odm_txpowertracking_thermal_meter_check(
-+	void		*adapter
-+)
-+{
-+	static u8			tm_trigger = 0;
-+	HAL_DATA_TYPE			*pHalData = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct	*dm = &(pHalData->DM_OutSrc);
-+	struct _hal_rf_			*rf = &(dm->rf_table);
-+	struct _halrf_tssi_data *tssi = &rf->halrf_tssi_data;
-+
-+	if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) {
-+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
-+			("===>odm_txpowertracking_thermal_meter_check(),mgnt_info->is_txpowertracking is false, return!!\n"));
-+		return;
-+	}
-+
-+	if (!tm_trigger) {
-+		if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) || IS_HARDWARE_TYPE_8192F(adapter)
-+		    ||IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
-+		    || IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter) || IS_HARDWARE_TYPE_8710B(adapter)
-+		    )/* JJ ADD 20161014 */
-+			PHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
-+		else if (IS_HARDWARE_TYPE_8822C(adapter)) {
-+			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
-+			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x00);
-+			odm_set_rf_reg(dm, RF_PATH_A, R_0x42, BIT(19), 0x01);
-+			
-+			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
-+			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x00);
-+			odm_set_rf_reg(dm, RF_PATH_B, R_0x42, BIT(19), 0x01);
-+		} else if (IS_HARDWARE_TYPE_8814B(adapter)) {
-+			odm_set_rf_reg(dm, RF_PATH_A, 0x42, BIT(17), 0x1);
-+			odm_set_rf_reg(dm, RF_PATH_B, 0x42, BIT(17), 0x1);
-+			odm_set_rf_reg(dm, RF_PATH_C, 0x42, BIT(17), 0x1);
-+			odm_set_rf_reg(dm, RF_PATH_D, 0x42, BIT(17), 0x1);
-+		} else
-+			PHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
-+
-+		if (dm->support_ic_type & ODM_RTL8814B) {
-+			ODM_delay_us(300);
-+			odm_txpowertracking_direct_call(adapter);
-+			tssi->thermal_trigger = 1;
-+		}
-+
-+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n"));
-+
-+		tm_trigger = 1;
-+		return;
-+	} else {
-+		RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n"));
-+		odm_txpowertracking_direct_call(adapter);
-+
-+		if (dm->support_ic_type & ODM_RTL8814B)
-+			tssi->thermal_trigger = 0;
-+
-+		tm_trigger = 0;
-+	}
-+}
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_win.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_win.h
-new file mode 100644
-index 000000000000..f84d440da560
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_powertracking_win.h
-@@ -0,0 +1,306 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_POWERTRACKING_H__
-+#define __HALRF_POWERTRACKING_H__
-+
-+#define	DPK_DELTA_MAPPING_NUM	13
-+#define	index_mapping_HP_NUM	15
-+#define	TXSCALE_TABLE_SIZE		37
-+#define	OFDM_TABLE_SIZE			43
-+#define	CCK_TABLE_SIZE			33
-+#define	CCK_TABLE_SIZE_8723D    41
-+#define	TXPWR_TRACK_TABLE_SIZE	30
-+#define	DELTA_SWINGIDX_SIZE     30
-+#define	DELTA_SWINTSSI_SIZE     61
-+#define	BAND_NUM				3
-+#define	MAX_RF_PATH	4
-+#define	CCK_TABLE_SIZE_88F	21
-+/* JJ ADD 20161014 */
-+#define	CCK_TABLE_SIZE_8710B   41
-+#define	CCK_TABLE_SIZE_8192F   41
-+
-+
-+#define	dm_check_txpowertracking	odm_txpowertracking_check
-+
-+#define IQK_MATRIX_SETTINGS_NUM	(14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
-+#define	AVG_THERMAL_NUM		8
-+#define	iqk_matrix_reg_num	8
-+#define	IQK_MAC_REG_NUM		4
-+#define	IQK_ADDA_REG_NUM		16
-+
-+#define	IQK_BB_REG_NUM		9
-+
-+
-+extern	u32 ofdm_swing_table[OFDM_TABLE_SIZE];
-+extern	u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
-+extern	u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
-+
-+extern	u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
-+extern	u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
-+extern	u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
-+extern	u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
-+extern	u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
-+extern	u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
-+extern	u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
-+/* JJ ADD 20161014 */
-+extern	u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
-+extern	u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F];
-+
-+extern  u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
-+
-+/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
-+static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};
-+static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11};
-+
-+void
-+odm_txpowertracking_check(
-+	void		*dm_void
-+);
-+
-+void
-+odm_txpowertracking_check_ap(
-+	void		*dm_void
-+);
-+
-+void
-+odm_txpowertracking_thermal_meter_init(
-+	void		*dm_void
-+);
-+
-+void
-+odm_txpowertracking_init(
-+	void		*dm_void
-+);
-+
-+void
-+odm_txpowertracking_check_mp(
-+	void		*dm_void
-+);
-+
-+
-+void
-+odm_txpowertracking_check_ce(
-+	void		*dm_void
-+);
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+
-+
-+void
-+odm_txpowertracking_thermal_meter_check(
-+	void		*adapter
-+);
-+
-+#endif
-+
-+struct iqk_matrix_regs_setting {
-+	boolean	is_iqk_done;
-+	s32		value[3][iqk_matrix_reg_num];
-+	boolean	is_bw_iqk_result_saved[3];
-+};
-+
-+struct dm_rf_calibration_struct {
-+	/* for tx power tracking */
-+
-+	u32	rega24; /* for TempCCK */
-+	s32	rege94;
-+	s32	rege9c;
-+	s32	regeb4;
-+	s32	regebc;
-+	/* u8 is_txpowertracking; */
-+	u8	tx_powercount;
-+	boolean is_txpowertracking_init;
-+	boolean is_txpowertracking;
-+	u8  	txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
-+	u8	tm_trigger;
-+	u8  	internal_pa_5g[2];	/* pathA / pathB */
-+
-+	u8  	thermal_meter[2];    /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
-+	u8	thermal_value;
-+	u8	thermal_value_path[MAX_RF_PATH];
-+	u8	thermal_value_lck;
-+	u8	thermal_value_iqk;
-+	u8	thermal_value_dpk;
-+	s8	thermal_value_delta; /* delta of thermal_value and efuse thermal */
-+	u8	thermal_value_avg[AVG_THERMAL_NUM];
-+	u8	thermal_value_avg_path[MAX_RF_PATH][AVG_THERMAL_NUM];
-+	u8	thermal_value_avg_index;
-+	u8	thermal_value_avg_index_path[MAX_RF_PATH];
-+	u8	thermal_value_rx_gain;
-+
-+
-+	boolean	is_reloadtxpowerindex;
-+	u8	is_rf_pi_enable;
-+	u32 	txpowertracking_callback_cnt; /* cosa add for debug */
-+
-+
-+	/* ------------------------- Tx power Tracking ------------------------- */
-+	u8	is_cck_in_ch14;
-+	u8	CCK_index;
-+	u8	OFDM_index[MAX_RF_PATH];
-+	s8	power_index_offset[MAX_RF_PATH];
-+	s8	delta_power_index[MAX_RF_PATH];
-+	s8	delta_power_index_last[MAX_RF_PATH];
-+	boolean is_tx_power_changed;
-+	s8	xtal_offset;
-+	s8	xtal_offset_last;
-+
-+	struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
-+	u8	delta_lck;
-+	s8  bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
-+	u8  delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	u8  delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
-+	s8  delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
-+	s8  delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
-+	u8  delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
-+
-+	u8			bb_swing_idx_ofdm[MAX_RF_PATH];
-+	u8			bb_swing_idx_ofdm_current;
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	u8			bb_swing_idx_ofdm_base[MAX_RF_PATH];
-+#else
-+	u8			bb_swing_idx_ofdm_base;
-+#endif
-+	boolean		default_bb_swing_index_flag;
-+	boolean			bb_swing_flag_ofdm;
-+	u8			bb_swing_idx_cck;
-+	u8			bb_swing_idx_cck_current;
-+	u8			bb_swing_idx_cck_base;
-+	u8			default_ofdm_index;
-+	u8			default_cck_index;
-+	s8			default_txagc_index;
-+	boolean			bb_swing_flag_cck;
-+
-+	s8			absolute_ofdm_swing_idx[MAX_RF_PATH];
-+	s8			remnant_ofdm_swing_idx[MAX_RF_PATH];
-+	s8			absolute_cck_swing_idx[MAX_RF_PATH];
-+	s8			remnant_cck_swing_idx;
-+	s8			modify_tx_agc_value;       /*Remnat compensate value at tx_agc */
-+	boolean			modify_tx_agc_flag_path_a;
-+	boolean			modify_tx_agc_flag_path_b;
-+	boolean			modify_tx_agc_flag_path_c;
-+	boolean			modify_tx_agc_flag_path_d;
-+	boolean			modify_tx_agc_flag_path_a_cck;
-+	boolean			modify_tx_agc_flag_path_b_cck;
-+
-+	s8			kfree_offset[MAX_RF_PATH];
-+
-+	/* -------------------------------------------------------------------- */
-+
-+	/* for IQK */
-+	u32	regc04;
-+	u32	reg874;
-+	u32	regc08;
-+	u32	regb68;
-+	u32	regb6c;
-+	u32	reg870;
-+	u32	reg860;
-+	u32	reg864;
-+
-+	boolean	is_iqk_initialized;
-+	boolean is_lck_in_progress;
-+	boolean	is_antenna_detected;
-+	boolean	is_need_iqk;
-+	boolean	is_iqk_in_progress;
-+	boolean	is_iqk_pa_off;
-+	u8	delta_iqk;
-+	u32	ADDA_backup[IQK_ADDA_REG_NUM];
-+	u32	IQK_MAC_backup[IQK_MAC_REG_NUM];
-+	u32	IQK_BB_backup_recover[9];
-+	u32	IQK_BB_backup[IQK_BB_REG_NUM];
-+	u32	tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
-+	u32	rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
-+	u32	tx_iqc_8703b[3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
-+	u32	rx_iqc_8703b[2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
-+	u32	tx_iqc_8723d[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
-+	u32	rx_iqc_8723d[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
-+	/* JJ ADD 20161014 */
-+	u32	tx_iqc_8710b[2][3][2];	/* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
-+	u32	rx_iqc_8710b[2][2][2];	/* { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}*/
-+
-+	u64	iqk_start_time;
-+	u64	iqk_total_progressing_time;
-+	u64	iqk_progressing_time;
-+	u64	lck_progressing_time;
-+	u32  lok_result;
-+	u8	iqk_step;
-+	u8	kcount;
-+	u8	retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
-+	boolean	is_mp_mode;
-+
-+	/* for APK */
-+	u32 	ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
-+	u8	is_ap_kdone;
-+	u8	is_apk_thermal_meter_ignore;
-+
-+	/* DPK */
-+	boolean is_dpk_fail;
-+	u8	is_dp_done;
-+	u8	is_dp_path_aok;
-+	u8	is_dp_path_bok;
-+
-+	u32	tx_lok[2];
-+	u32  dpk_tx_agc;
-+	s32  dpk_gain;
-+	u32  dpk_thermal[4];
-+
-+	s8 modify_tx_agc_value_ofdm;
-+	s8 modify_tx_agc_value_cck;
-+
-+	/*Add by Yuchen for Kfree Phydm*/
-+	u8			reg_rf_kfree_enable;	/*for registry*/
-+	u8			rf_kfree_enable;		/*for efuse enable check*/
-+};
-+
-+
-+
-+
-+#endif	/*#ifndef __HALRF_POWER_TRACKING_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_psd.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_psd.c
-new file mode 100644
-index 000000000000..bab7d09acd0b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_psd.c
-@@ -0,0 +1,531 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/*@===========================================================
-+ * include files
-+ *============================================================
-+ */
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+u64 _sqrt(u64 x)
-+{
-+	u64 i = 0;
-+	u64 j = (x >> 1) + 1;
-+
-+	while (i <= j) {
-+		u64 mid = (i + j) >> 1;
-+
-+		u64 sq = mid * mid;
-+
-+		if (sq == x)
-+			return mid;
-+		else if (sq < x)
-+			i = mid + 1;
-+		else
-+			j = mid - 1;
-+	}
-+
-+	return j;
-+}
-+
-+u32 halrf_get_psd_data(
-+	struct dm_struct *dm,
-+	u32 point)
-+{
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
-+	u32 psd_val = 0, psd_reg, psd_report, psd_point, psd_start, i, delay_time = 0;
-+
-+#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
-+	if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) {
-+		if (psd->average == 0)
-+			delay_time = 100;
-+		else
-+			delay_time = 0;
-+	}
-+#endif
-+#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
-+	if (dm->support_interface == ODM_ITRF_PCIE) {
-+		if (psd->average == 0)
-+			delay_time = 1000;
-+		else
-+			delay_time = 100;
-+	}
-+#endif
-+
-+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
-+		psd_reg = R_0x910;
-+		psd_report = R_0xf44;
-+	} else {
-+		psd_reg = R_0x808;
-+		psd_report = R_0x8b4;
-+	}
-+
-+	if (dm->support_ic_type & ODM_RTL8710B) {
-+		psd_point = 0xeffffc00;
-+		psd_start = 0x10000000;
-+	} else {
-+		psd_point = 0xffbffc00;
-+		psd_start = 0x00400000;
-+	}
-+
-+	psd_val = odm_get_bb_reg(dm, psd_reg, MASKDWORD);
-+
-+	psd_val &= psd_point;
-+	psd_val |= point;
-+
-+	odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
-+
-+	psd_val |= psd_start;
-+
-+	odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
-+
-+	for (i = 0; i < delay_time; i++)
-+		ODM_delay_us(1);
-+
-+	psd_val = odm_get_bb_reg(dm, psd_report, MASKDWORD);
-+
-+	if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8710B)) {
-+		psd_val &= MASKL3BYTES;
-+		psd_val = psd_val / 32;
-+	} else {
-+		psd_val &= MASKLWORD;
-+	}
-+
-+	return psd_val;
-+}
-+
-+void halrf_psd(
-+	struct dm_struct *dm,
-+	u32 point,
-+	u32 start_point,
-+	u32 stop_point,
-+	u32 average)
-+{
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
-+
-+	u32 i = 0, j = 0, k = 0;
-+	u32 psd_reg, avg_org, point_temp, average_tmp, mode;
-+	u64 data_tatal = 0, data_temp[64] = {0};
-+
-+	psd->buf_size = 256;
-+
-+	mode = average >> 16;
-+	
-+	if (mode == 2)
-+		average_tmp = 1;
-+	else
-+		average_tmp = average & 0xffff;
-+
-+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
-+		psd_reg = R_0x910;
-+	else
-+		psd_reg = R_0x808;
-+
-+#if 0
-+	dbg_print("[PSD]point=%d, start_point=%d, stop_point=%d, average=%d, average_tmp=%d, buf_size=%d\n",
-+		point, start_point, stop_point, average, average_tmp, psd->buf_size);
-+#endif
-+
-+	for (i = 0; i < psd->buf_size; i++)
-+		psd->psd_data[i] = 0;
-+
-+	if (dm->support_ic_type & ODM_RTL8710B)
-+		avg_org = odm_get_bb_reg(dm, psd_reg, 0x30000);
-+	else
-+		avg_org = odm_get_bb_reg(dm, psd_reg, 0x3000);
-+
-+	if (mode == 1) {
-+		if (dm->support_ic_type & ODM_RTL8710B)
-+			odm_set_bb_reg(dm, psd_reg, 0x30000, 0x1);
-+		else
-+			odm_set_bb_reg(dm, psd_reg, 0x3000, 0x1);
-+	}
-+
-+#if 0
-+	if (avg_temp == 0)
-+		avg = 1;
-+	else if (avg_temp == 1)
-+		avg = 8;
-+	else if (avg_temp == 2)
-+		avg = 16;
-+	else if (avg_temp == 3)
-+		avg = 32;
-+#endif
-+
-+	i = start_point;
-+	while (i < stop_point) {
-+		data_tatal = 0;
-+
-+		if (i >= point)
-+			point_temp = i - point;
-+		else
-+			point_temp = i;
-+
-+		for (k = 0; k < average_tmp; k++) {
-+			data_temp[k] = halrf_get_psd_data(dm, point_temp);
-+			data_tatal = data_tatal + (data_temp[k] * data_temp[k]);
-+
-+#if 0
-+			if ((k % 20) == 0)
-+				dbg_print("\n ");
-+
-+			dbg_print("0x%x ", data_temp[k]);
-+#endif
-+		}
-+#if 0
-+		/*dbg_print("\n");*/
-+#endif
-+
-+		data_tatal = phydm_division64((data_tatal * 100), average_tmp);
-+		psd->psd_data[j] = (u32)_sqrt(data_tatal);
-+
-+		i++;
-+		j++;
-+	}
-+
-+#if 0
-+	for (i = 0; i < psd->buf_size; i++) {
-+		if ((i % 20) == 0)
-+			dbg_print("\n ");
-+
-+		dbg_print("0x%x ", psd->psd_data[i]);
-+	}
-+	dbg_print("\n\n");
-+#endif
-+
-+	if (dm->support_ic_type & ODM_RTL8710B)
-+		odm_set_bb_reg(dm, psd_reg, 0x30000, avg_org);
-+	else
-+		odm_set_bb_reg(dm, psd_reg, 0x3000, avg_org);
-+}
-+
-+void backup_bb_register(struct dm_struct *dm, u32 *bb_backup, u32 *backup_bb_reg, u32 counter)
-+{
-+	u32 i ;
-+
-+	for (i = 0; i < counter; i++)
-+		bb_backup[i] = odm_get_bb_reg(dm, backup_bb_reg[i], MASKDWORD);
-+}
-+
-+void restore_bb_register(struct dm_struct *dm, u32 *bb_backup, u32 *backup_bb_reg, u32 counter)
-+{
-+	u32 i ;
-+
-+	for (i = 0; i < counter; i++)
-+		odm_set_bb_reg(dm, backup_bb_reg[i], MASKDWORD, bb_backup[i]);
-+}
-+
-+
-+
-+void _halrf_psd_iqk_init(struct dm_struct *dm)
-+{
-+	odm_set_bb_reg(dm, 0x1b04, MASKDWORD, 0x0);
-+	odm_set_bb_reg(dm, 0x1b08, MASKDWORD, 0x80);
-+	odm_set_bb_reg(dm, 0x1b0c, 0xc00, 0x3);
-+	odm_set_bb_reg(dm, 0x1b14, MASKDWORD, 0x0);
-+	odm_set_bb_reg(dm, 0x1b18, BIT(0), 0x1);
-+
-+	if (dm->support_ic_type & ODM_RTL8197G)
-+		odm_set_bb_reg(dm, 0x1b20, MASKDWORD, 0x00040008);
-+	if (dm->support_ic_type & ODM_RTL8198F)
-+		odm_set_bb_reg(dm, 0x1b20, MASKDWORD, 0x00000000);
-+
-+	if (dm->support_ic_type & (ODM_RTL8197G | ODM_RTL8198F)) {
-+		odm_set_bb_reg(dm, 0x1b24, MASKDWORD, 0x00030000);
-+		odm_set_bb_reg(dm, 0x1b28, MASKDWORD, 0x00000000);
-+		odm_set_bb_reg(dm, 0x1b2c, MASKDWORD, 0x00180018);
-+		odm_set_bb_reg(dm, 0x1b30, MASKDWORD, 0x20000000);
-+		/*odm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x20000000);*/
-+		/*odm_set_bb_reg(dm, 0x1b3c, MASKDWORD, 0x20000000);*/
-+	}
-+
-+	odm_set_bb_reg(dm, 0x1b1c, 0xfff, 0xd21);
-+	odm_set_bb_reg(dm, 0x1b1c, 0xfff00000, 0x821);
-+	odm_set_bb_reg(dm, 0x1b28, MASKDWORD, 0x0);
-+	odm_set_bb_reg(dm, 0x1bcc, 0x3f, 0x3f);	
-+}
-+
-+
-+u32 halrf_get_iqk_psd_data(
-+	struct dm_struct *dm,
-+	u32 point)
-+{
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
-+	u32 psd_val, psd_val1, psd_val2, psd_point, i, delay_time = 0;
-+
-+#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
-+	if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) {
-+		if (dm->support_ic_type & ODM_RTL8822C)
-+			delay_time = 1000;
-+		else
-+			delay_time = 0;
-+	}
-+#endif
-+#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
-+	if (dm->support_interface == ODM_ITRF_PCIE) {
-+		if (dm->support_ic_type & ODM_RTL8822C)
-+			delay_time = 1000;
-+		else
-+			delay_time = 150;
-+	}
-+#endif
-+	psd_point = odm_get_bb_reg(dm, R_0x1b2c, MASKDWORD);
-+
-+	psd_point &= 0xF000FFFF;
-+
-+	point &= 0xFFF;
-+
-+	psd_point = psd_point | (point << 16);
-+
-+	odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, psd_point);
-+
-+	odm_set_bb_reg(dm, R_0x1b34, BIT(0), 0x1);
-+
-+	odm_set_bb_reg(dm, R_0x1b34, BIT(0), 0x0);
-+
-+	for (i = 0; i < delay_time; i++)
-+		ODM_delay_us(1);
-+
-+	if (dm->support_ic_type & (ODM_RTL8197G | ODM_RTL8198F)) {
-+		if (dm->support_ic_type & ODM_RTL8197G)
-+			odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x001a0001);
-+		else
-+			odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);
-+
-+		psd_val1 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
-+
-+		psd_val1 = (psd_val1 & 0x001f0000) >> 16;
-+
-+		if (dm->support_ic_type & ODM_RTL8197G)
-+			odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x001b0001);
-+		else
-+			odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);
-+
-+		psd_val2 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
-+
-+		psd_val = (psd_val1 << 27) + (psd_val2 >> 5);
-+	} else {
-+		odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);
-+
-+		psd_val1 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
-+
-+		psd_val1 = (psd_val1 & 0x07FF0000) >> 16;
-+
-+		odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);
-+
-+		psd_val2 = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
-+
-+		psd_val = (psd_val1 << 21) + (psd_val2 >> 11);
-+	}
-+
-+	return psd_val;
-+}
-+
-+void halrf_iqk_psd(
-+	struct dm_struct *dm,
-+	u32 point,
-+	u32 start_point,
-+	u32 stop_point,
-+	u32 average)
-+{
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
-+
-+	u32 i = 0, j = 0, k = 0;
-+	u32 psd_reg, avg_org, point_temp, average_tmp = 32, mode, reg_tmp = 5;
-+	u64 data_tatal = 0, data_temp[64] = {0};
-+	s32 s_point_tmp;
-+
-+	psd->buf_size = 256;
-+
-+	mode = average >> 16;
-+
-+	if (mode == 2) {
-+		if (dm->support_ic_type & ODM_RTL8822C)
-+			average_tmp = 1;
-+		else {
-+			reg_tmp = odm_get_bb_reg(dm, R_0x1b1c, 0x000e0000);
-+			if (reg_tmp == 0)
-+				average_tmp = 1;
-+			else if (reg_tmp == 3)
-+				average_tmp = 8;
-+			else if (reg_tmp == 4)
-+				average_tmp = 16;
-+			else if (reg_tmp == 5)
-+				average_tmp = 32;
-+			odm_set_bb_reg(dm, R_0x1b1c, 0x000e0000, 0x0);
-+		}
-+	} else {
-+		reg_tmp = odm_get_bb_reg(dm, R_0x1b1c, 0x000e0000);
-+		if (reg_tmp == 0)
-+			average_tmp = 1;
-+		else if (reg_tmp == 3)
-+			average_tmp = 8;
-+		else if (reg_tmp == 4)
-+			average_tmp = 16;
-+		else if (reg_tmp == 5)
-+			average_tmp = 32;
-+		odm_set_bb_reg(dm, R_0x1b1c, 0x000e0000, 0x0);
-+	}
-+
-+#if 0
-+	DbgPrint("[PSD]point=%d, start_point=%d, stop_point=%d, average=0x%x, average_tmp=%d, buf_size=%d, mode=%d\n",
-+		point, start_point, stop_point, average, average_tmp, psd->buf_size, mode);
-+#endif
-+
-+	for (i = 0; i < psd->buf_size; i++)
-+		psd->psd_data[i] = 0;
-+
-+	i = start_point;
-+	while (i < stop_point) {
-+		data_tatal = 0;
-+
-+		if (i >= point)
-+			point_temp = i - point;
-+		else
-+		{
-+			if (dm->support_ic_type & ODM_RTL8814B)
-+			{
-+				s_point_tmp = i - point - 1;
-+				point_temp = s_point_tmp & 0xfff;
-+			}
-+			else
-+				point_temp = i;
-+		}
-+
-+		for (k = 0; k < average_tmp; k++) {
-+			data_temp[k] = halrf_get_iqk_psd_data(dm, point_temp);
-+			/*data_tatal = data_tatal + (data_temp[k] * data_temp[k]);*/
-+			data_tatal = data_tatal + data_temp[k];
-+
-+#if 0
-+			if ((k % 20) == 0)
-+				DbgPrint("\n ");
-+
-+			DbgPrint("0x%x ", data_temp[k]);
-+#endif
-+		}
-+
-+		data_tatal = phydm_division64((data_tatal * 10), average_tmp);
-+		psd->psd_data[j] = (u32)data_tatal;
-+
-+		i++;
-+		j++;
-+	}
-+
-+	if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F | ODM_RTL8197G))
-+		odm_set_bb_reg(dm, R_0x1b1c, 0x000e0000, reg_tmp);
-+
-+#if 0
-+	DbgPrint("\n [iqk psd]psd result:\n");
-+
-+	for (i = 0; i < psd->buf_size; i++) {
-+		if ((i % 20) == 0)
-+			DbgPrint("\n ");
-+
-+		DbgPrint("0x%x ", psd->psd_data[i]);
-+	}
-+	DbgPrint("\n\n");
-+#endif
-+}
-+
-+
-+u32
-+halrf_psd_init(
-+	void *dm_void)
-+{
-+	enum rt_status ret_status = RT_STATUS_SUCCESS;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
-+
-+#if 0
-+	u32 bb_backup[12];
-+	u32 backup_bb_reg[12] = {0x1b04, 0x1b08, 0x1b0c, 0x1b14, 0x1b18,
-+				0x1b1c, 0x1b28, 0x1bcc, 0x1b2c, 0x1b34,
-+				0x1bd4, 0x1bfc};
-+#endif
-+
-+	if (psd->psd_progress) {
-+		ret_status = RT_STATUS_PENDING;
-+	} else {
-+		psd->psd_progress = 1;
-+		if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8198F | ODM_RTL8197G)) {
-+			/*backup_bb_register(dm, bb_backup, backup_bb_reg, 12);*/
-+			_halrf_psd_iqk_init(dm);
-+			halrf_iqk_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
-+			/*restore_bb_register(dm, bb_backup, backup_bb_reg, 12);*/
-+		} else
-+			halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
-+		psd->psd_progress = 0;
-+	}
-+	return ret_status;
-+}
-+
-+u32
-+halrf_psd_query(
-+	void *dm_void,
-+	u32 *outbuf,
-+	u32 buf_size)
-+{
-+	enum rt_status ret_status = RT_STATUS_SUCCESS;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
-+
-+	if (psd->psd_progress)
-+		ret_status = RT_STATUS_PENDING;
-+	else
-+		odm_move_memory(dm, outbuf, psd->psd_data,
-+				sizeof(u32) * psd->buf_size);
-+
-+	return ret_status;
-+}
-+
-+u32
-+halrf_psd_init_query(
-+	void *dm_void,
-+	u32 *outbuf,
-+	u32 point,
-+	u32 start_point,
-+	u32 stop_point,
-+	u32 average,
-+	u32 buf_size)
-+{
-+	enum rt_status ret_status = RT_STATUS_SUCCESS;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+	struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
-+
-+	psd->point = point;
-+	psd->start_point = start_point;
-+	psd->stop_point = stop_point;
-+	psd->average = average;
-+
-+	if (psd->psd_progress) {
-+		ret_status = RT_STATUS_PENDING;
-+	} else {
-+		psd->psd_progress = 1;
-+		halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
-+		odm_move_memory(dm, outbuf, psd->psd_data, 0x400);
-+		psd->psd_progress = 0;
-+	}
-+
-+	return ret_status;
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_psd.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_psd.h
-new file mode 100644
-index 000000000000..f4a76746d9cb
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_psd.h
-@@ -0,0 +1,50 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_PSD_H__
-+#define __HALRF_PSD_H__
-+
-+
-+struct _halrf_psd_data {
-+	u32 point;
-+	u32 start_point;
-+	u32 stop_point;
-+	u32 average;
-+	u32 buf_size;
-+	u32 psd_data[256];
-+	u32 psd_progress;
-+};
-+
-+u32
-+halrf_psd_init(
-+	void *dm_void);
-+
-+u32
-+halrf_psd_query(
-+	void *dm_void,
-+	u32 *outbuf,
-+	u32 buf_size);
-+
-+u32
-+halrf_psd_init_query(
-+	void *dm_void,
-+	u32 *outbuf,
-+	u32 point,
-+	u32 start_point,
-+	u32 stop_point,
-+	u32 average,
-+	u32 buf_size);
-+
-+#endif /*#__HALRF_PSD_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_txgapcal.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_txgapcal.c
-new file mode 100644
-index 000000000000..0cc44974bf3f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_txgapcal.c
-@@ -0,0 +1,300 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+void odm_bub_sort(u32 *data, u32 n)
-+{
-+	int i, j, temp, sp;
-+
-+	for (i = n - 1; i >= 0; i--) {
-+		sp = 1;
-+		for (j = 0; j < i; j++) {
-+			if (data[j] < data[j + 1]) {
-+				temp = data[j];
-+				data[j] = data[j + 1];
-+				data[j + 1] = temp;
-+				sp = 0;
-+			}
-+		}
-+		if (sp == 1)
-+			break;
-+	}
-+}
-+
-+#if (RTL8197F_SUPPORT == 1)
-+
-+u4Byte
-+odm_tx_gain_gap_psd_8197f(
-+	void *dm_void,
-+	u1Byte rf_path,
-+	u4Byte rf56)
-+{
-+	PDM_ODM_T dm = (PDM_ODM_T)dm_void;
-+
-+	u1Byte i, j;
-+	u4Byte psd_vaule[5], psd_avg_time = 5, psd_vaule_temp;
-+
-+	u4Byte iqk_ctl_addr[2][6] = {{0xe30, 0xe34, 0xe50, 0xe54, 0xe38, 0xe3c},
-+				     {0xe50, 0xe54, 0xe30, 0xe34, 0xe58, 0xe5c}};
-+
-+	u4Byte psd_finish_bit[2] = {0x04000000, 0x20000000};
-+	u4Byte psd_fail_bit[2] = {0x08000000, 0x40000000};
-+
-+	u4Byte psd_cntl_value[2][2] = {{0x38008c1c, 0x10008c1c},
-+				       {0x38008c2c, 0x10008c2c}};
-+
-+	u4Byte psd_report_addr[2] = {0xea0, 0xec0};
-+
-+	odm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00e02);
-+
-+	ODM_delay_us(100);
-+
-+	odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x0);
-+
-+	odm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56);
-+	while (rf56 != (odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff)))
-+		odm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56);
-+
-+	odm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44FFBB44);
-+	odm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x00400040);
-+	odm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005403);
-+	odm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000804e4);
-+	odm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04203400);
-+	odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x80800000);
-+
-+	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][0], 0xffffffff, psd_cntl_value[rf_path][0]);
-+	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][1], 0xffffffff, psd_cntl_value[rf_path][1]);
-+	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][2], 0xffffffff, psd_cntl_value[rf_path][0]);
-+	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][3], 0xffffffff, psd_cntl_value[rf_path][0]);
-+	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][4], 0xffffffff, 0x8215001F);
-+	odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][5], 0xffffffff, 0x2805001F);
-+
-+	odm_set_bb_reg(dm, R_0xe40, 0xffffffff, 0x81007C00);
-+	odm_set_bb_reg(dm, R_0xe44, 0xffffffff, 0x81004800);
-+	odm_set_bb_reg(dm, R_0xe4c, 0xffffffff, 0x0046a8d0);
-+
-+	for (i = 0; i < psd_avg_time; i++) {
-+		for (j = 0; j < 1000; j++) {
-+			odm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xfa005800);
-+			odm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xf8005800);
-+
-+			while (!odm_get_bb_reg(dm, R_0xeac, psd_finish_bit[rf_path]))
-+				; /*wait finish bit*/
-+
-+			if (!odm_get_bb_reg(dm, R_0xeac, psd_fail_bit[rf_path])) { /*check fail bit*/
-+
-+				psd_vaule[i] = odm_get_bb_reg(dm, psd_report_addr[rf_path], 0xffffffff);
-+
-+				if (psd_vaule[i] > 0xffff)
-+					break;
-+			}
-+		}
-+
-+		RF_DBG(dm, DBG_RF_IQK,
-+		       "[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x time=%d psd_vaule=0x%x\n",
-+		       odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56,
-+		       odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), j,
-+		       psd_vaule[i]);
-+	}
-+
-+	odm_bub_sort(psd_vaule, psd_avg_time);
-+
-+	psd_vaule_temp = psd_vaule[(UINT)(psd_avg_time / 2)];
-+
-+	odm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44BBBB44);
-+	odm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x80408040);
-+	odm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005433);
-+	odm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000004e4);
-+	odm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04003400);
-+	odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x00000000);
-+
-+	RF_DBG(dm, DBG_RF_IQK,
-+	       "[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x psd_vaule_temp=0x%x\n",
-+	       odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56,
-+	       odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), psd_vaule_temp);
-+
-+	odm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00602);
-+
-+	return psd_vaule_temp;
-+}
-+
-+void odm_tx_gain_gap_calibration_8197f(
-+	void *dm_void)
-+{
-+	PDM_ODM_T dm = (PDM_ODM_T)dm_void;
-+
-+	u1Byte rf_path, rf0_idx, rf0_idx_current, rf0_idx_next, i, delta_gain_retry = 3;
-+
-+	s1Byte delta_gain_gap_pre, delta_gain_gap[2][11];
-+	u4Byte rf56_current, rf56_next, psd_value_current, psd_value_next;
-+	u4Byte psd_gap, rf56_current_temp[2][11];
-+	s4Byte rf33[2][11];
-+
-+	memset(rf33, 0x0, sizeof(rf33));
-+
-+	for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
-+		if (rf_path == RF_PATH_A)
-+			odm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x3); /*disable 3-wire*/
-+		else if (rf_path == RF_PATH_B)
-+			odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x3); /*disable 3-wire*/
-+
-+		ODM_delay_us(100);
-+
-+		for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
-+			rf0_idx_current = 3 * (rf0_idx - 1) + 1;
-+			odm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_current);
-+			ODM_delay_us(100);
-+			rf56_current_temp[rf_path][rf0_idx] = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff);
-+			rf56_current = rf56_current_temp[rf_path][rf0_idx];
-+
-+			rf0_idx_next = 3 * rf0_idx + 1;
-+			odm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_next);
-+			ODM_delay_us(100);
-+			rf56_next = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff);
-+
-+			RF_DBG(dm, DBG_RF_IQK,
-+			       "[TGGC] rf56_current[%d][%d]=0x%x rf56_next[%d][%d]=0x%x\n",
-+			       rf_path, rf0_idx, rf56_current, rf_path, rf0_idx,
-+			       rf56_next);
-+
-+			if ((rf56_current >> 5) == (rf56_next >> 5)) {
-+				delta_gain_gap[rf_path][rf0_idx] = 0;
-+
-+				RF_DBG(dm, DBG_RF_IQK,
-+				       "[TGGC] rf56_current[11:5] == rf56_next[%d][%d][11:5]=0x%x delta_gain_gap[%d][%d]=%d\n",
-+				       rf_path, rf0_idx, (rf56_next >> 5),
-+				       rf_path, rf0_idx,
-+				       delta_gain_gap[rf_path][rf0_idx]);
-+
-+				continue;
-+			}
-+
-+			RF_DBG(dm, DBG_RF_IQK,
-+			       "[TGGC] rf56_current[%d][%d][11:5]=0x%x != rf56_next[%d][%d][11:5]=0x%x\n",
-+			       rf_path, rf0_idx, (rf56_current >> 5), rf_path,
-+			       rf0_idx, (rf56_next >> 5));
-+
-+			for (i = 0; i < delta_gain_retry; i++) {
-+				psd_value_current = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_current);
-+
-+				psd_value_next = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_next - 2);
-+
-+				psd_gap = psd_value_next / (psd_value_current / 1000);
-+
-+#if 0
-+				if (psd_gap > 1413)
-+					delta_gain_gap[rf_path][rf0_idx] = 1;
-+				else if (psd_gap > 1122)
-+					delta_gain_gap[rf_path][rf0_idx] = 0;
-+				else
-+					delta_gain_gap[rf_path][rf0_idx] = -1;
-+#endif
-+
-+				if (psd_gap > 1445)
-+					delta_gain_gap[rf_path][rf0_idx] = 1;
-+				else if (psd_gap > 1096)
-+					delta_gain_gap[rf_path][rf0_idx] = 0;
-+				else
-+					delta_gain_gap[rf_path][rf0_idx] = -1;
-+
-+				if (i == 0)
-+					delta_gain_gap_pre = delta_gain_gap[rf_path][rf0_idx];
-+
-+				RF_DBG(dm, DBG_RF_IQK,
-+				       "[TGGC] psd_value_current=0x%x psd_value_next=0x%x psd_value_next/psd_value_current=%d delta_gain_gap[%d][%d]=%d\n",
-+				       psd_value_current, psd_value_next,
-+				       psd_gap, rf_path, rf0_idx,
-+				       delta_gain_gap[rf_path][rf0_idx]);
-+
-+				if (i == 0 && delta_gain_gap[rf_path][rf0_idx] == 0)
-+					break;
-+
-+				if (delta_gain_gap_pre != delta_gain_gap[rf_path][rf0_idx]) {
-+					delta_gain_gap[rf_path][rf0_idx] = 0;
-+
-+					RF_DBG(dm, DBG_RF_IQK, "[TGGC] delta_gain_gap_pre(%d) != delta_gain_gap[%d][%d](%d) time=%d\n",
-+					       delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i);
-+
-+					break;
-+				}
-+
-+				RF_DBG(dm, DBG_RF_IQK,
-+				       "[TGGC] delta_gain_gap_pre(%d) == delta_gain_gap[%d][%d](%d) time=%d\n",
-+				       delta_gain_gap_pre, rf_path, rf0_idx,
-+				       delta_gain_gap[rf_path][rf0_idx], i);
-+			}
-+		}
-+
-+		if (rf_path == RF_PATH_A)
-+			odm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x0); /*enable 3-wire*/
-+		else if (rf_path == RF_PATH_B)
-+			odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x0); /*enable 3-wire*/
-+
-+		ODM_delay_us(100);
-+	}
-+
-+#if 0
-+	/*odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22) | BIT(21) | BIT(20)), 0x0);*/ /*enable 3-wire*/
-+#endif
-+
-+	for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
-+		odm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00100);
-+
-+		for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
-+			rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + (rf56_current_temp[rf_path][rf0_idx] & 0x1f);
-+
-+			for (i = rf0_idx; i <= 10; i++)
-+				rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + delta_gain_gap[rf_path][i];
-+
-+			if (rf33[rf_path][rf0_idx] >= 0x1d)
-+				rf33[rf_path][rf0_idx] = 0x1d;
-+			else if (rf33[rf_path][rf0_idx] <= 0x2)
-+				rf33[rf_path][rf0_idx] = 0x2;
-+
-+			rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + ((rf0_idx - 1) * 0x4000) + (rf56_current_temp[rf_path][rf0_idx] & 0xfffe0);
-+
-+			RF_DBG(dm, DBG_RF_IQK,
-+			       "[TGGC] rf56[%d][%d]=0x%05x rf33[%d][%d]=0x%05x\n",
-+			       rf_path, rf0_idx,
-+			       rf56_current_temp[rf_path][rf0_idx], rf_path,
-+			       rf0_idx, rf33[rf_path][rf0_idx]);
-+
-+			odm_set_rf_reg(dm, rf_path, RF_0x33, bRFRegOffsetMask, rf33[rf_path][rf0_idx]);
-+		}
-+
-+		odm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00000);
-+	}
-+}
-+#endif
-+
-+void odm_tx_gain_gap_calibration(void *dm_void)
-+{
-+	PDM_ODM_T dm = (PDM_ODM_T)dm_void;
-+#if (RTL8197F_SUPPORT == 1)
-+	if (dm->SupportICType & ODM_RTL8197F)
-+		odm_tx_gain_gap_calibration_8197f(dm_void);
-+#endif
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_txgapcal.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_txgapcal.h
-new file mode 100644
-index 000000000000..09651cbee3b9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/halrf_txgapcal.h
-@@ -0,0 +1,31 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_TXGAPCAL_H__
-+#define __HALRF_TXGAPCAL_H__
-+
-+void odm_tx_gain_gap_calibration(void *dm_void);
-+
-+#endif /*__HALRF_TXGAPCAL_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/rtl8703b/halrf_8703b.c b/drivers/staging/rtl8723cs/hal/phydm/halrf/rtl8703b/halrf_8703b.c
-new file mode 100644
-index 000000000000..6630fee689a6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/rtl8703b/halrf_8703b.c
-@@ -0,0 +1,1857 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include "mp_precomp.h"
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#if RT_PLATFORM == PLATFORM_MACOSX
-+#include "phydm_precomp.h"
-+#else
-+#include "../phydm_precomp.h"
-+#endif
-+#else
-+#include "../../phydm_precomp.h"
-+#endif
-+
-+#if (RTL8703B_SUPPORT == 1)
-+
-+/*---------------------------Define Local Constant---------------------------*/
-+/* IQK */
-+#define IQK_DELAY_TIME_8703B 10
-+#define LCK_DELAY_TIME_8703B 100
-+
-+/* LTE_COEX */
-+#define REG_LTECOEX_CTRL 0x07C0
-+#define REG_LTECOEX_WRITE_DATA 0x07C4
-+#define REG_LTECOEX_READ_DATA 0x07C8
-+#define REG_LTECOEX_PATH_CONTROL 0x70
-+
-+/* 2010/04/25 MH Define the max tx power tracking tx agc power. */
-+#define ODM_TXPWRTRACK_MAX_IDX8703B 6
-+
-+#define idx_0xc94 0
-+#define idx_0xc80 1
-+#define idx_0xc4c 2
-+
-+#define idx_0xc14 0
-+#define idx_0xca0 1
-+
-+#define KEY 0
-+#define VAL 1
-+
-+/*---------------------------Define Local Constant---------------------------*/
-+
-+/* 3============================================================
-+ * 3 Tx Power Tracking
-+ * 3============================================================ */
-+
-+void set_iqk_matrix_8703b(struct dm_struct *dm, u8 OFDM_index, u8 rf_path,
-+			  s32 iqk_result_x, s32 iqk_result_y)
-+{
-+	s32 ele_A = 0, ele_D = 0, ele_C = 0, value32;
-+	s32 ele_A_ext = 0, ele_C_ext = 0, ele_D_ext = 0;
-+
-+	rf_path = RF_PATH_A;
-+
-+	if (OFDM_index >= OFDM_TABLE_SIZE)
-+		OFDM_index = OFDM_TABLE_SIZE - 1;
-+	else if (OFDM_index < 0)
-+		OFDM_index = 0;
-+
-+	if (iqk_result_x != 0 && (*dm->band_type == ODM_BAND_2_4G)) {
-+		/* new element D */
-+		ele_D = (ofdm_swing_table_new[OFDM_index] & 0xFFC00000) >> 22;
-+		ele_D_ext = (((iqk_result_x * ele_D) >> 7) & 0x01);
-+
-+		/* new element A */
-+		if ((iqk_result_x & 0x00000200) != 0) /* consider minus */
-+			iqk_result_x = iqk_result_x | 0xFFFFFC00;
-+		ele_A = ((iqk_result_x * ele_D) >> 8) & 0x000003FF;
-+		ele_A_ext = ((iqk_result_x * ele_D) >> 7) & 0x1;
-+		/* new element C */
-+		if ((iqk_result_y & 0x00000200) != 0)
-+			iqk_result_y = iqk_result_y | 0xFFFFFC00;
-+		ele_C = ((iqk_result_y * ele_D) >> 8) & 0x000003FF;
-+		ele_C_ext = ((iqk_result_y * ele_D) >> 7) & 0x1;
-+
-+		switch (rf_path) {
-+		case RF_PATH_A:
-+			/* write new elements A, C, D to regC80, regC94, reg0xc4c, and element B is always 0 */
-+			/* write 0xc80 */
-+			value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
-+			odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, value32);
-+			/* write 0xc94 */
-+			value32 = (ele_C & 0x000003C0) >> 6;
-+			odm_set_bb_reg(dm, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, value32);
-+			/* write 0xc4c */
-+			value32 = (ele_D_ext << 28) | (ele_A_ext << 31) | (ele_C_ext << 29);
-+			value32 = (odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(31) | BIT(29) | BIT(28)))) | value32;
-+			odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
-+			break;
-+		case RF_PATH_B:
-+			/* write new elements A, C, D to regC88, regC9C, regC4C, and element B is always 0 */
-+			/* write 0xc88 */
-+			value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
-+			odm_set_bb_reg(dm, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, value32);
-+			/* write 0xc9c */
-+			value32 = (ele_C & 0x000003C0) >> 6;
-+			odm_set_bb_reg(dm, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, value32);
-+			/* write 0xc4c */
-+			value32 = (ele_D_ext << 24) | (ele_A_ext << 27) | (ele_C_ext << 25);
-+			value32 = (odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(24) | BIT(27) | BIT(25)))) | value32;
-+			odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
-+			break;
-+		default:
-+			break;
-+		}
-+	} else {
-+		switch (rf_path) {
-+		case RF_PATH_A:
-+			odm_set_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_new[OFDM_index]);
-+			odm_set_bb_reg(dm, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, 0x00);
-+			value32 = odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(31) | BIT(29) | BIT(28)));
-+			odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
-+			break;
-+
-+		case RF_PATH_B:
-+			odm_set_bb_reg(dm, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_new[OFDM_index]);
-+			odm_set_bb_reg(dm, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, 0x00);
-+			value32 = odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & (~(BIT(24) | BIT(27) | BIT(25)));
-+			odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD, value32);
-+			break;
-+
-+		default:
-+			break;
-+		}
-+	}
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+	       "TxPwrTracking path %c: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x ele_A_ext = 0x%x ele_C_ext = 0x%x ele_D_ext = 0x%x\n",
-+	       (rf_path == RF_PATH_A ? 'A' : 'B'), (u32)iqk_result_x,
-+	       (u32)iqk_result_y, (u32)ele_A, (u32)ele_C, (u32)ele_D,
-+	       (u32)ele_A_ext, (u32)ele_C_ext, (u32)ele_D_ext);
-+}
-+
-+void set_cck_filter_coefficient_8703b(struct dm_struct *dm, u8 cck_swing_index)
-+{
-+	odm_write_1byte(dm, 0xa22, cck_swing_table_ch1_ch14_88f[cck_swing_index][0]);
-+	odm_write_1byte(dm, 0xa23, cck_swing_table_ch1_ch14_88f[cck_swing_index][1]);
-+	odm_write_1byte(dm, 0xa24, cck_swing_table_ch1_ch14_88f[cck_swing_index][2]);
-+	odm_write_1byte(dm, 0xa25, cck_swing_table_ch1_ch14_88f[cck_swing_index][3]);
-+	odm_write_1byte(dm, 0xa26, cck_swing_table_ch1_ch14_88f[cck_swing_index][4]);
-+	odm_write_1byte(dm, 0xa27, cck_swing_table_ch1_ch14_88f[cck_swing_index][5]);
-+	odm_write_1byte(dm, 0xa28, cck_swing_table_ch1_ch14_88f[cck_swing_index][6]);
-+	odm_write_1byte(dm, 0xa29, cck_swing_table_ch1_ch14_88f[cck_swing_index][7]);
-+	odm_write_1byte(dm, 0xa9a, cck_swing_table_ch1_ch14_88f[cck_swing_index][8]);
-+	odm_write_1byte(dm, 0xa9b, cck_swing_table_ch1_ch14_88f[cck_swing_index][9]);
-+	odm_write_1byte(dm, 0xa9c, cck_swing_table_ch1_ch14_88f[cck_swing_index][10]);
-+	odm_write_1byte(dm, 0xa9d, cck_swing_table_ch1_ch14_88f[cck_swing_index][11]);
-+	odm_write_1byte(dm, 0xaa0, cck_swing_table_ch1_ch14_88f[cck_swing_index][12]);
-+	odm_write_1byte(dm, 0xaa1, cck_swing_table_ch1_ch14_88f[cck_swing_index][13]);
-+	odm_write_1byte(dm, 0xaa2, cck_swing_table_ch1_ch14_88f[cck_swing_index][14]);
-+	odm_write_1byte(dm, 0xaa3, cck_swing_table_ch1_ch14_88f[cck_swing_index][15]);
-+}
-+
-+void do_iqk_8703b(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
-+		  u8 threshold)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	odm_reset_iqk_result(dm);
-+	dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
-+	halrf_iqk_trigger(dm, false);
-+}
-+
-+/*-----------------------------------------------------------------------------
-+ * Function:	odm_TxPwrTrackSetPwr88E()
-+ *
-+ * Overview:	88E change all channel tx power accordign to flag.
-+ *				OFDM & CCK are all different.
-+ *
-+ * Input:		NONE
-+ *
-+ * Output:		NONE
-+ *
-+ * Return:		NONE
-+ *
-+ * Revised History:
-+ *	When		Who		Remark
-+ *	04/23/2012	MHC		Create version 0.
-+ *
-+ *---------------------------------------------------------------------------*/
-+void odm_tx_pwr_track_set_pwr_8703b(void *dm_void, enum pwrtrack_method method,
-+				    u8 rf_path, u8 channel_mapped_index)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ADAPTER *adapter = dm->adapter;
-+	u8 pwr_tracking_limit_ofdm = 34; /* +0dB */
-+	u8 pwr_tracking_limit_cck = CCK_TABLE_SIZE_88F - 1; /* -2dB */
-+	u8 tx_rate = 0xFF;
-+	u8 final_ofdm_swing_index = 0;
-+	u8 final_cck_swing_index = 0;
-+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+#if (MP_DRIVER == 1) /*win MP */
-+	PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
-+
-+	tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
-+#else /*win normal*/
-+	PMGNT_INFO mgnt_info = &(((PADAPTER)adapter)->MgntInfo);
-+	if (!mgnt_info->ForcedDataRate) { /*auto rate*/
-+		tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
-+	} else
-+		tx_rate = (u8)mgnt_info->ForcedDataRate;
-+#endif
-+#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+	if (*dm->mp_mode == true) { /*CE MP*/
-+#ifdef CONFIG_MP_INCLUDED
-+		PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
-+
-+		tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
-+#endif
-+	} else { /*CE normal*/
-+		u16 rate = *(dm->forced_data_rate);
-+
-+		if (!rate) { /*auto rate*/
-+			if (dm->number_linked_client != 0)
-+				tx_rate = hw_rate_to_m_rate(dm->tx_rate);
-+			else
-+				tx_rate = rf->p_rate_index;
-+		} else /*force rate*/
-+			tx_rate = (u8)rate;
-+	}
-+#endif
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>ODM_TxPwrTrackSetPwr8703B\n");
-+
-+	if (tx_rate != 0xFF) {
-+		/*2 CCK*/
-+		if ((tx_rate >= MGN_1M && tx_rate <= MGN_5_5M) || tx_rate == MGN_11M)
-+			pwr_tracking_limit_cck = CCK_TABLE_SIZE_88F - 1;
-+		/*2 OFDM*/
-+		else if ((tx_rate >= MGN_6M) && (tx_rate <= MGN_48M))
-+			pwr_tracking_limit_ofdm = 36; /*+3dB*/
-+		else if (tx_rate == MGN_54M)
-+			pwr_tracking_limit_ofdm = 34; /*+2dB*/
-+		/*2 HT*/
-+		else if ((tx_rate >= MGN_MCS0) && (tx_rate <= MGN_MCS2)) /*QPSK/BPSK*/
-+			pwr_tracking_limit_ofdm = 38; /*+4dB*/
-+		else if ((tx_rate >= MGN_MCS3) && (tx_rate <= MGN_MCS4)) /*16QAM*/
-+			pwr_tracking_limit_ofdm = 36; /*+3dB*/
-+		else if ((tx_rate >= MGN_MCS5) && (tx_rate <= MGN_MCS7)) /*64QAM*/
-+			pwr_tracking_limit_ofdm = 34; /*+2dB*/
-+		else
-+			pwr_tracking_limit_ofdm = cali_info->default_ofdm_index; /*Default OFDM index = 30*/
-+	}
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "tx_rate=0x%x, pwr_tracking_limit=%d\n",
-+	       tx_rate, pwr_tracking_limit_ofdm);
-+
-+	if (method == TXAGC) {
-+		u32 pwr = 0, tx_agc = 0;
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       "odm_TxPwrTrackSetPwr8703B CH=%d\n", *(dm->channel));
-+
-+		cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path];
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+#if (MP_DRIVER != 1)
-+		cali_info->modify_tx_agc_flag_path_a = true;
-+		cali_info->modify_tx_agc_flag_path_a_cck = true;
-+
-+		odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, CCK);
-+		odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, OFDM);
-+		odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, HT_MCS0_MCS7);
-+#else
-+		pwr = odm_get_bb_reg(dm, REG_TX_AGC_A_RATE18_06, 0xFF);
-+		pwr += cali_info->power_index_offset[rf_path];
-+		odm_set_bb_reg(dm, REG_TX_AGC_A_CCK_1_MCS32, MASKBYTE1, pwr);
-+		tx_agc = (pwr << 16) | (pwr << 8) | (pwr);
-+		odm_set_bb_reg(dm, REG_TX_AGC_B_CCK_11_A_CCK_2_11, 0xffffff00, tx_agc);
-+		RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr8703B: CCK Tx-rf(A) Power = 0x%x\n", tx_agc));
-+
-+		pwr = odm_get_bb_reg(dm, REG_TX_AGC_A_RATE18_06, 0xFF);
-+		pwr += (cali_info->bb_swing_idx_ofdm[rf_path] - cali_info->bb_swing_idx_ofdm_base[rf_path]);
-+		tx_agc |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
-+		odm_set_bb_reg(dm, REG_TX_AGC_A_RATE18_06, MASKDWORD, tx_agc);
-+		odm_set_bb_reg(dm, REG_TX_AGC_A_RATE54_24, MASKDWORD, tx_agc);
-+		odm_set_bb_reg(dm, REG_TX_AGC_A_MCS03_MCS00, MASKDWORD, tx_agc);
-+		odm_set_bb_reg(dm, REG_TX_AGC_A_MCS07_MCS04, MASKDWORD, tx_agc);
-+		odm_set_bb_reg(dm, REG_TX_AGC_A_MCS11_MCS08, MASKDWORD, tx_agc);
-+		odm_set_bb_reg(dm, REG_TX_AGC_A_MCS15_MCS12, MASKDWORD, tx_agc);
-+		RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr8703B: OFDM Tx-rf(A) Power = 0x%x\n", tx_agc));
-+#endif
-+#endif
-+	} else if (method == BBSWING) {
-+		final_ofdm_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
-+		final_cck_swing_index = cali_info->default_cck_index + cali_info->absolute_ofdm_swing_idx[rf_path];
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       " cali_info->default_ofdm_index=%d,  cali_info->DefaultCCKIndex=%d, cali_info->absolute_ofdm_swing_idx[rf_path]=%d, cali_info->remnant_cck_swing_idx=%d   rf_path = %d\n",
-+		       cali_info->default_ofdm_index,
-+		       cali_info->default_cck_index,
-+		       cali_info->absolute_ofdm_swing_idx[rf_path],
-+		       cali_info->remnant_cck_swing_idx, rf_path);
-+
-+		/* Adjust BB swing by OFDM IQ matrix */
-+		if (final_ofdm_swing_index >= pwr_tracking_limit_ofdm)
-+			final_ofdm_swing_index = pwr_tracking_limit_ofdm;
-+		else if (final_ofdm_swing_index < 0)
-+			final_ofdm_swing_index = 0;
-+
-+		if (final_cck_swing_index >= CCK_TABLE_SIZE_88F)
-+			final_cck_swing_index = CCK_TABLE_SIZE_88F - 1;
-+		else if (cali_info->bb_swing_idx_cck < 0)
-+			final_cck_swing_index = 0;
-+
-+		set_iqk_matrix_8703b(dm, final_ofdm_swing_index, RF_PATH_A,
-+				     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
-+				     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
-+
-+		set_cck_filter_coefficient_8703b(dm, final_cck_swing_index);
-+
-+	} else if (method == MIX_MODE) {
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       " dm->default_ofdm_index=%d,  dm->DefaultCCKIndex=%d, dm->absolute_ofdm_swing_idx[rf_path]=%d, dm->remnant_cck_swing_idx=%d   rf_path = %d\n",
-+		       cali_info->default_ofdm_index,
-+		       cali_info->default_cck_index,
-+		       cali_info->absolute_ofdm_swing_idx[rf_path],
-+		       cali_info->remnant_cck_swing_idx, rf_path);
-+
-+		final_ofdm_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
-+		final_cck_swing_index = cali_info->default_cck_index + cali_info->absolute_ofdm_swing_idx[rf_path];
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       " dm->default_ofdm_index=%d,  dm->DefaultCCKIndex=%d, dm->absolute_ofdm_swing_idx[rf_path]=%d   rf_path = %d\n",
-+		       cali_info->default_ofdm_index,
-+		       cali_info->default_cck_index,
-+		       cali_info->absolute_ofdm_swing_idx[rf_path], rf_path);
-+
-+		RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+		       " final_ofdm_swing_index=%d,  final_cck_swing_index=%d rf_path=%d\n",
-+		       final_ofdm_swing_index, final_cck_swing_index, rf_path);
-+
-+		if (final_ofdm_swing_index > pwr_tracking_limit_ofdm) { /*BBSwing higher then Limit*/
-+			cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index - pwr_tracking_limit_ofdm;
-+
-+			set_iqk_matrix_8703b(dm, pwr_tracking_limit_ofdm, RF_PATH_A,
-+					     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
-+					     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
-+
-+			cali_info->modify_tx_agc_flag_path_a = true;
-+			odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, OFDM);
-+			odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, HT_MCS0_MCS7);
-+
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       " ******Path_A Over BBSwing Limit, pwr_tracking_limit = %d, Remnant tx_agc value = %d\n",
-+			       pwr_tracking_limit_ofdm,
-+			       cali_info->remnant_ofdm_swing_idx[rf_path]);
-+		} else if (final_ofdm_swing_index < 0) {
-+			cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index;
-+
-+			set_iqk_matrix_8703b(dm, 0, RF_PATH_A,
-+					     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
-+					     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
-+
-+			cali_info->modify_tx_agc_flag_path_a = true;
-+			odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, OFDM);
-+			odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, HT_MCS0_MCS7);
-+
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       " ******Path_A Lower then BBSwing lower bound  0, Remnant tx_agc value = %d\n",
-+			       cali_info->remnant_ofdm_swing_idx[rf_path]);
-+		} else {
-+			set_iqk_matrix_8703b(dm, final_ofdm_swing_index, RF_PATH_A,
-+					     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][0],
-+					     cali_info->iqk_matrix_reg_setting[channel_mapped_index].value[0][1]);
-+
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       " ******Path_A Compensate with BBSwing, final_ofdm_swing_index = %d\n",
-+			       final_ofdm_swing_index);
-+
-+			if (cali_info->modify_tx_agc_flag_path_a) { /*If tx_agc has changed, reset tx_agc again*/
-+				cali_info->remnant_ofdm_swing_idx[rf_path] = 0;
-+				odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, OFDM);
-+				odm_set_tx_power_index_by_rate_section(dm, (enum rf_path)rf_path, *dm->channel, HT_MCS0_MCS7);
-+				cali_info->modify_tx_agc_flag_path_a = false;
-+
-+				RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+				       " ******Path_A dm->Modify_TxAGC_Flag = false\n");
-+			}
-+		}
-+		if (final_cck_swing_index > pwr_tracking_limit_cck) {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       " final_cck_swing_index(%d) > pwr_tracking_limit_cck(%d)\n",
-+			       final_cck_swing_index, pwr_tracking_limit_cck);
-+
-+			cali_info->remnant_cck_swing_idx = final_cck_swing_index - pwr_tracking_limit_cck;
-+
-+			set_cck_filter_coefficient_8703b(dm, pwr_tracking_limit_cck);
-+
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "******Path_A CCK Over Limit, pwr_tracking_limit_cck = %d, dm->remnant_cck_swing_idx  = %d\n",
-+			       pwr_tracking_limit_cck,
-+			       cali_info->remnant_cck_swing_idx);
-+
-+			cali_info->modify_tx_agc_flag_path_a_cck = true;
-+
-+			odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, CCK);
-+
-+		} else if (final_cck_swing_index < 0) { /* Lowest CCK index = 0 */
-+
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       " final_cck_swing_index(%d) < 0      pwr_tracking_limit_cck(%d)\n",
-+			       final_cck_swing_index, pwr_tracking_limit_cck);
-+
-+			cali_info->remnant_cck_swing_idx = final_cck_swing_index;
-+
-+			set_cck_filter_coefficient_8703b(dm, 0);
-+
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "******Path_A CCK Under Limit, pwr_tracking_limit_cck = %d, dm->remnant_cck_swing_idx  = %d\n",
-+			       0, cali_info->remnant_cck_swing_idx);
-+
-+			cali_info->modify_tx_agc_flag_path_a_cck = true;
-+
-+			odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, CCK);
-+
-+		} else {
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       " else final_cck_swing_index=%d      pwr_tracking_limit_cck(%d)\n",
-+			       final_cck_swing_index, pwr_tracking_limit_cck);
-+
-+			set_cck_filter_coefficient_8703b(dm, final_cck_swing_index);
-+
-+			RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+			       "******Path_A CCK Compensate with BBSwing, final_cck_swing_index = %d\n",
-+			       final_cck_swing_index);
-+
-+			cali_info->modify_tx_agc_flag_path_a_cck = false;
-+
-+			cali_info->remnant_cck_swing_idx = 0;
-+
-+			if (cali_info->modify_tx_agc_flag_path_a_cck) { /*If tx_agc has changed, reset tx_agc again*/
-+				cali_info->remnant_cck_swing_idx = 0;
-+				odm_set_tx_power_index_by_rate_section(dm, RF_PATH_A, *dm->channel, CCK);
-+				cali_info->modify_tx_agc_flag_path_a_cck = false;
-+			}
-+		}
-+
-+	} else {
-+		return; /* This method is not supported. */
-+	}
-+}
-+
-+void get_delta_swing_table_8703b(void *dm_void, u8 **temperature_up_a,
-+				 u8 **temperature_down_a, u8 **temperature_up_b,
-+				 u8 **temperature_down_b)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ADAPTER *adapter = dm->adapter;
-+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
-+	struct _hal_rf_ *rf = &(dm->rf_table);
-+	u8 tx_rate = 0xFF;
-+	u8 channel = *dm->channel;
-+
-+	if (*dm->mp_mode == true) {
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+#if (MP_DRIVER == 1)
-+		PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
-+
-+		tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
-+#endif
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+#ifdef CONFIG_MP_INCLUDED
-+		PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
-+
-+		tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
-+#endif
-+#endif
-+#endif
-+	} else {
-+		u16 rate = *(dm->forced_data_rate);
-+
-+		if (!rate) { /*auto rate*/
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+			tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+			if (dm->number_linked_client != 0)
-+				tx_rate = hw_rate_to_m_rate(dm->tx_rate);
-+			else
-+				tx_rate = rf->p_rate_index;
-+#endif
-+		} else /*force rate*/
-+			tx_rate = (u8)rate;
-+	}
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Power Tracking tx_rate=0x%X\n",
-+	       tx_rate);
-+
-+	if (1 <= channel && channel <= 14) {
-+		if (IS_CCK_RATE(tx_rate)) {
-+			*temperature_up_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
-+			*temperature_down_a = cali_info->delta_swing_table_idx_2g_cck_a_n;
-+			*temperature_up_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
-+			*temperature_down_b = cali_info->delta_swing_table_idx_2g_cck_b_n;
-+		} else {
-+			*temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
-+			*temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
-+			*temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
-+			*temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
-+		}
-+	} else {
-+		*temperature_up_a = (u8 *)delta_swing_table_idx_2ga_p_8188e;
-+		*temperature_down_a = (u8 *)delta_swing_table_idx_2ga_n_8188e;
-+		*temperature_up_b = (u8 *)delta_swing_table_idx_2ga_p_8188e;
-+		*temperature_down_b = (u8 *)delta_swing_table_idx_2ga_n_8188e;
-+	}
-+
-+	return;
-+}
-+
-+void get_delta_swing_xtal_table_8703b(void *dm_void, s8 **temperature_up_xtal,
-+				      s8 **temperature_down_xtal)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
-+
-+	*temperature_up_xtal = cali_info->delta_swing_table_xtal_p;
-+	*temperature_down_xtal = cali_info->delta_swing_table_xtal_n;
-+}
-+
-+void odm_txxtaltrack_set_xtal_8703b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
-+
-+	s8 crystal_cap;
-+
-+	crystal_cap = dm->dm_cfo_track.crystal_cap_default & 0x3F;
-+	crystal_cap = crystal_cap + cali_info->xtal_offset;
-+
-+	if (crystal_cap < 0)
-+		crystal_cap = 0;
-+	else if (crystal_cap > 63)
-+		crystal_cap = 63;
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK,
-+	       "crystal_cap(%d)= dm->dm_cfo_track.crystal_cap_default(%d) + cali_info->xtal_offset(%d)\n",
-+	       crystal_cap, dm->dm_cfo_track.crystal_cap_default, cali_info->xtal_offset);
-+
-+	odm_set_bb_reg(dm, REG_MAC_PHY_CTRL, 0xFFF000, (crystal_cap | (crystal_cap << 6)));
-+
-+	RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "crystal_cap(0x2c)  0x%X\n",
-+	       odm_get_bb_reg(dm, REG_MAC_PHY_CTRL, 0xFFF000));
-+}
-+
-+void configure_txpower_track_8703b(struct txpwrtrack_cfg *config)
-+{
-+	config->swing_table_size_cck = CCK_TABLE_SIZE;
-+	config->swing_table_size_ofdm = OFDM_TABLE_SIZE;
-+	config->threshold_iqk = IQK_THRESHOLD;
-+	config->average_thermal_num = AVG_THERMAL_NUM_8703B;
-+	config->rf_path_count = MAX_PATH_NUM_8703B;
-+	config->thermal_reg_addr = RF_T_METER_8703B;
-+
-+	config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr_8703b;
-+	config->do_iqk = do_iqk_8703b;
-+	config->phy_lc_calibrate = halrf_lck_trigger;
-+	config->get_delta_swing_table = get_delta_swing_table_8703b;
-+	config->get_delta_swing_xtal_table = get_delta_swing_xtal_table_8703b;
-+	config->odm_txxtaltrack_set_xtal = odm_txxtaltrack_set_xtal_8703b;
-+}
-+
-+/* 1 7.	IQK */
-+#define MAX_TOLERANCE 5
-+#define IQK_DELAY_TIME 1 /* ms */
-+
-+u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
-+	phy_path_a_iqk_8703b(
-+		struct dm_struct *dm)
-+{
-+	u32 reg_eac, reg_e94, reg_e9c;
-+	u8 result = 0x00, ktime;
-+	u32 original_path, original_gnt;
-+
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]TX IQK!\n");
-+
-+	/*8703b IQK v2.0 20150713*/
-+	/*1 Tx IQK*/
-+	/*IQK setting*/
-+	odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
-+	odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
-+	/*path-A IQK setting*/
-+	odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
-+	odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
-+	odm_set_bb_reg(dm, REG_TX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
-+	odm_set_bb_reg(dm, REG_RX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
-+	/*	odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x8214010a);*/
-+	odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x8214030f);
-+	odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28110000);
-+	odm_set_bb_reg(dm, REG_TX_IQK_PI_B, MASKDWORD, 0x82110000);
-+	odm_set_bb_reg(dm, REG_RX_IQK_PI_B, MASKDWORD, 0x28110000);
-+
-+	/*LO calibration setting*/
-+	odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x00462911);
-+
-+	/*leave IQK mode*/
-+	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
-+
-+	/*PA, PAD setting*/
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x1);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x55, 0x0007f, 0x7);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x7f, RFREGOFFSETMASK, 0x0d400);
-+
-+	/*enter IQK mode*/
-+	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
-+
-+#if 1
-+	/*path setting*/
-+	/*Save Original path Owner, Original GNT*/
-+	original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
-+	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
-+	ODM_delay_ms(1);
-+	original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
-+
-+	/*set GNT_WL=1/GNT_BT=0  and path owner to WiFi for pause BT traffic*/
-+	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x00007700);
-+	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
-+	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1); /*0x70[26] =1 --> path Owner to WiFi*/
-+#endif
-+
-+	/*One shot, path A LOK & IQK*/
-+	odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
-+	odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
-+
-+	/* delay x ms */
-+	ODM_delay_ms(IQK_DELAY_TIME_8703B);
-+	ktime = 0;
-+	while ((odm_get_bb_reg(dm, R_0xe90, MASKDWORD) == 0) && ktime < 10) {
-+		ODM_delay_ms(5);
-+		ktime++;
-+	}
-+
-+#if 1
-+	/*path setting*/
-+	/*Restore GNT_WL/GNT_BT  and path owner*/
-+	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
-+	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
-+	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
-+
-+	original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
-+	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
-+	ODM_delay_ms(1);
-+	original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
-+
-+#endif
-+
-+	/*leave IQK mode*/
-+	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
-+	/*	PA/PAD controlled by 0x0*/
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x0);
-+
-+	/* Check failed*/
-+	reg_eac = odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
-+	reg_e94 = odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD);
-+	reg_e9c = odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD);
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac = 0x%x\n", reg_eac);
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", reg_e94,
-+	       reg_e9c);
-+	/*monitor image power before & after IQK*/
-+	RF_DBG(dm, DBG_RF_IQK,
-+	       "[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
-+	       odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
-+	       odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
-+
-+	if (!(reg_eac & BIT(28)) &&
-+	    (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
-+	    (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
-+
-+		result |= 0x01;
-+
-+	return result;
-+}
-+
-+u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
-+	phy_path_a_rx_iqk_8703b(
-+		struct dm_struct *dm)
-+{
-+	u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u4tmp, tmp;
-+	u8 result = 0x00, ktime;
-+	u32 original_path, original_gnt;
-+
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]RX IQK:Get TXIMR setting\n");
-+	/* 1 Get TX_XY */
-+
-+	/* IQK setting */
-+	odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
-+	odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
-+
-+	/* path-A IQK setting */
-+	odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
-+	odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
-+	odm_set_bb_reg(dm, REG_TX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
-+	odm_set_bb_reg(dm, REG_RX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
-+
-+	/*	odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82160c1f); */
-+	odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x8216000f);
-+	odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28110000);
-+	odm_set_bb_reg(dm, REG_TX_IQK_PI_B, MASKDWORD, 0x82110000);
-+	odm_set_bb_reg(dm, REG_RX_IQK_PI_B, MASKDWORD, 0x28110000);
-+
-+	/* LO calibration setting */
-+	odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x0046a911);
-+
-+	/* leave IQK mode */
-+	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
-+
-+	/* modify RXIQK mode table */
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_RCK_OS, RFREGOFFSETMASK, 0x30000);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G1, RFREGOFFSETMASK, 0x00007);
-+	/*IQK PA off*/
-+	/*	odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0xf7fb7); */
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0x57db7);
-+
-+	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
-+
-+#if 1
-+	/*path setting*/
-+	/*Save Original path Owner, Original GNT*/
-+	original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
-+	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
-+	ODM_delay_ms(1);
-+	original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
-+
-+	/*set GNT_WL=1/GNT_BT=0  and path owner to WiFi for pause BT traffic*/
-+	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x00007700);
-+	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
-+	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1); /*0x70[26] =1 --> path Owner to WiFi*/
-+#endif
-+
-+	/* One shot, path A LOK & IQK */
-+	odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
-+	odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
-+
-+	/* delay x ms */
-+	ODM_delay_ms(IQK_DELAY_TIME_8703B);
-+	ktime = 0;
-+	while ((odm_get_bb_reg(dm, R_0xe90, MASKDWORD) == 0) && ktime < 10) {
-+		ODM_delay_ms(5);
-+		ktime++;
-+	}
-+
-+#if 1
-+	/*path setting*/
-+	/*Restore GNT_WL/GNT_BT  and path owner*/
-+	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
-+	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
-+	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
-+
-+	original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
-+	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
-+	ODM_delay_ms(1);
-+	original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
-+
-+#endif
-+
-+	/* leave IQK mode */
-+	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
-+
-+	/* Check failed */
-+	reg_eac = odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
-+	reg_e94 = odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD);
-+	reg_e9c = odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD);
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac = 0x%x\n", reg_eac);
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe94 = 0x%x, 0xe9c = 0x%x\n", reg_e94,
-+	       reg_e9c);
-+	/*monitor image power before & after IQK*/
-+	RF_DBG(dm, DBG_RF_IQK,
-+	       "[IQK]0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
-+	       odm_get_bb_reg(dm, R_0xe90, MASKDWORD),
-+	       odm_get_bb_reg(dm, R_0xe98, MASKDWORD));
-+
-+	/* Allen 20131125 */
-+	tmp = (reg_e9c & 0x03FF0000) >> 16;
-+	if ((tmp & 0x200) > 0)
-+		tmp = 0x400 - tmp;
-+
-+	if (!(reg_eac & BIT(28)) &&
-+	    (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
-+	    (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
-+
-+		result |= 0x01;
-+	else /* if Tx not OK, ignore Rx */
-+		return result;
-+
-+	u4tmp = 0x80007C00 | (reg_e94 & 0x3FF0000) | ((reg_e9c & 0x3FF0000) >> 16);
-+	odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, u4tmp);
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xe40 = 0x%x u4tmp = 0x%x\n",
-+	       odm_get_bb_reg(dm, REG_TX_IQK, MASKDWORD), u4tmp);
-+
-+	/* 1 RX IQK */
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]RX IQK\n");
-+
-+	/* IQK setting */
-+	odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
-+
-+	/* path-A IQK setting */
-+	odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
-+	odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
-+	odm_set_bb_reg(dm, REG_TX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
-+	odm_set_bb_reg(dm, REG_RX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
-+
-+	odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82110000);
-+	odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28160c1f);
-+	/*	odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x2816001f);*/
-+	odm_set_bb_reg(dm, REG_TX_IQK_PI_B, MASKDWORD, 0x82110000);
-+	odm_set_bb_reg(dm, REG_RX_IQK_PI_B, MASKDWORD, 0x28110000);
-+
-+	/* LO calibration setting */
-+	odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x0046a8d1);
-+
-+	/* modify RXIQK mode table */
-+	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_RCK_OS, RFREGOFFSETMASK, 0x30000);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G1, RFREGOFFSETMASK, 0x00007);
-+	/*PA off*/
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, RFREGOFFSETMASK, 0xf7d77);
-+
-+	/*PA, PAD setting*/
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x1);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x55, 0x0007f, 0x5);
-+
-+	/*enter IQK mode*/
-+	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
-+
-+#if 1
-+	/*path setting*/
-+	/*Save Original path Owner, Original GNT*/
-+	original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
-+	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
-+	ODM_delay_ms(1);
-+	original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
-+
-+	/*set GNT_WL=1/GNT_BT=0  and path owner to WiFi for pause BT traffic*/
-+	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, 0x00007700);
-+	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc0020038); /*0x38[15:8] = 0x77*/
-+	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, BIT(26), 0x1); /*0x70[26] =1 --> path Owner to WiFi*/
-+#endif
-+
-+	/* One shot, path A LOK & IQK */
-+	odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
-+	odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
-+
-+	/* delay x ms */
-+	ODM_delay_ms(IQK_DELAY_TIME_8703B);
-+	ktime = 0;
-+	while ((odm_get_bb_reg(dm, R_0xe90, MASKDWORD) == 0) && ktime < 10) {
-+		ODM_delay_ms(5);
-+		ktime++;
-+	}
-+
-+#if 1
-+	/*path setting*/
-+	/*Restore GNT_WL/GNT_BT  and path owner*/
-+	odm_set_bb_reg(dm, REG_LTECOEX_WRITE_DATA, MASKDWORD, original_gnt);
-+	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0xc00f0038);
-+	odm_set_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, 0xffffffff, original_path);
-+
-+	original_path = odm_get_mac_reg(dm, REG_LTECOEX_PATH_CONTROL, MASKDWORD); /*save 0x70*/
-+	odm_set_bb_reg(dm, REG_LTECOEX_CTRL, MASKDWORD, 0x800f0038);
-+	ODM_delay_ms(1);
-+	original_gnt = odm_get_bb_reg(dm, REG_LTECOEX_READ_DATA, MASKDWORD); /*save 0x38*/
-+
-+#endif
-+
-+	/*leave IQK mode*/
-+	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
-+	/*	PA/PAD controlled by 0x0 */
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, 0x800, 0x0);
-+
-+	/* Check failed */
-+	reg_eac = odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD);
-+	reg_ea4 = odm_get_bb_reg(dm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD);
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xeac = 0x%x\n", reg_eac);
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]0xea4 = 0x%x, 0xeac = 0x%x\n", reg_ea4,
-+	       reg_eac);
-+	/* monitor image power before & after IQK */
-+	RF_DBG(dm, DBG_RF_IQK,
-+	       "[IQK]0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n",
-+	       odm_get_bb_reg(dm, R_0xea0, MASKDWORD),
-+	       odm_get_bb_reg(dm, R_0xea8, MASKDWORD));
-+
-+	/* Allen 20131125 */
-+	tmp = (reg_eac & 0x03FF0000) >> 16;
-+	if ((tmp & 0x200) > 0)
-+		tmp = 0x400 - tmp;
-+
-+	if (!(reg_eac & BIT(27)) && /*if Tx is OK, check whether Rx is OK*/
-+	    (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
-+	    (((reg_eac & 0x03FF0000) >> 16) != 0x36) &&
-+	    (((reg_ea4 & 0x03FF0000) >> 16) < 0x11a) &&
-+	    (((reg_ea4 & 0x03FF0000) >> 16) > 0xe6) &&
-+	    tmp < 0x1a)
-+		result |= 0x02;
-+	else /* if Tx not OK, ignore Rx */
-+		RF_DBG(dm, DBG_RF_IQK, "path A Rx IQK fail!!\n");
-+
-+	return result;
-+}
-+
-+void _phy_path_a_fill_iqk_matrix8703b(struct dm_struct *dm, boolean is_iqk_ok,
-+				      s32 result[][8], u8 final_candidate,
-+				      boolean is_tx_only)
-+{
-+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
-+	u32 oldval_0, X, TX0_A, reg, tmp0xc80, tmp0xc94, tmp0xc4c, tmp0xc14, tmp0xca0;
-+	s32 Y, TX0_C;
-+
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]path A IQ Calibration %s !\n",
-+	       (is_iqk_ok) ? "Success" : "Failed");
-+
-+	if (final_candidate == 0xFF)
-+		return;
-+
-+	else if (is_iqk_ok) {
-+		oldval_0 = (odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) >> 22) & 0x3FF;
-+
-+		X = result[final_candidate][0];
-+		if ((X & 0x00000200) != 0)
-+			X = X | 0xFFFFFC00;
-+		TX0_A = (X * oldval_0) >> 8;
-+		RF_DBG(dm, DBG_RF_IQK,
-+		       "[IQK]X = 0x%x, TX0_A = 0x%x, oldval_0 0x%x\n", X, TX0_A,
-+		       oldval_0);
-+		tmp0xc80 = (odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) & 0xfffffc00) | (TX0_A & 0x3ff);
-+		tmp0xc4c = (((X * oldval_0 >> 7) & 0x1) << 31) | (odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & 0x7fffffff);
-+
-+		Y = result[final_candidate][1];
-+		if ((Y & 0x00000200) != 0)
-+			Y = Y | 0xFFFFFC00;
-+
-+		/* 2 Tx IQC */
-+		TX0_C = (Y * oldval_0) >> 8;
-+		RF_DBG(dm, DBG_RF_IQK, "[IQK]Y = 0x%x, TX = 0x%x\n", Y, TX0_C);
-+
-+		tmp0xc94 = (((TX0_C & 0x3C0) >> 6) << 28) | (odm_get_bb_reg(dm, REG_OFDM_0_XC_TX_AFE, MASKDWORD) & 0x0fffffff);
-+
-+		cali_info->tx_iqc_8703b[idx_0xc94][KEY] = REG_OFDM_0_XC_TX_AFE;
-+		cali_info->tx_iqc_8703b[idx_0xc94][VAL] = tmp0xc94;
-+
-+		tmp0xc80 = (tmp0xc80 & 0xffc0ffff) | (TX0_C & 0x3F) << 16;
-+
-+		cali_info->tx_iqc_8703b[idx_0xc80][KEY] = REG_OFDM_0_XA_TX_IQ_IMBALANCE;
-+		cali_info->tx_iqc_8703b[idx_0xc80][VAL] = tmp0xc80;
-+
-+		tmp0xc4c = (tmp0xc4c & 0xdfffffff) | (((Y * oldval_0 >> 7) & 0x1) << 29);
-+
-+		cali_info->tx_iqc_8703b[idx_0xc4c][KEY] = REG_OFDM_0_ECCA_THRESHOLD;
-+		cali_info->tx_iqc_8703b[idx_0xc4c][VAL] = tmp0xc4c;
-+
-+		if (is_tx_only) {
-+			RF_DBG(dm, DBG_RF_IQK, "[IQK]%s only Tx OK\n",
-+			       __func__);
-+
-+			/* <20130226, Kordan> Saving RxIQC, otherwise not initialized. */
-+			cali_info->rx_iqc_8703b[idx_0xca0][KEY] = REG_OFDM_0_RX_IQ_EXT_ANTA;
-+			cali_info->rx_iqc_8703b[idx_0xca0][VAL] = 0xfffffff & odm_get_bb_reg(dm, REG_OFDM_0_RX_IQ_EXT_ANTA, MASKDWORD);
-+			cali_info->rx_iqc_8703b[idx_0xc14][KEY] = REG_OFDM_0_XA_RX_IQ_IMBALANCE;
-+			cali_info->rx_iqc_8703b[idx_0xc14][VAL] = 0x40000100;
-+			return;
-+		}
-+
-+		reg = result[final_candidate][2];
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+		if (RTL_ABS(reg, 0x100) >= 16)
-+			reg = 0x100;
-+#endif
-+
-+		/* 2 Rx IQC */
-+		tmp0xc14 = (0x40000100 & 0xfffffc00) | reg;
-+
-+		reg = result[final_candidate][3] & 0x3F;
-+		tmp0xc14 = (tmp0xc14 & 0xffff03ff) | (reg << 10);
-+
-+		cali_info->rx_iqc_8703b[idx_0xc14][KEY] = REG_OFDM_0_XA_RX_IQ_IMBALANCE;
-+		cali_info->rx_iqc_8703b[idx_0xc14][VAL] = tmp0xc14;
-+
-+		reg = (result[final_candidate][3] >> 6) & 0xF;
-+		tmp0xca0 = odm_get_bb_reg(dm, REG_OFDM_0_RX_IQ_EXT_ANTA, 0x0fffffff) | (reg << 28);
-+
-+		cali_info->rx_iqc_8703b[idx_0xca0][KEY] = REG_OFDM_0_RX_IQ_EXT_ANTA;
-+		cali_info->rx_iqc_8703b[idx_0xca0][VAL] = tmp0xca0;
-+	}
-+}
-+
-+#if 0
-+void
-+_phy_path_b_fill_iqk_matrix8703b(
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	struct dm_struct		*dm,
-+#else
-+	void	*adapter,
-+#endif
-+	boolean	is_iqk_ok,
-+	s32		result[][8],
-+	u8		final_candidate,
-+	boolean		is_tx_only			/* do Tx only */
-+)
-+{
-+	u32	oldval_1, X, TX1_A, reg, tmp0xc80, tmp0xc94, tmp0xc4c, tmp0xc14, tmp0xca0;
-+	s32	Y, TX1_C;
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	struct dm_struct		*dm = &hal_data->odmpriv;
-+#endif
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct dm_struct		*dm = &hal_data->DM_OutSrc;
-+#endif
-+#endif
-+	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
-+
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]path B IQ Calibration %s !\n",
-+	       (is_iqk_ok) ? "Success" : "Failed");
-+
-+	if (final_candidate == 0xFF)
-+		return;
-+
-+	else if (is_iqk_ok) {
-+		oldval_1 = (odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) >> 22) & 0x3FF;
-+
-+
-+		X = result[final_candidate][4];
-+		if ((X & 0x00000200) != 0)
-+			X = X | 0xFFFFFC00;
-+		TX1_A = (X * oldval_1) >> 8;
-+		RF_DBG(dm, DBG_RF_IQK, "[IQK]X = 0x%x, TX1_A = 0x%x\n", X,
-+		       TX1_A);
-+
-+		tmp0xc80 = (odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD) & 0xfffffc00) | (TX1_A & 0x3ff);
-+		tmp0xc4c = (((X * oldval_1 >> 7) & 0x1) << 31) | (odm_get_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKDWORD) & 0x7fffffff);
-+
-+		Y = result[final_candidate][5];
-+		if ((Y & 0x00000200) != 0)
-+			Y = Y | 0xFFFFFC00;
-+
-+		TX1_C = (Y * oldval_1) >> 8;
-+		RF_DBG(dm, DBG_RF_IQK, "[IQK]Y = 0x%x, TX1_C = 0x%x\n", Y,
-+		       TX1_C);
-+
-+		/*2 Tx IQC*/
-+
-+		tmp0xc94 = (((TX1_C & 0x3C0) >> 6) << 28) | (odm_get_bb_reg(dm, REG_OFDM_0_XC_TX_AFE, MASKDWORD) & 0x0fffffff);
-+
-+		cali_info->tx_iqc_8703b[PATH_S0][idx_0xc94][KEY] = REG_OFDM_0_XC_TX_AFE;
-+		cali_info->tx_iqc_8703b[PATH_S0][idx_0xc94][VAL] = tmp0xc94;
-+
-+		tmp0xc80 = (tmp0xc80 & 0xffc0ffff) | (TX1_C & 0x3F) << 16;
-+		cali_info->tx_iqc_8703b[PATH_S0][idx_0xc80][KEY] = REG_OFDM_0_XA_TX_IQ_IMBALANCE;
-+		cali_info->tx_iqc_8703b[PATH_S0][idx_0xc80][VAL] = tmp0xc80;
-+
-+		tmp0xc4c = (tmp0xc4c & 0xdfffffff) | (((Y * oldval_1 >> 7) & 0x1) << 29);
-+		cali_info->tx_iqc_8703b[PATH_S0][idx_0xc4c][KEY] = REG_OFDM_0_ECCA_THRESHOLD;
-+		cali_info->tx_iqc_8703b[PATH_S0][idx_0xc4c][VAL] = tmp0xc4c;
-+
-+		if (is_tx_only) {
-+			RF_DBG(dm, DBG_RF_IQK, "[IQK]%s only Tx OK\n",
-+			       __func__);
-+
-+			cali_info->rx_iqc_8703b[PATH_S0][idx_0xc14][KEY] = REG_OFDM_0_XA_RX_IQ_IMBALANCE;
-+			cali_info->rx_iqc_8703b[PATH_S0][idx_0xc14][VAL] = 0x40000100;
-+			cali_info->rx_iqc_8703b[PATH_S0][idx_0xca0][KEY] = REG_OFDM_0_RX_IQ_EXT_ANTA;
-+			cali_info->rx_iqc_8703b[PATH_S0][idx_0xca0][VAL] = 0x0fffffff & odm_get_bb_reg(dm, REG_OFDM_0_RX_IQ_EXT_ANTA, MASKDWORD);
-+			return;
-+		}
-+
-+		/* 2 Rx IQC */
-+		reg = result[final_candidate][6];
-+		tmp0xc14 = (0x40000100 & 0xfffffc00) | reg;
-+
-+		reg = result[final_candidate][7] & 0x3F;
-+		tmp0xc14 = (tmp0xc14 & 0xffff03ff) | (reg << 10);
-+
-+		cali_info->rx_iqc_8703b[PATH_S0][idx_0xc14][KEY] = REG_OFDM_0_XA_RX_IQ_IMBALANCE;
-+		cali_info->rx_iqc_8703b[PATH_S0][idx_0xc14][VAL] = tmp0xc14;
-+
-+		reg = (result[final_candidate][7] >> 6) & 0xF;
-+		tmp0xca0 = odm_get_bb_reg(dm, REG_OFDM_0_RX_IQ_EXT_ANTA, 0x0fffffff) | (reg << 28);
-+
-+		cali_info->rx_iqc_8703b[PATH_S0][idx_0xca0][KEY] = REG_OFDM_0_RX_IQ_EXT_ANTA;
-+		cali_info->rx_iqc_8703b[PATH_S0][idx_0xca0][VAL] = tmp0xca0;
-+	}
-+}
-+#endif
-+
-+boolean
-+odm_set_iqc_by_rfpath_8703b(struct dm_struct *dm)
-+{
-+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
-+
-+	if (cali_info->tx_iqc_8703b[idx_0xc80][VAL] != 0x0 && cali_info->rx_iqc_8703b[idx_0xc14][VAL] != 0x0) {
-+		RF_DBG(dm, DBG_RF_IQK, "[IQK]reload RF IQC!!!\n");
-+		RF_DBG(dm, DBG_RF_IQK, "[IQK]0xc80 = 0x%x!!!\n",
-+		       cali_info->tx_iqc_8703b[idx_0xc80][VAL]);
-+		RF_DBG(dm, DBG_RF_IQK, "[IQK]0xc14 = 0x%x!!!\n",
-+		       cali_info->tx_iqc_8703b[idx_0xc14][VAL]);
-+
-+		/* TX IQC */
-+		odm_set_bb_reg(dm, cali_info->tx_iqc_8703b[idx_0xc94][KEY], MASKH4BITS, (cali_info->tx_iqc_8703b[idx_0xc94][VAL] >> 28));
-+		odm_set_bb_reg(dm, cali_info->tx_iqc_8703b[idx_0xc80][KEY], MASKDWORD, cali_info->tx_iqc_8703b[idx_0xc80][VAL]);
-+		odm_set_bb_reg(dm, cali_info->tx_iqc_8703b[idx_0xc4c][KEY], BIT(31), (cali_info->tx_iqc_8703b[idx_0xc4c][VAL] >> 31));
-+		odm_set_bb_reg(dm, cali_info->tx_iqc_8703b[idx_0xc4c][KEY], BIT(29), ((cali_info->tx_iqc_8703b[idx_0xc4c][VAL] & BIT(29)) >> 29));
-+
-+		/* RX IQC */
-+		odm_set_bb_reg(dm, cali_info->rx_iqc_8703b[idx_0xc14][KEY], MASKDWORD, cali_info->rx_iqc_8703b[idx_0xc14][VAL]);
-+		odm_set_bb_reg(dm, cali_info->rx_iqc_8703b[idx_0xca0][KEY], MASKDWORD, cali_info->rx_iqc_8703b[idx_0xca0][VAL]);
-+		return true;
-+
-+	} else {
-+		RF_DBG(dm, DBG_RF_IQK, "[IQK]IQC value invalid!!!\n");
-+		return false;
-+	}
-+}
-+
-+void _phy_save_adda_registers8703b(struct dm_struct *dm, u32 *adda_reg,
-+				   u32 *adda_backup, u32 register_num)
-+{
-+	u32 i;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	if (odm_check_power_status(dm) == false)
-+		return;
-+#endif
-+
-+	/*	RF_DBG(dm,DBG_RF_IQK, "Save ADDA parameters.\n"); */
-+	for (i = 0; i < register_num; i++)
-+		adda_backup[i] = odm_get_bb_reg(dm, adda_reg[i], MASKDWORD);
-+}
-+
-+void _phy_save_mac_registers8703b(struct dm_struct *dm, u32 *mac_reg,
-+				  u32 *mac_backup)
-+{
-+	u32 i;
-+
-+	/*	RF_DBG(dm,DBG_RF_IQK, "Save MAC parameters.\n"); */
-+	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
-+		mac_backup[i] = odm_read_1byte(dm, mac_reg[i]);
-+
-+	mac_backup[i] = odm_read_4byte(dm, mac_reg[i]);
-+}
-+
-+void _phy_reload_adda_registers8703b(struct dm_struct *dm, u32 *adda_reg,
-+				     u32 *adda_backup, u32 regiester_num)
-+{
-+	u32 i;
-+
-+	/*	RF_DBG(dm,DBG_RF_IQK, "Reload ADDA power saving parameters !\n"); */
-+	for (i = 0; i < regiester_num; i++)
-+		odm_set_bb_reg(dm, adda_reg[i], MASKDWORD, adda_backup[i]);
-+}
-+
-+void _phy_reload_mac_registers8703b(struct dm_struct *dm, u32 *mac_reg,
-+				    u32 *mac_backup)
-+{
-+	u32 i;
-+
-+	/*	RF_DBG(dm,DBG_RF_IQK,  "Reload MAC parameters !\n"); */
-+	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
-+		odm_write_1byte(dm, mac_reg[i], (u8)mac_backup[i]);
-+
-+	odm_write_4byte(dm, mac_reg[i], mac_backup[i]);
-+}
-+
-+void _phy_path_adda_on8703b(struct dm_struct *dm, u32 *adda_reg,
-+			    boolean is_path_a_on)
-+{
-+	u32 path_on;
-+	u32 i;
-+
-+	/*	RF_DBG(dm,DBG_RF_IQK, "ADDA ON.\n"); */
-+	path_on = 0x03c00014;
-+	for (i = 0; i < IQK_ADDA_REG_NUM; i++)
-+		odm_set_bb_reg(dm, adda_reg[i], MASKDWORD, path_on);
-+}
-+
-+void _phy_mac_setting_calibration8703b(struct dm_struct *dm, u32 *mac_reg,
-+				       u32 *mac_backup)
-+{
-+	u32 i = 0;
-+
-+	/*	RF_DBG(dm,DBG_RF_IQK, "MAC settings for Calibration.\n"); */
-+	odm_write_1byte(dm, mac_reg[i], 0x3F);
-+	for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
-+		odm_write_1byte(dm, mac_reg[i], (u8)(mac_backup[i] & (~BIT(3))));
-+	/*remove 0x40[5]setting for coex reason */
-+	/*odm_write_1byte(dm, mac_reg[i], (u8)(mac_backup[i] & (~BIT(5))));*/
-+}
-+
-+boolean
-+phy_simularity_compare_8703b(struct dm_struct *dm, s32 result[][8], u8 c1,
-+			     u8 c2, boolean is2t)
-+{
-+	u32 i, j, diff, simularity_bit_map, bound = 0;
-+	u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
-+	boolean is_result = true;
-+
-+	/* #if !(DM_ODM_SUPPORT_TYPE & ODM_AP) */
-+	/*	bool		is2T = IS_92C_SERIAL( hal_data->version_id);
-+	 * #else */
-+	/* #endif */
-+
-+	s32 tmp1 = 0, tmp2 = 0;
-+
-+	if (is2t)
-+		bound = 8;
-+	else
-+		bound = 4;
-+
-+	/*	RF_DBG(dm,DBG_RF_IQK, "===> IQK:phy_simularity_compare_8192e c1 %d c2 %d!!!\n", c1, c2); */
-+
-+	simularity_bit_map = 0;
-+
-+	for (i = 0; i < bound; i++) {
-+		if (i == 1 || i == 3 || i == 5 || i == 7) {
-+			if ((result[c1][i] & 0x00000200) != 0)
-+				tmp1 = result[c1][i] | 0xFFFFFC00;
-+			else
-+				tmp1 = result[c1][i];
-+
-+			if ((result[c2][i] & 0x00000200) != 0)
-+				tmp2 = result[c2][i] | 0xFFFFFC00;
-+			else
-+				tmp2 = result[c2][i];
-+		} else {
-+			tmp1 = result[c1][i];
-+			tmp2 = result[c2][i];
-+		}
-+
-+		diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
-+
-+		if (diff > MAX_TOLERANCE) {
-+			/*			RF_DBG(dm,DBG_RF_IQK,  "IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n",  diff, i, result[c1][i], result[c2][i]); */
-+
-+			if ((i == 2 || i == 6) && !simularity_bit_map) {
-+				if (result[c1][i] + result[c1][i + 1] == 0)
-+					final_candidate[(i / 4)] = c2;
-+				else if (result[c2][i] + result[c2][i + 1] == 0)
-+					final_candidate[(i / 4)] = c1;
-+				else
-+					simularity_bit_map = simularity_bit_map | (1 << i);
-+			} else
-+				simularity_bit_map = simularity_bit_map | (1 << i);
-+		}
-+	}
-+
-+	/*	RF_DBG(dm,DBG_RF_IQK, "IQK:phy_simularity_compare_8192e simularity_bit_map   %x !!!\n", simularity_bit_map); */
-+
-+	if (simularity_bit_map == 0) {
-+		for (i = 0; i < (bound / 4); i++) {
-+			if (final_candidate[i] != 0xFF) {
-+				for (j = i * 4; j < (i + 1) * 4 - 2; j++)
-+					result[3][j] = result[final_candidate[i]][j];
-+				is_result = false;
-+			}
-+		}
-+		return is_result;
-+	}
-+
-+	if (!(simularity_bit_map & 0x03)) { /*path A TX OK*/
-+		for (i = 0; i < 2; i++)
-+			result[3][i] = result[c1][i];
-+	}
-+
-+	if (!(simularity_bit_map & 0x0c)) { /*path A RX OK*/
-+		for (i = 2; i < 4; i++)
-+			result[3][i] = result[c1][i];
-+	}
-+
-+	if (!(simularity_bit_map & 0x30)) { /*path B TX OK*/
-+		for (i = 4; i < 6; i++)
-+			result[3][i] = result[c1][i];
-+	}
-+
-+	if (!(simularity_bit_map & 0xc0)) { /*path B RX OK*/
-+		for (i = 6; i < 8; i++)
-+			result[3][i] = result[c1][i];
-+	}
-+
-+	return false;
-+}
-+
-+void _phy_check_coex_status_8703b(struct dm_struct *dm, boolean beforek)
-+{
-+	u8 u1b_tmp;
-+	u16 count = 0;
-+	u8 h2c_parameter;
-+
-+#if MP_DRIVER != 1
-+	if (beforek) {
-+		/* Set H2C cmd to inform FW (enable). */
-+		h2c_parameter = 1;
-+		odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
-+		/* Check 0x1e6 or 100ms timeout*/
-+		count = 0;
-+		u1b_tmp = odm_read_1byte(dm, 0x1e6);
-+		while (u1b_tmp != 0x1 && count < 5000) {
-+			ODM_delay_us(20);
-+			u1b_tmp = odm_read_1byte(dm, 0x1e6);
-+			count++;
-+		}
-+
-+		if (count >= 5000)
-+			RF_DBG(dm, DBG_RF_INIT,
-+			       "[IQK]Polling 0x1e6 to 1 for WiFi calibration H2C cmd FAIL! count(%d)",
-+			       count);
-+
-+		/* Wait BT IQK finished. */
-+		/* polling 0x1e7[0]=1 or 600ms timeout */
-+		count = 0;
-+		u1b_tmp = odm_read_1byte(dm, 0x1e7);
-+		while ((!(u1b_tmp & BIT(0))) && count < 30000) {
-+			ODM_delay_us(20);
-+			u1b_tmp = odm_read_1byte(dm, 0x1e7);
-+			count++;
-+		}
-+
-+		if (count >= 30000)
-+			RF_DBG(dm, DBG_RF_INIT,
-+			       "[IQK]Waiting BT IQK finish time out! count(%d)",
-+			       count);
-+	} else {
-+		/* Set H2C cmd to inform FW (disable). */
-+		h2c_parameter = 0;
-+		odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
-+		/* Check 0x1e6 or 100ms timeout */
-+		count = 0;
-+		u1b_tmp = odm_read_1byte(dm, 0x1e6);
-+		while (u1b_tmp != 0 && count < 5000) {
-+			ODM_delay_us(20);
-+			u1b_tmp = odm_read_1byte(dm, 0x1e6);
-+			count++;
-+		}
-+
-+		if (count >= 5000)
-+			RF_DBG(dm, DBG_RF_INIT,
-+			       "[IQK]Polling 0x1e6 to 0 for WiFi calibration H2C cmd FAIL! count(%d)",
-+			       count);
-+	}
-+#endif
-+}
-+
-+void _phy_iq_calibrate_8703b(struct dm_struct *dm, s32 result[][8], u8 t)
-+{
-+	u32 i;
-+	u8 path_aok = 0x0, path_bok = 0x0;
-+	u8 tmp0xc50 = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
-+	//u8			tmp0xc58 = (u8)odm_get_bb_reg(dm, R_0xc58, MASKBYTE0);
-+	u32 ADDA_REG[IQK_ADDA_REG_NUM] = {
-+		REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH,
-+		REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
-+		REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
-+		REG_TX_OFDM_BBON, REG_TX_TO_RX,
-+		REG_TX_TO_TX, REG_RX_CCK,
-+		REG_RX_OFDM, REG_RX_WAIT_RIFS,
-+		REG_RX_TO_RX, REG_STANDBY,
-+		REG_SLEEP, REG_PMPD_ANAEN};
-+	u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {
-+		REG_TXPAUSE, REG_BCN_CTRL,
-+		REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
-+
-+	/*since 92C & 92D have the different define in IQK_BB_REG*/
-+	u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
-+		REG_OFDM_0_TRX_PATH_ENABLE, REG_OFDM_0_TR_MUX_PAR,
-+		REG_FPGA0_XCD_RF_INTERFACE_SW, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
-+		REG_FPGA0_XAB_RF_INTERFACE_SW, REG_FPGA0_XA_RF_INTERFACE_OE,
-+		REG_FPGA0_XB_RF_INTERFACE_OE, REG_CCK_0_AFE_SETTING};
-+	u32 retry_count;
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	retry_count = 2;
-+#ifdef MP_TEST
-+	if (*(dm->mp_mode))
-+		retry_count = 9;
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+#if MP_DRIVER
-+	retry_count = 1;
-+#else
-+	retry_count = 2;
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+	if (*(dm->mp_mode))
-+		retry_count = 1;
-+	else
-+		retry_count = 2;
-+#endif
-+
-+	/* Note: IQ calibration must be performed after loading*/
-+	/*PHY_REG.txt , and radio_a, radio_b.txt*/
-+
-+	/* u32 bbvalue; */
-+
-+	if (t == 0) {
-+		/*	 	 bbvalue = odm_get_bb_reg(dm, REG_FPGA0_RFMOD, MASKDWORD);
-+		 * 			RT_DISP(FINIT, INIT_IQK, ("_phy_iq_calibrate_8188e()==>0x%08x\n",bbvalue)); */
-+
-+		RF_DBG(dm, DBG_RF_IQK, "[IQK]IQ Calibration for %d times\n", t);
-+
-+		/* Save ADDA parameters, turn path A ADDA on*/
-+		_phy_save_adda_registers8703b(dm, ADDA_REG, dm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
-+		_phy_save_mac_registers8703b(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
-+		_phy_save_adda_registers8703b(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
-+	}
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]IQ Calibration for %d times\n", t);
-+
-+	_phy_path_adda_on8703b(dm, ADDA_REG, true);
-+	/* MAC settings */
-+	_phy_mac_setting_calibration8703b(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
-+	/* BB setting */
-+	/*odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT24, 0x00);*/
-+	odm_set_bb_reg(dm, REG_CCK_0_AFE_SETTING, 0x0f000000, 0xf);
-+	odm_set_bb_reg(dm, REG_OFDM_0_TRX_PATH_ENABLE, MASKDWORD, 0x03a05600);
-+	odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800e4);
-+	odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x25204000);
-+
-+/* path A TX IQK */
-+#if 1
-+
-+	for (i = 0; i < retry_count; i++) {
-+		path_aok = phy_path_a_iqk_8703b(dm);
-+		if (path_aok == 0x01) {
-+			RF_DBG(dm, DBG_RF_IQK, "[IQK]Tx IQK Success!!\n");
-+			result[t][0] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
-+			result[t][1] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
-+			break;
-+		}
-+	}
-+#endif
-+
-+/* path A RXIQK */
-+#if 1
-+
-+	for (i = 0; i < retry_count; i++) {
-+		path_aok = phy_path_a_rx_iqk_8703b(dm);
-+		if (path_aok == 0x03) {
-+			RF_DBG(dm, DBG_RF_IQK, "[IQK]Rx IQK Success!!\n");
-+			/*			result[t][0] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD)&0x3FF0000)>>16;
-+			 *			result[t][1] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD)&0x3FF0000)>>16; */
-+			result[t][2] = (odm_get_bb_reg(dm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
-+			result[t][3] = (odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
-+			break;
-+		}
-+
-+		RF_DBG(dm, DBG_RF_IQK, "[IQK]Rx IQK Fail!!\n");
-+	}
-+
-+	if (0x00 == path_aok)
-+		RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK failed!!\n");
-+
-+#endif
-+
-+/* path B TX IQK */
-+#if 0
-+
-+#if MP_DRIVER != 1
-+	if ((*dm->is_1_antenna == false) || ((*dm->is_1_antenna == true) && (*dm->rf_default_path == 1))
-+	    || dm->support_interface == ODM_ITRF_USB)
-+#endif
-+	{
-+		for (i = 0 ; i < retry_count ; i++) {
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+			path_bok = phy_path_b_iqk_8703b(adapter);
-+#else
-+			path_bok = phy_path_b_iqk_8703b(dm);
-+#endif
-+			/*		if(path_bok == 0x03){ */
-+			if (path_bok == 0x01) {
-+				RF_DBG(dm, DBG_RF_IQK,
-+				       "[IQK]S0 Tx IQK Success!!\n");
-+				result[t][4] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
-+				result[t][5] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD) & 0x3FF0000) >> 16;
-+				break;
-+			}
-+		}
-+#endif
-+
-+/* path B RX IQK */
-+#if 0
-+
-+		for (i = 0 ; i < retry_count ; i++) {
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+			path_bok = phy_path_b_rx_iqk_8703b(adapter);
-+#else
-+			path_bok = phy_path_b_rx_iqk_8703b(dm);
-+#endif
-+			if (path_bok == 0x03) {
-+				RF_DBG(dm, DBG_RF_IQK,
-+				       "[IQK]S0 Rx IQK Success!!\n");
-+				/*				result[t][0] = (odm_get_bb_reg(dm, REG_TX_POWER_BEFORE_IQK_A, MASKDWORD)&0x3FF0000)>>16;
-+				 *				result[t][1] = (odm_get_bb_reg(dm, REG_TX_POWER_AFTER_IQK_A, MASKDWORD)&0x3FF0000)>>16; */
-+				result[t][6] = (odm_get_bb_reg(dm, REG_RX_POWER_BEFORE_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
-+				result[t][7] = (odm_get_bb_reg(dm, REG_RX_POWER_AFTER_IQK_A_2, MASKDWORD) & 0x3FF0000) >> 16;
-+				break;
-+
-+			} else
-+				RF_DBG(dm, DBG_RF_IQK,
-+				       "[IQK]S0 Rx IQK Fail!!\n");
-+		}
-+
-+
-+
-+		if (0x00 == path_bok)
-+			RF_DBG(dm, DBG_RF_IQK, "[IQK]S0 IQK failed!!\n");
-+	}
-+#endif
-+
-+	/* Back to BB mode, load original value */
-+	RF_DBG(dm, DBG_RF_IQK,
-+	       "[IQK]IQK:Back to BB mode, load original value!\n");
-+	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
-+
-+	if (t != 0) {
-+		/* Reload ADDA power saving parameters*/
-+		_phy_reload_adda_registers8703b(dm, ADDA_REG, dm->rf_calibrate_info.ADDA_backup, IQK_ADDA_REG_NUM);
-+		/* Reload MAC parameters*/
-+		_phy_reload_mac_registers8703b(dm, IQK_MAC_REG, dm->rf_calibrate_info.IQK_MAC_backup);
-+		_phy_reload_adda_registers8703b(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup, IQK_BB_REG_NUM);
-+		/* Allen initial gain 0xc50 */
-+		/* Restore RX initial gain */
-+		odm_set_bb_reg(dm, R_0xc50, MASKBYTE0, 0x50);
-+		odm_set_bb_reg(dm, R_0xc50, MASKBYTE0, tmp0xc50);
-+		/* load 0xe30 IQC default value */
-+		odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x01008c00);
-+		odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x01008c00);
-+	}
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]%s <==\n", __func__);
-+}
-+
-+void _phy_lc_calibrate_8703b(struct dm_struct *dm, boolean is2T)
-+{
-+	u8 tmp_reg;
-+	u32 rf_bmode = 0, lc_cal, cnt;
-+
-+	/*Check continuous TX and Packet TX*/
-+	tmp_reg = odm_read_1byte(dm, 0xd03);
-+
-+	if ((tmp_reg & 0x70) != 0) /*Deal with contisuous TX case*/
-+		odm_write_1byte(dm, 0xd03, tmp_reg & 0x8F); /*disable all continuous TX*/
-+	else /* Deal with Packet TX case*/
-+		odm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* block all queues*/
-+
-+	/*backup RF0x18*/
-+	lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
-+
-+	/*Start LCK*/
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000);
-+
-+	for (cnt = 0; cnt < 100; cnt++) {
-+		if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
-+			break;
-+
-+		ODM_delay_ms(10);
-+	}
-+	if (cnt == 100)
-+		RF_DBG(dm, DBG_RF_LCK, "LCK time out\n");
-+
-+	/*Recover channel number*/
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
-+
-+	/*Restore original situation*/
-+	if ((tmp_reg & 0x70) != 0) {
-+		/*Deal with contisuous TX case*/
-+		odm_write_1byte(dm, 0xd03, tmp_reg);
-+	} else {
-+		/* Deal with Packet TX case*/
-+		odm_write_1byte(dm, REG_TXPAUSE, 0x00);
-+	}
-+}
-+
-+/* IQK version: 0x5  20171109 */
-+/* 1. add coex. related setting*/
-+
-+void phy_iq_calibrate_8703b(void *dm_void, boolean is_recovery)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
-+	s32 result[4][8]; /* last is final result */
-+	u8 i, final_candidate, indexforchannel;
-+	boolean is_patha_ok, is_pathb_ok;
-+	s32 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, regecc, reg_tmp = 0;
-+	boolean is12simular, is13simular, is23simular;
-+	u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
-+		REG_OFDM_0_XA_RX_IQ_IMBALANCE, REG_OFDM_0_XB_RX_IQ_IMBALANCE,
-+		REG_OFDM_0_ECCA_THRESHOLD, REG_OFDM_0_AGC_RSSI_TABLE,
-+		REG_OFDM_0_XA_TX_IQ_IMBALANCE, REG_OFDM_0_XB_TX_IQ_IMBALANCE,
-+		REG_OFDM_0_XC_TX_AFE, REG_OFDM_0_XD_TX_AFE,
-+		REG_OFDM_0_RX_IQ_EXT_ANTA};
-+	boolean is_reload_iqk = false;
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
-+	if (is_recovery)
-+#else /* for ODM_WIN */
-+	if (is_recovery && !dm->is_in_hct_test) /* YJ,add for PowerTest,120405 */
-+#endif
-+	{
-+		RF_DBG(dm, DBG_RF_INIT, "[IQK]%s: Return due to is_recovery!\n",
-+		       __func__);
-+		_phy_reload_adda_registers8703b(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup_recover, 9);
-+		return;
-+	}
-+
-+	if (*dm->mp_mode == false) {
-+#if MP_DRIVER != 1
-+		/* check if IQK had been done before!! */
-+		RF_DBG(dm, DBG_RF_IQK, "[IQK] 0xc80 = 0x%x\n",
-+		       cali_info->tx_iqc_8703b[idx_0xc80][VAL]);
-+		if (odm_set_iqc_by_rfpath_8703b(dm)) {
-+			RF_DBG(dm, DBG_RF_IQK,
-+			       "[IQK]IQK value is reloaded!!!\n");
-+			is_reload_iqk = true;
-+		}
-+		if (is_reload_iqk)
-+			return;
-+#endif
-+	}
-+	/*Check & wait if BT is doing IQK*/
-+	if (*(dm->mp_mode) == false)
-+		_phy_check_coex_status_8703b(dm, true);
-+
-+	/* IQK start!!!!!!!!!! */
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK:Start!!!\n");
-+	for (i = 0; i < 8; i++) {
-+		result[0][i] = 0;
-+		result[1][i] = 0;
-+		result[2][i] = 0;
-+		result[3][i] = 0;
-+	}
-+	final_candidate = 0xff;
-+	is_patha_ok = false;
-+	is_pathb_ok = false;
-+	is12simular = false;
-+	is23simular = false;
-+	is13simular = false;
-+
-+	for (i = 0; i < 3; i++) {
-+		_phy_iq_calibrate_8703b(dm, result, i);
-+		if (i == 1) {
-+			is12simular = phy_simularity_compare_8703b(dm, result, 0, 1, true);
-+			if (is12simular) {
-+				final_candidate = 0;
-+				RF_DBG(dm, DBG_RF_IQK,
-+				       "[IQK]IQK: is12simular final_candidate is %x\n",
-+				       final_candidate);
-+				break;
-+			}
-+		}
-+
-+		if (i == 2) {
-+			is13simular = phy_simularity_compare_8703b(dm, result, 0, 2, true);
-+			if (is13simular) {
-+				final_candidate = 0;
-+				RF_DBG(dm, DBG_RF_IQK,
-+				       "[IQK]IQK: is13simular final_candidate is %x\n",
-+				       final_candidate);
-+
-+				break;
-+			}
-+			is23simular = phy_simularity_compare_8703b(dm, result, 1, 2, true);
-+			if (is23simular) {
-+				final_candidate = 1;
-+				RF_DBG(dm, DBG_RF_IQK,
-+				       "[IQK]IQK: is23simular final_candidate is %x\n",
-+				       final_candidate);
-+			} else {
-+				for (i = 0; i < 8; i++)
-+					reg_tmp += result[3][i];
-+
-+				if (reg_tmp != 0)
-+					final_candidate = 3;
-+				else
-+					final_candidate = 0xFF;
-+			}
-+		}
-+	}
-+	/*	RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate\n"));*/
-+
-+	for (i = 0; i < 4; i++) {
-+		rege94 = result[i][0];
-+		rege9c = result[i][1];
-+		regea4 = result[i][2];
-+		regeac = result[i][3];
-+		regeb4 = result[i][4];
-+		regebc = result[i][5];
-+		regec4 = result[i][6];
-+		regecc = result[i][7];
-+		RF_DBG(dm, DBG_RF_IQK,
-+		       "[IQK]IQK: rege94=%x rege9c=%x regea4=%x regeac=%x regeb4=%x regebc=%x regec4=%x regecc=%x\n ",
-+		       rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
-+		       regecc);
-+	}
-+
-+	if (final_candidate != 0xff) {
-+		dm->rf_calibrate_info.rege94 = rege94 = result[final_candidate][0];
-+		dm->rf_calibrate_info.rege9c = rege9c = result[final_candidate][1];
-+		regea4 = result[final_candidate][2];
-+		regeac = result[final_candidate][3];
-+		dm->rf_calibrate_info.regeb4 = regeb4 = result[final_candidate][4];
-+		dm->rf_calibrate_info.regebc = regebc = result[final_candidate][5];
-+		regec4 = result[final_candidate][6];
-+		regecc = result[final_candidate][7];
-+		RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK: final_candidate is %x\n",
-+		       final_candidate);
-+		RF_DBG(dm, DBG_RF_IQK,
-+		       "[IQK]IQK: rege94=%x rege9c=%x regea4=%x regeac=%x regeb4=%x regebc=%x regec4=%x regecc=%x\n ",
-+		       rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
-+		       regecc);
-+		is_patha_ok = is_pathb_ok = true;
-+	} else {
-+		RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK: FAIL use default value\n");
-+		dm->rf_calibrate_info.rege94 = dm->rf_calibrate_info.regeb4 = 0x100; /* X default value */
-+		dm->rf_calibrate_info.rege9c = dm->rf_calibrate_info.regebc = 0x0; /* Y default value */
-+	}
-+
-+	/* fill IQK matrix */
-+	if (rege94 != 0)
-+		_phy_path_a_fill_iqk_matrix8703b(dm, is_patha_ok, result, final_candidate, (regea4 == 0));
-+/*	if (regeb4 != 0)
-+	 *		_phy_path_b_fill_iqk_matrix8703b(adapter, is_pathb_ok, result, final_candidate, (regec4 == 0)); */
-+
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	indexforchannel = odm_get_right_chnl_place_for_iqk(*dm->channel);
-+#else
-+	indexforchannel = 0;
-+#endif
-+
-+	/* To Fix BSOD when final_candidate is 0xff
-+	 * by sherry 20120321 */
-+	if (final_candidate < 4) {
-+		for (i = 0; i < iqk_matrix_reg_num; i++)
-+			dm->rf_calibrate_info.iqk_matrix_reg_setting[indexforchannel].value[0][i] = result[final_candidate][i];
-+		dm->rf_calibrate_info.iqk_matrix_reg_setting[indexforchannel].is_iqk_done = true;
-+	}
-+	/* RT_DISP(FINIT, INIT_IQK, ("\nIQK OK indexforchannel %d.\n", indexforchannel)); */
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]\nIQK OK indexforchannel %d.\n",
-+	       indexforchannel);
-+	_phy_save_adda_registers8703b(dm, IQK_BB_REG_92C, dm->rf_calibrate_info.IQK_BB_backup_recover, IQK_BB_REG_NUM);
-+	/* fill IQK register */
-+	odm_set_iqc_by_rfpath_8703b(dm);
-+	if (*dm->mp_mode == false) {
-+		_phy_check_coex_status_8703b(dm, false);
-+	}
-+	RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK finished\n");
-+}
-+
-+void phy_lc_calibrate_8703b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	_phy_lc_calibrate_8703b(dm, false);
-+}
-+
-+void _phy_set_rf_path_switch_8703b(
-+#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
-+				   struct dm_struct *dm,
-+#else
-+				   void *adapter,
-+#endif
-+				   boolean is_main, boolean is2T)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+#endif
-+
-+	if (is_main) { /*Set WIFI S1*/
-+		odm_set_bb_reg(dm, R_0x7c4, MASKLWORD, 0x7703);
-+		odm_set_bb_reg(dm, R_0x7c0, MASKDWORD, 0xC00F0038);
-+	} else { /*Set BT S0*/
-+		odm_set_bb_reg(dm, R_0x7c4, MASKLWORD, 0xCC03);
-+		odm_set_bb_reg(dm, R_0x7c0, MASKDWORD, 0xC00F0038);
-+	}
-+}
-+
-+void phy_set_rf_path_switch_8703b(
-+#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
-+				  struct dm_struct *dm,
-+#else
-+				  void *adapter,
-+#endif
-+				  boolean is_main)
-+{
-+#if DISABLE_BB_RF
-+	return;
-+#endif
-+
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	_phy_set_rf_path_switch_8703b(dm, is_main, true);
-+#else
-+	_phy_set_rf_path_switch_8703b(adapter, is_main, true);
-+#endif
-+#endif
-+}
-+
-+/*return value true => WIFI(S1); false => BT(S0)*/
-+boolean _phy_query_rf_path_switch_8703b(
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+					struct dm_struct *dm,
-+#else
-+					void *adapter,
-+#endif
-+					boolean is2T)
-+{
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	struct dm_struct *dm = &hal_data->odmpriv;
-+#endif
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+#endif
-+#endif
-+
-+	if (odm_get_bb_reg(dm, R_0x7c4, MASKLWORD) == 0x7703)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+/*return value true => WIFI(S1); false => BT(S0)*/
-+boolean phy_query_rf_path_switch_8703b(
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+				       struct dm_struct *dm
-+#else
-+				       void *adapter
-+#endif
-+				       )
-+{
-+#if DISABLE_BB_RF
-+	return true;
-+#endif
-+
-+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	return _phy_query_rf_path_switch_8703b(adapter, false);
-+#else
-+	return _phy_query_rf_path_switch_8703b(dm, false);
-+#endif
-+}
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/halrf/rtl8703b/halrf_8703b.h b/drivers/staging/rtl8723cs/hal/phydm/halrf/rtl8703b/halrf_8703b.h
-new file mode 100644
-index 000000000000..826bd917b383
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/halrf/rtl8703b/halrf_8703b.h
-@@ -0,0 +1,89 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALRF_8703B_H__
-+#define __HALRF_8703B_H__
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+#define index_mapping_NUM_8703B 15
-+#define AVG_THERMAL_NUM_8703B 4
-+#define RF_T_METER_8703B 0x42
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+#if RT_PLATFORM == PLATFORM_MACOSX
-+#include "halphyrf_win.h"
-+#else
-+#include "../halrf/halphyrf_win.h"
-+#endif
-+#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+#include "../halphyrf_ce.h"
-+#endif
-+
-+void configure_txpower_track_8703b(struct txpwrtrack_cfg *config);
-+
-+void do_iqk_8703b(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
-+		  u8 threshold);
-+
-+void odm_tx_pwr_track_set_pwr_8703b(void *dm_void, enum pwrtrack_method method,
-+				    u8 rf_path, u8 channel_mapped_index);
-+
-+void odm_txxtaltrack_set_xtal_8703b(void *dm_void);
-+
-+/* 1 7.	IQK */
-+
-+void phy_iq_calibrate_8703b(void *dm_void, boolean is_recovery);
-+
-+boolean
-+odm_set_iqc_by_rfpath_8703b(struct dm_struct *dm);
-+
-+/*
-+ * LC calibrate
-+ */
-+void phy_lc_calibrate_8703b(void *dm_void);
-+
-+#if 0
-+/*
-+ * AP calibrate
-+ *   */
-+void
-+phy_ap_calibrate_8703b(
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	struct dm_struct		*dm,
-+#else
-+	void	*adapter,
-+#endif
-+	s8		delta);
-+void
-+phy_digital_predistortion_8703b(void	*adapter);
-+#endif
-+
-+void _phy_save_adda_registers_8703b(
-+	struct dm_struct *dm,
-+	u32 *adda_reg,
-+	u32 *adda_backup,
-+	u32 register_num);
-+
-+void _phy_path_adda_on_8703b(
-+	struct dm_struct *dm,
-+	u32 *adda_reg,
-+	boolean is_path_a_on,
-+	boolean is2T);
-+
-+void _phy_mac_setting_calibration_8703b(
-+	struct dm_struct *dm,
-+	u32 *mac_reg,
-+	u32 *mac_backup);
-+
-+#endif /*#ifndef __HALRF_8703B_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/mp_precomp.h b/drivers/staging/rtl8723cs/hal/phydm/mp_precomp.h
-new file mode 100644
-index 000000000000..897adc13ffca
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/mp_precomp.h
-@@ -0,0 +1,24 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm.c b/drivers/staging/rtl8723cs/hal/phydm/phydm.c
-new file mode 100644
-index 000000000000..0f7e7aa9291e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm.c
-@@ -0,0 +1,3820 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+const u16 phy_rate_table[] = {
-+	/*@20M*/
-+	1, 2, 5, 11,
-+	6, 9, 12, 18, 24, 36, 48, 54,
-+	6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/
-+	13, 26, 39, 52, 78, 104, 117, 130, /*@MCS8~15*/
-+	19, 39, 58, 78, 117, 156, 175, 195, /*@MCS16~23*/
-+	26, 52, 78, 104, 156, 208, 234, 260, /*@MCS24~31*/
-+	6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1ss MCS0~9*/
-+	13, 26, 39, 52, 78, 104, 117, 130, 156, 180, /*@2ss MCS0~9*/
-+	19, 39, 58, 78, 117, 156, 175, 195, 234, 260, /*@3ss MCS0~9*/
-+	26, 52, 78, 104, 156, 208, 234, 260, 312, 360 /*@4ss MCS0~9*/
-+};
-+
-+void phydm_traffic_load_decision(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 shift = 0;
-+
-+	/*@---TP & Trafic-load calculation---*/
-+
-+	if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
-+		dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
-+
-+	if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
-+		dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
-+
-+	dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
-+	dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
-+	dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
-+	dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
-+
-+	/*@AP:  <<3(8bit), >>20(10^6,M), >>0(1sec)*/
-+	shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1);
-+	/*@WIN&CE:  <<3(8bit), >>20(10^6,M), >>1(2sec)*/
-+
-+	dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1);
-+	dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1);
-+
-+	dm->total_tp = dm->tx_tp + dm->rx_tp;
-+
-+	/*@[Calculate TX/RX state]*/
-+	if (dm->tx_tp > (dm->rx_tp << 1))
-+		dm->txrx_state_all = TX_STATE;
-+	else if (dm->rx_tp > (dm->tx_tp << 1))
-+		dm->txrx_state_all = RX_STATE;
-+	else
-+		dm->txrx_state_all = BI_DIRECTION_STATE;
-+
-+	/*@[Traffic load decision]*/
-+	dm->pre_traffic_load = dm->traffic_load;
-+
-+	if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) {
-+		/* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
-+		dm->traffic_load = TRAFFIC_HIGH;
-+	} else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) {
-+		/*@( 0.5M * 8bit ) / 2sec =  2M bits /sec )*/
-+		dm->traffic_load = TRAFFIC_MID;
-+	} else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) {
-+		/*@( 0.1M * 8bit ) / 2sec =  0.4M bits /sec )*/
-+		dm->traffic_load = TRAFFIC_LOW;
-+	} else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) {
-+		/*@( 0.025M * 8bit ) / 2sec =  0.1M bits /sec )*/
-+		dm->traffic_load = TRAFFIC_ULTRA_LOW;
-+	} else {
-+		dm->traffic_load = TRAFFIC_NO_TP;
-+	}
-+
-+	/*@[Calculate consecutive idlel time]*/
-+	if (dm->traffic_load == 0)
-+		dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
-+	else
-+		dm->consecutive_idlel_time = 0;
-+
-+	#if 0
-+	PHYDM_DBG(dm, DBG_COMMON_FLOW,
-+		  "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
-+		  dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt,
-+		  dm->last_rx_ok_cnt);
-+
-+	PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp,
-+		  dm->rx_tp);
-+	#endif
-+}
-+
-+void phydm_cck_new_agc_chk(struct dm_struct *dm)
-+{
-+	u32 new_agc_addr = 0x0;
-+
-+	dm->cck_new_agc = false;
-+#if (RTL8723D_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT ||\
-+	RTL8197F_SUPPORT || RTL8710B_SUPPORT || RTL8192F_SUPPORT ||\
-+	RTL8195B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
-+	RTL8721D_SUPPORT || RTL8710C_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C |
-+	    ODM_RTL8197F | ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B |
-+	    ODM_RTL8721D | ODM_RTL8710C)) {
-+		new_agc_addr = R_0xa9c;
-+	} else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C |
-+		   ODM_RTL8814B | ODM_RTL8197G)) {
-+		new_agc_addr = R_0x1a9c;
-+	}
-+
-+		/*@1: new agc  0: old agc*/
-+	dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, new_agc_addr, BIT(17));
-+#endif
-+#if (RTL8723F_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8723F)) 
-+		dm->cck_new_agc = true;
-+#endif
-+}
-+
-+/*select 3 or 4 bit LNA */
-+void phydm_cck_lna_bit_num_chk(struct dm_struct *dm)
-+{
-+	boolean report_type = 0;
-+	#if (RTL8192E_SUPPORT)
-+	u32 value_824, value_82c;
-+	#endif
-+
-+	#if (RTL8192E_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8192E)) {
-+	/* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
-+	 * should be equal or CCK RSSI report may be incorrect
-+	 */
-+		value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9));
-+		value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9));
-+
-+		if (value_824 != value_82c)
-+			odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824);
-+		odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824);
-+		report_type = (boolean)value_824;
-+	}
-+	#endif
-+
-+	#if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT)
-+	if (dm->support_ic_type &
-+	    (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
-+		report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11));
-+
-+		if (report_type != 1)
-+			pr_debug("[Warning] CCK should be 4bit LNA\n");
-+	}
-+	#endif
-+
-+	#if (RTL8821C_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8821C) {
-+		if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
-+			report_type = 1;
-+	}
-+	#endif
-+
-+	dm->cck_agc_report_type = report_type;
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n",
-+		  dm->cck_agc_report_type);
-+}
-+
-+void phydm_init_cck_setting(struct dm_struct *dm)
-+{
-+	u32 reg_tmp = 0;
-+	u32 mask_tmp = 0;
-+
-+	phydm_cck_new_agc_chk(dm);
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		return;
-+
-+	reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm);
-+	mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm);
-+	dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain);
-+
-+	phydm_config_cck_rx_antenna_init(dm);
-+
-+	if (dm->support_ic_type & ODM_RTL8192F)
-+		phydm_config_cck_rx_path(dm, BB_PATH_AB);
-+	else if (dm->valid_path_set == BB_PATH_A)
-+		phydm_config_cck_rx_path(dm, BB_PATH_A);
-+	else if (dm->valid_path_set == BB_PATH_B)
-+		phydm_config_cck_rx_path(dm, BB_PATH_B);
-+
-+	phydm_cck_lna_bit_num_chk(dm);
-+	phydm_get_cck_rssi_table_from_reg(dm);
-+}
-+
-+#ifdef CONFIG_RFE_BY_HW_INFO
-+void phydm_init_hw_info_by_rfe(struct dm_struct *dm)
-+{
-+	#if (RTL8821C_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8821C)
-+		phydm_init_hw_info_by_rfe_type_8821c(dm);
-+	#endif
-+	#if (RTL8197F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197F)
-+		phydm_init_hw_info_by_rfe_type_8197f(dm);
-+	#endif
-+	#if (RTL8197G_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197G)
-+		phydm_init_hw_info_by_rfe_type_8197g(dm);
-+	#endif
-+}
-+#endif
-+
-+void phydm_common_info_self_init(struct dm_struct *dm)
-+{
-+	u32 reg_tmp = 0;
-+	u32 mask_tmp = 0;
-+
-+	dm->run_in_drv_fw = RUN_IN_DRIVER;
-+
-+	/*@BB IP Generation*/
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		dm->ic_ip_series = PHYDM_IC_JGR3;
-+	else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-+		dm->ic_ip_series = PHYDM_IC_AC;
-+	else if (dm->support_ic_type & ODM_IC_11N_SERIES)
-+		dm->ic_ip_series = PHYDM_IC_N;
-+
-+	/*@BB phy-status Generation*/
-+	if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC)
-+		dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_3;
-+	else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)
-+		dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_2;
-+	else
-+		dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_1;
-+
-+	phydm_init_cck_setting(dm);
-+
-+	reg_tmp = ODM_REG(BB_RX_PATH, dm);
-+	mask_tmp = ODM_BIT(BB_RX_PATH, dm);
-+	dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
-+#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
-+	dm->is_net_closed = &dm->BOOLEAN_temp;
-+
-+	phydm_init_debug_setting(dm);
-+#endif
-+	phydm_init_soft_ml_setting(dm);
-+
-+	dm->phydm_sys_up_time = 0;
-+
-+	if (dm->support_ic_type & ODM_IC_1SS)
-+		dm->num_rf_path = 1;
-+	else if (dm->support_ic_type & ODM_IC_2SS)
-+		dm->num_rf_path = 2;
-+	#if 0
-+	/* @RTK do not has IC which is equipped with 3 RF paths,
-+	 * so ODM_IC_3SS is an enpty macro and result in coverity check errors
-+	 */
-+	else if (dm->support_ic_type & ODM_IC_3SS)
-+		dm->num_rf_path = 3;
-+	#endif
-+	else if (dm->support_ic_type & ODM_IC_4SS)
-+		dm->num_rf_path = 4;
-+	else
-+		dm->num_rf_path = 1;
-+
-+	phydm_trx_antenna_setting_init(dm, dm->num_rf_path);
-+
-+	dm->tx_rate = 0xFF;
-+	dm->rssi_min_by_path = 0xFF;
-+
-+	dm->number_linked_client = 0;
-+	dm->pre_number_linked_client = 0;
-+	dm->number_active_client = 0;
-+	dm->pre_number_active_client = 0;
-+
-+	dm->last_tx_ok_cnt = 0;
-+	dm->last_rx_ok_cnt = 0;
-+	dm->tx_tp = 0;
-+	dm->rx_tp = 0;
-+	dm->total_tp = 0;
-+	dm->traffic_load = TRAFFIC_LOW;
-+
-+	dm->nbi_set_result = 0;
-+	dm->is_init_hw_info_by_rfe = false;
-+	dm->pre_dbg_priority = DBGPORT_RELEASE;
-+	dm->tp_active_th = 5;
-+	dm->disable_phydm_watchdog = 0;
-+
-+	dm->u8_dummy = 0xf;
-+	dm->u16_dummy = 0xffff;
-+	dm->u32_dummy = 0xffffffff;
-+#if (RTL8814B_SUPPORT)
-+/*@------------For spur detection Default Mode------------@*/
-+	dm->dsde_sel = DET_CSI;
-+	dm->csi_wgt = 4;
-+/*@-------------------------------------------------------@*/
-+#endif
-+	dm->pre_is_linked = false;
-+	dm->is_linked = false;
-+/*dym bw thre and it can config by registry*/
-+	if (dm->en_auto_bw_th == 0)
-+		dm->en_auto_bw_th = 20;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	if (!(dm->is_fcs_mode_enable)) {
-+		dm->is_fcs_mode_enable = &dm->boolean_dummy;
-+		pr_debug("[Warning] is_fcs_mode_enable=NULL\n");
-+	}
-+#endif
-+	/*init IOT table*/
-+	odm_memory_set(dm, &dm->iot_table, 0, sizeof(struct phydm_iot_center));
-+}
-+
-+void phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_iot_center	*iot_table = &dm->iot_table;
-+
-+	PHYDM_DBG(dm, DBG_CMN, "[IOT] 0x%x = %d\n", iot_idx, en);
-+	switch (iot_idx) {
-+	case 0x100f0401:
-+		iot_table->patch_id_100f0401 = en;
-+		PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_100f0401 = %d\n",
-+			  iot_table->patch_id_100f0401);
-+		break;
-+	case 0x10120200:
-+		iot_table->patch_id_10120200 = en;
-+		PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_10120200 = %d\n",
-+			  iot_table->patch_id_10120200);
-+		break;
-+	case 0x40010700:
-+		iot_table->patch_id_40010700 = en;
-+		PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_40010700 = %d\n",
-+			  iot_table->patch_id_40010700);
-+		break;
-+	case 0x021f0800:
-+		iot_table->patch_id_021f0800 = en;
-+		PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_021f0800 = %d\n",
-+			  iot_table->patch_id_021f0800);
-+		break;
-+	case 0x011f0500:
-+		iot_table->patch_id_011f0500 = en;
-+		PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_011f0500 = %d\n",
-+			  iot_table->patch_id_011f0500);
-+		break;
-+	default:
-+		pr_debug("[%s] warning!\n", __func__);
-+		break;
-+	}
-+}
-+
-+void phydm_cmn_sta_info_update(void *dm_void, u8 macid)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
-+	struct ra_sta_info *ra = NULL;
-+
-+	if (is_sta_active(sta)) {
-+		ra = &sta->ra_info;
-+	} else {
-+		PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n",
-+			  __func__);
-+		return;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
-+	PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id);
-+
-+	/*@[Calculate TX/RX state]*/
-+	if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))
-+		ra->txrx_state = TX_STATE;
-+	else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))
-+		ra->txrx_state = RX_STATE;
-+	else
-+		ra->txrx_state = BI_DIRECTION_STATE;
-+
-+	ra->is_noisy = dm->noisy_decision;
-+}
-+
-+void phydm_common_info_self_update(struct dm_struct *dm)
-+{
-+	u8 sta_cnt = 0, num_active_client = 0;
-+	u32 i, one_entry_macid = 0;
-+	u32 ma_rx_tp = 0;
-+	u32 tp_diff = 0;
-+	struct cmn_sta_info *sta;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	PADAPTER adapter = (PADAPTER)dm->adapter;
-+	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
-+
-+	sta = dm->phydm_sta_info[0];
-+
-+	/* STA mode is linked to AP */
-+	if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
-+		dm->bsta_state = true;
-+	else
-+		dm->bsta_state = false;
-+#endif
-+
-+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
-+		sta = dm->phydm_sta_info[i];
-+		if (is_sta_active(sta)) {
-+			sta_cnt++;
-+
-+			if (sta_cnt == 1)
-+				one_entry_macid = i;
-+
-+			phydm_cmn_sta_info_update(dm, (u8)i);
-+			#ifdef PHYDM_BEAMFORMING_SUPPORT
-+			/*@phydm_get_txbf_device_num(dm, (u8)i);*/
-+			#endif
-+
-+			ma_rx_tp = sta->rx_moving_average_tp +
-+				   sta->tx_moving_average_tp;
-+
-+			PHYDM_DBG(dm, DBG_COMMON_FLOW,
-+				  "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp);
-+
-+			if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
-+				num_active_client++;
-+		}
-+	}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	dm->is_linked = (sta_cnt != 0) ? true : false;
-+#endif
-+
-+	if (sta_cnt == 1) {
-+		dm->is_one_entry_only = true;
-+		dm->one_entry_macid = one_entry_macid;
-+		dm->one_entry_tp = ma_rx_tp;
-+
-+		dm->tp_active_occur = 0;
-+
-+		PHYDM_DBG(dm, DBG_COMMON_FLOW,
-+			  "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
-+			  dm->one_entry_tp, dm->pre_one_entry_tp);
-+
-+		if (dm->one_entry_tp > dm->pre_one_entry_tp &&
-+		    dm->pre_one_entry_tp <= 2) {
-+			tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp;
-+
-+			if (tp_diff > dm->tp_active_th)
-+				dm->tp_active_occur = 1;
-+		}
-+		dm->pre_one_entry_tp = dm->one_entry_tp;
-+	} else {
-+		dm->is_one_entry_only = false;
-+	}
-+
-+	dm->pre_number_linked_client = dm->number_linked_client;
-+	dm->pre_number_active_client = dm->number_active_client;
-+
-+	dm->number_linked_client = sta_cnt;
-+	dm->number_active_client = num_active_client;
-+
-+	/*Traffic load information update*/
-+	phydm_traffic_load_decision(dm);
-+
-+	dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;
-+
-+	dm->is_dfs_band = phydm_is_dfs_band(dm);
-+	dm->phy_dbg_info.show_phy_sts_cnt = 0;
-+
-+	/*[Link Status Check]*/
-+	dm->first_connect = dm->is_linked && !dm->pre_is_linked;
-+	dm->first_disconnect = !dm->is_linked && dm->pre_is_linked;
-+	dm->pre_is_linked = dm->is_linked;
-+}
-+
-+void phydm_common_info_self_reset(struct dm_struct *dm)
-+{
-+	struct odm_phy_dbg_info		*dbg_t = &dm->phy_dbg_info;
-+
-+	dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt;
-+	dbg_t->num_qry_beacon_pkt = 0;
-+
-+	dm->rxsc_l = 0xff;
-+	dm->rxsc_20 = 0xff;
-+	dm->rxsc_40 = 0xff;
-+	dm->rxsc_80 = 0xff;
-+}
-+
-+void *
-+phydm_get_structure(struct dm_struct *dm, u8 structure_type)
-+
-+{
-+	void *structure = NULL;
-+
-+	switch (structure_type) {
-+	case PHYDM_FALSEALMCNT:
-+		structure = &dm->false_alm_cnt;
-+		break;
-+
-+	case PHYDM_CFOTRACK:
-+		structure = &dm->dm_cfo_track;
-+		break;
-+
-+	case PHYDM_ADAPTIVITY:
-+		structure = &dm->adaptivity;
-+		break;
-+#ifdef CONFIG_PHYDM_DFS_MASTER
-+	case PHYDM_DFS:
-+		structure = &dm->dfs;
-+		break;
-+#endif
-+	default:
-+		break;
-+	}
-+
-+	return structure;
-+}
-+
-+void phydm_phy_info_update(struct dm_struct *dm)
-+{
-+#if (RTL8822B_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8822B)
-+		dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm);
-+#endif
-+}
-+
-+void phydm_hw_setting(struct dm_struct *dm)
-+{
-+#if (RTL8821A_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8821)
-+		odm_hw_setting_8821a(dm);
-+#endif
-+
-+#if (RTL8814A_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8814A)
-+		phydm_hwsetting_8814a(dm);
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8822B)
-+		phydm_hwsetting_8822b(dm);
-+#endif
-+
-+#if (RTL8812A_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8812)
-+		phydm_hwsetting_8812a(dm);
-+#endif
-+
-+#if (RTL8197F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197F)
-+		phydm_hwsetting_8197f(dm);
-+#endif
-+
-+#if (RTL8192F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8192F)
-+		phydm_hwsetting_8192f(dm);
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		phydm_hwsetting_8822c(dm);
-+#endif
-+
-+#if (RTL8197G_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197G)
-+		phydm_hwsetting_8197g(dm);
-+#endif
-+
-+#if (RTL8723F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8723F)
-+		phydm_hwsetting_8723f(dm);
-+#endif
-+
-+#if (RTL8821C_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8821C)
-+		phydm_hwsetting_8821c(dm);
-+#endif
-+
-+#if (RTL8812F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8812F)
-+		phydm_hwsetting_8812f(dm);
-+#endif
-+
-+#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
-+	phydm_cck_rx_pathdiv_watchdog(dm);
-+#endif
-+}
-+
-+__odm_func__
-+boolean phydm_chk_bb_rf_pkg_set_valid(struct dm_struct *dm)
-+{
-+	boolean valid = true;
-+
-+	if (dm->support_ic_type == ODM_RTL8822C) {
-+		#if (RTL8822C_SUPPORT)
-+		valid = phydm_chk_pkg_set_valid_8822c(dm,
-+						      RELEASE_VERSION_8822C,
-+						      RF_RELEASE_VERSION_8822C);
-+		#else
-+		valid = true; /*@Just for preventing compile warnings*/
-+		#endif
-+	#if (RTL8812F_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8812F) {
-+		valid = phydm_chk_pkg_set_valid_8812f(dm,
-+						      RELEASE_VERSION_8812F,
-+						      RF_RELEASE_VERSION_8812F);
-+	#endif
-+	#if (RTL8197G_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8197G) {
-+		valid = phydm_chk_pkg_set_valid_8197g(dm,
-+						      RELEASE_VERSION_8197G,
-+						      RF_RELEASE_VERSION_8197G);
-+	#endif
-+	#if (RTL8812F_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8812F) {
-+		valid = phydm_chk_pkg_set_valid_8812f(dm,
-+						      RELEASE_VERSION_8812F,
-+						      RF_RELEASE_VERSION_8812F);
-+	#endif
-+	#if (RTL8198F_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8198F) {
-+		valid = phydm_chk_pkg_set_valid_8198f(dm,
-+						      RELEASE_VERSION_8198F,
-+						      RF_RELEASE_VERSION_8198F);
-+	#endif
-+	#if (RTL8814B_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8814B) {
-+		valid = phydm_chk_pkg_set_valid_8814b(dm,
-+						      RELEASE_VERSION_8814B,
-+						      RF_RELEASE_VERSION_8814B);
-+	#endif
-+	#if (RTL8723F_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8723F) {
-+		valid = phydm_chk_pkg_set_valid_8723f(dm,
-+						      RELEASE_VERSION_8723F,
-+							  RF_RELEASE_VERSION_8723F);
-+	#endif
-+	}
-+
-+	return valid;
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+u64 phydm_supportability_init_win(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u64 support_ability = 0;
-+
-+	switch (dm->support_ic_type) {
-+/*@---------------N Series--------------------*/
-+#if (RTL8188E_SUPPORT)
-+	case ODM_RTL8188E:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR |
-+			ODM_BB_PRIMARY_CCA;
-+		break;
-+#endif
-+
-+#if (RTL8192E_SUPPORT)
-+	case ODM_RTL8192E:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR |
-+			ODM_BB_PRIMARY_CCA;
-+		break;
-+#endif
-+
-+#if (RTL8723B_SUPPORT)
-+	case ODM_RTL8723B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR |
-+			ODM_BB_PRIMARY_CCA;
-+		break;
-+#endif
-+
-+#if (RTL8703B_SUPPORT)
-+	case ODM_RTL8703B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8723D_SUPPORT)
-+	case ODM_RTL8723D:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			ODM_BB_PWR_TRAIN |
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8710B_SUPPORT)
-+	case ODM_RTL8710B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			ODM_BB_PWR_TRAIN |
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8188F_SUPPORT)
-+	case ODM_RTL8188F:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT)
-+	case ODM_RTL8192F:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			ODM_BB_PWR_TRAIN	|
-+			ODM_BB_RATE_ADAPTIVE |
-+			/*ODM_BB_PATH_DIV |*/
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ADAPTIVE_SOML |
-+			ODM_BB_ENV_MONITOR;
-+			/*ODM_BB_LNA_SAT_CHK |*/
-+			/*ODM_BB_PRIMARY_CCA*/
-+
-+		break;
-+#endif
-+
-+/*@---------------AC Series-------------------*/
-+
-+#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
-+	case ODM_RTL8812:
-+	case ODM_RTL8821:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_DYNAMIC_TXPWR |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8814A_SUPPORT)
-+	case ODM_RTL8814A:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_DYNAMIC_TXPWR |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+	case ODM_RTL8822B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR	|*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			/*ODM_BB_ADAPTIVE_SOML |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			/*ODM_BB_PATH_DIV |*/
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8821C_SUPPORT)
-+	case ODM_RTL8821C:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR	|*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+/*@---------------JGR3 Series-------------------*/
-+
-+#if (RTL8822C_SUPPORT)
-+	case ODM_RTL8822C:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_DYNAMIC_TXPWR |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_PATH_DIV |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8814B_SUPPORT)
-+	case ODM_RTL8814B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING;
-+			/*ODM_BB_ENV_MONITOR;*/
-+		break;
-+#endif
-+
-+#if (RTL8723F_SUPPORT)
-+	case ODM_RTL8723F:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/* ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+	default:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+
-+		pr_debug("[Warning] Supportability Init Warning !!!\n");
-+		break;
-+	}
-+
-+	return support_ability;
-+}
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+u64 phydm_supportability_init_ce(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u64 support_ability = 0;
-+
-+	switch (dm->support_ic_type) {
-+/*@---------------N Series--------------------*/
-+#if (RTL8188E_SUPPORT)
-+	case ODM_RTL8188E:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*@ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR |
-+			ODM_BB_PRIMARY_CCA;
-+		break;
-+#endif
-+
-+#if (RTL8192E_SUPPORT)
-+	case ODM_RTL8192E:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*@ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR |
-+			ODM_BB_PRIMARY_CCA;
-+		break;
-+#endif
-+
-+#if (RTL8723B_SUPPORT)
-+	case ODM_RTL8723B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*@ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR |
-+			ODM_BB_PRIMARY_CCA;
-+		break;
-+#endif
-+
-+#if (RTL8703B_SUPPORT)
-+	case ODM_RTL8703B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*@ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8723D_SUPPORT)
-+	case ODM_RTL8723D:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			ODM_BB_PWR_TRAIN	|
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8710B_SUPPORT)
-+	case ODM_RTL8710B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*@ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8188F_SUPPORT)
-+	case ODM_RTL8188F:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*@ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT)
-+	case ODM_RTL8192F:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			ODM_BB_PWR_TRAIN |
-+			ODM_BB_RATE_ADAPTIVE |
-+			/*ODM_BB_PATH_DIV |*/
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			/*@ODM_BB_ADAPTIVE_SOML |*/
-+			ODM_BB_ENV_MONITOR;
-+			/*@ODM_BB_LNA_SAT_CHK |*/
-+			/*@ODM_BB_PRIMARY_CCA*/
-+			break;
-+#endif
-+/*@---------------AC Series-------------------*/
-+
-+#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT)
-+	case ODM_RTL8812:
-+	case ODM_RTL8821:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*@ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8814A_SUPPORT)
-+	case ODM_RTL8814A:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*@ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+	case ODM_RTL8822B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_DYNAMIC_TXPWR	|
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*@ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			/*ODM_BB_PATH_DIV |*/
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8821C_SUPPORT)
-+	case ODM_RTL8821C:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_DYNAMIC_TXPWR |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*@ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+/*@---------------JGR3 Series-------------------*/
-+
-+#if (RTL8822C_SUPPORT)
-+	case ODM_RTL8822C:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_DYNAMIC_TXPWR	|
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			ODM_BB_RATE_ADAPTIVE |
-+			/* ODM_BB_PATH_DIV | */
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8814B_SUPPORT)
-+	case ODM_RTL8814B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*@ODM_BB_PWR_TRAIN |*/
-+			/*ODM_BB_RATE_ADAPTIVE |*/
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING;
-+			/*ODM_BB_ENV_MONITOR;*/
-+		break;
-+#endif
-+#if (RTL8723F_SUPPORT)
-+	case ODM_RTL8723F:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_DYNAMIC_TXPWR	|
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			ODM_BB_RATE_ADAPTIVE |
-+			/* ODM_BB_PATH_DIV | */
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+	default:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*@ODM_BB_DYNAMIC_TXPWR	|*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*@ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+
-+		pr_debug("[Warning] Supportability Init Warning !!!\n");
-+		break;
-+	}
-+
-+	return support_ability;
-+}
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+u64 phydm_supportability_init_ap(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u64 support_ability = 0;
-+
-+	switch (dm->support_ic_type) {
-+/*@---------------N Series--------------------*/
-+#if (RTL8188E_SUPPORT)
-+	case ODM_RTL8188E:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR |
-+			ODM_BB_PRIMARY_CCA;
-+		break;
-+#endif
-+
-+#if (RTL8192E_SUPPORT)
-+	case ODM_RTL8192E:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR |
-+			ODM_BB_PRIMARY_CCA;
-+		break;
-+#endif
-+
-+#if (RTL8723B_SUPPORT)
-+	case ODM_RTL8723B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN		|*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8198F_SUPPORT || RTL8197F_SUPPORT)
-+	case ODM_RTL8198F:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			/*ODM_BB_RATE_ADAPTIVE |*/
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING;
-+			/*ODM_BB_ADAPTIVE_SOML |*/
-+			/*ODM_BB_ENV_MONITOR |*/
-+			/*ODM_BB_LNA_SAT_CHK |*/
-+			/*ODM_BB_PRIMARY_CCA;*/
-+		break;
-+	case ODM_RTL8197F:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ADAPTIVE_SOML |
-+			ODM_BB_ENV_MONITOR |
-+			ODM_BB_LNA_SAT_CHK |
-+			ODM_BB_PRIMARY_CCA;
-+		break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT)
-+	case ODM_RTL8192F:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			/*ODM_BB_CFO_TRACKING |*/
-+			ODM_BB_ADAPTIVE_SOML |
-+			/*ODM_BB_PATH_DIV |*/
-+			ODM_BB_ENV_MONITOR |
-+			/*ODM_BB_LNA_SAT_CHK |*/
-+			/*ODM_BB_PRIMARY_CCA |*/
-+			0;
-+		break;
-+#endif
-+
-+/*@---------------AC Series-------------------*/
-+
-+#if (RTL8881A_SUPPORT)
-+	case ODM_RTL8881A:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8814A_SUPPORT)
-+	case ODM_RTL8814A:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+	case ODM_RTL8822B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			/*ODM_BB_ADAPTIVE_SOML |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8821C_SUPPORT)
-+	case ODM_RTL8821C:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+
-+		break;
-+#endif
-+
-+/*@---------------JGR3 Series-------------------*/
-+
-+#if (RTL8814B_SUPPORT)
-+	case ODM_RTL8814B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			/*ODM_BB_RATE_ADAPTIVE |*/
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8197G_SUPPORT)
-+	case ODM_RTL8197G:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8812F_SUPPORT)
-+	case ODM_RTL8812F:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_DYNAMIC_TXPWR	|
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			/*ODM_BB_CCK_PD |*/
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8723F_SUPPORT)
-+	case ODM_RTL8723F:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+	default:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+
-+		pr_debug("[Warning] Supportability Init Warning !!!\n");
-+		break;
-+	}
-+
-+	return support_ability;
-+}
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+u64 phydm_supportability_init_iot(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u64 support_ability = 0;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8710B_SUPPORT)
-+	case ODM_RTL8710B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8195A_SUPPORT)
-+	case ODM_RTL8195A:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8195B_SUPPORT)
-+	case ODM_RTL8195B:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8721D_SUPPORT)
-+	case ODM_RTL8721D:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+
-+#if (RTL8710C_SUPPORT)
-+	case ODM_RTL8710C:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_ADAPTIVITY |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+		break;
-+#endif
-+	default:
-+		support_ability |=
-+			ODM_BB_DIG |
-+			ODM_BB_RA_MASK |
-+			/*ODM_BB_DYNAMIC_TXPWR |*/
-+			ODM_BB_FA_CNT |
-+			ODM_BB_RSSI_MONITOR |
-+			ODM_BB_CCK_PD |
-+			/*ODM_BB_PWR_TRAIN |*/
-+			ODM_BB_RATE_ADAPTIVE |
-+			ODM_BB_CFO_TRACKING |
-+			ODM_BB_ENV_MONITOR;
-+
-+		pr_debug("[Warning] Supportability Init Warning !!!\n");
-+		break;
-+	}
-+
-+	return support_ability;
-+}
-+#endif
-+
-+void phydm_fwoffload_ability_init(struct dm_struct *dm,
-+				  enum phydm_offload_ability offload_ability)
-+{
-+	switch (offload_ability) {
-+	case PHYDM_PHY_PARAM_OFFLOAD:
-+		if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
-+			dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
-+		break;
-+
-+	case PHYDM_RF_IQK_OFFLOAD:
-+		dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
-+		break;
-+
-+	case PHYDM_RF_DPK_OFFLOAD:
-+		dm->fw_offload_ability |= PHYDM_RF_DPK_OFFLOAD;
-+		break;
-+
-+	default:
-+		PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
-+		break;
-+	}
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
-+		  dm->fw_offload_ability);
-+}
-+
-+void phydm_fwoffload_ability_clear(struct dm_struct *dm,
-+				   enum phydm_offload_ability offload_ability)
-+{
-+	switch (offload_ability) {
-+	case PHYDM_PHY_PARAM_OFFLOAD:
-+		if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD)
-+			dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
-+		break;
-+
-+	case PHYDM_RF_IQK_OFFLOAD:
-+		dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
-+		break;
-+
-+	case PHYDM_RF_DPK_OFFLOAD:
-+		dm->fw_offload_ability &= (~PHYDM_RF_DPK_OFFLOAD);
-+		break;	
-+
-+	default:
-+		PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
-+		break;
-+	}
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n",
-+		  dm->fw_offload_ability);
-+}
-+
-+void phydm_supportability_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u64 support_ability;
-+
-+	if (dm->manual_supportability &&
-+	    *dm->manual_supportability != 0xffffffff) {
-+		support_ability = *dm->manual_supportability;
-+	} else if (*dm->mp_mode) {
-+		support_ability = 0;
-+	} else {
-+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+		support_ability = phydm_supportability_init_win(dm);
-+		#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+		support_ability = phydm_supportability_init_ap(dm);
-+		#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+		support_ability = phydm_supportability_init_ce(dm);
-+		#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+		support_ability = phydm_supportability_init_iot(dm);
-+		#endif
-+
-+		/*@[Config Antenna Diversity]*/
-+		if (IS_FUNC_EN(dm->enable_antdiv))
-+			support_ability |= ODM_BB_ANT_DIV;
-+
-+		/*@[Config TXpath Diversity]*/
-+		if (IS_FUNC_EN(dm->enable_pathdiv))
-+			support_ability |= ODM_BB_PATH_DIV;
-+
-+		/*@[Config Adaptive SOML]*/
-+		if (IS_FUNC_EN(dm->en_adap_soml))
-+			support_ability |= ODM_BB_ADAPTIVE_SOML;
-+
-+		/*@[DYNAMIC_TXPWR and TSSI cannot coexist]*/
-+		if(IS_FUNC_EN(&dm->en_tssi_mode) &&
-+		    (dm->support_ic_type & ODM_RTL8822C))
-+			support_ability &= ~ODM_BB_DYNAMIC_TXPWR;
-+
-+	}
-+	dm->support_ability = support_ability;
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n",
-+		  dm->support_ic_type, *dm->mp_mode, dm->support_ability);
-+}
-+
-+void phydm_rfe_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n");
-+#if (RTL8822B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8822B)
-+		phydm_rfe_8822b_init(dm);
-+#endif
-+}
-+
-+#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
-+void phydm_tx_collsion_th_init(void *dm_void)
-+{
-+
-+struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8197G_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197G)
-+		phydm_tx_collsion_th_init_8197g(dm);
-+#endif
-+
-+#if (RTL8812F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8812F)
-+		phydm_tx_collsion_th_init_8812f(dm);
-+#endif
-+
-+}
-+
-+void phydm_tx_collsion_th_set(void *dm_void, u8 val_r2t, u8 val_t2r)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8197G_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197G)
-+		phydm_tx_collsion_th_set_8197g(dm, val_r2t, val_t2r);
-+#endif
-+
-+#if (RTL8812F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8812F)
-+		phydm_tx_collsion_th_set_8812f(dm, val_r2t, val_t2r);
-+#endif
-+	
-+}
-+#endif
-+
-+void phydm_dm_early_init(struct dm_struct *dm)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	phydm_init_debug_setting(dm);
-+#endif
-+}
-+
-+enum phydm_init_result odm_dm_init(struct dm_struct *dm)
-+{
-+	enum phydm_init_result result = PHYDM_INIT_SUCCESS;
-+
-+	if (!phydm_chk_bb_rf_pkg_set_valid(dm)) {
-+		pr_debug("[Warning][%s] Init fail\n", __func__);
-+		return PHYDM_INIT_FAIL_BBRF_REG_INVALID;
-+	}
-+
-+	halrf_init(dm);
-+	phydm_supportability_init(dm);
-+	phydm_pause_func_init(dm);
-+	phydm_rfe_init(dm);
-+	phydm_common_info_self_init(dm);
-+	phydm_rx_phy_status_init(dm);
-+#ifdef PHYDM_AUTO_DEGBUG
-+	phydm_auto_dbg_engine_init(dm);
-+#endif
-+	phydm_dig_init(dm);
-+#ifdef PHYDM_SUPPORT_CCKPD
-+#ifdef PHYDM_DCC_ENHANCE
-+	phydm_dig_cckpd_coex_init(dm);
-+#endif
-+	phydm_cck_pd_init(dm);
-+#endif
-+	phydm_env_monitor_init(dm);
-+	phydm_enhance_monitor_init(dm);
-+	phydm_adaptivity_init(dm);
-+	phydm_ra_info_init(dm);
-+	phydm_rssi_monitor_init(dm);
-+	phydm_cfo_tracking_init(dm);
-+	phydm_rf_init(dm);
-+	phydm_dc_cancellation(dm);
-+#ifdef PHYDM_TXA_CALIBRATION
-+	phydm_txcurrentcalibration(dm);
-+	phydm_get_pa_bias_offset(dm);
-+#endif
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	odm_antenna_diversity_init(dm);
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+	phydm_adaptive_soml_init(dm);
-+#endif
-+#ifdef CONFIG_PATH_DIVERSITY
-+	phydm_tx_path_diversity_init(dm);
-+#endif
-+#ifdef CONFIG_DYNAMIC_TX_TWR
-+	phydm_dynamic_tx_power_init(dm);
-+#endif
-+#if (PHYDM_LA_MODE_SUPPORT)
-+	phydm_la_init(dm);
-+#endif
-+
-+#ifdef PHYDM_BEAMFORMING_VERSION1
-+	phydm_beamforming_init(dm);
-+#endif
-+
-+#if (RTL8188E_SUPPORT)
-+	odm_ra_info_init_all(dm);
-+#endif
-+#ifdef PHYDM_PRIMARY_CCA
-+	phydm_primary_cca_init(dm);
-+#endif
-+#ifdef CONFIG_PSD_TOOL
-+	phydm_psd_init(dm);
-+#endif
-+
-+#ifdef CONFIG_SMART_ANTENNA
-+	phydm_smt_ant_init(dm);
-+#endif
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+	phydm_lna_sat_check_init(dm);
-+#endif
-+#ifdef CONFIG_MCC_DM
-+	phydm_mcc_init(dm);
-+#endif
-+
-+#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
-+	phydm_cck_rx_pathdiv_init(dm);
-+#endif
-+
-+#ifdef CONFIG_MU_RSOML
-+	phydm_mu_rsoml_init(dm);
-+#endif
-+
-+#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
-+	phydm_tx_collsion_th_init(dm);
-+#endif
-+
-+	return result;
-+}
-+
-+void odm_dm_reset(struct dm_struct *dm)
-+{
-+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	odm_ant_div_reset(dm);
-+	#endif
-+	phydm_set_edcca_threshold_api(dm);
-+}
-+
-+void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
-+			     char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 dm_value[10] = {0};
-+	u64 pre_support_ability, one = 1;
-+	u64 comp = 0;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i;
-+
-+	for (i = 0; i < 5; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
-+	}
-+
-+	pre_support_ability = dm->support_ability;
-+	comp = dm->support_ability;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\n================================\n");
-+
-+	if (dm_value[0] == 100) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[Supportability] PhyDM Selection\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "================================\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "00. (( %s ))DIG\n",
-+			 ((comp & ODM_BB_DIG) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "01. (( %s ))RA_MASK\n",
-+			 ((comp & ODM_BB_RA_MASK) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "02. (( %s ))DYN_TXPWR\n",
-+			 ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "03. (( %s ))FA_CNT\n",
-+			 ((comp & ODM_BB_FA_CNT) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "04. (( %s ))RSSI_MNTR\n",
-+			 ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "05. (( %s ))CCK_PD\n",
-+			 ((comp & ODM_BB_CCK_PD) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "06. (( %s ))ANT_DIV\n",
-+			 ((comp & ODM_BB_ANT_DIV) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "07. (( %s ))SMT_ANT\n",
-+			 ((comp & ODM_BB_SMT_ANT) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "08. (( %s ))PWR_TRAIN\n",
-+			 ((comp & ODM_BB_PWR_TRAIN) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "09. (( %s ))RA\n",
-+			 ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "10. (( %s ))PATH_DIV\n",
-+			 ((comp & ODM_BB_PATH_DIV) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "11. (( %s ))DFS\n",
-+			 ((comp & ODM_BB_DFS) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "12. (( %s ))DYN_ARFR\n",
-+			 ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "13. (( %s ))ADAPTIVITY\n",
-+			 ((comp & ODM_BB_ADAPTIVITY) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "14. (( %s ))CFO_TRACK\n",
-+			 ((comp & ODM_BB_CFO_TRACKING) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "15. (( %s ))ENV_MONITOR\n",
-+			 ((comp & ODM_BB_ENV_MONITOR) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "16. (( %s ))PRI_CCA\n",
-+			 ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "17. (( %s ))ADPTV_SOML\n",
-+			 ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "18. (( %s ))LNA_SAT_CHK\n",
-+			 ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "================================\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[Supportability] PhyDM offload ability\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "================================\n");
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "00. (( %s ))PHY PARAM OFFLOAD\n",
-+			 ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ?
-+			 ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "01. (( %s ))RF IQK OFFLOAD\n",
-+			 ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ?
-+			 ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "================================\n");
-+
-+	} else if (dm_value[0] == 101) {
-+		dm->support_ability = 0;
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Disable all support_ability components\n");
-+	} else {
-+		if (dm_value[1] == 1) { /* @enable */
-+			dm->support_ability |= (one << dm_value[0]);
-+		} else if (dm_value[1] == 2) {/* @disable */
-+			dm->support_ability &= ~(one << dm_value[0]);
-+		} else {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[Warning!!!]  1:enable,  2:disable\n");
-+		}
-+	}
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "pre-supportability = 0x%llx\n", pre_support_ability);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "Cur-supportability = 0x%llx\n", dm->support_ability);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "================================\n");
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_watchdog_lps_32k(struct dm_struct *dm)
-+{
-+	PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
-+
-+	phydm_common_info_self_update(dm);
-+	phydm_rssi_monitor_check(dm);
-+	phydm_dig_lps_32k(dm);
-+	phydm_common_info_self_reset(dm);
-+}
-+
-+void phydm_watchdog_lps(struct dm_struct *dm)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
-+	PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
-+
-+	phydm_common_info_self_update(dm);
-+	phydm_rssi_monitor_check(dm);
-+	phydm_basic_dbg_message(dm);
-+	phydm_receiver_blocking(dm);
-+	phydm_false_alarm_counter_statistics(dm);
-+	phydm_dig_by_rssi_lps(dm);
-+	#ifdef PHYDM_SUPPORT_CCKPD
-+	phydm_cck_pd_th(dm);
-+	#endif
-+	phydm_adaptivity(dm);
-+	#ifdef CONFIG_BW_INDICATION
-+	phydm_dyn_bw_indication(dm);
-+	#endif
-+	#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	/*@enable AntDiv in PS mode, request from SD4 Jeff*/
-+	odm_antenna_diversity(dm);
-+	#endif
-+	#endif
-+	phydm_common_info_self_reset(dm);
-+#endif
-+}
-+
-+void phydm_watchdog_mp(struct dm_struct *dm)
-+{
-+}
-+
-+void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (pause_type == PHYDM_PAUSE) {
-+		dm->disable_phydm_watchdog = 1;
-+		PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n");
-+	} else {
-+		dm->disable_phydm_watchdog = 0;
-+		PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n");
-+	}
-+}
-+
-+void phydm_pause_func_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
-+	dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
-+	dm->pause_lv_table.lv_antdiv = PHYDM_PAUSE_RELEASE;
-+	dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
-+	dm->pause_lv_table.lv_adapt = PHYDM_PAUSE_RELEASE;
-+	dm->pause_lv_table.lv_adsl = PHYDM_PAUSE_RELEASE;
-+}
-+
-+u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
-+		    enum phydm_pause_type pause_type,
-+		    enum phydm_pause_level pause_lv, u8 val_lehgth,
-+		    u32 *val_buf)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_func_poiner *func_t = &dm->phydm_func_handler;
-+	s8 *pause_lv_pre = &dm->s8_dummy;
-+	u32 *bkp_val = &dm->u32_dummy;
-+	u32 ori_val[5] = {0};
-+	u64 pause_func_bitmap = (u64)BIT(pause_func);
-+	u8 i = 0;
-+	u8 en_2rcca = 0;
-+	u8 en_bw40m = 0;
-+	u8 pause_result = PAUSE_FAIL;
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "\n");
-+	PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
-+		  ((pause_type == PHYDM_PAUSE) ? "Pause" :
-+		  ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
-+		  pause_lv, val_lehgth);
-+
-+	if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
-+		PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv);
-+		return PAUSE_FAIL;
-+	}
-+
-+	if (pause_func == F00_DIG) {
-+		PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n");
-+
-+		if (val_lehgth != 1) {
-+			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
-+			return PAUSE_FAIL;
-+		}
-+
-+		ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value);
-+		pause_lv_pre = &dm->pause_lv_table.lv_dig;
-+		bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val);
-+		/*@function pointer hook*/
-+		func_t->pause_phydm_handler = phydm_set_dig_val;
-+
-+#ifdef PHYDM_SUPPORT_CCKPD
-+	} else if (pause_func == F05_CCK_PD) {
-+		PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n");
-+
-+		if (val_lehgth != 1) {
-+			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
-+			return PAUSE_FAIL;
-+		}
-+
-+		ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv;
-+		pause_lv_pre = &dm->pause_lv_table.lv_cckpd;
-+		bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val);
-+		/*@function pointer hook*/
-+		func_t->pause_phydm_handler = phydm_set_cckpd_val;
-+#endif
-+
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	} else if (pause_func == F06_ANT_DIV) {
-+		PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n");
-+
-+		if (val_lehgth != 1) {
-+			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
-+			return PAUSE_FAIL;
-+		}
-+		/*@default antenna*/
-+		ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant);
-+		pause_lv_pre = &dm->pause_lv_table.lv_antdiv;
-+		bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val);
-+		/*@function pointer hook*/
-+		func_t->pause_phydm_handler = phydm_set_antdiv_val;
-+
-+#endif
-+#ifdef PHYDM_SUPPORT_ADAPTIVITY
-+	} else if (pause_func == F13_ADPTVTY) {
-+		PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n");
-+
-+		if (val_lehgth != 2) {
-+			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n");
-+			return PAUSE_FAIL;
-+		}
-+
-+		ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/
-+		ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/
-+		pause_lv_pre = &dm->pause_lv_table.lv_adapt;
-+		bkp_val = (u32 *)(&dm->adaptivity.rvrt_val);
-+		/*@function pointer hook*/
-+		func_t->pause_phydm_handler = phydm_set_edcca_val;
-+
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+	} else if (pause_func == F17_ADPTV_SOML) {
-+		PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n");
-+
-+		if (val_lehgth != 1) {
-+			PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n");
-+			return PAUSE_FAIL;
-+		}
-+		/*SOML_ON/OFF*/
-+		ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off);
-+
-+		pause_lv_pre = &dm->pause_lv_table.lv_adsl;
-+		bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val);
-+		 /*@function pointer hook*/
-+		func_t->pause_phydm_handler = phydm_set_adsl_val;
-+
-+#endif
-+	} else {
-+		PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n");
-+		return PAUSE_FAIL;
-+	}
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n",
-+		  pause_lv, *pause_lv_pre);
-+
-+	if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) {
-+		if (pause_lv <= *pause_lv_pre) {
-+			PHYDM_DBG(dm, ODM_COMP_API,
-+				  "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
-+			return PAUSE_FAIL;
-+		}
-+
-+		if (!(dm->pause_ability & pause_func_bitmap)) {
-+			for (i = 0; i < val_lehgth; i++)
-+				bkp_val[i] = ori_val[i];
-+		}
-+
-+		dm->pause_ability |= pause_func_bitmap;
-+		PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
-+			  dm->pause_ability);
-+
-+		if (pause_type == PHYDM_PAUSE) {
-+			for (i = 0; i < val_lehgth; i++)
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",
-+					  i, val_buf[i], bkp_val[i]);
-+			func_t->pause_phydm_handler(dm, val_buf, val_lehgth);
-+		} else {
-+			for (i = 0; i < val_lehgth; i++)
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",
-+					  i, bkp_val[i]);
-+		}
-+
-+		*pause_lv_pre = pause_lv;
-+		pause_result = PAUSE_SUCCESS;
-+
-+	} else if (pause_type == PHYDM_RESUME) {
-+		if (pause_lv < *pause_lv_pre) {
-+			PHYDM_DBG(dm, ODM_COMP_API,
-+				  "[Resume FAIL] Pre_LV >= Curr_LV\n");
-+			return PAUSE_FAIL;
-+		}
-+
-+		if ((dm->pause_ability & pause_func_bitmap) == 0) {
-+			PHYDM_DBG(dm, ODM_COMP_API,
-+				  "[RESUME] No Need to Revert\n");
-+			return PAUSE_SUCCESS;
-+		}
-+
-+		dm->pause_ability &= ~pause_func_bitmap;
-+		PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n",
-+			  dm->pause_ability);
-+
-+		*pause_lv_pre = PHYDM_PAUSE_RELEASE;
-+
-+		for (i = 0; i < val_lehgth; i++) {
-+			PHYDM_DBG(dm, ODM_COMP_API,
-+				  "[RESUME] val_idx[%d]={0x%x}\n", i,
-+				  bkp_val[i]);
-+		}
-+
-+		func_t->pause_phydm_handler(dm, bkp_val, val_lehgth);
-+
-+		pause_result = PAUSE_SUCCESS;
-+	} else {
-+		PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n");
-+		pause_result = PAUSE_FAIL;
-+	}
-+	return pause_result;
-+}
-+
-+void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
-+			      char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 i;
-+	u8 length = 0;
-+	u32 buf[5] = {0};
-+	u8 set_result = 0;
-+	enum phydm_func_idx func = 0;
-+	enum phydm_pause_type type = 0;
-+	enum phydm_pause_level lv = 0;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n");
-+
-+		goto out;
-+	}
-+
-+	for (i = 0; i < 10; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
-+	}
-+
-+	func = (enum phydm_func_idx)var1[0];
-+	type = (enum phydm_pause_type)var1[1];
-+	lv = (enum phydm_pause_level)var1[2];
-+
-+	for (i = 0; i < 5; i++)
-+		buf[i] = var1[3 + i];
-+
-+	if (func == F00_DIG) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[DIG]\n");
-+		length = 1;
-+
-+	} else if (func == F05_CCK_PD) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[CCK_PD]\n");
-+		length = 1;
-+	} else if (func == F06_ANT_DIV) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[Ant_Div]\n");
-+		length = 1;
-+	} else if (func == F13_ADPTVTY) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[Adaptivity]\n");
-+		length = 2;
-+	} else if (func == F17_ADPTV_SOML) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[ADSL]\n");
-+		length = 1;
-+	} else {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[Set Function Error]\n");
-+		length = 0;
-+	}
-+
-+	if (length != 0) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{%s, lv=%d} val = %d, %d}\n",
-+			 ((type == PHYDM_PAUSE) ? "Pause" :
-+			 ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
-+			 lv, var1[3], var1[4]);
-+
-+		set_result = phydm_pause_func(dm, func, type, lv, length, buf);
-+	}
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "set_result = %d\n", set_result);
-+
-+out:
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm,
-+				enum phydm_pause_type pause_type, u8 rssi)
-+{
-+	u32 igi_val = rssi + 10;
-+	u32 th_buf[2];
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] rssi=%d\n", __func__,
-+		  ((pause_type == PHYDM_PAUSE) ? "Pause" :
-+		  ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")),
-+		  rssi);
-+
-+	if (pause_type == PHYDM_RESUME) {
-+		phydm_pause_func(dm, F00_DIG, PHYDM_RESUME,
-+				 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
-+
-+		phydm_pause_func(dm, F13_ADPTVTY, PHYDM_RESUME,
-+				 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
-+	} else {
-+		odm_write_dig(dm, (u8)igi_val);
-+		phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE,
-+				 PHYDM_PAUSE_LEVEL_1, 1, &igi_val);
-+
-+		th_buf[0] = 0xff;
-+		th_buf[1] = 0xff;
-+
-+		phydm_pause_func(dm, F13_ADPTVTY, PHYDM_PAUSE,
-+				 PHYDM_PAUSE_LEVEL_1, 2, th_buf);
-+	}
-+}
-+
-+u8 phydm_stop_dm_watchdog_check(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->disable_phydm_watchdog == 1) {
-+		PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n");
-+		return true;
-+	} else {
-+		return false;
-+	}
-+}
-+
-+void phydm_watchdog(struct dm_struct *dm)
-+{
-+	PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
-+
-+	phydm_common_info_self_update(dm);
-+	phydm_phy_info_update(dm);
-+	phydm_rssi_monitor_check(dm);
-+	phydm_basic_dbg_message(dm);
-+	phydm_dm_summary(dm, FIRST_MACID);
-+#ifdef PHYDM_AUTO_DEGBUG
-+	phydm_auto_dbg_engine(dm);
-+#endif
-+	phydm_receiver_blocking(dm);
-+
-+	if (phydm_stop_dm_watchdog_check(dm) == true)
-+		return;
-+
-+	phydm_hw_setting(dm);
-+
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	if (dm->original_dig_restore == 0) {
-+		phydm_tdma_dig_timer_check(dm);
-+	} else
-+#endif
-+	{
-+		phydm_false_alarm_counter_statistics(dm);
-+	#if (ODM_IC_11N_SERIES_SUPPORT || ODM_IC_11AC_SERIES_SUPPORT)
-+		if (dm->support_ic_type & (ODM_IC_11N_SERIES |
-+					   ODM_IC_11AC_SERIES))
-+			phydm_noisy_detection(dm);
-+	#endif
-+
-+	#if defined(PHYDM_DCC_ENHANCE) && defined(PHYDM_SUPPORT_CCKPD)
-+		phydm_dig_cckpd_coex(dm);
-+	#else
-+		phydm_dig(dm);
-+		#ifdef PHYDM_SUPPORT_CCKPD
-+		phydm_cck_pd_th(dm);
-+		#endif
-+	#endif
-+	}
-+
-+#ifdef PHYDM_HW_IGI
-+	phydm_hwigi(dm);
-+#endif
-+#ifdef PHYDM_POWER_TRAINING_SUPPORT
-+	phydm_update_power_training_state(dm);
-+#endif
-+	phydm_adaptivity(dm);
-+	phydm_ra_info_watchdog(dm);
-+#ifdef CONFIG_PATH_DIVERSITY
-+	phydm_tx_path_diversity(dm);
-+#endif
-+	phydm_cfo_tracking(dm);
-+#ifdef CONFIG_DYNAMIC_TX_TWR
-+	phydm_dynamic_tx_power(dm);
-+#endif
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	odm_antenna_diversity(dm);
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+	phydm_adaptive_soml(dm);
-+#endif
-+
-+#ifdef PHYDM_BEAMFORMING_VERSION1
-+	phydm_beamforming_watchdog(dm);
-+#endif
-+
-+	halrf_watchdog(dm);
-+#ifdef PHYDM_PRIMARY_CCA
-+	phydm_primary_cca(dm);
-+#endif
-+#ifdef CONFIG_BW_INDICATION
-+	phydm_dyn_bw_indication(dm);
-+#endif
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	odm_dtc(dm);
-+#endif
-+
-+	phydm_env_mntr_watchdog(dm);
-+	phydm_enhance_mntr_watchdog(dm);
-+
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+	phydm_lna_sat_chk_watchdog(dm);
-+#endif
-+
-+#ifdef CONFIG_MCC_DM
-+	phydm_mcc_switch(dm);
-+#endif
-+
-+#ifdef CONFIG_MU_RSOML
-+	phydm_mu_rsoml_decision(dm);
-+#endif
-+
-+	phydm_common_info_self_reset(dm);
-+}
-+
-+void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx,
-+			 boolean enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 h2c_val[H2C_MAX_LENGTH] = {0};
-+	u8 para4[4]; /*4 bit*/
-+	u8 para8[4]; /*8 bit*/
-+	u8 i = 0;
-+
-+	for (i = 0; i < 4; i++) {
-+		para4[i] = 0;
-+		para8[i] = 0;
-+	}
-+
-+	switch (fun_idx) {
-+	case F00_DIG:
-+		phydm_fill_fw_dig_info(dm, &enable, para4, para8);
-+		break;
-+	default:
-+		pr_debug("[Warning] %s\n", __func__);
-+		return;
-+	}
-+
-+	h2c_val[0] = (u8)((fun_idx & 0x3f) | (enable << 6));
-+	h2c_val[1] = para8[0];
-+	h2c_val[2] = para8[1];
-+	h2c_val[3] = para8[2];
-+	h2c_val[4] = para8[3];
-+	h2c_val[5] = (para4[0] & 0xf) | ((para4[1] & 0xf) << 3);
-+	h2c_val[6] = (para4[2] & 0xf) | ((para4[3] & 0xf) << 3);
-+
-+	PHYDM_DBG(dm, DBG_FW_DM,
-+		  "H2C[0x59] fun_idx=%d,en=%d,para8={%x %x %x %x},para4={%x %x %x %x}\n",
-+		  fun_idx, enable,
-+		  para8[0], para8[1], para8[2], para8[3],
-+		  para4[0], para4[1], para4[2], para4[3]);
-+
-+	odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_DM_CTRL, H2C_MAX_LENGTH, h2c_val);
-+}
-+
-+/*@
-+ * Init /.. Fixed HW value. Only init time.
-+ */
-+void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info,
-+		       u64 value)
-+{
-+	/* This section is used for init value */
-+	switch (cmn_info) {
-+	/* @Fixed ODM value. */
-+	case ODM_CMNINFO_ABILITY:
-+		dm->support_ability = (u64)value;
-+		break;
-+
-+	case ODM_CMNINFO_RF_TYPE:
-+		dm->rf_type = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_PLATFORM:
-+		dm->support_platform = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_INTERFACE:
-+		dm->support_interface = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_MP_TEST_CHIP:
-+		dm->is_mp_chip = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_IC_TYPE:
-+		dm->support_ic_type = (u32)value;
-+		break;
-+
-+	case ODM_CMNINFO_CUT_VER:
-+		dm->cut_version = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_FAB_VER:
-+		dm->fab_version = (u8)value;
-+		break;
-+	case ODM_CMNINFO_FW_VER:
-+		dm->fw_version = (u8)value;
-+		break;
-+	case ODM_CMNINFO_FW_SUB_VER:
-+		dm->fw_sub_version = (u8)value;
-+		break;
-+	case ODM_CMNINFO_RFE_TYPE:
-+#if (RTL8821C_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8821C)
-+			dm->rfe_type_expand = (u8)value;
-+		else
-+#endif
-+			dm->rfe_type = (u8)value;
-+
-+#ifdef CONFIG_RFE_BY_HW_INFO
-+		phydm_init_hw_info_by_rfe(dm);
-+#endif
-+		break;
-+
-+	case ODM_CMNINFO_RF_ANTENNA_TYPE:
-+		dm->ant_div_type = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
-+		dm->with_extenal_ant_switch = (u8)value;
-+		break;
-+
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	case ODM_CMNINFO_BE_FIX_TX_ANT:
-+		dm->dm_fat_table.b_fix_tx_ant = (u8)value;
-+		break;
-+#endif
-+
-+	case ODM_CMNINFO_BOARD_TYPE:
-+		if (!dm->is_init_hw_info_by_rfe)
-+			dm->board_type = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_PACKAGE_TYPE:
-+		if (!dm->is_init_hw_info_by_rfe)
-+			dm->package_type = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_EXT_LNA:
-+		if (!dm->is_init_hw_info_by_rfe)
-+			dm->ext_lna = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_5G_EXT_LNA:
-+		if (!dm->is_init_hw_info_by_rfe)
-+			dm->ext_lna_5g = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_EXT_PA:
-+		if (!dm->is_init_hw_info_by_rfe)
-+			dm->ext_pa = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_5G_EXT_PA:
-+		if (!dm->is_init_hw_info_by_rfe)
-+			dm->ext_pa_5g = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_GPA:
-+		if (!dm->is_init_hw_info_by_rfe)
-+			dm->type_gpa = (u16)value;
-+		break;
-+
-+	case ODM_CMNINFO_APA:
-+		if (!dm->is_init_hw_info_by_rfe)
-+			dm->type_apa = (u16)value;
-+		break;
-+
-+	case ODM_CMNINFO_GLNA:
-+		if (!dm->is_init_hw_info_by_rfe)
-+			dm->type_glna = (u16)value;
-+		break;
-+
-+	case ODM_CMNINFO_ALNA:
-+		if (!dm->is_init_hw_info_by_rfe)
-+			dm->type_alna = (u16)value;
-+		break;
-+
-+	case ODM_CMNINFO_EXT_TRSW:
-+		if (!dm->is_init_hw_info_by_rfe)
-+			dm->ext_trsw = (u8)value;
-+		break;
-+	case ODM_CMNINFO_EXT_LNA_GAIN:
-+		dm->ext_lna_gain = (u8)value;
-+		break;
-+	case ODM_CMNINFO_PATCH_ID:
-+		dm->iot_table.win_patch_id = (u8)value;
-+		break;
-+	case ODM_CMNINFO_BINHCT_TEST:
-+		dm->is_in_hct_test = (boolean)value;
-+		break;
-+	case ODM_CMNINFO_BWIFI_TEST:
-+		dm->wifi_test = (u8)value;
-+		break;
-+	case ODM_CMNINFO_SMART_CONCURRENT:
-+		dm->is_dual_mac_smart_concurrent = (boolean)value;
-+		break;
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	case ODM_CMNINFO_CONFIG_BB_RF:
-+		dm->config_bbrf = (boolean)value;
-+		break;
-+#endif
-+	case ODM_CMNINFO_IQKPAOFF:
-+		dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
-+		break;
-+	case ODM_CMNINFO_REGRFKFREEENABLE:
-+		dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
-+		break;
-+	case ODM_CMNINFO_RFKFREEENABLE:
-+		dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
-+		break;
-+	case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
-+		dm->normal_rx_path = (u8)value;
-+		break;
-+	case ODM_CMNINFO_VALID_PATH_SET:
-+		dm->valid_path_set = (u8)value;
-+		break;
-+	case ODM_CMNINFO_EFUSE0X3D8:
-+		dm->efuse0x3d8 = (u8)value;
-+		break;
-+	case ODM_CMNINFO_EFUSE0X3D7:
-+		dm->efuse0x3d7 = (u8)value;
-+		break;
-+	case ODM_CMNINFO_ADVANCE_OTA:
-+		dm->p_advance_ota = (u8)value;
-+		break;
-+
-+#ifdef CONFIG_PHYDM_DFS_MASTER
-+	case ODM_CMNINFO_DFS_REGION_DOMAIN:
-+		dm->dfs_region_domain = (u8)value;
-+		break;
-+#endif
-+	case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
-+		dm->soft_ap_special_setting = (u32)value;
-+		break;
-+
-+	case ODM_CMNINFO_X_CAP_SETTING:
-+		dm->dm_cfo_track.crystal_cap_default = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_DPK_EN:
-+		/*@dm->dpk_en = (u1Byte)value;*/
-+		halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);
-+		break;
-+
-+	case ODM_CMNINFO_HP_HWID:
-+		dm->hp_hw_id = (boolean)value;
-+		break;
-+	case ODM_CMNINFO_TSSI_ENABLE:
-+		dm->en_tssi_mode = (u8)value;
-+		break;
-+	case ODM_CMNINFO_DIS_DPD:
-+		dm->en_dis_dpd = (boolean)value;
-+		break;
-+	case ODM_CMNINFO_EN_AUTO_BW_TH:
-+		dm->en_auto_bw_th = (u8)value;
-+		break;
-+#if (RTL8721D_SUPPORT)
-+	case ODM_CMNINFO_POWER_VOLTAGE:
-+		dm->power_voltage = (u8)value;
-+		break;
-+	case ODM_CMNINFO_ANTDIV_GPIO:
-+		dm->antdiv_gpio = (u8)value;
-+		break;
-+	case ODM_CMNINFO_PEAK_DETECT_MODE:
-+		dm->peak_detect_mode = (u8)value;
-+		break;
-+#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info,
-+		       void *value)
-+{
-+	/* @Hook call by reference pointer. */
-+	switch (cmn_info) {
-+	/* @Dynamic call by reference pointer. */
-+	case ODM_CMNINFO_TX_UNI:
-+		dm->num_tx_bytes_unicast = (u64 *)value;
-+		break;
-+
-+	case ODM_CMNINFO_RX_UNI:
-+		dm->num_rx_bytes_unicast = (u64 *)value;
-+		break;
-+
-+	case ODM_CMNINFO_BAND:
-+		dm->band_type = (u8 *)value;
-+		break;
-+
-+	case ODM_CMNINFO_SEC_CHNL_OFFSET:
-+		dm->sec_ch_offset = (u8 *)value;
-+		break;
-+
-+	case ODM_CMNINFO_SEC_MODE:
-+		dm->security = (u8 *)value;
-+		break;
-+
-+	case ODM_CMNINFO_BW:
-+		dm->band_width = (u8 *)value;
-+		break;
-+
-+	case ODM_CMNINFO_CHNL:
-+		dm->channel = (u8 *)value;
-+		break;
-+
-+	case ODM_CMNINFO_SCAN:
-+		dm->is_scan_in_process = (boolean *)value;
-+		break;
-+
-+	case ODM_CMNINFO_POWER_SAVING:
-+		dm->is_power_saving = (boolean *)value;
-+		break;
-+
-+	case ODM_CMNINFO_TDMA:
-+		dm->is_tdma = (boolean *)value;
-+		break;
-+
-+	case ODM_CMNINFO_ONE_PATH_CCA:
-+		dm->one_path_cca = (u8 *)value;
-+		break;
-+
-+	case ODM_CMNINFO_DRV_STOP:
-+		dm->is_driver_stopped = (boolean *)value;
-+		break;
-+	case ODM_CMNINFO_INIT_ON:
-+		dm->pinit_adpt_in_progress = (boolean *)value;
-+		break;
-+
-+	case ODM_CMNINFO_ANT_TEST:
-+		dm->antenna_test = (u8 *)value;
-+		break;
-+
-+	case ODM_CMNINFO_NET_CLOSED:
-+		dm->is_net_closed = (boolean *)value;
-+		break;
-+
-+	case ODM_CMNINFO_FORCED_RATE:
-+		dm->forced_data_rate = (u16 *)value;
-+		break;
-+	case ODM_CMNINFO_ANT_DIV:
-+		dm->enable_antdiv = (u8 *)value;
-+		break;
-+	case ODM_CMNINFO_PATH_DIV:
-+		dm->enable_pathdiv = (u8 *)value;
-+		break;
-+	case ODM_CMNINFO_ADAPTIVE_SOML:
-+		dm->en_adap_soml = (u8 *)value;
-+		break;
-+	case ODM_CMNINFO_ADAPTIVITY:
-+		dm->edcca_mode = (u8 *)value;
-+		break;
-+
-+	case ODM_CMNINFO_P2P_LINK:
-+		dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
-+		break;
-+
-+	case ODM_CMNINFO_IS1ANTENNA:
-+		dm->is_1_antenna = (boolean *)value;
-+		break;
-+
-+	case ODM_CMNINFO_RFDEFAULTPATH:
-+		dm->rf_default_path = (u8 *)value;
-+		break;
-+
-+	case ODM_CMNINFO_FCS_MODE: /* @fast channel switch (= MCC mode)*/
-+		dm->is_fcs_mode_enable = (boolean *)value;
-+		break;
-+
-+	case ODM_CMNINFO_HUBUSBMODE:
-+		dm->hub_usb_mode = (u8 *)value;
-+		break;
-+	case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
-+		dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;
-+		break;
-+	case ODM_CMNINFO_TX_TP:
-+		dm->current_tx_tp = (u32 *)value;
-+		break;
-+	case ODM_CMNINFO_RX_TP:
-+		dm->current_rx_tp = (u32 *)value;
-+		break;
-+	case ODM_CMNINFO_SOUNDING_SEQ:
-+		dm->sounding_seq = (u8 *)value;
-+		break;
-+#ifdef CONFIG_PHYDM_DFS_MASTER
-+	case ODM_CMNINFO_DFS_MASTER_ENABLE:
-+		dm->dfs_master_enabled = (u8 *)value;
-+		break;
-+#endif
-+
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
-+		dm->dm_fat_table.p_force_tx_by_desc = (u8 *)value;
-+		break;
-+	case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
-+		dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
-+		break;
-+	case ODM_CMNINFO_BF_ANTDIV_DECISION:
-+		dm->dm_fat_table.is_no_csi_feedback = (boolean *)value;
-+		break;
-+#endif
-+
-+	case ODM_CMNINFO_SOFT_AP_MODE:
-+		dm->soft_ap_mode = (u32 *)value;
-+		break;
-+	case ODM_CMNINFO_MP_MODE:
-+		dm->mp_mode = (u8 *)value;
-+		break;
-+	case ODM_CMNINFO_INTERRUPT_MASK:
-+		dm->interrupt_mask = (u32 *)value;
-+		break;
-+	case ODM_CMNINFO_BB_OPERATION_MODE:
-+		dm->bb_op_mode = (u8 *)value;
-+		break;
-+	case ODM_CMNINFO_MANUAL_SUPPORTABILITY:
-+		dm->manual_supportability = (u32 *)value;
-+		break;
-+	case ODM_CMNINFO_EN_DYM_BW_INDICATION:
-+		dm->dis_dym_bw_indication = (u8 *)value;
-+	default:
-+		/*do nothing*/
-+		break;
-+	}
-+}
-+
-+/*@
-+ * Update band/CHannel/.. The values are dynamic but non-per-packet.
-+ */
-+void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value)
-+{
-+	/* This init variable may be changed in run time. */
-+	switch (cmn_info) {
-+	case ODM_CMNINFO_LINK_IN_PROGRESS:
-+		dm->is_link_in_process = (boolean)value;
-+		break;
-+
-+	case ODM_CMNINFO_ABILITY:
-+		dm->support_ability = (u64)value;
-+		break;
-+
-+	case ODM_CMNINFO_RF_TYPE:
-+		dm->rf_type = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_WIFI_DIRECT:
-+		dm->is_wifi_direct = (boolean)value;
-+		break;
-+
-+	case ODM_CMNINFO_WIFI_DISPLAY:
-+		dm->is_wifi_display = (boolean)value;
-+		break;
-+
-+	case ODM_CMNINFO_LINK:
-+		dm->is_linked = (boolean)value;
-+		break;
-+
-+	case ODM_CMNINFO_CMW500LINK:
-+		dm->iot_table.is_linked_cmw500 = (boolean)value;
-+		break;
-+
-+	case ODM_CMNINFO_STATION_STATE:
-+		dm->bsta_state = (boolean)value;
-+		break;
-+
-+	case ODM_CMNINFO_RSSI_MIN:
-+#if 0
-+		dm->rssi_min = (u8)value;
-+#endif
-+		break;
-+
-+	case ODM_CMNINFO_RSSI_MIN_BY_PATH:
-+		dm->rssi_min_by_path = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_DBG_COMP:
-+		dm->debug_components = (u64)value;
-+		break;
-+
-+#ifdef ODM_CONFIG_BT_COEXIST
-+	/* The following is for BT HS mode and BT coexist mechanism. */
-+	case ODM_CMNINFO_BT_ENABLED:
-+		dm->bt_info_table.is_bt_enabled = (boolean)value;
-+		break;
-+
-+	case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
-+		dm->bt_info_table.is_bt_connect_process = (boolean)value;
-+		break;
-+
-+	case ODM_CMNINFO_BT_HS_RSSI:
-+		dm->bt_info_table.bt_hs_rssi = (u8)value;
-+		break;
-+
-+	case ODM_CMNINFO_BT_OPERATION:
-+		dm->bt_info_table.is_bt_hs_operation = (boolean)value;
-+		break;
-+
-+	case ODM_CMNINFO_BT_LIMITED_DIG:
-+		dm->bt_info_table.is_bt_limited_dig = (boolean)value;
-+		break;
-+#endif
-+
-+	case ODM_CMNINFO_AP_TOTAL_NUM:
-+		dm->ap_total_num = (u8)value;
-+		break;
-+
-+#ifdef CONFIG_PHYDM_DFS_MASTER
-+	case ODM_CMNINFO_DFS_REGION_DOMAIN:
-+		dm->dfs_region_domain = (u8)value;
-+		break;
-+#endif
-+
-+	case ODM_CMNINFO_BT_CONTINUOUS_TURN:
-+		dm->is_bt_continuous_turn = (boolean)value;
-+		break;
-+	case ODM_CMNINFO_IS_DOWNLOAD_FW:
-+		dm->is_download_fw = (boolean)value;
-+		break;
-+	case ODM_CMNINFO_PHYDM_PATCH_ID:
-+		dm->iot_table.phydm_patch_id = (u32)value;
-+		break;
-+	case ODM_CMNINFO_RRSR_VAL:
-+		dm->dm_ra_table.rrsr_val_init = (u32)value;
-+		break;
-+	case ODM_CMNINFO_LINKED_BF_SUPPORT:
-+		dm->linked_bf_support = (u8)value;
-+		break;
-+	case ODM_CMNINFO_FLATNESS_TYPE:
-+		dm->flatness_type = (u8)value;
-+		break;
-+	case ODM_CMNINFO_TSSI_ENABLE:
-+		dm->en_tssi_mode = (u8)value;
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type)
-+{
-+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct ccx_info *ccx_info = &dm->dm_ccx_info;
-+
-+	switch (info_type) {
-+	/*@=== [FA Relative] ===========================================*/
-+	case PHYDM_INFO_FA_OFDM:
-+		return fa_t->cnt_ofdm_fail;
-+
-+	case PHYDM_INFO_FA_CCK:
-+		return fa_t->cnt_cck_fail;
-+
-+	case PHYDM_INFO_FA_TOTAL:
-+		return fa_t->cnt_all;
-+
-+	case PHYDM_INFO_CCA_OFDM:
-+		return fa_t->cnt_ofdm_cca;
-+
-+	case PHYDM_INFO_CCA_CCK:
-+		return fa_t->cnt_cck_cca;
-+
-+	case PHYDM_INFO_CCA_ALL:
-+		return fa_t->cnt_cca_all;
-+
-+	case PHYDM_INFO_CRC32_OK_VHT:
-+		return fa_t->cnt_vht_crc32_ok;
-+
-+	case PHYDM_INFO_CRC32_OK_HT:
-+		return fa_t->cnt_ht_crc32_ok;
-+
-+	case PHYDM_INFO_CRC32_OK_LEGACY:
-+		return fa_t->cnt_ofdm_crc32_ok;
-+
-+	case PHYDM_INFO_CRC32_OK_CCK:
-+		return fa_t->cnt_cck_crc32_ok;
-+
-+	case PHYDM_INFO_CRC32_ERROR_VHT:
-+		return fa_t->cnt_vht_crc32_error;
-+
-+	case PHYDM_INFO_CRC32_ERROR_HT:
-+		return fa_t->cnt_ht_crc32_error;
-+
-+	case PHYDM_INFO_CRC32_ERROR_LEGACY:
-+		return fa_t->cnt_ofdm_crc32_error;
-+
-+	case PHYDM_INFO_CRC32_ERROR_CCK:
-+		return fa_t->cnt_cck_crc32_error;
-+
-+	case PHYDM_INFO_EDCCA_FLAG:
-+		return fa_t->edcca_flag;
-+
-+	case PHYDM_INFO_OFDM_ENABLE:
-+		return fa_t->ofdm_block_enable;
-+
-+	case PHYDM_INFO_CCK_ENABLE:
-+		return fa_t->cck_block_enable;
-+
-+	case PHYDM_INFO_DBG_PORT_0:
-+		return fa_t->dbg_port0;
-+
-+	case PHYDM_INFO_CRC32_OK_HT_AGG:
-+		return fa_t->cnt_ht_crc32_ok_agg;
-+
-+	case PHYDM_INFO_CRC32_ERROR_HT_AGG:
-+		return fa_t->cnt_ht_crc32_error_agg;
-+
-+	/*@=== [DIG] ================================================*/
-+
-+	case PHYDM_INFO_CURR_IGI:
-+		return dig_t->cur_ig_value;
-+
-+	/*@=== [RSSI] ===============================================*/
-+	case PHYDM_INFO_RSSI_MIN:
-+		return (u32)dm->rssi_min;
-+
-+	case PHYDM_INFO_RSSI_MAX:
-+		return (u32)dm->rssi_max;
-+
-+	case PHYDM_INFO_CLM_RATIO:
-+		return (u32)ccx_info->clm_ratio;
-+	case PHYDM_INFO_NHM_RATIO:
-+		return (u32)ccx_info->nhm_ratio;
-+	case PHYDM_INFO_NHM_NOISE_PWR:
-+		return (u32)ccx_info->nhm_level;
-+	case PHYDM_INFO_NHM_PWR:
-+		return (u32)ccx_info->nhm_pwr;
-+	case PHYDM_INFO_NHM_ENV_RATIO:
-+		return (u32)ccx_info->nhm_env_ratio;
-+
-+	default:
-+		return 0xffffffff;
-+	}
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void odm_init_all_work_items(struct dm_struct *dm)
-+{
-+	void *adapter = dm->adapter;
-+#if USE_WORKITEM
-+
-+#ifdef CONFIG_ADAPTIVE_SOML
-+	odm_initialize_work_item(dm,
-+				 &dm->dm_soml_table.phydm_adaptive_soml_workitem,
-+				 (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
-+				 (void *)adapter,
-+				 "AdaptiveSOMLWorkitem");
-+#endif
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	odm_initialize_work_item(dm,
-+				 &dm->phydm_evm_antdiv_workitem,
-+				 (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback,
-+				 (void *)adapter,
-+				 "EvmAntdivWorkitem");
-+#endif
-+
-+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+	odm_initialize_work_item(dm,
-+				 &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
-+				 (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
-+				 (void *)adapter,
-+				 "AntennaSwitchWorkitem");
-+#endif
-+#if (defined(CONFIG_HL_SMART_ANTENNA))
-+	odm_initialize_work_item(dm,
-+				 &dm->dm_sat_table.hl_smart_antenna_workitem,
-+				 (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
-+				 (void *)adapter,
-+				 "hl_smart_ant_workitem");
-+
-+	odm_initialize_work_item(dm,
-+				 &dm->dm_sat_table.hl_smart_antenna_decision_workitem,
-+				 (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
-+				 (void *)adapter,
-+				 "hl_smart_ant_decision_workitem");
-+#endif
-+
-+	odm_initialize_work_item(
-+		dm,
-+		&dm->ra_rpt_workitem,
-+		(RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
-+		(void *)adapter,
-+		"ra_rpt_workitem");
-+
-+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+	odm_initialize_work_item(
-+		dm,
-+		&dm->fast_ant_training_workitem,
-+		(RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
-+		(void *)adapter,
-+		"fast_ant_training_workitem");
-+#endif
-+
-+#endif /*#if USE_WORKITEM*/
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	odm_initialize_work_item(
-+		dm,
-+		&dm->beamforming_info.txbf_info.txbf_enter_work_item,
-+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
-+		(void *)adapter,
-+		"txbf_enter_work_item");
-+
-+	odm_initialize_work_item(
-+		dm,
-+		&dm->beamforming_info.txbf_info.txbf_leave_work_item,
-+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
-+		(void *)adapter,
-+		"txbf_leave_work_item");
-+
-+	odm_initialize_work_item(
-+		dm,
-+		&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,
-+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
-+		(void *)adapter,
-+		"txbf_fw_ndpa_work_item");
-+
-+	odm_initialize_work_item(
-+		dm,
-+		&dm->beamforming_info.txbf_info.txbf_clk_work_item,
-+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
-+		(void *)adapter,
-+		"txbf_clk_work_item");
-+
-+	odm_initialize_work_item(
-+		dm,
-+		&dm->beamforming_info.txbf_info.txbf_rate_work_item,
-+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
-+		(void *)adapter,
-+		"txbf_rate_work_item");
-+
-+	odm_initialize_work_item(
-+		dm,
-+		&dm->beamforming_info.txbf_info.txbf_status_work_item,
-+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
-+		(void *)adapter,
-+		"txbf_status_work_item");
-+
-+	odm_initialize_work_item(
-+		dm,
-+		&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,
-+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
-+		(void *)adapter,
-+		"txbf_reset_tx_path_work_item");
-+
-+	odm_initialize_work_item(
-+		dm,
-+		&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,
-+		(RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
-+		(void *)adapter,
-+		"txbf_get_tx_rate_work_item");
-+#endif
-+
-+#if (PHYDM_LA_MODE_SUPPORT == 1)
-+	odm_initialize_work_item(
-+		dm,
-+		&dm->adcsmp.adc_smp_work_item,
-+		(RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
-+		(void *)adapter,
-+		"adc_smp_work_item");
-+
-+	odm_initialize_work_item(
-+		dm,
-+		&dm->adcsmp.adc_smp_work_item_1,
-+		(RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
-+		(void *)adapter,
-+		"adc_smp_work_item_1");
-+#endif
-+}
-+
-+void odm_free_all_work_items(struct dm_struct *dm)
-+{
-+#if USE_WORKITEM
-+
-+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+	odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);
-+#endif
-+
-+#ifdef CONFIG_ADAPTIVE_SOML
-+	odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);
-+#endif
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	odm_free_work_item(&dm->phydm_evm_antdiv_workitem);
-+#endif
-+
-+#if (defined(CONFIG_HL_SMART_ANTENNA))
-+	odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);
-+	odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);
-+#endif
-+
-+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+	odm_free_work_item(&dm->fast_ant_training_workitem);
-+#endif
-+	odm_free_work_item(&dm->ra_rpt_workitem);
-+/*odm_free_work_item((&dm->sbdcnt_workitem));*/
-+#endif
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));
-+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));
-+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
-+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));
-+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));
-+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));
-+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
-+	odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
-+#endif
-+
-+#if (PHYDM_LA_MODE_SUPPORT == 1)
-+	odm_free_work_item((&dm->adcsmp.adc_smp_work_item));
-+	odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));
-+#endif
-+}
-+#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
-+
-+void odm_init_all_timers(struct dm_struct *dm)
-+{
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+	odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);
-+#endif
-+#if (defined(PHYDM_TDMA_DIG_SUPPORT))
-+#ifdef IS_USE_NEW_TDMA
-+	phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER);
-+#endif
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+	phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);
-+#endif
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+	phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	odm_initialize_timer(dm, &dm->sbdcnt_timer,
-+			     (void *)phydm_sbd_callback, NULL, "SbdTimer");
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
-+			     (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL,
-+			     "txbf_fw_ndpa_timer");
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,
-+			     (void *)beamforming_sw_timer_callback, NULL,
-+			     "beamforming_timer");
-+#endif
-+#endif
-+}
-+
-+void odm_cancel_all_timers(struct dm_struct *dm)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	/* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/
-+	if (dm->adapter == NULL)
-+		return;
-+#endif
-+
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+	odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);
-+#endif
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+#ifdef IS_USE_NEW_TDMA
-+	phydm_tdma_dig_timers(dm, CANCEL_TDMA_DIG_TIMMER);
-+#endif
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+	phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);
-+#endif
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+	phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	odm_cancel_timer(dm, &dm->sbdcnt_timer);
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);
-+#endif
-+#endif
-+}
-+
-+void odm_release_all_timers(struct dm_struct *dm)
-+{
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+	odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);
-+#endif
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+#ifdef IS_USE_NEW_TDMA
-+	phydm_tdma_dig_timers(dm, RELEASE_TDMA_DIG_TIMMER);
-+#endif
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+	phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);
-+#endif
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+	phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	odm_release_timer(dm, &dm->sbdcnt_timer);
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	odm_release_timer(dm, &dm->beamforming_info.beamforming_timer);
-+#endif
-+#endif
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+void odm_init_all_threads(
-+	struct dm_struct *dm)
-+{
-+#ifdef TPT_THREAD
-+	k_tpt_task_init(dm->priv);
-+#endif
-+}
-+
-+void odm_stop_all_threads(
-+	struct dm_struct *dm)
-+{
-+#ifdef TPT_THREAD
-+	k_tpt_task_stop(dm->priv);
-+#endif
-+}
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+/* @Justin: According to the current RRSI to adjust Response Frame TX power,
-+ * 2012/11/05
-+ */
-+void odm_dtc(struct dm_struct *dm)
-+{
-+#ifdef CONFIG_DM_RESP_TXAGC
-+/* RSSI higher than this value, start to decade TX power */
-+#define DTC_BASE 35
-+
-+/* RSSI lower than this value, start to increase TX power */
-+#define DTC_DWN_BASE (DTC_BASE - 5)
-+
-+	/* RSSI vs TX power step mapping: decade TX power */
-+	static const u8 dtc_table_down[] = {
-+		DTC_BASE,
-+		(DTC_BASE + 5),
-+		(DTC_BASE + 10),
-+		(DTC_BASE + 15),
-+		(DTC_BASE + 20),
-+		(DTC_BASE + 25)};
-+
-+	/* RSSI vs TX power step mapping: increase TX power */
-+	static const u8 dtc_table_up[] = {
-+		DTC_DWN_BASE,
-+		(DTC_DWN_BASE - 5),
-+		(DTC_DWN_BASE - 10),
-+		(DTC_DWN_BASE - 15),
-+		(DTC_DWN_BASE - 15),
-+		(DTC_DWN_BASE - 20),
-+		(DTC_DWN_BASE - 20),
-+		(DTC_DWN_BASE - 25),
-+		(DTC_DWN_BASE - 25),
-+		(DTC_DWN_BASE - 30),
-+		(DTC_DWN_BASE - 35)};
-+
-+	u8 i;
-+	u8 dtc_steps = 0;
-+	u8 sign;
-+	u8 resp_txagc = 0;
-+
-+	if (dm->rssi_min > DTC_BASE) {
-+		/* need to decade the CTS TX power */
-+		sign = 1;
-+		for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
-+			if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6)
-+				break;
-+			else
-+				dtc_steps++;
-+		}
-+	}
-+#if 0
-+	else if (dm->rssi_min > DTC_DWN_BASE) {
-+		/* needs to increase the CTS TX power */
-+		sign = 0;
-+		dtc_steps = 1;
-+		for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
-+			if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10)
-+				break;
-+			else
-+				dtc_steps++;
-+		}
-+	}
-+#endif
-+	else {
-+		sign = 0;
-+		dtc_steps = 0;
-+	}
-+
-+	resp_txagc = dtc_steps | (sign << 4);
-+	resp_txagc = resp_txagc | (resp_txagc << 5);
-+	odm_write_1byte(dm, 0x06d9, resp_txagc);
-+
-+	PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN,
-+		  "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__,
-+		  dm->rssi_min, sign ? "minus" : "plus", dtc_steps);
-+#endif /* @CONFIG_RESP_TXAGC_ADJUST */
-+}
-+
-+#endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
-+
-+/*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
-+void phydm_dc_cancellation(struct dm_struct *dm)
-+{
-+#ifdef PHYDM_DC_CANCELLATION
-+	u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};
-+	u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};
-+	u32 reg_value32[PHYDM_MAX_RF_PATH] = {0};
-+	u8 path = RF_PATH_A;
-+	u8 set_result;
-+
-+	if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
-+		return;
-+	if ((dm->support_ic_type & ODM_RTL8188F) &&
-+	    dm->cut_version < ODM_CUT_D)
-+		return;
-+	if ((dm->support_ic_type & ODM_RTL8192F) &&
-+	    dm->cut_version == ODM_CUT_A)
-+		return;
-+	if (*dm->band_width == CHANNEL_WIDTH_5)
-+		return;
-+	if (*dm->band_width == CHANNEL_WIDTH_10)
-+		return;
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
-+
-+	/*@DC_Estimation (only for 2x2 ic now) */
-+
-+	for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {
-+		if (path > RF_PATH_A &&
-+		    dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F |
-+					  ODM_RTL8710B | ODM_RTL8721D |
-+					  ODM_RTL8710C | ODM_RTL8723D))
-+			break;
-+		else if (path > RF_PATH_B &&
-+			 dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F))
-+			break;
-+		if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
-+			PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
-+			return;
-+		}
-+		odm_write_dig(dm, 0x7e);
-+		/*@Disable LNA*/
-+		if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
-+					   ODM_RTL8710C))
-+			halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
-+		/*Turn off 3-wire*/
-+		phydm_stop_3_wire(dm, PHYDM_SET);
-+		if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
-+			ODM_RTL8710B)) {
-+			/*set debug port to 0x235*/
-+			if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "Set Debug port Fail\n");
-+				return;
-+			}
-+		} else if (dm->support_ic_type & (ODM_RTL8721D |
-+			ODM_RTL8710C)) {
-+			/*set debug port to 0x200*/
-+			if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) {
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "Set Debug port Fail\n");
-+				return;
-+			}
-+		} else if (dm->support_ic_type & ODM_RTL8821C) {
-+			if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
-+				/*set debug port to 0x200*/
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "Set Debug port Fail\n");
-+				return;
-+			}
-+			phydm_bb_dbg_port_header_sel(dm, 0x0);
-+		} else if (dm->support_ic_type & ODM_RTL8822B) {
-+			if (path == RF_PATH_A &&
-+			    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) {
-+				/*set debug port to 0x200*/
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "Set Debug port Fail\n");
-+				return;
-+			}
-+			if (path == RF_PATH_B &&
-+			    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x202)) {
-+				/*set debug port to 0x200*/
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "Set Debug port Fail\n");
-+				return;
-+			}
-+			phydm_bb_dbg_port_header_sel(dm, 0x0);
-+		} else if (dm->support_ic_type & ODM_RTL8192F) {
-+			if (path == RF_PATH_A &&
-+			    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) {
-+				/*set debug port to 0x235*/
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "Set Debug port Fail\n");
-+				return;
-+			}
-+			if (path == RF_PATH_B &&
-+			    !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x23d)) {
-+				/*set debug port to 0x23d*/
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "Set Debug port Fail\n");
-+				return;
-+			}
-+		}
-+
-+		/*@disable CCK DCNF*/
-+		odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0);
-+
-+		PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n");
-+
-+		phydm_stop_ck320(dm, true); /*stop ck320*/
-+
-+		/* the same debug port both for path-a and path-b*/
-+		reg_value32[path] = phydm_get_bb_dbg_port_val(dm);
-+
-+		phydm_stop_ck320(dm, false); /*start ck320*/
-+
-+		phydm_release_bb_dbg_port(dm);
-+		/* @Turn on 3-wire*/
-+		phydm_stop_3_wire(dm, PHYDM_REVERT);
-+		/* @Enable LNA*/
-+		if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
-+					   ODM_RTL8710C))
-+			halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
-+
-+		odm_write_dig(dm, 0x20);
-+
-+		set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
-+
-+		PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n");
-+	}
-+
-+	/*@DC_Cancellation*/
-+	/*@DC compensation to CCK data path*/
-+	odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1);
-+	if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D |
-+		ODM_RTL8710B)) {
-+		offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
-+		offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
-+
-+		/*@Before filling into registers,
-+		 *offset should be multiplexed (-1)
-+		 */
-+		offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
-+				  (0x400 - offset_i_hex[0]) :
-+				  (0x1ff - offset_i_hex[0]);
-+		offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
-+				  (0x400 - offset_q_hex[0]) :
-+				  (0x1ff - offset_q_hex[0]);
-+
-+		odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
-+		odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
-+	} else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
-+		/* Path-a */
-+		offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
-+		offset_q_hex[0] = reg_value32[0] & 0x3ff;
-+
-+		/*@Before filling into registers,
-+		 *offset should be multiplexed (-1)
-+		 */
-+		offset_i_hex[0] = 0x400 - offset_i_hex[0];
-+		offset_q_hex[0] = 0x400 - offset_q_hex[0];
-+
-+		odm_set_bb_reg(dm, R_0xc10, 0x3c000000,
-+			       (0x3c0 & offset_i_hex[0]) >> 6);
-+		odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]);
-+		odm_set_bb_reg(dm, R_0xc14, 0x3c000000,
-+			       (0x3c0 & offset_q_hex[0]) >> 6);
-+		odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]);
-+
-+		/* Path-b */
-+		if (dm->rf_type > RF_1T1R) {
-+			offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
-+			offset_q_hex[1] = reg_value32[1] & 0x3ff;
-+
-+			/*@Before filling into registers,
-+			 *offset should be multiplexed (-1)
-+			 */
-+			offset_i_hex[1] = 0x400 - offset_i_hex[1];
-+			offset_q_hex[1] = 0x400 - offset_q_hex[1];
-+
-+			odm_set_bb_reg(dm, R_0xe10, 0x3c000000,
-+				       (0x3c0 & offset_i_hex[1]) >> 6);
-+			odm_set_bb_reg(dm, R_0xe10, 0xfc00,
-+				       0x3f & offset_i_hex[1]);
-+			odm_set_bb_reg(dm, R_0xe14, 0x3c000000,
-+				       (0x3c0 & offset_q_hex[1]) >> 6);
-+			odm_set_bb_reg(dm, R_0xe14, 0xfc00,
-+				       0x3f & offset_q_hex[1]);
-+		}
-+	} else if (dm->support_ic_type & (ODM_RTL8192F)) {
-+		/* Path-a I:df4[27:18],Q:df4[17:8]*/
-+		offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
-+		offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
-+
-+		/*@Before filling into registers,
-+		 *offset should be multiplexed (-1)
-+		 */
-+		offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ?
-+				  (0x400 - offset_i_hex[0]) :
-+				  (0xff - offset_i_hex[0]);
-+		offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ?
-+				  (0x400 - offset_q_hex[0]) :
-+				  (0xff - offset_q_hex[0]);
-+		/*Path-a I:c10[7:0],Q:c10[15:8]*/
-+		odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]);
-+		odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]);
-+
-+		/* Path-b */
-+		if (dm->rf_type > RF_1T1R) {
-+			/* @I:df4[27:18],Q:df4[17:8]*/
-+			offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18;
-+			offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8;
-+
-+			/*@Before filling into registers,
-+			 *offset should be multiplexed (-1)
-+			 */
-+			offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ?
-+					  (0x400 - offset_i_hex[1]) :
-+					  (0xff - offset_i_hex[1]);
-+			offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ?
-+					  (0x400 - offset_q_hex[1]) :
-+					  (0xff - offset_q_hex[1]);
-+			/*Path-b I:c18[7:0],Q:c18[15:8]*/
-+			odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]);
-+			odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]);
-+		}
-+	} else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
-+	 /*judy modified 20180517*/
-+		offset_i_hex[0] = (reg_value32[0] & 0xff80000) >> 19;
-+		offset_q_hex[0] = (reg_value32[0] & 0x3fe00) >> 9;
-+
-+		if ((offset_i_hex[0] > 0xF && offset_i_hex[0] < 0x1F1)
-+		    || (offset_q_hex[0] > 0xF && offset_q_hex[0] < 0x1F1)) {
-+		    	/*@Discard outliers*/
-+		   	 offset_i_hex[0] = 0x0;
-+		   	 offset_q_hex[0] = 0x0;	
-+		} else {
-+			/*@Before filling into registers,
-+		 	*offset should be multiplexed (-1)
-+			 */
-+			offset_i_hex[0] = 0x200 - offset_i_hex[0];
-+			offset_q_hex[0] = 0x200 - offset_q_hex[0];
-+		}
-+		odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]);
-+		odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]);
-+	}
-+#endif
-+}
-+
-+void phydm_receiver_blocking(void *dm_void)
-+{
-+#ifdef CONFIG_RECEIVER_BLOCKING
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 chnl = *dm->channel;
-+	u8 bw = *dm->band_width;
-+	u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000);
-+
-+	if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) ||
-+	    *dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
-+		return;
-+
-+	if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) ||
-+	    dm->support_ic_type & ODM_RTL8192E) {
-+	    /*@8188E_T version*/
-+		if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
-+			goto end;
-+
-+		if (bw == CHANNEL_WIDTH_20 && chnl == 1) {
-+			phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410,
-+					  PHYDM_DONT_CARE);
-+			dm->is_rx_blocking_en = true;
-+		} else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) {
-+			phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
-+					  PHYDM_DONT_CARE);
-+			dm->is_rx_blocking_en = true;
-+		} else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) {
-+			phydm_nbi_enable(dm, FUNC_DISABLE);
-+			odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
-+			dm->is_rx_blocking_en = false;
-+		}
-+		return;
-+	} else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) {
-+	/*@8188E_S version*/
-+		if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode)
-+			goto end;
-+
-+		if (bw == CHANNEL_WIDTH_20 && chnl == 13) {
-+			phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473,
-+					  PHYDM_DONT_CARE);
-+			dm->is_rx_blocking_en = true;
-+		} else if (dm->is_rx_blocking_en && chnl != 13) {
-+			phydm_nbi_enable(dm, FUNC_DISABLE);
-+			odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
-+			dm->is_rx_blocking_en = false;
-+		}
-+		return;
-+	}
-+
-+end:
-+	if (dm->is_rx_blocking_en) {
-+		phydm_nbi_enable(dm, FUNC_DISABLE);
-+		odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f);
-+		dm->is_rx_blocking_en = false;
-+	}
-+#endif
-+}
-+
-+void phydm_dyn_bw_indication(void *dm_void)
-+{
-+#ifdef CONFIG_BW_INDICATION
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 en_auto_bw_th = dm->en_auto_bw_th;
-+
-+	if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
-+		return;
-+
-+	/*driver decide bw cobime timing*/
-+	if (dm->dis_dym_bw_indication) {
-+		if (*dm->dis_dym_bw_indication)
-+			return;
-+	}
-+
-+	/*check for auto bw*/
-+	if (dm->rssi_min <= en_auto_bw_th && dm->is_linked) {
-+		phydm_bw_fixed_enable(dm, FUNC_DISABLE);
-+		return;
-+	}
-+
-+	phydm_bw_fixed_setting(dm);
-+#endif
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm.h b/drivers/staging/rtl8723cs/hal/phydm/phydm.h
-new file mode 100644
-index 000000000000..233528fc87f3
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm.h
-@@ -0,0 +1,1566 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALDMOUTSRC_H__
-+#define __HALDMOUTSRC_H__
-+
-+/*@============================================================*/
-+/*@include files*/
-+/*@============================================================*/
-+/*PHYDM header*/
-+#include "phydm_pre_define.h"
-+#include "phydm_features.h"
-+#include "phydm_dig.h"
-+#ifdef CONFIG_PATH_DIVERSITY
-+#include "phydm_pathdiv.h"
-+#endif
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+#include "phydm_antdiv.h"
-+#endif
-+
-+#include "phydm_soml.h"
-+
-+#ifdef CONFIG_SMART_ANTENNA
-+#include "phydm_smt_ant.h"
-+#endif
-+#ifdef CONFIG_ANT_DETECTION
-+#include "phydm_antdect.h"
-+#endif
-+#include "phydm_rainfo.h"
-+#ifdef CONFIG_DYNAMIC_TX_TWR
-+#include "phydm_dynamictxpower.h"
-+#endif
-+#include "phydm_cfotracking.h"
-+#include "phydm_adaptivity.h"
-+#include "phydm_dfs.h"
-+#include "phydm_ccx.h"
-+#include "txbf/phydm_hal_txbf_api.h"
-+#if (PHYDM_LA_MODE_SUPPORT)
-+#include "phydm_adc_sampling.h"
-+#endif
-+#ifdef CONFIG_PSD_TOOL
-+#include "phydm_psd.h"
-+#endif
-+#ifdef PHYDM_PRIMARY_CCA
-+#include "phydm_primary_cca.h"
-+#endif
-+#include "phydm_cck_pd.h"
-+#include "phydm_rssi_monitor.h"
-+#ifdef PHYDM_AUTO_DEGBUG
-+#include "phydm_auto_dbg.h"
-+#endif
-+#include "phydm_math_lib.h"
-+#include "phydm_noisemonitor.h"
-+#include "phydm_api.h"
-+#ifdef PHYDM_POWER_TRAINING_SUPPORT
-+#include "phydm_pow_train.h"
-+#endif
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+#include "phydm_lna_sat.h"
-+#endif
-+#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
-+#include "phydm_pmac_tx_setting.h"
-+#endif
-+#ifdef PHYDM_MP_SUPPORT
-+#include "phydm_mp.h"
-+#endif
-+
-+#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
-+#include "phydm_cck_rx_pathdiv.h"
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	#include "phydm_beamforming.h"
-+#endif
-+
-+#ifdef CONFIG_DIRECTIONAL_BF
-+#include "phydm_direct_bf.h"
-+#endif
-+
-+#include "phydm_regtable.h"
-+
-+/*@HALRF header*/
-+#include "halrf/halrf_iqk.h"
-+#include "halrf/halrf_dpk.h"
-+#include "halrf/halrf.h"
-+#include "halrf/halrf_powertracking.h"
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	#include "halrf/halphyrf_ap.h"
-+#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+	#include "halrf/halphyrf_ce.h"
-+#elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+	#include "halrf/halphyrf_win.h"
-+#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+	#include "halrf/halphyrf_iot.h"
-+#endif
-+
-+extern const u16	phy_rate_table[84];
-+
-+/*@============================================================*/
-+/*@Definition */
-+/*@============================================================*/
-+
-+/* Traffic load decision */
-+#define TRAFFIC_NO_TP			0
-+#define	TRAFFIC_ULTRA_LOW		1
-+#define	TRAFFIC_LOW			2
-+#define	TRAFFIC_MID			3
-+#define	TRAFFIC_HIGH			4
-+
-+#define	NONE				0
-+
-+#if defined(DM_ODM_CE_MAC80211)
-+#define MAX_2(x, y)					\
-+	__max2(typeof(x), typeof(y),			\
-+	      x, y)
-+#define __max2(t1, t2, x, y) ({		\
-+	t1 m80211_max1 = (x);					\
-+	t2 m80211_max2 = (y);					\
-+	m80211_max1 > m80211_max2 ? m80211_max1 : m80211_max2; })
-+
-+#define MIN_2(x, y)					\
-+	__min2(typeof(x), typeof(y),			\
-+	      x, y)
-+#define __min2(t1, t2, x, y) ({		\
-+	t1 m80211_min1 = (x);					\
-+	t2 m80211_min2 = (y);					\
-+	m80211_min1 < m80211_min2 ? m80211_min1 : m80211_min2; })
-+
-+#define DIFF_2(x, y)					\
-+	__diff2(typeof(x), typeof(y),			\
-+	      x, y)
-+#define __diff2(t1, t2, x, y) ({		\
-+	t1 __d1 = (x);					\
-+	t2 __d2 = (y);					\
-+	(__d1 >= __d2) ? (__d1 - __d2) : (__d2 - __d1); })
-+#else
-+#define MAX_2(_x_, _y_)	(((_x_) > (_y_)) ? (_x_) : (_y_))
-+#define MIN_2(_x_, _y_)	(((_x_) < (_y_)) ? (_x_) : (_y_))
-+#define DIFF_2(_x_, _y_)	((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_))
-+#endif
-+
-+#define IS_GREATER(_x_, _y_)	(((_x_) >= (_y_)) ? true : false)
-+#define IS_LESS(_x_, _y_)	(((_x_) < (_y_)) ? true : false)
-+
-+#if defined(DM_ODM_CE_MAC80211)
-+#define BYTE_DUPLICATE_2_DWORD(B0) ({	\
-+	u32 __b_dup = (B0);\
-+	(((__b_dup) << 24) | ((__b_dup) << 16) | ((__b_dup) << 8) | (__b_dup));\
-+	})
-+#else
-+#define BYTE_DUPLICATE_2_DWORD(B0)	\
-+	(((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0))
-+#endif
-+#define BYTE_2_DWORD(B3, B2, B1, B0)	\
-+	(((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0))
-+#define BIT_2_BYTE(B3, B2, B1, B0)	\
-+	(((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0))
-+
-+/*@For cmn sta info*/
-+#if defined(DM_ODM_CE_MAC80211)
-+#define is_sta_active(sta) ({	\
-+	struct cmn_sta_info *__sta = (sta);	\
-+	((__sta) && (__sta->dm_ctrl & STA_DM_CTRL_ACTIVE));	\
-+	})
-+
-+#define IS_FUNC_EN(name) ({	\
-+	u8 *__is_func_name = (name);	\
-+	(__is_func_name) && (*__is_func_name);	\
-+	})
-+#else
-+#define is_sta_active(sta)	((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE))
-+
-+#define IS_FUNC_EN(name)	((name) && (*name))
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	#define PHYDM_WATCH_DOG_PERIOD	1 /*second*/
-+#else
-+	#define PHYDM_WATCH_DOG_PERIOD	2 /*second*/
-+#endif
-+
-+#define PHY_HIST_SIZE		12
-+#define PHY_HIST_TH_SIZE	(PHY_HIST_SIZE - 1)
-+
-+/*@============================================================*/
-+/*structure and define*/
-+/*@============================================================*/
-+
-+#define		dm_type_by_fw		0
-+#define		dm_type_by_driver	1
-+
-+#define		HW_IGI_TXINFO_TABLE_SIZE 64
-+
-+#ifdef BB_RAM_SUPPORT
-+
-+struct phydm_bb_ram_per_sta {
-+	/* @Reg0x1E84 for RAM I/O*/
-+	boolean			hw_igi_en;
-+	boolean			tx_pwr_offset0_en;
-+	boolean			tx_pwr_offset1_en;
-+	/* @ macid from 0 to 63, above 63 => mapping to 63*/
-+	u8			macid_addr;
-+	/* @hw_igi value for paths after packet Tx in a period of time*/
-+	u8			hw_igi;
-+	/* @tx_pwr_offset0 offset for Tx power index*/
-+	s8			tx_pwr_offset0;
-+	s8			tx_pwr_offset1;
-+
-+};
-+
-+struct phydm_bb_ram_ctrl {
-+	/*@ For 98F/14B/22C/12F, each tx_pwr_ofst step will be 1dB*/
-+	struct phydm_bb_ram_per_sta pram_sta_ctrl[HW_IGI_TXINFO_TABLE_SIZE];
-+	/*------------ For table2 do not set power offset by macid --------*/
-+	/* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */
-+	boolean			tx_pwr_ofst_reg0_en;
-+	u8			tx_pwr_ofst_reg0;
-+	/* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */
-+	boolean			tx_pwr_ofst_reg1_en;
-+	u8			tx_pwr_ofst_reg1;
-+	boolean			hwigi_watchdog_en;
-+	u64			macid_is_linked;
-+	u64			hwigi_macid_is_linked;
-+};
-+
-+#endif
-+
-+struct phydm_phystatus_statistic {
-+	/*@[CCK]*/
-+	u32			rssi_cck_sum;
-+	u32			rssi_cck_cnt;
-+	u32			rssi_beacon_sum[RF_PATH_MEM_SIZE];
-+	u32			rssi_beacon_cnt;
-+	#ifdef PHYSTS_3RD_TYPE_SUPPORT
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	u32			rssi_cck_sum_abv_2ss[RF_PATH_MEM_SIZE - 1];
-+	#endif
-+	#endif
-+	/*@[OFDM]*/
-+	u32			rssi_ofdm_sum[RF_PATH_MEM_SIZE];
-+	u32			rssi_ofdm_cnt;
-+	u32			evm_ofdm_sum;
-+	u32			snr_ofdm_sum[RF_PATH_MEM_SIZE];
-+	u16			evm_ofdm_hist[PHY_HIST_SIZE];
-+	u16			snr_ofdm_hist[PHY_HIST_SIZE];
-+	/*@[1SS]*/
-+	u32			rssi_1ss_cnt;
-+	u32			rssi_1ss_sum[RF_PATH_MEM_SIZE];
-+	u32			evm_1ss_sum;
-+	u32			snr_1ss_sum[RF_PATH_MEM_SIZE];
-+	u16			evm_1ss_hist[PHY_HIST_SIZE];
-+	u16			snr_1ss_hist[PHY_HIST_SIZE];
-+	/*@[2SS]*/
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	u32			rssi_2ss_cnt;
-+	u32			rssi_2ss_sum[RF_PATH_MEM_SIZE];
-+	u32			evm_2ss_sum[2];
-+	u32			snr_2ss_sum[RF_PATH_MEM_SIZE];
-+	u16			evm_2ss_hist[2][PHY_HIST_SIZE];
-+	u16			snr_2ss_hist[2][PHY_HIST_SIZE];
-+	#endif
-+	/*@[3SS]*/
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	u32			rssi_3ss_cnt;
-+	u32			rssi_3ss_sum[RF_PATH_MEM_SIZE];
-+	u32			evm_3ss_sum[3];
-+	u32			snr_3ss_sum[RF_PATH_MEM_SIZE];
-+	u16			evm_3ss_hist[3][PHY_HIST_SIZE];
-+	u16			snr_3ss_hist[3][PHY_HIST_SIZE];
-+	#endif
-+	/*@[4SS]*/
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	u32			rssi_4ss_cnt;
-+	u32			rssi_4ss_sum[RF_PATH_MEM_SIZE];
-+	u32			evm_4ss_sum[4];
-+	u32			snr_4ss_sum[RF_PATH_MEM_SIZE];
-+	u16			evm_4ss_hist[4][PHY_HIST_SIZE];
-+	u16			snr_4ss_hist[4][PHY_HIST_SIZE];
-+	#endif
-+#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
-+	u16			p4_cnt[RF_PATH_MEM_SIZE]; /*phy-sts page4 cnt*/
-+	u16			cn_sum[RF_PATH_MEM_SIZE]; /*condition number*/
-+	u16			cn_hist[RF_PATH_MEM_SIZE][PHY_HIST_SIZE];
-+#endif
-+};
-+
-+struct phydm_phystatus_avg {
-+	/*@[CCK]*/
-+	u8			rssi_cck_avg;
-+	u8			rssi_beacon_avg[RF_PATH_MEM_SIZE];
-+	#ifdef PHYSTS_3RD_TYPE_SUPPORT
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	u8			rssi_cck_avg_abv_2ss[RF_PATH_MEM_SIZE - 1];
-+	#endif
-+	#endif
-+	/*@[OFDM]*/
-+	u8			rssi_ofdm_avg[RF_PATH_MEM_SIZE];
-+	u8			evm_ofdm_avg;
-+	u8			snr_ofdm_avg[RF_PATH_MEM_SIZE];
-+	/*@[1SS]*/
-+	u8			rssi_1ss_avg[RF_PATH_MEM_SIZE];
-+	u8			evm_1ss_avg;
-+	u8			snr_1ss_avg[RF_PATH_MEM_SIZE];
-+	/*@[2SS]*/
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	u8			rssi_2ss_avg[RF_PATH_MEM_SIZE];
-+	u8			evm_2ss_avg[2];
-+	u8			snr_2ss_avg[RF_PATH_MEM_SIZE];
-+	#endif
-+	/*@[3SS]*/
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	u8			rssi_3ss_avg[RF_PATH_MEM_SIZE];
-+	u8			evm_3ss_avg[3];
-+	u8			snr_3ss_avg[RF_PATH_MEM_SIZE];
-+	#endif
-+	/*@[4SS]*/
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	u8			rssi_4ss_avg[RF_PATH_MEM_SIZE];
-+	u8			evm_4ss_avg[4];
-+	u8			snr_4ss_avg[RF_PATH_MEM_SIZE];
-+	#endif
-+};
-+
-+struct odm_phy_dbg_info {
-+	/*@ODM Write,debug info*/
-+	u32			num_qry_phy_status_cck;
-+	u32			num_qry_phy_status_ofdm;
-+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT))
-+	u32			num_qry_mu_pkt;
-+	u32			num_qry_bf_pkt;
-+	u16			num_mu_vht_pkt[VHT_RATE_NUM];
-+	boolean			is_ldpc_pkt;
-+	boolean			is_stbc_pkt;
-+	u8			num_of_ppdu[4];
-+	u8			gid_num[4];
-+#endif
-+	u32			condi_num; /*@condition number U(18,4)*/
-+	u8			condi_num_cdf[CN_CNT_MAX];
-+	u8			num_qry_beacon_pkt;
-+	u8			beacon_cnt_in_period; /*@beacon cnt within watchdog period*/
-+	u8			beacon_phy_rate;
-+	u8			show_phy_sts_all_pkt;	/*@Show phy status witch not match BSSID*/
-+	u16			show_phy_sts_max_cnt;	/*@show number of phy-status row data per PHYDM watchdog*/
-+	u16			show_phy_sts_cnt;
-+	u16			num_qry_legacy_pkt[LEGACY_RATE_NUM];
-+	u16			num_qry_ht_pkt[HT_RATE_NUM];
-+	u16			num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*@20M SC*/
-+	boolean			ht_pkt_not_zero;
-+	boolean			low_bw_20_occur;
-+	#if ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)
-+	u16			num_qry_vht_pkt[VHT_RATE_NUM];
-+	u16			num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*@40M SC*/
-+	boolean			vht_pkt_not_zero;
-+	boolean			low_bw_40_occur;
-+	#endif
-+	u16			snr_hist_th[PHY_HIST_TH_SIZE];
-+	u16			evm_hist_th[PHY_HIST_TH_SIZE];
-+	#ifdef PHYSTS_3RD_TYPE_SUPPORT
-+	u16			cn_hist_th[PHY_HIST_TH_SIZE]; /*U(16,1)*/
-+	u8			condition_num_seg0;
-+	u8			eigen_val[4];
-+	s16			cfo_tail[4]; /*per-path's cfo_tail */
-+	#endif
-+	struct phydm_phystatus_statistic	physts_statistic_info;
-+	struct phydm_phystatus_avg		phystatus_statistic_avg;
-+};
-+
-+enum odm_cmninfo {
-+	/*@Fixed value*/
-+	/*@-----------HOOK BEFORE REG INIT-----------*/
-+	ODM_CMNINFO_PLATFORM = 0,
-+	ODM_CMNINFO_ABILITY,
-+	ODM_CMNINFO_INTERFACE,
-+	ODM_CMNINFO_MP_TEST_CHIP,
-+	ODM_CMNINFO_IC_TYPE,
-+	ODM_CMNINFO_CUT_VER,
-+	ODM_CMNINFO_FAB_VER,
-+	ODM_CMNINFO_FW_VER,
-+	ODM_CMNINFO_FW_SUB_VER,
-+	ODM_CMNINFO_RF_TYPE,
-+	ODM_CMNINFO_RFE_TYPE,
-+	ODM_CMNINFO_DPK_EN,
-+	ODM_CMNINFO_BOARD_TYPE,
-+	ODM_CMNINFO_PACKAGE_TYPE,
-+	ODM_CMNINFO_EXT_LNA,
-+	ODM_CMNINFO_5G_EXT_LNA,
-+	ODM_CMNINFO_EXT_PA,
-+	ODM_CMNINFO_5G_EXT_PA,
-+	ODM_CMNINFO_GPA,
-+	ODM_CMNINFO_APA,
-+	ODM_CMNINFO_GLNA,
-+	ODM_CMNINFO_ALNA,
-+	ODM_CMNINFO_TDMA,
-+	ODM_CMNINFO_EXT_TRSW,
-+	ODM_CMNINFO_EXT_LNA_GAIN,
-+	ODM_CMNINFO_PATCH_ID,
-+	ODM_CMNINFO_BINHCT_TEST,
-+	ODM_CMNINFO_BWIFI_TEST,
-+	ODM_CMNINFO_SMART_CONCURRENT,
-+	ODM_CMNINFO_CONFIG_BB_RF,
-+	ODM_CMNINFO_IQKPAOFF,
-+	ODM_CMNINFO_HUBUSBMODE,
-+	ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
-+	ODM_CMNINFO_TX_TP,
-+	ODM_CMNINFO_RX_TP,
-+	ODM_CMNINFO_SOUNDING_SEQ,
-+	ODM_CMNINFO_REGRFKFREEENABLE,
-+	ODM_CMNINFO_RFKFREEENABLE,
-+	ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
-+	ODM_CMNINFO_VALID_PATH_SET,
-+	ODM_CMNINFO_EFUSE0X3D8,
-+	ODM_CMNINFO_EFUSE0X3D7,
-+	ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING,
-+	ODM_CMNINFO_X_CAP_SETTING,
-+	ODM_CMNINFO_ADVANCE_OTA,
-+	ODM_CMNINFO_HP_HWID,
-+	ODM_CMNINFO_TSSI_ENABLE, /*also for cmn_info_update*/
-+	ODM_CMNINFO_DIS_DPD,
-+	ODM_CMNINFO_POWER_VOLTAGE,
-+	ODM_CMNINFO_ANTDIV_GPIO,
-+	ODM_CMNINFO_EN_AUTO_BW_TH,
-+	ODM_CMNINFO_PEAK_DETECT_MODE,
-+	/*@-----------HOOK BEFORE REG INIT-----------*/
-+
-+	/*@Dynamic value:*/
-+
-+	/*@--------- POINTER REFERENCE-----------*/
-+	ODM_CMNINFO_TX_UNI,
-+	ODM_CMNINFO_RX_UNI,
-+	ODM_CMNINFO_BAND,
-+	ODM_CMNINFO_SEC_CHNL_OFFSET,
-+	ODM_CMNINFO_SEC_MODE,
-+	ODM_CMNINFO_BW,
-+	ODM_CMNINFO_CHNL,
-+	ODM_CMNINFO_FORCED_RATE,
-+	ODM_CMNINFO_ANT_DIV,
-+	ODM_CMNINFO_PATH_DIV,
-+	ODM_CMNINFO_ADAPTIVE_SOML,
-+	ODM_CMNINFO_ADAPTIVITY,
-+	ODM_CMNINFO_SCAN,
-+	ODM_CMNINFO_POWER_SAVING,
-+	ODM_CMNINFO_ONE_PATH_CCA,
-+	ODM_CMNINFO_DRV_STOP,
-+	ODM_CMNINFO_PNP_IN,
-+	ODM_CMNINFO_INIT_ON,
-+	ODM_CMNINFO_ANT_TEST,
-+	ODM_CMNINFO_NET_CLOSED,
-+	ODM_CMNINFO_P2P_LINK,
-+	ODM_CMNINFO_FCS_MODE,
-+	ODM_CMNINFO_IS1ANTENNA,
-+	ODM_CMNINFO_RFDEFAULTPATH,
-+	ODM_CMNINFO_DFS_MASTER_ENABLE,
-+	ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
-+	ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
-+	ODM_CMNINFO_SOFT_AP_MODE,
-+	ODM_CMNINFO_MP_MODE,
-+	ODM_CMNINFO_INTERRUPT_MASK,
-+	ODM_CMNINFO_BB_OPERATION_MODE,
-+	ODM_CMNINFO_BF_ANTDIV_DECISION,
-+	ODM_CMNINFO_MANUAL_SUPPORTABILITY,
-+	ODM_CMNINFO_EN_DYM_BW_INDICATION,
-+	/*@--------- POINTER REFERENCE-----------*/
-+
-+	/*@------------CALL BY VALUE-------------*/
-+	ODM_CMNINFO_WIFI_DIRECT,
-+	ODM_CMNINFO_WIFI_DISPLAY,
-+	ODM_CMNINFO_LINK_IN_PROGRESS,
-+	ODM_CMNINFO_LINK,
-+	ODM_CMNINFO_CMW500LINK,
-+	ODM_CMNINFO_STATION_STATE,
-+	ODM_CMNINFO_RSSI_MIN,
-+	ODM_CMNINFO_RSSI_MIN_BY_PATH,
-+	ODM_CMNINFO_DBG_COMP,
-+	ODM_CMNINFO_RA_THRESHOLD_HIGH,	/*to be removed*/
-+	ODM_CMNINFO_RA_THRESHOLD_LOW,	/*to be removed*/
-+	ODM_CMNINFO_RF_ANTENNA_TYPE,
-+	ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
-+	ODM_CMNINFO_BE_FIX_TX_ANT,
-+	ODM_CMNINFO_BT_ENABLED,
-+	ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
-+	ODM_CMNINFO_BT_HS_RSSI,
-+	ODM_CMNINFO_BT_OPERATION,
-+	ODM_CMNINFO_BT_LIMITED_DIG,
-+	ODM_CMNINFO_AP_TOTAL_NUM,
-+	ODM_CMNINFO_POWER_TRAINING,
-+	ODM_CMNINFO_DFS_REGION_DOMAIN,
-+	ODM_CMNINFO_BT_CONTINUOUS_TURN,
-+	ODM_CMNINFO_IS_DOWNLOAD_FW,
-+	ODM_CMNINFO_PHYDM_PATCH_ID,
-+	ODM_CMNINFO_RRSR_VAL,
-+	ODM_CMNINFO_LINKED_BF_SUPPORT,
-+	ODM_CMNINFO_FLATNESS_TYPE,
-+	/*@------------CALL BY VALUE-------------*/
-+
-+	/*@Dynamic ptr array hook itms.*/
-+	ODM_CMNINFO_STA_STATUS,
-+	ODM_CMNINFO_MAX,
-+
-+};
-+
-+enum phydm_rfe_bb_source_sel {
-+	PAPE_2G			= 0,
-+	PAPE_5G			= 1,
-+	LNA0N_2G		= 2,
-+	LNAON_5G		= 3,
-+	TRSW			= 4,
-+	TRSW_B			= 5,
-+	GNT_BT			= 6,
-+	ZERO			= 7,
-+	ANTSEL_0		= 8,
-+	ANTSEL_1		= 9,
-+	ANTSEL_2		= 0xa,
-+	ANTSEL_3		= 0xb,
-+	ANTSEL_4		= 0xc,
-+	ANTSEL_5		= 0xd,
-+	ANTSEL_6		= 0xe,
-+	ANTSEL_7		= 0xf
-+};
-+
-+enum phydm_info_query {
-+	PHYDM_INFO_FA_OFDM,
-+	PHYDM_INFO_FA_CCK,
-+	PHYDM_INFO_FA_TOTAL,
-+	PHYDM_INFO_CCA_OFDM,
-+	PHYDM_INFO_CCA_CCK,
-+	PHYDM_INFO_CCA_ALL,
-+	PHYDM_INFO_CRC32_OK_VHT,
-+	PHYDM_INFO_CRC32_OK_HT,
-+	PHYDM_INFO_CRC32_OK_LEGACY,
-+	PHYDM_INFO_CRC32_OK_CCK,
-+	PHYDM_INFO_CRC32_ERROR_VHT,
-+	PHYDM_INFO_CRC32_ERROR_HT,
-+	PHYDM_INFO_CRC32_ERROR_LEGACY,
-+	PHYDM_INFO_CRC32_ERROR_CCK,
-+	PHYDM_INFO_EDCCA_FLAG,
-+	PHYDM_INFO_OFDM_ENABLE,
-+	PHYDM_INFO_CCK_ENABLE,
-+	PHYDM_INFO_CRC32_OK_HT_AGG,
-+	PHYDM_INFO_CRC32_ERROR_HT_AGG,
-+	PHYDM_INFO_DBG_PORT_0,
-+	PHYDM_INFO_CURR_IGI,
-+	PHYDM_INFO_RSSI_MIN,
-+	PHYDM_INFO_RSSI_MAX,
-+	PHYDM_INFO_CLM_RATIO,
-+	PHYDM_INFO_NHM_RATIO,
-+	PHYDM_INFO_NHM_NOISE_PWR,
-+	PHYDM_INFO_NHM_PWR,
-+	PHYDM_INFO_NHM_ENV_RATIO,
-+
-+};
-+
-+enum phydm_api {
-+	PHYDM_API_NBI		= 1,
-+	PHYDM_API_CSI_MASK	= 2,
-+};
-+
-+enum phydm_func_idx { /*@F_XXX = PHYDM XXX function*/
-+
-+	F00_DIG			= 0,
-+	F01_RA_MASK		= 1,
-+	F02_DYN_TXPWR		= 2,
-+	F03_FA_CNT		= 3,
-+	F04_RSSI_MNTR		= 4,
-+	F05_CCK_PD		= 5,
-+	F06_ANT_DIV		= 6,
-+	F07_SMT_ANT		= 7,
-+	F08_PWR_TRAIN		= 8,
-+	F09_RA			= 9,
-+	F10_PATH_DIV		= 10,
-+	F11_DFS			= 11,
-+	F12_DYN_ARFR		= 12,
-+	F13_ADPTVTY		= 13,
-+	F14_CFO_TRK		= 14,
-+	F15_ENV_MNTR		= 15,
-+	F16_PRI_CCA		= 16,
-+	F17_ADPTV_SOML		= 17,
-+	F18_LNA_SAT_CHK		= 18,
-+};
-+
-+/*@=[PHYDM supportability]==========================================*/
-+enum odm_ability {
-+	ODM_BB_DIG		= BIT(F00_DIG),
-+	ODM_BB_RA_MASK		= BIT(F01_RA_MASK),
-+	ODM_BB_DYNAMIC_TXPWR	= BIT(F02_DYN_TXPWR),
-+	ODM_BB_FA_CNT		= BIT(F03_FA_CNT),
-+	ODM_BB_RSSI_MONITOR	= BIT(F04_RSSI_MNTR),
-+	ODM_BB_CCK_PD		= BIT(F05_CCK_PD),
-+	ODM_BB_ANT_DIV		= BIT(F06_ANT_DIV),
-+	ODM_BB_SMT_ANT		= BIT(F07_SMT_ANT),
-+	ODM_BB_PWR_TRAIN	= BIT(F08_PWR_TRAIN),
-+	ODM_BB_RATE_ADAPTIVE	= BIT(F09_RA),
-+	ODM_BB_PATH_DIV		= BIT(F10_PATH_DIV),
-+	ODM_BB_DFS		= BIT(F11_DFS),
-+	ODM_BB_DYNAMIC_ARFR	= BIT(F12_DYN_ARFR),
-+	ODM_BB_ADAPTIVITY	= BIT(F13_ADPTVTY),
-+	ODM_BB_CFO_TRACKING	= BIT(F14_CFO_TRK),
-+	ODM_BB_ENV_MONITOR	= BIT(F15_ENV_MNTR),
-+	ODM_BB_PRIMARY_CCA	= BIT(F16_PRI_CCA),
-+	ODM_BB_ADAPTIVE_SOML	= BIT(F17_ADPTV_SOML),
-+	ODM_BB_LNA_SAT_CHK	= BIT(F18_LNA_SAT_CHK),
-+};
-+
-+/*@=[PHYDM Debug Component]=====================================*/
-+enum phydm_dbg_comp {
-+	/*@BB Driver Functions*/
-+	DBG_DIG			= BIT(F00_DIG),
-+	DBG_RA_MASK		= BIT(F01_RA_MASK),
-+	DBG_DYN_TXPWR		= BIT(F02_DYN_TXPWR),
-+	DBG_FA_CNT		= BIT(F03_FA_CNT),
-+	DBG_RSSI_MNTR		= BIT(F04_RSSI_MNTR),
-+	DBG_CCKPD		= BIT(F05_CCK_PD),
-+	DBG_ANT_DIV		= BIT(F06_ANT_DIV),
-+	DBG_SMT_ANT		= BIT(F07_SMT_ANT),
-+	DBG_PWR_TRAIN		= BIT(F08_PWR_TRAIN),
-+	DBG_RA			= BIT(F09_RA),
-+	DBG_PATH_DIV		= BIT(F10_PATH_DIV),
-+	DBG_DFS			= BIT(F11_DFS),
-+	DBG_DYN_ARFR		= BIT(F12_DYN_ARFR),
-+	DBG_ADPTVTY		= BIT(F13_ADPTVTY),
-+	DBG_CFO_TRK		= BIT(F14_CFO_TRK),
-+	DBG_ENV_MNTR		= BIT(F15_ENV_MNTR),
-+	DBG_PRI_CCA		= BIT(F16_PRI_CCA),
-+	DBG_ADPTV_SOML		= BIT(F17_ADPTV_SOML),
-+	DBG_LNA_SAT_CHK		= BIT(F18_LNA_SAT_CHK),
-+	/*Neet to re-arrange*/
-+	DBG_PHY_STATUS		= BIT(20),
-+	DBG_TMP			= BIT(21),
-+	DBG_FW_TRACE		= BIT(22),
-+	DBG_TXBF		= BIT(23),
-+	DBG_COMMON_FLOW		= BIT(24),
-+	DBG_COMP_MCC		= BIT(25),
-+	DBG_FW_DM		= BIT(26),
-+	DBG_DM_SUMMARY		= BIT(27),
-+	ODM_PHY_CONFIG		= BIT(28),
-+	ODM_COMP_INIT		= BIT(29),
-+	DBG_CMN			= BIT(30),/*@common*/
-+	ODM_COMP_API		= BIT(31)
-+};
-+
-+/*@=========================================================*/
-+
-+/*@ODM_CMNINFO_ONE_PATH_CCA*/
-+enum odm_cca_path {
-+	ODM_CCA_2R		= 0,
-+	ODM_CCA_1R_A		= 1,
-+	ODM_CCA_1R_B		= 2,
-+};
-+
-+enum phy_reg_pg_type {
-+	PHY_REG_PG_RELATIVE_VALUE = 0,
-+	PHY_REG_PG_EXACT_VALUE	= 1
-+};
-+
-+enum phydm_offload_ability {
-+	PHYDM_PHY_PARAM_OFFLOAD = BIT(0),
-+	PHYDM_RF_IQK_OFFLOAD	= BIT(1),
-+	PHYDM_RF_DPK_OFFLOAD	= BIT(2),
-+};
-+
-+enum phydm_init_result {
-+	PHYDM_INIT_SUCCESS = 0,
-+	PHYDM_INIT_FAIL_BBRF_REG_INVALID = 1
-+};
-+
-+struct phydm_pause_lv {
-+	s8			lv_dig;
-+	s8			lv_cckpd;
-+	s8			lv_antdiv;
-+	s8			lv_adapt;
-+	s8			lv_adsl;
-+};
-+
-+struct phydm_func_poiner {
-+	void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len);
-+};
-+
-+struct pkt_process_info {
-+	#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
-+	/*@send phystatus in each sampling time*/
-+	boolean			physts_auto_swch_en;
-+	u8			mac_ppdu_cnt;
-+	u8			phy_ppdu_cnt; /*change with phy cca cnt*/
-+	u8			page_bitmap_target;
-+	u8			page_bitmap_record;
-+	u8			ppdu_phy_rate;
-+	u8			ppdu_macid;
-+	boolean			is_1st_mpdu;
-+	#endif
-+	u8			lna_idx;
-+	u8			vga_idx;
-+};
-+
-+#ifdef ODM_CONFIG_BT_COEXIST
-+struct	phydm_bt_info {
-+	boolean			is_bt_enabled;		/*@BT is enabled*/
-+	boolean			is_bt_connect_process;	/*@BT HS is under connection progress.*/
-+	u8			bt_hs_rssi;		/*@BT HS mode wifi rssi value.*/
-+	boolean			is_bt_hs_operation;	/*@BT HS mode is under progress*/
-+	boolean			is_bt_limited_dig;	/*@BT is busy.*/
-+};
-+#endif
-+
-+struct	phydm_iot_center {
-+	boolean			is_linked_cmw500;
-+	u8			win_patch_id;		/*Customer ID*/
-+	boolean			patch_id_100f0401;
-+	boolean			patch_id_10120200;
-+	boolean			patch_id_40010700;
-+	boolean			patch_id_021f0800;
-+	boolean			patch_id_011f0500;
-+	u32			phydm_patch_id;		/*temp for CCX IOT */
-+};
-+
-+#if (RTL8822B_SUPPORT)
-+struct drp_rtl8822b_struct {
-+	enum bb_path path_judge;
-+	u16 path_a_cck_fa;
-+	u16 path_b_cck_fa;
-+};
-+#endif
-+
-+#ifdef CONFIG_MCC_DM
-+#define MCC_DM_REG_NUM	32
-+struct _phydm_mcc_dm_ {
-+	u8		mcc_pre_status;
-+	u8		mcc_reg_id[MCC_DM_REG_NUM];
-+	u16		mcc_dm_reg[MCC_DM_REG_NUM];
-+	u8		mcc_dm_val[MCC_DM_REG_NUM][2];
-+	/*mcc DIG*/
-+	u8		mcc_rssi[2];
-+	/*u8		mcc_igi[2];*/
-+
-+	/* need to be config by driver*/
-+	u8		mcc_status;
-+	u8		sta_macid[2][NUM_STA];
-+	u16		mcc_rf_ch[2];
-+
-+};
-+#endif
-+
-+#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
-+struct phydm_physts {
-+	u8			cck_gi_u_bnd;
-+	u8			cck_gi_l_bnd;
-+};
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	#if (RT_PLATFORM != PLATFORM_LINUX)
-+		typedef
-+	#endif
-+
-+struct dm_struct {
-+#else/*for AP, CE Team*/
-+struct dm_struct {
-+#endif
-+	/*@Add for different team use temporarily*/
-+	void			*adapter;		/*@For CE/NIC team*/
-+	struct rtl8192cd_priv	*priv;			/*@For AP team*/
-+	boolean			odm_ready;
-+	enum phy_reg_pg_type	phy_reg_pg_value_type;
-+	u8			phy_reg_pg_version;
-+	u64			support_ability;	/*@PHYDM function Supportability*/
-+	u64			pause_ability;		/*@PHYDM function pause Supportability*/
-+	u64			debug_components;
-+	u8			cmn_dbg_msg_period;
-+	u8			cmn_dbg_msg_cnt;
-+	u32			fw_debug_components;
-+	u32			num_qry_phy_status_all;	/*@CCK + OFDM*/
-+	u32			last_num_qry_phy_status_all;
-+	u32			rx_pwdb_ave;
-+	boolean		is_init_hw_info_by_rfe;
-+
-+	//TSSI
-+	u8			en_tssi_mode;
-+
-+	/*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
-+	boolean			is_cck_high_power;
-+	u8			rf_path_rx_enable;
-+	/*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
-+
-+	/* @COMMON INFORMATION */
-+
-+	/*@Init value*/
-+	/*@-----------HOOK BEFORE REG INIT-----------*/
-+
-+	u8			support_platform;	/*@PHYDM Platform info WIN/AP/CE = 1/2/3 */
-+	u8			normal_rx_path;
-+	u8			valid_path_set;	/*@use for single rx path only*/
-+	boolean			brxagcswitch;		/* @for rx AGC table switch in Microsoft case */
-+	u8			support_interface;	/*@PHYDM PCIE/USB/SDIO = 1/2/3*/
-+	u32			support_ic_type;	/*@PHYDM supported IC*/
-+	enum phydm_api_host	run_in_drv_fw;		/*@PHYDM API is using in FW or Driver*/
-+	u8			ic_ip_series;		/*N/AC/JGR3*/
-+	enum phydm_phy_sts_type	ic_phy_sts_type;	/*@Type1/type2/type3*/
-+	u8			cut_version;		/*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
-+	u8			fab_version;		/*@Fab version TSMC/UMC = 0/1*/
-+	u8			fw_version;
-+	u8			fw_sub_version;
-+	u8			rf_type;		/*@RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/
-+	u8			rfe_type;
-+	u8			board_type;
-+	u8			package_type;
-+	u16			type_glna;
-+	u16			type_gpa;
-+	u16			type_alna;
-+	u16			type_apa;
-+	u8			ext_lna;		/*@with 2G external LNA  NO/Yes = 0/1*/
-+	u8			ext_lna_5g;		/*@with 5G external LNA  NO/Yes = 0/1*/
-+	u8			ext_pa;			/*@with 2G external PNA  NO/Yes = 0/1*/
-+	u8			ext_pa_5g;		/*@with 5G external PNA  NO/Yes = 0/1*/
-+	u8			efuse0x3d7;		/*@with Efuse number*/
-+	u8			efuse0x3d8;
-+	u8			ext_trsw;		/*@with external TRSW  NO/Yes = 0/1*/
-+	u8			ext_lna_gain;		/*@gain of external lna*/
-+	boolean			is_in_hct_test;
-+	u8			wifi_test;
-+	boolean			is_dual_mac_smart_concurrent;
-+	u32			bk_support_ability;	/*SD4 only*/
-+	u8			with_extenal_ant_switch;
-+	/*@cck agc relative*/
-+	boolean			cck_new_agc;
-+	s8			cck_lna_gain_table[8];
-+	u8			cck_sat_cnt_th_init;
-+	/*@-------------------------------------*/
-+	u32			phydm_sys_up_time;
-+	u8			num_rf_path;		/*@ex: 8821C=1, 8192E=2, 8814B=4*/
-+	u32			soft_ap_special_setting;
-+	boolean			boolean_dummy;
-+	s8			s8_dummy;
-+	u8			u8_dummy;
-+	u16			u16_dummy;
-+	u32			u32_dummy;
-+	u8			rfe_hwsetting_band;
-+	u8			p_advance_ota;
-+	boolean			hp_hw_id;
-+	boolean			BOOLEAN_temp;
-+	boolean			is_dfs_band;
-+	u8			is_rx_blocking_en;
-+	u16			fw_offload_ability;
-+	boolean			is_download_fw;
-+	boolean			en_dis_dpd;
-+	u16			dis_dpd_rate;
-+	u8			en_auto_bw_th;
-+	#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
-+	u8			txagc_buff[RF_PATH_MEM_SIZE][PHY_NUM_RATE_IDX];
-+	u32			bp_0x9b0;
-+	#endif
-+	#if (RTL8822C_SUPPORT)
-+	u8			ofdm_rxagc_l_bnd[16];
-+	boolean			l_bnd_detect[16];
-+	u16			agc_rf_gain_ori[16][64];/*[table][mp_gain_idx]*/
-+	u16			agc_rf_gain[16][64];/*[table][mp_gain_idx]*/
-+	u8			agc_table_cnt;
-+	boolean			is_agc_tab_pos_shift;
-+	u8			agc_table_shift;
-+	#endif
-+/*@-----------HOOK BEFORE REG INIT-----------*/
-+/*@===========================================================*/
-+/*@====[ CALL BY Reference ]=========================================*/
-+/*@===========================================================*/
-+
-+	u64			*num_tx_bytes_unicast;	/*@TX Unicast byte cnt*/
-+	u64			*num_rx_bytes_unicast;	/*@RX Unicast byte cnt*/
-+	u8			*band_type;		/*@2.4G/5G = 0/1*/
-+	u8			*sec_ch_offset;		/*@Secondary channel offset don't_care/below/above = 0/1/2*/
-+	u8			*security;		/*@security mode Open/WEP/AES/TKIP = 0/1/2/3*/
-+	u8			*band_width;		/*@20M/40M/80M = 0/1/2*/
-+	u8			*channel;		/*@central CH number*/
-+	boolean			*is_scan_in_process;
-+	boolean			*is_power_saving;
-+	boolean			*is_tdma;
-+	u8			*one_path_cca;		/*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/
-+	u8			*antenna_test;
-+	boolean			*is_net_closed;
-+	boolean			*is_fcs_mode_enable;	/*@fast channel switch (= MCC mode)*/
-+	/*@--------- For 8723B IQK-------------------------------------*/
-+	boolean			*is_1_antenna;
-+	u8			*rf_default_path;	/* @0:S1, 1:S0 */
-+	/*@-----------------------------------------------------------*/
-+
-+	u16			*forced_data_rate;
-+	u8			*enable_antdiv;
-+	u8			*enable_pathdiv;
-+	u8			*en_adap_soml;
-+	u8			*edcca_mode;
-+	u8			*hub_usb_mode;		/*@1:USB2.0, 2:USB3.0*/
-+	boolean			*is_fw_dw_rsvd_page_in_progress;
-+	u32			*current_tx_tp;
-+	u32			*current_rx_tp;
-+	u8			*sounding_seq;
-+	u32			*soft_ap_mode;
-+	u8			*mp_mode;
-+	u32			*interrupt_mask;
-+	u8			*bb_op_mode;
-+	u32			*manual_supportability;
-+	u8			*dis_dym_bw_indication;
-+/*@===========================================================*/
-+/*@====[ CALL BY VALUE ]===========================================*/
-+/*@===========================================================*/
-+
-+	u8			disable_phydm_watchdog;
-+	boolean			is_link_in_process;
-+	boolean			is_wifi_direct;
-+	boolean			is_wifi_display;
-+	boolean			is_linked;
-+	boolean			pre_is_linked;
-+	boolean			first_connect;
-+	boolean			first_disconnect;
-+	boolean			bsta_state;
-+	u8			rssi_min;
-+	u8			rssi_min_macid;
-+	u8			pre_rssi_min;
-+	u8			rssi_max;
-+	u8			rssi_max_macid;
-+	u8			rssi_min_by_path;
-+	boolean			is_mp_chip;
-+	boolean			is_one_entry_only;
-+	u32			one_entry_macid;
-+	u32			one_entry_tp;
-+	u32			pre_one_entry_tp;
-+	u8			pre_number_linked_client;
-+	u8			number_linked_client;
-+	u8			pre_number_active_client;
-+	u8			number_active_client;
-+	boolean			is_disable_phy_api;
-+	u8			rssi_a;
-+	u8			rssi_b;
-+	u8			rssi_c;
-+	u8			rssi_d;
-+	s8			rxsc_80;
-+	s8			rxsc_40;
-+	s8			rxsc_20;
-+	s8			rxsc_l;
-+	u64			rssi_trsw;
-+	u64			rssi_trsw_h;
-+	u64			rssi_trsw_l;
-+	u64			rssi_trsw_iso;
-+	u8			tx_ant_status; /*TX path enable*/
-+	u8			rx_ant_status; /*RX path enable*/
-+	#ifdef PHYDM_COMPILE_ABOVE_4SS
-+	enum bb_path		tx_4ss_status; /*@Use N-X for 4STS rate*/
-+	#endif
-+	#ifdef PHYDM_COMPILE_ABOVE_3SS
-+	enum bb_path		tx_3ss_status; /*@Use N-X for 3STS rate*/
-+	#endif
-+	#ifdef PHYDM_COMPILE_ABOVE_2SS
-+	enum bb_path		tx_2ss_status; /*@Use N-X for 2STS rate*/
-+	#endif
-+	enum bb_path		tx_1ss_status; /*@Use N-X for 1STS rate*/
-+	u8			cck_lna_idx;
-+	u8			cck_vga_idx;
-+	u8			curr_station_id;
-+	u8			ofdm_agc_idx[4];
-+	u8			rx_rate;
-+	u8			rate_ss;
-+	u8			tx_rate;
-+	u8			linked_interval;
-+	u8			pre_channel;
-+	u32			txagc_offset_value_a;
-+	boolean			is_txagc_offset_positive_a;
-+	u32			txagc_offset_value_b;
-+	boolean			is_txagc_offset_positive_b;
-+	u8			ap_total_num;
-+	boolean			flatness_type;
-+	/*@[traffic]*/
-+	u8			traffic_load;
-+	u8			pre_traffic_load;
-+	u32			tx_tp;			/*@Mbps*/
-+	u32			rx_tp;			/*@Mbps*/
-+	u32			total_tp;		/*@Mbps*/
-+	u8			txrx_state_all;		/*@0:tx, 1:rx, 2:bi-dir*/
-+	u64			cur_tx_ok_cnt;
-+	u64			cur_rx_ok_cnt;
-+	u64			last_tx_ok_cnt;
-+	u64			last_rx_ok_cnt;
-+	u16			consecutive_idlel_time;	/*@unit: second*/
-+	/*@---------------------------*/
-+	boolean			is_bb_swing_offset_positive_a;
-+	boolean			is_bb_swing_offset_positive_b;
-+
-+	/*@[DIG]*/
-+	boolean			MPDIG_2G;		/*off MPDIG*/
-+	u8			times_2g;		/*@for MP DIG*/
-+	u8			force_igi;		/*@for debug*/
-+
-+	/*@[TDMA-DIG]*/
-+	u8			tdma_dig_timer_ms;
-+	u8			tdma_dig_state_number;
-+	u8			tdma_dig_low_upper_bond;
-+	u8			force_tdma_low_igi;
-+	u8			force_tdma_high_igi;
-+	u8			fix_expire_to_zero;
-+	boolean			original_dig_restore;
-+	/*@---------------------------*/
-+
-+	/*@[AntDiv]*/
-+	u8			ant_div_type;
-+	u8			antdiv_rssi;
-+	u8			fat_comb_a;
-+	u8			fat_comb_b;
-+	u8			antdiv_intvl;
-+	u8			antdiv_delay;
-+	u8			ant_type;
-+	u8			ant_type2;
-+	u8			pre_ant_type;
-+	u8			pre_ant_type2;
-+	u8			antdiv_period;
-+	u8			evm_antdiv_period;
-+	u8			antdiv_select;
-+	u8			antdiv_train_num; /*@training time for each antenna in EVM method*/
-+	u8			stop_antdiv_rssi_th;
-+	u16			stop_antdiv_tp_diff_th;
-+	u16			stop_antdiv_tp_th;
-+	u8			antdiv_tp_period;
-+	u16			tp_active_th;
-+	u8			tp_active_occur;
-+	u8			path_select;
-+	u8			antdiv_evm_en;
-+	u8			bdc_holdstate;
-+	u8			antdiv_counter;
-+	/*@---------------------------*/
-+
-+	u8			ndpa_period;
-+	boolean			h2c_rarpt_connect;
-+	boolean			cck_agc_report_type; /*@1:4bit LNA, 0:3bit LNA */
-+	u8			print_agc;
-+	u8			la_mode;
-+	/*@---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/
-+	u8			current_rf_set_8821c;
-+	u8			default_rf_set_8821c;
-+	u8			current_ant_num_8821c;
-+	u8			default_ant_num_8821c;
-+	u8			rfe_type_expand;
-+	/*@-----------------------------------------------------------*/
-+	/*@---For Adaptivtiy---------------------------------------------*/
-+	s8			TH_L2H_default;
-+	s8			th_edcca_hl_diff_default;
-+	s8			th_l2h_ini;
-+	s8			th_edcca_hl_diff;
-+	boolean			carrier_sense_enable;
-+	/*@-----------------------------------------------------------*/
-+	u8			pre_dbg_priority;
-+	u8			nbi_set_result;
-+	u8			c2h_cmd_start;
-+	u8			fw_debug_trace[60];
-+	u8			pre_c2h_seq;
-+	boolean			fw_buff_is_enpty;
-+	u32			data_frame_num;
-+	/*@--- for spur detection ---------------------------------------*/
-+	boolean			en_reg_mntr_bb;
-+	boolean			en_reg_mntr_rf;
-+	boolean			en_reg_mntr_mac;
-+	boolean			en_reg_mntr_byte;
-+	/*@--------------------------------------------------------------*/
-+#if (RTL8814B_SUPPORT || RTL8812F_SUPPORT || RTL8198F_SUPPORT)
-+	u8			dsde_sel;
-+	u8			nbi_path_sel;
-+	u8			csi_wgt;
-+#endif
-+#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT)
-+	u8			csi_wgt_th_db[5]; /*@wgt 4,3,2,1,0 */
-+						  /*    ^ ^ ^ ^ ^  */
-+#endif
-+	/*@------------------------------------------*/
-+
-+	/*@--- for noise detection ---------------------------------------*/
-+	boolean			is_noisy_state;
-+	boolean			noisy_decision; /*@b_noisy*/
-+	boolean			pre_b_noisy;
-+	u32			noisy_decision_smooth;
-+	/*@-----------------------------------------------------------*/
-+
-+	/*@--- for MCC ant weighting ------------------------------------*/
-+	boolean			is_stop_dym_ant_weighting;
-+	/*@-----------------------------------------------------------*/
-+
-+	boolean			is_disable_dym_ecs;
-+	boolean			is_disable_dym_ant_weighting;
-+	struct cmn_sta_info	*phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
-+	u8			phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/
-+
-+#if (RATE_ADAPTIVE_SUPPORT)
-+	u16			currmin_rpt_time;
-+	struct _phydm_txstatistic_ hw_stats;
-+	struct _odm_ra_info_	ra_info[ODM_ASSOCIATE_ENTRY_NUM];
-+/*Use mac_id as array index. STA mac_id=0*/
-+/*VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/
-+#endif
-+	/*@2012/02/14 MH Add to share 88E ra with other SW team*/
-+	/*We need to colelct all support abilit to a proper area.*/
-+	boolean			ra_support88e;
-+	boolean			*is_driver_stopped;
-+	boolean			*is_driver_is_going_to_pnp_set_power_sleep;
-+	boolean			*pinit_adpt_in_progress;
-+	boolean			is_user_assign_level;
-+	u8			RSSI_BT;		/*@come from BT*/
-+
-+	/*@---PSD Relative ---------------------------------------------*/
-+	boolean			is_psd_in_process;
-+	boolean			is_psd_active;
-+	/*@-----------------------------------------------------------*/
-+
-+	boolean			bsomlenabled;	/* @D-SoML control */
-+	u8			no_ndp_cnts;
-+	u16			ndp_cnt_pre;
-+	boolean			is_beamformed;
-+	u8			linked_bf_support;
-+	boolean			bhtstfdisabled;	/* @dynamic HTSTF gain control*/
-+	u32			n_iqk_cnt;
-+	u32			n_iqk_ok_cnt;
-+	u32			n_iqk_fail_cnt;
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	boolean			config_bbrf;
-+#endif
-+	boolean			is_disable_power_training;
-+	boolean			is_bt_continuous_turn;
-+	u8			enhance_pwr_th[3];
-+	u8			set_pwr_th[3];
-+	/*@----------Dyn Tx Pwr ---------------------------------------*/
-+#ifdef BB_RAM_SUPPORT
-+	struct phydm_bb_ram_ctrl p_bb_ram_ctrl;
-+#endif
-+	u8			dynamic_tx_high_power_lvl;
-+	void	(*fill_desc_dyntxpwr)(void *dm, u8 *desc, u8 dyn_tx_power);
-+	u8			last_dtp_lvl;
-+	u8			min_power_index;
-+	u32			tx_agc_ofdm_18_6;
-+	/*-------------------------------------------------------------*/
-+	u8			rx_pkt_type;
-+
-+#ifdef CONFIG_PHYDM_DFS_MASTER
-+	u8			dfs_region_domain;
-+	u8			*dfs_master_enabled;
-+	/*@---phydm_radar_detect_with_dbg_parm start --------------------*/
-+	u8			radar_detect_dbg_parm_en;
-+	u32			radar_detect_reg_918;
-+	u32			radar_detect_reg_91c;
-+	u32			radar_detect_reg_920;
-+	u32			radar_detect_reg_924;
-+
-+	u32			radar_detect_reg_a40;
-+	u32			radar_detect_reg_a44;
-+	u32			radar_detect_reg_a48;
-+	u32			radar_detect_reg_a4c;
-+	u32			radar_detect_reg_a50;
-+	u32			radar_detect_reg_a54;
-+
-+	u32			radar_detect_reg_f54;
-+	u32			radar_detect_reg_f58;
-+	u32			radar_detect_reg_f5c;
-+	u32			radar_detect_reg_f70;
-+	u32			radar_detect_reg_f74;
-+	/*@---For zero-wait DFS---------------------------------------*/
-+	boolean			seg1_dfs_flag;
-+	/*@-----------------------------------------------------------*/
-+/*@-----------------------------------------------------------*/
-+#endif
-+
-+/*@=== RTL8721D ===*/
-+#if (RTL8721D_SUPPORT)
-+	boolean			cbw20_adc80;
-+	boolean			invalid_mode;
-+	u8			power_voltage;
-+	u8			cca_cbw20_lev;
-+	u8			cca_cbw40_lev;
-+	u8			antdiv_gpio;
-+	u8			peak_detect_mode;
-+#endif
-+
-+/*@=== PHYDM Timer ========================================== (start)*/
-+
-+	struct phydm_timer_list	mpt_dig_timer;
-+	struct phydm_timer_list	fast_ant_training_timer;
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	struct phydm_timer_list	evm_fast_ant_training_timer;
-+#endif
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	struct phydm_timer_list tdma_dig_timer;
-+#endif
-+	struct phydm_timer_list	sbdcnt_timer;
-+
-+/*@=== PHYDM Workitem ======================================= (start)*/
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#if USE_WORKITEM
-+	RT_WORK_ITEM		fast_ant_training_workitem;
-+	RT_WORK_ITEM		ra_rpt_workitem;
-+	RT_WORK_ITEM		sbdcnt_workitem;
-+	RT_WORK_ITEM		phydm_evm_antdiv_workitem;
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	RT_WORK_ITEM		phydm_tdma_dig_workitem;
-+#endif
-+#endif
-+#endif
-+
-+/*@=== PHYDM Structure ======================================== (start)*/
-+	struct	phydm_func_poiner	phydm_func_handler;
-+	struct	phydm_iot_center	iot_table;
-+
-+#ifdef ODM_CONFIG_BT_COEXIST
-+	struct	phydm_bt_info		bt_info_table;
-+#endif
-+
-+	struct	pkt_process_info	pkt_proc_struct;
-+	struct phydm_adaptivity_struct	adaptivity;
-+#ifdef CONFIG_PHYDM_DFS_MASTER
-+	struct _DFS_STATISTICS		dfs;
-+#endif
-+	struct odm_noise_monitor	noise_level;
-+	struct odm_phy_dbg_info		phy_dbg_info;
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	struct odm_phy_dbg_info		phy_dbg_info_win_bkp;
-+#endif
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	struct phydm_bf_rate_info_jgr3 bf_rate_info_jgr3;
-+#endif
-+
-+#ifdef CONFIG_ADAPTIVE_SOML
-+	struct adaptive_soml		dm_soml_table;
-+#endif
-+
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+	#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	struct _BF_DIV_COEX_		dm_bdc_table;
-+	#endif
-+
-+	#if (defined(CONFIG_HL_SMART_ANTENNA))
-+	struct smt_ant_honbo		dm_sat_table;
-+	#endif
-+#endif
-+
-+#if (defined(CONFIG_SMART_ANTENNA))
-+	struct smt_ant			smtant_table;
-+#endif
-+
-+	struct _hal_rf_			rf_table;	/*@for HALRF function*/
-+	struct dm_rf_calibration_struct	rf_calibrate_info;
-+	struct dm_iqk_info		IQK_info;
-+	struct dm_dpk_info		dpk_info;
-+	struct dm_dack_info		dack_info;
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	struct phydm_fat_struct		dm_fat_table;
-+	struct sw_antenna_switch	dm_swat_table;
-+#endif
-+	struct phydm_dig_struct		dm_dig_table;
-+
-+#ifdef PHYDM_SUPPORT_CCKPD
-+	struct phydm_cckpd_struct	dm_cckpd_table;
-+
-+	#ifdef PHYDM_DCC_ENHANCE
-+	struct phydm_dcc_struct		dm_dcc_info; /*dig cckpd coex*/
-+	#endif
-+#endif
-+
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+	struct phydm_lna_sat_t		dm_lna_sat_info;
-+#endif
-+
-+#ifdef CONFIG_MCC_DM
-+	struct _phydm_mcc_dm_ mcc_dm;
-+#endif
-+
-+#ifdef PHYDM_PRIMARY_CCA
-+	struct phydm_pricca_struct	dm_pri_cca;
-+#endif
-+
-+	struct ra_table			dm_ra_table;
-+	struct phydm_fa_struct		false_alm_cnt;
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	struct phydm_fa_acc_struct	false_alm_cnt_acc;
-+#ifdef IS_USE_NEW_TDMA
-+	struct phydm_fa_acc_struct	false_alm_cnt_acc_low;
-+#endif
-+#endif
-+	struct phydm_cfo_track_struct	dm_cfo_track;
-+	struct ccx_info			dm_ccx_info;
-+
-+	struct odm_power_trim_data	power_trim_data;
-+#if (RTL8822B_SUPPORT)
-+	struct drp_rtl8822b_struct	phydm_rtl8822b;
-+#endif
-+
-+#ifdef CONFIG_PSD_TOOL
-+	struct psd_info			dm_psd_table;
-+#endif
-+
-+#if (PHYDM_LA_MODE_SUPPORT)
-+	struct rt_adcsmp		adcsmp;
-+#endif
-+
-+#if (defined(CONFIG_PATH_DIVERSITY))
-+	struct _ODM_PATH_DIVERSITY_	dm_path_div;
-+#endif
-+
-+#if (defined(CONFIG_ANT_DETECTION))
-+	struct _ANT_DETECTED_INFO	ant_detected_info;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	struct _RT_BEAMFORMING_INFO 	beamforming_info;
-+#endif
-+#endif
-+#ifdef PHYDM_AUTO_DEGBUG
-+	struct	phydm_auto_dbg_struct	auto_dbg_table;
-+#endif
-+
-+	struct	phydm_pause_lv		pause_lv_table;
-+	struct	phydm_api_stuc		api_table;
-+#ifdef PHYDM_POWER_TRAINING_SUPPORT
-+	struct	phydm_pow_train_stuc	pow_train_table;
-+#endif
-+
-+#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
-+	struct phydm_pmac_tx dm_pmac_tx_table;
-+#endif
-+
-+#ifdef PHYDM_MP_SUPPORT
-+	struct phydm_mp dm_mp_table;
-+#endif
-+
-+#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
-+	struct phydm_cck_rx_pathdiv dm_cck_rx_pathdiv_table;
-+#endif
-+/*@==========================================================*/
-+
-+#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
-+	/*@-------------------phydm_phystatus report --------------------*/
-+	struct phydm_physts dm_physts_table;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+
-+#if (RT_PLATFORM != PLATFORM_LINUX)
-+} dm_struct;	/*@DM_Dynamic_Mechanism_Structure*/
-+#else
-+};
-+#endif
-+
-+#else	/*@for AP,CE Team*/
-+};
-+#endif
-+
-+enum phydm_adv_ota {
-+	PHYDM_PATHB_1RCCA		= BIT(0),
-+	PHYDM_HP_OTA_SETTING_A		= BIT(1),
-+	PHYDM_HP_OTA_SETTING_B		= BIT(2),
-+	PHYDM_ASUS_OTA_SETTING		= BIT(3),
-+	PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4),
-+	PHYDM_HP_OTA_SETTING_CCK_PATH	= BIT(5),
-+	PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6),
-+
-+};
-+
-+enum phydm_bb_op_mode {
-+	PHYDM_PERFORMANCE_MODE	= 0,		/*Service one device*/
-+	PHYDM_BALANCE_MODE	= 1,		/*@Service more than one device*/
-+};
-+
-+enum phydm_structure_type {
-+	PHYDM_FALSEALMCNT,
-+	PHYDM_CFOTRACK,
-+	PHYDM_ADAPTIVITY,
-+	PHYDM_DFS,
-+	PHYDM_ROMINFO,
-+
-+};
-+
-+enum odm_bb_config_type {
-+	CONFIG_BB_PHY_REG,
-+	CONFIG_BB_AGC_TAB,
-+	CONFIG_BB_AGC_TAB_2G,
-+	CONFIG_BB_AGC_TAB_5G,
-+	CONFIG_BB_PHY_REG_PG,
-+	CONFIG_BB_PHY_REG_MP,
-+	CONFIG_BB_AGC_TAB_DIFF,
-+	CONFIG_BB_RF_CAL_INIT,
-+};
-+
-+enum odm_rf_config_type {
-+	CONFIG_RF_RADIO,
-+	CONFIG_RF_TXPWR_LMT,
-+	CONFIG_RF_SYN_RADIO,
-+};
-+
-+enum odm_fw_config_type {
-+	CONFIG_FW_NIC,
-+	CONFIG_FW_NIC_2,
-+	CONFIG_FW_AP,
-+	CONFIG_FW_AP_2,
-+	CONFIG_FW_MP,
-+	CONFIG_FW_WOWLAN,
-+	CONFIG_FW_WOWLAN_2,
-+	CONFIG_FW_AP_WOWLAN,
-+	CONFIG_FW_BT,
-+};
-+
-+/*status code*/
-+#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
-+enum rt_status {
-+	RT_STATUS_SUCCESS,
-+	RT_STATUS_FAILURE,
-+	RT_STATUS_PENDING,
-+	RT_STATUS_RESOURCE,
-+	RT_STATUS_INVALID_CONTEXT,
-+	RT_STATUS_INVALID_PARAMETER,
-+	RT_STATUS_NOT_SUPPORT,
-+	RT_STATUS_OS_API_FAILED,
-+};
-+#endif	/*@end of enum rt_status definition*/
-+
-+void
-+phydm_watchdog_lps(struct dm_struct *dm);
-+
-+void
-+phydm_watchdog_lps_32k(struct dm_struct *dm);
-+
-+void
-+phydm_txcurrentcalibration(struct dm_struct *dm);
-+
-+void
-+phydm_dm_early_init(struct dm_struct *dm);
-+
-+enum phydm_init_result
-+odm_dm_init(struct dm_struct *dm);
-+
-+void
-+odm_dm_reset(struct dm_struct *dm);
-+
-+void
-+phydm_fwoffload_ability_init(struct dm_struct *dm,
-+			     enum phydm_offload_ability offload_ability);
-+
-+void
-+phydm_fwoffload_ability_clear(struct dm_struct *dm,
-+			      enum phydm_offload_ability offload_ability);
-+
-+void
-+phydm_supportability_en(void *dm_void, char input[][16], u32 *_used,
-+			char *output, u32 *_out_len);
-+
-+void
-+phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type);
-+
-+void
-+phydm_watchdog(struct dm_struct *dm);
-+
-+void
-+phydm_watchdog_mp(struct dm_struct *dm);
-+
-+void
-+phydm_pause_func_init(void *dm_void);
-+
-+u8
-+phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func,
-+		 enum phydm_pause_type pause_type,
-+		 enum phydm_pause_level pause_lv, u8 val_lehgth, u32 *val_buf);
-+
-+void
-+phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used,
-+			 char *output, u32 *_out_len);
-+
-+void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm,
-+				enum phydm_pause_type pause_type, u8 rssi);
-+
-+void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx,
-+			 boolean enable);
-+
-+void
-+odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value);
-+
-+void
-+odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, void *value);
-+
-+void
-+odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value);
-+
-+u32
-+phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type);
-+
-+void
-+odm_init_all_timers(struct dm_struct *dm);
-+
-+void
-+odm_cancel_all_timers(struct dm_struct *dm);
-+
-+void
-+odm_release_all_timers(struct dm_struct *dm);
-+
-+void *
-+phydm_get_structure(struct dm_struct *dm, u8 structure_type);
-+
-+void
-+phydm_dc_cancellation(struct dm_struct *dm);
-+
-+void
-+phydm_receiver_blocking(void *dm_void);
-+
-+void
-+phydm_dyn_bw_indication(void *dm_void);
-+
-+void
-+phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en);
-+
-+
-+#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
-+void
-+phydm_tx_collsion_th_init(void *dm_void);
-+
-+void
-+phydm_tx_collsion_th_set(void *dm_void, u8 val_r2t, u8 val_t2r);
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void
-+odm_init_all_work_items(
-+	struct dm_struct	*dm
-+);
-+void
-+odm_free_all_work_items(
-+	struct dm_struct	*dm
-+);
-+#endif	/*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+void
-+odm_dtc(struct dm_struct *dm);
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+void
-+odm_init_all_threads(
-+	struct dm_struct	*dm
-+);
-+
-+void
-+odm_stop_all_threads(
-+	struct dm_struct	*dm
-+);
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm.mk b/drivers/staging/rtl8723cs/hal/phydm/phydm.mk
-new file mode 100644
-index 000000000000..dcf919909781
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm.mk
-@@ -0,0 +1,248 @@
-+EXTRA_CFLAGS += -I$(srctree)/$(src)/hal/phydm
-+
-+_PHYDM_FILES := hal/phydm/phydm_debug.o	\
-+								hal/phydm/phydm_antdiv.o\
-+								hal/phydm/phydm_soml.o\
-+								hal/phydm/phydm_smt_ant.o\
-+								hal/phydm/phydm_antdect.o\
-+								hal/phydm/phydm_interface.o\
-+								hal/phydm/phydm_phystatus.o\
-+								hal/phydm/phydm_hwconfig.o\
-+								hal/phydm/phydm.o\
-+								hal/phydm/phydm_dig.o\
-+								hal/phydm/phydm_pathdiv.o\
-+								hal/phydm/phydm_rainfo.o\
-+								hal/phydm/phydm_dynamictxpower.o\
-+								hal/phydm/phydm_adaptivity.o\
-+								hal/phydm/phydm_cfotracking.o\
-+								hal/phydm/phydm_noisemonitor.o\
-+								hal/phydm/phydm_beamforming.o\
-+								hal/phydm/phydm_direct_bf.o\
-+								hal/phydm/phydm_dfs.o\
-+								hal/phydm/txbf/halcomtxbf.o\
-+								hal/phydm/txbf/haltxbfinterface.o\
-+								hal/phydm/txbf/phydm_hal_txbf_api.o\
-+								hal/phydm/phydm_adc_sampling.o\
-+								hal/phydm/phydm_ccx.o\
-+								hal/phydm/phydm_psd.o\
-+								hal/phydm/phydm_primary_cca.o\
-+								hal/phydm/phydm_cck_pd.o\
-+								hal/phydm/phydm_rssi_monitor.o\
-+								hal/phydm/phydm_auto_dbg.o\
-+								hal/phydm/phydm_math_lib.o\
-+								hal/phydm/phydm_api.o\
-+								hal/phydm/phydm_pow_train.o\
-+								hal/phydm/phydm_lna_sat.o\
-+								hal/phydm/phydm_pmac_tx_setting.o\
-+								hal/phydm/phydm_mp.o\
-+								hal/phydm/phydm_cck_rx_pathdiv.o\
-+								hal/phydm/halrf/halrf.o\
-+								hal/phydm/halrf/halrf_debug.o\
-+								hal/phydm/halrf/halphyrf_ce.o\
-+								hal/phydm/halrf/halrf_powertracking_ce.o\
-+								hal/phydm/halrf/halrf_powertracking.o\
-+								hal/phydm/halrf/halrf_kfree.o\
-+								hal/phydm/halrf/halrf_psd.o
-+		
-+ifeq ($(CONFIG_RTL8188E), y)
-+RTL871X = rtl8188e
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\
-+								hal/phydm/$(RTL871X)/hal8188erateadaptive.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8188e.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8192E), y)
-+RTL871X = rtl8192e
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8192e.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8812A), y)
-+RTL871X = rtl8812a
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8812a.o\
-+								hal/phydm/txbf/haltxbfjaguar.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8821A), y)
-+RTL871X = rtl8821a
-+_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\
-+								hal/phydm/rtl8821a/halhwimg8821a_bb.o\
-+								hal/phydm/rtl8821a/halhwimg8821a_rf.o\
-+								hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\
-+								hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\
-+								hal/phydm/rtl8821a/phydm_regconfig8821a.o\
-+								hal/phydm/rtl8821a/phydm_rtl8821a.o\
-+								hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\
-+								hal/phydm/txbf/haltxbfjaguar.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8723B), y)
-+RTL871X = rtl8723b
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\
-+								hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8723b.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8814A), y)
-+RTL871X = rtl8814a
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\
-+								hal/phydm/halrf/$(RTL871X)/halhwimg8814a_rf.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8814a.o\
-+								hal/phydm/txbf/haltxbf8814a.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8723C), y)
-+RTL871X = rtl8703b
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8703b.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8703b.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8723D), y)
-+RTL871X = rtl8723d
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8723d.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8723d.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8710B), y)
-+RTL871X = rtl8710b
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8710b.o\
-+								hal/phydm/halrf/$(RTL871X)/halhwimg8710b_rf.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8710b.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8188F), y)
-+RTL871X = rtl8188f
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \
-+								hal/phydm/$(RTL871X)/phydm_rtl8188f.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8822B), y)
-+RTL871X = rtl8822b
-+_PHYDM_FILES +=	hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \
-+								hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \
-+								hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \
-+								hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \
-+								hal/phydm/halrf/$(RTL871X)/halhwimg8822b_rf.o \
-+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \
-+								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \
-+								hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \
-+								hal/phydm/$(RTL871X)/phydm_rtl8822b.o
-+
-+_PHYDM_FILES +=	hal/phydm/txbf/haltxbf8822b.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8821C), y)
-+RTL871X = rtl8821c
-+_PHYDM_FILES +=	hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
-+								hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \
-+								hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \
-+								hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8821c.o\
-+								hal/phydm/halrf/$(RTL871X)/halhwimg8821c_rf.o \
-+								hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
-+endif
-+ifeq ($(CONFIG_RTL8192F), y)
-+RTL871X = rtl8192f
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\
-+								hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8192f.o\
-+								hal/phydm/halrf/$(RTL871X)/halhwimg8192f_rf.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8192f.o	
-+endif
-+
-+ifeq ($(CONFIG_RTL8198F), y)
-+RTL871X = rtl8198f
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\
-+								hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8198f.o\
-+								hal/phydm/halrf/$(RTL871X)/halhwimg8198f_rf.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8822C), y)
-+RTL871X = rtl8822c
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822c_bb.o\
-+								hal/phydm/$(RTL871X)/phydm_hal_api8822c.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8822c.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8822c.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8822c.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822c.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_tssi_8822c.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_dpk_8822c.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_txgapk_8822c.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822c.o\
-+								hal/phydm/halrf/$(RTL871X)/halhwimg8822c_rf.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8814B), y)
-+RTL871X = rtl8814b
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814b_bb.o\
-+								hal/phydm/$(RTL871X)/phydm_hal_api8814b.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8814b.o\
-+								hal/phydm/$(RTL871X)/phydm_extraagc8814b.o\
-+								hal/phydm/halrf/$(RTL871X)/halhwimg8814b_rf.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8814b.o \
-+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814b.o \
-+								hal/phydm/halrf/$(RTL871X)/halrf_dpk_8814b.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8814b.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_txgapk_8814b.o
-+endif
-+ifeq ($(CONFIG_RTL8723F), y)
-+RTL871X = rtl8723f
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723f_bb.o\
-+								hal/phydm/$(RTL871X)/phydm_hal_api8723f.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8723f.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8723f.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8723f.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8723f.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_tssi_8723f.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_dpk_8723f.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8723f.o\
-+								hal/phydm/halrf/$(RTL871X)/halhwimg8723f_rf.o
-+endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_adaptivity.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_adaptivity.c
-new file mode 100644
-index 000000000000..4cf4ee0bffb0
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_adaptivity.c
-@@ -0,0 +1,845 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ************************************************************/
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	#if WPP_SOFTWARE_TRACE
-+		#include "PhyDM_Adaptivity.tmh"
-+	#endif
-+#endif
-+#ifdef PHYDM_SUPPORT_ADAPTIVITY
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+boolean
-+phydm_check_channel_plan(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
-+	void *adapter = dm->adapter;
-+	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
-+
-+	if (mgnt_info->RegEnableAdaptivity != 2)
-+		return false;
-+
-+	if (!dm->carrier_sense_enable) { /*@check domain Code for adaptivity or CarrierSense*/
-+		if ((*dm->band_type == ODM_BAND_5G) &&
-+		    !(adapt->regulation_5g == REGULATION_ETSI || adapt->regulation_5g == REGULATION_WW)) {
-+			PHYDM_DBG(dm, DBG_ADPTVTY,
-+				  "adaptivity skip 5G domain code : %d\n",
-+				  adapt->regulation_5g);
-+			return true;
-+		} else if ((*dm->band_type == ODM_BAND_2_4G) &&
-+			   !(adapt->regulation_2g == REGULATION_ETSI || adapt->regulation_2g == REGULATION_WW)) {
-+			PHYDM_DBG(dm, DBG_ADPTVTY,
-+				  "adaptivity skip 2.4G domain code : %d\n",
-+				  adapt->regulation_2g);
-+			return true;
-+		} else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {
-+			PHYDM_DBG(dm, DBG_ADPTVTY,
-+				  "adaptivity neither 2G nor 5G band, return\n");
-+			return true;
-+		}
-+	} else {
-+		if ((*dm->band_type == ODM_BAND_5G) &&
-+		    !(adapt->regulation_5g == REGULATION_MKK || adapt->regulation_5g == REGULATION_WW)) {
-+			PHYDM_DBG(dm, DBG_ADPTVTY,
-+				  "CarrierSense skip 5G domain code : %d\n",
-+				  adapt->regulation_5g);
-+			return true;
-+		} else if ((*dm->band_type == ODM_BAND_2_4G) &&
-+			   !(adapt->regulation_2g == REGULATION_MKK || adapt->regulation_2g == REGULATION_WW)) {
-+			PHYDM_DBG(dm, DBG_ADPTVTY,
-+				  "CarrierSense skip 2.4G domain code : %d\n",
-+				  adapt->regulation_2g);
-+			return true;
-+		} else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {
-+			PHYDM_DBG(dm, DBG_ADPTVTY,
-+				  "CarrierSense neither 2G nor 5G band, return\n");
-+			return true;
-+		}
-+	}
-+
-+	return false;
-+}
-+
-+boolean
-+phydm_soft_ap_special_set(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
-+	boolean disable_ap_adapt_setting = false;
-+
-+	if (dm->soft_ap_mode != NULL) {
-+		if (*dm->soft_ap_mode != 0 &&
-+		    (dm->soft_ap_special_setting & BIT(0)))
-+			disable_ap_adapt_setting = true;
-+		else
-+			disable_ap_adapt_setting = false;
-+		PHYDM_DBG(dm, DBG_ADPTVTY,
-+			  "soft_ap_setting = %x, soft_ap = %d, dis_ap_adapt = %d\n",
-+			  dm->soft_ap_special_setting, *dm->soft_ap_mode,
-+			  disable_ap_adapt_setting);
-+	}
-+
-+	return disable_ap_adapt_setting;
-+}
-+
-+boolean
-+phydm_ap_num_check(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
-+	boolean dis_adapt = false;
-+
-+	if  (dm->ap_total_num > adapt->ap_num_th)
-+		dis_adapt = true;
-+	else
-+		dis_adapt = false;
-+
-+	PHYDM_DBG(dm, DBG_ADPTVTY, "AP total num = %d, AP num threshold = %d\n",
-+		  dm->ap_total_num, adapt->ap_num_th);
-+	return dis_adapt;
-+}
-+
-+void phydm_check_adaptivity(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
-+	boolean disable_adapt = false;
-+
-+	if (!adapt->mode_cvrt_en)
-+		return;
-+
-+	if (phydm_check_channel_plan(dm) || phydm_ap_num_check(dm) ||
-+	    phydm_soft_ap_special_set(dm))
-+		disable_adapt = true;
-+
-+	if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE && disable_adapt)
-+		*dm->edcca_mode = PHYDM_EDCCA_NORMAL_MODE;
-+	else if (*dm->edcca_mode == PHYDM_EDCCA_NORMAL_MODE && !disable_adapt)
-+		*dm->edcca_mode = PHYDM_EDCCA_ADAPT_MODE;
-+}
-+
-+void phydm_set_l2h_th_ini_win(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	 /*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		if (dm->support_ic_type & ODM_RTL8822C)
-+			dm->th_l2h_ini = 45;
-+		else if (dm->support_ic_type & ODM_RTL8814B)
-+			dm->th_l2h_ini = 49;
-+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+	 /*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/
-+		if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812)) {
-+			dm->th_l2h_ini = -17;
-+		} else {
-+			if (*dm->band_type == ODM_BAND_5G)
-+				dm->th_l2h_ini = -14;
-+			else if (*dm->band_type == ODM_BAND_2_4G)
-+				dm->th_l2h_ini = -9;
-+		}
-+	} else { /*ODM_IC_11N_SERIES*/
-+		dm->th_l2h_ini = -9;
-+	}
-+}
-+#endif
-+
-+void phydm_dig_up_bound_lmt_en(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
-+
-+	if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE ||
-+	    !dm->is_linked) {
-+		adapt->igi_up_bound_lmt_cnt = 0;
-+		adapt->igi_lmt_en = false;
-+		return;
-+	}
-+
-+	if (dm->total_tp > 1) {
-+		adapt->igi_lmt_en = true;
-+		adapt->igi_up_bound_lmt_cnt = adapt->igi_up_bound_lmt_val;
-+		PHYDM_DBG(dm, DBG_ADPTVTY,
-+			  "TP >1, Start limit IGI upper bound\n");
-+	} else {
-+		if (adapt->igi_up_bound_lmt_cnt == 0)
-+			adapt->igi_lmt_en = false;
-+		else
-+			adapt->igi_up_bound_lmt_cnt--;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ADPTVTY, "IGI_lmt_cnt = %d\n",
-+		  adapt->igi_up_bound_lmt_cnt);
-+}
-+
-+void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		odm_set_bb_reg(dm, R_0x84c, MASKBYTE2, (u8)L2H + 0x80);
-+		odm_set_bb_reg(dm, R_0x84c, MASKBYTE3, (u8)H2L + 0x80);
-+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		odm_set_bb_reg(dm, R_0xc4c, MASKBYTE0, (u8)L2H);
-+		odm_set_bb_reg(dm, R_0xc4c, MASKBYTE2, (u8)H2L);
-+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		odm_set_bb_reg(dm, R_0x8a4, MASKBYTE0, (u8)L2H);
-+		odm_set_bb_reg(dm, R_0x8a4, MASKBYTE1, (u8)H2L);
-+	}
-+}
-+
-+void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (state == PHYDM_IGNORE_EDCCA) {
-+		/*@ignore EDCCA*/
-+		odm_set_mac_reg(dm, R_0x520, BIT(15), 1);
-+		/*@enable EDCCA count down*/
-+		odm_set_mac_reg(dm, R_0x524, BIT(11), 0);
-+	} else { /*@don't set MAC ignore EDCCA signal*/
-+		/*@don't ignore EDCCA*/
-+		odm_set_mac_reg(dm, R_0x520, BIT(15), 0);
-+		/*@disable EDCCA count down*/
-+		odm_set_mac_reg(dm, R_0x524, BIT(11), 1);
-+	}
-+	PHYDM_DBG(dm, DBG_ADPTVTY, "EDCCA enable state = %d\n", state);
-+}
-+
-+void phydm_search_pwdb_lower_bound(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
-+	u32 value32 = 0, reg_value32 = 0;
-+	u8 cnt = 0, try_count = 0;
-+	u8 tx_edcca1 = 0;
-+	boolean is_adjust = true;
-+	s8 th_l2h, th_h2l, igi_target_dc = 0x32;
-+	s8 diff = 0;
-+	s8 IGI = adapt->igi_base + 30 + dm->th_l2h_ini - dm->th_edcca_hl_diff;
-+
-+	halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
-+	diff = igi_target_dc - IGI;
-+	th_l2h = dm->th_l2h_ini + diff;
-+	if (th_l2h > 10)
-+		th_l2h = 10;
-+
-+	th_h2l = th_l2h - dm->th_edcca_hl_diff;
-+	phydm_set_edcca_threshold(dm, th_h2l, th_l2h);
-+	ODM_delay_ms(30);
-+
-+	while (is_adjust) {
-+		/*@check CCA status*/
-+		/*set debug port to 0x0*/
-+		if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {
-+			reg_value32 = phydm_get_bb_dbg_port_val(dm);
-+
-+			while (reg_value32 & BIT(3) && try_count < 3) {
-+				ODM_delay_ms(3);
-+				try_count = try_count + 1;
-+				reg_value32 = phydm_get_bb_dbg_port_val(dm);
-+			}
-+			phydm_release_bb_dbg_port(dm);
-+			try_count = 0;
-+		}
-+
-+		/*@count EDCCA signal = 1 times*/
-+		for (cnt = 0; cnt < 20; cnt++) {
-+			if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1,
-+						  adapt->adaptivity_dbg_port)) {
-+				value32 = phydm_get_bb_dbg_port_val(dm);
-+				phydm_release_bb_dbg_port(dm);
-+			}
-+
-+			if (value32 & BIT(30) && dm->support_ic_type &
-+						 (ODM_RTL8723B | ODM_RTL8188E))
-+				tx_edcca1 = tx_edcca1 + 1;
-+			else if (value32 & BIT(29))
-+				tx_edcca1 = tx_edcca1 + 1;
-+		}
-+
-+		if (tx_edcca1 > 1) {
-+			IGI = IGI - 1;
-+			th_l2h = th_l2h + 1;
-+			if (th_l2h > 10)
-+				th_l2h = 10;
-+
-+			th_h2l = th_l2h - dm->th_edcca_hl_diff;
-+			phydm_set_edcca_threshold(dm, th_h2l, th_l2h);
-+			tx_edcca1 = 0;
-+			if (th_l2h == 10)
-+				is_adjust = false;
-+
-+		} else {
-+			is_adjust = false;
-+		}
-+	}
-+
-+	adapt->adapt_igi_up = IGI - ADAPT_DC_BACKOFF;
-+	adapt->h2l_lb = th_h2l + ADAPT_DC_BACKOFF;
-+	adapt->l2h_lb = th_l2h + ADAPT_DC_BACKOFF;
-+
-+	halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
-+	phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/
-+}
-+
-+boolean phydm_re_search_condition(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
-+	u8 adaptivity_igi_upper = adaptivity->adapt_igi_up + ADAPT_DC_BACKOFF;
-+
-+	if (adaptivity_igi_upper <= 0x26)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+void phydm_set_l2h_th_ini(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	 /*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		if (dm->support_ic_type & ODM_RTL8822C)
-+			dm->th_l2h_ini = 45;
-+		else if (dm->support_ic_type & ODM_RTL8814B)
-+			dm->th_l2h_ini = 49;
-+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+	 /*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/
-+		if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812))
-+			dm->th_l2h_ini = -17;
-+		else
-+			dm->th_l2h_ini = -14;
-+	} else { /*ODM_IC_11N_SERIES*/
-+		if (dm->support_ic_type & ODM_RTL8721D)
-+			dm->th_l2h_ini = -14;
-+		else
-+			dm->th_l2h_ini = -11;
-+	}
-+}
-+
-+void phydm_set_l2h_th_ini_carrier_sense(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		dm->th_l2h_ini = 60; /*@ -50dBm*/
-+	else
-+		dm->th_l2h_ini = 10; /*@ -50dBm*/
-+}
-+
-+void phydm_set_forgetting_factor(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
-+		return;
-+
-+	if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A |
-+				  ODM_RTL8195B))
-+		odm_set_bb_reg(dm, R_0x8a0, BIT(1) | BIT(0), 0);
-+}
-+
-+void phydm_edcca_decision_opt(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
-+		return;
-+
-+	if (dm->support_ic_type & ODM_RTL8822B)
-+		odm_set_bb_reg(dm, R_0x8dc, BIT(5), 0x1);
-+	else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
-+		odm_set_bb_reg(dm, R_0xce8, BIT(13), 0x1);
-+	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		odm_set_bb_reg(dm, R_0x844, BIT(30) | BIT(29), 0x0);
-+}
-+
-+void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
-+			    char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	char help[] = "-h";
-+	u32 dm_value[10] = {0};
-+	u8 i = 0, input_idx = 0;
-+	u32 reg_value32 = 0;
-+	s8 h2l_diff = 0;
-+
-+	for (i = 0; i < 5; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
-+		input_idx++;
-+	}
-+	if (strcmp(input[1], help) == 0) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Show adaptivity message: {0}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Enter debug mode: {1} {th_l2h_ini} {th_edcca_hl_diff}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Leave debug mode: {2}\n");
-+		goto out;
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	if (dm_value[0] == PHYDM_ADAPT_DEBUG) {
-+		adaptivity->debug_mode = true;
-+		if (dm_value[1] != 0)
-+			dm->th_l2h_ini = (s8)dm_value[1];
-+		if (dm_value[2] != 0)
-+			dm->th_edcca_hl_diff = (s8)dm_value[2];
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
-+			 dm->th_l2h_ini, dm->th_edcca_hl_diff);
-+	} else if (dm_value[0] == PHYDM_ADAPT_RESUME) {
-+		adaptivity->debug_mode = false;
-+		dm->th_l2h_ini = adaptivity->th_l2h_ini_backup;
-+		dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
-+	} else if (dm_value[0] == PHYDM_ADAPT_MSG) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "debug_mode = %s, th_l2h_ini = %d\n",
-+			 (adaptivity->debug_mode ? "TRUE" : "FALSE"),
-+			 dm->th_l2h_ini);
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+			reg_value32 = odm_get_bb_reg(dm, R_0x84c, MASKDWORD);
-+			h2l_diff = (s8)((0x00ff0000 & reg_value32) >> 16) -
-+				   (s8)((0xff000000 & reg_value32) >> 24);
-+		} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+			reg_value32 = odm_get_bb_reg(dm, R_0xc4c, MASKDWORD);
-+			h2l_diff = (s8)(0x000000ff & reg_value32) -
-+				   (s8)((0x00ff0000 & reg_value32) >> 16);
-+		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+			reg_value32 = odm_get_bb_reg(dm, R_0x8a4, MASKDWORD);
-+			h2l_diff = (s8)(0x000000ff & reg_value32) -
-+				   (s8)((0x0000ff00 & reg_value32) >> 8);
-+		}
-+
-+		if (h2l_diff == 7)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "adaptivity enable\n");
-+		else
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "adaptivity disable\n");
-+	}
-+
-+out:
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (val_len != 2) {
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "[Error][adaptivity]Need val_len = 2\n");
-+		return;
-+	}
-+	phydm_set_edcca_threshold(dm, (s8)val_buf[1], (s8)val_buf[0]);
-+}
-+
-+boolean phydm_edcca_abort(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter = dm->adapter;
-+	u32 is_fw_in_psmode = false;
-+#endif
-+
-+	if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) {
-+		PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity disable\n");
-+		return true;
-+	}
-+
-+	if (dm->pause_ability & ODM_BB_ADAPTIVITY) {
-+		PHYDM_DBG(dm, DBG_ADPTVTY, "Return: Pause ADPTVTY in LV=%d\n",
-+			  dm->pause_lv_table.lv_adapt);
-+		return true;
-+	}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	((PADAPTER)adapter)->HalFunc.GetHwRegHandler(adapter,
-+						      HW_VAR_FW_PSMODE_STATUS,
-+						      (u8 *)(&is_fw_in_psmode));
-+
-+	/*@Disable EDCCA while under LPS mode, added by Roger, 2012.09.14.*/
-+	if (is_fw_in_psmode)
-+		return true;
-+#endif
-+
-+	return false;
-+}
-+
-+void phydm_edcca_thre_calc_jgr3(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
-+	u8 igi = dig_t->cur_ig_value;
-+	s8 th_l2h = 0, th_h2l = 0;
-+
-+	if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
-+		/*prevent pwdB clipping and result in Miss Detection*/
-+		adapt->l2h_dyn_min = (u8)(dm->th_l2h_ini - ADC_BACKOFF);
-+
-+		if (igi < adapt->l2h_dyn_min)
-+			th_l2h = igi + ADC_BACKOFF;
-+		else
-+			th_l2h = dm->th_l2h_ini;
-+
-+		th_h2l = th_l2h - dm->th_edcca_hl_diff;
-+	} else {
-+		th_l2h = MAX_2(igi + TH_L2H_DIFF_IGI, EDCCA_TH_L2H_LB);
-+		th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
-+	}
-+	adapt->th_l2h = th_l2h;
-+	adapt->th_h2l = th_h2l;
-+
-+	phydm_set_edcca_threshold(dm, adapt->th_h2l, adapt->th_l2h);
-+}
-+
-+void phydm_edcca_thre_calc(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
-+	u8 igi = dig_t->cur_ig_value;
-+	s8 th_l2h = 0, th_h2l = 0;
-+	s8 diff = 0, igi_target = adapt->igi_base;
-+
-+	if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {
-+		/*@fix EDCCA hang issue*/
-+		if (dm->support_ic_type & ODM_RTL8812) {
-+			/*@ADC_mask disable*/
-+			odm_set_bb_reg(dm, R_0x800, BIT(10), 1);
-+			/*@ADC_mask enable*/
-+			odm_set_bb_reg(dm, R_0x800, BIT(10), 0);
-+		}
-+
-+		if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
-+			/*@Limit IGI upper bound for adaptivity*/
-+			phydm_dig_up_bound_lmt_en(dm);
-+			diff = igi_target - (s8)igi;
-+			th_l2h = dm->th_l2h_ini + diff;
-+			if (th_l2h > 10)
-+				th_l2h = 10;
-+
-+			th_h2l = th_l2h - dm->th_edcca_hl_diff;
-+		} else {
-+			th_l2h = 70 - igi;
-+			th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
-+		}
-+		/*replace lower bound to prevent EDCCA always equal 1*/
-+		if (th_h2l < adapt->h2l_lb)
-+			th_h2l = adapt->h2l_lb;
-+		if (th_l2h < adapt->l2h_lb)
-+			th_l2h = adapt->l2h_lb;
-+		PHYDM_DBG(dm, DBG_ADPTVTY,
-+			  "adapt_igi_up=0x%x, l2h_lb = %d dBm, h2l_lb = %d dBm\n",
-+			  adapt->adapt_igi_up,
-+			  IGI_2_DBM(adapt->l2h_lb + adapt->adapt_igi_up),
-+			  IGI_2_DBM(adapt->h2l_lb + adapt->adapt_igi_up));
-+	} else { /* < JGR2 & N*/
-+		if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
-+			/*need to consider PwdB upper bound for 8814 later IC*/
-+			adapt->l2h_dyn_min = (u8)(dm->th_l2h_ini + igi_target);
-+
-+			if (igi < adapt->l2h_dyn_min)
-+				th_l2h = igi;
-+			else
-+				th_l2h = adapt->l2h_dyn_min;
-+
-+			th_h2l = th_l2h - dm->th_edcca_hl_diff;
-+		} else {
-+			th_l2h = MAX_2(igi + TH_L2H_DIFF_IGI, EDCCA_TH_L2H_LB);
-+			th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
-+		}
-+	}
-+
-+	adapt->th_l2h = th_l2h;
-+	adapt->th_h2l = th_h2l;
-+
-+	phydm_set_edcca_threshold(dm, adapt->th_h2l, adapt->th_l2h);
-+}
-+#endif
-+
-+void phydm_set_edcca_threshold_api(void *dm_void)
-+{
-+#ifdef PHYDM_SUPPORT_ADAPTIVITY
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
-+
-+	if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
-+		return;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		phydm_edcca_thre_calc_jgr3(dm);
-+	else
-+		phydm_edcca_thre_calc(dm);
-+
-+	PHYDM_DBG(dm, DBG_ADPTVTY,
-+		  "API :IGI = 0x%x, th_l2h = %d, th_h2l = %d\n",
-+		  dm->dm_dig_table.cur_ig_value, adapt->th_l2h, adapt->th_h2l);
-+#endif
-+}
-+
-+void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
-+				u32 value)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
-+
-+	switch (cmn_info) {
-+	case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
-+		dm->carrier_sense_enable = (boolean)value;
-+		break;
-+	case PHYDM_ADAPINFO_TH_L2H_INI:
-+		dm->th_l2h_ini = (s8)value;
-+		break;
-+	case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
-+		dm->th_edcca_hl_diff = (s8)value;
-+		break;
-+	case PHYDM_ADAPINFO_AP_NUM_TH:
-+		adaptivity->ap_num_th = (u8)value;
-+		break;
-+	case PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND:
-+		adaptivity->switch_th_l2h_ini_in_band = (u8)value;
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info,
-+				  u32 value)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
-+
-+	/*This init variable may be changed in run time.*/
-+	switch (cmn_info) {
-+	case PHYDM_ADAPINFO_DOMAIN_CODE_2G:
-+		adapt->regulation_2g = (u8)value;
-+		break;
-+	case PHYDM_ADAPINFO_DOMAIN_CODE_5G:
-+		adapt->regulation_5g = (u8)value;
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+void phydm_adaptivity_init(void *dm_void)
-+{
-+#ifdef PHYDM_SUPPORT_ADAPTIVITY
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
-+
-+	/* @[Config Adaptivity]*/
-+	if (!dm->edcca_mode) {
-+		pr_debug("[%s] warning!\n", __func__);
-+		dm->edcca_mode = &dm->u8_dummy;
-+		dm->support_ability &= ~ODM_BB_ADAPTIVITY;
-+		return;
-+	}
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	if (!dm->carrier_sense_enable) {
-+		if (dm->th_l2h_ini == 0 &&
-+		    !adaptivity->switch_th_l2h_ini_in_band)
-+			phydm_set_l2h_th_ini(dm);
-+	} else {
-+		phydm_set_l2h_th_ini_carrier_sense(dm);
-+	}
-+
-+	if (dm->th_edcca_hl_diff == 0)
-+		dm->th_edcca_hl_diff = 7;
-+
-+	if (dm->wifi_test & RT_WIFI_LOGO)
-+		dm->support_ability &= ~ODM_BB_ADAPTIVITY;
-+
-+	if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE)
-+		adaptivity->mode_cvrt_en = true;
-+	else
-+		adaptivity->mode_cvrt_en = false;
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	if (!dm->carrier_sense_enable) {
-+		if (dm->th_l2h_ini == 0)
-+			phydm_set_l2h_th_ini(dm);
-+	} else {
-+		phydm_set_l2h_th_ini_carrier_sense(dm);
-+	}
-+
-+	if (dm->th_edcca_hl_diff == 0)
-+		dm->th_edcca_hl_diff = 7;
-+
-+	if (dm->wifi_test || *dm->mp_mode)
-+		dm->support_ability &= ~ODM_BB_ADAPTIVITY;
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	if (dm->carrier_sense_enable) {
-+		phydm_set_l2h_th_ini_carrier_sense(dm);
-+		dm->th_edcca_hl_diff = 7;
-+	} else {
-+		dm->th_l2h_ini = dm->TH_L2H_default; /*set by mib*/
-+		dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_default;
-+	}
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	if (!dm->carrier_sense_enable) {
-+		if (dm->th_l2h_ini == 0)
-+			phydm_set_l2h_th_ini(dm);
-+	} else {
-+		phydm_set_l2h_th_ini_carrier_sense(dm);
-+	}
-+
-+	if (dm->th_edcca_hl_diff == 0)
-+		dm->th_edcca_hl_diff = 7;
-+#endif
-+
-+	adaptivity->debug_mode = false;
-+	adaptivity->th_l2h_ini_backup = dm->th_l2h_ini;
-+	adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff;
-+	adaptivity->igi_base = 0x32;
-+	adaptivity->adapt_igi_up = 0;
-+	adaptivity->h2l_lb = 0;
-+	adaptivity->l2h_lb = 0;
-+	adaptivity->l2h_dyn_min = 0;
-+	adaptivity->th_l2h = 0x7f;
-+	adaptivity->th_h2l = 0x7f;
-+
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES)
-+		adaptivity->adaptivity_dbg_port = 0x208;
-+	else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-+		adaptivity->adaptivity_dbg_port = 0x209;
-+
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES &&
-+	    !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
-+		if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) {
-+			/*set to page B1*/
-+			odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x1);
-+			/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
-+			odm_set_bb_reg(dm, R_0xbc0, BIT(27) | BIT(26), 0x1);
-+			odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x0);
-+		} else {
-+			/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
-+			odm_set_bb_reg(dm, R_0xe24, BIT(21) | BIT(20), 0x1);
-+		}
-+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES &&
-+		   !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
-+		/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
-+		odm_set_bb_reg(dm, R_0x944, BIT(29) | BIT(28), 0x1);
-+	}
-+
-+	if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {
-+		phydm_search_pwdb_lower_bound(dm);
-+		if (phydm_re_search_condition(dm))
-+			phydm_search_pwdb_lower_bound(dm);
-+	} else {
-+		/*resume to no link state*/
-+		phydm_set_edcca_threshold(dm, 0x7f, 0x7f);
-+	}
-+
-+	/*@whether to ignore EDCCA*/
-+	phydm_mac_edcca_state(dm, PHYDM_DONT_IGNORE_EDCCA);
-+
-+	/*@forgetting factor setting*/
-+	phydm_set_forgetting_factor(dm);
-+
-+	/*@EDCCA behavior based on maximum or mean power*/
-+	phydm_edcca_decision_opt(dm);
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	adaptivity->igi_up_bound_lmt_val = 180;
-+#else
-+	adaptivity->igi_up_bound_lmt_val = 90;
-+#endif
-+	adaptivity->igi_up_bound_lmt_cnt = 0;
-+	adaptivity->igi_lmt_en = false;
-+#endif
-+}
-+
-+void phydm_adaptivity(void *dm_void)
-+{
-+#ifdef PHYDM_SUPPORT_ADAPTIVITY
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+	if (phydm_edcca_abort(dm))
-+		return;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	phydm_check_adaptivity(dm); /*@Check adaptivity enable*/
-+
-+	if (!dm->carrier_sense_enable &&
-+	    !adapt->debug_mode &&
-+	    adapt->switch_th_l2h_ini_in_band)
-+		phydm_set_l2h_th_ini_win(dm);
-+#endif
-+
-+	PHYDM_DBG(dm, DBG_ADPTVTY, "%s ====>\n", __func__);
-+	PHYDM_DBG(dm, DBG_ADPTVTY, "mode = %s, debug_mode = %d\n",
-+		  (*dm->edcca_mode ?
-+		  (dm->carrier_sense_enable ?
-+		  "CARRIER SENSE" :
-+		  "ADAPTIVITY") :
-+		  "NORMAL"),
-+		  adapt->debug_mode);
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		phydm_edcca_thre_calc_jgr3(dm);
-+	else
-+		phydm_edcca_thre_calc(dm);
-+
-+	if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE)
-+		PHYDM_DBG(dm, DBG_ADPTVTY,
-+			  "th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
-+			  dm->th_l2h_ini, dm->th_edcca_hl_diff);
-+	if (dm->support_ic_type & ODM_IC_PWDB_EDCCA)
-+		PHYDM_DBG(dm, DBG_ADPTVTY,
-+			  "IGI = 0x%x, th_l2h = %d dBm, th_h2l = %d dBm\n",
-+			  dig_t->cur_ig_value,
-+			  IGI_2_DBM(adapt->th_l2h + dig_t->cur_ig_value),
-+			  IGI_2_DBM(adapt->th_h2l + dig_t->cur_ig_value));
-+	else
-+		PHYDM_DBG(dm, DBG_ADPTVTY,
-+			  "IGI = 0x%x, th_l2h = %d dBm, th_h2l = %d dBm\n",
-+			  dig_t->cur_ig_value,
-+			  IGI_2_DBM(adapt->th_l2h),
-+			  IGI_2_DBM(adapt->th_h2l));
-+#endif
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_adaptivity.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_adaptivity.h
-new file mode 100644
-index 000000000000..f125fb1f79ca
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_adaptivity.h
-@@ -0,0 +1,126 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDMADAPTIVITY_H__
-+#define __PHYDMADAPTIVITY_H__
-+
-+#define ADAPTIVITY_VERSION "9.7.07" /*@20190321 changed by Kevin,
-+				     *add 8721D threshold l2h init
-+				     */
-+#define ADC_BACKOFF 12
-+#define EDCCA_TH_L2H_LB 48
-+#define TH_L2H_DIFF_IGI 8
-+#define EDCCA_HL_DIFF_NORMAL 8
-+#define IGI_2_DBM(igi) (igi - 110)
-+/*@ [PHYDM-337][Old IC] EDCCA TH = IGI + REG setting*/
-+#define ODM_IC_PWDB_EDCCA (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |\
-+			   ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8812)
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
-+	#define ADAPT_DC_BACKOFF 2
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	#define ADAPT_DC_BACKOFF 4
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	#define ADAPT_DC_BACKOFF 0
-+#endif
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+enum phydm_regulation_type {
-+	REGULATION_FCC		= 0,
-+	REGULATION_MKK		= 1,
-+	REGULATION_ETSI		= 2,
-+	REGULATION_WW		= 3,
-+	MAX_REGULATION_NUM	= 4
-+};
-+#endif
-+
-+enum phydm_edcca_mode {
-+	PHYDM_EDCCA_NORMAL_MODE = 0,
-+	PHYDM_EDCCA_ADAPT_MODE = 1
-+};
-+
-+enum phydm_adapinfo {
-+	PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
-+	PHYDM_ADAPINFO_TH_L2H_INI,
-+	PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
-+	PHYDM_ADAPINFO_AP_NUM_TH,
-+	PHYDM_ADAPINFO_DOMAIN_CODE_2G,
-+	PHYDM_ADAPINFO_DOMAIN_CODE_5G,
-+	PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND
-+};
-+
-+enum phydm_mac_edcca_type {
-+	PHYDM_IGNORE_EDCCA		= 0,
-+	PHYDM_DONT_IGNORE_EDCCA		= 1
-+};
-+
-+enum phydm_adaptivity_debug_mode {
-+	PHYDM_ADAPT_MSG			= 0,
-+	PHYDM_ADAPT_DEBUG		= 1,
-+	PHYDM_ADAPT_RESUME		= 2,
-+};
-+
-+struct phydm_adaptivity_struct {
-+	boolean			mode_cvrt_en;
-+	s8			th_l2h_ini_backup;
-+	s8			th_edcca_hl_diff_backup;
-+	s8			igi_base;
-+	s8			h2l_lb;
-+	s8			l2h_lb;
-+	u8			ap_num_th;
-+	u8			l2h_dyn_min;
-+	u32			adaptivity_dbg_port; /*N:0x208, AC:0x209*/
-+	u8			debug_mode;
-+	u16			igi_up_bound_lmt_cnt;	/*@When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/
-+	u16			igi_up_bound_lmt_val;	/*@max value of igi_up_bound_lmt_cnt*/
-+	boolean			igi_lmt_en;
-+	u8			adapt_igi_up;
-+	u32			rvrt_val[2]; /*@all rvrt_val for pause API must set to u32*/
-+	s8			th_l2h;
-+	s8			th_h2l;
-+	u8			regulation_2g;
-+	u8			regulation_5g;
-+	u8			switch_th_l2h_ini_in_band;
-+};
-+
-+#ifdef PHYDM_SUPPORT_ADAPTIVITY
-+void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
-+			    char *output, u32 *_out_len);
-+
-+void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len);
-+#endif
-+
-+void phydm_set_edcca_threshold_api(void *dm_void);
-+
-+void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
-+				u32 value);
-+
-+void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info,
-+				  u32 value);
-+
-+void phydm_adaptivity_init(void *dm_void);
-+
-+void phydm_adaptivity(void *dm_void);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_adc_sampling.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_adc_sampling.c
-new file mode 100644
-index 000000000000..bbbf9befb728
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_adc_sampling.c
-@@ -0,0 +1,1647 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#if (PHYDM_LA_MODE_SUPPORT)
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8192F_SUPPORT)
-+	#include "rtl8197f/Hal8197FPhyReg.h"
-+	#include "WlanHAL/HalMac88XX/halmac_reg2.h"
-+	#else
-+	#include "WlanHAL/HalHeader/HalComReg.h"
-+	#endif
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	#if WPP_SOFTWARE_TRACE
-+	#include "phydm_adc_sampling.tmh"
-+	#endif
-+#endif
-+
-+#if RTL8814B_SUPPORT
-+boolean phydm_la_finish_addr_recover_8814B(void *dm_void, u32 *finish_addr)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	boolean recover_success;
-+
-+	if (dm->support_ic_type != ODM_RTL8814B)
-+		return false;
-+
-+	if (smp->la_buff_mode == ADCSMP_BUFF_HALF) {
-+		if (*finish_addr < 0x4000) /*0~0x4000*/
-+			*finish_addr += 0x8000;
-+
-+		recover_success = true;
-+	} else {
-+		if (*finish_addr >= 0x4000 && *finish_addr < 0x8000)
-+			recover_success = true;
-+		else
-+			recover_success = false;
-+	}
-+	pr_debug("[8814B] recover_success=(%d)\n", recover_success);
-+
-+	return recover_success;
-+}
-+#endif
-+
-+#if RTL8198F_SUPPORT
-+void phydm_la_pre_run(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
-+	u8 i = 0;
-+	u8 tmp = 0;
-+	u8 target_polling_bit = BIT(1);
-+
-+	if (!(dm->support_ic_type & ODM_RTL8198F))
-+		return;
-+
-+	if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG)
-+		return;
-+
-+	/*pre run */
-+	/*force to bb trigger*/
-+	odm_set_mac_reg(dm, R_0x7c0, BIT(3), 0);
-+	/*dma_trig_and(AND1) output 1*/
-+	odm_set_bb_reg(dm, R_0x1ce4, 0xf0000000, 0x0);
-+	/*r_dma_trigger_AND1_inv = 1*/
-+	odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/
-+	/* polling bit for BB ADC mode */
-+	odm_set_mac_reg(dm, R_0x7c0, BIT(1), 1);
-+
-+	pr_debug("buf[end:start]=(0x%x~0x%x)\n", buf->end_pos, buf->start_pos);
-+
-+	do {
-+		tmp = odm_read_1byte(dm, R_0x7c0);
-+		if ((tmp & target_polling_bit) == false) {
-+			pr_debug("LA pre-run fail.\n");
-+			phydm_la_stop(dm);
-+			phydm_release_bb_dbg_port(dm);
-+		} else {
-+			ODM_delay_ms(100);
-+			pr_debug("LA pre-run while_cnt = %d.\n", i);
-+			i++;
-+		}
-+	} while (i < 3);
-+
-+	/*r_dma_trigger_AND1_inv = 0*/
-+	odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/
-+
-+	if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG)
-+		odm_set_mac_reg(dm, R_0x7c0, BIT(3), 1);
-+}
-+#endif
-+
-+#if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
-+void
-+phydm_la_clk_en(void *dm_void, boolean enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 val = (enable) ? 1 : 0;
-+
-+	if (!(dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)))
-+		return;
-+
-+	if (dm->support_ic_type == ODM_RTL8821C &&
-+	    dm->cut_version == ODM_CUT_A)
-+		return;
-+
-+	odm_set_bb_reg(dm, R_0x95c, BIT(23), val);
-+}
-+#endif
-+
-+#if (RTL8723F_SUPPORT)
-+void
-+phydm_la_mac_clk_en(void *dm_void, boolean enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 val = (enable) ? 1 : 0;
-+
-+	if (!(dm->support_ic_type & ODM_RTL8723F))
-+		return;
-+
-+	odm_set_mac_reg(dm, R_0x1008, BIT(1), val);
-+}
-+#endif
-+
-+#if (RTL8197F_SUPPORT)
-+void
-+phydm_la_stop_dma_8197f(void *dm_void, enum phydm_backup_type opt)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+
-+	if (dm->support_ic_type != ODM_RTL8197F)
-+		return;
-+
-+	if (opt == PHYDM_BACKUP) {
-+		/*Stop DMA*/
-+		smp->backup_dma = odm_get_mac_reg(dm, R_0x300, 0xffff);
-+		odm_set_mac_reg(dm, R_0x300, 0x7fff, 0x7fff);
-+	} else { /*restore*/
-+		/*Resume DMA*/
-+		odm_set_mac_reg(dm, R_0x300, 0x7fff, smp->backup_dma);
-+	}
-+}
-+#endif
-+
-+#ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
-+void
-+phydm_la_mv_data_2_tx_buffer(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
-+
-+	if (!(dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC))
-+		return;
-+
-+	pr_debug("GetTxPktBuf from iMEM\n");
-+	odm_set_mac_reg(dm, R_0x7c0, BIT(0), 0x0); /*Disable LA mode HW block*/
-+
-+	/* 98F LA memory loccation is separate from normal
-+	 * driver use, DMA is no longer required to stop
-+	 */
-+	#if (RTL8197F_SUPPORT)
-+	phydm_la_stop_dma_8197f(dm, PHYDM_BACKUP);
-+	#endif
-+
-+	/* @move LA mode content from IMEM to TxPktBuffer
-+	 * Source : OCPBASE_IMEM 0x00000000
-+	 * Destination : OCPBASE_TXBUF 0x18780000
-+	 * Length : 64K
-+	 */
-+	GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv,
-+						       OCPBASE_IMEM,
-+						       OCPBASE_TXBUF
-+						       + buf->start_pos,
-+						       0x10000);
-+}
-+#endif
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+
-+void phydm_la_bb_adv_reset_jgr3(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	struct la_adv_trig *adv = &smp->adv_trig_table;
-+
-+	odm_memory_set(dm, adv, 0, sizeof(struct la_adv_trig));
-+
-+}
-+
-+void phydm_la_bb_adv_trig_setting_jgr3(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	struct la_adv_trig *adv = &smp->adv_trig_table;
-+
-+	pr_debug(" *ADV BB-trig = %d\n", adv->la_adv_bbtrigger_en);
-+
-+	if (!adv->la_adv_bbtrigger_en) { /*normal LA mode & back to default*/
-+		/*@AND0*/
-+		odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 0);
-+
-+		/*@AND1*/
-+		odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, 0);
-+		odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/
-+		/*@AND2*/
-+		odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0);
-+		odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/
-+		/*@AND3*/
-+		odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0);
-+		odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/
-+		/*@AND4*/
-+		odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, 0); /*@AND 4 mask en*/
-+		odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/
-+	} else {
-+		/*@AND0 */
-+		/*path 1 default: enable ori. BB trigger*/
-+		odm_set_bb_reg(dm, R_0x1ce4, BIT(27),
-+			       (adv->la_ori_bb_dis ? 1 : 0));
-+
-+		/* @AND1 */
-+		odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv);
-+		odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, adv->la_and1_sel);
-+		odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val);
-+
-+		/*@AND2 */
-+		odm_set_bb_reg(dm, R_0x1ce8, BIT(15), adv->la_and2_inv);
-+		odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, adv->la_and2_sel);
-+		odm_set_bb_reg(dm, R_0x1ce8, 0x7c00, adv->la_and2_val);
-+
-+		/*@AND3 */
-+		odm_set_bb_reg(dm, R_0x1ce8, BIT(25), adv->la_and3_inv);
-+		odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, adv->la_and3_sel);
-+		odm_set_bb_reg(dm, R_0x1ce8, 0x1f00000, adv->la_and3_val);
-+
-+		/*@AND4 */
-+		odm_set_bb_reg(dm, R_0x1ce8, BIT(26), adv->la_and4_inv);
-+		odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, adv->la_and4_mask);
-+		odm_set_bb_reg(dm, R_0x1cec, MASKDWORD, adv->la_and4_bitmap);
-+	}
-+}
-+
-+void phydm_la_bb_adv_cmd_show_jgr3(void *dm_void, u32 *_used,
-+				   char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	struct la_adv_trig *adv = &smp->adv_trig_table;
-+
-+	PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+		 "  *And0 Disable=%d\n", adv->la_ori_bb_dis);
-+	PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+		 "  *And1{sel,val,inv}={0x%x,0x%x,%d}\n  *And2{sel,val,inv}={0x%x,0x%x,%d}\n  *And3{sel,val,inv}={0x%x,0x%x,%d}\n",
-+		 adv->la_and1_sel, adv->la_and1_val, adv->la_and1_inv,
-+		 adv->la_and2_sel, adv->la_and2_val, adv->la_and2_inv,
-+		 adv->la_and3_sel, adv->la_and3_val, adv->la_and3_inv);
-+	PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+		 "  *And4{mask,bitmap,inv}={0x%x,0x%x,%d}\n",
-+		 adv->la_and4_mask, adv->la_and4_bitmap, adv->la_and4_inv);
-+}
-+
-+void phydm_la_bb_adv_cmd_jgr3(void *dm_void, char input[][16], u32 *_used,
-+			      char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	struct la_adv_trig *adv = &smp->adv_trig_table;
-+	u32 var1[10] = {0};
-+	u32 adv_trig_en;
-+
-+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
-+		return;
-+
-+	if ((strcmp(input[2], "show") == 0)) {
-+		phydm_la_bb_adv_cmd_show_jgr3(dm, _used, output, _out_len);
-+		return;
-+	}
-+
-+	PHYDM_SSCANF(input[2], DCMD_HEX, &var1[0]);
-+	PHYDM_SSCANF(input[3], DCMD_HEX, &var1[1]);
-+	PHYDM_SSCANF(input[4], DCMD_HEX, &var1[2]);
-+	PHYDM_SSCANF(input[5], DCMD_HEX, &var1[3]);
-+	PHYDM_SSCANF(input[6], DCMD_HEX, &var1[4]);
-+
-+	adv_trig_en = var1[0];
-+
-+	if (adv_trig_en != 1) {
-+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+			 "Back to Ori-BB-trig\n");
-+		phydm_la_bb_adv_reset_jgr3(dm);
-+		return;
-+	}
-+
-+	adv->la_adv_bbtrigger_en = true;
-+
-+	if (var1[1] == 0) {
-+		adv->la_ori_bb_dis = (boolean)var1[2];
-+	} else if (var1[1] == 1) {
-+		adv->la_and1_sel = (u8)var1[2];
-+		adv->la_and1_val = (u8)var1[3];
-+		adv->la_and1_inv = (boolean)var1[4];
-+	} else if (var1[1] == 2) {
-+		adv->la_and2_sel = (u8)var1[2];
-+		adv->la_and2_val = (u8)var1[3];
-+		adv->la_and2_inv = (boolean)var1[4];
-+	} else if (var1[1] == 3) {
-+		adv->la_and3_sel = (u8)var1[2];
-+		adv->la_and3_val = (u8)var1[3];
-+		adv->la_and2_inv = (boolean)var1[4];
-+	}  else if (var1[1] == 4) {
-+		adv->la_and4_mask = var1[2];
-+		adv->la_and4_bitmap = var1[3];
-+		adv->la_and4_inv = (boolean)var1[4];
-+	}
-+
-+	PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+		 "[Adv_trig_en=%d]\n\n", adv_trig_en);
-+
-+	phydm_la_bb_adv_cmd_show_jgr3(dm, _used, output, _out_len);
-+}
-+
-+void phydm_la_cmd_fast_jgr3(void *dm_void, char input[][16], u32 *_used,
-+			    char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	struct la_adv_trig *adv = &smp->adv_trig_table;
-+	enum auto_detection_state ad_mode;
-+	const u8 ofdm_codeword[8] = {0xb, 0xf, 0xa, 0xe, 0x9, 0xd, 0x8, 0xc};
-+	u32 codeword;
-+	u8 rate_idx;
-+	u32 trig_time_cca = 0;
-+	s32 val_sign32_tmp = 0;
-+	u32 var[10] = {0};
-+	u8 bw = *dm->band_width;
-+
-+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
-+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+			 "Only Support for JGR-3 ICs\n");
-+		return;
-+	}
-+
-+	if (bw > 2) {
-+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+			 "Not Support for BW > %dM\n", 20 << bw);
-+		return;
-+	}
-+
-+	PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var[0]);
-+	PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var[1]);
-+	PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var[2]);
-+
-+	trig_time_cca = ((smp->smp_number_max >> (bw + 1)) / 10)
-+			- (2 << (2 - bw)) - (2 - bw);
-+
-+	if (var[0] < 10) {
-+	/*=== [Type: 0 ~ 10] : CCA P-edge trigger ==========================*/
-+		/*--- Basic Trigger Setting --------------------------------*/
-+		smp->la_trig_mode = 1;
-+		smp->la_trig_sig_sel = 2;
-+		smp->la_trigger_time = trig_time_cca;
-+		smp->la_mac_mask_or_hdr_sel = 0;
-+		smp->la_trigger_edge = 0;
-+		smp->la_smp_rate = 2 - bw;
-+		smp->la_count = 0;
-+		if (var[0] == 0) { /*AGC*/
-+			smp->la_dma_type = 5;
-+			smp->la_dbg_port = 0x870;
-+		} else if (var[0] == 1) { /*EVM*/
-+			smp->la_dma_type = 4;
-+			smp->la_dbg_port = 0x392;
-+		} else if (var[0] == 2) { /*SNR*/
-+			smp->la_dma_type = 4;
-+			if (var[1] == 0)
-+				smp->la_dbg_port = 0x89e;
-+			else
-+				smp->la_dbg_port = 0xa9e;
-+		} else if (var[0] == 3) { /*CFO*/
-+			smp->la_dma_type = 4;
-+			if (var[1] == 0)
-+				smp->la_dbg_port = 0x88c;
-+			else
-+				smp->la_dbg_port = 0xa8c;
-+		}  else if (var[0] == 4) { /*ADC*/
-+			if (var[1] == 0) {
-+				smp->la_dma_type = 0;
-+				smp->la_dbg_port = 0x880;
-+			} else {
-+				smp->la_dma_type = 1;
-+				smp->la_dbg_port = 0xa80;
-+			}
-+		}
-+		/*--- Adv-Trigger Setting------------------------------------*/
-+		adv->la_adv_bbtrigger_en = false;
-+	} else if (var[0] < 20) {
-+	/*=== [Type: 10 ~ 19]: RX-EVM Trigger ===============================*/
-+		/*--- Basic Trigger Setting ---------------------------------*/
-+		smp->la_trig_mode = 0;
-+		smp->la_trig_sig_sel = 0;
-+		smp->la_mac_mask_or_hdr_sel = 0;
-+		smp->la_trigger_edge = 0;
-+		smp->la_smp_rate = 2 - bw;
-+		smp->la_count = 0;
-+		smp->la_dma_type = 4;
-+		smp->la_dbg_port = 0x392;
-+
-+		/*--- Adv-Trigger Setting -----------------------------------*/
-+		phydm_la_bb_adv_reset_jgr3(dm);
-+		adv->la_adv_bbtrigger_en = true;
-+
-+		/*And[0]*/
-+		adv->la_ori_bb_dis = true;
-+
-+		/*And[1]*/
-+		adv->la_and1_inv = 0;
-+		adv->la_and1_sel = 4; /*RX-state*/
-+		if (var[2] == 0) {
-+			/*L-preamble 8+8+4 = 20*/
-+			smp->la_trigger_time = trig_time_cca - 20;
-+			/*Legacy Data*/
-+			adv->la_and1_val = 5;
-+		} else if (var[2] == 1) {
-+			/*HT-preamble (8+8+4) + (8+4+4*Nrx) = 32 + Nrx * 4*/
-+			smp->la_trigger_time = trig_time_cca - 32 -
-+					       (dm->num_rf_path * 4);
-+			/*HT Data*/
-+			adv->la_and1_val = 18;
-+		} else {
-+			/*VHT-preamble (8+8+4) + (8+4+4*Nrx) +4 = 36 + Nrx * 4*/
-+			smp->la_trigger_time = trig_time_cca - 36 -
-+					       (dm->num_rf_path * 4);
-+			/*VHT Data*/
-+			adv->la_and1_val = 18;
-+		}
-+
-+		/*And[2]*/
-+		adv->la_and2_inv = 0;
-+		adv->la_and2_sel = 0; /*Disable*/
-+
-+		/*And[3]*/
-+		adv->la_and2_inv = 0;
-+		adv->la_and3_sel = 0; /*Disable*/
-+
-+		/*And[4]*/
-+		adv->la_and4_inv = 0;
-+
-+		if (var[0] == 11) {
-+			/*[>= -X dB]*/
-+			if (var[1] == 2) {
-+				adv->la_and4_bitmap = 0;
-+				adv->la_and4_mask = 0x1;
-+			} else if (var[1] == 4) {
-+				adv->la_and4_bitmap = 0;
-+				adv->la_and4_mask = 0x3;
-+			} else if (var[1] == 8) {
-+				adv->la_and4_bitmap = 0;
-+				adv->la_and4_mask = 0x7;
-+			} else if (var[1] == 16) {
-+				adv->la_and4_bitmap = 0;
-+				adv->la_and4_mask = 0xf;
-+			} else if (var[1] == 32) {
-+				adv->la_and4_bitmap = 0;
-+				adv->la_and4_mask = 0x1f;
-+			} else if (var[1] == 64) {
-+				adv->la_and4_bitmap = 0;
-+				adv->la_and4_mask = 0x3f;
-+			} else {
-+				PDM_SNPF(*_out_len, *_used, output + *_used,
-+					 *_out_len - *_used,
-+					 "Not Support >= -%d dB\n", var[1]);
-+				return;
-+			}
-+		} else if (var[0] == 10) {
-+			/*[<= -X dB]*/
-+			if (var[1] == 2) {
-+				adv->la_and4_bitmap = 0x7e;
-+				adv->la_and4_mask = 0x7e;
-+			} else if (var[1] == 4) {
-+				adv->la_and4_bitmap = 0x7c;
-+				adv->la_and4_mask = 0x7c;
-+			} else if (var[1] == 8) {
-+				adv->la_and4_bitmap = 0x78;
-+				adv->la_and4_mask = 0x78;
-+			} else if (var[1] == 16) {
-+				adv->la_and4_bitmap = 0x70;
-+				adv->la_and4_mask = 0x70;
-+			} else if (var[1] == 32) {
-+				adv->la_and4_bitmap = 0x60;
-+				adv->la_and4_mask = 0x60;
-+			} else if (var[1] == 64) {
-+				adv->la_and4_bitmap = 0x40;
-+				adv->la_and4_mask = 0x40;
-+			} else {
-+				PDM_SNPF(*_out_len, *_used, output + *_used,
-+					 *_out_len - *_used,
-+					 "Not Support <= -%d dB\n", var[1]);
-+				return;
-+			}
-+		} else if (var[0] == 12) {
-+			/*[= -X dB]*/
-+			val_sign32_tmp = 0 - (s32)var[1];
-+			adv->la_and4_bitmap = (u32)(val_sign32_tmp & 0x7f);
-+			adv->la_and4_mask = 0x7f;
-+		}
-+	} else if (var[0] < 30) {
-+	/*=== [Type: 20 ~ 29]: RX-Rate Trigger ==============================*/
-+		/*--- Basic Trigger Setting ---------------------------------*/
-+		smp->la_trig_mode = 0;
-+		smp->la_trig_sig_sel = 0;
-+		smp->la_mac_mask_or_hdr_sel = 0;
-+		smp->la_trigger_edge = 0;
-+		smp->la_smp_rate = 2 - bw;
-+		smp->la_count = 0;
-+		smp->la_dma_type = 4;
-+
-+		rate_idx = (u8)var[1];
-+
-+		/*--- Adv-Trigger Setting -----------------------------------*/
-+		phydm_la_bb_adv_reset_jgr3(dm);
-+		adv->la_adv_bbtrigger_en = true;
-+
-+		/*And[0]*/
-+		adv->la_ori_bb_dis = true;
-+
-+		/*And[1]*/
-+		adv->la_and1_inv = 0;
-+		adv->la_and1_sel = 4; /*RX-state*/
-+
-+		if (rate_idx <= ODM_RATE54M && rate_idx >= ODM_RATE6M) {
-+			ad_mode = AD_LEGACY_MODE;
-+			codeword = (u32)ofdm_codeword[rate_idx - ODM_RATE6M];
-+			smp->la_dbg_port = 0x3a9;
-+			/*L-preamble 8+8 = 16*/
-+			smp->la_trigger_time = trig_time_cca - 20;
-+			/*Legacy Data*/
-+			adv->la_and1_val = 5;
-+		} else if (rate_idx <= ODM_RATEMCS31) {
-+			ad_mode = AD_HT_MODE;
-+			codeword = (u32)(rate_idx - ODM_RATEMCS0);
-+			smp->la_dbg_port = 0x3aa;
-+			/*HT-preamble (8+8+4) + (8+4+4*Nrx) = 32 + Nrx * 4*/
-+			smp->la_trigger_time = trig_time_cca - 32 -
-+					       (dm->num_rf_path * 4);
-+			/*HT,VHT Data*/
-+			adv->la_and1_val = 18;
-+		} else if (rate_idx <= ODM_RATEVHTSS4MCS9) {
-+			ad_mode = AD_VHT_MODE;
-+			codeword = (u32)phydm_rate_order_compute(dm, rate_idx);
-+			codeword--;
-+			smp->la_dbg_port = 0x3ab;
-+			/*VHT-preamble (8+8+4) + (8+4+4*Nrx) = 36 + Nrx * 4*/
-+			smp->la_trigger_time = trig_time_cca - 36 -
-+					       (dm->num_rf_path * 4);
-+			/*HT,VHT Data*/
-+			adv->la_and1_val = 18;
-+		} else {
-+			PDM_SNPF(*_out_len, *_used, output + *_used,
-+				 *_out_len - *_used,
-+				 "Not Support\n");
-+			return;
-+		}
-+
-+		/*And[2]*/
-+		adv->la_and2_inv = 0;
-+		adv->la_and2_sel = 0; /*Disable*/
-+
-+		/*And[3]*/
-+		adv->la_and2_inv = 0;
-+		adv->la_and3_sel = 0; /*Disable*/
-+
-+		/*And[4]*/
-+		adv->la_and4_inv = 0;
-+
-+		if (var[0] == 20) {
-+			if (ad_mode == AD_LEGACY_MODE) {
-+				adv->la_and4_bitmap = codeword;
-+				adv->la_and4_mask = 0x3000000f;
-+			} else if (ad_mode == AD_HT_MODE) {
-+				adv->la_and4_bitmap = (2 << 28) | codeword;
-+				adv->la_and4_mask = 0x3000003f;
-+			}  else { /* AD_VHT_MODE*/
-+				adv->la_and4_bitmap = (1 << 28) |
-+						      (codeword << 4);
-+				adv->la_and4_mask = 0x300000f0;
-+			}
-+		} else {
-+			PDM_SNPF(*_out_len, *_used, output + *_used,
-+				 *_out_len - *_used,
-+				 "Not Support\n");
-+			return;
-+		}
-+	} else {
-+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+			 "Not Support\n");
-+		return;
-+	}
-+	PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+		 "[Basic-Trigger]\n");
-+	PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+		 "  *echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
-+		 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
-+		 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
-+		 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
-+		 smp->la_count);
-+	pr_debug("echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
-+		 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
-+		 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
-+		 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
-+		 smp->la_count);
-+
-+	if (adv->la_adv_bbtrigger_en) {
-+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+			 "[Adv-Trigger]\n");
-+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+			 "  *And0 Disable=%d\n", adv->la_ori_bb_dis);
-+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+			 "  *And1{sel,val,inv}={0x%x,0x%x,%d}\n  *And2{sel,val,inv}={0x%x,0x%x,%d}\n  *And3{sel,val,inv}={0x%x,0x%x,%d}\n",
-+			 adv->la_and1_sel, adv->la_and1_val, adv->la_and1_inv,
-+			 adv->la_and2_sel, adv->la_and2_val, adv->la_and2_inv,
-+			 adv->la_and3_sel, adv->la_and3_val, adv->la_and3_inv);
-+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+			 "  *And4{mask,bitmap,inv}={0x%x,0x%x,%d}\n",
-+			 adv->la_and4_mask, adv->la_and4_bitmap,
-+			 adv->la_and4_inv);
-+	}
-+	phydm_la_set(dm);
-+}
-+
-+#endif
-+
-+void
-+phydm_la_buffer_print(void *dm_void, char input[][16], u32 *_used,
-+		      char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
-+	u64 la_pattern_msb, la_pattern_lsb;
-+	u64 la_pattern, la_pattern_part;
-+	s64 tmp_s64;
-+	u64 mask = 0xffffffff;
-+	u8 mask_length = 0;
-+	u32 i;
-+	u32 idx;
-+	u32 var[10] = {0};
-+
-+	if (!buf->octet || buf->length == 0 || buf->length < smp->smp_number)
-+		return;
-+
-+	PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var[0]);
-+	PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var[1]);
-+	PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var[2]);
-+	PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var[3]);
-+
-+	pr_debug("echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
-+		 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
-+		 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
-+		 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
-+		 smp->la_count);
-+	pr_debug("[LA Data Dump] smp_number = %d\n", smp->smp_number);
-+	pr_debug("Dump_Start\n");
-+
-+	if (var[0] == 0) {
-+		for (i = 0; i < smp->smp_number; i++) {
-+			idx = i << 1;
-+			pr_debug("%08x%08x\n", buf->octet[idx],
-+				 buf->octet[idx + 1]);
-+		}
-+	} else if (var[0] == 1) {
-+		/*------------------------*/
-+		if (var[1] == 0)
-+			pr_debug("[Hex]\n");
-+		else if (var[1] == 1)
-+			pr_debug("[Dec unsigned]\n");
-+		else if (var[1] == 2)
-+			pr_debug("[Dec signed]\n");
-+
-+		pr_debug("BIT[%d:%d]\n", var[3], var[2]);
-+
-+		if (var[2] > var[3]) {
-+			pr_debug("[Warning] BIT_L > BIT_H\n");
-+			return;
-+		}
-+
-+		mask_length = (u8)(var[3] - var[2] + 1);
-+		mask = phydm_gen_bitmask(mask_length) << var[2];
-+		/*------------------------*/
-+		for (i = 0; i < smp->smp_number; i++) {
-+			idx = i << 1;
-+			la_pattern_msb = (u64)buf->octet[idx];
-+			la_pattern_lsb = (u64)buf->octet[idx + 1];
-+			la_pattern = (la_pattern_msb << 32) | la_pattern_lsb;
-+			la_pattern_part = (la_pattern & mask) >> var[2];
-+
-+			if (var[1] == 0) {
-+				pr_debug("0x%llx\n", la_pattern_part);
-+			} else if (var[1] == 1) {
-+				pr_debug("%llu\n", la_pattern_part);
-+			} else if (var[1] == 2) {
-+				tmp_s64 = phydm_cnvrt_2_sign_64(la_pattern_part,
-+								mask_length);
-+				pr_debug("%lld\n", tmp_s64);
-+			}
-+		}
-+	}
-+	pr_debug("Dump_End\n\n");
-+}
-+
-+void
-+phydm_la_buffer_release(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
-+
-+	if (buf->length != 0x0) {
-+		odm_free_memory(dm, buf->octet, buf->length);
-+		buf->length = 0x0;
-+	}
-+}
-+
-+boolean
-+phydm_la_buffer_allocate(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	#endif
-+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
-+	boolean ret = true;
-+
-+	pr_debug("[LA mode BufferAllocate]\n");
-+
-+	if (buf->length == 0) {
-+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+		if (PlatformAllocateMemoryWithZero(adapter, (void **)&
-+						   buf->octet,
-+						   buf->buffer_size) !=
-+						   RT_STATUS_SUCCESS)
-+			ret = false;
-+	#else
-+		odm_allocate_memory(dm, (void **)&buf->octet, buf->buffer_size);
-+
-+		if (!buf->octet)
-+			ret = false;
-+	#endif
-+
-+		if (ret)
-+			buf->length = buf->buffer_size;
-+	}
-+
-+	return ret;
-+}
-+
-+void phydm_la_access_tx_pkt_buf(void *dm_void, u32 addr, u32 buff_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
-+	u32 page;
-+	u32 data_l = 0, data_h = 0;
-+
-+	#if (RTL8192F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8192F) {
-+		#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+		indirect_access_sdram_8192f(dm->adapter, TX_PACKET_BUFFER,
-+					    TRUE, (u16)addr >> 3, 0,
-+					    &data_h, &data_l);
-+		#else
-+		odm_write_1byte(dm, R_0x0106, 0x69);
-+		odm_set_mac_reg(dm, R_0x0140, MASKDWORD, addr >> 3);
-+		data_l = odm_get_mac_reg(dm, R_0x0144, MASKDWORD);
-+		data_h = odm_get_mac_reg(dm, R_0x0148, MASKDWORD);
-+		odm_write_1byte(dm, R_0x0106, 0x0);
-+		#endif
-+	} else
-+	#endif
-+	{
-+		/* Reg140=0x780+(addr>>12),
-+		 * addr=0x30~0x3F, total 16 pages
-+		 */
-+		page = addr >> 12;
-+
-+		if (page != smp->txff_page) {
-+			smp->txff_page = page;
-+			odm_set_mac_reg(dm, R_0x0140, MASKLWORD, 0x780 + page);
-+		}
-+		data_l = odm_read_4byte(dm, R_0x8000 + (addr & 0xfff));
-+		data_h = odm_read_4byte(dm, R_0x8000 + (addr & 0xfff) + 4);
-+	}
-+
-+	buf->octet[buff_idx] = data_h;
-+	buf->octet[buff_idx + 1] = data_l;
-+
-+	/*@==== [Print LA Patterns] ==========================================*/
-+	if (smp->is_la_print)
-+		pr_debug("%08x%08x\n", data_h, data_l);
-+}
-+
-+void phydm_la_get_tx_pkt_buf(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
-+	u32 i = 0, value32 = 0;
-+	u32 addr = 0, finish_addr = 0; /* @(unit: 8Byte)*/
-+	boolean is_round_up = false;
-+	u32 addr_8byte = 0;
-+	u32 round_up_point = 0;
-+	#if (RTL8814B_SUPPORT)
-+	boolean recover_success = true;
-+	#endif
-+
-+	odm_memory_set(dm, buf->octet, 0, buf->length);
-+	pr_debug("GetTxPktBuf\n");
-+
-+	/*@==== [Get LA Report] ==============================================*/
-+	if (dm->support_ic_type & ODM_RTL8192F) {
-+		value32 = odm_read_4byte(dm, R_0x7f0);
-+		is_round_up = (boolean)((value32 & BIT(31)) >> 31);
-+		finish_addr = (value32 & 0x7FFF8000) >> 15; /*@16 bit (unit: 8Byte)*/
-+	} else {
-+		odm_write_1byte(dm, R_0x0106, 0x69);
-+		value32 = odm_read_4byte(dm, R_0x7c0);
-+		is_round_up = (boolean)((value32 & BIT(31)) >> 31);
-+
-+		if (dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC)
-+			finish_addr = (value32 & 0x7FFF8000) >> 15; /*@16 bit (unit: 8Byte)*/
-+		else
-+			finish_addr = (value32 & 0x7FFF0000) >> 16; /*@15bit (unit: 8Byte)*/
-+	}
-+
-+	#if (RTL8814B_SUPPORT)
-+	recover_success = phydm_la_finish_addr_recover_8814B(dm, &finish_addr);
-+	#endif
-+
-+	pr_debug("start_addr = ((0x%x)), end_addr = ((0x%x)), buffer_size = ((0x%x))\n",
-+		 buf->start_pos, buf->end_pos, buf->buffer_size);
-+	if (is_round_up) {
-+		pr_debug("buf_start(0x%x)|----2---->|finish_addr(0x%x)|----1---->|buf_end(0x%x)\n",
-+			 buf->start_pos, finish_addr << 3, buf->end_pos);
-+		addr = (finish_addr + 2) << 3; /*+1 or +2 ??*/
-+		round_up_point = (buf->end_pos - addr) >> 3; /*@Byte to 8Byte*/
-+		smp->smp_number = smp->smp_number_max;
-+		pr_debug("is_round_up=(%d), round_up_point=(%d), 0x7c0/0x7F0=(0x%x), smp_number=(%d)\n",
-+			 is_round_up, round_up_point, value32, smp->smp_number);
-+	} else {
-+		pr_debug("buf_start(0x%x)|------->|finish_addr(0x%x)             |buf_end(0x%x)\n",
-+			 buf->start_pos, finish_addr << 3, buf->end_pos);
-+		addr = buf->start_pos;
-+		addr_8byte = addr >> 3;
-+		smp->smp_number = DIFF_2(addr_8byte, finish_addr);
-+
-+		pr_debug("is_round_up=(%d), smp_number=(%d)\n",
-+			 is_round_up, smp->smp_number);
-+	}
-+
-+	/*@==== [Get LA Patterns in TXFF] ====================================*/
-+	pr_debug("Dump_Start\n");
-+	#ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
-+	phydm_la_mv_data_2_tx_buffer(dm);
-+	#endif
-+
-+	#if (RTL8814B_SUPPORT)
-+	if ((dm->support_ic_type & ODM_RTL8814B) && !recover_success) {
-+		addr = buf->start_pos;
-+		smp->smp_number = smp->smp_number_max;
-+	}
-+	#endif
-+
-+	for (i = 0; i < smp->smp_number; i++) {
-+		phydm_la_access_tx_pkt_buf(dm, addr, i << 1);
-+		addr += 8;
-+
-+		if (addr >= buf->end_pos)
-+			addr = buf->start_pos; /*Ring buffer*/
-+	}
-+
-+	#if (RTL8197F_SUPPORT)
-+	phydm_la_stop_dma_8197f(dm, PHYDM_RESTORE);
-+	#endif
-+	pr_debug("Dump_End\n");
-+}
-+
-+void phydm_la_set_trig_src(void *dm_void, u8 la_trig_mode)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 reg = (dm->support_ic_type == ODM_RTL8192F) ? R_0x7f0 : R_0x7c0;
-+
-+	if (la_trig_mode == PHYDM_ADC_MAC_TRIG)
-+		odm_set_mac_reg(dm, reg, BIT(3), 1);
-+	else
-+		odm_set_mac_reg(dm, reg, BIT(3), 0);
-+}
-+
-+void phydm_la_set_mac_iq_dump(void *dm_void, boolean impossible_trig_condi)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	u32 reg_value = 0;
-+	u32 reg1 = 0, reg2 = 0, reg3 = 0;
-+
-+	if (dm->support_ic_type & ODM_RTL8192F) {
-+		reg1 = R_0x7f0;
-+		reg2 = R_0x7f4;
-+		reg3 = R_0x7f8;
-+	} else {
-+		reg1 = R_0x7c0;
-+		reg2 = R_0x7c4;
-+		reg3 = R_0x7c8;
-+	}
-+
-+	odm_write_1byte(dm, reg1, 0); /*@clear all reg1*/
-+	/*@Enable LA mode HW block*/
-+	odm_set_mac_reg(dm, reg1, BIT(0), 1);
-+
-+	#if (RTL8723F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8723F)
-+		phydm_la_mac_clk_en(dm, true);
-+	#endif
-+
-+	if (smp->la_trig_mode == PHYDM_MAC_TRIG) {
-+		smp->la_dump_mode = LA_MAC_DBG_DUMP;
-+		/*polling bit for MAC mode*/
-+		odm_set_mac_reg(dm, reg1, BIT(2), 1);
-+		/*trigger mode for MAC*/
-+		odm_set_mac_reg(dm, reg1, 0x18,	smp->la_trigger_edge);
-+		pr_debug("[MAC_trig] ref_mask=(0x%x), ref_value=(0x%x), dbg_port =(0x%x)\n",
-+			 smp->la_mac_mask_or_hdr_sel, smp->la_trig_sig_sel,
-+			 smp->la_dbg_port);
-+		/*@[Set MAC Debug Port]*/
-+		odm_set_mac_reg(dm, R_0xf4, BIT(16), 1);
-+		odm_set_mac_reg(dm, R_0x38, 0xff0000, smp->la_dbg_port);
-+		odm_set_mac_reg(dm, reg2, MASKDWORD,
-+				smp->la_mac_mask_or_hdr_sel);
-+		odm_set_mac_reg(dm, reg3, MASKDWORD, smp->la_trig_sig_sel);
-+	} else {
-+		smp->la_dump_mode = LA_BB_ADC_DUMP;
-+
-+		if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
-+			/*polling bit for MAC trigger event*/
-+			if (impossible_trig_condi)
-+				phydm_la_set_trig_src(dm, PHYDM_ADC_BB_TRIG);
-+			else
-+				phydm_la_set_trig_src(dm, PHYDM_ADC_MAC_TRIG);
-+
-+			odm_set_mac_reg(dm, reg1, 0xc0,	smp->la_trig_sig_sel);
-+
-+			if (smp->la_trig_sig_sel == ADCSMP_TRIG_REG) {
-+				/* @manual trigger reg1[5] = 0->1*/
-+				odm_set_mac_reg(dm, reg1, BIT(5), 1);
-+			}
-+		}
-+		/*polling bit for BB ADC mode*/
-+		odm_set_mac_reg(dm, reg1, BIT(1), 1);
-+	}
-+
-+	reg_value = odm_get_mac_reg(dm, reg1, 0xff);
-+	pr_debug("4. [Set MAC IQ dump] 0x%x[7:0]=(0x%x)\n", reg1, reg_value);
-+
-+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
-+		    ("4. [Set MAC IQ dump] 0x%x[7:0]=(0x%x)\n", reg1,
-+		    reg_value));
-+	#endif
-+}
-+
-+void phydm_la_set_bb_dbg_port(void *dm_void, boolean impossible_trig_condi)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+
-+	u8	trig_mode = smp->la_trig_mode;
-+	u32	trig_sel = smp->la_trig_sig_sel;
-+	u32	dbg_port = smp->la_dbg_port;
-+
-+	if (trig_mode == PHYDM_MAC_TRIG)
-+		trig_sel = 0; /*@ignore this setting*/
-+
-+	/*set BB debug port*/
-+	if (impossible_trig_condi) {
-+		dbg_port = 0xf;
-+		trig_sel = 0;
-+		pr_debug("[BB Setting] fake-trigger!\n");
-+	}
-+
-+	if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port)) {
-+		pr_debug(" *Set dbg_port=(0x%x)\n", dbg_port);
-+	} else {
-+		dbg_port = phydm_get_bb_dbg_port_idx(dm);
-+		pr_debug("[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port);
-+	}
-+
-+	/*@debug port bit*/
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		odm_set_bb_reg(dm, R_0x95c, 0x1f, trig_sel);
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, trig_sel);
-+	#endif
-+	} else {
-+		odm_set_bb_reg(dm, R_0x9a0, 0x1f, trig_sel);
-+	}
-+
-+	if (smp->la_trig_mode == PHYDM_ADC_BB_TRIG) {
-+		pr_debug(" *Set dbg_port[BIT] = %d\n", trig_sel);
-+
-+		#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+		RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
-+			    (" *Set dbg_port[BIT] = %d\n", trig_sel));
-+		#endif
-+	}
-+}
-+
-+void phydm_la_set_bb(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+
-+	u8	trig_mode = smp->la_trig_mode;
-+	u8	edge = smp->la_trigger_edge;
-+	u8	smp_rate = smp->la_smp_rate;
-+	u8	dma_type = smp->la_dma_type;
-+	u32	dbg_port_hdr_sel = 0;
-+	char	*trig_mode_word = NULL;
-+
-+	pr_debug("3. [BB Setting] mode=(%d), Edge=(%s), smp_rate=(%dM), Dma_type=(%d)\n",
-+		 trig_mode,
-+		 (edge == 0) ? "P" : "N", 80 >> smp_rate, dma_type);
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		if (trig_mode == PHYDM_ADC_RF0_TRIG)
-+			dbg_port_hdr_sel = 9; /*@DBGOUT_RFC_a[31:0]*/
-+		else if (trig_mode == PHYDM_ADC_RF1_TRIG)
-+			dbg_port_hdr_sel = 8; /*@DBGOUT_RFC_b[31:0]*/
-+		else if ((trig_mode == PHYDM_ADC_BB_TRIG) ||
-+			 (trig_mode == PHYDM_ADC_MAC_TRIG)) {
-+			if (smp->la_mac_mask_or_hdr_sel <= 0xf)
-+				dbg_port_hdr_sel = smp->la_mac_mask_or_hdr_sel;
-+			else
-+				dbg_port_hdr_sel = 0;
-+		}
-+
-+		phydm_bb_dbg_port_header_sel(dm, dbg_port_hdr_sel);
-+
-+		odm_set_bb_reg(dm, R_0x8b4, BIT(7), 1);/*@update rpt every pkt*/
-+		odm_set_bb_reg(dm, R_0x95c, 0xf00, dma_type);
-+		/*@0: posedge, 1: negedge*/
-+		odm_set_bb_reg(dm, R_0x95c, BIT(31), edge);
-+		odm_set_bb_reg(dm, R_0x95c, 0xe0, smp_rate);
-+		/*	@(0:) '80MHz'
-+		 *	(1:) '40MHz'
-+		 *	(2:) '20MHz'
-+		 *	(3:) '10MHz'
-+		 *	(4:) '5MHz'
-+		 *	(5:) '2.5MHz'
-+		 *	(6:) '1.25MHz'
-+		 *	(7:) '160MHz (for BW160 ic)'
-+		 */
-+		#if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
-+		phydm_la_clk_en(dm, true);
-+		#endif
-+
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		odm_set_bb_reg(dm, R_0x1eb4, BIT(23), 0x1);/*@update rpt every pkt*/
-+		/*@MAC-PHY timing*/
-+		odm_set_bb_reg(dm, R_0x1ce4, BIT(7) | BIT(6), 0);
-+		odm_set_bb_reg(dm, R_0x1cf4, BIT(23), 1); /*@LA mode on*/
-+		odm_set_bb_reg(dm, R_0x1ce4, 0x3f, dma_type);
-+		/*@0: posedge, 1: negedge ??*/
-+		odm_set_bb_reg(dm, R_0x1ce4, BIT(26), edge);
-+		odm_set_bb_reg(dm, R_0x1ce4, 0x700, smp_rate);
-+
-+		phydm_la_bb_adv_trig_setting_jgr3(dm);
-+	#endif
-+	} else {
-+		if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
-+			odm_set_bb_reg(dm, R_0xd00, BIT(26), 0x1); /*@update rpt every pkt*/
-+
-+		#if (RTL8192F_SUPPORT)
-+		if ((dm->support_ic_type & ODM_RTL8192F))
-+			/*@LA reset HW block enable for true-mac asic*/
-+			odm_set_bb_reg(dm, R_0x9a0, BIT(15), 1);
-+		#endif
-+
-+		odm_set_bb_reg(dm, R_0x9a0, 0xf00, dma_type);
-+		/*@0: posedge, 1: negedge*/
-+		odm_set_bb_reg(dm, R_0x9a0, BIT(31), edge);
-+		odm_set_bb_reg(dm, R_0x9a0, 0xe0, smp_rate);
-+		/*	@(0:) '80MHz'
-+		 *	(1:) '40MHz'
-+		 *	(2:) '20MHz'
-+		 *	(3:) '10MHz'
-+		 *	(4:) '5MHz'
-+		 *	(5:) '2.5MHz'
-+		 *	(6:) '1.25MHz'
-+		 *	(7:) '160MHz (for BW160 ic)'
-+		 */
-+	}
-+}
-+
-+void phydm_la_set_mac_trigger_time(void *dm_void, u32 trigger_time_mu_sec)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 time_unit_num = 0;
-+	u32 unit = 0;
-+
-+	if (trigger_time_mu_sec < 128)
-+		unit = 0; /*unit: 1mu sec*/
-+	else if (trigger_time_mu_sec < 256)
-+		unit = 1; /*unit: 2mu sec*/
-+	else if (trigger_time_mu_sec < 512)
-+		unit = 2; /*unit: 4mu sec*/
-+	else if (trigger_time_mu_sec < 1024)
-+		unit = 3; /*unit: 8mu sec*/
-+	else if (trigger_time_mu_sec < 2048)
-+		unit = 4; /*unit: 16mu sec*/
-+	else if (trigger_time_mu_sec < 4096)
-+		unit = 5; /*unit: 32mu sec*/
-+	else if (trigger_time_mu_sec < 8192)
-+		unit = 6; /*unit: 64mu sec*/
-+	else if (trigger_time_mu_sec < 16384)
-+		if (dm->support_ic_type & ODM_RTL8723F)
-+			unit = 7; /*unit: 128mu sec*/
-+
-+	time_unit_num = (u8)(trigger_time_mu_sec >> unit);
-+
-+	pr_debug("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
-+		 time_unit_num, unit);
-+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, (
-+		    "3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
-+		    time_unit_num, unit));
-+	#endif
-+
-+	if (dm->support_ic_type & ODM_RTL8192F) {
-+		odm_set_mac_reg(dm, R_0x7fc, BIT(2) | BIT(1) | BIT(0), unit);
-+		odm_set_mac_reg(dm, R_0x7f0, 0x7f00, (time_unit_num & 0x7f));
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	} else if (dm->support_ic_type & ODM_RTL8814B) {
-+		odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit);
-+		odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		odm_set_mac_reg(dm, R_0x7cc, BIT(18) | BIT(17) | BIT(16), unit);
-+		odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
-+	#endif
-+	} else {
-+		odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit);
-+		odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
-+	}
-+}
-+
-+void phydm_la_set_buff_mode(void *dm_void, enum la_buff_mode mode)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	struct rtl8192cd_priv		*priv = dm->priv;
-+	u8 normal_LA_on = priv->pmib->miscEntry.normal_LA_on;
-+#endif
-+	u32 buff_size_base = 0;
-+	u32 end_pos_tmp = 0;
-+
-+	smp->la_buff_mode = mode;
-+	switch (dm->support_ic_type) {
-+	case ODM_RTL8814A:
-+		buff_size_base = 0x10000;
-+		end_pos_tmp = 0x40000;
-+		break;
-+	case ODM_RTL8822B:
-+	case ODM_RTL8822C:
-+	case ODM_RTL8812F:
-+		buff_size_base = 0x20000; /*@WIN: TX_FIFO_SIZE_LA_8822C*/
-+		end_pos_tmp = 0x40000;
-+		break;
-+	case ODM_RTL8814B:
-+		buff_size_base = 0x30000;
-+		end_pos_tmp = 0x60000;
-+		break;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	case ODM_RTL8197F:
-+	case ODM_RTL8198F:
-+	case ODM_RTL8197G:
-+		buff_size_base = 0x10000;
-+		end_pos_tmp = (normal_LA_on == 1) ? 0x20000 : 0x10000;
-+		break;
-+#endif
-+	case ODM_RTL8192F:
-+		buff_size_base = 0xE000;
-+		end_pos_tmp = 0x10000;
-+		break;
-+	case ODM_RTL8821C:
-+		buff_size_base = 0x8000;
-+		end_pos_tmp = 0x10000;
-+		break;
-+	case ODM_RTL8195B:
-+		buff_size_base = 0x4000;
-+		end_pos_tmp = 0x8000;
-+		break;
-+	case ODM_RTL8723F:
-+		buff_size_base = 0x20000;
-+		end_pos_tmp = 0x60000;
-+		break;
-+	default:
-+		pr_debug("[%s] Warning!", __func__);
-+		break;
-+	}
-+
-+	buf->buffer_size = buff_size_base;
-+
-+	if (dm->support_ic_type & ODM_RTL8814B) {
-+		if (mode == ADCSMP_BUFF_HALF) {
-+			odm_set_mac_reg(dm, R_0x7cc, BIT(21), 0);
-+		} else {
-+			buf->buffer_size = buf->buffer_size << 1;
-+			odm_set_mac_reg(dm, R_0x7cc, BIT(21), 1);
-+		}
-+	} else if (dm->support_ic_type & FULL_BUFF_MODE_SUPPORT) {
-+		if (mode == ADCSMP_BUFF_HALF) {
-+			odm_set_mac_reg(dm, R_0x7cc, BIT(30), 0);
-+		} else {
-+			buf->buffer_size = buf->buffer_size << 1;
-+			odm_set_mac_reg(dm, R_0x7cc, BIT(30), 1);
-+		}
-+	}
-+
-+	buf->end_pos = end_pos_tmp;
-+	buf->start_pos = end_pos_tmp - buf->buffer_size;
-+	smp->smp_number_max = buf->buffer_size >> 3;
-+
-+	pr_debug("start_addr=(0x%x), end_addr=(0x%x), buffer_size=(0x%x), smp_number_max=(%d)\n",
-+		 buf->start_pos, buf->end_pos, buf->buffer_size,
-+		 smp->smp_number_max);
-+}
-+
-+void phydm_la_adc_smp_start(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	u8 tmp_u1b = 0;
-+	u8 i = 0;
-+	u8 polling_bit = 0;
-+	u8 bkp_val = 0;
-+	boolean polling_ok = false;
-+	boolean impossible_trig_condi = (smp->en_fake_trig) ? true : false;
-+
-+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
-+		    ("1. [BB Setting] Mode=(%d), DbgPort=(0x%x), Edge=(%d), SmpRate=(%d), Trig_Sel=(0x%x), Dma_type=(%d)\n",
-+		    smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge,
-+		    smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type));
-+	#endif
-+	pr_debug("1. [BB Setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
-+		 smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge,
-+		 smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type);
-+
-+	if(dm->support_ic_type & ODM_RTL8723F)
-+		bkp_val = (u8)odm_get_mac_reg(dm, R_0x1008, BIT(1));
-+
-+	phydm_la_set_mac_trigger_time(dm, smp->la_trigger_time);
-+	phydm_la_set_bb(dm);
-+	phydm_la_set_bb_dbg_port(dm, impossible_trig_condi);
-+	phydm_la_set_mac_iq_dump(dm, impossible_trig_condi);
-+
-+	#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	watchdog_stop(dm->priv);
-+	#endif
-+
-+	if (impossible_trig_condi) {
-+		ODM_delay_ms(100);
-+		phydm_la_set_bb_dbg_port(dm, false);
-+
-+		if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
-+			phydm_la_set_trig_src(dm, PHYDM_ADC_MAC_TRIG);
-+		}
-+	}
-+#if RTL8198F_SUPPORT
-+	phydm_la_pre_run(dm);
-+#endif
-+	polling_bit = (smp->la_dump_mode == LA_BB_ADC_DUMP) ? BIT(1) : BIT(2);
-+	do { /*Polling time always use 100ms, when it exceed 2s, break loop*/
-+		if (dm->support_ic_type & ODM_RTL8192F)
-+			tmp_u1b = odm_read_1byte(dm, R_0x7f0);
-+		else
-+			tmp_u1b = odm_read_1byte(dm, R_0x7c0);
-+
-+		pr_debug("[%d] polling rpt=((0x%x))\n", i, tmp_u1b);
-+
-+		if (smp->adc_smp_state != ADCSMP_STATE_SET) {
-+			pr_debug("[state Error] state != ADCSMP_STATE_SET\n");
-+			break;
-+
-+		} else if (tmp_u1b & polling_bit) {
-+			ODM_delay_ms(100);
-+			i++;
-+			continue;
-+		} else {
-+			pr_debug("[LA Query OK] polling_bit=%d\n", polling_bit);
-+			polling_ok = true;
-+			break;
-+		}
-+	} while (i < 20);
-+
-+	if (smp->adc_smp_state == ADCSMP_STATE_SET) {
-+		if (polling_ok)
-+			phydm_la_get_tx_pkt_buf(dm);
-+		else
-+			pr_debug("[Polling timeout]\n");
-+	}
-+
-+	#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	watchdog_resume(dm->priv);
-+	#endif
-+
-+	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	if (smp->adc_smp_state == ADCSMP_STATE_SET)
-+		smp->adc_smp_state = ADCSMP_STATE_QUERY;
-+	#endif
-+
-+	pr_debug("[LA mode] la_count = ((%d))\n", smp->la_count);
-+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
-+		    ("[LA mode] la_count = ((%d))\n", smp->la_count));
-+	#endif
-+
-+	phydm_la_stop(dm);
-+
-+	if (smp->la_count == 0) {
-+		pr_debug("LA Dump finished ---------->\n\n\n");
-+		phydm_release_bb_dbg_port(dm);
-+
-+		#if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
-+		phydm_la_clk_en(dm, false);
-+		#endif
-+		#if (RTL8723F_SUPPORT)
-+		if(dm->support_ic_type & ODM_RTL8723F)
-+			phydm_la_mac_clk_en(dm, (bkp_val == 1) ? true : false);
-+		#endif
-+	} else {
-+		smp->la_count--;
-+		pr_debug("LA Dump more ---------->\n\n\n");
-+		phydm_la_set(dm);
-+	}
-+}
-+
-+void phydm_la_set(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean is_set_success = true;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+
-+	if (smp->adc_smp_state != ADCSMP_STATE_IDLE)
-+		is_set_success = false;
-+	else if (smp->adc_smp_buf.length == 0)
-+		is_set_success = phydm_la_buffer_allocate(dm);
-+
-+	if (!is_set_success) {
-+		pr_debug("[LA Set Fail] LA_State=(%d)\n", smp->adc_smp_state);
-+		return;
-+	}
-+
-+	smp->adc_smp_state = ADCSMP_STATE_SET;
-+
-+	pr_debug("[LA Set Success] LA_State=(%d)\n", smp->adc_smp_state);
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+
-+	pr_debug("ADCSmp_work_item_index=(%d)\n", smp->la_work_item_index);
-+
-+	if (smp->la_work_item_index != 0) {
-+		odm_schedule_work_item(&smp->adc_smp_work_item_1);
-+		smp->la_work_item_index = 0;
-+	} else {
-+		odm_schedule_work_item(&smp->adc_smp_work_item);
-+		smp->la_work_item_index = 1;
-+	}
-+#else
-+	phydm_la_adc_smp_start(dm);
-+#endif
-+}
-+
-+void phydm_la_cmd(void *dm_void, char input[][16], u32 *_used, char *output,
-+		  u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
-+		return;
-+
-+#ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
-+	if (dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC) {
-+		if (dm->is_download_fw)
-+			return;
-+	}
-+	#if RTL8198F_SUPPORT
-+	if (dm->support_ic_type & ODM_RTL8198F) {
-+		if (!*dm->mp_mode && !dm->priv->pmib->miscEntry.normal_LA_on) {
-+			pr_debug("plz re-set normal_LA_on = 1 & DnUp.\n");
-+			return;
-+		}
-+	}
-+	#endif
-+#endif
-+
-+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+
-+	/*@dbg_print("echo cmd input_num = %d\n", input_num);*/
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "=====[LA Mode Help] =============================\n");
-+		/*Trigger*/
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "BB_trig:  1 0 {DbgPort Bit} {DMA#} {TrigTime} {DbgPort_head(Jgr2)}\n\t{DbgPort} {Edge: 0(P),1(N)} {f_smp:80 >> N} {Capture num}\n\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "MAC_trig: 1 1 {0-ok/1-fail/2-cca} {DMA#} {TrigTime} {DbgPort_head(Jgr2)}\n\t{DbgPort} {N/A} {f_smp:80 >> N} {Cpture num}\n\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "All: {En} {0:ADC_BB_trig,1:ADC MAC_trig,2:RF0,3:RF1,4:MAC}\n\t{BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA#} {TrigTime}\n\t{DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n\n");
-+		/*Adv-Trig*/
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "adv show\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "adv {adv_trig_en} {0:And[0]_disable} {en}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "adv {adv_trig_en} {1~3: And[3:0]} {Sel} {Val} {Inv}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "adv {adv_trig_en} {4: And[4]} {BitMask} {BitVal} {Inv}\n\n");
-+		#endif
-+		/*Setting*/
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "set {1:tx_buff_size} {0: half, 1:full}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "set {2:Fake Trigger} {en}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "set {3:Auto Print} {en}\n\n");
-+		/*Print*/
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "print {0: all(Hex)}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "print {1: partial} {0:hex 1:dec 2: s-dec} {bit_L} {bit_H}\n\n");
-+
-+		/*Fast Trigger*/
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "fast {0: CCA trig & AGC Dbg Port}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "fast {1: CCA trig & EVM Dbg Port}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "fast {2: CCA trig & SNR Dbg Port}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "fast {3: CCA trig & CFO Dbg Port}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "fast {4: CCA trig & ADC output Dbg Port}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "fast {10: EVM>=-X dB, 11: EVM<=-X dB} {X=2/4/8/16/32/64} {0:Lgcy, 1:HT}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "fast {12: EVM=-X dB} {X} {0:Lgcy, 1:HT}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "fast {20: RX-rate-idx=X} {X}\n");
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "=================================================\n");
-+	} else if ((strcmp(input[1], "print") == 0)) {
-+		phydm_la_buffer_print(dm, input, &used, output, &out_len);
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	} else if ((strcmp(input[1], "fast") == 0)) {
-+		phydm_la_cmd_fast_jgr3(dm, input, &used, output, &out_len);
-+
-+	} else if ((strcmp(input[1], "adv") == 0)) {
-+		phydm_la_bb_adv_cmd_jgr3(dm, input, &used, output, &out_len);
-+#endif
-+	} else if ((strcmp(input[1], "set") == 0)) {
-+		PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
-+
-+		if (var1[1] == 1) {
-+			PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
-+			phydm_la_set_buff_mode(dm, (enum la_buff_mode)var1[2]);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Buff_mode=(%d/2)\n", smp->la_buff_mode + 1);
-+		} else if (var1[1] == 2) {
-+			PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
-+			smp->en_fake_trig = (boolean)var1[2];
-+
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "en_fake_trig=(%d)\n", smp->en_fake_trig);
-+		} else if (var1[1] == 3) {
-+			PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
-+			smp->is_la_print = (boolean)var1[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Auto print=(%d)\n", smp->is_la_print);
-+		}
-+	} else if (var1[0] == 1) {
-+		PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
-+
-+		smp->la_trig_mode = (u8)var1[1];
-+
-+		if (smp->la_trig_mode == PHYDM_MAC_TRIG)
-+			PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
-+		else
-+			PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
-+		smp->la_trig_sig_sel = var1[2];
-+
-+		PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
-+		PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
-+		PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
-+		PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
-+		PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
-+		PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
-+		PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
-+
-+		smp->la_dma_type = (u8)var1[3];
-+		smp->la_trigger_time = var1[4]; /*unit: us*/
-+		smp->la_mac_mask_or_hdr_sel = var1[5];
-+		smp->la_dbg_port = var1[6];
-+		smp->la_trigger_edge = (u8)var1[7];
-+		smp->la_smp_rate = (u8)(var1[8] & 0x7);
-+		smp->la_count = var1[9];
-+
-+		pr_debug("echo lamode %d %d %d %d %d %d %x %d %d %d\n",
-+			 var1[0], var1[1], var1[2], var1[3], var1[4],
-+			 var1[5], var1[6], var1[7], var1[8], var1[9]);
-+		#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+		RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
-+			    ("echo lamode %d %d %d %d %d %d %x %d %d %d\n",
-+			    var1[0], var1[1], var1[2], var1[3],
-+			    var1[4], var1[5], var1[6], var1[7],
-+			    var1[8], var1[9]));
-+		#endif
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "a.En= ((1)),  b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n",
-+			 smp->la_trig_mode, smp->la_trig_sig_sel,
-+			 smp->la_dma_type);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n",
-+			 smp->la_trigger_time,
-+			 smp->la_mac_mask_or_hdr_sel, smp->la_dbg_port);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n",
-+			 smp->la_trigger_edge, (80 >> smp->la_smp_rate),
-+			 smp->la_count);
-+
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "k.en_new_bbtrigger = ((%d))\n",
-+			 smp->adv_trig_table.la_adv_bbtrigger_en);
-+		#endif
-+
-+		phydm_la_set(dm);
-+	} else {
-+		phydm_la_stop(dm);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Disable LA mode\n");
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_la_stop(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+
-+	smp->adc_smp_state = ADCSMP_STATE_IDLE;
-+}
-+
-+void phydm_la_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+	struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
-+
-+	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
-+		return;
-+
-+	smp->adc_smp_state = ADCSMP_STATE_IDLE;
-+	smp->is_la_print = true;
-+	smp->en_fake_trig = false;
-+	smp->txff_page = 0xffffffff;
-+	phydm_la_set_buff_mode(dm, ADCSMP_BUFF_HALF);
-+
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	phydm_la_bb_adv_reset_jgr3(dm);
-+	#endif
-+}
-+
-+void adc_smp_de_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
-+		return;
-+
-+	phydm_la_stop(dm);
-+	phydm_la_buffer_release(dm);
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+void adc_smp_work_item_callback(void *context)
-+{
-+	void *adapter = (void *)context;
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+	struct rt_adcsmp *smp = &dm->adcsmp;
-+
-+	pr_debug("[WorkItem Call back] LA_State=(%d)\n", smp->adc_smp_state);
-+	phydm_la_adc_smp_start(dm);
-+}
-+#endif
-+#endif /*@endif PHYDM_LA_MODE_SUPPORT*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_adc_sampling.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_adc_sampling.h
-new file mode 100644
-index 000000000000..0e00e2719664
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_adc_sampling.h
-@@ -0,0 +1,172 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __INC_ADCSMP_H
-+#define __INC_ADCSMP_H
-+
-+#if (PHYDM_LA_MODE_SUPPORT)
-+
-+/* 2020.07.03 [8723F] Fix SD4 compile error*/
-+#define DYNAMIC_LA_MODE "4.2"
-+
-+/* @1 ============================================================
-+ * 1  Definition
-+ * 1 ============================================================
-+ */
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+#if (RTL8197F_SUPPORT || RTL8198F_SUPPORT || RTL8197G_SUPPORT)
-+	#define PHYDM_COMPILE_LA_STORE_IN_IMEM
-+#endif
-+#endif
-+
-+#define PHYDM_LA_STORE_IN_IMEM_IC (ODM_RTL8197F | ODM_RTL8198F | ODM_RTL8197G)
-+
-+#define FULL_BUFF_MODE_SUPPORT (ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\
-+				ODM_RTL8812F | ODM_RTL8814B)
-+
-+/* @ ============================================================
-+ *  enumrate
-+ *  ============================================================
-+ */
-+enum la_dump_mode {
-+	LA_BB_ADC_DUMP		= 0,
-+	LA_MAC_DBG_DUMP		= 1
-+};
-+
-+enum rt_adcsmp_trig_sel {
-+	PHYDM_ADC_BB_TRIG	= 0,
-+	PHYDM_ADC_MAC_TRIG	= 1,
-+	PHYDM_ADC_RF0_TRIG	= 2,
-+	PHYDM_ADC_RF1_TRIG	= 3,
-+	PHYDM_MAC_TRIG		= 4
-+};
-+
-+enum rt_adcsmp_trig_sig_sel {
-+	ADCSMP_TRIG_CRCOK	= 0,
-+	ADCSMP_TRIG_CRCFAIL	= 1,
-+	ADCSMP_TRIG_CCA		= 2,
-+	ADCSMP_TRIG_REG		= 3
-+};
-+
-+enum rt_adcsmp_state {
-+	ADCSMP_STATE_IDLE	= 0,
-+	ADCSMP_STATE_SET	= 1,
-+	ADCSMP_STATE_QUERY	= 2
-+};
-+
-+enum la_buff_mode {
-+	ADCSMP_BUFF_HALF	= 0,
-+	ADCSMP_BUFF_ALL		= 1	/*Only use in MP Driver*/
-+};
-+
-+/* @ ============================================================
-+ *   structure
-+ *  ============================================================
-+ */
-+
-+struct rt_adcsmp_string {
-+	u32			*octet;
-+	u32			length;
-+	u32			buffer_size;
-+	u32			start_pos;
-+	u32			end_pos;	/*@buf addr*/
-+};
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+struct la_adv_trig {
-+	boolean			la_adv_bbtrigger_en;
-+	boolean			la_ori_bb_dis;
-+	u8			la_and1_sel;
-+	u8			la_and1_val;
-+	boolean			la_and1_inv;
-+	u8			la_and2_sel;
-+	u8			la_and2_val;
-+	boolean			la_and2_inv;
-+	u8			la_and3_sel;
-+	u8			la_and3_val;
-+	boolean			la_and3_inv;
-+	u32			la_and4_mask;
-+	u32			la_and4_bitmap;
-+	boolean			la_and4_inv;
-+};
-+#endif
-+
-+struct rt_adcsmp {
-+	struct rt_adcsmp_string	adc_smp_buf;
-+	enum rt_adcsmp_state	adc_smp_state;
-+	enum la_buff_mode	la_buff_mode;
-+	enum la_dump_mode	la_dump_mode;
-+	u8			la_trig_mode;
-+	u32			la_trig_sig_sel;
-+	u8			la_dma_type;
-+	u32			la_trigger_time;
-+	/*@1.BB mode: Dbg port header sel, 2.MAC mode: for reference mask*/
-+	u32			la_mac_mask_or_hdr_sel;
-+	u32			la_dbg_port;
-+	u8			la_trigger_edge;
-+	u8			la_smp_rate;
-+	u32			la_count;
-+	u32			smp_number;
-+	u32			smp_number_max;
-+	u32			txff_page;
-+	boolean			is_la_print;
-+	boolean			en_fake_trig;
-+#if (RTL8197F_SUPPORT)
-+	u32			backup_dma;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	u8			la_work_item_index;
-+	RT_WORK_ITEM		adc_smp_work_item;
-+	RT_WORK_ITEM		adc_smp_work_item_1;
-+#endif
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	struct la_adv_trig	adv_trig_table;
-+#endif
-+};
-+
-+/* @ ============================================================
-+ *  Function Prototype
-+ *  ============================================================
-+ */
-+
-+void phydm_la_set(void *dm_void);
-+
-+void phydm_la_cmd(void *dm_void, char input[][16], u32 *_used, char *output,
-+		  u32 *_out_len);
-+
-+void phydm_la_stop(void *dm_void);
-+
-+void phydm_la_init(void *dm_void);
-+
-+void adc_smp_de_init(void *dm_void);
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+void adc_smp_work_item_callback(void *context);
-+#endif
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_antdect.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_antdect.c
-new file mode 100644
-index 000000000000..a3213896ccdb
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_antdect.c
-@@ -0,0 +1,888 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/* ************************************************************
-+ * include files
-+ * ************************************************************ */
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef CONFIG_ANT_DETECTION
-+
-+/* @IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter)
-+ * IS_ANT_DETECT_SUPPORT_RSSI(adapter)
-+ * IS_ANT_DETECT_SUPPORT_PSD(adapter) */
-+
-+/* @1 [1. Single Tone method] =================================================== */
-+
-+/*@
-+ * Description:
-+ *	Set Single/Dual Antenna default setting for products that do not do detection in advance.
-+ *
-+ * Added by Joseph, 2012.03.22
-+ *   */
-+void odm_sw_ant_div_construct_scan_chnl(
-+	void *adapter,
-+	u8 scan_chnl)
-+{
-+}
-+
-+u8 odm_sw_ant_div_select_scan_chnl(
-+	void *adapter)
-+{
-+	return 0;
-+}
-+
-+void odm_single_dual_antenna_default_setting(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
-+	void *adapter = dm->adapter;
-+
-+	u8 bt_ant_num = BT_GetPgAntNum(adapter);
-+	/* Set default antenna A and B status */
-+	if (bt_ant_num == 2) {
-+		dm_swat_table->ANTA_ON = true;
-+		dm_swat_table->ANTB_ON = true;
-+
-+	} else if (bt_ant_num == 1) {
-+		/* Set antenna A as default */
-+		dm_swat_table->ANTA_ON = true;
-+		dm_swat_table->ANTB_ON = false;
-+
-+	} else
-+		RT_ASSERT(false, ("Incorrect antenna number!!\n"));
-+}
-+
-+/* @2 8723A ANT DETECT
-+ *
-+ * Description:
-+ *	Implement IQK single tone for RF DPK loopback and BB PSD scanning.
-+ *	This function is cooperated with BB team Neil.
-+ *
-+ * Added by Roger, 2011.12.15
-+ *   */
-+boolean
-+odm_single_dual_antenna_detection(
-+	void *dm_void,
-+	u8 mode)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	void *adapter = dm->adapter;
-+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
-+	u32 current_channel, rf_loop_reg;
-+	u8 n;
-+	u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca;
-+	u8 initial_gain = 0x5a;
-+	u32 PSD_report_tmp;
-+	u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0;
-+	boolean is_result = true;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__);
-+
-+	if (!(dm->support_ic_type & ODM_RTL8723B))
-+		return is_result;
-+
-+	/* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
-+	if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(((PADAPTER)adapter)))
-+		return is_result;
-+
-+	/* @1 Backup Current RF/BB Settings */
-+
-+	current_channel = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
-+	rf_loop_reg = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK);
-+	if (dm->support_ic_type & ODM_RTL8723B) {
-+		reg92c = odm_get_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD);
-+		reg930 = odm_get_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD);
-+		reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
-+		regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
-+		reg064 = odm_get_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29));
-+		odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x1);
-+		odm_set_bb_reg(dm, rfe_ctrl_anta_src, 0xff, 0x77);
-+		odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* @dbg 7 */
-+		odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0); /* @dbg 8 */
-+		odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x0);
-+	}
-+
-+	ODM_delay_us(10);
-+
-+	/* Store A path Register 88c, c08, 874, c50 */
-+	reg88c = odm_get_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD);
-+	regc08 = odm_get_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD);
-+	reg874 = odm_get_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD);
-+	regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
-+
-+	/* Store AFE Registers */
-+	if (dm->support_ic_type & ODM_RTL8723B)
-+		afe_rrx_wait_cca = odm_get_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD);
-+
-+	/* Set PSD 128 pts */
-+	odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* @128 pts */
-+
-+	/* To SET CH1 to do */
-+	odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* @channel 1 */
-+
-+	/* @AFE all on step */
-+	if (dm->support_ic_type & ODM_RTL8723B)
-+		odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016);
-+
-+	/* @3 wire Disable */
-+	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0);
-+
-+	/* @BB IQK setting */
-+	odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4);
-+	odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000);
-+
-+	/* @IQK setting tone@ 4.34Mhz */
-+	odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C);
-+	odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
-+
-+	/* Page B init */
-+	odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000);
-+	odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000);
-+	odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
-+	odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
-+	if (dm->support_ic_type & ODM_RTL8723B) {
-+		odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016);
-+		odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016);
-+	}
-+	odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0);
-+	odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain);
-+
-+	/* @IQK Single tone start */
-+	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
-+	odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
-+	odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
-+
-+	ODM_delay_us(10000);
-+
-+	/* PSD report of antenna A */
-+	PSD_report_tmp = 0x0;
-+	for (n = 0; n < 2; n++) {
-+		PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);
-+		if (PSD_report_tmp > ant_a_report)
-+			ant_a_report = PSD_report_tmp;
-+	}
-+
-+	/* @change to Antenna B */
-+	if (dm->support_ic_type & ODM_RTL8723B) {
-+		odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
-+		odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
-+	}
-+
-+	ODM_delay_us(10);
-+
-+	/* PSD report of antenna B */
-+	PSD_report_tmp = 0x0;
-+	for (n = 0; n < 2; n++) {
-+		PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);
-+		if (PSD_report_tmp > ant_b_report)
-+			ant_b_report = PSD_report_tmp;
-+	}
-+
-+	/* @Close IQK Single Tone function */
-+	odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
-+
-+	/* @1 Return to antanna A */
-+	if (dm->support_ic_type & ODM_RTL8723B) {
-+		/* @external DPDT */
-+		odm_set_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD, reg92c);
-+
-+		/* @internal S0/S1 */
-+		odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
-+		odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
-+		odm_set_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD, reg930);
-+		odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064);
-+	}
-+
-+	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c);
-+	odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08);
-+	odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874);
-+	odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40);
-+	odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_loop_reg);
-+
-+	/* Reload AFE Registers */
-+	if (dm->support_ic_type & ODM_RTL8723B)
-+		odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca);
-+
-+	if (dm->support_ic_type & ODM_RTL8723B) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_A[%d]= %d\n", 2416,
-+			  ant_a_report);
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_B[%d]= %d\n", 2416,
-+			  ant_b_report);
-+
-+		/* @2 Test ant B based on ant A is ON */
-+		if (ant_a_report >= 100 && ant_b_report >= 100 && ant_a_report <= 135 && ant_b_report <= 135) {
-+			u8 TH1 = 2, TH2 = 6;
-+
-+			if ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) {
-+				dm_swat_table->ANTA_ON = true;
-+				dm_swat_table->ANTB_ON = true;
-+				PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual Antenna\n",
-+					  __func__);
-+			} else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) ||
-+				   ((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) {
-+				dm_swat_table->ANTA_ON = false;
-+				dm_swat_table->ANTB_ON = false;
-+				is_result = false;
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "%s: Need to check again\n",
-+					  __func__);
-+			} else {
-+				dm_swat_table->ANTA_ON = true;
-+				dm_swat_table->ANTB_ON = false;
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "%s: Single Antenna\n", __func__);
-+			}
-+			dm->ant_detected_info.is_ant_detected = true;
-+			dm->ant_detected_info.db_for_ant_a = ant_a_report;
-+			dm->ant_detected_info.db_for_ant_b = ant_b_report;
-+			dm->ant_detected_info.db_for_ant_o = ant_0_report;
-+
-+		} else {
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "return false!!\n");
-+			is_result = false;
-+		}
-+	}
-+	return is_result;
-+}
-+
-+/* @1 [2. Scan AP RSSI method] ================================================== */
-+
-+boolean
-+odm_sw_ant_div_check_before_link(
-+	void *dm_void)
-+{
-+#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
-+
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	void *adapter = dm->adapter;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	//PMGNT_INFO		mgnt_info = &adapter->MgntInfo;
-+	PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo);
-+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	s8 score = 0;
-+	PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc;
-+	u8 power_target_L = 9, power_target_H = 16;
-+	u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff;
-+	u16 index, counter = 0;
-+	static u8 scan_channel;
-+	u32 tmp_swas_no_link_bk_reg948;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n",
-+		  dm->dm_swat_table.ANTA_ON, dm->dm_swat_table.ANTB_ON);
-+
-+	/* @if(HP id) */
-+	{
-+		if (dm->dm_swat_table.rssi_ant_dect_result == true && dm->support_ic_type == ODM_RTL8723B) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "8723B RSSI-based Antenna Detection is done\n");
-+			return false;
-+		}
-+
-+		if (dm->support_ic_type == ODM_RTL8723B) {
-+			if (dm_swat_table->swas_no_link_bk_reg948 == 0xff)
-+				dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
-+		}
-+	}
-+
-+	if (dm->adapter == NULL) { /* @For BSOD when plug/unplug fast.  //By YJ,120413 */
-+		/* The ODM structure is not initialized. */
-+		return false;
-+	}
-+
-+	/* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
-+	if (!IS_ANT_DETECT_SUPPORT_RSSI(((PADAPTER)adapter)))
-+		return false;
-+	else
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "Antenna Detection: RSSI method\n");
-+
-+	/* Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. */
-+	odm_acquire_spin_lock(dm, RT_RF_STATE_SPINLOCK);
-+	if (hal_data->eRFPowerState != eRfOn || mgnt_info->RFChangeInProgress || mgnt_info->bMediaConnect) {
-+		odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "%s: rf_change_in_progress(%x), e_rf_power_state(%x)\n",
-+			  __func__, mgnt_info->RFChangeInProgress,
-+			  hal_data->eRFPowerState);
-+
-+		dm_swat_table->swas_no_link_state = 0;
-+
-+		return false;
-+	} else
-+		odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->swas_no_link_state = %d\n",
-+		  dm_swat_table->swas_no_link_state);
-+	/* @1 Run AntDiv mechanism "Before Link" part. */
-+	if (dm_swat_table->swas_no_link_state == 0) {
-+		/* @1 Prepare to do Scan again to check current antenna state. */
-+
-+		/* Set check state to next step. */
-+		dm_swat_table->swas_no_link_state = 1;
-+
-+		/* @Copy Current Scan list. */
-+		mgnt_info->tmpNumBssDesc = mgnt_info->NumBssDesc;
-+		PlatformMoveMemory((void *)mgnt_info->tmpbssDesc, (void *)mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC);
-+
-+		/* @Go back to scan function again. */
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Scan one more time\n",
-+			  __func__);
-+		mgnt_info->ScanStep = 0;
-+		mgnt_info->bScanAntDetect = true;
-+		scan_channel = odm_sw_ant_div_select_scan_chnl(adapter);
-+
-+		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
-+			if (fat_tab->rx_idle_ant == MAIN_ANT)
-+				odm_update_rx_idle_ant(dm, AUX_ANT);
-+			else
-+				odm_update_rx_idle_ant(dm, MAIN_ANT);
-+			if (scan_channel == 0) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "%s: No AP List Avaiable, Using ant(%s)\n",
-+					  __func__,
-+					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
-+					  "AUX_ANT" : "MAIN_ANT");
-+
-+				if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
-+					dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_5g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
-+				} else {
-+					dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_2g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
-+				}
-+				return false;
-+			}
-+
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "%s: Change to %s for testing.\n", __func__,
-+				  ((fat_tab->rx_idle_ant == MAIN_ANT) ?
-+				  "MAIN_ANT" : "AUX_ANT"));
-+		} else if (dm->support_ic_type & (ODM_RTL8723B)) {
-+			/*Switch Antenna to another one.*/
-+
-+			tmp_swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
-+
-+			if (dm_swat_table->cur_antenna == MAIN_ANT && tmp_swas_no_link_bk_reg948 == 0x200) {
-+				odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
-+				odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
-+				dm_swat_table->cur_antenna = AUX_ANT;
-+			} else {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "Reg[948]= (( %x )) was in wrong state\n",
-+					  tmp_swas_no_link_bk_reg948);
-+				return false;
-+			}
-+			ODM_delay_us(10);
-+
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "%s: Change to (( %s-ant))  for testing.\n",
-+				  __func__,
-+				  (dm_swat_table->cur_antenna == MAIN_ANT) ?
-+				  "MAIN" : "AUX");
-+		}
-+
-+		odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
-+		PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
-+
-+		return true;
-+	} else { /* @dm_swat_table->swas_no_link_state == 1 */
-+		/* @1 ScanComple() is called after antenna swiched. */
-+		/* @1 Check scan result and determine which antenna is going */
-+		/* @1 to be used. */
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV, " tmp_num_bss_desc= (( %d ))\n",
-+			  mgnt_info->tmpNumBssDesc); /* @debug for Dino */
-+
-+		for (index = 0; index < mgnt_info->tmpNumBssDesc; index++) {
-+			p_tmp_bss_desc = &mgnt_info->tmpbssDesc[index]; /* @Antenna 1 */
-+			p_test_bss_desc = &mgnt_info->bssDesc[index]; /* @Antenna 2 */
-+
-+			if (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "%s: ERROR!! This shall not happen.\n",
-+					  __func__);
-+				continue;
-+			}
-+
-+			if (dm->support_ic_type != ODM_RTL8723B) {
-+				if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
-+					if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) {
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score++\n", __func__);
-+						RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
-+
-+						score++;
-+						PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
-+					} else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) {
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score--\n", __func__);
-+						RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
-+						score--;
-+					} else {
-+						if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp < 5000) {
-+							RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "The 2nd Antenna didn't get this AP\n\n");
-+						}
-+					}
-+				}
-+			} else { /* @8723B */
-+				if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber);
-+
-+					if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { /* Pow(Ant1) > Pow(Ant2) */
-+						counter++;
-+						tmp_power_diff = (u8)(p_tmp_bss_desc->RecvSignalPower - p_test_bss_desc->RecvSignalPower);
-+						power_diff = power_diff + tmp_power_diff;
-+
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
-+						PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
-+						PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
-+
-+#if 0
-+						/* PHYDM_DBG(dm,DBG_ANT_DIV, "tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff); */
-+#endif
-+						if (tmp_power_diff > max_power_diff)
-+							max_power_diff = tmp_power_diff;
-+						if (tmp_power_diff < min_power_diff)
-+							min_power_diff = tmp_power_diff;
-+#if 0
-+						/* PHYDM_DBG(dm,DBG_ANT_DIV, "max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff); */
-+#endif
-+
-+						PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
-+					} else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */
-+						counter++;
-+						tmp_power_diff = (u8)(p_test_bss_desc->RecvSignalPower - p_tmp_bss_desc->RecvSignalPower);
-+						power_diff = power_diff + tmp_power_diff;
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
-+						PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
-+						PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
-+						if (tmp_power_diff > max_power_diff)
-+							max_power_diff = tmp_power_diff;
-+						if (tmp_power_diff < min_power_diff)
-+							min_power_diff = tmp_power_diff;
-+					} else { /* Pow(Ant1) = Pow(Ant2) */
-+						if (p_test_bss_desc->bdTstamp > p_tmp_bss_desc->bdTstamp) { /* Stamp(Ant1) < Stamp(Ant2) */
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);
-+							if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp > 5000) {
-+								counter++;
-+								PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
-+								PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
-+								PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
-+								min_power_diff = 0;
-+							}
-+						} else
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);
-+					}
-+				}
-+			}
-+		}
-+
-+		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
-+			if (mgnt_info->NumBssDesc != 0 && score < 0) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "%s: Using ant(%s)\n", __func__,
-+					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
-+					  "MAIN_ANT" : "AUX_ANT");
-+			} else {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "%s: Remain ant(%s)\n", __func__,
-+					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
-+					  "AUX_ANT" : "MAIN_ANT");
-+
-+				if (fat_tab->rx_idle_ant == MAIN_ANT)
-+					odm_update_rx_idle_ant(dm, AUX_ANT);
-+				else
-+					odm_update_rx_idle_ant(dm, MAIN_ANT);
-+			}
-+
-+			if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
-+				dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "dm_swat_table->ant_5g=%s\n",
-+					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
-+					  "MAIN_ANT" : "AUX_ANT");
-+			} else {
-+				dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "dm_swat_table->ant_2g=%s\n",
-+					  (fat_tab->rx_idle_ant == MAIN_ANT) ?
-+					  "MAIN_ANT" : "AUX_ANT");
-+			}
-+		} else if (dm->support_ic_type == ODM_RTL8723B) {
-+			if (counter == 0) {
-+				if (dm->dm_swat_table.pre_aux_fail_detec == false) {
-+					dm->dm_swat_table.pre_aux_fail_detec = true;
-+					dm->dm_swat_table.rssi_ant_dect_result = false;
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] ->  Scan Target-channel again\n");
-+
-+					/* @3 [ Scan again ] */
-+					odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
-+					PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
-+					return true;
-+				} else { /* pre_aux_fail_detec == true */
-+					/* @2 [ Single Antenna ] */
-+					dm->dm_swat_table.pre_aux_fail_detec = false;
-+					dm->dm_swat_table.rssi_ant_dect_result = true;
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[  Still cannot find any AP ]]\n");
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
-+				}
-+				dm->dm_swat_table.aux_fail_detec_counter++;
-+			} else {
-+				dm->dm_swat_table.pre_aux_fail_detec = false;
-+
-+				if (counter == 3) {
-+					avg_power_diff = ((power_diff - max_power_diff - min_power_diff) >> 1) + ((max_power_diff + min_power_diff) >> 2);
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) ,  power_diff: (( %d ))\n", counter, power_diff);
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) ,  min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
-+				} else if (counter >= 4) {
-+					avg_power_diff = (power_diff - max_power_diff - min_power_diff) / (counter - 2);
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) ,  power_diff: (( %d ))\n", counter, power_diff);
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) ,  min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
-+
-+				} else { /* @counter==1,2 */
-+					avg_power_diff = power_diff / counter;
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "avg_power_diff: (( %d )) , counter: (( %d )) ,  power_diff: (( %d ))\n", avg_power_diff, counter, power_diff);
-+				}
-+
-+				/* @2 [ Retry ] */
-+				if (avg_power_diff >= power_target_L && avg_power_diff <= power_target_H) {
-+					dm->dm_swat_table.retry_counter++;
-+
-+					if (dm->dm_swat_table.retry_counter <= 3) {
-+						dm->dm_swat_table.rssi_ant_dect_result = false;
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Low confidence result ]] avg_power_diff= (( %d ))  ->  Scan Target-channel again ]]\n", avg_power_diff);
-+
-+						/* @3 [ Scan again ] */
-+						odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
-+						PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
-+						return true;
-+					} else {
-+						dm->dm_swat_table.rssi_ant_dect_result = true;
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Still Low confidence result ]]  (( retry_counter > 3 ))\n");
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
-+					}
-+				}
-+				/* @2 [ Dual Antenna ] */
-+				else if ((mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) {
-+					dm->dm_swat_table.rssi_ant_dect_result = true;
-+					if (dm->dm_swat_table.ANTB_ON == false) {
-+						dm->dm_swat_table.ANTA_ON = true;
-+						dm->dm_swat_table.ANTB_ON = true;
-+					}
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual antenna\n", __func__);
-+					dm->dm_swat_table.dual_ant_counter++;
-+
-+					/* set bt coexDM from 1ant coexDM to 2ant coexDM */
-+					BT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2);
-+
-+					/* @3 [ Init antenna diversity ] */
-+					dm->support_ability |= ODM_BB_ANT_DIV;
-+					odm_ant_div_init(dm);
-+				}
-+				/* @2 [ Single Antenna ] */
-+				else if (avg_power_diff > power_target_H) {
-+					dm->dm_swat_table.rssi_ant_dect_result = true;
-+					if (dm->dm_swat_table.ANTB_ON == true) {
-+						dm->dm_swat_table.ANTA_ON = true;
-+						dm->dm_swat_table.ANTB_ON = false;
-+#if 0
-+						/* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */
-+#endif
-+					}
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
-+					dm->dm_swat_table.single_ant_counter++;
-+				}
-+			}
-+#if 0
-+			/* PHYDM_DBG(dm,DBG_ANT_DIV, "is_result=(( %d ))\n",dm->dm_swat_table.rssi_ant_dect_result); */
-+#endif
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n",
-+				  dm->dm_swat_table.dual_ant_counter,
-+				  dm->dm_swat_table.single_ant_counter,
-+				  dm->dm_swat_table.retry_counter,
-+				  dm->dm_swat_table.aux_fail_detec_counter);
-+
-+			/* @2 recover the antenna setting */
-+
-+			if (dm->dm_swat_table.ANTB_ON == false)
-+				odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, (dm_swat_table->swas_no_link_bk_reg948));
-+
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "is_result=(( %d )), Recover  Reg[948]= (( %x ))\n\n",
-+				  dm->dm_swat_table.rssi_ant_dect_result,
-+				  dm_swat_table->swas_no_link_bk_reg948);
-+		}
-+
-+		/* @Check state reset to default and wait for next time. */
-+		dm_swat_table->swas_no_link_state = 0;
-+		mgnt_info->bScanAntDetect = false;
-+
-+		return false;
-+	}
-+
-+#else
-+	return false;
-+#endif
-+
-+	return false;
-+}
-+
-+/* @1 [3. PSD method] ========================================================== */
-+void odm_single_dual_antenna_detection_psd(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 channel_ori;
-+	u8 initial_gain = 0x36;
-+	u8 tone_idx;
-+	u8 tone_lenth_1 = 7, tone_lenth_2 = 4;
-+	u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56};
-+	u16 tone_idx_2[4] = {8, 24, 40, 56};
-+	u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0};
-+	/* u8	tone_lenth_1=4, tone_lenth_2=2; */
-+	/* u16	tone_idx_1[4]={88, 120, 24, 56}; */
-+	/* u16	tone_idx_2[2]={ 24,  56}; */
-+	/* u32	psd_report_main[6]={0}, psd_report_aux[6]={0}; */
-+
-+	u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0;
-+	u32 PSD_power_threshold;
-+	u32 main_psd_result = 0, aux_psd_result = 0;
-+	u32 regc50, reg948, regb2c, regc14, reg908;
-+	u32 i = 0, test_num = 8;
-+
-+	if (dm->support_ic_type != ODM_RTL8723B)
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__);
-+
-+	/* @2 [ Backup Current RF/BB Settings ] */
-+
-+	channel_ori = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
-+	reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
-+	regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
-+	regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
-+	regc14 = odm_get_bb_reg(dm, R_0xc14, MASKDWORD);
-+	reg908 = odm_get_bb_reg(dm, R_0x908, MASKDWORD);
-+
-+	/* @2 [ setting for doing PSD function (CH4)] */
-+	odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 0); /* @disable whole CCK block */
-+	odm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* Turn off TX  ->  Pause TX Queue */
-+	odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */
-+
-+	/* PHYTXON while loop */
-+	odm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x803);
-+	while (odm_get_bb_reg(dm, R_0xdf4, BIT(6))) {
-+		i++;
-+		if (i > 1000000) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "Wait in %s() more than %d times!\n",
-+				  __FUNCTION__, i);
-+			break;
-+		}
-+	}
-+
-+	odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain);
-+	odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */
-+	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable    88c[23:20]=0xf */
-+	odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt	 */ /* Set PSD 128 ptss */
-+	ODM_delay_us(3000);
-+
-+	/* @2 [ Doing PSD Function in (CH4)] */
-+
-+	/* @Antenna A */
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant   (CH4)\n");
-+	odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200);
-+	ODM_delay_us(10);
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "dbg\n");
-+	for (i = 0; i < test_num; i++) {
-+		for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
-+			PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
-+			/* @if(  PSD_report_temp>psd_report_main[tone_idx]  ) */
-+			psd_report_main[tone_idx] += PSD_report_temp;
-+		}
-+	}
-+	/* @Antenna B */
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant   (CH4)\n");
-+	odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280);
-+	ODM_delay_us(10);
-+	for (i = 0; i < test_num; i++) {
-+		for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
-+			PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
-+			/* @if(  PSD_report_temp>psd_report_aux[tone_idx]  ) */
-+			psd_report_aux[tone_idx] += PSD_report_temp;
-+		}
-+	}
-+	/* @2 [ Doing PSD Function in (CH8)] */
-+
-+	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable    88c[23:20]=0x0 */
-+	ODM_delay_us(3000);
-+
-+	odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain);
-+	odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */
-+
-+	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable    88c[23:20]=0xf */
-+	ODM_delay_us(3000);
-+
-+	/* @Antenna A */
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant   (CH8)\n");
-+	odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200);
-+	ODM_delay_us(10);
-+
-+	for (i = 0; i < test_num; i++) {
-+		for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
-+			PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
-+			/* @if(  PSD_report_temp>psd_report_main[tone_idx]  ) */
-+			psd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp;
-+		}
-+	}
-+
-+	/* @Antenna B */
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant   (CH8)\n");
-+	odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280);
-+	ODM_delay_us(10);
-+
-+	for (i = 0; i < test_num; i++) {
-+		for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
-+			PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
-+			/* @if(  PSD_report_temp>psd_report_aux[tone_idx]  ) */
-+			psd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp;
-+		}
-+	}
-+
-+	/* @2 [ Calculate Result ] */
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "\nMain PSD Result: (ALL)\n");
-+	for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1),
-+			  psd_report_main[tone_idx]);
-+		main_psd_result += psd_report_main[tone_idx];
-+		if (psd_report_main[tone_idx] > max_psd_report_main)
-+			max_psd_report_main = psd_report_main[tone_idx];
-+	}
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "--------------------------- \nTotal_Main= (( %d ))\n",
-+		  main_psd_result);
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Main = (( %d ))\n",
-+		  max_psd_report_main);
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "\nAux PSD Result: (ALL)\n");
-+	for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1),
-+			  psd_report_aux[tone_idx]);
-+		aux_psd_result += psd_report_aux[tone_idx];
-+		if (psd_report_aux[tone_idx] > max_psd_report_aux)
-+			max_psd_report_aux = psd_report_aux[tone_idx];
-+	}
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "--------------------------- \nTotal_Aux= (( %d ))\n",
-+		  aux_psd_result);
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Aux = (( %d ))\n\n",
-+		  max_psd_report_aux);
-+
-+	/* @main_psd_result=main_psd_result-max_psd_report_main; */
-+	/* @aux_psd_result=aux_psd_result-max_psd_report_aux; */
-+	PSD_power_threshold = (main_psd_result * 7) >> 3;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n",
-+		  main_psd_result, aux_psd_result, PSD_power_threshold);
-+
-+	/* @3 [ Dual Antenna ] */
-+	if (aux_psd_result >= PSD_power_threshold) {
-+		if (dm->dm_swat_table.ANTB_ON == false) {
-+			dm->dm_swat_table.ANTA_ON = true;
-+			dm->dm_swat_table.ANTB_ON = true;
-+		}
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "odm_sw_ant_div_check_before_link(): Dual antenna\n");
-+
-+#if 0
-+		/* set bt coexDM from 1ant coexDM to 2ant coexDM */
-+		/* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */
-+#endif
-+
-+		/* @Init antenna diversity */
-+		dm->support_ability |= ODM_BB_ANT_DIV;
-+		odm_ant_div_init(dm);
-+	}
-+	/* @3 [ Single Antenna ] */
-+	else {
-+		if (dm->dm_swat_table.ANTB_ON == true) {
-+			dm->dm_swat_table.ANTA_ON = true;
-+			dm->dm_swat_table.ANTB_ON = false;
-+		}
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "odm_sw_ant_div_check_before_link(): Single antenna\n");
-+	}
-+
-+	/* @2 [ Recover all parameters ] */
-+
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori);
-+	odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable    88c[23:20]=0x0 */
-+	odm_set_bb_reg(dm, R_0xc50, 0x7f, regc50);
-+
-+	odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
-+	odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
-+
-+	odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 1); /* @enable whole CCK block */
-+	odm_write_1byte(dm, REG_TXPAUSE, 0x0); /* Turn on TX	 */ /* Resume TX Queue */
-+	odm_set_bb_reg(dm, R_0xc14, MASKDWORD, regc14); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */
-+	odm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908);
-+
-+	return;
-+}
-+
-+void odm_sw_ant_detect_init(void *dm_void)
-+{
-+#if (RTL8723B_SUPPORT == 1)
-+
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
-+
-+	if (dm->support_ic_type != ODM_RTL8723B)
-+		return;
-+
-+	/* @dm_swat_table->pre_antenna = MAIN_ANT; */
-+	/* @dm_swat_table->cur_antenna = MAIN_ANT; */
-+	dm_swat_table->swas_no_link_state = 0;
-+	dm_swat_table->pre_aux_fail_detec = false;
-+	dm_swat_table->swas_no_link_bk_reg948 = 0xff;
-+
-+#ifdef CONFIG_PSD_TOOL
-+	phydm_psd_init(dm);
-+#endif
-+#endif
-+}
-+#endif
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_antdect.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_antdect.h
-new file mode 100644
-index 000000000000..f7fc75f185ab
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_antdect.h
-@@ -0,0 +1,78 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDMANTDECT_H__
-+#define __PHYDMANTDECT_H__
-+
-+#define ANTDECT_VERSION "2.1"
-+
-+#if (defined(CONFIG_ANT_DETECTION))
-+/* @#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
-+/* @ANT Test */
-+#define ANTTESTALL 0x00 /*@ant A or B will be Testing*/
-+#define ANTTESTA 0x01 /*@ant A will be Testing*/
-+#define ANTTESTB 0x02 /*@ant B will be testing*/
-+
-+#define MAX_ANTENNA_DETECTION_CNT 10
-+
-+struct _ANT_DETECTED_INFO {
-+	boolean is_ant_detected;
-+	u32 db_for_ant_a;
-+	u32 db_for_ant_b;
-+	u32 db_for_ant_o;
-+};
-+
-+enum dm_swas {
-+	antenna_a = 1,
-+	antenna_b = 2,
-+	antenna_max = 3,
-+};
-+
-+/* @1 [1. Single Tone method] =================================================== */
-+
-+void odm_single_dual_antenna_default_setting(
-+	void *dm_void);
-+
-+boolean
-+odm_single_dual_antenna_detection(
-+	void *dm_void,
-+	u8 mode);
-+
-+/* @1 [2. Scan AP RSSI method] ================================================== */
-+
-+#define sw_ant_div_check_before_link odm_sw_ant_div_check_before_link
-+
-+boolean
-+odm_sw_ant_div_check_before_link(
-+	void *dm_void);
-+
-+/* @1 [3. PSD method] ========================================================== */
-+
-+void odm_single_dual_antenna_detection_psd(
-+	void *dm_void);
-+
-+void odm_sw_ant_detect_init(void *dm_void);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_antdiv.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_antdiv.c
-new file mode 100644
-index 000000000000..5be61b63d73a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_antdiv.c
-@@ -0,0 +1,6552 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+/*******************************************************
-+ * when antenna test utility is on or some testing need to disable antenna
-+ * diversity call this function to disable all ODM related mechanisms which
-+ * will switch antenna.
-+ *****************************************************
-+ */
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+#if (RTL8710C_SUPPORT == 1)
-+void odm_s0s1_sw_ant_div_init_8710c(void *dm_void)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	struct sw_antenna_switch	*swat_tab = &dm->dm_swat_table;
-+	struct phydm_fat_struct		*fat_tab = &dm->dm_fat_table;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "***8710C AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
-+	/*MAC setting*/
-+	HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xdc, HAL_READ32(SYSTEM_CTRL_BASE, R_0xdc) | BIT18 | BIT17 | BIT16);
-+	HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xac, HAL_READ32(SYSTEM_CTRL_BASE, R_0xac) | BIT24 | BIT6);
-+	HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x10, 0x307);
-+	HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x08, 0x80000111);
-+	HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x1208, 0x800000);
-+
-+	/* Status init */
-+	fat_tab->is_become_linked  = false;
-+	swat_tab->try_flag = SWAW_STEP_INIT;
-+	swat_tab->double_chk_flag = 0;
-+	swat_tab->cur_antenna = MAIN_ANT;
-+	swat_tab->pre_ant = MAIN_ANT;
-+	dm->antdiv_counter = CONFIG_ANTDIV_PERIOD;
-+}
-+
-+void odm_trx_hw_ant_div_init_8710c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[8710C] AntDiv_Init =>  ant_div_type=[CG_TRX_HW_ANTDIV]\n");
-+	odm_set_mac_reg(dm, R_0x74, BIT(13) | BIT(12), 1);
-+	odm_set_mac_reg(dm, R_0x74, BIT(4), 1);
-+
-+	/*@BT Coexistence*/
-+	/*@keep antsel_map when GNT_BT = 1*/
-+	odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
-+	
-+	/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
-+	odm_set_bb_reg(dm, R_0x874, BIT(23), 1);
-+	odm_set_bb_reg(dm, R_0x930, 0xF00, 8); /* RFE CTRL_2 ANTSEL0 */
-+
-+	odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
-+	odm_set_bb_reg(dm, R_0x804, BIT(8), 0); /* r_keep_rfpin */
-+
-+	/*@Mapping Table*/
-+	//odm_set_bb_reg(dm, R_0x864, BIT2|BIT1|BIT0, 2); 
-+	odm_set_bb_reg(dm, R_0x944, 0xFFFF, 0xffff); 
-+	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
-+	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
-+	/*@antenna training	*/
-+	odm_set_bb_reg(dm, R_0xe08, BIT(16), 0);
-+	
-+	//need to check!!!!!!!!!!
-+	/* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */
-+	odm_set_bb_reg(dm, R_0xccc, BIT(12), 0);
-+	/* @Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */
-+	odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01);
-+	/* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */
-+	odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0);
-+	/* @b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable (CCK)*/
-+	odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06);
-+	/* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable (CCK) */
-+	odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00);
-+
-+	/*OFDM HW AntDiv Parameters*/
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0x80);
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00);
-+	odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04);
-+
-+	/*@CCK HW AntDiv Parameters*/
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
-+	odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0);
-+
-+	odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf);
-+	odm_set_bb_reg(dm, R_0xa14, 0x1F, 0xf);
-+	odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1);
-+	odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0);
-+	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1);
-+}
-+void odm_update_rx_idle_ant_8710c(void *dm_void, u8 ant, u32 default_ant,
-+				  u32 optional_ant)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	void *adapter = dm->adapter;
-+	
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "***odm_update_rx_idle_ant_8710c!!!\n");
-+	if (dm->ant_div_type == S0S1_SW_ANTDIV) {
-+		if (default_ant == 0x0)
-+			HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x1210,0x800000);
-+		else
-+			HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x1214,0x800000);
-+		
-+		fat_tab->rx_idle_ant = ant;
-+	}else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
-+		odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
-+		/*@Default RX*/
-+		odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
-+		/*@Optional RX*/
-+		odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
-+		/*@Default TX*/
-+		fat_tab->rx_idle_ant = ant;
-+	}
-+}
-+#endif
-+
-+#if (RTL8721D_SUPPORT == 1)
-+
-+void odm_update_rx_idle_ant_8721d(void *dm_void, u8 ant, u32 default_ant,
-+				  u32 optional_ant)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
-+	/*@Default RX*/
-+	odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
-+	/*@Optional RX*/
-+	odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
-+	/*@Default TX*/
-+	fat_tab->rx_idle_ant = ant;
-+}
-+
-+void odm_trx_hw_ant_div_init_8721d(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[8721D] AntDiv_Init =>  ant_div_type=[CG_TRX_HW_ANTDIV]\n");
-+
-+	/*@BT Coexistence*/
-+	/*@keep antsel_map when GNT_BT = 1*/
-+	odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
-+	/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
-+	odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
-+	/* @Disable hw antsw & fast_train.antsw when BT TX/RX */
-+	odm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c);
-+
-+	switch (dm->antdiv_gpio) {
-+	case ANTDIV_GPIO_PA2PA4: {
-+		PAD_CMD(_PA_2, ENABLE);
-+		Pinmux_Config(_PA_2, PINMUX_FUNCTION_RFE);
-+		PAD_CMD(_PA_4, ENABLE);
-+		Pinmux_Config(_PA_4, PINMUX_FUNCTION_RFE);
-+		break;
-+	}
-+	case ANTDIV_GPIO_PA5PA6: {
-+		PAD_CMD(_PA_5, ENABLE);
-+		Pinmux_Config(_PA_5, PINMUX_FUNCTION_RFE);
-+		PAD_CMD(_PA_6, ENABLE);
-+		Pinmux_Config(_PA_6, PINMUX_FUNCTION_RFE);
-+		break;
-+	}
-+	case ANTDIV_GPIO_PA12PA13: {
-+		PAD_CMD(_PA_12, ENABLE);
-+		Pinmux_Config(_PA_12, PINMUX_FUNCTION_RFE);
-+		PAD_CMD(_PA_13, ENABLE);
-+		Pinmux_Config(_PA_13, PINMUX_FUNCTION_RFE);
-+		break;
-+	}
-+	case ANTDIV_GPIO_PA14PA15: {
-+		PAD_CMD(_PA_14, ENABLE);
-+		Pinmux_Config(_PA_14, PINMUX_FUNCTION_RFE);
-+		PAD_CMD(_PA_15, ENABLE);
-+		Pinmux_Config(_PA_15, PINMUX_FUNCTION_RFE);
-+		break;
-+	}
-+	case ANTDIV_GPIO_PA16PA17: {
-+		PAD_CMD(_PA_16, ENABLE);
-+		Pinmux_Config(_PA_16, PINMUX_FUNCTION_RFE);
-+		PAD_CMD(_PA_17, ENABLE);
-+		Pinmux_Config(_PA_17, PINMUX_FUNCTION_RFE);
-+		break;
-+	}
-+	case ANTDIV_GPIO_PB1PB2: {
-+		PAD_CMD(_PB_1, ENABLE);
-+		Pinmux_Config(_PB_1, PINMUX_FUNCTION_RFE);
-+		PAD_CMD(_PB_2, ENABLE);
-+		Pinmux_Config(_PB_2, PINMUX_FUNCTION_RFE);
-+		break;
-+	}
-+	case ANTDIV_GPIO_PB26PB29: {
-+		PAD_CMD(_PB_26, ENABLE);
-+		Pinmux_Config(_PB_26, PINMUX_FUNCTION_RFE);
-+		PAD_CMD(_PB_29, ENABLE);
-+		Pinmux_Config(_PB_29, PINMUX_FUNCTION_RFE);
-+		break;
-+	}
-+	case ANTDIV_GPIO_PB1PB2PB26:{
-+		PAD_CMD(_PB_1, ENABLE);
-+		Pinmux_Config(_PB_1, PINMUX_FUNCTION_RFE);
-+		PAD_CMD(_PB_2, ENABLE);
-+		Pinmux_Config(_PB_2, PINMUX_FUNCTION_RFE);
-+		PAD_CMD(_PB_26, ENABLE);
-+		Pinmux_Config(_PB_26, PINMUX_FUNCTION_RFE);
-+		break;
-+	}
-+	default: {
-+	}
-+	}
-+
-+	if (dm->antdiv_gpio == ANTDIV_GPIO_PA12PA13 ||
-+	    dm->antdiv_gpio == ANTDIV_GPIO_PA14PA15 ||
-+	    dm->antdiv_gpio == ANTDIV_GPIO_PA16PA17 ||
-+	    dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2) {
-+		/* ANT_SEL_P, ANT_SEL_N */
-+		odm_set_bb_reg(dm, R_0x930, 0xF, 8);
-+		odm_set_bb_reg(dm, R_0x930, 0xF0, 8);
-+		odm_set_bb_reg(dm, R_0x92c, BIT(1) | BIT(0), 2);
-+		odm_set_bb_reg(dm, R_0x944, 0x00000003, 0x3);
-+	} else if (dm->antdiv_gpio == ANTDIV_GPIO_PA2PA4 ||
-+		   dm->antdiv_gpio == ANTDIV_GPIO_PA5PA6 ||
-+		   dm->antdiv_gpio == ANTDIV_GPIO_PB26PB29) {
-+		/* TRSW_P, TRSW_N */
-+		odm_set_bb_reg(dm, R_0x930, 0xF00, 8);
-+		odm_set_bb_reg(dm, R_0x930, 0xF000, 8);
-+		odm_set_bb_reg(dm, R_0x92c, BIT(3) | BIT(2), 2);
-+		odm_set_bb_reg(dm, R_0x944, 0x0000000C, 0x3); 	
-+	}
-+	else if(dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2PB26){
-+              /* 3 antenna diversity for AmebaD only */
-+		odm_set_bb_reg(dm, R_0x930, 0xF, 8);
-+		odm_set_bb_reg(dm, R_0x930, 0xF0, 9);
-+		odm_set_bb_reg(dm, R_0x930, 0xF00,0xa); /* set the RFE control table to select antenna*/
-+		odm_set_bb_reg(dm, R_0x944, 0x00000007, 0x7);
-+	}
-+
-+	u32 sysreg208 = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0);
-+
-+	sysreg208 |= BIT(28);
-+	HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0, sysreg208);
-+
-+	u32 sysreg344 =
-+		      HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL);
-+
-+	sysreg344 |= BIT(9);
-+	HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);
-+
-+	u32 sysreg280 = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0);
-+
-+	sysreg280 |= 0x7;
-+	HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0, sysreg280);
-+
-+	sysreg344 |= BIT(8);
-+	HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);
-+
-+	sysreg344 |= BIT(0);
-+	HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344);
-+
-+	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
-+	odm_set_bb_reg(dm, R_0x804, 0xF00, 1); /* r_keep_rfpin */
-+
-+	/*PTA setting: WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL)*/
-+	/*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/
-+	/*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/
-+	/*@GNT_WL tx*/
-+	odm_set_bb_reg(dm, R_0x950, BIT(29), 0);
-+
-+	/*@Mapping Table*/
-+	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
-+	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
-+	if (dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2PB26) {
-+		odm_set_bb_reg(dm, R_0x914, 0x00000F, 0x1);
-+		odm_set_bb_reg(dm, R_0x914, 0x000F00, 0x2);
-+		odm_set_bb_reg(dm, R_0x914, 0x0F0000, 0x4);
-+	}
-+	/* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */
-+	/* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */
-+
-+	/* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */
-+	odm_set_bb_reg(dm, R_0xccc, BIT(12), 0);
-+	/* @Low-to-High threshold for WLBB_SEL_RF_ON */
-+	/*when OFDM enable */
-+	odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01);
-+	/* @High-to-Low threshold for WLBB_SEL_RF_ON */
-+	/* when OFDM enable */
-+	odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0);
-+	/* @b Low-to-High threshold for WLBB_SEL_RF_ON*/
-+	/*when OFDM disable ( only CCK ) */
-+	odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06);
-+	/* @High-to-Low threshold for WLBB_SEL_RF_ON*/
-+	/* when OFDM disable ( only CCK ) */
-+	odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00);
-+
-+	/*OFDM HW AntDiv Parameters*/
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0);
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00);
-+	odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04);
-+
-+	/*@CCK HW AntDiv Parameters*/
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 0);
-+	odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0);
-+
-+	odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf);
-+	odm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8);
-+	odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1);
-+	odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0);
-+	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1);
-+
-+	/*@disable antenna training	*/
-+	odm_set_bb_reg(dm, R_0xe08, BIT(16), 0);
-+	odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
-+}
-+#endif
-+
-+void odm_stop_antenna_switch_dm(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	/* @disable ODM antenna diversity */
-+	dm->support_ability &= ~ODM_BB_ANT_DIV;
-+#if (RTL8710C_SUPPORT == 1)
-+	dm->support_ability |= ODM_BB_ANT_DIV;
-+#endif
-+	if (fat_tab->div_path_type == ANT_PATH_A)
-+		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
-+	else if (fat_tab->div_path_type == ANT_PATH_B)
-+		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
-+	else if (fat_tab->div_path_type == ANT_PATH_AB)
-+		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
-+	odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "STOP Antenna Diversity\n");
-+}
-+
-+void phydm_enable_antenna_diversity(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	dm->support_ability |= ODM_BB_ANT_DIV;
-+	dm->antdiv_select = 0;
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "AntDiv is enabled & Re-Init AntDiv\n");
-+	odm_antenna_diversity_init(dm);
-+}
-+
-+void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C,...*/)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type == ODM_RTL8723B) {
-+		if (ant_setting == 0) /* @ant A*/
-+			odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000000);
-+		else if (ant_setting == 1)
-+			odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000280);
-+	} else if (dm->support_ic_type == ODM_RTL8723D) {
-+		if (ant_setting == 0) /* @ant A*/
-+			odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0000);
-+		else if (ant_setting == 1)
-+			odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0280);
-+	}
-+}
-+
-+/* ****************************************************** */
-+
-+void odm_sw_ant_div_rest_after_link(void *dm_void)
-+{
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	u32 i;
-+
-+	if (dm->ant_div_type == S0S1_SW_ANTDIV) {
-+		swat_tab->try_flag = SWAW_STEP_INIT;
-+		swat_tab->rssi_trying = 0;
-+		swat_tab->double_chk_flag = 0;
-+		fat_tab->rx_idle_ant = MAIN_ANT;
-+
-+		for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
-+			phydm_antdiv_reset_statistic(dm, i);
-+	}
-+
-+#endif
-+}
-+
-+void phydm_n_on_off(void *dm_void, u8 swch, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	if (path == ANT_PATH_A) {
-+		odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
-+	} else if (path == ANT_PATH_B) {
-+		odm_set_bb_reg(dm, R_0xc58, BIT(7), swch);
-+	} else if (path == ANT_PATH_AB) {
-+		odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
-+		odm_set_bb_reg(dm, R_0xc58, BIT(7), swch);
-+	}
-+	odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
-+#if (RTL8723D_SUPPORT == 1)
-+	/*@Mingzhi 2017-05-08*/
-+	if (dm->support_ic_type == ODM_RTL8723D) {
-+		if (swch == ANTDIV_ON) {
-+			odm_set_bb_reg(dm, R_0xce0, BIT(1), 1);
-+			odm_set_bb_reg(dm, R_0x948, BIT(6), 1);
-+			/*@1:HW ctrl  0:SW ctrl*/
-+		} else {
-+			odm_set_bb_reg(dm, R_0xce0, BIT(1), 0);
-+			odm_set_bb_reg(dm, R_0x948, BIT(6), 0);
-+			/*@1:HW ctrl  0:SW ctrl*/
-+		}
-+	}
-+#endif
-+}
-+
-+void phydm_ac_on_off(void *dm_void, u8 swch, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	if (dm->support_ic_type & ODM_RTL8812) {
-+		odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
-+		/* OFDM AntDiv function block enable */
-+		odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
-+		/* @CCK AntDiv function block enable */
-+	} else if (dm->support_ic_type & ODM_RTL8822B) {
-+		odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
-+		odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
-+		if (path == ANT_PATH_A) {
-+			odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
-+		} else if (path == ANT_PATH_B) {
-+			odm_set_bb_reg(dm, R_0xe50, BIT(7), swch);
-+		} else if (path == ANT_PATH_AB) {
-+			odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
-+			odm_set_bb_reg(dm, R_0xe50, BIT(7), swch);
-+		}
-+	} else {
-+		odm_set_bb_reg(dm, R_0x8d4, BIT(24), swch);
-+		/* OFDM AntDiv function block enable */
-+
-+		if (dm->cut_version >= ODM_CUT_C &&
-+		    dm->support_ic_type == ODM_RTL8821 &&
-+		    dm->ant_div_type != S0S1_SW_ANTDIV) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n",
-+				  (swch == ANTDIV_ON) ? "ON" : "OFF");
-+			odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
-+			odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
-+			/* @CCK AntDiv function block enable */
-+		} else {
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n",
-+				  (swch == ANTDIV_ON) ? "ON" : "OFF");
-+			odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
-+			odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
-+			/* @CCK AntDiv function block enable */
-+		}
-+	}
-+}
-+
-+void phydm_jgr3_on_off(void *dm_void, u8 swch, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	odm_set_bb_reg(dm, R_0x8a0, BIT(17), swch);
-+	/* OFDM AntDiv function block enable */
-+	odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
-+	/* @CCK AntDiv function block enable */
-+}
-+
-+void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	if (fat_tab->ant_div_on_off != swch) {
-+		if (dm->ant_div_type == S0S1_SW_ANTDIV)
-+			return;
-+
-+		if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "(( Turn %s )) N-Series HW-AntDiv block\n",
-+				  (swch == ANTDIV_ON) ? "ON" : "OFF");
-+			phydm_n_on_off(dm, swch, path);
-+
-+		} else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "(( Turn %s )) AC-Series HW-AntDiv block\n",
-+				  (swch == ANTDIV_ON) ? "ON" : "OFF");
-+			phydm_ac_on_off(dm, swch, path);
-+		} else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "(( Turn %s )) JGR3 HW-AntDiv block\n",
-+				  (swch == ANTDIV_ON) ? "ON" : "OFF");
-+			phydm_jgr3_on_off(dm, swch, path);
-+		}
-+	}
-+	fat_tab->ant_div_on_off = swch;
-+}
-+
-+void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	u8 enable;
-+
-+	if (fat_tab->b_fix_tx_ant == NO_FIX_TX_ANT)
-+		enable = (swch == TX_BY_DESC) ? 1 : 0;
-+	else
-+		enable = 0; /*@Force TX by Reg*/
-+
-+	if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
-+		if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
-+			odm_set_bb_reg(dm, R_0x80c, BIT(21), enable);
-+		else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
-+			odm_set_bb_reg(dm, R_0x900, BIT(18), enable);
-+		else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT)
-+			odm_set_bb_reg(dm, R_0x186c, BIT(1), enable);
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[AntDiv] TX_Ant_BY (( %s ))\n",
-+			  (enable == TX_BY_DESC) ? "DESC" : "REG");
-+	}
-+}
-+
-+void phydm_antdiv_reset_statistic(void *dm_void, u32 macid)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	fat_tab->main_sum[macid] = 0;
-+	fat_tab->aux_sum[macid] = 0;
-+	fat_tab->main_cnt[macid] = 0;
-+	fat_tab->aux_cnt[macid] = 0;
-+	fat_tab->main_sum_cck[macid] = 0;
-+	fat_tab->aux_sum_cck[macid] = 0;
-+	fat_tab->main_cnt_cck[macid] = 0;
-+	fat_tab->aux_cnt_cck[macid] = 0;
-+}
-+
-+void phydm_fast_training_enable(void *dm_void, u8 swch)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 enable;
-+
-+	if (swch == FAT_ON)
-+		enable = 1;
-+	else
-+		enable = 0;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "Fast ant Training_en = ((%d))\n", enable);
-+
-+	if (dm->support_ic_type == ODM_RTL8188E) {
-+		odm_set_bb_reg(dm, R_0xe08, BIT(16), enable);
-+			/*@enable fast training*/
-+	} else if (dm->support_ic_type == ODM_RTL8192E) {
-+		odm_set_bb_reg(dm, R_0xb34, BIT(28), enable);
-+			/*@enable fast training (path-A)*/
-+#if 0
-+		odm_set_bb_reg(dm, R_0xb34, BIT(29), enable);
-+			/*enable fast training (path-B)*/
-+#endif
-+	} else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) {
-+		odm_set_bb_reg(dm, R_0x900, BIT(19), enable);
-+			/*@enable fast training */
-+	}
-+}
-+
-+void phydm_keep_rx_ack_ant_by_tx_ant_time(void *dm_void, u32 time)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	/* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/
-+	if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
-+		odm_set_bb_reg(dm, R_0xe20, 0xf00000, time);
-+	else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
-+		odm_set_bb_reg(dm, R_0x818, 0xf00000, time);
-+}
-+
-+void phydm_update_rx_idle_ac(void *dm_void, u8 ant, u32 default_ant,
-+			     u32 optional_ant, u32 default_tx_ant)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	u16 value16 = odm_read_2byte(dm, ODM_REG_TRMUX_11AC + 2);
-+	/* @2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to  */
-+	/* @prevnt incorrect 0xc08 bit0-15.We still not know why it is changed*/
-+	value16 &= ~(BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(7) | BIT(6) |
-+		   BIT(5) | BIT(4) | BIT(3));
-+	value16 |= ((u16)default_ant << 3);
-+	value16 |= ((u16)optional_ant << 6);
-+	value16 |= ((u16)default_tx_ant << 9);
-+	odm_write_2byte(dm, ODM_REG_TRMUX_11AC + 2, value16);
-+#if 0
-+	odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0x380000, default_ant);
-+		/* @Default RX */
-+	odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0x1c00000, optional_ant);
-+		/* Optional RX */
-+	odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0xe000000, default_ant);
-+		/* @Default TX */
-+#endif
-+}
-+
-+void phydm_update_rx_idle_n(void *dm_void, u8 ant, u32 default_ant,
-+			    u32 optional_ant, u32 default_tx_ant)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 value32;
-+
-+	if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) {
-+		odm_set_bb_reg(dm, R_0xb38, 0x38, default_ant);
-+			/* @Default RX */
-+		odm_set_bb_reg(dm, R_0xb38, 0x1c0, optional_ant);
-+			/* Optional RX */
-+		odm_set_bb_reg(dm, R_0x860, 0x7000, default_ant);
-+			/* @Default TX */
-+#if (RTL8723B_SUPPORT == 1)
-+	} else if (dm->support_ic_type == ODM_RTL8723B) {
-+		value32 = odm_get_bb_reg(dm, R_0x948, 0xFFF);
-+
-+		if (value32 != 0x280)
-+			odm_update_rx_idle_ant_8723b(dm, ant, default_ant,
-+						     optional_ant);
-+		else
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n");
-+#endif
-+
-+#if (RTL8723D_SUPPORT == 1) /*@Mingzhi 2017-05-08*/
-+	} else if (dm->support_ic_type == ODM_RTL8723D) {
-+		phydm_set_tx_ant_pwr_8723d(dm, ant);
-+		odm_update_rx_idle_ant_8723d(dm, ant, default_ant,
-+					     optional_ant);
-+#endif
-+
-+#if (RTL8721D_SUPPORT == 1)
-+	} else if (dm->support_ic_type == ODM_RTL8721D) {
-+		odm_update_rx_idle_ant_8721d(dm, ant, default_ant,
-+					     optional_ant);
-+#endif
-+
-+#if (RTL8710C_SUPPORT == 1)
-+	} else if (dm->support_ic_type == ODM_RTL8710C) {
-+		odm_update_rx_idle_ant_8710c(dm, ant, default_ant,
-+					     optional_ant);
-+#endif
-+
-+	} else {
-+/*@8188E & 8188F*/
-+/*@		if (dm->support_ic_type == ODM_RTL8723D) {*/
-+/*#if (RTL8723D_SUPPORT == 1)*/
-+/*			phydm_set_tx_ant_pwr_8723d(dm, ant);*/
-+/*#endif*/
-+/*		}*/
-+#if (RTL8188F_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8188F)
-+			phydm_update_rx_idle_antenna_8188F(dm, default_ant);
-+#endif
-+
-+		odm_set_bb_reg(dm, R_0x864, 0x38, default_ant);/*@Default RX*/
-+		odm_set_bb_reg(dm, R_0x864, 0x1c0, optional_ant);
-+			/*Optional RX*/
-+		odm_set_bb_reg(dm, R_0x860, 0x7000, default_tx_ant);
-+			/*@Default TX*/
-+	}
-+}
-+
-+void phydm_update_rx_idle_jgr3(void *dm_void, u8 ant, u32 default_ant,
-+			       u32 optional_ant, u32 default_tx_ant)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 value32;
-+
-+	odm_set_bb_reg(dm, R_0x1884, 0xf0, default_ant);/*@Default RX*/
-+	odm_set_bb_reg(dm, R_0x1884, 0xf00, optional_ant);
-+		/*Optional RX*/
-+	odm_set_bb_reg(dm, R_0x1884, 0xf000, default_tx_ant);
-+		/*@Default TX*/
-+}
-+void odm_update_rx_idle_ant(void *dm_void, u8 ant)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	u32 default_ant, optional_ant, value32, default_tx_ant;
-+
-+	if (fat_tab->rx_idle_ant != ant) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ Update Rx-Idle-ant ] rx_idle_ant =%s\n",
-+			  (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
-+
-+		if (!(dm->support_ic_type & ODM_RTL8723B))
-+			fat_tab->rx_idle_ant = ant;
-+
-+		if (ant == MAIN_ANT) {
-+			default_ant = ANT1_2G;
-+			optional_ant = ANT2_2G;
-+		} else {
-+			default_ant = ANT2_2G;
-+			optional_ant = ANT1_2G;
-+		}
-+
-+		if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
-+			default_tx_ant = (fat_tab->b_fix_tx_ant ==
-+					 FIX_TX_AT_MAIN) ? 0 : 1;
-+		else
-+			default_tx_ant = default_ant;
-+
-+		if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
-+			phydm_update_rx_idle_n(dm, ant, default_ant,
-+					       optional_ant, default_tx_ant);
-+		} else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
-+			phydm_update_rx_idle_ac(dm, ant, default_ant,
-+						optional_ant, default_tx_ant);
-+		} else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT) {
-+			phydm_update_rx_idle_jgr3(dm, ant, default_ant,
-+						  optional_ant, default_tx_ant);
-+		}
-+		/*PathA Resp Tx*/
-+		if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B |
-+		    ODM_RTL8814A | ODM_RTL8195B))
-+			odm_set_mac_reg(dm, R_0x6d8, 0x7, default_tx_ant);
-+		else if (dm->support_ic_type == ODM_RTL8188E)
-+			odm_set_mac_reg(dm, R_0x6d8, 0xc0, default_tx_ant);
-+		else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT)
-+			odm_set_mac_reg(dm, R_0x6f8, 0xf, default_tx_ant);
-+		else
-+			odm_set_mac_reg(dm, R_0x6d8, 0x700, default_tx_ant);
-+
-+	} else { /* @fat_tab->rx_idle_ant == ant */
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ Stay in Ori-ant ]  rx_idle_ant =%s\n",
-+			  (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
-+		fat_tab->rx_idle_ant = ant;
-+	}
-+}
-+
-+#if (RTL8721D_SUPPORT)
-+void odm_update_rx_idle_ant_sp3t(void *dm_void, u8 ant) /* added by Jiao Qi on May.25,2020, for AmebaD SP3T only */
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	u32 default_ant, optional_ant, value32, default_tx_ant;
-+
-+	if (!(dm->support_ic_type & ODM_RTL8723B))
-+		fat_tab->rx_idle_ant = ant;
-+
-+		default_ant  = fat_tab->ant_idx_vec[0]-1;
-+		optional_ant = fat_tab->ant_idx_vec[1]-1;
-+
-+		if(fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
-+			default_tx_ant = (fat_tab->b_fix_tx_ant ==
-+					 FIX_TX_AT_MAIN) ? 0 : 1;
-+		else
-+			default_tx_ant = default_ant;
-+
-+		odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
-+		/*@Default RX*/
-+		odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
-+		/*@Optional RX*/
-+		odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
-+		/*@Default TX*/
-+		
-+		/*PathA Resp Tx*/
-+		if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B |
-+		    ODM_RTL8814A))
-+			odm_set_mac_reg(dm, R_0x6d8, 0x7, default_tx_ant);
-+		else if (dm->support_ic_type == ODM_RTL8188E)
-+			odm_set_mac_reg(dm, R_0x6d8, 0xc0, default_tx_ant);
-+		else
-+			odm_set_mac_reg(dm, R_0x6d8, 0x700, default_tx_ant);
-+
-+}
-+#endif
-+void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	u32 default_ant, optional_ant, value32, default_tx_ant;
-+
-+	if (fat_tab->rx_idle_ant2 != ant) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ Update Rx-Idle-ant2 ] rx_idle_ant2 =%s\n",
-+			  (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
-+		if (ant == MAIN_ANT) {
-+			default_ant = ANT1_2G;
-+			optional_ant = ANT2_2G;
-+		} else {
-+			default_ant = ANT2_2G;
-+			optional_ant = ANT1_2G;
-+		}
-+
-+		if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
-+			default_tx_ant = (fat_tab->b_fix_tx_ant ==
-+					  FIX_TX_AT_MAIN) ? 0 : 1;
-+		else
-+			default_tx_ant = default_ant;
-+		if (dm->support_ic_type & ODM_RTL8822B) {
-+			u16 v16 = odm_read_2byte(dm, ODM_REG_ANT_11AC_B + 2);
-+
-+			v16 &= ~(0xff8);/*0xE08[11:3]*/
-+			v16 |= ((u16)default_ant << 3);
-+			v16 |= ((u16)optional_ant << 6);
-+			v16 |= ((u16)default_tx_ant << 9);
-+			odm_write_2byte(dm, ODM_REG_ANT_11AC_B + 2, v16);
-+			odm_set_mac_reg(dm, R_0x6d8, 0x38, default_tx_ant);
-+			/*PathB Resp Tx*/
-+		}
-+	} else {
-+		/* fat_tab->rx_idle_ant2 == ant */
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[Stay Ori Ant] rx_idle_ant2 = %s\n",
-+			  (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
-+		fat_tab->rx_idle_ant2 = ant;
-+	}
-+}
-+
-+void phydm_set_antdiv_val(void *dm_void, u32 *val_buf,	u8 val_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ability & ODM_BB_ANT_DIV))
-+		return;
-+
-+	if (val_len != 1) {
-+		PHYDM_DBG(dm, ODM_COMP_API, "[Error][antdiv]Need val_len=1\n");
-+		return;
-+	}
-+
-+	odm_update_rx_idle_ant(dm, (u8)(*val_buf));
-+}
-+
-+void odm_update_tx_ant(void *dm_void, u8 ant, u32 mac_id)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	u8 tx_ant;
-+
-+	if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
-+		ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ?
-+		       MAIN_ANT : AUX_ANT;
-+
-+	if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
-+		tx_ant = ant;
-+	else {
-+		if (ant == MAIN_ANT)
-+			tx_ant = ANT1_2G;
-+		else
-+			tx_ant = ANT2_2G;
-+	}
-+#if (RTL8721D_SUPPORT)
-+	if (dm->antdiv_gpio != ANTDIV_GPIO_PB1PB2PB26) {
-+		if (ant == MAIN_ANT)
-+			tx_ant = ANT1_2G;
-+		else
-+			tx_ant = ANT2_2G;
-+		}
-+	else		
-+		tx_ant = fat_tab->ant_idx_vec[0]-1;
-+#endif
-+	fat_tab->antsel_a[mac_id] = tx_ant & BIT(0);
-+	fat_tab->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1;
-+	fat_tab->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[Set TX-DESC value]: mac_id:(( %d )),  tx_ant = (( %s ))\n",
-+		  mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
-+#if 0
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "antsel_tr_mux=(( 3'b%d%d%d ))\n",
-+		  fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
-+		  fat_tab->antsel_a[mac_id]);
-+#endif
-+}
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+
-+void odm_bdc_init(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "\n[ BDC Initialization......]\n");
-+	dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
-+	dm_bdc_table->bdc_mode = BDC_MODE_NULL;
-+	dm_bdc_table->bdc_try_flag = 0;
-+	dm_bdc_table->bd_ccoex_type_wbfer = 0;
-+	dm->bdc_holdstate = 0xff;
-+
-+	if (dm->support_ic_type == ODM_RTL8192E) {
-+		odm_set_bb_reg(dm, R_0xd7c, 0x0FFFFFFF, 0x1081008);
-+		odm_set_bb_reg(dm, R_0xd80, 0x0FFFFFFF, 0);
-+	} else if (dm->support_ic_type == ODM_RTL8812) {
-+		odm_set_bb_reg(dm, R_0x9b0, 0x0FFFFFFF, 0x1081008);
-+			/* @0x9b0[30:0] = 01081008 */
-+		odm_set_bb_reg(dm, R_0x9b4, 0x0FFFFFFF, 0);
-+			/* @0x9b4[31:0] = 00000000 */
-+	}
-+}
-+
-+void odm_CSI_on_off(
-+	void *dm_void,
-+	u8 CSI_en)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	if (CSI_en == CSI_ON) {
-+		if (dm->support_ic_type == ODM_RTL8192E)
-+			odm_set_mac_reg(dm, R_0xd84, BIT(11), 1);
-+				/* @0xd84[11]=1 */
-+		else if (dm->support_ic_type == ODM_RTL8812)
-+			odm_set_mac_reg(dm, R_0x9b0, BIT(31), 1);
-+				/* @0x9b0[31]=1 */
-+
-+	} else if (CSI_en == CSI_OFF) {
-+		if (dm->support_ic_type == ODM_RTL8192E)
-+			odm_set_mac_reg(dm, R_0xd84, BIT(11), 0);
-+				/* @0xd84[11]=0 */
-+		else if (dm->support_ic_type == ODM_RTL8812)
-+			odm_set_mac_reg(dm, R_0x9b0, BIT(31), 0);
-+				/* @0x9b0[31]=0 */
-+	}
-+}
-+
-+void odm_bd_ccoex_type_with_bfer_client(
-+	void *dm_void,
-+	u8 swch)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
-+	u8 bd_ccoex_type_wbfer;
-+
-+	if (swch == DIVON_CSIOFF) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[BDCcoexType: 1] {DIV,CSI} ={1,0}\n");
-+		bd_ccoex_type_wbfer = 1;
-+
-+		if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
-+			odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
-+			odm_CSI_on_off(dm, CSI_OFF);
-+			dm_bdc_table->bd_ccoex_type_wbfer = 1;
-+		}
-+	} else if (swch == DIVOFF_CSION) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[BDCcoexType: 2] {DIV,CSI} ={0,1}\n");
-+		bd_ccoex_type_wbfer = 2;
-+
-+		if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
-+			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
-+			odm_CSI_on_off(dm, CSI_ON);
-+			dm_bdc_table->bd_ccoex_type_wbfer = 2;
-+		}
-+	}
-+}
-+
-+void odm_bf_ant_div_mode_arbitration(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
-+	u8 current_bdc_mode;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "\n");
-+
-+	/* @2 mode 1 */
-+	if (dm_bdc_table->num_txbfee_client != 0 &&
-+	    dm_bdc_table->num_txbfer_client == 0) {
-+		current_bdc_mode = BDC_MODE_1;
-+
-+		if (current_bdc_mode != dm_bdc_table->bdc_mode) {
-+			dm_bdc_table->bdc_mode = BDC_MODE_1;
-+			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
-+			dm_bdc_table->bdc_rx_idle_update_counter = 1;
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode1 ))\n");
-+		}
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[Antdiv + BF coextance mode] : (( Mode1 ))\n");
-+	}
-+	/* @2 mode 2 */
-+	else if ((dm_bdc_table->num_txbfee_client == 0) &&
-+		 (dm_bdc_table->num_txbfer_client != 0)) {
-+		current_bdc_mode = BDC_MODE_2;
-+
-+		if (current_bdc_mode != dm_bdc_table->bdc_mode) {
-+			dm_bdc_table->bdc_mode = BDC_MODE_2;
-+			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
-+			dm_bdc_table->bdc_try_flag = 0;
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode2 ))\n");
-+		}
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[Antdiv + BF coextance mode] : (( Mode2 ))\n");
-+	}
-+	/* @2 mode 3 */
-+	else if ((dm_bdc_table->num_txbfee_client != 0) &&
-+		 (dm_bdc_table->num_txbfer_client != 0)) {
-+		current_bdc_mode = BDC_MODE_3;
-+
-+		if (current_bdc_mode != dm_bdc_table->bdc_mode) {
-+			dm_bdc_table->bdc_mode = BDC_MODE_3;
-+			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
-+			dm_bdc_table->bdc_try_flag = 0;
-+			dm_bdc_table->bdc_rx_idle_update_counter = 1;
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode3 ))\n");
-+		}
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[Antdiv + BF coextance mode] : (( Mode3 ))\n");
-+	}
-+	/* @2 mode 4 */
-+	else if ((dm_bdc_table->num_txbfee_client == 0) &&
-+		 (dm_bdc_table->num_txbfer_client == 0)) {
-+		current_bdc_mode = BDC_MODE_4;
-+
-+		if (current_bdc_mode != dm_bdc_table->bdc_mode) {
-+			dm_bdc_table->bdc_mode = BDC_MODE_4;
-+			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode4 ))\n");
-+		}
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[Antdiv + BF coextance mode] : (( Mode4 ))\n");
-+	}
-+#endif
-+}
-+
-+void odm_div_train_state_setting(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "\n*****[S T A R T ]*****  [2-0. DIV_TRAIN_STATE]\n");
-+	dm_bdc_table->bdc_try_counter = 2;
-+	dm_bdc_table->bdc_try_flag = 1;
-+	dm_bdc_table->BDC_state = bdc_bfer_train_state;
-+	odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
-+}
-+
-+void odm_bd_ccoex_bfee_rx_div_arbitration(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
-+	boolean stop_bf_flag;
-+	u8 bdc_active_mode;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "***{ num_BFee,  num_BFer, num_client}  = (( %d  ,  %d  ,  %d))\n",
-+		  dm_bdc_table->num_txbfee_client,
-+		  dm_bdc_table->num_txbfer_client, dm_bdc_table->num_client);
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "***{ num_BF_tars,  num_DIV_tars }  = ((  %d  ,  %d ))\n",
-+		  dm_bdc_table->num_bf_tar, dm_bdc_table->num_div_tar);
-+
-+	/* @2 [ MIB control ] */
-+	if (dm->bdc_holdstate == 2) {
-+		odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
-+		dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ BF STATE]\n");
-+		return;
-+	} else if (dm->bdc_holdstate == 1) {
-+		dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
-+		odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
-+		return;
-+	}
-+
-+	/* @------------------------------------------------------------ */
-+
-+	/* @2 mode 2 & 3 */
-+	if (dm_bdc_table->bdc_mode == BDC_MODE_2 ||
-+	    dm_bdc_table->bdc_mode == BDC_MODE_3) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "\n{ Try_flag,  Try_counter } = {  %d , %d  }\n",
-+			  dm_bdc_table->bdc_try_flag,
-+			  dm_bdc_table->bdc_try_counter);
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "BDCcoexType = (( %d ))\n\n",
-+			  dm_bdc_table->bd_ccoex_type_wbfer);
-+
-+		/* @All Client have Bfer-Cap------------------------------- */
-+		if (dm_bdc_table->num_txbfer_client == dm_bdc_table->num_client) {
-+			/* @BFer STA Only?: yes */
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "BFer STA only?  (( Yes ))\n");
-+			dm_bdc_table->bdc_try_flag = 0;
-+			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
-+			odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
-+			return;
-+		} else
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "BFer STA only?  (( No ))\n");
-+		if (dm_bdc_table->is_all_bf_sta_idle == false && dm_bdc_table->is_all_div_sta_idle == true) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "All DIV-STA are idle, but BF-STA not\n");
-+			dm_bdc_table->bdc_try_flag = 0;
-+			dm_bdc_table->BDC_state = bdc_bfer_train_state;
-+			odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
-+			return;
-+		} else if (dm_bdc_table->is_all_bf_sta_idle == true && dm_bdc_table->is_all_div_sta_idle == false) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "All BF-STA are idle, but DIV-STA not\n");
-+			dm_bdc_table->bdc_try_flag = 0;
-+			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
-+			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
-+			return;
-+		}
-+
-+		/* Select active mode-------------------------------------- */
-+		if (dm_bdc_table->num_bf_tar == 0) { /* Selsect_1,  Selsect_2 */
-+			if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "Select active mode (( 1 ))\n");
-+				dm_bdc_table->bdc_active_mode = 1;
-+			} else {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "Select active mode  (( 2 ))\n");
-+				dm_bdc_table->bdc_active_mode = 2;
-+			}
-+			dm_bdc_table->bdc_try_flag = 0;
-+			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
-+			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
-+			return;
-+		} else { /* num_bf_tar > 0 */
-+			if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "Select active mode (( 3 ))\n");
-+				dm_bdc_table->bdc_active_mode = 3;
-+				dm_bdc_table->bdc_try_flag = 0;
-+				dm_bdc_table->BDC_state = bdc_bfer_train_state;
-+				odm_bd_ccoex_type_with_bfer_client(dm,
-+								   DIVOFF_CSION)
-+								   ;
-+				return;
-+			} else { /* Selsect_4 */
-+				bdc_active_mode = 4;
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "Select active mode (( 4 ))\n");
-+
-+				if (bdc_active_mode != dm_bdc_table->bdc_active_mode) {
-+					dm_bdc_table->bdc_active_mode = 4;
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "Change to active mode (( 4 ))  &  return!!!\n");
-+					return;
-+				}
-+			}
-+		}
-+
-+#if 1
-+		if (dm->bdc_holdstate == 0xff) {
-+			dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
-+			odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
-+			return;
-+		}
-+#endif
-+
-+		/* @Does Client number changed ? ------------------------------- */
-+		if (dm_bdc_table->num_client != dm_bdc_table->pre_num_client) {
-+			dm_bdc_table->bdc_try_flag = 0;
-+			dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[  The number of client has been changed !!!]   return to (( BDC_DIV_TRAIN_STATE ))\n");
-+		}
-+		dm_bdc_table->pre_num_client = dm_bdc_table->num_client;
-+
-+		if (dm_bdc_table->bdc_try_flag == 0) {
-+			/* @2 DIV_TRAIN_STATE (mode 2-0) */
-+			if (dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE)
-+				odm_div_train_state_setting(dm);
-+			/* @2 BFer_TRAIN_STATE (mode 2-1) */
-+			else if (dm_bdc_table->BDC_state == bdc_bfer_train_state) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "*****[2-1. BFer_TRAIN_STATE ]*****\n");
-+
-+#if 0
-+				/* @if(dm_bdc_table->num_bf_tar==0) */
-+				/* @{ */
-+				/*	PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist?  : (( No )),   [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n"); */
-+				/*	odm_div_train_state_setting( dm); */
-+				/* @} */
-+				/* else */ /* num_bf_tar != 0 */
-+				/* @{ */
-+#endif
-+				dm_bdc_table->bdc_try_counter = 2;
-+				dm_bdc_table->bdc_try_flag = 1;
-+				dm_bdc_table->BDC_state = BDC_DECISION_STATE;
-+				odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "BF_tars exist?  : (( Yes )),   [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n");
-+				/* @} */
-+			}
-+			/* @2 DECISION_STATE (mode 2-2) */
-+			else if (dm_bdc_table->BDC_state == BDC_DECISION_STATE) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "*****[2-2. DECISION_STATE]*****\n");
-+#if 0
-+				/* @if(dm_bdc_table->num_bf_tar==0) */
-+				/* @{ */
-+				/*	ODM_AntDiv_Printk(("BF_tars exist?  : (( No )),   [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */
-+				/*	odm_div_train_state_setting( dm); */
-+				/* @} */
-+				/* else */ /* num_bf_tar != 0 */
-+				/* @{ */
-+#endif
-+				if (dm_bdc_table->BF_pass == false || dm_bdc_table->DIV_pass == false)
-+					stop_bf_flag = true;
-+				else
-+					stop_bf_flag = false;
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "BF_tars exist?  : (( Yes )),  {BF_pass, DIV_pass, stop_bf_flag }  = { %d, %d, %d }\n",
-+					  dm_bdc_table->BF_pass,
-+					  dm_bdc_table->DIV_pass, stop_bf_flag);
-+
-+				if (stop_bf_flag == true) { /* @DIV_en */
-+					dm_bdc_table->bdc_hold_counter = 10; /* @20 */
-+					odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
-+					dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ stop_bf_flag= ((true)),   BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
-+				} else { /* @BF_en */
-+					dm_bdc_table->bdc_hold_counter = 10; /* @20 */
-+					odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
-+					dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "[stop_bf_flag= ((false)),   BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n");
-+				}
-+				/* @} */
-+			}
-+			/* @2 BF-HOLD_STATE (mode 2-3) */
-+			else if (dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "*****[2-3. BF_HOLD_STATE ]*****\n");
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "bdc_hold_counter = (( %d ))\n",
-+					  dm_bdc_table->bdc_hold_counter);
-+
-+				if (dm_bdc_table->bdc_hold_counter == 1) {
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
-+					odm_div_train_state_setting(dm);
-+				} else {
-+					dm_bdc_table->bdc_hold_counter--;
-+
-+#if 0
-+					/* @if(dm_bdc_table->num_bf_tar==0) */
-+					/* @{ */
-+					/*	PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist?  : (( No )),   [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); */
-+					/*	odm_div_train_state_setting( dm); */
-+					/* @} */
-+					/* else */ /* num_bf_tar != 0 */
-+					/* @{ */
-+					/* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist?  : (( Yes ))\n"); */
-+#endif
-+					dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
-+					odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n");
-+					/* @} */
-+				}
-+			}
-+			/* @2 DIV-HOLD_STATE (mode 2-4) */
-+			else if (dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "*****[2-4. DIV_HOLD_STATE ]*****\n");
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "bdc_hold_counter = (( %d ))\n",
-+					  dm_bdc_table->bdc_hold_counter);
-+
-+				if (dm_bdc_table->bdc_hold_counter == 1) {
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
-+					odm_div_train_state_setting(dm);
-+				} else {
-+					dm_bdc_table->bdc_hold_counter--;
-+					dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
-+					odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
-+				}
-+			}
-+
-+		} else if (dm_bdc_table->bdc_try_flag == 1) {
-+			/* @2 Set Training counter */
-+			if (dm_bdc_table->bdc_try_counter > 1) {
-+				dm_bdc_table->bdc_try_counter--;
-+				if (dm_bdc_table->bdc_try_counter == 1)
-+					dm_bdc_table->bdc_try_flag = 0;
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV, "Training !!\n");
-+				/* return ; */
-+			}
-+		}
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "\n[end]\n");
-+
-+#endif /* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */
-+}
-+
-+#endif
-+#endif /* @#ifdef PHYDM_BEAMFORMING_SUPPORT*/
-+
-+#if (RTL8188E_SUPPORT == 1)
-+
-+void odm_rx_hw_ant_div_init_88e(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 value32;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+	/* @MAC setting */
-+	value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
-+	odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD,
-+			value32 | (BIT(23) | BIT(25)));
-+			/* Reg4C[25]=1, Reg4C[23]=1 for pin output */
-+	/* Pin Settings */
-+	odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
-+			/* reg870[8]=1'b0, reg870[9]=1'b0 */
-+			/* antsel antselb by HW */
-+	odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
-+			/* reg864[10]=1'b0 */ /* antsel2 by HW */
-+	odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1);
-+			/* regb2c[22]=1'b0 */ /* disable CS/CG switch */
-+	odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
-+			/* regb2c[31]=1'b1 */ /* output at CG only */
-+	/* OFDM Settings */
-+	odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
-+	/* @CCK Settings */
-+	odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
-+			/* @Fix CCK PHY status report issue */
-+	odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
-+			/* @CCK complete HW AntDiv within 64 samples */
-+
-+	odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001);
-+			/* @antenna mapping table */
-+
-+	fat_tab->enable_ctrl_frame_antdiv = 1;
-+}
-+
-+void odm_trx_hw_ant_div_init_88e(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 value32;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+	/* @MAC setting */
-+	value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
-+	odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD,
-+			value32 | (BIT(23) | BIT(25)));
-+			/* Reg4C[25]=1, Reg4C[23]=1 for pin output */
-+	/* Pin Settings */
-+	odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
-+			/* reg870[8]=1'b0, reg870[9]=1'b0 */
-+			/* antsel antselb by HW */
-+	odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
-+			/* reg864[10]=1'b0 */ /* antsel2 by HW */
-+	odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0);
-+			/* regb2c[22]=1'b0 */ /* disable CS/CG switch */
-+	odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
-+			/* regb2c[31]=1'b1 */ /* output at CG only */
-+	/* OFDM Settings */
-+	odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
-+	/* @CCK Settings */
-+	odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
-+			/* @Fix CCK PHY status report issue */
-+	odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
-+			/* @CCK complete HW AntDiv within 64 samples */
-+
-+	/* @antenna mapping table */
-+	if (!dm->is_mp_chip) { /* testchip */
-+		odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, 0x700, 1);
-+				/* Reg858[10:8]=3'b001 */
-+		odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, 0x3800, 2);
-+				/* Reg858[13:11]=3'b010 */
-+	} else /* @MPchip */
-+		odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201);
-+				/*Reg914=3'b010, Reg915=3'b001*/
-+
-+	fat_tab->enable_ctrl_frame_antdiv = 1;
-+}
-+
-+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+void odm_smart_hw_ant_div_init_88e(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 value32, i;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "***8188E AntDiv_Init =>  ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
-+
-+#if 0
-+	if (*dm->mp_mode == true) {
-+		PHYDM_DBG(dm, ODM_COMP_INIT, "dm->ant_div_type: %d\n",
-+			  dm->ant_div_type);
-+		return;
-+	}
-+#endif
-+
-+	fat_tab->train_idx = 0;
-+	fat_tab->fat_state = FAT_PREPARE_STATE;
-+
-+	dm->fat_comb_a = 5;
-+	dm->antdiv_intvl = 0x64; /* @100ms */
-+
-+	for (i = 0; i < 6; i++)
-+		fat_tab->bssid[i] = 0;
-+	for (i = 0; i < (dm->fat_comb_a); i++) {
-+		fat_tab->ant_sum_rssi[i] = 0;
-+		fat_tab->ant_rssi_cnt[i] = 0;
-+		fat_tab->ant_ave_rssi[i] = 0;
-+	}
-+
-+	/* @MAC setting */
-+	value32 = odm_get_mac_reg(dm, R_0x4c, MASKDWORD);
-+	odm_set_mac_reg(dm, R_0x4c, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
-+	value32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD);
-+	odm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
-+	/* value32 = platform_efio_read_4byte(adapter, 0x7B4); */
-+	/* platform_efio_write_4byte(adapter, 0x7b4, value32|BIT(18));	 */ /* append MACID in reponse packet */
-+
-+	/* @Match MAC ADDR */
-+	odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0);
-+	odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0);
-+
-+	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0		 */ /* antsel antselb by HW */
-+	odm_set_bb_reg(dm, R_0x864, BIT(10), 0); /* reg864[10]=1'b0	 */ /* antsel2 by HW */
-+	odm_set_bb_reg(dm, R_0xb2c, BIT(22), 0); /* regb2c[22]=1'b0	 */ /* disable CS/CG switch */
-+	odm_set_bb_reg(dm, R_0xb2c, BIT(31), 0); /* regb2c[31]=1'b1	 */ /* output at CS only */
-+	odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x000000a0);
-+
-+	/* @antenna mapping table */
-+	if (dm->fat_comb_a == 2) {
-+		if (!dm->is_mp_chip) { /* testchip */
-+			odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
-+			odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
-+		} else { /* @MPchip */
-+			odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 1);
-+			odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2);
-+		}
-+	} else {
-+		if (!dm->is_mp_chip) { /* testchip */
-+			odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 0); /* Reg858[10:8]=3'b000 */
-+			odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 1); /* Reg858[13:11]=3'b001 */
-+			odm_set_bb_reg(dm, R_0x878, BIT(16), 0);
-+			odm_set_bb_reg(dm, R_0x858, BIT(15) | BIT(14), 2); /* @(Reg878[0],Reg858[14:15])=3'b010 */
-+			odm_set_bb_reg(dm, R_0x878, BIT(19) | BIT(18) | BIT(17), 3); /* Reg878[3:1]=3b'011 */
-+			odm_set_bb_reg(dm, R_0x878, BIT(22) | BIT(21) | BIT(20), 4); /* Reg878[6:4]=3b'100 */
-+			odm_set_bb_reg(dm, R_0x878, BIT(25) | BIT(24) | BIT(23), 5); /* Reg878[9:7]=3b'101 */
-+			odm_set_bb_reg(dm, R_0x878, BIT(28) | BIT(27) | BIT(26), 6); /* Reg878[12:10]=3b'110 */
-+			odm_set_bb_reg(dm, R_0x878, BIT(31) | BIT(30) | BIT(29), 7); /* Reg878[15:13]=3b'111 */
-+		} else { /* @MPchip */
-+			odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 4); /* @0: 3b'000 */
-+			odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2); /* @1: 3b'001 */
-+			odm_set_bb_reg(dm, R_0x914, MASKBYTE2, 0); /* @2: 3b'010 */
-+			odm_set_bb_reg(dm, R_0x914, MASKBYTE3, 1); /* @3: 3b'011 */
-+			odm_set_bb_reg(dm, R_0x918, MASKBYTE0, 3); /* @4: 3b'100 */
-+			odm_set_bb_reg(dm, R_0x918, MASKBYTE1, 5); /* @5: 3b'101 */
-+			odm_set_bb_reg(dm, R_0x918, MASKBYTE2, 6); /* @6: 3b'110 */
-+			odm_set_bb_reg(dm, R_0x918, MASKBYTE3, 255); /* @7: 3b'111 */
-+		}
-+	}
-+
-+	/* @Default ant setting when no fast training */
-+	odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), 0); /* @Default RX */
-+	odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
-+	odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), 0); /* @Default TX */
-+
-+	/* @Enter Traing state */
-+	odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), (dm->fat_comb_a - 1)); /* reg864[2:0]=3'd6	 */ /* ant combination=reg864[2:0]+1 */
-+
-+#if 0
-+	/* SW Control */
-+	/* phy_set_bb_reg(adapter, 0x864, BIT10, 1); */
-+	/* phy_set_bb_reg(adapter, 0x870, BIT9, 1); */
-+	/* phy_set_bb_reg(adapter, 0x870, BIT8, 1); */
-+	/* phy_set_bb_reg(adapter, 0x864, BIT11, 1); */
-+	/* phy_set_bb_reg(adapter, 0x860, BIT9, 0); */
-+	/* phy_set_bb_reg(adapter, 0x860, BIT8, 0); */
-+#endif
-+}
-+#endif
-+
-+#endif /* @#if (RTL8188E_SUPPORT == 1) */
-+
-+#if (RTL8192E_SUPPORT == 1)
-+void odm_rx_hw_ant_div_init_92e(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+#if 0
-+	if (*dm->mp_mode == true) {
-+		odm_ant_div_on_off(dm, ANTDIV_OFF);
-+		odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
-+		/* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */
-+		odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);
-+		/* @1:CG, 0:CS */
-+		return;
-+	}
-+#endif
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+	/* Pin Settings */
-+	odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
-+		/* reg870[8]=1'b0,   antsel is controled by HWs */
-+	odm_set_bb_reg(dm, R_0xc50, BIT(8), 1);
-+		/* regc50[8]=1'b1    CS/CG switching is controled by HWs*/
-+
-+	/* @Mapping table */
-+	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
-+		/* @antenna mapping table */
-+
-+	/* OFDM Settings */
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
-+
-+	/* @CCK Settings */
-+	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
-+		/* Select which path to receive for CCK_1 & CCK_2 */
-+	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
-+		/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+		/* @Fix CCK PHY status report issue */
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
-+		/* @CCK complete HW AntDiv within 64 samples */
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	phydm_evm_sw_antdiv_init(dm);
-+#endif
-+}
-+
-+void odm_trx_hw_ant_div_init_92e(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if 0
-+	if (*dm->mp_mode == true) {
-+		odm_ant_div_on_off(dm, ANTDIV_OFF);
-+		odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */
-+		odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);  /* @1:CG, 0:CS */
-+		return;
-+	}
-+#endif
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+	/* @3 --RFE pin setting--------- */
-+	/* @[MAC] */
-+	odm_set_mac_reg(dm, R_0x38, BIT(11), 1);
-+		/* @DBG PAD Driving control (GPIO 8) */
-+	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */
-+	odm_set_mac_reg(dm, R_0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */
-+	/* @[BB] */
-+	odm_set_bb_reg(dm, R_0x944, BIT(3), 1); /* RFE_buffer */
-+	odm_set_bb_reg(dm, R_0x944, BIT(8), 1);
-+	odm_set_bb_reg(dm, R_0x940, BIT(7) | BIT(6), 0x0);
-+		/* r_rfe_path_sel_   (RFE_CTRL_3) */
-+	odm_set_bb_reg(dm, R_0x940, BIT(17) | BIT(16), 0x0);
-+		/* r_rfe_path_sel_   (RFE_CTRL_8) */
-+	odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer */
-+	odm_set_bb_reg(dm, R_0x92c, BIT(3), 0); /* rfe_inv  (RFE_CTRL_3) */
-+	odm_set_bb_reg(dm, R_0x92c, BIT(8), 1); /* rfe_inv  (RFE_CTRL_8) */
-+	odm_set_bb_reg(dm, R_0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */
-+	odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */
-+	/* @3 ------------------------- */
-+
-+	/* Pin Settings */
-+	odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
-+		/* path-A  */ /* disable CS/CG switch */
-+
-+#if 0
-+	/* @Let it follows PHY_REG for bit9 setting */
-+	if (dm->priv->pshare->rf_ft_var.use_ext_pa ||
-+	    dm->priv->pshare->rf_ft_var.use_ext_lna)
-+		odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);/* path-A output at CS */
-+	else
-+		odm_set_bb_reg(dm, R_0xc50, BIT(9), 0);
-+			/* path-A output at CG ->normal power */
-+#endif
-+
-+	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
-+		/* path-A*/ /* antsel antselb by HW */
-+	odm_set_bb_reg(dm, R_0xb38, BIT(10), 0);/* path-A*/ /* antsel2 by HW */
-+
-+	/* @Mapping table */
-+	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
-+		/* @antenna mapping table */
-+
-+	/* OFDM Settings */
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
-+
-+	/* @CCK Settings */
-+	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
-+		/* Select which path to receive for CCK_1 & CCK_2 */
-+	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
-+		/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+		/* @Fix CCK PHY status report issue */
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
-+		/* @CCK complete HW AntDiv within 64 samples */
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	phydm_evm_sw_antdiv_init(dm);
-+#endif
-+}
-+
-+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+void odm_smart_hw_ant_div_init_92e(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "***8192E AntDiv_Init =>  ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
-+}
-+#endif
-+
-+#endif /* @#if (RTL8192E_SUPPORT == 1) */
-+
-+#if (RTL8192F_SUPPORT == 1)
-+void odm_rx_hw_ant_div_init_92f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+	/* Pin Settings */
-+	odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
-+		/* reg870[8]=1'b0, "antsel" is controlled by HWs */
-+	odm_set_bb_reg(dm, R_0xc50, BIT(8), 1);
-+		/* regc50[8]=1'b1, " CS/CG switching" is controlled by HWs */
-+
-+	/* @Mapping table */
-+	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
-+		/* @antenna mapping table */
-+
-+	/* OFDM Settings */
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
-+
-+	/* @CCK Settings */
-+	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
-+		/* Select which path to receive for CCK_1 & CCK_2 */
-+	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
-+		/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+		/* @Fix CCK PHY status report issue */
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
-+		/* @CCK complete HW AntDiv within 64 samples */
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	phydm_evm_sw_antdiv_init(dm);
-+#endif
-+}
-+
-+void odm_trx_hw_ant_div_init_92f(void *dm_void)
-+
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+	/* @3 --RFE pin setting--------- */
-+	/* @[MAC] */
-+	odm_set_mac_reg(dm, R_0x1048, BIT(0), 1);
-+		/* @DBG PAD Driving control (gpioA_0) */
-+	odm_set_mac_reg(dm, R_0x1048, BIT(1), 1);
-+		/* @DBG PAD Driving control (gpioA_1) */
-+	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1);
-+	odm_set_mac_reg(dm, R_0x1038, BIT(25) | BIT(24) | BIT(23), 0);
-+		/* @gpioA_0,gpioA_1*/
-+	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
-+	/* @[BB] */
-+	odm_set_bb_reg(dm, R_0x944, BIT(8), 1); /* output enable */
-+	odm_set_bb_reg(dm, R_0x944, BIT(9), 1);
-+	odm_set_bb_reg(dm, R_0x940, BIT(16) | BIT(17), 0x0);
-+		/* r_rfe_path_sel_   (RFE_CTRL_8) */
-+	odm_set_bb_reg(dm, R_0x940, BIT(18) | BIT(19), 0x0);
-+		/* r_rfe_path_sel_   (RFE_CTRL_9) */
-+	odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer_en */
-+	odm_set_bb_reg(dm, R_0x92c, BIT(8), 0); /* rfe_inv  (RFE_CTRL_8) */
-+	odm_set_bb_reg(dm, R_0x92c, BIT(9), 1); /* rfe_inv  (RFE_CTRL_9) */
-+	odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */
-+	odm_set_bb_reg(dm, R_0x934, 0xF0, 0x8); /* path-A, RFE_CTRL_9 */
-+	/* @3 ------------------------- */
-+
-+	/* Pin Settings */
-+	odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
-+		/* path-A,disable CS/CG switch */
-+	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
-+		/* path-A*, antsel antselb by HW */
-+	odm_set_bb_reg(dm, R_0xb38, BIT(10), 0); /* path-A ,antsel2 by HW */
-+
-+	/* @Mapping table */
-+	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
-+		/* @antenna mapping table */
-+
-+	/* OFDM Settings */
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
-+
-+	/* @CCK Settings */
-+	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
-+		/* Select which path to receive for CCK_1 & CCK_2 */
-+	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
-+		/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+		/* @Fix CCK PHY status report issue */
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
-+		/* @CCK complete HW AntDiv within 64 samples */
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	phydm_evm_sw_antdiv_init(dm);
-+#endif
-+}
-+
-+#endif /* @#if (RTL8192F_SUPPORT == 1) */
-+
-+#if (RTL8822B_SUPPORT == 1)
-+void phydm_trx_hw_ant_div_init_22b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+	/* Pin Settings */
-+	odm_set_bb_reg(dm, R_0xcb8, BIT(21) | BIT(20), 0x1);
-+	odm_set_bb_reg(dm, R_0xcb8, BIT(23) | BIT(22), 0x1);
-+	odm_set_bb_reg(dm, R_0xc1c, BIT(7) | BIT(6), 0x0);
-+	/* @------------------------- */
-+
-+	/* @Mapping table */
-+	/* @antenna mapping table */
-+	odm_set_bb_reg(dm, R_0xca4, 0xFFFF, 0x0100);
-+
-+	/* OFDM Settings */
-+	/* thershold */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0);
-+	/* @bias */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0);
-+	odm_set_bb_reg(dm, R_0x668, BIT(3), 0x1);
-+
-+	/* @CCK Settings */
-+	/* Select which path to receive for CCK_1 & CCK_2 */
-+	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
-+	/* @Fix CCK PHY status report issue */
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+	/* @CCK complete HW AntDiv within 64 samples */
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
-+	/* @BT Coexistence */
-+	/* @keep antsel_map when GNT_BT = 1 */
-+	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
-+	/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
-+	odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
-+	/* response TX ant by RX ant */
-+	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
-+#if (defined(CONFIG_2T4R_ANTENNA))
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "***8822B AntDiv_Init =>  2T4R case\n");
-+	/* Pin Settings */
-+	odm_set_bb_reg(dm, R_0xeb8, BIT(21) | BIT(20), 0x1);
-+	odm_set_bb_reg(dm, R_0xeb8, BIT(23) | BIT(22), 0x1);
-+	odm_set_bb_reg(dm, R_0xe1c, BIT(7) | BIT(6), 0x0);
-+	/* @BT Coexistence */
-+	odm_set_bb_reg(dm, R_0xeac, BIT(9), 1);
-+	/* @keep antsel_map when GNT_BT = 1 */
-+	/* Mapping table */
-+	/* antenna mapping table */
-+	odm_set_bb_reg(dm, R_0xea4, 0xFFFF, 0x0100);
-+	/*odm_set_bb_reg(dm, R_0x900, 0x30000, 0x3);*/
-+#endif
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	phydm_evm_sw_antdiv_init(dm);
-+#endif
-+}
-+#endif /* @#if (RTL8822B_SUPPORT == 1) */
-+
-+#if (RTL8197F_SUPPORT == 1)
-+void phydm_rx_hw_ant_div_init_97f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+#if 0
-+	if (*dm->mp_mode == true) {
-+		odm_ant_div_on_off(dm, ANTDIV_OFF);
-+		odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
-+		/* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */
-+		odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);  /* @1:CG, 0:CS */
-+		return;
-+	}
-+#endif
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+	/* Pin Settings */
-+	odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
-+		/* reg870[8]=1'b0, */ /* "antsel" is controlled by HWs */
-+	odm_set_bb_reg(dm, R_0xc50, BIT(8), 1);
-+		/* regc50[8]=1'b1 *//*"CS/CG switching" is controlled by HWs */
-+
-+	/* @Mapping table */
-+	odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100);
-+		/* @antenna mapping table */
-+
-+	/* OFDM Settings */
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
-+
-+	/* @CCK Settings */
-+	odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
-+		/* Select which path to receive for CCK_1 & CCK_2 */
-+	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0);
-+		/* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+		/* @Fix CCK PHY status report issue */
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
-+		/* @CCK complete HW AntDiv within 64 samples */
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	phydm_evm_sw_antdiv_init(dm);
-+#endif
-+}
-+#endif //#if (RTL8197F_SUPPORT == 1)
-+
-+#if (RTL8197G_SUPPORT == 1)
-+void phydm_rx_hw_ant_div_init_97g(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+	/* Pin Settings */
-+	odm_set_bb_reg(dm, R_0x1884, BIT(23), 0);
-+		/* reg1844[23]=1'b0 *//*"CS/CG switching" is controlled by HWs*/
-+	odm_set_bb_reg(dm, R_0x1884, BIT(16), 1);
-+		/* reg1844[16]=1'b1 *//*"antsel" is controlled by HWs*/
-+
-+	/* @Mapping table */
-+	odm_set_bb_reg(dm, R_0x1870, 0xFFFF, 0x0100);
-+		/* @antenna mapping table */
-+
-+	/* OFDM Settings */
-+	odm_set_bb_reg(dm, R_0x1938, 0xFFE0, 0xA0); /* thershold */
-+	odm_set_bb_reg(dm, R_0x1938, 0x7FF0000, 0x0); /* @bias */
-+
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	phydm_evm_sw_antdiv_init(dm);
-+#endif
-+}
-+#endif //#if (RTL8197F_SUPPORT == 1)
-+
-+#if (RTL8723D_SUPPORT == 1)
-+void odm_trx_hw_ant_div_init_8723d(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+	/*@BT Coexistence*/
-+	/*@keep antsel_map when GNT_BT = 1*/
-+	odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
-+	/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
-+	odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
-+	/* @Disable hw antsw & fast_train.antsw when BT TX/RX */
-+	odm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c);
-+
-+	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
-+#if 0
-+	/*PTA setting: WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL)*/
-+	/*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/
-+	/*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/
-+#endif
-+	/*@GNT_WL tx*/
-+	odm_set_bb_reg(dm, R_0x950, BIT(29), 0);
-+
-+	/*@Mapping Table*/
-+	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
-+	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 3);
-+#if 0
-+	/* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */
-+	/* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */
-+#endif
-+
-+	/* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */
-+	odm_set_bb_reg(dm, R_0xccc, BIT(12), 0);
-+	/* @Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */
-+	odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01);
-+	/* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */
-+	odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0);
-+	/* @b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable (CCK)*/
-+	odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06);
-+	/* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable (CCK) */
-+	odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00);
-+
-+	/*OFDM HW AntDiv Parameters*/
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0);
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00);
-+	odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04);
-+
-+	/*@CCK HW AntDiv Parameters*/
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
-+	odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0);
-+
-+	odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf);
-+	odm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8);
-+	odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1);
-+	odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0);
-+	odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1);
-+
-+	/*@disable antenna training	*/
-+	odm_set_bb_reg(dm, R_0xe08, BIT(16), 0);
-+	odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
-+}
-+/*@Mingzhi 2017-05-08*/
-+
-+void odm_s0s1_sw_ant_div_init_8723d(void *dm_void)
-+{
-+	struct dm_struct		*dm = (struct dm_struct *)dm_void;
-+	struct sw_antenna_switch	*swat_tab = &dm->dm_swat_table;
-+	struct phydm_fat_struct		*fat_tab = &dm->dm_fat_table;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "***8723D AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
-+
-+	/*@keep antsel_map when GNT_BT = 1*/
-+	odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
-+
-+	/* @Disable antsw when GNT_BT=1 */
-+	odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
-+
-+	/* @Mapping Table */
-+	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
-+	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
-+
-+	/* Output Pin Settings */
-+#if 0
-+	/* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */
-+#endif
-+	odm_set_bb_reg(dm, R_0x870, BIT(8), 1);
-+	odm_set_bb_reg(dm, R_0x870, BIT(9), 1);
-+
-+	/* Status init */
-+	fat_tab->is_become_linked  = false;
-+	swat_tab->try_flag = SWAW_STEP_INIT;
-+	swat_tab->double_chk_flag = 0;
-+	swat_tab->cur_antenna = MAIN_ANT;
-+	swat_tab->pre_ant = MAIN_ANT;
-+	dm->antdiv_counter = CONFIG_ANTDIV_PERIOD;
-+
-+	/* @2 [--For HW Bug setting] */
-+	odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant  by Reg */
-+}
-+
-+void odm_update_rx_idle_ant_8723d(void *dm_void, u8 ant, u32 default_ant,
-+				  u32 optional_ant)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	void *adapter = dm->adapter;
-+	u8 count = 0;
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+	/*score board to BT ,a002:WL to do ant-div*/
-+	odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa002);
-+	ODM_delay_us(50);
-+#endif
-+#if 0
-+	/*	odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);	*/
-+#endif
-+	if (dm->ant_div_type == S0S1_SW_ANTDIV) {
-+	odm_set_bb_reg(dm, R_0x860, BIT(8), default_ant);
-+	odm_set_bb_reg(dm, R_0x860, BIT(9), default_ant);
-+	}
-+	odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
-+		/*@Default RX*/
-+	odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
-+		/*Optional RX*/
-+	odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
-+		/*@Default TX*/
-+	fat_tab->rx_idle_ant = ant;
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+	/*score board to BT ,a000:WL@S1 a001:WL@S0*/
-+	if (default_ant == ANT1_2G)
-+		odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa000);
-+	else
-+		odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa001);
-+#endif
-+}
-+
-+void phydm_set_tx_ant_pwr_8723d(void *dm_void, u8 ant)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	void *adapter = dm->adapter;
-+
-+	fat_tab->rx_idle_ant = ant;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	rtw_hal_set_tx_power_level(adapter, *dm->channel);
-+#endif
-+}
-+#endif
-+
-+#if (RTL8723B_SUPPORT == 1)
-+void odm_trx_hw_ant_div_init_8723b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "***8723B AntDiv_Init =>  ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\n");
-+
-+	/* @Mapping Table */
-+	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
-+	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
-+
-+	/* OFDM HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0); /* thershold */
-+	odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00); /* @bias */
-+
-+	/* @CCK HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+		/* patch for clk from 88M to 80M */
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
-+		/* @do 64 samples */
-+
-+	/* @BT Coexistence */
-+	odm_set_bb_reg(dm, R_0x864, BIT(12), 0);
-+		/* @keep antsel_map when GNT_BT = 1 */
-+	odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
-+		/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
-+
-+	/* Output Pin Settings */
-+	odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
-+
-+	odm_set_bb_reg(dm, R_0x948, BIT(6), 0);
-+		/* WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL) */
-+	odm_set_bb_reg(dm, R_0x948, BIT(7), 0);
-+
-+	odm_set_mac_reg(dm, R_0x40, BIT(3), 1);
-+	odm_set_mac_reg(dm, R_0x38, BIT(11), 1);
-+	odm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2);
-+		/* select DPDT_P and DPDT_N as output pin */
-+
-+	odm_set_bb_reg(dm, R_0x944, BIT(0) | BIT(1), 3); /* @in/out */
-+	odm_set_bb_reg(dm, R_0x944, BIT(31), 0);
-+
-+	odm_set_bb_reg(dm, R_0x92c, BIT(1), 0); /* @DPDT_P non-inverse */
-+	odm_set_bb_reg(dm, R_0x92c, BIT(0), 1); /* @DPDT_N inverse */
-+
-+	odm_set_bb_reg(dm, R_0x930, 0xF0, 8); /* @DPDT_P = ANTSEL[0] */
-+	odm_set_bb_reg(dm, R_0x930, 0xF, 8); /* @DPDT_N = ANTSEL[0] */
-+
-+	/* @2 [--For HW Bug setting] */
-+	if (dm->ant_type == ODM_AUTO_ANT)
-+		odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
-+			/* @CCK AntDiv function block enable */
-+}
-+
-+void odm_s0s1_sw_ant_div_init_8723b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
-+
-+	/* @Mapping Table */
-+	odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
-+	odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
-+
-+#if 0
-+	/* Output Pin Settings */
-+	/* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */
-+#endif
-+	odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
-+
-+	fat_tab->is_become_linked = false;
-+	swat_tab->try_flag = SWAW_STEP_INIT;
-+	swat_tab->double_chk_flag = 0;
-+
-+	/* @2 [--For HW Bug setting] */
-+	odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant  by Reg */
-+}
-+
-+void odm_update_rx_idle_ant_8723b(
-+	void *dm_void,
-+	u8 ant,
-+	u32 default_ant,
-+	u32 optional_ant)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	void *adapter = dm->adapter;
-+	u8 count = 0;
-+	/*u8			u1_temp;*/
-+	/*u8			h2c_parameter;*/
-+
-+	if (!dm->is_linked && dm->ant_type == ODM_AUTO_ANT) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\n");
-+		return;
-+	}
-+
-+#if 0
-+	/* Send H2C command to FW */
-+	/* @Enable wifi calibration */
-+	h2c_parameter = true;
-+	odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
-+
-+	/* @Check if H2C command sucess or not (0x1e6) */
-+	u1_temp = odm_read_1byte(dm, 0x1e6);
-+	while ((u1_temp != 0x1) && (count < 100)) {
-+		ODM_delay_us(10);
-+		u1_temp = odm_read_1byte(dm, 0x1e6);
-+		count++;
-+	}
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\n",
-+		  u1_temp, count);
-+
-+	if (u1_temp == 0x1) {
-+		/* @Check if BT is doing IQK (0x1e7) */
-+		count = 0;
-+		u1_temp = odm_read_1byte(dm, 0x1e7);
-+		while ((!(u1_temp & BIT(0)))  && (count < 100)) {
-+			ODM_delay_us(50);
-+			u1_temp = odm_read_1byte(dm, 0x1e7);
-+			count++;
-+		}
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\n",
-+			  u1_temp, count);
-+
-+		if (u1_temp & BIT(0)) {
-+			odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);
-+			odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant);
-+			odm_set_bb_reg(dm, R_0x864, 0x38, default_ant);
-+					/* @Default RX */
-+			odm_set_bb_reg(dm, R_0x864, 0x1c0, optional_ant);
-+					/* @Optional RX */
-+			odm_set_bb_reg(dm, R_0x860, 0x7000, default_ant);
-+					/* @Default TX */
-+			fat_tab->rx_idle_ant = ant;
-+
-+			/* Set TX AGC by S0/S1 */
-+			/* Need to consider Linux driver */
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+			adapter->hal_func.set_tx_power_level_handler(adapter, *dm->channel);
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+			rtw_hal_set_tx_power_level(adapter, *dm->channel);
-+#endif
-+
-+			/* Set IQC by S0/S1 */
-+			odm_set_iqc_by_rfpath(dm, default_ant);
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n");
-+		} else
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\n");
-+	} else
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\n");
-+
-+	/* Send H2C command to FW */
-+	/* @Disable wifi calibration */
-+	h2c_parameter = false;
-+	odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
-+#else
-+
-+	odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);
-+	odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant);
-+	odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant);
-+			/*@Default RX*/
-+	odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant);
-+			/*Optional RX*/
-+	odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant);
-+			/*@Default TX*/
-+	fat_tab->rx_idle_ant = ant;
-+
-+/* Set TX AGC by S0/S1 */
-+/* Need to consider Linux driver */
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	rtw_hal_set_tx_power_level(adapter, *dm->channel);
-+#endif
-+
-+	/* Set IQC by S0/S1 */
-+	odm_set_iqc_by_rfpath(dm, default_ant);
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n");
-+
-+#endif
-+}
-+
-+boolean
-+phydm_is_bt_enable_8723b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 bt_state;
-+#if 0
-+	/*u32			reg75;*/
-+
-+	/*reg75 = odm_get_bb_reg(dm, R_0x74, BIT8);*/
-+	/*odm_set_bb_reg(dm, R_0x74, BIT8, 0x0);*/
-+#endif
-+	odm_set_bb_reg(dm, R_0xa0, BIT(24) | BIT(25) | BIT(26), 0x5);
-+	bt_state = odm_get_bb_reg(dm, R_0xa0, 0xf);
-+#if 0
-+	/*odm_set_bb_reg(dm, R_0x74, BIT8, reg75);*/
-+#endif
-+
-+	if (bt_state == 4 || bt_state == 7 || bt_state == 9 || bt_state == 13)
-+		return true;
-+	else
-+		return false;
-+}
-+#endif /* @#if (RTL8723B_SUPPORT == 1) */
-+
-+#if (RTL8821A_SUPPORT == 1)
-+
-+void odm_trx_hw_ant_div_init_8821a(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+	/* Output Pin Settings */
-+	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
-+
-+	odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
-+	odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
-+
-+	odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
-+
-+	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
-+			/* select DPDT_P and DPDT_N as output pin */
-+	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
-+	odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
-+	odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
-+
-+	/* @Mapping Table */
-+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
-+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
-+
-+	/* OFDM HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
-+
-+	/* @CCK HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+		/* patch for clk from 88M to 80M */
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
-+
-+	odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
-+		/* @ANTSEL_CCK sent to the smart_antenna circuit */
-+	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
-+		/* @CCK AntDiv function block enable */
-+
-+	/* @BT Coexistence */
-+	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
-+		/* @keep antsel_map when GNT_BT = 1 */
-+	odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
-+		/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
-+
-+	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
-+		/* settling time of antdiv by RF LNA = 100ns */
-+
-+	/* response TX ant by RX ant */
-+	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
-+}
-+
-+void odm_s0s1_sw_ant_div_init_8821a(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+	/* Output Pin Settings */
-+	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
-+
-+	odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
-+	odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
-+
-+	odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
-+
-+	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
-+		/* select DPDT_P and DPDT_N as output pin */
-+	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
-+	odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
-+	odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
-+
-+	/* @Mapping Table */
-+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
-+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
-+
-+	/* OFDM HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
-+
-+	/* @CCK HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+		/* patch for clk from 88M to 80M */
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
-+
-+	odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
-+		/* @ANTSEL_CCK sent to the smart_antenna circuit */
-+	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
-+		/* @CCK AntDiv function block enable */
-+
-+	/* @BT Coexistence */
-+	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
-+		/* @keep antsel_map when GNT_BT = 1 */
-+	odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
-+		/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
-+
-+	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
-+		/* settling time of antdiv by RF LNA = 100ns */
-+
-+	/* response TX ant by RX ant */
-+	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
-+
-+	odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
-+
-+	swat_tab->try_flag = SWAW_STEP_INIT;
-+	swat_tab->double_chk_flag = 0;
-+	swat_tab->cur_antenna = MAIN_ANT;
-+	swat_tab->pre_ant = MAIN_ANT;
-+	swat_tab->swas_no_link_state = 0;
-+}
-+#endif /* @#if (RTL8821A_SUPPORT == 1) */
-+
-+#if (RTL8821C_SUPPORT == 1)
-+void odm_trx_hw_ant_div_init_8821c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+	/* Output Pin Settings */
-+	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
-+
-+	odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
-+	odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
-+
-+	odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
-+
-+	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
-+		/* select DPDT_P and DPDT_N as output pin */
-+	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
-+	odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
-+	odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
-+
-+	/* @Mapping Table */
-+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
-+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
-+
-+	/* OFDM HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
-+
-+	/* @CCK HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+		/* patch for clk from 88M to 80M */
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
-+
-+	odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
-+		/* @ANTSEL_CCK sent to the smart_antenna circuit */
-+	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
-+		/* @CCK AntDiv function block enable */
-+
-+	/* @BT Coexistence */
-+	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
-+		/* @keep antsel_map when GNT_BT = 1 */
-+	odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
-+		/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
-+
-+	/* Timming issue */
-+	odm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0);
-+		/*@keep antidx after tx for ACK ( unit x 3.2 mu sec)*/
-+	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
-+		/* settling time of antdiv by RF LNA = 100ns */
-+
-+	/* response TX ant by RX ant */
-+	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
-+}
-+
-+void phydm_s0s1_sw_ant_div_init_8821c(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+	/* Output Pin Settings */
-+	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
-+
-+	odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
-+	odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
-+
-+	odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
-+
-+	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
-+		/* select DPDT_P and DPDT_N as output pin */
-+	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
-+	odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
-+	odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
-+
-+	/* @Mapping Table */
-+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
-+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
-+
-+	/* OFDM HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x00); /* @bias */
-+
-+	/* @CCK HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+		/* patch for clk from 88M to 80M */
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
-+
-+	odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
-+		/* @ANTSEL_CCK sent to the smart_antenna circuit */
-+	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
-+		/* @CCK AntDiv function block enable */
-+
-+	/* @BT Coexistence */
-+	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
-+		/* @keep antsel_map when GNT_BT = 1 */
-+	odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
-+		/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
-+
-+	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
-+		/* settling time of antdiv by RF LNA = 100ns */
-+
-+	/* response TX ant by RX ant */
-+	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
-+
-+	odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
-+
-+	swat_tab->try_flag = SWAW_STEP_INIT;
-+	swat_tab->double_chk_flag = 0;
-+	swat_tab->cur_antenna = MAIN_ANT;
-+	swat_tab->pre_ant = MAIN_ANT;
-+	swat_tab->swas_no_link_state = 0;
-+}
-+#endif /* @#if (RTL8821C_SUPPORT == 1) */
-+
-+#if (RTL8195B_SUPPORT == 1)
-+void odm_trx_hw_ant_div_init_8195b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+	
-+	odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
-+	/*RFE control pin 0,1*/
-+	odm_set_bb_reg(dm, R_0xcb0, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
-+	odm_set_bb_reg(dm, R_0xcb0, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(20), 0); /* @DPDT_P non-inverse */
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(21), 1); /* @DPDT_N inverse */
-+
-+	/* @Mapping Table */
-+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
-+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
-+
-+	/* OFDM HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
-+
-+	/* @CCK HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+		/* patch for clk from 88M to 80M */
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
-+
-+	odm_set_bb_reg(dm, R_0x800, BIT(25), 0);
-+		/* @ANTSEL_CCK sent to the smart_antenna circuit */
-+	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0);
-+		/* @CCK AntDiv function block enable */
-+
-+	/* @BT Coexistence */
-+	odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
-+		/* @keep antsel_map when GNT_BT = 1 */
-+	odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
-+		/* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
-+
-+	/* Timming issue */
-+	odm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0);
-+		/*@keep antidx after tx for ACK ( unit x 3.2 mu sec)*/
-+	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
-+		/* settling time of antdiv by RF LNA = 100ns */
-+
-+	/* response TX ant by RX ant */
-+	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
-+}
-+#endif /* @#if (RTL8195B_SUPPORT == 1) */
-+
-+#if (RTL8881A_SUPPORT == 1)
-+void odm_trx_hw_ant_div_init_8881a(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+	/* Output Pin Settings */
-+	/* @[SPDT related] */
-+	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
-+	odm_set_mac_reg(dm, R_0x4c, BIT(26), 0);
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(22), 0);
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(24), 1);
-+	odm_set_bb_reg(dm, R_0xcb0, 0xF00, 8); /* @DPDT_P = ANTSEL[0] */
-+	odm_set_bb_reg(dm, R_0xcb0, 0xF0000, 8); /* @DPDT_N = ANTSEL[0] */
-+
-+	/* @Mapping Table */
-+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
-+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
-+
-+	/* OFDM HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */
-+	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
-+		/* settling time of antdiv by RF LNA = 100ns */
-+
-+	/* @CCK HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+		/* patch for clk from 88M to 80M */
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
-+
-+	/* @2 [--For HW Bug setting] */
-+
-+	odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
-+		/* TX ant  by Reg *//* A-cut bug */
-+}
-+
-+#endif /* @#if (RTL8881A_SUPPORT == 1) */
-+
-+#if (RTL8812A_SUPPORT == 1)
-+void odm_trx_hw_ant_div_init_8812a(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+	/* @3 */ /* @3 --RFE pin setting--------- */
-+	/* @[BB] */
-+	odm_set_bb_reg(dm, R_0x900, BIT(10) | BIT(9) | BIT(8), 0x0);
-+		/* @disable SW switch */
-+	odm_set_bb_reg(dm, R_0x900, BIT(17) | BIT(16), 0x0);
-+	odm_set_bb_reg(dm, R_0x974, BIT(7) | BIT(6), 0x3); /* @in/out */
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(26), 0);
-+	odm_set_bb_reg(dm, R_0xcb4, BIT(27), 1);
-+	odm_set_bb_reg(dm, R_0xcb0, 0xF000000, 8); /* @DPDT_P = ANTSEL[0] */
-+	odm_set_bb_reg(dm, R_0xcb0, 0xF0000000, 8); /* @DPDT_N = ANTSEL[0] */
-+	/* @3 ------------------------- */
-+
-+	/* @Mapping Table */
-+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
-+	odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
-+
-+	/* OFDM HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
-+	odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */
-+	odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3);
-+		/* settling time of antdiv by RF LNA = 100ns */
-+
-+	/* @CCK HW AntDiv Parameters */
-+	odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
-+		/* patch for clk from 88M to 80M */
-+	odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
-+
-+	/* @2 [--For HW Bug setting] */
-+
-+	odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
-+		/* TX ant  by Reg */ /* A-cut bug */
-+}
-+
-+#endif /* @#if (RTL8812A_SUPPORT == 1) */
-+
-+#if (RTL8188F_SUPPORT == 1)
-+void odm_s0s1_sw_ant_div_init_8188f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__);
-+
-+#if 0
-+	/*@GPIO setting*/
-+	/*odm_set_mac_reg(dm, R_0x64, BIT(18), 0); */
-+	/*odm_set_mac_reg(dm, R_0x44, BIT(28)|BIT(27), 0);*/
-+	/*odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3);*/
-+		/*enable_output for P_GPIO[4:3]*/
-+	/*odm_set_mac_reg(dm, R_0x44, BIT(12)|BIT(11), 0);*/ /*output value*/
-+	/*odm_set_mac_reg(dm, R_0x40, BIT(1)|BIT(0), 0);*/ /*GPIO function*/
-+#endif
-+
-+	if (dm->support_ic_type == ODM_RTL8188F) {
-+		if (dm->support_interface == ODM_ITRF_USB)
-+			odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3);
-+				/*@enable_output for P_GPIO[4:3]*/
-+		else if (dm->support_interface == ODM_ITRF_SDIO)
-+			odm_set_mac_reg(dm, R_0x44, BIT(18), 0x1);
-+				/*@enable_output for P_GPIO[2]*/
-+	}
-+
-+	fat_tab->is_become_linked = false;
-+	swat_tab->try_flag = SWAW_STEP_INIT;
-+	swat_tab->double_chk_flag = 0;
-+}
-+
-+void phydm_update_rx_idle_antenna_8188F(void *dm_void, u32 default_ant)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 codeword;
-+
-+	if (dm->support_ic_type == ODM_RTL8188F) {
-+		if (dm->support_interface == ODM_ITRF_USB) {
-+			if (default_ant == ANT1_2G)
-+				codeword = 1; /*@2'b01*/
-+			else
-+				codeword = 2; /*@2'b10*/
-+			odm_set_mac_reg(dm, R_0x44, 0x1800, codeword);
-+				/*@GPIO[4:3] output value*/
-+		} else if (dm->support_interface == ODM_ITRF_SDIO) {
-+			if (default_ant == ANT1_2G) {
-+				codeword = 0; /*@1'b0*/
-+				odm_set_bb_reg(dm, R_0x870, 0x300, 0x3);
-+				odm_set_bb_reg(dm, R_0x860, 0x300, 0x1);
-+			} else {
-+				codeword = 1; /*@1'b1*/
-+				odm_set_bb_reg(dm, R_0x870, 0x300, 0x3);
-+				odm_set_bb_reg(dm, R_0x860, 0x300, 0x2);
-+			}
-+			odm_set_mac_reg(dm, R_0x44, BIT(10), codeword);
-+				/*@GPIO[2] output value*/
-+		}
-+	}
-+}
-+#endif
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+void phydm_rx_rate_for_antdiv(void *dm_void, void *pkt_info_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	struct phydm_perpkt_info_struct *pktinfo = NULL;
-+	u8 data_rate = 0;
-+
-+	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
-+	data_rate = pktinfo->data_rate & 0x7f;
-+
-+	if (!fat_tab->get_stats)
-+		return;
-+
-+	if (fat_tab->antsel_rx_keep_0 == ANT1_2G) {
-+		if (data_rate >= ODM_RATEMCS0 &&
-+		    data_rate <= ODM_RATEMCS15)
-+			fat_tab->main_ht_cnt[data_rate - ODM_RATEMCS0]++;
-+		else if (data_rate >= ODM_RATEVHTSS1MCS0 &&
-+			 data_rate <= ODM_RATEVHTSS2MCS9)
-+			fat_tab->main_vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++;
-+	} else { /*ANT2_2G*/
-+		if (data_rate >= ODM_RATEMCS0 &&
-+		    data_rate <= ODM_RATEMCS15)
-+			fat_tab->aux_ht_cnt[data_rate - ODM_RATEMCS0]++;
-+		else if (data_rate >= ODM_RATEVHTSS1MCS0 &&
-+			 data_rate <= ODM_RATEVHTSS2MCS9)
-+			fat_tab->aux_vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++;
-+	}
-+}
-+
-+void phydm_antdiv_reset_rx_rate(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	odm_memory_set(dm, &fat_tab->main_ht_cnt[0], 0, HT_IDX * 2);
-+	odm_memory_set(dm, &fat_tab->aux_ht_cnt[0], 0, HT_IDX * 2);
-+	odm_memory_set(dm, &fat_tab->main_vht_cnt[0], 0, VHT_IDX * 2);
-+	odm_memory_set(dm, &fat_tab->aux_vht_cnt[0], 0, VHT_IDX * 2);
-+}
-+
-+void phydm_statistics_evm_1ss(void *dm_void,	void *phy_info_void,
-+			      u8 antsel_tr_mux, u32 id, u32 utility)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	struct phydm_phyinfo_struct *phy_info = NULL;
-+
-+	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
-+	if (antsel_tr_mux == ANT1_2G) {
-+		fat_tab->main_evm_sum[id] += ((phy_info->rx_mimo_evm_dbm[0])
-+					     << 5);
-+		fat_tab->main_evm_cnt[id]++;
-+	} else {
-+		fat_tab->aux_evm_sum[id] += ((phy_info->rx_mimo_evm_dbm[0])
-+					    << 5);
-+		fat_tab->aux_evm_cnt[id]++;
-+	}
-+}
-+
-+void phydm_statistics_evm_2ss(void *dm_void,	void *phy_info_void,
-+			      u8 antsel_tr_mux, u32 id, u32 utility)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	struct phydm_phyinfo_struct *phy_info = NULL;
-+
-+	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
-+	if (antsel_tr_mux == ANT1_2G) {
-+		fat_tab->main_evm_2ss_sum[id][0] += phy_info->rx_mimo_evm_dbm[0]
-+						    << 5;
-+		fat_tab->main_evm_2ss_sum[id][1] += phy_info->rx_mimo_evm_dbm[1]
-+						    << 5;
-+		fat_tab->main_evm_2ss_cnt[id]++;
-+
-+	} else {
-+		fat_tab->aux_evm_2ss_sum[id][0] += (phy_info->rx_mimo_evm_dbm[0]
-+						   << 5);
-+		fat_tab->aux_evm_2ss_sum[id][1] += (phy_info->rx_mimo_evm_dbm[1]
-+						   << 5);
-+		fat_tab->aux_evm_2ss_cnt[id]++;
-+	}
-+}
-+
-+void phydm_evm_sw_antdiv_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	/*@EVM enhance AntDiv method init----------------*/
-+	fat_tab->evm_method_enable = 0;
-+	fat_tab->fat_state = NORMAL_STATE_MIAN;
-+	fat_tab->fat_state_cnt = 0;
-+	fat_tab->pre_antdiv_rssi = 0;
-+
-+	dm->antdiv_intvl = 30;
-+	dm->antdiv_delay = 20;
-+	dm->antdiv_train_num = 4;
-+	if (dm->support_ic_type & ODM_RTL8192E)
-+		odm_set_bb_reg(dm, R_0x910, 0x3f, 0xf);
-+	dm->antdiv_evm_en = 1;
-+	/*@dm->antdiv_period=1;*/
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	dm->evm_antdiv_period = 1;
-+#else
-+	dm->evm_antdiv_period = 3;
-+#endif
-+	dm->stop_antdiv_rssi_th = 3;
-+	dm->stop_antdiv_tp_th = 80;
-+	dm->antdiv_tp_period = 3;
-+	dm->stop_antdiv_tp_diff_th = 5;
-+}
-+
-+void odm_evm_fast_ant_reset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	fat_tab->evm_method_enable = 0;
-+	if (fat_tab->div_path_type == ANT_PATH_A)
-+		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
-+	else if (fat_tab->div_path_type == ANT_PATH_B)
-+		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
-+	else if (fat_tab->div_path_type == ANT_PATH_AB)
-+		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
-+	fat_tab->fat_state = NORMAL_STATE_MIAN;
-+	fat_tab->fat_state_cnt = 0;
-+	dm->antdiv_period = 0;
-+	odm_set_mac_reg(dm, R_0x608, BIT(8), 0);
-+}
-+
-+void odm_evm_enhance_ant_div(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 main_rssi, aux_rssi;
-+	u32 main_crc_utility = 0, aux_crc_utility = 0, utility_ratio = 1;
-+	u32 main_evm, aux_evm, diff_rssi = 0, diff_EVM = 0;
-+	u32 main_2ss_evm[2], aux_2ss_evm[2];
-+	u32 main_1ss_evm, aux_1ss_evm;
-+	u32 main_2ss_evm_sum, aux_2ss_evm_sum;
-+	u8 score_EVM = 0, score_CRC = 0;
-+	u8 rssi_larger_ant = 0;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	u32 value32, i, mac_id;
-+	boolean main_above1 = false, aux_above1 = false;
-+	boolean force_antenna = false;
-+	struct cmn_sta_info *sta;
-+	u32 main_tp_avg, aux_tp_avg;
-+	u8 curr_rssi, rssi_diff;
-+	u32 tp_diff, tp_diff_avg;
-+	u16 main_max_cnt = 0, aux_max_cnt = 0;
-+	u16 main_max_idx = 0, aux_max_idx = 0;
-+	u16 main_cnt_all = 0, aux_cnt_all = 0;
-+	u8 rate_num = dm->num_rf_path;
-+	u8 rate_ss_shift = 0;
-+	u8 tp_diff_return = 0, tp_return = 0, rssi_return = 0;
-+	u8 target_ant_evm_1ss, target_ant_evm_2ss;
-+	u8 decision_evm_ss;
-+	u8 next_ant;
-+
-+	fat_tab->target_ant_enhance = 0xFF;
-+
-+	if ((dm->support_ic_type & ODM_EVM_ANTDIV_IC)) {
-+		if (dm->is_one_entry_only) {
-+#if 0
-+			/* PHYDM_DBG(dm,DBG_ANT_DIV, "[One Client only]\n"); */
-+#endif
-+			mac_id = dm->one_entry_macid;
-+			sta = dm->phydm_sta_info[mac_id];
-+
-+			main_rssi = (fat_tab->main_cnt[mac_id] != 0) ? (fat_tab->main_sum[mac_id] / fat_tab->main_cnt[mac_id]) : 0;
-+			aux_rssi = (fat_tab->aux_cnt[mac_id] != 0) ? (fat_tab->aux_sum[mac_id] / fat_tab->aux_cnt[mac_id]) : 0;
-+
-+			if ((main_rssi == 0 && aux_rssi != 0 && aux_rssi >= FORCE_RSSI_DIFF) || (main_rssi != 0 && aux_rssi == 0 && main_rssi >= FORCE_RSSI_DIFF))
-+				diff_rssi = FORCE_RSSI_DIFF;
-+			else if (main_rssi != 0 && aux_rssi != 0)
-+				diff_rssi = (main_rssi >= aux_rssi) ? (main_rssi - aux_rssi) : (aux_rssi - main_rssi);
-+
-+			if (main_rssi >= aux_rssi)
-+				rssi_larger_ant = MAIN_ANT;
-+			else
-+				rssi_larger_ant = AUX_ANT;
-+
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "Main_Cnt=(( %d )), main_rssi=(( %d ))\n",
-+				  fat_tab->main_cnt[mac_id], main_rssi);
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "Aux_Cnt=(( %d )), aux_rssi=(( %d ))\n",
-+				  fat_tab->aux_cnt[mac_id], aux_rssi);
-+
-+			if (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || fat_tab->evm_method_enable == 1)
-+			    /* @&& (diff_rssi <= FORCE_RSSI_DIFF + 1) */
-+			    ) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "> TH_H || evm_method_enable==1\n");
-+
-+				if ((main_rssi >= evm_rssi_th_low || aux_rssi >= evm_rssi_th_low)) {
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "> TH_L, fat_state_cnt =((%d))\n", fat_tab->fat_state_cnt);
-+
-+					/*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/
-+					if (fat_tab->fat_state_cnt < (dm->antdiv_train_num << 1)) {
-+						if (fat_tab->fat_state_cnt == 0) {
-+							/*Reset EVM 1SS Method */
-+							fat_tab->main_evm_sum[mac_id] = 0;
-+							fat_tab->aux_evm_sum[mac_id] = 0;
-+							fat_tab->main_evm_cnt[mac_id] = 0;
-+							fat_tab->aux_evm_cnt[mac_id] = 0;
-+							/*Reset EVM 2SS Method */
-+							fat_tab->main_evm_2ss_sum[mac_id][0] = 0;
-+							fat_tab->main_evm_2ss_sum[mac_id][1] = 0;
-+							fat_tab->aux_evm_2ss_sum[mac_id][0] = 0;
-+							fat_tab->aux_evm_2ss_sum[mac_id][1] = 0;
-+							fat_tab->main_evm_2ss_cnt[mac_id] = 0;
-+							fat_tab->aux_evm_2ss_cnt[mac_id] = 0;
-+
-+							/*Reset TP Method */
-+							fat_tab->main_tp = 0;
-+							fat_tab->aux_tp = 0;
-+							fat_tab->main_tp_cnt = 0;
-+							fat_tab->aux_tp_cnt = 0;
-+							phydm_antdiv_reset_rx_rate(dm);
-+
-+							/*Reset CRC Method */
-+							fat_tab->main_crc32_ok_cnt = 0;
-+							fat_tab->main_crc32_fail_cnt = 0;
-+							fat_tab->aux_crc32_ok_cnt = 0;
-+							fat_tab->aux_crc32_fail_cnt = 0;
-+
-+#ifdef SKIP_EVM_ANTDIV_TRAINING_PATCH
-+							if ((*dm->band_width == CHANNEL_WIDTH_20) && sta->mimo_type == RF_2T2R) {
-+								/*@1. Skip training: RSSI*/
-+#if 0
-+								/*PHYDM_DBG(pDM_Odm,DBG_ANT_DIV, "TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt);*/
-+#endif
-+								curr_rssi = (u8)((fat_tab->rx_idle_ant == MAIN_ANT) ? main_rssi : aux_rssi);
-+								rssi_diff = (curr_rssi > fat_tab->pre_antdiv_rssi) ? (curr_rssi - fat_tab->pre_antdiv_rssi) : (fat_tab->pre_antdiv_rssi - curr_rssi);
-+
-+								PHYDM_DBG(dm, DBG_ANT_DIV, "[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, fat_tab->pre_antdiv_rssi);
-+
-+								fat_tab->pre_antdiv_rssi = curr_rssi;
-+								if (rssi_diff < dm->stop_antdiv_rssi_th && curr_rssi != 0)
-+									rssi_return = 1;
-+
-+								/*@2. Skip training: TP Diff*/
-+								tp_diff = (dm->rx_tp > fat_tab->pre_antdiv_tp) ? (dm->rx_tp - fat_tab->pre_antdiv_tp) : (fat_tab->pre_antdiv_tp - dm->rx_tp);
-+
-+								PHYDM_DBG(dm, DBG_ANT_DIV, "[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", dm->rx_tp, fat_tab->pre_antdiv_tp);
-+								fat_tab->pre_antdiv_tp = dm->rx_tp;
-+								if ((tp_diff < (u32)(dm->stop_antdiv_tp_diff_th) && dm->rx_tp != 0))
-+									tp_diff_return = 1;
-+
-+								PHYDM_DBG(dm, DBG_ANT_DIV, "[3] tp_return, curr_rx_tp=((%d))\n", dm->rx_tp);
-+								/*@3. Skip training: TP*/
-+								if (dm->rx_tp >= (u32)(dm->stop_antdiv_tp_th))
-+									tp_return = 1;
-+
-+								PHYDM_DBG(dm, DBG_ANT_DIV, "[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return);
-+								/*@4. Joint Return Decision*/
-+								if (tp_return) {
-+									if (tp_diff_return || rssi_diff) {
-+										PHYDM_DBG(dm, DBG_ANT_DIV, "***Return EVM SW AntDiv\n");
-+										return;
-+									}
-+								}
-+							}
-+#endif
-+
-+							fat_tab->evm_method_enable = 1;
-+							if (fat_tab->div_path_type == ANT_PATH_A)
-+								odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
-+							else if (fat_tab->div_path_type == ANT_PATH_B)
-+								odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
-+							else if (fat_tab->div_path_type == ANT_PATH_AB)
-+								odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
-+							dm->antdiv_period = dm->evm_antdiv_period;
-+							odm_set_mac_reg(dm, R_0x608, BIT(8), 1); /*RCR accepts CRC32-Error packets*/
-+							fat_tab->fat_state_cnt++;
-+							fat_tab->get_stats = false;
-+							next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? MAIN_ANT : AUX_ANT;
-+							odm_update_rx_idle_ant(dm, next_ant);
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv Delay ]\n");
-+							odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_delay); //ms
-+						} else if ((fat_tab->fat_state_cnt % 2) != 0) {
-+							fat_tab->fat_state_cnt++;
-+							fat_tab->get_stats = true;
-+							odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_intvl); //ms
-+						} else if ((fat_tab->fat_state_cnt % 2) == 0) {
-+							fat_tab->fat_state_cnt++;
-+							fat_tab->get_stats = false;
-+							next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
-+							odm_update_rx_idle_ant(dm, next_ant);
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv Delay ]\n");
-+							odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_delay); //ms
-+						}
-+					}
-+					/*@Decision state: 4==============================================================*/
-+					else {
-+						fat_tab->get_stats = false;
-+						fat_tab->fat_state_cnt = 0;
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "[Decisoin state ]\n");
-+
-+/* @3 [CRC32 statistic] */
-+#if 0
-+						if ((fat_tab->main_crc32_ok_cnt > (fat_tab->aux_crc32_ok_cnt << 1)) || (diff_rssi >= 40 && rssi_larger_ant == MAIN_ANT)) {
-+							fat_tab->target_ant_crc32 = MAIN_ANT;
-+							force_antenna = true;
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Main\n");
-+						} else if ((fat_tab->aux_crc32_ok_cnt > ((fat_tab->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == AUX_ANT))) {
-+							fat_tab->target_ant_crc32 = AUX_ANT;
-+							force_antenna = true;
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Aux\n");
-+						} else
-+#endif
-+						{
-+							if (fat_tab->main_crc32_fail_cnt <= 5)
-+								fat_tab->main_crc32_fail_cnt = 5;
-+
-+							if (fat_tab->aux_crc32_fail_cnt <= 5)
-+								fat_tab->aux_crc32_fail_cnt = 5;
-+
-+							if (fat_tab->main_crc32_ok_cnt > fat_tab->main_crc32_fail_cnt)
-+								main_above1 = true;
-+
-+							if (fat_tab->aux_crc32_ok_cnt > fat_tab->aux_crc32_fail_cnt)
-+								aux_above1 = true;
-+
-+							if (main_above1 == true && aux_above1 == false) {
-+								force_antenna = true;
-+								fat_tab->target_ant_crc32 = MAIN_ANT;
-+							} else if (main_above1 == false && aux_above1 == true) {
-+								force_antenna = true;
-+								fat_tab->target_ant_crc32 = AUX_ANT;
-+							} else if (main_above1 == true && aux_above1 == true) {
-+								main_crc_utility = ((fat_tab->main_crc32_ok_cnt) << 7) / fat_tab->main_crc32_fail_cnt;
-+								aux_crc_utility = ((fat_tab->aux_crc32_ok_cnt) << 7) / fat_tab->aux_crc32_fail_cnt;
-+								fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
-+
-+								if (main_crc_utility != 0 && aux_crc_utility != 0) {
-+									if (main_crc_utility >= aux_crc_utility)
-+										utility_ratio = (main_crc_utility << 1) / aux_crc_utility;
-+									else
-+										utility_ratio = (aux_crc_utility << 1) / main_crc_utility;
-+								}
-+							} else if (main_above1 == false && aux_above1 == false) {
-+								if (fat_tab->main_crc32_ok_cnt == 0)
-+									fat_tab->main_crc32_ok_cnt = 1;
-+								if (fat_tab->aux_crc32_ok_cnt == 0)
-+									fat_tab->aux_crc32_ok_cnt = 1;
-+
-+								main_crc_utility = ((fat_tab->main_crc32_fail_cnt) << 7) / fat_tab->main_crc32_ok_cnt;
-+								aux_crc_utility = ((fat_tab->aux_crc32_fail_cnt) << 7) / fat_tab->aux_crc32_ok_cnt;
-+								fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
-+
-+								if (main_crc_utility != 0 && aux_crc_utility != 0) {
-+									if (main_crc_utility >= aux_crc_utility)
-+										utility_ratio = (main_crc_utility << 1) / (aux_crc_utility);
-+									else
-+										utility_ratio = (aux_crc_utility << 1) / (main_crc_utility);
-+								}
-+							}
-+						}
-+						odm_set_mac_reg(dm, R_0x608, BIT(8), 0); /* NOT Accept CRC32 Error packets. */
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->main_crc32_ok_cnt, fat_tab->main_crc32_fail_cnt, main_crc_utility);
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->aux_crc32_ok_cnt, fat_tab->aux_crc32_fail_cnt, aux_crc_utility);
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "***1.TargetAnt_CRC32 = ((%s))\n", (fat_tab->target_ant_crc32 == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
-+
-+						for (i = 0; i < HT_IDX; i++) {
-+							main_cnt_all += fat_tab->main_ht_cnt[i];
-+							aux_cnt_all += fat_tab->aux_ht_cnt[i];
-+
-+							if (fat_tab->main_ht_cnt[i] > main_max_cnt) {
-+								main_max_cnt = fat_tab->main_ht_cnt[i];
-+								main_max_idx = i;
-+							}
-+
-+							if (fat_tab->aux_ht_cnt[i] > aux_max_cnt) {
-+								aux_max_cnt = fat_tab->aux_ht_cnt[i];
-+								aux_max_idx = i;
-+							}
-+						}
-+
-+						for (i = 0; i < rate_num; i++) {
-+							rate_ss_shift = (i << 3);
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "*main_ht_cnt  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
-+							(rate_ss_shift), (rate_ss_shift + 7),
-+							fat_tab->main_ht_cnt[rate_ss_shift + 0], fat_tab->main_ht_cnt[rate_ss_shift + 1],
-+							fat_tab->main_ht_cnt[rate_ss_shift + 2], fat_tab->main_ht_cnt[rate_ss_shift + 3],
-+							fat_tab->main_ht_cnt[rate_ss_shift + 4], fat_tab->main_ht_cnt[rate_ss_shift + 5],
-+							fat_tab->main_ht_cnt[rate_ss_shift + 6], fat_tab->main_ht_cnt[rate_ss_shift + 7]);
-+						}
-+
-+						for (i = 0; i < rate_num; i++) {
-+							rate_ss_shift = (i << 3);
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "*aux_ht_cnt  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
-+							(rate_ss_shift), (rate_ss_shift + 7),
-+							fat_tab->aux_ht_cnt[rate_ss_shift + 0], fat_tab->aux_ht_cnt[rate_ss_shift + 1],
-+							fat_tab->aux_ht_cnt[rate_ss_shift + 2], fat_tab->aux_ht_cnt[rate_ss_shift + 3],
-+							fat_tab->aux_ht_cnt[rate_ss_shift + 4], fat_tab->aux_ht_cnt[rate_ss_shift + 5],
-+							fat_tab->aux_ht_cnt[rate_ss_shift + 6], fat_tab->aux_ht_cnt[rate_ss_shift + 7]);
-+						}
-+
-+						/* @3 [EVM statistic] */
-+						/*@1SS EVM*/
-+						main_1ss_evm = (fat_tab->main_evm_cnt[mac_id] != 0) ? (fat_tab->main_evm_sum[mac_id] / fat_tab->main_evm_cnt[mac_id]) : 0;
-+						aux_1ss_evm = (fat_tab->aux_evm_cnt[mac_id] != 0) ? (fat_tab->aux_evm_sum[mac_id] / fat_tab->aux_evm_cnt[mac_id]) : 0;
-+						target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? (fat_tab->pre_target_ant_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT);
-+
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main1ss_EVM= ((  %d ))\n", fat_tab->main_evm_cnt[mac_id], main_1ss_evm);
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_1ss_EVM = ((  %d ))\n", fat_tab->aux_evm_cnt[mac_id], aux_1ss_evm);
-+
-+						/*@2SS EVM*/
-+						main_2ss_evm[0] = (fat_tab->main_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->main_evm_2ss_sum[mac_id][0] / fat_tab->main_evm_2ss_cnt[mac_id]) : 0;
-+						main_2ss_evm[1] = (fat_tab->main_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->main_evm_2ss_sum[mac_id][1] / fat_tab->main_evm_2ss_cnt[mac_id]) : 0;
-+						main_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1];
-+
-+						aux_2ss_evm[0] = (fat_tab->aux_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->aux_evm_2ss_sum[mac_id][0] / fat_tab->aux_evm_2ss_cnt[mac_id]) : 0;
-+						aux_2ss_evm[1] = (fat_tab->aux_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->aux_evm_2ss_sum[mac_id][1] / fat_tab->aux_evm_2ss_cnt[mac_id]) : 0;
-+						aux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1];
-+
-+						target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (fat_tab->pre_target_ant_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT);
-+
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
-+							  fat_tab->main_evm_2ss_cnt[mac_id], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum);
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
-+							  fat_tab->aux_evm_2ss_cnt[mac_id], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum);
-+
-+						if ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) {
-+							decision_evm_ss = 2;
-+							main_evm = main_2ss_evm_sum;
-+							aux_evm = aux_2ss_evm_sum;
-+							fat_tab->target_ant_evm = target_ant_evm_2ss;
-+						} else {
-+							decision_evm_ss = 1;
-+							main_evm = main_1ss_evm;
-+							aux_evm = aux_1ss_evm;
-+							fat_tab->target_ant_evm = target_ant_evm_1ss;
-+						}
-+
-+						if ((main_evm == 0 || aux_evm == 0))
-+							diff_EVM = 100;
-+						else if (main_evm >= aux_evm)
-+							diff_EVM = main_evm - aux_evm;
-+						else
-+							diff_EVM = aux_evm - main_evm;
-+
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (fat_tab->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
-+
-+						//3 [TP statistic]
-+						main_tp_avg = (fat_tab->main_tp_cnt != 0) ? (fat_tab->main_tp / fat_tab->main_tp_cnt) : 0;
-+						aux_tp_avg = (fat_tab->aux_tp_cnt != 0) ? (fat_tab->aux_tp / fat_tab->aux_tp_cnt) : 0;
-+						tp_diff_avg = DIFF_2(main_tp_avg, aux_tp_avg);
-+						fat_tab->target_ant_tp = (tp_diff_avg < 100) ? (fat_tab->pre_target_ant_enhance) : ((main_tp_avg >= aux_tp_avg) ? MAIN_ANT : AUX_ANT);
-+
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main_TP = ((%d))\n", fat_tab->main_tp_cnt, main_tp_avg);
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_TP = ((%d))\n", fat_tab->aux_tp_cnt, aux_tp_avg);
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "***3.TargetAnt_TP = ((%s))\n", (fat_tab->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
-+
-+						/*Reset TP Method */
-+						fat_tab->main_tp = 0;
-+						fat_tab->aux_tp = 0;
-+						fat_tab->main_tp_cnt = 0;
-+						fat_tab->aux_tp_cnt = 0;
-+
-+						/* @2 [ Decision state ] */
-+						#if 1
-+						if (main_max_idx == aux_max_idx && ((main_cnt_all + aux_cnt_all) != 0)) {
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision EVM, main_max_idx = ((MCS%d)), aux_max_idx = ((MCS%d))\n", main_max_idx, aux_max_idx);
-+							fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
-+						} else {
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision TP, main_max_idx = ((MCS%d)), aux_max_idx = ((MCS%d))\n", main_max_idx, aux_max_idx);
-+							fat_tab->target_ant_enhance = fat_tab->target_ant_tp;
-+						}
-+						#else
-+						if (fat_tab->target_ant_evm == fat_tab->target_ant_crc32) {
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
-+
-+							if ((utility_ratio < 2 && force_antenna == false) && diff_EVM <= 30)
-+								fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;
-+							else
-+								fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
-+						}
-+						#if 0
-+						else if ((diff_EVM <= 50 && (utility_ratio > 4 && force_antenna == false)) || (force_antenna == true)) {
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
-+							fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
-+						}
-+						#endif
-+						else if (diff_EVM >= 20) {
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
-+							fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
-+						} else if (utility_ratio >= 6 && force_antenna == false) {
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
-+							fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
-+						} else {
-+							PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
-+
-+							if (force_antenna == true)
-+								score_CRC = 2;
-+							else if (utility_ratio >= 5) /*@>2.5*/
-+								score_CRC = 2;
-+							else if (utility_ratio >= 4) /*@>2*/
-+								score_CRC = 1;
-+							else
-+								score_CRC = 0;
-+
-+							if (diff_EVM >= 15)
-+								score_EVM = 3;
-+							else if (diff_EVM >= 10)
-+								score_EVM = 2;
-+							else if (diff_EVM >= 5)
-+								score_EVM = 1;
-+							else
-+								score_EVM = 0;
-+
-+							if (score_CRC > score_EVM)
-+								fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
-+							else if (score_CRC < score_EVM)
-+								fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
-+							else
-+								fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;
-+						}
-+						#endif
-+						fat_tab->pre_target_ant_enhance = fat_tab->target_ant_enhance;
-+
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "*** 4.TargetAnt_enhance = (( %s ))******\n", (fat_tab->target_ant_enhance == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
-+					}
-+				} else { /* RSSI< = evm_rssi_th_low */
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "[ <TH_L: escape from > TH_L ]\n");
-+					odm_evm_fast_ant_reset(dm);
-+				}
-+			} else {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "[escape from> TH_H || evm_method_enable==1]\n");
-+				odm_evm_fast_ant_reset(dm);
-+			}
-+		} else {
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "[multi-Client]\n");
-+			odm_evm_fast_ant_reset(dm);
-+		}
-+	}
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void phydm_evm_antdiv_callback(
-+	struct phydm_timer_list *timer)
-+{
-+	void *adapter = (void *)timer->Adapter;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+
-+	#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+	#if USE_WORKITEM
-+	odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem);
-+	#else
-+	{
-+		odm_hw_ant_div(dm);
-+	}
-+	#endif
-+	#else
-+	odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem);
-+	#endif
-+}
-+
-+void phydm_evm_antdiv_workitem_callback(
-+	void *context)
-+{
-+	void *adapter = (void *)context;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+
-+	odm_hw_ant_div(dm);
-+}
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+void phydm_evm_antdiv_callback(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	void *padapter = dm->adapter;
-+
-+	if (*dm->is_net_closed)
-+		return;
-+	if (dm->support_interface == ODM_ITRF_PCIE) {
-+		odm_hw_ant_div(dm);
-+	} else {
-+		/* @Can't do I/O in timer callback*/
-+		phydm_run_in_thread_cmd(dm,
-+					phydm_evm_antdiv_workitem_callback,
-+					padapter);
-+	}
-+}
-+
-+void phydm_evm_antdiv_workitem_callback(void *context)
-+{
-+	void *adapter = (void *)context;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->odmpriv;
-+
-+	odm_hw_ant_div(dm);
-+}
-+
-+#else
-+void phydm_evm_antdiv_callback(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "******AntDiv_Callback******\n");
-+	odm_hw_ant_div(dm);
-+}
-+#endif
-+
-+#endif
-+
-+void odm_hw_ant_div(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 i, min_max_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0;
-+	u32 main_rssi, aux_rssi, mian_cnt, aux_cnt, local_max_rssi;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	u8 rx_idle_ant = fat_tab->rx_idle_ant, target_ant = 7;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct cmn_sta_info *sta;
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
-+	u32 TH1 = 500000;
-+	u32 TH2 = 10000000;
-+	u32 ma_rx_temp, degrade_TP_temp, improve_TP_temp;
-+	u8 monitor_rssi_threshold = 30;
-+
-+	dm_bdc_table->BF_pass = true;
-+	dm_bdc_table->DIV_pass = true;
-+	dm_bdc_table->is_all_div_sta_idle = true;
-+	dm_bdc_table->is_all_bf_sta_idle = true;
-+	dm_bdc_table->num_bf_tar = 0;
-+	dm_bdc_table->num_div_tar = 0;
-+	dm_bdc_table->num_client = 0;
-+#endif
-+#endif
-+
-+	if (!dm->is_linked) { /* @is_linked==False */
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
-+
-+		if (fat_tab->is_become_linked) {
-+			if (fat_tab->div_path_type == ANT_PATH_A)
-+				odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
-+			else if (fat_tab->div_path_type == ANT_PATH_B)
-+				odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
-+			else if (fat_tab->div_path_type == ANT_PATH_AB)
-+				odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
-+			odm_update_rx_idle_ant(dm, MAIN_ANT);
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
-+			dm->antdiv_period = 0;
-+
-+			fat_tab->is_become_linked = dm->is_linked;
-+		}
-+		return;
-+	} else {
-+		if (!fat_tab->is_become_linked) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
-+			if (fat_tab->div_path_type == ANT_PATH_A)
-+				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
-+			else if (fat_tab->div_path_type == ANT_PATH_B)
-+				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
-+			else if (fat_tab->div_path_type == ANT_PATH_AB)
-+				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
-+			#if 0
-+			/*odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);*/
-+
-+			/* @if(dm->support_ic_type == ODM_RTL8821 ) */
-+			/* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */
-+			/* CCK AntDiv function disable */
-+
-+			/* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */
-+			/* @else if(dm->support_ic_type == ODM_RTL8881A) */
-+			/* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */
-+			/* CCK AntDiv function disable */
-+			/* @#endif */
-+
-+			/* @else if(dm->support_ic_type == ODM_RTL8723B ||*/
-+			/* @dm->support_ic_type == ODM_RTL8812) */
-+			/* odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); */
-+			/* CCK AntDiv function disable */
-+			#endif
-+
-+			fat_tab->is_become_linked = dm->is_linked;
-+
-+			if (dm->support_ic_type == ODM_RTL8723B &&
-+			    dm->ant_div_type == CG_TRX_HW_ANTDIV) {
-+				odm_set_bb_reg(dm, R_0x930, 0xF0, 8);
-+				/* @DPDT_P = ANTSEL[0] for 8723B AntDiv */
-+				odm_set_bb_reg(dm, R_0x930, 0xF, 8);
-+				/* @DPDT_N = ANTSEL[0] */
-+			}
-+
-+			/* @ BDC Init */
-+			#ifdef PHYDM_BEAMFORMING_SUPPORT
-+			#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+			odm_bdc_init(dm);
-+			#endif
-+			#endif
-+
-+			#ifdef ODM_EVM_ENHANCE_ANTDIV
-+			odm_evm_fast_ant_reset(dm);
-+			#endif
-+		}
-+	}
-+
-+	if (!(*fat_tab->p_force_tx_by_desc)) {
-+		if (dm->is_one_entry_only)
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
-+		else
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
-+	}
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	if (dm->antdiv_evm_en == 1) {
-+		odm_evm_enhance_ant_div(dm);
-+		if (fat_tab->fat_state_cnt != 0)
-+			return;
-+	} else
-+		odm_evm_fast_ant_reset(dm);
-+#endif
-+
-+/* @2 BDC mode Arbitration */
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0)
-+		odm_bf_ant_div_mode_arbitration(dm);
-+#endif
-+#endif
-+
-+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
-+		sta = dm->phydm_sta_info[i];
-+		if (!is_sta_active(sta)) {
-+			phydm_antdiv_reset_statistic(dm, i);
-+			continue;
-+		}
-+
-+		/* @2 Caculate RSSI per Antenna */
-+		if (fat_tab->main_cnt[i] != 0 || fat_tab->aux_cnt[i] != 0) {
-+			mian_cnt = fat_tab->main_cnt[i];
-+			aux_cnt = fat_tab->aux_cnt[i];
-+			main_rssi = (mian_cnt != 0) ?
-+				    (fat_tab->main_sum[i] / mian_cnt) : 0;
-+			aux_rssi = (aux_cnt != 0) ?
-+				   (fat_tab->aux_sum[i] / aux_cnt) : 0;
-+			target_ant = (mian_cnt == aux_cnt) ?
-+				     fat_tab->rx_idle_ant :
-+				     ((mian_cnt >= aux_cnt) ?
-+				     fat_tab->ant_idx_vec[0]:fat_tab->ant_idx_vec[1]);
-+				     /*Use counter number for OFDM*/
-+
-+		} else { /*@CCK only case*/
-+			mian_cnt = fat_tab->main_cnt_cck[i];
-+			aux_cnt = fat_tab->aux_cnt_cck[i];
-+			main_rssi = (mian_cnt != 0) ?
-+				    (fat_tab->main_sum_cck[i] / mian_cnt) : 0;
-+			aux_rssi = (aux_cnt != 0) ?
-+				   (fat_tab->aux_sum_cck[i] / aux_cnt) : 0;
-+			target_ant = (main_rssi == aux_rssi) ?
-+				     fat_tab->rx_idle_ant :
-+				     ((main_rssi >= aux_rssi) ?
-+				     fat_tab->ant_idx_vec[0]:fat_tab->ant_idx_vec[1]);
-+				     /*Use RSSI for CCK only case*/
-+		}
-+#if (RTL8721D_SUPPORT)
-+	if(dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2PB26) { /* added by Jiao Qi on May.25,2020, only for 3 antenna diversity */
-+		u8 tmp;
-+		if(target_ant == fat_tab->ant_idx_vec[0]){/* switch the second & third ant index */
-+			tmp = fat_tab->ant_idx_vec[1];
-+			fat_tab->ant_idx_vec[1] = fat_tab->ant_idx_vec[2];
-+			fat_tab->ant_idx_vec[2] = tmp;
-+		}else{
-+			/* switch the first & second ant index */
-+			tmp = fat_tab->ant_idx_vec[0];
-+			fat_tab->ant_idx_vec[0] = fat_tab->ant_idx_vec[1];
-+			fat_tab->ant_idx_vec[1] = tmp;
-+			/* switch the second & third ant index */
-+			tmp = fat_tab->ant_idx_vec[1];
-+			fat_tab->ant_idx_vec[1] = fat_tab->ant_idx_vec[2];
-+			fat_tab->ant_idx_vec[2] = tmp;
-+		}
-+	}
-+#endif
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "*** Client[ %d ] : Main_Cnt = (( %d ))  ,  CCK_Main_Cnt = (( %d )) ,  main_rssi= ((  %d ))\n",
-+			  i, fat_tab->main_cnt[i],
-+			  fat_tab->main_cnt_cck[i], main_rssi);
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "*** Client[ %d ] : Aux_Cnt   = (( %d ))  , CCK_Aux_Cnt   = (( %d )) ,  aux_rssi = ((  %d ))\n",
-+			  i, fat_tab->aux_cnt[i],
-+			  fat_tab->aux_cnt_cck[i], aux_rssi);
-+
-+		local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi;
-+		/* @ Select max_rssi for DIG */
-+		if (local_max_rssi > ant_div_max_rssi && local_max_rssi < 40)
-+			ant_div_max_rssi = local_max_rssi;
-+		if (local_max_rssi > max_rssi)
-+			max_rssi = local_max_rssi;
-+
-+		/* @ Select RX Idle Antenna */
-+		if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {
-+			rx_idle_ant = target_ant;
-+			min_max_rssi = local_max_rssi;
-+		}
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+		if (dm->antdiv_evm_en == 1) {
-+			if (fat_tab->target_ant_enhance != 0xFF) {
-+				target_ant = fat_tab->target_ant_enhance;
-+				rx_idle_ant = fat_tab->target_ant_enhance;
-+			}
-+		}
-+#endif
-+
-+		/* @2 Select TX Antenna */
-+		if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
-+			#ifdef PHYDM_BEAMFORMING_SUPPORT
-+			#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+			if (dm_bdc_table->w_bfee_client[i] == 0)
-+			#endif
-+			#endif
-+			{
-+				odm_update_tx_ant(dm, target_ant, i);
-+			}
-+		}
-+
-+/* @------------------------------------------------------------ */
-+
-+		#ifdef PHYDM_BEAMFORMING_SUPPORT
-+		#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+
-+		dm_bdc_table->num_client++;
-+
-+		if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
-+			/* @2 Byte counter */
-+
-+			ma_rx_temp = sta->rx_moving_average_tp; /* RX  TP   ( bit /sec) */
-+
-+			if (dm_bdc_table->BDC_state == bdc_bfer_train_state)
-+				dm_bdc_table->MA_rx_TP_DIV[i] = ma_rx_temp;
-+			else
-+				dm_bdc_table->MA_rx_TP[i] = ma_rx_temp;
-+
-+			if (ma_rx_temp < TH2 && ma_rx_temp > TH1 && local_max_rssi <= monitor_rssi_threshold) {
-+				if (dm_bdc_table->w_bfer_client[i] == 1) { /* @Bfer_Target */
-+					dm_bdc_table->num_bf_tar++;
-+
-+					if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) {
-+						improve_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 9) >> 3; /* @* 1.125 */
-+						dm_bdc_table->BF_pass = (dm_bdc_table->MA_rx_TP[i] > improve_TP_temp) ? true : false;
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :  { MA_rx_TP,improve_TP_temp, MA_rx_TP_DIV,  BF_pass}={ %d,  %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], improve_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->BF_pass);
-+					}
-+				} else { /* @DIV_Target */
-+					dm_bdc_table->num_div_tar++;
-+
-+					if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) {
-+						degrade_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 5) >> 3; /* @* 0.625 */
-+						dm_bdc_table->DIV_pass = (dm_bdc_table->MA_rx_TP[i] > degrade_TP_temp) ? true : false;
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :  { MA_rx_TP, degrade_TP_temp, MA_rx_TP_DIV,  DIV_pass}=\n{ %d,  %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], degrade_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->DIV_pass);
-+					}
-+				}
-+			}
-+
-+			if (ma_rx_temp > TH1) {
-+				if (dm_bdc_table->w_bfer_client[i] == 1) /* @Bfer_Target */
-+					dm_bdc_table->is_all_bf_sta_idle = false;
-+				else /* @DIV_Target */
-+					dm_bdc_table->is_all_div_sta_idle = false;
-+			}
-+
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "*** Client[ %d ] :  { BFmeeCap, BFmerCap}  = { %d , %d }\n",
-+				  i, dm_bdc_table->w_bfee_client[i],
-+				  dm_bdc_table->w_bfer_client[i]);
-+
-+			if (dm_bdc_table->BDC_state == bdc_bfer_train_state)
-+				PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :    MA_rx_TP_DIV = (( %d ))\n", i, dm_bdc_table->MA_rx_TP_DIV[i]);
-+
-+			else
-+				PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :    MA_rx_TP = (( %d ))\n", i, dm_bdc_table->MA_rx_TP[i]);
-+		}
-+		#endif
-+		#endif
-+
-+		#ifdef PHYDM_BEAMFORMING_SUPPORT
-+		#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+		if (dm_bdc_table->bdc_try_flag == 0)
-+		#endif
-+		#endif
-+		{
-+			phydm_antdiv_reset_statistic(dm, i);
-+		}
-+	}
-+
-+/* @2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) */
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "*** rx_idle_ant = (( %s ))\n",
-+		  (rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	if (dm_bdc_table->bdc_mode == BDC_MODE_1 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "*** bdc_rx_idle_update_counter = (( %d ))\n",
-+			  dm_bdc_table->bdc_rx_idle_update_counter);
-+
-+		if (dm_bdc_table->bdc_rx_idle_update_counter == 1) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "***Update RxIdle Antenna!!!\n");
-+			dm_bdc_table->bdc_rx_idle_update_counter = 30;
-+			odm_update_rx_idle_ant(dm, rx_idle_ant);
-+		} else {
-+			dm_bdc_table->bdc_rx_idle_update_counter--;
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "***NOT update RxIdle Antenna because of BF  ( need to fix TX-ant)\n");
-+		}
-+	} else
-+#endif
-+#endif
-+		odm_update_rx_idle_ant(dm, rx_idle_ant);
-+#else
-+#if (RTL8721D_SUPPORT)
-+if (dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2PB26) {
-+	if(odm_get_bb_reg(dm,R_0xc50,0x80) || odm_get_bb_reg(dm, R_0xa00, 0x8000))
-+		odm_update_rx_idle_ant_sp3t(dm, rx_idle_ant);
-+}
-+else
-+#endif
-+	odm_update_rx_idle_ant(dm, rx_idle_ant);
-+
-+#endif /* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */
-+
-+/* @2 BDC Main Algorithm */
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0)
-+		odm_bd_ccoex_bfee_rx_div_arbitration(dm);
-+
-+	dm_bdc_table->num_txbfee_client = 0;
-+	dm_bdc_table->num_txbfer_client = 0;
-+#endif
-+#endif
-+
-+	if (ant_div_max_rssi == 0)
-+		dig_t->ant_div_rssi_max = dm->rssi_min;
-+	else
-+		dig_t->ant_div_rssi_max = ant_div_max_rssi;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "***AntDiv End***\n\n");
-+}
-+
-+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+
-+void odm_s0s1_sw_ant_div_reset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	fat_tab->is_become_linked = false;
-+	swat_tab->try_flag = SWAW_STEP_INIT;
-+	swat_tab->double_chk_flag = 0;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "%s: fat_tab->is_become_linked = %d\n",
-+		  __func__, fat_tab->is_become_linked);
-+}
-+
-+void phydm_sw_antdiv_train_time(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
-+	u8 high_traffic_train_time_u = 0x32, high_traffic_train_time_l = 0;
-+	u8 low_traffic_train_time_u = 200, low_traffic_train_time_l = 0;
-+	u8 train_time_temp;
-+
-+	if (dm->traffic_load == TRAFFIC_HIGH) {
-+		train_time_temp = swat_tab->train_time;
-+
-+		if (swat_tab->train_time_flag == 3) {
-+			high_traffic_train_time_l = 0xa;
-+
-+			if (train_time_temp <= 16)
-+				train_time_temp = high_traffic_train_time_l;
-+			else
-+				train_time_temp -= 16;
-+
-+		} else if (swat_tab->train_time_flag == 2) {
-+			train_time_temp -= 8;
-+			high_traffic_train_time_l = 0xf;
-+		} else if (swat_tab->train_time_flag == 1) {
-+			train_time_temp -= 4;
-+			high_traffic_train_time_l = 0x1e;
-+		} else if (swat_tab->train_time_flag == 0) {
-+			train_time_temp += 8;
-+			high_traffic_train_time_l = 0x28;
-+		}
-+
-+		if (dm->support_ic_type == ODM_RTL8188F) {
-+			if (dm->support_interface == ODM_ITRF_SDIO)
-+				high_traffic_train_time_l += 0xa;
-+		}
-+
-+		/* @-- */
-+		if (train_time_temp > high_traffic_train_time_u)
-+			train_time_temp = high_traffic_train_time_u;
-+
-+		else if (train_time_temp < high_traffic_train_time_l)
-+			train_time_temp = high_traffic_train_time_l;
-+
-+		swat_tab->train_time = train_time_temp; /*@10ms~200ms*/
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "train_time_flag=((%d)), train_time=((%d))\n",
-+			  swat_tab->train_time_flag,
-+			  swat_tab->train_time);
-+
-+	} else if ((dm->traffic_load == TRAFFIC_MID) ||
-+		   (dm->traffic_load == TRAFFIC_LOW)) {
-+		train_time_temp = swat_tab->train_time;
-+
-+		if (swat_tab->train_time_flag == 3) {
-+			low_traffic_train_time_l = 10;
-+			if (train_time_temp < 50)
-+				train_time_temp = low_traffic_train_time_l;
-+			else
-+				train_time_temp -= 50;
-+		} else if (swat_tab->train_time_flag == 2) {
-+			train_time_temp -= 30;
-+			low_traffic_train_time_l = 36;
-+		} else if (swat_tab->train_time_flag == 1) {
-+			train_time_temp -= 10;
-+			low_traffic_train_time_l = 40;
-+		} else {
-+			train_time_temp += 10;
-+			low_traffic_train_time_l = 50;
-+		}
-+
-+		if (dm->support_ic_type == ODM_RTL8188F) {
-+			if (dm->support_interface == ODM_ITRF_SDIO)
-+				low_traffic_train_time_l += 10;
-+		}
-+
-+		/* @-- */
-+		if (train_time_temp >= low_traffic_train_time_u)
-+			train_time_temp = low_traffic_train_time_u;
-+
-+		else if (train_time_temp <= low_traffic_train_time_l)
-+			train_time_temp = low_traffic_train_time_l;
-+
-+		swat_tab->train_time = train_time_temp; /*@10ms~200ms*/
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "train_time_flag=((%d)) , train_time=((%d))\n",
-+			  swat_tab->train_time_flag, swat_tab->train_time);
-+
-+	} else {
-+		swat_tab->train_time = 0xc8; /*@200ms*/
-+	}
-+}
-+
-+void phydm_sw_antdiv_decision(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	u32 i, min_max_rssi = 0xFF, local_max_rssi, local_min_rssi;
-+	u32 main_rssi, aux_rssi;
-+	u8 rx_idle_ant = swat_tab->pre_ant;
-+	u8 target_ant = swat_tab->pre_ant, next_ant = 0;
-+	struct cmn_sta_info *entry = NULL;
-+	u32 main_cnt = 0, aux_cnt = 0, main_sum = 0, aux_sum = 0;
-+	u32 main_ctrl_cnt = 0, aux_ctrl_cnt = 0;
-+	boolean is_by_ctrl_frame = false;
-+	boolean cond_23d_main, cond_23d_aux;
-+	u64 pkt_cnt_total = 0;
-+
-+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
-+		entry = dm->phydm_sta_info[i];
-+		if (!is_sta_active(entry)) {
-+			phydm_antdiv_reset_statistic(dm, i);
-+			continue;
-+		}
-+
-+		/* @2 Caculate RSSI per Antenna */
-+		if (fat_tab->main_cnt[i] != 0 || fat_tab->aux_cnt[i] != 0) {
-+			main_cnt = (u32)fat_tab->main_cnt[i];
-+			aux_cnt = (u32)fat_tab->aux_cnt[i];
-+			main_rssi = (main_cnt != 0) ?
-+				    (fat_tab->main_sum[i] / main_cnt) : 0;
-+			aux_rssi = (aux_cnt != 0) ?
-+				   (fat_tab->aux_sum[i] / aux_cnt) : 0;
-+			if (dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710C) {
-+				cond_23d_main = (aux_cnt > main_cnt) &&
-+						((main_rssi - aux_rssi < 5) ||
-+						(aux_rssi > main_rssi));
-+				cond_23d_aux = (main_cnt > aux_cnt) &&
-+					       ((aux_rssi - main_rssi < 5) ||
-+					       (main_rssi > aux_rssi));
-+				if (swat_tab->pre_ant == MAIN_ANT) {
-+					if (main_cnt == 0)
-+						target_ant = (aux_cnt != 0) ?
-+							     AUX_ANT :
-+							     swat_tab->pre_ant;
-+					else
-+						target_ant = cond_23d_main ?
-+							     AUX_ANT :
-+							     swat_tab->pre_ant;
-+				} else {
-+					if (aux_cnt == 0)
-+						target_ant = (main_cnt != 0) ?
-+							     MAIN_ANT :
-+							     swat_tab->pre_ant;
-+					else
-+						target_ant = cond_23d_aux ?
-+							     MAIN_ANT :
-+							     swat_tab->pre_ant;
-+				}
-+			} else {
-+				if (swat_tab->pre_ant == MAIN_ANT) {
-+					target_ant = (aux_rssi > main_rssi) ?
-+						     AUX_ANT :
-+						     swat_tab->pre_ant;
-+				} else if (swat_tab->pre_ant == AUX_ANT) {
-+					target_ant = (main_rssi > aux_rssi) ?
-+						     MAIN_ANT :
-+						     swat_tab->pre_ant;
-+				}
-+			}
-+		} else { /*@CCK only case*/
-+			main_cnt = fat_tab->main_cnt_cck[i];
-+			aux_cnt = fat_tab->aux_cnt_cck[i];
-+			main_rssi = (main_cnt != 0) ?
-+				    (fat_tab->main_sum_cck[i] / main_cnt) : 0;
-+			aux_rssi = (aux_cnt != 0) ?
-+				   (fat_tab->aux_sum_cck[i] / aux_cnt) : 0;
-+			target_ant = (main_rssi == aux_rssi) ?
-+				     swat_tab->pre_ant :
-+				     ((main_rssi >= aux_rssi) ?
-+				     MAIN_ANT : AUX_ANT);
-+				     /*Use RSSI for CCK only case*/
-+		}
-+		local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi;
-+		local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi;
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "***  CCK_counter_main = (( %d ))  , CCK_counter_aux= ((  %d ))\n",
-+			  fat_tab->main_cnt_cck[i], fat_tab->aux_cnt_cck[i]);
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "***  OFDM_counter_main = (( %d ))  , OFDM_counter_aux= ((  %d ))\n",
-+			  fat_tab->main_cnt[i], fat_tab->aux_cnt[i]);
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "***  main_Cnt = (( %d ))  , aux_Cnt   = (( %d ))\n",
-+			  main_cnt, aux_cnt);
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "***  main_rssi= ((  %d )) , aux_rssi = ((  %d ))\n",
-+			  main_rssi, aux_rssi);
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i,
-+			  (target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
-+
-+		/* @2 Select RX Idle Antenna */
-+
-+		if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {
-+			rx_idle_ant = target_ant;
-+			min_max_rssi = local_max_rssi;
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "*** local_max_rssi-local_min_rssi = ((%d))\n",
-+				  (local_max_rssi - local_min_rssi));
-+
-+			if ((local_max_rssi - local_min_rssi) > 8) {
-+				if (local_min_rssi != 0) {
-+					swat_tab->train_time_flag = 3;
-+				} else {
-+					if (min_max_rssi > RSSI_CHECK_THRESHOLD)
-+						swat_tab->train_time_flag = 0;
-+					else
-+						swat_tab->train_time_flag = 3;
-+				}
-+			} else if ((local_max_rssi - local_min_rssi) > 5) {
-+				swat_tab->train_time_flag = 2;
-+			} else if ((local_max_rssi - local_min_rssi) > 2) {
-+				swat_tab->train_time_flag = 1;
-+			} else {
-+				swat_tab->train_time_flag = 0;
-+			}
-+		}
-+
-+		/* @2 Select TX Antenna */
-+		if (target_ant == MAIN_ANT)
-+			fat_tab->antsel_a[i] = ANT1_2G;
-+		else
-+			fat_tab->antsel_a[i] = ANT2_2G;
-+
-+		phydm_antdiv_reset_statistic(dm, i);
-+		pkt_cnt_total += (main_cnt + aux_cnt);
-+	}
-+
-+	if (swat_tab->is_sw_ant_div_by_ctrl_frame) {
-+		odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_DETERMINE);
-+		is_by_ctrl_frame = true;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "Control frame packet counter = %d, data frame packet counter = %llu\n",
-+		  swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame, pkt_cnt_total);
-+
-+	if (min_max_rssi == 0xff || ((pkt_cnt_total <
-+	    (swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame >> 1)) &&
-+	    dm->phy_dbg_info.num_qry_beacon_pkt < 2)) {
-+		min_max_rssi = 0;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "Check RSSI of control frame because min_max_rssi == 0xff\n");
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "is_by_ctrl_frame = %d\n",
-+			  is_by_ctrl_frame);
-+
-+		if (is_by_ctrl_frame) {
-+			main_ctrl_cnt = fat_tab->main_ctrl_cnt;
-+			aux_ctrl_cnt = fat_tab->aux_ctrl_cnt;
-+			main_rssi = (main_ctrl_cnt != 0) ?
-+				    (fat_tab->main_ctrl_sum / main_ctrl_cnt) :
-+				    0;
-+			aux_rssi = (aux_ctrl_cnt != 0) ?
-+				   (fat_tab->aux_ctrl_sum / aux_ctrl_cnt) : 0;
-+
-+			if (main_ctrl_cnt <= 1 &&
-+			    fat_tab->cck_ctrl_frame_cnt_main >= 1)
-+				main_rssi = 0;
-+
-+			if (aux_ctrl_cnt <= 1 &&
-+			    fat_tab->cck_ctrl_frame_cnt_aux >= 1)
-+				aux_rssi = 0;
-+
-+			if (main_rssi != 0 || aux_rssi != 0) {
-+				rx_idle_ant = (main_rssi == aux_rssi) ?
-+					      swat_tab->pre_ant :
-+					      ((main_rssi >= aux_rssi) ?
-+					      MAIN_ANT : AUX_ANT);
-+				local_max_rssi = (main_rssi >= aux_rssi) ?
-+						 main_rssi : aux_rssi;
-+				local_min_rssi = (main_rssi >= aux_rssi) ?
-+						 aux_rssi : main_rssi;
-+
-+				if ((local_max_rssi - local_min_rssi) > 8)
-+					swat_tab->train_time_flag = 3;
-+				else if ((local_max_rssi - local_min_rssi) > 5)
-+					swat_tab->train_time_flag = 2;
-+				else if ((local_max_rssi - local_min_rssi) > 2)
-+					swat_tab->train_time_flag = 1;
-+				else
-+					swat_tab->train_time_flag = 0;
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "Control frame: main_rssi = %d, aux_rssi = %d\n",
-+					  main_rssi, aux_rssi);
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "rx_idle_ant decided by control frame = %s\n",
-+					  (rx_idle_ant == MAIN_ANT ?
-+					  "MAIN" : "AUX"));
-+			}
-+		}
-+	}
-+
-+	fat_tab->min_max_rssi = min_max_rssi;
-+	swat_tab->try_flag = SWAW_STEP_PEEK;
-+
-+	if (swat_tab->double_chk_flag == 1) {
-+		swat_tab->double_chk_flag = 0;
-+
-+		if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  " [Double check] min_max_rssi ((%d)) > %d again!!\n",
-+				  fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD);
-+
-+			odm_update_rx_idle_ant(dm, rx_idle_ant);
-+
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[reset try_flag = 0] Training accomplished !!!]\n\n\n");
-+		} else {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  " [Double check] min_max_rssi ((%d)) <= %d !!\n",
-+				  fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD);
-+
-+			next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?
-+				   AUX_ANT : MAIN_ANT;
-+			swat_tab->try_flag = SWAW_STEP_PEEK;
-+			swat_tab->reset_idx = RSSI_CHECK_RESET_PERIOD;
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[set try_flag=0]  Normal state:  Need to tryg again!!\n\n\n");
-+		}
-+	} else {
-+		if (fat_tab->min_max_rssi < RSSI_CHECK_THRESHOLD)
-+			swat_tab->reset_idx = RSSI_CHECK_RESET_PERIOD;
-+
-+		swat_tab->pre_ant = rx_idle_ant;
-+		odm_update_rx_idle_ant(dm, rx_idle_ant);
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[reset try_flag = 0] Training accomplished !!!]\n\n\n");
-+	}
-+}
-+
-+void odm_s0s1_sw_ant_div(void *dm_void, u8 step)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	u32 value32;
-+	u8 next_ant = 0;
-+
-+	if (!dm->is_linked) { /* @is_linked==False */
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
-+		if (fat_tab->is_become_linked == true) {
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
-+			if (dm->support_ic_type == ODM_RTL8723B) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "Set REG 948[9:6]=0x0\n");
-+				odm_set_bb_reg(dm, R_0x948, 0x3c0, 0x0);
-+			}
-+			fat_tab->is_become_linked = dm->is_linked;
-+		}
-+		return;
-+	} else {
-+		if (fat_tab->is_become_linked == false) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
-+
-+			if (dm->support_ic_type == ODM_RTL8723B) {
-+				value32 = odm_get_bb_reg(dm, R_0x864, 0x38);
-+
-+#if (RTL8723B_SUPPORT == 1)
-+				if (value32 == 0x0)
-+					odm_update_rx_idle_ant_8723b(dm,
-+								     MAIN_ANT,
-+								     ANT1_2G,
-+								     ANT2_2G);
-+				else if (value32 == 0x1)
-+					odm_update_rx_idle_ant_8723b(dm,
-+								     AUX_ANT,
-+								     ANT2_2G,
-+								     ANT1_2G);
-+#endif
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "8723B: First link! Force antenna to  %s\n",
-+					  (value32 == 0x0 ? "MAIN" : "AUX"));
-+			}
-+
-+			if (dm->support_ic_type == ODM_RTL8723D) {
-+				value32 = odm_get_bb_reg(dm, R_0x864, 0x38);
-+#if (RTL8723D_SUPPORT == 1)
-+				if (value32 == 0x0)
-+					odm_update_rx_idle_ant_8723d(dm,
-+								     MAIN_ANT,
-+								     ANT1_2G,
-+								     ANT2_2G);
-+				else if (value32 == 0x1)
-+					odm_update_rx_idle_ant_8723d(dm,
-+								     AUX_ANT,
-+								     ANT2_2G,
-+								     ANT1_2G);
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "8723D: First link! Force antenna to  %s\n",
-+					  (value32 == 0x0 ? "MAIN" : "AUX"));
-+#endif
-+			}
-+			if (dm->support_ic_type == ODM_RTL8710C) {
-+#if (RTL8710C_SUPPORT == 1)
-+				value32 = (HAL_READ32(SYSTEM_CTRL_BASE, R_0x121c) & 0x800000);
-+				if (value32 == 0x0)
-+					odm_update_rx_idle_ant_8710c(dm,
-+								     MAIN_ANT,
-+								     ANT1_2G,
-+								     ANT2_2G);
-+				else if (value32 == 0x1)
-+					odm_update_rx_idle_ant_8710c(dm,
-+								     AUX_ANT,
-+								     ANT2_2G,
-+								     ANT1_2G);
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "8710C: First link! Force antenna to  %s\n",
-+					  (value32 == 0x0 ? "MAIN" : "AUX"));
-+#endif
-+			}
-+			fat_tab->is_become_linked = dm->is_linked;
-+		}
-+	}
-+
-+	if (!(*fat_tab->p_force_tx_by_desc)) {
-+		if (dm->is_one_entry_only == true)
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
-+		else
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[%d] { try_flag=(( %d )), step=(( %d )), double_chk_flag = (( %d )) }\n",
-+		  __LINE__, swat_tab->try_flag, step,
-+		  swat_tab->double_chk_flag);
-+
-+	/* @ Handling step mismatch condition. */
-+	/* @ Peak step is not finished at last time. */
-+	/* @ Recover the variable and check again. */
-+	if (step != swat_tab->try_flag) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[step != try_flag]    Need to Reset After Link\n");
-+		odm_sw_ant_div_rest_after_link(dm);
-+	}
-+
-+	if (swat_tab->try_flag == SWAW_STEP_INIT) {
-+		swat_tab->try_flag = SWAW_STEP_PEEK;
-+		swat_tab->train_time_flag = 0;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[set try_flag = 0]  Prepare for peek!\n\n");
-+		return;
-+
-+	} else {
-+		/* @1 Normal state (Begin Trying) */
-+		if (swat_tab->try_flag == SWAW_STEP_PEEK) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), traffic_load = (%d))\n",
-+				  dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt,
-+				  dm->traffic_load);
-+			phydm_sw_antdiv_train_time(dm);
-+
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "Current min_max_rssi is ((%d))\n",
-+				  fat_tab->min_max_rssi);
-+
-+			/* @---reset index--- */
-+			if (swat_tab->reset_idx >= RSSI_CHECK_RESET_PERIOD) {
-+				fat_tab->min_max_rssi = 0;
-+				swat_tab->reset_idx = 0;
-+			}
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "reset_idx = (( %d ))\n",
-+				  swat_tab->reset_idx);
-+
-+			swat_tab->reset_idx++;
-+
-+			/* @---double check flag--- */
-+			if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD &&
-+			    swat_tab->double_chk_flag == 0) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  " min_max_rssi is ((%d)), and > %d\n",
-+					  fat_tab->min_max_rssi,
-+					  RSSI_CHECK_THRESHOLD);
-+
-+				swat_tab->double_chk_flag = 1;
-+				swat_tab->try_flag = SWAW_STEP_DETERMINE;
-+				swat_tab->rssi_trying = 0;
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "Test the current ant for (( %d )) ms again\n",
-+					  swat_tab->train_time);
-+				odm_update_rx_idle_ant(dm,
-+						       fat_tab->rx_idle_ant);
-+				odm_set_timer(dm, &swat_tab->sw_antdiv_timer,
-+					      swat_tab->train_time); /*@ms*/
-+				return;
-+			}
-+
-+			next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?
-+				   AUX_ANT : MAIN_ANT;
-+
-+			swat_tab->try_flag = SWAW_STEP_DETERMINE;
-+
-+			if (swat_tab->reset_idx <= 1)
-+				swat_tab->rssi_trying = 2;
-+			else
-+				swat_tab->rssi_trying = 1;
-+
-+			odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_PEEK);
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[set try_flag=1]  Normal state:  Begin Trying!!\n");
-+
-+		} else if ((swat_tab->try_flag == SWAW_STEP_DETERMINE) &&
-+			   (swat_tab->double_chk_flag == 0)) {
-+			next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ?
-+				   AUX_ANT : MAIN_ANT;
-+			swat_tab->rssi_trying--;
-+		}
-+
-+		/* @1 Decision state */
-+		if (swat_tab->try_flag == SWAW_STEP_DETERMINE &&
-+		    swat_tab->rssi_trying == 0) {
-+			phydm_sw_antdiv_decision(dm);
-+			return;
-+		}
-+	}
-+
-+	/* @1 4.Change TRX antenna */
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "rssi_trying = (( %d )),    ant: (( %s )) >>> (( %s ))\n",
-+		  swat_tab->rssi_trying,
-+		  (fat_tab->rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"),
-+		  (next_ant == MAIN_ANT ? "MAIN" : "AUX"));
-+
-+	odm_update_rx_idle_ant(dm, next_ant);
-+
-+	/* @1 5.Reset Statistics */
-+
-+	fat_tab->rx_idle_ant = next_ant;
-+
-+	if (dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710C) {
-+
-+		if (fat_tab->rx_idle_ant == MAIN_ANT) {
-+			fat_tab->main_sum[0] = 0;
-+			fat_tab->main_cnt[0] = 0;
-+			fat_tab->main_sum_cck[0] = 0;
-+			fat_tab->main_cnt_cck[0] = 0;
-+		} else {
-+			fat_tab->aux_sum[0] = 0;
-+			fat_tab->aux_cnt[0] = 0;
-+			fat_tab->aux_sum_cck[0] = 0;
-+			fat_tab->aux_cnt_cck[0] = 0;
-+		}
-+	}
-+
-+	if (dm->support_ic_type == ODM_RTL8188F) {
-+		if (dm->support_interface == ODM_ITRF_SDIO) {
-+			ODM_delay_us(200);
-+
-+			if (fat_tab->rx_idle_ant == MAIN_ANT) {
-+				fat_tab->main_sum[0] = 0;
-+				fat_tab->main_cnt[0] = 0;
-+				fat_tab->main_sum_cck[0] = 0;
-+				fat_tab->main_cnt_cck[0] = 0;
-+			} else {
-+				fat_tab->aux_sum[0] = 0;
-+				fat_tab->aux_cnt[0] = 0;
-+				fat_tab->aux_sum_cck[0] = 0;
-+				fat_tab->aux_cnt_cck[0] = 0;
-+			}
-+		}
-+	}
-+	/* @1 6.Set next timer   (Trying state) */
-+	PHYDM_DBG(dm, DBG_ANT_DIV, " Test ((%s)) ant for (( %d )) ms\n",
-+		  (next_ant == MAIN_ANT ? "MAIN" : "AUX"),
-+		  swat_tab->train_time);
-+	odm_set_timer(dm, &swat_tab->sw_antdiv_timer, swat_tab->train_time);
-+								/*@ms*/
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void odm_sw_antdiv_callback(struct phydm_timer_list *timer)
-+{
-+	void *adapter = (void *)timer->Adapter;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct sw_antenna_switch *swat_tab = &hal_data->DM_OutSrc.dm_swat_table;
-+
-+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+#if USE_WORKITEM
-+	odm_schedule_work_item(&swat_tab->phydm_sw_antenna_switch_workitem);
-+#else
-+	{
-+#if 0
-+		/* @dbg_print("SW_antdiv_Callback"); */
-+#endif
-+		odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);
-+	}
-+#endif
-+#else
-+	odm_schedule_work_item(&swat_tab->phydm_sw_antenna_switch_workitem);
-+#endif
-+}
-+
-+void odm_sw_antdiv_workitem_callback(void *context)
-+{
-+	void *adapter = (void *)context;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+
-+#if 0
-+	/* @dbg_print("SW_antdiv_Workitem_Callback"); */
-+#endif
-+	odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);
-+}
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+
-+void odm_sw_antdiv_workitem_callback(void *context)
-+{
-+	void *
-+		adapter = (void *)context;
-+	HAL_DATA_TYPE
-+	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+
-+#if 0
-+	/*@dbg_print("SW_antdiv_Workitem_Callback");*/
-+#endif
-+	odm_s0s1_sw_ant_div(&hal_data->odmpriv, SWAW_STEP_DETERMINE);
-+}
-+
-+void odm_sw_antdiv_callback(void *function_context)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)function_context;
-+	void *padapter = dm->adapter;
-+	if (*dm->is_net_closed == true)
-+		return;
-+
-+#if 0 /* @Can't do I/O in timer callback*/
-+	odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE);
-+#else
-+	rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback,
-+			      padapter);
-+#endif
-+}
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+void odm_sw_antdiv_callback(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "******AntDiv_Callback******\n");
-+	odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE);
-+}
-+#endif
-+
-+void odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	switch (step) {
-+	case SWAW_STEP_PEEK:
-+		swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame = 0;
-+		swat_tab->is_sw_ant_div_by_ctrl_frame = true;
-+		fat_tab->main_ctrl_cnt = 0;
-+		fat_tab->aux_ctrl_cnt = 0;
-+		fat_tab->main_ctrl_sum = 0;
-+		fat_tab->aux_ctrl_sum = 0;
-+		fat_tab->cck_ctrl_frame_cnt_main = 0;
-+		fat_tab->cck_ctrl_frame_cnt_aux = 0;
-+		fat_tab->ofdm_ctrl_frame_cnt_main = 0;
-+		fat_tab->ofdm_ctrl_frame_cnt_aux = 0;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n");
-+		break;
-+	case SWAW_STEP_DETERMINE:
-+		swat_tab->is_sw_ant_div_by_ctrl_frame = false;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "odm_S0S1_SwAntDivForAPMode(): Stop peek\n");
-+		break;
-+	default:
-+		swat_tab->is_sw_ant_div_by_ctrl_frame = false;
-+		break;
-+	}
-+}
-+
-+void odm_antsel_statistics_ctrl(void *dm_void, u8 antsel_tr_mux,
-+				u32 rx_pwdb_all)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	if (antsel_tr_mux == ANT1_2G) {
-+		fat_tab->main_ctrl_sum += rx_pwdb_all;
-+		fat_tab->main_ctrl_cnt++;
-+	} else {
-+		fat_tab->aux_ctrl_sum += rx_pwdb_all;
-+		fat_tab->aux_ctrl_cnt++;
-+	}
-+}
-+
-+void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void,
-+						    void *phy_info_void,
-+						    void *pkt_info_void
-+	/*	struct phydm_phyinfo_struct*		phy_info, */
-+	/*	struct phydm_perpkt_info_struct*		pktinfo */
-+	)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_phyinfo_struct *phy_info = NULL;
-+	struct phydm_perpkt_info_struct *pktinfo = NULL;
-+	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	u8 rssi_cck;
-+
-+	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
-+	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
-+
-+	if (!(dm->support_ability & ODM_BB_ANT_DIV))
-+		return;
-+
-+	if (dm->ant_div_type != S0S1_SW_ANTDIV)
-+		return;
-+
-+	/* @In try state */
-+	if (!swat_tab->is_sw_ant_div_by_ctrl_frame)
-+		return;
-+
-+	/* No HW error and match receiver address */
-+	if (!pktinfo->is_to_self)
-+		return;
-+
-+	swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame++;
-+
-+	if (pktinfo->is_cck_rate) {
-+		rssi_cck = phy_info->rx_mimo_signal_strength[RF_PATH_A];
-+		fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ?
-+					    ANT1_2G : ANT2_2G;
-+
-+		if (fat_tab->antsel_rx_keep_0 == ANT1_2G)
-+			fat_tab->cck_ctrl_frame_cnt_main++;
-+		else
-+			fat_tab->cck_ctrl_frame_cnt_aux++;
-+
-+		odm_antsel_statistics_ctrl(dm, fat_tab->antsel_rx_keep_0,
-+					   rssi_cck);
-+	} else {
-+		fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ?
-+					    ANT1_2G : ANT2_2G;
-+
-+		if (fat_tab->antsel_rx_keep_0 == ANT1_2G)
-+			fat_tab->ofdm_ctrl_frame_cnt_main++;
-+		else
-+			fat_tab->ofdm_ctrl_frame_cnt_aux++;
-+
-+		odm_antsel_statistics_ctrl(dm, fat_tab->antsel_rx_keep_0,
-+					   phy_info->rx_pwdb_all);
-+	}
-+}
-+
-+#endif /* @#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) */
-+
-+void odm_set_next_mac_addr_target(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	struct cmn_sta_info *entry;
-+	u32 value32, i;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "%s ==>\n", __func__);
-+
-+	if (dm->is_linked) {
-+		for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
-+			if ((fat_tab->train_idx + 1) == ODM_ASSOCIATE_ENTRY_NUM)
-+				fat_tab->train_idx = 0;
-+			else
-+				fat_tab->train_idx++;
-+
-+			entry = dm->phydm_sta_info[fat_tab->train_idx];
-+
-+			if (is_sta_active(entry)) {
-+				/*@Match MAC ADDR*/
-+				value32 = (entry->mac_addr[5] << 8) | entry->mac_addr[4];
-+
-+				odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, value32); /*@0x7b4~0x7b5*/
-+
-+				value32 = (entry->mac_addr[3] << 24) | (entry->mac_addr[2] << 16) | (entry->mac_addr[1] << 8) | entry->mac_addr[0];
-+
-+				odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, value32); /*@0x7b0~0x7b3*/
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "fat_tab->train_idx=%d\n",
-+					  fat_tab->train_idx);
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "Training MAC addr = %x:%x:%x:%x:%x:%x\n",
-+					  entry->mac_addr[5],
-+					  entry->mac_addr[4],
-+					  entry->mac_addr[3],
-+					  entry->mac_addr[2],
-+					  entry->mac_addr[1],
-+					  entry->mac_addr[0]);
-+
-+				break;
-+			}
-+		}
-+	}
-+}
-+
-+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+
-+void odm_fast_ant_training(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	u32 max_rssi_path_a = 0, pckcnt_path_a = 0;
-+	u8 i, target_ant_path_a = 0;
-+	boolean is_pkt_filter_macth_path_a = false;
-+#if (RTL8192E_SUPPORT == 1)
-+	u32 max_rssi_path_b = 0, pckcnt_path_b = 0;
-+	u8 target_ant_path_b = 0;
-+	boolean is_pkt_filter_macth_path_b = false;
-+#endif
-+
-+	if (!dm->is_linked) { /* @is_linked==False */
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
-+
-+		if (fat_tab->is_become_linked == true) {
-+			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
-+			phydm_fast_training_enable(dm, FAT_OFF);
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
-+			fat_tab->is_become_linked = dm->is_linked;
-+		}
-+		return;
-+	} else {
-+		if (fat_tab->is_become_linked == false) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked!!!]\n");
-+			fat_tab->is_become_linked = dm->is_linked;
-+		}
-+	}
-+
-+	if (!(*fat_tab->p_force_tx_by_desc)) {
-+		if (dm->is_one_entry_only == true)
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
-+		else
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
-+	}
-+
-+	if (dm->support_ic_type == ODM_RTL8188E)
-+		odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1));
-+#if (RTL8192E_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8192E) {
-+		odm_set_bb_reg(dm, R_0xb38, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1)); /* path-A  */ /* ant combination=regB38[2:0]+1 */
-+		odm_set_bb_reg(dm, R_0xb38, BIT(18) | BIT(17) | BIT(16), ((dm->fat_comb_b) - 1)); /* path-B  */ /* ant combination=regB38[18:16]+1 */
-+	}
-+#endif
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "==>%s\n", __func__);
-+
-+	/* @1 TRAINING STATE */
-+	if (fat_tab->fat_state == FAT_TRAINING_STATE) {
-+		/* @2 Caculate RSSI per Antenna */
-+
-+		/* @3 [path-A]--------------------------- */
-+		for (i = 0; i < (dm->fat_comb_a); i++) { /* @i : antenna index */
-+			if (fat_tab->ant_rssi_cnt[i] == 0)
-+				fat_tab->ant_ave_rssi[i] = 0;
-+			else {
-+				fat_tab->ant_ave_rssi[i] = fat_tab->ant_sum_rssi[i] / fat_tab->ant_rssi_cnt[i];
-+				is_pkt_filter_macth_path_a = true;
-+			}
-+
-+			if (fat_tab->ant_ave_rssi[i] > max_rssi_path_a) {
-+				max_rssi_path_a = fat_tab->ant_ave_rssi[i];
-+				pckcnt_path_a = fat_tab->ant_rssi_cnt[i];
-+				target_ant_path_a = i;
-+			} else if (fat_tab->ant_ave_rssi[i] == max_rssi_path_a) {
-+				if (fat_tab->ant_rssi_cnt[i] > pckcnt_path_a) {
-+					max_rssi_path_a = fat_tab->ant_ave_rssi[i];
-+					pckcnt_path_a = fat_tab->ant_rssi_cnt[i];
-+					target_ant_path_a = i;
-+				}
-+			}
-+
-+			PHYDM_DBG(
-+				  "*** ant-index : [ %d ],      counter = (( %d )),     Avg RSSI = (( %d ))\n",
-+				  i, fat_tab->ant_rssi_cnt[i],
-+				  fat_tab->ant_ave_rssi[i]);
-+		}
-+
-+#if 0
-+#if (RTL8192E_SUPPORT == 1)
-+		/* @3 [path-B]--------------------------- */
-+		for (i = 0; i < (dm->fat_comb_b); i++) {
-+			if (fat_tab->antRSSIcnt_pathB[i] == 0)
-+				fat_tab->antAveRSSI_pathB[i] = 0;
-+			else { /*  @(ant_rssi_cnt[i] != 0) */
-+				fat_tab->antAveRSSI_pathB[i] = fat_tab->antSumRSSI_pathB[i] / fat_tab->antRSSIcnt_pathB[i];
-+				is_pkt_filter_macth_path_b = true;
-+			}
-+			if (fat_tab->antAveRSSI_pathB[i] > max_rssi_path_b) {
-+				max_rssi_path_b = fat_tab->antAveRSSI_pathB[i];
-+				pckcnt_path_b = fat_tab->antRSSIcnt_pathB[i];
-+				target_ant_path_b = (u8)i;
-+			}
-+			if (fat_tab->antAveRSSI_pathB[i] == max_rssi_path_b) {
-+				if (fat_tab->antRSSIcnt_pathB > pckcnt_path_b) {
-+					max_rssi_path_b = fat_tab->antAveRSSI_pathB[i];
-+					target_ant_path_b = (u8)i;
-+				}
-+			}
-+			if (dm->fat_print_rssi == 1) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "***{path-B}: Sum RSSI[%d] = (( %d )),      cnt RSSI [%d] = (( %d )),     Avg RSSI[%d] = (( %d ))\n",
-+					  i, fat_tab->antSumRSSI_pathB[i], i,
-+					  fat_tab->antRSSIcnt_pathB[i], i,
-+					  fat_tab->antAveRSSI_pathB[i]);
-+			}
-+		}
-+#endif
-+#endif
-+
-+		/* @1 DECISION STATE */
-+
-+		/* @2 Select TRX Antenna */
-+
-+		phydm_fast_training_enable(dm, FAT_OFF);
-+
-+		/* @3 [path-A]--------------------------- */
-+		if (is_pkt_filter_macth_path_a == false) {
-+#if 0
-+			/* PHYDM_DBG(dm,DBG_ANT_DIV, "{path-A}: None Packet is matched\n"); */
-+#endif
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "{path-A}: None Packet is matched\n");
-+			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
-+		} else {
-+			PHYDM_DBG(
-+				  "target_ant_path_a = (( %d )) , max_rssi_path_a = (( %d ))\n",
-+				  target_ant_path_a, max_rssi_path_a);
-+
-+			/* @3 [ update RX-optional ant ]        Default RX is Omni, Optional RX is the best decision by FAT */
-+			if (dm->support_ic_type == ODM_RTL8188E)
-+				odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), target_ant_path_a);
-+			else if (dm->support_ic_type == ODM_RTL8192E)
-+				odm_set_bb_reg(dm, R_0xb38, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); /* Optional RX [pth-A] */
-+
-+			/* @3 [ update TX ant ] */
-+			odm_update_tx_ant(dm, target_ant_path_a, (fat_tab->train_idx));
-+
-+			if (target_ant_path_a == 0)
-+				odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
-+		}
-+#if 0
-+#if (RTL8192E_SUPPORT == 1)
-+		/* @3 [path-B]--------------------------- */
-+		if (is_pkt_filter_macth_path_b == false) {
-+			if (dm->fat_print_rssi == 1)
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "***[%d]{path-B}: None Packet is matched\n\n\n",
-+					  __LINE__);
-+		} else {
-+			if (dm->fat_print_rssi == 1) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  " ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\n\n\n",
-+					  target_ant_path_b, max_rssi_path_b);
-+			}
-+			odm_set_bb_reg(dm, R_0xb38, BIT(21) | BIT20 | BIT19, target_ant_path_b);	/* @Default RX is Omni, Optional RX is the best decision by FAT */
-+			odm_set_bb_reg(dm, R_0x80c, BIT(21), 1); /* Reg80c[21]=1'b1		//from TX Info */
-+
-+			fat_tab->antsel_pathB[fat_tab->train_idx] = target_ant_path_b;
-+		}
-+#endif
-+#endif
-+
-+		/* @2 Reset counter */
-+		for (i = 0; i < (dm->fat_comb_a); i++) {
-+			fat_tab->ant_sum_rssi[i] = 0;
-+			fat_tab->ant_rssi_cnt[i] = 0;
-+		}
-+		/*@
-+		#if (RTL8192E_SUPPORT == 1)
-+		for(i=0; i<=(dm->fat_comb_b); i++)
-+		{
-+			fat_tab->antSumRSSI_pathB[i] = 0;
-+			fat_tab->antRSSIcnt_pathB[i] = 0;
-+		}
-+		#endif
-+		*/
-+
-+		fat_tab->fat_state = FAT_PREPARE_STATE;
-+		return;
-+	}
-+
-+	/* @1 NORMAL STATE */
-+	if (fat_tab->fat_state == FAT_PREPARE_STATE) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[ Start Prepare state ]\n");
-+
-+		odm_set_next_mac_addr_target(dm);
-+
-+		/* @2 Prepare Training */
-+		fat_tab->fat_state = FAT_TRAINING_STATE;
-+		phydm_fast_training_enable(dm, FAT_ON);
-+		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
-+		/* @enable HW AntDiv */
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[Start Training state]\n");
-+
-+		odm_set_timer(dm, &dm->fast_ant_training_timer, dm->antdiv_intvl); /* @ms */
-+	}
-+}
-+
-+void odm_fast_ant_training_callback(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	if (*(dm->is_net_closed) == true)
-+		return;
-+#endif
-+
-+#if USE_WORKITEM
-+	odm_schedule_work_item(&dm->fast_ant_training_workitem);
-+#else
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__);
-+	odm_fast_ant_training(dm);
-+#endif
-+}
-+
-+void odm_fast_ant_training_work_item_callback(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__);
-+	odm_fast_ant_training(dm);
-+}
-+
-+#endif
-+
-+void odm_ant_div_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	struct sw_antenna_switch *swat_tab = &dm->dm_swat_table;
-+       u8 i;
-+	if (!(dm->support_ability & ODM_BB_ANT_DIV)) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[Return!!!]   Not Support Antenna Diversity Function\n");
-+		return;
-+	}
-+/* @--- */
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n");
-+		if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))
-+			return;
-+	} else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n");
-+		if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))
-+			return;
-+	} else if (fat_tab->ant_div_2g_5g == (ODM_ANTDIV_2G | ODM_ANTDIV_5G))
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n");
-+
-+#endif
-+	/* @--- */
-+
-+	/* @2 [--General---] */
-+	dm->antdiv_period = 0;
-+
-+	fat_tab->is_become_linked = false;
-+	fat_tab->ant_div_on_off = 0xff;
-+	
-+	for(i=0;i<3;i++) 
-+		fat_tab->ant_idx_vec[i]=i+1; /* initialize ant_idx_vec for SP3T */
-+	
-+
-+/* @3       -   AP   - */
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	odm_bdc_init(dm);
-+#endif
-+#endif
-+
-+/* @3     -   WIN   - */
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	swat_tab->ant_5g = MAIN_ANT;
-+	swat_tab->ant_2g = MAIN_ANT;
-+//#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+//	swat_tab->ant_2g = MAIN_ANT;
-+#endif
-+
-+	/* @2 [---Set MAIN_ANT as default antenna if Auto-ant enable---] */
-+	if (fat_tab->div_path_type == ANT_PATH_A)
-+		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
-+	else if (fat_tab->div_path_type == ANT_PATH_B)
-+		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
-+	else if (fat_tab->div_path_type == ANT_PATH_AB)
-+		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
-+
-+	dm->ant_type = ODM_AUTO_ANT;
-+
-+	fat_tab->rx_idle_ant = 0xff;
-+
-+	if (dm->support_ic_type == ODM_RTL8710C) {
-+		/* Soft ware*/
-+#if (RTL8710C_SUPPORT == 1)
-+		if (dm->ant_div_type == S0S1_SW_ANTDIV) {
-+			HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xdc, HAL_READ32(SYSTEM_CTRL_BASE, R_0xdc) | BIT18 | BIT17 | BIT16);
-+			HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xac, HAL_READ32(SYSTEM_CTRL_BASE, R_0xac) | BIT24 | BIT6);
-+			HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x10, 0x307);// 1: enable gpio db32 clock , 1: enable gpio pclock
-+			HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x08, 0x80000111);
-+			HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x1208, 0x800000);
-+		} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
-+			HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xdc, HAL_READ32(SYSTEM_CTRL_BASE, R_0xdc) | BIT18 | BIT17);
-+			HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xdc, HAL_READ32(SYSTEM_CTRL_BASE, R_0xdc) & (~BIT16));
-+			HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xac, HAL_READ32(SYSTEM_CTRL_BASE, R_0xac) | BIT24 | BIT6);
-+		} else {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				"[Return!!!] 8710C  Not Supprrt This AntDiv type\n");
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+			return;
-+		}
-+#endif 
-+	}
-+	
-+	/*to make RX-idle-antenna will be updated absolutly*/
-+	odm_update_rx_idle_ant(dm, MAIN_ANT);
-+	phydm_keep_rx_ack_ant_by_tx_ant_time(dm, 0);
-+	/* Timming issue: keep Rx ant after tx for ACK(5 x 3.2 mu = 16mu sec)*/
-+
-+	/* @2 [---Set TX Antenna---] */
-+	if (!fat_tab->p_force_tx_by_desc) {
-+		fat_tab->force_tx_by_desc = 0;
-+		fat_tab->p_force_tx_by_desc = &fat_tab->force_tx_by_desc;
-+	}
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "p_force_tx_by_desc = %d\n",
-+		  *fat_tab->p_force_tx_by_desc);
-+
-+	if (*fat_tab->p_force_tx_by_desc)
-+		odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
-+	else
-+		odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
-+
-+	/* @2 [--88E---] */
-+	if (dm->support_ic_type == ODM_RTL8188E) {
-+#if (RTL8188E_SUPPORT == 1)
-+		/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
-+		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
-+		/* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
-+
-+		if (dm->ant_div_type != CGCS_RX_HW_ANTDIV &&
-+		    dm->ant_div_type != CG_TRX_HW_ANTDIV &&
-+		    dm->ant_div_type != CG_TRX_SMART_ANTDIV) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[Return!!!]  88E Not Supprrt This AntDiv type\n");
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+			return;
-+		}
-+
-+		if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
-+			odm_rx_hw_ant_div_init_88e(dm);
-+		else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
-+			odm_trx_hw_ant_div_init_88e(dm);
-+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+		else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
-+			odm_smart_hw_ant_div_init_88e(dm);
-+#endif
-+#endif
-+	}
-+
-+/* @2 [--92E---] */
-+#if (RTL8192E_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8192E) {
-+		/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
-+		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
-+		/* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
-+
-+		if (dm->ant_div_type != CGCS_RX_HW_ANTDIV &&
-+		    dm->ant_div_type != CG_TRX_HW_ANTDIV &&
-+		    dm->ant_div_type != CG_TRX_SMART_ANTDIV) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[Return!!!]  8192E Not Supprrt This AntDiv type\n");
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+			return;
-+		}
-+
-+		if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
-+			odm_rx_hw_ant_div_init_92e(dm);
-+		else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
-+			odm_trx_hw_ant_div_init_92e(dm);
-+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+		else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
-+			odm_smart_hw_ant_div_init_92e(dm);
-+#endif
-+	}
-+#endif
-+
-+	/* @2 [--92F---] */
-+#if (RTL8192F_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8192F) {
-+	/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
-+	/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
-+	/* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
-+
-+	if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
-+		if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[Return!!!]  8192F Not Supprrt This AntDiv type\n");
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+			return;
-+		}
-+	}
-+	if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
-+		odm_rx_hw_ant_div_init_92f(dm);
-+	else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
-+	odm_trx_hw_ant_div_init_92f(dm);
-+	}
-+#endif
-+
-+#if (RTL8197F_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8197F) {
-+		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
-+
-+		if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[Return!!!]  8197F Not Supprrt This AntDiv type\n");
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+			return;
-+		}
-+		phydm_rx_hw_ant_div_init_97f(dm);
-+	}
-+#endif
-+
-+#if (RTL8197G_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8197G) {
-+		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
-+
-+		if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[Return!!!]  8197F Not Supprrt This AntDiv type\n");
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+			return;
-+		}
-+		phydm_rx_hw_ant_div_init_97g(dm);
-+	}
-+#endif
-+/* @2 [--8723B---] */
-+#if (RTL8723B_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8723B) {
-+		dm->ant_div_type = S0S1_SW_ANTDIV;
-+		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
-+
-+		if (dm->ant_div_type != S0S1_SW_ANTDIV &&
-+		    dm->ant_div_type != CG_TRX_HW_ANTDIV) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[Return!!!] 8723B  Not Supprrt This AntDiv type\n");
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+			return;
-+		}
-+
-+		if (dm->ant_div_type == S0S1_SW_ANTDIV)
-+			odm_s0s1_sw_ant_div_init_8723b(dm);
-+		else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
-+			odm_trx_hw_ant_div_init_8723b(dm);
-+	}
-+#endif
-+/*@2 [--8723D---]*/
-+#if (RTL8723D_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8723D) {
-+		if (fat_tab->p_default_s0_s1 == NULL) {
-+			fat_tab->default_s0_s1 = 1;
-+			fat_tab->p_default_s0_s1 = &fat_tab->default_s0_s1;
-+		}
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "default_s0_s1 = %d\n",
-+			  *fat_tab->p_default_s0_s1);
-+
-+		if (*fat_tab->p_default_s0_s1 == true)
-+			odm_update_rx_idle_ant(dm, MAIN_ANT);
-+		else
-+			odm_update_rx_idle_ant(dm, AUX_ANT);
-+
-+		if (dm->ant_div_type == S0S1_TRX_HW_ANTDIV)
-+			odm_trx_hw_ant_div_init_8723d(dm);
-+		else if (dm->ant_div_type == S0S1_SW_ANTDIV)
-+			odm_s0s1_sw_ant_div_init_8723d(dm);
-+		else {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				"[Return!!!] 8723D  Not Supprrt This AntDiv type\n");
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+			return;
-+		}
-+	}
-+#endif
-+#if (RTL8710C_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8710C) {
-+		if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
-+			odm_trx_hw_ant_div_init_8710c(dm);
-+		else if(dm->ant_div_type == S0S1_SW_ANTDIV){
-+			if (fat_tab->p_default_s0_s1 == NULL){
-+				fat_tab->default_s0_s1 = 1;
-+				fat_tab->p_default_s0_s1 = &fat_tab->default_s0_s1;
-+				}
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "default_s0_s1 = %d\n",
-+				*fat_tab->p_default_s0_s1);
-+			if (*fat_tab->p_default_s0_s1 == true)
-+				odm_update_rx_idle_ant(dm, MAIN_ANT);
-+			else
-+				odm_update_rx_idle_ant(dm, AUX_ANT);
-+			odm_s0s1_sw_ant_div_init_8710c(dm);
-+			}
-+	}
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8721D) {
-+		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
-+
-+		if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[Return!!!]  8721D Not Supprrt This AntDiv type\n");
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+			return;
-+		}
-+		if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
-+			odm_trx_hw_ant_div_init_8721d(dm);
-+	}
-+#endif
-+/* @2 [--8811A 8821A---] */
-+#if (RTL8821A_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8821) {
-+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
-+		dm->ant_div_type = HL_SW_SMART_ANT_TYPE1;
-+
-+		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
-+			odm_trx_hw_ant_div_init_8821a(dm);
-+			phydm_hl_smart_ant_type1_init_8821a(dm);
-+		} else
-+#endif
-+		{
-+#ifdef ODM_CONFIG_BT_COEXIST
-+			dm->ant_div_type = S0S1_SW_ANTDIV;
-+#else
-+			dm->ant_div_type = CG_TRX_HW_ANTDIV;
-+#endif
-+
-+			if (dm->ant_div_type != CG_TRX_HW_ANTDIV &&
-+			    dm->ant_div_type != S0S1_SW_ANTDIV) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "[Return!!!] 8821A & 8811A  Not Supprrt This AntDiv type\n");
-+				dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+				return;
-+			}
-+			if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
-+				odm_trx_hw_ant_div_init_8821a(dm);
-+			else if (dm->ant_div_type == S0S1_SW_ANTDIV)
-+				odm_s0s1_sw_ant_div_init_8821a(dm);
-+		}
-+	}
-+#endif
-+
-+/* @2 [--8821C---] */
-+#if (RTL8821C_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8821C) {
-+		dm->ant_div_type = S0S1_SW_ANTDIV;
-+		if (dm->ant_div_type != S0S1_SW_ANTDIV) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[Return!!!] 8821C  Not Supprrt This AntDiv type\n");
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+			return;
-+		}
-+		phydm_s0s1_sw_ant_div_init_8821c(dm);
-+		odm_trx_hw_ant_div_init_8821c(dm);
-+	}
-+#endif
-+
-+/* @2 [--8195B---] */
-+#if (RTL8195B_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8195B) {
-+		dm->ant_div_type = CG_TRX_HW_ANTDIV;
-+		if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[Return!!!] 8821C  Not Supprrt This AntDiv type\n");
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+			return;
-+		}
-+		odm_trx_hw_ant_div_init_8195b(dm);
-+	}
-+#endif
-+
-+/* @2 [--8881A---] */
-+#if (RTL8881A_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8881A) {
-+		/* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
-+		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
-+
-+		if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
-+			odm_trx_hw_ant_div_init_8881a(dm);
-+		} else {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[Return!!!] 8881A  Not Supprrt This AntDiv type\n");
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+			return;
-+		}
-+
-+		odm_trx_hw_ant_div_init_8881a(dm);
-+	}
-+#endif
-+
-+/* @2 [--8812---] */
-+#if (RTL8812A_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8812) {
-+		/* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
-+
-+		if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[Return!!!] 8812A  Not Supprrt This AntDiv type\n");
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+			return;
-+		}
-+		odm_trx_hw_ant_div_init_8812a(dm);
-+	}
-+#endif
-+
-+/*@[--8188F---]*/
-+#if (RTL8188F_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8188F) {
-+		dm->ant_div_type = S0S1_SW_ANTDIV;
-+		odm_s0s1_sw_ant_div_init_8188f(dm);
-+	}
-+#endif
-+
-+/*@[--8822B---]*/
-+#if (RTL8822B_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8822B) {
-+		dm->ant_div_type = CG_TRX_HW_ANTDIV;
-+
-+		if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[Return!!!]  8822B Not Supprrt This AntDiv type\n");
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+			return;
-+		}
-+		phydm_trx_hw_ant_div_init_22b(dm);
-+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
-+		dm->ant_div_type = HL_SW_SMART_ANT_TYPE2;
-+
-+		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2)
-+			phydm_hl_smart_ant_type2_init_8822b(dm);
-+#endif
-+	}
-+#endif
-+
-+/*@PHYDM_DBG(dm, DBG_ANT_DIV, "*** support_ic_type=[%lu]\n",*/
-+/*dm->support_ic_type);*/
-+/*PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv support_ability=[%lu]\n",*/
-+/*	  (dm->support_ability & ODM_BB_ANT_DIV)>>6);*/
-+/*PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv type=[%d]\n",dm->ant_div_type);*/
-+}
-+
-+void odm_ant_div(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	void *adapter = dm->adapter;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+#if (defined(CONFIG_HL_SMART_ANTENNA))
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+#endif
-+
-+	if (!(dm->support_ability & ODM_BB_ANT_DIV))
-+		return;
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	if (dm->is_linked) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "tp_active_occur=((%d)), evm_method_enable=((%d))\n",
-+			  dm->tp_active_occur, fat_tab->evm_method_enable);
-+
-+		if (dm->tp_active_occur == 1 &&
-+		    fat_tab->evm_method_enable == 1) {
-+			fat_tab->idx_ant_div_counter_5g = dm->antdiv_period;
-+			fat_tab->idx_ant_div_counter_2g = dm->antdiv_period;
-+		}
-+	}
-+#endif
-+
-+	if (*dm->band_type == ODM_BAND_5G) {
-+		if (fat_tab->idx_ant_div_counter_5g < dm->antdiv_period) {
-+			fat_tab->idx_ant_div_counter_5g++;
-+			return;
-+		} else
-+			fat_tab->idx_ant_div_counter_5g = 0;
-+	} else if (*dm->band_type == ODM_BAND_2_4G) {
-+		if (fat_tab->idx_ant_div_counter_2g < dm->antdiv_period) {
-+			fat_tab->idx_ant_div_counter_2g++;
-+			return;
-+		} else
-+			fat_tab->idx_ant_div_counter_2g = 0;
-+	}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE)
-+
-+	if (fat_tab->enable_ctrl_frame_antdiv) {
-+		if (dm->data_frame_num <= 10 && dm->is_linked)
-+			fat_tab->use_ctrl_frame_antdiv = 1;
-+		else
-+			fat_tab->use_ctrl_frame_antdiv = 0;
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n",
-+			  fat_tab->use_ctrl_frame_antdiv, dm->data_frame_num);
-+		dm->data_frame_num = 0;
-+	}
-+
-+	{
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+
-+		enum beamforming_cap beamform_cap = phydm_get_beamform_cap(dm);
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "is_bt_continuous_turn = ((%d))\n",
-+			  dm->is_bt_continuous_turn);
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ AntDiv Beam Cap ]   cap= ((%d))\n", beamform_cap);
-+		if (!dm->is_bt_continuous_turn) {
-+			if ((beamform_cap & BEAMFORMEE_CAP) &&
-+			    (!(*fat_tab->is_no_csi_feedback))) {
-+			    /* @BFmee On  &&   Div On->Div Off */
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "[ AntDiv : OFF ]   BFmee ==1; cap= ((%d))\n",
-+					  beamform_cap);
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "[ AntDiv BF]   is_no_csi_feedback= ((%d))\n",
-+					  *(fat_tab->is_no_csi_feedback));
-+				if (fat_tab->fix_ant_bfee == 0) {
-+					odm_ant_div_on_off(dm, ANTDIV_OFF,
-+							   ANT_PATH_A);
-+					fat_tab->fix_ant_bfee = 1;
-+				}
-+				return;
-+			} else { /* @BFmee Off   &&   Div Off->Div On */
-+				if (fat_tab->fix_ant_bfee == 1 &&
-+				    dm->is_linked) {
-+					PHYDM_DBG(dm, DBG_ANT_DIV,
-+						  "[ AntDiv : ON ]   BFmee ==0; cap=((%d))\n",
-+						  beamform_cap);
-+					PHYDM_DBG(dm, DBG_ANT_DIV,
-+						  "[ AntDiv BF]   is_no_csi_feedback= ((%d))\n",
-+						  *fat_tab->is_no_csi_feedback);
-+					if (dm->ant_div_type != S0S1_SW_ANTDIV)
-+						odm_ant_div_on_off(dm, ANTDIV_ON
-+								   , ANT_PATH_A)
-+								   ;
-+					fat_tab->fix_ant_bfee = 0;
-+				}
-+			}
-+		} else {
-+			if (fat_tab->div_path_type == ANT_PATH_A)
-+				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
-+			else if (fat_tab->div_path_type == ANT_PATH_B)
-+				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
-+			else if (fat_tab->div_path_type == ANT_PATH_AB)
-+				odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
-+		}
-+#endif
-+	}
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	/* @----------just for fool proof */
-+
-+	if (dm->antdiv_rssi)
-+		dm->debug_components |= DBG_ANT_DIV;
-+	else
-+		dm->debug_components &= ~DBG_ANT_DIV;
-+
-+	if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) {
-+		if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))
-+			return;
-+	} else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) {
-+		if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))
-+			return;
-+	}
-+#endif
-+
-+	/* @---------- */
-+
-+	if (dm->antdiv_select == 1)
-+		dm->ant_type = ODM_FIX_MAIN_ANT;
-+	else if (dm->antdiv_select == 2)
-+		dm->ant_type = ODM_FIX_AUX_ANT;
-+	else { /* @if (dm->antdiv_select==0) */
-+		dm->ant_type = ODM_AUTO_ANT;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+		/*Stop Antenna diversity for CMW500 testing case*/
-+		if (dm->consecutive_idlel_time >= 10) {
-+			dm->ant_type = ODM_FIX_MAIN_ANT;
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "[AntDiv: OFF] No TP case, consecutive_idlel_time=((%d))\n",
-+				  dm->consecutive_idlel_time);
-+		}
-+#endif
-+	}
-+
-+	/*PHYDM_DBG(dm, DBG_ANT_DIV,"ant_type= (%d), pre_ant_type= (%d)\n",*/
-+	/*dm->ant_type,dm->pre_ant_type); */
-+
-+	if (dm->ant_type != ODM_AUTO_ANT) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "Fix Antenna at (( %s ))\n",
-+			  (dm->ant_type == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX");
-+
-+		if (dm->ant_type != dm->pre_ant_type) {
-+			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
-+
-+			if (dm->ant_type == ODM_FIX_MAIN_ANT)
-+				odm_update_rx_idle_ant(dm, MAIN_ANT);
-+			else if (dm->ant_type == ODM_FIX_AUX_ANT)
-+				odm_update_rx_idle_ant(dm, AUX_ANT);
-+		}
-+		dm->pre_ant_type = dm->ant_type;
-+		return;
-+	} else {
-+		if (dm->ant_type != dm->pre_ant_type) {
-+			odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
-+		}
-+		dm->pre_ant_type = dm->ant_type;
-+	}
-+#if (defined(CONFIG_2T4R_ANTENNA))
-+	if (dm->ant_type2 != ODM_AUTO_ANT) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "PathB Fix Ant at (( %s ))\n",
-+			  (dm->ant_type2 == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX");
-+
-+		if (dm->ant_type2 != dm->pre_ant_type2) {
-+			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
-+
-+			if (dm->ant_type2 == ODM_FIX_MAIN_ANT)
-+				phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT);
-+			else if (dm->ant_type2 == ODM_FIX_AUX_ANT)
-+				phydm_update_rx_idle_ant_pathb(dm, AUX_ANT);
-+		}
-+		dm->pre_ant_type2 = dm->ant_type2;
-+		return;
-+	}
-+	if (dm->ant_type2 != dm->pre_ant_type2) {
-+		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
-+		odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
-+	}
-+	dm->pre_ant_type2 = dm->ant_type2;
-+
-+#endif
-+
-+/*@ ----------------------------------------------- */
-+/*@ [--8188E--] */
-+	if (dm->support_ic_type == ODM_RTL8188E) {
-+#if (RTL8188E_SUPPORT == 1)
-+		if (dm->ant_div_type == CG_TRX_HW_ANTDIV ||
-+		    dm->ant_div_type == CGCS_RX_HW_ANTDIV)
-+			odm_hw_ant_div(dm);
-+
-+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
-+	(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+		else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
-+			odm_fast_ant_training(dm);
-+#endif
-+
-+#endif
-+	}
-+/*@ [--8192E--] */
-+#if (RTL8192E_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8192E) {
-+		if (dm->ant_div_type == CGCS_RX_HW_ANTDIV ||
-+		    dm->ant_div_type == CG_TRX_HW_ANTDIV)
-+			odm_hw_ant_div(dm);
-+
-+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
-+	(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+		else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
-+			odm_fast_ant_training(dm);
-+#endif
-+	}
-+#endif
-+/*@ [--8197F--] */
-+#if (RTL8197F_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8197F) {
-+		if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
-+			odm_hw_ant_div(dm);
-+	}
-+#endif
-+
-+/*@ [--8197G--] */
-+#if (RTL8197G_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8197G) {
-+		if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
-+			odm_hw_ant_div(dm);
-+	}
-+#endif
-+
-+#if (RTL8723B_SUPPORT == 1)
-+/*@ [--8723B---] */
-+	else if (dm->support_ic_type == ODM_RTL8723B) {
-+		if (phydm_is_bt_enable_8723b(dm)) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "[BT is enable!!!]\n");
-+			if (fat_tab->is_become_linked == true) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "Set REG 948[9:6]=0x0\n");
-+				if (dm->support_ic_type == ODM_RTL8723B)
-+					odm_set_bb_reg(dm, R_0x948, 0x3c0, 0x0)
-+						       ;
-+
-+				fat_tab->is_become_linked = false;
-+			}
-+		} else {
-+			if (dm->ant_div_type == S0S1_SW_ANTDIV) {
-+				#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+				odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
-+				#endif
-+			} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
-+				odm_hw_ant_div(dm);
-+		}
-+	}
-+#endif
-+/*@ [--8723D--]*/
-+#if (RTL8723D_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8723D) {
-+		if (dm->ant_div_type == S0S1_SW_ANTDIV) {
-+			#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+			if (dm->antdiv_counter == CONFIG_ANTDIV_PERIOD) {
-+				odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
-+				dm->antdiv_counter--;
-+			} else {
-+				dm->antdiv_counter--;
-+			}
-+			if (dm->antdiv_counter == 0)
-+				dm->antdiv_counter = CONFIG_ANTDIV_PERIOD;
-+			#endif
-+		} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
-+			odm_hw_ant_div(dm);
-+		}
-+	}
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8721D) {
-+		if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
-+			odm_hw_ant_div(dm);
-+		}
-+	}
-+#endif
-+#if (RTL8710C_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8710C) {
-+		if (dm->ant_div_type == S0S1_SW_ANTDIV) {
-+			#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+			if (dm->antdiv_counter == CONFIG_ANTDIV_PERIOD) {
-+				odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
-+				dm->antdiv_counter--;
-+			} else {
-+				dm->antdiv_counter--;
-+			}
-+			if (dm->antdiv_counter == 0)
-+				dm->antdiv_counter = CONFIG_ANTDIV_PERIOD;
-+			#endif
-+		} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
-+			odm_hw_ant_div(dm);
-+		}
-+	}
-+#endif
-+/*@ [--8821A--] */
-+#if (RTL8821A_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8821) {
-+		#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
-+		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
-+			if (sat_tab->fix_beam_pattern_en != 0) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n",
-+					  sat_tab->fix_beam_pattern_codeword);
-+				/*return;*/
-+			} else {
-+				odm_fast_ant_training_hl_smart_antenna_type1(dm);
-+			}
-+
-+		} else
-+		#endif
-+		{
-+		#ifdef ODM_CONFIG_BT_COEXIST
-+			if (!dm->bt_info_table.is_bt_enabled) { /*@BT disabled*/
-+				if (dm->ant_div_type == S0S1_SW_ANTDIV) {
-+					dm->ant_div_type = CG_TRX_HW_ANTDIV;
-+					PHYDM_DBG(dm, DBG_ANT_DIV,
-+						  " [S0S1_SW_ANTDIV]  ->  [CG_TRX_HW_ANTDIV]\n");
-+					/*odm_set_bb_reg(dm, 0x8d4, BIT24, 1);*/
-+					if (fat_tab->is_become_linked == true)
-+						odm_ant_div_on_off(dm,
-+								   ANTDIV_ON,
-+								   ANT_PATH_A);
-+				}
-+
-+			} else { /*@BT enabled*/
-+
-+				if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
-+					dm->ant_div_type = S0S1_SW_ANTDIV;
-+					PHYDM_DBG(dm, DBG_ANT_DIV,
-+						  " [CG_TRX_HW_ANTDIV]  ->  [S0S1_SW_ANTDIV]\n");
-+					/*odm_set_bb_reg(dm, 0x8d4, BIT24, 0);*/
-+					odm_ant_div_on_off(dm, ANTDIV_OFF,
-+							   ANT_PATH_A);
-+				}
-+			}
-+		#endif
-+
-+			if (dm->ant_div_type == S0S1_SW_ANTDIV) {
-+				#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+				odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
-+				#endif
-+			} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
-+				odm_hw_ant_div(dm);
-+			}
-+		}
-+	}
-+#endif
-+
-+/*@ [--8821C--] */
-+#if (RTL8821C_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8821C) {
-+		if (!dm->is_bt_continuous_turn) {
-+			dm->ant_div_type = S0S1_SW_ANTDIV;
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "is_bt_continuous_turn = ((%d))   ==> SW AntDiv\n",
-+				  dm->is_bt_continuous_turn);
-+
-+		} else {
-+			dm->ant_div_type = CG_TRX_HW_ANTDIV;
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "is_bt_continuous_turn = ((%d))   ==> HW AntDiv\n",
-+				  dm->is_bt_continuous_turn);
-+			odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
-+		}
-+
-+		if (fat_tab->force_antdiv_type)
-+			dm->ant_div_type = fat_tab->antdiv_type_dbg;
-+
-+		if (dm->ant_div_type == S0S1_SW_ANTDIV) {
-+			#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+			odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
-+			#endif
-+		} else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
-+			odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
-+			odm_hw_ant_div(dm);
-+		}
-+	}
-+#endif
-+
-+/* @ [--8195B--] */
-+#if (RTL8195B_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8195B) {
-+		if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
-+			odm_hw_ant_div(dm);
-+		}
-+	}
-+#endif
-+
-+/* @ [--8881A--] */
-+#if (RTL8881A_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8881A)
-+		odm_hw_ant_div(dm);
-+#endif
-+
-+/*@ [--8812A--] */
-+#if (RTL8812A_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8812)
-+		odm_hw_ant_div(dm);
-+#endif
-+
-+#if (RTL8188F_SUPPORT == 1)
-+/*@ [--8188F--]*/
-+	else if (dm->support_ic_type == ODM_RTL8188F) {
-+		#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+		odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
-+		#endif
-+	}
-+#endif
-+
-+/*@ [--8822B--]*/
-+#if (RTL8822B_SUPPORT == 1)
-+	else if (dm->support_ic_type == ODM_RTL8822B) {
-+		if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
-+			odm_hw_ant_div(dm);
-+		#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
-+		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) {
-+			if (sat_tab->fix_beam_pattern_en != 0)
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n",
-+					  sat_tab->fix_beam_pattern_codeword);
-+			else
-+				phydm_fast_ant_training_hl_smart_antenna_type2(dm);
-+		}
-+		#endif
-+	}
-+#endif
-+}
-+
-+void odm_antsel_statistics(void *dm_void, void *phy_info_void,
-+			   u8 antsel_tr_mux, u32 mac_id, u32 utility, u8 method,
-+			   u8 is_cck_rate)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	struct phydm_phyinfo_struct *phy_info = NULL;
-+
-+	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
-+
-+	if (method == RSSI_METHOD) {
-+		if (is_cck_rate) {
-+			if (antsel_tr_mux == fat_tab->ant_idx_vec[0]-1) {
-+	/*to prevent u16 overflow, max(RSSI)=100, 65435+100 = 65535 (u16)*/
-+				if (fat_tab->main_sum_cck[mac_id] > 65435)
-+					return;
-+
-+				fat_tab->main_sum_cck[mac_id] += (u16)utility;
-+				fat_tab->main_cnt_cck[mac_id]++;
-+			} else {
-+				if (fat_tab->aux_sum_cck[mac_id] > 65435)
-+					return;
-+
-+				fat_tab->aux_sum_cck[mac_id] += (u16)utility;
-+				fat_tab->aux_cnt_cck[mac_id]++;
-+			}
-+
-+		} else { /*ofdm rate*/
-+
-+			if (antsel_tr_mux == fat_tab->ant_idx_vec[0]-1) {
-+				if (fat_tab->main_sum[mac_id] > 65435)
-+					return;
-+
-+				fat_tab->main_sum[mac_id] += (u16)utility;
-+				fat_tab->main_cnt[mac_id]++;
-+			} else {
-+				if (fat_tab->aux_sum[mac_id] > 65435)
-+					return;
-+
-+				fat_tab->aux_sum[mac_id] += (u16)utility;
-+				fat_tab->aux_cnt[mac_id]++;
-+			}
-+		}
-+	}
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	else if (method == EVM_METHOD) {
-+		if (!fat_tab->get_stats)
-+			return;
-+
-+		if (dm->rate_ss == 1) {
-+			phydm_statistics_evm_1ss(dm, phy_info, antsel_tr_mux,
-+						 mac_id, utility);
-+		} else { /*@>= 2SS*/
-+			phydm_statistics_evm_2ss(dm, phy_info, antsel_tr_mux,
-+						 mac_id, utility);
-+		}
-+
-+	} else if (method == CRC32_METHOD) {
-+		if (antsel_tr_mux == ANT1_2G) {
-+			fat_tab->main_crc32_ok_cnt += utility;
-+			fat_tab->main_crc32_fail_cnt++;
-+		} else {
-+			fat_tab->aux_crc32_ok_cnt += utility;
-+			fat_tab->aux_crc32_fail_cnt++;
-+		}
-+
-+	} else if (method == TP_METHOD) {
-+		if (!fat_tab->get_stats)
-+			return;
-+		if (utility <= ODM_RATEMCS15 && utility >= ODM_RATEMCS0) {
-+			if (antsel_tr_mux == ANT1_2G) {
-+				fat_tab->main_tp += (phy_rate_table[utility])
-+						    << 5;
-+				fat_tab->main_tp_cnt++;
-+			} else {
-+				fat_tab->aux_tp += (phy_rate_table[utility])
-+						   << 5;
-+				fat_tab->aux_tp_cnt++;
-+			}
-+		}
-+	}
-+#endif
-+}
-+
-+void odm_process_rssi_smart(void *dm_void, void *phy_info_void,
-+			    void *pkt_info_void, u8 rx_power_ant0)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_phyinfo_struct *phy_info = NULL;
-+	struct phydm_perpkt_info_struct *pktinfo = NULL;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
-+	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
-+
-+	if ((dm->support_ic_type & ODM_SMART_ANT_SUPPORT) &&
-+	    pktinfo->is_packet_to_self &&
-+	    fat_tab->fat_state == FAT_TRAINING_STATE) {
-+	/* @(pktinfo->is_packet_match_bssid && (!pktinfo->is_packet_beacon)) */
-+		u8 antsel_tr_mux;
-+
-+		antsel_tr_mux = (fat_tab->antsel_rx_keep_2 << 2) |
-+				(fat_tab->antsel_rx_keep_1 << 1) |
-+				fat_tab->antsel_rx_keep_0;
-+		fat_tab->ant_sum_rssi[antsel_tr_mux] += rx_power_ant0;
-+		fat_tab->ant_rssi_cnt[antsel_tr_mux]++;
-+	}
-+}
-+
-+void odm_process_rssi_normal(void *dm_void, void *phy_info_void,
-+			     void *pkt_info_void, u8 rx_pwr0)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_phyinfo_struct *phy_info = NULL;
-+	struct phydm_perpkt_info_struct *pktinfo = NULL;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	u8 rx_evm0, rx_evm1;
-+	boolean b_main;
-+
-+	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
-+	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
-+	rx_evm0 = phy_info->rx_mimo_signal_quality[0];
-+	rx_evm1 = phy_info->rx_mimo_signal_quality[1];
-+
-+	if (!(pktinfo->is_packet_to_self || fat_tab->use_ctrl_frame_antdiv))
-+		return;
-+
-+	if (dm->ant_div_type == S0S1_SW_ANTDIV) {
-+		if (pktinfo->is_cck_rate ||
-+		    dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8710C) {
-+
-+			b_main = (fat_tab->rx_idle_ant == MAIN_ANT);
-+			fat_tab->antsel_rx_keep_0 = b_main ? ANT1_2G : ANT2_2G;
-+		}
-+
-+		odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
-+				      pktinfo->station_id, rx_pwr0, RSSI_METHOD,
-+				      pktinfo->is_cck_rate);
-+	} else {
-+		odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
-+				      pktinfo->station_id, rx_pwr0, RSSI_METHOD,
-+				      pktinfo->is_cck_rate);
-+
-+		#ifdef ODM_EVM_ENHANCE_ANTDIV
-+		if (!(dm->support_ic_type & ODM_EVM_ANTDIV_IC))
-+			return;
-+		if (pktinfo->is_cck_rate)
-+			return;
-+
-+		odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
-+				      pktinfo->station_id, rx_evm0, EVM_METHOD,
-+				      pktinfo->is_cck_rate);
-+		odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0,
-+				      pktinfo->station_id, pktinfo->data_rate,
-+				      TP_METHOD, pktinfo->is_cck_rate);
-+		#endif
-+	}
-+}
-+
-+void odm_process_rssi_for_ant_div(void *dm_void, void *phy_info_void,
-+				  void *pkt_info_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_phyinfo_struct *phy_info = NULL;
-+	struct phydm_perpkt_info_struct *pktinfo = NULL;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+#if (defined(CONFIG_HL_SMART_ANTENNA))
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+	u32 beam_tmp;
-+	u8 next_ant;
-+	u8 train_pkt_number;
-+#endif
-+	boolean b_main;
-+	u8 rx_power_ant0, rx_power_ant1;
-+	u8 rx_evm_ant0, rx_evm_ant1;
-+	u8 rssi_avg;
-+	u64 rssi_linear = 0;
-+
-+	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
-+	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
-+	rx_power_ant0 = phy_info->rx_mimo_signal_strength[0];
-+	rx_power_ant1 = phy_info->rx_mimo_signal_strength[1];
-+	rx_evm_ant0 = phy_info->rx_mimo_signal_quality[0];
-+	rx_evm_ant1 = phy_info->rx_mimo_signal_quality[1];
-+
-+	if ((dm->support_ic_type & ODM_IC_2SS) && !pktinfo->is_cck_rate) {
-+		if (rx_power_ant1 < 100) {
-+			rssi_linear = phydm_db_2_linear(rx_power_ant0) +
-+				      phydm_db_2_linear(rx_power_ant1);
-+			/* @Rounding and removing fractional bits */
-+			rssi_linear = (rssi_linear +
-+				       (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
-+			/* @Calculate average RSSI */
-+			rssi_linear = DIVIDED_2(rssi_linear);
-+			/* @averaged PWDB */
-+			rssi_avg = (u8)odm_convert_to_db(rssi_linear);
-+		}
-+
-+	} else {
-+		rx_power_ant0 = (u8)phy_info->rx_pwdb_all;
-+		rssi_avg = rx_power_ant0;
-+	}
-+
-+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
-+	if ((dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) && (fat_tab->fat_state == FAT_TRAINING_STATE))
-+		phydm_process_rssi_for_hb_smtant_type2(dm, phy_info, pktinfo, rssi_avg); /*@for 8822B*/
-+	else
-+#endif
-+
-+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
-+#ifdef CONFIG_FAT_PATCH
-+		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1 && fat_tab->fat_state == FAT_TRAINING_STATE) {
-+		/*@[Beacon]*/
-+		if (pktinfo->is_packet_beacon) {
-+			sat_tab->beacon_counter++;
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "MatchBSSID_beacon_counter = ((%d))\n",
-+				  sat_tab->beacon_counter);
-+
-+			if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) {
-+				if (sat_tab->ant_num > 1) {
-+					next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
-+					odm_update_rx_idle_ant(dm, next_ant);
-+				}
-+
-+				sat_tab->update_beam_idx++;
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n",
-+					  sat_tab->pre_beacon_counter,
-+					  sat_tab->pkt_counter,
-+					  sat_tab->update_beam_idx);
-+
-+				sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
-+				sat_tab->pkt_counter = 0;
-+			}
-+		}
-+		/*@[data]*/
-+		else if (pktinfo->is_packet_to_self) {
-+			if (sat_tab->pkt_skip_statistic_en == 0) {
-+				/*@
-+				PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]:  antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
-+					pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0);
-+				*/
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n",
-+					  pktinfo->station_id,
-+					  sat_tab->pkt_counter,
-+					  fat_tab->antsel_rx_keep_0,
-+					  sat_tab->fast_training_beam_num,
-+					  rx_power_ant0);
-+
-+				sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0;
-+				sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++;
-+				sat_tab->pkt_counter++;
-+
-+#if 1
-+				train_pkt_number = sat_tab->beam_train_cnt[fat_tab->rx_idle_ant - 1][sat_tab->fast_training_beam_num];
-+#else
-+				train_pkt_number = sat_tab->per_beam_training_pkt_num;
-+#endif
-+
-+				/*Swich Antenna erery N pkts*/
-+				if (sat_tab->pkt_counter == train_pkt_number) {
-+					if (sat_tab->ant_num > 1) {
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number);
-+						next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
-+						odm_update_rx_idle_ant(dm, next_ant);
-+					}
-+
-+					sat_tab->update_beam_idx++;
-+					PHYDM_DBG(dm, DBG_ANT_DIV, "pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n",
-+						  sat_tab->pre_beacon_counter, sat_tab->update_beam_idx);
-+
-+					sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
-+					sat_tab->pkt_counter = 0;
-+				}
-+			}
-+		}
-+
-+		/*Swich Beam after switch "sat_tab->ant_num" antennas*/
-+		if (sat_tab->update_beam_idx == sat_tab->ant_num) {
-+			sat_tab->update_beam_idx = 0;
-+			sat_tab->pkt_counter = 0;
-+			beam_tmp = sat_tab->fast_training_beam_num;
-+
-+			if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
-+				fat_tab->fat_state = FAT_DECISION_STATE;
-+
-+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+				if (dm->support_interface == ODM_ITRF_PCIE)
-+					odm_fast_ant_training_hl_smart_antenna_type1(dm);
-+#endif
-+#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
-+				if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
-+					odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
-+#endif
-+
-+			} else {
-+				sat_tab->fast_training_beam_num++;
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "Update Beam_num (( %d )) -> (( %d ))\n",
-+					  beam_tmp,
-+					  sat_tab->fast_training_beam_num);
-+				phydm_set_all_ant_same_beam_num(dm);
-+
-+				fat_tab->fat_state = FAT_TRAINING_STATE;
-+			}
-+		}
-+	}
-+#else
-+
-+		if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
-+		if ((dm->support_ic_type & ODM_HL_SMART_ANT_TYPE1_SUPPORT) &&
-+		    pktinfo->is_packet_to_self &&
-+		    fat_tab->fat_state == FAT_TRAINING_STATE) {
-+			if (sat_tab->pkt_skip_statistic_en == 0) {
-+				/*@
-+				PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]:  antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
-+					pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0);
-+				*/
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "StaID[%d]:  antsel_pathA = ((%d)), is_packet_to_self = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
-+					  pktinfo->station_id,
-+					  fat_tab->antsel_rx_keep_0,
-+					  pktinfo->is_packet_to_self,
-+					  sat_tab->fast_training_beam_num,
-+					  rx_power_ant0);
-+
-+				sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0;
-+				sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++;
-+				sat_tab->pkt_counter++;
-+
-+				/*swich beam every N pkt*/
-+				if (sat_tab->pkt_counter >= sat_tab->per_beam_training_pkt_num) {
-+					sat_tab->pkt_counter = 0;
-+					beam_tmp = sat_tab->fast_training_beam_num;
-+
-+					if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
-+						fat_tab->fat_state = FAT_DECISION_STATE;
-+
-+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+						if (dm->support_interface == ODM_ITRF_PCIE)
-+							odm_fast_ant_training_hl_smart_antenna_type1(dm);
-+#endif
-+#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
-+						if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
-+							odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
-+#endif
-+
-+					} else {
-+						sat_tab->fast_training_beam_num++;
-+						phydm_set_all_ant_same_beam_num(dm);
-+
-+						fat_tab->fat_state = FAT_TRAINING_STATE;
-+						PHYDM_DBG(dm, DBG_ANT_DIV, "Update  Beam_num (( %d )) -> (( %d ))\n", beam_tmp, sat_tab->fast_training_beam_num);
-+					}
-+				}
-+			}
-+		}
-+	}
-+#endif
-+	else
-+#endif
-+		if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) {
-+			odm_process_rssi_smart(dm, phy_info, pktinfo,
-+					       rx_power_ant0);
-+		} else { /* @ant_div_type != CG_TRX_SMART_ANTDIV */
-+			odm_process_rssi_normal(dm, phy_info, pktinfo,
-+						rx_power_ant0);
-+		}
-+#if 0
-+/* PHYDM_DBG(dm,DBG_ANT_DIV,"is_cck_rate=%d, pwdb_all=%d\n",
-+ *	     pktinfo->is_cck_rate, phy_info->rx_pwdb_all);
-+ * PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=3'b%d%d%d\n",
-+ *	     fat_tab->antsel_rx_keep_2, fat_tab->antsel_rx_keep_1,
-+ *	     fat_tab->antsel_rx_keep_0);
-+ */
-+#endif
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
-+void odm_set_tx_ant_by_tx_info(void *dm_void, u8 *desc, u8 mac_id)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	if (!(dm->support_ability & ODM_BB_ANT_DIV))
-+		return;
-+
-+	if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
-+		return;
-+
-+	if (dm->support_ic_type == (ODM_RTL8723B | ODM_RTL8721D)) {
-+#if (RTL8723B_SUPPORT == 1 || RTL8721D_SUPPORT == 1)
-+		SET_TX_DESC_ANTSEL_A_8723B(desc, fat_tab->antsel_a[mac_id]);
-+/*PHYDM_DBG(dm,DBG_ANT_DIV,
-+ *	   "[8723B] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
-+ *	    mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
-+ *	    fat_tab->antsel_a[mac_id]);
-+ */
-+#endif
-+	} else if (dm->support_ic_type == ODM_RTL8821) {
-+#if (RTL8821A_SUPPORT == 1)
-+		SET_TX_DESC_ANTSEL_A_8812(desc, fat_tab->antsel_a[mac_id]);
-+/*PHYDM_DBG(dm,DBG_ANT_DIV,
-+ *	   "[8821A] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
-+ *	    mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
-+ *	    fat_tab->antsel_a[mac_id]);
-+ */
-+#endif
-+	} else if (dm->support_ic_type == ODM_RTL8188E) {
-+#if (RTL8188E_SUPPORT == 1)
-+		SET_TX_DESC_ANTSEL_A_88E(desc, fat_tab->antsel_a[mac_id]);
-+		SET_TX_DESC_ANTSEL_B_88E(desc, fat_tab->antsel_b[mac_id]);
-+		SET_TX_DESC_ANTSEL_C_88E(desc, fat_tab->antsel_c[mac_id]);
-+/*PHYDM_DBG(dm,DBG_ANT_DIV,
-+ *	   "[8188E] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
-+ *	    mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
-+ *	    fat_tab->antsel_a[mac_id]);
-+ */
-+#endif
-+	} else if (dm->support_ic_type == ODM_RTL8821C) {
-+#if (RTL8821C_SUPPORT == 1)
-+		SET_TX_DESC_ANTSEL_A_8821C(desc, fat_tab->antsel_a[mac_id]);
-+/*PHYDM_DBG(dm,DBG_ANT_DIV,
-+ *	   "[8821C] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
-+ *	    mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id],
-+ *	    fat_tab->antsel_a[mac_id]);
-+ */
-+#endif
-+	} else if (dm->support_ic_type == ODM_RTL8195B) {
-+#if (RTL8195B_SUPPORT == 1)
-+		SET_TX_DESC_ANTSEL_A_8195B(desc, fat_tab->antsel_a[mac_id]);
-+#endif
-+	} else if (dm->support_ic_type == ODM_RTL8822B) {
-+#if (RTL8822B_SUPPORT == 1)
-+		SET_TX_DESC_ANTSEL_A_8822B(desc, fat_tab->antsel_a[mac_id]);
-+#endif
-+
-+	}
-+}
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+
-+void odm_set_tx_ant_by_tx_info(
-+	struct rtl8192cd_priv *priv,
-+	struct tx_desc *pdesc,
-+	unsigned short aid)
-+{
-+	struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+
-+	if (!(dm->support_ability & ODM_BB_ANT_DIV))
-+		return;
-+
-+	if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
-+		return;
-+
-+	if (dm->support_ic_type == ODM_RTL8881A) {
-+#if 0
-+		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);	*/
-+#endif
-+		pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));
-+		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
-+	} else if (dm->support_ic_type == ODM_RTL8192E) {
-+#if 0
-+		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__);	*/
-+#endif
-+		pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));
-+		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
-+	} else if (dm->support_ic_type == ODM_RTL8197F) {
-+#if 0
-+		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__);	*/
-+#endif
-+		pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16)));
-+		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
-+	} else if (dm->support_ic_type == ODM_RTL8822B) {
-+		pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16)));
-+		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
-+	} else if (dm->support_ic_type == ODM_RTL8188E) {
-+#if 0
-+		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/
-+#endif
-+		pdesc->Dword2 &= set_desc(~BIT(24));
-+		pdesc->Dword2 &= set_desc(~BIT(25));
-+		pdesc->Dword7 &= set_desc(~BIT(29));
-+
-+		pdesc->Dword2 |= set_desc(fat_tab->antsel_a[aid] << 24);
-+		pdesc->Dword2 |= set_desc(fat_tab->antsel_b[aid] << 25);
-+		pdesc->Dword7 |= set_desc(fat_tab->antsel_c[aid] << 29);
-+
-+	} else if (dm->support_ic_type == ODM_RTL8812) {
-+		/*@[path-A]*/
-+#if 0
-+		/*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/
-+#endif
-+
-+		pdesc->Dword6 &= set_desc(~BIT(16));
-+		pdesc->Dword6 &= set_desc(~BIT(17));
-+		pdesc->Dword6 &= set_desc(~BIT(18));
-+
-+		pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
-+		pdesc->Dword6 |= set_desc(fat_tab->antsel_b[aid] << 17);
-+		pdesc->Dword6 |= set_desc(fat_tab->antsel_c[aid] << 18);
-+	}
-+}
-+
-+#if 1 /*@def CONFIG_WLAN_HAL*/
-+void odm_set_tx_ant_by_tx_info_hal(
-+	struct rtl8192cd_priv *priv,
-+	void *pdesc_data,
-+	u16 aid)
-+{
-+	struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	PTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data;
-+
-+	if (!(dm->support_ability & ODM_BB_ANT_DIV))
-+		return;
-+
-+	if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
-+		return;
-+
-+	if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8814A |
-+	    ODM_RTL8197F | ODM_RTL8822B)) {
-+#if 0
-+		/*panic_printk("[%s] [%d] **odm_set_tx_ant_by_tx_info_hal**\n",
-+		 *	       __FUNCTION__,__LINE__);
-+		 */
-+#endif
-+		pdescdata->ant_sel = 1;
-+		pdescdata->ant_sel_a = fat_tab->antsel_a[aid];
-+	}
-+}
-+#endif /*@#ifdef CONFIG_WLAN_HAL*/
-+
-+#endif
-+
-+void odm_ant_div_config(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "WIN Config Antenna Diversity\n");
-+	/*@
-+	if(dm->support_ic_type==ODM_RTL8723B)
-+	{
-+		if((!dm->swat_tab.ANTA_ON || !dm->swat_tab.ANTB_ON))
-+			dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+	}
-+	*/
-+	#if (defined(CONFIG_2T3R_ANTENNA))
-+	#if (RTL8822B_SUPPORT == 1)
-+		dm->rfe_type = ANT_2T3R_RFE_TYPE;
-+	#endif
-+	#endif
-+
-+	#if (defined(CONFIG_2T4R_ANTENNA))
-+	#if (RTL8822B_SUPPORT == 1)
-+		dm->rfe_type = ANT_2T4R_RFE_TYPE;
-+	#endif
-+	#endif
-+
-+	if (dm->support_ic_type == ODM_RTL8723D)
-+		dm->ant_div_type = S0S1_SW_ANTDIV;
-+#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "CE Config Antenna Diversity\n");
-+
-+	if (dm->support_ic_type == ODM_RTL8723B)
-+		dm->ant_div_type = S0S1_SW_ANTDIV;
-+
-+	if (dm->support_ic_type == ODM_RTL8723D)
-+		dm->ant_div_type = S0S1_SW_ANTDIV;
-+#elif (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "IOT Config Antenna Diversity\n");
-+
-+	if (dm->support_ic_type == ODM_RTL8721D)
-+		dm->ant_div_type = CG_TRX_HW_ANTDIV;
-+	if (dm->support_ic_type == ODM_RTL8710C){
-+		if(dm->cut_version >  ODM_CUT_C)
-+			dm->ant_div_type = CG_TRX_HW_ANTDIV;
-+		else
-+			dm->ant_div_type = S0S1_SW_ANTDIV;
-+	}
-+
-+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "AP Config Antenna Diversity\n");
-+
-+	/* @2 [ NOT_SUPPORT_ANTDIV ] */
-+#if (defined(CONFIG_NOT_SUPPORT_ANTDIV))
-+	dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n");
-+
-+	/* @2 [ 2G&5G_SUPPORT_ANTDIV ] */
-+#elif (defined(CONFIG_2G5G_SUPPORT_ANTDIV))
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously\n");
-+	fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G | ODM_ANTDIV_5G);
-+
-+	if (dm->support_ic_type & ODM_ANTDIV_SUPPORT)
-+		dm->support_ability |= ODM_BB_ANT_DIV;
-+	if (*dm->band_type == ODM_BAND_5G) {
-+	#if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))
-+		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
-+		panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
-+	#elif (defined(CONFIG_5G_CG_TRX_DIVERSITY) ||\
-+		defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))
-+		dm->ant_div_type = CG_TRX_HW_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
-+		panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
-+	#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
-+		dm->ant_div_type = CG_TRX_SMART_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n");
-+	#elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))
-+		dm->ant_div_type = S0S1_SW_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n");
-+	#endif
-+	} else if (*dm->band_type == ODM_BAND_2_4G) {
-+	#if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))
-+		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
-+	#elif (defined(CONFIG_2G_CG_TRX_DIVERSITY) ||\
-+		defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))
-+		dm->ant_div_type = CG_TRX_HW_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
-+	#elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+		dm->ant_div_type = CG_TRX_SMART_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n");
-+	#elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))
-+		dm->ant_div_type = S0S1_SW_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n");
-+	#endif
-+	}
-+
-+	/* @2 [ 5G_SUPPORT_ANTDIV ] */
-+#elif (defined(CONFIG_5G_SUPPORT_ANTDIV))
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n");
-+	panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n");
-+	fat_tab->ant_div_2g_5g = (ODM_ANTDIV_5G);
-+	if (*dm->band_type == ODM_BAND_5G) {
-+		if (dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)
-+			dm->support_ability |= ODM_BB_ANT_DIV;
-+	#if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))
-+		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
-+		panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
-+	#elif (defined(CONFIG_5G_CG_TRX_DIVERSITY))
-+		dm->ant_div_type = CG_TRX_HW_ANTDIV;
-+		panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
-+	#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
-+		dm->ant_div_type = CG_TRX_SMART_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n");
-+	#elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))
-+		dm->ant_div_type = S0S1_SW_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n");
-+	#endif
-+	} else if (*dm->band_type == ODM_BAND_2_4G) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 2G ant_div_type\n");
-+		dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+	}
-+
-+	/* @2 [ 2G_SUPPORT_ANTDIV ] */
-+#elif (defined(CONFIG_2G_SUPPORT_ANTDIV))
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n");
-+	fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G);
-+	if (*dm->band_type == ODM_BAND_2_4G) {
-+		if (dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)
-+			dm->support_ability |= ODM_BB_ANT_DIV;
-+	#if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))
-+		dm->ant_div_type = CGCS_RX_HW_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
-+	#elif (defined(CONFIG_2G_CG_TRX_DIVERSITY))
-+		dm->ant_div_type = CG_TRX_HW_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
-+	#elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+		dm->ant_div_type = CG_TRX_SMART_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n");
-+	#elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))
-+		dm->ant_div_type = S0S1_SW_ANTDIV;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n");
-+	#endif
-+	} else if (*dm->band_type == ODM_BAND_5G) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 5G ant_div_type\n");
-+		dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+	}
-+#endif
-+
-+	if (!(dm->support_ic_type & ODM_ANTDIV_SUPPORT_IC)) {
-+		fat_tab->ant_div_2g_5g = 0;
-+		dm->support_ability &= ~(ODM_BB_ANT_DIV);
-+	}
-+#endif
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n",
-+		  ((dm->support_ability & ODM_BB_ANT_DIV) ? 1 : 0));
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[AntDiv Config Info] be_fix_tx_ant = ((%d))\n",
-+		  dm->dm_fat_table.b_fix_tx_ant);
-+}
-+
-+void odm_ant_div_timers(void *dm_void, u8 state)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	if (state == INIT_ANTDIV_TIMMER) {
-+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+		odm_initialize_timer(dm,
-+				     &dm->dm_swat_table.sw_antdiv_timer,
-+				     (void *)odm_sw_antdiv_callback, NULL,
-+				     "sw_antdiv_timer");
-+#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
-+	(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+		odm_initialize_timer(dm, &dm->fast_ant_training_timer,
-+				     (void *)odm_fast_ant_training_callback,
-+				     NULL, "fast_ant_training_timer");
-+#endif
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+		odm_initialize_timer(dm, &dm->evm_fast_ant_training_timer,
-+				     (void *)phydm_evm_antdiv_callback, NULL,
-+				     "evm_fast_ant_training_timer");
-+#endif
-+	} else if (state == CANCEL_ANTDIV_TIMMER) {
-+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+		odm_cancel_timer(dm,
-+				 &dm->dm_swat_table.sw_antdiv_timer);
-+#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
-+	(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+		odm_cancel_timer(dm, &dm->fast_ant_training_timer);
-+#endif
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+		odm_cancel_timer(dm, &dm->evm_fast_ant_training_timer);
-+#endif
-+	} else if (state == RELEASE_ANTDIV_TIMMER) {
-+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+		odm_release_timer(dm,
-+				  &dm->dm_swat_table.sw_antdiv_timer);
-+#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
-+	(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+		odm_release_timer(dm, &dm->fast_ant_training_timer);
-+#endif
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+		odm_release_timer(dm, &dm->evm_fast_ant_training_timer);
-+#endif
-+	}
-+}
-+
-+void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used,
-+			char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct	*fat_tab = &dm->dm_fat_table;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 dm_value[10] = {0};
-+	char help[] = "-h";
-+	u8 i, input_idx = 0;
-+
-+	for (i = 0; i < 5; i++) {
-+		if (input[i + 1]) {
-+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
-+			input_idx++;
-+		}
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{1} {0:auto, 1:fix main, 2:fix auto}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{2} {antdiv_period}\n");
-+		#if (RTL8821C_SUPPORT == 1)
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{3} {en} {0:Default, 1:HW_Div, 2:SW_Div}\n");
-+		#endif
-+
-+	} else if (dm_value[0] == 1) {
-+	/*@fixed or auto antenna*/
-+		if (dm_value[1] == 0) {
-+			dm->ant_type = ODM_AUTO_ANT;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "AntDiv: Auto\n");
-+		} else if (dm_value[1] == 1) {
-+			dm->ant_type = ODM_FIX_MAIN_ANT;
-+			
-+		#if (RTL8710C_SUPPORT == 1)
-+			dm->antdiv_select = 1;
-+		#endif
-+		
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "AntDiv: Fix Main\n");
-+		} else if (dm_value[1] == 2) {
-+			dm->ant_type = ODM_FIX_AUX_ANT;
-+			
-+		#if (RTL8710C_SUPPORT == 1)
-+			dm->antdiv_select = 2;
-+		#endif
-+		
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "AntDiv: Fix Aux\n");
-+		}
-+
-+		if (dm->ant_type != ODM_AUTO_ANT) {
-+			odm_stop_antenna_switch_dm(dm);
-+			if (dm->ant_type == ODM_FIX_MAIN_ANT)
-+				odm_update_rx_idle_ant(dm, MAIN_ANT);
-+			else if (dm->ant_type == ODM_FIX_AUX_ANT)
-+				odm_update_rx_idle_ant(dm, AUX_ANT);
-+		} else {
-+			phydm_enable_antenna_diversity(dm);
-+		}
-+		dm->pre_ant_type = dm->ant_type;
-+	} else if (dm_value[0] == 2) {
-+	/*@dynamic period for AntDiv*/
-+		dm->antdiv_period = (u8)dm_value[1];
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "AntDiv_period=((%d))\n", dm->antdiv_period);
-+	}
-+	#if (RTL8821C_SUPPORT == 1)
-+	else if (dm_value[0] == 3 &&
-+		 dm->support_ic_type == ODM_RTL8821C) {
-+		/*Only for 8821C*/
-+		if (dm_value[1] == 0) {
-+			fat_tab->force_antdiv_type = false;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[8821C] AntDiv: Default\n");
-+		} else if (dm_value[1] == 1) {
-+			fat_tab->force_antdiv_type = true;
-+			fat_tab->antdiv_type_dbg = CG_TRX_HW_ANTDIV;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[8821C] AntDiv: HW diversity\n");
-+		} else if (dm_value[1] == 2) {
-+			fat_tab->force_antdiv_type = true;
-+			fat_tab->antdiv_type_dbg = S0S1_SW_ANTDIV;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[8821C] AntDiv: SW diversity\n");
-+		}
-+	}
-+	#endif
-+	#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	else if (dm_value[0] == 4) {
-+		if (dm_value[1] == 0) {
-+			/*@init parameters for EVM AntDiv*/
-+			phydm_evm_sw_antdiv_init(dm);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "init evm antdiv parameters\n");
-+		} else if (dm_value[1] == 1) {
-+			/*training number for EVM AntDiv*/
-+			dm->antdiv_train_num = (u8)dm_value[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "antdiv_train_num = ((%d))\n",
-+				 dm->antdiv_train_num);
-+		} else if (dm_value[1] == 2) {
-+			/*training interval for EVM AntDiv*/
-+			dm->antdiv_intvl = (u8)dm_value[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "antdiv_intvl = ((%d))\n",
-+				 dm->antdiv_intvl);
-+		} else if (dm_value[1] == 3) {
-+			/*@function period for EVM AntDiv*/
-+			dm->evm_antdiv_period = (u8)dm_value[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "evm_antdiv_period = ((%d))\n",
-+				 dm->evm_antdiv_period);
-+		} else if (dm_value[1] == 100) {/*show parameters*/
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "ant_type = ((%d))\n", dm->ant_type);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "antdiv_train_num = ((%d))\n",
-+				 dm->antdiv_train_num);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "antdiv_intvl = ((%d))\n",
-+				 dm->antdiv_intvl);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "evm_antdiv_period = ((%d))\n",
-+				 dm->evm_antdiv_period);
-+		}
-+	}
-+	#ifdef CONFIG_2T4R_ANTENNA
-+	else if (dm_value[0] == 5) { /*Only for 8822B 2T4R case*/
-+
-+		if (dm_value[1] == 0) {
-+			dm->ant_type2 = ODM_AUTO_ANT;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "AntDiv: PathB Auto\n");
-+		} else if (dm_value[1] == 1) {
-+			dm->ant_type2 = ODM_FIX_MAIN_ANT;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "AntDiv: PathB Fix Main\n");
-+		} else if (dm_value[1] == 2) {
-+			dm->ant_type2 = ODM_FIX_AUX_ANT;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "AntDiv: PathB Fix Aux\n");
-+		}
-+
-+		if (dm->ant_type2 != ODM_AUTO_ANT) {
-+			odm_stop_antenna_switch_dm(dm);
-+			if (dm->ant_type2 == ODM_FIX_MAIN_ANT)
-+				phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT);
-+			else if (dm->ant_type2 == ODM_FIX_AUX_ANT)
-+				phydm_update_rx_idle_ant_pathb(dm, AUX_ANT);
-+		} else {
-+			phydm_enable_antenna_diversity(dm);
-+		}
-+		dm->pre_ant_type2 = dm->ant_type2;
-+	}
-+	#endif
-+	#endif
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void odm_ant_div_reset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ability & ODM_BB_ANT_DIV))
-+		return;
-+
-+	#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+	if (dm->ant_div_type == S0S1_SW_ANTDIV)
-+		odm_s0s1_sw_ant_div_reset(dm);
-+	#endif
-+}
-+
-+void odm_antenna_diversity_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	odm_ant_div_config(dm);
-+	odm_ant_div_init(dm);
-+}
-+
-+void odm_antenna_diversity(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (*dm->mp_mode)
-+		return;
-+
-+	if (!(dm->support_ability & ODM_BB_ANT_DIV)) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[Return!!!]   Not Support Antenna Diversity Function\n");
-+		return;
-+	}
-+
-+	if (dm->pause_ability & ODM_BB_ANT_DIV) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "Return: Pause AntDIv in LV=%d\n",
-+			  dm->pause_lv_table.lv_antdiv);
-+		return;
-+	}
-+
-+	odm_ant_div(dm);
-+}
-+#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_antdiv.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_antdiv.h
-new file mode 100644
-index 000000000000..df6d60521267
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_antdiv.h
-@@ -0,0 +1,547 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDMANTDIV_H__
-+#define __PHYDMANTDIV_H__
-+
-+/*@#define ANTDIV_VERSION	"2.0"  //2014.11.04*/
-+/*@#define ANTDIV_VERSION	"2.1"  //2015.01.13  Dino*/
-+/*@#define ANTDIV_VERSION	"2.2"  2015.01.16  Dino*/
-+/*@#define ANTDIV_VERSION	"3.1"  2015.07.29  YuChen,remove 92c 92d 8723a*/
-+/*@#define ANTDIV_VERSION	"3.2"  2015.08.11  Stanley, disable antenna*/
-+				/*@diversity when BT is enable for 8723B*/
-+/*@#define ANTDIV_VERSION	"3.3"  2015.08.12  Stanley. 8723B does not*/
-+				/*@need to check the antenna is control by BT,*/
-+				/*@because antenna diversity only works when */
-+				/*@BT is disable or radio off*/
-+/*@#define ANTDIV_VERSION	"3.4"  2015.08.28 Dino 1.Add 8821A Smart */
-+				/*@Antenna 2. Add 8188F SW S0S1 Antenna*/
-+				/*@Diversity*/
-+/*@#define ANTDIV_VERSION	"3.5"  2015.10.07 Stanley Always check antenna*/
-+				/*@detection result from BT-coex. for 8723B,*/
-+				/*@not from PHYDM*/
-+/*@#define ANTDIV_VERSION	"3.6"*/ /*@2015.11.16  Stanley  */
-+/*@#define ANTDIV_VERSION	"3.7"  2015.11.20 Dino Add SmartAnt FAT Patch */
-+/*@#define ANTDIV_VERSION	"3.8"  2015.12.21 Dino, Add SmartAnt dynamic*/
-+				/*@training packet num */
-+/*@#define ANTDIV_VERSION	"3.9"  2016.01.05 Dino, Add SmartAnt cmd for*/
-+				/*@converting single & two smtant, and add cmd*/
-+				/*@for adjust truth table */
-+#define ANTDIV_VERSION "4.0"	/*@2017.05.25  Mark, Add SW antenna diversity*/
-+				/*@for 8821c because HW transient issue */
-+
-+/* @1 ============================================================
-+ * 1  Definition
-+ * 1 ============================================================
-+ */
-+
-+#define	ANTDIV_INIT		0xff
-+#define	MAIN_ANT	1		/*@ant A or ant Main   or S1*/
-+#define	AUX_ANT		2		/*@AntB or ant Aux   or S0*/
-+#define	MAX_ANT		3		/* @3 for AP using*/
-+
-+#define ANT1_2G 0
-+/* @= ANT2_5G for 8723D  BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */
-+#define ANT2_2G 1
-+/* @= ANT1_5G for 8723D  BTG S0  RX S0S1 diversity for 8723D, TX fixed at S1 */
-+/*smart antenna*/
-+#define SUPPORT_RF_PATH_NUM 4
-+#define SUPPORT_BEAM_PATTERN_NUM 4
-+#define NUM_ANTENNA_8821A	2
-+
-+#define SUPPORT_BEAM_SET_PATTERN_NUM		16
-+
-+#define	NO_FIX_TX_ANT		0
-+#define	FIX_TX_AT_MAIN	1
-+#define	FIX_AUX_AT_MAIN	2
-+
-+/* @Antenna Diversty Control type */
-+#define	ODM_AUTO_ANT		0
-+#define	ODM_FIX_MAIN_ANT	1
-+#define	ODM_FIX_AUX_ANT	2
-+
-+#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\
-+			ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A |\
-+			ODM_RTL8197F | ODM_RTL8721D | ODM_RTL8710C)
-+#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\
-+			ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B |\
-+			ODM_RTL8195B)
-+#define ODM_JGR3_ANTDIV_SUPPORT ODM_RTL8197G
-+#define ODM_ANTDIV_SUPPORT	(ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT |\
-+			ODM_JGR3_ANTDIV_SUPPORT)
-+#define ODM_SMART_ANT_SUPPORT	(ODM_RTL8188E | ODM_RTL8192E)
-+#define ODM_HL_SMART_ANT_TYPE1_SUPPORT		(ODM_RTL8821 | ODM_RTL8822B)
-+
-+#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\
-+			ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D |\
-+			ODM_RTL8197F | ODM_RTL8197G)
-+#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\
-+			ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8195B)
-+
-+#define ODM_ANTDIV_SUPPORT_IC (ODM_ANTDIV_2G_SUPPORT_IC | ODM_ANTDIV_5G_SUPPORT_IC)
-+
-+#define ODM_EVM_ANTDIV_IC (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8822B |\
-+			ODM_RTL8197G)
-+
-+#define ODM_ANTDIV_2G	BIT(0)
-+#define ODM_ANTDIV_5G	BIT(1)
-+
-+#define ANTDIV_ON	1
-+#define ANTDIV_OFF	0
-+
-+#define ANT_PATH_A	0
-+#define ANT_PATH_B	1
-+#define ANT_PATH_AB	2
-+
-+#define FAT_ON	1
-+#define FAT_OFF	0
-+
-+#define TX_BY_DESC	1
-+#define TX_BY_REG	0
-+
-+#define RSSI_METHOD	0
-+#define EVM_METHOD		1
-+#define CRC32_METHOD	2
-+#define TP_METHOD		3
-+
-+#define INIT_ANTDIV_TIMMER		0
-+#define CANCEL_ANTDIV_TIMMER	1
-+#define RELEASE_ANTDIV_TIMMER	2
-+
-+#define CRC32_FAIL	1
-+#define CRC32_OK	0
-+
-+#define evm_rssi_th_high	25
-+#define evm_rssi_th_low	20
-+
-+#define NORMAL_STATE_MIAN	1
-+#define NORMAL_STATE_AUX	2
-+#define TRAINING_STATE		3
-+
-+#define FORCE_RSSI_DIFF 10
-+
-+#define HT_IDX 16
-+#define VHT_IDX 20
-+
-+#define CSI_ON	1
-+#define CSI_OFF	0
-+
-+#define DIVON_CSIOFF 1
-+#define DIVOFF_CSION 2
-+
-+#define BDC_DIV_TRAIN_STATE	0
-+#define bdc_bfer_train_state	1
-+#define BDC_DECISION_STATE		2
-+#define BDC_BF_HOLD_STATE		3
-+#define BDC_DIV_HOLD_STATE		4
-+
-+#define BDC_MODE_1 1
-+#define BDC_MODE_2 2
-+#define BDC_MODE_3 3
-+#define BDC_MODE_4 4
-+#define BDC_MODE_NULL 0xff
-+
-+/*SW S0S1 antenna diversity*/
-+#define SWAW_STEP_INIT			0xff
-+#define SWAW_STEP_PEEK		0
-+#define SWAW_STEP_DETERMINE	1
-+
-+#define RSSI_CHECK_RESET_PERIOD	10
-+#define RSSI_CHECK_THRESHOLD		50
-+
-+/*@Hong Lin Smart antenna*/
-+#define HL_SMTANT_2WIRE_DATA_LEN 24
-+
-+#if (RTL8723D_SUPPORT == 1 || RTL8710C_SUPPORT == 1)
-+	#ifndef CONFIG_ANTDIV_PERIOD
-+		#define CONFIG_ANTDIV_PERIOD 1
-+	#endif
-+#endif
-+/* @1 ============================================================
-+ * 1  structure
-+ * 1 ============================================================
-+ */
-+
-+
-+struct sw_antenna_switch {
-+	u8		double_chk_flag;
-+	/*@If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than*/
-+	/*@check this antenna again*/
-+	u8		try_flag;
-+	s32		pre_rssi;
-+	u8		cur_antenna;
-+	u8		pre_ant;
-+	u8		rssi_trying;
-+	u8		reset_idx;
-+	u8		train_time;
-+	u8		train_time_flag;
-+	/*@base on RSSI difference between two antennas*/
-+	struct phydm_timer_list	sw_antdiv_timer;
-+	u32		pkt_cnt_sw_ant_div_by_ctrl_frame;
-+	boolean		is_sw_ant_div_by_ctrl_frame;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#if USE_WORKITEM
-+	RT_WORK_ITEM	phydm_sw_antenna_switch_workitem;
-+#endif
-+#endif
-+
-+	/* @AntDect (Before link Antenna Switch check) need to be moved*/
-+	u16		single_ant_counter;
-+	u16		dual_ant_counter;
-+	u16		aux_fail_detec_counter;
-+	u16		retry_counter;
-+	u8		swas_no_link_state;
-+	u32		swas_no_link_bk_reg948;
-+	boolean		ANTA_ON;	/*To indicate ant A is or not*/
-+	boolean		ANTB_ON;	/*@To indicate ant B is on or not*/
-+	boolean		pre_aux_fail_detec;
-+	boolean		rssi_ant_dect_result;
-+	u8		ant_5g;
-+	u8		ant_2g;
-+};
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+struct _BF_DIV_COEX_ {
-+	boolean w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM];
-+	boolean w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM];
-+	u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
-+	u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
-+
-+	u8 bd_ccoex_type_wbfer;
-+	u8 num_txbfee_client;
-+	u8 num_txbfer_client;
-+	u8 bdc_try_counter;
-+	u8 bdc_hold_counter;
-+	u8 bdc_mode;
-+	u8 bdc_active_mode;
-+	u8 BDC_state;
-+	u8 bdc_rx_idle_update_counter;
-+	u8 num_client;
-+	u8 pre_num_client;
-+	u8 num_bf_tar;
-+	u8 num_div_tar;
-+
-+	boolean is_all_div_sta_idle;
-+	boolean is_all_bf_sta_idle;
-+	boolean bdc_try_flag;
-+	boolean BF_pass;
-+	boolean DIV_pass;
-+};
-+#endif
-+#endif
-+
-+struct phydm_fat_struct {
-+	u8	bssid[6];
-+	u8	antsel_rx_keep_0;
-+	u8	antsel_rx_keep_1;
-+	u8	antsel_rx_keep_2;
-+	u8	antsel_rx_keep_3;
-+	u32	ant_sum_rssi[7];
-+	u32	ant_rssi_cnt[7];
-+	u32	ant_ave_rssi[7];
-+	u8	fat_state;
-+	u8	fat_state_cnt;
-+	u32	train_idx;
-+	u8	antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
-+	u8	antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
-+	u8	antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
-+	u16	main_ht_cnt[HT_IDX];
-+	u16	aux_ht_cnt[HT_IDX];
-+	u16	main_vht_cnt[VHT_IDX];
-+	u16	aux_vht_cnt[VHT_IDX];
-+	u16	main_sum[ODM_ASSOCIATE_ENTRY_NUM];
-+	u16	aux_sum[ODM_ASSOCIATE_ENTRY_NUM];
-+	u16	main_cnt[ODM_ASSOCIATE_ENTRY_NUM];
-+	u16	aux_cnt[ODM_ASSOCIATE_ENTRY_NUM];
-+	u16	main_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
-+	u16	aux_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
-+	u16	main_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
-+	u16	aux_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
-+	u8	rx_idle_ant;
-+	u8	rx_idle_ant2;
-+	u32	rvrt_val; /*all rvrt_val for pause API must set to u32*/
-+	u8	ant_div_on_off;
-+	u8	div_path_type;
-+	boolean	is_become_linked;
-+	boolean get_stats;
-+	u32	min_max_rssi;
-+	u8	idx_ant_div_counter_2g;
-+	u8	idx_ant_div_counter_5g;
-+	u8	ant_div_2g_5g;
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	/*@For 1SS RX phy rate*/
-+	u32	main_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
-+	u32	aux_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
-+	u32	main_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
-+	u32	aux_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
-+
-+	/*@For 2SS RX phy rate*/
-+	u32	main_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A1+B*/
-+	u32	aux_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A2+B*/
-+	u32	main_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
-+	u32	aux_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
-+
-+	boolean	evm_method_enable;
-+	u8	target_ant_evm;
-+	u8	target_ant_crc32;
-+	u8	target_ant_tp;
-+	u8	target_ant_enhance;
-+	u8	pre_target_ant_enhance;
-+	u16	main_mpdu_ok_cnt;
-+	u16	aux_mpdu_ok_cnt;
-+
-+	u32	crc32_ok_cnt;
-+	u32	crc32_fail_cnt;
-+	u32	main_crc32_ok_cnt;
-+	u32	aux_crc32_ok_cnt;
-+	u32	main_crc32_fail_cnt;
-+	u32	aux_crc32_fail_cnt;
-+
-+	u32	main_tp;
-+	u32	aux_tp;
-+	u32	main_tp_cnt;
-+	u32	aux_tp_cnt;
-+
-+	u8	pre_antdiv_rssi;
-+	u8	pre_antdiv_tp;
-+#endif
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
-+	u32    cck_ctrl_frame_cnt_main;
-+	u32    cck_ctrl_frame_cnt_aux;
-+	u32    ofdm_ctrl_frame_cnt_main;
-+	u32    ofdm_ctrl_frame_cnt_aux;
-+	u32	main_ctrl_sum;
-+	u32	aux_ctrl_sum;
-+	u32	main_ctrl_cnt;
-+	u32	aux_ctrl_cnt;
-+#endif
-+
-+	u8	b_fix_tx_ant;
-+	boolean	fix_ant_bfee;
-+	boolean	enable_ctrl_frame_antdiv;
-+	boolean	use_ctrl_frame_antdiv;
-+	boolean	*is_no_csi_feedback;
-+	boolean	force_antdiv_type;
-+	u8	antdiv_type_dbg;
-+	u8	hw_antsw_occur;
-+	u8	*p_force_tx_by_desc;
-+	u8	force_tx_by_desc;
-+	/*@A temp value, will hook to driver team's outer parameter later*/
-+	u8	*p_default_s0_s1;
-+	u8	default_s0_s1;
-+	u8 ant_idx_vec[3]; /* for SP3T only, added by Jiao Qi on June.6,2020*/
-+
-+
-+};
-+
-+/* @1 ============================================================
-+ * 1  enumeration
-+ * 1 ============================================================
-+ */
-+
-+enum fat_state /*@Fast antenna training*/
-+{
-+	FAT_BEFORE_LINK_STATE	= 0,
-+	FAT_PREPARE_STATE			= 1,
-+	FAT_TRAINING_STATE		= 2,
-+	FAT_DECISION_STATE		= 3
-+};
-+
-+enum ant_div_type {
-+	NO_ANTDIV			= 0xFF,
-+	CG_TRX_HW_ANTDIV			= 0x01,
-+	CGCS_RX_HW_ANTDIV		= 0x02,
-+	FIXED_HW_ANTDIV		= 0x03,
-+	CG_TRX_SMART_ANTDIV	= 0x04,
-+	CGCS_RX_SW_ANTDIV	= 0x05,
-+	S0S1_SW_ANTDIV	= 0x06, /*@8723B intrnal switch S0 S1*/
-+	S0S1_TRX_HW_ANTDIV	= 0x07, /*TRX S0S1 diversity for 8723D*/
-+	HL_SW_SMART_ANT_TYPE1	= 0x10,
-+	/*@Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys,*/
-+	/*@and each ant. is equipped with 4 antenna patterns*/
-+	HL_SW_SMART_ANT_TYPE2	= 0x11
-+	/*@Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
-+};
-+
-+/* @1 ============================================================
-+ * 1  function prototype
-+ * 1 ============================================================
-+ */
-+
-+void odm_stop_antenna_switch_dm(void *dm_void);
-+
-+void phydm_enable_antenna_diversity(void *dm_void);
-+
-+void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C,....*/
-+			);
-+
-+#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
-+
-+void odm_sw_ant_div_rest_after_link(void *dm_void);
-+
-+void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path);
-+
-+void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch);
-+
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+
-+void phydm_antdiv_reset_statistic(void *dm_void, u32 macid);
-+
-+void odm_update_rx_idle_ant(void *dm_void, u8 ant);
-+
-+void odm_update_rx_idle_ant_sp3t(void *dm_void, u8 ant);
-+
-+void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant);
-+
-+void phydm_set_antdiv_val(void *dm_void, u32 *val_buf,	u8 val_len);
-+
-+#if (RTL8723B_SUPPORT == 1)
-+void odm_update_rx_idle_ant_8723b(void *dm_void, u8 ant, u32 default_ant,
-+				  u32 optional_ant);
-+#endif
-+
-+#if (RTL8188F_SUPPORT == 1)
-+void phydm_update_rx_idle_antenna_8188F(void *dm_void,	u32 default_ant);
-+#endif
-+
-+#if (RTL8723D_SUPPORT == 1)
-+
-+void phydm_set_tx_ant_pwr_8723d(void *dm_void, u8 ant);
-+
-+void odm_update_rx_idle_ant_8723d(void *dm_void, u8 ant, u32 default_ant,
-+				  u32 optional_ant);
-+
-+#endif
-+
-+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void odm_sw_antdiv_callback(struct phydm_timer_list *timer);
-+
-+void odm_sw_antdiv_workitem_callback(void *context);
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+
-+void odm_sw_antdiv_workitem_callback(void *context);
-+
-+void odm_sw_antdiv_callback(void *function_context);
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+
-+void odm_sw_antdiv_callback(void *dm_void);
-+
-+#endif
-+
-+void odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step);
-+
-+void odm_antsel_statistics_ctrl(void *dm_void,	u8 antsel_tr_mux,
-+				u32 rx_pwdb_all);
-+
-+void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void,
-+						    void *phy_info_void,
-+						    void *pkt_info_void);
-+
-+#endif
-+
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+void phydm_evm_sw_antdiv_init(void *dm_void);
-+
-+void phydm_rx_rate_for_antdiv(void *dm_void, void *pkt_info_void);
-+
-+void phydm_antdiv_reset_rx_rate(void *dm_void);
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void phydm_evm_antdiv_callback(struct phydm_timer_list *timer);
-+
-+void phydm_evm_antdiv_workitem_callback(void *context);
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+void phydm_evm_antdiv_callback(void *dm_void);
-+
-+void phydm_evm_antdiv_workitem_callback(void *context);
-+
-+#else
-+void phydm_evm_antdiv_callback(void *dm_void);
-+#endif
-+
-+#endif
-+
-+void odm_hw_ant_div(void *dm_void);
-+
-+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
-+	(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+void odm_fast_ant_training(
-+	void *dm_void);
-+
-+void odm_fast_ant_training_callback(void *dm_void);
-+
-+void odm_fast_ant_training_work_item_callback(void *dm_void);
-+#endif
-+
-+void odm_ant_div_init(void *dm_void);
-+
-+void odm_ant_div(void *dm_void);
-+
-+void odm_antsel_statistics(void *dm_void, void *phy_info_void,
-+			   u8 antsel_tr_mux, u32 mac_id, u32 utility, u8 method,
-+			   u8 is_cck_rate);
-+
-+void odm_process_rssi_for_ant_div(void *dm_void, void *phy_info_void,
-+				  void *pkt_info_void);
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+void odm_set_tx_ant_by_tx_info(void *dm_void,	 u8 *desc, u8 mac_id);
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+
-+struct tx_desc;
-+/*@declared tx_desc here or compile error happened when enabled 8822B*/
-+
-+void odm_set_tx_ant_by_tx_info(struct rtl8192cd_priv *priv,
-+			       struct tx_desc *pdesc, unsigned short aid);
-+
-+#if 1 /*@def def CONFIG_WLAN_HAL*/
-+void odm_set_tx_ant_by_tx_info_hal(struct rtl8192cd_priv *priv,
-+				   void *pdesc_data, u16 aid);
-+#endif /*@#ifdef CONFIG_WLAN_HAL*/
-+#endif
-+
-+void odm_ant_div_config(void *dm_void);
-+
-+void odm_ant_div_timers(void *dm_void, u8 state);
-+
-+void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used,
-+			char *output, u32 *_out_len);
-+
-+void odm_ant_div_reset(void *dm_void);
-+
-+void odm_antenna_diversity_init(void *dm_void);
-+
-+void odm_antenna_diversity(void *dm_void);
-+#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/
-+#endif /*@#ifndef	__ODMANTDIV_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_api.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_api.c
-new file mode 100644
-index 000000000000..a5e736db1e67
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_api.c
-@@ -0,0 +1,3763 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ * ************************************************************
-+ */
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+enum channel_width phydm_rxsc_2_bw(void *dm_void, u8 rxsc)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	enum channel_width bw = 0;
-+
-+	/* @Check RX bandwidth */
-+	if (rxsc == 0)
-+		bw = *dm->band_width; /*@full bw*/
-+	else if (rxsc >= 1 && rxsc <= 8)
-+		bw = CHANNEL_WIDTH_20;
-+	else if (rxsc >= 9 && rxsc <= 12)
-+		bw = CHANNEL_WIDTH_40;
-+	else /*if (rxsc >= 13)*/
-+		bw = CHANNEL_WIDTH_80;
-+
-+	return bw;
-+}
-+
-+void phydm_reset_bb_hw_cnt(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	/*@ Reset all counter when 1 */
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		#if (RTL8723F_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8723F) {
-+			odm_set_bb_reg(dm, R_0x2a44, BIT(21), 0);
-+			odm_set_bb_reg(dm, R_0x2a44, BIT(21), 1);
-+		}
-+		#endif
-+		odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 1);
-+		odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0);
-+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		/*@ Reset all counter when 1 (including PMAC and PHY)*/
-+		/* Reset Page F counter*/
-+		odm_set_bb_reg(dm, R_0xb58, BIT(0), 1);
-+		odm_set_bb_reg(dm, R_0xb58, BIT(0), 0);
-+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x1);
-+		odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x0);
-+	}
-+}
-+
-+void phydm_dynamic_ant_weighting(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#ifdef DYN_ANT_WEIGHTING_SUPPORT
-+	#if (RTL8197F_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8197F))
-+		phydm_dynamic_ant_weighting_8197f(dm);
-+	#endif
-+
-+	#if (RTL8812A_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8812)) {
-+		phydm_dynamic_ant_weighting_8812a(dm);
-+	}
-+	#endif
-+
-+	#if (RTL8822B_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8822B))
-+		phydm_dynamic_ant_weighting_8822b(dm);
-+	#endif
-+#endif
-+}
-+
-+#ifdef DYN_ANT_WEIGHTING_SUPPORT
-+void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,
-+			  char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	if (!(dm->support_ic_type &
-+	    (ODM_RTL8192F | ODM_RTL8822B | ODM_RTL8812 | ODM_RTL8197F))) {
-+		return;
-+	}
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "echo dis_dym_ant_weighting {0/1}\n");
-+
-+	} else {
-+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+
-+		if (var1[0] == 1) {
-+			dm->is_disable_dym_ant_weighting = 1;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Disable dyn-ant-weighting\n");
-+		} else {
-+			dm->is_disable_dym_ant_weighting = 0;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Enable dyn-ant-weighting\n");
-+		}
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+#endif
-+
-+void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 rx_ant = 0, tx_ant = 0;
-+	u8 path_bitmap = 1;
-+
-+	path_bitmap = (u8)phydm_gen_bitmask(num_rf_path);
-+
-+	/*PHYDM_DBG(dm, ODM_COMP_INIT, "path_bitmap=0x%x\n", path_bitmap);*/
-+
-+	dm->tx_ant_status = path_bitmap;
-+	dm->rx_ant_status = path_bitmap;
-+
-+	if (num_rf_path == PDM_1SS)
-+		return;
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	if (dm->support_ic_type &
-+		   (ODM_RTL8192F | ODM_RTL8192E | ODM_RTL8197F)) {
-+		dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0xc04, 0x3);
-+		dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x90c, 0x3);
-+	} else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8814A)) {
-+		dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0x808, 0xf);
-+		dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x80c, 0xf);
-+	}
-+	#endif
-+	/* @trx_ant_status are already updated in trx mode API in JGR3 ICs */
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "[%s]ant_status{tx,rx}={0x%x, 0x%x}\n",
-+		  __func__, dm->tx_ant_status, dm->rx_ant_status);
-+}
-+
-+void phydm_config_ofdm_tx_path(void *dm_void, enum bb_path path)
-+{
-+#if (RTL8192E_SUPPORT || RTL8192F_SUPPORT || RTL8812A_SUPPORT)
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 ofdm_tx_path = 0x33;
-+
-+	if (dm->num_rf_path == PDM_1SS)
-+		return;
-+
-+	switch (dm->support_ic_type) {
-+	#if (RTL8192E_SUPPORT || RTL8192F_SUPPORT)
-+	case ODM_RTL8192E:
-+	case ODM_RTL8192F:
-+		if (path == BB_PATH_A)
-+			odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313);
-+		else if (path == BB_PATH_B)
-+			odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x82221323);
-+		else if (path == BB_PATH_AB)
-+			odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333);
-+
-+		break;
-+	#endif
-+
-+	#if (RTL8812A_SUPPORT)
-+	case ODM_RTL8812:
-+		if (path == BB_PATH_A)
-+			ofdm_tx_path = 0x11;
-+		else if (path == BB_PATH_B)
-+			ofdm_tx_path = 0x22;
-+		else if (path == BB_PATH_AB)
-+			ofdm_tx_path = 0x33;
-+
-+		odm_set_bb_reg(dm, R_0x80c, 0xff00, ofdm_tx_path);
-+
-+		break;
-+	#endif
-+
-+	default:
-+		break;
-+	}
-+#endif
-+}
-+
-+void phydm_config_ofdm_rx_path(void *dm_void, enum bb_path path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 val = 0;
-+
-+	if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8192F)) {
-+#if (RTL8192E_SUPPORT || RTL8192F_SUPPORT)
-+		if (path == BB_PATH_A)
-+			val = 1;
-+		else if (path == BB_PATH_B)
-+			val = 2;
-+		else if (path == BB_PATH_AB)
-+			val = 3;
-+
-+		odm_set_bb_reg(dm, R_0xc04, 0xff, ((val << 4) | val));
-+		odm_set_bb_reg(dm, R_0xd04, 0xf, val);
-+#endif
-+	}
-+#if (RTL8812A_SUPPORT || RTL8822B_SUPPORT)
-+	else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) {
-+		if (path == BB_PATH_A)
-+			val = 1;
-+		else if (path == BB_PATH_B)
-+			val = 2;
-+		else if (path == BB_PATH_AB)
-+			val = 3;
-+
-+		odm_set_bb_reg(dm, R_0x808, MASKBYTE0, ((val << 4) | val));
-+	}
-+#endif
-+}
-+
-+void phydm_config_cck_rx_antenna_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	if (dm->support_ic_type & ODM_IC_1SS)
-+		return;
-+
-+	/*@CCK 2R CCA parameters*/
-+	odm_set_bb_reg(dm, R_0xa00, BIT(15), 0x0); /*@Disable Ant diversity*/
-+	odm_set_bb_reg(dm, R_0xa70, BIT(7), 0); /*@Concurrent CCA at LSB & USB*/
-+	odm_set_bb_reg(dm, R_0xa74, BIT(8), 0); /*RX path diversity enable*/
-+	odm_set_bb_reg(dm, R_0xa14, BIT(7), 0); /*r_en_mrc_antsel*/
-+	odm_set_bb_reg(dm, R_0xa20, (BIT(5) | BIT(4)), 1); /*@MBC weighting*/
-+
-+	if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F))
-+		odm_set_bb_reg(dm, R_0xa08, BIT(28), 1); /*r_cck_2nd_sel_eco*/
-+	else if (dm->support_ic_type & ODM_RTL8814A)
-+		odm_set_bb_reg(dm, R_0xa84, BIT(28), 1); /*@2R CCA only*/
-+#endif
-+}
-+
-+void phydm_config_cck_rx_path(void *dm_void, enum bb_path path)
-+{
-+#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 path_div_select = 0;
-+	u8 cck_path[2] = {0};
-+	u8 en_2R_path = 0;
-+	u8 en_2R_mrc = 0;
-+	u8 i = 0, j = 0;
-+	u8 num_enable_path = 0;
-+	u8 cck_mrc_max_path = 2;
-+
-+	if (dm->support_ic_type & ODM_IC_1SS)
-+		return;
-+
-+	for (i = 0; i < 4; i++) {
-+		if (path & BIT(i)) { /*@ex: PHYDM_ABCD*/
-+			num_enable_path++;
-+			cck_path[j] = i;
-+			j++;
-+		}
-+		if (num_enable_path >= cck_mrc_max_path)
-+			break;
-+	}
-+
-+	if (num_enable_path > 1) {
-+		path_div_select = 1;
-+		en_2R_path = 1;
-+		en_2R_mrc = 1;
-+	} else {
-+		path_div_select = 0;
-+		en_2R_path = 0;
-+		en_2R_mrc = 0;
-+	}
-+	/*@CCK_1 input signal path*/
-+	odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), cck_path[0]);
-+	/*@CCK_2 input signal path*/
-+	odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), cck_path[1]);
-+	/*@enable Rx path diversity*/
-+	odm_set_bb_reg(dm, R_0xa74, BIT(8), path_div_select);
-+	/*@enable 2R Rx path*/
-+	odm_set_bb_reg(dm, R_0xa2c, BIT(18), en_2R_path);
-+	/*@enable 2R MRC*/
-+	odm_set_bb_reg(dm, R_0xa2c, BIT(22), en_2R_mrc);
-+	if (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) {
-+		if (path == BB_PATH_A) {
-+			odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
-+			odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0);
-+			odm_set_bb_reg(dm, R_0xa74, BIT(8), 0);
-+			odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0);
-+			odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0);
-+		} else if (path == BB_PATH_B) {/*@for DC cancellation*/
-+			odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1);
-+			odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
-+			odm_set_bb_reg(dm, R_0xa74, BIT(8), 0);
-+			odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0);
-+			odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0);
-+		} else if (path == BB_PATH_AB) {
-+			odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
-+			odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
-+			odm_set_bb_reg(dm, R_0xa74, BIT(8), 1);
-+			odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 1);
-+			odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 1);
-+		}
-+	} else if (dm->support_ic_type & ODM_RTL8822B) {
-+		if (path == BB_PATH_A) {
-+			odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0);
-+			odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0);
-+		} else {
-+			odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1);
-+			odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1);
-+		}
-+	}
-+
-+#endif
-+}
-+
-+void phydm_config_cck_tx_path(void *dm_void, enum bb_path path)
-+{
-+#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (path == BB_PATH_A)
-+		odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8);
-+	else if (path == BB_PATH_B)
-+		odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x4);
-+	else /*if (path == BB_PATH_AB)*/
-+		odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);
-+#endif
-+}
-+
-+void phydm_config_trx_path_v2(void *dm_void, char input[][16], u32 *_used,
-+			      char *output, u32 *_out_len)
-+{
-+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\
-+	RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT ||\
-+	RTL8812F_SUPPORT || RTL8198F_SUPPORT)
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 val[10] = {0};
-+	char help[] = "-h";
-+	u8 i = 0, input_idx = 0;
-+	enum bb_path tx_path, rx_path, tx_path_ctrl;
-+	boolean dbg_mode_en;
-+
-+	if (!(dm->support_ic_type &
-+	    (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8822C |
-+	     ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8198F)))
-+		return;
-+
-+	for (i = 0; i < 5; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
-+		input_idx++;
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	dbg_mode_en = (boolean)val[0];
-+	tx_path = (enum bb_path)val[1];
-+	rx_path = (enum bb_path)val[2];
-+	tx_path_ctrl = (enum bb_path)val[3];
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8822B |
-+					   ODM_RTL8192F)) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "{en} {tx_path} {rx_path} {ff:auto, else:1ss_tx_path}\n"
-+				 );
-+		} else {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "{en} {tx_path} {rx_path} {is_tx_2_path}\n");
-+		}
-+
-+	} else if (dbg_mode_en) {
-+		dm->is_disable_phy_api = false;
-+		phydm_api_trx_mode(dm, tx_path, rx_path, tx_path_ctrl);
-+		dm->is_disable_phy_api = true;
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "T/RX path = 0x%x/0x%x, tx_path_ctrl=%d\n",
-+			 tx_path, rx_path, tx_path_ctrl);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "T/RX path_en={0x%x, 0x%x}, tx_1ss=%d\n",
-+			 dm->tx_ant_status, dm->rx_ant_status,
-+			 dm->tx_1ss_status);
-+	} else {
-+		dm->is_disable_phy_api = false;
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Disable API debug mode\n");
-+	}
-+#endif
-+}
-+
-+void phydm_config_trx_path_v1(void *dm_void, char input[][16], u32 *_used,
-+			      char *output, u32 *_out_len)
-+{
-+#if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 val[10] = {0};
-+	char help[] = "-h";
-+	u8 i = 0, input_idx = 0;
-+
-+	if (!(dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)))
-+		return;
-+
-+	for (i = 0; i < 5; i++) {
-+		if (input[i + 1]) {
-+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
-+			input_idx++;
-+		}
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{0:CCK, 1:OFDM} {1:TX, 2:RX} {1:path_A, 2:path_B, 3:path_AB}\n");
-+
-+		*_used = used;
-+		*_out_len = out_len;
-+		return;
-+
-+	} else if (val[0] == 0) {
-+	/* @CCK */
-+		if (val[1] == 1) { /*TX*/
-+			if (val[2] == 1)
-+				phydm_config_cck_tx_path(dm, BB_PATH_A);
-+			else if (val[2] == 2)
-+				phydm_config_cck_tx_path(dm, BB_PATH_B);
-+			else if (val[2] == 3)
-+				phydm_config_cck_tx_path(dm, BB_PATH_AB);
-+		} else if (val[1] == 2) { /*RX*/
-+
-+			phydm_config_cck_rx_antenna_init(dm);
-+
-+			if (val[2] == 1)
-+				phydm_config_cck_rx_path(dm, BB_PATH_A);
-+			else if (val[2] == 2)
-+				phydm_config_cck_rx_path(dm, BB_PATH_B);
-+			else if (val[2] == 3)
-+				phydm_config_cck_rx_path(dm, BB_PATH_AB);
-+			}
-+		}
-+	/* OFDM */
-+	else if (val[0] == 1) {
-+		if (val[1] == 1) /*TX*/
-+			phydm_config_ofdm_tx_path(dm, val[2]);
-+		else if (val[1] == 2) /*RX*/
-+			phydm_config_ofdm_rx_path(dm, val[2]);
-+	}
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n",
-+		 (val[0] == 1) ? "OFDM" : "CCK",
-+		 (val[1] == 1) ? "TX" : "RX",
-+		 (val[2] & 0x1) ? "A" : "", (val[2] & 0x2) ? "B" : "",
-+		 (val[2] & 0x4) ? "C" : "",
-+		 (val[2] & 0x8) ? "D" : "");
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+#endif
-+}
-+
-+void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,
-+			   char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) {
-+		#if (RTL8192E_SUPPORT || RTL8812A_SUPPORT)
-+		phydm_config_trx_path_v1(dm, input, _used, output, _out_len);
-+		#endif
-+	} else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F |
-+		   ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F |
-+		   ODM_RTL8197G | ODM_RTL8814B | ODM_RTL8198F)) {
-+		#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT ||\
-+		     RTL8192F_SUPPORT || RTL8822C_SUPPORT ||\
-+		     RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
-+		     RTL8197G_SUPPORT || RTL8198F_SUPPORT)
-+		phydm_config_trx_path_v2(dm, input, _used, output, _out_len);
-+		#endif
-+	}
-+}
-+
-+void phydm_tx_2path(void *dm_void)
-+{
-+#if (defined(PHYDM_COMPILE_IC_2SS))
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	enum bb_path rx_path = (enum bb_path)dm->rx_ant_status;
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
-+
-+
-+	if (!(dm->support_ic_type & ODM_IC_2SS))
-+		return;
-+
-+	#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8197F_SUPPORT ||\
-+	     RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |
-+	    ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G))
-+		phydm_api_trx_mode(dm, BB_PATH_AB, rx_path, BB_PATH_AB);
-+	#endif
-+
-+	#if (RTL8812A_SUPPORT || RTL8192E_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {
-+		phydm_config_cck_tx_path(dm, BB_PATH_AB);
-+		phydm_config_ofdm_tx_path(dm, BB_PATH_AB);
-+	}
-+	#endif
-+#endif
-+}
-+
-+void phydm_stop_3_wire(void *dm_void, u8 set_type)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (set_type == PHYDM_SET) {
-+		/*@[Stop 3-wires]*/
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+			odm_set_bb_reg(dm, R_0x180c, 0x3, 0x0);
-+			odm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1);
-+
-+			#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+			if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
-+				odm_set_bb_reg(dm, R_0x410c, 0x3, 0x0);
-+				odm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1);
-+			}
-+			#endif
-+
-+			#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+			if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
-+				odm_set_bb_reg(dm, R_0x520c, 0x3, 0x0);
-+				odm_set_bb_reg(dm, R_0x520c, BIT(28), 0x1);
-+				odm_set_bb_reg(dm, R_0x530c, 0x3, 0x0);
-+				odm_set_bb_reg(dm, R_0x530c, BIT(28), 0x1);
-+			}
-+			#endif
-+		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+			odm_set_bb_reg(dm, R_0xc00, 0xf, 0x4);
-+			odm_set_bb_reg(dm, R_0xe00, 0xf, 0x4);
-+		} else {
-+			odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0xf);
-+		}
-+
-+	} else { /*@if (set_type == PHYDM_REVERT)*/
-+
-+		/*@[Start 3-wires]*/
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+			odm_set_bb_reg(dm, R_0x180c, 0x3, 0x3);
-+			odm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1);
-+
-+			#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+			if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
-+				odm_set_bb_reg(dm, R_0x410c, 0x3, 0x3);
-+				odm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1);
-+			}
-+			#endif
-+
-+			#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+			if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
-+				odm_set_bb_reg(dm, R_0x520c, 0x3, 0x3);
-+				odm_set_bb_reg(dm, R_0x520c, BIT(28), 0x1);
-+				odm_set_bb_reg(dm, R_0x530c, 0x3, 0x3);
-+				odm_set_bb_reg(dm, R_0x530c, BIT(28), 0x1);
-+			}
-+			#endif
-+		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+			odm_set_bb_reg(dm, R_0xc00, 0xf, 0x7);
-+			odm_set_bb_reg(dm, R_0xe00, 0xf, 0x7);
-+		} else {
-+			odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0x0);
-+		}
-+	}
-+}
-+
-+u8 phydm_stop_ic_trx(void *dm_void, u8 set_type)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_api_stuc *api = &dm->api_table;
-+	u8 i = 0;
-+	boolean trx_idle_success = false;
-+	u32 dbg_port_value = 0;
-+
-+	if (set_type == PHYDM_SET) {
-+	/*[Stop TRX]---------------------------------------------------------*/
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+			#if (RTL8723F_SUPPORT)
-+			/*Judy 2020-0515*/
-+			/*set debug port to 0x0*/
-+			if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0))
-+				return PHYDM_SET_FAIL;
-+			#endif
-+			for (i = 0; i < 100; i++) {
-+				dbg_port_value = odm_get_bb_reg(dm, R_0x2db4,
-+								MASKDWORD);
-+				/* BB idle */
-+				if ((dbg_port_value & 0x1FFEFF3F) == 0 &&
-+				    (dbg_port_value & 0xC0010000) ==
-+				    0xC0010000) {
-+					PHYDM_DBG(dm, ODM_COMP_API,
-+						  "Stop trx wait for (%d) times\n",
-+						  i);
-+
-+					trx_idle_success = true;
-+					break;
-+				}
-+			}
-+		} else {
-+			/*set debug port to 0x0*/
-+			if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0))
-+				return PHYDM_SET_FAIL;
-+			for (i = 0; i < 100; i++) {
-+				dbg_port_value = phydm_get_bb_dbg_port_val(dm);
-+				/* PHYTXON && CCA_all */
-+				if (dm->support_ic_type & (ODM_RTL8721D |
-+					ODM_RTL8710B | ODM_RTL8710C |
-+					ODM_RTL8188F | ODM_RTL8723D)) {
-+					if ((dbg_port_value &
-+					    (BIT(20) | BIT(15))) == 0) {
-+						PHYDM_DBG(dm, ODM_COMP_API,
-+							  "Stop trx wait for (%d) times\n",
-+							  i);
-+
-+						trx_idle_success = true;
-+						break;
-+					}
-+				} else {
-+					if ((dbg_port_value &
-+					    (BIT(17) | BIT(3))) == 0) {
-+						PHYDM_DBG(dm, ODM_COMP_API,
-+							  "Stop trx wait for (%d) times\n",
-+							  i);
-+
-+						trx_idle_success = true;
-+						break;
-+					}
-+				}
-+				ODM_delay_ms(1);
-+			}
-+			phydm_release_bb_dbg_port(dm);
-+		}
-+
-+		if (trx_idle_success) {
-+			api->tx_queue_bitmap = odm_read_1byte(dm, R_0x522);
-+
-+			/*pause all TX queue*/
-+			odm_set_mac_reg(dm, R_0x520, 0xff0000, 0xff);
-+
-+			if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+				/*disable OFDM RX CCA*/
-+				odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff);
-+			} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+				/*disable OFDM RX CCA*/
-+				odm_set_bb_reg(dm, R_0x838, BIT(1), 1);
-+			} else {
-+				api->rxiqc_reg1 = odm_read_4byte(dm, R_0xc14);
-+				api->rxiqc_reg2 = odm_read_4byte(dm, R_0xc1c);
-+				/* [ Set IQK Matrix = 0 ]
-+				 * equivalent to [ Turn off CCA]
-+				 */
-+				odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0);
-+				odm_set_bb_reg(dm, R_0xc1c, MASKDWORD, 0x0);
-+			}
-+			phydm_dis_cck_trx(dm, PHYDM_SET);
-+		} else {
-+			return PHYDM_SET_FAIL;
-+		}
-+
-+		return PHYDM_SET_SUCCESS;
-+
-+	} else { /*@if (set_type == PHYDM_REVERT)*/
-+		/*Release all TX queue*/
-+		odm_write_1byte(dm, R_0x522, api->tx_queue_bitmap);
-+
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+			/*@enable OFDM RX CCA*/
-+			odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0);
-+		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+			/*@enable OFDM RX CCA*/
-+			odm_set_bb_reg(dm, R_0x838, BIT(1), 0);
-+		} else {
-+			/* @[Set IQK Matrix = 0] equivalent to [ Turn off CCA]*/
-+			odm_write_4byte(dm, R_0xc14, api->rxiqc_reg1);
-+			odm_write_4byte(dm, R_0xc1c, api->rxiqc_reg2);
-+		}
-+		phydm_dis_cck_trx(dm, PHYDM_REVERT);
-+		return PHYDM_SET_SUCCESS;
-+	}
-+}
-+
-+void phydm_dis_cck_trx(void *dm_void, u8 set_type)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_api_stuc *api = &dm->api_table;
-+
-+	if (set_type == PHYDM_SET) {
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+			if(dm->support_ic_type & ODM_RTL8723F) {
-+				api->ccktx_path = 1;
-+				/* @disable CCK CCA */
-+				odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x1);
-+				/* @disable CCK Tx */
-+				odm_set_bb_reg(dm, R_0x2a00, BIT(1), 0x1);
-+			} else {
-+				api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0x1a04,
-+							     	0xf0000000);
-+				/* @CCK RxIQ weighting = [0,0] */
-+				odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
-+				/* @disable CCK Tx */
-+				odm_set_bb_reg(dm, R_0x1a04, 0xf0000000, 0x0);
-+			}
-+		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+			api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04,
-+							     0xf0000000);
-+			/* @disable CCK block */
-+			odm_set_bb_reg(dm, R_0x808, BIT(28), 0);
-+			/* @disable CCK Tx */
-+			odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x0);
-+		} else {
-+			api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04,
-+							     0xf0000000);
-+			/* @disable whole CCK block */
-+			odm_set_bb_reg(dm, R_0x800, BIT(24), 0);
-+			/* @disable CCK Tx */
-+			odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x0);
-+		}
-+	} else if (set_type == PHYDM_REVERT) {
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+			if(dm->support_ic_type & ODM_RTL8723F) {
-+				/* @enable CCK CCA */
-+				odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x0);
-+				/* @enable CCK Tx */
-+				odm_set_bb_reg(dm, R_0x2a00, BIT(1), 0x0);
-+			} else {
-+				/* @CCK RxIQ weighting = [1,1] */
-+				odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
-+				/* @enable CCK Tx */
-+				odm_set_bb_reg(dm, R_0x1a04, 0xf0000000,
-+				       	api->ccktx_path);
-+			}
-+		} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+			/* @enable CCK block */
-+			odm_set_bb_reg(dm, R_0x808, BIT(28), 1);
-+			/* @enable CCK Tx */
-+			odm_set_bb_reg(dm, R_0xa04, 0xf0000000,
-+				       api->ccktx_path);
-+		} else {
-+			/* @enable whole CCK block */
-+			odm_set_bb_reg(dm, R_0x800, BIT(24), 1);
-+			/* @enable CCK Tx */
-+			odm_set_bb_reg(dm, R_0xa04, 0xf0000000,
-+				       api->ccktx_path);
-+		}
-+	}
-+}
-+
-+void phydm_bw_fixed_enable(void *dm_void, u8 enable)
-+{
-+#ifdef CONFIG_BW_INDICATION
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean val = (enable == FUNC_ENABLE) ? 1 : 0;
-+
-+	if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8195B))
-+		odm_set_bb_reg(dm, R_0x840, BIT(4), val);
-+	else if (dm->support_ic_type & ODM_RTL8822C)
-+		odm_set_bb_reg(dm, R_0x878, BIT(28), val);
-+#endif
-+}
-+
-+void phydm_bw_fixed_setting(void *dm_void)
-+{
-+#ifdef CONFIG_BW_INDICATION
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_api_stuc *api = &dm->api_table;
-+	u8 bw = *dm->band_width;
-+	u32 reg = 0, reg_mask = 0, reg_value = 0;
-+
-+	if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT))
-+		return;
-+
-+	if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B |
-+	    ODM_RTL8195B)) {
-+		reg = R_0x840;
-+		reg_mask = 0xf;
-+		reg_value = api->pri_ch_idx;
-+	} else if (dm->support_ic_type & ODM_RTL8822C) {
-+		reg = R_0x878;
-+		reg_mask = 0xc0000000;
-+		reg_value = 0x0;
-+	}
-+
-+	switch (bw) {
-+	case CHANNEL_WIDTH_80:
-+		odm_set_bb_reg(dm, reg, reg_mask, reg_value);
-+		break;
-+	case CHANNEL_WIDTH_40:
-+		odm_set_bb_reg(dm, reg, reg_mask, reg_value);
-+		break;
-+	default:
-+		odm_set_bb_reg(dm, reg, reg_mask, 0x0);
-+	}
-+
-+	phydm_bw_fixed_enable(dm, FUNC_ENABLE);
-+#endif
-+}
-+
-+void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch)
-+{
-+#if (RTL8821A_SUPPORT || RTL8881A_SUPPORT)
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)))
-+		return;
-+
-+	/*Output Pin Settings*/
-+
-+	/*select DPDT_P and DPDT_N as output pin*/
-+	odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
-+
-+	/*@by WLAN control*/
-+	odm_set_mac_reg(dm, R_0x4c, BIT(24), 1);
-+
-+	/*@DPDT_N = 1b'0*/ /*@DPDT_P = 1b'0*/
-+	odm_set_bb_reg(dm, R_0xcb4, 0xFF, 77);
-+
-+	if (ext_ant_switch == 1) { /*@2b'01*/
-+		odm_set_bb_reg(dm, R_0xcb4, (BIT(29) | BIT(28)), 1);
-+		PHYDM_DBG(dm, ODM_COMP_API, "8821A ant swh=2b'01\n");
-+	} else if (ext_ant_switch == 2) { /*@2b'10*/
-+		odm_set_bb_reg(dm, R_0xcb4, BIT(29) | BIT(28), 2);
-+		PHYDM_DBG(dm, ODM_COMP_API, "*8821A ant swh=2b'10\n");
-+	}
-+#endif
-+}
-+
-+void phydm_csi_mask_enable(void *dm_void, u32 enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean en = false;
-+
-+	en = (enable == FUNC_ENABLE) ? true : false;
-+
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		odm_set_bb_reg(dm, R_0xd2c, BIT(28), en);
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "Enable CSI Mask:  Reg 0xD2C[28] = ((0x%x))\n", en);
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		odm_set_bb_reg(dm, R_0xc0c, BIT(3), en);
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "Enable CSI Mask:  Reg 0xc0c[3] = ((0x%x))\n", en);
-+	#endif
-+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		odm_set_bb_reg(dm, R_0x874, BIT(0), en);
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "Enable CSI Mask:  Reg 0x874[0] = ((0x%x))\n", en);
-+	}
-+}
-+
-+void phydm_clean_all_csi_mask(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		odm_set_bb_reg(dm, R_0xd40, MASKDWORD, 0);
-+		odm_set_bb_reg(dm, R_0xd44, MASKDWORD, 0);
-+		odm_set_bb_reg(dm, R_0xd48, MASKDWORD, 0);
-+		odm_set_bb_reg(dm, R_0xd4c, MASKDWORD, 0);
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		u8 i = 0, idx_lmt = 0;
-+
-+		if (dm->support_ic_type &
-+		   (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G))
-+			idx_lmt = 127;
-+		else /*@for IC supporting 80 + 80*/
-+			idx_lmt = 255;
-+
-+		odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);
-+		odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);
-+		for (i = 0; i < idx_lmt; i++) {
-+			odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, i);
-+			odm_set_bb_reg(dm, R_0x1d94, MASKBYTE0, 0x0);
-+		}
-+		odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);
-+	#endif
-+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		odm_set_bb_reg(dm, R_0x880, MASKDWORD, 0);
-+		odm_set_bb_reg(dm, R_0x884, MASKDWORD, 0);
-+		odm_set_bb_reg(dm, R_0x888, MASKDWORD, 0);
-+		odm_set_bb_reg(dm, R_0x88c, MASKDWORD, 0);
-+		odm_set_bb_reg(dm, R_0x890, MASKDWORD, 0);
-+		odm_set_bb_reg(dm, R_0x894, MASKDWORD, 0);
-+		odm_set_bb_reg(dm, R_0x898, MASKDWORD, 0);
-+		odm_set_bb_reg(dm, R_0x89c, MASKDWORD, 0);
-+	}
-+}
-+
-+void phydm_set_csi_mask(void *dm_void, u32 tone_idx_tmp, u8 tone_direction)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 byte_offset = 0, bit_offset = 0;
-+	u32 target_reg = 0;
-+	u8 reg_tmp_value = 0;
-+	u32 tone_num = 64;
-+	u32 tone_num_shift = 0;
-+	u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0;
-+
-+	/* @calculate real tone idx*/
-+	if ((tone_idx_tmp % 10) >= 5)
-+		tone_idx_tmp += 10;
-+
-+	tone_idx_tmp = (tone_idx_tmp / 10);
-+
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		tone_num = 64;
-+		csi_mask_reg_p = 0xD40;
-+		csi_mask_reg_n = 0xD48;
-+
-+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		tone_num = 128;
-+		csi_mask_reg_p = 0x880;
-+		csi_mask_reg_n = 0x890;
-+	}
-+
-+	if (tone_direction == FREQ_POSITIVE) {
-+		if (tone_idx_tmp >= (tone_num - 1))
-+			tone_idx_tmp = (tone_num - 1);
-+
-+		byte_offset = (u8)(tone_idx_tmp >> 3);
-+		bit_offset = (u8)(tone_idx_tmp & 0x7);
-+		target_reg = csi_mask_reg_p + byte_offset;
-+
-+	} else {
-+		tone_num_shift = tone_num;
-+
-+		if (tone_idx_tmp >= tone_num)
-+			tone_idx_tmp = tone_num;
-+
-+		tone_idx_tmp = tone_num - tone_idx_tmp;
-+
-+		byte_offset = (u8)(tone_idx_tmp >> 3);
-+		bit_offset = (u8)(tone_idx_tmp & 0x7);
-+		target_reg = csi_mask_reg_n + byte_offset;
-+	}
-+
-+	reg_tmp_value = odm_read_1byte(dm, target_reg);
-+	PHYDM_DBG(dm, ODM_COMP_API,
-+		  "Pre Mask tone idx[%d]:  Reg0x%x = ((0x%x))\n",
-+		  (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value);
-+	reg_tmp_value |= BIT(bit_offset);
-+	odm_write_1byte(dm, target_reg, reg_tmp_value);
-+	PHYDM_DBG(dm, ODM_COMP_API,
-+		  "New Mask tone idx[%d]:  Reg0x%x = ((0x%x))\n",
-+		  (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value);
-+}
-+
-+void phydm_set_nbi_reg(void *dm_void, u32 tone_idx_tmp, u32 bw)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	/*tone_idx X 10*/
-+	u32 nbi_128[NBI_128TONE] = {25, 55, 85, 115, 135,
-+				    155, 185, 205, 225, 245,
-+				    265, 285, 305, 335, 355,
-+				    375, 395, 415, 435, 455,
-+				    485, 505, 525, 555, 585, 615, 635};
-+	/*tone_idx X 10*/
-+	u32 nbi_256[NBI_256TONE] = {25, 55, 85, 115, 135,
-+				    155, 175, 195, 225, 245,
-+				    265, 285, 305, 325, 345,
-+				    365, 385, 405, 425, 445,
-+				    465, 485, 505, 525, 545,
-+				    565, 585, 605, 625, 645,
-+				    665, 695, 715, 735, 755,
-+				    775, 795, 815, 835, 855,
-+				    875, 895, 915, 935, 955,
-+				    975, 995, 1015, 1035, 1055,
-+				    1085, 1105, 1125, 1145, 1175,
-+				    1195, 1225, 1255, 1275};
-+	u32 reg_idx = 0;
-+	u32 i;
-+	u8 nbi_table_idx = FFT_128_TYPE;
-+
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		nbi_table_idx = FFT_128_TYPE;
-+	} else if (dm->support_ic_type & ODM_IC_11AC_1_SERIES) {
-+		nbi_table_idx = FFT_256_TYPE;
-+	} else if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) {
-+		if (bw == 80)
-+			nbi_table_idx = FFT_256_TYPE;
-+		else /*@20M, 40M*/
-+			nbi_table_idx = FFT_128_TYPE;
-+	}
-+
-+	if (nbi_table_idx == FFT_128_TYPE) {
-+		for (i = 0; i < NBI_128TONE; i++) {
-+			if (tone_idx_tmp < nbi_128[i]) {
-+				reg_idx = i + 1;
-+				break;
-+			}
-+		}
-+
-+	} else if (nbi_table_idx == FFT_256_TYPE) {
-+		for (i = 0; i < NBI_256TONE; i++) {
-+			if (tone_idx_tmp < nbi_256[i]) {
-+				reg_idx = i + 1;
-+				break;
-+			}
-+		}
-+	}
-+
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		odm_set_bb_reg(dm, R_0xc40, 0x1f000000, reg_idx);
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "Set tone idx:  Reg0xC40[28:24] = ((0x%x))\n",
-+			  reg_idx);
-+	} else {
-+		odm_set_bb_reg(dm, R_0x87c, 0xfc000, reg_idx);
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "Set tone idx: Reg0x87C[19:14] = ((0x%x))\n",
-+			  reg_idx);
-+	}
-+}
-+
-+void phydm_nbi_enable(void *dm_void, u32 enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 val = 0;
-+
-+	val = (enable == FUNC_ENABLE) ? 1 : 0;
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val);
-+
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		if (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) {
-+			val = (enable == FUNC_ENABLE) ? 0xf : 0;
-+			odm_set_bb_reg(dm, R_0xc50, 0xf000000, val);
-+		} else {
-+			odm_set_bb_reg(dm, R_0xc40, BIT(9), val);
-+		}
-+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C |
-+		    ODM_RTL8195B)) {
-+			odm_set_bb_reg(dm, R_0x87c, BIT(13), val);
-+			odm_set_bb_reg(dm, R_0xc20, BIT(28), val);
-+			if (dm->rf_type > RF_1T1R)
-+				odm_set_bb_reg(dm, R_0xe20, BIT(28), val);
-+		} else {
-+			odm_set_bb_reg(dm, R_0x87c, BIT(13), val);
-+		}
-+	}
-+}
-+
-+u8 phydm_find_fc(void *dm_void, u32 channel, u32 bw, u32 second_ch, u32 *fc_in)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 fc = *fc_in;
-+	u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100,
-+						  108, 116, 124, 132, 140,
-+						  149, 157, 165, 173};
-+	u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132,
-+						  149, 165};
-+	u32 *start_ch = &start_ch_per_40m[0];
-+	u32 num_start_channel = NUM_START_CH_40M;
-+	u32 channel_offset = 0;
-+	u32 i;
-+
-+	/*@2.4G*/
-+	if (channel <= 14 && channel > 0) {
-+		if (bw == 80)
-+			return PHYDM_SET_FAIL;
-+
-+		fc = 2412 + (channel - 1) * 5;
-+
-+		if (bw == 40 && second_ch == PHYDM_ABOVE) {
-+			if (channel >= 10) {
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
-+					  channel, second_ch);
-+				return PHYDM_SET_FAIL;
-+			}
-+			fc += 10;
-+		} else if (bw == 40 && (second_ch == PHYDM_BELOW)) {
-+			if (channel <= 2) {
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
-+					  channel, second_ch);
-+				return PHYDM_SET_FAIL;
-+			}
-+			fc -= 10;
-+		}
-+	}
-+	/*@5G*/
-+	else if (channel >= 36 && channel <= 177) {
-+		if (bw != 20) {
-+			if (bw == 40) {
-+				num_start_channel = NUM_START_CH_40M;
-+				start_ch = &start_ch_per_40m[0];
-+				channel_offset = CH_OFFSET_40M;
-+			} else if (bw == 80) {
-+				num_start_channel = NUM_START_CH_80M;
-+				start_ch = &start_ch_per_80m[0];
-+				channel_offset = CH_OFFSET_80M;
-+			}
-+
-+			for (i = 0; i < (num_start_channel - 1); i++) {
-+				if (channel < start_ch[i + 1]) {
-+					channel = start_ch[i] + channel_offset;
-+					break;
-+				}
-+			}
-+			PHYDM_DBG(dm, ODM_COMP_API, "Mod_CH = ((%d))\n",
-+				  channel);
-+		}
-+
-+		fc = 5180 + (channel - 36) * 5;
-+
-+	} else {
-+		PHYDM_DBG(dm, ODM_COMP_API, "CH = ((%d)) Error setting\n",
-+			  channel);
-+		return PHYDM_SET_FAIL;
-+	}
-+
-+	*fc_in = fc;
-+
-+	return PHYDM_SET_SUCCESS;
-+}
-+
-+u8 phydm_find_intf_distance(void *dm_void, u32 bw, u32 fc, u32 f_interference,
-+			    u32 *tone_idx_tmp_in)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 bw_up = 0, bw_low = 0;
-+	u32 int_distance = 0;
-+	u32 tone_idx_tmp = 0;
-+	u8 set_result = PHYDM_SET_NO_NEED;
-+
-+	bw_up = fc + bw / 2;
-+	bw_low = fc - bw / 2;
-+
-+	PHYDM_DBG(dm, ODM_COMP_API,
-+		  "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low,
-+		  fc, bw_up, f_interference);
-+
-+	if (f_interference >= bw_low && f_interference <= bw_up) {
-+		int_distance = DIFF_2(fc, f_interference);
-+		/*@10*(int_distance /0.3125)*/
-+		tone_idx_tmp = (int_distance << 5);
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n",
-+			  int_distance, tone_idx_tmp / 10,
-+			  tone_idx_tmp % 10);
-+		*tone_idx_tmp_in = tone_idx_tmp;
-+		set_result = PHYDM_SET_SUCCESS;
-+	}
-+
-+	return set_result;
-+}
-+
-+u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw,
-+			  u32 f_intf, u32 sec_ch)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 fc = 2412;
-+	u8 direction = FREQ_POSITIVE;
-+	u32 tone_idx = 0;
-+	u8 set_result = PHYDM_SET_SUCCESS;
-+	u8 rpt = 0;
-+
-+	if (enable == FUNC_DISABLE) {
-+		set_result = PHYDM_SET_SUCCESS;
-+		phydm_clean_all_csi_mask(dm);
-+
-+	} else {
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
-+			  ch, bw, f_intf,
-+			  (((bw == 20) || (ch > 14)) ? "Don't care" :
-+			  (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
-+
-+		/*@calculate fc*/
-+		if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
-+			set_result = PHYDM_SET_FAIL;
-+		} else {
-+			/*@calculate interference distance*/
-+			rpt = phydm_find_intf_distance(dm, bw, fc, f_intf,
-+						       &tone_idx);
-+			if (rpt == PHYDM_SET_SUCCESS) {
-+				if (f_intf >= fc)
-+					direction = FREQ_POSITIVE;
-+				else
-+					direction = FREQ_NEGATIVE;
-+
-+				phydm_set_csi_mask(dm, tone_idx, direction);
-+				set_result = PHYDM_SET_SUCCESS;
-+			} else {
-+				set_result = PHYDM_SET_NO_NEED;
-+			}
-+		}
-+	}
-+
-+	if (set_result == PHYDM_SET_SUCCESS)
-+		phydm_csi_mask_enable(dm, enable);
-+	else
-+		phydm_csi_mask_enable(dm, FUNC_DISABLE);
-+
-+	return set_result;
-+}
-+
-+boolean phydm_spur_case_mapping(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 channel = *dm->channel, bw = *dm->band_width;
-+	boolean mapping_result = false;
-+#if (RTL8814B_SUPPORT == 1)
-+	if (channel == 153 && bw == CHANNEL_WIDTH_20) {
-+		odm_set_bb_reg(dm, R_0x804, BIT(31), 0);
-+		odm_set_bb_reg(dm, R_0xc00, BIT(25) | BIT(24), 0);
-+		mapping_result =  true;
-+	} else if (channel == 151 && bw == CHANNEL_WIDTH_40) {
-+		odm_set_bb_reg(dm, R_0x804, BIT(31), 0);
-+		odm_set_bb_reg(dm, R_0xc00, BIT(25) | BIT(24), 0);
-+		mapping_result =  true;
-+	} else if (channel == 155 && bw == CHANNEL_WIDTH_80) {
-+		odm_set_bb_reg(dm, R_0x804, BIT(31), 0);
-+		odm_set_bb_reg(dm, R_0xc00, BIT(25) | BIT(24), 0);
-+		mapping_result =  true;
-+	} else {
-+		odm_set_bb_reg(dm, R_0x804, BIT(31), 1);
-+		odm_set_bb_reg(dm, R_0xc00, BIT(25) | BIT(24), 1);
-+	}
-+#endif
-+	return mapping_result;
-+}
-+
-+enum odm_rf_band phydm_ch_to_rf_band(void *dm_void, u8 central_ch)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	enum odm_rf_band rf_band = ODM_RF_BAND_5G_LOW;
-+
-+	if (central_ch <= 14)
-+		rf_band = ODM_RF_BAND_2G;
-+	else if (central_ch >= 36 && central_ch <= 64)
-+		rf_band = ODM_RF_BAND_5G_LOW;
-+	else if ((central_ch >= 100) && (central_ch <= 144))
-+		rf_band = ODM_RF_BAND_5G_MID;
-+	else if (central_ch >= 149)
-+		rf_band = ODM_RF_BAND_5G_HIGH;
-+	else
-+		PHYDM_DBG(dm, ODM_COMP_API, "mapping channel to band fail\n");
-+
-+	return rf_band;
-+}
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+u32 phydm_rf_psd_jgr3(void *dm_void, u8 path, u32 tone_idx)
-+{
-+#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 reg_1b04 = 0, reg_1b08 = 0, reg_1b0c_11_10 = 0;
-+	u32 reg_1b14 = 0, reg_1b18 = 0, reg_1b1c = 0;
-+	u32 reg_1b28 = 0;
-+	u32 reg_1bcc_5_0 = 0;
-+	u32 reg_1b2c_27_16 = 0, reg_1b34 = 0, reg_1bd4 = 0;
-+	u32 reg_180c = 0, reg_410c = 0, reg_520c = 0, reg_530c = 0;
-+	u32 igi = 0;
-+	u32 i = 0;
-+	u32 psd_val = 0, psd_val_msb = 0, psd_val_lsb = 0, psd_max = 0;
-+	u32 psd_status_temp = 0;
-+	u16 poll_cnt = 0;
-+
-+	/*read and record the ori. value*/
-+	reg_1b04 = odm_get_bb_reg(dm, R_0x1b04, MASKDWORD);
-+	reg_1b08 = odm_get_bb_reg(dm, R_0x1b08, MASKDWORD);
-+	reg_1b0c_11_10 = odm_get_bb_reg(dm, R_0x1b0c, 0xc00);
-+	reg_1b14 = odm_get_bb_reg(dm, R_0x1b14, MASKDWORD);
-+	reg_1b18 = odm_get_bb_reg(dm, R_0x1b18, MASKDWORD);
-+	reg_1b1c = odm_get_bb_reg(dm, R_0x1b1c, MASKDWORD);
-+	reg_1b28 = odm_get_bb_reg(dm, R_0x1b28, MASKDWORD);
-+	reg_1bcc_5_0 = odm_get_bb_reg(dm, R_0x1bcc, 0x3f);
-+	reg_1b2c_27_16 = odm_get_bb_reg(dm, R_0x1b2c, 0xfff0000);
-+	reg_1b34 = odm_get_bb_reg(dm, R_0x1b34, MASKDWORD);
-+	reg_1bd4 = odm_get_bb_reg(dm, R_0x1bd4, MASKDWORD);
-+	igi = odm_get_bb_reg(dm, R_0x1d70, MASKDWORD);
-+	reg_180c = odm_get_bb_reg(dm, R_0x180c, 0x3);
-+	reg_410c = odm_get_bb_reg(dm, R_0x410c, 0x3);
-+	reg_520c = odm_get_bb_reg(dm, R_0x520c, 0x3);
-+	reg_530c = odm_get_bb_reg(dm, R_0x530c, 0x3);
-+
-+	/*rf psd reg setting*/
-+	odm_set_bb_reg(dm, R_0x1b00, 0x6, path); /*path is RF_path*/
-+	odm_set_bb_reg(dm, R_0x1b04, MASKDWORD, 0x0);
-+	odm_set_bb_reg(dm, R_0x1b08, MASKDWORD, 0x80);
-+	odm_set_bb_reg(dm, R_0x1b0c, 0xc00, 0x3);
-+	odm_set_bb_reg(dm, R_0x1b14, MASKDWORD, 0x0);
-+	odm_set_bb_reg(dm, R_0x1b18, MASKDWORD, 0x1);
-+/*#if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/
-+	odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, 0x82103D21);
-+/*#else*/
-+	/*odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, 0x821A3D21);*/
-+/*#endif*/
-+	odm_set_bb_reg(dm, R_0x1b28, MASKDWORD, 0x0);
-+	odm_set_bb_reg(dm, R_0x1bcc, 0x3f, 0x3f);
-+	odm_set_bb_reg(dm, R_0x8a0, 0xf, 0x0); /* AGC off */
-+	odm_set_bb_reg(dm, R_0x1d70, MASKDWORD, 0x20202020);
-+
-+	for (i = tone_idx - 1; i <= tone_idx + 1; i++) {
-+		/*set psd tone_idx for detection*/
-+		odm_set_bb_reg(dm, R_0x1b2c, 0xfff0000, i);
-+		/*one shot for RXIQK psd*/
-+		odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x1);
-+		odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x0);
-+
-+		if (dm->support_ic_type & ODM_RTL8814B)
-+			for (poll_cnt = 0; poll_cnt < 20; poll_cnt++) {
-+				odm_set_bb_reg(dm, R_0x1bd4, 0x3f0000, 0x2b);
-+				psd_status_temp = odm_get_bb_reg(dm, R_0x1bfc,
-+								 BIT(1));
-+				if (!psd_status_temp)
-+					ODM_delay_us(10);
-+				else
-+					break;
-+			}
-+		else
-+			ODM_delay_us(250);
-+
-+		/*read RxIQK power*/
-+		odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001);
-+		if (dm->support_ic_type & ODM_RTL8814B)
-+			psd_val_msb = odm_get_bb_reg(dm, R_0x1bfc, 0x7ff0000);
-+		else if (dm->support_ic_type & ODM_RTL8198F)
-+			psd_val_msb = odm_get_bb_reg(dm, R_0x1bfc, 0x1f0000);
-+
-+		odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001);
-+		psd_val_lsb = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD);
-+		if (dm->support_ic_type & ODM_RTL8814B)
-+			psd_val = (psd_val_msb << 21) + (psd_val_lsb >> 11);
-+		else if (dm->support_ic_type & ODM_RTL8198F)
-+			psd_val = (psd_val_msb << 27) + (psd_val_lsb >> 5);
-+
-+		if (psd_val > psd_max)
-+			psd_max = psd_val;
-+	}
-+
-+	/*refill the ori. value*/
-+	odm_set_bb_reg(dm, R_0x1b00, 0x6, path);
-+	odm_set_bb_reg(dm, R_0x1b04, MASKDWORD, reg_1b04);
-+	odm_set_bb_reg(dm, R_0x1b08, MASKDWORD, reg_1b08);
-+	odm_set_bb_reg(dm, R_0x1b0c, 0xc00, reg_1b0c_11_10);
-+	odm_set_bb_reg(dm, R_0x1b14, MASKDWORD, reg_1b14);
-+	odm_set_bb_reg(dm, R_0x1b18, MASKDWORD, reg_1b18);
-+	odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, reg_1b1c);
-+	odm_set_bb_reg(dm, R_0x1b28, MASKDWORD, reg_1b28);
-+	odm_set_bb_reg(dm, R_0x1bcc, 0x3f, reg_1bcc_5_0);
-+	odm_set_bb_reg(dm, R_0x1b2c, 0xfff0000, reg_1b2c_27_16);
-+	odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, reg_1b34);
-+	odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, reg_1bd4);
-+	odm_set_bb_reg(dm, R_0x8a0, 0xf, 0xf); /* AGC on */
-+	odm_set_bb_reg(dm, R_0x1d70, MASKDWORD, igi);
-+	PHYDM_DBG(dm, ODM_COMP_API, "psd_max %d\n", psd_max);
-+
-+	return psd_max;
-+#else
-+	return 0;
-+#endif
-+}
-+
-+u8 phydm_find_intf_distance_jgr3(void *dm_void, u32 bw, u32 fc,
-+				 u32 f_interference, u32 *tone_idx_tmp_in)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 bw_up = 0, bw_low = 0;
-+	u32 int_distance = 0;
-+	u32 tone_idx_tmp = 0;
-+	u8 set_result = PHYDM_SET_NO_NEED;
-+	u8 channel = *dm->channel;
-+
-+	bw_up = 1000 * (fc + bw / 2);
-+	bw_low = 1000 * (fc - bw / 2);
-+	fc = 1000 * fc;
-+
-+	PHYDM_DBG(dm, ODM_COMP_API,
-+		  "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low,
-+		  fc, bw_up, f_interference);
-+
-+	if (f_interference >= bw_low && f_interference <= bw_up) {
-+		int_distance = DIFF_2(fc, f_interference);
-+		/*@10*(int_distance /0.3125)*/
-+		if (channel < 15 &&
-+		    (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F)))
-+			tone_idx_tmp = int_distance / 312;
-+		else
-+			tone_idx_tmp = ((int_distance + 156) / 312);
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "int_distance = ((%d)) , tone_idx_tmp = ((%d))\n",
-+			  int_distance, tone_idx_tmp);
-+		*tone_idx_tmp_in = tone_idx_tmp;
-+		set_result = PHYDM_SET_SUCCESS;
-+	}
-+
-+	return set_result;
-+}
-+
-+u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,
-+			       u32 f_intf, u32 sec_ch, u8 wgt)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 fc = 2412;
-+	u8 direction = FREQ_POSITIVE;
-+	u32 tone_idx = 0;
-+	u8 set_result = PHYDM_SET_SUCCESS;
-+	u8 rpt = 0;
-+
-+	if (enable == FUNC_DISABLE) {
-+		phydm_csi_mask_enable(dm, FUNC_ENABLE);
-+		phydm_clean_all_csi_mask(dm);
-+		phydm_csi_mask_enable(dm, FUNC_DISABLE);
-+		set_result = PHYDM_SET_SUCCESS;
-+	} else {
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "[Set CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s)), wgt = ((%d))\n",
-+			  ch, bw, f_intf,
-+			  (((bw == 20) || (ch > 14)) ? "Don't care" :
-+			  (sec_ch == PHYDM_ABOVE) ? "H" : "L"), wgt);
-+
-+		/*@calculate fc*/
-+		if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
-+			set_result = PHYDM_SET_FAIL;
-+		} else {
-+			/*@calculate interference distance*/
-+			rpt = phydm_find_intf_distance_jgr3(dm, bw, fc, f_intf,
-+							    &tone_idx);
-+			if (rpt == PHYDM_SET_SUCCESS) {
-+				if (f_intf >= 1000 * fc)
-+					direction = FREQ_POSITIVE;
-+				else
-+					direction = FREQ_NEGATIVE;
-+
-+				phydm_csi_mask_enable(dm, FUNC_ENABLE);
-+				phydm_set_csi_mask_jgr3(dm, tone_idx, direction,
-+							wgt);
-+				set_result = PHYDM_SET_SUCCESS;
-+			} else {
-+				set_result = PHYDM_SET_NO_NEED;
-+			}
-+		}
-+		if (!(set_result == PHYDM_SET_SUCCESS))
-+			phydm_csi_mask_enable(dm, FUNC_DISABLE);
-+	}
-+
-+	return set_result;
-+}
-+
-+void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
-+			     u8 wgt)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 multi_tone_idx_tmp = 0;
-+	u32 reg_tmp = 0;
-+	u32 tone_num = 64;
-+	u32 table_addr = 0;
-+	u32 addr = 0;
-+	u8 rf_bw = 0;
-+	u8 value = 0;
-+	u8 channel = *dm->channel;
-+
-+	rf_bw = odm_read_1byte(dm, R_0x9b0);
-+	if (((rf_bw & 0xc) >> 2) == 0x2)
-+		tone_num = 128; /* @RF80 : tone(-1) at tone_idx=255 */
-+	else
-+		tone_num = 64; /* @RF20/40 : tone(-1) at tone_idx=127 */
-+
-+	if (tone_direction == FREQ_POSITIVE) {
-+		if (tone_idx_tmp >= (tone_num - 1))
-+			tone_idx_tmp = (tone_num - 1);
-+	} else {
-+		if (tone_idx_tmp >= tone_num)
-+			tone_idx_tmp = tone_num;
-+
-+		tone_idx_tmp = (tone_num << 1) - tone_idx_tmp;
-+	}
-+	table_addr = tone_idx_tmp >> 1;
-+
-+	reg_tmp = odm_read_4byte(dm, R_0x1d94);
-+	PHYDM_DBG(dm, ODM_COMP_API,
-+		  "Pre Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
-+		  tone_idx_tmp, reg_tmp);
-+	odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);
-+	odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);
-+
-+	if (channel < 15 &&
-+	    (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F))) {
-+		if (tone_idx_tmp % 2 == 1) {
-+			if (tone_direction == FREQ_POSITIVE) {
-+				/*===Tone 1===*/
-+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
-+					       (table_addr & 0xff));
-+				value = (BIT(3) | (wgt & 0x7)) << 4;
-+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
-+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "New Mask tone 1 idx[%d]: Reg0x1d94 = ((0x%x))\n",
-+					  tone_idx_tmp, reg_tmp);
-+				/*===Tone 2===*/
-+				value = 0;
-+				multi_tone_idx_tmp = tone_idx_tmp + 1;
-+				table_addr = multi_tone_idx_tmp >> 1;
-+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
-+					       (table_addr & 0xff));
-+				value = (BIT(3) | (wgt & 0x7));
-+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
-+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "New Mask tone 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
-+					  tone_idx_tmp, reg_tmp);
-+			} else {
-+				/*===Tone 1 & 2===*/
-+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
-+					       (table_addr & 0xff));
-+				value = ((BIT(3) | (wgt & 0x7)) << 4) |
-+					(BIT(3) | (wgt & 0x7));
-+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
-+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "New Mask tone 1 & 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
-+					  tone_idx_tmp, reg_tmp);
-+			}
-+		} else {
-+			if (tone_direction == FREQ_POSITIVE) {
-+				/*===Tone 1 & 2===*/
-+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
-+					       (table_addr & 0xff));
-+				value = ((BIT(3) | (wgt & 0x7)) << 4) |
-+					(BIT(3) | (wgt & 0x7));
-+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
-+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "New Mask tone 1 & 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
-+					  tone_idx_tmp, reg_tmp);
-+			} else {
-+				/*===Tone 1===*/
-+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
-+					       (table_addr & 0xff));
-+				value = (BIT(3) | (wgt & 0x7));
-+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
-+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "New Mask tone 1 idx[%d]: Reg0x1d94 = ((0x%x))\n",
-+					  tone_idx_tmp, reg_tmp);
-+
-+				/*===Tone 2===*/
-+				value = 0;
-+				multi_tone_idx_tmp = tone_idx_tmp - 1;
-+				table_addr = multi_tone_idx_tmp >> 1;
-+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
-+					       (table_addr & 0xff));
-+				value = (BIT(3) | (wgt & 0x7)) << 4;
-+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
-+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "New Mask tone 2 idx[%d]: Reg0x1d94 = ((0x%x))\n",
-+					  tone_idx_tmp, reg_tmp);
-+			}
-+		}
-+	} else {
-+		if ((dm->support_ic_type & (ODM_RTL8814B)) &&
-+		    phydm_spur_case_mapping(dm)) {
-+			if (!(tone_idx_tmp % 2)) {
-+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
-+					       (table_addr & 0xff));
-+				value = ((BIT(3) | (((wgt + 4) <= 7 ? (wgt +
-+					 4) : 7) & 0x7)) << 4) | (BIT(3) |
-+					 (wgt & 0x7));
-+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
-+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
-+					  tone_idx_tmp, reg_tmp);
-+				if (tone_idx_tmp == 0)
-+					table_addr = tone_num - 1;
-+				else
-+					table_addr = table_addr - 1;
-+				if (tone_idx_tmp != tone_num) {
-+					odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
-+						       (table_addr & 0xff));
-+					value = (BIT(3) | (((wgt + 4) <= 7 ?
-+						 (wgt + 4) : 7) & 0x7)) << 4;
-+					odm_set_bb_reg(dm, R_0x1d94, 0xff,
-+						       value);
-+					reg_tmp = odm_read_4byte(dm, R_0x1d94);
-+					PHYDM_DBG(dm, ODM_COMP_API,
-+						  "New Mask Reg0x1d94 = ((0x%x))\n",
-+						  reg_tmp);
-+				}
-+			} else {
-+				odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
-+					       (table_addr & 0xff));
-+				value = ((BIT(3) | (wgt & 0x7)) << 4) |
-+					 (BIT(3) | (((wgt + 4) <= 7 ? (wgt +
-+					  4) : 7) & 0x7));
-+				odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
-+				reg_tmp = odm_read_4byte(dm, R_0x1d94);
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
-+					  tone_idx_tmp, reg_tmp);
-+				if (tone_idx_tmp == (tone_num << 1) - 1)
-+					table_addr = 0;
-+				else
-+					table_addr = table_addr + 1;
-+				if (tone_idx_tmp != tone_num - 1) {
-+					odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2,
-+						       (table_addr & 0xff));
-+					value = (BIT(3) | (((wgt + 4) <= 7 ?
-+						 (wgt + 4) : 7) & 0x7));
-+					odm_set_bb_reg(dm, R_0x1d94, 0xff,
-+						       value);
-+					reg_tmp = odm_read_4byte(dm, R_0x1d94);
-+					PHYDM_DBG(dm, ODM_COMP_API,
-+						  "New Mask Reg0x1d94 = ((0x%x))\n",
-+						  reg_tmp);
-+				}
-+			}
-+		} else {
-+			odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, (table_addr &
-+				       0xff));
-+			if (tone_idx_tmp % 2)
-+				value = (BIT(3) | (wgt & 0x7)) << 4;
-+			else
-+				value = BIT(3) | (wgt & 0x7);
-+
-+			odm_set_bb_reg(dm, R_0x1d94, 0xff, value);
-+			reg_tmp = odm_read_4byte(dm, R_0x1d94);
-+			PHYDM_DBG(dm, ODM_COMP_API,
-+				  "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n",
-+				  tone_idx_tmp, reg_tmp);
-+		}
-+	}
-+	odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);
-+}
-+
-+void phydm_nbi_reset_jgr3(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	odm_set_bb_reg(dm, R_0x818, BIT(3), 1);
-+	odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0);
-+	odm_set_bb_reg(dm, R_0x818, BIT(3), 0);
-+	odm_set_bb_reg(dm, R_0x818, BIT(11), 0);
-+	#if RTL8814B_SUPPORT
-+	if (dm->support_ic_type & ODM_RTL8814B) {
-+		odm_set_bb_reg(dm, R_0x1944, 0x300, 0x3);
-+		odm_set_bb_reg(dm, R_0x4044, 0x300, 0x3);
-+		odm_set_bb_reg(dm, R_0x5044, 0x300, 0x3);
-+		odm_set_bb_reg(dm, R_0x5144, 0x300, 0x3);
-+		odm_set_bb_reg(dm, R_0x810, 0xf, 0x0);
-+		odm_set_bb_reg(dm, R_0x810, 0xf0000, 0x0);
-+		odm_set_bb_reg(dm, R_0xc24, MASKDWORD, 0x406000ff);
-+	}
-+	#endif
-+}
-+
-+u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
-+			  u32 sec_ch, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 fc = 2412;
-+	u8 direction = FREQ_POSITIVE;
-+	u32 tone_idx = 0;
-+	u8 set_result = PHYDM_SET_SUCCESS;
-+	u8 rpt = 0;
-+
-+	if (enable == FUNC_DISABLE) {
-+		phydm_nbi_reset_jgr3(dm);
-+		set_result = PHYDM_SET_SUCCESS;
-+	} else {
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
-+			  ch, bw, f_intf,
-+			  (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) ||
-+			  (ch > 14)) ? "Don't care" :
-+			  (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
-+
-+		/*@calculate fc*/
-+		if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
-+			set_result = PHYDM_SET_FAIL;
-+		} else {
-+			/*@calculate interference distance*/
-+			rpt = phydm_find_intf_distance_jgr3(dm, bw, fc, f_intf,
-+							    &tone_idx);
-+			if (rpt == PHYDM_SET_SUCCESS) {
-+				if (f_intf >= 1000 * fc)
-+					direction = FREQ_POSITIVE;
-+				else
-+					direction = FREQ_NEGATIVE;
-+
-+				phydm_set_nbi_reg_jgr3(dm, tone_idx, direction,
-+						       path);
-+				set_result = PHYDM_SET_SUCCESS;
-+			} else {
-+				set_result = PHYDM_SET_NO_NEED;
-+			}
-+		}
-+	}
-+
-+	if (set_result == PHYDM_SET_SUCCESS)
-+		phydm_nbi_enable_jgr3(dm, enable, path);
-+	else
-+		phydm_nbi_enable_jgr3(dm, FUNC_DISABLE, path);
-+
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		odm_set_bb_reg(dm, R_0x1d3c, BIT(19), 0);
-+
-+	return set_result;
-+}
-+
-+void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
-+			    u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 reg_tmp_value = 0;
-+	u32 tone_num = 64;
-+	u32 addr = 0;
-+	u8 rf_bw = 0;
-+
-+	rf_bw = odm_read_1byte(dm, R_0x9b0);
-+	if (((rf_bw & 0xc) >> 2) == 0x2)
-+		tone_num = 128; /* RF80 : tone-1 at tone_idx=255 */
-+	else
-+		tone_num = 64; /* RF20/40 : tone-1 at tone_idx=127 */
-+
-+	if (tone_direction == FREQ_POSITIVE) {
-+		if (tone_idx_tmp >= (tone_num - 1))
-+			tone_idx_tmp = (tone_num - 1);
-+	} else {
-+		if (tone_idx_tmp >= tone_num)
-+			tone_idx_tmp = tone_num;
-+
-+		tone_idx_tmp = (tone_num << 1) - tone_idx_tmp;
-+	}
-+	/*Mark the tone idx for Packet detection*/
-+	#if RTL8814B_SUPPORT
-+	if (dm->support_ic_type & ODM_RTL8814B) {
-+		odm_set_bb_reg(dm, R_0xc24, 0xff, 0xff);
-+		if ((*dm->channel == 5) &&
-+		    (*dm->band_width == CHANNEL_WIDTH_40))
-+			odm_set_bb_reg(dm, R_0xc24, 0xff00, 0x1a);
-+		else
-+			odm_set_bb_reg(dm, R_0xc24, 0xff00, tone_idx_tmp);
-+	}
-+	#endif
-+	switch (path) {
-+	case RF_PATH_A:
-+		odm_set_bb_reg(dm, R_0x1944, 0x001FF000, tone_idx_tmp);
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "Set tone idx[%d]:PATH-A = ((0x%x))\n",
-+			  tone_idx_tmp, tone_idx_tmp);
-+		break;
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	case RF_PATH_B:
-+		odm_set_bb_reg(dm, R_0x4044, 0x001FF000, tone_idx_tmp);
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "Set tone idx[%d]:PATH-B = ((0x%x))\n",
-+			  tone_idx_tmp, tone_idx_tmp);
-+		break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	case RF_PATH_C:
-+		odm_set_bb_reg(dm, R_0x5044, 0x001FF000, tone_idx_tmp);
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "Set tone idx[%d]:PATH-C = ((0x%x))\n",
-+			  tone_idx_tmp, tone_idx_tmp);
-+		break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	case RF_PATH_D:
-+		odm_set_bb_reg(dm, R_0x5144, 0x001FF000, tone_idx_tmp);
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "Set tone idx[%d]:PATH-D = ((0x%x))\n",
-+			  tone_idx_tmp, tone_idx_tmp);
-+		break;
-+	#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean val = false;
-+
-+	val = (enable == FUNC_ENABLE) ? true : false;
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val);
-+
-+	if (dm->support_ic_type & ODM_RTL8814B) {
-+		odm_set_bb_reg(dm, R_0x1d3c, BIT(19), val);
-+		odm_set_bb_reg(dm, R_0x818, BIT(3), val);
-+	} else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
-+		odm_set_bb_reg(dm, R_0x818, BIT(3), !val);
-+	}
-+	odm_set_bb_reg(dm, R_0x818, BIT(11), val);
-+	odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0xf);
-+
-+	if (enable == FUNC_ENABLE) {
-+		switch (path) {
-+		case RF_PATH_A:
-+			odm_set_bb_reg(dm, R_0x1940, BIT(31), val);
-+			break;
-+		#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+		case RF_PATH_B:
-+			odm_set_bb_reg(dm, R_0x4040, BIT(31), val);
-+			break;
-+		#endif
-+		#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+		case RF_PATH_C:
-+			odm_set_bb_reg(dm, R_0x5040, BIT(31), val);
-+			break;
-+		#endif
-+		#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+		case RF_PATH_D:
-+			odm_set_bb_reg(dm, R_0x5140, BIT(31), val);
-+			break;
-+		#endif
-+		default:
-+			break;
-+		}
-+	} else {
-+		odm_set_bb_reg(dm, R_0x1940, BIT(31), val);
-+		#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+		odm_set_bb_reg(dm, R_0x4040, BIT(31), val);
-+		#endif
-+		#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+		odm_set_bb_reg(dm, R_0x5040, BIT(31), val);
-+		#endif
-+		#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+		odm_set_bb_reg(dm, R_0x5140, BIT(31), val);
-+		#endif
-+		#if RTL8812F_SUPPORT
-+		if (dm->support_ic_type & ODM_RTL8812F) {
-+			odm_set_bb_reg(dm, R_0x818, BIT(3), val);
-+			odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0x0);
-+		}
-+		#endif
-+	}
-+}
-+
-+u8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info,
-+			  enum rf_path ant_path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	s8 evm_org, cfo_org, rxsnr_org;
-+	u8 i, return_info = 0, tmp_lsb = 0, tmp_msb = 0, tmp_info = 0;
-+
-+	/* Update the status for each pkt */
-+	odm_set_bb_reg(dm, R_0x8c4, 0xfff000, 0x448);
-+	odm_set_bb_reg(dm, R_0x8c0, MASKLWORD, 0x4001);
-+	/* PHY status Page1 */
-+	odm_set_bb_reg(dm, R_0x8c0, 0x3C00000, 0x1);
-+	/*choose debug port for phystatus */
-+	odm_set_bb_reg(dm, R_0x1c3c, 0xFFF00, 0x380);
-+
-+	if (info == PHY_PWDB) {
-+		/* Choose the report of the diff path */
-+		if (ant_path == RF_PATH_A)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1);
-+		else if (ant_path == RF_PATH_B)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x2);
-+		else if (ant_path == RF_PATH_C)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x3);
-+		else if (ant_path == RF_PATH_D)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x4);
-+	} else if (info == PHY_EVM) {
-+		/* Choose the report of the diff path */
-+		if (ant_path == RF_PATH_A)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x10);
-+		else if (ant_path == RF_PATH_B)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x11);
-+		else if (ant_path == RF_PATH_C)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x12);
-+		else if (ant_path == RF_PATH_D)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x13);
-+		return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
-+	} else if (info == PHY_CFO) {
-+		/* Choose the report of the diff path */
-+		if (ant_path == RF_PATH_A)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x14);
-+		else if (ant_path == RF_PATH_B)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x15);
-+		else if (ant_path == RF_PATH_C)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x16);
-+		else if (ant_path == RF_PATH_D)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x17);
-+		return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
-+	} else if (info == PHY_RXSNR) {
-+		/* Choose the report of the diff path */
-+		if (ant_path == RF_PATH_A)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x18);
-+		else if (ant_path == RF_PATH_B)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x19);
-+		else if (ant_path == RF_PATH_C)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1a);
-+		else if (ant_path == RF_PATH_D)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1b);
-+		return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
-+	} else if (info == PHY_LGAIN) {
-+		/* choose page */
-+		odm_set_bb_reg(dm, R_0x8c0, 0x3c00000, 0x2);
-+		/* Choose the report of the diff path */
-+		if (ant_path == RF_PATH_A) {
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xd);
-+			tmp_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3f);
-+			return_info = tmp_info;
-+		} else if (ant_path == RF_PATH_B) {
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xd);
-+			tmp_lsb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xc0);
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xe);
-+			tmp_msb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xf);
-+			tmp_info |= (tmp_msb << 2) | tmp_lsb;
-+			return_info = tmp_info;
-+		} else if (ant_path == RF_PATH_C) {
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xe);
-+			tmp_lsb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xf0);
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xf);
-+			tmp_msb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3);
-+			tmp_info |= (tmp_msb << 4) | tmp_lsb;
-+			return_info = tmp_info;
-+		} else if (ant_path == RF_PATH_D) {
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x10);
-+			tmp_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3f);
-+			return_info = tmp_info;
-+		}
-+	} else if (info == PHY_HT_AAGC_GAIN) {
-+		/* choose page */
-+		odm_set_bb_reg(dm, R_0x8c0, 0x3c00000, 0x2);
-+		/* Choose the report of the diff path */
-+		if (ant_path == RF_PATH_A)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x12);
-+		else if (ant_path == RF_PATH_B)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x13);
-+		else if (ant_path == RF_PATH_C)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x14);
-+		else if (ant_path == RF_PATH_D)
-+			odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x15);
-+		return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff);
-+	}
-+	return return_info;
-+}
-+
-+void phydm_ex_hal8814b_wifi_only_hw_config(void *dm_void)
-+{
-+	/*BB control*/
-+	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2);*/
-+	/*SW control*/
-+	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0xff, 0x77);*/
-+	/*antenna mux switch */
-+	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x974, 0x300, 0x3);*/
-+
-+	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1990, 0x300, 0x0);*/
-+
-+	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x80000, 0x0);*/
-+	/*switch to WL side controller and gnt_wl gnt_bt debug signal */
-+	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0xff000000, 0x0e);*/
-+	/*gnt_wl=1 , gnt_bt=0*/
-+	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff,
-+	 *			     0x7700);
-+	 */
-+	/*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff,
-+	 *			     0xc00f0038);
-+	 */
-+}
-+
-+void phydm_user_position_for_sniffer(void *dm_void, u8 user_position)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	/* user position valid */
-+	odm_set_bb_reg(dm, R_0xa68, BIT(17), 1);
-+	/* Select user seat from pmac */
-+	odm_set_bb_reg(dm, R_0xa68, BIT(16), 1);
-+	/*user seat*/
-+	odm_set_bb_reg(dm, R_0xa68, (BIT(19) | BIT(18)), user_position);
-+}
-+
-+boolean
-+phydm_bb_ctrl_txagc_ofst_jgr3(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
-+			      u8 add_half_db /*@(+0.5 dB)*/)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	s8 pw_idx = pw_offset * 4; /*@ 7Bit, 0.25dB unit*/
-+
-+	if (pw_offset < -16 || pw_offset > 15) {
-+		pr_debug("[Warning][%s]Ofst error=%d", __func__, pw_offset);
-+		return false;
-+	}
-+
-+	if (add_half_db)
-+		pw_idx += 2;
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "Pw_ofst=0x%x\n", pw_idx);
-+
-+	odm_set_bb_reg(dm, R_0x18a0, 0x3f, pw_idx);
-+
-+	if (dm->num_rf_path >= 2)
-+		odm_set_bb_reg(dm, R_0x41a0, 0x3f, pw_idx);
-+
-+	if (dm->num_rf_path >= 3)
-+		odm_set_bb_reg(dm, R_0x52a0, 0x3f, pw_idx);
-+
-+	if (dm->num_rf_path >= 4)
-+		odm_set_bb_reg(dm, R_0x53a0, 0x3f, pw_idx);
-+
-+	return true;
-+}
-+
-+#endif
-+u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
-+		     u32 sec_ch)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 fc = 2412;
-+	u8 direction = FREQ_POSITIVE;
-+	u32 tone_idx = 0;
-+	u8 set_result = PHYDM_SET_SUCCESS;
-+	u8 rpt = 0;
-+
-+	if (enable == FUNC_DISABLE) {
-+		set_result = PHYDM_SET_SUCCESS;
-+	} else {
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
-+			  ch, bw, f_intf,
-+			  (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) ||
-+			  (ch > 14)) ? "Don't care" :
-+			  (sec_ch == PHYDM_ABOVE) ? "H" : "L"));
-+
-+		/*@calculate fc*/
-+		if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) {
-+			set_result = PHYDM_SET_FAIL;
-+		} else {
-+			/*@calculate interference distance*/
-+			rpt = phydm_find_intf_distance(dm, bw, fc, f_intf,
-+						       &tone_idx);
-+			if (rpt == PHYDM_SET_SUCCESS) {
-+				if (f_intf >= fc)
-+					direction = FREQ_POSITIVE;
-+				else
-+					direction = FREQ_NEGATIVE;
-+
-+				phydm_set_nbi_reg(dm, tone_idx, bw);
-+
-+				set_result = PHYDM_SET_SUCCESS;
-+			} else {
-+				set_result = PHYDM_SET_NO_NEED;
-+		}
-+	}
-+	}
-+
-+	if (set_result == PHYDM_SET_SUCCESS)
-+		phydm_nbi_enable(dm, enable);
-+	else
-+		phydm_nbi_enable(dm, FUNC_DISABLE);
-+
-+	return set_result;
-+}
-+
-+void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used, char *output,
-+		     u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 val[10] = {0};
-+	char help[] = "-h";
-+	u8 i = 0, input_idx = 0, idx_lmt = 0;
-+	u32 enable = 0; /*@function enable*/
-+	u32 ch = 0;
-+	u32 bw = 0;
-+	u32 f_int = 0; /*@interference frequency*/
-+	u32 sec_ch = 0; /*secondary channel*/
-+	u8 rpt = 0;
-+	u8 path = 0;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		idx_lmt = 6;
-+	else
-+		idx_lmt = 5;
-+	for (i = 0; i < idx_lmt; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
-+		input_idx++;
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	enable = val[0];
-+	ch = val[1];
-+	bw = val[2];
-+	f_int = val[3];
-+	sec_ch = val[4];
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	path = (u8)val[5];
-+	#endif
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(khz)} {Scnd_CH(L=1, H=2)} {Path:A~D(0~3)}\n");
-+		else
-+		#endif
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(khz)} {Scnd_CH(L=1, H=2)}\n");
-+		*_used = used;
-+		*_out_len = out_len;
-+		return;
-+	} else if (val[0] == FUNC_ENABLE) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
-+			 ch, bw, f_int,
-+			 ((sec_ch == PHYDM_DONT_CARE) ||
-+			 (bw == 20) || (ch > 14)) ? "Don't care" :
-+			 ((sec_ch == PHYDM_ABOVE) ? "H" : "L"));
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+			rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int,
-+						     sec_ch, path);
-+		else
-+		#endif
-+			rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int,
-+						sec_ch);
-+	} else if (val[0] == FUNC_DISABLE) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[Disable NBI]\n");
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+			rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int,
-+						     sec_ch, path);
-+		else
-+		#endif
-+			rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int,
-+						sec_ch);
-+	} else {
-+		rpt = PHYDM_SET_FAIL;
-+	}
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "[NBI set result: %s]\n",
-+		 (rpt == PHYDM_SET_SUCCESS) ? "Success" :
-+		 ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error"));
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used, char *output,
-+		     u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 val[10] = {0};
-+	char help[] = "-h";
-+	u8 i = 0, input_idx = 0, idx_lmt = 0;
-+	u32 enable = 0;  /*@function enable*/
-+	u32 ch = 0;
-+	u32 bw = 0;
-+	u32 f_int = 0; /*@interference frequency*/
-+	u32 sec_ch = 0;  /*secondary channel*/
-+	u8 rpt = 0;
-+	u8 wgt = 0;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		idx_lmt = 6;
-+	else
-+		idx_lmt = 5;
-+
-+	for (i = 0; i < idx_lmt; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
-+		input_idx++;
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	enable = val[0];
-+	ch = val[1];
-+	bw = val[2];
-+	f_int = val[3];
-+	sec_ch = val[4];
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	wgt = (u8)val[5];
-+	#endif
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(KHz)} {Scnd_CH(L=1, H=2)}\n{wgt:(7:3/4),(6~1: 1/2 ~ 1/64),(0:0)}\n");
-+		else
-+		#endif
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)}\n");
-+
-+		*_used = used;
-+		*_out_len = out_len;
-+		return;
-+
-+	} else if (val[0] == FUNC_ENABLE) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
-+			 ch, bw, f_int,
-+			 (ch > 14) ? "Don't care" :
-+			 (((sec_ch == PHYDM_DONT_CARE) ||
-+			 (bw == 20) || (ch > 14)) ? "H" : "L"));
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+			rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw,
-+							  f_int, sec_ch, wgt);
-+		else
-+		#endif
-+			rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int,
-+						     sec_ch);
-+	} else if (val[0] == FUNC_DISABLE) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[Disable CSI MASK]\n");
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+			rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw,
-+							  f_int, sec_ch, wgt);
-+		else
-+		#endif
-+			rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int,
-+						     sec_ch);
-+	} else {
-+		rpt = PHYDM_SET_FAIL;
-+	}
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "[CSI MASK set result: %s]\n",
-+		 (rpt == PHYDM_SET_SUCCESS) ? "Success" :
-+		 ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error"));
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_stop_ck320(void *dm_void, u8 enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 val = enable ? 1 : 0;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		odm_set_bb_reg(dm, R_0x8b4, BIT(6), val);
-+	} else {
-+		if (dm->support_ic_type & ODM_IC_N_2SS) /*N-2SS*/
-+			odm_set_bb_reg(dm, R_0x87c, BIT(29), val);
-+		else /*N-1SS*/
-+			odm_set_bb_reg(dm, R_0x87c, BIT(31), val);
-+	}
-+}
-+
-+boolean
-+phydm_bb_ctrl_txagc_ofst(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
-+			 u8 add_half_db /*@(+0.5 dB)*/)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	s8 pw_idx;
-+	u8 offset_bit_num = 0;
-+
-+	if (dm->support_ic_type & N_IC_TX_OFFEST_5_BIT) {
-+		/*@ 5Bit, 0.5dB unit*/
-+		if (pw_offset < -8 || pw_offset > 7) {
-+			pr_debug("[Warning][%s] Ofst=%d", __func__, pw_offset);
-+			return false;
-+		}
-+		offset_bit_num = 5;
-+	} else {
-+		if (pw_offset < -16 || pw_offset > 15) {
-+			pr_debug("[Warning][%s] Ofst=%d", __func__, pw_offset);
-+			return false;
-+		}
-+		if (dm->support_ic_type & N_IC_TX_OFFEST_7_BIT) {
-+		/*@ 7Bit, 0.25dB unit*/
-+			offset_bit_num = 7;
-+		} else {
-+		/*@ 6Bit, 0.5dB unit*/
-+			offset_bit_num = 6;
-+		}
-+	}
-+
-+	pw_idx = (offset_bit_num == 7) ? pw_offset * 4 : pw_offset * 2;
-+
-+	if (add_half_db)
-+		pw_idx = (offset_bit_num == 7) ? pw_idx + 2 : pw_idx + 1;
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "Pw_ofst=0x%x\n", pw_idx);
-+
-+	switch (dm->ic_ip_series) {
-+	case PHYDM_IC_AC:
-+		odm_set_bb_reg(dm, R_0x8b4, 0x3f, pw_idx); /*6Bit*/
-+		break;
-+	case PHYDM_IC_N:
-+		if (offset_bit_num == 5) {
-+			odm_set_bb_reg(dm, R_0x80c, 0x1f00, pw_idx);
-+			if (dm->num_rf_path >= 2)
-+				odm_set_bb_reg(dm, R_0x80c, 0x3e000, pw_idx);
-+		} else if (offset_bit_num == 6) {
-+			odm_set_bb_reg(dm, R_0x80c, 0x3f00, pw_idx);
-+			if (dm->num_rf_path >= 2)
-+				odm_set_bb_reg(dm, R_0x80c, 0xfc000, pw_idx);
-+		}  else { /*7Bit*/
-+			odm_set_bb_reg(dm, R_0x80c, 0x7f00, pw_idx);
-+			if (dm->num_rf_path >= 2)
-+				odm_set_bb_reg(dm, R_0x80c, 0x3f8000, pw_idx);
-+		}
-+		break;
-+	}
-+	return true;
-+}
-+
-+boolean
-+phydm_set_bb_txagc_offset(void *dm_void, s8 pw_offset, /*@(unit: dB)*/
-+			  u8 add_half_db /*@(+0.5 dB)*/)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean rpt = false;
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "power_offset=%d, add_half_db =%d\n",
-+		  pw_offset, add_half_db);
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		rpt = phydm_bb_ctrl_txagc_ofst_jgr3(dm, pw_offset, add_half_db);
-+	} else
-+#endif
-+	{
-+		rpt = phydm_bb_ctrl_txagc_ofst(dm, pw_offset, add_half_db);
-+	}
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "TX AGC Offset set_success=%d", rpt);
-+
-+	return rpt;
-+}
-+
-+#ifdef PHYDM_COMMON_API_SUPPORT
-+void phydm_reset_txagc(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 r_txagc_cck[4] = {R_0x18a0, R_0x41a0, R_0x52a0, R_0x53a0};
-+	u32 r_txagc_ofdm[4] = {R_0x18e8, R_0x41e8, R_0x52e8, R_0x53e8};
-+	u32 r_txagc_diff = R_0x3a00;
-+	u8 i = 0;
-+
-+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
-+		PHYDM_DBG(dm, ODM_COMP_API, "Only for JGR3 ICs!\n");
-+		return;
-+	}
-+
-+	for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
-+		odm_set_bb_reg(dm, r_txagc_cck[i], 0x7f0000, 0x0);
-+		odm_set_bb_reg(dm, r_txagc_ofdm[i], 0x1fc00, 0x0);
-+	}
-+
-+	for (i = 0; i <= ODM_RATEVHTSS4MCS6; i = i + 4)
-+		odm_set_bb_reg(dm, r_txagc_diff + i, MASKDWORD, 0x0);
-+}
-+boolean
-+phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
-+		      boolean is_positive) {
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean ret = false;
-+	u32 txagc_cck = 0;
-+	u32 txagc_ofdm = 0;
-+	u32 r_txagc_ofdm[4] = {R_0x18e8, R_0x41e8, R_0x52e8, R_0x53e8};
-+	u32 r_txagc_cck[4] = {R_0x18a0, R_0x41a0, R_0x52a0, R_0x53a0};
-+
-+	#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT)
-+	if (dm->support_ic_type &
-+	   (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) {
-+		if (path > RF_PATH_B) {
-+			PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
-+				  path);
-+			return false;
-+		}
-+		txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path],
-+						   0x7F0000);
-+		txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path],
-+						    0x1FC00);
-+		if (is_positive) {
-+			if (((txagc_cck + pwr_offset) > 127) ||
-+			    ((txagc_ofdm + pwr_offset) > 127))
-+				return false;
-+
-+			txagc_cck += pwr_offset;
-+			txagc_ofdm += pwr_offset;
-+		} else {
-+			if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
-+				return false;
-+
-+			txagc_cck -= pwr_offset;
-+			txagc_ofdm -= pwr_offset;
-+		}
-+		#if (RTL8822C_SUPPORT)
-+		ret = config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_cck,
-+							 path, PDM_CCK);
-+		ret &= config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_ofdm,
-+							 path, PDM_OFDM);
-+		#endif
-+		#if (RTL8812F_SUPPORT)
-+		ret = config_phydm_write_txagc_ref_8812f(dm, (u8)txagc_cck,
-+							 path, PDM_CCK);
-+		ret &= config_phydm_write_txagc_ref_8812f(dm, (u8)txagc_ofdm,
-+							 path, PDM_OFDM);
-+		#endif
-+		#if (RTL8197G_SUPPORT)
-+		ret = config_phydm_write_txagc_ref_8197g(dm, (u8)txagc_cck,
-+							 path, PDM_CCK);
-+		ret &= config_phydm_write_txagc_ref_8197g(dm, (u8)txagc_ofdm,
-+							 path, PDM_OFDM);
-+		#endif
-+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
-+			  "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
-+			  __func__, path, txagc_cck, txagc_ofdm);
-+	}
-+	#endif
-+
-+	#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) {
-+		if (path > RF_PATH_D) {
-+			PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
-+				  path);
-+			return false;
-+		}
-+		txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path],
-+						   0x7F0000);
-+		txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path],
-+						    0x1FC00);
-+		if (is_positive) {
-+			if (((txagc_cck + pwr_offset) > 127) ||
-+			    ((txagc_ofdm + pwr_offset) > 127))
-+				return false;
-+
-+			txagc_cck += pwr_offset;
-+			txagc_ofdm += pwr_offset;
-+		} else {
-+			if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
-+				return false;
-+
-+			txagc_cck -= pwr_offset;
-+			txagc_ofdm -= pwr_offset;
-+		}
-+		#if (RTL8198F_SUPPORT)
-+		ret = config_phydm_write_txagc_ref_8198f(dm, (u8)txagc_cck,
-+							 path, PDM_CCK);
-+		ret &= config_phydm_write_txagc_ref_8198f(dm, (u8)txagc_ofdm,
-+							 path, PDM_OFDM);
-+		#endif
-+		#if (RTL8814B_SUPPORT)
-+		ret = config_phydm_write_txagc_ref_8814b(dm, (u8)txagc_cck,
-+							 path, PDM_CCK);
-+		ret &= config_phydm_write_txagc_ref_8814b(dm, (u8)txagc_ofdm,
-+							 path, PDM_OFDM);
-+		#endif
-+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
-+			  "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
-+			  __func__, path, txagc_cck, txagc_ofdm);
-+	}
-+	#endif
-+
-+	#if (RTL8723F_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8723F)) {
-+		if (path > RF_PATH_A) {
-+			PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n",
-+				  path);
-+			return false;
-+		}
-+		txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path],
-+						   0x7F0000);
-+		txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path],
-+						    0x1FC00);
-+		if (is_positive) {
-+			if (((txagc_cck + pwr_offset) > 127) ||
-+			    ((txagc_ofdm + pwr_offset) > 127))
-+				return false;
-+
-+			txagc_cck += pwr_offset;
-+			txagc_ofdm += pwr_offset;
-+		} else {
-+			if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm)
-+				return false;
-+
-+			txagc_cck -= pwr_offset;
-+			txagc_ofdm -= pwr_offset;
-+		}
-+		#if (RTL8723F_SUPPORT)
-+		ret = config_phydm_write_txagc_ref_8723f(dm, (u8)txagc_cck,
-+							 path, PDM_CCK);
-+		ret &= config_phydm_write_txagc_ref_8723f(dm, (u8)txagc_ofdm,
-+							 path, PDM_OFDM);
-+		#endif
-+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
-+			  "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n",
-+			  __func__, path, txagc_cck, txagc_ofdm);
-+	}
-+	#endif
-+
-+	return ret;
-+}
-+
-+boolean
-+phydm_api_set_txagc(void *dm_void, u32 pwr_idx, enum rf_path path,
-+		    u8 rate, boolean is_single_rate)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean ret = false;
-+	#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT ||\
-+	     RTL8814B_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
-+	u8 base = 0;
-+	u8 txagc_tmp = 0;
-+	s8 pw_by_rate_tmp = 0;
-+	s8 pw_by_rate_new = 0;
-+	#endif
-+	#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	u8 i = 0;
-+	#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)
-+	if (dm->support_ic_type &
-+	    (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) {
-+		if (is_single_rate) {
-+			#if (RTL8822B_SUPPORT)
-+			if (dm->support_ic_type == ODM_RTL8822B)
-+				ret = phydm_write_txagc_1byte_8822b(dm, pwr_idx,
-+								    path, rate);
-+			#endif
-+
-+			#if (RTL8821C_SUPPORT)
-+			if (dm->support_ic_type == ODM_RTL8821C)
-+				ret = phydm_write_txagc_1byte_8821c(dm, pwr_idx,
-+								    path, rate);
-+			#endif
-+
-+			#if (RTL8195B_SUPPORT)
-+			if (dm->support_ic_type == ODM_RTL8195B)
-+				ret = phydm_write_txagc_1byte_8195b(dm, pwr_idx,
-+								    path, rate);
-+			#endif
-+
-+			#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+			set_current_tx_agc(dm->priv, path, rate, (u8)pwr_idx);
-+			#endif
-+
-+		} else {
-+			#if (RTL8822B_SUPPORT)
-+			if (dm->support_ic_type == ODM_RTL8822B)
-+				ret = config_phydm_write_txagc_8822b(dm,
-+								     pwr_idx,
-+								     path,
-+								     rate);
-+			#endif
-+
-+			#if (RTL8821C_SUPPORT)
-+			if (dm->support_ic_type == ODM_RTL8821C)
-+				ret = config_phydm_write_txagc_8821c(dm,
-+								     pwr_idx,
-+								     path,
-+								     rate);
-+			#endif
-+
-+			#if (RTL8195B_SUPPORT)
-+			if (dm->support_ic_type == ODM_RTL8195B)
-+				ret = config_phydm_write_txagc_8195b(dm,
-+								     pwr_idx,
-+								     path,
-+								     rate);
-+			#endif
-+
-+			#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+			for (i = 0; i < 4; i++)
-+				set_current_tx_agc(dm->priv, path, (rate + i),
-+						   (u8)pwr_idx);
-+			#endif
-+		}
-+	}
-+#endif
-+
-+#if (RTL8198F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8198F) {
-+		if (rate < 0x4)
-+			txagc_tmp = config_phydm_read_txagc_8198f(dm, path,
-+								  rate,
-+								  PDM_CCK);
-+		else
-+			txagc_tmp = config_phydm_read_txagc_8198f(dm, path,
-+								  rate,
-+								  PDM_OFDM);
-+
-+		pw_by_rate_tmp = config_phydm_read_txagc_diff_8198f(dm, rate);
-+		base = txagc_tmp -  pw_by_rate_tmp;
-+		base = base & 0x7f;
-+		if (DIFF_2((pwr_idx & 0x7f), base) > 64 || pwr_idx > 127)
-+			return false;
-+
-+		pw_by_rate_new = (s8)(pwr_idx - base);
-+		ret = phydm_write_txagc_1byte_8198f(dm, pw_by_rate_new, rate);
-+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
-+			  "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
-+			  __func__, path, rate, base, pw_by_rate_new);
-+	}
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8822C) {
-+		if (rate < 0x4)
-+			txagc_tmp = config_phydm_read_txagc_8822c(dm, path,
-+								  rate,
-+								  PDM_CCK);
-+		else
-+			txagc_tmp = config_phydm_read_txagc_8822c(dm, path,
-+								  rate,
-+								  PDM_OFDM);
-+
-+		pw_by_rate_tmp = config_phydm_read_txagc_diff_8822c(dm, rate);
-+		base = txagc_tmp - pw_by_rate_tmp;
-+		base = base & 0x7f;
-+		if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
-+			return false;
-+
-+		pw_by_rate_new = (s8)(pwr_idx - base);
-+		ret = phydm_write_txagc_1byte_8822c(dm, pw_by_rate_new, rate);
-+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
-+			  "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
-+			  __func__, path, rate, base, pw_by_rate_new);
-+	}
-+#endif
-+
-+#if (RTL8814B_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8814B) {
-+		if (rate < 0x4)
-+			txagc_tmp = config_phydm_read_txagc_8814b(dm, path,
-+								  rate,
-+								  PDM_CCK);
-+		else
-+			txagc_tmp = config_phydm_read_txagc_8814b(dm, path,
-+								  rate,
-+								  PDM_OFDM);
-+
-+		pw_by_rate_tmp = config_phydm_read_txagc_diff_8814b(dm, rate);
-+		base = txagc_tmp -  pw_by_rate_tmp;
-+		base = base & 0x7f;
-+		if (DIFF_2((pwr_idx & 0x7f), base) > 64)
-+			return false;
-+
-+		pw_by_rate_new = (s8)(pwr_idx - base);
-+		ret = phydm_write_txagc_1byte_8814b(dm, pw_by_rate_new, rate);
-+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
-+			  "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
-+			  __func__, path, rate, base, pw_by_rate_new);
-+	}
-+#endif
-+
-+#if (RTL8812F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8812F) {
-+		if (rate < 0x4)
-+			txagc_tmp = config_phydm_read_txagc_8812f(dm, path,
-+								  rate,
-+								  PDM_CCK);
-+		else
-+			txagc_tmp = config_phydm_read_txagc_8812f(dm, path,
-+								  rate,
-+								  PDM_OFDM);
-+
-+		pw_by_rate_tmp = config_phydm_read_txagc_diff_8812f(dm, rate);
-+		base = txagc_tmp - pw_by_rate_tmp;
-+		base = base & 0x7f;
-+		if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
-+			return false;
-+
-+		pw_by_rate_new = (s8)(pwr_idx - base);
-+		ret = phydm_write_txagc_1byte_8812f(dm, pw_by_rate_new, rate);
-+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
-+			  "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
-+			  __func__, path, rate, base, pw_by_rate_new);
-+	}
-+#endif
-+
-+#if (RTL8197G_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197G) {
-+		if (rate < 0x4)
-+			txagc_tmp = config_phydm_read_txagc_8197g(dm, path,
-+								  rate,
-+								  PDM_CCK);
-+		else
-+			txagc_tmp = config_phydm_read_txagc_8197g(dm, path,
-+								  rate,
-+								  PDM_OFDM);
-+
-+		pw_by_rate_tmp = config_phydm_read_txagc_diff_8197g(dm, rate);
-+		base = txagc_tmp - pw_by_rate_tmp;
-+		base = base & 0x7f;
-+		if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
-+			return false;
-+
-+		pw_by_rate_new = (s8)(pwr_idx - base);
-+		ret = phydm_write_txagc_1byte_8197g(dm, pw_by_rate_new, rate);
-+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
-+			  "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
-+			  __func__, path, rate, base, pw_by_rate_new);
-+	}
-+#endif
-+#if (RTL8723F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8723F) {
-+		if (rate < 0x4)
-+			txagc_tmp = config_phydm_read_txagc_8723f(dm, path,
-+								  rate,
-+								  PDM_CCK);
-+		else
-+			txagc_tmp = config_phydm_read_txagc_8723f(dm, path,
-+								  rate,
-+								  PDM_OFDM);
-+
-+		pw_by_rate_tmp = config_phydm_read_txagc_diff_8723f(dm, rate);
-+		base = txagc_tmp - pw_by_rate_tmp;
-+		base = base & 0x7f;
-+		if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127)
-+			return false;
-+
-+		pw_by_rate_new = (s8)(pwr_idx - base);
-+		ret = phydm_write_txagc_1byte_8723f(dm, pw_by_rate_new, rate);
-+		PHYDM_DBG(dm, ODM_PHY_CONFIG,
-+			  "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n",
-+			  __func__, path, rate, base, pw_by_rate_new);
-+	}
-+#endif
-+
-+#if (RTL8197F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197F)
-+		ret = config_phydm_write_txagc_8197f(dm, pwr_idx, path, rate);
-+#endif
-+
-+#if (RTL8192F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8192F)
-+		ret = config_phydm_write_txagc_8192f(dm, pwr_idx, path, rate);
-+#endif
-+
-+#if (RTL8721D_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8721D)
-+		ret = config_phydm_write_txagc_8721d(dm, pwr_idx, path, rate);
-+#endif
-+#if (RTL8710C_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8710C)
-+		ret = config_phydm_write_txagc_8710c(dm, pwr_idx, path, rate);
-+#endif
-+	return ret;
-+}
-+
-+u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 ret = 0;
-+
-+#if (RTL8822B_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8822B)
-+		ret = config_phydm_read_txagc_8822b(dm, path, hw_rate);
-+#endif
-+
-+#if (RTL8197F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197F)
-+		ret = config_phydm_read_txagc_8197f(dm, path, hw_rate);
-+#endif
-+
-+#if (RTL8821C_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8821C)
-+		ret = config_phydm_read_txagc_8821c(dm, path, hw_rate);
-+#endif
-+
-+#if (RTL8195B_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8195B)
-+		ret = config_phydm_read_txagc_8195b(dm, path, hw_rate);
-+#endif
-+
-+/*@jj add 20170822*/
-+#if (RTL8192F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8192F)
-+		ret = config_phydm_read_txagc_8192f(dm, path, hw_rate);
-+#endif
-+
-+#if (RTL8198F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8198F) {
-+		if (hw_rate < 0x4) {
-+			ret = config_phydm_read_txagc_8198f(dm, path, hw_rate,
-+							    PDM_CCK);
-+		} else {
-+			ret = config_phydm_read_txagc_8198f(dm, path, hw_rate,
-+							    PDM_OFDM);
-+		}
-+	}
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8822C) {
-+		if (hw_rate < 0x4) {
-+			ret = config_phydm_read_txagc_8822c(dm, path, hw_rate,
-+							    PDM_CCK);
-+		} else {
-+			ret = config_phydm_read_txagc_8822c(dm, path, hw_rate,
-+							    PDM_OFDM);
-+		}
-+	}
-+#endif
-+
-+#if (RTL8723F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8723F) {
-+		if (hw_rate < 0x4) {
-+			ret = config_phydm_read_txagc_8723f(dm, path, hw_rate,
-+							    PDM_CCK);
-+		} else {
-+			ret = config_phydm_read_txagc_8723f(dm, path, hw_rate,
-+							    PDM_OFDM);
-+		}
-+	}
-+#endif
-+
-+#if (RTL8814B_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8814B) {
-+		if (hw_rate < 0x4) {
-+			ret = config_phydm_read_txagc_8814b(dm, path, hw_rate,
-+							    PDM_CCK);
-+		} else {
-+			ret = config_phydm_read_txagc_8814b(dm, path, hw_rate,
-+							    PDM_OFDM);
-+		}
-+	}
-+#endif
-+
-+#if (RTL8812F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8812F) {
-+		if (hw_rate < 0x4) {
-+			ret = config_phydm_read_txagc_8812f(dm, path, hw_rate,
-+							    PDM_CCK);
-+		} else {
-+			ret = config_phydm_read_txagc_8812f(dm, path, hw_rate,
-+							    PDM_OFDM);
-+		}
-+	}
-+#endif
-+
-+#if (RTL8197G_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197G) {
-+		if (hw_rate < 0x4) {
-+			ret = config_phydm_read_txagc_8197g(dm, path,
-+							    hw_rate,
-+							    PDM_CCK);
-+		} else {
-+			ret = config_phydm_read_txagc_8197g(dm, path,
-+							    hw_rate,
-+							    PDM_OFDM);
-+		}
-+	}
-+#endif
-+
-+#if (RTL8721D_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8721D)
-+		ret = config_phydm_read_txagc_8721d(dm, path, hw_rate);
-+#endif
-+#if (RTL8710C_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8710C)
-+		ret = config_phydm_read_txagc_8710c(dm, path, hw_rate);
-+#endif
-+	return ret;
-+}
-+
-+#if (RTL8822C_SUPPORT)
-+void phydm_shift_rxagc_table(void *dm_void, boolean is_pos_shift, u8 sft)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i = 0;
-+	u8 j = 0;
-+	u32 reg = 0;
-+	u16 max_rf_gain = 0;
-+	u16 min_rf_gain = 0;
-+
-+	dm->is_agc_tab_pos_shift = is_pos_shift;
-+	dm->agc_table_shift = sft;
-+
-+	for (i = 0; i <= dm->agc_table_cnt; i++) {
-+		max_rf_gain = dm->agc_rf_gain_ori[i][0];
-+		min_rf_gain = dm->agc_rf_gain_ori[i][63];
-+
-+		if (dm->support_ic_type & ODM_RTL8822C)
-+			dm->l_bnd_detect[i] = false;
-+
-+		for (j = 0; j < 64; j++) {
-+			if (is_pos_shift) {
-+				if (j < sft)
-+					reg = (max_rf_gain & 0x3ff);
-+				else
-+					reg = (dm->agc_rf_gain_ori[i][j - sft] &
-+						 0x3ff);
-+			} else {
-+				if (j > 63 - sft)
-+					reg = (min_rf_gain & 0x3ff);
-+
-+				else
-+					reg = (dm->agc_rf_gain_ori[i][j + sft] &
-+						 0x3ff);
-+			}
-+			dm->agc_rf_gain[i][j] = (u16)(reg & 0x3ff);
-+
-+			reg |= (j & 0x3f) << 16;/*mp_gain_idx*/
-+			reg |= (i & 0xf) << 22;/*table*/
-+			reg |= BIT(29) | BIT(28);/*write en*/
-+			odm_set_bb_reg(dm, R_0x1d90, MASKDWORD, reg);
-+		}
-+	}
-+
-+	if (dm->support_ic_type & ODM_RTL8822C)
-+		odm_set_bb_reg(dm, R_0x828, 0xf8, L_BND_DEFAULT_8822C);
-+}
-+#endif
-+
-+boolean
-+phydm_api_switch_bw_channel(void *dm_void, u8 ch, u8 pri_ch,
-+			    enum channel_width bw)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean ret = false;
-+
-+	switch (dm->support_ic_type) {
-+#if (RTL8822B_SUPPORT)
-+	case ODM_RTL8822B:
-+		ret = config_phydm_switch_channel_bw_8822b(dm, ch, pri_ch, bw);
-+	break;
-+#endif
-+
-+#if (RTL8197F_SUPPORT)
-+	case ODM_RTL8197F:
-+		ret = config_phydm_switch_channel_bw_8197f(dm, ch, pri_ch, bw);
-+	break;
-+#endif
-+
-+#if (RTL8821C_SUPPORT)
-+	case ODM_RTL8821C:
-+		ret = config_phydm_switch_channel_bw_8821c(dm, ch, pri_ch, bw);
-+	break;
-+#endif
-+
-+#if (RTL8195B_SUPPORT)
-+	case ODM_RTL8195B:
-+		ret = config_phydm_switch_channel_bw_8195b(dm, ch, pri_ch, bw);
-+	break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT)
-+	case ODM_RTL8192F:
-+		ret = config_phydm_switch_channel_bw_8192f(dm, ch, pri_ch, bw);
-+	break;
-+#endif
-+
-+#if (RTL8198F_SUPPORT)
-+	case ODM_RTL8198F:
-+		ret = config_phydm_switch_channel_bw_8198f(dm, ch, pri_ch, bw);
-+	break;
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	case ODM_RTL8822C:
-+		ret = config_phydm_switch_channel_bw_8822c(dm, ch, pri_ch, bw);
-+	break;
-+#endif
-+
-+#if (RTL8723F_SUPPORT)
-+	case ODM_RTL8723F:
-+		ret = config_phydm_switch_channel_bw_8723f(dm, ch, pri_ch, bw);
-+	break;
-+#endif
-+
-+#if (RTL8814B_SUPPORT)
-+	case ODM_RTL8814B:
-+		ret = config_phydm_switch_channel_bw_8814b(dm, ch, pri_ch, bw);
-+	break;
-+#endif
-+
-+#if (RTL8812F_SUPPORT)
-+	case ODM_RTL8812F:
-+		ret = config_phydm_switch_channel_bw_8812f(dm, ch, pri_ch, bw);
-+	break;
-+#endif
-+
-+#if (RTL8197G_SUPPORT)
-+	case ODM_RTL8197G:
-+		ret = config_phydm_switch_channel_bw_8197g(dm, ch, pri_ch, bw);
-+	break;
-+#endif
-+
-+#if (RTL8721D_SUPPORT)
-+	case ODM_RTL8721D:
-+		ret = config_phydm_switch_channel_bw_8721d(dm, ch, pri_ch, bw);
-+	break;
-+#endif
-+#if (RTL8710C_SUPPORT)
-+	case ODM_RTL8710C:
-+		ret = config_phydm_switch_channel_bw_8710c(dm, ch, pri_ch, bw);
-+	break;
-+#endif
-+
-+	default:
-+		break;
-+	}
-+	return ret;
-+}
-+
-+boolean
-+phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,
-+		   enum bb_path tx_path_ctrl)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean ret = false;
-+	boolean is_2tx = false;
-+
-+	if (tx_path_ctrl == BB_PATH_AB)
-+		is_2tx = true;
-+
-+	switch (dm->support_ic_type) {
-+	#if (RTL8822B_SUPPORT)
-+	case ODM_RTL8822B:
-+		ret = config_phydm_trx_mode_8822b(dm, tx_path, rx_path,
-+						  tx_path_ctrl);
-+		break;
-+	#endif
-+
-+	#if (RTL8197F_SUPPORT)
-+	case ODM_RTL8197F:
-+		ret = config_phydm_trx_mode_8197f(dm, tx_path, rx_path, is_2tx);
-+		break;
-+	#endif
-+
-+	#if (RTL8192F_SUPPORT)
-+	case ODM_RTL8192F:
-+		ret = config_phydm_trx_mode_8192f(dm, tx_path, rx_path,
-+						  tx_path_ctrl);
-+		break;
-+	#endif
-+
-+	#if (RTL8198F_SUPPORT)
-+	case ODM_RTL8198F:
-+		ret = config_phydm_trx_mode_8198f(dm, tx_path, rx_path, is_2tx);
-+		break;
-+	#endif
-+
-+	#if (RTL8814B_SUPPORT)
-+	case ODM_RTL8814B:
-+		ret = config_phydm_trx_mode_8814b(dm, tx_path, rx_path);
-+		break;
-+	#endif
-+
-+	#if (RTL8822C_SUPPORT)
-+	case ODM_RTL8822C:
-+		ret = config_phydm_trx_mode_8822c(dm, tx_path, rx_path,
-+						  tx_path_ctrl);
-+		break;
-+	#endif
-+
-+	#if (RTL8812F_SUPPORT)
-+	case ODM_RTL8812F:
-+		ret = config_phydm_trx_mode_8812f(dm, tx_path, rx_path, is_2tx);
-+		break;
-+	#endif
-+
-+	#if (RTL8197G_SUPPORT)
-+	case ODM_RTL8197G:
-+		ret = config_phydm_trx_mode_8197g(dm, tx_path, rx_path, is_2tx);
-+		break;
-+	#endif
-+
-+	#if (RTL8721D_SUPPORT)
-+	case ODM_RTL8721D:
-+		ret = config_phydm_trx_mode_8721d(dm, tx_path, rx_path, is_2tx);
-+		break;
-+	#endif
-+
-+	#if (RTL8710C_SUPPORT)
-+	case ODM_RTL8710C:
-+		ret = config_phydm_trx_mode_8710c(dm, tx_path, rx_path, is_2tx);
-+		break;
-+	#endif
-+	}
-+	return ret;
-+}
-+#endif
-+
-+#ifdef PHYDM_COMMON_API_NOT_SUPPORT
-+u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 read_back_data = INVALID_TXAGC_DATA;
-+	u32 reg_txagc;
-+	u32 reg_mask;
-+	/* This function is for 92E/88E etc... */
-+	/* @Input need to be HW rate index, not driver rate index!!!! */
-+
-+	/* @Error handling */
-+	if (path > RF_PATH_B || hw_rate > ODM_RATEMCS15) {
-+		PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: unsupported path (%d)\n",
-+			  __func__, path);
-+		return INVALID_TXAGC_DATA;
-+	}
-+
-+	if (path == RF_PATH_A) {
-+		switch (hw_rate) {
-+		case ODM_RATE1M:
-+			reg_txagc = R_0xe08;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATE2M:
-+			reg_txagc = R_0x86c;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATE5_5M:
-+			reg_txagc = R_0x86c;
-+			reg_mask = 0x007f0000;
-+			break;
-+		case ODM_RATE11M:
-+			reg_txagc = R_0x86c;
-+			reg_mask = 0x7f000000;
-+			break;
-+
-+		case ODM_RATE6M:
-+			reg_txagc = R_0xe00;
-+			reg_mask = 0x0000007f;
-+			break;
-+		case ODM_RATE9M:
-+			reg_txagc = R_0xe00;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATE12M:
-+			reg_txagc = R_0xe00;
-+			reg_mask = 0x007f0000;
-+			break;
-+		case ODM_RATE18M:
-+			reg_txagc = R_0xe00;
-+			reg_mask = 0x7f000000;
-+			break;
-+		case ODM_RATE24M:
-+			reg_txagc = R_0xe04;
-+			reg_mask = 0x0000007f;
-+			break;
-+		case ODM_RATE36M:
-+			reg_txagc = R_0xe04;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATE48M:
-+			reg_txagc = R_0xe04;
-+			reg_mask = 0x007f0000;
-+			break;
-+		case ODM_RATE54M:
-+			reg_txagc = R_0xe04;
-+			reg_mask = 0x7f000000;
-+			break;
-+
-+		case ODM_RATEMCS0:
-+			reg_txagc = R_0xe10;
-+			reg_mask = 0x0000007f;
-+			break;
-+		case ODM_RATEMCS1:
-+			reg_txagc = R_0xe10;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATEMCS2:
-+			reg_txagc = R_0xe10;
-+			reg_mask = 0x007f0000;
-+			break;
-+		case ODM_RATEMCS3:
-+			reg_txagc = R_0xe10;
-+			reg_mask = 0x7f000000;
-+			break;
-+		case ODM_RATEMCS4:
-+			reg_txagc = R_0xe14;
-+			reg_mask = 0x0000007f;
-+			break;
-+		case ODM_RATEMCS5:
-+			reg_txagc = R_0xe14;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATEMCS6:
-+			reg_txagc = R_0xe14;
-+			reg_mask = 0x007f0000;
-+			break;
-+		case ODM_RATEMCS7:
-+			reg_txagc = R_0xe14;
-+			reg_mask = 0x7f000000;
-+			break;
-+		case ODM_RATEMCS8:
-+			reg_txagc = R_0xe18;
-+			reg_mask = 0x0000007f;
-+			break;
-+		case ODM_RATEMCS9:
-+			reg_txagc = R_0xe18;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATEMCS10:
-+			reg_txagc = R_0xe18;
-+			reg_mask = 0x007f0000;
-+			break;
-+		case ODM_RATEMCS11:
-+			reg_txagc = R_0xe18;
-+			reg_mask = 0x7f000000;
-+			break;
-+		case ODM_RATEMCS12:
-+			reg_txagc = R_0xe1c;
-+			reg_mask = 0x0000007f;
-+			break;
-+		case ODM_RATEMCS13:
-+			reg_txagc = R_0xe1c;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATEMCS14:
-+			reg_txagc = R_0xe1c;
-+			reg_mask = 0x007f0000;
-+			break;
-+		case ODM_RATEMCS15:
-+			reg_txagc = R_0xe1c;
-+			reg_mask = 0x7f000000;
-+			break;
-+
-+		default:
-+			PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n");
-+			break;
-+		}
-+	} else if (path == RF_PATH_B) {
-+		switch (hw_rate) {
-+		case ODM_RATE1M:
-+			reg_txagc = R_0x838;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATE2M:
-+			reg_txagc = R_0x838;
-+			reg_mask = 0x007f0000;
-+			break;
-+		case ODM_RATE5_5M:
-+			reg_txagc = R_0x838;
-+			reg_mask = 0x7f000000;
-+			break;
-+		case ODM_RATE11M:
-+			reg_txagc = R_0x86c;
-+			reg_mask = 0x0000007f;
-+			break;
-+
-+		case ODM_RATE6M:
-+			reg_txagc = R_0x830;
-+			reg_mask = 0x0000007f;
-+			break;
-+		case ODM_RATE9M:
-+			reg_txagc = R_0x830;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATE12M:
-+			reg_txagc = R_0x830;
-+			reg_mask = 0x007f0000;
-+			break;
-+		case ODM_RATE18M:
-+			reg_txagc = R_0x830;
-+			reg_mask = 0x7f000000;
-+			break;
-+		case ODM_RATE24M:
-+			reg_txagc = R_0x834;
-+			reg_mask = 0x0000007f;
-+			break;
-+		case ODM_RATE36M:
-+			reg_txagc = R_0x834;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATE48M:
-+			reg_txagc = R_0x834;
-+			reg_mask = 0x007f0000;
-+			break;
-+		case ODM_RATE54M:
-+			reg_txagc = R_0x834;
-+			reg_mask = 0x7f000000;
-+			break;
-+
-+		case ODM_RATEMCS0:
-+			reg_txagc = R_0x83c;
-+			reg_mask = 0x0000007f;
-+			break;
-+		case ODM_RATEMCS1:
-+			reg_txagc = R_0x83c;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATEMCS2:
-+			reg_txagc = R_0x83c;
-+			reg_mask = 0x007f0000;
-+			break;
-+		case ODM_RATEMCS3:
-+			reg_txagc = R_0x83c;
-+			reg_mask = 0x7f000000;
-+			break;
-+		case ODM_RATEMCS4:
-+			reg_txagc = R_0x848;
-+			reg_mask = 0x0000007f;
-+			break;
-+		case ODM_RATEMCS5:
-+			reg_txagc = R_0x848;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATEMCS6:
-+			reg_txagc = R_0x848;
-+			reg_mask = 0x007f0000;
-+			break;
-+		case ODM_RATEMCS7:
-+			reg_txagc = R_0x848;
-+			reg_mask = 0x7f000000;
-+			break;
-+
-+		case ODM_RATEMCS8:
-+			reg_txagc = R_0x84c;
-+			reg_mask = 0x0000007f;
-+			break;
-+		case ODM_RATEMCS9:
-+			reg_txagc = R_0x84c;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATEMCS10:
-+			reg_txagc = R_0x84c;
-+			reg_mask = 0x007f0000;
-+			break;
-+		case ODM_RATEMCS11:
-+			reg_txagc = R_0x84c;
-+			reg_mask = 0x7f000000;
-+			break;
-+		case ODM_RATEMCS12:
-+			reg_txagc = R_0x868;
-+			reg_mask = 0x0000007f;
-+			break;
-+		case ODM_RATEMCS13:
-+			reg_txagc = R_0x868;
-+			reg_mask = 0x00007f00;
-+			break;
-+		case ODM_RATEMCS14:
-+			reg_txagc = R_0x868;
-+			reg_mask = 0x007f0000;
-+			break;
-+		case ODM_RATEMCS15:
-+			reg_txagc = R_0x868;
-+			reg_mask = 0x7f000000;
-+			break;
-+
-+		default:
-+			PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n");
-+			break;
-+		}
-+	} else {
-+		PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid RF path!!\n");
-+	}
-+	read_back_data = (u8)odm_get_bb_reg(dm, reg_txagc, reg_mask);
-+	PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: path-%d rate index 0x%x = 0x%x\n",
-+		  __func__, path, hw_rate, read_back_data);
-+	return read_back_data;
-+}
-+#endif
-+
-+#ifdef CONFIG_MCC_DM
-+#ifdef DYN_ANT_WEIGHTING_SUPPORT
-+void phydm_set_weighting_cmn(struct dm_struct *dm)
-+{
-+	PHYDM_DBG(dm, DBG_COMP_MCC, "%s\n", __func__);
-+	odm_set_bb_reg(dm, 0xc04, (BIT(18) | BIT(21)), 0x0);
-+	odm_set_bb_reg(dm, 0xe04, (BIT(18) | BIT(21)), 0x0);
-+}
-+
-+void phydm_set_weighting_mcc(u8 b_equal_weighting, void *dm_void, u8 port)
-+{
-+	/*u8 reg_8;*/
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
-+	u8	val_0x98e, val_0x98f, val_0x81b;
-+	u32 temp_reg;
-+
-+	PHYDM_DBG(dm, DBG_COMP_MCC, "ant_weighting_mcc, port = %d\n", port);
-+	if (b_equal_weighting) {
-+		temp_reg = odm_get_bb_reg(dm, 0x98c, 0x00ff0000);
-+		val_0x98e = (u8)(temp_reg >> 16) & 0xc0;
-+		temp_reg = odm_get_bb_reg(dm, 0x98c, 0xff000000);
-+		val_0x98f = (u8)(temp_reg >> 24) & 0x7f;
-+		temp_reg = odm_get_bb_reg(dm, 0x818, 0xff000000);
-+		val_0x81b = (u8)(temp_reg >> 24) & 0xfd;
-+		PHYDM_DBG(dm, DBG_COMP_MCC, "Equal weighting ,rssi_min = %d\n",
-+			  dm->rssi_min);
-+		/*equal weighting*/
-+	} else {
-+		val_0x98e = 0x44;
-+		val_0x98f = 0x43;
-+		temp_reg = odm_get_bb_reg(dm, 0x818, 0xff000000);
-+		val_0x81b = (u8)(temp_reg >> 24) | BIT(2);
-+		PHYDM_DBG(dm, DBG_COMP_MCC, "AGC weighting ,rssi_min = %d\n",
-+			  dm->rssi_min);
-+		/*fix sec_min_wgt = 1/2*/
-+	}
-+	mcc_dm->mcc_reg_id[2] = 0x2;
-+	mcc_dm->mcc_dm_reg[2] = 0x98e;
-+	mcc_dm->mcc_dm_val[2][port] = val_0x98e;
-+
-+	mcc_dm->mcc_reg_id[3] = 0x3;
-+	mcc_dm->mcc_dm_reg[3] = 0x98f;
-+	mcc_dm->mcc_dm_val[3][port] = val_0x98f;
-+
-+	mcc_dm->mcc_reg_id[4] = 0x4;
-+	mcc_dm->mcc_dm_reg[4] = 0x81b;
-+	mcc_dm->mcc_dm_val[4][port] = val_0x81b;
-+}
-+
-+void phydm_dyn_ant_dec_mcc(u8 port, u8 rssi_in, void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 rssi_l2h = 43, rssi_h2l = 37;
-+
-+	if (rssi_in == 0xff)
-+		phydm_set_weighting_mcc(FALSE, dm, port);
-+	else if (rssi_in >= rssi_l2h)
-+		phydm_set_weighting_mcc(TRUE, dm, port);
-+	else if (rssi_in <= rssi_h2l)
-+		phydm_set_weighting_mcc(FALSE, dm, port);
-+}
-+
-+void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
-+	u8	i;
-+
-+	phydm_set_weighting_cmn(dm);
-+	for (i = 0; i <= 1; i++)
-+		phydm_dyn_ant_dec_mcc(i, mcc_dm->mcc_rssi[i], dm);
-+}
-+#endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/
-+
-+void phydm_mcc_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
-+	u8	i;
-+
-+	/*PHYDM_DBG(dm, DBG_COMP_MCC, ("MCC init\n"));*/
-+	PHYDM_DBG(dm, DBG_COMP_MCC, "MCC init\n");
-+	for (i = 0; i < MCC_DM_REG_NUM; i++) {
-+		mcc_dm->mcc_reg_id[i] = 0xff;
-+		mcc_dm->mcc_dm_reg[i] = 0;
-+		mcc_dm->mcc_dm_val[i][0] = 0;
-+		mcc_dm->mcc_dm_val[i][1] = 0;
-+	}
-+	for (i = 0; i < NUM_STA; i++) {
-+		mcc_dm->sta_macid[0][i] = 0xff;
-+		mcc_dm->sta_macid[1][i] = 0xff;
-+	}
-+	/* Function init */
-+	dm->is_stop_dym_ant_weighting = 0;
-+}
-+
-+u8 phydm_check(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
-+	struct cmn_sta_info			*p_entry = NULL;
-+	u8	shift = 0;
-+	u8	i = 0;
-+	u8	j = 0;
-+	u8	rssi_min[2] = {0xff, 0xff};
-+	u8	sta_num = 8;
-+	u8 mcc_macid = 0;
-+
-+	for (i = 0; i <= 1; i++) {
-+		for (j = 0; j < sta_num; j++) {
-+			if (mcc_dm->sta_macid[i][j] != 0xff) {
-+				mcc_macid = mcc_dm->sta_macid[i][j];
-+				p_entry = dm->phydm_sta_info[mcc_macid];
-+				if (!p_entry) {
-+					PHYDM_DBG(dm, DBG_COMP_MCC,
-+						  "PEntry NULL(mac=%d)\n",
-+						  mcc_dm->sta_macid[i][j]);
-+					return _FAIL;
-+				}
-+				PHYDM_DBG(dm, DBG_COMP_MCC,
-+					  "undec_smoothed_pwdb=%d\n",
-+					  p_entry->rssi_stat.rssi);
-+				if (p_entry->rssi_stat.rssi < rssi_min[i])
-+					rssi_min[i] = p_entry->rssi_stat.rssi;
-+			}
-+		}
-+	}
-+	mcc_dm->mcc_rssi[0] = (u8)rssi_min[0];
-+	mcc_dm->mcc_rssi[1] = (u8)rssi_min[1];
-+	return _SUCCESS;
-+}
-+
-+void phydm_mcc_h2ccmd_rst(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
-+	u8 i;
-+	u8 regid;
-+	u8 h2c_mcc[H2C_MAX_LENGTH];
-+
-+	/* RST MCC */
-+	for (i = 0; i < H2C_MAX_LENGTH; i++)
-+		h2c_mcc[i] = 0xff;
-+	h2c_mcc[0] = 0x00;
-+	odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);
-+	PHYDM_DBG(dm, DBG_COMP_MCC, "MCC H2C RST\n");
-+}
-+
-+void phydm_mcc_h2ccmd(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
-+	u8 i;
-+	u8 regid;
-+	u8 h2c_mcc[H2C_MAX_LENGTH];
-+
-+	if (mcc_dm->mcc_rf_ch[0] == 0xff && mcc_dm->mcc_rf_ch[1] == 0xff) {
-+		PHYDM_DBG(dm, DBG_COMP_MCC, "MCC channel Error\n");
-+		return;
-+	}
-+	/* Set Channel number */
-+	for (i = 0; i < H2C_MAX_LENGTH; i++)
-+		h2c_mcc[i] = 0xff;
-+	h2c_mcc[0] = 0xe0;
-+	h2c_mcc[1] = (u8)(mcc_dm->mcc_rf_ch[0]);
-+	h2c_mcc[2] = (u8)(mcc_dm->mcc_rf_ch[0] >> 8);
-+	h2c_mcc[3] = (u8)(mcc_dm->mcc_rf_ch[1]);
-+	h2c_mcc[4] = (u8)(mcc_dm->mcc_rf_ch[1] >> 8);
-+	h2c_mcc[5] = 0xff;
-+	h2c_mcc[6] = 0xff;
-+	odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc);
-+	PHYDM_DBG(dm, DBG_COMP_MCC,
-+		  "MCC H2C SetCH: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
-+		  h2c_mcc[0], h2c_mcc[1], h2c_mcc[2], h2c_mcc[3],
-+		  h2c_mcc[4], h2c_mcc[5], h2c_mcc[6]);
-+
-+	/* Set Reg and value*/
-+	for (i = 0; i < H2C_MAX_LENGTH; i++)
-+		h2c_mcc[i] = 0xff;
-+
-+	for (i = 0; i < MCC_DM_REG_NUM; i++) {
-+		regid = mcc_dm->mcc_reg_id[i];
-+		if (regid != 0xff) {
-+			h2c_mcc[0] = 0xa0 | (regid & 0x1f);
-+			h2c_mcc[1] = (u8)(mcc_dm->mcc_dm_reg[i]);
-+			h2c_mcc[2] = (u8)(mcc_dm->mcc_dm_reg[i] >> 8);
-+			h2c_mcc[3] = mcc_dm->mcc_dm_val[i][0];
-+			h2c_mcc[4] = mcc_dm->mcc_dm_val[i][1];
-+			h2c_mcc[5] = 0xff;
-+			h2c_mcc[6] = 0xff;
-+			odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH,
-+					 h2c_mcc);
-+			PHYDM_DBG(dm, DBG_COMP_MCC,
-+				  "MCC H2C: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
-+				  h2c_mcc[0], h2c_mcc[1], h2c_mcc[2],
-+				  h2c_mcc[3], h2c_mcc[4],
-+				  h2c_mcc[5], h2c_mcc[6]);
-+		}
-+	}
-+}
-+
-+void phydm_mcc_ctrl(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+	PHYDM_DBG(dm, DBG_COMP_MCC, "MCC status: %x\n", mcc_dm->mcc_status);
-+	/*MCC stage no change*/
-+	if (mcc_dm->mcc_status == mcc_dm->mcc_pre_status)
-+		return;
-+	/*Not in MCC stage*/
-+	if (mcc_dm->mcc_status == 0) {
-+		/* Enable normal Ant-weighting */
-+		dm->is_stop_dym_ant_weighting = 0;
-+		/* Enable normal DIG */
-+		odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, 0x20);
-+	} else {
-+		/* Disable normal Ant-weighting */
-+		dm->is_stop_dym_ant_weighting = 1;
-+		/* Enable normal DIG */
-+		odm_pause_dig(dm, PHYDM_PAUSE_NO_SET, PHYDM_PAUSE_LEVEL_1,
-+			      0x20);
-+	}
-+	if (mcc_dm->mcc_status == 0 && mcc_dm->mcc_pre_status != 0)
-+		phydm_mcc_init(dm);
-+	mcc_dm->mcc_pre_status = mcc_dm->mcc_status;
-+	}
-+
-+void phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add,
-+		       u8 val0, u8 val1)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
-+
-+	mcc_dm->mcc_reg_id[regid] = regid;
-+	mcc_dm->mcc_dm_reg[regid] = reg_add;
-+	mcc_dm->mcc_dm_val[regid][0] = val0;
-+	mcc_dm->mcc_dm_val[regid][1] = val1;
-+}
-+
-+void phydm_mcc_switch(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
-+	s8 ret;
-+
-+	phydm_mcc_ctrl(dm);
-+	if (mcc_dm->mcc_status == 0) {/*Not in MCC stage*/
-+		phydm_mcc_h2ccmd_rst(dm);
-+		return;
-+	}
-+	PHYDM_DBG(dm, DBG_COMP_MCC, "MCC switch\n");
-+	ret = phydm_check(dm);
-+	if (ret == _FAIL) {
-+		PHYDM_DBG(dm, DBG_COMP_MCC, "MCC check fail\n");
-+		return;
-+	}
-+	/* Set IGI*/
-+	phydm_mcc_igi_cal(dm);
-+
-+	/* Set Antenna Gain*/
-+#if (RTL8822B_SUPPORT == 1)
-+	phydm_dynamic_ant_weighting_mcc_8822b(dm);
-+#endif
-+	/* Set H2C Cmd*/
-+	phydm_mcc_h2ccmd(dm);
-+}
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void phydm_normal_driver_rx_sniffer(
-+	struct dm_struct *dm,
-+	u8 *desc,
-+	PRT_RFD_STATUS rt_rfd_status,
-+	u8 *drv_info,
-+	u8 phy_status)
-+{
-+#if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING))
-+	u32 *msg;
-+	u16 seq_num;
-+
-+	if (rt_rfd_status->packet_report_type != NORMAL_RX)
-+		return;
-+
-+	if (!dm->is_linked) {
-+		if (rt_rfd_status->is_hw_error)
-+			return;
-+	}
-+
-+	if (phy_status == true) {
-+		if (dm->rx_pkt_type == type_block_ack ||
-+		    dm->rx_pkt_type == type_rts || dm->rx_pkt_type == type_cts)
-+			seq_num = 0;
-+		else
-+			seq_num = rt_rfd_status->seq_num;
-+
-+		PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
-+			    "%04d , %01s, rate=0x%02x, L=%04d , %s , %s",
-+			    seq_num,
-+			    /*rt_rfd_status->mac_id,*/
-+			    (rt_rfd_status->is_crc ? "C" :
-+			    rt_rfd_status->is_ampdu ? "A" : "_"),
-+			    rt_rfd_status->data_rate,
-+			    rt_rfd_status->length,
-+			    ((rt_rfd_status->band_width == 0) ? "20M" :
-+			    ((rt_rfd_status->band_width == 1) ? "40M" : "80M")),
-+			    (rt_rfd_status->is_ldpc ? "LDP" : "BCC"));
-+
-+		if (dm->rx_pkt_type == type_asoc_req)
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_REQ");
-+		else if (dm->rx_pkt_type == type_asoc_rsp)
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_RSP");
-+		else if (dm->rx_pkt_type == type_probe_req)
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_REQ");
-+		else if (dm->rx_pkt_type == type_probe_rsp)
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_RSP");
-+		else if (dm->rx_pkt_type == type_deauth)
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "DEAUTH");
-+		else if (dm->rx_pkt_type == type_beacon)
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BEACON");
-+		else if (dm->rx_pkt_type == type_block_ack_req)
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BA_REQ");
-+		else if (dm->rx_pkt_type == type_rts)
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__RTS_");
-+		else if (dm->rx_pkt_type == type_cts)
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__CTS_");
-+		else if (dm->rx_pkt_type == type_ack)
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__ACK_");
-+		else if (dm->rx_pkt_type == type_block_ack)
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__BA__");
-+		else if (dm->rx_pkt_type == type_data)
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "_DATA_");
-+		else if (dm->rx_pkt_type == type_data_ack)
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "Data_Ack");
-+		else if (dm->rx_pkt_type == type_qos_data)
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "QoS_Data");
-+		else
-+			PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [0x%x]",
-+				    dm->rx_pkt_type);
-+
-+		PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [RSSI=%d,%d,%d,%d ]",
-+			    dm->rssi_a,
-+			    dm->rssi_b,
-+			    dm->rssi_c,
-+			    dm->rssi_d);
-+
-+		msg = (u32 *)drv_info;
-+
-+		PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
-+			    " , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n",
-+			    msg[6], msg[5], msg[4], msg[3],
-+			    msg[2], msg[1], msg[1]);
-+	} else {
-+		PHYDM_DBG_F(dm, ODM_COMP_SNIFFER,
-+			    "%04d , %01s, rate=0x%02x, L=%04d , %s , %s\n",
-+			    rt_rfd_status->seq_num,
-+			    /*rt_rfd_status->mac_id,*/
-+			    (rt_rfd_status->is_crc ? "C" :
-+			    (rt_rfd_status->is_ampdu) ? "A" : "_"),
-+			    rt_rfd_status->data_rate,
-+			    rt_rfd_status->length,
-+			    ((rt_rfd_status->band_width == 0) ? "20M" :
-+			    ((rt_rfd_status->band_width == 1) ? "40M" : "80M")),
-+			    (rt_rfd_status->is_ldpc ? "LDP" : "BCC"));
-+	}
-+
-+#endif
-+}
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_api.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_api.h
-new file mode 100644
-index 000000000000..a27b72514b59
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_api.h
-@@ -0,0 +1,228 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_API_H__
-+#define __PHYDM_API_H__
-+
-+/* 2019.10.22 Add get/shift rxagc API for 8822C*/
-+#define PHYDM_API_VERSION "2.3"
-+
-+/* @1 ============================================================
-+ * 1  Definition
-+ * 1 ============================================================
-+ */
-+#define N_IC_TX_OFFEST_5_BIT (ODM_RTL8188E | ODM_RTL8192E)
-+
-+#define N_IC_TX_OFFEST_6_BIT (ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B |\
-+			ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8195A |\
-+			ODM_RTL8188F)
-+
-+#define N_IC_TX_OFFEST_7_BIT (ODM_RTL8721D | ODM_RTL8710C)
-+
-+#define CN_CNT_MAX 10 /*@max condition number threshold*/
-+
-+#define FUNC_ENABLE 1
-+#define FUNC_DISABLE 2
-+
-+/*@NBI API------------------------------------*/
-+#define NBI_128TONE 27 /*register table size*/
-+#define NBI_256TONE 59 /*register table size*/
-+
-+#define NUM_START_CH_80M 7
-+#define NUM_START_CH_40M 14
-+
-+#define CH_OFFSET_40M 2
-+#define CH_OFFSET_80M 6
-+
-+#define FFT_128_TYPE 1
-+#define FFT_256_TYPE 2
-+
-+#define FREQ_POSITIVE 1
-+#define FREQ_NEGATIVE 2
-+/*@------------------------------------------------*/
-+
-+enum phystat_rpt {
-+	PHY_PWDB = 0,
-+	PHY_EVM = 1,
-+	PHY_CFO = 2,
-+	PHY_RXSNR = 3,
-+	PHY_LGAIN = 4,
-+	PHY_HT_AAGC_GAIN = 5,
-+};
-+
-+#ifndef PHYDM_COMMON_API_SUPPORT
-+#define INVALID_RF_DATA 0xffffffff
-+#define INVALID_TXAGC_DATA 0xff
-+#endif
-+
-+/* @1 ============================================================
-+ * 1  structure
-+ * 1 ============================================================
-+ */
-+
-+struct phydm_api_stuc {
-+	u32 rxiqc_reg1; /*N-mode: for pathA REG0xc14*/
-+	u32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/
-+	u8 tx_queue_bitmap; /*REG0x520[23:16]*/
-+	u8 ccktx_path;
-+	u8 pri_ch_idx;
-+};
-+
-+/* @1 ============================================================
-+ * 1  enumeration
-+ * 1 ============================================================
-+ */
-+
-+/* @1 ============================================================
-+ * 1  function prototype
-+ * 1 ============================================================
-+ */
-+enum channel_width phydm_rxsc_2_bw(void *dm_void, u8 rxsc);
-+
-+void phydm_reset_bb_hw_cnt(void *dm_void);
-+
-+void phydm_dynamic_ant_weighting(void *dm_void);
-+
-+#ifdef DYN_ANT_WEIGHTING_SUPPORT
-+void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,
-+			  char *output, u32 *_out_len);
-+#endif
-+
-+void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path);
-+
-+void phydm_config_ofdm_rx_path(void *dm_void, enum bb_path path);
-+
-+void phydm_config_cck_rx_path(void *dm_void, enum bb_path path);
-+
-+void phydm_config_cck_rx_antenna_init(void *dm_void);
-+
-+void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,
-+			   char *output, u32 *_out_len);
-+
-+void phydm_config_ofdm_tx_path(void *dm_void, enum bb_path path);
-+
-+void phydm_config_cck_tx_path(void *dm_void, enum bb_path path);
-+
-+void phydm_tx_2path(void *dm_void);
-+
-+void phydm_stop_3_wire(void *dm_void, u8 set_type);
-+
-+u8 phydm_stop_ic_trx(void *dm_void, u8 set_type);
-+
-+void phydm_dis_cck_trx(void *dm_void, u8 set_type);
-+
-+void phydm_bw_fixed_enable(void *dm_void, u8 enable);
-+
-+void phydm_bw_fixed_setting(void *dm_void);
-+
-+void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch);
-+
-+void phydm_nbi_enable(void *dm_void, u32 enable);
-+
-+u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
-+			  u32 sec_ch);
-+
-+u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
-+		     u32 sec_ch);
-+
-+void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used,
-+		     char *output, u32 *_out_len);
-+
-+void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used,
-+		     char *output, u32 *_out_len);
-+
-+void phydm_stop_ck320(void *dm_void, u8 enable);
-+
-+boolean
-+phydm_set_bb_txagc_offset(void *dm_void, s8 power_offset, u8 add_half_db);
-+
-+boolean phydm_spur_case_mapping(void *dm_void);
-+
-+enum odm_rf_band phydm_ch_to_rf_band(void *dm_void, u8 central_ch);
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+u32 phydm_rf_psd_jgr3(void *dm_void, u8 path, u32 tone_idx);
-+
-+u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,
-+			       u32 f_intf, u32 sec_ch, u8 wgt);
-+
-+void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
-+			     u8 wgt);
-+
-+u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
-+			  u32 sec_ch, u8 path);
-+
-+void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
-+			    u8 path);
-+
-+void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path);
-+
-+u8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info,
-+			  enum rf_path ant_path);
-+void phydm_user_position_for_sniffer(void *dm_void, u8 user_position);
-+
-+#endif
-+
-+#ifdef PHYDM_COMMON_API_SUPPORT
-+void phydm_reset_txagc(void *dm_void);
-+
-+boolean
-+phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
-+		      boolean is_positive);
-+boolean
-+phydm_api_set_txagc(void *dm_void, u32 power_index, enum rf_path path,
-+		    u8 hw_rate, boolean is_single_rate);
-+
-+u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate);
-+
-+#if (RTL8822C_SUPPORT)
-+void phydm_shift_rxagc_table(void *dm_void, boolean shift_up, u8 shift);
-+#endif
-+
-+boolean
-+phydm_api_switch_bw_channel(void *dm_void, u8 central_ch, u8 primary_ch_idx,
-+			    enum channel_width bandwidth);
-+
-+boolean
-+phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,
-+		   enum bb_path tx_path_ctrl);
-+
-+#endif
-+
-+#ifdef PHYDM_COMMON_API_NOT_SUPPORT
-+u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate);
-+#endif
-+
-+#ifdef CONFIG_MCC_DM
-+#ifdef DYN_ANT_WEIGHTING_SUPPORT
-+void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void);
-+#endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/
-+void phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add,
-+		       u8 val0,	u8 val1);
-+u8 phydm_check(void *dm_void);
-+void phydm_mcc_init(void *dm_void);
-+void phydm_mcc_switch(void *dm_void);
-+#endif /*#ifdef CONFIG_MCC_DM*/
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_auto_dbg.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_auto_dbg.c
-new file mode 100644
-index 000000000000..203764d7c4ec
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_auto_dbg.c
-@@ -0,0 +1,725 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef PHYDM_AUTO_DEGBUG
-+
-+void phydm_check_hang_reset(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
-+
-+	atd_t->dbg_step = 0;
-+	atd_t->auto_dbg_type = AUTO_DBG_STOP;
-+	phydm_pause_dm_watchdog(dm, PHYDM_RESUME);
-+	dm->debug_components &= (~ODM_COMP_API);
-+}
-+
-+void phydm_check_hang_init(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
-+
-+	atd_t->dbg_step = 0;
-+	atd_t->auto_dbg_type = AUTO_DBG_STOP;
-+	phydm_pause_dm_watchdog(dm, PHYDM_RESUME);
-+}
-+
-+#if (ODM_IC_11N_SERIES_SUPPORT == 1)
-+void phydm_auto_check_hang_engine_n(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
-+	struct n_dbgport_803 dbgport_803 = {0};
-+	u32 value32_tmp = 0, value32_tmp_2 = 0;
-+	u8 i;
-+	u32 curr_dbg_port_val[DBGPORT_CHK_NUM] = {0, 0, 0, 0, 0, 0};
-+	u16 curr_ofdm_t_cnt;
-+	u16 curr_ofdm_r_cnt;
-+	u16 curr_cck_t_cnt;
-+	u16 curr_cck_r_cnt;
-+	u16 curr_ofdm_crc_error_cnt;
-+	u16 curr_cck_crc_error_cnt;
-+	u16 diff_ofdm_t_cnt;
-+	u16 diff_ofdm_r_cnt;
-+	u16 diff_cck_t_cnt;
-+	u16 diff_cck_r_cnt;
-+	u16 diff_ofdm_crc_error_cnt;
-+	u16 diff_cck_crc_error_cnt;
-+	u8 rf_mode;
-+
-+	if (atd_t->auto_dbg_type == AUTO_DBG_STOP)
-+		return;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		phydm_check_hang_reset(dm);
-+		return;
-+	}
-+
-+	if (atd_t->dbg_step == 0) {
-+		pr_debug("dbg_step=0\n\n");
-+
-+		/*Reset all packet counter*/
-+		odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
-+		odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
-+
-+	} else if (atd_t->dbg_step == 1) {
-+		pr_debug("dbg_step=1\n\n");
-+
-+		/*Check packet counter Register*/
-+		atd_t->ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD);
-+		atd_t->ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD);
-+		atd_t->ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94,
-+								MASKHWORD);
-+
-+		atd_t->cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD);
-+		atd_t->cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD);
-+		atd_t->cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84,
-+							       0x3fff);
-+
-+		/*Check Debug Port*/
-+		for (i = 0; i < DBGPORT_CHK_NUM; i++) {
-+			if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3,
-+						  (u32)atd_t->dbg_port_table[i])
-+						  ) {
-+				atd_t->dbg_port_val[i] =
-+					phydm_get_bb_dbg_port_val(dm);
-+				phydm_release_bb_dbg_port(dm);
-+			}
-+		}
-+
-+	} else if (atd_t->dbg_step == 2) {
-+		pr_debug("dbg_step=2\n\n");
-+
-+		/*Check packet counter Register*/
-+		curr_ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD);
-+		curr_ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD);
-+		curr_ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94,
-+							      MASKHWORD);
-+
-+		curr_cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD);
-+		curr_cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD);
-+		curr_cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84,
-+							     0x3fff);
-+
-+		/*Check Debug Port*/
-+		for (i = 0; i < DBGPORT_CHK_NUM; i++) {
-+			if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3,
-+						  (u32)atd_t->dbg_port_table[i])
-+						  ) {
-+				curr_dbg_port_val[i] =
-+					phydm_get_bb_dbg_port_val(dm);
-+				phydm_release_bb_dbg_port(dm);
-+			}
-+		}
-+
-+		/*=== Make check hang decision ===============================*/
-+		pr_debug("Check Hang Decision\n\n");
-+
-+		/* ----- Check RF Register -----------------------------------*/
-+		for (i = 0; i < dm->num_rf_path; i++) {
-+			rf_mode = (u8)odm_get_rf_reg(dm, i, RF_0x0, 0xf0000);
-+			pr_debug("RF0x0[%d] = 0x%x\n", i, rf_mode);
-+			if (rf_mode > 3) {
-+				pr_debug("Incorrect RF mode\n");
-+				pr_debug("ReasonCode:RHN-1\n");
-+			}
-+		}
-+		value32_tmp = odm_get_rf_reg(dm, 0, RF_0xb0, 0xf0000);
-+		if (dm->support_ic_type == ODM_RTL8188E) {
-+			if (value32_tmp != 0xff8c8) {
-+				pr_debug("ReasonCode:RHN-3\n");
-+			}
-+		}
-+		/* ----- Check BB Register ----------------------------------*/
-+		/*BB mode table*/
-+		value32_tmp = odm_get_bb_reg(dm, R_0x824, 0xe);
-+		value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0xe);
-+		pr_debug("BB TX mode table {A, B}= {%d, %d}\n",
-+			 value32_tmp, value32_tmp_2);
-+
-+		if (value32_tmp > 3 || value32_tmp_2 > 3) {
-+			pr_debug("ReasonCode:RHN-2\n");
-+		}
-+
-+		value32_tmp = odm_get_bb_reg(dm, R_0x824, 0x700000);
-+		value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0x700000);
-+		pr_debug("BB RX mode table {A, B}= {%d, %d}\n", value32_tmp,
-+			 value32_tmp_2);
-+
-+		if (value32_tmp > 3 || value32_tmp_2 > 3) {
-+			pr_debug("ReasonCode:RHN-2\n");
-+		}
-+
-+		/*BB HW Block*/
-+		value32_tmp = odm_get_bb_reg(dm, R_0x800, MASKDWORD);
-+
-+		if (!(value32_tmp & BIT(24))) {
-+			pr_debug("Reg0x800[24] = 0, CCK BLK is disabled\n");
-+			pr_debug("ReasonCode: THN-3\n");
-+		}
-+
-+		if (!(value32_tmp & BIT(25))) {
-+			pr_debug("Reg0x800[24] = 0, OFDM BLK is disabled\n");
-+			pr_debug("ReasonCode:THN-3\n");
-+		}
-+
-+		/*BB Continue TX*/
-+		value32_tmp = odm_get_bb_reg(dm, R_0xd00, 0x70000000);
-+		pr_debug("Continue TX=%d\n", value32_tmp);
-+		if (value32_tmp != 0) {
-+			pr_debug("ReasonCode: THN-4\n");
-+		}
-+
-+		/* ----- Check Packet Counter --------------------------------*/
-+		diff_ofdm_t_cnt = curr_ofdm_t_cnt - atd_t->ofdm_t_cnt;
-+		diff_ofdm_r_cnt = curr_ofdm_r_cnt - atd_t->ofdm_r_cnt;
-+		diff_ofdm_crc_error_cnt = curr_ofdm_crc_error_cnt -
-+					  atd_t->ofdm_crc_error_cnt;
-+
-+		diff_cck_t_cnt = curr_cck_t_cnt - atd_t->cck_t_cnt;
-+		diff_cck_r_cnt = curr_cck_r_cnt - atd_t->cck_r_cnt;
-+		diff_cck_crc_error_cnt = curr_cck_crc_error_cnt -
-+					 atd_t->cck_crc_error_cnt;
-+
-+		pr_debug("OFDM[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
-+			 atd_t->ofdm_t_cnt, atd_t->ofdm_r_cnt,
-+			 atd_t->ofdm_crc_error_cnt);
-+		pr_debug("OFDM[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
-+			 curr_ofdm_t_cnt, curr_ofdm_r_cnt,
-+			 curr_ofdm_crc_error_cnt);
-+		pr_debug("OFDM_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
-+			 diff_ofdm_t_cnt, diff_ofdm_r_cnt,
-+			 diff_ofdm_crc_error_cnt);
-+
-+		pr_debug("CCK[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
-+			 atd_t->cck_t_cnt, atd_t->cck_r_cnt,
-+			 atd_t->cck_crc_error_cnt);
-+		pr_debug("CCK[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
-+			 curr_cck_t_cnt, curr_cck_r_cnt,
-+			 curr_cck_crc_error_cnt);
-+		pr_debug("CCK_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
-+			 diff_cck_t_cnt, diff_cck_r_cnt,
-+			 diff_cck_crc_error_cnt);
-+
-+		/* ----- Check Dbg Port --------------------------------*/
-+
-+		for (i = 0; i < DBGPORT_CHK_NUM; i++) {
-+			pr_debug("Dbg_port=((0x%x))\n",
-+				 atd_t->dbg_port_table[i]);
-+			pr_debug("Val{pre, curr}={0x%x, 0x%x}\n",
-+				 atd_t->dbg_port_val[i], curr_dbg_port_val[i]);
-+
-+			if (atd_t->dbg_port_table[i] == 0) {
-+				if (atd_t->dbg_port_val[i] ==
-+				    curr_dbg_port_val[i]) {
-+					pr_debug("BB state hang\n");
-+					pr_debug("ReasonCode:\n");
-+				}
-+
-+			} else if (atd_t->dbg_port_table[i] == 0x803) {
-+				if (atd_t->dbg_port_val[i] ==
-+				    curr_dbg_port_val[i]) {
-+					/* dbgport_803 =  */
-+					/* (struct n_dbgport_803 )   */
-+					/* (atd_t->dbg_port_val[i]); */
-+					odm_move_memory(dm, &dbgport_803,
-+							&atd_t->dbg_port_val[i],
-+							sizeof(struct n_dbgport_803));
-+					pr_debug("RSTB{BB, GLB, OFDM}={%d, %d,%d}\n",
-+						 dbgport_803.bb_rst_b,
-+						 dbgport_803.glb_rst_b,
-+						 dbgport_803.ofdm_rst_b);
-+					pr_debug("{ofdm_tx_en, cck_tx_en, phy_tx_on}={%d, %d, %d}\n",
-+						 dbgport_803.ofdm_tx_en,
-+						 dbgport_803.cck_tx_en,
-+						 dbgport_803.phy_tx_on);
-+					pr_debug("CCA_PP{OFDM, CCK}={%d, %d}\n",
-+						 dbgport_803.ofdm_cca_pp,
-+						 dbgport_803.cck_cca_pp);
-+
-+					if (dbgport_803.phy_tx_on)
-+						pr_debug("Maybe TX Hang\n");
-+					else if (dbgport_803.ofdm_cca_pp ||
-+						 dbgport_803.cck_cca_pp)
-+						pr_debug("Maybe RX Hang\n");
-+				}
-+
-+			} else if (atd_t->dbg_port_table[i] == 0x208) {
-+				if ((atd_t->dbg_port_val[i] & BIT(30)) &&
-+				    (curr_dbg_port_val[i] & BIT(30))) {
-+					pr_debug("EDCCA Pause TX\n");
-+					pr_debug("ReasonCode: THN-2\n");
-+				}
-+
-+			} else if (atd_t->dbg_port_table[i] == 0xab0) {
-+				/* atd_t->dbg_port_val[i] & 0xffffff == 0 */
-+				/* curr_dbg_port_val[i] & 0xffffff == 0 */
-+				if (((atd_t->dbg_port_val[i] &
-+				      MASK24BITS) == 0) ||
-+				    ((curr_dbg_port_val[i] &
-+				      MASK24BITS) == 0)) {
-+					pr_debug("Wrong L-SIG formate\n");
-+					pr_debug("ReasonCode: THN-1\n");
-+				}
-+			}
-+		}
-+
-+		phydm_check_hang_reset(dm);
-+	}
-+
-+	atd_t->dbg_step++;
-+}
-+
-+void phydm_bb_auto_check_hang_start_n(
-+	void *dm_void,
-+	u32 *_used,
-+	char *output,
-+	u32 *_out_len)
-+{
-+	u32 value32 = 0;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-+		return;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "PHYDM auto check hang (N-series) is started, Please check the system log\n");
-+
-+	dm->debug_components |= ODM_COMP_API;
-+	atd_t->auto_dbg_type = AUTO_DBG_CHECK_HANG;
-+	atd_t->dbg_step = 0;
-+
-+	phydm_pause_dm_watchdog(dm, PHYDM_PAUSE);
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_dbg_port_dump_n(void *dm_void, u32 *_used, char *output,
-+			   u32 *_out_len)
-+{
-+	u32 value32 = 0;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-+		return;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "not support now\n");
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#endif
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
-+void phydm_dbg_port_dump_ac(void *dm_void, u32 *_used, char *output,
-+			    u32 *_out_len)
-+{
-+	u32 value32 = 0;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES)
-+		return;
-+
-+	value32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", value32);
-+
-+	if (dm->support_ic_type & ODM_RTL8822B)
-+		odm_set_bb_reg(dm, R_0x198c, BIT(2) | BIT(1) | BIT(0), 7);
-+
-+	/* dbg_port = basic state machine */
-+	{
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "basic state machine", value32);
-+	}
-+
-+	/* dbg_port = state machine */
-+	{
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "state machine", value32);
-+	}
-+
-+	/* dbg_port = CCA-related*/
-+	{
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "CCA-related", value32);
-+	}
-+
-+	/* dbg_port = edcca/rxd*/
-+	{
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "edcca/rxd", value32);
-+	}
-+
-+	/* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/
-+	{
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x",
-+			 "rx_state/mux_state/ADC_MASK_OFDM", value32);
-+	}
-+
-+	/* dbg_port = bf-related*/
-+	{
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "bf-related", value32);
-+	}
-+
-+	/* dbg_port = bf-related*/
-+	{
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "bf-related", value32);
-+	}
-+
-+	/* dbg_port = txon/rxd*/
-+	{
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "txon/rxd", value32);
-+	}
-+
-+	/* dbg_port = l_rate/l_length*/
-+	{
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "l_rate/l_length", value32);
-+	}
-+
-+	/* dbg_port = rxd/rxd_hit*/
-+	{
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "rxd/rxd_hit", value32);
-+	}
-+
-+	/* dbg_port = dis_cca*/
-+	{
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "dis_cca", value32);
-+	}
-+
-+	/* dbg_port = tx*/
-+	{
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "tx", value32);
-+	}
-+
-+	/* dbg_port = rx plcp*/
-+	{
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "rx plcp", value32);
-+
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "rx plcp", value32);
-+
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "rx plcp", value32);
-+
-+		odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3);
-+		value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "0x8fc", value32);
-+
-+		value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = 0x%x", "rx plcp", value32);
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+#endif
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+void phydm_dbg_port_dump_jgr3(void *dm_void, u32 *_used, char *output,
-+			      u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	/*u32 dbg_port_idx_all[3] = {0x000, 0x001, 0x002};*/
-+	u32 val = 0;
-+	u32 dbg_port_idx = 0;
-+	u32 i = 0;
-+
-+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
-+		return;
-+
-+	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+		      "%-17s = %s\n", "DbgPort index", "Value");
-+
-+#if 0
-+	/*0x000/0x001/0x002*/
-+	for (i = 0; i < 3; i++) {
-+		dbg_port_idx = dbg_port_idx_all[i];
-+		if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) {
-+			val = phydm_get_bb_dbg_port_val(dm);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "0x%-15x = 0x%x\n", dbg_port_idx, val);
-+			phydm_release_bb_dbg_port(dm);
-+		}
-+	}
-+#endif
-+	for (dbg_port_idx = 0x0; dbg_port_idx <= 0xfff; dbg_port_idx++) {
-+		if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) {
-+			val = phydm_get_bb_dbg_port_val(dm);
-+			PDM_VAST_SNPF(out_len, used, output + used,
-+				      out_len - used,
-+				      "0x%-15x = 0x%x\n", dbg_port_idx, val);
-+			phydm_release_bb_dbg_port(dm);
-+		}
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+#endif
-+
-+void phydm_dbg_port_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+		      "------ BB debug port start ------\n");
-+
-+	switch (dm->ic_ip_series) {
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	case PHYDM_IC_JGR3:
-+		phydm_dbg_port_dump_jgr3(dm, &used, output, &out_len);
-+		break;
-+	#endif
-+
-+	#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
-+	case PHYDM_IC_AC:
-+		phydm_dbg_port_dump_ac(dm, &used, output, &out_len);
-+		break;
-+	#endif
-+
-+	#if (ODM_IC_11N_SERIES_SUPPORT == 1)
-+	case PHYDM_IC_N:
-+		phydm_dbg_port_dump_n(dm, &used, output, &out_len);
-+		break;
-+	#endif
-+
-+	default:
-+		break;
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_auto_dbg_console(
-+	void *dm_void,
-+	char input[][16],
-+	u32 *_used,
-+	char *output,
-+	u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "hang: {1} {1:Show DbgPort, 2:Auto check hang}\n");
-+		return;
-+	} else if (var1[0] == 1) {
-+		PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
-+		if (var1[1] == 1) {
-+			phydm_dbg_port_dump(dm, &used, output, &out_len);
-+		} else if (var1[1] == 2) {
-+			if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used, "Not support\n");
-+			} else {
-+				#if (ODM_IC_11N_SERIES_SUPPORT == 1)
-+				phydm_bb_auto_check_hang_start_n(dm, &used,
-+								 output,
-+								 &out_len);
-+				#else
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used, "Not support\n");
-+				#endif
-+			}
-+		}
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_auto_dbg_engine(void *dm_void)
-+{
-+	u32 value32 = 0;
-+
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
-+
-+	if (atd_t->auto_dbg_type == AUTO_DBG_STOP)
-+		return;
-+
-+	pr_debug("%s ======>\n", __func__);
-+
-+	if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_HANG) {
-+		if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+			pr_debug("Not Support\n");
-+		} else {
-+			#if (ODM_IC_11N_SERIES_SUPPORT == 1)
-+			phydm_auto_check_hang_engine_n(dm);
-+			#else
-+			pr_debug("Not Support\n");
-+			#endif
-+		}
-+
-+	} else if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_RA) {
-+		pr_debug("Not Support\n");
-+	}
-+}
-+
-+void phydm_auto_dbg_engine_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
-+	u16 dbg_port_table[DBGPORT_CHK_NUM] = {0x0, 0x803, 0x208, 0xab0,
-+					       0xab1, 0xab2};
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
-+
-+	odm_move_memory(dm, &atd_t->dbg_port_table[0],
-+			&dbg_port_table[0], (DBGPORT_CHK_NUM * 2));
-+
-+	phydm_check_hang_init(dm);
-+}
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_auto_dbg.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_auto_dbg.h
-new file mode 100644
-index 000000000000..78bde627f83c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_auto_dbg.h
-@@ -0,0 +1,115 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_AUTO_DBG_H__
-+#define __PHYDM_AUTO_DBG_H__
-+
-+#define AUTO_DBG_VERSION "1.0" /* @2017.05.015  Dino, Add phydm_auto_dbg.h*/
-+
-+/* @1 ============================================================
-+ * 1  Definition
-+ * 1 ============================================================
-+ */
-+
-+#define AUTO_CHK_HANG_STEP_MAX 3
-+#define DBGPORT_CHK_NUM 6
-+
-+#ifdef PHYDM_AUTO_DEGBUG
-+
-+/* @1 ============================================================
-+ * 1  enumeration
-+ * 1 ============================================================
-+ */
-+
-+enum auto_dbg_type_e {
-+	AUTO_DBG_STOP		= 0,
-+	AUTO_DBG_CHECK_HANG	= 1,
-+	AUTO_DBG_CHECK_RA	= 2,
-+	AUTO_DBG_CHECK_DIG	= 3
-+};
-+
-+/* @1 ============================================================
-+ * 1  structure
-+ * 1 ============================================================
-+ */
-+
-+struct n_dbgport_803 {
-+	/*@BYTE 3*/
-+	u8 bb_rst_b : 1;
-+	u8 glb_rst_b : 1;
-+	u8 zero_1bit_1 : 1;
-+	u8 ofdm_rst_b : 1;
-+	u8 cck_txpe : 1;
-+	u8 ofdm_txpe : 1;
-+	u8 phy_tx_on : 1;
-+	u8 tdrdy : 1;
-+	/*@BYTE 2*/
-+	u8 txd : 8;
-+	/*@BYTE 1*/
-+	u8 cck_cca_pp : 1;
-+	u8 ofdm_cca_pp : 1;
-+	u8 rx_rst : 1;
-+	u8 rdrdy : 1;
-+	u8 rxd_7_4 : 4;
-+	/*@BYTE 0*/
-+	u8 rxd_3_0 : 4;
-+	u8 ofdm_tx_en : 1;
-+	u8 cck_tx_en : 1;
-+	u8 zero_1bit_2 : 1;
-+	u8 clk_80m : 1;
-+};
-+
-+struct phydm_auto_dbg_struct {
-+	enum auto_dbg_type_e auto_dbg_type;
-+	u8 dbg_step;
-+	u16 dbg_port_table[DBGPORT_CHK_NUM];
-+	u32 dbg_port_val[DBGPORT_CHK_NUM];
-+	u16 ofdm_t_cnt;
-+	u16 ofdm_r_cnt;
-+	u16 cck_t_cnt;
-+	u16 cck_r_cnt;
-+	u16 ofdm_crc_error_cnt;
-+	u16 cck_crc_error_cnt;
-+};
-+
-+/* @1 ============================================================
-+ * 1  function prototype
-+ * 1 ============================================================
-+ */
-+
-+void phydm_dbg_port_dump(void *dm_void, u32 *used, char *output, u32 *out_len);
-+
-+void phydm_auto_dbg_console(
-+	void *dm_void,
-+	char input[][16],
-+	u32 *_used,
-+	char *output,
-+	u32 *_out_len);
-+
-+void phydm_auto_dbg_engine(void *dm_void);
-+
-+void phydm_auto_dbg_engine_init(void *dm_void);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_beamforming.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_beamforming.c
-new file mode 100644
-index 000000000000..1c055c8b9fb8
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_beamforming.c
-@@ -0,0 +1,1989 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	#if WPP_SOFTWARE_TRACE
-+		#include "phydm_beamforming.tmh"
-+	#endif
-+#endif
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+
-+void phydm_get_txbf_device_num(
-+	void *dm_void,
-+	u8 macid)
-+{
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*@For BDC*/
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
-+	struct bf_cmn_info *bf = NULL;
-+	struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
-+	u8 act_as_bfer = 0;
-+	u8 act_as_bfee = 0;
-+
-+	if (!(dm->support_ability & ODM_BB_ANT_DIV))
-+		return;
-+
-+	if (is_sta_active(sta)) {
-+		bf = &(sta->bf_info);
-+	} else {
-+		PHYDM_DBG(dm, DBG_TXBF, "[Warning] %s invalid sta_info\n",
-+			  __func__);
-+		return;
-+	}
-+
-+	if (sta->support_wireless_set & WIRELESS_VHT) {
-+		if (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE)
-+			act_as_bfer = 1;
-+
-+		if (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMER_ENABLE)
-+			act_as_bfee = 1;
-+
-+	} else if (sta->support_wireless_set & WIRELESS_HT) {
-+		if (bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE)
-+			act_as_bfer = 1;
-+
-+		if (bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMER_ENABLE)
-+			act_as_bfee = 1;
-+	}
-+
-+	if (act_as_bfer)
-+		{ /* Our Device act as BFer */
-+			dm_bdc_table->w_bfee_client[macid] = true;
-+			dm_bdc_table->num_txbfee_client++;
-+		}
-+	else
-+		dm_bdc_table->w_bfee_client[macid] = false;
-+
-+	if (act_as_bfee)
-+		{ /* Our Device act as BFee */
-+			dm_bdc_table->w_bfer_client[macid] = true;
-+			dm_bdc_table->num_txbfer_client++;
-+		}
-+	else
-+		dm_bdc_table->w_bfer_client[macid] = false;
-+
-+#endif
-+#endif
-+}
-+
-+struct _RT_BEAMFORM_STAINFO *
-+phydm_sta_info_init(struct dm_struct *dm, u16 sta_idx, u8 *my_mac_addr)
-+{
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORM_STAINFO *entry = &beam_info->beamform_sta_info;
-+	struct cmn_sta_info *cmn_sta = dm->phydm_sta_info[sta_idx];
-+	//void					*adapter = dm->adapter;
-+	ADAPTER * adapter = dm->adapter;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	PMGNT_INFO p_MgntInfo = &((adapter)->MgntInfo);
-+	PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo);
-+	PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo);
-+#endif
-+
-+	if (!is_sta_active(cmn_sta)) {
-+		PHYDM_DBG(dm, DBG_TXBF, "%s => sta_info(mac_id:%d) failed\n",
-+			  __func__, sta_idx);
-+		#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		rtw_warn_on(1);
-+		#endif
-+
-+		return entry;
-+	}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	/*odm_move_memory(dm, (PVOID)(entry->my_mac_addr),*/
-+	/*(PVOID)(adapter->CurrentAddress), 6);*/
-+	odm_move_memory(dm, entry->my_mac_addr, my_mac_addr, 6);
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	/*odm_move_memory(dm, entry->my_mac_addr,*/
-+	/*adapter_mac_addr(sta->padapter), 6);*/
-+	odm_move_memory(dm, entry->my_mac_addr, my_mac_addr, 6);
-+#endif
-+
-+	entry->aid = cmn_sta->aid;
-+	entry->ra = cmn_sta->mac_addr;
-+	entry->mac_id = cmn_sta->mac_id;
-+	entry->bw = cmn_sta->bw_mode;
-+	entry->cur_beamform = cmn_sta->bf_info.ht_beamform_cap;
-+	entry->ht_beamform_cap = cmn_sta->bf_info.ht_beamform_cap;
-+
-+#if ODM_IC_11AC_SERIES_SUPPORT
-+	if (cmn_sta->support_wireless_set & WIRELESS_VHT) {
-+		entry->cur_beamform_vht = cmn_sta->bf_info.vht_beamform_cap;
-+		entry->vht_beamform_cap = cmn_sta->bf_info.vht_beamform_cap;
-+	}
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*To Be Removed */
-+	entry->ht_beamform_cap = p_ht_info->HtBeamformCap; /*To Be Removed*/
-+	entry->vht_beamform_cap = p_vht_info->VhtBeamformCap; /*To Be Removed*/
-+
-+	if (sta_idx == 0) { /*@client mode*/
-+		#if ODM_IC_11AC_SERIES_SUPPORT
-+		if (cmn_sta->support_wireless_set & WIRELESS_VHT)
-+			entry->cur_beamform_vht = p_vht_info->VhtCurBeamform;
-+		#endif
-+	}
-+#endif
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "wireless_set = 0x%x, staidx = %d\n",
-+		  cmn_sta->support_wireless_set, sta_idx);
-+	PHYDM_DBG(dm, DBG_TXBF,
-+		  "entry->cur_beamform = 0x%x, entry->cur_beamform_vht = 0x%x\n",
-+		  entry->cur_beamform, entry->cur_beamform_vht);
-+	return entry;
-+}
-+void phydm_sta_info_update(
-+	struct dm_struct *dm,
-+	u16 sta_idx,
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry)
-+{
-+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
-+
-+	if (!is_sta_active(sta))
-+		return;
-+
-+	sta->bf_info.p_aid = beamform_entry->p_aid;
-+	sta->bf_info.g_id = beamform_entry->g_id;
-+}
-+
-+struct _RT_BEAMFORMEE_ENTRY *
-+phydm_beamforming_get_bfee_entry_by_addr(
-+	void *dm_void,
-+	u8 *RA,
-+	u8 *idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i = 0;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
-+		if (beam_info->beamformee_entry[i].is_used && (eq_mac_addr(RA, beam_info->beamformee_entry[i].mac_addr))) {
-+			*idx = i;
-+			return &beam_info->beamformee_entry[i];
-+		}
-+	}
-+
-+	return NULL;
-+}
-+
-+struct _RT_BEAMFORMER_ENTRY *
-+phydm_beamforming_get_bfer_entry_by_addr(
-+	void *dm_void,
-+	u8 *TA,
-+	u8 *idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i = 0;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) {
-+		if (beam_info->beamformer_entry[i].is_used && (eq_mac_addr(TA, beam_info->beamformer_entry[i].mac_addr))) {
-+			*idx = i;
-+			return &beam_info->beamformer_entry[i];
-+		}
-+	}
-+
-+	return NULL;
-+}
-+
-+struct _RT_BEAMFORMEE_ENTRY *
-+phydm_beamforming_get_entry_by_mac_id(
-+	void *dm_void,
-+	u8 mac_id,
-+	u8 *idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i = 0;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
-+		if (beam_info->beamformee_entry[i].is_used && mac_id == beam_info->beamformee_entry[i].mac_id) {
-+			*idx = i;
-+			return &beam_info->beamformee_entry[i];
-+		}
-+	}
-+
-+	return NULL;
-+}
-+
-+enum beamforming_cap
-+phydm_beamforming_get_entry_beam_cap_by_mac_id(
-+	void *dm_void,
-+	u8 mac_id)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i = 0;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	enum beamforming_cap beamform_entry_cap = BEAMFORMING_CAP_NONE;
-+
-+	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
-+		if (beam_info->beamformee_entry[i].is_used && mac_id == beam_info->beamformee_entry[i].mac_id) {
-+			beamform_entry_cap = beam_info->beamformee_entry[i].beamform_entry_cap;
-+			i = BEAMFORMEE_ENTRY_NUM;
-+		}
-+	}
-+
-+	return beamform_entry_cap;
-+}
-+
-+struct _RT_BEAMFORMEE_ENTRY *
-+phydm_beamforming_get_free_bfee_entry(
-+	void *dm_void,
-+	u8 *idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i = 0;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
-+		if (beam_info->beamformee_entry[i].is_used == false) {
-+			*idx = i;
-+			return &beam_info->beamformee_entry[i];
-+		}
-+	}
-+	return NULL;
-+}
-+
-+struct _RT_BEAMFORMER_ENTRY *
-+phydm_beamforming_get_free_bfer_entry(
-+	void *dm_void,
-+	u8 *idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i = 0;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s ===>\n", __func__);
-+
-+	for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) {
-+		if (beam_info->beamformer_entry[i].is_used == false) {
-+			*idx = i;
-+			return &beam_info->beamformer_entry[i];
-+		}
-+	}
-+	return NULL;
-+}
-+
-+/*@
-+ * Description: Get the first entry index of MU Beamformee.
-+ *
-+ * Return value: index of the first MU sta.
-+ *
-+ * 2015.05.25. Created by tynli.
-+ *
-+ */
-+u8 phydm_beamforming_get_first_mu_bfee_entry_idx(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 idx = 0xFF;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	boolean is_found = false;
-+
-+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
-+		if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].is_mu_sta) {
-+			PHYDM_DBG(dm, DBG_TXBF, "[%s] idx=%d!\n", __func__,
-+				  idx);
-+			is_found = true;
-+			break;
-+		}
-+	}
-+
-+	if (!is_found)
-+		idx = 0xFF;
-+
-+	return idx;
-+}
-+
-+/*@Add SU BFee and MU BFee*/
-+struct _RT_BEAMFORMEE_ENTRY *
-+beamforming_add_bfee_entry(
-+	void *dm_void,
-+	struct _RT_BEAMFORM_STAINFO *sta,
-+	enum beamforming_cap beamform_cap,
-+	u8 num_of_sounding_dim,
-+	u8 comp_steering_num_of_bfer,
-+	u8 *idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMEE_ENTRY *entry = phydm_beamforming_get_free_bfee_entry(dm, idx);
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
-+
-+	if (entry != NULL) {
-+		entry->is_used = true;
-+		entry->aid = sta->aid;
-+		entry->mac_id = sta->mac_id;
-+		entry->sound_bw = sta->bw;
-+		odm_move_memory(dm, entry->my_mac_addr, sta->my_mac_addr, 6);
-+
-+		if (phydm_acting_determine(dm, phydm_acting_as_ap)) {
-+			/*@BSSID[44:47] xor BSSID[40:43]*/
-+			u16 bssid = ((sta->my_mac_addr[5] & 0xf0) >> 4) ^ (sta->my_mac_addr[5] & 0xf);
-+			/*@(dec(A) + dec(B)*32) mod 512*/
-+			entry->p_aid = (sta->aid + bssid * 32) & 0x1ff;
-+			entry->g_id = 63;
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "%s: BFee P_AID addressed to STA=%d\n",
-+				  __func__, entry->p_aid);
-+		} else if (phydm_acting_determine(dm, phydm_acting_as_ibss)) {
-+			/*@ad hoc mode*/
-+			entry->p_aid = 0;
-+			entry->g_id = 63;
-+			PHYDM_DBG(dm, DBG_TXBF, "%s: BFee P_AID as IBSS=%d\n",
-+				  __func__, entry->p_aid);
-+		} else {
-+			/*@client mode*/
-+			entry->p_aid = sta->ra[5];
-+			/*@BSSID[39:47]*/
-+			entry->p_aid = (entry->p_aid << 1) | (sta->ra[4] >> 7);
-+			entry->g_id = 0;
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "%s: BFee P_AID addressed to AP=0x%X\n",
-+				  __func__, entry->p_aid);
-+		}
-+		cp_mac_addr(entry->mac_addr, sta->ra);
-+		entry->is_txbf = false;
-+		entry->is_sound = false;
-+		entry->sound_period = 400;
-+		entry->beamform_entry_cap = beamform_cap;
-+		entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
-+
-+		/*		@entry->log_seq = 0xff;				Move to beamforming_add_bfer_entry*/
-+		/*		@entry->log_retry_cnt = 0;			Move to beamforming_add_bfer_entry*/
-+		/*		@entry->LogSuccessCnt = 0;		Move to beamforming_add_bfer_entry*/
-+
-+		entry->log_status_fail_cnt = 0;
-+
-+		entry->num_of_sounding_dim = num_of_sounding_dim;
-+		entry->comp_steering_num_of_bfer = comp_steering_num_of_bfer;
-+
-+		if (beamform_cap & BEAMFORMER_CAP_VHT_MU) {
-+			dm->beamforming_info.beamformee_mu_cnt += 1;
-+			entry->is_mu_sta = true;
-+			dm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(dm);
-+		} else if (beamform_cap & (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) {
-+			dm->beamforming_info.beamformee_su_cnt += 1;
-+			entry->is_mu_sta = false;
-+		}
-+
-+		return entry;
-+	} else
-+		return NULL;
-+}
-+
-+/*@Add SU BFee and MU BFer*/
-+struct _RT_BEAMFORMER_ENTRY *
-+beamforming_add_bfer_entry(
-+	void *dm_void,
-+	struct _RT_BEAMFORM_STAINFO *sta,
-+	enum beamforming_cap beamform_cap,
-+	u8 num_of_sounding_dim,
-+	u8 *idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMER_ENTRY *entry = phydm_beamforming_get_free_bfer_entry(dm, idx);
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
-+
-+	if (entry != NULL) {
-+		entry->is_used = true;
-+		odm_move_memory(dm, entry->my_mac_addr, sta->my_mac_addr, 6);
-+		if (phydm_acting_determine(dm, phydm_acting_as_ap)) {
-+			/*@BSSID[44:47] xor BSSID[40:43]*/
-+			u16 bssid = ((sta->my_mac_addr[5] & 0xf0) >> 4) ^ (sta->my_mac_addr[5] & 0xf);
-+
-+			entry->p_aid = (sta->aid + bssid * 32) & 0x1ff;
-+			entry->g_id = 63;
-+			/*@(dec(A) + dec(B)*32) mod 512*/
-+		} else if (phydm_acting_determine(dm, phydm_acting_as_ibss)) {
-+			entry->p_aid = 0;
-+			entry->g_id = 63;
-+		} else {
-+			entry->p_aid = sta->ra[5];
-+			/*@BSSID[39:47]*/
-+			entry->p_aid = (entry->p_aid << 1) | (sta->ra[4] >> 7);
-+			entry->g_id = 0;
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "%s: P_AID addressed to AP=0x%X\n", __func__,
-+				  entry->p_aid);
-+		}
-+
-+		cp_mac_addr(entry->mac_addr, sta->ra);
-+		entry->beamform_entry_cap = beamform_cap;
-+
-+		entry->pre_log_seq = 0; /*@Modified by Jeffery @2015-04-13*/
-+		entry->log_seq = 0; /*@Modified by Jeffery @2014-10-29*/
-+		entry->log_retry_cnt = 0; /*@Modified by Jeffery @2014-10-29*/
-+		entry->log_success = 0; /*@log_success is NOT needed to be accumulated, so  LogSuccessCnt->log_success, 2015-04-13, Jeffery*/
-+		entry->clock_reset_times = 0; /*@Modified by Jeffery @2015-04-13*/
-+
-+		entry->num_of_sounding_dim = num_of_sounding_dim;
-+
-+		if (beamform_cap & BEAMFORMEE_CAP_VHT_MU) {
-+			dm->beamforming_info.beamformer_mu_cnt += 1;
-+			entry->is_mu_ap = true;
-+			entry->aid = sta->aid;
-+		} else if (beamform_cap & (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) {
-+			dm->beamforming_info.beamformer_su_cnt += 1;
-+			entry->is_mu_ap = false;
-+		}
-+
-+		return entry;
-+	} else
-+		return NULL;
-+}
-+
-+/* Used for beamforming_start_v1 */
-+void phydm_beamforming_ndpa_rate(
-+	void *dm_void,
-+	enum channel_width BW,
-+	u8 rate)
-+{
-+	u16 ndpa_rate = rate;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
-+
-+	if (ndpa_rate == 0) {
-+		if (dm->rssi_min > 30) /* @link RSSI > 30% */
-+			ndpa_rate = ODM_RATE24M;
-+		else
-+			ndpa_rate = ODM_RATE6M;
-+	}
-+
-+	if (ndpa_rate < ODM_RATEMCS0)
-+		BW = (enum channel_width)CHANNEL_WIDTH_20;
-+
-+	ndpa_rate = (ndpa_rate << 8) | BW;
-+	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate);
-+}
-+
-+/* Used for beamforming_start_sw and  beamforming_start_fw */
-+void phydm_beamforming_dym_ndpa_rate(
-+	void *dm_void)
-+{
-+	u16 ndpa_rate = ODM_RATE6M, BW;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	ndpa_rate = ODM_RATE6M;
-+	BW = CHANNEL_WIDTH_20;
-+
-+	ndpa_rate = ndpa_rate << 8 | BW;
-+	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate);
-+	PHYDM_DBG(dm, DBG_TXBF, "%s End, NDPA rate = 0x%X\n", __func__,
-+		  ndpa_rate);
-+}
-+
-+/*@
-+*	SW Sounding : SW Timer unit 1ms
-+*				 HW Timer unit (1/32000) s  32k is clock.
-+*	FW Sounding : FW Timer unit 10ms
-+*/
-+void beamforming_dym_period(
-+	void *dm_void,
-+	u8 status)
-+{
-+	u8 idx;
-+	boolean is_change_period = false;
-+	u16 sound_period_sw, sound_period_fw;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
-+
-+	struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx];
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	/* @3 TODO  per-client throughput caculation. */
-+
-+	if ((*dm->current_tx_tp + *dm->current_rx_tp > 2) && (entry->log_status_fail_cnt <= 20 || status)) {
-+		sound_period_sw = 40; /* @40ms */
-+		sound_period_fw = 40; /* @From  H2C cmd, unit = 10ms */
-+	} else {
-+		sound_period_sw = 4000; /* @4s */
-+		sound_period_fw = 400;
-+	}
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s]sound_period_sw=%d, sound_period_fw=%d\n",
-+		  __func__, sound_period_sw, sound_period_fw);
-+
-+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
-+		beamform_entry = beam_info->beamformee_entry + idx;
-+
-+		if (beamform_entry->default_csi_cnt > 20) {
-+			/*@Modified by David*/
-+			sound_period_sw = 4000;
-+			sound_period_fw = 400;
-+		}
-+
-+		PHYDM_DBG(dm, DBG_TXBF, "[%s] period = %d\n", __func__,
-+			  sound_period_sw);
-+		if ((beamform_entry->beamform_entry_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) == 0)
-+			continue;
-+
-+		if (sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || sound_info->sound_mode == SOUNDING_FW_HT_TIMER) {
-+			if (beamform_entry->sound_period != sound_period_fw) {
-+				beamform_entry->sound_period = sound_period_fw;
-+				is_change_period = true; /*Only FW sounding need to send H2C packet to change sound period. */
-+			}
-+		} else if (beamform_entry->sound_period != sound_period_sw)
-+			beamform_entry->sound_period = sound_period_sw;
-+	}
-+
-+	if (is_change_period)
-+		hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx);
-+}
-+
-+boolean
-+beamforming_send_ht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	enum channel_width BW,
-+	u8 q_idx)
-+{
-+	boolean ret = true;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (q_idx == BEACON_QUEUE)
-+		ret = send_fw_ht_ndpa_packet(dm, RA, BW);
-+	else
-+		ret = send_sw_ht_ndpa_packet(dm, RA, BW);
-+
-+	return ret;
-+}
-+
-+boolean
-+beamforming_send_vht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	u16 AID,
-+	enum channel_width BW,
-+	u8 q_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	boolean ret = true;
-+
-+	hal_com_txbf_set(dm, TXBF_SET_GET_TX_RATE, NULL);
-+
-+	if (beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7 && beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9 && !beam_info->snding3ss)
-+		PHYDM_DBG(dm, DBG_TXBF, "@%s: 3SS VHT 789 don't sounding\n",
-+			  __func__);
-+
-+	else {
-+		if (q_idx == BEACON_QUEUE) /* Send to reserved page => FW NDPA */
-+			ret = send_fw_vht_ndpa_packet(dm, RA, AID, BW);
-+		else {
-+#ifdef SUPPORT_MU_BF
-+#if (SUPPORT_MU_BF == 1)
-+			beam_info->is_mu_sounding = true;
-+			ret = send_sw_vht_mu_ndpa_packet(dm, BW);
-+#else
-+			beam_info->is_mu_sounding = false;
-+			ret = send_sw_vht_ndpa_packet(dm, RA, AID, BW);
-+#endif
-+#else
-+			beam_info->is_mu_sounding = false;
-+			ret = send_sw_vht_ndpa_packet(dm, RA, AID, BW);
-+#endif
-+		}
-+	}
-+	return ret;
-+}
-+
-+enum beamforming_notify_state
-+phydm_beamfomring_is_sounding(
-+	void *dm_void,
-+	struct _RT_BEAMFORMING_INFO *beam_info,
-+	u8 *idx)
-+{
-+	enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE;
-+	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
-+
-+	/*@if(( Beamforming_GetBeamCap(beam_info) & BEAMFORMER_CAP) == 0)*/
-+	/*@is_sounding = BEAMFORMING_NOTIFY_RESET;*/
-+	if (beam_oid_info.sound_oid_mode == sounding_stop_all_timer) {
-+		is_sounding = BEAMFORMING_NOTIFY_RESET;
-+		goto out;
-+	}
-+
-+	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
-+		PHYDM_DBG(dm, DBG_TXBF,
-+			  "@%s: BFee Entry %d is_used=%d, is_sound=%d\n",
-+			  __func__, i, beam_info->beamformee_entry[i].is_used,
-+			  beam_info->beamformee_entry[i].is_sound);
-+		if (beam_info->beamformee_entry[i].is_used && !beam_info->beamformee_entry[i].is_sound) {
-+			PHYDM_DBG(dm, DBG_TXBF, "%s: Add BFee entry %d\n",
-+				  __func__, i);
-+			*idx = i;
-+			if (beam_info->beamformee_entry[i].is_mu_sta)
-+				is_sounding = BEAMFORMEE_NOTIFY_ADD_MU;
-+			else
-+				is_sounding = BEAMFORMEE_NOTIFY_ADD_SU;
-+		}
-+
-+		if (!beam_info->beamformee_entry[i].is_used && beam_info->beamformee_entry[i].is_sound) {
-+			PHYDM_DBG(dm, DBG_TXBF, "%s: Delete BFee entry %d\n",
-+				  __func__, i);
-+			*idx = i;
-+			if (beam_info->beamformee_entry[i].is_mu_sta)
-+				is_sounding = BEAMFORMEE_NOTIFY_DELETE_MU;
-+			else
-+				is_sounding = BEAMFORMEE_NOTIFY_DELETE_SU;
-+		}
-+	}
-+
-+out:
-+	PHYDM_DBG(dm, DBG_TXBF, "%s End, is_sounding = %d\n", __func__,
-+		  is_sounding);
-+	return is_sounding;
-+}
-+
-+/* This function is unused */
-+u8 phydm_beamforming_sounding_idx(
-+	void *dm_void,
-+	struct _RT_BEAMFORMING_INFO *beam_info)
-+{
-+	u8 idx = 0;
-+	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
-+
-+	if (beam_oid_info.sound_oid_mode == SOUNDING_SW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER ||
-+	    beam_oid_info.sound_oid_mode == SOUNDING_HW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER)
-+		idx = beam_oid_info.sound_oid_idx;
-+	else {
-+		u8 i;
-+		for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
-+			if (beam_info->beamformee_entry[i].is_used && !beam_info->beamformee_entry[i].is_sound) {
-+				idx = i;
-+				break;
-+			}
-+		}
-+	}
-+
-+	return idx;
-+}
-+
-+enum sounding_mode
-+phydm_beamforming_sounding_mode(
-+	void *dm_void,
-+	struct _RT_BEAMFORMING_INFO *beam_info,
-+	u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 support_interface = dm->support_interface;
-+
-+	struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx];
-+	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
-+	enum sounding_mode mode = beam_oid_info.sound_oid_mode;
-+
-+	if (beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER) {
-+		if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
-+			mode = beam_oid_info.sound_oid_mode;
-+		else
-+			mode = sounding_stop_all_timer;
-+	} else if (beam_oid_info.sound_oid_mode == SOUNDING_SW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_HT_TIMER) {
-+		if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)
-+			mode = beam_oid_info.sound_oid_mode;
-+		else
-+			mode = sounding_stop_all_timer;
-+	} else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) {
-+		if (support_interface == ODM_ITRF_USB && !(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)))
-+			mode = SOUNDING_FW_VHT_TIMER;
-+		else
-+			mode = SOUNDING_SW_VHT_TIMER;
-+	} else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) {
-+		if (support_interface == ODM_ITRF_USB && !(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)))
-+			mode = SOUNDING_FW_HT_TIMER;
-+		else
-+			mode = SOUNDING_SW_HT_TIMER;
-+	} else
-+		mode = sounding_stop_all_timer;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] support_interface=%d, mode=%d\n",
-+		  __func__, support_interface, mode);
-+
-+	return mode;
-+}
-+
-+u16 phydm_beamforming_sounding_time(
-+	void *dm_void,
-+	struct _RT_BEAMFORMING_INFO *beam_info,
-+	enum sounding_mode mode,
-+	u8 idx)
-+{
-+	u16 sounding_time = 0xffff;
-+	struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx];
-+	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
-+
-+	if (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER)
-+		sounding_time = beam_oid_info.sound_oid_period * 32;
-+	else if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_SW_VHT_TIMER)
-+		/*@Modified by David*/
-+		sounding_time = beam_entry.sound_period; /*@beam_oid_info.sound_oid_period;*/
-+	else
-+		sounding_time = beam_entry.sound_period;
-+
-+	return sounding_time;
-+}
-+
-+enum channel_width
-+phydm_beamforming_sounding_bw(
-+	void *dm_void,
-+	struct _RT_BEAMFORMING_INFO *beam_info,
-+	enum sounding_mode mode,
-+	u8 idx)
-+{
-+	enum channel_width sounding_bw = CHANNEL_WIDTH_20;
-+	struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx];
-+	struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER)
-+		sounding_bw = beam_oid_info.sound_oid_bw;
-+	else if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_SW_VHT_TIMER)
-+		/*@Modified by David*/
-+		sounding_bw = beam_entry.sound_bw; /*@beam_oid_info.sound_oid_bw;*/
-+	else
-+		sounding_bw = beam_entry.sound_bw;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s, sounding_bw=0x%X\n", __func__,
-+		  sounding_bw);
-+
-+	return sounding_bw;
-+}
-+
-+boolean
-+phydm_beamforming_select_beam_entry(
-+	void *dm_void,
-+	struct _RT_BEAMFORMING_INFO *beam_info)
-+{
-+	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	/*@entry.is_sound is different between first and latter NDPA, and should not be used as BFee entry selection*/
-+	/*@BTW, latter modification should sync to the selection mechanism of AP/ADSL instead of the fixed sound_idx.*/
-+	sound_info->sound_idx = phydm_beamforming_sounding_idx(dm, beam_info);
-+	/*sound_info->sound_idx = 0;*/
-+
-+	if (sound_info->sound_idx < BEAMFORMEE_ENTRY_NUM)
-+		sound_info->sound_mode = phydm_beamforming_sounding_mode(dm, beam_info, sound_info->sound_idx);
-+	else
-+		sound_info->sound_mode = sounding_stop_all_timer;
-+
-+	if (sounding_stop_all_timer == sound_info->sound_mode) {
-+		PHYDM_DBG(dm, DBG_TXBF,
-+			  "[%s] Return because of sounding_stop_all_timer\n",
-+			  __func__);
-+		return false;
-+	} else {
-+		sound_info->sound_bw = phydm_beamforming_sounding_bw(dm, beam_info, sound_info->sound_mode, sound_info->sound_idx);
-+		sound_info->sound_period = phydm_beamforming_sounding_time(dm, beam_info, sound_info->sound_mode, sound_info->sound_idx);
-+		return true;
-+	}
-+}
-+
-+/*SU BFee Entry Only*/
-+boolean
-+phydm_beamforming_start_period(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean ret = true;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
-+
-+	phydm_beamforming_dym_ndpa_rate(dm);
-+
-+	phydm_beamforming_select_beam_entry(dm, beam_info); /* @Modified */
-+
-+	if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)
-+		odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);
-+	else if (sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || sound_info->sound_mode == SOUNDING_HW_HT_TIMER ||
-+		 sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) {
-+		HAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF;
-+		u32 val = (sound_info->sound_period | (timer_type << 16));
-+
-+		/* @HW timer stop: All IC has the same setting */
-+		phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type));
-+		/* odm_write_1byte(dm, 0x15F, 0); */
-+		/* @HW timer init: All IC has the same setting, but 92E & 8812A only write 2 bytes */
-+		phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_INIT, (u8 *)(&val));
-+		/* odm_write_1byte(dm, 0x164, 1); */
-+		/* odm_write_4byte(dm, 0x15C, val); */
-+		/* @HW timer start: All IC has the same setting */
-+		phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_START, (u8 *)(&timer_type));
-+		/* odm_write_1byte(dm, 0x15F, 0x5); */
-+	} else if (sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || sound_info->sound_mode == SOUNDING_FW_HT_TIMER)
-+		ret = beamforming_start_fw(dm, sound_info->sound_idx);
-+	else
-+		ret = false;
-+
-+	PHYDM_DBG(dm, DBG_TXBF,
-+		  "[%s] sound_idx=%d, sound_mode=%d, sound_bw=%d, sound_period=%d\n",
-+		  __func__, sound_info->sound_idx, sound_info->sound_mode,
-+		  sound_info->sound_bw, sound_info->sound_period);
-+
-+	return ret;
-+}
-+
-+/* Used after beamforming_leave, and will clear the setting of the "already deleted" entry
-+ *SU BFee Entry Only*/
-+void phydm_beamforming_end_period_sw(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	/*void					*adapter = dm->adapter;*/
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
-+
-+	HAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
-+
-+	if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)
-+		odm_cancel_timer(dm, &beam_info->beamforming_timer);
-+	else if (sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || sound_info->sound_mode == SOUNDING_HW_HT_TIMER ||
-+		 sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER)
-+		/*@HW timer stop: All IC has the same setting*/
-+		phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type));
-+	/*odm_write_1byte(dm, 0x15F, 0);*/
-+}
-+
-+void phydm_beamforming_end_period_fw(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 idx = 0;
-+
-+	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx);
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s]\n", __func__);
-+}
-+
-+/*SU BFee Entry Only*/
-+void phydm_beamforming_clear_entry_sw(
-+	void *dm_void,
-+	boolean is_delete,
-+	u8 delete_idx)
-+{
-+	u8 idx = 0;
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	if (is_delete) {
-+		if (delete_idx < BEAMFORMEE_ENTRY_NUM) {
-+			beamform_entry = beam_info->beamformee_entry + delete_idx;
-+			if (!(!beamform_entry->is_used && beamform_entry->is_sound)) {
-+				PHYDM_DBG(dm, DBG_TXBF,
-+					  "[%s] SW delete_idx is wrong!!!!!\n",
-+					  __func__);
-+				return;
-+			}
-+		}
-+
-+		PHYDM_DBG(dm, DBG_TXBF, "[%s] SW delete BFee entry %d\n",
-+			  __func__, delete_idx);
-+		if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) {
-+			beamform_entry->is_beamforming_in_progress = false;
-+			beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
-+		} else if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
-+			beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
-+			hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&delete_idx);
-+		}
-+		beamform_entry->is_sound = false;
-+		return;
-+	}
-+
-+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
-+		beamform_entry = beam_info->beamformee_entry + idx;
-+
-+		/*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/
-+		/*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/
-+		/*@However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/
-+
-+		if (!beamform_entry->is_sound)
-+			continue;
-+
-+		PHYDM_DBG(dm, DBG_TXBF, "[%s] SW reset BFee entry %d\n",
-+			  __func__, idx);
-+		/*@
-+		*	If End procedure is
-+		*	1. Between (Send NDPA, C2H packet return), reset state to initialized.
-+		*	After C2H packet return , status bit will be set to zero.
-+		*
-+		*	2. After C2H packet, then reset state to initialized and clear status bit.
-+		*/
-+
-+		if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
-+			phydm_beamforming_end_sw(dm, 0);
-+		else if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
-+			beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
-+			hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx);
-+		}
-+
-+		beamform_entry->is_sound = false;
-+	}
-+}
-+
-+void phydm_beamforming_clear_entry_fw(
-+	void *dm_void,
-+	boolean is_delete,
-+	u8 delete_idx)
-+{
-+	u8 idx = 0;
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	if (is_delete) {
-+		if (delete_idx < BEAMFORMEE_ENTRY_NUM) {
-+			beamform_entry = beam_info->beamformee_entry + delete_idx;
-+
-+			if (!(!beamform_entry->is_used && beamform_entry->is_sound)) {
-+				PHYDM_DBG(dm, DBG_TXBF,
-+					  "[%s] FW delete_idx is wrong!!!!!\n",
-+					  __func__);
-+				return;
-+			}
-+		}
-+		PHYDM_DBG(dm, DBG_TXBF, "%s: FW delete BFee entry %d\n",
-+			  __func__, delete_idx);
-+		beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;
-+		beamform_entry->is_sound = false;
-+	} else {
-+		for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
-+			beamform_entry = beam_info->beamformee_entry + idx;
-+
-+			/*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/
-+			/*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/
-+			/*@However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/
-+
-+			if (beamform_entry->is_sound) {
-+				PHYDM_DBG(dm, DBG_TXBF,
-+					  "[%s]FW reset BFee entry %d\n",
-+					  __func__, idx);
-+				/*@
-+				*	If End procedure is
-+				*	1. Between (Send NDPA, C2H packet return), reset state to initialized.
-+				*	After C2H packet return , status bit will be set to zero.
-+				*
-+				*	2. After C2H packet, then reset state to initialized and clear status bit.
-+				*/
-+
-+				beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
-+				beamform_entry->is_sound = false;
-+			}
-+		}
-+	}
-+}
-+
-+/*@
-+*	Called :
-+*	1. Add and delete entry : beamforming_enter/beamforming_leave
-+*	2. FW trigger :  Beamforming_SetTxBFen
-+*	3. Set OID_RT_BEAMFORMING_PERIOD : beamforming_control_v2
-+*/
-+void phydm_beamforming_notify(
-+	void *dm_void)
-+{
-+	u8 idx = BEAMFORMEE_ENTRY_NUM;
-+	enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
-+
-+	is_sounding = phydm_beamfomring_is_sounding(dm, beam_info, &idx);
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s, Before notify, is_sounding=%d, idx=%d\n",
-+		  __func__, is_sounding, idx);
-+	PHYDM_DBG(dm, DBG_TXBF, "%s: beam_info->beamformee_su_cnt = %d\n",
-+		  __func__, beam_info->beamformee_su_cnt);
-+
-+	switch (is_sounding) {
-+	case BEAMFORMEE_NOTIFY_ADD_SU:
-+		PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_ADD_SU\n",
-+			  __func__);
-+		phydm_beamforming_start_period(dm);
-+		break;
-+
-+	case BEAMFORMEE_NOTIFY_DELETE_SU:
-+		PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_DELETE_SU\n",
-+			  __func__);
-+		if (sound_info->sound_mode == SOUNDING_FW_HT_TIMER || sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) {
-+			phydm_beamforming_clear_entry_fw(dm, true, idx);
-+			if (beam_info->beamformee_su_cnt == 0) { /* @For 2->1 entry, we should not cancel SW timer */
-+				phydm_beamforming_end_period_fw(dm);
-+				PHYDM_DBG(dm, DBG_TXBF, "%s: No BFee left\n",
-+					  __func__);
-+			}
-+		} else {
-+			phydm_beamforming_clear_entry_sw(dm, true, idx);
-+			if (beam_info->beamformee_su_cnt == 0) { /* @For 2->1 entry, we should not cancel SW timer */
-+				phydm_beamforming_end_period_sw(dm);
-+				PHYDM_DBG(dm, DBG_TXBF, "%s: No BFee left\n",
-+					  __func__);
-+			}
-+		}
-+		break;
-+
-+	case BEAMFORMEE_NOTIFY_ADD_MU:
-+		PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_ADD_MU\n",
-+			  __func__);
-+		if (beam_info->beamformee_mu_cnt == 2) {
-+			/*@if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)
-+				odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);*/
-+			odm_set_timer(dm, &beam_info->beamforming_timer, 1000); /*@Do MU sounding every 1sec*/
-+		} else
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "%s: Less or larger than 2 MU STAs, not to set timer\n",
-+				  __func__);
-+		break;
-+
-+	case BEAMFORMEE_NOTIFY_DELETE_MU:
-+		PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_DELETE_MU\n",
-+			  __func__);
-+		if (beam_info->beamformee_mu_cnt == 1) {
-+			/*@if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)*/ {
-+				odm_cancel_timer(dm, &beam_info->beamforming_timer);
-+				PHYDM_DBG(dm, DBG_TXBF,
-+					  "%s: Less than 2 MU STAs, stop sounding\n",
-+					  __func__);
-+			}
-+		}
-+		break;
-+
-+	case BEAMFORMING_NOTIFY_RESET:
-+		if (sound_info->sound_mode == SOUNDING_FW_HT_TIMER || sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) {
-+			phydm_beamforming_clear_entry_fw(dm, false, idx);
-+			phydm_beamforming_end_period_fw(dm);
-+		} else {
-+			phydm_beamforming_clear_entry_sw(dm, false, idx);
-+			phydm_beamforming_end_period_sw(dm);
-+		}
-+
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+boolean
-+beamforming_init_entry(void *dm_void, u16 sta_idx, u8 *bfer_bfee_idx,
-+		       u8 *my_mac_addr)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *cmn_sta = dm->phydm_sta_info[sta_idx];
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
-+	struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL;
-+	struct _RT_BEAMFORM_STAINFO *sta = NULL;
-+	enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;
-+	u8 bfer_idx = 0xF, bfee_idx = 0xF;
-+	u8 num_of_sounding_dim = 0, comp_steering_num_of_bfer = 0;
-+
-+	if (!is_sta_active(cmn_sta)) {
-+		PHYDM_DBG(dm, DBG_TXBF, "%s => sta_info(mac_id:%d) failed\n",
-+			  __func__, sta_idx);
-+		#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		rtw_warn_on(1);
-+		#endif
-+		return false;
-+	}
-+
-+	sta = phydm_sta_info_init(dm, sta_idx, my_mac_addr);
-+	/*The current setting does not support Beaforming*/
-+	if (BEAMFORMING_CAP_NONE == sta->ht_beamform_cap && BEAMFORMING_CAP_NONE == sta->vht_beamform_cap) {
-+		PHYDM_DBG(dm, DBG_TXBF,
-+			  "The configuration disabled Beamforming! Skip...\n");
-+		return false;
-+	}
-+
-+	if (!(cmn_sta->support_wireless_set & (WIRELESS_VHT | WIRELESS_HT)))
-+		return false;
-+	else {
-+		if (cmn_sta->support_wireless_set & WIRELESS_HT) { /*@HT*/
-+			if (TEST_FLAG(sta->cur_beamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { /*We are Beamformee because the STA is Beamformer*/
-+				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_HT_EXPLICIT);
-+				num_of_sounding_dim = (sta->cur_beamform & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6;
-+			}
-+			/*We are Beamformer because the STA is Beamformee*/
-+			if (TEST_FLAG(sta->cur_beamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE) ||
-+			    TEST_FLAG(sta->ht_beamform_cap, BEAMFORMING_HT_BEAMFORMER_TEST)) {
-+				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_HT_EXPLICIT);
-+				comp_steering_num_of_bfer = (sta->cur_beamform & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4;
-+			}
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "[%s] HT cur_beamform=0x%X, beamform_cap=0x%X\n",
-+				  __func__, sta->cur_beamform, beamform_cap);
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "[%s] HT num_of_sounding_dim=%d, comp_steering_num_of_bfer=%d\n",
-+				  __func__, num_of_sounding_dim,
-+				  comp_steering_num_of_bfer);
-+		}
-+#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
-+		if (cmn_sta->support_wireless_set & WIRELESS_VHT) { /*VHT*/
-+
-+			/* We are Beamformee because the STA is SU Beamformer*/
-+			if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
-+				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_SU);
-+				num_of_sounding_dim = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;
-+			}
-+			/* We are Beamformer because the STA is SU Beamformee*/
-+			if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) ||
-+			    TEST_FLAG(sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) {
-+				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_SU);
-+				comp_steering_num_of_bfer = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;
-+			}
-+			/* We are Beamformee because the STA is MU Beamformer*/
-+			if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {
-+				beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_MU);
-+				num_of_sounding_dim = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;
-+			}
-+			/* We are Beamformer because the STA is MU Beamformee*/
-+			if (phydm_acting_determine(dm, phydm_acting_as_ap)) { /* Only AP mode supports to act an MU beamformer */
-+				if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE) ||
-+				    TEST_FLAG(sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) {
-+					beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_MU);
-+					comp_steering_num_of_bfer = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;
-+				}
-+			}
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "[%s]VHT cur_beamform_vht=0x%X, beamform_cap=0x%X\n",
-+				  __func__, sta->cur_beamform_vht,
-+				  beamform_cap);
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "[%s]VHT num_of_sounding_dim=0x%X, comp_steering_num_of_bfer=0x%X\n",
-+				  __func__, num_of_sounding_dim,
-+				  comp_steering_num_of_bfer);
-+		}
-+#endif
-+	}
-+
-+	if (beamform_cap == BEAMFORMING_CAP_NONE)
-+		return false;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Self BF Entry Cap = 0x%02X\n", __func__,
-+		  beamform_cap);
-+
-+	/*We are BFee, so the entry is BFer*/
-+	if (beamform_cap & (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) {
-+		beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, sta->ra, &bfer_idx);
-+
-+		if (beamformer_entry == NULL) {
-+			beamformer_entry = beamforming_add_bfer_entry(dm, sta, beamform_cap, num_of_sounding_dim, &bfer_idx);
-+			if (beamformer_entry == NULL)
-+				PHYDM_DBG(dm, DBG_TXBF,
-+					  "[%s]Not enough BFer entry!!!!!\n",
-+					  __func__);
-+		}
-+	}
-+
-+	/*We are BFer, so the entry is BFee*/
-+	if (beamform_cap & (BEAMFORMER_CAP_VHT_MU | BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) {
-+		beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, sta->ra, &bfee_idx);
-+
-+		/*@if BFeeIdx = 0xF, that represent for no matched MACID among all linked entrys */
-+		PHYDM_DBG(dm, DBG_TXBF, "[%s] Get BFee entry 0x%X by address\n",
-+			  __func__, bfee_idx);
-+		if (beamform_entry == NULL) {
-+			beamform_entry = beamforming_add_bfee_entry(dm, sta, beamform_cap, num_of_sounding_dim, comp_steering_num_of_bfer, &bfee_idx);
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "[%s]: sta->AID=%d, sta->mac_id=%d\n",
-+				  __func__, sta->aid, sta->mac_id);
-+
-+			PHYDM_DBG(dm, DBG_TXBF, "[%s]: Add BFee entry %d\n",
-+				  __func__, bfee_idx);
-+
-+			if (beamform_entry == NULL)
-+				return false;
-+			else
-+				beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING;
-+		} else {
-+			/*@Entry has been created. If entry is initialing or progressing then errors occur.*/
-+			if (beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED &&
-+			    beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED)
-+				return false;
-+			else
-+				beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING;
-+		}
-+		beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
-+		phydm_sta_info_update(dm, sta_idx, beamform_entry);
-+	}
-+
-+	*bfer_bfee_idx = (bfer_idx << 4) | bfee_idx;
-+	PHYDM_DBG(dm, DBG_TXBF,
-+		  "[%s] End: bfer_idx=0x%X, bfee_idx=0x%X, bfer_bfee_idx=0x%X\n",
-+		  __func__, bfer_idx, bfee_idx, *bfer_bfee_idx);
-+
-+	return true;
-+}
-+
-+void beamforming_deinit_entry(
-+	void *dm_void,
-+	u8 *RA)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 idx = 0;
-+
-+	struct _RT_BEAMFORMER_ENTRY *bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, RA, &idx);
-+	struct _RT_BEAMFORMEE_ENTRY *bfee_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
-+	boolean ret = false;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
-+
-+	if (bfee_entry != NULL) {
-+		PHYDM_DBG(dm, DBG_TXBF, "%s, bfee_entry\n", __func__);
-+		bfee_entry->is_used = false;
-+		bfee_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE;
-+		bfee_entry->is_beamforming_in_progress = false;
-+		if (bfee_entry->is_mu_sta) {
-+			dm->beamforming_info.beamformee_mu_cnt -= 1;
-+			dm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(dm);
-+		} else
-+			dm->beamforming_info.beamformee_su_cnt -= 1;
-+		ret = true;
-+	}
-+
-+	if (bfer_entry != NULL) {
-+		PHYDM_DBG(dm, DBG_TXBF, "%s, bfer_entry\n", __func__);
-+		bfer_entry->is_used = false;
-+		bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE;
-+		if (bfer_entry->is_mu_ap)
-+			dm->beamforming_info.beamformer_mu_cnt -= 1;
-+		else
-+			dm->beamforming_info.beamformer_su_cnt -= 1;
-+		ret = true;
-+	}
-+
-+	if (ret == true)
-+		hal_com_txbf_set(dm, TXBF_SET_SOUNDING_LEAVE, (u8 *)&idx);
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s End, idx = 0x%X\n", __func__, idx);
-+}
-+
-+boolean
-+beamforming_start_v1(
-+	void *dm_void,
-+	u8 *RA,
-+	boolean mode,
-+	enum channel_width BW,
-+	u8 rate)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 idx = 0;
-+	struct _RT_BEAMFORMEE_ENTRY *entry;
-+	boolean ret = true;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
-+
-+	if (entry->is_used == false) {
-+		entry->is_beamforming_in_progress = false;
-+		return false;
-+	} else {
-+		if (entry->is_beamforming_in_progress)
-+			return false;
-+
-+		entry->is_beamforming_in_progress = true;
-+
-+		if (mode == 1) {
-+			if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) {
-+				entry->is_beamforming_in_progress = false;
-+				return false;
-+			}
-+		} else if (mode == 0) {
-+			if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) {
-+				entry->is_beamforming_in_progress = false;
-+				return false;
-+			}
-+		}
-+
-+		if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) {
-+			entry->is_beamforming_in_progress = false;
-+			return false;
-+		} else {
-+			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING;
-+			entry->is_sound = true;
-+		}
-+	}
-+
-+	entry->sound_bw = BW;
-+	beam_info->beamformee_cur_idx = idx;
-+	phydm_beamforming_ndpa_rate(dm, BW, rate);
-+	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx);
-+
-+	if (mode == 1)
-+		ret = beamforming_send_ht_ndpa_packet(dm, RA, BW, NORMAL_QUEUE);
-+	else
-+		ret = beamforming_send_vht_ndpa_packet(dm, RA, entry->aid, BW, NORMAL_QUEUE);
-+
-+	if (ret == false) {
-+		beamforming_leave(dm, RA);
-+		entry->is_beamforming_in_progress = false;
-+		return false;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s  idx %d\n", __func__, idx);
-+	return true;
-+}
-+
-+boolean
-+beamforming_start_sw(
-+	void *dm_void,
-+	u8 idx,
-+	u8 mode,
-+	enum channel_width BW)
-+{
-+	u8 *ra = NULL;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMEE_ENTRY *entry;
-+	boolean ret = true;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+#ifdef SUPPORT_MU_BF
-+#if (SUPPORT_MU_BF == 1)
-+	u8 i, poll_sta_cnt = 0;
-+	boolean is_get_first_bfee = false;
-+#endif
-+#endif
-+
-+	if (beam_info->is_mu_sounding) {
-+		beam_info->is_mu_sounding_in_progress = true;
-+		entry = &beam_info->beamformee_entry[idx];
-+		ra = entry->mac_addr;
-+
-+	} else {
-+		entry = &beam_info->beamformee_entry[idx];
-+
-+		if (entry->is_used == false) {
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "Skip Beamforming, no entry for idx =%d\n",
-+				  idx);
-+			entry->is_beamforming_in_progress = false;
-+			return false;
-+		}
-+
-+		if (entry->is_beamforming_in_progress) {
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "is_beamforming_in_progress, skip...\n");
-+			return false;
-+		}
-+
-+		entry->is_beamforming_in_progress = true;
-+		ra = entry->mac_addr;
-+
-+		if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER) {
-+			if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) {
-+				entry->is_beamforming_in_progress = false;
-+				PHYDM_DBG(dm, DBG_TXBF,
-+					  "%s Return by not support BEAMFORMER_CAP_HT_EXPLICIT <==\n",
-+					  __func__);
-+				return false;
-+			}
-+		} else if (mode == SOUNDING_SW_VHT_TIMER || mode == SOUNDING_HW_VHT_TIMER || mode == SOUNDING_AUTO_VHT_TIMER) {
-+			if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) {
-+				entry->is_beamforming_in_progress = false;
-+				PHYDM_DBG(dm, DBG_TXBF,
-+					  "%s Return by not support BEAMFORMER_CAP_VHT_SU <==\n",
-+					  __func__);
-+				return false;
-+			}
-+		}
-+		if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) {
-+			entry->is_beamforming_in_progress = false;
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "%s Return by incorrect beamform_entry_state(%d) <==\n",
-+				  __func__, entry->beamform_entry_state);
-+			return false;
-+		} else {
-+			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING;
-+			entry->is_sound = true;
-+		}
-+
-+		beam_info->beamformee_cur_idx = idx;
-+	}
-+
-+	/*@2014.12.22 Luke: Need to be checked*/
-+	/*@GET_TXBF_INFO(adapter)->fTxbfSet(adapter, TXBF_SET_SOUNDING_STATUS, (u8*)&idx);*/
-+
-+	if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER)
-+		ret = beamforming_send_ht_ndpa_packet(dm, ra, BW, NORMAL_QUEUE);
-+	else
-+		ret = beamforming_send_vht_ndpa_packet(dm, ra, entry->aid, BW, NORMAL_QUEUE);
-+
-+	if (ret == false) {
-+		beamforming_leave(dm, ra);
-+		entry->is_beamforming_in_progress = false;
-+		return false;
-+	}
-+
-+/*@--------------------------
-+	 * Send BF Report Poll for MU BF
-+	--------------------------*/
-+#ifdef SUPPORT_MU_BF
-+#if (SUPPORT_MU_BF == 1)
-+	if (beam_info->beamformee_mu_cnt <= 1)
-+		goto out;
-+
-+	/* @More than 1 MU STA*/
-+	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
-+		entry = &beam_info->beamformee_entry[i];
-+		if (!entry->is_mu_sta)
-+			continue;
-+
-+		if (!is_get_first_bfee) {
-+			is_get_first_bfee = true;
-+			continue;
-+		}
-+
-+		poll_sta_cnt++;
-+		if (poll_sta_cnt == (beam_info->beamformee_mu_cnt - 1)) /* The last STA*/
-+			send_sw_vht_bf_report_poll(dm, entry->mac_addr, true);
-+		else
-+			send_sw_vht_bf_report_poll(dm, entry->mac_addr, false);
-+	}
-+out:
-+#endif
-+#endif
-+	return true;
-+}
-+
-+boolean
-+beamforming_start_fw(
-+	void *dm_void,
-+	u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMEE_ENTRY *entry;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	entry = &beam_info->beamformee_entry[idx];
-+	if (entry->is_used == false) {
-+		PHYDM_DBG(dm, DBG_TXBF,
-+			  "Skip Beamforming, no entry for idx =%d\n", idx);
-+		return false;
-+	}
-+
-+	entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING;
-+	entry->is_sound = true;
-+	hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx);
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] End, idx=0x%X\n", __func__, idx);
-+	return true;
-+}
-+
-+void beamforming_check_sounding_success(
-+	void *dm_void,
-+	boolean status)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx];
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[David]@%s Start!\n", __func__);
-+
-+	if (status == 1) {
-+		if (entry->log_status_fail_cnt == 21)
-+			beamforming_dym_period(dm, status);
-+		entry->log_status_fail_cnt = 0;
-+	} else if (entry->log_status_fail_cnt <= 20) {
-+		entry->log_status_fail_cnt++;
-+		PHYDM_DBG(dm, DBG_TXBF, "%s log_status_fail_cnt %d\n", __func__,
-+			  entry->log_status_fail_cnt);
-+	}
-+	if (entry->log_status_fail_cnt > 20) {
-+		entry->log_status_fail_cnt = 21;
-+		PHYDM_DBG(dm, DBG_TXBF,
-+			  "%s log_status_fail_cnt > 20, Stop SOUNDING\n",
-+			  __func__);
-+		beamforming_dym_period(dm, status);
-+	}
-+}
-+
-+void phydm_beamforming_end_sw(
-+	void *dm_void,
-+	boolean status)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx];
-+
-+	if (beam_info->is_mu_sounding) {
-+		PHYDM_DBG(dm, DBG_TXBF, "%s: MU sounding done\n", __func__);
-+		beam_info->is_mu_sounding_in_progress = false;
-+		hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS,
-+				 (u8 *)&beam_info->beamformee_cur_idx);
-+	} else {
-+		if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSING) {
-+			PHYDM_DBG(dm, DBG_TXBF, "[%s] BeamformStatus %d\n",
-+				  __func__, entry->beamform_entry_state);
-+			return;
-+		}
-+
-+		if (beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7 && beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9 && !beam_info->snding3ss) {
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "[%s] VHT3SS 7,8,9, do not apply V matrix.\n",
-+				  __func__);
-+			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
-+			hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS,
-+					 (u8 *)&beam_info->beamformee_cur_idx);
-+		} else if (status == 1) {
-+			entry->log_status_fail_cnt = 0;
-+			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
-+			hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS,
-+					 (u8 *)&beam_info->beamformee_cur_idx);
-+		} else {
-+			entry->log_status_fail_cnt++;
-+			entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
-+			hal_com_txbf_set(dm, TXBF_SET_TX_PATH_RESET,
-+					 (u8 *)&beam_info->beamformee_cur_idx);
-+			PHYDM_DBG(dm, DBG_TXBF, "[%s] log_status_fail_cnt %d\n",
-+				  __func__, entry->log_status_fail_cnt);
-+		}
-+
-+		if (entry->log_status_fail_cnt > 50) {
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "%s log_status_fail_cnt > 50, Stop SOUNDING\n",
-+				  __func__);
-+			entry->is_sound = false;
-+			beamforming_deinit_entry(dm, entry->mac_addr);
-+
-+			/*@Modified by David - Every action of deleting entry should follow by Notify*/
-+			phydm_beamforming_notify(dm);
-+		}
-+
-+		entry->is_beamforming_in_progress = false;
-+	}
-+	PHYDM_DBG(dm, DBG_TXBF, "%s: status=%d\n", __func__, status);
-+}
-+
-+void beamforming_timer_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *dm_void
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	void *context
-+#endif
-+	)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	void *adapter = (void *)context;
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->odmpriv;
-+#endif
-+	boolean ret = false;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+	struct _RT_BEAMFORMEE_ENTRY *entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]);
-+	struct _RT_SOUNDING_INFO *sound_info = &(beam_info->sounding_info);
-+	boolean is_beamforming_in_progress;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
-+
-+	if (beam_info->is_mu_sounding)
-+		is_beamforming_in_progress = beam_info->is_mu_sounding_in_progress;
-+	else
-+		is_beamforming_in_progress = entry->is_beamforming_in_progress;
-+
-+	if (is_beamforming_in_progress) {
-+		PHYDM_DBG(dm, DBG_TXBF,
-+			  "is_beamforming_in_progress, reset it\n");
-+		phydm_beamforming_end_sw(dm, 0);
-+	}
-+
-+	ret = phydm_beamforming_select_beam_entry(dm, beam_info);
-+#if (SUPPORT_MU_BF == 1)
-+	if (ret && beam_info->beamformee_mu_cnt > 1)
-+		ret = 1;
-+	else
-+		ret = 0;
-+#endif
-+	if (ret)
-+		ret = beamforming_start_sw(dm, sound_info->sound_idx, sound_info->sound_mode, sound_info->sound_bw);
-+	else
-+		PHYDM_DBG(dm, DBG_TXBF,
-+			  "%s, Error value return from BeamformingStart_V2\n",
-+			  __func__);
-+
-+	if (beam_info->beamformee_su_cnt != 0 || beam_info->beamformee_mu_cnt > 1) {
-+		if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)
-+			odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);
-+		else {
-+			u32 val = (sound_info->sound_period << 16) | HAL_TIMER_TXBF;
-+			phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_RESTART, (u8 *)(&val));
-+		}
-+	}
-+}
-+
-+void beamforming_sw_timer_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct phydm_timer_list *timer
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	void *function_context
-+#endif
-+	)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter = (void *)timer->Adapter;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+	beamforming_timer_callback(dm);
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	struct dm_struct *dm = (struct dm_struct *)function_context;
-+	void *adapter = dm->adapter;
-+
-+	if (*dm->is_net_closed == true)
-+		return;
-+	phydm_run_in_thread_cmd(dm, beamforming_timer_callback, adapter);
-+#endif
-+}
-+
-+void phydm_beamforming_init(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMING_OID_INFO *beam_oid_info = &beam_info->beamforming_oid_info;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter = dm->adapter;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+
-+#ifdef BEAMFORMING_VERSION_1
-+	if (hal_data->beamforming_version != BEAMFORMING_VERSION_1) {
-+		return;
-+	}
-+#endif
-+#endif
-+
-+	beam_oid_info->sound_oid_mode = SOUNDING_STOP_OID_TIMER;
-+	PHYDM_DBG(dm, DBG_TXBF, "%s mode (%d)\n", __func__,
-+		  beam_oid_info->sound_oid_mode);
-+
-+	beam_info->beamformee_su_cnt = 0;
-+	beam_info->beamformer_su_cnt = 0;
-+	beam_info->beamformee_mu_cnt = 0;
-+	beam_info->beamformer_mu_cnt = 0;
-+	beam_info->beamformee_mu_reg_maping = 0;
-+	beam_info->mu_ap_index = 0;
-+	beam_info->is_mu_sounding = false;
-+	beam_info->first_mu_bfee_index = 0xFF;
-+	beam_info->apply_v_matrix = true;
-+	beam_info->snding3ss = false;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	beam_info->source_adapter = dm->adapter;
-+#endif
-+	hal_com_txbf_beamform_init(dm);
-+}
-+
-+boolean
-+phydm_acting_determine(
-+	void *dm_void,
-+	enum phydm_acting_type type)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean ret = false;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter = dm->beamforming_info.source_adapter;
-+#else
-+	struct _ADAPTER *adapter = dm->adapter;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	if (type == phydm_acting_as_ap)
-+		ret = ACTING_AS_AP(adapter);
-+	else if (type == phydm_acting_as_ibss)
-+		ret = ACTING_AS_IBSS(((PADAPTER)(adapter)));
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-+
-+	if (type == phydm_acting_as_ap)
-+		ret = check_fwstate(pmlmepriv, WIFI_AP_STATE);
-+	else if (type == phydm_acting_as_ibss)
-+		ret = check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
-+#endif
-+
-+	return ret;
-+}
-+
-+void beamforming_enter(void *dm_void, u16 sta_idx, u8 *my_mac_addr)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 bfer_bfee_idx = 0xff;
-+
-+	if (beamforming_init_entry(dm, sta_idx, &bfer_bfee_idx, my_mac_addr))
-+		hal_com_txbf_set(dm, TXBF_SET_SOUNDING_ENTER, (u8 *)&bfer_bfee_idx);
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] End!\n", __func__);
-+}
-+
-+void beamforming_leave(
-+	void *dm_void,
-+	u8 *RA)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (RA != NULL) {
-+		beamforming_deinit_entry(dm, RA);
-+		phydm_beamforming_notify(dm);
-+	}
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] End!!\n", __func__);
-+}
-+
-+enum beamforming_cap
-+phydm_beamforming_get_beam_cap(
-+	void *dm_void,
-+	struct _RT_BEAMFORMING_INFO *beam_info)
-+{
-+	u8 i;
-+	boolean is_self_beamformer = false;
-+	boolean is_self_beamformee = false;
-+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
-+	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
-+	enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
-+		beamformee_entry = beam_info->beamformee_entry[i];
-+
-+		if (beamformee_entry.is_used) {
-+			is_self_beamformer = true;
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "[%s] BFee entry %d is_used=true\n", __func__,
-+				  i);
-+			break;
-+		}
-+	}
-+
-+	for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) {
-+		beamformer_entry = beam_info->beamformer_entry[i];
-+
-+		if (beamformer_entry.is_used) {
-+			is_self_beamformee = true;
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "[%s]: BFer entry %d is_used=true\n",
-+				  __func__, i);
-+			break;
-+		}
-+	}
-+
-+	if (is_self_beamformer)
-+		beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP);
-+	if (is_self_beamformee)
-+		beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP);
-+
-+	return beamform_cap;
-+}
-+
-+boolean
-+beamforming_control_v1(
-+	void *dm_void,
-+	u8 *RA,
-+	u8 AID,
-+	u8 mode,
-+	enum channel_width BW,
-+	u8 rate)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean ret = true;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "AID (%d), mode (%d), BW (%d)\n", AID, mode,
-+		  BW);
-+
-+	switch (mode) {
-+	case 0:
-+		ret = beamforming_start_v1(dm, RA, 0, BW, rate);
-+		break;
-+	case 1:
-+		ret = beamforming_start_v1(dm, RA, 1, BW, rate);
-+		break;
-+	case 2:
-+		phydm_beamforming_ndpa_rate(dm, BW, rate);
-+		ret = beamforming_send_vht_ndpa_packet(dm, RA, AID, BW, NORMAL_QUEUE);
-+		break;
-+	case 3:
-+		phydm_beamforming_ndpa_rate(dm, BW, rate);
-+		ret = beamforming_send_ht_ndpa_packet(dm, RA, BW, NORMAL_QUEUE);
-+		break;
-+	}
-+	return ret;
-+}
-+
-+/*Only OID uses this function*/
-+boolean
-+phydm_beamforming_control_v2(
-+	void *dm_void,
-+	u8 idx,
-+	u8 mode,
-+	enum channel_width BW,
-+	u16 period)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMING_OID_INFO *beam_oid_info = &beam_info->beamforming_oid_info;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
-+	PHYDM_DBG(dm, DBG_TXBF, "idx (%d), mode (%d), BW (%d), period (%d)\n",
-+		  idx, mode, BW, period);
-+
-+	beam_oid_info->sound_oid_idx = idx;
-+	beam_oid_info->sound_oid_mode = (enum sounding_mode)mode;
-+	beam_oid_info->sound_oid_bw = BW;
-+	beam_oid_info->sound_oid_period = period;
-+
-+	phydm_beamforming_notify(dm);
-+
-+	return true;
-+}
-+
-+void phydm_beamforming_watchdog(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__);
-+
-+	if (beam_info->beamformee_su_cnt == 0)
-+		return;
-+
-+	beamforming_dym_period(dm, 0);
-+}
-+enum beamforming_cap
-+phydm_get_beamform_cap(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = NULL;
-+	struct bf_cmn_info *bf_info = NULL;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	void *adapter = dm->adapter;
-+	enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE;
-+	u8 macid;
-+	u8 ht_curbeamformcap = 0;
-+	u16 vht_curbeamformcap = 0;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	PMGNT_INFO p_MgntInfo = &(((PADAPTER)(adapter))->MgntInfo);
-+	PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo);
-+	PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo);
-+
-+	ht_curbeamformcap = p_ht_info->HtCurBeamform;
-+	vht_curbeamformcap = p_vht_info->VhtCurBeamform;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[%s] WIN ht_curcap = %d ; vht_curcap = %d\n", __func__,
-+		  ht_curbeamformcap, vht_curbeamformcap);
-+
-+	if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) /*We are Beamformee because the STA is Beamformer*/
-+		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP));
-+
-+	/*We are Beamformer because the STA is Beamformee*/
-+	if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMEE_ENABLE))
-+		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP));
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
-+
-+	/* We are Beamformee because the STA is SU Beamformer*/
-+	if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMER_ENABLE))
-+		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP));
-+
-+	/* We are Beamformer because the STA is SU Beamformee*/
-+	if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE))
-+		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP));
-+
-+	/* We are Beamformee because the STA is MU Beamformer*/
-+	if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE))
-+		beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP));
-+#endif
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+
-+	for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
-+		sta = dm->phydm_sta_info[macid];
-+
-+		if (!is_sta_active(sta))
-+			continue;
-+
-+		bf_info = &sta->bf_info;
-+		vht_curbeamformcap = bf_info->vht_beamform_cap;
-+		ht_curbeamformcap = bf_info->ht_beamform_cap;
-+
-+		if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) /*We are Beamformee because the STA is Beamformer*/
-+			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP));
-+
-+		/*We are Beamformer because the STA is Beamformee*/
-+		if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMEE_ENABLE))
-+			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP));
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
-+		/* We are Beamformee because the STA is SU Beamformer*/
-+		if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMER_ENABLE))
-+			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP));
-+
-+		/* We are Beamformer because the STA is SU Beamformee*/
-+		if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE))
-+			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP));
-+
-+		/* We are Beamformee because the STA is MU Beamformer*/
-+		if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE))
-+			beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP));
-+#endif
-+	}
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[%s] CE ht_curcap = %d ; vht_curcap = %d\n",
-+		  __func__, ht_curbeamformcap, vht_curbeamformcap);
-+
-+#endif
-+
-+	return beamform_cap;
-+}
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_beamforming.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_beamforming.h
-new file mode 100644
-index 000000000000..efb53e3099da
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_beamforming.h
-@@ -0,0 +1,363 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __INC_PHYDM_BEAMFORMING_H
-+#define __INC_PHYDM_BEAMFORMING_H
-+
-+/*@Beamforming Related*/
-+#include "txbf/halcomtxbf.h"
-+#include "txbf/haltxbfjaguar.h"
-+#include "txbf/haltxbf8192e.h"
-+#include "txbf/haltxbf8814a.h"
-+#include "txbf/haltxbf8822b.h"
-+#include "txbf/haltxbfinterface.h"
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+#define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0)
-+#define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5])
-+
-+#endif
-+
-+#define MAX_BEAMFORMEE_SU 2
-+#define MAX_BEAMFORMER_SU 2
-+#if ((RTL8822B_SUPPORT == 1) || (RTL8812F_SUPPORT == 1))
-+#define MAX_BEAMFORMEE_MU 6
-+#define MAX_BEAMFORMER_MU 1
-+#else
-+#define MAX_BEAMFORMEE_MU 0
-+#define MAX_BEAMFORMER_MU 0
-+#endif
-+
-+#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU)
-+#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU)
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+/*@for different naming between WIN and CE*/
-+#define BEACON_QUEUE BCN_QUEUE_INX
-+#define NORMAL_QUEUE MGT_QUEUE_INX
-+#define RT_DISABLE_FUNC RTW_DISABLE_FUNC
-+#define RT_ENABLE_FUNC RTW_ENABLE_FUNC
-+#endif
-+
-+enum beamforming_entry_state {
-+	BEAMFORMING_ENTRY_STATE_UNINITIALIZE,
-+	BEAMFORMING_ENTRY_STATE_INITIALIZEING,
-+	BEAMFORMING_ENTRY_STATE_INITIALIZED,
-+	BEAMFORMING_ENTRY_STATE_PROGRESSING,
-+	BEAMFORMING_ENTRY_STATE_PROGRESSED
-+};
-+
-+enum beamforming_notify_state {
-+	BEAMFORMING_NOTIFY_NONE,
-+	BEAMFORMING_NOTIFY_ADD,
-+	BEAMFORMING_NOTIFY_DELETE,
-+	BEAMFORMEE_NOTIFY_ADD_SU,
-+	BEAMFORMEE_NOTIFY_DELETE_SU,
-+	BEAMFORMEE_NOTIFY_ADD_MU,
-+	BEAMFORMEE_NOTIFY_DELETE_MU,
-+	BEAMFORMING_NOTIFY_RESET
-+};
-+
-+enum beamforming_cap {
-+	BEAMFORMING_CAP_NONE = 0x0,
-+	BEAMFORMER_CAP_HT_EXPLICIT = BIT(1),
-+	BEAMFORMEE_CAP_HT_EXPLICIT = BIT(2),
-+	BEAMFORMER_CAP_VHT_SU = BIT(5), /* @Self has er Cap, because Reg er  & peer ee */
-+	BEAMFORMEE_CAP_VHT_SU = BIT(6), /* @Self has ee Cap, because Reg ee & peer er */
-+	BEAMFORMER_CAP_VHT_MU = BIT(7), /* @Self has er Cap, because Reg er  & peer ee */
-+	BEAMFORMEE_CAP_VHT_MU = BIT(8), /* @Self has ee Cap, because Reg ee & peer er */
-+	BEAMFORMER_CAP = BIT(9),
-+	BEAMFORMEE_CAP = BIT(10),
-+};
-+
-+enum sounding_mode {
-+	SOUNDING_SW_VHT_TIMER = 0x0,
-+	SOUNDING_SW_HT_TIMER = 0x1,
-+	sounding_stop_all_timer = 0x2,
-+	SOUNDING_HW_VHT_TIMER = 0x3,
-+	SOUNDING_HW_HT_TIMER = 0x4,
-+	SOUNDING_STOP_OID_TIMER = 0x5,
-+	SOUNDING_AUTO_VHT_TIMER = 0x6,
-+	SOUNDING_AUTO_HT_TIMER = 0x7,
-+	SOUNDING_FW_VHT_TIMER = 0x8,
-+	SOUNDING_FW_HT_TIMER = 0x9,
-+};
-+
-+struct _RT_BEAMFORM_STAINFO {
-+	u8 *ra;
-+	u16 aid;
-+	u16 mac_id;
-+	u8 my_mac_addr[6];
-+	/*WIRELESS_MODE				wireless_mode;*/
-+	enum channel_width bw;
-+	enum beamforming_cap beamform_cap;
-+	u8 ht_beamform_cap;
-+	u16 vht_beamform_cap;
-+	u8 cur_beamform;
-+	u16 cur_beamform_vht;
-+};
-+
-+struct _RT_BEAMFORMEE_ENTRY {
-+	boolean is_used;
-+	boolean is_txbf;
-+	boolean is_sound;
-+	u16 aid; /*Used to construct AID field of NDPA packet.*/
-+	u16 mac_id; /*Used to Set Reg42C in IBSS mode. */
-+	u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
-+	u8 g_id; /*Used to fill Tx DESC*/
-+	u8 my_mac_addr[6];
-+	u8 mac_addr[6]; /*@Used to fill Reg6E4 to fill Mac address of CSI report frame.*/
-+	enum channel_width sound_bw; /*Sounding band_width*/
-+	u16 sound_period;
-+	enum beamforming_cap beamform_entry_cap;
-+	enum beamforming_entry_state beamform_entry_state;
-+	boolean is_beamforming_in_progress;
-+	/*@u8	log_seq;									// Move to _RT_BEAMFORMER_ENTRY*/
-+	/*@u16	log_retry_cnt:3;		// 0~4				// Move to _RT_BEAMFORMER_ENTRY*/
-+	/*@u16	LogSuccessCnt:2;		// 0~2				// Move to _RT_BEAMFORMER_ENTRY*/
-+	u16 log_status_fail_cnt : 5; /* @0~21 */
-+	u16 default_csi_cnt : 5; /* @0~21 */
-+	u8 csi_matrix[327];
-+	u16 csi_matrix_len;
-+	u8 num_of_sounding_dim;
-+	u8 comp_steering_num_of_bfer;
-+	u8 su_reg_index;
-+	/*@For MU-MIMO*/
-+	boolean is_mu_sta;
-+	u8 mu_reg_index;
-+	u8 gid_valid[8];
-+	u8 user_position[16];
-+};
-+
-+struct _RT_BEAMFORMER_ENTRY {
-+	boolean is_used;
-+	/*P_AID of BFer entry is probably not used*/
-+	u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
-+	u8 g_id;
-+	u8 my_mac_addr[6];
-+	u8 mac_addr[6];
-+	enum beamforming_cap beamform_entry_cap;
-+	u8 num_of_sounding_dim;
-+	u8 clock_reset_times; /*@Modified by Jeffery @2015-04-10*/
-+	u8 pre_log_seq; /*@Modified by Jeffery @2015-03-30*/
-+	u8 log_seq; /*@Modified by Jeffery @2014-10-29*/
-+	u16 log_retry_cnt : 3; /*@Modified by Jeffery @2014-10-29*/
-+	u16 log_success : 2; /*@Modified by Jeffery @2014-10-29*/
-+	u8 su_reg_index;
-+	/*@For MU-MIMO*/
-+	boolean is_mu_ap;
-+	u8 gid_valid[8];
-+	u8 user_position[16];
-+	u16 aid;
-+};
-+
-+struct _RT_SOUNDING_INFO {
-+	u8 sound_idx;
-+	enum channel_width sound_bw;
-+	enum sounding_mode sound_mode;
-+	u16 sound_period;
-+};
-+
-+struct _RT_BEAMFORMING_OID_INFO {
-+	u8 sound_oid_idx;
-+	enum channel_width sound_oid_bw;
-+	enum sounding_mode sound_oid_mode;
-+	u16 sound_oid_period;
-+};
-+
-+struct _RT_BEAMFORMING_INFO {
-+	enum beamforming_cap beamform_cap;
-+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM];
-+	struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM];
-+	struct _RT_BEAMFORM_STAINFO beamform_sta_info;
-+	u8 beamformee_cur_idx;
-+	struct phydm_timer_list beamforming_timer;
-+	struct phydm_timer_list mu_timer;
-+	struct _RT_SOUNDING_INFO sounding_info;
-+	struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info;
-+	struct _HAL_TXBF_INFO txbf_info;
-+	u8 sounding_sequence;
-+	u8 beamformee_su_cnt;
-+	u8 beamformer_su_cnt;
-+	u32 beamformee_su_reg_maping;
-+	u32 beamformer_su_reg_maping;
-+	/*@For MU-MINO*/
-+	u8 beamformee_mu_cnt;
-+	u8 beamformer_mu_cnt;
-+	u32 beamformee_mu_reg_maping;
-+	u8 mu_ap_index;
-+	boolean is_mu_sounding;
-+	u8 first_mu_bfee_index;
-+	boolean is_mu_sounding_in_progress;
-+	boolean dbg_disable_mu_tx;
-+	boolean apply_v_matrix;
-+	boolean snding3ss;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *source_adapter;
-+#endif
-+	/* @Control register */
-+	u32 reg_mu_tx_ctrl; /* @For USB/SDIO interfaces aync I/O */
-+	u8 tx_bf_data_rate;
-+	u8 last_usb_hub;
-+};
-+
-+void phydm_get_txbf_device_num(
-+	void *dm_void,
-+	u8 macid);
-+
-+struct _RT_NDPA_STA_INFO {
-+	u16 aid : 12;
-+	u16 feedback_type : 1;
-+	u16 nc_index : 3;
-+};
-+
-+enum phydm_acting_type {
-+	phydm_acting_as_ibss = 0,
-+	phydm_acting_as_ap = 1
-+};
-+
-+enum beamforming_cap
-+phydm_beamforming_get_entry_beam_cap_by_mac_id(
-+	void *dm_void,
-+	u8 mac_id);
-+
-+struct _RT_BEAMFORMEE_ENTRY *
-+phydm_beamforming_get_bfee_entry_by_addr(
-+	void *dm_void,
-+	u8 *RA,
-+	u8 *idx);
-+
-+struct _RT_BEAMFORMER_ENTRY *
-+phydm_beamforming_get_bfer_entry_by_addr(
-+	void *dm_void,
-+	u8 *TA,
-+	u8 *idx);
-+
-+void phydm_beamforming_notify(
-+	void *dm_void);
-+
-+boolean
-+phydm_acting_determine(
-+	void *dm_void,
-+	enum phydm_acting_type type);
-+
-+void beamforming_enter(void *dm_void, u16 sta_idx, u8 *my_mac_addr);
-+
-+void beamforming_leave(
-+	void *dm_void,
-+	u8 *RA);
-+
-+boolean
-+beamforming_start_fw(
-+	void *dm_void,
-+	u8 idx);
-+
-+void beamforming_check_sounding_success(
-+	void *dm_void,
-+	boolean status);
-+
-+void phydm_beamforming_end_sw(
-+	void *dm_void,
-+	boolean status);
-+
-+void beamforming_timer_callback(
-+	void *dm_void);
-+
-+void phydm_beamforming_init(
-+	void *dm_void);
-+
-+enum beamforming_cap
-+phydm_beamforming_get_beam_cap(
-+	void *dm_void,
-+	struct _RT_BEAMFORMING_INFO *beam_info);
-+
-+enum beamforming_cap
-+phydm_get_beamform_cap(
-+	void *dm_void);
-+
-+boolean
-+beamforming_control_v1(
-+	void *dm_void,
-+	u8 *RA,
-+	u8 AID,
-+	u8 mode,
-+	enum channel_width BW,
-+	u8 rate);
-+
-+boolean
-+phydm_beamforming_control_v2(
-+	void *dm_void,
-+	u8 idx,
-+	u8 mode,
-+	enum channel_width BW,
-+	u16 period);
-+
-+void phydm_beamforming_watchdog(
-+	void *dm_void);
-+
-+void beamforming_sw_timer_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct phydm_timer_list *timer
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	void *function_context
-+#endif
-+	);
-+
-+boolean
-+beamforming_send_ht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	enum channel_width BW,
-+	u8 q_idx);
-+
-+boolean
-+beamforming_send_vht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	u16 AID,
-+	enum channel_width BW,
-+	u8 q_idx);
-+
-+#else
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
-+#define beamforming_gid_paid(adapter, tcb)
-+#define phydm_acting_determine(dm, type) false
-+#define beamforming_enter(dm, sta_idx, my_mac_addr)
-+#define beamforming_leave(dm, RA)
-+#define beamforming_end_fw(dm)
-+#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true
-+#define beamforming_control_v2(dm, idx, mode, BW, period) true
-+#define phydm_beamforming_end_sw(dm, _status)
-+#define beamforming_timer_callback(dm)
-+#define phydm_beamforming_init(dm)
-+#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false
-+#define beamforming_watchdog(dm)
-+#define phydm_beamforming_watchdog(dm)
-+#endif /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/
-+#endif /*@#ifdef PHYDM_BEAMFORMING_SUPPORT*/
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_cck_pd.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_cck_pd.c
-new file mode 100644
-index 000000000000..c1c5be1dcd0f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_cck_pd.c
-@@ -0,0 +1,1906 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef PHYDM_SUPPORT_CCKPD
-+#ifdef PHYDM_COMPILE_CCKPD_TYPE1
-+void phydm_write_cck_pd_type1(void *dm_void, u8 cca_th)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "[%s] cck_cca_th=((0x%x))\n",
-+		  __func__, cca_th);
-+
-+	odm_write_1byte(dm, R_0xa0a, cca_th);
-+	cckpd_t->cur_cck_cca_thres = cca_th;
-+}
-+
-+void phydm_set_cckpd_lv_type1(void *dm_void, enum cckpd_lv lv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	u8 pd_th = 0;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
-+	PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
-+
-+	if (cckpd_t->cck_pd_lv == lv) {
-+		PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
-+		return;
-+	}
-+
-+	cckpd_t->cck_pd_lv = lv;
-+	cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
-+
-+	if (lv == CCK_PD_LV_4)
-+		pd_th = 0xed;
-+	else if (lv == CCK_PD_LV_3)
-+		pd_th = 0xdd;
-+	else if (lv == CCK_PD_LV_2)
-+		pd_th = 0xcd;
-+	else if (lv == CCK_PD_LV_1)
-+		pd_th = 0x83;
-+	else if (lv == CCK_PD_LV_0)
-+		pd_th = 0x40;
-+
-+	phydm_write_cck_pd_type1(dm, pd_th);
-+}
-+
-+void phydm_cckpd_type1(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	enum cckpd_lv lv = CCK_PD_LV_INIT;
-+	boolean is_update = true;
-+
-+	if (dm->is_linked) {
-+	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+		if (dm->rssi_min > 60) {
-+			lv = CCK_PD_LV_3;
-+		} else if (dm->rssi_min > 35) {
-+			lv = CCK_PD_LV_2;
-+		} else if (dm->rssi_min > 20) {
-+			if (cckpd_t->cck_fa_ma > 500)
-+				lv = CCK_PD_LV_2;
-+			else if (cckpd_t->cck_fa_ma < 250)
-+				lv = CCK_PD_LV_1;
-+			else
-+				is_update = false;
-+		} else { /*RSSI < 20*/
-+			lv = CCK_PD_LV_1;
-+		}
-+	#else /*ODM_AP*/
-+		if (dig_t->cur_ig_value > 0x32)
-+			lv = CCK_PD_LV_4;
-+		else if (dig_t->cur_ig_value > 0x2a)
-+			lv = CCK_PD_LV_3;
-+		else if (dig_t->cur_ig_value > 0x24)
-+			lv = CCK_PD_LV_2;
-+		else
-+			lv = CCK_PD_LV_1;
-+	#endif
-+	} else {
-+		if (cckpd_t->cck_fa_ma > 1000)
-+			lv = CCK_PD_LV_1;
-+		else if (cckpd_t->cck_fa_ma < 500)
-+			lv = CCK_PD_LV_0;
-+		else
-+			is_update = false;
-+	}
-+
-+	/*[Abnormal case] =================================================*/
-+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	/*@HP 22B LPS power consumption issue & [PCIE-1596]*/
-+	if (dm->hp_hw_id && dm->traffic_load == TRAFFIC_ULTRA_LOW) {
-+		lv = CCK_PD_LV_0;
-+		PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case1\n");
-+	} else if ((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) &&
-+	    cckpd_t->cck_fa_ma > 200 && dm->rssi_min <= 20) {
-+		lv = CCK_PD_LV_1;
-+		cckpd_t->cck_pd_lv = lv;
-+		phydm_write_cck_pd_type1(dm, 0xc3); /*@for ASUS OTA test*/
-+		is_update = false;
-+		PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case2\n");
-+	}
-+	#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+		#ifdef MCR_WIRELESS_EXTEND
-+		lv = CCK_PD_LV_2;
-+		cckpd_t->cck_pd_lv = lv;
-+		phydm_write_cck_pd_type1(dm, 0x43);
-+		is_update = false;
-+		PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case3\n");
-+		#endif
-+	#endif
-+	/*=================================================================*/
-+
-+	if (is_update)
-+		phydm_set_cckpd_lv_type1(dm, lv);
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "is_linked=%d, lv=%d, pd_th=0x%x\n\n",
-+		  dm->is_linked, cckpd_t->cck_pd_lv,
-+		  cckpd_t->cur_cck_cca_thres);
-+}
-+#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE1*/
-+
-+#ifdef PHYDM_COMPILE_CCKPD_TYPE2
-+void phydm_write_cck_pd_type2(void *dm_void, u8 cca_th, u8 cca_th_aaa)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "[%s] pd_th=0x%x, cs_ratio=0x%x\n",
-+		  __func__, cca_th, cca_th_aaa);
-+
-+	odm_set_bb_reg(dm, R_0xa08, 0x3f0000, cca_th);
-+	odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, cca_th_aaa);
-+	cckpd_t->cur_cck_cca_thres = cca_th;
-+	cckpd_t->cck_cca_th_aaa = cca_th_aaa;
-+}
-+
-+void phydm_set_cckpd_lv_type2(void *dm_void, enum cckpd_lv lv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	u8 pd_th = 0, cs_ratio = 0, cs_2r_offset = 0;
-+	u8 cck_n_rx = 1;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
-+	PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
-+
-+	/*@r_mrx & r_cca_mrc*/
-+	cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(18)) &&
-+		    odm_get_bb_reg(dm, R_0xa2c, BIT(22))) ? 2 : 1;
-+
-+	if (cckpd_t->cck_pd_lv == lv && cckpd_t->cck_n_rx == cck_n_rx) {
-+		PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
-+		return;
-+	}
-+
-+	cckpd_t->cck_n_rx = cck_n_rx;
-+	cckpd_t->cck_pd_lv = lv;
-+	cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
-+
-+	if (lv == CCK_PD_LV_4) {
-+		cs_ratio = cckpd_t->aaa_default + 8;
-+		cs_2r_offset = 5;
-+		pd_th = 0xd;
-+	} else if (lv == CCK_PD_LV_3) {
-+		cs_ratio = cckpd_t->aaa_default + 6;
-+		cs_2r_offset = 4;
-+		pd_th = 0xd;
-+	} else if (lv == CCK_PD_LV_2) {
-+		cs_ratio = cckpd_t->aaa_default + 4;
-+		cs_2r_offset = 3;
-+		pd_th = 0xd;
-+	} else if (lv == CCK_PD_LV_1) {
-+		cs_ratio = cckpd_t->aaa_default + 2;
-+		cs_2r_offset = 1;
-+		pd_th = 0x7;
-+	} else if (lv == CCK_PD_LV_0) {
-+		cs_ratio = cckpd_t->aaa_default;
-+		cs_2r_offset = 0;
-+		pd_th = 0x3;
-+	}
-+
-+	if (cckpd_t->cck_n_rx == 2) {
-+		if (cs_ratio >= cs_2r_offset)
-+			cs_ratio = cs_ratio - cs_2r_offset;
-+		else
-+			cs_ratio = 0;
-+	}
-+	phydm_write_cck_pd_type2(dm, pd_th, cs_ratio);
-+}
-+
-+#if 0
-+void phydm_set_cckpd_lv_type2_bcn(void *dm_void, enum cckpd_lv lv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	u8 pd_th = 0, cs_ratio = 0, cs_2r_offset = 0;
-+	u8 cck_n_rx = 1;
-+	u8 cs_ratio_pre = 0;
-+	u8 bcn_cnt = dm->phy_dbg_info.beacon_cnt_in_period; //BCN CNT
-+	u8 ofst = 0;
-+	u8 ofst_direc = 0; //0:+, 1:-
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
-+	PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
-+
-+	/*@r_mrx & r_cca_mrc*/
-+	cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(18)) &&
-+		    odm_get_bb_reg(dm, R_0xa2c, BIT(22))) ? 2 : 1;
-+	cs_ratio_pre = (u8)((odm_get_bb_reg(dm, R_0xaa8, 0x1f0000)));
-+	PHYDM_DBG(dm, DBG_CCKPD, "BCN: %d, pre CS ratio: 0x%x\n", bcn_cnt,
-+		  cs_ratio_pre);
-+
-+	if (cckpd_t->cck_pd_lv == lv && cckpd_t->cck_n_rx == cck_n_rx &&
-+	    (bcn_cnt >= 10 && bcn_cnt < 14)) {
-+		PHYDM_DBG(dm, DBG_CCKPD, "BCN ok, stay lv=%d, cs ratio=0x%x\n",
-+			  lv, cs_ratio_pre);
-+		return;
-+	}
-+
-+	cckpd_t->cck_n_rx = cck_n_rx;
-+	cckpd_t->cck_pd_lv = lv;
-+	cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
-+
-+	if (lv == CCK_PD_LV_4) {
-+		cs_ratio = cckpd_t->aaa_default + 8;
-+		cs_2r_offset = 5;
-+		pd_th = 0xd;
-+	} else if (lv == CCK_PD_LV_3) {
-+		cs_ratio = cckpd_t->aaa_default + 6;
-+		cs_2r_offset = 4;
-+		pd_th = 0xd;
-+	} else if (lv == CCK_PD_LV_2) {
-+		cs_ratio = cckpd_t->aaa_default + 4;
-+		cs_2r_offset = 3;
-+		pd_th = 0xd;
-+	} else if (lv == CCK_PD_LV_1) {
-+		cs_ratio = cckpd_t->aaa_default + 2;
-+		cs_2r_offset = 1;
-+		pd_th = 0x7;
-+	} else if (lv == CCK_PD_LV_0) {
-+		cs_ratio = cckpd_t->aaa_default;
-+		cs_2r_offset = 0;
-+		pd_th = 0x3;
-+	}
-+
-+	if (cckpd_t->cck_n_rx == 2) {
-+		if (cs_ratio >= cs_2r_offset)
-+			cs_ratio = cs_ratio - cs_2r_offset;
-+		else
-+			cs_ratio = 0;
-+	}
-+
-+	if (bcn_cnt >= 18) {
-+		ofst_direc = 0;
-+		ofst = 0x2;
-+	} else if (bcn_cnt >= 14) {
-+		ofst_direc = 0;
-+		ofst = 0x1;
-+	} else if (bcn_cnt >= 10) {
-+		ofst_direc = 0;
-+		ofst = 0x0;
-+	} else if (bcn_cnt >= 5) {
-+		ofst_direc = 1;
-+		ofst = 0x3;
-+	} else {
-+		ofst_direc = 1;
-+		ofst = 0x4;
-+	}
-+	PHYDM_DBG(dm, DBG_CCKPD, "bcn:(%d), ofst:(%s%d)\n", bcn_cnt,
-+		  ((ofst_direc) ? "-" : "+"), ofst);
-+
-+	if (ofst_direc == 0)
-+		cs_ratio = cs_ratio + ofst;
-+	else
-+		cs_ratio = cs_ratio - ofst;
-+
-+	if (cs_ratio == cs_ratio_pre) {
-+		PHYDM_DBG(dm, DBG_CCKPD, "Same cs ratio, lv=%d cs_ratio=0x%x\n",
-+			  lv, cs_ratio);
-+		return;
-+	}
-+	phydm_write_cck_pd_type2(dm, pd_th, cs_ratio);
-+}
-+#endif
-+
-+void phydm_cckpd_type2(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	enum cckpd_lv lv = CCK_PD_LV_INIT;
-+	u8 igi = dig_t->cur_ig_value;
-+	u8 rssi_min = dm->rssi_min;
-+	boolean is_update = true;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
-+
-+	if (dm->is_linked) {
-+		if (igi > 0x38 && rssi_min > 32) {
-+			lv = CCK_PD_LV_4;
-+		} else if (igi > 0x2a && rssi_min > 32) {
-+			lv = CCK_PD_LV_3;
-+		} else if (igi > 0x24 || (rssi_min > 24 && rssi_min <= 30)) {
-+			lv = CCK_PD_LV_2;
-+		} else if (igi <= 0x24 || rssi_min < 22) {
-+			if (cckpd_t->cck_fa_ma > 1000) {
-+				lv = CCK_PD_LV_1;
-+			} else if (cckpd_t->cck_fa_ma < 500) {
-+				lv = CCK_PD_LV_0;
-+			} else {
-+				is_update = false;
-+			}
-+		} else {
-+			is_update = false;
-+		}
-+	} else {
-+		if (cckpd_t->cck_fa_ma > 1000) {
-+			lv = CCK_PD_LV_1;
-+		} else if (cckpd_t->cck_fa_ma < 500) {
-+			lv = CCK_PD_LV_0;
-+		} else {
-+			is_update = false;
-+		}
-+	}
-+
-+	/*[Abnormal case] =================================================*/
-+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	/*@21C Miracast lag issue & [PCIE-3298]*/
-+	if (dm->support_ic_type & ODM_RTL8821C && rssi_min > 60) {
-+		lv = CCK_PD_LV_4;
-+		cckpd_t->cck_pd_lv = lv;
-+		phydm_write_cck_pd_type2(dm, 0x1d, (cckpd_t->aaa_default + 8));
-+		is_update = false;
-+		PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case1\n");
-+	}
-+	#endif
-+	/*=================================================================*/
-+
-+	if (is_update) {
-+		phydm_set_cckpd_lv_type2(dm, lv);
-+	}
-+
-+	PHYDM_DBG(dm, DBG_CCKPD,
-+		  "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x\n\n",
-+		  dm->is_linked, cckpd_t->cck_pd_lv, cckpd_t->cck_n_rx,
-+		  cckpd_t->cck_cca_th_aaa, cckpd_t->cur_cck_cca_thres);
-+}
-+#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE2*/
-+
-+#ifdef PHYDM_COMPILE_CCKPD_TYPE3
-+void phydm_write_cck_pd_type3(void *dm_void, u8 pd_th, u8 cs_ratio,
-+			      enum cckpd_mode mode)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD,
-+		  "[%s] mode=%d, pd_th=0x%x, cs_ratio=0x%x\n", __func__,
-+		  mode, pd_th, cs_ratio);
-+
-+	switch (mode) {
-+	case CCK_BW20_1R: /*RFBW20_1R*/
-+	{
-+		cckpd_t->cur_cck_pd_20m_1r = pd_th;
-+		cckpd_t->cur_cck_cs_ratio_20m_1r = cs_ratio;
-+		odm_set_bb_reg(dm, R_0xac8, 0xff, pd_th);
-+		odm_set_bb_reg(dm, R_0xad0, 0x1f, cs_ratio);
-+	} break;
-+	case CCK_BW20_2R: /*RFBW20_2R*/
-+	{
-+		cckpd_t->cur_cck_pd_20m_2r = pd_th;
-+		cckpd_t->cur_cck_cs_ratio_20m_2r = cs_ratio;
-+		odm_set_bb_reg(dm, R_0xac8, 0xff00, pd_th);
-+		odm_set_bb_reg(dm, R_0xad0, 0x3e0, cs_ratio);
-+	} break;
-+	case CCK_BW40_1R: /*RFBW40_1R*/
-+	{
-+		cckpd_t->cur_cck_pd_40m_1r = pd_th;
-+		cckpd_t->cur_cck_cs_ratio_40m_1r = cs_ratio;
-+		odm_set_bb_reg(dm, R_0xacc, 0xff, pd_th);
-+		odm_set_bb_reg(dm, R_0xad0, 0x1f00000, cs_ratio);
-+	} break;
-+	case CCK_BW40_2R: /*RFBW40_2R*/
-+	{
-+		cckpd_t->cur_cck_pd_40m_2r = pd_th;
-+		cckpd_t->cur_cck_cs_ratio_40m_2r = cs_ratio;
-+		odm_set_bb_reg(dm, R_0xacc, 0xff00, pd_th);
-+		odm_set_bb_reg(dm, R_0xad0, 0x3e000000, cs_ratio);
-+	} break;
-+
-+	default:
-+		/*@pr_debug("[%s] warning!\n", __func__);*/
-+		break;
-+	}
-+}
-+
-+void phydm_set_cckpd_lv_type3(void *dm_void, enum cckpd_lv lv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	enum cckpd_mode cck_mode = CCK_BW20_2R;
-+	enum channel_width cck_bw = CHANNEL_WIDTH_20;
-+	u8 cck_n_rx = 1;
-+	u8 pd_th;
-+	u8 cs_ratio;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
-+	PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
-+
-+	/*[Check Nrx]*/
-+	cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(17))) ? 2 : 1;
-+
-+	/*[Check BW]*/
-+	if (odm_get_bb_reg(dm, R_0x800, BIT(0)))
-+		cck_bw = CHANNEL_WIDTH_40;
-+	else
-+		cck_bw = CHANNEL_WIDTH_20;
-+
-+	/*[Check LV]*/
-+	if (cckpd_t->cck_pd_lv == lv &&
-+	    cckpd_t->cck_n_rx == cck_n_rx &&
-+	    cckpd_t->cck_bw == cck_bw) {
-+		PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
-+		return;
-+	}
-+
-+	cckpd_t->cck_bw = cck_bw;
-+	cckpd_t->cck_n_rx = cck_n_rx;
-+	cckpd_t->cck_pd_lv = lv;
-+	cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
-+
-+	if (cck_n_rx == 2) {
-+		if (cck_bw == CHANNEL_WIDTH_20) {
-+			pd_th = cckpd_t->cck_pd_20m_2r;
-+			cs_ratio = cckpd_t->cck_cs_ratio_20m_2r;
-+			cck_mode = CCK_BW20_2R;
-+		} else {
-+			pd_th = cckpd_t->cck_pd_40m_2r;
-+			cs_ratio = cckpd_t->cck_cs_ratio_40m_2r;
-+			cck_mode = CCK_BW40_2R;
-+		}
-+	} else {
-+		if (cck_bw == CHANNEL_WIDTH_20) {
-+			pd_th = cckpd_t->cck_pd_20m_1r;
-+			cs_ratio = cckpd_t->cck_cs_ratio_20m_1r;
-+			cck_mode = CCK_BW20_1R;
-+		} else {
-+			pd_th = cckpd_t->cck_pd_40m_1r;
-+			cs_ratio = cckpd_t->cck_cs_ratio_40m_1r;
-+			cck_mode = CCK_BW40_1R;
-+		}
-+	}
-+
-+	if (lv == CCK_PD_LV_4) {
-+		if (cck_n_rx == 2) {
-+			pd_th += 4;
-+			cs_ratio += 2;
-+		} else {
-+			pd_th += 4;
-+			cs_ratio += 3;
-+		}
-+	} else if (lv == CCK_PD_LV_3) {
-+		if (cck_n_rx == 2) {
-+			pd_th += 3;
-+			cs_ratio += 1;
-+		} else {
-+			pd_th += 3;
-+			cs_ratio += 2;
-+		}
-+	} else if (lv == CCK_PD_LV_2) {
-+		pd_th += 2;
-+		cs_ratio += 1;
-+	} else if (lv == CCK_PD_LV_1) {
-+		pd_th += 1;
-+		cs_ratio += 1;
-+	}
-+
-+	phydm_write_cck_pd_type3(dm, pd_th, cs_ratio, cck_mode);
-+}
-+
-+void phydm_cckpd_type3(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	enum cckpd_lv lv = CCK_PD_LV_INIT;
-+	u8 igi = dm->dm_dig_table.cur_ig_value;
-+	boolean is_update = true;
-+	u8 pd_th = 0;
-+	u8 cs_ratio = 0;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
-+
-+	if (dm->is_linked) {
-+		if (igi > 0x38 && dm->rssi_min > 32) {
-+			lv = CCK_PD_LV_4;
-+		} else if ((igi > 0x2a) && (dm->rssi_min > 32)) {
-+			lv = CCK_PD_LV_3;
-+		} else if ((igi > 0x24) ||
-+			   (dm->rssi_min > 24 && dm->rssi_min <= 30)) {
-+			lv = CCK_PD_LV_2;
-+		} else if ((igi <= 0x24) || (dm->rssi_min < 22)) {
-+			if (cckpd_t->cck_fa_ma > 1000)
-+				lv = CCK_PD_LV_1;
-+			else if (cckpd_t->cck_fa_ma < 500)
-+				lv = CCK_PD_LV_0;
-+			else
-+				is_update = false;
-+		}
-+	} else {
-+		if (cckpd_t->cck_fa_ma > 1000)
-+			lv = CCK_PD_LV_1;
-+		else if (cckpd_t->cck_fa_ma < 500)
-+			lv = CCK_PD_LV_0;
-+		else
-+			is_update = false;
-+	}
-+
-+	if (is_update)
-+		phydm_set_cckpd_lv_type3(dm, lv);
-+
-+	if (cckpd_t->cck_n_rx == 2) {
-+		if (cckpd_t->cck_bw == CHANNEL_WIDTH_20) {
-+			pd_th = cckpd_t->cur_cck_pd_20m_2r;
-+			cs_ratio = cckpd_t->cur_cck_cs_ratio_20m_2r;
-+		} else {
-+			pd_th = cckpd_t->cur_cck_pd_40m_2r;
-+			cs_ratio = cckpd_t->cur_cck_cs_ratio_40m_2r;
-+		}
-+	} else {
-+		if (cckpd_t->cck_bw == CHANNEL_WIDTH_20) {
-+			pd_th = cckpd_t->cur_cck_pd_20m_1r;
-+			cs_ratio = cckpd_t->cur_cck_cs_ratio_20m_1r;
-+		} else {
-+			pd_th = cckpd_t->cur_cck_pd_40m_1r;
-+			cs_ratio = cckpd_t->cur_cck_cs_ratio_40m_1r;
-+		}
-+	}
-+	PHYDM_DBG(dm, DBG_CCKPD,
-+		  "[%dR][%dM] is_linked=%d, lv=%d, cs_ratio=0x%x, pd_th=0x%x\n\n",
-+		  cckpd_t->cck_n_rx, 20 << cckpd_t->cck_bw, dm->is_linked,
-+		  cckpd_t->cck_pd_lv, cs_ratio, pd_th);
-+}
-+
-+void phydm_cck_pd_init_type3(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	u32 reg_tmp = 0;
-+
-+	/*Get Default value*/
-+	cckpd_t->cck_pd_20m_1r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff);
-+	cckpd_t->cck_pd_20m_2r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff00);
-+	cckpd_t->cck_pd_40m_1r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff);
-+	cckpd_t->cck_pd_40m_2r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff00);
-+
-+	reg_tmp = odm_get_bb_reg(dm, R_0xad0, MASKDWORD);
-+	cckpd_t->cck_cs_ratio_20m_1r = (u8)(reg_tmp & 0x1f);
-+	cckpd_t->cck_cs_ratio_20m_2r = (u8)((reg_tmp & 0x3e0) >> 5);
-+	cckpd_t->cck_cs_ratio_40m_1r = (u8)((reg_tmp & 0x1f00000) >> 20);
-+	cckpd_t->cck_cs_ratio_40m_2r = (u8)((reg_tmp & 0x3e000000) >> 25);
-+}
-+#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE3*/
-+
-+#ifdef PHYDM_COMPILE_CCKPD_TYPE4
-+void phydm_write_cck_pd_type4(void *dm_void, enum cckpd_lv lv,
-+			      enum cckpd_mode mode)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	u32 val = 0;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "write CCK CCA parameters(CS_ratio & PD)\n");
-+	switch (mode) {
-+	case CCK_BW20_1R: /*RFBW20_1R*/
-+	{
-+		val = cckpd_t->cckpd_jgr3[0][0][0][lv];
-+		odm_set_bb_reg(dm, R_0x1ac8, 0xff, val);
-+		val = cckpd_t->cckpd_jgr3[0][0][1][lv];
-+		odm_set_bb_reg(dm, R_0x1ad0, 0x1f, val);
-+	} break;
-+	case CCK_BW40_1R: /*RFBW40_1R*/
-+	{
-+		val = cckpd_t->cckpd_jgr3[1][0][0][lv];
-+		odm_set_bb_reg(dm, R_0x1acc, 0xff, val);
-+		val = cckpd_t->cckpd_jgr3[1][0][1][lv];
-+		odm_set_bb_reg(dm, R_0x1ad0, 0x01F00000, val);
-+	} break;
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	case CCK_BW20_2R: /*RFBW20_2R*/
-+	{
-+		val = cckpd_t->cckpd_jgr3[0][1][0][lv];
-+		odm_set_bb_reg(dm, R_0x1ac8, 0xff00, val);
-+		val = cckpd_t->cckpd_jgr3[0][1][1][lv];
-+		odm_set_bb_reg(dm, R_0x1ad0, 0x3e0, val);
-+	} break;
-+	case CCK_BW40_2R: /*RFBW40_2R*/
-+	{
-+		val = cckpd_t->cckpd_jgr3[1][1][0][lv];
-+		odm_set_bb_reg(dm, R_0x1acc, 0xff00, val);
-+		val = cckpd_t->cckpd_jgr3[1][1][1][lv];
-+		odm_set_bb_reg(dm, R_0x1ad0, 0x3E000000, val);
-+	} break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	case CCK_BW20_3R: /*RFBW20_3R*/
-+	{
-+		val = cckpd_t->cckpd_jgr3[0][2][0][lv];
-+		odm_set_bb_reg(dm, R_0x1ac8, 0xff0000, val);
-+		val = cckpd_t->cckpd_jgr3[0][2][1][lv];
-+		odm_set_bb_reg(dm, R_0x1ad0, 0x7c00, val);
-+	} break;
-+	case CCK_BW40_3R: /*RFBW40_3R*/
-+	{
-+		val = cckpd_t->cckpd_jgr3[1][2][0][lv];
-+		odm_set_bb_reg(dm, R_0x1acc, 0xff0000, val);
-+		val = cckpd_t->cckpd_jgr3[1][2][1][lv] & 0x3;
-+		odm_set_bb_reg(dm, R_0x1ad0, 0xC0000000, val);
-+		val = (cckpd_t->cckpd_jgr3[1][2][1][lv] & 0x1c) >> 2;
-+		odm_set_bb_reg(dm, R_0x1ad4, 0x7, val);
-+	} break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	case CCK_BW20_4R: /*RFBW20_4R*/
-+	{
-+		val = cckpd_t->cckpd_jgr3[0][3][0][lv];
-+		odm_set_bb_reg(dm, R_0x1ac8, 0xff000000, val);
-+		val = cckpd_t->cckpd_jgr3[0][3][1][lv];
-+		odm_set_bb_reg(dm, R_0x1ad0, 0xF8000, val);
-+	} break;
-+	case CCK_BW40_4R: /*RFBW40_4R*/
-+	{
-+		val = cckpd_t->cckpd_jgr3[1][3][0][lv];
-+		odm_set_bb_reg(dm, R_0x1acc, 0xff000000, val);
-+		val = cckpd_t->cckpd_jgr3[1][3][1][lv];
-+		odm_set_bb_reg(dm, R_0x1ad4, 0xf8, val);
-+	} break;
-+	#endif
-+	default:
-+		/*@pr_debug("[%s] warning!\n", __func__);*/
-+		break;
-+	}
-+}
-+
-+void phydm_set_cck_pd_lv_type4(void *dm_void, enum cckpd_lv lv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	enum cckpd_mode cck_mode = CCK_BW20_2R;
-+	enum channel_width cck_bw = CHANNEL_WIDTH_20;
-+	u8 cck_n_rx = 0;
-+	u32 val = 0;
-+	/*u32 val_dbg = 0;*/
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
-+	PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
-+
-+	/*[Check Nrx]*/
-+	cck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
-+
-+	/*[Check BW]*/
-+	val = odm_get_bb_reg(dm, R_0x9b0, 0xc);
-+	if (val == 0)
-+		cck_bw = CHANNEL_WIDTH_20;
-+	else if (val == 1)
-+		cck_bw = CHANNEL_WIDTH_40;
-+	else
-+		cck_bw = CHANNEL_WIDTH_80;
-+
-+	/*[Check LV]*/
-+	if (cckpd_t->cck_pd_lv == lv &&
-+	    cckpd_t->cck_n_rx == cck_n_rx &&
-+	    cckpd_t->cck_bw == cck_bw) {
-+		PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
-+		return;
-+	}
-+
-+	cckpd_t->cck_bw = cck_bw;
-+	cckpd_t->cck_n_rx = cck_n_rx;
-+	cckpd_t->cck_pd_lv = lv;
-+	cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
-+
-+	switch (cck_n_rx) {
-+	case 1: /*1R*/
-+	{
-+		if (cck_bw == CHANNEL_WIDTH_20)
-+			cck_mode = CCK_BW20_1R;
-+		else if (cck_bw == CHANNEL_WIDTH_40)
-+			cck_mode = CCK_BW40_1R;
-+	} break;
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	case 2: /*2R*/
-+	{
-+		if (cck_bw == CHANNEL_WIDTH_20)
-+			cck_mode = CCK_BW20_2R;
-+		else if (cck_bw == CHANNEL_WIDTH_40)
-+			cck_mode = CCK_BW40_2R;
-+	} break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	case 3: /*3R*/
-+	{
-+		if (cck_bw == CHANNEL_WIDTH_20)
-+			cck_mode = CCK_BW20_3R;
-+		else if (cck_bw == CHANNEL_WIDTH_40)
-+			cck_mode = CCK_BW40_3R;
-+	} break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	case 4: /*4R*/
-+	{
-+		if (cck_bw == CHANNEL_WIDTH_20)
-+			cck_mode = CCK_BW20_4R;
-+		else if (cck_bw == CHANNEL_WIDTH_40)
-+			cck_mode = CCK_BW40_4R;
-+	} break;
-+	#endif
-+	default:
-+		/*@pr_debug("[%s] warning!\n", __func__);*/
-+		break;
-+	}
-+	phydm_write_cck_pd_type4(dm, lv, cck_mode);
-+}
-+
-+void phydm_read_cckpd_para_type4(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	u8 bw = 0; /*r_RX_RF_BW*/
-+	u8 n_rx = 0;
-+	u8 curr_cck_pd_t[2][4][2];
-+	u32 reg0 = 0;
-+	u32 reg1 = 0;
-+	u32 reg2 = 0;
-+	u32 reg3 = 0;
-+
-+	if (!(dm->debug_components & DBG_CCKPD))
-+		return;
-+
-+	bw = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc);
-+	n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
-+
-+	reg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD);
-+	reg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD);
-+	reg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD);
-+	reg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD);
-+	curr_cck_pd_t[0][0][0] = (u8)(reg0 & 0x000000ff);
-+	curr_cck_pd_t[1][0][0] = (u8)(reg1 & 0x000000ff);
-+	curr_cck_pd_t[0][0][1] = (u8)(reg2 & 0x0000001f);
-+	curr_cck_pd_t[1][0][1] = (u8)((reg2 & 0x01f00000) >> 20);
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
-+		curr_cck_pd_t[0][1][0] = (u8)((reg0 & 0x0000ff00) >> 8);
-+		curr_cck_pd_t[1][1][0] = (u8)((reg1 & 0x0000ff00) >> 8);
-+		curr_cck_pd_t[0][1][1] = (u8)((reg2 & 0x000003E0) >> 5);
-+		curr_cck_pd_t[1][1][1] = (u8)((reg2 & 0x3E000000) >> 25);
-+	}
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {
-+		curr_cck_pd_t[0][2][0] = (u8)((reg0 & 0x00ff0000) >> 16);
-+		curr_cck_pd_t[1][2][0] = (u8)((reg1 & 0x00ff0000) >> 16);
-+		curr_cck_pd_t[0][2][1] = (u8)((reg2 & 0x00007C00) >> 10);
-+		curr_cck_pd_t[1][2][1] = (u8)((reg2 & 0xC0000000) >> 30) |
-+					 (u8)((reg3 & 0x00000007) << 2);
-+	}
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
-+		curr_cck_pd_t[0][3][0] = (u8)((reg0 & 0xff000000) >> 24);
-+		curr_cck_pd_t[1][3][0] = (u8)((reg1 & 0xff000000) >> 24);
-+		curr_cck_pd_t[0][3][1] = (u8)((reg2 & 0x000F8000) >> 15);
-+		curr_cck_pd_t[1][3][1] = (u8)((reg3 & 0x000000F8) >> 3);
-+	}
-+	#endif
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "bw=%dM, Nrx=%d\n", 20 << bw, n_rx);
-+	PHYDM_DBG(dm, DBG_CCKPD, "lv=%d, readback CS_th=0x%x, PD th=0x%x\n",
-+		  cckpd_t->cck_pd_lv,
-+		  curr_cck_pd_t[bw][n_rx - 1][1],
-+		  curr_cck_pd_t[bw][n_rx - 1][0]);
-+}
-+
-+void phydm_cckpd_type4(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	u8 igi = dm->dm_dig_table.cur_ig_value;
-+	enum cckpd_lv lv = 0;
-+	boolean is_update = true;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
-+
-+	if (dm->is_linked) {
-+		PHYDM_DBG(dm, DBG_CCKPD, "Linked!!!\n");
-+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+		if (dm->rssi_min > 40) {
-+			lv = CCK_PD_LV_4;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
-+		} else if (dm->rssi_min > 32) {
-+			lv = CCK_PD_LV_3;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
-+		} else if (dm->rssi_min > 24) {
-+			lv = CCK_PD_LV_2;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
-+		} else {
-+			if (cckpd_t->cck_fa_ma > 1000) {
-+				lv = CCK_PD_LV_1;
-+				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-1\n");
-+			} else if (cckpd_t->cck_fa_ma < 500) {
-+				lv = CCK_PD_LV_0;
-+				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-2\n");
-+			} else {
-+				is_update = false;
-+				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-3\n");
-+			}
-+		}
-+		#else /*ODM_AP*/
-+		if (igi > 0x38 && dm->rssi_min > 32) {
-+			lv = CCK_PD_LV_4;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
-+		} else if (igi > 0x2a && dm->rssi_min > 32) {
-+			lv = CCK_PD_LV_3;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
-+		} else if (igi > 0x24 || dm->rssi_min > 24) {
-+			lv = CCK_PD_LV_2;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
-+		} else {
-+			if (cckpd_t->cck_fa_ma > 1000) {
-+				lv = CCK_PD_LV_1;
-+				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-1\n");
-+			} else if (cckpd_t->cck_fa_ma < 500) {
-+				lv = CCK_PD_LV_0;
-+				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-2\n");
-+			} else {
-+				is_update = false;
-+				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-3\n");
-+			}
-+		}
-+		#endif
-+	} else {
-+		PHYDM_DBG(dm, DBG_CCKPD, "UnLinked!!!\n");
-+		if (cckpd_t->cck_fa_ma > 1000) {
-+			lv = CCK_PD_LV_1;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
-+		} else if (cckpd_t->cck_fa_ma < 500) {
-+			lv = CCK_PD_LV_0;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
-+		} else {
-+			is_update = false;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
-+		}
-+	}
-+
-+	if (is_update) {
-+		phydm_set_cck_pd_lv_type4(dm, lv);
-+
-+		PHYDM_DBG(dm, DBG_CCKPD, "setting CS_th = 0x%x, PD th = 0x%x\n",
-+			  cckpd_t->cckpd_jgr3[cckpd_t->cck_bw]
-+			  [cckpd_t->cck_n_rx - 1][1][lv],
-+			  cckpd_t->cckpd_jgr3[cckpd_t->cck_bw]
-+			  [cckpd_t->cck_n_rx - 1][0][lv]);
-+	}
-+	phydm_read_cckpd_para_type4(dm);
-+}
-+
-+void phydm_cck_pd_init_type4(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	u32 reg0 = 0;
-+	u32 reg1 = 0;
-+	u32 reg2 = 0;
-+	u32 reg3 = 0;
-+	u8 pw_step = 0;
-+	u8 cs_step = 0;
-+	u8 cck_bw = 0; /*r_RX_RF_BW*/
-+	u8 cck_n_rx = 0;
-+	u8 val = 0;
-+	u8 i = 0;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__);
-+
-+	#if 0
-+	/*@
-+	 *cckpd_t[0][0][0][0] =  1ac8[7:0]	r_PD_lim_RFBW20_1R
-+	 *cckpd_t[0][1][0][0] =  1ac8[15:8]	r_PD_lim_RFBW20_2R
-+	 *cckpd_t[0][2][0][0] =  1ac8[23:16]	r_PD_lim_RFBW20_3R
-+	 *cckpd_t[0][3][0][0] =  1ac8[31:24]	r_PD_lim_RFBW20_4R
-+	 *cckpd_t[1][0][0][0] =  1acc[7:0]	r_PD_lim_RFBW40_1R
-+	 *cckpd_t[1][1][0][0] =  1acc[15:8]	r_PD_lim_RFBW40_2R
-+	 *cckpd_t[1][2][0][0] =  1acc[23:16]	r_PD_lim_RFBW40_3R
-+	 *cckpd_t[1][3][0][0] =  1acc[31:24]	r_PD_lim_RFBW40_4R
-+	 *
-+	 *
-+	 *cckpd_t[0][0][1][0] =  1ad0[4:0]	r_CS_ratio_RFBW20_1R[4:0]
-+	 *cckpd_t[0][1][1][0] =  1ad0[9:5]	r_CS_ratio_RFBW20_2R[4:0]
-+	 *cckpd_t[0][2][1][0] =  1ad0[14:10]	r_CS_ratio_RFBW20_3R[4:0]
-+	 *cckpd_t[0][3][1][0] =  1ad0[19:15]	r_CS_ratio_RFBW20_4R[4:0]
-+	 *cckpd_t[1][0][1][0] =  1ad0[24:20]	r_CS_ratio_RFBW40_1R[4:0]
-+	 *cckpd_t[1][1][1][0] =  1ad0[29:25]	r_CS_ratio_RFBW40_2R[4:0]
-+	 *cckpd_t[1][2][1][0] =  1ad0[31:30]	r_CS_ratio_RFBW40_3R[1:0]
-+	 *			 1ad4[2:0]	r_CS_ratio_RFBW40_3R[4:2]
-+	 *cckpd_t[1][3][1][0] =  1ad4[7:3]	r_CS_ratio_RFBW40_4R[4:0]
-+	 */
-+	#endif
-+	/*[Check Nrx]*/
-+	cck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
-+
-+	/*[Check BW]*/
-+	val = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc);
-+	if (val == 0)
-+		cck_bw = CHANNEL_WIDTH_20;
-+	else if (val == 1)
-+		cck_bw = CHANNEL_WIDTH_40;
-+	else
-+		cck_bw = CHANNEL_WIDTH_80;
-+
-+	cckpd_t->cck_bw = cck_bw;
-+	cckpd_t->cck_n_rx = cck_n_rx;
-+	reg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD);
-+	reg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD);
-+	reg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD);
-+	reg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD);
-+
-+	for (i = 0 ; i < CCK_PD_LV_MAX ; i++) {
-+		pw_step = i * 2;
-+		cs_step = i * 2;
-+
-+		#if (RTL8197G_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8197G) {
-+			pw_step = i;
-+			cs_step = i;
-+			if (i > CCK_PD_LV_3) {
-+				pw_step = 3;
-+				cs_step = 3;
-+			}
-+		}
-+		#endif
-+
-+		#if (RTL8822C_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8822C) {
-+			if (i == CCK_PD_LV_1) {
-+				pw_step = 9; /*IGI-19.2:0x11=d'17*/
-+				cs_step = 0;
-+			} else if (i == CCK_PD_LV_2) {
-+				pw_step = 12; /*IGI-15.5:0x14=d'20*/
-+				cs_step = 1;
-+			} else if (i == CCK_PD_LV_3) {
-+				pw_step = 14; /*IGI-14:0x16=d'22*/
-+				cs_step = 1;
-+			} else if (i == CCK_PD_LV_4) {
-+				pw_step = 17; /*IGI-12:0x19=d'25*/
-+				cs_step = 1;
-+			}
-+		}
-+		#endif
-+		
-+		val = (u8)(reg0 & 0x000000ff) + pw_step;
-+		PHYDM_DBG(dm, DBG_CCKPD, "lvl %d val = %x\n\n", i, val);
-+		cckpd_t->cckpd_jgr3[0][0][0][i] = val;
-+
-+		val = (u8)(reg1 & 0x000000ff) + pw_step;
-+		cckpd_t->cckpd_jgr3[1][0][0][i] = val;
-+
-+		val = (u8)(reg2 & 0x0000001f) + cs_step;
-+		cckpd_t->cckpd_jgr3[0][0][1][i] = val;
-+
-+		val = (u8)((reg2 & 0x01f00000) >> 20) + cs_step;
-+		cckpd_t->cckpd_jgr3[1][0][1][i] = val;
-+
-+		#ifdef PHYDM_COMPILE_ABOVE_2SS
-+		if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
-+			val = (u8)((reg0 & 0x0000ff00) >> 8) + pw_step;
-+			cckpd_t->cckpd_jgr3[0][1][0][i] = val;
-+
-+			val = (u8)((reg1 & 0x0000ff00) >> 8) + pw_step;
-+			cckpd_t->cckpd_jgr3[1][1][0][i] = val;
-+
-+			val = (u8)((reg2 & 0x000003e0) >> 5) + cs_step;
-+			cckpd_t->cckpd_jgr3[0][1][1][i] = val;
-+
-+			val = (u8)((reg2 & 0x3e000000) >> 25) + cs_step;
-+			cckpd_t->cckpd_jgr3[1][1][1][i] = val;
-+		}
-+		#endif
-+
-+		#ifdef PHYDM_COMPILE_ABOVE_3SS
-+		if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {
-+			val = (u8)((reg0 & 0x00ff0000) >> 16) + pw_step;
-+			cckpd_t->cckpd_jgr3[0][2][0][i] = val;
-+
-+			val = (u8)((reg1 & 0x00ff0000) >> 16) + pw_step;
-+			cckpd_t->cckpd_jgr3[1][2][0][i] = val;
-+			val = (u8)((reg2 & 0x00007c00) >> 10) + cs_step;
-+			cckpd_t->cckpd_jgr3[0][2][1][i] = val;
-+			val = (u8)(((reg2 & 0xc0000000) >> 30) |
-+			      ((reg3 & 0x7) << 3)) + cs_step;
-+			cckpd_t->cckpd_jgr3[1][2][1][i] = val;
-+		}
-+		#endif
-+
-+		#ifdef PHYDM_COMPILE_ABOVE_4SS
-+		if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
-+			val = (u8)((reg0 & 0xff000000) >> 24) + pw_step;
-+			cckpd_t->cckpd_jgr3[0][3][0][i] = val;
-+
-+			val = (u8)((reg1 & 0xff000000) >> 24) + pw_step;
-+			cckpd_t->cckpd_jgr3[1][3][0][i] = val;
-+
-+			val = (u8)((reg2 & 0x000f8000) >> 15) + cs_step;
-+			cckpd_t->cckpd_jgr3[0][3][1][i] = val;
-+
-+			val = (u8)((reg3 & 0x000000f8) >> 3) + cs_step;
-+			cckpd_t->cckpd_jgr3[1][3][1][i] = val;
-+		}
-+		#endif
-+	}
-+}
-+
-+void phydm_invalid_cckpd_type4(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	u8 val = 0;
-+	u8 i = 0;
-+	u8 j = 0;
-+	u8 k = 0;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__);
-+
-+	for (i = 0; i < CCK_PD_LV_MAX; i++) {
-+		for (j = 0; j < 2; j++) {
-+			for (k = 0; k < dm->num_rf_path; k++) {
-+				val = cckpd_t->cckpd_jgr3[j][k][1][i];
-+				if (val == INVALID_CS_RATIO_0)
-+					cckpd_t->cckpd_jgr3[j][k][1][i] = 0x1c;
-+				else if (val == INVALID_CS_RATIO_1)
-+					cckpd_t->cckpd_jgr3[j][k][1][i] = 0x1e;
-+				else if (val > MAXVALID_CS_RATIO)
-+					cckpd_t->cckpd_jgr3[j][k][1][i] =
-+					MAXVALID_CS_RATIO;
-+			}
-+		}
-+
-+		#if (RTL8198F_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8198F) {
-+			val = cckpd_t->cckpd_jgr3[0][3][1][i];
-+			if (i == CCK_PD_LV_1 && val > 0x10)
-+				cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10;
-+			else if (i == CCK_PD_LV_2 && val > 0x10)
-+				cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10;
-+			else if (i == CCK_PD_LV_3 && val > 0x10)
-+				cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10;
-+			else if (i == CCK_PD_LV_4 && val > 0x10)
-+				cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10;
-+			val = cckpd_t->cckpd_jgr3[1][3][1][i];
-+			if (i == CCK_PD_LV_1 && val > 0xF)
-+				cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF;
-+			else if (i == CCK_PD_LV_2 && val > 0xF)
-+				cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF;
-+			else if (i == CCK_PD_LV_3 && val > 0xF)
-+				cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF;
-+			else if (i == CCK_PD_LV_4 && val > 0xF)
-+				cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF;
-+		}
-+		#endif
-+	}
-+}
-+
-+#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE4*/
-+
-+
-+#ifdef PHYDM_COMPILE_CCKPD_TYPE5
-+void phydm_write_cck_pd_type5(void *dm_void, enum cckpd_lv lv,
-+			      enum cckpd_mode mode)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	u32 val = 0;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "write CCK CCA parameters(CS_ratio & PD)\n");
-+	switch (mode) {
-+	case CCK_BW20_1R: /*RFBW20_1R*/
-+	{
-+		val = cckpd_t->cck_pd_table_jgr3[0][0][0][lv];
-+		odm_set_bb_reg(dm, R_0x1a30, 0x1f, val);
-+		val = cckpd_t->cck_pd_table_jgr3[0][0][1][lv];
-+		odm_set_bb_reg(dm, R_0x1a20, 0x1f, val);
-+	} break;
-+	case CCK_BW40_1R: /*RFBW40_1R*/
-+	{
-+		val = cckpd_t->cck_pd_table_jgr3[1][0][0][lv];
-+		odm_set_bb_reg(dm, R_0x1a34, 0x1f, val);
-+		val = cckpd_t->cck_pd_table_jgr3[1][0][1][lv];
-+		odm_set_bb_reg(dm, R_0x1a24, 0x1f, val);
-+	} break;
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	case CCK_BW20_2R: /*RFBW20_2R*/
-+	{
-+		val = cckpd_t->cck_pd_table_jgr3[0][1][0][lv];
-+		odm_set_bb_reg(dm, R_0x1a30, 0x3e0, val);
-+		val = cckpd_t->cck_pd_table_jgr3[0][1][1][lv];
-+		odm_set_bb_reg(dm, R_0x1a20, 0x3e0, val);
-+	} break;
-+	case CCK_BW40_2R: /*RFBW40_2R*/
-+	{
-+		val = cckpd_t->cck_pd_table_jgr3[1][1][0][lv];
-+		odm_set_bb_reg(dm, R_0x1a34, 0x3e0, val);
-+		val = cckpd_t->cck_pd_table_jgr3[1][1][1][lv];
-+		odm_set_bb_reg(dm, R_0x1a24, 0x3e0, val);
-+	} break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	case CCK_BW20_3R: /*RFBW20_3R*/
-+	{
-+		val = cckpd_t->cck_pd_table_jgr3[0][2][0][lv];
-+		odm_set_bb_reg(dm, R_0x1a30, 0x7c00, val);
-+		val = cckpd_t->cck_pd_table_jgr3[0][2][1][lv];
-+		odm_set_bb_reg(dm, R_0x1a20, 0x7c00, val);
-+	} break;
-+	case CCK_BW40_3R: /*RFBW40_3R*/
-+	{
-+		val = cckpd_t->cck_pd_table_jgr3[1][2][0][lv];
-+		odm_set_bb_reg(dm, R_0x1a34, 0x7c00, val);
-+		val = cckpd_t->cck_pd_table_jgr3[1][2][1][lv];
-+		odm_set_bb_reg(dm, R_0x1a24, 0x7c00, val);
-+	} break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	case CCK_BW20_4R: /*RFBW20_4R*/
-+	{
-+		val = cckpd_t->cck_pd_table_jgr3[0][3][0][lv];
-+		odm_set_bb_reg(dm, R_0x1a30, 0xF8000, val);
-+		val = cckpd_t->cck_pd_table_jgr3[0][3][1][lv];
-+		odm_set_bb_reg(dm, R_0x1a20, 0xF8000, val);
-+	} break;
-+	case CCK_BW40_4R: /*RFBW40_4R*/
-+	{
-+		val = cckpd_t->cck_pd_table_jgr3[1][3][0][lv];
-+		odm_set_bb_reg(dm, R_0x1a34, 0xF8000, val);
-+		val = cckpd_t->cck_pd_table_jgr3[1][3][1][lv];
-+		odm_set_bb_reg(dm, R_0x1a24, 0xF8000, val);
-+	} break;
-+	#endif
-+	default:
-+		/*@pr_debug("[%s] warning!\n", __func__);*/
-+		break;
-+	}
-+}
-+
-+
-+void phydm_set_cck_pd_lv_type5(void *dm_void, enum cckpd_lv lv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	enum cckpd_mode cck_mode = CCK_BW20_1R;
-+	enum channel_width cck_bw = CHANNEL_WIDTH_20;
-+	u8 cck_n_rx = 0;
-+	u32 val = 0;
-+	/*u32 val_dbg = 0;*/
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
-+	PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
-+
-+	/*[Check Nrx] for 8723F*/
-+	cck_n_rx = 1;
-+
-+	/*[Check BW]*/
-+	val = odm_get_bb_reg(dm, R_0x9b0, 0xc);
-+	if (val == 0)
-+		cck_bw = CHANNEL_WIDTH_20;
-+	else if (val == 1)
-+		cck_bw = CHANNEL_WIDTH_40;
-+	else
-+		cck_bw = CHANNEL_WIDTH_80;
-+
-+	/*[Check LV]*/
-+	if (cckpd_t->cck_pd_lv == lv &&
-+	    cckpd_t->cck_n_rx == cck_n_rx &&
-+	    cckpd_t->cck_bw == cck_bw) {
-+		PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
-+		return;
-+	}
-+	cckpd_t->cck_bw = cck_bw;
-+	cckpd_t->cck_n_rx = cck_n_rx;
-+	cckpd_t->cck_pd_lv = lv;
-+	cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
-+
-+	switch (cck_n_rx) {
-+	case 1: /*1R*/
-+	{
-+		if (cck_bw == CHANNEL_WIDTH_20)
-+			cck_mode = CCK_BW20_1R;
-+		else if (cck_bw == CHANNEL_WIDTH_40)
-+			cck_mode = CCK_BW40_1R;
-+	} break;
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	case 2: /*2R*/
-+	{
-+		if (cck_bw == CHANNEL_WIDTH_20)
-+			cck_mode = CCK_BW20_2R;
-+		else if (cck_bw == CHANNEL_WIDTH_40)
-+			cck_mode = CCK_BW40_2R;
-+	} break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	case 3: /*3R*/
-+	{
-+		if (cck_bw == CHANNEL_WIDTH_20)
-+			cck_mode = CCK_BW20_3R;
-+		else if (cck_bw == CHANNEL_WIDTH_40)
-+			cck_mode = CCK_BW40_3R;
-+	} break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	case 4: /*4R*/
-+	{
-+		if (cck_bw == CHANNEL_WIDTH_20)
-+			cck_mode = CCK_BW20_4R;
-+		else if (cck_bw == CHANNEL_WIDTH_40)
-+			cck_mode = CCK_BW40_4R;
-+	} break;
-+	#endif
-+	default:
-+		/*@pr_debug("[%s] warning!\n", __func__);*/
-+		break;
-+	}
-+
-+
-+	
-+phydm_write_cck_pd_type5(dm, lv, cck_mode);
-+}
-+
-+void phydm_read_cckpd_para_type5(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	u8 bw = 0; /*r_RX_RF_BW*/
-+	u8 n_rx = 0;
-+	u8 curr_cck_pd_t[2][4][2];
-+	u32 reg0 = 0;
-+	u32 reg1 = 0;
-+	u32 reg2 = 0;
-+	u32 reg3 = 0;
-+
-+	bw = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc);
-+
-+	reg0 = odm_get_bb_reg(dm, R_0x1a30, MASKDWORD);
-+	reg1 = odm_get_bb_reg(dm, R_0x1a34, MASKDWORD);
-+	reg2 = odm_get_bb_reg(dm, R_0x1a20, MASKDWORD);
-+	reg3 = odm_get_bb_reg(dm, R_0x1a24, MASKDWORD);
-+	curr_cck_pd_t[0][0][0] = (u8)(reg0 & 0x0000001f);
-+	curr_cck_pd_t[1][0][0] = (u8)(reg1 & 0x0000001f);
-+	curr_cck_pd_t[0][0][1] = (u8)(reg2 & 0x0000001f);
-+	curr_cck_pd_t[1][0][1] = (u8)(reg3 & 0x0000001f);
-+	n_rx = 1;
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
-+		curr_cck_pd_t[0][1][0] = (u8)((reg0 & 0x000003E0) >> 5);
-+		curr_cck_pd_t[1][1][0] = (u8)((reg1 & 0x000003E0) >> 5);
-+		curr_cck_pd_t[0][1][1] = (u8)((reg2 & 0x000003E0) >> 5);
-+		curr_cck_pd_t[1][1][1] = (u8)((reg3 & 0x000003E0) >> 5);
-+		n_rx = 2;
-+	}
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {
-+		curr_cck_pd_t[0][2][0] = (u8)((reg0 & 0x00007C00) >> 10);
-+		curr_cck_pd_t[1][2][0] = (u8)((reg1 & 0x00007C00) >> 10);
-+		curr_cck_pd_t[0][2][1] = (u8)((reg2 & 0x00007C00) >> 10);
-+		curr_cck_pd_t[1][2][1] = (u8)((reg3 & 0x00007C00) >> 10);
-+		n_rx = 3;
-+	}
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
-+		curr_cck_pd_t[0][3][0] = (u8)((reg0 & 0x000F8000) >> 15);
-+		curr_cck_pd_t[1][3][0] = (u8)((reg1 & 0x000F8000) >> 15);
-+		curr_cck_pd_t[0][3][1] = (u8)((reg2 & 0x000F8000) >> 15);
-+		curr_cck_pd_t[1][3][1] = (u8)((reg3 & 0x000F8000) >> 15);
-+		n_rx = 4;
-+	}
-+	#endif
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "bw=%dM, Nrx=%d\n", 20 << bw, n_rx);
-+	PHYDM_DBG(dm, DBG_CCKPD, "lv=%d, readback CS_th=0x%x, PD th=0x%x\n",
-+		  cckpd_t->cck_pd_lv,
-+		  curr_cck_pd_t[bw][n_rx - 1][1],
-+		  curr_cck_pd_t[bw][n_rx - 1][0]);
-+}
-+
-+void phydm_cckpd_type5(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	u8 igi = dm->dm_dig_table.cur_ig_value;
-+	enum cckpd_lv lv = 0;
-+	boolean is_update = true;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
-+
-+	if (dm->is_linked) {
-+		PHYDM_DBG(dm, DBG_CCKPD, "Linked!!!\n");
-+		if (dm->rssi_min > 40) {
-+			lv = CCK_PD_LV_4;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
-+		} else if (dm->rssi_min > 32) {
-+			lv = CCK_PD_LV_3;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
-+		} else if (dm->rssi_min > 24) {
-+			lv = CCK_PD_LV_2;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
-+		} else {
-+			if (cckpd_t->cck_fa_ma > 1000) {
-+				lv = CCK_PD_LV_1;
-+				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-1\n");
-+			} else if (cckpd_t->cck_fa_ma < 500) {
-+				lv = CCK_PD_LV_0;
-+				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-2\n");
-+			} else {
-+				is_update = false;
-+				PHYDM_DBG(dm, DBG_CCKPD, "Order 4-3\n");
-+			}
-+		}
-+	} else {
-+	PHYDM_DBG(dm, DBG_CCKPD, "UnLinked!!!\n");
-+		if (cckpd_t->cck_fa_ma > 1000) {
-+			lv = CCK_PD_LV_1;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
-+		} else if (cckpd_t->cck_fa_ma < 500) {
-+			lv = CCK_PD_LV_0;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
-+		} else {
-+			is_update = false;
-+			PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
-+		}
-+	}
-+
-+	if (is_update) {
-+		phydm_set_cck_pd_lv_type5(dm, lv);
-+
-+		PHYDM_DBG(dm, DBG_CCKPD, "setting CS_th = 0x%x, PD th = 0x%x\n",
-+			  cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw]
-+			  [cckpd_t->cck_n_rx - 1][1][lv],
-+			  cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw]
-+			  [cckpd_t->cck_n_rx - 1][0][lv]);
-+	}
-+
-+	phydm_read_cckpd_para_type5(dm);
-+}
-+
-+void phydm_cck_pd_init_type5(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	u32 reg0 = 0;
-+	u32 reg1 = 0;
-+	u32 reg2 = 0;
-+	u32 reg3 = 0;
-+	u8 pw_step = 0;
-+	u8 cs_step = 0;
-+	u8 cck_bw = 0; /*r_RX_RF_BW*/
-+	u8 cck_n_rx = 0;
-+	u8 val = 0;
-+	u8 i = 0;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__);
-+	#if 0
-+	/*@
-+	 *cckpd_t[0][0][0][0] =  1a30[4:0]	r_PD_lim_RFBW20_1R
-+	 *cckpd_t[0][1][0][0] =  1a30[9:5]	r_PD_lim_RFBW20_2R
-+	 *cckpd_t[0][2][0][0] =  1a30[14:10]	r_PD_lim_RFBW20_3R
-+	 *cckpd_t[0][3][0][0] =  1a30[19:15]	r_PD_lim_RFBW20_4R
-+	 *cckpd_t[1][0][0][0] =  1a34[4:0]	r_PD_lim_RFBW40_1R
-+	 *cckpd_t[1][1][0][0] =  1a34[9:5]	r_PD_lim_RFBW40_2R
-+	 *cckpd_t[1][2][0][0] =  1a34[14:10]	r_PD_lim_RFBW40_3R
-+	 *cckpd_t[1][3][0][0] =  1a34[19:15]	r_PD_lim_RFBW40_4R
-+	 *
-+	 *
-+	 *cckpd_t[0][0][1][0] =  1a20[4:0]	r_CS_ratio_RFBW20_1R
-+	 *cckpd_t[0][1][1][0] =  1a20[9:5]	r_CS_ratio_RFBW20_2R
-+	 *cckpd_t[0][2][1][0] =  1a20[14:10]	r_CS_ratio_RFBW20_3R
-+	 *cckpd_t[0][3][1][0] =  1a20[19:15]	r_CS_ratio_RFBW20_4R
-+	 *cckpd_t[1][0][1][0] =  1a24[4:0]	r_CS_ratio_RFBW40_1R
-+	 *cckpd_t[1][1][1][0] =  1a24[9:5]	r_CS_ratio_RFBW40_2R
-+	 *cckpd_t[1][2][1][0] =  1a24[14:10]	r_CS_ratio_RFBW40_3R
-+	 *cckpd_t[1][3][1][0] =  1a24[19:15]	r_CS_ratio_RFBW40_4R
-+	 */
-+	#endif
-+	/*[Check Nrx]*/
-+	cck_n_rx = 1;
-+
-+	/*[Check BW]*/
-+	val = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc);
-+	if (val == 0)
-+		cck_bw = CHANNEL_WIDTH_20;
-+	else if (val == 1)
-+		cck_bw = CHANNEL_WIDTH_40;
-+	else
-+		cck_bw = CHANNEL_WIDTH_80;
-+
-+	cckpd_t->cck_bw = cck_bw;
-+	reg0 = odm_get_bb_reg(dm, R_0x1a30, MASKDWORD);
-+	reg1 = odm_get_bb_reg(dm, R_0x1a34, MASKDWORD);
-+	reg2 = odm_get_bb_reg(dm, R_0x1a20, MASKDWORD);
-+	reg3 = odm_get_bb_reg(dm, R_0x1a24, MASKDWORD);
-+
-+	for (i = 0 ; i < CCK_PD_LV_MAX ; i++) {
-+		pw_step = i * 2;
-+		cs_step = i * 2;
-+
-+		#if (RTL8723F_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8723F) {
-+			if (i == CCK_PD_LV_1) {
-+				pw_step = 9; /*IGI-19.2:0x11=d'17*/
-+				cs_step = 0;
-+			} else if (i == CCK_PD_LV_2) {
-+				pw_step = 12; /*IGI-15.5:0x14=d'20*/
-+				cs_step = 1;
-+			} else if (i == CCK_PD_LV_3) {
-+				pw_step = 14; /*IGI-14:0x16=d'22*/
-+				cs_step = 1;
-+			} else if (i == CCK_PD_LV_4) {
-+				pw_step = 17; /*IGI-12:0x19=d'25*/
-+				cs_step = 1;
-+			}
-+		}
-+		#endif
-+		val = (u8)(reg0 & 0x0000001F) + pw_step;
-+		PHYDM_DBG(dm, DBG_CCKPD, "lvl %d val = %x\n\n", i, val);
-+		cckpd_t->cck_pd_table_jgr3[0][0][0][i] = val;
-+
-+		val = (u8)(reg1 & 0x0000001F) + pw_step;
-+		cckpd_t->cck_pd_table_jgr3[1][0][0][i] = val;
-+
-+		val = (u8)(reg2 & 0x0000001F) + cs_step;
-+		cckpd_t->cck_pd_table_jgr3[0][0][1][i] = val;
-+
-+		val = (u8)(reg3 & 0x0000001F) + cs_step;
-+		cckpd_t->cck_pd_table_jgr3[1][0][1][i] = val;
-+
-+		#ifdef PHYDM_COMPILE_ABOVE_2SS
-+		if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
-+			val = (u8)((reg0 & 0x000003E0) >> 5) + pw_step;
-+			cckpd_t->cck_pd_table_jgr3[0][1][0][i] = val;
-+
-+			val = (u8)((reg1 & 0x000003E0) >> 5) + pw_step;
-+			cckpd_t->cck_pd_table_jgr3[1][1][0][i] = val;
-+
-+			val = (u8)((reg2 & 0x000003E0) >> 5) + cs_step;
-+			cckpd_t->cck_pd_table_jgr3[0][1][1][i] = val;
-+
-+			val = (u8)((reg3 & 0x000003E0) >> 5) + cs_step;
-+			cckpd_t->cck_pd_table_jgr3[1][1][1][i] = val;
-+
-+			cck_n_rx = 2;
-+		}
-+		#endif
-+		#ifdef PHYDM_COMPILE_ABOVE_3SS
-+		if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {
-+			val = (u8)((reg0 & 0x00007C00) >> 10) + pw_step;
-+			cckpd_t->cck_pd_table_jgr3[0][2][0][i] = val;
-+
-+			val = (u8)((reg1 & 0x00007C00) >> 10) + pw_step;
-+			cckpd_t->cck_pd_table_jgr3[1][2][0][i] = val;
-+
-+			val = (u8)((reg2 & 0x00007C00) >> 10) + cs_step;
-+			cckpd_t->cck_pd_table_jgr3[0][2][1][i] = val;
-+
-+			val = (u8)((reg3 & 0x00007C00) >> 10) + cs_step;
-+			cckpd_t->cck_pd_table_jgr3[1][2][1][i] = val;
-+
-+			cck_n_rx = 3;
-+		}
-+		#endif
-+
-+		#ifdef PHYDM_COMPILE_ABOVE_4SS
-+		if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
-+			val = (u8)((reg0 & 0x000F8000) >> 15) + pw_step;
-+			cckpd_t->cck_pd_table_jgr3[0][3][0][i] = val;
-+
-+			val = (u8)((reg1 & 0x000F8000) >> 15) + pw_step;
-+			cckpd_t->cck_pd_table_jgr3[1][3][0][i] = val;
-+
-+			val = (u8)((reg2 & 0x000F8000) >> 15) + cs_step;
-+			cckpd_t->cck_pd_table_jgr3[0][3][1][i] = val;
-+
-+			val = (u8)((reg3 & 0x000F8000) >> 15) + cs_step;
-+			cckpd_t->cck_pd_table_jgr3[1][3][1][i] = val;
-+
-+			cck_n_rx = 4;
-+		}
-+		#endif
-+			}
-+	cckpd_t->cck_n_rx = cck_n_rx;
-+}
-+
-+
-+
-+
-+#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE5*/
-+
-+
-+
-+
-+void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	enum cckpd_lv lv;
-+
-+	if (val_len != 1) {
-+		PHYDM_DBG(dm, ODM_COMP_API, "[Error][CCKPD]Need val_len=1\n");
-+		return;
-+	}
-+
-+	lv = (enum cckpd_lv)val_buf[0];
-+
-+	if (lv > CCK_PD_LV_4) {
-+		pr_debug("[%s] warning! lv=%d\n", __func__, lv);
-+		return;
-+	}
-+
-+	switch (cckpd_t->cckpd_hw_type) {
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE1
-+	case 1:
-+		phydm_set_cckpd_lv_type1(dm, lv);
-+		break;
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE2
-+	case 2:
-+		phydm_set_cckpd_lv_type2(dm, lv);
-+		break;
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE3
-+	case 3:
-+		phydm_set_cckpd_lv_type3(dm, lv);
-+		break;
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE4
-+	case 4:
-+		phydm_set_cck_pd_lv_type4(dm, lv);
-+		break;
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE5
-+	case 5:
-+		phydm_set_cck_pd_lv_type5(dm, lv);
-+		break;
-+	#endif
-+	default:
-+		pr_debug("[%s]warning\n", __func__);
-+		break;
-+	}
-+}
-+
-+boolean
-+phydm_stop_cck_pd_th(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ability & ODM_BB_FA_CNT)) {
-+		PHYDM_DBG(dm, DBG_CCKPD, "Not Support:ODM_BB_FA_CNT disable\n");
-+		return true;
-+	}
-+
-+	if (!(dm->support_ability & ODM_BB_CCK_PD)) {
-+		PHYDM_DBG(dm, DBG_CCKPD, "Not Support:ODM_BB_CCK_PD disable\n");
-+		return true;
-+	}
-+
-+	if (dm->pause_ability & ODM_BB_CCK_PD) {
-+		PHYDM_DBG(dm, DBG_CCKPD, "Return: Pause CCKPD in LV=%d\n",
-+			  dm->pause_lv_table.lv_cckpd);
-+		return true;
-+	}
-+
-+	if (dm->is_linked && (*dm->channel > 36)) {
-+		PHYDM_DBG(dm, DBG_CCKPD, "Return: 5G CH=%d\n", *dm->channel);
-+		return true;
-+	}
-+	return false;
-+}
-+
-+void phydm_cck_pd_th(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	u32 cck_fa = fa_t->cnt_cck_fail;
-+	#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	struct phydm_fa_acc_struct *fa_acc_t = &dm->false_alm_cnt_acc;
-+	#endif
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "[%s] ======>\n", __func__);
-+
-+	if (phydm_stop_cck_pd_th(dm))
-+		return;
-+
-+	#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	if (dm->original_dig_restore)
-+		cck_fa = fa_t->cnt_cck_fail;
-+	else
-+		cck_fa = fa_acc_t->cnt_cck_fail_1sec;
-+	#endif
-+
-+	if (cckpd_t->cck_fa_ma == CCK_FA_MA_RESET)
-+		cckpd_t->cck_fa_ma = cck_fa;
-+	else
-+		cckpd_t->cck_fa_ma = (cckpd_t->cck_fa_ma * 3 + cck_fa) >> 2;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD,
-+		  "IGI=0x%x, rssi_min=%d, cck_fa=%d, cck_fa_ma=%d\n",
-+		  dm->dm_dig_table.cur_ig_value, dm->rssi_min,
-+		  cck_fa, cckpd_t->cck_fa_ma);
-+
-+	switch (cckpd_t->cckpd_hw_type) {
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE1
-+	case 1:
-+		phydm_cckpd_type1(dm);
-+		break;
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE2
-+	case 2:
-+		phydm_cckpd_type2(dm);
-+		break;
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE3
-+	case 3:
-+		phydm_cckpd_type3(dm);
-+		break;
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE4
-+	case 4:
-+		#ifdef PHYDM_DCC_ENHANCE
-+		if (dm->dm_dcc_info.dcc_en)
-+			phydm_cckpd_type4_dcc(dm);
-+		else
-+		#endif
-+			phydm_cckpd_type4(dm);
-+		break;
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE5
-+	case 5:
-+		phydm_cckpd_type5(dm);
-+		break;
-+	#endif
-+	default:
-+		pr_debug("[%s]warning\n", __func__);
-+		break;
-+	}
-+}
-+
-+void phydm_cck_pd_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+
-+	if (*dm->mp_mode)
-+		return;
-+
-+	if (dm->support_ic_type & CCK_PD_IC_TYPE1)
-+		cckpd_t->cckpd_hw_type = 1;
-+	else if (dm->support_ic_type & CCK_PD_IC_TYPE2)
-+		cckpd_t->cckpd_hw_type = 2;
-+	else if (dm->support_ic_type & CCK_PD_IC_TYPE3)
-+		cckpd_t->cckpd_hw_type = 3;
-+	else if (dm->support_ic_type & CCK_PD_IC_TYPE4)
-+		cckpd_t->cckpd_hw_type = 4;
-+
-+	if (dm->support_ic_type & CCK_PD_IC_TYPE5)
-+		cckpd_t->cckpd_hw_type = 5;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "[%s] cckpd_hw_type=%d\n",
-+		  __func__, cckpd_t->cckpd_hw_type);
-+
-+	cckpd_t->cck_pd_lv = CCK_PD_LV_INIT;
-+	cckpd_t->cck_n_rx = 0xff;
-+	cckpd_t->cck_bw = CHANNEL_WIDTH_MAX;
-+	cckpd_t->cck_fa_th[1] = 400;
-+	cckpd_t->cck_fa_th[0] = 200;
-+
-+	switch (cckpd_t->cckpd_hw_type) {
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE1
-+	case 1:
-+		phydm_set_cckpd_lv_type1(dm, CCK_PD_LV_1);
-+		break;
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE2
-+	case 2:
-+		cckpd_t->aaa_default = odm_read_1byte(dm, 0xaaa) & 0x1f;
-+		phydm_set_cckpd_lv_type2(dm, CCK_PD_LV_1);
-+		break;
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE3
-+	case 3:
-+		phydm_cck_pd_init_type3(dm);
-+		phydm_set_cckpd_lv_type3(dm, CCK_PD_LV_1);
-+		break;
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE4
-+	case 4:
-+		phydm_cck_pd_init_type4(dm);
-+		phydm_invalid_cckpd_type4(dm);
-+		phydm_set_cck_pd_lv_type4(dm, CCK_PD_LV_1);
-+		break;
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE5
-+	case 5:
-+		phydm_cck_pd_init_type5(dm);
-+		break;
-+	#endif
-+	default:
-+		pr_debug("[%s]warning\n", __func__);
-+		break;
-+	}
-+}
-+
-+#ifdef PHYDM_DCC_ENHANCE
-+
-+void phydm_cckpd_type4_dcc(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	enum cckpd_lv lv_curr = cckpd_t->cck_pd_lv;
-+	enum phydm_cck_pd_trend trend = CCKPD_STABLE;
-+	u8 th_ofst = 0;
-+	u16 lv_up_th, lv_down_th;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
-+
-+	if (!dm->is_linked)
-+		th_ofst = 1;
-+
-+	lv_up_th = (cckpd_t->cck_fa_th[1]) << th_ofst;
-+	lv_down_th = (cckpd_t->cck_fa_th[0]) << th_ofst;
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "th{Up, Down}: {%d, %d}\n",
-+		  lv_up_th, lv_down_th);
-+
-+	if (cckpd_t->cck_fa_ma > lv_up_th) {
-+		if (lv_curr <= CCK_PD_LV_3) {
-+			lv_curr++;
-+			trend = CCKPD_INCREASING;
-+		} else {
-+			lv_curr = CCK_PD_LV_4;
-+		}
-+	} else if (cckpd_t->cck_fa_ma < lv_down_th) {
-+		if (lv_curr >= CCK_PD_LV_1) {
-+			lv_curr--;
-+			trend = CCKPD_DECREASING;
-+		} else {
-+			lv_curr = CCK_PD_LV_0;
-+		}
-+	}
-+
-+	PHYDM_DBG(dm, DBG_CCKPD, "lv: %d->%d\n", cckpd_t->cck_pd_lv, lv_curr);
-+#if 1
-+	if (trend != CCKPD_STABLE) {
-+		phydm_set_cck_pd_lv_type4(dm, lv_curr);
-+
-+		PHYDM_DBG(dm, DBG_CCKPD, "setting CS_th = 0x%x, PD th = 0x%x\n",
-+			  cckpd_t->cckpd_jgr3[cckpd_t->cck_bw]
-+			  [cckpd_t->cck_n_rx - 1][1][lv_curr],
-+			  cckpd_t->cckpd_jgr3[cckpd_t->cck_bw]
-+			  [cckpd_t->cck_n_rx - 1][0][lv_curr]);
-+	}
-+	phydm_read_cckpd_para_type4(dm);
-+#endif
-+}
-+
-+boolean phydm_do_cckpd(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+	if (dig_t->igi_trend == DIG_INCREASING)
-+		return false;
-+
-+	return true;
-+}
-+
-+void phydm_dig_cckpd_coex(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dcc_struct	*dcc = &dm->dm_dcc_info;
-+
-+	if (*dm->channel > 36) {
-+		phydm_dig(dm);
-+		return;
-+	} else if (!dcc->dcc_en) {
-+		phydm_dig(dm);
-+		phydm_cck_pd_th(dm);
-+		return;
-+	}
-+
-+	dcc->dig_execute_cnt++;
-+	PHYDM_DBG(dm, DBG_CCKPD, "DCC_cnt: %d\n", dcc->dig_execute_cnt);
-+
-+	if (dcc->dig_execute_cnt % dcc->dcc_ratio) {
-+		PHYDM_DBG(dm, DBG_CCKPD, "DCC: DIG\n");
-+		phydm_dig(dm);
-+	} else {
-+		if (phydm_do_cckpd(dm)) {
-+			PHYDM_DBG(dm, DBG_CCKPD, "DCC: CCKPD\n");
-+			dcc->dcc_mode = DCC_CCK_PD;
-+			phydm_cck_pd_th(dm);
-+		} else {
-+			PHYDM_DBG(dm, DBG_CCKPD, "DCC: Boost_DIG\n");
-+			dcc->dcc_mode = DCC_DIG;
-+			phydm_dig(dm);
-+		}
-+	}
-+}
-+
-+void phydm_dig_cckpd_coex_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_dcc_struct	*dcc = &dm->dm_dcc_info;
-+
-+	dcc->dcc_mode = DCC_DIG;
-+	dcc->dcc_en = false;
-+	dcc->dig_execute_cnt = 0;
-+	dcc->dcc_ratio = 2;
-+}
-+
-+void phydm_dig_cckpd_coex_dbg(void *dm_void, char input[][16], u32 *_used,
-+			      char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
-+	struct phydm_dcc_struct	*dcc = &dm->dm_dcc_info;
-+	char help[] = "-h";
-+	u32 var[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i = 0;
-+
-+	for (i = 0; i < 3; i++) {
-+		if (input[i + 1])
-+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
-+	}
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Enable: en {0/1}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "DCC_ratio: ratio {x}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "threshold: th {Down_th} {Up_th}\n");
-+	} else if ((strcmp(input[1], "en") == 0)) {
-+		dcc->dcc_en = (var[1]) ? true : false;
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "en=%d\n", dcc->dcc_en);
-+	} else if ((strcmp(input[1], "ratio") == 0)) {
-+		dcc->dcc_ratio = (u8)var[1];
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Ratio=%d\n", dcc->dcc_ratio);
-+	} else if ((strcmp(input[1], "th") == 0)) {
-+		cckpd_t->cck_fa_th[1] = (u16)var[2];
-+		cckpd_t->cck_fa_th[0] = (u16)var[1];
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "th{Down, Up}: {%d, %d}\n",
-+			 cckpd_t->cck_fa_th[0], cckpd_t->cck_fa_th[1]);
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#endif
-+#endif /*#ifdef PHYDM_SUPPORT_CCKPD*/
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_cck_pd.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_cck_pd.h
-new file mode 100644
-index 000000000000..f1b2d8c64af9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_cck_pd.h
-@@ -0,0 +1,201 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_CCK_PD_H__
-+#define __PHYDM_CCK_PD_H__
-+
-+/* 2019.12.25 decrease CS_ratio in 8822C due to Lenovo test result(PCIE-5136).*/
-+#define CCK_PD_VERSION "4.0"
-+
-+/*@
-+ * 1 ============================================================
-+ * 1  Definition
-+ * 1 ============================================================
-+ */
-+#define CCK_FA_MA_RESET 0xffffffff
-+
-+#define INVALID_CS_RATIO_0 0x1b /* @ only for type4 ICs*/
-+#define INVALID_CS_RATIO_1 0x1d /* @ only for type4 ICs*/
-+#define MAXVALID_CS_RATIO 0x1f
-+/*@Run time flag of CCK_PD HW type*/
-+#define CCK_PD_IC_TYPE1 (ODM_RTL8188E | ODM_RTL8812 | ODM_RTL8821 |\
-+			ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8814A |\
-+			ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8703B |\
-+			ODM_RTL8195A | ODM_RTL8188F)
-+
-+#define CCK_PD_IC_TYPE2 (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |\
-+			ODM_RTL8710B | ODM_RTL8195B) /*extend 0xaaa*/
-+
-+#define CCK_PD_IC_TYPE3 (ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C)
-+/*@extend for different bw & path*/
-+
-+#define CCK_PD_IC_TYPE4 ODM_IC_JGR3_SERIES /*@extend for different bw & path*/
-+#define CCK_PD_IC_TYPE5 (ODM_RTL8723F) /*@extend for different CR*/
-+
-+/*@Compile time flag of CCK_PD HW type*/
-+#if (RTL8188E_SUPPORT || RTL8812A_SUPPORT || RTL8821A_SUPPORT ||\
-+	RTL8192E_SUPPORT || RTL8723B_SUPPORT || RTL8814A_SUPPORT ||\
-+	RTL8881A_SUPPORT || RTL8822B_SUPPORT || RTL8703B_SUPPORT ||\
-+	RTL8195A_SUPPORT || RTL8188F_SUPPORT)
-+	#define PHYDM_COMPILE_CCKPD_TYPE1 /*@only 0xa0a*/
-+#endif
-+
-+#if (RTL8197F_SUPPORT || RTL8821C_SUPPORT || RTL8723D_SUPPORT ||\
-+	RTL8710B_SUPPORT || RTL8195B_SUPPORT)
-+	#define PHYDM_COMPILE_CCKPD_TYPE2 /*@extend 0xaaa*/
-+#endif
-+
-+#if (RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
-+	#define PHYDM_COMPILE_CCKPD_TYPE3 /*@extend for different & path*/
-+#endif
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	#define PHYDM_COMPILE_CCKPD_TYPE4 /*@extend for different bw & path*/
-+#endif
-+#if (RTL8723F_SUPPORT)
-+	#define PHYDM_COMPILE_CCKPD_TYPE5 /*@extend for different & path*/
-+#endif
-+
-+/*@
-+ * 1 ============================================================
-+ * 1  enumeration
-+ * 1 ============================================================
-+ */
-+enum cckpd_lv {
-+	CCK_PD_LV_INIT = 0xff,
-+	CCK_PD_LV_0 = 0,
-+	CCK_PD_LV_1 = 1,
-+	CCK_PD_LV_2 = 2,
-+	CCK_PD_LV_3 = 3,
-+	CCK_PD_LV_4 = 4,
-+	CCK_PD_LV_MAX = 5
-+};
-+
-+enum cckpd_mode {
-+	CCK_BW20_1R = 0,
-+	CCK_BW20_2R = 1,
-+	CCK_BW20_3R = 2,
-+	CCK_BW20_4R = 3,
-+	CCK_BW40_1R = 4,
-+	CCK_BW40_2R = 5,
-+	CCK_BW40_3R = 6,
-+	CCK_BW40_4R = 7
-+};
-+
-+enum dcc_mode {
-+	DCC_DIG		= 0,
-+	DCC_CCK_PD	= 1
-+};
-+
-+enum phydm_cck_pd_trend {
-+	CCKPD_STABLE			= 0,
-+	CCKPD_INCREASING		= 1,
-+	CCKPD_DECREASING		= 2
-+};
-+
-+/*@
-+ * 1 ============================================================
-+ * 1  structure
-+ * 1 ============================================================
-+ */
-+
-+#ifdef PHYDM_SUPPORT_CCKPD
-+
-+#ifdef PHYDM_DCC_ENHANCE
-+struct phydm_dcc_struct { /*DIG CCK_PD coexistence*/
-+	boolean		dcc_en;
-+	enum dcc_mode	dcc_mode;
-+	u32		dig_execute_cnt;
-+	u8		dcc_ratio;
-+};
-+#endif
-+
-+struct phydm_cckpd_struct {
-+	u8		cckpd_hw_type;
-+	u8		cur_cck_cca_thres; /*@current cck_pd value 0xa0a*/
-+	u32		cck_fa_ma;
-+	u32		rvrt_val; /*all rvrt_val for pause API must set to u32*/
-+	u8		pause_lv;
-+	u8		cck_n_rx;
-+	u16		cck_fa_th[2];
-+	enum channel_width cck_bw;
-+	enum cckpd_lv	cck_pd_lv;
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE2
-+	u8		cck_cca_th_aaa; /*@current cs_ratio value 0xaaa*/
-+	u8		aaa_default;	/*@Init cs_ratio value - 0xaaa*/
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE3
-+	/*Default value*/
-+	u8		cck_pd_20m_1r;
-+	u8		cck_pd_20m_2r;
-+	u8		cck_pd_40m_1r;
-+	u8		cck_pd_40m_2r;
-+	u8		cck_cs_ratio_20m_1r;
-+	u8		cck_cs_ratio_20m_2r;
-+	u8		cck_cs_ratio_40m_1r;
-+	u8		cck_cs_ratio_40m_2r;
-+	/*Current value*/
-+	u8		cur_cck_pd_20m_1r;
-+	u8		cur_cck_pd_20m_2r;
-+	u8		cur_cck_pd_40m_1r;
-+	u8		cur_cck_pd_40m_2r;
-+	u8		cur_cck_cs_ratio_20m_1r;
-+	u8		cur_cck_cs_ratio_20m_2r;
-+	u8		cur_cck_cs_ratio_40m_1r;
-+	u8		cur_cck_cs_ratio_40m_2r;
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE4
-+	/*@[bw][nrx][0:PD/1:CS][lv]*/
-+	u8		cckpd_jgr3[2][4][2][CCK_PD_LV_MAX];
-+	#endif
-+	#ifdef PHYDM_COMPILE_CCKPD_TYPE5
-+	/*@[bw][nrx][0:PD/1:CS][lv]*/
-+	u8		cck_pd_table_jgr3[2][4][2][CCK_PD_LV_MAX];
-+	#endif
-+};
-+#endif
-+
-+/*@
-+ * 1 ============================================================
-+ * 1  function prototype
-+ * 1 ============================================================
-+ */
-+void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len);
-+
-+void phydm_cck_pd_th(void *dm_void);
-+
-+void phydm_cck_pd_init(void *dm_void);
-+
-+#ifdef PHYDM_DCC_ENHANCE
-+void phydm_cckpd_type4_dcc(void *dm_void);
-+
-+void phydm_dig_cckpd_coex(void *dm_void);
-+
-+void phydm_dig_cckpd_coex_init(void *dm_void);
-+
-+void phydm_dig_cckpd_coex_dbg(void *dm_void, char input[][16], u32 *_used,
-+			      char *output, u32 *_out_len);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_cck_rx_pathdiv.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_cck_rx_pathdiv.c
-new file mode 100644
-index 000000000000..3106f19395c8
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_cck_rx_pathdiv.c
-@@ -0,0 +1,163 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT /* @PHYDM-342*/
-+void phydm_cck_rx_pathdiv_manaul(void *dm_void, boolean en_cck_rx_pathdiv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	/* @Can not apply for 98F/14B/97G from DD YC*/
-+	if (en_cck_rx_pathdiv) {
-+		odm_set_bb_reg(dm, R_0x1a14, BIT(7), 0x0);
-+		odm_set_bb_reg(dm, R_0x1a74, BIT(8), 0x1);
-+	} else {
-+		odm_set_bb_reg(dm, R_0x1a14, BIT(7), 0x1);
-+		odm_set_bb_reg(dm, R_0x1a74, BIT(8), 0x0);
-+	}
-+}
-+
-+void phydm_cck_rx_pathdiv_watchdog(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
-+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
-+	u8 rssi_th = 0;
-+	u32 rssi_a = 0, rssi_b = 0, rssi_avg = 0;
-+
-+	if (!cckrx_t->en_cck_rx_pathdiv)
-+		return;
-+
-+	rssi_a = PHYDM_DIV(cckrx_t->path_a_sum, cckrx_t->path_a_cnt);
-+	rssi_b = PHYDM_DIV(cckrx_t->path_b_sum, cckrx_t->path_b_cnt);
-+	rssi_avg = (rssi_a + rssi_b) >> 1;
-+
-+	pr_debug("Rx-A:%d, Rx-B:%d, avg:%d\n", rssi_a, rssi_b, rssi_avg);
-+
-+	cckrx_t->path_a_cnt = 0;
-+	cckrx_t->path_a_sum = 0;
-+	cckrx_t->path_b_cnt = 0;
-+	cckrx_t->path_b_sum = 0;
-+
-+	if (fa_t->cnt_all >= 100)
-+		rssi_th = cckrx_t->rssi_fa_th;
-+	else
-+		rssi_th = cckrx_t->rssi_th;
-+
-+	if (dm->phy_dbg_info.num_qry_beacon_pkt > 14 && rssi_avg <= rssi_th)
-+		phydm_cck_rx_pathdiv_manaul(dm, true);
-+	else
-+		phydm_cck_rx_pathdiv_manaul(dm, false);
-+}
-+
-+void phydm_cck_rx_pathdiv_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
-+
-+	cckrx_t->en_cck_rx_pathdiv = false;
-+	cckrx_t->path_a_cnt = 0;
-+	cckrx_t->path_a_sum = 0;
-+	cckrx_t->path_b_cnt = 0;
-+	cckrx_t->path_b_sum = 0;
-+	cckrx_t->rssi_fa_th = 45;
-+	cckrx_t->rssi_th = 25;
-+}
-+
-+void phydm_process_rssi_for_cck_rx_pathdiv(void *dm_void, void *phy_info_void,
-+					   void *pkt_info_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_phyinfo_struct *phy_info = NULL;
-+	struct phydm_perpkt_info_struct *pktinfo = NULL;
-+	struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
-+
-+	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
-+	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
-+
-+	if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid))
-+		return;
-+
-+	if (pktinfo->is_cck_rate)
-+		return;
-+
-+	cckrx_t->path_a_sum += phy_info->rx_mimo_signal_strength[0];
-+	cckrx_t->path_a_cnt++;
-+
-+	cckrx_t->path_b_sum += phy_info->rx_mimo_signal_strength[1];
-+	cckrx_t->path_b_cnt++;
-+}
-+
-+void phydm_cck_rx_pathdiv_dbg(void *dm_void, char input[][16], u32 *_used,
-+			      char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i = 0;
-+
-+	if (!(dm->support_ic_type & ODM_RTL8822C))
-+		return;
-+
-+	for (i = 0; i < 3; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
-+	}
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "CCK rx pathdiv manual on: {1} {En}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "CCK rx pathdiv watchdog on: {2} {En}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "CCK rx pathdiv rssi_th : {3} {th} {fa_th}\n");
-+	} else if (var1[0] == 1) {
-+		if (var1[1] == 1)
-+			phydm_cck_rx_pathdiv_manaul(dm, true);
-+		else
-+			phydm_cck_rx_pathdiv_manaul(dm, false);
-+	} else if (var1[0] == 2) {
-+		if (var1[1] == 1) {
-+			cckrx_t->en_cck_rx_pathdiv = true;
-+		} else {
-+			cckrx_t->en_cck_rx_pathdiv = false;
-+			phydm_cck_rx_pathdiv_manaul(dm, false);
-+		}
-+	} else if (var1[0] == 3) {
-+		cckrx_t->rssi_th = (u8)var1[1];
-+		cckrx_t->rssi_fa_th = (u8)var1[2];
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_cck_rx_pathdiv.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_cck_rx_pathdiv.h
-new file mode 100644
-index 000000000000..952bcf5f987e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_cck_rx_pathdiv.h
-@@ -0,0 +1,67 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_CCK_RX_PATHDIV_H__
-+#define __PHYDM_CCK_RX_PATHDIV_H__
-+
-+#define CCK_RX_PATHDIV_VERSION "1.1"
-+
-+/* @1 ============================================================
-+ * 1  Definition
-+ * 1 ============================================================
-+ */
-+/* @1 ============================================================
-+ * 1  structure
-+ * 1 ============================================================
-+ */
-+struct phydm_cck_rx_pathdiv {
-+	boolean en_cck_rx_pathdiv;
-+	u32	path_a_sum;
-+	u32	path_b_sum;
-+	u16	path_a_cnt;
-+	u16	path_b_cnt;
-+	u8	rssi_fa_th;
-+	u8	rssi_th;
-+};
-+
-+/* @1 ============================================================
-+ * 1  enumeration
-+ * 1 ============================================================
-+ */
-+
-+/* @1 ============================================================
-+ * 1  function prototype
-+ * 1 ============================================================
-+ */
-+void phydm_cck_rx_pathdiv_watchdog(void *dm_void);
-+
-+void phydm_cck_rx_pathdiv_init(void *dm_void);
-+
-+void phydm_process_rssi_for_cck_rx_pathdiv(void *dm_void, void *phy_info_void,
-+					   void *pkt_info_void);
-+
-+void phydm_cck_rx_pathdiv_dbg(void *dm_void, char input[][16], u32 *_used,
-+			      char *output, u32 *_out_len);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_ccx.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_ccx.c
-new file mode 100644
-index 000000000000..1b8493dbbde9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_ccx.c
-@@ -0,0 +1,3290 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+void phydm_ccx_hw_restart(void *dm_void)
-+			  /*@Will Restart NHM/CLM/FAHM simultaneously*/
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 reg1 = 0;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-+		reg1 = R_0x994;
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		reg1 = R_0x1e60;
-+	#endif
-+	else
-+		reg1 = R_0x890;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+	/*@disable NHM,CLM, FAHM*/
-+	odm_set_bb_reg(dm, reg1, 0x7, 0x0);
-+	odm_set_bb_reg(dm, reg1, BIT(8), 0x0);
-+	odm_set_bb_reg(dm, reg1, BIT(8), 0x1);
-+}
-+
-+#ifdef FAHM_SUPPORT
-+
-+void phydm_fahm_racing_release(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u32 value32 = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "fahm_racing_release : lv:(%d)->(0)\n",
-+		  ccx->fahm_set_lv);
-+
-+	ccx->fahm_ongoing = false;
-+	ccx->fahm_set_lv = FAHM_RELEASE;
-+
-+	if (!(ccx->fahm_app == FAHM_BACKGROUND || ccx->fahm_app == FAHM_ACS))
-+		phydm_pause_func(dm, F00_DIG, PHYDM_RESUME,
-+				 PHYDM_PAUSE_LEVEL_1, 1, &value32);
-+
-+	ccx->fahm_app = FAHM_BACKGROUND;
-+}
-+
-+u8 phydm_fahm_racing_ctrl(void *dm_void, enum phydm_fahm_level lv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 set_result = PHYDM_SET_SUCCESS;
-+	/*acquire to control FAHM API*/
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "fahm_ongoing=%d, lv:(%d)->(%d)\n",
-+		  ccx->fahm_ongoing, ccx->fahm_set_lv, lv);
-+	if (ccx->fahm_ongoing) {
-+		if (lv <= ccx->fahm_set_lv) {
-+			set_result = PHYDM_SET_FAIL;
-+		} else {
-+			phydm_ccx_hw_restart(dm);
-+			ccx->fahm_ongoing = false;
-+		}
-+	}
-+
-+	if (set_result)
-+		ccx->fahm_set_lv = lv;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "fahm racing success=%d\n", set_result);
-+	return set_result;
-+}
-+
-+void phydm_fahm_trigger(void *dm_void)
-+{ /*@unit (4us)*/
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u32 reg = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	switch (dm->ic_ip_series) {
-+	case PHYDM_IC_JGR3:
-+		reg = R_0x1e60;
-+		break;
-+	case PHYDM_IC_AC:
-+		reg = R_0x994;
-+		break;
-+	case PHYDM_IC_N:
-+		reg = R_0x890;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	odm_set_bb_reg(dm, reg, BIT(2), 0);
-+	odm_set_bb_reg(dm, reg, BIT(2), 1);
-+
-+	ccx->fahm_trigger_time = dm->phydm_sys_up_time;
-+	ccx->fahm_rpt_stamp++;
-+	ccx->fahm_ongoing = true;
-+}
-+
-+boolean
-+phydm_fahm_check_rdy(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean is_ready = false;
-+	u32 reg = 0, reg_bit = 0;
-+
-+	switch (dm->ic_ip_series) {
-+	case PHYDM_IC_JGR3:
-+		reg = R_0x2d84;
-+		reg_bit = 31;
-+		break;
-+	case PHYDM_IC_AC:
-+		reg = R_0x1f98;
-+		reg_bit = 31;
-+		break;
-+	case PHYDM_IC_N:
-+		reg = R_0x9f0;
-+		reg_bit = 31;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (odm_get_bb_reg(dm, reg, BIT(reg_bit)))
-+		is_ready = true;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "FAHM rdy=%d\n", is_ready);
-+
-+	return is_ready;
-+}
-+
-+u8 phydm_fahm_cal_wgt_avg(void *dm_void, u8 start_i, u8 end_i, u16 r_sum,
-+			  u16 period)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 i = 0;
-+	u32 pwr_tmp = 0;
-+	u8 pwr = 0;
-+	u32 fahm_valid = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	if (r_sum == 0) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "rpt_sum = 0, don't need to update\n");
-+		return 0x0;
-+	} else if (end_i > NHM_RPT_NUM - 1) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "[WARNING]end_i is larger than 11!!\n");
-+		return 0x0;
-+	}
-+
-+	for (i = start_i; i <= end_i; i++) {
-+		if (i == 0)
-+			pwr_tmp += ccx->fahm_result[0] *
-+				   MAX_2(ccx->fahm_th[0] - 2, 0);
-+		else if (i == (NHM_RPT_NUM - 1))
-+			pwr_tmp += ccx->fahm_result[NHM_RPT_NUM - 1] *
-+				   (ccx->fahm_th[NHM_TH_NUM - 1] + 2);
-+		else
-+			pwr_tmp += ccx->fahm_result[i] *
-+				   (ccx->fahm_th[i - 1] + ccx->fahm_th[i]) >> 1;
-+	}
-+
-+	/* protection for the case of minus pwr(RSSI)*/
-+	pwr = (u8)(NTH_TH_2_RSSI(MAX_2(PHYDM_DIV(pwr_tmp, r_sum), 20)));
-+	fahm_valid = PHYDM_DIV(r_sum * 100, period);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "valid: ((%d)) percent, pwr(RSSI)=((%d))\n",
-+		  fahm_valid, pwr);
-+
-+	return pwr;
-+}
-+
-+void phydm_fahm_get_utility(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+
-+	if (ccx->fahm_rpt_sum >= ccx->fahm_result[0]) {
-+		ccx->fahm_pwr = phydm_fahm_cal_wgt_avg(dm, 0, NHM_RPT_NUM - 1,
-+						       ccx->fahm_rpt_sum,
-+						       ccx->fahm_period);
-+	} else {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "[warning] fahm_rpt_sum invalid\n");
-+		ccx->fahm_pwr = 0;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "fahm_pwr=%d\n", ccx->fahm_pwr);
-+}
-+
-+boolean
-+phydm_fahm_get_result(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u32 value32 = 0;
-+	u16 denom; /*fahm_denominator packet count*/
-+	u32 reg1 = 0;
-+	u32 reg2 = 0;
-+	u8 i = 0;
-+	u32 fahm_rpt_sum_tmp = 0;
-+
-+	switch (dm->ic_ip_series) {
-+	case PHYDM_IC_JGR3:
-+		reg1 = R_0x2d6c;
-+		reg2 = R_0x2d84;
-+		break;
-+	case PHYDM_IC_AC:
-+		reg1 = R_0x1f80;
-+		reg2 = R_0x1f98;
-+		break;
-+	case PHYDM_IC_N:
-+		reg1 = R_0x9d8;
-+		reg2 = R_0x9f0;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (!(phydm_fahm_check_rdy(dm))) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get FAHM report Fail\n");
-+		phydm_fahm_racing_release(dm);
-+		return false;
-+	}
-+
-+	/*@Get FAHM Denominator*/
-+	denom = (u16)odm_get_bb_reg(dm, reg2, MASKLWORD);
-+
-+	if (ccx->fahm_period >= 65530)
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "FAHM denominator = %d, valid: %d percent\n", denom,
-+			  (denom * 100) >> 16);
-+
-+	/*Get FAHM numerator and sum all fahm_result*/
-+	for (i = 0; i < 6; i++) {
-+		value32 = odm_get_bb_reg(dm, reg1 + (i << 2), MASKDWORD);
-+		ccx->fahm_result[i * 2] = (u16)(value32 & MASKLWORD);
-+		ccx->fahm_result[i * 2 + 1] = (u16)((value32 & MASKHWORD) >> 16);
-+		fahm_rpt_sum_tmp = (u32)(fahm_rpt_sum_tmp +
-+					 ccx->fahm_result[i * 2] +
-+					 ccx->fahm_result[i * 2 + 1]);
-+	}
-+
-+	ccx->fahm_rpt_sum = (u16)fahm_rpt_sum_tmp;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "FAHM_Rpt[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n",
-+		  ccx->fahm_rpt_stamp, ccx->fahm_result[11],
-+		  ccx->fahm_result[10], ccx->fahm_result[9],
-+		  ccx->fahm_result[8], ccx->fahm_result[7], ccx->fahm_result[6],
-+		  ccx->fahm_result[5], ccx->fahm_result[4], ccx->fahm_result[3],
-+		  ccx->fahm_result[2], ccx->fahm_result[1],
-+		  ccx->fahm_result[0]);
-+
-+	phydm_fahm_racing_release(dm);
-+
-+	if (fahm_rpt_sum_tmp > 0xffff) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "[Warning] Invalid FAHM RPT, total=%d\n",
-+			  fahm_rpt_sum_tmp);
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+void phydm_fahm_set_th_reg(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u32 val = 0;
-+
-+	/*Set FAHM threshold*/ /*Unit: PWdB U(8,1)*/
-+	switch (dm->ic_ip_series) {
-+	case PHYDM_IC_JGR3:
-+		val = BYTE_2_DWORD(ccx->fahm_th[3], ccx->fahm_th[2],
-+				   ccx->fahm_th[1], ccx->fahm_th[0]);
-+		odm_set_bb_reg(dm, R_0x1e50, MASKDWORD, val);
-+		val = BYTE_2_DWORD(ccx->fahm_th[7], ccx->fahm_th[6],
-+				   ccx->fahm_th[5], ccx->fahm_th[4]);
-+		odm_set_bb_reg(dm, R_0x1e54, MASKDWORD, val);
-+		val = BYTE_2_DWORD(0, ccx->fahm_th[10], ccx->fahm_th[9],
-+				   ccx->fahm_th[8]);
-+		odm_set_bb_reg(dm, R_0x1e58, 0xffffff, val);
-+		break;
-+	case PHYDM_IC_AC:
-+		val = BYTE_2_DWORD(0, ccx->fahm_th[2], ccx->fahm_th[1],
-+				   ccx->fahm_th[0]);
-+		odm_set_bb_reg(dm, R_0x1c38, 0xffffff00, val);
-+		val = BYTE_2_DWORD(0, ccx->fahm_th[5], ccx->fahm_th[4],
-+				   ccx->fahm_th[3]);
-+		odm_set_bb_reg(dm, R_0x1c78, 0xffffff00, val);
-+		val = BYTE_2_DWORD(0, 0, ccx->fahm_th[7], ccx->fahm_th[6]);
-+		odm_set_bb_reg(dm, R_0x1c7c, 0xffff0000, val);
-+		val = BYTE_2_DWORD(0, ccx->fahm_th[10], ccx->fahm_th[9],
-+				   ccx->fahm_th[8]);
-+		odm_set_bb_reg(dm, R_0x1cb8, 0xffffff00, val);
-+		break;
-+	case PHYDM_IC_N:
-+		val = BYTE_2_DWORD(ccx->fahm_th[3], ccx->fahm_th[2],
-+				   ccx->fahm_th[1], ccx->fahm_th[0]);
-+		odm_set_bb_reg(dm, R_0x970, MASKDWORD, val);
-+		val = BYTE_2_DWORD(ccx->fahm_th[7], ccx->fahm_th[6],
-+				   ccx->fahm_th[5], ccx->fahm_th[4]);
-+		odm_set_bb_reg(dm, R_0x974, MASKDWORD, val);
-+		val = BYTE_2_DWORD(0, ccx->fahm_th[10], ccx->fahm_th[9],
-+				   ccx->fahm_th[8]);
-+		odm_set_bb_reg(dm, R_0x978, 0xffffff, val);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "Update FAHM_th[H->L]=[%d %d %d %d %d %d %d %d %d %d %d]\n",
-+		  ccx->fahm_th[10], ccx->fahm_th[9], ccx->fahm_th[8],
-+		  ccx->fahm_th[7], ccx->fahm_th[6], ccx->fahm_th[5],
-+		  ccx->fahm_th[4], ccx->fahm_th[3], ccx->fahm_th[2],
-+		  ccx->fahm_th[1], ccx->fahm_th[0]);
-+}
-+
-+boolean
-+phydm_fahm_th_update_chk(void *dm_void, enum fahm_application fahm_app,
-+			 u8 *fahm_th, u32 *igi_new, boolean en_1db_mode,
-+			 u8 fahm_th0_manual)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	boolean is_update = false;
-+	u8 igi_curr = phydm_get_igi(dm, BB_PATH_A);
-+	u8 i = 0;
-+	u8 th_tmp = igi_curr - CCA_CAP;
-+	u8 th_step = 2;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "fahm_th_update_chk : App=%d, fahm_igi=0x%x, igi_curr=0x%x\n",
-+		  fahm_app, ccx->fahm_igi, igi_curr);
-+
-+	if (igi_curr < 0x10) /* Protect for invalid IGI*/
-+		return false;
-+
-+	switch (fahm_app) {
-+	case FAHM_BACKGROUND: /*Get IGI from driver parameter(cur_ig_value)*/
-+		if (ccx->fahm_igi != igi_curr || ccx->fahm_app != fahm_app) {
-+			is_update = true;
-+			*igi_new = (u32)igi_curr;
-+
-+			fahm_th[0] = (u8)IGI_2_NHM_TH(th_tmp);
-+
-+			for (i = 1; i <= 10; i++)
-+				fahm_th[i] = fahm_th[0] +
-+					    IGI_2_NHM_TH(th_step * i);
-+
-+		}
-+		break;
-+	case FAHM_ACS:
-+		if (ccx->fahm_igi != igi_curr || ccx->fahm_app != fahm_app) {
-+			is_update = true;
-+			*igi_new = (u32)igi_curr;
-+			fahm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - CCA_CAP);
-+			for (i = 1; i <= 10; i++)
-+				fahm_th[i] = fahm_th[0] + IGI_2_NHM_TH(2 * i);
-+		}
-+		break;
-+	case FAHM_DBG: /*Get IGI from register*/
-+		igi_curr = phydm_get_igi(dm, BB_PATH_A);
-+		if (ccx->fahm_igi != igi_curr || ccx->fahm_app != fahm_app) {
-+			is_update = true;
-+			*igi_new = (u32)igi_curr;
-+			if (en_1db_mode) {
-+				fahm_th[0] = (u8)IGI_2_NHM_TH(fahm_th0_manual +
-+							      10);
-+				th_step = 1;
-+			} else {
-+				fahm_th[0] = (u8)IGI_2_NHM_TH(igi_curr -
-+							      CCA_CAP);
-+			}
-+
-+			for (i = 1; i <= 10; i++)
-+				fahm_th[i] = fahm_th[0] +
-+					     IGI_2_NHM_TH(th_step * i);
-+		}
-+		break;
-+	}
-+
-+	if (is_update) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "[Update FAHM_TH] igi_RSSI=%d\n",
-+			  IGI_2_RSSI(*igi_new));
-+
-+		for (i = 0; i < NHM_TH_NUM; i++)
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "FAHM_th[%d](RSSI) = %d\n",
-+				  i, NTH_TH_2_RSSI(fahm_th[i]));
-+	} else {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "No need to update FAHM_TH\n");
-+	}
-+	return is_update;
-+}
-+
-+void phydm_fahm_set(void *dm_void, enum fahm_opt_fa inclu_fa,
-+		    enum fahm_opt_crc32_ok inclu_crc32_ok,
-+		    enum fahm_opt_crc32_err inclu_crc32_err,
-+		    enum fahm_application app, u16 period, boolean en_1db_mode,
-+		    u8 th0_manual)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 fahm_th[NHM_TH_NUM] = {0};
-+	u32 igi = 0x20;
-+	u32 reg1 = 0, reg2 = 0, reg3 = 0;
-+	u32 val_tmp = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "incld{fa, crc32_ok, crc32_err}={%d, %d, %d}, period=%d\n",
-+		  inclu_fa, inclu_crc32_ok, inclu_crc32_err, period);
-+
-+	switch (dm->ic_ip_series) {
-+	case PHYDM_IC_JGR3:
-+		reg1 = R_0x1e60;
-+		reg2 = R_0x1e58;
-+		reg3 = R_0x1e5c;
-+		break;
-+	case PHYDM_IC_AC:
-+		reg1 = R_0x994;
-+		reg2 = R_0x1cf8;
-+		break;
-+	case PHYDM_IC_N:
-+		reg1 = R_0x890;
-+		reg2 = R_0x978;
-+		reg3 = R_0x97c;
-+		break;
-+	default:
-+		 break;
-+	}
-+
-+	/*Set enable fa, ignore crc32 ok, ignore crc32 err*/
-+	if (inclu_fa != ccx->fahm_incld_fa ||
-+	    inclu_crc32_ok != ccx->fahm_incld_crc32_ok ||
-+	    inclu_crc32_err != ccx->fahm_incld_crc32_err) {
-+		val_tmp = (u32)((inclu_crc32_err << 2) | (inclu_crc32_ok << 1) |
-+			  inclu_fa);
-+		odm_set_bb_reg(dm, reg1, 0xe0, val_tmp);
-+		ccx->fahm_incld_fa = inclu_fa;
-+		ccx->fahm_incld_crc32_ok = inclu_crc32_ok;
-+		ccx->fahm_incld_crc32_err = inclu_crc32_err;
-+	}
-+
-+	/*Set FAHM period*/
-+	if (period != ccx->fahm_period) {
-+		switch (dm->ic_ip_series) {
-+		case PHYDM_IC_AC:
-+			odm_set_bb_reg(dm, reg2, 0xffff00, period);
-+			break;
-+		case PHYDM_IC_JGR3:
-+		case PHYDM_IC_N:
-+			odm_set_bb_reg(dm, reg2, 0xff000000, (period & 0xff));
-+			odm_set_bb_reg(dm, reg3, 0xff, (period & 0xff00) >> 8);
-+			break;
-+		default:
-+			break;
-+		}
-+
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "Update FAHM period ((%d)) -> ((%d))\n",
-+			  ccx->fahm_period, period);
-+
-+		ccx->fahm_period = period;
-+	}
-+
-+	/*Set FAHM threshold*/
-+	if (phydm_fahm_th_update_chk(dm, app, &fahm_th[0], &igi, en_1db_mode,
-+				     th0_manual)) {
-+		/*Pause IGI*/
-+		if (app == FAHM_BACKGROUND || app == FAHM_ACS) {
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "DIG Free Run\n");
-+		} else if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE,
-+					    PHYDM_PAUSE_LEVEL_1, 1, &igi)
-+					    == PAUSE_FAIL) {
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG Fail\n");
-+			return;
-+		} else {
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG=0x%x\n", igi);
-+		}
-+		ccx->fahm_app = app;
-+		ccx->fahm_igi = (u8)igi;
-+		odm_move_memory(dm, &ccx->fahm_th[0], &fahm_th, NHM_TH_NUM);
-+
-+		/*Set FAHM th*/
-+		phydm_fahm_set_th_reg(dm);
-+	}
-+}
-+
-+boolean
-+phydm_fahm_mntr_set(void *dm_void, struct fahm_para_info *para)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u16 fahm_time = 0; /*unit: 4us*/
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	if (para->mntr_time == 0)
-+		return false;
-+
-+	if (para->lv >= FAHM_MAX_NUM) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Wrong LV=%d\n", para->lv);
-+		return false;
-+	}
-+
-+	if (phydm_fahm_racing_ctrl(dm, para->lv) == PHYDM_SET_FAIL)
-+		return false;
-+
-+	if (para->mntr_time >= 262)
-+		fahm_time = NHM_PERIOD_MAX;
-+	else
-+		fahm_time = para->mntr_time * MS_TO_4US_RATIO;
-+
-+	phydm_fahm_set(dm, para->incld_fa, para->incld_crc32_ok,
-+		       para->incld_crc32_err, para->app, fahm_time,
-+		       para->en_1db_mode, para->th0_manual);
-+
-+	return true;
-+}
-+
-+boolean
-+phydm_fahm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	struct fahm_para_info para = {0};
-+	boolean fahm_chk_result = false;
-+	boolean fahm_polling_result = false;
-+	u32 sys_return_time = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	if (ccx->fahm_manual_ctrl) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "FAHM in manual ctrl\n");
-+		return fahm_chk_result;
-+	}
-+	sys_return_time = ccx->fahm_trigger_time + MAX_ENV_MNTR_TIME;
-+	if (ccx->fahm_app != FAHM_BACKGROUND &&
-+	    (sys_return_time > dm->phydm_sys_up_time)) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "fahm_app=%d, trigger_time %d, sys_time=%d\n",
-+			  ccx->fahm_app, ccx->fahm_trigger_time,
-+			  dm->phydm_sys_up_time);
-+
-+		return fahm_chk_result;
-+	}
-+
-+	/*[FAHM get result & calculate Utility]---------------------------*/
-+	fahm_polling_result = phydm_fahm_get_result(dm);
-+	if (fahm_polling_result) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get FAHM_rpt success\n");
-+		phydm_fahm_get_utility(dm);
-+	}
-+
-+	/*[FAHM trigger setting]------------------------------------------*/
-+	para.incld_fa = FAHM_INCLUDE_FA;
-+	para.incld_crc32_ok = FAHM_EXCLUDE_CRC32_OK;
-+	para.incld_crc32_err = FAHM_EXCLUDE_CRC32_ERR;
-+	para.app = FAHM_BACKGROUND;
-+	para.lv = FAHM_LV_1;
-+	para.en_1db_mode = false;
-+	para.mntr_time = monitor_time;
-+
-+	fahm_chk_result = phydm_fahm_mntr_set(dm, &para);
-+
-+	return fahm_chk_result;
-+}
-+
-+void phydm_fahm_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 denum_sel = 0;
-+	u32 reg = 0;
-+
-+	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_FAHM))
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	ccx->fahm_app = FAHM_BACKGROUND;
-+	ccx->fahm_igi = 0xff;
-+
-+	/*Set FAHM threshold*/
-+	ccx->fahm_ongoing = false;
-+	ccx->fahm_set_lv = FAHM_RELEASE;
-+
-+	if (phydm_fahm_th_update_chk(dm, ccx->fahm_app, &ccx->fahm_th[0],
-+				    (u32 *)&ccx->fahm_igi, false, 0))
-+		phydm_fahm_set_th_reg(dm);
-+
-+	ccx->fahm_period = 0;
-+
-+	ccx->fahm_incld_fa = FAHM_FA_INIT;
-+	ccx->fahm_incld_crc32_ok = FAHM_CRC32_OK_INIT;
-+	ccx->fahm_incld_crc32_err = FAHM_CRC32_ERR_INIT;
-+
-+	ccx->fahm_manual_ctrl = 0;
-+	ccx->fahm_rpt_stamp = 0;
-+
-+	switch (dm->ic_ip_series) {
-+	case PHYDM_IC_JGR3:
-+		reg = R_0x1e60;
-+		break;
-+	case PHYDM_IC_AC:
-+		reg = R_0x994;
-+		break;
-+	case PHYDM_IC_N:
-+		reg = R_0x890;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	/*enable CCK/OFDM CRC32 check*/
-+	odm_set_bb_reg(dm, reg, 0x18, 0x3);
-+	/*denominator:FA/CRC32_OK/CRC32_ERR*/
-+	odm_set_bb_reg(dm, reg, 0x7000, 0x7);
-+}
-+
-+void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
-+		    u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	struct fahm_para_info para = {0};
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u16 result_tmp = 0;
-+	u8 i = 0;
-+
-+	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_FAHM))
-+		return;
-+
-+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "FAHM Basic-Trigger 262ms: {1}\n");
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "FAHM Adv-Trigger: {2} {Include FA} {Include CRC32 ok} {Include CRC32 Err}\n {App:1 for dbg} {LV:1~4} {0~262ms}, 1dB mode :{en} {t[0](RSSI)}\n");
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "FAHM Get Result: {100}\n");
-+	} else if (var1[0] == 100) { /*Get FAHM results*/
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "IGI=0x%x, rpt_stamp=%d\n", ccx->fahm_igi,
-+			 ccx->fahm_rpt_stamp);
-+
-+		if (phydm_fahm_get_result(dm)) {
-+			for (i = 0; i < NHM_RPT_NUM; i++) {
-+				result_tmp = ccx->fahm_result[i];
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used,
-+					 "fahm_rpt[%d] = %d (%d percent)\n",
-+					 i, result_tmp,
-+					 (((result_tmp * 100) + 32768) >> 16));
-+			}
-+			phydm_fahm_get_utility(dm);
-+
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "fahm_pwr=%d\n", ccx->fahm_pwr);
-+		} else {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Get FAHM_rpt Fail\n");
-+		}
-+		ccx->fahm_manual_ctrl = 0;
-+	} else { /*FAMH trigger*/
-+		ccx->fahm_manual_ctrl = 1;
-+
-+		for (i = 1; i < 9; i++)
-+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
-+
-+		if (var1[0] == 1) {
-+			para.incld_fa = FAHM_INCLUDE_FA;
-+			para.incld_crc32_ok = FAHM_EXCLUDE_CRC32_OK;
-+			para.incld_crc32_err = FAHM_EXCLUDE_CRC32_ERR;
-+			para.app = FAHM_DBG;
-+			para.lv = FAHM_LV_4;
-+			para.mntr_time = 262;
-+			para.en_1db_mode = false;
-+			para.th0_manual = 0;
-+		} else {
-+			para.incld_fa = (enum fahm_opt_fa)var1[1];
-+			para.incld_crc32_ok = (enum fahm_opt_crc32_ok)var1[2];
-+			para.incld_crc32_err = (enum fahm_opt_crc32_err)var1[3];
-+			para.app = (enum fahm_application)var1[4];
-+			para.lv = (enum phydm_fahm_level)var1[5];
-+			para.mntr_time = (u16)var1[6];
-+			para.en_1db_mode = (boolean)var1[7];
-+			para.th0_manual = (u8)var1[8];
-+		}
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "fa=%d, crc32_ok=%d, crc32_err=%d, app=%d, lv=%d, time=%d ms\n",
-+			 para.incld_fa, para.incld_crc32_ok,
-+			 para.incld_crc32_err, para.app, para.lv,
-+			 para.mntr_time);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "en_1db_mode=%d, th0(for 1db mode)=%d\n",
-+			 para.en_1db_mode, para.th0_manual);
-+
-+		if (phydm_fahm_mntr_set(dm, &para))
-+			phydm_fahm_trigger(dm);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "IGI=0x%x, rpt_stamp=%d\n", ccx->fahm_igi,
-+			 ccx->fahm_rpt_stamp);
-+
-+		for (i = 0; i < NHM_TH_NUM; i++)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "FAHM_th[%d] RSSI = %d\n", i,
-+				 NTH_TH_2_RSSI(ccx->fahm_th[i]));
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_fahm_watchdog(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	boolean fahm_chk_ok = false;
-+
-+	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_FAHM))
-+		return;
-+
-+	fahm_chk_ok = phydm_fahm_mntr_chk(dm, 262);
-+
-+	if (fahm_chk_ok)
-+		phydm_fahm_trigger(dm);
-+}
-+
-+
-+#endif /*#ifdef FAHM_SUPPORT*/
-+
-+#ifdef NHM_SUPPORT
-+
-+void phydm_nhm_racing_release(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u32 value32 = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "lv:(%d)->(0)\n", ccx->nhm_set_lv);
-+
-+	ccx->nhm_ongoing = false;
-+	ccx->nhm_set_lv = NHM_RELEASE;
-+
-+	if (!(ccx->nhm_app == NHM_BACKGROUND || ccx->nhm_app == NHM_ACS)) {
-+		phydm_pause_func(dm, F00_DIG, PHYDM_RESUME,
-+				 PHYDM_PAUSE_LEVEL_1, 1, &value32);
-+	}
-+
-+	ccx->nhm_app = NHM_BACKGROUND;
-+}
-+
-+u8 phydm_nhm_racing_ctrl(void *dm_void, enum phydm_nhm_level nhm_lv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 set_result = PHYDM_SET_SUCCESS;
-+	/*@acquire to control NHM API*/
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_ongoing=%d, lv:(%d)->(%d)\n",
-+		  ccx->nhm_ongoing, ccx->nhm_set_lv, nhm_lv);
-+	if (ccx->nhm_ongoing) {
-+		if (nhm_lv <= ccx->nhm_set_lv) {
-+			set_result = PHYDM_SET_FAIL;
-+		} else {
-+			phydm_ccx_hw_restart(dm);
-+			ccx->nhm_ongoing = false;
-+		}
-+	}
-+
-+	if (set_result)
-+		ccx->nhm_set_lv = nhm_lv;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm racing success=%d\n", set_result);
-+	return set_result;
-+}
-+
-+void phydm_nhm_trigger(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u32 nhm_reg1 = 0;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-+		nhm_reg1 = R_0x994;
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		nhm_reg1 = R_0x1e60;
-+	#endif
-+	else
-+		nhm_reg1 = R_0x890;
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	/* @Trigger NHM*/
-+	pdm_set_reg(dm, nhm_reg1, BIT(1), 0);
-+	pdm_set_reg(dm, nhm_reg1, BIT(1), 1);
-+	ccx->nhm_trigger_time = dm->phydm_sys_up_time;
-+	ccx->nhm_rpt_stamp++;
-+	ccx->nhm_ongoing = true;
-+}
-+
-+boolean
-+phydm_nhm_check_rdy(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean is_ready = false;
-+	u32 reg1 = 0, reg1_bit = 0;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		reg1 = R_0xfb4;
-+		reg1_bit = 16;
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		reg1 = R_0x2d4c;
-+		reg1_bit = 16;
-+	#endif
-+	} else {
-+		reg1 = R_0x8b4;
-+		if (dm->support_ic_type & (ODM_RTL8710B | ODM_RTL8721D |
-+					ODM_RTL8710C))
-+			reg1_bit = 25;
-+		else
-+			reg1_bit = 17;
-+	}
-+	if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit)))
-+		is_ready = true;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM rdy=%d\n", is_ready);
-+
-+	return is_ready;
-+}
-+
-+void phydm_nhm_cal_wgt(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 i = 0;
-+
-+	for (i = 0; i < NHM_RPT_NUM; i++) {
-+		if (i == 0)
-+			ccx->nhm_wgt[0] = (u8)(MAX_2(ccx->nhm_th[0] - 2, 0));
-+		else if (i == (NHM_RPT_NUM - 1))
-+			ccx->nhm_wgt[NHM_RPT_NUM - 1] = (u8)(ccx->nhm_th[NHM_TH_NUM - 1] + 2);
-+		else
-+			ccx->nhm_wgt[i] = (u8)((ccx->nhm_th[i - 1] + ccx->nhm_th[i]) >> 1);
-+	}
-+}
-+
-+u8 phydm_nhm_cal_wgt_avg(void *dm_void, u8 start_i, u8 end_i, u8 n_sum)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 i = 0;
-+	u32 noise_tmp = 0;
-+	u8 noise = 0;
-+	u32 nhm_valid = 0;
-+
-+	if (n_sum == 0) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "n_sum = 0, don't need to update noise\n");
-+		return 0x0;
-+	} else if (end_i > NHM_RPT_NUM - 1) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "[WARNING]end_i is larger than 11!!\n");
-+		return 0x0;
-+	}
-+
-+	for (i = start_i; i <= end_i; i++)
-+		noise_tmp += ccx->nhm_result[i] * ccx->nhm_wgt[i];
-+
-+	/* protection for the case of minus noise(RSSI)*/
-+	noise = (u8)(NTH_TH_2_RSSI(MAX_2(PHYDM_DIV(noise_tmp, n_sum), 20)));
-+	nhm_valid = (n_sum * 100) >> 8;
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "cal wgt_avg : valid: ((%d)) percent, noise(RSSI)=((%d))\n",
-+		  nhm_valid, noise);
-+
-+	return noise;
-+}
-+
-+u8 phydm_nhm_cal_nhm_env(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 first_idx = 0;
-+	u8 nhm_env = 0;
-+	u8 i = 0;
-+
-+	nhm_env = ccx->nhm_rpt_sum;
-+
-+	/*search first cluster*/
-+	for (i = 0; i < NHM_RPT_NUM; i++) {
-+		if (ccx->nhm_result[i]) {
-+			first_idx = i;
-+			break;
-+		}
-+	}
-+
-+	/*exclude first cluster under -80dBm*/
-+	for (i = 0; i < 4; i++) {
-+		if (((first_idx + i) < NHM_RPT_NUM) &&
-+		    (ccx->nhm_wgt[first_idx + i] <= NHM_IC_NOISE_TH))
-+			nhm_env -= ccx->nhm_result[first_idx + i];
-+	}
-+
-+	/*exclude nhm_rpt[0] above -80dBm*/
-+	if (ccx->nhm_wgt[0] > NHM_IC_NOISE_TH)
-+		nhm_env -= ccx->nhm_result[0];
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "cal nhm_env: first_idx=%d, nhm_env=%d\n",
-+		  first_idx, nhm_env);
-+
-+	return nhm_env;
-+}
-+
-+void phydm_nhm_get_utility(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 nhm_rpt_non_0 = 0;
-+	u8 nhm_rpt_non_11 = 0;
-+	u8 nhm_env = 0;
-+
-+	if (ccx->nhm_rpt_sum >= ccx->nhm_result[0]) {
-+		phydm_nhm_cal_wgt(dm);
-+
-+		nhm_rpt_non_0 = ccx->nhm_rpt_sum - ccx->nhm_result[0];
-+		nhm_rpt_non_11 = ccx->nhm_rpt_sum - ccx->nhm_result[11];
-+		/*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/
-+		nhm_env = phydm_nhm_cal_nhm_env(dm);
-+		ccx->nhm_ratio = (nhm_rpt_non_0 * 100) >> 8;
-+		ccx->nhm_env_ratio = (nhm_env * 100) >> 8;
-+		ccx->nhm_level_valid = (nhm_rpt_non_11 * 100) >> 8;
-+		ccx->nhm_level = phydm_nhm_cal_wgt_avg(dm, 0, NHM_RPT_NUM - 2,
-+						     nhm_rpt_non_11);
-+		ccx->nhm_pwr = phydm_nhm_cal_wgt_avg(dm, 0, NHM_RPT_NUM - 1,
-+						     ccx->nhm_rpt_sum);
-+	} else {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "[warning] nhm_rpt_sum invalid\n");
-+		ccx->nhm_ratio = 0;
-+		ccx->nhm_env_ratio = 0;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "nhm_ratio=%d, nhm_env_ratio=%d, nhm_level=%d, nhm_pwr=%d\n",
-+		  ccx->nhm_ratio, ccx->nhm_env_ratio, ccx->nhm_level,
-+		  ccx->nhm_pwr);
-+}
-+
-+boolean
-+phydm_nhm_get_result(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u32 value32 = 0;
-+	u8 i = 0;
-+	u32 nhm_reg1 = 0;
-+	u16 nhm_rpt_sum_tmp = 0;
-+	u16 nhm_duration = 0;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-+		nhm_reg1 = R_0x994;
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		nhm_reg1 = R_0x1e60;
-+	#endif
-+	else
-+		nhm_reg1 = R_0x890;
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	if (!(dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
-+				     ODM_RTL8197G | ODM_RTL8723F)))
-+		pdm_set_reg(dm, nhm_reg1, BIT(1), 0);
-+
-+	if (!(phydm_nhm_check_rdy(dm))) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM report Fail\n");
-+		phydm_nhm_racing_release(dm);
-+		return false;
-+	}
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		value32 = odm_read_4byte(dm, R_0xfa8);
-+		odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4);
-+
-+		value32 = odm_read_4byte(dm, R_0xfac);
-+		odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4);
-+
-+		value32 = odm_read_4byte(dm, R_0xfb0);
-+		odm_move_memory(dm, &ccx->nhm_result[8], &value32, 4);
-+
-+		/*@Get NHM duration*/
-+		value32 = odm_read_4byte(dm, R_0xfb4);
-+		nhm_duration = (u16)(value32 & MASKLWORD);
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		value32 = odm_read_4byte(dm, R_0x2d40);
-+		odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4);
-+
-+		value32 = odm_read_4byte(dm, R_0x2d44);
-+		odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4);
-+
-+		value32 = odm_read_4byte(dm, R_0x2d48);
-+		odm_move_memory(dm, &ccx->nhm_result[8], &value32, 4);
-+
-+		/*@Get NHM duration*/
-+		value32 = odm_read_4byte(dm, R_0x2d4c);
-+		nhm_duration = (u16)(value32 & MASKLWORD);
-+	#endif
-+	} else {
-+		value32 = odm_read_4byte(dm, R_0x8d8);
-+		odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4);
-+
-+		value32 = odm_read_4byte(dm, R_0x8dc);
-+		odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4);
-+
-+		value32 = odm_get_bb_reg(dm, R_0x8d0, 0xffff0000);
-+		odm_move_memory(dm, &ccx->nhm_result[8], &value32, 2);
-+
-+		value32 = odm_read_4byte(dm, R_0x8d4);
-+
-+		ccx->nhm_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
-+		ccx->nhm_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
-+
-+		/*@Get NHM duration*/
-+		nhm_duration = (u16)(value32 & MASKLWORD);
-+	}
-+
-+	/* sum all nhm_result */
-+	if (ccx->nhm_period >= 65530)
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "NHM valid time = %d, valid: %d percent\n",
-+			  nhm_duration, (nhm_duration * 100) >> 16);
-+
-+	for (i = 0; i < NHM_RPT_NUM; i++)
-+		nhm_rpt_sum_tmp = (u16)(nhm_rpt_sum_tmp + ccx->nhm_result[i]);
-+
-+	ccx->nhm_rpt_sum = (u8)nhm_rpt_sum_tmp;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "NHM_Rpt[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n",
-+		  ccx->nhm_rpt_stamp, ccx->nhm_result[11], ccx->nhm_result[10],
-+		  ccx->nhm_result[9], ccx->nhm_result[8], ccx->nhm_result[7],
-+		  ccx->nhm_result[6], ccx->nhm_result[5], ccx->nhm_result[4],
-+		  ccx->nhm_result[3], ccx->nhm_result[2], ccx->nhm_result[1],
-+		  ccx->nhm_result[0]);
-+
-+	phydm_nhm_racing_release(dm);
-+
-+	if (nhm_rpt_sum_tmp > 255) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "[Warning] Invalid NHM RPT, total=%d\n",
-+			  nhm_rpt_sum_tmp);
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+void phydm_nhm_set_th_reg(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u32 reg1 = 0, reg2 = 0, reg3 = 0, reg4 = 0, reg4_bit = 0;
-+	u32 val = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		reg1 = R_0x994;
-+		reg2 = R_0x998;
-+		reg3 = R_0x99c;
-+		reg4 = R_0x9a0;
-+		reg4_bit = MASKBYTE0;
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		reg1 = R_0x1e60;
-+		reg2 = R_0x1e44;
-+		reg3 = R_0x1e48;
-+		reg4 = R_0x1e5c;
-+		reg4_bit = MASKBYTE2;
-+	#endif
-+	} else {
-+		reg1 = R_0x890;
-+		reg2 = R_0x898;
-+		reg3 = R_0x89c;
-+		reg4 = R_0xe28;
-+		reg4_bit = MASKBYTE0;
-+	}
-+
-+	/*Set NHM threshold*/ /*Unit: PWdB U(8,1)*/
-+	val = BYTE_2_DWORD(ccx->nhm_th[3], ccx->nhm_th[2],
-+			   ccx->nhm_th[1], ccx->nhm_th[0]);
-+	pdm_set_reg(dm, reg2, MASKDWORD, val);
-+	val = BYTE_2_DWORD(ccx->nhm_th[7], ccx->nhm_th[6],
-+			   ccx->nhm_th[5], ccx->nhm_th[4]);
-+	pdm_set_reg(dm, reg3, MASKDWORD, val);
-+	pdm_set_reg(dm, reg4, reg4_bit, ccx->nhm_th[8]);
-+	val = BYTE_2_DWORD(0, 0, ccx->nhm_th[10], ccx->nhm_th[9]);
-+	pdm_set_reg(dm, reg1, 0xffff0000, val);
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "Update NHM_th[H->L]=[%d %d %d %d %d %d %d %d %d %d %d]\n",
-+		  ccx->nhm_th[10], ccx->nhm_th[9], ccx->nhm_th[8],
-+		  ccx->nhm_th[7], ccx->nhm_th[6], ccx->nhm_th[5],
-+		  ccx->nhm_th[4], ccx->nhm_th[3], ccx->nhm_th[2],
-+		  ccx->nhm_th[1], ccx->nhm_th[0]);
-+}
-+
-+boolean
-+phydm_nhm_th_update_chk(void *dm_void, enum nhm_application nhm_app, u8 *nhm_th,
-+			u32 *igi_new, boolean en_1db_mode, u8 nhm_th0_manual)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	boolean is_update = false;
-+	u8 igi_curr = phydm_get_igi(dm, BB_PATH_A);
-+	u8 nhm_igi_th_11k_low[NHM_TH_NUM] = {0x12, 0x15, 0x18, 0x1b, 0x1e,
-+					     0x23, 0x28, 0x2c, 0x78,
-+					     0x78, 0x78};
-+	u8 nhm_igi_th_11k_high[NHM_TH_NUM] = {0x1e, 0x23, 0x28, 0x2d, 0x32,
-+					      0x37, 0x78, 0x78, 0x78, 0x78,
-+					      0x78};
-+	u8 nhm_igi_th_xbox[NHM_TH_NUM] = {0x1a, 0x2c, 0x2e, 0x30, 0x32, 0x34,
-+					  0x36, 0x38, 0x3a, 0x3c, 0x3d};
-+	u8 i = 0;
-+	u8 th_tmp = igi_curr - CCA_CAP;
-+	u8 th_step = 2;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "App=%d, nhm_igi=0x%x, igi_curr=0x%x\n",
-+		  nhm_app, ccx->nhm_igi, igi_curr);
-+
-+	if (igi_curr < 0x10) /* Protect for invalid IGI*/
-+		return false;
-+
-+	switch (nhm_app) {
-+	case NHM_BACKGROUND: /* @Get IGI form driver parameter(cur_ig_value)*/
-+		if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) {
-+			is_update = true;
-+			*igi_new = (u32)igi_curr;
-+
-+			#ifdef NHM_DYM_PW_TH_SUPPORT
-+			if (ccx->nhm_dym_pw_th_en) {
-+				th_tmp = MAX_2(igi_curr - DYM_PWTH_CCA_CAP, 0);
-+				th_step = 3;
-+			}
-+			#endif
-+
-+			nhm_th[0] = (u8)IGI_2_NHM_TH(th_tmp);
-+
-+			for (i = 1; i <= 10; i++)
-+				nhm_th[i] = nhm_th[0] +
-+					    IGI_2_NHM_TH(th_step * i);
-+
-+		}
-+		break;
-+
-+	case NHM_ACS:
-+		if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) {
-+			is_update = true;
-+			*igi_new = (u32)igi_curr;
-+			nhm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - CCA_CAP);
-+			for (i = 1; i <= 10; i++)
-+				nhm_th[i] = nhm_th[0] + IGI_2_NHM_TH(2 * i);
-+		}
-+		break;
-+
-+	case IEEE_11K_HIGH:
-+		is_update = true;
-+		*igi_new = 0x2c;
-+		for (i = 0; i < NHM_TH_NUM; i++)
-+			nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_11k_high[i]);
-+		break;
-+
-+	case IEEE_11K_LOW:
-+		is_update = true;
-+		*igi_new = 0x20;
-+		for (i = 0; i < NHM_TH_NUM; i++)
-+			nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_11k_low[i]);
-+		break;
-+
-+	case INTEL_XBOX:
-+		is_update = true;
-+		*igi_new = 0x36;
-+		for (i = 0; i < NHM_TH_NUM; i++)
-+			nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_xbox[i]);
-+		break;
-+
-+	case NHM_DBG: /*@Get IGI form register*/
-+		igi_curr = phydm_get_igi(dm, BB_PATH_A);
-+		if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) {
-+			is_update = true;
-+			*igi_new = (u32)igi_curr;
-+			if (en_1db_mode) {
-+				nhm_th[0] = (u8)IGI_2_NHM_TH(nhm_th0_manual +
-+							     10);
-+				th_step = 1;
-+			} else {
-+				nhm_th[0] = (u8)IGI_2_NHM_TH(igi_curr -
-+							     CCA_CAP);
-+			}
-+
-+			for (i = 1; i <= 10; i++)
-+				nhm_th[i] = nhm_th[0] + IGI_2_NHM_TH(th_step *
-+					    i);
-+		}
-+		break;
-+	}
-+
-+	if (is_update) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "[Update NHM_TH] igi_RSSI=%d\n",
-+			  IGI_2_RSSI(*igi_new));
-+
-+		for (i = 0; i < NHM_TH_NUM; i++) {
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM_th[%d](RSSI) = %d\n",
-+				  i, NTH_TH_2_RSSI(nhm_th[i]));
-+		}
-+	} else {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "No need to update NHM_TH\n");
-+	}
-+	return is_update;
-+}
-+
-+void phydm_nhm_set(void *dm_void, enum nhm_option_txon_all include_tx,
-+		   enum nhm_option_cca_all include_cca,
-+		   enum nhm_divider_opt_all divi_opt,
-+		   enum nhm_application nhm_app, u16 period,
-+		   boolean en_1db_mode, u8 nhm_th0_manual)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 nhm_th[NHM_TH_NUM] = {0};
-+	u32 igi = 0x20;
-+	u32 reg1 = 0, reg2 = 0;
-+	u32 val_tmp = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "incld{tx, cca}={%d, %d}, divi_opt=%d, period=%d\n",
-+		  include_tx, include_cca, divi_opt, period);
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		reg1 = R_0x994;
-+		reg2 = R_0x990;
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		reg1 = R_0x1e60;
-+		reg2 = R_0x1e40;
-+	#endif
-+	} else {
-+		reg1 = R_0x890;
-+		reg2 = R_0x894;
-+	}
-+
-+	/*Set disable_ignore_cca, disable_ignore_txon, ccx_en*/
-+	if (include_tx != ccx->nhm_include_txon ||
-+	    include_cca != ccx->nhm_include_cca ||
-+	    divi_opt != ccx->nhm_divider_opt) {
-+	    /* some old ic is not supported on NHM divider option */
-+		if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B |
-+		    ODM_RTL8195A | ODM_RTL8192E)) {
-+			val_tmp = (u32)((include_tx << 2) |
-+				  (include_cca << 1) | 1);
-+			pdm_set_reg(dm, reg1, 0x700, val_tmp);
-+		} else {
-+			val_tmp = (u32)BIT_2_BYTE(divi_opt, include_tx,
-+				  include_cca, 1);
-+			pdm_set_reg(dm, reg1, 0xf00, val_tmp);
-+		}
-+		ccx->nhm_include_txon = include_tx;
-+		ccx->nhm_include_cca = include_cca;
-+		ccx->nhm_divider_opt = divi_opt;
-+	}
-+
-+	/*Set NHM period*/
-+	if (period != ccx->nhm_period) {
-+		pdm_set_reg(dm, reg2, MASKHWORD, period);
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "Update NHM period ((%d)) -> ((%d))\n",
-+			  ccx->nhm_period, period);
-+
-+		ccx->nhm_period = period;
-+	}
-+
-+	/*Set NHM threshold*/
-+	if (phydm_nhm_th_update_chk(dm, nhm_app, &nhm_th[0], &igi,
-+				    en_1db_mode, nhm_th0_manual)) {
-+		/*Pause IGI*/
-+		if (nhm_app == NHM_BACKGROUND || nhm_app == NHM_ACS) {
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "DIG Free Run\n");
-+		} else if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE,
-+					    PHYDM_PAUSE_LEVEL_1, 1, &igi)
-+					    == PAUSE_FAIL) {
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG Fail\n");
-+			return;
-+		} else {
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG=0x%x\n", igi);
-+		}
-+		ccx->nhm_app = nhm_app;
-+		ccx->nhm_igi = (u8)igi;
-+		odm_move_memory(dm, &ccx->nhm_th[0], &nhm_th, NHM_TH_NUM);
-+
-+		/*Set NHM th*/
-+		phydm_nhm_set_th_reg(dm);
-+	}
-+}
-+
-+boolean
-+phydm_nhm_mntr_set(void *dm_void, struct nhm_para_info *nhm_para)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u16 nhm_time = 0; /*unit: 4us*/
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	if (nhm_para->mntr_time == 0)
-+		return false;
-+
-+	if (nhm_para->nhm_lv >= NHM_MAX_NUM) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Wrong LV=%d\n", nhm_para->nhm_lv);
-+		return false;
-+	}
-+
-+	if (phydm_nhm_racing_ctrl(dm, nhm_para->nhm_lv) == PHYDM_SET_FAIL)
-+		return false;
-+
-+	if (nhm_para->mntr_time >= 262)
-+		nhm_time = NHM_PERIOD_MAX;
-+	else
-+		nhm_time = nhm_para->mntr_time * MS_TO_4US_RATIO;
-+
-+	phydm_nhm_set(dm, nhm_para->incld_txon, nhm_para->incld_cca,
-+		      nhm_para->div_opt, nhm_para->nhm_app, nhm_time,
-+		      nhm_para->en_1db_mode, nhm_para->nhm_th0_manual);
-+
-+	return true;
-+}
-+
-+#ifdef NHM_DYM_PW_TH_SUPPORT
-+void
-+phydm_nhm_restore_pw_th(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+
-+	odm_set_bb_reg(dm, R_0x82c, 0x3f, ccx->pw_th_rf20_ori);
-+}
-+
-+void
-+phydm_nhm_set_pw_th(void *dm_void, u8 noise, boolean chk_succ)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	boolean not_update = false;
-+	u8 pw_th_rf20_new = 0;
-+	u8 pw_th_u_bnd = 0;
-+	s8 noise_diff = 0;
-+	u8 point_mean = 15;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	if (*dm->band_width != CHANNEL_WIDTH_20 ||
-+	    *dm->band_type == ODM_BAND_5G) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,  "bandwidth=((%d)), band=((%d))\n",
-+			  *dm->band_width, *dm->band_type);
-+		phydm_nhm_restore_pw_th(dm);
-+		return;
-+	}
-+
-+	if (chk_succ) {
-+		noise_diff = noise - (ccx->nhm_igi - 10);
-+		pw_th_u_bnd = (u8)(noise_diff + 32 + point_mean);
-+
-+		pw_th_u_bnd = MIN_2(pw_th_u_bnd, ccx->nhm_pw_th_max);
-+
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "noise_diff=((%d)), max=((%d)), pw_th_u_bnd=((%d))\n",
-+			  noise_diff, ccx->nhm_pw_th_max, pw_th_u_bnd);
-+
-+		if (pw_th_u_bnd > ccx->pw_th_rf20_cur) {
-+			pw_th_rf20_new = ccx->pw_th_rf20_cur + 1;
-+		} else if (pw_th_u_bnd < ccx->pw_th_rf20_cur) {
-+			if (ccx->pw_th_rf20_cur > ccx->pw_th_rf20_ori)
-+				pw_th_rf20_new = ccx->pw_th_rf20_cur - 1;
-+			else /*ccx->pw_th_rf20_cur == ccx->pw_th_ori*/
-+				not_update = true;
-+		} else {/*pw_th_u_bnd == ccx->pw_th_rf20_cur*/
-+			not_update = true;
-+		}
-+	} else {
-+		if (ccx->pw_th_rf20_cur > ccx->pw_th_rf20_ori)
-+			pw_th_rf20_new = ccx->pw_th_rf20_cur - 1;
-+		else /*ccx->pw_th_rf20_cur == ccx->pw_th_ori*/
-+			not_update = true;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "pw_th_cur=((%d)), pw_th_new=((%d))\n",
-+		  ccx->pw_th_rf20_cur, pw_th_rf20_new);
-+
-+	if (!not_update) {
-+		odm_set_bb_reg(dm, R_0x82c, 0x3f, pw_th_rf20_new);
-+		ccx->pw_th_rf20_cur = pw_th_rf20_new;
-+	}
-+}
-+
-+void
-+phydm_nhm_dym_pw_th(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 i = 0;
-+	u8 n_sum = 0;
-+	u8 noise = 0;
-+	boolean chk_succ = false;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	for (i = 0; i < NHM_RPT_NUM - 3; i++) {
-+		n_sum = ccx->nhm_result[i] + ccx->nhm_result[i + 1] +
-+			ccx->nhm_result[i + 2] + ccx->nhm_result[i + 3];
-+		if (n_sum >= ccx->nhm_sl_pw_th) {
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Do sl[%d:%d]\n", i, i + 3);
-+			chk_succ = true;
-+			noise = phydm_nhm_cal_wgt_avg(dm, i, i + 3, n_sum);
-+			break;
-+		}
-+	}
-+
-+	if (!chk_succ)
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "SL method failed!\n");
-+
-+	phydm_nhm_set_pw_th(dm, noise, chk_succ);
-+}
-+
-+boolean
-+phydm_nhm_dym_pw_th_en(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	struct phydm_iot_center	*iot_table = &dm->iot_table;
-+
-+	if (!(dm->support_ic_type & ODM_RTL8822C))
-+		return false;
-+
-+	if (ccx->dym_pwth_manual_ctrl)
-+		return true;
-+
-+	if (dm->iot_table.phydm_patch_id == 0x100f0401 ||
-+	    iot_table->patch_id_100f0401) {
-+		return true;
-+	} else if (ccx->nhm_dym_pw_th_en) {
-+		phydm_nhm_restore_pw_th(dm);
-+		return false;
-+	} else {
-+		return false;
-+	}
-+}
-+#endif
-+
-+/*Environment Monitor*/
-+boolean
-+phydm_nhm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	struct nhm_para_info nhm_para = {0};
-+	boolean nhm_chk_result = false;
-+	boolean nhm_polling_result = false;
-+	u32 sys_return_time = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	if (ccx->nhm_manual_ctrl) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM in manual ctrl\n");
-+		return nhm_chk_result;
-+	}
-+	sys_return_time = ccx->nhm_trigger_time + MAX_ENV_MNTR_TIME;
-+	if (ccx->nhm_app != NHM_BACKGROUND &&
-+	    (sys_return_time > dm->phydm_sys_up_time)) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "nhm_app=%d, trigger_time %d, sys_time=%d\n",
-+			  ccx->nhm_app, ccx->nhm_trigger_time,
-+			  dm->phydm_sys_up_time);
-+
-+		return nhm_chk_result;
-+	}
-+
-+	/*[NHM get result & calculate Utility----------------------------*/
-+	nhm_polling_result = phydm_nhm_get_result(dm);
-+	if (nhm_polling_result) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n");
-+		phydm_nhm_get_utility(dm);
-+	}
-+
-+	#ifdef NHM_DYM_PW_TH_SUPPORT
-+	ccx->nhm_dym_pw_th_en = phydm_nhm_dym_pw_th_en(dm);
-+	if (ccx->nhm_dym_pw_th_en) {
-+		if (nhm_polling_result)
-+			phydm_nhm_dym_pw_th(dm);
-+		else
-+			phydm_nhm_set_pw_th(dm, 0x0, false);
-+	}
-+	#endif
-+
-+	/*[NHM trigger setting]------------------------------------------*/
-+	nhm_para.incld_txon = NHM_EXCLUDE_TXON;
-+	nhm_para.incld_cca = NHM_EXCLUDE_CCA;
-+	nhm_para.div_opt = NHM_CNT_ALL;
-+	nhm_para.nhm_app = NHM_BACKGROUND;
-+	nhm_para.nhm_lv = NHM_LV_1;
-+	nhm_para.en_1db_mode = false;
-+	nhm_para.mntr_time = monitor_time;
-+
-+	#ifdef NHM_DYM_PW_TH_SUPPORT
-+	if (ccx->nhm_dym_pw_th_en) {
-+		nhm_para.div_opt = NHM_VALID;
-+		nhm_para.mntr_time = monitor_time >> ccx->nhm_period_decre;
-+	}
-+	#endif
-+
-+	nhm_chk_result = phydm_nhm_mntr_set(dm, &nhm_para);
-+
-+	return nhm_chk_result;
-+}
-+
-+void phydm_nhm_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "cur_igi=0x%x\n",
-+		  dm->dm_dig_table.cur_ig_value);
-+
-+	ccx->nhm_app = NHM_BACKGROUND;
-+	ccx->nhm_igi = 0xff;
-+
-+	/*Set NHM threshold*/
-+	ccx->nhm_ongoing = false;
-+	ccx->nhm_set_lv = NHM_RELEASE;
-+
-+	if (phydm_nhm_th_update_chk(dm, ccx->nhm_app, &ccx->nhm_th[0],
-+				    (u32 *)&ccx->nhm_igi, false, 0))
-+		phydm_nhm_set_th_reg(dm);
-+
-+	ccx->nhm_period = 0;
-+
-+	ccx->nhm_include_cca = NHM_CCA_INIT;
-+	ccx->nhm_include_txon = NHM_TXON_INIT;
-+	ccx->nhm_divider_opt = NHM_CNT_INIT;
-+
-+	ccx->nhm_manual_ctrl = 0;
-+	ccx->nhm_rpt_stamp = 0;
-+
-+	#ifdef NHM_DYM_PW_TH_SUPPORT
-+	if (dm->support_ic_type & ODM_RTL8822C) {
-+		ccx->nhm_dym_pw_th_en = false;
-+		ccx->pw_th_rf20_ori = (u8)odm_get_bb_reg(dm, R_0x82c, 0x3f);
-+		ccx->pw_th_rf20_cur = ccx->pw_th_rf20_ori;
-+		ccx->nhm_pw_th_max = 63;
-+		ccx->nhm_sl_pw_th = 100; /*39%*/
-+		ccx->nhm_period_decre = 1;
-+		ccx->dym_pwth_manual_ctrl = false;
-+	}
-+	#endif
-+}
-+
-+void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
-+		   u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	struct nhm_para_info nhm_para = {0};
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 result_tmp = 0;
-+	u8 i = 0;
-+
-+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "NHM Basic-Trigger 262ms: {1}\n");
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "NHM Adv-Trigger: {2} {Include TXON} {Include CCA}\n{0:Cnt_all, 1:Cnt valid} {App:5 for dbg} {LV:1~4} {0~262ms}, 1dB mode :{en} {t[0](RSSI)}\n");
-+		#ifdef NHM_DYM_PW_TH_SUPPORT
-+		if (dm->support_ic_type & ODM_RTL8822C) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "NHM dym_pw_th: {3} {0:off}\n");
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "NHM dym_pw_th: {3} {1:on} {max} {period_decre} {sl_th}\n");
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "NHM dym_pw_th: {3} {2:fast on}\n");
-+		}
-+		#endif
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "NHM Get Result: {100}\n");
-+	} else if (var1[0] == 100) { /*Get NHM results*/
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "IGI=0x%x, rpt_stamp=%d\n", ccx->nhm_igi,
-+			 ccx->nhm_rpt_stamp);
-+
-+		if (phydm_nhm_get_result(dm)) {
-+			for (i = 0; i < NHM_RPT_NUM; i++) {
-+				result_tmp = ccx->nhm_result[i];
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used,
-+					 "nhm_rpt[%d] = %d (%d percent)\n",
-+					 i, result_tmp,
-+					 (((result_tmp * 100) + 128) >> 8));
-+			}
-+			phydm_nhm_get_utility(dm);
-+
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "NHM_noise: valid: %d percent, noise(RSSI) = %d\n",
-+				 ccx->nhm_level_valid, ccx->nhm_level);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "NHM_pwr: nhm_pwr (RSSI) = %d\n", ccx->nhm_pwr);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "ratio: nhm_ratio=%d, nhm_env_ratio=%d\n",
-+				 ccx->nhm_ratio, ccx->nhm_env_ratio);
-+		} else {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Get NHM_rpt Fail\n");
-+		}
-+		ccx->nhm_manual_ctrl = 0;
-+	#ifdef NHM_DYM_PW_TH_SUPPORT
-+	} else if (var1[0] == 3) { /*NMH dym_pw_th*/
-+		if (dm->support_ic_type & ODM_RTL8822C) {
-+			for (i = 1; i < 7; i++) {
-+				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
-+					     &var1[i]);
-+			}
-+
-+			if (var1[1] == 1) {
-+				ccx->nhm_dym_pw_th_en = true;
-+				ccx->nhm_pw_th_max = (u8)var1[2];
-+				ccx->nhm_period_decre = (u8)var1[3];
-+				ccx->nhm_sl_pw_th = (u8)var1[4];
-+				ccx->dym_pwth_manual_ctrl = true;
-+			} else if (var1[1] == 2) {
-+				ccx->nhm_dym_pw_th_en = true;
-+				ccx->nhm_pw_th_max = 63;
-+				ccx->nhm_period_decre = 1;
-+				ccx->nhm_sl_pw_th = 100;
-+				ccx->dym_pwth_manual_ctrl = true;
-+			} else {
-+				ccx->nhm_dym_pw_th_en = false;
-+				phydm_nhm_restore_pw_th(dm);
-+				ccx->dym_pwth_manual_ctrl = false;
-+			}
-+		}
-+	#endif
-+	} else { /*NMH trigger*/
-+		ccx->nhm_manual_ctrl = 1;
-+
-+		for (i = 1; i < 9; i++) {
-+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
-+				     &var1[i]);
-+		}
-+
-+		if (var1[0] == 1) {
-+			nhm_para.incld_txon = NHM_EXCLUDE_TXON;
-+			nhm_para.incld_cca = NHM_EXCLUDE_CCA;
-+			nhm_para.div_opt = NHM_CNT_ALL;
-+			nhm_para.nhm_app = NHM_DBG;
-+			nhm_para.nhm_lv = NHM_LV_4;
-+			nhm_para.mntr_time = 262;
-+			nhm_para.en_1db_mode = false;
-+			nhm_para.nhm_th0_manual = 0;
-+		} else {
-+			nhm_para.incld_txon = (enum nhm_option_txon_all)var1[1];
-+			nhm_para.incld_cca = (enum nhm_option_cca_all)var1[2];
-+			nhm_para.div_opt = (enum nhm_divider_opt_all)var1[3];
-+			nhm_para.nhm_app = (enum nhm_application)var1[4];
-+			nhm_para.nhm_lv = (enum phydm_nhm_level)var1[5];
-+			nhm_para.mntr_time = (u16)var1[6];
-+			nhm_para.en_1db_mode = (boolean)var1[7];
-+			nhm_para.nhm_th0_manual = (u8)var1[8];
-+
-+			/*some old ic is not supported on NHM divider option */
-+			if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B |
-+			    ODM_RTL8195A | ODM_RTL8192E)) {
-+				nhm_para.div_opt = NHM_CNT_ALL;
-+			}
-+		}
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "txon=%d, cca=%d, dev=%d, app=%d, lv=%d, time=%d ms\n",
-+			 nhm_para.incld_txon, nhm_para.incld_cca,
-+			 nhm_para.div_opt, nhm_para.nhm_app,
-+			 nhm_para.nhm_lv, nhm_para.mntr_time);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "en_1db_mode=%d, th0(for 1db mode)=%d\n",
-+			 nhm_para.en_1db_mode, nhm_para.nhm_th0_manual);
-+
-+		if (phydm_nhm_mntr_set(dm, &nhm_para))
-+			phydm_nhm_trigger(dm);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "IGI=0x%x, rpt_stamp=%d\n", ccx->nhm_igi,
-+			 ccx->nhm_rpt_stamp);
-+
-+		for (i = 0; i < NHM_TH_NUM; i++) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "NHM_th[%d] RSSI = %d\n", i,
-+				 NTH_TH_2_RSSI(ccx->nhm_th[i]));
-+		}
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#endif /*@#ifdef NHM_SUPPORT*/
-+
-+#ifdef CLM_SUPPORT
-+
-+void phydm_clm_racing_release(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "lv:(%d)->(0)\n", ccx->clm_set_lv);
-+
-+	ccx->clm_ongoing = false;
-+	ccx->clm_set_lv = CLM_RELEASE;
-+	ccx->clm_app = CLM_BACKGROUND;
-+}
-+
-+u8 phydm_clm_racing_ctrl(void *dm_void, enum phydm_clm_level clm_lv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 set_result = PHYDM_SET_SUCCESS;
-+	/*@acquire to control CLM API*/
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_ongoing=%d, lv:(%d)->(%d)\n",
-+		  ccx->clm_ongoing, ccx->clm_set_lv, clm_lv);
-+	if (ccx->clm_ongoing) {
-+		if (clm_lv <= ccx->clm_set_lv) {
-+			set_result = PHYDM_SET_FAIL;
-+		} else {
-+			phydm_ccx_hw_restart(dm);
-+			ccx->clm_ongoing = false;
-+		}
-+	}
-+
-+	if (set_result)
-+		ccx->clm_set_lv = clm_lv;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "clm racing success=%d\n", set_result);
-+	return set_result;
-+}
-+
-+void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx_info = &dm->dm_ccx_info;
-+	u8 clm_report = cmd_buf[0];
-+	/*@u8 clm_report_idx = cmd_buf[1];*/
-+
-+	if (cmd_len >= 12)
-+		return;
-+
-+	ccx_info->clm_fw_result_acc += clm_report;
-+	ccx_info->clm_fw_result_cnt++;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%d] clm_report= %d\n",
-+		  ccx_info->clm_fw_result_cnt, clm_report);
-+}
-+
-+void phydm_clm_h2c(void *dm_void, u16 obs_time, u8 fw_clm_en)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 h2c_val[H2C_MAX_LENGTH] = {0};
-+	u8 i = 0;
-+	u8 obs_time_idx = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "obs_time_index=%d *4 us\n", obs_time);
-+
-+	for (i = 1; i <= 16; i++) {
-+		if (obs_time & BIT(16 - i)) {
-+			obs_time_idx = 16 - i;
-+			break;
-+		}
-+	}
-+#if 0
-+	obs_time = (2 ^ 16 - 1)~(2 ^ 15)  => obs_time_idx = 15  (65535 ~32768)
-+	obs_time = (2 ^ 15 - 1)~(2 ^ 14)  => obs_time_idx = 14
-+	...
-+	...
-+	...
-+	obs_time = (2 ^ 1 - 1)~(2 ^ 0)  => obs_time_idx = 0
-+
-+#endif
-+
-+	h2c_val[0] = obs_time_idx | (((fw_clm_en) ? 1 : 0) << 7);
-+	h2c_val[1] = CLM_MAX_REPORT_TIME;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "PHYDM h2c[0x4d]=0x%x %x %x %x %x %x %x\n",
-+		  h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2],
-+		  h2c_val[1], h2c_val[0]);
-+
-+	odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_CLM_MNTR, H2C_MAX_LENGTH, h2c_val);
-+}
-+
-+void phydm_clm_setting(void *dm_void, u16 clm_period /*@4us sample 1 time*/)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+
-+	if (ccx->clm_period != clm_period) {
-+		if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-+			odm_set_bb_reg(dm, R_0x990, MASKLWORD, clm_period);
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+			odm_set_bb_reg(dm, R_0x1e40, MASKLWORD, clm_period);
-+		#endif
-+		else if (dm->support_ic_type & ODM_IC_11N_SERIES)
-+			odm_set_bb_reg(dm, R_0x894, MASKLWORD, clm_period);
-+
-+		ccx->clm_period = clm_period;
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "Update CLM period ((%d)) -> ((%d))\n",
-+			  ccx->clm_period, clm_period);
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "Set CLM period=%d * 4us\n",
-+		  ccx->clm_period);
-+}
-+
-+void phydm_clm_trigger(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u32 reg1 = 0;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-+		reg1 = R_0x994;
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		reg1 = R_0x1e60;
-+	#endif
-+	else
-+		reg1 = R_0x890;
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	odm_set_bb_reg(dm, reg1, BIT(0), 0x0);
-+	odm_set_bb_reg(dm, reg1, BIT(0), 0x1);
-+
-+	ccx->clm_trigger_time = dm->phydm_sys_up_time;
-+	ccx->clm_rpt_stamp++;
-+	ccx->clm_ongoing = true;
-+}
-+
-+boolean
-+phydm_clm_check_rdy(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean is_ready = false;
-+	u32 reg1 = 0, reg1_bit = 0;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		reg1 = R_0xfa4;
-+		reg1_bit = 16;
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		reg1 = R_0x2d88;
-+		reg1_bit = 16;
-+	#endif
-+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		if (dm->support_ic_type & (ODM_RTL8710B | ODM_RTL8721D |
-+					ODM_RTL8710C)) {
-+			reg1 = R_0x8b4;
-+			reg1_bit = 24;
-+		} else {
-+			reg1 = R_0x8b4;
-+			reg1_bit = 16;
-+		}
-+	}
-+	if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit)))
-+		is_ready = true;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM rdy=%d\n", is_ready);
-+
-+	return is_ready;
-+}
-+
-+void phydm_clm_get_utility(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u32 clm_result_tmp;
-+
-+	if (ccx->clm_period == 0) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "[warning] clm_period = 0\n");
-+		ccx->clm_ratio = 0;
-+	} else if (ccx->clm_period >= 65530) {
-+		clm_result_tmp = (u32)(ccx->clm_result * 100);
-+		ccx->clm_ratio = (u8)((clm_result_tmp + (1 << 15)) >> 16);
-+	} else {
-+		clm_result_tmp = (u32)(ccx->clm_result * 100);
-+		ccx->clm_ratio = (u8)(clm_result_tmp / (u32)ccx->clm_period);
-+	}
-+}
-+
-+boolean
-+phydm_clm_get_result(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx_info = &dm->dm_ccx_info;
-+	u32 reg1 = 0;
-+	u32 val = 0;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-+		reg1 = R_0x994;
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		reg1 = R_0x1e60;
-+	#endif
-+	else
-+		reg1 = R_0x890;
-+	if (!(dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
-+				     ODM_RTL8197G | ODM_RTL8723F)))
-+		odm_set_bb_reg(dm, reg1, BIT(0), 0x0);
-+	if (!(phydm_clm_check_rdy(dm))) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM report Fail\n");
-+		phydm_clm_racing_release(dm);
-+		return false;
-+	}
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		val = odm_get_bb_reg(dm, R_0xfa4, MASKLWORD);
-+		ccx_info->clm_result = (u16)val;
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		val = odm_get_bb_reg(dm, R_0x2d88, MASKLWORD);
-+		ccx_info->clm_result = (u16)val;
-+	#endif
-+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		val = odm_get_bb_reg(dm, R_0x8d0, MASKLWORD);
-+		ccx_info->clm_result = (u16)val;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM result = %d *4 us\n",
-+		  ccx_info->clm_result);
-+	phydm_clm_racing_release(dm);
-+	return true;
-+}
-+
-+void phydm_clm_mntr_fw(void *dm_void, u16 monitor_time /*unit ms*/)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u32 val = 0;
-+
-+	/*@[Get CLM report]*/
-+	if (ccx->clm_fw_result_cnt != 0) {
-+		val = ccx->clm_fw_result_acc / ccx->clm_fw_result_cnt;
-+		ccx->clm_ratio = (u8)val;
-+	} else {
-+		ccx->clm_ratio = 0;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n",
-+		  ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt);
-+
-+	ccx->clm_fw_result_acc = 0;
-+	ccx->clm_fw_result_cnt = 0;
-+
-+	/*@[CLM trigger]*/
-+	if (monitor_time >= 262)
-+		ccx->clm_period = 65535;
-+	else
-+		ccx->clm_period = monitor_time * MS_TO_4US_RATIO;
-+
-+	phydm_clm_h2c(dm, ccx->clm_period, true);
-+}
-+
-+boolean
-+phydm_clm_mntr_set(void *dm_void, struct clm_para_info *clm_para)
-+{
-+	/*@Driver Monitor CLM*/
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u16 clm_period = 0;
-+
-+	if (clm_para->mntr_time == 0)
-+		return false;
-+
-+	if (clm_para->clm_lv >= CLM_MAX_NUM) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "[WARNING] Wrong LV=%d\n",
-+			  clm_para->clm_lv);
-+		return false;
-+	}
-+
-+	if (phydm_clm_racing_ctrl(dm, clm_para->clm_lv) == PHYDM_SET_FAIL)
-+		return false;
-+
-+	if (clm_para->mntr_time >= 262)
-+		clm_period = CLM_PERIOD_MAX;
-+	else
-+		clm_period = clm_para->mntr_time * MS_TO_4US_RATIO;
-+
-+	ccx->clm_app = clm_para->clm_app;
-+	phydm_clm_setting(dm, clm_period);
-+
-+	return true;
-+}
-+
-+boolean
-+phydm_clm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	struct clm_para_info clm_para = {0};
-+	boolean clm_chk_result = false;
-+	u32 sys_return_time = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
-+	if (ccx->clm_manual_ctrl) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM in manual ctrl\n");
-+		return clm_chk_result;
-+	}
-+
-+	sys_return_time = ccx->clm_trigger_time + MAX_ENV_MNTR_TIME;
-+
-+	if (ccx->clm_app != CLM_BACKGROUND &&
-+	    sys_return_time > dm->phydm_sys_up_time) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "trigger_time %d, sys_time=%d\n",
-+			  ccx->clm_trigger_time, dm->phydm_sys_up_time);
-+
-+		return clm_chk_result;
-+	}
-+
-+	clm_para.clm_app = CLM_BACKGROUND;
-+	clm_para.clm_lv = CLM_LV_1;
-+	clm_para.mntr_time = monitor_time;
-+	if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) {
-+		/*@[Get CLM report]*/
-+		if (phydm_clm_get_result(dm)) {
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM_rpt success\n");
-+			phydm_clm_get_utility(dm);
-+		}
-+
-+		/*@[CLM trigger]----------------------------------------------*/
-+		if (phydm_clm_mntr_set(dm, &clm_para))
-+			clm_chk_result = true;
-+	} else {
-+		phydm_clm_mntr_fw(dm, monitor_time);
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_ratio=%d\n", ccx->clm_ratio);
-+
-+	/*@PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_chk_result=%d\n",clm_chk_result);*/
-+
-+	return clm_chk_result;
-+}
-+
-+void phydm_set_clm_mntr_mode(void *dm_void, enum clm_monitor_mode mode)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx_info = &dm->dm_ccx_info;
-+
-+	if (ccx_info->clm_mntr_mode != mode) {
-+		ccx_info->clm_mntr_mode = mode;
-+		phydm_ccx_hw_restart(dm);
-+
-+		if (mode == CLM_DRIVER_MNTR)
-+			phydm_clm_h2c(dm, CLM_PERIOD_MAX, 0);
-+	}
-+}
-+
-+void phydm_clm_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+	ccx->clm_ongoing = false;
-+	ccx->clm_manual_ctrl = 0;
-+	ccx->clm_mntr_mode = CLM_DRIVER_MNTR;
-+	ccx->clm_period = 0;
-+	ccx->clm_rpt_stamp = 0;
-+	phydm_clm_setting(dm, 65535);
-+}
-+
-+void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
-+		   u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	struct clm_para_info clm_para = {0};
-+	u32 i;
-+
-+	for (i = 0; i < 4; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
-+	}
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "CLM Driver Basic-Trigger 262ms: {1}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "CLM Driver Adv-Trigger: {2} {app} {LV} {0~262ms}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "CLM FW Trigger: {3} {1:drv, 2:fw}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "CLM Get Result: {100}\n");
-+	} else if (var1[0] == 100) { /* @Get CLM results */
-+
-+		if (phydm_clm_get_result(dm))
-+			phydm_clm_get_utility(dm);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "clm_rpt_stamp=%d\n", ccx->clm_rpt_stamp);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "clm_ratio:((%d percent)) = (%d us/ %d us)\n",
-+			 ccx->clm_ratio, ccx->clm_result << 2,
-+			 ccx->clm_period << 2);
-+
-+		ccx->clm_manual_ctrl = 0;
-+	} else if (var1[0] == 3) {
-+		phydm_set_clm_mntr_mode(dm, (enum clm_monitor_mode)var1[1]);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "CLM mode: %s mode\n",
-+			 ((ccx->clm_mntr_mode == CLM_FW_MNTR) ? "FW" : "Drv"));
-+	} else { /* Set & trigger CLM */
-+		ccx->clm_manual_ctrl = 1;
-+
-+		if (var1[0] == 1) {
-+			clm_para.clm_app = CLM_BACKGROUND;
-+			clm_para.clm_lv = CLM_LV_4;
-+			clm_para.mntr_time = 262;
-+			ccx->clm_mntr_mode = CLM_DRIVER_MNTR;
-+		} else if (var1[0] == 2) {
-+			clm_para.clm_app = (enum clm_application)var1[1];
-+			clm_para.clm_lv = (enum phydm_clm_level)var1[2];
-+			ccx->clm_mntr_mode = CLM_DRIVER_MNTR;
-+			clm_para.mntr_time = (u16)var1[3];
-+		}
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "app=%d, lv=%d, mode=%s, time=%d ms\n",
-+			 clm_para.clm_app, clm_para.clm_lv,
-+			 ((ccx->clm_mntr_mode == CLM_FW_MNTR) ? "FW" :
-+			 "driver"), clm_para.mntr_time);
-+
-+		if (phydm_clm_mntr_set(dm, &clm_para))
-+			phydm_clm_trigger(dm);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "clm_rpt_stamp=%d\n", ccx->clm_rpt_stamp);
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#endif /*@#ifdef CLM_SUPPORT*/
-+
-+u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para,
-+			  struct clm_para_info *clm_para,
-+			  struct env_trig_rpt *trig_rpt)
-+{
-+	u8 trigger_result = 0;
-+#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	boolean nhm_set_ok = false;
-+	boolean clm_set_ok = false;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
-+
-+	/*@[NHM]*/
-+	nhm_set_ok = phydm_nhm_mntr_set(dm, nhm_para);
-+
-+	/*@[CLM]*/
-+	if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) {
-+		clm_set_ok = phydm_clm_mntr_set(dm, clm_para);
-+	} else if (ccx->clm_mntr_mode == CLM_FW_MNTR) {
-+		phydm_clm_h2c(dm, CLM_PERIOD_MAX, true);
-+		trigger_result |= CLM_SUCCESS;
-+	}
-+
-+	if (nhm_set_ok) {
-+		phydm_nhm_trigger(dm);
-+		trigger_result |= NHM_SUCCESS;
-+	}
-+
-+	if (clm_set_ok) {
-+		phydm_clm_trigger(dm);
-+		trigger_result |= CLM_SUCCESS;
-+	}
-+
-+	/*@monitor for the test duration*/
-+	ccx->start_time = odm_get_current_time(dm);
-+
-+	trig_rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp;
-+	trig_rpt->clm_rpt_stamp = ccx->clm_rpt_stamp;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_rpt_stamp=%d, clm_rpt_stamp=%d,\n\n",
-+		  trig_rpt->nhm_rpt_stamp, trig_rpt->clm_rpt_stamp);
-+#endif
-+	return trigger_result;
-+}
-+
-+u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt)
-+{
-+	u8 env_mntr_rpt = 0;
-+#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u64 progressing_time = 0;
-+	u32 val_tmp = 0;
-+
-+	/*@monitor for the test duration*/
-+	progressing_time = odm_get_progressing_time(dm, ccx->start_time);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "env_time=%lld\n", progressing_time);
-+
-+	/*@Get NHM result*/
-+	if (phydm_nhm_get_result(dm)) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n");
-+		phydm_nhm_get_utility(dm);
-+		rpt->nhm_ratio = ccx->nhm_ratio;
-+		rpt->nhm_env_ratio = ccx->nhm_env_ratio;
-+		rpt->nhm_noise_pwr = ccx->nhm_level;
-+		rpt->nhm_pwr = ccx->nhm_pwr;
-+		env_mntr_rpt |= NHM_SUCCESS;
-+
-+		odm_move_memory(dm, &rpt->nhm_result[0],
-+				&ccx->nhm_result[0], NHM_RPT_NUM);
-+	} else {
-+		rpt->nhm_ratio = ENV_MNTR_FAIL;
-+		rpt->nhm_env_ratio = ENV_MNTR_FAIL;
-+	}
-+
-+	/*@Get CLM result*/
-+	if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) {
-+		if (phydm_clm_get_result(dm)) {
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM_rpt success\n");
-+			phydm_clm_get_utility(dm);
-+			env_mntr_rpt |= CLM_SUCCESS;
-+			rpt->clm_ratio = ccx->clm_ratio;
-+		} else {
-+			rpt->clm_ratio = ENV_MNTR_FAIL;
-+		}
-+
-+	} else {
-+		if (ccx->clm_fw_result_cnt != 0) {
-+			val_tmp = ccx->clm_fw_result_acc
-+			/ ccx->clm_fw_result_cnt;
-+			ccx->clm_ratio = (u8)val_tmp;
-+		} else {
-+			ccx->clm_ratio = 0;
-+		}
-+
-+		rpt->clm_ratio = ccx->clm_ratio;
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n",
-+			  ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt);
-+
-+		ccx->clm_fw_result_acc = 0;
-+		ccx->clm_fw_result_cnt = 0;
-+		env_mntr_rpt |= CLM_SUCCESS;
-+	}
-+
-+	rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp;
-+	rpt->clm_rpt_stamp = ccx->clm_rpt_stamp;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "IGI=0x%x, nhm_ratio=%d, nhm_env_ratio=%d, clm_ratio=%d, nhm_rpt_stamp=%d, clm_rpt_stamp=%d\n\n",
-+		  ccx->nhm_igi, rpt->nhm_ratio, rpt->nhm_env_ratio,
-+		  rpt->clm_ratio, rpt->nhm_rpt_stamp, rpt->clm_rpt_stamp);
-+#endif
-+	return env_mntr_rpt;
-+}
-+
-+/*@Environment Monitor*/
-+void phydm_env_mntr_watchdog(void *dm_void)
-+{
-+#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	boolean nhm_chk_ok = false;
-+	boolean clm_chk_ok = false;
-+
-+	if (!(dm->support_ability & ODM_BB_ENV_MONITOR))
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+	nhm_chk_ok = phydm_nhm_mntr_chk(dm, 262); /*@monitor 262ms*/
-+	clm_chk_ok = phydm_clm_mntr_chk(dm, 262); /*@monitor 262ms*/
-+
-+	/*@PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_chk_ok %d\n\n",nhm_chk_ok);*/
-+	/*@PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_chk_ok %d\n\n",clm_chk_ok);*/
-+
-+	if (nhm_chk_ok)
-+		phydm_nhm_trigger(dm);
-+
-+	if (clm_chk_ok)
-+		phydm_clm_trigger(dm);
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "Summary: nhm_ratio=((%d)) clm_ratio=((%d))\n\n",
-+		  ccx->nhm_ratio, ccx->clm_ratio);
-+
-+	#ifdef FAHM_SUPPORT
-+	phydm_fahm_watchdog(dm);
-+	#endif
-+#endif
-+}
-+
-+void phydm_env_monitor_init(void *dm_void)
-+{
-+#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT))
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	phydm_ccx_hw_restart(dm);
-+	phydm_nhm_init(dm);
-+	phydm_clm_init(dm);
-+	#ifdef FAHM_SUPPORT
-+	phydm_fahm_init(dm);
-+	#endif
-+#endif
-+}
-+
-+void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
-+			char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	struct clm_para_info clm_para = {0};
-+	struct nhm_para_info nhm_para = {0};
-+	struct env_mntr_rpt rpt = {0};
-+	struct env_trig_rpt trig_rpt = {0};
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 set_result = 0;
-+	u8 i = 0;
-+
-+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Basic-Trigger 262ms: {1}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Get Result: {100}\n");
-+	} else if (var1[0] == 100) { /* Get results */
-+		set_result = phydm_env_mntr_result(dm, &rpt);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Set Result=%d\n nhm_ratio=%d nhm_env_ratio=%d clm_ratio=%d\n nhm_rpt_stamp=%d, clm_rpt_stamp=%d,\n",
-+			 set_result, rpt.nhm_ratio, rpt.nhm_env_ratio,
-+			 rpt.clm_ratio, rpt.nhm_rpt_stamp, rpt.clm_rpt_stamp);
-+
-+		for (i = 0; i <= 11; i++) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "nhm_rpt[%d] = %d (%d percent)\n", i,
-+				 rpt.nhm_result[i],
-+				 (((rpt.nhm_result[i] * 100) + 128) >> 8));
-+		}
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[NHM] valid: %d percent, noise(RSSI) = %d\n",
-+			 ccx->nhm_level_valid, ccx->nhm_level);
-+	} else { /* Set & trigger*/
-+		/*nhm para*/
-+		nhm_para.incld_txon = NHM_EXCLUDE_TXON;
-+		nhm_para.incld_cca = NHM_EXCLUDE_CCA;
-+		nhm_para.div_opt = NHM_CNT_ALL;
-+		nhm_para.nhm_app = NHM_ACS;
-+		nhm_para.nhm_lv = NHM_LV_2;
-+		nhm_para.mntr_time = 262;
-+		nhm_para.en_1db_mode = false;
-+
-+		/*clm para*/
-+		clm_para.clm_app = CLM_ACS;
-+		clm_para.clm_lv = CLM_LV_2;
-+		clm_para.mntr_time = 262;
-+
-+		set_result = phydm_env_mntr_trigger(dm, &nhm_para,
-+						    &clm_para, &trig_rpt);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Set Result=%d, nhm_rpt_stamp=%d, clm_rpt_stamp=%d\n",
-+			 set_result, trig_rpt.nhm_rpt_stamp,
-+			 trig_rpt.clm_rpt_stamp);
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#ifdef IFS_CLM_SUPPORT
-+void phydm_ifs_clm_restart(void *dm_void)
-+			  /*Will Restart IFS CLM simultaneously*/
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 reg1 = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	/*restart IFS_CLM*/
-+	odm_set_bb_reg(dm, R_0x1ee4, BIT(29), 0x0);
-+	odm_set_bb_reg(dm, R_0x1ee4, BIT(29), 0x1);
-+}
-+
-+void phydm_ifs_clm_racing_release(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "ifs clm lv:(%d)->(0)\n",
-+		  ccx->ifs_clm_set_lv);
-+
-+	ccx->ifs_clm_ongoing = false;
-+	ccx->ifs_clm_set_lv = IFS_CLM_RELEASE;
-+	ccx->ifs_clm_app = IFS_CLM_BACKGROUND;
-+}
-+
-+u8 phydm_ifs_clm_racing_ctrl(void *dm_void, enum phydm_ifs_clm_level ifs_clm_lv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 set_result = PHYDM_SET_SUCCESS;
-+	/*acquire to control IFS CLM API*/
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "ifs clm_ongoing=%d, lv:(%d)->(%d)\n",
-+		  ccx->ifs_clm_ongoing, ccx->ifs_clm_set_lv, ifs_clm_lv);
-+	if (ccx->ifs_clm_ongoing) {
-+		if (ifs_clm_lv <= ccx->ifs_clm_set_lv) {
-+			set_result = PHYDM_SET_FAIL;
-+		} else {
-+			phydm_ifs_clm_restart(dm);
-+			ccx->ifs_clm_ongoing = false;
-+		}
-+	}
-+
-+	if (set_result)
-+		ccx->ifs_clm_set_lv = ifs_clm_lv;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "ifs clm racing success=%d\n", set_result);
-+	return set_result;
-+}
-+
-+void phydm_ifs_clm_trigger(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	/*Trigger IFS_CLM*/
-+	pdm_set_reg(dm, R_0x1ee4, BIT(29), 0);
-+	pdm_set_reg(dm, R_0x1ee4, BIT(29), 1);
-+	ccx->ifs_clm_trigger_time = dm->phydm_sys_up_time;
-+	ccx->ifs_clm_rpt_stamp++;
-+	ccx->ifs_clm_ongoing = true;
-+}
-+
-+void phydm_ifs_clm_get_utility(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u32 numerator = 0;
-+	u16 denominator = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	denominator = ccx->ifs_clm_period;
-+	numerator = ccx->ifs_clm_tx * 100;
-+	ccx->ifs_clm_tx_ratio = (u8)PHYDM_DIV(numerator, denominator);
-+	numerator = ccx->ifs_clm_edcca_excl_cca * 100;
-+	ccx->ifs_clm_edcca_excl_cca_ratio = (u8)PHYDM_DIV(numerator,
-+							  denominator);
-+	numerator = (ccx->ifs_clm_cckfa + ccx->ifs_clm_ofdmfa) * 100;
-+	ccx->ifs_clm_fa_ratio = (u8)PHYDM_DIV(numerator, denominator);
-+	numerator = (ccx->ifs_clm_cckcca_excl_fa +
-+		     ccx->ifs_clm_ofdmcca_excl_fa) * 100;
-+	ccx->ifs_clm_cca_excl_fa_ratio = (u8)PHYDM_DIV(numerator, denominator);
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "Tx_ratio = %d, EDCCA_exclude_CCA_ratio = %d \n",
-+		  ccx->ifs_clm_tx_ratio, ccx->ifs_clm_edcca_excl_cca_ratio);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "FA_ratio = %d, CCA_exclude_FA_ratio = %d \n",
-+		  ccx->ifs_clm_fa_ratio, ccx->ifs_clm_cca_excl_fa_ratio);
-+}
-+
-+void phydm_ifs_clm_get_result(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u32 value32 = 0;
-+	u8 i = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	/*Enhance CLM result*/
-+	value32 = odm_get_bb_reg(dm, R_0x2e60, MASKDWORD);
-+	ccx->ifs_clm_tx = (u16)(value32 & MASKLWORD);
-+	ccx->ifs_clm_edcca_excl_cca = (u16)((value32 & MASKHWORD) >> 16);
-+	value32 = odm_get_bb_reg(dm, R_0x2e64, MASKDWORD);
-+	ccx->ifs_clm_ofdmfa = (u16)(value32 & MASKLWORD);
-+	ccx->ifs_clm_ofdmcca_excl_fa = (u16)((value32 & MASKHWORD) >> 16);
-+	value32 = odm_get_bb_reg(dm, R_0x2e68, MASKDWORD);
-+	ccx->ifs_clm_cckfa = (u16)(value32 & MASKLWORD);
-+	ccx->ifs_clm_cckcca_excl_fa = (u16)((value32 & MASKHWORD) >> 16);
-+	value32 = odm_get_bb_reg(dm, R_0x2e6c, MASKDWORD);
-+	ccx->ifs_clm_total_cca = (u16)(value32 & MASKLWORD);
-+
-+	/* IFS result */
-+	value32 = odm_get_bb_reg(dm, R_0x2e70, MASKDWORD);
-+	odm_move_memory(dm, &ccx->ifs_clm_his[0], &value32, 4);
-+	value32 = odm_get_bb_reg(dm, R_0x2e74, MASKDWORD);
-+	ccx->ifs_clm_avg[0] = (u16)(value32 & MASKLWORD);
-+	ccx->ifs_clm_avg[1] = (u16)((value32 & MASKHWORD) >> 16);
-+	value32 = odm_get_bb_reg(dm, R_0x2e78, MASKDWORD);
-+	ccx->ifs_clm_avg[2] = (u16)(value32 & MASKLWORD);
-+	ccx->ifs_clm_avg[3] = (u16)((value32 & MASKHWORD) >> 16);
-+	value32 = odm_get_bb_reg(dm, R_0x2e7c, MASKDWORD);
-+	ccx->ifs_clm_avg_cca[0] = (u16)(value32 & MASKLWORD);
-+	ccx->ifs_clm_avg_cca[1] = (u16)((value32 & MASKHWORD) >> 16);
-+	value32 = odm_get_bb_reg(dm, R_0x2e80, MASKDWORD);
-+	ccx->ifs_clm_avg_cca[2] = (u16)(value32 & MASKLWORD);
-+	ccx->ifs_clm_avg_cca[3] = (u16)((value32 & MASKHWORD) >> 16);
-+
-+	/* Print Result */
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "ECLM_Rpt[%d]: \nTx = %d, EDCCA_exclude_CCA = %d \n",
-+		  ccx->ifs_clm_rpt_stamp, ccx->ifs_clm_tx,
-+		  ccx->ifs_clm_edcca_excl_cca);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "[FA_cnt] {CCK, OFDM} = {%d, %d}\n",
-+		  ccx->ifs_clm_cckfa, ccx->ifs_clm_ofdmfa);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "[CCA_exclude_FA_cnt] {CCK, OFDM} = {%d, %d}\n",
-+		  ccx->ifs_clm_cckcca_excl_fa, ccx->ifs_clm_ofdmcca_excl_fa);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "CCATotal = %d\n", ccx->ifs_clm_total_cca);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "Time:[his, avg, avg_cca]\n");
-+	for (i = 0; i < IFS_CLM_NUM; i++)
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "T%d:[%d, %d, %d]\n", i + 1,
-+			  ccx->ifs_clm_his[i], ccx->ifs_clm_avg[i],
-+			  ccx->ifs_clm_avg_cca[i]);
-+
-+	phydm_ifs_clm_racing_release(dm);
-+
-+	return;
-+}
-+
-+void phydm_ifs_clm_set_th_reg(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 i = 0;
-+	
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	/*Set IFS period TH*/
-+	odm_set_bb_reg(dm, R_0x1ed4, BIT(31), ccx->ifs_clm_th_en[0]);
-+	odm_set_bb_reg(dm, R_0x1ed8, BIT(31), ccx->ifs_clm_th_en[1]);
-+	odm_set_bb_reg(dm, R_0x1edc, BIT(31), ccx->ifs_clm_th_en[2]);
-+	odm_set_bb_reg(dm, R_0x1ee0, BIT(31), ccx->ifs_clm_th_en[3]);
-+	odm_set_bb_reg(dm, R_0x1ed4, 0x7fff0000, ccx->ifs_clm_th_low[0]);
-+	odm_set_bb_reg(dm, R_0x1ed8, 0x7fff0000, ccx->ifs_clm_th_low[1]);
-+	odm_set_bb_reg(dm, R_0x1edc, 0x7fff0000, ccx->ifs_clm_th_low[2]);
-+	odm_set_bb_reg(dm, R_0x1ee0, 0x7fff0000, ccx->ifs_clm_th_low[3]);
-+	odm_set_bb_reg(dm, R_0x1ed4, MASKLWORD, ccx->ifs_clm_th_high[0]);
-+	odm_set_bb_reg(dm, R_0x1ed8, MASKLWORD, ccx->ifs_clm_th_high[1]);
-+	odm_set_bb_reg(dm, R_0x1edc, MASKLWORD, ccx->ifs_clm_th_high[2]);
-+	odm_set_bb_reg(dm, R_0x1ee0, MASKLWORD, ccx->ifs_clm_th_high[3]);
-+
-+	for (i = 0; i < IFS_CLM_NUM; i++)
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "Update IFS_CLM_th%d[High Low] : [%d %d]\n", i + 1,
-+		  	  ccx->ifs_clm_th_high[i], ccx->ifs_clm_th_low[i]);
-+}
-+
-+boolean phydm_ifs_clm_th_update_chk(void *dm_void,
-+				    enum ifs_clm_application ifs_clm_app,
-+				    boolean *ifs_clm_th_en, u16 *ifs_clm_th_low,
-+				    u16 *ifs_clm_th_high, s16 th_shift)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	boolean is_update = false;
-+	u16 ifs_clm_th_low_bg[IFS_CLM_NUM] = {12, 5, 2, 0};
-+	u16 ifs_clm_th_high_bg[IFS_CLM_NUM] = {64, 12, 5, 2};
-+	u8 i = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "App=%d, th_shift=%d\n", ifs_clm_app,
-+		  th_shift);
-+
-+	switch (ifs_clm_app) {
-+	case IFS_CLM_BACKGROUND:
-+	case IFS_CLM_ACS:
-+	case IFS_CLM_HP_TAS:
-+		if (ccx->ifs_clm_app != ifs_clm_app || th_shift != 0) {
-+			is_update = true;
-+
-+			for (i = 0; i < IFS_CLM_NUM; i++) {
-+				ifs_clm_th_en[i] = true;
-+				ifs_clm_th_low[i] = ifs_clm_th_low_bg[i];
-+				ifs_clm_th_high[i] = ifs_clm_th_high_bg[i];
-+			}
-+		}
-+		break;
-+	case IFS_CLM_DBG:
-+		if (ccx->ifs_clm_app != ifs_clm_app || th_shift != 0) {
-+			is_update = true;
-+
-+			for (i = 0; i < IFS_CLM_NUM; i++) {
-+				ifs_clm_th_en[i] = true;
-+				ifs_clm_th_low[i] = MAX_2(ccx->ifs_clm_th_low[i] +
-+						    th_shift, 0);
-+				ifs_clm_th_high[i] = MAX_2(ccx->ifs_clm_th_high[i] +
-+						     th_shift, 0);
-+			}
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (is_update)
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "[Update IFS_TH]\n");
-+	else
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "No need to update IFS_TH\n");
-+
-+	return is_update;
-+}
-+
-+void phydm_ifs_clm_set(void *dm_void, enum ifs_clm_application ifs_clm_app,
-+		       u16 period, u8 ctrl_unit, s16 th_shift)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	boolean ifs_clm_th_en[IFS_CLM_NUM] =  {0};
-+	u16 ifs_clm_th_low[IFS_CLM_NUM] =  {0};
-+	u16 ifs_clm_th_high[IFS_CLM_NUM] =  {0};
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "period=%d, ctrl_unit=%d\n", period,
-+		  ctrl_unit);
-+
-+	/*Set Unit*/
-+	if (ctrl_unit != ccx->ifs_clm_ctrl_unit) {	
-+		odm_set_bb_reg(dm, R_0x1ee4, 0xc0000000, ctrl_unit);
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "Update IFS_CLM unit ((%d)) -> ((%d))\n",
-+			  ccx->ifs_clm_ctrl_unit, ctrl_unit);
-+		ccx->ifs_clm_ctrl_unit = ctrl_unit;
-+	}
-+
-+	/*Set Duration*/
-+	if (period != ccx->ifs_clm_period) {
-+		odm_set_bb_reg(dm, R_0x1eec, 0xc0000000, (period & 0x3));
-+		odm_set_bb_reg(dm, R_0x1ef0, 0xfe000000, ((period >> 2) &
-+			       0x7f));
-+		odm_set_bb_reg(dm, R_0x1ef4, 0xc0000000, ((period >> 9) &
-+			       0x3));
-+		odm_set_bb_reg(dm, R_0x1ef8, 0x3e000000, ((period >> 11) &
-+			       0x1f));
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "Update IFS_CLM period ((%d)) -> ((%d))\n",
-+			  ccx->ifs_clm_period, period);
-+		ccx->ifs_clm_period = period;
-+	}
-+
-+	/*Set IFS CLM threshold*/
-+	if (phydm_ifs_clm_th_update_chk(dm, ifs_clm_app, &ifs_clm_th_en[0],
-+					&ifs_clm_th_low[0], &ifs_clm_th_high[0],
-+					th_shift)) {
-+
-+		ccx->ifs_clm_app = ifs_clm_app;
-+		odm_move_memory(dm, &ccx->ifs_clm_th_en[0], &ifs_clm_th_en,
-+				IFS_CLM_NUM);
-+		odm_move_memory(dm, &ccx->ifs_clm_th_low[0], &ifs_clm_th_low,
-+				IFS_CLM_NUM);
-+		odm_move_memory(dm, &ccx->ifs_clm_th_high[0], &ifs_clm_th_high,
-+				IFS_CLM_NUM);
-+
-+		phydm_ifs_clm_set_th_reg(dm);
-+	}
-+}
-+
-+boolean
-+phydm_ifs_clm_mntr_set(void *dm_void, struct ifs_clm_para_info *ifs_clm_para)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u16 ifs_clm_time = 0; /*unit: 4/8/12/16us*/
-+	u8 unit = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	if (ifs_clm_para->mntr_time == 0)
-+		return false;
-+
-+	if (ifs_clm_para->ifs_clm_lv >= IFS_CLM_MAX_NUM) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Wrong LV=%d\n",
-+			  ifs_clm_para->ifs_clm_lv);
-+		return false;
-+	}
-+
-+	if (phydm_ifs_clm_racing_ctrl(dm, ifs_clm_para->ifs_clm_lv) == PHYDM_SET_FAIL)
-+		return false;
-+
-+	if (ifs_clm_para->mntr_time >= 1048) {
-+		unit = IFS_CLM_16;
-+		ifs_clm_time = IFS_CLM_PERIOD_MAX; /*65535 * 16us = 1048ms*/
-+	} else if (ifs_clm_para->mntr_time >= 786) {/*65535 * 12us = 786 ms*/
-+		unit = IFS_CLM_16;
-+		ifs_clm_time = PHYDM_DIV(ifs_clm_para->mntr_time * MS_TO_US, 16);
-+	} else if (ifs_clm_para->mntr_time >= 524) {
-+		unit = IFS_CLM_12;
-+		ifs_clm_time = PHYDM_DIV(ifs_clm_para->mntr_time * MS_TO_US, 12);
-+	} else if (ifs_clm_para->mntr_time >= 262) {
-+		unit = IFS_CLM_8;
-+		ifs_clm_time = PHYDM_DIV(ifs_clm_para->mntr_time * MS_TO_US, 8);
-+	} else {
-+		unit = IFS_CLM_4;
-+		ifs_clm_time = PHYDM_DIV(ifs_clm_para->mntr_time * MS_TO_US, 4);
-+	}
-+
-+	phydm_ifs_clm_set(dm, ifs_clm_para->ifs_clm_app, ifs_clm_time, unit,
-+			  ifs_clm_para->th_shift);
-+
-+	return true;
-+}
-+
-+boolean
-+phydm_ifs_clm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	struct ifs_clm_para_info ifs_clm_para = {0};
-+	boolean ifs_clm_chk_result = false;
-+	u32 sys_return_time = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	if (ccx->ifs_clm_manual_ctrl) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "IFS CLM in manual ctrl\n");
-+		return ifs_clm_chk_result;
-+	}
-+
-+	sys_return_time = ccx->ifs_clm_trigger_time + MAX_ENV_MNTR_TIME;
-+	if (ccx->ifs_clm_app != IFS_CLM_BACKGROUND &&
-+	    (sys_return_time > dm->phydm_sys_up_time)) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "ifs_clm_app=%d, trigger_time %d, sys_time=%d\n",
-+			  ccx->ifs_clm_app, ccx->ifs_clm_trigger_time,
-+			  dm->phydm_sys_up_time);
-+
-+		return ifs_clm_chk_result;
-+	}
-+
-+	/*[IFS CLM get result ------------------------------------]*/
-+	phydm_ifs_clm_get_result(dm);
-+	phydm_ifs_clm_get_utility(dm);
-+
-+	/*[IFS CLM trigger setting]------------------------------------------*/
-+	ifs_clm_para.ifs_clm_app = IFS_CLM_BACKGROUND;
-+	ifs_clm_para.ifs_clm_lv = IFS_CLM_LV_1;
-+	ifs_clm_para.mntr_time = monitor_time;
-+	ifs_clm_para.th_shift = 0;
-+
-+	ifs_clm_chk_result = phydm_ifs_clm_mntr_set(dm, &ifs_clm_para);
-+
-+	return ifs_clm_chk_result;
-+}
-+
-+void phydm_ifs_clm_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+
-+	ccx->ifs_clm_app = IFS_CLM_BACKGROUND;
-+
-+	/*Set IFS threshold*/
-+	ccx->ifs_clm_ongoing = false;
-+	ccx->ifs_clm_set_lv = IFS_CLM_RELEASE;
-+
-+	if (phydm_ifs_clm_th_update_chk(dm, ccx->ifs_clm_app,
-+					&ccx->ifs_clm_th_en[0],
-+					&ccx->ifs_clm_th_low[0],
-+					&ccx->ifs_clm_th_high[0], 0xffff))
-+		phydm_ifs_clm_set_th_reg(dm);
-+
-+	ccx->ifs_clm_period = 0;
-+	ccx->ifs_clm_ctrl_unit = IFS_CLM_INIT;
-+	ccx->ifs_clm_manual_ctrl = 0;
-+	ccx->ifs_clm_rpt_stamp = 0;
-+}
-+
-+void phydm_ifs_clm_dbg(void *dm_void, char input[][16], u32 *_used,
-+		       char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	struct ifs_clm_para_info ifs_clm_para;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 result_tmp = 0;
-+	u8 i = 0;
-+	u16 th_shift = 0;
-+
-+	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_IFS_CLM))
-+		return;
-+
-+	for (i = 0; i < 5; i++) {
-+		if (input[i + 1])
-+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
-+				     &var1[i]);
-+	}
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "IFS_CLM Basic-Trigger 960ms: {1}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "IFS_CLM Adv-Trigger: {2} {App:3 for dbg} {LV:1~4} {0~2096ms} {th_shift}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "IFS_CLM Get Result: {100}\n");
-+	} else if (var1[0] == 100) { /*Get IFS_CLM results*/
-+		phydm_ifs_clm_get_result(dm);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			  "ECLM_Rpt[%d]: \nTx = %d \nEDCCA_exclude_CCA = %d\n",
-+			  ccx->ifs_clm_rpt_stamp, ccx->ifs_clm_tx,
-+			  ccx->ifs_clm_edcca_excl_cca);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			  "[FA_cnt] {CCK, OFDM} = {%d, %d}\n",
-+			  ccx->ifs_clm_cckfa, ccx->ifs_clm_ofdmfa);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			  "[CCA_exclude_FA_cnt] {CCK, OFDM} = {%d, %d}\n",
-+			  ccx->ifs_clm_cckcca_excl_fa,
-+			  ccx->ifs_clm_ofdmcca_excl_fa);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "CCATotal = %d\n", ccx->ifs_clm_total_cca);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Time:[his, avg, avg_cca]\n");
-+		for (i = 0; i < IFS_CLM_NUM; i++)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				  "T%d:[%d, %d, %d]\n", i + 1,
-+				  ccx->ifs_clm_his[i], ccx->ifs_clm_avg[i],
-+				  ccx->ifs_clm_avg_cca[i]);
-+
-+		phydm_ifs_clm_get_utility(dm);
-+
-+		ccx->ifs_clm_manual_ctrl = 0;
-+	} else { /*IFS_CLM trigger*/
-+		ccx->ifs_clm_manual_ctrl = 1;
-+
-+		if (var1[0] == 1) {
-+			ifs_clm_para.ifs_clm_app = IFS_CLM_DBG;
-+			ifs_clm_para.ifs_clm_lv = IFS_CLM_LV_4;
-+			ifs_clm_para.mntr_time = 960;
-+			ifs_clm_para.th_shift = 0;
-+		} else {
-+			ifs_clm_para.ifs_clm_app = (enum ifs_clm_application)var1[1];
-+			ifs_clm_para.ifs_clm_lv = (enum phydm_ifs_clm_level)var1[2];
-+			ifs_clm_para.mntr_time = (u16)var1[3];
-+			ifs_clm_para.th_shift = (s16)var1[4];
-+		}
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "app=%d, lv=%d, time=%d ms, th_shift=%s%d\n",
-+			 ifs_clm_para.ifs_clm_app, ifs_clm_para.ifs_clm_lv,
-+			 ifs_clm_para.mntr_time,
-+			 (ifs_clm_para.th_shift > 0) ? "+" : "-",
-+			 ifs_clm_para.th_shift);
-+
-+		if (phydm_ifs_clm_mntr_set(dm, &ifs_clm_para) == PHYDM_SET_SUCCESS)
-+			phydm_ifs_clm_trigger(dm);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "rpt_stamp=%d\n", ccx->ifs_clm_rpt_stamp);
-+		for (i = 0; i < IFS_CLM_NUM; i++)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				  "IFS_CLM_th%d[High Low] : [%d %d]\n", i + 1,
-+			  	  ccx->ifs_clm_th_high[i],
-+			  	  ccx->ifs_clm_th_low[i]);
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+#endif
-+
-+u8 phydm_enhance_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para,
-+			     struct clm_para_info *clm_para,
-+			     struct fahm_para_info *fahm_para,
-+			     struct ifs_clm_para_info *ifs_clm_para,
-+			     struct enhance_mntr_trig_rpt *trig_rpt)
-+{
-+	u8 trigger_result = 0;
-+#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT) && defined(FAHM_SUPPORT) && defined(IFS_CLM_SUPPORT))
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	boolean nhm_set_ok = false;
-+	boolean clm_set_ok = false;
-+	boolean fahm_set_ok = false;
-+	boolean ifs_clm_set_ok = false;
-+
-+	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_FAHM) ||
-+	    !(dm->support_ic_type & PHYDM_IC_SUPPORT_IFS_CLM))
-+		return trigger_result;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
-+
-+	nhm_set_ok = phydm_nhm_mntr_set(dm, nhm_para);
-+
-+	if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) {
-+		clm_set_ok = phydm_clm_mntr_set(dm, clm_para);
-+	} else if (ccx->clm_mntr_mode == CLM_FW_MNTR) {
-+		phydm_clm_h2c(dm, CLM_PERIOD_MAX, true);
-+		trigger_result |= CLM_SUCCESS;
-+	}
-+
-+	fahm_set_ok = phydm_fahm_mntr_set(dm, fahm_para);
-+
-+	ifs_clm_set_ok = phydm_ifs_clm_mntr_set(dm, ifs_clm_para);
-+
-+	if (nhm_set_ok) {
-+		phydm_nhm_trigger(dm);
-+		trigger_result |= NHM_SUCCESS;
-+	}
-+
-+	if (clm_set_ok) {
-+		phydm_clm_trigger(dm);
-+		trigger_result |= CLM_SUCCESS;
-+	}
-+
-+	if (fahm_set_ok) {
-+		phydm_fahm_trigger(dm);
-+		trigger_result |= FAHM_SUCCESS;
-+	}
-+
-+	if (ifs_clm_set_ok) {
-+		phydm_ifs_clm_trigger(dm);
-+		trigger_result |= IFS_CLM_SUCCESS;
-+	}
-+
-+	/*monitor for the test duration*/
-+	ccx->start_time = odm_get_current_time(dm);
-+
-+	trig_rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp;
-+	trig_rpt->clm_rpt_stamp = ccx->clm_rpt_stamp;
-+	trig_rpt->fahm_rpt_stamp = ccx->fahm_rpt_stamp;
-+	trig_rpt->ifs_clm_rpt_stamp = ccx->ifs_clm_rpt_stamp;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "rpt_stamp{NHM, CLM, FAHM, IFS_CLM}={%d, %d, %d, %d}\n\n",
-+		  trig_rpt->nhm_rpt_stamp, trig_rpt->clm_rpt_stamp,
-+		  trig_rpt->fahm_rpt_stamp, trig_rpt->ifs_clm_rpt_stamp);
-+
-+#endif
-+	return trigger_result;
-+}
-+
-+u8 phydm_enhance_mntr_result(void *dm_void, struct enhance_mntr_rpt *rpt)
-+{
-+	u8 enhance_mntr_rpt = 0;
-+#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT) && defined(FAHM_SUPPORT) && defined(IFS_CLM_SUPPORT))
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u64 progressing_time = 0;
-+	u32 val_tmp = 0;
-+
-+	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_FAHM) ||
-+	    !(dm->support_ic_type & PHYDM_IC_SUPPORT_IFS_CLM))
-+		return enhance_mntr_rpt;
-+
-+	/*monitor for the test duration*/
-+	progressing_time = odm_get_progressing_time(dm, ccx->start_time);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__);
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "enhance_mntr_time=%lld\n",
-+		  progressing_time);
-+
-+	/*Get NHM result*/
-+	if (phydm_nhm_get_result(dm)) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n");
-+		phydm_nhm_get_utility(dm);
-+		rpt->nhm_ratio = ccx->nhm_ratio;
-+		rpt->nhm_env_ratio = ccx->nhm_env_ratio;
-+		rpt->nhm_noise_pwr = ccx->nhm_level;
-+		rpt->nhm_pwr = ccx->nhm_pwr;
-+		enhance_mntr_rpt |= NHM_SUCCESS;
-+
-+		odm_move_memory(dm, &rpt->nhm_result[0],
-+				&ccx->nhm_result[0], NHM_RPT_NUM);
-+	} else {
-+		rpt->nhm_ratio = ENV_MNTR_FAIL;
-+		rpt->nhm_env_ratio = ENV_MNTR_FAIL;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "[NHM]rpt_stamp=%d, IGI=0x%x, ratio=%d, env_ratio=%d, noise_pwr=%d, pwr=%d\n",
-+		  rpt->nhm_rpt_stamp, ccx->nhm_igi, rpt->nhm_ratio,
-+		  rpt->nhm_env_ratio, rpt->nhm_noise_pwr, rpt->nhm_pwr);
-+
-+	/*Get CLM result*/
-+	if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) {
-+		if (phydm_clm_get_result(dm)) {
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM_rpt success\n");
-+			phydm_clm_get_utility(dm);
-+			enhance_mntr_rpt |= CLM_SUCCESS;
-+			rpt->clm_ratio = ccx->clm_ratio;
-+		} else {
-+			rpt->clm_ratio = ENV_MNTR_FAIL;
-+		}
-+	} else {
-+		if (ccx->clm_fw_result_cnt != 0) {
-+			val_tmp = ccx->clm_fw_result_acc
-+			/ ccx->clm_fw_result_cnt;
-+			ccx->clm_ratio = (u8)val_tmp;
-+		} else {
-+			ccx->clm_ratio = 0;
-+		}
-+		rpt->clm_ratio = ccx->clm_ratio;
-+		PHYDM_DBG(dm, DBG_ENV_MNTR,
-+			  "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n",
-+			  ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt);
-+
-+		ccx->clm_fw_result_acc = 0;
-+		ccx->clm_fw_result_cnt = 0;
-+		enhance_mntr_rpt |= CLM_SUCCESS;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[CLM]rpt_stamp=%d, ratio=%d\n",
-+		  rpt->clm_rpt_stamp, rpt->clm_ratio);
-+
-+	/*Get FAHM result*/
-+	if (phydm_fahm_get_result(dm)) {
-+		PHYDM_DBG(dm, DBG_ENV_MNTR, "Get FAHM_rpt success\n");
-+		phydm_fahm_get_utility(dm);
-+		rpt->fahm_pwr = ccx->fahm_pwr;
-+		enhance_mntr_rpt |= FAHM_SUCCESS;
-+
-+		odm_move_memory(dm, &rpt->fahm_result[0],
-+				&ccx->fahm_result[0], NHM_RPT_NUM * 2);
-+	} else {
-+		rpt->fahm_pwr = 0;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[FAHM]rpt_stamp=%d, IGI=0x%x, pwr=%d\n",
-+		  rpt->fahm_rpt_stamp, ccx->fahm_igi, rpt->fahm_pwr);
-+
-+	/*Get IFS_CLM result*/
-+	phydm_ifs_clm_get_result(dm);
-+	phydm_ifs_clm_get_utility(dm);
-+	rpt->ifs_clm_tx_ratio = ccx->ifs_clm_tx_ratio;
-+	rpt->ifs_clm_edcca_excl_cca_ratio = ccx->ifs_clm_edcca_excl_cca_ratio;
-+	rpt->ifs_clm_fa_ratio = ccx->ifs_clm_fa_ratio;
-+	rpt->ifs_clm_cca_excl_fa_ratio = ccx->ifs_clm_cca_excl_fa_ratio;
-+	rpt->ifs_clm_rpt_stamp = ccx->ifs_clm_rpt_stamp;
-+	enhance_mntr_rpt |= IFS_CLM_SUCCESS;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "[IFS_CLM]rpt_stamp = %d, Tx_ratio = %d, EDCCA_exclude_CCA_ratio = %d\n",
-+		  ccx->ifs_clm_rpt_stamp, ccx->ifs_clm_tx_ratio,
-+		  ccx->ifs_clm_edcca_excl_cca_ratio);	
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "FA_ratio = %d, CCA_exclude_FA_ratio = %d\n",
-+		  ccx->ifs_clm_fa_ratio, ccx->ifs_clm_cca_excl_fa_ratio);
-+
-+	rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp;
-+	rpt->clm_rpt_stamp = ccx->clm_rpt_stamp;
-+	rpt->fahm_rpt_stamp = ccx->fahm_rpt_stamp;
-+	rpt->ifs_clm_rpt_stamp = ccx->ifs_clm_rpt_stamp;
-+#endif
-+	return enhance_mntr_rpt;
-+}
-+
-+void phydm_enhance_mntr_watchdog(void *dm_void)
-+{
-+#ifdef IFS_CLM_SUPPORT
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	boolean ifs_clm_chk_ok = false;
-+
-+	if (!(dm->support_ability & ODM_BB_ENV_MONITOR))
-+		return;
-+
-+	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_IFS_CLM))
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+	ifs_clm_chk_ok = phydm_ifs_clm_mntr_chk(dm, 960); /*monitor 960ms*/
-+
-+	if (ifs_clm_chk_ok)
-+		phydm_ifs_clm_trigger(dm);
-+#endif
-+}
-+
-+void phydm_enhance_monitor_init(void *dm_void)
-+{
-+#ifdef IFS_CLM_SUPPORT
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_IFS_CLM))
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__);
-+	phydm_ifs_clm_restart(dm);
-+	phydm_ifs_clm_init(dm);
-+#endif
-+}
-+
-+void phydm_enhance_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
-+			    char *output, u32 *_out_len)
-+{
-+#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT) && defined(FAHM_SUPPORT) && defined(IFS_CLM_SUPPORT))
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	struct nhm_para_info nhm_para = {0};
-+	struct clm_para_info clm_para = {0};
-+	struct fahm_para_info fahm_para = {0};
-+	struct ifs_clm_para_info ifs_clm_para = {0};
-+	struct enhance_mntr_rpt rpt = {0};
-+	struct enhance_mntr_trig_rpt trig_rpt = {0};
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u8 set_result = 0;
-+	u8 i = 0;
-+
-+	if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_FAHM) ||
-+	    !(dm->support_ic_type & PHYDM_IC_SUPPORT_IFS_CLM))
-+		return;
-+
-+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Basic-Trigger 960ms for ifs_clm, 262ms for others: {1}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Get Result: {100}\n");
-+	} else if (var1[0] == 100) { /* Get results */
-+		set_result = phydm_enhance_mntr_result(dm, &rpt);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Set Result=%d, rpt_stamp{NHM, CLM, FAHM, IFS_CLM}={%d, %d, %d, %d}\n",
-+			 set_result, rpt.nhm_rpt_stamp, rpt.clm_rpt_stamp,
-+			 rpt.fahm_rpt_stamp, rpt.ifs_clm_rpt_stamp);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "nhm_IGI=0x%x, nhm_ratio=%d, ,nhm_env_ratio=%d, noise_pwr=%d, pwr=%d\n",
-+			 ccx->nhm_igi, rpt.nhm_ratio, rpt.nhm_env_ratio,
-+			 rpt.nhm_noise_pwr, rpt.nhm_pwr);
-+
-+		for (i = 0; i <= 11; i++) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "nhm_rpt[%d] = %d (%d percent)\n", i,
-+				 rpt.nhm_result[i],
-+				 (((rpt.nhm_result[i] * 100) + 128) >> 8));
-+		}
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "clm_ratio=%d, fahm_IGI=0x%x, fahm_pwr=%d\n",
-+			 rpt.clm_ratio, ccx->fahm_igi, rpt.fahm_pwr);
-+
-+		for (i = 0; i <= 11; i++) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "fahm_rpt[%d] = %d (%d percent)\n", i,
-+				 rpt.fahm_result[i],
-+				 (((rpt.fahm_result[i] * 100) + 32768) >> 16));
-+		}
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "ifs_clm_Tx_ratio = %d, ifs_clm_EDCCA_exclude_CCA_ratio = %d \n",
-+			 rpt.ifs_clm_tx_ratio,
-+			 rpt.ifs_clm_edcca_excl_cca_ratio);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "ifs_clm_FA_ratio = %d, ifs_clm_CCA_exclude_FA_ratio = %d \n",
-+			 rpt.ifs_clm_fa_ratio, rpt.ifs_clm_cca_excl_fa_ratio);
-+	} else { /* Set & trigger*/
-+		/*nhm para*/
-+		nhm_para.incld_txon = NHM_EXCLUDE_TXON;
-+		nhm_para.incld_cca = NHM_EXCLUDE_CCA;
-+		nhm_para.div_opt = NHM_CNT_ALL;
-+		nhm_para.nhm_app = NHM_ACS;
-+		nhm_para.nhm_lv = NHM_LV_2;
-+		nhm_para.mntr_time = 262;
-+		nhm_para.en_1db_mode = false;
-+
-+		/*clm para*/
-+		clm_para.clm_app = CLM_ACS;
-+		clm_para.clm_lv = CLM_LV_2;
-+		clm_para.mntr_time = 262;
-+
-+		/*fahm para*/
-+		fahm_para.incld_fa = FAHM_INCLUDE_FA;
-+		fahm_para.incld_crc32_ok = FAHM_EXCLUDE_CRC32_OK;
-+		fahm_para.incld_crc32_err = FAHM_EXCLUDE_CRC32_ERR;
-+		fahm_para.app = FAHM_ACS;
-+		fahm_para.lv = FAHM_LV_2;
-+		fahm_para.mntr_time = 262;
-+		fahm_para.en_1db_mode = false;
-+
-+		ifs_clm_para.ifs_clm_app = IFS_CLM_ACS;
-+		ifs_clm_para.ifs_clm_lv = IFS_CLM_LV_2;
-+		ifs_clm_para.mntr_time = 960;
-+		ifs_clm_para.th_shift = 0;
-+
-+		set_result = phydm_enhance_mntr_trigger(dm, &nhm_para,
-+							&clm_para, &fahm_para,
-+							&ifs_clm_para,
-+							&trig_rpt);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Set Result=%d, rpt_stamp{NHM, CLM, FAHM, IFS_CLM}={%d, %d ,%d, %d}\n",
-+			 set_result, trig_rpt.nhm_rpt_stamp,
-+			 trig_rpt.clm_rpt_stamp, trig_rpt.fahm_rpt_stamp,
-+			 trig_rpt.ifs_clm_rpt_stamp);
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+#endif
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_ccx.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_ccx.h
-new file mode 100644
-index 000000000000..a125a1685555
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_ccx.h
-@@ -0,0 +1,428 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDMCCX_H__
-+#define __PHYDMCCX_H__
-+
-+/* 2020.07.21 Fix 8723F compile warning and remove 8723f in dym_pw_th(this machanism is WA patch only for 8822C ASUS)*/
-+#define CCX_VERSION "4.4"
-+
-+/* @1 ============================================================
-+ * 1  Definition
-+ * 1 ============================================================
-+ */
-+#define CCX_EN 1
-+
-+#define	MAX_ENV_MNTR_TIME	8	/*second*/
-+#define	MS_TO_US		1000
-+#define	MS_TO_4US_RATIO		250
-+#define	CCA_CAP			14
-+#define	CLM_MAX_REPORT_TIME	10
-+#define	CLM_PERIOD_MAX		65535
-+#define	IFS_CLM_PERIOD_MAX	65535
-+#define	NHM_PERIOD_MAX		65534
-+#define	NHM_TH_NUM		11	/*threshold number of NHM/FAHM*/
-+#define	NHM_RPT_NUM		12
-+#define NHM_IC_NOISE_TH		60	/*60/2 - 10 = 20 = -80 dBm*/
-+#define	IFS_CLM_NUM		4
-+#ifdef NHM_DYM_PW_TH_SUPPORT
-+#define	DYM_PWTH_CCA_CAP	24
-+#endif
-+
-+#define	IGI_2_NHM_TH(igi)	((igi) << 1)/*NHM/FAHM threshold = IGI * 2*/
-+#define	NTH_TH_2_RSSI(th)	((th >> 1) - 10)
-+
-+#define NHM_SUCCESS		BIT(0)
-+#define CLM_SUCCESS		BIT(1)
-+#define FAHM_SUCCESS		BIT(2)
-+#define IFS_CLM_SUCCESS		BIT(3)
-+#define	ENV_MNTR_FAIL		0xff
-+
-+/* @1 ============================================================
-+ * 1 enumrate
-+ * 1 ============================================================
-+ */
-+enum phydm_clm_level {
-+	CLM_RELEASE		= 0,
-+	CLM_LV_1		= 1,	/* @Low Priority function */
-+	CLM_LV_2		= 2,	/* @Middle Priority function */
-+	CLM_LV_3		= 3,	/* @High priority function (ex: Check hang function) */
-+	CLM_LV_4		= 4,	/* @Debug function (the highest priority) */
-+	CLM_MAX_NUM		= 5
-+};
-+
-+enum phydm_nhm_level {
-+	NHM_RELEASE		= 0,
-+	NHM_LV_1		= 1,	/* @Low Priority function */
-+	NHM_LV_2		= 2,	/* @Middle Priority function */
-+	NHM_LV_3		= 3,	/* @High priority function (ex: Check hang function) */
-+	NHM_LV_4		= 4,	/* @Debug function (the highest priority) */
-+	NHM_MAX_NUM		= 5
-+};
-+
-+enum phydm_fahm_level {
-+	FAHM_RELEASE		= 0,
-+	FAHM_LV_1		= 1,	/* Low Priority function */
-+	FAHM_LV_2		= 2,	/* Middle Priority function */
-+	FAHM_LV_3		= 3,	/* High priority function (ex: Check hang function) */
-+	FAHM_LV_4		= 4,	/* Debug function (the highest priority) */
-+	FAHM_MAX_NUM		= 5
-+};
-+
-+enum phydm_ifs_clm_level {
-+	IFS_CLM_RELEASE		= 0,
-+	IFS_CLM_LV_1		= 1,	/* @Low Priority function */
-+	IFS_CLM_LV_2		= 2,	/* @Middle Priority function */
-+	IFS_CLM_LV_3		= 3,	/* @High priority function (ex: Check hang function) */
-+	IFS_CLM_LV_4		= 4,	/* @Debug function (the highest priority) */
-+	IFS_CLM_MAX_NUM		= 5
-+};
-+
-+enum nhm_divider_opt_all {
-+	NHM_CNT_ALL		= 0,	/*nhm SUM report <= 255*/
-+	NHM_VALID		= 1,	/*nhm SUM report = 255*/
-+	NHM_CNT_INIT
-+};
-+
-+enum nhm_setting {
-+	SET_NHM_SETTING,
-+	STORE_NHM_SETTING,
-+	RESTORE_NHM_SETTING
-+};
-+
-+enum nhm_option_cca_all {
-+	NHM_EXCLUDE_CCA		= 0,
-+	NHM_INCLUDE_CCA		= 1,
-+	NHM_CCA_INIT
-+};
-+
-+enum nhm_option_txon_all {
-+	NHM_EXCLUDE_TXON	= 0,
-+	NHM_INCLUDE_TXON	= 1,
-+	NHM_TXON_INIT
-+};
-+
-+enum nhm_application {
-+	NHM_BACKGROUND		= 0,/*@default*/
-+	NHM_ACS			= 1,
-+	IEEE_11K_HIGH		= 2,
-+	IEEE_11K_LOW		= 3,
-+	INTEL_XBOX		= 4,
-+	NHM_DBG			= 5, /*@manual trigger*/
-+};
-+
-+enum clm_application {
-+	CLM_BACKGROUND		= 0,/*@default*/
-+	CLM_ACS			= 1,
-+};
-+
-+enum fahm_opt_fa {
-+	FAHM_EXCLUDE_FA	= 	0,
-+	FAHM_INCLUDE_FA	= 	1,
-+	FAHM_FA_INIT
-+};
-+
-+enum fahm_opt_crc32_ok {
-+	FAHM_EXCLUDE_CRC32_OK	= 0,
-+	FAHM_INCLUDE_CRC32_OK	= 1,
-+	FAHM_CRC32_OK_INIT
-+};
-+
-+enum fahm_opt_crc32_err {
-+	FAHM_EXCLUDE_CRC32_ERR	= 0,
-+	FAHM_INCLUDE_CRC32_ERR	= 1,
-+	FAHM_CRC32_ERR_INIT
-+};
-+
-+enum fahm_application {
-+	FAHM_BACKGROUND		= 0,/*default*/
-+	FAHM_ACS		= 1,
-+	FAHM_DBG		= 2, /*manual trigger*/
-+};
-+
-+enum ifs_clm_application {
-+	IFS_CLM_BACKGROUND		= 0,/*default*/
-+	IFS_CLM_ACS			= 1,
-+	IFS_CLM_HP_TAS			= 2,
-+	IFS_CLM_DBG			= 3,
-+};
-+
-+enum clm_monitor_mode {
-+	CLM_DRIVER_MNTR		= 1,
-+	CLM_FW_MNTR		= 2
-+};
-+
-+enum phydm_ifs_clm_unit {
-+	IFS_CLM_4		= 0,	/*4us*/
-+	IFS_CLM_8		= 1,	/*8us*/
-+	IFS_CLM_12		= 2,	/*12us*/
-+	IFS_CLM_16		= 3,	/*16us*/
-+	IFS_CLM_INIT
-+};
-+
-+/* @1 ============================================================
-+ * 1  structure
-+ * 1 ============================================================
-+ */
-+struct env_trig_rpt {
-+	u8			nhm_rpt_stamp;
-+	u8			clm_rpt_stamp;
-+};
-+
-+struct env_mntr_rpt {
-+	u8			nhm_ratio;
-+	u8			nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/
-+	u8			nhm_result[NHM_RPT_NUM];
-+	u8			clm_ratio;
-+	u8			nhm_rpt_stamp;
-+	u8			clm_rpt_stamp;
-+	u8			nhm_noise_pwr; /*including r[0]~r[10]*/
-+	u8			nhm_pwr; /*including r[0]~r[11]*/
-+};
-+
-+struct enhance_mntr_trig_rpt {
-+	u8			nhm_rpt_stamp;
-+	u8			clm_rpt_stamp;
-+	u8			fahm_rpt_stamp;
-+	u8			ifs_clm_rpt_stamp;
-+};
-+
-+struct enhance_mntr_rpt {
-+	u8			nhm_ratio;
-+	u8			nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/
-+	u8			nhm_result[NHM_RPT_NUM];
-+	u8			clm_ratio;
-+	u8			nhm_rpt_stamp;
-+	u8			clm_rpt_stamp;
-+	u8			nhm_noise_pwr; /*including r[0]~r[10]*/
-+	u8			nhm_pwr; /*including r[0]~r[11]*/
-+	u16			fahm_result[NHM_RPT_NUM];
-+	u8			fahm_rpt_stamp;
-+	u8			fahm_pwr;
-+	u8			ifs_clm_rpt_stamp;
-+	u8			ifs_clm_tx_ratio;
-+	u8			ifs_clm_edcca_excl_cca_ratio;
-+	u8			ifs_clm_fa_ratio;
-+	u8			ifs_clm_cca_excl_fa_ratio;
-+};
-+
-+struct nhm_para_info {
-+	enum nhm_option_txon_all	incld_txon;	/*@Include TX on*/
-+	enum nhm_option_cca_all		incld_cca;	/*@Include CCA*/
-+	enum nhm_divider_opt_all	div_opt;	/*@divider option*/
-+	enum nhm_application		nhm_app;
-+	enum phydm_nhm_level		nhm_lv;
-+	u16				mntr_time;	/*@0~262 unit ms*/
-+	boolean				en_1db_mode;
-+	u8				nhm_th0_manual;	/* for 1-db mode*/
-+};
-+
-+struct clm_para_info {
-+	enum clm_application		clm_app;
-+	enum phydm_clm_level		clm_lv;
-+	u16				mntr_time;	/*@0~262 unit ms*/
-+};
-+
-+struct fahm_para_info {
-+	enum fahm_opt_fa		incld_fa;
-+	enum fahm_opt_crc32_ok		incld_crc32_ok;
-+	enum fahm_opt_crc32_err		incld_crc32_err;
-+	enum fahm_application		app;
-+	enum phydm_fahm_level		lv;
-+	u16				mntr_time;	/*0~262 unit ms*/
-+	boolean				en_1db_mode;
-+	u8				th0_manual;/* for 1-db mode*/
-+};
-+
-+struct ifs_clm_para_info {
-+	enum ifs_clm_application	ifs_clm_app;
-+	enum phydm_ifs_clm_level	ifs_clm_lv;
-+	enum phydm_ifs_clm_unit		ifs_clm_ctrl_unit;	/*unit*/
-+	u16				mntr_time;	/*ms*/
-+	boolean				ifs_clm_th_en[IFS_CLM_NUM];
-+	u16				ifs_clm_th_low[IFS_CLM_NUM];
-+	u16				ifs_clm_th_high[IFS_CLM_NUM];
-+	s16				th_shift;
-+};
-+
-+struct ccx_info {
-+	u32			nhm_trigger_time;
-+	u32			clm_trigger_time;
-+	u32			fahm_trigger_time;
-+	u32			ifs_clm_trigger_time;
-+	u64			start_time;	/*@monitor for the test duration*/
-+#ifdef NHM_SUPPORT
-+	enum nhm_application		nhm_app;
-+	enum nhm_option_txon_all	nhm_include_txon;
-+	enum nhm_option_cca_all		nhm_include_cca;
-+	enum nhm_divider_opt_all 	nhm_divider_opt;
-+	/*Report*/
-+	u8			nhm_th[NHM_TH_NUM];
-+	u8			nhm_result[NHM_RPT_NUM];
-+	u8			nhm_wgt[NHM_RPT_NUM];
-+	u16			nhm_period;	/* @4us per unit */
-+	u8			nhm_igi;
-+	u8			nhm_manual_ctrl;
-+	u8			nhm_ratio;	/*@1% per nuit, it means the interference igi can't overcome.*/
-+	u8			nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/
-+	u8			nhm_rpt_sum;
-+	u8			nhm_set_lv;
-+	boolean			nhm_ongoing;
-+	u8			nhm_rpt_stamp;
-+	u8			nhm_level; /*including r[0]~r[10]*/
-+	u8			nhm_level_valid;
-+	u8			nhm_pwr; /*including r[0]~r[11]*/
-+#ifdef NHM_DYM_PW_TH_SUPPORT
-+	boolean			nhm_dym_pw_th_en;
-+	boolean			dym_pwth_manual_ctrl;
-+	u8			pw_th_rf20_ori;
-+	u8			pw_th_rf20_cur;
-+	u8			nhm_pw_th_max;
-+	u8			nhm_period_decre;
-+	u8			nhm_sl_pw_th;
-+#endif
-+#endif
-+
-+#ifdef CLM_SUPPORT
-+	enum clm_application	clm_app;
-+	u8			clm_manual_ctrl;
-+	u8			clm_set_lv;
-+	boolean			clm_ongoing;
-+	u16			clm_period;	/* @4us per unit */
-+	u16			clm_result;
-+	u8			clm_ratio;
-+	u32			clm_fw_result_acc;
-+	u8			clm_fw_result_cnt;
-+	enum clm_monitor_mode	clm_mntr_mode;
-+	u8			clm_rpt_stamp;
-+#endif
-+#ifdef FAHM_SUPPORT
-+	enum fahm_application	fahm_app;
-+	enum fahm_opt_fa	fahm_incld_fa;
-+	enum fahm_opt_crc32_ok	fahm_incld_crc32_ok;
-+	enum fahm_opt_crc32_err	fahm_incld_crc32_err;
-+	boolean			fahm_ongoing;
-+	u8			fahm_nume_sel;	/*@fahm_numerator_sel: select {FA, CRCOK, CRC_fail} */
-+	u8			fahm_denom_sel;	/*@fahm_denominator_sel: select {FA, CRCOK, CRC_fail} */
-+	u8			fahm_th[NHM_TH_NUM];
-+	u16			fahm_result[NHM_RPT_NUM];
-+	u16			fahm_period;	/*unit: 4us*/
-+	u8			fahm_igi;
-+	u8			fahm_manual_ctrl;
-+	u16			fahm_rpt_sum;
-+	u8			fahm_set_lv;
-+	u8			fahm_rpt_stamp;
-+	u8			fahm_pwr; /*including r[0]~r[11]*/
-+#endif
-+#ifdef IFS_CLM_SUPPORT
-+	enum ifs_clm_application	ifs_clm_app;
-+	/*Control*/
-+	enum phydm_ifs_clm_unit ifs_clm_ctrl_unit; /*4,8,12,16us per unit*/
-+	u16			ifs_clm_period;
-+	boolean			ifs_clm_th_en[IFS_CLM_NUM];
-+	u16			ifs_clm_th_low[IFS_CLM_NUM];
-+	u16			ifs_clm_th_high[IFS_CLM_NUM];
-+	/*Flow control*/
-+	u8			ifs_clm_set_lv;
-+	u8			ifs_clm_manual_ctrl;
-+	boolean			ifs_clm_ongoing;
-+	/*Report*/
-+	u8			ifs_clm_rpt_stamp;
-+	u16			ifs_clm_tx;
-+	u16			ifs_clm_edcca_excl_cca;
-+	u16			ifs_clm_ofdmfa;
-+	u16			ifs_clm_ofdmcca_excl_fa;
-+	u16			ifs_clm_cckfa;
-+	u16			ifs_clm_cckcca_excl_fa;
-+	u8			ifs_clm_his[IFS_CLM_NUM];	/*trx_neg_edge to CCA/FA posedge per times*/
-+	u16			ifs_clm_total_cca;
-+	u16			ifs_clm_avg[IFS_CLM_NUM];	/*4,8,12,16us per unit*/
-+	u16			ifs_clm_avg_cca[IFS_CLM_NUM];	/*4,8,12,16us per unit*/
-+	u8			ifs_clm_tx_ratio;
-+	u8			ifs_clm_edcca_excl_cca_ratio;
-+	u8			ifs_clm_fa_ratio;
-+	u8			ifs_clm_cca_excl_fa_ratio;
-+#endif
-+};
-+
-+/* @1 ============================================================
-+ * 1 Function Prototype
-+ * 1 ============================================================
-+ */
-+
-+#ifdef FAHM_SUPPORT
-+void phydm_fahm_init(void *dm_void);
-+
-+void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
-+		    u32 *_out_len);
-+#endif
-+
-+#ifdef NHM_SUPPORT
-+void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
-+		   u32 *_out_len);
-+u8 phydm_get_igi(void *dm_void, enum bb_path path);
-+#endif
-+
-+#ifdef CLM_SUPPORT
-+void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
-+
-+void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
-+		   u32 *_out_len);
-+#endif
-+
-+u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para,
-+			  struct clm_para_info *clm_para,
-+			  struct env_trig_rpt *rpt);
-+
-+u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt);
-+
-+void phydm_env_mntr_watchdog(void *dm_void);
-+
-+void phydm_env_monitor_init(void *dm_void);
-+
-+void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
-+			char *output, u32 *_out_len);
-+
-+#ifdef IFS_CLM_SUPPORT
-+void phydm_ifs_clm_dbg(void *dm_void, char input[][16], u32 *_used,
-+		       char *output, u32 *_out_len);
-+#endif
-+
-+u8 phydm_enhance_mntr_trigger(void *dm_void,
-+			      struct nhm_para_info *nhm_para,
-+			      struct clm_para_info *clm_para,
-+			      struct fahm_para_info *fahm_para,
-+			      struct ifs_clm_para_info *ifs_clm_para,
-+			      struct enhance_mntr_trig_rpt *trig_rpt);
-+
-+u8 phydm_enhance_mntr_result(void *dm_void, struct enhance_mntr_rpt *rpt);
-+
-+void phydm_enhance_mntr_watchdog(void *dm_void);
-+
-+void phydm_enhance_monitor_init(void *dm_void);
-+
-+void phydm_enhance_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
-+			char *output, u32 *_out_len);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_cfotracking.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_cfotracking.c
-new file mode 100644
-index 000000000000..748556bf7065
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_cfotracking.c
-@@ -0,0 +1,623 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+s32 phydm_get_cfo_hz(void *dm_void, u32 val, u8 bit_num, u8 frac_num)
-+{
-+	s32 val_s = 0;
-+
-+	val_s = phydm_cnvrt_2_sign(val, bit_num);
-+
-+	if (frac_num == 10) /*@ (X*312500)/1024 ~= X*305*/
-+		val_s *= 305;
-+	else if (frac_num == 11) /*@ (X*312500)/2048 ~= X*152*/
-+		val_s *= 152;
-+	else if (frac_num == 12) /*@ (X*312500)/4096 ~= X*76*/
-+		val_s *= 76;
-+
-+	return val_s;
-+}
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT)
-+void phydm_get_cfo_info_ac(void *dm_void, struct phydm_cfo_rpt *cfo)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i = 0;
-+	u32 val[4] = {0};
-+	u32 val_1[4] = {0};
-+	u32 val_2[4] = {0};
-+	u32 val_tmp = 0;
-+
-+	val[0] = odm_read_4byte(dm, R_0xd0c);
-+	val_1[0] = odm_read_4byte(dm, R_0xd10);
-+	val_2[0] = odm_get_bb_reg(dm, R_0xd14, 0x1fff0000);
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	val[1] = odm_read_4byte(dm, R_0xd4c);
-+	val_1[1] = odm_read_4byte(dm, R_0xd50);
-+	val_2[1] = odm_get_bb_reg(dm, R_0xd54, 0x1fff0000);
-+	#endif
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	val[2] = odm_read_4byte(dm, R_0xd8c);
-+	val_1[2] = odm_read_4byte(dm, R_0xd90);
-+	val_2[2] = odm_get_bb_reg(dm, R_0xd94, 0x1fff0000);
-+	#endif
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	val[3] = odm_read_4byte(dm, R_0xdcc);
-+	val_1[3] = odm_read_4byte(dm, R_0xdd0);
-+	val_2[3] = odm_get_bb_reg(dm, R_0xdd4, 0x1fff0000);
-+	#endif
-+
-+	for (i = 0; i < dm->num_rf_path; i++) {
-+		val_tmp = val[i] & 0xfff;	/*@ Short CFO, S(12,11)*/
-+		cfo->cfo_rpt_s[i] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
-+
-+		val_tmp = val[i] >> 16;		/*@ Long CFO, S(13,12)*/
-+		cfo->cfo_rpt_l[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
-+
-+		val_tmp = val_1[i] & 0x7ff;	/*@ SCFO, S(11,10)*/
-+		cfo->cfo_rpt_sec[i] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
-+
-+		val_tmp = val_1[i] >> 16;	/*@ Acq CFO, S(13,12)*/
-+		cfo->cfo_rpt_acq[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
-+
-+		val_tmp = val_2[i];		/*@ End CFO, S(13,12)*/
-+		cfo->cfo_rpt_end[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
-+	}
-+}
-+#endif
-+
-+#if (ODM_IC_11N_SERIES_SUPPORT)
-+void phydm_get_cfo_info_n(void *dm_void, struct phydm_cfo_rpt *cfo)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 val[5] = {0};
-+	u32 val_tmp = 0;
-+
-+	odm_set_bb_reg(dm, R_0xd00, BIT(26), 1);
-+
-+	val[0] = odm_read_4byte(dm, R_0xdac); /*@ Short CFO*/
-+	val[1] = odm_read_4byte(dm, R_0xdb0); /*@ Long CFO*/
-+	val[2] = odm_read_4byte(dm, R_0xdb8); /*@ Sec CFO*/
-+	val[3] = odm_read_4byte(dm, R_0xde0); /*@ Acq CFO*/
-+	val[4] = odm_read_4byte(dm, R_0xdbc); /*@ End CFO*/
-+
-+	/*@[path-A]*/
-+	if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
-+		val_tmp = (val[0] & 0x0fff0000) >> 16; /*@ Short CFO, S(12,11)*/
-+		cfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
-+		val_tmp = (val[1] & 0x0fff0000) >> 16;	/*@ Long CFO, S(12,11)*/
-+		cfo->cfo_rpt_l[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
-+		val_tmp = (val[2] & 0x0fff0000) >> 16;	/*@ Sec CFO, S(12,11)*/
-+		cfo->cfo_rpt_sec[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
-+		val_tmp = (val[3] & 0x0fff0000) >> 16;	/*@ Acq CFO, S(12,11)*/
-+		cfo->cfo_rpt_acq[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
-+		val_tmp = (val[4] & 0x0fff0000) >> 16;	/*@ Acq CFO, S(12,11)*/
-+		cfo->cfo_rpt_end[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
-+	} else {
-+		val_tmp = (val[0] & 0x0fff0000) >> 16; /*@ Short CFO, S(12,11)*/
-+		cfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
-+		val_tmp = (val[1] & 0x1fff0000) >> 16;	/*@ Long CFO, S(13,12)*/
-+		cfo->cfo_rpt_l[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
-+		val_tmp = (val[2] & 0x7ff0000) >> 16;	/*@ Sec CFO, S(11,10)*/
-+		cfo->cfo_rpt_sec[0] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
-+		val_tmp = (val[3] & 0x1fff0000) >> 16;	/*@ Acq CFO, S(13,12)*/
-+		cfo->cfo_rpt_acq[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
-+		val_tmp = (val[4] & 0x1fff0000) >> 16;	/*@ Acq CFO, S(13,12)*/
-+		cfo->cfo_rpt_end[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
-+	}
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	/*@[path-B]*/
-+	val_tmp = val[0] & 0xfff;		/*@ Short CFO, S(12,11)*/
-+	cfo->cfo_rpt_s[1] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
-+	val_tmp = val[1] & 0x1fff;		/*@ Long CFO, S(13,12)*/
-+	cfo->cfo_rpt_l[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
-+	val_tmp = val[2] & 0x7ff;		/*@ Sec CFO, S(11,10)*/
-+	cfo->cfo_rpt_sec[1] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
-+	val_tmp = val[3] & 0x1fff;		/*@ Acq CFO, S(13,12)*/
-+	cfo->cfo_rpt_acq[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
-+	val_tmp = val[4] & 0x1fff;		/*@ Acq CFO, S(13,12)*/
-+	cfo->cfo_rpt_end[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
-+	#endif
-+}
-+
-+void phydm_set_atc_status(void *dm_void, boolean atc_status)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
-+	u32 reg_tmp = 0;
-+	u32 mask_tmp = 0;
-+
-+	PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]ATC_en=%d\n", __func__, atc_status);
-+
-+	if (cfo_track->is_atc_status == atc_status)
-+		return;
-+
-+	reg_tmp = ODM_REG(BB_ATC, dm);
-+	mask_tmp = ODM_BIT(BB_ATC, dm);
-+	odm_set_bb_reg(dm, reg_tmp, mask_tmp, atc_status);
-+	cfo_track->is_atc_status = atc_status;
-+}
-+
-+boolean
-+phydm_get_atc_status(void *dm_void)
-+{
-+	boolean atc_status = false;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 reg_tmp = 0;
-+	u32 mask_tmp = 0;
-+
-+	reg_tmp = ODM_REG(BB_ATC, dm);
-+	mask_tmp = ODM_BIT(BB_ATC, dm);
-+
-+	atc_status = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
-+
-+	PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]atc_status=%d\n", __func__, atc_status);
-+	return atc_status;
-+}
-+#endif
-+
-+void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	switch (dm->ic_ip_series) {
-+	#if (ODM_IC_11N_SERIES_SUPPORT)
-+	case PHYDM_IC_N:
-+		phydm_get_cfo_info_n(dm, cfo);
-+		break;
-+	#endif
-+	#if (ODM_IC_11AC_SERIES_SUPPORT)
-+	case PHYDM_IC_AC:
-+		phydm_get_cfo_info_ac(dm, cfo);
-+		break;
-+	#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+boolean
-+phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
-+	u32 reg_val = 0;
-+
-+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
-+	    ODM_RTL8195B | ODM_RTL8812F | ODM_RTL8721D | ODM_RTL8710C|ODM_RTL8723F)) {
-+		crystal_cap &= 0x7F;
-+		reg_val = crystal_cap | (crystal_cap << 7);
-+	} else {
-+		crystal_cap &= 0x3F;
-+		reg_val = crystal_cap | (crystal_cap << 6);
-+	}
-+
-+	cfo_track->crystal_cap = crystal_cap;
-+
-+	if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) {
-+		#if (RTL8188E_SUPPORT || RTL8188F_SUPPORT)
-+		/* write 0x24[22:17] = 0x24[16:11] = crystal_cap */
-+		odm_set_mac_reg(dm, R_0x24, 0x7ff800, reg_val);
-+		#endif
-+	}
-+	#if (RTL8812A_SUPPORT)
-+	else if (dm->support_ic_type & ODM_RTL8812) {
-+		/* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */
-+		odm_set_mac_reg(dm, R_0x2c, 0x7FF80000, reg_val);
-+	}
-+	#endif
-+	#if (RTL8703B_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\
-+	     RTL8821A_SUPPORT || RTL8723D_SUPPORT)
-+	else if ((dm->support_ic_type &
-+		 (ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 |
-+		 ODM_RTL8723D))) {
-+		/* @0x2C[23:18] = 0x2C[17:12] = crystal_cap */
-+		odm_set_mac_reg(dm, R_0x2c, 0x00FFF000, reg_val);
-+	}
-+	#endif
-+	#if (RTL8814A_SUPPORT)
-+	else if (dm->support_ic_type & ODM_RTL8814A) {
-+		/* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */
-+		odm_set_mac_reg(dm, R_0x2c, 0x07FF8000, reg_val);
-+	}
-+	#endif
-+	#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8197F_SUPPORT ||\
-+	     RTL8192F_SUPPORT || RTL8197G_SUPPORT || RTL8198F_SUPPORT)
-+	else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C |
-+		 ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8197G | ODM_RTL8198F)) {
-+		/* write 0x24[30:25] = 0x28[6:1] = crystal_cap */
-+		odm_set_mac_reg(dm, R_0x24, 0x7e000000, crystal_cap);
-+		odm_set_mac_reg(dm, R_0x28, 0x7e, crystal_cap);
-+	}
-+	#endif
-+	#if (RTL8710B_SUPPORT)
-+	else if (dm->support_ic_type & (ODM_RTL8710B)) {
-+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+		/* write 0x60[29:24] = 0x60[23:18] = crystal_cap */
-+		HAL_SetSYSOnReg(dm->adapter, R_0x60, 0x3FFC0000, reg_val);
-+		#endif
-+	}
-+	#endif
-+	#if (RTL8195B_SUPPORT)
-+	else if (dm->support_ic_type & ODM_RTL8195B) {
-+		phydm_set_crystalcap(dm, (u8)(reg_val & 0x7f));
-+	}
-+	#endif
-+	#if (RTL8721D_SUPPORT)
-+	else if (dm->support_ic_type & (ODM_RTL8721D)) {
-+		/* write 0x4800_0228[30:24] crystal_cap */
-+		/*HAL_SetSYSOnReg(dm->adapter, */
-+		/*REG_SYS_XTAL_8721d, 0x7F000000, crystal_cap);*/
-+		u32 temp_val = HAL_READ32(SYSTEM_CTRL_BASE_LP,
-+					   REG_SYS_EFUSE_SYSCFG2);
-+		temp_val = ((crystal_cap << 24) & 0x7F000000)
-+						| (temp_val & (~0x7F000000));
-+		HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_SYS_EFUSE_SYSCFG2,
-+			    temp_val);
-+	}
-+	#endif
-+	#if (RTL8710C_SUPPORT)
-+	else if (dm->support_ic_type & (ODM_RTL8710C)) {
-+		/* write MAC reg 0x28[13:7][6:0] crystal_cap */
-+		phydm_set_crystalcap(dm, (u8)(reg_val & 0x7f));
-+	}
-+	#endif
-+	#if (RTL8723F_SUPPORT)
-+	else if (dm->support_ic_type & ODM_RTL8723F) {
-+		/* write 0x103c[23:17] = 0x103c[16:10] = crystal_cap */
-+		odm_set_mac_reg(dm, R_0x103c, 0x00FFFC00, reg_val);
-+	}
-+	#endif
-+#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
-+	else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
-+		 ODM_RTL8812F)) {
-+		/* write 0x1040[23:17] = 0x1040[16:10] = crystal_cap */
-+		odm_set_mac_reg(dm, R_0x1040, 0x00FFFC00, reg_val);
-+	} else {
-+		return false;
-+	}
-+#endif
-+	return true;
-+}
-+
-+void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
-+
-+	if (cfo_track->crystal_cap == crystal_cap)
-+		return;
-+
-+	if (phydm_set_crystal_cap_reg(dm, crystal_cap))
-+		PHYDM_DBG(dm, DBG_CFO_TRK, "Set crystal_cap = 0x%x\n",
-+			  cfo_track->crystal_cap);
-+	else
-+		PHYDM_DBG(dm, DBG_CFO_TRK, "Set fail\n");
-+}
-+
-+void phydm_cfo_tracking_reset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
-+
-+	PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__);
-+
-+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8195B |
-+	    ODM_RTL8812F|ODM_RTL8723F))
-+		cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x7f;
-+	else
-+		cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x3f;
-+
-+	cfo_track->is_adjust = true;
-+
-+	if (cfo_track->crystal_cap > cfo_track->def_x_cap) {
-+		phydm_set_crystal_cap(dm, cfo_track->crystal_cap - 1);
-+		PHYDM_DBG(dm, DBG_CFO_TRK, "approch to Init-val (0x%x)\n",
-+			  cfo_track->crystal_cap);
-+
-+	} else if (cfo_track->crystal_cap < cfo_track->def_x_cap) {
-+		phydm_set_crystal_cap(dm, cfo_track->crystal_cap + 1);
-+		PHYDM_DBG(dm, DBG_CFO_TRK, "approch to init-val 0x%x\n",
-+			  cfo_track->crystal_cap);
-+	}
-+
-+#if ODM_IC_11N_SERIES_SUPPORT
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES)
-+		phydm_set_atc_status(dm, true);
-+#endif
-+#endif
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_AP))
-+	if (dm->support_ic_type & ODM_RTL8814B) {
-+		/*Disable advance time for CFO residual*/
-+		odm_set_bb_reg(dm, R_0xc2c, BIT29, 0x0);
-+	}
-+#endif
-+#endif
-+}
-+
-+void phydm_cfo_tracking_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
-+
-+	PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]=========>\n", __func__);
-+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8195B |
-+	    ODM_RTL8812F|ODM_RTL8723F))
-+		cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x7f;
-+	else
-+		cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x3f;
-+
-+	cfo_track->def_x_cap = cfo_track->crystal_cap;
-+	cfo_track->is_adjust = true;
-+	PHYDM_DBG(dm, DBG_CFO_TRK, "crystal_cap=0x%x\n", cfo_track->def_x_cap);
-+
-+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
-+	/* @Crystal cap. control by WiFi */
-+	if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))
-+		odm_set_mac_reg(dm, R_0x10, 0x40, 0x1);
-+#endif
-+}
-+
-+void phydm_cfo_tracking(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
-+	s32 cfo_avg = 0, cfo_path_sum = 0, cfo_abs = 0;
-+	u32 cfo_rpt_sum = 0, cfo_khz_avg[4] = {0};
-+	s8 crystal_cap = cfo_track->crystal_cap;
-+	u8 i = 0, valid_path_cnt = 0;
-+
-+	if (!(dm->support_ability & ODM_BB_CFO_TRACKING))
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__);
-+
-+	if (!dm->is_linked || !dm->is_one_entry_only) {
-+		phydm_cfo_tracking_reset(dm);
-+		PHYDM_DBG(dm, DBG_CFO_TRK, "is_linked=%d, one_entry_only=%d\n",
-+			  dm->is_linked, dm->is_one_entry_only);
-+
-+	} else {
-+		/* No new packet */
-+		if (cfo_track->packet_count == cfo_track->packet_count_pre) {
-+			PHYDM_DBG(dm, DBG_CFO_TRK, "Pkt cnt doesn't change\n");
-+			return;
-+		}
-+		cfo_track->packet_count_pre = cfo_track->packet_count;
-+
-+		/*@Calculate CFO */
-+		for (i = 0; i < dm->num_rf_path; i++) {
-+			if (!(dm->rx_ant_status & BIT(i)))
-+				continue;
-+
-+			valid_path_cnt++;
-+
-+			if (cfo_track->CFO_tail[i] < 0)
-+				cfo_abs = 0 - cfo_track->CFO_tail[i];
-+			else
-+				cfo_abs = cfo_track->CFO_tail[i];
-+
-+			cfo_rpt_sum = (u32)CFO_HW_RPT_2_KHZ(cfo_abs);
-+			cfo_khz_avg[i] = PHYDM_DIV(cfo_rpt_sum,
-+						   cfo_track->CFO_cnt[i]);
-+
-+			PHYDM_DBG(dm, DBG_CFO_TRK,
-+				  "[Path-%d] CFO_sum=((%d)), cnt=((%d)), CFO_avg=((%s%d))kHz\n",
-+				  i, cfo_rpt_sum, cfo_track->CFO_cnt[i],
-+				  ((cfo_track->CFO_tail[i] < 0) ? "-" : " "),
-+				  cfo_khz_avg[i]);
-+
-+			if (cfo_track->CFO_tail[i] < 0)
-+				cfo_path_sum += (0 - (s32)cfo_khz_avg[i]);
-+			else
-+				cfo_path_sum += (s32)cfo_khz_avg[i];
-+		}
-+
-+		if (valid_path_cnt >= 2)
-+			cfo_avg = cfo_path_sum / valid_path_cnt;
-+		else
-+			cfo_avg = cfo_path_sum;
-+
-+		cfo_track->CFO_ave_pre = cfo_avg;
-+
-+		PHYDM_DBG(dm, DBG_CFO_TRK, "path_cnt=%d, CFO_avg_path=%d kHz\n",
-+			  valid_path_cnt, cfo_avg);
-+
-+		/*reset counter*/
-+		for (i = 0; i < dm->num_rf_path; i++) {
-+			cfo_track->CFO_tail[i] = 0;
-+			cfo_track->CFO_cnt[i] = 0;
-+		}
-+
-+		/* To adjust crystal cap or not */
-+		if (!cfo_track->is_adjust) {
-+			if (cfo_avg > CFO_TRK_ENABLE_TH ||
-+			    cfo_avg < (-CFO_TRK_ENABLE_TH))
-+				cfo_track->is_adjust = true;
-+		} else {
-+			if (cfo_avg <= CFO_TRK_STOP_TH &&
-+			    cfo_avg >= (-CFO_TRK_STOP_TH))
-+				cfo_track->is_adjust = false;
-+		}
-+
-+		#ifdef ODM_CONFIG_BT_COEXIST
-+		/*@BT case: Disable CFO tracking */
-+		if (dm->bt_info_table.is_bt_enabled) {
-+			cfo_track->is_adjust = false;
-+			phydm_set_crystal_cap(dm, cfo_track->def_x_cap);
-+			PHYDM_DBG(dm, DBG_CFO_TRK, "[BT]Disable CFO_track\n");
-+		}
-+		#endif
-+
-+		/*@Adjust Crystal Cap. */
-+		if (cfo_track->is_adjust) {
-+			if (cfo_avg > CFO_TRK_STOP_TH)
-+				crystal_cap += 1;
-+			else if (cfo_avg < (-CFO_TRK_STOP_TH))
-+				crystal_cap -= 1;
-+
-+			if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
-+			    ODM_RTL8195B | ODM_RTL8812F|ODM_RTL8723F)) {
-+				if (crystal_cap > 0x7F)
-+					crystal_cap = 0x7F;
-+			} else {
-+				if (crystal_cap > 0x3F)
-+					crystal_cap = 0x3F;
-+			}
-+			if (crystal_cap < 0)
-+				crystal_cap = 0;
-+
-+			phydm_set_crystal_cap(dm, (u8)crystal_cap);
-+		}
-+
-+		PHYDM_DBG(dm, DBG_CFO_TRK, "X_cap{Curr,Default}={0x%x,0x%x}\n",
-+			  cfo_track->crystal_cap, cfo_track->def_x_cap);
-+
-+		/* @Dynamic ATC switch */
-+		#if ODM_IC_11N_SERIES_SUPPORT
-+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+		if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+			if (cfo_avg < CFO_TH_ATC && cfo_avg > -CFO_TH_ATC)
-+				phydm_set_atc_status(dm, false);
-+			else
-+				phydm_set_atc_status(dm, true);
-+
-+		}
-+		#endif
-+		#endif
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_AP))
-+		if (dm->support_ic_type & ODM_RTL8814B) {
-+			//Disable advance time for CFO residual
-+			odm_set_bb_reg(dm, R_0xc2c, BIT29, 0x0);
-+		}
-+		#endif
-+		#endif
-+	}
-+}
-+
-+void phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,
-+		       u8 num_ss)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_perpkt_info_struct *pktinfo = NULL;
-+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
-+	boolean valid_info = false;
-+	u8 i = 0;
-+
-+	if (!(dm->support_ability & ODM_BB_CFO_TRACKING))
-+		return;
-+
-+	pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void;
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
-+	if (pktinfo->is_packet_match_bssid)
-+		valid_info = true;
-+#else
-+	if (dm->number_active_client == 1)
-+		valid_info = true;
-+#endif
-+	if (valid_info) {
-+		if (num_ss > dm->num_rf_path) /*@For fool proof*/
-+			num_ss = dm->num_rf_path;
-+		#if 0
-+		PHYDM_DBG(dm, DBG_CFO_TRK, "num_ss=%d, num_rf_path=%d\n",
-+			  num_ss, dm->num_rf_path);
-+		#endif
-+
-+		/* @ Update CFO report for path-A & path-B */
-+		/* Only paht-A and path-B have CFO tail and short CFO */
-+		for (i = 0; i < dm->num_rf_path; i++) {
-+			if (!(dm->rx_ant_status & BIT(i)))
-+				continue;
-+			cfo_track->CFO_tail[i] += pcfotail[i];
-+			cfo_track->CFO_cnt[i]++;
-+			#if 0
-+			PHYDM_DBG(dm, DBG_CFO_TRK,
-+				  "[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n",
-+				  pktinfo->station_id, i, pktinfo->data_rate,
-+				  pcfotail[i], cfo_track->CFO_tail[i],
-+				  cfo_track->CFO_cnt[i]);
-+			#endif
-+		}
-+
-+		/* @ Update packet counter */
-+		if (cfo_track->packet_count == 0xffffffff)
-+			cfo_track->packet_count = 0;
-+		else
-+			cfo_track->packet_count++;
-+	}
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void phy_Init_crystal_capacity(void *dm_void, u8 crystal_cap)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!phydm_set_crystal_cap_reg(dm, crystal_cap))
-+		RT_TRACE_F(COMP_INIT, DBG_SERIOUS,
-+			   ("Crystal is not initialized!\n"));
-+}
-+#endif
-+
-+void phydm_cfo_tracking_debug(void *dm_void, char input[][16], u32 *_used,
-+			      char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "set Xcap: {1}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "show Xcap: {100}\n");
-+	} else {
-+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+
-+		if (var1[0] == 1) {
-+			PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
-+			phydm_set_crystal_cap(dm, (u8)var1[1]);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Set X_cap=0x%x\n", cfo_track->crystal_cap);
-+		} else if (var1[0] == 100) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "X_cap=0x%x\n", cfo_track->crystal_cap);
-+		}
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_cfotracking.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_cfotracking.h
-new file mode 100644
-index 000000000000..253f3ba3eabe
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_cfotracking.h
-@@ -0,0 +1,74 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDMCFOTRACK_H__
-+#define __PHYDMCFOTRACK_H__
-+
-+/* 2019.03.28 fix 8197G crystal_cap register address*/
-+#define CFO_TRACKING_VERSION "2.4"
-+
-+#define		CFO_TRK_ENABLE_TH	20 /* @kHz enable CFO_Track threshold*/
-+#define		CFO_TRK_STOP_TH		10 /* @kHz disable CFO_Track threshold*/
-+#define		CFO_TH_ATC		80 /* @kHz */
-+
-+struct phydm_cfo_track_struct {
-+	boolean		is_atc_status;
-+	boolean		is_adjust;	/*@already modify crystal cap*/
-+	u8		crystal_cap;
-+	u8		crystal_cap_default;
-+	u8		def_x_cap;
-+	s32		CFO_tail[4];
-+	u32		CFO_cnt[4];
-+	s32		CFO_ave_pre;
-+	u32		packet_count;
-+	u32		packet_count_pre;
-+};
-+
-+struct phydm_cfo_rpt {
-+	s32 cfo_rpt_s[PHYDM_MAX_RF_PATH];
-+	s32 cfo_rpt_l[PHYDM_MAX_RF_PATH];
-+	s32 cfo_rpt_acq[PHYDM_MAX_RF_PATH];
-+	s32 cfo_rpt_sec[PHYDM_MAX_RF_PATH];
-+	s32 cfo_rpt_end[PHYDM_MAX_RF_PATH];
-+};
-+
-+void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo);
-+
-+boolean phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap);
-+
-+void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap);
-+
-+void phydm_cfo_tracking_init(void *dm_void);
-+
-+void phydm_cfo_tracking(void *dm_void);
-+
-+void phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,
-+		       u8 num_ss);
-+void phydm_cfo_tracking_debug(void *dm_void, char input[][16], u32 *_used,
-+			      char *output, u32 *_out_len);
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void phy_Init_crystal_capacity(void *dm_void, u8 crystal_cap);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_debug.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_debug.c
-new file mode 100644
-index 000000000000..5b28ca28b22c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_debug.c
-@@ -0,0 +1,6156 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+void phydm_init_debug_setting(struct dm_struct *dm)
-+{
-+	dm->fw_debug_components = 0;
-+	dm->debug_components =
-+
-+#if DBG
-+	/*@BB Functions*/
-+	/*@DBG_DIG					|*/
-+	/*@DBG_RA_MASK					|*/
-+	/*@DBG_DYN_TXPWR				|*/
-+	/*@DBG_FA_CNT					|*/
-+	/*@DBG_RSSI_MNTR				|*/
-+	/*@DBG_CCKPD					|*/
-+	/*@DBG_ANT_DIV					|*/
-+	/*@DBG_SMT_ANT					|*/
-+	/*@DBG_PWR_TRAIN				|*/
-+	/*@DBG_RA					|*/
-+	/*@DBG_PATH_DIV					|*/
-+	/*@DBG_DFS					|*/
-+	/*@DBG_DYN_ARFR					|*/
-+	/*@DBG_ADPTVTY					|*/
-+	/*@DBG_CFO_TRK					|*/
-+	/*@DBG_ENV_MNTR					|*/
-+	/*@DBG_PRI_CCA					|*/
-+	/*@DBG_ADPTV_SOML				|*/
-+	/*@DBG_LNA_SAT_CHK				|*/
-+	/*@DBG_PHY_STATUS				|*/
-+	/*@DBG_TMP					|*/
-+	/*@DBG_FW_TRACE					|*/
-+	/*@DBG_TXBF					|*/
-+	/*@DBG_COMMON_FLOW				|*/
-+	/*@ODM_PHY_CONFIG				|*/
-+	/*@ODM_COMP_INIT				|*/
-+	/*@DBG_CMN					|*/
-+	/*@ODM_COMP_API					|*/
-+#endif
-+	0;
-+
-+	dm->fw_buff_is_enpty = true;
-+	dm->pre_c2h_seq = 0;
-+	dm->c2h_cmd_start = 0;
-+	dm->cmn_dbg_msg_cnt = PHYDM_WATCH_DOG_PERIOD;
-+	dm->cmn_dbg_msg_period = PHYDM_WATCH_DOG_PERIOD;
-+	phydm_reset_rx_rate_distribution(dm);
-+}
-+
-+void phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		odm_set_bb_reg(dm, R_0x8f8, 0x3c00000, header_idx);
-+
-+		/*@
-+		 * header_idx:
-+		 *	(0:) '{ofdm_dbg[31:0]}'
-+		 *	(1:) '{cca,crc32_fail,dbg_ofdm[29:0]}'
-+		 *	(2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}'
-+		 *	(3:) '{cca,crc32_ok,dbg_ofdm[29:0]}'
-+		 *	(4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}'
-+		 *	(5:) '{dbg_iqk_anta}'
-+		 *	(6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}'
-+		 *	(7:) '{dbg_iqk_antb}'
-+		 *	(8:) '{DBGOUT_RFC_b[31:0]}'
-+		 *	(9:) '{DBGOUT_RFC_a[31:0]}'
-+		 *	(a:) '{dbg_ofdm}'
-+		 *	(b:) '{dbg_cck}'
-+		 */
-+	}
-+}
-+
-+void phydm_bb_dbg_port_clock_en(void *dm_void, u8 enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 reg_value = 0;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) {
-+		/*@enable/disable debug port clock, for power saving*/
-+		reg_value = enable ? 0x7 : 0;
-+		odm_set_bb_reg(dm, R_0x198c, 0x7, reg_value);
-+	}
-+}
-+
-+u32 phydm_get_bb_dbg_port_idx(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 val = 0;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		phydm_bb_dbg_port_clock_en(dm, true);
-+		val = odm_get_bb_reg(dm, R_0x8fc, MASKDWORD);
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		val = odm_get_bb_reg(dm, R_0x1c3c, 0xfff00);
-+	} else { /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/
-+		val = odm_get_bb_reg(dm, R_0x908, MASKDWORD);
-+	}
-+	return val;
-+}
-+
-+u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 dbg_port_result = false;
-+
-+	if (curr_dbg_priority > dm->pre_dbg_priority) {
-+		if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+			phydm_bb_dbg_port_clock_en(dm, true);
-+
-+			odm_set_bb_reg(dm, R_0x8fc, MASKDWORD, debug_port);
-+		} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+			odm_set_bb_reg(dm, R_0x1c3c, 0xfff00, debug_port);
-+		} else { /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/
-+			odm_set_bb_reg(dm, R_0x908, MASKDWORD, debug_port);
-+		}
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "DbgPort ((0x%x)) set success, Cur_priority=((%d)), Pre_priority=((%d))\n",
-+			  debug_port, curr_dbg_priority, dm->pre_dbg_priority);
-+		dm->pre_dbg_priority = curr_dbg_priority;
-+		dbg_port_result = true;
-+	}
-+
-+	return dbg_port_result;
-+}
-+
-+void phydm_release_bb_dbg_port(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	phydm_bb_dbg_port_clock_en(dm, false);
-+	phydm_bb_dbg_port_header_sel(dm, 0);
-+
-+	dm->pre_dbg_priority = DBGPORT_RELEASE;
-+	PHYDM_DBG(dm, ODM_COMP_API, "Release BB dbg_port\n");
-+}
-+
-+u32 phydm_get_bb_dbg_port_val(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 dbg_port_value = 0;
-+
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-+		dbg_port_value = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD);
-+	else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		dbg_port_value = odm_get_bb_reg(dm, R_0x2dbc, MASKDWORD);
-+	else /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/
-+		dbg_port_value = odm_get_bb_reg(dm, R_0xdf4, MASKDWORD);
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "dbg_port_value = 0x%x\n", dbg_port_value);
-+	return dbg_port_value;
-+}
-+
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+#if (ODM_IC_11N_SERIES_SUPPORT)
-+void phydm_bb_hw_dbg_info_n(void *dm_void, u32 *_used, char *output,
-+			    u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 value32 = 0, value32_1 = 0;
-+	u8 rf_gain_a = 0, rf_gain_b = 0, rf_gain_c = 0, rf_gain_d = 0;
-+	u8 rx_snr_a = 0, rx_snr_b = 0, rx_snr_c = 0, rx_snr_d = 0;
-+	s8 rxevm_0 = 0, rxevm_1 = 0;
-+	#if 1
-+	struct phydm_cfo_rpt cfo;
-+	u8 i = 0;
-+	#else
-+	s32 short_cfo_a = 0, short_cfo_b = 0, long_cfo_a = 0, long_cfo_b = 0;
-+	s32 scfo_a = 0, scfo_b = 0, avg_cfo_a = 0, avg_cfo_b = 0;
-+	s32 cfo_end_a = 0, cfo_end_b = 0, acq_cfo_a = 0, acq_cfo_b = 0;
-+	#endif
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n",
-+		 "BB Report Info");
-+
-+	/*@AGC result*/
-+	value32 = odm_get_bb_reg(dm, R_0xdd0, MASKDWORD);
-+	rf_gain_a = (u8)(value32 & 0x3f);
-+	rf_gain_a = rf_gain_a << 1;
-+
-+	rf_gain_b = (u8)((value32 >> 8) & 0x3f);
-+	rf_gain_b = rf_gain_b << 1;
-+
-+	rf_gain_c = (u8)((value32 >> 16) & 0x3f);
-+	rf_gain_c = rf_gain_c << 1;
-+
-+	rf_gain_d = (u8)((value32 >> 24) & 0x3f);
-+	rf_gain_d = rf_gain_d << 1;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)",
-+		 rf_gain_a, rf_gain_b, rf_gain_c, rf_gain_d);
-+
-+	/*SNR report*/
-+	value32 = odm_get_bb_reg(dm, R_0xdd4, MASKDWORD);
-+	rx_snr_a = (u8)(value32 & 0xff);
-+	rx_snr_a = rx_snr_a >> 1;
-+
-+	rx_snr_b = (u8)((value32 >> 8) & 0xff);
-+	rx_snr_b = rx_snr_b >> 1;
-+
-+	rx_snr_c = (u8)((value32 >> 16) & 0xff);
-+	rx_snr_c = rx_snr_c >> 1;
-+
-+	rx_snr_d = (u8)((value32 >> 24) & 0xff);
-+	rx_snr_d = rx_snr_d >> 1;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)",
-+		 rx_snr_a, rx_snr_b, rx_snr_c, rx_snr_d);
-+
-+	/* PostFFT related info*/
-+	value32 = odm_get_bb_reg(dm, R_0xdd8, MASKDWORD);
-+
-+	rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16);
-+	rxevm_0 /= 2;
-+	if (rxevm_0 < -63)
-+		rxevm_0 = 0;
-+
-+	rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24);
-+	rxevm_1 /= 2;
-+	if (rxevm_1 < -63)
-+		rxevm_1 = 0;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d", "RXEVM (1ss/2ss)", rxevm_0, rxevm_1);
-+
-+#if 1
-+	phydm_get_cfo_info(dm, &cfo);
-+	for (i = 0; i < dm->num_rf_path; i++) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %s[%d] %-28s = {%d, %d, %d, %d, %d}",
-+			 "CFO", i, "{S, L, Sec, Acq, End}",
-+			 cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i], cfo.cfo_rpt_sec[i],
-+			 cfo.cfo_rpt_acq[i], cfo.cfo_rpt_end[i]);
-+	}
-+#else
-+	/*@CFO Report Info*/
-+	odm_set_bb_reg(dm, R_0xd00, BIT(26), 1);
-+
-+	/*Short CFO*/
-+	value32 = odm_get_bb_reg(dm, R_0xdac, MASKDWORD);
-+	value32_1 = odm_get_bb_reg(dm, R_0xdb0, MASKDWORD);
-+
-+	short_cfo_b = (s32)(value32 & 0xfff); /*S(12,11)*/
-+	short_cfo_a = (s32)((value32 & 0x0fff0000) >> 16);
-+
-+	long_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
-+	long_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
-+
-+	/*SFO 2's to dec*/
-+	if (short_cfo_a > 2047)
-+		short_cfo_a = short_cfo_a - 4096;
-+	if (short_cfo_b > 2047)
-+		short_cfo_b = short_cfo_b - 4096;
-+
-+	short_cfo_a = (short_cfo_a * 312500) / 2048;
-+	short_cfo_b = (short_cfo_b * 312500) / 2048;
-+
-+	/*@LFO 2's to dec*/
-+
-+	if (long_cfo_a > 4095)
-+		long_cfo_a = long_cfo_a - 8192;
-+
-+	if (long_cfo_b > 4095)
-+		long_cfo_b = long_cfo_b - 8192;
-+
-+	long_cfo_a = long_cfo_a * 312500 / 4096;
-+	long_cfo_b = long_cfo_b * 312500 / 4096;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s",
-+		 "CFO Report Info");
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d", "Short CFO(Hz) <A/B>", short_cfo_a,
-+		 short_cfo_b);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d", "Long CFO(Hz) <A/B>", long_cfo_a,
-+		 long_cfo_b);
-+
-+	/*SCFO*/
-+	value32 = odm_get_bb_reg(dm, R_0xdb8, MASKDWORD);
-+	value32_1 = odm_get_bb_reg(dm, R_0xdb4, MASKDWORD);
-+
-+	scfo_b = (s32)(value32 & 0x7ff); /*S(11,10)*/
-+	scfo_a = (s32)((value32 & 0x07ff0000) >> 16);
-+
-+	if (scfo_a > 1023)
-+		scfo_a = scfo_a - 2048;
-+
-+	if (scfo_b > 1023)
-+		scfo_b = scfo_b - 2048;
-+
-+	scfo_a = scfo_a * 312500 / 1024;
-+	scfo_b = scfo_b * 312500 / 1024;
-+
-+	avg_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
-+	avg_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
-+
-+	if (avg_cfo_a > 4095)
-+		avg_cfo_a = avg_cfo_a - 8192;
-+
-+	if (avg_cfo_b > 4095)
-+		avg_cfo_b = avg_cfo_b - 8192;
-+
-+	avg_cfo_a = avg_cfo_a * 312500 / 4096;
-+	avg_cfo_b = avg_cfo_b * 312500 / 4096;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d", "value SCFO(Hz) <A/B>", scfo_a,
-+		 scfo_b);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d", "Avg CFO(Hz) <A/B>", avg_cfo_a,
-+		 avg_cfo_b);
-+
-+	value32 = odm_get_bb_reg(dm, R_0xdbc, MASKDWORD);
-+	value32_1 = odm_get_bb_reg(dm, R_0xde0, MASKDWORD);
-+
-+	cfo_end_b = (s32)(value32 & 0x1fff); /*S(13,12)*/
-+	cfo_end_a = (s32)((value32 & 0x1fff0000) >> 16);
-+
-+	if (cfo_end_a > 4095)
-+		cfo_end_a = cfo_end_a - 8192;
-+
-+	if (cfo_end_b > 4095)
-+		cfo_end_b = cfo_end_b - 8192;
-+
-+	cfo_end_a = cfo_end_a * 312500 / 4096;
-+	cfo_end_b = cfo_end_b * 312500 / 4096;
-+
-+	acq_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/
-+	acq_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16);
-+
-+	if (acq_cfo_a > 4095)
-+		acq_cfo_a = acq_cfo_a - 8192;
-+
-+	if (acq_cfo_b > 4095)
-+		acq_cfo_b = acq_cfo_b - 8192;
-+
-+	acq_cfo_a = acq_cfo_a * 312500 / 4096;
-+	acq_cfo_b = acq_cfo_b * 312500 / 4096;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d", "End CFO(Hz) <A/B>", cfo_end_a,
-+		 cfo_end_b);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d", "ACQ CFO(Hz) <A/B>", acq_cfo_a,
-+		 acq_cfo_b);
-+#endif
-+}
-+#endif
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT)
-+#if (RTL8822B_SUPPORT)
-+void phydm_bb_hw_dbg_info_8822b(void *dm_void, u32 *_used, char *output,
-+				u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 condi_num = 0;
-+	u8 i = 0;
-+
-+	if (!(dm->support_ic_type == ODM_RTL8822B))
-+		return;
-+
-+	condi_num = phydm_get_condi_num_8822b(dm);
-+	phydm_get_condi_num_acc_8822b(dm);
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d.%.4d", "condi_num",
-+		 condi_num >> 4, phydm_show_fraction_num(condi_num & 0xf, 4));
-+
-+	for (i = 0; i < CN_CNT_MAX; i++) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n Tone_num[CN>%d]%-21s = %d",
-+			 i, " ", dm->phy_dbg_info.condi_num_cdf[i]);
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+#endif
-+
-+void phydm_bb_hw_dbg_info_ac(void *dm_void, u32 *_used, char *output,
-+			     u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	char *tmp_string = NULL;
-+	u8 rx_ht_bw, rx_vht_bw, rxsc, rx_ht, bw_idx = 0;
-+	static u8 v_rx_bw;
-+	u32 value32, value32_1, value32_2, value32_3;
-+	struct phydm_cfo_rpt cfo;
-+	u8 i = 0;
-+	static u8 tail, parity, rsv, vrsv, smooth, htsound, agg;
-+	static u8 stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts;
-+	static u8 vtxops, vrsv2, vbrsv, bf, vbcrc;
-+	static u16 h_length, htcrc8, length;
-+	static u16 vpaid;
-+	static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail;
-+	static u8 hmcss, hrx_bw;
-+	u8 pwdb;
-+	s8 rxevm_0, rxevm_1, rxevm_2;
-+	u8 rf_gain[4];
-+	u8 rx_snr[4];
-+	s32 sig_power;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n",
-+		 "BB Report Info");
-+
-+	/*@ [BW & Mode] =====================================================*/
-+
-+	value32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD);
-+	rx_ht = (u8)((value32 & 0x180) >> 7);
-+
-+	if (rx_ht == AD_VHT_MODE) {
-+		tmp_string = "VHT";
-+		bw_idx = (u8)((value32 >> 1) & 0x3);
-+	} else if (rx_ht == AD_HT_MODE) {
-+		tmp_string = "HT";
-+		bw_idx = (u8)(value32 & 0x1);
-+	} else {
-+		tmp_string = "Legacy";
-+		bw_idx = 0;
-+	}
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s %s %dM", "mode", tmp_string, (20 << bw_idx));
-+
-+	if (rx_ht != AD_LEGACY_MODE) {
-+		rxsc = (u8)(value32 & 0x78);
-+
-+		if (rxsc == 0)
-+			tmp_string = "duplicate/full bw";
-+		else if (rxsc == 1)
-+			tmp_string = "usc20-1";
-+		else if (rxsc == 2)
-+			tmp_string = "lsc20-1";
-+		else if (rxsc == 3)
-+			tmp_string = "usc20-2";
-+		else if (rxsc == 4)
-+			tmp_string = "lsc20-2";
-+		else if (rxsc == 9)
-+			tmp_string = "usc40";
-+		else if (rxsc == 10)
-+			tmp_string = "lsc40";
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "  %-35s", tmp_string);
-+	}
-+
-+	/*@ [RX signal power and AGC related info] ==========================*/
-+
-+	pwdb = (u8)odm_get_bb_reg(dm, R_0xf90, MASKBYTE1);
-+	sig_power = -110 + (pwdb >> 1);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d", "OFDM RX Signal Power(dB)", sig_power);
-+
-+	value32 = odm_get_bb_reg(dm, R_0xd14, MASKDWORD);
-+	rx_snr[RF_PATH_A] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/
-+	rf_gain[RF_PATH_A] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);
-+
-+	value32 = odm_get_bb_reg(dm, R_0xd54, MASKDWORD);
-+	rx_snr[RF_PATH_B] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/
-+	rf_gain[RF_PATH_B] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);
-+
-+	value32 = odm_get_bb_reg(dm, R_0xd94, MASKDWORD);
-+	rx_snr[RF_PATH_C] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/
-+	rf_gain[RF_PATH_C] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);
-+
-+	value32 = odm_get_bb_reg(dm, R_0xdd4, MASKDWORD);
-+	rx_snr[RF_PATH_D] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/
-+	rf_gain[RF_PATH_D] = (s8)(((value32 & MASKBYTE1) >> 8) * 2);
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)",
-+		 rf_gain[RF_PATH_A], rf_gain[RF_PATH_B],
-+		 rf_gain[RF_PATH_C], rf_gain[RF_PATH_D]);
-+
-+	/*@ [RX counter Info] ===============================================*/
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d", "OFDM CCA cnt",
-+		 odm_get_bb_reg(dm, R_0xf08, 0xFFFF0000));
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d", "OFDM SBD Fail cnt",
-+		 odm_get_bb_reg(dm, R_0xfd0, 0xFFFF));
-+
-+	value32 = odm_get_bb_reg(dm, R_0xfc4, MASKDWORD);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail cnt",
-+		 value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16));
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d", "CCK CCA cnt",
-+		 odm_get_bb_reg(dm, R_0xfcc, 0xFFFF));
-+
-+	value32 = odm_get_bb_reg(dm, R_0xfbc, MASKDWORD);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d",
-+		 "LSIG (parity Fail/rate Illegal) cnt", value32 & 0xFFFF,
-+		 ((value32 & 0xFFFF0000) >> 16));
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT cnt",
-+		 odm_get_bb_reg(dm, R_0xfc0, (0xFFFF0000 >> 16)),
-+		 odm_get_bb_reg(dm, R_0xfc8, 0xFFFF));
-+
-+	/*@ [PostFFT Info] =================================================*/
-+	value32 = odm_get_bb_reg(dm, R_0xf8c, MASKDWORD);
-+	rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16);
-+	rxevm_0 /= 2;
-+	if (rxevm_0 < -63)
-+		rxevm_0 = 0;
-+
-+	rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24);
-+	rxevm_1 /= 2;
-+	value32 = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);
-+	rxevm_2 = (s8)((value32 & MASKBYTE2) >> 16);
-+	rxevm_2 /= 2;
-+
-+	if (rxevm_1 < -63)
-+		rxevm_1 = 0;
-+	if (rxevm_2 < -63)
-+		rxevm_2 = 0;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)", rxevm_0,
-+		 rxevm_1, rxevm_2);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D dB)",
-+		 rx_snr[RF_PATH_A], rx_snr[RF_PATH_B],
-+		 rx_snr[RF_PATH_C], rx_snr[RF_PATH_D]);
-+
-+	value32 = odm_get_bb_reg(dm, R_0xf8c, MASKDWORD);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d", "CSI_1st /CSI_2nd", value32 & 0xFFFF,
-+		 ((value32 & 0xFFFF0000) >> 16));
-+
-+	/*@ [CFO Report Info] ===============================================*/
-+	phydm_get_cfo_info(dm, &cfo);
-+	for (i = 0; i < dm->num_rf_path; i++) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %s[%d] %-28s = {%d, %d, %d, %d, %d}",
-+			 "CFO", i, "{S, L, Sec, Acq, End}",
-+			 cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i], cfo.cfo_rpt_sec[i],
-+			 cfo.cfo_rpt_acq[i], cfo.cfo_rpt_end[i]);
-+	}
-+
-+	/*@ [L-SIG Content] =================================================*/
-+	value32 = odm_get_bb_reg(dm, R_0xf20, MASKDWORD);
-+
-+	tail = (u8)((value32 & 0xfc0000) >> 18);/*@[23:18]*/
-+	parity = (u8)((value32 & 0x20000) >> 17);/*@[17]*/
-+	length = (u16)((value32 & 0x1ffe0) >> 5);/*@[16:5]*/
-+	rsv = (u8)((value32 & 0x10) >> 4);/*@[4]*/
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s",
-+		 "L-SIG");
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d M", "rate",
-+		 phydm_get_l_sig_rate(dm, (u8)(value32 & 0x0f)));
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %x / %d / %d", "Rsv/length/parity", rsv, length,
-+		 parity);
-+
-+	if (rx_ht == AD_HT_MODE) {
-+	/*@ [HT SIG 1] ======================================================*/
-+		value32 = odm_get_bb_reg(dm, R_0xf2c, MASKDWORD);
-+
-+		hmcss = (u8)(value32 & 0x7F);
-+		hrx_bw = (u8)((value32 & 0x80) >> 7);
-+		h_length = (u16)((value32 & 0x0fff00) >> 8);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s", "HT-SIG1");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %d / %d / %d", "MCS/BW/length",
-+			 hmcss, hrx_bw, h_length);
-+	/*@ [HT SIG 2] ======================================================*/
-+		value32 = odm_get_bb_reg(dm, R_0xf30, MASKDWORD);
-+		smooth = (u8)(value32 & 0x01);
-+		htsound = (u8)((value32 & 0x02) >> 1);
-+		rsv = (u8)((value32 & 0x04) >> 2);
-+		agg = (u8)((value32 & 0x08) >> 3);
-+		stbc = (u8)((value32 & 0x30) >> 4);
-+		fec = (u8)((value32 & 0x40) >> 6);
-+		sgi = (u8)((value32 & 0x80) >> 7);
-+		htltf = (u8)((value32 & 0x300) >> 8);
-+		htcrc8 = (u16)((value32 & 0x3fc00) >> 10);
-+		tail = (u8)((value32 & 0xfc0000) >> 18);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s",
-+			 "HT-SIG2");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %x / %x / %x / %x / %x / %x",
-+			 "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC",
-+			 smooth, htsound, rsv, agg, stbc, fec);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %x / %x / %x / %x",
-+			 "SGI/E-HT-LTFs/CRC/tail",
-+			 sgi, htltf, htcrc8, tail);
-+	} else if (rx_ht == AD_VHT_MODE) {
-+	/*@ [VHT SIG A1] ====================================================*/
-+		value32 = odm_get_bb_reg(dm, R_0xf2c, MASKDWORD);
-+
-+		v_rx_bw = (u8)(value32 & 0x03);
-+		vrsv = (u8)((value32 & 0x04) >> 2);
-+		vstbc = (u8)((value32 & 0x08) >> 3);
-+		vgid = (u8)((value32 & 0x3f0) >> 4);
-+		v_nsts = (u8)(((value32 & 0x1c00) >> 10) + 1);
-+		vpaid = (u16)((value32 & 0x3fe000) >> 13);
-+		vtxops = (u8)((value32 & 0x400000) >> 22);
-+		vrsv2 = (u8)((value32 & 0x800000) >> 23);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s",
-+			 "VHT-SIG-A1");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x",
-+			 "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw,
-+			 vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2);
-+
-+	/*@ [VHT SIG A2] ====================================================*/
-+		value32 = odm_get_bb_reg(dm, R_0xf30, MASKDWORD);
-+
-+		/* @sgi=(u8)(value32&0x01); */
-+		sgiext = (u8)(value32 & 0x03);
-+		/* @fec = (u8)(value32&0x04); */
-+		fecext = (u8)((value32 & 0x0C) >> 2);
-+
-+		v_mcss = (u8)((value32 & 0xf0) >> 4);
-+		bf = (u8)((value32 & 0x100) >> 8);
-+		vrsv = (u8)((value32 & 0x200) >> 9);
-+		vhtcrc8 = (u16)((value32 & 0x3fc00) >> 10);
-+		v_tail = (u8)((value32 & 0xfc0000) >> 18);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s", "VHT-SIG-A2");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x",
-+			 "SGI/FEC/MCS/BF/Rsv/CRC/tail",
-+			 sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail);
-+
-+	/*@ [VHT SIG B] ====================================================*/
-+		value32 = odm_get_bb_reg(dm, R_0xf34, MASKDWORD);
-+
-+		#if 0
-+		v_length = (u16)(value32 & 0x1fffff);
-+		vbrsv = (u8)((value32 & 0x600000) >> 21);
-+		vb_tail = (u16)((value32 & 0x1f800000) >> 23);
-+		vbcrc = (u8)((value32 & 0x80000000) >> 31);
-+		#endif
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s", "VHT-SIG-B");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %x",
-+			 "Codeword", value32);
-+
-+		#if 0
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %x / %x / %x / %x",
-+			 "length/Rsv/tail/CRC",
-+			 v_length, vbrsv, vb_tail, vbcrc);
-+		#endif
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+#endif
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+void phydm_bb_hw_dbg_info_jgr3(void *dm_void, u32 *_used, char *output,
-+			       u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	char *tmp_string = NULL;
-+	u8 rx_ht_bw = 0, rx_vht_bw = 0, rx_ht = 0;
-+	static u8 v_rx_bw;
-+	u32 value32 = 0;
-+	u8 i = 0;
-+	static u8 tail, parity, rsv, vrsv, smooth, htsound, agg;
-+	static u8 stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts;
-+	static u8 vtxops, vrsv2, vbrsv, bf, vbcrc;
-+	static u16 h_length, htcrc8, length;
-+	static u16 vpaid;
-+	static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail;
-+	static u8 hmcss, hrx_bw;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n",
-+		 "BB Report Info");
-+
-+	/*@ [Mode] =====================================================*/
-+
-+	value32 = odm_get_bb_reg(dm, R_0x2c20, MASKDWORD);
-+	rx_ht = (u8)((value32 & 0xC0000) >> 18);
-+	if (rx_ht == AD_VHT_MODE)
-+		tmp_string = "VHT";
-+	else if (rx_ht == AD_HT_MODE)
-+		tmp_string = "HT";
-+	else
-+		tmp_string = "Legacy";
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s %s", "mode", tmp_string);
-+	/*@ [RX counter Info] ===============================================*/
-+
-+	if (dm->support_ic_type & ODM_RTL8723F) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %d", "CCK CCA cnt",
-+			 odm_get_bb_reg(dm, R_0x2aa0, 0xFFFF));
-+	} else {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %d", "CCK CCA cnt",
-+			 odm_get_bb_reg(dm, R_0x2c08, 0xFFFF));
-+	}
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d", "OFDM CCA cnt",
-+		 odm_get_bb_reg(dm, R_0x2c08, 0xFFFF0000));
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d", "OFDM SBD Fail cnt",
-+		 odm_get_bb_reg(dm, R_0x2d20, 0xFFFF0000));
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d",
-+		 "LSIG (parity Fail/rate Illegal) cnt",
-+		 odm_get_bb_reg(dm, R_0x2d04, 0xFFFF0000),
-+		 odm_get_bb_reg(dm, R_0x2d08, 0xFFFF));
-+
-+	value32 = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT cnt",
-+		 value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16));
-+
-+	value32 = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail cnt",
-+		 value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16));
-+	/*@ [L-SIG Content] =================================================*/
-+	value32 = odm_get_bb_reg(dm, R_0x2c20, MASKDWORD);
-+
-+	parity = (u8)((value32 & 0x20000) >> 17);/*@[17]*/
-+	length = (u16)((value32 & 0x1ffe0) >> 5);/*@[16:5]*/
-+	rsv = (u8)((value32 & 0x10) >> 4);/*@[4]*/
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s",
-+		 "L-SIG");
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %d M", "rate",
-+		 phydm_get_l_sig_rate(dm, (u8)(value32 & 0x0f)));
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\r\n %-35s = %x / %d / %d", "Rsv/length/parity", rsv, length,
-+		 parity);
-+
-+	if (rx_ht == AD_HT_MODE) {
-+	/*@ [HT SIG 1] ======================================================*/
-+		value32 = odm_get_bb_reg(dm, R_0x2c2c, MASKDWORD);
-+
-+		hmcss = (u8)(value32 & 0x7F);
-+		hrx_bw = (u8)((value32 & 0x80) >> 7);
-+		h_length = (u16)((value32 & 0x0fff00) >> 8);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s", "HT-SIG1");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %d / %d / %d", "MCS/BW/length",
-+			 hmcss, hrx_bw, h_length);
-+	/*@ [HT SIG 2] ======================================================*/
-+		value32 = odm_get_bb_reg(dm, R_0x2c30, MASKDWORD);
-+		smooth = (u8)(value32 & 0x01);
-+		htsound = (u8)((value32 & 0x02) >> 1);
-+		rsv = (u8)((value32 & 0x04) >> 2);
-+		agg = (u8)((value32 & 0x08) >> 3);
-+		stbc = (u8)((value32 & 0x30) >> 4);
-+		fec = (u8)((value32 & 0x40) >> 6);
-+		sgi = (u8)((value32 & 0x80) >> 7);
-+		htltf = (u8)((value32 & 0x300) >> 8);
-+		htcrc8 = (u16)((value32 & 0x3fc00) >> 10);
-+		tail = (u8)((value32 & 0xfc0000) >> 18);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s",
-+			 "HT-SIG2");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %x / %x / %x / %x / %x / %x",
-+			 "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC",
-+			 smooth, htsound, rsv, agg, stbc, fec);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %x / %x / %x / %x",
-+			 "SGI/E-HT-LTFs/CRC/tail",
-+			 sgi, htltf, htcrc8, tail);
-+	} else if (rx_ht == AD_VHT_MODE) {
-+	/*@ [VHT SIG A1] ====================================================*/
-+		value32 = odm_get_bb_reg(dm, R_0x2c2c, MASKDWORD);
-+
-+		v_rx_bw = (u8)(value32 & 0x03);
-+		vrsv = (u8)((value32 & 0x04) >> 2);
-+		vstbc = (u8)((value32 & 0x08) >> 3);
-+		vgid = (u8)((value32 & 0x3f0) >> 4);
-+		v_nsts = (u8)(((value32 & 0x1c00) >> 10) + 1);
-+		vpaid = (u16)((value32 & 0x3fe000) >> 13);
-+		vtxops = (u8)((value32 & 0x400000) >> 22);
-+		vrsv2 = (u8)((value32 & 0x800000) >> 23);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s",
-+			 "VHT-SIG-A1");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x",
-+			 "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw,
-+			 vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2);
-+
-+	/*@ [VHT SIG A2] ====================================================*/
-+		value32 = odm_get_bb_reg(dm, R_0x2c30, MASKDWORD);
-+
-+		/* @sgi=(u8)(value32&0x01); */
-+		sgiext = (u8)(value32 & 0x03);
-+		/* @fec = (u8)(value32&0x04); */
-+		fecext = (u8)((value32 & 0x0C) >> 2);
-+
-+		v_mcss = (u8)((value32 & 0xf0) >> 4);
-+		bf = (u8)((value32 & 0x100) >> 8);
-+		vrsv = (u8)((value32 & 0x200) >> 9);
-+		vhtcrc8 = (u16)((value32 & 0x3fc00) >> 10);
-+		v_tail = (u8)((value32 & 0xfc0000) >> 18);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s", "VHT-SIG-A2");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x",
-+			 "SGI/FEC/MCS/BF/Rsv/CRC/tail",
-+			 sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail);
-+
-+	/*@ [VHT SIG B] ====================================================*/
-+		value32 = odm_get_bb_reg(dm, R_0x2c34, MASKDWORD);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s", "VHT-SIG-B");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %x",
-+			 "Codeword", value32);
-+
-+		if (v_rx_bw == 0) {
-+			v_length = (u16)(value32 & 0x1ffff);
-+			vbrsv = (u8)((value32 & 0xE0000) >> 17);
-+			vb_tail = (u16)((value32 & 0x03F00000) >> 20);
-+		} else if (v_rx_bw == 1) {
-+			v_length = (u16)(value32 & 0x7FFFF);
-+			vbrsv = (u8)((value32 & 0x180000) >> 19);
-+			vb_tail = (u16)((value32 & 0x07E00000) >> 21);
-+		} else if (v_rx_bw == 2) {
-+			v_length = (u16)(value32 & 0x1fffff);
-+			vbrsv = (u8)((value32 & 0x600000) >> 21);
-+			vb_tail = (u16)((value32 & 0x1f800000) >> 23);
-+		}
-+		vbcrc = (u8)((value32 & 0x80000000) >> 31);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "\r\n %-35s = %x / %x / %x / %x",
-+			 "length/Rsv/tail/CRC",
-+			 v_length, vbrsv, vb_tail, vbcrc);
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+#endif
-+
-+u8 phydm_get_l_sig_rate(void *dm_void, u8 rate_idx_l_sig)
-+{
-+	u8 rate_idx = 0xff;
-+
-+	switch (rate_idx_l_sig) {
-+	case 0x0b:
-+		rate_idx = 6;
-+		break;
-+	case 0x0f:
-+		rate_idx = 9;
-+		break;
-+	case 0x0a:
-+		rate_idx = 12;
-+		break;
-+	case 0x0e:
-+		rate_idx = 18;
-+		break;
-+	case 0x09:
-+		rate_idx = 24;
-+		break;
-+	case 0x0d:
-+		rate_idx = 36;
-+		break;
-+	case 0x08:
-+		rate_idx = 48;
-+		break;
-+	case 0x0c:
-+		rate_idx = 54;
-+		break;
-+	default:
-+		rate_idx = 0xff;
-+		break;
-+	}
-+
-+	return rate_idx;
-+}
-+
-+void phydm_bb_hw_dbg_info(void *dm_void, char input[][16], u32 *_used,
-+			  char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	switch (dm->ic_ip_series) {
-+	#if (ODM_IC_11N_SERIES_SUPPORT)
-+	case PHYDM_IC_N:
-+		phydm_bb_hw_dbg_info_n(dm, &used, output, &out_len);
-+		break;
-+	#endif
-+
-+	#if (ODM_IC_11AC_SERIES_SUPPORT)
-+	case PHYDM_IC_AC:
-+		phydm_bb_hw_dbg_info_ac(dm, &used, output, &out_len);
-+		phydm_reset_bb_hw_cnt(dm);
-+		#if (RTL8822B_SUPPORT)
-+		phydm_bb_hw_dbg_info_8822b(dm, &used, output, &out_len);
-+		#endif
-+		break;
-+	#endif
-+
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	case PHYDM_IC_JGR3:
-+		phydm_bb_hw_dbg_info_jgr3(dm, &used, output, &out_len);
-+		phydm_reset_bb_hw_cnt(dm);
-+		break;
-+	#endif
-+	default:
-+		break;
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+
-+void phydm_dm_summary_cli_win(void *dm_void, char *buf, u8 macid)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;
-+	struct cmn_sta_info *sta = NULL;
-+	struct ra_sta_info *ra = NULL;
-+	struct dtp_info *dtp = NULL;
-+	u64 comp = dm->support_ability;
-+	u64 pause_comp = dm->pause_ability;
-+
-+	if (!dm->is_linked) {
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "[%s]No Link !!!\n", __func__);
-+		RT_PRINT(buf);
-+		return;
-+	}
-+
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "00.(%s) %-12s: IGI=0x%x, Dyn_Rng=0x%x~0x%x, FA_th={%d,%d,%d}\n",
-+		   ((comp & ODM_BB_DIG) ?
-+		   ((pause_comp & ODM_BB_DIG) ? "P" : "V") : "."),
-+		   "DIG",
-+		   dig_t->cur_ig_value,
-+		   dig_t->rx_gain_range_min, dig_t->rx_gain_range_max,
-+		   dig_t->fa_th[0], dig_t->fa_th[1], dig_t->fa_th[2]);
-+        RT_PRINT(buf);
-+
-+	sta = dm->phydm_sta_info[macid];
-+	if (is_sta_active(sta)) {
-+		ra = &sta->ra_info;
-+		dtp = &sta->dtp_stat;
-+
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "01.(%s) %-12s: rssi_lv=%d, mask=0x%llx\n",
-+			   ((comp & ODM_BB_RA_MASK) ?
-+			   ((pause_comp & ODM_BB_RA_MASK) ? "P" : "V") : "."),
-+			   "RaMask",
-+			   ra->rssi_level, ra->ramask);
-+		RT_PRINT(buf);
-+
-+		#ifdef CONFIG_DYNAMIC_TX_TWR
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "02.(%s) %-12s: pwr_lv=%d\n",
-+			   ((comp & ODM_BB_DYNAMIC_TXPWR) ?
-+			   ((pause_comp & ODM_BB_DYNAMIC_TXPWR) ? "P" : "V") : "."),
-+			   "DynTxPwr",
-+			   dtp->sta_tx_high_power_lvl);
-+		RT_PRINT(buf);
-+		#endif
-+	}
-+
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "05.(%s) %-12s: cck_pd_lv=%d\n",
-+		   ((comp & ODM_BB_CCK_PD) ?
-+		   ((pause_comp & ODM_BB_CCK_PD) ? "P" : "V") : "."),
-+		   "CCK_PD", dm->dm_cckpd_table.cck_pd_lv);
-+	RT_PRINT(buf);
-+
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "06.(%s) %-12s: div_type=%d, curr_ant=%s\n",
-+		   ((comp & ODM_BB_ANT_DIV) ?
-+		   ((pause_comp & ODM_BB_ANT_DIV) ? "P" : "V") : "."),
-+		   "ANT_DIV",
-+		   dm->ant_div_type,
-+		   (dm->dm_fat_table.rx_idle_ant == MAIN_ANT) ? "MAIN" : "AUX");
-+	RT_PRINT(buf);
-+#endif
-+
-+#ifdef PHYDM_POWER_TRAINING_SUPPORT
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "08.(%s) %-12s: PT_score=%d, disable_PT=%d\n",
-+		   ((comp & ODM_BB_PWR_TRAIN) ?
-+		   ((pause_comp & ODM_BB_PWR_TRAIN) ? "P" : "V") : "."),
-+		   "PwrTrain",
-+		   dm->pow_train_table.pow_train_score,
-+		   dm->is_disable_power_training);
-+	RT_PRINT(buf);
-+#endif
-+
-+#ifdef CONFIG_PHYDM_DFS_MASTER
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "11.(%s) %-12s: dbg_mode=%d, region_domain=%d\n",
-+		   ((comp & ODM_BB_DFS) ?
-+		   ((pause_comp & ODM_BB_DFS) ? "P" : "V") : "."),
-+		   "DFS",
-+		   dm->dfs.dbg_mode, dm->dfs_region_domain);
-+	RT_PRINT(buf);
-+#endif
-+#ifdef PHYDM_SUPPORT_ADAPTIVITY
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "13.(%s) %-12s: th{l2h, h2l}={%d, %d}, edcca_flag=%d\n",
-+		   ((comp & ODM_BB_ADAPTIVITY) ?
-+		   ((pause_comp & ODM_BB_ADAPTIVITY) ? "P" : "V") : "."),
-+		   "Adaptivity",
-+		   dm->adaptivity.th_l2h, dm->adaptivity.th_h2l,
-+		   dm->false_alm_cnt.edcca_flag);
-+	RT_PRINT(buf);
-+#endif
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "14.(%s) %-12s: CFO_avg=%d kHz, CFO_traking=%s%d\n",
-+		   ((comp & ODM_BB_CFO_TRACKING) ?
-+		   ((pause_comp & ODM_BB_CFO_TRACKING) ? "P" : "V") : "."),
-+		   "CfoTrack",
-+		   cfo_t->CFO_ave_pre,
-+		   ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"),
-+		   DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));
-+	RT_PRINT(buf);
-+
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+		   "15.(%s) %-12s: ratio{nhm, clm}={%d, %d}, level{valid, RSSI}={%d, %d}\n",
-+		   ((comp & ODM_BB_ENV_MONITOR) ?
-+		   ((pause_comp & ODM_BB_ENV_MONITOR) ? "P" : "V") : "."),
-+		   "EnvMntr",
-+		   dm->dm_ccx_info.nhm_ratio, dm->dm_ccx_info.clm_ratio,
-+		   dm->dm_ccx_info.nhm_level_valid, dm->dm_ccx_info.nhm_level);
-+	RT_PRINT(buf);
-+#ifdef PHYDM_PRIMARY_CCA
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "16.(%s) %-12s: CCA @ (%s SB)\n",
-+		   ((comp & ODM_BB_PRIMARY_CCA) ?
-+		   ((pause_comp & ODM_BB_PRIMARY_CCA) ? "P" : "V") : "."),
-+		   "PriCCA",
-+		   ((dm->dm_pri_cca.mf_state == MF_USC_LSC) ? "D" :
-+		   ((dm->dm_pri_cca.mf_state == MF_LSC) ? "L" : "U")));
-+	RT_PRINT(buf);
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "17.(%s) %-12s: soml_en = %s\n",
-+		   ((comp & ODM_BB_ADAPTIVE_SOML) ?
-+		   ((pause_comp & ODM_BB_ADAPTIVE_SOML) ? "P" : "V") : "."),
-+		   "A-SOML",
-+		   (dm->dm_soml_table.soml_last_state == SOML_ON) ?
-+		   "ON" : "OFF");
-+	RT_PRINT(buf);
-+#endif
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "18.(%s) %-12s:\n",
-+		   ((comp & ODM_BB_LNA_SAT_CHK) ?
-+		   ((pause_comp & ODM_BB_LNA_SAT_CHK) ? "P" : "V") : "."),
-+		   "LNA_SAT_CHK");
-+	RT_PRINT(buf);
-+#endif
-+}
-+
-+void phydm_basic_dbg_msg_cli_win(void *dm_void, char *buf)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
-+	struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;
-+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info_win_bkp;
-+	struct phydm_phystatus_statistic *dbg_s = &dbg->physts_statistic_info;
-+	struct phydm_phystatus_avg *dbg_avg = &dbg->phystatus_statistic_avg;
-+
-+	char *rate_type = NULL;
-+	u8 tmp_rssi_avg[4];
-+	u8 tmp_snr_avg[4];
-+	u8 tmp_evm_avg[4];
-+	u32 tmp_cnt = 0;
-+	u8 macid, target_macid = 0;
-+	u8 i = 0;
-+	u8 rate_num = dm->num_rf_path;
-+	u8 ss_ofst = 0;
-+	struct cmn_sta_info *entry = NULL;
-+	char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
-+
-+
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n PHYDM Common Dbg Msg --------->");
-+	RT_PRINT(buf);
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n System up time=%d", dm->phydm_sys_up_time);
-+	RT_PRINT(buf);
-+
-+	if (dm->is_linked) {
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n ID=((%d)), BW=((%d)), fc=((CH-%d))",
-+			   dm->curr_station_id, 20 << *dm->band_width, *dm->channel);
-+		RT_PRINT(buf);
-+
-+		if (((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_40)) &&
-+		    (dm->support_ic_type & ODM_IC_11N_SERIES)) {
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Primary CCA at ((%s SB))",
-+				   (*dm->sec_ch_offset == SECOND_CH_AT_LSB) ? "U" : "L");
-+			RT_PRINT(buf);
-+		}
-+
-+		if (dm->cck_new_agc || dm->rx_rate > ODM_RATE11M) {
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}",
-+				   dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1],
-+				   dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]);
-+			RT_PRINT(buf);
-+		} else {
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [CCK AGC Idx] {LNA,VGA}={0x%x, 0x%x}",
-+				   dm->cck_lna_idx, dm->cck_vga_idx);
-+			RT_PRINT(buf);
-+		}
-+
-+		phydm_print_rate_2_buff(dm, dm->rx_rate, dbg_buf, PHYDM_SNPRINT_SIZE);
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n RSSI:{%d, %d, %d, %d}, RxRate:%s (0x%x)",
-+			   (dm->rssi_a == 0xff) ? 0 : dm->rssi_a,
-+			   (dm->rssi_b == 0xff) ? 0 : dm->rssi_b,
-+			   (dm->rssi_c == 0xff) ? 0 : dm->rssi_c,
-+			   (dm->rssi_d == 0xff) ? 0 : dm->rssi_d,
-+			  dbg_buf, dm->rx_rate);
-+		RT_PRINT(buf);
-+
-+		phydm_print_rate_2_buff(dm, dm->phy_dbg_info.beacon_phy_rate, dbg_buf, PHYDM_SNPRINT_SIZE);
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Beacon_cnt=%d, rate_idx:%s (0x%x)",
-+			   dm->phy_dbg_info.beacon_cnt_in_period,
-+			   dbg_buf,
-+			   dm->phy_dbg_info.beacon_phy_rate);
-+		RT_PRINT(buf);
-+
-+		/*Show phydm_rx_rate_distribution;*/
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [RxRate Cnt] =============>");
-+		RT_PRINT(buf);
-+
-+		/*@======CCK=================================================*/
-+		if (*dm->channel <= 14) {
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * CCK = {%d, %d, %d, %d}",
-+				   dbg->num_qry_legacy_pkt[0], dbg->num_qry_legacy_pkt[1],
-+				   dbg->num_qry_legacy_pkt[2], dbg->num_qry_legacy_pkt[3]);
-+			RT_PRINT(buf);
-+		}
-+		/*@======OFDM================================================*/
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}",
-+			   dbg->num_qry_legacy_pkt[4], dbg->num_qry_legacy_pkt[5],
-+			   dbg->num_qry_legacy_pkt[6], dbg->num_qry_legacy_pkt[7],
-+			   dbg->num_qry_legacy_pkt[8], dbg->num_qry_legacy_pkt[9],
-+			   dbg->num_qry_legacy_pkt[10], dbg->num_qry_legacy_pkt[11]);
-+		RT_PRINT(buf);
-+
-+		/*@======HT==================================================*/
-+		if (dbg->ht_pkt_not_zero) {
-+			for (i = 0; i < rate_num; i++) {
-+				ss_ofst = (i << 3);
-+
-+				RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}",
-+					   (ss_ofst), (ss_ofst + 7),
-+					   dbg->num_qry_ht_pkt[ss_ofst + 0], dbg->num_qry_ht_pkt[ss_ofst + 1],
-+					   dbg->num_qry_ht_pkt[ss_ofst + 2], dbg->num_qry_ht_pkt[ss_ofst + 3],
-+					   dbg->num_qry_ht_pkt[ss_ofst + 4], dbg->num_qry_ht_pkt[ss_ofst + 5],
-+					   dbg->num_qry_ht_pkt[ss_ofst + 6], dbg->num_qry_ht_pkt[ss_ofst + 7]);
-+				RT_PRINT(buf);
-+			}
-+
-+			if (dbg->low_bw_20_occur) {
-+				for (i = 0; i < rate_num; i++) {
-+					ss_ofst = (i << 3);
-+
-+					RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * [Low BW 20M] HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}",
-+						   (ss_ofst), (ss_ofst + 7),
-+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 0], dbg->num_qry_pkt_sc_20m[ss_ofst + 1],
-+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 2], dbg->num_qry_pkt_sc_20m[ss_ofst + 3],
-+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 4], dbg->num_qry_pkt_sc_20m[ss_ofst + 5],
-+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 6], dbg->num_qry_pkt_sc_20m[ss_ofst + 7]);
-+					RT_PRINT(buf);
-+				}
-+			}
-+		}
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
-+		/*@======VHT=================================================*/
-+		if (dbg->vht_pkt_not_zero) {
-+			for (i = 0; i < rate_num; i++) {
-+				ss_ofst = 10 * i;
-+
-+				RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}",
-+					   (i + 1),
-+					   dbg->num_qry_vht_pkt[ss_ofst + 0], dbg->num_qry_vht_pkt[ss_ofst + 1],
-+					   dbg->num_qry_vht_pkt[ss_ofst + 2], dbg->num_qry_vht_pkt[ss_ofst + 3],
-+					   dbg->num_qry_vht_pkt[ss_ofst + 4], dbg->num_qry_vht_pkt[ss_ofst + 5],
-+					   dbg->num_qry_vht_pkt[ss_ofst + 6], dbg->num_qry_vht_pkt[ss_ofst + 7],
-+					   dbg->num_qry_vht_pkt[ss_ofst + 8], dbg->num_qry_vht_pkt[ss_ofst + 9]);
-+				RT_PRINT(buf);
-+			}
-+
-+			if (dbg->low_bw_20_occur) {
-+				for (i = 0; i < rate_num; i++) {
-+					ss_ofst = 10 * i;
-+
-+					RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n *[Low BW 20M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}",
-+						   (i + 1),
-+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 0], dbg->num_qry_pkt_sc_20m[ss_ofst + 1],
-+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 2], dbg->num_qry_pkt_sc_20m[ss_ofst + 3],
-+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 4], dbg->num_qry_pkt_sc_20m[ss_ofst + 5],
-+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 6], dbg->num_qry_pkt_sc_20m[ss_ofst + 7],
-+						   dbg->num_qry_pkt_sc_20m[ss_ofst + 8], dbg->num_qry_pkt_sc_20m[ss_ofst + 9]);
-+					RT_PRINT(buf);
-+				}
-+			}
-+
-+			if (dbg->low_bw_40_occur) {
-+				for (i = 0; i < rate_num; i++) {
-+					ss_ofst = 10 * i;
-+
-+					RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n *[Low BW 40M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}",
-+						   (i + 1),
-+						   dbg->num_qry_pkt_sc_40m[ss_ofst + 0], dbg->num_qry_pkt_sc_40m[ss_ofst + 1],
-+						   dbg->num_qry_pkt_sc_40m[ss_ofst + 2], dbg->num_qry_pkt_sc_40m[ss_ofst + 3],
-+						   dbg->num_qry_pkt_sc_40m[ss_ofst + 4], dbg->num_qry_pkt_sc_40m[ss_ofst + 5],
-+						   dbg->num_qry_pkt_sc_40m[ss_ofst + 6], dbg->num_qry_pkt_sc_40m[ss_ofst + 7],
-+						   dbg->num_qry_pkt_sc_40m[ss_ofst + 8], dbg->num_qry_pkt_sc_40m[ss_ofst + 9]);
-+					RT_PRINT(buf);
-+				}
-+			}
-+		}
-+#endif
-+
-+		//1 Show phydm_avg_phystatus_val
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+			   "\r\n [Avg PHY Statistic] ==============>\n");
-+		RT_PRINT(buf);
-+
-+		/*===[Beacon]===*/
-+		switch (dm->num_rf_path) {
-+#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+		case 4:
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n",
-+				   "[Beacon]", dbg_s->rssi_beacon_cnt,
-+				   dbg_avg->rssi_beacon_avg[0],
-+				   dbg_avg->rssi_beacon_avg[1],
-+				   dbg_avg->rssi_beacon_avg[2],
-+				   dbg_avg->rssi_beacon_avg[3]);
-+			break;
-+#endif
-+#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+		case 3:
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n",
-+				   "[Beacon]", dbg_s->rssi_beacon_cnt,
-+				   dbg_avg->rssi_beacon_avg[0],
-+				   dbg_avg->rssi_beacon_avg[1],
-+				   dbg_avg->rssi_beacon_avg[2]);
-+			break;
-+#endif
-+#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+		case 2:
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n",
-+				   "[Beacon]", dbg_s->rssi_beacon_cnt,
-+				   dbg_avg->rssi_beacon_avg[0],
-+				   dbg_avg->rssi_beacon_avg[1]);
-+			break;
-+#endif
-+		default:
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n",
-+				   "[Beacon]", dbg_s->rssi_beacon_cnt,
-+				   dbg_avg->rssi_beacon_avg[0]);
-+			break;
-+		}
-+		RT_PRINT(buf);
-+
-+		/*===[CCK]===*/
-+		switch (dm->num_rf_path) {
-+#ifdef PHYSTS_3RD_TYPE_SUPPORT
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+		case 4:
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n",
-+				   "[CCK]", dbg_s->rssi_cck_cnt,
-+				   dbg_avg->rssi_cck_avg,
-+				   dbg_avg->rssi_cck_avg_abv_2ss[0],
-+				   dbg_avg->rssi_cck_avg_abv_2ss[1],
-+				   dbg_avg->rssi_cck_avg_abv_2ss[2]);
-+			break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+		case 3:
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n",
-+				   "[CCK]", dbg_s->rssi_cck_cnt,
-+				   dbg_avg->rssi_cck_avg,
-+				   dbg_avg->rssi_cck_avg_abv_2ss[0],
-+				   dbg_avg->rssi_cck_avg_abv_2ss[1]);
-+			break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+		case 2:
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n",
-+				   "[CCK]", dbg_s->rssi_cck_cnt,
-+				   dbg_avg->rssi_cck_avg,
-+				   dbg_avg->rssi_cck_avg_abv_2ss[0]);
-+			break;
-+	#endif
-+#endif
-+		default:
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n",
-+				   "[CCK]", dbg_s->rssi_cck_cnt,
-+				   dbg_avg->rssi_cck_avg);
-+			break;
-+		}
-+		RT_PRINT(buf);
-+
-+		for (i = 0; i <= 4; i++) {
-+			if (i > dm->num_rf_path)
-+				break;
-+
-+			odm_memory_set(dm, tmp_rssi_avg, 0, 4);
-+			odm_memory_set(dm, tmp_snr_avg, 0, 4);
-+			odm_memory_set(dm, tmp_evm_avg, 0, 4);
-+
-+			#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+			if (i == 4) {
-+				rate_type = "[4-SS]";
-+				tmp_cnt = dbg_s->rssi_4ss_cnt;
-+				odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_4ss_avg, dm->num_rf_path);
-+				odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_4ss_avg, dm->num_rf_path);
-+				odm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_4ss_avg, 4);
-+			} else
-+			#endif
-+			#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+			if (i == 3) {
-+				rate_type = "[3-SS]";
-+				tmp_cnt = dbg_s->rssi_3ss_cnt;
-+				odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_3ss_avg, dm->num_rf_path);
-+				odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_3ss_avg, dm->num_rf_path);
-+				odm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_3ss_avg, 3);
-+			} else
-+			#endif
-+			#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+			if (i == 2) {
-+				rate_type = "[2-SS]";
-+				tmp_cnt = dbg_s->rssi_2ss_cnt;
-+				odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_2ss_avg, dm->num_rf_path);
-+				odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_2ss_avg, dm->num_rf_path);
-+				odm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_2ss_avg, 2);
-+			} else
-+			#endif
-+			if (i == 1) {
-+				rate_type = "[1-SS]";
-+				tmp_cnt = dbg_s->rssi_1ss_cnt;
-+				odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_1ss_avg, dm->num_rf_path);
-+				odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_1ss_avg, dm->num_rf_path);
-+				odm_move_memory(dm, tmp_evm_avg, &dbg_avg->evm_1ss_avg, 1);
-+			} else {
-+				rate_type = "[L-OFDM]";
-+				tmp_cnt = dbg_s->rssi_ofdm_cnt;
-+				odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_ofdm_avg, dm->num_rf_path);
-+				odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_ofdm_avg, dm->num_rf_path);
-+				odm_move_memory(dm, tmp_evm_avg, &dbg_avg->evm_ofdm_avg, 1);
-+			}
-+
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+				   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d, -%.2d}\n",
-+				    rate_type, tmp_cnt,
-+				    tmp_rssi_avg[0], tmp_rssi_avg[1], tmp_rssi_avg[2], tmp_rssi_avg[3],
-+				    tmp_snr_avg[0], tmp_snr_avg[1], tmp_snr_avg[2], tmp_snr_avg[3],
-+				    tmp_evm_avg[0], tmp_evm_avg[1], tmp_evm_avg[2], tmp_evm_avg[3]);
-+			RT_PRINT(buf);
-+		}
-+		/*@----------------------------------------------------------*/
-+
-+		/*Print TX rate*/
-+		for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
-+			entry = dm->phydm_sta_info[macid];
-+
-+			if (is_sta_active(entry)) {
-+				phydm_print_rate_2_buff(dm, entry->ra_info.curr_tx_rate, dbg_buf, PHYDM_SNPRINT_SIZE);
-+				RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n TxRate[%d]=%s (0x%x)", macid, dbg_buf, entry->ra_info.curr_tx_rate);
-+				RT_PRINT(buf);
-+				target_macid = macid;
-+				break;
-+			}
-+		}
-+
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+			   "\r\n TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))",
-+			   dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load);
-+		RT_PRINT(buf);
-+
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n CFO_avg=((%d kHz)), CFO_traking = ((%s%d))",
-+			   cfo_t->CFO_ave_pre,
-+			   ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"),
-+			   DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));
-+		RT_PRINT(buf);
-+
-+		/* @Condition number */
-+		#if (RTL8822B_SUPPORT)
-+		if (dm->support_ic_type == ODM_RTL8822B) {
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Condi_Num=((%d.%.4d))",
-+				   dm->phy_dbg_info.condi_num >> 4,
-+				   phydm_show_fraction_num(dm->phy_dbg_info.condi_num & 0xf, 4));
-+			RT_PRINT(buf);
-+		}
-+		#endif
-+
-+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))
-+		/*STBC or LDPC pkt*/
-+		if (dm->support_ic_type & (PHYSTS_2ND_TYPE_IC |
-+					   PHYSTS_3RD_TYPE_IC))
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Coding: LDPC=((%s)), STBC=((%s))",
-+				   (dm->phy_dbg_info.is_ldpc_pkt) ? "Y" : "N",
-+				   (dm->phy_dbg_info.is_stbc_pkt) ? "Y" : "N");
-+			RT_PRINT(buf);
-+#endif
-+
-+	} else {
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n No Link !!!");
-+		RT_PRINT(buf);
-+	}
-+
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}",
-+		   fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
-+	RT_PRINT(buf);
-+
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}",
-+		   fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);
-+	RT_PRINT(buf);
-+
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+		   "\r\n [OFDM FA] Parity=%d, Rate=%d, Fast_Fsync=%d, SBD=%d",
-+		   fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
-+		   fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail);
-+	RT_PRINT(buf);
-+
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [HT FA] CRC8=%d, MCS=%d",
-+		   fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail);
-+	RT_PRINT(buf);
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
-+	if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+			   "\r\n [VHT FA] SIGA_CRC8=%d, SIGB_CRC8=%d, MCS=%d",
-+			   fa_t->cnt_crc8_fail_vhta, fa_t->cnt_crc8_fail_vhtb,
-+			   fa_t->cnt_mcs_fail_vht);
-+		RT_PRINT(buf);
-+	}
-+#endif
-+
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+		   "\r\n [CRC32 OK Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}",
-+		   fa_t->cnt_cck_crc32_ok, fa_t->cnt_ofdm_crc32_ok,
-+		   fa_t->cnt_ht_crc32_ok, fa_t->cnt_vht_crc32_ok,
-+		   fa_t->cnt_crc32_ok_all);
-+	RT_PRINT(buf);
-+
-+	RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+		   "\r\n [CRC32 Err Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}",
-+		   fa_t->cnt_cck_crc32_error, fa_t->cnt_ofdm_crc32_error,
-+		   fa_t->cnt_ht_crc32_error, fa_t->cnt_vht_crc32_error,
-+		   fa_t->cnt_crc32_error_all);
-+	RT_PRINT(buf);
-+
-+	if (fa_t->ofdm2_rate_idx) {
-+		phydm_print_rate_2_buff(dm, fa_t->ofdm2_rate_idx,
-+					dbg_buf, PHYDM_SNPRINT_SIZE);
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+			   "\r\n [OFDM:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)",
-+			   dbg_buf, fa_t->cnt_ofdm2_crc32_error,
-+			   fa_t->cnt_ofdm2_crc32_ok, fa_t->ofdm2_pcr);
-+		RT_PRINT(buf);
-+	}
-+
-+	if (fa_t->ht2_rate_idx) {
-+		phydm_print_rate_2_buff(dm, fa_t->ht2_rate_idx, dbg_buf,
-+					PHYDM_SNPRINT_SIZE);
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+			   "\r\n [HT  :%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)",
-+			   dbg_buf, fa_t->cnt_ht2_crc32_error,
-+			   fa_t->cnt_ht2_crc32_ok, fa_t->ht2_pcr);
-+		RT_PRINT(buf);
-+	}
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
-+	if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
-+		if (fa_t->vht2_rate_idx) {
-+			phydm_print_rate_2_buff(dm, fa_t->vht2_rate_idx,
-+						dbg_buf, PHYDM_SNPRINT_SIZE);
-+			RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+				   "\r\n [VHT :%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)",
-+				   dbg_buf, fa_t->cnt_vht2_crc32_error,
-+				   fa_t->cnt_vht2_crc32_ok, fa_t->vht2_pcr);
-+			RT_PRINT(buf);
-+		}
-+	}
-+#endif
-+
-+	if (dm->support_ic_type & (ODM_IC_11N_SERIES | ODM_IC_11AC_SERIES))
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+			   "\r\n is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d\n",
-+			   dm->is_linked, dm->number_linked_client, dm->rssi_min,
-+			   dm->dm_dig_table.cur_ig_value, dm->noisy_decision);
-+	else
-+		RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE,
-+			   "\r\n is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x\n",
-+			   dm->is_linked, dm->number_linked_client, dm->rssi_min,
-+			   dm->dm_dig_table.cur_ig_value);
-+
-+	RT_PRINT(buf);
-+
-+	phydm_dm_summary_cli_win(dm, buf, target_macid);
-+}
-+
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+void phydm_sbd_check(
-+	struct dm_struct *dm)
-+{
-+	static u32 pkt_cnt;
-+	static boolean sbd_state;
-+	u32 sym_count, count, value32;
-+
-+	if (sbd_state == 0) {
-+		pkt_cnt++;
-+		/*read SBD conter once every 5 packets*/
-+		if (pkt_cnt % 5 == 0) {
-+			odm_set_timer(dm, &dm->sbdcnt_timer, 0); /*@ms*/
-+			sbd_state = 1;
-+		}
-+	} else { /*read counter*/
-+		value32 = odm_get_bb_reg(dm, R_0xf98, MASKDWORD);
-+		sym_count = (value32 & 0x7C000000) >> 26;
-+		count = (value32 & 0x3F00000) >> 20;
-+		pr_debug("#SBD# sym_count %d count %d\n", sym_count, count);
-+		sbd_state = 0;
-+	}
-+}
-+#endif
-+
-+void phydm_sbd_callback(
-+	struct phydm_timer_list *timer)
-+{
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+	void *adapter = timer->Adapter;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+
-+#if USE_WORKITEM
-+	odm_schedule_work_item(&dm->sbdcnt_workitem);
-+#else
-+	phydm_sbd_check(dm);
-+#endif
-+#endif
-+}
-+
-+void phydm_sbd_workitem_callback(
-+	void *context)
-+{
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+	void *adapter = (void *)context;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+
-+	phydm_sbd_check(dm);
-+#endif
-+}
-+#endif
-+
-+void phydm_reset_rx_rate_distribution(struct dm_struct *dm)
-+{
-+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
-+
-+	odm_memory_set(dm, &dbg->num_qry_legacy_pkt[0], 0,
-+		       (LEGACY_RATE_NUM * 2));
-+	odm_memory_set(dm, &dbg->num_qry_ht_pkt[0], 0,
-+		       (HT_RATE_NUM * 2));
-+	odm_memory_set(dm, &dbg->num_qry_pkt_sc_20m[0], 0,
-+		       (LOW_BW_RATE_NUM * 2));
-+
-+	dbg->ht_pkt_not_zero = false;
-+	dbg->low_bw_20_occur = false;
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
-+	odm_memory_set(dm, &dbg->num_qry_vht_pkt[0], 0, VHT_RATE_NUM * 2);
-+	odm_memory_set(dm, &dbg->num_qry_pkt_sc_40m[0], 0, LOW_BW_RATE_NUM * 2);
-+	#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) || (defined(PHYSTS_3RD_TYPE_SUPPORT))
-+	odm_memory_set(dm, &dbg->num_mu_vht_pkt[0], 0, VHT_RATE_NUM * 2);
-+	#endif
-+	dbg->vht_pkt_not_zero = false;
-+	dbg->low_bw_40_occur = false;
-+#endif
-+}
-+
-+void phydm_rx_rate_distribution(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
-+	u8 i = 0;
-+	u8 rate_num = dm->num_rf_path, ss_ofst = 0;
-+
-+	PHYDM_DBG(dm, DBG_CMN, "[RxRate Cnt] =============>\n");
-+
-+	/*@======CCK=========================================================*/
-+	if (*dm->channel <= 14) {
-+		PHYDM_DBG(dm, DBG_CMN, "* CCK = {%d, %d, %d, %d}\n",
-+			  dbg->num_qry_legacy_pkt[0],
-+			  dbg->num_qry_legacy_pkt[1],
-+			  dbg->num_qry_legacy_pkt[2],
-+			  dbg->num_qry_legacy_pkt[3]);
-+	}
-+	/*@======OFDM========================================================*/
-+	PHYDM_DBG(dm, DBG_CMN, "* OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
-+		  dbg->num_qry_legacy_pkt[4], dbg->num_qry_legacy_pkt[5],
-+		  dbg->num_qry_legacy_pkt[6], dbg->num_qry_legacy_pkt[7],
-+		  dbg->num_qry_legacy_pkt[8], dbg->num_qry_legacy_pkt[9],
-+		  dbg->num_qry_legacy_pkt[10], dbg->num_qry_legacy_pkt[11]);
-+
-+	/*@======HT==========================================================*/
-+	if (dbg->ht_pkt_not_zero) {
-+		for (i = 0; i < rate_num; i++) {
-+			ss_ofst = (i << 3);
-+
-+			PHYDM_DBG(dm, DBG_CMN,
-+				  "* HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
-+				  (ss_ofst), (ss_ofst + 7),
-+				  dbg->num_qry_ht_pkt[ss_ofst + 0],
-+				  dbg->num_qry_ht_pkt[ss_ofst + 1],
-+				  dbg->num_qry_ht_pkt[ss_ofst + 2],
-+				  dbg->num_qry_ht_pkt[ss_ofst + 3],
-+				  dbg->num_qry_ht_pkt[ss_ofst + 4],
-+				  dbg->num_qry_ht_pkt[ss_ofst + 5],
-+				  dbg->num_qry_ht_pkt[ss_ofst + 6],
-+				  dbg->num_qry_ht_pkt[ss_ofst + 7]);
-+		}
-+
-+		if (dbg->low_bw_20_occur) {
-+			for (i = 0; i < rate_num; i++) {
-+				ss_ofst = (i << 3);
-+
-+				PHYDM_DBG(dm, DBG_CMN,
-+					  "* [Low BW 20M] HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
-+					  (ss_ofst), (ss_ofst + 7),
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 0],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 1],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 2],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 3],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 4],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 5],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 6],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 7]);
-+			}
-+		}
-+	}
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
-+	/*@======VHT==========================================================*/
-+	if (dbg->vht_pkt_not_zero) {
-+		for (i = 0; i < rate_num; i++) {
-+			ss_ofst = 10 * i;
-+
-+			PHYDM_DBG(dm, DBG_CMN,
-+				  "* VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
-+				  (i + 1),
-+				  dbg->num_qry_vht_pkt[ss_ofst + 0],
-+				  dbg->num_qry_vht_pkt[ss_ofst + 1],
-+				  dbg->num_qry_vht_pkt[ss_ofst + 2],
-+				  dbg->num_qry_vht_pkt[ss_ofst + 3],
-+				  dbg->num_qry_vht_pkt[ss_ofst + 4],
-+				  dbg->num_qry_vht_pkt[ss_ofst + 5],
-+				  dbg->num_qry_vht_pkt[ss_ofst + 6],
-+				  dbg->num_qry_vht_pkt[ss_ofst + 7],
-+				  dbg->num_qry_vht_pkt[ss_ofst + 8],
-+				  dbg->num_qry_vht_pkt[ss_ofst + 9]);
-+		}
-+
-+		if (dbg->low_bw_20_occur) {
-+			for (i = 0; i < rate_num; i++) {
-+				ss_ofst = 10 * i;
-+
-+				PHYDM_DBG(dm, DBG_CMN,
-+					  "*[Low BW 20M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
-+					  (i + 1),
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 0],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 1],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 2],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 3],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 4],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 5],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 6],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 7],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 8],
-+					  dbg->num_qry_pkt_sc_20m[ss_ofst + 9]);
-+			}
-+		}
-+
-+		if (dbg->low_bw_40_occur) {
-+			for (i = 0; i < rate_num; i++) {
-+				ss_ofst = 10 * i;
-+
-+				PHYDM_DBG(dm, DBG_CMN,
-+					  "*[Low BW 40M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
-+					  (i + 1),
-+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 0],
-+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 1],
-+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 2],
-+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 3],
-+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 4],
-+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 5],
-+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 6],
-+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 7],
-+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 8],
-+					  dbg->num_qry_pkt_sc_40m[ss_ofst + 9]);
-+			}
-+		}
-+	}
-+#endif
-+}
-+
-+u16 phydm_rx_utility(void *dm_void, u16 avg_phy_rate, u8 rx_max_ss,
-+		     enum channel_width bw)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
-+	u16 utility_primitive = 0, utility = 0;
-+
-+	if (dbg->ht_pkt_not_zero) {
-+	/*@ MCS7 20M: tp = 65, 1000/65 = 15.38, 65*15.5 = 1007*/
-+		utility_primitive = avg_phy_rate * 15 + (avg_phy_rate >> 1);
-+	}
-+#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
-+	else if (dbg->vht_pkt_not_zero) {
-+	/*@ VHT 1SS MCS9(fake) 20M: tp = 90, 1000/90 = 11.11, 65*11.125 = 1001*/
-+		utility_primitive = avg_phy_rate * 11 + (avg_phy_rate >> 3);
-+	}
-+#endif
-+	else {
-+	/*@ 54M, 1000/54 = 18.5, 54*18.5 = 999*/
-+		utility_primitive = avg_phy_rate * 18 + (avg_phy_rate >> 1);
-+	}
-+
-+	utility = (utility_primitive / rx_max_ss) >> bw;
-+
-+	if (utility > 1000)
-+		utility = 1000;
-+
-+	return utility;
-+}
-+
-+u16 phydm_rx_avg_phy_rate(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
-+	u8 i = 0, rate_num = 0, rate_base = 0;
-+	u16 rate = 0, avg_phy_rate = 0;
-+	u32 pkt_cnt = 0, phy_rate_sum = 0;
-+
-+	if (dbg->ht_pkt_not_zero) {
-+		rate_num = HT_RATE_NUM;
-+		rate_base = ODM_RATEMCS0;
-+		for (i = 0; i < rate_num; i++) {
-+			rate = phy_rate_table[i + rate_base] << *dm->band_width;
-+			phy_rate_sum += dbg->num_qry_ht_pkt[i] * rate;
-+			pkt_cnt += dbg->num_qry_ht_pkt[i];
-+		}
-+	}
-+#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
-+	else if (dbg->vht_pkt_not_zero) {
-+		rate_num = VHT_RATE_NUM;
-+		rate_base = ODM_RATEVHTSS1MCS0;
-+		for (i = 0; i < rate_num; i++) {
-+			rate = phy_rate_table[i + rate_base] << *dm->band_width;
-+			phy_rate_sum += dbg->num_qry_vht_pkt[i] * rate;
-+			pkt_cnt += dbg->num_qry_vht_pkt[i];
-+		}
-+	}
-+#endif
-+	else {
-+		for (i = ODM_RATE1M; i <= ODM_RATE54M; i++) {
-+			/*SKIP 1M & 6M for beacon case*/
-+			if (*dm->channel < 36 && i == ODM_RATE1M)
-+				continue;
-+
-+			if (*dm->channel >= 36 && i == ODM_RATE6M)
-+				continue;
-+
-+			rate = phy_rate_table[i];
-+			phy_rate_sum += dbg->num_qry_legacy_pkt[i] * rate;
-+			pkt_cnt += dbg->num_qry_legacy_pkt[i];
-+		}
-+	}
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
-+	if (dbg->low_bw_40_occur) {
-+		for (i = 0; i < LOW_BW_RATE_NUM; i++) {
-+			rate = phy_rate_table[i + rate_base]
-+			       << CHANNEL_WIDTH_40;
-+			phy_rate_sum += dbg->num_qry_pkt_sc_40m[i] * rate;
-+			pkt_cnt += dbg->num_qry_pkt_sc_40m[i];
-+		}
-+	}
-+#endif
-+
-+	if (dbg->low_bw_20_occur) {
-+		for (i = 0; i < LOW_BW_RATE_NUM; i++) {
-+			rate = phy_rate_table[i + rate_base];
-+			phy_rate_sum += dbg->num_qry_pkt_sc_20m[i] * rate;
-+			pkt_cnt += dbg->num_qry_pkt_sc_20m[i];
-+		}
-+	}
-+
-+	avg_phy_rate = (pkt_cnt == 0) ? 0 : (u16)(phy_rate_sum / pkt_cnt);
-+
-+	return avg_phy_rate;
-+}
-+
-+void phydm_print_hist_2_buf(void *dm_void, u16 *val, u16 len, char *buf,
-+			    u16 buf_size)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (len == PHY_HIST_SIZE) {
-+		PHYDM_SNPRINTF(buf, buf_size,
-+			       "[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]",
-+			       val[0], val[1], val[2], val[3], val[4],
-+			       val[5], val[6], val[7], val[8], val[9],
-+			       val[10], val[11]);
-+	} else if (len == (PHY_HIST_SIZE - 1)) {
-+		PHYDM_SNPRINTF(buf, buf_size,
-+			       "[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]",
-+			       val[0], val[1], val[2], val[3], val[4],
-+			       val[5], val[6], val[7], val[8], val[9],
-+			       val[10]);
-+	}
-+}
-+
-+void phydm_nss_hitogram(void *dm_void, enum PDM_RATE_TYPE rate_type)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
-+	char buf[PHYDM_SNPRINT_SIZE] = {0};
-+	u16 buf_size = PHYDM_SNPRINT_SIZE;
-+	u16 h_size = PHY_HIST_SIZE;
-+	u16 *evm_hist = &dbg_s->evm_1ss_hist[0];
-+	u16 *snr_hist = &dbg_s->snr_1ss_hist[0];
-+	u8 i = 0;
-+	u8 ss = phydm_rate_type_2_num_ss(dm, rate_type);
-+
-+	for (i = 0; i < ss; i++) {
-+		if (rate_type == PDM_1SS) {
-+			evm_hist = &dbg_s->evm_1ss_hist[0];
-+			snr_hist = &dbg_s->snr_1ss_hist[0];
-+		} else if (rate_type == PDM_2SS) {
-+			#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+			evm_hist = &dbg_s->evm_2ss_hist[i][0];
-+			snr_hist = &dbg_s->snr_2ss_hist[i][0];
-+			#endif
-+		} else if (rate_type == PDM_3SS) {
-+			#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+			evm_hist = &dbg_s->evm_3ss_hist[i][0];
-+			snr_hist = &dbg_s->snr_3ss_hist[i][0];
-+			#endif
-+		} else if (rate_type == PDM_4SS) {
-+			#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+			evm_hist = &dbg_s->evm_4ss_hist[i][0];
-+			snr_hist = &dbg_s->snr_4ss_hist[i][0];
-+			#endif
-+		}
-+
-+		phydm_print_hist_2_buf(dm, evm_hist, h_size, buf, buf_size);
-+		PHYDM_DBG(dm, DBG_CMN, "[%d-SS][EVM][%d]=%s\n", ss, i, buf);
-+		phydm_print_hist_2_buf(dm, snr_hist, h_size, buf, buf_size);
-+		PHYDM_DBG(dm, DBG_CMN, "[%d-SS][SNR][%d]=%s\n",  ss, i, buf);
-+	}
-+}
-+
-+#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
-+void phydm_show_cn_hitogram(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
-+	u16 th_tmp[PHY_HIST_TH_SIZE];
-+	char buf[PHYDM_SNPRINT_SIZE] = {0};
-+	u8 i = 0;
-+	u16 *cn_hist = NULL;
-+	u32 cn_avg = 0;
-+
-+	if (!dm->pkt_proc_struct.physts_auto_swch_en)
-+		return;
-+
-+	if (dm->num_rf_path == 1)
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_CMN, "[Condition number Histogram] ========>\n");
-+/*@===[Threshold]=============================================================*/
-+	for (i = 0; i < PHY_HIST_TH_SIZE; i++)
-+		th_tmp[i] = dbg_i->cn_hist_th[i] >> 1;
-+
-+	phydm_print_hist_2_buf(dm, th_tmp,
-+			       PHY_HIST_TH_SIZE, buf, PHYDM_SNPRINT_SIZE);
-+	PHYDM_DBG(dm, DBG_CMN, "%-24s=%s\n", "[CN_TH]", buf);
-+
-+/*@===[Histogram]=============================================================*/
-+
-+	for (i = 1; i <= dm->num_rf_path; i++) {
-+		if (dbg_s->p4_cnt[i] == 0)
-+			continue;
-+
-+		cn_avg = PHYDM_DIV((dbg_s->cn_sum[i] +
-+				   (dbg_s->p4_cnt[i] >> 1)) << 2,
-+				   dbg_s->p4_cnt[i]); /*u(8,1)<<2 -> u(10,3)*/
-+
-+		cn_hist = &dbg_s->cn_hist[i][0];
-+		phydm_print_hist_2_buf(dm, cn_hist,
-+				       PHY_HIST_SIZE, buf, PHYDM_SNPRINT_SIZE);
-+		PHYDM_DBG(dm, DBG_CMN, "[%d-SS]%s=(avg:%d.%4d)%s\n",
-+			  i + 1, "[CN]", cn_avg >> 3,
-+			  phydm_show_fraction_num(cn_avg & 0x7, 3), buf);
-+	}
-+}
-+#endif
-+
-+void phydm_show_phy_hitogram(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
-+	char buf[PHYDM_SNPRINT_SIZE] = {0};
-+	u16 buf_size = PHYDM_SNPRINT_SIZE;
-+	u16 th_size = PHY_HIST_SIZE - 1;
-+	u8 i = 0;
-+
-+	PHYDM_DBG(dm, DBG_CMN, "[PHY Histogram] ==============>\n");
-+/*@===[Threshold]=============================================================*/
-+	phydm_print_hist_2_buf(dm, dbg_i->evm_hist_th, th_size, buf, buf_size);
-+	PHYDM_DBG(dm, DBG_CMN, "%-16s=%s\n", "[EVM_TH]", buf);
-+
-+	phydm_print_hist_2_buf(dm, dbg_i->snr_hist_th, th_size, buf, buf_size);
-+	PHYDM_DBG(dm, DBG_CMN, "%-16s=%s\n", "[SNR_TH]", buf);
-+/*@===[OFDM]==================================================================*/
-+	if (dbg_s->rssi_ofdm_cnt) {
-+		phydm_print_hist_2_buf(dm, dbg_s->evm_ofdm_hist, PHY_HIST_SIZE,
-+				       buf, buf_size);
-+		PHYDM_DBG(dm, DBG_CMN, "%-14s=%s\n", "[OFDM][EVM]", buf);
-+
-+		phydm_print_hist_2_buf(dm, dbg_s->snr_ofdm_hist, PHY_HIST_SIZE,
-+				       buf, buf_size);
-+		PHYDM_DBG(dm, DBG_CMN, "%-14s=%s\n", "[OFDM][SNR]", buf);
-+	}
-+/*@===[1-SS]==================================================================*/
-+	if (dbg_s->rssi_1ss_cnt)
-+		phydm_nss_hitogram(dm, PDM_1SS);
-+/*@===[2-SS]==================================================================*/
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	if ((dm->support_ic_type & PHYDM_IC_ABOVE_2SS) && dbg_s->rssi_2ss_cnt)
-+		phydm_nss_hitogram(dm, PDM_2SS);
-+	#endif
-+/*@===[3-SS]==================================================================*/
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	if ((dm->support_ic_type & PHYDM_IC_ABOVE_3SS) && dbg_s->rssi_3ss_cnt)
-+		phydm_nss_hitogram(dm, PDM_3SS);
-+	#endif
-+/*@===[4-SS]==================================================================*/
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS && dbg_s->rssi_4ss_cnt)
-+		phydm_nss_hitogram(dm, PDM_4SS);
-+	#endif
-+}
-+
-+void phydm_avg_phy_val_nss(void *dm_void, u8 nss)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
-+	struct phydm_phystatus_avg *dbg_avg = &dbg_i->phystatus_statistic_avg;
-+	char *rate_type = NULL;
-+	u32 *tmp_cnt = NULL;
-+	u8 *tmp_rssi_avg = NULL;
-+	u32 *tmp_rssi_sum = NULL;
-+	u8 *tmp_snr_avg = NULL;
-+	u32 *tmp_snr_sum = NULL;
-+	u8 *tmp_evm_avg = NULL;
-+	u32 *tmp_evm_sum = NULL;
-+	u8 evm_rpt_show[RF_PATH_MEM_SIZE];
-+	u8 i = 0;
-+
-+	odm_memory_set(dm, &evm_rpt_show[0], 0, RF_PATH_MEM_SIZE);
-+
-+	switch (nss) {
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	case 4:
-+		rate_type = "[4-SS]";
-+		tmp_cnt = &dbg_s->rssi_4ss_cnt;
-+		tmp_rssi_avg = &dbg_avg->rssi_4ss_avg[0];
-+		tmp_snr_avg = &dbg_avg->snr_4ss_avg[0];
-+		tmp_rssi_sum = &dbg_s->rssi_4ss_sum[0];
-+		tmp_snr_sum = &dbg_s->snr_4ss_sum[0];
-+		tmp_evm_avg = &dbg_avg->evm_4ss_avg[0];
-+		tmp_evm_sum = &dbg_s->evm_4ss_sum[0];
-+		break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	case 3:
-+		rate_type = "[3-SS]";
-+		tmp_cnt = &dbg_s->rssi_3ss_cnt;
-+		tmp_rssi_avg = &dbg_avg->rssi_3ss_avg[0];
-+		tmp_snr_avg = &dbg_avg->snr_3ss_avg[0];
-+		tmp_rssi_sum = &dbg_s->rssi_3ss_sum[0];
-+		tmp_snr_sum = &dbg_s->snr_3ss_sum[0];
-+		tmp_evm_avg = &dbg_avg->evm_3ss_avg[0];
-+		tmp_evm_sum = &dbg_s->evm_3ss_sum[0];
-+		break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	case 2:
-+		rate_type = "[2-SS]";
-+		tmp_cnt = &dbg_s->rssi_2ss_cnt;
-+		tmp_rssi_avg = &dbg_avg->rssi_2ss_avg[0];
-+		tmp_snr_avg = &dbg_avg->snr_2ss_avg[0];
-+		tmp_rssi_sum = &dbg_s->rssi_2ss_sum[0];
-+		tmp_snr_sum = &dbg_s->snr_2ss_sum[0];
-+		tmp_evm_avg = &dbg_avg->evm_2ss_avg[0];
-+		tmp_evm_sum = &dbg_s->evm_2ss_sum[0];
-+		break;
-+	#endif
-+	case 1:
-+		rate_type = "[1-SS]";
-+		tmp_cnt = &dbg_s->rssi_1ss_cnt;
-+		tmp_rssi_avg = &dbg_avg->rssi_1ss_avg[0];
-+		tmp_snr_avg = &dbg_avg->snr_1ss_avg[0];
-+		tmp_rssi_sum = &dbg_s->rssi_1ss_sum[0];
-+		tmp_snr_sum = &dbg_s->snr_1ss_sum[0];
-+		tmp_evm_avg = &dbg_avg->evm_1ss_avg;
-+		tmp_evm_sum = &dbg_s->evm_1ss_sum;
-+		break;
-+	case 0:
-+		rate_type = "[L-OFDM]";
-+		tmp_cnt = &dbg_s->rssi_ofdm_cnt;
-+		tmp_rssi_avg = &dbg_avg->rssi_ofdm_avg[0];
-+		tmp_snr_avg = &dbg_avg->snr_ofdm_avg[0];
-+		tmp_rssi_sum = &dbg_s->rssi_ofdm_sum[0];
-+		tmp_snr_sum = &dbg_s->snr_ofdm_sum[0];
-+		tmp_evm_avg = &dbg_avg->evm_ofdm_avg;
-+		tmp_evm_sum = &dbg_s->evm_ofdm_sum;
-+		break;
-+	default:
-+		PHYDM_DBG(dm, DBG_CMN, "[warning] %s\n", __func__);
-+		return;
-+	}
-+
-+	if (*tmp_cnt != 0) {
-+		for (i = 0; i < dm->num_rf_path; i++) {
-+			tmp_rssi_avg[i] = (u8)(tmp_rssi_sum[i] / *tmp_cnt);
-+			tmp_snr_avg[i] = (u8)(tmp_snr_sum[i] / *tmp_cnt);
-+		}
-+
-+		if (nss == 0 || nss == 1) {
-+			*tmp_evm_avg = (u8)(*tmp_evm_sum / *tmp_cnt);
-+			evm_rpt_show[0] = *tmp_evm_avg;
-+		} else {
-+			for (i = 0; i < nss; i++) {
-+				tmp_evm_avg[i] = (u8)(tmp_evm_sum[i] /
-+						      *tmp_cnt);
-+				evm_rpt_show[i] = tmp_evm_avg[i];
-+			}
-+		}
-+	}
-+
-+#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	PHYDM_DBG(dm, DBG_CMN,
-+		  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d, -%.2d}\n",
-+		  rate_type, *tmp_cnt,
-+		  tmp_rssi_avg[0], tmp_rssi_avg[1], tmp_rssi_avg[2],
-+		  tmp_rssi_avg[3], tmp_snr_avg[0], tmp_snr_avg[1],
-+		  tmp_snr_avg[2], tmp_snr_avg[3], evm_rpt_show[0],
-+		  evm_rpt_show[1], evm_rpt_show[2], evm_rpt_show[3]);
-+#elif (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	PHYDM_DBG(dm, DBG_CMN,
-+		  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d}\n",
-+		  rate_type, *tmp_cnt,
-+		  tmp_rssi_avg[0], tmp_rssi_avg[1], tmp_rssi_avg[2],
-+		  tmp_snr_avg[0], tmp_snr_avg[1], tmp_snr_avg[2],
-+		  evm_rpt_show[0], evm_rpt_show[1], evm_rpt_show[2]);
-+#elif (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	PHYDM_DBG(dm, DBG_CMN,
-+		  "* %-8s Cnt= ((%.3d)) RSSI:{%.2d, %.2d} SNR:{%.2d, %.2d} EVM:{-%.2d, -%.2d}\n",
-+		  rate_type, *tmp_cnt,
-+		  tmp_rssi_avg[0], tmp_rssi_avg[1],
-+		  tmp_snr_avg[0], tmp_snr_avg[1],
-+		  evm_rpt_show[0], evm_rpt_show[1]);
-+#else
-+	PHYDM_DBG(dm, DBG_CMN,
-+		  "* %-8s Cnt= ((%.3d)) RSSI:{%.2d} SNR:{%.2d} EVM:{-%.2d}\n",
-+		  rate_type, *tmp_cnt,
-+		  tmp_rssi_avg[0], tmp_snr_avg[0], evm_rpt_show[0]);
-+#endif
-+}
-+
-+void phydm_get_avg_phystatus_val(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
-+	struct phydm_phystatus_avg *dbg_avg = &dbg_i->phystatus_statistic_avg;
-+	u32 avg_tmp = 0;
-+	u8 i = 0;
-+
-+	PHYDM_DBG(dm, DBG_CMN, "[PHY Avg] ==============>\n");
-+	phydm_reset_phystatus_avg(dm);
-+
-+	/*@===[Beacon]===*/
-+	if (dbg_s->rssi_beacon_cnt) {
-+		for (i = 0; i < dm->num_rf_path; i++) {
-+			avg_tmp = dbg_s->rssi_beacon_sum[i] /
-+				  dbg_s->rssi_beacon_cnt;
-+			dbg_avg->rssi_beacon_avg[i] = (u8)avg_tmp;
-+		}
-+	}
-+
-+	switch (dm->num_rf_path) {
-+#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	case 4:
-+		PHYDM_DBG(dm, DBG_CMN,
-+			  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n",
-+			  "[Beacon]", dbg_s->rssi_beacon_cnt,
-+			  dbg_avg->rssi_beacon_avg[0],
-+			  dbg_avg->rssi_beacon_avg[1],
-+			  dbg_avg->rssi_beacon_avg[2],
-+			  dbg_avg->rssi_beacon_avg[3]);
-+		break;
-+#endif
-+#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	case 3:
-+		PHYDM_DBG(dm, DBG_CMN,
-+			  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n",
-+			  "[Beacon]", dbg_s->rssi_beacon_cnt,
-+			  dbg_avg->rssi_beacon_avg[0],
-+			  dbg_avg->rssi_beacon_avg[1],
-+			  dbg_avg->rssi_beacon_avg[2]);
-+		break;
-+#endif
-+#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	case 2:
-+		PHYDM_DBG(dm, DBG_CMN,
-+			  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n",
-+			  "[Beacon]", dbg_s->rssi_beacon_cnt,
-+			  dbg_avg->rssi_beacon_avg[0],
-+			  dbg_avg->rssi_beacon_avg[1]);
-+		break;
-+#endif
-+	default:
-+		PHYDM_DBG(dm, DBG_CMN, "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n",
-+			  "[Beacon]", dbg_s->rssi_beacon_cnt,
-+			  dbg_avg->rssi_beacon_avg[0]);
-+		break;
-+	}
-+
-+	/*@===[CCK]===*/
-+	if (dbg_s->rssi_cck_cnt) {
-+		dbg_avg->rssi_cck_avg = (u8)(dbg_s->rssi_cck_sum /
-+					     dbg_s->rssi_cck_cnt);
-+		#if (defined(PHYSTS_3RD_TYPE_SUPPORT) && defined(PHYDM_COMPILE_ABOVE_2SS))
-+		if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {
-+			for (i = 0; i < dm->num_rf_path - 1; i++) {
-+				avg_tmp = dbg_s->rssi_cck_sum_abv_2ss[i] /
-+					  dbg_s->rssi_cck_cnt;
-+				dbg_avg->rssi_cck_avg_abv_2ss[i] = (u8)avg_tmp;
-+			}
-+		}
-+		#endif
-+	}
-+
-+	switch (dm->num_rf_path) {
-+#ifdef PHYSTS_3RD_TYPE_SUPPORT
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	case 4:
-+		PHYDM_DBG(dm, DBG_CMN,
-+			  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n",
-+			  "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg,
-+			  dbg_avg->rssi_cck_avg_abv_2ss[0],
-+			  dbg_avg->rssi_cck_avg_abv_2ss[1],
-+			  dbg_avg->rssi_cck_avg_abv_2ss[2]);
-+		break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	case 3:
-+		PHYDM_DBG(dm, DBG_CMN,
-+			  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n",
-+			  "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg,
-+			  dbg_avg->rssi_cck_avg_abv_2ss[0],
-+			  dbg_avg->rssi_cck_avg_abv_2ss[1]);
-+		break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	case 2:
-+		PHYDM_DBG(dm, DBG_CMN,
-+			  "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n",
-+			  "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg,
-+			  dbg_avg->rssi_cck_avg_abv_2ss[0]);
-+		break;
-+	#endif
-+#endif
-+	default:
-+		PHYDM_DBG(dm, DBG_CMN, "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n",
-+			  "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg);
-+		break;
-+	}
-+
-+	for (i = 0; i <= dm->num_rf_path; i++)
-+		phydm_avg_phy_val_nss(dm, i);
-+}
-+
-+void phydm_get_phy_statistic(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = dm->phydm_sta_info[dm->one_entry_macid];
-+	enum channel_width bw;
-+	u16 avg_phy_rate = 0;
-+	u16 utility = 0;
-+	u8 rx_ss = 1;
-+
-+	avg_phy_rate = phydm_rx_avg_phy_rate(dm);
-+
-+	if (dm->is_one_entry_only && is_sta_active(sta)) {
-+		rx_ss = phydm_get_rx_stream_num(dm, sta->mimo_type);
-+		bw = sta->bw_mode;
-+		utility = phydm_rx_utility(dm, avg_phy_rate, rx_ss, bw);
-+	}
-+	PHYDM_DBG(dm, DBG_CMN, "Avg_rx_rate = %d, rx_utility=( %d / 1000 )\n",
-+		  avg_phy_rate, utility);
-+
-+	phydm_rx_rate_distribution(dm);
-+	phydm_reset_rx_rate_distribution(dm);
-+
-+	phydm_show_phy_hitogram(dm);
-+	#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
-+	phydm_show_cn_hitogram(dm);
-+	#endif
-+	phydm_get_avg_phystatus_val(dm);
-+	phydm_reset_phystatus_statistic(dm);
-+};
-+
-+void phydm_basic_dbg_msg_linked(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;
-+	struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info;
-+	u16 macid, client_cnt = 0;
-+	u8 rate = 0;
-+	struct cmn_sta_info *entry = NULL;
-+	char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
-+	struct phydm_cfo_rpt cfo;
-+	u8 i = 0;
-+
-+	PHYDM_DBG(dm, DBG_CMN, "ID=((%d)), BW=((%d)), fc=((CH-%d))\n",
-+		  dm->curr_station_id, 20 << *dm->band_width, *dm->channel);
-+
-+	#ifdef ODM_IC_11N_SERIES_SUPPORT
-+	#ifdef PHYDM_PRIMARY_CCA
-+	if (((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_40)) &&
-+	    (dm->support_ic_type & ODM_IC_11N_SERIES) &&
-+	    (dm->support_ability & ODM_BB_PRIMARY_CCA)) {
-+		PHYDM_DBG(dm, DBG_CMN, "Primary CCA at ((%s SB))\n",
-+			  ((*dm->sec_ch_offset == SECOND_CH_AT_LSB) ? "U" :
-+			  "L"));
-+	}
-+	#endif
-+	#endif
-+
-+	if (dm->cck_new_agc || dm->rx_rate > ODM_RATE11M) {
-+		PHYDM_DBG(dm, DBG_CMN, "[AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}\n",
-+			  dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1],
-+			  dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]);
-+	} else {
-+		PHYDM_DBG(dm, DBG_CMN, "[CCK AGC Idx] {LNA,VGA}={0x%x, 0x%x}\n",
-+			  dm->cck_lna_idx, dm->cck_vga_idx);
-+	}
-+
-+	phydm_print_rate_2_buff(dm, dm->rx_rate, dbg_buf, PHYDM_SNPRINT_SIZE);
-+	PHYDM_DBG(dm, DBG_CMN, "RSSI:{%d, %d, %d, %d}, RxRate:%s (0x%x)\n",
-+		  (dm->rssi_a == 0xff) ? 0 : dm->rssi_a,
-+		  (dm->rssi_b == 0xff) ? 0 : dm->rssi_b,
-+		  (dm->rssi_c == 0xff) ? 0 : dm->rssi_c,
-+		  (dm->rssi_d == 0xff) ? 0 : dm->rssi_d,
-+		  dbg_buf, dm->rx_rate);
-+
-+	rate = dbg_t->beacon_phy_rate;
-+	phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);
-+
-+	PHYDM_DBG(dm, DBG_CMN, "Beacon_cnt=%d, rate_idx=%s (0x%x)\n",
-+		  dbg_t->num_qry_beacon_pkt, dbg_buf, dbg_t->beacon_phy_rate);
-+
-+	phydm_get_phy_statistic(dm);
-+
-+	PHYDM_DBG(dm, DBG_CMN,
-+		  "rxsc_idx {Legacy, 20, 40, 80} = {%d, %d, %d, %d}\n",
-+		  dm->rxsc_l, dm->rxsc_20, dm->rxsc_40, dm->rxsc_80);
-+
-+	/*Print TX rate*/
-+	for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
-+		entry = dm->phydm_sta_info[macid];
-+
-+		if (!is_sta_active(entry))
-+			continue;
-+
-+		rate = entry->ra_info.curr_tx_rate;
-+		phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);
-+		PHYDM_DBG(dm, DBG_CMN, "TxRate[%d]=%s (0x%x)\n",
-+			  macid, dbg_buf, entry->ra_info.curr_tx_rate);
-+
-+		client_cnt++;
-+
-+		if (client_cnt >= dm->number_linked_client)
-+			break;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_CMN,
-+		  "TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))\n",
-+		  dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load);
-+
-+	PHYDM_DBG(dm, DBG_CMN, "CFO_avg=((%d kHz)), CFO_traking = ((%s%d))\n",
-+		  cfo_t->CFO_ave_pre,
-+		  ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"),
-+		  DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));
-+
-+	/* @CFO report */
-+	switch (dm->ic_ip_series) {
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	case PHYDM_IC_JGR3:
-+		PHYDM_DBG(dm, DBG_CMN, "cfo_tail = {%d, %d, %d, %d}\n",
-+			  dbg_t->cfo_tail[0], dbg_t->cfo_tail[1],
-+			  dbg_t->cfo_tail[2], dbg_t->cfo_tail[3]);
-+		break;
-+	#endif
-+	default:
-+		phydm_get_cfo_info(dm, &cfo);
-+		for (i = 0; i < dm->num_rf_path; i++) {
-+			PHYDM_DBG(dm, DBG_CMN,
-+				  "CFO[%d] {S, L, Sec, Acq, End} = {%d, %d, %d, %d, %d}\n",
-+				  i, cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i],
-+				  cfo.cfo_rpt_sec[i], cfo.cfo_rpt_acq[i],
-+				  cfo.cfo_rpt_end[i]);
-+		}
-+		break;
-+	}
-+
-+/* @Condition number */
-+#if (RTL8822B_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8822B) {
-+		PHYDM_DBG(dm, DBG_CMN, "Condi_Num=((%d.%.4d)), %d\n",
-+			  dbg_t->condi_num >> 4,
-+			  phydm_show_fraction_num(dbg_t->condi_num & 0xf, 4),
-+			  dbg_t->condi_num);
-+	}
-+#endif
-+#ifdef PHYSTS_3RD_TYPE_SUPPORT
-+	if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {
-+		PHYDM_DBG(dm, DBG_CMN, "Condi_Num=((%d.%4d dB))\n",
-+			  dbg_t->condi_num >> 1,
-+			  phydm_show_fraction_num(dbg_t->condi_num & 0x1, 1));
-+	}
-+#endif
-+
-+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))
-+	/*STBC or LDPC pkt*/
-+	if (dm->support_ic_type & (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC))
-+		PHYDM_DBG(dm, DBG_CMN, "Coding: LDPC=((%s)), STBC=((%s))\n",
-+			  (dbg_t->is_ldpc_pkt) ? "Y" : "N",
-+			  (dbg_t->is_stbc_pkt) ? "Y" : "N");
-+#endif
-+
-+#if (RTL8822C_SUPPORT || RTL8723F_SUPPORT)
-+	/*Beamformed pkt*/
-+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8723F))
-+		PHYDM_DBG(dm, DBG_CMN, "Beamformed=((%s))\n",
-+			  (dm->is_beamformed) ? "Y" : "N");
-+#endif
-+}
-+
-+void phydm_dm_summary(void *dm_void, u8 macid)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track;
-+	struct cmn_sta_info *sta = NULL;
-+	struct ra_sta_info *ra = NULL;
-+	struct dtp_info *dtp = NULL;
-+	u64 comp = dm->support_ability;
-+	u64 pause_comp = dm->pause_ability;
-+
-+	if (!(dm->debug_components & DBG_DM_SUMMARY))
-+		return;
-+
-+	if (!dm->is_linked) {
-+		pr_debug("[%s]No Link !!!\n", __func__);
-+		return;
-+	}
-+
-+	sta = dm->phydm_sta_info[macid];
-+
-+	if (!is_sta_active(sta)) {
-+		pr_debug("[Warning] %s invalid STA, macid=%d\n",
-+			 __func__, macid);
-+		return;
-+	}
-+
-+	ra = &sta->ra_info;
-+	dtp = &sta->dtp_stat;
-+	pr_debug("[%s]===========>\n", __func__);
-+
-+	pr_debug("00.(%s) %-12s: IGI=0x%x, Dyn_Rng=0x%x~0x%x, FA_th={%d,%d,%d}\n",
-+		 ((comp & ODM_BB_DIG) ?
-+		 ((pause_comp & ODM_BB_DIG) ? "P" : "V") : "."),
-+		 "DIG",
-+		 dig_t->cur_ig_value,
-+		 dig_t->rx_gain_range_min, dig_t->rx_gain_range_max,
-+		 dig_t->fa_th[0], dig_t->fa_th[1], dig_t->fa_th[2]);
-+
-+	pr_debug("01.(%s) %-12s: rssi_lv=%d, mask=0x%llx\n",
-+		 ((comp & ODM_BB_RA_MASK) ?
-+		 ((pause_comp & ODM_BB_RA_MASK) ? "P" : "V") : "."),
-+		 "RaMask",
-+		 ra->rssi_level, ra->ramask);
-+
-+#ifdef CONFIG_DYNAMIC_TX_TWR
-+	pr_debug("02.(%s) %-12s: pwr_lv=%d\n",
-+		 ((comp & ODM_BB_DYNAMIC_TXPWR) ?
-+		 ((pause_comp & ODM_BB_DYNAMIC_TXPWR) ? "P" : "V") : "."),
-+		 "DynTxPwr",
-+		 dtp->sta_tx_high_power_lvl);
-+#endif
-+
-+	pr_debug("05.(%s) %-12s: cck_pd_lv=%d\n",
-+		 ((comp & ODM_BB_CCK_PD) ?
-+		 ((pause_comp & ODM_BB_CCK_PD) ? "P" : "V") : "."),
-+		 "CCK_PD", dm->dm_cckpd_table.cck_pd_lv);
-+
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	pr_debug("06.(%s) %-12s: div_type=%d, curr_ant=%s\n",
-+		 ((comp & ODM_BB_ANT_DIV) ?
-+		 ((pause_comp & ODM_BB_ANT_DIV) ? "P" : "V") : "."),
-+		 "ANT_DIV",
-+		 dm->ant_div_type,
-+		 (dm->dm_fat_table.rx_idle_ant == MAIN_ANT) ? "MAIN" : "AUX");
-+#endif
-+
-+#ifdef PHYDM_POWER_TRAINING_SUPPORT
-+	pr_debug("08.(%s) %-12s: PT_score=%d, disable_PT=%d\n",
-+		 ((comp & ODM_BB_PWR_TRAIN) ?
-+		 ((pause_comp & ODM_BB_PWR_TRAIN) ? "P" : "V") : "."),
-+		 "PwrTrain",
-+		 dm->pow_train_table.pow_train_score,
-+		 dm->is_disable_power_training);
-+#endif
-+
-+#ifdef CONFIG_PHYDM_DFS_MASTER
-+	pr_debug("11.(%s) %-12s: dbg_mode=%d, region_domain=%d\n",
-+		 ((comp & ODM_BB_DFS) ?
-+		 ((pause_comp & ODM_BB_DFS) ? "P" : "V") : "."),
-+		 "DFS",
-+		 dm->dfs.dbg_mode, dm->dfs_region_domain);
-+#endif
-+#ifdef PHYDM_SUPPORT_ADAPTIVITY
-+	pr_debug("13.(%s) %-12s: th{l2h, h2l}={%d, %d}, edcca_flag=%d\n",
-+		 ((comp & ODM_BB_ADAPTIVITY) ?
-+		 ((pause_comp & ODM_BB_ADAPTIVITY) ? "P" : "V") : "."),
-+		 "Adaptivity",
-+		 dm->adaptivity.th_l2h, dm->adaptivity.th_h2l,
-+		 dm->false_alm_cnt.edcca_flag);
-+#endif
-+	pr_debug("14.(%s) %-12s: CFO_avg=%d kHz, CFO_traking=%s%d\n",
-+		 ((comp & ODM_BB_CFO_TRACKING) ?
-+		 ((pause_comp & ODM_BB_CFO_TRACKING) ? "P" : "V") : "."),
-+		 "CfoTrack",
-+		 cfo_t->CFO_ave_pre,
-+		 ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"),
-+		 DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap));
-+
-+	pr_debug("15.(%s) %-12s: ratio{nhm, clm}={%d, %d}\n",
-+		 ((comp & ODM_BB_ENV_MONITOR) ?
-+		 ((pause_comp & ODM_BB_ENV_MONITOR) ? "P" : "V") : "."),
-+		 "EnvMntr",
-+		 dm->dm_ccx_info.nhm_ratio, dm->dm_ccx_info.clm_ratio);
-+
-+#ifdef PHYDM_PRIMARY_CCA
-+	pr_debug("16.(%s) %-12s: CCA @ (%s SB)\n",
-+		 ((comp & ODM_BB_PRIMARY_CCA) ?
-+		 ((pause_comp & ODM_BB_PRIMARY_CCA) ? "P" : "V") : "."),
-+		 "PriCCA",
-+		 ((dm->dm_pri_cca.mf_state == MF_USC_LSC) ? "D" :
-+		 ((dm->dm_pri_cca.mf_state == MF_LSC) ? "L" : "U")));
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+	pr_debug("17.(%s) %-12s: soml_en = %s\n",
-+		 ((comp & ODM_BB_ADAPTIVE_SOML) ?
-+		 ((pause_comp & ODM_BB_ADAPTIVE_SOML) ? "P" : "V") : "."),
-+		 "A-SOML",
-+		 (dm->dm_soml_table.soml_last_state == SOML_ON) ?
-+		 "ON" : "OFF");
-+#endif
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+	pr_debug("18.(%s) %-12s:\n",
-+		 ((comp & ODM_BB_LNA_SAT_CHK) ?
-+		 ((pause_comp & ODM_BB_LNA_SAT_CHK) ? "P" : "V") : "."),
-+		 "LNA_SAT_CHK");
-+#endif
-+}
-+
-+void phydm_basic_dbg_message(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
-+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct odm_phy_dbg_info *dbg_b = &dm->phy_dbg_info_win_bkp;
-+	#endif
-+	#ifdef NHM_SUPPORT
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	#endif
-+
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	/* backup memory*/
-+	odm_move_memory(dm, dbg_b, dbg, sizeof(struct odm_phy_dbg_info));
-+	#endif
-+
-+	if (!(dm->debug_components & DBG_CMN)) {
-+		#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+		/* reset rx rate distribution*/
-+		phydm_reset_rx_rate_distribution(dm);
-+		/* cal & reset avg of rssi/snr/evm*/
-+		phydm_get_avg_phystatus_val(dm);
-+		/* reset sum of rssi/snr/evm*/
-+		phydm_reset_phystatus_statistic(dm);
-+		#endif
-+		return;
-+	}
-+
-+	if (dm->cmn_dbg_msg_cnt >= dm->cmn_dbg_msg_period) {
-+		dm->cmn_dbg_msg_cnt = PHYDM_WATCH_DOG_PERIOD;
-+	} else {
-+		dm->cmn_dbg_msg_cnt += PHYDM_WATCH_DOG_PERIOD;
-+		return;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_CMN, "[%s] System up time: ((%d sec))---->\n",
-+		  __func__, dm->phydm_sys_up_time);
-+
-+	if (dm->is_linked)
-+		phydm_basic_dbg_msg_linked(dm);
-+	else
-+		PHYDM_DBG(dm, DBG_CMN, "No Link !!!\n");
-+
-+	PHYDM_DBG(dm, DBG_CMN, "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
-+		  fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
-+	PHYDM_DBG(dm, DBG_CMN, "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
-+		  fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);
-+	PHYDM_DBG(dm, DBG_CMN,
-+		  "[OFDM FA] Parity=%d, Rate=%d, Fast_Fsync=%d, SBD=%d\n",
-+		  fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
-+		  fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail);
-+	PHYDM_DBG(dm, DBG_CMN, "[HT FA] CRC8=%d, MCS=%d\n",
-+		  fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail);
-+#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
-+	if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
-+		PHYDM_DBG(dm, DBG_CMN,
-+			  "[VHT FA] SIGA_CRC8=%d, SIGB_CRC8=%d, MCS=%d\n",
-+			  fa_t->cnt_crc8_fail_vhta, fa_t->cnt_crc8_fail_vhtb,
-+			  fa_t->cnt_mcs_fail_vht);
-+	}
-+#endif
-+	PHYDM_DBG(dm, DBG_CMN,
-+		  "[CRC32 OK Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
-+		  fa_t->cnt_cck_crc32_ok, fa_t->cnt_ofdm_crc32_ok,
-+		  fa_t->cnt_ht_crc32_ok, fa_t->cnt_vht_crc32_ok,
-+		  fa_t->cnt_crc32_ok_all);
-+	PHYDM_DBG(dm, DBG_CMN,
-+		  "[CRC32 Err Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
-+		  fa_t->cnt_cck_crc32_error, fa_t->cnt_ofdm_crc32_error,
-+		  fa_t->cnt_ht_crc32_error, fa_t->cnt_vht_crc32_error,
-+		  fa_t->cnt_crc32_error_all);
-+
-+	if (dm->support_ic_type & (ODM_IC_11N_SERIES | ODM_IC_11AC_SERIES))
-+		PHYDM_DBG(dm, DBG_CMN,
-+			  "is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d\n",
-+			  dm->is_linked, dm->number_linked_client, dm->rssi_min,
-+			  dm->dm_dig_table.cur_ig_value, dm->noisy_decision);
-+	else
-+		PHYDM_DBG(dm, DBG_CMN,
-+			  "is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x\n",
-+			  dm->is_linked, dm->number_linked_client, dm->rssi_min,
-+			  dm->dm_dig_table.cur_ig_value);
-+
-+#ifdef NHM_SUPPORT
-+	if (dm->support_ability & ODM_BB_ENV_MONITOR) {
-+		PHYDM_DBG(dm, DBG_CMN,
-+			  "[NHM] valid: %d percent, noise(RSSI) = %d\n",
-+			  ccx->nhm_level_valid, ccx->nhm_level);
-+	}
-+#endif
-+}
-+
-+void phydm_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len)
-+{
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char *cut = NULL;
-+	char *ic_type = NULL;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 date = 0;
-+	char *commit_by = NULL;
-+	u32 release_ver = 0;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
-+		 "% Basic Profile %");
-+
-+	if (dm->support_ic_type == ODM_RTL8188E) {
-+#if (RTL8188E_SUPPORT)
-+		ic_type = "RTL8188E";
-+		date = RELEASE_DATE_8188E;
-+		commit_by = COMMIT_BY_8188E;
-+		release_ver = RELEASE_VERSION_8188E;
-+#endif
-+#if (RTL8812A_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8812) {
-+		ic_type = "RTL8812A";
-+		date = RELEASE_DATE_8812A;
-+		commit_by = COMMIT_BY_8812A;
-+		release_ver = RELEASE_VERSION_8812A;
-+#endif
-+#if (RTL8821A_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8821) {
-+		ic_type = "RTL8821A";
-+		date = RELEASE_DATE_8821A;
-+		commit_by = COMMIT_BY_8821A;
-+		release_ver = RELEASE_VERSION_8821A;
-+#endif
-+#if (RTL8192E_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8192E) {
-+		ic_type = "RTL8192E";
-+		date = RELEASE_DATE_8192E;
-+		commit_by = COMMIT_BY_8192E;
-+		release_ver = RELEASE_VERSION_8192E;
-+#endif
-+#if (RTL8723B_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8723B) {
-+		ic_type = "RTL8723B";
-+		date = RELEASE_DATE_8723B;
-+		commit_by = COMMIT_BY_8723B;
-+		release_ver = RELEASE_VERSION_8723B;
-+#endif
-+#if (RTL8814A_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8814A) {
-+		ic_type = "RTL8814A";
-+		date = RELEASE_DATE_8814A;
-+		commit_by = COMMIT_BY_8814A;
-+		release_ver = RELEASE_VERSION_8814A;
-+#endif
-+#if (RTL8881A_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8881A) {
-+		ic_type = "RTL8881A";
-+#endif
-+#if (RTL8822B_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8822B) {
-+		ic_type = "RTL8822B";
-+		date = RELEASE_DATE_8822B;
-+		commit_by = COMMIT_BY_8822B;
-+		release_ver = RELEASE_VERSION_8822B;
-+#endif
-+#if (RTL8197F_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8197F) {
-+		ic_type = "RTL8197F";
-+		date = RELEASE_DATE_8197F;
-+		commit_by = COMMIT_BY_8197F;
-+		release_ver = RELEASE_VERSION_8197F;
-+#endif
-+#if (RTL8703B_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8703B) {
-+		ic_type = "RTL8703B";
-+		date = RELEASE_DATE_8703B;
-+		commit_by = COMMIT_BY_8703B;
-+		release_ver = RELEASE_VERSION_8703B;
-+#endif
-+#if (RTL8195A_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8195A) {
-+		ic_type = "RTL8195A";
-+#endif
-+#if (RTL8188F_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8188F) {
-+		ic_type = "RTL8188F";
-+		date = RELEASE_DATE_8188F;
-+		commit_by = COMMIT_BY_8188F;
-+		release_ver = RELEASE_VERSION_8188F;
-+#endif
-+#if (RTL8723D_SUPPORT)
-+	} else if (dm->support_ic_type == ODM_RTL8723D) {
-+		ic_type = "RTL8723D";
-+		date = RELEASE_DATE_8723D;
-+		commit_by = COMMIT_BY_8723D;
-+		release_ver = RELEASE_VERSION_8723D;
-+#endif
-+	}
-+
-+/* @JJ ADD 20161014 */
-+#if (RTL8710B_SUPPORT)
-+	else if (dm->support_ic_type == ODM_RTL8710B) {
-+		ic_type = "RTL8710B";
-+		date = RELEASE_DATE_8710B;
-+		commit_by = COMMIT_BY_8710B;
-+		release_ver = RELEASE_VERSION_8710B;
-+	}
-+#endif
-+
-+#if (RTL8721D_SUPPORT)
-+	else if (dm->support_ic_type == ODM_RTL8721D) {
-+		ic_type = "RTL8721D";
-+		date = RELEASE_DATE_8721D;
-+		commit_by = COMMIT_BY_8721D;
-+		release_ver = RELEASE_VERSION_8721D;
-+	}
-+#endif
-+
-+#if (RTL8710C_SUPPORT)
-+	else if (dm->support_ic_type == ODM_RTL8710C) {
-+		ic_type = "RTL8710C";
-+		date = RELEASE_DATE_8710C;
-+		commit_by = COMMIT_BY_8710C;
-+		release_ver = RELEASE_VERSION_8710C;
-+	}
-+#endif
-+
-+#if (RTL8821C_SUPPORT)
-+	else if (dm->support_ic_type == ODM_RTL8821C) {
-+		ic_type = "RTL8821C";
-+		date = RELEASE_DATE_8821C;
-+		commit_by = COMMIT_BY_8821C;
-+		release_ver = RELEASE_VERSION_8821C;
-+	}
-+#endif
-+
-+/*@jj add 20170822*/
-+#if (RTL8192F_SUPPORT)
-+	else if (dm->support_ic_type == ODM_RTL8192F) {
-+		ic_type = "RTL8192F";
-+		date = RELEASE_DATE_8192F;
-+		commit_by = COMMIT_BY_8192F;
-+		release_ver = RELEASE_VERSION_8192F;
-+	}
-+#endif
-+
-+#if (RTL8198F_SUPPORT)
-+	else if (dm->support_ic_type == ODM_RTL8198F) {
-+		ic_type = "RTL8198F";
-+		date = RELEASE_DATE_8198F;
-+		commit_by = COMMIT_BY_8198F;
-+		release_ver = RELEASE_VERSION_8198F;
-+	}
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	else if (dm->support_ic_type == ODM_RTL8822C) {
-+		ic_type = "RTL8822C";
-+		date = RELEASE_DATE_8822C;
-+		commit_by = COMMIT_BY_8822C;
-+		release_ver = RELEASE_VERSION_8822C;
-+	}
-+#endif
-+
-+#if (RTL8723F_SUPPORT)
-+	else if (dm->support_ic_type == ODM_RTL8723F) {
-+		ic_type = "RTL8723F";
-+		date = RELEASE_DATE_8723F;
-+		commit_by = COMMIT_BY_8723F;
-+		release_ver = RELEASE_VERSION_8723F;
-+	}
-+#endif
-+#if (RTL8812F_SUPPORT)
-+	else if (dm->support_ic_type == ODM_RTL8812F) {
-+		ic_type = "RTL8812F";
-+		date = RELEASE_DATE_8812F;
-+		commit_by = COMMIT_BY_8812F;
-+		release_ver = RELEASE_VERSION_8812F;
-+	}
-+#endif
-+
-+#if (RTL8197G_SUPPORT)
-+	else if (dm->support_ic_type == ODM_RTL8197G) {
-+		ic_type = "RTL8197G";
-+		date = RELEASE_DATE_8197G;
-+		commit_by = COMMIT_BY_8197G;
-+		release_ver = RELEASE_VERSION_8197G;
-+	}
-+#endif
-+
-+#if (RTL8814B_SUPPORT)
-+	else if (dm->support_ic_type == ODM_RTL8814B) {
-+		ic_type = "RTL8814B";
-+		date = RELEASE_DATE_8814B;
-+		commit_by = COMMIT_BY_8814B;
-+		release_ver = RELEASE_VERSION_8814B;
-+	}
-+#endif
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "  %-35s: %s (MP Chip: %s)\n", "IC type", ic_type,
-+		 dm->is_mp_chip ? "Yes" : "No");
-+
-+	if (dm->cut_version == ODM_CUT_A)
-+		cut = "A";
-+	else if (dm->cut_version == ODM_CUT_B)
-+		cut = "B";
-+	else if (dm->cut_version == ODM_CUT_C)
-+		cut = "C";
-+	else if (dm->cut_version == ODM_CUT_D)
-+		cut = "D";
-+	else if (dm->cut_version == ODM_CUT_E)
-+		cut = "E";
-+	else if (dm->cut_version == ODM_CUT_F)
-+		cut = "F";
-+	else if (dm->cut_version == ODM_CUT_G)
-+		cut = "G";
-+	else if (dm->cut_version == ODM_CUT_H)
-+		cut = "H";
-+	else if (dm->cut_version == ODM_CUT_I)
-+		cut = "I";
-+	else if (dm->cut_version == ODM_CUT_J)
-+		cut = "J";
-+	else if (dm->cut_version == ODM_CUT_K)
-+		cut = "K";
-+	else if (dm->cut_version == ODM_CUT_L)
-+		cut = "L";
-+	else if (dm->cut_version == ODM_CUT_M)
-+		cut = "M";
-+	else if (dm->cut_version == ODM_CUT_N)
-+		cut = "N";
-+	else if (dm->cut_version == ODM_CUT_O)
-+		cut = "O";
-+	else if (dm->cut_version == ODM_CUT_TEST)
-+		cut = "TEST";
-+	else
-+		cut = "UNKNOWN";
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %d\n",
-+		 "RFE type", dm->rfe_type);
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "CART_Ver", cut);
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %d\n",
-+		 "PHY Para Ver", odm_get_hw_img_version(dm));
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %d\n",
-+		 "PHY Para Commit date", date);
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "PHY Para Commit by", commit_by);
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %d\n",
-+		 "PHY Para Release Ver", release_ver);
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "  %-35s: %d (Subversion: %d)\n", "FW Ver", dm->fw_version,
-+		 dm->fw_sub_version);
-+
-+	/* @1 PHY DM version List */
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n",
-+		 "% PHYDM version %");
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "Code base", PHYDM_CODE_BASE);
-+#ifdef PHYDM_SVN_REV
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "PHYDM SVN Ver", PHYDM_SVN_REV);
-+#endif
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "Release Date", PHYDM_RELEASE_DATE);
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "Adaptivity", ADAPTIVITY_VERSION);
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "DIG", DIG_VERSION);
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "CFO Tracking", CFO_TRACKING_VERSION);
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "AntDiv", ANTDIV_VERSION);
-+#endif
-+#ifdef CONFIG_DYNAMIC_TX_TWR
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "Dynamic TxPower", DYNAMIC_TXPWR_VERSION);
-+#endif
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "RA Info", RAINFO_VERSION);
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "AntDetect", ANTDECT_VERSION);
-+#endif
-+#ifdef CONFIG_PATH_DIVERSITY
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "PathDiv", PATHDIV_VERSION);
-+#endif
-+#ifdef CONFIG_ADAPTIVE_SOML
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "Adaptive SOML", ADAPTIVE_SOML_VERSION);
-+#endif
-+#if (PHYDM_LA_MODE_SUPPORT)
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "LA mode", DYNAMIC_LA_MODE);
-+#endif
-+#ifdef PHYDM_PRIMARY_CCA
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "Primary CCA", PRIMARYCCA_VERSION);
-+#endif
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "  %-35s: %s\n",
-+		 "DFS", DFS_VERSION);
-+
-+#if (RTL8822B_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8822B)
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "  %-35s: %s\n", "PHY config 8822B",
-+			 PHY_CONFIG_VERSION_8822B);
-+
-+#endif
-+#if (RTL8197F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197F)
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "  %-35s: %s\n", "PHY config 8197F",
-+			 PHY_CONFIG_VERSION_8197F);
-+#endif
-+
-+/*@jj add 20170822*/
-+#if (RTL8192F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8192F)
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "  %-35s: %s\n", "PHY config 8192F",
-+			 PHY_CONFIG_VERSION_8192F);
-+#endif
-+#if (RTL8721D_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8721D)
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "  %-35s: %s\n", "PHY config 8721D",
-+			 PHY_CONFIG_VERSION_8721D);
-+#endif
-+
-+#if (RTL8710C_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8710C)
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "  %-35s: %s\n", "PHY config 8710C",
-+			 PHY_CONFIG_VERSION_8710C);
-+#endif
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+
-+#endif /*@#if CONFIG_PHYDM_DEBUG_FUNCTION*/
-+}
-+
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+void phydm_fw_trace_en_h2c(void *dm_void, boolean enable,
-+			   u32 fw_dbg_comp, u32 monitor_mode, u32 macid)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 h2c_parameter[7] = {0};
-+	u8 cmd_length;
-+
-+	if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
-+		h2c_parameter[0] = enable;
-+		h2c_parameter[1] = (u8)(fw_dbg_comp & MASKBYTE0);
-+		h2c_parameter[2] = (u8)((fw_dbg_comp & MASKBYTE1) >> 8);
-+		h2c_parameter[3] = (u8)((fw_dbg_comp & MASKBYTE2) >> 16);
-+		h2c_parameter[4] = (u8)((fw_dbg_comp & MASKBYTE3) >> 24);
-+		h2c_parameter[5] = (u8)monitor_mode;
-+		h2c_parameter[6] = (u8)macid;
-+		cmd_length = 7;
-+
-+	} else {
-+		h2c_parameter[0] = enable;
-+		h2c_parameter[1] = (u8)monitor_mode;
-+		h2c_parameter[2] = (u8)macid;
-+		cmd_length = 3;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_FW_TRACE,
-+		  "[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n",
-+		  enable, monitor_mode, macid);
-+
-+	odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_TRACE_EN, cmd_length, h2c_parameter);
-+}
-+
-+void phydm_get_per_path_txagc(void *dm_void, u8 path, u32 *_used, char *output,
-+			      u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 rate_idx = 0;
-+	u8 txagc = 0;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+#ifdef PHYDM_COMMON_API_SUPPORT
-+	if (!(dm->support_ic_type & CMN_API_SUPPORT_IC))
-+		return;
-+
-+	if (dm->num_rf_path == 1 && path > RF_PATH_A)
-+		return;
-+	else if (dm->num_rf_path == 2 && path > RF_PATH_B)
-+		return;
-+	else if (dm->num_rf_path == 3 && path > RF_PATH_C)
-+		return;
-+	else if (dm->num_rf_path == 4 && path > RF_PATH_D)
-+		return;
-+
-+	for (rate_idx = 0; rate_idx <= 0x53; rate_idx++) {
-+		if (!(dm->support_ic_type & PHYDM_IC_ABOVE_3SS) &&
-+		    ((rate_idx >= ODM_RATEMCS16 &&
-+		    rate_idx < ODM_RATEVHTSS1MCS0) ||
-+		    rate_idx >= ODM_RATEVHTSS3MCS0))
-+			continue;
-+
-+		if (rate_idx == ODM_RATE1M)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "  %-35s\n", "CCK====>");
-+		else if (rate_idx == ODM_RATE6M)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n  %-35s\n", "OFDM====>");
-+		else if (rate_idx == ODM_RATEMCS0)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n  %-35s\n", "HT 1ss====>");
-+		else if (rate_idx == ODM_RATEMCS8)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n  %-35s\n", "HT 2ss====>");
-+		else if (rate_idx == ODM_RATEMCS16)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n  %-35s\n", "HT 3ss====>");
-+		else if (rate_idx == ODM_RATEMCS24)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n  %-35s\n", "HT 4ss====>");
-+		else if (rate_idx == ODM_RATEVHTSS1MCS0)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n  %-35s\n", "VHT 1ss====>");
-+		else if (rate_idx == ODM_RATEVHTSS2MCS0)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n  %-35s\n", "VHT 2ss====>");
-+		else if (rate_idx == ODM_RATEVHTSS3MCS0)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n  %-35s\n", "VHT 3ss====>");
-+		else if (rate_idx == ODM_RATEVHTSS4MCS0)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n  %-35s\n", "VHT 4ss====>");
-+
-+		txagc = phydm_api_get_txagc(dm, (enum rf_path)path, rate_idx);
-+		if (config_phydm_read_txagc_check(txagc))
-+			PDM_SNPF(out_len, used, output + used,
-+				 out_len - used, "  0x%02x    ", txagc);
-+		else
-+			PDM_SNPF(out_len, used, output + used,
-+				 out_len - used, "  0x%s    ", "xx");
-+	}
-+#endif
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_get_txagc(void *dm_void, u32 *_used, char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i = 0;
-+
-+	#if (RTL8822C_SUPPORT)
-+	PDM_SNPF(out_len, used, output + used,
-+		 out_len - used, "Disabled DPD rate mask: 0x%x\n",
-+		 dm->dis_dpd_rate);
-+	#endif
-+
-+	for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
-+		if (i == RF_PATH_A)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "%-35s\n", "path-A====================");
-+		else if (i == RF_PATH_B)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n%-35s\n", "path-B====================");
-+		else if (i == RF_PATH_C)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n%-35s\n", "path-C====================");
-+		else if (i == RF_PATH_D)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\n%-35s\n", "path-D====================");
-+
-+		phydm_get_per_path_txagc(dm, i, &used, output, &out_len);
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_set_txagc(void *dm_void, u32 *const val, u32 *_used,
-+		     char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i = 0;
-+	u32 pow = 0; /*power index*/
-+	u8 vht_start_rate = ODM_RATEVHTSS1MCS0;
-+	boolean rpt = true;
-+	enum rf_path path = RF_PATH_A;
-+
-+/*@val[1] = path*/
-+/*@val[2] = hw_rate*/
-+/*@val[3] = power_index*/
-+
-+#ifdef PHYDM_COMMON_API_SUPPORT
-+	if (!(dm->support_ic_type & CMN_API_SUPPORT_IC))
-+		return;
-+
-+	path = (enum rf_path)val[1];
-+
-+	if (val[1] >= dm->num_rf_path) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Write path-%d rate_idx-0x%x fail\n", val[1], val[2]);
-+	} else if ((u8)val[2] != 0xff) {
-+		if (phydm_api_set_txagc(dm, val[3], path, (u8)val[2], true))
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Write path-%d rate_idx-0x%x = 0x%x\n",
-+				 val[1], val[2], val[3]);
-+		else
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Write path-%d rate index-0x%x fail\n",
-+				 val[1], val[2]);
-+	} else {
-+
-+		if (dm->support_ic_type &
-+		    (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) {
-+			pow = (val[3] & 0x3f);
-+			pow = BYTE_DUPLICATE_2_DWORD(pow);
-+
-+			for (i = 0; i < ODM_RATEVHTSS2MCS9; i += 4)
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
-+		} else if (dm->support_ic_type &
-+			   (ODM_RTL8197F | ODM_RTL8192F)) {
-+			pow = (val[3] & 0x3f);
-+			for (i = 0; i <= ODM_RATEMCS15; i++)
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
-+		} else if (dm->support_ic_type & ODM_RTL8198F) {
-+			pow = (val[3] & 0x7f);
-+			for (i = 0; i <= ODM_RATEVHTSS4MCS9; i++)
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
-+		} else if (dm->support_ic_type &
-+			   (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) {
-+			pow = (val[3] & 0x7f);
-+			for (i = 0; i <= ODM_RATEMCS15; i++)
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
-+			for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++)
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
-+		} else if (dm->support_ic_type &
-+			   (ODM_RTL8721D | ODM_RTL8710C)) {
-+			pow = (val[3] & 0x3f);
-+			for (i = 0; i <= ODM_RATEMCS7; i++)
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
-+		} else if (dm->support_ic_type &(ODM_RTL8723F)) {
-+			pow = (val[3] & 0x7f);
-+			for (i = 0; i <= ODM_RATEMCS7; i++)
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 0);
-+		}
-+
-+		if (rpt)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Write all TXAGC of path-%d = 0x%x\n",
-+				 val[1], val[3]);
-+		else
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Write all TXAGC of path-%d fail\n", val[1]);
-+	}
-+
-+#endif
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_shift_txagc(void *dm_void, u32 *const val, u32 *_used, char *output,
-+		       u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i = 0;
-+	u32 pow = 0; /*Power index*/
-+	boolean rpt = true;
-+	u8 vht_start_rate = ODM_RATEVHTSS1MCS0;
-+	enum rf_path path = RF_PATH_A;
-+
-+#ifdef PHYDM_COMMON_API_SUPPORT
-+	if (!(dm->support_ic_type & CMN_API_SUPPORT_IC))
-+		return;
-+
-+	if (val[1] >= dm->num_rf_path) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Write path-%d fail\n", val[1]);
-+		return;
-+	}
-+
-+	path = (enum rf_path)val[1];
-+
-+	if ((u8)val[2] == 0) {
-+	/*@{0:-, 1:+} {Pwr Offset}*/
-+		if (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)) {
-+			for (i = 0; i <= ODM_RATEMCS7; i++) {
-+				pow = phydm_api_get_txagc(dm, path, i) - val[3];
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
-+			}
-+			for (i = vht_start_rate; i <= ODM_RATEVHTSS1MCS9; i++) {
-+				pow = phydm_api_get_txagc(dm, path, i) - val[3];
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
-+			}
-+		} else if (dm->support_ic_type & (ODM_RTL8822B)) {
-+			for (i = 0; i <= ODM_RATEMCS15; i++) {
-+				pow = phydm_api_get_txagc(dm, path, i) - val[3];
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
-+			}
-+			for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++) {
-+				pow = phydm_api_get_txagc(dm, path, i) - val[3];
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
-+			}
-+		} else if (dm->support_ic_type &
-+			   (ODM_RTL8197F | ODM_RTL8192F)) {
-+			for (i = 0; i <= ODM_RATEMCS15; i++) {
-+				pow = phydm_api_get_txagc(dm, path, i) - val[3];
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
-+			}
-+		} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+			rpt &= phydm_api_shift_txagc(dm, val[3], path, 0);
-+		} else if (dm->support_ic_type &
-+			   (ODM_RTL8721D | ODM_RTL8710C)) {
-+			for (i = 0; i <= ODM_RATEMCS7; i++) {
-+				pow = phydm_api_get_txagc(dm, path, i) - val[3];
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
-+			}
-+		}
-+	} else if ((u8)val[2] == 1) {
-+	/*@{0:-, 1:+} {Pwr Offset}*/
-+		if (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)) {
-+			for (i = 0; i <= ODM_RATEMCS7; i++) {
-+				pow = phydm_api_get_txagc(dm, path, i) + val[3];
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
-+			}
-+			for (i = vht_start_rate; i <= ODM_RATEVHTSS1MCS9; i++) {
-+				pow = phydm_api_get_txagc(dm, path, i) + val[3];
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
-+			}
-+		} else if (dm->support_ic_type & (ODM_RTL8822B)) {
-+			for (i = 0; i <= ODM_RATEMCS15; i++) {
-+				pow = phydm_api_get_txagc(dm, path, i) + val[3];
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
-+			}
-+			for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++) {
-+				pow = phydm_api_get_txagc(dm, path, i) + val[3];
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
-+			}
-+		} else if (dm->support_ic_type &
-+			   (ODM_RTL8197F | ODM_RTL8192F)) {
-+			for (i = 0; i <= ODM_RATEMCS15; i++) {
-+				pow = phydm_api_get_txagc(dm, path, i) + val[3];
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
-+			}
-+		} else if (dm->support_ic_type & (ODM_RTL8721D |
-+						  ODM_RTL8710C)) {
-+			for (i = 0; i <= ODM_RATEMCS7; i++) {
-+				pow = phydm_api_get_txagc(dm, path, i) + val[3];
-+				rpt &= phydm_api_set_txagc(dm, pow, path, i, 1);
-+			}
-+		} else if (dm->support_ic_type &
-+			   (ODM_RTL8822C | ODM_RTL8814B |
-+			    ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8723F)) {
-+			rpt &= phydm_api_shift_txagc(dm, val[3], path, 1);
-+		}
-+	}
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[All rate] Set Path-%d Pow_idx: %s %d\n",
-+			 val[1], (val[2] ? "+" : "-"), val[3]);
-+	else
-+	#endif
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[All rate] Set Path-%d Pow_idx: %s %d(%d.%s dB)\n",
-+			 val[1], (val[2] ? "+" : "-"), val[3], val[3] >> 1,
-+			 ((val[3] & 1) ? "5" : "0"));
-+
-+#endif
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_set_txagc_dbg(void *dm_void, char input[][16], u32 *_used,
-+			 char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 var1[10] = {0};
-+	char help[] = "-h";
-+	u8 i = 0, input_idx = 0;
-+
-+	for (i = 0; i < 5; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
-+		input_idx++;
-+	}
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{Dis:0, En:1} {pathA~D(0~3)} {rate_idx(Hex), All_rate:0xff} {txagc_idx (Hex)}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{Pwr Shift(All rate):2} {pathA~D(0~3)} {0:-, 1:+} {Pwr Offset(Hex)}\n");
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{reset all rate ref/diff to 0x0:0xff}\n");
-+		#endif
-+	} else if (var1[0] == 0) {
-+		dm->is_disable_phy_api = false;
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Disable API debug mode\n");
-+	} else if (var1[0] == 1) {
-+		dm->is_disable_phy_api = false;
-+		#ifdef CONFIG_TXAGC_DEBUG_8822C
-+		config_phydm_write_txagc_8822c(dm, var1[3],
-+					       (enum rf_path)var1[1],
-+					       (u8)var1[2]);
-+		#elif (defined(CONFIG_TXAGC_DEBUG_8814B))
-+		config_phydm_write_txagc_8814b(dm, var1[3],
-+					       (enum rf_path)var1[1],
-+					       (u8)var1[2]);
-+		#else
-+		phydm_set_txagc(dm, (u32 *)var1, &used, output, &out_len);
-+		#endif
-+		dm->is_disable_phy_api = true;
-+	} else if (var1[0] == 2) {
-+		PHYDM_SSCANF(input[4], DCMD_HEX, &var1[3]);
-+		dm->is_disable_phy_api = false;
-+		phydm_shift_txagc(dm, (u32 *)var1, &used, output, &out_len);
-+		dm->is_disable_phy_api = true;
-+	}
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	else if (var1[0] == 0xff) {
-+		dm->is_disable_phy_api = false;
-+		phydm_reset_txagc(dm);
-+		dm->is_disable_phy_api = true;
-+	}
-+	#endif
-+	#ifdef CONFIG_TXAGC_DEBUG_8822C
-+	else if (var1[0] == 3) {
-+		dm->is_disable_phy_api = false;
-+		phydm_txagc_tab_buff_show_8822c(dm);
-+		dm->is_disable_phy_api = true;
-+	} else if (var1[0] == 4) {
-+		dm->is_disable_phy_api = false;
-+		config_phydm_set_txagc_to_hw_8822c(dm);
-+		dm->is_disable_phy_api = true;
-+	}
-+	#elif (defined(CONFIG_TXAGC_DEBUG_8814B))
-+	else if (var1[0] == 3) {
-+		dm->is_disable_phy_api = false;
-+		phydm_txagc_tab_buff_show_8814b(dm);
-+		dm->is_disable_phy_api = true;
-+	} else if (var1[0] == 4) {
-+		dm->is_disable_phy_api = false;
-+		config_phydm_set_txagc_to_hw_8814b(dm);
-+		dm->is_disable_phy_api = true;
-+	}
-+	#endif
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_cmn_msg_setting(void *dm_void, u32 *val, u32 *_used,
-+			   char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	if (val[1] == 1) {
-+		dm->cmn_dbg_msg_period = (u8)val[2];
-+
-+		if (dm->cmn_dbg_msg_period < PHYDM_WATCH_DOG_PERIOD)
-+			dm->cmn_dbg_msg_period = PHYDM_WATCH_DOG_PERIOD;
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "cmn_dbg_msg_period=%d\n", dm->cmn_dbg_msg_period);
-+	}
-+
-+#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
-+	if (val[1] == 1)
-+		phydm_physts_auto_switch_jgr3_set(dm, true, BIT(4) | BIT(1));
-+	else
-+		phydm_physts_auto_switch_jgr3_set(dm, false, BIT(1));
-+#endif
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_debug_trace(void *dm_void, char input[][16], u32 *_used,
-+		       char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u64 pre_debug_components, one = 1;
-+	u64 comp = 0;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 val[10] = {0};
-+	u8 i = 0;
-+
-+	for (i = 0; i < 5; i++) {
-+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
-+	}
-+	comp = dm->debug_components;
-+	pre_debug_components = dm->debug_components;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "\n================================\n");
-+	if (val[0] == 100) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[DBG MSG] Component Selection\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "================================\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "00. (( %s ))DIG\n",
-+			 ((comp & DBG_DIG) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "01. (( %s ))RA_MASK\n",
-+			 ((comp & DBG_RA_MASK) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "02. (( %s ))DYN_TXPWR\n",
-+			 ((comp & DBG_DYN_TXPWR) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "03. (( %s ))FA_CNT\n",
-+			 ((comp & DBG_FA_CNT) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "04. (( %s ))RSSI_MNTR\n",
-+			 ((comp & DBG_RSSI_MNTR) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "05. (( %s ))CCKPD\n",
-+			 ((comp & DBG_CCKPD) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "06. (( %s ))ANT_DIV\n",
-+			 ((comp & DBG_ANT_DIV) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "07. (( %s ))SMT_ANT\n",
-+			 ((comp & DBG_SMT_ANT) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "08. (( %s ))PWR_TRAIN\n",
-+			 ((comp & DBG_PWR_TRAIN) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "09. (( %s ))RA\n",
-+			 ((comp & DBG_RA) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "10. (( %s ))PATH_DIV\n",
-+			 ((comp & DBG_PATH_DIV) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "11. (( %s ))DFS\n",
-+			 ((comp & DBG_DFS) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "12. (( %s ))DYN_ARFR\n",
-+			 ((comp & DBG_DYN_ARFR) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "13. (( %s ))ADAPTIVITY\n",
-+			 ((comp & DBG_ADPTVTY) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "14. (( %s ))CFO_TRK\n",
-+			 ((comp & DBG_CFO_TRK) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "15. (( %s ))ENV_MNTR\n",
-+			 ((comp & DBG_ENV_MNTR) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "16. (( %s ))PRI_CCA\n",
-+			 ((comp & DBG_PRI_CCA) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "17. (( %s ))ADPTV_SOML\n",
-+			 ((comp & DBG_ADPTV_SOML) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "18. (( %s ))LNA_SAT_CHK\n",
-+			 ((comp & DBG_LNA_SAT_CHK) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "20. (( %s ))PHY_STATUS\n",
-+			 ((comp & DBG_PHY_STATUS) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "21. (( %s ))TMP\n",
-+			 ((comp & DBG_TMP) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "22. (( %s ))FW_DBG_TRACE\n",
-+			 ((comp & DBG_FW_TRACE) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "23. (( %s ))TXBF\n",
-+			 ((comp & DBG_TXBF) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "24. (( %s ))COMMON_FLOW\n",
-+			 ((comp & DBG_COMMON_FLOW) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "28. (( %s ))PHY_CONFIG\n",
-+			 ((comp & ODM_PHY_CONFIG) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "29. (( %s ))INIT\n",
-+			 ((comp & ODM_COMP_INIT) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "30. (( %s ))COMMON\n",
-+			 ((comp & DBG_CMN) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "31. (( %s ))API\n",
-+			 ((comp & ODM_COMP_API) ? ("V") : (".")));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "================================\n");
-+
-+	} else if (val[0] == 101) {
-+		dm->debug_components = 0;
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Disable all debug components\n");
-+	} else {
-+		if (val[1] == 1) /*@enable*/
-+			dm->debug_components |= (one << val[0]);
-+		else if (val[1] == 2) /*@disable*/
-+			dm->debug_components &= ~(one << val[0]);
-+		else
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[Warning]  1:on,  2:off\n");
-+
-+		if ((BIT(val[0]) == DBG_PHY_STATUS) && val[1] == 1) {
-+			dm->phy_dbg_info.show_phy_sts_all_pkt = (u8)val[2];
-+			dm->phy_dbg_info.show_phy_sts_max_cnt = (u16)val[3];
-+
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "show_all_pkt=%d, show_max_num=%d\n\n",
-+				 dm->phy_dbg_info.show_phy_sts_all_pkt,
-+				 dm->phy_dbg_info.show_phy_sts_max_cnt);
-+
-+		} else if (BIT(val[0]) == DBG_CMN) {
-+			phydm_cmn_msg_setting(dm, val, &used, output, &out_len);
-+		}
-+	}
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "pre-DbgComponents = 0x%llx\n", pre_debug_components);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "Curr-DbgComponents = 0x%llx\n", dm->debug_components);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "================================\n");
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_fw_debug_trace(void *dm_void, char input[][16], u32 *_used,
-+			  char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 val[10] = {0};
-+	u8 i, input_idx = 0;
-+	char help[] = "-h";
-+	u32 pre_fw_debug_components = 0, one = 1;
-+	u32 comp = 0;
-+
-+	for (i = 0; i < 5; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
-+		input_idx++;
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	pre_fw_debug_components = dm->fw_debug_components;
-+	comp = dm->fw_debug_components;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "{dbg_comp} {1:en, 2:dis} {mode} {macid}\n");
-+	} else {
-+		if (val[0] == 101) {
-+			dm->fw_debug_components = 0;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "%s\n", "Clear all fw debug components");
-+		} else {
-+			if (val[1] == 1) /*@enable*/
-+				dm->fw_debug_components |= (one << val[0]);
-+			else if (val[1] == 2) /*@disable*/
-+				dm->fw_debug_components &= ~(one << val[0]);
-+			else
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used, "%s\n",
-+					 "[Warning!!!]  1:enable,  2:disable");
-+		}
-+
-+		comp = dm->fw_debug_components;
-+
-+		if (comp == 0) {
-+			dm->debug_components &= ~DBG_FW_TRACE;
-+			/*@H2C to enable C2H Msg*/
-+			phydm_fw_trace_en_h2c(dm, false, comp, val[2], val[3]);
-+		} else {
-+			dm->debug_components |= DBG_FW_TRACE;
-+			/*@H2C to enable C2H Msg*/
-+			phydm_fw_trace_en_h2c(dm, true, comp, val[2], val[3]);
-+		}
-+	}
-+}
-+
-+#if (ODM_IC_11N_SERIES_SUPPORT)
-+void phydm_dump_bb_reg_n(void *dm_void, u32 *_used, char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 addr = 0;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	/*@For Nseries IC we only need to dump page8 to pageF using 3 digits*/
-+	for (addr = 0x800; addr < 0xfff; addr += 4) {
-+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+			      "0x%03x 0x%08x\n",
-+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+#endif
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT)
-+void phydm_dump_bb_reg_ac(void *dm_void, u32 *_used, char *output,
-+			  u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 addr = 0;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	for (addr = 0x800; addr < 0xfff; addr += 4) {
-+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+			      "0x%04x 0x%08x\n",
-+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
-+	}
-+
-+	if (!(dm->support_ic_type &
-+	    (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C | ODM_RTL8195B)))
-+		goto rpt_reg;
-+
-+	if (dm->rf_type > RF_2T2R) {
-+		for (addr = 0x1800; addr < 0x18ff; addr += 4)
-+			PDM_VAST_SNPF(out_len, used, output + used,
-+				      out_len - used, "0x%04x 0x%08x\n",
-+				      addr,
-+				      odm_get_bb_reg(dm, addr, MASKDWORD));
-+	}
-+
-+	if (dm->rf_type > RF_3T3R) {
-+		for (addr = 0x1a00; addr < 0x1aff; addr += 4)
-+			PDM_VAST_SNPF(out_len, used, output + used,
-+				      out_len - used, "0x%04x 0x%08x\n",
-+				      addr,
-+				      odm_get_bb_reg(dm, addr, MASKDWORD));
-+	}
-+
-+	for (addr = 0x1900; addr < 0x19ff; addr += 4)
-+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+			      "0x%04x 0x%08x\n",
-+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
-+
-+	for (addr = 0x1c00; addr < 0x1cff; addr += 4)
-+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+			      "0x%04x 0x%08x\n",
-+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
-+
-+	for (addr = 0x1f00; addr < 0x1fff; addr += 4)
-+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+			      "0x%04x 0x%08x\n",
-+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
-+
-+rpt_reg:
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#endif
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+void phydm_dump_bb_reg_jgr3(void *dm_void, u32 *_used, char *output,
-+			    u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 addr = 0;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		for (addr = 0x800; addr < 0xdff; addr += 4)
-+			PDM_VAST_SNPF(out_len, used, output + used,
-+				      out_len - used, "0x%04x 0x%08x\n", addr,
-+				      odm_get_bb_reg(dm, addr, MASKDWORD));
-+
-+		for (addr = 0x1800; addr < 0x1aff; addr += 4)
-+			PDM_VAST_SNPF(out_len, used, output + used,
-+				      out_len - used, "0x%04x 0x%08x\n", addr,
-+				      odm_get_bb_reg(dm, addr, MASKDWORD));
-+
-+		for (addr = 0x1c00; addr < 0x1eff; addr += 4)
-+			PDM_VAST_SNPF(out_len, used, output + used,
-+				      out_len - used, "0x%04x 0x%08x\n", addr,
-+				      odm_get_bb_reg(dm, addr, MASKDWORD));
-+
-+		#if (defined(RTL8723F_SUPPORT))
-+		if (dm->support_ic_type & ODM_RTL8723F) {
-+			for (addr = 0x2a00; addr < 0x2a5c; addr += 4) {
-+				PDM_VAST_SNPF(out_len, used, output + used,
-+					      out_len - used, "0x%04x 0x%08x\n",
-+					      addr,
-+					      odm_get_bb_reg(dm, addr,
-+							     MASKDWORD));
-+			}
-+		}
-+		#endif
-+
-+		for (addr = 0x4000; addr < 0x41ff; addr += 4)
-+			PDM_VAST_SNPF(out_len, used, output + used,
-+				      out_len - used, "0x%04x 0x%08x\n", addr,
-+				      odm_get_bb_reg(dm, addr, MASKDWORD));
-+
-+		#if (defined(RTL8723F_SUPPORT))
-+		if (dm->support_ic_type & ODM_RTL8723F) {
-+			for (addr = 0x4300; addr < 0x43bf; addr += 4) {
-+				PDM_VAST_SNPF(out_len, used, output + used,
-+					      out_len - used, "0x%04x 0x%08x\n",
-+					      addr,
-+					      odm_get_bb_reg(dm, addr,
-+							     MASKDWORD));
-+			}
-+		}
-+		#endif
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_dump_bb_reg2_jgr3(void *dm_void, u32 *_used, char *output,
-+			     u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 addr = 0;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
-+		return;
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
-+		for (addr = 0x5000; addr < 0x53ff; addr += 4) {
-+			PDM_VAST_SNPF(out_len, used, output + used,
-+				      out_len - used, "0x%04x 0x%08x\n",
-+				      addr,
-+				      odm_get_bb_reg(dm, addr, MASKDWORD));
-+		}
-+	}
-+	#endif
-+
-+	/* @Do not change the order of page-2C/2D*/
-+	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+		      "------ BB report-register start ------\n");
-+
-+	#if (defined(RTL8723F_SUPPORT))
-+	if (dm->support_ic_type & ODM_RTL8723F) {
-+		for (addr = 0x2aa0; addr < 0x2aff; addr += 4) {
-+			PDM_VAST_SNPF(out_len, used, output + used,
-+				      out_len - used, "0x%04x 0x%08x\n",
-+				      addr,
-+				      odm_get_bb_reg(dm, addr, MASKDWORD));
-+		}
-+	}
-+	#endif
-+
-+	for (addr = 0x2c00; addr < 0x2dff; addr += 4) {
-+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+			      "0x%04x 0x%08x\n",
-+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_get_per_path_anapar_jgr3(void *dm_void, u8 path, u32 *_used,
-+				    char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 state = 0;
-+	u8 state_bp = 0;
-+	u32 control_bb = 0;
-+	u32 control_pow = 0;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 reg_idx = 0;
-+	u32 dbgport_idx = 0;
-+	u32 dbgport_val = 0;
-+
-+	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+		      "path-%d:\n", path);
-+
-+	if (path == RF_PATH_A) {
-+		reg_idx = R_0x1830;
-+		dbgport_idx = 0x9F0;
-+	} else if (path == RF_PATH_B) {
-+		reg_idx = R_0x4130;
-+		dbgport_idx = 0xBF0;
-+	} else if (path == RF_PATH_C) {
-+		reg_idx = R_0x5230;
-+		dbgport_idx = 0xDF0;
-+	} else if (path == RF_PATH_D) {
-+		reg_idx = R_0x5330;
-+		dbgport_idx = 0xFF0;
-+	}
-+
-+	state_bp = (u8)odm_get_bb_reg(dm, reg_idx, 0xf00000);
-+	odm_set_bb_reg(dm, reg_idx, 0x38000000, 0x5); /* @read en*/
-+
-+	for (state = 0; state <= 0xf; state++) {
-+		odm_set_bb_reg(dm, reg_idx, 0xF00000, state);
-+		if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbgport_idx)) {
-+			dbgport_val = phydm_get_bb_dbg_port_val(dm);
-+			phydm_release_bb_dbg_port(dm);
-+		} else {
-+			PDM_VAST_SNPF(out_len, used, output + used,
-+				      out_len - used,
-+				      "state:0x%x = read dbg_port error!\n",
-+				      state);
-+		}
-+		control_bb = (dbgport_val & 0xFFFF0) >> 4;
-+		control_pow = dbgport_val & 0xF;
-+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+			      "state:0x%x = control_bb:0x%x pow_bb:0x%x\n",
-+			      state, control_bb, control_pow);
-+	}
-+	odm_set_bb_reg(dm, reg_idx, 0xf00000, state_bp);
-+	odm_set_bb_reg(dm, reg_idx, 0x38000000, 0x6); /* @write en*/
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_get_csi_table_jgr3(void *dm_void, u32 *_used, char *output,
-+				    u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 table_idx = 0;
-+	u8 table_val = 0;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 dbgport_idx = 0x39e;
-+	u32 dbgport_val = 0;
-+
-+	/*enable clk*/
-+	odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3);
-+	/*enable read table*/
-+	odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x2);
-+
-+	for (table_idx = 0; table_idx < 128; table_idx++) {
-+		odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, table_idx);
-+		if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbgport_idx)) {
-+			dbgport_val = phydm_get_bb_dbg_port_val(dm);
-+			phydm_release_bb_dbg_port(dm);
-+		} else {
-+			PDM_VAST_SNPF(out_len, used, output + used,
-+				      out_len - used,
-+				      "table_idx:0x%x = read dbg_port error!\n",
-+				      table_idx);
-+		}
-+		table_val = dbgport_val >> 24;
-+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+			      "table_idx: 0x%x = 0x%x\n",
-+			      table_idx, table_val);
-+	}
-+	/*enable write table*/
-+	odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1);
-+	/*disable clk*/
-+	odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0);
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#endif
-+
-+void phydm_dump_bb_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+		      "BB==========\n");
-+	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+		      "------ BB control register start ------\n");
-+
-+	switch (dm->ic_ip_series) {
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	case PHYDM_IC_JGR3:
-+		phydm_dump_bb_reg_jgr3(dm, &used, output, &out_len);
-+		break;
-+	#endif
-+
-+	#if (ODM_IC_11AC_SERIES_SUPPORT)
-+	case PHYDM_IC_AC:
-+		phydm_dump_bb_reg_ac(dm, &used, output, &out_len);
-+		break;
-+	#endif
-+
-+	#if (ODM_IC_11N_SERIES_SUPPORT)
-+	case PHYDM_IC_N:
-+		phydm_dump_bb_reg_n(dm, &used, output, &out_len);
-+		break;
-+	#endif
-+
-+	default:
-+		break;
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_dump_rf_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 addr = 0;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 reg = 0;
-+
-+	/* @dump RF register */
-+	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+		      "RF-A==========\n");
-+
-+	for (addr = 0; addr <= 0xFF; addr++) {
-+		reg = odm_get_rf_reg(dm, RF_PATH_A, addr, RFREG_MASK);
-+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+			      "0x%02x 0x%05x\n", addr, reg);
-+		}
-+
-+#ifdef PHYDM_COMPILE_ABOVE_2SS
-+	if (dm->rf_type > RF_1T1R) {
-+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+			      "RF-B==========\n");
-+
-+		for (addr = 0; addr <= 0xFF; addr++) {
-+			reg = odm_get_rf_reg(dm, RF_PATH_B, addr, RFREG_MASK);
-+			PDM_VAST_SNPF(out_len, used, output + used,
-+				      out_len - used, "0x%02x 0x%05x\n",
-+				      addr, reg);
-+		}
-+	}
-+#endif
-+
-+#ifdef PHYDM_COMPILE_ABOVE_3SS
-+	if (dm->rf_type > RF_2T2R) {
-+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+			      "RF-C==========\n");
-+
-+		for (addr = 0; addr <= 0xFF; addr++) {
-+			reg = odm_get_rf_reg(dm, RF_PATH_C, addr, RFREG_MASK);
-+			PDM_VAST_SNPF(out_len, used, output + used,
-+				      out_len - used, "0x%02x 0x%05x\n",
-+				      addr, reg);
-+		}
-+	}
-+#endif
-+
-+#ifdef PHYDM_COMPILE_ABOVE_4SS
-+	if (dm->rf_type > RF_3T3R) {
-+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+			      "RF-D==========\n");
-+
-+		for (addr = 0; addr <= 0xFF; addr++) {
-+			reg = odm_get_rf_reg(dm, RF_PATH_D, addr, RFREG_MASK);
-+			PDM_VAST_SNPF(out_len, used, output + used,
-+				      out_len - used, "0x%02x 0x%05x\n",
-+				      addr, reg);
-+		}
-+	}
-+#endif
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_dump_mac_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 addr = 0;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	/* @dump MAC register */
-+	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+		      "MAC==========\n");
-+
-+	for (addr = 0; addr < 0x7ff; addr += 4)
-+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+			      "0x%04x 0x%08x\n",
-+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
-+
-+	for (addr = 0x1000; addr < 0x17ff; addr += 4)
-+		PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+			      "0x%04x 0x%08x\n",
-+			      addr, odm_get_bb_reg(dm, addr, MASKDWORD));
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_dump_reg(void *dm_void, char input[][16], u32 *_used, char *output,
-+		    u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 addr = 0;
-+
-+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "dumpreg {0:all, 1:BB, 2:RF, 3:MAC 4:BB2 for jgr3}\n");
-+		else
-+		#endif
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "dumpreg {0:all, 1:BB, 2:RF, 3:MAC}\n");
-+	} else if (var1[0] == 0) {
-+		phydm_dump_mac_reg(dm, &used, output, &out_len);
-+		phydm_dump_bb_reg(dm, &used, output, &out_len);
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		if (dm->ic_ip_series == PHYDM_IC_JGR3)
-+			phydm_dump_bb_reg2_jgr3(dm, &used, output, &out_len);
-+		#endif
-+
-+		phydm_dump_rf_reg(dm, &used, output, &out_len);
-+	} else if (var1[0] == 1) {
-+		phydm_dump_bb_reg(dm, &used, output, &out_len);
-+	} else if (var1[0] == 2) {
-+		phydm_dump_rf_reg(dm, &used, output, &out_len);
-+	} else if (var1[0] == 3) {
-+		phydm_dump_mac_reg(dm, &used, output, &out_len);
-+	} else if (var1[0] == 4) {
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		if (dm->ic_ip_series == PHYDM_IC_JGR3)
-+			phydm_dump_bb_reg2_jgr3(dm, &used, output, &out_len);
-+		#endif
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_enable_big_jump(void *dm_void, char input[][16], u32 *_used,
-+			   char *output, u32 *_out_len)
-+{
-+#if (RTL8822B_SUPPORT)
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	u32 dm_value[10] = {0};
-+	u8 i, input_idx = 0;
-+	u32 val;
-+
-+	if (!(dm->support_ic_type & ODM_RTL8822B))
-+		return;
-+
-+	for (i = 0; i < 5; i++) {
-+		if (input[i + 1]) {
-+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
-+			input_idx++;
-+		}
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	if (dm_value[0] == 0) {
-+		dm->dm_dig_table.enable_adjust_big_jump = false;
-+
-+		val = (dig_t->big_jump_step3 << 5) |
-+		      (dig_t->big_jump_step2 << 3) |
-+		      dig_t->big_jump_step1;
-+
-+		odm_set_bb_reg(dm, R_0x8c8, 0xfe, val);
-+	} else {
-+		dm->dm_dig_table.enable_adjust_big_jump = true;
-+	}
-+#endif
-+}
-+
-+void phydm_show_rx_rate(void *dm_void, char input[][16], u32 *_used,
-+			char *output, u32 *_out_len)
-+{
-+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8814B_SUPPORT ||\
-+	RTL8195B_SUPPORT || RTL8822C_SUPPORT || RTL8723F_SUPPORT)
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 var1[10] = {0};
-+	char help[] = "-h";
-+	u8 i, input_idx = 0;
-+
-+	for (i = 0; i < 5; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
-+		input_idx++;
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{1: show Rx rate, 0:reset counter}\n");
-+		*_used = used;
-+		*_out_len = out_len;
-+		return;
-+
-+	} else if (var1[0] == 0) {
-+		phydm_reset_rx_rate_distribution(dm);
-+		*_used = used;
-+		*_out_len = out_len;
-+		return;
-+	}
-+
-+	/* @==Show SU Rate====================================================*/
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "=====Rx SU rate Statistics=====\n");
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "[SU][1SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n",
-+		 dbg->num_qry_vht_pkt[0], dbg->num_qry_vht_pkt[1],
-+		 dbg->num_qry_vht_pkt[2], dbg->num_qry_vht_pkt[3],
-+		 dbg->num_qry_vht_pkt[4], dbg->num_qry_vht_pkt[5],
-+		 dbg->num_qry_vht_pkt[6], dbg->num_qry_vht_pkt[7],
-+		 dbg->num_qry_vht_pkt[8], dbg->num_qry_vht_pkt[9]);
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[SU][2SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n",
-+			 dbg->num_qry_vht_pkt[10], dbg->num_qry_vht_pkt[11],
-+			 dbg->num_qry_vht_pkt[12], dbg->num_qry_vht_pkt[13],
-+			 dbg->num_qry_vht_pkt[14], dbg->num_qry_vht_pkt[15],
-+			 dbg->num_qry_vht_pkt[16], dbg->num_qry_vht_pkt[17],
-+			 dbg->num_qry_vht_pkt[18], dbg->num_qry_vht_pkt[19]);
-+	}
-+	#endif
-+	/* @==Show MU Rate====================================================*/
-+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT))
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "=====Rx MU rate Statistics=====\n");
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "[MU][1SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n",
-+		 dbg->num_mu_vht_pkt[0], dbg->num_mu_vht_pkt[1],
-+		 dbg->num_mu_vht_pkt[2], dbg->num_mu_vht_pkt[3],
-+		 dbg->num_mu_vht_pkt[4], dbg->num_mu_vht_pkt[5],
-+		 dbg->num_mu_vht_pkt[6], dbg->num_mu_vht_pkt[7],
-+		 dbg->num_mu_vht_pkt[8], dbg->num_mu_vht_pkt[9]);
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[MU][2SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n",
-+			 dbg->num_mu_vht_pkt[10], dbg->num_mu_vht_pkt[11],
-+			 dbg->num_mu_vht_pkt[12], dbg->num_mu_vht_pkt[13],
-+			 dbg->num_mu_vht_pkt[14], dbg->num_mu_vht_pkt[15],
-+			 dbg->num_mu_vht_pkt[16], dbg->num_mu_vht_pkt[17],
-+			 dbg->num_mu_vht_pkt[18], dbg->num_mu_vht_pkt[19]);
-+	}
-+	#endif
-+#endif
-+	*_used = used;
-+	*_out_len = out_len;
-+#endif
-+}
-+
-+void phydm_per_tone_evm(void *dm_void, char input[][16], u32 *_used,
-+			char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i, j;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 var1[4] = {0};
-+	u32 val, tone_num, round;
-+	s8 rxevm_0, rxevm_1;
-+	s32 avg_num, evm_tone_0[256] = {0}, evm_tone_1[256] = {0};
-+	s32 rxevm_sum_0, rxevm_sum_1;
-+
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		pr_debug("n series not support yet !\n");
-+		return;
-+	}
-+
-+	for (i = 0; i < 4; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
-+	}
-+
-+	avg_num = var1[0];
-+	round = var1[1];
-+
-+	if (!dm->is_linked) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "No Link !!\n");
-+
-+		*_used = used;
-+		*_out_len = out_len;
-+
-+		return;
-+	}
-+
-+	pr_debug("ID=((%d)), BW=((%d)), fc=((CH-%d))\n", dm->curr_station_id,
-+		 20 << *dm->band_width, *dm->channel);
-+	pr_debug("avg_num =((%d)), round =((%d))\n", avg_num, round);
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	watchdog_stop(dm->priv);
-+#endif
-+	for (j = 0; j < round; j++) {
-+		pr_debug("\nround((%d))\n", (j + 1));
-+		if (*dm->band_width == CHANNEL_WIDTH_20) {
-+			for (tone_num = 228; tone_num <= 255; tone_num++) {
-+				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
-+				rxevm_sum_0 = 0;
-+				rxevm_sum_1 = 0;
-+				for (i = 0; i < avg_num; i++) {
-+					val = odm_read_4byte(dm, R_0xf8c);
-+
-+					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
-+					rxevm_0 = (rxevm_0 / 2);
-+					if (rxevm_0 < -63)
-+						rxevm_0 = 0;
-+
-+					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
-+					rxevm_1 = (rxevm_1 / 2);
-+					if (rxevm_1 < -63)
-+						rxevm_1 = 0;
-+					rxevm_sum_0 += rxevm_0;
-+					rxevm_sum_1 += rxevm_1;
-+					ODM_delay_ms(1);
-+				}
-+				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
-+				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
-+				pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n",
-+					 (256 - tone_num), evm_tone_0[tone_num],
-+					 evm_tone_1[tone_num]);
-+			}
-+
-+			for (tone_num = 1; tone_num <= 28; tone_num++) {
-+				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
-+				rxevm_sum_0 = 0;
-+				rxevm_sum_1 = 0;
-+				for (i = 0; i < avg_num; i++) {
-+					val = odm_read_4byte(dm, R_0xf8c);
-+
-+					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
-+					rxevm_0 = (rxevm_0 / 2);
-+					if (rxevm_0 < -63)
-+						rxevm_0 = 0;
-+
-+					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
-+					rxevm_1 = (rxevm_1 / 2);
-+					if (rxevm_1 < -63)
-+						rxevm_1 = 0;
-+					rxevm_sum_0 += rxevm_0;
-+					rxevm_sum_1 += rxevm_1;
-+					ODM_delay_ms(1);
-+				}
-+				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
-+				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
-+				pr_debug("Tone(%-3d) RXEVM(1ss/2ss)=%d, %d\n",
-+					 tone_num, evm_tone_0[tone_num],
-+					 evm_tone_1[tone_num]);
-+			}
-+		} else if (*dm->band_width == CHANNEL_WIDTH_40) {
-+			for (tone_num = 198; tone_num <= 254; tone_num++) {
-+				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
-+				rxevm_sum_0 = 0;
-+				rxevm_sum_1 = 0;
-+				for (i = 0; i < avg_num; i++) {
-+					val = odm_read_4byte(dm, R_0xf8c);
-+
-+					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
-+					rxevm_0 = (rxevm_0 / 2);
-+					if (rxevm_0 < -63)
-+						rxevm_0 = 0;
-+
-+					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
-+					rxevm_1 = (rxevm_1 / 2);
-+					if (rxevm_1 < -63)
-+						rxevm_1 = 0;
-+
-+					rxevm_sum_0 += rxevm_0;
-+					rxevm_sum_1 += rxevm_1;
-+					ODM_delay_ms(1);
-+				}
-+				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
-+				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
-+				pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n",
-+					 (256 - tone_num), evm_tone_0[tone_num],
-+					 evm_tone_1[tone_num]);
-+			}
-+
-+			for (tone_num = 2; tone_num <= 58; tone_num++) {
-+				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
-+				rxevm_sum_0 = 0;
-+				rxevm_sum_1 = 0;
-+				for (i = 0; i < avg_num; i++) {
-+					val = odm_read_4byte(dm, R_0xf8c);
-+
-+					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
-+					rxevm_0 = (rxevm_0 / 2);
-+					if (rxevm_0 < -63)
-+						rxevm_0 = 0;
-+
-+					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
-+					rxevm_1 = (rxevm_1 / 2);
-+					if (rxevm_1 < -63)
-+						rxevm_1 = 0;
-+					rxevm_sum_0 += rxevm_0;
-+					rxevm_sum_1 += rxevm_1;
-+					ODM_delay_ms(1);
-+				}
-+				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
-+				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
-+				pr_debug("Tone(%-3d) RXEVM(1ss/2ss)=%d, %d\n",
-+					 tone_num, evm_tone_0[tone_num],
-+					 evm_tone_1[tone_num]);
-+			}
-+		} else if (*dm->band_width == CHANNEL_WIDTH_80) {
-+			for (tone_num = 134; tone_num <= 254; tone_num++) {
-+				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
-+				rxevm_sum_0 = 0;
-+				rxevm_sum_1 = 0;
-+				for (i = 0; i < avg_num; i++) {
-+					val = odm_read_4byte(dm, R_0xf8c);
-+
-+					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
-+					rxevm_0 = (rxevm_0 / 2);
-+					if (rxevm_0 < -63)
-+						rxevm_0 = 0;
-+
-+					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
-+					rxevm_1 = (rxevm_1 / 2);
-+					if (rxevm_1 < -63)
-+						rxevm_1 = 0;
-+					rxevm_sum_0 += rxevm_0;
-+					rxevm_sum_1 += rxevm_1;
-+					ODM_delay_ms(1);
-+				}
-+				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
-+				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
-+				pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n",
-+					 (256 - tone_num), evm_tone_0[tone_num],
-+					 evm_tone_1[tone_num]);
-+			}
-+
-+			for (tone_num = 2; tone_num <= 122; tone_num++) {
-+				odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num);
-+				rxevm_sum_0 = 0;
-+				rxevm_sum_1 = 0;
-+				for (i = 0; i < avg_num; i++) {
-+					val = odm_read_4byte(dm, R_0xf8c);
-+
-+					rxevm_0 = (s8)((val & MASKBYTE2) >> 16);
-+					rxevm_0 = (rxevm_0 / 2);
-+					if (rxevm_0 < -63)
-+						rxevm_0 = 0;
-+
-+					rxevm_1 = (s8)((val & MASKBYTE3) >> 24);
-+					rxevm_1 = (rxevm_1 / 2);
-+					if (rxevm_1 < -63)
-+						rxevm_1 = 0;
-+					rxevm_sum_0 += rxevm_0;
-+					rxevm_sum_1 += rxevm_1;
-+					ODM_delay_ms(1);
-+				}
-+				evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num);
-+				evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num);
-+				pr_debug("Tone(%-3d) RXEVM (1ss/2ss)=%d, %d\n",
-+					 tone_num, evm_tone_0[tone_num],
-+					 evm_tone_1[tone_num]);
-+			}
-+		}
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_bw_ch_adjust(void *dm_void, char input[][16],
-+			u32 *_used, char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i;
-+	boolean is_enable_dbg_mode;
-+	u8 central_ch, primary_ch_idx;
-+	enum channel_width bw;
-+
-+#ifdef PHYDM_COMMON_API_SUPPORT
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{en} {CH} {pr_ch_idx 1/2/3/4/9/10} {0:20M,1:40M,2:80M}\n");
-+		goto out;
-+	}
-+
-+	if (!(dm->support_ic_type & CMN_API_SUPPORT_IC)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Not support this API\n");
-+		goto out;
-+	}
-+
-+	for (i = 0; i < 4; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
-+	}
-+
-+	is_enable_dbg_mode = (boolean)var1[0];
-+	central_ch = (u8)var1[1];
-+	primary_ch_idx = (u8)var1[2];
-+	bw = (enum channel_width)var1[3];
-+
-+	if (is_enable_dbg_mode) {
-+		dm->is_disable_phy_api = false;
-+		phydm_api_switch_bw_channel(dm, central_ch, primary_ch_idx, bw);
-+		dm->is_disable_phy_api = true;
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "central_ch = %d, primary_ch_idx = %d, bw = %d\n",
-+			 central_ch, primary_ch_idx, bw);
-+	}
-+out:
-+#endif
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_ext_rf_element_ctrl(void *dm_void, char input[][16], u32 *_used,
-+			       char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 val[10] = {0};
-+	u8 i = 0, input_idx = 0;
-+
-+	for (i = 0; i < 5; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]);
-+		input_idx++;
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	if (val[0] == 1) /*@ext switch*/ {
-+		phydm_set_ext_switch(dm, val[1]);
-+	}
-+}
-+
-+void phydm_print_dbgport(void *dm_void, char input[][16], u32 *_used,
-+			 char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 dbg_port_value = 0;
-+	u8 val[32];
-+	u8 tmp = 0;
-+	u8 i;
-+
-+	if (strcmp(input[1], help) == 0) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{dbg_port_idx}\n");
-+		goto out;
-+	}
-+
-+	PHYDM_SSCANF(input[1], DCMD_HEX, &var1[0]);
-+
-+	dm->debug_components |= ODM_COMP_API;
-+	if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, var1[0])) {
-+		dbg_port_value = phydm_get_bb_dbg_port_val(dm);
-+		phydm_release_bb_dbg_port(dm);
-+
-+		for (i = 0; i < 32; i++)
-+			val[i] = (u8)((dbg_port_value & BIT(i)) >> i);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Dbg Port[0x%x] = ((0x%x))\n", var1[0],
-+			 dbg_port_value);
-+
-+		for (i = 4; i != 0; i--) {
-+			tmp = 8 * (i - 1);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "val[%d:%d] = 8b'%d %d %d %d %d %d %d %d\n",
-+				 tmp + 7, tmp, val[tmp + 7], val[tmp + 6],
-+				 val[tmp + 5], val[tmp + 4], val[tmp + 3],
-+				 val[tmp + 2], val[tmp + 1], val[tmp + 0]);
-+		}
-+	}
-+	dm->debug_components &= (~ODM_COMP_API);
-+out:
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_get_anapar_table(void *dm_void, u32 *_used, char *output,
-+			    u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	enum rf_path i = RF_PATH_A;
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
-+		return;
-+
-+	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+		      "------ Analog parameters start ------\n");
-+
-+	for (i = RF_PATH_A; i < (enum rf_path)dm->num_rf_path; i++)
-+		phydm_get_per_path_anapar_jgr3(dm, i, &used, output, &out_len);
-+#endif
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_get_csi_table(void *dm_void, u32 *_used, char *output,
-+			    u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
-+		return;
-+
-+	PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
-+		      "------ CSI Table Parsing start ------\n");
-+
-+	phydm_get_csi_table_jgr3(dm, &used, output, &out_len);
-+#endif
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_dd_dbg_dump(void *dm_void, char input[][16], u32 *_used,
-+		       char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "dump: {1}\n");
-+		return;
-+	} else if (var1[0] == 1) {
-+		/*[Reg]*/
-+		phydm_dump_mac_reg(dm, &used, output, &out_len);
-+		phydm_dump_bb_reg(dm, &used, output, &out_len);
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		if (dm->ic_ip_series == PHYDM_IC_JGR3)
-+			phydm_dump_bb_reg2_jgr3(dm, &used, output, &out_len);
-+		#endif
-+
-+		phydm_dump_rf_reg(dm, &used, output, &out_len);
-+		/*[Dbg Port]*/
-+		#ifdef PHYDM_AUTO_DEGBUG
-+		phydm_dbg_port_dump(dm, &used, output, &out_len);
-+		#endif
-+		/*[Analog Parameters]*/
-+		phydm_get_anapar_table(dm, &used, output, &out_len);
-+	}
-+}
-+
-+void phydm_nss_hitogram_mp(void *dm_void, enum PDM_RATE_TYPE rate_type,
-+			   u32 *_used, char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	char buf[PHYDM_SNPRINT_SIZE] = {0};
-+	u16 buf_size = PHYDM_SNPRINT_SIZE;
-+	u16 h_size = PHY_HIST_SIZE;
-+	u16 *evm_hist = &dbg_s->evm_1ss_hist[0];
-+	u16 *snr_hist = &dbg_s->snr_1ss_hist[0];
-+	u8 i = 0;
-+	u8 ss = phydm_rate_type_2_num_ss(dm, rate_type);
-+
-+	if (rate_type == PDM_OFDM) {
-+		phydm_print_hist_2_buf(dm, dbg_s->evm_ofdm_hist, PHY_HIST_SIZE,
-+				       buf, buf_size);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "%-14s=%s\n", "[OFDM][EVM]", buf);
-+
-+		phydm_print_hist_2_buf(dm, dbg_s->snr_ofdm_hist, PHY_HIST_SIZE,
-+				       buf, buf_size);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "%-14s=%s\n", "[OFDM][SNR]", buf);
-+
-+		*_used = used;
-+		*_out_len = out_len;
-+		return;
-+	}
-+
-+	for (i = 0; i < ss; i++) {
-+		if (rate_type == PDM_1SS) {
-+			evm_hist = &dbg_s->evm_1ss_hist[0];
-+			snr_hist = &dbg_s->snr_1ss_hist[0];
-+		} else if (rate_type == PDM_2SS) {
-+			#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+			evm_hist = &dbg_s->evm_2ss_hist[i][0];
-+			snr_hist = &dbg_s->snr_2ss_hist[i][0];
-+			#endif
-+		} else if (rate_type == PDM_3SS) {
-+			#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+			evm_hist = &dbg_s->evm_3ss_hist[i][0];
-+			snr_hist = &dbg_s->snr_3ss_hist[i][0];
-+			#endif
-+		} else if (rate_type == PDM_4SS) {
-+			#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+			evm_hist = &dbg_s->evm_4ss_hist[i][0];
-+			snr_hist = &dbg_s->snr_4ss_hist[i][0];
-+			#endif
-+		}
-+
-+		phydm_print_hist_2_buf(dm, evm_hist, h_size, buf, buf_size);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[%d-SS][EVM][%d]=%s\n", ss, i, buf);
-+		phydm_print_hist_2_buf(dm, snr_hist, h_size, buf, buf_size);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[%d-SS][SNR][%d]=%s\n",  ss, i, buf);
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_mp_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
-+		  u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
-+	struct phydm_phystatus_avg *dbg_avg = &dbg_i->phystatus_statistic_avg;
-+	char *rate_type = NULL;
-+	u8 tmp_rssi_avg[4];
-+	u8 tmp_snr_avg[4];
-+	u8 tmp_evm_avg[4];
-+	u32 tmp_cnt = 0;
-+	char buf[PHYDM_SNPRINT_SIZE] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 var1[10] = {0};
-+	u16 buf_size = PHYDM_SNPRINT_SIZE;
-+	u16 th_size = PHY_HIST_SIZE - 1;
-+	u8 i = 0;
-+
-+	if (!(*dm->mp_mode))
-+		return;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "BW=((%d)), fc=((CH-%d))\n",
-+		 20 << *dm->band_width, *dm->channel);
-+
-+	/*@===[PHY Histogram]================================================*/
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "[PHY Histogram] ==============>\n");
-+	/*@===[Threshold]===*/
-+	phydm_print_hist_2_buf(dm, dbg_i->evm_hist_th, th_size, buf, buf_size);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "%-16s=%s\n", "[EVM_TH]", buf);
-+	phydm_print_hist_2_buf(dm, dbg_i->snr_hist_th, th_size, buf, buf_size);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "%-16s=%s\n", "[SNR_TH]", buf);
-+	/*@===[OFDM]===*/
-+	phydm_nss_hitogram_mp(dm, PDM_OFDM, &used, output, &out_len);
-+	/*@===[1-SS]===*/
-+	phydm_nss_hitogram_mp(dm, PDM_1SS, &used, output, &out_len);
-+	/*@===[2-SS]===*/
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
-+		phydm_nss_hitogram_mp(dm, PDM_2SS, &used, output, &out_len);
-+	#endif
-+	/*@===[3-SS]===*/
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS)
-+		phydm_nss_hitogram_mp(dm, PDM_3SS, &used, output, &out_len);
-+	#endif
-+	/*@===[4-SS]===*/
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS)
-+		phydm_nss_hitogram_mp(dm, PDM_4SS, &used, output, &out_len);
-+	#endif
-+	/*@===[PHY Avg]======================================================*/
-+	phydm_get_avg_phystatus_val(dm);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "[PHY Avg] ==============>\n");
-+
-+	phydm_get_avg_phystatus_val(dm);
-+
-+	switch (dm->num_rf_path) {
-+#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	case 4:
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n",
-+			 "[Beacon]", dbg_s->rssi_beacon_cnt,
-+			 dbg_avg->rssi_beacon_avg[0],
-+			 dbg_avg->rssi_beacon_avg[1],
-+			 dbg_avg->rssi_beacon_avg[2],
-+			 dbg_avg->rssi_beacon_avg[3]);
-+		break;
-+#endif
-+#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	case 3:
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n",
-+			 "[Beacon]", dbg_s->rssi_beacon_cnt,
-+			 dbg_avg->rssi_beacon_avg[0],
-+			 dbg_avg->rssi_beacon_avg[1],
-+			 dbg_avg->rssi_beacon_avg[2]);
-+		break;
-+#endif
-+#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	case 2:
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n",
-+			 "[Beacon]", dbg_s->rssi_beacon_cnt,
-+			 dbg_avg->rssi_beacon_avg[0],
-+			 dbg_avg->rssi_beacon_avg[1]);
-+		break;
-+#endif
-+	default:
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n",
-+			 "[Beacon]", dbg_s->rssi_beacon_cnt,
-+			 dbg_avg->rssi_beacon_avg[0]);
-+		break;
-+	}
-+
-+	switch (dm->num_rf_path) {
-+#ifdef PHYSTS_3RD_TYPE_SUPPORT
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	case 4:
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n",
-+			 "[CCK]", dbg_s->rssi_cck_cnt,
-+			 dbg_avg->rssi_cck_avg,
-+			 dbg_avg->rssi_cck_avg_abv_2ss[0],
-+			 dbg_avg->rssi_cck_avg_abv_2ss[1],
-+			 dbg_avg->rssi_cck_avg_abv_2ss[2]);
-+		break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	case 3:
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n",
-+			 "[CCK]", dbg_s->rssi_cck_cnt,
-+			 dbg_avg->rssi_cck_avg,
-+			 dbg_avg->rssi_cck_avg_abv_2ss[0],
-+			 dbg_avg->rssi_cck_avg_abv_2ss[1]);
-+		break;
-+	#endif
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	case 2:
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n",
-+			 "[CCK]", dbg_s->rssi_cck_cnt,
-+			 dbg_avg->rssi_cck_avg,
-+			 dbg_avg->rssi_cck_avg_abv_2ss[0]);
-+		break;
-+	#endif
-+#endif
-+	default:
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n",
-+			 "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg);
-+		break;
-+	}
-+
-+	for (i = 0; i <= 4; i++) {
-+		if (i > dm->num_rf_path)
-+			break;
-+
-+		odm_memory_set(dm, tmp_rssi_avg, 0, 4);
-+		odm_memory_set(dm, tmp_snr_avg, 0, 4);
-+		odm_memory_set(dm, tmp_evm_avg, 0, 4);
-+
-+		switch (i) {
-+		#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+		case 4:
-+			rate_type = "[4-SS]";
-+			tmp_cnt = dbg_s->rssi_4ss_cnt;
-+			odm_move_memory(dm, tmp_rssi_avg,
-+					dbg_avg->rssi_4ss_avg, dm->num_rf_path);
-+			odm_move_memory(dm, tmp_snr_avg,
-+					dbg_avg->snr_4ss_avg, dm->num_rf_path);
-+			odm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_4ss_avg,
-+					4);
-+			break;
-+		#endif
-+		#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+		case 3:
-+			rate_type = "[3-SS]";
-+			tmp_cnt = dbg_s->rssi_3ss_cnt;
-+			odm_move_memory(dm, tmp_rssi_avg,
-+					dbg_avg->rssi_3ss_avg, dm->num_rf_path);
-+			odm_move_memory(dm, tmp_snr_avg,
-+					dbg_avg->snr_3ss_avg, dm->num_rf_path);
-+			odm_move_memory(dm, tmp_evm_avg,
-+					dbg_avg->evm_3ss_avg, 3);
-+			break;
-+		#endif
-+		#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+		case 2:
-+			rate_type = "[2-SS]";
-+			tmp_cnt = dbg_s->rssi_2ss_cnt;
-+			odm_move_memory(dm, tmp_rssi_avg,
-+					dbg_avg->rssi_2ss_avg, dm->num_rf_path);
-+			odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_2ss_avg,
-+					dm->num_rf_path);
-+			odm_move_memory(dm, tmp_evm_avg,
-+					dbg_avg->evm_2ss_avg, 2);
-+			break;
-+		#endif
-+		case 1:
-+			rate_type = "[1-SS]";
-+			tmp_cnt = dbg_s->rssi_1ss_cnt;
-+			odm_move_memory(dm, tmp_rssi_avg,
-+					dbg_avg->rssi_1ss_avg, dm->num_rf_path);
-+			odm_move_memory(dm, tmp_snr_avg,
-+					dbg_avg->snr_1ss_avg, dm->num_rf_path);
-+			odm_move_memory(dm, tmp_evm_avg,
-+					&dbg_avg->evm_1ss_avg, 1);
-+			break;
-+		default:
-+			rate_type = "[L-OFDM]";
-+			tmp_cnt = dbg_s->rssi_ofdm_cnt;
-+			odm_move_memory(dm, tmp_rssi_avg,
-+					dbg_avg->rssi_ofdm_avg,
-+					dm->num_rf_path);
-+			odm_move_memory(dm, tmp_snr_avg,
-+					dbg_avg->snr_ofdm_avg, dm->num_rf_path);
-+			odm_move_memory(dm, tmp_evm_avg,
-+					&dbg_avg->evm_ofdm_avg, 1);
-+			break;
-+		}
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			   "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d, -%.2d}\n",
-+			    rate_type, tmp_cnt,
-+			    tmp_rssi_avg[0], tmp_rssi_avg[1],
-+			    tmp_rssi_avg[2], tmp_rssi_avg[3],
-+			    tmp_snr_avg[0], tmp_snr_avg[1],
-+			    tmp_snr_avg[2], tmp_snr_avg[3],
-+			    tmp_evm_avg[0], tmp_evm_avg[1],
-+			    tmp_evm_avg[2], tmp_evm_avg[3]);
-+	}
-+
-+	phydm_reset_phystatus_statistic(dm);
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "rxsc_idx {Legacy, 20, 40, 80} = {%d, %d, %d, %d}\n",
-+		 dm->rxsc_l, dm->rxsc_20, dm->rxsc_40, dm->rxsc_80);
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_reg_monitor(void *dm_void, char input[][16], u32 *_used,
-+		       char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	boolean en_mntr = false;
-+	u8 i = 0;
-+
-+	for (i = 0; i < 7; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
-+	}
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "reg_mntr {en} {0:all, 1:BB, 2:RF, 3:MAC 4:1/2/4 byte}\n");
-+	} else {
-+		if (var1[0] == 1)
-+			en_mntr = true;
-+		else
-+			en_mntr = false;
-+
-+		if (var1[1] == 0) {
-+			dm->en_reg_mntr_bb = en_mntr;
-+			dm->en_reg_mntr_rf = en_mntr;
-+			dm->en_reg_mntr_mac = en_mntr;
-+			dm->en_reg_mntr_byte = en_mntr;
-+		} else if (var1[1] == 1) {
-+			dm->en_reg_mntr_bb = en_mntr;
-+		} else if (var1[1] == 2) {
-+			dm->en_reg_mntr_rf = en_mntr;
-+		} else if (var1[1] == 3) {
-+			dm->en_reg_mntr_mac = en_mntr;
-+		} else if (var1[1] == 4) {
-+			dm->en_reg_mntr_byte = en_mntr;
-+		}
-+	}
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "en: BB:%d, RF:%d, MAC:%d, byte:%d\n", dm->en_reg_mntr_bb,
-+		 dm->en_reg_mntr_rf, dm->en_reg_mntr_mac, dm->en_reg_mntr_byte);
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#if (RTL8822C_SUPPORT)
-+u16 phydm_get_agc_rf_gain(void *dm_void, boolean is_mod, u8 tab, u8 mp_gain_i)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u16 rf_gain = 0x0;
-+
-+	if (is_mod)
-+		rf_gain = dm->agc_rf_gain[tab][mp_gain_i];
-+	else
-+		rf_gain = dm->agc_rf_gain_ori[tab][mp_gain_i];
-+
-+	return rf_gain;
-+}
-+#endif
-+
-+void phydm_get_rxagc_table_dbg(void *dm_void, char input[][16], u32 *_used,
-+			       char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 tab = 0;
-+	boolean is_modified = false;
-+	u8 mp_gain = 0;
-+	u16 rf_gain = 0;
-+	u8 i = 0;
-+
-+#if (RTL8822C_SUPPORT)
-+	if (!(dm->support_ic_type & ODM_RTL8822C))
-+		return;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "get rxagc table : {0:ori, 1:modified} {table:0~15} {mp_gain_idx:0~63, all:0xff}\n");
-+	} else {
-+		for (i = 0; i < 3; i++) {
-+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
-+		}
-+
-+		is_modified = (boolean)var1[0];
-+		tab = (u8)var1[1];
-+		mp_gain = (u8)var1[2];
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "agc_table_cnt:%d, is_agc_tab_pos_shift:%d, agc_table_shift:%d\n",
-+			 dm->agc_table_cnt, dm->is_agc_tab_pos_shift,
-+			 dm->agc_table_shift);
-+
-+		if (mp_gain == 0xff) {
-+			for (i = 0; i < 64; i++) {
-+				rf_gain = phydm_get_agc_rf_gain(dm, is_modified,
-+								tab, i);
-+
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used,
-+					 "agc_table:%d, mp_gain_idx:0x%x, rf_gain_idx:0x%x\n",
-+					 tab, i, rf_gain);
-+			}
-+		} else {
-+			rf_gain = phydm_get_agc_rf_gain(dm, is_modified, tab,
-+							mp_gain);
-+
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "agc_table:%d, mp_gain_idx:0x%x, rf_gain_idx:0x%x\n",
-+				 tab, mp_gain, rf_gain);
-+		}
-+	}
-+#endif
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_shift_rxagc_table_dbg(void *dm_void, char input[][16], u32 *_used,
-+				 char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i = 0;
-+	u16 value_db = 0;
-+
-+#if (RTL8822C_SUPPORT)
-+	if (!(dm->support_ic_type & ODM_RTL8822C))
-+		return;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "shift rxagc table : {0:-, 1:+} {value(0~63, unit:2dB)}\n");
-+	} else {
-+		for (i = 0; i < 3; i++) {
-+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
-+				     &var1[i]);
-+		}
-+
-+		if ((u8)var1[1] > 63) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Do not enter the value larger than 63!\n");
-+		} else {
-+			phydm_shift_rxagc_table(dm, (boolean)var1[0],
-+						(u8)var1[1]);
-+
-+			value_db = (u8)var1[1] << 1;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "shift %s%d dB gain\n",
-+				 (((boolean)var1[0]) ? "+" : "-"), value_db);
-+		}
-+	}
-+#endif
-+}
-+
-+#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT)
-+void phydm_spur_detect_dbg(void *dm_void, char input[][16], u32 *_used,
-+			   char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 i;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{0: Auto spur detect(NBI+CSI), 1:NBI always ON/ CSI Auto,");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "2: CSI always On/ NBI Auto, 3: Disable, 4: CSI & NBI ON}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{If CSI always ON (Mode 2 or 4) -> CSI wgt manual(0~7)}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{5: Adjust CSI weight threshold} {0:-,1:+} {th offset}\n");
-+	} else {
-+		for (i = 0; i < 10; i++) {
-+			if (input[i + 1])
-+				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
-+					     &var1[i]);
-+		}
-+
-+		if (var1[0] == 1) {
-+			dm->dsde_sel = DET_NBI;
-+		} else if (var1[0] == 2) {
-+			dm->dsde_sel = DET_CSI;
-+		} else if (var1[0] == 3) {
-+			dm->dsde_sel = DET_DISABLE;
-+		} else if (var1[0] == 4) {
-+			dm->dsde_sel = DET_CSI_NBI_EN;
-+		} else if (var1[0] == 0) {
-+			dm->dsde_sel = DET_AUTO;
-+		} else if (var1[0] == 5) {
-+			if (var1[1] == 0)
-+				for (i = 0; i < 5; i++)
-+					dm->csi_wgt_th_db[i] -= (u8)var1[2];
-+			else if (var1[1] == 1)
-+				for (i = 0; i < 5; i++)
-+					dm->csi_wgt_th_db[i] += (u8)var1[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used, "current csi weight threshold:\n");
-+			for (i = 0; i < 5; i++)
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used, "----%2d",
-+					 dm->csi_wgt_th_db[i]);
-+			PDM_SNPF(out_len, used, output + used, out_len - used, "\n");
-+			for (i = 0; i < 5; i++)
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used, "--%d--|", i);
-+			PDM_SNPF(out_len, used, output + used, out_len - used, "\n");
-+		} else {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Spur detection mode invalid!\n");
-+			return;
-+		}
-+		if (var1[0] < 5)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "spur detect mode = %d\n", dm->dsde_sel);
-+
-+		if (dm->dsde_sel == DET_CSI_NBI_EN) {
-+			if (var1[1] < 8) {
-+				dm->csi_wgt = (u8)var1[1];
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used, "CSI wgt %d\n",
-+					 dm->csi_wgt);
-+			} else {
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used,
-+					 "CSI wgt setting invalid. Please set the correct wgt!\n");
-+				return;
-+			}
-+		}
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+#endif
-+
-+struct phydm_command {
-+	char name[16];
-+	u8 id;
-+};
-+
-+enum PHYDM_CMD_ID {
-+	PHYDM_HELP,
-+	PHYDM_DEMO,
-+	PHYDM_RF_CMD,
-+	PHYDM_DIG,
-+	PHYDM_RA,
-+	PHYDM_PROFILE,
-+	PHYDM_ANTDIV,
-+	PHYDM_PATHDIV,
-+	PHYDM_DEBUG,
-+	PHYDM_MP_DEBUG,
-+	PHYDM_FW_DEBUG,
-+	PHYDM_SUPPORT_ABILITY,
-+	PHYDM_GET_TXAGC,
-+	PHYDM_SET_TXAGC,
-+	PHYDM_SMART_ANT,
-+	PHYDM_CH_BW,
-+	PHYDM_TRX_PATH,
-+	PHYDM_LA_MODE,
-+	PHYDM_DUMP_REG,
-+	PHYDM_AUTO_DBG,
-+	PHYDM_DD_DBG,
-+	PHYDM_BIG_JUMP,
-+	PHYDM_SHOW_RXRATE,
-+	PHYDM_NBI_EN,
-+	PHYDM_CSI_MASK_EN,
-+	PHYDM_DFS_DEBUG,
-+	PHYDM_DFS_HIST,
-+	PHYDM_NHM,
-+	PHYDM_CLM,
-+	PHYDM_FAHM,
-+	PHYDM_ENV_MNTR,
-+	PHYDM_BB_INFO,
-+	//PHYDM_TXBF,
-+	PHYDM_H2C,
-+	PHYDM_EXT_RF_E_CTRL,
-+	PHYDM_ADAPTIVE_SOML,
-+	PHYDM_PSD,
-+	PHYDM_DEBUG_PORT,
-+	PHYDM_DIS_HTSTF_CONTROL,
-+	PHYDM_CFO_TRK,
-+	PHYDM_ADAPTIVITY_DEBUG,
-+	PHYDM_DIS_DYM_ANT_WEIGHTING,
-+	PHYDM_FORECE_PT_STATE,
-+	PHYDM_STA_INFO,
-+	PHYDM_PAUSE_FUNC,
-+	PHYDM_PER_TONE_EVM,
-+	PHYDM_DYN_TXPWR,
-+	PHYDM_LNA_SAT,
-+	PHYDM_ANAPAR,
-+	PHYDM_CCK_RX_PATHDIV,
-+	PHYDM_BEAM_FORMING,
-+	PHYDM_REG_MONITOR,
-+#if RTL8814B_SUPPORT
-+	PHYDM_SPUR_DETECT,
-+#endif
-+	PHYDM_PHY_STATUS,
-+	PHYDM_CRC32_CNT,
-+	PHYDM_DCC,
-+#ifdef PHYDM_HW_IGI
-+	PHYDM_HWIGI,
-+#endif
-+#ifdef PHYDM_HW_SWITCH_AGC_TAB
-+	PHYDM_HW_AGCTAB,
-+#endif
-+	PHYDM_PMAC_TX,
-+	PHYDM_GET_RXAGC,
-+	PHYDM_SHIFT_RXAGC,
-+	PHYDM_IFS_CLM,
-+	PHYDM_ENHANCE_MNTR,
-+	PHYDM_CSI_DBG
-+};
-+
-+struct phydm_command phy_dm_ary[] = {
-+	{"-h", PHYDM_HELP}, /*@do not move this element to other position*/
-+	{"demo", PHYDM_DEMO}, /*@do not move this element to other position*/
-+	{"rf", PHYDM_RF_CMD},
-+	{"dig", PHYDM_DIG},
-+	{"ra", PHYDM_RA},
-+	{"profile", PHYDM_PROFILE},
-+	{"antdiv", PHYDM_ANTDIV},
-+	{"pathdiv", PHYDM_PATHDIV},
-+	{"dbg", PHYDM_DEBUG},
-+	{"mp_dbg", PHYDM_MP_DEBUG},
-+	{"fw_dbg", PHYDM_FW_DEBUG},
-+	{"ability", PHYDM_SUPPORT_ABILITY},
-+	{"get_txagc", PHYDM_GET_TXAGC},
-+	{"set_txagc", PHYDM_SET_TXAGC},
-+	{"smtant", PHYDM_SMART_ANT},
-+	{"ch_bw", PHYDM_CH_BW},
-+	{"trxpath", PHYDM_TRX_PATH},
-+	{"lamode", PHYDM_LA_MODE},
-+	{"dumpreg", PHYDM_DUMP_REG},
-+	{"auto_dbg", PHYDM_AUTO_DBG},
-+	{"dd_dbg", PHYDM_DD_DBG},
-+	{"bigjump", PHYDM_BIG_JUMP},
-+	{"rxrate", PHYDM_SHOW_RXRATE},
-+	{"nbi", PHYDM_NBI_EN},
-+	{"csi_mask", PHYDM_CSI_MASK_EN},
-+	{"dfs", PHYDM_DFS_DEBUG},
-+	{"dfs_hist", PHYDM_DFS_HIST},
-+	{"nhm", PHYDM_NHM},
-+	{"clm", PHYDM_CLM},
-+	{"fahm", PHYDM_FAHM},
-+	{"env_mntr", PHYDM_ENV_MNTR},
-+	{"bbinfo", PHYDM_BB_INFO},
-+	/*{"txbf", PHYDM_TXBF},*/
-+	{"h2c", PHYDM_H2C},
-+	{"ext_rfe", PHYDM_EXT_RF_E_CTRL},
-+	{"soml", PHYDM_ADAPTIVE_SOML},
-+	{"psd", PHYDM_PSD},
-+	{"dbgport", PHYDM_DEBUG_PORT},
-+	{"dis_htstf", PHYDM_DIS_HTSTF_CONTROL},
-+	{"cfo_trk", PHYDM_CFO_TRK},
-+	{"adapt_debug", PHYDM_ADAPTIVITY_DEBUG},
-+	{"dis_dym_ant_wgt", PHYDM_DIS_DYM_ANT_WEIGHTING},
-+	{"force_pt_state", PHYDM_FORECE_PT_STATE},
-+	{"sta_info", PHYDM_STA_INFO},
-+	{"pause", PHYDM_PAUSE_FUNC},
-+	{"evm", PHYDM_PER_TONE_EVM},
-+	{"dyn_txpwr", PHYDM_DYN_TXPWR},
-+	{"lna_sat", PHYDM_LNA_SAT},
-+	{"anapar", PHYDM_ANAPAR},
-+	{"cck_rx_pathdiv", PHYDM_CCK_RX_PATHDIV},
-+	{"bf", PHYDM_BEAM_FORMING},
-+	{"reg_mntr", PHYDM_REG_MONITOR},
-+#if RTL8814B_SUPPORT
-+	{"spur_detect", PHYDM_SPUR_DETECT},
-+#endif
-+	{"physts", PHYDM_PHY_STATUS},
-+	{"crc32_cnt", PHYDM_CRC32_CNT},
-+#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
-+	{"pmac_tx", PHYDM_PMAC_TX},
-+#endif
-+#ifdef PHYDM_HW_IGI
-+	{"hwigi", PHYDM_HWIGI},
-+#endif
-+#ifdef PHYDM_HW_SWITCH_AGC_TAB
-+	{"hw_agctab", PHYDM_HW_AGCTAB},
-+#endif
-+	{"dcc", PHYDM_DCC},
-+	{"get_rxagc", PHYDM_GET_RXAGC},
-+	{"shift_rxagc", PHYDM_SHIFT_RXAGC},
-+	{"ifs_clm", PHYDM_IFS_CLM},
-+	{"enh_mntr", PHYDM_ENHANCE_MNTR},
-+	{"csi_dbg", PHYDM_CSI_DBG}
-+	};
-+
-+#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
-+
-+void phydm_cmd_parser(struct dm_struct *dm, char input[][MAX_ARGV],
-+		      u32 input_num, u8 flag, char *output, u32 out_len)
-+{
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+	u32 used = 0;
-+	u8 id = 0;
-+	u32 var1[10] = {0};
-+	u32 i;
-+	u32 phydm_ary_size = sizeof(phy_dm_ary) / sizeof(struct phydm_command);
-+
-+	if (flag == 0) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "GET, nothing to print\n");
-+		return;
-+	}
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used, "\n");
-+
-+	/* Parsing Cmd ID */
-+	if (input_num) {
-+		for (i = 0; i < phydm_ary_size; i++) {
-+			if (strcmp(phy_dm_ary[i].name, input[0]) == 0) {
-+				id = phy_dm_ary[i].id;
-+				break;
-+			}
-+		}
-+		if (i == phydm_ary_size) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "PHYDM command not found!\n");
-+			return;
-+		}
-+	}
-+
-+	switch (id) {
-+	case PHYDM_HELP: {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "BB cmd ==>\n");
-+
-+		for (i = 0; i < phydm_ary_size - 2; i++)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "  %-5d: %s\n", i, phy_dm_ary[i + 2].name);
-+	} break;
-+
-+	case PHYDM_DEMO: { /*@echo demo 10 0x3a z abcde >cmd*/
-+		u32 directory = 0;
-+
-+		#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
-+		char char_temp;
-+		#else
-+		u32 char_temp = ' ';
-+		#endif
-+
-+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Decimal value = %d\n", directory);
-+		PHYDM_SSCANF(input[2], DCMD_HEX, &directory);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Hex value = 0x%x\n", directory);
-+		PHYDM_SSCANF(input[3], DCMD_CHAR, &char_temp);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Char = %c\n", char_temp);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "String = %s\n", input[4]);
-+	} break;
-+	case PHYDM_RF_CMD:
-+		halrf_cmd_parser(dm, input, &used, output, &out_len, input_num);
-+		break;
-+
-+	case PHYDM_DIG:
-+		phydm_dig_debug(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_RA:
-+		phydm_ra_debug(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_ANTDIV:
-+		#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+		phydm_antdiv_debug(dm, input, &used, output, &out_len);
-+		#endif
-+		break;
-+
-+	case PHYDM_PATHDIV:
-+		#if (defined(CONFIG_PATH_DIVERSITY))
-+		phydm_pathdiv_debug(dm, input, &used, output, &out_len);
-+		#endif
-+		break;
-+
-+	case PHYDM_DEBUG:
-+		phydm_debug_trace(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_MP_DEBUG:
-+		phydm_mp_dbg(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_FW_DEBUG:
-+		phydm_fw_debug_trace(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_SUPPORT_ABILITY:
-+		phydm_supportability_en(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_SMART_ANT:
-+		#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+
-+		#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
-+		phydm_hl_smt_ant_dbg_type2(dm, input, &used, output, &out_len);
-+		#elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))
-+		phydm_hl_smart_ant_debug(dm, input, &used, output, &out_len);
-+		#endif
-+
-+		#elif (defined(CONFIG_CUMITEK_SMART_ANTENNA))
-+		phydm_cumitek_smt_ant_debug(dm, input, &used, output, &out_len);
-+		#endif
-+
-+		break;
-+
-+	case PHYDM_CH_BW:
-+		phydm_bw_ch_adjust(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_PROFILE:
-+		phydm_basic_profile(dm, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_GET_TXAGC:
-+		phydm_get_txagc(dm, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_SET_TXAGC:
-+		phydm_set_txagc_dbg(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_TRX_PATH:
-+		phydm_config_trx_path(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_LA_MODE:
-+		#if (PHYDM_LA_MODE_SUPPORT)
-+		phydm_la_cmd(dm, input, &used, output, &out_len);
-+		#endif
-+		break;
-+
-+	case PHYDM_DUMP_REG:
-+		phydm_dump_reg(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_BIG_JUMP:
-+		phydm_enable_big_jump(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_AUTO_DBG:
-+		#ifdef PHYDM_AUTO_DEGBUG
-+		phydm_auto_dbg_console(dm, input, &used, output, &out_len);
-+		#endif
-+		break;
-+
-+	case PHYDM_DD_DBG:
-+		phydm_dd_dbg_dump(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_SHOW_RXRATE:
-+		phydm_show_rx_rate(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_NBI_EN:
-+		phydm_nbi_debug(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_CSI_MASK_EN:
-+		phydm_csi_debug(dm, input, &used, output, &out_len);
-+		break;
-+
-+	#ifdef CONFIG_PHYDM_DFS_MASTER
-+	case PHYDM_DFS_DEBUG:
-+		phydm_dfs_debug(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_DFS_HIST:
-+		phydm_dfs_hist_dbg(dm, input, &used, output, &out_len);
-+		break;
-+	#endif
-+
-+	case PHYDM_NHM:
-+		#ifdef NHM_SUPPORT
-+		phydm_nhm_dbg(dm, input, &used, output, &out_len);
-+		#endif
-+		break;
-+
-+	case PHYDM_CLM:
-+		#ifdef CLM_SUPPORT
-+		phydm_clm_dbg(dm, input, &used, output, &out_len);
-+		#endif
-+		break;
-+
-+	#ifdef FAHM_SUPPORT
-+	case PHYDM_FAHM:
-+		phydm_fahm_dbg(dm, input, &used, output, &out_len);
-+		break;
-+	#endif
-+
-+	case PHYDM_ENV_MNTR:
-+		phydm_env_mntr_dbg(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_BB_INFO:
-+		phydm_bb_hw_dbg_info(dm, input, &used, output, &out_len);
-+		break;
-+	/*
-+	case PHYDM_TXBF: {
-+	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	#ifdef PHYDM_BEAMFORMING_SUPPORT
-+		struct _RT_BEAMFORMING_INFO *beamforming_info = NULL;
-+
-+		beamforming_info = &dm->beamforming_info;
-+
-+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+		if (var1[0] == 0) {
-+			beamforming_info->apply_v_matrix = false;
-+			beamforming_info->snding3ss = true;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\r\n dont apply V matrix and 3SS 789 snding\n");
-+		} else if (var1[0] == 1) {
-+			beamforming_info->apply_v_matrix = true;
-+			beamforming_info->snding3ss = true;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\r\n apply V matrix and 3SS 789 snding\n");
-+		} else if (var1[0] == 2) {
-+			beamforming_info->apply_v_matrix = true;
-+			beamforming_info->snding3ss = false;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\r\n default txbf setting\n");
-+		} else
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "\r\n unknown cmd!!\n");
-+	#endif
-+	#endif
-+	} break;
-+	*/
-+	case PHYDM_H2C:
-+		phydm_h2C_debug(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_EXT_RF_E_CTRL:
-+		phydm_ext_rf_element_ctrl(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_ADAPTIVE_SOML:
-+		#ifdef CONFIG_ADAPTIVE_SOML
-+		phydm_soml_debug(dm, input, &used, output, &out_len);
-+		#endif
-+		break;
-+
-+	case PHYDM_PSD:
-+
-+		#ifdef CONFIG_PSD_TOOL
-+		phydm_psd_debug(dm, input, &used, output, &out_len);
-+		#endif
-+
-+		break;
-+
-+	case PHYDM_DEBUG_PORT:
-+		phydm_print_dbgport(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_DIS_HTSTF_CONTROL: {
-+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+
-+		if (var1[0] == 1) {
-+			/* setting being false is for debug */
-+			dm->bhtstfdisabled = true;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Dynamic HT-STF Gain Control is Disable\n");
-+		} else {
-+			/* @default setting should be true,
-+			 * always be dynamic control
-+			 */
-+			dm->bhtstfdisabled = false;
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Dynamic HT-STF Gain Control is Enable\n");
-+		}
-+	} break;
-+
-+	case PHYDM_CFO_TRK:
-+		phydm_cfo_tracking_debug(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_ADAPTIVITY_DEBUG:
-+		#ifdef PHYDM_SUPPORT_ADAPTIVITY
-+		phydm_adaptivity_debug(dm, input, &used, output, &out_len);
-+		#endif
-+		break;
-+
-+	case PHYDM_DIS_DYM_ANT_WEIGHTING:
-+		#ifdef DYN_ANT_WEIGHTING_SUPPORT
-+		phydm_ant_weight_dbg(dm, input, &used, output, &out_len);
-+		#endif
-+		break;
-+
-+	case PHYDM_FORECE_PT_STATE:
-+		#ifdef PHYDM_POWER_TRAINING_SUPPORT
-+		phydm_pow_train_debug(dm, input, &used, output, &out_len);
-+		#endif
-+		break;
-+
-+	case PHYDM_STA_INFO:
-+		phydm_show_sta_info(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_PAUSE_FUNC:
-+		phydm_pause_func_console(dm, input, &used, output, &out_len);
-+		break;
-+
-+	case PHYDM_PER_TONE_EVM:
-+		phydm_per_tone_evm(dm, input, &used, output, &out_len);
-+		break;
-+
-+	#ifdef CONFIG_DYNAMIC_TX_TWR
-+	case PHYDM_DYN_TXPWR:
-+		phydm_dtp_debug(dm, input, &used, output, &out_len);
-+		break;
-+	#endif
-+
-+	case PHYDM_LNA_SAT:
-+		#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+		phydm_lna_sat_debug(dm, input, &used, output, &out_len);
-+		#endif
-+		break;
-+
-+	case PHYDM_ANAPAR:
-+		phydm_get_anapar_table(dm, &used, output, &out_len);
-+		break;
-+	case PHYDM_CCK_RX_PATHDIV:
-+		#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT
-+		phydm_cck_rx_pathdiv_dbg(dm, input, &used, output, &out_len);
-+		#endif
-+		break;
-+
-+	case PHYDM_BEAM_FORMING:
-+		#ifdef CONFIG_BB_TXBF_API
-+		phydm_bf_debug(dm, input, &used, output, &out_len);
-+		#endif
-+		break;
-+	case PHYDM_REG_MONITOR:
-+		phydm_reg_monitor(dm, input, &used, output, &out_len);
-+		break;
-+
-+#if RTL8814B_SUPPORT
-+	case PHYDM_SPUR_DETECT:
-+		phydm_spur_detect_dbg(dm, input, &used, output, &out_len);
-+		break;
-+#endif
-+	case PHYDM_CRC32_CNT:
-+		phydm_crc32_cnt_dbg(dm, input, &used, output, &out_len);
-+		break;
-+	case PHYDM_PHY_STATUS:
-+		phydm_physts_dbg(dm, input, &used, output, &out_len);
-+		break;
-+#ifdef PHYDM_DCC_ENHANCE
-+	case PHYDM_DCC:
-+		phydm_dig_cckpd_coex_dbg(dm, input, &used, output, &out_len);
-+		break;
-+#endif
-+#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
-+	case PHYDM_PMAC_TX:
-+		phydm_pmac_tx_dbg(dm, input, &used, output, &out_len);
-+		break;
-+#endif
-+#ifdef PHYDM_HW_IGI
-+	case PHYDM_HWIGI:
-+		phydm_hwigi_dbg(dm, input, &used, output, &out_len);
-+		break;
-+#endif
-+#ifdef PHYDM_HW_SWITCH_AGC_TAB
-+	case PHYDM_HW_AGCTAB:
-+		phydm_auto_agc_tab_debug(dm, input, &used, output, &out_len);
-+		break;
-+#endif
-+	case PHYDM_GET_RXAGC:
-+		phydm_get_rxagc_table_dbg(dm, input, &used, output, &out_len);
-+		break;
-+	case PHYDM_SHIFT_RXAGC:
-+		phydm_shift_rxagc_table_dbg(dm, input, &used, output, &out_len);
-+		break;
-+	case PHYDM_IFS_CLM:
-+		#ifdef IFS_CLM_SUPPORT
-+		phydm_ifs_clm_dbg(dm, input, &used, output, &out_len);
-+		#endif
-+		break;
-+	case PHYDM_ENHANCE_MNTR:
-+		phydm_enhance_mntr_dbg(dm, input, &used, output, &out_len);
-+		break;
-+	case PHYDM_CSI_DBG:
-+		phydm_get_csi_table(dm, &used, output, &out_len);
-+		break;
-+	default:
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Do not support this command\n");
-+		break;
-+	}
-+#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
-+}
-+
-+#if defined __ECOS || defined __ICCARM__
-+#ifndef strsep
-+char *strsep(char **s, const char *ct)
-+{
-+	char *sbegin = *s;
-+	char *end;
-+
-+	if (!sbegin)
-+		return NULL;
-+
-+	end = strpbrk(sbegin, ct);
-+	if (end)
-+		*end++ = '\0';
-+	*s = end;
-+	return sbegin;
-+}
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP | ODM_IOT))
-+s32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag,
-+	      char *output, u32 out_len)
-+{
-+	char *token;
-+	u32 argc = 0;
-+	char argv[MAX_ARGC][MAX_ARGV];
-+
-+	do {
-+		token = strsep(&input, ", ");
-+		if (token) {
-+			if (strlen(token) <= MAX_ARGV)
-+				strcpy(argv[argc], token);
-+
-+			argc++;
-+		} else {
-+			break;
-+		}
-+	} while (argc < MAX_ARGC);
-+
-+	if (argc == 1)
-+		argv[0][strlen(argv[0]) - 1] = '\0';
-+
-+	phydm_cmd_parser(dm, argv, argc, flag, output, out_len);
-+
-+	return 0;
-+}
-+#endif
-+
-+void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
-+{
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	/*@u8	debug_trace_11byte[60];*/
-+	u8 freg_num, c2h_seq, buf_0 = 0;
-+
-+	if (!(dm->support_ic_type & PHYDM_IC_3081_SERIES))
-+		return;
-+
-+	if (cmd_len > 12 || cmd_len == 0) {
-+		pr_debug("[Warning] Error C2H cmd_len=%d\n", cmd_len);
-+		return;
-+	}
-+
-+	buf_0 = cmd_buf[0];
-+	freg_num = (buf_0 & 0xf);
-+	c2h_seq = (buf_0 & 0xf0) >> 4;
-+
-+	#if 0
-+	PHYDM_DBG(dm, DBG_FW_TRACE,
-+		  "[FW debug message] freg_num = (( %d )), c2h_seq=(( %d ))\n",
-+		  freg_num, c2h_seq);
-+
-+	strncpy(debug_trace_11byte, &cmd_buf[1], (cmd_len - 1));
-+	debug_trace_11byte[cmd_len - 1] = '\0';
-+	PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] %s\n",
-+		  debug_trace_11byte);
-+	PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] cmd_len = (( %d ))\n",
-+		  cmd_len);
-+	PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] c2h_cmd_start=((%d))\n",
-+		  dm->c2h_cmd_start);
-+
-+	PHYDM_DBG(dm, DBG_FW_TRACE, "pre_seq = (( %d )), current_seq=((%d))\n",
-+		  dm->pre_c2h_seq, c2h_seq);
-+	PHYDM_DBG(dm, DBG_FW_TRACE, "fw_buff_is_enpty = (( %d ))\n",
-+		  dm->fw_buff_is_enpty);
-+	#endif
-+
-+	if (c2h_seq != dm->pre_c2h_seq && dm->fw_buff_is_enpty == false) {
-+		dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
-+		PHYDM_DBG(dm, DBG_FW_TRACE, "[FW Dbg Queue Overflow] %s\n",
-+			  dm->fw_debug_trace);
-+		dm->c2h_cmd_start = 0;
-+	}
-+
-+	if ((cmd_len - 1) > (60 - dm->c2h_cmd_start)) {
-+		dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
-+		PHYDM_DBG(dm, DBG_FW_TRACE,
-+			  "[FW Dbg Queue error: wrong C2H length] %s\n",
-+			  dm->fw_debug_trace);
-+		dm->c2h_cmd_start = 0;
-+		return;
-+	}
-+
-+	strncpy((char *)&dm->fw_debug_trace[dm->c2h_cmd_start],
-+		(char *)&cmd_buf[1], (cmd_len - 1));
-+	dm->c2h_cmd_start += (cmd_len - 1);
-+	dm->fw_buff_is_enpty = false;
-+
-+	if (freg_num == 0 || dm->c2h_cmd_start >= 60) {
-+		if (dm->c2h_cmd_start < 60)
-+			dm->fw_debug_trace[dm->c2h_cmd_start] = '\0';
-+		else
-+			dm->fw_debug_trace[59] = '\0';
-+
-+		PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s\n",
-+			  dm->fw_debug_trace);
-+
-+		dm->c2h_cmd_start = 0;
-+		dm->fw_buff_is_enpty = true;
-+	}
-+
-+	dm->pre_c2h_seq = c2h_seq;
-+#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
-+}
-+
-+void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len)
-+{
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 function = buffer[0];
-+	u8 dbg_num = buffer[1];
-+	u16 content_0 = (((u16)buffer[3]) << 8) | ((u16)buffer[2]);
-+	u16 content_1 = (((u16)buffer[5]) << 8) | ((u16)buffer[4]);
-+	u16 content_2 = (((u16)buffer[7]) << 8) | ((u16)buffer[6]);
-+	u16 content_3 = (((u16)buffer[9]) << 8) | ((u16)buffer[8]);
-+	u16 content_4 = (((u16)buffer[11]) << 8) | ((u16)buffer[10]);
-+
-+	if (cmd_len > 12)
-+		PHYDM_DBG(dm, DBG_FW_TRACE,
-+			  "[FW Msg] Invalid cmd length (( %d )) >12\n",
-+			  cmd_len);
-+/*@--------------------------------------------*/
-+#ifdef CONFIG_RA_FW_DBG_CODE
-+	if (function == RATE_DECISION) {
-+		if (dbg_num == 0) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] RA_CNT=((%d))  Max_device=((%d))--------------------------->\n",
-+					  content_1, content_2);
-+			else if (content_0 == 2)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] Check RA macid= ((%d)), MediaStatus=((%d)), Dis_RA=((%d)),  try_bit=((0x%x))\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+			else if (content_0 == 3)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] Check RA  total=((%d)),  drop=((0x%x)), TXRPT_TRY_bit=((%x)), bNoisy=((%x))\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+		} else if (dbg_num == 1) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] RTY[0,1,2,3]=[ %d , %d , %d , %d ]\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+			else if (content_0 == 2) {
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] RTY[4]=[ %d ], drop=(( %d )), total=(( %d )), current_rate=((0x %x ))",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+				phydm_print_rate(dm, (u8)content_4,
-+						 DBG_FW_TRACE);
-+			} else if (content_0 == 3)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] penality_idx=(( %d ))\n",
-+					  content_1);
-+			else if (content_0 == 4)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] RSSI=(( %d )), ra_stage = (( %d ))\n",
-+					  content_1, content_2);
-+		} else if (dbg_num == 3) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] Fast_RA (( DOWN ))  total=((%d)),  total>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+			else if (content_0 == 2)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] Fast_RA (( UP ))  total_acc=((%d)),  total_acc>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+			else if (content_0 == 3)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] Fast_RA (( UP )) ((rate Down Hold))  RA_CNT=((%d))\n",
-+					  content_1);
-+			else if (content_0 == 4)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] Fast_RA (( UP )) ((tota_accl<5 skip))  RA_CNT=((%d))\n",
-+					  content_1);
-+			else if (content_0 == 8)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] Fast_RA (( Reset Tx Rpt )) RA_CNT=((%d))\n",
-+					  content_1);
-+		} else if (dbg_num == 4) {
-+			if (content_0 == 3)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] RER_CNT   PCR_ori =(( %d )),  ratio_ori =(( %d )), pcr_updown_bitmap =(( 0x%x )), pcr_var_diff =(( %d ))\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+			else if (content_0 == 4)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] pcr_shift_value =(( %s%d )), rate_down_threshold =(( %d )), rate_up_threshold =(( %d ))\n",
-+					  ((content_1) ? "+" : "-"), content_2,
-+					  content_3, content_4);
-+			else if (content_0 == 5)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] pcr_mean =(( %d )), PCR_VAR =(( %d )), offset =(( %d )), decision_offset_p =(( %d ))\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+		} else if (dbg_num == 5) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] (( UP))  Nsc=(( %d )), N_High=(( %d )), RateUp_Waiting=(( %d )), RateUp_Fail=(( %d ))\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+			else if (content_0 == 2)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] ((DOWN))  Nsc=(( %d )), N_Low=(( %d ))\n",
-+					  content_1, content_2);
-+			else if (content_0 == 3)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] ((HOLD))  Nsc=((%d)), N_High=((%d)), N_Low=((%d)), Reset_CNT=((%d))\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+		} else if (dbg_num == 0x60) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] ((AP RPT))  macid=((%d)), BUPDATE[macid]=((%d))\n",
-+					  content_1, content_2);
-+			else if (content_0 == 4)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] ((AP RPT))  pass=((%d)), rty_num=((%d)), drop=((%d)), total=((%d))\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+			else if (content_0 == 5)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW] ((AP RPT))  PASS=((%d)), RTY_NUM=((%d)), DROP=((%d)), TOTAL=((%d))\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+		}
-+	} else if (function == INIT_RA_TABLE) {
-+		if (dbg_num == 3)
-+			PHYDM_DBG(dm, DBG_FW_TRACE,
-+				  "[FW][INIT_RA_INFO] Ra_init, RA_SKIP_CNT = (( %d ))\n",
-+				  content_0);
-+	} else if (function == RATE_UP) {
-+		if (dbg_num == 2) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW][RateUp]  ((Highest rate->return)), macid=((%d))  Nsc=((%d))\n",
-+					  content_1, content_2);
-+		} else if (dbg_num == 5) {
-+			if (content_0 == 0)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW][RateUp]  ((rate UP)), up_rate_tmp=((0x%x)), rate_idx=((0x%x)), SGI_en=((%d)),  SGI=((%d))\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+			else if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW][RateUp]  ((rate UP)), rate_1=((0x%x)), rate_2=((0x%x)), BW=((%d)), Try_Bit=((%d))\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+		}
-+	} else if (function == RATE_DOWN) {
-+		if (dbg_num == 5) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW][RateDownStep]  ((rate Down)), macid=((%d)), rate1=((0x%x)),  rate2=((0x%x)), BW=((%d))\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+		}
-+	} else if (function == TRY_DONE) {
-+		if (dbg_num == 1) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW][Try Done]  ((try succsess )) macid=((%d)), Try_Done_cnt=((%d))\n",
-+					  content_1, content_2);
-+		} else if (dbg_num == 2) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW][Try Done]  ((try)) macid=((%d)), Try_Done_cnt=((%d)),  rate_2=((%d)),  try_succes=((%d))\n",
-+					  content_1, content_2, content_3,
-+					  content_4);
-+		}
-+	} else if (function == RA_H2C) {
-+		if (dbg_num == 1) {
-+			if (content_0 == 0)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW][H2C=0x49]  fw_trace_en=((%d)), mode =((%d)),  macid=((%d))\n",
-+					  content_1, content_2, content_3);
-+		}
-+	} else if (function == F_RATE_AP_RPT) {
-+		if (dbg_num == 1) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW][AP RPT]  ((1)), SPE_STATIS=((0x%x))---------->\n",
-+					  content_3);
-+		} else if (dbg_num == 2) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW][AP RPT]  RTY_all=((%d))\n",
-+					  content_1);
-+		} else if (dbg_num == 3) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW][AP RPT]  MACID1[%d], TOTAL=((%d)),  RTY=((%d))\n",
-+					  content_3, content_1, content_2);
-+		} else if (dbg_num == 4) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW][AP RPT]  MACID2[%d], TOTAL=((%d)),  RTY=((%d))\n",
-+					  content_3, content_1, content_2);
-+		} else if (dbg_num == 5) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW][AP RPT]  MACID1[%d], PASS=((%d)),  DROP=((%d))\n",
-+					  content_3, content_1, content_2);
-+		} else if (dbg_num == 6) {
-+			if (content_0 == 1)
-+				PHYDM_DBG(dm, DBG_FW_TRACE,
-+					  "[FW][AP RPT]  MACID2[%d],, PASS=((%d)),  DROP=((%d))\n",
-+					  content_3, content_1, content_2);
-+		}
-+	} else if (function == DBC_FW_CLM) {
-+		PHYDM_DBG(dm, DBG_FW_TRACE,
-+			  "[FW][CLM][%d, %d] = {%d, %d, %d, %d}\n", dbg_num,
-+			  content_0, content_1, content_2, content_3,
-+			  content_4);
-+	} else {
-+		PHYDM_DBG(dm, DBG_FW_TRACE,
-+			  "[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n",
-+			  function, dbg_num, content_0, content_1, content_2,
-+			  content_3, content_4);
-+	}
-+#else
-+	PHYDM_DBG(dm, DBG_FW_TRACE,
-+		  "[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function,
-+		  dbg_num, content_0, content_1, content_2, content_3,
-+		  content_4);
-+#endif
-+/*@--------------------------------------------*/
-+
-+#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
-+}
-+
-+void phydm_fw_trace_handler_8051(void *dm_void, u8 *buffer, u8 cmd_len)
-+{
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	int i = 0;
-+	u8 extend_c2h_sub_id = 0, extend_c2h_dbg_len = 0;
-+	u8 extend_c2h_dbg_seq = 0;
-+	u8 fw_debug_trace[128];
-+	u8 *extend_c2h_dbg_content = 0;
-+
-+	if (cmd_len > 127)
-+		return;
-+
-+	extend_c2h_sub_id = buffer[0];
-+	extend_c2h_dbg_len = buffer[1];
-+	extend_c2h_dbg_content = buffer + 2; /*@DbgSeq+DbgContent for show HEX*/
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	RT_DISP(FC2H, C2H_Summary, ("[Extend C2H packet], Extend_c2hSubId=0x%x, extend_c2h_dbg_len=%d\n",
-+				    extend_c2h_sub_id, extend_c2h_dbg_len));
-+
-+	RT_DISP_DATA(FC2H, C2H_Summary, "[Extend C2H packet], Content Hex:", extend_c2h_dbg_content, cmd_len - 2);
-+#endif
-+
-+go_backfor_aggre_dbg_pkt:
-+	i = 0;
-+	extend_c2h_dbg_seq = buffer[2];
-+	extend_c2h_dbg_content = buffer + 3;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	RT_DISP(FC2H, C2H_Summary, ("[RTKFW, SEQ= %d] :", extend_c2h_dbg_seq));
-+#endif
-+
-+	for (;; i++) {
-+		fw_debug_trace[i] = extend_c2h_dbg_content[i];
-+		if (extend_c2h_dbg_content[i + 1] == '\0') {
-+			fw_debug_trace[i + 1] = '\0';
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s",
-+				  &fw_debug_trace[0]);
-+			break;
-+		} else if (extend_c2h_dbg_content[i] == '\n') {
-+			fw_debug_trace[i + 1] = '\0';
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s",
-+				  &fw_debug_trace[0]);
-+			buffer = extend_c2h_dbg_content + i + 3;
-+			goto go_backfor_aggre_dbg_pkt;
-+		}
-+	}
-+#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_debug.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_debug.h
-new file mode 100644
-index 000000000000..06e809b57458
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_debug.h
-@@ -0,0 +1,484 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __ODM_DBG_H__
-+#define __ODM_DBG_H__
-+
-+/*#define DEBUG_VERSION	"1.1"*/ /*2015.07.29 YuChen*/
-+/*#define DEBUG_VERSION	"1.2"*/ /*2015.08.28 Dino*/
-+/*#define DEBUG_VERSION	"1.3"*/ /*2016.04.28 YuChen*/
-+/*#define DEBUG_VERSION	"1.4"*/ /*2017.03.13 Dino*/
-+/*#define DEBUG_VERSION "2.0"*/ /*2018.01.10 Dino*/
-+/*2020.07.03 fix cck report bug due to 8723F coding error*/
-+#define DEBUG_VERSION "4.6"
-+
-+/*@
-+ * ============================================================
-+ *  Definition
-+ * ============================================================
-+ */
-+
-+/*@FW DBG MSG*/
-+#define	RATE_DECISION		1
-+#define	INIT_RA_TABLE		2
-+#define	RATE_UP			4
-+#define	RATE_DOWN		8
-+#define	TRY_DONE		16
-+#define	RA_H2C			32
-+#define	F_RATE_AP_RPT		64
-+#define	DBC_FW_CLM		9
-+
-+#define PHYDM_SNPRINT_SIZE	64
-+/* @----------------------------------------------------------------------------
-+ * Define the tracing components
-+ *
-+ * -----------------------------------------------------------------------------
-+ * BB FW Functions
-+ */
-+#define	PHYDM_FW_COMP_RA	BIT(0)
-+#define	PHYDM_FW_COMP_MU	BIT(1)
-+#define	PHYDM_FW_COMP_PATH_DIV	BIT(2)
-+#define	PHYDM_FW_COMP_PT	BIT(3)
-+
-+/*@------------------------Export Marco Definition---------------------------*/
-+
-+#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	#if (DBG_CMD_SUPPORT == 1)
-+		extern	VOID DCMD_Printf(const char *pMsg);
-+	#else
-+		#define DCMD_Printf(_pMsg)
-+	#endif
-+
-+	#if OS_WIN_FROM_WIN10(OS_VERSION)
-+	#define	pr_debug(fmt, ...) DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, fmt, ##__VA_ARGS__)
-+	#else
-+	#define	pr_debug		DbgPrint
-+	#endif
-+
-+	#define	dcmd_printf		DCMD_Printf
-+	#define	dcmd_scanf		DCMD_Scanf
-+	#define	RT_PRINTK		pr_debug
-+	#define	PRINT_MAX_SIZE		512
-+	#define PHYDM_SNPRINTF		RT_SPRINTF
-+	#define	PHYDM_TRACE(_MSG_) 	EXhalPHYDMoutsrc_Print(_MSG_)
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	#define PHYDM_SNPRINTF		snprintf
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	#undef	pr_debug
-+	#define pr_debug		printk
-+	#define RT_PRINTK(fmt, args...)	pr_debug(fmt, ## args)
-+	#define	RT_DISP(dbgtype, dbgflag, printstr)
-+	#define RT_TRACE(adapter, comp, drv_level, fmt, args...)	\
-+		RTW_INFO(fmt, ## args)
-+	#define PHYDM_SNPRINTF		snprintf
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+	#define pr_debug(fmt, args...)		RTW_PRINT_MSG(fmt, ## args)
-+	#define RT_DEBUG(comp, drv_level, fmt, args...)	\
-+		RTW_PRINT_MSG(fmt, ## args)
-+	#define PHYDM_SNPRINTF		snprintf
-+#else
-+	#define pr_debug	panic_printk
-+	/*@#define RT_PRINTK(fmt, args...)	pr_debug("%s(): " fmt, __FUNCTION__, ## args);*/
-+	#define RT_PRINTK(fmt, args...)	pr_debug(fmt, ## args)
-+	#define PHYDM_SNPRINTF		snprintf
-+#endif
-+
-+#ifndef ASSERT
-+	#define ASSERT(expr)
-+#endif
-+
-+#if DBG
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+#define PHYDM_DBG(dm, comp, fmt, args...)			\
-+	do {							\
-+		if ((comp) & dm->debug_components) {          \
-+			pr_debug("[PHYDM] ");			\
-+			RT_PRINTK(fmt, ## args);		\
-+		}						\
-+	} while (0)
-+
-+#define PHYDM_DBG_F(dm, comp, fmt, args...)			\
-+	do {							\
-+		if ((comp) & dm->debug_components) {		\
-+			RT_PRINTK(fmt, ## args);		\
-+		}						\
-+	} while (0)
-+
-+#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)		\
-+	do {							\
-+		if ((comp) & dm->debug_components) {		\
-+			int __i;				\
-+			u8 *__ptr = (u8 *)addr;			\
-+			pr_debug("[PHYDM] ");			\
-+			pr_debug(title_str);			\
-+			pr_debug(" ");				\
-+			for (__i = 0; __i < 6; __i++)		\
-+				pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-");\
-+			pr_debug("\n");				\
-+		}						\
-+	} while (0)
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+static __inline void PHYDM_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
-+{
-+	RT_STATUS rt_status;
-+	va_list args;
-+	char buf[PRINT_MAX_SIZE] = {0};
-+
-+	if ((comp & dm->debug_components) == 0)
-+		return;
-+
-+	if (fmt == NULL)
-+		return;
-+
-+	va_start(args, fmt);
-+	rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
-+	va_end(args);
-+
-+	if (rt_status != RT_STATUS_SUCCESS) {
-+		DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
-+		return;
-+	}
-+
-+	#if OS_WIN_FROM_WIN10(OS_VERSION)
-+	DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, "%s", buf);
-+	#else
-+	DbgPrint("%s", buf);
-+	#endif
-+}
-+
-+static __inline void PHYDM_DBG_F(PDM_ODM_T dm, int comp, char *fmt, ...)
-+{
-+	RT_STATUS rt_status;
-+	va_list args;
-+	char buf[PRINT_MAX_SIZE] = {0};
-+
-+	if ((comp & dm->debug_components) == 0)
-+		return;
-+
-+	if (fmt == NULL)
-+		return;
-+
-+	va_start(args, fmt);
-+	rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
-+	va_end(args);
-+
-+	if (rt_status != RT_STATUS_SUCCESS) {
-+		/*@DbgPrint("DM Print Fail\n");*/
-+		return;
-+	}
-+
-+	#if OS_WIN_FROM_WIN10(OS_VERSION)
-+	DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, "%s", buf);
-+	#else
-+	DbgPrint("%s", buf);
-+	#endif
-+}
-+
-+#define PHYDM_PRINT_ADDR(p_dm, comp, title_str, ptr)		\
-+	do {							\
-+		if ((comp) & p_dm->debug_components) {		\
-+								\
-+			int __i;				\
-+			u8 *__ptr = (u8 *)ptr;			\
-+			pr_debug("[PHYDM] ");			\
-+			pr_debug(title_str);			\
-+			pr_debug(" ");				\
-+			for (__i = 0; __i < 6; __i++)		\
-+				pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-");	\
-+			pr_debug("\n");				\
-+		}	\
-+	} while (0)
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+
-+#define PHYDM_DBG(dm, comp, fmt, args...)			\
-+	do {							\
-+		if ((comp) & dm->debug_components) {		\
-+			RT_DEBUG(COMP_PHYDM, \
-+				 DBG_DMESG, "[PHYDM] " fmt, ##args);	\
-+		}						\
-+	} while (0)
-+
-+#define PHYDM_DBG_F(dm, comp, fmt, args...)			\
-+	do {							\
-+		if ((comp) & dm->debug_components) {		\
-+			RT_DEBUG(COMP_PHYDM, \
-+				 DBG_DMESG, fmt, ##args);	\
-+		}	\
-+	} while (0)
-+
-+#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)		\
-+	do {							\
-+		if ((comp) & dm->debug_components) {		\
-+			RT_DEBUG(COMP_PHYDM, \
-+				 DBG_DMESG, "[PHYDM] " title_str "%pM\n",	\
-+				 addr);				\
-+		}						\
-+	} while (0)
-+
-+#elif defined(DM_ODM_CE_MAC80211_V2)
-+
-+#define PHYDM_DBG(dm, comp, fmt, args...)
-+#define PHYDM_DBG_F(dm, comp, fmt, args...)
-+#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)
-+
-+#else
-+
-+#define PHYDM_DBG(dm, comp, fmt, args...)			\
-+	do {							\
-+		struct dm_struct *__dm = (dm);			\
-+		if ((comp) & __dm->debug_components) {		\
-+			RT_TRACE(((struct rtl_priv *)__dm->adapter),\
-+				 COMP_PHYDM, DBG_DMESG,		\
-+				 "[PHYDM] " fmt, ##args);	\
-+		}						\
-+	} while (0)
-+
-+#define PHYDM_DBG_F(dm, comp, fmt, args...)			\
-+	do {							\
-+		struct dm_struct *__dm = (dm);			\
-+		if ((comp) & __dm->debug_components) {		\
-+			RT_TRACE(((struct rtl_priv *)__dm->adapter),\
-+				 COMP_PHYDM, DBG_DMESG, fmt, ##args);	\
-+		}	\
-+	} while (0)
-+
-+#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)		\
-+	do {							\
-+		struct dm_struct *__dm = (dm);			\
-+		if ((comp) & __dm->debug_components) {		\
-+			RT_TRACE(((struct rtl_priv *)__dm->adapter),\
-+				 COMP_PHYDM, DBG_DMESG,		\
-+				 "[PHYDM] " title_str "%pM\n", addr);\
-+		}						\
-+	} while (0)
-+#endif
-+
-+#else /*@#if DBG*/
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+static __inline void PHYDM_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
-+{
-+	RT_STATUS rt_status;
-+	va_list args;
-+	char buf[PRINT_MAX_SIZE] = {0};
-+
-+	if ((comp & dm->debug_components) == 0)
-+		return;
-+
-+	if (fmt == NULL)
-+		return;
-+
-+	va_start(args, fmt);
-+	rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
-+	va_end(args);
-+
-+	if (rt_status != RT_STATUS_SUCCESS) {
-+		DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
-+		return;
-+	}
-+
-+	PHYDM_TRACE(buf);
-+}
-+static __inline void PHYDM_DBG_F(struct dm_struct *dm, int comp, char *fmt, ...)
-+{
-+}
-+#else
-+#define PHYDM_DBG(dm, comp, fmt, args...)
-+#define PHYDM_DBG_F(dm, comp, fmt, args...)
-+#endif
-+#define PHYDM_PRINT_ADDR(dm, comp, title_str, ptr)
-+
-+#endif
-+
-+#define	DBGPORT_PRI_3	3	/*@Debug function (the highest priority)*/
-+#define	DBGPORT_PRI_2	2	/*@Check hang function & Strong function*/
-+#define	DBGPORT_PRI_1	1	/*Watch dog function*/
-+#define	DBGPORT_RELEASE	0	/*@Init value (the lowest priority)*/
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#define	PHYDM_DBGPRINT		0
-+#define	PHYDM_SSCANF(x, y, z)	dcmd_scanf(x, y, z)
-+#define	PDM_VAST_SNPF		PDM_SNPF
-+#if (PHYDM_DBGPRINT == 1)
-+#define	PDM_SNPF(msg)	\
-+	do {\
-+		rsprintf msg;\
-+		pr_debug("%s", output);\
-+	} while (0)
-+#else
-+
-+static __inline void PDM_SNPF(u32 out_len, u32 used, char *buff, int len,
-+			      char *fmt, ...)
-+{
-+	RT_STATUS rt_status;
-+	va_list args;
-+	char buf[PRINT_MAX_SIZE] = {0};
-+
-+	if (fmt == NULL)
-+		return;
-+
-+	va_start(args, fmt);
-+	rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
-+	va_end(args);
-+
-+	if (rt_status != RT_STATUS_SUCCESS) {
-+		/*@DbgPrint("DM Print Fail\n");*/
-+		return;
-+	}
-+
-+	DCMD_Printf(buf);
-+}
-+
-+
-+
-+#endif	/*@#if (PHYDM_DBGPRINT == 1)*/
-+#else	/*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__)
-+	#define	PHYDM_DBGPRINT	0
-+	#else
-+	#define	PHYDM_DBGPRINT	1
-+	#endif
-+#define	MAX_ARGC		20
-+#define	MAX_ARGV		16
-+#define	DCMD_DECIMAL		"%d"
-+#define	DCMD_CHAR		"%c"
-+#define	DCMD_HEX		"%x"
-+
-+#define	PHYDM_SSCANF(x, y, z)	sscanf(x, y, z)
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) RT_PRINTK(fmt, ## args)
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+#define	PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...)	\
-+	do {								\
-+		RT_DEBUG(COMP_PHYDM, DBG_DMESG, fmt, ##args);		\
-+	} while (0)
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+#define	PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...)
-+#else
-+#define	PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...)	\
-+		RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \
-+			DBG_DMESG, fmt, ##args)
-+#endif
-+
-+#if (PHYDM_DBGPRINT == 1)
-+#define	PDM_SNPF(out_len, used, buff, len, fmt, args...)		\
-+	do {								\
-+		snprintf(buff, len, fmt, ##args);			\
-+		pr_debug("%s", output);					\
-+	} while (0)
-+#else
-+#define	PDM_SNPF(out_len, used, buff, len, fmt, args...)		\
-+	do {								\
-+		u32 *__pdm_snpf_u = &(used);				\
-+		if (out_len > *__pdm_snpf_u)				\
-+			*__pdm_snpf_u += snprintf(buff, len, fmt, ##args);\
-+	} while (0)
-+#endif
-+#endif
-+/* @1 ============================================================
-+ * 1  enumeration
-+ * 1 ============================================================
-+ */
-+
-+enum auto_detection_state { /*@Fast antenna training*/
-+	AD_LEGACY_MODE	= 0,
-+	AD_HT_MODE	= 1,
-+	AD_VHT_MODE	= 2
-+};
-+
-+/*@
-+ * ============================================================
-+ * 1  structure
-+ * ============================================================
-+ */
-+
-+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
-+u8 phydm_get_l_sig_rate(void *dm_void, u8 rate_idx_l_sig);
-+#endif
-+
-+void phydm_init_debug_setting(struct dm_struct *dm);
-+
-+void phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx);
-+
-+u32 phydm_get_bb_dbg_port_idx(void *dm_void);
-+
-+u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port);
-+
-+void phydm_release_bb_dbg_port(void *dm_void);
-+
-+u32 phydm_get_bb_dbg_port_val(void *dm_void);
-+
-+void phydm_reset_rx_rate_distribution(struct dm_struct *dm);
-+
-+void phydm_rx_rate_distribution(void *dm_void);
-+
-+u16 phydm_rx_avg_phy_rate(void *dm_void);
-+
-+void phydm_show_phy_hitogram(void *dm_void);
-+
-+void phydm_get_avg_phystatus_val(void *dm_void);
-+
-+void phydm_get_phy_statistic(void *dm_void);
-+
-+void phydm_dm_summary(void *dm_void, u8 macid);
-+
-+void phydm_basic_dbg_message(void *dm_void);
-+
-+void phydm_basic_profile(void *dm_void, u32 *_used, char *output,
-+			 u32 *_out_len);
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
-+s32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag,
-+	      char *output, u32 out_len);
-+#endif
-+void phydm_cmd_parser(struct dm_struct *dm, char input[][16], u32 input_num,
-+		      u8 flag, char *output, u32 out_len);
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void phydm_basic_dbg_msg_cli_win(void *dm_void, char *buf);
-+
-+void phydm_sbd_check(
-+	struct dm_struct *dm);
-+
-+void phydm_sbd_callback(
-+	struct phydm_timer_list *timer);
-+
-+void phydm_sbd_workitem_callback(
-+	void *context);
-+#endif
-+
-+void phydm_fw_trace_en_h2c(void *dm_void, boolean enable,
-+			   u32 fw_debug_component, u32 monitor_mode, u32 macid);
-+
-+void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
-+
-+void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len);
-+
-+void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len);
-+
-+#endif /* @__ODM_DBG_H__ */
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_dfs.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_dfs.c
-new file mode 100644
-index 000000000000..0384148d8bb5
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_dfs.c
-@@ -0,0 +1,2193 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@
-+ * ============================================================
-+ * include files
-+ * ============================================================
-+ */
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#if defined(CONFIG_PHYDM_DFS_MASTER)
-+
-+boolean phydm_dfs_is_meteorology_channel(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	u8 ch = *dm->channel;
-+	u8 bw = *dm->band_width;
-+
-+	return ((bw  == CHANNEL_WIDTH_80 && (ch) >= 116 && (ch) <= 128) ||
-+		(bw  == CHANNEL_WIDTH_40 && (ch) >= 116 && (ch) <= 128) ||
-+		(bw  == CHANNEL_WIDTH_20 && (ch) >= 120 && (ch) <= 128));
-+}
-+
-+void phydm_dfs_segment_distinguish(void *dm_void, enum rf_syn syn_path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ic_type & (ODM_RTL8814B)))
-+		return;
-+	if (syn_path == RF_SYN1)
-+		dm->seg1_dfs_flag = 1;
-+	else
-+		dm->seg1_dfs_flag = 0;
-+}
-+
-+void phydm_dfs_segment_flag_reset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ic_type & (ODM_RTL8814B)))
-+		return;
-+	if (dm->seg1_dfs_flag)
-+		dm->seg1_dfs_flag = 0;
-+}
-+
-+void phydm_radar_detect_reset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
-+				   ODM_RTL8197G | ODM_RTL8723F)) {
-+		odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
-+		odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
-+	#if (RTL8721D_SUPPORT)
-+	} else if (dm->support_ic_type & (ODM_RTL8721D)) {
-+		odm_set_bb_reg(dm, R_0xf58, BIT(29), 0);
-+		odm_set_bb_reg(dm, R_0xf58, BIT(29), 1);
-+	#endif
-+	} else if (dm->support_ic_type & (ODM_RTL8814B)) {
-+		if (dm->seg1_dfs_flag == 1) {
-+			odm_set_bb_reg(dm, R_0xa6c, BIT(0), 0);
-+			odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
-+			return;
-+		}
-+		odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
-+		odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
-+	} else {
-+		odm_set_bb_reg(dm, R_0x924, BIT(15), 0);
-+		odm_set_bb_reg(dm, R_0x924, BIT(15), 1);
-+	}
-+}
-+
-+void phydm_radar_detect_disable(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
-+				   ODM_RTL8197G | ODM_RTL8723F))
-+		odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
-+	else if (dm->support_ic_type & (ODM_RTL8814B)) {
-+		if (dm->seg1_dfs_flag == 1) {
-+			odm_set_bb_reg(dm, R_0xa6c, BIT(0), 0);
-+			dm->seg1_dfs_flag = 0;
-+			return;
-+		}
-+		odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
-+	}
-+	#if (RTL8721D_SUPPORT)
-+	else if (dm->support_ic_type & (ODM_RTL8721D))
-+		odm_set_bb_reg(dm, R_0xf58, BIT(29), 0);
-+	#endif
-+	else
-+		odm_set_bb_reg(dm, R_0x924, BIT(15), 0);
-+
-+	PHYDM_DBG(dm, DBG_DFS, "\n");
-+}
-+
-+static void phydm_radar_detect_with_dbg_parm(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_RTL8721D) {
-+		odm_set_bb_reg(dm, R_0xf54, MASKDWORD,
-+			       dm->radar_detect_reg_f54);
-+		odm_set_bb_reg(dm, R_0xf58, MASKDWORD,
-+			       dm->radar_detect_reg_f58);
-+		odm_set_bb_reg(dm, R_0xf5c, MASKDWORD,
-+			       dm->radar_detect_reg_f5c);
-+		odm_set_bb_reg(dm, R_0xf70, MASKDWORD,
-+			       dm->radar_detect_reg_f70);
-+		odm_set_bb_reg(dm, R_0xf74, MASKDWORD,
-+			       dm->radar_detect_reg_f74);
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		odm_set_bb_reg(dm, R_0xa40, MASKDWORD,
-+			       dm->radar_detect_reg_a40);
-+		odm_set_bb_reg(dm, R_0xa44, MASKDWORD,
-+			       dm->radar_detect_reg_a44);
-+		odm_set_bb_reg(dm, R_0xa48, MASKDWORD,
-+			       dm->radar_detect_reg_a48);
-+		odm_set_bb_reg(dm, R_0xa4c, MASKDWORD,
-+			       dm->radar_detect_reg_a4c);
-+		odm_set_bb_reg(dm, R_0xa50, MASKDWORD,
-+			       dm->radar_detect_reg_a50);
-+		odm_set_bb_reg(dm, R_0xa54, MASKDWORD,
-+			       dm->radar_detect_reg_a54);
-+	} else {
-+		odm_set_bb_reg(dm, R_0x918, MASKDWORD,
-+			       dm->radar_detect_reg_918);
-+		odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
-+			       dm->radar_detect_reg_91c);
-+		odm_set_bb_reg(dm, R_0x920, MASKDWORD,
-+			       dm->radar_detect_reg_920);
-+		odm_set_bb_reg(dm, R_0x924, MASKDWORD,
-+			       dm->radar_detect_reg_924);
-+	}
-+}
-+
-+/* @Init radar detection parameters, called after ch, bw is set */
-+
-+void phydm_radar_detect_enable(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _DFS_STATISTICS *dfs = &dm->dfs;
-+	u8 region_domain = dm->dfs_region_domain;
-+	u8 c_channel = *dm->channel;
-+	u8 band_width = *dm->band_width;
-+	u8 enable = 0, i;
-+	u8 short_pw_upperbound = 0;
-+
-+	PHYDM_DBG(dm, DBG_DFS, "test, region_domain = %d\n", region_domain);
-+	if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {
-+		PHYDM_DBG(dm, DBG_DFS, "PHYDM_DFS_DOMAIN_UNKNOWN\n");
-+		goto exit;
-+	}
-+
-+	if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) {
-+		odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
-+		odm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06);
-+
-+		if (dm->radar_detect_dbg_parm_en) {
-+			phydm_radar_detect_with_dbg_parm(dm);
-+			enable = 1;
-+			goto exit;
-+		}
-+
-+		if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
-+			odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c17ecdf);
-+			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
-+			odm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fa21a20);
-+			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f69204);
-+
-+		} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
-+			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
-+			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234);
-+
-+			if (c_channel >= 52 && c_channel <= 64) {
-+				odm_set_bb_reg(dm, R_0x918, MASKDWORD,
-+					       0x1c16ecdf);
-+				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
-+					       0x0f141a20);
-+			} else {
-+				odm_set_bb_reg(dm, R_0x918, MASKDWORD,
-+					       0x1c16acdf);
-+				if (band_width == CHANNEL_WIDTH_20)
-+					odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
-+						       0x64721a20);
-+				else
-+					odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
-+						       0x68721a20);
-+			}
-+
-+		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
-+			odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf);
-+			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500);
-+			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67231);
-+			if (band_width == CHANNEL_WIDTH_20)
-+				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
-+					       0x64741a20);
-+			else
-+				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
-+					       0x68741a20);
-+
-+		} else {
-+			/* not supported */
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "Unsupported dfs_region_domain:%d\n",
-+				  region_domain);
-+			goto exit;
-+		}
-+
-+	} else if (dm->support_ic_type &
-+		   (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
-+
-+		odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
-+		odm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06);
-+
-+		/* @8822B only, when BW = 20M, DFIR output is 40Mhz,
-+		 * but DFS input is 80MMHz, so it need to upgrade to 80MHz
-+		 */
-+		if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
-+			if (band_width == CHANNEL_WIDTH_20)
-+				odm_set_bb_reg(dm, R_0x1984, BIT(26), 1);
-+			else
-+				odm_set_bb_reg(dm, R_0x1984, BIT(26), 0);
-+		}
-+
-+		if (dm->radar_detect_dbg_parm_en) {
-+			phydm_radar_detect_with_dbg_parm(dm);
-+			enable = 1;
-+			goto exit;
-+		}
-+
-+		if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
-+			odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf);
-+			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500);
-+			odm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fc01a1f);
-+			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f57204);
-+
-+		} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
-+			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500);
-+			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234);
-+
-+			if (c_channel >= 52 && c_channel <= 64) {
-+				odm_set_bb_reg(dm, R_0x918, MASKDWORD,
-+					       0x1c16ecdf);
-+				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
-+					       0x0f141a1f);
-+			} else {
-+				odm_set_bb_reg(dm, R_0x918, MASKDWORD,
-+					       0x1c166cdf);
-+				if (band_width == CHANNEL_WIDTH_20)
-+					odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
-+						       0x64721a1f);
-+				else
-+					odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
-+						       0x68721a1f);
-+			}
-+
-+		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
-+			odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c176cdf);
-+			odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8400);
-+			odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe076d231);
-+			if (band_width == CHANNEL_WIDTH_20)
-+				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
-+					       0x64901a1f);
-+			else
-+				odm_set_bb_reg(dm, R_0x91c, MASKDWORD,
-+					       0x62901a1f);
-+
-+		} else {
-+			/* not supported */
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "Unsupported dfs_region_domain:%d\n",
-+				  region_domain);
-+			goto exit;
-+		}
-+		/*RXHP low corner will extend the pulse width,
-+		 *so we need to increase the upper bound.
-+		 */
-+		if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
-+			if (odm_get_bb_reg(dm, 0x8d8,
-+					   BIT28 | BIT27 | BIT26) == 0) {
-+				short_pw_upperbound =
-+					(u8)odm_get_bb_reg(dm, 0x91c,
-+						       BIT23 | BIT22 |
-+						       BIT21 | BIT20);
-+				if ((short_pw_upperbound + 4) > 15)
-+					odm_set_bb_reg(dm, 0x91c,
-+						       BIT23 | BIT22 |
-+						       BIT21 | BIT20, 15);
-+				else
-+					odm_set_bb_reg(dm, 0x91c,
-+						       BIT23 | BIT22 |
-+						       BIT21 | BIT20,
-+						       short_pw_upperbound + 4);
-+			}
-+			/*@if peak index -1~+1, use original NB method*/
-+			odm_set_bb_reg(dm, 0x19e4, 0x003C0000, 13);
-+			odm_set_bb_reg(dm, 0x924, 0x70000, 0);
-+		}
-+
-+		if (dm->support_ic_type & (ODM_RTL8881A))
-+			odm_set_bb_reg(dm, 0xb00, 0xc0000000, 3);
-+
-+		/*@for 8814 new dfs mechanism setting*/
-+		if (dm->support_ic_type &
-+		    (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
-+			/*Turn off dfs scaling factor*/
-+			odm_set_bb_reg(dm, 0x19e4, 0x1fff, 0x0c00);
-+			/*NonDC peak_th = 2times DC peak_th*/
-+			odm_set_bb_reg(dm, 0x19e4, 0x30000, 1);
-+			/*power for debug and auto test flow latch after ST*/
-+			odm_set_bb_reg(dm, 0x9f8, 0xc0000000, 3);
-+
-+			/*@low pulse width radar pattern will cause wrong drop*/
-+			/*@disable peak index should the same
-+			 *during the same short pulse (new mechan)
-+			 */
-+			odm_set_bb_reg(dm, 0x9f4, 0x80000000, 0);
-+
-+			/*@disable peak index should the same
-+			 *during the same short pulse (old mechan)
-+			 */
-+			odm_set_bb_reg(dm, 0x924, 0x20000000, 0);
-+
-+			/*@if peak index diff >=2, then drop the result*/
-+			odm_set_bb_reg(dm, 0x19e4, 0xe000, 2);
-+			if (region_domain == 2) {
-+				if ((c_channel >= 52) && (c_channel <= 64)) {
-+					/*pulse width hist th setting*/
-+					/*th1=2*04us*/
-+					odm_set_bb_reg(dm, 0x19e4,
-+						       0xff000000, 2);
-+					/*th2 = 3*0.4us, th3 = 4*0.4us
-+					 *th4 = 7*0.4, th5 = 34*0.4
-+					 */
-+					odm_set_bb_reg(dm, 0x19e8,
-+						       MASKDWORD, 0x22070403);
-+
-+					/*PRI hist th setting*/
-+					/*th1=42*32us*/
-+					odm_set_bb_reg(dm, 0x19b8,
-+						       0x00007f80, 42);
-+					/*th2=47*32us, th3=115*32us,
-+					 *th4=123*32us, th5=130*32us
-+					 */
-+					odm_set_bb_reg(dm, 0x19ec,
-+						       MASKDWORD, 0x827b732f);
-+				} else {
-+					/*pulse width hist th setting*/
-+					/*th1=2*04us*/
-+					odm_set_bb_reg(dm, 0x19e4,
-+						       0xff000000, 1);
-+					/*th2 = 13*0.4us, th3 = 26*0.4us
-+					 *th4 = 75*0.4us, th5 = 255*0.4us
-+					 */
-+					odm_set_bb_reg(dm, 0x19e8,
-+						       MASKDWORD, 0xff4b1a0d);
-+					/*PRI hist th setting*/
-+					/*th1=4*32us*/
-+
-+					odm_set_bb_reg(dm, 0x19b8,
-+						       0x00007f80, 4);
-+					/*th2=8*32us, th3=16*32us,
-+					 *th4=32*32us, th5=128*32=4096us
-+					 */
-+					odm_set_bb_reg(dm, 0x19ec,
-+						       MASKDWORD, 0x80201008);
-+				}
-+			}
-+			/*@ETSI*/
-+			else if (region_domain == 3) {
-+				/*pulse width hist th setting*/
-+				/*th1=2*04us*/
-+				odm_set_bb_reg(dm, 0x19e4, 0xff000000, 1);
-+				odm_set_bb_reg(dm, 0x19e8,
-+					       MASKDWORD, 0x68260d06);
-+				/*PRI hist th setting*/
-+				/*th1=7*32us*/
-+				odm_set_bb_reg(dm, 0x19b8, 0x00007f80, 7);
-+				/*th2=40*32us, th3=80*32us,
-+				 *th4=110*32us, th5=157*32=5024
-+				 */
-+				odm_set_bb_reg(dm, 0x19ec,
-+					       MASKDWORD, 0xc06e2010);
-+			}
-+			/*@FCC*/
-+			else if (region_domain == 1) {
-+				/*pulse width hist th setting*/
-+				/*th1=2*04us*/
-+				odm_set_bb_reg(dm, 0x19e4, 0xff000000, 2);
-+				/*th2 = 13*0.4us, th3 = 26*0.4us,
-+				 *th4 = 75*0.4us, th5 = 255*0.4us
-+				 */
-+				odm_set_bb_reg(dm, 0x19e8,
-+					       MASKDWORD, 0xff4b1a0d);
-+
-+				/*PRI hist th setting*/
-+				/*th1=4*32us*/
-+				odm_set_bb_reg(dm, 0x19b8, 0x00007f80, 4);
-+				/*th2=8*32us, th3=21*32us,
-+				 *th4=32*32us, th5=96*32=3072
-+				 */
-+				if (band_width == CHANNEL_WIDTH_20)
-+					odm_set_bb_reg(dm, 0x19ec,
-+						       MASKDWORD, 0x60282010);
-+				else
-+					odm_set_bb_reg(dm, 0x19ec,
-+						       MASKDWORD, 0x60282420);
-+			} else {
-+			}
-+		}
-+	} else if (dm->support_ic_type &
-+		   ODM_IC_JGR3_SERIES) {
-+		if (dm->radar_detect_dbg_parm_en) {
-+			phydm_radar_detect_with_dbg_parm(dm);
-+			enable = 1;
-+			goto exit;
-+		}
-+		if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
-+			odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);
-+			if (dm->support_ic_type & (ODM_RTL8814B)) {
-+				if (dm->seg1_dfs_flag == 1)
-+					odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
-+			}
-+			odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);
-+			odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
-+			odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);
-+			odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);
-+			odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);
-+		} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
-+			odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);
-+			if (dm->support_ic_type & (ODM_RTL8814B)) {
-+				if (dm->seg1_dfs_flag == 1)
-+					odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
-+			}
-+			odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);
-+			odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
-+			odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);
-+			odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);
-+			odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);
-+		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
-+			odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd);
-+			if (dm->support_ic_type & (ODM_RTL8814B)) {
-+				if (dm->seg1_dfs_flag == 1)
-+					odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1);
-+			}
-+			odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd);
-+			odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254);
-+			odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345);
-+			odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003);
-+			odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8);
-+		} else {
-+			/* not supported */
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "Unsupported dfs_region_domain:%d\n",
-+				  region_domain);
-+			goto exit;
-+		}
-+	#if (RTL8721D_SUPPORT)
-+	} else if (dm->support_ic_type & ODM_RTL8721D) {
-+		odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10);
-+		/*CCA MASK*/
-+		odm_set_bb_reg(dm, R_0xc38, 0x07c00000, 0x06);
-+		/*CCA Threshold*/
-+		odm_set_bb_reg(dm, R_0xc3c, 0x00000007, 0x0);
-+
-+		if (dm->radar_detect_dbg_parm_en) {
-+			phydm_radar_detect_with_dbg_parm(dm);
-+			enable = 1;
-+			goto exit;
-+		}
-+
-+		if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
-+			odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);
-+			odm_set_bb_reg(dm, R_0xf58, MASKDWORD, 0x354cd7dd);
-+			odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab25);
-+			odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fab98);
-+			odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc45029f);
-+
-+		} else if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
-+			odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);
-+			odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab25);
-+			odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fb398);
-+			odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc450e9d);
-+
-+			if (c_channel >= 52 && c_channel <= 64) {
-+				odm_set_bb_reg(dm, R_0xf58, MASKDWORD,
-+					       0x354cd7fd);
-+			} else {
-+				odm_set_bb_reg(dm, R_0xf58, MASKDWORD,
-+					       0x354cd7bd);
-+			}
-+		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
-+			odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8);
-+			odm_set_bb_reg(dm, R_0xf58, MASKDWORD, 0x3558d7bd);
-+			odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab35);
-+			odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fb398);
-+			odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc444e9d);
-+		} else {
-+			/* not supported */
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "Unsupported dfs_region_domain:%d\n",
-+				  region_domain);
-+			goto exit;
-+		}
-+
-+		/*if peak index -1~+1, use original NB method*/
-+		odm_set_bb_reg(dm, R_0xf70, 0x00070000, 0x7);
-+		odm_set_bb_reg(dm, R_0xf74, 0x000c0000, 0);
-+
-+		/*Turn off dfs scaling factor*/
-+		odm_set_bb_reg(dm, R_0xf70, 0x00080000, 0x0);
-+		/*NonDC peak_th = 2times DC peak_th*/
-+		odm_set_bb_reg(dm, R_0xf58, 0x00007800, 1);
-+
-+		/*low pulse width radar pattern will cause wrong drop*/
-+		/*disable peak index should the same*/
-+		/*during the same short pulse (new mechan)*/
-+		odm_set_bb_reg(dm, R_0xf70, 0x00100000, 0x0);
-+		/*if peak index diff >=2, then drop the result*/
-+		odm_set_bb_reg(dm, R_0xf70, 0x30000000, 0x2);
-+	#endif
-+	} else {
-+		/*not supported IC type*/
-+		PHYDM_DBG(dm, DBG_DFS, "Unsupported IC type:%d\n",
-+			  dm->support_ic_type);
-+		goto exit;
-+	}
-+
-+	enable = 1;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00007f00);
-+		dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0xa50, 0x000000f0);
-+		dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0xa48, 0x00c00000);
-+		dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xa50,
-+							     0x00f00000);
-+		dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xa4c,
-+							    0xf0000000);
-+		dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00030000);
-+		dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, R_0xa40,
-+							 0x30000000);
-+		dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, R_0xa44,
-+							 0x00000007);
-+	#if (RTL8721D_SUPPORT)
-+	} else if (dm->support_ic_type & (ODM_RTL8721D)) {
-+		dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xf54,
-+						     0x0000001f) << 2);
-+		dfs->st_l2h_cur += (u8)odm_get_bb_reg(dm, R_0xf58, 0xc0000000);
-+		dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0xf70, 0x03c00000);
-+		dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0xf5c, 0x00000030);
-+		dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xf70,
-+							     0x00007800);
-+		dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xf74,
-+							    0x0000000f);
-+		dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0xf58, 0x18000000);
-+		dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, R_0xf58,
-+							 0x00030000);
-+		dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm,
-+							 R_0xf58, 0x00007c00);
-+	#endif
-+	} else {
-+		dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff);
-+		dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0x918, 0x00001f00);
-+		dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0x918, 0x00030000);
-+		dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920,
-+							     0x000f0000);
-+		dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920,
-+							    0x00f00000);
-+		dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0x920, 0x00000300);
-+		dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, 0x924, 0x00000180);
-+		dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, 0x924, 0x00007000);
-+	}
-+
-+		phydm_dfs_parameter_init(dm);
-+
-+exit:
-+	if (enable) {
-+		phydm_radar_detect_reset(dm);
-+		PHYDM_DBG(dm, DBG_DFS, "on cch:%u, bw:%u\n", c_channel,
-+			  band_width);
-+	} else
-+		phydm_radar_detect_disable(dm);
-+}
-+
-+void phydm_dfs_parameter_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _DFS_STATISTICS *dfs = &dm->dfs;
-+
-+	u8 i;
-+	for (i = 0; i < 5; i++) {
-+		dfs->pulse_flag_hist[i] = 0;
-+		dfs->pulse_type_hist[i] = 0;
-+		dfs->radar_det_mask_hist[i] = 0;
-+		dfs->fa_inc_hist[i] = 0;
-+	}
-+
-+	/*@for dfs mode*/
-+	dfs->force_TP_mode = 0;
-+	dfs->sw_trigger_mode = 0;
-+	dfs->det_print = 0;
-+	dfs->det_print2 = 0;
-+	dfs->print_hist_rpt = 0;
-+	if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
-+		dfs->hist_cond_on = 1;
-+	else
-+		dfs->hist_cond_on = 0;
-+
-+	/*@for dynamic dfs*/
-+	dfs->pwdb_th = 8;
-+	dfs->fa_mask_th = 30 * (dfs->dfs_polling_time) / 100;
-+	dfs->st_l2h_min = 0x20;
-+	dfs->st_l2h_max = 0x4e;
-+	dfs->pwdb_scalar_factor = 12;
-+
-+	/*@for dfs histogram*/
-+	dfs->pri_hist_th = 5;
-+	dfs->pri_sum_g1_th = 9;
-+	dfs->pri_sum_g5_th = 5;
-+	dfs->pri_sum_g1_fcc_th = 4;		/*@FCC Type6*/
-+	dfs->pri_sum_g3_fcc_th = 6;
-+	dfs->pri_sum_safe_th = 50;
-+	dfs->pri_sum_safe_fcc_th = 110;		/*@30 for AP*/
-+	dfs->pri_sum_type4_th = 16;
-+	dfs->pri_sum_type6_th = 12;
-+	dfs->pri_sum_g5_under_g1_th = 4;
-+	dfs->pri_pw_diff_th = 4;
-+	dfs->pri_pw_diff_fcc_th = 8;
-+	dfs->pri_pw_diff_fcc_idle_th = 2;
-+	dfs->pri_pw_diff_w53_th = 10;
-+	dfs->pw_std_th = 7;			/*@FCC Type4*/
-+	dfs->pw_std_idle_th = 10;
-+	dfs->pri_std_th = 6;			/*@FCC Type3,4,6*/
-+	dfs->pri_std_idle_th = 10;
-+	dfs->pri_type1_upp_fcc_th = 110;
-+	dfs->pri_type1_low_fcc_th = 50;
-+	dfs->pri_type1_cen_fcc_th = 70;
-+	dfs->pw_g0_th = 8;
-+	dfs->pw_long_lower_th = 6;		/*@7->6*/
-+	dfs->pri_long_upper_th = 30;
-+	dfs->pw_long_lower_20m_th = 7;		/*@7 for AP*/
-+	dfs->pw_long_sum_upper_th = 60;
-+	dfs->type4_pw_max_cnt = 7;
-+	dfs->type4_safe_pri_sum_th = 5;
-+}
-+
-+void phydm_dfs_dynamic_setting(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _DFS_STATISTICS *dfs = &dm->dfs;
-+
-+	u8 peak_th_cur = 0, short_pulse_cnt_th_cur = 0;
-+	u8 long_pulse_cnt_th_cur = 0, three_peak_opt_cur = 0;
-+	u8 three_peak_th2_cur = 0;
-+	u8 peak_window_cur = 0;
-+	u8 region_domain = dm->dfs_region_domain;
-+	u8 c_channel = *dm->channel;
-+
-+	if (dm->rx_tp + dm->tx_tp <= 2) {
-+		dfs->idle_mode = 1;
-+		if (dfs->force_TP_mode)
-+			dfs->idle_mode = 0;
-+	} else {
-+		dfs->idle_mode = 0;
-+	}
-+
-+	if (dfs->idle_mode == 1) { /*@idle (no traffic)*/
-+		peak_th_cur = 3;
-+		short_pulse_cnt_th_cur = 6;
-+		long_pulse_cnt_th_cur = 9;
-+		peak_window_cur = 2;
-+		three_peak_opt_cur = 0;
-+		three_peak_th2_cur = 2;
-+		if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
-+			if (c_channel >= 52 && c_channel <= 64) {
-+				short_pulse_cnt_th_cur = 14;
-+				long_pulse_cnt_th_cur = 15;
-+				three_peak_th2_cur = 0;
-+			} else {
-+				short_pulse_cnt_th_cur = 6;
-+				three_peak_th2_cur = 0;
-+				long_pulse_cnt_th_cur = 10;
-+			}
-+		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
-+			three_peak_th2_cur = 0;
-+		} else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
-+			long_pulse_cnt_th_cur = 15;
-+			if (phydm_dfs_is_meteorology_channel(dm)) {
-+			/*need to add check cac end condition*/
-+				peak_th_cur = 2;
-+				three_peak_opt_cur = 0;
-+				three_peak_th2_cur = 0;
-+				short_pulse_cnt_th_cur = 7;
-+			} else {
-+				three_peak_opt_cur = 0;
-+				three_peak_th2_cur = 0;
-+				short_pulse_cnt_th_cur = 7;
-+			}
-+		} else /*@default: FCC*/
-+			three_peak_th2_cur = 0;
-+
-+	} else { /*@in service (with TP)*/
-+		peak_th_cur = 2;
-+		short_pulse_cnt_th_cur = 6;
-+		long_pulse_cnt_th_cur = 7;
-+		peak_window_cur = 2;
-+		three_peak_opt_cur = 0;
-+		three_peak_th2_cur = 2;
-+		if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
-+			if (c_channel >= 52 && c_channel <= 64) {
-+				long_pulse_cnt_th_cur = 15;
-+				/*@for high duty cycle*/
-+				short_pulse_cnt_th_cur = 5;
-+				three_peak_th2_cur = 0;
-+			} else {
-+				three_peak_opt_cur = 0;
-+				three_peak_th2_cur = 0;
-+				long_pulse_cnt_th_cur = 8;
-+			}
-+		} else if (region_domain == PHYDM_DFS_DOMAIN_FCC) {
-+			long_pulse_cnt_th_cur = 5;	/*for 80M FCC*/
-+			short_pulse_cnt_th_cur = 5;	/*for 80M FCC*/
-+		} else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
-+			long_pulse_cnt_th_cur = 15;
-+			short_pulse_cnt_th_cur = 5;
-+			three_peak_opt_cur = 0;
-+		}
-+	}
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		if (dfs->peak_th != peak_th_cur)
-+			odm_set_bb_reg(dm, R_0xa48, 0x00c00000, peak_th_cur);
-+		if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)
-+			odm_set_bb_reg(dm, R_0xa50, 0x00f00000,
-+				       short_pulse_cnt_th_cur);
-+		if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)
-+			odm_set_bb_reg(dm, R_0xa4c, 0xf0000000,
-+				       long_pulse_cnt_th_cur);
-+		if (dfs->peak_window != peak_window_cur)
-+			odm_set_bb_reg(dm, R_0xa40, 0x00030000,
-+				       peak_window_cur);
-+		if (dfs->three_peak_opt != three_peak_opt_cur)
-+			odm_set_bb_reg(dm, R_0xa40, 0x30000000,
-+				       three_peak_opt_cur);
-+		if (dfs->three_peak_th2 != three_peak_th2_cur)
-+			odm_set_bb_reg(dm, R_0xa44, 0x00000007,
-+				       three_peak_th2_cur);
-+	#if (RTL8721D_SUPPORT)
-+	} else if (dm->support_ic_type & (ODM_RTL8721D)) {
-+		if (dfs->peak_th != peak_th_cur)
-+			odm_set_bb_reg(dm, R_0xf5c, 0x00000030, peak_th_cur);
-+		if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)
-+			odm_set_bb_reg(dm, R_0xf70, 0x00007800,
-+				       short_pulse_cnt_th_cur);
-+		if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)
-+			odm_set_bb_reg(dm, R_0xf74, 0x0000000f,
-+				       long_pulse_cnt_th_cur);
-+		if (dfs->peak_window != peak_window_cur)
-+			odm_set_bb_reg(dm, R_0xf58, 0x18000000,
-+				       peak_window_cur);
-+		if (dfs->three_peak_opt != three_peak_opt_cur)
-+			odm_set_bb_reg(dm, R_0xf58, 0x00030000,
-+				       three_peak_opt_cur);
-+		if (dfs->three_peak_th2 != three_peak_th2_cur)
-+			odm_set_bb_reg(dm, R_0xf58, 0x00007c00,
-+				       three_peak_th2_cur);
-+	#endif
-+	} else {
-+		if (dfs->peak_th != peak_th_cur)
-+			odm_set_bb_reg(dm, R_0x918, 0x00030000, peak_th_cur);
-+		if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur)
-+			odm_set_bb_reg(dm, R_0x920, 0x000f0000,
-+				       short_pulse_cnt_th_cur);
-+		if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur)
-+			odm_set_bb_reg(dm, R_0x920, 0x00f00000,
-+				       long_pulse_cnt_th_cur);
-+		if (dfs->peak_window != peak_window_cur)
-+			odm_set_bb_reg(dm, R_0x920, 0x00000300,
-+				       peak_window_cur);
-+		if (dfs->three_peak_opt != three_peak_opt_cur)
-+			odm_set_bb_reg(dm, R_0x924, 0x00000180,
-+				       three_peak_opt_cur);
-+		if (dfs->three_peak_th2 != three_peak_th2_cur)
-+			odm_set_bb_reg(dm, R_0x924, 0x00007000,
-+				       three_peak_th2_cur);
-+	}
-+
-+	dfs->peak_th = peak_th_cur;
-+	dfs->short_pulse_cnt_th = short_pulse_cnt_th_cur;
-+	dfs->long_pulse_cnt_th = long_pulse_cnt_th_cur;
-+	dfs->peak_window = peak_window_cur;
-+	dfs->three_peak_opt = three_peak_opt_cur;
-+	dfs->three_peak_th2 = three_peak_th2_cur;
-+}
-+
-+boolean
-+phydm_radar_detect_dm_check(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _DFS_STATISTICS *dfs = &dm->dfs;
-+	u8 region_domain = dm->dfs_region_domain, index = 0;
-+
-+	u16 i = 0, j = 0, fa_count_cur = 0, fa_count_inc = 0;
-+	u16 total_fa_in_hist = 0, total_pulse_count_inc = 0;
-+	u16 short_pulse_cnt_inc = 0, short_pulse_cnt_cur = 0;
-+	u16 long_pulse_cnt_inc = 0, long_pulse_cnt_cur = 0;
-+	u32 regf98_value = 0, reg918_value = 0, reg91c_value = 0;
-+	u32 reg920_value = 0, reg924_value = 0, radar_rpt_reg_value = 0;
-+	u32 regf54_value = 0, regf58_value = 0, regf5c_value = 0;
-+	u32 regdf4_value = 0, regf70_value = 0, regf74_value = 0;
-+	#if (RTL8812F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
-+	u32 rega40_value = 0, rega44_value = 0, rega48_value = 0;
-+	u32 rega4c_value = 0, rega50_value = 0, rega54_value = 0;
-+	#endif
-+	#if (RTL8721D_SUPPORT)
-+	u32 reg908_value = 0, regdf4_value = 0;
-+	u32 regf54_value = 0, regf58_value = 0, regf5c_value = 0;
-+	u32 regf70_value = 0, regf74_value = 0;
-+	#endif
-+	boolean tri_short_pulse = 0, tri_long_pulse = 0, radar_type = 0;
-+	boolean fault_flag_det = 0, fault_flag_psd = 0, fa_flag = 0;
-+	boolean radar_detected = 0;
-+	u8 st_l2h_new = 0, fa_mask_th = 0, k = 0, sum = 0;
-+	u8 c_channel = *dm->channel;
-+
-+	/*@Get FA count during past 100ms, R_0xf48 for AC series*/
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		fa_count_cur = (u16)odm_get_bb_reg(dm, R_0x2d00, MASKLWORD);
-+	#if (RTL8721D_SUPPORT)
-+	else if (dm->support_ic_type & (ODM_RTL8721D)) {
-+		fa_count_cur = (u16)odm_get_bb_reg(dm,
-+						   ODM_REG_OFDM_FA_TYPE2_11N,
-+						   MASKHWORD);
-+		fa_count_cur += (u16)odm_get_bb_reg(dm,
-+						    ODM_REG_OFDM_FA_TYPE3_11N,
-+						    MASKLWORD);
-+		fa_count_cur += (u16)odm_get_bb_reg(dm,
-+						    ODM_REG_OFDM_FA_TYPE3_11N,
-+						    MASKHWORD);
-+		fa_count_cur += (u16)odm_get_bb_reg(dm,
-+						    ODM_REG_OFDM_FA_TYPE4_11N,
-+						    MASKLWORD);
-+		fa_count_cur += (u16)odm_get_bb_reg(dm,
-+						    ODM_REG_OFDM_FA_TYPE1_11N,
-+						    MASKLWORD);
-+		fa_count_cur += (u16)odm_get_bb_reg(dm,
-+						    ODM_REG_OFDM_FA_TYPE1_11N,
-+						    MASKHWORD);
-+	}
-+	#endif
-+	else
-+		fa_count_cur = (u16)odm_get_bb_reg(dm, R_0xf48, 0x0000ffff);
-+
-+	if (dfs->fa_count_pre == 0)
-+		fa_count_inc = 0;
-+	else if (fa_count_cur >= dfs->fa_count_pre)
-+		fa_count_inc = fa_count_cur - dfs->fa_count_pre;
-+	else
-+		fa_count_inc = fa_count_cur;
-+	dfs->fa_count_pre = fa_count_cur;
-+
-+	dfs->fa_inc_hist[dfs->mask_idx] = fa_count_inc;
-+
-+	for (i = 0; i < 5; i++)
-+		total_fa_in_hist = total_fa_in_hist + dfs->fa_inc_hist[i];
-+
-+	if (dfs->mask_idx >= 2)
-+		index = dfs->mask_idx - 2;
-+	else
-+		index = 5 + dfs->mask_idx - 2;
-+
-+	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |
-+				   ODM_RTL8197G| ODM_RTL8723F)) {
-+		radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00, 0xffffffff);
-+		short_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800)
-+					    >> 11);
-+		long_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x0fc00000)
-+					    >> 22);
-+	#if (RTL8721D_SUPPORT)
-+	} else if (dm->support_ic_type & (ODM_RTL8721D)) {
-+		reg908_value = (u32)odm_get_bb_reg(dm, R_0x908, MASKDWORD);
-+		odm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x254);
-+		regdf4_value = odm_get_bb_reg(dm, R_0xdf4, MASKDWORD);
-+		short_pulse_cnt_cur = (u16)((regdf4_value & 0x000ff000) >> 12);
-+		long_pulse_cnt_cur = (u16)((regdf4_value & 0x0fc00000) >> 22);
-+
-+		tri_short_pulse = (regdf4_value & BIT(20)) ? 1 : 0;
-+		tri_long_pulse = (regdf4_value & BIT(28)) ? 1 : 0;
-+		if (tri_short_pulse || tri_long_pulse) {
-+			odm_set_bb_reg(dm, R_0xf58, BIT(29), 0);
-+			odm_set_bb_reg(dm, R_0xf58, BIT(29), 1);
-+		}
-+	#endif
-+	} else if (dm->support_ic_type & (ODM_RTL8814B)) {
-+		if (dm->seg1_dfs_flag == 1)
-+			radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e20,
-+							     0xffffffff);
-+		else
-+			radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00,
-+							     0xffffffff);
-+		short_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800)
-+					    >> 11);
-+		long_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x0fc00000)
-+					    >> 22);
-+	} else {
-+		regf98_value = odm_get_bb_reg(dm, R_0xf98, 0xffffffff);
-+		short_pulse_cnt_cur = (u16)(regf98_value & 0x000000ff);
-+		long_pulse_cnt_cur = (u16)((regf98_value & 0x0000ff00) >> 8);
-+	}
-+
-+	/*@Get short pulse count, need carefully handle the counter overflow*/
-+	if (short_pulse_cnt_cur >= dfs->short_pulse_cnt_pre) {
-+		short_pulse_cnt_inc = short_pulse_cnt_cur -
-+				      dfs->short_pulse_cnt_pre;
-+	} else {
-+		short_pulse_cnt_inc = short_pulse_cnt_cur;
-+	}
-+	dfs->short_pulse_cnt_pre = short_pulse_cnt_cur;
-+
-+	/*@Get long pulse count, need carefully handle the counter overflow*/
-+	if (long_pulse_cnt_cur >= dfs->long_pulse_cnt_pre) {
-+		long_pulse_cnt_inc = long_pulse_cnt_cur -
-+				     dfs->long_pulse_cnt_pre;
-+	} else {
-+		long_pulse_cnt_inc = long_pulse_cnt_cur;
-+	}
-+	dfs->long_pulse_cnt_pre = long_pulse_cnt_cur;
-+
-+	total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc;
-+
-+	if (dfs->det_print) {
-+		PHYDM_DBG(dm, DBG_DFS,
-+			  "===============================================\n");
-+		PHYDM_DBG(dm, DBG_DFS, "FA_count_inc[%d]\n", fa_count_inc);
-+		if (dm->support_ic_type & (ODM_RTL8721D)) {
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "Init_Gain[%x] st_l2h_cur[%x] 0xdf4[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
-+				  dfs->igi_cur, dfs->st_l2h_cur, regdf4_value,
-+				  short_pulse_cnt_inc, long_pulse_cnt_inc);
-+			regf54_value = odm_get_bb_reg(dm, R_0xf54, MASKDWORD);
-+			regf58_value = odm_get_bb_reg(dm, R_0xf58, MASKDWORD);
-+			regf5c_value = odm_get_bb_reg(dm, R_0xf5c, MASKDWORD);
-+			regf70_value = odm_get_bb_reg(dm, R_0xf70, MASKDWORD);
-+			regf74_value = odm_get_bb_reg(dm, R_0xf74, MASKDWORD);
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "0xf54[%08x] 0xf58[%08x] 0xf5c[%08x] 0xf70[%08x] 0xf74[%08x]\n",
-+				  regf54_value, regf58_value, regf5c_value,
-+				  regf70_value, regf74_value);
-+		} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "Init_Gain[%x] st_l2h_cur[%x] 0x2dbc[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
-+				  dfs->igi_cur, dfs->st_l2h_cur,
-+				  radar_rpt_reg_value, short_pulse_cnt_inc,
-+				  long_pulse_cnt_inc);
-+		#if (RTL8812F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
-+			rega40_value = odm_get_bb_reg(dm, R_0xa40, MASKDWORD);
-+			rega44_value = odm_get_bb_reg(dm, R_0xa44, MASKDWORD);
-+			rega48_value = odm_get_bb_reg(dm, R_0xa48, MASKDWORD);
-+			rega4c_value = odm_get_bb_reg(dm, R_0xa4c, MASKDWORD);
-+			rega50_value = odm_get_bb_reg(dm, R_0xa50, MASKDWORD);
-+			rega54_value = odm_get_bb_reg(dm, R_0xa54, MASKDWORD);
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "0xa40[%08x] 0xa44[%08x] 0xa48[%08x] 0xa4c[%08x] 0xa50[%08x] 0xa54[%08x]\n",
-+				  rega40_value, rega44_value, rega48_value,
-+				  rega4c_value, rega50_value, rega54_value);
-+		#endif
-+		} else {
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
-+				  dfs->igi_cur, dfs->st_l2h_cur, regf98_value,
-+				  short_pulse_cnt_inc, long_pulse_cnt_inc);
-+			reg918_value = odm_get_bb_reg(dm, R_0x918,
-+						      0xffffffff);
-+			reg91c_value = odm_get_bb_reg(dm, R_0x91c,
-+						      0xffffffff);
-+			reg920_value = odm_get_bb_reg(dm, R_0x920,
-+						      0xffffffff);
-+			reg924_value = odm_get_bb_reg(dm, R_0x924,
-+						      0xffffffff);
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\n",
-+				  reg918_value, reg91c_value,
-+				  reg920_value, reg924_value);
-+		}
-+		PHYDM_DBG(dm, DBG_DFS, "Throughput: %dMbps\n",
-+			  (dm->rx_tp + dm->tx_tp));
-+
-+		PHYDM_DBG(dm, DBG_DFS,
-+			  "dfs_regdomain = %d, dbg_mode = %d, idle_mode = %d, print_hist_rpt = %d, hist_cond_on = %d\n",
-+			  region_domain, dfs->dbg_mode,
-+			  dfs->idle_mode, dfs->print_hist_rpt,
-+			  dfs->hist_cond_on);
-+	}
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		tri_short_pulse = (radar_rpt_reg_value & BIT(20)) ? 1 : 0;
-+		tri_long_pulse = (radar_rpt_reg_value & BIT(28)) ? 1 : 0;
-+	} else {
-+		tri_short_pulse = (regf98_value & BIT(17)) ? 1 : 0;
-+		tri_long_pulse = (regf98_value & BIT(19)) ? 1 : 0;
-+	}
-+
-+	if (tri_short_pulse) {
-+		phydm_radar_detect_reset(dm);
-+	}
-+	if (tri_long_pulse) {
-+		phydm_radar_detect_reset(dm);
-+		if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
-+			if (c_channel >= 52 && c_channel <= 64) {
-+				tri_long_pulse = 0;
-+			}
-+		}
-+		if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
-+			tri_long_pulse = 0;
-+		}
-+	}
-+
-+	st_l2h_new = dfs->st_l2h_cur;
-+	dfs->pulse_flag_hist[dfs->mask_idx] = tri_short_pulse | tri_long_pulse;
-+	dfs->pulse_type_hist[dfs->mask_idx] = (tri_long_pulse) ? 1 : 0;
-+
-+	/* PSD(not ready) */
-+
-+	fault_flag_det = 0;
-+	fault_flag_psd = 0;
-+	fa_flag = 0;
-+	if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
-+		fa_mask_th = dfs->fa_mask_th + 20;
-+	} else {
-+		fa_mask_th = dfs->fa_mask_th;
-+	}
-+	if (total_fa_in_hist >= fa_mask_th || dfs->igi_cur >= 0x30) {
-+		/* st_l2h_new = dfs->st_l2h_max; */
-+		dfs->radar_det_mask_hist[index] = 1;
-+		if (dfs->pulse_flag_hist[index] == 1) {
-+			dfs->pulse_flag_hist[index] = 0;
-+			if (dfs->det_print2) {
-+				PHYDM_DBG(dm, DBG_DFS,
-+					  "Radar is masked : FA mask\n");
-+			}
-+		}
-+		fa_flag = 1;
-+	} else {
-+		dfs->radar_det_mask_hist[index] = 0;
-+	}
-+
-+	if (dfs->det_print) {
-+		PHYDM_DBG(dm, DBG_DFS, "mask_idx: %d\n", dfs->mask_idx);
-+		PHYDM_DBG(dm, DBG_DFS, "radar_det_mask_hist: ");
-+		for (i = 0; i < 5; i++)
-+			PHYDM_DBG(dm, DBG_DFS, "%d ",
-+				  dfs->radar_det_mask_hist[i]);
-+		PHYDM_DBG(dm, DBG_DFS, "pulse_flag_hist: ");
-+		for (i = 0; i < 5; i++)
-+			PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->pulse_flag_hist[i]);
-+		PHYDM_DBG(dm, DBG_DFS, "fa_inc_hist: ");
-+		for (i = 0; i < 5; i++)
-+			PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->fa_inc_hist[i]);
-+		PHYDM_DBG(dm, DBG_DFS,
-+			  "\nfa_mask_th: %d, total_fa_in_hist: %d ",
-+			  fa_mask_th, total_fa_in_hist);
-+	}
-+
-+	sum = 0;
-+	for (k = 0; k < 5; k++) {
-+		if (dfs->radar_det_mask_hist[k] == 1)
-+			sum++;
-+	}
-+
-+	if (dfs->mask_hist_checked <= 5)
-+		dfs->mask_hist_checked++;
-+
-+	if (dfs->mask_hist_checked >= 5 && dfs->pulse_flag_hist[index]) {
-+		if (sum <= 2) {
-+			if (dfs->hist_cond_on) {
-+				/*return the value from hist_radar_detected*/
-+				radar_detected = phydm_dfs_hist_log(dm, index);
-+			} else {
-+				if (dfs->pulse_type_hist[index] == 0)
-+					dfs->radar_type = 0;
-+				else if (dfs->pulse_type_hist[index] == 1)
-+					dfs->radar_type = 1;
-+				radar_detected = 1;
-+				PHYDM_DBG(dm, DBG_DFS,
-+					  "Detected type %d radar signal!\n",
-+					  dfs->radar_type);
-+			}
-+		} else {
-+			fault_flag_det = 1;
-+			if (dfs->det_print2) {
-+				PHYDM_DBG(dm, DBG_DFS,
-+					  "Radar is masked : mask_hist large than thd\n");
-+			}
-+		}
-+	}
-+
-+	dfs->mask_idx++;
-+	if (dfs->mask_idx == 5)
-+		dfs->mask_idx = 0;
-+
-+	if (fault_flag_det == 0 && fault_flag_psd == 0 && fa_flag == 0) {
-+		if (dfs->igi_cur < 0x30) {
-+			st_l2h_new = dfs->st_l2h_min;
-+		}
-+	}
-+
-+	if (st_l2h_new != dfs->st_l2h_cur) {
-+		if (st_l2h_new < dfs->st_l2h_min) {
-+			dfs->st_l2h_cur = dfs->st_l2h_min;
-+		} else if (st_l2h_new > dfs->st_l2h_max)
-+			dfs->st_l2h_cur = dfs->st_l2h_max;
-+		else
-+			dfs->st_l2h_cur = st_l2h_new;
-+		/*odm_set_bb_reg(dm, R_0x91c, 0xff, dfs->st_l2h_cur);*/
-+
-+		dfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)
-+				    / 2 + dfs->pwdb_scalar_factor;
-+
-+		/*@limit the pwdb value to absolute lower bound 8*/
-+		dfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th);
-+
-+		/*@limit the pwdb value to absolute upper bound 0x1f*/
-+		dfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f);
-+
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+			odm_set_bb_reg(dm, R_0xa50, 0x000000f0,
-+				       dfs->pwdb_th_cur);
-+		#if (RTL8721D_SUPPORT)
-+		else if (dm->support_ic_type & ODM_RTL8721D) {
-+			odm_set_bb_reg(dm, R_0xf54, 0x0000001f,
-+				       ((dfs->st_l2h_cur & 0x0000007c) >> 2));
-+			odm_set_bb_reg(dm, R_0xf58, 0xc0000000,
-+				       (dfs->st_l2h_cur & 0x00000003));
-+			odm_set_bb_reg(dm, R_0xf70, 0x03c00000,
-+				       dfs->pwdb_th_cur);
-+		}
-+		#endif
-+		else
-+			odm_set_bb_reg(dm, R_0x918, 0x00001f00,
-+				       dfs->pwdb_th_cur);
-+	}
-+
-+	if (dfs->det_print) {
-+		PHYDM_DBG(dm, DBG_DFS,
-+			  "fault_flag_det[%d], fault_flag_psd[%d], DFS_detected [%d]\n",
-+			  fault_flag_det, fault_flag_psd, radar_detected);
-+	}
-+	#if (RTL8721D_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8721D))
-+		odm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908_value);
-+	#endif
-+
-+	return radar_detected;
-+}
-+
-+#if (RTL8814A_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT)
-+void phydm_dfs_histogram_radar_distinguish(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _DFS_STATISTICS *dfs = &dm->dfs;
-+	u8 region_domain = dm->dfs_region_domain;
-+	u8 c_channel = *dm->channel;
-+	u8 band_width = *dm->band_width;
-+
-+	u8 dfs_pw_thd1 = 0, dfs_pw_thd2 = 0, dfs_pw_thd3 = 0;
-+	u8 dfs_pw_thd4 = 0, dfs_pw_thd5 = 0;
-+	u8 dfs_pri_thd1 = 0, dfs_pri_thd2 = 0, dfs_pri_thd3 = 0;
-+	u8 dfs_pri_thd4 = 0, dfs_pri_thd5 = 0;
-+	u8 pri_th = 0, i = 0;
-+	u8 max_pri_idx = 0, max_pw_idx = 0, max_pri_cnt_th = 0;
-+	u8 max_pri_cnt_fcc_g1_th = 0, max_pri_cnt_fcc_g3_th = 0;
-+	u8 safe_pri_pw_diff_th = 0, safe_pri_pw_diff_fcc_th = 0;
-+	u8 safe_pri_pw_diff_w53_th = 0, safe_pri_pw_diff_fcc_idle_th = 0;
-+	u8 j = 0;
-+	u32 dfs_hist1_pw = 0, dfs_hist2_pw = 0, g_pw[6] = {0};
-+	u32 dfs_hist1_pri = 0, dfs_hist2_pri = 0, g_pri[6] = {0};
-+	u8 pw_sum_g0g5 = 0, pw_sum_g1g2g3g4 = 0;
-+	u8 pri_sum_g0g5 = 0, pri_sum_g1g2g3g4 = 0;
-+	u16 pw_sum_ss_g1g2g3g4 = 0, pri_sum_ss_g1g2g3g4 = 0;
-+	u8 max_pri_cnt = 0, max_pw_cnt = 0;
-+	#if (RTL8721D_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8721D))
-+		return;
-+	#endif
-+
-+	/*read pulse width hist report*/
-+	odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x1);
-+	dfs_hist1_pw = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);
-+	dfs_hist2_pw = odm_get_bb_reg(dm, 0xf74, 0xffffffff);
-+
-+	g_pw[0] = (unsigned int)((dfs_hist2_pw & 0xff000000) >> 24);
-+	g_pw[1] = (unsigned int)((dfs_hist2_pw & 0x00ff0000) >> 16);
-+	g_pw[2] = (unsigned int)((dfs_hist2_pw & 0x0000ff00) >> 8);
-+	g_pw[3] = (unsigned int)dfs_hist2_pw & 0x000000ff;
-+	g_pw[4] = (unsigned int)((dfs_hist1_pw & 0xff000000) >> 24);
-+	g_pw[5] = (unsigned int)((dfs_hist1_pw & 0x00ff0000) >> 16);
-+
-+	/*read pulse repetition interval hist report*/
-+	odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x3);
-+	dfs_hist1_pri = odm_get_bb_reg(dm, 0xf5c, 0xffffffff);
-+	dfs_hist2_pri = odm_get_bb_reg(dm, 0xf74, 0xffffffff);
-+	odm_set_bb_reg(dm, 0x19b4, 0x10000000, 1); /*reset histo report*/
-+	odm_set_bb_reg(dm, 0x19b4, 0x10000000, 0); /*@continue histo report*/
-+
-+	g_pri[0] = (unsigned int)((dfs_hist2_pri & 0xff000000) >> 24);
-+	g_pri[1] = (unsigned int)((dfs_hist2_pri & 0x00ff0000) >> 16);
-+	g_pri[2] = (unsigned int)((dfs_hist2_pri & 0x0000ff00) >> 8);
-+	g_pri[3] = (unsigned int)dfs_hist2_pri & 0x000000ff;
-+	g_pri[4] = (unsigned int)((dfs_hist1_pri & 0xff000000) >> 24);
-+	g_pri[5] = (unsigned int)((dfs_hist1_pri & 0x00ff0000) >> 16);
-+
-+	dfs->pri_cond1 = 0;
-+	dfs->pri_cond2 = 0;
-+	dfs->pri_cond3 = 0;
-+	dfs->pri_cond4 = 0;
-+	dfs->pri_cond5 = 0;
-+	dfs->pw_cond1 = 0;
-+	dfs->pw_cond2 = 0;
-+	dfs->pw_cond3 = 0;
-+	dfs->pri_type3_4_cond1 = 0;	/*@for ETSI*/
-+	dfs->pri_type3_4_cond2 = 0;	/*@for ETSI*/
-+	dfs->pw_long_cond1 = 0;		/*@for long radar*/
-+	dfs->pw_long_cond2 = 0;		/*@for long radar*/
-+	dfs->pri_long_cond1 = 0;	/*@for long radar*/
-+	dfs->pw_flag = 0;
-+	dfs->pri_flag = 0;
-+	dfs->pri_type3_4_flag = 0;	/*@for ETSI*/
-+	dfs->long_radar_flag = 0;
-+	dfs->pw_std = 0;	/*The std(var) of reasonable num of pw group*/
-+	dfs->pri_std = 0;	/*The std(var) of reasonable num of pri group*/
-+
-+	for (i = 0; i < 6; i++) {
-+		dfs->pw_hold_sum[i] = 0;
-+		dfs->pri_hold_sum[i] = 0;
-+	}
-+
-+	if (dfs->idle_mode == 1)
-+		pri_th = dfs->pri_hist_th;
-+	else
-+		pri_th = dfs->pri_hist_th - 1;
-+
-+	for (i = 0; i < 6; i++) {
-+		dfs->pw_hold[dfs->hist_idx][i] = (u8)g_pw[i];
-+		dfs->pri_hold[dfs->hist_idx][i] = (u8)g_pri[i];
-+		/*@collect whole histogram report may take some time
-+		 *so we add the counter of 2 time slots in FCC and ETSI
-+		 */
-+		dfs->pw_hold_sum[i] = dfs->pw_hold_sum[i] +
-+			dfs->pw_hold[(dfs->hist_idx + 1) % 3][i] +
-+			dfs->pw_hold[(dfs->hist_idx + 2) % 3][i];
-+		dfs->pri_hold_sum[i] = dfs->pri_hold_sum[i] +
-+			dfs->pri_hold[(dfs->hist_idx + 1) % 3][i] +
-+			dfs->pri_hold[(dfs->hist_idx + 2) % 3][i];
-+	}
-+	/*@For long radar type*/
-+	for (j = 1; j < 4; j++) {
-+		dfs->pw_long_hold_sum[i] = dfs->pw_long_hold_sum[i] +
-+			dfs->pw_hold[(dfs->hist_long_idx + j) % 4][i];
-+		dfs->pri_long_hold_sum[i] = dfs->pri_long_hold_sum[i] +
-+			dfs->pri_hold[(dfs->hist_long_idx + j) % 4][i];
-+	}
-+
-+	dfs->hist_idx++;
-+	if (dfs->hist_idx == 3)
-+		dfs->hist_idx = 0;
-+	dfs->hist_long_idx++;
-+	if (dfs->hist_long_idx == 4)
-+		dfs->hist_long_idx = 0;
-+
-+	max_pri_cnt = 0;
-+	max_pri_idx = 0;
-+	max_pw_cnt = 0;
-+	max_pw_idx = 0;
-+	max_pri_cnt_th = dfs->pri_sum_g1_th;
-+	max_pri_cnt_fcc_g1_th = dfs->pri_sum_g1_fcc_th;
-+	max_pri_cnt_fcc_g3_th = dfs->pri_sum_g3_fcc_th;
-+	safe_pri_pw_diff_th = dfs->pri_pw_diff_th;
-+	safe_pri_pw_diff_fcc_th = dfs->pri_pw_diff_fcc_th;
-+	safe_pri_pw_diff_fcc_idle_th = dfs->pri_pw_diff_fcc_idle_th;
-+	safe_pri_pw_diff_w53_th = dfs->pri_pw_diff_w53_th;
-+
-+	/*@g1 to g4 is the reseasonable range of pri and pw*/
-+	for (i = 1; i <= 4; i++) {
-+		if (dfs->pri_hold_sum[i] > max_pri_cnt) {
-+			max_pri_cnt = dfs->pri_hold_sum[i];
-+			max_pri_idx = i;
-+		}
-+		if (dfs->pw_hold_sum[i] > max_pw_cnt) {
-+			max_pw_cnt = dfs->pw_hold_sum[i];
-+			max_pw_idx = i;
-+		}
-+		if (dfs->pri_hold_sum[i] >= pri_th)
-+			dfs->pri_cond1 = 1;
-+	}
-+
-+	pri_sum_g0g5 = dfs->pri_hold_sum[0];
-+	if (pri_sum_g0g5 == 0)
-+		pri_sum_g0g5 = 1;
-+	pri_sum_g1g2g3g4 = dfs->pri_hold_sum[1] + dfs->pri_hold_sum[2]
-+			 + dfs->pri_hold_sum[3] + dfs->pri_hold_sum[4];
-+
-+	/*pw will reduce because of dc, so we do not treat g0 as illegal group*/
-+	pw_sum_g0g5 = dfs->pw_hold_sum[5];
-+	if (pw_sum_g0g5 == 0)
-+		pw_sum_g0g5 = 1;
-+	pw_sum_g1g2g3g4 = dfs->pw_hold_sum[1] + dfs->pw_hold_sum[2] +
-+				dfs->pw_hold_sum[3] + dfs->pw_hold_sum[4];
-+
-+	/*@Calculate the variation from g1 to g4*/
-+	for (i = 1; i < 5; i++) {
-+		/*Sum of square*/
-+		pw_sum_ss_g1g2g3g4 = pw_sum_ss_g1g2g3g4 +
-+		(dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4)) *
-+		(dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4));
-+		pri_sum_ss_g1g2g3g4 = pri_sum_ss_g1g2g3g4 +
-+		(dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4)) *
-+		(dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4));
-+	}
-+	/*The value may less than the normal variance,
-+	 *since the variable type is int (not float)
-+	 */
-+		dfs->pw_std = (u8)(pw_sum_ss_g1g2g3g4 / 4);
-+		dfs->pri_std = (u8)(pri_sum_ss_g1g2g3g4 / 4);
-+
-+	if (region_domain == 1) {
-+		dfs->pri_type3_4_flag = 1;	/*@ETSI flag*/
-+
-+		/*(OTA) Cancel long PRI case*/
-+		dfs->pri_cond2 = 1;
-+
-+		/*reasonable group shouldn't large*/
-+		if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2 &&
-+		    pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th)
-+			dfs->pri_cond3 = 1;
-+
-+		/*@Cancel the condition that the abs between pri and pw*/
-+		if (dfs->pri_std >= dfs->pri_std_th)
-+			dfs->pri_cond4 = 1;
-+		else if (max_pri_idx == 1 &&
-+			 max_pri_cnt >= max_pri_cnt_fcc_g1_th)
-+			dfs->pri_cond4 = 1;
-+
-+		/*(OTA) Cancel the condition (type 3,4 distinction)*/
-+		dfs->pri_cond5 = 1;
-+
-+		if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 &&
-+		    dfs->pri_cond4 && dfs->pri_cond5)
-+			dfs->pri_flag = 1;
-+
-+		/* PW judgment conditions for short radar type */
-+		/*ratio of reasonable and illegal group && g5 should be zero*/
-+		if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) &&
-+		    (dfs->pw_hold_sum[5] <= 1))
-+			dfs->pw_cond1 = 1;
-+		/*unreasonable group*/
-+		if (dfs->pw_hold_sum[4] == 0 && dfs->pw_hold_sum[5] == 0)
-+			dfs->pw_cond2 = 1;
-+		/*pw's std (short radar) should be large(=7)*/
-+		if (dfs->pw_std >= dfs->pw_std_th)
-+			dfs->pw_cond3 = 1;
-+		if (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3)
-+			dfs->pw_flag = 1;
-+
-+		/* @Judgment conditions of long radar type */
-+		if (band_width == CHANNEL_WIDTH_20) {
-+			if (dfs->pw_long_hold_sum[4] >=
-+			    dfs->pw_long_lower_20m_th)
-+				dfs->pw_long_cond1 = 1;
-+		} else{
-+			if (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th)
-+				dfs->pw_long_cond1 = 1;
-+		}
-+		/* @Disable the condition that dfs->pw_long_hold_sum[1] */
-+		if (dfs->pw_long_hold_sum[2] + dfs->pw_long_hold_sum[3] +
-+		    dfs->pw_long_hold_sum[4] <= dfs->pw_long_sum_upper_th &&
-+		    dfs->pw_long_hold_sum[2] <= dfs->pw_long_hold_sum[4] &&
-+		    dfs->pw_long_hold_sum[3] <= dfs->pw_long_hold_sum[4])
-+			dfs->pw_long_cond2 = 1;
-+		/*@g4 should be large for long radar*/
-+		if (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th)
-+			dfs->pri_long_cond1 = 1;
-+		if (dfs->pw_long_cond1 && dfs->pw_long_cond2 &&
-+		    dfs->pri_long_cond1)
-+			dfs->long_radar_flag = 1;
-+	} else if (region_domain == 2) {
-+		dfs->pri_type3_4_flag = 1;	/*@ETSI flag*/
-+
-+		/*PRI judgment conditions for short radar type*/
-+		if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2)
-+			dfs->pri_cond2 = 1;
-+
-+		/*reasonable group shouldn't too large*/
-+		if (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th)
-+			dfs->pri_cond3 = 1;
-+
-+		/*Cancel the abs diff between pri and pw for idle mode (thr=2)*/
-+		dfs->pri_cond4 = 1;
-+
-+		if (dfs->idle_mode == 1) {
-+			if (dfs->pri_std >= dfs->pri_std_idle_th) {
-+				if (max_pw_idx == 3 &&
-+				    pri_sum_g1g2g3g4 <= dfs->pri_sum_type4_th){
-+		/*To distinguish between type 4 radar and false detection*/
-+					dfs->pri_cond5 = 1;
-+				} else if (max_pw_idx == 1 &&
-+					   pri_sum_g1g2g3g4 >=
-+					   dfs->pri_sum_type6_th) {
-+		/*To distinguish between type 6 radar and false detection*/
-+					dfs->pri_cond5 = 1;
-+				} else {
-+		/*pri variation of short radar should be large (idle mode)*/
-+					dfs->pri_cond5 = 1;
-+				}
-+			}
-+		} else {
-+		/*pri variation of short radar should be large (TP mode)*/
-+			if (dfs->pri_std >= dfs->pri_std_th)
-+				dfs->pri_cond5 = 1;
-+		}
-+
-+		if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 &&
-+		    dfs->pri_cond4 && dfs->pri_cond5)
-+			dfs->pri_flag = 1;
-+
-+		/* PW judgment conditions for short radar type */
-+		if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) &&
-+		    (dfs->pw_hold_sum[5] <= 1))
-+		/*ratio of reasonable and illegal group && g5 should be zero*/
-+			dfs->pw_cond1 = 1;
-+
-+		if ((c_channel >= 52) && (c_channel <= 64))
-+			dfs->pw_cond2 = 1;
-+		/*unreasonable group shouldn't too large*/
-+		else if (dfs->pw_hold_sum[0] <= dfs->pw_g0_th)
-+			dfs->pw_cond2 = 1;
-+
-+		if (dfs->idle_mode == 1) {
-+		/*pw variation of short radar should be large (idle mode)*/
-+			if (dfs->pw_std >= dfs->pw_std_idle_th)
-+				dfs->pw_cond3 = 1;
-+		} else {
-+		/*pw variation of short radar should be large (TP mode)*/
-+			if (dfs->pw_std >= dfs->pw_std_th)
-+				dfs->pw_cond3 = 1;
-+		}
-+		if (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3)
-+			dfs->pw_flag = 1;
-+
-+		/* @Judgment conditions of long radar type */
-+		if (band_width == CHANNEL_WIDTH_20) {
-+			if (dfs->pw_long_hold_sum[4] >=
-+			    dfs->pw_long_lower_20m_th)
-+				dfs->pw_long_cond1 = 1;
-+		} else{
-+			if (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th)
-+				dfs->pw_long_cond1 = 1;
-+		}
-+		if (dfs->pw_long_hold_sum[1] + dfs->pw_long_hold_sum[2] +
-+		    dfs->pw_long_hold_sum[3] + dfs->pw_long_hold_sum[4]
-+		    <= dfs->pw_long_sum_upper_th)
-+			dfs->pw_long_cond2 = 1;
-+		/*@g4 should be large for long radar*/
-+		if (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th)
-+			dfs->pri_long_cond1 = 1;
-+		if (dfs->pw_long_cond1 &&
-+		    dfs->pw_long_cond2 && dfs->pri_long_cond1)
-+			dfs->long_radar_flag = 1;
-+	} else if (region_domain == 3) {
-+		/*ratio of reasonable group and illegal group */
-+		if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2)
-+			dfs->pri_cond2 = 1;
-+
-+		if (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_th)
-+			dfs->pri_cond3 = 1;
-+
-+		/*@Cancel the condition that the abs between pri and pw*/
-+			dfs->pri_cond4 = 1;
-+
-+		if (dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_th)
-+			dfs->pri_cond5 = 1;
-+
-+		if (band_width == CHANNEL_WIDTH_40) {
-+			if (max_pw_idx == 4) {
-+				if (max_pw_cnt >= dfs->type4_pw_max_cnt &&
-+				    pri_sum_g1g2g3g4 >=
-+				    dfs->type4_safe_pri_sum_th) {
-+					dfs->pri_cond1 = 1;
-+					dfs->pri_cond4 = 1;
-+					dfs->pri_type3_4_cond1 = 1;
-+				}
-+			}
-+		}
-+
-+		if (dfs->pri_cond1 && dfs->pri_cond2 &&
-+		    dfs->pri_cond3 && dfs->pri_cond4 && dfs->pri_cond5)
-+			dfs->pri_flag = 1;
-+
-+		if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2))
-+			dfs->pw_flag = 1;
-+
-+		/*@max num pri group is g1 means radar type3 or type4*/
-+		if (max_pri_idx == 1) {
-+			if (max_pri_cnt >= max_pri_cnt_th)
-+				dfs->pri_type3_4_cond1 = 1;
-+			if (dfs->pri_hold_sum[4] <=
-+			    dfs->pri_sum_g5_under_g1_th &&
-+			    dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_under_g1_th)
-+				dfs->pri_type3_4_cond2 = 1;
-+		} else {
-+			dfs->pri_type3_4_cond1 = 1;
-+			dfs->pri_type3_4_cond2 = 1;
-+		}
-+		if (dfs->pri_type3_4_cond1 && dfs->pri_type3_4_cond2)
-+			dfs->pri_type3_4_flag = 1;
-+	} else {
-+	}
-+
-+	if (dfs->print_hist_rpt) {
-+		dfs_pw_thd1 = (u8)odm_get_bb_reg(dm, 0x19e4, 0xff000000);
-+		dfs_pw_thd2 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x000000ff);
-+		dfs_pw_thd3 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x0000ff00);
-+		dfs_pw_thd4 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x00ff0000);
-+		dfs_pw_thd5 = (u8)odm_get_bb_reg(dm, 0x19e8, 0xff000000);
-+
-+		dfs_pri_thd1 = (u8)odm_get_bb_reg(dm, 0x19b8, 0x7F80);
-+		dfs_pri_thd2 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x000000ff);
-+		dfs_pri_thd3 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x0000ff00);
-+		dfs_pri_thd4 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x00ff0000);
-+		dfs_pri_thd5 = (u8)odm_get_bb_reg(dm, 0x19ec, 0xff000000);
-+
-+		PHYDM_DBG(dm, DBG_DFS, "\ndfs_pw_thd=%d %d %d %d %d\n",
-+			  dfs_pw_thd1, dfs_pw_thd2, dfs_pw_thd3,
-+			  dfs_pw_thd4, dfs_pw_thd5);
-+		PHYDM_DBG(dm, DBG_DFS, "-----pulse width hist-----\n");
-+		PHYDM_DBG(dm, DBG_DFS, "dfs_hist_pw=%x %x\n",
-+			  dfs_hist1_pw, dfs_hist2_pw);
-+		PHYDM_DBG(dm, DBG_DFS, "g_pw_hist = %x %x %x %x %x %x\n",
-+			  g_pw[0], g_pw[1], g_pw[2], g_pw[3],
-+			  g_pw[4], g_pw[5]);
-+		PHYDM_DBG(dm, DBG_DFS, "dfs_pri_thd=%d %d %d %d %d\n",
-+			  dfs_pri_thd1, dfs_pri_thd2, dfs_pri_thd3,
-+			  dfs_pri_thd4, dfs_pri_thd5);
-+		PHYDM_DBG(dm, DBG_DFS, "-----pulse interval hist-----\n");
-+		PHYDM_DBG(dm, DBG_DFS, "dfs_hist_pri=%x %x\n",
-+			  dfs_hist1_pri, dfs_hist2_pri);
-+		PHYDM_DBG(dm, DBG_DFS,
-+			  "g_pri_hist = %x %x %x %x %x %x, pw_flag = %d, pri_flag = %d\n",
-+			  g_pri[0], g_pri[1], g_pri[2], g_pri[3], g_pri[4],
-+			  g_pri[5], dfs->pw_flag, dfs->pri_flag);
-+		if (region_domain == 1 || region_domain == 3) {
-+			PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
-+				  (dfs->hist_idx + 2) % 3);
-+		} else {
-+			PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
-+				  (dfs->hist_idx + 3) % 4);
-+		}
-+		PHYDM_DBG(dm, DBG_DFS, "hist_long_idx= %d\n",
-+			  (dfs->hist_long_idx + 299) % 300);
-+		PHYDM_DBG(dm, DBG_DFS,
-+			  "pw_sum_g0g5 = %d, pw_sum_g1g2g3g4 = %d\n",
-+			  pw_sum_g0g5, pw_sum_g1g2g3g4);
-+		PHYDM_DBG(dm, DBG_DFS,
-+			  "pri_sum_g0g5 = %d, pri_sum_g1g2g3g4 = %d\n",
-+			  pri_sum_g0g5, pri_sum_g1g2g3g4);
-+		PHYDM_DBG(dm, DBG_DFS, "pw_hold_sum = %d %d %d %d %d %d\n",
-+			  dfs->pw_hold_sum[0], dfs->pw_hold_sum[1],
-+			  dfs->pw_hold_sum[2], dfs->pw_hold_sum[3],
-+			  dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]);
-+		PHYDM_DBG(dm, DBG_DFS, "pri_hold_sum = %d %d %d %d %d %d\n",
-+			  dfs->pri_hold_sum[0], dfs->pri_hold_sum[1],
-+			  dfs->pri_hold_sum[2], dfs->pri_hold_sum[3],
-+			  dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]);
-+		PHYDM_DBG(dm, DBG_DFS, "pw_long_hold_sum = %d %d %d %d %d %d\n",
-+			  dfs->pw_long_hold_sum[0], dfs->pw_long_hold_sum[1],
-+			  dfs->pw_long_hold_sum[2], dfs->pw_long_hold_sum[3],
-+			  dfs->pw_long_hold_sum[4], dfs->pw_long_hold_sum[5]);
-+		PHYDM_DBG(dm, DBG_DFS,
-+			  "pri_long_hold_sum = %d %d %d %d %d %d\n",
-+			  dfs->pri_long_hold_sum[0], dfs->pri_long_hold_sum[1],
-+			  dfs->pri_long_hold_sum[2], dfs->pri_long_hold_sum[3],
-+			  dfs->pri_long_hold_sum[4], dfs->pri_long_hold_sum[5]);
-+		PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n", dfs->idle_mode);
-+		PHYDM_DBG(dm, DBG_DFS, "pw_standard = %d\n", dfs->pw_std);
-+		PHYDM_DBG(dm, DBG_DFS, "pri_standard = %d\n", dfs->pri_std);
-+		PHYDM_DBG(dm, DBG_DFS, "\n");
-+		PHYDM_DBG(dm, DBG_DFS,
-+			  "pri_cond1 = %d, pri_cond2 = %d, pri_cond3 = %d, pri_cond4 = %d, pri_cond5 = %d\n",
-+			  dfs->pri_cond1, dfs->pri_cond2, dfs->pri_cond3,
-+			  dfs->pri_cond4, dfs->pri_cond5);
-+		PHYDM_DBG(dm, DBG_DFS,
-+			  "bandwidth = %d, pri_th = %d, max_pri_cnt_th = %d, safe_pri_pw_diff_th = %d\n",
-+			  band_width, pri_th, max_pri_cnt_th,
-+			  safe_pri_pw_diff_th);
-+	}
-+}
-+#endif
-+boolean phydm_dfs_hist_log(void *dm_void, u8 index)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _DFS_STATISTICS *dfs = &dm->dfs;
-+	u8 i = 0, j = 0;
-+	boolean hist_radar_detected = 0;
-+
-+	if (dfs->pulse_type_hist[index] == 0) {
-+		dfs->radar_type = 0;
-+		if (dfs->pw_flag && dfs->pri_flag &&
-+		    dfs->pri_type3_4_flag) {
-+			hist_radar_detected = 1;
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "Detected type %d radar signal!\n",
-+				  dfs->radar_type);
-+			if (dfs->det_print2) {
-+				PHYDM_DBG(dm, DBG_DFS,
-+					  "hist_idx= %d\n",
-+					  (dfs->hist_idx + 3) % 4);
-+				for (j = 0; j < 4; j++) {
-+				for (i = 0; i < 6; i++) {
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "pri_hold = %d ",
-+						  dfs->pri_hold[j][i]);
-+				}
-+				PHYDM_DBG(dm, DBG_DFS, "\n");
-+				}
-+				PHYDM_DBG(dm, DBG_DFS, "\n");
-+				for (j = 0; j < 4; j++) {
-+				for (i = 0; i < 6; i++) {
-+					PHYDM_DBG(dm, DBG_DFS, "pw_hold = %d ",
-+						  dfs->pw_hold[j][i]);
-+				}
-+					PHYDM_DBG(dm, DBG_DFS, "\n");
-+				}
-+				PHYDM_DBG(dm, DBG_DFS, "\n");
-+				PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
-+					  dfs->idle_mode);
-+				PHYDM_DBG(dm, DBG_DFS,
-+					  "pw_hold_sum = %d %d %d %d %d %d\n",
-+					  dfs->pw_hold_sum[0],
-+					  dfs->pw_hold_sum[1],
-+					  dfs->pw_hold_sum[2],
-+					  dfs->pw_hold_sum[3],
-+					  dfs->pw_hold_sum[4],
-+					  dfs->pw_hold_sum[5]);
-+				PHYDM_DBG(dm, DBG_DFS,
-+					  "pri_hold_sum = %d %d %d %d %d %d\n",
-+					  dfs->pri_hold_sum[0],
-+					  dfs->pri_hold_sum[1],
-+					  dfs->pri_hold_sum[2],
-+					  dfs->pri_hold_sum[3],
-+					  dfs->pri_hold_sum[4],
-+					  dfs->pri_hold_sum[5]);
-+			}
-+		} else {
-+		if (dfs->det_print2) {
-+			if (dfs->pulse_flag_hist[index] &&
-+			    dfs->pri_flag == 0) {
-+				PHYDM_DBG(dm, DBG_DFS, "pri_variation = %d\n",
-+					  dfs->pri_std);
-+				PHYDM_DBG(dm, DBG_DFS,
-+					  "PRI criterion is not satisfied!\n");
-+				if (dfs->pri_cond1 == 0)
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "pri_cond1 is not satisfied!\n");
-+				if (dfs->pri_cond2 == 0)
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "pri_cond2 is not satisfied!\n");
-+				if (dfs->pri_cond3 == 0)
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "pri_cond3 is not satisfied!\n");
-+				if (dfs->pri_cond4 == 0)
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "pri_cond4 is not satisfied!\n");
-+				if (dfs->pri_cond5 == 0)
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "pri_cond5 is not satisfied!\n");
-+			}
-+			if (dfs->pulse_flag_hist[index] &&
-+			    dfs->pw_flag == 0) {
-+				PHYDM_DBG(dm, DBG_DFS, "pw_variation = %d\n",
-+					  dfs->pw_std);
-+				PHYDM_DBG(dm, DBG_DFS,
-+					  "PW criterion is not satisfied!\n");
-+				if (dfs->pw_cond1 == 0)
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "pw_cond1 is not satisfied!\n");
-+				if (dfs->pw_cond2 == 0)
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "pw_cond2 is not satisfied!\n");
-+				if (dfs->pw_cond3 == 0)
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "pw_cond3 is not satisfied!\n");
-+			}
-+			if (dfs->pulse_flag_hist[index] &&
-+			    (dfs->pri_type3_4_flag == 0)) {
-+				PHYDM_DBG(dm, DBG_DFS,
-+					  "pri_type3_4 criterion is not satisfied!\n");
-+				if (dfs->pri_type3_4_cond1 == 0)
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "pri_type3_4_cond1 is not satisfied!\n");
-+				if (dfs->pri_type3_4_cond2 == 0)
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "pri_type3_4_cond2 is not satisfied!\n");
-+			}
-+			PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n",
-+				  (dfs->hist_idx + 3) % 4);
-+			for (j = 0; j < 4; j++) {
-+				for (i = 0; i < 6; i++) {
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "pri_hold = %d ",
-+						  dfs->pri_hold[j][i]);
-+				}
-+				PHYDM_DBG(dm, DBG_DFS, "\n");
-+			}
-+			PHYDM_DBG(dm, DBG_DFS, "\n");
-+			for (j = 0; j < 4; j++) {
-+				for (i = 0; i < 6; i++)
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "pw_hold = %d ",
-+						  dfs->pw_hold[j][i]);
-+				PHYDM_DBG(dm, DBG_DFS, "\n");
-+			}
-+			PHYDM_DBG(dm, DBG_DFS, "\n");
-+			PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
-+				  dfs->idle_mode);
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "pw_hold_sum = %d %d %d %d %d %d\n",
-+				  dfs->pw_hold_sum[0], dfs->pw_hold_sum[1],
-+				  dfs->pw_hold_sum[2], dfs->pw_hold_sum[3],
-+				  dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]);
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "pri_hold_sum = %d %d %d %d %d %d\n",
-+				  dfs->pri_hold_sum[0], dfs->pri_hold_sum[1],
-+				  dfs->pri_hold_sum[2], dfs->pri_hold_sum[3],
-+				  dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]);
-+		}
-+		}
-+	} else {
-+		dfs->radar_type = 1;
-+		if (dfs->det_print2) {
-+			PHYDM_DBG(dm, DBG_DFS, "\n");
-+			PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n",
-+				  dfs->idle_mode);
-+		}
-+		/* @Long radar should satisfy three conditions */
-+		if (dfs->long_radar_flag == 1) {
-+			hist_radar_detected = 1;
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "Detected type %d radar signal!\n",
-+				  dfs->radar_type);
-+		} else {
-+			if (dfs->det_print2) {
-+				if (dfs->pw_long_cond1 == 0)
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "--pw_long_cond1 is not satisfied!--\n");
-+				if (dfs->pw_long_cond2 == 0)
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "--pw_long_cond2 is not satisfied!--\n");
-+				if (dfs->pri_long_cond1 == 0)
-+					PHYDM_DBG(dm, DBG_DFS,
-+						  "--pri_long_cond1 is not satisfied!--\n");
-+			}
-+		}
-+	}
-+	return hist_radar_detected;
-+}
-+
-+boolean phydm_radar_detect(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _DFS_STATISTICS *dfs = &dm->dfs;
-+	boolean radar_detected = false;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		dfs->igi_cur = (u8)odm_get_bb_reg(dm, R_0x1d70, 0x0000007f);
-+		dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00007f00);
-+	#if (RTL8721D_SUPPORT)
-+	} else if (dm->support_ic_type & (ODM_RTL8721D)) {
-+		dfs->st_l2h_cur = (u8)(odm_get_bb_reg(dm, R_0xf54,
-+						      0x0000001f) << 2);
-+		dfs->st_l2h_cur += (u8)odm_get_bb_reg(dm, R_0xf58, 0xc0000000);
-+	#endif
-+	} else {
-+		dfs->igi_cur = (u8)odm_get_bb_reg(dm, R_0xc50, 0x0000007f);
-+		dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff);
-+	}
-+
-+	/* @dynamic pwdb calibration */
-+	if (dfs->igi_pre != dfs->igi_cur) {
-+		dfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur)
-+				    / 2 + dfs->pwdb_scalar_factor;
-+
-+		/* @limit the pwdb value to absolute lower bound 0xa */
-+		dfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th);
-+		/* @limit the pwdb value to absolute upper bound 0x1f */
-+		dfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f);
-+
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+			odm_set_bb_reg(dm, R_0xa50, 0x000000f0,
-+				       dfs->pwdb_th_cur);
-+		#if (RTL8721D_SUPPORT)
-+		else if (dm->support_ic_type & (ODM_RTL8721D))
-+			odm_set_bb_reg(dm, R_0xf70, 0x03c00000,
-+				       dfs->pwdb_th_cur);
-+		#endif
-+		else
-+			odm_set_bb_reg(dm, R_0x918, 0x00001f00,
-+				       dfs->pwdb_th_cur);
-+	}
-+	dfs->igi_pre = dfs->igi_cur;
-+
-+	phydm_dfs_dynamic_setting(dm);
-+	#if (RTL8814A_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
-+		phydm_dfs_histogram_radar_distinguish(dm);
-+	#endif
-+	radar_detected = phydm_radar_detect_dm_check(dm);
-+
-+	if (radar_detected) {
-+		PHYDM_DBG(dm, DBG_DFS,
-+			  "Radar detect: %d\n", radar_detected);
-+		phydm_radar_detect_reset(dm);
-+		if (dfs->dbg_mode == 1) {
-+			PHYDM_DBG(dm, DBG_DFS,
-+				  "Radar is detected in DFS dbg mode.\n");
-+			radar_detected = 0;
-+		}
-+	}
-+
-+	if (dfs->sw_trigger_mode) {
-+		radar_detected = 1;
-+		PHYDM_DBG(dm, DBG_DFS,
-+			  "Radar is detected in DFS SW trigger mode.\n");
-+	}
-+
-+	return radar_detected;
-+}
-+
-+void phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used,
-+			char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _DFS_STATISTICS *dfs = &dm->dfs;
-+	char help[] = "-h";
-+	u32 argv[5] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{0} pri_hist_th = %d\n", dfs->pri_hist_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{1} pri_sum_g1_th = %d\n", dfs->pri_sum_g1_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{2} pri_sum_g5_th = %d\n", dfs->pri_sum_g5_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{3} pri_sum_g1_fcc_th = %d\n",
-+			 dfs->pri_sum_g1_fcc_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{4} pri_sum_g3_fcc_th = %d\n",
-+			 dfs->pri_sum_g3_fcc_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{5} pri_sum_safe_fcc_th = %d\n",
-+			 dfs->pri_sum_safe_fcc_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{6} pri_sum_type4_th = %d\n", dfs->pri_sum_type4_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{7} pri_sum_type6_th = %d\n", dfs->pri_sum_type6_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{8} pri_sum_safe_th = %d\n", dfs->pri_sum_safe_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{9} pri_sum_g5_under_g1_th = %d\n",
-+			 dfs->pri_sum_g5_under_g1_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{10} pri_pw_diff_th = %d\n", dfs->pri_pw_diff_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{11} pri_pw_diff_fcc_th = %d\n",
-+			 dfs->pri_pw_diff_fcc_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{12} pri_pw_diff_fcc_idle_th = %d\n",
-+			 dfs->pri_pw_diff_fcc_idle_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{13} pri_pw_diff_w53_th = %d\n",
-+			 dfs->pri_pw_diff_w53_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{14} pri_type1_low_fcc_th = %d\n",
-+			 dfs->pri_type1_low_fcc_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{15} pri_type1_upp_fcc_th = %d\n",
-+			 dfs->pri_type1_upp_fcc_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{16} pri_type1_cen_fcc_th = %d\n",
-+			 dfs->pri_type1_cen_fcc_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{17} pw_g0_th = %d\n", dfs->pw_g0_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{18} pw_long_lower_20m_th = %d\n",
-+			 dfs->pw_long_lower_20m_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{19} pw_long_lower_th = %d\n",
-+			 dfs->pw_long_lower_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{20} pri_long_upper_th = %d\n",
-+			 dfs->pri_long_upper_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{21} pw_long_sum_upper_th = %d\n",
-+			 dfs->pw_long_sum_upper_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{22} pw_std_th = %d\n", dfs->pw_std_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{23} pw_std_idle_th = %d\n", dfs->pw_std_idle_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{24} pri_std_th = %d\n", dfs->pri_std_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{25} pri_std_idle_th = %d\n", dfs->pri_std_idle_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{26} type4_pw_max_cnt = %d\n", dfs->type4_pw_max_cnt);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{27} type4_safe_pri_sum_th = %d\n",
-+			 dfs->type4_safe_pri_sum_th);
-+	} else {
-+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &argv[0]);
-+
-+		for (i = 1; i < 5; i++) {
-+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
-+				     &argv[i]);
-+		}
-+		if (argv[0] == 0) {
-+			dfs->pri_hist_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_hist_th = %d\n",
-+				 dfs->pri_hist_th);
-+		} else if (argv[0] == 1) {
-+			dfs->pri_sum_g1_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_sum_g1_th = %d\n",
-+				 dfs->pri_sum_g1_th);
-+		} else if (argv[0] == 2) {
-+			dfs->pri_sum_g5_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_sum_g5_th = %d\n",
-+				 dfs->pri_sum_g5_th);
-+		} else if (argv[0] == 3) {
-+			dfs->pri_sum_g1_fcc_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_sum_g1_fcc_th = %d\n",
-+				 dfs->pri_sum_g1_fcc_th);
-+		} else if (argv[0] == 4) {
-+			dfs->pri_sum_g3_fcc_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_sum_g3_fcc_th = %d\n",
-+				 dfs->pri_sum_g3_fcc_th);
-+		} else if (argv[0] == 5) {
-+			dfs->pri_sum_safe_fcc_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_sum_safe_fcc_th = %d\n",
-+				 dfs->pri_sum_safe_fcc_th);
-+		} else if (argv[0] == 6) {
-+			dfs->pri_sum_type4_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_sum_type4_th = %d\n",
-+				 dfs->pri_sum_type4_th);
-+		} else if (argv[0] == 7) {
-+			dfs->pri_sum_type6_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_sum_type6_th = %d\n",
-+				 dfs->pri_sum_type6_th);
-+		} else if (argv[0] == 8) {
-+			dfs->pri_sum_safe_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_sum_safe_th = %d\n",
-+				 dfs->pri_sum_safe_th);
-+		} else if (argv[0] == 9) {
-+			dfs->pri_sum_g5_under_g1_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_sum_g5_under_g1_th = %d\n",
-+				 dfs->pri_sum_g5_under_g1_th);
-+		} else if (argv[0] == 10) {
-+			dfs->pri_pw_diff_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_pw_diff_th = %d\n",
-+				 dfs->pri_pw_diff_th);
-+		} else if (argv[0] == 11) {
-+			dfs->pri_pw_diff_fcc_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_pw_diff_fcc_th = %d\n",
-+				 dfs->pri_pw_diff_fcc_th);
-+		} else if (argv[0] == 12) {
-+			dfs->pri_pw_diff_fcc_idle_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_pw_diff_fcc_idle_th = %d\n",
-+				 dfs->pri_pw_diff_fcc_idle_th);
-+		} else if (argv[0] == 13) {
-+			dfs->pri_pw_diff_w53_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_pw_diff_w53_th = %d\n",
-+				 dfs->pri_pw_diff_w53_th);
-+		} else if (argv[0] == 14) {
-+			dfs->pri_type1_low_fcc_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_type1_low_fcc_th = %d\n",
-+				 dfs->pri_type1_low_fcc_th);
-+		} else if (argv[0] == 15) {
-+			dfs->pri_type1_upp_fcc_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_type1_upp_fcc_th = %d\n",
-+				 dfs->pri_type1_upp_fcc_th);
-+		} else if (argv[0] == 16) {
-+			dfs->pri_type1_cen_fcc_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_type1_cen_fcc_th = %d\n",
-+				 dfs->pri_type1_cen_fcc_th);
-+		} else if (argv[0] == 17) {
-+			dfs->pw_g0_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pw_g0_th = %d\n",
-+				 dfs->pw_g0_th);
-+		} else if (argv[0] == 18) {
-+			dfs->pw_long_lower_20m_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pw_long_lower_20m_th = %d\n",
-+				 dfs->pw_long_lower_20m_th);
-+		} else if (argv[0] == 19) {
-+			dfs->pw_long_lower_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pw_long_lower_th = %d\n",
-+				 dfs->pw_long_lower_th);
-+		} else if (argv[0] == 20) {
-+			dfs->pri_long_upper_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_long_upper_th = %d\n",
-+				 dfs->pri_long_upper_th);
-+		} else if (argv[0] == 21) {
-+			dfs->pw_long_sum_upper_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pw_long_sum_upper_th = %d\n",
-+				 dfs->pw_long_sum_upper_th);
-+		} else if (argv[0] == 22) {
-+			dfs->pw_std_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pw_std_th = %d\n",
-+				 dfs->pw_std_th);
-+		} else if (argv[0] == 23) {
-+			dfs->pw_std_idle_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pw_std_idle_th = %d\n",
-+				 dfs->pw_std_idle_th);
-+		} else if (argv[0] == 24) {
-+			dfs->pri_std_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_std_th = %d\n",
-+				 dfs->pri_std_th);
-+		} else if (argv[0] == 25) {
-+			dfs->pri_std_idle_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pri_std_idle_th = %d\n",
-+				 dfs->pri_std_idle_th);
-+		} else if (argv[0] == 26) {
-+			dfs->type4_pw_max_cnt = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "type4_pw_max_cnt = %d\n",
-+				 dfs->type4_pw_max_cnt);
-+		} else if (argv[0] == 27) {
-+			dfs->type4_safe_pri_sum_th = (u8)argv[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "type4_safe_pri_sum_th = %d\n",
-+				 dfs->type4_safe_pri_sum_th);
-+		}
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,
-+		     char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _DFS_STATISTICS *dfs = &dm->dfs;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 argv[10] = {0};
-+	u8 i, input_idx = 0;
-+
-+	for (i = 0; i < 7; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_HEX, &argv[i]);
-+		input_idx++;
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	dfs->dbg_mode = (boolean)argv[0];
-+	dfs->sw_trigger_mode = (boolean)argv[1];
-+	dfs->force_TP_mode = (boolean)argv[2];
-+	dfs->det_print = (boolean)argv[3];
-+	dfs->det_print2 = (boolean)argv[4];
-+	dfs->print_hist_rpt = (boolean)argv[5];
-+	dfs->hist_cond_on = (boolean)argv[6];
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "dbg_mode: %d, sw_trigger_mode: %d, force_TP_mode: %d, det_print: %d,det_print2: %d, print_hist_rpt: %d, hist_cond_on: %d\n",
-+		 dfs->dbg_mode, dfs->sw_trigger_mode, dfs->force_TP_mode,
-+		 dfs->det_print, dfs->det_print2, dfs->print_hist_rpt,
-+		 dfs->hist_cond_on);
-+}
-+
-+u8 phydm_dfs_polling_time(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _DFS_STATISTICS *dfs = &dm->dfs;
-+
-+	if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
-+		dfs->dfs_polling_time = 40;
-+	else
-+		dfs->dfs_polling_time = 100;
-+
-+	return dfs->dfs_polling_time;
-+}
-+
-+#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */
-+
-+boolean
-+phydm_is_dfs_band(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (((*dm->channel >= 52) && (*dm->channel <= 64)) ||
-+	    ((*dm->channel >= 100) && (*dm->channel <= 144)))
-+		return true;
-+	else
-+		return false;
-+}
-+
-+boolean
-+phydm_dfs_master_enabled(void *dm_void)
-+{
-+#ifdef CONFIG_PHYDM_DFS_MASTER
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean ret_val = false;
-+
-+	if (dm->dfs_master_enabled) /*pointer protection*/
-+		ret_val = *dm->dfs_master_enabled ? true : false;
-+
-+	return ret_val;
-+#else
-+	return false;
-+#endif
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+void phydm_dfs_ap_reset_radar_detect_counter_and_flag(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	/* @Clear Radar Counter and Radar flag */
-+	odm_set_bb_reg(dm, R_0xa40, BIT(15), 0);
-+	odm_set_bb_reg(dm, R_0xa40, BIT(15), 1);
-+
-+	/* RT_TRACE(COMP_DFS, DBG_LOUD, ("[DFS], After reset radar counter, 0xcf8 = 0x%x, 0xcf4 = 0x%x\n", */
-+	/* PHY_QueryBBReg(Adapter, 0xcf8, bMaskDWord), */
-+	/* PHY_QueryBBReg(Adapter, 0xcf4, bMaskDWord))); */
-+}
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_dfs.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_dfs.h
-new file mode 100644
-index 000000000000..fabc640e73b3
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_dfs.h
-@@ -0,0 +1,191 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_DFS_H__
-+#define __PHYDM_DFS_H__
-+
-+#define DFS_VERSION "1.1"
-+
-+/*@
-+ * ============================================================
-+ *  Definition
-+ * ============================================================
-+ */
-+
-+/*@
-+ * ============================================================
-+ * 1  structure
-+ * ============================================================
-+ */
-+
-+struct _DFS_STATISTICS {
-+	u8		mask_idx;
-+	u8		igi_cur;
-+	u8		igi_pre;
-+	u8		st_l2h_cur;
-+	u16		fa_count_pre;
-+	u16		fa_inc_hist[5];
-+	u16		short_pulse_cnt_pre;
-+	u16		long_pulse_cnt_pre;
-+	u8		pwdb_th;
-+	u8		pwdb_th_cur;
-+	u8		pwdb_scalar_factor;
-+	u8		peak_th;
-+	u8		short_pulse_cnt_th;
-+	u8		long_pulse_cnt_th;
-+	u8		peak_window;
-+	u8		three_peak_opt;
-+	u8		three_peak_th2;
-+	u8		fa_mask_th;
-+	u8		st_l2h_max;
-+	u8		st_l2h_min;
-+	u8		dfs_polling_time;
-+	u8		mask_hist_checked : 3;
-+	boolean		pulse_flag_hist[5];
-+	boolean		pulse_type_hist[5];
-+	boolean		radar_det_mask_hist[5];
-+	boolean		idle_mode;
-+	boolean		force_TP_mode;
-+	boolean		dbg_mode;
-+	boolean		sw_trigger_mode;
-+	boolean		det_print;
-+	boolean		det_print2;
-+	boolean		radar_type;
-+	boolean		print_hist_rpt;
-+	boolean		hist_cond_on;
-+	/*@dfs histogram*/
-+	boolean		pri_cond1;
-+	boolean		pri_cond2;
-+	boolean		pri_cond3;
-+	boolean		pri_cond4;
-+	boolean		pri_cond5;
-+	boolean		pw_cond1;
-+	boolean		pw_cond2;
-+	boolean		pw_cond3;
-+	boolean		pri_type3_4_cond1;	/*@for ETSI*/
-+	boolean		pri_type3_4_cond2;	/*@for ETSI*/
-+	boolean		pw_long_cond1;	/*@for long radar*/
-+	boolean		pw_long_cond2;	/*@for long radar*/
-+	boolean		pri_long_cond1;	/*@for long radar*/
-+	boolean		pw_flag;
-+	boolean		pri_flag;
-+	boolean		pri_type3_4_flag;	/*@for ETSI*/
-+	boolean		long_radar_flag;
-+	u8		pri_hold_sum[6];
-+	u8		pw_hold_sum[6];
-+	u8		pri_long_hold_sum[6];
-+	u8		pw_long_hold_sum[6];
-+	u8		hist_idx;
-+	u8		hist_long_idx;
-+	u8		pw_hold[4][6];
-+	u8		pri_hold[4][6];
-+	u8		pw_std;	/*@The std(var) of reasonable num of pw group*/
-+	u8		pri_std;/*@The std(var) of reasonable num of pri group*/
-+	/*@dfs histogram threshold*/
-+	u8		pri_hist_th : 3;
-+	u8		pri_sum_g1_th : 4;
-+	u8		pri_sum_g5_th : 4;
-+	u8		pri_sum_g1_fcc_th : 3;
-+	u8		pri_sum_g3_fcc_th : 3;
-+	u8		pri_sum_safe_fcc_th : 7;
-+	u8		pri_sum_type4_th : 5;
-+	u8		pri_sum_type6_th : 5;
-+	u8		pri_sum_safe_th : 6;
-+	u8		pri_sum_g5_under_g1_th : 3;
-+	u8		pri_pw_diff_th : 3;
-+	u8		pri_pw_diff_fcc_th : 4;
-+	u8		pri_pw_diff_fcc_idle_th : 2;
-+	u8		pri_pw_diff_w53_th : 4;
-+	u8		pri_type1_low_fcc_th : 7;
-+	u8		pri_type1_upp_fcc_th : 7;
-+	u8		pri_type1_cen_fcc_th : 7;
-+	u8		pw_g0_th : 4;
-+	u8		pw_long_lower_20m_th : 4;
-+	u8		pw_long_lower_th : 3;
-+	u8		pri_long_upper_th : 6;
-+	u8		pw_long_sum_upper_th : 7;
-+	u8		pw_std_th : 4;
-+	u8		pw_std_idle_th : 4;
-+	u8		pri_std_th : 4;
-+	u8		pri_std_idle_th : 4;
-+	u8		type4_pw_max_cnt : 4;
-+	u8		type4_safe_pri_sum_th : 3;
-+};
-+
-+/*@
-+ * ============================================================
-+ * enumeration
-+ * ============================================================
-+ */
-+
-+enum phydm_dfs_region_domain {
-+	PHYDM_DFS_DOMAIN_UNKNOWN =	0,
-+	PHYDM_DFS_DOMAIN_FCC =		1,
-+	PHYDM_DFS_DOMAIN_MKK =		2,
-+	PHYDM_DFS_DOMAIN_ETSI =		3,
-+};
-+
-+/*@
-+ * ============================================================
-+ * function prototype
-+ * ============================================================
-+ */
-+#if defined(CONFIG_PHYDM_DFS_MASTER)
-+void phydm_radar_detect_reset(void *dm_void);
-+void phydm_radar_detect_disable(void *dm_void);
-+void phydm_radar_detect_enable(void *dm_void);
-+boolean phydm_radar_detect(void *dm_void);
-+void phydm_dfs_histogram_radar_distinguish(void *dm_void);
-+boolean phydm_dfs_hist_log(void *dm_void, u8 index);
-+void phydm_dfs_parameter_init(void *dm_void);
-+void phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used,
-+			char *output, u32 *_out_len);
-+void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,
-+		     char *output, u32 *_out_len);
-+u8 phydm_dfs_polling_time(void *dm_void);
-+#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */
-+
-+boolean
-+phydm_dfs_is_meteorology_channel(void *dm_void);
-+
-+void
-+phydm_dfs_segment_distinguish(void *dm_void, enum rf_syn syn_path);
-+
-+void
-+phydm_dfs_segment_flag_reset(void *dm_void);
-+
-+boolean
-+phydm_is_dfs_band(void *dm_void);
-+
-+boolean
-+phydm_dfs_master_enabled(void *dm_void);
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+void phydm_dfs_ap_reset_radar_detect_counter_and_flag(void *dm_void);
-+#endif
-+#endif
-+
-+#endif /*@#ifndef __PHYDM_DFS_H__ */
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_dig.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_dig.c
-new file mode 100644
-index 000000000000..cb654c6e7ff2
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_dig.c
-@@ -0,0 +1,3516 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ * ************************************************************
-+ */
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef CFG_DIG_DAMPING_CHK
-+void phydm_dig_recorder_reset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
-+
-+	odm_memory_set(dm, &dig_rc->igi_bitmap, 0,
-+		       sizeof(struct phydm_dig_recorder_strcut));
-+}
-+
-+void phydm_dig_recorder(void *dm_void, u8 igi_curr,
-+			u32 fa_cnt)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
-+	u8 igi_pre = dig_rc->igi_history[0];
-+	u8 igi_up = 0;
-+
-+	if (!dm->is_linked)
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
-+
-+	if (dm->first_connect) {
-+		phydm_dig_recorder_reset(dm);
-+		dig_rc->igi_history[0] = igi_curr;
-+		dig_rc->fa_history[0] = fa_cnt;
-+		return;
-+	}
-+
-+	if (igi_curr % 2)
-+		igi_curr--;
-+
-+	igi_pre = dig_rc->igi_history[0];
-+	igi_up = (igi_curr > igi_pre) ? 1 : 0;
-+	dig_rc->igi_bitmap = ((dig_rc->igi_bitmap << 1) & 0xfe) | igi_up;
-+
-+	dig_rc->igi_history[3] = dig_rc->igi_history[2];
-+	dig_rc->igi_history[2] = dig_rc->igi_history[1];
-+	dig_rc->igi_history[1] = dig_rc->igi_history[0];
-+	dig_rc->igi_history[0] = igi_curr;
-+
-+	dig_rc->fa_history[3] = dig_rc->fa_history[2];
-+	dig_rc->fa_history[2] = dig_rc->fa_history[1];
-+	dig_rc->fa_history[1] = dig_rc->fa_history[0];
-+	dig_rc->fa_history[0] = fa_cnt;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "igi_history[3:0] = {0x%x, 0x%x, 0x%x, 0x%x}\n",
-+		  dig_rc->igi_history[3], dig_rc->igi_history[2],
-+		  dig_rc->igi_history[1], dig_rc->igi_history[0]);
-+	PHYDM_DBG(dm, DBG_DIG, "fa_history[3:0] = {%d, %d, %d, %d}\n",
-+		  dig_rc->fa_history[3], dig_rc->fa_history[2],
-+		  dig_rc->fa_history[1], dig_rc->fa_history[0]);
-+	PHYDM_DBG(dm, DBG_DIG, "igi_bitmap = {%d, %d, %d, %d} = 0x%x\n",
-+		  (u8)((dig_rc->igi_bitmap & BIT(3)) >> 3),
-+		  (u8)((dig_rc->igi_bitmap & BIT(2)) >> 2),
-+		  (u8)((dig_rc->igi_bitmap & BIT(1)) >> 1),
-+		  (u8)(dig_rc->igi_bitmap & BIT(0)),
-+		  dig_rc->igi_bitmap);
-+}
-+
-+void phydm_dig_damping_chk(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
-+	u8 igi_bitmap_4bit = dig_rc->igi_bitmap & 0xf;
-+	u8 diff1 = 0, diff2 = 0;
-+	u32 fa_low_th = dig_t->fa_th[0];
-+	u32 fa_high_th = dig_t->fa_th[1];
-+	u32 fa_high_th2 = dig_t->fa_th[2];
-+	u8 fa_pattern_match = 0;
-+	u32 time_tmp = 0;
-+
-+	if (!dm->is_linked)
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
-+
-+	/*@== Release Damping ================================================*/
-+	if (dig_rc->damping_limit_en) {
-+		PHYDM_DBG(dm, DBG_DIG,
-+			  "[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n",
-+			  dig_rc->limit_time, dm->phydm_sys_up_time);
-+
-+		time_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD;
-+
-+		if (DIFF_2(dm->rssi_min, dig_rc->limit_rssi) > 3 ||
-+		    time_tmp < dm->phydm_sys_up_time) {
-+			dig_rc->damping_limit_en = 0;
-+			PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, limit_rssi=%d\n",
-+				  dm->rssi_min, dig_rc->limit_rssi);
-+		}
-+		return;
-+	}
-+
-+	/*@== Damping Pattern Check===========================================*/
-+	PHYDM_DBG(dm, DBG_DIG, "fa_th{H, L}= {%d,%d}\n", fa_high_th, fa_low_th);
-+
-+	switch (igi_bitmap_4bit) {
-+	case 0x5:
-+	/*@ 4b'0101 
-+	* IGI:[3]down(0x24)->[2]up(0x26)->[1]down(0x24)->[0]up(0x26)->[new](Lock @ 0x26)
-+	* FA: [3] >high1   ->[2] <low   ->[1] >high1   ->[0] <low   ->[new]   <low
-+	*
-+	* IGI:[3]down(0x24)->[2]up(0x28)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)
-+	* FA: [3] >high2   ->[2] <low   ->[1] >high2   ->[0] <low   ->[new]   <low
-+	*/
-+		if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
-+			diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
-+
-+		if (dig_rc->igi_history[2] > dig_rc->igi_history[3])
-+			diff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3];
-+
-+		if (dig_rc->fa_history[0] < fa_low_th &&
-+		    dig_rc->fa_history[1] > fa_high_th &&
-+		    dig_rc->fa_history[2] < fa_low_th &&
-+		    dig_rc->fa_history[3] > fa_high_th) {
-+		    /*@Check each fa element*/
-+			fa_pattern_match = 1;
-+		}
-+		break;
-+	case 0x9:
-+	/*@ 4b'1001
-+	* IGI:[3]up(0x28)->[2]down(0x26)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28)
-+	* FA: [3]  <low  ->[2] <low     ->[1] >high2   ->[0] <low   ->[new]  <low
-+	*/
-+		if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
-+			diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
-+
-+		if (dig_rc->igi_history[2] < dig_rc->igi_history[3])
-+			diff2 = dig_rc->igi_history[3] - dig_rc->igi_history[2];
-+
-+		if (dig_rc->fa_history[0] < fa_low_th &&
-+		    dig_rc->fa_history[1] > fa_high_th2 &&
-+		    dig_rc->fa_history[2] < fa_low_th &&
-+		    dig_rc->fa_history[3] < fa_low_th) {
-+		    /*@Check each fa element*/
-+			fa_pattern_match = 1;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) {
-+		dig_rc->damping_limit_en = 1;
-+		dig_rc->damping_limit_val = dig_rc->igi_history[0];
-+		dig_rc->limit_time = dm->phydm_sys_up_time;
-+		dig_rc->limit_rssi = dm->rssi_min;
-+
-+		PHYDM_DBG(dm, DBG_DIG,
-+			  "[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\n",
-+			  dig_rc->damping_limit_val,
-+			  dig_rc->limit_time, dig_rc->limit_rssi);
-+	}
-+
-+	PHYDM_DBG(dm, DBG_DIG, "damping_limit=%d\n", dig_rc->damping_limit_en);
-+}
-+#endif
-+
-+void phydm_fa_threshold_check(void *dm_void, boolean is_dfs_band)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+	if (dig_t->is_dbg_fa_th) {
-+		PHYDM_DBG(dm, DBG_DIG, "Manual Fix FA_th\n");
-+	} else if (dm->is_linked) {
-+		if (dm->rssi_min < 20) { /*@[PHYDM-252]*/
-+			dig_t->fa_th[0] = 500;
-+			dig_t->fa_th[1] = 750;
-+			dig_t->fa_th[2] = 1000;
-+		} else if (((dm->rx_tp >> 2) > dm->tx_tp) && /*Test RX TP*/
-+			   (dm->rx_tp < 10) && (dm->rx_tp > 1)) { /*TP=1~10Mb*/
-+			dig_t->fa_th[0] = 125;
-+			dig_t->fa_th[1] = 250;
-+			dig_t->fa_th[2] = 500;
-+		} else {
-+			dig_t->fa_th[0] = 250;
-+			dig_t->fa_th[1] = 500;
-+			dig_t->fa_th[2] = 750;
-+		}
-+	} else {
-+		if (is_dfs_band) { /* @For DFS band and no link */
-+
-+			dig_t->fa_th[0] = 250;
-+			dig_t->fa_th[1] = 1000;
-+			dig_t->fa_th[2] = 2000;
-+		} else {
-+			dig_t->fa_th[0] = 2000;
-+			dig_t->fa_th[1] = 4000;
-+			dig_t->fa_th[2] = 5000;
-+		}
-+	}
-+
-+	PHYDM_DBG(dm, DBG_DIG, "FA_th={%d,%d,%d}\n", dig_t->fa_th[0],
-+		  dig_t->fa_th[1], dig_t->fa_th[2]);
-+}
-+
-+void phydm_set_big_jump_step(void *dm_void, u8 curr_igi)
-+{
-+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90};
-+	u8 big_jump_lmt = dig_t->big_jump_lmt[dig_t->agc_table_idx];
-+	u8 i;
-+
-+	if (dig_t->enable_adjust_big_jump == 0)
-+		return;
-+
-+	for (i = 0; i <= dig_t->big_jump_step1; i++) {
-+		if ((curr_igi + step1[i]) > big_jump_lmt) {
-+			if (i != 0)
-+				i = i - 1;
-+			break;
-+		} else if (i == dig_t->big_jump_step1) {
-+			break;
-+		}
-+	}
-+	if (dm->support_ic_type & ODM_RTL8822B)
-+		odm_set_bb_reg(dm, R_0x8c8, 0xe, i);
-+	else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
-+		odm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i);
-+
-+	PHYDM_DBG(dm, DBG_DIG, "Bigjump = %d (ori = 0x%x), LMT=0x%x\n", i,
-+		  dig_t->big_jump_step1, big_jump_lmt);
-+#endif
-+}
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+void phydm_write_dig_reg_jgr3(void *dm_void, u8 igi)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
-+
-+	/* Set IGI value */
-+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
-+		return;
-+
-+	odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC, igi);
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
-+		odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3, igi);
-+	#endif
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
-+		odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3, igi);
-+		odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3, igi);
-+	}
-+	#endif
-+}
-+
-+u8 phydm_get_igi_reg_val_jgr3(void *dm_void, enum bb_path path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 val = 0;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
-+
-+	/* Set IGI value */
-+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
-+		return (u8)val;
-+
-+	if (path == BB_PATH_A)
-+		val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC);
-+#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	else if (path == BB_PATH_B)
-+		val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3);
-+#endif
-+
-+#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	else if (path == BB_PATH_C)
-+		val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3);
-+#endif
-+
-+#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	else if (path == BB_PATH_D)
-+		val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3);
-+#endif
-+	return (u8)val;
-+}
-+
-+void phydm_fa_cnt_statistics_jgr3(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
-+	u32 ret_value = 0;
-+	u32 cck_enable = 0;
-+
-+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
-+		return;
-+
-+	ret_value = odm_get_bb_reg(dm, R_0x2d20, MASKDWORD);
-+	fa_t->cnt_fast_fsync = ret_value & 0xffff;
-+	fa_t->cnt_sb_search_fail = (ret_value & 0xffff0000) >> 16;
-+
-+	ret_value = odm_get_bb_reg(dm, R_0x2d04, MASKDWORD);
-+	fa_t->cnt_parity_fail = (ret_value & 0xffff0000) >> 16;
-+
-+	ret_value = odm_get_bb_reg(dm, R_0x2d08, MASKDWORD);
-+	fa_t->cnt_rate_illegal = ret_value & 0xffff;
-+	fa_t->cnt_crc8_fail = (ret_value & 0xffff0000) >> 16;
-+
-+	ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
-+	fa_t->cnt_mcs_fail = ret_value & 0xffff;
-+
-+	/* read CCK CRC32 counter */
-+	if (dm->support_ic_type & ODM_RTL8723F)
-+		ret_value = odm_get_bb_reg(dm, R_0x2aac, MASKDWORD);
-+	else
-+		ret_value = odm_get_bb_reg(dm, R_0x2c04, MASKDWORD);
-+	fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
-+	fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
-+
-+	/* read OFDM CRC32 counter */
-+	ret_value = odm_get_bb_reg(dm, R_0x2c14, MASKDWORD);
-+	fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
-+	fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
-+
-+	/* read OFDM2 CRC32 counter */
-+	ret_value = odm_get_bb_reg(dm, R_0x2c1c, MASKDWORD);
-+	fa_t->cnt_ofdm2_crc32_ok = ret_value & 0xffff;
-+	fa_t->cnt_ofdm2_crc32_error = (ret_value & 0xffff0000) >> 16;
-+
-+	/* read HT CRC32 counter */
-+	ret_value = odm_get_bb_reg(dm, R_0x2c10, MASKDWORD);
-+	fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
-+	fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
-+
-+	/* read HT2 CRC32 counter */
-+	ret_value = odm_get_bb_reg(dm, R_0x2c18, MASKDWORD);
-+	fa_t->cnt_ht2_crc32_ok = ret_value & 0xffff;
-+	fa_t->cnt_ht2_crc32_error = (ret_value & 0xffff0000) >> 16;
-+
-+	/*for VHT part */
-+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
-+	    ODM_RTL8814B)) {
-+		/*read VHT CRC32 counter */
-+		ret_value = odm_get_bb_reg(dm, R_0x2c0c, MASKDWORD);
-+		fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
-+		fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
-+
-+		/*read VHT2 CRC32 counter */
-+		ret_value = odm_get_bb_reg(dm, R_0x2c54, MASKDWORD);
-+		fa_t->cnt_vht2_crc32_ok = ret_value & 0xffff;
-+		fa_t->cnt_vht2_crc32_error = (ret_value & 0xffff0000) >> 16;
-+
-+		ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
-+		fa_t->cnt_mcs_fail_vht = (ret_value & 0xffff0000) >> 16;
-+
-+		ret_value = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);
-+		fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff;
-+		fa_t->cnt_crc8_fail_vhtb = (ret_value & 0xffff0000) >> 16;
-+	} else {
-+		fa_t->cnt_vht_crc32_error = 0;
-+		fa_t->cnt_vht_crc32_ok = 0;
-+		fa_t->cnt_vht2_crc32_error = 0;
-+		fa_t->cnt_vht2_crc32_ok = 0;
-+		fa_t->cnt_mcs_fail_vht = 0;
-+		fa_t->cnt_crc8_fail_vhta = 0;
-+		fa_t->cnt_crc8_fail_vhtb = 0;
-+	}
-+
-+	/* @calculate OFDM FA counter instead of reading brk_cnt*/
-+	fa_t->cnt_ofdm_fail = fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
-+			      fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
-+			      fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail +
-+			      fa_t->cnt_mcs_fail_vht + fa_t->cnt_crc8_fail_vhta;
-+
-+	/* Read CCK FA counter */
-+	if (dm->support_ic_type & ODM_RTL8723F){
-+		ret_value= odm_get_bb_reg(dm, R_0x2aa8, MASKLWORD);
-+	       fa_t->cnt_cck_fail=(ret_value&0xffff)+((ret_value&0xffff0000)>>16);
-+		}
-+	else
-+		fa_t->cnt_cck_fail = odm_get_bb_reg(dm, R_0x1a5c, MASKLWORD);
-+
-+	/* read CCK/OFDM CCA counter */
-+	ret_value = odm_get_bb_reg(dm, R_0x2c08, MASKDWORD);
-+	fa_t->cnt_ofdm_cca = ((ret_value & 0xffff0000) >> 16);
-+	if (dm->support_ic_type & ODM_RTL8723F)
-+		ret_value = odm_get_bb_reg(dm, R_0x2aa0, MASKDWORD);
-+	fa_t->cnt_cck_cca = ret_value & 0xffff;
-+
-+	/* @CCK RxIQ weighting = 1 => 0x1a14[9:8]=0x0 */
-+	if (dm->support_ic_type & ODM_RTL8723F)
-+		cck_enable = odm_get_bb_reg(dm, R_0x2a24, BIT(13));
-+	else
-+		cck_enable = odm_get_bb_reg(dm, R_0x1a14, 0x300);
-+	
-+	if (cck_enable == 0x0) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
-+		fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;
-+		fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
-+	} else {
-+		fa_t->cnt_all = fa_t->cnt_ofdm_fail;
-+		fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
-+	}
-+}
-+
-+#endif
-+
-+void phydm_write_dig_reg_c50(void *dm_void, u8 igi)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
-+
-+	odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), igi);
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
-+		odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), igi);
-+	#endif
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
-+		odm_set_bb_reg(dm, ODM_REG(IGI_C, dm), ODM_BIT(IGI, dm), igi);
-+		odm_set_bb_reg(dm, ODM_REG(IGI_D, dm), ODM_BIT(IGI, dm), igi);
-+	}
-+	#endif
-+}
-+
-+void phydm_write_dig_reg(void *dm_void, u8 igi)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	u8 rf_gain = 0;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
-+
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		phydm_write_dig_reg_jgr3(dm, igi);
-+	else
-+	#endif
-+		phydm_write_dig_reg_c50(dm, igi);
-+
-+	#if (RTL8721D_SUPPORT)
-+	if (dm->invalid_mode) {
-+		if (igi <= 0x10)
-+			rf_gain = 0xfa;
-+		else if (igi <= 0x40)
-+			rf_gain = 0xe3 + 0x20 - (igi >> 1);
-+		else if (igi <= 0x50)
-+			rf_gain = 0xcb - (igi >> 1);
-+		else if (igi <= 0x5e)
-+			rf_gain = 0x92 - (igi >> 1);
-+		else if (igi <= 0x64)
-+			rf_gain = 0x74 - (igi >> 1);
-+		else
-+			rf_gain = (0x3d > (igi >> 1)) ? (0x3d - (igi >> 1)) : 0;
-+		odm_set_bb_reg(dm, R_0x850, 0x1fe0, rf_gain);
-+	}
-+	#endif
-+
-+	if (igi == dig_t->cur_ig_value)
-+		dig_t->igi_trend = DIG_STABLE;
-+	else if (igi > dig_t->cur_ig_value)
-+		dig_t->igi_trend = DIG_INCREASING;
-+	else
-+		dig_t->igi_trend = DIG_DECREASING;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "Update IGI:0x%x -> 0x%x\n",
-+		  dig_t->cur_ig_value, igi);
-+
-+	dig_t->cur_ig_value = igi;
-+}
-+
-+void odm_write_dig(void *dm_void, u8 new_igi)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
-+
-+	/* @1 Check IGI by upper bound */
-+	if (adaptivity->igi_lmt_en &&
-+	    new_igi > adaptivity->adapt_igi_up && dm->is_linked) {
-+		new_igi = adaptivity->adapt_igi_up;
-+
-+		PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n",
-+			  new_igi);
-+	}
-+
-+	#if (RTL8192F_SUPPORT)
-+	if ((dm->support_ic_type & ODM_RTL8192F) &&
-+	    dm->cut_version == ODM_CUT_A &&
-+	    new_igi > 0x38) {
-+		new_igi = 0x38;
-+		PHYDM_DBG(dm, DBG_DIG,
-+			  "Force 92F Adaptivity Up-bound=((0x%x))\n", new_igi);
-+	}
-+	#endif
-+
-+	if (dig_t->cur_ig_value != new_igi) {
-+		#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
-+		/* @Modify big jump step for 8822B and 8197F */
-+		if (dm->support_ic_type &
-+		    (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F))
-+			phydm_set_big_jump_step(dm, new_igi);
-+		#endif
-+
-+		#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
-+		/* Set IGI value of CCK for new CCK AGC */
-+		if (dm->cck_new_agc &&
-+		    (dm->support_ic_type & PHYSTS_2ND_TYPE_IC))
-+			odm_set_bb_reg(dm, R_0xa0c, 0x3f00, (new_igi >> 1));
-+		#endif
-+
-+		/*@Add by YuChen for USB IO too slow issue*/
-+		if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
-+			if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
-+			    new_igi < dig_t->cur_ig_value) {
-+				dig_t->cur_ig_value = new_igi;
-+				phydm_adaptivity(dm);
-+			}
-+		} else {
-+			if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
-+			    new_igi > dig_t->cur_ig_value) {
-+				dig_t->cur_ig_value = new_igi;
-+				phydm_adaptivity(dm);
-+			}
-+		}
-+		phydm_write_dig_reg(dm, new_igi);
-+	} else {
-+		dig_t->igi_trend = DIG_STABLE;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_DIG, "[%s]New_igi=((0x%x))\n\n",
-+		  ((dig_t->igi_trend == DIG_STABLE) ? "=" :
-+		  ((dig_t->igi_trend == DIG_INCREASING) ? "+" : "-")),
-+		  new_igi);
-+}
-+
-+u8 phydm_get_igi_reg_val(void *dm_void, enum bb_path path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 val = 0;
-+	u32 bit_map = ODM_BIT(IGI, dm);
-+
-+	switch (path) {
-+	case BB_PATH_A:
-+		val = odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), bit_map);
-+		break;
-+	#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	case BB_PATH_B:
-+		val = odm_get_bb_reg(dm, ODM_REG(IGI_B, dm), bit_map);
-+		break;
-+	#endif
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	case BB_PATH_C:
-+		val = odm_get_bb_reg(dm, ODM_REG(IGI_C, dm), bit_map);
-+		break;
-+	#endif
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	case BB_PATH_D:
-+		val = odm_get_bb_reg(dm, ODM_REG(IGI_D, dm), bit_map);
-+		break;
-+	#endif
-+
-+	default:
-+		break;
-+	}
-+
-+	return (u8)val;
-+}
-+
-+u8 phydm_get_igi(void *dm_void, enum bb_path path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 val = 0;
-+
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		val = phydm_get_igi_reg_val_jgr3(dm, path);
-+	else
-+	#endif
-+		val = phydm_get_igi_reg_val(dm, path);
-+
-+	return val;
-+}
-+
-+void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (val_len != 1) {
-+		PHYDM_DBG(dm, ODM_COMP_API, "[Error][DIG]Need val_len=1\n");
-+		return;
-+	}
-+
-+	odm_write_dig(dm, (u8)(*val_buf));
-+}
-+
-+void odm_pause_dig(void *dm_void, enum phydm_pause_type type,
-+		   enum phydm_pause_level lv, u8 igi_input)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 rpt = false;
-+	u32 igi = (u32)igi_input;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "[%s]type=%d, LV=%d, igi=0x%x\n", __func__, type,
-+		  lv, igi);
-+
-+	switch (type) {
-+	case PHYDM_PAUSE:
-+	case PHYDM_PAUSE_NO_SET: {
-+		rpt = phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, lv, 1, &igi);
-+		break;
-+	}
-+
-+	case PHYDM_RESUME: {
-+		rpt = phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, lv, 1, &igi);
-+		break;
-+	}
-+	default:
-+		PHYDM_DBG(dm, DBG_DIG, "Wrong type\n");
-+		break;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_DIG, "DIG pause_result=%d\n", rpt);
-+}
-+
-+boolean
-+phydm_dig_abort(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+#endif
-+
-+	/* support_ability */
-+	if ((!(dm->support_ability & ODM_BB_FA_CNT)) ||
-+	    (!(dm->support_ability & ODM_BB_DIG))) {
-+		PHYDM_DBG(dm, DBG_DIG, "[DIG] Not Support\n");
-+		return true;
-+	}
-+
-+	if (dm->pause_ability & ODM_BB_DIG) {
-+		PHYDM_DBG(dm, DBG_DIG, "Return: Pause DIG in LV=%d\n",
-+			  dm->pause_lv_table.lv_dig);
-+		return true;
-+	}
-+
-+	if (*dm->is_scan_in_process) {
-+		PHYDM_DBG(dm, DBG_DIG, "Return: Scan in process\n");
-+		return true;
-+	}
-+
-+	if (dm->dm_dig_table.fw_dig_enable) {
-+		PHYDM_DBG(dm, DBG_DIG, "Return: FW DIG enable\n");
-+		return true;
-+	}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#if OS_WIN_FROM_WIN7(OS_VERSION)
-+	if (IsAPModeExist(adapter) && ((PADAPTER)(adapter))->bInHctTest) {
-+		PHYDM_DBG(dm, DBG_DIG, " Return: Is AP mode or In HCT Test\n");
-+		return true;
-+	}
-+#endif
-+#endif
-+
-+	return false;
-+}
-+
-+#ifdef PHYDM_HW_IGI
-+#ifdef BB_RAM_SUPPORT
-+void phydm_rd_hwigi_pre_setting(void *dm_void, u32 *_used, char *output,
-+				u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 igi_ofst = 0x0;
-+	u32 t1, t2, t3 = 0x0;
-+
-+	igi_ofst = (u8)odm_get_bb_reg(dm, R_0x1e80, MASKBYTE0);
-+	t1 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE1) * 400;
-+	t2 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE2) * 400;
-+	t3 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE3) * 400;
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "igi_offset:0x%x, t1:%d(ns), t2:%d(ns), t3:%d(ns)\n",
-+		 igi_ofst, t1, t2, t3);
-+}
-+
-+void phydm_set_hwigi_pre_setting(void *dm_void, u8 igi_ofst, u8 t1, u8 t2,
-+				 u8 t3)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 reg_0x1e80 = 0;
-+
-+	reg_0x1e80 = igi_ofst + (t1 << 8) + (t2 << 16) + (t3 << 24);
-+	odm_set_bb_reg(dm, R_0x1e80, MASKDWORD, reg_0x1e80);
-+}
-+
-+void phydm_rd_hwigi_table(void *dm_void, u8 macid, u32 *_used, char *output,
-+			  u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	boolean hwigi_en = false;
-+	u8 hwigi = 0x0;
-+	u8 hwigi_rx_offset = 0x0;
-+	u32 reg_0x1e84 = 0x0;
-+
-+	reg_0x1e84 |= (macid & 0x3f) << 24; /*macid*/
-+	reg_0x1e84 |= BIT(31); /*read_en*/
-+	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
-+
-+	hwigi_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(15));
-+	hwigi = (u8)odm_get_bb_reg(dm, R_0x2de8, 0x7f00);
-+	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "(macid:%d) hwigi_en:%d, hwigi:0x%x\n", macid, hwigi_en,
-+		 hwigi);
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_wt_hwigi_table(void *dm_void, u8 macid, boolean hwigi_en, u8 hwigi)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
-+	u32 reg_0x1e84 = 0;
-+
-+	if (macid > 63)
-+		macid = 63;
-+
-+	dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid];
-+	dm_ram_per_sta->hw_igi_en = hwigi_en;
-+	dm_ram_per_sta->hw_igi = hwigi;
-+
-+	reg_0x1e84 = (dm_ram_per_sta->tx_pwr_offset0_en << 15) +
-+		     ((dm_ram_per_sta->tx_pwr_offset0 & 0x7f) << 8) +
-+		     (dm_ram_per_sta->tx_pwr_offset1_en << 23) +
-+		     ((dm_ram_per_sta->tx_pwr_offset1 & 0x7f) << 16);
-+
-+	reg_0x1e84 |= (hwigi_en << 7) + (hwigi & 0x7f);
-+	reg_0x1e84 |= (macid & 0x3f) << 24;/*macid*/
-+	reg_0x1e84 |= BIT(30); /*write_en*/
-+	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
-+	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); /*read_en*/
-+	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /*disable rd/wt*/
-+}
-+
-+void phydm_rst_hwigi(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
-+	u32 reg_0x1e84 = 0;
-+	u8 i = 0;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "reset hwigi!\n");
-+
-+	for (i = 0; i < 64; i++) {
-+		dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[i];
-+		dm_ram_per_sta->hw_igi_en = false;
-+		dm_ram_per_sta->hw_igi = 0x0;
-+
-+		reg_0x1e84 = (dm_ram_per_sta->tx_pwr_offset0_en << 15) +
-+			     ((dm_ram_per_sta->tx_pwr_offset0 & 0x7f) << 8) +
-+			     (dm_ram_per_sta->tx_pwr_offset1_en << 23) +
-+			     ((dm_ram_per_sta->tx_pwr_offset1 & 0x7f) << 16);
-+
-+		reg_0x1e84 |= (i & 0x3f) << 24;
-+		reg_0x1e84 |= BIT(30);
-+		odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
-+	}
-+
-+	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000);
-+	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0);
-+}
-+
-+void phydm_hwigi_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
-+	u8 igi_ofst = 0x0;
-+	u8 t1 = 0x0;
-+	u8 t2 = 0x0;
-+	u8 t3 = 0x0;
-+
-+	t1 = 0x55; /*34 us*/
-+	t3 = 0x55; /*34 us*/
-+
-+	bb_ctrl->hwigi_watchdog_en = false;
-+	phydm_set_hwigi_pre_setting(dm, igi_ofst, t1, t2, t3);
-+}
-+
-+void phydm_hwigi(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = NULL;
-+	struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
-+	struct rssi_info *rssi = NULL;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
-+	u8 sta_cnt = 0;
-+	u8 i = 0;
-+	u8 hwigi = 0x0;
-+	u8 macid = 0;
-+	u8 macid_cnt = 0;
-+	u64 macid_cur = 0;
-+	u64 macid_diff = 0;
-+	u64 macid_mask = 0;
-+
-+	if (!(bb_ctrl->hwigi_watchdog_en)) {
-+		return;
-+	}
-+
-+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
-+		sta = dm->phydm_sta_info[i];
-+		if (is_sta_active(sta)) {
-+			sta_cnt++;
-+
-+			if (sta->mac_id > 63)
-+				macid = 63;
-+			else
-+				macid = sta->mac_id;
-+
-+			dm_ram_per_sta = &bb_ctrl->pram_sta_ctrl[macid];
-+			rssi = &sta->rssi_stat;
-+			macid_mask = (u64)BIT(sta->mac_id);
-+			bb_ctrl->hwigi_macid_is_linked |= macid_mask;
-+			macid_cur |= macid_mask;
-+			PHYDM_DBG(dm, DBG_DIG,
-+				  "STA_id=%d, MACID=%d, RSSI=%d, hwigi_en=%d, hwigi=0x%x\n",
-+				  i, sta->mac_id, rssi->rssi,
-+				  dm_ram_per_sta->hw_igi_en,
-+				  dm_ram_per_sta->hw_igi);
-+
-+			hwigi = MAX_2((u8)(rssi->rssi + 10),
-+				      dig_t->cur_ig_value);
-+
-+			if (hwigi > DIG_MAX_PERFORMANCE_MODE)
-+				hwigi = DIG_MAX_PERFORMANCE_MODE;
-+			else if (hwigi < DIG_MIN_PERFORMANCE)
-+				hwigi = DIG_MIN_PERFORMANCE;
-+
-+			if (dm_ram_per_sta->hw_igi == hwigi) {
-+				PHYDM_DBG(dm, DBG_DIG,
-+					  "hwigi not change!\n");
-+			} else {
-+
-+				PHYDM_DBG(dm, DBG_DIG,
-+					  "hwigi update: ((0x%x)) -> ((0x%x))\n",
-+					  dm_ram_per_sta->hw_igi, hwigi);
-+
-+				phydm_wt_hwigi_table(dm, sta->mac_id, true, hwigi);
-+			}
-+
-+			if (sta_cnt == dm->number_linked_client)
-+				break;
-+		}
-+	}
-+	macid_diff = bb_ctrl->hwigi_macid_is_linked ^ macid_cur;
-+	if (macid_diff)
-+		bb_ctrl->hwigi_macid_is_linked &= ~macid_diff;
-+	while (macid_diff) {
-+		if (macid_diff & 0x1)
-+			phydm_wt_hwigi_table(dm, macid_cnt, false, 0x0);
-+		macid_cnt++;
-+		macid_diff >>= 1;
-+	}
-+}
-+
-+void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used,
-+		     char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
-+	char help[] = "-h";
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 var1[7] = {0};
-+	u8 i = 0;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Disable/Enable watchdog : {0/1}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Set hwigi pre-setting: {2} {IGI offset} {T1(after data tx)} {T2(after Rx)} {T3(after rsp tx)}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Set hwigi table: {3} {en} {value} {macid}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Read hwigi : {4} {macid(0~63), 255:all}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Reset all hwigi : {5}\n");
-+	} else {
-+		for (i = 0; i < 7; i++) {
-+			if (input[i + 1])
-+				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
-+					     &var1[i]);
-+		}
-+		switch (var1[0]) {
-+		case 0:
-+		case 1:
-+			bb_ctrl->hwigi_watchdog_en = (var1[0]) ? true : false;
-+			break;
-+		case 2:
-+			phydm_set_hwigi_pre_setting(dm, (u8)var1[1],
-+						    (u8)var1[2], (u8)var1[3],
-+						    (u8)var1[4]);
-+			break;
-+		case 3:
-+			phydm_wt_hwigi_table(dm, (u8)var1[3], (boolean)var1[1],
-+					     (boolean)var1[2]);
-+			break;
-+		case 4:
-+			phydm_rd_hwigi_pre_setting(dm, &used, output, &out_len);
-+			if ((u8)var1[1] == 0xff)
-+				for (i = 0; i < 64; i++)
-+					phydm_rd_hwigi_table(dm, i, &used,
-+							     output, &out_len);
-+			else
-+				phydm_rd_hwigi_table(dm, (u8)var1[1], &used,
-+						     output, &out_len);
-+			break;
-+		case 5:
-+			phydm_rst_hwigi(dm);
-+			break;
-+		}
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+#endif
-+#endif
-+
-+void phydm_dig_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	struct phydm_fa_struct *false_alm_cnt = &dm->false_alm_cnt;
-+#endif
-+	u32 ret_value = 0;
-+	u8 i;
-+
-+	dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
-+	dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
-+	dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
-+
-+	dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
-+
-+	dig_t->fa_th[0] = 250;
-+	dig_t->fa_th[1] = 500;
-+	dig_t->fa_th[2] = 750;
-+	dig_t->is_dbg_fa_th = false;
-+	dig_t->igi_dyn_up_hit = false;
-+	dig_t->fw_dig_enable = false;
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	/* @For RTL8881A */
-+	false_alm_cnt->cnt_ofdm_fail_pre = 0;
-+#endif
-+
-+	dig_t->rx_gain_range_max = DIG_MAX_BALANCE_MODE;
-+	dig_t->rx_gain_range_min = dig_t->cur_ig_value;
-+
-+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
-+	if (dm->support_ic_type &
-+	    (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) {
-+		dig_t->enable_adjust_big_jump = 1;
-+
-+		if (dm->support_ic_type & ODM_RTL8822B)
-+			ret_value = odm_get_bb_reg(dm, R_0x8c8, MASKLWORD);
-+		else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
-+			ret_value = odm_get_bb_reg(dm, R_0xc74, MASKLWORD);
-+
-+		dig_t->big_jump_step1 = (u8)(ret_value & 0xe) >> 1;
-+		dig_t->big_jump_step2 = (u8)(ret_value & 0x30) >> 4;
-+		dig_t->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6;
-+
-+		for (i = 0; i < sizeof(dig_t->big_jump_lmt); i++) {
-+			if (dig_t->big_jump_lmt[i] == 0)
-+				dig_t->big_jump_lmt[i] = 0x64;
-+				/* Set -10dBm as default value */
-+		}
-+	}
-+#endif
-+
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+		dm->original_dig_restore = true;
-+		dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
-+		dm->tdma_dig_timer_ms = DIG_TIMER_MS;
-+	#endif
-+	dig_t->tdma_force_l_igi = 0xff;
-+	dig_t->tdma_force_h_igi = 0xff;
-+#endif
-+#ifdef CFG_DIG_DAMPING_CHK
-+	phydm_dig_recorder_reset(dm);
-+	dig_t->dig_dl_en = 1;
-+#endif
-+
-+#ifdef PHYDM_HW_IGI
-+	phydm_hwigi_init(dm);
-+#endif
-+}
-+void phydm_dig_abs_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
-+{
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
-+
-+	if (is_dfs_band) {
-+		if (*dm->band_width == CHANNEL_WIDTH_20){
-+			if (dm->support_ic_type &
-+				(ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
-+				if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
-+					dig_t->dm_dig_min = DIG_MIN_DFS + 2;
-+				else
-+					dig_t->dm_dig_min = DIG_MIN_DFS;
-+			}
-+			else
-+				dig_t->dm_dig_min = DIG_MIN_DFS;
-+		}
-+		else
-+			dig_t->dm_dig_min = DIG_MIN_DFS;
-+
-+		dig_t->dig_max_of_min = DIG_MIN_DFS;
-+		dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
-+	} else if (!dm->is_linked) {
-+		dig_t->dm_dig_max = DIG_MAX_COVERAGR;
-+		dig_t->dm_dig_min = DIG_MIN_COVERAGE;
-+	} else {
-+		if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
-+		/*service > 2 devices*/
-+			dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
-+			#if (DIG_HW == 1)
-+			dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
-+			#else
-+			dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
-+			#endif
-+		} else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
-+		/*service 1 devices*/
-+			if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE &&
-+			    dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
-+			/*dig_max shouldn't be too high because of adaptivity*/
-+				dig_t->dm_dig_max =
-+					MIN_2((adapt->th_l2h + 40),
-+					      DIG_MAX_PERFORMANCE_MODE);
-+			else
-+				dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
-+
-+			dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
-+		}
-+
-+		if (dm->support_ic_type &
-+		    (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
-+			dig_t->dm_dig_min = 0x1c;
-+		else if (dm->support_ic_type & ODM_RTL8197F)
-+			dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
-+		else
-+			dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
-+		  dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
-+}
-+
-+void phydm_dig_dym_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
-+{
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+#ifdef CFG_DIG_DAMPING_CHK
-+	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
-+#endif
-+	u8 offset = 15, tmp_max = 0;
-+	u8 max_of_rssi_min = 0;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
-+
-+	if (!dm->is_linked) {
-+		/*@if no link, always stay at lower bound*/
-+		dig_t->rx_gain_range_max = dig_t->dig_max_of_min;
-+		dig_t->rx_gain_range_min = dig_t->dm_dig_min;
-+
-+		PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
-+			  dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
-+		return;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n", dm->rssi_min, offset);
-+
-+	/* @DIG lower bound */
-+	if (is_dfs_band)
-+		dig_t->rx_gain_range_min = dig_t->dm_dig_min;
-+	else if (dm->rssi_min > dig_t->dig_max_of_min)
-+		dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
-+	else if (dm->rssi_min < dig_t->dm_dig_min)
-+		dig_t->rx_gain_range_min = dig_t->dm_dig_min;
-+	else
-+		dig_t->rx_gain_range_min = dm->rssi_min;
-+
-+#ifdef CFG_DIG_DAMPING_CHK
-+	/*@Limit Dyn min by damping*/
-+	if (dig_t->dig_dl_en &&
-+	    dig_rc->damping_limit_en &&
-+	    dig_t->rx_gain_range_min < dig_rc->damping_limit_val) {
-+		PHYDM_DBG(dm, DBG_DIG,
-+			  "[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\n",
-+			  dig_t->rx_gain_range_min, dig_rc->damping_limit_val);
-+
-+		dig_t->rx_gain_range_min = dig_rc->damping_limit_val;
-+	}
-+#endif
-+
-+	/* @DIG upper bound */
-+	tmp_max = dig_t->rx_gain_range_min + offset;
-+	if (dig_t->rx_gain_range_min != dm->rssi_min) {
-+		max_of_rssi_min = dm->rssi_min + offset;
-+		if (tmp_max > max_of_rssi_min)
-+			tmp_max = max_of_rssi_min;
-+	}
-+
-+	if (tmp_max > dig_t->dm_dig_max)
-+		dig_t->rx_gain_range_max = dig_t->dm_dig_max;
-+	else if (tmp_max < dig_t->dm_dig_min)
-+		dig_t->rx_gain_range_max = dig_t->dm_dig_min;
-+	else
-+		dig_t->rx_gain_range_max = tmp_max;
-+
-+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	/* @1 Force Lower Bound for AntDiv */
-+	if (!dm->is_one_entry_only &&
-+	    (dm->support_ability & ODM_BB_ANT_DIV) &&
-+	    (dm->ant_div_type == CG_TRX_HW_ANTDIV ||
-+	     dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
-+		if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
-+			dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
-+		else
-+			dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
-+
-+		PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
-+			  dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
-+	}
-+	#endif
-+
-+	PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
-+		  dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
-+}
-+
-+void phydm_dig_abnormal_case(struct dm_struct *dm)
-+{
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+	/* @Abnormal lower bound case */
-+	if (dig_t->rx_gain_range_min > dig_t->rx_gain_range_max)
-+		dig_t->rx_gain_range_min = dig_t->rx_gain_range_max;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "Abnoraml checked {Max, Min}={0x%x, 0x%x}\n",
-+		  dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
-+}
-+
-+u8 phydm_new_igi_by_fa(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *step_size)
-+{
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+	if (fa_cnt > dig_t->fa_th[2])
-+		igi = igi + step_size[0];
-+	else if (fa_cnt > dig_t->fa_th[1])
-+		igi = igi + step_size[1];
-+	else if (fa_cnt < dig_t->fa_th[0])
-+		igi = igi - step_size[2];
-+
-+	return igi;
-+}
-+
-+u8 phydm_get_new_igi(struct dm_struct *dm, u8 igi, u32 fa_cnt,
-+		     boolean is_dfs_band)
-+{
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	u8 step[3] = {0};
-+
-+	if (dm->is_linked) {
-+		if (dm->pre_rssi_min <= dm->rssi_min) {
-+			PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
-+			step[0] = 2;
-+			step[1] = 1;
-+			step[2] = 2;
-+		} else {
-+			step[0] = 4;
-+			step[1] = 2;
-+			step[2] = 2;
-+		}
-+	} else {
-+		step[0] = 2;
-+		step[1] = 1;
-+		step[2] = 2;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
-+		  step[0]);
-+
-+	if (dm->first_connect) {
-+		if (is_dfs_band) {
-+			if (dm->rssi_min > DIG_MAX_DFS)
-+				igi = DIG_MAX_DFS;
-+			else
-+				igi = dm->rssi_min;
-+			PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
-+				  dig_t->rx_gain_range_max);
-+		} else {
-+			igi = dig_t->rx_gain_range_min;
-+		}
-+
-+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+		#if (RTL8812A_SUPPORT)
-+		if (dm->support_ic_type == ODM_RTL8812)
-+			odm_config_bb_with_header_file(dm,
-+						       CONFIG_BB_AGC_TAB_DIFF);
-+		#endif
-+		#endif
-+		PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
-+	} else if (dm->is_linked) {
-+		PHYDM_DBG(dm, DBG_DIG, "Adjust IGI @ linked\n");
-+		/* @4 Abnormal # beacon case */
-+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+		if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 &&
-+		    fa_cnt < DM_DIG_FA_TH1 && dm->bsta_state &&
-+		    dm->support_ic_type != ODM_RTL8723D &&
-+		    dm->support_ic_type != ODM_RTL8822C) {
-+			dig_t->rx_gain_range_min = 0x1c;
-+			igi = dig_t->rx_gain_range_min;
-+			PHYDM_DBG(dm, DBG_DIG, "Beacon_num=%d,force igi=0x%x\n",
-+				  dm->phy_dbg_info.num_qry_beacon_pkt, igi);
-+		} else {
-+			igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
-+		}
-+		#else
-+		igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
-+		#endif
-+	} else {
-+		/* @2 Before link */
-+		PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
-+
-+		if (dm->first_disconnect) {
-+			igi = dig_t->dm_dig_min;
-+			PHYDM_DBG(dm, DBG_DIG,
-+				  "First disconnect:foce IGI to lower bound\n");
-+		} else {
-+			PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
-+				  igi, fa_cnt);
-+
-+			igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
-+		}
-+	}
-+
-+	/*@Check IGI by dyn-upper/lower bound */
-+	if (igi < dig_t->rx_gain_range_min)
-+		igi = dig_t->rx_gain_range_min;
-+
-+	if (igi >= dig_t->rx_gain_range_max) {
-+		igi = dig_t->rx_gain_range_max;
-+		dig_t->igi_dyn_up_hit = true;
-+	} else {
-+		dig_t->igi_dyn_up_hit = false;
-+	}
-+	PHYDM_DBG(dm, DBG_DIG, "igi_dyn_up_hit=%d\n",
-+		  dig_t->igi_dyn_up_hit);
-+
-+	PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n",
-+		  fa_cnt, dig_t->cur_ig_value, igi);
-+
-+	return igi;
-+}
-+
-+boolean phydm_dig_dfs_mode_en(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean dfs_mode_en = false;
-+
-+	/* @Modify lower bound for DFS band */
-+	if (dm->is_dfs_band) {
-+		#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+		dfs_mode_en = true;
-+		#else
-+		if (phydm_dfs_master_enabled(dm))
-+			dfs_mode_en = true;
-+		#endif
-+		PHYDM_DBG(dm, DBG_DIG, "In DFS band\n");
-+	}
-+	return dfs_mode_en;
-+}
-+
-+void phydm_dig(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_fa_struct *fa = &dm->false_alm_cnt;
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
-+#endif
-+	u8 igi = dig_t->cur_ig_value;
-+	u8 new_igi = 0x20;
-+	u32 fa_cnt = fa->cnt_all;
-+	boolean dfs_mode_en = false;
-+
-+#ifdef PHYDM_DCC_ENHANCE
-+	if (dm->dm_dcc_info.dcc_en)
-+		fa_cnt = fa->cnt_ofdm_fail; /*OFDM FA only*/
-+#endif
-+
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	if (!(dm->original_dig_restore)) {
-+		if (dig_t->cur_ig_value_tdma == 0)
-+			dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
-+
-+		igi = dig_t->cur_ig_value_tdma;
-+		fa_cnt = falm_cnt_acc->cnt_all_1sec;
-+	}
-+#endif
-+
-+	if (phydm_dig_abort(dm)) {
-+		dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
-+		return;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_DIG, "%s Start===>\n", __func__);
-+	PHYDM_DBG(dm, DBG_DIG,
-+		  "is_linked=%d, RSSI=%d, 1stConnect=%d, 1stDisconnect=%d\n",
-+		  dm->is_linked, dm->rssi_min,
-+		  dm->first_connect, dm->first_disconnect);
-+
-+	PHYDM_DBG(dm, DBG_DIG, "DIG ((%s)) mode\n",
-+		  (*dm->bb_op_mode ? "Balance" : "Performance"));
-+
-+	/*@DFS mode enable check*/
-+	dfs_mode_en = phydm_dig_dfs_mode_en(dm);
-+
-+#ifdef CFG_DIG_DAMPING_CHK
-+	/*Record IGI History*/
-+	phydm_dig_recorder(dm, igi, fa_cnt);
-+
-+	/*@DIG Damping Check*/
-+	phydm_dig_damping_chk(dm);
-+#endif
-+
-+	/*@Absolute Boundary Decision */
-+	phydm_dig_abs_boundary_decision(dm, dfs_mode_en);
-+
-+	/*@Dynamic Boundary Decision*/
-+	phydm_dig_dym_boundary_decision(dm, dfs_mode_en);
-+
-+	/*@Abnormal case check*/
-+	phydm_dig_abnormal_case(dm);
-+
-+	/*@FA threshold decision */
-+	phydm_fa_threshold_check(dm, dfs_mode_en);
-+
-+	/*Select new IGI by FA */
-+	new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
-+
-+	/* @1 Update status */
-+	#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	if (!(dm->original_dig_restore)) {
-+		dig_t->cur_ig_value_tdma = new_igi;
-+		/*@It is possible fa_acc_1sec_tsf >= */
-+		/*@1sec while tdma_dig_state == 0*/
-+		if (dig_t->tdma_dig_state != 0)
-+			odm_write_dig(dm, dig_t->cur_ig_value_tdma);
-+	} else
-+	#endif
-+		odm_write_dig(dm, new_igi);
-+}
-+
-+void phydm_dig_lps_32k(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 current_igi = dm->rssi_min;
-+
-+	odm_write_dig(dm, current_igi);
-+}
-+
-+void phydm_dig_by_rssi_lps(void *dm_void)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *falm_cnt;
-+
-+	u8 rssi_lower = DIG_MIN_LPS; /* @0x1E or 0x1C */
-+	u8 current_igi = dm->rssi_min;
-+
-+	falm_cnt = &dm->false_alm_cnt;
-+	if (phydm_dig_abort(dm))
-+		return;
-+
-+	current_igi = current_igi + RSSI_OFFSET_DIG_LPS;
-+	PHYDM_DBG(dm, DBG_DIG, "%s==>\n", __func__);
-+
-+	/* Using FW PS mode to make IGI */
-+	/* @Adjust by  FA in LPS MODE */
-+	if (falm_cnt->cnt_all > DM_DIG_FA_TH2_LPS)
-+		current_igi = current_igi + 4;
-+	else if (falm_cnt->cnt_all > DM_DIG_FA_TH1_LPS)
-+		current_igi = current_igi + 2;
-+	else if (falm_cnt->cnt_all < DM_DIG_FA_TH0_LPS)
-+		current_igi = current_igi - 2;
-+
-+	/* @Lower bound checking */
-+
-+	/* RSSI Lower bound check */
-+	if ((dm->rssi_min - 10) > DIG_MIN_LPS)
-+		rssi_lower = (dm->rssi_min - 10);
-+	else
-+		rssi_lower = DIG_MIN_LPS;
-+
-+	/* Upper and Lower Bound checking */
-+	if (current_igi > DIG_MAX_LPS)
-+		current_igi = DIG_MAX_LPS;
-+	else if (current_igi < rssi_lower)
-+		current_igi = rssi_lower;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "fa_cnt_all=%d, rssi_min=%d, curr_igi=0x%x\n",
-+		  falm_cnt->cnt_all, dm->rssi_min, current_igi);
-+	odm_write_dig(dm, current_igi);
-+#endif
-+}
-+
-+void phydm_get_dig_coverage(void *dm_void, u8 *max, u8 *min)
-+{
-+	*min = DIG_MIN_COVERAGE;
-+	*max = DIG_MAX_PERFORMANCE_MODE;
-+}
-+
-+u8 phydm_get_igi_for_target_pin_scan(void *dm_void, u8 rssi)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 igi = 0;
-+	u8 max = 0;
-+	u8 min = 0;
-+
-+	igi = rssi + 10;
-+
-+	phydm_get_dig_coverage(dm, &max, &min);
-+
-+	if (igi > max)
-+		igi = max;
-+	else if (igi < min)
-+		igi = min;
-+
-+	return igi;
-+}
-+
-+/* @3============================================================
-+ * 3 FASLE ALARM CHECK
-+ * 3============================================================
-+ */
-+void phydm_false_alarm_counter_reg_reset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
-+#endif
-+	u32 false_alm_cnt = 0;
-+
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	if (!(dm->original_dig_restore)) {
-+		if (dig_t->cur_ig_value_tdma == 0)
-+			dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
-+
-+		false_alm_cnt = falm_cnt_acc->cnt_all_1sec;
-+	} else
-+#endif
-+	{
-+		false_alm_cnt = falm_cnt->cnt_all;
-+	}
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		if (dm->support_ic_type & ODM_RTL8723F) {
-+			/* @reset CCK FA and CCA counter */
-+			odm_set_bb_reg(dm, R_0x2a44, BIT(21), 0);
-+			odm_set_bb_reg(dm, R_0x2a44, BIT(21), 1);
-+		} else {
-+		/* @reset CCK FA counter */
-+		odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 0);
-+		odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 2);
-+
-+		/* @reset CCK CCA counter */
-+		odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 0);
-+		odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 2);
-+		}
-+		/* @Disable common rx clk gating => WLANBB-1106*/
-+		odm_set_bb_reg(dm, R_0x1d2c, BIT(31), 0);
-+		/* @reset OFDM CCA counter, OFDM FA counter*/
-+		phydm_reset_bb_hw_cnt(dm);
-+		/* @Enable common rx clk gating => WLANBB-1106*/
-+		odm_set_bb_reg(dm, R_0x1d2c, BIT(31), 1);
-+	}
-+#endif
-+#if (ODM_IC_11N_SERIES_SUPPORT)
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		/* @reset false alarm counter registers*/
-+		odm_set_bb_reg(dm, R_0xc0c, BIT(31), 1);
-+		odm_set_bb_reg(dm, R_0xc0c, BIT(31), 0);
-+		odm_set_bb_reg(dm, R_0xd00, BIT(27), 1);
-+		odm_set_bb_reg(dm, R_0xd00, BIT(27), 0);
-+
-+		/* @update ofdm counter*/
-+		/* @update page C counter*/
-+		odm_set_bb_reg(dm, R_0xc00, BIT(31), 0);
-+		/* @update page D counter*/
-+		odm_set_bb_reg(dm, R_0xd00, BIT(31), 0);
-+
-+		/* @reset CCK CCA counter*/
-+		odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 0);
-+		odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 2);
-+
-+		/* @reset CCK FA counter*/
-+		odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 0);
-+		odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 2);
-+
-+		/* @reset CRC32 counter*/
-+		odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
-+		odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
-+	}
-+#endif /* @#if (ODM_IC_11N_SERIES_SUPPORT) */
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT)
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		#if (RTL8881A_SUPPORT)
-+		/* @Reset FA counter by enable/disable OFDM */
-+		if ((dm->support_ic_type == ODM_RTL8881A) &&
-+		    false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) {
-+			/* reset OFDM */
-+			odm_set_bb_reg(dm, R_0x808, BIT(29), 0);
-+			odm_set_bb_reg(dm, R_0x808, BIT(29), 1);
-+			false_alm_cnt->cnt_ofdm_fail_pre = 0;
-+			PHYDM_DBG(dm, DBG_FA_CNT, "Reset FA_cnt\n");
-+		}
-+		#endif /* @#if (RTL8881A_SUPPORT) */
-+
-+		/* @reset OFDM FA countner */
-+		odm_set_bb_reg(dm, R_0x9a4, BIT(17), 1);
-+		odm_set_bb_reg(dm, R_0x9a4, BIT(17), 0);
-+
-+		/* @reset CCK FA counter */
-+		odm_set_bb_reg(dm, R_0xa2c, BIT(15), 0);
-+		odm_set_bb_reg(dm, R_0xa2c, BIT(15), 1);
-+
-+		/* @reset CCA counter */
-+		phydm_reset_bb_hw_cnt(dm);
-+	}
-+#endif /* @#if (ODM_IC_11AC_SERIES_SUPPORT) */
-+}
-+
-+void phydm_false_alarm_counter_reg_hold(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_RTL8723F)
-+		return;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		/* @hold cck counter */
-+		odm_set_bb_reg(dm, R_0x1a2c, BIT(12), 1);
-+		odm_set_bb_reg(dm, R_0x1a2c, BIT(14), 1);
-+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		/*@hold ofdm counter*/
-+		/*@hold page C counter*/
-+		odm_set_bb_reg(dm, R_0xc00, BIT(31), 1);
-+		/*@hold page D counter*/
-+		odm_set_bb_reg(dm, R_0xd00, BIT(31), 1);
-+
-+		/*@hold cck counter*/
-+		odm_set_bb_reg(dm, R_0xa2c, BIT(12), 1);
-+		odm_set_bb_reg(dm, R_0xa2c, BIT(14), 1);
-+	}
-+}
-+
-+#if (ODM_IC_11N_SERIES_SUPPORT)
-+void phydm_fa_cnt_statistics_n(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
-+	u32 reg = 0;
-+
-+	if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
-+		return;
-+
-+	/* @hold ofdm & cck counter */
-+	phydm_false_alarm_counter_reg_hold(dm);
-+
-+	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
-+	fa_t->cnt_fast_fsync = (reg & 0xffff);
-+	fa_t->cnt_sb_search_fail = ((reg & 0xffff0000) >> 16);
-+
-+	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
-+	fa_t->cnt_ofdm_cca = (reg & 0xffff);
-+	fa_t->cnt_parity_fail = ((reg & 0xffff0000) >> 16);
-+
-+	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
-+	fa_t->cnt_rate_illegal = (reg & 0xffff);
-+	fa_t->cnt_crc8_fail = ((reg & 0xffff0000) >> 16);
-+
-+	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
-+	fa_t->cnt_mcs_fail = (reg & 0xffff);
-+
-+	fa_t->cnt_ofdm_fail =
-+		fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
-+		fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
-+		fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail;
-+
-+	/* read CCK CRC32 counter */
-+	fa_t->cnt_cck_crc32_error = odm_get_bb_reg(dm, R_0xf84, MASKDWORD);
-+	fa_t->cnt_cck_crc32_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);
-+
-+	/* read OFDM CRC32 counter */
-+	reg = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD);
-+	fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;
-+	fa_t->cnt_ofdm_crc32_ok = reg & 0xffff;
-+
-+	/* read OFDM2 CRC32 counter */
-+	reg = odm_get_bb_reg(dm, R_0xf9c, MASKDWORD);
-+	fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;
-+	fa_t->cnt_ofdm2_crc32_ok = reg & 0xffff;
-+
-+	/* read HT CRC32 counter */
-+	reg = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD);
-+	fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;
-+	fa_t->cnt_ht_crc32_ok = reg & 0xffff;
-+
-+	/* read HT2 CRC32 counter */
-+	reg = odm_get_bb_reg(dm, R_0xf98, MASKDWORD);
-+	fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;
-+	fa_t->cnt_ht2_crc32_ok = reg & 0xffff;
-+
-+	/* read VHT CRC32 counter */
-+	fa_t->cnt_vht_crc32_error = 0;
-+	fa_t->cnt_vht_crc32_ok = 0;
-+
-+	#if (RTL8723D_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8723D) {
-+		/* read HT CRC32 agg counter */
-+		reg = odm_get_bb_reg(dm, R_0xfb8, MASKDWORD);
-+		fa_t->cnt_ht_crc32_error_agg = (reg & 0xffff0000) >> 16;
-+		fa_t->cnt_ht_crc32_ok_agg = reg & 0xffff;
-+	}
-+	#endif
-+
-+	#if (RTL8188E_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8188E) {
-+		reg = odm_get_bb_reg(dm, ODM_REG_SC_CNT_11N, MASKDWORD);
-+		fa_t->cnt_bw_lsc = (reg & 0xffff);
-+		fa_t->cnt_bw_usc = ((reg & 0xffff0000) >> 16);
-+	}
-+	#endif
-+
-+	reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0);
-+	fa_t->cnt_cck_fail = reg;
-+
-+	reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3);
-+	fa_t->cnt_cck_fail += (reg & 0xff) << 8;
-+
-+	reg = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD);
-+	fa_t->cnt_cck_cca = ((reg & 0xFF) << 8) | ((reg & 0xFF00) >> 8);
-+
-+	fa_t->cnt_all_pre = fa_t->cnt_all;
-+
-+	fa_t->cnt_all = fa_t->cnt_fast_fsync +
-+			fa_t->cnt_sb_search_fail +
-+			fa_t->cnt_parity_fail +
-+			fa_t->cnt_rate_illegal +
-+			fa_t->cnt_crc8_fail +
-+			fa_t->cnt_mcs_fail +
-+			fa_t->cnt_cck_fail;
-+
-+	fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca + fa_t->cnt_cck_cca;
-+}
-+#endif
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT)
-+void phydm_fa_cnt_statistics_ac(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
-+	u32 ret_value = 0;
-+	u32 cck_enable = 0;
-+
-+	if (!(dm->support_ic_type & ODM_IC_11AC_SERIES))
-+		return;
-+
-+	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11AC, MASKDWORD);
-+	fa_t->cnt_fast_fsync = (ret_value & 0xffff0000) >> 16;
-+
-+	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11AC, MASKDWORD);
-+	fa_t->cnt_sb_search_fail = ret_value & 0xffff;
-+
-+	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11AC, MASKDWORD);
-+	fa_t->cnt_parity_fail = ret_value & 0xffff;
-+	fa_t->cnt_rate_illegal = (ret_value & 0xffff0000) >> 16;
-+
-+	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11AC, MASKDWORD);
-+	fa_t->cnt_crc8_fail = ret_value & 0xffff;
-+	fa_t->cnt_mcs_fail = (ret_value & 0xffff0000) >> 16;
-+
-+	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE5_11AC, MASKDWORD);
-+	fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff;
-+	fa_t->cnt_crc8_fail_vhtb = ret_value & 0xffff0000 >> 16;
-+
-+	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE6_11AC, MASKDWORD);
-+	fa_t->cnt_mcs_fail_vht = ret_value & 0xffff;
-+
-+	/* read OFDM FA counter */
-+	fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0xf48, MASKLWORD);
-+
-+	/* Read CCK FA counter */
-+	fa_t->cnt_cck_fail = odm_get_bb_reg(dm, ODM_REG_CCK_FA_11AC, MASKLWORD);
-+
-+	/* read CCK/OFDM CCA counter */
-+	ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD);
-+	fa_t->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16;
-+	fa_t->cnt_cck_cca = ret_value & 0xffff;
-+
-+	/* read CCK CRC32 counter */
-+	ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD);
-+	fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
-+	fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
-+
-+	/* read OFDM CRC32 counter */
-+	ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD);
-+	fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
-+	fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
-+
-+	/* read OFDM2 CRC32 counter */
-+	ret_value = odm_get_bb_reg(dm, R_0xf1c, MASKDWORD);
-+	fa_t->cnt_ofdm2_crc32_ok = ret_value & 0xffff;
-+	fa_t->cnt_ofdm2_crc32_error = (ret_value & 0xffff0000) >> 16;
-+
-+	/* read HT CRC32 counter */
-+	ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD);
-+	fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
-+	fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
-+
-+	/* read HT2 CRC32 counter */
-+	ret_value = odm_get_bb_reg(dm, R_0xf18, MASKDWORD);
-+	fa_t->cnt_ht2_crc32_ok = ret_value & 0xffff;
-+	fa_t->cnt_ht2_crc32_error = (ret_value & 0xffff0000) >> 16;
-+
-+	/* read VHT CRC32 counter */
-+	ret_value = odm_get_bb_reg(dm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD);
-+	fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
-+	fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
-+
-+	/*read VHT2 CRC32 counter */
-+	ret_value = odm_get_bb_reg(dm, R_0xf54, MASKDWORD);
-+	fa_t->cnt_vht2_crc32_ok = ret_value & 0xffff;
-+	fa_t->cnt_vht2_crc32_error = (ret_value & 0xffff0000) >> 16;
-+
-+	#if (RTL8881A_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8881A) {
-+		u32 tmp = 0;
-+
-+		if (fa_t->cnt_ofdm_fail >= fa_t->cnt_ofdm_fail_pre) {
-+			tmp = fa_t->cnt_ofdm_fail_pre;
-+			fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
-+			fa_t->cnt_ofdm_fail = fa_t->cnt_ofdm_fail - tmp;
-+		} else {
-+			fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
-+		}
-+
-+		PHYDM_DBG(dm, DBG_FA_CNT,
-+			  "[8881]cnt_ofdm_fail{curr,pre}={%d,%d}\n",
-+			  fa_t->cnt_ofdm_fail_pre, tmp);
-+	}
-+	#endif
-+
-+	cck_enable = odm_get_bb_reg(dm, ODM_REG_BB_RX_PATH_11AC, BIT(28));
-+
-+	if (cck_enable) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
-+		fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;
-+		fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
-+	} else {
-+		fa_t->cnt_all = fa_t->cnt_ofdm_fail;
-+		fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
-+	}
-+}
-+#endif
-+
-+u32 phydm_get_edcca_report(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
-+	u32 dbg_port = dm->adaptivity.adaptivity_dbg_port;
-+	u32 val = 0;
-+
-+	if (dm->support_ic_type & ODM_RTL8723D) {
-+		val = odm_get_bb_reg(dm, R_0x9a0, BIT(29));
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		val = odm_get_bb_reg(dm, R_0x2d38, BIT(24));
-+	} else if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, dbg_port)) {
-+		if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))
-+			val = (phydm_get_bb_dbg_port_val(dm) & BIT(30)) >> 30;
-+		else
-+			val = (phydm_get_bb_dbg_port_val(dm) & BIT(29)) >> 29;
-+		phydm_release_bb_dbg_port(dm);
-+	}
-+
-+	return val;
-+}
-+
-+void phydm_get_dbg_port_info(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		fa_t->dbg_port0 = odm_get_bb_reg(dm, R_0x2db4, MASKDWORD);
-+	} else {
-+		/*set debug port to 0x0*/
-+		if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {
-+			fa_t->dbg_port0 = phydm_get_bb_dbg_port_val(dm);
-+			phydm_release_bb_dbg_port(dm);
-+		}
-+	}
-+
-+	fa_t->edcca_flag = (boolean)phydm_get_edcca_report(dm);
-+
-+	PHYDM_DBG(dm, DBG_FA_CNT, "FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n",
-+		  fa_t->dbg_port0, fa_t->edcca_flag);
-+}
-+
-+void phydm_set_crc32_cnt2_rate(void *dm_void, u8 rate_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
-+	boolean is_ofdm_rate = phydm_is_ofdm_rate(dm, rate_idx);
-+	boolean is_ht_rate = phydm_is_ht_rate(dm, rate_idx);
-+	boolean is_vht_rate = phydm_is_vht_rate(dm, rate_idx);
-+	u32 reg_addr = 0x0;
-+	u32 ofdm_rate_bitmask = 0x0;
-+	u32 ht_mcs_bitmask = 0x0;
-+	u32 vht_mcs_bitmask = 0x0;
-+	u32 vht_ss_bitmask = 0x0;
-+	u8 rate = 0x0;
-+	u8 ss = 0x0;
-+
-+	if (!is_ofdm_rate && !is_ht_rate && !is_vht_rate)
-+		PHYDM_DBG(dm, DBG_FA_CNT,
-+			  "[FA CNT] rate_idx = (0x%x) is not supported !\n",
-+			  rate_idx);
-+
-+	switch (dm->ic_ip_series) {
-+	case PHYDM_IC_N:
-+		reg_addr = R_0xf04;
-+		ofdm_rate_bitmask = 0x0000f000;
-+		ht_mcs_bitmask = 0x007f0000;
-+		break;
-+	case PHYDM_IC_AC:
-+		reg_addr = R_0xb04;
-+		ofdm_rate_bitmask = 0x0000f000;
-+		ht_mcs_bitmask = 0x007f0000;
-+		vht_mcs_bitmask = 0x0f000000;
-+		vht_ss_bitmask = 0x30000000;
-+		break;
-+	case PHYDM_IC_JGR3:
-+		reg_addr = R_0x1eb8;
-+		ofdm_rate_bitmask = 0x00000f00;
-+		ht_mcs_bitmask = 0x007f0000;
-+		vht_mcs_bitmask = 0x0000f000;
-+		vht_ss_bitmask = 0x000000c0;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (is_ofdm_rate) {
-+		rate = phydm_legacy_rate_2_spec_rate(dm, rate_idx);
-+
-+		odm_set_bb_reg(dm, reg_addr, ofdm_rate_bitmask, rate);
-+		fa_t->ofdm2_rate_idx = rate_idx;
-+	} else if (is_ht_rate) {
-+		rate = phydm_rate_2_rate_digit(dm, rate_idx);
-+
-+		odm_set_bb_reg(dm, reg_addr, ht_mcs_bitmask, rate);
-+		fa_t->ht2_rate_idx = rate_idx;
-+	} else if (is_vht_rate) {
-+		rate = phydm_rate_2_rate_digit(dm, rate_idx);
-+		ss = phydm_rate_to_num_ss(dm, rate_idx);
-+
-+		odm_set_bb_reg(dm, reg_addr, vht_mcs_bitmask, rate);
-+		odm_set_bb_reg(dm, reg_addr, vht_ss_bitmask, ss - 1);
-+		fa_t->vht2_rate_idx = rate_idx;
-+	}
-+}
-+
-+void phydm_false_alarm_counter_statistics(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
-+	char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
-+	u32 tmp = 0;
-+
-+	if (!(dm->support_ability & ODM_BB_FA_CNT))
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_FA_CNT, "%s======>\n", __func__);
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		phydm_fa_cnt_statistics_jgr3(dm);
-+		#endif
-+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		#if (ODM_IC_11N_SERIES_SUPPORT)
-+		phydm_fa_cnt_statistics_n(dm);
-+		#endif
-+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		#if (ODM_IC_11AC_SERIES_SUPPORT)
-+		phydm_fa_cnt_statistics_ac(dm);
-+		#endif
-+	}
-+
-+	phydm_get_dbg_port_info(dm);
-+	phydm_false_alarm_counter_reg_reset(dm_void);
-+
-+	fa_t->time_fa_all = fa_t->cnt_fast_fsync * 12 +
-+			    fa_t->cnt_sb_search_fail * 12 +
-+			    fa_t->cnt_parity_fail * 28 +
-+			    fa_t->cnt_rate_illegal * 28 +
-+			    fa_t->cnt_crc8_fail * 20 +
-+			    fa_t->cnt_crc8_fail_vhta * 28 +
-+			    fa_t->cnt_mcs_fail_vht * 36 +
-+			    fa_t->cnt_mcs_fail * 32 +
-+			    fa_t->cnt_cck_fail * 80;
-+
-+	fa_t->cnt_crc32_error_all = fa_t->cnt_vht_crc32_error +
-+				    fa_t->cnt_ht_crc32_error +
-+				    fa_t->cnt_ofdm_crc32_error +
-+				    fa_t->cnt_cck_crc32_error;
-+
-+	fa_t->cnt_crc32_ok_all = fa_t->cnt_vht_crc32_ok +
-+				 fa_t->cnt_ht_crc32_ok +
-+				 fa_t->cnt_ofdm_crc32_ok +
-+				 fa_t->cnt_cck_crc32_ok;
-+
-+	PHYDM_DBG(dm, DBG_FA_CNT,
-+		  "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
-+		  fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
-+	PHYDM_DBG(dm, DBG_FA_CNT,
-+		  "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
-+		  fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);
-+	PHYDM_DBG(dm, DBG_FA_CNT,
-+		  "[OFDM FA] Parity=%d, Rate=%d, Fast_Fsync=%d, SBD=%d\n",
-+		  fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
-+		  fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail);
-+	PHYDM_DBG(dm, DBG_FA_CNT, "[HT FA] CRC8=%d, MCS=%d\n",
-+		  fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail);
-+#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
-+	if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
-+		PHYDM_DBG(dm, DBG_FA_CNT,
-+			  "[VHT FA] SIGA_CRC8=%d, SIGB_CRC8=%d, MCS=%d\n",
-+			  fa_t->cnt_crc8_fail_vhta, fa_t->cnt_crc8_fail_vhtb,
-+			  fa_t->cnt_mcs_fail_vht);
-+	}
-+#endif
-+
-+	PHYDM_DBG(dm, DBG_FA_CNT,
-+		  "[CRC32 OK Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
-+		  fa_t->cnt_cck_crc32_ok, fa_t->cnt_ofdm_crc32_ok,
-+		  fa_t->cnt_ht_crc32_ok, fa_t->cnt_vht_crc32_ok,
-+		  fa_t->cnt_crc32_ok_all);
-+	PHYDM_DBG(dm, DBG_FA_CNT,
-+		  "[CRC32 Err Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n",
-+		  fa_t->cnt_cck_crc32_error, fa_t->cnt_ofdm_crc32_error,
-+		  fa_t->cnt_ht_crc32_error, fa_t->cnt_vht_crc32_error,
-+		  fa_t->cnt_crc32_error_all);
-+
-+	if (fa_t->ofdm2_rate_idx) {
-+		tmp = fa_t->cnt_ofdm2_crc32_error + fa_t->cnt_ofdm2_crc32_ok;
-+		fa_t->ofdm2_pcr = (u8)PHYDM_DIV(fa_t->cnt_ofdm2_crc32_ok * 100,
-+						tmp);
-+		phydm_print_rate_2_buff(dm, fa_t->ofdm2_rate_idx, dbg_buf,
-+					PHYDM_SNPRINT_SIZE);
-+		PHYDM_DBG(dm, DBG_FA_CNT,
-+			  "[OFDM:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
-+			  dbg_buf, fa_t->cnt_ofdm2_crc32_error,
-+			  fa_t->cnt_ofdm2_crc32_ok, fa_t->ofdm2_pcr);
-+	} else {
-+		phydm_set_crc32_cnt2_rate(dm, ODM_RATE6M);
-+	}
-+
-+	if (fa_t->ht2_rate_idx) {
-+		tmp = fa_t->cnt_ht2_crc32_error + fa_t->cnt_ht2_crc32_ok;
-+		fa_t->ht2_pcr = (u8)PHYDM_DIV(fa_t->cnt_ht2_crc32_ok * 100,
-+					      tmp);
-+		phydm_print_rate_2_buff(dm, fa_t->ht2_rate_idx, dbg_buf,
-+					PHYDM_SNPRINT_SIZE);
-+		PHYDM_DBG(dm, DBG_FA_CNT,
-+			  "[HT:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
-+			  dbg_buf, fa_t->cnt_ht2_crc32_error,
-+			  fa_t->cnt_ht2_crc32_ok, fa_t->ht2_pcr);
-+	} else {
-+		phydm_set_crc32_cnt2_rate(dm, ODM_RATEMCS0);
-+	}
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
-+	if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) {
-+		if (fa_t->vht2_rate_idx) {
-+			tmp = fa_t->cnt_vht2_crc32_error +
-+			      fa_t->cnt_vht2_crc32_ok;
-+			fa_t->vht2_pcr = (u8)PHYDM_DIV(fa_t->cnt_vht2_crc32_ok *
-+						       100, tmp);
-+			phydm_print_rate_2_buff(dm, fa_t->vht2_rate_idx,
-+						dbg_buf, PHYDM_SNPRINT_SIZE);
-+			PHYDM_DBG(dm, DBG_FA_CNT,
-+				  "[VHT:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n",
-+				  dbg_buf, fa_t->cnt_vht2_crc32_error,
-+				  fa_t->cnt_vht2_crc32_ok, fa_t->vht2_pcr);
-+		} else {
-+			phydm_set_crc32_cnt2_rate(dm, ODM_RATEVHTSS1MCS0);
-+		}
-+	}
-+#endif
-+}
-+
-+void phydm_fill_fw_dig_info(void *dm_void, boolean *enable,
-+			    u8 *para4, u8 *para8) {
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+	dig_t->fw_dig_enable = *enable;
-+	para8[0] = dig_t->rx_gain_range_max;
-+	para8[1] = dig_t->rx_gain_range_min;
-+	para8[2] = dm->number_linked_client;
-+	para4[0] = (u8)DIG_LPS_MODE;
-+}
-+
-+void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used,
-+			 char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i = 0;
-+	u8 rate = 0x0;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[CRC32 Cnt] {rate_idx}\n");
-+	} else {
-+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+		rate = (u8)var1[0];
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{rate}={0x%x}", rate);
-+
-+		phydm_set_crc32_cnt2_rate(dm, rate);
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+void phydm_set_tdma_dig_timer(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 delta_time_us = dm->tdma_dig_timer_ms * 1000;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	u32 timeout = 0;
-+	u32 current_time_stamp, diff_time_stamp, regb0 = 0;
-+
-+	/*some IC has no FREERUN_CUNT register, like 92E*/
-+	if (dm->support_ic_type & ODM_RTL8197F)
-+		current_time_stamp = odm_get_bb_reg(dm, R_0x568, 0xffffffff);
-+	else
-+		return;
-+
-+	timeout = current_time_stamp + delta_time_us;
-+
-+	diff_time_stamp = current_time_stamp - dig_t->cur_timestamp;
-+	dig_t->pre_timestamp = dig_t->cur_timestamp;
-+	dig_t->cur_timestamp = current_time_stamp;
-+
-+	/*@HIMR0, it shows HW interrupt mask*/
-+	regb0 = odm_get_bb_reg(dm, R_0xb0, 0xffffffff);
-+
-+	PHYDM_DBG(dm, DBG_DIG, "Set next timer\n");
-+	PHYDM_DBG(dm, DBG_DIG,
-+		  "curr_time_stamp=%d, delta_time_us=%d\n",
-+		  current_time_stamp, delta_time_us);
-+	PHYDM_DBG(dm, DBG_DIG,
-+		  "timeout=%d, diff_time_stamp=%d, Reg0xb0 = 0x%x\n",
-+		  timeout, diff_time_stamp, regb0);
-+
-+	if (dm->support_ic_type & ODM_RTL8197F) /*REG_PS_TIMER2*/
-+		odm_set_bb_reg(dm, R_0x588, 0xffffffff, timeout);
-+	else {
-+		PHYDM_DBG(dm, DBG_DIG, "NOT 97F, NOT start\n");
-+		return;
-+	}
-+}
-+
-+void phydm_tdma_dig_timer_check(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d\n",
-+		  dig_t->tdma_dig_cnt, dig_t->pre_tdma_dig_cnt);
-+
-+	if (dig_t->tdma_dig_cnt == 0 ||
-+	    dig_t->tdma_dig_cnt == dig_t->pre_tdma_dig_cnt) {
-+		if (dm->support_ability & ODM_BB_DIG) {
-+#ifdef IS_USE_NEW_TDMA
-+			if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B |
-+			    ODM_RTL8812F | ODM_RTL8822B | ODM_RTL8192F |
-+			    ODM_RTL8821C | ODM_RTL8197G | ODM_RTL8822C |
-+			    ODM_RTL8723D| ODM_RTL8723F)) {
-+				PHYDM_DBG(dm, DBG_DIG,
-+					  "Check fail, Restart timer\n\n");
-+				phydm_false_alarm_counter_reset(dm);
-+				odm_set_timer(dm, &dm->tdma_dig_timer,
-+					      dm->tdma_dig_timer_ms);
-+			} else {
-+				PHYDM_DBG(dm, DBG_DIG,
-+					  "Not support TDMADIG, no SW timer\n");
-+			}
-+#else
-+			/*@if interrupt mask info is got.*/
-+			/*Reg0xb0 is no longer needed*/
-+#if 0
-+			/*regb0 = odm_get_bb_reg(dm, R_0xb0, bMaskDWord);*/
-+#endif
-+			PHYDM_DBG(dm, DBG_DIG,
-+				  "Check fail, Mask[0]=0x%x, restart timer\n",
-+				  *dm->interrupt_mask);
-+
-+			phydm_tdma_dig_add_interrupt_mask_handler(dm);
-+			phydm_enable_rx_related_interrupt_handler(dm);
-+			phydm_set_tdma_dig_timer(dm);
-+#endif
-+		}
-+	} else {
-+		PHYDM_DBG(dm, DBG_DIG, "Check pass, update pre_tdma_dig_cnt\n");
-+	}
-+
-+	dig_t->pre_tdma_dig_cnt = dig_t->tdma_dig_cnt;
-+}
-+
-+/*@different IC/team may use different timer for tdma-dig*/
-+void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (DM_ODM_SUPPORT_TYPE == (ODM_AP))
-+	if (dm->support_ic_type & ODM_RTL8197F) {
-+		/*@HAL_INT_TYPE_PSTIMEOUT2*/
-+		phydm_add_interrupt_mask_handler(dm, HAL_INT_TYPE_PSTIMEOUT2);
-+	}
-+#elif (DM_ODM_SUPPORT_TYPE == (ODM_WIN))
-+#elif (DM_ODM_SUPPORT_TYPE == (ODM_CE))
-+#endif
-+}
-+
-+/* will be triggered by HW timer*/
-+void phydm_tdma_dig(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
-+	u32 reg_c50 = 0;
-+
-+#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
-+	RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT)
-+#ifdef IS_USE_NEW_TDMA
-+	if (dm->support_ic_type &
-+	    (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8822B |
-+	     ODM_RTL8192F | ODM_RTL8821C)) {
-+		PHYDM_DBG(dm, DBG_DIG, "98F/14B/12F/22B/92F/21C, new tdma\n");
-+		return;
-+	}
-+#endif
-+#endif
-+	reg_c50 = odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
-+
-+	dig_t->tdma_dig_state =
-+		dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, regc50=0x%x\n",
-+		  dig_t->tdma_dig_state, reg_c50);
-+
-+	dig_t->tdma_dig_cnt++;
-+
-+	if (dig_t->tdma_dig_state == 1) {
-+		/* update IGI from tdma_dig_state == 0*/
-+		if (dig_t->cur_ig_value_tdma == 0)
-+			dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
-+
-+		odm_write_dig(dm, dig_t->cur_ig_value_tdma);
-+		phydm_tdma_false_alarm_counter_check(dm);
-+		PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, reset FA counter\n",
-+			  dig_t->tdma_dig_state);
-+
-+	} else if (dig_t->tdma_dig_state == 0) {
-+		/* update dig_t->CurIGValue,*/
-+		/* @it may different from dig_t->cur_ig_value_tdma */
-+		/* TDMA IGI upperbond @ L-state = */
-+		/* rf_ft_var.tdma_dig_low_upper_bond = 0x26 */
-+
-+		if (dig_t->cur_ig_value >= dm->tdma_dig_low_upper_bond)
-+			dig_t->low_ig_value = dm->tdma_dig_low_upper_bond;
-+		else
-+			dig_t->low_ig_value = dig_t->cur_ig_value;
-+
-+		odm_write_dig(dm, dig_t->low_ig_value);
-+		phydm_tdma_false_alarm_counter_check(dm);
-+	} else {
-+		phydm_tdma_false_alarm_counter_check(dm);
-+	}
-+}
-+
-+/*@============================================================*/
-+/*@FASLE ALARM CHECK*/
-+/*@============================================================*/
-+void phydm_tdma_false_alarm_counter_check(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
-+	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	boolean rssi_dump_en = 0;
-+	u32 timestamp = 0;
-+	u8 tdma_dig_state_number = 0;
-+	u32 start_th = 0;
-+
-+	if (dig_t->tdma_dig_state == 1)
-+		phydm_false_alarm_counter_reset(dm);
-+	/* Reset FalseAlarmCounterStatistics */
-+	/* @fa_acc_1sec_tsf = fa_acc_1sec_tsf, keep */
-+	/* @fa_end_tsf = fa_start_tsf = TSF */
-+	else {
-+		phydm_false_alarm_counter_statistics(dm);
-+		if (dm->support_ic_type & ODM_RTL8197F) /*REG_FREERUN_CNT*/
-+			timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
-+		else {
-+			PHYDM_DBG(dm, DBG_DIG, "NOT 97F! NOT start\n");
-+			return;
-+		}
-+		dig_t->fa_end_timestamp = timestamp;
-+		dig_t->fa_acc_1sec_timestamp +=
-+			(dig_t->fa_end_timestamp - dig_t->fa_start_timestamp);
-+
-+		/*prevent dumb*/
-+		if (dm->tdma_dig_state_number == 1)
-+			dm->tdma_dig_state_number = 2;
-+
-+		tdma_dig_state_number = dm->tdma_dig_state_number;
-+		dig_t->sec_factor =
-+			tdma_dig_state_number / (tdma_dig_state_number - 1);
-+
-+		/*@1sec = 1000000us*/
-+		if (dig_t->sec_factor)
-+			start_th = (u32)(1000000 / dig_t->sec_factor);
-+
-+		if (dig_t->fa_acc_1sec_timestamp >= start_th) {
-+			rssi_dump_en = 1;
-+			phydm_false_alarm_counter_acc(dm, rssi_dump_en);
-+			PHYDM_DBG(dm, DBG_DIG,
-+				  "sec_factor=%d, total FA=%d, is_linked=%d\n",
-+				  dig_t->sec_factor, falm_cnt_acc->cnt_all,
-+				  dm->is_linked);
-+
-+			phydm_noisy_detection(dm);
-+			#ifdef PHYDM_SUPPORT_CCKPD
-+			phydm_cck_pd_th(dm);
-+			#endif
-+			phydm_dig(dm);
-+			phydm_false_alarm_counter_acc_reset(dm);
-+
-+			/* Reset FalseAlarmCounterStatistics */
-+			/* @fa_end_tsf = fa_start_tsf = TSF, keep */
-+			/* @fa_acc_1sec_tsf = 0 */
-+			phydm_false_alarm_counter_reset(dm);
-+		} else {
-+			phydm_false_alarm_counter_acc(dm, rssi_dump_en);
-+		}
-+	}
-+}
-+
-+void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
-+	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+	falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
-+	falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
-+	falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
-+	falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
-+	falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
-+	falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
-+	falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
-+	falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
-+	falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
-+	falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
-+	falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
-+	falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
-+	falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
-+	falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
-+	falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
-+	falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
-+	falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
-+	falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
-+	falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
-+	falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
-+	falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
-+	falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
-+
-+	if (rssi_dump_en == 1) {
-+		falm_cnt_acc->cnt_all_1sec =
-+			falm_cnt_acc->cnt_all * dig_t->sec_factor;
-+		falm_cnt_acc->cnt_cca_all_1sec =
-+			falm_cnt_acc->cnt_cca_all * dig_t->sec_factor;
-+		falm_cnt_acc->cnt_cck_fail_1sec =
-+			falm_cnt_acc->cnt_cck_fail * dig_t->sec_factor;
-+	}
-+}
-+
-+void phydm_false_alarm_counter_acc_reset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
-+
-+#ifdef IS_USE_NEW_TDMA
-+	struct phydm_fa_acc_struct *falm_cnt_acc_low = NULL;
-+	u32 tmp_cca_1sec = 0;
-+	u32 tmp_fa_1sec = 0;
-+
-+	/*@clear L-fa_acc struct*/
-+	falm_cnt_acc_low = &dm->false_alm_cnt_acc_low;
-+	tmp_cca_1sec = falm_cnt_acc_low->cnt_cca_all_1sec;
-+	tmp_fa_1sec = falm_cnt_acc_low->cnt_all_1sec;
-+	odm_memory_set(dm, falm_cnt_acc_low, 0, sizeof(dm->false_alm_cnt_acc));
-+	falm_cnt_acc_low->cnt_cca_all_1sec = tmp_cca_1sec;
-+	falm_cnt_acc_low->cnt_all_1sec = tmp_fa_1sec;
-+
-+	/*@clear H-fa_acc struct*/
-+	falm_cnt_acc = &dm->false_alm_cnt_acc;
-+	tmp_cca_1sec = falm_cnt_acc->cnt_cca_all_1sec;
-+	tmp_fa_1sec = falm_cnt_acc->cnt_all_1sec;
-+	odm_memory_set(dm, falm_cnt_acc, 0, sizeof(dm->false_alm_cnt_acc));
-+	falm_cnt_acc->cnt_cca_all_1sec = tmp_cca_1sec;
-+	falm_cnt_acc->cnt_all_1sec = tmp_fa_1sec;
-+#else
-+	falm_cnt_acc = &dm->false_alm_cnt_acc;
-+	/* @Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump */
-+	/* @do NOT need to be reset */
-+	odm_memory_set(dm, falm_cnt_acc, 0, sizeof(falm_cnt_acc));
-+#endif
-+}
-+
-+void phydm_false_alarm_counter_reset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *falm_cnt;
-+	struct phydm_dig_struct *dig_t;
-+	u32 timestamp;
-+
-+	falm_cnt = &dm->false_alm_cnt;
-+	dig_t = &dm->dm_dig_table;
-+
-+	memset(falm_cnt, 0, sizeof(dm->false_alm_cnt));
-+	phydm_false_alarm_counter_reg_reset(dm);
-+
-+#ifdef IS_USE_NEW_TDMA
-+	return;
-+#endif
-+	if (dig_t->tdma_dig_state != 1)
-+		dig_t->fa_acc_1sec_timestamp = 0;
-+	else
-+		dig_t->fa_acc_1sec_timestamp = dig_t->fa_acc_1sec_timestamp;
-+
-+	/*REG_FREERUN_CNT*/
-+	timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
-+	dig_t->fa_start_timestamp = timestamp;
-+	dig_t->fa_end_timestamp = timestamp;
-+}
-+
-+void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	switch (type) {
-+	case ENABLE_TDMA:
-+		dm->original_dig_restore = !((boolean)input);
-+		break;
-+	case MODE_DECISION:
-+		if (input == (u8)MODE_PERFORMANCE)
-+			dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES + 2;
-+		else if (input == (u8)MODE_COVERAGE)
-+			dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
-+		else
-+			dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES;
-+		break;
-+	}
-+}
-+
-+#ifdef IS_USE_NEW_TDMA
-+#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
-+static void pre_phydm_tdma_dig_cbk(unsigned long task_dm)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)task_dm;
-+	struct rtl8192cd_priv *priv = dm->priv;
-+	struct priv_shared_info *pshare = priv->pshare;
-+
-+	if (!(priv->drv_state & DRV_STATE_OPEN))
-+		return;
-+
-+	if (pshare->bDriverStopped || pshare->bSurpriseRemoved) {
-+		printk("[%s] bDriverStopped(%d) OR bSurpriseRemoved(%d)\n",
-+		         __FUNCTION__, pshare->bDriverStopped,
-+		         pshare->bSurpriseRemoved);
-+		return;
-+	}
-+
-+	rtw_enqueue_timer_event(priv, &pshare->tdma_dig_event,
-+			           ENQUEUE_TO_TAIL);
-+}
-+
-+void phydm_tdma_dig_timers_usb(void *dm_void, u8 state)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+	if (state == INIT_TDMA_DIG_TIMMER) {
-+		struct rtl8192cd_priv *priv = dm->priv;
-+
-+		init_timer(&dm->tdma_dig_timer);
-+		dm->tdma_dig_timer.data = (unsigned long)dm;
-+		dm->tdma_dig_timer.function = pre_phydm_tdma_dig_cbk;
-+		INIT_TIMER_EVENT_ENTRY(&priv->pshare->tdma_dig_event,
-+					    phydm_tdma_dig_cbk,
-+					   (unsigned long)dm);
-+	} else if (state == CANCEL_TDMA_DIG_TIMMER) {
-+		odm_cancel_timer(dm, &dm->tdma_dig_timer);
-+	} else if (state == RELEASE_TDMA_DIG_TIMMER) {
-+		odm_release_timer(dm, &dm->tdma_dig_timer);
-+	}
-+}
-+#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
-+
-+void phydm_tdma_dig_timers(void *dm_void, u8 state)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
-+	struct rtl8192cd_priv *priv = dm->priv;
-+
-+	if (priv->hci_type == RTL_HCI_USB) {
-+		phydm_tdma_dig_timers_usb(dm_void, state);
-+		return;
-+	}
-+#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
-+
-+	if (state == INIT_TDMA_DIG_TIMMER)
-+		odm_initialize_timer(dm, &dm->tdma_dig_timer,
-+				     (void *)phydm_tdma_dig_cbk,
-+				     NULL, "phydm_tdma_dig_timer");
-+	else if (state == CANCEL_TDMA_DIG_TIMMER)
-+		odm_cancel_timer(dm, &dm->tdma_dig_timer);
-+	else if (state == RELEASE_TDMA_DIG_TIMMER)
-+		odm_release_timer(dm, &dm->tdma_dig_timer);
-+}
-+
-+u8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max,
-+		     u8 *rx_gain_min, boolean is_dfs_band)
-+{
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	u8 step[3] = {0};
-+	u8 cur_igi = igi;
-+
-+	if (dm->is_linked) {
-+		if (dm->pre_rssi_min <= dm->rssi_min) {
-+			PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
-+			step[0] = 2;
-+			step[1] = 1;
-+			step[2] = 2;
-+		} else {
-+			step[0] = 4;
-+			step[1] = 2;
-+			step[2] = 2;
-+		}
-+	} else {
-+		step[0] = 2;
-+		step[1] = 1;
-+		step[2] = 2;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
-+		  step[0]);
-+
-+	if (dm->first_connect) {
-+		if (is_dfs_band) {
-+			if (dm->rssi_min > DIG_MAX_DFS)
-+				igi = DIG_MAX_DFS;
-+			else
-+				igi = dm->rssi_min;
-+			PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
-+				  *rx_gain_max);
-+		} else {
-+			igi = *rx_gain_min;
-+		}
-+
-+		#if 0
-+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+		#if (RTL8812A_SUPPORT)
-+		if (dm->support_ic_type == ODM_RTL8812)
-+			odm_config_bb_with_header_file(dm,
-+						       CONFIG_BB_AGC_TAB_DIFF);
-+		#endif
-+		#endif
-+		#endif
-+		PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
-+	} else {
-+		/* @2 Before link */
-+		PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
-+
-+		if (dm->first_disconnect) {
-+			igi = dig_t->dm_dig_min;
-+			PHYDM_DBG(dm, DBG_DIG,
-+				  "First disconnect:foce IGI to lower bound\n");
-+		} else {
-+			PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
-+				  igi, fa_cnt);
-+
-+			igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
-+		}
-+	}
-+	/*@Check IGI by dyn-upper/lower bound */
-+	if (igi < *rx_gain_min)
-+		igi = *rx_gain_min;
-+
-+	if (igi > *rx_gain_max)
-+		igi = *rx_gain_max;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n",
-+		  fa_cnt, cur_igi, igi);
-+
-+	return igi;
-+}
-+
-+void phydm_write_tdma_dig(void *dm_void, u8 new_igi)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
-+#if 0
-+	/* @1 Check IGI by upper bound */
-+	if (adaptivity->igi_lmt_en &&
-+	    new_igi > adaptivity->adapt_igi_up && dm->is_linked) {
-+		new_igi = adaptivity->adapt_igi_up;
-+
-+		PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n",
-+			  new_igi);
-+	}
-+#endif
-+	phydm_write_dig_reg(dm, new_igi);
-+
-+	PHYDM_DBG(dm, DBG_DIG, "New %s-IGI=((0x%x))\n",
-+		  (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE) ? "L" : "H",
-+		  new_igi);
-+}
-+
-+void phydm_tdma_dig_new(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+	if (phydm_dig_abort(dm) || dm->original_dig_restore)
-+		return;
-+	/*@
-+	 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
-+	 *	  dig_t->tdma_dig_state);
-+	 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
-+	 *	  dig_t->cur_ig_value_tdma,
-+	 *	  dig_t->low_ig_value);
-+	 */
-+	phydm_tdma_fa_cnt_chk(dm);
-+
-+	/*@prevent dumb*/
-+	if (dm->tdma_dig_state_number < 2)
-+		dm->tdma_dig_state_number = 2;
-+
-+	/*@update state*/
-+	dig_t->tdma_dig_cnt++;
-+	dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
-+
-+	/*@
-+	 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
-+	 *	  dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
-+	 */
-+
-+	if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
-+		odm_write_dig(dm, dig_t->low_ig_value);
-+	else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
-+		odm_write_dig(dm, dig_t->cur_ig_value_tdma);
-+
-+	odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
-+}
-+
-+/*@callback function triggered by SW timer*/
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void phydm_tdma_dig_cbk(struct phydm_timer_list *timer)
-+{
-+	void *adapter = (void *)timer->Adapter;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrcs;
-+
-+	#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+	#if USE_WORKITEM
-+	odm_schedule_work_item(&dm->phydm_tdma_dig_workitem);
-+	#else
-+	phydm_tdma_dig_new(dm);
-+	#endif
-+	#else
-+	odm_schedule_work_item(&dm->phydm_tdma_dig_workitem);
-+	#endif
-+}
-+
-+void phydm_tdma_dig_workitem_callback(void *context)
-+{
-+	void *adapter = (void *)context;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+
-+	phydm_tdma_dig_new(dm);
-+}
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+void phydm_tdma_dig_cbk(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	void *padapter = dm->adapter;
-+
-+	if (dm->support_interface == ODM_ITRF_PCIE)
-+		phydm_tdma_dig_workitem_callback(dm);
-+	/* @Can't do I/O in timer callback*/
-+	else
-+		phydm_run_in_thread_cmd(dm, phydm_tdma_dig_workitem_callback,
-+					dm);
-+}
-+
-+void phydm_tdma_dig_workitem_callback(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+	if (phydm_dig_abort(dm) || (dm->original_dig_restore))
-+		return;
-+	/*@
-+	 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
-+	 *	  dig_t->tdma_dig_state);
-+	 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
-+	 *	  dig_t->cur_ig_value_tdma,
-+	 *	  dig_t->low_ig_value);
-+	 */
-+	phydm_tdma_fa_cnt_chk(dm);
-+
-+	/*@prevent dumb*/
-+	if (dm->tdma_dig_state_number < 2)
-+		dm->tdma_dig_state_number = 2;
-+
-+	/*@update state*/
-+	dig_t->tdma_dig_cnt++;
-+	dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
-+
-+	/*@
-+	 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
-+	 *	  dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
-+	 */
-+
-+	if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
-+		odm_write_dig(dm, dig_t->low_ig_value);
-+	else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
-+		odm_write_dig(dm, dig_t->cur_ig_value_tdma);
-+
-+	odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
-+}
-+#else
-+void phydm_tdma_dig_cbk(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+
-+	if (phydm_dig_abort(dm) || dm->original_dig_restore)
-+		return;
-+	/*@
-+	 *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
-+	 *	  dig_t->tdma_dig_state);
-+	 *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
-+	 *	  dig_t->cur_ig_value_tdma,
-+	 *	  dig_t->low_ig_value);
-+	 */
-+	phydm_tdma_fa_cnt_chk(dm);
-+
-+	/*@prevent dumb*/
-+	if (dm->tdma_dig_state_number < 2)
-+		dm->tdma_dig_state_number = 2;
-+
-+	/*@update state*/
-+	dig_t->tdma_dig_cnt++;
-+	dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
-+
-+	/*@
-+	 *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
-+	 *	  dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
-+	 */
-+
-+	if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
-+		phydm_write_tdma_dig(dm, dig_t->low_ig_value);
-+	else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
-+		phydm_write_tdma_dig(dm, dig_t->cur_ig_value_tdma);
-+
-+	odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
-+}
-+#endif
-+/*@============================================================*/
-+/*@FASLE ALARM CHECK*/
-+/*@============================================================*/
-+void phydm_tdma_fa_cnt_chk(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
-+	struct phydm_fa_acc_struct *fa_t_acc = &dm->false_alm_cnt_acc;
-+	struct phydm_fa_acc_struct *fa_t_acc_low = &dm->false_alm_cnt_acc_low;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	boolean tdma_dig_block_1sec_flag = false;
-+	u32 timestamp = 0;
-+	u8 states_per_block = dm->tdma_dig_state_number;
-+	u8 cur_tdma_dig_state = 0;
-+	u32 start_th = 0;
-+	u8 state_diff = 0;
-+	u32 tdma_dig_block_period_ms = 0;
-+	u32 tdma_dig_block_cnt_thd = 0;
-+	u32 timestamp_diff = 0;
-+
-+	/*@calculate duration of a tdma block*/
-+	tdma_dig_block_period_ms = dm->tdma_dig_timer_ms * states_per_block;
-+
-+	/*@
-+	 *caution!ONE_SEC_MS must be divisible by tdma_dig_block_period_ms,
-+	 *or FA will be fewer.
-+	 */
-+	tdma_dig_block_cnt_thd = ONE_SEC_MS / tdma_dig_block_period_ms;
-+
-+	/*@tdma_dig_state == 0, collect H-state FA, else, collect L-state FA*/
-+	if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
-+		cur_tdma_dig_state = TDMA_DIG_LOW_STATE;
-+	else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
-+		cur_tdma_dig_state = TDMA_DIG_HIGH_STATE;
-+	/*@
-+	 *PHYDM_DBG(dm, DBG_DIG, "in state %d, dig count %d\n",
-+	 *	  cur_tdma_dig_state, dig_t->tdma_dig_cnt);
-+	 */
-+	if (cur_tdma_dig_state == 0) {
-+		/*@L-state indicates next block*/
-+		dig_t->tdma_dig_block_cnt++;
-+
-+		/*@1sec dump check*/
-+		if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
-+			tdma_dig_block_1sec_flag = true;
-+
-+		/*@
-+		 *PHYDM_DBG(dm, DBG_DIG,"[L-state] tdma_dig_block_cnt=%d\n",
-+		 *	  dig_t->tdma_dig_block_cnt);
-+		 */
-+
-+		/*@collect FA till this block end*/
-+		phydm_false_alarm_counter_statistics(dm);
-+		phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag,
-+				 cur_tdma_dig_state);
-+		/*@1s L-FA collect end*/
-+
-+		/*@1sec dump reached*/
-+		if (tdma_dig_block_1sec_flag) {
-+			/*@L-DIG*/
-+			phydm_noisy_detection(dm);
-+			#ifdef PHYDM_SUPPORT_CCKPD
-+			phydm_cck_pd_th(dm);
-+			#endif
-+			PHYDM_DBG(dm, DBG_DIG, "run tdma L-state dig ====>\n");
-+			phydm_tdma_low_dig(dm);
-+			PHYDM_DBG(dm, DBG_DIG, "\n\n");
-+		}
-+	} else if (cur_tdma_dig_state == 1) {
-+		/*@1sec dump check*/
-+		if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
-+			tdma_dig_block_1sec_flag = true;
-+
-+		/*@
-+		 *PHYDM_DBG(dm, DBG_DIG,"[H-state] tdma_dig_block_cnt=%d\n",
-+		 *	  dig_t->tdma_dig_block_cnt);
-+		 */
-+
-+		/*@collect FA till this block end*/
-+		phydm_false_alarm_counter_statistics(dm);
-+		phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag,
-+				 cur_tdma_dig_state);
-+		/*@1s H-FA collect end*/
-+
-+		/*@1sec dump reached*/
-+		state_diff = dm->tdma_dig_state_number - dig_t->tdma_dig_state;
-+		if (tdma_dig_block_1sec_flag && state_diff == 1) {
-+			/*@H-DIG*/
-+			phydm_noisy_detection(dm);
-+			#ifdef PHYDM_SUPPORT_CCKPD
-+			phydm_cck_pd_th(dm);
-+			#endif
-+			PHYDM_DBG(dm, DBG_DIG, "run tdma H-state dig ====>\n");
-+			phydm_tdma_high_dig(dm);
-+			PHYDM_DBG(dm, DBG_DIG, "\n\n");
-+			PHYDM_DBG(dm, DBG_DIG, "1 sec reached, is_linked=%d\n",
-+				  dm->is_linked);
-+			PHYDM_DBG(dm, DBG_DIG, "1 sec L-CCA=%d, L-FA=%d\n",
-+				  fa_t_acc_low->cnt_cca_all_1sec,
-+				  fa_t_acc_low->cnt_all_1sec);
-+			PHYDM_DBG(dm, DBG_DIG, "1 sec H-CCA=%d, H-FA=%d\n",
-+				  fa_t_acc->cnt_cca_all_1sec,
-+				  fa_t_acc->cnt_all_1sec);
-+			PHYDM_DBG(dm, DBG_DIG,
-+				  "1 sec TOTAL-CCA=%d, TOTAL-FA=%d\n\n",
-+				  fa_t_acc->cnt_cca_all +
-+				  fa_t_acc_low->cnt_cca_all,
-+				  fa_t_acc->cnt_all + fa_t_acc_low->cnt_all);
-+
-+			/*@Reset AccFalseAlarmCounterStatistics */
-+			phydm_false_alarm_counter_acc_reset(dm);
-+			dig_t->tdma_dig_block_cnt = 0;
-+		}
-+	}
-+	/*@Reset FalseAlarmCounterStatistics */
-+	phydm_false_alarm_counter_reset(dm);
-+}
-+
-+void phydm_tdma_low_dig(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
-+	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc_low;
-+#ifdef CFG_DIG_DAMPING_CHK
-+	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
-+#endif
-+	u8 igi = dig_t->cur_ig_value;
-+	u8 new_igi = 0x20;
-+	u8 tdma_l_igi = dig_t->low_ig_value;
-+	u8 tdma_l_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE];
-+	u8 tdma_l_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE];
-+	u32 fa_cnt = falm_cnt->cnt_all;
-+	boolean dfs_mode_en = false, is_performance = true;
-+	u8 rssi_min = dm->rssi_min;
-+	u8 igi_upper_rssi_min = 0;
-+	u8 offset = 15;
-+
-+	if (!(dm->original_dig_restore)) {
-+		if (tdma_l_igi == 0)
-+			tdma_l_igi = igi;
-+
-+		fa_cnt = falm_cnt_acc->cnt_all_1sec;
-+	}
-+
-+	if (phydm_dig_abort(dm)) {
-+		dig_t->low_ig_value = phydm_get_igi(dm, BB_PATH_A);
-+		return;
-+	}
-+
-+	/*@Mode Decision*/
-+	dfs_mode_en = false;
-+	is_performance = true;
-+
-+	/* @Abs Boundary Decision*/
-+	dig_t->dm_dig_max = DIG_MAX_COVERAGR; //0x26
-+	dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; //0x20
-+	dig_t->dig_max_of_min = DIG_MAX_OF_MIN_COVERAGE; //0x22
-+
-+	if (dm->is_dfs_band) {
-+		if (*dm->band_width == CHANNEL_WIDTH_20){
-+			if (dm->support_ic_type &
-+				(ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
-+				if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
-+					dig_t->dm_dig_min = DIG_MIN_DFS + 2;
-+				else
-+					dig_t->dm_dig_min = DIG_MIN_DFS;
-+			}
-+			else
-+				dig_t->dm_dig_min = DIG_MIN_DFS;
-+		}
-+		else
-+			dig_t->dm_dig_min = DIG_MIN_DFS;
-+
-+	} else {
-+		#if 0
-+		if (dm->support_ic_type &
-+		    (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
-+			dig_t->dm_dig_min = 0x1c;
-+		else if (dm->support_ic_type & ODM_RTL8197F)
-+			dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
-+		#endif
-+	}
-+
-+	PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
-+		  dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
-+
-+	/* @Dyn Boundary by RSSI*/
-+	if (!dm->is_linked) {
-+		/*@if no link, always stay at lower bound*/
-+		tdma_l_dym_max = 0x26;
-+		tdma_l_dym_min = dig_t->dm_dig_min;
-+
-+		PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
-+			  tdma_l_dym_max, tdma_l_dym_min);
-+	} else {
-+		PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
-+			  dm->rssi_min, offset);
-+
-+		/* @DIG lower bound in L-state*/
-+		tdma_l_dym_min = dig_t->dm_dig_min;
-+		if (dm->is_dfs_band)
-+			tdma_l_dym_min = DIG_MIN_DFS;
-+		/*@
-+		 *#ifdef CFG_DIG_DAMPING_CHK
-+		 *@Limit Dyn min by damping
-+		 *if (dig_t->dig_dl_en &&
-+		 *   dig_rc->damping_limit_en &&
-+		 *   tdma_l_dym_min < dig_rc->damping_limit_val) {
-+		 *	PHYDM_DBG(dm, DBG_DIG,
-+		 *		  "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
-+		 *		  tdma_l_dym_min, dig_rc->damping_limit_val);
-+		 *
-+		 *	tdma_l_dym_min = dig_rc->damping_limit_val;
-+		 *}
-+		 *#endif
-+		 */
-+
-+		/*@DIG upper bound in L-state*/
-+		igi_upper_rssi_min = rssi_min + offset;
-+		if (igi_upper_rssi_min > dig_t->dm_dig_max)
-+			tdma_l_dym_max = dig_t->dm_dig_max;
-+		else if (igi_upper_rssi_min < dig_t->dm_dig_min)
-+			tdma_l_dym_max = dig_t->dm_dig_min;
-+		else
-+			tdma_l_dym_max = igi_upper_rssi_min;
-+
-+		/* @1 Force Lower Bound for AntDiv */
-+		/*@
-+		 *if (!dm->is_one_entry_only &&
-+		 *(dm->support_ability & ODM_BB_ANT_DIV) &&
-+		 *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
-+		 *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
-+		 *if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
-+		 *	dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
-+		 *else
-+		 *	dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
-+		 *
-+		 *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
-+		 *	  dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
-+		 *}
-+		 */
-+
-+		PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
-+			  tdma_l_dym_max, tdma_l_dym_min);
-+	}
-+
-+	/*@Abnormal Case Check*/
-+	/*@Abnormal lower bound case*/
-+	if (tdma_l_dym_min > tdma_l_dym_max)
-+		tdma_l_dym_min = tdma_l_dym_max;
-+
-+	PHYDM_DBG(dm, DBG_DIG,
-+		  "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
-+		  tdma_l_dym_max, tdma_l_dym_min);
-+
-+	/*@False Alarm Threshold Decision*/
-+	phydm_fa_threshold_check(dm, dfs_mode_en);
-+
-+	/*@Adjust Initial Gain by False Alarm*/
-+	/*Select new IGI by FA */
-+	if (!(dm->original_dig_restore)) {
-+		tdma_l_igi = get_new_igi_bound(dm, tdma_l_igi, fa_cnt,
-+					       &tdma_l_dym_max,
-+					       &tdma_l_dym_min,
-+					       dfs_mode_en);
-+	} else {
-+		new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
-+	}
-+
-+	/*Update status*/
-+	if (!(dm->original_dig_restore)) {
-+		if (dig_t->tdma_force_l_igi == 0xff)
-+			dig_t->low_ig_value = tdma_l_igi;
-+		else
-+			dig_t->low_ig_value = dig_t->tdma_force_l_igi;
-+		dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = tdma_l_dym_min;
-+		dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = tdma_l_dym_max;
-+#if 0
-+		/*odm_write_dig(dm, tdma_l_igi);*/
-+#endif
-+	} else {
-+		odm_write_dig(dm, new_igi);
-+	}
-+}
-+
-+void phydm_tdma_high_dig(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
-+	struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
-+#ifdef CFG_DIG_DAMPING_CHK
-+	struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
-+#endif
-+	u8 igi = dig_t->cur_ig_value;
-+	u8 new_igi = 0x20;
-+	u8 tdma_h_igi = dig_t->cur_ig_value_tdma;
-+	u8 tdma_h_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE];
-+	u8 tdma_h_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE];
-+	u32 fa_cnt = falm_cnt->cnt_all;
-+	boolean dfs_mode_en = false, is_performance = true;
-+	u8 rssi_min = dm->rssi_min;
-+	u8 igi_upper_rssi_min = 0;
-+	u8 offset = 15;
-+
-+	if (!(dm->original_dig_restore)) {
-+		if (tdma_h_igi == 0)
-+			tdma_h_igi = igi;
-+
-+		fa_cnt = falm_cnt_acc->cnt_all_1sec;
-+	}
-+
-+	if (phydm_dig_abort(dm)) {
-+		dig_t->cur_ig_value_tdma = phydm_get_igi(dm, BB_PATH_A);
-+		return;
-+	}
-+
-+	/*@Mode Decision*/
-+	dfs_mode_en = false;
-+	is_performance = true;
-+
-+	/*@Abs Boundary Decision*/
-+	dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; // 0x2a
-+
-+	if (!dm->is_linked) {
-+		dig_t->dm_dig_max = DIG_MAX_COVERAGR;
-+		dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; // 0x20
-+	} else if (dm->is_dfs_band) {
-+		if (*dm->band_width == CHANNEL_WIDTH_20){
-+			if (dm->support_ic_type &
-+				(ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){
-+				if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1)
-+					dig_t->dm_dig_min = DIG_MIN_DFS + 2;
-+				else
-+					dig_t->dm_dig_min = DIG_MIN_DFS;
-+			}
-+			else
-+				dig_t->dm_dig_min = DIG_MIN_DFS;
-+		}
-+		else
-+			dig_t->dm_dig_min = DIG_MIN_DFS;
-+
-+		dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
-+		dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
-+	} else {
-+		if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
-+		/*service > 2 devices*/
-+			dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
-+			#if (DIG_HW == 1)
-+			dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
-+			#else
-+			dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
-+			#endif
-+		} else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
-+		/*service 1 devices*/
-+			dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
-+			dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
-+		}
-+
-+		#if 0
-+		if (dm->support_ic_type &
-+		    (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
-+			dig_t->dm_dig_min = 0x1c;
-+		else if (dm->support_ic_type & ODM_RTL8197F)
-+			dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
-+		else
-+		#endif
-+			dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
-+	}
-+	PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
-+		  dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
-+
-+	/*@Dyn Boundary by RSSI*/
-+	if (!dm->is_linked) {
-+		/*@if no link, always stay at lower bound*/
-+		tdma_h_dym_max = dig_t->dig_max_of_min;
-+		tdma_h_dym_min = dig_t->dm_dig_min;
-+
-+		PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
-+			  tdma_h_dym_max, tdma_h_dym_min);
-+	} else {
-+		PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
-+			  dm->rssi_min, offset);
-+
-+		/* @DIG lower bound in H-state*/
-+		if (dm->is_dfs_band)
-+			tdma_h_dym_min = DIG_MIN_DFS;
-+		else if (rssi_min < dig_t->dm_dig_min)
-+			tdma_h_dym_min = dig_t->dm_dig_min;
-+		else
-+			tdma_h_dym_min = rssi_min; // turbo not considered yet
-+
-+#ifdef CFG_DIG_DAMPING_CHK
-+		/*@Limit Dyn min by damping*/
-+		if (dig_t->dig_dl_en &&
-+		    dig_rc->damping_limit_en &&
-+		    tdma_h_dym_min < dig_rc->damping_limit_val) {
-+			PHYDM_DBG(dm, DBG_DIG,
-+				  "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
-+				  tdma_h_dym_min, dig_rc->damping_limit_val);
-+
-+			tdma_h_dym_min = dig_rc->damping_limit_val;
-+		}
-+#endif
-+
-+		/*@DIG upper bound in H-state*/
-+		igi_upper_rssi_min = rssi_min + offset;
-+		if (igi_upper_rssi_min > dig_t->dm_dig_max)
-+			tdma_h_dym_max = dig_t->dm_dig_max;
-+		else
-+			tdma_h_dym_max = igi_upper_rssi_min;
-+
-+		/* @1 Force Lower Bound for AntDiv */
-+		/*@
-+		 *if (!dm->is_one_entry_only &&
-+		 *(dm->support_ability & ODM_BB_ANT_DIV) &&
-+		 *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
-+		 *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
-+		 *	if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
-+		 *	dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
-+		 *	else
-+		 *	dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
-+		 */
-+		/*@
-+		 *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
-+		 *	  dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
-+		 *}
-+		 */
-+		PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
-+			  tdma_h_dym_max, tdma_h_dym_min);
-+	}
-+
-+	/*@Abnormal Case Check*/
-+	/*@Abnormal low higher bound case*/
-+	if (tdma_h_dym_max < dig_t->dm_dig_min)
-+		tdma_h_dym_max = dig_t->dm_dig_min;
-+	/*@Abnormal lower bound case*/
-+	if (tdma_h_dym_min > tdma_h_dym_max)
-+		tdma_h_dym_min = tdma_h_dym_max;
-+
-+	PHYDM_DBG(dm, DBG_DIG, "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
-+		  tdma_h_dym_max, tdma_h_dym_min);
-+
-+	/*@False Alarm Threshold Decision*/
-+	phydm_fa_threshold_check(dm, dfs_mode_en);
-+
-+	/*@Adjust Initial Gain by False Alarm*/
-+	/*Select new IGI by FA */
-+	if (!(dm->original_dig_restore)) {
-+		tdma_h_igi = get_new_igi_bound(dm, tdma_h_igi, fa_cnt,
-+					       &tdma_h_dym_max,
-+					       &tdma_h_dym_min,
-+					       dfs_mode_en);
-+	} else {
-+		new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
-+	}
-+
-+	/*Update status*/
-+	if (!(dm->original_dig_restore)) {
-+		if (dig_t->tdma_force_h_igi == 0xff)
-+			dig_t->cur_ig_value_tdma = tdma_h_igi;
-+		else
-+			dig_t->cur_ig_value_tdma = dig_t->tdma_force_h_igi;
-+		dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = tdma_h_dym_min;
-+		dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = tdma_h_dym_max;
-+#if 0
-+		/*odm_write_dig(dm, tdma_h_igi);*/
-+#endif
-+	} else {
-+		odm_write_dig(dm, new_igi);
-+	}
-+}
-+
-+void phydm_fa_cnt_acc(void *dm_void, boolean tdma_dig_block_1sec_flag,
-+		      u8 cur_tdma_dig_state)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
-+	struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	u8 factor_num = 0;
-+	u8 factor_denum = 1;
-+	u8 total_state_number = 0;
-+
-+	if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE)
-+		falm_cnt_acc = &dm->false_alm_cnt_acc_low;
-+	else if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE)
-+
-+		falm_cnt_acc = &dm->false_alm_cnt_acc;
-+	/*@
-+	 *PHYDM_DBG(dm, DBG_DIG,
-+	 *	  "[%s] ==> dig_state=%d, one_sec=%d\n", __func__,
-+	 *	  cur_tdma_dig_state, tdma_dig_block_1sec_flag);
-+	 */
-+	falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
-+	falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
-+	falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
-+	falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
-+	falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
-+	falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
-+	falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
-+	falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
-+	falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
-+	falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
-+	falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
-+	falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
-+	falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
-+	falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
-+	falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
-+	falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
-+	falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
-+	falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
-+	falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
-+	falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
-+	falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
-+	falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
-+
-+	/*@
-+	 *PHYDM_DBG(dm, DBG_DIG,
-+	 *	"[CCA Cnt]     {CCK, OFDM, Total} = {%d, %d, %d}\n",
-+	 *	falm_cnt->cnt_cck_cca,
-+	 *	falm_cnt->cnt_ofdm_cca,
-+	 *	falm_cnt->cnt_cca_all);
-+	 *PHYDM_DBG(dm, DBG_DIG,
-+	 *	"[FA Cnt]      {CCK, OFDM, Total} = {%d, %d, %d}\n",
-+	 *	falm_cnt->cnt_cck_fail,
-+	 *	falm_cnt->cnt_ofdm_fail,
-+	 *	falm_cnt->cnt_all);
-+	 */
-+	if (tdma_dig_block_1sec_flag) {
-+		total_state_number = dm->tdma_dig_state_number;
-+
-+		if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE) {
-+			factor_num = total_state_number;
-+			factor_denum = total_state_number - 1;
-+		} else if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE) {
-+			factor_num = total_state_number;
-+			factor_denum = 1;
-+		}
-+
-+		falm_cnt_acc->cnt_all_1sec =
-+			falm_cnt_acc->cnt_all * factor_num / factor_denum;
-+		falm_cnt_acc->cnt_cca_all_1sec =
-+			falm_cnt_acc->cnt_cca_all * factor_num / factor_denum;
-+		falm_cnt_acc->cnt_cck_fail_1sec =
-+			falm_cnt_acc->cnt_cck_fail * factor_num / factor_denum;
-+
-+		PHYDM_DBG(dm, DBG_DIG,
-+			  "[ACC CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
-+			  falm_cnt_acc->cnt_cck_cca,
-+			  falm_cnt_acc->cnt_ofdm_cca,
-+			  falm_cnt_acc->cnt_cca_all);
-+		PHYDM_DBG(dm, DBG_DIG,
-+			  "[ACC FA Cnt]  {CCK, OFDM, Total} = {%d, %d, %d}\n\n",
-+			  falm_cnt_acc->cnt_cck_fail,
-+			  falm_cnt_acc->cnt_ofdm_fail,
-+			  falm_cnt_acc->cnt_all);
-+
-+	}
-+}
-+#endif /*@#ifdef IS_USE_NEW_TDMA*/
-+#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
-+
-+void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
-+		     u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i = 0;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{0} {en} fa_th[0] fa_th[1] fa_th[2]\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{1} {Damping Limit en}\n");
-+		#ifdef PHYDM_TDMA_DIG_SUPPORT
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{2} {original_dig_restore = %d}\n",
-+			 dm->original_dig_restore);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{3} {tdma_dig_timer_ms = %d}\n",
-+			 dm->tdma_dig_timer_ms);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{4} {tdma_dig_state_number = %d}\n",
-+			 dm->tdma_dig_state_number);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{5} {0:L-state,1:H-state} {force IGI} (L,H)=(%2x,%2x)\n",
-+			 dig_t->tdma_force_l_igi, dig_t->tdma_force_h_igi);
-+		#endif
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{6} {fw_dig_en}\n");
-+	} else {
-+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+
-+		for (i = 1; i < 10; i++)
-+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
-+
-+		if (var1[0] == 0) {
-+			if (var1[1] == 1) {
-+				dig_t->is_dbg_fa_th = true;
-+				dig_t->fa_th[0] = (u16)var1[2];
-+				dig_t->fa_th[1] = (u16)var1[3];
-+				dig_t->fa_th[2] = (u16)var1[4];
-+
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used,
-+					 "Set DIG fa_th[0:2]= {%d, %d, %d}\n",
-+					 dig_t->fa_th[0], dig_t->fa_th[1],
-+					 dig_t->fa_th[2]);
-+			} else {
-+				dig_t->is_dbg_fa_th = false;
-+			}
-+		#ifdef PHYDM_TDMA_DIG_SUPPORT
-+		} else if (var1[0] == 2) {
-+			dm->original_dig_restore = (u8)var1[1];
-+			if (dm->original_dig_restore == 1) {
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used, "Disable TDMA-DIG\n");
-+			} else {
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used, "Enable TDMA-DIG\n");
-+			}
-+		} else if (var1[0] == 3) {
-+			dm->tdma_dig_timer_ms = (u8)var1[1];
-+			PDM_SNPF(out_len, used, output + used,
-+				 out_len - used, "tdma_dig_timer_ms = %d\n",
-+				 dm->tdma_dig_timer_ms);
-+		} else if (var1[0] == 4) {
-+			dm->tdma_dig_state_number = (u8)var1[1];
-+			PDM_SNPF(out_len, used, output + used,
-+				 out_len - used, "tdma_dig_state_number = %d\n",
-+				 dm->tdma_dig_state_number);
-+		} else if (var1[0] == 5) {
-+			PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
-+			if (var1[1] == 0) {
-+				dig_t->tdma_force_l_igi = (u8)var1[2];
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used,
-+					 "force L-state IGI = %2x\n",
-+					 dig_t->tdma_force_l_igi);
-+			} else if (var1[1] == 1) {
-+				dig_t->tdma_force_h_igi = (u8)var1[2];
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used,
-+					 "force H-state IGI = %2x\n",
-+					 dig_t->tdma_force_h_igi);
-+			}
-+		#endif
-+		}
-+
-+		#ifdef CFG_DIG_DAMPING_CHK
-+		else if (var1[0] == 1) {
-+			dig_t->dig_dl_en = (u8)var1[1];
-+			/*@*/
-+		}
-+		#endif
-+		else if (var1[0] == 6) {
-+			phydm_fw_dm_ctrl_en(dm, F00_DIG, (boolean)var1[1]);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "fw_dig_enable = %2x\n", dig_t->fw_dig_enable);
-+		}
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#ifdef CONFIG_MCC_DM
-+#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT|| RTL8723F_SUPPORT)
-+void phydm_mcc_igi_clr(void *dm_void, u8 clr_port)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
-+
-+	mcc_dm->mcc_rssi[clr_port] = 0xff;
-+	mcc_dm->mcc_dm_val[0][clr_port] = 0xff; /* 0xc50 clr */
-+	mcc_dm->mcc_dm_val[1][clr_port] = 0xff; /* 0xe50 clr */
-+}
-+
-+void phydm_mcc_igi_chk(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
-+
-+	if (mcc_dm->mcc_dm_val[0][0] == 0xff &&
-+	    mcc_dm->mcc_dm_val[0][1] == 0xff) {
-+		mcc_dm->mcc_dm_reg[0] = 0xffff;
-+		mcc_dm->mcc_reg_id[0] = 0xff;
-+	}
-+	if (mcc_dm->mcc_dm_val[1][0] == 0xff &&
-+	    mcc_dm->mcc_dm_val[1][1] == 0xff) {
-+		mcc_dm->mcc_dm_reg[1] = 0xffff;
-+		mcc_dm->mcc_reg_id[1] = 0xff;
-+	}
-+}
-+
-+void phydm_mcc_igi_cal(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	u8	shift = 0;
-+	u8	igi_val0, igi_val1;
-+
-+	if (mcc_dm->mcc_rssi[0] == 0xff)
-+		phydm_mcc_igi_clr(dm, 0);
-+	if (mcc_dm->mcc_rssi[1] == 0xff)
-+		phydm_mcc_igi_clr(dm, 1);
-+	phydm_mcc_igi_chk(dm);
-+	igi_val0 = mcc_dm->mcc_rssi[0] - shift;
-+	igi_val1 = mcc_dm->mcc_rssi[1] - shift;
-+
-+	if (igi_val0 < DIG_MIN_PERFORMANCE)
-+		igi_val0 = DIG_MIN_PERFORMANCE;
-+
-+	if (igi_val1 < DIG_MIN_PERFORMANCE)
-+		igi_val1 = DIG_MIN_PERFORMANCE;
-+
-+	switch (dm->ic_ip_series) {
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	case PHYDM_IC_JGR3:
-+		phydm_fill_mcccmd(dm, 0, R_0x1d70, igi_val0, igi_val1);
-+		phydm_fill_mcccmd(dm, 1, R_0x1d70 + 1, igi_val0, igi_val1);
-+		break;
-+	#endif
-+	default:
-+		phydm_fill_mcccmd(dm, 0, R_0xc50, igi_val0, igi_val1);
-+		phydm_fill_mcccmd(dm, 1, R_0xe50, igi_val0, igi_val1);
-+		break;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_COMP_MCC, "RSSI_min: %d %d, MCC_igi: %d %d\n",
-+		  mcc_dm->mcc_rssi[0], mcc_dm->mcc_rssi[1],
-+		  mcc_dm->mcc_dm_val[0][0], mcc_dm->mcc_dm_val[0][1]);
-+}
-+#endif /*#if (RTL8822B_SUPPORT)*/
-+#endif /*#ifdef CONFIG_MCC_DM*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_dig.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_dig.h
-new file mode 100644
-index 000000000000..9d5586fc48e9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_dig.h
-@@ -0,0 +1,380 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDMDIG_H__
-+#define __PHYDMDIG_H__
-+
-+/* 2019.10.25 remove redundant code*/
-+#define DIG_VERSION "3.7"
-+
-+#define	DIG_HW		0
-+#define DIG_LIMIT_PERIOD 60 /*60 sec*/
-+
-+/*@--------------------Define ---------------------------------------*/
-+
-+/*@=== [DIG Boundary] ========================================*/
-+/*@DIG coverage mode*/
-+#define	DIG_MAX_COVERAGR		0x26
-+#define	DIG_MIN_COVERAGE		0x1c
-+#define	DIG_MAX_OF_MIN_COVERAGE		0x22
-+
-+/*@[DIG Balance mode]*/
-+#if (DIG_HW == 1)
-+#define	DIG_MAX_BALANCE_MODE		0x32
-+#else
-+#define	DIG_MAX_BALANCE_MODE		0x3e
-+#endif
-+#define	DIG_MAX_OF_MIN_BALANCE_MODE	0x2a
-+
-+/*@[DIG Performance mode]*/
-+#define	DIG_MAX_PERFORMANCE_MODE	0x5a
-+#define	DIG_MAX_OF_MIN_PERFORMANCE_MODE	0x40	/*@[WLANBB-871]*/
-+#define	DIG_MIN_PERFORMANCE		0x20
-+
-+/*@DIG DFS function*/
-+#define	DIG_MAX_DFS			0x28
-+#define	DIG_MIN_DFS			0x20
-+
-+/*@DIG LPS function*/
-+#define	DIG_MAX_LPS			0x3e
-+#define	DIG_MIN_LPS			0x20
-+
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+#define DIG_NUM_OF_TDMA_STATES	2 /*@L, H state*/
-+#define DIG_TIMER_MS			250
-+#define	ONE_SEC_MS			1000
-+#endif
-+
-+/*@=== [DIG FA Threshold] ======================================*/
-+
-+/*Normal*/
-+#define	DM_DIG_FA_TH0			500
-+#define	DM_DIG_FA_TH1			750
-+
-+/*@LPS*/
-+#define	DM_DIG_FA_TH0_LPS		4	/* @-> 4 lps */
-+#define	DM_DIG_FA_TH1_LPS		15	/* @-> 15 lps */
-+#define	DM_DIG_FA_TH2_LPS		30	/* @-> 30 lps */
-+
-+#define	RSSI_OFFSET_DIG_LPS		5
-+#define DIG_RECORD_NUM			4
-+
-+/*@--------------------Enum-----------------------------------*/
-+enum phydm_dig_mode {
-+	PHYDM_DIG_PERFORAMNCE_MODE	= 0,
-+	PHYDM_DIG_COVERAGE_MODE		= 1,
-+};
-+
-+enum phydm_dig_trend {
-+	DIG_STABLE			= 0,
-+	DIG_INCREASING			= 1,
-+	DIG_DECREASING			= 2
-+};
-+
-+enum phydm_fw_dig_mode_e {
-+	DIG_PERFORMANCE_MODE	= 0,
-+	DIG_COVERAGE_MODE	= 1,
-+	DIG_LPS_MODE		= 2
-+};
-+
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+enum upd_type {
-+	ENABLE_TDMA,
-+	MODE_DECISION
-+};
-+
-+enum tdma_opmode {
-+	MODE_PERFORMANCE = 1,
-+	MODE_COVERAGE = 2
-+};
-+
-+#ifdef IS_USE_NEW_TDMA
-+enum tdma_dig_timer {
-+	INIT_TDMA_DIG_TIMMER,
-+	CANCEL_TDMA_DIG_TIMMER,
-+	RELEASE_TDMA_DIG_TIMMER
-+};
-+
-+enum tdma_dig_state {
-+	TDMA_DIG_LOW_STATE = 0,
-+	TDMA_DIG_HIGH_STATE = 1,
-+	NORMAL_DIG = 2
-+};
-+#endif
-+#endif
-+
-+/*@--------------------Define Struct-----------------------------------*/
-+#ifdef CFG_DIG_DAMPING_CHK
-+struct phydm_dig_recorder_strcut {
-+	u8		igi_bitmap; /*@Don't add any new parameter before this*/
-+	u8		igi_history[DIG_RECORD_NUM];
-+	u32		fa_history[DIG_RECORD_NUM];
-+	u8		damping_limit_en;
-+	u8		damping_limit_val; /*@Limit IGI_dyn_min*/
-+	u32		limit_time;
-+	u8		limit_rssi;
-+};
-+#endif
-+
-+struct phydm_mcc_dig {
-+	u8		mcc_rssi_A;
-+	u8		mcc_rssi_B;
-+};
-+
-+struct phydm_dig_struct {
-+#ifdef CFG_DIG_DAMPING_CHK
-+	struct phydm_dig_recorder_strcut dig_recorder_t;
-+	u8		dig_dl_en; /*@damping limit function enable*/
-+#endif
-+	boolean		fw_dig_enable;
-+	boolean		is_dbg_fa_th;
-+	u8		cur_ig_value;
-+	boolean		igi_dyn_up_hit;
-+	u8		igi_trend;
-+	u32		rvrt_val; /*all rvrt_val for pause API must set to u32*/
-+	u8		igi_backup;
-+	u8		rx_gain_range_max;	/*@dig_dynamic_max*/
-+	u8		rx_gain_range_min;	/*@dig_dynamic_min*/
-+	u8		dm_dig_max;		/*@Absolutly upper bound*/
-+	u8		dm_dig_min;		/*@Absolutly lower bound*/
-+	u8		dig_max_of_min;		/*@Absolutly max of min*/
-+	u32		ant_div_rssi_max;
-+	u8		*is_p2p_in_process;
-+	u16		fa_th[3];
-+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\
-+	RTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\
-+	RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8721D_SUPPORT ||\
-+	RTL8710C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT ||\
-+	RTL8723F_SUPPORT)
-+	u8		rf_gain_idx;
-+	u8		agc_table_idx;
-+	u8		big_jump_lmt[16];
-+	u8		enable_adjust_big_jump:1;
-+	u8		big_jump_step1:3;
-+	u8		big_jump_step2:2;
-+	u8		big_jump_step3:2;
-+#endif
-+	u8		upcheck_init_val;
-+	u8		lv0_ratio_reciprocal;
-+	u8		lv1_ratio_reciprocal;
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	u8		cur_ig_value_tdma;
-+	u8		low_ig_value;
-+	u8		tdma_dig_state;	/*@To distinguish which state is now.(L-sate or H-state)*/
-+	u8		tdma_dig_cnt;	/*@for phydm_tdma_dig_timer_check use*/
-+	u8		pre_tdma_dig_cnt;
-+	u8		sec_factor;
-+	u32		cur_timestamp;
-+	u32		pre_timestamp;
-+	u32		fa_start_timestamp;
-+	u32		fa_end_timestamp;
-+	u32		fa_acc_1sec_timestamp;
-+#ifdef IS_USE_NEW_TDMA
-+	u8		tdma_dig_block_cnt;/*@for 1 second dump indicator use*/
-+			/*@dynamic upper bound for L/H state*/
-+	u8		tdma_rx_gain_max[DIG_NUM_OF_TDMA_STATES];
-+			/*@dynamic lower bound for L/H state*/
-+	u8		tdma_rx_gain_min[DIG_NUM_OF_TDMA_STATES];
-+			/*To distinguish current state(L-sate or H-state)*/
-+#endif
-+	u8		tdma_force_l_igi;
-+	u8		tdma_force_h_igi;
-+#endif
-+};
-+
-+struct phydm_fa_struct {
-+	u32		cnt_parity_fail;
-+	u32		cnt_rate_illegal;
-+	u32		cnt_crc8_fail;
-+	u32		cnt_crc8_fail_vhta;
-+	u32		cnt_crc8_fail_vhtb;
-+	u32		cnt_mcs_fail;
-+	u32		cnt_mcs_fail_vht;
-+	u32		cnt_ofdm_fail;
-+	u32		cnt_ofdm_fail_pre;	/* @For RTL8881A */
-+	u32		cnt_cck_fail;
-+	u32		cnt_all;
-+	u32		cnt_all_accumulated;
-+	u32		cnt_all_pre;
-+	u32		cnt_fast_fsync;
-+	u32		cnt_sb_search_fail;
-+	u32		cnt_ofdm_cca;
-+	u32		cnt_cck_cca;
-+	u32		cnt_cca_all;
-+	u32		cnt_bw_usc;
-+	u32		cnt_bw_lsc;
-+	u32		cnt_cck_crc32_error;
-+	u32		cnt_cck_crc32_ok;
-+	u32		cnt_ofdm_crc32_error;
-+	u32		cnt_ofdm_crc32_ok;
-+	u32		cnt_ht_crc32_error;
-+	u32		cnt_ht_crc32_ok;
-+	u32		cnt_ht_crc32_error_agg;
-+	u32		cnt_ht_crc32_ok_agg;
-+	u32		cnt_vht_crc32_error;
-+	u32		cnt_vht_crc32_ok;
-+	u32		cnt_crc32_error_all;
-+	u32		cnt_crc32_ok_all;
-+	u32		time_fa_all;
-+	boolean		cck_block_enable;
-+	boolean		ofdm_block_enable;
-+	u32		dbg_port0;
-+	boolean		edcca_flag;
-+	u8		ofdm2_rate_idx;
-+	u32		cnt_ofdm2_crc32_error;
-+	u32		cnt_ofdm2_crc32_ok;
-+	u8		ofdm2_pcr;
-+	u8		ht2_rate_idx;
-+	u32		cnt_ht2_crc32_error;
-+	u32		cnt_ht2_crc32_ok;
-+	u8		ht2_pcr;
-+	u8		vht2_rate_idx;
-+	u32		cnt_vht2_crc32_error;
-+	u32		cnt_vht2_crc32_ok;
-+	u8		vht2_pcr;
-+
-+};
-+
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+struct phydm_fa_acc_struct {
-+	u32		cnt_parity_fail;
-+	u32		cnt_rate_illegal;
-+	u32		cnt_crc8_fail;
-+	u32		cnt_mcs_fail;
-+	u32		cnt_ofdm_fail;
-+	u32		cnt_ofdm_fail_pre;	/*@For RTL8881A*/
-+	u32		cnt_cck_fail;
-+	u32		cnt_all;
-+	u32		cnt_all_pre;
-+	u32		cnt_fast_fsync;
-+	u32		cnt_sb_search_fail;
-+	u32		cnt_ofdm_cca;
-+	u32		cnt_cck_cca;
-+	u32		cnt_cca_all;
-+	u32		cnt_cck_crc32_error;
-+	u32		cnt_cck_crc32_ok;
-+	u32		cnt_ofdm_crc32_error;
-+	u32		cnt_ofdm_crc32_ok;
-+	u32		cnt_ht_crc32_error;
-+	u32		cnt_ht_crc32_ok;
-+	u32		cnt_vht_crc32_error;
-+	u32		cnt_vht_crc32_ok;
-+	u32		cnt_crc32_error_all;
-+	u32		cnt_crc32_ok_all;
-+	u32		cnt_all_1sec;
-+	u32		cnt_cca_all_1sec;
-+	u32		cnt_cck_fail_1sec;
-+};
-+
-+#endif	/*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
-+
-+/*@--------------------Function declaration-----------------------------*/
-+void phydm_write_dig_reg(void *dm_void, u8 igi);
-+
-+void odm_write_dig(void *dm_void, u8 current_igi);
-+
-+u8 phydm_get_igi(void *dm_void, enum bb_path path);
-+
-+void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len);
-+
-+void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type,
-+		   enum phydm_pause_level pause_level, u8 igi_value);
-+
-+#ifdef PHYDM_HW_IGI
-+void phydm_hwigi(void *dm_void);
-+
-+void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used,
-+		     char *output, u32 *_out_len);
-+#endif
-+
-+void phydm_dig_init(void *dm_void);
-+
-+void phydm_dig(void *dm_void);
-+
-+void phydm_dig_lps_32k(void *dm_void);
-+
-+void phydm_dig_by_rssi_lps(void *dm_void);
-+
-+void phydm_get_dig_coverage(void *dm_void, u8 *max, u8 *min);
-+
-+u8 phydm_get_igi_for_target_pin_scan(void *dm_void, u8 rssi);
-+
-+void phydm_false_alarm_counter_statistics(void *dm_void);
-+
-+u32 phydm_get_edcca_report(void * dm_void);
-+
-+#ifdef PHYDM_TDMA_DIG_SUPPORT
-+void phydm_set_tdma_dig_timer(void *dm_void);
-+
-+void phydm_tdma_dig_timer_check(void *dm_void);
-+
-+void phydm_tdma_dig(void *dm_void);
-+
-+void phydm_tdma_false_alarm_counter_check(void *dm_void);
-+
-+void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void);
-+
-+void phydm_false_alarm_counter_reset(void *dm_void);
-+
-+void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en);
-+
-+void phydm_false_alarm_counter_acc_reset(void *dm_void);
-+
-+void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input);
-+
-+#ifdef IS_USE_NEW_TDMA
-+void phydm_tdma_dig_timers(void *dm_void, u8 state);
-+
-+void phydm_tdma_dig_cbk(void *dm_void);
-+
-+void phydm_tdma_dig_workitem_callback(void *dm_void);
-+
-+void phydm_tdma_fa_cnt_chk(void *dm_void);
-+
-+void phydm_tdma_low_dig(void *dm_void);
-+
-+void phydm_tdma_high_dig(void *dm_void);
-+
-+void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en,
-+		      u8 cur_tdma_dig_state);
-+#endif /*@#ifdef IS_USE_NEW_TDMA*/
-+#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
-+
-+void phydm_set_ofdm_agc_tab(void *dm_void, u8 tab_sel);
-+
-+void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
-+		     u32 *_out_len);
-+
-+void phydm_fill_fw_dig_info(void *dm_void, boolean *enable,
-+			    u8 *para4, u8 *para8);
-+
-+void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used,
-+			 char *output, u32 *_out_len);
-+
-+#ifdef CONFIG_MCC_DM
-+void phydm_mcc_igi_cal(void *dm_void);
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_direct_bf.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_direct_bf.c
-new file mode 100644
-index 000000000000..55dd2f8dacca
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_direct_bf.c
-@@ -0,0 +1,366 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ***************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+#ifdef CONFIG_DIRECTIONAL_BF
-+#ifdef PHYDM_COMPILE_IC_2SS
-+void phydm_iq_gen_en(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	enum rf_path i = RF_PATH_A;
-+	enum rf_path path = RF_PATH_A;
-+
-+	#if (ODM_IC_11AC_SERIES_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8822B) {
-+		for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
-+			/*RF mode table write enable*/
-+			odm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x1);
-+			/*Select RX mode*/
-+			odm_set_rf_reg(dm, path, RF_0x33, 0xF, 3);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, path, RF_0x3e, 0xfffff, 0x00036);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, path, RF_0x3f, 0xfffff, 0x5AFCE);
-+			/*RF mode table write disable*/
-+			odm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x0);
-+		}
-+	}
-+	#endif
-+
-+	#if (ODM_IC_11N_SERIES_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8192F) {
-+		/*RF mode table write enable*/
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1);
-+		/* Path A */
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x08000);
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0005f);
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x01042);
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000);
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0004f);
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x71fc2);
-+		/* Path B */
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x08000);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00050);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x01042);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00040);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x71fc2);
-+		/*RF mode table write disable*/
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0);
-+	}
-+	#endif
-+
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (dm->support_ic_type & ODM_RTL8197G) {
-+		/*RF mode table write enable*/
-+		/* Path A */
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1);
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000);
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x000cf);
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x71fc2);
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0);
-+
-+		/* Path B */
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x000cf);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x71fc2);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x08000);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x000ef);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x01042);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0);
-+	}
-+	#endif
-+
-+}
-+
-+void phydm_dis_cdd(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	#if (ODM_IC_11AC_SERIES_SUPPORT)
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		odm_set_bb_reg(dm, R_0x808, 0x3ffff00, 0);
-+		odm_set_bb_reg(dm, R_0x9ac, 0x1fff, 0);
-+		odm_set_bb_reg(dm, R_0x9ac, BIT(13), 1);
-+	}
-+	#endif
-+	#if (ODM_IC_11N_SERIES_SUPPORT)
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		odm_set_bb_reg(dm, R_0x90c, 0xffffffff, 0x83321333);
-+		/* Set Tx delay setting for CCK pathA,B*/
-+		odm_set_bb_reg(dm, R_0xa2c, 0xf0000000, 0);
-+		/*Enable Tx CDD for HT part when spatial expansion is applied*/
-+		odm_set_bb_reg(dm, R_0xd00, BIT(8), 0);
-+		/* Tx CDD for Legacy*/
-+		odm_set_bb_reg(dm, R_0xd04, 0xf0000, 0);
-+		/* Tx CDD for non-HT*/
-+		odm_set_bb_reg(dm, R_0xd0c, 0x3c0, 0);
-+		/* Tx CDD for HT SS1*/
-+		odm_set_bb_reg(dm, R_0xd0c, 0xf8000, 0);
-+	}
-+	#endif
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		/* Tx CDD for Legacy Preamble*/
-+		odm_set_bb_reg(dm, R_0x1cc0, 0xffffffff, 0x24800000);
-+		/* Tx CDD for HT Preamble*/
-+		odm_set_bb_reg(dm, R_0x1cb0, 0xffffffff, 0);
-+	}
-+	#endif
-+}
-+
-+void phydm_pathb_q_matrix_rotate_en(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	phydm_iq_gen_en(dm);
-+
-+	/*#ifdef PHYDM_COMMON_API_SUPPORT*/
-+	/*path selection is controlled by driver*/
-+	#if 0
-+	if (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, BB_PATH_AB))
-+		return;
-+	#endif
-+
-+	phydm_dis_cdd(dm);
-+	phydm_pathb_q_matrix_rotate(dm, 0);
-+
-+	#if (ODM_IC_11AC_SERIES_SUPPORT)
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		/*Set Q matrix r_v11 =1*/
-+		odm_set_bb_reg(dm, R_0x195c, MASKDWORD, 0x40000);
-+		/*Set Q matrix enable*/
-+		odm_set_bb_reg(dm, R_0x191c, BIT(7), 1);
-+	}
-+	#endif
-+}
-+
-+void phydm_pathb_q_matrix_rotate(void *dm_void, u16 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	#if (ODM_IC_11AC_SERIES_SUPPORT)
-+	u32 phase_table_0[ANGLE_NUM] = {0x40000, 0x376CF, 0x20000, 0x00000,
-+					0xFE0000, 0xFC8930, 0xFC0000,
-+					0xFC8930, 0xFDFFFF, 0x000000,
-+					0x020000, 0x0376CF};
-+	u32 phase_table_1[ANGLE_NUM] = {0x00000, 0x1FFFF, 0x376CF, 0x40000,
-+					0x0376CF, 0x01FFFF, 0x000000,
-+					0xFDFFFF, 0xFC8930, 0xFC0000,
-+					0xFC8930, 0xFDFFFF};
-+	#endif
-+	#if (ODM_IC_11N_SERIES_SUPPORT)
-+	u32 phase_table_n_0[ANGLE_NUM] = {0x00, 0x0B, 0x02, 0x00, 0x02, 0x02,
-+					  0x04, 0x02, 0x0D, 0x09, 0x04, 0x0B};
-+	u32 phase_table_n_1[ANGLE_NUM] = {0x40000100, 0x377F00DD, 0x201D8880,
-+					  0x00000000, 0xE01D8B80, 0xC8BF0322,
-+					  0xC000FF00, 0xC8BF0322, 0xDFE2777F,
-+					  0xFFC003FF, 0x20227480, 0x377F00DD};
-+	u32 phase_table_n_2[ANGLE_NUM] = {0x00, 0x1E, 0x3C, 0x4C, 0x3C, 0x1E,
-+					  0x0F, 0xD2, 0xC3, 0xC4, 0xC3, 0xD2};
-+	#endif
-+	if (idx >= ANGLE_NUM) {
-+		pr_debug("[%s]warning Phase Set Error: %d\n", __func__, idx);
-+		return;
-+	}
-+
-+	switch (dm->ic_ip_series) {
-+	#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
-+	case PHYDM_IC_AC:
-+		/*Set Q matrix r_v21*/
-+		odm_set_bb_reg(dm, R_0x1954, 0xffffff, phase_table_0[idx]);
-+		odm_set_bb_reg(dm, R_0x1950, 0xffffff, phase_table_1[idx]);
-+		break;
-+	#endif
-+
-+	#if (ODM_IC_11N_SERIES_SUPPORT == 1)
-+	case PHYDM_IC_N:
-+		/*Set Q matrix r_v21*/
-+		odm_set_bb_reg(dm, R_0xc4c, 0xff000000, phase_table_n_0[idx]);
-+		odm_set_bb_reg(dm, R_0xc88, 0xffffffff, phase_table_n_1[idx]);
-+		odm_set_bb_reg(dm, R_0xc9c, 0xff000000, phase_table_n_2[idx]);
-+		break;
-+	#endif
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+/*Before use this API, Fill correct Tx Des. and Disable STBC in advance*/
-+void phydm_set_direct_bfer(void *dm_void, u16 phs_idx, u8 su_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if (RTL8822B_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8822B) {
-+#if 0
-+		u8 phi[13] = {0x0, 0x5, 0xa, 0xf, 0x15, 0x1a, 0x1f, 0x25,
-+			      0x2a, 0x2f, 0x35, 0x3a, 0x0};
-+		u8 psi[13] = {0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
-+			      0x7, 0x7, 0x7, 0x7};
-+		u16 psiphi[13] = {0x1c0, 0x1c5, 0x1ca, 0x1cf, 0x1d5, 0x1da,
-+				  0x1df, 0x1e5, 0x1ea, 0x1ef, 0x1f5, 0x1fa,
-+				  0x1c0}; //{Psi_4bit, Phi_6bit} of 0~360
-+#endif
-+		u16 ns[3] = {52, 108, 234}; //20/40/80 MHz subcarrier number
-+		u16 psiphi[13] = {0x1c0, 0x1c5, 0x1ca, 0x1cf, 0x1d5, 0x1da,
-+				  0x1df, 0x1e5, 0x1ea, 0x1ef, 0x1f5, 0x1fa,
-+				  0x1c0}; //{Psi_4bit, Phi_6bit} of 0~360
-+		u16 psiphiR;
-+		u8 i;
-+		u8 snr = 0x12; // for 1SS BF
-+		u8 nc = 0x0; //bit 2-0
-+		u8 nr = 0x1; //bit 5-3
-+		u8 ng = 0x0; //bit 7-6
-+		u8 cb = 0x1; //bit 9-8; 1 => phi:6, psi:4;
-+		u32 bw = odm_get_bb_reg(dm, R_0x8ac, 0x3); //bit 11-10
-+		u8 userid = su_idx; //bit 12
-+		u32 csi_report = 0x0;
-+		u32 ndp_bw = odm_get_bb_reg(dm, R_0x8ac, 0x3); //bit 11-10
-+		u8 ndp_sc = 0; //bit 11-10
-+		u32 ndp_info = 0x0;
-+
-+		u16 mem_num = 0;
-+		u8 mem_move = 0;
-+		u8 mem_sel = 0;
-+		u16 mem_addr = 0;
-+		u32 dw0, dw1;
-+		u64 vm_info = 0;
-+		u64 temp = 0;
-+		u8 vm_cnt = 0;
-+
-+		mem_num = ((8 + (6 + 4) * ns[bw]) >> 6) + 1; // SU codebook 1
-+
-+		/* setting NDP BW/SC info*/
-+		ndp_info = (ndp_bw & 0x3)  | (ndp_bw & 0x3) << 6 |
-+			   (ndp_bw & 0x3) << 12 | (ndp_sc & 0xf) << 2 |
-+			   (ndp_sc & 0xf) << 8 | (ndp_sc & 0xf) << 14;
-+		odm_set_bb_reg(dm, R_0xb58, 0x000FFFFC, ndp_info);
-+		odm_set_bb_reg(dm, R_0x19f8, 0x00010000, 1);
-+		ODM_delay_ms(1); // delay 1ms
-+		odm_set_bb_reg(dm, R_0x19f8, 0x00010000, 0);
-+
-+		/* setting CSI report info*/
-+		csi_report = (userid & 0x1) << 12 | (bw & 0x3) << 10 |
-+			     (cb & 0x3) << 8 | (ng & 0x3) << 6 |
-+			     (nr & 0x7) << 3 | (nc & 0x7);
-+		odm_set_bb_reg(dm, R_0x72c, 0x1FFF, csi_report);
-+		odm_set_bb_reg(dm, R_0x71c, 0x80000000, 1);
-+		PHYDM_DBG(dm, DBG_TXBF, "[%s] direct BF csi report 0x%x\n",
-+			  __func__, csi_report);
-+		/*========================*/
-+
-+		odm_set_bb_reg(dm, R_0x19b8, 0x40, 1); //0x19b8[6]:1 to csi_rpt
-+		odm_set_bb_reg(dm, R_0x19e0, 0x3FC0, 0xFF); //gated_clk off
-+		odm_set_bb_reg(dm, R_0x9e8, 0x2000000, 1); //abnormal txbf
-+		odm_set_bb_reg(dm, R_0x9e8, 0x1000000, 0); //read phi psi
-+		odm_set_bb_reg(dm, R_0x9e8, 0x70000000, su_idx); //SU user 0
-+		odm_set_bb_reg(dm, R_0x1910, 0x8000, 0); //BFer
-+
-+		dw0 = 0; // for 0x9ec
-+		dw1 = 0; // for 0x1900
-+		mem_addr = 0;
-+		mem_sel = 0;
-+		mem_move = 0;
-+		vm_info = vm_info | (snr & 0xff); //V matrix info
-+		vm_cnt = 8; // V matrix length counter
-+		psiphiR = (psiphi[phs_idx] & 0x3ff);
-+
-+		while (mem_addr < mem_num) {
-+			while (vm_cnt <= 32) {
-+				// shift only max. 32 bit
-+				if (vm_cnt >= 20) {
-+					temp = psiphiR << 20;
-+					temp = temp << (vm_cnt - 20);
-+				} else {
-+					temp = psiphiR << vm_cnt;
-+				}
-+				vm_info |= temp;
-+				vm_cnt += 10;
-+			}
-+			if (mem_sel == 0) {
-+				dw0 = vm_info & 0xffffffff;
-+				vm_info = vm_info >> 32;
-+				vm_cnt -= 32;
-+				mem_sel = 1;
-+				mem_move = 0;
-+			} else {
-+				dw1 = vm_info & 0xffffffff;
-+				vm_info = vm_info >> 32;
-+				vm_cnt -= 32;
-+				mem_sel = 0;
-+				mem_move = 1;
-+			}
-+			if (mem_move == 1) {
-+				odm_set_bb_reg(dm, 0x9e8, 0x1000000, 0);
-+					       //read phi psi
-+				odm_set_bb_reg(dm, 0x1910, 0x3FF0000,
-+					       mem_addr);
-+				odm_set_bb_reg(dm, 0x09ec, 0xFFFFFFFF, dw0);
-+				odm_set_bb_reg(dm, 0x1900, 0xFFFFFFFF, dw1);
-+				odm_set_bb_reg(dm, 0x9e8, 0x1000000, 1);
-+					       //write phi psi
-+				mem_move = 0;
-+				mem_addr += 1;
-+			}
-+		}
-+		odm_set_bb_reg(dm, 0x9e8, 0x2000000, 0); //normal txbf
-+	}
-+#endif
-+} //end function
-+
-+/*Before use this API, Disable STBC in advance*/
-+/*only 1SS rate can improve performance*/
-+void phydm_set_direct_bfer_txdesc_en(void *dm_void, u8 enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if (RTL8197G_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197G) {
-+		phydm_iq_gen_en(dm);
-+
-+		/*#ifdef PHYDM_COMMON_API_SUPPORT*/
-+		/*path selection is controlled by driver, use 1ss 2Tx*/
-+		#if 0
-+		if (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, BB_PATH_AB))
-+			return;
-+		#endif
-+
-+		phydm_dis_cdd(dm);
-+		if (enable)
-+			odm_set_bb_reg(dm, R_0x1d90, 0x8000, 1);
-+		else
-+			odm_set_bb_reg(dm, R_0x1d90, 0x8000, 0);
-+	}
-+#endif
-+} //end function
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_direct_bf.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_direct_bf.h
-new file mode 100644
-index 000000000000..c9c4c4bed628
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_direct_bf.h
-@@ -0,0 +1,44 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_DIR_BF_H__
-+#define __PHYDM_DIR_BF_H__
-+
-+#ifdef CONFIG_DIRECTIONAL_BF
-+#define ANGLE_NUM	12
-+
-+/*@
-+ * ============================================================
-+ * function prototype
-+ * ============================================================
-+ */
-+void phydm_iq_gen_en(void *dm_void);
-+void phydm_dis_cdd(void *dm_void);
-+void phydm_pathb_q_matrix_rotate_en(void *dm_void);
-+void phydm_pathb_q_matrix_rotate(void *dm_void, u16 idx);
-+void phydm_set_direct_bfer(void *dm_void, u16 phs_idx, u8 su_idx);
-+void phydm_set_direct_bfer_txdesc_en(void *dm_void, u8 enable);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_dynamictxpower.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_dynamictxpower.c
-new file mode 100644
-index 000000000000..2ccbd1ae822f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_dynamictxpower.c
-@@ -0,0 +1,795 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*************************************************************
-+ * include files
-+ ************************************************************/
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef CONFIG_DYNAMIC_TX_TWR
-+#ifdef BB_RAM_SUPPORT
-+void phydm_rd_reg_pwr(void *dm_void, u32 *_used, char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	boolean pwr_ofst0_en = false;
-+	boolean pwr_ofst1_en = false;
-+	s8 pwr_ofst0 = 0;
-+	s8 pwr_ofst1 = 0;
-+
-+	pwr_ofst0_en = (boolean)odm_get_bb_reg(dm, R_0x1e70, BIT(23));
-+	pwr_ofst1_en = (boolean)odm_get_bb_reg(dm, R_0x1e70, BIT(31));
-+	pwr_ofst0 = (s8)odm_get_bb_reg(dm, R_0x1e70, 0x7f0000);
-+	pwr_ofst1 = (s8)odm_get_bb_reg(dm, R_0x1e70, 0x7f000000);
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "reg0: en:%d, pwr_ofst:0x%x, reg1: en:%d, pwr_ofst:0x%x\n",
-+		 pwr_ofst0_en, pwr_ofst0, pwr_ofst1_en, pwr_ofst1);
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+};
-+
-+void phydm_wt_reg_pwr(void *dm_void, boolean is_ofst1, boolean pwr_ofst_en,
-+		      s8 pwr_ofst)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
-+	u8 reg_0x1e70 = 0;
-+
-+	if (!is_ofst1) {
-+		bb_ctrl->tx_pwr_ofst_reg0_en = pwr_ofst_en;
-+		bb_ctrl->tx_pwr_ofst_reg0 = pwr_ofst;
-+
-+		reg_0x1e70 |= (pwr_ofst_en << 7) + (pwr_ofst & 0x7f);
-+		odm_set_bb_reg(dm, R_0x1e70, 0x00ff0000, reg_0x1e70);
-+	} else {
-+		bb_ctrl->tx_pwr_ofst_reg1_en = pwr_ofst_en;
-+		bb_ctrl->tx_pwr_ofst_reg1 = pwr_ofst;
-+
-+		reg_0x1e70 |= (pwr_ofst_en << 7) + (pwr_ofst & 0x7f);
-+		odm_set_bb_reg(dm, R_0x1e70, 0xff000000, reg_0x1e70);
-+	}
-+};
-+
-+void phydm_rd_ram_pwr(void *dm_void, u8 macid, u32 *_used, char *output,
-+		      u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	boolean pwr_ofst0_en = false;
-+	boolean pwr_ofst1_en = false;
-+	s8 pwr_ofst0 = 0;
-+	s8 pwr_ofst1 = 0;
-+	u32 reg_0x1e84 = 0;
-+
-+	reg_0x1e84 |= (macid & 0x3f) << 24; /* macid*/
-+	reg_0x1e84 |= BIT(31); /* read_en*/
-+	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
-+
-+	pwr_ofst0_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(23));
-+	pwr_ofst1_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(31));
-+	pwr_ofst0 = (s8)odm_get_bb_reg(dm, R_0x2de8, 0x7f0000);
-+	pwr_ofst1 = (s8)odm_get_bb_reg(dm, R_0x2de8, 0x7f000000);
-+	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "(macid:%d) ram0: en:%d, pwr_ofst:0x%x, ram1: en:%d, pwr_ofst:0x%x\n",
-+		 macid, pwr_ofst0_en, pwr_ofst0, pwr_ofst1_en, pwr_ofst1);
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+};
-+
-+void phydm_wt_ram_pwr(void *dm_void, u8 macid, boolean is_ofst1,
-+		      boolean pwr_ofst_en, s8 pwr_ofst)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
-+	u32 reg_0x1e84 = 0;
-+	boolean pwr_ofst_ano_en = false;
-+	s8 pwr_ofst_ano = 0;
-+
-+	if (macid > 63)
-+		macid = 63;
-+
-+	dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid];
-+	reg_0x1e84 = (dm_ram_per_sta->hw_igi_en << 7) + dm_ram_per_sta->hw_igi;
-+	if (!is_ofst1) {
-+		dm_ram_per_sta->tx_pwr_offset0_en = pwr_ofst_en;
-+		dm_ram_per_sta->tx_pwr_offset0 = pwr_ofst;
-+
-+		pwr_ofst_ano_en = dm_ram_per_sta->tx_pwr_offset1_en;
-+		pwr_ofst_ano = dm_ram_per_sta->tx_pwr_offset1;
-+
-+		reg_0x1e84 |= (pwr_ofst_en << 15) + ((pwr_ofst & 0x7f) << 8) +
-+			      (pwr_ofst_ano_en << 23) +
-+			      ((pwr_ofst_ano & 0x7f) << 16);
-+	} else {
-+		dm_ram_per_sta->tx_pwr_offset1_en = pwr_ofst_en;
-+		dm_ram_per_sta->tx_pwr_offset1 = pwr_ofst;
-+
-+		pwr_ofst_ano_en = dm_ram_per_sta->tx_pwr_offset0_en;
-+		pwr_ofst_ano = dm_ram_per_sta->tx_pwr_offset0;
-+
-+		reg_0x1e84 |= (pwr_ofst_ano_en << 15) +
-+			      ((pwr_ofst_ano & 0x7f) << 8) +
-+			      (pwr_ofst_en << 23) +  ((pwr_ofst & 0x7f) << 16);
-+	}
-+	reg_0x1e84 |= (macid & 0x3f) << 24;/* macid*/
-+	reg_0x1e84 |= BIT(30); /* write_en*/
-+	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
-+	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); /* read_en*/
-+	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
-+};
-+
-+void phydm_rst_ram_pwr(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
-+	u32 reg_0x1e84 = 0;
-+	u8 i = 0;
-+
-+	for (i = 0; i < 64; i++) {
-+		dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[i];
-+		dm_ram_per_sta->tx_pwr_offset0_en = false;
-+		dm_ram_per_sta->tx_pwr_offset1_en = false;
-+		dm_ram_per_sta->tx_pwr_offset0 = 0x0;
-+		dm_ram_per_sta->tx_pwr_offset1 = 0x0;
-+		reg_0x1e84 = (dm_ram_per_sta->hw_igi_en << 7) +
-+			     dm_ram_per_sta->hw_igi;
-+		reg_0x1e84 |= (i & 0x3f) << 24;
-+		reg_0x1e84 |= BIT(30);
-+		odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
-+	}
-+
-+	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000);
-+	odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0);
-+};
-+
-+u8 phydm_pwr_lv_mapping_2nd(u8 tx_pwr_lv)
-+{
-+	if (tx_pwr_lv == tx_high_pwr_level_level3)
-+		return PHYDM_2ND_OFFSET_MINUS_11DB;
-+	else if (tx_pwr_lv == tx_high_pwr_level_level2)
-+		return PHYDM_2ND_OFFSET_MINUS_7DB;
-+	else if (tx_pwr_lv == tx_high_pwr_level_level1)
-+		return PHYDM_2ND_OFFSET_MINUS_3DB;
-+	else
-+		return PHYDM_2ND_OFFSET_ZERO;
-+}
-+
-+void phydm_pwr_lv_ctrl(void *dm_void, u8 macid, u8 tx_pwr_lv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	s8 pwr_offset = 0;
-+
-+	if (tx_pwr_lv == tx_high_pwr_level_level3)
-+		pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_11DB;
-+	else if (tx_pwr_lv == tx_high_pwr_level_level2)
-+		pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_7DB;
-+	else if (tx_pwr_lv == tx_high_pwr_level_level1)
-+		pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_3DB;
-+	else
-+		pwr_offset = PHYDM_BBRAM_OFFSET_ZERO;
-+
-+	phydm_wt_ram_pwr(dm, macid, RAM_PWR_OFST0, true, pwr_offset);
-+}
-+
-+void phydm_dtp_fill_cmninfo_2nd(void *dm_void, u8 sta_id, u8 dtp_lvl)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
-+	struct dtp_info *dtp = NULL;
-+
-+	if (!is_sta_active(sta))
-+		return;
-+
-+	dtp = &dm->phydm_sta_info[sta_id]->dtp_stat;
-+	dtp->dyn_tx_power = phydm_pwr_lv_mapping_2nd(dtp_lvl);
-+	phydm_pwr_lv_ctrl(dm, sta->mac_id, dtp_lvl);
-+
-+	PHYDM_DBG(dm, DBG_DYN_TXPWR,
-+		  "Fill cmninfo TxPwr: sta_id=(%d), macid=(%d), PwrLv (%d)\n",
-+		  sta_id, sta->mac_id, dtp->dyn_tx_power);
-+}
-+
-+void phydm_dtp_init_2nd(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
-+		return;
-+
-+	#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
-+		phydm_rst_ram_pwr(dm);
-+		/* rsp tx use type 0*/
-+		odm_set_mac_reg(dm, R_0x6d8, BIT(19) | BIT(18), RAM_PWR_OFST0);
-+	}
-+	#endif
-+};
-+#endif
-+
-+boolean
-+phydm_check_rates(void *dm_void, u8 rate_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 check_rate_bitmap0 = 0x08080808; /* @check CCK11M, OFDM54M, MCS7, MCS15*/
-+	u32 check_rate_bitmap1 = 0x80200808; /* @check MCS23, MCS31, VHT1SS M9, VHT2SS M9*/
-+	u32 check_rate_bitmap2 = 0x00080200; /* @check VHT3SS M9, VHT4SS M9*/
-+	u32 bitmap_result;
-+
-+#if (RTL8822B_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8822B) {
-+		check_rate_bitmap2 &= 0;
-+		check_rate_bitmap1 &= 0xfffff000;
-+		check_rate_bitmap0 &= 0x0fffffff;
-+	}
-+#endif
-+#if (RTL8197F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197F) {
-+		check_rate_bitmap2 &= 0;
-+		check_rate_bitmap1 &= 0;
-+		check_rate_bitmap0 &= 0x0fffffff;
-+	}
-+#endif
-+#if (RTL8192E_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8192E) {
-+		check_rate_bitmap2 &= 0;
-+		check_rate_bitmap1 &= 0;
-+		check_rate_bitmap0 &= 0x0fffffff;
-+	}
-+#endif
-+#if (RTL8192F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8192F) {
-+		check_rate_bitmap2 &= 0;
-+		check_rate_bitmap1 &= 0;
-+		check_rate_bitmap0 &= 0x0fffffff;
-+	}
-+#endif
-+#if (RTL8721D_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8721D) {
-+		check_rate_bitmap2 &= 0;
-+		check_rate_bitmap1 &= 0;
-+		check_rate_bitmap0 &= 0x000fffff;
-+	}
-+#endif
-+#if (RTL8821C_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8821C) {
-+		check_rate_bitmap2 &= 0;
-+		check_rate_bitmap1 &= 0x003ff000;
-+		check_rate_bitmap0 &= 0x000fffff;
-+	}
-+#endif
-+	if (rate_idx >= 64)
-+		bitmap_result = BIT(rate_idx - 64) & check_rate_bitmap2;
-+	else if (rate_idx >= 32)
-+		bitmap_result = BIT(rate_idx - 32) & check_rate_bitmap1;
-+	else if (rate_idx <= 31)
-+		bitmap_result = BIT(rate_idx) & check_rate_bitmap0;
-+
-+	if (bitmap_result != 0)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+enum rf_path
-+phydm_check_paths(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	enum rf_path max_path = RF_PATH_A;
-+
-+	if (dm->num_rf_path == 1)
-+		max_path = RF_PATH_A;
-+	if (dm->num_rf_path == 2)
-+		max_path = RF_PATH_B;
-+	if (dm->num_rf_path == 3)
-+		max_path = RF_PATH_C;
-+	if (dm->num_rf_path == 4)
-+		max_path = RF_PATH_D;
-+
-+	return max_path;
-+}
-+
-+#ifdef PHYDM_COMMON_API_NOT_SUPPORT
-+u8 phydm_dtp_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 ret = 0xff;
-+
-+	ret = config_phydm_read_txagc_n(dm, path, hw_rate);
-+
-+	return ret;
-+}
-+#endif
-+
-+u8 phydm_search_min_power_index(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	enum rf_path path;
-+	enum rf_path max_path;
-+	u8 min_gain_index = 0x3f;
-+	u8 gain_index = 0;
-+	u8 i;
-+
-+	PHYDM_DBG(dm, DBG_DYN_TXPWR, "%s\n", __func__);
-+	max_path = phydm_check_paths(dm);
-+	for (path = 0; path <= max_path; path++)
-+		for (i = 0; i < 84; i++)
-+			if (phydm_check_rates(dm, i)) {
-+
-+				if (dm->support_ic_type & PHYDM_COMMON_API_IC) {
-+				#ifdef PHYDM_COMMON_API_SUPPORT
-+				/*97F,8822B,92F,8821C*/
-+				gain_index = phydm_api_get_txagc(dm, path, i);
-+				#endif
-+				} else {
-+				/*92E*/
-+				#ifdef PHYDM_COMMON_API_NOT_SUPPORT
-+				gain_index = phydm_dtp_get_txagc(dm, path, i);
-+				#endif
-+				}
-+
-+				if (gain_index == 0xff) {
-+					min_gain_index = 0x20;
-+					PHYDM_DBG(dm, DBG_DYN_TXPWR, 
-+						  "Error Gain idx!! Rewite to: ((%d))\n",
-+						  min_gain_index);
-+					break;
-+				}
-+				PHYDM_DBG(dm, DBG_DYN_TXPWR,
-+					  "Support Rate: ((%d)) -> Gain idx: ((%d))\n",
-+					  i, gain_index);
-+				if (gain_index < min_gain_index)
-+					min_gain_index = gain_index;
-+			}
-+	return min_gain_index;
-+}
-+
-+void phydm_dynamic_tx_power_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i = 0;
-+
-+	dm->last_dtp_lvl = tx_high_pwr_level_normal;
-+	dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
-+
-+	switch (dm->ic_ip_series) {
-+	#ifdef BB_RAM_SUPPORT
-+	case PHYDM_IC_JGR3:
-+		dm->set_pwr_th[0] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL1;
-+		dm->set_pwr_th[1] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL2;
-+		dm->set_pwr_th[2] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL3;
-+		phydm_dtp_init_2nd(dm);
-+		break;
-+	#endif
-+	default:
-+		for (i = 0; i < 3; i++)
-+			dm->enhance_pwr_th[i] = 0xff;
-+
-+		dm->set_pwr_th[0] = TX_POWER_NEAR_FIELD_THRESH_LVL1;
-+		dm->set_pwr_th[1] = TX_POWER_NEAR_FIELD_THRESH_LVL2;
-+		dm->set_pwr_th[2] = 0xff;
-+		dm->min_power_index = phydm_search_min_power_index(dm);
-+		PHYDM_DBG(dm, DBG_DYN_TXPWR, "DTP init: Min Gain idx: ((%d))\n",
-+			  dm->min_power_index);
-+		break;
-+	}
-+}
-+
-+void phydm_noisy_enhance_hp_th(void *dm_void, u8 noisy_state)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (noisy_state == 0) {
-+		dm->enhance_pwr_th[0] = dm->set_pwr_th[0];
-+		dm->enhance_pwr_th[1] = dm->set_pwr_th[1];
-+		dm->enhance_pwr_th[2] = dm->set_pwr_th[2];
-+	} else {
-+		dm->enhance_pwr_th[0] = dm->set_pwr_th[0] + 8;
-+		dm->enhance_pwr_th[1] = dm->set_pwr_th[1] + 5;
-+		dm->enhance_pwr_th[2] = dm->set_pwr_th[2];
-+	}
-+	PHYDM_DBG(dm, DBG_DYN_TXPWR,
-+		  "DTP hp_enhance_th: Lv1_th =%d ,Lv2_th = %d ,Lv3_th = %d\n",
-+		  dm->enhance_pwr_th[0], dm->enhance_pwr_th[1],
-+		  dm->enhance_pwr_th[2]);
-+}
-+
-+u8 phydm_pwr_lvl_check(void *dm_void, u8 input_rssi, u8 last_pwr_lv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 th[DTP_POWER_LEVEL_SIZE];
-+	u8 i;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++)
-+			th[i] = dm->set_pwr_th[i];
-+
-+		PHYDM_DBG(dm, DBG_DYN_TXPWR,
-+			  "Ori-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n",
-+			  th[0], th[1], th[2]);
-+
-+		for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++) {
-+			if (i >= (last_pwr_lv))
-+				th[i] += DTP_FLOOR_UP_GAP;
-+		}
-+
-+		PHYDM_DBG(dm, DBG_DYN_TXPWR,
-+			  "Mod-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n",
-+			  th[0], th[1], th[2]);
-+	} else {
-+		for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++)
-+			th[i] = dm->enhance_pwr_th[i];
-+		for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++) {
-+			if (i >= (last_pwr_lv))
-+				th[i] += DTP_FLOOR_UP_GAP;
-+		}
-+	}
-+
-+	if (input_rssi >= th[2])
-+		return tx_high_pwr_level_level3;
-+	else if (input_rssi < th[2] && input_rssi >= th[1])
-+		return tx_high_pwr_level_level2;
-+	else if (input_rssi < th[1] && input_rssi >= th[0])
-+		return tx_high_pwr_level_level1;
-+	else
-+		return tx_high_pwr_level_normal;
-+}
-+
-+u8 phydm_pwr_lv_mapping(u8 tx_pwr_lv)
-+{
-+	if (tx_pwr_lv == tx_high_pwr_level_level3)
-+		return PHYDM_OFFSET_MINUS_11DB;
-+	else if (tx_pwr_lv == tx_high_pwr_level_level2)
-+		return PHYDM_OFFSET_MINUS_7DB;
-+	else if (tx_pwr_lv == tx_high_pwr_level_level1)
-+		return PHYDM_OFFSET_MINUS_3DB;
-+	else
-+		return PHYDM_OFFSET_ZERO;
-+}
-+
-+void phydm_dynamic_response_power(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 rpwr = 0;
-+
-+	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
-+		return;
-+
-+	if (dm->dynamic_tx_high_power_lvl == dm->last_dtp_lvl) {
-+		PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr not change\n");
-+		return;
-+	}
-+	PHYDM_DBG(dm, DBG_DYN_TXPWR,
-+		  "RespPwr update_DTP_lv: ((%d)) -> ((%d))\n", dm->last_dtp_lvl,
-+		  dm->dynamic_tx_high_power_lvl);
-+	dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl;
-+	rpwr = phydm_pwr_lv_mapping(dm->dynamic_tx_high_power_lvl);
-+	odm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT(19) | BIT(18),
-+			rpwr);
-+	PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr Set TxPwr: Lv (%d)\n",
-+		  dm->dynamic_tx_high_power_lvl);
-+}
-+
-+void phydm_dtp_fill_cmninfo(void *dm_void, u8 sta_id, u8 dtp_lvl)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
-+	struct dtp_info *dtp = NULL;
-+
-+	if (!is_sta_active(sta))
-+		return;
-+
-+	dtp = &sta->dtp_stat;
-+	dtp->dyn_tx_power = phydm_pwr_lv_mapping(dtp_lvl);
-+	PHYDM_DBG(dm, DBG_DYN_TXPWR,
-+		  "Fill cmninfo TxPwr: sta_id=(%d), macid=(%d), PwrLv (%d)\n",
-+		  sta_id, sta->mac_id, dtp->dyn_tx_power);
-+}
-+
-+void phydm_dtp_per_sta(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = NULL;
-+	struct dtp_info *dtp = NULL;
-+	struct rssi_info *rssi = NULL;
-+	struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
-+	u8 sta_cnt = 0;
-+	u8 i = 0;
-+	u8 curr_pwr_lv = 0;
-+	u8 last_pwr_lv = 0;
-+	u8 mac_id_cnt = 0;
-+	u64 macid_cur = 0;
-+	u64 macid_diff = 0;
-+	u64 macid_mask = 0;
-+
-+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
-+		sta = dm->phydm_sta_info[i];
-+		if (is_sta_active(sta)) {
-+			sta_cnt++;
-+
-+			dtp = &sta->dtp_stat;
-+			rssi = &sta->rssi_stat;
-+			macid_mask = (u64)BIT(sta->mac_id);
-+			if (!(bb_ctrl->macid_is_linked & macid_mask))
-+				dtp->sta_last_dtp_lvl = tx_high_pwr_level_normal;
-+
-+			last_pwr_lv = dtp->sta_last_dtp_lvl;
-+			curr_pwr_lv = phydm_pwr_lvl_check(dm, rssi->rssi,
-+							  last_pwr_lv);
-+			dtp->sta_tx_high_power_lvl = curr_pwr_lv;
-+			PHYDM_DBG(dm, DBG_DYN_TXPWR,
-+				  "STA_id=%d, MACID=%d , RSSI: %d , GetPwrLv: %d\n",
-+				  i, sta->mac_id, rssi->rssi, curr_pwr_lv);
-+
-+			bb_ctrl->macid_is_linked |= macid_mask;
-+			macid_cur |= macid_mask;
-+			PHYDM_DBG(dm, DBG_DYN_TXPWR,
-+				    "macid_is_linked: (0x%llx), macid_cur: (0x%llx)\n",
-+				    bb_ctrl->macid_is_linked, macid_cur);
-+
-+			if (curr_pwr_lv == last_pwr_lv && dtp->sta_is_alive) {
-+				dtp->sta_tx_high_power_lvl = last_pwr_lv;
-+				PHYDM_DBG(dm, DBG_DYN_TXPWR,
-+					  "DTP_lv not change: ((%d))\n",
-+					  curr_pwr_lv);
-+			} else {
-+				PHYDM_DBG(dm, DBG_DYN_TXPWR,
-+					  "DTP_lv update: ((%d)) -> ((%d))\n",
-+					  last_pwr_lv, curr_pwr_lv);
-+
-+				dtp->sta_last_dtp_lvl = curr_pwr_lv;
-+
-+				switch (dm->ic_ip_series) {
-+				#ifdef BB_RAM_SUPPORT
-+				case PHYDM_IC_JGR3:
-+					phydm_dtp_fill_cmninfo_2nd(dm, i, curr_pwr_lv);
-+					break;
-+				#endif
-+				default:
-+					phydm_dtp_fill_cmninfo(dm, i, curr_pwr_lv);
-+					break;
-+				}
-+				if(!dtp->sta_is_alive)
-+					dtp->sta_is_alive = true;
-+			}
-+
-+			if (sta_cnt == dm->number_linked_client)
-+				break;
-+		}
-+	}
-+
-+	macid_diff = bb_ctrl->macid_is_linked ^ macid_cur;
-+	if (macid_diff)
-+		bb_ctrl->macid_is_linked &= ~macid_diff;
-+	while (macid_diff) {
-+		if (macid_diff & 0x1)
-+			phydm_pwr_lv_ctrl(dm, mac_id_cnt, tx_high_pwr_level_normal);
-+		mac_id_cnt++;
-+		macid_diff >>= 1;
-+	}
-+}
-+
-+void odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 sta_id)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
-+	struct dtp_info *dtp = NULL;
-+
-+	if (!is_sta_active(sta))
-+		return;
-+	dtp = &sta->dtp_stat;
-+
-+	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
-+		return;
-+
-+	if (dm->fill_desc_dyntxpwr)
-+		dm->fill_desc_dyntxpwr(dm, desc, dtp->dyn_tx_power);
-+	else
-+		PHYDM_DBG(dm, DBG_DYN_TXPWR,
-+			  "%s: fill_desc_dyntxpwr is null!\n", __func__);
-+
-+	if (dtp->last_tx_power != dtp->dyn_tx_power) {
-+		PHYDM_DBG(dm, DBG_DYN_TXPWR,
-+			  "%s: last_offset=%d, txpwr_offset=%d\n", __func__,
-+			  dtp->last_tx_power, dtp->dyn_tx_power);
-+		dtp->last_tx_power = dtp->dyn_tx_power;
-+	}
-+}
-+
-+void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,
-+			     u32 *_out_len)
-+{
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[7] = {0};
-+	u8 set_pwr_th1, set_pwr_th2, set_pwr_th3;
-+	u8 i = 0;
-+	#ifdef BB_RAM_SUPPORT
-+	s8 pwr_ofst_tmp = 0x0;
-+	#endif
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Set DTP threhosld: {1} {Lv1_th} {Lv2_th} {Lv3_th}\n");
-+		#ifdef BB_RAM_SUPPORT
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Set pwr_tx_offset: {2} {0:reg 1:macid} {en} {offset 0/1} {0:-, 1:+} {Pwr Offset} {macid}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Read pwr_tx_offset : {3} {0:reg 1:macid} {macid(0~63), 255:all}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Reset all ram pwr_tx_offset : {4}\n");
-+		#endif
-+	} else {
-+		for (i = 0; i < 7; i++) {
-+			if (input[i + 1])
-+				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
-+					     &var1[i]);
-+		}
-+		switch (var1[0]) {
-+		case 1:
-+			for (i = 0; i < 3; i++) {
-+				if (var1[i] == 0 || var1[i] > 100)
-+					dm->set_pwr_th[i] = 0xff;
-+				else
-+					dm->set_pwr_th[i] = (u8)var1[1 + i];
-+			}
-+
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "DTP_TH[0:2] = {%d, %d, %d}\n",
-+				 dm->set_pwr_th[0], dm->set_pwr_th[1],
-+				 dm->set_pwr_th[2]);
-+			break;
-+		#ifdef BB_RAM_SUPPORT
-+		case 2:
-+			if ((boolean)var1[4])
-+				pwr_ofst_tmp = (s8)var1[5];
-+			else
-+				pwr_ofst_tmp = 0x0 - (s8)var1[5];
-+
-+			if ((boolean)var1[1])
-+				phydm_wt_ram_pwr(dm, (u8)var1[6],
-+						 (boolean)var1[3],
-+						 (boolean)var1[2],
-+						 pwr_ofst_tmp);
-+			else
-+				phydm_wt_reg_pwr(dm, (boolean)var1[3],
-+						 (boolean)var1[2],
-+						 pwr_ofst_tmp);
-+			break;
-+		case 3:
-+			if ((boolean)var1[1]) {
-+				if ((u8)var1[2] == 0xff)
-+					for (i = 0; i < 64; i++)
-+						phydm_rd_ram_pwr(dm, i, &used,
-+								 output,
-+								 &out_len);
-+				else
-+					phydm_rd_ram_pwr(dm, (u8)var1[2], &used,
-+							 output, &out_len);
-+			} else {
-+				phydm_rd_reg_pwr(dm, &used, output, &out_len);
-+			}
-+			break;
-+		case 4:
-+			phydm_rst_ram_pwr(dm);
-+			break;
-+		#endif
-+		}
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_dynamic_tx_power(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = NULL;
-+	u8 i = 0;
-+
-+	u8 rssi_min = dm->rssi_min;
-+	u8 rssi_tmp = 0;
-+
-+	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
-+		return;
-+
-+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
-+		PHYDM_DBG(dm, DBG_DYN_TXPWR,
-+			  "[%s] RSSI_min = %d, Noisy_dec = %d\n", __func__,
-+			  rssi_min, dm->noisy_decision);
-+		phydm_noisy_enhance_hp_th(dm, dm->noisy_decision);
-+		/* Response Power */
-+		dm->dynamic_tx_high_power_lvl = phydm_pwr_lvl_check(dm,
-+								    rssi_min,
-+							    dm->last_dtp_lvl);
-+		phydm_dynamic_response_power(dm);
-+	}
-+	/* Per STA Tx power */
-+	phydm_dtp_per_sta(dm);
-+}
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+void phydm_dynamic_tx_power_init_win(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	void *adapter = dm->adapter;
-+	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
-+
-+	mgnt_info->bDynamicTxPowerEnable = false;
-+	#if DEV_BUS_TYPE == RT_USB_INTERFACE
-+	if (RT_GetInterfaceSelection((PADAPTER)adapter) ==
-+	    INTF_SEL1_USB_High_Power) {
-+		mgnt_info->bDynamicTxPowerEnable = true;
-+	}
-+	#endif
-+
-+	hal_data->LastDTPLvl = tx_high_pwr_level_normal;
-+	hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
-+
-+	PHYDM_DBG(dm, DBG_DYN_TXPWR, "[%s] DTP=%d\n", __func__,
-+		  mgnt_info->bDynamicTxPowerEnable);
-+}
-+
-+void phydm_dynamic_tx_power_win(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
-+		return;
-+
-+	#if (RTL8814A_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8814A)
-+		odm_dynamic_tx_power_8814a(dm);
-+	#endif
-+
-+	#if (RTL8821A_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8821) {
-+		void *adapter = dm->adapter;
-+		PMGNT_INFO mgnt_info = GetDefaultMgntInfo((PADAPTER)adapter);
-+
-+		if (mgnt_info->RegRspPwr == 1) {
-+			if (dm->rssi_min > 60) {
-+				/*Resp TXAGC offset = -3dB*/
-+				odm_set_mac_reg(dm, R_0x6d8, 0x1C0000, 1);
-+			} else if (dm->rssi_min < 55) {
-+				/*Resp TXAGC offset = 0dB*/
-+				odm_set_mac_reg(dm, R_0x6d8, 0x1C0000, 0);
-+			}
-+		}
-+	}
-+	#endif
-+}
-+#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
-+#endif /* @#ifdef CONFIG_DYNAMIC_TX_TWR */
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_dynamictxpower.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_dynamictxpower.h
-new file mode 100644
-index 000000000000..88be431f421b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_dynamictxpower.h
-@@ -0,0 +1,142 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDMDYNAMICTXPOWER_H__
-+#define __PHYDMDYNAMICTXPOWER_H__
-+
-+#ifdef CONFIG_DYNAMIC_TX_TWR
-+/* @============================================================
-+ *  Definition
-+ * ============================================================
-+ */
-+
-+/* 2020.6.23, Let gain_idx be initialized to 0 for linux compile warning*/
-+#define DYNAMIC_TXPWR_VERSION "2.1"
-+
-+#define DTP_POWER_LEVEL_SIZE 3
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
-+#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
-+#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
-+#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
-+#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 80
-+#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 63
-+#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 55
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90
-+#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85
-+#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 80
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90
-+#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85
-+#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 80
-+#endif
-+
-+#define tx_high_pwr_level_normal 0
-+#define tx_high_pwr_level_level1 1
-+#define tx_high_pwr_level_level2 2
-+#define tx_high_pwr_level_level3 3
-+#define tx_high_pwr_level_unchange 4
-+#define DTP_FLOOR_UP_GAP 3
-+
-+/* @============================================================
-+ * enumrate
-+ * ============================================================
-+ */
-+enum phydm_dtp_power_offset {
-+	PHYDM_OFFSET_ZERO = 0,
-+	PHYDM_OFFSET_MINUS_3DB = 1,
-+	PHYDM_OFFSET_MINUS_7DB = 2,
-+	PHYDM_OFFSET_MINUS_11DB = 3,
-+	PHYDM_OFFSET_ADD_3DB = 4,
-+	PHYDM_OFFSET_ADD_6DB = 5
-+};
-+
-+enum phydm_dtp_power_offset_2nd {
-+	PHYDM_2ND_OFFSET_ZERO = 0,
-+	PHYDM_2ND_OFFSET_MINUS_3DB = 1,
-+	PHYDM_2ND_OFFSET_MINUS_7DB = 2,
-+	PHYDM_2ND_OFFSET_MINUS_11DB = 3
-+};
-+
-+enum phydm_dtp_power_offset_bbram {
-+	/*@ HW min use 1dB*/
-+	PHYDM_BBRAM_OFFSET_ZERO = 0,
-+	PHYDM_BBRAM_OFFSET_MINUS_3DB = -3,
-+	PHYDM_BBRAM_OFFSET_MINUS_7DB = -7,
-+	PHYDM_BBRAM_OFFSET_MINUS_11DB = -11
-+};
-+
-+enum phydm_dtp_power_pkt_type {
-+	RAM_PWR_OFST0		= 0,
-+	RAM_PWR_OFST1		= 1,
-+	REG_PWR_OFST0		= 2,
-+	REG_PWR_OFST1		= 3
-+};
-+
-+/* @============================================================
-+ *  structure
-+ * ============================================================
-+ */
-+
-+/* @============================================================
-+ *  Function Prototype
-+ * ============================================================
-+ */
-+
-+extern void
-+odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 mac_id);
-+
-+void phydm_dynamic_tx_power(void *dm_void);
-+
-+void phydm_dynamic_tx_power_init(void *dm_void);
-+
-+void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,
-+			     u32 *_out_len);
-+
-+void phydm_rd_reg_pwr(void *dm_void, u32 *_used, char *output, u32 *_out_len);
-+
-+void phydm_wt_reg_pwr(void *dm_void, boolean is_ofst1, boolean pwr_ofst_en,
-+            		     s8 pwr_ofst);
-+
-+void phydm_wt_ram_pwr(void *dm_void, u8 macid, boolean is_ofst1, 
-+		             boolean pwr_ofst_en, s8 pwr_ofst);
-+
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void odm_dynamic_tx_power_win(void *dm_void);
-+#endif
-+
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_features.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_features.h
-new file mode 100644
-index 000000000000..bbbc9edabc8d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_features.h
-@@ -0,0 +1,82 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_FEATURES_H__
-+#define __PHYDM_FEATURES_H__
-+
-+#define CONFIG_RUN_IN_DRV
-+#define ODM_DC_CANCELLATION_SUPPORT		(ODM_RTL8188F | \
-+						 ODM_RTL8710B | \
-+						 ODM_RTL8192F | \
-+						 ODM_RTL8821C | \
-+						 ODM_RTL8822B | \
-+						 ODM_RTL8721D | \
-+						 ODM_RTL8723D | \
-+						 ODM_RTL8710C)
-+#define ODM_RECEIVER_BLOCKING_SUPPORT	(ODM_RTL8188E | ODM_RTL8192E)
-+#define ODM_DYM_BW_INDICATION_SUPPORT	(ODM_RTL8821C | \
-+					 ODM_RTL8822B | \
-+					 ODM_RTL8822C)
-+
-+/*@20170103 YuChen add for FW API*/
-+#define PHYDM_FW_API_ENABLE_8822B		1
-+#define PHYDM_FW_API_FUNC_ENABLE_8822B		1
-+#define PHYDM_FW_API_ENABLE_8821C		1
-+#define PHYDM_FW_API_FUNC_ENABLE_8821C		1
-+#define PHYDM_FW_API_ENABLE_8195B		1
-+#define PHYDM_FW_API_FUNC_ENABLE_8195B		1
-+#define PHYDM_FW_API_ENABLE_8198F		1
-+#define PHYDM_FW_API_FUNC_ENABLE_8198F		1
-+#define PHYDM_FW_API_ENABLE_8822C 1
-+#define PHYDM_FW_API_FUNC_ENABLE_8822C 1
-+#define PHYDM_FW_API_ENABLE_8814B 1
-+#define PHYDM_FW_API_FUNC_ENABLE_8814B 1
-+#define PHYDM_FW_API_ENABLE_8812F 1
-+#define PHYDM_FW_API_FUNC_ENABLE_8812F 1
-+#define PHYDM_FW_API_ENABLE_8197G 1
-+#define PHYDM_FW_API_FUNC_ENABLE_8197G 1
-+#define PHYDM_FW_API_ENABLE_8723F 1
-+#define PHYDM_FW_API_FUNC_ENABLE_8723F 1
-+
-+#define CONFIG_POWERSAVING 0
-+
-+#ifdef BEAMFORMING_SUPPORT
-+#if (BEAMFORMING_SUPPORT)
-+	#define PHYDM_BEAMFORMING_SUPPORT
-+#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	#include	"phydm_features_win.h"
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	#include	"phydm_features_ce.h"
-+	/*@#include	"phydm_features_ce2_kernel.h"*/
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	#include	"phydm_features_ap.h"
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+	#include	"phydm_features_iot.h"
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_features_ap.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_features_ap.h
-new file mode 100644
-index 000000000000..38a0eebc993a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_features_ap.h
-@@ -0,0 +1,227 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef	__PHYDM_FEATURES_AP_H__
-+#define __PHYDM_FEATURES_AP_H__
-+
-+#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
-+	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
-+	RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\
-+	RTL8197G_SUPPORT || RTL8723F_SUPPORT)
-+	#define PHYDM_LA_MODE_SUPPORT			1
-+#else
-+	#define PHYDM_LA_MODE_SUPPORT			0
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
-+	RTL8192F_SUPPORT)
-+	#define DYN_ANT_WEIGHTING_SUPPORT
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8198F_SUPPORT || RTL8814B_SUPPORT ||\
-+     RTL8197G_SUPPORT || RTL8812F_SUPPORT || RTL8723F_SUPPORT)
-+	#define FAHM_SUPPORT
-+#endif
-+
-+#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT || RTL8723F_SUPPORT)
-+	#define IFS_CLM_SUPPORT
-+#endif
-+	#define NHM_SUPPORT
-+	#define CLM_SUPPORT
-+
-+#if (RTL8812F_SUPPORT)
-+	/*#define PHYDM_PHYSTAUS_AUTO_SWITCH*/
-+#endif
-+
-+#if (RTL8197F_SUPPORT)
-+	/*#define PHYDM_TDMA_DIG_SUPPORT*/
-+#endif
-+
-+#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
-+	RTL8197G_SUPPORT || RTL8723F_SUPPORT)
-+	#define PHYDM_TDMA_DIG_SUPPORT 1
-+	#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	#define IS_USE_NEW_TDMA /*new tdma dig test*/
-+	#endif
-+#endif
-+
-+#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT ||\
-+	RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
-+	#define PHYDM_LNA_SAT_CHK_SUPPORT
-+	#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+
-+		#if (RTL8197F_SUPPORT)
-+		/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
-+		#endif
-+
-+		#if (RTL8822B_SUPPORT)
-+		/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
-+		#endif
-+
-+		#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
-+		#define PHYDM_LNA_SAT_CHK_TYPE1
-+		#endif
-+	#endif
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+	/*#define PHYDM_POWER_TRAINING_SUPPORT*/
-+#endif
-+
-+#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
-+	RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
-+	#define PHYDM_PMAC_TX_SETTING_SUPPORT
-+#endif
-+
-+#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
-+	RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
-+	#define PHYDM_MP_SUPPORT
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+	#define PHYDM_TXA_CALIBRATION
-+#endif
-+
-+#if (RTL8188E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
-+	#define	PHYDM_PRIMARY_CCA
-+#endif
-+
-+#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
-+	RTL8822B_SUPPORT || RTL8192F_SUPPORT)
-+	#define	PHYDM_DC_CANCELLATION
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
-+	#define	CONFIG_ADAPTIVE_SOML
-+#endif
-+
-+#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
-+	RTL8192E_SUPPORT || RTL8723B_SUPPORT)
-+	/*#define	CONFIG_RA_FW_DBG_CODE*/
-+#endif
-+
-+#if (RTL8192F_SUPPORT == 1)
-+	/*#define	CONFIG_8912F_SPUR_CALIBRATION*/
-+#endif
-+
-+#if (RTL8822B_SUPPORT == 1)
-+	/* #define	CONFIG_8822B_SPUR_CALIBRATION */
-+#endif
-+
-+#if (RTL8197G_SUPPORT)
-+	#define CONFIG_DIRECTIONAL_BF
-+#endif
-+
-+#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT)
-+	#define CONFIG_DYNAMIC_TX_TWR
-+#endif
-+
-+#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT)
-+	#define PHYDM_HW_IGI
-+#endif
-+
-+#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT)
-+	#define CONFIG_DYNAMIC_TXCOLLISION_TH
-+#endif
-+
-+/*#define	CONFIG_PSD_TOOL*/
-+#define PHYDM_SUPPORT_CCKPD
-+#define PHYDM_SUPPORT_ADAPTIVITY
-+/*#define	CONFIG_PATH_DIVERSITY*/
-+/*#define	CONFIG_RA_DYNAMIC_RTY_LIMIT*/
-+/*#define	CONFIG_RA_DYNAMIC_RATE_ID*/
-+#define	CONFIG_BB_TXBF_API
-+/*#define	ODM_CONFIG_BT_COEXIST*/
-+#define	PHYDM_SUPPORT_RSSI_MONITOR
-+#if !defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION)
-+	#define CONFIG_PHYDM_DEBUG_FUNCTION
-+#endif
-+
-+/* [ Configure Antenna Diversity ] */
-+#if (RTL8188F_SUPPORT)
-+	#ifdef CONFIG_ANTENNA_DIVERSITY
-+		#define CONFIG_PHYDM_ANTENNA_DIVERSITY
-+		#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+	#endif
-+#endif
-+
-+#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) || defined(CONFIG_RTL_8197F_ANT_SWITCH) || defined(CONFIG_RTL_8197G_ANT_SWITCH)
-+	#define CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	#define ODM_EVM_ENHANCE_ANTDIV
-+	/*#define SKIP_EVM_ANTDIV_TRAINING_PATCH*/
-+
-+	/*----------*/
-+	#ifdef CONFIG_NO_2G_DIVERSITY_8197F
-+		#define CONFIG_NO_2G_DIVERSITY
-+	#elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197F)
-+		#define CONFIG_2G_CGCS_RX_DIVERSITY
-+	#elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197F)
-+		#define CONFIG_2G_CG_TRX_DIVERSITY
-+	#endif
-+
-+	/*----------*/
-+	#ifdef CONFIG_NO_2G_DIVERSITY_8197G
-+		#define CONFIG_NO_2G_DIVERSITY
-+	#elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197G)
-+		#define CONFIG_2G_CGCS_RX_DIVERSITY
-+	#elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197G)
-+		#define CONFIG_2G_CG_TRX_DIVERSITY
-+	#endif
-+
-+	#if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
-+		#define CONFIG_NO_2G_DIVERSITY
-+	#endif
-+
-+	#ifdef CONFIG_NO_5G_DIVERSITY_8881A
-+		#define CONFIG_NO_5G_DIVERSITY
-+	#elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A)
-+		#define CONFIG_5G_CGCS_RX_DIVERSITY
-+	#elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A)
-+		#define CONFIG_5G_CG_TRX_DIVERSITY
-+	#elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)
-+		#define CONFIG_2G5G_CG_TRX_DIVERSITY
-+	#endif
-+	#if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
-+		#define CONFIG_NO_5G_DIVERSITY
-+	#endif
-+	/*----------*/
-+	#if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
-+		#define CONFIG_NOT_SUPPORT_ANTDIV
-+	#elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
-+		#define CONFIG_2G_SUPPORT_ANTDIV
-+	#elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY))
-+		#define CONFIG_5G_SUPPORT_ANTDIV
-+	#elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY))
-+			#define CONFIG_2G5G_SUPPORT_ANTDIV
-+	#endif
-+		/*----------*/
-+#endif /*Antenna Diveristy*/
-+
-+/*[SmartAntenna]*/
-+/*#define	CONFIG_SMART_ANTENNA*/
-+#ifdef CONFIG_SMART_ANTENNA
-+	/*#define	CONFIG_CUMITEK_SMART_ANTENNA*/
-+#endif
-+#define CFG_DIG_DAMPING_CHK
-+/* --------------------------------------------------*/
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
-+	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
-+	     RTL8814B_SUPPORT || RTL8812F_SUPPORT)
-+		#define	DRIVER_BEAMFORMING_VERSION2
-+	#endif
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_features_ce.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_features_ce.h
-new file mode 100644
-index 000000000000..5c11753e1bfa
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_features_ce.h
-@@ -0,0 +1,245 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_FEATURES_CE_H__
-+#define __PHYDM_FEATURES_CE_H__
-+
-+#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
-+	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
-+	RTL8822C_SUPPORT || RTL8723F_SUPPORT)
-+	#define PHYDM_LA_MODE_SUPPORT			1
-+#else
-+	#define PHYDM_LA_MODE_SUPPORT			0
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
-+	RTL8192F_SUPPORT)
-+	#define DYN_ANT_WEIGHTING_SUPPORT
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8822C_SUPPORT ||\
-+	RTL8814B_SUPPORT || RTL8723F_SUPPORT)
-+	#define FAHM_SUPPORT
-+#endif
-+
-+#if (RTL8822C_SUPPORT || RTL8723F_SUPPORT)
-+	#define IFS_CLM_SUPPORT
-+#endif
-+	#define NHM_SUPPORT
-+	#define CLM_SUPPORT
-+
-+#if (RTL8822C_SUPPORT)
-+	#define NHM_DYM_PW_TH_SUPPORT
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	/*@#define PHYDM_PHYSTAUS_AUTO_SWITCH*/
-+#endif
-+
-+/*@#define PHYDM_TDMA_DIG_SUPPORT*/
-+
-+#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT ||\
-+	RTL8822C_SUPPORT || RTL8723D_SUPPORT )
-+	#ifdef CONFIG_TDMADIG
-+	#define PHYDM_TDMA_DIG_SUPPORT
-+	#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	#define IS_USE_NEW_TDMA /*new tdma dig test*/
-+	#endif
-+	#endif
-+#endif
-+
-+#if (RTL8814B_SUPPORT)
-+	/*@#define PHYDM_TDMA_DIG_SUPPORT*/
-+	#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	/*@#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/
-+	#endif
-+#endif
-+
-+#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT)
-+	/*@#define PHYDM_LNA_SAT_CHK_SUPPORT*/
-+	#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+
-+		#if (RTL8197F_SUPPORT)
-+		/*@#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
-+		#endif
-+
-+		#if (RTL8822B_SUPPORT)
-+		/*@#define PHYDM_LNA_SAT_CHK_TYPE2*/
-+		#endif
-+
-+		#if (RTL8814B_SUPPORT)
-+		/*@#define PHYDM_LNA_SAT_CHK_TYPE1*/
-+		#endif
-+	#endif
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8723D_SUPPORT)
-+	#define PHYDM_POWER_TRAINING_SUPPORT
-+#endif
-+
-+#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
-+	#define PHYDM_PMAC_TX_SETTING_SUPPORT
-+#endif
-+
-+#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
-+	#define PHYDM_MP_SUPPORT
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	#define	PHYDM_CCK_RX_PATHDIV_SUPPORT
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+	#define PHYDM_TXA_CALIBRATION
-+#endif
-+
-+#if (RTL8188E_SUPPORT)
-+	#define	PHYDM_PRIMARY_CCA
-+#endif
-+
-+#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
-+	RTL8822B_SUPPORT || RTL8192F_SUPPORT)
-+	#define	PHYDM_DC_CANCELLATION
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
-+	#define	CONFIG_ADAPTIVE_SOML
-+#endif
-+
-+#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
-+	#define	CONFIG_RECEIVER_BLOCKING
-+#endif
-+
-+#if (RTL8821C_SUPPORT || RTL8822C_SUPPORT || RTL8822B_SUPPORT)
-+	#define CONFIG_BW_INDICATION
-+#endif
-+
-+#if (RTL8192F_SUPPORT)
-+	/*#define	CONFIG_8912F_SPUR_CALIBRATION*/
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+	#define	CONFIG_8822B_SPUR_CALIBRATION
-+#endif
-+
-+#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
-+#define CONFIG_DYNAMIC_TX_TWR
-+#endif
-+#if (RTL8822C_SUPPORT)
-+#define PHYDM_HW_IGI
-+#endif
-+#define PHYDM_SUPPORT_CCKPD
-+#define PHYDM_SUPPORT_ADAPTIVITY
-+
-+/*@Antenna Diversity*/
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	#define CONFIG_PHYDM_ANTENNA_DIVERSITY
-+
-+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+
-+		#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\
-+		     RTL8188F_SUPPORT || RTL8821C_SUPPORT ||\
-+		     RTL8723D_SUPPORT)
-+			#define	CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+		#endif
-+
-+		#if (RTL8821A_SUPPORT)
-+			/*@#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
-+		#endif
-+
-+		#if (RTL8822B_SUPPORT)
-+			/*@#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
-+		#endif
-+
-+	#endif
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8192F_SUPPORT)
-+	#define CONFIG_PATH_DIVERSITY
-+#endif
-+
-+/*@[SmartAntenna]*/
-+/*@#define	CONFIG_SMART_ANTENNA*/
-+#ifdef CONFIG_SMART_ANTENNA
-+	/*@#define	CONFIG_CUMITEK_SMART_ANTENNA*/
-+#endif
-+/* @--------------------------------------------------*/
-+
-+#ifdef CONFIG_DFS_MASTER
-+	#define CONFIG_PHYDM_DFS_MASTER
-+#endif
-+
-+#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
-+	RTL8192E_SUPPORT || RTL8723B_SUPPORT)
-+	/*@#define	CONFIG_RA_FW_DBG_CODE*/
-+#endif
-+
-+#define	CONFIG_PSD_TOOL
-+/*@#define	CONFIG_ANT_DETECTION*/
-+/*@#define	CONFIG_RA_DYNAMIC_RTY_LIMIT*/
-+#define	CONFIG_BB_TXBF_API
-+#define	CONFIG_PHYDM_DEBUG_FUNCTION
-+
-+#ifdef CONFIG_BT_COEXIST
-+	#define	ODM_CONFIG_BT_COEXIST
-+#endif
-+#define	PHYDM_SUPPORT_RSSI_MONITOR
-+#define	PHYDM_AUTO_DEGBUG
-+#define CFG_DIG_DAMPING_CHK
-+
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8192E_SUPPORT ||\
-+	     RTL8814A_SUPPORT || RTL8881A_SUPPORT)
-+		#define	PHYDM_BEAMFORMING_VERSION1
-+	#endif
-+	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
-+	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
-+	     RTL8822C_SUPPORT || RTL8814B_SUPPORT)
-+		#define	DRIVER_BEAMFORMING_VERSION2
-+	#endif
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT)
-+	#ifdef CONFIG_MCC_MODE
-+	#define	CONFIG_MCC_DM
-+	#endif
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+	#ifdef CONFIG_DYNAMIC_BYPASS_MODE
-+	#define	CONFIG_DYNAMIC_BYPASS
-+	#endif
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)
-+	#define CONFIG_DIRECTIONAL_BF
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	#define CONFIG_MU_RSOML
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_features_ce2_kernel.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_features_ce2_kernel.h
-new file mode 100644
-index 000000000000..c206ea605892
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_features_ce2_kernel.h
-@@ -0,0 +1,84 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_FEATURES_CE_H__
-+#define __PHYDM_FEATURES_CE_H__
-+
-+#define PHYDM_LA_MODE_SUPPORT			0
-+
-+#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
-+	RTL8192F_SUPPORT)
-+	#define DYN_ANT_WEIGHTING_SUPPORT
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
-+	#define FAHM_SUPPORT
-+#endif
-+	#define NHM_SUPPORT
-+	#define CLM_SUPPORT
-+
-+#if (RTL8822B_SUPPORT)
-+	#define PHYDM_TXA_CALIBRATION
-+#endif
-+
-+#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
-+	RTL8822B_SUPPORT || RTL8192F_SUPPORT)
-+	#define	PHYDM_DC_CANCELLATION
-+#endif
-+
-+#if (RTL8192F_SUPPORT == 1)
-+	/*#define	CONFIG_8912F_SPUR_CALIBRATION*/
-+#endif
-+
-+#if (RTL8822B_SUPPORT == 1)
-+	/* #define	CONFIG_8822B_SPUR_CALIBRATION */
-+#endif
-+
-+#define PHYDM_SUPPORT_CCKPD
-+#define PHYDM_SUPPORT_ADAPTIVITY
-+
-+#ifdef CONFIG_DFS_MASTER
-+	#define CONFIG_PHYDM_DFS_MASTER
-+#endif
-+
-+#define	CONFIG_BB_TXBF_API
-+#define	CONFIG_PHYDM_DEBUG_FUNCTION
-+
-+#ifdef CONFIG_BT_COEXIST
-+	#define	ODM_CONFIG_BT_COEXIST
-+#endif
-+#define	PHYDM_SUPPORT_RSSI_MONITOR
-+#define CFG_DIG_DAMPING_CHK
-+
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
-+	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
-+	     RTL8822C_SUPPORT || RTL8814B_SUPPORT)
-+		#define	DRIVER_BEAMFORMING_VERSION2
-+	#endif
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_features_iot.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_features_iot.h
-new file mode 100644
-index 000000000000..ce8793eb6ae4
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_features_iot.h
-@@ -0,0 +1,177 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef	__PHYDM_FEATURES_IOT_H__
-+#define __PHYDM_FEATURES_IOT_H__
-+
-+#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
-+	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
-+	RTL8822C_SUPPORT || RTL8195B_SUPPORT)
-+	#define PHYDM_LA_MODE_SUPPORT			1
-+#else
-+	#define PHYDM_LA_MODE_SUPPORT			0
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
-+	RTL8192F_SUPPORT)
-+	#define DYN_ANT_WEIGHTING_SUPPORT
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
-+	#define FAHM_SUPPORT
-+#endif
-+	#define NHM_SUPPORT
-+	#define CLM_SUPPORT
-+
-+/*#define PHYDM_TDMA_DIG_SUPPORT*/
-+
-+#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT)
-+	/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
-+	#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+		#if (RTL8197F_SUPPORT)
-+		/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
-+		#endif
-+
-+		#if (RTL8822B_SUPPORT)
-+		/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
-+		#endif
-+	#endif
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
-+	#define PHYDM_POWER_TRAINING_SUPPORT
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	/* #define PHYDM_PMAC_TX_SETTING_SUPPORT */
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	/* #define PHYDM_MP_SUPPORT */
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+	#define PHYDM_TXA_CALIBRATION
-+#endif
-+
-+#if (RTL8188E_SUPPORT)
-+	#define	PHYDM_PRIMARY_CCA
-+#endif
-+
-+#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
-+	RTL8822B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
-+	#define	PHYDM_DC_CANCELLATION
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
-+	#define	CONFIG_ADAPTIVE_SOML
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+	/*#define	CONFIG_DYNAMIC_RX_PATH*/
-+#endif
-+
-+#if (RTL8822B_SUPPORT == 1)
-+	/* #define	CONFIG_8822B_SPUR_CALIBRATION */
-+#endif
-+
-+#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
-+	#define	CONFIG_RECEIVER_BLOCKING
-+#endif
-+
-+#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
-+#define CONFIG_DYNAMIC_TX_TWR
-+#endif
-+#define PHYDM_SUPPORT_CCKPD
-+#define PHYDM_SUPPORT_ADAPTIVITY
-+
-+/*Antenna Diversity*/
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	#define CONFIG_PHYDM_ANTENNA_DIVERSITY
-+
-+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+
-+		#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\
-+		     RTL8188F_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)
-+			#define	CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+		#endif
-+		
-+		#if (RTL8710C_SUPPORT)
-+			//#define	CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+		#endif
-+		
-+		#if (RTL8821A_SUPPORT)
-+			/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
-+		#endif
-+
-+		#if (RTL8822B_SUPPORT)
-+			/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
-+		#endif
-+	#endif
-+#endif
-+
-+/*[SmartAntenna]*/
-+/*#define	CONFIG_SMART_ANTENNA*/
-+#ifdef CONFIG_SMART_ANTENNA
-+	/*#define	CONFIG_CUMITEK_SMART_ANTENNA*/
-+#endif
-+/* --------------------------------------------------*/
-+
-+#ifdef CONFIG_DFS_MASTER
-+	#define CONFIG_PHYDM_DFS_MASTER
-+#endif
-+
-+#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
-+	RTL8192E_SUPPORT || RTL8723B_SUPPORT)
-+	/*#define	CONFIG_RA_FW_DBG_CODE*/
-+#endif
-+
-+#define	CONFIG_PSD_TOOL
-+/*#define	CONFIG_RA_DBG_CMD*/
-+/*#define	CONFIG_ANT_DETECTION*/
-+/*#define	CONFIG_PATH_DIVERSITY*/
-+/*#define	CONFIG_RA_DYNAMIC_RTY_LIMIT*/
-+//#define	CONFIG_BB_TXBF_API
-+#if DBG
-+#define	CONFIG_PHYDM_DEBUG_FUNCTION
-+#endif
-+
-+#ifdef CONFIG_BT_COEXIST
-+	#define	ODM_CONFIG_BT_COEXIST
-+#endif
-+#define	PHYDM_SUPPORT_RSSI_MONITOR
-+/*#define	PHYDM_AUTO_DEGBUG*/
-+#define CFG_DIG_DAMPING_CHK
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
-+	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
-+	     RTL8822C_SUPPORT || RTL8814B_SUPPORT)
-+		#define	DRIVER_BEAMFORMING_VERSION2
-+		#define	CONFIG_BB_TXBF_API
-+	#endif
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_features_win.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_features_win.h
-new file mode 100644
-index 000000000000..824699e6200c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_features_win.h
-@@ -0,0 +1,215 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef	__PHYDM_FEATURES_WIN_H__
-+#define __PHYDM_FEATURES_WIN_H__
-+
-+#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
-+	RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
-+	RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
-+	#define PHYDM_LA_MODE_SUPPORT			1
-+#else
-+	#define PHYDM_LA_MODE_SUPPORT			0
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
-+	RTL8192F_SUPPORT)
-+	#define DYN_ANT_WEIGHTING_SUPPORT
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8822C_SUPPORT ||\
-+     RTL8814B_SUPPORT || RTL8723F_SUPPORT)
-+	#define FAHM_SUPPORT
-+#endif
-+
-+#if (RTL8822C_SUPPORT || RTL8723F_SUPPORT)
-+	#define IFS_CLM_SUPPORT
-+#endif
-+	#define NHM_SUPPORT
-+	#define CLM_SUPPORT
-+
-+#if (RTL8822C_SUPPORT)
-+	#define NHM_DYM_PW_TH_SUPPORT
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	#define PHYDM_PHYSTAUS_AUTO_SWITCH
-+#endif
-+
-+/*#define PHYDM_TDMA_DIG_SUPPORT*/
-+
-+#if (RTL8814B_SUPPORT)
-+	/*#define PHYDM_TDMA_DIG_SUPPORT*/
-+	#ifdef PHYDM_TDMA_DIG_SUPPORT
-+	/*#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/
-+	#endif
-+#endif
-+
-+#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT)
-+	/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
-+	#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+
-+		#if (RTL8197F_SUPPORT)
-+		/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
-+		#endif
-+
-+		#if (RTL8822B_SUPPORT)
-+		/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
-+		#endif
-+
-+		#if (RTL8814B_SUPPORT)
-+		/*#define PHYDM_LNA_SAT_CHK_TYPE1*/
-+		#endif
-+	#endif
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8710B_SUPPORT || RTL8723D_SUPPORT ||\
-+	RTL8192F_SUPPORT)
-+	#define	PHYDM_POWER_TRAINING_SUPPORT
-+#endif
-+
-+#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
-+	#define	PHYDM_PMAC_TX_SETTING_SUPPORT
-+#endif
-+
-+#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
-+	#define	PHYDM_MP_SUPPORT
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	#define	PHYDM_CCK_RX_PATHDIV_SUPPORT
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+	#define	PHYDM_TXA_CALIBRATION
-+#endif
-+
-+#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
-+	#define	PHYDM_PRIMARY_CCA
-+#endif
-+
-+#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
-+	RTL8822B_SUPPORT || RTL8192F_SUPPORT)
-+	#define	PHYDM_DC_CANCELLATION
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
-+	#define	CONFIG_ADAPTIVE_SOML
-+#endif
-+
-+#if (RTL8192F_SUPPORT)
-+	#define	CONFIG_8912F_SPUR_CALIBRATION
-+#endif
-+
-+/*Antenna Diversity*/
-+#define	CONFIG_PHYDM_ANTENNA_DIVERSITY
-+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+
-+	#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT || RTL8188F_SUPPORT ||\
-+	     RTL8821C_SUPPORT || RTL8723D_SUPPORT)
-+		#define	CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+	#endif
-+
-+	#if (RTL8822B_SUPPORT)
-+		/*#define	ODM_EVM_ENHANCE_ANTDIV*/
-+		/*#define	CONFIG_2T3R_ANTENNA*/
-+		/*#define	CONFIG_2T4R_ANTENNA*/
-+	#endif
-+
-+	/* --[SmtAnt]-----------------------------------------*/
-+	#if (RTL8821A_SUPPORT)
-+		/*#define	CONFIG_HL_SMART_ANTENNA_TYPE1*/
-+		#define	CONFIG_FAT_PATCH
-+	#endif
-+	
-+	#if (RTL8822B_SUPPORT)
-+		/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
-+	#endif
-+	
-+	#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1) || defined(CONFIG_HL_SMART_ANTENNA_TYPE2))
-+		#define	CONFIG_HL_SMART_ANTENNA
-+	#endif
-+
-+	/* --------------------------------------------------*/
-+
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8192F_SUPPORT)
-+	#define CONFIG_PATH_DIVERSITY
-+#endif
-+
-+/*[SmartAntenna]*/
-+#define	CONFIG_SMART_ANTENNA
-+#ifdef CONFIG_SMART_ANTENNA
-+	/*#define	CONFIG_CUMITEK_SMART_ANTENNA*/
-+#endif
-+	/* --------------------------------------------------*/
-+
-+#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
-+	#define	CONFIG_RECEIVER_BLOCKING
-+#endif
-+
-+#if (RTL8821C_SUPPORT || RTL8822C_SUPPORT || RTL8822B_SUPPORT)
-+	#define CONFIG_BW_INDICATION
-+#endif
-+
-+#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
-+	RTL8192E_SUPPORT || RTL8723B_SUPPORT)
-+	#define	CONFIG_RA_FW_DBG_CODE
-+#endif
-+
-+/* #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR */
-+#define CONFIG_DYNAMIC_TX_TWR
-+/* #endif */
-+#if (RTL8822C_SUPPORT)
-+#define PHYDM_HW_IGI
-+#endif
-+#define	CONFIG_PSD_TOOL
-+#define PHYDM_SUPPORT_ADAPTIVITY
-+#define	PHYDM_SUPPORT_CCKPD
-+#if (defined(PHYDM_SUPPORT_CCKPD) && RTL8822C_SUPPORT)
-+	#define PHYDM_DCC_ENHANCE
-+#endif
-+/*#define	CONFIG_RA_DYNAMIC_RTY_LIMIT*/
-+#define CONFIG_ANT_DETECTION
-+#define	CONFIG_BB_TXBF_API
-+#define	ODM_CONFIG_BT_COEXIST
-+#define	CONFIG_PHYDM_DFS_MASTER
-+#define	PHYDM_SUPPORT_RSSI_MONITOR
-+#define	PHYDM_AUTO_DEGBUG
-+#define CONFIG_PHYDM_DEBUG_FUNCTION
-+#define CFG_DIG_DAMPING_CHK
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT ||  RTL8192E_SUPPORT ||\
-+	     RTL8814A_SUPPORT || RTL8881A_SUPPORT)
-+		#define	PHYDM_BEAMFORMING_VERSION1
-+	#endif
-+	#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
-+	     RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
-+	     RTL8822C_SUPPORT || RTL8814B_SUPPORT)
-+		#define	DRIVER_BEAMFORMING_VERSION2
-+	#endif
-+#endif
-+
-+#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)
-+	/*#define CONFIG_DIRECTIONAL_BF*/
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	#define CONFIG_MU_RSOML
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_hwconfig.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_hwconfig.c
-new file mode 100644
-index 000000000000..1e3589183974
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_hwconfig.c
-@@ -0,0 +1,1674 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(dm))
-+#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(dm))
-+
-+#if (PHYDM_TESTCHIP_SUPPORT == 1)
-+#define READ_AND_CONFIG(ic, txt)                     \
-+	do {                                         \
-+		if (dm->is_mp_chip)                  \
-+			READ_AND_CONFIG_MP(ic, txt); \
-+		else                                 \
-+			READ_AND_CONFIG_TC(ic, txt); \
-+	} while (0)
-+#else
-+#define READ_AND_CONFIG READ_AND_CONFIG_MP
-+#endif
-+
-+#define GET_VERSION_MP(ic, txt) (odm_get_version_mp_##ic##txt())
-+#define GET_VERSION_TC(ic, txt) (odm_get_version_tc_##ic##txt())
-+
-+#if (PHYDM_TESTCHIP_SUPPORT == 1)
-+#define GET_VERSION(ic, txt) (dm->is_mp_chip ? GET_VERSION_MP(ic, txt) : GET_VERSION_TC(ic, txt))
-+#else
-+#define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt)
-+#endif
-+
-+enum hal_status
-+odm_config_rf_with_header_file(struct dm_struct *dm,
-+			       enum odm_rf_config_type config_type,
-+			       u8 e_rf_path)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
-+#endif
-+	enum hal_status result = HAL_STATUS_SUCCESS;
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__,
-+		  (dm->is_mp_chip) ? "MPChip" : "TestChip");
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
-+		  dm->support_platform, dm->support_interface, dm->board_type);
-+
-+/* @1 AP doesn't use PHYDM power tracking table in these ICs */
-+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+#if (RTL8812A_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8812) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8812a, _radioa);
-+			else if (e_rf_path == RF_PATH_B)
-+				READ_AND_CONFIG_MP(8812a, _radiob);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE)
-+			HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+			if ((hal_data->EEPROMSVID == 0x17AA && hal_data->EEPROMSMID == 0xA811) ||
-+			    (hal_data->EEPROMSVID == 0x10EC && hal_data->EEPROMSMID == 0xA812) ||
-+			    (hal_data->EEPROMSVID == 0x10EC && hal_data->EEPROMSMID == 0x8812))
-+				READ_AND_CONFIG_MP(8812a, _txpwr_lmt_hm812a03);
-+			else
-+#endif
-+				READ_AND_CONFIG_MP(8812a, _txpwr_lmt);
-+		}
-+	}
-+#endif
-+#if (RTL8821A_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8821) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8821a, _radioa);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
-+			if (dm->support_interface == ODM_ITRF_USB) {
-+				if (dm->ext_pa_5g || dm->ext_lna_5g)
-+					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_fem);
-+				else
-+					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_ipa);
-+			} else {
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+				if (mgnt_info->CustomerID == RT_CID_8821AE_ASUS_MB)
-+					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_8mm);
-+				else if (mgnt_info->CustomerID == RT_CID_ASUS_NB)
-+					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_5mm);
-+				else
-+#endif
-+					READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a);
-+			}
-+		}
-+	}
-+#endif
-+#if (RTL8192E_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8192E) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8192e, _radioa);
-+			else if (e_rf_path == RF_PATH_B)
-+				READ_AND_CONFIG_MP(8192e, _radiob);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) /*Refine by Vincent Lan for 5mm SAR pwr limit*/
-+			HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+
-+			if ((hal_data->EEPROMSVID == 0x11AD && hal_data->EEPROMSMID == 0x8192) ||
-+			    (hal_data->EEPROMSVID == 0x11AD && hal_data->EEPROMSMID == 0x8193))
-+				READ_AND_CONFIG_MP(8192e, _txpwr_lmt_8192e_sar_5mm);
-+			else
-+#endif
-+				READ_AND_CONFIG_MP(8192e, _txpwr_lmt);
-+		}
-+	}
-+#endif
-+#if (RTL8723D_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8723D) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8723d, _radioa);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
-+			READ_AND_CONFIG_MP(8723d, _txpwr_lmt);
-+		}
-+	}
-+#endif
-+/* @JJ ADD 20161014 */
-+#if (RTL8710B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8710B) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8710b, _radioa);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT)
-+			READ_AND_CONFIG_MP(8710b, _txpwr_lmt);
-+	}
-+#endif
-+
-+#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
-+/* @1 All platforms support */
-+#if (RTL8188E_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8188E) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8188e, _radioa);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT)
-+			READ_AND_CONFIG_MP(8188e, _txpwr_lmt);
-+	}
-+#endif
-+#if (RTL8723B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8723B) {
-+		if (config_type == CONFIG_RF_RADIO)
-+			READ_AND_CONFIG_MP(8723b, _radioa);
-+		else if (config_type == CONFIG_RF_TXPWR_LMT)
-+			READ_AND_CONFIG_MP(8723b, _txpwr_lmt);
-+	}
-+#endif
-+#if (RTL8814A_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8814A) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8814a, _radioa);
-+			else if (e_rf_path == RF_PATH_B)
-+				READ_AND_CONFIG_MP(8814a, _radiob);
-+			else if (e_rf_path == RF_PATH_C)
-+				READ_AND_CONFIG_MP(8814a, _radioc);
-+			else if (e_rf_path == RF_PATH_D)
-+				READ_AND_CONFIG_MP(8814a, _radiod);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
-+			if (dm->rfe_type == 0)
-+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type0);
-+			else if (dm->rfe_type == 1)
-+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type1);
-+			else if (dm->rfe_type == 2)
-+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type2);
-+			else if (dm->rfe_type == 3)
-+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type3);
-+			else if (dm->rfe_type == 5)
-+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type5);
-+			else if (dm->rfe_type == 7)
-+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type7);
-+			else if (dm->rfe_type == 8)
-+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type8);
-+			else
-+				READ_AND_CONFIG_MP(8814a, _txpwr_lmt);
-+		}
-+	}
-+#endif
-+#if (RTL8703B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8703B) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8703b, _radioa);
-+		}
-+	}
-+#endif
-+#if (RTL8188F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8188F) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8188f, _radioa);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT)
-+			READ_AND_CONFIG_MP(8188f, _txpwr_lmt);
-+	}
-+#endif
-+#if (RTL8822B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8822B) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8822b, _radioa);
-+			else if (e_rf_path == RF_PATH_B)
-+				READ_AND_CONFIG_MP(8822b, _radiob);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
-+			if (dm->rfe_type == 5)
-+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type5);
-+			else if (dm->rfe_type == 2)
-+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type2);
-+			else if (dm->rfe_type == 3)
-+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type3);
-+			else if (dm->rfe_type == 4)
-+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type4);
-+			else if (dm->rfe_type == 12)
-+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type12);
-+			else if (dm->rfe_type == 15)
-+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type15);
-+			else if (dm->rfe_type == 16)
-+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type16);
-+			else if (dm->rfe_type == 17)
-+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type17);
-+			else if (dm->rfe_type == 18)
-+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type18);
-+			//else if (dm->rfe_type == 19)
-+				//READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type19);
-+			else
-+				READ_AND_CONFIG_MP(8822b, _txpwr_lmt);
-+		}
-+	}
-+#endif
-+
-+#if (RTL8197F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8197F) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8197f, _radioa);
-+			else if (e_rf_path == RF_PATH_B)
-+				READ_AND_CONFIG_MP(8197f, _radiob);
-+		}
-+	}
-+#endif
-+/*@jj add 20170822*/
-+#if (RTL8192F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8192F) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8192f, _radioa);
-+			else if (e_rf_path == RF_PATH_B)
-+				READ_AND_CONFIG_MP(8192f, _radiob);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
-+			if (dm->rfe_type == 0)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type0);
-+			else if (dm->rfe_type == 1)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type1);
-+			else if (dm->rfe_type == 2)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type2);
-+			else if (dm->rfe_type == 3)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type3);
-+			else if (dm->rfe_type == 4)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type4);
-+			else if (dm->rfe_type == 5)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type5);
-+			else if (dm->rfe_type == 6)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type6);
-+			else if (dm->rfe_type == 7)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type7);
-+			else if (dm->rfe_type == 8)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type8);
-+			else if (dm->rfe_type == 9)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type9);
-+			else if (dm->rfe_type == 10)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type10);
-+			else if (dm->rfe_type == 11)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type11);
-+			else if (dm->rfe_type == 12)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type12);
-+			else if (dm->rfe_type == 13)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type13);
-+			else if (dm->rfe_type == 14)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type14);
-+			else if (dm->rfe_type == 15)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type15);
-+			else if (dm->rfe_type == 16)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type16);
-+			else if (dm->rfe_type == 17)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type17);
-+			else if (dm->rfe_type == 18)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type18);
-+			else if (dm->rfe_type == 19)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type19);
-+			else if (dm->rfe_type == 20)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type20);
-+			else if (dm->rfe_type == 21)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type21);
-+			else if (dm->rfe_type == 22)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type22);
-+			else if (dm->rfe_type == 23)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type23);
-+			else if (dm->rfe_type == 24)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type24);
-+			else if (dm->rfe_type == 25)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type25);
-+			else if (dm->rfe_type == 26)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type26);
-+			else if (dm->rfe_type == 27)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type27);
-+			else if (dm->rfe_type == 28)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type28);
-+			else if (dm->rfe_type == 29)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type29);
-+			else if (dm->rfe_type == 30)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type30);
-+			else if (dm->rfe_type == 31)
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type31);
-+			else
-+				READ_AND_CONFIG_MP(8192f, _txpwr_lmt);
-+		}
-+	}
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8721D) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8721d, _radioa);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
-+			if (dm->power_voltage == ODM_POWER_18V)
-+				READ_AND_CONFIG_MP(8721d, _txpwr_lmt_type0);
-+			else
-+				READ_AND_CONFIG_MP(8721d, _txpwr_lmt_type1);
-+		}
-+	}
-+#endif
-+
-+#if (RTL8710C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8710C) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8710c, _radioa);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT)
-+			READ_AND_CONFIG_MP(8710c, _txpwr_lmt);
-+	}
-+#endif
-+
-+#if (RTL8821C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8821C) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG(8821c, _radioa);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
-+			READ_AND_CONFIG(8821c, _txpwr_lmt);
-+		}
-+	}
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+        if (dm->support_ic_type == ODM_RTL8195B) {
-+                if (config_type == CONFIG_RF_RADIO) {
-+                        if (e_rf_path == RF_PATH_A)
-+                                READ_AND_CONFIG(8195b, _radioa);
-+                } else if (config_type == CONFIG_RF_TXPWR_LMT) {
-+                        READ_AND_CONFIG(8195b, _txpwr_lmt);
-+                }
-+        }
-+#endif
-+#if (RTL8198F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8198F) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8198f, _radioa);
-+			else if (e_rf_path == RF_PATH_B)
-+				READ_AND_CONFIG_MP(8198f, _radiob);
-+			else if (e_rf_path == RF_PATH_C)
-+				READ_AND_CONFIG_MP(8198f, _radioc);
-+			else if (e_rf_path == RF_PATH_D)
-+				READ_AND_CONFIG_MP(8198f, _radiod);
-+		}
-+	}
-+#endif
-+/*#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8814b, _radioa);
-+			else if (e_rf_path == RF_PATH_B)
-+				READ_AND_CONFIG_MP(8814b, _radiob);
-+			else if (e_rf_path == RF_PATH_C)
-+				READ_AND_CONFIG_MP(8814b, _radioc);
-+			else if (e_rf_path == RF_PATH_D)
-+				READ_AND_CONFIG_MP(8814b, _radiod);
-+		}
-+	}
-+#endif
-+*/
-+#if (RTL8822C_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8822C) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8822c, _radioa);
-+			else if (e_rf_path == RF_PATH_B)
-+				READ_AND_CONFIG_MP(8822c, _radiob);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
-+			if (dm->rfe_type == 5)
-+				READ_AND_CONFIG_MP(8822c, _txpwr_lmt_type5);
-+			else
-+				READ_AND_CONFIG_MP(8822c, _txpwr_lmt);
-+		}
-+	}
-+#endif
-+#if (RTL8723F_SUPPORT)
-+		if (dm->support_ic_type == ODM_RTL8723F) {
-+			if (config_type == CONFIG_RF_RADIO) {
-+				if (e_rf_path == RF_PATH_A)
-+					READ_AND_CONFIG_MP(8723f, _radioa);
-+				if (e_rf_path == RF_PATH_B)
-+					READ_AND_CONFIG_MP(8723f, _radiob);
-+			} else if (config_type == CONFIG_RF_TXPWR_LMT) {
-+				READ_AND_CONFIG_MP(8723f, _txpwr_lmt);
-+			}
-+		}
-+#endif
-+#if (RTL8812F_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8812F) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8812f, _radioa);
-+			else if (e_rf_path == RF_PATH_B)
-+				READ_AND_CONFIG_MP(8812f, _radiob);
-+		}
-+	}
-+#endif
-+#if (RTL8197G_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8197G) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8197g, _radioa);
-+			else if (e_rf_path == RF_PATH_B)
-+				READ_AND_CONFIG_MP(8197g, _radiob);
-+		}
-+	}
-+#endif
-+
-+ /*8814B need review, when phydm has related files*/
-+ #if (RTL8814B_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		if (config_type == CONFIG_RF_RADIO) {
-+			if (e_rf_path == RF_PATH_A)
-+				READ_AND_CONFIG_MP(8814b, _radioa);
-+			else if (e_rf_path == RF_PATH_B)
-+				READ_AND_CONFIG_MP(8814b, _radiob);
-+			else if (e_rf_path == RF_PATH_C)
-+				READ_AND_CONFIG_MP(8814b, _radioc);
-+			else if (e_rf_path == RF_PATH_D)
-+				READ_AND_CONFIG_MP(8814b, _radiod);
-+		}
-+		if (config_type == CONFIG_RF_SYN_RADIO) {
-+			if (e_rf_path == RF_SYN0)
-+				READ_AND_CONFIG_MP(8814b, _radiosyn0);
-+			else if (e_rf_path == RF_SYN1)
-+				READ_AND_CONFIG_MP(8814b, _radiosyn1);
-+		} else if (config_type == CONFIG_RF_TXPWR_LMT) {
-+			READ_AND_CONFIG_MP(8814b, _txpwr_lmt);
-+		}
-+	}
-+  #endif
-+
-+	if (config_type == CONFIG_RF_RADIO) {
-+		if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
-+			result = phydm_set_reg_by_fw(dm,
-+						     PHYDM_HALMAC_CMD_END,
-+						     0,
-+						     0,
-+						     0,
-+						     (enum rf_path)0,
-+						     0);
-+			PHYDM_DBG(dm, ODM_COMP_INIT,
-+				  "rf param offload end!result = %d", result);
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+enum hal_status
-+odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm)
-+{
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__,
-+		  (dm->is_mp_chip) ? "MPChip" : "TestChip");
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
-+		  dm->support_platform, dm->support_interface, dm->board_type);
-+
-+/* @1 AP doesn't use PHYDM power tracking table in these ICs */
-+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+#if RTL8821A_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8821) {
-+		if (dm->support_interface == ODM_ITRF_PCIE)
-+			READ_AND_CONFIG_MP(8821a, _txpowertrack_pcie);
-+		else if (dm->support_interface == ODM_ITRF_USB)
-+			READ_AND_CONFIG_MP(8821a, _txpowertrack_usb);
-+		else if (dm->support_interface == ODM_ITRF_SDIO)
-+			READ_AND_CONFIG_MP(8821a, _txpowertrack_sdio);
-+	}
-+#endif
-+#if RTL8812A_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8812) {
-+		if (dm->support_interface == ODM_ITRF_PCIE)
-+			READ_AND_CONFIG_MP(8812a, _txpowertrack_pcie);
-+		else if (dm->support_interface == ODM_ITRF_USB) {
-+			if (dm->rfe_type == 3 && dm->is_mp_chip)
-+				READ_AND_CONFIG_MP(8812a, _txpowertrack_rfe3);
-+			else
-+				READ_AND_CONFIG_MP(8812a, _txpowertrack_usb);
-+		}
-+	}
-+#endif
-+#if RTL8192E_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8192E) {
-+		if (dm->support_interface == ODM_ITRF_PCIE)
-+			READ_AND_CONFIG_MP(8192e, _txpowertrack_pcie);
-+		else if (dm->support_interface == ODM_ITRF_USB)
-+			READ_AND_CONFIG_MP(8192e, _txpowertrack_usb);
-+		else if (dm->support_interface == ODM_ITRF_SDIO)
-+			READ_AND_CONFIG_MP(8192e, _txpowertrack_sdio);
-+	}
-+#endif
-+#if RTL8723D_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8723D) {
-+		if (dm->support_interface == ODM_ITRF_PCIE)
-+			READ_AND_CONFIG_MP(8723d, _txpowertrack_pcie);
-+		else if (dm->support_interface == ODM_ITRF_USB)
-+			READ_AND_CONFIG_MP(8723d, _txpowertrack_usb);
-+		else if (dm->support_interface == ODM_ITRF_SDIO)
-+			READ_AND_CONFIG_MP(8723d, _txpowertrack_sdio);
-+
-+		READ_AND_CONFIG_MP(8723d, _txxtaltrack);
-+	}
-+#endif
-+/* @JJ ADD 20161014 */
-+#if RTL8710B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8710B) {
-+		if (dm->package_type == 1)
-+			READ_AND_CONFIG_MP(8710b, _txpowertrack_qfn48m_smic);
-+		else if (dm->package_type == 5)
-+			READ_AND_CONFIG_MP(8710b, _txpowertrack_qfn48m_umc);
-+
-+		READ_AND_CONFIG_MP(8710b, _txxtaltrack);
-+	}
-+#endif
-+#if RTL8188E_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8188E) {
-+		if (odm_get_mac_reg(dm, R_0xf0, 0xF000) >= 8) { /*@if 0xF0[15:12] >= 8, SMIC*/
-+			if (dm->support_interface == ODM_ITRF_PCIE)
-+				READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie_icut);
-+			else if (dm->support_interface == ODM_ITRF_USB)
-+				READ_AND_CONFIG_MP(8188e, _txpowertrack_usb_icut);
-+			else if (dm->support_interface == ODM_ITRF_SDIO)
-+				READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio_icut);
-+		} else { /*@else 0xF0[15:12] < 8, TSMC*/
-+			if (dm->support_interface == ODM_ITRF_PCIE)
-+				READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie);
-+			else if (dm->support_interface == ODM_ITRF_USB)
-+				READ_AND_CONFIG_MP(8188e, _txpowertrack_usb);
-+			else if (dm->support_interface == ODM_ITRF_SDIO)
-+				READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio);
-+		}
-+	}
-+#endif
-+#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
-+/* @1 All platforms support */
-+#if RTL8723B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8723B) {
-+		if (dm->support_interface == ODM_ITRF_PCIE)
-+			READ_AND_CONFIG_MP(8723b, _txpowertrack_pcie);
-+		else if (dm->support_interface == ODM_ITRF_USB)
-+			READ_AND_CONFIG_MP(8723b, _txpowertrack_usb);
-+		else if (dm->support_interface == ODM_ITRF_SDIO)
-+			READ_AND_CONFIG_MP(8723b, _txpowertrack_sdio);
-+	}
-+#endif
-+#if RTL8814A_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8814A) {
-+		if (dm->rfe_type == 0)
-+			READ_AND_CONFIG_MP(8814a, _txpowertrack_type0);
-+		else if (dm->rfe_type == 2)
-+			READ_AND_CONFIG_MP(8814a, _txpowertrack_type2);
-+		else if (dm->rfe_type == 5)
-+			READ_AND_CONFIG_MP(8814a, _txpowertrack_type5);
-+		else if (dm->rfe_type == 7)
-+			READ_AND_CONFIG_MP(8814a, _txpowertrack_type7);
-+		else if (dm->rfe_type == 8)
-+			READ_AND_CONFIG_MP(8814a, _txpowertrack_type8);
-+		else
-+			READ_AND_CONFIG_MP(8814a, _txpowertrack);
-+
-+		READ_AND_CONFIG_MP(8814a, _txpowertssi);
-+	}
-+#endif
-+#if RTL8703B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8703B) {
-+		if (dm->support_interface == ODM_ITRF_USB)
-+			READ_AND_CONFIG_MP(8703b, _txpowertrack_usb);
-+		else if (dm->support_interface == ODM_ITRF_SDIO)
-+			READ_AND_CONFIG_MP(8703b, _txpowertrack_sdio);
-+
-+		READ_AND_CONFIG_MP(8703b, _txxtaltrack);
-+	}
-+#endif
-+#if RTL8188F_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8188F) {
-+		if (dm->support_interface == ODM_ITRF_USB)
-+			READ_AND_CONFIG_MP(8188f, _txpowertrack_usb);
-+		else if (dm->support_interface == ODM_ITRF_SDIO)
-+			READ_AND_CONFIG_MP(8188f, _txpowertrack_sdio);
-+	}
-+#endif
-+#if RTL8822B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8822B) {
-+		if (dm->rfe_type == 0)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type0);
-+		else if (dm->rfe_type == 1)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type1);
-+		else if (dm->rfe_type == 2)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type2);
-+		else if ((dm->rfe_type == 3) || (dm->rfe_type == 5))
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type3_type5);
-+		else if (dm->rfe_type == 4)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type4);
-+		else if (dm->rfe_type == 6)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type6);
-+		else if (dm->rfe_type == 7)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type7);
-+		else if (dm->rfe_type == 8)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type8);
-+		else if (dm->rfe_type == 9)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type9);
-+		else if (dm->rfe_type == 10)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type10);
-+		else if (dm->rfe_type == 11)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type11);
-+		else if (dm->rfe_type == 12)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type12);
-+		else if (dm->rfe_type == 13)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type13);
-+		else if (dm->rfe_type == 14)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type14);
-+		else if (dm->rfe_type == 15)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type15);
-+		else if (dm->rfe_type == 16)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type16);
-+		else if (dm->rfe_type == 17)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type17);
-+		else if (dm->rfe_type == 18)
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack_type18);
-+		//else if (dm->rfe_type == 19)
-+			//READ_AND_CONFIG_MP(8822b, _txpowertrack_type19);
-+		else
-+			READ_AND_CONFIG_MP(8822b, _txpowertrack);
-+	}
-+#endif
-+#if RTL8197F_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8197F) {
-+		if (dm->rfe_type == 0)
-+			READ_AND_CONFIG_MP(8197f, _txpowertrack_type0);
-+		else if (dm->rfe_type == 1)
-+			READ_AND_CONFIG_MP(8197f, _txpowertrack_type1);
-+		else
-+			READ_AND_CONFIG_MP(8197f, _txpowertrack);
-+	}
-+#endif
-+/*@jj add 20170822*/
-+#if RTL8192F_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8192F) {
-+		if (dm->rfe_type == 0)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type0);
-+		else if (dm->rfe_type == 1)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type1);
-+		else if (dm->rfe_type == 2)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type2);
-+		else if (dm->rfe_type == 3)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type3);
-+		else if (dm->rfe_type == 4)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type4);
-+		else if (dm->rfe_type == 5)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type5);
-+		else if (dm->rfe_type == 6)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type6);
-+		else if (dm->rfe_type == 7)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type7);
-+		else if (dm->rfe_type == 8)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type8);
-+		else if (dm->rfe_type == 9)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type9);
-+		else if (dm->rfe_type == 10)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type10);
-+		else if (dm->rfe_type == 11)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type11);
-+		else if (dm->rfe_type == 12)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type12);
-+		else if (dm->rfe_type == 13)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type13);
-+		else if (dm->rfe_type == 14)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type14);
-+		else if (dm->rfe_type == 15)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type15);
-+		else if (dm->rfe_type == 16)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type16);
-+		else if (dm->rfe_type == 17)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type17);
-+		else if (dm->rfe_type == 18)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type18);
-+		else if (dm->rfe_type == 19)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type19);
-+		else if (dm->rfe_type == 20)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type20);
-+		else if (dm->rfe_type == 21)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type21);
-+		else if (dm->rfe_type == 22)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type22);
-+		else if (dm->rfe_type == 23)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type23);
-+		else if (dm->rfe_type == 24)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type24);
-+		else if (dm->rfe_type == 25)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type25);
-+		else if (dm->rfe_type == 26)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type26);
-+		else if (dm->rfe_type == 27)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type27);
-+		else if (dm->rfe_type == 28)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type28);
-+		else if (dm->rfe_type == 29)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type29);
-+		else if (dm->rfe_type == 30)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type30);
-+		else if (dm->rfe_type == 31)
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack_type31);
-+		else
-+			READ_AND_CONFIG_MP(8192f, _txpowertrack);
-+
-+		READ_AND_CONFIG_MP(8192f, _txxtaltrack);
-+	}
-+#endif
-+
-+#if RTL8721D_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8721D) {
-+		#if 0
-+		if (dm->package_type == 1)
-+			READ_AND_CONFIG_MP(8721d, _txpowertrack_qfn48m_smic);
-+		else if (dm->package_type == 5)
-+			READ_AND_CONFIG_MP(8721d, _txpowertrack_qfn48m_umc);
-+		#endif
-+		READ_AND_CONFIG_MP(8721d, _txpowertrack);
-+		READ_AND_CONFIG_MP(8721d, _txxtaltrack);
-+	}
-+#endif
-+
-+#if RTL8710C_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8710C) {
-+		#if 0
-+		if (dm->package_type == 1)
-+			READ_AND_CONFIG_MP(8710c, _txpowertrack_qfn48m_smic);
-+		else if (dm->package_type == 5)
-+			READ_AND_CONFIG_MP(8710c, _txpowertrack_qfn48m_umc);
-+		#endif
-+		READ_AND_CONFIG_MP(8710c, _txpowertrack);
-+		READ_AND_CONFIG_MP(8710c, _txxtaltrack);
-+	}
-+#endif
-+
-+#if RTL8821C_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8821C) {
-+		if (dm->rfe_type == 0x5)
-+			READ_AND_CONFIG(8821c, _txpowertrack_type0x28);
-+		else if (dm->rfe_type == 0x4)
-+			READ_AND_CONFIG(8821c, _txpowertrack_type0x20);
-+		else
-+			READ_AND_CONFIG(8821c, _txpowertrack);
-+	}
-+#endif
-+
-+#if RTL8198F_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8198F) {
-+		if (dm->rfe_type == 0)
-+			READ_AND_CONFIG_MP(8198f, _txpowertrack_type0);
-+		else if (dm->rfe_type == 1)
-+			READ_AND_CONFIG_MP(8198f, _txpowertrack_type1);
-+		else if (dm->rfe_type == 3)
-+			READ_AND_CONFIG_MP(8198f, _txpowertrack_type3);
-+		else
-+			READ_AND_CONFIG_MP(8198f, _txpowertrack);
-+		}
-+#endif
-+
-+#if RTL8195B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8195B) {
-+		if (dm->package_type == 1) {
-+			READ_AND_CONFIG_MP(8195b, _txpowertrack_pkg1);
-+			READ_AND_CONFIG_MP(8195b, _txxtaltrack_pkg1);
-+		} else {
-+			READ_AND_CONFIG_MP(8195b, _txpowertrack);
-+			READ_AND_CONFIG_MP(8195b, _txxtaltrack);
-+		}
-+	}
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8822C) {
-+		if (dm->en_tssi_mode)
-+			READ_AND_CONFIG_MP(8822c, _txpowertracktssi);
-+		else
-+			READ_AND_CONFIG_MP(8822c, _txpowertrack);
-+	}
-+#endif
-+
-+#if (RTL8723F_SUPPORT)
-+		if (dm->support_ic_type == ODM_RTL8723F)
-+			READ_AND_CONFIG_MP(8723f, _txpowertrack);
-+#endif
-+#if (RTL8812F_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8812F) {
-+		if (dm->rfe_type == 0)
-+			READ_AND_CONFIG_MP(8812f, _txpowertrack_type0);
-+		else if (dm->rfe_type == 1)
-+			READ_AND_CONFIG_MP(8812f, _txpowertrack_type1);
-+		else if (dm->rfe_type == 2)
-+			READ_AND_CONFIG_MP(8812f, _txpowertrack_type2);
-+		else if (dm->rfe_type == 3)
-+			READ_AND_CONFIG_MP(8812f, _txpowertrack_type3);
-+		else if (dm->rfe_type == 4)
-+			READ_AND_CONFIG_MP(8812f, _txpowertrack_type4);
-+		else
-+			READ_AND_CONFIG_MP(8812f, _txpowertrack);
-+	}
-+#endif
-+
-+#if (RTL8197G_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8197G)
-+		READ_AND_CONFIG_MP(8197g, _txpowertrack);
-+#endif
-+
-+#if RTL8814B_SUPPORT
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		if (dm->rfe_type == 0)
-+			READ_AND_CONFIG_MP(8814b, _txpowertrack_type0);
-+		else if (dm->rfe_type == 1)
-+			READ_AND_CONFIG_MP(8814b, _txpowertrack_type1);
-+		else if (dm->rfe_type == 2)
-+			READ_AND_CONFIG_MP(8814b, _txpowertrack_type2);
-+#if 0
-+		else if (dm->rfe_type == 3)
-+			READ_AND_CONFIG_MP(8814b, _txpowertrack_type3);
-+		else if (dm->rfe_type == 6)
-+			READ_AND_CONFIG_MP(8814b, _txpowertrack_type6);
-+#endif
-+		else
-+			READ_AND_CONFIG_MP(8814b, _txpowertrack);
-+		}
-+#endif
-+
-+	return HAL_STATUS_SUCCESS;
-+}
-+
-+enum hal_status
-+odm_config_bb_with_header_file(struct dm_struct *dm,
-+			       enum odm_bb_config_type config_type)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
-+#endif
-+	enum hal_status result = HAL_STATUS_SUCCESS;
-+
-+/* @1 AP doesn't use PHYDM initialization in these ICs */
-+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+#if (RTL8812A_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8812) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8812a, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8812a, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG) {
-+			if (dm->rfe_type == 3 && dm->is_mp_chip)
-+				READ_AND_CONFIG_MP(8812a, _phy_reg_pg_asus);
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+			else if (mgnt_info->CustomerID == RT_CID_WNC_NEC && dm->is_mp_chip)
-+				READ_AND_CONFIG_MP(8812a, _phy_reg_pg_nec);
-+#if RT_PLATFORM == PLATFORM_MACOSX
-+			/*@{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/
-+			else if (mgnt_info->CustomerID == RT_CID_DNI_BUFFALO)
-+				READ_AND_CONFIG_MP(8812a, _phy_reg_pg_dni);
-+			/* TP-Link T4UH, Isaiah 2015-03-16*/
-+			else if (mgnt_info->CustomerID == RT_CID_TPLINK_HPWR) {
-+				pr_debug("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n");
-+				READ_AND_CONFIG_MP(8812a, _phy_reg_pg_tplink);
-+			}
-+#endif
-+#endif
-+			else
-+				READ_AND_CONFIG_MP(8812a, _phy_reg_pg);
-+		} else if (config_type == CONFIG_BB_PHY_REG_MP)
-+			READ_AND_CONFIG_MP(8812a, _phy_reg_mp);
-+		else if (config_type == CONFIG_BB_AGC_TAB_DIFF) {
-+			dm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD;
-+			/*@AGC_TAB DIFF dont support FW offload*/
-+			if ((*dm->channel >= 36) && (*dm->channel <= 64))
-+				AGC_DIFF_CONFIG_MP(8812a, lb);
-+			else if (*dm->channel >= 100)
-+				AGC_DIFF_CONFIG_MP(8812a, hb);
-+		}
-+	}
-+#endif
-+#if (RTL8821A_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8821) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8821a, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8821a, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG) {
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
-+			HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+
-+			if ((hal_data->EEPROMSVID == 0x1043 && hal_data->EEPROMSMID == 0x207F))
-+				READ_AND_CONFIG_MP(8821a, _phy_reg_pg_e202_sa);
-+			else
-+#endif
-+#if (RT_PLATFORM == PLATFORM_MACOSX)
-+				/*@  for BUFFALO pwr by rate table */
-+				if (mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) {
-+				/*@  for BUFFALO pwr by rate table (JP/US)*/
-+				if (mgnt_info->ChannelPlan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G)
-+					READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_us);
-+				else
-+					READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_jp);
-+			} else
-+#endif
-+#endif
-+				READ_AND_CONFIG_MP(8821a, _phy_reg_pg);
-+		}
-+	}
-+#endif
-+#if (RTL8192E_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8192E) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8192e, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8192e, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG)
-+			READ_AND_CONFIG_MP(8192e, _phy_reg_pg);
-+	}
-+#endif
-+#if (RTL8723D_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8723D) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8723d, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8723d, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG)
-+			READ_AND_CONFIG_MP(8723d, _phy_reg_pg);
-+	}
-+#endif
-+/* @JJ ADD 20161014 */
-+#if (RTL8710B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8710B) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8710b, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8710b, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG)
-+			READ_AND_CONFIG_MP(8710b, _phy_reg_pg);
-+	}
-+#endif
-+
-+#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
-+/* @1 All platforms support */
-+#if (RTL8188E_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8188E) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8188e, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8188e, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG)
-+			READ_AND_CONFIG_MP(8188e, _phy_reg_pg);
-+	}
-+#endif
-+#if (RTL8723B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8723B) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8723b, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8723b, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG)
-+			READ_AND_CONFIG_MP(8723b, _phy_reg_pg);
-+	}
-+#endif
-+#if (RTL8814A_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8814A) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8814a, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8814a, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG) {
-+			if (dm->rfe_type == 0)
-+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type0);
-+			else if (dm->rfe_type == 2)
-+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type2);
-+			else if (dm->rfe_type == 3)
-+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type3);
-+			else if (dm->rfe_type == 4)
-+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type4);
-+			else if (dm->rfe_type == 5)
-+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type5);
-+			else if (dm->rfe_type == 7)
-+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type7);
-+			else if (dm->rfe_type == 8)
-+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type8);
-+			else
-+				READ_AND_CONFIG_MP(8814a, _phy_reg_pg);
-+		} else if (config_type == CONFIG_BB_PHY_REG_MP)
-+			READ_AND_CONFIG_MP(8814a, _phy_reg_mp);
-+	}
-+#endif
-+#if (RTL8703B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8703B) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8703b, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8703b, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG)
-+			READ_AND_CONFIG_MP(8703b, _phy_reg_pg);
-+	}
-+#endif
-+#if (RTL8188F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8188F) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8188f, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8188f, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG)
-+			READ_AND_CONFIG_MP(8188f, _phy_reg_pg);
-+	}
-+#endif
-+#if (RTL8822B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8822B) {
-+		if (config_type == CONFIG_BB_PHY_REG) {
-+			READ_AND_CONFIG_MP(8822b, _phy_reg);
-+		} else if (config_type == CONFIG_BB_AGC_TAB) {
-+			READ_AND_CONFIG_MP(8822b, _agc_tab);
-+		} else if (config_type == CONFIG_BB_PHY_REG_PG) {
-+			if (dm->rfe_type == 2)
-+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type2);
-+			else if (dm->rfe_type == 3)
-+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type3);
-+			else if (dm->rfe_type == 4)
-+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type4);
-+			else if (dm->rfe_type == 5)
-+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type5);
-+			else if (dm->rfe_type == 12)
-+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type12);
-+			else if (dm->rfe_type == 15)
-+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type15);
-+			else if (dm->rfe_type == 16)
-+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type16);
-+			else if (dm->rfe_type == 17)
-+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type17);
-+			else if (dm->rfe_type == 18)
-+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type18);
-+			//else if (dm->rfe_type == 19)
-+				//READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type19);
-+			else
-+				READ_AND_CONFIG_MP(8822b, _phy_reg_pg);
-+		}
-+	}
-+#endif
-+
-+#if (RTL8197F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8197F) {
-+		if (config_type == CONFIG_BB_PHY_REG) {
-+			READ_AND_CONFIG_MP(8197f, _phy_reg);
-+			if (dm->cut_version == ODM_CUT_A)
-+				phydm_phypara_a_cut(dm);
-+		} else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8197f, _agc_tab);
-+	}
-+#endif
-+/*@jj add 20170822*/
-+#if (RTL8192F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8192F) {
-+		if (config_type == CONFIG_BB_PHY_REG) {
-+			READ_AND_CONFIG_MP(8192f, _phy_reg);
-+		} else if (config_type == CONFIG_BB_AGC_TAB) {
-+			READ_AND_CONFIG_MP(8192f, _agc_tab);
-+		} else if (config_type == CONFIG_BB_PHY_REG_PG) {
-+			if (dm->rfe_type == 0)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type0);
-+			else if (dm->rfe_type == 1)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type1);
-+			else if (dm->rfe_type == 2)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type2);
-+			else if (dm->rfe_type == 3)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type3);
-+			else if (dm->rfe_type == 4)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type4);
-+			else if (dm->rfe_type == 5)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type5);
-+			else if (dm->rfe_type == 6)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type6);
-+			else if (dm->rfe_type == 7)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type7);
-+			else if (dm->rfe_type == 8)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type8);
-+			else if (dm->rfe_type == 9)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type9);
-+			else if (dm->rfe_type == 10)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type10);
-+			else if (dm->rfe_type == 11)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type11);
-+			else if (dm->rfe_type == 12)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type12);
-+			else if (dm->rfe_type == 13)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type13);
-+			else if (dm->rfe_type == 14)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type14);
-+			else if (dm->rfe_type == 15)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type15);
-+			else if (dm->rfe_type == 16)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type16);
-+			else if (dm->rfe_type == 17)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type17);
-+			else if (dm->rfe_type == 18)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type18);
-+			else if (dm->rfe_type == 19)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type19);
-+			else if (dm->rfe_type == 20)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type20);
-+			else if (dm->rfe_type == 21)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type21);
-+			else if (dm->rfe_type == 22)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type22);
-+			else if (dm->rfe_type == 23)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type23);
-+			else if (dm->rfe_type == 24)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type24);
-+			else if (dm->rfe_type == 25)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type25);
-+			else if (dm->rfe_type == 26)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type26);
-+			else if (dm->rfe_type == 27)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type27);
-+			else if (dm->rfe_type == 28)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type28);
-+			else if (dm->rfe_type == 29)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type29);
-+			else if (dm->rfe_type == 30)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type30);
-+			else if (dm->rfe_type == 31)
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type31);
-+			else
-+				READ_AND_CONFIG_MP(8192f, _phy_reg_pg);
-+		}
-+	}
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8721D) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8721d, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8721d, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG) {
-+			if (dm->power_voltage == ODM_POWER_18V)
-+				READ_AND_CONFIG_MP(8721d, _phy_reg_pg_type0);
-+			else
-+				READ_AND_CONFIG_MP(8721d, _phy_reg_pg_type1);
-+		}
-+	}
-+#endif
-+
-+#if (RTL8710C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8710C) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8710c, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8710c, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG)
-+			READ_AND_CONFIG_MP(8710c, _phy_reg_pg);
-+	}
-+#endif
-+
-+#if (RTL8821C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8821C) {
-+		if (config_type == CONFIG_BB_PHY_REG) {
-+			READ_AND_CONFIG(8821c, _phy_reg);
-+		} else if (config_type == CONFIG_BB_AGC_TAB) {
-+			READ_AND_CONFIG(8821c, _agc_tab);
-+			/* @According to RFEtype, choosing correct AGC table*/
-+			if (dm->default_rf_set_8821c == SWITCH_TO_BTG)
-+				AGC_DIFF_CONFIG_MP(8821c, btg);
-+		} else if (config_type == CONFIG_BB_PHY_REG_PG) {
-+			if (dm->rfe_type == 0x5)
-+				READ_AND_CONFIG(8821c, _phy_reg_pg_type0x28);
-+			else
-+				READ_AND_CONFIG(8821c, _phy_reg_pg);
-+		} else if (config_type == CONFIG_BB_AGC_TAB_DIFF) {
-+			dm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD;
-+			/*@AGC_TAB DIFF dont support FW offload*/
-+			if (dm->current_rf_set_8821c == SWITCH_TO_BTG)
-+				AGC_DIFF_CONFIG_MP(8821c, btg);
-+			else if (dm->current_rf_set_8821c == SWITCH_TO_WLG)
-+				AGC_DIFF_CONFIG_MP(8821c, wlg);
-+		} else if (config_type == CONFIG_BB_PHY_REG_MP) {
-+			READ_AND_CONFIG(8821c, _phy_reg_mp);
-+		}
-+	}
-+#endif
-+
-+#if (RTL8195A_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8195A) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG(8195a, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG(8195a, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG)
-+			READ_AND_CONFIG(8195a, _phy_reg_pg);
-+	}
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8195B) {
-+		if (config_type == CONFIG_BB_PHY_REG) {
-+			READ_AND_CONFIG(8195b, _phy_reg);
-+		} else if (config_type == CONFIG_BB_AGC_TAB) {
-+			READ_AND_CONFIG(8195b, _agc_tab);
-+		} else if (config_type == CONFIG_BB_PHY_REG_PG) {
-+			READ_AND_CONFIG(8195b, _phy_reg_pg);
-+		} else if (config_type == CONFIG_BB_PHY_REG_MP) {
-+			if (dm->package_type == 1)
-+				odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, 0x10);
-+			else
-+				odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, 0x12);
-+		}
-+	}
-+#endif
-+#if (RTL8198F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8198F) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8198f, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8198f, _agc_tab);
-+	}
-+#endif
-+#if (RTL8814B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8814b, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8814b, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG) {
-+			if (dm->rfe_type == 1)
-+				READ_AND_CONFIG(8814b, _phy_reg_pg_type1);
-+			else
-+				READ_AND_CONFIG(8814b, _phy_reg_pg);
-+		}
-+	}
-+#endif
-+#if (RTL8822C_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8822C) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8822c, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8822c, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG)
-+			READ_AND_CONFIG(8822c, _phy_reg_pg);
-+	}
-+#endif
-+#if (RTL8723F_SUPPORT)
-+		if (dm->support_ic_type == ODM_RTL8723F) {
-+			if (config_type == CONFIG_BB_PHY_REG)
-+				READ_AND_CONFIG_MP(8723f, _phy_reg);
-+			else if (config_type == CONFIG_BB_AGC_TAB)
-+				READ_AND_CONFIG_MP(8723f, _agc_tab);
-+			else if (config_type == CONFIG_BB_PHY_REG_PG)
-+				READ_AND_CONFIG(8723f, _phy_reg_pg);
-+		}
-+#endif
-+#if (RTL8812F_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8812F) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8812f, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8812f, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG)
-+			READ_AND_CONFIG(8812f, _phy_reg_pg);
-+	}
-+#endif
-+#if (RTL8197G_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8197G) {
-+		if (config_type == CONFIG_BB_PHY_REG)
-+			READ_AND_CONFIG_MP(8197g, _phy_reg);
-+		else if (config_type == CONFIG_BB_AGC_TAB)
-+			READ_AND_CONFIG_MP(8197g, _agc_tab);
-+		else if (config_type == CONFIG_BB_PHY_REG_PG)
-+			READ_AND_CONFIG(8197g, _phy_reg_pg);
-+	}
-+#endif
-+
-+	if (config_type == CONFIG_BB_PHY_REG ||
-+	    config_type == CONFIG_BB_AGC_TAB)
-+		if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
-+			result = phydm_set_reg_by_fw(dm,
-+						     PHYDM_HALMAC_CMD_END,
-+						     0,
-+						     0,
-+						     0,
-+						     (enum rf_path)0,
-+						     0);
-+			PHYDM_DBG(dm, ODM_COMP_INIT,
-+				  "phy param offload end!result = %d", result);
-+		}
-+
-+	return result;
-+}
-+
-+enum hal_status
-+odm_config_mac_with_header_file(struct dm_struct *dm)
-+{
-+	enum hal_status result = HAL_STATUS_SUCCESS;
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__,
-+		  (dm->is_mp_chip) ? "MPChip" : "TestChip");
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
-+		  dm->support_platform, dm->support_interface, dm->board_type);
-+
-+#ifdef PHYDM_IC_HALMAC_PARAM_SUPPORT
-+	if (dm->support_ic_type & PHYDM_IC_SUPPORT_HALMAC_PARAM_OFFLOAD) {
-+		PHYDM_DBG(dm, ODM_COMP_INIT, "MAC para-package in HALMAC\n");
-+		return result;
-+	}
-+#endif
-+
-+/* @1 AP doesn't use PHYDM initialization in these ICs */
-+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+#if (RTL8812A_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8812)
-+		READ_AND_CONFIG_MP(8812a, _mac_reg);
-+#endif
-+#if (RTL8821A_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8821)
-+		READ_AND_CONFIG_MP(8821a, _mac_reg);
-+#endif
-+#if (RTL8192E_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8192E)
-+		READ_AND_CONFIG_MP(8192e, _mac_reg);
-+#endif
-+#if (RTL8723D_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8723D)
-+		READ_AND_CONFIG_MP(8723d, _mac_reg);
-+#endif
-+#if (RTL8710B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8710B)
-+		READ_AND_CONFIG_MP(8710b, _mac_reg);
-+#endif
-+#endif /* @(DM_ODM_SUPPORT_TYPE !=  ODM_AP) */
-+
-+/* @1 All platforms support */
-+#if (RTL8188E_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8188E)
-+		READ_AND_CONFIG_MP(8188e, _mac_reg);
-+#endif
-+#if (RTL8723B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8723B)
-+		READ_AND_CONFIG_MP(8723b, _mac_reg);
-+#endif
-+#if (RTL8814A_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8814A)
-+		READ_AND_CONFIG_MP(8814a, _mac_reg);
-+#endif
-+#if (RTL8703B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8703B)
-+		READ_AND_CONFIG_MP(8703b, _mac_reg);
-+#endif
-+#if (RTL8188F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8188F)
-+		READ_AND_CONFIG_MP(8188f, _mac_reg);
-+#endif
-+#if (RTL8822B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8822B)
-+		READ_AND_CONFIG_MP(8822b, _mac_reg);
-+#endif
-+#if (RTL8197F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8197F)
-+		READ_AND_CONFIG_MP(8197f, _mac_reg);
-+#endif
-+#if (RTL8192F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8192F)
-+		READ_AND_CONFIG_MP(8192f, _mac_reg);
-+#endif
-+#if (RTL8721D_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8721D)
-+		READ_AND_CONFIG_MP(8721d, _mac_reg);
-+#endif
-+
-+#if (RTL8710C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8710C)
-+		READ_AND_CONFIG_MP(8710c, _mac_reg);
-+#endif
-+
-+#if (RTL8821C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8821C)
-+		READ_AND_CONFIG(8821c, _mac_reg);
-+#endif
-+#if (RTL8195A_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8195A)
-+		READ_AND_CONFIG_MP(8195a, _mac_reg);
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8195B)
-+		READ_AND_CONFIG_MP(8195b, _mac_reg);
-+#endif
-+#if (RTL8198F_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8198F)
-+		READ_AND_CONFIG_MP(8198f, _mac_reg);
-+#endif
-+#if (RTL8197G_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8197G)
-+		READ_AND_CONFIG_MP(8197g, _mac_reg);
-+#endif
-+
-+	if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
-+		result = phydm_set_reg_by_fw(dm,
-+					     PHYDM_HALMAC_CMD_END,
-+					     0,
-+					     0,
-+					     0,
-+					     (enum rf_path)0,
-+					     0);
-+		PHYDM_DBG(dm, ODM_COMP_INIT,
-+			  "mac param offload end!result = %d", result);
-+	}
-+
-+	return result;
-+}
-+
-+u32 odm_get_hw_img_version(struct dm_struct *dm)
-+{
-+	u32 version = 0;
-+
-+	switch (dm->support_ic_type) {
-+/* @1 AP doesn't use PHYDM initialization in these ICs */
-+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+#if (RTL8821A_SUPPORT)
-+	case ODM_RTL8821:
-+		version = odm_get_version_mp_8821a_phy_reg();
-+		break;
-+#endif
-+#if (RTL8192E_SUPPORT)
-+	case ODM_RTL8192E:
-+		version = odm_get_version_mp_8192e_phy_reg();
-+		break;
-+#endif
-+#if (RTL8812A_SUPPORT)
-+	case ODM_RTL8812:
-+		version = odm_get_version_mp_8812a_phy_reg();
-+		break;
-+#endif
-+#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */
-+#if (RTL8723D_SUPPORT)
-+	case ODM_RTL8723D:
-+		version = odm_get_version_mp_8723d_phy_reg();
-+		break;
-+#endif
-+#if (RTL8710B_SUPPORT)
-+	case ODM_RTL8710B:
-+		version = odm_get_version_mp_8710b_phy_reg();
-+		break;
-+#endif
-+#if (RTL8188E_SUPPORT)
-+	case ODM_RTL8188E:
-+		version = odm_get_version_mp_8188e_phy_reg();
-+		break;
-+#endif
-+#if (RTL8723B_SUPPORT)
-+	case ODM_RTL8723B:
-+		version = odm_get_version_mp_8723b_phy_reg();
-+		break;
-+#endif
-+#if (RTL8814A_SUPPORT)
-+	case ODM_RTL8814A:
-+		version = odm_get_version_mp_8814a_phy_reg();
-+		break;
-+#endif
-+#if (RTL8703B_SUPPORT)
-+	case ODM_RTL8703B:
-+		version = odm_get_version_mp_8703b_phy_reg();
-+		break;
-+#endif
-+#if (RTL8188F_SUPPORT)
-+	case ODM_RTL8188F:
-+		version = odm_get_version_mp_8188f_phy_reg();
-+		break;
-+#endif
-+#if (RTL8822B_SUPPORT)
-+	case ODM_RTL8822B:
-+		version = odm_get_version_mp_8822b_phy_reg();
-+		break;
-+#endif
-+#if (RTL8197F_SUPPORT)
-+	case ODM_RTL8197F:
-+		version = odm_get_version_mp_8197f_phy_reg();
-+		break;
-+#endif
-+
-+#if (RTL8192F_SUPPORT)
-+	case ODM_RTL8192F:
-+		version = odm_get_version_mp_8192f_phy_reg();
-+		break;
-+#endif
-+#if (RTL8721D_SUPPORT)
-+	case ODM_RTL8721D:
-+		version = odm_get_version_mp_8721d_phy_reg();
-+		break;
-+#endif
-+#if (RTL8710C_SUPPORT)
-+	case ODM_RTL8710C:
-+		version = GET_VERSION_MP(8710c, _mac_reg);
-+#endif
-+#if (RTL8821C_SUPPORT)
-+	case ODM_RTL8821C:
-+		version = odm_get_version_mp_8821c_phy_reg();
-+		break;
-+#endif
-+#if (RTL8195B_SUPPORT)
-+	case ODM_RTL8195B:
-+		version = odm_get_version_mp_8195b_phy_reg();
-+		break;
-+#endif
-+#if (RTL8198F_SUPPORT)
-+	case ODM_RTL8198F:
-+		version = odm_get_version_mp_8198f_phy_reg();
-+		break;
-+#endif
-+#if (RTL8822C_SUPPORT)
-+	case ODM_RTL8822C:
-+		version = odm_get_version_mp_8822c_phy_reg();
-+		break;
-+#endif
-+#if (RTL8812F_SUPPORT)
-+	case ODM_RTL8812F:
-+		version = odm_get_version_mp_8812f_phy_reg();
-+		break;
-+#endif
-+#if (RTL8197G_SUPPORT)
-+	case ODM_RTL8197G:
-+		version = odm_get_version_mp_8197g_phy_reg();
-+		break;
-+#endif
-+#if (RTL8723F_SUPPORT)
-+	case ODM_RTL8723F:
-+		version = odm_get_version_mp_8723f_phy_reg();
-+		break;
-+#endif
-+#if (RTL8814B_SUPPORT)
-+	case ODM_RTL8814B:
-+		version = odm_get_version_mp_8814b_phy_reg();
-+		break;
-+#endif
-+	}
-+
-+	return version;
-+}
-+
-+u32 query_phydm_trx_capability(struct dm_struct *dm)
-+{
-+	u32 value32 = 0xFFFFFFFF;
-+
-+#if (RTL8821C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8821C)
-+		value32 = query_phydm_trx_capability_8821c(dm);
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8195B)
-+		value32 = query_phydm_trx_capability_8195b(dm);
-+#endif
-+	return value32;
-+}
-+
-+u32 query_phydm_stbc_capability(struct dm_struct *dm)
-+{
-+	u32 value32 = 0xFFFFFFFF;
-+
-+#if (RTL8821C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8821C)
-+		value32 = query_phydm_stbc_capability_8821c(dm);
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8195B)
-+		value32 = query_phydm_stbc_capability_8195b(dm);
-+#endif
-+
-+	return value32;
-+}
-+
-+u32 query_phydm_ldpc_capability(struct dm_struct *dm)
-+{
-+	u32 value32 = 0xFFFFFFFF;
-+
-+#if (RTL8821C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8821C)
-+		value32 = query_phydm_ldpc_capability_8821c(dm);
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8195B)
-+		value32 = query_phydm_ldpc_capability_8195b(dm);
-+#endif
-+	return value32;
-+}
-+
-+u32 query_phydm_txbf_parameters(struct dm_struct *dm)
-+{
-+	u32 value32 = 0xFFFFFFFF;
-+
-+#if (RTL8821C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8821C)
-+		value32 = query_phydm_txbf_parameters_8821c(dm);
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8195B)
-+		value32 = query_phydm_txbf_parameters_8195b(dm);
-+#endif
-+	return value32;
-+}
-+
-+u32 query_phydm_txbf_capability(struct dm_struct *dm)
-+{
-+	u32 value32 = 0xFFFFFFFF;
-+
-+#if (RTL8821C_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8821C)
-+		value32 = query_phydm_txbf_capability_8821c(dm);
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8195B)
-+		value32 = query_phydm_txbf_capability_8195b(dm);
-+#endif
-+	return value32;
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_hwconfig.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_hwconfig.h
-new file mode 100644
-index 000000000000..7c4d1e38cba4
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_hwconfig.h
-@@ -0,0 +1,79 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HALHWOUTSRC_H__
-+#define __HALHWOUTSRC_H__
-+
-+/*@--------------------------Define -------------------------------------------*/
-+#define AGC_DIFF_CONFIG_MP(ic, band)				\
-+	(odm_read_and_config_mp_##ic##_agc_tab_diff(dm,		\
-+	array_mp_##ic##_agc_tab_diff_##band,			\
-+	sizeof(array_mp_##ic##_agc_tab_diff_##band) / sizeof(u32)))
-+#define AGC_DIFF_CONFIG_TC(ic, band)				\
-+	(odm_read_and_config_tc_##ic##_agc_tab_diff(dm,		\
-+	array_tc_##ic##_agc_tab_diff_##band,			\
-+	sizeof(array_tc_##ic##_agc_tab_diff_##band) / sizeof(u32)))
-+#if defined(DM_ODM_CE_MAC80211)
-+#else
-+#define AGC_DIFF_CONFIG(ic, band)                     \
-+	do {                                          \
-+		if (dm->is_mp_chip)                   \
-+			AGC_DIFF_CONFIG_MP(ic, band); \
-+		else                                  \
-+			AGC_DIFF_CONFIG_TC(ic, band); \
-+	} while (0)
-+#endif
-+/*@************************************************************
-+ * structure and define
-+ ************************************************************/
-+
-+enum hal_status
-+odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm);
-+
-+enum hal_status
-+odm_config_rf_with_header_file(struct dm_struct *dm,
-+			       enum odm_rf_config_type config_type,
-+			       u8 e_rf_path);
-+
-+enum hal_status
-+odm_config_bb_with_header_file(struct dm_struct *dm,
-+			       enum odm_bb_config_type config_type);
-+
-+enum hal_status
-+odm_config_mac_with_header_file(struct dm_struct *dm);
-+
-+u32 odm_get_hw_img_version(struct dm_struct *dm);
-+
-+u32 query_phydm_trx_capability(struct dm_struct *dm);
-+
-+u32 query_phydm_stbc_capability(struct dm_struct *dm);
-+
-+u32 query_phydm_ldpc_capability(struct dm_struct *dm);
-+
-+u32 query_phydm_txbf_parameters(struct dm_struct *dm);
-+
-+u32 query_phydm_txbf_capability(struct dm_struct *dm);
-+
-+#endif /*@#ifndef	__HALHWOUTSRC_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_interface.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_interface.c
-new file mode 100644
-index 000000000000..7a0c42805950
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_interface.c
-@@ -0,0 +1,1480 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+/*@
-+ * ODM IO Relative API.
-+ */
-+
-+u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	struct rtl8192cd_priv *priv = dm->priv;
-+	return RTL_R8(reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+
-+	return rtl_read_byte(rtlpriv, reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+
-+	return rtw_read8(rtwdev, reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	void *adapter = dm->adapter;
-+	return rtw_read8(adapter, reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	return PlatformEFIORead1Byte(adapter, reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	void *adapter = dm->adapter;
-+
-+	return rtw_read8(adapter, reg_addr);
-+#endif
-+}
-+
-+u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	struct rtl8192cd_priv *priv = dm->priv;
-+	return RTL_R16(reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+
-+	return rtl_read_word(rtlpriv, reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+
-+	return rtw_read16(rtwdev, reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	void *adapter = dm->adapter;
-+	return rtw_read16(adapter, reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	return PlatformEFIORead2Byte(adapter, reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	void *adapter = dm->adapter;
-+
-+	return rtw_read16(adapter, reg_addr);
-+#endif
-+}
-+
-+u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	struct rtl8192cd_priv *priv = dm->priv;
-+	return RTL_R32(reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+
-+	return rtl_read_dword(rtlpriv, reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+
-+	return rtw_read32(rtwdev, reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	void *adapter = dm->adapter;
-+	return rtw_read32(adapter, reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	return PlatformEFIORead4Byte(adapter, reg_addr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	void *adapter = dm->adapter;
-+
-+	return rtw_read32(adapter, reg_addr);
-+#endif
-+}
-+
-+void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	struct rtl8192cd_priv *priv = dm->priv;
-+	RTL_W8(reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+
-+	rtl_write_byte(rtlpriv, reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+
-+	rtw_write8(rtwdev, reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	void *adapter = dm->adapter;
-+	rtw_write8(adapter, reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PlatformEFIOWrite1Byte(adapter, reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	void *adapter = dm->adapter;
-+
-+	rtw_write8(adapter, reg_addr, data);
-+#endif
-+
-+	if (dm->en_reg_mntr_byte)
-+		pr_debug("1byte:addr=0x%x, data=0x%x\n", reg_addr, data);
-+}
-+
-+void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	struct rtl8192cd_priv *priv = dm->priv;
-+	RTL_W16(reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+
-+	rtl_write_word(rtlpriv, reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+
-+	rtw_write16(rtwdev, reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	void *adapter = dm->adapter;
-+	rtw_write16(adapter, reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PlatformEFIOWrite2Byte(adapter, reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	void *adapter = dm->adapter;
-+
-+	rtw_write16(adapter, reg_addr, data);
-+#endif
-+
-+	if (dm->en_reg_mntr_byte)
-+		pr_debug("2byte:addr=0x%x, data=0x%x\n", reg_addr, data);
-+}
-+
-+void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	struct rtl8192cd_priv *priv = dm->priv;
-+	RTL_W32(reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+
-+	rtl_write_dword(rtlpriv, reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+
-+	rtw_write32(rtwdev, reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	void *adapter = dm->adapter;
-+	rtw_write32(adapter, reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PlatformEFIOWrite4Byte(adapter, reg_addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	void *adapter = dm->adapter;
-+
-+	rtw_write32(adapter, reg_addr, data);
-+#endif
-+
-+	if (dm->en_reg_mntr_byte)
-+		pr_debug("4byte:addr=0x%x, data=0x%x\n", reg_addr, data);
-+}
-+
-+void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PHY_SetBBReg(adapter, reg_addr, bit_mask, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+
-+	rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+
-+	rtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
-+#else
-+	phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
-+#endif
-+
-+	if (dm->en_reg_mntr_mac)
-+		pr_debug("MAC:addr=0x%x, mask=0x%x, data=0x%x\n",
-+			 reg_addr, bit_mask, data);
-+}
-+
-+u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	return phy_query_bb_reg(dm->priv, reg_addr, bit_mask);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	return PHY_QueryMacReg(dm->adapter, reg_addr, bit_mask);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+
-+	return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+
-+	return rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
-+#else
-+	return phy_query_mac_reg(dm->adapter, reg_addr, bit_mask);
-+#endif
-+}
-+
-+void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PHY_SetBBReg(adapter, reg_addr, bit_mask, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+
-+	rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+
-+	rtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
-+#else
-+	phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data);
-+#endif
-+
-+	if (dm->en_reg_mntr_bb)
-+		pr_debug("BB:addr=0x%x, mask=0x%x, data=0x%x\n",
-+			 reg_addr, bit_mask, data);
-+}
-+
-+u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	return phy_query_bb_reg(dm->priv, reg_addr, bit_mask);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	return PHY_QueryBBReg(adapter, reg_addr, bit_mask);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+
-+	return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+
-+	return rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
-+#else
-+	return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask);
-+#endif
-+}
-+
-+void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
-+		    u32 bit_mask, u32 data)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	phy_set_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PHY_SetRFReg(adapter, e_rf_path, reg_addr, bit_mask, data);
-+	ODM_delay_us(2);
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+
-+	rtl_set_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+
-+	rtw_write_rf(rtwdev, e_rf_path, reg_addr, bit_mask, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data);
-+	ODM_delay_us(2);
-+#endif
-+
-+	if (dm->en_reg_mntr_rf)
-+		pr_debug("RF:path=0x%x, addr=0x%x, mask=0x%x, data=0x%x\n",
-+			 e_rf_path, reg_addr, bit_mask, data);
-+}
-+
-+u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
-+		   u32 bit_mask)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	return phy_query_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, 1);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	return PHY_QueryRFReg(adapter, e_rf_path, reg_addr, bit_mask);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+
-+	return rtl_get_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+
-+	return rtw_read_rf(rtwdev, e_rf_path, reg_addr, bit_mask);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask);
-+#else
-+	return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask);
-+#endif
-+}
-+
-+enum hal_status
-+phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type,
-+		    u32 offset, u32 data, u32 mask, enum rf_path e_rf_path,
-+		    u32 delay_time)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+	return HAL_MAC_Config_PHY_WriteNByte(dm,
-+					     config_type,
-+					     offset,
-+					     data,
-+					     mask,
-+					     e_rf_path,
-+					     delay_time);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	return -ENOTSUPP;
-+#else
-+	return rtw_phydm_cfg_phy_para(dm,
-+				      config_type,
-+				      offset,
-+				      data,
-+				      mask,
-+				      e_rf_path,
-+				      delay_time);
-+#endif
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
-+#endif
-+}
-+
-+/*@
-+ * ODM Memory relative API.
-+ */
-+void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	*ptr = kmalloc(length, GFP_ATOMIC);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	*ptr = kmalloc(length, GFP_ATOMIC);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	*ptr = kmalloc(length, GFP_ATOMIC);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	*ptr = rtw_zvmalloc(length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PlatformAllocateMemory(adapter, ptr, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	*ptr = rtw_zvmalloc(length);
-+#endif
-+}
-+
-+/* @length could be ignored, used to detect memory leakage. */
-+void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	kfree(ptr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	kfree(ptr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	kfree(ptr);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	rtw_vmfree(ptr, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	/* struct void*    adapter = dm->adapter; */
-+	PlatformFreeMemory(ptr, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	rtw_vmfree(ptr, length);
-+#endif
-+}
-+
-+void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	memcpy(dest, src, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	memcpy(dest, src, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	memcpy(dest, src, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	_rtw_memcpy(dest, src, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	PlatformMoveMemory(dest, src, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	rtw_memcpy(dest, src, length);
-+#endif
-+}
-+
-+void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	memset(pbuf, value, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	memset(pbuf, value, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	memset(pbuf, value, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	_rtw_memset(pbuf, value, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	PlatformFillMemory(pbuf, length, value);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	rtw_memset(pbuf, value, length);
-+#endif
-+}
-+
-+s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2, u32 length)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	return memcmp(buf1, buf2, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	return memcmp(buf1, buf2, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	return memcmp(buf1, buf2, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	return _rtw_memcmp(buf1, buf2, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	return PlatformCompareMemory(buf1, buf2, length);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	return rtw_memcmp(buf1, buf2, length);
-+#endif
-+}
-+
-+/*@
-+ * ODM MISC relative API.
-+ */
-+void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+
-+	rtl_odm_acquirespinlock(rtlpriv, type);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+
-+	spin_lock(&rtwdev->hal.dm_lock);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	void *adapter = dm->adapter;
-+	rtw_odm_acquirespinlock(adapter, type);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PlatformAcquireSpinLock(adapter, type);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	void *adapter = dm->adapter;
-+
-+	rtw_odm_acquirespinlock(adapter, type);
-+#endif
-+}
-+
-+void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+
-+	rtl_odm_releasespinlock(rtlpriv, type);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+
-+	spin_unlock(&rtwdev->hal.dm_lock);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	void *adapter = dm->adapter;
-+	rtw_odm_releasespinlock(adapter, type);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PlatformReleaseSpinLock(adapter, type);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	void *adapter = dm->adapter;
-+
-+	rtw_odm_releasespinlock(adapter, type);
-+#endif
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+/*@
-+ * Work item relative API. FOr MP driver only~!
-+ *   */
-+void odm_initialize_work_item(
-+	struct dm_struct *dm,
-+	PRT_WORK_ITEM work_item,
-+	RT_WORKITEM_CALL_BACK callback,
-+	void *context,
-+	const char *id)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PlatformInitializeWorkItem(adapter, work_item, callback, context, id);
-+#endif
-+}
-+
-+void odm_start_work_item(
-+	PRT_WORK_ITEM p_rt_work_item)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	PlatformStartWorkItem(p_rt_work_item);
-+#endif
-+}
-+
-+void odm_stop_work_item(
-+	PRT_WORK_ITEM p_rt_work_item)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	PlatformStopWorkItem(p_rt_work_item);
-+#endif
-+}
-+
-+void odm_free_work_item(
-+	PRT_WORK_ITEM p_rt_work_item)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	PlatformFreeWorkItem(p_rt_work_item);
-+#endif
-+}
-+
-+void odm_schedule_work_item(
-+	PRT_WORK_ITEM p_rt_work_item)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	PlatformScheduleWorkItem(p_rt_work_item);
-+#endif
-+}
-+
-+boolean
-+odm_is_work_item_scheduled(
-+	PRT_WORK_ITEM p_rt_work_item)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	return PlatformIsWorkItemScheduled(p_rt_work_item);
-+#endif
-+}
-+#endif
-+
-+/*@
-+ * ODM Timer relative API.
-+ */
-+
-+void ODM_delay_ms(u32 ms)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	delay_ms(ms);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	mdelay(ms);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	mdelay(ms);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	rtw_mdelay_os(ms);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	delay_ms(ms);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	rtw_mdelay_os(ms);
-+#endif
-+}
-+
-+void ODM_delay_us(u32 us)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	delay_us(us);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	udelay(us);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	udelay(us);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	rtw_udelay_os(us);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	PlatformStallExecution(us);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	rtw_udelay_os(us);
-+#endif
-+}
-+
-+void ODM_sleep_ms(u32 ms)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	delay_ms(ms);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	msleep(ms);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	msleep(ms);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	rtw_msleep_os(ms);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	delay_ms(ms);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	rtw_msleep_os(ms);
-+#endif
-+}
-+
-+void ODM_sleep_us(u32 us)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	delay_us(us);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	usleep_range(us, us + 1);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	usleep_range(us, us + 1);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	rtw_usleep_os(us);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	PlatformStallExecution(us);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	rtw_usleep_os(us);
-+#endif
-+}
-+
-+void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
-+		   u32 ms_delay)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	mod_timer(timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(ms_delay));
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	mod_timer(timer, jiffies + msecs_to_jiffies(ms_delay));
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	mod_timer(&timer->timer, jiffies + msecs_to_jiffies(ms_delay));
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	_set_timer(timer, ms_delay); /* @ms */
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PlatformSetTimer(adapter, timer, ms_delay);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	rtw_set_timer(timer, ms_delay); /* @ms */
-+#endif
-+}
-+
-+void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
-+			  void *call_back_func, void *context,
-+			  const char *sz_id)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	init_timer(timer);
-+	timer->function = call_back_func;
-+	timer->data = (unsigned long)dm;
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	timer_setup(timer, call_back_func, 0);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	struct _ADAPTER *adapter = dm->adapter;
-+
-+	_init_timer(timer, adapter->pnetdev, call_back_func, dm);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+
-+	PlatformInitializeTimer(adapter, timer, (RT_TIMER_CALL_BACK)call_back_func, context, sz_id);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	struct _ADAPTER *adapter = dm->adapter;
-+
-+	rtw_init_timer(timer, adapter->pnetdev, (TIMER_FUN)call_back_func, dm, NULL);
-+#endif
-+}
-+
-+void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	del_timer(timer);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	del_timer(timer);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	del_timer(&timer->timer);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	_cancel_timer_ex(timer);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PlatformCancelTimer(adapter, timer);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	rtw_cancel_timer(timer);
-+#endif
-+}
-+
-+void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+
-+	void *adapter = dm->adapter;
-+
-+	/* @<20120301, Kordan> If the initilization fails,
-+	 * InitializeAdapterXxx will return regardless of InitHalDm.
-+	 * Hence, uninitialized timers cause BSOD when the driver
-+	 * releases resources since the init fail.
-+	 */
-+	if (timer == 0) {
-+		PHYDM_DBG(dm, ODM_COMP_INIT,
-+			  "[%s] Timer is NULL! Please check!\n", __func__);
-+		return;
-+	}
-+
-+	PlatformReleaseTimer(adapter, timer);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	rtw_del_timer(timer);
-+#endif
-+}
-+
-+u8 phydm_trans_h2c_id(struct dm_struct *dm, u8 phydm_h2c_id)
-+{
-+	u8 platform_h2c_id = phydm_h2c_id;
-+
-+	switch (phydm_h2c_id) {
-+	/* @1 [0] */
-+	case ODM_H2C_RSSI_REPORT:
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+		#if (RTL8188E_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8188E)
-+			platform_h2c_id = H2C_88E_RSSI_REPORT;
-+		else
-+		#endif
-+			platform_h2c_id = H2C_RSSI_REPORT;
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+		platform_h2c_id = H2C_RSSI_SETTING;
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
-+		if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES))
-+			platform_h2c_id = H2C_88XX_RSSI_REPORT;
-+		else
-+#endif
-+#if (RTL8812A_SUPPORT == 1)
-+			if (dm->support_ic_type == ODM_RTL8812)
-+			platform_h2c_id = H2C_8812_RSSI_REPORT;
-+		else
-+#endif
-+		{
-+		}
-+#endif
-+
-+		break;
-+
-+	/* @1 [3] */
-+	case ODM_H2C_WIFI_CALIBRATION:
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+		platform_h2c_id = H2C_WIFI_CALIBRATION;
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+#if (RTL8723B_SUPPORT == 1)
-+		platform_h2c_id = H2C_8723B_BT_WLAN_CALIBRATION;
-+#endif
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+#endif
-+		break;
-+
-+	/* @1 [4] */
-+	case ODM_H2C_IQ_CALIBRATION:
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+		platform_h2c_id = H2C_IQ_CALIBRATION;
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
-+		platform_h2c_id = H2C_8812_IQ_CALIBRATION;
-+#endif
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+#endif
-+
-+		break;
-+	/* @1 [5] */
-+	case ODM_H2C_RA_PARA_ADJUST:
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+		platform_h2c_id = H2C_RA_PARA_ADJUST;
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
-+		platform_h2c_id = H2C_8812_RA_PARA_ADJUST;
-+#elif ((RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1))
-+		platform_h2c_id = H2C_RA_PARA_ADJUST;
-+#elif (RTL8192E_SUPPORT == 1)
-+		platform_h2c_id = H2C_8192E_RA_PARA_ADJUST;
-+#elif (RTL8723B_SUPPORT == 1)
-+		platform_h2c_id = H2C_8723B_RA_PARA_ADJUST;
-+#endif
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
-+		if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES))
-+			platform_h2c_id = H2C_88XX_RA_PARA_ADJUST;
-+		else
-+#endif
-+#if (RTL8812A_SUPPORT == 1)
-+			if (dm->support_ic_type == ODM_RTL8812)
-+			platform_h2c_id = H2C_8812_RA_PARA_ADJUST;
-+		else
-+#endif
-+		{
-+		}
-+#endif
-+
-+		break;
-+
-+	/* @1 [6] */
-+	case PHYDM_H2C_DYNAMIC_TX_PATH:
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	#if (RTL8814A_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8814A)
-+			platform_h2c_id = H2C_8814A_DYNAMIC_TX_PATH;
-+	#endif
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+#if (RTL8814A_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8814A)
-+			platform_h2c_id = H2C_DYNAMIC_TX_PATH;
-+#endif
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+#if (RTL8814A_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8814A)
-+			platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH;
-+#endif
-+
-+#endif
-+
-+		break;
-+
-+	/* @[7]*/
-+	case PHYDM_H2C_FW_TRACE_EN:
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+
-+		platform_h2c_id = H2C_FW_TRACE_EN;
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+
-+		platform_h2c_id = 0x49;
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/
-+		if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES))
-+			platform_h2c_id = H2C_88XX_FW_TRACE_EN;
-+		else
-+#endif
-+#if (RTL8812A_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8812)
-+			platform_h2c_id = H2C_8812_FW_TRACE_EN;
-+		else
-+#endif
-+		{
-+		}
-+
-+#endif
-+
-+		break;
-+
-+	case PHYDM_H2C_TXBF:
-+#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1))
-+		if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812))
-+			platform_h2c_id = 0x41; /*@H2C_TxBF*/
-+#endif
-+		break;
-+
-+	case PHYDM_H2C_MU:
-+#if (RTL8822B_SUPPORT == 1)
-+		platform_h2c_id = 0x4a; /*@H2C_MU*/
-+#endif
-+		break;
-+
-+	default:
-+		platform_h2c_id = phydm_h2c_id;
-+		break;
-+	}
-+
-+	return platform_h2c_id;
-+}
-+
-+/*@ODM FW relative API.*/
-+
-+void odm_fill_h2c_cmd(struct dm_struct *dm, u8 phydm_h2c_id, u32 cmd_len,
-+		      u8 *cmd_buf)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	struct rtw_dev *rtwdev = dm->adapter;
-+	u8 cmd_id, cmd_class;
-+	u8 h2c_pkt[8];
-+#else
-+	void *adapter = dm->adapter;
-+#endif
-+	u8 h2c_id = phydm_trans_h2c_id(dm, phydm_h2c_id);
-+
-+	PHYDM_DBG(dm, DBG_RA, "[H2C]  h2c_id=((0x%x))\n", h2c_id);
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	if (dm->support_ic_type == ODM_RTL8188E) {
-+		if (!dm->ra_support88e)
-+			FillH2CCmd88E(adapter, h2c_id, cmd_len, cmd_buf);
-+	} else if (dm->support_ic_type == ODM_RTL8814A)
-+		FillH2CCmd8814A(adapter, h2c_id, cmd_len, cmd_buf);
-+	else if (dm->support_ic_type == ODM_RTL8822B)
-+		FillH2CCmd8822B(adapter, h2c_id, cmd_len, cmd_buf);
-+	else
-+		FillH2CCmd(adapter, h2c_id, cmd_len, cmd_buf);
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+
-+	#ifdef DM_ODM_CE_MAC80211
-+	rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->hw, h2c_id, cmd_len, cmd_buf);
-+	#elif defined(DM_ODM_CE_MAC80211_V2)
-+	cmd_id = phydm_h2c_id & 0x1f;
-+	cmd_class = (phydm_h2c_id >> RTW_H2C_CLASS_OFFSET) & 0x7;
-+	memcpy(h2c_pkt + 1, cmd_buf, 7);
-+	h2c_pkt[0] = phydm_h2c_id;
-+	rtw_fw_send_h2c_packet(rtwdev, h2c_pkt, cmd_id, cmd_class);
-+	/* TODO: implement fill h2c command for rtwlan */
-+	#else
-+	rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf);
-+	#endif
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+
-+	#if (RTL8812A_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8812) {
-+		fill_h2c_cmd8812(dm->priv, h2c_id, cmd_len, cmd_buf);
-+	} else
-+	#endif
-+	{
-+		GET_HAL_INTERFACE(dm->priv)->fill_h2c_cmd_handler(dm->priv, h2c_id, cmd_len, cmd_buf);
-+	}
-+
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf);
-+
-+#endif
-+}
-+
-+u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
-+			     u8 *tmp_buf)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter = dm->adapter;
-+#endif
-+	u8 extend_c2h_sub_id = 0;
-+	u8 find_c2h_cmd = true;
-+
-+	if (c2h_cmd_len > 12 || c2h_cmd_len == 0) {
-+		pr_debug("[Warning] Error C2H ID=%d, len=%d\n",
-+			 c2h_cmd_id, c2h_cmd_len);
-+
-+		find_c2h_cmd = false;
-+		return find_c2h_cmd;
-+	}
-+
-+	switch (c2h_cmd_id) {
-+	case PHYDM_C2H_DBG:
-+		phydm_fw_trace_handler(dm, tmp_buf, c2h_cmd_len);
-+		break;
-+
-+	case PHYDM_C2H_RA_RPT:
-+		phydm_c2h_ra_report_handler(dm, tmp_buf, c2h_cmd_len);
-+		break;
-+
-+	case PHYDM_C2H_RA_PARA_RPT:
-+		odm_c2h_ra_para_report_handler(dm, tmp_buf, c2h_cmd_len);
-+		break;
-+#ifdef CONFIG_PATH_DIVERSITY
-+	case PHYDM_C2H_DYNAMIC_TX_PATH_RPT:
-+		if (dm->support_ic_type & (ODM_RTL8814A))
-+			phydm_c2h_dtp_handler(dm, tmp_buf, c2h_cmd_len);
-+		break;
-+#endif
-+
-+	case PHYDM_C2H_IQK_FINISH:
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+		if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) {
-+			RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Finish ==\n"));
-+			odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
-+			dm->rf_calibrate_info.is_iqk_in_progress = false;
-+			odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
-+			dm->rf_calibrate_info.iqk_progressing_time = 0;
-+			dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time);
-+		}
-+
-+#endif
-+		break;
-+
-+	case PHYDM_C2H_CLM_MONITOR:
-+		phydm_clm_c2h_report_handler(dm, tmp_buf, c2h_cmd_len);
-+		break;
-+
-+	case PHYDM_C2H_DBG_CODE:
-+		phydm_fw_trace_handler_code(dm, tmp_buf, c2h_cmd_len);
-+		break;
-+
-+	case PHYDM_C2H_EXTEND:
-+		extend_c2h_sub_id = tmp_buf[0];
-+		if (extend_c2h_sub_id == PHYDM_EXTEND_C2H_DBG_PRINT)
-+			phydm_fw_trace_handler_8051(dm, tmp_buf, c2h_cmd_len);
-+
-+		break;
-+
-+	default:
-+		find_c2h_cmd = false;
-+		break;
-+	}
-+
-+	return find_c2h_cmd;
-+}
-+
-+u64 odm_get_current_time(struct dm_struct *dm)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	return (u64)rtw_get_current_time();
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	return jiffies;
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	return jiffies;
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	return rtw_get_current_time();
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	return PlatformGetCurrentTime();
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	return rtw_get_current_time();
-+#endif
-+}
-+
-+u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	return rtw_get_passing_time_ms((u32)start_time);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	return jiffies_to_msecs(jiffies - start_time);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	return jiffies_to_msecs(jiffies - start_time);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	return rtw_get_passing_time_ms((systime)start_time);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	return ((PlatformGetCurrentTime() - start_time) >> 10);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	return rtw_get_passing_time_ms(start_time);
-+#endif
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \
-+	(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
-+
-+void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 RegName,
-+					u8 *val)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	struct _ADAPTER *adapter = dm->adapter;
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	((PADAPTER)adapter)->HalFunc.SetHwRegHandler(adapter, RegName, val);
-+#else
-+	adapter->hal_func.set_hw_reg_handler(adapter, RegName, val);
-+#endif
-+
-+#endif
-+}
-+
-+void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm,
-+					     enum _HAL_DEF_VARIABLE e_variable,
-+					     void *value)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	struct _ADAPTER *adapter = dm->adapter;
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	((PADAPTER)adapter)->HalFunc.GetHalDefVarHandler(adapter, e_variable, value);
-+#else
-+	adapter->hal_func.get_hal_def_var_handler(adapter, e_variable, value);
-+#endif
-+
-+#endif
-+}
-+
-+#endif
-+
-+void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm,
-+					    enum rf_path path, u8 ch,
-+					    u8 section)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+	PHY_SetTxPowerIndexByRateSection(adapter, path, ch, section);
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	void *adapter = dm->adapter;
-+
-+	phy_set_tx_power_index_by_rs(adapter, ch, path, section);
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	phy_set_tx_power_index_by_rate_section(dm->adapter, path, ch, section);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	void *adapter = dm->adapter;
-+
-+	PHY_SetTxPowerIndexByRateSection(adapter, path, ch, section);
-+#endif
-+}
-+
-+u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 rate,
-+			  u8 bw, u8 ch)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+
-+	return PHY_GetTxPowerIndex(dm->adapter, path, rate, (CHANNEL_WIDTH)bw, ch);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	void *adapter = dm->adapter;
-+
-+	return phy_get_tx_power_index(adapter, path, rate, bw, ch);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	void *adapter = dm->adapter;
-+
-+	return phy_get_tx_power_index(adapter, path, rate, bw, ch);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	return phy_get_tx_power_index(dm->adapter, path, rate, bw, ch);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	void *adapter = dm->adapter;
-+
-+	return PHY_GetTxPowerIndex(dm->adapter, path, rate, bw, ch);
-+#endif
-+}
-+
-+u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data,
-+			   boolean b_pseu_do_test)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+
-+	return (u8)EFUSE_OneByteRead(adapter, addr, data, b_pseu_do_test);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	void *adapter = dm->adapter;
-+
-+	return rtl_efuse_onebyte_read(adapter, addr, data, b_pseu_do_test);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+	return -1;
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	return efuse_onebyte_read(dm->adapter, addr, data, b_pseu_do_test);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
-+	return Efuse_OneByteRead(dm, addr, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	void *adapter = dm->adapter;
-+
-+	return (u8)efuse_OneByteRead(adapter, addr, data, b_pseu_do_test);
-+#endif
-+}
-+
-+void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset,
-+				u32 *data)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	void *adapter = dm->adapter;
-+
-+	EFUSE_ShadowRead(adapter, type, offset, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	void *adapter = dm->adapter;
-+
-+	rtl_efuse_logical_map_read(adapter, type, offset, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	efuse_logical_map_read(dm->adapter, type, offset, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	void *adapter = dm->adapter;
-+
-+	EFUSE_ShadowRead(adapter, type, offset, data);
-+#endif
-+}
-+
-+enum hal_status
-+odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment)
-+{
-+	enum hal_status iqk_result = HAL_STATUS_FAILURE;
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	struct _ADAPTER *adapter = dm->adapter;
-+
-+	if (HAL_MAC_FWIQK_Trigger(&GET_HAL_MAC_INFO(adapter), clear, segment) == 0)
-+		iqk_result = HAL_STATUS_SUCCESS;
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	void *adapter = dm->adapter;
-+
-+	iqk_result = rtl_phydm_fw_iqk(adapter, clear, segment);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+#else
-+	iqk_result = rtw_phydm_fw_iqk(dm, clear, segment);
-+#endif
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
-+	iqk_result = rtw_phydm_fw_iqk(dm, clear, segment);
-+#endif
-+	return iqk_result;
-+}
-+
-+enum hal_status
-+odm_dpk_by_fw(struct dm_struct *dm)
-+{
-+	enum hal_status dpk_result = HAL_STATUS_FAILURE;
-+#if 0
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	struct _ADAPTER *adapter = dm->adapter;
-+
-+	if (hal_mac_fwdpk_trigger(&GET_HAL_MAC_INFO(adapter)) == 0)
-+		dpk_result = HAL_STATUS_SUCCESS;
-+#else
-+	dpk_result = rtw_phydm_fw_dpk(dm);
-+#endif
-+
-+#endif
-+	return dpk_result;
-+}
-+
-+void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 mac_id,
-+			     struct cmn_sta_info *pcmn_sta_info)
-+{
-+	dm->phydm_sta_info[mac_id] = pcmn_sta_info;
-+
-+	if (is_sta_active(pcmn_sta_info))
-+		dm->phydm_macid_table[pcmn_sta_info->mac_id] = mac_id;
-+}
-+
-+void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx,
-+			       struct cmn_sta_info *pcmn_sta_info)
-+{
-+	if (is_sta_active(pcmn_sta_info))
-+		dm->phydm_macid_table[pcmn_sta_info->mac_id] = entry_idx;
-+}
-+
-+void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+
-+	struct rtl8192cd_priv *priv = dm->priv;
-+
-+	#if IS_EXIST_PCI || IS_EXIST_EMBEDDED
-+	if (dm->support_interface == ODM_ITRF_PCIE)
-+		GET_HAL_INTERFACE(priv)->AddInterruptMaskHandler(priv,
-+								 interrupt_type)
-+								 ;
-+	#endif
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+#endif
-+}
-+
-+void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+
-+	struct rtl8192cd_priv *priv = dm->priv;
-+
-+	#if IS_EXIST_PCI || IS_EXIST_EMBEDDED
-+	if (dm->support_interface == ODM_ITRF_PCIE)
-+		GET_HAL_INTERFACE(priv)->EnableRxRelatedInterruptHandler(priv);
-+	#endif
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+#endif
-+}
-+
-+void phydm_iqk_wait(struct dm_struct *dm, u32 timeout)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+#else
-+	void *adapter = dm->adapter;
-+
-+	rtl8812_iqk_wait(adapter, timeout);
-+#endif
-+#endif
-+}
-+
-+u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+	return HwRateToMRate(rate);
-+#endif
-+	return 0;
-+}
-+
-+void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+	ROM_odm_SetCrystalCap(dm, crystal_cap);
-+#endif
-+}
-+
-+void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),
-+			     void *context)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+	PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n");
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	void *adapter = dm->adapter;
-+
-+	rtw_run_in_thread_cmd(adapter, func, context);
-+#endif
-+}
-+
-+u8 phydm_get_tx_rate(struct dm_struct *dm)
-+{
-+	struct _hal_rf_ *rf = &dm->rf_table;
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	struct _ADAPTER *adapter = dm->adapter;
-+#endif
-+	u8 tx_rate = 0xff;
-+	u8 mpt_rate_index = 0;
-+
-+	if (*dm->mp_mode == 1) {
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+#if (MP_DRIVER == 1)
-+		PMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx;
-+
-+		tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
-+#endif
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+#ifdef CONFIG_MP_INCLUDED
-+		if (rf->mp_rate_index)
-+			mpt_rate_index = *rf->mp_rate_index;
-+
-+		tx_rate = mpt_to_mgnt_rate(mpt_rate_index);
-+#endif
-+#endif
-+#endif
-+	} else {
-+		u16 rate = *dm->forced_data_rate;
-+
-+		if (!rate) { /*auto rate*/
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+			struct _ADAPTER *adapter = dm->adapter;
-+
-+			tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+			tx_rate = dm->tx_rate;
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+			if (dm->number_linked_client != 0)
-+				tx_rate = hw_rate_to_m_rate(dm->tx_rate);
-+			else
-+				tx_rate = rf->p_rate_index;
-+#endif
-+		} else { /*force rate*/
-+			tx_rate = (u8)rate;
-+		}
-+	}
-+
-+	return tx_rate;
-+}
-+
-+u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path,
-+					u8 rate, u8 bandwidth, u8 channel)
-+{
-+	u8 tx_power_dbm = 0;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct _ADAPTER *adapter = dm->adapter;
-+	tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValue(adapter, rf_path, rate, bandwidth, channel);
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	tx_power_dbm = phy_get_tx_power_final_absolute_value(dm->adapter, rf_path, rate, bandwidth, channel);
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValue(dm, rf_path, rate, bandwidth, channel);
-+#endif
-+	return tx_power_dbm;
-+}
-+
-+s16 phydm_get_tx_power_mdbm(struct dm_struct *dm, u8 rf_path,
-+					u8 rate, u8 bandwidth, u8 channel)
-+{
-+	s16 tx_power_dbm = 0;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct _ADAPTER *adapter = dm->adapter;
-+	tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValuemdBm(adapter, rf_path, rate, bandwidth, channel);
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	tx_power_dbm = rtw_odm_get_tx_power_mbm(dm, rf_path, rate, bandwidth, channel);
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValuembm(dm, rf_path, rate, bandwidth, channel);
-+#endif
-+	return tx_power_dbm;
-+}
-+
-+u32 phydm_rfe_ctrl_gpio(struct dm_struct *dm, u8 gpio_num)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	return rtw_phydm_rfe_ctrl_gpio(dm->adapter, gpio_num);
-+#endif
-+	return 0;
-+}
-+
-+u64 phydm_division64(u64 x, u64 y)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	do_div(x, y); 
-+	return x;
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	return x / y;
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	return rtw_division64(x, y);
-+#endif
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_interface.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_interface.h
-new file mode 100644
-index 000000000000..2c75a23c77aa
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_interface.h
-@@ -0,0 +1,328 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __ODM_INTERFACE_H__
-+#define __ODM_INTERFACE_H__
-+
-+#define INTERFACE_VERSION "1.2"
-+
-+#define pdm_set_reg odm_set_bb_reg
-+
-+/*@=========== Constant/Structure/Enum/... Define*/
-+
-+enum phydm_h2c_cmd {
-+	PHYDM_H2C_RA_MASK		= 0x40,
-+	PHYDM_H2C_TXBF			= 0x41,
-+	ODM_H2C_RSSI_REPORT		= 0x42,
-+	ODM_H2C_IQ_CALIBRATION		= 0x45,
-+	PHYDM_RA_MASK_ABOVE_3SS		= 0x46,
-+	ODM_H2C_RA_PARA_ADJUST		= 0x47,
-+	PHYDM_H2C_DYNAMIC_TX_PATH	= 0x48,
-+	PHYDM_H2C_FW_TRACE_EN		= 0x49,
-+	ODM_H2C_WIFI_CALIBRATION	= 0x6d,
-+	PHYDM_H2C_MU			= 0x4a,
-+	PHYDM_H2C_FW_GENERAL_INIT	= 0x4c,
-+	PHYDM_H2C_FW_CLM_MNTR		= 0x4d,
-+	PHYDM_H2C_MCC			= 0x4f,
-+	PHYDM_H2C_RESP_TX_PATH_CTRL	= 0x50,
-+	PHYDM_H2C_RESP_TX_ANT_CTRL	= 0x51,
-+	PHYDM_H2C_FW_DM_CTRL		= 0x55,
-+	ODM_MAX_H2CCMD
-+};
-+
-+enum phydm_c2h_evt {
-+	PHYDM_C2H_DBG =		0,
-+	PHYDM_C2H_LB =		1,
-+	PHYDM_C2H_XBF =		2,
-+	PHYDM_C2H_TX_REPORT =	3,
-+	PHYDM_C2H_INFO =	9,
-+	PHYDM_C2H_BT_MP =	11,
-+	PHYDM_C2H_RA_RPT =	12,
-+	PHYDM_C2H_RA_PARA_RPT = 14,
-+	PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15,
-+	PHYDM_C2H_IQK_FINISH =	17, /*@0x11*/
-+	PHYDM_C2H_CLM_MONITOR =	0x2a,
-+	PHYDM_C2H_DBG_CODE =	0xFE,
-+	PHYDM_C2H_EXTEND =	0xFF,
-+};
-+
-+enum phydm_extend_c2h_evt {
-+	PHYDM_EXTEND_C2H_DBG_PRINT = 0
-+
-+};
-+
-+enum phydm_halmac_param {
-+	PHYDM_HALMAC_CMD_MAC_W8 = 0,
-+	PHYDM_HALMAC_CMD_MAC_W16 = 1,
-+	PHYDM_HALMAC_CMD_MAC_W32 = 2,
-+	PHYDM_HALMAC_CMD_BB_W8,
-+	PHYDM_HALMAC_CMD_BB_W16,
-+	PHYDM_HALMAC_CMD_BB_W32,
-+	PHYDM_HALMAC_CMD_RF_W,
-+	PHYDM_HALMAC_CMD_DELAY_US,
-+	PHYDM_HALMAC_CMD_DELAY_MS,
-+	PHYDM_HALMAC_CMD_END = 0XFF,
-+};
-+
-+/*@=========== Macro Define*/
-+
-+#define _reg_all(_name)			ODM_##_name
-+#define _reg_ic(_name, _ic)		ODM_##_name##_ic
-+#define _bit_all(_name)			BIT_##_name
-+#define _bit_ic(_name, _ic)		BIT_##_name##_ic
-+
-+#if defined(DM_ODM_CE_MAC80211)
-+#define ODM_BIT(name, dm)				\
-+	((dm->support_ic_type & ODM_IC_11N_SERIES) ?	\
-+	 ODM_BIT_##name##_11N : ODM_BIT_##name##_11AC)
-+
-+#define ODM_REG(name, dm)				\
-+	((dm->support_ic_type & ODM_IC_11N_SERIES) ?	\
-+	 ODM_REG_##name##_11N : ODM_REG_##name##_11AC)
-+#else
-+#define _reg_11N(_name)			ODM_REG_##_name##_11N
-+#define _reg_11AC(_name)		ODM_REG_##_name##_11AC
-+#define _bit_11N(_name)			ODM_BIT_##_name##_11N
-+#define _bit_11AC(_name)		ODM_BIT_##_name##_11AC
-+
-+#ifdef __ECOS
-+#define _rtk_cat(_name, _ic_type, _func)                                \
-+	(                                                               \
-+		((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
-+						   _func##_11AC(_name))
-+#else
-+
-+#define _cat(_name, _ic_type, _func)                                    \
-+	(                                                               \
-+		((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
-+						   _func##_11AC(_name))
-+#endif
-+/*@
-+ * only sample code
-+ *#define _cat(_name, _ic_type, _func)					\
-+ *	(								\
-+ *		((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) :\
-+ *		_func##_ic(_name, _8195)				\
-+ *	)
-+ */
-+
-+/* @_name: name of register or bit.
-+ * Example: "ODM_REG(R_A_AGC_CORE1, dm)"
-+ * gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C",
-+ * depends on support_ic_type.
-+ */
-+#ifdef __ECOS
-+	#define ODM_REG(_name, _pdm_odm)	\
-+		_rtk_cat(_name, _pdm_odm->support_ic_type, _reg)
-+	#define ODM_BIT(_name, _pdm_odm)	\
-+		_rtk_cat(_name, _pdm_odm->support_ic_type, _bit)
-+#else
-+	#define ODM_REG(_name, _pdm_odm)	\
-+		_cat(_name, _pdm_odm->support_ic_type, _reg)
-+	#define ODM_BIT(_name, _pdm_odm)	\
-+		_cat(_name, _pdm_odm->support_ic_type, _bit)
-+#endif
-+
-+#endif
-+/*@
-+ * =========== Extern Variable ??? It should be forbidden.
-+ */
-+
-+/*@
-+ * =========== EXtern Function Prototype
-+ */
-+
-+u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr);
-+
-+u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr);
-+
-+u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr);
-+
-+void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data);
-+
-+void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data);
-+
-+void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data);
-+
-+void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask,
-+		     u32 data);
-+
-+u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask);
-+
-+void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data);
-+
-+u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask);
-+
-+void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
-+		    u32 bit_mask, u32 data);
-+
-+u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
-+		   u32 bit_mask);
-+
-+/*@
-+ * Memory Relative Function.
-+ */
-+void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length);
-+void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length);
-+
-+void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length);
-+
-+s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2,
-+		       u32 length);
-+
-+void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length);
-+
-+/*@
-+ * ODM MISC-spin lock relative API.
-+ */
-+void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type);
-+
-+void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type);
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+/*@
-+ * ODM MISC-workitem relative API.
-+ */
-+void odm_initialize_work_item(
-+	struct dm_struct *dm,
-+	PRT_WORK_ITEM p_rt_work_item,
-+	RT_WORKITEM_CALL_BACK rt_work_item_callback,
-+	void *context,
-+	const char *sz_id);
-+
-+void odm_start_work_item(
-+	PRT_WORK_ITEM p_rt_work_item);
-+
-+void odm_stop_work_item(
-+	PRT_WORK_ITEM p_rt_work_item);
-+
-+void odm_free_work_item(
-+	PRT_WORK_ITEM p_rt_work_item);
-+
-+void odm_schedule_work_item(
-+	PRT_WORK_ITEM p_rt_work_item);
-+
-+boolean
-+odm_is_work_item_scheduled(
-+	PRT_WORK_ITEM p_rt_work_item);
-+#endif
-+
-+/*@
-+ * ODM Timer relative API.
-+ */
-+void ODM_delay_ms(u32 ms);
-+
-+void ODM_delay_us(u32 us);
-+
-+void ODM_sleep_ms(u32 ms);
-+
-+void ODM_sleep_us(u32 us);
-+
-+void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
-+		   u32 ms_delay);
-+
-+void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
-+			  void *call_back_func, void *context,
-+			  const char *sz_id);
-+
-+void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer);
-+
-+void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer);
-+
-+/*ODM FW relative API.*/
-+
-+enum hal_status
-+phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type,
-+		    u32 offset, u32 data, u32 mask, enum rf_path e_rf_path,
-+		    u32 delay_time);
-+
-+void odm_fill_h2c_cmd(struct dm_struct *dm, u8 element_id, u32 cmd_len,
-+		      u8 *cmd_buffer);
-+
-+u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
-+			     u8 *tmp_buf);
-+
-+u64 odm_get_current_time(struct dm_struct *dm);
-+u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time);
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \
-+	(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
-+
-+void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 reg_Name,
-+					u8 *val);
-+
-+void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm,
-+					     enum _HAL_DEF_VARIABLE e_variable,
-+					     void *value);
-+
-+#endif
-+
-+void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm,
-+					    enum rf_path path, u8 channel,
-+					    u8 rate_section);
-+
-+u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 tx_rate,
-+			  u8 band_width, u8 channel);
-+
-+u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data,
-+			   boolean b_pseu_do_test);
-+
-+void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset,
-+				u32 *data);
-+
-+enum hal_status
-+odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment);
-+
-+enum hal_status
-+odm_dpk_by_fw(struct dm_struct *dm);
-+
-+void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 index,
-+			     struct cmn_sta_info *pcmn_sta_info);
-+
-+void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx,
-+			       struct cmn_sta_info *pcmn_sta_info);
-+
-+void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type);
-+
-+void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm);
-+
-+void phydm_iqk_wait(struct dm_struct *dm, u32 timeout);
-+u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate);
-+
-+void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap);
-+void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),
-+			     void *context);
-+u8 phydm_get_tx_rate(struct dm_struct *dm);
-+u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path,
-+					u8 rate, u8 bandwidth, u8 channel);
-+
-+s16 phydm_get_tx_power_mdbm(struct dm_struct *dm, u8 rf_path,
-+					u8 rate, u8 bandwidth, u8 channel);
-+
-+u32 phydm_rfe_ctrl_gpio(struct dm_struct *dm, u8 gpio_num);
-+
-+u64 phydm_division64(u64 x, u64 y);
-+
-+#endif /* @__ODM_INTERFACE_H__ */
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_lna_sat.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_lna_sat.c
-new file mode 100644
-index 000000000000..f48ae5c798d6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_lna_sat.c
-@@ -0,0 +1,1688 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*************************************************************
-+ * include files
-+ * *************************************************************/
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+
-+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+void phydm_lna_sat_chk_init(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
-+
-+	lna_info->check_time = 0;
-+	lna_info->sat_cnt_acc_patha = 0;
-+	lna_info->sat_cnt_acc_pathb = 0;
-+	#ifdef PHYDM_IC_ABOVE_3SS
-+	lna_info->sat_cnt_acc_pathc = 0;
-+	#endif
-+	#ifdef PHYDM_IC_ABOVE_4SS
-+	lna_info->sat_cnt_acc_pathd = 0;
-+	#endif
-+	lna_info->cur_sat_status = 0;
-+	lna_info->pre_sat_status = 0;
-+	lna_info->cur_timer_check_cnt = 0;
-+	lna_info->pre_timer_check_cnt = 0;
-+
-+	#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
-+		phydm_lna_sat_chk_bb_init(dm);
-+	#endif
-+}
-+
-+#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
-+void phydm_lna_sat_chk_bb_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
-+
-+	boolean disable_bb_switch_tab = false;
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
-+
-+	/*@set table switch mux r_6table_sel_anten*/
-+	odm_set_bb_reg(dm, 0x18ac, BIT(8), 0);
-+
-+	/*@tab decision when idle*/
-+	odm_set_bb_reg(dm, 0x18ac, BIT(16), disable_bb_switch_tab);
-+	odm_set_bb_reg(dm, 0x41ac, BIT(16), disable_bb_switch_tab);
-+	odm_set_bb_reg(dm, 0x52ac, BIT(16), disable_bb_switch_tab);
-+	odm_set_bb_reg(dm, 0x53ac, BIT(16), disable_bb_switch_tab);
-+	/*@tab decision when ofdmcca*/
-+	odm_set_bb_reg(dm, 0x18ac, BIT(17), disable_bb_switch_tab);
-+	odm_set_bb_reg(dm, 0x41ac, BIT(17), disable_bb_switch_tab);
-+	odm_set_bb_reg(dm, 0x52ac, BIT(17), disable_bb_switch_tab);
-+	odm_set_bb_reg(dm, 0x53ac, BIT(17), disable_bb_switch_tab);
-+}
-+
-+void phydm_set_ofdm_agc_tab_path(
-+	void *dm_void,
-+	u8 tab_sel,
-+	enum rf_path path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
-+	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) {
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "set AGC Tab%d\n", tab_sel);
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "r_6table_sel_anten = 0x%x\n",
-+			  odm_get_bb_reg(dm, 0x18ac, BIT(8)));
-+	}
-+
-+	if (dm->support_ic_type & ODM_RTL8198F) {
-+		/*@table sel:0/2, mapping 2 to 1 */
-+		if (tab_sel == OFDM_AGC_TAB_0) {
-+			odm_set_bb_reg(dm, 0x18ac, BIT(4), 0);
-+			odm_set_bb_reg(dm, 0x41ac, BIT(4), 0);
-+			odm_set_bb_reg(dm, 0x52ac, BIT(4), 0);
-+			odm_set_bb_reg(dm, 0x53ac, BIT(4), 0);
-+		} else if (tab_sel == OFDM_AGC_TAB_2) {
-+			odm_set_bb_reg(dm, 0x18ac, BIT(4), 1);
-+			odm_set_bb_reg(dm, 0x41ac, BIT(4), 1);
-+			odm_set_bb_reg(dm, 0x52ac, BIT(4), 1);
-+			odm_set_bb_reg(dm, 0x53ac, BIT(4), 1);
-+		} else {
-+			odm_set_bb_reg(dm, 0x18ac, BIT(4), 0);
-+			odm_set_bb_reg(dm, 0x41ac, BIT(4), 0);
-+			odm_set_bb_reg(dm, 0x52ac, BIT(4), 0);
-+			odm_set_bb_reg(dm, 0x53ac, BIT(4), 0);
-+		}
-+	} else if (dm->support_ic_type & ODM_RTL8814B) {
-+		if (tab_sel == OFDM_AGC_TAB_0) {
-+			odm_set_bb_reg(dm, 0x18ac, 0xf0, 0);
-+			odm_set_bb_reg(dm, 0x41ac, 0xf0, 0);
-+			odm_set_bb_reg(dm, 0x52ac, 0xf0, 0);
-+			odm_set_bb_reg(dm, 0x53ac, 0xf0, 0);
-+		} else if (tab_sel == OFDM_AGC_TAB_2) {
-+			odm_set_bb_reg(dm, 0x18ac, 0xf0, 2);
-+			odm_set_bb_reg(dm, 0x41ac, 0xf0, 2);
-+			odm_set_bb_reg(dm, 0x52ac, 0xf0, 2);
-+			odm_set_bb_reg(dm, 0x53ac, 0xf0, 2);
-+		} else {
-+			odm_set_bb_reg(dm, 0x18ac, 0xf0, 0);
-+			odm_set_bb_reg(dm, 0x41ac, 0xf0, 0);
-+			odm_set_bb_reg(dm, 0x52ac, 0xf0, 0);
-+			odm_set_bb_reg(dm, 0x53ac, 0xf0, 0);
-+		}
-+	}
-+}
-+
-+u8 phydm_get_ofdm_agc_tab_path(
-+	void *dm_void,
-+	enum rf_path path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 tab_sel = 0;
-+
-+	if (dm->support_ic_type & ODM_RTL8198F) {
-+		tab_sel = (u8)odm_get_bb_reg(dm, R_0x18ac, BIT(4));
-+		if (tab_sel == 0)
-+			tab_sel = OFDM_AGC_TAB_0;
-+		else if (tab_sel == 1)
-+			tab_sel = OFDM_AGC_TAB_2;
-+	} else if (dm->support_ic_type & ODM_RTL8814B) {
-+		tab_sel = (u8)odm_get_bb_reg(dm, R_0x18ac, 0xf0);
-+		if (tab_sel == 0)
-+			tab_sel = OFDM_AGC_TAB_0;
-+		else if (tab_sel == 2)
-+			tab_sel = OFDM_AGC_TAB_2;
-+	}
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "get path %d AGC Tab %d\n",
-+		  path, tab_sel);
-+	return tab_sel;
-+}
-+#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/
-+
-+void phydm_set_ofdm_agc_tab(
-+	void *dm_void,
-+	u8 tab_sel)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	/*@table sel:0/2, 1 is used for CCK */
-+	if (tab_sel == OFDM_AGC_TAB_0)
-+		odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_0);
-+	else if (tab_sel == OFDM_AGC_TAB_2)
-+		odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_2);
-+	else
-+		odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_0);
-+}
-+
-+u8 phydm_get_ofdm_agc_tab(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	return (u8)odm_get_bb_reg(dm, R_0xc70, 0x1e00);
-+}
-+
-+void phydm_lna_sat_chk(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
-+	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
-+	u8 igi_rssi_min;
-+	u8 rssi_min = dm->rssi_min;
-+	u32 sat_status_a, sat_status_b;
-+	#ifdef PHYDM_IC_ABOVE_3SS
-+	u32 sat_status_c;
-+	#endif
-+	#ifdef PHYDM_IC_ABOVE_4SS
-+	u32 sat_status_d;
-+	#endif
-+	u8 igi_restore = dig_t->cur_ig_value;
-+	u8 i, chk_cnt = lna_info->chk_cnt;
-+	u32 lna_sat_cnt_thd = 0;
-+	u8 agc_tab;
-+	u32 max_check_time = 0;
-+	/*@use rssi_max if rssi_min is not stable;*/
-+	/*@rssi_min = dm->rssi_max;*/
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __func__);
-+
-+	if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) {
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Func disable\n");
-+		return;
-+	}
-+
-+	if (lna_info->is_disable_lna_sat_chk) {
-+		phydm_lna_sat_chk_init(dm);
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "disable_lna_sat_chk\n");
-+		return;
-+	}
-+
-+	/*@move igi to target pin of rssi_min */
-+	if (rssi_min == 0 || rssi_min == 0xff) {
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+			  "rssi_min=%d, set AGC Tab0\n", rssi_min);
-+		/*@adapt agc table 0*/
-+		phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);
-+		phydm_lna_sat_chk_init(dm);
-+		return;
-+	} else if (rssi_min % 2 != 0) {
-+		igi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI - 1;
-+	} else {
-+		igi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI;
-+	}
-+
-+	if ((lna_info->chk_period > 0) && (lna_info->chk_period <= ONE_SEC_MS))
-+		max_check_time = chk_cnt * (ONE_SEC_MS / (lna_info->chk_period)) * 5;
-+	else
-+		max_check_time = chk_cnt * 5;
-+
-+	lna_sat_cnt_thd = (max_check_time * lna_info->chk_duty_cycle) / 100;
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+		  "check_time=%d, rssi_min=%d, igi_rssi_min=0x%x\nchk_cnt=%d, chk_period=%d, max_check_time=%d, lna_sat_cnt_thd=%d\n",
-+		  lna_info->check_time,
-+		  rssi_min,
-+		  igi_rssi_min,
-+		  chk_cnt,
-+		  lna_info->chk_period,
-+		  max_check_time,
-+		  lna_sat_cnt_thd);
-+
-+	odm_write_dig(dm, igi_rssi_min);
-+
-+	/*@adapt agc table 0 check saturation status*/
-+	#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
-+		phydm_set_ofdm_agc_tab_path(dm, OFDM_AGC_TAB_0, RF_PATH_A);
-+	else
-+	#endif
-+		phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);
-+	/*@open rf power detection ckt & set detection range */
-+#if (RTL8198F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8198F) {
-+		/*@set rf detection range (threshold)*/
-+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_A, 0x85,
-+						0x3f, 0x3f);
-+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_B, 0x85,
-+						0x3f, 0x3f);
-+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_C, 0x85,
-+						0x3f, 0x3f);
-+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_D, 0x85,
-+						0x3f, 0x3f);
-+		/*@open rf power detection ckt*/
-+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_A, 0x86, 0x10, 1);
-+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_B, 0x86, 0x10, 1);
-+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_C, 0x86, 0x10, 1);
-+		config_phydm_write_rf_reg_8198f(dm, RF_PATH_D, 0x86, 0x10, 1);
-+	}
-+#elif (RTL8814B_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8814B) {
-+		/*@set rf detection range (threshold)*/
-+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x8B, 0x3, 0x3);
-+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x8B, 0x3, 0x3);
-+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x8B, 0x3, 0x3);
-+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x8B, 0x3, 0x3);
-+		/*@open rf power detection ckt*/
-+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x8B, 0x4, 1);
-+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x8B, 0x4, 1);
-+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x8B, 0x4, 1);
-+		config_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x8B, 0x4, 1);
-+	}
-+#else
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x86, 0x1f, 0x10);
-+	odm_set_rf_reg(dm, RF_PATH_B, RF_0x86, 0x1f, 0x10);
-+	#ifdef PHYDM_IC_ABOVE_3SS
-+	odm_set_rf_reg(dm, RF_PATH_C, RF_0x86, 0x1f, 0x10);
-+	#endif
-+	#ifdef PHYDM_IC_ABOVE_4SS
-+	odm_set_rf_reg(dm, RF_PATH_D, RF_0x86, 0x1f, 0x10);
-+	#endif
-+#endif
-+
-+	/*@check saturation status*/
-+	for (i = 0; i < chk_cnt; i++) {
-+#if (RTL8198F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8198F) {
-+		sat_status_a = config_phydm_read_rf_reg_8198f(dm, RF_PATH_A,
-+							      RF_0xae,
-+							      0xe0000);
-+		sat_status_b = config_phydm_read_rf_reg_8198f(dm, RF_PATH_B,
-+							      RF_0xae,
-+							      0xe0000);
-+		sat_status_c = config_phydm_read_rf_reg_8198f(dm, RF_PATH_C,
-+							      RF_0xae,
-+							      0xe0000);
-+		sat_status_d = config_phydm_read_rf_reg_8198f(dm, RF_PATH_D,
-+							      RF_0xae,
-+							      0xe0000);
-+	}
-+#elif (RTL8814B_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8814B) {
-+	/*@read peak detector info from 8814B rf reg*/
-+		sat_status_a = config_phydm_read_rf_reg_8814b(dm, RF_PATH_A,
-+							      RF_0xae,
-+							      0xc0000);
-+		sat_status_b = config_phydm_read_rf_reg_8814b(dm, RF_PATH_B,
-+							      RF_0xae,
-+							      0xc0000);
-+		sat_status_c = config_phydm_read_rf_reg_8814b(dm, RF_PATH_C,
-+							      RF_0xae,
-+							      0xc0000);
-+		sat_status_d = config_phydm_read_rf_reg_8814b(dm, RF_PATH_D,
-+							      RF_0xae,
-+							      0xc0000);
-+	}
-+#else
-+		sat_status_a = odm_get_rf_reg(dm, RF_PATH_A, RF_0xae, 0xc0000);
-+		sat_status_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0xae, 0xc0000);
-+		#ifdef PHYDM_IC_ABOVE_3SS
-+		sat_status_c = odm_get_rf_reg(dm, RF_PATH_C, RF_0xae, 0xc0000);
-+		#endif
-+		#ifdef PHYDM_IC_ABOVE_4SS
-+		sat_status_d = odm_get_rf_reg(dm, RF_PATH_D, RF_0xae, 0xc0000);
-+		#endif
-+#endif
-+
-+		if (sat_status_a != 0)
-+			lna_info->sat_cnt_acc_patha++;
-+		if (sat_status_b != 0)
-+			lna_info->sat_cnt_acc_pathb++;
-+		#ifdef PHYDM_IC_ABOVE_3SS
-+		if (sat_status_c != 0)
-+			lna_info->sat_cnt_acc_pathc++;
-+		#endif
-+		#ifdef PHYDM_IC_ABOVE_4SS
-+		if (sat_status_d != 0)
-+			lna_info->sat_cnt_acc_pathd++;
-+		#endif
-+
-+		if (lna_info->sat_cnt_acc_patha >= lna_sat_cnt_thd ||
-+		    lna_info->sat_cnt_acc_pathb >= lna_sat_cnt_thd ||
-+		    #ifdef PHYDM_IC_ABOVE_3SS
-+		    lna_info->sat_cnt_acc_pathc >= lna_sat_cnt_thd ||
-+		    #endif
-+		    #ifdef PHYDM_IC_ABOVE_4SS
-+		    lna_info->sat_cnt_acc_pathd >= lna_sat_cnt_thd ||
-+		    #endif
-+		    0) {
-+			lna_info->cur_sat_status = 1;
-+			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+				  "cur_sat_status=%d, check_time=%d\n",
-+				  lna_info->cur_sat_status,
-+				  lna_info->check_time);
-+			break;
-+		}
-+		lna_info->cur_sat_status = 0;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+		  "cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_patha=%d, sat_cnt_acc_pathb=%d\n",
-+		  lna_info->cur_sat_status,
-+		  lna_info->pre_sat_status,
-+		  lna_info->sat_cnt_acc_patha,
-+		  lna_info->sat_cnt_acc_pathb);
-+
-+	#ifdef PHYDM_IC_ABOVE_4SS
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+		  "cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_pathc=%d, sat_cnt_acc_pathd=%d\n",
-+		  lna_info->cur_sat_status,
-+		  lna_info->pre_sat_status,
-+		  lna_info->sat_cnt_acc_pathc,
-+		  lna_info->sat_cnt_acc_pathd);
-+	#endif
-+	/*@agc table decision*/
-+	if (lna_info->cur_sat_status) {
-+		if (!lna_info->dis_agc_table_swh)
-+			#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
-+			if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
-+				phydm_set_ofdm_agc_tab_path(dm,
-+							    OFDM_AGC_TAB_2,
-+							    RF_PATH_A);
-+			else
-+			#endif
-+				phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_2);
-+		else
-+			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+				  "disable set to AGC Tab%d\n", OFDM_AGC_TAB_2);
-+		lna_info->check_time = 0;
-+		lna_info->sat_cnt_acc_patha = 0;
-+		lna_info->sat_cnt_acc_pathb = 0;
-+		#ifdef PHYDM_IC_ABOVE_3SS
-+		lna_info->sat_cnt_acc_pathc = 0;
-+		#endif
-+		#ifdef PHYDM_IC_ABOVE_4SS
-+		lna_info->sat_cnt_acc_pathd = 0;
-+		#endif
-+		lna_info->pre_sat_status = lna_info->cur_sat_status;
-+
-+	} else if (lna_info->check_time <= (max_check_time - 1)) {
-+		if (lna_info->pre_sat_status && !lna_info->dis_agc_table_swh)
-+			#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
-+			if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
-+				phydm_set_ofdm_agc_tab_path(dm,
-+							    OFDM_AGC_TAB_2,
-+							    RF_PATH_A);
-+			else
-+			#endif
-+				phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_2);
-+
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ckeck time not reached\n");
-+		if (lna_info->dis_agc_table_swh)
-+			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+				  "disable set to AGC Tab%d\n", OFDM_AGC_TAB_2);
-+		lna_info->check_time++;
-+
-+	} else if (lna_info->check_time >= max_check_time) {
-+		if (!lna_info->dis_agc_table_swh)
-+			#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
-+			if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
-+				phydm_set_ofdm_agc_tab_path(dm,
-+							    OFDM_AGC_TAB_0,
-+							    RF_PATH_A);
-+			else
-+			#endif
-+				phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);
-+
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ckeck time reached\n");
-+		if (lna_info->dis_agc_table_swh)
-+			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+				  "disable set to AGC Tab%d\n", OFDM_AGC_TAB_0);
-+		lna_info->check_time = 0;
-+		lna_info->sat_cnt_acc_patha = 0;
-+		lna_info->sat_cnt_acc_pathb = 0;
-+		#ifdef PHYDM_IC_ABOVE_3SS
-+		lna_info->sat_cnt_acc_pathc = 0;
-+		#endif
-+		#ifdef PHYDM_IC_ABOVE_4SS
-+		lna_info->sat_cnt_acc_pathd = 0;
-+		#endif
-+		lna_info->pre_sat_status = lna_info->cur_sat_status;
-+	}
-+
-+	#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
-+		agc_tab = phydm_get_ofdm_agc_tab_path(dm, RF_PATH_A);
-+	else
-+	#endif
-+		agc_tab = phydm_get_ofdm_agc_tab(dm);
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "use AGC tab %d\n", agc_tab);
-+
-+	/*@restore previous igi*/
-+	odm_write_dig(dm, igi_restore);
-+	lna_info->cur_timer_check_cnt++;
-+	odm_set_timer(dm, &lna_info->phydm_lna_sat_chk_timer,
-+		      lna_info->chk_period);
-+}
-+
-+void phydm_lna_sat_chk_callback(
-+	void *dm_void
-+
-+	)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __func__);
-+	phydm_lna_sat_chk(dm);
-+}
-+
-+void phydm_lna_sat_chk_timers(
-+	void *dm_void,
-+	u8 state)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
-+
-+	if (state == INIT_LNA_SAT_CHK_TIMMER) {
-+		odm_initialize_timer(dm,
-+				     &lna_info->phydm_lna_sat_chk_timer,
-+				     (void *)phydm_lna_sat_chk_callback, NULL,
-+				     "phydm_lna_sat_chk_timer");
-+	} else if (state == CANCEL_LNA_SAT_CHK_TIMMER) {
-+		odm_cancel_timer(dm, &lna_info->phydm_lna_sat_chk_timer);
-+	} else if (state == RELEASE_LNA_SAT_CHK_TIMMER) {
-+		odm_release_timer(dm, &lna_info->phydm_lna_sat_chk_timer);
-+	}
-+}
-+
-+void phydm_lna_sat_chk_watchdog_type1(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info;
-+
-+	u8 rssi_min = dm->rssi_min;
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
-+
-+	if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) {
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+			  "func disable\n");
-+		return;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+		  "pre_timer_check_cnt=%d, cur_timer_check_cnt=%d\n",
-+		  lna_info->pre_timer_check_cnt,
-+		  lna_info->cur_timer_check_cnt);
-+
-+	if (lna_info->is_disable_lna_sat_chk) {
-+		phydm_lna_sat_chk_init(dm);
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+			  "is_disable_lna_sat_chk=%d, return\n",
-+			  lna_info->is_disable_lna_sat_chk);
-+		return;
-+	}
-+
-+	if (rssi_min == 0 || rssi_min == 0xff) {
-+		/*@adapt agc table 0 */
-+		phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0);
-+		phydm_lna_sat_chk_init(dm);
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+			  "rssi_min=%d, return\n", rssi_min);
-+		return;
-+	}
-+
-+	if (lna_info->cur_timer_check_cnt == lna_info->pre_timer_check_cnt) {
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "fail, restart timer\n");
-+		odm_set_timer(dm, &lna_info->phydm_lna_sat_chk_timer,
-+			      lna_info->chk_period);
-+	} else {
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Timer check pass\n");
-+	}
-+	lna_info->pre_timer_check_cnt = lna_info->cur_timer_check_cnt;
-+}
-+
-+#endif /*@#ifdef PHYDM_LNA_SAT_CHK_TYPE1*/
-+
-+#ifdef PHYDM_LNA_SAT_CHK_TYPE2
-+
-+void phydm_bubble_sort(
-+	void *dm_void,
-+	u8 *array,
-+	u16 array_length)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u16 i, j;
-+	u8 temp;
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
-+	for (i = 0; i < (array_length - 1); i++) {
-+		for (j = (i + 1); j < (array_length); j++) {
-+			if (array[i] > array[j]) {
-+				temp = array[i];
-+				array[i] = array[j];
-+				array[j] = temp;
-+			}
-+		}
-+	}
-+}
-+
-+void phydm_lna_sat_chk_type2_init(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
-+	u8 real_shift = pinfo->total_bit_shift;
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
-+
-+	pinfo->total_cnt_snr = 1 << real_shift;
-+	pinfo->is_sm_done = TRUE;
-+	pinfo->is_snr_done = FALSE;
-+	pinfo->cur_snr_mean = 0;
-+	pinfo->cur_snr_var = 0;
-+	pinfo->cur_lower_snr_mean = 0;
-+	pinfo->pre_snr_mean = 0;
-+	pinfo->pre_snr_var = 0;
-+	pinfo->pre_lower_snr_mean = 0;
-+	pinfo->nxt_state = ORI_TABLE_MONITOR;
-+	pinfo->pre_state = ORI_TABLE_MONITOR;
-+}
-+
-+void phydm_snr_collect(
-+	void *dm_void,
-+	u8 rx_snr)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
-+
-+	if (pinfo->is_sm_done) {
-+		/* @adapt only path-A for calculation */
-+		pinfo->snr_statistic[pinfo->cnt_snr_statistic] = rx_snr;
-+
-+		if (pinfo->cnt_snr_statistic == (pinfo->total_cnt_snr - 1)) {
-+			pinfo->is_snr_done = TRUE;
-+			pinfo->cnt_snr_statistic = 0;
-+		} else {
-+			pinfo->cnt_snr_statistic++;
-+		}
-+	} else {
-+		return;
-+	}
-+}
-+
-+void phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*lna_t = &dm->dm_lna_sat_info;
-+	struct phydm_perpkt_info_struct *pktinfo = NULL;
-+	u8 target_macid = dm->rssi_min_macid;
-+
-+	if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK))
-+		return;
-+
-+	pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void;
-+
-+	if (!pktinfo->is_packet_match_bssid)
-+		return;
-+
-+	if (lna_t->force_traget_macid != 0)
-+		target_macid = lna_t->force_traget_macid;
-+
-+	if (target_macid != pktinfo->station_id)
-+		return;
-+
-+	phydm_snr_collect(dm, rx_snr[0]); /*path-A B C D???*/
-+}
-+
-+void phydm_snr_data_processing(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
-+	u8 real_shift = pinfo->total_bit_shift;
-+	u16 total_snr_cnt = pinfo->total_cnt_snr;
-+	u16 total_loop_cnt = (total_snr_cnt - 1), i;
-+	u32 temp;
-+	u32 sum_snr_statistic = 0;
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+		  "total_loop_cnt=%d\n", total_loop_cnt);
-+
-+	for (i = 0; (i <= total_loop_cnt); i++) {
-+		if (pinfo->is_snr_detail_en) {
-+			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+				  "snr[%d]=%d\n", i, pinfo->snr_statistic[i]);
-+		}
-+
-+		sum_snr_statistic += (u32)(pinfo->snr_statistic[i]);
-+
-+		pinfo->snr_statistic_sqr[i] = (u16)(pinfo->snr_statistic[i] * pinfo->snr_statistic[i]);
-+	}
-+
-+	phydm_bubble_sort(dm, pinfo->snr_statistic, pinfo->total_cnt_snr);
-+
-+	/*update SNR's cur mean*/
-+	pinfo->cur_snr_mean = (sum_snr_statistic >> real_shift);
-+
-+	for (i = 0; (i <= total_loop_cnt); i++) {
-+		if (pinfo->snr_statistic[i] >= pinfo->cur_snr_mean)
-+			temp = pinfo->snr_statistic[i] - pinfo->cur_snr_mean;
-+		else
-+			temp = pinfo->cur_snr_mean - pinfo->snr_statistic[i];
-+
-+		pinfo->cur_snr_var += (temp * temp);
-+	}
-+
-+	/*update SNR's VAR*/
-+	pinfo->cur_snr_var = (pinfo->cur_snr_var >> real_shift);
-+
-+	/*@acquire lower SNR's statistics*/
-+	temp = 0;
-+	pinfo->cnt_lower_snr_statistic = (total_snr_cnt >> pinfo->lwr_snr_ratio_bit_shift);
-+	pinfo->cnt_lower_snr_statistic = MAX_2(pinfo->cnt_lower_snr_statistic, SNR_RPT_MAX);
-+
-+	for (i = 0; i < pinfo->cnt_lower_snr_statistic; i++)
-+		temp += pinfo->snr_statistic[i];
-+
-+	pinfo->cur_lower_snr_mean = temp >> (real_shift - pinfo->lwr_snr_ratio_bit_shift);
-+}
-+
-+boolean phydm_is_snr_improve(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
-+	boolean is_snr_improve;
-+	u8 cur_state = pinfo->nxt_state;
-+	u32 cur_mean = pinfo->cur_snr_mean;
-+	u32 pre_mean = pinfo->pre_snr_mean;
-+	u32 cur_lower_mean = pinfo->cur_lower_snr_mean;
-+	u32 pre_lower_mean = pinfo->pre_lower_snr_mean;
-+	u32 cur_var = pinfo->cur_snr_var;
-+
-+	/*special case, zero VAR, interference is gone*/
-+	 /*@make sure pre_var is larger enough*/
-+	if (cur_state == SAT_TABLE_MONITOR ||
-+	    cur_state == ORI_TABLE_TRAINING) {
-+		if (cur_mean >= pre_mean) {
-+			if (cur_var == 0)
-+				return true;
-+		}
-+	}
-+#if 0
-+	/*special case, mean degrade less than VAR improvement*/
-+	/*@make sure pre_var is larger enough*/
-+	if (cur_state == ORI_TABLE_MONITOR &&
-+	    cur_mean < pre_mean &&
-+	    cur_var < pre_var) {
-+		diff_mean = pre_mean - cur_mean;
-+		diff_var = pre_var - cur_var;
-+		return (diff_var > (2 * diff_mean * diff_mean)) ? true : false;
-+	}
-+
-+#endif
-+	if (cur_lower_mean >= (pre_lower_mean + pinfo->delta_snr_mean))
-+		is_snr_improve = true;
-+	else
-+		is_snr_improve = false;
-+#if 0
-+/* @condition refine, mean is bigger enough or VAR is smaller enough*/
-+/* @1. from mean's view, mean improve delta_snr_mean(2), VAR not degrade lot*/
-+	if (cur_mean > (pre_mean + pinfo->delta_snr_mean)) {
-+		is_mean_improve = TRUE;
-+		is_var_improve = (cur_var <= pre_var + dm->delta_snr_var)
-+				 ? TRUE : FALSE;
-+
-+	} else if (cur_var + dm->delta_snr_var <= pre_var) {
-+		is_var_improve = TRUE;
-+		is_mean_improve = ((cur_mean + 1) >= pre_mean) ? TRUE : FALSE;
-+	} else {
-+		return false;
-+	}
-+#endif
-+	return is_snr_improve;
-+}
-+
-+boolean phydm_is_snr_degrade(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
-+	u32 cur_lower_mean = pinfo->cur_lower_snr_mean;
-+	u32 pre_lower_mean = pinfo->pre_lower_snr_mean;
-+	boolean is_degrade;
-+
-+	if (cur_lower_mean <= (pre_lower_mean - pinfo->delta_snr_mean))
-+		is_degrade = TRUE;
-+	else
-+		is_degrade = FALSE;
-+#if 0
-+	is_mean_dgrade = (pinfo->cur_snr_mean + pinfo->delta_snr_mean <= pinfo->pre_snr_mean) ? TRUE : FALSE;
-+	is_var_degrade = (pinfo->cur_snr_var > (pinfo->pre_snr_var + pinfo->delta_snr_mean)) ? TRUE : FALSE;
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d\n",
-+		  __func__,
-+		  pinfo->cur_snr_mean,
-+		  pinfo->pre_snr_mean,
-+		  pinfo->cur_snr_var,
-+		  pinfo->pre_snr_var);
-+
-+	return (is_mean_dgrade & is_var_degrade);
-+#endif
-+	return is_degrade;
-+}
-+
-+boolean phydm_is_large_var(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
-+	boolean is_large_var = (pinfo->cur_snr_var >= pinfo->snr_var_thd) ? TRUE : FALSE;
-+
-+	return is_large_var;
-+}
-+
-+void phydm_update_pre_status(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
-+
-+	pinfo->pre_lower_snr_mean = pinfo->cur_lower_snr_mean;
-+	pinfo->pre_snr_mean = pinfo->cur_snr_mean;
-+	pinfo->pre_snr_var = pinfo->cur_snr_var;
-+}
-+
-+void phydm_ori_table_monitor(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
-+
-+	if (phydm_is_large_var(dm)) {
-+		pinfo->nxt_state = SAT_TABLE_TRAINING;
-+		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
-+	} else {
-+		pinfo->nxt_state = ORI_TABLE_MONITOR;
-+		/*switch to anti-sat table*/
-+		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
-+	}
-+	phydm_update_pre_status(dm);
-+	pinfo->pre_state = ORI_TABLE_MONITOR;
-+}
-+
-+void phydm_sat_table_training(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
-+
-+	#if 0
-+	if pre_state = ORI_TABLE_MONITOR || SAT_TABLE_TRY_FAIL,
-+	/*@"pre" adapt ori-table, "cur" adapt sat-table*/
-+	/*@adapt ori table*/
-+	if (pinfo->pre_state == ORI_TABLE_MONITOR) {
-+		pinfo->nxt_state = SAT_TABLE_TRAINING;
-+		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
-+	} else {
-+	#endif
-+	if (phydm_is_snr_improve(dm)) {
-+		pinfo->nxt_state = SAT_TABLE_MONITOR;
-+	} else {
-+		pinfo->nxt_state = SAT_TABLE_TRY_FAIL;
-+		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
-+	}
-+	/*@}*/
-+
-+	phydm_update_pre_status(dm);
-+	pinfo->pre_state = SAT_TABLE_TRAINING;
-+}
-+
-+void phydm_sat_table_try_fail(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
-+
-+	/* @if pre_state = SAT_TABLE_TRAINING, "pre" adapt sat-table, "cur" adapt ori-table */
-+	/* @if pre_state = SAT_TABLE_TRY_FAIL, "pre" adapt ori-table, "cur" adapt ori-table */
-+
-+	if (phydm_is_large_var(dm)) {
-+		if (phydm_is_snr_degrade(dm)) {
-+			pinfo->nxt_state = SAT_TABLE_TRAINING;
-+			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
-+		} else {
-+			pinfo->nxt_state = SAT_TABLE_TRY_FAIL;
-+		}
-+	} else {
-+		pinfo->nxt_state = ORI_TABLE_MONITOR;
-+	}
-+	phydm_update_pre_status(dm);
-+	pinfo->pre_state = SAT_TABLE_TRY_FAIL;
-+}
-+
-+void phydm_sat_table_monitor(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
-+
-+	if (phydm_is_snr_improve(dm)) {
-+		pinfo->sat_table_monitor_times = 0;
-+
-+		/* @if pre_state = SAT_TABLE_MONITOR, "pre" adapt sat-table, "cur" adapt sat-table */
-+		if (pinfo->pre_state == SAT_TABLE_MONITOR) {
-+			pinfo->nxt_state = ORI_TABLE_TRAINING;
-+			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
-+			//phydm_update_pre_status(dm);
-+		} else {
-+			pinfo->nxt_state = SAT_TABLE_MONITOR;
-+		}
-+
-+		/* @if pre_state = SAT_TABLE_TRAINING, "pre" adapt sat-table, "cur" adapt sat-table */
-+		/* @if pre_state = ORI_TABLE_TRAINING, "pre" adapt ori-table, "cur" adapt sat-table */
-+		/*pre_state above is no need to update*/
-+	} else {
-+		if (pinfo->sat_table_monitor_times == pinfo->force_change_period) {
-+			PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s: sat_table_monitor_times=%d\n",
-+				  __func__, pinfo->sat_table_monitor_times);
-+
-+			pinfo->nxt_state = ORI_TABLE_TRAINING;
-+			pinfo->sat_table_monitor_times = 0;
-+			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
-+		} else {
-+			pinfo->nxt_state = SAT_TABLE_MONITOR;
-+			pinfo->sat_table_monitor_times++;
-+		}
-+	}
-+	phydm_update_pre_status(dm);
-+	pinfo->pre_state = SAT_TABLE_MONITOR;
-+}
-+
-+void phydm_ori_table_training(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
-+
-+	/* pre_state = SAT_TABLE_MONITOR, "pre" adapt sat-table, "cur" adapt ori-table */
-+
-+	if (phydm_is_snr_degrade(dm) == FALSE) {
-+		pinfo->nxt_state = ORI_TABLE_MONITOR;
-+	} else {
-+		if (pinfo->pre_snr_var == 0)
-+			pinfo->nxt_state = ORI_TABLE_TRY_FAIL;
-+		else
-+			pinfo->nxt_state = SAT_TABLE_MONITOR;
-+
-+		config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
-+	}
-+	phydm_update_pre_status(dm);
-+	pinfo->pre_state = ORI_TABLE_TRAINING;
-+}
-+
-+void phydm_ori_table_try_fail(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
-+
-+	if (pinfo->pre_state == ORI_TABLE_TRY_FAIL) {
-+		if (phydm_is_snr_improve(dm)) {
-+			pinfo->nxt_state = ORI_TABLE_TRAINING;
-+			pinfo->ori_table_try_fail_times = 0;
-+			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
-+		} else {
-+			if (pinfo->ori_table_try_fail_times == pinfo->force_change_period) {
-+				PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+					  "%s: ori_table_try_fail_times=%d\n", __func__, pinfo->ori_table_try_fail_times);
-+
-+				pinfo->nxt_state = ORI_TABLE_TRY_FAIL;
-+				pinfo->ori_table_try_fail_times = 0;
-+				phydm_update_pre_status(dm);
-+			} else {
-+				pinfo->nxt_state = ORI_TABLE_TRY_FAIL;
-+				pinfo->ori_table_try_fail_times++;
-+				phydm_update_pre_status(dm);
-+				//config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
-+			}
-+		}
-+	} else {
-+		pinfo->nxt_state = ORI_TABLE_TRY_FAIL;
-+		pinfo->ori_table_try_fail_times = 0;
-+		phydm_update_pre_status(dm);
-+		//config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
-+	}
-+
-+#if 0
-+	if (phydm_is_large_var(dm)) {
-+		if (phydm_is_snr_degrade(dm)) {
-+			pinfo->nxt_state = SAT_TABLE_TRAINING;
-+			config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
-+		} else {
-+			pinfo->nxt_state = SAT_TABLE_TRY_FAIL;
-+		}
-+	} else {
-+		pinfo->nxt_state = ORI_TABLE_MONITOR;
-+	}
-+
-+	phydm_update_pre_status(dm);
-+#endif
-+	pinfo->pre_state = ORI_TABLE_TRY_FAIL;
-+}
-+
-+char *phydm_lna_sat_state_msg(
-+	void *dm_void,
-+	IN u8 state)
-+{
-+	char *dbg_message;
-+
-+	switch (state) {
-+	case ORI_TABLE_MONITOR:
-+		dbg_message = "ORI_TABLE_MONITOR";
-+		break;
-+
-+	case SAT_TABLE_TRAINING:
-+		dbg_message = "SAT_TABLE_TRAINING";
-+		break;
-+
-+	case SAT_TABLE_TRY_FAIL:
-+		dbg_message = "SAT_TABLE_TRY_FAIL";
-+		break;
-+
-+	case SAT_TABLE_MONITOR:
-+		dbg_message = "SAT_TABLE_MONITOR";
-+		break;
-+
-+	case ORI_TABLE_TRAINING:
-+		dbg_message = "ORI_TABLE_TRAINING";
-+		break;
-+
-+	case ORI_TABLE_TRY_FAIL:
-+		dbg_message = "ORI_TABLE_TRY_FAIL";
-+		break;
-+
-+	default:
-+		dbg_message = "ORI_TABLE_MONITOR";
-+		break;
-+	}
-+
-+	return dbg_message;
-+}
-+
-+void phydm_lna_sat_type2_sm(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*pinfo = &dm->dm_lna_sat_info;
-+	u8 state = pinfo->nxt_state;
-+	u8 agc_tab = (u8)odm_get_bb_reg(dm, 0x958, 0x1f);
-+	char *dbg_message, *nxt_dbg_message;
-+	u8 real_shift = pinfo->total_bit_shift;
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n\n%s ==>\n", __func__);
-+
-+	if ((dm->support_ic_type & ODM_RTL8822B) == FALSE) {
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ODM_BB_LNA_SAT_CHK_TYPE2 only support 22B.\n");
-+		return;
-+	}
-+
-+	if ((dm->support_ability & ODM_BB_LNA_SAT_CHK) == FALSE) {
-+		phydm_lna_sat_chk_type2_init(dm);
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ODM_BB_LNA_SAT_CHK_TYPE2 is NOT supported, cur table=%d\n", agc_tab);
-+		return;
-+	}
-+
-+	if (pinfo->is_snr_done)
-+		phydm_snr_data_processing(dm);
-+	else
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "cur agc table %d\n", agc_tab);
-+
-+	if (pinfo->is_force_lna_sat_table != AUTO_AGC_TABLE) {
-+		/*reset state machine*/
-+		pinfo->nxt_state = ORI_TABLE_MONITOR;
-+		if (pinfo->is_snr_done) {
-+			if (pinfo->is_force_lna_sat_table == DEFAULT_AGC_TABLE)
-+				config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
-+			else if (pinfo->is_force_lna_sat_table == LNA_SAT_AGC_TABLE)
-+				config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE);
-+			else
-+				config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE);
-+
-+			PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+				  "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\n",
-+				  __func__,
-+				  pinfo->cur_snr_mean,
-+				  pinfo->pre_snr_mean,
-+				  pinfo->cur_snr_var,
-+				  pinfo->pre_snr_var,
-+				  pinfo->cur_lower_snr_mean,
-+				  pinfo->pre_lower_snr_mean,
-+				  pinfo->cnt_lower_snr_statistic);
-+
-+			pinfo->is_snr_done = FALSE;
-+			pinfo->is_sm_done = TRUE;
-+			phydm_update_pre_status(dm);
-+		} else {
-+			return;
-+		}
-+	} else if (pinfo->is_snr_done) {
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+			  "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\n",
-+			  __func__,
-+			  pinfo->cur_snr_mean,
-+			  pinfo->pre_snr_mean,
-+			  pinfo->cur_snr_var,
-+			  pinfo->pre_snr_var,
-+			  pinfo->cur_lower_snr_mean,
-+			  pinfo->pre_lower_snr_mean,
-+			  pinfo->cnt_lower_snr_statistic);
-+
-+		switch (state) {
-+		case ORI_TABLE_MONITOR:
-+			dbg_message = "ORI_TABLE_MONITOR";
-+			phydm_ori_table_monitor(dm);
-+			break;
-+
-+		case SAT_TABLE_TRAINING:
-+			dbg_message = "SAT_TABLE_TRAINING";
-+			phydm_sat_table_training(dm);
-+			break;
-+
-+		case SAT_TABLE_TRY_FAIL:
-+			dbg_message = "SAT_TABLE_TRY_FAIL";
-+			phydm_sat_table_try_fail(dm);
-+			break;
-+
-+		case SAT_TABLE_MONITOR:
-+			dbg_message = "SAT_TABLE_MONITOR";
-+			phydm_sat_table_monitor(dm);
-+			break;
-+
-+		case ORI_TABLE_TRAINING:
-+			dbg_message = "ORI_TABLE_TRAINING";
-+			phydm_ori_table_training(dm);
-+			break;
-+
-+		case ORI_TABLE_TRY_FAIL:
-+			dbg_message = "ORI_TABLE_TRAINING";
-+			phydm_ori_table_try_fail(dm);
-+			break;
-+
-+		default:
-+			dbg_message = "ORI_TABLE_MONITOR";
-+			phydm_ori_table_monitor(dm);
-+			break;
-+		}
-+
-+		dbg_message = phydm_lna_sat_state_msg(dm, state);
-+		nxt_dbg_message = phydm_lna_sat_state_msg(dm, pinfo->nxt_state);
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "state: [%s]->[%s]\n",
-+			  dbg_message, nxt_dbg_message);
-+
-+		pinfo->is_snr_done = FALSE;
-+		pinfo->is_sm_done = TRUE;
-+		pinfo->total_cnt_snr = 1 << real_shift;
-+
-+	} else {
-+		return;
-+	}
-+}
-+#endif /*@#ifdef PHYDM_LNA_SAT_CHK_TYPE2*/
-+
-+#ifdef PHYDM_HW_SWITCH_AGC_TAB
-+u32 phydm_get_lna_pd_reg(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 rf_pd_reg = RF_0x8b;
-+
-+#if (RTL8814B_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8814B) {
-+			if (*dm->channel <= 14)
-+				rf_pd_reg = RF_0x87;
-+			else
-+				rf_pd_reg = RF_0x8b;
-+		}
-+#endif
-+	return rf_pd_reg;
-+}
-+
-+u32 phydm_get_lna_pd_en_mask(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 rf_pd_en_msk = BIT(2);
-+
-+#if (RTL8814B_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8814B) {
-+			if (*dm->channel <= 14)
-+				rf_pd_en_msk = BIT(4);
-+			else
-+				rf_pd_en_msk = BIT(2);
-+		}
-+#endif
-+	return rf_pd_en_msk;
-+}
-+
-+boolean phydm_get_lna_pd_en(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 rf_pd_reg = RF_0x8b;
-+	u32 rf_pd_en_msk = BIT(2);
-+	u32 pd_en = 0;
-+
-+	rf_pd_reg = phydm_get_lna_pd_reg(dm);
-+	rf_pd_en_msk = phydm_get_lna_pd_en_mask(dm);
-+
-+#if (RTL8814B_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8814B)
-+			pd_en = config_phydm_read_rf_reg_8814b(dm, RF_PATH_A,
-+							       rf_pd_reg,
-+							       rf_pd_en_msk);
-+#endif
-+	return (boolean)pd_en;
-+}
-+
-+void phydm_set_lna_pd_en(void *dm_void, boolean lna_pd_en)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	enum rf_path i = RF_PATH_A;
-+	u32 rf_pd_reg = RF_0x8b;
-+	u32 rf_pd_en_msk = BIT(2);
-+
-+	rf_pd_reg = phydm_get_lna_pd_reg(dm);
-+	rf_pd_en_msk = phydm_get_lna_pd_en_mask(dm);
-+
-+#if (RTL8814B_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8814B)
-+			for (i = RF_PATH_A; i < MAX_PATH_NUM_8814B; i++)
-+				config_phydm_write_rf_reg_8814b(dm, i,
-+								rf_pd_reg,
-+								rf_pd_en_msk,
-+								(u8)lna_pd_en);
-+#endif
-+}
-+
-+u32 phydm_get_lna_pd_th_mask(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 rf_pd_th_msk = 0x3;
-+
-+#if (RTL8814B_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8814B)
-+			rf_pd_th_msk = 0x3;
-+#endif
-+	return rf_pd_th_msk;
-+}
-+
-+enum lna_pd_th_level phydm_get_lna_pd_th_lv(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 rf_pd_reg = RF_0x8b;
-+	u32 rf_pd_th_msk = 0x3;
-+	u32 pd_th_lv = 0x0;
-+
-+	rf_pd_reg = phydm_get_lna_pd_reg(dm);
-+	rf_pd_th_msk = phydm_get_lna_pd_th_mask(dm);
-+
-+#if (RTL8814B_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		pd_th_lv = config_phydm_read_rf_reg_8814b(dm, RF_PATH_A,
-+							  rf_pd_reg,
-+							  rf_pd_th_msk);
-+#endif
-+	return (enum lna_pd_th_level)pd_th_lv;
-+}
-+
-+void phydm_set_lna_pd_th_lv(void *dm_void,
-+			    enum lna_pd_th_level lna_pd_th_lv)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	enum rf_path i = RF_PATH_A;
-+	u32 rf_pd_reg = RF_0x8b;
-+	u32 rf_pd_th_msk = 0x3;
-+
-+	rf_pd_reg = phydm_get_lna_pd_reg(dm);
-+	rf_pd_th_msk = phydm_get_lna_pd_th_mask(dm);
-+
-+#if (RTL8814B_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8814B)
-+			for (i = RF_PATH_A; i < MAX_PATH_NUM_8814B; i++)
-+				config_phydm_write_rf_reg_8814b(dm, i,
-+								rf_pd_reg,
-+								rf_pd_th_msk,
-+								lna_pd_th_lv);
-+#endif
-+}
-+
-+u32 phydm_get_sat_agc_tab_version(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+#if (RTL8814B_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		return odm_get_version_mp_8814b_extra_agc_tab();
-+#endif
-+	return 0;
-+}
-+
-+boolean phydm_get_auto_agc_config(void *dm_void,
-+				  enum agc_tab_switch_state state_sel)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 state_en = 0;
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	switch (state_sel) {
-+	case AGC_SWH_IDLE:
-+		state_en = odm_get_bb_reg(dm, R_0x18ac, BIT(16));
-+		break;
-+	case AGC_SWH_OFDM:
-+		state_en = odm_get_bb_reg(dm, R_0x18ac, BIT(17));
-+		break;
-+	case AGC_SWH_CCK:
-+		state_en = odm_get_bb_reg(dm, R_0x18ac, BIT(18));
-+		break;
-+	default:
-+		state_en = 0;
-+		break;
-+	}
-+#endif
-+	return (boolean)state_en;
-+}
-+
-+boolean phydm_is_auto_agc_on(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean state_on = false;
-+
-+	state_on = ((phydm_get_auto_agc_config(dm, AGC_SWH_IDLE) ||
-+		     phydm_get_auto_agc_config(dm, AGC_SWH_CCK) ||
-+		     phydm_get_auto_agc_config(dm, AGC_SWH_OFDM)) &&
-+		     phydm_get_lna_pd_en(dm));
-+
-+	return state_on;
-+}
-+
-+void phydm_config_auto_agc(void *dm_void,
-+			   boolean idle_en,
-+			   boolean cck_cca_en,
-+			   boolean ofdm_cca_en)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 hwagc_opt = 0;
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (dm->support_ic_type & ~ODM_RTL8814B)
-+		return;
-+
-+	if (idle_en)
-+		hwagc_opt |= BIT(0);
-+	else
-+		hwagc_opt &= ~BIT(0);
-+	if (ofdm_cca_en)
-+		hwagc_opt |= BIT(1);
-+	else
-+		hwagc_opt &= ~BIT(1);
-+	if (cck_cca_en)
-+		hwagc_opt |= BIT(2);
-+	else
-+		hwagc_opt &= ~BIT(2);
-+
-+	odm_set_bb_reg(dm, R_0x18ac, BIT(18) | BIT(17) | BIT(16), hwagc_opt);
-+#ifdef PHYDM_COMPILE_ABOVE_2SS
-+	odm_set_bb_reg(dm, R_0x41ac, BIT(18) | BIT(17) | BIT(16), hwagc_opt);
-+#endif
-+#ifdef PHYDM_COMPILE_ABOVE_3SS
-+	odm_set_bb_reg(dm, R_0x52ac, BIT(18) | BIT(17) | BIT(16), hwagc_opt);
-+#endif
-+#ifdef PHYDM_COMPILE_ABOVE_4SS
-+	odm_set_bb_reg(dm, R_0x53ac, BIT(18) | BIT(17) | BIT(16), hwagc_opt);
-+#endif
-+#endif
-+}
-+
-+void phydm_auto_agc_tab_reset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	phydm_set_lna_pd_th_lv(dm, 0x0);
-+	phydm_config_auto_agc(dm, true, false, true);
-+	phydm_set_lna_pd_en(dm, true);
-+}
-+
-+void phydm_auto_agc_tab_off(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	phydm_config_auto_agc(dm, false, false, false);
-+	phydm_set_lna_pd_en(dm, false);
-+}
-+
-+void phydm_switch_sat_agc_by_band(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;
-+
-+#if (RTL8814B_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8814B)
-+		odm_config_mp_8814b_extra_agc_tab(dm, lna_sat->cur_rf_band);
-+#endif
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	pr_debug("%s ==> switch to band%d\n", __func__, lna_sat->cur_rf_band);
-+#else
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==> switch to band%d\n",
-+		  __func__, lna_sat->cur_rf_band);
-+#endif
-+}
-+
-+void phydm_auto_agc_tab_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;
-+	u8 channel = *dm->channel;
-+
-+	lna_sat->cur_rf_band = phydm_ch_to_rf_band(dm, channel);
-+	phydm_switch_sat_agc_by_band(dm);
-+
-+	if ((dm->support_ability & ODM_BB_LNA_SAT_CHK)) {
-+		phydm_auto_agc_tab_reset(dm);
-+		lna_sat->hw_swh_tab_on = true;
-+	} else {
-+		phydm_auto_agc_tab_off(dm);
-+		lna_sat->hw_swh_tab_on = false;
-+	}
-+}
-+
-+void phydm_auto_agc_tab_watchdog(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;
-+	boolean hw_swh_on = false;
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
-+
-+	if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) {
-+		if (lna_sat->hw_swh_tab_on) {
-+			phydm_auto_agc_tab_off(dm);
-+			lna_sat->hw_swh_tab_on = false;
-+		}
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Disabled LNA sat. check\n");
-+		return;
-+	}
-+
-+	if (!lna_sat->hw_swh_tab_on)
-+		PHYDM_DBG(dm, DBG_LNA_SAT_CHK,
-+			  "[WARNING] HW switch AGC Tab not fully enabled\n");
-+}
-+
-+void phydm_auto_agc_tab_debug(void *dm_void, char input[][16], u32 *_used,
-+			      char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i;
-+	u8 agc_tab = 0;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "LNA sat. AGC Tab version : %d\n",
-+			 phydm_get_sat_agc_tab_version(dm));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Enable LNA peak detector : {0} {lna_pd_en = %d}\n",
-+			 phydm_get_lna_pd_en(dm));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Set LNA peak detector lv : {1} {lna_pd_th_lv = %d}\n",
-+			 phydm_get_lna_pd_th_lv(dm));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Config hw switch AGC tab : {2} {hw_swh_en_rx_idle} {hw_swh_en_cck_cca} {hw_swh_en_ofdm_cca} = (%d, %d, %d)\n",
-+			 phydm_get_auto_agc_config(dm, AGC_SWH_IDLE),
-+			 phydm_get_auto_agc_config(dm, AGC_SWH_CCK),
-+			 phydm_get_auto_agc_config(dm, AGC_SWH_OFDM));
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Reset to default setting : {3}\n",
-+			 phydm_get_auto_agc_config(dm, AGC_SWH_IDLE),
-+			 phydm_get_auto_agc_config(dm, AGC_SWH_CCK),
-+			 phydm_get_auto_agc_config(dm, AGC_SWH_OFDM));
-+
-+	} else {
-+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+		for (i = 1; i < 10; i++) {
-+			if (input[i + 1])
-+				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
-+					     &var1[i]);
-+		}
-+		
-+		if (var1[0] == 0) {
-+			phydm_set_lna_pd_en(dm, (boolean)var1[1]);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "set lna_pd_en = %d\n",
-+				 (u8)phydm_get_lna_pd_en(dm));
-+		} else if (var1[0] == 1) {
-+			phydm_set_lna_pd_th_lv(dm, (u8)var1[1]);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "set lna_pd_th_lv = %d\n",
-+				 phydm_get_lna_pd_th_lv(dm));
-+		}  else if (var1[0] == 2) {
-+			phydm_config_auto_agc(dm, (boolean)var1[1],
-+					      (boolean)var1[2],
-+					      (boolean)var1[3]);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "set hw switch agc tab en: (rx_idle, cck_cca, ofdm_cca) = (%d, %d, %d)\n",
-+				 phydm_get_auto_agc_config(dm, AGC_SWH_IDLE),
-+				 phydm_get_auto_agc_config(dm, AGC_SWH_CCK),
-+				 phydm_get_auto_agc_config(dm, AGC_SWH_OFDM));
-+		}  else if (var1[0] == 3) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "reset to default settings\n");
-+			phydm_auto_agc_tab_reset(dm);
-+		}
-+		lna_sat->hw_swh_tab_on = phydm_is_auto_agc_on(dm);
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+#endif /*@#ifdef PHYDM_HW_SWITCH_AGC_TAB*/
-+
-+void phydm_lna_sat_debug(void *dm_void,	char input[][16], u32 *_used,
-+			 char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*lna_t = &dm->dm_lna_sat_info;
-+	char help[] = "-h";
-+	char monitor[] = "-m";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i;
-+	u8 agc_tab = 0;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "monitor: -m\n");
-+		#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{0} {lna_sat_chk_en}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{1} {agc_table_switch_en}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{2} {chk_cnt per callback}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{3} {chk_period(ms)}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{4} {chk_duty_cycle(%)}\n");
-+		#endif
-+	} else if ((strcmp(input[1], monitor) == 0)) {
-+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+		#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
-+		if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B))
-+			agc_tab = phydm_get_ofdm_agc_tab_path(dm, RF_PATH_A);
-+		else
-+		#endif
-+			agc_tab = phydm_get_ofdm_agc_tab(dm);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "%s%d, %s%d, %s%d, %s%d\n",
-+			 "check_time = ", lna_t->check_time,
-+			 "pre_sat_status = ", lna_t->pre_sat_status,
-+			 "cur_sat_status = ", lna_t->cur_sat_status,
-+			 "current AGC tab = ", agc_tab);
-+#endif
-+	} else {
-+		PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+
-+		for (i = 1; i < 10; i++) {
-+			if (input[i + 1])
-+				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
-+					     &var1[i]);
-+		}
-+		#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+		if (var1[0] == 0) {
-+			if (var1[1] == 1)
-+				lna_t->is_disable_lna_sat_chk = false;
-+			else if (var1[1] == 0)
-+				lna_t->is_disable_lna_sat_chk = true;
-+
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "dis_lna_sat_chk=%d\n",
-+				 lna_t->is_disable_lna_sat_chk);
-+		} else if (var1[0] == 1) {
-+			if (var1[1] == 1)
-+				lna_t->dis_agc_table_swh = false;
-+			else if (var1[1] == 0)
-+				lna_t->dis_agc_table_swh = true;
-+
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "dis_agc_table_swh=%d\n",
-+				 lna_t->dis_agc_table_swh);
-+
-+		} else if (var1[0] == 2) {
-+			lna_t->chk_cnt = (u8)var1[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "chk_cnt=%d\n", lna_t->chk_cnt);
-+		} else if (var1[0] == 3) {
-+			lna_t->chk_period = var1[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "chk_period=%d\n", lna_t->chk_period);
-+		} else if (var1[0] == 4) {
-+			lna_t->chk_duty_cycle = (u8)var1[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "chk_duty_cycle=%d\n",
-+				 lna_t->chk_duty_cycle);
-+		}
-+		#endif
-+		#ifdef PHYDM_LNA_SAT_CHK_TYPE2
-+		if (var1[0] == 1)
-+			lna_t->force_traget_macid = var1[1];
-+		#endif
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_lna_sat_chk_watchdog(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info;
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);
-+
-+	if (lna_sat->lna_sat_type == LNA_SAT_WITH_PEAK_DET) {
-+		#ifdef PHYDM_HW_SWITCH_AGC_TAB
-+		if (dm->support_ic_type & ODM_RTL8814B) {
-+			phydm_auto_agc_tab_watchdog(dm);
-+			return;
-+		}
-+		#endif
-+		#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+		if (dm->support_ic_type &
-+		    (ODM_RTL8197F | ODM_RTL8198F | ODM_RTL8814B)) {
-+			phydm_lna_sat_chk_watchdog_type1(dm);
-+			return;
-+		}
-+		#endif
-+	} else if (lna_sat->lna_sat_type == LNA_SAT_WITH_TRAIN) {
-+		#ifdef PHYDM_LNA_SAT_CHK_TYPE2
-+		return;
-+		#endif
-+	}
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "support_ic_type match fail, return\n");
-+}
-+
-+void phydm_lna_sat_config(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;
-+
-+	lna_sat->lna_sat_type = 0;
-+	#if (RTL8822B_SUPPORT == 1)
-+	if (dm->support_ic_type & (ODM_RTL8822B))
-+		lna_sat->lna_sat_type = LNA_SAT_WITH_TRAIN;
-+	#endif
-+
-+	#if (RTL8197F_SUPPORT || RTL8192F_SUPPORT || \
-+	     RTL8198F_SUPPORT || RTL8814B_SUPPORT)
-+	if (dm->support_ic_type &
-+	    (ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8198F | ODM_RTL8814B))
-+		lna_sat->lna_sat_type = LNA_SAT_WITH_PEAK_DET;
-+	#endif
-+
-+	PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "[%s] lna_sat_type=%d\n",
-+		  __func__, lna_sat->lna_sat_type);
-+}
-+
-+void phydm_lna_sat_check_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_lna_sat_t	*lna_sat = &dm->dm_lna_sat_info;
-+
-+	/*@2018.04.17 Johnson*/
-+	phydm_lna_sat_config(dm);
-+	#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+	lna_sat->chk_period = LNA_CHK_PERIOD;
-+	lna_sat->chk_cnt = LNA_CHK_CNT;
-+	lna_sat->chk_duty_cycle = LNA_CHK_DUTY_CYCLE;
-+	lna_sat->dis_agc_table_swh = false;
-+	#endif
-+	/*@2018.04.17 Johnson end*/
-+
-+	if (lna_sat->lna_sat_type == LNA_SAT_WITH_PEAK_DET) {
-+		#ifdef PHYDM_HW_SWITCH_AGC_TAB
-+		if (dm->support_ic_type & ODM_RTL8814B) {
-+			phydm_auto_agc_tab_init(dm);
-+			return;
-+		}
-+		#endif
-+		#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+		phydm_lna_sat_chk_init(dm);
-+		#endif
-+	} else if (lna_sat->lna_sat_type == LNA_SAT_WITH_TRAIN) {
-+		#ifdef PHYDM_LNA_SAT_CHK_TYPE2
-+		phydm_lna_sat_chk_type2_init(dm);
-+		#endif
-+	}
-+}
-+
-+#endif /*@#ifdef PHYDM_LNA_SAT_CHK_SUPPORT*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_lna_sat.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_lna_sat.h
-new file mode 100644
-index 000000000000..69a9349969c2
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_lna_sat.h
-@@ -0,0 +1,196 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_LNA_SAT_H__
-+#define __PHYDM_LNA_SAT_H__
-+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
-+/* @1 ============================================================
-+ * 1  Definition
-+ * 1 ============================================================
-+ */
-+
-+#define LNA_SAT_VERSION "1.1"
-+
-+/*@LNA saturation check*/
-+#define	OFDM_AGC_TAB_0			0
-+#define	OFDM_AGC_TAB_2			2
-+
-+#define	DIFF_RSSI_TO_IGI		10
-+#define	ONE_SEC_MS			1000
-+
-+#define LNA_CHK_PERIOD			100 /*@ms*/
-+#define LNA_CHK_CNT			10 /*@checks per callback*/
-+#define LNA_CHK_DUTY_CYCLE		5 /*@percentage*/
-+
-+#define	DELTA_STD	2
-+#define	DELTA_MEAN	2
-+#define	SNR_STATISTIC_SHIFT	8
-+#define	SNR_RPT_MAX	256
-+
-+/* @1 ============================================================
-+ * 1 enumrate
-+ * 1 ============================================================
-+ */
-+
-+enum lna_sat_timer_state {
-+	INIT_LNA_SAT_CHK_TIMMER,
-+	CANCEL_LNA_SAT_CHK_TIMMER,
-+	RELEASE_LNA_SAT_CHK_TIMMER
-+};
-+
-+#ifdef PHYDM_LNA_SAT_CHK_TYPE2
-+enum lna_sat_chk_type2_status {
-+	ORI_TABLE_MONITOR,
-+	ORI_TABLE_TRAINING,
-+	SAT_TABLE_MONITOR,
-+	SAT_TABLE_TRAINING,
-+	SAT_TABLE_TRY_FAIL,
-+	ORI_TABLE_TRY_FAIL
-+};
-+
-+#endif
-+
-+enum lna_sat_type {
-+	LNA_SAT_WITH_PEAK_DET	= 1,	/*type1*/
-+	LNA_SAT_WITH_TRAIN	= 2,	/*type2*/
-+};
-+
-+#ifdef PHYDM_HW_SWITCH_AGC_TAB
-+enum lna_pd_th_level {
-+	LNA_PD_TH_LEVEL0	= 0,
-+	LNA_PD_TH_LEVEL1	= 1,
-+	LNA_PD_TH_LEVEL2	= 2,
-+	LNA_PD_TH_LEVEL3	= 3
-+};
-+
-+enum agc_tab_switch_state {
-+	AGC_SWH_IDLE,
-+	AGC_SWH_CCK,
-+	AGC_SWH_OFDM
-+};
-+#endif
-+
-+/* @1 ============================================================
-+ * 1  structure
-+ * 1 ============================================================
-+ */
-+
-+struct phydm_lna_sat_t {
-+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+	u8			chk_cnt;
-+	u8			chk_duty_cycle;
-+	u32			chk_period;/*@ms*/
-+	boolean			is_disable_lna_sat_chk;
-+	boolean			dis_agc_table_swh;
-+#endif
-+#ifdef PHYDM_LNA_SAT_CHK_TYPE2
-+	u8			force_traget_macid;
-+	u32			snr_var_thd;
-+	u32			delta_snr_mean;
-+	u16			ori_table_try_fail_times;
-+	u16			cnt_lower_snr_statistic;
-+	u16			sat_table_monitor_times;
-+	u16			force_change_period;
-+	u8			is_snr_detail_en;
-+	u8			is_force_lna_sat_table;
-+	u8			lwr_snr_ratio_bit_shift;
-+	u8			cnt_snr_statistic;
-+	u16			snr_statistic_sqr[SNR_RPT_MAX];
-+	u8			snr_statistic[SNR_RPT_MAX];
-+	u8			is_sm_done;
-+	u8			is_snr_done;
-+	u32			cur_snr_var;
-+	u8			total_bit_shift;
-+	u8			total_cnt_snr;
-+	u32			cur_snr_mean;
-+	u8			cur_snr_var0;
-+	u32			cur_lower_snr_mean;
-+	u32			pre_snr_mean;
-+	u32			pre_snr_var;
-+	u32			pre_lower_snr_mean;
-+	u8			nxt_state;
-+	u8			pre_state;
-+#endif
-+	enum lna_sat_type	lna_sat_type;
-+	u32			sat_cnt_acc_patha;
-+	u32			sat_cnt_acc_pathb;
-+#ifdef PHYDM_IC_ABOVE_3SS
-+	u32			sat_cnt_acc_pathc;
-+#endif
-+#ifdef PHYDM_IC_ABOVE_4SS
-+	u32			sat_cnt_acc_pathd;
-+#endif
-+	u32			check_time;
-+	boolean			pre_sat_status;
-+	boolean			cur_sat_status;
-+#ifdef PHYDM_HW_SWITCH_AGC_TAB
-+	boolean			hw_swh_tab_on;
-+	enum odm_rf_band	cur_rf_band;
-+#endif
-+	struct phydm_timer_list	phydm_lna_sat_chk_timer;
-+	u32			cur_timer_check_cnt;
-+	u32			pre_timer_check_cnt;
-+};
-+
-+/* @1 ============================================================
-+ * 1 function prototype
-+ * 1 ============================================================
-+ */
-+void phydm_lna_sat_chk_init(void *dm_void);
-+
-+u8 phydm_get_ofdm_agc_tab(void *dm_void);
-+
-+void phydm_lna_sat_chk(void *dm_void);
-+
-+void phydm_lna_sat_chk_timers(void *dm_void, u8 state);
-+
-+#ifdef PHYDM_LNA_SAT_CHK_TYPE1
-+#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
-+void phydm_lna_sat_chk_bb_init(void *dm_void);
-+
-+void phydm_set_ofdm_agc_tab_path(void *dm_void,
-+				 u8 tab_sel, enum rf_path path);
-+
-+u8 phydm_get_ofdm_agc_tab_path(void *dm_void, enum rf_path path);
-+#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/
-+#endif
-+
-+#ifdef PHYDM_LNA_SAT_CHK_TYPE2
-+void phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr);
-+#endif
-+
-+void phydm_lna_sat_debug(void *dm_void, char input[][16], u32 *_used,
-+			 char *output, u32 *_out_len);
-+
-+void phydm_lna_sat_chk_watchdog(void *dm_void);
-+
-+void phydm_lna_sat_check_init(void *dm_void);
-+
-+#ifdef PHYDM_HW_SWITCH_AGC_TAB
-+void phydm_auto_agc_tab_debug(void *dm_void, char input[][16], u32 *_used,
-+			      char *output, u32 *_out_len);
-+#endif
-+#endif /*@#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_math_lib.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_math_lib.c
-new file mode 100644
-index 000000000000..c6c1035af055
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_math_lib.c
-@@ -0,0 +1,290 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+const u32 db_invert_table[12][8] = {
-+	{10, 13, 16, 20, 25, 32, 40, 50}, /* @U(32,3) */
-+	{64, 80, 101, 128, 160, 201, 256, 318}, /* @U(32,3) */
-+	{401, 505, 635, 800, 1007, 1268, 1596, 2010}, /* @U(32,3) */
-+	{316, 398, 501, 631, 794, 1000, 1259, 1585}, /* @U(32,0) */
-+	{1995, 2512, 3162, 3981, 5012, 6310, 7943, 10000}, /* @U(32,0) */
-+	{12589, 15849, 19953, 25119, 31623, 39811, 50119, 63098}, /* @U(32,0) */
-+	{79433, 100000, 125893, 158489, 199526, 251189, 316228,
-+	 398107}, /* @U(32,0) */
-+	{501187, 630957, 794328, 1000000, 1258925, 1584893, 1995262,
-+	 2511886}, /* @U(32,0) */
-+	{3162278, 3981072, 5011872, 6309573, 7943282, 1000000, 12589254,
-+	 15848932}, /* @U(32,0) */
-+	{19952623, 25118864, 31622777, 39810717, 50118723, 63095734,
-+	 79432823, 100000000}, /* @U(32,0) */
-+	{125892541, 158489319, 199526232, 251188643, 316227766, 398107171,
-+	 501187234, 630957345}, /* @U(32,0) */
-+	{794328235, 1000000000, 1258925412, 1584893192, 1995262315,
-+	 2511886432U, 3162277660U, 3981071706U} }; /* @U(32,0) */
-+
-+/*Y = 10*log(X)*/
-+s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit)
-+{
-+	s32 Y, integer = 0, decimal = 0;
-+	u32 i;
-+
-+	if (X == 0)
-+		X = 1; /* @log2(x), x can't be 0 */
-+
-+	for (i = (total_bit - 1); i > 0; i--) {
-+		if (X & BIT(i)) {
-+			integer = i;
-+			if (i > 0) {
-+				/*decimal is 0.5dB*3=1.5dB~=2dB */
-+				decimal = (X & BIT(i - 1)) ? 2 : 0;
-+			}
-+			break;
-+		}
-+	}
-+
-+	Y = 3 * (integer - decimal_bit) + decimal; /* @10*log(x)=3*log2(x), */
-+
-+	return Y;
-+}
-+
-+s32 odm_sign_conversion(s32 value, u32 total_bit)
-+{
-+	if (value & BIT(total_bit - 1))
-+		value -= BIT(total_bit);
-+
-+	return value;
-+}
-+
-+/*threshold must form low to high*/
-+u16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u16 i = 0;
-+	u16 ret_val = 0;
-+	u16 max_th = threshold[th_len - 1];
-+
-+	for (i = 0; i < th_len; i++) {
-+		if (val < threshold[i]) {
-+			ret_val = i;
-+			break;
-+		} else if (val >= max_th) {
-+			ret_val = th_len;
-+			break;
-+		}
-+	}
-+
-+	return ret_val;
-+}
-+
-+void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
-+		       u8 seq_length)
-+{
-+	u8 i = 0, j = 0;
-+	u32 tmp_a, tmp_b;
-+	u32 tmp_idx_a, tmp_idx_b;
-+
-+	for (i = 0; i < seq_length; i++)
-+		rank_idx[i] = i;
-+
-+	for (i = 0; i < (seq_length - 1); i++) {
-+		for (j = 0; j < (seq_length - 1 - i); j++) {
-+			tmp_a = value[j];
-+			tmp_b = value[j + 1];
-+
-+			tmp_idx_a = rank_idx[j];
-+			tmp_idx_b = rank_idx[j + 1];
-+
-+			if (tmp_a < tmp_b) {
-+				value[j] = tmp_b;
-+				value[j + 1] = tmp_a;
-+
-+				rank_idx[j] = tmp_idx_b;
-+				rank_idx[j + 1] = tmp_idx_a;
-+			}
-+		}
-+	}
-+
-+	for (i = 0; i < seq_length; i++)
-+		idx_out[rank_idx[i]] = i + 1;
-+}
-+
-+u32 odm_convert_to_db(u64 value)
-+{
-+	u8 i;
-+	u8 j;
-+	u32 dB;
-+
-+	if (value >= db_invert_table[11][7])
-+		return 96; /* @maximum 96 dB */
-+
-+	for (i = 0; i < 12; i++) {
-+		if (i <= 2 && (value << FRAC_BITS) <= db_invert_table[i][7])
-+			break;
-+		else if (i > 2 && value <= db_invert_table[i][7])
-+			break;
-+	}
-+
-+	for (j = 0; j < 8; j++) {
-+		if (i <= 2 && (value << FRAC_BITS) <= db_invert_table[i][j])
-+			break;
-+		else if (i > 2 && i < 12 && value <= db_invert_table[i][j])
-+			break;
-+	}
-+
-+	/*special cases*/
-+	if (j == 0 && i == 0)
-+		goto end;
-+
-+	if (i == 3 && j == 0) {
-+		if (db_invert_table[3][0] - value >
-+		    value - (db_invert_table[2][7] >> FRAC_BITS)) {
-+			i = 2;
-+			j = 7;
-+		}
-+		goto end;
-+	}
-+
-+	if (i < 3)
-+		value = value << FRAC_BITS; /*@elements of row 0~2 shift left*/
-+
-+	/*compare difference to get precise dB*/
-+	if (j == 0) {
-+		if (db_invert_table[i][j] - value >
-+		    value - db_invert_table[i - 1][7]) {
-+			i = i - 1;
-+			j = 7;
-+		}
-+	} else {
-+		if (db_invert_table[i][j] - value >
-+		    value - db_invert_table[i][j - 1]) {
-+			j = j - 1;
-+		}
-+	}
-+end:
-+	dB = (i << 3) + j + 1;
-+
-+	return dB;
-+}
-+
-+u64 phydm_db_2_linear(u32 value)
-+{
-+	u8 i = 0;
-+	u8 j = 0;
-+	u64 linear = 0;
-+
-+	value = value & 0xFF;
-+
-+	/* @1dB~96dB */
-+	if (value > 96) {
-+		value = 96;
-+	} else if (value < 1) {
-+		linear = 1;
-+		return linear;
-+	}
-+
-+	i = (u8)((value - 1) >> 3);
-+	j = (u8)(value - 1) - (i << 3);
-+
-+	linear = db_invert_table[i][j];
-+
-+	if (i > 2)
-+		linear = linear << FRAC_BITS;
-+
-+	return linear;
-+}
-+
-+u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num)
-+{
-+	u8 i = 0;
-+	u16 val = 0;
-+	u16 base = 5000;
-+
-+	for (i = bit_num; i > 0; i--) {
-+		if (frac_val & BIT(i - 1))
-+			val += (base >> (bit_num - i));
-+	}
-+	return val;
-+}
-+
-+u16 phydm_ones_num_in_bitmap(u64 val, u8 size)
-+{
-+	u8 i = 0;
-+	u8 ones_num = 0;
-+
-+	for (i = 0; i < size; i++) {
-+		if (val & BIT(0))
-+			ones_num++;
-+
-+		val = val >> 1;
-+	}
-+
-+	return ones_num;
-+}
-+
-+u64 phydm_gen_bitmask(u8 mask_num)
-+{
-+	u8 i = 0;
-+	u64 bitmask = 0;
-+
-+	if (mask_num > 64)
-+		return 1;
-+
-+	for (i = 0; i < mask_num; i++)
-+		bitmask = (bitmask << 1) | BIT(0);
-+
-+	return bitmask;
-+}
-+
-+s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num)
-+{
-+	if (bit_num >= 32)
-+		return (s32)val;
-+
-+	if (val & BIT(bit_num - 1)) /*Sign BIT*/
-+		val -= (1 << bit_num); /*@2's*/
-+
-+	return val;
-+}
-+
-+s64 phydm_cnvrt_2_sign_64(u64 val, u8 bit_num)
-+{
-+	u64 one = 1;
-+	s64 val_sign = (s64)val;
-+
-+	if (bit_num >= 64)
-+		return (s64)val;
-+
-+	if (val & (one << (bit_num - 1))) /*Sign BIT*/
-+		val_sign = val - (one << bit_num); /*@2's*/
-+
-+	return val_sign;
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_math_lib.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_math_lib.h
-new file mode 100644
-index 000000000000..a96ae5ee4826
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_math_lib.h
-@@ -0,0 +1,120 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_MATH_LIB_H__
-+#define __PHYDM_MATH_LIB_H__
-+
-+/* @2019.01.24 remove linear2db debug log*/
-+#define AUTO_MATH_LIB_VERSION "1.2"
-+
-+/*@
-+ * 1 ============================================================
-+ * 1  Definition
-+ * 1 ============================================================
-+ */
-+
-+#define PHYDM_DIV(a, b) ((b) ? ((a) / (b)) : 0)
-+#define DIVIDED_2(X) ((X) >> 1)
-+/*@1/3 ~ 11/32*/
-+#if defined(DM_ODM_CE_MAC80211)
-+#define DIVIDED_3(X) ({	\
-+	u32 div_3_tmp = (X);	\
-+	(((div_3_tmp) + ((div_3_tmp) << 1) + ((div_3_tmp) << 3)) >> 5); })
-+#else
-+#define DIVIDED_3(X) (((X) + ((X) << 1) + ((X) << 3)) >> 5)
-+#endif
-+#define DIVIDED_4(X) ((X) >> 2)
-+
-+/*Store Ori Value*/
-+#if defined(DM_ODM_CE_MAC80211)
-+#define WEIGHTING_AVG(v1, w1, v2, w2)	\
-+	__WEIGHTING_AVG(v1, w1, v2, w2, typeof(v1), typeof(w1), typeof(v2), \
-+			typeof(w2))
-+#define __WEIGHTING_AVG(v1, w1, v2, w2, t1, t2, t3, t4)	({	\
-+	t1 __w_a_v1 = (v1);	\
-+	t2 __w_a_w1 = (w1);	\
-+	t3 __w_a_v2 = (v2);	\
-+	t4 __w_a_w2 = (w2);	\
-+	((__w_a_v1) * (__w_a_w1) + (__w_a_v2) * (__w_a_w2))	\
-+	/ ((__w_a_w2) + (__w_a_w1)); })
-+#else
-+#define WEIGHTING_AVG(v1, w1, v2, w2) \
-+	(((v1) * (w1) + (v2) * (w2)) / ((w2) + (w1)))
-+#endif
-+
-+/*Store 2^ma x Value*/
-+#if defined(DM_ODM_CE_MAC80211)
-+#define MA_ACC(old, new_val, ma) ({	\
-+	s16 __ma_acc_o = (old);		\
-+	(__ma_acc_o) - ((__ma_acc_o) >> (ma)) + (new_val); })
-+#define GET_MA_VAL(val, ma) ({	\
-+	s16 __get_ma_tmp = (ma);\
-+	((val) + (1 << ((__get_ma_tmp) - 1))) >> (__get_ma_tmp); })
-+#else
-+#define MA_ACC(old, new_val, ma) ((old) - ((old) >> (ma)) + (new_val))
-+#define GET_MA_VAL(val, ma) (((val) + (1 << ((ma) - 1))) >> (ma))
-+#endif
-+#define FRAC_BITS 3
-+/*@
-+ * 1 ============================================================
-+ * 1  enumeration
-+ * 1 ============================================================
-+ */
-+
-+/*@
-+ * 1 ============================================================
-+ * 1  structure
-+ * 1 ============================================================
-+ */
-+
-+/*@
-+ * 1 ============================================================
-+ * 1  function prototype
-+ * 1 ============================================================
-+ */
-+
-+s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit);
-+
-+s32 odm_sign_conversion(s32 value, u32 total_bit);
-+
-+u16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len);
-+
-+void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
-+		       u8 seq_length);
-+
-+u32 odm_convert_to_db(u64 value);
-+
-+u64 phydm_db_2_linear(u32 value);
-+
-+u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num);
-+
-+u16 phydm_ones_num_in_bitmap(u64 val, u8 size);
-+
-+u64 phydm_gen_bitmask(u8 mask_num);
-+
-+s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num);
-+
-+s64 phydm_cnvrt_2_sign_64(u64 val, u8 bit_num);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_mp.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_mp.c
-new file mode 100644
-index 000000000000..4b2bd52faabd
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_mp.c
-@@ -0,0 +1,408 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef PHYDM_MP_SUPPORT
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+
-+void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
-+				   u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_mp *mp = &dm->dm_mp_table;
-+	u8 start = RF_PATH_A, end = RF_PATH_A;
-+	u8 i = 0;
-+	u8 central_ch = 0;
-+	boolean is_2g_ch = false;
-+
-+	switch (path) {
-+	case RF_PATH_A:
-+	case RF_PATH_B:
-+	case RF_PATH_C:
-+	case RF_PATH_D:
-+		start = path;
-+		end = path;
-+		break;
-+	case RF_PATH_AB:
-+		start = RF_PATH_A;
-+		end = RF_PATH_B;
-+		break;
-+#if (defined(PHYDM_COMPILE_IC_4SS))
-+	case RF_PATH_AC:
-+		start = RF_PATH_A;
-+		end = RF_PATH_C;
-+		break;
-+	case RF_PATH_AD:
-+		start = RF_PATH_A;
-+		end = RF_PATH_D;
-+		break;
-+	case RF_PATH_BC:
-+		start = RF_PATH_B;
-+		end = RF_PATH_C;
-+		break;
-+	case RF_PATH_BD:
-+		start = RF_PATH_B;
-+		end = RF_PATH_D;
-+		break;
-+	case RF_PATH_CD:
-+		start = RF_PATH_C;
-+		end = RF_PATH_D;
-+		break;
-+	case RF_PATH_ABC:
-+		start = RF_PATH_A;
-+		end = RF_PATH_C;
-+		break;
-+	case RF_PATH_ABD:
-+		start = RF_PATH_A;
-+		end = RF_PATH_D;
-+		break;
-+	case RF_PATH_ACD:
-+		start = RF_PATH_A;
-+		end = RF_PATH_D;
-+		break;
-+	case RF_PATH_BCD:
-+		start = RF_PATH_B;
-+		end = RF_PATH_D;
-+		break;
-+	case RF_PATH_ABCD:
-+		start = RF_PATH_A;
-+		end = RF_PATH_D;
-+		break;
-+#endif
-+	}
-+
-+	central_ch = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff);
-+	is_2g_ch = (central_ch <= 14) ? true : false;
-+
-+	if (is_single_tone) {
-+		/*Disable CCA*/
-+		if (is_2g_ch) { /*CCK RxIQ weighting = [0,0]*/
-+			if(dm->support_ic_type & ODM_RTL8723F) {
-+				odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x1); /*CCK*/
-+			} else {
-+				odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x0);
-+				odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
-+			}
-+		}
-+		odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff); /*OFDM*/
-+		if (dm->support_ic_type & ODM_RTL8723F) {
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x5, BIT(0), 0x0);
-+			for (i = start; i <= end; i++) {
-+				mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK);
-+				/*Tx mode: RF0x00[19:16]=4'b0010 */
-+				odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
-+				/*Lowest RF gain index: RF_0x1[5:0] TX power*/
-+				mp->rf1[i] = odm_get_rf_reg(dm, i, RF_0x1, RFREG_MASK);
-+				odm_set_rf_reg(dm, i, RF_0x1, 0x3f, 0x0);//TX power
-+				/*RF LO enabled */
-+				odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
-+			}
-+		} else {
-+			for (i = start; i <= end; i++) {
-+				mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK);
-+				/*Tx mode: RF0x00[19:16]=4'b0010 */
-+				odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
-+				/*Lowest RF gain index: RF_0x0[4:0] = 0*/
-+				odm_set_rf_reg(dm, i, RF_0x0, 0x1f, 0x0);
-+				/*RF LO enabled */
-+				odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
-+			}
-+		}
-+		
-+		#if (RTL8814B_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8814B) {
-+			mp->rf0_syn[RF_SYN0] = config_phydm_read_syn_reg_8814b(
-+					       dm, RF_SYN0, RF_0x0, RFREG_MASK);
-+			/*Lowest RF gain index: RF_0x0[4:0] = 0x0*/
-+			config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
-+							0x1f, 0x0);
-+			/*RF LO enabled */
-+			config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
-+							BIT(1), 0x1);
-+			/*SYN1*/
-+			if (*dm->band_width == CHANNEL_WIDTH_80_80) {
-+				mp->rf0_syn[RF_SYN1] = config_phydm_read_syn_reg_8814b(
-+						       dm, RF_SYN1, RF_0x0,
-+						       RFREG_MASK);
-+				config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
-+								RF_0x0, 0x1f,
-+								0x0);
-+				config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
-+								RF_0x58, BIT(1),
-+								0x1);
-+			}
-+		}
-+		#endif
-+	} else {
-+		/*Enable CCA*/
-+		if (is_2g_ch) { /*CCK RxIQ weighting = [1,1]*/
-+			if(dm->support_ic_type & ODM_RTL8723F) {
-+				odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x0); /*CCK*/ 
-+			} else {
-+				odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x1);
-+				odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
-+			}
-+		}
-+		odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0); /*OFDM*/
-+
-+		if(dm->support_ic_type & ODM_RTL8723F) {
-+			for (i = start; i <= end; i++) {
-+				odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]);
-+				odm_set_rf_reg(dm, i, RF_0x1, RFREG_MASK, mp->rf1[i]);
-+				/*RF LO disabled */
-+				odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
-+			}
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x5, BIT(0), 0x1);
-+		} else {
-+			for (i = start; i <= end; i++) {
-+				odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]);
-+				/*RF LO disabled */
-+				odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
-+			}
-+		}
-+		#if (RTL8814B_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8814B) {
-+			config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
-+							RFREG_MASK,
-+							mp->rf0_syn[RF_SYN0]);
-+			config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
-+							BIT(1), 0x0);
-+			/*SYN1*/
-+			if (*dm->band_width == CHANNEL_WIDTH_80_80) {
-+				config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
-+								RF_0x0,
-+								RFREG_MASK,
-+								mp->rf0_syn[RF_SYN1]);
-+				config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
-+								RF_0x58, BIT(1),
-+								0x0);
-+			}
-+		}
-+		#endif
-+	}
-+}
-+
-+void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,
-+				    u32 rate_index)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_mp *mp = &dm->dm_mp_table;
-+
-+	if (is_carrier_supp) {
-+		if (phydm_is_cck_rate(dm, (u8)rate_index)) {
-+			/*if CCK block on? */
-+			if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
-+				odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);
-+
-+			if(dm->support_ic_type & ODM_RTL8723F){
-+				/* @Carrier suppress tx */
-+				odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x1);
-+				/*turn off scramble setting */
-+				odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x1);
-+				/*Set CCK Tx Test Rate, set TxRate to 2Mbps */
-+				odm_set_bb_reg(dm, R_0x2a08, 0x300000, 0x1);
-+				/* BB and PMAC cont tx */
-+				odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x1);
-+				odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x1);
-+				/* TX CCK ON */
-+				odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
-+				odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
-+			}
-+			else {
-+				/*Turn Off All Test mode */
-+				odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
-+				
-+				/*transmit mode */
-+				odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2);	
-+				/*turn off scramble setting */
-+				odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x0);
-+				/*Set CCK Tx Test Rate, set TxRate to 1Mbps */
-+				odm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0);
-+			}
-+		}
-+	} else { /*Stop Carrier Suppression. */
-+		if (phydm_is_cck_rate(dm, (u8)rate_index)) {
-+			if(dm->support_ic_type & ODM_RTL8723F) {
-+				/* TX Stop */
-+				odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x1);
-+				/* Clear BB cont tx */
-+				odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x0);
-+				/* Clear PMAC cont tx */
-+				odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x0);
-+				/* Clear TX Stop */
-+				odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x0);
-+				/* normal mode */
-+				odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x0);
-+				/* turn on scramble setting */
-+				odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0);
-+			}
-+			else {
-+				/*normal mode */
-+				odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);			
-+				/*turn on scramble setting */
-+				odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
-+			}
-+			/*BB Reset */
-+			odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
-+			odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
-+		}
-+	}
-+}
-+
-+void phydm_mp_set_single_carrier_jgr3(void *dm_void, boolean is_single_carrier)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_mp *mp = &dm->dm_mp_table;
-+
-+	if (is_single_carrier) {
-+		/*1. if OFDM block on? */
-+		if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
-+			odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
-+		
-+		if (dm->support_ic_type & ODM_RTL8723F) {
-+			/*3. turn on scramble setting */
-+			odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0);
-+			/*4. Turn On single carrier. */
-+			odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
-+		}
-+		else {
-+			/*2. set CCK test mode off, set to CCK normal mode */
-+			odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
-+			/*3. turn on scramble setting */
-+			odm_set_bb_reg(dm, R_0x1a00, BIT(3), 1);
-+			/*4. Turn On single carrier. */
-+			odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
-+		}
-+	} else {
-+		/*Turn off all test modes. */
-+		odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF);
-+
-+		/*Delay 10 ms */
-+		ODM_delay_ms(10);
-+
-+		/*BB Reset*/
-+		odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
-+		odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
-+	}
-+}
-+
-+void phydm_mp_get_tx_ok_jgr3(void *dm_void, u32 rate_index)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_mp *mp = &dm->dm_mp_table;
-+
-+	if (phydm_is_cck_rate(dm, (u8)rate_index))
-+		mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
-+	else
-+		mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de0, MASKLWORD);
-+}
-+
-+void phydm_mp_get_rx_ok_jgr3(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_mp *mp = &dm->dm_mp_table;
-+
-+	u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0;
-+	u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0;
-+	if(dm->support_ic_type & ODM_RTL8723F)
-+		cck_ok = odm_get_bb_reg(dm, R_0x2aac, MASKLWORD);
-+	else
-+		cck_ok = odm_get_bb_reg(dm, R_0x2c04, MASKLWORD);
-+	ofdm_ok = odm_get_bb_reg(dm, R_0x2c14, MASKLWORD);
-+	ht_ok = odm_get_bb_reg(dm, R_0x2c10, MASKLWORD);
-+	vht_ok = odm_get_bb_reg(dm, R_0x2c0c, MASKLWORD);
-+	if(dm->support_ic_type & ODM_RTL8723F)
-+		cck_err = odm_get_bb_reg(dm, R_0x2aac, MASKHWORD);
-+	else
-+		cck_err = odm_get_bb_reg(dm, R_0x2c04, MASKHWORD);
-+	ofdm_err = odm_get_bb_reg(dm, R_0x2c14, MASKHWORD);
-+	ht_err = odm_get_bb_reg(dm, R_0x2c10, MASKHWORD);
-+	vht_err = odm_get_bb_reg(dm, R_0x2c0c, MASKHWORD);
-+
-+	mp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok;
-+	mp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err;
-+	mp->io_value = (u32)mp->rx_phy_ok_cnt;
-+}
-+#endif
-+void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	phydm_set_crystal_cap(dm, crystal_cap);
-+}
-+
-+void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		phydm_mp_set_single_tone_jgr3(dm, is_single_tone, path);
-+}
-+
-+void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
-+			       u32 rate_index)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		phydm_mp_set_carrier_supp_jgr3(dm, is_carrier_supp, rate_index);
-+}
-+
-+void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		phydm_mp_set_single_carrier_jgr3(dm, is_single_carrier);
-+}
-+void phydm_mp_reset_rx_counters_phy(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	phydm_reset_bb_hw_cnt(dm);
-+}
-+
-+void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		phydm_mp_get_tx_ok_jgr3(dm, rate_index);
-+}
-+
-+void phydm_mp_get_rx_ok(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		phydm_mp_get_rx_ok_jgr3(dm);
-+}
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_mp.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_mp.h
-new file mode 100644
-index 000000000000..5805a0378e4a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_mp.h
-@@ -0,0 +1,83 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_MP_H__
-+#define __PHYDM_MP_H__
-+
-+/*2020.04.27 Refine single tone Tx flow*/
-+#define MP_VERSION "1.5"
-+
-+/* @1 ============================================================
-+ * 1  Definition
-+ * 1 ============================================================
-+ */
-+/* @1 ============================================================
-+ * 1  structure
-+ * 1 ============================================================
-+ */
-+struct phydm_mp {
-+	/*Rx OK count, statistics used in Mass Production Test.*/
-+	u64 tx_phy_ok_cnt;
-+	u64 rx_phy_ok_cnt;
-+	/*Rx CRC32 error count, statistics used in Mass Production Test.*/
-+	u64 rx_phy_crc_err_cnt;
-+	/*The Value of IO operation is depend of MptActType.*/
-+	u32 io_value;
-+	u32 rf0[RF_PATH_MEM_SIZE];
-+	#if (RTL8814B_SUPPORT)
-+	u32 rf0_syn[2];
-+	#endif
-+	u32 rf1[RF_PATH_MEM_SIZE];
-+};
-+
-+/* @1 ============================================================
-+ * 1  enumeration
-+ * 1 ============================================================
-+ */
-+enum TX_MODE_OFDM {
-+	OFDM_OFF = 0,	
-+	OFDM_CONT_TX = 1,
-+	OFDM_SINGLE_CARRIER = 2,
-+	OFDM_SINGLE_TONE = 4,
-+};
-+/* @1 ============================================================
-+ * 1  function prototype
-+ * 1 ============================================================
-+ */
-+void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap);
-+
-+void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path);
-+
-+void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
-+			       u32 rate_index);
-+
-+void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier);
-+
-+void phydm_mp_reset_rx_counters_phy(void *dm_void);
-+
-+void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index);
-+
-+void phydm_mp_get_rx_ok(void *dm_void);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_noisemonitor.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_noisemonitor.c
-new file mode 100644
-index 000000000000..d2e95cfa0233
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_noisemonitor.c
-@@ -0,0 +1,467 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*************************************************************
-+ * include files
-+ ************************************************************/
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+/**************************************************
-+ * This function is for inband noise test utility only
-+ * To obtain the inband noise level(dbm), do the following.
-+ * 1. disable DIG and Power Saving
-+ * 2. Set initial gain = 0x1a
-+ * 3. Stop updating idle time pwer report (for driver read)
-+ *	- 0x80c[25]
-+ *
-+ *************************************************/
-+
-+void phydm_set_noise_data_sum(struct noise_level *noise_data, u8 max_rf_path)
-+{
-+	u8 i = 0;
-+
-+	for (i = RF_PATH_A; i < max_rf_path; i++) {
-+		if (noise_data->valid_cnt[i])
-+			noise_data->sum[i] /= noise_data->valid_cnt[i];
-+		else
-+			noise_data->sum[i] = 0;
-+	}
-+}
-+
-+#if (ODM_IC_11N_SERIES_SUPPORT)
-+s16 odm_inband_noise_monitor_n(struct dm_struct *dm, u8 is_pause_dig, u8 igi,
-+			       u32 max_time)
-+{
-+	u32 tmp4b;
-+	u8 max_rf_path = 0, i = 0;
-+	u8 reg_c50, reg_c58, valid_done = 0;
-+	struct noise_level noise_data;
-+	u64 start = 0, func_start = 0, func_end = 0;
-+	s8 val_s8 = 0;
-+
-+	func_start = odm_get_current_time(dm);
-+	dm->noise_level.noise_all = 0;
-+
-+	if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R)
-+		max_rf_path = 2;
-+	else
-+		max_rf_path = 1;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "odm_DebugControlInbandNoise_Nseries() ==>\n");
-+
-+	odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
-+	/* step 1. Disable DIG && Set initial gain. */
-+
-+	if (is_pause_dig)
-+		odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
-+
-+	/* step 3. Get noise power level */
-+	start = odm_get_current_time(dm);
-+	while (1) {
-+		/* Stop updating idle time pwer report (for driver read) */
-+		odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1);
-+
-+		/* Read Noise Floor Report */
-+		tmp4b = odm_get_bb_reg(dm, R_0x8f8, MASKDWORD);
-+
-+		/* update idle time pwer report per 5us */
-+		odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0);
-+
-+		ODM_delay_us(5);
-+
-+		noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);
-+		noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
-+
-+		for (i = RF_PATH_A; i < max_rf_path; i++) {
-+			noise_data.sval[i] = (s8)noise_data.value[i];
-+			noise_data.sval[i] /= 2;
-+		}
-+
-+		for (i = RF_PATH_A; i < max_rf_path; i++) {
-+			if (noise_data.valid_cnt[i] >= VALID_CNT)
-+				continue;
-+
-+			noise_data.valid_cnt[i]++;
-+			noise_data.sum[i] += noise_data.sval[i];
-+			PHYDM_DBG(dm, DBG_ENV_MNTR,
-+				  "rf_path:%d Valid sval=%d\n", i,
-+				  noise_data.sval[i]);
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n",
-+				  noise_data.sum[i]);
-+			if (noise_data.valid_cnt[i] == VALID_CNT)
-+				valid_done++;
-+		}
-+		if (valid_done == max_rf_path ||
-+		    (odm_get_progressing_time(dm, start) > max_time)) {
-+			phydm_set_noise_data_sum(&noise_data, max_rf_path);
-+			break;
-+		}
-+	}
-+	reg_c50 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0);
-+	reg_c50 &= ~BIT(7);
-+	val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
-+	dm->noise_level.noise[RF_PATH_A] = val_s8;
-+	dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];
-+
-+	if (max_rf_path == 2) {
-+		reg_c58 = (u8)odm_get_bb_reg(dm, R_0xc58, MASKBYTE0);
-+		reg_c58 &= ~BIT(7);
-+		val_s8 = (s8)(-110 + reg_c58 + noise_data.sum[RF_PATH_B]);
-+		dm->noise_level.noise[RF_PATH_B] = val_s8;
-+		dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];
-+	}
-+	dm->noise_level.noise_all /= max_rf_path;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "noise_a = %d, noise_b = %d, noise_all = %d\n",
-+		  dm->noise_level.noise[RF_PATH_A],
-+		  dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all);
-+
-+	/* step 4. Recover the Dig */
-+	if (is_pause_dig)
-+		odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
-+	func_end = odm_get_progressing_time(dm, func_start);
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n");
-+	return dm->noise_level.noise_all;
-+}
-+#endif
-+
-+#if (ODM_IC_11AC_SERIES_SUPPORT)
-+s16 phydm_idle_noise_measure_ac(struct dm_struct *dm, u8 pause_dig,
-+				u8 igi, u32 max_time)
-+{
-+	u32 tmp4b;
-+	u8 max_rf_path = 0, i = 0;
-+	u8 reg_c50, reg_e50, valid_done = 0;
-+	u64 start = 0, func_start = 0, func_end = 0;
-+	struct noise_level noise_data;
-+	s8 val_s8 = 0;
-+
-+	func_start = odm_get_current_time(dm);
-+	dm->noise_level.noise_all = 0;
-+
-+	if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R)
-+		max_rf_path = 2;
-+	else
-+		max_rf_path = 1;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "%s==>\n", __func__);
-+
-+	odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
-+
-+	/*Step 1. Disable DIG && Set initial gain.*/
-+
-+	if (pause_dig)
-+		odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
-+
-+	/*Step 2. Get noise power level*/
-+	start = odm_get_current_time(dm);
-+
-+	while (1) {
-+		/*Stop updating idle time pwer report (for driver read)*/
-+		odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x1);
-+
-+		/*Read Noise Floor Report*/
-+		tmp4b = odm_get_bb_reg(dm, R_0xff0, MASKDWORD);
-+
-+		/*update idle time pwer report per 5us*/
-+		odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x0);
-+
-+		ODM_delay_us(5);
-+
-+		noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);
-+		noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
-+
-+		for (i = RF_PATH_A; i < max_rf_path; i++) {
-+			noise_data.sval[i] = (s8)noise_data.value[i];
-+			noise_data.sval[i] = noise_data.sval[i] >> 1;
-+		}
-+
-+		for (i = RF_PATH_A; i < max_rf_path; i++) {
-+			if (noise_data.valid_cnt[i] >= VALID_CNT)
-+				continue;
-+
-+			noise_data.valid_cnt[i]++;
-+			noise_data.sum[i] += noise_data.sval[i];
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Path:%d Valid sval = %d\n",
-+				  i, noise_data.sval[i]);
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d\n",
-+				  noise_data.sum[i]);
-+			if (noise_data.valid_cnt[i] == VALID_CNT)
-+				valid_done++;
-+		}
-+
-+		if (valid_done == max_rf_path ||
-+		    (odm_get_progressing_time(dm, start) > max_time)) {
-+			phydm_set_noise_data_sum(&noise_data, max_rf_path);
-+			break;
-+		}
-+	}
-+	reg_c50 = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
-+	reg_c50 &= ~BIT(7);
-+	val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
-+	dm->noise_level.noise[RF_PATH_A] = val_s8;
-+	dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];
-+
-+	if (max_rf_path == 2) {
-+		reg_e50 = (u8)odm_get_bb_reg(dm, R_0xe50, MASKBYTE0);
-+		reg_e50 &= ~BIT(7);
-+		val_s8 = (s8)(-110 + reg_e50 + noise_data.sum[RF_PATH_B]);
-+		dm->noise_level.noise[RF_PATH_B] = val_s8;
-+		dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];
-+	}
-+	dm->noise_level.noise_all /= max_rf_path;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "noise_a = %d, noise_b = %d, noise_all = %d\n",
-+		  dm->noise_level.noise[RF_PATH_A],
-+		  dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all);
-+
-+	/*Step 3. Recover the Dig*/
-+	if (pause_dig)
-+		odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
-+	func_end = odm_get_progressing_time(dm, func_start);
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n");
-+	return dm->noise_level.noise_all;
-+}
-+
-+s16 odm_inband_noise_monitor_ac(struct dm_struct *dm, u8 pause_dig, u8 igi,
-+				u32 max_time)
-+{
-+	s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
-+	s32 value32, pwdb_A = 0, sval, noise, sum = 0;
-+	boolean pd_flag;
-+	u8 valid_cnt = 0;
-+	u8 invalid_cnt = 0;
-+	u64 start = 0, func_start = 0, func_end = 0, proc_time = 0;
-+	s32 val_s32 = 0;
-+	s16 rpt = 0;
-+	u8 val_u8 = 0;
-+
-+	if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
-+		rpt = phydm_idle_noise_measure_ac(dm, pause_dig, igi, max_time);
-+		return rpt;
-+	}
-+
-+	if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))
-+		return 0;
-+
-+	func_start = odm_get_current_time(dm);
-+	dm->noise_level.noise_all = 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "%s ==>\n", __func__);
-+
-+	/* step 1. Disable DIG && Set initial gain. */
-+	if (pause_dig)
-+		odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
-+
-+	/* step 3. Get noise power level */
-+	start = odm_get_current_time(dm);
-+
-+	/* step 3. Get noise power level */
-+	while (1) {
-+		/*Set IGI=0x1C */
-+		odm_write_dig(dm, 0x1C);
-+		/*stop CK320&CK88 */
-+		odm_set_bb_reg(dm, R_0x8b4, BIT(6), 1);
-+		/*Read path-A */
-+		/*set debug port*/
-+		odm_set_bb_reg(dm, R_0x8fc, MASKDWORD, 0x200);
-+		/*read debug port*/
-+		value32 = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD);
-+		/*rxi_buf_anta=RegFA0[19:10]*/
-+		rxi_buf_anta = (value32 & 0xFFC00) >> 10;
-+		rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/
-+
-+		pd_flag = (boolean)((value32 & BIT(31)) >> 31);
-+
-+		/*Not in packet detection period or Tx state */
-+		if (!pd_flag || rxi_buf_anta != 0x200) {
-+			/*sign conversion*/
-+			rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10);
-+			rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10);
-+
-+			val_s32 = rxi_buf_anta * rxi_buf_anta +
-+				  rxq_buf_anta * rxq_buf_anta;
-+			/*S(10,9)*S(10,9)=S(20,18)*/
-+			pwdb_A = odm_pwdb_conversion(val_s32, 20, 18);
-+
-+			PHYDM_DBG(dm, DBG_ENV_MNTR,
-+				  "pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n",
-+				  pwdb_A, rxi_buf_anta & 0x3FF,
-+				  rxq_buf_anta & 0x3FF);
-+		}
-+		/*Start CK320&CK88*/
-+		odm_set_bb_reg(dm, R_0x8b4, BIT(6), 0);
-+		/*@BB Reset*/
-+		val_u8 = odm_read_1byte(dm, 0x02) & (~BIT(0));
-+		odm_write_1byte(dm, 0x02, val_u8);
-+		val_u8 = odm_read_1byte(dm, 0x02) | BIT(0);
-+		odm_write_1byte(dm, 0x02, val_u8);
-+		/*PMAC Reset*/
-+		val_u8 = odm_read_1byte(dm, 0xB03) & (~BIT(0));
-+		odm_write_1byte(dm, 0xB03, val_u8);
-+		val_u8 = odm_read_1byte(dm, 0xB03) | BIT(0);
-+		odm_write_1byte(dm, 0xB03, val_u8);
-+		/*@CCK Reset*/
-+		if (odm_read_1byte(dm, 0x80B) & BIT(4)) {
-+			val_u8 = odm_read_1byte(dm, 0x80B) & (~BIT(4));
-+			odm_write_1byte(dm, 0x80B, val_u8);
-+			val_u8 = odm_read_1byte(dm, 0x80B) | BIT(4);
-+			odm_write_1byte(dm, 0x80B, val_u8);
-+		}
-+
-+		sval = pwdb_A;
-+
-+		if ((sval < 0 && sval >= -27) && valid_cnt < VALID_CNT) {
-+			valid_cnt++;
-+			sum += sval;
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Valid sval = %d\n", sval);
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", sum);
-+			if (valid_cnt >= VALID_CNT ||
-+			    (odm_get_progressing_time(dm, start) > max_time)) {
-+				sum /= VALID_CNT;
-+				PHYDM_DBG(dm, DBG_ENV_MNTR,
-+					  "After divided, sum = %d\n", sum);
-+				break;
-+			}
-+		} else {
-+			/*Invalid sval and return -110 dBm*/
-+			invalid_cnt++;
-+			PHYDM_DBG(dm, DBG_ENV_MNTR, "Invalid sval\n");
-+			if (invalid_cnt >= VALID_CNT + 5) {
-+				PHYDM_DBG(dm, DBG_ENV_MNTR,
-+					  "Invalid count > TH, Return -110, Break!!\n");
-+				return -110;
-+			}
-+		}
-+	}
-+
-+	/*@ADC backoff is 12dB,*/
-+	/*Ptarget=0x1C-110=-82dBm*/
-+	noise = sum + 12 + 0x1C - 110;
-+
-+	/*Offset*/
-+	noise = noise - 3;
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "noise = %d\n", noise);
-+	dm->noise_level.noise_all = (s16)noise;
-+
-+	/* step 4. Recover the Dig*/
-+	if (pause_dig)
-+		odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
-+
-+	func_end = odm_get_progressing_time(dm, func_start);
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR, "%s <==\n", __func__);
-+
-+	return dm->noise_level.noise_all;
-+}
-+#endif
-+
-+s16 odm_inband_noise_monitor(void *dm_void, u8 pause_dig, u8 igi,
-+			     u32 max_time)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	s16 val = 0;
-+
-+	igi = 0x32;
-+
-+	/* since HW ability is about +15~-35,
-+	 * we fix IGI = -60 for maximum coverage
-+	 */
-+	#if (ODM_IC_11AC_SERIES_SUPPORT)
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES)
-+		val = odm_inband_noise_monitor_ac(dm, pause_dig, igi, max_time);
-+	#endif
-+
-+	#if (ODM_IC_11N_SERIES_SUPPORT)
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES)
-+		val = odm_inband_noise_monitor_n(dm, pause_dig, igi, max_time);
-+	#endif
-+
-+	return val;
-+}
-+
-+void phydm_noisy_detection(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 total_fa_cnt, total_cca_cnt;
-+	u32 score = 0, i, score_smooth;
-+
-+	total_cca_cnt = dm->false_alm_cnt.cnt_cca_all;
-+	total_fa_cnt = dm->false_alm_cnt.cnt_all;
-+
-+#if 0
-+	if (total_fa_cnt * 16 >= total_cca_cnt * 14)    /*  @87.5 */
-+		;
-+	else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /*  @75 */
-+		;
-+	else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /*  @56.25 */
-+		;
-+	else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /*  @50 */
-+		;
-+	else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /*  @43.75 */
-+		;
-+	else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /*  @37.5 */
-+		;
-+	else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /*  @31.25% */
-+		;
-+	else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /*  @25% */
-+		;
-+	else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /*  @18.75% */
-+		;
-+	else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /*  @12.5% */
-+		;
-+	else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /*  @6.25% */
-+		;
-+#endif
-+	for (i = 0; i <= 16; i++) {
-+		if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) {
-+			score = 16 - i;
-+			break;
-+		}
-+	}
-+
-+	/* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */
-+	dm->noisy_decision_smooth = (dm->noisy_decision_smooth >> 1) +
-+				    (score << 2);
-+
-+	/* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */
-+	if (total_cca_cnt >= 300)
-+		score_smooth = (dm->noisy_decision_smooth + 3) >> 3;
-+	else
-+		score_smooth = 0;
-+
-+	dm->noisy_decision = (score_smooth >= 3) ? 1 : 0;
-+
-+	PHYDM_DBG(dm, DBG_ENV_MNTR,
-+		  "[NoisyDetection] CCA_cnt=%d,FA_cnt=%d, noisy_dec_smooth=%d, score=%d, score_smooth=%d, noisy_dec=%d\n",
-+		  total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score,
-+		  score_smooth, dm->noisy_decision);
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_noisemonitor.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_noisemonitor.h
-new file mode 100644
-index 000000000000..507285adb5bb
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_noisemonitor.h
-@@ -0,0 +1,48 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+#ifndef __ODMNOISEMONITOR_H__
-+#define __ODMNOISEMONITOR_H__
-+
-+#define VALID_CNT 5
-+
-+struct noise_level {
-+	u8 value[PHYDM_MAX_RF_PATH];
-+	s8 sval[PHYDM_MAX_RF_PATH];
-+	s32 sum[PHYDM_MAX_RF_PATH];
-+	u8 valid[PHYDM_MAX_RF_PATH];
-+	u8 valid_cnt[PHYDM_MAX_RF_PATH];
-+};
-+
-+struct odm_noise_monitor {
-+	s8 noise[PHYDM_MAX_RF_PATH];
-+	s16 noise_all;
-+};
-+
-+s16 odm_inband_noise_monitor(void *dm_void, u8 is_pause_dig, u8 igi_value,
-+			     u32 max_time);
-+
-+void phydm_noisy_detection(void *dm_void);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_pathdiv.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_pathdiv.c
-new file mode 100644
-index 000000000000..a6b347cf75b2
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_pathdiv.c
-@@ -0,0 +1,1113 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*************************************************************
-+ * include files
-+ ************************************************************/
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef CONFIG_PATH_DIVERSITY
-+#if RTL8814A_SUPPORT
-+void phydm_dtp_fix_tx_path(
-+	void *dm_void,
-+	u8 path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+	u8 i, num_enable_path = 0;
-+
-+	if (path == p_div->pre_tx_path)
-+		return;
-+	else
-+		p_div->pre_tx_path = path;
-+
-+	odm_set_bb_reg(dm, R_0x93c, BIT(18) | BIT(19), 3);
-+
-+	for (i = 0; i < 4; i++) {
-+		if (path & BIT(i))
-+			num_enable_path++;
-+	}
-+	PHYDM_DBG(dm, DBG_PATH_DIV, " number of turn-on path : (( %d ))\n",
-+		  num_enable_path);
-+
-+	if (num_enable_path == 1) {
-+		odm_set_bb_reg(dm, R_0x93c, 0xf00000, path);
-+
-+		if (path == BB_PATH_A) { /* @1-1 */
-+			PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A ))\n");
-+			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
-+		} else if (path == BB_PATH_B) { /* @1-2 */
-+			PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( B ))\n");
-+			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);
-+		} else if (path == BB_PATH_C) { /* @1-3 */
-+			PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( C ))\n");
-+			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 0);
-+
-+		} else if (path == BB_PATH_D) { /* @1-4 */
-+			PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( D ))\n");
-+			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 0);
-+		}
-+
-+	} else if (num_enable_path == 2) {
-+		odm_set_bb_reg(dm, R_0x93c, 0xf00000, path);
-+		odm_set_bb_reg(dm, R_0x940, 0xf0, path);
-+
-+		if (path == (BB_PATH_AB)) { /* @2-1 */
-+			PHYDM_DBG(dm, DBG_PATH_DIV,
-+				  " Turn on path (( A B ))\n");
-+			/* set for 1ss */
-+			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
-+			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1);
-+			/* set for 2ss */
-+			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
-+			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1);
-+		} else if (path == BB_PATH_AC) { /* @2-2 */
-+			PHYDM_DBG(dm, DBG_PATH_DIV,
-+				  " Turn on path (( A C ))\n");
-+			/* set for 1ss */
-+			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
-+			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);
-+			/* set for 2ss */
-+			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
-+			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);
-+		} else if (path == BB_PATH_AD) { /* @2-3 */
-+			PHYDM_DBG(dm, DBG_PATH_DIV,
-+				  " Turn on path (( A D ))\n");
-+			/* set for 1ss */
-+			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
-+			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1);
-+			/* set for 2ss */
-+			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
-+			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1);
-+		} else if (path == BB_PATH_BC) { /* @2-4 */
-+			PHYDM_DBG(dm, DBG_PATH_DIV,
-+				  " Turn on path (( B C ))\n");
-+			/* set for 1ss */
-+			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);
-+			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);
-+			/* set for 2ss */
-+			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0);
-+			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);
-+		} else if (path == BB_PATH_BD) { /* @2-5 */
-+			PHYDM_DBG(dm, DBG_PATH_DIV,
-+				  " Turn on path (( B D ))\n");
-+			/* set for 1ss */
-+			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);
-+			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1);
-+			/* set for 2ss */
-+			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0);
-+			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1);
-+		} else if (path == BB_PATH_CD) { /* @2-6 */
-+			PHYDM_DBG(dm, DBG_PATH_DIV,
-+				  " Turn on path (( C D ))\n");
-+			/* set for 1ss */
-+			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 0);
-+			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1);
-+			/* set for 2ss */
-+			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 0);
-+			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1);
-+		}
-+
-+	} else if (num_enable_path == 3) {
-+		odm_set_bb_reg(dm, R_0x93c, 0xf00000, path);
-+		odm_set_bb_reg(dm, R_0x940, 0xf0, path);
-+		odm_set_bb_reg(dm, R_0x940, 0xf0000, path);
-+
-+		if (path == BB_PATH_ABC) { /* @3-1 */
-+			PHYDM_DBG(dm, DBG_PATH_DIV,
-+				  " Turn on path (( A B C))\n");
-+			/* set for 1ss */
-+			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
-+			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1);
-+			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 2);
-+			/* set for 2ss */
-+			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
-+			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1);
-+			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 2);
-+			/* set for 3ss */
-+			odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0);
-+			odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 1);
-+			odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 2);
-+		} else if (path == BB_PATH_ABD) { /* @3-2 */
-+			PHYDM_DBG(dm, DBG_PATH_DIV,
-+				  " Turn on path (( A B D ))\n");
-+			/* set for 1ss */
-+			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
-+			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1);
-+			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2);
-+			/* set for 2ss */
-+			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
-+			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1);
-+			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2);
-+			/* set for 3ss */
-+			odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0);
-+			odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 1);
-+			odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2);
-+
-+		} else if (path == BB_PATH_ACD) { /* @3-3 */
-+			PHYDM_DBG(dm, DBG_PATH_DIV,
-+				  " Turn on path (( A C D ))\n");
-+			/* set for 1ss */
-+			odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0);
-+			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);
-+			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2);
-+			/* set for 2ss */
-+			odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0);
-+			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);
-+			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2);
-+			/* set for 3ss */
-+			odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0);
-+			odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 1);
-+			odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2);
-+		} else if (path == BB_PATH_BCD) { /* @3-4 */
-+			PHYDM_DBG(dm, DBG_PATH_DIV,
-+				  " Turn on path (( B C D))\n");
-+			/* set for 1ss */
-+			odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0);
-+			odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1);
-+			odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2);
-+			/* set for 2ss */
-+			odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0);
-+			odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1);
-+			odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2);
-+			/* set for 3ss */
-+			odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 0);
-+			odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 1);
-+			odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2);
-+		}
-+	} else if (num_enable_path == 4)
-+		PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path ((A  B C D))\n");
-+}
-+
-+void phydm_find_default_path(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+	u32 rssi_a = 0, rssi_b = 0, rssi_c = 0, rssi_d = 0, rssi_bcd = 0;
-+	u32 rssi_total_a = 0, rssi_total_b = 0;
-+	u32 rssi_total_c = 0, rssi_total_d = 0;
-+
-+	/* @2 Default path Selection By RSSI */
-+
-+	rssi_a = (p_div->path_a_cnt_all > 0) ?
-+		 (p_div->path_a_sum_all / p_div->path_a_cnt_all) : 0;
-+	rssi_b = (p_div->path_b_cnt_all > 0) ?
-+		 (p_div->path_b_sum_all / p_div->path_b_cnt_all) : 0;
-+	rssi_c = (p_div->path_c_cnt_all > 0) ?
-+		 (p_div->path_c_sum_all / p_div->path_c_cnt_all) : 0;
-+	rssi_d = (p_div->path_d_cnt_all > 0) ?
-+		 (p_div->path_d_sum_all / p_div->path_d_cnt_all) : 0;
-+
-+	p_div->path_a_sum_all = 0;
-+	p_div->path_a_cnt_all = 0;
-+	p_div->path_b_sum_all = 0;
-+	p_div->path_b_cnt_all = 0;
-+	p_div->path_c_sum_all = 0;
-+	p_div->path_c_cnt_all = 0;
-+	p_div->path_d_sum_all = 0;
-+	p_div->path_d_cnt_all = 0;
-+
-+	if (p_div->use_path_a_as_default_ant == 1) {
-+		rssi_bcd = (rssi_b + rssi_c + rssi_d) / 3;
-+
-+		if ((rssi_a + ANT_DECT_RSSI_TH) > rssi_bcd) {
-+			p_div->is_path_a_exist = true;
-+			p_div->default_path = PATH_A;
-+		} else {
-+			p_div->is_path_a_exist = false;
-+		}
-+	} else {
-+		if (rssi_a >= rssi_b &&
-+		    rssi_a >= rssi_c &&
-+		    rssi_a >= rssi_d)
-+			p_div->default_path = PATH_A;
-+		else if ((rssi_b >= rssi_c) && (rssi_b >= rssi_d))
-+			p_div->default_path = PATH_B;
-+		else if (rssi_c >= rssi_d)
-+			p_div->default_path = PATH_C;
-+		else
-+			p_div->default_path = PATH_D;
-+	}
-+}
-+
-+void phydm_candidate_dtp_update(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+
-+	p_div->num_candidate = 3;
-+
-+	if (p_div->use_path_a_as_default_ant == 1) {
-+		if (p_div->num_tx_path == 3) {
-+			if (p_div->is_path_a_exist) {
-+				p_div->ant_candidate_1 = BB_PATH_ABC;
-+				p_div->ant_candidate_2 = BB_PATH_ABD;
-+				p_div->ant_candidate_3 = BB_PATH_ACD;
-+			} else { /* use path BCD */
-+				p_div->num_candidate = 1;
-+				phydm_dtp_fix_tx_path(dm, BB_PATH_BCD);
-+				return;
-+			}
-+		} else if (p_div->num_tx_path == 2) {
-+			if (p_div->is_path_a_exist) {
-+				p_div->ant_candidate_1 = BB_PATH_AB;
-+				p_div->ant_candidate_2 = BB_PATH_AC;
-+				p_div->ant_candidate_3 = BB_PATH_AD;
-+			} else {
-+				p_div->ant_candidate_1 = BB_PATH_BC;
-+				p_div->ant_candidate_2 = BB_PATH_BD;
-+				p_div->ant_candidate_3 = BB_PATH_CD;
-+			}
-+		}
-+	} else {
-+		/* @2 3 TX mode */
-+		if (p_div->num_tx_path == 3) { /* @choose 3 ant form 4 */
-+			if (p_div->default_path == PATH_A) {
-+			/* @choose 2 ant form 3 */
-+				p_div->ant_candidate_1 = BB_PATH_ABC;
-+				p_div->ant_candidate_2 = BB_PATH_ABD;
-+				p_div->ant_candidate_3 = BB_PATH_ACD;
-+			} else if (p_div->default_path == PATH_B) {
-+				p_div->ant_candidate_1 = BB_PATH_ABC;
-+				p_div->ant_candidate_2 = BB_PATH_ABD;
-+				p_div->ant_candidate_3 = BB_PATH_BCD;
-+			} else if (p_div->default_path == PATH_C) {
-+				p_div->ant_candidate_1 = BB_PATH_ABC;
-+				p_div->ant_candidate_2 = BB_PATH_ACD;
-+				p_div->ant_candidate_3 = BB_PATH_BCD;
-+			} else if (p_div->default_path == PATH_D) {
-+				p_div->ant_candidate_1 = BB_PATH_ABD;
-+				p_div->ant_candidate_2 = BB_PATH_ACD;
-+				p_div->ant_candidate_3 = BB_PATH_BCD;
-+			}
-+		}
-+
-+		/* @2 2 TX mode */
-+		else if (p_div->num_tx_path == 2) { /* @choose 2 ant form 4 */
-+			if (p_div->default_path == PATH_A) {
-+			/* @choose 2 ant form 3 */
-+				p_div->ant_candidate_1 = BB_PATH_AB;
-+				p_div->ant_candidate_2 = BB_PATH_AC;
-+				p_div->ant_candidate_3 = BB_PATH_AD;
-+			} else if (p_div->default_path == PATH_B) {
-+				p_div->ant_candidate_1 = BB_PATH_AB;
-+				p_div->ant_candidate_2 = BB_PATH_BC;
-+				p_div->ant_candidate_3 = BB_PATH_BD;
-+			} else if (p_div->default_path == PATH_C) {
-+				p_div->ant_candidate_1 = BB_PATH_AC;
-+				p_div->ant_candidate_2 = BB_PATH_BC;
-+				p_div->ant_candidate_3 = BB_PATH_CD;
-+			} else if (p_div->default_path == PATH_D) {
-+				p_div->ant_candidate_1 = BB_PATH_AD;
-+				p_div->ant_candidate_2 = BB_PATH_BD;
-+				p_div->ant_candidate_3 = BB_PATH_CD;
-+			}
-+		}
-+	}
-+}
-+
-+void phydm_dynamic_tx_path(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+
-+	struct sta_info *entry;
-+	u32 i;
-+	u8 num_client = 0;
-+	u8 h2c_parameter[6] = {0};
-+
-+	if (!dm->is_linked) { /* @is_linked==False */
-+		PHYDM_DBG(dm, DBG_PATH_DIV, "DTP_8814 [No Link!!!]\n");
-+
-+		if (p_div->is_become_linked) {
-+			PHYDM_DBG(dm, DBG_PATH_DIV, "[Be disconnected]---->\n");
-+			p_div->is_become_linked = dm->is_linked;
-+		}
-+		return;
-+	} else {
-+		if (!p_div->is_become_linked) {
-+			PHYDM_DBG(dm, DBG_PATH_DIV, " [Be Linked !!!]----->\n");
-+			p_div->is_become_linked = dm->is_linked;
-+		}
-+	}
-+
-+	/* @2 [period CTRL] */
-+	if (p_div->dtp_period >= 2) {
-+		p_div->dtp_period = 0;
-+	} else {
-+		p_div->dtp_period++;
-+		return;
-+	}
-+
-+	/* @2 [Fix path] */
-+	if (dm->path_select != PHYDM_AUTO_PATH)
-+		return;
-+
-+/* @2 [Check Bfer] */
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+	{
-+		enum beamforming_cap beamform_cap = (dm->beamforming_info.beamform_cap);
-+
-+		if (beamform_cap & BEAMFORMER_CAP) { /* @BFmer On  &&   Div On->Div Off */
-+			if (p_div->fix_path_bfer == 0) {
-+				PHYDM_DBG(dm, DBG_PATH_DIV,
-+					  "[ PathDiv : OFF ]   BFmer ==1\n");
-+				p_div->fix_path_bfer = 1;
-+			}
-+			return;
-+		} else { /* @BFmer Off   &&   Div Off->Div On */
-+			if (p_div->fix_path_bfer == 1) {
-+				PHYDM_DBG(dm, DBG_PATH_DIV,
-+					  "[ PathDiv : ON ]   BFmer ==0\n");
-+				p_div->fix_path_bfer = 0;
-+			}
-+		}
-+	}
-+#endif
-+#endif
-+
-+	if (p_div->use_path_a_as_default_ant == 1) {
-+		phydm_find_default_path(dm);
-+		phydm_candidate_dtp_update(dm);
-+	} else {
-+		if (p_div->phydm_dtp_state == PHYDM_DTP_INIT) {
-+			phydm_find_default_path(dm);
-+			phydm_candidate_dtp_update(dm);
-+			p_div->phydm_dtp_state = PHYDM_DTP_RUNNING_1;
-+		}
-+
-+		else if (p_div->phydm_dtp_state == PHYDM_DTP_RUNNING_1) {
-+			p_div->dtp_check_patha_counter++;
-+
-+			if (p_div->dtp_check_patha_counter >=
-+			    NUM_RESET_DTP_PERIOD) {
-+				p_div->dtp_check_patha_counter = 0;
-+				p_div->phydm_dtp_state = PHYDM_DTP_INIT;
-+			}
-+#if 0
-+			/* @2 Search space update */
-+			else {
-+				/* @1.  find the worst candidate */
-+
-+
-+				/* @2. repalce the worst candidate */
-+			}
-+#endif
-+		}
-+	}
-+
-+	/* @2 Dynamic path Selection H2C */
-+
-+	if (p_div->num_candidate == 1) {
-+		return;
-+	} else {
-+		h2c_parameter[0] = p_div->num_candidate;
-+		h2c_parameter[1] = p_div->num_tx_path;
-+		h2c_parameter[2] = p_div->ant_candidate_1;
-+		h2c_parameter[3] = p_div->ant_candidate_2;
-+		h2c_parameter[4] = p_div->ant_candidate_3;
-+
-+		odm_fill_h2c_cmd(dm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, h2c_parameter);
-+	}
-+}
-+
-+void phydm_dynamic_tx_path_init(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+	void *adapter = dm->adapter;
-+	u8 search_space_2[NUM_CHOOSE2_FROM4] = {BB_PATH_AB, BB_PATH_AC, BB_PATH_AD, BB_PATH_BC, BB_PATH_BD, BB_PATH_CD};
-+	u8 search_space_3[NUM_CHOOSE3_FROM4] = {BB_PATH_BCD, BB_PATH_ACD, BB_PATH_ABD, BB_PATH_ABC};
-+
-+#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT)
-+	p_div->is_u3_mode = (*dm->hub_usb_mode == 2) ? 1 : 0;
-+	PHYDM_DBG(dm, DBG_PATH_DIV, "[WIN USB] is_u3_mode = (( %d ))\n",
-+		  p_div->is_u3_mode);
-+#else
-+	p_div->is_u3_mode = 1;
-+#endif
-+	PHYDM_DBG(dm, DBG_PATH_DIV, "Dynamic TX path Init 8814\n");
-+
-+	memcpy(&p_div->search_space_2[0], &search_space_2[0],
-+	       NUM_CHOOSE2_FROM4);
-+	memcpy(&p_div->search_space_3[0], &search_space_3[0],
-+	       NUM_CHOOSE3_FROM4);
-+
-+	p_div->use_path_a_as_default_ant = 1;
-+	p_div->phydm_dtp_state = PHYDM_DTP_INIT;
-+	dm->path_select = PHYDM_AUTO_PATH;
-+	p_div->phydm_path_div_type = PHYDM_4R_PATH_DIV;
-+
-+	if (p_div->is_u3_mode) {
-+		p_div->num_tx_path = 3;
-+		phydm_dtp_fix_tx_path(dm, BB_PATH_BCD); /* @3TX  Set Init TX path*/
-+
-+	} else {
-+		p_div->num_tx_path = 2;
-+		phydm_dtp_fix_tx_path(dm, BB_PATH_BC); /* @2TX // Set Init TX path*/
-+	}
-+}
-+
-+void phydm_process_rssi_for_path_div_8814a(void *dm_void, void *phy_info_void,
-+					   void *pkt_info_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_phyinfo_struct *phy_info = NULL;
-+	struct phydm_perpkt_info_struct *pktinfo = NULL;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+
-+	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
-+	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
-+
-+	if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid))
-+		return;
-+
-+	if (pktinfo->data_rate <= ODM_RATE11M)
-+		return;
-+
-+	if (p_div->phydm_path_div_type == PHYDM_4R_PATH_DIV) {
-+		p_div->path_a_sum_all += phy_info->rx_mimo_signal_strength[0];
-+		p_div->path_a_cnt_all++;
-+
-+		p_div->path_b_sum_all += phy_info->rx_mimo_signal_strength[1];
-+		p_div->path_b_cnt_all++;
-+
-+		p_div->path_c_sum_all += phy_info->rx_mimo_signal_strength[2];
-+		p_div->path_c_cnt_all++;
-+
-+		p_div->path_d_sum_all += phy_info->rx_mimo_signal_strength[3];
-+		p_div->path_d_cnt_all++;
-+	}
-+}
-+
-+void phydm_pathdiv_debug_8814a(void *dm_void, char input[][16], u32 *_used,
-+			       char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 dm_value[10] = {0};
-+	u8 i, input_idx = 0;
-+
-+	for (i = 0; i < 5; i++) {
-+		if (input[i + 1]) {
-+			PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
-+			input_idx++;
-+		}
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	dm->path_select = (u8)(dm_value[0] & 0xf);
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "Path_select = (( 0x%x ))\n", dm->path_select);
-+
-+	/* @2 [Fix path] */
-+	if (dm->path_select != PHYDM_AUTO_PATH) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Turn on path  [%s%s%s%s]\n",
-+			 ((dm->path_select) & 0x1) ? "A" : "",
-+			 ((dm->path_select) & 0x2) ? "B" : "",
-+			 ((dm->path_select) & 0x4) ? "C" : "",
-+			 ((dm->path_select) & 0x8) ? "D" : "");
-+
-+		phydm_dtp_fix_tx_path(dm, dm->path_select);
-+	} else {
-+		PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n",
-+			 "Auto path");
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#endif /* @#if RTL8814A_SUPPORT */
-+
-+#if RTL8812A_SUPPORT
-+void phydm_update_tx_path_8812a(void *dm_void, enum bb_path path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+
-+	if (p_div->default_tx_path != path) {
-+		PHYDM_DBG(dm, DBG_PATH_DIV, "Need to Update Tx path\n");
-+
-+		if (path == BB_PATH_A) {
-+			/*Tx by Reg*/
-+			odm_set_bb_reg(dm, R_0x80c, 0xFFF0, 0x111);
-+			/*Resp Tx by Txinfo*/
-+			odm_set_bb_reg(dm, R_0x6d8, 0xc0, 1);
-+		} else {
-+			/*Tx by Reg*/
-+			odm_set_bb_reg(dm, R_0x80c, 0xFFF0, 0x222);
-+			 /*Resp Tx by Txinfo*/
-+			odm_set_bb_reg(dm, R_0x6d8, 0xc0, 2);
-+		}
-+	}
-+	p_div->default_tx_path = path;
-+
-+	PHYDM_DBG(dm, DBG_PATH_DIV, "path=%s\n",
-+		  (path == BB_PATH_A) ? "A" : "B");
-+}
-+
-+void phydm_path_diversity_init_8812a(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+	u32 i;
-+
-+	odm_set_bb_reg(dm, R_0x80c, BIT(29), 1); /* Tx path from Reg */
-+	odm_set_bb_reg(dm, R_0x80c, 0xFFF0, 0x111); /* Tx by Reg */
-+	odm_set_bb_reg(dm, R_0x6d8, BIT(7) | BIT6, 1); /* Resp Tx by Txinfo */
-+	phydm_set_tx_path_by_bb_reg(dm, RF_PATH_A);
-+
-+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
-+		p_div->path_sel[i] = 1; /* TxInfo default at path-A */
-+}
-+#endif
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+void phydm_set_resp_tx_path_by_fw_jgr3(void *dm_void, u8 macid,
-+				       enum bb_path path, boolean enable)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+	u8 h2c_para[7] = {0};
-+	u8 path_map[4] = {0}; /* tx logic map*/
-+	u8 num_enable_path = 0;
-+	u8 n_tx_path_ctrl_map = 0;
-+	u8 i = 0, n_sts = 0;
-+
-+	/*Response TX is controlled in FW ctrl info*/
-+
-+	PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] =====>\n", __func__);
-+
-+	if (enable) {
-+		n_tx_path_ctrl_map = path;
-+
-+		for (i = 0; i < 4; i++) {
-+			path_map[i] = 0;
-+			if (path & BIT(i))
-+				num_enable_path++;
-+		}
-+
-+		for (i = 0; i < 4; i++) {
-+			if (path & BIT(i)) {
-+				path_map[i] = n_sts;
-+				n_sts++;
-+
-+				if (n_sts == num_enable_path)
-+					break;
-+			}
-+		}
-+	}
-+
-+	PHYDM_DBG(dm, DBG_PATH_DIV, "ctrl_map=0x%x Map[D:A]={%d, %d, %d, %d}\n",
-+		  n_tx_path_ctrl_map,
-+		  path_map[3], path_map[2], path_map[1], path_map[0]);
-+
-+	h2c_para[0] = macid;
-+	h2c_para[1] = n_tx_path_ctrl_map;
-+	h2c_para[2] = (path_map[3] << 6) | (path_map[2] << 4) |
-+		      (path_map[1] << 2) | path_map[0];
-+
-+	odm_fill_h2c_cmd(dm, PHYDM_H2C_DYNAMIC_TX_PATH, 7, h2c_para);
-+}
-+
-+void phydm_get_tx_path_txdesc_jgr3(void *dm_void, u8 macid,
-+				   struct path_txdesc_ctrl *desc)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+	u8 ant_map_a = 0, ant_map_b = 0;
-+	u8 ntx_map = 0;
-+
-+	if (p_div->path_sel[macid] == BB_PATH_A) {
-+		desc->ant_map_a = 0; /*offest24[23:22]*/
-+		desc->ant_map_b = 0; /*offest24[25:24]*/
-+		desc->ntx_map = BB_PATH_A; /*offest28[23:20]*/
-+	} else if (p_div->path_sel[macid] == BB_PATH_B) {
-+		desc->ant_map_a = 0; /*offest24[23:22]*/
-+		desc->ant_map_b = 0; /*offest24[25:24]*/
-+		desc->ntx_map = BB_PATH_B; /*offest28[23:20]*/
-+	} else {
-+		desc->ant_map_a = 0; /*offest24[23:22]*/
-+		desc->ant_map_b = 1; /*offest24[25:24]*/
-+		desc->ntx_map = BB_PATH_AB; /*offest28[23:20]*/
-+	}
-+}
-+#endif
-+
-+void phydm_tx_path_by_mac_or_reg(void *dm_void, enum phydm_path_ctrl ctrl)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+
-+	PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] ctrl=%s\n",
-+		  __func__, (ctrl == TX_PATH_BY_REG) ? "REG" : "DESC");
-+
-+	if (ctrl == p_div->tx_path_ctrl)
-+		return;
-+
-+	p_div->tx_path_ctrl = ctrl;
-+
-+	switch (dm->support_ic_type) {
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	case ODM_RTL8822B:
-+	case ODM_RTL8822C:
-+	case ODM_RTL8812F:
-+	case ODM_RTL8197G:
-+		if (ctrl == TX_PATH_BY_REG) {
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(16), 0); /*OFDM*/
-+			odm_set_bb_reg(dm, R_0x1a84, 0xe0, 0); /*CCK*/
-+		} else {
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(16), 1); /*OFDM*/
-+			odm_set_bb_reg(dm, R_0x1a84, 0xe0, 7); /*CCK*/
-+		}
-+
-+		break;
-+	#endif
-+	#if 0 /*(RTL8822B_SUPPORT)*/ /*@ HW Bug*/
-+	case ODM_RTL8822B:
-+		if (ctrl == TX_PATH_BY_REG) {
-+			odm_set_bb_reg(dm, R_0x93c, BIT(18), 0);
-+			odm_set_bb_reg(dm, R_0xa84, 0xe0, 0); /*CCK*/
-+		} else {
-+			odm_set_bb_reg(dm, R_0x93c, BIT(18), 1);
-+			odm_set_bb_reg(dm, R_0xa84, 0xe0, 7); /*CCK*/
-+		}
-+
-+		break;
-+	#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+void phydm_fix_1ss_tx_path_by_bb_reg(void *dm_void,
-+				     enum bb_path tx_path_sel_1ss,
-+				     enum bb_path tx_path_sel_cck)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+
-+	if (tx_path_sel_1ss != BB_PATH_AUTO) {
-+		p_div->ofdm_fix_path_en = true;
-+		p_div->ofdm_fix_path_sel = tx_path_sel_1ss;
-+	} else {
-+		p_div->ofdm_fix_path_en = false;
-+		p_div->ofdm_fix_path_sel = dm->tx_1ss_status;
-+	}
-+
-+	if (tx_path_sel_cck != BB_PATH_AUTO) {
-+		p_div->cck_fix_path_en = true;
-+		p_div->cck_fix_path_sel = tx_path_sel_cck;
-+	} else {
-+		p_div->cck_fix_path_en = false;
-+		p_div->cck_fix_path_sel = dm->tx_1ss_status;
-+	}
-+
-+	p_div->force_update = true;
-+
-+	PHYDM_DBG(dm, DBG_PATH_DIV,
-+		  "{OFDM_fix_en=%d, path=%d} {CCK_fix_en=%d, path=%d}\n",
-+		  p_div->ofdm_fix_path_en, p_div->ofdm_fix_path_sel,
-+		  p_div->cck_fix_path_en, p_div->cck_fix_path_sel);
-+}
-+
-+void phydm_set_tx_path_by_bb_reg(void *dm_void, enum bb_path tx_path_sel_1ss)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+	enum bb_path tx_path_sel_cck = tx_path_sel_1ss;
-+
-+	if (!p_div->force_update) {
-+		if (tx_path_sel_1ss == p_div->default_tx_path) {
-+			PHYDM_DBG(dm, DBG_PATH_DIV, "Stay in TX path=%s\n",
-+				  (tx_path_sel_1ss == BB_PATH_A) ? "A" : "B");
-+			return;
-+		}
-+	}
-+	p_div->force_update = false;
-+
-+	p_div->default_tx_path = tx_path_sel_1ss;
-+
-+	PHYDM_DBG(dm, DBG_PATH_DIV, "Switch TX path=%s\n",
-+		  (tx_path_sel_1ss == BB_PATH_A) ? "A" : "B");
-+
-+	/*Adv-ctrl mode*/
-+	if (p_div->cck_fix_path_en) {
-+		PHYDM_DBG(dm, DBG_PATH_DIV, "Fix CCK TX path=%d\n",
-+			  p_div->cck_fix_path_sel);
-+		tx_path_sel_cck = p_div->cck_fix_path_sel;
-+	}
-+
-+	if (p_div->ofdm_fix_path_en) {
-+		PHYDM_DBG(dm, DBG_PATH_DIV, "Fix OFDM TX path=%d\n",
-+			  p_div->ofdm_fix_path_sel);
-+		tx_path_sel_1ss = p_div->ofdm_fix_path_sel;
-+	}
-+
-+	switch (dm->support_ic_type) {
-+	#if RTL8822C_SUPPORT
-+	case ODM_RTL8822C:
-+		phydm_config_tx_path_8822c(dm, dm->tx_2ss_status,
-+					   tx_path_sel_1ss, tx_path_sel_cck);
-+		break;
-+	#endif
-+
-+	#if RTL8822B_SUPPORT
-+	case ODM_RTL8822B:
-+		if (dm->tx_ant_status != BB_PATH_AB)
-+			return;
-+
-+		phydm_config_tx_path_8822b(dm, BB_PATH_AB,
-+					   tx_path_sel_1ss, tx_path_sel_cck);
-+		break;
-+	#endif
-+
-+	#if RTL8192F_SUPPORT
-+	case ODM_RTL8192F:
-+		if (dm->tx_ant_status != BB_PATH_AB)
-+			return;
-+
-+		phydm_config_tx_path_8192f(dm, BB_PATH_AB,
-+					   tx_path_sel_1ss, tx_path_sel_cck);
-+		break;
-+	#endif
-+
-+	#if RTL8812A_SUPPORT
-+	case ODM_RTL8812:
-+		phydm_update_tx_path_8812a(dm, tx_path_sel_1ss);
-+		break;
-+	#endif
-+	default:
-+		break;
-+	}
-+}
-+
-+void phydm_tx_path_diversity_2ss(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+	struct cmn_sta_info *sta;
-+	enum bb_path default_tx_path = BB_PATH_A, path = BB_PATH_A;
-+	u32 rssi_a = 0, rssi_b = 0;
-+	u32 local_max_rssi, glb_min_rssi = 0xff;
-+	u8 i = 0;
-+
-+	PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] =======>\n", __func__);
-+
-+	if (!dm->is_linked) {
-+		if (dm->first_disconnect)
-+			phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG);
-+
-+		PHYDM_DBG(dm, DBG_PATH_DIV, "No Link\n");
-+		return;
-+	}
-+
-+	#if 0/*def PHYDM_IC_JGR3_SERIES_SUPPORT*/
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		if (dm->is_one_entry_only || p_div->cck_fix_path_en ||
-+		    p_div->ofdm_fix_path_en)
-+			phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG);
-+		else
-+			phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_DESC);
-+	}
-+	#endif
-+
-+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
-+		sta = dm->phydm_sta_info[i];
-+		if (!is_sta_active(sta))
-+			continue;
-+
-+		/* 2 Caculate RSSI per path */
-+		rssi_a = PHYDM_DIV(p_div->path_a_sum[i], p_div->path_a_cnt[i]);
-+		rssi_b = PHYDM_DIV(p_div->path_b_sum[i], p_div->path_b_cnt[i]);
-+
-+		if (rssi_a == rssi_b)
-+			path =  p_div->default_tx_path;
-+		else
-+			path = (rssi_a > rssi_b) ? BB_PATH_A : BB_PATH_B;
-+
-+		local_max_rssi = (rssi_a > rssi_b) ? rssi_a : rssi_b;
-+
-+		PHYDM_DBG(dm, DBG_PATH_DIV,
-+			  "[%d]PathA sum=%d, cnt=%d, avg_rssi=%d\n",
-+			  i, p_div->path_a_sum[i],
-+			  p_div->path_a_cnt[i], rssi_a);
-+		PHYDM_DBG(dm, DBG_PATH_DIV,
-+			  "[%d]PathB sum=%d, cnt=%d, avg_rssi=%d\n",
-+			  i, p_div->path_b_sum[i],
-+			  p_div->path_b_cnt[i], rssi_b);
-+
-+		/*Select default Tx path */
-+		if (local_max_rssi < glb_min_rssi) {
-+			glb_min_rssi = local_max_rssi;
-+			default_tx_path = path;
-+		}
-+
-+		if (p_div->path_sel[i] != path) {
-+			p_div->path_sel[i] = path;
-+			#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+			if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+				phydm_set_resp_tx_path_by_fw_jgr3(dm, i,
-+								  path, true);
-+			#endif
-+		}
-+
-+		p_div->path_a_cnt[i] = 0;
-+		p_div->path_a_sum[i] = 0;
-+		p_div->path_b_cnt[i] = 0;
-+		p_div->path_b_sum[i] = 0;
-+	}
-+
-+	/* 2 Update default Tx path */
-+	phydm_set_tx_path_by_bb_reg(dm, default_tx_path);
-+	PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] end\n\n", __func__);
-+}
-+
-+void phydm_tx_path_diversity(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+
-+	p_div->path_div_in_progress = false;
-+
-+	if (!(dm->support_ability & ODM_BB_PATH_DIV))
-+		return;
-+
-+	if (p_div->stop_path_div) {
-+		PHYDM_DBG(dm, DBG_PATH_DIV,
-+			  "stop_path_div=1, tx_1ss_status=%d\n",
-+			  dm->tx_1ss_status);
-+		return;
-+	}
-+
-+	switch (dm->support_ic_type) {
-+	#ifdef PHYDM_CONFIG_PATH_DIV_V2
-+	case ODM_RTL8822B:
-+	case ODM_RTL8822C:
-+	case ODM_RTL8192F:
-+	case ODM_RTL8812F:
-+	case ODM_RTL8197G:
-+		if (dm->rx_ant_status != BB_PATH_AB) {
-+			PHYDM_DBG(dm, DBG_PATH_DIV,
-+				  "[Return] tx_Path_en=%d, rx_Path_en=%d\n",
-+				  dm->tx_ant_status, dm->rx_ant_status);
-+			return;
-+		}
-+
-+		p_div->path_div_in_progress = true;
-+		phydm_tx_path_diversity_2ss(dm);
-+		break;
-+	#endif
-+
-+	#if (RTL8812A_SUPPORT)
-+	case ODM_RTL8812:
-+		phydm_tx_path_diversity_2ss(dm);
-+		break;
-+	#endif
-+
-+	#if RTL8814A_SUPPORT
-+	case ODM_RTL8814A:
-+		phydm_dynamic_tx_path(dm);
-+		break;
-+	#endif
-+	}
-+}
-+
-+void phydm_tx_path_diversity_init_v2(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+	u32 i = 0;
-+
-+	PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] ====>\n", __func__);
-+
-+	/*BB_PATH_AB is a invalid value used for init state*/
-+	p_div->default_tx_path = BB_PATH_A;
-+	p_div->tx_path_ctrl = TX_PATH_CTRL_INIT;
-+	p_div->path_div_in_progress = false;
-+
-+	p_div->cck_fix_path_en = false;
-+	p_div->ofdm_fix_path_en = false;
-+	p_div->force_update = false;
-+
-+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
-+		p_div->path_sel[i] = BB_PATH_A; /* TxInfo default at path-A */
-+
-+	phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG);
-+}
-+
-+void phydm_tx_path_diversity_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ability & ODM_BB_PATH_DIV))
-+		return;
-+
-+	switch (dm->support_ic_type) {
-+	#ifdef PHYDM_CONFIG_PATH_DIV_V2
-+	case ODM_RTL8822C:
-+	case ODM_RTL8822B:
-+	case ODM_RTL8192F:
-+	case ODM_RTL8812F:
-+	case ODM_RTL8197G:
-+	phydm_tx_path_diversity_init_v2(dm); /*@ After 8822B*/
-+	break;
-+	#endif
-+
-+	#if RTL8812A_SUPPORT
-+	case ODM_RTL8812:
-+	phydm_path_diversity_init_8812a(dm);
-+	break;
-+	#endif
-+
-+	#if RTL8814A_SUPPORT
-+	case ODM_RTL8814A:
-+	phydm_dynamic_tx_path_init(dm);
-+	break;
-+	#endif
-+	}
-+}
-+
-+void phydm_process_rssi_for_path_div(void *dm_void, void *phy_info_void,
-+				     void *pkt_info_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_phyinfo_struct *phy_info = NULL;
-+	struct phydm_perpkt_info_struct *pktinfo = NULL;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+	u8 id = 0;
-+
-+	phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
-+	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
-+
-+	if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid))
-+		return;
-+
-+	if (pktinfo->is_cck_rate)
-+		return;
-+
-+	id = pktinfo->station_id;
-+	p_div->path_a_sum[id] += phy_info->rx_mimo_signal_strength[0];
-+	p_div->path_a_cnt[id]++;
-+
-+	p_div->path_b_sum[id] += phy_info->rx_mimo_signal_strength[1];
-+	p_div->path_b_cnt[id]++;
-+}
-+
-+void phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used,
-+			 char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+	char help[] = "-h";
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 val[10] = {0};
-+	u8 i, input_idx = 0;
-+
-+	for (i = 0; i < 5; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]);
-+		input_idx++;
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	PHYDM_SSCANF(input[1], DCMD_HEX, &val[0]);
-+	PHYDM_SSCANF(input[2], DCMD_HEX, &val[1]);
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{1:TX Ctrl Sig} {0:BB, 1:MAC}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{2:BB Default TX REG} {path}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{3:MAC DESC TX} {path} {macid}\n");
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{4:MAC Resp TX} {path} {macid}\n");
-+		#endif
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{5:Fix 1ss path} {ofdm path} {cck path}\n");
-+	} else if (val[0] == 1) {
-+		phydm_tx_path_by_mac_or_reg(dm, (enum phydm_path_ctrl)val[1]);
-+	} else if (val[0] == 2) {
-+		phydm_set_tx_path_by_bb_reg(dm, (enum bb_path)val[1]);
-+	} else if (val[0] == 3) {
-+		p_div->path_sel[val[2]] = (enum bb_path)val[1];
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	} else if (val[0] == 4) {
-+		phydm_set_resp_tx_path_by_fw_jgr3(dm, (u8)val[2],
-+						  (enum bb_path)val[1], true);
-+	#endif
-+	} else if (val[0] == 5) {
-+		phydm_fix_1ss_tx_path_by_bb_reg(dm, (enum bb_path)val[1],
-+						(enum bb_path)val[2]);
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div;
-+
-+	u8 macid = cmd_buf[0];
-+	u8 target = cmd_buf[1];
-+	u8 nsc_1 = cmd_buf[2];
-+	u8 nsc_2 = cmd_buf[3];
-+	u8 nsc_3 = cmd_buf[4];
-+
-+	PHYDM_DBG(dm, DBG_PATH_DIV, "Target_candidate = (( %d ))\n", target);
-+/*@
-+	if( (nsc_1 >= nsc_2) &&  (nsc_1 >= nsc_3))
-+	{
-+		phydm_dtp_fix_tx_path(dm, p_div->ant_candidate_1);
-+	}
-+	else	if( nsc_2 >= nsc_3)
-+	{
-+		phydm_dtp_fix_tx_path(dm, p_div->ant_candidate_2);
-+	}
-+	else
-+	{
-+		phydm_dtp_fix_tx_path(dm, p_div->ant_candidate_3);
-+	}
-+	*/
-+}
-+
-+#endif /*  @#ifdef CONFIG_PATH_DIVERSITY */
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_pathdiv.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_pathdiv.h
-new file mode 100644
-index 000000000000..ee3438252f64
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_pathdiv.h
-@@ -0,0 +1,145 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDMPATHDIV_H__
-+#define __PHYDMPATHDIV_H__
-+
-+#ifdef CONFIG_PATH_DIVERSITY
-+/* @2019.03.07 open resp tx path h2c only for 1ss status*/
-+#define PATHDIV_VERSION "4.4"
-+
-+#if (RTL8192F_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\
-+	RTL8812F_SUPPORT || RTL8197G_SUPPORT)
-+	#define PHYDM_CONFIG_PATH_DIV_V2
-+#endif
-+
-+#define USE_PATH_A_AS_DEFAULT_ANT /* @for 8814 dynamic TX path selection */
-+
-+#define NUM_RESET_DTP_PERIOD 5
-+#define ANT_DECT_RSSI_TH 3
-+
-+#define PATH_A 1
-+#define PATH_B 2
-+#define PATH_C 3
-+#define PATH_D 4
-+
-+#define PHYDM_AUTO_PATH 0
-+#define PHYDM_FIX_PATH 1
-+
-+#define NUM_CHOOSE2_FROM4 6
-+#define NUM_CHOOSE3_FROM4 4
-+
-+enum phydm_dtp_state {
-+	PHYDM_DTP_INIT = 1,
-+	PHYDM_DTP_RUNNING_1
-+};
-+
-+enum phydm_path_div_type {
-+	PHYDM_2R_PATH_DIV = 1,
-+	PHYDM_4R_PATH_DIV = 2
-+};
-+
-+enum phydm_path_ctrl {
-+	TX_PATH_BY_REG = 0,
-+	TX_PATH_BY_DESC = 1,
-+	TX_PATH_CTRL_INIT
-+};
-+
-+struct path_txdesc_ctrl {
-+	u8 ant_map_a : 2;
-+	u8 ant_map_b : 2;
-+	u8 ntx_map : 4;
-+};
-+
-+struct _ODM_PATH_DIVERSITY_ {
-+	boolean stop_path_div; /*@Limit by enabled path number*/
-+	boolean path_div_in_progress;
-+	boolean	cck_fix_path_en; /*@ BB Reg for Adv-Ctrl (or debug mode)*/
-+	boolean	ofdm_fix_path_en; /*@ BB Reg for Adv-Ctrl (or debug mode)*/
-+	enum bb_path cck_fix_path_sel; /*@ BB Reg for Adv-Ctrl (or debug mode)*/
-+	enum bb_path ofdm_fix_path_sel;/*@ BB Reg for Adv-Ctrl (or debug mode)*/
-+	enum phydm_path_ctrl tx_path_ctrl;
-+	enum bb_path default_tx_path;
-+	enum bb_path path_sel[ODM_ASSOCIATE_ENTRY_NUM];
-+	u32	path_a_sum[ODM_ASSOCIATE_ENTRY_NUM];
-+	u32	path_b_sum[ODM_ASSOCIATE_ENTRY_NUM];
-+	u16	path_a_cnt[ODM_ASSOCIATE_ENTRY_NUM];
-+	u16	path_b_cnt[ODM_ASSOCIATE_ENTRY_NUM];
-+	u8	phydm_path_div_type;
-+	boolean force_update;
-+#if RTL8814A_SUPPORT
-+
-+	u32	path_a_sum_all;
-+	u32	path_b_sum_all;
-+	u32	path_c_sum_all;
-+	u32	path_d_sum_all;
-+
-+	u32	path_a_cnt_all;
-+	u32	path_b_cnt_all;
-+	u32	path_c_cnt_all;
-+	u32	path_d_cnt_all;
-+
-+	u8	dtp_period;
-+	boolean	is_become_linked;
-+	boolean	is_u3_mode;
-+	u8	num_tx_path;
-+	u8	default_path;
-+	u8	num_candidate;
-+	u8	ant_candidate_1;
-+	u8	ant_candidate_2;
-+	u8	ant_candidate_3;
-+	u8     phydm_dtp_state;
-+	u8	dtp_check_patha_counter;
-+	boolean	fix_path_bfer;
-+	u8	search_space_2[NUM_CHOOSE2_FROM4];
-+	u8	search_space_3[NUM_CHOOSE3_FROM4];
-+
-+	u8	pre_tx_path;
-+	u8	use_path_a_as_default_ant;
-+	boolean	is_path_a_exist;
-+
-+#endif
-+};
-+
-+void phydm_set_tx_path_by_bb_reg(void *dm_void, enum bb_path tx_path_sel_1ss);
-+
-+void phydm_get_tx_path_txdesc_jgr3(void *dm_void, u8 macid,
-+				   struct path_txdesc_ctrl *desc);
-+
-+void phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
-+
-+void phydm_tx_path_diversity_init(void *dm_void);
-+
-+void phydm_tx_path_diversity(void *dm_void);
-+
-+void phydm_process_rssi_for_path_div(void *dm_void, void *phy_info_void,
-+				     void *pkt_info_void);
-+
-+void phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used,
-+			 char *output, u32 *_out_len);
-+
-+#endif /* @#ifdef CONFIG_PATH_DIVERSITY */
-+#endif /* @#ifndef  __PHYDMPATHDIV_H__ */
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_phystatus.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_phystatus.c
-new file mode 100644
-index 000000000000..7d7ecd7c6a83
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_phystatus.c
-@@ -0,0 +1,3245 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef PHYDM_COMPILE_MU
-+u8 phydm_get_gid(struct dm_struct *dm, u8 *phy_status_inf)
-+{
-+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
-+	struct phy_sts_rpt_jgr2_type1 *rpt_jgr2 = NULL;
-+#endif
-+#ifdef PHYSTS_3RD_TYPE_SUPPORT
-+	struct phy_sts_rpt_jgr3_type1 *rpt_jgr3 = NULL;
-+#endif
-+	u8 gid = 0;
-+
-+	if (dm->ic_phy_sts_type == PHYDM_PHYSTS_TYPE_1)
-+		return 0;
-+
-+	if ((*phy_status_inf & 0xf) != 1)
-+		return 0;
-+
-+	switch (dm->ic_phy_sts_type) {
-+	#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
-+	case PHYDM_PHYSTS_TYPE_2:
-+		rpt_jgr2 = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;
-+		gid = rpt_jgr2->gid;
-+		break;
-+	#endif
-+	#ifdef PHYSTS_3RD_TYPE_SUPPORT
-+	case PHYDM_PHYSTS_TYPE_3:
-+		rpt_jgr3 = (struct phy_sts_rpt_jgr3_type1 *)phy_status_inf;
-+		gid = rpt_jgr3->gid;
-+		break;
-+	#endif
-+	default:
-+		break;
-+	}
-+
-+	return gid;
-+}
-+#endif
-+
-+void phydm_rx_statistic_cal(struct dm_struct *dm,
-+			    struct phydm_phyinfo_struct *phy_info,
-+			    u8 *phy_status_inf,
-+			    struct phydm_perpkt_info_struct *pktinfo)
-+{
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	struct phydm_bf_rate_info_jgr3 *bfrateinfo = &dm->bf_rate_info_jgr3;
-+#endif
-+
-+	u8 rate = (pktinfo->data_rate & 0x7f);
-+	u8 bw_idx = phy_info->band_width;
-+	u8 offset = 0;
-+	u8 gid = 0;
-+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))
-+	u8 val = 0;
-+#endif
-+	#ifdef PHYDM_COMPILE_MU
-+	u8 is_mu_pkt = 0;
-+	#endif
-+
-+	if (rate <= ODM_RATE54M) {
-+		dbg_i->num_qry_legacy_pkt[rate]++;
-+	} else if (rate <= ODM_RATEMCS31) {
-+		dbg_i->ht_pkt_not_zero = true;
-+		offset = rate - ODM_RATEMCS0;
-+
-+		if (offset > (HT_RATE_NUM - 1))
-+			offset = HT_RATE_NUM - 1;
-+
-+		if (dm->support_ic_type &
-+		    (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC)) {
-+			if (bw_idx == *dm->band_width) {
-+				dbg_i->num_qry_ht_pkt[offset]++;
-+
-+			} else if (bw_idx == CHANNEL_WIDTH_20) {
-+				dbg_i->num_qry_pkt_sc_20m[offset]++;
-+				dbg_i->low_bw_20_occur = true;
-+			}
-+		} else {
-+			dbg_i->num_qry_ht_pkt[offset]++;
-+		}
-+	}
-+#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT))
-+	else if (rate <= ODM_RATEVHTSS4MCS9) {
-+		offset = rate - ODM_RATEVHTSS1MCS0;
-+
-+		if (offset > (VHT_RATE_NUM - 1))
-+			offset = VHT_RATE_NUM - 1;
-+
-+		#ifdef PHYDM_COMPILE_MU
-+		gid = phydm_get_gid(dm, phy_status_inf);
-+
-+		if (gid != 0 && gid != 63)
-+			is_mu_pkt = true;
-+
-+		if (is_mu_pkt) {
-+		#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT ||\
-+		     (defined(PHYSTS_3RD_TYPE_SUPPORT)))
-+			dbg_i->num_mu_vht_pkt[offset]++;
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+			bfrateinfo->num_mu_vht_pkt[offset]++;
-+		#endif
-+		#else
-+			dbg_i->num_qry_vht_pkt[offset]++; /*@for debug*/
-+		#endif
-+		} else
-+		#endif
-+		{
-+			dbg_i->vht_pkt_not_zero = true;
-+
-+			if (dm->support_ic_type &
-+			    (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC)) {
-+				if (bw_idx == *dm->band_width) {
-+					dbg_i->num_qry_vht_pkt[offset]++;
-+				#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+					bfrateinfo->num_qry_vht_pkt[offset]++;
-+				#endif
-+
-+				} else if (bw_idx == CHANNEL_WIDTH_20) {
-+					dbg_i->num_qry_pkt_sc_20m[offset]++;
-+					dbg_i->low_bw_20_occur = true;
-+				} else {/*@if (bw_idx == CHANNEL_WIDTH_40)*/
-+					dbg_i->num_qry_pkt_sc_40m[offset]++;
-+					dbg_i->low_bw_40_occur = true;
-+				}
-+			} else {
-+				dbg_i->num_qry_vht_pkt[offset]++;
-+			}
-+		}
-+
-+		#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT ||\
-+		     (defined(PHYSTS_3RD_TYPE_SUPPORT)))
-+		if (pktinfo->ppdu_cnt < 4) {
-+			val = rate;
-+
-+			#ifdef PHYDM_COMPILE_MU
-+			if (is_mu_pkt)
-+				val |= BIT(7);
-+			#endif
-+
-+			dbg_i->num_of_ppdu[pktinfo->ppdu_cnt] = val;
-+			dbg_i->gid_num[pktinfo->ppdu_cnt] = gid;
-+		}
-+		#endif
-+	}
-+#endif
-+}
-+
-+void phydm_reset_phystatus_avg(struct dm_struct *dm)
-+{
-+	struct phydm_phystatus_avg *dbg_avg = NULL;
-+
-+	dbg_avg = &dm->phy_dbg_info.phystatus_statistic_avg;
-+	odm_memory_set(dm, &dbg_avg->rssi_cck_avg, 0,
-+		       sizeof(struct phydm_phystatus_avg));
-+}
-+
-+void phydm_reset_phystatus_statistic(struct dm_struct *dm)
-+{
-+	struct phydm_phystatus_statistic *dbg_s = NULL;
-+
-+	dbg_s = &dm->phy_dbg_info.physts_statistic_info;
-+
-+	odm_memory_set(dm, &dbg_s->rssi_cck_sum, 0,
-+		       sizeof(struct phydm_phystatus_statistic));
-+}
-+
-+void phydm_reset_phy_info(struct dm_struct *dm,
-+			  struct phydm_phyinfo_struct *phy_info)
-+{
-+	u8 i = 0;
-+
-+	odm_memory_set(dm, &phy_info->physts_rpt_valid, 0,
-+		       sizeof(struct phydm_phyinfo_struct));
-+
-+	phy_info->rx_power = -110;
-+	phy_info->recv_signal_power = -110;
-+
-+	for (i = 0; i < dm->num_rf_path; i++)
-+		phy_info->rx_pwr[i] = -110;
-+}
-+
-+void phydm_avg_rssi_evm_snr(void *dm_void,
-+			    struct phydm_phyinfo_struct *phy_info,
-+			    struct phydm_perpkt_info_struct *pktinfo)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
-+	u8 *rssi = phy_info->rx_mimo_signal_strength;
-+	u8 *evm = phy_info->rx_mimo_evm_dbm;
-+	s8 *snr = phy_info->rx_snr;
-+	u32 size = PHYSTS_PATH_NUM; /*size of path=4*/
-+	u16 size_th = PHY_HIST_SIZE - 1; /*size of threshold*/
-+	u16 val = 0, intvl = 0;
-+	u8 i = 0;
-+
-+	if (pktinfo->is_packet_beacon) {
-+		for (i = 0; i < dm->num_rf_path; i++)
-+			dbg_s->rssi_beacon_sum[i] += rssi[i];
-+
-+		dbg_s->rssi_beacon_cnt++;
-+	}
-+
-+	if (pktinfo->data_rate <= ODM_RATE11M) {
-+		/*RSSI*/
-+		dbg_s->rssi_cck_sum += rssi[0];
-+		#if (defined(PHYSTS_3RD_TYPE_SUPPORT) && defined(PHYDM_COMPILE_ABOVE_2SS))
-+		if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {
-+			for (i = 1; i < dm->num_rf_path; i++)
-+				dbg_s->rssi_cck_sum_abv_2ss[i - 1] += rssi[i];
-+		}
-+		#endif
-+		dbg_s->rssi_cck_cnt++;
-+	} else if (pktinfo->data_rate <= ODM_RATE54M) {
-+		for (i = 0; i < dm->num_rf_path; i++) {
-+			/*SNR & RSSI*/
-+			dbg_s->snr_ofdm_sum[i] += snr[i];
-+			dbg_s->rssi_ofdm_sum[i] += rssi[i];
-+		}
-+		/*@evm*/
-+		dbg_s->evm_ofdm_sum += evm[0];
-+		dbg_s->rssi_ofdm_cnt++;
-+
-+		val = (u16)evm[0];
-+		intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th);
-+		dbg_s->evm_ofdm_hist[intvl]++;
-+
-+		val = (u16)snr[0];
-+		intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th);
-+		dbg_s->snr_ofdm_hist[intvl]++;
-+
-+	} else if (pktinfo->rate_ss == 1) {
-+/*@===[1-SS]==================================================================*/
-+		for (i = 0; i < dm->num_rf_path; i++) {
-+			/*SNR & RSSI*/
-+			dbg_s->snr_1ss_sum[i] += snr[i];
-+			dbg_s->rssi_1ss_sum[i] += rssi[i];
-+		}
-+
-+		/*@evm*/
-+		dbg_s->evm_1ss_sum += evm[0];
-+		/*@EVM Histogram*/
-+		val = (u16)evm[0];
-+		intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th);
-+		dbg_s->evm_1ss_hist[intvl]++;
-+
-+		/*SNR Histogram*/
-+		val = (u16)snr[0];
-+		intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th);
-+		dbg_s->snr_1ss_hist[intvl]++;
-+
-+		dbg_s->rssi_1ss_cnt++;
-+	} else if (pktinfo->rate_ss == 2) {
-+/*@===[2-SS]==================================================================*/
-+		#if (defined(PHYDM_COMPILE_ABOVE_2SS))
-+		for (i = 0; i < dm->num_rf_path; i++) {
-+			/*SNR & RSSI*/
-+			dbg_s->snr_2ss_sum[i] += snr[i];
-+			dbg_s->rssi_2ss_sum[i] += rssi[i];
-+		}
-+
-+		for (i = 0; i < pktinfo->rate_ss; i++) {
-+			/*@evm*/
-+			dbg_s->evm_2ss_sum[i] += evm[i];
-+			/*@EVM Histogram*/
-+			val = (u16)evm[i];
-+			intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
-+						  size_th);
-+			dbg_s->evm_2ss_hist[i][intvl]++;
-+
-+			/*SNR Histogram*/
-+			val = (u16)snr[i];
-+			intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
-+						  size_th);
-+			dbg_s->snr_2ss_hist[i][intvl]++;
-+		}
-+		dbg_s->rssi_2ss_cnt++;
-+		#endif
-+	} else if (pktinfo->rate_ss == 3) {
-+/*@===[3-SS]==================================================================*/
-+		#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+		for (i = 0; i < dm->num_rf_path; i++) {
-+			/*SNR & RSSI*/
-+			dbg_s->snr_3ss_sum[i] += snr[i];
-+			dbg_s->rssi_3ss_sum[i] += rssi[i];
-+		}
-+
-+		for (i = 0; i < pktinfo->rate_ss; i++) {
-+			/*@evm*/
-+			dbg_s->evm_3ss_sum[i] += evm[i];
-+			/*@EVM Histogram*/
-+			val = (u16)evm[i];
-+			intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
-+						  size_th);
-+			dbg_s->evm_3ss_hist[i][intvl]++;
-+
-+			/*SNR Histogram*/
-+			val = (u16)snr[i];
-+			intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
-+						  size_th);
-+			dbg_s->snr_3ss_hist[i][intvl]++;
-+		}
-+		dbg_s->rssi_3ss_cnt++;
-+		#endif
-+	} else if (pktinfo->rate_ss == 4) {
-+/*@===[4-SS]==================================================================*/
-+		#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+		for (i = 0; i < dm->num_rf_path; i++) {
-+			/*SNR & RSSI*/
-+			dbg_s->snr_4ss_sum[i] += snr[i];
-+			dbg_s->rssi_4ss_sum[i] += rssi[i];
-+		}
-+
-+		for (i = 0; i < pktinfo->rate_ss; i++) {
-+			/*@evm*/
-+			dbg_s->evm_4ss_sum[i] += evm[i];
-+
-+			/*@EVM Histogram*/
-+			val = (u16)evm[i];
-+			intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th,
-+						  size_th);
-+			dbg_s->evm_4ss_hist[i][intvl]++;
-+
-+			/*SNR Histogram*/
-+			val = (u16)snr[i];
-+			intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th,
-+						  size_th);
-+			dbg_s->snr_4ss_hist[i][intvl]++;
-+		}
-+		dbg_s->rssi_4ss_cnt++;
-+		#endif
-+	}
-+}
-+
-+void phydm_avg_phystatus_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	u16 snr_hist_th[PHY_HIST_TH_SIZE] = {5, 8, 11, 14, 17, 20, 23, 26,
-+					      29, 32, 35};
-+	u16 evm_hist_th[PHY_HIST_TH_SIZE] = {5, 8, 11, 14, 17, 20, 23, 26,
-+					      29, 32, 35};
-+	#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
-+	u16 cn_hist_th[PHY_HIST_TH_SIZE] = {2, 3, 4, 5, 6, 8, 10,
-+					    12, 14, 16, 18};
-+	#endif
-+	u32 size = PHY_HIST_TH_SIZE * 2;
-+	u8 i = 0;
-+
-+	odm_move_memory(dm, dbg_i->snr_hist_th, snr_hist_th, size);
-+	odm_move_memory(dm, dbg_i->evm_hist_th, evm_hist_th, size);
-+	#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
-+	dm->pkt_proc_struct.physts_auto_swch_en = false;
-+	for (i = 0; i < PHY_HIST_TH_SIZE; i++)
-+		dbg_i->cn_hist_th[i] = cn_hist_th[i] << 1;
-+	#endif
-+}
-+
-+u8 phydm_get_signal_quality(struct phydm_phyinfo_struct *phy_info,
-+			    struct dm_struct *dm,
-+			    struct phy_status_rpt_8192cd *phy_sts)
-+{
-+	u8 sq_rpt;
-+	u8 result = 0;
-+
-+	if (phy_info->rx_pwdb_all > 40 && !dm->is_in_hct_test) {
-+		result = 100;
-+	} else {
-+		sq_rpt = phy_sts->cck_sig_qual_ofdm_pwdb_all;
-+
-+		if (sq_rpt > 64)
-+			result = 0;
-+		else if (sq_rpt < 20)
-+			result = 100;
-+		else
-+			result = ((64 - sq_rpt) * 100) / 44;
-+	}
-+
-+	return result;
-+}
-+
-+u8 phydm_pw_2_percent(s8 ant_power)
-+{
-+	if ((ant_power <= -100) || ant_power >= 20)
-+		return 0;
-+	else if (ant_power >= 0)
-+		return 100;
-+	else
-+		return 100 + ant_power;
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+void phydm_process_signal_strength(struct dm_struct *dm,
-+				   struct phydm_phyinfo_struct *phy_info,
-+				   struct phydm_perpkt_info_struct *pktinfo)
-+{
-+	boolean is_cck_rate = 0;
-+	u8 avg_rssi = 0, tmp_rssi = 0, best_rssi = 0, second_rssi = 0;
-+	u8 ss = 0; /*signal strenth after scale mapping*/
-+	u8 pwdb = phy_info->rx_pwdb_all;
-+	u8 i;
-+
-+	is_cck_rate = (pktinfo->data_rate <= ODM_RATE11M) ? true : false;
-+
-+	/*use the best two RSSI only*/
-+	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
-+		tmp_rssi = phy_info->rx_mimo_signal_strength[i];
-+
-+		/*@Get the best two RSSI*/
-+		if (tmp_rssi > best_rssi && tmp_rssi > second_rssi) {
-+			second_rssi = best_rssi;
-+			best_rssi = tmp_rssi;
-+		} else if (tmp_rssi > second_rssi && tmp_rssi <= best_rssi) {
-+			second_rssi = tmp_rssi;
-+		}
-+	}
-+
-+	if (best_rssi == 0)
-+		return;
-+
-+	if (pktinfo->rate_ss == 1)
-+		avg_rssi = best_rssi;
-+	else
-+		avg_rssi = (best_rssi + second_rssi) >> 1;
-+
-+	/* Update signal strength to UI,
-+	 * and phy_info->rx_pwdb_all is the maximum RSSI of all path
-+	 */
-+	if (dm->support_ic_type & (PHYSTS_3RD_TYPE_IC | PHYSTS_2ND_TYPE_IC))
-+		ss = SignalScaleProc(dm->adapter, pwdb, false, false);
-+	else
-+		ss = SignalScaleProc(dm->adapter, pwdb, true, is_cck_rate);
-+
-+	phy_info->signal_strength = ss;
-+}
-+
-+static u8 phydm_sq_patch_lenovo(
-+	struct dm_struct *dm,
-+	u8 is_cck_rate,
-+	u8 pwdb_all,
-+	u8 path,
-+	u8 RSSI)
-+{
-+	u8 sq = 0;
-+
-+	if (is_cck_rate) {
-+		if (dm->support_ic_type & ODM_RTL8192E) {
-+/*@
-+ * <Roger_Notes>
-+ * Expected signal strength and bars indication at Lenovo lab. 2013.04.11
-+ * 802.11n, 802.11b, 802.11g only at channel 6
-+ *
-+ *	Attenuation (dB)	OS Signal Bars	RSSI by Xirrus (dBm)
-+ *		50				5			-49
-+ *		55				5			-49
-+ *		60				5			-50
-+ *		65				5			-51
-+ *		70				5			-52
-+ *		75				5			-54
-+ *		80				5			-55
-+ *		85				4			-60
-+ *		90				3			-63
-+ *		95				3			-65
-+ *		100				2			-67
-+ *		102				2			-67
-+ *		104				1			-70
-+ */
-+			if (pwdb_all >= 50)
-+				sq = 100;
-+			else if (pwdb_all >= 35 && pwdb_all < 50)
-+				sq = 80;
-+			else if (pwdb_all >= 31 && pwdb_all < 35)
-+				sq = 60;
-+			else if (pwdb_all >= 22 && pwdb_all < 31)
-+				sq = 40;
-+			else if (pwdb_all >= 18 && pwdb_all < 22)
-+				sq = 20;
-+			else
-+				sq = 10;
-+		} else {
-+			if (pwdb_all >= 50)
-+				sq = 100;
-+			else if (pwdb_all >= 35 && pwdb_all < 50)
-+				sq = 80;
-+			else if (pwdb_all >= 22 && pwdb_all < 35)
-+				sq = 60;
-+			else if (pwdb_all >= 18 && pwdb_all < 22)
-+				sq = 40;
-+			else
-+				sq = 10;
-+		}
-+
-+	} else {
-+		/* OFDM rate */
-+
-+		if (dm->support_ic_type & ODM_RTL8192E) {
-+			if (RSSI >= 45)
-+				sq = 100;
-+			else if (RSSI >= 22 && RSSI < 45)
-+				sq = 80;
-+			else if (RSSI >= 18 && RSSI < 22)
-+				sq = 40;
-+			else
-+				sq = 20;
-+		} else {
-+			if (RSSI >= 45)
-+				sq = 100;
-+			else if (RSSI >= 22 && RSSI < 45)
-+				sq = 80;
-+			else if (RSSI >= 18 && RSSI < 22)
-+				sq = 40;
-+			else
-+				sq = 20;
-+		}
-+	}
-+	return sq;
-+}
-+
-+static u8 phydm_sq_patch_rt_cid_819x_acer(
-+	struct dm_struct *dm,
-+	u8 is_cck_rate,
-+	u8 pwdb_all,
-+	u8 path,
-+	u8 RSSI)
-+{
-+	u8 sq = 0;
-+
-+	if (is_cck_rate) {
-+#if OS_WIN_FROM_WIN8(OS_VERSION)
-+		if (pwdb_all >= 50)
-+			sq = 100;
-+		else if (pwdb_all >= 35 && pwdb_all < 50)
-+			sq = 80;
-+		else if (pwdb_all >= 30 && pwdb_all < 35)
-+			sq = 60;
-+		else if (pwdb_all >= 25 && pwdb_all < 30)
-+			sq = 40;
-+		else if (pwdb_all >= 20 && pwdb_all < 25)
-+			sq = 20;
-+		else
-+			sq = 10;
-+#else
-+		if (pwdb_all >= 50)
-+			sq = 100;
-+		else if (pwdb_all >= 35 && pwdb_all < 50)
-+			sq = 80;
-+		else if (pwdb_all >= 30 && pwdb_all < 35)
-+			sq = 60;
-+		else if (pwdb_all >= 25 && pwdb_all < 30)
-+			sq = 40;
-+		else if (pwdb_all >= 20 && pwdb_all < 25)
-+			sq = 20;
-+		else
-+			sq = 10;
-+
-+		/* @Abnormal case, do not indicate the value above 20 on Win7 */
-+		if (pwdb_all == 0)
-+			sq = 20;
-+#endif
-+
-+	} else {
-+		/* OFDM rate */
-+		if (dm->support_ic_type & ODM_RTL8192E) {
-+			if (RSSI >= 45)
-+				sq = 100;
-+			else if (RSSI >= 22 && RSSI < 45)
-+				sq = 80;
-+			else if (RSSI >= 18 && RSSI < 22)
-+				sq = 40;
-+			else
-+				sq = 20;
-+		} else {
-+			if (RSSI >= 35)
-+				sq = 100;
-+			else if (RSSI >= 30 && RSSI < 35)
-+				sq = 80;
-+			else if (RSSI >= 25 && RSSI < 30)
-+				sq = 40;
-+			else
-+				sq = 20;
-+		}
-+	}
-+	return sq;
-+}
-+#endif
-+
-+static u8
-+phydm_evm_2_percent(s8 value)
-+{
-+	/* @-33dB~0dB to 0%~99% */
-+	s8 ret_val;
-+
-+	ret_val = value;
-+	ret_val /= 2;
-+
-+/*@dbg_print("value=%d\n", value);*/
-+#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	if (ret_val >= 0)
-+		ret_val = 0;
-+
-+	if (ret_val <= -40)
-+		ret_val = -40;
-+
-+	ret_val = 0 - ret_val;
-+	ret_val *= 3;
-+#else
-+	if (ret_val >= 0)
-+		ret_val = 0;
-+
-+	if (ret_val <= -33)
-+		ret_val = -33;
-+
-+	ret_val = 0 - ret_val;
-+	ret_val *= 3;
-+
-+	if (ret_val == 99)
-+		ret_val = 100;
-+#endif
-+
-+	return (u8)ret_val;
-+}
-+
-+s8 phydm_cck_rssi_convert(struct dm_struct *dm, u16 lna_idx, u8 vga_idx)
-+{
-+	/*@phydm_get_cck_rssi_table_from_reg*/
-+	return (dm->cck_lna_gain_table[lna_idx] - (vga_idx << 1));
-+}
-+
-+void phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm)
-+{
-+	u8 used_lna_idx_tmp;
-+	u32 reg_0xa80 = 0x7431, reg_0xabc = 0xcbe5edfd;
-+	u32 val = 0;
-+	u8 i;
-+
-+	/*@example: {-53, -43, -33, -27, -19, -13, -3, 1}*/
-+	/*@{0xCB, 0xD5, 0xDF, 0xE5, 0xED, 0xF3, 0xFD, 0x2}*/
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "CCK LNA Gain table init\n");
-+
-+	if (!(dm->support_ic_type & ODM_RTL8197F))
-+		return;
-+
-+	reg_0xa80 = odm_get_bb_reg(dm, R_0xa80, 0xFFFF);
-+	reg_0xabc = odm_get_bb_reg(dm, R_0xabc, MASKDWORD);
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xa80 = 0x%x\n", reg_0xa80);
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xabc = 0x%x\n", reg_0xabc);
-+
-+	for (i = 0; i <= 3; i++) {
-+		used_lna_idx_tmp = (u8)((reg_0xa80 >> (4 * i)) & 0x7);
-+		val = (reg_0xabc >> (8 * i)) & 0xff;
-+		dm->cck_lna_gain_table[used_lna_idx_tmp] = (s8)val;
-+	}
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "cck_lna_gain_table = {%d,%d,%d,%d,%d,%d,%d,%d}\n",
-+		  dm->cck_lna_gain_table[0], dm->cck_lna_gain_table[1],
-+		  dm->cck_lna_gain_table[2], dm->cck_lna_gain_table[3],
-+		  dm->cck_lna_gain_table[4], dm->cck_lna_gain_table[5],
-+		  dm->cck_lna_gain_table[6], dm->cck_lna_gain_table[7]);
-+}
-+
-+s8 phydm_get_cck_rssi(void *dm_void, u8 lna_idx, u8 vga_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	s8 rx_pow = 0;
-+
-+	switch (dm->support_ic_type) {
-+	#if (RTL8197F_SUPPORT)
-+	case ODM_RTL8197F:
-+		rx_pow = phydm_cck_rssi_convert(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8723D_SUPPORT)
-+	case ODM_RTL8723D:
-+		rx_pow = phydm_cckrssi_8723d(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8710B_SUPPORT)
-+	case ODM_RTL8710B:
-+		rx_pow = phydm_cckrssi_8710b(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8721D_SUPPORT)
-+	case ODM_RTL8721D:
-+		rx_pow = phydm_cckrssi_8721d(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8710C_SUPPORT)
-+	case ODM_RTL8710C:
-+		rx_pow = phydm_cckrssi_8710c(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8192F_SUPPORT)
-+	case ODM_RTL8192F:
-+		rx_pow = phydm_cckrssi_8192f(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8821C_SUPPORT)
-+	case ODM_RTL8821C:
-+		rx_pow = phydm_cck_rssi_8821c(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8195B_SUPPORT)
-+	case ODM_RTL8195B:
-+		rx_pow = phydm_cck_rssi_8195B(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8188E_SUPPORT)
-+	case ODM_RTL8188E:
-+		rx_pow = phydm_cck_rssi_8188e(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8192E_SUPPORT)
-+	case ODM_RTL8192E:
-+		rx_pow = phydm_cck_rssi_8192e(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8723B_SUPPORT)
-+	case ODM_RTL8723B:
-+		rx_pow = phydm_cck_rssi_8723b(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8703B_SUPPORT)
-+	case ODM_RTL8703B:
-+		rx_pow = phydm_cck_rssi_8703b(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8188F_SUPPORT)
-+	case ODM_RTL8188F:
-+		rx_pow = phydm_cck_rssi_8188f(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8195A_SUPPORT)
-+	case ODM_RTL8195A:
-+		rx_pow = phydm_cck_rssi_8195a(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8812A_SUPPORT)
-+	case ODM_RTL8812:
-+		rx_pow = phydm_cck_rssi_8812a(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8821A_SUPPORT || RTL8881A_SUPPORT)
-+	case ODM_RTL8821:
-+	case ODM_RTL8881A:
-+		rx_pow = phydm_cck_rssi_8821a(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	#if (RTL8814A_SUPPORT)
-+	case ODM_RTL8814A:
-+		rx_pow = phydm_cck_rssi_8814a(dm, lna_idx, vga_idx);
-+		break;
-+	#endif
-+
-+	default:
-+		break;
-+	}
-+
-+	return rx_pow;
-+}
-+
-+#if (ODM_IC_11N_SERIES_SUPPORT)
-+void phydm_phy_sts_n_parsing(struct dm_struct *dm,
-+			     struct phydm_phyinfo_struct *phy_info,
-+			     u8 *phy_status_inf,
-+			     struct phydm_perpkt_info_struct *pktinfo)
-+{
-+	u8 i = 0;
-+	s8 rx_pwr[4], rx_pwr_all = 0;
-+	u8 EVM, pwdb_all = 0, pwdb_all_bt = 0;
-+	u8 RSSI, total_rssi = 0;
-+	u8 rf_rx_num = 0;
-+	u8 lna_idx = 0;
-+	u8 vga_idx = 0;
-+	u8 cck_agc_rpt;
-+	s8 evm_tmp = 0;
-+	u8 sq = 0;
-+	u8 val_tmp = 0;
-+	s8 val_s8 = 0;
-+	struct phy_status_rpt_8192cd *phy_sts = NULL;
-+
-+	phy_sts = (struct phy_status_rpt_8192cd *)phy_status_inf;
-+
-+	if (pktinfo->is_cck_rate) {
-+		cck_agc_rpt = phy_sts->cck_agc_rpt_ofdm_cfosho_a;
-+
-+		/*@3 bit LNA*/
-+		lna_idx = ((cck_agc_rpt & 0xE0) >> 5);
-+		vga_idx = (cck_agc_rpt & 0x1F);
-+
-+		#if (RTL8703B_SUPPORT)
-+		if (dm->support_ic_type & (ODM_RTL8703B) &&
-+		    dm->cck_agc_report_type == 1) {
-+			/*@4 bit LNA*/
-+			if (phy_sts->cck_rpt_b_ofdm_cfosho_b & BIT(7))
-+				val_tmp = 1;
-+			else
-+				val_tmp = 0;
-+			lna_idx = (val_tmp << 3) | lna_idx;
-+		}
-+		#endif
-+
-+		rx_pwr_all = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
-+
-+		PHYDM_DBG(dm, DBG_RSSI_MNTR,
-+			  "ext_lna_gain (( %d )), lna_idx: (( 0x%x )), vga_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n",
-+			  dm->ext_lna_gain, lna_idx, vga_idx, rx_pwr_all);
-+
-+		if (dm->board_type & ODM_BOARD_EXT_LNA)
-+			rx_pwr_all -= dm->ext_lna_gain;
-+
-+		pwdb_all = phydm_pw_2_percent(rx_pwr_all);
-+
-+		if (pktinfo->is_to_self) {
-+			dm->cck_lna_idx = lna_idx;
-+			dm->cck_vga_idx = vga_idx;
-+		}
-+
-+		phy_info->rx_pwdb_all = pwdb_all;
-+		phy_info->bt_rx_rssi_percentage = pwdb_all;
-+		phy_info->recv_signal_power = rx_pwr_all;
-+
-+		/* @(3) Get Signal Quality (EVM) */
-+		#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+		if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO)
-+			sq = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0);
-+		else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER)
-+			sq = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0);
-+		else
-+		#endif
-+			sq = phydm_get_signal_quality(phy_info, dm, phy_sts);
-+
-+		/* @dbg_print("cck sq = %d\n", sq); */
-+
-+		phy_info->signal_quality = sq;
-+		phy_info->rx_mimo_signal_quality[RF_PATH_A] = sq;
-+		phy_info->rx_mimo_signal_quality[RF_PATH_B] = -1;
-+
-+		for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
-+			if (i == 0)
-+				phy_info->rx_mimo_signal_strength[0] = pwdb_all;
-+			else
-+				phy_info->rx_mimo_signal_strength[i] = 0;
-+		}
-+	} else { /* @2 is OFDM rate */
-+
-+		/* @(1)Get RSSI for HT rate */
-+
-+		for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
-+			if (dm->rf_path_rx_enable & BIT(i))
-+				rf_rx_num++;
-+
-+			val_s8 = phy_sts->path_agc[i].gain & 0x3F;
-+			rx_pwr[i] = (val_s8 * 2) - 110;
-+
-+			if (pktinfo->is_to_self)
-+				dm->ofdm_agc_idx[i] = val_s8;
-+
-+			phy_info->rx_pwr[i] = rx_pwr[i];
-+			RSSI = phydm_pw_2_percent(rx_pwr[i]);
-+			total_rssi += RSSI;
-+
-+			phy_info->rx_mimo_signal_strength[i] = (u8)RSSI;
-+
-+			/* @Get Rx snr value in DB */
-+			val_s8 = (s8)(phy_sts->path_rxsnr[i] / 2);
-+			phy_info->rx_snr[i] = val_s8;
-+
-+			/* Record Signal Strength for next packet */
-+
-+			#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+			if (i == RF_PATH_A) {
-+				if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {
-+					phy_info->signal_quality = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, i, RSSI);
-+				} else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER)
-+					phy_info->signal_quality = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, RSSI);
-+			}
-+			#endif
-+		}
-+
-+		/* @(2)PWDB, Average PWDB calculated by hardware (for RA) */
-+		val_s8 = phy_sts->cck_sig_qual_ofdm_pwdb_all >> 1;
-+		rx_pwr_all = (val_s8  & 0x7f) - 110;
-+
-+		pwdb_all = phydm_pw_2_percent(rx_pwr_all);
-+		pwdb_all_bt = pwdb_all;
-+
-+		phy_info->rx_pwdb_all = pwdb_all;
-+		phy_info->bt_rx_rssi_percentage = pwdb_all_bt;
-+		phy_info->rx_power = rx_pwr_all;
-+		phy_info->recv_signal_power = rx_pwr_all;
-+
-+		/* @(3)EVM of HT rate */
-+		for (i = 0; i < pktinfo->rate_ss; i++) {
-+		/* @Do not use shift operation like "rx_evmX >>= 1"
-+		 * because the compilor of free build environment
-+		 * fill most significant bit to "zero" when doing shifting
-+		 * operation which may change a negative
-+		 * value to positive one, then the dbm value
-+		 * (which is supposed to be negative) is not correct anymore.
-+		 */
-+			if (i >= PHYDM_MAX_RF_PATH_N)
-+				break;
-+
-+			EVM = phydm_evm_2_percent(phy_sts->stream_rxevm[i]);
-+
-+			/*@Fill value in RFD, Get the 1st spatial stream only*/
-+			if (i == RF_PATH_A)
-+				phy_info->signal_quality = (u8)(EVM & 0xff);
-+
-+			phy_info->rx_mimo_signal_quality[i] = (u8)(EVM & 0xff);
-+
-+			if (phy_sts->stream_rxevm[i] < 0)
-+				evm_tmp = 0 - phy_sts->stream_rxevm[i];
-+
-+			if (evm_tmp == 64)
-+				evm_tmp = 0;
-+
-+			phy_info->rx_mimo_evm_dbm[i] = (u8)evm_tmp;
-+		}
-+		phydm_parsing_cfo(dm, pktinfo,
-+				  phy_sts->path_cfotail, pktinfo->rate_ss);
-+	}
-+
-+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->ant_sel;
-+	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->ant_sel_b;
-+	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antsel_rx_keep_2;
-+	#endif
-+}
-+#endif
-+
-+#if ODM_IC_11AC_SERIES_SUPPORT
-+static s16
-+phydm_cfo(s8 value)
-+{
-+	s16 ret_val;
-+
-+	if (value < 0) {
-+		ret_val = 0 - value;
-+		ret_val = (ret_val << 1) + (ret_val >> 1); /*@2.5~=312.5/2^7 */
-+		ret_val = ret_val | BIT(12); /*set bit12 as 1 for negative cfo*/
-+	} else {
-+		ret_val = value;
-+		ret_val = (ret_val << 1) + (ret_val >> 1); /* @*2.5~=312.5/2^7*/
-+	}
-+	return ret_val;
-+}
-+
-+static u8
-+phydm_evm_dbm(s8 value)
-+{
-+	s8 ret_val = value;
-+
-+	/* @-33dB~0dB to 33dB ~ 0dB */
-+	if (ret_val == -128)
-+		ret_val = 127;
-+	else if (ret_val < 0)
-+		ret_val = 0 - ret_val;
-+
-+	ret_val = ret_val >> 1;
-+	return (u8)ret_val;
-+}
-+
-+void phydm_rx_physts_bw_parsing(struct phydm_phyinfo_struct *phy_info,
-+				struct phydm_perpkt_info_struct *
-+				pktinfo,
-+				struct phy_status_rpt_8812 *
-+				phy_sts)
-+{
-+	if (pktinfo->data_rate > ODM_RATE54M) {
-+		switch (phy_sts->r_RFMOD) {
-+		case 1:
-+			if (phy_sts->sub_chnl == 0)
-+				phy_info->band_width = 1;
-+			else
-+				phy_info->band_width = 0;
-+			break;
-+
-+		case 2:
-+			if (phy_sts->sub_chnl == 0)
-+				phy_info->band_width = 2;
-+			else if (phy_sts->sub_chnl == 9 ||
-+				 phy_sts->sub_chnl == 10)
-+				phy_info->band_width = 1;
-+			else
-+				phy_info->band_width = 0;
-+			break;
-+
-+		default:
-+		case 0:
-+			phy_info->band_width = 0;
-+			break;
-+		}
-+	}
-+}
-+
-+void phydm_get_sq(struct dm_struct *dm, struct phydm_phyinfo_struct *phy_info,
-+		  u8 is_cck_rate)
-+{
-+	u8 sq = 0;
-+	u8 pwdb_all = phy_info->rx_pwdb_all; /*precentage*/
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	u8 rssi = phy_info->rx_mimo_signal_strength[0];
-+	#endif
-+
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) {
-+		if (is_cck_rate)
-+			sq = phydm_sq_patch_lenovo(dm, 1, pwdb_all, 0, 0);
-+		else
-+			sq = phydm_sq_patch_lenovo(dm, 0, pwdb_all, 0, rssi);
-+	} else
-+	#endif
-+	{
-+		if (is_cck_rate) {
-+			if (pwdb_all > 40 && !dm->is_in_hct_test) {
-+				sq = 100;
-+			} else {
-+				if (pwdb_all > 64)
-+					sq = 0;
-+				else if (pwdb_all < 20)
-+					sq = 100;
-+				else
-+					sq = ((64 - pwdb_all) * 100) / 44;
-+			}
-+		} else {
-+			sq = phy_info->rx_mimo_signal_quality[0];
-+		}
-+	}
-+
-+#if 0
-+	/* @dbg_print("cck sq = %d\n", sq); */
-+#endif
-+	phy_info->signal_quality = sq;
-+}
-+
-+void phydm_rx_physts_1st_type(struct dm_struct *dm,
-+			      struct phydm_phyinfo_struct *phy_info,
-+			      u8 *phy_status_inf,
-+			      struct phydm_perpkt_info_struct *pktinfo)
-+{
-+	u8 i = 0;
-+	s8 rx_pwr_db = 0;
-+	u8 val = 0; /*tmp value*/
-+	s8 val_s8 = 0; /*tmp value*/
-+	u8 rssi = 0; /*pre path RSSI*/
-+	u8 rf_rx_num = 0;
-+	u8 lna_idx = 0, vga_idx = 0;
-+	u8 cck_agc_rpt = 0;
-+	struct phy_status_rpt_8812 *phy_sts = NULL;
-+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	#endif
-+
-+	phy_sts = (struct phy_status_rpt_8812 *)phy_status_inf;
-+	phydm_rx_physts_bw_parsing(phy_info, pktinfo, phy_sts);
-+
-+	/* @== [CCK rate] ====================================================*/
-+	if (pktinfo->is_cck_rate) {
-+		cck_agc_rpt = phy_sts->cfosho[0];
-+		lna_idx = (cck_agc_rpt & 0xE0) >> 5;
-+		vga_idx = cck_agc_rpt & 0x1F;
-+
-+		rx_pwr_db = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
-+		rssi = phydm_pw_2_percent(rx_pwr_db);
-+
-+		if (dm->support_ic_type == ODM_RTL8812 &&
-+		    !dm->is_cck_high_power) {
-+			if (rssi >= 80) {
-+				rssi = ((rssi - 80) << 1) +
-+					   ((rssi - 80) >> 1) + 80;
-+			} else if ((rssi <= 78) && (rssi >= 20)) {
-+				rssi += 3;
-+			}
-+		}
-+		dm->cck_lna_idx = lna_idx;
-+		dm->cck_vga_idx = vga_idx;
-+
-+		phy_info->rx_pwdb_all = rssi;
-+		phy_info->rx_mimo_signal_strength[0] = rssi;
-+	} else {
-+	/* @== [OFDM rate] ===================================================*/
-+		for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
-+			/*@[RSSI]*/
-+			if (dm->rf_path_rx_enable & BIT(i))
-+				rf_rx_num++;
-+
-+			if (i < RF_PATH_C)
-+				val = phy_sts->gain_trsw[i];
-+			else
-+				val = phy_sts->gain_trsw_cd[i - 2];
-+
-+			phy_info->rx_pwr[i] = (val & 0x7F) - 110;
-+			rssi = phydm_pw_2_percent(phy_info->rx_pwr[i]);
-+			phy_info->rx_mimo_signal_strength[i] = rssi;
-+
-+			/*@[SNR]*/
-+			if (i < RF_PATH_C)
-+				val_s8 = phy_sts->rxsnr[i];
-+			else if (dm->support_ic_type & (ODM_RTL8814A))
-+				val_s8 = (s8)phy_sts->csi_current[i - 2];
-+
-+			phy_info->rx_snr[i] = val_s8 >> 1;
-+
-+			/*@[CFO_short  & CFO_tail]*/
-+			if (i < RF_PATH_C) {
-+				val_s8 = phy_sts->cfosho[i];
-+				phy_info->cfo_short[i] = phydm_cfo(val_s8);
-+				val_s8 = phy_sts->cfotail[i];
-+				phy_info->cfo_tail[i] = phydm_cfo(val_s8);
-+			}
-+
-+			if (i < RF_PATH_C && pktinfo->is_to_self)
-+				dm->ofdm_agc_idx[i] = phy_sts->gain_trsw[i];
-+		}
-+
-+	/* @== [PWDB] ========================================================*/
-+
-+		/*@(Avg PWDB calculated by hardware*/
-+		if (!dm->is_mp_chip) /*@8812, 8821*/
-+			val = phy_sts->pwdb_all;
-+		else
-+			val = phy_sts->pwdb_all >> 1; /*old fomula*/
-+
-+		rx_pwr_db = (val & 0x7f) - 110;
-+		phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db);
-+
-+		/*@(4)EVM of OFDM rate*/
-+		for (i = 0; i < pktinfo->rate_ss; i++) {
-+			if (!pktinfo->is_cck_rate &&
-+			    pktinfo->data_rate <= ODM_RATE54M) {
-+				val_s8 = phy_sts->sigevm;
-+			} else if (i < RF_PATH_C) {
-+				if (phy_sts->rxevm[i] == -128)
-+					phy_sts->rxevm[i] = -25;
-+
-+				val_s8 = phy_sts->rxevm[i];
-+			} else {
-+				if (phy_sts->rxevm_cd[i - 2] == -128)
-+					phy_sts->rxevm_cd[i - 2] = -25;
-+
-+				val_s8 = phy_sts->rxevm_cd[i - 2];
-+			}
-+			/*@[EVM to 0~100%]*/
-+			val = phydm_evm_2_percent(val_s8);
-+			phy_info->rx_mimo_signal_quality[i] = val;
-+			/*@[EVM dBm]*/
-+			phy_info->rx_mimo_evm_dbm[i] = phydm_evm_dbm(val_s8);
-+		}
-+		phydm_parsing_cfo(dm, pktinfo,
-+				  phy_sts->cfotail, pktinfo->rate_ss);
-+	}
-+
-+	/* @== [General Info] ================================================*/
-+
-+	phy_info->rx_power = rx_pwr_db;
-+	phy_info->bt_rx_rssi_percentage = phy_info->rx_pwdb_all;
-+	phy_info->recv_signal_power = phy_info->rx_power;
-+	phydm_get_sq(dm, phy_info, pktinfo->is_cck_rate);
-+
-+	dm->rx_pwdb_ave = dm->rx_pwdb_ave + phy_info->rx_pwdb_all;
-+
-+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	fat_tab->hw_antsw_occur = phy_sts->hw_antsw_occur;
-+	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_anta;
-+	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_antb;
-+	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_antc;
-+	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_antd;
-+	#endif
-+}
-+
-+#endif
-+
-+void phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id)
-+{
-+	struct cmn_sta_info *sta;
-+
-+	sta = dm->phydm_sta_info[station_id];
-+
-+	if (!is_sta_active(sta))
-+		return;
-+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "Reset RSSI for macid = (( %d ))\n",
-+		  station_id);
-+
-+	sta->rssi_stat.rssi_cck = -1;
-+	sta->rssi_stat.rssi_ofdm = -1;
-+	sta->rssi_stat.rssi = -1;
-+	sta->rssi_stat.ofdm_pkt_cnt = 0;
-+	sta->rssi_stat.cck_pkt_cnt = 0;
-+	sta->rssi_stat.cck_sum_power = 0;
-+	sta->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT;
-+	sta->rssi_stat.packet_map = 0;
-+	sta->rssi_stat.valid_bit = 0;
-+}
-+
-+#if (ODM_IC_11N_SERIES_SUPPORT || ODM_IC_11AC_SERIES_SUPPORT)
-+
-+s32 phydm_get_rssi_8814_ofdm(struct dm_struct *dm, u8 *rssi_in)
-+{
-+	s32 rssi_avg;
-+	u8 rx_count = 0;
-+	u64 rssi_linear = 0;
-+
-+	if (dm->rx_ant_status & BB_PATH_A) {
-+		rx_count++;
-+		rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_A]);
-+	}
-+
-+	if (dm->rx_ant_status & BB_PATH_B) {
-+		rx_count++;
-+		rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_B]);
-+	}
-+
-+	if (dm->rx_ant_status & BB_PATH_C) {
-+		rx_count++;
-+		rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_C]);
-+	}
-+
-+	if (dm->rx_ant_status & BB_PATH_D) {
-+		rx_count++;
-+		rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_D]);
-+	}
-+
-+	/* @Rounding and removing fractional bits */
-+	rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
-+
-+	/* @Calculate average RSSI */
-+	switch (rx_count) {
-+	case 2:
-+		rssi_linear = DIVIDED_2(rssi_linear);
-+		break;
-+	case 3:
-+		rssi_linear = DIVIDED_3(rssi_linear);
-+		break;
-+	case 4:
-+		rssi_linear = DIVIDED_4(rssi_linear);
-+		break;
-+	}
-+	rssi_avg = odm_convert_to_db(rssi_linear);
-+
-+	return rssi_avg;
-+}
-+
-+void phydm_process_rssi_for_dm(struct dm_struct *dm,
-+			       struct phydm_phyinfo_struct *phy_info,
-+			       struct phydm_perpkt_info_struct *pktinfo)
-+{
-+	s32 rssi_ave = 0; /*@average among all paths*/
-+	s8 rssi_all = 0; /*@average value of CCK & OFDM*/
-+	s8 rssi_cck_tmp = 0, rssi_ofdm_tmp = 0;
-+	u8 i = 0;
-+	u8 rssi_max = 0, rssi_min = 0;
-+	u32 w1 = 0, w2 = 0; /*weighting*/
-+	u8 send_rssi_2_fw = 0;
-+	u8 *rssi_tmp = NULL;
-+	struct cmn_sta_info *sta = NULL;
-+	struct rssi_info *rssi_t = NULL;
-+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	#endif
-+	#endif
-+
-+	if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
-+		return;
-+
-+	#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
-+	odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(dm, phy_info, pktinfo);
-+	#endif
-+
-+	sta = dm->phydm_sta_info[pktinfo->station_id];
-+
-+	if (!is_sta_active(sta))
-+		return;
-+
-+	rssi_t = &sta->rssi_stat;
-+
-+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-+	if ((dm->support_ability & ODM_BB_ANT_DIV) &&
-+	    fat_tab->enable_ctrl_frame_antdiv) {
-+		if (pktinfo->is_packet_match_bssid)
-+			dm->data_frame_num++;
-+
-+		if (fat_tab->use_ctrl_frame_antdiv) {
-+			if (!pktinfo->is_to_self) /*@data frame + CTRL frame*/
-+				return;
-+		} else {
-+			/*@data frame only*/
-+			if (!pktinfo->is_packet_match_bssid)
-+				return;
-+		}
-+	} else
-+	#endif
-+	#endif
-+	{
-+		if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
-+			return;
-+	}
-+
-+	if (pktinfo->is_packet_beacon) {
-+		dm->phy_dbg_info.num_qry_beacon_pkt++;
-+		dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
-+	}
-+
-+	/* @--------------Statistic for antenna/path diversity--------------- */
-+	#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	if (dm->antdiv_evm_en)
-+		phydm_rx_rate_for_antdiv(dm, pktinfo);
-+	#endif
-+
-+	#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+	if (dm->support_ability & ODM_BB_ANT_DIV)
-+		odm_process_rssi_for_ant_div(dm, phy_info, pktinfo);
-+	#endif
-+
-+	#if (defined(CONFIG_PATH_DIVERSITY))
-+	if (dm->support_ability & ODM_BB_PATH_DIV)
-+		phydm_process_rssi_for_path_div(dm, phy_info, pktinfo);
-+	#endif
-+	/* @----------------------------------------------------------------- */
-+
-+	rssi_cck_tmp = rssi_t->rssi_cck;
-+	rssi_ofdm_tmp = rssi_t->rssi_ofdm;
-+	rssi_all = rssi_t->rssi;
-+
-+	if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_beacon))
-+		return;
-+
-+	if (!pktinfo->is_cck_rate) {
-+/* @=== [ofdm RSSI] ======================================================== */
-+		rssi_tmp = phy_info->rx_mimo_signal_strength;
-+
-+		#if (RTL8814A_SUPPORT == 1)
-+		if (dm->support_ic_type & (ODM_RTL8814A)) {
-+			rssi_ave = phydm_get_rssi_8814_ofdm(dm, rssi_tmp);
-+		} else
-+		#endif
-+		{
-+			if (rssi_tmp[RF_PATH_B] == 0) {
-+				rssi_ave = rssi_tmp[RF_PATH_A];
-+			} else {
-+				if (rssi_tmp[RF_PATH_A] > rssi_tmp[RF_PATH_B]) {
-+					rssi_max = rssi_tmp[RF_PATH_A];
-+					rssi_min = rssi_tmp[RF_PATH_B];
-+				} else {
-+					rssi_max = rssi_tmp[RF_PATH_B];
-+					rssi_min = rssi_tmp[RF_PATH_A];
-+				}
-+				if ((rssi_max - rssi_min) < 3)
-+					rssi_ave = rssi_max;
-+				else if ((rssi_max - rssi_min) < 6)
-+					rssi_ave = rssi_max - 1;
-+				else if ((rssi_max - rssi_min) < 10)
-+					rssi_ave = rssi_max - 2;
-+				else
-+					rssi_ave = rssi_max - 3;
-+			}
-+		}
-+
-+		/* OFDM MA RSSI */
-+		if (rssi_ofdm_tmp <= 0) { /* @initialize */
-+			rssi_ofdm_tmp = (s8)phy_info->rx_pwdb_all;
-+		} else {
-+			rssi_ofdm_tmp = (s8)WEIGHTING_AVG(rssi_ofdm_tmp,
-+							  (1 << RSSI_MA) - 1,
-+							  rssi_ave, 1);
-+			if (phy_info->rx_pwdb_all > (u32)rssi_ofdm_tmp)
-+				rssi_ofdm_tmp++;
-+		}
-+
-+		PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi_ofdm=%d\n", rssi_ofdm_tmp);
-+	} else {
-+/* @=== [cck RSSI] ========================================================= */
-+		rssi_ave = phy_info->rx_pwdb_all;
-+
-+		if (rssi_t->cck_pkt_cnt <= 63)
-+			rssi_t->cck_pkt_cnt++;
-+
-+		/* @1 Process CCK RSSI */
-+		if (rssi_cck_tmp <= 0) { /* @initialize */
-+			rssi_cck_tmp = (s8)phy_info->rx_pwdb_all;
-+			rssi_t->cck_sum_power = (u16)phy_info->rx_pwdb_all;
-+			rssi_t->cck_pkt_cnt = 1; /*reset*/
-+			PHYDM_DBG(dm, DBG_RSSI_MNTR, "[1]CCK_INIT\n");
-+		} else if (rssi_t->cck_pkt_cnt <= CCK_RSSI_INIT_COUNT) {
-+			rssi_t->cck_sum_power = rssi_t->cck_sum_power +
-+						(u16)phy_info->rx_pwdb_all;
-+
-+			rssi_cck_tmp = rssi_t->cck_sum_power /
-+				       rssi_t->cck_pkt_cnt;
-+
-+			PHYDM_DBG(dm, DBG_RSSI_MNTR,
-+				  "[2]SumPow=%d, cck_pkt=%d\n",
-+				  rssi_t->cck_sum_power, rssi_t->cck_pkt_cnt);
-+		} else {
-+			rssi_cck_tmp = (s8)WEIGHTING_AVG(rssi_cck_tmp,
-+							 (1 << RSSI_MA) - 1,
-+							 phy_info->rx_pwdb_all,
-+							 1);
-+			if (phy_info->rx_pwdb_all > (u32)rssi_cck_tmp)
-+				rssi_cck_tmp++;
-+		}
-+		PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi_cck=%d\n", rssi_cck_tmp);
-+	}
-+
-+/* @=== [ofdm + cck weighting RSSI] ========================================= */
-+	if (!pktinfo->is_cck_rate) {
-+		if (rssi_t->ofdm_pkt_cnt < 8 && !(rssi_t->packet_map & BIT(7)))
-+			rssi_t->ofdm_pkt_cnt++; /*OFDM packet cnt in bitmap*/
-+
-+		rssi_t->packet_map = (rssi_t->packet_map << 1) | BIT(0);
-+	} else {
-+		if (rssi_t->ofdm_pkt_cnt > 0 && rssi_t->packet_map & BIT(7))
-+			rssi_t->ofdm_pkt_cnt--;
-+
-+		rssi_t->packet_map = rssi_t->packet_map << 1;
-+	}
-+
-+	if (rssi_t->ofdm_pkt_cnt == 8) {
-+		rssi_all = rssi_ofdm_tmp;
-+	} else {
-+		if (rssi_t->valid_bit < 8)
-+			rssi_t->valid_bit++;
-+
-+		if (rssi_t->valid_bit == 8) {
-+			if (rssi_t->ofdm_pkt_cnt > 4)
-+				w1 = 64;
-+			else
-+				w1 = (u32)(rssi_t->ofdm_pkt_cnt << 4);
-+
-+			w2 = 64 - w1;
-+
-+			rssi_all = (s8)((w1 * (u32)rssi_ofdm_tmp +
-+					 w2 * (u32)rssi_cck_tmp) >> 6);
-+		} else if (rssi_t->valid_bit != 0) { /*@(valid_bit > 8)*/
-+			w1 = (u32)rssi_t->ofdm_pkt_cnt;
-+			w2 = (u32)(rssi_t->valid_bit - rssi_t->ofdm_pkt_cnt);
-+			rssi_all = (s8)WEIGHTING_AVG((u32)rssi_ofdm_tmp, w1,
-+						     (u32)rssi_cck_tmp, w2);
-+		} else {
-+			rssi_all = 0;
-+		}
-+	}
-+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi=%d,w1=%d,w2=%d\n", rssi_all, w1, w2);
-+
-+	if ((rssi_t->ofdm_pkt_cnt >= 1 || rssi_t->cck_pkt_cnt >= 5) &&
-+	    rssi_t->is_send_rssi == RA_RSSI_STATE_INIT) {
-+		send_rssi_2_fw = 1;
-+		rssi_t->is_send_rssi = RA_RSSI_STATE_SEND;
-+	}
-+
-+	rssi_t->rssi_cck = rssi_cck_tmp;
-+	rssi_t->rssi_ofdm = rssi_ofdm_tmp;
-+	rssi_t->rssi = rssi_all;
-+
-+	if (send_rssi_2_fw) { /* Trigger init rate by RSSI */
-+		if (rssi_t->ofdm_pkt_cnt != 0)
-+			rssi_t->rssi = rssi_ofdm_tmp;
-+
-+		PHYDM_DBG(dm, DBG_RSSI_MNTR,
-+			  "[Send to FW] PWDB=%d, ofdm_pkt=%d, cck_pkt=%d\n",
-+			  rssi_all, rssi_t->ofdm_pkt_cnt, rssi_t->cck_pkt_cnt);
-+	}
-+
-+#if 0
-+	/* @dbg_print("ofdm_pkt=%d, weighting=%d\n", ofdm_pkt_cnt, weighting);*/
-+	/* @dbg_print("rssi_ofdm_tmp=%d, rssi_all=%d, rssi_cck_tmp=%d\n", */
-+	/*	rssi_ofdm_tmp, rssi_all, rssi_cck_tmp); */
-+#endif
-+}
-+#endif
-+
-+#ifdef PHYSTS_3RD_TYPE_SUPPORT
-+#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
-+void phydm_physts_auto_switch_jgr3_reset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
-+
-+	pkt_proc->phy_ppdu_cnt = 0xff;
-+	pkt_proc->mac_ppdu_cnt = 0xff;
-+	pkt_proc->page_bitmap_record = 0;
-+}
-+
-+boolean phydm_physts_auto_switch_jgr3(void *dm_void, u8 *phy_sts,
-+				      struct phydm_perpkt_info_struct *pktinfo)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
-+	boolean is_skip_physts_parsing = false;
-+	u8 phy_sts_byte0 = (*phy_sts & 0xff);
-+	u8 phy_ppdu_cnt_pre = 0, mac_ppdu_cnt_pre = 0;
-+	u8 ppdu_phy_rate_pre = 0, ppdu_macid_pre = 0;
-+	u8 page = phy_sts_byte0 & 0xf;
-+
-+	if (!pkt_proc->physts_auto_swch_en)
-+		return is_skip_physts_parsing;
-+
-+	phy_ppdu_cnt_pre = pkt_proc->phy_ppdu_cnt;
-+	mac_ppdu_cnt_pre = pkt_proc->mac_ppdu_cnt;
-+	ppdu_phy_rate_pre = pkt_proc->ppdu_phy_rate;
-+	ppdu_macid_pre = pkt_proc->ppdu_macid;
-+
-+	pkt_proc->phy_ppdu_cnt = (phy_sts_byte0 & 0x30) >> 4;
-+	pkt_proc->mac_ppdu_cnt = pktinfo->ppdu_cnt;
-+	pkt_proc->ppdu_phy_rate = pktinfo->data_rate;
-+	pkt_proc->ppdu_macid = pktinfo->station_id;
-+
-+	PHYDM_DBG(dm, DBG_PHY_STATUS,
-+		  "[rate:0x%x] PPDU mac{pre, curr}= {%d, %d}, phy{pre, curr}= {%d, %d}\n",
-+		  pktinfo->data_rate, mac_ppdu_cnt_pre, pkt_proc->mac_ppdu_cnt,
-+		  phy_ppdu_cnt_pre, pkt_proc->phy_ppdu_cnt);
-+
-+	if (pktinfo->data_rate < ODM_RATEMCS0) {
-+		pkt_proc->page_bitmap_record = 0;
-+		return is_skip_physts_parsing;
-+	}
-+
-+	if (ppdu_macid_pre == pkt_proc->ppdu_macid &&
-+	    ppdu_phy_rate_pre == pkt_proc->ppdu_phy_rate &&
-+	    phy_ppdu_cnt_pre == pkt_proc->phy_ppdu_cnt &&
-+	    mac_ppdu_cnt_pre == pkt_proc->mac_ppdu_cnt) {
-+		if (pkt_proc->page_bitmap_record & BIT(page)) {
-+			/*@PHYDM_DBG(dm, DBG_PHY_STATUS, "collect page-%d enough\n", page);*/
-+			is_skip_physts_parsing = true;
-+		} else if (pkt_proc->page_bitmap_record ==
-+			   pkt_proc->page_bitmap_target) {
-+			/*@PHYDM_DBG(dm, DBG_PHY_STATUS, "collect all enough\n");*/
-+			is_skip_physts_parsing = true;
-+		} else {
-+			/*@PHYDM_DBG(dm, DBG_PHY_STATUS, "update page-%d\n", page);*/
-+			pkt_proc->page_bitmap_record |= BIT(page);
-+		}
-+		pkt_proc->is_1st_mpdu = false;
-+	} else {
-+		/*@PHYDM_DBG(dm, DBG_PHY_STATUS, "[New Pkt] update page-%d\n", page);*/
-+		pkt_proc->page_bitmap_record = BIT(page);
-+		pkt_proc->is_1st_mpdu = true;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_PHY_STATUS,
-+		  "bitmap{record, target}= {0x%x, 0x%x}\n",
-+		  pkt_proc->page_bitmap_record,
-+		  pkt_proc->page_bitmap_target);
-+
-+	return is_skip_physts_parsing;
-+}
-+
-+void phydm_physts_auto_switch_jgr3_set(void *dm_void, boolean enable,
-+				       u8 bitmap_en)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
-+	u16 en_page_num = 1;
-+
-+	if (!(dm->support_ic_type & PHYSTS_AUTO_SWITCH_IC))
-+		return;
-+#if 0
-+	if (!(dm->support_ic_type & PHYSTS_3RD_TYPE_IC))
-+		return;
-+#endif
-+	pkt_proc->physts_auto_swch_en = enable;
-+	pkt_proc->page_bitmap_target = bitmap_en;
-+	phydm_physts_auto_switch_jgr3_reset(dm);
-+	en_page_num = phydm_ones_num_in_bitmap((u64)bitmap_en, 8);
-+
-+	PHYDM_DBG(dm, DBG_CMN, "[%s]en=%d, bitmap_en=%d, en_page_num=%d\n",
-+		  __func__, enable, bitmap_en, en_page_num);
-+
-+	if (enable) {
-+		/*@per MPDU latch & update phy-staatus*/
-+		odm_set_mac_reg(dm, R_0x60c, BIT(31), 1);
-+		/*@Update Period (OFDM Symbol)*/
-+		odm_set_bb_reg(dm, R_0x8c0, 0xfc000, 3);
-+		/*@switchin bitmap*/
-+		odm_set_bb_reg(dm, R_0x8c4, 0x7f80000, bitmap_en);
-+		/*@mode 3*/
-+		odm_set_bb_reg(dm, R_0x8c4, (BIT(28) | BIT(27)), 3);
-+	} else {
-+		odm_set_mac_reg(dm, R_0x60c, BIT(31), 0);
-+		odm_set_bb_reg(dm, R_0x8c0, 0xfc000, 0x1);
-+		odm_set_bb_reg(dm, R_0x8c4, 0x7f80000, 0x2);
-+		odm_set_bb_reg(dm, R_0x8c4, (BIT(28) | BIT(27)), 0);
-+	}
-+}
-+
-+void phydm_avg_condi_num(void *dm_void,
-+			 struct phydm_phyinfo_struct *phy_info,
-+			 struct phydm_perpkt_info_struct *pktinfo)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info;
-+	u16 size_th = PHY_HIST_SIZE - 1; /*size of threshold*/
-+	u16 val = 0, intvl = 0;
-+	u8 arry_idx = 0;
-+
-+	if (pktinfo->rate_ss == 1)
-+		return;
-+
-+	arry_idx = pktinfo->rate_ss - 1;
-+
-+	dbg_s->p4_cnt[arry_idx]++;
-+	dbg_s->cn_sum[arry_idx] += dbg_i->condition_num_seg0;
-+
-+	/*CN Histogram*/
-+	val = (u16)dbg_i->condition_num_seg0;
-+	intvl = phydm_find_intrvl(dm, val, dbg_i->cn_hist_th, size_th);
-+	dbg_s->cn_hist[arry_idx][intvl]++;
-+
-+	dbg_i->condi_num = (u32)dbg_i->condition_num_seg0; /*will remove*/
-+}
-+#endif
-+
-+void phydm_print_phystat_jgr3(struct dm_struct *dm, u8 *phy_sts,
-+			      struct phydm_perpkt_info_struct *pktinfo,
-+			      struct phydm_phyinfo_struct *phy_info)
-+{
-+	struct phy_sts_rpt_jgr3_type0 *rpt0 = NULL;
-+	struct phy_sts_rpt_jgr3_type1 *rpt1 = NULL;
-+	struct phy_sts_rpt_jgr3_type2_3 *rpt2 = NULL;
-+	struct phy_sts_rpt_jgr3_type4 *rpt3 = NULL;
-+	struct phy_sts_rpt_jgr3_type5 *rpt4 = NULL;
-+	struct phy_sts_rpt_jgr3_type6 *rpt5 = NULL;
-+	
-+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
-+	u8 phy_status_page_num = (*phy_sts & 0xf);
-+	u32 *phy_status_tmp = NULL;
-+	u8 i = 0;
-+	/*u32 size = PHY_STATUS_JRGUAR3_DW_LEN << 2;*/
-+
-+	if (!(dm->debug_components & DBG_PHY_STATUS))
-+		return;
-+
-+	rpt0 = (struct phy_sts_rpt_jgr3_type0 *)phy_sts;
-+	rpt1 = (struct phy_sts_rpt_jgr3_type1 *)phy_sts;
-+	rpt2 = (struct phy_sts_rpt_jgr3_type2_3 *)phy_sts;
-+	rpt3 = (struct phy_sts_rpt_jgr3_type4 *)phy_sts;
-+	rpt4 = (struct phy_sts_rpt_jgr3_type5 *)phy_sts;
-+
-+	if (dm->support_ic_type & ODM_RTL8723F) {
-+		rpt5 = (struct phy_sts_rpt_jgr3_type6 *)phy_sts;
-+		
-+		if (pktinfo->is_cck_rate)
-+			phy_status_page_num  = 0;
-+	}
-+
-+	phy_status_tmp = (u32 *)phy_sts;
-+
-+	if (dbg->show_phy_sts_all_pkt == 0) {
-+		if (!pktinfo->is_packet_match_bssid)
-+			return;
-+	}
-+
-+	dbg->show_phy_sts_cnt++;
-+
-+	if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) {
-+		if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt)
-+			return;
-+	}
-+
-+	if (phy_status_page_num == 0)
-+		pr_debug("Phy Status Rpt: CCK\n");
-+	else
-+		pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num);
-+
-+	pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d, ppdu_cnt=%d\n",
-+		 pktinfo->station_id, pktinfo->data_rate,
-+		 pktinfo->is_packet_match_bssid, pktinfo->ppdu_cnt);
-+
-+	for (i = 0; i < PHY_STATUS_JRGUAR3_DW_LEN; i++)
-+		pr_debug("Offset[%d:%d] = 0x%x\n",
-+			 ((4 * i) + 3), (4 * i), phy_status_tmp[i]);
-+
-+	if (phy_status_page_num == 0) { /* @CCK(default) */
-+		if (dm->support_ic_type & ODM_RTL8723F) {
-+			#if (RTL8723F_SUPPORT)
-+			pr_debug("[0] Pop_idx=%d, Pkt_cnt=%d, Channel_msb=%d, AGC_table_path0=%d, TRSW_mux_keep=%d, HW_AntSW_occur_keep_cck=%d, Gnt_BT_keep_cnt=%d,Rssi_msb=%d\n",
-+				 rpt5->pop_idx, rpt5->pkt_cnt,
-+				 rpt5->channel_msb, rpt5->agc_table_a,
-+				 rpt5->trsw, rpt5->hw_antsw_occur_keep_cck,
-+				 rpt5->gnt_bt_keep_cck, rpt5->rssi_msb);
-+			pr_debug("[4] Channel=%d, Antidx_CCK_keep=%d, Cck_mp_gain_idx_keep=%d\n",
-+				 rpt5->channel, rpt5->antidx_a,
-+				 rpt5->mp_gain_idx_a);
-+			pr_debug("[8] Rssi=%d\n",rpt5->rssi);
-+			pr_debug("[12] Avg_cfo=%d\n",rpt5->avg_cfo);
-+			pr_debug("[16] Coarse_cfo=%d, Coarse_cfo_msb=%d, Avg_cfo_msb=%d, Evm_hdr=%d\n",
-+				 rpt5->coarse_cfo, rpt5->coarse_cfo_msb,
-+				 rpt5->avg_cfo_msb, rpt5->evm_hdr);
-+			pr_debug("[20] Evm_pld=%d\n",rpt5->evm_pld);
-+			#endif
-+		} else {
-+			pr_debug("[0] Pkt_cnt=%d, Channel_msb=%d, Pwdb_a=%d, Gain_a=%d, TRSW=%d, AGC_table_b=%d, AGC_table_c=%d,\n",
-+				 rpt0->pkt_cnt, rpt0->channel_msb, rpt0->pwdb_a,
-+				 rpt0->gain_a, rpt0->trsw, rpt0->agc_table_b,
-+				 rpt0->agc_table_c);
-+			pr_debug("[4] Path_Sel_o=%d, Gnt_BT_keep_cnt=%d, HW_AntSW_occur_keep_cck=%d,\n Band=%d, Channel=%d, AGC_table_a=%d, l_RXSC=%d, AGC_table_d=%d\n",
-+				 rpt0->path_sel_o, rpt0->gnt_bt_keep_cck,
-+				 rpt0->hw_antsw_occur_keep_cck, rpt0->band,
-+				 rpt0->channel, rpt0->agc_table_a, rpt0->l_rxsc,
-+				 rpt0->agc_table_d);
-+			pr_debug("[8] AntIdx={%d, %d, %d, %d}, Length=%d\n",
-+				 rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b,
-+				 rpt0->antidx_a, rpt0->length);
-+			pr_debug("[12] MF_off=%d, SQloss=%d, lockbit=%d, raterr=%d, rxrate=%d, lna_h_a=%d, CCK_BB_power_a=%d, lna_l_a=%d, vga_a=%d, sq=%d\n",
-+				 rpt0->mf_off, rpt0->sqloss, rpt0->lockbit,
-+				 rpt0->raterr, rpt0->rxrate, rpt0->lna_h_a,
-+				 rpt0->bb_power_a, rpt0->lna_l_a, rpt0->vga_a,
-+				 rpt0->signal_quality);
-+			pr_debug("[16] Gain_b=%d, lna_h_b=%d, CCK_BB_power_b=%d, lna_l_b=%d, vga_b=%d, Pwdb_b=%d\n",
-+				 rpt0->gain_b, rpt0->lna_h_b, rpt0->bb_power_b,
-+				 rpt0->lna_l_b, rpt0->vga_b, rpt0->pwdb_b);
-+			pr_debug("[20] Gain_c=%d, lna_h_c=%d, CCK_BB_power_c=%d, lna_l_c=%d, vga_c=%d, Pwdb_c=%d\n",
-+				 rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c,
-+				 rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c);
-+			pr_debug("[24] Gain_d=%d, lna_h_d=%d, CCK_BB_power_d=%d, lna_l_d=%d, vga_d=%d, Pwdb_d=%d\n",
-+				 rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c,
-+				 rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c);
-+		}
-+	} else if (phy_status_page_num == 1) {
-+		pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_pri_msb=%d, Pkt_cnt=%d,\n",
-+			 rpt1->pwdb_c, rpt1->pwdb_b, rpt1->pwdb_a,
-+			 rpt1->channel_pri_msb, rpt1->pkt_cnt);
-+		pr_debug("[4] BF: %d, stbc=%d, ldpc=%d, gnt_bt=%d, band=%d, Ch_pri_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb[D]=%d\n",
-+			 rpt1->beamformed, rpt1->stbc, rpt1->ldpc, rpt1->gnt_bt,
-+			 rpt1->band, rpt1->channel_pri_lsb, rpt1->ht_rxsc,
-+			 rpt1->l_rxsc, rpt1->pwdb_d);
-+		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}, Channel_sec[msb,lsb]={%d, %d}\n",
-+			 rpt1->antidx_d, rpt1->antidx_c,
-+			 rpt1->antidx_b, rpt1->antidx_a,
-+			 rpt1->hw_antsw_occur_d, rpt1->hw_antsw_occur_c,
-+			 rpt1->hw_antsw_occur_b, rpt1->hw_antsw_occur_a,
-+			 rpt1->channel_sec_msb, rpt1->channel_sec_lsb);
-+		pr_debug("[12] GID=%d, PAID[msb,lsb]={%d,%d}\n",
-+			 rpt1->gid, rpt1->paid_msb, rpt1->paid);
-+		pr_debug("[16] RX_EVM[D:A]={%d, %d, %d, %d}\n",
-+			 rpt1->rxevm[3], rpt1->rxevm[2],
-+			 rpt1->rxevm[1], rpt1->rxevm[0]);
-+		pr_debug("[20] CFO_tail[D:A]={%d, %d, %d, %d}\n",
-+			 rpt1->cfo_tail[3], rpt1->cfo_tail[2],
-+			 rpt1->cfo_tail[1], rpt1->cfo_tail[0]);
-+		pr_debug("[24] RX_SNR[D:A]={%d, %d, %d, %d}\n\n",
-+			 rpt1->rxsnr[3], rpt1->rxsnr[2],
-+			 rpt1->rxsnr[1], rpt1->rxsnr[0]);
-+	} else if (phy_status_page_num == 2 || phy_status_page_num == 3) {
-+		pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
-+			 rpt2->pwdb[2], rpt2->pwdb[1], rpt2->pwdb[0],
-+			 rpt2->channel_msb, rpt2->pkt_cnt);
-+		pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, Gnt_BT=%d, band=%d, CH_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
-+			 rpt2->beamformed, rpt2->stbc, rpt2->ldpc, rpt2->gnt_bt,
-+			 rpt2->band, rpt2->channel_lsb,
-+			 rpt2->ht_rxsc, rpt2->l_rxsc, rpt2->pwdb[3]);
-+		pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, pwed_th=%d, shift_l_map=%d\n",
-+			 rpt2->agc_table_d, rpt2->agc_table_c,
-+			 rpt2->agc_table_b, rpt2->agc_table_a,
-+			 rpt2->pwed_th, rpt2->shift_l_map);
-+		pr_debug("[12] AvgNoisePowerdB=%d, mp_gain_c[msb, lsb]={%d, %d}, mp_gain_b[msb, lsb]={%d, %d}, mp_gain_a=%d, cnt_cca2agc_rdy=%d\n",
-+			 rpt2->avg_noise_pwr_lsb, rpt2->mp_gain_c_msb,
-+			 rpt2->mp_gain_c_lsb, rpt2->mp_gain_b_msb,
-+			 rpt2->mp_gain_b_lsb, rpt2->mp_gain_a,
-+			 rpt2->cnt_cca2agc_rdy);
-+		pr_debug("[16] HT AAGC gain[B:A]={%d, %d}, AAGC step[D:A]={%d, %d, %d, %d}, IsFreqSelectFadimg=%d, mp_gain_d=%d\n",
-+			 rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0],
-+			 rpt2->aagc_step_d, rpt2->aagc_step_c,
-+			 rpt2->aagc_step_b, rpt2->aagc_step_a,
-+			 rpt2->is_freq_select_fading, rpt2->mp_gain_d);
-+		pr_debug("[20] DAGC gain ant[B:A]={%d, %d}, HT AAGC gain[D:C]={%d, %d}\n",
-+			 rpt2->dagc_gain[1], rpt2->dagc_gain[0],
-+			 rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2]);
-+		pr_debug("[24] AvgNoisePwerdB=%d, syn_count[msb, lsb]={%d, %d}, counter=%d, DAGC gain ant[D:C]={%d, %d}\n",
-+			 rpt2->avg_noise_pwr_msb, rpt2->syn_count_msb,
-+			 rpt2->syn_count_lsb, rpt2->counter,
-+			 rpt2->dagc_gain[3], rpt2->dagc_gain[2]);
-+	} else if (phy_status_page_num == 4) { /*type 4*/
-+		pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
-+			 rpt3->pwdb[2], rpt3->pwdb[1], rpt3->pwdb[0],
-+			 rpt3->channel_msb, rpt3->pkt_cnt);
-+		pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
-+			 rpt3->beamformed, rpt3->stbc, rpt3->ldpc, rpt3->gnt_bt,
-+			 rpt3->band, rpt3->channel_lsb, rpt3->ht_rxsc,
-+			 rpt3->l_rxsc, rpt3->pwdb[3]);
-+		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}, Training_done[D:A]={%d, %d, %d, %d},\n    BadToneCnt_CN_excess_0=%d, BadToneCnt_min_eign_0=%d\n",
-+			 rpt3->antidx_d, rpt3->antidx_c,
-+			 rpt3->antidx_b, rpt3->antidx_a,
-+			 rpt3->hw_antsw_occur_d, rpt3->hw_antsw_occur_c,
-+			 rpt3->hw_antsw_occur_b, rpt3->hw_antsw_occur_a,
-+			 rpt3->training_done_d, rpt3->training_done_c,
-+			 rpt3->training_done_b, rpt3->training_done_a,
-+			 rpt3->bad_tone_cnt_cn_excess_0,
-+			 rpt3->bad_tone_cnt_min_eign_0);
-+		pr_debug("[12] avg_cond_num_1=%d, avg_cond_num_0=%d, bad_tone_cnt_cn_excess_1=%d,\n     bad_tone_cnt_min_eign_1=%d, Tx_pkt_cnt=%d\n",
-+			 ((rpt3->avg_cond_num_1_msb << 1) |
-+			 rpt3->avg_cond_num_1_lsb),
-+			 rpt3->avg_cond_num_0, rpt3->bad_tone_cnt_cn_excess_1,
-+			 rpt3->bad_tone_cnt_min_eign_1, rpt3->tx_pkt_cnt);
-+		pr_debug("[16] Stream RXEVM[D:A]={%d, %d, %d, %d}\n",
-+			 rpt3->rxevm[3], rpt3->rxevm[2],
-+			 rpt3->rxevm[1], rpt3->rxevm[0]);
-+		pr_debug("[20] Eigenvalue[D:A]={%d, %d, %d, %d}\n",
-+			 rpt3->eigenvalue[3], rpt3->eigenvalue[2],
-+			 rpt3->eigenvalue[1], rpt3->eigenvalue[0]);
-+		pr_debug("[24] RX SNR[D:A]={%d, %d, %d, %d}\n",
-+			 rpt3->rxsnr[3], rpt3->rxsnr[2],
-+			 rpt3->rxsnr[1], rpt3->rxsnr[0]);
-+	} else if (phy_status_page_num == 5) { /*type 5*/
-+		pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n",
-+			 rpt4->pwdb[2], rpt4->pwdb[1], rpt4->pwdb[0],
-+			 rpt4->channel_msb, rpt4->pkt_cnt);
-+		pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n",
-+			 rpt4->beamformed, rpt4->stbc, rpt4->ldpc, rpt4->gnt_bt,
-+			 rpt4->band, rpt4->channel_lsb, rpt4->ht_rxsc,
-+			 rpt4->l_rxsc, rpt4->pwdb[3]);
-+		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}\n",
-+			 rpt4->antidx_d, rpt4->antidx_c,
-+			 rpt4->antidx_b, rpt4->antidx_a,
-+			 rpt4->hw_antsw_occur_d, rpt4->hw_antsw_occur_c,
-+			 rpt4->hw_antsw_occur_b, rpt4->hw_antsw_occur_a);
-+		pr_debug("[12] Inf_posD[1,0]={%d, %d}, Inf_posC[1,0]={%d, %d}, Inf_posB[1,0]={%d, %d}, Inf_posA[1,0]={%d, %d}, Tx_pkt_cnt=%d\n",
-+			 rpt4->inf_pos_1_D_flg, rpt4->inf_pos_0_D_flg,
-+			 rpt4->inf_pos_1_C_flg, rpt4->inf_pos_0_C_flg,
-+			 rpt4->inf_pos_1_B_flg, rpt4->inf_pos_0_B_flg,
-+			 rpt4->inf_pos_1_A_flg, rpt4->inf_pos_0_A_flg,
-+			 rpt4->tx_pkt_cnt);
-+		pr_debug("[16] Inf_pos_B[1,0]={%d, %d}, Inf_pos_A[1,0]={%d, %d}\n",
-+			 rpt4->inf_pos_1_b, rpt4->inf_pos_0_b,
-+			 rpt4->inf_pos_1_a, rpt4->inf_pos_0_a);
-+		pr_debug("[20] Inf_pos_D[1,0]={%d, %d}, Inf_pos_C[1,0]={%d, %d}\n",
-+			 rpt4->inf_pos_1_d, rpt4->inf_pos_0_d,
-+			 rpt4->inf_pos_1_c, rpt4->inf_pos_0_c);
-+	}
-+}
-+
-+void phydm_reset_phy_info_jgr3(struct dm_struct *phydm,
-+			       struct phydm_phyinfo_struct *phy_info)
-+{
-+	u8 i;
-+
-+	phy_info->rx_pwdb_all = 0;
-+	phy_info->signal_quality = 0;
-+	phy_info->band_width = 0;
-+	phy_info->rx_count = 0;
-+	phy_info->rx_power = -110;
-+	phy_info->recv_signal_power = -110;
-+	phy_info->bt_rx_rssi_percentage = 0;
-+	phy_info->signal_strength = 0;
-+	phy_info->channel = 0;
-+	phy_info->is_mu_packet = 0;
-+	phy_info->is_beamformed = 0;
-+	phy_info->rxsc = 0;
-+
-+	for (i = 0; i < 4; i++) {
-+		phy_info->rx_mimo_signal_strength[i] = 0;
-+		phy_info->rx_mimo_signal_quality[i] = 0;
-+		phy_info->rx_mimo_evm_dbm[i] = 0;
-+		phy_info->cfo_short[i] = 0;
-+		phy_info->cfo_tail[i] = 0;
-+		phy_info->rx_pwr[i] = -110;
-+		phy_info->rx_snr[i] = 0;
-+	}
-+}
-+
-+#if 0
-+void phydm_per_path_info_3rd(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail,
-+			     s8 rx_snr, struct phydm_phyinfo_struct *phy_info)
-+{
-+	u8 evm_dbm = 0;
-+	u8 evm_percentage = 0;
-+
-+	/* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */
-+
-+	evm_dbm = (rx_evm == -128) ? 0 : ((u8)(0 - rx_evm) >> 1);
-+	evm_percentage = (evm_dbm >= 34) ? 100 : evm_dbm * 3;
-+
-+	phy_info->rx_pwr[rx_path] = pwr;
-+
-+	/*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/
-+	phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1;
-+	phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
-+	phy_info->rx_mimo_signal_strength[rx_path] = phydm_pw_2_percent(pwr);
-+	phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
-+	phy_info->rx_snr[rx_path] = rx_snr >> 1;
-+}
-+
-+void phydm_common_phy_info_jgr3(s8 rx_power, u8 channel, boolean is_beamformed,
-+				boolean is_mu_packet, u8 bandwidth,
-+				u8 signal_quality, u8 rxsc,
-+				struct phydm_phyinfo_struct *phy_info)
-+{
-+	phy_info->rx_power = rx_power; /* RSSI in dB */
-+	phy_info->recv_signal_power = rx_power; /* RSSI in dB */
-+	phy_info->channel = channel; /* @channel number */
-+	phy_info->is_beamformed = is_beamformed; /* @apply BF */
-+	phy_info->is_mu_packet = is_mu_packet; /* @MU packet */
-+	phy_info->rxsc = rxsc;
-+
-+	phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_power); /*percentage */
-+	phy_info->signal_quality = signal_quality; /* signal quality */
-+	phy_info->band_width = bandwidth; /* @bandwidth */
-+}
-+#endif
-+
-+void phydm_get_physts_0_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
-+			     struct phydm_perpkt_info_struct *pktinfo,
-+			     struct phydm_phyinfo_struct *phy_info)
-+{
-+	/* type 0 is used for cck packet */
-+	struct phy_sts_rpt_jgr3_type0 *phy_sts = NULL;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	u8 sq = 0, i, rx_cnt = 0;
-+	s8 rx_power[4], pwdb;
-+	s8 rx_pwr_db_max = -120;
-+
-+	phy_sts = (struct phy_sts_rpt_jgr3_type0 *)phy_status_inf;
-+
-+	#if (RTL8197G_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197G) {
-+		if (dm->rx_ant_status == BB_PATH_B) {
-+			phy_sts->pwdb_b = phy_sts->pwdb_a;
-+			phy_sts->gain_b = phy_sts->gain_a;
-+			phy_sts->pwdb_a = 0;
-+			phy_sts->gain_a = 0;
-+		}
-+	}
-+	#endif
-+
-+	rx_power[0] = phy_sts->pwdb_a;
-+	rx_power[1] = phy_sts->pwdb_b;
-+	rx_power[2] = phy_sts->pwdb_c;
-+	rx_power[3] = phy_sts->pwdb_d;
-+
-+	#if (RTL8822C_SUPPORT || RTL8197G_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8197G)) {
-+		struct phydm_physts *physts_table = &dm->dm_physts_table;
-+		if (phy_sts->gain_a < physts_table->cck_gi_l_bnd)
-+			rx_power[0] += ((physts_table->cck_gi_l_bnd -
-+					phy_sts->gain_a) << 1);
-+		else if (phy_sts->gain_a > physts_table->cck_gi_u_bnd)
-+			rx_power[0] -= ((phy_sts->gain_a -
-+					physts_table->cck_gi_u_bnd) << 1);
-+
-+		if (phy_sts->gain_b < physts_table->cck_gi_l_bnd)
-+			rx_power[1] += ((physts_table->cck_gi_l_bnd -
-+					phy_sts->gain_b) << 1);
-+		else if (phy_sts->gain_b > physts_table->cck_gi_u_bnd)
-+			rx_power[1] -= ((phy_sts->gain_b -
-+					physts_table->cck_gi_u_bnd) << 1);
-+	}
-+	#endif
-+
-+	/* @Update per-path information */
-+	for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
-+		if ((dm->rx_ant_status & BIT(i)) == 0)
-+			continue;
-+
-+		rx_cnt++; /* @check the number of the ant */
-+
-+		if (rx_cnt > dm->num_rf_path)
-+			break;
-+
-+		if (pktinfo->is_to_self)
-+			dm->ofdm_agc_idx[i] = rx_power[i];
-+
-+		/* @Setting the RX power: agc_idx -110 dBm*/
-+		pwdb = rx_power[i] - 110;
-+
-+		phy_info->rx_pwr[i] = pwdb;
-+		phy_info->rx_mimo_signal_strength[i] = phydm_pw_2_percent(pwdb);
-+
-+		/* search maximum pwdb */
-+		if (pwdb > rx_pwr_db_max)
-+			rx_pwr_db_max = pwdb;
-+	}
-+
-+	/* @Calculate Signal Quality*/
-+	if (phy_sts->signal_quality >= 64) {
-+		sq = 0;
-+	} else if (phy_sts->signal_quality <= 20) {
-+		sq = 100;
-+	} else {
-+		/* @mapping to 2~99% */
-+		sq = 64 - phy_sts->signal_quality;
-+		sq = ((sq << 3) + sq) >> 2;
-+	}
-+
-+	/* @Modify CCK PWDB if old AGC */
-+	if (!dm->cck_new_agc) {
-+		u8 lna_idx[4], vga_idx[4];
-+
-+		lna_idx[0] = ((phy_sts->lna_h_a << 3) | phy_sts->lna_l_a);
-+		vga_idx[0] = phy_sts->vga_a;
-+		lna_idx[1] = ((phy_sts->lna_h_b << 3) | phy_sts->lna_l_b);
-+		vga_idx[1] = phy_sts->vga_b;
-+		lna_idx[2] = ((phy_sts->lna_h_c << 3) | phy_sts->lna_l_c);
-+		vga_idx[2] = phy_sts->vga_c;
-+		lna_idx[3] = ((phy_sts->lna_h_d << 3) | phy_sts->lna_l_d);
-+		vga_idx[3] = phy_sts->vga_d;
-+	}
-+
-+	/*@CCK no STBC and LDPC*/
-+	dbg_i->is_ldpc_pkt = false;
-+	dbg_i->is_stbc_pkt = false;
-+
-+	/*cck channel has hw bug, [WLANBB-1429]*/
-+	phy_info->channel = 0;
-+	phy_info->rx_power = rx_pwr_db_max;
-+	phy_info->recv_signal_power = rx_pwr_db_max;
-+	phy_info->is_beamformed = false;
-+	phy_info->is_mu_packet = false;
-+	phy_info->rxsc = phy_sts->l_rxsc;
-+	phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db_max);
-+	phy_info->signal_quality = sq;
-+	phy_info->band_width = CHANNEL_WIDTH_20;
-+
-+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
-+	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
-+	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
-+	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
-+	#endif
-+}
-+
-+void phydm_get_physts_1_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
-+				    struct phydm_perpkt_info_struct *pktinfo,
-+				    struct phydm_phyinfo_struct *phy_info)
-+{
-+	struct phy_sts_rpt_jgr3_type1 *phy_sts = NULL;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	s8 evm = 0;
-+	u8 i;
-+	s8 sq = 0;
-+
-+	phy_sts = (struct phy_sts_rpt_jgr3_type1 *)phy_status_inf;
-+
-+	/* SNR: S(8,1), EVM: S(8,1), CFO: S(8,7) */
-+
-+	for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
-+		if ((dm->rx_ant_status & BIT(i)) == 0)
-+			continue;
-+
-+		evm = phy_sts->rxevm[i];
-+		evm = (evm == -128) ? 0 : ((0 - evm) >> 1);
-+		sq = (evm >= 34) ? 100 : evm * 3; /* @Convert EVM to 0~100%*/
-+
-+		phy_info->rx_mimo_evm_dbm[i] = (u8)evm;
-+		phy_info->rx_mimo_signal_quality[i] = sq;
-+		phy_info->rx_snr[i] = phy_sts->rxsnr[i] >> 1;
-+		/*@CFO(kHz) = CFO_tail*312.5(kHz)/2^7 ~= CFO tail * 5/2 (kHz)*/
-+		phy_info->cfo_tail[i] = (phy_sts->cfo_tail[i] * 5) >> 1;
-+		dbg_i->cfo_tail[i] = (phy_sts->cfo_tail[i] * 5) >> 1;
-+	}
-+	phy_info->signal_quality = phy_info->rx_mimo_signal_quality[0];
-+
-+	if (phy_sts->gid != 0 && phy_sts->gid != 63) {
-+		phy_info->is_mu_packet = true;
-+		dbg_i->num_qry_mu_pkt++;
-+	} else {
-+		phy_info->is_mu_packet = false;
-+	}
-+
-+	phydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss);
-+
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
-+	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
-+	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
-+	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
-+#endif
-+}
-+
-+void phydm_get_physts_2_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
-+				    struct phydm_perpkt_info_struct *pktinfo,
-+				    struct phydm_phyinfo_struct *phy_info)
-+{
-+	/* type 2 & 3 is used for ofdm packet */
-+	struct phy_sts_rpt_jgr3_type2_3 *phy_sts = NULL;
-+}
-+
-+void phydm_get_physts_4_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
-+				    struct phydm_perpkt_info_struct *pktinfo,
-+				    struct phydm_phyinfo_struct *phy_info)
-+{
-+	struct phy_sts_rpt_jgr3_type4 *phy_sts = NULL;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	s8 evm = 0;
-+	u8 i;
-+	s8 sq = 0;
-+
-+	phy_sts = (struct phy_sts_rpt_jgr3_type4 *)phy_status_inf;
-+
-+	/* SNR: S(8,1), EVM: S(8,1), CFO: S(8,7) */
-+
-+	for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
-+		if ((dm->rx_ant_status & BIT(i)) == 0)
-+			continue;
-+
-+		evm = phy_sts->rxevm[i];
-+		evm = (evm == -128) ? 0 : ((0 - evm) >> 1);
-+		sq = (evm >= 34) ? 100 : evm * 3; /* @Convert EVM to 0~100%*/
-+
-+		phy_info->rx_mimo_evm_dbm[i] = (u8)evm;
-+		phy_info->rx_mimo_signal_quality[i] = sq;
-+		phy_info->rx_snr[i] = phy_sts->rxsnr[i] >> 1;
-+	}
-+	phy_info->signal_quality = phy_info->rx_mimo_signal_quality[0];
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
-+	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
-+	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
-+	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
-+#endif
-+	odm_move_memory(dm, dbg_i->eigen_val, phy_sts->eigenvalue, 4);
-+	dbg_i->condition_num_seg0 = phy_sts->avg_cond_num_0;
-+}
-+
-+void phydm_get_physts_5_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
-+				    struct phydm_perpkt_info_struct *pktinfo,
-+				    struct phydm_phyinfo_struct *phy_info)
-+{
-+	struct phy_sts_rpt_jgr3_type5 *phy_sts = NULL;
-+
-+}
-+#if (RTL8723F_SUPPORT)
-+void phydm_get_physts_6_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
-+			     struct phydm_perpkt_info_struct *pktinfo,
-+			     struct phydm_phyinfo_struct *phy_info)
-+{
-+	/* type 0 is used for cck packet */
-+	struct phy_sts_rpt_jgr3_type6 *phy_sts = NULL;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	u8 sq = 0, i, rx_cnt = 0;
-+	s8 rx_power[4], pwdb;
-+	s8 rx_pwr_db_max = -120;
-+	u8 evm = 0;
-+	phy_sts = (struct phy_sts_rpt_jgr3_type6 *)phy_status_inf;
-+	/* judy_add_8723F_0512 */
-+	/* rssi S(11,3) */
-+	rx_power[0] = (s8)((phy_sts->rssi_msb << 5) + (phy_sts->rssi >> 3));
-+	/* @Update per-path information */
-+	for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
-+		if ((dm->rx_ant_status & BIT(i)) == 0)
-+			continue;
-+
-+		rx_cnt++; /* @check the number of the ant */
-+
-+		if (rx_cnt > dm->num_rf_path)
-+			break;
-+
-+		if (pktinfo->is_to_self)
-+			dm->ofdm_agc_idx[i] = rx_power[i]+110;
-+
-+		/* @Setting the RX power: agc_idx dBm*/
-+		pwdb = rx_power[i];
-+
-+		phy_info->rx_pwr[i] = pwdb;
-+		phy_info->rx_mimo_signal_strength[i] = phydm_pw_2_percent(pwdb);
-+
-+		/* search maximum pwdb */
-+		if (pwdb > rx_pwr_db_max)
-+			rx_pwr_db_max = pwdb;
-+	}
-+	
-+	/* @Calculate EVM U(8,2)*/
-+	evm = phy_sts->evm_pld >> 2;
-+	if (pktinfo->data_rate > ODM_RATE2M)
-+		phy_info->rx_cck_evm = (u8)(evm - 10);/* @5_5M/11M*/
-+	else
-+		phy_info->rx_cck_evm = (u8)(evm - 12);/* @1M/2M*/
-+
-+	sq = (phy_info->rx_cck_evm >= 34) ? 100 : phy_info->rx_cck_evm * 3;
-+	phy_info->signal_quality = sq;
-+	/*@CCK no STBC and LDPC*/
-+	dbg_i->is_ldpc_pkt = false;
-+	dbg_i->is_stbc_pkt = false;
-+
-+	/*cck channel has hw bug, [WLANBB-1429]*/
-+	phy_info->channel = 0;
-+	phy_info->rx_power = rx_pwr_db_max;
-+	phy_info->recv_signal_power = rx_pwr_db_max;
-+	phy_info->is_beamformed = false;
-+	phy_info->is_mu_packet = false;
-+	phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db_max);
-+	phy_info->band_width = CHANNEL_WIDTH_20;
-+	
-+	//phydm_parsing_cfo(dm, pktinfo, phy_sts->avg_cfo, pktinfo->rate_ss);
-+	
-+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
-+	dm->dm_fat_table.antsel_rx_keep_1 = 0;
-+	dm->dm_fat_table.antsel_rx_keep_2 = 0;
-+	dm->dm_fat_table.antsel_rx_keep_3 = 0;
-+	#endif
-+}
-+#endif
-+void phydm_get_physts_ofdm_cmn_jgr3(struct dm_struct *dm, u8 *phy_status_inf,
-+				    struct phydm_perpkt_info_struct *pktinfo,
-+				    struct phydm_phyinfo_struct *phy_info)
-+{
-+	struct phy_sts_rpt_jgr3_ofdm_cmn *phy_sts = NULL;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	s8 rx_pwr_db_max = -120;
-+	s8 pwdb = 0;
-+	u8 i, rx_cnt = 0;
-+
-+	phy_sts = (struct phy_sts_rpt_jgr3_ofdm_cmn *)phy_status_inf;
-+
-+	/* Parsing Offset0 & 4*/
-+	for (i = RF_PATH_A; i < dm->num_rf_path; i++) {
-+		if ((dm->rx_ant_status & BIT(i)) == 0)
-+			continue;
-+
-+		rx_cnt++; /* @check the number of the ant */
-+
-+		pwdb = (s8)phy_sts->pwdb[i] - 110; /*@dB*/
-+
-+		if (pktinfo->is_to_self)
-+			dm->ofdm_agc_idx[i] = phy_sts->pwdb[i];
-+
-+		/* search maximum pwdb */
-+		if (pwdb > rx_pwr_db_max)
-+			rx_pwr_db_max = pwdb;
-+
-+		phy_info->rx_pwr[i] = pwdb;
-+		phy_info->rx_mimo_signal_strength[i] = phydm_pw_2_percent(pwdb);
-+	}
-+
-+	phy_info->rx_count = (rx_cnt > 0) ? rx_cnt - 1 : 0; /*from 1~4 to 0~3 */
-+	phy_info->rx_power = rx_pwr_db_max;
-+	phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db_max);
-+	phy_info->recv_signal_power = rx_pwr_db_max;
-+	phy_info->channel = phy_sts->channel_lsb;
-+	phy_info->is_beamformed = (boolean)phy_sts->beamformed;
-+	phy_info->rxsc = (PHYDM_IS_LEGACY_RATE(pktinfo->data_rate)) ?
-+			  phy_sts->l_rxsc : phy_sts->ht_rxsc;
-+	phy_info->band_width = phydm_rxsc_2_bw(dm, phy_info->rxsc);
-+
-+	dbg_i->is_ldpc_pkt = phy_sts->ldpc;
-+	dbg_i->is_stbc_pkt = phy_sts->stbc;
-+	dbg_i->num_qry_bf_pkt += phy_sts->beamformed;
-+}
-+
-+void phydm_process_dm_rssi_jgr3(struct dm_struct *dm,
-+				struct phydm_phyinfo_struct *phy_info,
-+				struct phydm_perpkt_info_struct *pktinfo)
-+{
-+	struct cmn_sta_info *sta = NULL;
-+	struct rssi_info *rssi_t = NULL;
-+	u8 rssi_tmp = 0;
-+	u64 rssi_linear = 0;
-+	s16 rssi_db = 0;
-+	u8 i = 0;
-+	u8 rx_count = 0;
-+
-+	#if (defined(PHYDM_CCK_RX_PATHDIV_SUPPORT))
-+	struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
-+	#endif
-+
-+	/*@[Step4]*/
-+	if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
-+		return;
-+
-+	sta = dm->phydm_sta_info[pktinfo->station_id];
-+
-+	if (!is_sta_active(sta))
-+		return;
-+
-+	if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
-+		return;
-+
-+	if (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon))
-+		return;
-+
-+	if (pktinfo->is_packet_beacon) {
-+		dm->phy_dbg_info.num_qry_beacon_pkt++;
-+		dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
-+	}
-+
-+	#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+	if (dm->support_ability & ODM_BB_ANT_DIV)
-+		odm_process_rssi_for_ant_div(dm, phy_info, pktinfo);
-+	#endif
-+
-+	#ifdef ODM_EVM_ENHANCE_ANTDIV
-+	phydm_rx_rate_for_antdiv(dm, pktinfo);
-+	#endif
-+
-+	#if (defined(CONFIG_PATH_DIVERSITY))
-+	if (dm->support_ability & ODM_BB_PATH_DIV)
-+		phydm_process_rssi_for_path_div(dm, phy_info, pktinfo);
-+	#endif
-+
-+	#if (defined(PHYDM_CCK_RX_PATHDIV_SUPPORT))
-+	if (cckrx_t->en_cck_rx_pathdiv)
-+		phydm_process_rssi_for_cck_rx_pathdiv(dm, phy_info, pktinfo);
-+	#endif
-+
-+	rssi_t = &sta->rssi_stat;
-+
-+	for (i = 0; i < dm->num_rf_path; i++) {
-+		rssi_tmp = phy_info->rx_mimo_signal_strength[i];
-+		if (rssi_tmp != 0) {
-+			rx_count++;
-+			rssi_linear += phydm_db_2_linear(rssi_tmp);
-+		}
-+	}
-+	/* @Rounding and removing fractional bits */
-+	rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
-+
-+	switch (rx_count) {
-+	case 2:
-+		rssi_linear = DIVIDED_2(rssi_linear);
-+		break;
-+	case 3:
-+		rssi_linear = DIVIDED_3(rssi_linear);
-+		break;
-+	case 4:
-+		rssi_linear = DIVIDED_4(rssi_linear);
-+		break;
-+	}
-+
-+	rssi_db = (s16)odm_convert_to_db(rssi_linear);
-+
-+	if (rssi_t->rssi_acc == 0) {
-+		rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA);
-+		rssi_t->rssi = (s8)(rssi_db);
-+	} else {
-+		rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, rssi_db, RSSI_MA);
-+		rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, RSSI_MA);
-+	}
-+
-+	if (pktinfo->is_cck_rate)
-+		rssi_t->rssi_cck = (s8)rssi_db;
-+	else
-+		rssi_t->rssi_ofdm = (s8)rssi_db;
-+}
-+
-+void phydm_rx_physts_jgr3(void *dm_void, u8 *phy_sts,
-+			  struct phydm_perpkt_info_struct *pktinfo,
-+			  struct phydm_phyinfo_struct *phy_info)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 phy_status_type = (*phy_sts & 0xf);
-+	if (dm->support_ic_type & ODM_RTL8723F) {
-+		if (pktinfo->data_rate <= ODM_RATE11M)
-+			phy_status_type = 6;
-+	}
-+	/*@[Step 2]*/
-+	/*phydm_reset_phy_info_jgr3(dm, phy_info);*/ /* @Memory reset */
-+
-+	/* Phy status parsing */
-+	switch (phy_status_type) {
-+	case 0: /*@CCK*/
-+		phydm_get_physts_0_jgr3(dm, phy_sts, pktinfo, phy_info);
-+		break;
-+	case 1:
-+		phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
-+		phydm_get_physts_1_others_jgr3(dm, phy_sts, pktinfo, phy_info);
-+		break;
-+	case 2:
-+	case 3:
-+		phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
-+		phydm_get_physts_2_others_jgr3(dm, phy_sts, pktinfo, phy_info);
-+		break;
-+	case 4:
-+		phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
-+		phydm_get_physts_4_others_jgr3(dm, phy_sts, pktinfo, phy_info);
-+		break;
-+	case 5:
-+		phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info);
-+		phydm_get_physts_5_others_jgr3(dm, phy_sts, pktinfo, phy_info);
-+		break;
-+#if (RTL8723F_SUPPORT)
-+	case 6:
-+		phydm_get_physts_6_jgr3(dm, phy_sts, pktinfo, phy_info);
-+		break;
-+#endif
-+	default:
-+		break;
-+	}
-+
-+#if 0
-+	PHYDM_DBG(dm, DBG_PHY_STATUS, "RSSI: {%d, %d}\n",
-+		  phy_info->rx_mimo_signal_strength[0],
-+		  phy_info->rx_mimo_signal_strength[1]);
-+	PHYDM_DBG(dm, DBG_PHY_STATUS, "rxdb: {%d, %d}\n",
-+		  phy_info->rx_pwr[0], phy_info->rx_pwr[1]);
-+	PHYDM_DBG(dm, DBG_PHY_STATUS, "EVM: {%d, %d}\n",
-+		  phy_info->rx_mimo_evm_dbm[0], phy_info->rx_mimo_evm_dbm[1]);
-+	PHYDM_DBG(dm, DBG_PHY_STATUS, "SQ: {%d, %d}\n",
-+		  phy_info->rx_mimo_signal_quality[0],
-+		  phy_info->rx_mimo_signal_quality[1]);
-+	PHYDM_DBG(dm, DBG_PHY_STATUS, "SNR: {%d, %d}\n",
-+		  phy_info->rx_snr[0], phy_info->rx_snr[1]);
-+	PHYDM_DBG(dm, DBG_PHY_STATUS, "CFO: {%d, %d}\n",
-+		  phy_info->cfo_tail[0], phy_info->cfo_tail[1]);
-+	PHYDM_DBG(dm, DBG_PHY_STATUS,
-+		  "rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n",
-+		  phy_info->rx_pwdb_all, phy_info->rx_power,
-+		  phy_info->recv_signal_power);
-+	PHYDM_DBG(dm, DBG_PHY_STATUS, "signal_quality = %d\n",
-+		  phy_info->signal_quality);
-+	PHYDM_DBG(dm, DBG_PHY_STATUS,
-+		  "is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n",
-+		  phy_info->is_beamformed, phy_info->is_mu_packet,
-+		  phy_info->rx_count);
-+	PHYDM_DBG(dm, DBG_PHY_STATUS,
-+		  "channel = %d, rxsc = %d, band_width = %d\n",
-+		  phy_info->channel, phy_info->rxsc, phy_info->band_width);
-+#endif
-+
-+	/*@[Step 1]*/
-+	phydm_print_phystat_jgr3(dm, phy_sts, pktinfo, phy_info);
-+}
-+
-+#endif
-+
-+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
-+/* @For 8822B only!! need to move to FW finally */
-+/*@==============================================*/
-+
-+boolean
-+phydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate,
-+		      u8 *p_gid)
-+{
-+	u8 data_rate = 0, gid = 0;
-+	boolean is_mu = false;
-+
-+	data_rate = phydm->phy_dbg_info.num_of_ppdu[ppdu_idx];
-+	gid = phydm->phy_dbg_info.gid_num[ppdu_idx];
-+
-+	if (data_rate & BIT(7)) {
-+		is_mu = true;
-+		data_rate = data_rate & ~(BIT(7));
-+	} else {
-+		is_mu = false;
-+	}
-+
-+	*p_data_rate = data_rate;
-+	*p_gid = gid;
-+
-+	return is_mu;
-+}
-+
-+void phydm_print_phy_sts_jgr2(struct dm_struct *dm, u8 *phy_status_inf,
-+			      struct phydm_perpkt_info_struct *pktinfo,
-+			      struct phydm_phyinfo_struct *phy_info)
-+{
-+	struct phy_sts_rpt_jgr2_type0 *rpt0 = NULL;
-+	struct phy_sts_rpt_jgr2_type1 *rpt = NULL;
-+	struct phy_sts_rpt_jgr2_type2 *rpt2 = NULL;
-+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
-+	u8 phy_status_page_num = (*phy_status_inf & 0xf);
-+	u32 phy_status[PHY_STATUS_JRGUAR2_DW_LEN] = {0};
-+	u8 i;
-+	u32 size = PHY_STATUS_JRGUAR2_DW_LEN << 2;
-+
-+	rpt0 = (struct phy_sts_rpt_jgr2_type0 *)phy_status_inf;
-+	rpt = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;
-+	rpt2 = (struct phy_sts_rpt_jgr2_type2 *)phy_status_inf;
-+
-+	odm_move_memory(dm, phy_status, phy_status_inf, size);
-+
-+	if (!(dm->debug_components & DBG_PHY_STATUS))
-+		return;
-+
-+	if (dbg->show_phy_sts_all_pkt == 0) {
-+		if (!pktinfo->is_packet_match_bssid)
-+			return;
-+	}
-+
-+	dbg->show_phy_sts_cnt++;
-+	#if 0
-+	dbg_print("cnt=%d, max=%d\n",
-+		  dbg->show_phy_sts_cnt, dbg->show_phy_sts_max_cnt);
-+	#endif
-+
-+	if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) {
-+		if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt)
-+			return;
-+	}
-+
-+	pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num);
-+	pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d\n",
-+		 pktinfo->station_id, pktinfo->data_rate,
-+		 pktinfo->is_packet_match_bssid);
-+
-+	for (i = 0; i < PHY_STATUS_JRGUAR2_DW_LEN; i++)
-+		pr_debug("Offset[%d:%d] = 0x%x\n",
-+			 ((4 * i) + 3), (4 * i), phy_status[i]);
-+
-+	if (phy_status_page_num == 0) {
-+		pr_debug("[0] TRSW=%d, MP_gain_idx=%d, pwdb=%d\n",
-+			 rpt0->trsw, rpt0->gain, rpt0->pwdb);
-+		pr_debug("[4] band=%d, CH=%d, agc_table = %d, rxsc = %d\n",
-+			 rpt0->band, rpt0->channel,
-+			 rpt0->agc_table, rpt0->rxsc);
-+		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n",
-+			 rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b,
-+			 rpt0->antidx_a, rpt0->length);
-+		pr_debug("[12] lna_h=%d, bb_pwr=%d, lna_l=%d, vga=%d, sq=%d\n",
-+			 rpt0->lna_h, rpt0->bb_power, rpt0->lna_l,
-+			 rpt0->vga, rpt0->signal_quality);
-+
-+	} else if (phy_status_page_num == 1) {
-+		pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n",
-+			 rpt->pwdb[3], rpt->pwdb[2],
-+			 rpt->pwdb[1], rpt->pwdb[0]);
-+		pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht, l]={%d, %d}\n",
-+			 rpt->beamformed, rpt->ldpc, rpt->stbc, rpt->gnt_bt,
-+			 rpt->hw_antsw_occu, rpt->band, rpt->channel,
-+			 rpt->ht_rxsc, rpt->l_rxsc);
-+		pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n",
-+			 rpt->antidx_d, rpt->antidx_c, rpt->antidx_b,
-+			 rpt->antidx_a, rpt->lsig_length);
-+		pr_debug("[12] rf_mode=%d, NBI=%d, Intf_pos=%d, GID=%d, PAID=%d\n",
-+			 rpt->rf_mode, rpt->nb_intf_flag,
-+			 (rpt->intf_pos + (rpt->intf_pos_msb << 8)), rpt->gid,
-+			 (rpt->paid + (rpt->paid_msb << 8)));
-+		pr_debug("[16] EVM[D:A]={%d, %d, %d, %d}\n",
-+			 rpt->rxevm[3], rpt->rxevm[2],
-+			 rpt->rxevm[1], rpt->rxevm[0]);
-+		pr_debug("[20] CFO[D:A]={%d, %d, %d, %d}\n",
-+			 rpt->cfo_tail[3], rpt->cfo_tail[2], rpt->cfo_tail[1],
-+			 rpt->cfo_tail[0]);
-+		pr_debug("[24] SNR[D:A]={%d, %d, %d, %d}\n\n",
-+			 rpt->rxsnr[3], rpt->rxsnr[2], rpt->rxsnr[1],
-+			 rpt->rxsnr[0]);
-+
-+	} else if (phy_status_page_num == 2) {
-+		pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n",
-+			 rpt2->pwdb[3], rpt2->pwdb[2], rpt2->pwdb[1],
-+			 rpt2->pwdb[0]);
-+		pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht,l]={%d, %d}\n",
-+			 rpt2->beamformed, rpt2->ldpc, rpt2->stbc, rpt2->gnt_bt,
-+			 rpt2->hw_antsw_occu, rpt2->band, rpt2->channel,
-+			 rpt2->ht_rxsc, rpt2->l_rxsc);
-+		pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, cnt_pw2cca=%d, shift_l_map=%d\n",
-+			 rpt2->agc_table_d, rpt2->agc_table_c,
-+			 rpt2->agc_table_b, rpt2->agc_table_a,
-+			 rpt2->cnt_pw2cca, rpt2->shift_l_map);
-+		pr_debug("[12] (TRSW|Gain)[D:A]={%d %d, %d %d, %d %d, %d %d}, cnt_cca2agc_rdy=%d\n",
-+			 rpt2->trsw_d, rpt2->gain_d, rpt2->trsw_c, rpt2->gain_c,
-+			 rpt2->trsw_b, rpt2->gain_b, rpt2->trsw_a,
-+			 rpt2->gain_a, rpt2->cnt_cca2agc_rdy);
-+		pr_debug("[16] AAGC step[D:A]={%d, %d, %d, %d} HT AAGC gain[D:A]={%d, %d, %d, %d}\n",
-+			 rpt2->aagc_step_d, rpt2->aagc_step_c,
-+			 rpt2->aagc_step_b, rpt2->aagc_step_a,
-+			 rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2],
-+			 rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0]);
-+		pr_debug("[20] DAGC gain[D:A]={%d, %d, %d, %d}\n",
-+			 rpt2->dagc_gain[3],
-+			 rpt2->dagc_gain[2], rpt2->dagc_gain[1],
-+			 rpt2->dagc_gain[0]);
-+		pr_debug("[24] syn_cnt: %d, Cnt=%d\n\n",
-+			 rpt2->syn_count, rpt2->counter);
-+	}
-+}
-+
-+void phydm_set_per_path_phy_info(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail,
-+				 s8 rx_snr, u8 ant_idx,
-+				 struct phydm_phyinfo_struct *phy_info)
-+{
-+	u8 evm_dbm = 0;
-+	u8 evm_percentage = 0;
-+
-+	/* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */
-+
-+	if (rx_evm < 0) {
-+		/* @Calculate EVM in dBm */
-+		evm_dbm = ((u8)(0 - rx_evm) >> 1);
-+
-+		if (evm_dbm == 64)
-+			evm_dbm = 0; /*@if 1SS rate, evm_dbm [2nd stream] =64*/
-+
-+		if (evm_dbm != 0) {
-+			/* @Convert EVM to 0%~100% percentage */
-+			if (evm_dbm >= 34)
-+				evm_percentage = 100;
-+			else
-+				evm_percentage = (evm_dbm << 1) + (evm_dbm);
-+		}
-+	}
-+
-+	phy_info->rx_pwr[rx_path] = pwr;
-+
-+	/*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/
-+	phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1;
-+	phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;
-+	phy_info->rx_mimo_signal_strength[rx_path] = phydm_pw_2_percent(pwr);
-+	phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage;
-+	phy_info->rx_snr[rx_path] = rx_snr >> 1;
-+	phy_info->ant_idx[rx_path] = ant_idx;
-+
-+#if 0
-+	if (!pktinfo->is_packet_match_bssid)
-+		return;
-+
-+	dbg_print("path (%d)--------\n", rx_path);
-+	dbg_print("rx_pwr = %d, Signal strength = %d\n",
-+		  phy_info->rx_pwr[rx_path],
-+		  phy_info->rx_mimo_signal_strength[rx_path]);
-+	dbg_print("evm_dbm = %d, Signal quality = %d\n",
-+		  phy_info->rx_mimo_evm_dbm[rx_path],
-+		  phy_info->rx_mimo_signal_quality[rx_path]);
-+	dbg_print("CFO = %d, SNR = %d\n",
-+		  phy_info->cfo_tail[rx_path], phy_info->rx_snr[rx_path]);
-+
-+#endif
-+}
-+
-+void phydm_set_common_phy_info(s8 rx_power, u8 channel, boolean is_beamformed,
-+			       boolean is_mu_packet, u8 bandwidth,
-+			       u8 signal_quality, u8 rxsc,
-+			       struct phydm_phyinfo_struct *phy_info)
-+{
-+	phy_info->rx_power = rx_power; /* RSSI in dB */
-+	phy_info->recv_signal_power = rx_power; /* RSSI in dB */
-+	phy_info->channel = channel; /* @channel number */
-+	phy_info->is_beamformed = is_beamformed; /* @apply BF */
-+	phy_info->is_mu_packet = is_mu_packet; /* @MU packet */
-+	phy_info->rxsc = rxsc;
-+
-+	/* RSSI in percentage */
-+	phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_power);
-+	phy_info->signal_quality = signal_quality; /* signal quality */
-+	phy_info->band_width = bandwidth; /* @bandwidth */
-+
-+#if 0
-+	if (!pktinfo->is_packet_match_bssid)
-+		return;
-+
-+	dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n",
-+		  phy_info->rx_pwdb_all, phy_info->rx_power,
-+		  phy_info->recv_signal_power);
-+	dbg_print("signal_quality = %d\n", phy_info->signal_quality);
-+	dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n",
-+		  phy_info->is_beamformed, phy_info->is_mu_packet,
-+		  phy_info->rx_count + 1);
-+	dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel,
-+		  rxsc, bandwidth);
-+
-+#endif
-+}
-+
-+void phydm_get_phy_sts_type0(struct dm_struct *dm, u8 *phy_status_inf,
-+			     struct phydm_perpkt_info_struct *pktinfo,
-+			     struct phydm_phyinfo_struct *phy_info)
-+{
-+	/* type 0 is used for cck packet */
-+	struct phy_sts_rpt_jgr2_type0 *phy_sts = NULL;
-+	u8 sq = 0;
-+	s8 rx_pow = 0;
-+	u8 lna_idx = 0, vga_idx = 0;
-+	u8 ant_idx;
-+
-+	phy_sts = (struct phy_sts_rpt_jgr2_type0 *)phy_status_inf;
-+	rx_pow = phy_sts->pwdb - 110;
-+
-+	/* Fill in per-path antenna index */
-+	ant_idx = phy_sts->antidx_a;
-+
-+	if (dm->support_ic_type & ODM_RTL8723D) {
-+		#if (RTL8723D_SUPPORT)
-+		rx_pow = phy_sts->pwdb - 97;
-+		#endif
-+	}
-+	#if (RTL8821C_SUPPORT)
-+	else if (dm->support_ic_type & ODM_RTL8821C) {
-+		if (phy_sts->pwdb >= -57)
-+			rx_pow = phy_sts->pwdb - 100;
-+		else
-+			rx_pow = phy_sts->pwdb - 102;
-+	}
-+	#endif
-+
-+	if (pktinfo->is_to_self) {
-+		dm->ofdm_agc_idx[0] = phy_sts->pwdb;
-+		dm->ofdm_agc_idx[1] = 0;
-+		dm->ofdm_agc_idx[2] = 0;
-+		dm->ofdm_agc_idx[3] = 0;
-+	}
-+
-+	/* @Calculate Signal Quality*/
-+	if (phy_sts->signal_quality >= 64) {
-+		sq = 0;
-+	} else if (phy_sts->signal_quality <= 20) {
-+		sq = 100;
-+	} else {
-+		/* @mapping to 2~99% */
-+		sq = 64 - phy_sts->signal_quality;
-+		sq = ((sq << 3) + sq) >> 2;
-+	}
-+
-+	/* @Get RSSI for old CCK AGC */
-+	if (!dm->cck_new_agc) {
-+		vga_idx = phy_sts->vga;
-+
-+		if (dm->support_ic_type & ODM_RTL8197F) {
-+			/*@3bit LNA*/
-+			lna_idx = phy_sts->lna_l;
-+		} else {
-+			/*@4bit LNA*/
-+			lna_idx = (phy_sts->lna_h << 3) | phy_sts->lna_l;
-+		}
-+		rx_pow = phydm_get_cck_rssi(dm, lna_idx, vga_idx);
-+	}
-+
-+	/* @Confirm CCK RSSI */
-+	#if (RTL8197F_SUPPORT)
-+	if (dm->support_ic_type & ODM_RTL8197F) {
-+		u8 bb_pwr_th_l = 5; /* round( 31*0.15 ) */
-+		u8 bb_pwr_th_h = 27; /* round( 31*0.85 ) */
-+
-+		if (phy_sts->bb_power < bb_pwr_th_l ||
-+		    phy_sts->bb_power > bb_pwr_th_h)
-+			rx_pow = 0; /* @Error RSSI for CCK ; set 100*/
-+	}
-+	#endif
-+
-+	/*@CCK no STBC and LDPC*/
-+	dm->phy_dbg_info.is_ldpc_pkt = false;
-+	dm->phy_dbg_info.is_stbc_pkt = false;
-+
-+	/* Update Common information */
-+	phydm_set_common_phy_info(rx_pow, phy_sts->channel, false,
-+				  false, CHANNEL_WIDTH_20, sq,
-+				  phy_sts->rxsc, phy_info);
-+	/* Update CCK pwdb */
-+	phydm_set_per_path_phy_info(RF_PATH_A, rx_pow, 0, 0, 0, ant_idx,
-+				    phy_info);
-+
-+	#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
-+	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
-+	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
-+	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
-+	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
-+	#endif
-+}
-+
-+void phydm_get_phy_sts_type1(struct dm_struct *dm, u8 *phy_status_inf,
-+			     struct phydm_perpkt_info_struct *pktinfo,
-+			     struct phydm_phyinfo_struct *phy_info)
-+{
-+	/* type 1 is used for ofdm packet */
-+	struct phy_sts_rpt_jgr2_type1 *phy_sts = NULL;
-+	struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info;
-+	s8 rx_pwr_db = -120;
-+	s8 rx_pwr = 0;
-+	u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;
-+	boolean is_mu;
-+	u8 ant_idx[4];
-+
-+	phy_sts = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf;
-+
-+	/* Fill in per-path antenna index */
-+	ant_idx[0] = phy_sts->antidx_a;
-+	ant_idx[1] = phy_sts->antidx_b;
-+	ant_idx[2] = phy_sts->antidx_c;
-+	ant_idx[3] = phy_sts->antidx_d;
-+
-+	/* Update per-path information */
-+	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
-+		if (!(dm->rx_ant_status & BIT(i)))
-+			continue;
-+		rx_count++;
-+
-+		if (rx_count > dm->num_rf_path)
-+			break;
-+
-+		/* Update per-path information
-+		 * (RSSI_dB RSSI_percentage EVM SNR CFO sq)
-+		 */
-+		/* @EVM report is reported by stream, not path */
-+		rx_pwr = phy_sts->pwdb[i] - 110; /* per-path pwdb(dB)*/
-+
-+		if (pktinfo->is_to_self)
-+			dm->ofdm_agc_idx[i] = phy_sts->pwdb[i];
-+
-+		phydm_set_per_path_phy_info(i, rx_pwr,
-+					    phy_sts->rxevm[rx_count - 1],
-+					    phy_sts->cfo_tail[i],
-+					    phy_sts->rxsnr[i],
-+					    ant_idx[i], phy_info);
-+		/* search maximum pwdb */
-+		if (rx_pwr > rx_pwr_db)
-+			rx_pwr_db = rx_pwr;
-+	}
-+
-+	/* @mapping RX counter from 1~4 to 0~3 */
-+	if (rx_count > 0)
-+		phy_info->rx_count = rx_count - 1;
-+
-+	/* @Check if MU packet or not */
-+	if (phy_sts->gid != 0 && phy_sts->gid != 63) {
-+		is_mu = true;
-+		dbg_i->num_qry_mu_pkt++;
-+	} else {
-+		is_mu = false;
-+	}
-+
-+	/* @count BF packet */
-+	dbg_i->num_qry_bf_pkt = dbg_i->num_qry_bf_pkt + phy_sts->beamformed;
-+
-+	/*STBC or LDPC pkt*/
-+	dbg_i->is_ldpc_pkt = phy_sts->ldpc;
-+	dbg_i->is_stbc_pkt = phy_sts->stbc;
-+
-+	/* @Check sub-channel */
-+	if (pktinfo->data_rate > ODM_RATE11M &&
-+	    pktinfo->data_rate < ODM_RATEMCS0)
-+		rxsc = phy_sts->l_rxsc;
-+	else
-+		rxsc = phy_sts->ht_rxsc;
-+
-+	/* @Check RX bandwidth */
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		if (rxsc >= 1 && rxsc <= 8)
-+			bw = CHANNEL_WIDTH_20;
-+		else if ((rxsc >= 9) && (rxsc <= 12))
-+			bw = CHANNEL_WIDTH_40;
-+		else if (rxsc >= 13)
-+			bw = CHANNEL_WIDTH_80;
-+		else
-+			bw = phy_sts->rf_mode;
-+
-+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		if (phy_sts->rf_mode == 0)
-+			bw = CHANNEL_WIDTH_20;
-+		else if ((rxsc == 1) || (rxsc == 2))
-+			bw = CHANNEL_WIDTH_20;
-+		else
-+			bw = CHANNEL_WIDTH_40;
-+	}
-+
-+	/* Update packet information */
-+	phydm_set_common_phy_info(rx_pwr_db, phy_sts->channel,
-+				  (boolean)phy_sts->beamformed, is_mu, bw,
-+				  phy_info->rx_mimo_signal_quality[0],
-+				  rxsc, phy_info);
-+
-+	phydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss);
-+	#ifdef PHYDM_LNA_SAT_CHK_TYPE2
-+	phydm_parsing_snr(dm, pktinfo, phy_sts->rxsnr);
-+	#endif
-+
-+	#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+	dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a;
-+	dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b;
-+	dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c;
-+	dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d;
-+	#endif
-+}
-+
-+void phydm_get_phy_sts_type2(struct dm_struct *dm, u8 *phy_status_inf,
-+			     struct phydm_perpkt_info_struct *pktinfo,
-+			     struct phydm_phyinfo_struct *phy_info)
-+{
-+	struct phy_sts_rpt_jgr2_type2 *phy_sts = NULL;
-+	s8 rx_pwr_db_max = -120;
-+	s8 rx_pwr = 0;
-+	u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0;
-+
-+	phy_sts = (struct phy_sts_rpt_jgr2_type2 *)phy_status_inf;
-+
-+	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
-+		if (!(dm->rx_ant_status & BIT(i)))
-+			continue;
-+		rx_count++;
-+
-+		if (rx_count > dm->num_rf_path)
-+			break;
-+
-+		/* Update per-path information*/
-+		/* RSSI_dB, RSSI_percentage, EVM, SNR, CFO, sq */
-+		#if (RTL8197F_SUPPORT)
-+		if ((dm->support_ic_type & ODM_RTL8197F) &&
-+		    phy_sts->pwdb[i] == 0x7f) { /*@97f workaround*/
-+
-+			if (i == RF_PATH_A) {
-+				rx_pwr = (phy_sts->gain_a) << 1;
-+				rx_pwr = rx_pwr - 110;
-+			} else if (i == RF_PATH_B) {
-+				rx_pwr = (phy_sts->gain_b) << 1;
-+				rx_pwr = rx_pwr - 110;
-+			} else {
-+				rx_pwr = 0;
-+			}
-+		} else
-+		#endif
-+			rx_pwr = phy_sts->pwdb[i] - 110; /*@dBm*/
-+
-+		phydm_set_per_path_phy_info(i, rx_pwr, 0, 0, 0, 0, phy_info);
-+
-+		if (rx_pwr > rx_pwr_db_max) /* search max pwdb */
-+			rx_pwr_db_max = rx_pwr;
-+	}
-+
-+	/* @mapping RX counter from 1~4 to 0~3 */
-+	if (rx_count > 0)
-+		phy_info->rx_count = rx_count - 1;
-+
-+	/* @Check RX sub-channel */
-+	if (pktinfo->data_rate > ODM_RATE11M &&
-+	    pktinfo->data_rate < ODM_RATEMCS0)
-+		rxsc = phy_sts->l_rxsc;
-+	else
-+		rxsc = phy_sts->ht_rxsc;
-+
-+	/*STBC or LDPC pkt*/
-+	dm->phy_dbg_info.is_ldpc_pkt = phy_sts->ldpc;
-+	dm->phy_dbg_info.is_stbc_pkt = phy_sts->stbc;
-+
-+	/* @Check RX bandwidth */
-+	/* @BW information of sc=0 is useless,
-+	 *because there is no information of RF mode
-+	 */
-+	if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		if (rxsc >= 1 && rxsc <= 8)
-+			bw = CHANNEL_WIDTH_20;
-+		else if ((rxsc >= 9) && (rxsc <= 12))
-+			bw = CHANNEL_WIDTH_40;
-+		else if (rxsc >= 13)
-+			bw = CHANNEL_WIDTH_80;
-+
-+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		if (rxsc == 3)
-+			bw = CHANNEL_WIDTH_40;
-+		else if ((rxsc == 1) || (rxsc == 2))
-+			bw = CHANNEL_WIDTH_20;
-+	}
-+
-+	/* Update packet information */
-+	phydm_set_common_phy_info(rx_pwr_db_max, phy_sts->channel,
-+				  (boolean)phy_sts->beamformed,
-+				  false, bw, 0, rxsc, phy_info);
-+}
-+
-+void phydm_process_rssi_for_dm_2nd_type(struct dm_struct *dm,
-+					struct phydm_phyinfo_struct *phy_info,
-+					struct phydm_perpkt_info_struct *pktinfo
-+					)
-+{
-+	struct cmn_sta_info *sta = NULL;
-+	struct rssi_info *rssi_t = NULL;
-+	u8 rssi_tmp = 0;
-+	u64 rssi_linear = 0;
-+	s16 rssi_db = 0;
-+	u8 i = 0;
-+
-+	if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM)
-+		return;
-+
-+	sta = dm->phydm_sta_info[pktinfo->station_id];
-+
-+	if (!is_sta_active(sta))
-+		return;
-+
-+	if (!pktinfo->is_packet_match_bssid) /*@data frame only*/
-+		return;
-+
-+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-+	if (dm->support_ability & ODM_BB_ANT_DIV)
-+		odm_process_rssi_for_ant_div(dm, phy_info, pktinfo);
-+#endif
-+
-+#if (defined(CONFIG_PATH_DIVERSITY))
-+	if (dm->support_ability & ODM_BB_PATH_DIV)
-+		phydm_process_rssi_for_path_div(dm, phy_info, pktinfo);
-+#endif
-+
-+#ifdef CONFIG_ADAPTIVE_SOML
-+	phydm_rx_qam_for_soml(dm, pktinfo);
-+	phydm_rx_rate_for_soml(dm, pktinfo);
-+#endif
-+
-+	if (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon))
-+		return;
-+
-+	if (pktinfo->is_packet_beacon) {
-+		dm->phy_dbg_info.num_qry_beacon_pkt++;
-+		dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate;
-+	}
-+
-+	rssi_t = &sta->rssi_stat;
-+
-+	for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) {
-+		rssi_tmp = phy_info->rx_mimo_signal_strength[i];
-+		if (rssi_tmp != 0)
-+			rssi_linear += phydm_db_2_linear(rssi_tmp);
-+	}
-+	/* @Rounding and removing fractional bits */
-+	rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
-+
-+	switch (phy_info->rx_count + 1) {
-+	case 2:
-+		rssi_linear = DIVIDED_2(rssi_linear);
-+		break;
-+	case 3:
-+		rssi_linear = DIVIDED_3(rssi_linear);
-+		break;
-+	case 4:
-+		rssi_linear = DIVIDED_4(rssi_linear);
-+		break;
-+	}
-+
-+	rssi_db = (s16)odm_convert_to_db(rssi_linear);
-+
-+	if (rssi_t->rssi_acc == 0) {
-+		rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA);
-+		rssi_t->rssi = (s8)(rssi_db);
-+	} else {
-+		rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, rssi_db, RSSI_MA);
-+		rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, RSSI_MA);
-+	}
-+
-+	if (pktinfo->is_cck_rate)
-+		rssi_t->rssi_cck = (s8)rssi_db;
-+	else
-+		rssi_t->rssi_ofdm = (s8)rssi_db;
-+}
-+
-+void phydm_rx_physts_2nd_type(void *dm_void, u8 *phy_sts,
-+			      struct phydm_perpkt_info_struct *pktinfo,
-+			      struct phydm_phyinfo_struct *phy_info)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 page = (*phy_sts & 0xf);
-+
-+	/* Phy status parsing */
-+	switch (page) {
-+	case 0: /*@CCK*/
-+		phydm_get_phy_sts_type0(dm, phy_sts, pktinfo, phy_info);
-+		break;
-+	case 1:
-+		phydm_get_phy_sts_type1(dm, phy_sts, pktinfo, phy_info);
-+		break;
-+	case 2:
-+		phydm_get_phy_sts_type2(dm, phy_sts, pktinfo, phy_info);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)
-+	if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B))
-+		phydm_print_phy_sts_jgr2(dm, phy_sts, pktinfo, phy_info);
-+#endif
-+}
-+
-+/*@==============================================*/
-+#endif
-+
-+boolean odm_phy_status_query(struct dm_struct *dm,
-+			     struct phydm_phyinfo_struct *phy_info,
-+			     u8 *phy_sts,
-+			     struct phydm_perpkt_info_struct *pktinfo)
-+{
-+#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
-+	struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct;
-+	boolean auto_swch_en = dm->pkt_proc_struct.physts_auto_swch_en;
-+#endif
-+	u8 rate = pktinfo->data_rate;
-+	u8 page = (*phy_sts & 0xf);
-+
-+	pktinfo->is_cck_rate = PHYDM_IS_CCK_RATE(rate);
-+	pktinfo->rate_ss = phydm_rate_to_num_ss(dm, rate);
-+	dm->rate_ss = pktinfo->rate_ss; /*@For AP EVM SW antenna diversity use*/
-+
-+	if (pktinfo->is_cck_rate)
-+		dm->phy_dbg_info.num_qry_phy_status_cck++;
-+	else
-+		dm->phy_dbg_info.num_qry_phy_status_ofdm++;
-+
-+	/*Reset phy_info*/
-+	phydm_reset_phy_info(dm, phy_info);
-+
-+	if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) {
-+		#ifdef PHYSTS_3RD_TYPE_SUPPORT
-+		#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
-+		if (phydm_physts_auto_switch_jgr3(dm, phy_sts, pktinfo)) {
-+			PHYDM_DBG(dm, DBG_PHY_STATUS, "SKIP parsing\n");
-+			phy_info->physts_rpt_valid = false;
-+			return false;
-+		}
-+		#endif
-+		phydm_rx_physts_jgr3(dm, phy_sts, pktinfo, phy_info);
-+		phydm_process_dm_rssi_jgr3(dm, phy_info, pktinfo);
-+		#endif
-+	} else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
-+		#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
-+		phydm_rx_physts_2nd_type(dm, phy_sts, pktinfo, phy_info);
-+		phydm_process_rssi_for_dm_2nd_type(dm, phy_info, pktinfo);
-+		#endif
-+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		#if ODM_IC_11AC_SERIES_SUPPORT
-+		phydm_rx_physts_1st_type(dm, phy_info, phy_sts, pktinfo);
-+		phydm_process_rssi_for_dm(dm, phy_info, pktinfo);
-+		#endif
-+	} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		#if ODM_IC_11N_SERIES_SUPPORT
-+		phydm_phy_sts_n_parsing(dm, phy_info, phy_sts, pktinfo);
-+		phydm_process_rssi_for_dm(dm, phy_info, pktinfo);
-+		#endif
-+	}
-+	phy_info->signal_strength = phy_info->rx_pwdb_all;
-+	#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	phydm_process_signal_strength(dm, phy_info, pktinfo);
-+	#endif
-+
-+	/*For basic debug message*/
-+	if (pktinfo->is_packet_match_bssid || *dm->mp_mode) {
-+		dm->curr_station_id = pktinfo->station_id;
-+		dm->rx_rate = rate;
-+		dm->rssi_a = phy_info->rx_mimo_signal_strength[RF_PATH_A];
-+		dm->rssi_b = phy_info->rx_mimo_signal_strength[RF_PATH_B];
-+		dm->rssi_c = phy_info->rx_mimo_signal_strength[RF_PATH_C];
-+		dm->rssi_d = phy_info->rx_mimo_signal_strength[RF_PATH_D];
-+
-+		if (rate >= ODM_RATE6M && rate <= ODM_RATE54M)
-+			dm->rxsc_l = (s8)phy_info->rxsc;
-+		else if (phy_info->band_width == CHANNEL_WIDTH_20)
-+			dm->rxsc_20 = (s8)phy_info->rxsc;
-+		else if (phy_info->band_width == CHANNEL_WIDTH_40)
-+			dm->rxsc_40 = (s8)phy_info->rxsc;
-+		else if (phy_info->band_width == CHANNEL_WIDTH_80)
-+			dm->rxsc_80 = (s8)phy_info->rxsc;
-+
-+		#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
-+		if (auto_swch_en && page == 4 && pktinfo->rate_ss > 1)
-+			phydm_avg_condi_num(dm, phy_info, pktinfo);
-+
-+		if (!auto_swch_en ||
-+		    (pkt_proc->is_1st_mpdu || PHYDM_IS_LEGACY_RATE(rate)))
-+		#endif
-+		{
-+			phydm_avg_rssi_evm_snr(dm, phy_info, pktinfo);
-+			phydm_rx_statistic_cal(dm, phy_info, phy_sts, pktinfo);
-+		}
-+	}
-+
-+	phy_info->physts_rpt_valid = true;
-+	return true;
-+}
-+
-+void phydm_rx_phy_status_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info;
-+
-+	dbg->show_phy_sts_all_pkt = 0;
-+	dbg->show_phy_sts_max_cnt = 1;
-+	dbg->show_phy_sts_cnt = 0;
-+
-+	phydm_avg_phystatus_init(dm);
-+
-+	#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
-+	dm->pkt_proc_struct.physts_auto_swch_en = false;
-+	#endif
-+}
-+
-+void phydm_physts_dbg(void *dm_void, char input[][16], u32 *_used,
-+		      char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	boolean enable;
-+	u32 var[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i = 0;
-+
-+	for (i = 0; i < 3; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
-+	}
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Page Auto Switching: swh {en} {bitmap(hex)}\n");
-+	} else if ((strcmp(input[1], "swh") == 0)) {
-+		#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
-+		PHYDM_SSCANF(input[3], DCMD_HEX, &var[2]);
-+		enable = (boolean)var[1];
-+		phydm_physts_auto_switch_jgr3_set(dm, enable, (u8)var[2]);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Page Auto Switching: en=%d, bitmap=0x%x\n",
-+			 enable, var[2]);
-+		#endif
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_phystatus.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_phystatus.h
-new file mode 100644
-index 000000000000..c65b6245f83e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_phystatus.h
-@@ -0,0 +1,1250 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_PHYSTATUS_H__
-+#define __PHYDM_PHYSTATUS_H__
-+
-+/* 2020.07.03 fix cck report bug due to 8723F coding error*/
-+#define PHYSTS_VERSION "1.2"
-+
-+/*@--------------------------Define ------------------------------------------*/
-+#define CCK_RSSI_INIT_COUNT 5
-+
-+#define RA_RSSI_STATE_INIT 0
-+#define RA_RSSI_STATE_SEND 1
-+#define RA_RSSI_STATE_HOLD 2
-+
-+#if defined(DM_ODM_CE_MAC80211)
-+#define CFO_HW_RPT_2_KHZ(val) ({		\
-+	s32 cfo_hw_rpt_2_khz_tmp = (val);	\
-+	(cfo_hw_rpt_2_khz_tmp << 1) + (cfo_hw_rpt_2_khz_tmp >> 1);	\
-+	})
-+#else
-+#define CFO_HW_RPT_2_KHZ(val) ((val << 1) + (val >> 1))
-+#endif
-+
-+/* @(X* 312.5 Khz)>>7 ~=  X*2.5 Khz= (X<<1 + X>>1)Khz  */
-+
-+#define IGI_2_RSSI(igi) (igi - 10)
-+
-+#define PHY_STATUS_JRGUAR2_DW_LEN 7 /* @7*4 = 28 Byte */
-+#define PHY_STATUS_JRGUAR3_DW_LEN 7 /* @7*4 = 28 Byte */
-+#define SHOW_PHY_STATUS_UNLIMITED 0
-+#define RSSI_MA 4 /*moving average factor for RSSI: 2^4=16 */
-+
-+#define PHYSTS_PATH_NUM 4
-+
-+/*@************************************************************
-+ * structure and define
-+ ************************************************************/
-+
-+__PACK struct phy_rx_agc_info {
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 gain : 7, trsw : 1;
-+#else
-+	u8 trsw : 1, gain : 7;
-+#endif
-+};
-+
-+__PACK struct phy_status_rpt_8192cd {
-+	struct phy_rx_agc_info path_agc[2];
-+	u8	ch_corr[2];
-+	u8	cck_sig_qual_ofdm_pwdb_all;
-+	u8	cck_agc_rpt_ofdm_cfosho_a;
-+	u8	cck_rpt_b_ofdm_cfosho_b;
-+	u8	rsvd_1;/*@ch_corr_msb;*/
-+	u8	noise_power_db_msb;
-+	s8	path_cfotail[2];
-+	u8	pcts_mask[2];
-+	s8	stream_rxevm[2];
-+	u8	path_rxsnr[2];
-+	u8	noise_power_db_lsb;
-+	u8	rsvd_2[3];
-+	u8	stream_csi[2];
-+	u8	stream_target_csi[2];
-+	s8	sig_evm;
-+	u8	rsvd_3;
-+
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8	antsel_rx_keep_2: 1;	/*@ex_intf_flg:1;*/
-+	u8	sgi_en: 1;
-+	u8	rxsc: 2;
-+	u8	idle_long: 1;
-+	u8	r_ant_train_en: 1;
-+	u8	ant_sel_b: 1;
-+	u8	ant_sel: 1;
-+#else	/*@_BIG_ENDIAN_	*/
-+	u8	ant_sel: 1;
-+	u8	ant_sel_b: 1;
-+	u8	r_ant_train_en: 1;
-+	u8	idle_long: 1;
-+	u8	rxsc: 2;
-+	u8	sgi_en: 1;
-+	u8	antsel_rx_keep_2: 1;/*@ex_intf_flg:1;*/
-+#endif
-+};
-+
-+struct phy_status_rpt_8812 {
-+	/*	@DWORD 0*/
-+	u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/
-+	u8 chl_num_LSB; /*@channel number[7:0]*/
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 chl_num_MSB : 2; /*@channel number[9:8]*/
-+	u8 sub_chnl : 4; /*sub-channel location[3:0]*/
-+	u8 r_RFMOD : 2; /*RF mode[1:0]*/
-+#else /*@_BIG_ENDIAN_	*/
-+	u8 r_RFMOD : 2;
-+	u8 sub_chnl : 4;
-+	u8 chl_num_MSB : 2;
-+#endif
-+
-+	/*	@DWORD 1*/
-+	u8 pwdb_all; /*@CCK signal quality / OFDM pwdb all*/
-+	s8 cfosho[2]; /*@CCK AGC report and CCK_BB_Power*/
-+		      /*OFDM path-A and path-B short CFO*/
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 resvd_0 : 6;
-+	u8 bt_RF_ch_MSB : 2; /*@8812A:2'b0  8814A: bt rf channel keep[7:6]*/
-+#else /*@_BIG_ENDIAN_*/
-+	u8 bt_RF_ch_MSB : 2;
-+	u8 resvd_0 : 6;
-+#endif
-+
-+/*	@DWORD 2*/
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 ant_div_sw_a : 1; /*@8812A: ant_div_sw_a    8814A: 1'b0*/
-+	u8 ant_div_sw_b : 1; /*@8812A: ant_div_sw_b    8814A: 1'b0*/
-+	u8 bt_RF_ch_LSB : 6; /*@8812A: 6'b0     8814A: bt rf channel keep[5:0]*/
-+#else /*@_BIG_ENDIAN_	*/
-+	u8 bt_RF_ch_LSB : 6;
-+	u8 ant_div_sw_b : 1;
-+	u8 ant_div_sw_a : 1;
-+#endif
-+	s8 cfotail[2]; /*@DW2 byte 1 DW2 byte 2	path-A and path-B CFO tail*/
-+	u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/
-+	u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/
-+
-+	/*	@DWORD 3*/
-+	s8 rxevm[2]; /*@DW3 byte 1 DW3 byte 2	stream 1 and stream 2 RX EVM*/
-+	s8 rxsnr[2]; /*@DW3 byte 3 DW4 byte 0	path-A and path-B RX SNR*/
-+
-+	/*	@DWORD 4*/
-+	u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 PCTS_MSK_RPT_3 : 6; /*PCTS mask report[29:24]*/
-+	u8 pcts_rpt_valid : 1; /*pcts_rpt_valid*/
-+	u8 resvd_1 : 1; /*@1'b0*/
-+#else /*@_BIG_ENDIAN_*/
-+	u8 resvd_1 : 1;
-+	u8 pcts_rpt_valid : 1;
-+	u8 PCTS_MSK_RPT_3 : 6;
-+#endif
-+	s8 rxevm_cd[2]; /*@8812A: 16'b0*/
-+			/*@8814A: stream 3 and stream 4 RX EVM*/
-+	/*	@DWORD 5*/
-+	u8 csi_current[2]; /*@8812A: stream 1 and 2 CSI*/
-+			   /*@8814A:  path-C and path-D RX SNR*/
-+	u8 gain_trsw_cd[2]; /*path-C and path-D {TRSW, gain[6:0] }*/
-+
-+	/*	@DWORD 6*/
-+	s8 sigevm; /*signal field EVM*/
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 antidx_antc : 3;	/*@8812A: 3'b0	8814A: antidx_antc[2:0]*/
-+	u8 antidx_antd : 3;	/*@8812A: 3'b0	8814A: antidx_antd[2:0]*/
-+	u8 dpdt_ctrl_keep : 1;	/*@8812A: 1'b0	8814A: dpdt_ctrl_keep*/
-+	u8 GNT_BT_keep : 1;	/*@8812A: 1'b0	8814A: GNT_BT_keep*/
-+#else /*@_BIG_ENDIAN_*/
-+	u8 GNT_BT_keep : 1;
-+	u8 dpdt_ctrl_keep : 1;
-+	u8 antidx_antd : 3;
-+	u8 antidx_antc : 3;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 antidx_anta : 3; /*@antidx_anta[2:0]*/
-+	u8 antidx_antb : 3; /*@antidx_antb[2:0]*/
-+	u8 hw_antsw_occur : 2; /*@1'b0*/
-+#else /*@_BIG_ENDIAN_*/
-+	u8 hw_antsw_occur : 2;
-+	u8 antidx_antb : 3;
-+	u8 antidx_anta : 3;
-+#endif
-+};
-+
-+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
-+
-+__PACK struct phy_sts_rpt_jgr2_type0 {
-+	/* @DW0 */
-+	u8 page_num;
-+	u8 pwdb;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 gain : 6;
-+	u8 rsvd_0 : 1;
-+	u8 trsw : 1;
-+#else
-+	u8 trsw : 1;
-+	u8 rsvd_0 : 1;
-+	u8 gain : 6;
-+#endif
-+	u8 rsvd_1;
-+
-+	/* @DW1 */
-+	u8 rsvd_2;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 rxsc : 4;
-+	u8 agc_table : 4;
-+#else
-+	u8 agc_table : 4;
-+	u8 rxsc : 4;
-+#endif
-+	u8 channel;
-+	u8 band;
-+
-+	/* @DW2 */
-+	u16 length;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 antidx_a : 3;
-+	u8 antidx_b : 3;
-+	u8 rsvd_3 : 2;
-+	u8 antidx_c : 3;
-+	u8 antidx_d : 3;
-+	u8 rsvd_4 : 2;
-+#else
-+	u8 rsvd_3 : 2;
-+	u8 antidx_b : 3;
-+	u8 antidx_a : 3;
-+	u8 rsvd_4 : 2;
-+	u8 antidx_d : 3;
-+	u8 antidx_c : 3;
-+#endif
-+
-+	/* @DW3 */
-+	u8 signal_quality;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 vga : 5;
-+	u8 lna_l : 3;
-+	u8 bb_power : 6;
-+	u8 rsvd_9 : 1;
-+	u8 lna_h : 1;
-+#else
-+	u8 lna_l : 3;
-+	u8 vga : 5;
-+	u8 lna_h : 1;
-+	u8 rsvd_9 : 1;
-+	u8 bb_power : 6;
-+#endif
-+	u8 rsvd_5;
-+
-+	/* @DW4 */
-+	u32 rsvd_6;
-+
-+	/* @DW5 */
-+	u32 rsvd_7;
-+
-+	/* @DW6 */
-+	u32 rsvd_8;
-+};
-+
-+__PACK struct phy_sts_rpt_jgr2_type1 {
-+	/* @DW0 and DW1 */
-+	u8 page_num;
-+	u8 pwdb[4];
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 l_rxsc : 4;
-+	u8 ht_rxsc : 4;
-+#else
-+	u8 ht_rxsc : 4;
-+	u8 l_rxsc : 4;
-+#endif
-+	u8 channel;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 band : 2;
-+	u8 rsvd_0 : 1;
-+	u8 hw_antsw_occu : 1;
-+	u8 gnt_bt : 1;
-+	u8 ldpc : 1;
-+	u8 stbc : 1;
-+	u8 beamformed : 1;
-+#else
-+	u8 beamformed : 1;
-+	u8 stbc : 1;
-+	u8 ldpc : 1;
-+	u8 gnt_bt : 1;
-+	u8 hw_antsw_occu : 1;
-+	u8 rsvd_0 : 1;
-+	u8 band : 2;
-+#endif
-+
-+	/* @DW2 */
-+	u16 lsig_length;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 antidx_a : 3;
-+	u8 antidx_b : 3;
-+	u8 rsvd_1 : 2;
-+	u8 antidx_c : 3;
-+	u8 antidx_d : 3;
-+	u8 rsvd_2 : 2;
-+#else
-+	u8 rsvd_1 : 2;
-+	u8 antidx_b : 3;
-+	u8 antidx_a : 3;
-+	u8 rsvd_2 : 2;
-+	u8 antidx_d : 3;
-+	u8 antidx_c : 3;
-+#endif
-+
-+	/* @DW3 */
-+	u8 paid;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 paid_msb : 1;
-+	u8 gid : 6;
-+	u8 rsvd_3 : 1;
-+#else
-+	u8 rsvd_3 : 1;
-+	u8 gid : 6;
-+	u8 paid_msb : 1;
-+#endif
-+	u8 intf_pos;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 intf_pos_msb : 1;
-+	u8 rsvd_4 : 2;
-+	u8 nb_intf_flag : 1;
-+	u8 rf_mode : 2;
-+	u8 rsvd_5 : 2;
-+#else
-+	u8 rsvd_5 : 2;
-+	u8 rf_mode : 2;
-+	u8 nb_intf_flag : 1;
-+	u8 rsvd_4 : 2;
-+	u8 intf_pos_msb : 1;
-+#endif
-+
-+	/* @DW4 */
-+	s8 rxevm[4]; /* s(8,1) */
-+
-+	/* @DW5 */
-+	s8 cfo_tail[4]; /* s(8,7) */
-+
-+	/* @DW6 */
-+	s8 rxsnr[4]; /* s(8,1) */
-+};
-+
-+__PACK struct phy_sts_rpt_jgr2_type2 {
-+	/* @DW0 ane DW1 */
-+	u8 page_num;
-+	u8 pwdb[4];
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 l_rxsc : 4;
-+	u8 ht_rxsc : 4;
-+#else
-+	u8 ht_rxsc : 4;
-+	u8 l_rxsc : 4;
-+#endif
-+	u8 channel;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 band : 2;
-+	u8 rsvd_0 : 1;
-+	u8 hw_antsw_occu : 1;
-+	u8 gnt_bt : 1;
-+	u8 ldpc : 1;
-+	u8 stbc : 1;
-+	u8 beamformed : 1;
-+#else
-+	u8 beamformed : 1;
-+	u8 stbc : 1;
-+	u8 ldpc : 1;
-+	u8 gnt_bt : 1;
-+	u8 hw_antsw_occu : 1;
-+	u8 rsvd_0 : 1;
-+	u8 band : 2;
-+#endif
-+
-+/* @DW2 */
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 shift_l_map : 6;
-+	u8 rsvd_1 : 2;
-+#else
-+	u8 rsvd_1 : 2;
-+	u8 shift_l_map : 6;
-+#endif
-+	u8 cnt_pw2cca;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 agc_table_a : 4;
-+	u8 agc_table_b : 4;
-+	u8 agc_table_c : 4;
-+	u8 agc_table_d : 4;
-+#else
-+	u8 agc_table_b : 4;
-+	u8 agc_table_a : 4;
-+	u8 agc_table_d : 4;
-+	u8 agc_table_c : 4;
-+#endif
-+
-+	/* @DW3 ~ DW6*/
-+	u8 cnt_cca2agc_rdy;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 gain_a : 6;
-+	u8 rsvd_2 : 1;
-+	u8 trsw_a : 1;
-+	u8 gain_b : 6;
-+	u8 rsvd_3 : 1;
-+	u8 trsw_b : 1;
-+	u8 gain_c : 6;
-+	u8 rsvd_4 : 1;
-+	u8 trsw_c : 1;
-+	u8 gain_d : 6;
-+	u8 rsvd_5 : 1;
-+	u8 trsw_d : 1;
-+	u8 aagc_step_a : 2;
-+	u8 aagc_step_b : 2;
-+	u8 aagc_step_c : 2;
-+	u8 aagc_step_d : 2;
-+#else
-+	u8 trsw_a : 1;
-+	u8 rsvd_2 : 1;
-+	u8 gain_a : 6;
-+	u8 trsw_b : 1;
-+	u8 rsvd_3 : 1;
-+	u8 gain_b : 6;
-+	u8 trsw_c : 1;
-+	u8 rsvd_4 : 1;
-+	u8 gain_c : 6;
-+	u8 trsw_d : 1;
-+	u8 rsvd_5 : 1;
-+	u8 gain_d : 6;
-+	u8 aagc_step_d : 2;
-+	u8 aagc_step_c : 2;
-+	u8 aagc_step_b : 2;
-+	u8 aagc_step_a : 2;
-+#endif
-+	u8 ht_aagc_gain[4];
-+	u8 dagc_gain[4];
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 counter : 6;
-+	u8 rsvd_6 : 2;
-+	u8 syn_count : 5;
-+	u8 rsvd_7 : 3;
-+#else
-+	u8 rsvd_6 : 2;
-+	u8 counter : 6;
-+	u8 rsvd_7 : 3;
-+	u8 syn_count : 5;
-+#endif
-+};
-+#endif
-+
-+/*@==============================================*/
-+#ifdef PHYSTS_3RD_TYPE_SUPPORT
-+__PACK struct phy_sts_rpt_jgr3_type0 {
-+/* @DW0 : Offset 0 */
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 page_num : 4;
-+	u8 pkt_cnt : 2;
-+	u8 channel_msb : 2;
-+#else
-+	u8 channel_msb : 2;
-+	u8 pkt_cnt : 2;
-+	u8 page_num : 4;
-+#endif
-+	u8 pwdb_a;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 gain_a : 6;
-+	u8 rsvd_0 : 1;
-+	u8 trsw : 1;
-+#else
-+	u8 trsw : 1;
-+	u8 rsvd_0 : 1;
-+	u8 gain_a : 6;
-+#endif
-+
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 agc_table_b : 4;
-+	u8 agc_table_c : 4;
-+#else
-+	u8 agc_table_c : 4;
-+	u8 agc_table_b : 4;
-+#endif
-+
-+/* @DW1 : Offset 4 */
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 rsvd_1 : 4;
-+	u8 agc_table_d : 4;
-+#else
-+	u8 agc_table_d : 4;
-+	u8 rsvd_1 : 4;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 l_rxsc : 4;
-+	u8 agc_table_a : 4;
-+#else
-+	u8 agc_table_a : 4;
-+	u8 l_rxsc : 4;
-+#endif
-+	u8 channel;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 band : 2;
-+	u8 rsvd_2_1 : 1;
-+	u8 hw_antsw_occur_keep_cck : 1;
-+	u8 gnt_bt_keep_cck : 1;
-+	u8 rsvd_2_2 : 1;
-+	u8 path_sel_o : 2;
-+#else
-+	u8 path_sel_o : 2;
-+	u8 rsvd_2_2 : 1;
-+	u8 gnt_bt_keep_cck : 1;
-+	u8 hw_antsw_occur_keep_cck : 1;
-+	u8 rsvd_2_1 : 1;
-+	u8 band : 2;
-+#endif
-+
-+	/* @DW2 : Offset 8 */
-+	u16 length;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 antidx_a : 4;
-+	u8 antidx_b : 4;
-+#else
-+	u8 antidx_b : 4;
-+	u8 antidx_a : 4;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 antidx_c : 4;
-+	u8 antidx_d : 4;
-+#else
-+	u8 antidx_d : 4;
-+	u8 antidx_c : 4;
-+#endif
-+
-+	/* @DW3 : Offset 12 */
-+	u8 signal_quality;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 vga_a : 5;
-+	u8 lna_l_a : 3;
-+#else
-+	u8 lna_l_a : 3;
-+	u8 vga_a : 5;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 bb_power_a : 6;
-+	u8 rsvd_3_1 : 1;
-+	u8 lna_h_a : 1;
-+#else
-+
-+	u8 lna_h_a : 1;
-+	u8 rsvd_3_1 : 1;
-+	u8 bb_power_a : 6;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 rxrate : 2;
-+	u8 raterr : 1;
-+	u8 lockbit : 1;
-+	u8 sqloss : 1;
-+	u8 mf_off : 1;
-+	u8 rsvd_3_2 : 2;
-+#else
-+	u8 rsvd_3_2 : 2;
-+	u8 mf_off : 1;
-+	u8 sqloss : 1;
-+	u8 lockbit : 1;
-+	u8 raterr : 1;
-+	u8 rxrate : 2;
-+#endif
-+
-+	/* @DW4 : Offset 16 */
-+	u8 pwdb_b;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 vga_b : 5;
-+	u8 lna_l_b : 3;
-+#else
-+	u8 lna_l_b : 3;
-+	u8 vga_b : 5;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 bb_power_b : 6;
-+	u8 rsvd_4_1 : 1;
-+	u8 lna_h_b : 1;
-+#else
-+	u8 lna_h_b : 1;
-+	u8 rsvd_4_1 : 1;
-+	u8 bb_power_b : 6;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 gain_b : 6;
-+	u8 rsvd_4_2 : 2;
-+#else
-+	u8 rsvd_4_2 : 2;
-+	u8 gain_b : 6;
-+#endif
-+
-+	/* @DW5 : Offset 20 */
-+	u8 pwdb_c;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 vga_c : 5;
-+	u8 lna_l_c : 3;
-+#else
-+	u8 lna_l_c : 3;
-+	u8 vga_c : 5;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 bb_power_c : 6;
-+	u8 rsvd_5_1 : 1;
-+	u8 lna_h_c : 1;
-+#else
-+	u8 lna_h_c : 1;
-+	u8 rsvd_5_1 : 1;
-+	u8 bb_power_c : 6;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 gain_c : 6;
-+	u8 rsvd_5_2 : 2;
-+#else
-+	u8 rsvd_5_2 : 2;
-+	u8 gain_c : 6;
-+#endif
-+
-+	/* @DW6 : Offset 24 */
-+	u8 pwdb_d;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 vga_d : 5;
-+	u8 lna_l_d : 3;
-+#else
-+	u8 lna_l_d : 3;
-+	u8 vga_d : 5;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 bb_power_d : 6;
-+	u8 rsvd_6_1 : 1;
-+	u8 lna_h_d : 1;
-+#else
-+	u8 lna_h_d : 1;
-+	u8 rsvd_6_1 : 1;
-+	u8 bb_power_d : 6;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 gain_d : 6;
-+	u8 rsvd_6_2 : 2;
-+#else
-+	u8 rsvd_6_2 : 2;
-+	u8 gain_d : 6;
-+#endif
-+};
-+#if(RTL8723F_SUPPORT)
-+__PACK struct phy_sts_rpt_jgr3_type6 {
-+	/* judy_add_8723F_0512 */
-+/* @DW0 : Offset 0 */
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 pop_idx : 4;
-+	u8 pkt_cnt : 2;
-+	u8 channel_msb : 2;
-+#else
-+	u8 channel_msb : 2;
-+	u8 pkt_cnt : 2;
-+	u8 pop_idx : 4;
-+#endif
-+
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 agc_table_a : 4;
-+	u8 rsvd_0 : 4;
-+#else
-+	u8 rsvd_0 : 4;
-+	u8 agc_table_a : 4;
-+#endif
-+	u8 rsvd_1 : 8;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 trsw : 1;
-+	u8 hw_antsw_occur_keep_cck : 1;
-+	u8 gnt_bt_keep_cck : 1;
-+	u8 rssi_msb : 3;
-+	u8 rsvd_2 : 2;	
-+#else
-+	u8 rsvd_2 : 2;
-+	u8 rssi_msb : 3;
-+	u8 gnt_bt_keep_cck : 1;
-+	u8 hw_antsw_occur_keep_cck : 1;
-+	u8 trsw : 1;
-+#endif
-+
-+/* @DW1 : Offset 4 */
-+	u8 channel;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 antidx_a : 4;
-+	u8 rsvd_2_1 : 4;
-+#else
-+	u8 rsvd_2_1 : 4;
-+	u8 antidx_a : 4;
-+#endif
-+	u8 rsvd_2_2;
-+	u8 mp_gain_idx_a;
-+
-+/* @DW2 : Offset 8 */
-+	u16 rsvd_3_1;
-+	u8 rsvd_4_1;
-+	u8 rssi;
-+
-+/* @DW3 : Offset 12 */
-+	u16 rsvd_4_2;
-+	u8 rsvd_5_1;
-+	u8 avg_cfo;	
-+/* @DW4 : Offset 16 */
-+	u8 coarse_cfo;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 coarse_cfo_msb : 4;
-+	u8 avg_cfo_msb : 4;
-+#else
-+	u8 avg_cfo_msb : 4;
-+	u8 coarse_cfo_msb : 4;
-+#endif
-+	u8 evm_hdr;
-+	u8 evm_pld;
-+/* @DW5 : Offset 20 */
-+	u32 rsvd_6_1;
-+	u32 rsvd_7_1;
-+};
-+#endif
-+__PACK struct phy_sts_rpt_jgr3_type1 {
-+/* @DW0 : Offset 0 */
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 page_num : 4;
-+	u8 pkt_cnt : 2;
-+	u8 channel_pri_msb : 2;
-+#else
-+	u8 channel_pri_msb : 2;
-+	u8 pkt_cnt : 2;
-+	u8 page_num : 4;
-+#endif
-+	u8 pwdb_a;
-+	u8 pwdb_b;
-+	u8 pwdb_c;
-+
-+	/* @DW1 : Offset 4 */
-+	u8 pwdb_d;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 l_rxsc : 4;
-+	u8 ht_rxsc : 4;
-+#else
-+	u8 ht_rxsc : 4;
-+	u8 l_rxsc : 4;
-+#endif
-+	u8 channel_pri_lsb;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 band : 2;
-+	u8 rsvd_0 : 2;
-+	u8 gnt_bt : 1;
-+	u8 ldpc : 1;
-+	u8 stbc : 1;
-+	u8 beamformed : 1;
-+#else
-+	u8 beamformed : 1;
-+	u8 stbc : 1;
-+	u8 ldpc : 1;
-+	u8 gnt_bt : 1;
-+	u8 rsvd_0 : 2;
-+	u8 band : 2;
-+#endif
-+
-+	/* @DW2 : Offset 8 */
-+	u8 channel_sec_lsb;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 channel_sec_msb : 2;
-+	u8 rsvd_1 : 2;
-+	u8 hw_antsw_occur_a : 1;
-+	u8 hw_antsw_occur_b : 1;
-+	u8 hw_antsw_occur_c : 1;
-+	u8 hw_antsw_occur_d : 1;
-+#else
-+	u8 hw_antsw_occur_d : 1;
-+	u8 hw_antsw_occur_c : 1;
-+	u8 hw_antsw_occur_b : 1;
-+	u8 hw_antsw_occur_a : 1;
-+	u8 rsvd_1 : 2;
-+	u8 channel_sec_msb : 2;
-+
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 antidx_a : 4;
-+	u8 antidx_b : 4;
-+#else
-+	u8 antidx_b : 4;
-+	u8 antidx_a : 4;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 antidx_c : 4;
-+	u8 antidx_d : 4;
-+#else
-+	u8 antidx_d : 4;
-+	u8 antidx_c : 4;
-+#endif
-+
-+	/* @DW3 : Offset 12 */
-+	u8 paid;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 paid_msb : 1;
-+	u8 gid : 6;
-+	u8 rsvd_3 : 1;
-+#else
-+	u8 rsvd_3 : 1;
-+	u8 gid : 6;
-+	u8 paid_msb : 1;
-+#endif
-+	u16 rsvd_4;
-+#if 0
-+	/*@
-+	u8		rsvd_4;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8		rsvd_5: 6;
-+	u8		rf_mode: 2;
-+#else
-+	u8		rf_mode: 2;
-+	u8		rsvd_5: 6;
-+#endif
-+*/
-+#endif
-+	/* @DW4 : Offset 16 */
-+	s8 rxevm[4]; /* s(8,1) */
-+
-+	/* @DW5 : Offset 20 */
-+	s8 cfo_tail[4]; /* s(8,7) */
-+
-+	/* @DW6 : Offset 24 */
-+	s8 rxsnr[4]; /* s(8,1) */
-+};
-+
-+__PACK struct phy_sts_rpt_jgr3_type2_3 {
-+/* Type2 is primary channel & type3 is secondary channel */
-+/* @DW0 and DW1: Offest 0 and Offset 4 */
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 page_num : 4;
-+	u8 pkt_cnt : 2;
-+	u8 channel_msb : 2;
-+#else
-+	u8 channel_msb : 2;
-+	u8 pkt_cnt : 2;
-+	u8 page_num : 4;
-+#endif
-+	u8 pwdb[4];
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 l_rxsc : 4;
-+	u8 ht_rxsc : 4;
-+#else
-+	u8 ht_rxsc : 4;
-+	u8 l_rxsc : 4;
-+#endif
-+	u8 channel_lsb;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 band : 2;
-+	u8 rsvd_0 : 2;
-+	u8 gnt_bt : 1;
-+	u8 ldpc : 1;
-+	u8 stbc : 1;
-+	u8 beamformed : 1;
-+#else
-+	u8 beamformed : 1;
-+	u8 stbc : 1;
-+	u8 ldpc : 1;
-+	u8 gnt_bt : 1;
-+	u8 rsvd_0 : 2;
-+	u8 band : 2;
-+#endif
-+
-+/* @DW2 : Offset 8 */
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 shift_l_map : 6;
-+	u8 rsvd_1 : 2;
-+#else
-+	u8 rsvd_1 : 2;
-+	u8 shift_l_map : 6;
-+#endif
-+	s8 pwed_th; /* @dynamic energy threshold S(8,2) */
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 agc_table_a : 4;
-+	u8 agc_table_b : 4;
-+#else
-+	u8 agc_table_b : 4;
-+	u8 agc_table_a : 4;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 agc_table_c : 4;
-+	u8 agc_table_d : 4;
-+#else
-+	u8 agc_table_d : 4;
-+	u8 agc_table_c : 4;
-+#endif
-+
-+	/* @DW3 : Offset 12 */
-+	u8 cnt_cca2agc_rdy; /* Time(ns) = cnt_cca2agc_ready*25 */
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 mp_gain_a : 6;
-+	u8 mp_gain_b_lsb : 2;
-+#else
-+	u8 mp_gain_b_lsb : 2;
-+	u8 mp_gain_a : 6;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 mp_gain_b_msb : 4;
-+	u8 mp_gain_c_lsb : 4;
-+#else
-+	u8 mp_gain_c_lsb : 4;
-+	u8 mp_gain_b_msb : 4;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 mp_gain_c_msb : 2;
-+	u8 avg_noise_pwr_lsb : 4;
-+	u8 rsvd_3 : 2;
-+	/* u8		r_rfmod:2; */
-+#else
-+	/* u8		r_rfmod:2; */
-+	u8 rsvd_3 : 2;
-+	u8 avg_noise_pwr_lsb : 4;
-+	u8 mp_gain_c_msb : 2;
-+#endif
-+	/* @DW4 ~ 5: offset 16 ~20 */
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 mp_gain_d : 6;
-+	u8 is_freq_select_fading : 1;
-+	u8 rsvd_2 : 1;
-+#else
-+	u8 rsvd_2 : 1;
-+	u8 is_freq_select_fading : 1;
-+	u8 mp_gain_d : 6;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 aagc_step_a : 2;
-+	u8 aagc_step_b : 2;
-+	u8 aagc_step_c : 2;
-+	u8 aagc_step_d : 2;
-+#else
-+	u8 aagc_step_d : 2;
-+	u8 aagc_step_c : 2;
-+	u8 aagc_step_b : 2;
-+	u8 aagc_step_a : 2;
-+#endif
-+	u8 ht_aagc_gain[4];
-+	u8 dagc_gain[4];
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 counter : 6;
-+	u8 syn_count_lsb : 2;
-+#else
-+	u8 syn_count_lsb : 2;
-+	u8 counter : 6;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 syn_count_msb : 3;
-+	u8 avg_noise_pwr_msb : 5;
-+#else
-+	u8 avg_noise_pwr_msb : 5;
-+	u8 syn_count_msb : 3;
-+#endif
-+};
-+
-+__PACK struct phy_sts_rpt_jgr3_type4 {
-+/* smart antenna */
-+/* @DW0 and DW1 : offset 0 and 4  */
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 page_num : 4;
-+	u8 pkt_cnt : 2;
-+	u8 channel_msb : 2;
-+#else
-+	u8 channel_msb : 2;
-+	u8 pkt_cnt : 2;
-+	u8 page_num : 4;
-+#endif
-+	u8 pwdb[4];
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 l_rxsc : 4;
-+	u8 ht_rxsc : 4;
-+#else
-+	u8 ht_rxsc : 4;
-+	u8 l_rxsc : 4;
-+#endif
-+	u8 channel_lsb;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 band : 2;
-+	u8 rsvd_0 : 2;
-+	u8 gnt_bt : 1;
-+	u8 ldpc : 1;
-+	u8 stbc : 1;
-+	u8 beamformed : 1;
-+#else
-+	u8 beamformed : 1;
-+	u8 stbc : 1;
-+	u8 ldpc : 1;
-+	u8 gnt_bt : 1;
-+	u8 rsvd_0 : 1;
-+	u8 band : 2;
-+#endif
-+
-+/* @DW2 : offset 8 */
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 bad_tone_cnt_min_eign_0 : 4;
-+	u8 bad_tone_cnt_cn_excess_0 : 4;
-+#else
-+	u8 bad_tone_cnt_cn_excess_0 : 4;
-+	u8 bad_tone_cnt_min_eign_0 : 4;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 training_done_a : 1;
-+	u8 training_done_b : 1;
-+	u8 training_done_c : 1;
-+	u8 training_done_d : 1;
-+	u8 hw_antsw_occur_a : 1;
-+	u8 hw_antsw_occur_b : 1;
-+	u8 hw_antsw_occur_c : 1;
-+	u8 hw_antsw_occur_d : 1;
-+#else
-+	u8 hw_antsw_occur_d : 1;
-+	u8 hw_antsw_occur_c : 1;
-+	u8 hw_antsw_occur_b : 1;
-+	u8 hw_antsw_occur_a : 1;
-+	u8 training_done_d : 1;
-+	u8 training_done_c : 1;
-+	u8 training_done_b : 1;
-+	u8 training_done_a : 1;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 antidx_a : 4;
-+	u8 antidx_b : 4;
-+#else
-+	u8 antidx_b : 4;
-+	u8 antidx_a : 4;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 antidx_c : 4;
-+	u8 antidx_d : 4;
-+#else
-+	u8 antidx_d : 4;
-+	u8 antidx_c : 4;
-+#endif
-+/* @DW3 : offset 12 */
-+	u8 tx_pkt_cnt;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 bad_tone_cnt_min_eign_1 : 4;
-+	u8 bad_tone_cnt_cn_excess_1 : 4;
-+#else
-+	u8 bad_tone_cnt_cn_excess_1 : 4;
-+	u8 bad_tone_cnt_min_eign_1 : 4;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 avg_cond_num_0 : 7;
-+	u8 avg_cond_num_1_lsb : 1;
-+#else
-+	u8 avg_cond_num_1_lsb : 1;
-+	u8 avg_cond_num_0 : 7;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 avg_cond_num_1_msb : 6;
-+	u8 rsvd_1 : 2;
-+#else
-+	u8 rsvd_1 : 2;
-+	u8 avg_cond_num_1_msb : 6;
-+#endif
-+
-+	/* @DW4 : offset 16 */
-+	s8 rxevm[4]; /* s(8,1) */
-+
-+	/* @DW5 : offset 20 */
-+	u8 eigenvalue[4]; /* @eigenvalue or eigenvalue of seg0 (in dB) */
-+
-+	/* @DW6 : ofset 24 */
-+	s8 rxsnr[4]; /* s(8,1) */
-+};
-+
-+__PACK struct phy_sts_rpt_jgr3_type5 {
-+/* @Debug */
-+/* @DW0 ane DW1 : offset 0 and 4 */
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 page_num : 4;
-+	u8 pkt_cnt : 2;
-+	u8 channel_msb : 2;
-+#else
-+	u8 channel_msb : 2;
-+	u8 pkt_cnt : 2;
-+	u8 page_num : 4;
-+#endif
-+	u8 pwdb[4];
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 l_rxsc : 4;
-+	u8 ht_rxsc : 4;
-+#else
-+	u8 ht_rxsc : 4;
-+	u8 l_rxsc : 4;
-+#endif
-+	u8 channel_lsb;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 band : 2;
-+	u8 rsvd_0 : 2;
-+	u8 gnt_bt : 1;
-+	u8 ldpc : 1;
-+	u8 stbc : 1;
-+	u8 beamformed : 1;
-+#else
-+	u8 beamformed : 1;
-+	u8 stbc : 1;
-+	u8 ldpc : 1;
-+	u8 gnt_bt : 1;
-+	u8 rsvd_0 : 2;
-+	u8 band : 2;
-+#endif
-+	/* @DW2 : offset 8 */
-+	u8 rsvd_1;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 rsvd_2 : 4;
-+	u8 hw_antsw_occur_a : 1;
-+	u8 hw_antsw_occur_b : 1;
-+	u8 hw_antsw_occur_c : 1;
-+	u8 hw_antsw_occur_d : 1;
-+#else
-+	u8 hw_antsw_occur_d : 1;
-+	u8 hw_antsw_occur_c : 1;
-+	u8 hw_antsw_occur_b : 1;
-+	u8 hw_antsw_occur_a : 1;
-+	u8 rsvd_2 : 4;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 antidx_a : 4;
-+	u8 antidx_b : 4;
-+#else
-+	u8 antidx_b : 4;
-+	u8 antidx_a : 4;
-+#endif
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 antidx_c : 4;
-+	u8 antidx_d : 4;
-+#else
-+	u8 antidx_d : 4;
-+	u8 antidx_c : 4;
-+#endif
-+	/* @DW3 : offset 12 */
-+	u8 tx_pkt_cnt;
-+#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 inf_pos_0_A_flg : 1;
-+	u8 inf_pos_1_A_flg : 1;
-+	u8 inf_pos_0_B_flg : 1;
-+	u8 inf_pos_1_B_flg : 1;
-+	u8 inf_pos_0_C_flg : 1;
-+	u8 inf_pos_1_C_flg : 1;
-+	u8 inf_pos_0_D_flg : 1;
-+	u8 inf_pos_1_D_flg : 1;
-+#else
-+	u8 inf_pos_1_D_flg : 1;
-+	u8 inf_pos_0_D_flg : 1;
-+	u8 inf_pos_1_C_flg : 1;
-+	u8 inf_pos_0_C_flg : 1;
-+	u8 inf_pos_1_B_flg : 1;
-+	u8 inf_pos_0_B_flg : 1;
-+	u8 inf_pos_1_A_flg : 1;
-+	u8 inf_pos_0_A_flg : 1;
-+#endif
-+	u8 rsvd_3;
-+	u8 rsvd_4;
-+	/* @DW4 : offset 16 */
-+	u8 inf_pos_0_a;
-+	u8 inf_pos_1_a;
-+	u8 inf_pos_0_b;
-+	u8 inf_pos_1_b;
-+	/* @DW5 : offset 20 */
-+	u8 inf_pos_0_c;
-+	u8 inf_pos_1_c;
-+	u8 inf_pos_0_d;
-+	u8 inf_pos_1_d;
-+};
-+
-+__PACK struct phy_sts_rpt_jgr3_ofdm_cmn {
-+	#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 page_num : 4;
-+	u8 pkt_cnt : 2;
-+	u8 channel_msb : 2;
-+	#else
-+	u8 channel_msb : 2;
-+	u8 pkt_cnt : 2;
-+	u8 page_num : 4;
-+	#endif
-+	u8 pwdb[4];
-+	#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 l_rxsc : 4;
-+	u8 ht_rxsc : 4;
-+	#else
-+	u8 ht_rxsc : 4;
-+	u8 l_rxsc : 4;
-+	#endif
-+	u8 channel_lsb;
-+	#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
-+	u8 band : 2;
-+	u8 rsvd_0 : 2;
-+	u8 gnt_bt : 1;
-+	u8 ldpc : 1;
-+	u8 stbc : 1;
-+	u8 beamformed : 1;
-+	#else
-+	u8 beamformed : 1;
-+	u8 stbc : 1;
-+	u8 ldpc : 1;
-+	u8 gnt_bt : 1;
-+	u8 rsvd_0 : 1;
-+	u8 band : 2;
-+	#endif
-+};
-+#endif /*@#ifdef PHYSTS_3RD_TYPE_SUPPORT*/
-+
-+#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH
-+void phydm_physts_auto_switch_jgr3_set(void *dm_void, boolean enable,
-+				       u8 bitmap_en);
-+#endif
-+
-+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
-+boolean
-+phydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate,
-+		      u8 *p_gid);
-+#endif
-+
-+void phydm_reset_phystatus_avg(struct dm_struct *dm);
-+
-+void phydm_reset_phystatus_statistic(struct dm_struct *dm);
-+
-+void phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id);
-+
-+void phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm);
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void phydm_normal_driver_rx_sniffer(
-+	struct dm_struct *dm,
-+	u8 *desc,
-+	PRT_RFD_STATUS rt_rfd_status,
-+	u8 *drv_info,
-+	u8 phy_status);
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+s32 phydm_signal_scale_mapping(struct dm_struct *dm, s32 curr_sig);
-+#endif
-+
-+boolean odm_phy_status_query(struct dm_struct *dm,
-+			     struct phydm_phyinfo_struct *phy_info,
-+			     u8 *phy_sts,
-+			     struct phydm_perpkt_info_struct *pktinfo);
-+
-+void phydm_rx_phy_status_init(void *dm_void);
-+
-+void phydm_physts_dbg(void *dm_void, char input[][16], u32 *_used,
-+		      char *output, u32 *_out_len);
-+
-+#endif /*@#ifndef	__HALHWOUTSRC_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_pmac_tx_setting.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_pmac_tx_setting.c
-new file mode 100644
-index 000000000000..296f39c39975
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_pmac_tx_setting.c
-@@ -0,0 +1,584 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+void phydm_start_cck_cont_tx_jgr3(void *dm_void,
-+				  struct phydm_pmac_info *tx_info)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
-+	u8 rate = tx_info->tx_rate; /* HW rate */
-+
-+	/* if CCK block on? */
-+	if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
-+		odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 0x1);
-+	if (dm->support_ic_type & ODM_RTL8723F) {
-+		odm_set_bb_reg(dm, R_0x2a08, BIT(21)|BIT(20), rate);
-+		odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0); /* turn on scrambler*/
-+	} else {
-+	/* Turn Off All Test mode */
-+	odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
-+
-+	odm_set_bb_reg(dm, R_0x1a00, 0x3000, rate);
-+	odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); /* transmit mode */
-+	odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/
-+
-+	/* Fix rate selection issue */
-+	odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x1);
-+	/* set RX weighting for path I & Q to 0 */
-+	odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
-+	/* set loopback mode */
-+	odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x1);
-+	}
-+	pmac_tx->cck_cont_tx = true;
-+	pmac_tx->ofdm_cont_tx = false;
-+}
-+
-+void phydm_stop_cck_cont_tx_jgr3(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
-+
-+	pmac_tx->cck_cont_tx = false;
-+	pmac_tx->ofdm_cont_tx = false;
-+
-+	if (dm->support_ic_type & ODM_RTL8723F) {
-+		/* @Disable pmac tx_en*/
-+		odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0); /* turn on scrambler*/
-+	} else {
-+		odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); /* normal mode */
-+		odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/
-+
-+		/* back to default */
-+		odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x0);
-+		odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
-+		odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x0);
-+	}
-+	/* BB Reset */
-+	odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
-+	odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
-+}
-+
-+void phydm_start_ofdm_cont_tx_jgr3(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
-+
-+	/* 1. if OFDM block on */
-+	if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
-+		odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 0x1);
-+	if (!(dm->support_ic_type & ODM_RTL8723F)) {
-+
-+		/* 2. set CCK test mode off, set to CCK normal mode */
-+		odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
-+
-+		/* 3. turn on scramble setting */
-+		odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
-+	}
-+	/* 4. Turn On Continue Tx and turn off the other test modes. */
-+	odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x1);
-+
-+	pmac_tx->cck_cont_tx = false;
-+	pmac_tx->ofdm_cont_tx = true;
-+}
-+
-+void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
-+
-+	pmac_tx->cck_cont_tx = false;
-+	pmac_tx->ofdm_cont_tx = false;
-+
-+	/* Turn Off All Test mode */
-+	odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
-+
-+	/* Delay 10 ms */
-+	ODM_delay_ms(10);
-+
-+	/* BB Reset */
-+	odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
-+	odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
-+}
-+
-+void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
-+	u32 tmp = 0;
-+
-+	odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x2); /* TX Stop */
-+	if (dm->support_ic_type & ODM_RTL8723F) {
-+		if (tx_info->mode == CONT_TX) {
-+			if (pmac_tx->is_cck_rate) {
-+				/* TX Stop */
-+				odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x1);
-+				/* Clear BB cont tx */
-+				odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x0);
-+				/* Clear PMAC cont tx */
-+				odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x0);
-+				/* Clear TX Stop */
-+				odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x0);
-+				phydm_stop_cck_cont_tx_jgr3(dm);
-+			} else 
-+				phydm_stop_ofdm_cont_tx_jgr3(dm);
-+		} else {
-+			if (pmac_tx->is_cck_rate) {
-+				/* packet_count = 0x1 */
-+				odm_set_bb_reg(dm, R_0x2a04, 0x03ff0000, 0x1);
-+				/* @Disable pmac tx_en*/
-+				odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
-+				/* @Enable pmac tx_en*/
-+				odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
-+				phydm_stop_cck_cont_tx_jgr3(dm);
-+			}
-+		} 
-+	}else {
-+		if (tx_info->mode == CONT_TX) {
-+		if (pmac_tx->is_cck_rate)
-+			phydm_stop_cck_cont_tx_jgr3(dm);
-+		else
-+			phydm_stop_ofdm_cont_tx_jgr3(dm);
-+		}
-+	}
-+}
-+
-+void phydm_set_mac_phy_txinfo_jgr3(void *dm_void,
-+				   struct phydm_pmac_info *tx_info)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
-+	u32 tmp = 0;
-+
-+	odm_set_bb_reg(dm, R_0xa58, 0x003f8000, tx_info->tx_rate);
-+
-+	/*0x900[1] ndp_sound */
-+	odm_set_bb_reg(dm, R_0x900, BIT(1), tx_info->ndp_sound);
-+
-+	#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	tx_info->m_stbc = tx_info->m_stbc - 1;
-+	#endif
-+	/*0x900[27:24] txsc [29:28] bw [31:30] m_stbc */
-+	tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |
-+		((tx_info->m_stbc) << 6);
-+	odm_set_bb_reg(dm, R_0x900, 0xff000000, tmp);
-+
-+	if (tx_info->tx_sc == 1) /*upper*/
-+		odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x5);
-+	else if (tx_info->tx_sc == 2) /*lower*/
-+		odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x6);
-+	else /* duplicate*/
-+		odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x0);
-+
-+	if (pmac_tx->is_ht_rate) {
-+		odm_set_bb_reg(dm, R_0x900, BIT(0), 0x1);
-+		odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0);
-+	} else if (pmac_tx->is_vht_rate) {
-+		odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0);
-+		odm_set_bb_reg(dm, R_0x900, BIT(2), 0x1);
-+	} else {
-+		odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0);
-+		odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0);
-+	}
-+
-+	/* for TX interval */
-+	odm_set_bb_reg(dm, R_0x9b8, MASKHWORD, tx_info->packet_period);
-+}
-+
-+void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
-+	u32 tmp = 0;
-+
-+	if (pmac_tx->is_cck_rate)
-+		return;
-+
-+	odm_set_bb_reg(dm, R_0x1eb4, 0xfffff, tx_info->packet_count);
-+
-+	/* L-SIG */
-+	tmp = BYTE_2_DWORD(0, tx_info->lsig[2], tx_info->lsig[1],
-+			   tx_info->lsig[0]);
-+	odm_set_bb_reg(dm, R_0x908, 0xffffff, tmp);
-+	if (pmac_tx->is_ht_rate) {
-+	/* HT SIG */
-+		tmp = BYTE_2_DWORD(0, tx_info->ht_sig[2], tx_info->ht_sig[1],
-+				   tx_info->ht_sig[0]);
-+		odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
-+		tmp = BYTE_2_DWORD(0, tx_info->ht_sig[5], tx_info->ht_sig[4],
-+				   tx_info->ht_sig[3]);
-+		odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
-+	} else if (pmac_tx->is_vht_rate) {
-+	/* VHT SIG A/B/serv_field/delimiter */
-+		tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[2],
-+				   tx_info->vht_sig_a[1],
-+				   tx_info->vht_sig_a[0]);
-+		odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
-+		tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[5],
-+				   tx_info->vht_sig_a[4],
-+				   tx_info->vht_sig_a[3]);
-+		odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
-+		tmp = BYTE_2_DWORD(tx_info->vht_sig_b[3], tx_info->vht_sig_b[2],
-+				   tx_info->vht_sig_b[1],
-+				   tx_info->vht_sig_b[0]);
-+		odm_set_bb_reg(dm, R_0x914, 0x1fffffff, tmp);
-+		odm_set_bb_reg(dm, R_0x938, 0xff00, tx_info->vht_sig_b_crc);
-+
-+		tmp = BYTE_2_DWORD(tx_info->vht_delimiter[3],
-+				   tx_info->vht_delimiter[2],
-+				   tx_info->vht_delimiter[1],
-+				   tx_info->vht_delimiter[0]);
-+		odm_set_bb_reg(dm, R_0x940, MASKDWORD, tmp);
-+	}
-+}
-+
-+void phydm_set_cck_preamble_hdr_jgr3(void *dm_void,
-+				     struct phydm_pmac_info *tx_info)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
-+	u32 tmp = 0;
-+	u8 rate = tx_info->tx_rate; /* HW rate */
-+
-+	if (!pmac_tx->is_cck_rate)
-+		return;
-+
-+	if (dm->support_ic_type & ODM_RTL8723F) {
-+		#if (RTL8723F_SUPPORT)
-+		odm_set_bb_reg(dm, R_0x2a04, 0x03ff0000, tx_info->packet_count);
-+		odm_set_bb_reg(dm, R_0x2a08, BIT(22), tx_info->service_field_bit2);
-+		odm_set_bb_reg(dm, R_0x2a08, BIT(21) | BIT(20), rate);
-+		odm_set_bb_reg(dm, R_0x2a08, 0x1ffff, tx_info->packet_length);
-+		/* turn on scrambler */
-+		odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0);
-+
-+		if (tx_info->is_short_preamble)
-+			odm_set_bb_reg(dm, R_0x2a08, BIT(19), 0x1);
-+		else
-+			odm_set_bb_reg(dm, R_0x2a08, BIT(19), 0x0);
-+		#endif
-+	} else {
-+		tmp = tx_info->packet_count | (tx_info->sfd << 16);
-+		odm_set_bb_reg(dm, R_0x1e64, MASKDWORD, tmp);
-+		tmp = tx_info->signal_field | (tx_info->service_field << 8) |
-+	      	(tx_info->length << 16);
-+		odm_set_bb_reg(dm, R_0x1e68, MASKDWORD, tmp);
-+		tmp = BYTE_2_DWORD(0, 0, tx_info->crc16[1], tx_info->crc16[0]);
-+		odm_set_bb_reg(dm, R_0x1e6c, MASKLWORD, tmp);
-+
-+		if (tx_info->is_short_preamble)
-+			odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x0);
-+		else
-+			odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x1);
-+	}
-+}
-+
-+void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
-+			 enum phydm_pmac_mode mode)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
-+
-+	if (mode == CONT_TX) {
-+		tx_info->packet_count = 1;
-+
-+		if (pmac_tx->is_cck_rate)
-+			phydm_start_cck_cont_tx_jgr3(dm, tx_info);
-+		else
-+			phydm_start_ofdm_cont_tx_jgr3(dm);
-+	}
-+}
-+
-+void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
-+
-+	odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x1); /*Turn on PMAC */
-+
-+	if (dm->support_ic_type & ODM_RTL8723F) {
-+		if (pmac_tx->is_cck_rate) {
-+			if (tx_info->mode == CONT_TX) {
-+				/* BB and PMAC cont tx */
-+				odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x1);
-+				odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x1);
-+			}
-+			/* TX CCK ON */
-+			odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
-+			odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
-+		} else {
-+			odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x0); /*TX Ofdm OFF */
-+			odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x4); /*TX Ofdm ON */
-+		}
-+	} else {
-+		/*mac scramble seed setting, only in 8198F */
-+		#if (RTL8198F_SUPPORT)
-+			if (dm->support_ic_type & ODM_RTL8198F)
-+				if (!odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
-+					odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x1);
-+		#endif
-+ 
-+		if (pmac_tx->is_cck_rate){
-+			odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x8); /*TX CCK ON */
-+			odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x0);
-+		} else {
-+			odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x4); /*TX Ofdm ON */
-+		}
-+	}
-+}
-+
-+void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
-+			    enum rf_path mpt_rf_path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
-+
-+	pmac_tx->is_cck_rate = phydm_is_cck_rate(dm, tx_info->tx_rate);
-+	pmac_tx->is_ofdm_rate = phydm_is_ofdm_rate(dm, tx_info->tx_rate);
-+	pmac_tx->is_ht_rate = phydm_is_ht_rate(dm, tx_info->tx_rate);
-+	pmac_tx->is_vht_rate = phydm_is_vht_rate(dm, tx_info->tx_rate);
-+	pmac_tx->path = mpt_rf_path;
-+
-+	if (!tx_info->en_pmac_tx) {
-+		phydm_stop_pmac_tx_jgr3(dm, tx_info);
-+		return;
-+	}
-+
-+	phydm_set_mode_jgr3(dm, tx_info, tx_info->mode);
-+
-+	if (pmac_tx->is_cck_rate)
-+		phydm_set_cck_preamble_hdr_jgr3(dm, tx_info);
-+	else
-+		phydm_set_sig_jgr3(dm, tx_info);
-+
-+	phydm_set_mac_phy_txinfo_jgr3(dm, tx_info);
-+	phydm_set_pmac_txon_jgr3(dm, tx_info);
-+}
-+
-+void phydm_set_tmac_tx_jgr3(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	/* Turn on TMAC */
-+	if (odm_get_bb_reg(dm, R_0x1d08, BIT(0)))
-+		odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x0);
-+
-+	/* mac scramble seed setting, only in 8198F */
-+	#if (RTL8198F_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8198F)
-+			if (odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
-+				odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x0);
-+	#endif
-+
-+	/* Turn on TMAC CCK */
-+	if (!(dm->support_ic_type & ODM_RTL8723F)) {
-+		if (!odm_get_bb_reg(dm, R_0x1a84, BIT(31)))
-+			odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x1);
-+	}
-+}
-+#endif
-+
-+void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		phydm_start_cck_cont_tx_jgr3(dm, tx_info);
-+	#endif
-+}
-+
-+void phydm_stop_cck_cont_tx(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		phydm_stop_cck_cont_tx_jgr3(dm);
-+	#endif
-+}
-+
-+void phydm_start_ofdm_cont_tx(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		phydm_start_ofdm_cont_tx_jgr3(dm);
-+	#endif
-+}
-+
-+void phydm_stop_ofdm_cont_tx(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		phydm_stop_ofdm_cont_tx_jgr3(dm);
-+	#endif
-+}
-+
-+void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
-+		       enum rf_path mpt_rf_path)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		phydm_set_pmac_tx_jgr3(dm, tx_info, mpt_rf_path);
-+	#endif
-+}
-+
-+void phydm_set_tmac_tx(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+		phydm_set_tmac_tx_jgr3(dm);
-+	#endif
-+}
-+
-+void phydm_pmac_tx_dbg(void *dm_void, char input[][16], u32 *_used,
-+		       char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pmac_info tx_info;
-+	char help[] = "-h";
-+	char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
-+	u32 var[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i = 0;
-+	u32 tx_cnt = 0x0;
-+	u8 poll_cnt = 0x0;
-+
-+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]);
-+
-+	if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
-+		return;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[pmac_tx] basic : {1} {rate_idx}(only 1M & 6M) {count}\n");
-+	} else {
-+		for (i = 1; i < 7; i++) {
-+			if (input[i + 1]) {
-+				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
-+					     &var[i]);
-+			}
-+		}
-+
-+		tx_info.en_pmac_tx = true;
-+		tx_info.mode = PKTS_TX;
-+		tx_info.ndp_sound = false;
-+		tx_info.bw = CHANNEL_WIDTH_20;
-+		tx_info.tx_sc = 0x0; /*duplicate*/
-+		tx_info.m_stbc = 0x0; /*disable*/
-+		tx_info.packet_period = 2000; /*d'500 us*/
-+		tx_info.tx_rate = (u8)var[1];
-+		tx_info.packet_count = (u32)var[2];
-+
-+		if (tx_info.tx_rate == ODM_RATE1M) {
-+			tx_info.signal_field = 0xa; /*rate = 1M*/
-+			tx_info.service_field = 0x0;
-+			if (dm->support_ic_type & ODM_RTL8723F) {
-+				tx_info.service_field_bit2= 0x1;
-+				tx_info.packet_length = 1000; /*1000 bytes*/
-+			}
-+			tx_info.length = 8000; /*d'8000 us=1000 bytes*/
-+			tx_info.crc16[0] = 0x60;
-+			tx_info.crc16[1] = 0x8e;
-+			/*long preamble*/
-+			tx_info.is_short_preamble = false;
-+			tx_info.sfd = 0xf3a0;
-+		} else if (tx_info.tx_rate == ODM_RATE6M) {
-+			/*l-sig[3:0] = rate = 6M = 0xb*/
-+			/*l-sig[16:5] = length = 1000 bytes*/
-+			/*l-sig[17] = parity = 1*/
-+			tx_info.lsig[0] = 0xb;
-+			tx_info.lsig[1] = 0x7d;
-+			tx_info.lsig[2] = 0x2;
-+		}
-+		phydm_print_rate_2_buff(dm, tx_info.tx_rate, dbg_buf,
-+					PHYDM_SNPRINT_SIZE);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "rate=%s, count=%d, pkt_interval=500(us), length=1000(bytes)\n",
-+			 dbg_buf, tx_info.packet_count);
-+
-+		if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "check trx idle failed, please try again.\n");
-+			return;
-+		}
-+
-+		phydm_reset_bb_hw_cnt(dm);
-+		phydm_set_pmac_tx_jgr3(dm, &tx_info, RF_PATH_A);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "pmac_tx enabled, please wait for tx_cnt = %d\n",
-+			 tx_info.packet_count);
-+		while (1) {
-+			if (phydm_is_cck_rate(dm, tx_info.tx_rate))
-+				tx_cnt = odm_get_bb_reg(dm, R_0x2de4,
-+							MASKLWORD);
-+			else
-+				tx_cnt = odm_get_bb_reg(dm, R_0x2de0,
-+							MASKLWORD);
-+
-+			if (tx_cnt >= tx_info.packet_count || poll_cnt >= 10)
-+				break;
-+
-+			ODM_delay_ms(100);
-+			poll_cnt++;
-+		}
-+
-+		if (tx_cnt < tx_info.packet_count)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "polling time out(1s), tx_cnt = %d\n", tx_cnt);
-+		else
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "pmac_tx finished, poll_cnt = %d\n", poll_cnt);
-+
-+		tx_info.en_pmac_tx = false;
-+		phydm_set_pmac_tx(dm, &tx_info, RF_PATH_A);
-+		phydm_set_tmac_tx(dm);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Stop pmac_tx and turn on true mac mode.\n");
-+
-+		phydm_stop_ic_trx(dm, PHYDM_REVERT);
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+#endif
-\ No newline at end of file
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_pmac_tx_setting.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_pmac_tx_setting.h
-new file mode 100644
-index 000000000000..532219ba66b1
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_pmac_tx_setting.h
-@@ -0,0 +1,111 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_PMAC_TX_SETTING_H__
-+#define __PHYDM_PMAC_TX_SETTING_H__
-+
-+/*2020.03.16 Fix TxInfo content in B mode*/
-+#define PMAC_TX_SETTING_VERSION "2.1"
-+
-+/* 1 ============================================================
-+ * 1  Definition
-+ * 1 ============================================================
-+ */
-+
-+/* 1 ============================================================
-+ * 1  structure
-+ * 1 ============================================================
-+ */
-+struct phydm_pmac_info {
-+	u8 en_pmac_tx:1; /*0: disable pmac 1: enable pmac */
-+	u8 mode:3; /*0: Packet TX 3:Continuous TX */
-+	u8 tx_rate; /*should be HW rate*/
-+	u8 tx_sc;
-+	u8 is_short_preamble:1;
-+	u8 ndp_sound:1;
-+	u8 bw:3; /* 0:20 1:40 2:80Mhz */
-+	u8 m_stbc; /* bSTBC + 1 for WIN/CE, bSTBC for others*/
-+	u16 packet_period;
-+	u32 packet_count;
-+	u32 packet_length;
-+	u8 packet_pattern;
-+	u16 sfd;
-+	u8 signal_field;
-+	u8 service_field;
-+	u8 service_field_bit2:1;
-+	u16 length;
-+	u8 crc16[2];
-+	u8 lsig[3];
-+	u8 ht_sig[6];
-+	u8 vht_sig_a[6];
-+	u8 vht_sig_b[4];
-+	u8 vht_sig_b_crc;
-+	u8 vht_delimiter[4];
-+};
-+
-+struct phydm_pmac_tx {
-+	boolean is_cck_rate;
-+	boolean is_ofdm_rate;
-+	boolean is_ht_rate;
-+	boolean is_vht_rate;
-+	boolean cck_cont_tx;
-+	boolean ofdm_cont_tx;
-+	u8 path;
-+};
-+
-+/* 1 ============================================================
-+ * 1  enumeration
-+ * 1 ============================================================
-+ */
-+
-+enum phydm_pmac_mode {
-+	NONE_TEST,
-+	PKTS_TX,
-+	PKTS_RX,
-+	CONT_TX,
-+	OFDM_SINGLE_TONE_TX,
-+	CCK_CARRIER_SIPPRESSION_TX
-+};
-+
-+/* 1 ============================================================
-+ * 1  function prototype
-+ * 1 ============================================================
-+ */
-+void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info);
-+
-+void phydm_stop_cck_cont_tx(void *dm_void);
-+
-+void phydm_start_ofdm_cont_tx(void *dm_void);
-+
-+void phydm_stop_ofdm_cont_tx(void *dm_void);
-+
-+void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
-+		       enum rf_path mpt_rf_path);
-+
-+void phydm_set_tmac_tx(void *dm_void);
-+
-+void phydm_pmac_tx_dbg(void *dm_void, char input[][16], u32 *_used,
-+		       char *output, u32 *_out_len);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_pow_train.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_pow_train.c
-new file mode 100644
-index 000000000000..56bc2411d252
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_pow_train.c
-@@ -0,0 +1,171 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef PHYDM_POWER_TRAINING_SUPPORT
-+void phydm_reset_pt_para(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
-+
-+	pt_t->pow_train_score = 0;
-+}
-+
-+void phydm_update_power_training_state(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
-+	struct phydm_fa_struct *fa_cnt = &dm->false_alm_cnt;
-+	struct ccx_info *ccx = &dm->dm_ccx_info;
-+	u32 pt_score_tmp = ENABLE_PT_SCORE;
-+	u32 crc_ok_cnt = 0;
-+	u32 cca_cnt = 0;
-+
-+	/*@is_disable_power_training is the key to H2C to disable/enable PT*/
-+	/*@if is_disable_power_training == 1, it will use largest power*/
-+	if (!(dm->support_ability & ODM_BB_PWR_TRAIN) || !dm->is_linked) {
-+		dm->is_disable_power_training = true;
-+		phydm_reset_pt_para(dm);
-+		return;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_PWR_TRAIN, "%s ======>\n", __func__);
-+
-+	if (pt_t->pt_state == DISABLE_POW_TRAIN) {
-+		dm->is_disable_power_training = true;
-+		phydm_reset_pt_para(dm);
-+		PHYDM_DBG(dm, DBG_PWR_TRAIN, "Disable PT\n");
-+		return;
-+
-+	} else if (pt_t->pt_state == ENABLE_POW_TRAIN) {
-+		dm->is_disable_power_training = false;
-+		phydm_reset_pt_para(dm);
-+		PHYDM_DBG(dm, DBG_PWR_TRAIN, "Enable PT\n");
-+		return;
-+
-+	} else if (pt_t->pt_state == DYNAMIC_POW_TRAIN) {
-+		PHYDM_DBG(dm, DBG_PWR_TRAIN, "Dynamic PT\n");
-+
-+		/* @Compute score */
-+		crc_ok_cnt = dm->phy_dbg_info.num_qry_phy_status_ofdm +
-+			     dm->phy_dbg_info.num_qry_phy_status_cck;
-+		cca_cnt = fa_cnt->cnt_cca_all;
-+#if 0
-+		if (crc_ok_cnt > cca_cnt) { /*invalid situation*/
-+			pt_score_tmp = KEEP_PRE_PT_SCORE;
-+			return;
-+		} else if ((crc_ok_cnt + (crc_ok_cnt >> 1)) <= cca_cnt) {
-+		/* @???crc_ok <= (2/3)*cca */
-+			pt_score_tmp = DISABLE_PT_SCORE;
-+			dm->is_disable_power_training = true;
-+		} else if ((crc_ok_cnt + (crc_ok_cnt >> 2)) <= cca_cnt) {
-+		/* @???crc_ok <= (4/5)*cca */
-+			pt_score_tmp = KEEP_PRE_PT_SCORE;
-+		} else {
-+		/* @???crc_ok > (4/5)*cca */
-+			pt_score_tmp = ENABLE_PT_SCORE;
-+			dm->is_disable_power_training = false;
-+		}
-+#endif
-+		if (ccx->nhm_ratio > 10) {
-+			pt_score_tmp = DISABLE_PT_SCORE;
-+			dm->is_disable_power_training = true;
-+		} else if (ccx->nhm_ratio < 5) {
-+			pt_score_tmp = ENABLE_PT_SCORE;
-+			dm->is_disable_power_training = false;
-+		} else {
-+			pt_score_tmp = KEEP_PRE_PT_SCORE;
-+		}
-+
-+		PHYDM_DBG(dm, DBG_PWR_TRAIN,
-+			  "pkt_cnt{ofdm,cck,all} = {%d, %d, %d}, cnt_cca_all=%d\n",
-+			  dm->phy_dbg_info.num_qry_phy_status_ofdm,
-+			  dm->phy_dbg_info.num_qry_phy_status_cck,
-+			  crc_ok_cnt, cca_cnt);
-+
-+		PHYDM_DBG(dm, DBG_PWR_TRAIN, "pt_score_tmp=%d\n", pt_score_tmp);
-+
-+		/* smoothing */
-+		pt_t->pow_train_score = (pt_score_tmp << 4) +
-+					(pt_t->pow_train_score >> 1) +
-+					(pt_t->pow_train_score >> 2);
-+
-+		pt_score_tmp = (pt_t->pow_train_score + 32) >> 6;
-+
-+		PHYDM_DBG(dm, DBG_PWR_TRAIN,
-+			  "pow_train_score = %d, score after smoothing = %d, is_disable_PT = %d\n",
-+			  pt_t->pow_train_score, pt_score_tmp,
-+			  dm->is_disable_power_training);
-+	} else {
-+		PHYDM_DBG(dm, DBG_PWR_TRAIN, "[%s]warning\n", __func__);
-+	}
-+}
-+
-+void phydm_pow_train_debug(
-+	void *dm_void,
-+	char input[][16],
-+	u32 *_used,
-+	char *output,
-+	u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 i;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{0: Auto PT, 1:enable, 2: disable}\n");
-+	} else {
-+		for (i = 0; i < 10; i++) {
-+			if (input[i + 1])
-+				PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
-+		}
-+
-+		if (var1[0] == 0)
-+			pt_t->pt_state = DYNAMIC_POW_TRAIN;
-+		else if (var1[0] == 1)
-+			pt_t->pt_state = ENABLE_POW_TRAIN;
-+		else if (var1[0] == 2)
-+			pt_t->pt_state = DISABLE_POW_TRAIN;
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "PT state = %d\n", pt_t->pt_state);
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_pow_train.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_pow_train.h
-new file mode 100644
-index 000000000000..f966607aa48e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_pow_train.h
-@@ -0,0 +1,84 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_POW_TRAIN_H__
-+#define __PHYDM_POW_TRAIN_H__
-+
-+#define POW_TRAIN_VERSION "1.0" /* @2017.07.0141  Dino, Add phydm_pow_train.h*/
-+
-+/****************************************************************
-+ * 1 ============================================================
-+ * 1  Definition
-+ * 1 ============================================================
-+ ***************************************************************/
-+
-+#ifdef PHYDM_POWER_TRAINING_SUPPORT
-+/****************************************************************
-+ * 1 ============================================================
-+ * 1  structure
-+ * 1 ============================================================
-+ ***************************************************************/
-+
-+struct phydm_pow_train_stuc {
-+	u8 pt_state;
-+	u32 pow_train_score;
-+};
-+
-+/****************************************************************
-+ * 1 ============================================================
-+ * 1  enumeration
-+ * 1 ============================================================
-+ ***************************************************************/
-+
-+enum pow_train_state {
-+	DYNAMIC_POW_TRAIN = 0,
-+	ENABLE_POW_TRAIN = 1,
-+	DISABLE_POW_TRAIN = 2
-+};
-+
-+enum power_training_score {
-+	DISABLE_PT_SCORE = 0,
-+	KEEP_PRE_PT_SCORE = 1,
-+	ENABLE_PT_SCORE = 2
-+};
-+
-+/****************************************************************
-+ * 1 ============================================================
-+ * 1  function prototype
-+ * 1 ============================================================
-+ ***************************************************************/
-+
-+void phydm_update_power_training_state(
-+	void *dm_void);
-+
-+void phydm_pow_train_debug(
-+	void *dm_void,
-+	char input[][16],
-+	u32 *_used,
-+	char *output,
-+	u32 *_out_len);
-+
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_pre_define.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_pre_define.h
-new file mode 100644
-index 000000000000..f3fdfaf6c104
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_pre_define.h
-@@ -0,0 +1,1020 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDMPREDEFINE_H__
-+#define __PHYDMPREDEFINE_H__
-+
-+/****************************************************************
-+ * 1 ============================================================
-+ * 1  Definition
-+ * 1 ============================================================
-+ ***************************************************************/
-+
-+#define PHYDM_CODE_BASE			"PHYDM_V049"
-+#define PHYDM_RELEASE_DATE		"20200720.0"
-+
-+/*PHYDM API status*/
-+#define	PHYDM_SET_FAIL			0
-+#define	PHYDM_SET_SUCCESS		1
-+#define	PHYDM_SET_NO_NEED		3
-+
-+/*PHYDM Set/Revert*/
-+#define	PHYDM_SET			1
-+#define	PHYDM_REVERT			2
-+
-+/* @Max path of IC */
-+/*N-IC*/
-+#define MAX_PATH_NUM_8188E		1
-+#define MAX_PATH_NUM_8188F		1
-+#define MAX_PATH_NUM_8710B		1
-+#define MAX_PATH_NUM_8723B		1
-+#define MAX_PATH_NUM_8723D		1
-+#define MAX_PATH_NUM_8703B		1
-+#define MAX_PATH_NUM_8192E		2
-+#define MAX_PATH_NUM_8192F		2
-+#define MAX_PATH_NUM_8197F		2
-+#define MAX_PATH_NUM_8198F		4
-+#define MAX_PATH_NUM_8197G		2
-+#define MAX_PATH_NUM_8721D		1
-+#define MAX_PATH_NUM_8710C		1
-+#define MAX_PATH_NUM_8723F		2
-+
-+/*@AC-IC*/
-+#define MAX_PATH_NUM_8821A		1
-+#define MAX_PATH_NUM_8881A		1
-+#define MAX_PATH_NUM_8821C		1
-+#define MAX_PATH_NUM_8195B		1
-+#define MAX_PATH_NUM_8812A		2
-+#define MAX_PATH_NUM_8822B		2
-+#define MAX_PATH_NUM_8822C		2
-+#define MAX_PATH_NUM_8814A		4
-+#define MAX_PATH_NUM_8814B		4
-+#define MAX_PATH_NUM_8814C		4
-+#define MAX_PATH_NUM_8195B		1
-+#define MAX_PATH_NUM_8812F		2
-+
-+/* @Max RF path */
-+#define PHYDM_MAX_RF_PATH_N		2	/*@For old N-series IC*/
-+#define PHYDM_MAX_RF_PATH		4
-+
-+/* number of entry */
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+	#ifdef DM_ODM_CE_MAC80211
-+		/* @defined in wifi.h (32+1) */
-+	#else
-+		#define	ASSOCIATE_ENTRY_NUM	MACID_NUM_SW_LIMIT  /* @Max size of asoc_entry[].*/
-+	#endif
-+	#define	ODM_ASSOCIATE_ENTRY_NUM	ASSOCIATE_ENTRY_NUM
-+#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	#define ASSOCIATE_ENTRY_NUM	NUM_STAT
-+	#define	ODM_ASSOCIATE_ENTRY_NUM	(ASSOCIATE_ENTRY_NUM + 1)
-+#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
-+	#ifdef CONFIG_CONCURRENT_MODE
-+		#define ASSOCIATE_ENTRY_NUM	NUM_STA + 2 /*@2 is for station mod*/
-+	#else
-+		#define ASSOCIATE_ENTRY_NUM	NUM_STA /*@8 is for max size of asoc_entry[].*/
-+	#endif
-+	#define	ODM_ASSOCIATE_ENTRY_NUM	ASSOCIATE_ENTRY_NUM
-+#else
-+	#define ODM_ASSOCIATE_ENTRY_NUM	(((ASSOCIATE_ENTRY_NUM + 1) * 3) + 1)
-+#endif
-+
-+/* @-----MGN rate--------------------------------- */
-+
-+enum PDM_RATE_TYPE {
-+	PDM_1SS			= 1,	/*VHT/HT 1SS*/
-+	PDM_2SS			= 2,	/*VHT/HT 2SS*/
-+	PDM_3SS			= 3,	/*VHT/HT 3SS*/
-+	PDM_4SS			= 4,	/*VHT/HT 4SS*/
-+	PDM_CCK			= 11,	/*@B*/
-+	PDM_OFDM		= 12	/*@G*/
-+};
-+
-+enum ODM_MGN_RATE {
-+	ODM_MGN_1M		= 0x02,
-+	ODM_MGN_2M		= 0x04,
-+	ODM_MGN_5_5M		= 0x0B,
-+	ODM_MGN_6M		= 0x0C,
-+	ODM_MGN_9M		= 0x12,
-+	ODM_MGN_11M		= 0x16,
-+	ODM_MGN_12M		= 0x18,
-+	ODM_MGN_18M		= 0x24,
-+	ODM_MGN_24M		= 0x30,
-+	ODM_MGN_36M		= 0x48,
-+	ODM_MGN_48M		= 0x60,
-+	ODM_MGN_54M		= 0x6C,
-+	ODM_MGN_MCS32		= 0x7F,
-+	ODM_MGN_MCS0		= 0x80,
-+	ODM_MGN_MCS1,
-+	ODM_MGN_MCS2,
-+	ODM_MGN_MCS3,
-+	ODM_MGN_MCS4,
-+	ODM_MGN_MCS5,
-+	ODM_MGN_MCS6,
-+	ODM_MGN_MCS7		= 0x87,
-+	ODM_MGN_MCS8,
-+	ODM_MGN_MCS9,
-+	ODM_MGN_MCS10,
-+	ODM_MGN_MCS11,
-+	ODM_MGN_MCS12,
-+	ODM_MGN_MCS13,
-+	ODM_MGN_MCS14,
-+	ODM_MGN_MCS15,
-+	ODM_MGN_MCS16		= 0x90,
-+	ODM_MGN_MCS17,
-+	ODM_MGN_MCS18,
-+	ODM_MGN_MCS19,
-+	ODM_MGN_MCS20,
-+	ODM_MGN_MCS21,
-+	ODM_MGN_MCS22,
-+	ODM_MGN_MCS23,
-+	ODM_MGN_MCS24		= 0x98,
-+	ODM_MGN_MCS25,
-+	ODM_MGN_MCS26,
-+	ODM_MGN_MCS27,
-+	ODM_MGN_MCS28,
-+	ODM_MGN_MCS29,
-+	ODM_MGN_MCS30,
-+	ODM_MGN_MCS31,
-+	ODM_MGN_VHT1SS_MCS0	= 0xa0,
-+	ODM_MGN_VHT1SS_MCS1,
-+	ODM_MGN_VHT1SS_MCS2,
-+	ODM_MGN_VHT1SS_MCS3,
-+	ODM_MGN_VHT1SS_MCS4,
-+	ODM_MGN_VHT1SS_MCS5,
-+	ODM_MGN_VHT1SS_MCS6,
-+	ODM_MGN_VHT1SS_MCS7,
-+	ODM_MGN_VHT1SS_MCS8,
-+	ODM_MGN_VHT1SS_MCS9,
-+	ODM_MGN_VHT2SS_MCS0	= 0xaa,
-+	ODM_MGN_VHT2SS_MCS1	= 0xab,
-+	ODM_MGN_VHT2SS_MCS2,
-+	ODM_MGN_VHT2SS_MCS3,
-+	ODM_MGN_VHT2SS_MCS4,
-+	ODM_MGN_VHT2SS_MCS5	= 0xaf,
-+	ODM_MGN_VHT2SS_MCS6	= 0xb0,
-+	ODM_MGN_VHT2SS_MCS7,
-+	ODM_MGN_VHT2SS_MCS8,
-+	ODM_MGN_VHT2SS_MCS9	= 0xb3,
-+	ODM_MGN_VHT3SS_MCS0	= 0xb4,
-+	ODM_MGN_VHT3SS_MCS1,
-+	ODM_MGN_VHT3SS_MCS2,
-+	ODM_MGN_VHT3SS_MCS3,
-+	ODM_MGN_VHT3SS_MCS4,
-+	ODM_MGN_VHT3SS_MCS5,
-+	ODM_MGN_VHT3SS_MCS6,
-+	ODM_MGN_VHT3SS_MCS7	= 0xbb,
-+	ODM_MGN_VHT3SS_MCS8	= 0xbc,
-+	ODM_MGN_VHT3SS_MCS9	= 0xbd,
-+	ODM_MGN_VHT4SS_MCS0	= 0xbe,
-+	ODM_MGN_VHT4SS_MCS1,
-+	ODM_MGN_VHT4SS_MCS2,
-+	ODM_MGN_VHT4SS_MCS3,
-+	ODM_MGN_VHT4SS_MCS4,
-+	ODM_MGN_VHT4SS_MCS5,
-+	ODM_MGN_VHT4SS_MCS6,
-+	ODM_MGN_VHT4SS_MCS7,
-+	ODM_MGN_VHT4SS_MCS8,
-+	ODM_MGN_VHT4SS_MCS9	= 0xc7,
-+	ODM_MGN_UNKNOWN
-+};
-+
-+#define	ODM_MGN_MCS0_SG		0xc0
-+#define	ODM_MGN_MCS1_SG		0xc1
-+#define	ODM_MGN_MCS2_SG		0xc2
-+#define	ODM_MGN_MCS3_SG		0xc3
-+#define	ODM_MGN_MCS4_SG		0xc4
-+#define	ODM_MGN_MCS5_SG		0xc5
-+#define	ODM_MGN_MCS6_SG		0xc6
-+#define	ODM_MGN_MCS7_SG		0xc7
-+#define	ODM_MGN_MCS8_SG		0xc8
-+#define	ODM_MGN_MCS9_SG		0xc9
-+#define	ODM_MGN_MCS10_SG	0xca
-+#define	ODM_MGN_MCS11_SG	0xcb
-+#define	ODM_MGN_MCS12_SG	0xcc
-+#define	ODM_MGN_MCS13_SG	0xcd
-+#define	ODM_MGN_MCS14_SG	0xce
-+#define	ODM_MGN_MCS15_SG	0xcf
-+
-+/* @-----DESC rate--------------------------------- */
-+
-+#define ODM_RATEMCS15_SG	0x1c
-+#define ODM_RATEMCS32		0x20
-+
-+enum phydm_ctrl_info_rate {
-+	ODM_RATE1M		= 0x00,
-+	ODM_RATE2M		= 0x01,
-+	ODM_RATE5_5M		= 0x02,
-+	ODM_RATE11M		= 0x03,
-+/* OFDM Rates, TxHT = 0 */
-+	ODM_RATE6M		= 0x04,
-+	ODM_RATE9M		= 0x05,
-+	ODM_RATE12M		= 0x06,
-+	ODM_RATE18M		= 0x07,
-+	ODM_RATE24M		= 0x08,
-+	ODM_RATE36M		= 0x09,
-+	ODM_RATE48M		= 0x0A,
-+	ODM_RATE54M		= 0x0B,
-+/* @MCS Rates, TxHT = 1 */
-+	ODM_RATEMCS0		= 0x0C,
-+	ODM_RATEMCS1		= 0x0D,
-+	ODM_RATEMCS2		= 0x0E,
-+	ODM_RATEMCS3		= 0x0F,
-+	ODM_RATEMCS4		= 0x10,
-+	ODM_RATEMCS5		= 0x11,
-+	ODM_RATEMCS6		= 0x12,
-+	ODM_RATEMCS7		= 0x13,
-+	ODM_RATEMCS8		= 0x14,
-+	ODM_RATEMCS9		= 0x15,
-+	ODM_RATEMCS10		= 0x16,
-+	ODM_RATEMCS11		= 0x17,
-+	ODM_RATEMCS12		= 0x18,
-+	ODM_RATEMCS13		= 0x19,
-+	ODM_RATEMCS14		= 0x1A,
-+	ODM_RATEMCS15		= 0x1B,
-+	ODM_RATEMCS16		= 0x1C,
-+	ODM_RATEMCS17		= 0x1D,
-+	ODM_RATEMCS18		= 0x1E,
-+	ODM_RATEMCS19		= 0x1F,
-+	ODM_RATEMCS20		= 0x20,
-+	ODM_RATEMCS21		= 0x21,
-+	ODM_RATEMCS22		= 0x22,
-+	ODM_RATEMCS23		= 0x23,
-+	ODM_RATEMCS24		= 0x24,
-+	ODM_RATEMCS25		= 0x25,
-+	ODM_RATEMCS26		= 0x26,
-+	ODM_RATEMCS27		= 0x27,
-+	ODM_RATEMCS28		= 0x28,
-+	ODM_RATEMCS29		= 0x29,
-+	ODM_RATEMCS30		= 0x2A,
-+	ODM_RATEMCS31		= 0x2B,
-+	ODM_RATEVHTSS1MCS0	= 0x2C,
-+	ODM_RATEVHTSS1MCS1	= 0x2D,
-+	ODM_RATEVHTSS1MCS2	= 0x2E,
-+	ODM_RATEVHTSS1MCS3	= 0x2F,
-+	ODM_RATEVHTSS1MCS4	= 0x30,
-+	ODM_RATEVHTSS1MCS5	= 0x31,
-+	ODM_RATEVHTSS1MCS6	= 0x32,
-+	ODM_RATEVHTSS1MCS7	= 0x33,
-+	ODM_RATEVHTSS1MCS8	= 0x34,
-+	ODM_RATEVHTSS1MCS9	= 0x35,
-+	ODM_RATEVHTSS2MCS0	= 0x36,
-+	ODM_RATEVHTSS2MCS1	= 0x37,
-+	ODM_RATEVHTSS2MCS2	= 0x38,
-+	ODM_RATEVHTSS2MCS3	= 0x39,
-+	ODM_RATEVHTSS2MCS4	= 0x3A,
-+	ODM_RATEVHTSS2MCS5	= 0x3B,
-+	ODM_RATEVHTSS2MCS6	= 0x3C,
-+	ODM_RATEVHTSS2MCS7	= 0x3D,
-+	ODM_RATEVHTSS2MCS8	= 0x3E,
-+	ODM_RATEVHTSS2MCS9	= 0x3F,
-+	ODM_RATEVHTSS3MCS0	= 0x40,
-+	ODM_RATEVHTSS3MCS1	= 0x41,
-+	ODM_RATEVHTSS3MCS2	= 0x42,
-+	ODM_RATEVHTSS3MCS3	= 0x43,
-+	ODM_RATEVHTSS3MCS4	= 0x44,
-+	ODM_RATEVHTSS3MCS5	= 0x45,
-+	ODM_RATEVHTSS3MCS6	= 0x46,
-+	ODM_RATEVHTSS3MCS7	= 0x47,
-+	ODM_RATEVHTSS3MCS8	= 0x48,
-+	ODM_RATEVHTSS3MCS9	= 0x49,
-+	ODM_RATEVHTSS4MCS0	= 0x4A,
-+	ODM_RATEVHTSS4MCS1	= 0x4B,
-+	ODM_RATEVHTSS4MCS2	= 0x4C,
-+	ODM_RATEVHTSS4MCS3	= 0x4D,
-+	ODM_RATEVHTSS4MCS4	= 0x4E,
-+	ODM_RATEVHTSS4MCS5	= 0x4F,
-+	ODM_RATEVHTSS4MCS6	= 0x50,
-+	ODM_RATEVHTSS4MCS7	= 0x51,
-+	ODM_RATEVHTSS4MCS8	= 0x52,
-+	ODM_RATEVHTSS4MCS9	= 0x53,
-+};
-+
-+enum phydm_legacy_spec_rate {
-+	PHYDM_SPEC_RATE_6M	= 0xb,
-+	PHYDM_SPEC_RATE_9M	= 0xf,
-+	PHYDM_SPEC_RATE_12M	= 0xa,
-+	PHYDM_SPEC_RATE_18M	= 0xe,
-+	PHYDM_SPEC_RATE_24M	= 0x9,
-+	PHYDM_SPEC_RATE_36M	= 0xd,
-+	PHYDM_SPEC_RATE_48M	= 0x8,
-+	PHYDM_SPEC_RATE_54M	= 0xc
-+};
-+
-+#define NUM_RATE_AC_4SS (ODM_RATEVHTSS4MCS9 + 1)
-+#define NUM_RATE_AC_3SS (ODM_RATEVHTSS3MCS9 + 1)
-+#define NUM_RATE_AC_2SS (ODM_RATEVHTSS2MCS9 + 1)
-+#define NUM_RATE_AC_1SS (ODM_RATEVHTSS1MCS9 + 1)
-+#define NUM_RATE_N_4SS (ODM_RATEMCS31 + 1)
-+#define NUM_RATE_N_3SS (ODM_RATEMCS23 + 1)
-+#define NUM_RATE_N_2SS (ODM_RATEMCS15 + 1)
-+#define NUM_RATE_N_1SS (ODM_RATEMCS7 + 1)
-+
-+/*Define from larger rate size to small rate size, DO NOT change the position*/
-+/*[AC-4SS]*/
-+#if (RTL8814B_SUPPORT)
-+	#define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS
-+/*[AC-3SS]*/
-+#elif (RTL8814A_SUPPORT)
-+	#define PHY_NUM_RATE_IDX NUM_RATE_AC_3SS
-+/*[AC-2SS]*/
-+#elif (RTL8812A_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\
-+	RTL8812F_SUPPORT)
-+	#define PHY_NUM_RATE_IDX NUM_RATE_AC_2SS
-+/*[AC-1SS]*/
-+#elif (RTL8881A_SUPPORT || RTL8821A_SUPPORT || RTL8821C_SUPPORT ||\
-+	RTL8195B_SUPPORT)
-+	#define PHY_NUM_RATE_IDX NUM_RATE_AC_1SS
-+/*[N-4SS]*/
-+#elif (RTL8198F_SUPPORT)
-+	#define PHY_NUM_RATE_IDX NUM_RATE_N_4SS
-+/*[N-2SS]*/
-+#elif (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\
-+	RTL8197G_SUPPORT)
-+	#define PHY_NUM_RATE_IDX NUM_RATE_N_2SS
-+/*[N-1SS]*/
-+#elif (RTL8723B_SUPPORT || RTL8703B_SUPPORT || RTL8188E_SUPPORT || \
-+	RTL8188F_SUPPORT || RTL8723D_SUPPORT || RTL8195A_SUPPORT ||\
-+	RTL8710B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT || RTL8723F_SUPPORT)
-+	#define PHY_NUM_RATE_IDX NUM_RATE_N_1SS
-+#else
-+	#define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	#define CONFIG_SFW_SUPPORTED
-+#endif
-+
-+/****************************************************************
-+ * 1 ============================================================
-+ * 1  enumeration
-+ * 1 ============================================================
-+ ***************************************************************/
-+
-+/*	ODM_CMNINFO_INTERFACE */
-+enum odm_interface {
-+	ODM_ITRF_PCIE	=	0x1,
-+	ODM_ITRF_USB	=	0x2,
-+	ODM_ITRF_SDIO	=	0x4,
-+	ODM_ITRF_ALL	=	0x7,
-+};
-+
-+enum phydm_api_host {
-+	RUN_IN_FW		= 0,
-+	RUN_IN_DRIVER		= 1,
-+};
-+
-+/*@========[Run time IC flag] ===================================*/
-+
-+enum phydm_ic {
-+	ODM_RTL8188E	=	BIT(0),
-+	ODM_RTL8812	=	BIT(1),
-+	ODM_RTL8821	=	BIT(2),
-+	ODM_RTL8192E	=	BIT(3),
-+	ODM_RTL8723B	=	BIT(4),
-+	ODM_RTL8814A	=	BIT(5),
-+	ODM_RTL8881A	=	BIT(6),
-+	ODM_RTL8822B	=	BIT(7),
-+	ODM_RTL8703B	=	BIT(8),
-+	ODM_RTL8195A	=	BIT(9),
-+	ODM_RTL8188F	=	BIT(10),
-+	ODM_RTL8723D	=	BIT(11),
-+	ODM_RTL8197F	=	BIT(12),
-+	ODM_RTL8821C	=	BIT(13),
-+	ODM_RTL8814B	=	BIT(14),
-+	ODM_RTL8198F	=	BIT(15),
-+	ODM_RTL8710B	=	BIT(16),
-+	ODM_RTL8192F	=	BIT(17),
-+	ODM_RTL8822C	=	BIT(18),
-+	ODM_RTL8195B	=	BIT(19),
-+	ODM_RTL8812F	=	BIT(20),
-+	ODM_RTL8197G	=	BIT(21),
-+	ODM_RTL8721D	=	BIT(22),
-+	ODM_RTL8710C	=	BIT(23),
-+	ODM_RTL8723F	=	BIT(24)
-+};
-+
-+#define ODM_IC_N_1SS		(ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B |\
-+				 ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8195A |\
-+				 ODM_RTL8710B | ODM_RTL8721D | ODM_RTL8710C)
-+#define ODM_IC_N_2SS		(ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F)
-+#define ODM_IC_N_3SS		0
-+#define ODM_IC_N_4SS		0
-+
-+#define ODM_IC_AC_1SS		(ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C |\
-+				 ODM_RTL8195B)
-+#define ODM_IC_AC_2SS		(ODM_RTL8812 | ODM_RTL8822B)
-+#define ODM_IC_AC_3SS		0
-+#define ODM_IC_AC_4SS		(ODM_RTL8814A)
-+
-+#define ODM_IC_JGR3_1SS		(ODM_RTL8723F)
-+#define ODM_IC_JGR3_2SS		(ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)
-+#define ODM_IC_JGR3_3SS		0
-+#define ODM_IC_JGR3_4SS		(ODM_RTL8198F | ODM_RTL8814B)
-+
-+/*@====the following macro DO NOT need to update when adding a new IC======= */
-+#define ODM_IC_1SS		(ODM_IC_N_1SS | ODM_IC_AC_1SS | ODM_IC_JGR3_1SS)
-+#define ODM_IC_2SS		(ODM_IC_N_2SS | ODM_IC_AC_2SS | ODM_IC_JGR3_2SS)
-+#define ODM_IC_3SS		(ODM_IC_N_3SS | ODM_IC_AC_3SS | ODM_IC_JGR3_3SS)
-+#define ODM_IC_4SS		(ODM_IC_N_4SS | ODM_IC_AC_4SS | ODM_IC_JGR3_4SS)
-+
-+#define PHYDM_IC_ABOVE_1SS	(ODM_IC_1SS | ODM_IC_2SS | ODM_IC_3SS |\
-+				 ODM_IC_4SS)
-+#define PHYDM_IC_ABOVE_2SS	(ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS)
-+#define PHYDM_IC_ABOVE_3SS	(ODM_IC_3SS | ODM_IC_4SS)
-+#define PHYDM_IC_ABOVE_4SS	ODM_IC_4SS
-+
-+#define ODM_IC_11N_SERIES	(ODM_IC_N_1SS | ODM_IC_N_2SS | ODM_IC_N_3SS |\
-+				 ODM_IC_N_4SS)
-+#define ODM_IC_11AC_SERIES	(ODM_IC_AC_1SS | ODM_IC_AC_2SS |\
-+				 ODM_IC_AC_3SS | ODM_IC_AC_4SS)
-+#define ODM_IC_JGR3_SERIES	(ODM_IC_JGR3_1SS | ODM_IC_JGR3_2SS |\
-+				 ODM_IC_JGR3_3SS | ODM_IC_JGR3_4SS)
-+/*@====================================================*/
-+
-+#define ODM_IC_11AC_1_SERIES	(ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)
-+#define ODM_IC_11AC_2_SERIES	(ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C |\
-+				 ODM_RTL8195B)
-+
-+/*@[Phy status type]*/
-+#define PHYSTS_2ND_TYPE_IC	(ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D |\
-+				 ODM_RTL8821C | ODM_RTL8710B | ODM_RTL8195B |\
-+				 ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C)
-+#define PHYSTS_3RD_TYPE_IC	(ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8822C |\
-+				 ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8723F)
-+/*@[FW Type]*/
-+#define PHYDM_IC_8051_SERIES	(ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 |\
-+				 ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B |\
-+				 ODM_RTL8188F | ODM_RTL8192F | ODM_RTL8721D |\
-+				 ODM_RTL8710C)
-+#define PHYDM_IC_3081_SERIES	(ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\
-+				 ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\
-+				 ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8814B |\
-+				 ODM_RTL8197G | ODM_RTL8723F)
-+/*@[LA mode]*/
-+#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\
-+				  ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\
-+				  ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F |\
-+				  ODM_RTL8195B | ODM_RTL8814B | ODM_RTL8197G | ODM_RTL8723F)
-+/*@[BF]*/
-+#define ODM_IC_TXBF_SUPPORT	(ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 |\
-+				 ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B |\
-+				 ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B |\
-+				 ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |\
-+				 ODM_RTL8814B | ODM_RTL8197G)
-+#define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B |\
-+				  ODM_RTL8195B | ODM_RTL8198F | ODM_RTL8822C |\
-+				  ODM_RTL8812F | ODM_RTL8723F)
-+#define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B | ODM_RTL8198F |\
-+				  ODM_RTL8822C | ODM_RTL8812F)
-+
-+#define PHYDM_IC_SUPPORT_MU (PHYDM_IC_SUPPORT_MU_BFEE |\
-+				PHYDM_IC_SUPPORT_MU_BFER)
-+/*@[PHYDM API]*/
-+#define CMN_API_SUPPORT_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |\
-+			    ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\
-+			    ODM_RTL8198F | ODM_RTL8812F | ODM_RTL8814B |\
-+			    ODM_RTL8197G | ODM_RTL8721D | ODM_RTL8710C | ODM_RTL8723F)
-+
-+/* fw offload ability*/
-+#define PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD (ODM_RTL8814A | ODM_RTL8822B |\
-+					   ODM_RTL8821C | ODM_RTL8822C)
-+
-+/* halmac offload ability*/
-+#define PHYDM_IC_SUPPORT_HALMAC_PARAM_OFFLOAD (ODM_RTL8822C | ODM_RTL8812F |\
-+					       ODM_RTL8814B | ODM_RTL8723F)
-+
-+/*[CCX]*/
-+#define PHYDM_IC_SUPPORT_FAHM	(ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8198F |\
-+				 ODM_RTL8814B | ODM_RTL8822C | ODM_RTL8812F |\
-+				 ODM_RTL8197G | ODM_RTL8723F)
-+#define PHYDM_IC_SUPPORT_IFS_CLM (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8723F)
-+
-+/*[ARFR]*/
-+/*for MAC HW control rate_id=0~12 and 2.4g vht mode(1ss/2ss) support*/
-+#define PHYDM_IC_RATEID_IDX_TYPE2 (ODM_RTL8822B | ODM_RTL8822C | ODM_RTL8195B |\
-+				  ODM_RTL8821C)
-+
-+/*@========[Compile time IC flag] ========================*/
-+/*@========[AC-3/AC/N Support] ===========================*/
-+
-+#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
-+	RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
-+	#define PHYDM_IC_JGR3_SERIES_SUPPORT
-+	#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT)
-+		#define PHYDM_IC_JGR3_80M_SUPPORT
-+	#endif
-+#endif
-+
-+#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\
-+	RTL8723F_SUPPORT)
-+	#define PHYDM_IC_HALMAC_PARAM_SUPPORT
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+
-+	#ifdef RTK_AC_SUPPORT
-+	#define ODM_IC_11AC_SERIES_SUPPORT	1
-+	#else
-+	#define ODM_IC_11AC_SERIES_SUPPORT	0
-+	#endif
-+
-+	#define ODM_IC_11N_SERIES_SUPPORT	1
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+	#define ODM_IC_11AC_SERIES_SUPPORT	1
-+	#define ODM_IC_11N_SERIES_SUPPORT	1
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+
-+	#define ODM_IC_11AC_SERIES_SUPPORT	1
-+	#define ODM_IC_11N_SERIES_SUPPORT	1
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+
-+	#define ODM_IC_11AC_SERIES_SUPPORT		1
-+	#define ODM_IC_11N_SERIES_SUPPORT			1
-+
-+#else /*ODM_CE*/
-+
-+	#if (RTL8188E_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\
-+	     RTL8195A_SUPPORT || RTL8703B_SUPPORT || RTL8188F_SUPPORT ||\
-+	     RTL8723D_SUPPORT || RTL8197F_SUPPORT || RTL8710B_SUPPORT ||\
-+	     RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
-+		#define ODM_IC_11N_SERIES_SUPPORT	1
-+		#define ODM_IC_11AC_SERIES_SUPPORT	0
-+	#else
-+		#define ODM_IC_11N_SERIES_SUPPORT	0
-+		#define ODM_IC_11AC_SERIES_SUPPORT	1
-+	#endif
-+#endif
-+
-+/*@===IC SS Compile Flag, prepare for code size reduction==============*/
-+#if (RTL8188E_SUPPORT || RTL8188F_SUPPORT || RTL8723B_SUPPORT ||\
-+	RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8881A_SUPPORT ||\
-+	RTL8821A_SUPPORT || RTL8821C_SUPPORT || RTL8195A_SUPPORT ||\
-+	RTL8710B_SUPPORT || RTL8195B_SUPPORT || RTL8721D_SUPPORT ||\
-+	RTL8710C_SUPPORT || RTL8723F_SUPPORT)
-+
-+	#define PHYDM_COMPILE_IC_1SS
-+#endif
-+
-+#if (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8812A_SUPPORT ||\
-+	RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8822C_SUPPORT ||\
-+	RTL8812F_SUPPORT || RTL8197G_SUPPORT)
-+	#define PHYDM_COMPILE_IC_2SS
-+#endif
-+
-+/*@#define PHYDM_COMPILE_IC_3SS*/
-+
-+#if ((RTL8814B_SUPPORT) || (RTL8814A_SUPPORT) || (RTL8198F_SUPPORT))
-+	#define PHYDM_COMPILE_IC_4SS
-+#endif
-+
-+/*@==[ABOVE N-SS COMPILE FLAG]=================================================*/
-+#if (defined(PHYDM_COMPILE_IC_1SS) || defined(PHYDM_COMPILE_IC_2SS) ||\
-+	defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS))
-+	#define PHYDM_COMPILE_ABOVE_1SS
-+#endif
-+
-+#if (defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) ||\
-+	defined(PHYDM_COMPILE_IC_4SS))
-+	#define PHYDM_COMPILE_ABOVE_2SS
-+#endif
-+
-+#if (defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS))
-+	#define PHYDM_COMPILE_ABOVE_3SS
-+#endif
-+
-+#if (defined(PHYDM_COMPILE_IC_4SS))
-+	#define PHYDM_COMPILE_ABOVE_4SS
-+#endif
-+
-+/*@==[Max RF path number among all compiled ICs]==============================*/
-+/*@ ex: support 8814B & 8821C => size=4 */
-+/*@ ex: support 8822C & 8821C => size=2 */
-+#if (defined(PHYDM_COMPILE_IC_4SS))
-+	#define RF_PATH_MEM_SIZE 4
-+#elif (defined(PHYDM_COMPILE_IC_3SS))
-+	#define RF_PATH_MEM_SIZE 3
-+#elif (defined(PHYDM_COMPILE_IC_2SS))
-+	#define RF_PATH_MEM_SIZE 2
-+#else
-+	#define RF_PATH_MEM_SIZE 1
-+#endif
-+
-+/*@========[New Phy-Status Support] ========================*/
-+#if (RTL8197F_SUPPORT || RTL8723D_SUPPORT || RTL8822B_SUPPORT ||\
-+	RTL8821C_SUPPORT || RTL8710B_SUPPORT || RTL8195B_SUPPORT ||\
-+	RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
-+	#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT			1
-+#else
-+	#define ODM_PHY_STATUS_NEW_TYPE_SUPPORT			0
-+#endif
-+
-+#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT ||\
-+	RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
-+	#define PHYSTS_3RD_TYPE_SUPPORT
-+#endif
-+
-+#ifdef PHYSTS_3RD_TYPE_SUPPORT
-+	#define PHYSTS_AUTO_SWITCH_IC (ODM_RTL8822C)
-+#endif
-+
-+#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT ||\
-+	RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
-+	#define BB_RAM_SUPPORT
-+#endif
-+
-+#if (RTL8821C_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\
-+	RTL8812F_SUPPORT || RTL8814B_SUPPORT || RTL8195B_SUPPORT ||\
-+	RTL8198F_SUPPORT)
-+	#define PHYDM_COMPILE_MU
-+#endif
-+
-+#if (RTL8822B_SUPPORT)
-+	#define CONFIG_MU_JAGUAR_2
-+#endif
-+
-+#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT  || RTL8812F_SUPPORT)
-+	#define CONFIG_MU_JAGUAR_3
-+#endif
-+
-+#if (defined(CONFIG_MU_JAGUAR_2) || defined(CONFIG_MU_JAGUAR_3))
-+	#if (RTL8814B_SUPPORT)
-+		#define MU_EX_MACID		76
-+	#elif (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT)
-+		#define MU_EX_MACID		30
-+	#endif
-+#endif
-+/*@============================================================================*/
-+
-+#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\
-+	RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8822C_SUPPORT ||\
-+	RTL8198F_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\
-+	RTL8197G_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT || RTL8723F_SUPPORT)
-+#define PHYDM_COMMON_API_SUPPORT
-+#endif
-+
-+#define PHYDM_COMMON_API_IC (ODM_IC_JGR3_SERIES | ODM_RTL8822B  |\
-+		ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8192F | ODM_RTL8195B |\
-+		ODM_RTL8721D | ODM_RTL8710C)
-+
-+#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT || RTL8821A_SUPPORT ||\
-+	RTL8812A_SUPPORT || RTL8723B_SUPPORT || RTL8703B_SUPPORT ||\
-+	RTL8195A_SUPPORT || RTL8814A_SUPPORT)
-+#define PHYDM_COMMON_API_NOT_SUPPORT
-+#endif
-+
-+#if (RTL8821C_SUPPORT || RTL8197F_SUPPORT || RTL8197G_SUPPORT)
-+	#define CONFIG_RFE_BY_HW_INFO
-+#endif
-+
-+#define	CCK_RATE_NUM		4
-+#define	OFDM_RATE_NUM		8
-+
-+#define	LEGACY_RATE_NUM		12
-+
-+#define	HT_RATE_NUM_4SS		32
-+#define	VHT_RATE_NUM_4SS	40
-+
-+#define	HT_RATE_NUM_3SS		24
-+#define	VHT_RATE_NUM_3SS	30
-+
-+#define	HT_RATE_NUM_2SS		16
-+#define	VHT_RATE_NUM_2SS	20
-+
-+#define	HT_RATE_NUM_1SS		8
-+#define	VHT_RATE_NUM_1SS	10
-+#if (defined(PHYDM_COMPILE_ABOVE_4SS))
-+	#define	HT_RATE_NUM	HT_RATE_NUM_4SS
-+	#define	VHT_RATE_NUM	VHT_RATE_NUM_4SS
-+#elif (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	#define	HT_RATE_NUM	HT_RATE_NUM_3SS
-+	#define	VHT_RATE_NUM	VHT_RATE_NUM_3SS
-+#elif (defined(PHYDM_COMPILE_ABOVE_2SS))
-+	#define	HT_RATE_NUM	HT_RATE_NUM_2SS
-+	#define	VHT_RATE_NUM	VHT_RATE_NUM_2SS
-+#else
-+	#define	HT_RATE_NUM	HT_RATE_NUM_1SS
-+	#define	VHT_RATE_NUM	VHT_RATE_NUM_1SS
-+#endif
-+
-+#define	LOW_BW_RATE_NUM		VHT_RATE_NUM
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+#define	SECOND_CH_AT_LSB	2	/*@primary CH @ MSB,  SD4: HAL_PRIME_CHNL_OFFSET_UPPER*/
-+#define	SECOND_CH_AT_USB	1	/*@primary CH @ LSB,   SD4: HAL_PRIME_CHNL_OFFSET_LOWER*/
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#define	SECOND_CH_AT_LSB	2	/*@primary CH @ MSB,  SD7: HAL_PRIME_CHNL_OFFSET_UPPER*/
-+#define	SECOND_CH_AT_USB	1	/*@primary CH @ LSB,   SD7: HAL_PRIME_CHNL_OFFSET_LOWER*/
-+#else /*if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/
-+#define	SECOND_CH_AT_LSB	1	/*@primary CH @ MSB,  SD8: HT_2NDCH_OFFSET_BELOW*/
-+#define	SECOND_CH_AT_USB	2	/*@primary CH @ LSB,   SD8: HT_2NDCH_OFFSET_ABOVE*/
-+#endif
-+
-+enum phydm_ic_ip {
-+	PHYDM_IC_N		= 0,
-+	PHYDM_IC_AC		= 1,
-+	PHYDM_IC_JGR3		= 2
-+};
-+
-+enum phydm_phy_sts_type {
-+	PHYDM_PHYSTS_TYPE_1	= 1,
-+	PHYDM_PHYSTS_TYPE_2	= 2,
-+	PHYDM_PHYSTS_TYPE_3	= 3
-+};
-+
-+/* ODM_CMNINFO_CUT_VER */
-+enum odm_cut_version {
-+	ODM_CUT_A		= 0,
-+	ODM_CUT_B		= 1,
-+	ODM_CUT_C		= 2,
-+	ODM_CUT_D		= 3,
-+	ODM_CUT_E		= 4,
-+	ODM_CUT_F		= 5,
-+	ODM_CUT_G		= 6,
-+	ODM_CUT_H		= 7,
-+	ODM_CUT_I		= 8,
-+	ODM_CUT_J		= 9,
-+	ODM_CUT_K		= 10,
-+	ODM_CUT_L		= 11,
-+	ODM_CUT_M		= 12,
-+	ODM_CUT_N		= 13,
-+	ODM_CUT_O		= 14,
-+	ODM_CUT_TEST		= 15,
-+};
-+
-+/* ODM_CMNINFO_FAB_VER */
-+enum odm_fab {
-+	ODM_TSMC		= 0,
-+	ODM_UMC			= 1,
-+};
-+
-+/* ODM_CMNINFO_OP_MODE */
-+enum odm_operation_mode {
-+	ODM_NO_LINK		= BIT(0),
-+	ODM_LINK		= BIT(1),
-+	ODM_SCAN		= BIT(2),
-+	ODM_POWERSAVE		= BIT(3),
-+	ODM_AP_MODE		= BIT(4),
-+	ODM_CLIENT_MODE		= BIT(5),
-+	ODM_AD_HOC		= BIT(6),
-+	ODM_WIFI_DIRECT		= BIT(7),
-+	ODM_WIFI_DISPLAY	= BIT(8),
-+};
-+
-+/* ODM_CMNINFO_WM_MODE */
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+enum odm_wireless_mode {
-+	ODM_WM_UNKNOW		= 0x0,
-+	ODM_WM_B		= BIT(0),
-+	ODM_WM_G		= BIT(1),
-+	ODM_WM_A		= BIT(2),
-+	ODM_WM_N24G		= BIT(3),
-+	ODM_WM_N5G		= BIT(4),
-+	ODM_WM_AUTO		= BIT(5),
-+	ODM_WM_AC		= BIT(6),
-+};
-+#else
-+enum odm_wireless_mode {
-+	ODM_WM_UNKNOWN		= 0x00,/*@0x0*/
-+	ODM_WM_A		= BIT(0), /* @0x1*/
-+	ODM_WM_B		= BIT(1), /* @0x2*/
-+	ODM_WM_G		= BIT(2),/* @0x4*/
-+	ODM_WM_AUTO		= BIT(3),/* @0x8*/
-+	ODM_WM_N24G		= BIT(4),/* @0x10*/
-+	ODM_WM_N5G		= BIT(5),/* @0x20*/
-+	ODM_WM_AC_5G		= BIT(6),/* @0x40*/
-+	ODM_WM_AC_24G		= BIT(7),/* @0x80*/
-+	ODM_WM_AC_ONLY		= BIT(8),/* @0x100*/
-+	ODM_WM_MAX		= BIT(11)/* @0x800*/
-+
-+};
-+#endif
-+
-+/* ODM_CMNINFO_BAND */
-+enum odm_band_type {
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	ODM_BAND_2_4G		= BIT(0),
-+	ODM_BAND_5G		= BIT(1),
-+#else
-+	ODM_BAND_2_4G		= 0,
-+	ODM_BAND_5G,
-+	ODM_BAND_ON_BOTH,
-+	ODM_BANDMAX
-+#endif
-+};
-+
-+enum odm_rf_band {
-+	ODM_RF_BAND_2G		= 0,
-+	ODM_RF_BAND_5G_LOW	= 1,
-+	ODM_RF_BAND_5G_MID	= 2,
-+	ODM_RF_BAND_5G_HIGH	= 3,
-+};
-+
-+/* ODM_CMNINFO_SEC_CHNL_OFFSET */
-+enum phydm_sec_chnl_offset {
-+	PHYDM_DONT_CARE		= 0,
-+	PHYDM_BELOW		= 1,
-+	PHYDM_ABOVE		= 2
-+};
-+
-+/* ODM_CMNINFO_SEC_MODE */
-+enum odm_security {
-+	ODM_SEC_OPEN		= 0,
-+	ODM_SEC_WEP40		= 1,
-+	ODM_SEC_TKIP		= 2,
-+	ODM_SEC_RESERVE		= 3,
-+	ODM_SEC_AESCCMP		= 4,
-+	ODM_SEC_WEP104		= 5,
-+	ODM_WEP_WPA_MIXED	= 6, /* WEP + WPA */
-+	ODM_SEC_SMS4		= 7,
-+};
-+
-+/* ODM_CMNINFO_CHNL */
-+
-+/* ODM_CMNINFO_BOARD_TYPE */
-+enum odm_board_type {
-+	ODM_BOARD_DEFAULT	= 0,	  /* The DEFAULT case. */
-+	ODM_BOARD_MINICARD	= BIT(0), /* @0 = non-mini card, 1= mini card. */
-+	ODM_BOARD_SLIM		= BIT(1), /* @0 = non-slim card, 1 = slim card */
-+	ODM_BOARD_BT		= BIT(2), /* @0 = without BT card, 1 = with BT */
-+	ODM_BOARD_EXT_PA	= BIT(3), /* @0 = no 2G ext-PA, 1 = existing 2G ext-PA */
-+	ODM_BOARD_EXT_LNA	= BIT(4), /* @0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
-+	ODM_BOARD_EXT_TRSW	= BIT(5), /* @0 = no ext-TRSW, 1 = existing ext-TRSW */
-+	ODM_BOARD_EXT_PA_5G	= BIT(6), /* @0 = no 5G ext-PA, 1 = existing 5G ext-PA */
-+	ODM_BOARD_EXT_LNA_5G	= BIT(7), /* @0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
-+};
-+
-+enum odm_package_type {
-+	ODM_PACKAGE_DEFAULT	= 0,
-+	ODM_PACKAGE_QFN68	= BIT(0),
-+	ODM_PACKAGE_TFBGA90	= BIT(1),
-+	ODM_PACKAGE_TFBGA79	= BIT(2),
-+};
-+
-+enum odm_type_gpa {
-+	TYPE_GPA0		= 0x0000,
-+	TYPE_GPA1		= 0x0055,
-+	TYPE_GPA2		= 0x00AA,
-+	TYPE_GPA3		= 0x00FF,
-+	TYPE_GPA4		= 0x5500,
-+	TYPE_GPA5		= 0x5555,
-+	TYPE_GPA6		= 0x55AA,
-+	TYPE_GPA7		= 0x55FF,
-+	TYPE_GPA8		= 0xAA00,
-+	TYPE_GPA9		= 0xAA55,
-+	TYPE_GPA10		= 0xAAAA,
-+	TYPE_GPA11		= 0xAAFF,
-+	TYPE_GPA12		= 0xFF00,
-+	TYPE_GPA13		= 0xFF55,
-+	TYPE_GPA14		= 0xFFAA,
-+	TYPE_GPA15		= 0xFFFF,
-+};
-+
-+enum odm_type_apa {
-+	TYPE_APA0		= 0x0000,
-+	TYPE_APA1		= 0x0055,
-+	TYPE_APA2		= 0x00AA,
-+	TYPE_APA3		= 0x00FF,
-+	TYPE_APA4		= 0x5500,
-+	TYPE_APA5		= 0x5555,
-+	TYPE_APA6		= 0x55AA,
-+	TYPE_APA7		= 0x55FF,
-+	TYPE_APA8		= 0xAA00,
-+	TYPE_APA9		= 0xAA55,
-+	TYPE_APA10		= 0xAAAA,
-+	TYPE_APA11		= 0xAAFF,
-+	TYPE_APA12		= 0xFF00,
-+	TYPE_APA13		= 0xFF55,
-+	TYPE_APA14		= 0xFFAA,
-+	TYPE_APA15		= 0xFFFF,
-+};
-+
-+enum odm_type_glna {
-+	TYPE_GLNA0		= 0x0000,
-+	TYPE_GLNA1		= 0x0055,
-+	TYPE_GLNA2		= 0x00AA,
-+	TYPE_GLNA3		= 0x00FF,
-+	TYPE_GLNA4		= 0x5500,
-+	TYPE_GLNA5		= 0x5555,
-+	TYPE_GLNA6		= 0x55AA,
-+	TYPE_GLNA7		= 0x55FF,
-+	TYPE_GLNA8		= 0xAA00,
-+	TYPE_GLNA9		= 0xAA55,
-+	TYPE_GLNA10		= 0xAAAA,
-+	TYPE_GLNA11		= 0xAAFF,
-+	TYPE_GLNA12		= 0xFF00,
-+	TYPE_GLNA13		= 0xFF55,
-+	TYPE_GLNA14		= 0xFFAA,
-+	TYPE_GLNA15		= 0xFFFF,
-+};
-+
-+enum odm_type_alna {
-+	TYPE_ALNA0		= 0x0000,
-+	TYPE_ALNA1		= 0x0055,
-+	TYPE_ALNA2		= 0x00AA,
-+	TYPE_ALNA3		= 0x00FF,
-+	TYPE_ALNA4		= 0x5500,
-+	TYPE_ALNA5		= 0x5555,
-+	TYPE_ALNA6		= 0x55AA,
-+	TYPE_ALNA7		= 0x55FF,
-+	TYPE_ALNA8		= 0xAA00,
-+	TYPE_ALNA9		= 0xAA55,
-+	TYPE_ALNA10		= 0xAAAA,
-+	TYPE_ALNA11		= 0xAAFF,
-+	TYPE_ALNA12		= 0xFF00,
-+	TYPE_ALNA13		= 0xFF55,
-+	TYPE_ALNA14		= 0xFFAA,
-+	TYPE_ALNA15		= 0xFFFF,
-+};
-+
-+#if (RTL8721D_SUPPORT)
-+/* ODM_CMNINFO_POWER_VOLTAGE */
-+enum odm_power_voltage {
-+	ODM_POWER_18V		= 0,
-+	ODM_POWER_33V		= 1,
-+};
-+
-+/* ODM_CMNINFO_ANTDIV_GPIO */
-+enum odm_antdiv_gpio {
-+	ANTDIV_GPIO_PA2PA4	= 0,
-+	ANTDIV_GPIO_PA5PA6	= 1,
-+	ANTDIV_GPIO_PA12PA13	= 2,
-+	ANTDIV_GPIO_PA14PA15	= 3,
-+	ANTDIV_GPIO_PA16PA17	= 4,
-+	ANTDIV_GPIO_PB1PB2	= 5,
-+	ANTDIV_GPIO_PB26PB29	= 6,
-+	ANTDIV_GPIO_PB1PB2PB26 = 7, // add by Jiao Qi for AmebaD SP3T only
-+};
-+
-+/* ODM_CMNINFO_PEAK_DETECT_MODE */
-+enum odm_peak_detect_mode {
-+	ODM_PD_DIS		= 0,
-+	ODM_PD_ENG		= 1,
-+	ODM_PD_ENA		= 2,
-+	ODM_PD_ENALL		= 3,
-+};
-+#endif
-+
-+#define	PAUSE_FAIL		0
-+#define	PAUSE_SUCCESS		1
-+
-+enum odm_parameter_init {
-+	ODM_PRE_SETTING		= 0,
-+	ODM_POST_SETTING	= 1,
-+	ODM_INIT_FW_SETTING	= 2,
-+	ODM_PRE_RF_SET		= 3,
-+	ODM_POST_RF_SET		= 4
-+};
-+
-+enum phydm_pause_type {
-+	PHYDM_PAUSE		= 1,	/*Pause & Set new value*/
-+	PHYDM_PAUSE_NO_SET	= 2,	/*Pause & Stay in current value*/
-+	PHYDM_RESUME		= 3
-+};
-+
-+enum phydm_backup_type {
-+	PHYDM_BACKUP	= 1,
-+	PHYDM_RESTORE	= 2
-+};
-+
-+enum phydm_pause_level {
-+	PHYDM_PAUSE_RELEASE	= -1,
-+	PHYDM_PAUSE_LEVEL_0	= 0,	/* @Low Priority function */
-+	PHYDM_PAUSE_LEVEL_1	= 1,	/* @Middle Priority function */
-+	PHYDM_PAUSE_LEVEL_2	= 2,	/* @High priority function (ex: Check hang function) */
-+	PHYDM_PAUSE_LEVEL_3	= 3,	/* @Debug function (the highest priority) */
-+	PHYDM_PAUSE_MAX_NUM	= 4
-+};
-+
-+enum phydm_dis_hw_fun {
-+	HW_FUN_DIS		= 0,	/*@Disable a cetain HW function & backup the original value*/
-+	HW_FUN_RESUME		= 1	/*Revert */
-+};
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_precomp.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_precomp.h
-new file mode 100644
-index 000000000000..c30584e6ec7b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_precomp.h
-@@ -0,0 +1,651 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __ODM_PRECOMP_H__
-+#define __ODM_PRECOMP_H__
-+
-+#include "phydm_types.h"
-+#include "halrf/halrf_features.h"
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	#include "Precomp.h"		/* @We need to include mp_precomp.h due to batch file setting. */
-+#else
-+	#define		TEST_FALG___		1
-+#endif
-+
-+/* @2 Config Flags and Structs - defined by each ODM type */
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	#include "../8192cd_cfg.h"
-+	#include "../odm_inc.h"
-+
-+	#include "../8192cd.h"
-+	#include "../8192cd_util.h"
-+	#include "../8192cd_hw.h"
-+	#ifdef _BIG_ENDIAN_
-+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_BIG
-+	#else
-+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_LITTLE
-+	#endif
-+
-+	#include "../8192cd_headers.h"
-+	#include "../8192cd_debug.h"
-+
-+	#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
-+		#define INIT_TIMER_EVENT_ENTRY(_entry, _func, _data) \
-+		do { \
-+			_rtw_init_listhead(&(_entry)->list); \
-+			(_entry)->data = (_data); \
-+			(_entry)->function = (_func); \
-+		} while (0)
-+	#endif
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	#ifdef DM_ODM_CE_MAC80211
-+		#include "../wifi.h"
-+		#include "rtl_phydm.h"
-+	#elif defined(DM_ODM_CE_MAC80211_V2)
-+		#include "../main.h"
-+		#include "../hw.h"
-+		#include "../fw.h"
-+	#endif
-+	#define __PACK
-+	#define __WLAN_ATTRIB_PACK__
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	#include "mp_precomp.h"
-+	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_LITTLE
-+	#define __PACK
-+	#define __WLAN_ATTRIB_PACK__
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+	#include <drv_types.h>
-+	#include <wifi.h>
-+	#define	ODM_ENDIAN_TYPE				ODM_ENDIAN_LITTLE
-+	#define __PACK
-+#endif
-+
-+/* @2 OutSrc Header Files */
-+
-+#include "phydm.h"
-+#include "phydm_hwconfig.h"
-+#include "phydm_phystatus.h"
-+#include "phydm_debug.h"
-+#include "phydm_regdefine11ac.h"
-+#include "phydm_regdefine11n.h"
-+#include "phydm_interface.h"
-+#include "phydm_reg.h"
-+#include "halrf/halrf_debug.h"
-+
-+#ifndef RTL8188E_SUPPORT
-+	#define	RTL8188E_SUPPORT	0
-+#endif
-+#ifndef RTL8812A_SUPPORT
-+	#define	RTL8812A_SUPPORT	0
-+#endif
-+#ifndef RTL8821A_SUPPORT
-+	#define	RTL8821A_SUPPORT	0
-+#endif
-+#ifndef RTL8192E_SUPPORT
-+	#define	RTL8192E_SUPPORT	0
-+#endif
-+#ifndef RTL8723B_SUPPORT
-+	#define	RTL8723B_SUPPORT	0
-+#endif
-+#ifndef RTL8814A_SUPPORT
-+	#define	RTL8814A_SUPPORT	0
-+#endif
-+#ifndef RTL8881A_SUPPORT
-+	#define	RTL8881A_SUPPORT	0
-+#endif
-+#ifndef RTL8822B_SUPPORT
-+	#define	RTL8822B_SUPPORT	0
-+#endif
-+#ifndef RTL8703B_SUPPORT
-+	#define	RTL8703B_SUPPORT	0
-+#endif
-+#ifndef RTL8195A_SUPPORT
-+	#define	RTL8195A_SUPPORT	0
-+#endif
-+#ifndef RTL8188F_SUPPORT
-+	#define	RTL8188F_SUPPORT	0
-+#endif
-+#ifndef RTL8723D_SUPPORT
-+	#define	RTL8723D_SUPPORT	0
-+#endif
-+#ifndef RTL8197F_SUPPORT
-+	#define	RTL8197F_SUPPORT	0
-+#endif
-+#ifndef RTL8821C_SUPPORT
-+	#define	RTL8821C_SUPPORT	0
-+#endif
-+#ifndef RTL8814B_SUPPORT
-+	#define	RTL8814B_SUPPORT	0
-+#endif
-+#ifndef RTL8198F_SUPPORT
-+	#define	RTL8198F_SUPPORT	0
-+#endif
-+#ifndef RTL8710B_SUPPORT
-+	#define	RTL8710B_SUPPORT	0
-+#endif
-+#ifndef RTL8192F_SUPPORT
-+	#define	RTL8192F_SUPPORT	0
-+#endif
-+#ifndef RTL8822C_SUPPORT
-+	#define	RTL8822C_SUPPORT	0
-+#endif
-+#ifndef RTL8195B_SUPPORT
-+	#define	RTL8195B_SUPPORT	0
-+#endif
-+#ifndef RTL8812F_SUPPORT
-+	#define	RTL8812F_SUPPORT	0
-+#endif
-+#ifndef RTL8197G_SUPPORT
-+	#define	RTL8197G_SUPPORT	0
-+#endif
-+#ifndef RTL8721D_SUPPORT
-+	#define	RTL8721D_SUPPORT	0
-+#endif
-+#ifndef RTL8710C_SUPPORT
-+	#define	RTL8710C_SUPPORT	0
-+#endif
-+#ifndef RTL8723F_SUPPORT
-+	#define	RTL8723F_SUPPORT	0
-+#endif
-+#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && \
-+	(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
-+
-+void phy_set_tx_power_limit(
-+	struct dm_struct *dm,
-+	u8 *regulation,
-+	u8 *band,
-+	u8 *bandwidth,
-+	u8 *rate_section,
-+	u8 *rf_path,
-+	u8 *channel,
-+	u8 *power_limit);
-+
-+void phy_set_tx_power_limit_ex(struct dm_struct *dm, u8 regulation, u8 band,
-+			       u8 bandwidth, u8 rate_section, u8 rf_path,
-+			       u8 channel, s8 power_limit);
-+
-+enum hal_status
-+rtw_phydm_fw_iqk(
-+	struct dm_struct *dm,
-+	u8 clear,
-+	u8 segment);
-+
-+enum hal_status
-+rtw_phydm_fw_dpk(
-+	struct dm_struct *dm);
-+
-+enum hal_status
-+rtw_phydm_cfg_phy_para(
-+	struct dm_struct *dm,
-+	enum phydm_halmac_param config_type,
-+	u32 offset,
-+	u32 data,
-+	u32 mask,
-+	enum rf_path e_rf_path,
-+	u32 delay_time);
-+
-+#endif
-+
-+#if RTL8188E_SUPPORT == 1
-+	#define RTL8188E_T_SUPPORT 1
-+	#ifdef CONFIG_SFW_SUPPORTED
-+		#define RTL8188E_S_SUPPORT 1
-+	#else
-+		#define RTL8188E_S_SUPPORT 0
-+	#endif
-+
-+	#include "rtl8188e/hal8188erateadaptive.h" /* @for  RA,Power training */
-+	#include "rtl8188e/halhwimg8188e_mac.h"
-+	#include "rtl8188e/halhwimg8188e_rf.h"
-+	#include "rtl8188e/halhwimg8188e_bb.h"
-+	#include "rtl8188e/phydm_regconfig8188e.h"
-+	#include "rtl8188e/phydm_rtl8188e.h"
-+	#include "rtl8188e/hal8188ereg.h"
-+	#include "rtl8188e/version_rtl8188e.h"
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "rtl8188e_hal.h"
-+		#include "halrf/rtl8188e/halrf_8188e_ce.h"
-+	#endif
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+		#include "halrf/rtl8188e/halrf_8188e_win.h"
-+	#endif
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+		#include "halrf/rtl8188e/halrf_8188e_ap.h"
-+	#endif
-+#endif /* @88E END */
-+
-+#if (RTL8192E_SUPPORT == 1)
-+
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+		#include "halrf/rtl8192e/halrf_8192e_win.h" /*@FOR_8192E_IQK*/
-+	#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+		#include "halrf/rtl8192e/halrf_8192e_ap.h" /*@FOR_8192E_IQK*/
-+	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "halrf/rtl8192e/halrf_8192e_ce.h" /*@FOR_8192E_IQK*/
-+	#endif
-+
-+	#include "rtl8192e/phydm_rtl8192e.h" /* @FOR_8192E_IQK */
-+	#include "rtl8192e/version_rtl8192e.h"
-+	#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+		#include "rtl8192e/halhwimg8192e_bb.h"
-+		#include "rtl8192e/halhwimg8192e_mac.h"
-+		#include "rtl8192e/halhwimg8192e_rf.h"
-+		#include "rtl8192e/phydm_regconfig8192e.h"
-+		#include "rtl8192e/hal8192ereg.h"
-+	#endif
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "rtl8192e_hal.h"
-+	#endif
-+#endif /* @92E END */
-+
-+#if (RTL8812A_SUPPORT == 1)
-+
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+		#include "halrf/rtl8812a/halrf_8812a_win.h"
-+	#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+		#include "halrf/rtl8812a/halrf_8812a_ap.h"
-+	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "halrf/rtl8812a/halrf_8812a_ce.h"
-+	#endif
-+
-+	#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+		#include "rtl8812a/halhwimg8812a_bb.h"
-+		#include "rtl8812a/halhwimg8812a_mac.h"
-+		#include "rtl8812a/halhwimg8812a_rf.h"
-+		#include "rtl8812a/phydm_regconfig8812a.h"
-+	#endif
-+	#include "rtl8812a/phydm_rtl8812a.h"
-+
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "rtl8812a_hal.h"
-+	#endif
-+	#include "rtl8812a/version_rtl8812a.h"
-+
-+#endif /* @8812 END */
-+
-+#if (RTL8814A_SUPPORT == 1)
-+
-+	#include "rtl8814a/halhwimg8814a_mac.h"
-+	#include "rtl8814a/halhwimg8814a_bb.h"
-+	#include "rtl8814a/version_rtl8814a.h"
-+	#include "rtl8814a/phydm_rtl8814a.h"
-+	#include "halrf/rtl8814a/halhwimg8814a_rf.h"
-+	#include "halrf/rtl8814a/version_rtl8814a_rf.h"
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+		#include "halrf/rtl8814a/halrf_8814a_win.h"
-+	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "halrf/rtl8814a/halrf_8814a_ce.h"
-+	#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+		#include "halrf/rtl8814a/halrf_8814a_ap.h"
-+	#endif
-+	#include "rtl8814a/phydm_regconfig8814a.h"
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "rtl8814a_hal.h"
-+		#include "halrf/rtl8814a/halrf_iqk_8814a.h"
-+	#endif
-+#endif /* @8814 END */
-+
-+#if (RTL8881A_SUPPORT == 1)/* @FOR_8881_IQK */
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+		#include "halrf/rtl8821a/halrf_iqk_8821a_win.h"
-+	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"
-+	#else
-+		#include "halrf/rtl8821a/halrf_iqk_8821a_ap.h"
-+	#endif
-+#endif
-+
-+#if (RTL8723B_SUPPORT == 1)
-+	#include "rtl8723b/halhwimg8723b_mac.h"
-+	#include "rtl8723b/halhwimg8723b_rf.h"
-+	#include "rtl8723b/halhwimg8723b_bb.h"
-+	#include "rtl8723b/phydm_regconfig8723b.h"
-+	#include "rtl8723b/phydm_rtl8723b.h"
-+	#include "rtl8723b/hal8723breg.h"
-+	#include "rtl8723b/version_rtl8723b.h"
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+		#include "halrf/rtl8723b/halrf_8723b_win.h"
-+	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "halrf/rtl8723b/halrf_8723b_ce.h"
-+		#include "rtl8723b/halhwimg8723b_mp.h"
-+		#include "rtl8723b_hal.h"
-+	#else
-+		#include "halrf/rtl8723b/halrf_8723b_ap.h"
-+	#endif
-+#endif
-+
-+#if (RTL8821A_SUPPORT == 1)
-+	#include "rtl8821a/halhwimg8821a_mac.h"
-+	#include "rtl8821a/halhwimg8821a_rf.h"
-+	#include "rtl8821a/halhwimg8821a_bb.h"
-+	#include "rtl8821a/phydm_regconfig8821a.h"
-+	#include "rtl8821a/phydm_rtl8821a.h"
-+	#include "rtl8821a/version_rtl8821a.h"
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+		#include "halrf/rtl8821a/halrf_8821a_win.h"
-+	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "halrf/rtl8821a/halrf_8821a_ce.h"
-+		#include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"/*@for IQK*/
-+		#include "halrf/rtl8812a/halrf_8812a_ce.h"/*@for IQK,LCK,Power-tracking*/
-+		#include "rtl8812a_hal.h"
-+	#else
-+	#endif
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+#include "../halmac/halmac_reg2.h"
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
-+#include "../halmac/halmac_reg2.h"
-+#endif
-+
-+
-+#if (RTL8822B_SUPPORT == 1)
-+	#include "rtl8822b/halhwimg8822b_mac.h"
-+	#include "rtl8822b/halhwimg8822b_bb.h"
-+	#include "rtl8822b/phydm_regconfig8822b.h"
-+	#include "halrf/rtl8822b/halrf_8822b.h"
-+	#include "halrf/rtl8822b/halhwimg8822b_rf.h"
-+	#include "halrf/rtl8822b/version_rtl8822b_rf.h"
-+	#include "rtl8822b/phydm_rtl8822b.h"
-+	#include "rtl8822b/phydm_hal_api8822b.h"
-+	#include "rtl8822b/version_rtl8822b.h"
-+
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#ifdef DM_ODM_CE_MAC80211
-+			#include "../halmac/halmac_reg_8822b.h"
-+		#elif defined(DM_ODM_CE_MAC80211_V2)
-+			#include "../halmac/halmac_reg_8822b.h"
-+		#else
-+			#include <hal_data.h>		/* @struct HAL_DATA_TYPE */
-+			#include <rtl8822b_hal.h>	/* @RX_SMOOTH_FACTOR, reg definition and etc.*/
-+		#endif
-+	#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	#endif
-+
-+#endif
-+
-+#if (RTL8703B_SUPPORT == 1)
-+	#include "rtl8703b/phydm_rtl8703b.h"
-+	#include "rtl8703b/phydm_regconfig8703b.h"
-+	#include "rtl8703b/halhwimg8703b_mac.h"
-+	#include "rtl8703b/halhwimg8703b_rf.h"
-+	#include "rtl8703b/halhwimg8703b_bb.h"
-+	#include "halrf/rtl8703b/halrf_8703b.h"
-+	#include "rtl8703b/version_rtl8703b.h"
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "rtl8703b_hal.h"
-+	#endif
-+#endif
-+
-+#if (RTL8188F_SUPPORT == 1)
-+	#include "rtl8188f/halhwimg8188f_mac.h"
-+	#include "rtl8188f/halhwimg8188f_rf.h"
-+	#include "rtl8188f/halhwimg8188f_bb.h"
-+	#include "rtl8188f/hal8188freg.h"
-+	#include "rtl8188f/phydm_rtl8188f.h"
-+	#include "rtl8188f/phydm_regconfig8188f.h"
-+	#include "halrf/rtl8188f/halrf_8188f.h" /*@for IQK,LCK,Power-tracking*/
-+	#include "rtl8188f/version_rtl8188f.h"
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "rtl8188f_hal.h"
-+	#endif
-+#endif
-+
-+#if (RTL8723D_SUPPORT == 1)
-+	#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+
-+		#include "rtl8723d/halhwimg8723d_bb.h"
-+		#include "rtl8723d/halhwimg8723d_mac.h"
-+		#include "rtl8723d/halhwimg8723d_rf.h"
-+		#include "rtl8723d/phydm_regconfig8723d.h"
-+		#include "rtl8723d/hal8723dreg.h"
-+		#include "rtl8723d/phydm_rtl8723d.h"
-+		#include "halrf/rtl8723d/halrf_8723d.h"
-+		#include "rtl8723d/version_rtl8723d.h"
-+	#endif
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#ifdef DM_ODM_CE_MAC80211
-+		#else
-+		#include "rtl8723d_hal.h"
-+		#endif
-+	#endif
-+#endif /* @8723D End */
-+
-+#if (RTL8710B_SUPPORT == 1)
-+	#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+
-+		#include "rtl8710b/halhwimg8710b_bb.h"
-+		#include "rtl8710b/halhwimg8710b_mac.h"
-+		#include "rtl8710b/phydm_regconfig8710b.h"
-+		#include "rtl8710b/hal8710breg.h"
-+		#include "rtl8710b/phydm_rtl8710b.h"
-+		#include "halrf/rtl8710b/halrf_8710b.h"
-+		#include "halrf/rtl8710b/halhwimg8710b_rf.h"
-+		#include "halrf/rtl8710b/version_rtl8710b_rf.h"
-+		#include "rtl8710b/version_rtl8710b.h"
-+	#endif
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "rtl8710b_hal.h"
-+	#endif
-+#endif /* @8710B End */
-+
-+#if (RTL8197F_SUPPORT == 1)
-+	#include "rtl8197f/halhwimg8197f_mac.h"
-+	#include "rtl8197f/halhwimg8197f_bb.h"
-+	#include "rtl8197f/phydm_hal_api8197f.h"
-+	#include "rtl8197f/version_rtl8197f.h"
-+	#include "rtl8197f/phydm_rtl8197f.h"
-+	#include "rtl8197f/phydm_regconfig8197f.h"
-+	#include "halrf/rtl8197f/halrf_8197f.h"
-+	#include "halrf/rtl8197f/halrf_iqk_8197f.h"
-+	#include "halrf/rtl8197f/halrf_dpk_8197f.h"
-+	#include "halrf/rtl8197f/halhwimg8197f_rf.h"
-+	#include "halrf/rtl8197f/version_rtl8197f_rf.h"
-+#endif
-+
-+#if (RTL8821C_SUPPORT == 1)
-+	#include "rtl8821c/phydm_hal_api8821c.h"
-+	#include "rtl8821c/halhwimg8821c_mac.h"
-+	#include "rtl8821c/halhwimg8821c_bb.h"
-+	#include "rtl8821c/phydm_regconfig8821c.h"
-+	#include "rtl8821c/phydm_rtl8821c.h"
-+	#include "halrf/rtl8821c/halrf_8821c.h"
-+	#include "halrf/rtl8821c/halhwimg8821c_rf.h"
-+	#include "halrf/rtl8821c/version_rtl8821c_rf.h"
-+	#include "rtl8821c/version_rtl8821c.h"
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#ifdef DM_ODM_CE_MAC80211
-+		#include "../halmac/halmac_reg_8821c.h"
-+		#else
-+		#include "rtl8821c_hal.h"
-+		#endif
-+	#endif
-+#endif
-+
-+#if (RTL8192F_SUPPORT == 1)
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "rtl8192f_hal.h"/*need to before rf.h*/
-+	#endif
-+	#include "rtl8192f/halhwimg8192f_mac.h"
-+	#include "rtl8192f/halhwimg8192f_bb.h"
-+	#include "rtl8192f/phydm_hal_api8192f.h"
-+	#include "rtl8192f/version_rtl8192f.h"
-+	#include "rtl8192f/phydm_rtl8192f.h"
-+	#include "rtl8192f/phydm_regconfig8192f.h"
-+	#include "halrf/rtl8192f/halrf_8192f.h"
-+	#include "halrf/rtl8192f/halhwimg8192f_rf.h"
-+	#include "halrf/rtl8192f/version_rtl8192f_rf.h"
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+		#include "halrf/rtl8192f/halrf_dpk_8192f.h"
-+	#endif
-+#endif
-+
-+#if (RTL8721D_SUPPORT == 1)
-+	#include "halrf/rtl8721d/halrf_btiqk_8721d.h"
-+	#include "halrf/rtl8721d/halrf_rfk_init_8721d.h"
-+	#include "halrf/rtl8721d/halrf_dpk_8721d.h"
-+	#include "halrf/rtl8721d/halrf_8721d.h"
-+	#include "halrf/rtl8721d/halhwimg8721d_rf.h"
-+	#include "halrf/rtl8721d/version_rtl8721d_rf.h"
-+	#include "rtl8721d/phydm_hal_api8721d.h"
-+	#include "rtl8721d/phydm_regconfig8721d.h"
-+	#include "rtl8721d/halhwimg8721d_mac.h"
-+	#include "rtl8721d/halhwimg8721d_bb.h"
-+	#include "rtl8721d/version_rtl8721d.h"
-+	#include "rtl8721d/phydm_rtl8721d.h"
-+	#include "rtl8721d/hal8721dreg.h"
-+	#include <hal_data.h>
-+	#if 0
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	#endif
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "rtl8721d_hal.h"
-+	#endif
-+	#endif
-+#endif
-+
-+#if (RTL8710C_SUPPORT == 1)
-+	#include "halrf/rtl8710c/halrf_8710c.h"
-+	#include "halrf/rtl8710c/halhwimg8710c_rf.h"
-+	//#include "halrf/rtl8710c/version_rtl8710c_rf.h"
-+	#include "rtl8710c/phydm_hal_api8710c.h"
-+	#include "rtl8710c/phydm_regconfig8710c.h"
-+	#include "rtl8710c/halhwimg8710c_mac.h"
-+	#include "rtl8710c/halhwimg8710c_bb.h"
-+	#include "rtl8710c/version_rtl8710c.h"
-+	#include "rtl8710c/phydm_rtl8710c.h"
-+	//#include "rtl8710c/hal87100creg.h"
-+	#include <hal_data.h> /*@HAL_DATA_TYPE*/
-+	#if 0
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+		#include "halrf/rtl8710c/halrf_dpk_8710c.h"
-+	#endif
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include "rtl8710c_hal.h"
-+	#endif
-+	#endif
-+#endif
-+
-+#if (RTL8195B_SUPPORT == 1)
-+	#include "halrf/rtl8195b/halrf_8195b.h"
-+	#include "halrf/rtl8195b/halhwimg8195b_rf.h"
-+	#include "halrf/rtl8195b/version_rtl8195b_rf.h"
-+	#include "rtl8195b/phydm_hal_api8195b.h"
-+	#include "rtl8195b/phydm_regconfig8195b.h"
-+	#include "rtl8195b/halhwimg8195b_mac.h"
-+	#include "rtl8195b/halhwimg8195b_bb.h"
-+	#include "rtl8195b/version_rtl8195b.h"
-+	#include <hal_data.h> /*@HAL_DATA_TYPE*/
-+#endif
-+
-+#if (RTL8198F_SUPPORT == 1)
-+	#include "rtl8198f/phydm_regconfig8198f.h"
-+	#include "rtl8198f/phydm_hal_api8198f.h"
-+	#include "rtl8198f/halhwimg8198f_mac.h"
-+	#include "rtl8198f/halhwimg8198f_bb.h"
-+	#include "rtl8198f/version_rtl8198f.h"
-+	#include "halrf/rtl8198f/halrf_8198f.h"
-+	#include "halrf/rtl8198f/halrf_iqk_8198f.h"
-+	#include "halrf/rtl8198f/halhwimg8198f_rf.h"
-+	#include "halrf/rtl8198f/version_rtl8198f_rf.h"
-+#endif
-+
-+#if (RTL8822C_SUPPORT)
-+	#include "rtl8822c/halhwimg8822c_bb.h"
-+	#include "rtl8822c/phydm_regconfig8822c.h"
-+	#include "rtl8822c/phydm_hal_api8822c.h"
-+	#include "rtl8822c/version_rtl8822c.h"
-+	#include "rtl8822c/phydm_rtl8822c.h"
-+	#include "halrf/rtl8822c/halrf_8822c.h"
-+	#include "halrf/rtl8822c/halhwimg8822c_rf.h"
-+	#include "halrf/rtl8822c/version_rtl8822c_rf.h"
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	/* @struct HAL_DATA_TYPE */
-+	#include <hal_data.h>
-+	/* @RX_SMOOTH_FACTOR, reg definition and etc.*/
-+	#include <rtl8822c_hal.h>
-+	#endif
-+#endif
-+#if (RTL8814B_SUPPORT == 1)
-+	#include "rtl8814b/halhwimg8814b_bb.h"
-+	#include "rtl8814b/phydm_regconfig8814b.h"
-+	#include "halrf/rtl8814b/halrf_8814b.h"
-+	#include "halrf/rtl8814b/halhwimg8814b_rf.h"
-+	#include "halrf/rtl8814b/version_rtl8814b_rf.h"
-+	#include "rtl8814b/phydm_hal_api8814b.h"
-+	#include "rtl8814b/version_rtl8814b.h"
-+	#include "rtl8814b/phydm_extraagc8814b.h"
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+		#include <hal_data.h>		/* @struct HAL_DATA_TYPE */
-+		#include <rtl8814b_hal.h>	/* @RX_SMOOTH_FACTOR, reg definition and etc.*/
-+	#endif
-+#endif
-+#if (RTL8812F_SUPPORT)
-+	#include "rtl8812f/halhwimg8812f_bb.h"
-+	#include "rtl8812f/phydm_regconfig8812f.h"
-+	#include "halrf/rtl8812f/halrf_8812f.h"
-+	#include "halrf/rtl8812f/halhwimg8812f_rf.h"
-+	#include "halrf/rtl8812f/version_rtl8812f_rf.h"
-+	#include "rtl8812f/phydm_hal_api8812f.h"
-+	#include "rtl8812f/version_rtl8812f.h"
-+	#include "rtl8812f/phydm_rtl8812f.h"
-+#endif
-+#if (RTL8197G_SUPPORT)
-+	#include "rtl8197g/halhwimg8197g_bb.h"
-+	#include "rtl8197g/halhwimg8197g_mac.h"
-+	#include "rtl8197g/phydm_regconfig8197g.h"
-+	#include "halrf/rtl8197g/halrf_8197g.h"
-+	#include "halrf/rtl8197g/halhwimg8197g_rf.h"
-+	#include "halrf/rtl8197g/version_rtl8197g_rf.h"
-+	#include "rtl8197g/phydm_hal_api8197g.h"
-+	#include "rtl8197g/version_rtl8197g.h"
-+	#include "rtl8197g/phydm_rtl8197g.h"
-+#endif
-+#if (RTL8723F_SUPPORT)
-+	#include "rtl8723f/halhwimg8723f_bb.h"
-+	#include "rtl8723f/halhwimg8723f_mac.h"
-+	#include "rtl8723f/phydm_regconfig8723f.h"
-+	#include "halrf/rtl8723f/halrf_8723f.h"
-+	#include "halrf/rtl8723f/halhwimg8723f_rf.h"
-+	#include "halrf/rtl8723f/version_rtl8723f_rf.h"
-+	#include "halrf/rtl8723f/halrf_iqk_8723f.h"
-+	#include "halrf/rtl8723f/halrf_dpk_8723f.h"
-+	#include "halrf/rtl8723f/halrf_tssi_8723f.h"
-+	#include "halrf/rtl8723f/halrf_rfk_init_8723f.h"
-+	#include "rtl8723f/phydm_hal_api8723f.h"
-+	#include "rtl8723f/version_rtl8723f.h"
-+	#include "rtl8723f/phydm_rtl8723f.h"
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	/* @struct HAL_DATA_TYPE */
-+	#include <hal_data.h>
-+	/* @RX_SMOOTH_FACTOR, reg definition and etc.*/
-+	#include <rtl8723f_hal.h>
-+	#endif
-+#endif
-+#endif /* @__ODM_PRECOMP_H__ */
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_primary_cca.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_primary_cca.c
-new file mode 100644
-index 000000000000..dec6c5365f08
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_primary_cca.c
-@@ -0,0 +1,173 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*************************************************************
-+ * include files
-+ ************************************************************/
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+#ifdef PHYDM_PRIMARY_CCA
-+
-+void phydm_write_dynamic_cca(
-+	void *dm_void,
-+	u8 curr_mf_state
-+
-+	)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
-+
-+	if (pri_cca->mf_state == curr_mf_state)
-+		return;
-+
-+	if (dm->support_ic_type & ODM_IC_11N_SERIES) {
-+		if (curr_mf_state == MF_USC_LSC) {
-+			odm_set_bb_reg(dm, R_0xc6c, 0x180, MF_USC_LSC);
-+			/*@40M OFDM MF CCA threshold*/
-+			odm_set_bb_reg(dm, R_0xc84, 0xf0000000,
-+				       pri_cca->cca_th_40m_bkp);
-+		} else {
-+			odm_set_bb_reg(dm, R_0xc6c, 0x180, curr_mf_state);
-+			/*@40M OFDM MF CCA threshold*/
-+			odm_set_bb_reg(dm, R_0xc84, 0xf0000000, 0);
-+		}
-+	}
-+
-+	pri_cca->mf_state = curr_mf_state;
-+	PHYDM_DBG(dm, DBG_PRI_CCA, "Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\n",
-+		  ((curr_mf_state == MF_USC_LSC) ? "D" :
-+		  ((curr_mf_state == MF_LSC) ? "L" : "U")), curr_mf_state);
-+}
-+
-+void phydm_primary_cca_reset(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
-+
-+	PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Reset\n");
-+	pri_cca->mf_state = 0xff;
-+	pri_cca->pre_bw = (enum channel_width)0xff;
-+	phydm_write_dynamic_cca(dm, MF_USC_LSC);
-+}
-+
-+void phydm_primary_cca_11n(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
-+	enum channel_width curr_bw = (enum channel_width)*dm->band_width;
-+
-+	if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
-+		return;
-+
-+	if (!dm->is_linked) {
-+		PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][No Link!!!]\n");
-+
-+		if (pri_cca->pri_cca_is_become_linked) {
-+			phydm_primary_cca_reset(dm);
-+			pri_cca->pri_cca_is_become_linked = dm->is_linked;
-+		}
-+		return;
-+	} else {
-+		if (!pri_cca->pri_cca_is_become_linked) {
-+			PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][Linked !!!]\n");
-+			pri_cca->pri_cca_is_become_linked = dm->is_linked;
-+		}
-+	}
-+
-+	if (curr_bw != pri_cca->pre_bw) {
-+		PHYDM_DBG(dm, DBG_PRI_CCA, "[Primary CCA] start ==>\n");
-+		pri_cca->pre_bw = curr_bw;
-+
-+		if (curr_bw == CHANNEL_WIDTH_40) {
-+			if (*dm->sec_ch_offset == SECOND_CH_AT_LSB) {
-+			/* Primary CH @ upper sideband*/
-+				PHYDM_DBG(dm, DBG_PRI_CCA,
-+					  "BW40M, Primary CH at USB\n");
-+				phydm_write_dynamic_cca(dm, MF_USC);
-+			} else {
-+			/*Primary CH @ lower sideband*/
-+				PHYDM_DBG(dm, DBG_PRI_CCA,
-+					  "BW40M, Primary CH at LSB\n");
-+				phydm_write_dynamic_cca(dm, MF_LSC);
-+			}
-+		} else {
-+			PHYDM_DBG(dm, DBG_PRI_CCA, "Not BW40M, USB + LSB\n");
-+			phydm_primary_cca_reset(dm);
-+		}
-+	}
-+}
-+
-+boolean
-+odm_dynamic_primary_cca_dup_rts(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
-+
-+	return pri_cca->dup_rts_flag;
-+}
-+
-+void phydm_primary_cca_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
-+
-+	if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
-+		return;
-+
-+	if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Init ==>\n");
-+#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1)
-+	pri_cca->dup_rts_flag = 0;
-+	pri_cca->intf_flag = 0;
-+	pri_cca->intf_type = 0;
-+	pri_cca->monitor_flag = 0;
-+	pri_cca->pri_cca_flag = 0;
-+	pri_cca->ch_offset = 0;
-+#endif
-+	pri_cca->mf_state = 0xff;
-+	pri_cca->pre_bw = (enum channel_width)0xff;
-+	pri_cca->cca_th_40m_bkp = (u8)odm_get_bb_reg(dm, R_0xc84, 0xf0000000);
-+}
-+
-+void phydm_primary_cca(void *dm_void)
-+{
-+#ifdef PHYDM_PRIMARY_CCA
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
-+		return;
-+
-+	if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
-+		return;
-+
-+	phydm_primary_cca_11n(dm);
-+
-+#endif
-+}
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_primary_cca.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_primary_cca.h
-new file mode 100644
-index 000000000000..1978586f293d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_primary_cca.h
-@@ -0,0 +1,76 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_PRIMARYCCA_H__
-+#define __PHYDM_PRIMARYCCA_H__
-+
-+#ifdef PHYDM_PRIMARY_CCA
-+#define PRIMARYCCA_VERSION "2.0"
-+
-+/*@============================================================*/
-+/*@Definition */
-+/*@============================================================*/
-+
-+#define	OFDMCCA_TH		500
-+#define	bw_ind_bias		500
-+#define	PRI_CCA_MONITOR_TIME	30
-+
-+/*@============================================================*/
-+/*structure and define*/
-+/*@============================================================*/
-+enum primary_cca_ch_position { /*N-series REG0xc6c[8:7]*/
-+	MF_USC_LSC	= 0,
-+	MF_LSC		= 1,
-+	MF_USC		= 2
-+};
-+
-+struct phydm_pricca_struct {
-+	#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1)
-+	u8	pri_cca_flag;
-+	u8	intf_flag;
-+	u8	intf_type;
-+	u8	monitor_flag;
-+	u8	ch_offset;
-+	#endif
-+	u8	dup_rts_flag;
-+	u8	cca_th_40m_bkp; /*@c84[31:28]*/
-+	enum channel_width	pre_bw;
-+	u8	pri_cca_is_become_linked;
-+	u8	mf_state;
-+};
-+
-+/*@============================================================*/
-+/*@function prototype*/
-+/*@============================================================*/
-+void phydm_write_dynamic_cca(void *dm_void, u8 curr_mf_state);
-+
-+boolean odm_dynamic_primary_cca_dup_rts(void *dm_void);
-+
-+void phydm_primary_cca_init(void *dm_void);
-+
-+void phydm_primary_cca(void *dm_void);
-+#endif /*@#ifdef PHYDM_PRIMARY_CCA*/
-+#endif /*@#ifndef	__PHYDM_PRIMARYCCA_H__*/
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_psd.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_psd.c
-new file mode 100644
-index 000000000000..8a19160b9079
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_psd.c
-@@ -0,0 +1,564 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/******************************************************************************
-+ * include files
-+ *****************************************************************************/
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef CONFIG_PSD_TOOL
-+u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct psd_info *dm_psd_table = &dm->dm_psd_table;
-+	u32 psd_report = 0;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		#if(RTL8723F_SUPPORT)
-+		if (dm->support_ic_type & (ODM_RTL8723F)) {
-+			odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff80000, psd_tone_idx & 0x7ff);
-+			/*PSD trigger start*/
-+			odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(16), 1);
-+			ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
-+			/*PSD trigger stop*/
-+			odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(16), 0);
-+		}
-+		#endif
-+		#if 0
-+		odm_set_bb_reg(dm, R_0x1e8c, 0x3ff, psd_tone_idx & 0x3ff);
-+		odm_set_bb_reg(dm, R_0x1e88, BIT(27) | BIT(26),
-+			       psd_tone_idx >> 10);
-+		/*PSD trigger start*/
-+		odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 1);
-+		ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
-+		/*PSD trigger stop*/
-+		odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 0);
-+		#endif
-+	} else if (dm->support_ic_type & (ODM_RTL8721D |
-+				ODM_RTL8710C)) {
-+		odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0xfff, psd_tone_idx);
-+		odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 1);
-+		/*PSD trigger start*/
-+		ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
-+		odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 0);
-+		/*PSD trigger stop*/
-+	} else {
-+		odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx);
-+		/*PSD trigger start*/
-+		odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 1);
-+		ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
-+		/*PSD trigger stop*/
-+		odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 0);
-+	}
-+
-+	/*Get PSD Report*/
-+	if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
-+				ODM_RTL8710C)) {
-+		psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
-+					    0xffffff);
-+		psd_report = psd_report >> 5;
-+	} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		#if(RTL8723F_SUPPORT)
-+		if (dm->support_ic_type & (ODM_RTL8723F)) {
-+			psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
-+					   	 0x1ffffff);
-+		}
-+		#endif
-+		#if 0
-+		psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
-+					    0xffffff);
-+		#endif
-+	} else {
-+		psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
-+					    0xffff);
-+	}
-+	psd_report = odm_convert_to_db((u64)psd_report) + igi;
-+
-+	return psd_report;
-+}
-+
-+u8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127};
-+u8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67};
-+
-+u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct psd_info *dm_psd_table = &dm->dm_psd_table;
-+	u32 i = 0, mod_tone_idx = 0;
-+	u32 t = 0;
-+	u16 fft_max_half_bw = 0;
-+	u16 psd_fc_channel = dm_psd_table->psd_fc_channel;
-+	u8 ag_rf_mode_reg = 0;
-+	u8 is_5G = 0;
-+	u32 psd_result_tmp = 0;
-+	u8 psd_result = 0;
-+	u8 psd_result_cali_tone[7] = {0};
-+	u8 psd_result_cali_val[7] = {0};
-+	u8 noise_idx = 0;
-+	u8 set_result = 0;
-+	u32 igi_tmp = 0x6e;
-+
-+	if (dm->support_ic_type == ODM_RTL8821) {
-+		odm_move_memory(dm, psd_result_cali_tone,
-+				psd_result_cali_tone_8821, 7);
-+		odm_move_memory(dm, psd_result_cali_val,
-+				psd_result_cali_val_8821, 7);
-+	}
-+
-+	dm_psd_table->psd_in_progress = 1;
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "PSD Start =>\n");
-+
-+	/* @[Stop DIG]*/
-+	/* @IGI target at 0dBm & make it can't CCA*/
-+	if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_3, 1,
-+			     &igi_tmp) == PAUSE_FAIL) {
-+		return PHYDM_SET_FAIL;
-+	}
-+
-+	ODM_delay_us(10);
-+
-+	if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
-+		phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3,
-+				 1, &igi_tmp);
-+		return PHYDM_SET_FAIL;
-+	}
-+
-+	/* @[Set IGI]*/
-+	phydm_write_dig_reg(dm, (u8)igi);
-+
-+	/* @[Backup RF Reg]*/
-+	dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18,
-+						   RFREG_MASK);
-+	dm_psd_table->rf_0x18_bkp_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0x18,
-+						     RFREG_MASK);
-+
-+	if (psd_fc_channel > 14) {
-+		is_5G = 1;
-+		if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
-+					   ODM_RTL8197G)) {
-+		#if 0
-+			if (psd_fc_channel < 80)
-+				ag_rf_mode_reg = 0x1;
-+			else if (psd_fc_channel >= 80 && psd_fc_channel <= 140)
-+				ag_rf_mode_reg = 0x3;
-+			else if (psd_fc_channel > 140)
-+				ag_rf_mode_reg = 0x5;
-+		#endif
-+		} else if (dm->support_ic_type & ODM_RTL8723F) {
-+				if (psd_fc_channel < 80)
-+					ag_rf_mode_reg = 0x1;
-+				else if (psd_fc_channel >= 80 && psd_fc_channel <= 144)
-+					ag_rf_mode_reg = 0x5;
-+				else if (psd_fc_channel > 144)
-+					ag_rf_mode_reg = 0x9;
-+		} else if (dm->support_ic_type == ODM_RTL8721D) {
-+			if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
-+				ag_rf_mode_reg = 0x1;
-+			else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
-+				ag_rf_mode_reg = 0x5;
-+			else if (psd_fc_channel > 140)
-+				ag_rf_mode_reg = 0x9;
-+		} else {
-+			if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
-+				ag_rf_mode_reg = 0x1;
-+			else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
-+				ag_rf_mode_reg = 0x3;
-+			else if (psd_fc_channel > 140)
-+				ag_rf_mode_reg = 0x5;
-+		}
-+	}
-+
-+	/* Set RF fc*/
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff, psd_fc_channel);
-+	odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xff, psd_fc_channel);
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x300, is_5G);
-+	odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x300, is_5G);
-+	if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
-+				   ODM_RTL8197G)) {
-+		#if 0
-+		/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x3000,
-+			       dm_psd_table->psd_bw_rf_reg);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x3000,
-+			       dm_psd_table->psd_bw_rf_reg);
-+		/* Set RF ag fc mode*/
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x70000,
-+			       ag_rf_mode_reg);
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x70000,
-+			       ag_rf_mode_reg);
-+		#endif
-+	} else if (dm->support_ic_type & ODM_RTL8723F) {
-+			/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x1c00,
-+				       dm_psd_table->psd_bw_rf_reg);
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x1c00,
-+				       dm_psd_table->psd_bw_rf_reg);
-+			/* Set RF ag fc mode*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x30000,	1);
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x30000,	1);
-+			if(ag_rf_mode_reg == 1) {
-+				odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 0);
-+				odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 0);
-+			}
-+			else if(ag_rf_mode_reg == 5){
-+				odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 1);
-+				odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 1);
-+			}
-+			else {
-+				odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 2);	
-+				odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 2);	
-+			}
-+	} else {
-+		/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
-+		if (dm->support_ic_type == ODM_RTL8721D) {
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x1c00,
-+				       dm_psd_table->psd_bw_rf_reg);
-+#if (RTL8710C_SUPPORT == 1)
-+		} else if (dm->support_ic_type == ODM_RTL8710C) {
-+			odm_set_rf_reg(dm, RF_PATH_A,
-+							RF_0x18, 0x1c00,
-+						dm_psd_table->psd_bw_rf_reg);
-+#endif
-+		} else {
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xc00,
-+				       dm_psd_table->psd_bw_rf_reg);
-+		}
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xc00,
-+				       dm_psd_table->psd_bw_rf_reg);
-+			/* Set RF ag fc mode*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xf0000,
-+				       ag_rf_mode_reg);
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xf0000,
-+				       ag_rf_mode_reg);
-+	}
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES){
-+		if (dm->support_ic_type & ODM_RTL8723F) {
-+		PHYDM_DBG(dm, ODM_COMP_API, "0x1d70=((0x%x))\n",
-+			  odm_get_bb_reg(dm, R_0x1d70, MASKDWORD));
-+		PHYDM_DBG(dm, ODM_COMP_API, "RF0x19=((0x%x))\n",
-+			 odm_get_rf_reg(dm, RF_PATH_A, RF_0x19, RFREG_MASK));
-+		}
-+	} else
-+		PHYDM_DBG(dm, ODM_COMP_API, "0xc50=((0x%x))\n",
-+			  odm_get_bb_reg(dm, R_0xc50, MASKDWORD));
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "RF0x18=((0x%x))\n",
-+		  odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK));
-+
-+	/* @[Stop 3-wires]*/
-+	phydm_stop_3_wire(dm, PHYDM_SET);
-+
-+	ODM_delay_us(10);
-+
-+	if (stop_point > (dm_psd_table->fft_smp_point - 1))
-+		stop_point = (dm_psd_table->fft_smp_point - 1);
-+
-+	if (start_point > (dm_psd_table->fft_smp_point - 1))
-+		start_point = (dm_psd_table->fft_smp_point - 1);
-+
-+	if (start_point > stop_point)
-+		stop_point = start_point;
-+
-+	for (i = start_point; i <= stop_point; i++) {
-+		fft_max_half_bw = (dm_psd_table->fft_smp_point) >> 1;
-+
-+		if (i < fft_max_half_bw)
-+			mod_tone_idx = i + fft_max_half_bw;
-+		else
-+			mod_tone_idx = i - fft_max_half_bw;
-+
-+		psd_result_tmp = 0;
-+		for (t = 0; t < dm_psd_table->sw_avg_time; t++)
-+			psd_result_tmp += phydm_get_psd_data(dm, mod_tone_idx,
-+							     igi);
-+		psd_result =
-+			(u8)((psd_result_tmp / dm_psd_table->sw_avg_time)) -
-+			dm_psd_table->psd_pwr_common_offset;
-+
-+		if (dm_psd_table->fft_smp_point == 128 &&
-+		    dm_psd_table->noise_k_en) {
-+			if (i > psd_result_cali_tone[noise_idx])
-+				noise_idx++;
-+
-+			if (noise_idx > 6)
-+				noise_idx = 6;
-+
-+			if (psd_result >= psd_result_cali_val[noise_idx])
-+				psd_result = psd_result -
-+					     psd_result_cali_val[noise_idx];
-+			else
-+				psd_result = 0;
-+
-+			dm_psd_table->psd_result[i] = psd_result;
-+		}
-+
-+		PHYDM_DBG(dm, ODM_COMP_API, "[%d] N_cali = %d, PSD = %d\n",
-+			  mod_tone_idx, psd_result_cali_val[noise_idx],
-+			  psd_result);
-+	}
-+
-+	/*@[Start 3-wires]*/
-+	phydm_stop_3_wire(dm, PHYDM_REVERT);
-+
-+	ODM_delay_us(10);
-+
-+	/*@[Revert Reg]*/
-+	set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
-+
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK,
-+		       dm_psd_table->rf_0x18_bkp);
-+	odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREG_MASK,
-+		       dm_psd_table->rf_0x18_bkp_b);
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "PSD finished\n\n");
-+
-+	phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3, 1,
-+			 &igi_tmp);
-+	dm_psd_table->psd_in_progress = 0;
-+
-+	return PHYDM_SET_SUCCESS;
-+}
-+
-+void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
-+			    u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,
-+			    u8 psd_input, u8 channel, u8 noise_k_en)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct psd_info *dm_psd_table = &dm->dm_psd_table;
-+	u8 fft_smp_point_idx = 0;
-+
-+	dm_psd_table->fft_smp_point = fft_smp_point;
-+
-+	if (sw_avg_time == 0)
-+		sw_avg_time = 1;
-+
-+	dm_psd_table->sw_avg_time = sw_avg_time;
-+	dm_psd_table->psd_fc_channel = channel;
-+	dm_psd_table->noise_k_en = noise_k_en;
-+	if (dm->support_ic_type & ODM_RTL8723F) {
-+		if (fft_smp_point == 128)
-+			fft_smp_point_idx = 3;
-+		else if (fft_smp_point == 256)
-+			fft_smp_point_idx = 2;
-+		else if (fft_smp_point == 512)
-+			fft_smp_point_idx = 1;
-+		else if (fft_smp_point == 1024)
-+			fft_smp_point_idx = 0;
-+	} 
-+	else {
-+		if (fft_smp_point == 128)
-+			fft_smp_point_idx = 0;
-+		else if (fft_smp_point == 256)
-+			fft_smp_point_idx = 1;
-+		else if (fft_smp_point == 512)
-+			fft_smp_point_idx = 2;
-+		else if (fft_smp_point == 1024)
-+			fft_smp_point_idx = 3;
-+	}
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		#if (RTL8723F_SUPPORT)
-+		odm_set_bb_reg(dm, R_0x1e8c, BIT(12) | BIT(11), hw_avg_time);
-+		odm_set_bb_reg(dm, R_0x1e8c, BIT(14) | BIT(13),
-+				       fft_smp_point_idx);
-+		odm_set_bb_reg(dm, R_0x1e8c, BIT(18) | BIT(17), ant_sel);
-+		odm_set_bb_reg(dm, R_0x1e88, BIT(25) | BIT(24), psd_input);
-+		#else
-+		#if 0
-+		odm_set_bb_reg(dm, R_0x1e8c, BIT(11) | BIT(10), i_q_setting);
-+		odm_set_bb_reg(dm, R_0x1e8c, BIT(13) | BIT(12), hw_avg_time);
-+
-+		if (fft_smp_point == 4096) {
-+			odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x2);
-+		} else if (fft_smp_point == 2048) {
-+			odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x1);
-+		} else {
-+			odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x0);
-+			odm_set_bb_reg(dm, R_0x1e8c, BIT(15) | BIT(14),
-+				       fft_smp_point_idx);
-+		}
-+		odm_set_bb_reg(dm, R_0x1e8c, BIT(17) | BIT(16), ant_sel);
-+		odm_set_bb_reg(dm, R_0x1e8c, BIT(23) | BIT(22), psd_input);
-+		#endif
-+		#endif
-+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		odm_set_bb_reg(dm, R_0x910, BIT(11) | BIT(10), i_q_setting);
-+		odm_set_bb_reg(dm, R_0x910, BIT(13) | BIT(12), hw_avg_time);
-+		odm_set_bb_reg(dm, R_0x910, BIT(15) | BIT(14),
-+			       fft_smp_point_idx);
-+		odm_set_bb_reg(dm, R_0x910, BIT(17) | BIT(16), ant_sel);
-+		odm_set_bb_reg(dm, R_0x910, BIT(23), psd_input);
-+	} else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
-+		odm_set_bb_reg(dm, R_0x808, BIT(19) | BIT(18), i_q_setting);
-+		odm_set_bb_reg(dm, R_0x808, BIT(21) | BIT(20), hw_avg_time);
-+		odm_set_bb_reg(dm, R_0x808, BIT(23) | BIT(22),
-+			       fft_smp_point_idx);
-+		odm_set_bb_reg(dm, R_0x804, BIT(5) | BIT(4), ant_sel);
-+		odm_set_bb_reg(dm, R_0x80c, BIT(23), psd_input);
-+
-+#if 0
-+	} else {	/*ODM_IC_11N_SERIES*/
-+#endif
-+	}
-+	/*@bw = (*dm->band_width); //ODM_BW20M */
-+	/*@channel = *(dm->channel);*/
-+}
-+
-+void phydm_psd_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct psd_info *dm_psd_table = &dm->dm_psd_table;
-+
-+	PHYDM_DBG(dm, ODM_COMP_API, "PSD para init\n");
-+
-+	dm_psd_table->psd_in_progress = false;
-+
-+	if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
-+		#if (RTL8723F_SUPPORT)
-+		if (dm->support_ic_type & ODM_RTL8723F) {
-+			dm_psd_table->psd_reg = R_0x1e8c;
-+			dm_psd_table->psd_report_reg = R_0x2d90;
-+
-+			/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
-+			dm_psd_table->psd_bw_rf_reg = 2;
-+		}
-+		#else
-+		#if 0
-+		dm_psd_table->psd_reg = R_0x1e8c;
-+		dm_psd_table->psd_report_reg = R_0x2d90;
-+
-+		/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
-+		dm_psd_table->psd_bw_rf_reg = 1;
-+		#endif
-+
-+		return;
-+		#endif
-+	} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
-+		dm_psd_table->psd_reg = R_0x910;
-+		dm_psd_table->psd_report_reg = R_0xf44;
-+
-+		/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
-+		if (ODM_IC_11AC_2_SERIES)
-+			dm_psd_table->psd_bw_rf_reg = 1;
-+		else
-+			dm_psd_table->psd_bw_rf_reg = 2;
-+	} else {
-+		dm_psd_table->psd_reg = R_0x808;
-+		dm_psd_table->psd_report_reg = R_0x8b4;
-+		/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
-+		dm_psd_table->psd_bw_rf_reg = 2;
-+	}
-+
-+	dm_psd_table->psd_pwr_common_offset = 0;
-+
-+	phydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0);
-+#if 0
-+	/*phydm_psd(dm, 0x3c, 0, 127);*/ /* target at -50dBm */
-+#endif
-+}
-+
-+void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,
-+		     char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u8 i = 0;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		#if (RTL8723F_SUPPORT)
-+				if (dm->support_ic_type & ODM_RTL8723F)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)}\n{path_sel 0~3} {0:ADC, 1:rxdata_fir_in, 2:rx_nbi_nf_stage2} {CH} {noise_k}\n\n");
-+		#endif
-+		#if 0
-+		if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4) 2048 4096}\n{path_sel 0~3} {0:ADC, 1:rxdata_fir_in, 2:rx_nbi_nf_stage2} {CH} {noise_k}\n\n");
-+		else
-+		#endif
-+		#endif
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n");
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{1} {IGI(hex)} {start_point} {stop_point}\n");
-+		goto out;
-+	}
-+
-+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
-+
-+	if (var1[0] == 0) {
-+		for (i = 1; i < 10; i++) {
-+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
-+				     &var1[i]);
-+		}
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n",
-+			 var1[1], var1[2], var1[3], var1[4], var1[5],
-+			 var1[6], (u8)var1[7], (u8)var1[8]);
-+		phydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2],
-+				       (u8)var1[3], (u16)var1[4],
-+				       (u8)var1[5], (u8)var1[6],
-+				       (u8)var1[7], (u8)var1[8]);
-+
-+	} else if (var1[0] == 1) {
-+		PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
-+		PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
-+		PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n",
-+			 var1[1], var1[2], var1[3]);
-+		dm->debug_components |= ODM_COMP_API;
-+		if (phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]) ==
-+		    PHYDM_SET_FAIL)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "PSD_SET_FAIL\n");
-+		dm->debug_components &= ~(ODM_COMP_API);
-+	}
-+
-+out:
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+u8 phydm_get_psd_result_table(void *dm_void, int index)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct psd_info *dm_psd_table = &dm->dm_psd_table;
-+	u8 result = 0;
-+
-+	if (index < 128)
-+		result = dm_psd_table->psd_result[index];
-+
-+	return result;
-+}
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_psd.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_psd.h
-new file mode 100644
-index 000000000000..dec384ab2b99
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_psd.h
-@@ -0,0 +1,68 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDMPSD_H__
-+#define __PHYDMPSD_H__
-+
-+/*@#define PSD_VERSION	"1.0"*/ /*@2016.09.22  Dino*/
-+/*@2016.10.07  Dino, Add Option for PSD Tone index Selection */
-+/*@2019.04.26  Early return & "IF0" for JGR3 ICs */
-+#define PSD_VERSION "1.2"
-+
-+#ifdef CONFIG_PSD_TOOL
-+
-+
-+struct psd_info {
-+	u8	psd_in_progress;
-+	u32	psd_reg;
-+	u32	psd_report_reg;
-+	u8	psd_pwr_common_offset;
-+	u16	sw_avg_time;
-+	u16	fft_smp_point;
-+	u32	rf_0x18_bkp;
-+	u32	rf_0x18_bkp_b;
-+	u16	psd_fc_channel;
-+	u32	psd_bw_rf_reg;
-+	u8	psd_result[128];
-+	u8	noise_k_en;
-+};
-+
-+u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi);
-+
-+void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,
-+		     char *output, u32 *_out_len);
-+
-+u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point);
-+
-+void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
-+			    u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,
-+			    u8 psd_input, u8 channel, u8 noise_k_en);
-+
-+void phydm_psd_init(void *dm_void);
-+
-+u8 phydm_get_psd_result_table(void *dm_void, int index);
-+
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_rainfo.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_rainfo.c
-new file mode 100644
-index 000000000000..69738c98accb
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_rainfo.c
-@@ -0,0 +1,2431 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ************************************************************/
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+boolean phydm_is_vht_rate(void *dm_void, u8 rate)
-+{
-+	return ((rate & 0x7f) >= ODM_RATEVHTSS1MCS0) ? true : false;
-+}
-+
-+boolean phydm_is_ht_rate(void *dm_void, u8 rate)
-+{
-+	return (((rate & 0x7f) >= ODM_RATEMCS0) &&
-+		((rate & 0x7f) <= ODM_RATEMCS31)) ? true : false;
-+}
-+
-+boolean phydm_is_ofdm_rate(void *dm_void, u8 rate)
-+{
-+	return (((rate & 0x7f) >= ODM_RATE6M) &&
-+		((rate & 0x7f) <= ODM_RATE54M)) ? true : false;
-+}
-+
-+boolean phydm_is_cck_rate(void *dm_void, u8 rate)
-+{
-+	return ((rate & 0x7f) <= ODM_RATE11M) ? true : false;
-+}
-+
-+u8 phydm_legacy_rate_2_spec_rate(void *dm_void, u8 rate)
-+{
-+	u8 rate_idx = 0x0;
-+	u8 legacy_spec_rate_t[8] = {PHYDM_SPEC_RATE_6M, PHYDM_SPEC_RATE_9M,
-+				    PHYDM_SPEC_RATE_12M, PHYDM_SPEC_RATE_18M,
-+				    PHYDM_SPEC_RATE_24M, PHYDM_SPEC_RATE_36M,
-+				    PHYDM_SPEC_RATE_48M, PHYDM_SPEC_RATE_54M};
-+
-+	if ((rate >= ODM_RATE6M) && (rate <= ODM_RATE54M))
-+		rate_idx = rate - ODM_RATE6M;
-+	return legacy_spec_rate_t[rate_idx];
-+}
-+
-+u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate)
-+{
-+	u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
-+	u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
-+	u8 rate_digit = 0;
-+
-+	if (rate_idx >= ODM_RATEVHTSS1MCS0)
-+		rate_digit = (rate_idx - ODM_RATEVHTSS1MCS0) % 10;
-+	else if (rate_idx >= ODM_RATEMCS0)
-+		rate_digit = (rate_idx - ODM_RATEMCS0);
-+	else if (rate_idx <= ODM_RATE54M)
-+		rate_digit = legacy_table[rate_idx];
-+
-+	return rate_digit;
-+}
-+
-+u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type)
-+{
-+	u8 num_ss = 1;
-+
-+	switch (type) {
-+	case PDM_CCK:
-+	case PDM_OFDM:
-+	case PDM_1SS:
-+		num_ss = 1;
-+		break;
-+	case PDM_2SS:
-+		num_ss = 2;
-+		break;
-+	case PDM_3SS:
-+		num_ss = 3;
-+		break;
-+	case PDM_4SS:
-+		num_ss = 4;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return num_ss;
-+}
-+
-+u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate)
-+{
-+	u8 num_ss = 1;
-+
-+	if (data_rate <= ODM_RATE54M)
-+		num_ss = 1;
-+	else if (data_rate <= ODM_RATEMCS31)
-+		num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1;
-+	else if (data_rate <= ODM_RATEVHTSS1MCS9)
-+		num_ss = 1;
-+	else if (data_rate <= ODM_RATEVHTSS2MCS9)
-+		num_ss = 2;
-+	else if (data_rate <= ODM_RATEVHTSS3MCS9)
-+		num_ss = 3;
-+	else if (data_rate <= ODM_RATEVHTSS4MCS9)
-+		num_ss = 4;
-+
-+	return num_ss;
-+}
-+
-+void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,
-+		     char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 dm_value[10] = {0};
-+	u8 i = 0, input_idx = 0;
-+	u8 h2c_parameter[H2C_MAX_LENGTH] = {0};
-+	u8 phydm_h2c_id = 0;
-+
-+	for (i = 0; i < 8; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
-+		input_idx++;
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	phydm_h2c_id = (u8)dm_value[0];
-+
-+	PDM_SNPF(out_len, used, output + used, out_len - used,
-+		 "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id);
-+
-+	for (i = 0; i < H2C_MAX_LENGTH; i++) {
-+		h2c_parameter[i] = (u8)dm_value[i + 1];
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "H2C: Byte[%d] = ((0x%x))\n", i, h2c_parameter[i]);
-+	}
-+
-+	odm_fill_h2c_cmd(dm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter);
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_fw_fix_rate(void *dm_void, u8 en, u8 macid, u8 bw, u8 rate)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 reg_u32_tmp;
-+
-+	if (dm->support_ic_type & PHYDM_IC_8051_SERIES) {
-+		reg_u32_tmp = (bw << 24) | (rate << 16) | (macid << 8) | en;
-+		odm_set_mac_reg(dm, R_0x4a0, MASKDWORD, reg_u32_tmp);
-+
-+	} else {
-+		if (en == 1)
-+			reg_u32_tmp = BYTE_2_DWORD(0x60, macid, bw, rate);
-+		else
-+			reg_u32_tmp = 0x40000000;
-+		if (dm->support_ic_type & ODM_RTL8814B)
-+			odm_set_mac_reg(dm, R_0x448, MASKDWORD, reg_u32_tmp);
-+		else
-+			odm_set_mac_reg(dm, R_0x450, MASKDWORD, reg_u32_tmp);
-+	}
-+	if (en == 1) {
-+		PHYDM_DBG(dm, ODM_COMP_API,
-+			  "FW fix TX rate[id =%d], %dM, Rate(%d)=", macid,
-+			  (20 << bw), rate);
-+		phydm_print_rate(dm, rate, ODM_COMP_API);
-+	} else {
-+		PHYDM_DBG(dm, ODM_COMP_API, "Auto Rate\n");
-+	}
-+}
-+
-+void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
-+		    u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	char help[] = "-h";
-+	u32 var[5] = {0};
-+	u8 macid = 0, bw = 0, rate = 0;
-+	u8 tx_cls_en = 0, tx_cls_th = 0, tmp = 0;
-+	u8 i = 0;
-+
-+	for (i = 0; i < 5; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
-+	}
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{1} {0:-,1:+} {ofst}: set offset\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{1} {100}: show offset\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{2} {en} {macid} {bw} {rate}: fw fix rate\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{3} {en}: Dynamic RRSR\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{4} {0:pkt RA, 1:TBTT RA, 100:query RA mode}\n");
-+#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{5} {0:dis, 1:en}{th; 255:auto, xx:dB}: Tx CLS\n");
-+#endif
-+	} else if (var[0] == 1) { /*@Adjust PCR offset*/
-+
-+		if (var[1] == 100) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[Get] RA_ofst=((%s%d))\n",
-+				 ((ra_tab->ra_ofst_direc) ? "+" : "-"),
-+				 ra_tab->ra_th_ofst);
-+
-+		} else if (var[1] == 0) {
-+			ra_tab->ra_ofst_direc = 0;
-+			ra_tab->ra_th_ofst = (u8)var[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[Set] RA_ofst=((-%d))\n", ra_tab->ra_th_ofst);
-+		} else if (var[1] == 1) {
-+			ra_tab->ra_ofst_direc = 1;
-+			ra_tab->ra_th_ofst = (u8)var[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[Set] RA_ofst=((+%d))\n", ra_tab->ra_th_ofst);
-+		}
-+
-+	} else if (var[0] == 2) { /*@FW fix rate*/
-+		macid = (u8)var[2];
-+		bw = (u8)var[3];
-+		rate = (u8)var[4];
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[FW fix TX Rate] {en, macid,bw,rate}={%d, %d, %d, 0x%x}",
-+			 var[1], macid, bw, rate);
-+
-+		phydm_fw_fix_rate(dm, (u8)var[1], macid, bw, rate);
-+	} else if (var[0] == 3) { /*@Dynamic RRSR*/
-+		ra_tab->dynamic_rrsr_en = (boolean)var[1];
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[Dynamic RRSR] enable=%d", ra_tab->dynamic_rrsr_en);
-+	} else if (var[0] == 4) { /*@RA trigger mode*/
-+		if (var[1] == 0 || var[1] == 1)
-+			ra_tab->ra_trigger_mode = (u8)var[1];
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+		"[RA trigger] mode=%d\n", ra_tab->ra_trigger_mode);
-+#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
-+	} else if (var[0] == 5) { /*@Tx Collision Detection*/
-+		tx_cls_en = (u8)var[1];
-+		ra_tab->ra_tx_cls_th = (u8)var[2];
-+		tmp = (u8)var[2];
-+		tx_cls_th = (tmp < 50) ? 0 : (tmp > 81) ? 31 : tmp - 50;
-+		if (tx_cls_en) {
-+			odm_set_bb_reg(dm, R_0x8f8, BIT(16), 1);
-+			if (ra_tab->ra_tx_cls_th != 255) {
-+				phydm_tx_collsion_th_set(dm, tx_cls_th,
-+							 tx_cls_th);
-+			}
-+
-+		} else {
-+			odm_set_bb_reg(dm, R_0x8f8, BIT(16), 0);
-+		}
-+
-+		if (tx_cls_en & ra_tab->ra_tx_cls_th != 255) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[Tx Collision Detec] {en, th}={%d, %d}\n",
-+				 tx_cls_en, tx_cls_th + 50);
-+		} else if (tx_cls_en & ra_tab->ra_tx_cls_th == 255) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[Tx Collision Detec] {en, th}={%d, auto}\n",
-+				 tx_cls_en);
-+		} else {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[Tx Collision Detec] {en, th}={%d, xx}\n",
-+				 tx_cls_en);
-+		}
-+#endif
-+	} else {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[Set] Error\n");
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_ra_mask_report_h2c_trigger(void *dm_void,
-+				      struct ra_mask_rpt_trig *trig_rpt)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+
-+	phydm_fw_trace_en_h2c(dm, true, 1, 2, trig_rpt->macid);
-+
-+	trig_rpt->ra_mask_rpt_stamp = ra_tab->ra_mask_rpt_stamp;
-+}
-+void phydm_ra_mask_report_c2h_result(void *dm_void, struct ra_mask_rpt *rpt)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+	u8 i = 0;
-+
-+	rpt->ra_mask_rpt_stamp = ra_tab->ra_mask_rpt_stamp;
-+
-+	odm_move_memory(dm, &rpt->ra_mask_buf[0], &ra_tab->ra_mask_buf[0], 8);
-+}
-+
-+void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+	u8 mode = cmd_buf[0]; /*Retry Penalty, NH, NL*/
-+	u8 i;
-+
-+	PHYDM_DBG(dm, DBG_FW_TRACE, "[%s] [mode: %d]----------------------->\n",
-+		  __func__, mode);
-+
-+	if (mode == RADBG_DEBUG_MONITOR1) {
-+		if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "RSSI =",
-+				  cmd_buf[1]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n", "rate =",
-+				  cmd_buf[2] & 0x7f);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "SGI =",
-+				  (cmd_buf[2] & 0x80) >> 7);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "BW =",
-+				  cmd_buf[3]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "BW_max =",
-+				  cmd_buf[4]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
-+				  "multi_rate0 =", cmd_buf[5]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
-+				  "multi_rate1 =", cmd_buf[6]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "DISRA =",
-+				  cmd_buf[7]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "VHT_EN =",
-+				  cmd_buf[8]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n",
-+				  "SGI_support =", cmd_buf[9]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "try_ness =",
-+				  cmd_buf[10]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n", "pre_rate =",
-+				  cmd_buf[11]);
-+		} else {
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "RSSI =",
-+				  cmd_buf[1]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %x\n", "BW =",
-+				  cmd_buf[2]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "DISRA =",
-+				  cmd_buf[3]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "VHT_EN =",
-+				  cmd_buf[4]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n",
-+				  "Hightest rate =", cmd_buf[5]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
-+				  "Lowest rate =", cmd_buf[6]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
-+				  "SGI_support =", cmd_buf[7]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "Rate_ID =",
-+				  cmd_buf[8]);
-+		}
-+	} else if (mode == RADBG_DEBUG_MONITOR2) {
-+		if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "rate_id =",
-+				  cmd_buf[1]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
-+				  "highest_rate =", cmd_buf[2]);
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n",
-+				  "lowest_rate =", cmd_buf[3]);
-+
-+			for (i = 4; i <= 11; i++)
-+				PHYDM_DBG(dm, DBG_FW_TRACE, "RAMASK =  0x%x\n",
-+					  cmd_buf[i]);
-+
-+			odm_move_memory(dm, &ra_tab->ra_mask_buf[0], &cmd_buf[4], 8);
-+			ra_tab->ra_mask_rpt_stamp++;
-+		} else {
-+			PHYDM_DBG(dm, DBG_FW_TRACE,
-+				  "%5s  %x%x  %x%x  %x%x  %x%x\n", "RA Mask:",
-+				  cmd_buf[8], cmd_buf[7], cmd_buf[6],
-+				  cmd_buf[5], cmd_buf[4], cmd_buf[3],
-+				  cmd_buf[2], cmd_buf[1]);
-+		}
-+	} else if (mode == RADBG_DEBUG_MONITOR3) {
-+		for (i = 0; i < (cmd_len - 1); i++)
-+			PHYDM_DBG(dm, DBG_FW_TRACE, "content[%d] = %d\n", i,
-+				  cmd_buf[1 + i]);
-+	} else if (mode == RADBG_DEBUG_MONITOR4)
-+		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  {%d.%d}\n", "RA version =",
-+			  cmd_buf[1], cmd_buf[2]);
-+	else if (mode == RADBG_DEBUG_MONITOR5) {
-+		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n", "Current rate =",
-+			  cmd_buf[1]);
-+		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "Retry ratio =",
-+			  cmd_buf[2]);
-+		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  %d\n", "rate down ratio =",
-+			  cmd_buf[3]);
-+		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x\n", "highest rate =",
-+			  cmd_buf[4]);
-+		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  {0x%x 0x%x}\n", "Muti-try =",
-+			  cmd_buf[5], cmd_buf[6]);
-+		PHYDM_DBG(dm, DBG_FW_TRACE, "%5s  0x%x%x%x%x%x\n", "RA mask =",
-+			  cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8],
-+			  cmd_buf[7]);
-+	}
-+	PHYDM_DBG(dm, DBG_FW_TRACE, "-------------------------------\n");
-+}
-+
-+void phydm_ra_dynamic_retry_count(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ability & ODM_BB_DYNAMIC_ARFR))
-+		return;
-+
-+	/*PHYDM_DBG(dm, DBG_RA, "dm->pre_b_noisy = %d\n", dm->pre_b_noisy );*/
-+
-+	if (dm->pre_b_noisy != dm->noisy_decision) {
-+		if (dm->noisy_decision) {
-+			PHYDM_DBG(dm, DBG_DYN_ARFR, "Noisy Env. RA fallback\n");
-+			odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x0);
-+			odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x04030201);
-+		} else {
-+			PHYDM_DBG(dm, DBG_DYN_ARFR, "Clean Env. RA fallback\n");
-+			odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x01000000);
-+			odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x06050402);
-+		}
-+		dm->pre_b_noisy = dm->noisy_decision;
-+	}
-+}
-+
-+void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
-+	boolean vht_en = phydm_is_vht_rate(dm, rate_idx);
-+	u8 b_sgi = (rate & 0x80) >> 7;
-+	u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);
-+	u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);
-+
-+	PHYDM_DBG_F(dm, dbg_component, "( %s%s%s%s%s%d%s%s)\n",
-+		    (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "",
-+		    (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "",
-+		    (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "",
-+		    (vht_en && (rate_ss == 4)) ? "VHT 4ss " : "",
-+		    (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
-+		    rate_digit,
-+		    (b_sgi) ? "-S" : " ",
-+		    (rate_idx >= ODM_RATEMCS0) ? "" : "M");
-+}
-+
-+void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
-+	boolean vht_en = phydm_is_vht_rate(dm, rate_idx);
-+	u8 b_sgi = (rate & 0x80) >> 7;
-+	u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);
-+	u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);
-+
-+	PHYDM_SNPRINTF(buf, buf_size, "( %s%s%s%s%s%d%s%s)",
-+		       (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "",
-+		       (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "",
-+		       (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "",
-+		       (vht_en && (rate_ss == 4)) ? "VHT 4ss " : "",
-+		       (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
-+		       rate_digit,
-+		       (b_sgi) ? "-S" : " ",
-+		       (rate_idx >= ODM_RATEMCS0) ? "" : "M");
-+}
-+
-+void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+	struct cmn_sta_info *sta = NULL;
-+	u8 macid = cmd_buf[1];
-+	u8 rate = cmd_buf[0];
-+	u8 ra_ratio = 0xff;
-+	u8 curr_bw = 0xff;
-+	u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
-+	u8 rate_order;
-+	u8 gid_index = 0;
-+	u8 txcls_rate = 0;
-+	char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
-+
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	sta = dm->phydm_sta_info[dm->phydm_macid_table[macid]];
-+	#else
-+	sta = dm->phydm_sta_info[macid];
-+	#endif
-+
-+	if (cmd_len == 7) {
-+		ra_ratio = cmd_buf[5];
-+		curr_bw = cmd_buf[6];
-+		PHYDM_DBG(dm, DBG_RA, "[%d] PER=%d\n", macid, ra_ratio);
-+	} else if (cmd_len == 8) {
-+		ra_ratio = cmd_buf[5];
-+		curr_bw = cmd_buf[6];
-+		txcls_rate = cmd_buf[7];
-+		PHYDM_DBG(dm, DBG_RA, "[%d] PER=%d TxCLS=%d\n", macid, ra_ratio,
-+			  txcls_rate);
-+	}
-+
-+	if (cmd_buf[3] != 0) {
-+		if (cmd_buf[3] == 0xff)
-+			PHYDM_DBG(dm, DBG_RA, "FW Fix Rate\n");
-+		else if (cmd_buf[3] == 1)
-+			PHYDM_DBG(dm, DBG_RA, "Try Success\n");
-+		else if (cmd_buf[3] == 2)
-+			PHYDM_DBG(dm, DBG_RA, "Try Fail & Again\n");
-+		else if (cmd_buf[3] == 3)
-+			PHYDM_DBG(dm, DBG_RA, "Rate Back\n");
-+		else if (cmd_buf[3] == 4)
-+			PHYDM_DBG(dm, DBG_RA, "Start rate by RSSI\n");
-+		else if (cmd_buf[3] == 5)
-+			PHYDM_DBG(dm, DBG_RA, "Try rate\n");
-+	}
-+	phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);
-+	PHYDM_DBG(dm, DBG_RA, "Tx Rate=%s (%d)\n", dbg_buf, rate);
-+
-+#ifdef MU_EX_MACID
-+	if (macid >= 128 && macid < (128 + MU_EX_MACID)) {
-+		gid_index = macid - 128;
-+		ra_tab->mu1_rate[gid_index] = rate;
-+	}
-+	if (macid >= ODM_ASSOCIATE_ENTRY_NUM)
-+		return;
-+#endif
-+	if (is_sta_active(sta)) {
-+		sta->ra_info.curr_tx_rate = rate;
-+		sta->ra_info.curr_tx_bw = (enum channel_width)curr_bw;
-+		sta->ra_info.curr_retry_ratio = ra_ratio;
-+	}
-+
-+	/*trigger power training*/
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+
-+	rate_order = phydm_rate_order_compute(dm, rate_idx);
-+
-+	if (dm->is_one_entry_only ||
-+	    (rate_order > ra_tab->highest_client_tx_order &&
-+	    ra_tab->power_tracking_flag == 1)) {
-+		halrf_update_pwr_track(dm, rate_idx);
-+		ra_tab->power_tracking_flag = 0;
-+	}
-+
-+#endif
-+
-+#if 0
-+	/*trigger dynamic rate ID*/
-+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E))
-+		phydm_update_rate_id(dm, rate, macid);
-+#endif
-+}
-+
-+void odm_ra_post_action_on_assoc(void *dm_void)
-+{
-+}
-+
-+void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,
-+				   u8 ra_th_ofst)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+
-+	ra_tab->ra_ofst_direc = ra_ofst_direc;
-+	ra_tab->ra_th_ofst = ra_th_ofst;
-+	PHYDM_DBG(dm, DBG_RA_MASK, "Set ra_th_offset=(( %s%d ))\n",
-+		  ((ra_ofst_direc) ? "+" : "-"), ra_th_ofst);
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+
-+void phydm_gen_ramask_h2c_AP(
-+	void *dm_void,
-+	struct rtl8192cd_priv *priv,
-+	struct sta_info *entry,
-+	u8 rssi_level)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type == ODM_RTL8812) {
-+		#if (RTL8812A_SUPPORT == 1)
-+		UpdateHalRAMask8812(priv, entry, rssi_level);
-+		#endif
-+	} else if (dm->support_ic_type == ODM_RTL8188E) {
-+		#if (RTL8188E_SUPPORT == 1)
-+		#ifdef TXREPORT
-+		add_RATid(priv, entry);
-+		#endif
-+		#endif
-+	} else {
-+		#ifdef CONFIG_WLAN_HAL
-+		GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, entry, rssi_level);
-+		#endif
-+	}
-+}
-+
-+void phydm_update_hal_ra_mask(
-+	void *dm_void,
-+	u32 wireless_mode,
-+	u8 rf_type,
-+	u8 bw,
-+	u8 mimo_ps_enable,
-+	u8 disable_cck_rate,
-+	u32 *ratr_bitmap_msb_in,
-+	u32 *ratr_bitmap_lsb_in,
-+	u8 tx_rate_level)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 ratr_bitmap = *ratr_bitmap_lsb_in;
-+	u32 ratr_bitmap_msb = *ratr_bitmap_msb_in;
-+
-+#if 0
-+	/*PHYDM_DBG(dm, DBG_RA_MASK, "phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type);*/
-+#endif
-+	PHYDM_DBG(dm, DBG_RA_MASK,
-+		  "Platfoem original RA Mask = (( 0x %x | %x ))\n",
-+		  ratr_bitmap_msb, ratr_bitmap);
-+
-+	switch (wireless_mode) {
-+	case PHYDM_WIRELESS_MODE_B: {
-+		ratr_bitmap &= 0x0000000f;
-+	} break;
-+
-+	case PHYDM_WIRELESS_MODE_G: {
-+		ratr_bitmap &= 0x00000ff5;
-+	} break;
-+
-+	case PHYDM_WIRELESS_MODE_A: {
-+		ratr_bitmap &= 0x00000ff0;
-+	} break;
-+
-+	case PHYDM_WIRELESS_MODE_N_24G:
-+	case PHYDM_WIRELESS_MODE_N_5G: {
-+		if (mimo_ps_enable)
-+			rf_type = RF_1T1R;
-+
-+		if (rf_type == RF_1T1R) {
-+			if (bw == CHANNEL_WIDTH_40)
-+				ratr_bitmap &= 0x000ff015;
-+			else
-+				ratr_bitmap &= 0x000ff005;
-+		} else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
-+			if (bw == CHANNEL_WIDTH_40)
-+				ratr_bitmap &= 0x0ffff015;
-+			else
-+				ratr_bitmap &= 0x0ffff005;
-+		} else { /*@3T*/
-+
-+			ratr_bitmap &= 0xfffff015;
-+			ratr_bitmap_msb &= 0xf;
-+		}
-+	} break;
-+
-+	case PHYDM_WIRELESS_MODE_AC_24G: {
-+		if (rf_type == RF_1T1R) {
-+			ratr_bitmap &= 0x003ff015;
-+		} else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
-+			ratr_bitmap &= 0xfffff015;
-+		} else { /*@3T*/
-+
-+			ratr_bitmap &= 0xfffff010;
-+			ratr_bitmap_msb &= 0x3ff;
-+		}
-+
-+		if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/
-+			ratr_bitmap &= 0x7fdfffff;
-+			ratr_bitmap_msb &= 0x1ff;
-+		}
-+	} break;
-+
-+	case PHYDM_WIRELESS_MODE_AC_5G: {
-+		if (rf_type == RF_1T1R) {
-+			ratr_bitmap &= 0x003ff010;
-+		} else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
-+			ratr_bitmap &= 0xfffff010;
-+		} else { /*@3T*/
-+
-+			ratr_bitmap &= 0xfffff010;
-+			ratr_bitmap_msb &= 0x3ff;
-+		}
-+
-+		if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/
-+			ratr_bitmap &= 0x7fdfffff;
-+			ratr_bitmap_msb &= 0x1ff;
-+		}
-+	} break;
-+
-+	default:
-+		break;
-+	}
-+
-+	if (wireless_mode != PHYDM_WIRELESS_MODE_B) {
-+		if (tx_rate_level == 0)
-+			ratr_bitmap &= 0xffffffff;
-+		else if (tx_rate_level == 1)
-+			ratr_bitmap &= 0xfffffff0;
-+		else if (tx_rate_level == 2)
-+			ratr_bitmap &= 0xffffefe0;
-+		else if (tx_rate_level == 3)
-+			ratr_bitmap &= 0xffffcfc0;
-+		else if (tx_rate_level == 4)
-+			ratr_bitmap &= 0xffff8f80;
-+		else if (tx_rate_level >= 5)
-+			ratr_bitmap &= 0xffff0f00;
-+	}
-+
-+	if (disable_cck_rate)
-+		ratr_bitmap &= 0xfffffff0;
-+
-+	PHYDM_DBG(dm, DBG_RA_MASK,
-+		  "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n",
-+		  wireless_mode, rf_type, bw, mimo_ps_enable, tx_rate_level);
-+
-+#if 0
-+	/*PHYDM_DBG(dm, DBG_RA_MASK, "111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap);*/
-+#endif
-+
-+	*ratr_bitmap_lsb_in = ratr_bitmap;
-+	*ratr_bitmap_msb_in = ratr_bitmap_msb;
-+	PHYDM_DBG(dm, DBG_RA_MASK,
-+		  "Phydm modified RA Mask = (( 0x %x | %x ))\n",
-+		  *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in);
-+}
-+
-+#endif
-+
-+void phydm_rate_adaptive_mask_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_t = &dm->dm_ra_table;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	PADAPTER adapter = dm->adapter;
-+	PMGNT_INFO mgnt_info = &(adapter->MgntInfo);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)dm->adapter));
-+
-+	if (mgnt_info->DM_Type == dm_type_by_driver)
-+		hal_data->bUseRAMask = true;
-+	else
-+		hal_data->bUseRAMask = false;
-+
-+#endif
-+
-+	ra_t->ldpc_thres = 35;
-+	ra_t->up_ramask_cnt = 0;
-+	ra_t->up_ramask_cnt_tmp = 0;
-+}
-+
-+void phydm_refresh_rate_adaptive_mask(void *dm_void)
-+{
-+/*@Will be removed*/
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	phydm_ra_mask_watchdog(dm);
-+}
-+
-+void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,
-+			 char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = NULL;
-+	struct ra_sta_info *ra = NULL;
-+#ifdef CONFIG_BEAMFORMING
-+	struct bf_cmn_info *bf = NULL;
-+#endif
-+	char help[] = "-h";
-+	u32 var[10] = {0};
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 i, sta_idx_start, sta_idx_end;
-+	u8 tatal_sta_num = 0;
-+
-+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]);
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "All STA: {1}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "STA[macid]: {2} {macid}\n");
-+		return;
-+	} else if (var[0] == 1) {
-+		sta_idx_start = 0;
-+		sta_idx_end = ODM_ASSOCIATE_ENTRY_NUM;
-+	} else if (var[0] == 2) {
-+		sta_idx_start = var[1];
-+		sta_idx_end = var[1];
-+	} else {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Warning input value!\n");
-+		return;
-+	}
-+
-+	for (i = sta_idx_start; i < sta_idx_end; i++) {
-+		sta = dm->phydm_sta_info[i];
-+
-+		if (!is_sta_active(sta))
-+			continue;
-+
-+		ra = &sta->ra_info;
-+		#ifdef CONFIG_BEAMFORMING
-+		bf = &sta->bf_info;
-+		#endif
-+
-+		tatal_sta_num++;
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "==[sta_idx: %d][MACID: %d]============>\n", i,
-+			 sta->mac_id);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "AID:%d\n", sta->aid);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "ADDR:%x-%x-%x-%x-%x-%x\n", sta->mac_addr[5],
-+			 sta->mac_addr[4], sta->mac_addr[3], sta->mac_addr[2],
-+			 sta->mac_addr[1], sta->mac_addr[0]);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "DM_ctrl:0x%x\n", sta->dm_ctrl);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "BW:%d, MIMO_Type:0x%x\n", sta->bw_mode,
-+			 sta->mimo_type);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "STBC_en:%d, LDPC_en=%d\n", sta->stbc_en,
-+			 sta->ldpc_en);
-+
-+		/*@[RSSI Info]*/
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "RSSI{All, OFDM, CCK}={%d, %d, %d}\n",
-+			 sta->rssi_stat.rssi, sta->rssi_stat.rssi_ofdm,
-+			 sta->rssi_stat.rssi_cck);
-+
-+		/*@[RA Info]*/
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Rate_ID:%d, RSSI_LV:%d, ra_bw:%d, SGI_en:%d\n",
-+			 ra->rate_id, ra->rssi_level, ra->ra_bw_mode,
-+			 ra->is_support_sgi);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "VHT_en:%d, Wireless_set=0x%x, sm_ps=%d\n",
-+			 ra->is_vht_enable, sta->support_wireless_set,
-+			 sta->sm_ps);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Dis{RA, PT}={%d, %d}, TxRx:%d, Noisy:%d\n",
-+			 ra->disable_ra, ra->disable_pt, ra->txrx_state,
-+			 ra->is_noisy);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "TX{Rate, BW}={0x%x, %d}, RTY:%d\n", ra->curr_tx_rate,
-+			 ra->curr_tx_bw, ra->curr_retry_ratio);
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "RA_Mask:0x%llx\n", ra->ramask);
-+
-+		/*@[TP]*/
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "TP{TX,RX}={%d, %d}\n", sta->tx_moving_average_tp,
-+			 sta->rx_moving_average_tp);
-+
-+#ifdef CONFIG_BEAMFORMING
-+		/*@[Beamforming]*/
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "BF CAP{HT,VHT}={0x%x, 0x%x}\n", bf->ht_beamform_cap,
-+			 bf->vht_beamform_cap);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "BF {p_aid,g_id}={0x%x, 0x%x}\n\n", bf->p_aid,
-+			 bf->g_id);
-+#endif
-+	}
-+
-+	if (tatal_sta_num == 0) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "No Linked STA\n");
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+u8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 rx_num = 1;
-+
-+	if (type == RF_1T1R)
-+		rx_num = 1;
-+	else if (type == RF_2T2R || type == RF_1T2R)
-+		rx_num = 2;
-+	else if (type == RF_3T3R || type == RF_2T3R)
-+		rx_num = 3;
-+	else if (type == RF_4T4R || type == RF_3T4R || type == RF_2T4R)
-+		rx_num = 4;
-+	else
-+		pr_debug("[Warrning] %s\n", __func__);
-+
-+	return rx_num;
-+}
-+
-+u8 phydm_get_tx_stream_num(void *dm_void, enum rf_type type)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 tx_num = 1;
-+
-+	if (type == RF_1T1R || type == RF_1T2R)
-+		tx_num = 1;
-+	else if (type == RF_2T2R || type == RF_2T3R || type == RF_2T4R)
-+		tx_num = 2;
-+	else if (type == RF_3T3R || type == RF_3T4R)
-+		tx_num = 3;
-+	else if (type == RF_4T4R)
-+		tx_num = 4;
-+	else
-+		PHYDM_DBG(dm, DBG_RA, "[Warrning] no mimo_type is found\n");
-+
-+	return tx_num;
-+}
-+
-+u64 phydm_get_bb_mod_ra_mask(void *dm_void, u8 sta_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_iot_center	*iot_table = &dm->iot_table;
-+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
-+	struct ra_sta_info *ra = NULL;
-+	enum channel_width bw = 0;
-+	enum wireless_set wrls_mode = 0;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	struct rtl8192cd_priv *priv = dm->priv;
-+#endif
-+	u8 tx_stream_num = 1;
-+	u8 rssi_lv = 0;
-+	u64 ra_mask_bitmap = 0;
-+
-+	if (is_sta_active(sta)) {
-+		ra = &sta->ra_info;
-+		bw = ra->ra_bw_mode;
-+		wrls_mode = sta->support_wireless_set;
-+		tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type);
-+		rssi_lv = ra->rssi_level;
-+		ra_mask_bitmap = ra->ramask;
-+	} else {
-+		PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__);
-+		return 0;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_RA, "macid=%d ori_RA_Mask= 0x%llx\n", sta->mac_id,
-+		  ra_mask_bitmap);
-+	PHYDM_DBG(dm, DBG_RA,
-+		  "wireless_mode=0x%x, tx_ss=%d, BW=%d, MimoPs=%d, rssi_lv=%d\n",
-+		  wrls_mode, tx_stream_num, bw, sta->sm_ps, rssi_lv);
-+
-+	if (sta->sm_ps == SM_PS_STATIC) /*@mimo_ps_enable*/
-+		tx_stream_num = 1;
-+
-+	/*@[Modify RA Mask by Wireless Mode]*/
-+
-+	if (wrls_mode == WIRELESS_CCK) { /*@B mode*/
-+		ra_mask_bitmap &= 0x0000000f;
-+	} else if (wrls_mode == WIRELESS_OFDM) { /*@G mode*/
-+		ra_mask_bitmap &= 0x00000ff0;
-+	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) { /*@BG mode*/
-+		ra_mask_bitmap &= 0x00000ff5;
-+	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {
-+		/*N_2G*/
-+		if (tx_stream_num == 1) {
-+			if (bw == CHANNEL_WIDTH_40)
-+				ra_mask_bitmap &= 0x000ff015;
-+			else
-+				ra_mask_bitmap &= 0x000ff005;
-+		} else if (tx_stream_num == 2) {
-+			if (bw == CHANNEL_WIDTH_40)
-+				ra_mask_bitmap &= 0x0ffff015;
-+			else
-+				ra_mask_bitmap &= 0x0ffff005;
-+		} else if (tx_stream_num == 3) {
-+			ra_mask_bitmap &= 0xffffff015;
-+		} else {
-+			ra_mask_bitmap &= 0xffffffff015;
-+		}
-+	} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) { /*N_5G*/
-+
-+		if (tx_stream_num == 1) {
-+			if (bw == CHANNEL_WIDTH_40)
-+				ra_mask_bitmap &= 0x000ff030;
-+			else
-+				ra_mask_bitmap &= 0x000ff010;
-+		} else if (tx_stream_num == 2) {
-+			if (bw == CHANNEL_WIDTH_40)
-+				ra_mask_bitmap &= 0x0ffff030;
-+			else
-+				ra_mask_bitmap &= 0x0ffff010;
-+		} else if (tx_stream_num == 3) {
-+			ra_mask_bitmap &= 0xffffff010;
-+		} else {
-+			ra_mask_bitmap &= 0xffffffff010;
-+		}
-+	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {
-+		/*@AC_2G*/
-+		if (tx_stream_num == 1)
-+			ra_mask_bitmap &= 0x003ff015;
-+		else if (tx_stream_num == 2)
-+			ra_mask_bitmap &= 0xfffff015;
-+		else if (tx_stream_num == 3)
-+			ra_mask_bitmap &= 0x3fffffff015;
-+		else /*@AC_4SS 2G*/
-+			ra_mask_bitmap &= 0x000ffffffffff015;
-+		if (bw == CHANNEL_WIDTH_20) {
-+		/* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/
-+			ra_mask_bitmap &= 0x0007ffff7fdff015;
-+		} else if (bw == CHANNEL_WIDTH_80) {
-+		/* @AC 80MHz doesn't support 3SS MCS6*/
-+			ra_mask_bitmap &= 0x000fffbffffff015;
-+		}
-+	} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { /*@AC_5G*/
-+
-+		if (tx_stream_num == 1)
-+			ra_mask_bitmap &= 0x003ff010;
-+		else if (tx_stream_num == 2)
-+			ra_mask_bitmap &= 0xfffff010;
-+		else if (tx_stream_num == 3)
-+			ra_mask_bitmap &= 0x3fffffff010;
-+		else /*@AC_4SS 5G*/
-+			ra_mask_bitmap &= 0x000ffffffffff010;
-+
-+		if (bw == CHANNEL_WIDTH_20) {
-+		/* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/
-+			ra_mask_bitmap &= 0x0007ffff7fdff010;
-+		} else if (bw == CHANNEL_WIDTH_80) {
-+		/* @AC 80MHz doesn't support 3SS MCS6*/
-+			ra_mask_bitmap &= 0x000fffbffffff010;
-+		} else if (bw == CHANNEL_WIDTH_160) {
-+		/* @AC 80M+80M doesn't support 3SS & 4SS*/
-+			ra_mask_bitmap &= 0xfffff010;
-+		}
-+	} else {
-+		PHYDM_DBG(dm, DBG_RA, "[Warrning] RA mask is Not found\n");
-+	}
-+
-+	PHYDM_DBG(dm, DBG_RA, "Mod by mode=0x%llx\n", ra_mask_bitmap);
-+
-+#if ((DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
-+	if (priv->pshare->veriwave_sta_num > 0) {
-+		PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap);
-+		return ra_mask_bitmap;
-+	}
-+#endif
-+	/*@[Modify RA Mask by RSSI level]*/
-+	if (wrls_mode != WIRELESS_CCK) {
-+		if (iot_table->patch_id_40010700) {
-+			ra_mask_bitmap &= (rssi_lv == 0 ?
-+					  0xffffffffffffffff :
-+					  0xfffffffffffffff0);
-+			return ra_mask_bitmap;
-+		}
-+
-+		if (rssi_lv == 0)
-+			ra_mask_bitmap &= 0xffffffffffffffff;
-+		else if (rssi_lv == 1)
-+			ra_mask_bitmap &= 0xfffffffffffffff0;
-+		else if (rssi_lv == 2)
-+			ra_mask_bitmap &= 0xffffffffffffefe0;
-+		else if (rssi_lv == 3)
-+			ra_mask_bitmap &= 0xffffffffffffcfc0;
-+		else if (rssi_lv == 4)
-+			ra_mask_bitmap &= 0xffffffffffff8f80;
-+		else if (rssi_lv >= 5)
-+			ra_mask_bitmap &= 0xffffffffffff0f00;
-+	}
-+	PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap);
-+
-+	return ra_mask_bitmap;
-+}
-+
-+u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
-+	struct ra_sta_info *ra = NULL;
-+	enum wireless_set wrls_set = 0;
-+	u8 rssi_lv = 0;
-+	u8 rate_idx = 0;
-+	u8 rate_ofst = 0;
-+
-+	if (is_sta_active(sta)) {
-+		ra = &sta->ra_info;
-+		wrls_set = sta->support_wireless_set;
-+		rssi_lv = ra->rssi_level;
-+	} else {
-+		pr_debug("[Warning] %s: invalid STA\n", __func__);
-+		return 0;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_RA, "[%s]macid=%d, wireless_set=0x%x, rssi_lv=%d\n",
-+		  __func__, sta->mac_id, wrls_set, rssi_lv);
-+
-+	rate_ofst = (rssi_lv <= 1) ? 0 : (rssi_lv - 1);
-+
-+	if (wrls_set & WIRELESS_VHT) {
-+		rate_idx = ODM_RATEVHTSS1MCS0 + rate_ofst;
-+	} else if (wrls_set & WIRELESS_HT) {
-+		rate_idx = ODM_RATEMCS0 + rate_ofst;
-+	} else if (wrls_set & WIRELESS_OFDM) {
-+		rate_idx = ODM_RATE6M + rate_ofst;
-+	} else {
-+		rate_idx = ODM_RATE1M + rate_ofst;
-+
-+		if (rate_idx > ODM_RATE11M)
-+			rate_idx = ODM_RATE11M;
-+	}
-+	return rate_idx;
-+}
-+
-+u8 phydm_get_rate_id(void *dm_void, u8 sta_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
-+	struct ra_sta_info *ra = NULL;
-+	enum channel_width bw = 0;
-+	enum wireless_set wrls_mode = 0;
-+	u8 tx_stream_num = 1;
-+	u8 rate_id_idx = PHYDM_BGN_20M_1SS;
-+
-+	if (is_sta_active(sta)) {
-+		ra = &sta->ra_info;
-+		bw = ra->ra_bw_mode;
-+		wrls_mode = sta->support_wireless_set;
-+		tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type);
-+
-+	} else {
-+		PHYDM_DBG(dm, DBG_RA, "[Warning] %s: invalid STA\n", __func__);
-+		return 0;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_RA, "macid=%d,wireless_set=0x%x,tx_SS_num=%d,BW=%d\n",
-+		  sta->mac_id, wrls_mode, tx_stream_num, bw);
-+
-+	if (wrls_mode == WIRELESS_CCK) {
-+	/*@B mode*/
-+		rate_id_idx = PHYDM_B_20M;
-+	} else if (wrls_mode == WIRELESS_OFDM) {
-+	/*@G mode*/
-+		rate_id_idx = PHYDM_G;
-+	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) {
-+	/*@BG mode*/
-+		rate_id_idx = PHYDM_BG;
-+	} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) {
-+	/*@GN mode*/
-+		if (tx_stream_num == 1)
-+			rate_id_idx = PHYDM_GN_N1SS;
-+		else if (tx_stream_num == 2)
-+			rate_id_idx = PHYDM_GN_N2SS;
-+		else if (tx_stream_num == 3)
-+			rate_id_idx = PHYDM_ARFR5_N_3SS;
-+	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {
-+	 /*@BGN mode*/
-+		if (bw == CHANNEL_WIDTH_40) {
-+			if (tx_stream_num == 1)
-+				rate_id_idx = PHYDM_BGN_40M_1SS;
-+			else if (tx_stream_num == 2)
-+				rate_id_idx = PHYDM_BGN_40M_2SS;
-+			else if (tx_stream_num == 3)
-+				rate_id_idx = PHYDM_ARFR5_N_3SS;
-+			else if (tx_stream_num == 4)
-+				rate_id_idx = PHYDM_ARFR7_N_4SS;
-+
-+		} else {
-+			if (tx_stream_num == 1)
-+				rate_id_idx = PHYDM_BGN_20M_1SS;
-+			else if (tx_stream_num == 2)
-+				rate_id_idx = PHYDM_BGN_20M_2SS;
-+			else if (tx_stream_num == 3)
-+				rate_id_idx = PHYDM_ARFR5_N_3SS;
-+			else if (tx_stream_num == 4)
-+				rate_id_idx = PHYDM_ARFR7_N_4SS;
-+		}
-+	} else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) {
-+	/*@AC mode*/
-+		if (bw == CHANNEL_WIDTH_160) {
-+			if (tx_stream_num == 1)
-+				rate_id_idx = PHYDM_ARFR1_AC_1SS;
-+			else if (tx_stream_num == 2)
-+				rate_id_idx = PHYDM_ARFR0_AC_2SS;
-+			else if (tx_stream_num == 3)
-+				rate_id_idx = PHYDM_ARFR0_AC_2SS;
-+			else if (tx_stream_num == 4)
-+				rate_id_idx = PHYDM_ARFR0_AC_2SS;
-+		} else {
-+			if (tx_stream_num == 1)
-+				rate_id_idx = PHYDM_ARFR1_AC_1SS;
-+			else if (tx_stream_num == 2)
-+				rate_id_idx = PHYDM_ARFR0_AC_2SS;
-+			else if (tx_stream_num == 3)
-+				rate_id_idx = PHYDM_ARFR4_AC_3SS;
-+			else if (tx_stream_num == 4)
-+				rate_id_idx = PHYDM_ARFR6_AC_4SS;
-+			}
-+	} else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {
-+	/*@AC 2.4G mode*/
-+		if (bw >= CHANNEL_WIDTH_80) {
-+			if (tx_stream_num == 1)
-+				rate_id_idx = PHYDM_ARFR1_AC_1SS;
-+			else if (tx_stream_num == 2)
-+				rate_id_idx = PHYDM_ARFR0_AC_2SS;
-+			else if (tx_stream_num == 3)
-+				rate_id_idx = PHYDM_ARFR4_AC_3SS;
-+			else if (tx_stream_num == 4)
-+				rate_id_idx = PHYDM_ARFR6_AC_4SS;
-+		} else {
-+			if (tx_stream_num == 1) {
-+				if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2)
-+					rate_id_idx = PHYDM_TYPE2_ARFR5_AC_2G_1SS;
-+				else
-+					rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
-+			} else if (tx_stream_num == 2) {
-+				if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2)
-+					rate_id_idx = PHYDM_TYPE2_ARFR3_AC_2G_2SS;
-+				else
-+					rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
-+			} else if (tx_stream_num == 3) {
-+				rate_id_idx = PHYDM_ARFR4_AC_3SS;
-+			} else if (tx_stream_num == 4) {
-+				rate_id_idx = PHYDM_ARFR6_AC_4SS;
-+			}
-+		}
-+	} else {
-+		PHYDM_DBG(dm, DBG_RA, "[Warrning] No rate_id is found\n");
-+		rate_id_idx = 0;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_RA, "Rate_ID=((0x%x))\n", rate_id_idx);
-+
-+	return rate_id_idx;
-+}
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+void phydm_ra_mode_selection(void *dm_void, u8 mode)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+	u8 pre_mode = ra_tab->ra_trigger_mode; /* 0:pkt RA, 1:TBTT RA */
-+
-+	if (mode >= 2) {
-+		PHYDM_DBG(dm, DBG_RA, "RA mode selection Fail\n");
-+	} else {
-+		ra_tab->ra_trigger_mode = mode;
-+		PHYDM_DBG(dm, DBG_RA, "RA mode, 0:pkt RA, 1:TBTT RA\n");
-+		PHYDM_DBG(dm, DBG_RA, "PreMode=%d,CurMode=%d\n", pre_mode,
-+			  mode);
-+	}
-+}
-+#endif
-+
-+void phydm_ra_h2c(void *dm_void, u8 sta_idx, u8 dis_ra, u8 dis_pt,
-+		  u8 no_update_bw, u8 init_ra_lv, u64 ra_mask)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
-+	struct ra_sta_info *ra = NULL;
-+	u8 h2c_val[H2C_MAX_LENGTH] = {0};
-+	u8 rate_id_idx = 0;
-+
-+	if (is_sta_active(sta)) {
-+		ra = &sta->ra_info;
-+	} else {
-+		PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid sta_info\n",
-+			  __func__);
-+		return;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__);
-+	PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id);
-+	
-+#ifdef PHYDM_POWER_TRAINING_SUPPORT
-+	if ((dm->support_ability & ODM_BB_PWR_TRAIN) && !dm->is_disable_power_training)
-+		dis_pt = false;
-+	else 
-+		dis_pt = true;
-+	
-+#else
-+	dis_pt= true;
-+#endif
-+
-+	rate_id_idx = ra->rate_id;
-+
-+	/*for compatibility issues with FW RA [PHYDM-405]*/
-+	if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2) {
-+		if (rate_id_idx == PHYDM_TYPE2_ARFR5_AC_2G_1SS) 
-+			rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
-+		else if (rate_id_idx == PHYDM_TYPE2_ARFR3_AC_2G_2SS)
-+			rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
-+	}
-+
-+	h2c_val[0] = sta->mac_id;
-+	h2c_val[1] = (rate_id_idx & 0x1f) | ((init_ra_lv & 0x3) << 5) |
-+		     (ra->is_support_sgi << 7);
-+	h2c_val[2] = (u8)((ra->ra_bw_mode) | (((sta->ldpc_en) ? 1 : 0) << 2) |
-+			  ((no_update_bw & 0x1) << 3) |
-+			  (ra->is_vht_enable << 4) |
-+			  ((dis_pt & 0x1) << 6) | ((dis_ra & 0x1) << 7));
-+
-+	h2c_val[3] = (u8)(ra_mask & 0xff);
-+	h2c_val[4] = (u8)((ra_mask & 0xff00) >> 8);
-+	h2c_val[5] = (u8)((ra_mask & 0xff0000) >> 16);
-+	h2c_val[6] = (u8)((ra_mask & 0xff000000) >> 24);
-+
-+	PHYDM_DBG(dm, DBG_RA, "PHYDM h2c[0x40]=0x%x %x %x %x %x %x %x\n",
-+		  h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2],
-+		  h2c_val[1], h2c_val[0]);
-+
-+	odm_fill_h2c_cmd(dm, PHYDM_H2C_RA_MASK, H2C_MAX_LENGTH, h2c_val);
-+
-+	#if (defined(PHYDM_COMPILE_ABOVE_3SS))
-+	if (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) {
-+		h2c_val[3] = (u8)((ra_mask >> 32) & 0x000000ff);
-+		h2c_val[4] = (u8)(((ra_mask >> 32) & 0x0000ff00) >> 8);
-+		h2c_val[5] = (u8)(((ra_mask >> 32) & 0x00ff0000) >> 16);
-+		h2c_val[6] = (u8)(((ra_mask >> 32) & 0xff000000) >> 24);
-+
-+		PHYDM_DBG(dm, DBG_RA, "h2c[0x46]=0x%x %x %x %x %x %x %x\n",
-+			  h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3],
-+			  h2c_val[2], h2c_val[1], h2c_val[0]);
-+
-+		odm_fill_h2c_cmd(dm, PHYDM_RA_MASK_ABOVE_3SS,
-+				 H2C_MAX_LENGTH, h2c_val);
-+	}
-+	#endif
-+}
-+
-+void phydm_ra_registed(void *dm_void, u8 sta_idx,
-+		       /*@index of sta_info array, not MACID*/
-+		       u8 rssi_from_assoc)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_t = &dm->dm_ra_table;
-+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
-+	struct ra_sta_info *ra = NULL;
-+	u8 init_ra_lv = 0;
-+	u64 ra_mask = 0;
-+	/*@SD7 STA_idx != macid*/
-+	/*@SD4,8 STA_idx == macid, */
-+
-+	PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
-+
-+	if (is_sta_active(sta)) {
-+		ra = &sta->ra_info;
-+		PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx,
-+			  sta->mac_id);
-+	} else {
-+		PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid STA\n",
-+			  __func__);
-+		PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d\n", sta_idx);
-+		return;
-+	}
-+
-+	#if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8188E)
-+		ra->rate_id = phydm_get_rate_id_88e(dm, sta_idx);
-+	else
-+	#endif
-+	{
-+		ra->rate_id = phydm_get_rate_id(dm, sta_idx);
-+	}
-+
-+	ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);
-+
-+	PHYDM_DBG(dm, DBG_RA_MASK, "rssi_assoc=%d\n", rssi_from_assoc);
-+
-+	if (rssi_from_assoc > 40)
-+		init_ra_lv = 1;
-+	else if (rssi_from_assoc > 20)
-+		init_ra_lv = 2;
-+	else if (rssi_from_assoc > 1)
-+		init_ra_lv = 3;
-+	else
-+		init_ra_lv = 0;
-+
-+	if (ra_t->record_ra_info)
-+		ra_t->record_ra_info(dm, sta_idx, sta, ra_mask);
-+
-+	#if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8188E)
-+		/*@Driver RA*/
-+		phydm_ra_update_8188e(dm, sta_idx, ra->rate_id,
-+				      (u32)ra_mask, ra->is_support_sgi);
-+	else
-+	#endif
-+	{
-+		/*@FW RA*/
-+		phydm_ra_h2c(dm, sta_idx, ra->disable_ra, ra->disable_pt, 0,
-+			     init_ra_lv, ra_mask);
-+	}
-+}
-+
-+void phydm_ra_offline(void *dm_void, u8 sta_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_t = &dm->dm_ra_table;
-+	struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
-+	struct ra_sta_info *ra = NULL;
-+
-+	if (is_sta_active(sta)) {
-+		ra = &sta->ra_info;
-+	} else {
-+		PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__);
-+		return;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__);
-+	PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id);
-+
-+	odm_memory_set(dm, &ra->rate_id, 0, sizeof(struct ra_sta_info));
-+	ra->disable_ra = 1;
-+	ra->disable_pt = 1;
-+
-+	if (ra_t->record_ra_info)
-+		ra_t->record_ra_info(dm, sta->mac_id, sta, 0);
-+
-+	if (dm->support_ic_type != ODM_RTL8188E)
-+		phydm_ra_h2c(dm, sta->mac_id, 1, 1, 0, 0, 0);
-+}
-+
-+void phydm_ra_mask_watchdog(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_t = &dm->dm_ra_table;
-+	struct cmn_sta_info *sta = NULL;
-+	struct ra_sta_info *ra = NULL;
-+	boolean force_ra_mask_en = false;
-+	u8 sta_idx;
-+	u64 ra_mask;
-+	u8 rssi_lv_new;
-+	u8 rssi = 0;
-+
-+	if (!(dm->support_ability & ODM_BB_RA_MASK))
-+		return;
-+
-+	if (!dm->is_linked || (dm->phydm_sys_up_time % 2) == 1)
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
-+
-+	ra_t->up_ramask_cnt++;
-+
-+	if (ra_t->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD) {
-+		ra_t->up_ramask_cnt = 0;
-+		force_ra_mask_en = true;
-+	}
-+
-+	for (sta_idx = 0; sta_idx < ODM_ASSOCIATE_ENTRY_NUM; sta_idx++) {
-+		sta = dm->phydm_sta_info[sta_idx];
-+
-+		if (!is_sta_active(sta))
-+			continue;
-+
-+		ra = &sta->ra_info;
-+
-+		if (ra->disable_ra)
-+			continue;
-+
-+		PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx,
-+			  sta->mac_id);
-+
-+		rssi = (u8)(sta->rssi_stat.rssi);
-+
-+		/*@to be modified*/
-+		#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
-+		if (dm->support_ic_type == ODM_RTL8812 ||
-+			(dm->support_ic_type == ODM_RTL8821 &&
-+			 dm->cut_version == ODM_CUT_A)
-+			) {
-+			if (rssi < ra_t->ldpc_thres) {
-+				/*@LDPC TX enable*/
-+				#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+				set_ra_ldpc_8812(sta, true);
-+				#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+				MgntSet_TX_LDPC(dm->adapter, sta->mac_id, true);
-+				#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+				/*to be added*/
-+				#endif
-+				PHYDM_DBG(dm, DBG_RA_MASK,
-+					  "RSSI=%d, ldpc_en =TRUE\n", rssi);
-+
-+			} else if (rssi > (ra_t->ldpc_thres + 3)) {
-+				/*@LDPC TX disable*/
-+				#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+				set_ra_ldpc_8812(sta, false);
-+				#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+				MgntSet_TX_LDPC(dm->adapter, sta->mac_id, false);
-+				#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+				/*to be added*/
-+				#endif
-+				PHYDM_DBG(dm, DBG_RA_MASK,
-+					  "RSSI=%d, ldpc_en =FALSE\n", rssi);
-+			}
-+		}
-+		#endif
-+
-+		rssi_lv_new = phydm_rssi_lv_dec(dm, (u32)rssi, ra->rssi_level);
-+
-+		if (ra->rssi_level != rssi_lv_new ||
-+		    (force_ra_mask_en && dm->number_linked_client < 10)) {
-+			PHYDM_DBG(dm, DBG_RA_MASK, "RSSI LV:((%d))->((%d))\n",
-+				  ra->rssi_level, rssi_lv_new);
-+
-+			ra->rssi_level = rssi_lv_new;
-+
-+			ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);
-+
-+			if (ra_t->record_ra_info)
-+				ra_t->record_ra_info(dm, sta_idx, sta, ra_mask);
-+
-+			#if (RTL8188E_SUPPORT) && (RATE_ADAPTIVE_SUPPORT)
-+			if (dm->support_ic_type == ODM_RTL8188E)
-+				/*@Driver RA*/
-+				phydm_ra_update_8188e(dm, sta_idx, ra->rate_id,
-+						      (u32)ra_mask,
-+						      ra->is_support_sgi);
-+			else
-+			#endif
-+			{
-+				/*@FW RA*/
-+				phydm_ra_h2c(dm, sta_idx, ra->disable_ra,
-+					     ra->disable_pt, 1, 0, ra_mask);
-+			}
-+		}
-+	}
-+}
-+
-+u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 vht_en_out = 0;
-+
-+	if (wireless_mode == PHYDM_WIRELESS_MODE_AC_5G ||
-+	    wireless_mode == PHYDM_WIRELESS_MODE_AC_24G ||
-+	    wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY)
-+		vht_en_out = 1;
-+
-+	PHYDM_DBG(dm, DBG_RA, "wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n",
-+		  wireless_mode, vht_en_out);
-+	return vht_en_out;
-+}
-+
-+u8 phydm_rftype2rateid_2g_n20(void *dm_void, u8 rf_type)
-+{
-+	u8 rate_id_idx = 0;
-+
-+	if (rf_type == RF_1T1R)
-+		rate_id_idx = PHYDM_BGN_20M_1SS;
-+	else if (rf_type == RF_2T2R)
-+		rate_id_idx = PHYDM_BGN_20M_2SS;
-+	else if (rf_type == RF_3T3R)
-+		rate_id_idx = PHYDM_ARFR5_N_3SS;
-+	else
-+		rate_id_idx = PHYDM_ARFR7_N_4SS;
-+	return rate_id_idx;
-+}
-+
-+u8 phydm_rftype2rateid_2g_n40(void *dm_void, u8 rf_type)
-+{
-+	u8 rate_id_idx = 0;
-+
-+	if (rf_type == RF_1T1R)
-+		rate_id_idx = PHYDM_BGN_40M_1SS;
-+	else if (rf_type == RF_2T2R)
-+		rate_id_idx = PHYDM_BGN_40M_2SS;
-+	else if (rf_type == RF_3T3R)
-+		rate_id_idx = PHYDM_ARFR5_N_3SS;
-+	else
-+		rate_id_idx = PHYDM_ARFR7_N_4SS;
-+	return rate_id_idx;
-+}
-+
-+u8 phydm_rftype2rateid_5g_n(void *dm_void, u8 rf_type)
-+{
-+	u8 rate_id_idx = 0;
-+
-+	if (rf_type == RF_1T1R)
-+		rate_id_idx = PHYDM_GN_N1SS;
-+	else if (rf_type == RF_2T2R)
-+		rate_id_idx = PHYDM_GN_N2SS;
-+	else if (rf_type == RF_3T3R)
-+		rate_id_idx = PHYDM_ARFR5_N_3SS;
-+	else
-+		rate_id_idx = PHYDM_ARFR7_N_4SS;
-+	return rate_id_idx;
-+}
-+
-+u8 phydm_rftype2rateid_ac80(void *dm_void, u8 rf_type)
-+{
-+	u8 rate_id_idx = 0;
-+
-+	if (rf_type == RF_1T1R)
-+		rate_id_idx = PHYDM_ARFR1_AC_1SS;
-+	else if (rf_type == RF_2T2R)
-+		rate_id_idx = PHYDM_ARFR0_AC_2SS;
-+	else if (rf_type == RF_3T3R)
-+		rate_id_idx = PHYDM_ARFR4_AC_3SS;
-+	else
-+		rate_id_idx = PHYDM_ARFR6_AC_4SS;
-+	return rate_id_idx;
-+}
-+
-+u8 phydm_rftype2rateid_ac40(void *dm_void, u8 rf_type)
-+{
-+	u8 rate_id_idx = 0;
-+
-+	if (rf_type == RF_1T1R)
-+		rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
-+	else if (rf_type == RF_2T2R)
-+		rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
-+	else if (rf_type == RF_3T3R)
-+		rate_id_idx = PHYDM_ARFR4_AC_3SS;
-+	else
-+		rate_id_idx = PHYDM_ARFR6_AC_4SS;
-+	return rate_id_idx;
-+}
-+
-+u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 rate_id_idx = 0;
-+
-+	PHYDM_DBG(dm, DBG_RA,
-+		  "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n",
-+		  wireless_mode, rf_type, bw);
-+
-+	switch (wireless_mode) {
-+	case PHYDM_WIRELESS_MODE_N_24G:
-+		if (bw == CHANNEL_WIDTH_40)
-+			rate_id_idx = phydm_rftype2rateid_2g_n40(dm, rf_type);
-+		else
-+			rate_id_idx = phydm_rftype2rateid_2g_n20(dm, rf_type);
-+		break;
-+
-+	case PHYDM_WIRELESS_MODE_N_5G:
-+		rate_id_idx = phydm_rftype2rateid_5g_n(dm, rf_type);
-+		break;
-+
-+	case PHYDM_WIRELESS_MODE_G:
-+		rate_id_idx = PHYDM_BG;
-+		break;
-+
-+	case PHYDM_WIRELESS_MODE_A:
-+		rate_id_idx = PHYDM_G;
-+		break;
-+
-+	case PHYDM_WIRELESS_MODE_B:
-+		rate_id_idx = PHYDM_B_20M;
-+		break;
-+
-+	case PHYDM_WIRELESS_MODE_AC_5G:
-+	case PHYDM_WIRELESS_MODE_AC_ONLY:
-+		rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type);
-+		break;
-+
-+	case PHYDM_WIRELESS_MODE_AC_24G:
-+/*@Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/
-+		if (bw >= CHANNEL_WIDTH_80)
-+			rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type);
-+		else
-+			rate_id_idx = phydm_rftype2rateid_ac40(dm, rf_type);
-+		break;
-+
-+	default:
-+		rate_id_idx = 0;
-+		break;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_RA, "RA rate ID = (( 0x%x ))\n", rate_id_idx);
-+
-+	return rate_id_idx;
-+}
-+
-+u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	/*@MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/
-+	u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};
-+	u8 new_rssi_lv = 0;
-+	u8 i;
-+
-+	PHYDM_DBG(dm, DBG_RA_MASK,
-+		  "curr RA level=(%d), Table_ori=[%d, %d, %d, %d, %d, %d]\n",
-+		  ratr_state, rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2],
-+		  rssi_lv_t[3], rssi_lv_t[4], rssi_lv_t[5]);
-+
-+	for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
-+		if (i >= (ratr_state))
-+			rssi_lv_t[i] += RA_FLOOR_UP_GAP;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_RA_MASK,
-+		  "RSSI=(%d), Table_mod=[%d, %d, %d, %d, %d, %d]\n", rssi,
-+		  rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2], rssi_lv_t[3],
-+		  rssi_lv_t[4], rssi_lv_t[5]);
-+
-+	for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
-+		if (rssi < rssi_lv_t[i]) {
-+			new_rssi_lv = i;
-+			break;
-+		}
-+	}
-+	return new_rssi_lv;
-+}
-+
-+enum phydm_qam_order phydm_get_ofdm_qam_order(void *dm_void, u8 rate_idx)
-+{
-+	u8 tmp_idx = rate_idx;
-+	enum phydm_qam_order qam_order = PHYDM_QAM_BPSK;
-+	enum phydm_qam_order qam[10] = {PHYDM_QAM_BPSK, PHYDM_QAM_QPSK,
-+					PHYDM_QAM_QPSK, PHYDM_QAM_16QAM,
-+					PHYDM_QAM_16QAM, PHYDM_QAM_64QAM,
-+					PHYDM_QAM_64QAM, PHYDM_QAM_64QAM,
-+					PHYDM_QAM_256QAM, PHYDM_QAM_256QAM};
-+
-+	if (rate_idx <= ODM_RATE11M)
-+		return PHYDM_QAM_CCK;
-+
-+	if (rate_idx >= ODM_RATEVHTSS1MCS0) {
-+		if (rate_idx >= ODM_RATEVHTSS4MCS0)
-+			tmp_idx -= ODM_RATEVHTSS4MCS0;
-+		else if (rate_idx >= ODM_RATEVHTSS3MCS0)
-+			tmp_idx -= ODM_RATEVHTSS3MCS0;
-+		else if (rate_idx >= ODM_RATEVHTSS2MCS0)
-+			tmp_idx -= ODM_RATEVHTSS2MCS0;
-+		else
-+			tmp_idx -= ODM_RATEVHTSS1MCS0;
-+
-+		qam_order = qam[tmp_idx];
-+	} else if (rate_idx >= ODM_RATEMCS0) {
-+		if (rate_idx >= ODM_RATEMCS24)
-+			tmp_idx -= ODM_RATEMCS24;
-+		else if (rate_idx >= ODM_RATEMCS16)
-+			tmp_idx -= ODM_RATEMCS16;
-+		else if (rate_idx >= ODM_RATEMCS8)
-+			tmp_idx -= ODM_RATEMCS8;
-+		else
-+			tmp_idx -= ODM_RATEMCS0;
-+
-+		qam_order = qam[tmp_idx];
-+	} else {
-+		if (rate_idx > ODM_RATE6M) {
-+			tmp_idx -= ODM_RATE6M;
-+			qam_order = qam[tmp_idx - 1];
-+		} else {
-+			qam_order = PHYDM_QAM_BPSK;
-+		}
-+	}
-+
-+	return qam_order;
-+}
-+
-+u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx)
-+{
-+	u8 rate_order = rate_idx & 0x7f;
-+
-+	rate_idx &= 0x7f;
-+
-+	if (rate_idx >= ODM_RATEVHTSS4MCS0)
-+		rate_order -= ODM_RATEVHTSS4MCS0;
-+	else if (rate_idx >= ODM_RATEVHTSS3MCS0)
-+		rate_order -= ODM_RATEVHTSS3MCS0;
-+	else if (rate_idx >= ODM_RATEVHTSS2MCS0)
-+		rate_order -= ODM_RATEVHTSS2MCS0;
-+	else if (rate_idx >= ODM_RATEVHTSS1MCS0)
-+		rate_order -= ODM_RATEVHTSS1MCS0;
-+	else if (rate_idx >= ODM_RATEMCS24)
-+		rate_order -= ODM_RATEMCS24;
-+	else if (rate_idx >= ODM_RATEMCS16)
-+		rate_order -= ODM_RATEMCS16;
-+	else if (rate_idx >= ODM_RATEMCS8)
-+		rate_order -= ODM_RATEMCS8;
-+	else if (rate_idx >= ODM_RATEMCS0)
-+		rate_order -= ODM_RATEMCS0;
-+	else if (rate_idx >= ODM_RATE6M)
-+		rate_order -= ODM_RATE6M;
-+	else
-+		rate_order -= ODM_RATE1M;
-+
-+	if (rate_idx >= ODM_RATEMCS0)
-+		rate_order++;
-+
-+	return rate_order;
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+u8 phydm_rate2ss(void *dm_void, u8 rate_idx)
-+{
-+	u8 ret = 0xff;
-+	u8 i, j;
-+	u8 search_idx;
-+	u32 ss_mapping_tab[4][3] = {{0x00000000, 0x003ff000, 0x000ff000},
-+				    {0x00000000, 0xffc00000, 0x0ff00000},
-+				    {0x000003ff, 0x0000000f, 0xf0000000},
-+				    {0x000ffc00, 0x00000ff0, 0x00000000} };
-+	if (rate_idx < 32) {
-+		search_idx = rate_idx;
-+		j = 0;
-+	} else if (rate_idx < 64) {
-+		search_idx = rate_idx - 32;
-+		j = 1;
-+	} else {
-+		search_idx = rate_idx - 64;
-+		j = 2;
-+	}
-+	for (i = 0; i < 4; i++)
-+		if (ss_mapping_tab[i][j] & BIT(search_idx))
-+			ret = i;
-+	return ret;
-+}
-+
-+u8 phydm_rate2plcp(void *dm_void, u8 rate_idx)
-+{
-+	u8 rate2ss = 0;
-+	u8 ltftime = 0;
-+	u8 plcptime = 0xff;
-+
-+	if (rate_idx < ODM_RATE6M) {
-+		plcptime = 192;
-+		/* @CCK PLCP = 192us (long preamble) */
-+	} else if (rate_idx < ODM_RATEMCS0) {
-+		plcptime = 20;
-+		/* @LegOFDM PLCP = 20us */
-+	} else {
-+		if (rate_idx < ODM_RATEVHTSS1MCS0)
-+			plcptime = 32;
-+		/* @HT mode PLCP = 20us + 12us + 4us x Nss */
-+		else
-+			plcptime = 36;
-+		/* VHT mode PLCP = 20us + 16us + 4us x Nss */
-+		rate2ss = phydm_rate2ss(dm_void, rate_idx);
-+		if (rate2ss != 0xff)
-+			ltftime = (rate2ss + 1) * 4;
-+		else
-+			return 0xff;
-+
-+		plcptime += ltftime;
-+	}
-+	return plcptime;
-+}
-+
-+u8 phydm_get_plcp(void *dm_void, u16 macid)
-+{
-+	u8 plcp_time = 0;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = NULL;
-+	struct ra_sta_info *ra = NULL;
-+
-+	sta = dm->phydm_sta_info[macid];
-+	ra = &sta->ra_info;
-+	plcp_time = phydm_rate2plcp(dm, ra->curr_tx_rate);
-+	return plcp_time;
-+}
-+#endif
-+
-+void phydm_ra_common_info_update(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+	struct cmn_sta_info *sta = NULL;
-+	u16 macid;
-+	u8 rate_order_tmp;
-+	u8 rate_idx = 0;
-+	u8 cnt = 0;
-+
-+	ra_tab->highest_client_tx_order = 0;
-+	ra_tab->power_tracking_flag = 1;
-+
-+	if (!dm->number_linked_client)
-+		return;
-+
-+	for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
-+		sta = dm->phydm_sta_info[macid];
-+
-+		if (!is_sta_active(sta))
-+			continue;
-+
-+		rate_idx = sta->ra_info.curr_tx_rate & 0x7f;
-+		rate_order_tmp = phydm_rate_order_compute(dm, rate_idx);
-+
-+		if (rate_order_tmp >= ra_tab->highest_client_tx_order) {
-+			ra_tab->highest_client_tx_order = rate_order_tmp;
-+			ra_tab->highest_client_tx_rate_order = macid;
-+		}
-+
-+		cnt++;
-+
-+		if (cnt == dm->number_linked_client)
-+			break;
-+	}
-+	PHYDM_DBG(dm, DBG_RA,
-+		  "MACID[%d], Highest Tx order Update for power traking: %d\n",
-+		  ra_tab->highest_client_tx_rate_order,
-+		  ra_tab->highest_client_tx_order);
-+}
-+
-+void phydm_rrsr_set_register(void *dm_void, u32 rrsr_val)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	odm_set_mac_reg(dm, R_0x440, 0xfffff, rrsr_val);
-+}
-+
-+void phydm_masked_rrsr_set_register(void *dm_void, u32 rrsr_val)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+
-+	if (ra_tab->rrsr_val_curr == rrsr_val)
-+		return;
-+
-+	ra_tab->rrsr_val_curr = rrsr_val;
-+	odm_set_mac_reg(dm, R_0x440, 0xfffff, rrsr_val);
-+}
-+
-+void phydm_rrsr_mask(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra = &dm->dm_ra_table;
-+	struct cmn_sta_info *sta = NULL;
-+	u8 rate_order = 0;
-+	u8 rate_order_min = 0xff;
-+	u32 rrsr_mask = 0, rrsr_mask_ofdm = 0;
-+	u8 tx_rate_idx = 0;
-+	u8 i = 0, sta_cnt = 0;
-+
-+	if (!ra->dynamic_rrsr_en)
-+		return;
-+
-+	if (!dm->is_linked) {
-+		phydm_masked_rrsr_set_register(dm, ra->rrsr_val_init);
-+		return;
-+	}
-+
-+#if 1
-+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
-+		sta = dm->phydm_sta_info[i];
-+		if (!is_sta_active(sta))
-+			continue;
-+
-+		sta_cnt++;
-+		tx_rate_idx = sta->ra_info.curr_tx_rate & 0x7f;
-+		rate_order = phydm_rate_order_compute(dm, tx_rate_idx);
-+		if (rate_order < rate_order_min)
-+			rate_order_min = rate_order;
-+
-+		if (sta_cnt == dm->number_linked_client)
-+			break;
-+	}
-+#else
-+	sta = dm->phydm_sta_info[dm->rssi_min_macid];
-+
-+	if (!is_sta_active(sta)) {
-+		PHYDM_DBG(dm, DBG_DYN_ARFR, "[Warning] %s invalid STA\n",
-+			  __func__);
-+		return;
-+	}
-+
-+	rate_order = phydm_rate_order_compute(dm, sta->ra_info.curr_tx_rate);
-+#endif
-+	if (rate_order_min == 0) {
-+		rrsr_mask = 0x1f;
-+	} else {
-+		rrsr_mask_ofdm = (u32)phydm_gen_bitmask(rate_order_min);
-+		rrsr_mask = (rrsr_mask_ofdm << 4) | 0xf;
-+	}
-+
-+	/*ra->rrsr_val_init = 0x15d;*/
-+
-+	phydm_masked_rrsr_set_register(dm, ra->rrsr_val_init & rrsr_mask);
-+
-+	PHYDM_DBG(dm, DBG_DYN_ARFR,
-+		  "tx{rate, rate_order_min}={0x%x, %d}, rrsr_init=0x%x, ofdm_rrsr_mask=0x%x, rrsr_val=0x%x\n",
-+		  tx_rate_idx, rate_order_min, ra->rrsr_val_init,
-+		  rrsr_mask, ra->rrsr_val_curr);
-+}
-+
-+void phydm_ra_info_watchdog(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	phydm_ra_common_info_update(dm);
-+	phydm_ra_dynamic_retry_count(dm);
-+	phydm_rrsr_mask(dm);
-+	phydm_ra_mask_watchdog(dm);
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	odm_refresh_basic_rate_mask(dm);
-+#endif
-+}
-+
-+void phydm_rrsr_en(void *dm_void, boolean en_rrsr)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+
-+	ra_tab->dynamic_rrsr_en = en_rrsr;
-+}
-+
-+void phydm_arfr_table_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2) {
-+		/*ARFR table3(2.4g ac 2ss) for rate_id = 16*/
-+		odm_set_mac_reg(dm, R_0x494, MASKDWORD, 0xfe01f015);
-+		odm_set_mac_reg(dm, R_0x498, MASKDWORD, 0x40000000);
-+
-+		/*ARFR table5(2.4g ac 1ss) for rate_id = 18*/
-+		odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0x3ff015);
-+		odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x40000000);
-+	}
-+}
-+
-+void phydm_ra_info_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+
-+	ra_tab->highest_client_tx_rate_order = 0;
-+	ra_tab->highest_client_tx_order = 0;
-+	ra_tab->ra_th_ofst = 0;
-+	ra_tab->ra_ofst_direc = 0;
-+	ra_tab->rrsr_val_init = odm_get_mac_reg(dm, R_0x440, MASKDWORD);
-+	ra_tab->dynamic_rrsr_en = false;
-+	ra_tab->ra_trigger_mode = 1; // default TBTT RA
-+	ra_tab->ra_tx_cls_th = 255;
-+#if (RTL8822B_SUPPORT == 1)
-+	if (dm->support_ic_type == ODM_RTL8822B) {
-+		u32 ret_value;
-+
-+		ret_value = odm_get_mac_reg(dm, R_0x4c8, MASKBYTE2);
-+		odm_set_mac_reg(dm, R_0x4cc, MASKBYTE3, (ret_value - 1));
-+	}
-+#endif
-+
-+	#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
-+	phydm_ra_dynamic_retry_limit_init(dm);
-+	#endif
-+
-+	#if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/
-+	phydm_ra_dynamic_rate_id_init(dm);
-+	#endif
-+
-+	phydm_arfr_table_init(dm);
-+
-+	phydm_rate_adaptive_mask_init(dm);
-+}
-+
-+u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 rts_ini_rate = ODM_RATE6M;
-+
-+	if (is_erp_protect) { /* use CCK rate as RTS*/
-+		rts_ini_rate = ODM_RATE1M;
-+	} else {
-+		switch (tx_rate) {
-+		case ODM_RATEVHTSS4MCS9:
-+		case ODM_RATEVHTSS4MCS8:
-+		case ODM_RATEVHTSS4MCS7:
-+		case ODM_RATEVHTSS4MCS6:
-+		case ODM_RATEVHTSS4MCS5:
-+		case ODM_RATEVHTSS4MCS4:
-+		case ODM_RATEVHTSS4MCS3:
-+		case ODM_RATEVHTSS3MCS9:
-+		case ODM_RATEVHTSS3MCS8:
-+		case ODM_RATEVHTSS3MCS7:
-+		case ODM_RATEVHTSS3MCS6:
-+		case ODM_RATEVHTSS3MCS5:
-+		case ODM_RATEVHTSS3MCS4:
-+		case ODM_RATEVHTSS3MCS3:
-+		case ODM_RATEVHTSS2MCS9:
-+		case ODM_RATEVHTSS2MCS8:
-+		case ODM_RATEVHTSS2MCS7:
-+		case ODM_RATEVHTSS2MCS6:
-+		case ODM_RATEVHTSS2MCS5:
-+		case ODM_RATEVHTSS2MCS4:
-+		case ODM_RATEVHTSS2MCS3:
-+		case ODM_RATEVHTSS1MCS9:
-+		case ODM_RATEVHTSS1MCS8:
-+		case ODM_RATEVHTSS1MCS7:
-+		case ODM_RATEVHTSS1MCS6:
-+		case ODM_RATEVHTSS1MCS5:
-+		case ODM_RATEVHTSS1MCS4:
-+		case ODM_RATEVHTSS1MCS3:
-+		case ODM_RATEMCS31:
-+		case ODM_RATEMCS30:
-+		case ODM_RATEMCS29:
-+		case ODM_RATEMCS28:
-+		case ODM_RATEMCS27:
-+		case ODM_RATEMCS23:
-+		case ODM_RATEMCS22:
-+		case ODM_RATEMCS21:
-+		case ODM_RATEMCS20:
-+		case ODM_RATEMCS19:
-+		case ODM_RATEMCS15:
-+		case ODM_RATEMCS14:
-+		case ODM_RATEMCS13:
-+		case ODM_RATEMCS12:
-+		case ODM_RATEMCS11:
-+		case ODM_RATEMCS7:
-+		case ODM_RATEMCS6:
-+		case ODM_RATEMCS5:
-+		case ODM_RATEMCS4:
-+		case ODM_RATEMCS3:
-+		case ODM_RATE54M:
-+		case ODM_RATE48M:
-+		case ODM_RATE36M:
-+		case ODM_RATE24M:
-+			rts_ini_rate = ODM_RATE24M;
-+			break;
-+		case ODM_RATEVHTSS4MCS2:
-+		case ODM_RATEVHTSS4MCS1:
-+		case ODM_RATEVHTSS3MCS2:
-+		case ODM_RATEVHTSS3MCS1:
-+		case ODM_RATEVHTSS2MCS2:
-+		case ODM_RATEVHTSS2MCS1:
-+		case ODM_RATEVHTSS1MCS2:
-+		case ODM_RATEVHTSS1MCS1:
-+		case ODM_RATEMCS26:
-+		case ODM_RATEMCS25:
-+		case ODM_RATEMCS18:
-+		case ODM_RATEMCS17:
-+		case ODM_RATEMCS10:
-+		case ODM_RATEMCS9:
-+		case ODM_RATEMCS2:
-+		case ODM_RATEMCS1:
-+		case ODM_RATE18M:
-+		case ODM_RATE12M:
-+			rts_ini_rate = ODM_RATE12M;
-+			break;
-+		case ODM_RATEVHTSS4MCS0:
-+		case ODM_RATEVHTSS3MCS0:
-+		case ODM_RATEVHTSS2MCS0:
-+		case ODM_RATEVHTSS1MCS0:
-+		case ODM_RATEMCS24:
-+		case ODM_RATEMCS16:
-+		case ODM_RATEMCS8:
-+		case ODM_RATEMCS0:
-+		case ODM_RATE9M:
-+		case ODM_RATE6M:
-+			rts_ini_rate = ODM_RATE6M;
-+			break;
-+		case ODM_RATE11M:
-+		case ODM_RATE5_5M:
-+		case ODM_RATE2M:
-+		case ODM_RATE1M:
-+			rts_ini_rate = ODM_RATE1M;
-+			break;
-+		default:
-+			rts_ini_rate = ODM_RATE6M;
-+			break;
-+		}
-+	}
-+
-+	if (*dm->band_type == ODM_BAND_5G) {
-+		if (rts_ini_rate < ODM_RATE6M)
-+			rts_ini_rate = ODM_RATE6M;
-+	}
-+	return rts_ini_rate;
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+void odm_refresh_basic_rate_mask(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	void *adapter = dm->adapter;
-+	static u8 stage = 0;
-+	u8 cur_stage = 0;
-+	OCTET_STRING os_rate_set;
-+	PMGNT_INFO mgnt_info = GetDefaultMgntInfo(((PADAPTER)adapter));
-+	u8 rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M};
-+
-+	if (dm->support_ic_type != ODM_RTL8812 && dm->support_ic_type != ODM_RTL8821)
-+		return;
-+
-+	if (dm->is_linked == false) /* unlink Default port information */
-+		cur_stage = 0;
-+	else if (dm->rssi_min < 40) /* @link RSSI  < 40% */
-+		cur_stage = 1;
-+	else if (dm->rssi_min > 45) /* @link RSSI > 45% */
-+		cur_stage = 3;
-+	else
-+		cur_stage = 2; /* @link  25% <= RSSI <= 30% */
-+
-+	if (cur_stage != stage) {
-+		if (cur_stage == 1) {
-+			FillOctetString(os_rate_set, rate_set, 5);
-+			FilterSupportRate(mgnt_info->mBrates, &os_rate_set, false);
-+			phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set);
-+		} else if (cur_stage == 3 && (stage == 1 || stage == 2))
-+			phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)(&mgnt_info->mBrates));
-+	}
-+
-+	stage = cur_stage;
-+}
-+
-+#endif
-+
-+#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
-+
-+void phydm_retry_limit_table_bound(
-+	void *dm_void,
-+	u8 *retry_limit,
-+	u8 offset)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+
-+	if (*retry_limit > offset) {
-+		*retry_limit -= offset;
-+
-+		if (*retry_limit < ra_tab->retrylimit_low)
-+			*retry_limit = ra_tab->retrylimit_low;
-+		else if (*retry_limit > ra_tab->retrylimit_high)
-+			*retry_limit = ra_tab->retrylimit_high;
-+	} else
-+		*retry_limit = ra_tab->retrylimit_low;
-+}
-+
-+void phydm_reset_retry_limit_table(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_t = &dm->dm_ra_table;
-+	u8 i;
-+
-+	u8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = {
-+		1, 1, 2, 4, /*@CCK*/
-+		2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/
-+		2, 4, 6, 8, 12, 18, 20, 22, /*@20M HT-1SS*/
-+		2, 4, 6, 8, 12, 18, 20, 22 /*@20M HT-2SS*/
-+	};
-+	u8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = {
-+		1, 1, 2, 4, /*@CCK*/
-+		2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/
-+		4, 8, 12, 16, 24, 32, 32, 32, /*@40M HT-1SS*/
-+		4, 8, 12, 16, 24, 32, 32, 32 /*@40M HT-2SS*/
-+	};
-+
-+	memcpy(&ra_t->per_rate_retrylimit_20M[0],
-+	       &per_rate_retrylimit_table_20M[0], PHY_NUM_RATE_IDX);
-+	memcpy(&ra_t->per_rate_retrylimit_40M[0],
-+	       &per_rate_retrylimit_table_40M[0], PHY_NUM_RATE_IDX);
-+
-+	for (i = 0; i < PHY_NUM_RATE_IDX; i++) {
-+		phydm_retry_limit_table_bound(dm,
-+					      &ra_t->per_rate_retrylimit_20M[i],
-+					      0);
-+		phydm_retry_limit_table_bound(dm,
-+					      &ra_t->per_rate_retrylimit_40M[i],
-+					      0);
-+	}
-+}
-+
-+void phydm_ra_dynamic_retry_limit_init(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+
-+	ra_tab->retry_descend_num = RA_RETRY_DESCEND_NUM;
-+	ra_tab->retrylimit_low = RA_RETRY_LIMIT_LOW;
-+	ra_tab->retrylimit_high = RA_RETRY_LIMIT_HIGH;
-+
-+	phydm_reset_retry_limit_table(dm);
-+}
-+
-+void phydm_ra_dynamic_retry_limit(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+	u8 i, retry_offset;
-+	u32 ma_rx_tp;
-+
-+	if (dm->pre_number_active_client == dm->number_active_client) {
-+		PHYDM_DBG(dm, DBG_RA,
-+			  "pre_number_active_client ==  number_active_client\n");
-+		return;
-+
-+	} else {
-+		if (dm->number_active_client == 1) {
-+			phydm_reset_retry_limit_table(dm);
-+			PHYDM_DBG(dm, DBG_RA,
-+				  "one client only->reset to default value\n");
-+		} else {
-+			retry_offset = dm->number_active_client * ra_tab->retry_descend_num;
-+
-+			for (i = 0; i < PHY_NUM_RATE_IDX; i++) {
-+				phydm_retry_limit_table_bound(dm,
-+							      &ra_tab->per_rate_retrylimit_20M[i],
-+							      retry_offset);
-+				phydm_retry_limit_table_bound(dm,
-+							      &ra_tab->per_rate_retrylimit_40M[i],
-+							      retry_offset);
-+			}
-+		}
-+	}
-+}
-+#endif
-+
-+#if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/
-+void phydm_ra_dynamic_rate_id_on_assoc(
-+	void *dm_void,
-+	u8 wireless_mode,
-+	u8 init_rate_id)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_RA,
-+		  "[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n",
-+		  dm->rf_type, wireless_mode, init_rate_id);
-+
-+	if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) {
-+		if ((dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) &&
-+		    (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G))) {
-+			PHYDM_DBG(dm, DBG_RA,
-+				  "[ON ASSOC] set N-2SS ARFR5 table\n");
-+			odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
-+			odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/
-+		} else if ((dm->support_ic_type & (ODM_RTL8812)) &&
-+			   (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY))) {
-+			PHYDM_DBG(dm, DBG_RA,
-+				  "[ON ASSOC] set AC-2SS ARFR0 table\n");
-+			odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/
-+			odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/
-+		}
-+	}
-+}
-+
-+void phydm_ra_dynamic_rate_id_init(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {
-+		odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
-+		odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/
-+
-+		odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/
-+		odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/
-+	}
-+}
-+
-+void phydm_update_rate_id(
-+	void *dm_void,
-+	u8 rate,
-+	u8 platform_macid)
-+{
-+#if 0
-+
-+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
-+	struct ra_table		*ra_tab = &dm->dm_ra_table;
-+	u8		current_tx_ss;
-+	u8		rate_idx = rate & 0x7f; /*remove bit7 SGI*/
-+	enum wireless_set wireless_set;
-+	u8		phydm_macid;
-+	struct cmn_sta_info	*sta;
-+
-+#if 0
-+	if (rate_idx >= ODM_RATEVHTSS2MCS0) {
-+		PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT2SS-MCS%d ))\n",
-+			  platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0));
-+		/*@dummy for SD4 check patch*/
-+	} else if (rate_idx >= ODM_RATEVHTSS1MCS0) {
-+		PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT1SS-MCS%d ))\n",
-+			  platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0));
-+		/*@dummy for SD4 check patch*/
-+	} else if (rate_idx >= ODM_RATEMCS0) {
-+		PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n",
-+			  platform_macid, (rate_idx - ODM_RATEMCS0));
-+		/*@dummy for SD4 check patch*/
-+	} else {
-+		PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n",
-+			  platform_macid, rate_idx);
-+		/*@dummy for SD4 check patch*/
-+	}
-+#endif
-+
-+	phydm_macid = dm->phydm_macid_table[platform_macid];
-+	sta = dm->phydm_sta_info[phydm_macid];
-+
-+	if (is_sta_active(sta)) {
-+		wireless_set = sta->support_wireless_set;
-+
-+		if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) {
-+			if (wireless_set & WIRELESS_HT) { /*N mode*/
-+				if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*@2SS mode*/
-+
-+					sta->ra_info.rate_id  = ARFR_5_RATE_ID;
-+					PHYDM_DBG(dm, DBG_RA, "ARFR_5\n");
-+				}
-+			} else if (wireless_set & WIRELESS_VHT) {/*@AC mode*/
-+				if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*@2SS mode*/
-+
-+					sta->ra_info.rate_id  = ARFR_0_RATE_ID;
-+					PHYDM_DBG(dm, DBG_RA, "ARFR_0\n");
-+				}
-+			} else
-+				sta->ra_info.rate_id  = ARFR_0_RATE_ID;
-+
-+			PHYDM_DBG(dm, DBG_RA, "UPdate_RateID[%d]: (( 0x%x ))\n",
-+				  platform_macid, sta->ra_info.rate_id);
-+		}
-+	}
-+#endif
-+}
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_rainfo.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_rainfo.h
-new file mode 100644
-index 000000000000..5cef3ce17c99
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_rainfo.h
-@@ -0,0 +1,333 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDMRAINFO_H__
-+#define __PHYDMRAINFO_H__
-+
-+/* 2020.08.05 Fix ARFR bug due to rate_id error for 2.4G VHT mode*/
-+#define RAINFO_VERSION "8.8"
-+
-+#define	FORCED_UPDATE_RAMASK_PERIOD	5
-+
-+#define	H2C_MAX_LENGTH		7
-+
-+#define	RA_FLOOR_UP_GAP		3
-+#define	RA_FLOOR_TABLE_SIZE	7
-+
-+#define	ACTIVE_TP_THRESHOLD	1
-+#define	RA_RETRY_DESCEND_NUM	2
-+#define	RA_RETRY_LIMIT_LOW	4
-+#define	RA_RETRY_LIMIT_HIGH	32
-+
-+#define PHYDM_IS_LEGACY_RATE(rate) ((rate <= ODM_RATE54M) ? true : false)
-+#define PHYDM_IS_CCK_RATE(rate) ((rate <= ODM_RATE11M) ? true : false)
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	#define	FIRST_MACID	1
-+#else
-+	#define	FIRST_MACID	0
-+#endif
-+
-+/* @1 ============================================================
-+ * 1 enumrate
-+ * 1 ============================================================
-+ */
-+
-+enum phydm_ra_dbg_para {
-+	RADBG_PCR_TH_OFFSET	= 0,
-+	RADBG_RTY_PENALTY	= 1,
-+	RADBG_N_HIGH		= 2,
-+	RADBG_N_LOW		= 3,
-+	RADBG_TRATE_UP_TABLE	= 4,
-+	RADBG_TRATE_DOWN_TABLE	= 5,
-+	RADBG_TRYING_NECESSARY	= 6,
-+	RADBG_TDROPING_NECESSARY = 7,
-+	RADBG_RATE_UP_RTY_RATIO	= 8,
-+	RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */
-+
-+	RADBG_DEBUG_MONITOR1	= 0xc,
-+	RADBG_DEBUG_MONITOR2	= 0xd,
-+	RADBG_DEBUG_MONITOR3	= 0xe,
-+	RADBG_DEBUG_MONITOR4	= 0xf,
-+	RADBG_DEBUG_MONITOR5	= 0x10,
-+	NUM_RA_PARA
-+};
-+
-+enum phydm_wireless_mode {
-+	PHYDM_WIRELESS_MODE_UNKNOWN	= 0x00,
-+	PHYDM_WIRELESS_MODE_A		= 0x01,
-+	PHYDM_WIRELESS_MODE_B		= 0x02,
-+	PHYDM_WIRELESS_MODE_G		= 0x04,
-+	PHYDM_WIRELESS_MODE_AUTO	= 0x08,
-+	PHYDM_WIRELESS_MODE_N_24G	= 0x10,
-+	PHYDM_WIRELESS_MODE_N_5G	= 0x20,
-+	PHYDM_WIRELESS_MODE_AC_5G	= 0x40,
-+	PHYDM_WIRELESS_MODE_AC_24G	= 0x80,
-+	PHYDM_WIRELESS_MODE_AC_ONLY	= 0x100,
-+	PHYDM_WIRELESS_MODE_MAX		= 0x800,
-+	PHYDM_WIRELESS_MODE_ALL		= 0xFFFF
-+};
-+
-+enum phydm_rateid_idx {
-+	PHYDM_BGN_40M_2SS	= 0,
-+	PHYDM_BGN_40M_1SS	= 1,
-+	PHYDM_BGN_20M_2SS	= 2,
-+	PHYDM_BGN_20M_1SS	= 3,
-+	PHYDM_GN_N2SS		= 4,
-+	PHYDM_GN_N1SS		= 5,
-+	PHYDM_BG		= 6,
-+	PHYDM_G			= 7,
-+	PHYDM_B_20M		= 8,
-+	PHYDM_ARFR0_AC_2SS	= 9,
-+	PHYDM_ARFR1_AC_1SS	= 10,
-+	PHYDM_ARFR2_AC_2G_1SS	= 11,
-+	PHYDM_ARFR3_AC_2G_2SS	= 12,
-+	PHYDM_ARFR4_AC_3SS	= 13,
-+	PHYDM_ARFR5_N_3SS	= 14,
-+	PHYDM_ARFR7_N_4SS	= 15,
-+	PHYDM_ARFR6_AC_4SS	= 16
-+};
-+
-+/*ARFR4(0x49c/0x4a0) can not be used because FW BT would use.*/
-+enum phydm_rateid_idx_type_2 {
-+	PHYDM_TYPE2_AC_2SS		= 9,
-+	PHYDM_TYPE2_AC_1SS		= 10,
-+	PHYDM_TYPE2_MIX_1SS		= 11,
-+	PHYDM_TYPE2_MIX_2SS		= 12,
-+	PHYDM_TYPE2_ARFR3_AC_2G_2SS	= 16, /*0x494/0x498*/
-+	PHYDM_TYPE2_ARFR5_AC_2G_1SS	= 18  /*0x4a4/0x4a8*/
-+};
-+
-+enum phydm_qam_order {
-+	PHYDM_QAM_CCK	= 0,
-+	PHYDM_QAM_BPSK	= 1,
-+	PHYDM_QAM_QPSK	= 2,
-+	PHYDM_QAM_16QAM	= 3,
-+	PHYDM_QAM_64QAM	= 4,
-+	PHYDM_QAM_256QAM = 5
-+};
-+
-+#if (RATE_ADAPTIVE_SUPPORT == 1)/* @88E RA */
-+
-+struct _phydm_txstatistic_ {
-+	u32	hw_total_tx;
-+	u32	hw_tx_success;
-+	u32	hw_tx_rty;
-+	u32	hw_tx_drop;
-+};
-+
-+/* @1 ============================================================
-+ * 1  structure
-+ * 1 ============================================================
-+ */
-+struct _odm_ra_info_ {
-+	u8	rate_id;
-+	u32	rate_mask;
-+	u32	ra_use_rate;
-+	u8	rate_sgi;
-+	u8	rssi_sta_ra;
-+	u8	pre_rssi_sta_ra;
-+	u8	sgi_enable;
-+	u8	decision_rate;
-+	u8	pre_rate;
-+	u8	highest_rate;
-+	u8	lowest_rate;
-+	u32	nsc_up;
-+	u32	nsc_down;
-+	u16	RTY[5];
-+	u32	TOTAL;
-+	u16	DROP;
-+	u8	active;
-+	u16	rpt_time;
-+	u8	ra_waiting_counter;
-+	u8	ra_pending_counter;
-+	u8	ra_drop_after_down;
-+#if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile  pass only~! */
-+	u8	pt_active;	/* on or off */
-+	u8	pt_try_state;	/* @0 trying state, 1 for decision state */
-+	u8	pt_stage;	/* @0~6 */
-+	u8	pt_stop_count;	/* Stop PT counter */
-+	u8	pt_pre_rate;	/* @if rate change do PT */
-+	u8	pt_pre_rssi;	/* @if RSSI change 5% do PT */
-+	u8	pt_mode_ss;	/* @decide whitch rate should do PT */
-+	u8	ra_stage;	/* @StageRA, decide how many times RA will be done between PT */
-+	u8	pt_smooth_factor;
-+#endif
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP) &&	((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
-+	u8	rate_down_counter;
-+	u8	rate_up_counter;
-+	u8	rate_direction;
-+	u8	bounding_type;
-+	u8	bounding_counter;
-+	u8	bounding_learning_time;
-+	u8	rate_down_start_time;
-+#endif
-+};
-+#endif
-+
-+
-+struct ra_table {
-+	#ifdef MU_EX_MACID
-+	u8	mu1_rate[MU_EX_MACID];
-+	#endif
-+	u8	highest_client_tx_order;
-+	u16	highest_client_tx_rate_order;
-+	u8	power_tracking_flag;
-+	u8	ra_th_ofst; /*RA_threshold_offset*/
-+	u8	ra_ofst_direc; /*RA_offset_direction*/
-+	u8	up_ramask_cnt; /*@force update_ra_mask counter*/
-+	u8	up_ramask_cnt_tmp; /*@Just for debug, should be removed latter*/
-+	u32	rrsr_val_init; /*0x440*/
-+	u32	rrsr_val_curr; /*0x440*/
-+	boolean dynamic_rrsr_en;
-+	u8	ra_trigger_mode; /*0: pkt RA, 1: TBTT RA*/
-+	u8	ra_tx_cls_th;	 /*255: auto, xx: in dB*/
-+#if 0	/*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
-+	u8	per_rate_retrylimit_20M[PHY_NUM_RATE_IDX];
-+	u8	per_rate_retrylimit_40M[PHY_NUM_RATE_IDX];
-+	u8	retry_descend_num;
-+	u8	retrylimit_low;
-+	u8	retrylimit_high;
-+#endif
-+	u8	ldpc_thres; /* @if RSSI > ldpc_th => switch from LPDC to BCC */
-+	void (*record_ra_info)(void *dm_void, u8 macid,
-+			       struct cmn_sta_info *sta, u64 ra_mask);
-+	u8	ra_mask_rpt_stamp;
-+	u8 	ra_mask_buf[8];
-+};
-+
-+struct ra_mask_rpt_trig {
-+	u8			ra_mask_rpt_stamp;
-+	u8			macid;
-+};
-+
-+struct ra_mask_rpt {
-+	u8			ra_mask_rpt_stamp;
-+	u8 			ra_mask_buf[8];
-+};
-+
-+/* @1 ============================================================
-+ * 1  Function Prototype
-+ * 1 ============================================================
-+ */
-+boolean phydm_is_cck_rate(void *dm_void, u8 rate);
-+
-+boolean phydm_is_ofdm_rate(void *dm_void, u8 rate);
-+
-+boolean phydm_is_ht_rate(void *dm_void, u8 rate);
-+
-+boolean phydm_is_vht_rate(void *dm_void, u8 rate);
-+
-+u8 phydm_legacy_rate_2_spec_rate(void *dm_void, u8 rate);
-+
-+u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate);
-+
-+u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type);
-+
-+u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate);
-+
-+void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,
-+		     char *output, u32 *_out_len);
-+
-+void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
-+		    u32 *_out_len);
-+
-+void phydm_ra_mask_report_h2c_trigger(void *dm_void,
-+				      struct ra_mask_rpt_trig *trig_rpt);
-+
-+void phydm_ra_mask_report_c2h_result(void *dm_void, struct ra_mask_rpt *rpt);
-+
-+void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
-+
-+void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component);
-+
-+void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size);
-+
-+void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
-+
-+u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx);
-+
-+void phydm_rrsr_set_register(void *dm_void, u32 rrsr_val);
-+
-+void phydm_ra_info_watchdog(void *dm_void);
-+
-+void phydm_rrsr_en(void *dm_void, boolean en_rrsr);
-+
-+void phydm_ra_info_init(void *dm_void);
-+
-+void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,
-+				   u8 ra_th_ofst);
-+
-+u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode);
-+
-+u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw);
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+void phydm_update_hal_ra_mask(
-+	void *dm_void,
-+	u32 wireless_mode,
-+	u8 rf_type,
-+	u8 BW,
-+	u8 mimo_ps_enable,
-+	u8 disable_cck_rate,
-+	u32 *ratr_bitmap_msb_in,
-+	u32 *ratr_bitmap_in,
-+	u8 tx_rate_level);
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+u8 phydm_get_plcp(void *dm_void, u16 macid);
-+#endif
-+
-+void phydm_refresh_rate_adaptive_mask(void *dm_void);
-+
-+u8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type);
-+
-+u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state);
-+
-+void odm_ra_post_action_on_assoc(void *dm);
-+
-+u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect);
-+
-+void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,
-+			 char *output, u32 *_out_len);
-+
-+u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx);
-+
-+void phydm_ra_registed(void *dm_void, u8 macid, u8 rssi_from_assoc);
-+
-+void phydm_ra_offline(void *dm_void, u8 macid);
-+
-+void phydm_ra_mask_watchdog(void *dm_void);
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void odm_refresh_basic_rate_mask(
-+	void *dm_void);
-+#endif
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+void phydm_ra_mode_selection(void *dm_void, u8 mode);
-+#endif
-+
-+#endif /*@#ifndef __PHYDMRAINFO_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_reg.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_reg.h
-new file mode 100644
-index 000000000000..0835f34bd4d6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_reg.h
-@@ -0,0 +1,243 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+/*************************************************************
-+ * File Name: odm_reg.h
-+ *
-+ * Description:
-+ *
-+ * This file is for general register definition.
-+ *
-+ *
-+ ************************************************************/
-+#ifndef __HAL_ODM_REG_H__
-+#define __HAL_ODM_REG_H__
-+
-+/*@
-+ * Register Definition
-+ *
-+ */
-+
-+/* @MAC REG */
-+#define	ODM_BB_RESET				0x002
-+#define	ODM_DUMMY				0x4fe
-+#define	RF_T_METER_OLD				0x24
-+#define	RF_T_METER_NEW				0x42
-+
-+#define	ODM_EDCA_VO_PARAM			0x500
-+#define	ODM_EDCA_VI_PARAM			0x504
-+#define	ODM_EDCA_BE_PARAM			0x508
-+#define	ODM_EDCA_BK_PARAM			0x50C
-+#define	ODM_TXPAUSE				0x522
-+
-+/* @LTE_COEX */
-+#define REG_LTECOEX_CTRL			0x07C0
-+#define REG_LTECOEX_WRITE_DATA			0x07C4
-+#define REG_LTECOEX_READ_DATA			0x07C8
-+#define REG_LTECOEX_PATH_CONTROL		0x70
-+
-+/* @BB REG */
-+#define	ODM_FPGA_PHY0_PAGE8			0x800
-+#define	ODM_PSD_SETTING				0x808
-+#define	ODM_AFE_SETTING				0x818
-+#define	ODM_TXAGC_B_6_18			0x830
-+#define	ODM_TXAGC_B_24_54			0x834
-+#define	ODM_TXAGC_B_MCS32_5			0x838
-+#define	ODM_TXAGC_B_MCS0_MCS3			0x83c
-+#define	ODM_TXAGC_B_MCS4_MCS7			0x848
-+#define	ODM_TXAGC_B_MCS8_MCS11			0x84c
-+#define	ODM_ANALOG_REGISTER			0x85c
-+#define	ODM_RF_INTERFACE_OUTPUT			0x860
-+#define	ODM_TXAGC_B_MCS12_MCS15			0x868
-+#define	ODM_TXAGC_B_11_A_2_11			0x86c
-+#define	ODM_AD_DA_LSB_MASK			0x874
-+#define	ODM_ENABLE_3_WIRE			0x88c
-+#define	ODM_PSD_REPORT				0x8b4
-+#define	ODM_R_ANT_SELECT			0x90c
-+#define	ODM_CCK_ANT_SELECT			0xa07
-+#define	ODM_CCK_PD_THRESH			0xa0a
-+#define	ODM_CCK_RF_REG1				0xa11
-+#define	ODM_CCK_MATCH_FILTER			0xa20
-+#define	ODM_CCK_RAKE_MAC			0xa2e
-+#define	ODM_CCK_CNT_RESET			0xa2d
-+#define	ODM_CCK_TX_DIVERSITY			0xa2f
-+#define	ODM_CCK_FA_CNT_MSB			0xa5b
-+#define	ODM_CCK_FA_CNT_LSB			0xa5c
-+#define	ODM_CCK_NEW_FUNCTION			0xa75
-+#define	ODM_OFDM_PHY0_PAGE_C			0xc00
-+#define	ODM_OFDM_RX_ANT				0xc04
-+#define	ODM_R_A_RXIQI				0xc14
-+#define	ODM_R_A_AGC_CORE1			0xc50
-+#define	ODM_R_A_AGC_CORE2			0xc54
-+#define	ODM_R_B_AGC_CORE1			0xc58
-+#define	ODM_R_AGC_PAR				0xc70
-+#define	ODM_R_HTSTF_AGC_PAR			0xc7c
-+#define	ODM_TX_PWR_TRAINING_A			0xc90
-+#define	ODM_TX_PWR_TRAINING_B			0xc98
-+#define	ODM_OFDM_FA_CNT1			0xcf0
-+#define	ODM_OFDM_PHY0_PAGE_D			0xd00
-+#define	ODM_OFDM_FA_CNT2			0xda0
-+#define	ODM_OFDM_FA_CNT3			0xda4
-+#define	ODM_OFDM_FA_CNT4			0xda8
-+#define	ODM_TXAGC_A_6_18			0xe00
-+#define	ODM_TXAGC_A_24_54			0xe04
-+#define	ODM_TXAGC_A_1_MCS32			0xe08
-+#define	ODM_TXAGC_A_MCS0_MCS3			0xe10
-+#define	ODM_TXAGC_A_MCS4_MCS7			0xe14
-+#define	ODM_TXAGC_A_MCS8_MCS11			0xe18
-+#define	ODM_TXAGC_A_MCS12_MCS15			0xe1c
-+
-+/* RF REG */
-+#define	ODM_GAIN_SETTING			0x00
-+#define	ODM_CHANNEL				0x18
-+#define	ODM_RF_T_METER				0x24
-+#define	ODM_RF_T_METER_92D			0x42
-+#define	ODM_RF_T_METER_88E			0x42
-+#define	ODM_RF_T_METER_92E			0x42
-+#define	ODM_RF_T_METER_8812			0x42
-+#define	REG_RF_TX_GAIN_OFFSET			0x55
-+
-+/* @ant Detect Reg */
-+#define	ODM_DPDT				0x300
-+
-+/* PSD Init */
-+#define	ODM_PSDREG				0x808
-+
-+/* @92D path Div */
-+#define	PATHDIV_REG				0xB30
-+#define	PATHDIV_TRI				0xBA0
-+
-+
-+/*@
-+ * Bitmap Definition
-+ */
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-+	/* TX AGC */
-+	#define		REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR		0xc20
-+	#define		REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR		0xc24
-+	#define		REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR		0xc28
-+	#define		REG_TX_AGC_A_MCS3_MCS0_JAGUAR			0xc2c
-+	#define		REG_TX_AGC_A_MCS7_MCS4_JAGUAR			0xc30
-+	#define		REG_TX_AGC_A_MCS11_MCS8_JAGUAR			0xc34
-+	#define		REG_TX_AGC_A_MCS15_MCS12_JAGUAR			0xc38
-+	#define		REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	0xc3c
-+	#define		REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	0xc40
-+	#define		REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	0xc44
-+	#define		REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	0xc48
-+	#define		REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	0xc4c
-+	#if defined(CONFIG_WLAN_HAL_8814AE)
-+		#define		REG_TX_AGC_A_MCS19_MCS16_JAGUAR		0xcd8
-+		#define		REG_TX_AGC_A_MCS23_MCS20_JAGUAR		0xcdc
-+		#define		REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	0xce0
-+		#define		REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	0xce4
-+		#define		REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	0xce8
-+	#endif
-+	#define		REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR		0xe20
-+	#define		REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR		0xe24
-+	#define		REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR		0xe28
-+	#define		REG_TX_AGC_B_MCS3_MCS0_JAGUAR			0xe2c
-+	#define		REG_TX_AGC_B_MCS7_MCS4_JAGUAR			0xe30
-+	#define		REG_TX_AGC_B_MCS11_MCS8_JAGUAR			0xe34
-+	#define		REG_TX_AGC_B_MCS15_MCS12_JAGUAR			0xe38
-+	#define		REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	0xe3c
-+	#define		REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	0xe40
-+	#define		REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	0xe44
-+	#define		REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	0xe48
-+	#define		REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	0xe4c
-+	#if defined(CONFIG_WLAN_HAL_8814AE)
-+		#define		REG_TX_AGC_B_MCS19_MCS16_JAGUAR		0xed8
-+		#define		REG_TX_AGC_B_MCS23_MCS20_JAGUAR		0xedc
-+		#define		REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	0xee0
-+		#define		REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	0xee4
-+		#define		REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	0xee8
-+		#define		REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR	0x1820
-+		#define		REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR	0x1824
-+		#define		REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR	0x1828
-+		#define		REG_TX_AGC_C_MCS3_MCS0_JAGUAR		0x182c
-+		#define		REG_TX_AGC_C_MCS7_MCS4_JAGUAR		0x1830
-+		#define		REG_TX_AGC_C_MCS11_MCS8_JAGUAR		0x1834
-+		#define		REG_TX_AGC_C_MCS15_MCS12_JAGUAR		0x1838
-+		#define		REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	0x183c
-+		#define		REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	0x1840
-+		#define		REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	0x1844
-+		#define		REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	0x1848
-+		#define		REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	0x184c
-+		#define		REG_TX_AGC_C_MCS19_MCS16_JAGUAR		0x18d8
-+		#define		REG_TX_AGC_C_MCS23_MCS20_JAGUAR		0x18dc
-+		#define		REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	0x18e0
-+		#define		REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	0x18e4
-+		#define		REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	0x18e8
-+		#define		REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR	0x1a20
-+		#define		REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR	0x1a24
-+		#define		REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR	0x1a28
-+		#define		REG_TX_AGC_D_MCS3_MCS0_JAGUAR		0x1a2c
-+		#define		REG_TX_AGC_D_MCS7_MCS4_JAGUAR		0x1a30
-+		#define		REG_TX_AGC_D_MCS11_MCS8_JAGUAR		0x1a34
-+		#define		REG_TX_AGC_D_MCS15_MCS12_JAGUAR		0x1a38
-+		#define		REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	0x1a3c
-+		#define		REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	0x1a40
-+		#define		REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	0x1a44
-+		#define		REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	0x1a48
-+		#define		REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	0x1a4c
-+		#define		REG_TX_AGC_D_MCS19_MCS16_JAGUAR		0x1ad8
-+		#define		REG_TX_AGC_D_MCS23_MCS20_JAGUAR		0x1adc
-+		#define		REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	0x1ae0
-+		#define		REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	0x1ae4
-+		#define		REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	0x1ae8
-+	#endif
-+
-+	#define		is_tx_agc_byte0_jaguar	0xff
-+	#define		is_tx_agc_byte1_jaguar	0xff00
-+	#define		is_tx_agc_byte2_jaguar	0xff0000
-+	#define		is_tx_agc_byte3_jaguar	0xff000000
-+#if defined(CONFIG_WLAN_HAL_8198F) || defined(CONFIG_WLAN_HAL_8822CE) ||\
-+defined(CONFIG_WLAN_HAL_8814BE) || defined(CONFIG_WLAN_HAL_8812FE) ||\
-+defined(CONFIG_WLAN_HAL_8197G)
-+		#define REG_TX_AGC_CCK_11_CCK_1_JAGUAR3		0x3a00
-+		#define REG_TX_AGC_OFDM_18_CCK_6_JAGUAR3	0x3a04
-+		#define	REG_TX_AGC_OFDM_54_CCK_24_JAGUAR3	0x3a08
-+		#define	REG_TX_AGC_MCS3_0_JAGUAR3		0x3a0c
-+		#define	REG_TX_AGC_MCS7_4_JAGUAR3		0x3a10
-+		#define	REG_TX_AGC_MCS11_8_JAGUAR3		0x3a14
-+		#define	REG_TX_AGC_MCS15_12_JAGUAR3		0x3a18
-+		#define	REG_TX_AGC_MCS19_16_JAGUAR3		0x3a1c
-+		#define	REG_TX_AGC_MCS23_20_JAGUAR3		0x3a20
-+		#define	REG_TX_AGC_MCS27_24_JAGUAR3		0x3a24
-+		#define	REG_TX_AGC_MCS31_28_JAGUAR3		0x3a28
-+		#define	REG_TX_AGC_VHT_Nss1_MCS3_0_JAGUAR3	0x3a2c
-+		#define	REG_TX_AGC_VHT_Nss1_MCS7_4_JAGUAR3	0x3a30
-+		#define	REG_TX_AGC_VHT_NSS2_MCS1_NSS1_MCS8_JAGUAR3	0x3a34
-+		#define	REG_TX_AGC_VHT_Nss2_MCS5_2_JAGUAR3	0x3a38
-+		#define	REG_TX_AGC_VHT_Nss2_MCS9_6_JAGUAR3	0x3a3c
-+		#define	REG_TX_AGC_VHT_Nss3_MCS3_0_JAGUAR3	0x3a40
-+		#define	REG_TX_AGC_VHT_Nss3_MCS7_4_JAGUAR3	0x3a44
-+		#define	REG_TX_AGC_VHT_Nss4_MCS1_Nss3_MCS8_JAGUAR3	0x3a48
-+		#define	REG_TX_AGC_VHT_Nss4_MCS5_2_JAGUAR3	0x3a4c
-+		#define	REG_TX_AGC_VHT_Nss4_MCS9_6_JAGUAR3	0x3a50
-+#endif
-+#endif
-+
-+#define	BIT_FA_RESET					BIT(0)
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_regdefine11ac.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_regdefine11ac.h
-new file mode 100644
-index 000000000000..7824ac22ca21
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_regdefine11ac.h
-@@ -0,0 +1,109 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __ODM_REGDEFINE11AC_H__
-+#define __ODM_REGDEFINE11AC_H__
-+
-+/* @2 RF REG LIST */
-+
-+
-+
-+/* @2 BB REG LIST */
-+/* PAGE 8 */
-+#define	ODM_REG_CCK_RPT_FORMAT_11AC		0x804
-+#define	ODM_REG_BB_RX_PATH_11AC			0x808
-+#define	ODM_REG_BB_TX_PATH_11AC			0x80c
-+#define	ODM_REG_BB_ATC_11AC			0x860
-+#define	ODM_REG_EDCCA_POWER_CAL			0x8dc
-+#define	ODM_REG_DBG_RPT_11AC			0x8fc
-+/* PAGE 9 */
-+#define	ODM_REG_EDCCA_DOWN_OPT			0x900
-+#define	ODM_REG_ACBB_EDCCA_ENHANCE		0x944
-+#define	odm_adc_trigger_jaguar2			0x95C	/*@ADC sample mode*/
-+#define	ODM_REG_OFDM_FA_RST_11AC		0x9A4
-+#define	ODM_REG_CCX_PERIOD_11AC			0x990
-+#define	ODM_REG_NHM_TH9_TH10_11AC		0x994
-+#define	ODM_REG_CLM_11AC			0x994
-+#define	ODM_REG_NHM_TH3_TO_TH0_11AC		0x998
-+#define	ODM_REG_NHM_TH7_TO_TH4_11AC		0x99c
-+#define	ODM_REG_NHM_TH8_11AC			0x9a0
-+#define	ODM_REG_NHM_9E8_11AC			0x9e8
-+#define	ODM_REG_CSI_CONTENT_VALUE		0x9b4
-+/* PAGE A */
-+#define	ODM_REG_CCK_CCA_11AC			0xA0A
-+#define	ODM_REG_CCK_FA_RST_11AC			0xA2C
-+#define	ODM_REG_CCK_FA_11AC			0xA5C
-+/* PAGE B */
-+#define	ODM_REG_RST_RPT_11AC			0xB58
-+/* PAGE C */
-+#define	ODM_REG_TRMUX_11AC			0xC08
-+#define	ODM_REG_IGI_A_11AC			0xC50
-+/* PAGE E */
-+#define	ODM_REG_IGI_B_11AC			0xE50
-+#define	ODM_REG_ANT_11AC_B			0xE08
-+/* PAGE F */
-+#define	ODM_REG_CCK_CRC32_CNT_11AC		0xF04
-+#define	ODM_REG_CCK_CCA_CNT_11AC		0xF08
-+#define	ODM_REG_VHT_CRC32_CNT_11AC		0xF0c
-+#define	ODM_REG_HT_CRC32_CNT_11AC		0xF10
-+#define	ODM_REG_OFDM_CRC32_CNT_11AC		0xF14
-+#define	ODM_REG_OFDM_FA_11AC			0xF48
-+#define	ODM_REG_OFDM_FA_TYPE1_11AC		0xFCC
-+#define	ODM_REG_OFDM_FA_TYPE2_11AC		0xFD0
-+#define	ODM_REG_OFDM_FA_TYPE3_11AC		0xFBC
-+#define	ODM_REG_OFDM_FA_TYPE4_11AC		0xFC0
-+#define	ODM_REG_OFDM_FA_TYPE5_11AC		0xFC4
-+#define	ODM_REG_OFDM_FA_TYPE6_11AC		0xFC8
-+#define	ODM_REG_RPT_11AC			0xfa0
-+#define	ODM_REG_CLM_RESULT_11AC			0xfa4
-+#define	ODM_REG_NHM_CNT_11AC			0xfa8
-+#define ODM_REG_NHM_DUR_READY_11AC		0xfb4
-+
-+#define	ODM_REG_NHM_CNT7_TO_CNT4_11AC		0xfac
-+#define	ODM_REG_NHM_CNT11_TO_CNT8_11AC		0xfb0
-+/* PAGE 18 */
-+#define	ODM_REG_IGI_C_11AC			0x1850
-+/* PAGE 1A */
-+#define	ODM_REG_IGI_D_11AC			0x1A50
-+
-+/* PAGE 1D */
-+#define	ODM_REG_IGI_11AC3			0x1D70
-+
-+/* @2 MAC REG LIST */
-+#define	ODM_REG_RESP_TX_11AC			0x6D8
-+
-+
-+
-+/* @DIG Related */
-+#define	ODM_BIT_IGI_11AC			0x0000007F
-+#define	ODM_BIT_IGI_B_11AC3			0x00007F00
-+#define	ODM_BIT_IGI_C_11AC3			0x007F0000
-+#define	ODM_BIT_IGI_D_11AC3			0x7F000000
-+#define	ODM_BIT_CCK_RPT_FORMAT_11AC		BIT(16)
-+#define	ODM_BIT_BB_RX_PATH_11AC			0xF
-+#define	ODM_BIT_BB_TX_PATH_11AC			0xF
-+#define	ODM_BIT_BB_ATC_11AC			BIT(14)
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_regdefine11n.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_regdefine11n.h
-new file mode 100644
-index 000000000000..aa162327a5a4
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_regdefine11n.h
-@@ -0,0 +1,220 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __ODM_REGDEFINE11N_H__
-+#define __ODM_REGDEFINE11N_H__
-+
-+/* @2 RF REG LIST */
-+#define	ODM_REG_RF_MODE_11N			0x00
-+#define	ODM_REG_RF_0B_11N			0x0B
-+#define	ODM_REG_CHNBW_11N			0x18
-+#define	ODM_REG_T_METER_11N			0x24
-+#define	ODM_REG_RF_25_11N			0x25
-+#define	ODM_REG_RF_26_11N			0x26
-+#define	ODM_REG_RF_27_11N			0x27
-+#define	ODM_REG_RF_2B_11N			0x2B
-+#define	ODM_REG_RF_2C_11N			0x2C
-+#define	ODM_REG_RXRF_A3_11N			0x3C
-+#define	ODM_REG_T_METER_92D_11N			0x42
-+#define	ODM_REG_T_METER_88E_11N			0x42
-+#define	ODM_REF_RF_DF_11N			0xDF
-+
-+
-+
-+/* @2 BB REG LIST
-+ * PAGE 8
-+ */
-+#define	ODM_REG_BB_CTRL_11N			0x800
-+#define	ODM_REG_RF_PIN_11N			0x804
-+#define	ODM_REG_PSD_CTRL_11N			0x808
-+#define	ODM_REG_TX_ANT_CTRL_11N			0x80C
-+#define	ODM_REG_BB_PWR_SAV5_11N			0x818
-+#define	ODM_REG_CCK_RPT_FORMAT_11N		0x824
-+#define	ODM_REG_CCK_RPT_FORMAT_11N_B		0x82C
-+#define	ODM_REG_RX_DEFAULT_A_11N		0x858
-+#define	ODM_REG_RX_DEFAULT_B_11N		0x85A
-+#define	ODM_REG_BB_PWR_SAV3_11N			0x85C
-+#define	ODM_REG_ANTSEL_CTRL_11N			0x860
-+#define	ODM_REG_RX_ANT_CTRL_11N			0x864
-+#define	ODM_REG_PIN_CTRL_11N			0x870
-+#define	ODM_REG_BB_PWR_SAV1_11N			0x874
-+#define	ODM_REG_ANTSEL_PATH_11N			0x878
-+#define	ODM_REG_BB_3WIRE_11N			0x88C
-+#define	ODM_REG_SC_CNT_11N			0x8C4
-+#define	ODM_REG_PSD_DATA_11N			0x8B4
-+#define	ODM_REG_CCX_PERIOD_11N			0x894
-+#define	ODM_REG_NHM_TH9_TH10_11N		0x890
-+#define	ODM_REG_CLM_11N				0x890
-+#define	ODM_REG_NHM_TH3_TO_TH0_11N		0x898
-+#define	ODM_REG_NHM_TH7_TO_TH4_11N		0x89c
-+#define ODM_REG_NHM_TH8_11N			0xe28
-+#define	ODM_REG_CLM_READY_11N			0x8b4
-+#define	ODM_REG_CLM_RESULT_11N			0x8d0
-+#define	ODM_REG_NHM_CNT_11N			0x8d8
-+
-+/* @For struct acs_info, Jeffery, 2014-12-26 */
-+#define	ODM_REG_NHM_CNT7_TO_CNT4_11N		0x8dc
-+#define	ODM_REG_NHM_CNT9_TO_CNT8_11N		0x8d0
-+#define	ODM_REG_NHM_CNT10_TO_CNT11_11N		0x8d4
-+
-+/* PAGE 9 */
-+#define	ODM_REG_BB_CTRL_PAGE9_11N		0x900
-+#define	ODM_REG_DBG_RPT_11N			0x908
-+#define	ODM_REG_BB_TX_PATH_11N			0x90c
-+#define	ODM_REG_ANT_MAPPING1_11N		0x914
-+#define	ODM_REG_ANT_MAPPING2_11N		0x918
-+#define	ODM_REG_EDCCA_DOWN_OPT_11N		0x948
-+#define	ODM_REG_RX_DFIR_MOD_97F			0x948
-+#define	ODM_REG_SOML_97F			0x998
-+
-+/* PAGE A */
-+#define	ODM_REG_CCK_ANTDIV_PARA1_11N		0xA00
-+#define	ODM_REG_CCK_ANT_SEL_11N			0xA04
-+#define	ODM_REG_CCK_CCA_11N			0xA0A
-+#define	ODM_REG_CCK_ANTDIV_PARA2_11N		0xA0C
-+#define	ODM_REG_CCK_ANTDIV_PARA3_11N		0xA10
-+#define	ODM_REG_CCK_ANTDIV_PARA4_11N		0xA14
-+#define	ODM_REG_CCK_FILTER_PARA1_11N		0xA22
-+#define	ODM_REG_CCK_FILTER_PARA2_11N		0xA23
-+#define	ODM_REG_CCK_FILTER_PARA3_11N		0xA24
-+#define	ODM_REG_CCK_FILTER_PARA4_11N		0xA25
-+#define	ODM_REG_CCK_FILTER_PARA5_11N		0xA26
-+#define	ODM_REG_CCK_FILTER_PARA6_11N		0xA27
-+#define	ODM_REG_CCK_FILTER_PARA7_11N		0xA28
-+#define	ODM_REG_CCK_FILTER_PARA8_11N		0xA29
-+#define	ODM_REG_CCK_FA_RST_11N			0xA2C
-+#define	ODM_REG_CCK_FA_MSB_11N			0xA58
-+#define	ODM_REG_CCK_FA_LSB_11N			0xA5C
-+#define	ODM_REG_CCK_CCA_CNT_11N			0xA60
-+#define	ODM_REG_BB_PWR_SAV4_11N			0xA74
-+/* PAGE B */
-+#define	ODM_REG_LNA_SWITCH_11N			0xB2C
-+#define	ODM_REG_PATH_SWITCH_11N			0xB30
-+#define	ODM_REG_RSSI_CTRL_11N			0xB38
-+#define	ODM_REG_CONFIG_ANTA_11N			0xB68
-+#define	ODM_REG_RSSI_BT_11N			0xB9C
-+#define	ODM_REG_RXCK_RFMOD			0xBB0
-+#define	ODM_REG_EDCCA_DCNF_97F			0xBC0
-+
-+/* PAGE C */
-+#define	ODM_REG_OFDM_FA_HOLDC_11N		0xC00
-+#define	ODM_REG_BB_RX_PATH_11N			0xC04
-+#define	ODM_REG_TRMUX_11N			0xC08
-+#define	ODM_REG_OFDM_FA_RSTC_11N		0xC0C
-+#define	ODM_REG_DOWNSAM_FACTOR_11N		0xC10
-+#define	ODM_REG_RXIQI_MATRIX_11N		0xC14
-+#define	ODM_REG_TXIQK_MATRIX_LSB1_11N		0xC4C
-+#define	ODM_REG_IGI_A_11N			0xC50
-+#define	ODM_REG_ANTDIV_PARA2_11N		0xC54
-+#define	ODM_REG_IGI_B_11N			0xC58
-+#define	ODM_REG_ANTDIV_PARA3_11N		0xC5C
-+#define   ODM_REG_L1SBD_PD_CH_11N		0XC6C
-+#define	ODM_REG_BB_PWR_SAV2_11N			0xC70
-+#define	ODM_REG_BB_AGC_SET_2_11N		0xc74
-+#define	ODM_REG_RX_OFF_11N			0xC7C
-+#define	ODM_REG_TXIQK_MATRIXA_11N		0xC80
-+#define	ODM_REG_TXIQK_MATRIXB_11N		0xC88
-+#define	ODM_REG_TXIQK_MATRIXA_LSB2_11N		0xC94
-+#define	ODM_REG_TXIQK_MATRIXB_LSB2_11N		0xC9C
-+#define	ODM_REG_RXIQK_MATRIX_LSB_11N		0xCA0
-+#define	ODM_REG_ANTDIV_PARA1_11N		0xCA4
-+#define	ODM_REG_SMALL_BANDWIDTH_11N		0xCE4
-+#define	ODM_REG_OFDM_FA_TYPE1_11N		0xCF0
-+/* PAGE D */
-+#define	ODM_REG_OFDM_FA_RSTD_11N		0xD00
-+#define	ODM_REG_BB_RX_ANT_11N			0xD04
-+#define	ODM_REG_BB_ATC_11N			0xD2C
-+#define	ODM_REG_OFDM_FA_TYPE2_11N		0xDA0
-+#define	ODM_REG_OFDM_FA_TYPE3_11N		0xDA4
-+#define	ODM_REG_OFDM_FA_TYPE4_11N		0xDA8
-+#define	ODM_REG_RPT_11N				0xDF4
-+/* PAGE E */
-+#define	ODM_REG_TXAGC_A_6_18_11N		0xE00
-+#define	ODM_REG_TXAGC_A_24_54_11N		0xE04
-+#define	ODM_REG_TXAGC_A_1_MCS32_11N		0xE08
-+#define	ODM_REG_TXAGC_A_MCS0_3_11N		0xE10
-+#define	ODM_REG_TXAGC_A_MCS4_7_11N		0xE14
-+#define	ODM_REG_TXAGC_A_MCS8_11_11N		0xE18
-+#define	ODM_REG_TXAGC_A_MCS12_15_11N		0xE1C
-+#define	ODM_REG_EDCCA_DCNF_11N			0xE24
-+#define	ODM_REG_TAP_UPD_97F			0xE24
-+#define	ODM_REG_FPGA0_IQK_11N			0xE28
-+#define	ODM_REG_PAGE_B1_97F			0xE28
-+#define	ODM_REG_TXIQK_TONE_A_11N		0xE30
-+#define	ODM_REG_RXIQK_TONE_A_11N		0xE34
-+#define	ODM_REG_TXIQK_PI_A_11N			0xE38
-+#define	ODM_REG_RXIQK_PI_A_11N			0xE3C
-+#define	ODM_REG_TXIQK_11N			0xE40
-+#define	ODM_REG_RXIQK_11N			0xE44
-+#define	ODM_REG_IQK_AGC_PTS_11N			0xE48
-+#define	ODM_REG_IQK_AGC_RSP_11N			0xE4C
-+#define	ODM_REG_BLUETOOTH_11N			0xE6C
-+#define	ODM_REG_RX_WAIT_CCA_11N			0xE70
-+#define	ODM_REG_TX_CCK_RFON_11N			0xE74
-+#define	ODM_REG_TX_CCK_BBON_11N			0xE78
-+#define	ODM_REG_OFDM_RFON_11N			0xE7C
-+#define	ODM_REG_OFDM_BBON_11N			0xE80
-+#define	ODM_REG_TX2RX_11N			0xE84
-+#define	ODM_REG_TX2TX_11N			0xE88
-+#define	ODM_REG_RX_CCK_11N			0xE8C
-+#define	ODM_REG_RX_OFDM_11N			0xED0
-+#define	ODM_REG_RX_WAIT_RIFS_11N		0xED4
-+#define	ODM_REG_RX2RX_11N			0xED8
-+#define	ODM_REG_STANDBY_11N			0xEDC
-+#define	ODM_REG_SLEEP_11N			0xEE0
-+#define	ODM_REG_PMPD_ANAEN_11N			0xEEC
-+/* PAGE F */
-+#define	ODM_REG_PAGE_F_RST_11N			0xF14
-+#define	ODM_REG_IGI_C_11N			0xF84
-+#define	ODM_REG_IGI_D_11N			0xF88
-+#define	ODM_REG_CCK_CRC32_ERROR_CNT_11N		0xF84
-+#define	ODM_REG_CCK_CRC32_OK_CNT_11N		0xF88
-+#define	ODM_REG_HT_CRC32_CNT_11N		0xF90
-+#define	ODM_REG_OFDM_CRC32_CNT_11N		0xF94
-+#define	ODM_REG_HT_CRC32_CNT_11N_AGG		0xFB8
-+
-+/* @2 MAC REG LIST */
-+#define	ODM_REG_BB_RST_11N			0x02
-+#define	ODM_REG_ANTSEL_PIN_11N			0x4C
-+#define	ODM_REG_EARLY_MODE_11N			0x4D0
-+#define	ODM_REG_RSSI_MONITOR_11N		0x4FE
-+#define	ODM_REG_EDCA_VO_11N			0x500
-+#define	ODM_REG_EDCA_VI_11N			0x504
-+#define	ODM_REG_EDCA_BE_11N			0x508
-+#define	ODM_REG_EDCA_BK_11N			0x50C
-+#define	ODM_REG_TXPAUSE_11N			0x522
-+#define	ODM_REG_RESP_TX_11N			0x6D8
-+#define	ODM_REG_ANT_TRAIN_PARA1_11N		0x7b0
-+#define	ODM_REG_ANT_TRAIN_PARA2_11N		0x7b4
-+
-+
-+/* @DIG Related */
-+#define	ODM_BIT_IGI_11N				0x0000007F
-+#define	ODM_BIT_CCK_RPT_FORMAT_11N		BIT(9)
-+#define	ODM_BIT_BB_RX_PATH_11N			0xF
-+#define	ODM_BIT_BB_TX_PATH_11N			0xF
-+#define	ODM_BIT_BB_ATC_11N			BIT(11)
-+#endif
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_regtable.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_regtable.h
-new file mode 100644
-index 000000000000..8376d4adb73d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_regtable.h
-@@ -0,0 +1,1109 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ *
-+ *****************************************************************************/
-+
-+#define R_0x0 0x0
-+#define R_0x00 0x00
-+#define R_0x08 0x08
-+#define R_0x0106 0x0106
-+#define R_0x0140 0x0140
-+#define R_0x0144 0x0144
-+#define R_0x0148 0x0148
-+#define R_0x040 0x040
-+#define R_0x10 0x10
-+#define R_0x100 0x100
-+#define R_0x1008 0x1008
-+#define R_0x1038 0x1038
-+#define R_0x103c 0x103c
-+#define R_0x1040 0x1040
-+#define R_0x1048 0x1048
-+#define R_0x1080 0x1080
-+#define R_0x1208 0x1208
-+#define R_0x1210 0x1210
-+#define R_0x1214 0x1214
-+#define R_0x1218 0x1218
-+#define R_0x121c 0x121c
-+#define R_0x14 0x14
-+#define R_0x14c0 0x14c0
-+#define R_0x14c4 0x14c4
-+#define R_0x14c8 0x14c8
-+#define R_0x14cc 0x14cc
-+#define R_0x1518 0x1518
-+#define R_0x1684 0x1684
-+#define R_0x1688 0x1688
-+#define R_0x168c 0x168c
-+#define R_0x1700 0x1700
-+#define R_0x1704 0x1704
-+#define R_0x1800 0x1800
-+#define R_0x1804 0x1804
-+#define R_0x1808 0x1808
-+#define R_0x180c 0x180c
-+#define R_0x1810 0x1810
-+#define R_0x1814 0x1814
-+#define R_0x1818 0x1818
-+#define R_0x181c 0x181c
-+#define R_0x1830 0x1830
-+#define R_0x1834 0x1834
-+#define R_0x1838 0x1838
-+#define R_0x183c 0x183c
-+#define R_0x1840 0x1840
-+#define R_0x1844 0x1844
-+#define R_0x1848 0x1848
-+#define R_0x1860 0x1860
-+#define R_0x1864 0x1864
-+#define R_0x1868 0x1868
-+#define R_0x186c 0x186c
-+#define R_0x1870 0x1870
-+#define R_0x1880 0x1880
-+#define R_0x1884 0x1884
-+#define R_0x188c 0x188c
-+#define R_0x1894 0x1894
-+#define R_0x189c 0x189c
-+#define R_0x18a0 0x18a0
-+#define R_0x18a4 0x18a4
-+#define R_0x18a8 0x18a8
-+#define R_0x18ac 0x18ac
-+#define R_0x18e0 0x18e0
-+#define R_0x18e8 0x18e8
-+#define R_0x18ec 0x18ec
-+#define R_0x18f0 0x18f0
-+#define R_0x18f8 0x18f8
-+#define R_0x18fc 0x18fc
-+#define R_0x1900 0x1900
-+#define R_0x1904 0x1904
-+#define R_0x1908 0x1908
-+#define R_0x1910 0x1910
-+#define R_0x1918 0x1918
-+#define R_0x191c 0x191c
-+#define R_0x1928 0x1928
-+#define R_0x1938 0x1938
-+#define R_0x1940 0x1940
-+#define R_0x1944 0x1944
-+#define R_0x1950 0x1950
-+#define R_0x1954 0x1954
-+#define R_0x195c 0x195c
-+#define R_0x1970 0x1970
-+#define R_0x1984 0x1984
-+#define R_0x1988 0x1988
-+#define R_0x198c 0x198c
-+#define R_0x1990 0x1990
-+#define R_0x1991 0x1991
-+#define R_0x1998 0x1998
-+#define R_0x19a8 0x19a8
-+#define R_0x19b8 0x19b8
-+#define R_0x19d4 0x19d4
-+#define R_0x19d8 0x19d8
-+#define R_0x19e0 0x19e0
-+#define R_0x19f0 0x19f0
-+#define R_0x19f8 0x19f8
-+#define R_0x1a00 0x1a00
-+#define R_0x1a04 0x1a04
-+#define R_0x1a08 0x1a08
-+#define R_0x1a0c 0x1a0c
-+#define R_0x1a10 0x1a10
-+#define R_0x1a14 0x1a14
-+#define R_0x1a18 0x1a18
-+#define R_0x1a1c 0x1a1c
-+#define R_0x1a20 0x1a20
-+#define R_0x1a24 0x1a24
-+#define R_0x1a28 0x1a28
-+#define R_0x1a2c 0x1a2c
-+#define R_0x1a30 0x1a30
-+#define R_0x1a34 0x1a34
-+#define R_0x1a38 0x1a38
-+#define R_0x1a5c 0x1a5c
-+#define R_0x1a70 0x1a70
-+#define R_0x1a74 0x1a74
-+#define R_0x1a80 0x1a80
-+#define R_0x1a84 0x1a84
-+#define R_0x1a8c 0x1a8c
-+#define R_0x1a94 0x1a94
-+#define R_0x1a98 0x1a98
-+#define R_0x1a9c 0x1a9c
-+#define R_0x1aa0 0x1aa0
-+#define R_0x1aa8 0x1aa8
-+#define R_0x1aac 0x1aac
-+#define R_0x1ab0 0x1ab0
-+#define R_0x1abc 0x1abc
-+#define R_0x1ac0 0x1ac0
-+#define R_0x1ac8 0x1ac8
-+#define R_0x1acc 0x1acc
-+#define R_0x1ad0 0x1ad0
-+#define R_0x1ad4 0x1ad4
-+#define R_0x1ae0 0x1ae0
-+#define R_0x1ae8 0x1ae8
-+#define R_0x1aec 0x1aec
-+#define R_0x1b00 0x1b00
-+#define R_0x1b04 0x1b04
-+#define R_0x1b08 0x1b08
-+#define R_0x1b0c 0x1b0c
-+#define R_0x1b10 0x1b10
-+#define R_0x1b14 0x1b14
-+#define R_0x1b18 0x1b18
-+#define R_0x1b1c 0x1b1c
-+#define R_0x1b20 0x1b20
-+#define R_0x1b23 0x1b23
-+#define R_0x1b24 0x1b24
-+#define R_0x1b28 0x1b28
-+#define R_0x1b2c 0x1b2c
-+#define R_0x1b30 0x1b30
-+#define R_0x1b34 0x1b34
-+#define R_0x1b38 0x1b38
-+#define R_0x1b3c 0x1b3c
-+#define R_0x1b40 0x1b40
-+#define R_0x1b44 0x1b44
-+#define R_0x1b48 0x1b48
-+#define R_0x1b4c 0x1b4c
-+#define R_0x1b50 0x1b50
-+#define R_0x1b54 0x1b54
-+#define R_0x1b58 0x1b58
-+#define R_0x1b5c 0x1b5c
-+#define R_0x1b60 0x1b60
-+#define R_0x1b64 0x1b64
-+#define R_0x1b67 0x1b67
-+#define R_0x1b68 0x1b68
-+#define R_0x1b6c 0x1b6c
-+#define R_0x1b70 0x1b70
-+#define R_0x1b74 0x1b74
-+#define R_0x1b78 0x1b78
-+#define R_0x1b7c 0x1b7c
-+#define R_0x1b80 0x1b80
-+#define R_0x1b83 0x1b83
-+#define R_0x1b84 0x1b84
-+#define R_0x1b88 0x1b88
-+#define R_0x1b8c 0x1b8c
-+#define R_0x1b90 0x1b90
-+#define R_0x1b92 0x1b92
-+#define R_0x1b94 0x1b94
-+#define R_0x1b97 0x1b97
-+#define R_0x1b98 0x1b98
-+#define R_0x1b9c 0x1b9c
-+#define R_0x1ba0 0x1ba0
-+#define R_0x1ba4 0x1ba4
-+#define R_0x1ba8 0x1ba8
-+#define R_0x1bac 0x1bac
-+#define R_0x1bb0 0x1bb0
-+#define R_0x1bb4 0x1bb4
-+#define R_0x1bb8 0x1bb8
-+#define R_0x1bbc 0x1bbc
-+#define R_0x1bc0 0x1bc0
-+#define R_0x1bc8 0x1bc8
-+#define R_0x1bca 0x1bca
-+#define R_0x1bcb 0x1bcb
-+#define R_0x1bcc 0x1bcc
-+#define R_0x1bce 0x1bce
-+#define R_0x1bd0 0x1bd0
-+#define R_0x1bd4 0x1bd4
-+#define R_0x1bd6 0x1bd6
-+#define R_0x1bd8 0x1bd8
-+#define R_0x1bdc 0x1bdc
-+#define R_0x1be3 0x1be3
-+#define R_0x1be4 0x1be4
-+#define R_0x1be8 0x1be8
-+#define R_0x1beb 0x1beb
-+#define R_0x1bec 0x1bec
-+#define R_0x1bef 0x1bef
-+#define R_0x1bf0 0x1bf0
-+#define R_0x1bf4 0x1bf4
-+#define R_0x1bf8 0x1bf8
-+#define R_0x1bfc 0x1bfc
-+#define R_0x1c 0x1c
-+#define R_0x1c20 0x1c20
-+#define R_0x1c24 0x1c24
-+#define R_0x1c28 0x1c28
-+#define R_0x1c2c 0x1c2c
-+#define R_0x1c30 0x1c30
-+#define R_0x1c34 0x1c34
-+#define R_0x1c38 0x1c38
-+#define R_0x1c3c 0x1c3c
-+#define R_0x1c64 0x1c64
-+#define R_0x1c68 0x1c68
-+#define R_0x1c6c 0x1c6c
-+#define R_0x1c74 0x1c74
-+#define R_0x1c78 0x1c78
-+#define R_0x1c7c 0x1c7c
-+#define R_0x1c80 0x1c80
-+#define R_0x1c90 0x1c90
-+#define R_0x1c94 0x1c94
-+#define R_0x1c98 0x1c98
-+#define R_0x1c9c 0x1c9c
-+#define R_0x1ca0 0x1ca0
-+#define R_0x1ca4 0x1ca4
-+#define R_0x1cb0 0x1cb0
-+#define R_0x1cb8 0x1cb8
-+#define R_0x1cbc 0x1cbc
-+#define R_0x1cc0 0x1cc0
-+#define R_0x1cd0 0x1cd0
-+#define R_0x1cd8 0x1cd8
-+#define R_0x1ce4 0x1ce4
-+#define R_0x1ce8 0x1ce8
-+#define R_0x1cec 0x1cec
-+#define R_0x1cf0 0x1cf0
-+#define R_0x1cf4 0x1cf4
-+#define R_0x1cf8 0x1cf8
-+#define R_0x1d04 0x1d04
-+#define R_0x1d08 0x1d08
-+#define R_0x1d0c 0x1d0c
-+#define R_0x1d10 0x1d10
-+#define R_0x1d2c 0x1d2c
-+#define R_0x1d30 0x1d30
-+#define R_0x1d3c 0x1d3c
-+#define R_0x1d40 0x1d40
-+#define R_0x1d44 0x1d44
-+#define R_0x1d48 0x1d48
-+#define R_0x1d58 0x1d58
-+#define R_0x1d60 0x1d60
-+#define R_0x1d6c 0x1d6c
-+#define R_0x1d70 0x1d70
-+#define R_0x1d90 0x1d90
-+#define R_0x1d94 0x1d94
-+#define R_0x1d9c 0x1d9c
-+#define R_0x1da4 0x1da4
-+#define R_0x1da8 0x1da8
-+#define R_0x1de8 0x1de8
-+#define R_0x1e14 0x1e14
-+#define R_0x1e18 0x1e18
-+#define R_0x1e1c 0x1e1c
-+#define R_0x1e24 0x1e24
-+#define R_0x1e28 0x1e28
-+#define R_0x1e2c 0x1e2c
-+#define R_0x1e28 0x1e28
-+#define R_0x1e30 0x1e30
-+#define R_0x1e40 0x1e40
-+#define R_0x1e44 0x1e44
-+#define R_0x1e48 0x1e48
-+#define R_0x1e4c 0x1e4c
-+#define R_0x1e50 0x1e50
-+#define R_0x1e54 0x1e54
-+#define R_0x1e58 0x1e58
-+#define R_0x1e5c 0x1e5c
-+#define R_0x1e60 0x1e60
-+#define R_0x1e64 0x1e64
-+#define R_0x1e68 0x1e68
-+#define R_0x1e6c 0x1e6c
-+#define R_0x1e70 0x1e70
-+#define R_0x1e7c 0x1e7c
-+#define R_0x1e80 0x1e80
-+#define R_0x1e84 0x1e84
-+#define R_0x1e88 0x1e88
-+#define R_0x1e8c 0x1e8c
-+#define R_0x1ea4 0x1ea4
-+#define R_0x1eb4 0x1eb4
-+#define R_0x1eb8 0x1eb8
-+#define R_0x1ed4 0x1ed4
-+#define R_0x1ed8 0x1ed8
-+#define R_0x1edc 0x1edc
-+#define R_0x1ee0 0x1ee0
-+#define R_0x1ee4 0x1ee4
-+#define R_0x1ee8 0x1ee8
-+#define R_0x1eec 0x1eec
-+#define R_0x1ef0 0x1ef0
-+#define R_0x1ef4 0x1ef4
-+#define R_0x1ef8 0x1ef8
-+#define R_0x1efc 0x1efc
-+#define R_0x1f80 0x1f80
-+#define R_0x1f98 0x1f98
-+#define R_0x24 0x24
-+#define R_0x28 0x28
-+#define R_0x2a00 0x2a00
-+#define R_0x2a04 0x2a04
-+#define R_0x2a08 0x2a08
-+#define R_0x2a24 0x2a24
-+#define R_0x2a38 0x2a38
-+#define R_0x2a3c 0x2a3c
-+#define R_0x2a44 0x2a44
-+#define R_0x2aa0 0x2aa0
-+#define R_0x2aa8 0x2aa8
-+#define R_0x2aac 0x2aac
-+#define R_0x2ad0 0x2ad0
-+#define R_0x2c 0x2c
-+#define R_0x28a4 0x28a4
-+#define R_0x2c04 0x2c04
-+#define R_0x2c08 0x2c08
-+#define R_0x2c0c 0x2c0c
-+#define R_0x2c10 0x2c10
-+#define R_0x2c14 0x2c14
-+#define R_0x2c18 0x2c18
-+#define R_0x2c1c 0x2c1c
-+#define R_0x2c20 0x2c20
-+#define R_0x2c2c 0x2c2c
-+#define R_0x2c30 0x2c30
-+#define R_0x2c34 0x2c34
-+#define R_0x2c54 0x2c54
-+#define R_0x2d00 0x2d00
-+#define R_0x2d04 0x2d04
-+#define R_0x2d08 0x2d08
-+#define R_0x2d0c 0x2d0c
-+#define R_0x2d10 0x2d10
-+#define R_0x2d20 0x2d20
-+#define R_0x2d38 0x2d38
-+#define R_0x2d40 0x2d40
-+#define R_0x2d44 0x2d44
-+#define R_0x2d48 0x2d48
-+#define R_0x2d4c 0x2d4c
-+#define R_0x2d6c 0x2d6c
-+#define R_0x2d84 0x2d84
-+#define R_0x2d88 0x2d88
-+#define R_0x2d90 0x2d90
-+#define R_0x2d9c 0x2d9c
-+#define R_0x2db4 0x2db4
-+#define R_0x2db8 0x2db8
-+#define R_0x2dbc 0x2dbc
-+#define R_0x2de0 0x2de0
-+#define R_0x2de4 0x2de4
-+#define R_0x2de8 0x2de8
-+#define R_0x2e00 0x2e00
-+#define R_0x2e20 0x2e20
-+#define R_0x2e60 0x2e60
-+#define R_0x2e64 0x2e64
-+#define R_0x2e68 0x2e68
-+#define R_0x2e6c 0x2e6c
-+#define R_0x2e70 0x2e70
-+#define R_0x2e74 0x2e74
-+#define R_0x2e78 0x2e78
-+#define R_0x2e7c 0x2e7c
-+#define R_0x2e80 0x2e80
-+#define R_0x300 0x300
-+#define R_0x38 0x38
-+#define R_0x3a00 0x3a00
-+#define R_0x3a04 0x3a04
-+#define R_0x3a08 0x3a08
-+#define R_0x3a0c 0x3a0c
-+#define R_0x3a10 0x3a10
-+#define R_0x3a14 0x3a14
-+#define R_0x3a18 0x3a18
-+#define R_0x3a1c 0x3a1c
-+#define R_0x3a20 0x3a20
-+#define R_0x3a24 0x3a24
-+#define R_0x3a28 0x3a28
-+#define R_0x3a2c 0x3a2c
-+#define R_0x3a30 0x3a30
-+#define R_0x3a34 0x3a34
-+#define R_0x3a38 0x3a38
-+#define R_0x3a3c 0x3a3c
-+#define R_0x3a40 0x3a40
-+#define R_0x3a44 0x3a44
-+#define R_0x3a48 0x3a48
-+#define R_0x3a4c 0x3a4c
-+#define R_0x3a50 0x3a50               
-+#define R_0x3a54 0x3a54
-+#define R_0x3a58 0x3a58
-+#define R_0x3a5c 0x3a5c
-+#define R_0x3a60 0x3a60
-+#define R_0x3a64 0x3a64
-+#define R_0x3a68 0x3a68
-+#define R_0x3a6c 0x3a6c
-+#define R_0x3a70 0x3a70
-+#define R_0x3a74 0x3a74
-+#define R_0x3a78 0x3a78
-+#define R_0x3a7c 0x3a7c
-+#define R_0x3a80 0x3a80
-+#define R_0x3a84 0x3a84
-+#define R_0x3a88 0x3a88
-+#define R_0x3a8c 0x3a8c
-+#define R_0x3a90 0x3a90
-+#define R_0x3a94 0x3a94
-+#define R_0x3a98 0x3a98
-+#define R_0x3a9c 0x3a9c
-+#define R_0x3aa0 0x3aa0
-+#define R_0x3aa4 0x3aa4
-+#define R_0x3c00 0x3c00
-+#define R_0x40 0x40
-+#define R_0x4000 0x4000
-+#define R_0x4008 0x4008
-+#define R_0x4018 0x4018
-+#define R_0x401c 0x401c
-+#define R_0x4028 0x4028
-+#define R_0x4040 0x4040
-+#define R_0x4044 0x4044
-+#define R_0x4100 0x4100
-+#define R_0x4104 0x4104
-+#define R_0x4108 0x4108
-+#define R_0x410c 0x410c
-+#define R_0x4110 0x4110
-+#define R_0x4114 0x4114
-+#define R_0x4118 0x4118
-+#define R_0x411c 0x411c
-+#define R_0x4130 0x4130
-+#define R_0x4134 0x4134
-+#define R_0x4138 0x4138
-+#define R_0x413c 0x413c
-+#define R_0x4140 0x4140
-+#define R_0x4144 0x4144
-+#define R_0x4148 0x4148
-+#define R_0x4160 0x4160
-+#define R_0x4164 0x4164
-+#define R_0x4168 0x4168
-+#define R_0x416c 0x416c
-+#define R_0x4180 0x4180
-+#define R_0x419c 0x419c
-+#define R_0x41a0 0x41a0
-+#define R_0x41a4 0x41a4
-+#define R_0x41a8 0x41a8
-+#define R_0x41ac 0x41ac
-+#define R_0x41e0 0x41e0
-+#define R_0x41e8 0x41e8
-+#define R_0x41ec 0x41ec
-+#define R_0x41f0 0x41f0
-+#define R_0x41f8 0x41f8
-+#define R_0x41fc 0x41fc
-+#define R_0x42 0x42
-+#define R_0x430 0x430
-+#define R_0x434 0x434
-+#define R_0x42b0 0x42b0
-+#define R_0x42b4 0x42b4
-+#define R_0x4300 0x4300
-+#define R_0x4304 0x4304
-+#define R_0x4308 0x4308
-+#define R_0x430c 0x430c
-+#define R_0x4310 0x4310
-+#define R_0x4314 0x4314
-+#define R_0x4318 0x4318
-+#define R_0x431c 0x431c
-+#define R_0x4320 0x4320
-+#define R_0x4324 0x4324
-+#define R_0x4328 0x4328
-+#define R_0x432c 0x432c
-+#define R_0x4330 0x4330
-+#define R_0x4334 0x4334
-+#define R_0x4338 0x4338
-+#define R_0x433c 0x433c
-+#define R_0x4340 0x4340
-+#define R_0x4344 0x4344
-+#define R_0x4348 0x4348
-+#define R_0x434c 0x434c
-+#define R_0x4350 0x4350
-+#define R_0x4354 0x4354
-+#define R_0x4358 0x4358
-+#define R_0x435c 0x435c
-+#define R_0x4360 0x4360
-+#define R_0x4364 0x4364
-+#define R_0x4368 0x4368
-+#define R_0x436c 0x436c
-+#define R_0x4370 0x4370
-+#define R_0x4374 0x4374
-+#define R_0x4378 0x4378
-+#define R_0x437c 0x437c
-+#define R_0x4380 0x4380
-+#define R_0x4384 0x4384
-+#define R_0x4388 0x4388
-+#define R_0x438c 0x438c
-+#define R_0x4390 0x4390
-+#define R_0x4394 0x4394
-+#define R_0x4398 0x4398
-+#define R_0x439c 0x439c
-+#define R_0x43a0 0x43a0
-+#define R_0x43a4 0x43a4
-+#define R_0x43a8 0x43a8
-+#define R_0x43ac 0x43ac
-+#define R_0x43b0 0x43b0
-+#define R_0x43b4 0x43b4
-+#define R_0x43b8 0x43b8
-+#define R_0x44 0x44
-+#define R_0x440 0x440
-+#define R_0x444 0x444
-+#define R_0x448 0x448
-+#define R_0x450 0x450
-+#define R_0x454 0x454
-+#define R_0x494 0x494
-+#define R_0x498 0x498
-+#define R_0x49c 0x49c
-+#define R_0x4a0 0x4a0
-+#define R_0x4a4 0x4a4
-+#define R_0x4a8 0x4a8
-+#define R_0x4c 0x4c
-+#define R_0x4c8 0x4c8
-+#define R_0x4cc 0x4cc
-+#define R_0x45a4 0x45a4
-+#define R_0x4c00 0x4c00
-+#define R_0x5000 0x5000
-+#define R_0x5008 0x5008
-+#define R_0x5018 0x5018
-+#define R_0x501c 0x501c
-+#define R_0x5028 0x5028
-+#define R_0x5040 0x5040
-+#define R_0x5044 0x5044
-+#define R_0x5100 0x5100
-+#define R_0x5108 0x5108
-+#define R_0x5118 0x5118
-+#define R_0x511c 0x511c
-+#define R_0x5128 0x5128
-+#define R_0x5140 0x5140
-+#define R_0x5144 0x5144
-+#define R_0x520 0x520
-+#define R_0x5200 0x5200
-+#define R_0x520c 0x520c
-+#define R_0x522 0x522
-+#define R_0x524 0x524
-+#define R_0x5230 0x5230
-+#define R_0x5234 0x5234
-+#define R_0x5238 0x5238
-+#define R_0x523c 0x523c
-+#define R_0x5240 0x5240
-+#define R_0x5244 0x5244
-+#define R_0x5248 0x5248
-+#define R_0x526c 0x526c
-+#define R_0x5280 0x5280
-+#define R_0x52a0 0x52a0
-+#define R_0x52a4 0x52a4
-+#define R_0x52ac 0x52ac
-+#define R_0x52e8 0x52e8
-+#define R_0x5300 0x5300
-+#define R_0x530c 0x530c
-+#define R_0x5330 0x5330
-+#define R_0x5334 0x5334
-+#define R_0x5338 0x5338
-+#define R_0x533c 0x533c
-+#define R_0x5340 0x5340
-+#define R_0x5344 0x5344
-+#define R_0x5348 0x5348
-+#define R_0x536c 0x536c
-+#define R_0x5380 0x5380
-+#define R_0x53a0 0x53a0
-+#define R_0x53a4 0x53a4
-+#define R_0x53ac 0x53ac
-+#define R_0x53e8 0x53e8
-+#define R_0x550 0x550
-+#define R_0x551 0x551
-+#define R_0x568 0x568
-+#define R_0x588 0x588
-+#define R_0x60 0x60
-+#define R_0x604 0x604
-+#define R_0x608 0x608
-+#define R_0x60c 0x60c
-+#define R_0x60f 0x60f
-+#define R_0x64 0x64
-+#define R_0x66 0x66
-+#define R_0x660 0x660
-+#define R_0x668 0x668
-+#define R_0x688 0x688
-+#define R_0x6a0 0x6a0
-+#define R_0x6d8 0x6d8
-+#define R_0x6dc 0x6dc
-+#define R_0x6f8 0x6f8
-+#define R_0x70 0x70
-+#define R_0x74 0x74
-+#define R_0x700 0x700
-+#define R_0x71c 0x71c
-+#define R_0x72c 0x72c
-+#define R_0x764 0x764
-+#define R_0x7b0 0x7b0
-+#define R_0x7b4 0x7b4
-+#define R_0x7c0 0x7c0
-+#define R_0x7c4 0x7c4
-+#define R_0x7c8 0x7c8
-+#define R_0x7cc 0x7cc
-+#define R_0x7f0 0x7f0
-+#define R_0x7f4 0x7f4
-+#define R_0x7f8 0x7f8
-+#define R_0x7fc 0x7fc
-+#define R_0x800 0x800
-+#define R_0x8000 0x8000
-+#define R_0x804 0x804
-+#define R_0x808 0x808
-+#define R_0x80c 0x80c
-+#define R_0x810 0x810
-+#define R_0x814 0x814
-+#define R_0x818 0x818
-+#define R_0x81c 0x81c
-+#define R_0x820 0x820
-+#define R_0x824 0x824
-+#define R_0x828 0x828
-+#define R_0x82c 0x82c
-+#define R_0x830 0x830
-+#define R_0x834 0x834
-+#define R_0x838 0x838
-+#define R_0x83c 0x83c
-+#define R_0x840 0x840
-+#define R_0x844 0x840
-+#define R_0x848 0x848
-+#define R_0x84c 0x84c
-+#define R_0x850 0x850
-+#define R_0x854 0x854
-+#define R_0x858 0x858
-+#define R_0x85c 0x85c
-+#define R_0x860 0x860
-+#define R_0x864 0x864
-+#define R_0x868 0x868
-+#define R_0x86c 0x86c
-+#define R_0x870 0x870
-+#define R_0x874 0x874
-+#define R_0x878 0x878
-+#define R_0x87c 0x87c
-+#define R_0x880 0x880
-+#define R_0x884 0x884
-+#define R_0x888 0x888
-+#define R_0x88c 0x88c
-+#define R_0x890 0x890
-+#define R_0x894 0x894
-+#define R_0x898 0x898
-+#define R_0x89c 0x89c
-+#define R_0x8a0 0x8a0
-+#define R_0x8a4 0x8a4
-+#define R_0x8ac 0x8ac
-+#define R_0x8b4 0x8b4
-+#define R_0x8b8 0x8b8
-+#define R_0x8c0 0x8c0
-+#define R_0x8c4 0x8c4
-+#define R_0x8c8 0x8c8
-+#define R_0x8cc 0x8cc
-+#define R_0x8d0 0x8d0
-+#define R_0x8d4 0x8d4
-+#define R_0x8d8 0x8d8
-+#define R_0x8dc 0x8dc
-+#define R_0x8f0 0x8f0
-+#define R_0x8f8 0x8f8
-+#define R_0x8fc 0x8fc
-+#define R_0x900 0x900
-+#define R_0x908 0x908
-+#define R_0x90c 0x90c
-+#define R_0x910 0x910
-+#define R_0x914 0x914
-+#define R_0x918 0x918
-+#define R_0x91c 0x91c
-+#define R_0x920 0x920
-+#define R_0x924 0x924
-+#define R_0x92c 0x92c
-+#define R_0x930 0x930
-+#define R_0x934 0x934
-+#define R_0x938 0x938
-+#define R_0x93c 0x93c
-+#define R_0x940 0x940
-+#define R_0x944 0x944
-+#define R_0x948 0x948
-+#define R_0x94c 0x94c
-+#define R_0x950 0x950
-+#define R_0x954 0x954
-+#define R_0x958 0x958
-+#define R_0x95c 0x95c
-+#define R_0x960 0x960
-+#define R_0x964 0x964
-+#define R_0x968 0x968
-+#define R_0x970 0x970
-+#define R_0x974 0x974
-+#define R_0x978 0x978
-+#define R_0x97c 0x97c
-+#define R_0x980 0x980
-+#define R_0x988 0x988
-+#define R_0x98c 0x98c
-+#define R_0x990 0x990
-+#define R_0x994 0x994
-+#define R_0x998 0x998
-+#define R_0x99c 0x99c
-+#define R_0x9a0 0x9a0
-+#define R_0x9a4 0x9a4
-+#define R_0x9ac 0x9ac
-+#define R_0x9b0 0x9b0
-+#define R_0x9b4 0x9b4
-+#define R_0x9b8 0x9b8
-+#define R_0x9cc 0x9cc
-+#define R_0x9d0 0x9d0
-+#define R_0x9d8 0x9d8
-+#define R_0x9e4 0x9e4
-+#define R_0x9e8 0x9e8
-+#define R_0x9f0 0x9f0
-+#define R_0xa0 0xa0
-+#define R_0xa00 0xa00
-+#define R_0xa04 0xa04
-+#define R_0xa08 0xa08
-+#define R_0xa0a 0xa0a
-+#define R_0xa0c 0xa0c
-+#define R_0xa10 0xa10
-+#define R_0xa14 0xa14
-+#define R_0xa20 0xa20
-+#define R_0xa24 0xa24
-+#define R_0xa28 0xa28
-+#define R_0xa2c 0xa2c
-+#define R_0xa40 0xa40
-+#define R_0xa44 0xa44
-+#define R_0xa48 0xa48
-+#define R_0xa4c 0xa4c
-+#define R_0xa50 0xa50
-+#define R_0xa54 0xa54
-+#define R_0xa58 0xa58
-+#define R_0xa68 0xa68
-+#define R_0xa6c 0xa6c
-+#define R_0xa70 0xa70
-+#define R_0xa74 0xa74
-+#define R_0xa78 0xa78
-+#define R_0xa8 0xa8
-+#define R_0xa80 0xa80
-+#define R_0xa84 0xa84
-+#define R_0xa98 0xa98
-+#define R_0xa9c 0xa9c
-+#define R_0xaa8 0xaa8
-+#define R_0xaac 0xaac
-+#define R_0xab4 0xab4
-+#define R_0xabc 0xabc
-+#define R_0xac 0xac
-+#define R_0xac8 0xac8
-+#define R_0xacc 0xacc
-+#define R_0xad0 0xad0
-+#define R_0xb0 0xb0
-+#define R_0xb00 0xb00
-+#define R_0xb04 0xb04
-+#define R_0xb07 0xb07
-+#define R_0xb08 0xb08
-+#define R_0xb0c 0xb0c
-+#define R_0xb10 0xb10
-+#define R_0xb14 0xb14
-+#define R_0xb18 0xb18
-+#define R_0xb1c 0xb1c
-+#define R_0xb20 0xb20
-+#define R_0xb24 0xb24
-+#define R_0xb28 0xb28
-+#define R_0xb2a 0xb2a
-+#define R_0xb2b 0xb2b
-+#define R_0xb2c 0xb2c
-+#define R_0xb30 0xb30
-+#define R_0xb34 0xb34
-+#define R_0xb38 0xb38
-+#define R_0xb3b 0xb3b
-+#define R_0xb3c 0xb3c
-+#define R_0xb40 0xb40
-+#define R_0xb44 0xb44
-+#define R_0xb48 0xb48
-+#define R_0xb54 0xb54
-+#define R_0xb58 0xb58
-+#define R_0xb60 0xb60
-+#define R_0xb64 0xb64
-+#define R_0xb68 0xb68
-+#define R_0xb6a 0xb6a
-+#define R_0xb6b 0xb6b
-+#define R_0xb6c 0xb6c
-+#define R_0xb6e 0xb6e
-+#define R_0xb70 0xb70
-+#define R_0xb74 0xb74
-+#define R_0xb77 0xb77
-+#define R_0xb78 0xb78
-+#define R_0xb7c 0xb7c
-+#define R_0xb80 0xb80
-+#define R_0xb84 0xb84
-+#define R_0xb88 0xb88
-+#define R_0xb8c 0xb8c
-+#define R_0xb90 0xb90
-+#define R_0xb94 0xb94
-+#define R_0xb98 0xb98
-+#define R_0xb9b 0xb9b
-+#define R_0xb9c 0xb9c
-+#define R_0xba0 0xba0
-+#define R_0xba4 0xba4
-+#define R_0xba8 0xba8
-+#define R_0xbac 0xbac
-+#define R_0xbad 0xbad
-+#define R_0xbc0 0xbc0
-+#define R_0xbc4 0xbc4
-+#define R_0xbc8 0xbc8
-+#define R_0xbcc 0xbcc
-+#define R_0xbd8 0xbd8
-+#define R_0xbdc 0xbdc
-+#define R_0xbe0 0xbe0
-+#define R_0xbe4 0xbe4
-+#define R_0xbe8 0xbe8
-+#define R_0xbec 0xbec
-+#define R_0xbf0 0xbf0
-+#define R_0xbf4 0xbf4
-+#define R_0xbf8 0xbf8
-+#define R_0xc00 0xc00
-+#define R_0xc04 0xc04
-+#define R_0xc08 0xc08
-+#define R_0xc0c 0xc0c
-+#define R_0xc10 0xc10
-+#define R_0xc14 0xc14
-+#define R_0xc18 0xc18
-+#define R_0xc1c 0xc1c
-+#define R_0xc20 0xc20
-+#define R_0xc24 0xc24
-+#define R_0xc2c 0xc2c
-+#define R_0xc30 0xc30
-+#define R_0xc34 0xc34
-+#define R_0xc38 0xc38
-+#define R_0xc3c 0xc3c
-+#define R_0xc40 0xc40
-+#define R_0xc44 0xc44
-+#define R_0xc4c 0xc4c
-+#define R_0xc50 0xc50
-+#define R_0xc54 0xc54
-+#define R_0xc58 0xc58
-+#define R_0xc5c 0xc5c
-+#define R_0xc6c 0xc6c
-+#define R_0xc70 0xc70
-+#define R_0xc74 0xc74
-+#define R_0xc78 0xc78
-+#define R_0xc7c 0xc7c
-+#define R_0xc80 0xc80
-+#define R_0xc84 0xc84
-+#define R_0xc88 0xc88
-+#define R_0xc8c 0xc8c
-+#define R_0xc90 0xc90
-+#define R_0xc94 0xc94
-+#define R_0xc9c 0xc9c
-+#define R_0xca0 0xca0
-+#define R_0xca4 0xca4
-+#define R_0xca8 0xca8
-+#define R_0xcac 0xcac
-+#define R_0xcb0 0xcb0
-+#define R_0xcb4 0xcb4
-+#define R_0xcb8 0xcb8
-+#define R_0xcbc 0xcbc
-+#define R_0xcbd 0xcbd
-+#define R_0xcbe 0xcbe
-+#define R_0xcc0 0xcc0
-+#define R_0xcc4 0xcc4
-+#define R_0xcc8 0xcc8
-+#define R_0xccc 0xccc
-+#define R_0xcd0 0xcd0
-+#define R_0xcd4 0xcd4
-+#define R_0xcd8 0xcd8
-+#define R_0xce0 0xce0
-+#define R_0xce4 0xce4
-+#define R_0xce8 0xce8
-+#define R_0xd00 0xd00
-+#define R_0xd04 0xd04
-+#define R_0xd08 0xd08
-+#define R_0xd0c 0xd0c
-+#define R_0xd10 0xd10
-+#define R_0xd14 0xd14
-+#define R_0xd2c 0xd2c
-+#define R_0xd30 0xd30
-+#define R_0xd40 0xd40
-+#define R_0xd44 0xd44
-+#define R_0xd48 0xd48
-+#define R_0xd4c 0xd4c
-+#define R_0xd50 0xd50
-+#define R_0xd54 0xd54
-+#define R_0xd5c 0xd5c
-+#define R_0xd6c 0xd6c
-+#define R_0xd7c 0xd7c
-+#define R_0xd80 0xd80
-+#define R_0xd84 0xd84
-+#define R_0xd8c 0xd8c
-+#define R_0xd90 0xd90
-+#define R_0xd94 0xd94
-+#define R_0xdac 0xdac
-+#define R_0xdb0 0xdb0
-+#define R_0xdb4 0xdb4
-+#define R_0xdb8 0xdb8
-+#define R_0xdbc 0xdbc
-+#define R_0xdc 0xdc
-+#define R_0xdcc 0xdcc
-+#define R_0xdd0 0xdd0
-+#define R_0xdd4 0xdd4
-+#define R_0xdd8 0xdd8
-+#define R_0xde0 0xde0
-+#define R_0xdec 0xdec
-+#define R_0xdf4 0xdf4
-+#define R_0xe00 0xe00
-+#define R_0xe04 0xe04
-+#define R_0xe08 0xe08
-+#define R_0xe10 0xe10
-+#define R_0xe14 0xe14
-+#define R_0xe18 0xe18
-+#define R_0xe1c 0xe1c
-+#define R_0xe20 0xe20
-+#define R_0xe24 0xe24
-+#define R_0xe28 0xe28
-+#define R_0xe30 0xe30
-+#define R_0xe34 0xe34
-+#define R_0xe38 0xe38
-+#define R_0xe3c 0xe3c
-+#define R_0xe40 0xe40
-+#define R_0xe44 0xe44
-+#define R_0xe48 0xe48
-+#define R_0xe4c 0xe4c
-+#define R_0xe50 0xe50
-+#define R_0xe54 0xe54
-+#define R_0xe5c 0xe5c
-+#define R_0xe64 0xe64
-+#define R_0xe6c 0xe6c
-+#define R_0xe70 0xe70
-+#define R_0xe74 0xe74
-+#define R_0xe78 0xe78
-+#define R_0xe7c 0xe7c
-+#define R_0xe80 0xe80
-+#define R_0xe84 0xe84
-+#define R_0xe88 0xe88
-+#define R_0xe8c 0xe8c
-+#define R_0xe90 0xe90
-+#define R_0xe94 0xe94
-+#define R_0xe98 0xe98
-+#define R_0xe9c 0xe9c
-+#define R_0xea0 0xea0
-+#define R_0xea4 0xea4
-+#define R_0xea8 0xea8
-+#define R_0xeac 0xeac
-+#define R_0xeb0 0xeb0
-+#define R_0xeb4 0xeb4
-+#define R_0xeb8 0xeb8
-+#define R_0xebc 0xebc
-+#define R_0xec 0xec
-+#define R_0xec0 0xec0
-+#define R_0xec4 0xec4
-+#define R_0xec8 0xec8
-+#define R_0xecc 0xecc
-+#define R_0xed0 0xed0
-+#define R_0xed4 0xed4
-+#define R_0xed8 0xed8
-+#define R_0xedc 0xedc
-+#define R_0xee0 0xee0
-+#define R_0xee8 0xee8
-+#define R_0xeec 0xeec
-+#define R_0xf0 0xf0
-+#define R_0xf00 0xf00
-+#define R_0xf04 0xf04
-+#define R_0xf08 0xf08
-+#define R_0xf0c 0xf0c
-+#define R_0xf10 0xf10
-+#define R_0xf14 0xf14
-+#define R_0xf18 0xf18
-+#define R_0xf1c 0xf1c
-+#define R_0xf20 0xf20
-+#define R_0xf24 0xf24
-+#define R_0xf2c 0xf2c
-+#define R_0xf30 0xf30
-+#define R_0xf34 0xf34
-+#define R_0xf4 0xf4
-+#define R_0xf44 0xf44
-+#define R_0xf48 0xf48
-+#define R_0xf4c 0xf4c
-+#define R_0xf50 0xf50
-+#define R_0xf54 0xf54
-+#define R_0xf58 0xf58
-+#define R_0xf5c 0xf5c
-+#define R_0xf70 0xf70
-+#define R_0xf74 0xf74
-+#define R_0xf80 0xf80
-+#define R_0xf84 0xf84
-+#define R_0xf87 0xf87
-+#define R_0xf88 0xf88
-+#define R_0xf8c 0xf8c
-+#define R_0xf90 0xf90
-+#define R_0xf94 0xf94
-+#define R_0xf98 0xf98
-+#define R_0xf9c 0xf9c
-+#define R_0xfa0 0xfa0
-+#define R_0xfa4 0xfa4
-+#define R_0xfa8 0xfa8
-+#define R_0xfac 0xfac
-+#define R_0xfb0 0xfb0
-+#define R_0xfb4 0xfb4
-+#define R_0xfb8 0xfb8
-+#define R_0xfbc 0xfbc
-+#define R_0xfc0 0xfc0
-+#define R_0xfc4 0xfc4
-+#define R_0xfc8 0xfc8
-+#define R_0xfcc 0xfcc
-+#define R_0xfd0 0xfd0
-+#define R_0xff0 0xff0
-+#define RF_0x0 0x0
-+#define RF_0x00 0x00
-+#define RF_0x08 0x08
-+#define RF_0x09 0x09
-+#define RF_0x0c 0x0c
-+#define RF_0x0d 0x0d
-+#define RF_0x1 0x1
-+#define RF_0x18 0x18
-+#define RF_0x19 0x19
-+#define RF_0x1a 0x1a
-+#define RF_0x1bf0 0x1bf0
-+#define RF_0x2 0x2
-+#define RF_0x3 0x3
-+#define RF_0x1e 0x1e
-+#define RF_0x1f 0x1f
-+#define RF_0x20 0x20
-+#define RF_0x30 0x30
-+#define RF_0x31 0x31
-+#define RF_0x32 0x32
-+#define RF_0x33 0x33
-+#define RF_0x35 0x35
-+#define RF_0x3e 0x3e
-+#define RF_0x3f 0x3f
-+#define RF_0x4 0x4
-+#define RF_0x42 0x42
-+#define RF_0x43 0x43
-+#define RF_0x5 0x5
-+#define RF_0x51 0x51
-+#define RF_0x52 0x52
-+#define RF_0x53 0x53
-+#define RF_0x54 0x54
-+#define RF_0x55 0x55
-+#define RF_0x56 0x56
-+#define RF_0x57 0x57
-+#define RF_0x58 0x58
-+#define RF_0x5c 0x5c
-+#define RF_0x5d 0x5d
-+#define RF_0x60 0x60
-+#define RF_0x61 0x61
-+#define RF_0x63 0x63
-+#define RF_0x64 0x64
-+#define RF_0x65 0x65
-+#define RF_0x66 0x66
-+#define RF_0x67 0x67
-+#define RF_0x6d 0x6d
-+#define RF_0x6e 0x6e
-+#define RF_0x6f 0x6f
-+#define RF_0x75 0x75
-+#define RF_0x76 0x76
-+#define RF_0x78 0x78
-+#define RF_0x7c 0x7c
-+#define RF_0x7f 0x7f
-+#define RF_0x8 0x8
-+#define RF_0x80 0x80
-+#define RF_0x81 0x81
-+#define RF_0x82 0x82
-+#define RF_0x83 0x83
-+#define RF_0x85 0x85
-+#define RF_0x86 0x86
-+#define RF_0x87 0x87
-+#define RF_0x8a 0x8a
-+#define RF_0x8b 0x8b
-+#define RF_0x8c 0x8c
-+#define RF_0x8d 0x8d
-+#define RF_0x8f 0x8f
-+#define RF_0x93 0x93
-+#define RF_0x9e 0x9e
-+#define RF_0x9f 0x9f
-+#define RF_0xa3 0xa3
-+#define RF_0xa9 0xa9
-+#define RF_0xae 0xae
-+#define RF_0xb0 0xb0
-+#define RF_0xb3 0xb3
-+#define RF_0xb4 0xb4
-+#define RF_0xb8 0xb8
-+#define RF_0xbc 0xbc
-+#define RF_0xbe 0xbe
-+#define RF_0xc4 0xc4
-+#define RF_0xc8 0xc8
-+#define RF_0xc9 0xc9
-+#define RF_0xca 0xca
-+#define RF_0xcc 0xcc
-+#define RF_0xd 0xd
-+#define RF_0xdd 0xdd
-+#define RF_0xde 0xde
-+#define RF_0xdf 0xdf
-+#define RF_0xed 0xed
-+#define RF_0xee 0xee
-+#define RF_0xef 0xef
-+#define RF_0xf5 0xf5
-+#define RF_0xf6 0xf6
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_rssi_monitor.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_rssi_monitor.c
-new file mode 100644
-index 000000000000..1fde03691a1a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_rssi_monitor.c
-@@ -0,0 +1,189 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*@************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef PHYDM_SUPPORT_RSSI_MONITOR
-+
-+void phydm_rssi_monitor_h2c(void *dm_void, u8 macid)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_t = &dm->dm_ra_table;
-+	struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
-+	struct ra_sta_info *ra = NULL;
-+	#ifdef CONFIG_BEAMFORMING
-+	struct bf_cmn_info *bf = NULL;
-+	#endif
-+	u8 h2c[H2C_MAX_LENGTH] = {0};
-+	u8 stbc_en, ldpc_en;
-+	u8 bf_en = 0;
-+	u8 is_rx, is_tx;
-+
-+	if (is_sta_active(sta)) {
-+		ra = &sta->ra_info;
-+	} else {
-+		PHYDM_DBG(dm, DBG_RSSI_MNTR, "[Warning] %s\n", __func__);
-+		return;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
-+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "MACID=%d\n", sta->mac_id);
-+
-+	is_rx = (ra->txrx_state == RX_STATE) ? 1 : 0;
-+	is_tx = (ra->txrx_state == TX_STATE) ? 1 : 0;
-+	stbc_en = (sta->stbc_en) ? 1 : 0;
-+	ldpc_en = (sta->ldpc_en) ? 1 : 0;
-+
-+	#ifdef CONFIG_BEAMFORMING
-+	bf = &sta->bf_info;
-+
-+	if ((bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE) ||
-+	    (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE))
-+		bf_en = 1;
-+	#endif
-+
-+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "RA_th_ofst=(( %s%d ))\n",
-+		  ((ra_t->ra_ofst_direc) ? "+" : "-"), ra_t->ra_th_ofst);
-+
-+	h2c[0] = sta->mac_id;
-+	h2c[1] = 0;
-+	h2c[2] = sta->rssi_stat.rssi;
-+	h2c[3] = is_rx | (stbc_en << 1) |
-+		     ((dm->noisy_decision & 0x1) << 2) | (bf_en << 6);
-+	h2c[4] = (ra_t->ra_th_ofst & 0x7f) |
-+		     ((ra_t->ra_ofst_direc & 0x1) << 7);
-+	h2c[5] = 0;
-+	h2c[6] = ((ra_t->ra_trigger_mode) << 2);
-+
-+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "PHYDM h2c[0x42]=0x%x %x %x %x %x %x %x\n",
-+		  h2c[6], h2c[5], h2c[4], h2c[3], h2c[2], h2c[1], h2c[0]);
-+
-+	#if (RTL8188E_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8188E)
-+		odm_ra_set_rssi_8188e(dm, sta->mac_id, sta->rssi_stat.rssi);
-+	else
-+	#endif
-+	{
-+		odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, H2C_MAX_LENGTH, h2c);
-+	}
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+void phydm_sta_rssi_init(void *dm_void, u8 macid, u8 init_rssi)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta = NULL;
-+	struct rssi_info *rssi_t = NULL;
-+
-+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
-+
-+	sta = dm->phydm_sta_info[macid];
-+	rssi_t = &sta->rssi_stat;
-+
-+	rssi_t->rssi_acc = (init_rssi << RSSI_MA);
-+	rssi_t->rssi = init_rssi;
-+}
-+#endif
-+void phydm_calculate_rssi_min_max(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct cmn_sta_info *sta;
-+	s8 rssi_max_tmp = 0, rssi_min_tmp = 100;
-+	u8 i;
-+	u8 sta_cnt = 0;
-+
-+	if (!dm->is_linked)
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
-+
-+	for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
-+		sta = dm->phydm_sta_info[i];
-+		if (is_sta_active(sta)) {
-+			sta_cnt++;
-+
-+			if (sta->rssi_stat.rssi < rssi_min_tmp) {
-+				rssi_min_tmp = sta->rssi_stat.rssi;
-+				dm->rssi_min_macid = i;
-+			}
-+
-+			if (sta->rssi_stat.rssi > rssi_max_tmp) {
-+				rssi_max_tmp = sta->rssi_stat.rssi;
-+				dm->rssi_max_macid = i;
-+			}
-+
-+			/*@[Send RSSI to FW]*/
-+			if (!sta->ra_info.disable_ra)
-+				phydm_rssi_monitor_h2c(dm, i);
-+
-+			if (sta_cnt == dm->number_linked_client)
-+				break;
-+		}
-+	}
-+	dm->pre_rssi_min = dm->rssi_min;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	if (dm->number_linked_client == 0)
-+		return;
-+#endif
-+	dm->rssi_max = (u8)rssi_max_tmp;
-+	dm->rssi_min = (u8)rssi_min_tmp;
-+}
-+
-+void phydm_rssi_monitor_check(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ability & ODM_BB_RSSI_MONITOR))
-+		return;
-+
-+	/*@for AP watchdog period = 1 sec*/
-+	if ((dm->phydm_sys_up_time % 2) == 1)
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
-+
-+	phydm_calculate_rssi_min_max(dm);
-+
-+	PHYDM_DBG(dm, DBG_RSSI_MNTR, "RSSI {max, min} = {%d, %d}\n",
-+		  dm->rssi_max, dm->rssi_min);
-+}
-+
-+void phydm_rssi_monitor_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+
-+	dm->pre_rssi_min = 0;
-+	dm->rssi_max = 0;
-+	dm->rssi_min = 0;
-+}
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_rssi_monitor.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_rssi_monitor.h
-new file mode 100644
-index 000000000000..b0f446ea292a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_rssi_monitor.h
-@@ -0,0 +1,58 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDM_RSSI_MONITOR_H__
-+#define __PHYDM_RSSI_MONITOR_H__
-+
-+#define RSSI_MONITOR_VERSION "2.0"
-+
-+/* @1 ============================================================
-+ * 1  Definition
-+ * 1 ============================================================
-+ */
-+
-+/* @1 ============================================================
-+ * 1  structure
-+ * 1 ============================================================
-+ */
-+
-+/* @1 ============================================================
-+ * 1  enumeration
-+ * 1 ============================================================
-+ */
-+
-+/* @1 ============================================================
-+ * 1  function prototype
-+ * 1 ============================================================
-+ */
-+
-+void phydm_rssi_monitor_check(void *dm_void);
-+
-+void phydm_rssi_monitor_init(void *dm_void);
-+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+void phydm_sta_rssi_init(void *dm_void, u8 macid, u8 init_rssi);
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_smt_ant.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_smt_ant.c
-new file mode 100644
-index 000000000000..8e805b3ce2d0
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_smt_ant.c
-@@ -0,0 +1,2277 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/* ************************************************************
-+ * include files
-+ * ************************************************************ */
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+/*******************************************************
-+ * when antenna test utility is on or some testing need to disable antenna diversity
-+ * call this function to disable all ODM related mechanisms which will switch antenna.
-+ ******************************************************/
-+#if (defined(CONFIG_SMART_ANTENNA))
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+#if (RTL8198F_SUPPORT == 1)
-+void phydm_smt_ant_init_98f(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 val = 0;
-+
-+	#if 0
-+	odm_set_bb_reg(dm, R_0x1da4, 0x3c, 4); /*6.25*4 = 25ms*/
-+	odm_set_bb_reg(dm, R_0x1da4, BIT(6), 1);
-+	odm_set_bb_reg(dm, R_0x1da4, BIT(7), 1);
-+	#endif
-+}
-+#endif
-+#endif
-+
-+#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
-+void phydm_cumitek_smt_ant_mapping_table_8822b(
-+	void *dm_void,
-+	u8 *table_path_a,
-+	u8 *table_path_b)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 path_a_0to3_idx = 0;
-+	u32 path_b_0to3_idx = 0;
-+	u32 path_a_4to7_idx = 0;
-+	u32 path_b_4to7_idx = 0;
-+
-+	path_a_0to3_idx = ((table_path_a[3] & 0xf) << 24) | ((table_path_a[2] & 0xf) << 16) | ((table_path_a[1] & 0xf) << 8) | (table_path_a[0] & 0xf);
-+
-+	path_b_0to3_idx = ((table_path_b[3] & 0xf) << 28) | ((table_path_b[2] & 0xf) << 20) | ((table_path_b[1] & 0xf) << 12) | ((table_path_b[0] & 0xf) << 4);
-+
-+	path_a_4to7_idx = ((table_path_a[7] & 0xf) << 24) | ((table_path_a[6] & 0xf) << 16) | ((table_path_a[5] & 0xf) << 8) | (table_path_a[4] & 0xf);
-+
-+	path_b_4to7_idx = ((table_path_b[7] & 0xf) << 28) | ((table_path_b[6] & 0xf) << 20) | ((table_path_b[5] & 0xf) << 12) | ((table_path_b[4] & 0xf) << 4);
-+
-+#if 0
-+	/*PHYDM_DBG(dm, DBG_SMT_ANT, "mapping table{A, B} = {0x%x, 0x%x}\n", path_a_0to3_idx, path_b_0to3_idx);*/
-+#endif
-+
-+	/*pathA*/
-+	odm_set_bb_reg(dm, R_0xca4, MASKDWORD, path_a_0to3_idx); /*@ant map 1*/
-+	odm_set_bb_reg(dm, R_0xca8, MASKDWORD, path_a_4to7_idx); /*@ant map 2*/
-+
-+	/*pathB*/
-+	odm_set_bb_reg(dm, R_0xea4, MASKDWORD, path_b_0to3_idx); /*@ant map 1*/
-+	odm_set_bb_reg(dm, R_0xea8, MASKDWORD, path_b_4to7_idx); /*@ant map 2*/
-+}
-+
-+void phydm_cumitek_smt_ant_init_8822b(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant *smtant_table = &dm->smtant_table;
-+	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
-+	u32 value32;
-+
-+	PHYDM_DBG(dm, DBG_SMT_ANT, "[8822B Cumitek SmtAnt Int]\n");
-+
-+	/*@========= MAC GPIO setting =================================*/
-+
-+	/* Pin, pin_name, RFE_CTRL_NUM*/
-+
-+	/* @A0, 55, 5G_TRSW, 3*/
-+	/* @A1, 52, 5G_TRSW, 0*/
-+	/* @A2, 25, 5G_TRSW, 8*/
-+
-+	/* @B0, 16, 5G_TRSW, 4*/
-+	/* @B1, 13, 5G_TRSW, 11*/
-+	/* @B2, 24, 5G_TRSW, 9*/
-+
-+	/*@for RFE_CTRL 8 & 9*/
-+	odm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2);
-+	odm_set_mac_reg(dm, R_0x44, BIT(27) | BIT(26), 0);
-+
-+	/*@for RFE_CTRL 0*/
-+	odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
-+	odm_set_mac_reg(dm, R_0x64, BIT(29), 1);
-+
-+	/*@for RFE_CTRL 2 & 3*/
-+	odm_set_mac_reg(dm, R_0x4c, BIT(26), 0);
-+	odm_set_mac_reg(dm, R_0x64, BIT(28), 1);
-+
-+	/*@for RFE_CTRL 11*/
-+	odm_set_mac_reg(dm, R_0x40, BIT(3), 1);
-+
-+	/*@0x604[25]=1 : 2bit mode for pathA&B&C&D*/
-+	/*@0x604[25]=0 : 3bit mode for pathA&B*/
-+	smtant_table->tx_desc_mode = 0;
-+	odm_set_mac_reg(dm, R_0x604, BIT(25), (u32)smtant_table->tx_desc_mode);
-+
-+	/*@========= BB RFE setting =================================*/
-+#if 0
-+	/*path A*/
-+	odm_set_bb_reg(dm, R_0x1990, BIT(3), 0);		/*RFE_CTRL_3*/ /*A_0*/
-+	odm_set_bb_reg(dm, R_0xcbc, BIT(3), 0);		/*@inv*/
-+	odm_set_bb_reg(dm, R_0xcb0, 0xf000, 8);
-+
-+	odm_set_bb_reg(dm, R_0x1990, BIT(0), 0);		/*RFE_CTRL_0*/ /*A_1*/
-+	odm_set_bb_reg(dm, R_0xcbc, BIT(0), 0);		/*@inv*/
-+	odm_set_bb_reg(dm, R_0xcb0, 0xf, 0x9);
-+
-+	odm_set_bb_reg(dm, R_0x1990, BIT(8), 0);		/*RFE_CTRL_8*/ /*A_2*/
-+	odm_set_bb_reg(dm, R_0xcbc, BIT(8), 0);		/*@inv*/
-+	odm_set_bb_reg(dm, R_0xcb4, 0xf, 0xa);
-+
-+
-+	/*path B*/
-+	odm_set_bb_reg(dm, R_0x1990, BIT(4), 1);		/*RFE_CTRL_4*/	/*B_0*/
-+	odm_set_bb_reg(dm, R_0xdbc, BIT(4), 0);		/*@inv*/
-+	odm_set_bb_reg(dm, R_0xdb0, 0xf0000, 0xb);
-+
-+	odm_set_bb_reg(dm, R_0x1990, BIT(11), 1);	/*RFE_CTRL_11*/	/*B_1*/
-+	odm_set_bb_reg(dm, R_0xdbc, BIT(11), 0);		/*@inv*/
-+	odm_set_bb_reg(dm, R_0xdb4, 0xf000, 0xc);
-+
-+	odm_set_bb_reg(dm, R_0x1990, BIT(9), 1);		/*RFE_CTRL_9*/	/*B_2*/
-+	odm_set_bb_reg(dm, R_0xdbc, BIT(9), 0);		/*@inv*/
-+	odm_set_bb_reg(dm, R_0xdb4, 0xf0, 0xd);
-+#endif
-+	/*@========= BB SmtAnt setting =================================*/
-+	odm_set_mac_reg(dm, R_0x6d8, BIT(22) | BIT(21), 2); /*resp tx by register*/
-+	odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
-+	odm_set_bb_reg(dm, R_0x804, BIT(4), 0); /*@lathch antsel*/
-+	odm_set_bb_reg(dm, R_0x818, 0xf00000, 0); /*@keep tx by rx*/
-+	odm_set_bb_reg(dm, R_0x900, BIT(19), 0); /*@fast train*/
-+	odm_set_bb_reg(dm, R_0x900, BIT(18), 1); /*@1: by TXDESC*/
-+
-+	/*pathA*/
-+	odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x03020100); /*@ant map 1*/
-+	odm_set_bb_reg(dm, R_0xca8, MASKDWORD, 0x07060504); /*@ant map 2*/
-+	odm_set_bb_reg(dm, R_0xcac, BIT(9), 0); /*@keep antsel map by GNT_BT*/
-+
-+	/*pathB*/
-+	odm_set_bb_reg(dm, R_0xea4, MASKDWORD, 0x30201000); /*@ant map 1*/
-+	odm_set_bb_reg(dm, R_0xea8, MASKDWORD, 0x70605040); /*@ant map 2*/
-+	odm_set_bb_reg(dm, R_0xeac, BIT(9), 0); /*@keep antsel map by GNT_BT*/
-+}
-+
-+void phydm_cumitek_smt_ant_init_8197f(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant *smtant_table = &dm->smtant_table;
-+	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
-+	u32 value32;
-+
-+	PHYDM_DBG(dm, DBG_SMT_ANT, "[8197F Cumitek SmtAnt Int]\n");
-+
-+	/*@GPIO setting*/
-+}
-+
-+void phydm_cumitek_smt_ant_init_8192f(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant *smtant_table = &dm->smtant_table;
-+	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
-+	u32 value32;
-+	PHYDM_DBG(dm, DBG_SMT_ANT, "[8192F Cumitek SmtAnt Int]\n");
-+
-+	/*@GPIO setting*/
-+}
-+
-+void phydm_cumitek_smt_tx_ant_update(
-+	void *dm_void,
-+	u8 tx_ant_idx_path_a,
-+	u8 tx_ant_idx_path_b,
-+	u32 mac_id)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant *smtant_table = &dm->smtant_table;
-+	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[Cumitek] Set TX-ANT[%d] = (( A:0x%x ,  B:0x%x ))\n", mac_id,
-+		  tx_ant_idx_path_a, tx_ant_idx_path_b);
-+
-+	/*path-A*/
-+	cumi_smtant_table->tx_ant_idx[0][mac_id] = tx_ant_idx_path_a; /*@fill this value into TXDESC*/
-+
-+	/*path-B*/
-+	cumi_smtant_table->tx_ant_idx[1][mac_id] = tx_ant_idx_path_b; /*@fill this value into TXDESC*/
-+}
-+
-+void phydm_cumitek_smt_rx_default_ant_update(
-+	void *dm_void,
-+	u8 rx_ant_idx_path_a,
-+	u8 rx_ant_idx_path_b)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant *smtant_table = &dm->smtant_table;
-+	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[Cumitek] Set RX-ANT = (( A:0x%x, B:0x%x ))\n",
-+		  rx_ant_idx_path_a, rx_ant_idx_path_b);
-+
-+	/*path-A*/
-+	if (cumi_smtant_table->rx_default_ant_idx[0] != rx_ant_idx_path_a) {
-+		#if (RTL8822B_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8822B) {
-+			odm_set_bb_reg(dm, R_0xc08, BIT(21) | BIT(20) | BIT(19), rx_ant_idx_path_a); /*@default RX antenna*/
-+			odm_set_mac_reg(dm, R_0x6d8, BIT(2) | BIT(1) | BIT(0), rx_ant_idx_path_a); /*@default response TX antenna*/
-+		}
-+		#endif
-+
-+		#if (RTL8197F_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8197F) {
-+		}
-+		#endif
-+
-+		/*@jj add 20170822*/
-+		#if (RTL8192F_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8192F) {
-+		}
-+		#endif
-+		cumi_smtant_table->rx_default_ant_idx[0] = rx_ant_idx_path_a;
-+	}
-+
-+	/*path-B*/
-+	if (cumi_smtant_table->rx_default_ant_idx[1] != rx_ant_idx_path_b) {
-+		#if (RTL8822B_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8822B) {
-+			odm_set_bb_reg(dm, R_0xe08, BIT(21) | BIT(20) | BIT(19), rx_ant_idx_path_b); /*@default antenna*/
-+			odm_set_mac_reg(dm, R_0x6d8, BIT(5) | BIT(4) | BIT(3), rx_ant_idx_path_b); /*@default response TX antenna*/
-+		}
-+		#endif
-+
-+		#if (RTL8197F_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8197F) {
-+		}
-+		#endif
-+
-+		/*@jj add 20170822*/
-+		#if (RTL8192F_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8192F) {
-+		}
-+		#endif
-+		cumi_smtant_table->rx_default_ant_idx[1] = rx_ant_idx_path_b;
-+	}
-+}
-+
-+void phydm_cumitek_smt_ant_debug(
-+	void *dm_void,
-+	char input[][16],
-+	u32 *_used,
-+	char *output,
-+	u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant *smtant_table = &dm->smtant_table;
-+	struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	char help[] = "-h";
-+	u32 dm_value[10] = {0};
-+	u8 i;
-+
-+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]);
-+
-+	if (strcmp(input[1], help) == 0) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{1} {PathA rx_ant_idx} {pathB rx_ant_idx}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{2} {PathA tx_ant_idx} {pathB tx_ant_idx} {macid}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{3} {PathA mapping table} {PathB mapping table}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "{4} {txdesc_mode 0:3bit, 1:2bit}\n");
-+
-+	} else if (dm_value[0] == 1) { /*@fix rx_idle pattern*/
-+
-+		PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]);
-+		PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]);
-+
-+		phydm_cumitek_smt_rx_default_ant_update(dm, (u8)dm_value[1], (u8)dm_value[2]);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "RX Ant{A, B}={%d, %d}\n", dm_value[1], dm_value[2]);
-+
-+	} else if (dm_value[0] == 2) { /*@fix tx pattern*/
-+
-+		for (i = 1; i < 4; i++) {
-+			if (input[i + 1])
-+				PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
-+		}
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "STA[%d] TX Ant{A, B}={%d, %d}\n", dm_value[3],
-+			 dm_value[1], dm_value[2]);
-+		phydm_cumitek_smt_tx_ant_update(dm, (u8)dm_value[1], (u8)dm_value[2], (u8)dm_value[3]);
-+
-+	} else if (dm_value[0] == 3) {
-+		u8 table_path_a[8] = {0};
-+		u8 table_path_b[8] = {0};
-+
-+		for (i = 1; i < 4; i++) {
-+			if (input[i + 1])
-+				PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
-+		}
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Set Path-AB mapping table={%d, %d}\n", dm_value[1],
-+			 dm_value[2]);
-+
-+		for (i = 0; i < 8; i++) {
-+			table_path_a[i] = (u8)((dm_value[1] >> (4 * i)) & 0xf);
-+			table_path_b[i] = (u8)((dm_value[2] >> (4 * i)) & 0xf);
-+		}
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Ant_Table_A[7:0]={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x}\n",
-+			 table_path_a[7], table_path_a[6], table_path_a[5],
-+			 table_path_a[4], table_path_a[3], table_path_a[2],
-+			 table_path_a[1], table_path_a[0]);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "Ant_Table_B[7:0]={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x}\n",
-+			 table_path_b[7], table_path_b[6], table_path_b[5],
-+			 table_path_b[4], table_path_b[3], table_path_b[2],
-+			 table_path_b[1], table_path_b[0]);
-+
-+		phydm_cumitek_smt_ant_mapping_table_8822b(dm, &table_path_a[0], &table_path_b[0]);
-+
-+	} else if (dm_value[0] == 4) {
-+		smtant_table->tx_desc_mode = (u8)dm_value[1];
-+		odm_set_mac_reg(dm, R_0x604, BIT(25), (u32)smtant_table->tx_desc_mode);
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+#endif
-+
-+#if (defined(CONFIG_HL_SMART_ANTENNA))
-+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
-+
-+#if (RTL8822B_SUPPORT == 1)
-+void phydm_hl_smart_ant_type2_init_8822b(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	u8 j;
-+	u8 rfu_codeword_table_init_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = {
-+		{1, 1}, /*@0*/
-+		{1, 2},
-+		{2, 1},
-+		{2, 2},
-+		{4, 0},
-+		{5, 0},
-+		{6, 0},
-+		{7, 0},
-+		{8, 0}, /*@8*/
-+		{9, 0},
-+		{0xa, 0},
-+		{0xb, 0},
-+		{0xc, 0},
-+		{0xd, 0},
-+		{0xe, 0},
-+		{0xf, 0}};
-+	u8 rfu_codeword_table_init_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = {
-+#if 1
-+		{9, 1}, /*@0*/
-+		{9, 9},
-+		{1, 9},
-+		{9, 6},
-+		{2, 1},
-+		{2, 9},
-+		{9, 2},
-+		{2, 2}, /*@8*/
-+		{6, 1},
-+		{6, 9},
-+		{2, 9},
-+		{2, 2},
-+		{6, 2},
-+		{6, 6},
-+		{2, 6},
-+		{1, 1}
-+#else
-+		{1, 1}, /*@0*/
-+		{9, 1},
-+		{9, 9},
-+		{1, 9},
-+		{1, 2},
-+		{9, 2},
-+		{9, 6},
-+		{1, 6},
-+		{2, 1}, /*@8*/
-+		{6, 1},
-+		{6, 9},
-+		{2, 9},
-+		{2, 2},
-+		{6, 2},
-+		{6, 6},
-+		{2, 6}
-+#endif
-+	};
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "***RTK 8822B SmartAnt_Init: Hong-Bo SmrtAnt Type2]\n");
-+
-+	/* @---------------------------------------- */
-+	/* @GPIO 0-1 for Beam control */
-+	/* reg0x66[2:0]=0 */
-+	/* reg0x44[25:24] = 0 */
-+	/* reg0x44[23:16]  enable_output for P_GPIO[7:0] */
-+	/* reg0x44[15:8]  output_value for P_GPIO[7:0] */
-+	/* reg0x40[1:0] = 0  GPIO function */
-+	/* @------------------------------------------ */
-+
-+	odm_move_memory(dm, sat_tab->rfu_codeword_table_2g, rfu_codeword_table_init_2g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B));
-+	odm_move_memory(dm, sat_tab->rfu_codeword_table_5g, rfu_codeword_table_init_5g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B));
-+
-+	/*@GPIO setting*/
-+	odm_set_mac_reg(dm, R_0x64, (BIT(18) | BIT(17) | BIT(16)), 0);
-+	odm_set_mac_reg(dm, R_0x44, BIT(25) | BIT(24), 0); /*@config P_GPIO[3:2] to data port*/
-+	odm_set_mac_reg(dm, R_0x44, BIT(17) | BIT(16), 0x3); /*@enable_output for P_GPIO[3:2]*/
-+#if 0
-+	/*odm_set_mac_reg(dm, R_0x44, BIT(9)|BIT(8), 0);*/ /*P_GPIO[3:2] output value*/
-+#endif
-+	odm_set_mac_reg(dm, R_0x40, BIT(1) | BIT(0), 0); /*@GPIO function*/
-+
-+	/*@Hong_lin smart antenna HW setting*/
-+	sat_tab->rfu_protocol_type = 2;
-+	sat_tab->rfu_protocol_delay_time = 45;
-+
-+	sat_tab->rfu_codeword_total_bit_num = 16; /*@max=32bit*/
-+	sat_tab->rfu_each_ant_bit_num = 4;
-+
-+	sat_tab->total_beam_set_num = 4;
-+	sat_tab->total_beam_set_num_2g = 4;
-+	sat_tab->total_beam_set_num_5g = 8;
-+
-+#if DEV_BUS_TYPE == RT_SDIO_INTERFACE
-+	if (dm->support_interface == ODM_ITRF_SDIO)
-+		sat_tab->latch_time = 100; /*@mu sec*/
-+#endif
-+#if DEV_BUS_TYPE == RT_USB_INTERFACE
-+	if (dm->support_interface == ODM_ITRF_USB)
-+		sat_tab->latch_time = 100; /*@mu sec*/
-+#endif
-+	sat_tab->pkt_skip_statistic_en = 0;
-+
-+	sat_tab->ant_num = 2;
-+	sat_tab->ant_num_total = MAX_PATH_NUM_8822B;
-+	sat_tab->first_train_ant = MAIN_ANT;
-+
-+	sat_tab->fix_beam_pattern_en = 0;
-+	sat_tab->decision_holding_period = 0;
-+
-+	/*@beam training setting*/
-+	sat_tab->pkt_counter = 0;
-+	sat_tab->per_beam_training_pkt_num = 10;
-+
-+	/*set default beam*/
-+	sat_tab->fast_training_beam_num = 0;
-+	sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
-+
-+	for (j = 0; j < SUPPORT_BEAM_SET_PATTERN_NUM; j++) {
-+		sat_tab->beam_set_avg_rssi_pre[j] = 0;
-+		sat_tab->beam_set_train_val_diff[j] = 0;
-+		sat_tab->beam_set_train_cnt[j] = 0;
-+	}
-+	phydm_set_rfu_beam_pattern_type2(dm);
-+	fat_tab->fat_state = FAT_BEFORE_LINK_STATE;
-+}
-+#endif
-+
-+u32 phydm_construct_hb_rfu_codeword_type2(
-+	void *dm_void,
-+	u32 beam_set_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+	u32 sync_codeword = 0x7f;
-+	u32 codeword = 0;
-+	u32 data_tmp = 0;
-+	u32 i;
-+
-+	for (i = 0; i < sat_tab->ant_num_total; i++) {
-+		if (*dm->band_type == ODM_BAND_5G)
-+			data_tmp = sat_tab->rfu_codeword_table_5g[beam_set_idx][i];
-+		else
-+			data_tmp = sat_tab->rfu_codeword_table_2g[beam_set_idx][i];
-+
-+		codeword |= (data_tmp << (i * sat_tab->rfu_each_ant_bit_num));
-+	}
-+
-+	codeword = (codeword << 8) | sync_codeword;
-+
-+	return codeword;
-+}
-+
-+void phydm_update_beam_pattern_type2(
-+	void *dm_void,
-+	u32 codeword,
-+	u32 codeword_length)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+	u8 i;
-+	boolean beam_ctrl_signal;
-+	u32 one = 0x1;
-+	u32 reg44_tmp_p, reg44_tmp_n, reg44_ori;
-+	u8 devide_num = 4;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "Set codeword = ((0x%x))\n", codeword);
-+
-+	reg44_ori = odm_get_mac_reg(dm, R_0x44, MASKDWORD);
-+	reg44_tmp_p = reg44_ori;
-+#if 0
-+	/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_ori =0x%x\n", reg44_ori);*/
-+#endif
-+
-+	/*@devide_num = (sat_tab->rfu_protocol_type == 2) ? 8 : 4;*/
-+
-+	for (i = 0; i <= (codeword_length - 1); i++) {
-+		beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i);
-+
-+		#if 1
-+		if (dm->debug_components & DBG_ANT_DIV) {
-+			if (i == (codeword_length - 1))
-+				pr_debug("%d ]\n", beam_ctrl_signal);
-+			else if (i == 0)
-+				pr_debug("Start sending codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal);
-+			else if ((i % devide_num) == (devide_num - 1))
-+				pr_debug("%d  |  ", beam_ctrl_signal);
-+			else
-+				pr_debug("%d ", beam_ctrl_signal);
-+		}
-+		#endif
-+
-+		if (dm->support_ic_type == ODM_RTL8821) {
-+			#if (RTL8821A_SUPPORT == 1)
-+			reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT(10))); /*@clean bit 10 & 11*/
-+			reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10));
-+			reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10)));
-+
-+#if 0
-+			/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n);*/
-+#endif
-+			odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
-+			odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);
-+			#endif
-+		}
-+		#if (RTL8822B_SUPPORT == 1)
-+		else if (dm->support_ic_type == ODM_RTL8822B) {
-+			if (sat_tab->rfu_protocol_type == 2) {
-+				reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*@clean bit 8*/
-+				reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*@get new clk high/low, exclusive-or*/
-+
-+				reg44_tmp_p |= (beam_ctrl_signal << 8);
-+
-+				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
-+				ODM_delay_us(sat_tab->rfu_protocol_delay_time);
-+#if 0
-+				/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal);*/
-+#endif
-+
-+			} else {
-+				reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT(8))); /*@clean bit 9 & 8*/
-+				reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8));
-+				reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8)));
-+
-+#if 0
-+				/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n); */
-+#endif
-+				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
-+				ODM_delay_us(10);
-+				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);
-+				ODM_delay_us(10);
-+			}
-+		}
-+		#endif
-+	}
-+}
-+
-+void phydm_update_rx_idle_beam_type2(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+	u32 i;
-+
-+	sat_tab->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(dm, sat_tab->rx_idle_beam_set_idx);
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[ Update Rx-Idle-Beam ] BeamSet idx = ((%d))\n",
-+		  sat_tab->rx_idle_beam_set_idx);
-+
-+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+	if (dm->support_interface == ODM_ITRF_PCIE)
-+		phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
-+#endif
-+#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
-+	if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
-+		odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
-+#if 0
-+	/*odm_stall_execution(1);*/
-+#endif
-+#endif
-+
-+	sat_tab->pre_codeword = sat_tab->update_beam_codeword;
-+}
-+
-+void phydm_hl_smt_ant_dbg_type2(
-+	void *dm_void,
-+	char input[][16],
-+	u32 *_used,
-+	char *output,
-+	u32 *_out_len
-+)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 one = 0x1;
-+	u32 codeword_length = sat_tab->rfu_codeword_total_bit_num;
-+	u32 beam_ctrl_signal, i;
-+	u8 devide_num = 4;
-+	char help[] = "-h";
-+	u32 dm_value[10] = {0};
-+
-+	PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]);
-+	PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]);
-+	PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]);
-+	PHYDM_SSCANF(input[4], DCMD_DECIMAL, &dm_value[3]);
-+	PHYDM_SSCANF(input[5], DCMD_DECIMAL, &dm_value[4]);
-+
-+	if (strcmp(input[1], help) == 0) {
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 " 1 {fix_en} {codeword(Hex)}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 " 3 {Fix_training_num_en} {Per_beam_training_pkt_num} {Decision_holding_period}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 " 5 {0:show, 1:2G, 2:5G} {beam_num} {idxA(Hex)} {idxB(Hex)}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 " 7 {0:show, 1:2G, 2:5G} {total_beam_set_num}\n");
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 " 8 {0:show, 1:set} {RFU delay time(us)}\n");
-+
-+	} else if (dm_value[0] == 1) { /*@fix beam pattern*/
-+
-+		sat_tab->fix_beam_pattern_en = dm_value[1];
-+
-+		if (sat_tab->fix_beam_pattern_en == 1) {
-+			PHYDM_SSCANF(input[3], DCMD_HEX, &dm_value[2]);
-+			sat_tab->fix_beam_pattern_codeword = dm_value[2];
-+
-+			if (sat_tab->fix_beam_pattern_codeword > (one << codeword_length)) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n",
-+					  sat_tab->fix_beam_pattern_codeword,
-+					  codeword_length);
-+
-+				(sat_tab->fix_beam_pattern_codeword) &= 0xffffff;
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "[ SmartAnt ] Auto modify to (0x%x)\n",
-+					  sat_tab->fix_beam_pattern_codeword);
-+			}
-+
-+			sat_tab->update_beam_codeword = sat_tab->fix_beam_pattern_codeword;
-+
-+			/*@---------------------------------------------------------*/
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Fix Beam Pattern\n");
-+
-+			/*@devide_num = (sat_tab->rfu_protocol_type == 2) ? 8 : 4;*/
-+
-+			for (i = 0; i <= (codeword_length - 1); i++) {
-+				beam_ctrl_signal = (boolean)((sat_tab->update_beam_codeword & BIT(i)) >> i);
-+
-+				if (i == (codeword_length - 1))
-+					PDM_SNPF(out_len, used,
-+						 output + used,
-+						 out_len - used,
-+						 "%d]\n",
-+						 beam_ctrl_signal);
-+				else if (i == 0)
-+					PDM_SNPF(out_len, used,
-+						 output + used,
-+						 out_len - used,
-+						 "Send Codeword[1:%d] to RFU -> [%d",
-+						 sat_tab->rfu_codeword_total_bit_num,
-+						 beam_ctrl_signal);
-+				else if ((i % devide_num) == (devide_num - 1))
-+					PDM_SNPF(out_len, used,
-+						 output + used,
-+						 out_len - used, "%d|",
-+						 beam_ctrl_signal);
-+				else
-+					PDM_SNPF(out_len, used,
-+						 output + used,
-+						 out_len - used, "%d",
-+						 beam_ctrl_signal);
-+			}
-+/*@---------------------------------------------------------*/
-+
-+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+			if (dm->support_interface == ODM_ITRF_PCIE)
-+				phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
-+#endif
-+#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
-+			if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
-+			odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
-+#if 0
-+			/*odm_stall_execution(1);*/
-+#endif
-+#endif
-+		} else if (sat_tab->fix_beam_pattern_en == 0)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[ SmartAnt ] Smart Antenna: Enable\n");
-+
-+	} else if (dm_value[0] == 2) { /*set latch time*/
-+
-+		sat_tab->latch_time = dm_value[1];
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ]  latch_time =0x%x\n",
-+			  sat_tab->latch_time);
-+	} else if (dm_value[0] == 3) {
-+		sat_tab->fix_training_num_en = dm_value[1];
-+
-+		if (sat_tab->fix_training_num_en == 1) {
-+			sat_tab->per_beam_training_pkt_num = (u8)dm_value[2];
-+			sat_tab->decision_holding_period = (u8)dm_value[3];
-+
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[SmtAnt] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n",
-+				 sat_tab->fix_training_num_en,
-+				 sat_tab->per_beam_training_pkt_num,
-+				 sat_tab->decision_holding_period);
-+
-+		} else if (sat_tab->fix_training_num_en == 0) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[ SmartAnt ]  AUTO per_beam_training_pkt_num\n");
-+		}
-+	} else if (dm_value[0] == 4) {
-+		#if 0
-+		if (dm_value[1] == 1) {
-+			sat_tab->ant_num = 1;
-+			sat_tab->first_train_ant = MAIN_ANT;
-+
-+		} else if (dm_value[1] == 2) {
-+			sat_tab->ant_num = 1;
-+			sat_tab->first_train_ant = AUX_ANT;
-+
-+		} else if (dm_value[1] == 3) {
-+			sat_tab->ant_num = 2;
-+			sat_tab->first_train_ant = MAIN_ANT;
-+		}
-+
-+		PDM_SNPF((output + used, out_len - used,
-+			 "[ SmartAnt ]  Set ant Num = (( %d )), first_train_ant = (( %d ))\n",
-+			 sat_tab->ant_num, (sat_tab->first_train_ant - 1)));
-+		#endif
-+	} else if (dm_value[0] == 5) { /*set beam set table*/
-+
-+		PHYDM_SSCANF(input[4], DCMD_HEX, &dm_value[3]);
-+		PHYDM_SSCANF(input[5], DCMD_HEX, &dm_value[4]);
-+
-+		if (dm_value[1] == 1) { /*@2G*/
-+			if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) {
-+				sat_tab->rfu_codeword_table_2g[dm_value[2]][0] = (u8)dm_value[3];
-+				sat_tab->rfu_codeword_table_2g[dm_value[2]][1] = (u8)dm_value[4];
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used,
-+					 "[SmtAnt] Set 2G Table[%d] = [A:0x%x, B:0x%x]\n",
-+					 dm_value[2], dm_value[3], dm_value[4]);
-+			}
-+
-+		} else if (dm_value[1] == 2) { /*@5G*/
-+			if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) {
-+				sat_tab->rfu_codeword_table_5g[dm_value[2]][0] = (u8)dm_value[3];
-+				sat_tab->rfu_codeword_table_5g[dm_value[2]][1] = (u8)dm_value[4];
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used,
-+					 "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n",
-+					 dm_value[2], dm_value[3], dm_value[4]);
-+			}
-+		} else if (dm_value[1] == 0) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[SmtAnt] 2G Beam Table==============>\n");
-+			for (i = 0; i < sat_tab->total_beam_set_num_2g; i++) {
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used,
-+					 "2G Table[%d] = [A:0x%x, B:0x%x]\n", i,
-+					 sat_tab->rfu_codeword_table_2g[i][0],
-+					 sat_tab->rfu_codeword_table_2g[i][1]);
-+			}
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[SmtAnt] 5G Beam Table==============>\n");
-+			for (i = 0; i < sat_tab->total_beam_set_num_5g; i++) {
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used,
-+					 "5G Table[%d] = [A:0x%x, B:0x%x]\n", i,
-+					 sat_tab->rfu_codeword_table_5g[i][0],
-+					 sat_tab->rfu_codeword_table_5g[i][1]);
-+			}
-+		}
-+
-+	} else if (dm_value[0] == 6) {
-+#if 0
-+		if (dm_value[1] == 0) {
-+			if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) {
-+				sat_tab->rfu_codeword_table_5g[dm_value[2] ][0] = (u8)dm_value[3];
-+				sat_tab->rfu_codeword_table_5g[dm_value[2] ][1] = (u8)dm_value[4];
-+				PDM_SNPF((output + used, out_len - used,
-+					 "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n",
-+					 dm_value[2], dm_value[3],
-+					 dm_value[4]));
-+			}
-+		} else {
-+			for (i = 0; i < sat_tab->total_beam_set_num_5g; i++) {
-+				PDM_SNPF((output + used, out_len - used,
-+					 "[SmtAnt] Read 5G Table[%d] = [A:0x%x, B:0x%x]\n",
-+					 i,
-+					 sat_tab->rfu_codeword_table_5g[i][0],
-+					 sat_tab->rfu_codeword_table_5g[i][1]));
-+			}
-+		}
-+#endif
-+	} else if (dm_value[0] == 7) {
-+		if (dm_value[1] == 1) {
-+			sat_tab->total_beam_set_num_2g = (u8)(dm_value[2]);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[ SmartAnt ] total_beam_set_num_2g = ((%d))\n",
-+				 sat_tab->total_beam_set_num_2g);
-+
-+		} else if (dm_value[1] == 2) {
-+			sat_tab->total_beam_set_num_5g = (u8)(dm_value[2]);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[ SmartAnt ] total_beam_set_num_5g = ((%d))\n",
-+				 sat_tab->total_beam_set_num_5g);
-+		} else if (dm_value[1] == 0) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[ SmartAnt ] Show total_beam_set_num{2g,5g} = {%d,%d}\n",
-+				 sat_tab->total_beam_set_num_2g,
-+				 sat_tab->total_beam_set_num_5g);
-+		}
-+
-+	} else if (dm_value[0] == 8) {
-+		if (dm_value[1] == 1) {
-+			sat_tab->rfu_protocol_delay_time = (u16)(dm_value[2]);
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[SmtAnt] Set rfu_protocol_delay_time = ((%d))\n",
-+				 sat_tab->rfu_protocol_delay_time);
-+		} else if (dm_value[1] == 0) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[SmtAnt] Read rfu_protocol_delay_time = ((%d))\n",
-+				 sat_tab->rfu_protocol_delay_time);
-+		}
-+	}
-+
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_set_rfu_beam_pattern_type2(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+
-+	if (dm->ant_div_type != HL_SW_SMART_ANT_TYPE2)
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "Training beam_set index = (( 0x%x ))\n",
-+		  sat_tab->fast_training_beam_num);
-+	sat_tab->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(dm, sat_tab->fast_training_beam_num);
-+
-+	#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+	if (dm->support_interface == ODM_ITRF_PCIE)
-+		phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
-+	#endif
-+	#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
-+	if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
-+		odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
-+#if 0
-+	/*odm_stall_execution(1);*/
-+#endif
-+	#endif
-+}
-+
-+void phydm_fast_ant_training_hl_smart_antenna_type2(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
-+	u32 codeword = 0;
-+	u8 i = 0, j = 0;
-+	u8 avg_rssi_tmp;
-+	u8 avg_rssi_tmp_ma;
-+	u8 max_beam_ant_rssi = 0;
-+	u8 rssi_target_beam = 0, target_beam_max_rssi = 0;
-+	u8 evm1ss_target_beam = 0, evm2ss_target_beam = 0;
-+	u32 target_beam_max_evm1ss = 0, target_beam_max_evm2ss = 0;
-+	u32 beam_tmp;
-+	u8 per_beam_val_diff_tmp = 0, training_pkt_num_offset;
-+	u32 avg_evm2ss[2] = {0}, avg_evm2ss_sum = 0;
-+	u32 avg_evm1ss = 0;
-+	u32 beam_path_evm_2ss_cnt_all = 0; /*sum of all 2SS-pattern cnt*/
-+	u32 beam_path_evm_1ss_cnt_all = 0; /*sum of all 1SS-pattern cnt*/
-+	u8 decision_type;
-+
-+	if (!dm->is_linked) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
-+
-+		if (fat_tab->is_become_linked == true) {
-+			sat_tab->decision_holding_period = 0;
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "Link->no Link\n");
-+			fat_tab->fat_state = FAT_BEFORE_LINK_STATE;
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "change to (( %d )) FAT_state\n",
-+				  fat_tab->fat_state);
-+			fat_tab->is_become_linked = dm->is_linked;
-+		}
-+		return;
-+
-+	} else {
-+		if (fat_tab->is_become_linked == false) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
-+
-+			fat_tab->fat_state = FAT_PREPARE_STATE;
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "change to (( %d )) FAT_state\n",
-+				  fat_tab->fat_state);
-+
-+			/*sat_tab->fast_training_beam_num = 0;*/
-+			/*phydm_set_rfu_beam_pattern_type2(dm);*/
-+
-+			fat_tab->is_become_linked = dm->is_linked;
-+		}
-+	}
-+
-+#if 0
-+	/*PHYDM_DBG(dm, DBG_ANT_DIV, "HL Smart ant Training: state (( %d ))\n", fat_tab->fat_state);*/
-+#endif
-+
-+	/* @[DECISION STATE] */
-+	/*@=======================================================================================*/
-+	if (fat_tab->fat_state == FAT_DECISION_STATE) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[ 3. In Decision state]\n");
-+
-+		/*@compute target beam in each antenna*/
-+
-+		for (j = 0; j < (sat_tab->total_beam_set_num); j++) {
-+			/*@[Decision1: RSSI]-------------------------------------------------------------------*/
-+			if (sat_tab->statistic_pkt_cnt[j] == 0) { /*@if new RSSI = 0 -> MA_RSSI-=2*/
-+				avg_rssi_tmp = sat_tab->beam_set_avg_rssi_pre[j];
-+				avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp;
-+				avg_rssi_tmp_ma = avg_rssi_tmp;
-+			} else {
-+				avg_rssi_tmp = (u8)((sat_tab->beam_set_rssi_avg_sum[j]) / (sat_tab->statistic_pkt_cnt[j]));
-+				avg_rssi_tmp_ma = (avg_rssi_tmp + sat_tab->beam_set_avg_rssi_pre[j]) >> 1;
-+			}
-+
-+			sat_tab->beam_set_avg_rssi_pre[j] = avg_rssi_tmp;
-+
-+			if (avg_rssi_tmp > target_beam_max_rssi) {
-+				rssi_target_beam = j;
-+				target_beam_max_rssi = avg_rssi_tmp;
-+			}
-+
-+			/*@[Decision2: EVM 2ss]-------------------------------------------------------------------*/
-+			if (sat_tab->beam_path_evm_2ss_cnt[j] != 0) {
-+				avg_evm2ss[0] = sat_tab->beam_path_evm_2ss_sum[j][0] / sat_tab->beam_path_evm_2ss_cnt[j];
-+				avg_evm2ss[1] = sat_tab->beam_path_evm_2ss_sum[j][1] / sat_tab->beam_path_evm_2ss_cnt[j];
-+				avg_evm2ss_sum = avg_evm2ss[0] + avg_evm2ss[1];
-+				beam_path_evm_2ss_cnt_all += sat_tab->beam_path_evm_2ss_cnt[j];
-+
-+				sat_tab->beam_set_avg_evm_2ss_pre[j] = (u8)avg_evm2ss_sum;
-+			}
-+
-+			if (avg_evm2ss_sum > target_beam_max_evm2ss) {
-+				evm2ss_target_beam = j;
-+				target_beam_max_evm2ss = avg_evm2ss_sum;
-+			}
-+
-+			/*@[Decision3: EVM 1ss]-------------------------------------------------------------------*/
-+			if (sat_tab->beam_path_evm_1ss_cnt[j] != 0) {
-+				avg_evm1ss = sat_tab->beam_path_evm_1ss_sum[j] / sat_tab->beam_path_evm_1ss_cnt[j];
-+				beam_path_evm_1ss_cnt_all += sat_tab->beam_path_evm_1ss_cnt[j];
-+
-+				sat_tab->beam_set_avg_evm_1ss_pre[j] = (u8)avg_evm1ss;
-+			}
-+
-+			if (avg_evm1ss > target_beam_max_evm1ss) {
-+				evm1ss_target_beam = j;
-+				target_beam_max_evm1ss = avg_evm1ss;
-+			}
-+
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "Beam[%d] Pkt_cnt=(( %d )), avg{MA,rssi}={%d, %d}, EVM1={%d}, EVM2={%d, %d, %d}\n",
-+				  j, sat_tab->statistic_pkt_cnt[j],
-+				  avg_rssi_tmp_ma, avg_rssi_tmp, avg_evm1ss,
-+				  avg_evm2ss[0], avg_evm2ss[1], avg_evm2ss_sum);
-+
-+			/*reset counter value*/
-+			sat_tab->beam_set_rssi_avg_sum[j] = 0;
-+			sat_tab->beam_path_rssi_sum[j][0] = 0;
-+			sat_tab->beam_path_rssi_sum[j][1] = 0;
-+			sat_tab->statistic_pkt_cnt[j] = 0;
-+
-+			sat_tab->beam_path_evm_2ss_sum[j][0] = 0;
-+			sat_tab->beam_path_evm_2ss_sum[j][1] = 0;
-+			sat_tab->beam_path_evm_2ss_cnt[j] = 0;
-+
-+			sat_tab->beam_path_evm_1ss_sum[j] = 0;
-+			sat_tab->beam_path_evm_1ss_cnt[j] = 0;
-+		}
-+
-+		/*@[Joint Decision]-------------------------------------------------------------------*/
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "--->1.[RSSI]      Target Beam(( %d )) RSSI_max=((%d))\n",
-+			  rssi_target_beam, target_beam_max_rssi);
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "--->2.[Evm2SS] Target Beam(( %d )) EVM2SS_max=((%d))\n",
-+			  evm2ss_target_beam, target_beam_max_evm2ss);
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "--->3.[Evm1SS] Target Beam(( %d )) EVM1SS_max=((%d))\n",
-+			  evm1ss_target_beam, target_beam_max_evm1ss);
-+
-+		if (target_beam_max_rssi <= 10) {
-+			sat_tab->rx_idle_beam_set_idx = rssi_target_beam;
-+			decision_type = 1;
-+		} else {
-+			if (beam_path_evm_2ss_cnt_all != 0) {
-+				sat_tab->rx_idle_beam_set_idx = evm2ss_target_beam;
-+				decision_type = 2;
-+			} else if (beam_path_evm_1ss_cnt_all != 0) {
-+				sat_tab->rx_idle_beam_set_idx = evm1ss_target_beam;
-+				decision_type = 3;
-+			} else {
-+				sat_tab->rx_idle_beam_set_idx = rssi_target_beam;
-+				decision_type = 1;
-+			}
-+		}
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "---> Decision_type=((%d)), Final Target Beam(( %d ))\n",
-+			  decision_type, sat_tab->rx_idle_beam_set_idx);
-+
-+		/*@Calculate packet counter offset*/
-+		for (j = 0; j < (sat_tab->total_beam_set_num); j++) {
-+			if (decision_type == 1) {
-+				per_beam_val_diff_tmp = target_beam_max_rssi - sat_tab->beam_set_avg_rssi_pre[j];
-+
-+			} else if (decision_type == 2) {
-+				per_beam_val_diff_tmp = ((u8)target_beam_max_evm2ss - sat_tab->beam_set_avg_evm_2ss_pre[j]) >> 1;
-+			} else if (decision_type == 3) {
-+				per_beam_val_diff_tmp = (u8)target_beam_max_evm1ss - sat_tab->beam_set_avg_evm_1ss_pre[j];
-+			}
-+			sat_tab->beam_set_train_val_diff[j] = per_beam_val_diff_tmp;
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "Beam_Set[%d]: diff= ((%d))\n", j,
-+				  per_beam_val_diff_tmp);
-+		}
-+
-+		/*set beam in each antenna*/
-+		phydm_update_rx_idle_beam_type2(dm);
-+		fat_tab->fat_state = FAT_PREPARE_STATE;
-+	}
-+	/* @[TRAINING STATE] */
-+	else if (fat_tab->fat_state == FAT_TRAINING_STATE) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2. In Training state]\n");
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "curr_beam_idx = (( %d )), pre_beam_idx = (( %d ))\n",
-+			  sat_tab->fast_training_beam_num,
-+			  sat_tab->pre_fast_training_beam_num);
-+
-+		if (sat_tab->fast_training_beam_num > sat_tab->pre_fast_training_beam_num)
-+
-+			sat_tab->force_update_beam_en = 0;
-+
-+		else {
-+			sat_tab->force_update_beam_en = 1;
-+
-+			sat_tab->pkt_counter = 0;
-+			beam_tmp = sat_tab->fast_training_beam_num;
-+			if (sat_tab->fast_training_beam_num >= ((u32)sat_tab->total_beam_set_num - 1)) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "[Timeout Update]  Beam_num (( %d )) -> (( decision ))\n",
-+					  sat_tab->fast_training_beam_num);
-+				fat_tab->fat_state = FAT_DECISION_STATE;
-+				phydm_fast_ant_training_hl_smart_antenna_type2(dm);
-+
-+			} else {
-+				sat_tab->fast_training_beam_num++;
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "[Timeout Update]  Beam_num (( %d )) -> (( %d ))\n",
-+					  beam_tmp,
-+					  sat_tab->fast_training_beam_num);
-+				phydm_set_rfu_beam_pattern_type2(dm);
-+				fat_tab->fat_state = FAT_TRAINING_STATE;
-+			}
-+		}
-+		sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "Update Pre_Beam =(( %d ))\n",
-+			  sat_tab->pre_fast_training_beam_num);
-+	}
-+	/*  @[Prepare state] */
-+	/*@=======================================================================================*/
-+	else if (fat_tab->fat_state == FAT_PREPARE_STATE) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "\n\n[ 1. In Prepare state]\n");
-+
-+		if (dm->pre_traffic_load == dm->traffic_load) {
-+			if (sat_tab->decision_holding_period != 0) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "Holding_period = (( %d )), return!!!\n",
-+					  sat_tab->decision_holding_period);
-+				sat_tab->decision_holding_period--;
-+				return;
-+			}
-+		}
-+
-+		/* Set training packet number*/
-+		if (sat_tab->fix_training_num_en == 0) {
-+			switch (dm->traffic_load) {
-+			case TRAFFIC_HIGH:
-+				sat_tab->per_beam_training_pkt_num = 8;
-+				sat_tab->decision_holding_period = 2;
-+				break;
-+			case TRAFFIC_MID:
-+				sat_tab->per_beam_training_pkt_num = 6;
-+				sat_tab->decision_holding_period = 3;
-+				break;
-+			case TRAFFIC_LOW:
-+				sat_tab->per_beam_training_pkt_num = 3; /*ping 60000*/
-+				sat_tab->decision_holding_period = 4;
-+				break;
-+			case TRAFFIC_ULTRA_LOW:
-+				sat_tab->per_beam_training_pkt_num = 1;
-+				sat_tab->decision_holding_period = 6;
-+				break;
-+			default:
-+				break;
-+			}
-+		}
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "TrafficLoad = (( %d )), Fix_beam = (( %d )), per_beam_training_pkt_num = (( %d )), decision_holding_period = ((%d))\n",
-+			  dm->traffic_load, sat_tab->fix_training_num_en,
-+			  sat_tab->per_beam_training_pkt_num,
-+			  sat_tab->decision_holding_period);
-+
-+		/*@Beam_set number*/
-+		if (*dm->band_type == ODM_BAND_5G) {
-+			sat_tab->total_beam_set_num = sat_tab->total_beam_set_num_5g;
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "5G beam_set num = ((%d))\n",
-+				  sat_tab->total_beam_set_num);
-+		} else {
-+			sat_tab->total_beam_set_num = sat_tab->total_beam_set_num_2g;
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "2G beam_set num = ((%d))\n",
-+				  sat_tab->total_beam_set_num);
-+		}
-+
-+		for (j = 0; j < (sat_tab->total_beam_set_num); j++) {
-+			training_pkt_num_offset = sat_tab->beam_set_train_val_diff[j];
-+
-+			if (sat_tab->per_beam_training_pkt_num > training_pkt_num_offset)
-+				sat_tab->beam_set_train_cnt[j] = sat_tab->per_beam_training_pkt_num - training_pkt_num_offset;
-+			else
-+				sat_tab->beam_set_train_cnt[j] = 1;
-+
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "Beam_Set[ %d ] training_pkt_offset = ((%d)), training_pkt_num = ((%d))\n",
-+				  j, sat_tab->beam_set_train_val_diff[j],
-+				  sat_tab->beam_set_train_cnt[j]);
-+		}
-+
-+		sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
-+		sat_tab->update_beam_idx = 0;
-+		sat_tab->pkt_counter = 0;
-+
-+		sat_tab->fast_training_beam_num = 0;
-+		phydm_set_rfu_beam_pattern_type2(dm);
-+		sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
-+		fat_tab->fat_state = FAT_TRAINING_STATE;
-+	}
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+void phydm_beam_switch_workitem_callback(
-+	void *context)
-+{
-+	void *adapter = (void *)context;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+
-+#if DEV_BUS_TYPE != RT_PCI_INTERFACE
-+	sat_tab->pkt_skip_statistic_en = 1;
-+#endif
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n",
-+		  sat_tab->pkt_skip_statistic_en);
-+
-+	phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
-+
-+#if DEV_BUS_TYPE != RT_PCI_INTERFACE
-+#if 0
-+	/*odm_stall_execution(sat_tab->latch_time);*/
-+#endif
-+	sat_tab->pkt_skip_statistic_en = 0;
-+#endif
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n",
-+		  sat_tab->pkt_skip_statistic_en, sat_tab->latch_time);
-+}
-+
-+void phydm_beam_decision_workitem_callback(
-+	void *context)
-+{
-+	void *adapter = (void *)context;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[ SmartAnt ] Beam decision Workitem Callback\n");
-+	phydm_fast_ant_training_hl_smart_antenna_type2(dm);
-+}
-+#endif
-+
-+void phydm_process_rssi_for_hb_smtant_type2(
-+	void *dm_void,
-+	void *phy_info_void,
-+	void *pkt_info_void,
-+	u8 rssi_avg)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
-+	struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+	u8 train_pkt_number;
-+	u32 beam_tmp;
-+	u8 rx_power_ant0 = phy_info->rx_mimo_signal_strength[0];
-+	u8 rx_power_ant1 = phy_info->rx_mimo_signal_strength[1];
-+	u8 rx_evm_ant0 = phy_info->rx_mimo_evm_dbm[0];
-+	u8 rx_evm_ant1 = phy_info->rx_mimo_evm_dbm[1];
-+
-+	/*@[Beacon]*/
-+	if (pktinfo->is_packet_beacon) {
-+		sat_tab->beacon_counter++;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "MatchBSSID_beacon_counter = ((%d))\n",
-+			  sat_tab->beacon_counter);
-+
-+		if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) {
-+			sat_tab->update_beam_idx++;
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n",
-+				  sat_tab->pre_beacon_counter,
-+				  sat_tab->pkt_counter,
-+				  sat_tab->update_beam_idx);
-+
-+			sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
-+			sat_tab->pkt_counter = 0;
-+		}
-+	}
-+	/*@[data]*/
-+	else if (pktinfo->is_packet_to_self) {
-+		if (sat_tab->pkt_skip_statistic_en == 0) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "ID[%d] pkt_cnt=((%d)): Beam_set = ((%d)), RSSI{A,B,avg} = {%d, %d, %d}\n",
-+				  pktinfo->station_id, sat_tab->pkt_counter,
-+				  sat_tab->fast_training_beam_num,
-+				  rx_power_ant0, rx_power_ant1, rssi_avg);
-+
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "Rate_ss = ((%d)), EVM{A,B} = {%d, %d}, RX Rate =",
-+				  pktinfo->rate_ss, rx_evm_ant0, rx_evm_ant1);
-+			phydm_print_rate(dm, dm->rx_rate, DBG_ANT_DIV);
-+
-+			if (sat_tab->pkt_counter >= 1) /*packet skip count*/
-+			{
-+				sat_tab->beam_set_rssi_avg_sum[sat_tab->fast_training_beam_num] += rssi_avg;
-+				sat_tab->statistic_pkt_cnt[sat_tab->fast_training_beam_num]++;
-+
-+				sat_tab->beam_path_rssi_sum[sat_tab->fast_training_beam_num][0] += rx_power_ant0;
-+				sat_tab->beam_path_rssi_sum[sat_tab->fast_training_beam_num][1] += rx_power_ant1;
-+
-+				if (pktinfo->rate_ss == 2) {
-+					sat_tab->beam_path_evm_2ss_sum[sat_tab->fast_training_beam_num][0] += rx_evm_ant0;
-+					sat_tab->beam_path_evm_2ss_sum[sat_tab->fast_training_beam_num][1] += rx_evm_ant1;
-+					sat_tab->beam_path_evm_2ss_cnt[sat_tab->fast_training_beam_num]++;
-+				} else {
-+					sat_tab->beam_path_evm_1ss_sum[sat_tab->fast_training_beam_num] += rx_evm_ant0;
-+					sat_tab->beam_path_evm_1ss_cnt[sat_tab->fast_training_beam_num]++;
-+				}
-+			}
-+
-+			sat_tab->pkt_counter++;
-+
-+			train_pkt_number = sat_tab->beam_set_train_cnt[sat_tab->fast_training_beam_num];
-+
-+			if (sat_tab->pkt_counter >= train_pkt_number) {
-+				sat_tab->update_beam_idx++;
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "pre_beacon_counter = ((%d)), Update_new_beam = ((%d))\n",
-+					  sat_tab->pre_beacon_counter,
-+					  sat_tab->update_beam_idx);
-+
-+				sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
-+				sat_tab->pkt_counter = 0;
-+			}
-+		}
-+	}
-+
-+	if (sat_tab->update_beam_idx > 0) {
-+		sat_tab->update_beam_idx = 0;
-+
-+		if (sat_tab->fast_training_beam_num >= ((u32)sat_tab->total_beam_set_num - 1)) {
-+			fat_tab->fat_state = FAT_DECISION_STATE;
-+
-+			#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+			if (dm->support_interface == ODM_ITRF_PCIE)
-+				phydm_fast_ant_training_hl_smart_antenna_type2(dm); /*@go to make decision*/
-+			#endif
-+			#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
-+			if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
-+				odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
-+			#endif
-+
-+		} else {
-+			beam_tmp = sat_tab->fast_training_beam_num;
-+			sat_tab->fast_training_beam_num++;
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "Update Beam_num (( %d )) -> (( %d ))\n",
-+				  beam_tmp, sat_tab->fast_training_beam_num);
-+			phydm_set_rfu_beam_pattern_type2(dm);
-+			sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
-+
-+			fat_tab->fat_state = FAT_TRAINING_STATE;
-+		}
-+	}
-+}
-+#endif
-+
-+#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))
-+
-+void phydm_hl_smart_ant_type1_init_8821a(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	u32 value32;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "***8821A SmartAnt_Init => ant_div_type=[Hong-Lin Smart ant Type1]\n");
-+
-+#if 0
-+	/* @---------------------------------------- */
-+	/* @GPIO 2-3 for Beam control */
-+	/* reg0x66[2]=0 */
-+	/* reg0x44[27:26] = 0 */
-+	/* reg0x44[23:16]  enable_output for P_GPIO[7:0] */
-+	/* reg0x44[15:8]  output_value for P_GPIO[7:0] */
-+	/* reg0x40[1:0] = 0  GPIO function */
-+	/* @------------------------------------------ */
-+#endif
-+
-+	/*@GPIO setting*/
-+	odm_set_mac_reg(dm, R_0x64, BIT(18), 0);
-+	odm_set_mac_reg(dm, R_0x44, BIT(27) | BIT(26), 0);
-+	odm_set_mac_reg(dm, R_0x44, BIT(19) | BIT(18), 0x3); /*@enable_output for P_GPIO[3:2]*/
-+#if 0
-+	/*odm_set_mac_reg(dm, R_0x44, BIT(11)|BIT(10), 0);*/ /*output value*/
-+#endif
-+	odm_set_mac_reg(dm, R_0x40, BIT(1) | BIT(0), 0); /*@GPIO function*/
-+
-+	/*@Hong_lin smart antenna HW setting*/
-+	sat_tab->rfu_codeword_total_bit_num = 24; /*@max=32*/
-+	sat_tab->rfu_each_ant_bit_num = 4;
-+	sat_tab->beam_patten_num_each_ant = 4;
-+
-+#if DEV_BUS_TYPE == RT_SDIO_INTERFACE
-+	sat_tab->latch_time = 100; /*@mu sec*/
-+#elif DEV_BUS_TYPE == RT_USB_INTERFACE
-+	sat_tab->latch_time = 100; /*@mu sec*/
-+#endif
-+	sat_tab->pkt_skip_statistic_en = 0;
-+
-+	sat_tab->ant_num = 1; /*@max=8*/
-+	sat_tab->ant_num_total = NUM_ANTENNA_8821A;
-+	sat_tab->first_train_ant = MAIN_ANT;
-+
-+	sat_tab->rfu_codeword_table[0] = 0x0;
-+	sat_tab->rfu_codeword_table[1] = 0x4;
-+	sat_tab->rfu_codeword_table[2] = 0x8;
-+	sat_tab->rfu_codeword_table[3] = 0xc;
-+
-+	sat_tab->rfu_codeword_table_5g[0] = 0x1;
-+	sat_tab->rfu_codeword_table_5g[1] = 0x2;
-+	sat_tab->rfu_codeword_table_5g[2] = 0x4;
-+	sat_tab->rfu_codeword_table_5g[3] = 0x8;
-+
-+	sat_tab->fix_beam_pattern_en = 0;
-+	sat_tab->decision_holding_period = 0;
-+
-+	/*@beam training setting*/
-+	sat_tab->pkt_counter = 0;
-+	sat_tab->per_beam_training_pkt_num = 10;
-+
-+	/*set default beam*/
-+	sat_tab->fast_training_beam_num = 0;
-+	sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
-+	phydm_set_all_ant_same_beam_num(dm);
-+
-+	fat_tab->fat_state = FAT_BEFORE_LINK_STATE;
-+
-+	odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x01000100);
-+	odm_set_bb_reg(dm, R_0xca8, MASKDWORD, 0x01000100);
-+
-+	/*@[BB] FAT setting*/
-+	odm_set_bb_reg(dm, R_0xc08, BIT(18) | BIT(17) | BIT(16), sat_tab->ant_num);
-+	odm_set_bb_reg(dm, R_0xc08, BIT(31), 0); /*@increase ant num every FAT period 0:+1, 1+2*/
-+	odm_set_bb_reg(dm, R_0x8c4, BIT(2) | BIT(1), 1); /*@change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/
-+	odm_set_bb_reg(dm, R_0x8c4, BIT(0), 1); /*@FAT_watchdog_en*/
-+
-+	value32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD);
-+	odm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /*Reg7B4[16]=1 enable antenna training */
-+	/*Reg7B4[17]=1 enable  match MAC addr*/
-+	odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0); /*@Match MAC ADDR*/
-+	odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0);
-+}
-+
-+u32 phydm_construct_hl_beam_codeword(
-+	void *dm_void,
-+	u32 *beam_pattern_idx,
-+	u32 ant_num)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+	u32 codeword = 0;
-+	u32 data_tmp;
-+	u32 i;
-+	u32 break_counter = 0;
-+
-+	if (ant_num < 8) {
-+		for (i = 0; i < (sat_tab->ant_num_total); i++) {
-+#if 0
-+			/*PHYDM_DBG(dm,DBG_ANT_DIV, "beam_pattern_num[%x] = %x\n",i,beam_pattern_num[i] );*/
-+#endif
-+			if ((i < (sat_tab->first_train_ant - 1)) || break_counter >= sat_tab->ant_num) {
-+				data_tmp = 0;
-+			} else {
-+				break_counter++;
-+
-+				if (beam_pattern_idx[i] == 0) {
-+					if (*dm->band_type == ODM_BAND_5G)
-+						data_tmp = sat_tab->rfu_codeword_table_5g[0];
-+					else
-+						data_tmp = sat_tab->rfu_codeword_table[0];
-+
-+				} else if (beam_pattern_idx[i] == 1) {
-+					if (*dm->band_type == ODM_BAND_5G)
-+						data_tmp = sat_tab->rfu_codeword_table_5g[1];
-+					else
-+						data_tmp = sat_tab->rfu_codeword_table[1];
-+
-+				} else if (beam_pattern_idx[i] == 2) {
-+					if (*dm->band_type == ODM_BAND_5G)
-+						data_tmp = sat_tab->rfu_codeword_table_5g[2];
-+					else
-+						data_tmp = sat_tab->rfu_codeword_table[2];
-+
-+				} else if (beam_pattern_idx[i] == 3) {
-+					if (*dm->band_type == ODM_BAND_5G)
-+						data_tmp = sat_tab->rfu_codeword_table_5g[3];
-+					else
-+						data_tmp = sat_tab->rfu_codeword_table[3];
-+				}
-+			}
-+
-+			codeword |= (data_tmp << (i * 4));
-+		}
-+	}
-+
-+	return codeword;
-+}
-+
-+void phydm_update_beam_pattern(
-+	void *dm_void,
-+	u32 codeword,
-+	u32 codeword_length)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+	u8 i;
-+	boolean beam_ctrl_signal;
-+	u32 one = 0x1;
-+	u32 reg44_tmp_p, reg44_tmp_n, reg44_ori;
-+	u8 devide_num = 4;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Set Beam Pattern =0x%x\n",
-+		  codeword);
-+
-+	reg44_ori = odm_get_mac_reg(dm, R_0x44, MASKDWORD);
-+	reg44_tmp_p = reg44_ori;
-+#if 0
-+	/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_ori =0x%x\n", reg44_ori);*/
-+#endif
-+
-+	devide_num = (sat_tab->rfu_protocol_type == 2) ? 6 : 4;
-+
-+	for (i = 0; i <= (codeword_length - 1); i++) {
-+		beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i);
-+
-+		if (dm->debug_components & DBG_ANT_DIV) {
-+			if (i == (codeword_length - 1))
-+				pr_debug("%d ]\n", beam_ctrl_signal);
-+			else if (i == 0)
-+				pr_debug("Send codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal);
-+			else if ((i % devide_num) == (devide_num - 1))
-+				pr_debug("%d  |  ", beam_ctrl_signal);
-+			else
-+				pr_debug("%d ", beam_ctrl_signal);
-+		}
-+
-+		if (dm->support_ic_type == ODM_RTL8821) {
-+			#if (RTL8821A_SUPPORT == 1)
-+			reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT(10))); /*@clean bit 10 & 11*/
-+			reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10));
-+			reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10)));
-+
-+#if 0
-+			/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n);*/
-+#endif
-+			odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
-+			odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);
-+			#endif
-+		}
-+		#if (RTL8822B_SUPPORT == 1)
-+		else if (dm->support_ic_type == ODM_RTL8822B) {
-+			if (sat_tab->rfu_protocol_type == 2) {
-+				reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*@clean bit 8*/
-+				reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*@get new clk high/low, exclusive-or*/
-+
-+				reg44_tmp_p |= (beam_ctrl_signal << 8);
-+
-+				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
-+				ODM_delay_us(10);
-+#if 0
-+				/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal);*/
-+#endif
-+
-+			} else {
-+				reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT(8))); /*@clean bit 9 & 8*/
-+				reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8));
-+				reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8)));
-+
-+#if 0
-+				/*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n); */
-+#endif
-+				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p);
-+				ODM_delay_us(10);
-+				odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n);
-+				ODM_delay_us(10);
-+			}
-+		}
-+		#endif
-+	}
-+}
-+
-+void phydm_update_rx_idle_beam(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+	u32 i;
-+
-+	sat_tab->update_beam_codeword = phydm_construct_hl_beam_codeword(dm,
-+									 &sat_tab->rx_idle_beam[0],
-+									 sat_tab->ant_num);
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "Set target beam_pattern codeword = (( 0x%x ))\n",
-+		  sat_tab->update_beam_codeword);
-+
-+	for (i = 0; i < (sat_tab->ant_num); i++)
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[ Update Rx-Idle-Beam ] RxIdleBeam[%d] =%d\n", i,
-+			  sat_tab->rx_idle_beam[i]);
-+
-+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+	if (dm->support_interface == ODM_ITRF_PCIE)
-+		phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
-+#endif
-+#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
-+	if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
-+		odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
-+#if 0
-+	/*odm_stall_execution(1);*/
-+#endif
-+#endif
-+
-+	sat_tab->pre_codeword = sat_tab->update_beam_codeword;
-+}
-+
-+void phydm_hl_smart_ant_debug(
-+	void *dm_void,
-+	char input[][16],
-+	u32 *_used,
-+	char *output,
-+	u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 one = 0x1;
-+	u32 codeword_length = sat_tab->rfu_codeword_total_bit_num;
-+	u32 beam_ctrl_signal, i;
-+	u8 devide_num = 4;
-+
-+	if (dm_value[0] == 1) { /*@fix beam pattern*/
-+
-+		sat_tab->fix_beam_pattern_en = dm_value[1];
-+
-+		if (sat_tab->fix_beam_pattern_en == 1) {
-+			sat_tab->fix_beam_pattern_codeword = dm_value[2];
-+
-+			if (sat_tab->fix_beam_pattern_codeword > (one << codeword_length)) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n",
-+					  sat_tab->fix_beam_pattern_codeword,
-+					  codeword_length);
-+
-+				(sat_tab->fix_beam_pattern_codeword) &= 0xffffff;
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "[ SmartAnt ] Auto modify to (0x%x)\n",
-+					  sat_tab->fix_beam_pattern_codeword);
-+			}
-+
-+			sat_tab->update_beam_codeword = sat_tab->fix_beam_pattern_codeword;
-+
-+			/*@---------------------------------------------------------*/
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "Fix Beam Pattern\n");
-+
-+			devide_num = (sat_tab->rfu_protocol_type == 2) ? 6 : 4;
-+
-+			for (i = 0; i <= (codeword_length - 1); i++) {
-+				beam_ctrl_signal = (boolean)((sat_tab->update_beam_codeword & BIT(i)) >> i);
-+
-+				if (i == (codeword_length - 1))
-+					PDM_SNPF(out_len, used,
-+						 output + used,
-+						 out_len - used,
-+						 "%d]\n",
-+						 beam_ctrl_signal);
-+				else if (i == 0)
-+					PDM_SNPF(out_len, used,
-+						 output + used,
-+						 out_len - used,
-+						 "Send Codeword[1:24] to RFU -> [%d",
-+						 beam_ctrl_signal);
-+				else if ((i % devide_num) == (devide_num - 1))
-+					PDM_SNPF(out_len, used,
-+						 output + used,
-+						 out_len - used, "%d|",
-+						 beam_ctrl_signal);
-+				else
-+					PDM_SNPF(out_len, used,
-+						 output + used,
-+						 out_len - used, "%d",
-+						 beam_ctrl_signal);
-+			}
-+/*@---------------------------------------------------------*/
-+
-+			#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+			if (dm->support_interface == ODM_ITRF_PCIE)
-+				phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
-+			#endif
-+			#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
-+			if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
-+				odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
-+#if 0
-+			/*odm_stall_execution(1);*/
-+#endif
-+			#endif
-+		} else if (sat_tab->fix_beam_pattern_en == 0)
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[ SmartAnt ] Smart Antenna: Enable\n");
-+
-+	} else if (dm_value[0] == 2) { /*set latch time*/
-+
-+		sat_tab->latch_time = dm_value[1];
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ]  latch_time =0x%x\n",
-+			  sat_tab->latch_time);
-+	} else if (dm_value[0] == 3) {
-+		sat_tab->fix_training_num_en = dm_value[1];
-+
-+		if (sat_tab->fix_training_num_en == 1) {
-+			sat_tab->per_beam_training_pkt_num = (u8)dm_value[2];
-+			sat_tab->decision_holding_period = (u8)dm_value[3];
-+
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[SmartAnt][Dbg] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n",
-+				 sat_tab->fix_training_num_en,
-+				 sat_tab->per_beam_training_pkt_num,
-+				 sat_tab->decision_holding_period);
-+
-+		} else if (sat_tab->fix_training_num_en == 0) {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[ SmartAnt ]  AUTO per_beam_training_pkt_num\n");
-+		}
-+	} else if (dm_value[0] == 4) {
-+		if (dm_value[1] == 1) {
-+			sat_tab->ant_num = 1;
-+			sat_tab->first_train_ant = MAIN_ANT;
-+
-+		} else if (dm_value[1] == 2) {
-+			sat_tab->ant_num = 1;
-+			sat_tab->first_train_ant = AUX_ANT;
-+
-+		} else if (dm_value[1] == 3) {
-+			sat_tab->ant_num = 2;
-+			sat_tab->first_train_ant = MAIN_ANT;
-+		}
-+
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "[ SmartAnt ]  Set ant Num = (( %d )), first_train_ant = (( %d ))\n",
-+			 sat_tab->ant_num, (sat_tab->first_train_ant - 1));
-+	} else if (dm_value[0] == 5) {
-+		if (dm_value[1] <= 3) {
-+			sat_tab->rfu_codeword_table[dm_value[1]] = dm_value[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[ SmartAnt ] Set Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n",
-+				 dm_value[1], dm_value[2]);
-+		} else {
-+			for (i = 0; i < 4; i++) {
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used,
-+					 "[ SmartAnt ] Show Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n",
-+					 i, sat_tab->rfu_codeword_table[i]);
-+			}
-+		}
-+	} else if (dm_value[0] == 6) {
-+		if (dm_value[1] <= 3) {
-+			sat_tab->rfu_codeword_table_5g[dm_value[1]] = dm_value[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[ SmartAnt ] Set Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n",
-+				 dm_value[1], dm_value[2]);
-+		} else {
-+			for (i = 0; i < 4; i++) {
-+				PDM_SNPF(out_len, used, output + used,
-+					 out_len - used,
-+					 "[ SmartAnt ] Show Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n",
-+					 i, sat_tab->rfu_codeword_table_5g[i]);
-+			}
-+		}
-+	} else if (dm_value[0] == 7) {
-+		if (dm_value[1] <= 4) {
-+			sat_tab->beam_patten_num_each_ant = dm_value[1];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[ SmartAnt ] Set Beam number = (( %d ))\n",
-+				 sat_tab->beam_patten_num_each_ant);
-+		} else {
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "[ SmartAnt ] Show Beam number = (( %d ))\n",
-+				 sat_tab->beam_patten_num_each_ant);
-+		}
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_set_all_ant_same_beam_num(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+
-+	if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { /*@2ant for 8821A*/
-+
-+		sat_tab->rx_idle_beam[0] = sat_tab->fast_training_beam_num;
-+		sat_tab->rx_idle_beam[1] = sat_tab->fast_training_beam_num;
-+	}
-+
-+	sat_tab->update_beam_codeword = phydm_construct_hl_beam_codeword(dm,
-+									 &sat_tab->rx_idle_beam[0],
-+									 sat_tab->ant_num);
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[ SmartAnt ] Set all ant beam_pattern: codeword = (( 0x%x ))\n",
-+		  sat_tab->update_beam_codeword);
-+
-+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+	if (dm->support_interface == ODM_ITRF_PCIE)
-+		phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
-+#endif
-+#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE
-+	if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO)
-+		odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem);
-+/*odm_stall_execution(1);*/
-+#endif
-+}
-+
-+void odm_fast_ant_training_hl_smart_antenna_type1(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+	struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
-+	struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
-+	u32 codeword = 0, i, j;
-+	u32 target_ant;
-+	u32 avg_rssi_tmp, avg_rssi_tmp_ma;
-+	u32 target_ant_beam_max_rssi[SUPPORT_RF_PATH_NUM] = {0};
-+	u32 max_beam_ant_rssi = 0;
-+	u32 target_ant_beam[SUPPORT_RF_PATH_NUM] = {0};
-+	u32 beam_tmp;
-+	u8 next_ant;
-+	u32 rssi_sorting_seq[SUPPORT_BEAM_PATTERN_NUM] = {0};
-+	u32 rank_idx_seq[SUPPORT_BEAM_PATTERN_NUM] = {0};
-+	u32 rank_idx_out[SUPPORT_BEAM_PATTERN_NUM] = {0};
-+	u8 per_beam_rssi_diff_tmp = 0, training_pkt_num_offset;
-+	u32 break_counter = 0;
-+	u32 used_ant;
-+
-+	if (!dm->is_linked) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
-+
-+		if (fat_tab->is_become_linked == true) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "Link->no Link\n");
-+			fat_tab->fat_state = FAT_BEFORE_LINK_STATE;
-+			odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "change to (( %d )) FAT_state\n",
-+				  fat_tab->fat_state);
-+
-+			fat_tab->is_become_linked = dm->is_linked;
-+		}
-+		return;
-+
-+	} else {
-+		if (fat_tab->is_become_linked == false) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
-+
-+			fat_tab->fat_state = FAT_PREPARE_STATE;
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "change to (( %d )) FAT_state\n",
-+				  fat_tab->fat_state);
-+
-+#if 0
-+			/*sat_tab->fast_training_beam_num = 0;*/
-+			/*phydm_set_all_ant_same_beam_num(dm);*/
-+#endif
-+
-+			fat_tab->is_become_linked = dm->is_linked;
-+		}
-+	}
-+
-+	if (!(*fat_tab->p_force_tx_by_desc)) {
-+		if (dm->is_one_entry_only == true)
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
-+		else
-+			odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
-+	}
-+
-+#if 0
-+	/*PHYDM_DBG(dm, DBG_ANT_DIV, "HL Smart ant Training: state (( %d ))\n", fat_tab->fat_state);*/
-+#endif
-+
-+	/* @[DECISION STATE] */
-+	/*@=======================================================================================*/
-+	if (fat_tab->fat_state == FAT_DECISION_STATE) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[ 3. In Decision state]\n");
-+		phydm_fast_training_enable(dm, FAT_OFF);
-+
-+		break_counter = 0;
-+		/*@compute target beam in each antenna*/
-+		for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) {
-+			for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) {
-+				if (sat_tab->pkt_rssi_cnt[i][j] == 0) {
-+					avg_rssi_tmp = sat_tab->pkt_rssi_pre[i][j];
-+					avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp;
-+					avg_rssi_tmp_ma = avg_rssi_tmp;
-+				} else {
-+					avg_rssi_tmp = (sat_tab->pkt_rssi_sum[i][j]) / (sat_tab->pkt_rssi_cnt[i][j]);
-+					avg_rssi_tmp_ma = (avg_rssi_tmp + sat_tab->pkt_rssi_pre[i][j]) >> 1;
-+				}
-+
-+				rssi_sorting_seq[j] = avg_rssi_tmp;
-+				sat_tab->pkt_rssi_pre[i][j] = avg_rssi_tmp;
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "ant[%d], Beam[%d]: pkt_cnt=(( %d )), avg_rssi_MA=(( %d )), avg_rssi=(( %d ))\n",
-+					  i, j, sat_tab->pkt_rssi_cnt[i][j],
-+					  avg_rssi_tmp_ma, avg_rssi_tmp);
-+
-+				if (avg_rssi_tmp > target_ant_beam_max_rssi[i]) {
-+					target_ant_beam[i] = j;
-+					target_ant_beam_max_rssi[i] = avg_rssi_tmp;
-+				}
-+
-+				/*reset counter value*/
-+				sat_tab->pkt_rssi_sum[i][j] = 0;
-+				sat_tab->pkt_rssi_cnt[i][j] = 0;
-+			}
-+			sat_tab->rx_idle_beam[i] = target_ant_beam[i];
-+			PHYDM_DBG(dm, DBG_ANT_DIV,
-+				  "---------> Target of ant[%d]: Beam_num-(( %d )) RSSI= ((%d))\n",
-+				  i, target_ant_beam[i],
-+				  target_ant_beam_max_rssi[i]);
-+
-+#if 0
-+			/*sorting*/
-+			/*@
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Pre]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3]);
-+			*/
-+
-+			/*phydm_seq_sorting(dm, &rssi_sorting_seq[0], &rank_idx_seq[0], &rank_idx_out[0], SUPPORT_BEAM_PATTERN_NUM);*/
-+
-+			/*@
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3]);
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rank_idx_seq = [%d, %d, %d, %d]\n", rank_idx_seq[0], rank_idx_seq[1], rank_idx_seq[2], rank_idx_seq[3]);
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rank_idx_out = [%d, %d, %d, %d]\n", rank_idx_out[0], rank_idx_out[1], rank_idx_out[2], rank_idx_out[3]);
-+			*/
-+#endif
-+
-+			if (target_ant_beam_max_rssi[i] > max_beam_ant_rssi) {
-+				target_ant = i;
-+				max_beam_ant_rssi = target_ant_beam_max_rssi[i];
-+#if
-+				/*PHYDM_DBG(dm, DBG_ANT_DIV, "Target of ant = (( %d )) max_beam_ant_rssi = (( %d ))\n",
-+					target_ant,  max_beam_ant_rssi);*/
-+#endif
-+			}
-+			break_counter++;
-+			if (break_counter >= sat_tab->ant_num)
-+				break;
-+		}
-+
-+#ifdef CONFIG_FAT_PATCH
-+		break_counter = 0;
-+		for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) {
-+			for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) {
-+				per_beam_rssi_diff_tmp = (u8)(max_beam_ant_rssi - sat_tab->pkt_rssi_pre[i][j]);
-+				sat_tab->beam_train_rssi_diff[i][j] = per_beam_rssi_diff_tmp;
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "ant[%d], Beam[%d]: RSSI_diff= ((%d))\n",
-+					  i, j, per_beam_rssi_diff_tmp);
-+			}
-+			break_counter++;
-+			if (break_counter >= sat_tab->ant_num)
-+				break;
-+		}
-+#endif
-+
-+		if (target_ant == 0)
-+			target_ant = MAIN_ANT;
-+		else if (target_ant == 1)
-+			target_ant = AUX_ANT;
-+
-+		if (sat_tab->ant_num > 1) {
-+			/* @[ update RX ant ]*/
-+			odm_update_rx_idle_ant(dm, (u8)target_ant);
-+
-+			/* @[ update TX ant ]*/
-+			odm_update_tx_ant(dm, (u8)target_ant, (fat_tab->train_idx));
-+		}
-+
-+		/*set beam in each antenna*/
-+		phydm_update_rx_idle_beam(dm);
-+
-+		odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
-+		fat_tab->fat_state = FAT_PREPARE_STATE;
-+		return;
-+	}
-+	/* @[TRAINING STATE] */
-+	else if (fat_tab->fat_state == FAT_TRAINING_STATE) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2. In Training state]\n");
-+
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "fat_beam_n = (( %d )), pre_fat_beam_n = (( %d ))\n",
-+			  sat_tab->fast_training_beam_num,
-+			  sat_tab->pre_fast_training_beam_num);
-+
-+		if (sat_tab->fast_training_beam_num > sat_tab->pre_fast_training_beam_num)
-+
-+			sat_tab->force_update_beam_en = 0;
-+
-+		else {
-+			sat_tab->force_update_beam_en = 1;
-+
-+			sat_tab->pkt_counter = 0;
-+			beam_tmp = sat_tab->fast_training_beam_num;
-+			if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "[Timeout Update]  Beam_num (( %d )) -> (( decision ))\n",
-+					  sat_tab->fast_training_beam_num);
-+				fat_tab->fat_state = FAT_DECISION_STATE;
-+				odm_fast_ant_training_hl_smart_antenna_type1(dm);
-+
-+			} else {
-+				sat_tab->fast_training_beam_num++;
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "[Timeout Update]  Beam_num (( %d )) -> (( %d ))\n",
-+					  beam_tmp,
-+					  sat_tab->fast_training_beam_num);
-+				phydm_set_all_ant_same_beam_num(dm);
-+				fat_tab->fat_state = FAT_TRAINING_STATE;
-+			}
-+		}
-+		sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "[prepare state] Update Pre_Beam =(( %d ))\n",
-+			  sat_tab->pre_fast_training_beam_num);
-+	}
-+	/*  @[Prepare state] */
-+	/*@=======================================================================================*/
-+	else if (fat_tab->fat_state == FAT_PREPARE_STATE) {
-+		PHYDM_DBG(dm, DBG_ANT_DIV, "\n\n[ 1. In Prepare state]\n");
-+
-+		if (dm->pre_traffic_load == dm->traffic_load) {
-+			if (sat_tab->decision_holding_period != 0) {
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "Holding_period = (( %d )), return!!!\n",
-+					  sat_tab->decision_holding_period);
-+				sat_tab->decision_holding_period--;
-+				return;
-+			}
-+		}
-+
-+		/* Set training packet number*/
-+		if (sat_tab->fix_training_num_en == 0) {
-+			switch (dm->traffic_load) {
-+			case TRAFFIC_HIGH:
-+				sat_tab->per_beam_training_pkt_num = 8;
-+				sat_tab->decision_holding_period = 2;
-+				break;
-+			case TRAFFIC_MID:
-+				sat_tab->per_beam_training_pkt_num = 6;
-+				sat_tab->decision_holding_period = 3;
-+				break;
-+			case TRAFFIC_LOW:
-+				sat_tab->per_beam_training_pkt_num = 3; /*ping 60000*/
-+				sat_tab->decision_holding_period = 4;
-+				break;
-+			case TRAFFIC_ULTRA_LOW:
-+				sat_tab->per_beam_training_pkt_num = 1;
-+				sat_tab->decision_holding_period = 6;
-+				break;
-+			default:
-+				break;
-+			}
-+		}
-+		PHYDM_DBG(dm, DBG_ANT_DIV,
-+			  "Fix_training_en = (( %d )), training_pkt_num_base = (( %d )), holding_period = ((%d))\n",
-+			  sat_tab->fix_training_num_en,
-+			  sat_tab->per_beam_training_pkt_num,
-+			  sat_tab->decision_holding_period);
-+
-+#ifdef CONFIG_FAT_PATCH
-+		break_counter = 0;
-+		for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) {
-+			for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) {
-+				per_beam_rssi_diff_tmp = sat_tab->beam_train_rssi_diff[i][j];
-+				training_pkt_num_offset = per_beam_rssi_diff_tmp;
-+
-+				if (sat_tab->per_beam_training_pkt_num > training_pkt_num_offset)
-+					sat_tab->beam_train_cnt[i][j] = sat_tab->per_beam_training_pkt_num - training_pkt_num_offset;
-+				else
-+					sat_tab->beam_train_cnt[i][j] = 1;
-+
-+				PHYDM_DBG(dm, DBG_ANT_DIV,
-+					  "ant[%d]: Beam_num-(( %d ))  training_pkt_num = ((%d))\n",
-+					  i, j, sat_tab->beam_train_cnt[i][j]);
-+			}
-+			break_counter++;
-+			if (break_counter >= sat_tab->ant_num)
-+				break;
-+		}
-+
-+		phydm_fast_training_enable(dm, FAT_OFF);
-+		sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
-+		sat_tab->update_beam_idx = 0;
-+
-+		if (*dm->band_type == ODM_BAND_5G) {
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "Set 5G ant\n");
-+			/*used_ant = (sat_tab->first_train_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;*/
-+			used_ant = sat_tab->first_train_ant;
-+		} else {
-+			PHYDM_DBG(dm, DBG_ANT_DIV, "Set 2.4G ant\n");
-+			used_ant = sat_tab->first_train_ant;
-+		}
-+
-+		odm_update_rx_idle_ant(dm, (u8)used_ant);
-+
-+#else
-+		/* Set training MAC addr. of target */
-+		odm_set_next_mac_addr_target(dm);
-+		phydm_fast_training_enable(dm, FAT_ON);
-+#endif
-+
-+		odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
-+		sat_tab->pkt_counter = 0;
-+		sat_tab->fast_training_beam_num = 0;
-+		phydm_set_all_ant_same_beam_num(dm);
-+		sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num;
-+		fat_tab->fat_state = FAT_TRAINING_STATE;
-+	}
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+void phydm_beam_switch_workitem_callback(
-+	void *context)
-+{
-+	void *adapter = (void *)context;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+	struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
-+
-+#if DEV_BUS_TYPE != RT_PCI_INTERFACE
-+	sat_tab->pkt_skip_statistic_en = 1;
-+#endif
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n",
-+		  sat_tab->pkt_skip_statistic_en);
-+
-+	phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num);
-+
-+#if DEV_BUS_TYPE != RT_PCI_INTERFACE
-+#if 0
-+	/*odm_stall_execution(sat_tab->latch_time);*/
-+#endif
-+	sat_tab->pkt_skip_statistic_en = 0;
-+#endif
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n",
-+		  sat_tab->pkt_skip_statistic_en, sat_tab->latch_time);
-+}
-+
-+void phydm_beam_decision_workitem_callback(
-+	void *context)
-+{
-+	void *adapter = (void *)context;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+
-+	PHYDM_DBG(dm, DBG_ANT_DIV,
-+		  "[ SmartAnt ] Beam decision Workitem Callback\n");
-+	odm_fast_ant_training_hl_smart_antenna_type1(dm);
-+}
-+#endif
-+
-+#endif /*@#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/
-+
-+#endif /*@#ifdef CONFIG_HL_SMART_ANTENNA*/
-+
-+void phydm_smt_ant_config(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant *smtant_table = &dm->smtant_table;
-+
-+#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
-+
-+	dm->support_ability |= ODM_BB_SMT_ANT;
-+	smtant_table->smt_ant_vendor = SMTANT_CUMITEK;
-+	smtant_table->smt_ant_type = 1;
-+#if (RTL8822B_SUPPORT == 1)
-+	dm->rfe_type = SMTANT_TMP_RFE_TYPE;
-+#endif
-+#elif (defined(CONFIG_HL_SMART_ANTENNA))
-+
-+	dm->support_ability |= ODM_BB_SMT_ANT;
-+	smtant_table->smt_ant_vendor = SMTANT_HON_BO;
-+
-+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
-+	smtant_table->smt_ant_type = 1;
-+#endif
-+
-+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
-+	smtant_table->smt_ant_type = 2;
-+#endif
-+#endif
-+
-+	PHYDM_DBG(dm, DBG_SMT_ANT,
-+		  "[SmtAnt Config] Vendor=((%d)), Smt_ant_type =((%d))\n",
-+		  smtant_table->smt_ant_vendor, smtant_table->smt_ant_type);
-+}
-+
-+void phydm_smt_ant_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct smt_ant *smtant_table = &dm->smtant_table;
-+
-+	phydm_smt_ant_config(dm);
-+
-+	if (smtant_table->smt_ant_vendor == SMTANT_CUMITEK) {
-+#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
-+#if (RTL8822B_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8822B)
-+			phydm_cumitek_smt_ant_init_8822b(dm);
-+#endif
-+
-+#if (RTL8197F_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8197F)
-+			phydm_cumitek_smt_ant_init_8197f(dm);
-+#endif
-+/*@jj add 20170822*/
-+#if (RTL8192F_SUPPORT == 1)
-+		if (dm->support_ic_type == ODM_RTL8192F)
-+			phydm_cumitek_smt_ant_init_8192f(dm);
-+#endif
-+#endif /*@#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))*/
-+
-+	} else if (smtant_table->smt_ant_vendor == SMTANT_HON_BO) {
-+#if (defined(CONFIG_HL_SMART_ANTENNA))
-+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
-+		if (dm->support_ic_type == ODM_RTL8821)
-+			phydm_hl_smart_ant_type1_init_8821a(dm);
-+#endif
-+
-+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
-+		if (dm->support_ic_type == ODM_RTL8822B)
-+			phydm_hl_smart_ant_type2_init_8822b(dm);
-+#endif
-+#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/
-+	}
-+}
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_smt_ant.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_smt_ant.h
-new file mode 100644
-index 000000000000..3a408c4c69e2
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_smt_ant.h
-@@ -0,0 +1,210 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __PHYDMSMTANT_H__
-+#define __PHYDMSMTANT_H__
-+
-+/*@#define SMT_ANT_VERSION	"1.1"*/ /*@2017.03.13*/
-+/*@#define SMT_ANT_VERSION	"1.2"*/ /*@2017.03.28*/
-+#define SMT_ANT_VERSION "2.0" /* @Add Cumitek SmtAnt 2017.05.25*/
-+
-+#define	SMTANT_RTK		1
-+#define	SMTANT_HON_BO	2
-+#define	SMTANT_CUMITEK	3
-+
-+#if (defined(CONFIG_SMART_ANTENNA))
-+
-+#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
-+struct smt_ant_cumitek {
-+	u8	tx_ant_idx[2][ODM_ASSOCIATE_ENTRY_NUM]; /*@[pathA~B] [MACID 0~128]*/
-+	u8	rx_default_ant_idx[2]; /*@[pathA~B]*/
-+};
-+#endif
-+
-+#if (defined(CONFIG_HL_SMART_ANTENNA))
-+struct smt_ant_honbo {
-+	u32	latch_time;
-+	boolean	pkt_skip_statistic_en;
-+	u32	fix_beam_pattern_en;
-+	u32	fix_training_num_en;
-+	u32	fix_beam_pattern_codeword;
-+	u32	update_beam_codeword;
-+	u32	ant_num; /*number of "used" smart beam antenna*/
-+	u32	ant_num_total;/*number of "total" smart beam antenna*/
-+	u32	first_train_ant; /*@decide witch antenna to train first*/
-+
-+	#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
-+	u32	pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];/*@rssi of each path with a certain beam pattern*/
-+	u8	beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
-+	u8	beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
-+	u32	rfu_codeword_table[4]; /*@2G beam truth table*/
-+	u32	rfu_codeword_table_5g[4]; /*@5G beam truth table*/
-+	u32	beam_patten_num_each_ant;/*@number of  beam can be switched in each antenna*/
-+	u32	rx_idle_beam[SUPPORT_RF_PATH_NUM];
-+	u32	pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM];
-+	u32	pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM];
-+	#endif
-+
-+	u32	fast_training_beam_num;/*@current training beam_set index*/
-+	u32	pre_fast_training_beam_num;/*pre training beam_set index*/
-+	u32	rfu_codeword_total_bit_num; /* @total bit number of RFU protocol*/
-+	u32	rfu_each_ant_bit_num; /* @bit number of RFU protocol for each ant*/
-+	u8	per_beam_training_pkt_num;
-+	u8	decision_holding_period;
-+
-+
-+	u32	pre_codeword;
-+	boolean	force_update_beam_en;
-+	u32	beacon_counter;
-+	u32	pre_beacon_counter;
-+	u8	pkt_counter;		/*@packet number that each beam-set should be colected in training state*/
-+	u8	update_beam_idx;	/*@the index announce that the beam can be updated*/
-+	u8	rfu_protocol_type;
-+	u16	rfu_protocol_delay_time;
-+
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	RT_WORK_ITEM	hl_smart_antenna_workitem;
-+	RT_WORK_ITEM	hl_smart_antenna_decision_workitem;
-+	#endif
-+
-+
-+	#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
-+	u8	beam_set_avg_rssi_pre[SUPPORT_BEAM_SET_PATTERN_NUM];		/*@avg pre_rssi of each beam set*/
-+	u8	beam_set_train_val_diff[SUPPORT_BEAM_SET_PATTERN_NUM];	/*@rssi of a beam pattern set, ex: a set = {ant1_beam=1, ant2_beam=3}*/
-+	u8	beam_set_train_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];			/*@training pkt num of each beam set*/
-+	u32	beam_set_rssi_avg_sum[SUPPORT_BEAM_SET_PATTERN_NUM];			/*@RSSI_sum of avg(pathA,pathB) for each beam-set)*/
-+	u32	beam_path_rssi_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*@RSSI_sum of each path for each beam-set)*/
-+
-+	u8	beam_set_avg_evm_2ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM];
-+	u32	beam_path_evm_2ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*@2SS evm_sum of each path for each beam-set)*/
-+	u32	beam_path_evm_2ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];
-+
-+	u8	beam_set_avg_evm_1ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM];
-+	u32	beam_path_evm_1ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM];/*@1SS evm_sum of each path for each beam-set)*/
-+	u32	beam_path_evm_1ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];
-+
-+	u32	statistic_pkt_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];				/*@statistic_pkt_cnt for SmtAnt make decision*/
-+
-+	u8	total_beam_set_num;	/*@number of  beam set can be switched*/
-+	u8	total_beam_set_num_2g;/*@number of  beam set can be switched in 2G*/
-+	u8	total_beam_set_num_5g;/*@number of  beam set can be switched in 5G*/
-+
-+	u8	rfu_codeword_table_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*@2G beam truth table*/
-+	u8	rfu_codeword_table_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*@5G beam truth table*/
-+	u8	rx_idle_beam_set_idx;	/*the filanl decsion result*/
-+	#endif
-+
-+
-+};
-+#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/
-+
-+struct smt_ant {
-+	u8	smt_ant_vendor;
-+	u8	smt_ant_type;
-+	u8	tx_desc_mode; /*@0:3 bit mode, 1:2 bit mode*/
-+	#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
-+	struct	smt_ant_cumitek	cumi_smtant_table;
-+	#endif
-+};
-+
-+#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
-+void phydm_cumitek_smt_tx_ant_update(
-+	void *dm_void,
-+	u8 tx_ant_idx_path_a,
-+	u8 tx_ant_idx_path_b,
-+	u32 mac_id);
-+
-+void phydm_cumitek_smt_rx_default_ant_update(
-+	void *dm_void,
-+	u8 rx_ant_idx_path_a,
-+	u8 rx_ant_idx_path_b);
-+
-+void phydm_cumitek_smt_ant_debug(
-+	void *dm_void,
-+	char input[][16],
-+	u32 *_used,
-+	char *output,
-+	u32 *_out_len);
-+
-+#endif
-+
-+#if (defined(CONFIG_HL_SMART_ANTENNA))
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void phydm_beam_switch_workitem_callback(
-+	void *context);
-+
-+void phydm_beam_decision_workitem_callback(
-+	void *context);
-+#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
-+
-+#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
-+void phydm_hl_smart_ant_type2_init_8822b(
-+	void *dm_void);
-+
-+void phydm_update_beam_pattern_type2(
-+	void *dm_void,
-+	u32 codeword,
-+	u32 codeword_length);
-+
-+void phydm_set_rfu_beam_pattern_type2(
-+	void *dm_void);
-+
-+void phydm_hl_smt_ant_dbg_type2(
-+	void *dm_void,
-+	char input[][16],
-+	u32 *_used,
-+	char *output,
-+	u32 *_out_len);
-+
-+void phydm_process_rssi_for_hb_smtant_type2(
-+	void *dm_void,
-+	void *phy_info_void,
-+	void *pkt_info_void,
-+	u8 rssi_avg);
-+
-+#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))*/
-+
-+#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))
-+
-+void phydm_update_beam_pattern(
-+	void *dm_void,
-+	u32 codeword,
-+	u32 codeword_length);
-+
-+void phydm_set_all_ant_same_beam_num(
-+	void *dm_void);
-+
-+void phydm_hl_smart_ant_debug(
-+	void *dm_void,
-+	char input[][16],
-+	u32 *_used,
-+	char *output,
-+	u32 *_out_len);
-+
-+#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))*/
-+#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/
-+void phydm_smt_ant_init(void *dm_void);
-+#endif /*@#if (defined(CONFIG_SMART_ANTENNA))*/
-+#endif
-\ No newline at end of file
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_soml.c b/drivers/staging/rtl8723cs/hal/phydm/phydm_soml.c
-new file mode 100644
-index 000000000000..cd4001afd0cf
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_soml.c
-@@ -0,0 +1,1451 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+
-+/*************************************************************
-+ * include files
-+ ************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#ifdef CONFIG_ADAPTIVE_SOML
-+
-+void phydm_dynamicsoftmletting(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 ret_val;
-+
-+#if (RTL8822B_SUPPORT == 1)
-+	if (!*dm->mp_mode) {
-+		if (dm->support_ic_type & ODM_RTL8822B) {
-+			if (!dm->is_linked | dm->iot_table.is_linked_cmw500)
-+				return;
-+
-+			if (dm->bsomlenabled) {
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "PHYDM_DynamicSoftMLSetting(): SoML has been enable, skip dynamic SoML switch\n");
-+				return;
-+			}
-+
-+			ret_val = odm_get_bb_reg(dm, R_0xf8c, MASKBYTE0);
-+			PHYDM_DBG(dm, ODM_COMP_API,
-+				  "PHYDM_DynamicSoftMLSetting(): Read 0xF8C = 0x%08X\n",
-+				  ret_val);
-+
-+			if (ret_val < 0x16) {
-+				PHYDM_DBG(dm, ODM_COMP_API,
-+					  "PHYDM_DynamicSoftMLSetting(): 0xF8C(== 0x%08X) < 0x16, enable SoML\n",
-+					  ret_val);
-+				phydm_somlrxhp_setting(dm, true);
-+#if 0
-+			/*odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xc10a0000);*/
-+#endif
-+				dm->bsomlenabled = true;
-+			}
-+		}
-+	}
-+#endif
-+}
-+
-+void phydm_soml_on_off(void *dm_void, u8 swch)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+
-+	if (swch == SOML_ON) {
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML, "(( Turn on )) SOML\n");
-+
-+		if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
-+			odm_set_bb_reg(dm, R_0x998, BIT(6), swch);
-+#if (RTL8822B_SUPPORT == 1)
-+		else if (dm->support_ic_type == ODM_RTL8822B)
-+			phydm_somlrxhp_setting(dm, true);
-+#endif
-+
-+	} else if (swch == SOML_OFF) {
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML, "(( Turn off )) SOML\n");
-+
-+		if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
-+			odm_set_bb_reg(dm, R_0x998, BIT(6), swch);
-+#if (RTL8822B_SUPPORT == 1)
-+		else if (dm->support_ic_type == ODM_RTL8822B)
-+			phydm_somlrxhp_setting(dm, false);
-+#endif
-+	}
-+	soml_tab->soml_on_off = swch;
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void phydm_adaptive_soml_callback(struct phydm_timer_list *timer)
-+{
-+	void *adapter = (void *)timer->Adapter;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+
-+	#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+	#if USE_WORKITEM
-+	odm_schedule_work_item(&soml_tab->phydm_adaptive_soml_workitem);
-+	#else
-+	{
-+#if 0
-+		/*@dbg_print("%s\n",__func__);*/
-+#endif
-+		phydm_adsl(dm);
-+	}
-+	#endif
-+	#else
-+	odm_schedule_work_item(&soml_tab->phydm_adaptive_soml_workitem);
-+	#endif
-+}
-+
-+void phydm_adaptive_soml_workitem_callback(void *context)
-+{
-+#ifdef CONFIG_ADAPTIVE_SOML
-+	void *adapter = (void *)context;
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+
-+#if 0
-+	/*@dbg_print("%s\n",__func__);*/
-+#endif
-+	phydm_adsl(dm);
-+#endif
-+}
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+void phydm_adaptive_soml_callback(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	void *padapter = dm->adapter;
-+
-+	if (*dm->is_net_closed == true)
-+		return;
-+	if (dm->support_interface == ODM_ITRF_PCIE)
-+		phydm_adsl(dm);
-+	else {
-+		/* @Can't do I/O in timer callback*/
-+		phydm_run_in_thread_cmd(dm,
-+					phydm_adaptive_soml_workitem_callback,
-+					dm);
-+	}
-+}
-+
-+void phydm_adaptive_soml_workitem_callback(void *context)
-+{
-+	struct dm_struct *dm = (void *)context;
-+
-+#if 0
-+	/*@dbg_print("%s\n",__func__);*/
-+#endif
-+	phydm_adsl(dm);
-+}
-+
-+#else
-+void phydm_adaptive_soml_callback(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ADPTV_SOML, "******SOML_Callback******\n");
-+	phydm_adsl(dm);
-+}
-+#endif
-+
-+void phydm_rx_rate_for_soml(void *dm_void, void *pkt_info_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	struct phydm_perpkt_info_struct *pktinfo = NULL;
-+	u8 data_rate;
-+
-+	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
-+	data_rate = (pktinfo->data_rate & 0x7f);
-+
-+	if (pktinfo->data_rate >= ODM_RATEMCS0 &&
-+	    pktinfo->data_rate <= ODM_RATEMCS31)
-+		soml_tab->ht_cnt[data_rate - ODM_RATEMCS0]++;
-+	else if ((pktinfo->data_rate >= ODM_RATEVHTSS1MCS0) &&
-+		 (pktinfo->data_rate <= ODM_RATEVHTSS4MCS9))
-+		soml_tab->vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++;
-+}
-+
-+void phydm_rx_qam_for_soml(void *dm_void, void *pkt_info_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	struct phydm_perpkt_info_struct *pktinfo = NULL;
-+	u8 date_rate;
-+
-+	pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
-+	date_rate = (pktinfo->data_rate & 0x7f);
-+	if (soml_tab->soml_state_cnt < (soml_tab->soml_train_num << 1)) {
-+		if (soml_tab->soml_on_off == SOML_ON) {
-+			return;
-+		} else if (soml_tab->soml_on_off == SOML_OFF) {
-+			if (date_rate >= ODM_RATEMCS8 &&
-+			    date_rate <= ODM_RATEMCS10)
-+				soml_tab->num_ht_qam[BPSK_QPSK]++;
-+
-+			else if ((date_rate >= ODM_RATEMCS11) &&
-+				 (date_rate <= ODM_RATEMCS12))
-+				soml_tab->num_ht_qam[QAM16]++;
-+
-+			else if ((date_rate >= ODM_RATEMCS13) &&
-+				 (date_rate <= ODM_RATEMCS15))
-+				soml_tab->num_ht_qam[QAM64]++;
-+
-+			else if ((date_rate >= ODM_RATEVHTSS2MCS0) &&
-+				 (date_rate <= ODM_RATEVHTSS2MCS2))
-+				soml_tab->num_vht_qam[BPSK_QPSK]++;
-+
-+			else if ((date_rate >= ODM_RATEVHTSS2MCS3) &&
-+				 (date_rate <= ODM_RATEVHTSS2MCS4))
-+				soml_tab->num_vht_qam[QAM16]++;
-+
-+			else if ((date_rate >= ODM_RATEVHTSS2MCS5) &&
-+				 (date_rate <= ODM_RATEVHTSS2MCS5))
-+				soml_tab->num_vht_qam[QAM64]++;
-+
-+			else if ((date_rate >= ODM_RATEVHTSS2MCS8) &&
-+				 (date_rate <= ODM_RATEVHTSS2MCS9))
-+				soml_tab->num_vht_qam[QAM256]++;
-+		}
-+	}
-+}
-+
-+void phydm_soml_reset_rx_rate(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	u8 order;
-+
-+	for (order = 0; order < HT_RATE_IDX; order++) {
-+		soml_tab->ht_cnt[order] = 0;
-+		soml_tab->pre_ht_cnt[order] = 0;
-+		soml_tab->ht_cnt_on[order] = 0;
-+		soml_tab->ht_cnt_off[order] = 0;
-+		soml_tab->ht_crc_ok_cnt_on[order] = 0;
-+		soml_tab->ht_crc_fail_cnt_on[order] = 0;
-+		soml_tab->ht_crc_ok_cnt_off[order] = 0;
-+		soml_tab->ht_crc_fail_cnt_off[order] = 0;
-+	}
-+
-+	for (order = 0; order < VHT_RATE_IDX; order++) {
-+		soml_tab->vht_cnt[order] = 0;
-+		soml_tab->pre_vht_cnt[order] = 0;
-+		soml_tab->vht_cnt_on[order] = 0;
-+		soml_tab->vht_cnt_off[order] = 0;
-+		soml_tab->vht_crc_ok_cnt_on[order] = 0;
-+		soml_tab->vht_crc_fail_cnt_on[order] = 0;
-+		soml_tab->vht_crc_ok_cnt_off[order] = 0;
-+		soml_tab->vht_crc_fail_cnt_off[order] = 0;
-+	}
-+}
-+
-+void phydm_soml_reset_qam(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	u8 order;
-+
-+	for (order = 0; order < HT_ORDER_TYPE; order++)
-+		soml_tab->num_ht_qam[order] = 0;
-+
-+	for (order = 0; order < VHT_ORDER_TYPE; order++)
-+		soml_tab->num_vht_qam[order] = 0;
-+}
-+
-+void phydm_soml_cfo_process(void *dm_void, s32 *diff_a, s32 *diff_b)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 value32, value32_1, value32_2, value32_3;
-+	s32 cfo_acq_a, cfo_acq_b, cfo_end_a, cfo_end_b;
-+
-+	value32 = odm_get_bb_reg(dm, R_0xd10, MASKDWORD);
-+	value32_1 = odm_get_bb_reg(dm, R_0xd14, MASKDWORD);
-+	value32_2 = odm_get_bb_reg(dm, R_0xd50, MASKDWORD);
-+	value32_3 = odm_get_bb_reg(dm, R_0xd54, MASKDWORD);
-+
-+	cfo_acq_a = (s32)((value32 & 0x1fff0000) >> 16);
-+	cfo_end_a = (s32)((value32_1 & 0x1fff0000) >> 16);
-+	cfo_acq_b = (s32)((value32_2 & 0x1fff0000) >> 16);
-+	cfo_end_b = (s32)((value32_3 & 0x1fff0000) >> 16);
-+
-+	*diff_a = ((cfo_acq_a >= cfo_end_a) ? (cfo_acq_a - cfo_end_a) :
-+		  (cfo_end_a - cfo_acq_a));
-+	*diff_b = ((cfo_acq_b >= cfo_end_b) ? (cfo_acq_b - cfo_end_b) :
-+		  (cfo_end_b - cfo_acq_b));
-+
-+	*diff_a = ((*diff_a * 312) + (*diff_a >> 1)) >> 12; /* @312.5/2^12 */
-+	*diff_b = ((*diff_b * 312) + (*diff_b >> 1)) >> 12; /* @312.5/2^12 */
-+}
-+
-+void phydm_soml_debug(void *dm_void, char input[][16], u32 *_used,
-+		      char *output, u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	u32 used = *_used;
-+	u32 out_len = *_out_len;
-+	u32 dm_value[10] = {0};
-+	u8 i = 0, input_idx = 0;
-+
-+	if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML))
-+		return;
-+
-+	for (i = 0; i < 5; i++) {
-+		if (input[i + 1]) {
-+			PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
-+			input_idx++;
-+		}
-+	}
-+
-+	if (input_idx == 0)
-+		return;
-+
-+	if (dm_value[0] == 1) { /*Turn on/off SOML*/
-+		soml_tab->soml_select = (u8)dm_value[1];
-+
-+	} else if (dm_value[0] == 2) { /*training number for SOML*/
-+
-+		soml_tab->soml_train_num = (u8)dm_value[1];
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "soml_train_num = ((%d))\n",
-+			 soml_tab->soml_train_num);
-+	} else if (dm_value[0] == 3) { /*training interval for SOML*/
-+
-+		soml_tab->soml_intvl = (u8)dm_value[1];
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "soml_intvl = ((%d))\n", soml_tab->soml_intvl);
-+	} else if (dm_value[0] == 4) { /*@function period for SOML*/
-+
-+		soml_tab->soml_period = (u8)dm_value[1];
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "soml_period = ((%d))\n", soml_tab->soml_period);
-+	} else if (dm_value[0] == 5) { /*@delay_time for SOML*/
-+
-+		soml_tab->soml_delay_time = (u8)dm_value[1];
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "soml_delay_time = ((%d))\n",
-+			 soml_tab->soml_delay_time);
-+	} else if (dm_value[0] == 6) { /* @for SOML Rx QAM distribution th*/
-+		if (dm_value[1] == 256) {
-+			soml_tab->qam256_dist_th = (u8)dm_value[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "qam256_dist_th = ((%d))\n",
-+				 soml_tab->qam256_dist_th);
-+		} else if (dm_value[1] == 64) {
-+			soml_tab->qam64_dist_th = (u8)dm_value[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "qam64_dist_th = ((%d))\n",
-+				 soml_tab->qam64_dist_th);
-+		} else if (dm_value[1] == 16) {
-+			soml_tab->qam16_dist_th = (u8)dm_value[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "qam16_dist_th = ((%d))\n",
-+				 soml_tab->qam16_dist_th);
-+		} else if (dm_value[1] == 4) {
-+			soml_tab->bpsk_qpsk_dist_th = (u8)dm_value[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "bpsk_qpsk_dist_th = ((%d))\n",
-+				 soml_tab->bpsk_qpsk_dist_th);
-+		}
-+	} else if (dm_value[0] == 7) { /* @for SOML cfo th*/
-+		if (dm_value[1] == 256) {
-+			soml_tab->cfo_qam256_th = (u8)dm_value[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "cfo_qam256_th = ((%d KHz))\n",
-+				 soml_tab->cfo_qam256_th);
-+		} else if (dm_value[1] == 64) {
-+			soml_tab->cfo_qam64_th = (u8)dm_value[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "cfo_qam64_th = ((%d KHz))\n",
-+				 soml_tab->cfo_qam64_th);
-+		} else if (dm_value[1] == 16) {
-+			soml_tab->cfo_qam16_th = (u8)dm_value[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "cfo_qam16_th = ((%d KHz))\n",
-+				 soml_tab->cfo_qam16_th);
-+		} else if (dm_value[1] == 4) {
-+			soml_tab->cfo_qpsk_th = (u8)dm_value[2];
-+			PDM_SNPF(out_len, used, output + used, out_len - used,
-+				 "cfo_qpsk_th = ((%d KHz))\n",
-+				 soml_tab->cfo_qpsk_th);
-+		}
-+	} else if (dm_value[0] == 100) {
-+		/*show parameters*/
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "soml_select = ((%d))\n", soml_tab->soml_select);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "soml_train_num = ((%d))\n",
-+			 soml_tab->soml_train_num);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "soml_intvl = ((%d))\n", soml_tab->soml_intvl);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "soml_period = ((%d))\n", soml_tab->soml_period);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "soml_delay_time = ((%d))\n\n",
-+			 soml_tab->soml_delay_time);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "qam256_dist_th = ((%d)),  qam64_dist_th = ((%d)), ",
-+			 soml_tab->qam256_dist_th,
-+			 soml_tab->qam64_dist_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "qam16_dist_th = ((%d)),  bpsk_qpsk_dist_th = ((%d))\n",
-+			 soml_tab->qam16_dist_th,
-+			 soml_tab->bpsk_qpsk_dist_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "cfo_qam256_th = ((%d KHz)),  cfo_qam64_th = ((%d KHz)), ",
-+			 soml_tab->cfo_qam256_th,
-+			 soml_tab->cfo_qam64_th);
-+		PDM_SNPF(out_len, used, output + used, out_len - used,
-+			 "cfo_qam16_th = ((%d KHz)),  cfo_qpsk_th  = ((%d KHz))\n",
-+			 soml_tab->cfo_qam16_th,
-+			 soml_tab->cfo_qpsk_th);
-+	}
-+	*_used = used;
-+	*_out_len = out_len;
-+}
-+
-+void phydm_soml_stats_ht_on(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	u8 i, mcs0;
-+	u16 num_bytes_diff, num_rate_diff;
-+
-+	mcs0 = ODM_RATEMCS0;
-+	for (i = mcs0; i <= ODM_RATEMCS15; i++) {
-+		num_rate_diff = soml_tab->ht_cnt[i - mcs0] -
-+				soml_tab->pre_ht_cnt[i - mcs0];
-+		soml_tab->ht_cnt_on[i - mcs0] += num_rate_diff;
-+		soml_tab->pre_ht_cnt[i - mcs0] = soml_tab->ht_cnt[i - mcs0];
-+		num_bytes_diff = soml_tab->ht_byte[i - mcs0] -
-+				 soml_tab->pre_ht_byte[i - mcs0];
-+		soml_tab->ht_byte_on[i - mcs0] += num_bytes_diff;
-+		soml_tab->pre_ht_byte[i - mcs0] = soml_tab->ht_byte[i - mcs0];
-+	}
-+}
-+
-+void phydm_soml_stats_ht_off(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	u8 i, mcs0;
-+	u16 num_bytes_diff, num_rate_diff;
-+
-+	mcs0 = ODM_RATEMCS0;
-+	for (i = mcs0; i <= ODM_RATEMCS15; i++) {
-+		num_rate_diff = soml_tab->ht_cnt[i - mcs0] -
-+				soml_tab->pre_ht_cnt[i - mcs0];
-+		soml_tab->ht_cnt_off[i - mcs0] += num_rate_diff;
-+		soml_tab->pre_ht_cnt[i - mcs0] = soml_tab->ht_cnt[i - mcs0];
-+		num_bytes_diff = soml_tab->ht_byte[i - mcs0] -
-+				 soml_tab->pre_ht_byte[i - mcs0];
-+		soml_tab->ht_byte_off[i - mcs0] += num_bytes_diff;
-+		soml_tab->pre_ht_byte[i - mcs0] = soml_tab->ht_byte[i - mcs0];
-+	}
-+}
-+
-+void phydm_soml_stats_vht_on(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	u8 j, vht0;
-+	u16 num_bytes_diff, num_rate_diff;
-+
-+	vht0 = ODM_RATEVHTSS1MCS0;
-+	for (j = vht0; j <= ODM_RATEVHTSS2MCS9; j++) {
-+		num_rate_diff = soml_tab->vht_cnt[j - vht0] -
-+				soml_tab->pre_vht_cnt[j - vht0];
-+		soml_tab->vht_cnt_on[j - vht0] += num_rate_diff;
-+		soml_tab->pre_vht_cnt[j - vht0] = soml_tab->vht_cnt[j - vht0];
-+		num_bytes_diff = soml_tab->vht_byte[j - vht0] -
-+				 soml_tab->pre_vht_byte[j - vht0];
-+		soml_tab->vht_byte_on[j - vht0] += num_bytes_diff;
-+		soml_tab->pre_vht_byte[j - vht0] = soml_tab->vht_byte[j - vht0];
-+	}
-+}
-+
-+void phydm_soml_stats_vht_off(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	u8 j, vht0;
-+	u16 num_bytes_diff, num_rate_diff;
-+
-+	vht0 = ODM_RATEVHTSS1MCS0;
-+	for (j = vht0; j <= ODM_RATEVHTSS2MCS9; j++) {
-+		num_rate_diff = soml_tab->vht_cnt[j - vht0] -
-+				soml_tab->pre_vht_cnt[j - vht0];
-+		soml_tab->vht_cnt_off[j - vht0] += num_rate_diff;
-+		soml_tab->pre_vht_cnt[j - vht0] = soml_tab->vht_cnt[j - vht0];
-+		num_bytes_diff = soml_tab->vht_byte[j - vht0] -
-+				 soml_tab->pre_vht_byte[j - vht0];
-+		soml_tab->vht_byte_off[j - vht0] += num_bytes_diff;
-+		soml_tab->pre_vht_byte[j - vht0] = soml_tab->vht_byte[j - vht0];
-+	}
-+}
-+
-+void phydm_soml_statistics(void *dm_void, u8 on_off_state)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+
-+	if (on_off_state == SOML_ON) {
-+		if (*dm->channel <= 14)
-+			phydm_soml_stats_ht_on(dm);
-+		if (dm->support_ic_type == ODM_RTL8822B)
-+			phydm_soml_stats_vht_on(dm);
-+	} else if (on_off_state == SOML_OFF) {
-+		if (*dm->channel <= 14)
-+			phydm_soml_stats_ht_off(dm);
-+		if (dm->support_ic_type == ODM_RTL8822B)
-+			phydm_soml_stats_vht_off(dm);
-+	}
-+}
-+
-+void phydm_adsl_init_state(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+
-+	u8 next_on_off;
-+	u16 ht_reset[HT_RATE_IDX] = {0}, vht_reset[VHT_RATE_IDX] = {0};
-+	u8 size = sizeof(ht_reset[0]);
-+
-+	phydm_soml_reset_rx_rate(dm);
-+	odm_move_memory(dm, soml_tab->ht_byte, ht_reset,
-+			HT_RATE_IDX * size);
-+	odm_move_memory(dm, soml_tab->ht_byte_on, ht_reset,
-+			HT_RATE_IDX * size);
-+	odm_move_memory(dm, soml_tab->ht_byte_off, ht_reset,
-+			HT_RATE_IDX * size);
-+	odm_move_memory(dm, soml_tab->vht_byte, vht_reset,
-+			VHT_RATE_IDX * size);
-+	odm_move_memory(dm, soml_tab->vht_byte_on, vht_reset,
-+			VHT_RATE_IDX * size);
-+	odm_move_memory(dm, soml_tab->vht_byte_off, vht_reset,
-+			VHT_RATE_IDX * size);
-+	if (dm->support_ic_type == ODM_RTL8822B) {
-+		soml_tab->cfo_cnt++;
-+		phydm_soml_cfo_process(dm,
-+				       &soml_tab->cfo_diff_a,
-+				       &soml_tab->cfo_diff_b);
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+			  "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n",
-+			  soml_tab->cfo_cnt, soml_tab->cfo_diff_a,
-+			  soml_tab->cfo_diff_b);
-+		soml_tab->cfo_diff_sum_a += soml_tab->cfo_diff_a;
-+		soml_tab->cfo_diff_sum_b += soml_tab->cfo_diff_b;
-+	}
-+
-+	soml_tab->is_soml_method_enable = 1;
-+	soml_tab->get_stats = false;
-+	soml_tab->soml_state_cnt++;
-+	next_on_off = (soml_tab->soml_on_off == SOML_ON) ? SOML_ON : SOML_OFF;
-+	phydm_soml_on_off(dm, next_on_off);
-+	odm_set_timer(dm, &soml_tab->phydm_adaptive_soml_timer,
-+		      soml_tab->soml_delay_time); /*@ms*/
-+}
-+
-+void phydm_adsl_odd_state(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	u16 ht_reset[HT_RATE_IDX] = {0}, vht_reset[VHT_RATE_IDX] = {0};
-+	u8 size = sizeof(ht_reset[0]);
-+
-+	soml_tab->get_stats = true;
-+	soml_tab->soml_state_cnt++;
-+	odm_move_memory(dm, soml_tab->pre_ht_cnt, soml_tab->ht_cnt,
-+			HT_RATE_IDX * size);
-+	odm_move_memory(dm, soml_tab->pre_vht_cnt, soml_tab->vht_cnt,
-+			VHT_RATE_IDX * size);
-+	odm_move_memory(dm, soml_tab->pre_ht_byte, soml_tab->ht_byte,
-+			HT_RATE_IDX * size);
-+	odm_move_memory(dm, soml_tab->pre_vht_byte, soml_tab->vht_byte,
-+			VHT_RATE_IDX * size);
-+
-+	if (dm->support_ic_type == ODM_RTL8822B) {
-+		soml_tab->cfo_cnt++;
-+		phydm_soml_cfo_process(dm,
-+				       &soml_tab->cfo_diff_a,
-+				       &soml_tab->cfo_diff_b);
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+			  "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n",
-+			  soml_tab->cfo_cnt, soml_tab->cfo_diff_a,
-+			  soml_tab->cfo_diff_b);
-+		soml_tab->cfo_diff_sum_a += soml_tab->cfo_diff_a;
-+		soml_tab->cfo_diff_sum_b += soml_tab->cfo_diff_b;
-+	}
-+	odm_set_timer(dm, &soml_tab->phydm_adaptive_soml_timer,
-+		      soml_tab->soml_intvl); /*@ms*/
-+}
-+
-+void phydm_adsl_even_state(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	u8 next_on_off;
-+
-+	soml_tab->get_stats = false;
-+	if (dm->support_ic_type == ODM_RTL8822B) {
-+		soml_tab->cfo_cnt++;
-+		phydm_soml_cfo_process(dm,
-+				       &soml_tab->cfo_diff_a,
-+				       &soml_tab->cfo_diff_b);
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+			  "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n",
-+			  soml_tab->cfo_cnt, soml_tab->cfo_diff_a,
-+			  soml_tab->cfo_diff_b);
-+		soml_tab->cfo_diff_sum_a += soml_tab->cfo_diff_a;
-+		soml_tab->cfo_diff_sum_b += soml_tab->cfo_diff_b;
-+	}
-+	soml_tab->soml_state_cnt++;
-+	phydm_soml_statistics(dm, soml_tab->soml_on_off);
-+	next_on_off = (soml_tab->soml_on_off == SOML_ON) ? SOML_OFF : SOML_ON;
-+	phydm_soml_on_off(dm, next_on_off);
-+	odm_set_timer(dm, &soml_tab->phydm_adaptive_soml_timer,
-+		      soml_tab->soml_delay_time); /*@ms*/
-+}
-+
-+void phydm_adsl_decision_state(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	boolean on_above = false, off_above = false;
-+	u8 i, max_idx_on = 0, max_idx_off = 0;
-+	u8 next_on_off = soml_tab->soml_last_state;
-+	u8 mcs0 = ODM_RATEMCS0, vht0 = ODM_RATEVHTSS1MCS0;
-+	u8 crc_taget = soml_tab->soml_last_state;
-+	u8 rate_num = 1, ss_shift = 0;
-+	u16 ht_ok_max_on = 0, ht_fail_max_on = 0, utility_on = 0;
-+	u16 ht_ok_max_off = 0, ht_fail_max_off = 0, utility_off = 0;
-+	u16 vht_ok_max_on = 0, vht_fail_max_on = 0;
-+	u16 vht_ok_max_off = 0, vht_fail_max_off = 0;
-+	u16 num_total_qam = 0;
-+	u16 cnt_max_on = 0, cnt_max_off = 0;
-+	u32 ht_total_cnt_on = 0, ht_total_cnt_off = 0;
-+	u32 total_ht_rate_on = 0, total_ht_rate_off = 0;
-+	u32 vht_total_cnt_on = 0, vht_total_cnt_off = 0;
-+	u32 total_vht_rate_on = 0, total_vht_rate_off = 0;
-+	u32 rate_per_pkt_on = 0, rate_per_pkt_off = 0;
-+	s32 cfo_diff_avg_a, cfo_diff_avg_b;
-+	u16 vht_phy_rate_table[] = {
-+		/*@20M*/
-+		6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1SS MCS0~9*/
-+		13, 26, 39, 52, 78, 104, 117, 130, 156, 180 /*@2SSMCS0~9*/
-+	};
-+
-+	if (dm->support_ic_type & ODM_IC_1SS)
-+		rate_num = 1;
-+	#ifdef PHYDM_COMPILE_ABOVE_2SS
-+	else if (dm->support_ic_type & ODM_IC_2SS)
-+		rate_num = 2;
-+	#endif
-+	#ifdef PHYDM_COMPILE_ABOVE_3SS
-+	else if (dm->support_ic_type & ODM_IC_3SS)
-+		rate_num = 3;
-+	#endif
-+	#ifdef PHYDM_COMPILE_ABOVE_4SS
-+	else if (dm->support_ic_type & ODM_IC_4SS)
-+		rate_num = 4;
-+	#endif
-+	else
-+		pr_debug("%s: mismatch IC type %x\n", __func__,
-+			 dm->support_ic_type);
-+	soml_tab->get_stats = false;
-+	PHYDM_DBG(dm, DBG_ADPTV_SOML, "[Decisoin state ]\n");
-+	phydm_soml_statistics(dm, soml_tab->soml_on_off);
-+	if (*dm->channel <= 14) {
-+		/* @[Search 1st and 2nd rate by counter] */
-+		for (i = 0; i < rate_num; i++) {
-+			ss_shift = (i << 3);
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "*ht_cnt_on  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
-+				  (ss_shift), (ss_shift + 7),
-+				  soml_tab->ht_cnt_on[ss_shift + 0],
-+				  soml_tab->ht_cnt_on[ss_shift + 1],
-+				  soml_tab->ht_cnt_on[ss_shift + 2],
-+				  soml_tab->ht_cnt_on[ss_shift + 3],
-+				  soml_tab->ht_cnt_on[ss_shift + 4],
-+				  soml_tab->ht_cnt_on[ss_shift + 5],
-+				  soml_tab->ht_cnt_on[ss_shift + 6],
-+				  soml_tab->ht_cnt_on[ss_shift + 7]);
-+		}
-+
-+		for (i = 0; i < rate_num; i++) {
-+			ss_shift = (i << 3);
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "*ht_cnt_off  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
-+				  (ss_shift), (ss_shift + 7),
-+				  soml_tab->ht_cnt_off[ss_shift + 0],
-+				  soml_tab->ht_cnt_off[ss_shift + 1],
-+				  soml_tab->ht_cnt_off[ss_shift + 2],
-+				  soml_tab->ht_cnt_off[ss_shift + 3],
-+				  soml_tab->ht_cnt_off[ss_shift + 4],
-+				  soml_tab->ht_cnt_off[ss_shift + 5],
-+				  soml_tab->ht_cnt_off[ss_shift + 6],
-+				  soml_tab->ht_cnt_off[ss_shift + 7]);
-+		}
-+
-+		for (i = 0; i < rate_num; i++) {
-+			ss_shift = (i << 3);
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "*ht_crc_ok_cnt_on  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
-+				  (ss_shift), (ss_shift + 7),
-+				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 0],
-+				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 1],
-+				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 2],
-+				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 3],
-+				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 4],
-+				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 5],
-+				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 6],
-+				  soml_tab->ht_crc_ok_cnt_on[ss_shift + 7]);
-+		}
-+
-+		for (i = 0; i < rate_num; i++) {
-+			ss_shift = (i << 3);
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "*ht_crc_fail_cnt_on  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
-+				  (ss_shift), (ss_shift + 7),
-+				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 0],
-+				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 1],
-+				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 2],
-+				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 3],
-+				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 4],
-+				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 5],
-+				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 6],
-+				  soml_tab->ht_crc_fail_cnt_on[ss_shift + 7]);
-+		}
-+
-+		for (i = 0; i < rate_num; i++) {
-+			ss_shift = (i << 3);
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "*ht_crc_ok_cnt_off  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
-+				  (ss_shift), (ss_shift + 7),
-+				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 0],
-+				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 1],
-+				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 2],
-+				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 3],
-+				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 4],
-+				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 5],
-+				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 6],
-+				  soml_tab->ht_crc_ok_cnt_off[ss_shift + 7]);
-+		}
-+
-+		for (i = 0; i < rate_num; i++) {
-+			ss_shift = (i << 3);
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "*ht_crc_fail_cnt_off  HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n",
-+				  (ss_shift), (ss_shift + 7),
-+				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 0],
-+				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 1],
-+				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 2],
-+				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 3],
-+				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 4],
-+				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 5],
-+				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 6],
-+				  soml_tab->ht_crc_fail_cnt_off[ss_shift + 7]);
-+		}
-+		for (i = ODM_RATEMCS0; i <= ODM_RATEMCS15; i++) {
-+			ht_total_cnt_on += soml_tab->ht_cnt_on[i - mcs0];
-+			ht_total_cnt_off += soml_tab->ht_cnt_off[i - mcs0];
-+			total_ht_rate_on += (soml_tab->ht_cnt_on[i - mcs0] *
-+					    phy_rate_table[i]);
-+			total_ht_rate_off += (soml_tab->ht_cnt_off[i - mcs0] *
-+					     phy_rate_table[i]);
-+			if (soml_tab->ht_cnt_on[i - mcs0] > cnt_max_on) {
-+				cnt_max_on = soml_tab->ht_cnt_on[i - mcs0];
-+				max_idx_on = i - mcs0;
-+			}
-+
-+			if (soml_tab->ht_cnt_off[i - mcs0] > cnt_max_off) {
-+				cnt_max_off = soml_tab->ht_cnt_off[i - mcs0];
-+				max_idx_off = i - mcs0;
-+			}
-+		}
-+		total_ht_rate_on = total_ht_rate_on << 3;
-+		total_ht_rate_off = total_ht_rate_off << 3;
-+		rate_per_pkt_on = (ht_total_cnt_on != 0) ?
-+				  (total_ht_rate_on / ht_total_cnt_on) : 0;
-+		rate_per_pkt_off = (ht_total_cnt_off != 0) ?
-+				   (total_ht_rate_off / ht_total_cnt_off) : 0;
-+		#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+		ht_ok_max_on = soml_tab->ht_crc_ok_cnt_on[max_idx_on];
-+		ht_fail_max_on = soml_tab->ht_crc_fail_cnt_on[max_idx_on];
-+		ht_ok_max_off = soml_tab->ht_crc_ok_cnt_off[max_idx_off];
-+		ht_fail_max_off = soml_tab->ht_crc_fail_cnt_off[max_idx_off];
-+
-+		if (ht_fail_max_on == 0)
-+			ht_fail_max_on = 1;
-+
-+		if (ht_fail_max_off == 0)
-+			ht_fail_max_off = 1;
-+
-+		if (ht_ok_max_on > ht_fail_max_on)
-+			on_above = true;
-+
-+		if (ht_ok_max_off > ht_fail_max_off)
-+			off_above = true;
-+
-+		if (on_above && !off_above) {
-+			crc_taget = SOML_ON;
-+		} else if (!on_above && off_above) {
-+			crc_taget = SOML_OFF;
-+		} else if (on_above && off_above) {
-+			utility_on = (ht_ok_max_on << 7) / ht_fail_max_on;
-+			utility_off = (ht_ok_max_off << 7) / ht_fail_max_off;
-+			crc_taget = (utility_on == utility_off) ?
-+				    (soml_tab->soml_last_state) :
-+				    ((utility_on > utility_off) ? SOML_ON :
-+				    SOML_OFF);
-+
-+		} else if (!on_above && !off_above) {
-+			if (ht_ok_max_on == 0)
-+				ht_ok_max_on = 1;
-+			if (ht_ok_max_off == 0)
-+				ht_ok_max_off = 1;
-+			utility_on = (ht_fail_max_on << 7) / ht_ok_max_on;
-+			utility_off = (ht_fail_max_off << 7) / ht_ok_max_off;
-+			crc_taget = (utility_on == utility_off) ?
-+				    (soml_tab->soml_last_state) :
-+				    ((utility_on < utility_off) ? SOML_ON :
-+				    SOML_OFF);
-+		}
-+		#endif
-+	} else if (dm->support_ic_type == ODM_RTL8822B) {
-+		cfo_diff_avg_a = soml_tab->cfo_diff_sum_a / soml_tab->cfo_cnt;
-+		cfo_diff_avg_b = soml_tab->cfo_diff_sum_b / soml_tab->cfo_cnt;
-+		soml_tab->cfo_diff_avg_a = (soml_tab->cfo_cnt != 0) ?
-+					   cfo_diff_avg_a : 0;
-+		soml_tab->cfo_diff_avg_b = (soml_tab->cfo_cnt != 0) ?
-+					   cfo_diff_avg_b : 0;
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+			  "[ cfo_diff_avg_a = %d KHz; cfo_diff_avg_b = %d KHz]\n",
-+			  soml_tab->cfo_diff_avg_a,
-+			  soml_tab->cfo_diff_avg_b);
-+		for (i = 0; i < VHT_ORDER_TYPE; i++)
-+			num_total_qam += soml_tab->num_vht_qam[i];
-+
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+			  "[ ((2SS)) BPSK_QPSK_count = %d ; 16QAM_count = %d ; 64QAM_count = %d ; 256QAM_count = %d ; num_total_qam = %d]\n",
-+			  soml_tab->num_vht_qam[BPSK_QPSK],
-+			  soml_tab->num_vht_qam[QAM16],
-+			  soml_tab->num_vht_qam[QAM64],
-+			  soml_tab->num_vht_qam[QAM256],
-+			  num_total_qam);
-+		if (((soml_tab->num_vht_qam[QAM256] * 100) >
-+		    (num_total_qam * soml_tab->qam256_dist_th)) &&
-+		    cfo_diff_avg_a > soml_tab->cfo_qam256_th &&
-+		    cfo_diff_avg_b > soml_tab->cfo_qam256_th) {
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "[  QAM256_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n",
-+				  soml_tab->qam256_dist_th,
-+				  soml_tab->cfo_qam256_th);
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
-+			phydm_soml_on_off(dm, SOML_OFF);
-+			return;
-+		} else if (((soml_tab->num_vht_qam[QAM64] * 100) >
-+			   (num_total_qam * soml_tab->qam64_dist_th)) &&
-+			   (cfo_diff_avg_a > soml_tab->cfo_qam64_th) &&
-+			   (cfo_diff_avg_b > soml_tab->cfo_qam64_th)) {
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "[  QAM64_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n",
-+				  soml_tab->qam64_dist_th,
-+				  soml_tab->cfo_qam64_th);
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
-+			phydm_soml_on_off(dm, SOML_OFF);
-+			return;
-+		} else if (((soml_tab->num_vht_qam[QAM16] * 100) >
-+			   (num_total_qam * soml_tab->qam16_dist_th)) &&
-+			   (cfo_diff_avg_a > soml_tab->cfo_qam16_th) &&
-+			   (cfo_diff_avg_b > soml_tab->cfo_qam16_th)) {
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "[  QAM16_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n",
-+				  soml_tab->qam16_dist_th,
-+				  soml_tab->cfo_qam16_th);
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
-+			phydm_soml_on_off(dm, SOML_OFF);
-+			return;
-+		} else if (((soml_tab->num_vht_qam[BPSK_QPSK] * 100) >
-+			   (num_total_qam * soml_tab->bpsk_qpsk_dist_th)) &&
-+			   (cfo_diff_avg_a > soml_tab->cfo_qpsk_th) &&
-+			   (cfo_diff_avg_b > soml_tab->cfo_qpsk_th)) {
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "[  BPSK_QPSK_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n",
-+				  soml_tab->bpsk_qpsk_dist_th,
-+				  soml_tab->cfo_qpsk_th);
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
-+			phydm_soml_on_off(dm, SOML_OFF);
-+			return;
-+		}
-+
-+		for (i = 0; i < rate_num; i++) {
-+			ss_shift = 10 * i;
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "[  vht_cnt_on  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n",
-+				  (i + 1),
-+				  soml_tab->vht_cnt_on[ss_shift + 0],
-+				  soml_tab->vht_cnt_on[ss_shift + 1],
-+				  soml_tab->vht_cnt_on[ss_shift + 2],
-+				  soml_tab->vht_cnt_on[ss_shift + 3],
-+				  soml_tab->vht_cnt_on[ss_shift + 4],
-+				  soml_tab->vht_cnt_on[ss_shift + 5],
-+				  soml_tab->vht_cnt_on[ss_shift + 6],
-+				  soml_tab->vht_cnt_on[ss_shift + 7],
-+				  soml_tab->vht_cnt_on[ss_shift + 8],
-+				  soml_tab->vht_cnt_on[ss_shift + 9]);
-+		}
-+
-+		for (i = 0; i < rate_num; i++) {
-+			ss_shift = 10 * i;
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "[  vht_cnt_off  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n",
-+				  (i + 1),
-+				  soml_tab->vht_cnt_off[ss_shift + 0],
-+				  soml_tab->vht_cnt_off[ss_shift + 1],
-+				  soml_tab->vht_cnt_off[ss_shift + 2],
-+				  soml_tab->vht_cnt_off[ss_shift + 3],
-+				  soml_tab->vht_cnt_off[ss_shift + 4],
-+				  soml_tab->vht_cnt_off[ss_shift + 5],
-+				  soml_tab->vht_cnt_off[ss_shift + 6],
-+				  soml_tab->vht_cnt_off[ss_shift + 7],
-+				  soml_tab->vht_cnt_off[ss_shift + 8],
-+				  soml_tab->vht_cnt_off[ss_shift + 9]);
-+		}
-+
-+		for (i = 0; i < rate_num; i++) {
-+			ss_shift = 10 * i;
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "*vht_crc_ok_cnt_on  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
-+				  (i + 1),
-+				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 0],
-+				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 1],
-+				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 2],
-+				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 3],
-+				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 4],
-+				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 5],
-+				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 6],
-+				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 7],
-+				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 8],
-+				  soml_tab->vht_crc_ok_cnt_on[ss_shift + 9]);
-+		}
-+		for (i = 0; i < rate_num; i++) {
-+			ss_shift = 10 * i;
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "*vht_crc_fail_cnt_on  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
-+				  (i + 1),
-+				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 0],
-+				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 1],
-+				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 2],
-+				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 3],
-+				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 4],
-+				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 5],
-+				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 6],
-+				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 7],
-+				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 8],
-+				  soml_tab->vht_crc_fail_cnt_on[ss_shift + 9]);
-+		}
-+		for (i = 0; i < rate_num; i++) {
-+			ss_shift = 10 * i;
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "*vht_crc_ok_cnt_off  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
-+				  (i + 1),
-+				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 0],
-+				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 1],
-+				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 2],
-+				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 3],
-+				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 4],
-+				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 5],
-+				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 6],
-+				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 7],
-+				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 8],
-+				  soml_tab->vht_crc_ok_cnt_off[ss_shift + 9]);
-+		}
-+		for (i = 0; i < rate_num; i++) {
-+			ss_shift = 10 * i;
-+			PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+				  "*vht_crc_fail_cnt_off  VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n",
-+				  (i + 1),
-+				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 0],
-+				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 1],
-+				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 2],
-+				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 3],
-+				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 4],
-+				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 5],
-+				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 6],
-+				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 7],
-+				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 8],
-+				  soml_tab->vht_crc_fail_cnt_off[ss_shift + 9]);
-+		}
-+
-+		for (i = ODM_RATEVHTSS2MCS0; i <= ODM_RATEVHTSS2MCS9; i++) {
-+			vht_total_cnt_on += soml_tab->vht_cnt_on[i - vht0];
-+			vht_total_cnt_off += soml_tab->vht_cnt_off[i - vht0];
-+			total_vht_rate_on += (soml_tab->vht_cnt_on[i - vht0] *
-+					     vht_phy_rate_table[i - vht0]);
-+			total_vht_rate_off += (soml_tab->vht_cnt_off[i - vht0] *
-+					      vht_phy_rate_table[i - vht0]);
-+
-+			if (soml_tab->vht_cnt_on[i - vht0] > cnt_max_on) {
-+				cnt_max_on = soml_tab->vht_cnt_on[i - vht0];
-+				max_idx_on = i - vht0;
-+			}
-+
-+			if (soml_tab->vht_cnt_off[i - vht0] > cnt_max_off) {
-+				cnt_max_off = soml_tab->vht_cnt_off[i - vht0];
-+				max_idx_off = i - vht0;
-+			}
-+		}
-+		total_vht_rate_on = total_vht_rate_on << 3;
-+		total_vht_rate_off = total_vht_rate_off << 3;
-+		rate_per_pkt_on = (vht_total_cnt_on != 0) ?
-+				  (total_vht_rate_on / vht_total_cnt_on) : 0;
-+		rate_per_pkt_off = (vht_total_cnt_off != 0) ?
-+				   (total_vht_rate_off / vht_total_cnt_off) : 0;
-+		#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+		vht_ok_max_on = soml_tab->vht_crc_ok_cnt_on[max_idx_on];
-+		vht_fail_max_on = soml_tab->vht_crc_fail_cnt_on[max_idx_on];
-+		vht_ok_max_off = soml_tab->vht_crc_ok_cnt_off[max_idx_off];
-+		vht_fail_max_off = soml_tab->vht_crc_fail_cnt_off[max_idx_off];
-+
-+		if (vht_fail_max_on == 0)
-+			vht_fail_max_on = 1;
-+
-+		if (vht_fail_max_off == 0)
-+			vht_fail_max_off = 1;
-+
-+		if (vht_ok_max_on > vht_fail_max_on)
-+			on_above = true;
-+
-+		if (vht_ok_max_off > vht_fail_max_off)
-+			off_above = true;
-+
-+		if (on_above && !off_above) {
-+			crc_taget = SOML_ON;
-+		} else if (!on_above && off_above) {
-+			crc_taget = SOML_OFF;
-+		} else if (on_above && off_above) {
-+			utility_on = (vht_ok_max_on << 7) / vht_fail_max_on;
-+			utility_off = (vht_ok_max_off << 7) / vht_fail_max_off;
-+			crc_taget = (utility_on == utility_off) ?
-+				    (soml_tab->soml_last_state) :
-+				    ((utility_on > utility_off) ? SOML_ON :
-+				    SOML_OFF);
-+
-+		} else if (!on_above && !off_above) {
-+			if (vht_ok_max_on == 0)
-+				vht_ok_max_on = 1;
-+			if (vht_ok_max_off == 0)
-+				vht_ok_max_off = 1;
-+			utility_on = (vht_fail_max_on << 7) / vht_ok_max_on;
-+			utility_off = (vht_fail_max_off << 7) / vht_ok_max_off;
-+			crc_taget = (utility_on == utility_off) ?
-+				    (soml_tab->soml_last_state) :
-+				    ((utility_on < utility_off) ? SOML_ON :
-+				    SOML_OFF);
-+		}
-+		#endif
-+
-+	}
-+
-+	/* @[Decision] */
-+	PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+		  "[  rate_per_pkt_on = %d ; rate_per_pkt_off = %d ]\n",
-+		  rate_per_pkt_on, rate_per_pkt_off);
-+	#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	if (max_idx_on == max_idx_off && max_idx_on != 0) {
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+			  "[ max_idx_on == max_idx_off ]\n");
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+			  "[ max_idx = %d, crc_utility_on = %d, crc_utility_off = %d, crc_target = %d]\n",
-+			  max_idx_on, utility_on, utility_off,
-+			  crc_taget);
-+		next_on_off = crc_taget;
-+	} else
-+	#endif
-+	if (rate_per_pkt_on > rate_per_pkt_off) {
-+		next_on_off = SOML_ON;
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+			  "[ rate_per_pkt_on > rate_per_pkt_off ==> SOML_ON ]\n");
-+	} else if (rate_per_pkt_on < rate_per_pkt_off) {
-+		next_on_off = SOML_OFF;
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+			  "[ rate_per_pkt_on < rate_per_pkt_off ==> SOML_OFF ]\n");
-+	} else {
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+			  "[ stay at soml_last_state ]\n");
-+		next_on_off = soml_tab->soml_last_state;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : ");
-+	phydm_soml_on_off(dm, next_on_off);
-+	soml_tab->soml_last_state = next_on_off;
-+}
-+
-+void phydm_adsl(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+
-+	if (dm->support_ic_type & PHYDM_ADAPTIVE_SOML_IC) {
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML, "soml_state_cnt =((%d))\n",
-+			  soml_tab->soml_state_cnt);
-+		/*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)===============*/
-+		if (soml_tab->soml_state_cnt <
-+		    (soml_tab->soml_train_num << 1)) {
-+			if (soml_tab->soml_state_cnt == 0)
-+				phydm_adsl_init_state(dm);
-+			else if ((soml_tab->soml_state_cnt % 2) != 0)
-+				phydm_adsl_odd_state(dm);
-+			else if ((soml_tab->soml_state_cnt % 2) == 0)
-+				phydm_adsl_even_state(dm);
-+		} else {
-+			phydm_adsl_decision_state(dm);
-+		}
-+	}
-+}
-+
-+void phydm_adaptive_soml_reset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+
-+	soml_tab->soml_state_cnt = 0;
-+	soml_tab->is_soml_method_enable = 0;
-+	soml_tab->soml_counter = 0;
-+}
-+
-+void phydm_set_adsl_val(void *dm_void, u32 *val_buf, u8 val_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML))
-+		return;
-+
-+	if (val_len != 1) {
-+		PHYDM_DBG(dm, ODM_COMP_API, "[Error][ADSL]Need val_len=1\n");
-+		return;
-+	}
-+
-+	phydm_soml_on_off(dm, (u8)val_buf[1]);
-+}
-+
-+void phydm_soml_crc_acq(void *dm_void, u8 rate_id, boolean crc32, u32 length)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	u8 offset = 0;
-+
-+	if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML))
-+		return;
-+
-+	if (!soml_tab->get_stats)
-+		return;
-+	if (length < 1400)
-+		return;
-+
-+	if (soml_tab->soml_on_off == SOML_ON) {
-+		if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS15) {
-+			offset = rate_id - ODM_RATEMCS0;
-+			if (crc32 == CRC_OK)
-+				soml_tab->ht_crc_ok_cnt_on[offset]++;
-+			else if (crc32 == CRC_FAIL)
-+				soml_tab->ht_crc_fail_cnt_on[offset]++;
-+		} else if (rate_id >= ODM_RATEVHTSS1MCS0 &&
-+			   rate_id <= ODM_RATEVHTSS2MCS9) {
-+			offset = rate_id - ODM_RATEVHTSS1MCS0;
-+			if (crc32 == CRC_OK)
-+				soml_tab->vht_crc_ok_cnt_on[offset]++;
-+			else if (crc32 == CRC_FAIL)
-+				soml_tab->vht_crc_fail_cnt_on[offset]++;
-+		}
-+	} else if (soml_tab->soml_on_off == SOML_OFF) {
-+		if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS15) {
-+			offset = rate_id - ODM_RATEMCS0;
-+			if (crc32 == CRC_OK)
-+				soml_tab->ht_crc_ok_cnt_off[offset]++;
-+			else if (crc32 == CRC_FAIL)
-+				soml_tab->ht_crc_fail_cnt_off[offset]++;
-+		} else if (rate_id >= ODM_RATEVHTSS1MCS0 &&
-+			   rate_id <= ODM_RATEVHTSS2MCS9) {
-+			offset = rate_id - ODM_RATEVHTSS1MCS0;
-+			if (crc32 == CRC_OK)
-+				soml_tab->vht_crc_ok_cnt_off[offset]++;
-+			else if (crc32 == CRC_FAIL)
-+				soml_tab->vht_crc_fail_cnt_off[offset]++;
-+		}
-+	}
-+}
-+
-+void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	u8 offset = 0;
-+
-+	if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML))
-+		return;
-+
-+	if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS31) {
-+		offset = rate_id - ODM_RATEMCS0;
-+		if (offset > (HT_RATE_IDX - 1))
-+			offset = HT_RATE_IDX - 1;
-+
-+		soml_tab->ht_byte[offset] += (u16)length;
-+	} else if (rate_id >= ODM_RATEVHTSS1MCS0 &&
-+		   rate_id <= ODM_RATEVHTSS4MCS9) {
-+		offset = rate_id - ODM_RATEVHTSS1MCS0;
-+		if (offset > (VHT_RATE_IDX - 1))
-+			offset = VHT_RATE_IDX - 1;
-+
-+		soml_tab->vht_byte[offset] += (u16)length;
-+	}
-+}
-+
-+#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
-+static void pre_phydm_adaptive_soml_callback(unsigned long task_dm)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)task_dm;
-+	struct rtl8192cd_priv *priv = dm->priv;
-+	struct priv_shared_info *pshare = priv->pshare;
-+
-+	if (!(priv->drv_state & DRV_STATE_OPEN))
-+		return;
-+	if (pshare->bDriverStopped || pshare->bSurpriseRemoved) {
-+		printk("[%s] bDriverStopped(%d) OR bSurpriseRemoved(%d)\n",
-+		       __FUNCTION__, pshare->bDriverStopped,
-+		       pshare->bSurpriseRemoved);
-+		return;
-+	}
-+
-+	rtw_enqueue_timer_event(priv, &pshare->adaptive_soml_event,
-+				ENQUEUE_TO_TAIL);
-+}
-+
-+void phydm_adaptive_soml_timers_usb(void *dm_void, u8 state)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+	struct rtl8192cd_priv *priv = dm->priv;
-+
-+	if (state == INIT_SOML_TIMMER) {
-+		init_timer(&soml_tab->phydm_adaptive_soml_timer);
-+		soml_tab->phydm_adaptive_soml_timer.data = (unsigned long)dm;
-+		soml_tab->phydm_adaptive_soml_timer.function = pre_phydm_adaptive_soml_callback;
-+		INIT_TIMER_EVENT_ENTRY(&priv->pshare->adaptive_soml_event,
-+				       phydm_adaptive_soml_callback,
-+				       (unsigned long)dm);
-+	} else if (state == CANCEL_SOML_TIMMER) {
-+		odm_cancel_timer(dm, &soml_tab->phydm_adaptive_soml_timer);
-+	} else if (state == RELEASE_SOML_TIMMER) {
-+		odm_release_timer(dm, &soml_tab->phydm_adaptive_soml_timer);
-+	}
-+}
-+#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
-+
-+void phydm_adaptive_soml_timers(void *dm_void, u8 state)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+
-+	if (!(dm->support_ic_type & PHYDM_ADAPTIVE_SOML_IC))
-+		return;
-+
-+#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
-+	struct rtl8192cd_priv *priv = dm->priv;
-+
-+	if (priv->hci_type == RTL_HCI_USB) {
-+		phydm_adaptive_soml_timers_usb(dm_void, state);
-+	} else
-+#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */
-+	{
-+	if (state == INIT_SOML_TIMMER) {
-+		odm_initialize_timer(dm, &soml_tab->phydm_adaptive_soml_timer,
-+				     (void *)phydm_adaptive_soml_callback, NULL,
-+				     "phydm_adaptive_soml_timer");
-+	} else if (state == CANCEL_SOML_TIMMER) {
-+		odm_cancel_timer(dm, &soml_tab->phydm_adaptive_soml_timer);
-+	} else if (state == RELEASE_SOML_TIMMER) {
-+		odm_release_timer(dm, &soml_tab->phydm_adaptive_soml_timer);
-+	}
-+	}
-+}
-+
-+void phydm_adaptive_soml_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+#if 0
-+	if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) {
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+			  "[Return]   Not Support Adaptive SOML\n");
-+		return;
-+	}
-+#endif
-+
-+	if (!(dm->support_ic_type & PHYDM_ADAPTIVE_SOML_IC))
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_ADPTV_SOML, "%s\n", __func__);
-+
-+	soml_tab->soml_state_cnt = 0;
-+	soml_tab->soml_delay_time = 40;
-+	soml_tab->soml_intvl = 150;
-+	soml_tab->soml_train_num = 4;
-+	soml_tab->is_soml_method_enable = 0;
-+	soml_tab->soml_counter = 0;
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+	soml_tab->soml_period = 1;
-+#else
-+	soml_tab->soml_period = 4;
-+#endif
-+	soml_tab->soml_select = 0;
-+	soml_tab->cfo_cnt = 0;
-+	soml_tab->cfo_diff_sum_a = 0;
-+	soml_tab->cfo_diff_sum_b = 0;
-+
-+	soml_tab->cfo_qpsk_th = 94;
-+	soml_tab->cfo_qam16_th = 38;
-+	soml_tab->cfo_qam64_th = 17;
-+	soml_tab->cfo_qam256_th = 7;
-+
-+	soml_tab->bpsk_qpsk_dist_th = 20;
-+	soml_tab->qam16_dist_th = 20;
-+	soml_tab->qam64_dist_th = 20;
-+	soml_tab->qam256_dist_th = 20;
-+
-+	if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
-+		odm_set_bb_reg(dm, 0x988, BIT(25), 1);
-+}
-+
-+void phydm_adaptive_soml(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+
-+	if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) {
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+			  "[Return!!!] Not Support Adaptive SOML Function\n");
-+		return;
-+	}
-+
-+	if (dm->pause_ability & ODM_BB_ADAPTIVE_SOML) {
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML, "Return: Pause ADSL in LV=%d\n",
-+			  dm->pause_lv_table.lv_adsl);
-+		return;
-+	}
-+
-+	if (soml_tab->soml_counter < soml_tab->soml_period) {
-+		soml_tab->soml_counter++;
-+		return;
-+	}
-+	soml_tab->soml_counter = 0;
-+	soml_tab->soml_state_cnt = 0;
-+	soml_tab->cfo_cnt = 0;
-+	soml_tab->cfo_diff_sum_a = 0;
-+	soml_tab->cfo_diff_sum_b = 0;
-+
-+	phydm_soml_reset_qam(dm);
-+
-+	if (soml_tab->soml_select == 0) {
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML,
-+			  "[ Adaptive SOML Training !!!]\n");
-+	} else if (soml_tab->soml_select == 1) {
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Stop Adaptive SOML !!!]\n");
-+		phydm_soml_on_off(dm, SOML_ON);
-+		return;
-+	} else if (soml_tab->soml_select == 2) {
-+		PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Stop Adaptive SOML !!!]\n");
-+		phydm_soml_on_off(dm, SOML_OFF);
-+		return;
-+	}
-+
-+	if (dm->support_ic_type & PHYDM_ADAPTIVE_SOML_IC)
-+		phydm_adsl(dm);
-+}
-+
-+void phydm_enable_adaptive_soml(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ADPTV_SOML, "[%s]\n", __func__);
-+	dm->support_ability |= ODM_BB_ADAPTIVE_SOML;
-+	phydm_soml_on_off(dm, SOML_ON);
-+}
-+
-+void phydm_stop_adaptive_soml(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_ADPTV_SOML, "[%s]\n", __func__);
-+	dm->support_ability &= ~ODM_BB_ADAPTIVE_SOML;
-+	phydm_soml_on_off(dm, SOML_ON);
-+}
-+
-+void phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl,
-+				  u8 period, u8 delay_time)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct adaptive_soml *soml_tab = &dm->dm_soml_table;
-+
-+	soml_tab->soml_train_num = train_num;
-+	soml_tab->soml_intvl = intvl;
-+	soml_tab->soml_period = period;
-+	soml_tab->soml_delay_time = delay_time;
-+}
-+#endif /* @end of CONFIG_ADAPTIVE_SOML*/
-+
-+void phydm_init_soft_ml_setting(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 soml_mask = BIT(31) | BIT(30) | BIT(29) | BIT(28);
-+
-+#if (RTL8822B_SUPPORT == 1)
-+	if (!*dm->mp_mode) {
-+		if (dm->support_ic_type & ODM_RTL8822B) {
-+#if 0
-+			/*odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xd10a0000);*/
-+#endif
-+			phydm_somlrxhp_setting(dm, true);
-+			dm->bsomlenabled = true;
-+		}
-+	}
-+#endif
-+#if (RTL8821C_SUPPORT == 1)
-+	if (!*dm->mp_mode) {
-+		if (dm->support_ic_type & ODM_RTL8821C)
-+			odm_set_bb_reg(dm, R_0x19a8, soml_mask, 0xd);
-+	}
-+#endif
-+#if (RTL8195B_SUPPORT == 1)
-+	if (!*dm->mp_mode) {
-+		if (dm->support_ic_type & ODM_RTL8195B)
-+			odm_set_bb_reg(dm, R_0x19a8, soml_mask, 0xd);
-+	}
-+#endif
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_soml.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_soml.h
-new file mode 100644
-index 000000000000..e2c6e17c2ec8
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_soml.h
-@@ -0,0 +1,199 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+#ifndef __PHYDMSOML_H__
-+#define __PHYDMSOML_H__
-+
-+/*@#define ADAPTIVE_SOML_VERSION	"1.0" Byte counter version*/
-+#define ADAPTIVE_SOML_VERSION "2.0" /*@add avg. phy rate decision 20180126*/
-+
-+#define PHYDM_ADAPTIVE_SOML_IC	(ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)
-+/*@jj add 20170822*/
-+
-+#define INIT_SOML_TIMMER			0
-+#define CANCEL_SOML_TIMMER			1
-+#define RELEASE_SOML_TIMMER		2
-+
-+#define SOML_RSSI_TH_HIGH	25
-+#define SOML_RSSI_TH_LOW	20
-+
-+#define HT_RATE_IDX			16
-+#define VHT_RATE_IDX		20
-+
-+#define HT_ORDER_TYPE		3
-+#define VHT_ORDER_TYPE		4
-+
-+#define CRC_FAIL	1
-+#define CRC_OK		0
-+
-+#if 0
-+#define CFO_QPSK_TH			20
-+#define CFO_QAM16_TH		20
-+#define CFO_QAM64_TH		20
-+#define CFO_QAM256_TH		20
-+
-+#define BPSK_QPSK_DIST		20
-+#define QAM16_DIST			30
-+#define QAM64_DIST			30
-+#define QAM256_DIST			20
-+#endif
-+#define HT_TYPE		1
-+#define VHT_TYPE		2
-+
-+#define SOML_ON		1
-+#define SOML_OFF		0
-+
-+#ifdef CONFIG_ADAPTIVE_SOML
-+
-+struct adaptive_soml {
-+	u32			rvrt_val; /*all rvrt_val for pause API must set to u32*/
-+	boolean			is_soml_method_enable;
-+	boolean			get_stats;
-+	u8			soml_on_off;
-+	u8			soml_state_cnt;
-+	u8			soml_delay_time;
-+	u8			soml_intvl;
-+	u8			soml_train_num;
-+	u8			soml_counter;
-+	u8			soml_period;
-+	u8			soml_select;
-+	u8			soml_last_state;
-+	u8			cfo_qpsk_th;
-+	u8			cfo_qam16_th;
-+	u8			cfo_qam64_th;
-+	u8			cfo_qam256_th;
-+	u8			bpsk_qpsk_dist_th;
-+	u8			qam16_dist_th;
-+	u8			qam64_dist_th;
-+	u8			qam256_dist_th;
-+	u8			cfo_cnt;
-+	s32			cfo_diff_a;
-+	s32			cfo_diff_b;
-+	s32			cfo_diff_sum_a;
-+	s32			cfo_diff_sum_b;
-+	s32			cfo_diff_avg_a;
-+	s32			cfo_diff_avg_b;
-+	u16			ht_cnt[HT_RATE_IDX];
-+	u16			pre_ht_cnt[HT_RATE_IDX];
-+	u16			ht_cnt_on[HT_RATE_IDX];
-+	u16			ht_cnt_off[HT_RATE_IDX];
-+	u16			ht_crc_ok_cnt_on[HT_RATE_IDX];
-+	u16			ht_crc_fail_cnt_on[HT_RATE_IDX];
-+	u16			ht_crc_ok_cnt_off[HT_RATE_IDX];
-+	u16			ht_crc_fail_cnt_off[HT_RATE_IDX];
-+	u16			vht_crc_ok_cnt_on[VHT_RATE_IDX];
-+	u16			vht_crc_fail_cnt_on[VHT_RATE_IDX];
-+	u16			vht_crc_ok_cnt_off[VHT_RATE_IDX];
-+	u16			vht_crc_fail_cnt_off[VHT_RATE_IDX];
-+
-+	u16			vht_cnt[VHT_RATE_IDX];
-+	u16			pre_vht_cnt[VHT_RATE_IDX];
-+	u16			vht_cnt_on[VHT_RATE_IDX];
-+	u16			vht_cnt_off[VHT_RATE_IDX];
-+
-+	u16			num_ht_qam[HT_ORDER_TYPE];
-+	u16			ht_byte[HT_RATE_IDX];
-+	u16			pre_ht_byte[HT_RATE_IDX];
-+	u16			ht_byte_on[HT_RATE_IDX];
-+	u16			ht_byte_off[HT_RATE_IDX];
-+	u16			num_vht_qam[VHT_ORDER_TYPE];
-+	u16			vht_byte[VHT_RATE_IDX];
-+	u16			pre_vht_byte[VHT_RATE_IDX];
-+	u16			vht_byte_on[VHT_RATE_IDX];
-+	u16			vht_byte_off[VHT_RATE_IDX];
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#if USE_WORKITEM
-+	RT_WORK_ITEM	phydm_adaptive_soml_workitem;
-+#endif
-+#endif
-+	struct phydm_timer_list		phydm_adaptive_soml_timer;
-+
-+};
-+
-+enum qam_order {
-+	BPSK_QPSK	= 0,
-+	QAM16		= 1,
-+	QAM64		= 2,
-+	QAM256		= 3
-+};
-+
-+void phydm_dynamicsoftmletting(void *dm_void);
-+
-+void phydm_soml_on_off(void *dm_void, u8 swch);
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void phydm_adaptive_soml_callback(struct phydm_timer_list *timer);
-+
-+void phydm_adaptive_soml_workitem_callback(void *context);
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+void phydm_adaptive_soml_callback(void *dm_void);
-+
-+void phydm_adaptive_soml_workitem_callback(void *context);
-+
-+#else
-+void phydm_adaptive_soml_callback(void *dm_void);
-+#endif
-+
-+void phydm_rx_rate_for_soml(void *dm_void, void *pkt_info_void);
-+
-+void phydm_rx_qam_for_soml(void *dm_void, void *pkt_info_void);
-+
-+void phydm_soml_reset_rx_rate(void *dm_void);
-+
-+void phydm_soml_reset_qam(void *dm_void);
-+
-+void phydm_soml_cfo_process(void *dm_void, s32 *diff_a, s32 *diff_b);
-+
-+void phydm_soml_debug(void *dm_void, char input[][16], u32 *_used,
-+		      char *output, u32 *_out_len);
-+
-+void phydm_soml_statistics(void *dm_void, u8 on_off_state);
-+
-+void phydm_adsl(void *dm_void);
-+
-+void phydm_adaptive_soml_reset(void *dm_void);
-+
-+void phydm_set_adsl_val(void *dm_void, u32 *val_buf, u8 val_len);
-+
-+void phydm_soml_crc_acq(void *dm_void, u8 rate_id, boolean crc32, u32 length);
-+
-+void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length);
-+
-+void phydm_adaptive_soml_timers(void *dm_void, u8 state);
-+
-+void phydm_adaptive_soml_init(void *dm_void);
-+
-+void phydm_adaptive_soml(void *dm_void);
-+
-+void phydm_enable_adaptive_soml(void *dm_void);
-+
-+void phydm_stop_adaptive_soml(void *dm_void);
-+
-+void phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl,
-+				  u8 period, u8 delay_time);
-+#endif
-+void phydm_init_soft_ml_setting(void *dm_void);
-+#endif /*@#ifndef	__PHYDMSOML_H__*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/phydm_types.h b/drivers/staging/rtl8723cs/hal/phydm/phydm_types.h
-new file mode 100644
-index 000000000000..4db8da5cf0b6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/phydm_types.h
-@@ -0,0 +1,413 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+#ifndef __ODM_TYPES_H__
-+#define __ODM_TYPES_H__
-+
-+/*Define Different SW team support*/
-+#define	ODM_AP			0x01	/*BIT(0)*/
-+#define	ODM_CE			0x04	/*BIT(2)*/
-+#define	ODM_WIN		0x08	/*BIT(3)*/
-+#define	ODM_ADSL		0x10
-+/*BIT(4)*/		/*already combine with ODM_AP, and is nouse now*/
-+#define	ODM_IOT		0x20	/*BIT(5)*/
-+
-+/*For FW API*/
-+#define	__iram_odm_func__
-+#define	__odm_func__
-+#define	__odm_func_aon__
-+
-+/*Deifne HW endian support*/
-+#define	ODM_ENDIAN_BIG	0
-+#define	ODM_ENDIAN_LITTLE	1
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	#define GET_PDM_ODM(__padapter)	((struct dm_struct*)(&(GET_HAL_DATA(__padapter))->DM_OutSrc))
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	#define GET_PDM_ODM(__padapter)	((struct dm_struct *)(&(GET_HAL_DATA(__padapter))->odmpriv))
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	#define GET_PDM_ODM(__padapter)	((struct dm_struct*)(&__padapter->pshare->_dmODM))
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
-+	#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
-+	/* enable PCI & USB HCI at the same time */
-+  	#define RT_PCI_USB_INTERFACE			1
-+  	#define	RT_PCI_INTERFACE			RT_PCI_USB_INTERFACE
-+	#define RT_USB_INTERFACE			RT_PCI_USB_INTERFACE
-+	#define	RT_SDIO_INTERFACE			3
-+  	#else
-+	#define	RT_PCI_INTERFACE			1
-+	#define	RT_USB_INTERFACE			2
-+	#define	RT_SDIO_INTERFACE			3
-+	#endif
-+#endif
-+
-+enum hal_status {
-+	HAL_STATUS_SUCCESS,
-+	HAL_STATUS_FAILURE,
-+#if 0
-+	RT_STATUS_PENDING,
-+	RT_STATUS_RESOURCE,
-+	RT_STATUS_INVALID_CONTEXT,
-+	RT_STATUS_INVALID_PARAMETER,
-+	RT_STATUS_NOT_SUPPORT,
-+	RT_STATUS_OS_API_FAILED,
-+#endif
-+};
-+
-+#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
-+
-+#define		VISTA_USB_RX_REVISE			0
-+
-+/*
-+ * Declare for ODM spin lock definition temporarily fro compile pass.
-+ */
-+enum rt_spinlock_type {
-+	RT_TX_SPINLOCK = 1,
-+	RT_RX_SPINLOCK = 2,
-+	RT_RM_SPINLOCK = 3,
-+	RT_CAM_SPINLOCK = 4,
-+	RT_SCAN_SPINLOCK = 5,
-+	RT_LOG_SPINLOCK = 7,
-+	RT_BW_SPINLOCK = 8,
-+	RT_CHNLOP_SPINLOCK = 9,
-+	RT_RF_OPERATE_SPINLOCK = 10,
-+	RT_INITIAL_SPINLOCK = 11,
-+	RT_RF_STATE_SPINLOCK = 12,
-+	/* For RF state. Added by Bruce, 2007-10-30. */
-+#if VISTA_USB_RX_REVISE
-+	RT_USBRX_CONTEXT_SPINLOCK = 13,
-+	RT_USBRX_POSTPROC_SPINLOCK = 14,
-+	/* protect data of adapter->IndicateW/ IndicateR */
-+#endif
-+	/* Shall we define Ndis 6.2 SpinLock Here ? */
-+	RT_PORT_SPINLOCK = 16,
-+	RT_VNIC_SPINLOCK = 17,
-+	RT_HVL_SPINLOCK = 18,
-+	RT_H2C_SPINLOCK = 20,
-+	/* For H2C cmd. Added by tynli. 2009.11.09. */
-+
-+	rt_bt_data_spinlock = 25,
-+
-+	RT_WAPI_OPTION_SPINLOCK = 26,
-+	RT_WAPI_RX_SPINLOCK = 27,
-+
-+	/* add for 92D CCK control issue */
-+	RT_CCK_PAGEA_SPINLOCK = 28,
-+	RT_BUFFER_SPINLOCK = 29,
-+	RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
-+	RT_GEN_TEMP_BUF_SPINLOCK = 31,
-+	RT_AWB_SPINLOCK = 32,
-+	RT_FW_PS_SPINLOCK = 33,
-+	RT_HW_TIMER_SPIN_LOCK = 34,
-+	RT_MPT_WI_SPINLOCK = 35,
-+	RT_P2P_SPIN_LOCK = 36,	/* Protect P2P context */
-+	RT_DBG_SPIN_LOCK = 37,
-+	RT_IQK_SPINLOCK = 38,
-+	RT_PENDED_OID_SPINLOCK = 39,
-+	RT_CHNLLIST_SPINLOCK = 40,
-+	RT_INDIC_SPINLOCK = 41,	/* protect indication */
-+	RT_RFD_SPINLOCK = 42,
-+	RT_SYNC_IO_CNT_SPINLOCK = 43,
-+	RT_LAST_SPINLOCK,
-+};
-+
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	#define sta_info 	_RT_WLAN_STA
-+	#define	__func__		__FUNCTION__
-+	#define	PHYDM_TESTCHIP_SUPPORT	TESTCHIP_SUPPORT
-+	#define MASKH3BYTES			0xffffff00
-+	#define SUCCESS	0
-+	#define FAIL	(-1)
-+
-+	#define	u8 		u1Byte
-+	#define	s8 		s1Byte
-+
-+	#define	u16		u2Byte
-+	#define	s16		s2Byte
-+
-+	#define	u32 	u4Byte
-+	#define	s32 		s4Byte
-+
-+	#define	u64		u8Byte
-+	#define	s64		s8Byte
-+
-+	#define	phydm_timer_list	_RT_TIMER
-+
-+	// for power limit table
-+	enum odm_pw_lmt_regulation_type {
-+		PW_LMT_REGU_FCC = 0,
-+		PW_LMT_REGU_ETSI = 1,
-+		PW_LMT_REGU_MKK = 2,
-+		PW_LMT_REGU_WW13 = 3,
-+		PW_LMT_REGU_IC = 4,
-+		PW_LMT_REGU_KCC = 5,
-+		PW_LMT_REGU_ACMA = 6,
-+		PW_LMT_REGU_CHILE = 7,
-+		PW_LMT_REGU_UKRAINE = 8,
-+		PW_LMT_REGU_MEXICO = 9,
-+		PW_LMT_REGU_CN = 10
-+	};
-+
-+	enum odm_pw_lmt_band_type {
-+		PW_LMT_BAND_2_4G = 0,
-+		PW_LMT_BAND_5G = 1
-+	};
-+
-+	enum odm_pw_lmt_bandwidth_type {
-+		PW_LMT_BW_20M = 0,
-+		PW_LMT_BW_40M = 1,
-+		PW_LMT_BW_80M = 2,
-+		PW_LMT_BW_160M = 3
-+	};
-+
-+	enum odm_pw_lmt_ratesection_type {
-+		PW_LMT_RS_CCK = 0,
-+		PW_LMT_RS_OFDM = 1,
-+		PW_LMT_RS_HT = 2,
-+		PW_LMT_RS_VHT = 3
-+	};
-+
-+	enum odm_pw_lmt_rfpath_type {
-+		PW_LMT_PH_1T = 0,
-+		PW_LMT_PH_2T = 1,
-+		PW_LMT_PH_3T = 2,
-+		PW_LMT_PH_4T = 3
-+	};
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
-+	#include "../typedef.h"
-+
-+	#ifdef CONFIG_PCI_HCI
-+	#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
-+		#define DEV_BUS_TYPE		RT_PCI_USB_INTERFACE
-+	#else
-+		#define DEV_BUS_TYPE		RT_PCI_INTERFACE
-+	#endif
-+	#endif
-+
-+	#if (defined(TESTCHIP_SUPPORT))
-+		#define	PHYDM_TESTCHIP_SUPPORT 1
-+	#else
-+		#define	PHYDM_TESTCHIP_SUPPORT 0
-+	#endif
-+
-+	#define	sta_info stat_info
-+	#define	boolean	bool
-+
-+	#define	phydm_timer_list	timer_list
-+	#if defined(__ECOS)
-+	#define s64	s8Byte
-+	#endif 
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
-+
-+	#include <asm/byteorder.h>
-+
-+	#define DEV_BUS_TYPE	RT_PCI_INTERFACE
-+
-+	#if defined(__LITTLE_ENDIAN)
-+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_LITTLE
-+	#elif defined(__BIG_ENDIAN)
-+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_BIG
-+	#else
-+		#error
-+	#endif
-+
-+	/* define useless flag to avoid compile warning */
-+	#define	USE_WORKITEM 0
-+	#define	FOR_BRAZIL_PRETEST 0
-+	#define	FPGA_TWO_MAC_VERIFICATION	0
-+	#define	RTL8881A_SUPPORT	0
-+	#define	PHYDM_TESTCHIP_SUPPORT 0
-+
-+
-+	#define RATE_ADAPTIVE_SUPPORT			0
-+	#define POWER_TRAINING_ACTIVE			0
-+
-+	#define sta_info	rtl_sta_info
-+	#define	boolean		bool
-+
-+	#define	phydm_timer_list	timer_list
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	#include <drv_types.h>
-+
-+	#ifdef CONFIG_USB_HCI
-+		#define DEV_BUS_TYPE	RT_USB_INTERFACE
-+	#elif defined(CONFIG_PCI_HCI)
-+		#define DEV_BUS_TYPE	RT_PCI_INTERFACE
-+	#elif defined(CONFIG_SDIO_HCI)
-+		#define DEV_BUS_TYPE	RT_SDIO_INTERFACE
-+	#elif defined(CONFIG_GSPI_HCI)
-+		#define DEV_BUS_TYPE	RT_SDIO_INTERFACE
-+	#endif
-+
-+
-+	#if defined(CONFIG_LITTLE_ENDIAN)
-+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_LITTLE
-+	#elif defined(CONFIG_BIG_ENDIAN)
-+		#define	ODM_ENDIAN_TYPE			ODM_ENDIAN_BIG
-+	#endif
-+
-+	#define	boolean	bool
-+
-+	#define SET_TX_DESC_ANTSEL_A_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 24, 1, __value)
-+	#define SET_TX_DESC_ANTSEL_B_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 25, 1, __value)
-+	#define SET_TX_DESC_ANTSEL_C_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 28, 29, 1, __value)
-+
-+	/* define useless flag to avoid compile warning */
-+	#define	USE_WORKITEM 0
-+	#define	FOR_BRAZIL_PRETEST 0
-+	#define	FPGA_TWO_MAC_VERIFICATION	0
-+	#define	RTL8881A_SUPPORT	0
-+
-+	#if (defined(TESTCHIP_SUPPORT))
-+		#define	PHYDM_TESTCHIP_SUPPORT 1
-+	#else
-+		#define	PHYDM_TESTCHIP_SUPPORT 0
-+	#endif
-+
-+	#define	phydm_timer_list	rtw_timer_list
-+
-+	// for power limit table
-+	enum odm_pw_lmt_regulation_type {
-+		PW_LMT_REGU_FCC = 0,
-+		PW_LMT_REGU_ETSI = 1,
-+		PW_LMT_REGU_MKK = 2,
-+		PW_LMT_REGU_WW13 = 3,
-+		PW_LMT_REGU_IC = 4,
-+		PW_LMT_REGU_KCC = 5,
-+		PW_LMT_REGU_ACMA = 6,
-+		PW_LMT_REGU_CHILE = 7,
-+		PW_LMT_REGU_UKRAINE = 8,
-+		PW_LMT_REGU_MEXICO = 9,
-+		PW_LMT_REGU_CN = 10
-+	};
-+
-+	enum odm_pw_lmt_band_type {
-+		PW_LMT_BAND_2_4G = 0,
-+		PW_LMT_BAND_5G = 1
-+	};
-+
-+	enum odm_pw_lmt_bandwidth_type {
-+		PW_LMT_BW_20M = 0,
-+		PW_LMT_BW_40M = 1,
-+		PW_LMT_BW_80M = 2,
-+		PW_LMT_BW_160M = 3
-+	};
-+
-+	enum odm_pw_lmt_ratesection_type {
-+		PW_LMT_RS_CCK = 0,
-+		PW_LMT_RS_OFDM = 1,
-+		PW_LMT_RS_HT = 2,
-+		PW_LMT_RS_VHT = 3
-+	};
-+
-+	enum odm_pw_lmt_rfpath_type {
-+		PW_LMT_PH_1T = 0,
-+		PW_LMT_PH_2T = 1,
-+		PW_LMT_PH_3T = 2,
-+		PW_LMT_PH_4T = 3
-+	};
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+	#define	boolean	bool
-+	#define true	_TRUE
-+	#define false	_FALSE
-+
-+	// for power limit table
-+	enum odm_pw_lmt_regulation_type {
-+		PW_LMT_REGU_NULL = 0,
-+		PW_LMT_REGU_FCC = 1,
-+		PW_LMT_REGU_ETSI = 2,
-+		PW_LMT_REGU_MKK = 3,
-+		PW_LMT_REGU_WW13 = 4
-+	};
-+
-+	enum odm_pw_lmt_band_type {
-+		PW_LMT_BAND_NULL = 0,
-+		PW_LMT_BAND_2_4G = 1,
-+		PW_LMT_BAND_5G = 2
-+	};
-+
-+	enum odm_pw_lmt_bandwidth_type {
-+		PW_LMT_BW_NULL = 0,
-+		PW_LMT_BW_20M = 1,
-+		PW_LMT_BW_40M = 2,
-+		PW_LMT_BW_80M = 3
-+	};
-+
-+	enum odm_pw_lmt_ratesection_type {
-+		PW_LMT_RS_NULL = 0,
-+		PW_LMT_RS_CCK = 1,
-+		PW_LMT_RS_OFDM = 2,
-+		PW_LMT_RS_HT = 3,
-+		PW_LMT_RS_VHT = 4
-+	};
-+
-+	enum odm_pw_lmt_rfpath_type {
-+		PW_LMT_PH_NULL = 0,
-+		PW_LMT_PH_1T = 1,
-+		PW_LMT_PH_2T = 2,
-+		PW_LMT_PH_3T = 3,
-+		PW_LMT_PH_4T = 4
-+	};
-+
-+	#define	phydm_timer_list	timer_list
-+
-+#endif
-+
-+#define READ_NEXT_PAIR(v1, v2, i) do { if (i + 2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i + 1]; } while (0)
-+#define COND_ELSE  2
-+#define COND_ENDIF 3
-+
-+#define	MASKBYTE0		0xff
-+#define	MASKBYTE1		0xff00
-+#define	MASKBYTE2		0xff0000
-+#define	MASKBYTE3		0xff000000
-+#define	MASKHWORD		0xffff0000
-+#define	MASKLWORD		0x0000ffff
-+#define	MASKDWORD		0xffffffff
-+
-+#define	MASK7BITS		0x7f
-+#define	MASK12BITS		0xfff
-+#define	MASKH4BITS		0xf0000000
-+#define	MASK20BITS		0xfffff
-+#define	MASK24BITS		0xffffff
-+#define	MASKOFDM_D		0xffc00000
-+#define	MASKCCK			0x3f3f3f3f
-+
-+#define RFREGOFFSETMASK		0xfffff
-+#define RFREG_MASK		0xfffff
-+
-+#define MASKH3BYTES		0xffffff00
-+#define MASKL3BYTES		0x00ffffff
-+#define MASKBYTE2HIGHNIBBLE	0x00f00000
-+#define MASKBYTE3LOWNIBBLE	0x0f000000
-+#define	MASKL3BYTES		0x00ffffff
-+
-+#endif /* __ODM_TYPES_H__ */
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_bb.c b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_bb.c
-new file mode 100644
-index 000000000000..f02e7ccdd659
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_bb.c
-@@ -0,0 +1,823 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/*Image2HeaderVersion: 3.5.2*/
-+#include "mp_precomp.h"
-+#include "../phydm_precomp.h"
-+
-+#if (RTL8703B_SUPPORT == 1)
-+static boolean
-+check_positive(
-+	struct dm_struct *dm,
-+	const u32	condition1,
-+	const u32	condition2,
-+	const u32	condition3,
-+	const u32	condition4
-+)
-+{
-+	u8	_board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
-+			((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
-+			((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
-+			((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
-+			((dm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/
-+			((dm->board_type & BIT(1)) >> 1) << 5 | /* _NGFF*/
-+			((dm->board_type & BIT(5)) >> 5) << 6;  /* _TRSWT*/
-+
-+	u32	cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
-+
-+	u8	cut_version_for_para = (dm->cut_version ==  ODM_CUT_A) ? 15 : dm->cut_version;
-+	u8	pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type;
-+
-+	u32	driver1 = cut_version_for_para << 24 |
-+			(dm->support_interface & 0xF0) << 16 |
-+			dm->support_platform << 16 |
-+			pkg_type_for_para << 12 |
-+			(dm->support_interface & 0x0F) << 8  |
-+			_board_type;
-+
-+	u32	driver2 = (dm->type_glna & 0xFF) <<  0 |
-+			(dm->type_gpa & 0xFF)  <<  8 |
-+			(dm->type_alna & 0xFF) << 16 |
-+			(dm->type_apa & 0xFF)  << 24;
-+
-+	u32	driver3 = 0;
-+
-+	u32	driver4 = (dm->type_glna & 0xFF00) >>  8 |
-+			(dm->type_gpa & 0xFF00) |
-+			(dm->type_alna & 0xFF00) << 8 |
-+			(dm->type_apa & 0xFF00)  << 16;
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
-+		  __func__, cond1, cond2, cond3, cond4);
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
-+		  __func__, driver1, driver2, driver3, driver4);
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "	(Platform, Interface) = (0x%X, 0x%X)\n",
-+		  dm->support_platform, dm->support_interface);
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "	(Board, Package) = (0x%X, 0x%X)\n", dm->board_type,
-+		  dm->package_type);
-+
-+
-+	/*============== value Defined Check ===============*/
-+	/*QFN type [15:12] and cut version [27:24] need to do value check*/
-+
-+	if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
-+		return false;
-+	if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
-+		return false;
-+
-+	/*=============== Bit Defined Check ================*/
-+	/* We don't care [31:28] */
-+
-+	cond1 &= 0x00FF0FFF;
-+	driver1 &= 0x00FF0FFF;
-+
-+	if ((cond1 & driver1) == cond1) {
-+		u32	bit_mask = 0;
-+
-+		if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
-+			return true;
-+
-+		if ((cond1 & BIT(0)) != 0) /*GLNA*/
-+			bit_mask |= 0x000000FF;
-+		if ((cond1 & BIT(1)) != 0) /*GPA*/
-+			bit_mask |= 0x0000FF00;
-+		if ((cond1 & BIT(2)) != 0) /*ALNA*/
-+			bit_mask |= 0x00FF0000;
-+		if ((cond1 & BIT(3)) != 0) /*APA*/
-+			bit_mask |= 0xFF000000;
-+
-+		if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask)))  /* board_type of each RF path is matched*/
-+			return true;
-+		else
-+			return false;
-+	} else
-+		return false;
-+}
-+
-+/******************************************************************************
-+*                           agc_tab.TXT
-+******************************************************************************/
-+
-+u32 array_mp_8703b_agc_tab[] = {
-+		0xC78, 0xFC000101,
-+		0xC78, 0xFB010101,
-+		0xC78, 0xFA020101,
-+		0xC78, 0xF9030101,
-+		0xC78, 0xF8040101,
-+		0xC78, 0xF7050101,
-+		0xC78, 0xF6060101,
-+		0xC78, 0xF5070101,
-+		0xC78, 0xF4080101,
-+		0xC78, 0xF3090101,
-+		0xC78, 0xF20A0101,
-+		0xC78, 0xF10B0101,
-+		0xC78, 0xF00C0101,
-+		0xC78, 0xEF0D0101,
-+		0xC78, 0xEE0E0101,
-+		0xC78, 0xED0F0101,
-+		0xC78, 0xEC100101,
-+		0xC78, 0xEB110101,
-+		0xC78, 0xEA120101,
-+		0xC78, 0xE9130101,
-+		0xC78, 0xE8140101,
-+		0xC78, 0xE7150101,
-+		0xC78, 0xE6160101,
-+		0xC78, 0xE5170101,
-+		0xC78, 0xE4180101,
-+		0xC78, 0xE3190101,
-+		0xC78, 0x661A0101,
-+		0xC78, 0x651B0101,
-+		0xC78, 0x641C0101,
-+		0xC78, 0x631D0101,
-+		0xC78, 0x071E0101,
-+		0xC78, 0x061F0101,
-+		0xC78, 0x05200101,
-+		0xC78, 0x04210101,
-+		0xC78, 0x03220101,
-+		0xC78, 0xE8230001,
-+		0xC78, 0xE7240001,
-+		0xC78, 0xE6250001,
-+		0xC78, 0xE5260001,
-+		0xC78, 0xE4270001,
-+		0xC78, 0x89280001,
-+		0xC78, 0x88290001,
-+		0xC78, 0x872A0001,
-+		0xC78, 0x862B0001,
-+		0xC78, 0x852C0001,
-+		0xC78, 0x482D0001,
-+		0xC78, 0x472E0001,
-+		0xC78, 0x462F0001,
-+		0xC78, 0x45300001,
-+		0xC78, 0x44310001,
-+		0xC78, 0x07320001,
-+		0xC78, 0x06330001,
-+		0xC78, 0x05340001,
-+		0xC78, 0x04350001,
-+		0xC78, 0x03360001,
-+		0xC78, 0x02370001,
-+		0xC78, 0x01380001,
-+		0xC78, 0x00390001,
-+		0xC78, 0x003A0001,
-+		0xC78, 0x003B0001,
-+		0xC78, 0x003C0001,
-+		0xC78, 0x003D0001,
-+		0xC78, 0x003E0001,
-+		0xC78, 0x003F0001,
-+		0xC78, 0x7F002001,
-+		0xC78, 0x7F012001,
-+		0xC78, 0x7F022001,
-+		0xC78, 0x7F032001,
-+		0xC78, 0x7F042001,
-+		0xC78, 0x7F052001,
-+		0xC78, 0x7F062001,
-+		0xC78, 0x7F072001,
-+		0xC78, 0x7F082001,
-+		0xC78, 0x7F092001,
-+		0xC78, 0x7F0A2001,
-+		0xC78, 0x7F0B2001,
-+		0xC78, 0x7F0C2001,
-+		0xC78, 0x7F0D2001,
-+		0xC78, 0x7F0E2001,
-+		0xC78, 0x7F0F2001,
-+		0xC78, 0x7F102001,
-+		0xC78, 0x7F112001,
-+		0xC78, 0x7E122001,
-+		0xC78, 0x7D132001,
-+		0xC78, 0x7C142001,
-+		0xC78, 0x7B152001,
-+		0xC78, 0x7A162001,
-+		0xC78, 0x79172001,
-+		0xC78, 0x78182001,
-+		0xC78, 0x77192001,
-+		0xC78, 0x761A2001,
-+		0xC78, 0x751B2001,
-+		0xC78, 0x741C2001,
-+		0xC78, 0x731D2001,
-+		0xC78, 0x721E2001,
-+		0xC78, 0x711F2001,
-+		0xC78, 0x70202001,
-+		0xC78, 0x6F212001,
-+		0xC78, 0x6E222001,
-+		0xC78, 0x6D232001,
-+		0xC78, 0x6C242001,
-+		0xC78, 0x6B252001,
-+		0xC78, 0x6A262001,
-+		0xC78, 0x69272001,
-+		0xC78, 0x68282001,
-+		0xC78, 0x67292001,
-+		0xC78, 0x662A2001,
-+		0xC78, 0x652B2001,
-+		0xC78, 0x642C2001,
-+		0xC78, 0x632D2001,
-+		0xC78, 0x622E2001,
-+		0xC78, 0x612F2001,
-+		0xC78, 0x60302001,
-+		0xC78, 0x42312001,
-+		0xC78, 0x41322001,
-+		0xC78, 0x40332001,
-+		0xC78, 0x23342001,
-+		0xC78, 0x22352001,
-+		0xC78, 0x21362001,
-+		0xC78, 0x20372001,
-+		0xC78, 0x00382001,
-+		0xC78, 0x02392001,
-+		0xC78, 0x013A2001,
-+		0xC78, 0x003B2001,
-+		0xC78, 0x003C2001,
-+		0xC78, 0x003D2001,
-+		0xC78, 0x003E2001,
-+		0xC78, 0x003F2001,
-+		0xC78, 0x7F003101,
-+		0xC78, 0x7F013101,
-+		0xC78, 0x7F023101,
-+		0xC78, 0x7F033101,
-+		0xC78, 0x7F043101,
-+		0xC78, 0x7F053101,
-+		0xC78, 0x7F063101,
-+		0xC78, 0x7E073101,
-+		0xC78, 0x7D083101,
-+		0xC78, 0x7C093101,
-+		0xC78, 0x7B0A3101,
-+		0xC78, 0x7A0B3101,
-+		0xC78, 0x790C3101,
-+		0xC78, 0x780D3101,
-+		0xC78, 0x770E3101,
-+		0xC78, 0x760F3101,
-+		0xC78, 0x75103101,
-+		0xC78, 0x74113101,
-+		0xC78, 0x73123101,
-+		0xC78, 0x72133101,
-+		0xC78, 0x71143101,
-+		0xC78, 0x70153101,
-+		0xC78, 0x6F163101,
-+		0xC78, 0x69173101,
-+		0xC78, 0x68183101,
-+		0xC78, 0x67193101,
-+		0xC78, 0x661A3101,
-+		0xC78, 0x651B3101,
-+		0xC78, 0x641C3101,
-+		0xC78, 0x631D3101,
-+		0xC78, 0x621E3101,
-+		0xC78, 0x611F3101,
-+		0xC78, 0x60203101,
-+		0xC78, 0x42213101,
-+		0xC78, 0x41223101,
-+		0xC78, 0x40233101,
-+		0xC78, 0x22243101,
-+		0xC78, 0x21253101,
-+		0xC78, 0x20263101,
-+		0xC78, 0x00273101,
-+		0xC78, 0x00283101,
-+		0xC78, 0x00293101,
-+		0xC78, 0x002A3101,
-+		0xC78, 0x002B3101,
-+		0xC78, 0x002C3101,
-+		0xC78, 0x002D3101,
-+		0xC78, 0x002E3101,
-+		0xC78, 0x002F3101,
-+		0xC78, 0x00303101,
-+		0xC78, 0x00313101,
-+		0xC78, 0x00323101,
-+		0xC78, 0x00333101,
-+		0xC78, 0x00343101,
-+		0xC78, 0x00353101,
-+		0xC78, 0x00363101,
-+		0xC78, 0x00373101,
-+		0xC78, 0x00383101,
-+		0xC78, 0x00393101,
-+		0xC78, 0x003A3101,
-+		0xC78, 0x003B3101,
-+		0xC78, 0x003C3101,
-+		0xC78, 0x003D3101,
-+		0xC78, 0x003E3101,
-+		0xC78, 0x003F3101,
-+		0xC78, 0xFA403101,
-+		0xC78, 0xF9413101,
-+		0xC78, 0xF8423101,
-+		0xC78, 0xF7433101,
-+		0xC78, 0xF6443101,
-+		0xC78, 0xF5453101,
-+		0xC78, 0xF4463101,
-+		0xC78, 0xF3473101,
-+		0xC78, 0xF2483101,
-+		0xC78, 0xE1493101,
-+		0xC78, 0xE04A3101,
-+		0xC78, 0xEF4B3101,
-+		0xC78, 0xEE4C3101,
-+		0xC78, 0xED4D3101,
-+		0xC78, 0xEC4E3101,
-+		0xC78, 0xEB4F3101,
-+		0xC78, 0xEA503101,
-+		0xC78, 0xE9513101,
-+		0xC78, 0xE8523101,
-+		0xC78, 0xE7533101,
-+		0xC78, 0xE6543101,
-+		0xC78, 0xE5553101,
-+		0xC78, 0xE4563101,
-+		0xC78, 0xE3573101,
-+		0xC78, 0xE2583101,
-+		0xC78, 0xE1593101,
-+		0xC78, 0xE05A3101,
-+		0xC78, 0xC25B3101,
-+		0xC78, 0xC15C3101,
-+		0xC78, 0xC05D3101,
-+		0xC78, 0x825E3101,
-+		0xC78, 0x815F3101,
-+		0xC78, 0x80603101,
-+		0xC78, 0x80613101,
-+		0xC78, 0x80623101,
-+		0xC78, 0x80633101,
-+		0xC78, 0x80643101,
-+		0xC78, 0x80653101,
-+		0xC78, 0x80663101,
-+		0xC78, 0x80673101,
-+		0xC78, 0x80683101,
-+		0xC78, 0x80693101,
-+		0xC78, 0x806A3101,
-+		0xC78, 0x806B3101,
-+		0xC78, 0x806C3101,
-+		0xC78, 0x806D3101,
-+		0xC78, 0x806E3101,
-+		0xC78, 0x806F3101,
-+		0xC78, 0x80703101,
-+		0xC78, 0x80713101,
-+		0xC78, 0x80723101,
-+		0xC78, 0x80733101,
-+		0xC78, 0x80743101,
-+		0xC78, 0x80753101,
-+		0xC78, 0x80763101,
-+		0xC78, 0x80773101,
-+		0xC78, 0x80783101,
-+		0xC78, 0x80793101,
-+		0xC78, 0x807A3101,
-+		0xC78, 0x807B3101,
-+		0xC78, 0x807C3101,
-+		0xC78, 0x807D3101,
-+		0xC78, 0x807E3101,
-+		0xC78, 0x807F3101,
-+		0xC78, 0xFF402001,
-+		0xC78, 0xFF412001,
-+		0xC78, 0xFF422001,
-+		0xC78, 0xFF432001,
-+		0xC78, 0xFF442001,
-+		0xC78, 0xFF452001,
-+		0xC78, 0xFF462001,
-+		0xC78, 0xFF472001,
-+		0xC78, 0xFF482001,
-+		0xC78, 0xFF492001,
-+		0xC78, 0xFF4A2001,
-+		0xC78, 0xFF4B2001,
-+		0xC78, 0xFF4C2001,
-+		0xC78, 0xFE4D2001,
-+		0xC78, 0xFD4E2001,
-+		0xC78, 0xFC4F2001,
-+		0xC78, 0xFB502001,
-+		0xC78, 0xFA512001,
-+		0xC78, 0xF9522001,
-+		0xC78, 0xF8532001,
-+		0xC78, 0xF7542001,
-+		0xC78, 0xF6552001,
-+		0xC78, 0xF5562001,
-+		0xC78, 0xF4572001,
-+		0xC78, 0xF3582001,
-+		0xC78, 0xF2592001,
-+		0xC78, 0xF15A2001,
-+		0xC78, 0xF05B2001,
-+		0xC78, 0xEF5C2001,
-+		0xC78, 0xEE5D2001,
-+		0xC78, 0xED5E2001,
-+		0xC78, 0xEC5F2001,
-+		0xC78, 0xEB602001,
-+		0xC78, 0xEA612001,
-+		0xC78, 0xE9622001,
-+		0xC78, 0xE8632001,
-+		0xC78, 0xE7642001,
-+		0xC78, 0xE6652001,
-+		0xC78, 0xE5662001,
-+		0xC78, 0xE4672001,
-+		0xC78, 0xE3682001,
-+		0xC78, 0xC5692001,
-+		0xC78, 0xC46A2001,
-+		0xC78, 0xC36B2001,
-+		0xC78, 0xA46C2001,
-+		0xC78, 0x846D2001,
-+		0xC78, 0x836E2001,
-+		0xC78, 0x826F2001,
-+		0xC78, 0x81702001,
-+		0xC78, 0x80712001,
-+		0xC78, 0x80722001,
-+		0xC78, 0x80732001,
-+		0xC78, 0x80742001,
-+		0xC78, 0x80752001,
-+		0xC78, 0x80762001,
-+		0xC78, 0x80772001,
-+		0xC78, 0x80782001,
-+		0xC78, 0x80792001,
-+		0xC78, 0x807A2001,
-+		0xC78, 0x807B2001,
-+		0xC78, 0x807C2001,
-+		0xC78, 0x807D2001,
-+		0xC78, 0x807E2001,
-+		0xC78, 0x807F2001,
-+		0xC50, 0x69553422,
-+		0xC50, 0x69553420,
-+
-+};
-+
-+void
-+odm_read_and_config_mp_8703b_agc_tab(struct dm_struct *dm)
-+{
-+	u32	i = 0;
-+	u8	c_cond;
-+	boolean	is_matched = true, is_skipped = false;
-+	u32	array_len = sizeof(array_mp_8703b_agc_tab) / sizeof(u32);
-+	u32	*array = array_mp_8703b_agc_tab;
-+
-+	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
-+
-+	while ((i + 1) < array_len) {
-+		v1 = array[i];
-+		v2 = array[i + 1];
-+
-+		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
-+			if (v1 & BIT(31)) {/* positive condition*/
-+				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
-+				if (c_cond == COND_ENDIF) {/*end*/
-+					is_matched = true;
-+					is_skipped = false;
-+					PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
-+				} else if (c_cond == COND_ELSE) { /*else*/
-+					is_matched = is_skipped ? false : true;
-+					PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
-+				} else {/*if , else if*/
-+					pre_v1 = v1;
-+					pre_v2 = v2;
-+					PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
-+				}
-+			} else if (v1 & BIT(30)) { /*negative condition*/
-+				if (is_skipped == false) {
-+					if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
-+						is_matched = true;
-+						is_skipped = true;
-+					} else {
-+						is_matched = false;
-+						is_skipped = false;
-+					}
-+				} else
-+					is_matched = false;
-+			}
-+		} else {
-+			if (is_matched)
-+				odm_config_bb_agc_8703b(dm, v1, MASKDWORD, v2);
-+		}
-+		i = i + 2;
-+	}
-+}
-+
-+u32
-+odm_get_version_mp_8703b_agc_tab(void)
-+{
-+		return 18;
-+}
-+
-+/******************************************************************************
-+*                           phy_reg.TXT
-+******************************************************************************/
-+
-+u32 array_mp_8703b_phy_reg[] = {
-+		0x800, 0x83045700,
-+		0x804, 0x00000003,
-+		0x808, 0x0000FC00,
-+		0x80C, 0x0000000A,
-+		0x810, 0x10001331,
-+		0x814, 0x020C3D10,
-+		0x818, 0x02200385,
-+		0x81C, 0x00000000,
-+		0x820, 0x01000100,
-+		0x824, 0x00390204,
-+		0x828, 0x00000000,
-+		0x82C, 0x00000000,
-+		0x830, 0x00000000,
-+		0x834, 0x00000000,
-+		0x838, 0x00000000,
-+		0x83C, 0x00000000,
-+		0x840, 0x00010000,
-+		0x844, 0x00000000,
-+		0x848, 0x00000000,
-+		0x84C, 0x00000000,
-+		0x850, 0x00000000,
-+		0x854, 0x00000000,
-+		0x858, 0x569A11A9,
-+		0x85C, 0x01000014,
-+		0x860, 0x66F60110,
-+		0x864, 0x061F0649,
-+		0x868, 0x00000000,
-+		0x86C, 0x27272700,
-+		0x870, 0x07000760,
-+		0x874, 0x25004000,
-+		0x878, 0x00000808,
-+		0x87C, 0x004F0201,
-+		0x880, 0xB0000B1E,
-+		0x884, 0x00000001,
-+		0x888, 0x00000000,
-+		0x88C, 0xCCC000C0,
-+		0x890, 0x00000800,
-+		0x894, 0xFFFFFFFE,
-+		0x898, 0x40302010,
-+		0x89C, 0x00706050,
-+		0x900, 0x00000000,
-+		0x904, 0x00000023,
-+		0x908, 0x00000000,
-+		0x90C, 0x81121111,
-+		0x910, 0x00000002,
-+		0x914, 0x00000201,
-+		0x948, 0x99000000,
-+		0x94C, 0x00000010,
-+		0x950, 0x20003800,
-+		0x954, 0x4A880000,
-+		0x958, 0x4BC5D87A,
-+		0x95C, 0x04EB9B79,
-+		0xA00, 0x00D047C8,
-+		0xA04, 0x80FF800C,
-+		0xA08, 0x8C838300,
-+		0xA0C, 0x2E7F120F,
-+		0xA10, 0x9500BB78,
-+		0xA14, 0x1114D028,
-+		0xA18, 0x00881117,
-+		0xA1C, 0x89140F00,
-+		0xA20, 0xD1D80000,
-+		0xA24, 0x5A7DA0BD,
-+		0xA28, 0x0000223B,
-+		0xA2C, 0x00D30000,
-+		0xA70, 0x101FBF00,
-+		0xA74, 0x00000007,
-+		0xA78, 0x00008900,
-+		0xA7C, 0x225B0606,
-+		0xA80, 0x2180FA74,
-+		0xA84, 0x00120000,
-+		0xA88, 0x040C0000,
-+		0xA8C, 0x12345678,
-+		0xA90, 0xABCDEF00,
-+		0xA94, 0x001B1B89,
-+		0xA98, 0x05100000,
-+		0xA9C, 0x3F000000,
-+		0xAA0, 0x00000000,
-+		0xB2C, 0x00000000,
-+		0xC00, 0x48071D40,
-+		0xC04, 0x03A05611,
-+		0xC08, 0x000000E4,
-+		0xC0C, 0x6C6C6C6C,
-+		0xC10, 0x18800000,
-+		0xC14, 0x40000100,
-+		0xC18, 0x08800000,
-+		0xC1C, 0x40000100,
-+		0xC20, 0x00000000,
-+		0xC24, 0x00000000,
-+		0xC28, 0x00000000,
-+		0xC2C, 0x00000000,
-+		0xC30, 0x69E9AC4B,
-+		0xC34, 0x31000040,
-+		0xC38, 0x21688080,
-+		0xC3C, 0x000016CC,
-+		0xC40, 0x1F78403F,
-+		0xC44, 0x00010036,
-+		0xC48, 0xEC020107,
-+		0xC4C, 0x007F037F,
-+		0xC50, 0x69553420,
-+		0xC54, 0x43BC0094,
-+		0xC58, 0x00015967,
-+		0xC5C, 0x18250492,
-+		0xC60, 0x00000000,
-+		0xC64, 0x7112848B,
-+		0xC68, 0x47C07BFF,
-+		0xC6C, 0x00000036,
-+		0xC70, 0x2C7F000D,
-+		0xC74, 0x020600DB,
-+		0xC78, 0x0000001F,
-+		0xC7C, 0x00B91612,
-+		0xC80, 0x390000E4,
-+		0xC84, 0x19F60000,
-+		0xC88, 0x40000100,
-+		0xC8C, 0x20200000,
-+		0xC90, 0x00091521,
-+		0xC94, 0x00000000,
-+		0xC98, 0x00121820,
-+		0xC9C, 0x00007F7F,
-+		0xCA0, 0x00000000,
-+		0xCA4, 0x000300A0,
-+		0xCA8, 0x00000000,
-+		0xCAC, 0x00000000,
-+		0xCB0, 0x00000000,
-+		0xCB4, 0x00000000,
-+		0xCB8, 0x00000000,
-+		0xCBC, 0x28000000,
-+		0xCC0, 0x00000000,
-+		0xCC4, 0x00000000,
-+		0xCC8, 0x00000000,
-+		0xCCC, 0x00000000,
-+		0xCD0, 0x00000000,
-+		0xCD4, 0x00000000,
-+		0xCD8, 0x64B22427,
-+		0xCDC, 0x00766932,
-+		0xCE0, 0x00222222,
-+		0xCE4, 0x10000000,
-+		0xCE8, 0x37644302,
-+		0xCEC, 0x2F97D40C,
-+		0xD00, 0x00030740,
-+		0xD04, 0x40020401,
-+		0xD08, 0x0000907F,
-+		0xD0C, 0x20010201,
-+		0xD10, 0xA0633333,
-+		0xD14, 0x3333BC53,
-+		0xD18, 0x7A8F5B6F,
-+		0xD2C, 0xCB979975,
-+		0xD30, 0x00000000,
-+		0xD34, 0x80608000,
-+		0xD38, 0x98000000,
-+		0xD3C, 0x40127353,
-+		0xD40, 0x00000000,
-+		0xD44, 0x00000000,
-+		0xD48, 0x00000000,
-+		0xD4C, 0x00000000,
-+		0xD50, 0x6437140A,
-+		0xD54, 0x00000000,
-+		0xD58, 0x00000282,
-+		0xD5C, 0x30032064,
-+		0xD60, 0x4653DE68,
-+		0xD64, 0x04518A3C,
-+		0xD68, 0x00002101,
-+		0xE00, 0x2D2D2D2D,
-+		0xE04, 0x2D2D2D2D,
-+		0xE08, 0x0390272D,
-+		0xE10, 0x2D2D2D2D,
-+		0xE14, 0x2D2D2D2D,
-+		0xE18, 0x2D2D2D2D,
-+		0xE1C, 0x2D2D2D2D,
-+		0xE28, 0x00000000,
-+		0xE30, 0x1000DC1F,
-+		0xE34, 0x10008C1F,
-+		0xE38, 0x02140102,
-+		0xE3C, 0x681604C2,
-+		0xE40, 0x01007C00,
-+		0xE44, 0x01004800,
-+		0xE48, 0xFB000000,
-+		0xE4C, 0x000028D1,
-+		0xE50, 0x1000DC1F,
-+		0xE54, 0x10008C1F,
-+		0xE58, 0x02140102,
-+		0xE5C, 0x28160D05,
-+		0xE60, 0x00000048,
-+		0xE68, 0x001B25A4,
-+		0xE6C, 0x01C00014,
-+		0xE70, 0x01C00014,
-+		0xE74, 0x02000014,
-+		0xE78, 0x02000014,
-+		0xE7C, 0x02000014,
-+		0xE80, 0x02000014,
-+		0xE84, 0x01C00014,
-+		0xE88, 0x02000014,
-+		0xE8C, 0x01C00014,
-+		0xED0, 0x01C00014,
-+		0xED4, 0x01C00014,
-+		0xED8, 0x01C00014,
-+		0xEDC, 0x00000014,
-+		0xEE0, 0x00000014,
-+		0xEE8, 0x21555448,
-+		0xEEC, 0x03C00014,
-+		0xF14, 0x00000003,
-+		0xF4C, 0x00000000,
-+		0xF00, 0x00000300,
-+
-+};
-+
-+void
-+odm_read_and_config_mp_8703b_phy_reg(struct dm_struct *dm)
-+{
-+	u32	i = 0;
-+	u8	c_cond;
-+	boolean	is_matched = true, is_skipped = false;
-+	u32	array_len = sizeof(array_mp_8703b_phy_reg) / sizeof(u32);
-+	u32	*array = array_mp_8703b_phy_reg;
-+
-+	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
-+
-+	while ((i + 1) < array_len) {
-+		v1 = array[i];
-+		v2 = array[i + 1];
-+
-+		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
-+			if (v1 & BIT(31)) {/* positive condition*/
-+				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
-+				if (c_cond == COND_ENDIF) {/*end*/
-+					is_matched = true;
-+					is_skipped = false;
-+					PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
-+				} else if (c_cond == COND_ELSE) { /*else*/
-+					is_matched = is_skipped ? false : true;
-+					PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
-+				} else {/*if , else if*/
-+					pre_v1 = v1;
-+					pre_v2 = v2;
-+					PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
-+				}
-+			} else if (v1 & BIT(30)) { /*negative condition*/
-+				if (is_skipped == false) {
-+					if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
-+						is_matched = true;
-+						is_skipped = true;
-+					} else {
-+						is_matched = false;
-+						is_skipped = false;
-+					}
-+				} else
-+					is_matched = false;
-+			}
-+		} else {
-+			if (is_matched)
-+				odm_config_bb_phy_8703b(dm, v1, MASKDWORD, v2);
-+		}
-+		i = i + 2;
-+	}
-+}
-+
-+u32
-+odm_get_version_mp_8703b_phy_reg(void)
-+{
-+		return 18;
-+}
-+
-+/******************************************************************************
-+*                           phy_reg_pg.TXT
-+******************************************************************************/
-+
-+u32 array_mp_8703b_phy_reg_pg[] = {
-+	0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200,
-+	0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200,
-+	0, 0, 0, 0x00000e00, 0xffffffff, 0x34363636,
-+	0, 0, 0, 0x00000e04, 0xffffffff, 0x28303234,
-+	0, 0, 0, 0x00000e10, 0xffffffff, 0x30343434,
-+	0, 0, 0, 0x00000e14, 0xffffffff, 0x26262830
-+};
-+
-+void
-+odm_read_and_config_mp_8703b_phy_reg_pg(struct dm_struct *dm)
-+{
-+	u32	i = 0;
-+	u32	array_len = sizeof(array_mp_8703b_phy_reg_pg) / sizeof(u32);
-+	u32	*array = array_mp_8703b_phy_reg_pg;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void	*adapter = dm->adapter;
-+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+
-+	PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
-+	hal_data->nLinesReadPwrByRate = array_len / 6;
-+#endif
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
-+
-+	dm->phy_reg_pg_version = 1;
-+	dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
-+
-+	for (i = 0; i < array_len; i += 6) {
-+		u32	v1 = array[i];
-+		u32	v2 = array[i + 1];
-+		u32	v3 = array[i + 2];
-+		u32	v4 = array[i + 3];
-+		u32	v5 = array[i + 4];
-+		u32	v6 = array[i + 5];
-+
-+		odm_config_bb_phy_reg_pg_8703b(dm, v1, v2, v3, v4, v5, v6);
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	rsprintf((char *)hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
-+		(v1 == 0 ? "2.4G" : "  5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6);
-+#endif
-+	}
-+}
-+
-+
-+
-+#endif /* end of HWIMG_SUPPORT*/
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_bb.h b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_bb.h
-new file mode 100644
-index 000000000000..1fcd6f99fd68
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_bb.h
-@@ -0,0 +1,51 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/*Image2HeaderVersion: 3.5.2*/
-+#if (RTL8703B_SUPPORT == 1)
-+#ifndef __INC_MP_BB_HW_IMG_8703B_H
-+#define __INC_MP_BB_HW_IMG_8703B_H
-+
-+
-+/******************************************************************************
-+*                           agc_tab.TXT
-+******************************************************************************/
-+
-+void
-+odm_read_and_config_mp_8703b_agc_tab( /* tc: Test Chip, mp: mp Chip*/
-+				     struct dm_struct *dm);
-+u32 odm_get_version_mp_8703b_agc_tab(void);
-+
-+/******************************************************************************
-+*                           phy_reg.TXT
-+******************************************************************************/
-+
-+void
-+odm_read_and_config_mp_8703b_phy_reg( /* tc: Test Chip, mp: mp Chip*/
-+				     struct dm_struct *dm);
-+u32 odm_get_version_mp_8703b_phy_reg(void);
-+
-+/******************************************************************************
-+*                           phy_reg_pg.TXT
-+******************************************************************************/
-+
-+void
-+odm_read_and_config_mp_8703b_phy_reg_pg( /* tc: Test Chip, mp: mp Chip*/
-+					struct dm_struct *dm);
-+u32	odm_get_version_mp_8703b_phy_reg_pg(void);
-+
-+#endif
-+#endif /* end of HWIMG_SUPPORT*/
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_mac.c b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_mac.c
-new file mode 100644
-index 000000000000..28d474a151a6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_mac.c
-@@ -0,0 +1,288 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/*Image2HeaderVersion: 3.5.2*/
-+#include "mp_precomp.h"
-+#include "../phydm_precomp.h"
-+
-+#if (RTL8703B_SUPPORT == 1)
-+static boolean
-+check_positive(
-+	struct dm_struct *dm,
-+	const u32	condition1,
-+	const u32	condition2,
-+	const u32	condition3,
-+	const u32	condition4
-+)
-+{
-+	u8	_board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
-+			((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
-+			((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
-+			((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
-+			((dm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/
-+			((dm->board_type & BIT(1)) >> 1) << 5 | /* _NGFF*/
-+			((dm->board_type & BIT(5)) >> 5) << 6;  /* _TRSWT*/
-+
-+	u32	cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
-+
-+	u8	cut_version_for_para = (dm->cut_version ==  ODM_CUT_A) ? 15 : dm->cut_version;
-+	u8	pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type;
-+
-+	u32	driver1 = cut_version_for_para << 24 |
-+			(dm->support_interface & 0xF0) << 16 |
-+			dm->support_platform << 16 |
-+			pkg_type_for_para << 12 |
-+			(dm->support_interface & 0x0F) << 8  |
-+			_board_type;
-+
-+	u32	driver2 = (dm->type_glna & 0xFF) <<  0 |
-+			(dm->type_gpa & 0xFF)  <<  8 |
-+			(dm->type_alna & 0xFF) << 16 |
-+			(dm->type_apa & 0xFF)  << 24;
-+
-+	u32	driver3 = 0;
-+
-+	u32	driver4 = (dm->type_glna & 0xFF00) >>  8 |
-+			(dm->type_gpa & 0xFF00) |
-+			(dm->type_alna & 0xFF00) << 8 |
-+			(dm->type_apa & 0xFF00)  << 16;
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
-+		  __func__, cond1, cond2, cond3, cond4);
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
-+		  __func__, driver1, driver2, driver3, driver4);
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "	(Platform, Interface) = (0x%X, 0x%X)\n",
-+		  dm->support_platform, dm->support_interface);
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "	(Board, Package) = (0x%X, 0x%X)\n", dm->board_type,
-+		  dm->package_type);
-+
-+
-+	/*============== value Defined Check ===============*/
-+	/*QFN type [15:12] and cut version [27:24] need to do value check*/
-+
-+	if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
-+		return false;
-+	if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
-+		return false;
-+
-+	/*=============== Bit Defined Check ================*/
-+	/* We don't care [31:28] */
-+
-+	cond1 &= 0x00FF0FFF;
-+	driver1 &= 0x00FF0FFF;
-+
-+	if ((cond1 & driver1) == cond1) {
-+		u32	bit_mask = 0;
-+
-+		if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
-+			return true;
-+
-+		if ((cond1 & BIT(0)) != 0) /*GLNA*/
-+			bit_mask |= 0x000000FF;
-+		if ((cond1 & BIT(1)) != 0) /*GPA*/
-+			bit_mask |= 0x0000FF00;
-+		if ((cond1 & BIT(2)) != 0) /*ALNA*/
-+			bit_mask |= 0x00FF0000;
-+		if ((cond1 & BIT(3)) != 0) /*APA*/
-+			bit_mask |= 0xFF000000;
-+
-+		if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask)))  /* board_type of each RF path is matched*/
-+			return true;
-+		else
-+			return false;
-+	} else
-+		return false;
-+}
-+
-+/******************************************************************************
-+*                           mac_reg.TXT
-+******************************************************************************/
-+
-+u32 array_mp_8703b_mac_reg[] = {
-+		0x02F, 0x00000030,
-+		0x035, 0x00000000,
-+		0x067, 0x00000002,
-+		0x092, 0x00000080,
-+		0x421, 0x0000000F,
-+		0x428, 0x0000000A,
-+		0x429, 0x00000010,
-+		0x430, 0x00000000,
-+		0x431, 0x00000000,
-+		0x432, 0x00000000,
-+		0x433, 0x00000001,
-+		0x434, 0x00000002,
-+		0x435, 0x00000003,
-+		0x436, 0x00000005,
-+		0x437, 0x00000007,
-+		0x438, 0x00000000,
-+		0x439, 0x00000000,
-+		0x43A, 0x00000000,
-+		0x43B, 0x00000001,
-+		0x43C, 0x00000002,
-+		0x43D, 0x00000003,
-+		0x43E, 0x00000005,
-+		0x43F, 0x00000007,
-+		0x440, 0x0000005D,
-+		0x441, 0x00000001,
-+		0x442, 0x00000000,
-+		0x444, 0x00000010,
-+		0x445, 0x00000000,
-+		0x446, 0x00000000,
-+		0x447, 0x00000000,
-+		0x448, 0x00000000,
-+		0x449, 0x000000F0,
-+		0x44A, 0x0000000F,
-+		0x44B, 0x0000003E,
-+		0x44C, 0x00000010,
-+		0x44D, 0x00000000,
-+		0x44E, 0x00000000,
-+		0x44F, 0x00000000,
-+		0x450, 0x00000000,
-+		0x451, 0x000000F0,
-+		0x452, 0x0000000F,
-+		0x453, 0x00000000,
-+		0x456, 0x0000005E,
-+		0x460, 0x00000066,
-+		0x461, 0x00000066,
-+		0x4C8, 0x000000FF,
-+		0x4C9, 0x00000008,
-+		0x4CC, 0x000000FF,
-+		0x4CD, 0x000000FF,
-+		0x4CE, 0x00000001,
-+		0x500, 0x00000026,
-+		0x501, 0x000000A2,
-+		0x502, 0x0000002F,
-+		0x503, 0x00000000,
-+		0x504, 0x00000028,
-+		0x505, 0x000000A3,
-+		0x506, 0x0000005E,
-+		0x507, 0x00000000,
-+		0x508, 0x0000002B,
-+		0x509, 0x000000A4,
-+		0x50A, 0x0000005E,
-+		0x50B, 0x00000000,
-+		0x50C, 0x0000004F,
-+		0x50D, 0x000000A4,
-+		0x50E, 0x00000000,
-+		0x50F, 0x00000000,
-+		0x512, 0x0000001C,
-+		0x514, 0x0000000A,
-+		0x516, 0x0000000A,
-+		0x525, 0x0000004F,
-+		0x550, 0x00000010,
-+		0x551, 0x00000010,
-+		0x559, 0x00000002,
-+		0x55C, 0x00000028,
-+		0x55D, 0x000000FF,
-+		0x605, 0x00000030,
-+		0x608, 0x0000000E,
-+		0x609, 0x0000002A,
-+		0x620, 0x000000FF,
-+		0x621, 0x000000FF,
-+		0x622, 0x000000FF,
-+		0x623, 0x000000FF,
-+		0x624, 0x000000FF,
-+		0x625, 0x000000FF,
-+		0x626, 0x000000FF,
-+		0x627, 0x000000FF,
-+		0x638, 0x00000028,
-+		0x63C, 0x0000000A,
-+		0x63D, 0x0000000A,
-+		0x63E, 0x0000000C,
-+		0x63F, 0x0000000C,
-+		0x640, 0x00000040,
-+		0x642, 0x00000040,
-+		0x643, 0x00000000,
-+		0x652, 0x000000C8,
-+		0x66A, 0x000000B0,
-+		0x66E, 0x00000005,
-+		0x700, 0x00000021,
-+		0x701, 0x00000043,
-+		0x702, 0x00000065,
-+		0x703, 0x00000087,
-+		0x708, 0x00000021,
-+		0x709, 0x00000043,
-+		0x70A, 0x00000065,
-+		0x70B, 0x00000087,
-+		0x765, 0x00000018,
-+		0x76E, 0x00000004,
-+
-+};
-+
-+void
-+odm_read_and_config_mp_8703b_mac_reg(struct dm_struct *dm)
-+{
-+	u32	i = 0;
-+	u8	c_cond;
-+	boolean	is_matched = true, is_skipped = false;
-+	u32	array_len = sizeof(array_mp_8703b_mac_reg) / sizeof(u32);
-+	u32	*array = array_mp_8703b_mac_reg;
-+
-+	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
-+
-+	while ((i + 1) < array_len) {
-+		v1 = array[i];
-+		v2 = array[i + 1];
-+
-+		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
-+			if (v1 & BIT(31)) {/* positive condition*/
-+				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
-+				if (c_cond == COND_ENDIF) {/*end*/
-+					is_matched = true;
-+					is_skipped = false;
-+					PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
-+				} else if (c_cond == COND_ELSE) { /*else*/
-+					is_matched = is_skipped ? false : true;
-+					PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
-+				} else {/*if , else if*/
-+					pre_v1 = v1;
-+					pre_v2 = v2;
-+					PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
-+				}
-+			} else if (v1 & BIT(30)) { /*negative condition*/
-+				if (is_skipped == false) {
-+					if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
-+						is_matched = true;
-+						is_skipped = true;
-+					} else {
-+						is_matched = false;
-+						is_skipped = false;
-+					}
-+				} else
-+					is_matched = false;
-+			}
-+		} else {
-+			if (is_matched)
-+				odm_config_mac_8703b(dm, v1, (u8)v2);
-+		}
-+		i = i + 2;
-+	}
-+}
-+
-+u32
-+odm_get_version_mp_8703b_mac_reg(void)
-+{
-+		return 18;
-+}
-+
-+#endif /* end of HWIMG_SUPPORT*/
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_mac.h b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_mac.h
-new file mode 100644
-index 000000000000..365c40aed6c6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_mac.h
-@@ -0,0 +1,33 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/*Image2HeaderVersion: 3.5.2*/
-+#if (RTL8703B_SUPPORT == 1)
-+#ifndef __INC_MP_MAC_HW_IMG_8703B_H
-+#define __INC_MP_MAC_HW_IMG_8703B_H
-+
-+
-+/******************************************************************************
-+*                           mac_reg.TXT
-+******************************************************************************/
-+
-+void
-+odm_read_and_config_mp_8703b_mac_reg( /* tc: Test Chip, mp: mp Chip*/
-+				     struct dm_struct *dm);
-+u32 odm_get_version_mp_8703b_mac_reg(void);
-+
-+#endif
-+#endif /* end of HWIMG_SUPPORT*/
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_rf.c b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_rf.c
-new file mode 100644
-index 000000000000..dae9e05b6f99
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_rf.c
-@@ -0,0 +1,997 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/*Image2HeaderVersion: 3.5.2*/
-+#include "mp_precomp.h"
-+#include "../phydm_precomp.h"
-+
-+#if (RTL8703B_SUPPORT == 1)
-+static boolean
-+check_positive(
-+	struct dm_struct *dm,
-+	const u32	condition1,
-+	const u32	condition2,
-+	const u32	condition3,
-+	const u32	condition4
-+)
-+{
-+	u8	_board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
-+			((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
-+			((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
-+			((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
-+			((dm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/
-+			((dm->board_type & BIT(1)) >> 1) << 5 | /* _NGFF*/
-+			((dm->board_type & BIT(5)) >> 5) << 6;  /* _TRSWT*/
-+
-+	u32	cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
-+
-+	u8	cut_version_for_para = (dm->cut_version ==  ODM_CUT_A) ? 15 : dm->cut_version;
-+	u8	pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type;
-+
-+	u32	driver1 = cut_version_for_para << 24 |
-+			(dm->support_interface & 0xF0) << 16 |
-+			dm->support_platform << 16 |
-+			pkg_type_for_para << 12 |
-+			(dm->support_interface & 0x0F) << 8  |
-+			_board_type;
-+
-+	u32	driver2 = (dm->type_glna & 0xFF) <<  0 |
-+			(dm->type_gpa & 0xFF)  <<  8 |
-+			(dm->type_alna & 0xFF) << 16 |
-+			(dm->type_apa & 0xFF)  << 24;
-+
-+	u32	driver3 = 0;
-+
-+	u32	driver4 = (dm->type_glna & 0xFF00) >>  8 |
-+			(dm->type_gpa & 0xFF00) |
-+			(dm->type_alna & 0xFF00) << 8 |
-+			(dm->type_apa & 0xFF00)  << 16;
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
-+		  __func__, cond1, cond2, cond3, cond4);
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
-+		  __func__, driver1, driver2, driver3, driver4);
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "	(Platform, Interface) = (0x%X, 0x%X)\n",
-+		  dm->support_platform, dm->support_interface);
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "	(Board, Package) = (0x%X, 0x%X)\n", dm->board_type,
-+		  dm->package_type);
-+
-+
-+	/*============== value Defined Check ===============*/
-+	/*QFN type [15:12] and cut version [27:24] need to do value check*/
-+
-+	if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
-+		return false;
-+	if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
-+		return false;
-+
-+	/*=============== Bit Defined Check ================*/
-+	/* We don't care [31:28] */
-+
-+	cond1 &= 0x00FF0FFF;
-+	driver1 &= 0x00FF0FFF;
-+
-+	if ((cond1 & driver1) == cond1) {
-+		u32	bit_mask = 0;
-+
-+		if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
-+			return true;
-+
-+		if ((cond1 & BIT(0)) != 0) /*GLNA*/
-+			bit_mask |= 0x000000FF;
-+		if ((cond1 & BIT(1)) != 0) /*GPA*/
-+			bit_mask |= 0x0000FF00;
-+		if ((cond1 & BIT(2)) != 0) /*ALNA*/
-+			bit_mask |= 0x00FF0000;
-+		if ((cond1 & BIT(3)) != 0) /*APA*/
-+			bit_mask |= 0xFF000000;
-+
-+		if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask)))  /* board_type of each RF path is matched*/
-+			return true;
-+		else
-+			return false;
-+	} else
-+		return false;
-+}
-+
-+/******************************************************************************
-+*                           radioa.TXT
-+******************************************************************************/
-+
-+u32 array_mp_8703b_radioa[] = {
-+		0x018, 0x00008C01,
-+		0x0B5, 0x0008C050,
-+		0x0B1, 0x00054258,
-+		0x0B2, 0x00054C00,
-+		0x030, 0x00018000,
-+		0x031, 0x00000027,
-+		0x032, 0x000A7F07,
-+		0x030, 0x00020000,
-+		0x031, 0x00000027,
-+		0x032, 0x000E7D87,
-+		0x01C, 0x000F8635,
-+		0x0EF, 0x00080000,
-+		0x030, 0x00008000,
-+		0x031, 0x00000004,
-+		0x032, 0x00006105,
-+		0x0EF, 0x00000000,
-+		0x0EF, 0x00000400,
-+		0x041, 0x0000BD54,
-+		0x041, 0x00003DD4,
-+		0x041, 0x0000FDD4,
-+		0x0EF, 0x00000000,
-+		0x0DF, 0x00000600,
-+		0x050, 0x0000C6DB,
-+		0x051, 0x00004505,
-+		0x052, 0x0000E31D,
-+		0x053, 0x00040579,
-+		0x054, 0x00000000,
-+		0x055, 0x0008206E,
-+		0x056, 0x00040000,
-+		0x0EF, 0x00000100,
-+		0x034, 0x0000ADD7,
-+		0x034, 0x00009DD4,
-+		0x034, 0x00008DD1,
-+		0x034, 0x00007DCE,
-+		0x034, 0x00006DCB,
-+		0x034, 0x00005CCE,
-+		0x034, 0x000048CD,
-+		0x034, 0x000034CC,
-+		0x034, 0x0000244F,
-+		0x034, 0x0000144C,
-+		0x034, 0x0000004E,
-+		0x0EF, 0x00000000,
-+		0x0EF, 0x00002000,
-+		0x03B, 0x0003801F,
-+		0x03B, 0x00030002,
-+		0x03B, 0x00028001,
-+		0x03B, 0x00020000,
-+		0x03B, 0x00018003,
-+		0x03B, 0x00010002,
-+		0x03B, 0x00008001,
-+		0x03B, 0x00000000,
-+		0x0EF, 0x00000000,
-+		0x082, 0x000C0000,
-+		0x083, 0x000AF025,
-+		0x01E, 0x00000C08,
-+
-+};
-+
-+void
-+odm_read_and_config_mp_8703b_radioa(struct dm_struct *dm)
-+{
-+	u32	i = 0;
-+	u8	c_cond;
-+	boolean	is_matched = true, is_skipped = false;
-+	u32	array_len = sizeof(array_mp_8703b_radioa) / sizeof(u32);
-+	u32	*array = array_mp_8703b_radioa;
-+
-+	u32	v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
-+
-+	while ((i + 1) < array_len) {
-+		v1 = array[i];
-+		v2 = array[i + 1];
-+
-+		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
-+			if (v1 & BIT(31)) {/* positive condition*/
-+				c_cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
-+				if (c_cond == COND_ENDIF) {/*end*/
-+					is_matched = true;
-+					is_skipped = false;
-+					PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
-+				} else if (c_cond == COND_ELSE) { /*else*/
-+					is_matched = is_skipped ? false : true;
-+					PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
-+				} else {/*if , else if*/
-+					pre_v1 = v1;
-+					pre_v2 = v2;
-+					PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
-+				}
-+			} else if (v1 & BIT(30)) { /*negative condition*/
-+				if (is_skipped == false) {
-+					if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
-+						is_matched = true;
-+						is_skipped = true;
-+					} else {
-+						is_matched = false;
-+						is_skipped = false;
-+					}
-+				} else
-+					is_matched = false;
-+			}
-+		} else {
-+			if (is_matched)
-+				odm_config_rf_radio_a_8703b(dm, v1, v2);
-+		}
-+		i = i + 2;
-+	}
-+}
-+
-+u32
-+odm_get_version_mp_8703b_radioa(void)
-+{
-+		return 18;
-+}
-+
-+/******************************************************************************
-+*                           txpowertrack_sdio.TXT
-+******************************************************************************/
-+
-+#if DEV_BUS_TYPE == RT_SDIO_INTERFACE
-+u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_sdio_8703b[][DELTA_SWINGIDX_SIZE] = {
-+	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18},
-+	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
-+	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
-+};
-+u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_sdio_8703b[][DELTA_SWINGIDX_SIZE] = {
-+	{0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
-+	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
-+	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
-+};
-+u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_sdio_8703b[][DELTA_SWINGIDX_SIZE] = {
-+	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18},
-+	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
-+	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
-+};
-+u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_sdio_8703b[][DELTA_SWINGIDX_SIZE] = {
-+	{0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
-+	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
-+	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
-+};
-+u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_sdio_8703b[]    = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
-+u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_sdio_8703b[]    = {0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15};
-+u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_sdio_8703b[]    = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
-+u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_sdio_8703b[]    = {0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15};
-+u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_sdio_8703b[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
-+u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_sdio_8703b[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13};
-+u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_sdio_8703b[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
-+u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_sdio_8703b[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13};
-+#endif
-+
-+void
-+odm_read_and_config_mp_8703b_txpowertrack_sdio(struct dm_struct *dm)
-+{
-+#if DEV_BUS_TYPE == RT_SDIO_INTERFACE
-+	struct dm_rf_calibration_struct  *cali_info = &(dm->rf_calibrate_info);
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8703b\n");
-+
-+
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_sdio_8703b, DELTA_SWINGIDX_SIZE);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_sdio_8703b, DELTA_SWINGIDX_SIZE);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_sdio_8703b, DELTA_SWINGIDX_SIZE);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_sdio_8703b, DELTA_SWINGIDX_SIZE);
-+
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_sdio_8703b, DELTA_SWINGIDX_SIZE);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_sdio_8703b, DELTA_SWINGIDX_SIZE);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_sdio_8703b, DELTA_SWINGIDX_SIZE);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_sdio_8703b, DELTA_SWINGIDX_SIZE);
-+
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_sdio_8703b, DELTA_SWINGIDX_SIZE * 3);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_sdio_8703b, DELTA_SWINGIDX_SIZE * 3);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_sdio_8703b, DELTA_SWINGIDX_SIZE * 3);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_sdio_8703b, DELTA_SWINGIDX_SIZE * 3);
-+#endif
-+}
-+
-+/******************************************************************************
-+*                           txpowertrack_usb.TXT
-+******************************************************************************/
-+
-+#if DEV_BUS_TYPE == RT_USB_INTERFACE
-+u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_usb_8703b[][DELTA_SWINGIDX_SIZE] = {
-+	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18},
-+	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
-+	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
-+};
-+u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_usb_8703b[][DELTA_SWINGIDX_SIZE] = {
-+	{0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
-+	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
-+	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
-+};
-+u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_usb_8703b[][DELTA_SWINGIDX_SIZE] = {
-+	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18},
-+	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
-+	{0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18},
-+};
-+u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_usb_8703b[][DELTA_SWINGIDX_SIZE] = {
-+	{0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
-+	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
-+	{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15},
-+};
-+u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_usb_8703b[]    = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
-+u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_usb_8703b[]    = {0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15};
-+u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_usb_8703b[]    = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
-+u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_usb_8703b[]    = {0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15};
-+u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_usb_8703b[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
-+u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_usb_8703b[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13};
-+u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_usb_8703b[] = {0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
-+u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_usb_8703b[] = {0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13};
-+#endif
-+
-+void
-+odm_read_and_config_mp_8703b_txpowertrack_usb(struct dm_struct *dm)
-+{
-+#if DEV_BUS_TYPE == RT_USB_INTERFACE
-+	struct dm_rf_calibration_struct  *cali_info = &(dm->rf_calibrate_info);
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8703b\n");
-+
-+
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_usb_8703b, DELTA_SWINGIDX_SIZE);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_usb_8703b, DELTA_SWINGIDX_SIZE);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_usb_8703b, DELTA_SWINGIDX_SIZE);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_usb_8703b, DELTA_SWINGIDX_SIZE);
-+
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_usb_8703b, DELTA_SWINGIDX_SIZE);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_usb_8703b, DELTA_SWINGIDX_SIZE);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_usb_8703b, DELTA_SWINGIDX_SIZE);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_usb_8703b, DELTA_SWINGIDX_SIZE);
-+
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_usb_8703b, DELTA_SWINGIDX_SIZE * 3);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_usb_8703b, DELTA_SWINGIDX_SIZE * 3);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_usb_8703b, DELTA_SWINGIDX_SIZE * 3);
-+	odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_usb_8703b, DELTA_SWINGIDX_SIZE * 3);
-+#endif
-+}
-+
-+/******************************************************************************
-+*                           txpwr_lmt.TXT
-+******************************************************************************/
-+
-+const char *array_mp_8703b_txpwr_lmt[] = {
-+	"FCC", "2.4G", "20M", "CCK", "1T", "01", "30",
-+	"ETSI", "2.4G", "20M", "CCK", "1T", "01", "26",
-+	"MKK", "2.4G", "20M", "CCK", "1T", "01", "32",
-+	"FCC", "2.4G", "20M", "CCK", "1T", "02", "30",
-+	"ETSI", "2.4G", "20M", "CCK", "1T", "02", "26",
-+	"MKK", "2.4G", "20M", "CCK", "1T", "02", "32",
-+	"FCC", "2.4G", "20M", "CCK", "1T", "03", "30",
-+	"ETSI", "2.4G", "20M", "CCK", "1T", "03", "26",
-+	"MKK", "2.4G", "20M", "CCK", "1T", "03", "32",
-+	"FCC", "2.4G", "20M", "CCK", "1T", "04", "30",
-+	"ETSI", "2.4G", "20M", "CCK", "1T", "04", "26",
-+	"MKK", "2.4G", "20M", "CCK", "1T", "04", "32",
-+	"FCC", "2.4G", "20M", "CCK", "1T", "05", "30",
-+	"ETSI", "2.4G", "20M", "CCK", "1T", "05", "26",
-+	"MKK", "2.4G", "20M", "CCK", "1T", "05", "32",
-+	"FCC", "2.4G", "20M", "CCK", "1T", "06", "30",
-+	"ETSI", "2.4G", "20M", "CCK", "1T", "06", "26",
-+	"MKK", "2.4G", "20M", "CCK", "1T", "06", "32",
-+	"FCC", "2.4G", "20M", "CCK", "1T", "07", "30",
-+	"ETSI", "2.4G", "20M", "CCK", "1T", "07", "26",
-+	"MKK", "2.4G", "20M", "CCK", "1T", "07", "32",
-+	"FCC", "2.4G", "20M", "CCK", "1T", "08", "30",
-+	"ETSI", "2.4G", "20M", "CCK", "1T", "08", "26",
-+	"MKK", "2.4G", "20M", "CCK", "1T", "08", "32",
-+	"FCC", "2.4G", "20M", "CCK", "1T", "09", "30",
-+	"ETSI", "2.4G", "20M", "CCK", "1T", "09", "26",
-+	"MKK", "2.4G", "20M", "CCK", "1T", "09", "32",
-+	"FCC", "2.4G", "20M", "CCK", "1T", "10", "30",
-+	"ETSI", "2.4G", "20M", "CCK", "1T", "10", "26",
-+	"MKK", "2.4G", "20M", "CCK", "1T", "10", "32",
-+	"FCC", "2.4G", "20M", "CCK", "1T", "11", "30",
-+	"ETSI", "2.4G", "20M", "CCK", "1T", "11", "26",
-+	"MKK", "2.4G", "20M", "CCK", "1T", "11", "32",
-+	"FCC", "2.4G", "20M", "CCK", "1T", "12", "63",
-+	"ETSI", "2.4G", "20M", "CCK", "1T", "12", "26",
-+	"MKK", "2.4G", "20M", "CCK", "1T", "12", "32",
-+	"FCC", "2.4G", "20M", "CCK", "1T", "13", "63",
-+	"ETSI", "2.4G", "20M", "CCK", "1T", "13", "26",
-+	"MKK", "2.4G", "20M", "CCK", "1T", "13", "32",
-+	"FCC", "2.4G", "20M", "CCK", "1T", "14", "63",
-+	"ETSI", "2.4G", "20M", "CCK", "1T", "14", "63",
-+	"MKK", "2.4G", "20M", "CCK", "1T", "14", "32",
-+	"FCC", "2.4G", "20M", "OFDM", "1T", "01", "28",
-+	"ETSI", "2.4G", "20M", "OFDM", "1T", "01", "28",
-+	"MKK", "2.4G", "20M", "OFDM", "1T", "01", "28",
-+	"FCC", "2.4G", "20M", "OFDM", "1T", "02", "28",
-+	"ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32",
-+	"MKK", "2.4G", "20M", "OFDM", "1T", "02", "32",
-+	"FCC", "2.4G", "20M", "OFDM", "1T", "03", "32",
-+	"ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32",
-+	"MKK", "2.4G", "20M", "OFDM", "1T", "03", "32",
-+	"FCC", "2.4G", "20M", "OFDM", "1T", "04", "32",
-+	"ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32",
-+	"MKK", "2.4G", "20M", "OFDM", "1T", "04", "32",
-+	"FCC", "2.4G", "20M", "OFDM", "1T", "05", "32",
-+	"ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32",
-+	"MKK", "2.4G", "20M", "OFDM", "1T", "05", "32",
-+	"FCC", "2.4G", "20M", "OFDM", "1T", "06", "32",
-+	"ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32",
-+	"MKK", "2.4G", "20M", "OFDM", "1T", "06", "32",
-+	"FCC", "2.4G", "20M", "OFDM", "1T", "07", "32",
-+	"ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32",
-+	"MKK", "2.4G", "20M", "OFDM", "1T", "07", "32",
-+	"FCC", "2.4G", "20M", "OFDM", "1T", "08", "32",
-+	"ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32",
-+	"MKK", "2.4G", "20M", "OFDM", "1T", "08", "32",
-+	"FCC", "2.4G", "20M", "OFDM", "1T", "09", "32",
-+	"ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32",
-+	"MKK", "2.4G", "20M", "OFDM", "1T", "09", "32",
-+	"FCC", "2.4G", "20M", "OFDM", "1T", "10", "28",
-+	"ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32",
-+	"MKK", "2.4G", "20M", "OFDM", "1T", "10", "32",
-+	"FCC", "2.4G", "20M", "OFDM", "1T", "11", "28",
-+	"ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32",
-+	"MKK", "2.4G", "20M", "OFDM", "1T", "11", "32",
-+	"FCC", "2.4G", "20M", "OFDM", "1T", "12", "63",
-+	"ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32",
-+	"MKK", "2.4G", "20M", "OFDM", "1T", "12", "32",
-+	"FCC", "2.4G", "20M", "OFDM", "1T", "13", "63",
-+	"ETSI", "2.4G", "20M", "OFDM", "1T", "13", "28",
-+	"MKK", "2.4G", "20M", "OFDM", "1T", "13", "28",
-+	"FCC", "2.4G", "20M", "OFDM", "1T", "14", "63",
-+	"ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63",
-+	"MKK", "2.4G", "20M", "OFDM", "1T", "14", "63",
-+	"FCC", "2.4G", "20M", "HT", "1T", "01", "26",
-+	"ETSI", "2.4G", "20M", "HT", "1T", "01", "26",
-+	"MKK", "2.4G", "20M", "HT", "1T", "01", "28",
-+	"FCC", "2.4G", "20M", "HT", "1T", "02", "26",
-+	"ETSI", "2.4G", "20M", "HT", "1T", "02", "32",
-+	"MKK", "2.4G", "20M", "HT", "1T", "02", "32",
-+	"FCC", "2.4G", "20M", "HT", "1T", "03", "32",
-+	"ETSI", "2.4G", "20M", "HT", "1T", "03", "32",
-+	"MKK", "2.4G", "20M", "HT", "1T", "03", "32",
-+	"FCC", "2.4G", "20M", "HT", "1T", "04", "32",
-+	"ETSI", "2.4G", "20M", "HT", "1T", "04", "32",
-+	"MKK", "2.4G", "20M", "HT", "1T", "04", "32",
-+	"FCC", "2.4G", "20M", "HT", "1T", "05", "32",
-+	"ETSI", "2.4G", "20M", "HT", "1T", "05", "32",
-+	"MKK", "2.4G", "20M", "HT", "1T", "05", "32",
-+	"FCC", "2.4G", "20M", "HT", "1T", "06", "32",
-+	"ETSI", "2.4G", "20M", "HT", "1T", "06", "32",
-+	"MKK", "2.4G", "20M", "HT", "1T", "06", "32",
-+	"FCC", "2.4G", "20M", "HT", "1T", "07", "32",
-+	"ETSI", "2.4G", "20M", "HT", "1T", "07", "32",
-+	"MKK", "2.4G", "20M", "HT", "1T", "07", "32",
-+	"FCC", "2.4G", "20M", "HT", "1T", "08", "32",
-+	"ETSI", "2.4G", "20M", "HT", "1T", "08", "32",
-+	"MKK", "2.4G", "20M", "HT", "1T", "08", "32",
-+	"FCC", "2.4G", "20M", "HT", "1T", "09", "32",
-+	"ETSI", "2.4G", "20M", "HT", "1T", "09", "32",
-+	"MKK", "2.4G", "20M", "HT", "1T", "09", "32",
-+	"FCC", "2.4G", "20M", "HT", "1T", "10", "26",
-+	"ETSI", "2.4G", "20M", "HT", "1T", "10", "32",
-+	"MKK", "2.4G", "20M", "HT", "1T", "10", "32",
-+	"FCC", "2.4G", "20M", "HT", "1T", "11", "26",
-+	"ETSI", "2.4G", "20M", "HT", "1T", "11", "32",
-+	"MKK", "2.4G", "20M", "HT", "1T", "11", "32",
-+	"FCC", "2.4G", "20M", "HT", "1T", "12", "63",
-+	"ETSI", "2.4G", "20M", "HT", "1T", "12", "32",
-+	"MKK", "2.4G", "20M", "HT", "1T", "12", "32",
-+	"FCC", "2.4G", "20M", "HT", "1T", "13", "63",
-+	"ETSI", "2.4G", "20M", "HT", "1T", "13", "26",
-+	"MKK", "2.4G", "20M", "HT", "1T", "13", "28",
-+	"FCC", "2.4G", "20M", "HT", "1T", "14", "63",
-+	"ETSI", "2.4G", "20M", "HT", "1T", "14", "63",
-+	"MKK", "2.4G", "20M", "HT", "1T", "14", "63",
-+	"FCC", "2.4G", "20M", "HT", "2T", "01", "28",
-+	"ETSI", "2.4G", "20M", "HT", "2T", "01", "30",
-+	"MKK", "2.4G", "20M", "HT", "2T", "01", "30",
-+	"FCC", "2.4G", "20M", "HT", "2T", "02", "28",
-+	"ETSI", "2.4G", "20M", "HT", "2T", "02", "30",
-+	"MKK", "2.4G", "20M", "HT", "2T", "02", "30",
-+	"FCC", "2.4G", "20M", "HT", "2T", "03", "30",
-+	"ETSI", "2.4G", "20M", "HT", "2T", "03", "30",
-+	"MKK", "2.4G", "20M", "HT", "2T", "03", "30",
-+	"FCC", "2.4G", "20M", "HT", "2T", "04", "30",
-+	"ETSI", "2.4G", "20M", "HT", "2T", "04", "30",
-+	"MKK", "2.4G", "20M", "HT", "2T", "04", "30",
-+	"FCC", "2.4G", "20M", "HT", "2T", "05", "30",
-+	"ETSI", "2.4G", "20M", "HT", "2T", "05", "30",
-+	"MKK", "2.4G", "20M", "HT", "2T", "05", "30",
-+	"FCC", "2.4G", "20M", "HT", "2T", "06", "30",
-+	"ETSI", "2.4G", "20M", "HT", "2T", "06", "30",
-+	"MKK", "2.4G", "20M", "HT", "2T", "06", "30",
-+	"FCC", "2.4G", "20M", "HT", "2T", "07", "30",
-+	"ETSI", "2.4G", "20M", "HT", "2T", "07", "30",
-+	"MKK", "2.4G", "20M", "HT", "2T", "07", "30",
-+	"FCC", "2.4G", "20M", "HT", "2T", "08", "30",
-+	"ETSI", "2.4G", "20M", "HT", "2T", "08", "30",
-+	"MKK", "2.4G", "20M", "HT", "2T", "08", "30",
-+	"FCC", "2.4G", "20M", "HT", "2T", "09", "28",
-+	"ETSI", "2.4G", "20M", "HT", "2T", "09", "30",
-+	"MKK", "2.4G", "20M", "HT", "2T", "09", "30",
-+	"FCC", "2.4G", "20M", "HT", "2T", "10", "28",
-+	"ETSI", "2.4G", "20M", "HT", "2T", "10", "30",
-+	"MKK", "2.4G", "20M", "HT", "2T", "10", "30",
-+	"FCC", "2.4G", "20M", "HT", "2T", "11", "28",
-+	"ETSI", "2.4G", "20M", "HT", "2T", "11", "30",
-+	"MKK", "2.4G", "20M", "HT", "2T", "11", "30",
-+	"FCC", "2.4G", "20M", "HT", "2T", "12", "63",
-+	"ETSI", "2.4G", "20M", "HT", "2T", "12", "30",
-+	"MKK", "2.4G", "20M", "HT", "2T", "12", "30",
-+	"FCC", "2.4G", "20M", "HT", "2T", "13", "63",
-+	"ETSI", "2.4G", "20M", "HT", "2T", "13", "30",
-+	"MKK", "2.4G", "20M", "HT", "2T", "13", "30",
-+	"FCC", "2.4G", "20M", "HT", "2T", "14", "63",
-+	"ETSI", "2.4G", "20M", "HT", "2T", "14", "63",
-+	"MKK", "2.4G", "20M", "HT", "2T", "14", "63",
-+	"FCC", "2.4G", "40M", "HT", "1T", "01", "63",
-+	"ETSI", "2.4G", "40M", "HT", "1T", "01", "63",
-+	"MKK", "2.4G", "40M", "HT", "1T", "01", "63",
-+	"FCC", "2.4G", "40M", "HT", "1T", "02", "63",
-+	"ETSI", "2.4G", "40M", "HT", "1T", "02", "63",
-+	"MKK", "2.4G", "40M", "HT", "1T", "02", "63",
-+	"FCC", "2.4G", "40M", "HT", "1T", "03", "26",
-+	"ETSI", "2.4G", "40M", "HT", "1T", "03", "26",
-+	"MKK", "2.4G", "40M", "HT", "1T", "03", "26",
-+	"FCC", "2.4G", "40M", "HT", "1T", "04", "26",
-+	"ETSI", "2.4G", "40M", "HT", "1T", "04", "28",
-+	"MKK", "2.4G", "40M", "HT", "1T", "04", "26",
-+	"FCC", "2.4G", "40M", "HT", "1T", "05", "28",
-+	"ETSI", "2.4G", "40M", "HT", "1T", "05", "28",
-+	"MKK", "2.4G", "40M", "HT", "1T", "05", "26",
-+	"FCC", "2.4G", "40M", "HT", "1T", "06", "28",
-+	"ETSI", "2.4G", "40M", "HT", "1T", "06", "28",
-+	"MKK", "2.4G", "40M", "HT", "1T", "06", "26",
-+	"FCC", "2.4G", "40M", "HT", "1T", "07", "28",
-+	"ETSI", "2.4G", "40M", "HT", "1T", "07", "28",
-+	"MKK", "2.4G", "40M", "HT", "1T", "07", "26",
-+	"FCC", "2.4G", "40M", "HT", "1T", "08", "26",
-+	"ETSI", "2.4G", "40M", "HT", "1T", "08", "28",
-+	"MKK", "2.4G", "40M", "HT", "1T", "08", "26",
-+	"FCC", "2.4G", "40M", "HT", "1T", "09", "26",
-+	"ETSI", "2.4G", "40M", "HT", "1T", "09", "28",
-+	"MKK", "2.4G", "40M", "HT", "1T", "09", "26",
-+	"FCC", "2.4G", "40M", "HT", "1T", "10", "26",
-+	"ETSI", "2.4G", "40M", "HT", "1T", "10", "28",
-+	"MKK", "2.4G", "40M", "HT", "1T", "10", "26",
-+	"FCC", "2.4G", "40M", "HT", "1T", "11", "26",
-+	"ETSI", "2.4G", "40M", "HT", "1T", "11", "26",
-+	"MKK", "2.4G", "40M", "HT", "1T", "11", "26",
-+	"FCC", "2.4G", "40M", "HT", "1T", "12", "63",
-+	"ETSI", "2.4G", "40M", "HT", "1T", "12", "26",
-+	"MKK", "2.4G", "40M", "HT", "1T", "12", "26",
-+	"FCC", "2.4G", "40M", "HT", "1T", "13", "63",
-+	"ETSI", "2.4G", "40M", "HT", "1T", "13", "26",
-+	"MKK", "2.4G", "40M", "HT", "1T", "13", "26",
-+	"FCC", "2.4G", "40M", "HT", "1T", "14", "63",
-+	"ETSI", "2.4G", "40M", "HT", "1T", "14", "63",
-+	"MKK", "2.4G", "40M", "HT", "1T", "14", "63",
-+	"FCC", "2.4G", "40M", "HT", "2T", "01", "63",
-+	"ETSI", "2.4G", "40M", "HT", "2T", "01", "63",
-+	"MKK", "2.4G", "40M", "HT", "2T", "01", "63",
-+	"FCC", "2.4G", "40M", "HT", "2T", "02", "63",
-+	"ETSI", "2.4G", "40M", "HT", "2T", "02", "63",
-+	"MKK", "2.4G", "40M", "HT", "2T", "02", "63",
-+	"FCC", "2.4G", "40M", "HT", "2T", "03", "26",
-+	"ETSI", "2.4G", "40M", "HT", "2T", "03", "26",
-+	"MKK", "2.4G", "40M", "HT", "2T", "03", "26",
-+	"FCC", "2.4G", "40M", "HT", "2T", "04", "26",
-+	"ETSI", "2.4G", "40M", "HT", "2T", "04", "26",
-+	"MKK", "2.4G", "40M", "HT", "2T", "04", "26",
-+	"FCC", "2.4G", "40M", "HT", "2T", "05", "26",
-+	"ETSI", "2.4G", "40M", "HT", "2T", "05", "26",
-+	"MKK", "2.4G", "40M", "HT", "2T", "05", "26",
-+	"FCC", "2.4G", "40M", "HT", "2T", "06", "26",
-+	"ETSI", "2.4G", "40M", "HT", "2T", "06", "26",
-+	"MKK", "2.4G", "40M", "HT", "2T", "06", "26",
-+	"FCC", "2.4G", "40M", "HT", "2T", "07", "26",
-+	"ETSI", "2.4G", "40M", "HT", "2T", "07", "26",
-+	"MKK", "2.4G", "40M", "HT", "2T", "07", "26",
-+	"FCC", "2.4G", "40M", "HT", "2T", "08", "26",
-+	"ETSI", "2.4G", "40M", "HT", "2T", "08", "26",
-+	"MKK", "2.4G", "40M", "HT", "2T", "08", "26",
-+	"FCC", "2.4G", "40M", "HT", "2T", "09", "26",
-+	"ETSI", "2.4G", "40M", "HT", "2T", "09", "26",
-+	"MKK", "2.4G", "40M", "HT", "2T", "09", "26",
-+	"FCC", "2.4G", "40M", "HT", "2T", "10", "26",
-+	"ETSI", "2.4G", "40M", "HT", "2T", "10", "26",
-+	"MKK", "2.4G", "40M", "HT", "2T", "10", "26",
-+	"FCC", "2.4G", "40M", "HT", "2T", "11", "26",
-+	"ETSI", "2.4G", "40M", "HT", "2T", "11", "26",
-+	"MKK", "2.4G", "40M", "HT", "2T", "11", "26",
-+	"FCC", "2.4G", "40M", "HT", "2T", "12", "63",
-+	"ETSI", "2.4G", "40M", "HT", "2T", "12", "26",
-+	"MKK", "2.4G", "40M", "HT", "2T", "12", "26",
-+	"FCC", "2.4G", "40M", "HT", "2T", "13", "63",
-+	"ETSI", "2.4G", "40M", "HT", "2T", "13", "26",
-+	"MKK", "2.4G", "40M", "HT", "2T", "13", "26",
-+	"FCC", "2.4G", "40M", "HT", "2T", "14", "63",
-+	"ETSI", "2.4G", "40M", "HT", "2T", "14", "63",
-+	"MKK", "2.4G", "40M", "HT", "2T", "14", "63",
-+	"FCC", "5G", "20M", "OFDM", "1T", "36", "30",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "36", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "36", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "40", "30",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "40", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "40", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "44", "30",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "44", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "44", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "48", "30",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "48", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "48", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "52", "34",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "52", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "52", "32",
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-+	"ETSI", "5G", "20M", "OFDM", "1T", "56", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "56", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "60", "32",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "60", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "60", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "64", "28",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "64", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "64", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "100", "30",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "100", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "100", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "114", "30",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "114", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "114", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "108", "32",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "108", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "108", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "112", "34",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "112", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "112", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "116", "34",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "116", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "116", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "120", "34",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "120", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "120", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "124", "34",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "124", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "124", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "128", "32",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "128", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "128", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "132", "30",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "132", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "132", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "136", "30",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "136", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "136", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "140", "28",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "140", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "140", "32",
-+	"FCC", "5G", "20M", "OFDM", "1T", "149", "34",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "149", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "149", "63",
-+	"FCC", "5G", "20M", "OFDM", "1T", "153", "34",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "153", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "153", "63",
-+	"FCC", "5G", "20M", "OFDM", "1T", "157", "34",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "157", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "157", "63",
-+	"FCC", "5G", "20M", "OFDM", "1T", "161", "34",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "161", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "161", "63",
-+	"FCC", "5G", "20M", "OFDM", "1T", "165", "34",
-+	"ETSI", "5G", "20M", "OFDM", "1T", "165", "32",
-+	"MKK", "5G", "20M", "OFDM", "1T", "165", "63",
-+	"FCC", "5G", "20M", "HT", "1T", "36", "30",
-+	"ETSI", "5G", "20M", "HT", "1T", "36", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "36", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "40", "30",
-+	"ETSI", "5G", "20M", "HT", "1T", "40", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "40", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "44", "30",
-+	"ETSI", "5G", "20M", "HT", "1T", "44", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "44", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "48", "30",
-+	"ETSI", "5G", "20M", "HT", "1T", "48", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "48", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "52", "34",
-+	"ETSI", "5G", "20M", "HT", "1T", "52", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "52", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "56", "34",
-+	"ETSI", "5G", "20M", "HT", "1T", "56", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "56", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "60", "32",
-+	"ETSI", "5G", "20M", "HT", "1T", "60", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "60", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "64", "28",
-+	"ETSI", "5G", "20M", "HT", "1T", "64", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "64", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "100", "30",
-+	"ETSI", "5G", "20M", "HT", "1T", "100", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "100", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "114", "30",
-+	"ETSI", "5G", "20M", "HT", "1T", "114", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "114", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "108", "32",
-+	"ETSI", "5G", "20M", "HT", "1T", "108", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "108", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "112", "34",
-+	"ETSI", "5G", "20M", "HT", "1T", "112", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "112", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "116", "34",
-+	"ETSI", "5G", "20M", "HT", "1T", "116", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "116", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "120", "34",
-+	"ETSI", "5G", "20M", "HT", "1T", "120", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "120", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "124", "34",
-+	"ETSI", "5G", "20M", "HT", "1T", "124", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "124", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "128", "32",
-+	"ETSI", "5G", "20M", "HT", "1T", "128", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "128", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "132", "30",
-+	"ETSI", "5G", "20M", "HT", "1T", "132", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "132", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "136", "30",
-+	"ETSI", "5G", "20M", "HT", "1T", "136", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "136", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "140", "28",
-+	"ETSI", "5G", "20M", "HT", "1T", "140", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "140", "32",
-+	"FCC", "5G", "20M", "HT", "1T", "149", "34",
-+	"ETSI", "5G", "20M", "HT", "1T", "149", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "149", "63",
-+	"FCC", "5G", "20M", "HT", "1T", "153", "34",
-+	"ETSI", "5G", "20M", "HT", "1T", "153", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "153", "63",
-+	"FCC", "5G", "20M", "HT", "1T", "157", "34",
-+	"ETSI", "5G", "20M", "HT", "1T", "157", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "157", "63",
-+	"FCC", "5G", "20M", "HT", "1T", "161", "34",
-+	"ETSI", "5G", "20M", "HT", "1T", "161", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "161", "63",
-+	"FCC", "5G", "20M", "HT", "1T", "165", "34",
-+	"ETSI", "5G", "20M", "HT", "1T", "165", "32",
-+	"MKK", "5G", "20M", "HT", "1T", "165", "63",
-+	"FCC", "5G", "20M", "HT", "2T", "36", "28",
-+	"ETSI", "5G", "20M", "HT", "2T", "36", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "36", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "40", "28",
-+	"ETSI", "5G", "20M", "HT", "2T", "40", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "40", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "44", "28",
-+	"ETSI", "5G", "20M", "HT", "2T", "44", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "44", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "48", "28",
-+	"ETSI", "5G", "20M", "HT", "2T", "48", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "48", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "52", "34",
-+	"ETSI", "5G", "20M", "HT", "2T", "52", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "52", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "56", "32",
-+	"ETSI", "5G", "20M", "HT", "2T", "56", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "56", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "60", "30",
-+	"ETSI", "5G", "20M", "HT", "2T", "60", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "60", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "64", "26",
-+	"ETSI", "5G", "20M", "HT", "2T", "64", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "64", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "100", "28",
-+	"ETSI", "5G", "20M", "HT", "2T", "100", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "100", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "114", "28",
-+	"ETSI", "5G", "20M", "HT", "2T", "114", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "114", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "108", "30",
-+	"ETSI", "5G", "20M", "HT", "2T", "108", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "108", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "112", "32",
-+	"ETSI", "5G", "20M", "HT", "2T", "112", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "112", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "116", "32",
-+	"ETSI", "5G", "20M", "HT", "2T", "116", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "116", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "120", "34",
-+	"ETSI", "5G", "20M", "HT", "2T", "120", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "120", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "124", "32",
-+	"ETSI", "5G", "20M", "HT", "2T", "124", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "124", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "128", "30",
-+	"ETSI", "5G", "20M", "HT", "2T", "128", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "128", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "132", "28",
-+	"ETSI", "5G", "20M", "HT", "2T", "132", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "132", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "136", "28",
-+	"ETSI", "5G", "20M", "HT", "2T", "136", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "136", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "140", "26",
-+	"ETSI", "5G", "20M", "HT", "2T", "140", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "140", "30",
-+	"FCC", "5G", "20M", "HT", "2T", "149", "34",
-+	"ETSI", "5G", "20M", "HT", "2T", "149", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "149", "63",
-+	"FCC", "5G", "20M", "HT", "2T", "153", "34",
-+	"ETSI", "5G", "20M", "HT", "2T", "153", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "153", "63",
-+	"FCC", "5G", "20M", "HT", "2T", "157", "34",
-+	"ETSI", "5G", "20M", "HT", "2T", "157", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "157", "63",
-+	"FCC", "5G", "20M", "HT", "2T", "161", "34",
-+	"ETSI", "5G", "20M", "HT", "2T", "161", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "161", "63",
-+	"FCC", "5G", "20M", "HT", "2T", "165", "34",
-+	"ETSI", "5G", "20M", "HT", "2T", "165", "30",
-+	"MKK", "5G", "20M", "HT", "2T", "165", "63",
-+	"FCC", "5G", "40M", "HT", "1T", "38", "30",
-+	"ETSI", "5G", "40M", "HT", "1T", "38", "32",
-+	"MKK", "5G", "40M", "HT", "1T", "38", "32",
-+	"FCC", "5G", "40M", "HT", "1T", "46", "30",
-+	"ETSI", "5G", "40M", "HT", "1T", "46", "32",
-+	"MKK", "5G", "40M", "HT", "1T", "46", "32",
-+	"FCC", "5G", "40M", "HT", "1T", "54", "32",
-+	"ETSI", "5G", "40M", "HT", "1T", "54", "32",
-+	"MKK", "5G", "40M", "HT", "1T", "54", "32",
-+	"FCC", "5G", "40M", "HT", "1T", "62", "32",
-+	"ETSI", "5G", "40M", "HT", "1T", "62", "32",
-+	"MKK", "5G", "40M", "HT", "1T", "62", "32",
-+	"FCC", "5G", "40M", "HT", "1T", "102", "28",
-+	"ETSI", "5G", "40M", "HT", "1T", "102", "32",
-+	"MKK", "5G", "40M", "HT", "1T", "102", "32",
-+	"FCC", "5G", "40M", "HT", "1T", "110", "32",
-+	"ETSI", "5G", "40M", "HT", "1T", "110", "32",
-+	"MKK", "5G", "40M", "HT", "1T", "110", "32",
-+	"FCC", "5G", "40M", "HT", "1T", "118", "34",
-+	"ETSI", "5G", "40M", "HT", "1T", "118", "32",
-+	"MKK", "5G", "40M", "HT", "1T", "118", "32",
-+	"FCC", "5G", "40M", "HT", "1T", "126", "34",
-+	"ETSI", "5G", "40M", "HT", "1T", "126", "32",
-+	"MKK", "5G", "40M", "HT", "1T", "126", "32",
-+	"FCC", "5G", "40M", "HT", "1T", "134", "32",
-+	"ETSI", "5G", "40M", "HT", "1T", "134", "32",
-+	"MKK", "5G", "40M", "HT", "1T", "134", "32",
-+	"FCC", "5G", "40M", "HT", "1T", "151", "34",
-+	"ETSI", "5G", "40M", "HT", "1T", "151", "32",
-+	"MKK", "5G", "40M", "HT", "1T", "151", "63",
-+	"FCC", "5G", "40M", "HT", "1T", "159", "34",
-+	"ETSI", "5G", "40M", "HT", "1T", "159", "32",
-+	"MKK", "5G", "40M", "HT", "1T", "159", "63",
-+	"FCC", "5G", "40M", "HT", "2T", "38", "28",
-+	"ETSI", "5G", "40M", "HT", "2T", "38", "30",
-+	"MKK", "5G", "40M", "HT", "2T", "38", "30",
-+	"FCC", "5G", "40M", "HT", "2T", "46", "28",
-+	"ETSI", "5G", "40M", "HT", "2T", "46", "30",
-+	"MKK", "5G", "40M", "HT", "2T", "46", "30",
-+	"FCC", "5G", "40M", "HT", "2T", "54", "30",
-+	"ETSI", "5G", "40M", "HT", "2T", "54", "30",
-+	"MKK", "5G", "40M", "HT", "2T", "54", "30",
-+	"FCC", "5G", "40M", "HT", "2T", "62", "30",
-+	"ETSI", "5G", "40M", "HT", "2T", "62", "30",
-+	"MKK", "5G", "40M", "HT", "2T", "62", "30",
-+	"FCC", "5G", "40M", "HT", "2T", "102", "26",
-+	"ETSI", "5G", "40M", "HT", "2T", "102", "30",
-+	"MKK", "5G", "40M", "HT", "2T", "102", "30",
-+	"FCC", "5G", "40M", "HT", "2T", "110", "30",
-+	"ETSI", "5G", "40M", "HT", "2T", "110", "30",
-+	"MKK", "5G", "40M", "HT", "2T", "110", "30",
-+	"FCC", "5G", "40M", "HT", "2T", "118", "34",
-+	"ETSI", "5G", "40M", "HT", "2T", "118", "30",
-+	"MKK", "5G", "40M", "HT", "2T", "118", "30",
-+	"FCC", "5G", "40M", "HT", "2T", "126", "32",
-+	"ETSI", "5G", "40M", "HT", "2T", "126", "30",
-+	"MKK", "5G", "40M", "HT", "2T", "126", "30",
-+	"FCC", "5G", "40M", "HT", "2T", "134", "30",
-+	"ETSI", "5G", "40M", "HT", "2T", "134", "30",
-+	"MKK", "5G", "40M", "HT", "2T", "134", "30",
-+	"FCC", "5G", "40M", "HT", "2T", "151", "34",
-+	"ETSI", "5G", "40M", "HT", "2T", "151", "30",
-+	"MKK", "5G", "40M", "HT", "2T", "151", "63",
-+	"FCC", "5G", "40M", "HT", "2T", "159", "34",
-+	"ETSI", "5G", "40M", "HT", "2T", "159", "30",
-+	"MKK", "5G", "40M", "HT", "2T", "159", "63",
-+	"FCC", "5G", "80M", "VHT", "1T", "42", "30",
-+	"ETSI", "5G", "80M", "VHT", "1T", "42", "32",
-+	"MKK", "5G", "80M", "VHT", "1T", "42", "32",
-+	"FCC", "5G", "80M", "VHT", "1T", "58", "28",
-+	"ETSI", "5G", "80M", "VHT", "1T", "58", "32",
-+	"MKK", "5G", "80M", "VHT", "1T", "58", "32",
-+	"FCC", "5G", "80M", "VHT", "1T", "106", "30",
-+	"ETSI", "5G", "80M", "VHT", "1T", "106", "32",
-+	"MKK", "5G", "80M", "VHT", "1T", "106", "32",
-+	"FCC", "5G", "80M", "VHT", "1T", "122", "34",
-+	"ETSI", "5G", "80M", "VHT", "1T", "122", "32",
-+	"MKK", "5G", "80M", "VHT", "1T", "122", "32",
-+	"FCC", "5G", "80M", "VHT", "1T", "155", "34",
-+	"ETSI", "5G", "80M", "VHT", "1T", "155", "32",
-+	"MKK", "5G", "80M", "VHT", "1T", "155", "63",
-+	"FCC", "5G", "80M", "VHT", "2T", "42", "28",
-+	"ETSI", "5G", "80M", "VHT", "2T", "42", "30",
-+	"MKK", "5G", "80M", "VHT", "2T", "42", "30",
-+	"FCC", "5G", "80M", "VHT", "2T", "58", "26",
-+	"ETSI", "5G", "80M", "VHT", "2T", "58", "30",
-+	"MKK", "5G", "80M", "VHT", "2T", "58", "30",
-+	"FCC", "5G", "80M", "VHT", "2T", "106", "28",
-+	"ETSI", "5G", "80M", "VHT", "2T", "106", "30",
-+	"MKK", "5G", "80M", "VHT", "2T", "106", "30",
-+	"FCC", "5G", "80M", "VHT", "2T", "122", "32",
-+	"ETSI", "5G", "80M", "VHT", "2T", "122", "30",
-+	"MKK", "5G", "80M", "VHT", "2T", "122", "30",
-+	"FCC", "5G", "80M", "VHT", "2T", "155", "34",
-+	"ETSI", "5G", "80M", "VHT", "2T", "155", "30",
-+	"MKK", "5G", "80M", "VHT", "2T", "155", "63"
-+};
-+
-+void
-+odm_read_and_config_mp_8703b_txpwr_lmt(struct dm_struct *dm)
-+{
-+	u32	i = 0;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+	u32	array_len = sizeof(array_mp_8703b_txpwr_lmt) / sizeof(u8);
-+	u8	*array = (u8 *)array_mp_8703b_txpwr_lmt;
-+#else
-+	u32	array_len = sizeof(array_mp_8703b_txpwr_lmt) / sizeof(u8 *);
-+	u8	**array = (u8 **)array_mp_8703b_txpwr_lmt;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void	*adapter = dm->adapter;
-+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+
-+	PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
-+	hal_data->nLinesReadPwrLmt = array_len / 7;
-+#endif
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
-+
-+	for (i = 0; i < array_len; i += 7) {
-+#if (DM_ODM_SUPPORT_TYPE == ODM_IOT)
-+		u8	regulation = array[i];
-+		u8	band = array[i + 1];
-+		u8	bandwidth = array[i + 2];
-+		u8	rate = array[i + 3];
-+		u8	rf_path = array[i + 4];
-+		u8	chnl = array[i + 5];
-+		u8	val = array[i + 6];
-+#else
-+		u8	*regulation = array[i];
-+		u8	*band = array[i + 1];
-+		u8	*bandwidth = array[i + 2];
-+		u8	*rate = array[i + 3];
-+		u8	*rf_path = array[i + 4];
-+		u8	*chnl = array[i + 5];
-+		u8	*val = array[i + 6];
-+#endif
-+
-+		odm_config_bb_txpwr_lmt_8703b(dm, regulation, band, bandwidth, rate, rf_path, chnl, val);
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+		rsprintf((char *)hal_data->BufOfLinesPwrLmt[i / 7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",",
-+		regulation, band, bandwidth, rate, rf_path, chnl, val);
-+#endif
-+	}
-+}
-+
-+/******************************************************************************
-+*                           txxtaltrack.TXT
-+******************************************************************************/
-+
-+s8 g_delta_swing_table_xtal_mp_n_txxtaltrack_8703b[]    = {0, 0, 0, -1, -1, -1, -1, -2, -2, -2, -3, -3, -3, -3, -3, -4, -2, -2, -1, -1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1};
-+s8 g_delta_swing_table_xtal_mp_p_txxtaltrack_8703b[]    = {0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 1, 0, -1, -1, -1, -2, -3, -7, -9, -10, -11, -14, -16, -18, -20, -22, -24, -26, -28, -30};
-+
-+void
-+odm_read_and_config_mp_8703b_txxtaltrack(struct dm_struct *dm)
-+{
-+	struct dm_rf_calibration_struct	*cali_info = &(dm->rf_calibrate_info);
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8703b\n");
-+
-+
-+	odm_move_memory(dm, cali_info->delta_swing_table_xtal_p, g_delta_swing_table_xtal_mp_p_txxtaltrack_8703b, DELTA_SWINGIDX_SIZE);
-+	odm_move_memory(dm, cali_info->delta_swing_table_xtal_n, g_delta_swing_table_xtal_mp_n_txxtaltrack_8703b, DELTA_SWINGIDX_SIZE);
-+}
-+
-+#endif /* end of HWIMG_SUPPORT*/
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_rf.h b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_rf.h
-new file mode 100644
-index 000000000000..3f596a9c594a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/halhwimg8703b_rf.h
-@@ -0,0 +1,69 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/*Image2HeaderVersion: 3.5.2*/
-+#if (RTL8703B_SUPPORT == 1)
-+#ifndef __INC_MP_RF_HW_IMG_8703B_H
-+#define __INC_MP_RF_HW_IMG_8703B_H
-+
-+
-+/******************************************************************************
-+*                           radioa.TXT
-+******************************************************************************/
-+
-+void
-+odm_read_and_config_mp_8703b_radioa( /* tc: Test Chip, mp: mp Chip*/
-+				    struct dm_struct *dm);
-+u32 odm_get_version_mp_8703b_radioa(void);
-+
-+/******************************************************************************
-+*                           txpowertrack_sdio.TXT
-+******************************************************************************/
-+
-+void
-+odm_read_and_config_mp_8703b_txpowertrack_sdio( /* tc: Test Chip, mp: mp Chip*/
-+					       struct dm_struct *dm);
-+u32	odm_get_version_mp_8703b_txpowertrack_sdio(void);
-+
-+/******************************************************************************
-+*                           txpowertrack_usb.TXT
-+******************************************************************************/
-+
-+void
-+odm_read_and_config_mp_8703b_txpowertrack_usb( /* tc: Test Chip, mp: mp Chip*/
-+					      struct dm_struct *dm);
-+u32	odm_get_version_mp_8703b_txpowertrack_usb(void);
-+
-+/******************************************************************************
-+*                           txpwr_lmt.TXT
-+******************************************************************************/
-+
-+void
-+odm_read_and_config_mp_8703b_txpwr_lmt( /* tc: Test Chip, mp: mp Chip*/
-+				       struct dm_struct *dm);
-+u32	odm_get_version_mp_8703b_txpwr_lmt(void);
-+
-+/******************************************************************************
-+*                           txxtaltrack.TXT
-+******************************************************************************/
-+
-+void
-+odm_read_and_config_mp_8703b_txxtaltrack( /* tc: Test Chip, mp: mp Chip*/
-+					 struct dm_struct *dm);
-+u32	odm_get_version_mp_8703b_txxtaltrack(void);
-+
-+#endif
-+#endif /* end of HWIMG_SUPPORT*/
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/phydm_regconfig8703b.c b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/phydm_regconfig8703b.c
-new file mode 100644
-index 000000000000..b5808c7966f4
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/phydm_regconfig8703b.c
-@@ -0,0 +1,167 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "../phydm_precomp.h"
-+
-+#if (RTL8703B_SUPPORT == 1)
-+
-+void odm_config_rf_reg_8703b(struct dm_struct *dm, u32 addr, u32 data,
-+			     enum rf_path RF_PATH, u32 reg_addr)
-+{
-+	if (addr == 0xfe || addr == 0xffe) {
-+#ifdef CONFIG_LONG_DELAY_ISSUE
-+		ODM_sleep_ms(50);
-+#else
-+		ODM_delay_ms(50);
-+#endif
-+	} else {
-+		odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
-+		/* Add 1us delay between BB/RF register setting. */
-+		ODM_delay_us(1);
-+	}
-+}
-+
-+void odm_config_rf_radio_a_8703b(struct dm_struct *dm, u32 addr, u32 data)
-+{
-+	u32 content = 0x1000; /* RF_Content: radioa_txt */
-+	u32 maskfor_phy_set = (u32)(content & 0xE000);
-+
-+	odm_config_rf_reg_8703b(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
-+		  addr, data);
-+}
-+
-+void odm_config_rf_radio_b_8703b(struct dm_struct *dm, u32 addr, u32 data)
-+{
-+	u32 content = 0x1001; /* RF_Content: radiob_txt */
-+	u32 maskfor_phy_set = (u32)(content & 0xE000);
-+
-+	odm_config_rf_reg_8703b(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n",
-+		  addr, data);
-+}
-+
-+void odm_config_rf_radio_c_8703b(struct dm_struct *dm, u32 addr, u32 data)
-+{
-+	u32 content = 0x1001; /* RF_Content: radiob_txt */
-+	u32 maskfor_phy_set = (u32)(content & 0xE000);
-+
-+	odm_config_rf_reg_8703b(dm, addr, data, RF_PATH_C, addr | maskfor_phy_set);
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "===> odm_config_rf_with_header_file: [RadioC] %08X %08X\n",
-+		  addr, data);
-+}
-+
-+void odm_config_rf_radio_d_8703b(struct dm_struct *dm, u32 addr, u32 data)
-+{
-+	u32 content = 0x1001; /* RF_Content: radiob_txt */
-+	u32 maskfor_phy_set = (u32)(content & 0xE000);
-+
-+	odm_config_rf_reg_8703b(dm, addr, data, RF_PATH_D, addr | maskfor_phy_set);
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "===> odm_config_rf_with_header_file: [RadioD] %08X %08X\n",
-+		  addr, data);
-+}
-+
-+void odm_config_mac_8703b(struct dm_struct *dm, u32 addr, u8 data)
-+{
-+	odm_write_1byte(dm, addr, data);
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n",
-+		  addr, data);
-+}
-+
-+void odm_config_bb_agc_8703b(struct dm_struct *dm, u32 addr, u32 bitmask,
-+			     u32 data)
-+{
-+	odm_set_bb_reg(dm, addr, bitmask, data);
-+	/* Add 1us delay between BB/RF register setting. */
-+	ODM_delay_us(1);
-+
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n",
-+		  addr, data);
-+}
-+
-+void odm_config_bb_phy_reg_pg_8703b(struct dm_struct *dm, u32 band, u32 rf_path,
-+				    u32 tx_num, u32 addr, u32 bitmask, u32 data)
-+{
-+	if (addr == 0xfe || addr == 0xffe)
-+#ifdef CONFIG_LONG_DELAY_ISSUE
-+		ODM_sleep_ms(50);
-+#else
-+		ODM_delay_ms(50);
-+#endif
-+	else {
-+#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+		phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+		PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
-+#endif
-+	}
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n",
-+		  addr, bitmask, data);
-+}
-+
-+void odm_config_bb_phy_8703b(struct dm_struct *dm, u32 addr, u32 bitmask,
-+			     u32 data)
-+{
-+	if (addr == 0xfe)
-+#ifdef CONFIG_LONG_DELAY_ISSUE
-+		ODM_sleep_ms(50);
-+#else
-+		ODM_delay_ms(50);
-+#endif
-+	else if (addr == 0xfd)
-+		ODM_delay_ms(5);
-+	else if (addr == 0xfc)
-+		ODM_delay_ms(1);
-+	else if (addr == 0xfb)
-+		ODM_delay_us(50);
-+	else if (addr == 0xfa)
-+		ODM_delay_us(5);
-+	else if (addr == 0xf9)
-+		ODM_delay_us(1);
-+	else
-+		odm_set_bb_reg(dm, addr, bitmask, data);
-+
-+	/* Add 1us delay between BB/RF register setting. */
-+	ODM_delay_us(1);
-+	PHYDM_DBG(dm, ODM_COMP_INIT,
-+		  "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n",
-+		  addr, data);
-+}
-+
-+void odm_config_bb_txpwr_lmt_8703b(struct dm_struct *dm, u8 *regulation,
-+				   u8 *band, u8 *bandwidth, u8 *rate_section,
-+				   u8 *rf_path, u8 *channel, u8 *power_limit)
-+{
-+#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
-+	phy_set_tx_power_limit(dm, regulation, band,
-+			       bandwidth, rate_section, rf_path, channel, power_limit);
-+#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-+	PHY_SetTxPowerLimit(dm, regulation, band,
-+			    bandwidth, rate_section, rf_path, channel, power_limit);
-+#endif
-+}
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/phydm_regconfig8703b.h b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/phydm_regconfig8703b.h
-new file mode 100644
-index 000000000000..bd2f649da520
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/phydm_regconfig8703b.h
-@@ -0,0 +1,47 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_ODM_REGCONFIG_H_8703B
-+#define __INC_ODM_REGCONFIG_H_8703B
-+
-+#if (RTL8703B_SUPPORT == 1)
-+
-+void odm_config_rf_reg_8703b(struct dm_struct *dm, u32 addr, u32 data,
-+			     enum rf_path RF_PATH, u32 reg_addr);
-+
-+void odm_config_rf_radio_a_8703b(struct dm_struct *dm, u32 addr, u32 data);
-+
-+void odm_config_rf_radio_b_8703b(struct dm_struct *dm, u32 addr, u32 data);
-+
-+void odm_config_rf_radio_c_8703b(struct dm_struct *dm, u32 addr, u32 data);
-+
-+void odm_config_rf_radio_d_8703b(struct dm_struct *dm, u32 addr, u32 data);
-+
-+void odm_config_mac_8703b(struct dm_struct *dm, u32 addr, u8 data);
-+
-+void odm_config_bb_agc_8703b(struct dm_struct *dm, u32 addr, u32 bitmask,
-+			     u32 data);
-+
-+void odm_config_bb_phy_reg_pg_8703b(struct dm_struct *dm, u32 band, u32 rf_path,
-+				    u32 tx_num, u32 addr, u32 bitmask,
-+				    u32 data);
-+
-+void odm_config_bb_phy_8703b(struct dm_struct *dm, u32 addr, u32 bitmask,
-+			     u32 data);
-+
-+void odm_config_bb_txpwr_lmt_8703b(struct dm_struct *dm, u8 *regulation,
-+				   u8 *band, u8 *bandwidth, u8 *rate_section,
-+				   u8 *rf_path, u8 *channel, u8 *power_limit);
-+#endif
-+#endif /* end of SUPPORT */
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/phydm_rtl8703b.c b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/phydm_rtl8703b.c
-new file mode 100644
-index 000000000000..394f4640336c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/phydm_rtl8703b.c
-@@ -0,0 +1,53 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "../phydm_precomp.h"
-+#if (RTL8703B_SUPPORT == 1)
-+s8 phydm_cck_rssi_8703b(struct dm_struct *dm, u16 lna_idx, u8 vga_idx)
-+{
-+	s8 rx_pwr_all = 0x00;
-+
-+	switch (lna_idx) {
-+	case 0xf:
-+		rx_pwr_all = -48 - (2 * vga_idx);
-+		break;
-+	case 0xb:
-+		rx_pwr_all = -42 - (2 * vga_idx); /*TBD*/
-+		break;
-+	case 0xa:
-+		rx_pwr_all = -36 - (2 * vga_idx);
-+		break;
-+	case 8:
-+		rx_pwr_all = -32 - (2 * vga_idx);
-+		break;
-+	case 7:
-+		rx_pwr_all = -19 - (2 * vga_idx);
-+		break;
-+	case 4:
-+		rx_pwr_all = -6 - (2 * vga_idx);
-+		break;
-+	case 0:
-+		rx_pwr_all = -2 - (2 * vga_idx);
-+		break;
-+	default:
-+		/*rx_pwr_all = -53+(2*(31-vga_idx));*/
-+		/*dbg_print("wrong LNA index\n");*/
-+		break;
-+	}
-+	return rx_pwr_all;
-+}
-+#endif
-+
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/phydm_rtl8703b.h b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/phydm_rtl8703b.h
-new file mode 100644
-index 000000000000..28f9196cb47e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/phydm_rtl8703b.h
-@@ -0,0 +1,21 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __ODM_RTL8703B_H__
-+#define __ODM_RTL8703B_H__
-+#if (RTL8703B_SUPPORT == 1)
-+s8 phydm_cck_rssi_8703b(struct dm_struct *dm, u16 lna_idx, u8 vga_idx);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/version_rtl8703b.h b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/version_rtl8703b.h
-new file mode 100644
-index 000000000000..b78e42fd0bc4
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/rtl8703b/version_rtl8703b.h
-@@ -0,0 +1,24 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*RTL8703B PHY Parameters*/
-+/*
-+[Caution]
-+  Since 01/Aug/2015, the commit rules will be simplified.
-+  You do not need to fill up the version.h anymore,
-+  only the maintenance supervisor fills it before formal release.
-+*/
-+#define	RELEASE_DATE_8703B		20170801
-+#define	COMMIT_BY_8703B			"BB_Dino"
-+#define	RELEASE_VERSION_8703B	18
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/sd4_phydm_2_kernel.mk b/drivers/staging/rtl8723cs/hal/phydm/sd4_phydm_2_kernel.mk
-new file mode 100644
-index 000000000000..09898476eded
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/sd4_phydm_2_kernel.mk
-@@ -0,0 +1,188 @@
-+EXTRA_CFLAGS += -I$(srctree)/$(src)/hal/phydm
-+
-+_PHYDM_FILES := hal/phydm/phydm_debug.o	\
-+								hal/phydm/phydm_interface.o\
-+								hal/phydm/phydm_phystatus.o\
-+								hal/phydm/phydm_hwconfig.o\
-+								hal/phydm/phydm.o\
-+								hal/phydm/phydm_dig.o\
-+								hal/phydm/phydm_rainfo.o\
-+								hal/phydm/phydm_adaptivity.o\
-+								hal/phydm/phydm_cfotracking.o\
-+								hal/phydm/phydm_noisemonitor.o\
-+								hal/phydm/phydm_beamforming.o\
-+								hal/phydm/phydm_dfs.o\
-+								hal/phydm/txbf/halcomtxbf.o\
-+								hal/phydm/txbf/haltxbfinterface.o\
-+								hal/phydm/txbf/phydm_hal_txbf_api.o\
-+								hal/phydm/phydm_ccx.o\
-+								hal/phydm/phydm_cck_pd.o\
-+								hal/phydm/phydm_rssi_monitor.o\
-+								hal/phydm/phydm_math_lib.o\
-+								hal/phydm/phydm_api.o\
-+								hal/phydm/halrf/halrf.o\
-+								hal/phydm/halrf/halrf_debug.o\
-+								hal/phydm/halrf/halphyrf_ce.o\
-+								hal/phydm/halrf/halrf_powertracking_ce.o\
-+								hal/phydm/halrf/halrf_powertracking.o\
-+								hal/phydm/halrf/halrf_kfree.o
-+
-+ifeq ($(CONFIG_RTL8188E), y)
-+RTL871X = rtl8188e
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\
-+								hal/phydm/$(RTL871X)/hal8188erateadaptive.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8188e.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8192E), y)
-+RTL871X = rtl8192e
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8192e.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8812A), y)
-+RTL871X = rtl8812a
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8812a.o\
-+								hal/phydm/txbf/haltxbfjaguar.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8821A), y)
-+RTL871X = rtl8821a
-+_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\
-+								hal/phydm/rtl8821a/halhwimg8821a_bb.o\
-+								hal/phydm/rtl8821a/halhwimg8821a_rf.o\
-+								hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\
-+								hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\
-+								hal/phydm/rtl8821a/phydm_regconfig8821a.o\
-+								hal/phydm/rtl8821a/phydm_rtl8821a.o\
-+								hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\
-+								hal/phydm/txbf/haltxbfjaguar.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8723B), y)
-+RTL871X = rtl8723b
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\
-+								hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8723b.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8814A), y)
-+RTL871X = rtl8814a
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8814a.o\
-+								hal/phydm/txbf/haltxbf8814a.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8723C), y)
-+RTL871X = rtl8703b
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8703b.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8703b.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8723D), y)
-+RTL871X = rtl8723d
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8723d.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8723d.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8710B), y)
-+RTL871X = rtl8710b
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8710b_rf.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8710b.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8710b.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8188F), y)
-+RTL871X = rtl8188f
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \
-+								hal/phydm/$(RTL871X)/phydm_rtl8188f.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8822B), y)
-+RTL871X = rtl8822b
-+_PHYDM_FILES +=	hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \
-+								hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \
-+								hal/phydm/$(RTL871X)/halhwimg8822b_rf.o \
-+								hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \
-+								hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \
-+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \
-+								hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \
-+								hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \
-+								hal/phydm/$(RTL871X)/phydm_rtl8822b.o
-+
-+_PHYDM_FILES +=	hal/phydm/txbf/haltxbf8822b.o
-+endif
-+
-+
-+ifeq ($(CONFIG_RTL8821C), y)
-+RTL871X = rtl8821c
-+_PHYDM_FILES +=	hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
-+								hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \
-+								hal/phydm/$(RTL871X)/halhwimg8821c_rf.o \
-+								hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \
-+								hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
-+endif
-+ifeq ($(CONFIG_RTL8192F), y)
-+RTL871X = rtl8192f
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8192f_rf.o\
-+								hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\
-+								hal/phydm/$(RTL871X)/phydm_rtl8192f.o\
-+								hal/phydm/halrf/$(RTL871X)/halrf_8192f.o
-+endif
-+
-+ifeq ($(CONFIG_RTL8198F), y)
-+RTL871X = rtl8198f
-+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\
-+								hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\
-+								hal/phydm/$(RTL871X)/halhwimg8198f_rf.o\
-+								hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\
-+								hal/phydm/$(RTL871X)/phydm_regconfig8198f.o
-+endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/txbf/halcomtxbf.c b/drivers/staging/rtl8723cs/hal/phydm/txbf/halcomtxbf.c
-new file mode 100644
-index 000000000000..ae45a5b1a61a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/txbf/halcomtxbf.c
-@@ -0,0 +1,520 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*@************************************************************
-+ * Description:
-+ *
-+ * This file is for TXBF mechanism
-+ *
-+ ************************************************************/
-+#include "mp_precomp.h"
-+#include "../phydm_precomp.h"
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+/*@Beamforming halcomtxbf API create by YuChen 2015/05*/
-+
-+void hal_com_txbf_beamform_init(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	boolean is_iqgen_setting_ok = false;
-+
-+	if (dm->support_ic_type & ODM_RTL8814A) {
-+		is_iqgen_setting_ok = phydm_beamforming_set_iqgen_8814A(dm);
-+		PHYDM_DBG(dm, DBG_TXBF, "[%s] is_iqgen_setting_ok = %d\n",
-+			  __func__, is_iqgen_setting_ok);
-+	}
-+}
-+
-+/*Only used for MU BFer Entry when get GID management frame (self as MU STA)*/
-+void hal_com_txbf_config_gtab(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->support_ic_type & ODM_RTL8822B)
-+		hal_txbf_8822b_config_gtab(dm);
-+}
-+
-+void phydm_beamform_set_sounding_enter(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+
-+	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_enter_work_item))
-+		odm_schedule_work_item(&p_txbf_info->txbf_enter_work_item);
-+#else
-+	hal_com_txbf_enter_work_item_callback(dm);
-+#endif
-+}
-+
-+void phydm_beamform_set_sounding_leave(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+
-+	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_leave_work_item))
-+		odm_schedule_work_item(&p_txbf_info->txbf_leave_work_item);
-+#else
-+	hal_com_txbf_leave_work_item_callback(dm);
-+#endif
-+}
-+
-+void phydm_beamform_set_sounding_rate(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+
-+	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_rate_work_item))
-+		odm_schedule_work_item(&p_txbf_info->txbf_rate_work_item);
-+#else
-+	hal_com_txbf_rate_work_item_callback(dm);
-+#endif
-+}
-+
-+void phydm_beamform_set_sounding_status(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+
-+	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_status_work_item))
-+		odm_schedule_work_item(&p_txbf_info->txbf_status_work_item);
-+#else
-+	hal_com_txbf_status_work_item_callback(dm);
-+#endif
-+}
-+
-+void phydm_beamform_set_sounding_fw_ndpa(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+
-+	if (*dm->is_fw_dw_rsvd_page_in_progress)
-+		odm_set_timer(dm, &p_txbf_info->txbf_fw_ndpa_timer, 5);
-+	else
-+		odm_schedule_work_item(&p_txbf_info->txbf_fw_ndpa_work_item);
-+#else
-+	hal_com_txbf_fw_ndpa_work_item_callback(dm);
-+#endif
-+}
-+
-+void phydm_beamform_set_sounding_clk(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+
-+	if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_clk_work_item))
-+		odm_schedule_work_item(&p_txbf_info->txbf_clk_work_item);
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	phydm_run_in_thread_cmd(dm, hal_com_txbf_clk_work_item_callback, dm);
-+#else
-+	hal_com_txbf_clk_work_item_callback(dm);
-+#endif
-+}
-+
-+void phydm_beamform_set_reset_tx_path(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+	struct _RT_WORK_ITEM *pwi = &p_txbf_info->txbf_reset_tx_path_work_item;
-+
-+	if (!odm_is_work_item_scheduled(pwi))
-+		odm_schedule_work_item(pwi);
-+#else
-+	hal_com_txbf_reset_tx_path_work_item_callback(dm);
-+#endif
-+}
-+
-+void phydm_beamform_set_get_tx_rate(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+	struct _RT_WORK_ITEM *pwi = &p_txbf_info->txbf_get_tx_rate_work_item;
-+
-+	if (!odm_is_work_item_scheduled(pwi))
-+		odm_schedule_work_item(pwi);
-+#else
-+	hal_com_txbf_get_tx_rate_work_item_callback(dm);
-+#endif
-+}
-+
-+void hal_com_txbf_enter_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+#else
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#endif
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+	u8 idx = p_txbf_info->txbf_idx;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
-+		hal_txbf_jaguar_enter(dm, idx);
-+	else if (dm->support_ic_type & ODM_RTL8192E)
-+		hal_txbf_8192e_enter(dm, idx);
-+	else if (dm->support_ic_type & ODM_RTL8814A)
-+		hal_txbf_8814a_enter(dm, idx);
-+	else if (dm->support_ic_type & ODM_RTL8822B)
-+		hal_txbf_8822b_enter(dm, idx);
-+}
-+
-+void hal_com_txbf_leave_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+#else
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#endif
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+
-+	u8 idx = p_txbf_info->txbf_idx;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
-+		hal_txbf_jaguar_leave(dm, idx);
-+	else if (dm->support_ic_type & ODM_RTL8192E)
-+		hal_txbf_8192e_leave(dm, idx);
-+	else if (dm->support_ic_type & ODM_RTL8814A)
-+		hal_txbf_8814a_leave(dm, idx);
-+	else if (dm->support_ic_type & ODM_RTL8822B)
-+		hal_txbf_8822b_leave(dm, idx);
-+}
-+
-+void hal_com_txbf_fw_ndpa_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+#else
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#endif
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+	u8 idx = p_txbf_info->ndpa_idx;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
-+		hal_txbf_jaguar_fw_txbf(dm, idx);
-+	else if (dm->support_ic_type & ODM_RTL8192E)
-+		hal_txbf_8192e_fw_tx_bf(dm, idx);
-+	else if (dm->support_ic_type & ODM_RTL8814A)
-+		hal_txbf_8814a_fw_txbf(dm, idx);
-+	else if (dm->support_ic_type & ODM_RTL8822B)
-+		hal_txbf_8822b_fw_txbf(dm, idx);
-+}
-+
-+void hal_com_txbf_clk_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+#else
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#endif
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (dm->support_ic_type & ODM_RTL8812)
-+		hal_txbf_jaguar_clk_8812a(dm);
-+}
-+
-+void hal_com_txbf_rate_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+#else
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#endif
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+	u8 BW = p_txbf_info->BW;
-+	u8 rate = p_txbf_info->rate;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (dm->support_ic_type & ODM_RTL8812)
-+		hal_txbf_8812a_set_ndpa_rate(dm, BW, rate);
-+	else if (dm->support_ic_type & ODM_RTL8192E)
-+		hal_txbf_8192e_set_ndpa_rate(dm, BW, rate);
-+	else if (dm->support_ic_type & ODM_RTL8814A)
-+		hal_txbf_8814a_set_ndpa_rate(dm, BW, rate);
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void hal_com_txbf_fw_ndpa_timer_callback(
-+	struct phydm_timer_list *timer)
-+{
-+	void *adapter = (void *)timer->Adapter;
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (*dm->is_fw_dw_rsvd_page_in_progress)
-+		odm_set_timer(dm, &(p_txbf_info->txbf_fw_ndpa_timer), 5);
-+	else
-+		odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item));
-+}
-+#endif
-+
-+void hal_com_txbf_status_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+#else
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#endif
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+
-+	u8 idx = p_txbf_info->txbf_idx;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))
-+		hal_txbf_jaguar_status(dm, idx);
-+	else if (dm->support_ic_type & ODM_RTL8192E)
-+		hal_txbf_8192e_status(dm, idx);
-+	else if (dm->support_ic_type & ODM_RTL8814A)
-+		hal_txbf_8814a_status(dm, idx);
-+	else if (dm->support_ic_type & ODM_RTL8822B)
-+		hal_txbf_8822b_status(dm, idx);
-+}
-+
-+void hal_com_txbf_reset_tx_path_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+#else
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#endif
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+
-+	u8 idx = p_txbf_info->txbf_idx;
-+
-+	if (dm->support_ic_type & ODM_RTL8814A)
-+		hal_txbf_8814a_reset_tx_path(dm, idx);
-+}
-+
-+void hal_com_txbf_get_tx_rate_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	)
-+{
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+#else
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#endif
-+
-+	if (dm->support_ic_type & ODM_RTL8814A)
-+		hal_txbf_8814a_get_tx_rate(dm);
-+}
-+
-+boolean
-+hal_com_txbf_set(
-+	void *dm_void,
-+	u8 set_type,
-+	void *p_in_buf)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 *p_u1_tmp = (u8 *)p_in_buf;
-+	struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] set_type = 0x%X\n", __func__, set_type);
-+
-+	switch (set_type) {
-+	case TXBF_SET_SOUNDING_ENTER:
-+		p_txbf_info->txbf_idx = *p_u1_tmp;
-+		phydm_beamform_set_sounding_enter(dm);
-+		break;
-+
-+	case TXBF_SET_SOUNDING_LEAVE:
-+		p_txbf_info->txbf_idx = *p_u1_tmp;
-+		phydm_beamform_set_sounding_leave(dm);
-+		break;
-+
-+	case TXBF_SET_SOUNDING_RATE:
-+		p_txbf_info->BW = p_u1_tmp[0];
-+		p_txbf_info->rate = p_u1_tmp[1];
-+		phydm_beamform_set_sounding_rate(dm);
-+		break;
-+
-+	case TXBF_SET_SOUNDING_STATUS:
-+		p_txbf_info->txbf_idx = *p_u1_tmp;
-+		phydm_beamform_set_sounding_status(dm);
-+		break;
-+
-+	case TXBF_SET_SOUNDING_FW_NDPA:
-+		p_txbf_info->ndpa_idx = *p_u1_tmp;
-+		phydm_beamform_set_sounding_fw_ndpa(dm);
-+		break;
-+
-+	case TXBF_SET_SOUNDING_CLK:
-+		phydm_beamform_set_sounding_clk(dm);
-+		break;
-+
-+	case TXBF_SET_TX_PATH_RESET:
-+		p_txbf_info->txbf_idx = *p_u1_tmp;
-+		phydm_beamform_set_reset_tx_path(dm);
-+		break;
-+
-+	case TXBF_SET_GET_TX_RATE:
-+		phydm_beamform_set_get_tx_rate(dm);
-+		break;
-+	}
-+
-+	return true;
-+}
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+boolean
-+hal_com_txbf_get(
-+	void *adapter,
-+	u8 get_type,
-+	void *p_out_buf)
-+{
-+	PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+	boolean *p_boolean = (boolean *)p_out_buf;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (get_type == TXBF_GET_EXPLICIT_BEAMFORMEE) {
-+		if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter))
-+			*p_boolean = false;
-+		else if (/*@IS_HARDWARE_TYPE_8822B(adapter)	||*/
-+			 IS_HARDWARE_TYPE_8821B(adapter) ||
-+			 IS_HARDWARE_TYPE_8192E(adapter) ||
-+			 IS_HARDWARE_TYPE_8192F(adapter) ||
-+			 IS_HARDWARE_TYPE_JAGUAR(adapter) ||
-+			 IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter) ||
-+			 IS_HARDWARE_TYPE_JAGUAR3(adapter))
-+			*p_boolean = true;
-+		else
-+			*p_boolean = false;
-+	} else if (get_type == TXBF_GET_EXPLICIT_BEAMFORMER) {
-+		if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter))
-+			*p_boolean = false;
-+		else if (/*@IS_HARDWARE_TYPE_8822B(adapter)	||*/
-+			 IS_HARDWARE_TYPE_8821B(adapter) ||
-+			 IS_HARDWARE_TYPE_8192E(adapter) ||
-+			 IS_HARDWARE_TYPE_8192F(adapter) ||
-+			 IS_HARDWARE_TYPE_JAGUAR(adapter) ||
-+			 IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter) ||
-+			 IS_HARDWARE_TYPE_JAGUAR3(adapter)) {
-+			if (hal_data->RF_Type == RF_2T2R ||
-+			    hal_data->RF_Type == RF_3T3R ||
-+			    hal_data->RF_Type == RF_4T4R)
-+				*p_boolean = true;
-+			else
-+				*p_boolean = false;
-+		} else
-+			*p_boolean = false;
-+	} else if (get_type == TXBF_GET_MU_MIMO_STA) {
-+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) ||\
-+	(RTL8822C_SUPPORT == 1))
-+		if (IS_HARDWARE_TYPE_8822B(adapter) ||
-+		    IS_HARDWARE_TYPE_8821C(adapter) ||
-+		    IS_HARDWARE_TYPE_JAGUAR3(adapter))
-+			*p_boolean = true;
-+		else
-+#endif
-+			*p_boolean = false;
-+
-+	} else if (get_type == TXBF_GET_MU_MIMO_AP) {
-+#if ((RTL8822B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1))
-+		if (IS_HARDWARE_TYPE_8822B(adapter) ||
-+		    IS_HARDWARE_TYPE_JAGUAR3(adapter))
-+			*p_boolean = true;
-+		else
-+#endif
-+			*p_boolean = false;
-+	}
-+
-+	return true;
-+}
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/txbf/halcomtxbf.h b/drivers/staging/rtl8723cs/hal/phydm/txbf/halcomtxbf.h
-new file mode 100644
-index 000000000000..5ad303394cba
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/txbf/halcomtxbf.h
-@@ -0,0 +1,183 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_COM_TXBF_H__
-+#define __HAL_COM_TXBF_H__
-+
-+#if 0
-+typedef	bool
-+(*TXBF_GET)(
-+	void*			adapter,
-+	u8			get_type,
-+	void*			p_out_buf
-+	);
-+
-+typedef	bool
-+(*TXBF_SET)(
-+	void*			adapter,
-+	u8			set_type,
-+	void*			p_in_buf
-+	);
-+#endif
-+
-+enum txbf_set_type {
-+	TXBF_SET_SOUNDING_ENTER,
-+	TXBF_SET_SOUNDING_LEAVE,
-+	TXBF_SET_SOUNDING_RATE,
-+	TXBF_SET_SOUNDING_STATUS,
-+	TXBF_SET_SOUNDING_FW_NDPA,
-+	TXBF_SET_SOUNDING_CLK,
-+	TXBF_SET_TX_PATH_RESET,
-+	TXBF_SET_GET_TX_RATE
-+};
-+
-+enum txbf_get_type {
-+	TXBF_GET_EXPLICIT_BEAMFORMEE,
-+	TXBF_GET_EXPLICIT_BEAMFORMER,
-+	TXBF_GET_MU_MIMO_STA,
-+	TXBF_GET_MU_MIMO_AP
-+};
-+
-+/* @2 HAL TXBF related */
-+struct _HAL_TXBF_INFO {
-+	u8 txbf_idx;
-+	u8 ndpa_idx;
-+	u8 BW;
-+	u8 rate;
-+
-+	struct phydm_timer_list txbf_fw_ndpa_timer;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	RT_WORK_ITEM txbf_enter_work_item;
-+	RT_WORK_ITEM txbf_leave_work_item;
-+	RT_WORK_ITEM txbf_fw_ndpa_work_item;
-+	RT_WORK_ITEM txbf_clk_work_item;
-+	RT_WORK_ITEM txbf_status_work_item;
-+	RT_WORK_ITEM txbf_rate_work_item;
-+	RT_WORK_ITEM txbf_reset_tx_path_work_item;
-+	RT_WORK_ITEM txbf_get_tx_rate_work_item;
-+#endif
-+};
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+
-+void hal_com_txbf_beamform_init(
-+	void *dm_void);
-+
-+void hal_com_txbf_config_gtab(
-+	void *dm_void);
-+
-+void hal_com_txbf_enter_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	);
-+
-+void hal_com_txbf_leave_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	);
-+
-+void hal_com_txbf_fw_ndpa_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	);
-+
-+void hal_com_txbf_clk_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	);
-+
-+void hal_com_txbf_reset_tx_path_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	);
-+
-+void hal_com_txbf_get_tx_rate_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	);
-+
-+void hal_com_txbf_rate_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	);
-+
-+void hal_com_txbf_fw_ndpa_timer_callback(
-+	struct phydm_timer_list *timer);
-+
-+void hal_com_txbf_status_work_item_callback(
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	void *adapter
-+#else
-+	void *dm_void
-+#endif
-+	);
-+
-+boolean
-+hal_com_txbf_set(
-+	void *dm_void,
-+	u8 set_type,
-+	void *p_in_buf);
-+
-+boolean
-+hal_com_txbf_get(
-+	void *adapter,
-+	u8 get_type,
-+	void *p_out_buf);
-+
-+#else
-+#define hal_com_txbf_beamform_init(dm_void) NULL
-+#define hal_com_txbf_config_gtab(dm_void) NULL
-+#define hal_com_txbf_enter_work_item_callback(_adapter) NULL
-+#define hal_com_txbf_leave_work_item_callback(_adapter) NULL
-+#define hal_com_txbf_fw_ndpa_work_item_callback(_adapter) NULL
-+#define hal_com_txbf_clk_work_item_callback(_adapter) NULL
-+#define hal_com_txbf_rate_work_item_callback(_adapter) NULL
-+#define hal_com_txbf_fw_ndpa_timer_callback(_adapter) NULL
-+#define hal_com_txbf_status_work_item_callback(_adapter) NULL
-+#define hal_com_txbf_get(_adapter, _get_type, _pout_buf)
-+
-+#endif
-+
-+#endif /*  @#ifndef __HAL_COM_TXBF_H__ */
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8192e.c b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8192e.c
-new file mode 100644
-index 000000000000..daac3e58aa3b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8192e.c
-@@ -0,0 +1,384 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*************************************************************
-+ * Description:
-+ *
-+ * This file is for 8192E TXBF mechanism
-+ *
-+ ************************************************************/
-+#include "mp_precomp.h"
-+#include "../phydm_precomp.h"
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+#if (RTL8192E_SUPPORT == 1)
-+
-+void hal_txbf_8192e_set_ndpa_rate(
-+	void *dm_void,
-+	u8 BW,
-+	u8 rate)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW));
-+}
-+
-+void hal_txbf_8192e_rf_mode(
-+	void *dm_void,
-+	struct _RT_BEAMFORMING_INFO *beam_info)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (dm->rf_type == RF_1T1R)
-+		return;
-+
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
-+	odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
-+
-+	if (beam_info->beamformee_su_cnt > 0) {
-+		/*Path_A*/
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode  0x30=0x18000*/
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/
-+		/*Path_B*/
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/
-+	} else {
-+		/*Path_A*/
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/
-+		/*Path_B*/
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/
-+	}
-+
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
-+	odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
-+
-+	if (beam_info->beamformee_su_cnt > 0) {
-+		odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333);
-+		odm_set_bb_reg(dm, R_0xa04, MASKBYTE3, 0xc1);
-+	} else
-+		odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313);
-+}
-+
-+void hal_txbf_8192e_fw_txbf_cmd(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 idx, period0 = 0, period1 = 0;
-+	u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
-+	u8 u1_tx_bf_parm[3] = {0};
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
-+		if (beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
-+			if (idx == 0) {
-+				if (beam_info->beamformee_entry[idx].is_sound)
-+					PageNum0 = 0xFE;
-+				else
-+					PageNum0 = 0xFF; /* stop sounding */
-+				period0 = (u8)(beam_info->beamformee_entry[idx].sound_period);
-+			} else if (idx == 1) {
-+				if (beam_info->beamformee_entry[idx].is_sound)
-+					PageNum1 = 0xFE;
-+				else
-+					PageNum1 = 0xFF; /* stop sounding */
-+				period1 = (u8)(beam_info->beamformee_entry[idx].sound_period);
-+			}
-+		}
-+	}
-+
-+	u1_tx_bf_parm[0] = PageNum0;
-+	u1_tx_bf_parm[1] = PageNum1;
-+	u1_tx_bf_parm[2] = (period1 << 4) | period0;
-+	odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
-+
-+	PHYDM_DBG(dm, DBG_TXBF,
-+		  "[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n",
-+		  __func__, PageNum0, period0, PageNum1, period1);
-+}
-+
-+void hal_txbf_8192e_download_ndpa(
-+	void *dm_void,
-+	u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 u1b_tmp = 0, tmp_reg422 = 0, head_page;
-+	u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
-+	boolean is_send_beacon = false;
-+	u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;
-+	/*@default reseved 1 page for the IC type which is undefined.*/
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	*dm->is_fw_dw_rsvd_page_in_progress = true;
-+#endif
-+	if (idx == 0)
-+		head_page = 0xFE;
-+	else
-+		head_page = 0xFE;
-+
-+	phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);
-+
-+	/*Set REG_CR bit 8. DMA beacon by SW.*/
-+	u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1);
-+	odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp | BIT(0)));
-+
-+	/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
-+	tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2);
-+	odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422 & (~BIT(6)));
-+
-+	if (tmp_reg422 & BIT(6)) {
-+		PHYDM_DBG(dm, DBG_TXBF,
-+			  "%s There is an adapter is sending beacon.\n",
-+			  __func__);
-+		is_send_beacon = true;
-+	}
-+
-+	/*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD	NDPA Head for TXDMA*/
-+	odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, head_page);
-+
-+	do {
-+		/*@Clear beacon valid check bit.*/
-+		bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
-+		odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 2, (bcn_valid_reg | BIT(0)));
-+
-+		/* @download NDPA rsvd page. */
-+		beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
-+
-+#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
-+		if (dm->support_interface == ODM_ITRF_PCIE) {
-+			u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3);
-+			count = 0;
-+			while ((count < 20) && (u1b_tmp & BIT(4))) {
-+				count++;
-+				ODM_delay_us(10);
-+				u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3);
-+			}
-+			odm_write_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3, u1b_tmp | BIT(4));
-+		}
-+#endif
-+
-+		/*@check rsvd page download OK.*/
-+		bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
-+		count = 0;
-+		while (!(bcn_valid_reg & BIT(0)) && count < 20) {
-+			count++;
-+			ODM_delay_us(10);
-+			bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
-+		}
-+		dl_bcn_count++;
-+	} while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);
-+
-+	if (!(bcn_valid_reg & BIT(0)))
-+		PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
-+			  __func__);
-+
-+	/*TDECTRL[15:8] 0x209[7:0] = 0xF9	Beacon Head for TXDMA*/
-+	odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, tx_page_bndy);
-+
-+	/*To make sure that if there exists an adapter which would like to send beacon.*/
-+	/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
-+	/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
-+	/*the beacon cannot be sent by HW.*/
-+	/*@2010.06.23. Added by tynli.*/
-+	if (is_send_beacon)
-+		odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422);
-+
-+	/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
-+	/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
-+	u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1);
-+	odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp & (~BIT(0))));
-+
-+	p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	*dm->is_fw_dw_rsvd_page_in_progress = false;
-+#endif
-+}
-+
-+void hal_txbf_8192e_enter(
-+	void *dm_void,
-+	u8 bfer_bfee_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i = 0;
-+	u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
-+	u8 bfee_idx = (bfer_bfee_idx & 0xF);
-+	u32 csi_param;
-+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
-+	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
-+	u16 sta_id = 0;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	hal_txbf_8192e_rf_mode(dm, beamforming_info);
-+
-+	if (dm->rf_type == RF_2T2R)
-+		odm_write_4byte(dm, 0xd80, 0x00000000); /*nc =2*/
-+
-+	if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
-+		beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
-+
-+		/*Sounding protocol control*/
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xCB);
-+
-+		/*@MAC address/Partial AID of Beamformer*/
-+		if (bfer_idx == 0) {
-+			for (i = 0; i < 6; i++)
-+				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8192E + i), beamformer_entry.mac_addr[i]);
-+		} else {
-+			for (i = 0; i < 6; i++)
-+				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8192E + i), beamformer_entry.mac_addr[i]);
-+		}
-+
-+		/*@CSI report parameters of Beamformer Default use nc = 2*/
-+		csi_param = 0x03090309;
-+
-+		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param);
-+		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8192E, csi_param);
-+		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param);
-+
-+		/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us,  MP chip)*/
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E + 3, 0x50);
-+	}
-+
-+	if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
-+		beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
-+
-+		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
-+			sta_id = beamformee_entry.mac_id;
-+		else
-+			sta_id = beamformee_entry.p_aid;
-+
-+		PHYDM_DBG(dm, DBG_TXBF, "[%s], sta_id=0x%X\n", __func__,
-+			  sta_id);
-+
-+		/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
-+		if (bfee_idx == 0) {
-+			odm_write_2byte(dm, REG_TXBF_CTRL_8192E, sta_id);
-+			odm_write_1byte(dm, REG_TXBF_CTRL_8192E + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 3) | BIT(4) | BIT(6) | BIT(7));
-+		} else
-+			odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, sta_id | BIT(12) | BIT(14) | BIT(15));
-+
-+		/*@CSI report parameters of Beamformee*/
-+		if (bfee_idx == 0) {
-+			/*@Get BIT24 & BIT25*/
-+			u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3) & 0x3;
-+
-+			odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3, tmp | 0x60);
-+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9));
-+		} else {
-+			/*Set BIT25*/
-+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, sta_id | 0xE200);
-+		}
-+		phydm_beamforming_notify(dm);
-+	}
-+}
-+
-+void hal_txbf_8192e_leave(
-+	void *dm_void,
-+	u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	hal_txbf_8192e_rf_mode(dm, beam_info);
-+
-+	/*	@Clear P_AID of Beamformee
-+	*	Clear MAC addresss of Beamformer
-+	*	Clear Associated Bfmee Sel
-+	*/
-+	if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE)
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xC8);
-+
-+	if (idx == 0) {
-+		odm_write_2byte(dm, REG_TXBF_CTRL_8192E, 0);
-+		odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0);
-+		odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E + 4, 0);
-+		odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0);
-+	} else {
-+		odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 2) & 0xF000);
-+		odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0);
-+		odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E + 4, 0);
-+		odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2) & 0x60);
-+	}
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] idx %d\n", __func__, idx);
-+}
-+
-+void hal_txbf_8192e_status(
-+	void *dm_void,
-+	u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u16 beam_ctrl_val;
-+	u32 beam_ctrl_reg;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];
-+
-+	if (phydm_acting_determine(dm, phydm_acting_as_ibss))
-+		beam_ctrl_val = beamform_entry.mac_id;
-+	else
-+		beam_ctrl_val = beamform_entry.p_aid;
-+
-+	if (idx == 0)
-+		beam_ctrl_reg = REG_TXBF_CTRL_8192E;
-+	else {
-+		beam_ctrl_reg = REG_TXBF_CTRL_8192E + 2;
-+		beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
-+	}
-+
-+	if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) {
-+		if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
-+			beam_ctrl_val |= BIT(9);
-+		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
-+			beam_ctrl_val |= BIT(10);
-+	} else
-+		beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
-+
-+	odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
-+
-+	PHYDM_DBG(dm, DBG_TXBF,
-+		  "[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__,
-+		  idx, beam_ctrl_reg, beam_ctrl_val);
-+}
-+
-+void hal_txbf_8192e_fw_tx_bf(
-+	void *dm_void,
-+	u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
-+		hal_txbf_8192e_download_ndpa(dm, idx);
-+
-+	hal_txbf_8192e_fw_txbf_cmd(dm);
-+}
-+
-+#endif /* @#if (RTL8192E_SUPPORT == 1)*/
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8192e.h b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8192e.h
-new file mode 100644
-index 000000000000..9b0c8321f991
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8192e.h
-@@ -0,0 +1,71 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_TXBF_8192E_H__
-+#define __HAL_TXBF_8192E_H__
-+
-+#if (RTL8192E_SUPPORT == 1)
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+
-+void hal_txbf_8192e_set_ndpa_rate(
-+	void *dm_void,
-+	u8 BW,
-+	u8 rate);
-+
-+void hal_txbf_8192e_enter(
-+	void *dm_void,
-+	u8 idx);
-+
-+void hal_txbf_8192e_leave(
-+	void *dm_void,
-+	u8 idx);
-+
-+void hal_txbf_8192e_status(
-+	void *dm_void,
-+	u8 idx);
-+
-+void hal_txbf_8192e_fw_tx_bf(
-+	void *dm_void,
-+	u8 idx);
-+#else
-+
-+#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate)
-+#define hal_txbf_8192e_enter(dm_void, idx)
-+#define hal_txbf_8192e_leave(dm_void, idx)
-+#define hal_txbf_8192e_status(dm_void, idx)
-+#define hal_txbf_8192e_fw_tx_bf(dm_void, idx)
-+
-+#endif
-+
-+#else
-+
-+#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate)
-+#define hal_txbf_8192e_enter(dm_void, idx)
-+#define hal_txbf_8192e_leave(dm_void, idx)
-+#define hal_txbf_8192e_status(dm_void, idx)
-+#define hal_txbf_8192e_fw_tx_bf(dm_void, idx)
-+
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8814a.c b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8814a.c
-new file mode 100644
-index 000000000000..7ad6ca909b49
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8814a.c
-@@ -0,0 +1,675 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/* ************************************************************
-+ * Description:
-+ *
-+ * This file is for 8814A TXBF mechanism
-+ *
-+ * ************************************************************ */
-+
-+#include "mp_precomp.h"
-+#include "../phydm_precomp.h"
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+#if (RTL8814A_SUPPORT == 1)
-+
-+boolean
-+phydm_beamforming_set_iqgen_8814A(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i = 0;
-+	u16 counter = 0;
-+	u32 rf_mode[4];
-+
-+	for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
-+		odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
-+
-+	while (1) {
-+		counter++;
-+		for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
-+			odm_set_rf_reg(dm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/
-+
-+		ODM_delay_us(2);
-+
-+		for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
-+			rf_mode[i] = odm_get_rf_reg(dm, i, RF_RCK_OS, 0xfffff);
-+
-+		if (rf_mode[0] == 0x18000 && rf_mode[1] == 0x18000 && rf_mode[2] == 0x18000 && rf_mode[3] == 0x18000)
-+			break;
-+		else if (counter == 100) {
-+			PHYDM_DBG(dm, DBG_TXBF, "iqgen setting fail:8814A\n");
-+			return false;
-+		}
-+	}
-+
-+	for (i = RF_PATH_A; i < MAX_RF_PATH; i++) {
-+		odm_set_rf_reg(dm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/
-+		odm_set_rf_reg(dm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*@Enable TXIQGEN in Rx mode*/
-+	}
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in Rx mode*/
-+
-+	for (i = RF_PATH_A; i < MAX_RF_PATH; i++)
-+		odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
-+
-+	return true;
-+}
-+
-+void hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8814A, BW);
-+	odm_write_1byte(dm, REG_NDPA_RATE_8814A, (u8)rate);
-+}
-+#if 0
-+#define PHYDM_MEMORY_MAP_BUF_READ 0x8000
-+#define PHYDM_CTRL_INFO_PAGE 0x660
-+
-+void
-+phydm_data_rate_8814a(
-+	struct dm_struct			*dm,
-+	u8				mac_id,
-+	u32				*data,
-+	u8				data_len
-+)
-+{
-+	u8	i = 0;
-+	u16	x_read_data_addr = 0;
-+
-+	odm_write_2byte(dm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE);
-+	x_read_data_addr = PHYDM_MEMORY_MAP_BUF_READ + mac_id * 32; /*@Ctrl Info: 32Bytes for each macid(n)*/
-+
-+	if (x_read_data_addr < PHYDM_MEMORY_MAP_BUF_READ || x_read_data_addr > 0x8FFF) {
-+		PHYDM_DBG(dm, DBG_TXBF,
-+			  "x_read_data_addr(0x%x) is not correct!\n",
-+			  x_read_data_addr);
-+		return;
-+	}
-+
-+	/* Read data */
-+	for (i = 0; i < data_len; i++)
-+		*(data + i) = odm_read_2byte(dm, x_read_data_addr + i);
-+}
-+#endif
-+
-+void hal_txbf_8814a_get_tx_rate(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY *entry;
-+	struct ra_table *ra_tab = &dm->dm_ra_table;
-+	struct cmn_sta_info *sta = NULL;
-+	u8 data_rate = 0xFF;
-+	u8 macid = 0;
-+
-+	entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]);
-+	macid = (u8)entry->mac_id;
-+
-+	sta = dm->phydm_sta_info[macid];
-+
-+	if (is_sta_active(sta)) {
-+		data_rate = (sta->ra_info.curr_tx_rate) & 0x7f; /*@Bit7 indicates SGI*/
-+		beam_info->tx_bf_data_rate = data_rate;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] dm->tx_bf_data_rate = 0x%x\n", __func__,
-+		  beam_info->tx_bf_data_rate);
-+}
-+
-+void hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+#if DEV_BUS_TYPE == RT_USB_INTERFACE
-+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
-+	u8 nr_index = 0, tx_ss = 0;
-+
-+	if (idx < BEAMFORMEE_ENTRY_NUM)
-+		beamformee_entry = beamforming_info->beamformee_entry[idx];
-+	else
-+		return;
-+
-+	if (beamforming_info->last_usb_hub != (*dm->hub_usb_mode)) {
-+		nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer);
-+
-+		if (*dm->hub_usb_mode == 2) {
-+			if (dm->rf_type == RF_4T4R)
-+				tx_ss = 0xf;
-+			else if (dm->rf_type == RF_3T3R)
-+				tx_ss = 0xe;
-+			else
-+				tx_ss = 0x6;
-+		} else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/
-+			tx_ss = 0x6;
-+		else
-+			tx_ss = 0x6;
-+
-+		if (tx_ss == 0xf) {
-+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);
-+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);
-+		} else if (tx_ss == 0xe) {
-+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);
-+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);
-+		} else if (tx_ss == 0x6) {
-+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);
-+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
-+		}
-+
-+		if (idx == 0) {
-+			switch (nr_index) {
-+			case 0:
-+				break;
-+
-+			case 1: /*Nsts = 2	BC*/
-+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
-+				break;
-+
-+			case 2: /*Nsts = 3	BCD*/
-+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
-+				break;
-+
-+			default: /*nr>3, same as Case 3*/
-+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
-+				break;
-+			}
-+		} else {
-+			switch (nr_index) {
-+			case 0:
-+				break;
-+
-+			case 1: /*Nsts = 2	BC*/
-+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
-+				break;
-+
-+			case 2: /*Nsts = 3	BCD*/
-+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
-+				break;
-+
-+			default: /*nr>3, same as Case 3*/
-+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
-+				break;
-+			}
-+		}
-+
-+		beamforming_info->last_usb_hub = *dm->hub_usb_mode;
-+	} else
-+		return;
-+#endif
-+}
-+
-+u8 hal_txbf_8814a_get_ntx(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 ntx = 0, tx_ss = 3;
-+
-+#if DEV_BUS_TYPE == RT_USB_INTERFACE
-+	tx_ss = *dm->hub_usb_mode;
-+#endif
-+	if (tx_ss == 3 || tx_ss == 2) {
-+		if (dm->rf_type == RF_4T4R)
-+			ntx = 3;
-+		else if (dm->rf_type == RF_3T3R)
-+			ntx = 2;
-+		else
-+			ntx = 1;
-+	} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
-+		ntx = 1;
-+	else
-+		ntx = 1;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ntx = %d\n", __func__, ntx);
-+	return ntx;
-+}
-+
-+u8 hal_txbf_8814a_get_nrx(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 nrx = 0;
-+
-+	if (dm->rf_type == RF_4T4R)
-+		nrx = 3;
-+	else if (dm->rf_type == RF_3T3R)
-+		nrx = 2;
-+	else if (dm->rf_type == RF_2T2R)
-+		nrx = 1;
-+	else if (dm->rf_type == RF_2T3R)
-+		nrx = 2;
-+	else if (dm->rf_type == RF_2T4R)
-+		nrx = 3;
-+	else if (dm->rf_type == RF_1T1R)
-+		nrx = 0;
-+	else if (dm->rf_type == RF_1T2R)
-+		nrx = 1;
-+	else
-+		nrx = 0;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] nrx = %d\n", __func__, nrx);
-+	return nrx;
-+}
-+
-+void hal_txbf_8814a_rf_mode(void *dm_void,
-+			    struct _RT_BEAMFORMING_INFO *beamforming_info,
-+			    u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 nr_index = 0;
-+	u8 tx_ss = 3; /*@default use 3 Tx*/
-+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
-+
-+	if (idx < BEAMFORMEE_ENTRY_NUM)
-+		beamformee_entry = beamforming_info->beamformee_entry[idx];
-+	else
-+		return;
-+
-+	nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer);
-+
-+	if (dm->rf_type == RF_1T1R)
-+		return;
-+
-+	if (beamforming_info->beamformee_su_cnt > 0) {
-+#if DEV_BUS_TYPE == RT_USB_INTERFACE
-+		beamforming_info->last_usb_hub = *dm->hub_usb_mode;
-+		tx_ss = *dm->hub_usb_mode;
-+#endif
-+		if (tx_ss == 3 || tx_ss == 2) {
-+			if (dm->rf_type == RF_4T4R)
-+				tx_ss = 0xf;
-+			else if (dm->rf_type == RF_3T3R)
-+				tx_ss = 0xe;
-+			else
-+				tx_ss = 0x6;
-+		} else if (tx_ss == 1) /*USB 2.0 always 2Tx*/
-+			tx_ss = 0x6;
-+		else
-+			tx_ss = 0x6;
-+
-+		if (tx_ss == 0xf) {
-+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);
-+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);
-+		} else if (tx_ss == 0xe) {
-+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);
-+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);
-+		} else if (tx_ss == 0x6) {
-+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);
-+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
-+		}
-+
-+		/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
-+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/
-+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*@if Nsts > Nc don't apply V matrix*/
-+
-+		if (idx == 0) {
-+			switch (nr_index) {
-+			case 0:
-+				break;
-+
-+			case 1: /*Nsts = 2	BC*/
-+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
-+				break;
-+
-+			case 2: /*Nsts = 3	BCD*/
-+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
-+				break;
-+
-+			default: /*nr>3, same as Case 3*/
-+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
-+
-+				break;
-+			}
-+		} else {
-+			switch (nr_index) {
-+			case 0:
-+				break;
-+
-+			case 1: /*Nsts = 2	BC*/
-+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/
-+				break;
-+
-+			case 2: /*Nsts = 3	BCD*/
-+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/
-+				break;
-+
-+			default: /*nr>3, same as Case 3*/
-+				odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/
-+				break;
-+			}
-+		}
-+	}
-+
-+	if (beamforming_info->beamformee_su_cnt == 0 && beamforming_info->beamformer_su_cnt == 0) {
-+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/
-+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360);
-+	}
-+}
-+#if 0
-+void
-+hal_txbf_8814a_download_ndpa(
-+	void			*dm_void,
-+	u8				idx
-+)
-+{
-+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
-+	u8			u1b_tmp = 0, tmp_reg422 = 0;
-+	u8			bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
-+	u16			head_page = 0x7FE;
-+	boolean			is_send_beacon = false;
-+	u16			tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/
-+	struct _RT_BEAMFORMING_INFO	*beam_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY	*p_beam_entry = beam_info->beamformee_entry + idx;
-+	void		*adapter = dm->adapter;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	*dm->is_fw_dw_rsvd_page_in_progress = true;
-+#endif
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy);
-+
-+	/*Set REG_CR bit 8. DMA beacon by SW.*/
-+	u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1);
-+	odm_write_1byte(dm,  REG_CR_8814A + 1, (u1b_tmp | BIT(0)));
-+
-+
-+	/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
-+	tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2);
-+	odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2,  tmp_reg422 & (~BIT(6)));
-+
-+	if (tmp_reg422 & BIT(6)) {
-+		PHYDM_DBG(dm, DBG_TXBF,
-+			  "%s: There is an adapter is sending beacon.\n",
-+			  __func__);
-+		is_send_beacon = true;
-+	}
-+
-+	/*@0x204[11:0]	Beacon Head for TXDMA*/
-+	odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, head_page);
-+
-+	do {
-+		/*@Clear beacon valid check bit.*/
-+		bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1);
-+		odm_write_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7)));
-+
-+		/*@download NDPA rsvd page.*/
-+		if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
-+			beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE);
-+		else
-+			beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
-+
-+		/*@check rsvd page download OK.*/
-+		bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1);
-+		count = 0;
-+		while (!(bcn_valid_reg & BIT(7)) && count < 20) {
-+			count++;
-+			ODM_delay_ms(10);
-+			bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 2);
-+		}
-+		dl_bcn_count++;
-+	} while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5);
-+
-+	if (!(bcn_valid_reg & BIT(7)))
-+		PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
-+			  __func__);
-+
-+	/*@0x204[11:0]	Beacon Head for TXDMA*/
-+	odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy);
-+
-+	/*To make sure that if there exists an adapter which would like to send beacon.*/
-+	/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
-+	/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
-+	/*the beacon cannot be sent by HW.*/
-+	/*@2010.06.23. Added by tynli.*/
-+	if (is_send_beacon)
-+		odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422);
-+
-+	/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
-+	/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
-+	u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1);
-+	odm_write_1byte(dm, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0))));
-+
-+	p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	*dm->is_fw_dw_rsvd_page_in_progress = false;
-+#endif
-+}
-+
-+void
-+hal_txbf_8814a_fw_txbf_cmd(
-+	void			*dm_void
-+)
-+{
-+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
-+	u8	idx, period = 0;
-+	u8	PageNum0 = 0xFF, PageNum1 = 0xFF;
-+	u8	u1_tx_bf_parm[3] = {0};
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
-+		if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
-+			if (beam_info->beamformee_entry[idx].is_sound) {
-+				PageNum0 = 0xFE;
-+				PageNum1 = 0x07;
-+				period = (u8)(beam_info->beamformee_entry[idx].sound_period);
-+			} else if (PageNum0 == 0xFF) {
-+				PageNum0 = 0xFF; /*stop sounding*/
-+				PageNum1 = 0x0F;
-+			}
-+		}
-+	}
-+
-+	u1_tx_bf_parm[0] = PageNum0;
-+	u1_tx_bf_parm[1] = PageNum1;
-+	u1_tx_bf_parm[2] = period;
-+	odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
-+
-+	PHYDM_DBG(dm, DBG_TXBF,
-+		  "[%s] PageNum0 = %d, PageNum1 = %d period = %d\n", __func__,
-+		  PageNum0, PageNum1, period);
-+}
-+#endif
-+void hal_txbf_8814a_enter(void *dm_void, u8 bfer_bfee_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i = 0;
-+	u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
-+	u8 bfee_idx = (bfer_bfee_idx & 0xF);
-+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
-+	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
-+	u16 sta_id = 0, csi_param = 0;
-+	u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] bfer_idx=%d, bfee_idx=%d\n", __func__,
-+		  bfer_idx, bfee_idx);
-+	odm_set_mac_reg(dm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202);
-+
-+	if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
-+		beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
-+		/*Sounding protocol control*/
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xDB);
-+
-+		/*@MAC address/Partial AID of Beamformer*/
-+		if (bfer_idx == 0) {
-+			for (i = 0; i < 6; i++)
-+				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]);
-+		} else {
-+			for (i = 0; i < 6; i++)
-+				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]);
-+		}
-+
-+		/*@CSI report parameters of Beamformer*/
-+		nc_index = hal_txbf_8814a_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/
-+		nr_index = beamformer_entry.num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
-+
-+		grouping = 0;
-+
-+		/*@for ac = 1, for n = 3*/
-+		if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)
-+			codebookinfo = 1;
-+		else if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
-+			codebookinfo = 3;
-+
-+		coefficientsize = 3;
-+
-+		csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));
-+
-+		if (bfer_idx == 0)
-+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, csi_param);
-+		else
-+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param);
-+		/*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A + 3, 0x40);
-+	}
-+
-+	if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
-+		beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
-+
-+		hal_txbf_8814a_rf_mode(dm, beamforming_info, bfee_idx);
-+
-+		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
-+			sta_id = beamformee_entry.mac_id;
-+		else
-+			sta_id = beamformee_entry.p_aid;
-+
-+		/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
-+		if (bfee_idx == 0) {
-+			odm_write_2byte(dm, REG_TXBF_CTRL_8814A, sta_id);
-+			odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));
-+		} else
-+			odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12));
-+
-+		/*@CSI report parameters of Beamformee*/
-+		if (bfee_idx == 0) {
-+			/*@Get BIT24 & BIT25*/
-+			u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3;
-+
-+			odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60);
-+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9));
-+		} else
-+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/
-+
-+		phydm_beamforming_notify(dm);
-+	}
-+}
-+
-+void hal_txbf_8814a_leave(void *dm_void, u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
-+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
-+
-+	if (idx < BEAMFORMER_ENTRY_NUM) {
-+		beamformer_entry = beamforming_info->beamformer_entry[idx];
-+		beamformee_entry = beamforming_info->beamformee_entry[idx];
-+	} else
-+		return;
-+
-+	/*@Clear P_AID of Beamformee*/
-+	/*@Clear MAC address of Beamformer*/
-+	/*@Clear Associated Bfmee Sel*/
-+
-+	if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xD8);
-+		if (idx == 0) {
-+			odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0);
-+			odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0);
-+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, 0);
-+		} else {
-+			odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0);
-+			odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0);
-+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0);
-+		}
-+	}
-+
-+	if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
-+		hal_txbf_8814a_rf_mode(dm, beamforming_info, idx);
-+		if (idx == 0) {
-+			odm_write_2byte(dm, REG_TXBF_CTRL_8814A, 0x0);
-+			odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));
-+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0);
-+		} else {
-+			odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT(14) | BIT(15) | BIT(12));
-+
-+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60);
-+		}
-+	}
-+}
-+
-+void hal_txbf_8814a_status(void *dm_void, u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u16 beam_ctrl_val, tmp_val;
-+	u32 beam_ctrl_reg;
-+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY beamform_entry;
-+
-+	if (idx < BEAMFORMEE_ENTRY_NUM)
-+		beamform_entry = beamforming_info->beamformee_entry[idx];
-+	else
-+		return;
-+
-+	if (phydm_acting_determine(dm, phydm_acting_as_ibss))
-+		beam_ctrl_val = beamform_entry.mac_id;
-+	else
-+		beam_ctrl_val = beamform_entry.p_aid;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "@%s, beamform_entry.beamform_entry_state = %d",
-+		  __func__, beamform_entry.beamform_entry_state);
-+
-+	if (idx == 0)
-+		beam_ctrl_reg = REG_TXBF_CTRL_8814A;
-+	else {
-+		beam_ctrl_reg = REG_TXBF_CTRL_8814A + 2;
-+		beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
-+	}
-+
-+	if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beamforming_info->apply_v_matrix == true) {
-+		if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
-+			beam_ctrl_val |= BIT(9);
-+		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
-+			beam_ctrl_val |= (BIT(9) | BIT(10));
-+		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80)
-+			beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
-+	} else {
-+		PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix", __func__);
-+		beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
-+	}
-+
-+	odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
-+	/*@disable NDP packet use beamforming */
-+	tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8814A);
-+	odm_write_2byte(dm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15));
-+}
-+
-+void hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx)
-+{
-+#if 0
-+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO	*beam_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY	*p_beam_entry = beam_info->beamformee_entry + idx;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
-+		hal_txbf_8814a_download_ndpa(dm, idx);
-+
-+	hal_txbf_8814a_fw_txbf_cmd(dm);
-+#endif
-+}
-+
-+#endif /* @(RTL8814A_SUPPORT == 1)*/
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8814a.h b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8814a.h
-new file mode 100644
-index 000000000000..61b33bbfbb9b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8814a.h
-@@ -0,0 +1,77 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_TXBF_8814A_H__
-+#define __HAL_TXBF_8814A_H__
-+
-+#if (RTL8814A_SUPPORT == 1)
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+
-+boolean
-+phydm_beamforming_set_iqgen_8814A(void *dm_void);
-+
-+void hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate);
-+
-+u8 hal_txbf_8814a_get_ntx(void *dm_void);
-+
-+void hal_txbf_8814a_enter(void *dm_void, u8 idx);
-+
-+void hal_txbf_8814a_leave(void *dm_void, u8 idx);
-+
-+void hal_txbf_8814a_status(void *dm_void, u8 idx);
-+
-+void hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx);
-+
-+void hal_txbf_8814a_get_tx_rate(void *dm_void);
-+
-+void hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx);
-+
-+#else
-+
-+#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate)
-+#define hal_txbf_8814a_get_ntx(dm_void) 0
-+#define hal_txbf_8814a_enter(dm_void, idx)
-+#define hal_txbf_8814a_leave(dm_void, idx)
-+#define hal_txbf_8814a_status(dm_void, idx)
-+#define hal_txbf_8814a_reset_tx_path(dm_void, idx)
-+#define hal_txbf_8814a_get_tx_rate(dm_void)
-+#define hal_txbf_8814a_fw_txbf(dm_void, idx)
-+#define phydm_beamforming_set_iqgen_8814A(dm_void) 0
-+
-+#endif
-+
-+#else
-+
-+#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate)
-+#define hal_txbf_8814a_get_ntx(dm_void) 0
-+#define hal_txbf_8814a_enter(dm_void, idx)
-+#define hal_txbf_8814a_leave(dm_void, idx)
-+#define hal_txbf_8814a_status(dm_void, idx)
-+#define hal_txbf_8814a_reset_tx_path(dm_void, idx)
-+#define hal_txbf_8814a_get_tx_rate(dm_void)
-+#define hal_txbf_8814a_fw_txbf(dm_void, idx)
-+#define phydm_beamforming_set_iqgen_8814A(dm_void) 0
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8822b.c b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8822b.c
-new file mode 100644
-index 000000000000..a1d35c9b178d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8822b.c
-@@ -0,0 +1,1088 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*@============================================================*/
-+/* @Description:                                              */
-+/*                                                           @*/
-+/* This file is for 8814A TXBF mechanism                     */
-+/*                                                           @*/
-+/*@============================================================*/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#if (RTL8822B_SUPPORT == 1)
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+
-+u8 hal_txbf_8822b_get_ntx(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 ntx = 0;
-+
-+#if DEV_BUS_TYPE == RT_USB_INTERFACE
-+	if (dm->support_interface == ODM_ITRF_USB) {
-+		if (*dm->hub_usb_mode == 2) { /*USB3.0*/
-+			if (dm->rf_type == RF_4T4R)
-+				ntx = 3;
-+			else if (dm->rf_type == RF_3T3R)
-+				ntx = 2;
-+			else
-+				ntx = 1;
-+		} else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/
-+			ntx = 1;
-+		else
-+			ntx = 1;
-+	} else
-+#endif
-+	{
-+		if (dm->rf_type == RF_4T4R)
-+			ntx = 3;
-+		else if (dm->rf_type == RF_3T3R)
-+			ntx = 2;
-+		else
-+			ntx = 1;
-+	}
-+
-+	return ntx;
-+}
-+
-+u8 hal_txbf_8822b_get_nrx(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 nrx = 0;
-+
-+	if (dm->rf_type == RF_4T4R)
-+		nrx = 3;
-+	else if (dm->rf_type == RF_3T3R)
-+		nrx = 2;
-+	else if (dm->rf_type == RF_2T2R)
-+		nrx = 1;
-+	else if (dm->rf_type == RF_2T3R)
-+		nrx = 2;
-+	else if (dm->rf_type == RF_2T4R)
-+		nrx = 3;
-+	else if (dm->rf_type == RF_1T1R)
-+		nrx = 0;
-+	else if (dm->rf_type == RF_1T2R)
-+		nrx = 1;
-+	else
-+		nrx = 0;
-+
-+	return nrx;
-+}
-+
-+/***************SU & MU BFee Entry********************/
-+void hal_txbf_8822b_rf_mode(
-+	void *dm_void,
-+	struct _RT_BEAMFORMING_INFO *beamforming_info,
-+	u8 idx)
-+{
-+#if 0
-+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
-+	u8				i, nr_index = 0;
-+	boolean				is_self_beamformer = false;
-+	boolean				is_self_beamformee = false;
-+	struct _RT_BEAMFORMEE_ENTRY	beamformee_entry;
-+
-+	if (idx < BEAMFORMEE_ENTRY_NUM)
-+		beamformee_entry = beamforming_info->beamformee_entry[idx];
-+	else
-+		return;
-+
-+	if (dm->rf_type == RF_1T1R)
-+		return;
-+
-+	for (i = RF_PATH_A; i < RF_PATH_B; i++) {
-+		odm_set_rf_reg(dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x1);
-+		/*RF mode table write enable*/
-+	}
-+
-+	if (beamforming_info->beamformee_su_cnt > 0 || beamforming_info->beamformee_mu_cnt > 0) {
-+		for (i = RF_PATH_A; i < RF_PATH_B; i++) {
-+			odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_addr, 0xfffff, 0x18000);
-+			/*Select RX mode*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data0, 0xfffff, 0xBE77F);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data1, 0xfffff, 0x226BF);
-+			/*@Enable TXIQGEN in RX mode*/
-+		}
-+		odm_set_rf_reg(dm, RF_PATH_A, rf_mode_table_data1, 0xfffff, 0xE26BF);
-+		/*@Enable TXIQGEN in RX mode*/
-+	}
-+
-+	for (i = RF_PATH_A; i < RF_PATH_B; i++) {
-+		odm_set_rf_reg(dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x0);
-+		/*RF mode table write disable*/
-+	}
-+
-+	if (beamforming_info->beamformee_su_cnt > 0) {
-+		/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
-+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2);			/*@enable BB TxBF ant mapping register*/
-+
-+		if (idx == 0) {
-+			/*Nsts = 2	AB*/
-+			odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433);
-+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
-+			/*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430);*/
-+
-+		} else {/*@IDX =1*/
-+			odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);
-+			odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
-+			/*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430;*/
-+		}
-+	} else {
-+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*@1SS by path-A*/
-+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*@2SS by path-A,B*/
-+	}
-+
-+	if (beamforming_info->beamformee_mu_cnt > 0) {
-+		/*@MU STAs share the common setting*/
-+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1);
-+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);
-+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
-+	}
-+#endif
-+}
-+#if 0
-+void
-+hal_txbf_8822b_download_ndpa(
-+	void			*adapter,
-+	u8				idx
-+)
-+{
-+	u8			u1b_tmp = 0, tmp_reg422 = 0;
-+	u8			bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
-+	u16			head_page = 0x7FE;
-+	boolean			is_send_beacon = false;
-+	HAL_DATA_TYPE	*hal_data = GET_HAL_DATA(adapter);
-+	u16			tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/
-+	struct _RT_BEAMFORMING_INFO	*beam_info = GET_BEAMFORM_INFO(adapter);
-+	struct _RT_BEAMFORMEE_ENTRY	*p_beam_entry = beam_info->beamformee_entry + idx;
-+
-+	hal_data->is_fw_dw_rsvd_page_in_progress = true;
-+	phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy);
-+
-+	/*Set REG_CR bit 8. DMA beacon by SW.*/
-+	u1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1);
-+	platform_efio_write_1byte(adapter,  REG_CR_8814A + 1, (u1b_tmp | BIT(0)));
-+
-+
-+	/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
-+	tmp_reg422 = platform_efio_read_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2);
-+	platform_efio_write_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2,  tmp_reg422 & (~BIT(6)));
-+
-+	if (tmp_reg422 & BIT(6)) {
-+		RT_TRACE(COMP_INIT, DBG_LOUD, ("SetBeamformDownloadNDPA_8814A(): There is an adapter is sending beacon.\n"));
-+		is_send_beacon = true;
-+	}
-+
-+	/*@0x204[11:0]	Beacon Head for TXDMA*/
-+	platform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, head_page);
-+
-+	do {
-+		/*@Clear beacon valid check bit.*/
-+		bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1);
-+		platform_efio_write_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7)));
-+
-+		/*@download NDPA rsvd page.*/
-+		if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
-+			beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE);
-+		else
-+			beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
-+
-+		/*@check rsvd page download OK.*/
-+		bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1);
-+		count = 0;
-+		while (!(bcn_valid_reg & BIT(7)) && count < 20) {
-+			count++;
-+			delay_us(10);
-+			bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 2);
-+		}
-+		dl_bcn_count++;
-+	} while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5);
-+
-+	if (!(bcn_valid_reg & BIT(0)))
-+		RT_DISP(FBEAM, FBEAM_ERROR, ("%s Download RSVD page failed!\n", __func__));
-+
-+	/*@0x204[11:0]	Beacon Head for TXDMA*/
-+	platform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy);
-+
-+	/*To make sure that if there exists an adapter which would like to send beacon.*/
-+	/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
-+	/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
-+	/*the beacon cannot be sent by HW.*/
-+	/*@2010.06.23. Added by tynli.*/
-+	if (is_send_beacon)
-+		platform_efio_write_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422);
-+
-+	/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
-+	/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
-+	u1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1);
-+	platform_efio_write_1byte(adapter, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0))));
-+
-+	p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
-+
-+	hal_data->is_fw_dw_rsvd_page_in_progress = false;
-+}
-+
-+void
-+hal_txbf_8822b_fw_txbf_cmd(
-+	void	*adapter
-+)
-+{
-+	u8	idx, period = 0;
-+	u8	PageNum0 = 0xFF, PageNum1 = 0xFF;
-+	u8	u1_tx_bf_parm[3] = {0};
-+
-+	PMGNT_INFO				mgnt_info = &(adapter->MgntInfo);
-+	struct _RT_BEAMFORMING_INFO	*beam_info = GET_BEAMFORM_INFO(adapter);
-+
-+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
-+		if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
-+			if (beam_info->beamformee_entry[idx].is_sound) {
-+				PageNum0 = 0xFE;
-+				PageNum1 = 0x07;
-+				period = (u8)(beam_info->beamformee_entry[idx].sound_period);
-+			} else if (PageNum0 == 0xFF) {
-+				PageNum0 = 0xFF; /*stop sounding*/
-+				PageNum1 = 0x0F;
-+			}
-+		}
-+	}
-+
-+	u1_tx_bf_parm[0] = PageNum0;
-+	u1_tx_bf_parm[1] = PageNum1;
-+	u1_tx_bf_parm[2] = period;
-+	fill_h2c_cmd(adapter, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
-+
-+	RT_DISP(FBEAM, FBEAM_FUN, ("@%s End, PageNum0 = 0x%x, PageNum1 = 0x%x period = %d", __func__, PageNum0, PageNum1, period));
-+}
-+#endif
-+
-+#if 0
-+void
-+hal_txbf_8822b_init(
-+	void			*dm_void
-+)
-+{
-+	struct dm_struct	*dm = (struct dm_struct *)dm_void;
-+	u8		u1b_tmp;
-+	struct _RT_BEAMFORMING_INFO		*beamforming_info = &dm->beamforming_info;
-+	void				*adapter = dm->adapter;
-+
-+	odm_set_bb_reg(dm, R_0x14c0, BIT(16), 1); /*@Enable P1 aggr new packet according to P0 transfer time*/
-+	odm_set_bb_reg(dm, R_0x14c0, BIT(15) | BIT14 | BIT13 | BIT12, 10); /*@MU Retry Limit*/
-+	odm_set_bb_reg(dm, R_0x14c0, BIT(7), 0); /*@Disable Tx MU-MIMO until sounding done*/
-+	odm_set_bb_reg(dm, R_0x14c0, 0x3F, 0); /* @Clear validity of MU STAs */
-+	odm_write_1byte(dm, 0x167c, 0x70); /*@MU-MIMO Option as default value*/
-+	odm_write_2byte(dm, 0x1680, 0); /*@MU-MIMO Control as default value*/
-+
-+	/* Set MU NDPA rate & BW source */
-+	/* @0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */
-+	u1b_tmp = odm_read_1byte(dm, 0x42C);
-+	odm_write_1byte(dm, REG_TXBF_CTRL_8822B, (u1b_tmp | BIT(6)));
-+	/* @0x45F[7:0] = 0x10 (rate=OFDM_6M, BW20) */
-+	odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, 0x10);
-+
-+	/*Temp Settings*/
-+	odm_set_bb_reg(dm, R_0x6dc, 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/
-+	odm_set_bb_reg(dm, R_0x1c94, MASKDWORD, 0xAFFFAFFF); /*@Grouping bitmap parameters*/
-+
-+	/* @Init HW variable */
-+	beamforming_info->reg_mu_tx_ctrl = odm_read_4byte(dm, 0x14c0);
-+
-+	if (dm->rf_type == RF_2T2R) { /*@2T2R*/
-+		PHYDM_DBG(dm, DBG_TXBF, "%s: rf_type is 2T2R\n", __func__);
-+		config_phydm_trx_mode_8822b(dm, (enum bb_path)3,
-+					    (enum bb_path)3, BB_PATH_AB;
-+	}
-+
-+#if (OMNIPEEK_SNIFFER_ENABLED == 1)
-+	/* @Config HW to receive packet on the user position from registry for sniffer mode. */
-+	/* odm_set_bb_reg(dm, R_0xb00, BIT(9), 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */
-+	odm_set_bb_reg(dm, R_0xb54, BIT(30), 1); /* RegB54[30] = 1 (force user position) */
-+	odm_set_bb_reg(dm, R_0xb54, (BIT(29) | BIT28), adapter->MgntInfo.sniff_user_position); /* RegB54[29:28] = user position (0~3) */
-+	PHYDM_DBG(dm, DBG_TXBF,
-+		  "Set adapter->MgntInfo.sniff_user_position=%#X\n",
-+		  adapter->MgntInfo.sniff_user_position);
-+#endif
-+}
-+#endif
-+
-+void hal_txbf_8822b_enter(
-+	void *dm_void,
-+	u8 bfer_bfee_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i = 0;
-+	u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
-+	u8 bfee_idx = (bfer_bfee_idx & 0xF);
-+	u16 csi_param = 0;
-+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry;
-+	struct _RT_BEAMFORMER_ENTRY *beamformer_entry;
-+	u16 value16, sta_id = 0;
-+	u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
-+	u32 gid_valid, user_position_l, user_position_h;
-+	u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};
-+	u8 u1b_tmp;
-+	u32 u4b_tmp;
-+
-+	RT_DISP(FBEAM, FBEAM_FUN, ("%s: bfer_bfee_idx=%d, bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_bfee_idx, bfer_idx, bfee_idx));
-+
-+	/*************SU BFer Entry Init*************/
-+	if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
-+		beamformer_entry = &beamforming_info->beamformer_entry[bfer_idx];
-+		beamformer_entry->is_mu_ap = false;
-+		/*Sounding protocol control*/
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB);
-+
-+		for (i = 0; i < MAX_BEAMFORMER_SU; i++) {
-+			if ((beamforming_info->beamformer_su_reg_maping & BIT(i)) == 0) {
-+				beamforming_info->beamformer_su_reg_maping |= BIT(i);
-+				beamformer_entry->su_reg_index = i;
-+				break;
-+			}
-+		}
-+
-+		/*@MAC address/Partial AID of Beamformer*/
-+		if (beamformer_entry->su_reg_index == 0) {
-+			for (i = 0; i < 6; i++)
-+				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]);
-+		} else {
-+			for (i = 0; i < 6; i++)
-+				odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8822B + i), beamformer_entry->mac_addr[i]);
-+		}
-+
-+		/*@CSI report parameters of Beamformer*/
-+		nc_index = hal_txbf_8822b_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/
-+		nr_index = beamformer_entry->num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
-+
-+		grouping = 0;
-+
-+		/*@for ac = 1, for n = 3*/
-+		if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)
-+			codebookinfo = 1;
-+		else if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
-+			codebookinfo = 3;
-+
-+		coefficientsize = 3;
-+
-+		csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));
-+
-+		if (bfer_idx == 0)
-+			odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B, csi_param);
-+		else
-+			odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, csi_param);
-+		/*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B + 3, 0x70);
-+	}
-+
-+	/*************SU BFee Entry Init*************/
-+	if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
-+		p_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx];
-+		p_beamformee_entry->is_mu_sta = false;
-+		hal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx);
-+
-+		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
-+			sta_id = p_beamformee_entry->mac_id;
-+		else
-+			sta_id = p_beamformee_entry->p_aid;
-+
-+		for (i = 0; i < MAX_BEAMFORMEE_SU; i++) {
-+			if ((beamforming_info->beamformee_su_reg_maping & BIT(i)) == 0) {
-+				beamforming_info->beamformee_su_reg_maping |= BIT(i);
-+				p_beamformee_entry->su_reg_index = i;
-+				break;
-+			}
-+		}
-+
-+		/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
-+		if (p_beamformee_entry->su_reg_index == 0) {
-+			odm_write_2byte(dm, REG_TXBF_CTRL_8822B, sta_id);
-+			odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7));
-+		} else
-+			odm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, sta_id | BIT(14) | BIT(15) | BIT(12));
-+
-+		/*@CSI report parameters of Beamformee*/
-+		if (p_beamformee_entry->su_reg_index == 0) {
-+			/*@Get BIT24 & BIT25*/
-+			u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3) & 0x3;
-+
-+			odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60);
-+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, sta_id | BIT(9));
-+		} else
-+			odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, sta_id | 0xE200); /*Set BIT25*/
-+
-+		phydm_beamforming_notify(dm);
-+	}
-+
-+	/*************MU BFer Entry Init*************/
-+	if (beamforming_info->beamformer_mu_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
-+		beamformer_entry = &beamforming_info->beamformer_entry[bfer_idx];
-+		beamforming_info->mu_ap_index = bfer_idx;
-+		beamformer_entry->is_mu_ap = true;
-+		for (i = 0; i < 8; i++)
-+			beamformer_entry->gid_valid[i] = 0;
-+		for (i = 0; i < 16; i++)
-+			beamformer_entry->user_position[i] = 0;
-+
-+		/*Sounding protocol control*/
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB);
-+
-+		/* @MAC address */
-+		for (i = 0; i < 6; i++)
-+			odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]);
-+
-+		/* Set partial AID */
-+		odm_write_2byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + 6), beamformer_entry->p_aid);
-+
-+		/* @Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/
-+		u1b_tmp = odm_read_1byte(dm, 0x1680);
-+		u1b_tmp = (beamformer_entry->p_aid) & 0xFFF;
-+		odm_write_1byte(dm, 0x1680, u1b_tmp);
-+
-+		/* Set 80us for leaving ndp_rx_standby_state */
-+		odm_write_1byte(dm, 0x71B, 0x50);
-+
-+		/* Set 0x6A0[14] = 1 to accept action_no_ack */
-+		u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1);
-+		u1b_tmp |= 0x40;
-+		odm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp);
-+		/* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */
-+		u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP1_8822B);
-+		u1b_tmp |= 0x30;
-+		odm_write_1byte(dm, REG_RXFLTMAP1_8822B, u1b_tmp);
-+
-+		/*@CSI report parameters of Beamformer*/
-+		nc_index = hal_txbf_8822b_get_nrx(dm); /* @Depend on RF type */
-+		nr_index = 1; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
-+		grouping = 0; /*no grouping*/
-+		codebookinfo = 1; /*@7 bit for psi, 9 bit for phi*/
-+		coefficientsize = 0; /*This is nothing really matter*/
-+		csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));
-+		odm_write_2byte(dm, 0x6F4, csi_param);
-+
-+		/*@for B-cut*/
-+		odm_set_bb_reg(dm, R_0x6a0, BIT(20), 0);
-+		odm_set_bb_reg(dm, R_0x688, BIT(20), 0);
-+	}
-+
-+	/*************MU BFee Entry Init*************/
-+	if (beamforming_info->beamformee_mu_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
-+		p_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx];
-+		p_beamformee_entry->is_mu_sta = true;
-+		for (i = 0; i < MAX_BEAMFORMEE_MU; i++) {
-+			if ((beamforming_info->beamformee_mu_reg_maping & BIT(i)) == 0) {
-+				beamforming_info->beamformee_mu_reg_maping |= BIT(i);
-+				p_beamformee_entry->mu_reg_index = i;
-+				break;
-+			}
-+		}
-+
-+		if (p_beamformee_entry->mu_reg_index == 0xFF) {
-+			/* There is no valid bit in beamformee_mu_reg_maping */
-+			RT_DISP(FBEAM, FBEAM_FUN, ("%s: ERROR! There is no valid bit in beamformee_mu_reg_maping!\n", __func__));
-+			return;
-+		}
-+
-+		/*User position table*/
-+		switch (p_beamformee_entry->mu_reg_index) {
-+		case 0:
-+			gid_valid = 0x7fe;
-+			user_position_l = 0x111110;
-+			user_position_h = 0x0;
-+			break;
-+		case 1:
-+			gid_valid = 0x7f806;
-+			user_position_l = 0x11000004;
-+			user_position_h = 0x11;
-+			break;
-+		case 2:
-+			gid_valid = 0x1f81818;
-+			user_position_l = 0x400040;
-+			user_position_h = 0x11100;
-+			break;
-+		case 3:
-+			gid_valid = 0x1e186060;
-+			user_position_l = 0x4000400;
-+			user_position_h = 0x1100040;
-+			break;
-+		case 4:
-+			gid_valid = 0x66618180;
-+			user_position_l = 0x40004000;
-+			user_position_h = 0x10040400;
-+			break;
-+		case 5:
-+			gid_valid = 0x79860600;
-+			user_position_l = 0x40000;
-+			user_position_h = 0x4404004;
-+			break;
-+		}
-+
-+		for (i = 0; i < 8; i++) {
-+			if (i < 4) {
-+				p_beamformee_entry->gid_valid[i] = (u8)(gid_valid & 0xFF);
-+				gid_valid = (gid_valid >> 8);
-+			} else
-+				p_beamformee_entry->gid_valid[i] = 0;
-+		}
-+		for (i = 0; i < 16; i++) {
-+			if (i < 4)
-+				p_beamformee_entry->user_position[i] = (u8)((user_position_l >> (i * 8)) & 0xFF);
-+			else if (i < 8)
-+				p_beamformee_entry->user_position[i] = (u8)((user_position_h >> ((i - 4) * 8)) & 0xFF);
-+			else
-+				p_beamformee_entry->user_position[i] = 0;
-+		}
-+
-+		/*Sounding protocol control*/
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB);
-+
-+		/*select MU STA table*/
-+		beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
-+		beamforming_info->reg_mu_tx_ctrl |= (p_beamformee_entry->mu_reg_index << 8) & (BIT(8) | BIT(9) | BIT(10));
-+		odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
-+
-+		odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, 0); /*Reset gid_valid table*/
-+		odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);
-+		odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);
-+
-+		/*set validity of MU STAs*/
-+		beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;
-+		beamforming_info->reg_mu_tx_ctrl |= beamforming_info->beamformee_mu_reg_maping & 0x3F;
-+		odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
-+
-+		PHYDM_DBG(dm, DBG_TXBF,
-+			  "@%s, reg_mu_tx_ctrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
-+			  __func__, beamforming_info->reg_mu_tx_ctrl,
-+			  user_position_l, user_position_h);
-+
-+		value16 = odm_read_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index]);
-+		value16 &= 0xFE00; /*@Clear PAID*/
-+		value16 |= BIT(9); /*@Enable MU BFee*/
-+		value16 |= p_beamformee_entry->p_aid;
-+		odm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], value16);
-+
-+		/* @0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */
-+		u1b_tmp = odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3);
-+		u1b_tmp |= 0xD0; /* Set bit 28, 30, 31 to 3b'111*/
-+		odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, u1b_tmp);
-+		/* Set NDPA to 6M*/
-+		odm_write_1byte(dm, REG_NDPA_RATE_8822B, 0x4);
-+
-+		u1b_tmp = odm_read_1byte(dm, REG_NDPA_OPT_CTRL_8822B);
-+		u1b_tmp &= 0xFC; /* @Clear bit 0, 1*/
-+		odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, u1b_tmp);
-+
-+		u4b_tmp = odm_read_4byte(dm, REG_SND_PTCL_CTRL_8822B);
-+		u4b_tmp = ((u4b_tmp & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202*/
-+		odm_write_4byte(dm, REG_SND_PTCL_CTRL_8822B, u4b_tmp);
-+
-+		/* Set 0x6A0[14] = 1 to accept action_no_ack */
-+		u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1);
-+		u1b_tmp |= 0x40;
-+		odm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp);
-+		/* @End of MAC registers setting */
-+
-+		hal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx);
-+#if (SUPPORT_MU_BF == 1)
-+		/*Special for plugfest*/
-+		delay_ms(50); /* wait for 4-way handshake ending*/
-+		send_sw_vht_gid_mgnt_frame(dm, p_beamformee_entry->mac_addr, bfee_idx);
-+#endif
-+
-+		phydm_beamforming_notify(dm);
-+#if 1
-+		{
-+			u32 ctrl_info_offset, index;
-+			/*Set Ctrl Info*/
-+			odm_write_2byte(dm, 0x140, 0x660);
-+			ctrl_info_offset = 0x8000 + 32 * p_beamformee_entry->mac_id;
-+			/*Reset Ctrl Info*/
-+			for (index = 0; index < 8; index++)
-+				odm_write_4byte(dm, ctrl_info_offset + index * 4, 0);
-+
-+			odm_write_4byte(dm, ctrl_info_offset, (p_beamformee_entry->mu_reg_index + 1) << 16);
-+			odm_write_1byte(dm, 0x81, 0x80); /*RPTBUF ready*/
-+
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "@%s, mac_id = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\n",
-+				  __func__, p_beamformee_entry->mac_id,
-+				  ctrl_info_offset,
-+				  p_beamformee_entry->mu_reg_index);
-+		}
-+#endif
-+	}
-+}
-+
-+void hal_txbf_8822b_leave(
-+	void *dm_void,
-+	u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMER_ENTRY *beamformer_entry;
-+	struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry;
-+	u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};
-+
-+	if (idx < BEAMFORMER_ENTRY_NUM) {
-+		beamformer_entry = &beamforming_info->beamformer_entry[idx];
-+		p_beamformee_entry = &beamforming_info->beamformee_entry[idx];
-+	} else
-+		return;
-+
-+	/*@Clear P_AID of Beamformee*/
-+	/*@Clear MAC address of Beamformer*/
-+	/*@Clear Associated Bfmee Sel*/
-+
-+	if (beamformer_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) {
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xD8);
-+		if (beamformer_entry->is_mu_ap == 0) { /*SU BFer */
-+			if (beamformer_entry->su_reg_index == 0) {
-+				odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0);
-+				odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8822B + 4, 0);
-+				odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0);
-+			} else {
-+				odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0);
-+				odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8822B + 4, 0);
-+				odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, 0);
-+			}
-+			beamforming_info->beamformer_su_reg_maping &= ~(BIT(beamformer_entry->su_reg_index));
-+			beamformer_entry->su_reg_index = 0xFF;
-+		} else { /*@MU BFer */
-+			/*set validity of MU STA0 and MU STA1*/
-+			beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;
-+			odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
-+
-+			odm_memory_set(dm, beamformer_entry->gid_valid, 0, 8);
-+			odm_memory_set(dm, beamformer_entry->user_position, 0, 16);
-+			beamformer_entry->is_mu_ap = false;
-+		}
-+	}
-+
-+	if (p_beamformee_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) {
-+		hal_txbf_8822b_rf_mode(dm, beamforming_info, idx);
-+		if (p_beamformee_entry->is_mu_sta == 0) { /*SU BFee*/
-+			if (p_beamformee_entry->su_reg_index == 0) {
-+				odm_write_2byte(dm, REG_TXBF_CTRL_8822B, 0x0);
-+				odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7));
-+				odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0);
-+			} else {
-+				odm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, 0x0 | BIT(14) | BIT(15) | BIT(12));
-+
-+				odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2,
-+						odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2) & 0x60);
-+			}
-+			beamforming_info->beamformee_su_reg_maping &= ~(BIT(p_beamformee_entry->su_reg_index));
-+			p_beamformee_entry->su_reg_index = 0xFF;
-+		} else { /*@MU BFee */
-+			/*@Disable sending NDPA & BF-rpt-poll to this BFee*/
-+			odm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], 0);
-+			/*set validity of MU STA*/
-+			beamforming_info->reg_mu_tx_ctrl &= ~(BIT(p_beamformee_entry->mu_reg_index));
-+			odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
-+
-+			p_beamformee_entry->is_mu_sta = false;
-+			beamforming_info->beamformee_mu_reg_maping &= ~(BIT(p_beamformee_entry->mu_reg_index));
-+			p_beamformee_entry->mu_reg_index = 0xFF;
-+		}
-+	}
-+}
-+
-+/***********SU & MU BFee Entry Only when souding done****************/
-+void hal_txbf_8822b_status(
-+	void *dm_void,
-+	u8 beamform_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u16 beam_ctrl_val, tmp_val;
-+	u32 beam_ctrl_reg;
-+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry;
-+	boolean is_mu_sounding = beamforming_info->is_mu_sounding, is_bitmap_ready = false;
-+	u16 bitmap;
-+	u8 idx, gid, i;
-+	u8 id1, id0;
-+	u32 gid_valid[6] = {0};
-+	u32 value32;
-+	boolean is_sounding_success[6] = {false};
-+
-+	if (beamform_idx < BEAMFORMEE_ENTRY_NUM)
-+		beamform_entry = &beamforming_info->beamformee_entry[beamform_idx];
-+	else
-+		return;
-+
-+	/*SU sounding done */
-+	if (is_mu_sounding == false) {
-+		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
-+			beam_ctrl_val = beamform_entry->mac_id;
-+		else
-+			beam_ctrl_val = beamform_entry->p_aid;
-+
-+		PHYDM_DBG(dm, DBG_TXBF,
-+			  "@%s, beamform_entry.beamform_entry_state = %d",
-+			  __func__, beamform_entry->beamform_entry_state);
-+
-+		if (beamform_entry->su_reg_index == 0)
-+			beam_ctrl_reg = REG_TXBF_CTRL_8822B;
-+		else {
-+			beam_ctrl_reg = REG_TXBF_CTRL_8822B + 2;
-+			beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
-+		}
-+
-+		if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
-+			if (beamform_entry->sound_bw == CHANNEL_WIDTH_20)
-+				beam_ctrl_val |= BIT(9);
-+			else if (beamform_entry->sound_bw == CHANNEL_WIDTH_40)
-+				beam_ctrl_val |= (BIT(9) | BIT(10));
-+			else if (beamform_entry->sound_bw == CHANNEL_WIDTH_80)
-+				beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
-+		} else {
-+			PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix",
-+				  __func__);
-+			beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
-+		}
-+
-+		odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
-+		/*@disable NDP packet use beamforming */
-+		tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8822B);
-+		odm_write_2byte(dm, REG_TXBF_CTRL_8822B, tmp_val | BIT(15));
-+	} else {
-+		PHYDM_DBG(dm, DBG_TXBF, "@%s, MU Sounding Done\n", __func__);
-+		/*@MU sounding done */
-+		if (1) { /* @(beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { */
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\n",
-+				  __func__);
-+
-+			value32 = odm_get_bb_reg(dm, R_0x1684, MASKDWORD);
-+			is_sounding_success[0] = (value32 & BIT(10)) ? 1 : 0;
-+			is_sounding_success[1] = (value32 & BIT(26)) ? 1 : 0;
-+			value32 = odm_get_bb_reg(dm, R_0x1688, MASKDWORD);
-+			is_sounding_success[2] = (value32 & BIT(10)) ? 1 : 0;
-+			is_sounding_success[3] = (value32 & BIT(26)) ? 1 : 0;
-+			value32 = odm_get_bb_reg(dm, R_0x168c, MASKDWORD);
-+			is_sounding_success[4] = (value32 & BIT(10)) ? 1 : 0;
-+			is_sounding_success[5] = (value32 & BIT(26)) ? 1 : 0;
-+
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "@%s, is_sounding_success STA1:%d,  STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n",
-+				  __func__, is_sounding_success[0],
-+				  is_sounding_success[1],
-+				  is_sounding_success[2],
-+				  is_sounding_success[3],
-+				  is_sounding_success[4],
-+				  is_sounding_success[5]);
-+
-+			value32 = odm_get_bb_reg(dm, R_0xf4c, 0xFFFF0000);
-+			/* odm_set_bb_reg(dm, R_0x19e0, MASKHWORD, 0xFFFF);Let MAC ignore bitmap */
-+
-+			is_bitmap_ready = (boolean)((value32 & BIT(15)) >> 15);
-+			bitmap = (u16)(value32 & 0x3FFF);
-+
-+			for (idx = 0; idx < 15; idx++) {
-+				if (idx < 5) { /*@bit0~4*/
-+					id0 = 0;
-+					id1 = (u8)(idx + 1);
-+				} else if (idx < 9) { /*@bit5~8*/
-+					id0 = 1;
-+					id1 = (u8)(idx - 3);
-+				} else if (idx < 12) { /*@bit9~11*/
-+					id0 = 2;
-+					id1 = (u8)(idx - 6);
-+				} else if (idx < 14) { /*@bit12~13*/
-+					id0 = 3;
-+					id1 = (u8)(idx - 8);
-+				} else { /*@bit14*/
-+					id0 = 4;
-+					id1 = (u8)(idx - 9);
-+				}
-+				if (bitmap & BIT(idx)) {
-+					/*Pair 1*/
-+					gid = (idx << 1) + 1;
-+					gid_valid[id0] |= (BIT(gid));
-+					gid_valid[id1] |= (BIT(gid));
-+					/*Pair 2*/
-+					gid += 1;
-+					gid_valid[id0] |= (BIT(gid));
-+					gid_valid[id1] |= (BIT(gid));
-+				} else {
-+					/*Pair 1*/
-+					gid = (idx << 1) + 1;
-+					gid_valid[id0] &= ~(BIT(gid));
-+					gid_valid[id1] &= ~(BIT(gid));
-+					/*Pair 2*/
-+					gid += 1;
-+					gid_valid[id0] &= ~(BIT(gid));
-+					gid_valid[id1] &= ~(BIT(gid));
-+				}
-+			}
-+
-+			for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) {
-+				beamform_entry = &beamforming_info->beamformee_entry[i];
-+				if (beamform_entry->is_mu_sta && beamform_entry->mu_reg_index < 6) {
-+					value32 = gid_valid[beamform_entry->mu_reg_index];
-+					for (idx = 0; idx < 4; idx++) {
-+						beamform_entry->gid_valid[idx] = (u8)(value32 & 0xFF);
-+						value32 = (value32 >> 8);
-+					}
-+				}
-+			}
-+
-+			for (idx = 0; idx < 6; idx++) {
-+				beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
-+				beamforming_info->reg_mu_tx_ctrl |= ((idx << 8) & (BIT(8) | BIT(9) | BIT(10)));
-+				odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
-+				odm_set_mac_reg(dm, R_0x14c4, MASKDWORD, gid_valid[idx]); /*set MU STA gid valid table*/
-+			}
-+
-+			/*@Enable TxMU PPDU*/
-+			if (beamforming_info->dbg_disable_mu_tx == false)
-+				beamforming_info->reg_mu_tx_ctrl |= BIT(7);
-+			else
-+				beamforming_info->reg_mu_tx_ctrl &= ~BIT(7);
-+			odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
-+		}
-+	}
-+}
-+
-+/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/
-+void hal_txbf_8822b_config_gtab(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL;
-+	u32 gid_valid = 0, user_position_l = 0, user_position_h = 0, i;
-+
-+	if (beamforming_info->mu_ap_index < BEAMFORMER_ENTRY_NUM)
-+		beamformer_entry = &beamforming_info->beamformer_entry[beamforming_info->mu_ap_index];
-+	else
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "%s==>\n", __func__);
-+
-+	/*@For GID 0~31*/
-+	for (i = 0; i < 4; i++)
-+		gid_valid |= (beamformer_entry->gid_valid[i] << (i << 3));
-+	for (i = 0; i < 8; i++) {
-+		if (i < 4)
-+			user_position_l |= (beamformer_entry->user_position[i] << (i << 3));
-+		else
-+			user_position_h |= (beamformer_entry->user_position[i] << ((i - 4) << 3));
-+	}
-+	/*select MU STA0 table*/
-+	beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
-+	odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
-+	odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, gid_valid);
-+	odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);
-+	odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);
-+
-+	PHYDM_DBG(dm, DBG_TXBF,
-+		  "%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
-+		  __func__, gid_valid, user_position_l, user_position_h);
-+
-+	gid_valid = 0;
-+	user_position_l = 0;
-+	user_position_h = 0;
-+
-+	/*@For GID 32~64*/
-+	for (i = 4; i < 8; i++)
-+		gid_valid |= (beamformer_entry->gid_valid[i] << ((i - 4) << 3));
-+	for (i = 8; i < 16; i++) {
-+		if (i < 4)
-+			user_position_l |= (beamformer_entry->user_position[i] << ((i - 8) << 3));
-+		else
-+			user_position_h |= (beamformer_entry->user_position[i] << ((i - 12) << 3));
-+	}
-+	/*select MU STA1 table*/
-+	beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10));
-+	beamforming_info->reg_mu_tx_ctrl |= BIT(8);
-+	odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
-+	odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, gid_valid);
-+	odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l);
-+	odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h);
-+
-+	PHYDM_DBG(dm, DBG_TXBF,
-+		  "%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n",
-+		  __func__, gid_valid, user_position_l, user_position_h);
-+
-+	/* Set validity of MU STA0 and MU STA1*/
-+	beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0;
-+	beamforming_info->reg_mu_tx_ctrl |= 0x3; /* STA0, STA1*/
-+	odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl);
-+}
-+
-+#if 0
-+/*This function translate the bitmap to GTAB*/
-+void
-+haltxbf8822b_gtab_translation(
-+	struct dm_struct			*dm
-+)
-+{
-+	u8 idx, gid;
-+	u8 id1, id0;
-+	u32 gid_valid[6] = {0};
-+	u32 user_position_lsb[6] = {0};
-+	u32 user_position_msb[6] = {0};
-+
-+	for (idx = 0; idx < 15; idx++) {
-+		if (idx < 5) {/*@bit0~4*/
-+			id0 = 0;
-+			id1 = (u8)(idx + 1);
-+		} else if (idx < 9) { /*@bit5~8*/
-+			id0 = 1;
-+			id1 = (u8)(idx - 3);
-+		} else if (idx < 12) { /*@bit9~11*/
-+			id0 = 2;
-+			id1 = (u8)(idx - 6);
-+		} else if (idx < 14) { /*@bit12~13*/
-+			id0 = 3;
-+			id1 = (u8)(idx - 8);
-+		} else { /*@bit14*/
-+			id0 = 4;
-+			id1 = (u8)(idx - 9);
-+		}
-+
-+		/*Pair 1*/
-+		gid = (idx << 1) + 1;
-+		gid_valid[id0] |= (1 << gid);
-+		gid_valid[id1] |= (1 << gid);
-+		if (gid < 16) {
-+			/*user_position_lsb[id0] |= (0 << (gid << 1));*/
-+			user_position_lsb[id1] |= (1 << (gid << 1));
-+		} else {
-+			/*user_position_msb[id0] |= (0 << ((gid - 16) << 1));*/
-+			user_position_msb[id1] |= (1 << ((gid - 16) << 1));
-+		}
-+
-+		/*Pair 2*/
-+		gid += 1;
-+		gid_valid[id0] |= (1 << gid);
-+		gid_valid[id1] |= (1 << gid);
-+		if (gid < 16) {
-+			user_position_lsb[id0] |= (1 << (gid << 1));
-+			/*user_position_lsb[id1] |= (0 << (gid << 1));*/
-+		} else {
-+			user_position_msb[id0] |= (1 << ((gid - 16) << 1));
-+			/*user_position_msb[id1] |= (0 << ((gid - 16) << 1));*/
-+		}
-+	}
-+
-+
-+	for (idx = 0; idx < 6; idx++) {
-+		/*@dbg_print("gid_valid[%d] = 0x%x\n", idx, gid_valid[idx]);
-+		dbg_print("user_position[%d] = 0x%x   %x\n", idx, user_position_msb[idx], user_position_lsb[idx]);*/
-+	}
-+}
-+#endif
-+
-+void hal_txbf_8822b_fw_txbf(
-+	void *dm_void,
-+	u8 idx)
-+{
-+#if 0
-+	struct _RT_BEAMFORMING_INFO	*beam_info = GET_BEAMFORM_INFO(adapter);
-+	struct _RT_BEAMFORMEE_ENTRY	*p_beam_entry = beam_info->beamformee_entry + idx;
-+
-+	if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
-+		hal_txbf_8822b_download_ndpa(adapter, idx);
-+
-+	hal_txbf_8822b_fw_txbf_cmd(adapter);
-+#endif
-+}
-+
-+#endif
-+
-+#if (defined(CONFIG_BB_TXBF_API))
-+/*this function is only used for BFer*/
-+void phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i;
-+
-+	if (dm->rf_type == RF_1T1R)
-+		return;
-+
-+	if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
-+		for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), 0x1); /*RF mode table write enable*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3); /*Select RX mode*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff, 0x00036); /*Set Table data*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff, 0x5AFCE); /*Set Table data*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), 0x0); /*RF mode table write disable*/
-+		}
-+	}
-+
-+	odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(30), 1); /*@if Nsts > Nc, don't apply V matrix*/
-+
-+	if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
-+		/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
-+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/
-+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); /*@ignore user since 8822B only 2Tx*/
-+
-+		/*Nsts = 2	AB*/
-+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);
-+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
-+
-+	} else {
-+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x0); /*@enable BB TxBF ant mapping register*/
-+		odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 0); /*@ignore user since 8822B only 2Tx*/
-+
-+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*@1SS by path-A*/
-+		odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*@2SS by path-A,B*/
-+	}
-+}
-+
-+/*this function is for BFer bug workaround*/
-+void phydm_8822b_sutxbfer_workaroud(void *dm_void, boolean enable_su_bfer,
-+				    u8 nc, u8 nr, u8 ng, u8 CB, u8 BW,
-+				    boolean is_vht)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (enable_su_bfer) {
-+		odm_set_bb_reg(dm, R_0x19f8, BIT(22) | BIT(21) | BIT(20), 0x1);
-+		odm_set_bb_reg(dm, R_0x19f8, BIT(25) | BIT(24) | BIT(23), 0x0);
-+		odm_set_bb_reg(dm, R_0x19f8, BIT(16), 0x1);
-+
-+		if (is_vht)
-+			odm_set_bb_reg(dm, R_0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x1f);
-+		else
-+			odm_set_bb_reg(dm, R_0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x22);
-+
-+		odm_set_bb_reg(dm, R_0x19f0, BIT(7) | BIT(6), nc);
-+		odm_set_bb_reg(dm, R_0x19f0, BIT(9) | BIT(8), nr);
-+		odm_set_bb_reg(dm, R_0x19f0, BIT(11) | BIT(10), ng);
-+		odm_set_bb_reg(dm, R_0x19f0, BIT(13) | BIT(12), CB);
-+
-+		odm_set_bb_reg(dm, R_0xb58, BIT(3) | BIT(2), BW);
-+		odm_set_bb_reg(dm, R_0xb58, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x0);
-+		odm_set_bb_reg(dm, R_0xb58, BIT(9) | BIT(8), BW);
-+		odm_set_bb_reg(dm, R_0xb58, BIT(13) | BIT(12) | BIT(11) | BIT(10), 0x0);
-+	} else {
-+		odm_set_bb_reg(dm, R_0x19f8, BIT(16), 0x0);
-+	}
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] enable_su_bfer = %d, is_vht = %d\n",
-+		  __func__, enable_su_bfer, is_vht);
-+	PHYDM_DBG(dm, DBG_TXBF,
-+		  "[%s] nc = %d, nr = %d, ng = %d, CB = %d, BW = %d\n",
-+		  __func__, nc, nr, ng, CB, BW);
-+}
-+#endif
-+#endif /* @(RTL8822B_SUPPORT == 1)*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8822b.h b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8822b.h
-new file mode 100644
-index 000000000000..552fba2a7a27
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbf8822b.h
-@@ -0,0 +1,78 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_TXBF_8822B_H__
-+#define __HAL_TXBF_8822B_H__
-+
-+#if (RTL8822B_SUPPORT == 1)
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+
-+void hal_txbf_8822b_enter(
-+	void *dm_void,
-+	u8 idx);
-+
-+void hal_txbf_8822b_leave(
-+	void *dm_void,
-+	u8 idx);
-+
-+void hal_txbf_8822b_status(
-+	void *dm_void,
-+	u8 beamform_idx);
-+
-+void hal_txbf_8822b_config_gtab(
-+	void *dm_void);
-+
-+void hal_txbf_8822b_fw_txbf(
-+	void *dm_void,
-+	u8 idx);
-+#else
-+#define hal_txbf_8822b_enter(dm_void, idx)
-+#define hal_txbf_8822b_leave(dm_void, idx)
-+#define hal_txbf_8822b_status(dm_void, idx)
-+#define hal_txbf_8822b_fw_txbf(dm_void, idx)
-+#define hal_txbf_8822b_config_gtab(dm_void)
-+
-+#endif
-+
-+#if (defined(CONFIG_BB_TXBF_API))
-+void phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);
-+
-+void phydm_8822b_sutxbfer_workaroud(void *dm_void, boolean enable_su_bfer,
-+				    u8 nc, u8 nr, u8 ng, u8 CB, u8 BW,
-+				    boolean is_vht);
-+
-+#else
-+#define phydm_8822btxbf_rfmode(dm_void, su_bfee_cnt, mu_bfee_cnt)
-+#define phydm_8822b_sutxbfer_workaroud(dm_void, enable_su_bfer, nc, nr, ng, CB, BW, is_vht)
-+#endif
-+
-+#else
-+#define hal_txbf_8822b_enter(dm_void, idx)
-+#define hal_txbf_8822b_leave(dm_void, idx)
-+#define hal_txbf_8822b_status(dm_void, idx)
-+#define hal_txbf_8822b_fw_txbf(dm_void, idx)
-+#define hal_txbf_8822b_config_gtab(dm_void)
-+
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbfinterface.c b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbfinterface.c
-new file mode 100644
-index 000000000000..c125fecadc6a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbfinterface.c
-@@ -0,0 +1,1484 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*************************************************************
-+ * Description:
-+ *
-+ * This file is for TXBF interface mechanism
-+ *
-+ ************************************************************/
-+#include "mp_precomp.h"
-+#include "../phydm_precomp.h"
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+void beamforming_gid_paid(
-+	void *adapter,
-+	PRT_TCB tcb)
-+{
-+	u8 RA[6] = {0};
-+	u8 *p_header = GET_FRAME_OF_FIRST_FRAG(adapter, tcb);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+
-+	if (((PADAPTER)adapter)->HardwareType < HARDWARE_TYPE_RTL8192EE)
-+		return;
-+	else if (IS_WIRELESS_MODE_N((PADAPTER)adapter) == false)
-+		return;
-+
-+#if (SUPPORT_MU_BF == 1)
-+	if (tcb->tx_bf_pkt_type == RT_BF_PKT_TYPE_BROADCAST_NDPA) { /* @MU NDPA */
-+#else
-+	if (0) {
-+#endif
-+		/* @Fill G_ID and P_AID */
-+		tcb->G_ID = 63;
-+		if (beam_info->first_mu_bfee_index < BEAMFORMEE_ENTRY_NUM) {
-+			tcb->P_AID = beam_info->beamformee_entry[beam_info->first_mu_bfee_index].p_aid;
-+			RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, tcb->G_ID, tcb->P_AID));
-+		}
-+	} else {
-+		GET_80211_HDR_ADDRESS1(p_header, &RA);
-+
-+		/* VHT SU PPDU carrying one or more group addressed MPDUs or */
-+		/* Transmitting a VHT NDP intended for multiple recipients */
-+		if (MacAddr_isBcst(RA) || MacAddr_isMulticast(RA) || tcb->macId == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) {
-+			tcb->G_ID = 63;
-+			tcb->P_AID = 0;
-+		} else if (ACTING_AS_AP(adapter)) {
-+			u16 AID = (u16)(MacIdGetOwnerAssociatedClientAID(adapter, tcb->macId) & 0x1ff); /*@AID[0:8]*/
-+
-+			/*RT_DISP(FBEAM, FBEAM_FUN, ("@%s  tcb->mac_id=0x%X, AID=0x%X\n", __func__, tcb->mac_id, AID));*/
-+			tcb->G_ID = 63;
-+
-+			if (AID == 0) /*@A PPDU sent by an AP to a non associated STA*/
-+				tcb->P_AID = 0;
-+			else { /*Sent by an AP and addressed to a STA associated with that AP*/
-+				u16 BSSID = 0;
-+				GET_80211_HDR_ADDRESS2(p_header, &RA);
-+				BSSID = ((RA[5] & 0xf0) >> 4) ^ (RA[5] & 0xf); /*@BSSID[44:47] xor BSSID[40:43]*/
-+				tcb->P_AID = (AID + BSSID * 32) & 0x1ff; /*@(dec(A) + dec(B)*32) mod 512*/
-+			}
-+		} else if (ACTING_AS_IBSS(((PADAPTER)adapter))) {
-+			tcb->G_ID = 63;
-+			/*P_AID for infrasturcture mode; MACID for ad-hoc mode. */
-+			tcb->P_AID = tcb->macId;
-+		} else if (MgntLinkStatusQuery(adapter)) { /*@Addressed to AP*/
-+			tcb->G_ID = 0;
-+			GET_80211_HDR_ADDRESS1(p_header, &RA);
-+			tcb->P_AID = RA[5]; /*RA[39:47]*/
-+			tcb->P_AID = (tcb->P_AID << 1) | (RA[4] >> 7);
-+		} else {
-+			tcb->G_ID = 63;
-+			tcb->P_AID = 0;
-+		}
-+		/*RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, tcb->G_ID, tcb->P_AID));*/
-+	}
-+}
-+
-+enum rt_status
-+beamforming_get_report_frame(
-+	void *adapter,
-+	PRT_RFD rfd,
-+	POCTET_STRING p_pdu_os)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
-+	u8 *p_mimo_ctrl_field, p_csi_matrix;
-+	u8 idx, nc, nr, CH_W;
-+	u16 csi_matrix_len = 0;
-+
-+	ACT_PKT_TYPE pkt_type = ACT_PKT_TYPE_UNKNOWN;
-+
-+	/* @Memory comparison to see if CSI report is the same with previous one */
-+	beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, Frame_Addr2(*p_pdu_os), &idx);
-+
-+	if (beamform_entry == NULL) {
-+		PHYDM_DBG(dm, DBG_TXBF, "%s: Cannot find entry by addr\n",
-+			  __func__);
-+		return RT_STATUS_FAILURE;
-+	}
-+
-+	pkt_type = PacketGetActionFrameType(p_pdu_os);
-+
-+	/* @-@ Modified by David */
-+	if (pkt_type == ACT_PKT_VHT_COMPRESSED_BEAMFORMING) {
-+		p_mimo_ctrl_field = p_pdu_os->Octet + 26;
-+		nc = ((*p_mimo_ctrl_field) & 0x7) + 1;
-+		nr = (((*p_mimo_ctrl_field) & 0x38) >> 3) + 1;
-+		CH_W = (((*p_mimo_ctrl_field) & 0xC0) >> 6);
-+		/*p_csi_matrix = p_mimo_ctrl_field + 3 + nc;*/ /* 24+(1+1+3)+2  MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */
-+		csi_matrix_len = p_pdu_os->Length - 26 - 3 - nc;
-+	} else if (pkt_type == ACT_PKT_HT_COMPRESSED_BEAMFORMING) {
-+		p_mimo_ctrl_field = p_pdu_os->Octet + 26;
-+		nc = ((*p_mimo_ctrl_field) & 0x3) + 1;
-+		nr = (((*p_mimo_ctrl_field) & 0xC) >> 2) + 1;
-+		CH_W = (((*p_mimo_ctrl_field) & 0x10) >> 4);
-+		/*p_csi_matrix = p_mimo_ctrl_field + 6 + nr;*/ /* 24+(1+1+6)+2  MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */
-+		csi_matrix_len = p_pdu_os->Length - 26 - 6 - nr;
-+	} else
-+		return RT_STATUS_SUCCESS;
-+
-+	PHYDM_DBG(dm, DBG_TXBF,
-+		  "[%s] idx=%d, pkt type=%d, nc=%d, nr=%d, CH_W=%d\n", __func__,
-+		  idx, pkt_type, nc, nr, CH_W);
-+
-+	return RT_STATUS_SUCCESS;
-+}
-+
-+void construct_ht_ndpa_packet(
-+	// 2017/11 MH PHYDM compile. But why need to use windows maco?
-+	// For all linux code, it should be useless?
-+	//void				*adapter = dm->adapter;
-+	ADAPTER * adapter,
-+	//void		*adapter,
-+	u8 *RA,
-+	u8 *buffer,
-+	u32 *p_length,
-+	enum channel_width BW)
-+{
-+	u16 duration = 0;
-+	PMGNT_INFO mgnt_info = &(((PADAPTER)adapter)->MgntInfo);
-+	//PMGNT_INFO				mgnt_info = &((MGNT_INFO)(((PADAPTER)adapter)->MgntInfo));
-+	OCTET_STRING p_ndpa_frame, action_content;
-+	u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};
-+
-+	PlatformZeroMemory(buffer, 32);
-+
-+	SET_80211_HDR_FRAME_CONTROL(buffer, 0);
-+
-+	SET_80211_HDR_ORDER(buffer, 1);
-+	SET_80211_HDR_TYPE_AND_SUBTYPE(buffer, Type_Action_No_Ack);
-+
-+	SET_80211_HDR_ADDRESS1(buffer, RA);
-+	SET_80211_HDR_ADDRESS2(buffer, ((PADAPTER)adapter)->CurrentAddress);
-+	SET_80211_HDR_ADDRESS3(buffer, ((PMGNT_INFO)mgnt_info)->Bssid);
-+
-+	duration = 2 * a_SifsTime + 40;
-+
-+	if (BW == CHANNEL_WIDTH_40)
-+		duration += 87;
-+	else
-+		duration += 180;
-+
-+	SET_80211_HDR_DURATION(buffer, duration);
-+
-+	/* @HT control field */
-+	SET_HT_CTRL_CSI_STEERING(buffer + sMacHdrLng, 3);
-+	SET_HT_CTRL_NDP_ANNOUNCEMENT(buffer + sMacHdrLng, 1);
-+
-+	FillOctetString(p_ndpa_frame, buffer, sMacHdrLng + sHTCLng);
-+
-+	FillOctetString(action_content, action_hdr, 4);
-+	PacketAppendData(&p_ndpa_frame, action_content);
-+
-+	*p_length = 32;
-+}
-+
-+boolean
-+send_fw_ht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	enum channel_width BW)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	void *adapter = dm->adapter;
-+	PRT_TCB tcb;
-+	PRT_TX_LOCAL_BUFFER p_buf;
-+	boolean ret = true;
-+	u32 buf_len;
-+	u8 *buf_addr;
-+	u8 desc_len = 0, idx = 0, ndp_tx_rate;
-+	void *p_def_adapter = GetDefaultAdapter(((PADAPTER)adapter));
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (beamform_entry == NULL)
-+		return false;
-+
-+	ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
-+		  ndp_tx_rate);
-+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (MgntGetFWBuffer(p_def_adapter, &tcb, &p_buf)) {
-+#if (DEV_BUS_TYPE != RT_PCI_INTERFACE)
-+		desc_len = ((PADAPTER)adapter)->HWDescHeadLength - hal_data->USBALLDummyLength;
-+#endif
-+		buf_addr = p_buf->Buffer.VirtualAddress + desc_len;
-+
-+		construct_ht_ndpa_packet(
-+			adapter,
-+			RA,
-+			buf_addr,
-+			&buf_len,
-+			BW);
-+
-+		tcb->PacketLength = buf_len + desc_len;
-+
-+		tcb->bTxEnableSwCalcDur = true;
-+
-+		tcb->BWOfPacket = BW;
-+
-+		if (ACTING_AS_IBSS(((PADAPTER)adapter)) || ACTING_AS_AP(((PADAPTER)adapter)))
-+			tcb->G_ID = 63;
-+
-+		tcb->P_AID = beamform_entry->p_aid;
-+		tcb->DataRate = ndp_tx_rate; /*rate of NDP decide by nr*/
-+
-+		((PADAPTER)adapter)->HalFunc.CmdSendPacketHandler(((PADAPTER)adapter), tcb, p_buf, tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false);
-+	} else
-+		ret = false;
-+
-+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (ret)
-+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
-+
-+	return ret;
-+}
-+
-+boolean
-+send_sw_ht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	enum channel_width BW)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	void *adapter = dm->adapter;
-+	PRT_TCB tcb;
-+	PRT_TX_LOCAL_BUFFER p_buf;
-+	boolean ret = true;
-+	u8 idx = 0, ndp_tx_rate = 0;
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
-+		  ndp_tx_rate);
-+
-+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
-+		construct_ht_ndpa_packet(
-+			adapter,
-+			RA,
-+			p_buf->Buffer.VirtualAddress,
-+			&tcb->PacketLength,
-+			BW);
-+
-+		tcb->bTxEnableSwCalcDur = true;
-+
-+		tcb->BWOfPacket = BW;
-+
-+		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);
-+	} else
-+		ret = false;
-+
-+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (ret)
-+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
-+
-+	return ret;
-+}
-+
-+void construct_vht_ndpa_packet(
-+	struct dm_struct *dm,
-+	u8 *RA,
-+	u16 AID,
-+	u8 *buffer,
-+	u32 *p_length,
-+	enum channel_width BW)
-+{
-+	u16 duration = 0;
-+	u8 sequence = 0;
-+	u8 *p_ndpa_frame = buffer;
-+	struct _RT_NDPA_STA_INFO sta_info;
-+	// 2017/11 MH PHYDM compile. But why need to use windows maco?
-+	// For all linux code, it should be useless?
-+	//void				*adapter = dm->adapter;
-+	ADAPTER * adapter = (PADAPTER)(dm->adapter);
-+	u8 idx = 0;
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
-+	/* @Frame control. */
-+	SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0);
-+	SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA);
-+
-+	SET_80211_HDR_ADDRESS1(p_ndpa_frame, RA);
-+	SET_80211_HDR_ADDRESS2(p_ndpa_frame, beamform_entry->my_mac_addr);
-+
-+	// 2017/11 MH PHYDM compile. But why need to use windows maco?
-+	// For all linux code, it should be useless?
-+	duration = 2 * a_SifsTime + 44;
-+
-+	if (BW == CHANNEL_WIDTH_80)
-+		duration += 40;
-+	else if (BW == CHANNEL_WIDTH_40)
-+		duration += 87;
-+	else
-+		duration += 180;
-+
-+	SET_80211_HDR_DURATION(p_ndpa_frame, duration);
-+
-+	sequence = *(dm->sounding_seq) << 2;
-+	odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1);
-+
-+	if (phydm_acting_determine(dm, phydm_acting_as_ibss) || phydm_acting_determine(dm, phydm_acting_as_ap) == false)
-+		AID = 0;
-+
-+	sta_info.aid = AID;
-+	sta_info.feedback_type = 0;
-+	sta_info.nc_index = 0;
-+
-+	odm_move_memory(dm, p_ndpa_frame + 17, (u8 *)&sta_info, 2);
-+
-+	*p_length = 19;
-+}
-+
-+boolean
-+send_fw_vht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	u16 AID,
-+	enum channel_width BW)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	void *adapter = dm->adapter;
-+	PRT_TCB tcb;
-+	PRT_TX_LOCAL_BUFFER p_buf;
-+	boolean ret = true;
-+	u32 buf_len;
-+	u8 *buf_addr;
-+	u8 desc_len = 0, idx = 0, ndp_tx_rate = 0;
-+	void *p_def_adapter = GetDefaultAdapter(((PADAPTER)adapter));
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (beamform_entry == NULL)
-+		return false;
-+
-+	ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
-+		  ndp_tx_rate);
-+
-+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (MgntGetFWBuffer(p_def_adapter, &tcb, &p_buf)) {
-+#if (DEV_BUS_TYPE != RT_PCI_INTERFACE)
-+		desc_len = ((PADAPTER)adapter)->HWDescHeadLength - hal_data->USBALLDummyLength;
-+#endif
-+		buf_addr = p_buf->Buffer.VirtualAddress + desc_len;
-+
-+		construct_vht_ndpa_packet(
-+			dm,
-+			RA,
-+			AID,
-+			buf_addr,
-+			&buf_len,
-+			BW);
-+
-+		tcb->PacketLength = buf_len + desc_len;
-+
-+		tcb->bTxEnableSwCalcDur = true;
-+
-+		tcb->BWOfPacket = BW;
-+
-+		if (phydm_acting_determine(dm, phydm_acting_as_ibss) || phydm_acting_determine(dm, phydm_acting_as_ap))
-+			tcb->G_ID = 63;
-+
-+		tcb->P_AID = beamform_entry->p_aid;
-+		tcb->DataRate = ndp_tx_rate; /*@decide by nr*/
-+
-+		((PADAPTER)adapter)->HalFunc.CmdSendPacketHandler(adapter, tcb, p_buf, tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false);
-+	} else
-+		ret = false;
-+
-+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] End, ret=%d\n", __func__, ret);
-+
-+	if (ret)
-+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
-+
-+	return ret;
-+}
-+
-+boolean
-+send_sw_vht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	u16 AID,
-+	enum channel_width BW)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	void *adapter = dm->adapter;
-+	PRT_TCB tcb;
-+	PRT_TX_LOCAL_BUFFER p_buf;
-+	boolean ret = true;
-+	u8 idx = 0, ndp_tx_rate = 0;
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
-+
-+	ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
-+		  ndp_tx_rate);
-+
-+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
-+		construct_vht_ndpa_packet(
-+			dm,
-+			RA,
-+			AID,
-+			p_buf->Buffer.VirtualAddress,
-+			&tcb->PacketLength,
-+			BW);
-+
-+		tcb->bTxEnableSwCalcDur = true;
-+		tcb->BWOfPacket = BW;
-+
-+		/*rate of NDP decide by nr*/
-+		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);
-+	} else
-+		ret = false;
-+
-+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (ret)
-+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
-+
-+	return ret;
-+}
-+
-+#ifdef SUPPORT_MU_BF
-+#if (SUPPORT_MU_BF == 1)
-+/*@
-+ * Description: On VHT GID management frame by an MU beamformee.
-+ *
-+ * 2015.05.20. Created by tynli.
-+ */
-+enum rt_status
-+beamforming_get_vht_gid_mgnt_frame(
-+	void *adapter,
-+	PRT_RFD rfd,
-+	POCTET_STRING p_pdu_os)
-+{
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
-+	struct dm_struct *dm = &hal_data->DM_OutSrc;
-+	enum rt_status rt_status = RT_STATUS_SUCCESS;
-+	u8 *p_buffer = NULL;
-+	u8 *p_raddr = NULL;
-+	u8 mem_status[8] = {0}, user_pos[16] = {0};
-+	u8 idx;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+	struct _RT_BEAMFORMER_ENTRY *beamform_entry = &beam_info->beamformer_entry[beam_info->mu_ap_index];
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] On VHT GID mgnt frame!\n", __func__);
-+
-+	/* @Check length*/
-+	if (p_pdu_os->length < (FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY + 16)) {
-+		PHYDM_DBG(dm, DBG_TXBF, "%s: Invalid length (%d)\n", __func__,
-+			  p_pdu_os->length);
-+		return RT_STATUS_INVALID_LENGTH;
-+	}
-+
-+	/* @Check RA*/
-+	p_raddr = (u8 *)(p_pdu_os->Octet) + 4;
-+	if (!eq_mac_addr(p_raddr, adapter->CurrentAddress)) {
-+		PHYDM_DBG(dm, DBG_TXBF, "%s: Drop because of RA error.\n",
-+			  __func__);
-+		return RT_STATUS_PKT_DROP;
-+	}
-+
-+	RT_DISP_DATA(FBEAM, FBEAM_DATA, "On VHT GID Mgnt Frame ==>:\n", p_pdu_os->Octet, p_pdu_os->length);
-+
-+	/*Parsing Membership status array*/
-+	p_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY;
-+	for (idx = 0; idx < 8; idx++) {
-+		mem_status[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx);
-+		beamform_entry->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx);
-+	}
-+
-+	RT_DISP_DATA(FBEAM, FBEAM_DATA, "mem_status: ", mem_status, 8);
-+
-+	/* Parsing User Position array*/
-+	p_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY;
-+	for (idx = 0; idx < 16; idx++) {
-+		user_pos[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx);
-+		beamform_entry->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx);
-+	}
-+
-+	RT_DISP_DATA(FBEAM, FBEAM_DATA, "user_pos: ", user_pos, 16);
-+
-+	/* @Group ID detail printed*/
-+	{
-+		u8 i, j;
-+		u8 tmp_val;
-+		u16 tmp_val2;
-+
-+		for (i = 0; i < 8; i++) {
-+			tmp_val = mem_status[i];
-+			tmp_val2 = ((user_pos[i * 2 + 1] << 8) & 0xFF00) + (user_pos[i * 2] & 0xFF);
-+			for (j = 0; j < 8; j++) {
-+				if ((tmp_val >> j) & BIT(0)) {
-+					PHYDM_DBG(dm, DBG_TXBF, "Use Group ID (%d), User Position (%d)\n",
-+						  (i * 8 + j), (tmp_val2 >> 2 * j) & 0x3);
-+				}
-+			}
-+		}
-+	}
-+
-+	/* @Indicate GID frame to IHV service. */
-+	{
-+		u8 indibuffer[24] = {0};
-+		u8 indioffset = 0;
-+
-+		PlatformMoveMemory(indibuffer + indioffset, beamform_entry->gid_valid, 8);
-+		indioffset += 8;
-+		PlatformMoveMemory(indibuffer + indioffset, beamform_entry->user_position, 16);
-+		indioffset += 16;
-+
-+		PlatformIndicateCustomStatus(
-+			adapter,
-+			RT_CUSTOM_EVENT_VHT_RECV_GID_MGNT_FRAME,
-+			RT_CUSTOM_INDI_TARGET_IHV,
-+			indibuffer,
-+			indioffset);
-+	}
-+
-+	/* @Config HW GID table */
-+	hal_com_txbf_config_gtab(dm);
-+
-+	return rt_status;
-+}
-+
-+/*@
-+ * Description: Construct VHT Group ID (GID) management frame.
-+ *
-+ * 2015.05.20. Created by tynli.
-+ */
-+void construct_vht_gid_mgnt_frame(
-+	struct dm_struct *dm,
-+	u8 *RA,
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry,
-+	u8 *buffer,
-+	u32 *p_length
-+
-+	)
-+{
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+	void *adapter = beam_info->source_adapter;
-+	OCTET_STRING os_ftm_frame, tmp;
-+
-+	FillOctetString(os_ftm_frame, buffer, 0);
-+	*p_length = 0;
-+
-+	ConstructMaFrameHdr(
-+		adapter,
-+		RA,
-+		ACT_CAT_VHT,
-+		ACT_VHT_GROUPID_MANAGEMENT,
-+		&os_ftm_frame);
-+
-+	/* @Membership status array*/
-+	FillOctetString(tmp, beamform_entry->gid_valid, 8);
-+	PacketAppendData(&os_ftm_frame, tmp);
-+
-+	/* User Position array*/
-+	FillOctetString(tmp, beamform_entry->user_position, 16);
-+	PacketAppendData(&os_ftm_frame, tmp);
-+
-+	*p_length = os_ftm_frame.length;
-+
-+	RT_DISP_DATA(FBEAM, FBEAM_DATA, "construct_vht_gid_mgnt_frame():\n", buffer, *p_length);
-+}
-+
-+boolean
-+send_sw_vht_gid_mgnt_frame(
-+	void *dm_void,
-+	u8 *RA,
-+	u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	PRT_TCB tcb;
-+	PRT_TX_LOCAL_BUFFER p_buf;
-+	boolean ret = true;
-+	u8 data_rate = 0;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = &beam_info->beamformee_entry[idx];
-+	void *adapter = beam_info->source_adapter;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
-+		construct_vht_gid_mgnt_frame(
-+			dm,
-+			RA,
-+			beamform_entry,
-+			p_buf->Buffer.VirtualAddress,
-+			&tcb->PacketLength);
-+
-+		tcb->bw_of_packet = CHANNEL_WIDTH_20;
-+		data_rate = MGN_6M;
-+		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, data_rate);
-+	} else
-+		ret = false;
-+
-+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (ret)
-+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
-+
-+	return ret;
-+}
-+
-+/*@
-+ * Description: Construct VHT beamforming report poll.
-+ *
-+ * 2015.05.20. Created by tynli.
-+ */
-+void construct_vht_bf_report_poll(
-+	struct dm_struct *dm,
-+	u8 *RA,
-+	u8 *buffer,
-+	u32 *p_length)
-+{
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+	void *adapter = beam_info->source_adapter;
-+	u8 *p_bf_rpt_poll = buffer;
-+
-+	/* @Frame control*/
-+	SET_80211_HDR_FRAME_CONTROL(p_bf_rpt_poll, 0);
-+	SET_80211_HDR_TYPE_AND_SUBTYPE(p_bf_rpt_poll, Type_Beamforming_Report_Poll);
-+
-+	/* @duration*/
-+	SET_80211_HDR_DURATION(p_bf_rpt_poll, 100);
-+
-+	/* RA*/
-+	SET_VHT_BF_REPORT_POLL_RA(p_bf_rpt_poll, RA);
-+
-+	/* TA*/
-+	SET_VHT_BF_REPORT_POLL_TA(p_bf_rpt_poll, adapter->CurrentAddress);
-+
-+	/* @Feedback Segment Retransmission Bitmap*/
-+	SET_VHT_BF_REPORT_POLL_FEEDBACK_SEG_RETRAN_BITMAP(p_bf_rpt_poll, 0xFF);
-+
-+	*p_length = 17;
-+
-+	RT_DISP_DATA(FBEAM, FBEAM_DATA, "construct_vht_bf_report_poll():\n", buffer, *p_length);
-+}
-+
-+boolean
-+send_sw_vht_bf_report_poll(
-+	void *dm_void,
-+	u8 *RA,
-+	boolean is_final_poll)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	PRT_TCB tcb;
-+	PRT_TX_LOCAL_BUFFER p_buf;
-+	boolean ret = true;
-+	u8 idx = 0, data_rate = 0;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
-+	void *adapter = beam_info->source_adapter;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
-+		construct_vht_bf_report_poll(
-+			dm,
-+			RA,
-+			p_buf->Buffer.VirtualAddress,
-+			&tcb->PacketLength);
-+
-+		tcb->bTxEnableSwCalcDur = true; /* @<tynli_note> need?*/
-+		tcb->BWOfPacket = CHANNEL_WIDTH_20;
-+
-+		if (is_final_poll)
-+			tcb->TxBFPktType = RT_BF_PKT_TYPE_FINAL_BF_REPORT_POLL;
-+		else
-+			tcb->TxBFPktType = RT_BF_PKT_TYPE_BF_REPORT_POLL;
-+
-+		data_rate = MGN_6M; /* @Legacy OFDM rate*/
-+		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, data_rate);
-+	} else
-+		ret = false;
-+
-+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (ret)
-+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "send_sw_vht_bf_report_poll:\n",
-+		p_buf->Buffer.VirtualAddress, tcb->PacketLength);
-+
-+	return ret;
-+}
-+
-+/*@
-+ * Description: Construct VHT MU NDPA packet.
-+ *	<Note> We should combine this function with construct_vht_ndpa_packet() in the future.
-+ *
-+ * 2015.05.21. Created by tynli.
-+ */
-+void construct_vht_mu_ndpa_packet(
-+	struct dm_struct *dm,
-+	enum channel_width BW,
-+	u8 *buffer,
-+	u32 *p_length)
-+{
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+	void *adapter = beam_info->source_adapter;
-+	u16 duration = 0;
-+	u8 sequence = 0;
-+	u8 *p_ndpa_frame = buffer;
-+	struct _RT_NDPA_STA_INFO sta_info;
-+	u8 idx;
-+	u8 dest_addr[6] = {0};
-+	struct _RT_BEAMFORMEE_ENTRY *entry = NULL;
-+
-+	/* @Fill the first MU BFee entry (STA1) MAC addr to destination address then
-+	     HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */
-+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
-+		entry = &(beam_info->beamformee_entry[idx]);
-+		if (entry->is_mu_sta) {
-+			cp_mac_addr(dest_addr, entry->mac_addr);
-+			break;
-+		}
-+	}
-+	if (entry == NULL)
-+		return;
-+
-+	/* @Frame control.*/
-+	SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0);
-+	SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA);
-+
-+	SET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr);
-+	SET_80211_HDR_ADDRESS2(p_ndpa_frame, entry->my_mac_addr);
-+
-+	/*@--------------------------------------------*/
-+	/* @<Note> Need to modify "duration" to MU consideration. */
-+	duration = 2 * a_SifsTime + 44;
-+
-+	if (BW == CHANNEL_WIDTH_80)
-+		duration += 40;
-+	else if (BW == CHANNEL_WIDTH_40)
-+		duration += 87;
-+	else
-+		duration += 180;
-+	/*@--------------------------------------------*/
-+
-+	SET_80211_HDR_DURATION(p_ndpa_frame, duration);
-+
-+	sequence = *(dm->sounding_seq) << 2;
-+	odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1);
-+
-+	*p_length = 17;
-+
-+	/* @Construct STA info. for multiple STAs*/
-+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
-+		entry = &(beam_info->beamformee_entry[idx]);
-+		if (entry->is_mu_sta) {
-+			sta_info.aid = entry->AID;
-+			sta_info.feedback_type = 1; /* @1'b1: MU*/
-+			sta_info.nc_index = 0;
-+
-+			PHYDM_DBG(dm, DBG_TXBF,
-+				  "[%s] Get beamformee_entry idx(%d), AID =%d\n",
-+				  __func__, idx, entry->AID);
-+
-+			odm_move_memory(dm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2);
-+			*p_length += 2;
-+		}
-+	}
-+}
-+
-+boolean
-+send_sw_vht_mu_ndpa_packet(
-+	void *dm_void,
-+	enum channel_width BW)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	PRT_TCB tcb;
-+	PRT_TX_LOCAL_BUFFER p_buf;
-+	boolean ret = true;
-+	u8 ndp_tx_rate = 0;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+	void *adapter = beam_info->source_adapter;
-+
-+	ndp_tx_rate = MGN_VHT2SS_MCS0;
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
-+		  ndp_tx_rate);
-+
-+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
-+		construct_vht_mu_ndpa_packet(
-+			dm,
-+			BW,
-+			p_buf->Buffer.VirtualAddress,
-+			&tcb->PacketLength);
-+
-+		tcb->bTxEnableSwCalcDur = true;
-+		tcb->BWOfPacket = BW;
-+		tcb->TxBFPktType = RT_BF_PKT_TYPE_BROADCAST_NDPA;
-+
-+		/*rate of NDP decide by nr*/
-+		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);
-+	} else
-+		ret = false;
-+
-+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (ret)
-+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
-+
-+	return ret;
-+}
-+
-+void dbg_construct_vht_mundpa_packet(
-+	struct dm_struct *dm,
-+	enum channel_width BW,
-+	u8 *buffer,
-+	u32 *p_length)
-+{
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+	void *adapter = beam_info->source_adapter;
-+	u16 duration = 0;
-+	u8 sequence = 0;
-+	u8 *p_ndpa_frame = buffer;
-+	struct _RT_NDPA_STA_INFO sta_info;
-+	u8 idx;
-+	u8 dest_addr[6] = {0};
-+	struct _RT_BEAMFORMEE_ENTRY *entry = NULL;
-+
-+	boolean is_STA1 = false;
-+
-+	/* @Fill the first MU BFee entry (STA1) MAC addr to destination address then
-+	     HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */
-+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
-+		entry = &(beam_info->beamformee_entry[idx]);
-+		if (entry->is_mu_sta) {
-+			if (is_STA1 == false) {
-+				is_STA1 = true;
-+				continue;
-+			} else {
-+				cp_mac_addr(dest_addr, entry->mac_addr);
-+				break;
-+			}
-+		}
-+	}
-+
-+	/* @Frame control.*/
-+	SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0);
-+	SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA);
-+
-+	SET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr);
-+	SET_80211_HDR_ADDRESS2(p_ndpa_frame, dm->CurrentAddress);
-+
-+	/*@--------------------------------------------*/
-+	/* @<Note> Need to modify "duration" to MU consideration. */
-+	duration = 2 * a_SifsTime + 44;
-+
-+	if (BW == CHANNEL_WIDTH_80)
-+		duration += 40;
-+	else if (BW == CHANNEL_WIDTH_40)
-+		duration += 87;
-+	else
-+		duration += 180;
-+	/*@--------------------------------------------*/
-+
-+	SET_80211_HDR_DURATION(p_ndpa_frame, duration);
-+
-+	sequence = *(dm->sounding_seq) << 2;
-+	odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1);
-+
-+	*p_length = 17;
-+
-+	/*STA2's STA Info*/
-+	sta_info.aid = entry->aid;
-+	sta_info.feedback_type = 1; /* @1'b1: MU */
-+	sta_info.nc_index = 0;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Get beamformee_entry idx(%d), AID =%d\n",
-+		  __func__, idx, entry->aid);
-+
-+	odm_move_memory(dm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2);
-+	*p_length += 2;
-+}
-+
-+boolean
-+dbg_send_sw_vht_mundpa_packet(
-+	void *dm_void,
-+	enum channel_width BW)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	PRT_TCB tcb;
-+	PRT_TX_LOCAL_BUFFER p_buf;
-+	boolean ret = true;
-+	u8 ndp_tx_rate = 0;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+	void *adapter = beam_info->source_adapter;
-+
-+	ndp_tx_rate = MGN_VHT2SS_MCS0;
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
-+		  ndp_tx_rate);
-+
-+	PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (MgntGetBuffer(adapter, &tcb, &p_buf)) {
-+		dbg_construct_vht_mundpa_packet(
-+			dm,
-+			BW,
-+			p_buf->Buffer.VirtualAddress,
-+			&tcb->PacketLength);
-+
-+		tcb->bTxEnableSwCalcDur = true;
-+		tcb->BWOfPacket = BW;
-+		tcb->TxBFPktType = RT_BF_PKT_TYPE_UNICAST_NDPA;
-+
-+		/*rate of NDP decide by nr*/
-+		MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate);
-+	} else
-+		ret = false;
-+
-+	PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK);
-+
-+	if (ret)
-+		RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength);
-+
-+	return ret;
-+}
-+
-+#endif /*@#if (SUPPORT_MU_BF == 1)*/
-+#endif /*@#ifdef SUPPORT_MU_BF*/
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+
-+u32 beamforming_get_report_frame(
-+	void *dm_void,
-+	union recv_frame *precv_frame)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u32 ret = _SUCCESS;
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL;
-+	u8 *pframe = precv_frame->u.hdr.rx_data;
-+	u32 frame_len = precv_frame->u.hdr.len;
-+	u8 *TA;
-+	u8 idx, offset;
-+
-+	/*@Memory comparison to see if CSI report is the same with previous one*/
-+	TA = get_addr2_ptr(pframe);
-+	beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, TA, &idx);
-+	if (beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
-+		offset = 31; /*@24+(1+1+3)+2  MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/
-+	else if (beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)
-+		offset = 34; /*@24+(1+1+6)+2  MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/
-+	else
-+		return ret;
-+
-+	return ret;
-+}
-+
-+boolean
-+send_fw_ht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	enum channel_width BW)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ADAPTER *adapter = dm->adapter;
-+	struct xmit_frame *pmgntframe;
-+	struct pkt_attrib *pattrib;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};
-+	u8 *pframe;
-+	u16 *fctrl;
-+	u16 duration = 0;
-+	u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+
-+	if (pmgntframe == NULL) {
-+		PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n",
-+			  __func__);
-+		return false;
-+	}
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(adapter, pattrib);
-+
-+	pattrib->qsel = QSLT_BEACON;
-+	ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
-+		  ndp_tx_rate);
-+	pattrib->rate = ndp_tx_rate;
-+	pattrib->bwmode = BW;
-+	pattrib->order = 1;
-+	pattrib->subtype = WIFI_ACTION_NOACK;
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &pwlanhdr->frame_ctl;
-+	*(fctrl) = 0;
-+
-+	set_order_bit(pframe);
-+	set_frame_sub_type(pframe, WIFI_ACTION_NOACK);
-+
-+	_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
-+		a_sifs_time = 10;
-+	else
-+		a_sifs_time = 16;
-+
-+	duration = 2 * a_sifs_time + 40;
-+
-+	if (BW == CHANNEL_WIDTH_40)
-+		duration += 87;
-+	else
-+		duration += 180;
-+
-+	set_duration(pframe, duration);
-+
-+	/* @HT control field */
-+	SET_HT_CTRL_CSI_STEERING(pframe + 24, 3);
-+	SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);
-+
-+	_rtw_memcpy(pframe + 28, action_hdr, 4);
-+
-+	pattrib->pktlen = 32;
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(adapter, pmgntframe);
-+
-+	return true;
-+}
-+
-+boolean
-+send_sw_ht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	enum channel_width BW)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ADAPTER *adapter = dm->adapter;
-+	struct xmit_frame *pmgntframe;
-+	struct pkt_attrib *pattrib;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c};
-+	u8 *pframe;
-+	u16 *fctrl;
-+	u16 duration = 0;
-+	u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
-+
-+	ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+
-+	if (pmgntframe == NULL) {
-+		PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n",
-+			  __func__);
-+		return false;
-+	}
-+
-+	/*update attribute*/
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(adapter, pattrib);
-+	pattrib->qsel = QSLT_MGNT;
-+	pattrib->rate = ndp_tx_rate;
-+	pattrib->bwmode = BW;
-+	pattrib->order = 1;
-+	pattrib->subtype = WIFI_ACTION_NOACK;
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &pwlanhdr->frame_ctl;
-+	*(fctrl) = 0;
-+
-+	set_order_bit(pframe);
-+	set_frame_sub_type(pframe, WIFI_ACTION_NOACK);
-+
-+	_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
-+		a_sifs_time = 10;
-+	else
-+		a_sifs_time = 16;
-+
-+	duration = 2 * a_sifs_time + 40;
-+
-+	if (BW == CHANNEL_WIDTH_40)
-+		duration += 87;
-+	else
-+		duration += 180;
-+
-+	set_duration(pframe, duration);
-+
-+	/*@HT control field*/
-+	SET_HT_CTRL_CSI_STEERING(pframe + 24, 3);
-+	SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);
-+
-+	_rtw_memcpy(pframe + 28, action_hdr, 4);
-+
-+	pattrib->pktlen = 32;
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(adapter, pmgntframe);
-+
-+	return true;
-+}
-+
-+boolean
-+send_fw_vht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	u16 AID,
-+	enum channel_width BW)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ADAPTER *adapter = dm->adapter;
-+	struct xmit_frame *pmgntframe;
-+	struct pkt_attrib *pattrib;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
-+	u8 *pframe;
-+	u16 *fctrl;
-+	u16 duration = 0;
-+	u8 sequence = 0, a_sifs_time = 0, ndp_tx_rate = 0, idx = 0;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
-+	struct _RT_NDPA_STA_INFO sta_info;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+
-+	if (pmgntframe == NULL) {
-+		PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n",
-+			  __func__);
-+		return false;
-+	}
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	_rtw_memcpy(pattrib->ra, RA, ETH_ALEN);
-+	update_mgntframe_attrib(adapter, pattrib);
-+
-+	pattrib->qsel = QSLT_BEACON;
-+	ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
-+		  ndp_tx_rate);
-+	pattrib->rate = ndp_tx_rate;
-+	pattrib->bwmode = BW;
-+	pattrib->subtype = WIFI_NDPA;
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &pwlanhdr->frame_ctl;
-+	*(fctrl) = 0;
-+
-+	set_frame_sub_type(pframe, WIFI_NDPA);
-+
-+	_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);
-+
-+	if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
-+		a_sifs_time = 16;
-+	else
-+		a_sifs_time = 10;
-+
-+	duration = 2 * a_sifs_time + 44;
-+
-+	if (BW == CHANNEL_WIDTH_80)
-+		duration += 40;
-+	else if (BW == CHANNEL_WIDTH_40)
-+		duration += 87;
-+	else
-+		duration += 180;
-+
-+	set_duration(pframe, duration);
-+
-+	sequence = beam_info->sounding_sequence << 2;
-+	if (beam_info->sounding_sequence >= 0x3f)
-+		beam_info->sounding_sequence = 0;
-+	else
-+		beam_info->sounding_sequence++;
-+
-+	_rtw_memcpy(pframe + 16, &sequence, 1);
-+
-+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
-+		AID = 0;
-+
-+	sta_info.aid = AID;
-+	sta_info.feedback_type = 0;
-+	sta_info.nc_index = 0;
-+
-+	_rtw_memcpy(pframe + 17, (u8 *)&sta_info, 2);
-+
-+	pattrib->pktlen = 19;
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(adapter, pmgntframe);
-+
-+	return true;
-+}
-+
-+boolean
-+send_sw_vht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	u16 AID,
-+	enum channel_width BW)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _ADAPTER *adapter = dm->adapter;
-+	struct xmit_frame *pmgntframe;
-+	struct pkt_attrib *pattrib;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
-+	struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
-+	struct _RT_NDPA_STA_INFO ndpa_sta_info;
-+	u8 ndp_tx_rate = 0, sequence = 0, a_sifs_time = 0, idx = 0;
-+	u8 *pframe;
-+	u16 *fctrl;
-+	u16 duration = 0;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info);
-+	struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx);
-+
-+	ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer);
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__,
-+		  ndp_tx_rate);
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+
-+	if (pmgntframe == NULL) {
-+		PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n",
-+			  __func__);
-+		return false;
-+	}
-+
-+	/*update attribute*/
-+	pattrib = &pmgntframe->attrib;
-+	_rtw_memcpy(pattrib->ra, RA, ETH_ALEN);
-+	update_mgntframe_attrib(adapter, pattrib);
-+	pattrib->qsel = QSLT_MGNT;
-+	pattrib->rate = ndp_tx_rate;
-+	pattrib->bwmode = BW;
-+	pattrib->subtype = WIFI_NDPA;
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &pwlanhdr->frame_ctl;
-+	*(fctrl) = 0;
-+
-+	set_frame_sub_type(pframe, WIFI_NDPA);
-+
-+	_rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN);
-+
-+	if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
-+		a_sifs_time = 16;
-+	else
-+		a_sifs_time = 10;
-+
-+	duration = 2 * a_sifs_time + 44;
-+
-+	if (BW == CHANNEL_WIDTH_80)
-+		duration += 40;
-+	else if (BW == CHANNEL_WIDTH_40)
-+		duration += 87;
-+	else
-+		duration += 180;
-+
-+	set_duration(pframe, duration);
-+
-+	sequence = beam_info->sounding_sequence << 2;
-+	if (beam_info->sounding_sequence >= 0x3f)
-+		beam_info->sounding_sequence = 0;
-+	else
-+		beam_info->sounding_sequence++;
-+
-+	_rtw_memcpy(pframe + 16, &sequence, 1);
-+	if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
-+		AID = 0;
-+
-+	ndpa_sta_info.aid = AID;
-+	ndpa_sta_info.feedback_type = 0;
-+	ndpa_sta_info.nc_index = 0;
-+
-+	_rtw_memcpy(pframe + 17, (u8 *)&ndpa_sta_info, 2);
-+
-+	pattrib->pktlen = 19;
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	dump_mgntframe(adapter, pmgntframe);
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] [%d]\n", __func__, __LINE__);
-+
-+	return true;
-+}
-+
-+#endif
-+
-+void beamforming_get_ndpa_frame(
-+	void *dm_void,
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	OCTET_STRING pdu_os
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	union recv_frame *precv_frame
-+#endif
-+	)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 *TA;
-+	u8 idx, sequence;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	u8 *p_ndpa_frame = pdu_os.Octet;
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	u8 *p_ndpa_frame = precv_frame->u.hdr.rx_data;
-+#endif
-+	struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL; /*@Modified By Jeffery @2014-10-29*/
-+
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	RT_DISP_DATA(FBEAM, FBEAM_DATA, "beamforming_get_ndpa_frame\n",
-+	pdu_os.Octet, pdu_os.Length);
-+	if (IsCtrlNDPA(p_ndpa_frame) == false)
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	if (get_frame_sub_type(p_ndpa_frame) != WIFI_NDPA)
-+#endif
-+		return;
-+	else if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))) {
-+		PHYDM_DBG(dm, DBG_TXBF, "[%s] not 8812 or 8821A, return\n",
-+			  __func__);
-+		return;
-+	}
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	TA = Frame_Addr2(pdu_os);
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	TA = get_addr2_ptr(p_ndpa_frame);
-+#endif
-+	/*Remove signaling TA. */
-+	TA[0] = TA[0] & 0xFE;
-+
-+	beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, TA, &idx); /* @Modified By Jeffery @2014-10-29 */
-+
-+	/*@Break options for Clock Reset*/
-+	if (beamformer_entry == NULL)
-+		return;
-+	else if (!(beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU))
-+		return;
-+	/*@log_success: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/
-+	/*@clock_reset_times: While BFer entry always doesn't receive our CSI, clock will reset again and again.So clock_reset_times is limited to 5 times.2015-04-13, Jeffery*/
-+	else if ((beamformer_entry->log_success == 1) || (beamformer_entry->clock_reset_times == 5)) {
-+		PHYDM_DBG(dm, DBG_TXBF,
-+			  "[%s] log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, log_success=%d, clock_reset_times=%d, clock reset is no longer needed.\n",
-+			  __func__, beamformer_entry->log_seq,
-+			  beamformer_entry->pre_log_seq,
-+			  beamformer_entry->log_retry_cnt,
-+			  beamformer_entry->log_success,
-+			  beamformer_entry->clock_reset_times);
-+
-+		return;
-+	}
-+
-+	sequence = (p_ndpa_frame[16]) >> 2;
-+
-+	PHYDM_DBG(dm, DBG_TXBF,
-+		  "[%s] Start, sequence=%d, log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, clock_reset_times=%d, log_success=%d\n",
-+		  __func__, sequence, beamformer_entry->log_seq,
-+		  beamformer_entry->pre_log_seq,
-+		  beamformer_entry->log_retry_cnt,
-+		  beamformer_entry->clock_reset_times,
-+		  beamformer_entry->log_success);
-+
-+	if (beamformer_entry->log_seq != 0 && beamformer_entry->pre_log_seq != 0) {
-+		/*Success condition*/
-+		if (beamformer_entry->log_seq != sequence && beamformer_entry->pre_log_seq != beamformer_entry->log_seq) {
-+			/* @break option for clcok reset, 2015-03-30, Jeffery */
-+			beamformer_entry->log_retry_cnt = 0;
-+			/*@As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/
-+			/*That is, log_success is NOT needed to be reset to zero, 2015-04-13, Jeffery*/
-+			beamformer_entry->log_success = 1;
-+
-+		} else { /*@Fail condition*/
-+
-+			if (beamformer_entry->log_retry_cnt == 5) {
-+				beamformer_entry->clock_reset_times++;
-+				beamformer_entry->log_retry_cnt = 0;
-+
-+				PHYDM_DBG(dm, DBG_TXBF,
-+					  "[%s] Clock Reset!!! clock_reset_times=%d\n",
-+					  __func__,
-+					  beamformer_entry->clock_reset_times);
-+				hal_com_txbf_set(dm, TXBF_SET_SOUNDING_CLK, NULL);
-+
-+			} else
-+				beamformer_entry->log_retry_cnt++;
-+		}
-+	}
-+
-+	/*Update log_seq & pre_log_seq*/
-+	beamformer_entry->pre_log_seq = beamformer_entry->log_seq;
-+	beamformer_entry->log_seq = sequence;
-+}
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbfinterface.h b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbfinterface.h
-new file mode 100644
-index 000000000000..b97aa349e702
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbfinterface.h
-@@ -0,0 +1,167 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_TXBF_INTERFACE_H__
-+#define __HAL_TXBF_INTERFACE_H__
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+
-+#define a_SifsTime ((IS_WIRELESS_MODE_5G(adapter) || IS_WIRELESS_MODE_N_24G(adapter)) ? 16 : 10)
-+
-+void beamforming_gid_paid(
-+	void *adapter,
-+	PRT_TCB tcb);
-+
-+enum rt_status
-+beamforming_get_report_frame(
-+	void *adapter,
-+	PRT_RFD rfd,
-+	POCTET_STRING p_pdu_os);
-+
-+void beamforming_get_ndpa_frame(
-+	void *dm_void,
-+	OCTET_STRING pdu_os);
-+
-+boolean
-+send_fw_ht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	enum channel_width BW);
-+
-+boolean
-+send_fw_vht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	u16 AID,
-+	enum channel_width BW);
-+
-+boolean
-+send_sw_vht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	u16 AID,
-+	enum channel_width BW);
-+
-+boolean
-+send_sw_ht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	enum channel_width BW);
-+
-+#if (SUPPORT_MU_BF == 1)
-+enum rt_status
-+beamforming_get_vht_gid_mgnt_frame(
-+	void *adapter,
-+	PRT_RFD rfd,
-+	POCTET_STRING p_pdu_os);
-+
-+boolean
-+send_sw_vht_gid_mgnt_frame(
-+	void *dm_void,
-+	u8 *RA,
-+	u8 idx);
-+
-+boolean
-+send_sw_vht_bf_report_poll(
-+	void *dm_void,
-+	u8 *RA,
-+	boolean is_final_poll);
-+
-+boolean
-+send_sw_vht_mu_ndpa_packet(
-+	void *dm_void,
-+	enum channel_width BW);
-+#else
-+#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE
-+#define send_sw_vht_gid_mgnt_frame(dm_void, RA)
-+#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll)
-+#define send_sw_vht_mu_ndpa_packet(dm_void, BW)
-+#endif
-+
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+
-+u32 beamforming_get_report_frame(
-+	void *dm_void,
-+	union recv_frame *precv_frame);
-+
-+boolean
-+send_fw_ht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	enum channel_width BW);
-+
-+boolean
-+send_sw_ht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	enum channel_width BW);
-+
-+boolean
-+send_fw_vht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	u16 AID,
-+	enum channel_width BW);
-+
-+boolean
-+send_sw_vht_ndpa_packet(
-+	void *dm_void,
-+	u8 *RA,
-+	u16 AID,
-+	enum channel_width BW);
-+#endif
-+
-+void beamforming_get_ndpa_frame(
-+	void *dm_void,
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	OCTET_STRING pdu_os
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+	union recv_frame *precv_frame
-+#endif
-+	);
-+
-+boolean
-+dbg_send_sw_vht_mundpa_packet(
-+	void *dm_void,
-+	enum channel_width BW);
-+
-+#else
-+#define beamforming_get_ndpa_frame(dm, _pdu_os)
-+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-+#define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE
-+#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+#define beamforming_get_report_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE
-+#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE
-+#endif
-+#define send_fw_ht_ndpa_packet(dm_void, RA, BW)
-+#define send_sw_ht_ndpa_packet(dm_void, RA, BW)
-+#define send_fw_vht_ndpa_packet(dm_void, RA, AID, BW)
-+#define send_sw_vht_ndpa_packet(dm_void, RA, AID, BW)
-+#define send_sw_vht_gid_mgnt_frame(dm_void, RA, idx)
-+#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll)
-+#define send_sw_vht_mu_ndpa_packet(dm_void, BW)
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbfjaguar.c b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbfjaguar.c
-new file mode 100644
-index 000000000000..6f1892837ada
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbfjaguar.c
-@@ -0,0 +1,509 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*************************************************************
-+ * Description:
-+ *
-+ * This file is for 8812/8821/8811 TXBF mechanism
-+ *
-+ ************************************************************/
-+#include "mp_precomp.h"
-+#include "../phydm_precomp.h"
-+
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
-+void hal_txbf_8812a_set_ndpa_rate(
-+	void *dm_void,
-+	u8 BW,
-+	u8 rate)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8812A, (rate << 2 | BW));
-+}
-+
-+void hal_txbf_jaguar_rf_mode(
-+	void *dm_void,
-+	struct _RT_BEAMFORMING_INFO *beam_info)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	if (dm->rf_type == RF_1T1R)
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] set TxIQGen\n", __func__);
-+
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/
-+	odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/
-+
-+	if (beam_info->beamformee_su_cnt > 0) {
-+		/* Paath_A */
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/
-+		/* Path_B */
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/
-+	} else {
-+		/* Paath_A */
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
-+		odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/
-+		/* Path_B */
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/
-+		odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/
-+	}
-+
-+	odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/
-+	odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/
-+
-+	if (beam_info->beamformee_su_cnt > 0)
-+		odm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x33);
-+	else
-+		odm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x11);
-+}
-+
-+void hal_txbf_jaguar_download_ndpa(
-+	void *dm_void,
-+	u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 u1b_tmp = 0, tmp_reg422 = 0, head_page;
-+	u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
-+	boolean is_send_beacon = false;
-+	u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*@default reseved 1 page for the IC type which is undefined.*/
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
-+	void *adapter = dm->adapter;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	*dm->is_fw_dw_rsvd_page_in_progress = true;
-+#endif
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	/* if (idx == 0) head_page = 0xFE; */
-+	/* else	head_page = 0xFE;*/
-+	head_page = 0xFE;
-+
-+	phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);
-+
-+	/*Set REG_CR bit 8. DMA beacon by SW.*/
-+	u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1);
-+	odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp | BIT(0)));
-+
-+	/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
-+	tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2);
-+	odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422 & (~BIT(6)));
-+
-+	if (tmp_reg422 & BIT(6)) {
-+		PHYDM_DBG(dm, DBG_TXBF,
-+			  "SetBeamformDownloadNDPA_8812(): There is an adapter is sending beacon.\n");
-+		is_send_beacon = true;
-+	}
-+
-+	/*TDECTRL[15:8] 0x209[7:0] = 0xF6	Beacon Head for TXDMA*/
-+	odm_write_1byte(dm, REG_TDECTRL_8812A + 1, head_page);
-+
-+	do {
-+		/*@Clear beacon valid check bit.*/
-+		bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);
-+		odm_write_1byte(dm, REG_TDECTRL_8812A + 2, (bcn_valid_reg | BIT(0)));
-+
-+		/*@download NDPA rsvd page.*/
-+		if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
-+			beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->aid, p_beam_entry->sound_bw, BEACON_QUEUE);
-+		else
-+			beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
-+
-+		/*@check rsvd page download OK.*/
-+		bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);
-+		count = 0;
-+		while (!(bcn_valid_reg & BIT(0)) && count < 20) {
-+			count++;
-+			ODM_delay_ms(10);
-+			bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2);
-+		}
-+		dl_bcn_count++;
-+	} while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);
-+
-+	if (!(bcn_valid_reg & BIT(0)))
-+		PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
-+			  __func__);
-+
-+	/*TDECTRL[15:8] 0x209[7:0] = 0xF6	Beacon Head for TXDMA*/
-+	odm_write_1byte(dm, REG_TDECTRL_8812A + 1, tx_page_bndy);
-+
-+	/*To make sure that if there exists an adapter which would like to send beacon.*/
-+	/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
-+	/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
-+	/*the beacon cannot be sent by HW.*/
-+	/*@2010.06.23. Added by tynli.*/
-+	if (is_send_beacon)
-+		odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422);
-+
-+	/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
-+	/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
-+	u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1);
-+	odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp & (~BIT(0))));
-+
-+	p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	*dm->is_fw_dw_rsvd_page_in_progress = false;
-+#endif
-+}
-+
-+void hal_txbf_jaguar_fw_txbf_cmd(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 idx, period0 = 0, period1 = 0;
-+	u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
-+	u8 u1_tx_bf_parm[3] = {0};
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
-+		/*@Modified by David*/
-+		if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
-+			if (idx == 0) {
-+				if (beam_info->beamformee_entry[idx].is_sound)
-+					PageNum0 = 0xFE;
-+				else
-+					PageNum0 = 0xFF; /*stop sounding*/
-+				period0 = (u8)(beam_info->beamformee_entry[idx].sound_period);
-+			} else if (idx == 1) {
-+				if (beam_info->beamformee_entry[idx].is_sound)
-+					PageNum1 = 0xFE;
-+				else
-+					PageNum1 = 0xFF; /*stop sounding*/
-+				period1 = (u8)(beam_info->beamformee_entry[idx].sound_period);
-+			}
-+		}
-+	}
-+
-+	u1_tx_bf_parm[0] = PageNum0;
-+	u1_tx_bf_parm[1] = PageNum1;
-+	u1_tx_bf_parm[2] = (period1 << 4) | period0;
-+	odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
-+
-+	PHYDM_DBG(dm, DBG_TXBF,
-+		  "[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n",
-+		  __func__, PageNum0, period0, PageNum1, period1);
-+}
-+
-+void hal_txbf_jaguar_enter(
-+	void *dm_void,
-+	u8 bfer_bfee_idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i = 0;
-+	u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
-+	u8 bfee_idx = (bfer_bfee_idx & 0xF);
-+	u32 csi_param;
-+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
-+	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
-+	u16 sta_id = 0;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!\n", __func__);
-+
-+	hal_txbf_jaguar_rf_mode(dm, beamforming_info);
-+
-+	if (dm->rf_type == RF_2T2R)
-+		odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x00000000); /*nc =2*/
-+	else
-+		odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x01081008); /*nc =1*/
-+
-+	if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
-+		beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
-+
-+		/*Sounding protocol control*/
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB);
-+
-+		/*@MAC address/Partial AID of Beamformer*/
-+		if (bfer_idx == 0) {
-+			for (i = 0; i < 6; i++)
-+				odm_write_1byte(dm, (REG_BFMER0_INFO_8812A + i), beamformer_entry.mac_addr[i]);
-+			/*@CSI report use legacy ofdm so don't need to fill P_AID. */
-+			/*platform_efio_write_2byte(adapter, REG_BFMER0_INFO_8812A+6, beamform_entry.P_AID); */
-+		} else {
-+			for (i = 0; i < 6; i++)
-+				odm_write_1byte(dm, (REG_BFMER1_INFO_8812A + i), beamformer_entry.mac_addr[i]);
-+			/*@CSI report use legacy ofdm so don't need to fill P_AID.*/
-+			/*platform_efio_write_2byte(adapter, REG_BFMER1_INFO_8812A+6, beamform_entry.P_AID);*/
-+		}
-+
-+		/*@CSI report parameters of Beamformee*/
-+		if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) {
-+			if (dm->rf_type == RF_2T2R)
-+				csi_param = 0x01090109;
-+			else
-+				csi_param = 0x01080108;
-+		} else {
-+			if (dm->rf_type == RF_2T2R)
-+				csi_param = 0x03090309;
-+			else
-+				csi_param = 0x03080308;
-+		}
-+
-+		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, csi_param);
-+		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, csi_param);
-+		odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, csi_param);
-+
-+		/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us,  MP chip)*/
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A + 3, 0x50);
-+	}
-+
-+	if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
-+		beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
-+
-+		if (phydm_acting_determine(dm, phydm_acting_as_ibss))
-+			sta_id = beamformee_entry.mac_id;
-+		else
-+			sta_id = beamformee_entry.p_aid;
-+
-+		/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
-+		if (bfee_idx == 0) {
-+			odm_write_2byte(dm, REG_TXBF_CTRL_8812A, sta_id);
-+			odm_write_1byte(dm, REG_TXBF_CTRL_8812A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8812A + 3) | BIT(4) | BIT(6) | BIT(7));
-+		} else
-+			odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, sta_id | BIT(12) | BIT(14) | BIT(15));
-+
-+		/*@CSI report parameters of Beamformee*/
-+		if (bfee_idx == 0) {
-+			/*@Get BIT24 & BIT25*/
-+			u8 tmp = odm_read_1byte(dm, REG_BFMEE_SEL_8812A + 3) & 0x3;
-+
-+			odm_write_1byte(dm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60);
-+			odm_write_2byte(dm, REG_BFMEE_SEL_8812A, sta_id | BIT(9));
-+		} else {
-+			/*Set BIT25*/
-+			odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, sta_id | 0xE200);
-+		}
-+		phydm_beamforming_notify(dm);
-+	}
-+}
-+
-+void hal_txbf_jaguar_leave(
-+	void *dm_void,
-+	u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMER_ENTRY beamformer_entry;
-+	struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
-+
-+	if (idx < BEAMFORMER_ENTRY_NUM) {
-+		beamformer_entry = beamforming_info->beamformer_entry[idx];
-+		beamformee_entry = beamforming_info->beamformee_entry[idx];
-+	} else
-+		return;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!, IDx = %d\n", __func__, idx);
-+
-+	/*@Clear P_AID of Beamformee*/
-+	/*@Clear MAC address of Beamformer*/
-+	/*@Clear Associated Bfmee Sel*/
-+
-+	if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8);
-+		if (idx == 0) {
-+			odm_write_4byte(dm, REG_BFMER0_INFO_8812A, 0);
-+			odm_write_2byte(dm, REG_BFMER0_INFO_8812A + 4, 0);
-+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0);
-+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0);
-+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0);
-+		} else {
-+			odm_write_4byte(dm, REG_BFMER1_INFO_8812A, 0);
-+			odm_write_2byte(dm, REG_BFMER1_INFO_8812A + 4, 0);
-+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0);
-+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0);
-+			odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0);
-+		}
-+	}
-+
-+	if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
-+		hal_txbf_jaguar_rf_mode(dm, beamforming_info);
-+		if (idx == 0) {
-+			odm_write_2byte(dm, REG_TXBF_CTRL_8812A, 0x0);
-+			odm_write_2byte(dm, REG_BFMEE_SEL_8812A, 0);
-+		} else {
-+			odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, odm_read_2byte(dm, REG_TXBF_CTRL_8812A + 2) & 0xF000);
-+			odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, odm_read_2byte(dm, REG_BFMEE_SEL_8812A + 2) & 0x60);
-+		}
-+	}
-+}
-+
-+void hal_txbf_jaguar_status(
-+	void *dm_void,
-+	u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u16 beam_ctrl_val;
-+	u32 beam_ctrl_reg;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];
-+
-+	if (phydm_acting_determine(dm, phydm_acting_as_ibss))
-+		beam_ctrl_val = beamform_entry.mac_id;
-+	else
-+		beam_ctrl_val = beamform_entry.p_aid;
-+
-+	if (idx == 0)
-+		beam_ctrl_reg = REG_TXBF_CTRL_8812A;
-+	else {
-+		beam_ctrl_reg = REG_TXBF_CTRL_8812A + 2;
-+		beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
-+	}
-+
-+	if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) {
-+		if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
-+			beam_ctrl_val |= BIT(9);
-+		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
-+			beam_ctrl_val |= (BIT(9) | BIT(10));
-+		else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80)
-+			beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
-+	} else
-+		beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] beam_ctrl_val = 0x%x!\n", __func__,
-+		  beam_ctrl_val);
-+
-+	odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
-+}
-+
-+void hal_txbf_jaguar_fw_txbf(
-+	void *dm_void,
-+	u8 idx)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+	struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
-+		hal_txbf_jaguar_download_ndpa(dm, idx);
-+
-+	hal_txbf_jaguar_fw_txbf_cmd(dm);
-+}
-+
-+void hal_txbf_jaguar_patch(
-+	void *dm_void,
-+	u8 operation)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE)
-+		return;
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	if (operation == SCAN_OPT_BACKUP_BAND0)
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8);
-+	else if (operation == SCAN_OPT_RESTORE)
-+		odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB);
-+#endif
-+}
-+
-+void hal_txbf_jaguar_clk_8812a(
-+	void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u16 u2btmp;
-+	u8 count = 0, u1btmp;
-+	void *adapter = dm->adapter;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
-+
-+	if (*dm->is_scan_in_process) {
-+		PHYDM_DBG(dm, DBG_TXBF, "[%s] return by Scan\n", __func__);
-+		return;
-+	}
-+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+	/*Stop PCIe TxDMA*/
-+	if (dm->support_interface == ODM_ITRF_PCIE)
-+		odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE);
-+#endif
-+
-+/*Stop Usb TxDMA*/
-+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-+	RT_DISABLE_FUNC((PADAPTER)adapter, DF_TX_BIT);
-+	PlatformReturnAllPendingTxPackets(adapter);
-+#else
-+	rtw_write_port_cancel(adapter);
-+#endif
-+
-+	/*Wait TXFF empty*/
-+	for (count = 0; count < 100; count++) {
-+		u2btmp = odm_read_2byte(dm, REG_TXPKT_EMPTY_8812A);
-+		u2btmp = u2btmp & 0xfff;
-+		if (u2btmp != 0xfff) {
-+			ODM_delay_ms(10);
-+			continue;
-+		} else
-+			break;
-+	}
-+
-+	/*TX pause*/
-+	odm_write_1byte(dm, REG_TXPAUSE_8812A, 0xFF);
-+
-+	/*Wait TX state Machine OK*/
-+	for (count = 0; count < 100; count++) {
-+		if (odm_read_4byte(dm, REG_SCH_TXCMD_8812A) != 0)
-+			continue;
-+		else
-+			break;
-+	}
-+
-+	/*Stop RX DMA path*/
-+	u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);
-+	odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT(2));
-+
-+	for (count = 0; count < 100; count++) {
-+		u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);
-+		if (u1btmp & BIT(1))
-+			break;
-+		else
-+			ODM_delay_ms(10);
-+	}
-+
-+	/*@Disable clock*/
-+	odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xf0);
-+	/*@Disable 320M*/
-+	odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0x8);
-+	/*@Enable 320M*/
-+	odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0xa);
-+	/*@Enable clock*/
-+	odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xfc);
-+
-+	/*Release Tx pause*/
-+	odm_write_1byte(dm, REG_TXPAUSE_8812A, 0);
-+
-+	/*@Enable RX DMA path*/
-+	u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A);
-+	odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT(2)));
-+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
-+	/*@Enable PCIe TxDMA*/
-+	if (dm->support_interface == ODM_ITRF_PCIE)
-+		odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0);
-+#endif
-+	/*Start Usb TxDMA*/
-+	RT_ENABLE_FUNC((PADAPTER)adapter, DF_TX_BIT);
-+}
-+
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbfjaguar.h b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbfjaguar.h
-new file mode 100644
-index 000000000000..2c9a623baf18
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/txbf/haltxbfjaguar.h
-@@ -0,0 +1,78 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_TXBF_JAGUAR_H__
-+#define __HAL_TXBF_JAGUAR_H__
-+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
-+#ifdef PHYDM_BEAMFORMING_SUPPORT
-+
-+void hal_txbf_8812a_set_ndpa_rate(
-+	void *dm_void,
-+	u8 BW,
-+	u8 rate);
-+
-+void hal_txbf_jaguar_enter(
-+	void *dm_void,
-+	u8 idx);
-+
-+void hal_txbf_jaguar_leave(
-+	void *dm_void,
-+	u8 idx);
-+
-+void hal_txbf_jaguar_status(
-+	void *dm_void,
-+	u8 idx);
-+
-+void hal_txbf_jaguar_fw_txbf(
-+	void *dm_void,
-+	u8 idx);
-+
-+void hal_txbf_jaguar_patch(
-+	void *dm_void,
-+	u8 operation);
-+
-+void hal_txbf_jaguar_clk_8812a(
-+	void *dm_void);
-+#else
-+
-+#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate)
-+#define hal_txbf_jaguar_enter(dm_void, idx)
-+#define hal_txbf_jaguar_leave(dm_void, idx)
-+#define hal_txbf_jaguar_status(dm_void, idx)
-+#define hal_txbf_jaguar_fw_txbf(dm_void, idx)
-+#define hal_txbf_jaguar_patch(dm_void, operation)
-+#define hal_txbf_jaguar_clk_8812a(dm_void)
-+#endif
-+#else
-+
-+#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate)
-+#define hal_txbf_jaguar_enter(dm_void, idx)
-+#define hal_txbf_jaguar_leave(dm_void, idx)
-+#define hal_txbf_jaguar_status(dm_void, idx)
-+#define hal_txbf_jaguar_fw_txbf(dm_void, idx)
-+#define hal_txbf_jaguar_patch(dm_void, operation)
-+#define hal_txbf_jaguar_clk_8812a(dm_void)
-+#endif
-+
-+#endif /*  @#ifndef __HAL_TXBF_JAGUAR_H__ */
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/txbf/phydm_hal_txbf_api.c b/drivers/staging/rtl8723cs/hal/phydm/txbf/phydm_hal_txbf_api.c
-new file mode 100644
-index 000000000000..33a7e71ff3f8
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/txbf/phydm_hal_txbf_api.c
-@@ -0,0 +1,759 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include "mp_precomp.h"
-+#include "phydm_precomp.h"
-+
-+#if (defined(CONFIG_BB_TXBF_API))
-+#if (RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8812F_SUPPORT == 1 ||\
-+	RTL8822C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8814B_SUPPORT == 1)
-+/*@Add by YuChen for 8822B MU-MIMO API*/
-+
-+/*this function is only used for BFer*/
-+u8 phydm_get_ndpa_rate(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 ndpa_rate = ODM_RATE6M;
-+
-+	if (dm->rssi_min >= 30) /*@link RSSI > 30%*/
-+		ndpa_rate = ODM_RATE24M;
-+	else if (dm->rssi_min <= 25)
-+		ndpa_rate = ODM_RATE6M;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] ndpa_rate = 0x%x\n", __func__, ndpa_rate);
-+
-+	return ndpa_rate;
-+}
-+
-+/*this function is only used for BFer*/
-+u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput,
-+				       u8 total_bfee_num, u8 *tx_rate)
-+{
-+	u8 idx = 0;
-+	u8 snddecision = 0xff;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	for (idx = 0; idx < total_bfee_num; idx++) {
-+		if (dm->support_ic_type & (ODM_RTL8814A)) {
-+			if ((tx_rate[idx] >= ODM_RATEVHTSS3MCS7 &&
-+			     tx_rate[idx] <= ODM_RATEVHTSS3MCS9))
-+				snddecision = snddecision & ~(1 << idx);
-+		} else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C |
-+			   ODM_RTL8812 | ODM_RTL8192F)) {
-+			if ((tx_rate[idx] >= ODM_RATEVHTSS2MCS7 &&
-+			     tx_rate[idx] <= ODM_RATEVHTSS2MCS9))
-+				snddecision = snddecision & ~(1 << idx);
-+		} else if (dm->support_ic_type & (ODM_RTL8814B)) {
-+			if ((tx_rate[idx] >= ODM_RATEVHTSS4MCS7 &&
-+			     tx_rate[idx] <= ODM_RATEVHTSS4MCS9))
-+				snddecision = snddecision & ~(1 << idx);
-+		}
-+	}
-+
-+	for (idx = 0; idx < total_bfee_num; idx++) {
-+		if (throughput[idx] <= 10)
-+			snddecision = snddecision & ~(1 << idx);
-+	}
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] soundingdecision = 0x%x\n", __func__,
-+		  snddecision);
-+
-+	return snddecision;
-+}
-+
-+/*this function is only used for BFer*/
-+u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput)
-+{
-+	u8 snding_score = 0;
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+
-+	/*throughput unit is Mbps*/
-+	if (throughput >= 500)
-+		snding_score = 100;
-+	else if (throughput >= 450)
-+		snding_score = 90;
-+	else if (throughput >= 400)
-+		snding_score = 80;
-+	else if (throughput >= 350)
-+		snding_score = 70;
-+	else if (throughput >= 300)
-+		snding_score = 60;
-+	else if (throughput >= 250)
-+		snding_score = 50;
-+	else if (throughput >= 200)
-+		snding_score = 40;
-+	else if (throughput >= 150)
-+		snding_score = 30;
-+	else if (throughput >= 100)
-+		snding_score = 20;
-+	else if (throughput >= 50)
-+		snding_score = 10;
-+	else
-+		snding_score = 0;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[%s] snding_score = 0x%x\n", __func__,
-+		  snding_score);
-+
-+	return snding_score;
-+}
-+
-+#endif
-+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 nr_index = 0;
-+	u8 ndp_tx_rate;
-+/*@Find nr*/
-+#if (RTL8814A_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814A)
-+		nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);
-+	else
-+		nr_index = tx_bf_nr(1, bfer_str_num);
-+
-+	switch (nr_index) {
-+	case 1:
-+		ndp_tx_rate = ODM_MGN_MCS8;
-+		break;
-+
-+	case 2:
-+		ndp_tx_rate = ODM_MGN_MCS16;
-+		break;
-+
-+	case 3:
-+		ndp_tx_rate = ODM_MGN_MCS24;
-+		break;
-+
-+	default:
-+		ndp_tx_rate = ODM_MGN_MCS8;
-+		break;
-+	}
-+#else
-+	ndp_tx_rate = ODM_MGN_MCS8;
-+#endif
-+
-+	return ndp_tx_rate;
-+}
-+
-+u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 nr_index = 0;
-+	u8 ndp_tx_rate;
-+/*@Find nr*/
-+#if (RTL8814A_SUPPORT == 1)
-+	if (dm->support_ic_type & ODM_RTL8814A)
-+		nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num);
-+	else
-+		nr_index = tx_bf_nr(1, bfer_str_num);
-+
-+	switch (nr_index) {
-+	case 1:
-+		ndp_tx_rate = ODM_MGN_VHT2SS_MCS0;
-+		break;
-+
-+	case 2:
-+		ndp_tx_rate = ODM_MGN_VHT3SS_MCS0;
-+		break;
-+
-+	case 3:
-+		ndp_tx_rate = ODM_MGN_VHT4SS_MCS0;
-+		break;
-+
-+	default:
-+		ndp_tx_rate = ODM_MGN_VHT2SS_MCS0;
-+		break;
-+	}
-+#else
-+	ndp_tx_rate = ODM_MGN_VHT2SS_MCS0;
-+#endif
-+
-+	return ndp_tx_rate;
-+}
-+#endif
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+/*this function is only used for BFer*/
-+void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i;
-+
-+	if (dm->rf_type == RF_1T1R)
-+		return;
-+#if (RTL8822C_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8822C) {
-+		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
-+			/*Path A ==================*/
-+			/*RF mode table write enable*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x1);
-+			/*Select RX mode*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, 0xF, 3);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, 0x3, 0x2);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0xfffff,
-+				       0x65AFF);
-+			/*RF mode table write disable*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x0);
-+
-+			/*Path B ==================*/
-+			/*RF mode table write enable*/
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x1);
-+			/*Select RX mode*/
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 3);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff,
-+				       0x996BF);
-+			/*Select Standby mode*/
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 1);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff,
-+				       0x99230);
-+			/*RF mode table write disable*/
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x0);
-+		}
-+
-+		/*@if Nsts > Nc, don't apply V matrix*/
-+		odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
-+
-+		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
-+			/*@enable BB TxBF ant mapping register*/
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
-+
-+			/* logic mapping */
-+			/* TX BF logic map and TX path en for Nsts = 1~2 */
-+			odm_set_bb_reg(dm, R_0x820, 0xff, 0x33);
-+			odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x404);
-+			odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33);
-+			odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404);
-+		} else {
-+			/*@Disable BB TxBF ant mapping register*/
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
-+			/*@1SS~2ss A, AB*/
-+			odm_set_bb_reg(dm, R_0x820, 0xff, 0x31);
-+			odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400);
-+		}
-+	}
-+#endif
-+#if (RTL8812F_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8812F) {
-+		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
-+			/*Path A ==================*/
-+			/*RF mode table write enable*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x1);
-+			/*Select RX mode*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, 0xF, 3);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, 0x3, 0x3);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0xfffff,
-+				       0x61AFE);
-+			/*RF mode table write disable*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x0);
-+
-+			/*Path B ==================*/
-+			/*RF mode table write enable*/
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x1);
-+			/*Select RX mode*/
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 3);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff,
-+				       0xD86BF);
-+			/*RF mode table write disable*/
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x0);
-+		}
-+
-+		/*@if Nsts > Nc, don't apply V matrix*/
-+		odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
-+
-+		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
-+			/*@enable BB TxBF ant mapping register*/
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
-+
-+			/* logic mapping */
-+			/* TX BF logic map and TX path en for Nsts = 1~2 */
-+			odm_set_bb_reg(dm, R_0x820, 0xff, 0x33);
-+			odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x404);
-+			odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33);
-+			odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404);
-+		} else {
-+			/*@Disable BB TxBF ant mapping register*/
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
-+			/*@1SS~2ss A, AB*/
-+			odm_set_bb_reg(dm, R_0x820, 0xff, 0x31);
-+			odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400);
-+		}
-+	}
-+#endif
-+#if (RTL8814B_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8814B) {
-+		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
-+			for (i = RF_PATH_A; i <= RF_PATH_D; i++) {
-+				/*RF mode table write enable*/
-+				odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
-+					       BIT(19), 0x1);
-+				/*Select RX mode*/
-+				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33,
-+					       0xF, 2);
-+				/*Set Table data*/
-+				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e,
-+					       0xfffff, 0x3fc);
-+				/*Set Table data*/
-+				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f,
-+					       0xfffff, 0x280f7);
-+				/*Select RX mode*/
-+				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33,
-+					       0xF, 3);
-+				/*Set Table data*/
-+				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e,
-+					       0xfffff, 0x365);
-+				/*Set Table data*/
-+				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f,
-+					       0xfffff, 0xafcf7);
-+				/*RF mode table write disable*/
-+				odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
-+					       BIT(19), 0x0);
-+			}
-+		}
-+		/*@if Nsts > Nc, don't apply V matrix*/
-+		odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
-+
-+		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
-+			/*@enable BB TxBF ant mapping register*/
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
-+
-+			/* logic mapping */
-+			/* TX BF logic map and TX path en for Nsts = 1~4 */
-+			//odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff);
-+			/*verification path-AC*/
-+			//odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4);
-+		} else {
-+			/*@Disable BB TxBF ant mapping register*/
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
-+			/*@1SS~4ss A, AB, ABC, ABCD*/
-+			//odm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731);
-+			//odm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400);
-+		}
-+	}
-+#endif
-+#if (RTL8198F_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8198F) {
-+		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
-+			for (i = RF_PATH_A; i <= RF_PATH_D; i++) {
-+				/*RF mode table write enable*/
-+				odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
-+					       BIT(19), 0x1);
-+				/*Select RX mode*/
-+				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x30,
-+					       0xfffff, 0x18000);
-+				/*Set Table data*/
-+				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x31,
-+					       0xfffff, 0x4f);
-+				/*Select RX mode*/
-+				odm_set_rf_reg(dm, (enum rf_path)i, RF_0x32,
-+					       0xfffff, 0x71fc0);
-+				/*RF mode table write disable*/
-+				odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef,
-+					       BIT(19), 0x0);
-+			}
-+		}
-+		/*@if Nsts > Nc, don't apply V matrix*/
-+		odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
-+
-+		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
-+			/*@enable BB TxBF ant mapping register*/
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
-+
-+			/* logic mapping */
-+			/* TX BF logic map and TX path en for Nsts = 1~4 */
-+			odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff);
-+			odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4);
-+		} else {
-+			/*@Disable BB TxBF ant mapping register*/
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
-+			/*@1SS~4ss A, AB, ABC, ABCD*/
-+			odm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731);
-+			odm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400);
-+		}
-+	}
-+#endif
-+#if (RTL8197G_SUPPORT)
-+	if (dm->support_ic_type == ODM_RTL8197G) {
-+		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
-+			/*Path A ==================*/
-+			/*RF mode table write enable*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x1);
-+			/*Set RF Rx mode table*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff,
-+				       0x18000);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff,
-+				       0x000cf);
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff,
-+				       0x71fc2);
-+			/*RF mode table write disable*/
-+			odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x0);
-+
-+			/*Path B ==================*/
-+			/*RF mode table write enable*/
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x1);
-+			/*Set RF Rx mode table*/
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff,
-+				       0x18000);
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff,
-+				       0x000cf);
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff,
-+				       0x71fc2);
-+			/*Set RF Standby mode table*/
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff,
-+				       0x18000);
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff,
-+				       0x000ef);
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff,
-+				       0x01042);
-+			/*RF mode table write disable*/
-+			odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x0);
-+		}
-+
-+		/*@if Nsts > Nc, don't apply V matrix*/
-+		odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
-+
-+		if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
-+			/*@enable BB TxBF ant mapping register*/
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
-+
-+			/* logic mapping */
-+			/* TX BF logic map and TX path en for Nsts = 1~2 */
-+			odm_set_bb_reg(dm, R_0x820, 0xff, 0x33);
-+			odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x404);
-+			odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33);
-+			odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404);
-+		} else {
-+			/*@Disable BB TxBF ant mapping register*/
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
-+			odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
-+			/*@1SS~2ss A, AB*/
-+			odm_set_bb_reg(dm, R_0x820, 0xff, 0x31);
-+			odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400);
-+		}
-+	}
-+#endif
-+}
-+
-+void phydm_mu_rsoml_reset(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s cnt reset\n", __func__);
-+
-+	odm_memory_set(dm, &rateinfo->num_mu_vht_pkt[0], 0, VHT_RATE_NUM * 2);
-+	odm_memory_set(dm, &rateinfo->num_qry_vht_pkt[0], 0, VHT_RATE_NUM * 2);
-+}
-+
-+void phydm_mu_rsoml_init(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;
-+	u32 val = 0;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s\n", __func__);
-+
-+	/*OFDM Tx*/
-+	val = odm_get_bb_reg(dm, R_0x820, MASKDWORD);
-+	rateinfo->tx_path_en_ofdm_2sts = (u8)((val & 0xf0) >> 4);
-+	rateinfo->tx_path_en_ofdm_1sts = (u8)(val & 0xf);
-+	/*OFDM Rx*/
-+	rateinfo->rx_path_en_ofdm = (u8)odm_get_bb_reg(dm, R_0x824, 0xf0000);
-+
-+	rateinfo->enable = 1;
-+	rateinfo->mu_ratio_th = 30;
-+	rateinfo->pre_mu_ratio = 0;
-+	rateinfo->mu_set_trxpath = 0;
-+	rateinfo->mu_been_iot = 0;
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s tx1ss=%d, tx2ss=%d, rx=%d\n",
-+		  __func__, rateinfo->tx_path_en_ofdm_1sts,
-+		  rateinfo->tx_path_en_ofdm_2sts, rateinfo->rx_path_en_ofdm);
-+
-+	phydm_mu_rsoml_reset(dm);
-+}
-+
-+void phydm_mu_rsoml_decision(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3;
-+	struct phydm_iot_center	*iot_table = &dm->iot_table;
-+	u8 offset = 0;
-+	u32 mu_ratio = 0;
-+	u32 su_pkt = 0;
-+	u32 mu_pkt = 0;
-+	u32 total_pkt = 0;
-+
-+	if (rateinfo->tx_path_en_ofdm_2sts != 3 ||
-+	    rateinfo->rx_path_en_ofdm != 3) {
-+		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] Init Not 2T2R 22CE\n");
-+		return;
-+	}
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML Decision eanble: %d\n",
-+		  rateinfo->enable);
-+
-+	if (!rateinfo->enable)
-+		return;
-+
-+	for (offset = 0; offset < VHT_RATE_NUM; offset++) {
-+		mu_pkt +=  rateinfo->num_mu_vht_pkt[offset];
-+		su_pkt +=  rateinfo->num_qry_vht_pkt[offset];
-+	}
-+	total_pkt = su_pkt + mu_pkt;
-+
-+	if (total_pkt == 0)
-+		mu_ratio = 0;
-+	else
-+		mu_ratio = (mu_pkt * 100) / total_pkt; // unit:%
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] MU rx ratio: %d, total pkt: %d\n",
-+		  mu_ratio, total_pkt);
-+
-+	if (mu_ratio > rateinfo->mu_ratio_th &&
-+	    rateinfo->pre_mu_ratio > rateinfo->mu_ratio_th) {
-+		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML status remain\n");
-+	} else if (mu_ratio <= rateinfo->mu_ratio_th &&
-+		 rateinfo->pre_mu_ratio <= rateinfo->mu_ratio_th) {
-+		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML status remain\n");
-+	} else if (mu_ratio > rateinfo->mu_ratio_th) {
-+		odm_set_bb_reg(dm, R_0xc00, BIT(26), 0);
-+		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML OFF\n");
-+	} else {
-+		odm_set_bb_reg(dm, R_0xc00, BIT(26), 1);
-+		PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML ON\n");
-+	}
-+
-+	PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] set_trxpath=%d, patch_10120200=%d\n",
-+		  rateinfo->mu_set_trxpath, iot_table->patch_id_10120200);
-+	if (rateinfo->mu_set_trxpath && iot_table->patch_id_10120200) {
-+		if (mu_ratio > rateinfo->mu_ratio_th) {
-+			phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_A,
-+					   BB_PATH_AUTO);
-+			PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT 2T1R\n");
-+			rateinfo->mu_been_iot = 1;
-+		} else {
-+			phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB,
-+					   BB_PATH_AUTO);
-+			PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT 2T2R\n");
-+			rateinfo->mu_been_iot = 0;
-+		}
-+	} else if (rateinfo->mu_been_iot == 1) {
-+		if (odm_get_bb_reg(dm, R_0x824, 0xf0000) == 1) {
-+			phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB,
-+					   BB_PATH_AUTO);
-+			PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT Restore\n");
-+			rateinfo->mu_been_iot = 0;
-+		}
-+	}
-+
-+	rateinfo->pre_mu_ratio = mu_ratio;
-+	phydm_mu_rsoml_reset(dm);
-+}
-+
-+
-+#if (RTL8814B_SUPPORT == 1)
-+void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	u8 i;
-+
-+	if (dm->rf_type == RF_1T1R)
-+		return;
-+
-+	if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
-+		for (i = RF_PATH_A; i <= RF_PATH_D; i += 3) {
-+			/*RF mode table write enable*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
-+				       0x1);
-+			/*Select RX mode*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 2);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,
-+				       0x3fc);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
-+				       0x280f7);
-+			/*Select RX mode*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,
-+				       0x365);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
-+				       0xafcf7);
-+			/*RF mode table write disable*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
-+				       0x0);
-+		}
-+		for (i = RF_PATH_B; i <= RF_PATH_C; i++) {
-+			/*RF mode table write enable*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
-+				       0x1);
-+			/*Select RX mode*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 2);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
-+				       0x280c7);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
-+				       0x280c7);
-+			/*Select RX mode*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff,
-+				       0x365);
-+			/*Set Table data*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff,
-+				       0xafcc7);
-+			/*RF mode table write disable*/
-+			odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19),
-+				       0x0);
-+		}
-+	}
-+	/*@if Nsts > Nc, don't apply V matrix*/
-+	odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1);
-+
-+	if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) {
-+		/*@enable BB TxBF ant mapping register*/
-+		odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2);
-+		odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1);
-+
-+		/* logic mapping */
-+		/* TX BF logic map and TX path en for Nsts = 1~2 */
-+		odm_set_bb_reg(dm, R_0x820, 0xff0000, 0x33); /*seg0*/
-+		odm_set_bb_reg(dm, R_0x824, 0xff00, 0xcc); /*seg1*/
-+		odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0xe4e4);
-+
-+	} else {
-+		/*@Disable BB TxBF ant mapping register*/
-+		odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0);
-+		odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0);
-+		/*@1SS~2ss A, AB*/
-+		odm_set_bb_reg(dm, R_0x820, 0xff, 0x31); /*seg0*/
-+		odm_set_bb_reg(dm, R_0x824, 0xff, 0xc8); /*seg1*/
-+		odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0xe420);
-+	}
-+}
-+#endif
-+#endif /*PHYSTS_3RD_TYPE_IC*/
-+
-+void phydm_txbf_avoid_hang(void *dm_void)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	
-+	/* avoid CCK CCA hang when the BF mode */
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT	
-+	odm_set_bb_reg(dm, R_0x1e6c, 0x100000, 0x1);
-+#endif
-+
-+	/* avoid CCK CCA hang when the BFee mode for 92F */
-+#if (RTL8192F_SUPPORT == 1)
-+	odm_set_bb_reg(dm, R_0xa70, 0xffff0000, 0x80ff);
-+#endif
-+}
-+
-+void phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output,
-+		    u32 *_out_len)
-+{
-+	struct dm_struct *dm = (struct dm_struct *)dm_void;
-+	char help[] = "-h";
-+	u32 var1[3] = {0};
-+	u32 i;
-+
-+	if ((strcmp(input[1], help) == 0)) {
-+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+			 "{BF ver1 :0}, {NO applyV:0; applyV:1; default:2}\n");
-+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+			 "{MU RSOML:1}, {MU enable:1/0}, {MU Ratio:40}\n");
-+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+			 "{MU TRxPath:2}, {TRxPath enable:1/0}\n");
-+		return;
-+	}
-+	for (i = 0; i < 3; i++) {
-+		PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
-+	}
-+	if (var1[0] == 0) {
-+		#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-+		#ifdef PHYDM_BEAMFORMING_SUPPORT
-+		struct _RT_BEAMFORMING_INFO *beamforming_info = NULL;
-+
-+		beamforming_info = &dm->beamforming_info;
-+
-+		if (var1[1] == 0) {
-+			beamforming_info->apply_v_matrix = false;
-+			beamforming_info->snding3ss = true;
-+			PDM_SNPF(*_out_len, *_used, output + *_used,
-+				 *_out_len - *_used,
-+				"\r\n dont apply V matrix and 3SS 789 snding\n");
-+		} else if (var1[1] == 1) {
-+			beamforming_info->apply_v_matrix = true;
-+			beamforming_info->snding3ss = true;
-+			PDM_SNPF(*_out_len, *_used, output + *_used,
-+				 *_out_len - *_used,
-+				 "\r\n apply V matrix and 3SS 789 snding\n");
-+		} else if (var1[1] == 2) {
-+			beamforming_info->apply_v_matrix = true;
-+			beamforming_info->snding3ss = false;
-+			PDM_SNPF(*_out_len, *_used, output + *_used,
-+				 *_out_len - *_used,
-+				 "\r\n default txbf setting\n");
-+		} else {
-+			PDM_SNPF(*_out_len, *_used, output + *_used,
-+				 *_out_len - *_used,
-+				 "\r\n unknown cmd!!\n");
-+		}
-+		#endif
-+		#endif
-+	} else if (var1[0] == 1) {
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		struct dm_struct *dm = (struct dm_struct *)dm_void;
-+		struct phydm_bf_rate_info_jgr3 *bfinfo = &dm->bf_rate_info_jgr3;
-+
-+		bfinfo->enable = (u8)var1[1];
-+		bfinfo->mu_ratio_th = (u8)var1[2];
-+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+			 "[MU RSOML] enable= %d, MU ratio TH= %d\n",
-+			 bfinfo->enable, bfinfo->mu_ratio_th);
-+		#endif
-+	} else if (var1[0] == 2) {
-+		#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+		struct dm_struct *dm = (struct dm_struct *)dm_void;
-+		struct phydm_bf_rate_info_jgr3 *bfinfo = &dm->bf_rate_info_jgr3;
-+
-+		bfinfo->mu_set_trxpath = (u8)var1[1];
-+		PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
-+			 "[MU TRxPath] mu_set_trxpath = %d\n",
-+			 bfinfo->mu_set_trxpath);
-+		#endif
-+	}
-+}
-+
-+#endif /*CONFIG_BB_TXBF_API*/
-diff --git a/drivers/staging/rtl8723cs/hal/phydm/txbf/phydm_hal_txbf_api.h b/drivers/staging/rtl8723cs/hal/phydm/txbf/phydm_hal_txbf_api.h
-new file mode 100644
-index 000000000000..15659ccb3ab8
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/phydm/txbf/phydm_hal_txbf_api.h
-@@ -0,0 +1,89 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017  Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * The full GNU General Public License is included in this distribution in the
-+ * file called LICENSE.
-+ *
-+ * Contact Information:
-+ * wlanfae <wlanfae@realtek.com>
-+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
-+ * Hsinchu 300, Taiwan.
-+ *
-+ * Larry Finger <Larry.Finger@lwfinger.net>
-+ *
-+ *****************************************************************************/
-+#ifndef __PHYDM_HAL_TXBF_API_H__
-+#define __PHYDM_HAL_TXBF_API_H__
-+
-+#if (defined(CONFIG_BB_TXBF_API))
-+
-+#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
-+#if defined(DM_ODM_CE_MAC80211)
-+#define tx_bf_nr(a, b) ({	\
-+	u8 __tx_bf_nr_a = (a);	\
-+	u8 __tx_bf_nr_b = (b);	\
-+	((__tx_bf_nr_a > __tx_bf_nr_b) ? (__tx_bf_nr_b) : (__tx_bf_nr_a)); })
-+#else
-+#define tx_bf_nr(a, b) ((a > b) ? (b) : (a))
-+#endif
-+
-+u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num);
-+
-+u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num);
-+
-+#endif
-+
-+#if (RTL8822B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\
-+	RTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8812F_SUPPORT == 1)
-+u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput,
-+				       u8 total_bfee_num, u8 *tx_rate);
-+u8 phydm_get_ndpa_rate(void *dm_void);
-+
-+u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput);
-+
-+#else
-+#define phydm_get_beamforming_sounding_info(dm, tp, bfee_num, rate) 0
-+#define phydm_get_ndpa_rate(dm)
-+#define phydm_get_mu_bfee_snding_decision(dm, tp)
-+
-+#endif
-+
-+#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
-+struct phydm_bf_rate_info_jgr3 {
-+	u8			enable;
-+	u8			mu_ratio_th;
-+	u32			pre_mu_ratio;
-+	u16			num_mu_vht_pkt[VHT_RATE_NUM];
-+	u16			num_qry_vht_pkt[VHT_RATE_NUM];
-+	boolean			mu_set_trxpath;
-+	u8			tx_path_en_ofdm_1sts;
-+	u8			tx_path_en_ofdm_2sts;
-+	u8			rx_path_en_ofdm;
-+	boolean			mu_been_iot;
-+};
-+
-+/*this function is only used for BFer*/
-+void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);
-+void phydm_txbf_avoid_hang(void *dm_void);
-+void phydm_mu_rsoml_init(void *dm_void);
-+void phydm_mu_rsoml_decision(void *dm_void);
-+
-+#if (RTL8814B_SUPPORT == 1)
-+void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt);
-+#endif
-+
-+#endif /*#PHYDM_IC_JGR3_SERIES_SUPPORT*/
-+void phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output,
-+		    u32 *_out_len);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/Hal8703BPwrSeq.c b/drivers/staging/rtl8723cs/hal/rtl8703b/Hal8703BPwrSeq.c
-new file mode 100644
-index 000000000000..0a3aeaf99e13
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/Hal8703BPwrSeq.c
-@@ -0,0 +1,84 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) Semiconductor - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+#include "Hal8703BPwrSeq.h"
-+
-+
-+/*
-+    drivers should parse below arrays and do the corresponding actions
-+*/
-+/* 3 Power on  Array */
-+WLAN_PWR_CFG rtl8703B_power_on_flow[RTL8703B_TRANS_CARDEMU_TO_ACT_STEPS + RTL8703B_TRANS_END_STEPS] = {
-+	RTL8703B_TRANS_CARDEMU_TO_ACT
-+	RTL8703B_TRANS_END
-+};
-+
-+/* 3Radio off GPIO Array */
-+WLAN_PWR_CFG rtl8703B_radio_off_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_END_STEPS] = {
-+	RTL8703B_TRANS_ACT_TO_CARDEMU
-+	RTL8703B_TRANS_END
-+};
-+
-+/* 3Card Disable Array */
-+WLAN_PWR_CFG rtl8703B_card_disable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS] = {
-+	RTL8703B_TRANS_ACT_TO_CARDEMU
-+	RTL8703B_TRANS_CARDEMU_TO_CARDDIS
-+	RTL8703B_TRANS_END
-+};
-+
-+/* 3 Card Enable Array */
-+WLAN_PWR_CFG rtl8703B_card_enable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS] = {
-+	RTL8703B_TRANS_CARDDIS_TO_CARDEMU
-+	RTL8703B_TRANS_CARDEMU_TO_ACT
-+	RTL8703B_TRANS_END
-+};
-+
-+/* 3Suspend Array */
-+WLAN_PWR_CFG rtl8703B_suspend_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8703B_TRANS_END_STEPS] = {
-+	RTL8703B_TRANS_ACT_TO_CARDEMU
-+	RTL8703B_TRANS_CARDEMU_TO_SUS
-+	RTL8703B_TRANS_END
-+};
-+
-+/* 3 Resume Array */
-+WLAN_PWR_CFG rtl8703B_resume_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8703B_TRANS_END_STEPS] = {
-+	RTL8703B_TRANS_SUS_TO_CARDEMU
-+	RTL8703B_TRANS_CARDEMU_TO_ACT
-+	RTL8703B_TRANS_END
-+};
-+
-+
-+
-+/* 3HWPDN Array */
-+WLAN_PWR_CFG rtl8703B_hwpdn_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS] = {
-+	RTL8703B_TRANS_ACT_TO_CARDEMU
-+	RTL8703B_TRANS_CARDEMU_TO_PDN
-+	RTL8703B_TRANS_END
-+};
-+
-+/* 3 Enter LPS */
-+WLAN_PWR_CFG rtl8703B_enter_lps_flow[RTL8703B_TRANS_ACT_TO_LPS_STEPS + RTL8703B_TRANS_END_STEPS] = {
-+	/* FW behavior */
-+	RTL8703B_TRANS_ACT_TO_LPS
-+	RTL8703B_TRANS_END
-+};
-+
-+/* 3 Leave LPS */
-+WLAN_PWR_CFG rtl8703B_leave_lps_flow[RTL8703B_TRANS_LPS_TO_ACT_STEPS + RTL8703B_TRANS_END_STEPS] = {
-+	/* FW behavior */
-+	RTL8703B_TRANS_LPS_TO_ACT
-+	RTL8703B_TRANS_END
-+};
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/hal8703b_fw.c b/drivers/staging/rtl8723cs/hal/rtl8703b/hal8703b_fw.c
-new file mode 100644
-index 000000000000..408250d57975
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/hal8703b_fw.c
-@@ -0,0 +1,7973 @@
-+/******************************************************************************
-+*
-+* Copyright(c) 2012 - 2017 Realtek Corporation.
-+*
-+* This program is free software; you can redistribute it and/or modify it
-+* under the terms of version 2 of the GNU General Public License as
-+* published by the Free Software Foundation.
-+*
-+* This program is distributed in the hope that it will be useful, but WITHOUT
-+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+* more details.
-+*
-+******************************************************************************/
-+
-+#ifdef CONFIG_RTL8703B
-+
-+#include "drv_types.h"
-+
-+#ifdef LOAD_FW_HEADER_FROM_DRIVER
-+
-+#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))
-+
-+u8 array_mp_8703b_fw_ap[] = {
-+0xB2, 0x03, 0x20, 0x00, 0x0B, 0x00, 0x00, 0x00,
-+0x06, 0x11, 0x10, 0x25, 0xFA, 0x4D, 0x02, 0x00,
-+0x25, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x02, 0x85, 0xB9, 0x02, 0xBB, 0x3A, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xA6, 0xBF, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xBB, 0xE6, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xBB, 0x3B, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xB6, 0xB3, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xBB, 0x93, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x02, 0x86, 0xD2, 0x02, 0x89, 0x0A, 0x02, 0x80,
-+0x86, 0x02, 0x80, 0x89, 0x02, 0x80, 0x8C, 0x02,
-+0x94, 0xE9, 0x02, 0x87, 0x72, 0x02, 0x80, 0x95,
-+0x02, 0x80, 0x98, 0x02, 0x80, 0x9B, 0x02, 0x80,
-+0x9E, 0x02, 0x80, 0xA1, 0x02, 0x80, 0xA4, 0x02,
-+0x80, 0xA7, 0x02, 0x80, 0xAA, 0x02, 0x80, 0xAD,
-+0x02, 0x80, 0xB0, 0x02, 0x8A, 0x7D, 0x02, 0x80,
-+0xB6, 0x02, 0x80, 0xB9, 0x02, 0x80, 0xBC, 0x02,
-+0x80, 0xBF, 0x02, 0x80, 0xC2, 0x02, 0x80, 0xC5,
-+0x02, 0x80, 0xC8, 0x02, 0x80, 0xCB, 0x02, 0x80,
-+0xCE, 0x02, 0x92, 0x78, 0x02, 0xCA, 0xBD, 0x02,
-+0x80, 0xD7, 0x02, 0x80, 0xDA, 0x02, 0x80, 0xDD,
-+0x02, 0x80, 0xE0, 0x02, 0x80, 0xE3, 0x02, 0x80,
-+0xE6, 0x02, 0x80, 0xE9, 0x02, 0x80, 0xEC, 0x00,
-+0x00, 0x00, 0x02, 0xCA, 0x06, 0x00, 0x00, 0x00,
-+0x02, 0x80, 0xF8, 0x02, 0x80, 0xFB, 0x02, 0x80,
-+0xFE, 0x02, 0x81, 0x01, 0x02, 0x81, 0x04, 0x02,
-+0x81, 0x07, 0x02, 0x81, 0x0A, 0x02, 0x81, 0x0D,
-+0x02, 0x81, 0x10, 0x02, 0x81, 0x13, 0x02, 0x81,
-+0x16, 0x02, 0x81, 0x19, 0x02, 0x81, 0x1C, 0x02,
-+0xC9, 0xAE, 0x02, 0x81, 0x22, 0x02, 0x81, 0x25,
-+0x02, 0x81, 0x28, 0x02, 0x81, 0x2B, 0x02, 0xAB,
-+0xF4, 0x02, 0x81, 0x31, 0x02, 0xA2, 0x7F, 0x02,
-+0xAB, 0x54, 0x02, 0xAA, 0xF2, 0x02, 0x90, 0xEA,
-+0x02, 0xC7, 0xBA, 0x02, 0x96, 0x47, 0x02, 0xCB,
-+0x80, 0x02, 0x81, 0x49, 0x02, 0x81, 0x4C, 0x02,
-+0x81, 0x4F, 0x02, 0x81, 0x52, 0x02, 0x81, 0x55,
-+0x02, 0x81, 0x58, 0x02, 0x81, 0x5B, 0x02, 0x90,
-+0xF5, 0x02, 0x81, 0x61, 0x02, 0x81, 0x64, 0x02,
-+0xCC, 0x99, 0x02, 0x81, 0x6A, 0x02, 0x81, 0x6D,
-+0x02, 0xBD, 0xCF, 0x02, 0xAB, 0xAC, 0x02, 0xCA,
-+0xB1, 0x02, 0xBF, 0x1F, 0x00, 0x00, 0x00, 0x00,
-+0x15, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x15,
-+0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x05, 0xF0,
-+0xFF, 0x0F, 0x00, 0x00, 0x00, 0x05, 0xF0, 0x0F,
-+0x00, 0x00, 0x00, 0x00, 0x10, 0xF0, 0xFF, 0x0F,
-+0x00, 0x00, 0x00, 0x10, 0xF0, 0x0F, 0x00, 0x00,
-+0x00, 0x00, 0xF5, 0x0F, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A,
-+0x08, 0x03, 0x03, 0x00, 0x04, 0x09, 0x07, 0x03,
-+0x03, 0x00, 0x04, 0x08, 0x06, 0x03, 0x02, 0x00,
-+0x04, 0x08, 0x05, 0x03, 0x01, 0x00, 0x04, 0x0D,
-+0x0A, 0x07, 0x05, 0x00, 0x08, 0x0C, 0x0A, 0x07,
-+0x04, 0x00, 0x08, 0x0B, 0x0A, 0x06, 0x05, 0x00,
-+0x08, 0x0B, 0x0A, 0x05, 0x03, 0x00, 0x08, 0x0B,
-+0x0A, 0x03, 0x02, 0x00, 0x08, 0x14, 0x12, 0x0C,
-+0x04, 0x00, 0x10, 0x14, 0x12, 0x09, 0x04, 0x00,
-+0x10, 0x24, 0x22, 0x1C, 0x12, 0x00, 0x20, 0x24,
-+0x22, 0x18, 0x0C, 0x00, 0x20, 0x24, 0x22, 0x14,
-+0x06, 0x00, 0x20, 0x24, 0x22, 0x0F, 0x04, 0x00,
-+0x20, 0x24, 0x21, 0x0A, 0x04, 0x00, 0x20, 0x23,
-+0x21, 0x0C, 0x04, 0x00, 0x20, 0x23, 0x1F, 0x0A,
-+0x04, 0x00, 0x20, 0x22, 0x1F, 0x0F, 0x04, 0x00,
-+0x20, 0x21, 0x1F, 0x16, 0x0C, 0x00, 0x20, 0x31,
-+0x2F, 0x20, 0x14, 0x00, 0x30, 0x31, 0x2F, 0x18,
-+0x10, 0x00, 0x30, 0x31, 0x2C, 0x18, 0x0C, 0x00,
-+0x30, 0x31, 0x2A, 0x14, 0x0C, 0x00, 0x30, 0x31,
-+0x28, 0x14, 0x00, 0x00, 0x30, 0x31, 0x24, 0x14,
-+0x00, 0x00, 0x30, 0x31, 0x1E, 0x14, 0x00, 0x00,
-+0x30, 0x04, 0x04, 0x04, 0x05, 0x08, 0x08, 0x09,
-+0x09, 0x0C, 0x0E, 0x10, 0x12, 0x06, 0x0B, 0x0D,
-+0x0E, 0x0F, 0x11, 0x12, 0x14, 0x00, 0x04, 0x00,
-+0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x23, 0x00,
-+0x2D, 0x00, 0x50, 0x00, 0x91, 0x00, 0xC3, 0x01,
-+0x27, 0x01, 0x31, 0x01, 0x5E, 0x00, 0xC8, 0x00,
-+0xF0, 0x00, 0xDC, 0x01, 0x5E, 0x01, 0x68, 0x01,
-+0x9A, 0x01, 0xCC, 0x01, 0xEA, 0x02, 0x02, 0x04,
-+0x08, 0x0C, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60,
-+0x6C, 0x14, 0x28, 0x32, 0x50, 0x78, 0xA0, 0xC8,
-+0xE6, 0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x02,
-+0x02, 0x03, 0x03, 0x04, 0x04, 0x02, 0x04, 0x06,
-+0x07, 0x07, 0x08, 0x08, 0x08, 0x01, 0x01, 0x01,
-+0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02,
-+0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02,
-+0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02,
-+0x02, 0x03, 0x03, 0x04, 0x05, 0x01, 0x02, 0x03,
-+0x04, 0x05, 0x06, 0x07, 0x08, 0x03, 0x03, 0x03,
-+0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x02, 0x02,
-+0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
-+0x02, 0x19, 0x06, 0x04, 0x02, 0x00, 0x18, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0xC2, 0xAF, 0x80, 0xFE, 0x32, 0x12, 0x83, 0x14,
-+0x85, 0xD0, 0x0B, 0x75, 0xD0, 0x08, 0xAA, 0xE0,
-+0xC2, 0x8C, 0xE5, 0x8A, 0x24, 0x67, 0xF5, 0x8A,
-+0xE5, 0x8C, 0x34, 0x79, 0xF5, 0x8C, 0xD2, 0x8C,
-+0xEC, 0x24, 0x87, 0xF8, 0xE6, 0xBC, 0x02, 0x02,
-+0x74, 0xFF, 0xC3, 0x95, 0x81, 0xB4, 0x40, 0x00,
-+0x40, 0xCE, 0x79, 0x03, 0x78, 0x80, 0x16, 0xE6,
-+0x08, 0x70, 0x0B, 0xC2, 0xAF, 0xE6, 0x30, 0xE1,
-+0x03, 0x44, 0x18, 0xF6, 0xD2, 0xAF, 0x08, 0xD9,
-+0xED, 0xEA, 0x8B, 0xD0, 0x22, 0xE5, 0x0C, 0xFF,
-+0x23, 0x24, 0x81, 0xF8, 0x0F, 0x08, 0x08, 0xBF,
-+0x03, 0x04, 0x7F, 0x00, 0x78, 0x81, 0xE6, 0x30,
-+0xE4, 0xF2, 0x00, 0xE5, 0x0C, 0xC3, 0x9F, 0x50,
-+0x20, 0x05, 0x0C, 0x74, 0x86, 0x25, 0x0C, 0xF8,
-+0xE6, 0xFD, 0xA6, 0x81, 0x08, 0xE6, 0xAE, 0x0C,
-+0xBE, 0x02, 0x02, 0x74, 0xFF, 0xCD, 0xF8, 0xE8,
-+0x6D, 0x60, 0xE0, 0x08, 0xE6, 0xC0, 0xE0, 0x80,
-+0xF6, 0xE5, 0x0C, 0xD3, 0x9F, 0x40, 0x27, 0xE5,
-+0x0C, 0x24, 0x87, 0xF8, 0xE6, 0xAE, 0x0C, 0xBE,
-+0x02, 0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xCD,
-+0xF8, 0xE5, 0x81, 0x6D, 0x60, 0x06, 0xD0, 0xE0,
-+0xF6, 0x18, 0x80, 0xF5, 0xE5, 0x0C, 0x24, 0x86,
-+0xC8, 0xF6, 0x15, 0x0C, 0x80, 0xD3, 0xE5, 0x0C,
-+0x23, 0x24, 0x81, 0xF8, 0x7F, 0x04, 0xC2, 0xAF,
-+0xE6, 0x30, 0xE0, 0x03, 0x10, 0xE2, 0x0C, 0x7F,
-+0x00, 0x30, 0xE1, 0x07, 0x30, 0xE3, 0x04, 0x7F,
-+0x08, 0x54, 0xF4, 0x54, 0x7C, 0xC6, 0xD2, 0xAF,
-+0x54, 0x80, 0x42, 0x07, 0x22, 0x78, 0x86, 0xA6,
-+0x81, 0x74, 0x02, 0x60, 0x06, 0xFF, 0x08, 0x76,
-+0xFF, 0xDF, 0xFB, 0x7F, 0x03, 0xE4, 0x78, 0x80,
-+0xF6, 0x08, 0xF6, 0x08, 0xDF, 0xFA, 0x78, 0x81,
-+0x76, 0x30, 0x90, 0x86, 0xCC, 0x74, 0x01, 0x93,
-+0xC0, 0xE0, 0xE4, 0x93, 0xC0, 0xE0, 0x43, 0x89,
-+0x01, 0x75, 0x8A, 0x60, 0x75, 0x8C, 0x79, 0xD2,
-+0x8C, 0xD2, 0xAF, 0x22, 0x02, 0xEF, 0xD3, 0x94,
-+0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0x74, 0x81,
-+0x2F, 0x2F, 0xF8, 0xE6, 0x20, 0xE5, 0xF4, 0xC2,
-+0xAF, 0xE6, 0x44, 0x30, 0xF6, 0xD2, 0xAF, 0xAE,
-+0x0C, 0xEE, 0xC3, 0x9F, 0x50, 0x21, 0x0E, 0x74,
-+0x86, 0x2E, 0xF8, 0xE6, 0xF9, 0x08, 0xE6, 0x18,
-+0xBE, 0x02, 0x02, 0x74, 0xFF, 0xFD, 0xED, 0x69,
-+0x60, 0x09, 0x09, 0xE7, 0x19, 0x19, 0xF7, 0x09,
-+0x09, 0x80, 0xF3, 0x16, 0x16, 0x80, 0xDA, 0xEE,
-+0xD3, 0x9F, 0x40, 0x04, 0x05, 0x81, 0x05, 0x81,
-+0xEE, 0xD3, 0x9F, 0x40, 0x22, 0x74, 0x86, 0x2E,
-+0xF8, 0x08, 0xE6, 0xF9, 0xEE, 0xB5, 0x0C, 0x02,
-+0xA9, 0x81, 0x18, 0x06, 0x06, 0xE6, 0xFD, 0xED,
-+0x69, 0x60, 0x09, 0x19, 0x19, 0xE7, 0x09, 0x09,
-+0xF7, 0x19, 0x80, 0xF3, 0x1E, 0x80, 0xD9, 0xEF,
-+0x24, 0x86, 0xF8, 0xE6, 0x04, 0xF8, 0xEF, 0x2F,
-+0x04, 0x90, 0x86, 0xCC, 0x93, 0xF6, 0x08, 0xEF,
-+0x2F, 0x93, 0xF6, 0x7F, 0x00, 0x22, 0xEF, 0xD3,
-+0x94, 0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0xEF,
-+0x23, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE5, 0xF4,
-+0xC2, 0xAF, 0xE6, 0x54, 0x8C, 0xF6, 0xD2, 0xAF,
-+0xE5, 0x0C, 0xB5, 0x07, 0x0A, 0x74, 0x86, 0x2F,
-+0xF8, 0xE6, 0xF5, 0x81, 0x02, 0x83, 0x5D, 0x50,
-+0x2E, 0x74, 0x87, 0x2F, 0xF8, 0xE6, 0xBF, 0x02,
-+0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xF9, 0x74,
-+0x86, 0x2F, 0xF8, 0xFB, 0xE6, 0xFC, 0xE9, 0x6C,
-+0x60, 0x08, 0xA8, 0x05, 0xE7, 0xF6, 0x1D, 0x19,
-+0x80, 0xF4, 0xA8, 0x03, 0xA6, 0x05, 0x1F, 0xE5,
-+0x0C, 0xB5, 0x07, 0xE3, 0x7F, 0x00, 0x22, 0x74,
-+0x87, 0x2F, 0xF8, 0xE6, 0xFD, 0x18, 0x86, 0x01,
-+0x0F, 0x74, 0x86, 0x2F, 0xF8, 0xA6, 0x01, 0x08,
-+0x86, 0x04, 0xE5, 0x0C, 0xB5, 0x07, 0x02, 0xAC,
-+0x81, 0xED, 0x6C, 0x60, 0x08, 0x0D, 0x09, 0xA8,
-+0x05, 0xE6, 0xF7, 0x80, 0xF4, 0xE5, 0x0C, 0xB5,
-+0x07, 0xDE, 0x89, 0x81, 0x7F, 0x00, 0x22, 0xEF,
-+0xD3, 0x94, 0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22,
-+0xEF, 0x23, 0x24, 0x81, 0xF8, 0xC2, 0xAF, 0xE6,
-+0x30, 0xE5, 0x05, 0x30, 0xE0, 0x02, 0xD2, 0xE4,
-+0xD2, 0xE2, 0xC6, 0xD2, 0xAF, 0x7F, 0x00, 0x30,
-+0xE2, 0x01, 0x0F, 0x02, 0x83, 0x5C, 0x8F, 0xF0,
-+0xE4, 0xFF, 0xFE, 0xE5, 0x0C, 0x23, 0x24, 0x80,
-+0xF8, 0xC2, 0xA9, 0x30, 0xF7, 0x0D, 0x7F, 0x08,
-+0xE6, 0x60, 0x0B, 0x2D, 0xF6, 0x60, 0x30, 0x50,
-+0x2E, 0x80, 0x07, 0x30, 0xF1, 0x06, 0xED, 0xF6,
-+0x60, 0x25, 0x7E, 0x02, 0x08, 0x30, 0xF0, 0x10,
-+0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x23, 0x0E, 0x30,
-+0xE2, 0x0C, 0xD2, 0xAF, 0x7F, 0x04, 0x80, 0x12,
-+0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x13, 0x54, 0xEC,
-+0x4E, 0xF6, 0xD2, 0xAF, 0x02, 0x83, 0x5D, 0x7F,
-+0x08, 0x08, 0xEF, 0x44, 0x83, 0xF4, 0xC2, 0xAF,
-+0x56, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x4F, 0xFF,
-+0x22, 0x02, 0x85, 0xF7, 0x02, 0x83, 0xED, 0xE4,
-+0x93, 0xA3, 0xF8, 0xE4, 0x93, 0xA3, 0x40, 0x03,
-+0xF6, 0x80, 0x01, 0xF2, 0x08, 0xDF, 0xF4, 0x80,
-+0x29, 0xE4, 0x93, 0xA3, 0xF8, 0x54, 0x07, 0x24,
-+0x0C, 0xC8, 0xC3, 0x33, 0xC4, 0x54, 0x0F, 0x44,
-+0x20, 0xC8, 0x83, 0x40, 0x04, 0xF4, 0x56, 0x80,
-+0x01, 0x46, 0xF6, 0xDF, 0xE4, 0x80, 0x0B, 0x01,
-+0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x90,
-+0x86, 0xB5, 0xE4, 0x7E, 0x01, 0x93, 0x60, 0xBC,
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-+0x03, 0xEB, 0x90, 0x06, 0xC7, 0xEF, 0xF0, 0x22,
-+0x90, 0x8F, 0xCB, 0x12, 0x04, 0xB2, 0x90, 0x06,
-+0xC4, 0xEF, 0xF0, 0x90, 0x8F, 0xCB, 0x12, 0x04,
-+0xB2, 0x78, 0x08, 0x12, 0x03, 0xEB, 0x90, 0x06,
-+0xC5, 0xEF, 0xF0, 0x90, 0x8F, 0xCB, 0x12, 0x04,
-+0xB2, 0x78, 0x10, 0x12, 0x03, 0xEB, 0x90, 0x06,
-+0xC6, 0xEF, 0xF0, 0x90, 0x8F, 0xCB, 0x02, 0x04,
-+0xB2, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0,
-+0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF,
-+0x01, 0xC3, 0xC0, 0xD0, 0x51, 0xE2, 0xF5, 0x83,
-+0xE0, 0x90, 0x91, 0x0D, 0xF0, 0xED, 0x90, 0x00,
-+0x73, 0x70, 0x06, 0xE0, 0x44, 0x04, 0xF0, 0x80,
-+0x04, 0xE0, 0x54, 0xFB, 0xF0, 0xD0, 0xD0, 0x92,
-+0xAF, 0x22, 0x90, 0x89, 0x7C, 0xA3, 0xE0, 0x24,
-+0x7F, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0x22, 0x90,
-+0x91, 0x7F, 0x12, 0x86, 0x86, 0x90, 0x91, 0x7B,
-+0x12, 0x86, 0x7D, 0x90, 0x91, 0x82, 0x12, 0x86,
-+0x86, 0x90, 0x91, 0x7E, 0xE0, 0x24, 0xFF, 0xFF,
-+0xE4, 0x34, 0xFF, 0xFE, 0x90, 0x91, 0x80, 0x8F,
-+0xF0, 0x12, 0x02, 0xE7, 0x90, 0x91, 0x83, 0xEE,
-+0x8F, 0xF0, 0x12, 0x02, 0xE7, 0x90, 0x91, 0x7E,
-+0xE0, 0xD3, 0x94, 0x00, 0x40, 0x2E, 0x90, 0x91,
-+0x82, 0x12, 0x86, 0x7D, 0x12, 0x02, 0x06, 0xFF,
-+0x90, 0x91, 0x7F, 0x12, 0x86, 0x7D, 0x12, 0x02,
-+0x06, 0xFE, 0x6F, 0x60, 0x05, 0xC3, 0xEE, 0x9F,
-+0xFF, 0x22, 0x90, 0x91, 0x80, 0x71, 0x57, 0x90,
-+0x91, 0x83, 0x71, 0x57, 0x90, 0x91, 0x7E, 0xE0,
-+0x14, 0xF0, 0x80, 0xC9, 0x7F, 0x00, 0x22, 0x74,
-+0xFF, 0xF5, 0xF0, 0x02, 0x02, 0xE7, 0x7D, 0x07,
-+0xEF, 0x5D, 0xC3, 0x60, 0x0A, 0x71, 0x73, 0x24,
-+0x08, 0xFF, 0xE4, 0x3E, 0xFE, 0x80, 0x03, 0x71,
-+0x73, 0xFF, 0x22, 0x74, 0xFF, 0x9D, 0xFD, 0x74,
-+0xFF, 0x94, 0x00, 0x5E, 0xFE, 0xED, 0x5F, 0x22,
-+0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90,
-+0x8A, 0xEA, 0xE0, 0x30, 0xE0, 0x1E, 0x90, 0x8A,
-+0xFC, 0xE0, 0x60, 0x05, 0x75, 0x0F, 0x40, 0x81,
-+0x2E, 0x90, 0x8A, 0x85, 0xE0, 0xD3, 0x94, 0x00,
-+0x40, 0x02, 0x80, 0x2D, 0x90, 0x8A, 0xE9, 0xE0,
-+0x60, 0x7B, 0x80, 0x55, 0x12, 0x79, 0x80, 0xEF,
-+0x64, 0x01, 0x60, 0x05, 0x75, 0x0F, 0x01, 0x80,
-+0x75, 0x90, 0x8A, 0x87, 0xE0, 0xFF, 0x54, 0x03,
-+0x60, 0x05, 0x75, 0x0F, 0x02, 0x80, 0x67, 0x90,
-+0x8A, 0x85, 0xE0, 0xFE, 0xE4, 0xC3, 0x9E, 0x50,
-+0x05, 0x75, 0x0F, 0x04, 0x80, 0x58, 0xEF, 0x30,
-+0xE2, 0x05, 0x75, 0x0F, 0x08, 0x80, 0x4F, 0x90,
-+0x8A, 0x87, 0xE0, 0x30, 0xE4, 0x05, 0x75, 0x0F,
-+0x10, 0x80, 0x43, 0x90, 0x8A, 0x7F, 0xE0, 0x13,
-+0x13, 0x54, 0x3F, 0x20, 0xE0, 0x05, 0x75, 0x0F,
-+0x20, 0x80, 0x33, 0x90, 0x8A, 0xE9, 0xE0, 0x60,
-+0x05, 0x75, 0x0F, 0x80, 0x80, 0x28, 0x90, 0x06,
-+0x62, 0xE0, 0x30, 0xE1, 0x05, 0x75, 0x0F, 0x11,
-+0x80, 0x1C, 0x90, 0x06, 0x62, 0xE0, 0x30, 0xE0,
-+0x0C, 0xE0, 0x54, 0xFC, 0xFF, 0xBF, 0x80, 0x05,
-+0x75, 0x0F, 0x12, 0x80, 0x09, 0x90, 0x01, 0xB8,
-+0xE4, 0xF0, 0x7F, 0x01, 0x80, 0x0E, 0x90, 0x01,
-+0xB9, 0x74, 0x04, 0xF0, 0x90, 0x01, 0xB8, 0xE5,
-+0x0F, 0xF0, 0x7F, 0x00, 0xD0, 0xD0, 0x92, 0xAF,
-+0x22, 0x90, 0x02, 0x87, 0xE0, 0x60, 0x02, 0x80,
-+0x08, 0x90, 0x01, 0x00, 0xE0, 0x64, 0x3F, 0x60,
-+0x05, 0x75, 0x63, 0x01, 0x80, 0x34, 0x90, 0x02,
-+0x96, 0xE0, 0x60, 0x05, 0x75, 0x63, 0x10, 0x80,
-+0x29, 0x90, 0x02, 0x86, 0xE0, 0x20, 0xE1, 0x02,
-+0x80, 0x07, 0x90, 0x02, 0x86, 0xE0, 0x30, 0xE3,
-+0x05, 0x75, 0x63, 0x04, 0x80, 0x14, 0x90, 0x8B,
-+0x33, 0xE0, 0x30, 0xE0, 0x05, 0x75, 0x63, 0x20,
-+0x80, 0x08, 0x90, 0x01, 0xB8, 0xE4, 0xF0, 0x7F,
-+0x01, 0x22, 0x90, 0x01, 0xB9, 0x74, 0x08, 0xF0,
-+0x90, 0x01, 0xB8, 0xE5, 0x63, 0xF0, 0x7F, 0x00,
-+0x22, 0xAC, 0x07, 0x90, 0x8A, 0x7F, 0x12, 0x87,
-+0xE4, 0x30, 0xE0, 0x02, 0xA1, 0x4B, 0x90, 0x8A,
-+0x7E, 0xE0, 0x30, 0xE0, 0x16, 0x90, 0x8A, 0xA0,
-+0xE0, 0x24, 0x04, 0x90, 0x8A, 0x98, 0xF0, 0x90,
-+0x8A, 0xA0, 0xE0, 0x24, 0x03, 0x90, 0x8A, 0x97,
-+0xF0, 0x80, 0x0D, 0x90, 0x8A, 0x98, 0x74, 0x02,
-+0xF0, 0x90, 0x8A, 0x97, 0x14, 0xF0, 0x0B, 0x0B,
-+0x90, 0x8A, 0x97, 0xE0, 0xFA, 0x90, 0x8A, 0x96,
-+0xE0, 0xD3, 0x9A, 0x50, 0x0D, 0x90, 0x8A, 0x8B,
-+0xEB, 0xF0, 0x90, 0x8A, 0x98, 0xE0, 0xC3, 0x9D,
-+0x80, 0x11, 0xC3, 0xED, 0x9A, 0x2B, 0x90, 0x8A,
-+0x8B, 0xF0, 0x90, 0x8A, 0x97, 0xE0, 0xFF, 0xA3,
-+0xE0, 0xC3, 0x9F, 0x2C, 0x90, 0x8A, 0x9B, 0xF0,
-+0x90, 0x8A, 0x98, 0xE0, 0xFF, 0x24, 0x0A, 0xFD,
-+0xE4, 0x33, 0xFC, 0x90, 0x8A, 0x9B, 0x12, 0xC7,
-+0xAF, 0x40, 0x04, 0xEF, 0x24, 0x0A, 0xF0, 0x90,
-+0x8A, 0x9B, 0xE0, 0xFF, 0x24, 0x23, 0xFD, 0xE4,
-+0x33, 0xFC, 0x90, 0x8A, 0x8B, 0x12, 0xC7, 0xAF,
-+0x40, 0x04, 0xEF, 0x24, 0x23, 0xF0, 0x90, 0x8A,
-+0x9B, 0xE0, 0xFF, 0x7E, 0x00, 0x90, 0x8A, 0x8F,
-+0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x05, 0x58,
-+0xE0, 0x6F, 0x70, 0x01, 0xE4, 0x60, 0x02, 0xB1,
-+0x5B, 0x80, 0x08, 0x90, 0x8A, 0x80, 0xE0, 0x44,
-+0x01, 0xF0, 0x22, 0x90, 0x8A, 0x80, 0xE0, 0x54,
-+0xFE, 0xF0, 0x22, 0x90, 0x8A, 0x8F, 0xA3, 0xE0,
-+0x90, 0x05, 0x58, 0xF0, 0x22, 0xD3, 0x10, 0xAF,
-+0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x8A, 0x80, 0xE0,
-+0xFE, 0xC3, 0x13, 0x30, 0xE0, 0x1F, 0x90, 0x91,
-+0x69, 0x74, 0x1E, 0xF0, 0x90, 0x91, 0x77, 0x74,
-+0x01, 0xF0, 0x90, 0x91, 0x6B, 0xEF, 0xF0, 0x7B,
-+0x01, 0x7A, 0x91, 0x79, 0x69, 0x12, 0x5A, 0x18,
-+0x7F, 0x04, 0x12, 0x87, 0x72, 0xD0, 0xD0, 0x92,
-+0xAF, 0x22, 0xE0, 0x54, 0xFE, 0x4E, 0xFE, 0xF0,
-+0xEF, 0x54, 0x02, 0xFF, 0xEE, 0x54, 0xFD, 0x4F,
-+0x22, 0xE0, 0x90, 0x01, 0xBA, 0xF0, 0x90, 0x8A,
-+0x85, 0xE0, 0x90, 0x01, 0xBB, 0x22, 0x74, 0x05,
-+0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83,
-+0x22, 0xE4, 0x90, 0x8E, 0xF6, 0xF0, 0x90, 0x8F,
-+0xAB, 0x22, 0x90, 0x91, 0x0E, 0xE0, 0xFF, 0x02,
-+0x59, 0x1B, 0x7D, 0x01, 0x7F, 0x02, 0x02, 0x7B,
-+0x53, 0x12, 0x7A, 0xA5, 0x90, 0x91, 0xAC, 0xE0,
-+0x22, 0x90, 0x90, 0x05, 0x74, 0x06, 0xF0, 0xA3,
-+0x22, 0xF0, 0x90, 0x00, 0x06, 0x02, 0x02, 0x1F,
-+0xF0, 0x90, 0x00, 0x05, 0x02, 0x02, 0x1F, 0x00,
-+0xD4, 0x96
-+};
-+
-+u32 array_length_mp_8703b_fw_ap = 19994;
-+
-+#endif /*defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))*/
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+
-+u8 array_mp_8703b_fw_nic[] = {
-+0xB2, 0x03, 0x10, 0x00, 0x0B, 0x00, 0x00, 0x00,
-+0x06, 0x11, 0x10, 0x24, 0x22, 0x4F, 0x02, 0x00,
-+0x25, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x02, 0x85, 0xB9, 0x02, 0xC4, 0x63, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xBD, 0xBE, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xC5, 0x2A, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xC4, 0x64, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xBA, 0xF7, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xC4, 0xD7, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x02, 0x86, 0xC5, 0x02, 0x8A, 0xF5, 0x02, 0x80,
-+0x86, 0x02, 0x80, 0x89, 0x02, 0x87, 0x28, 0x02,
-+0x8C, 0x48, 0x02, 0xB8, 0x63, 0x02, 0x80, 0x95,
-+0x02, 0x80, 0x98, 0x02, 0x80, 0x9B, 0x02, 0x80,
-+0x9E, 0x02, 0x80, 0xA1, 0x02, 0x80, 0xA4, 0x02,
-+0x80, 0xA7, 0x02, 0x80, 0xAA, 0x02, 0x80, 0xAD,
-+0x02, 0x80, 0xB0, 0x02, 0xA3, 0x0B, 0x02, 0x80,
-+0xB6, 0x02, 0x80, 0xB9, 0x02, 0x80, 0xBC, 0x02,
-+0x80, 0xBF, 0x02, 0x80, 0xC2, 0x02, 0x80, 0xC5,
-+0x02, 0x80, 0xC8, 0x02, 0x80, 0xCB, 0x02, 0x80,
-+0xCE, 0x02, 0x93, 0x7D, 0x02, 0xCA, 0x3B, 0x02,
-+0x80, 0xD7, 0x02, 0x80, 0xDA, 0x02, 0x80, 0xDD,
-+0x02, 0x80, 0xE0, 0x02, 0x80, 0xE3, 0x02, 0x80,
-+0xE6, 0x02, 0x80, 0xE9, 0x02, 0x80, 0xEC, 0x00,
-+0x00, 0x00, 0x02, 0xC9, 0x80, 0x00, 0x00, 0x00,
-+0x02, 0x80, 0xF8, 0x02, 0x80, 0xFB, 0x02, 0x80,
-+0xFE, 0x02, 0x81, 0x01, 0x02, 0x81, 0x04, 0x02,
-+0x81, 0x07, 0x02, 0x81, 0x0A, 0x02, 0x81, 0x0D,
-+0x02, 0x81, 0x10, 0x02, 0x81, 0x13, 0x02, 0x81,
-+0x16, 0x02, 0x81, 0x19, 0x02, 0x81, 0x1C, 0x02,
-+0xC6, 0xF4, 0x02, 0x81, 0x22, 0x02, 0x81, 0x25,
-+0x02, 0x81, 0x28, 0x02, 0x81, 0x2B, 0x02, 0x95,
-+0x93, 0x02, 0x81, 0x31, 0x02, 0xBA, 0x49, 0x02,
-+0xC3, 0x35, 0x02, 0xAD, 0x44, 0x02, 0xAB, 0x7B,
-+0x02, 0xC7, 0xD9, 0x02, 0x8D, 0xA8, 0x02, 0xCB,
-+0x05, 0x02, 0x81, 0x49, 0x02, 0x81, 0x4C, 0x02,
-+0x81, 0x4F, 0x02, 0x81, 0x52, 0x02, 0x81, 0x55,
-+0x02, 0x81, 0x58, 0x02, 0x81, 0x5B, 0x02, 0xAA,
-+0xB5, 0x02, 0x81, 0x61, 0x02, 0x81, 0x64, 0x02,
-+0xCC, 0x24, 0x02, 0x81, 0x6A, 0x02, 0x81, 0x6D,
-+0x02, 0xAC, 0x94, 0x02, 0xC3, 0x93, 0x02, 0xCA,
-+0x2F, 0x02, 0x9E, 0xBD, 0x00, 0x00, 0x00, 0x00,
-+0x15, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x15,
-+0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x05, 0xF0,
-+0xFF, 0x0F, 0x00, 0x00, 0x00, 0x05, 0xF0, 0x0F,
-+0x00, 0x00, 0x00, 0x00, 0x10, 0xF0, 0xFF, 0x0F,
-+0x00, 0x00, 0x00, 0x10, 0xF0, 0x0F, 0x00, 0x00,
-+0x00, 0x00, 0xF5, 0x0F, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A,
-+0x08, 0x03, 0x03, 0x00, 0x04, 0x09, 0x07, 0x03,
-+0x03, 0x00, 0x04, 0x08, 0x06, 0x03, 0x02, 0x00,
-+0x04, 0x08, 0x05, 0x03, 0x01, 0x00, 0x04, 0x0D,
-+0x0A, 0x07, 0x05, 0x00, 0x08, 0x0C, 0x0A, 0x07,
-+0x04, 0x00, 0x08, 0x0B, 0x0A, 0x06, 0x05, 0x00,
-+0x08, 0x0B, 0x0A, 0x05, 0x03, 0x00, 0x08, 0x0B,
-+0x0A, 0x03, 0x02, 0x00, 0x08, 0x14, 0x12, 0x0C,
-+0x04, 0x00, 0x10, 0x14, 0x12, 0x09, 0x04, 0x00,
-+0x10, 0x24, 0x22, 0x1C, 0x12, 0x00, 0x20, 0x24,
-+0x22, 0x18, 0x0C, 0x00, 0x20, 0x24, 0x22, 0x14,
-+0x06, 0x00, 0x20, 0x24, 0x22, 0x0F, 0x04, 0x00,
-+0x20, 0x24, 0x21, 0x0A, 0x04, 0x00, 0x20, 0x23,
-+0x21, 0x0C, 0x04, 0x00, 0x20, 0x23, 0x1F, 0x0A,
-+0x04, 0x00, 0x20, 0x22, 0x1F, 0x0F, 0x04, 0x00,
-+0x20, 0x21, 0x1F, 0x16, 0x0C, 0x00, 0x20, 0x31,
-+0x2F, 0x20, 0x14, 0x00, 0x30, 0x31, 0x2F, 0x18,
-+0x10, 0x00, 0x30, 0x31, 0x2C, 0x18, 0x0C, 0x00,
-+0x30, 0x31, 0x2A, 0x14, 0x0C, 0x00, 0x30, 0x31,
-+0x28, 0x14, 0x00, 0x00, 0x30, 0x31, 0x24, 0x14,
-+0x00, 0x00, 0x30, 0x31, 0x1E, 0x14, 0x00, 0x00,
-+0x30, 0x04, 0x04, 0x04, 0x05, 0x08, 0x08, 0x09,
-+0x09, 0x0C, 0x0E, 0x10, 0x12, 0x06, 0x0B, 0x0D,
-+0x0E, 0x0F, 0x11, 0x12, 0x14, 0x00, 0x04, 0x00,
-+0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x23, 0x00,
-+0x2D, 0x00, 0x50, 0x00, 0x91, 0x00, 0xC3, 0x01,
-+0x27, 0x01, 0x31, 0x01, 0x5E, 0x00, 0xC8, 0x00,
-+0xF0, 0x00, 0xDC, 0x01, 0x5E, 0x01, 0x68, 0x01,
-+0x9A, 0x01, 0xCC, 0x01, 0xEA, 0x02, 0x02, 0x04,
-+0x08, 0x0C, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60,
-+0x6C, 0x14, 0x28, 0x32, 0x50, 0x78, 0xA0, 0xC8,
-+0xE6, 0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x02,
-+0x02, 0x03, 0x03, 0x04, 0x04, 0x02, 0x04, 0x06,
-+0x07, 0x07, 0x08, 0x08, 0x08, 0x01, 0x01, 0x01,
-+0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02,
-+0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02,
-+0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02,
-+0x02, 0x03, 0x03, 0x04, 0x05, 0x01, 0x02, 0x03,
-+0x04, 0x05, 0x06, 0x07, 0x08, 0x03, 0x03, 0x03,
-+0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x02, 0x02,
-+0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
-+0x02, 0x19, 0x06, 0x04, 0x02, 0x00, 0x18, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0xC2, 0xAF, 0x80, 0xFE, 0x32, 0x12, 0x83, 0x14,
-+0x85, 0xD0, 0x0B, 0x75, 0xD0, 0x08, 0xAA, 0xE0,
-+0xC2, 0x8C, 0xE5, 0x8A, 0x24, 0x67, 0xF5, 0x8A,
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-+0x24, 0xC3, 0xF5, 0x82, 0xE4, 0x34, 0x8D, 0x22,
-+0x90, 0x8F, 0x84, 0xE0, 0x14, 0x90, 0x8F, 0x86,
-+0xF0, 0x22, 0xF0, 0x90, 0x8A, 0xEA, 0xE0, 0xC4,
-+0x13, 0x54, 0x07, 0x22, 0x90, 0x00, 0x04, 0x02,
-+0x03, 0x3E, 0x90, 0x8F, 0x85, 0xE0, 0x90, 0x05,
-+0x73, 0xF0, 0x22, 0x90, 0x8A, 0xEE, 0xE0, 0xC4,
-+0x13, 0x54, 0x07, 0x22, 0xFF, 0x12, 0x02, 0x06,
-+0x54, 0x0F, 0xFD, 0x22, 0x7D, 0x02, 0x7F, 0x02,
-+0x02, 0x7B, 0x53, 0xE0, 0x54, 0x03, 0x90, 0x8E,
-+0xA6, 0xF0, 0x22, 0x90, 0x8A, 0x89, 0xE0, 0x90,
-+0x05, 0x73, 0x22, 0x90, 0x8A, 0x87, 0xE0, 0x44,
-+0x10, 0xF0, 0x22, 0x12, 0x86, 0x71, 0xD3, 0x02,
-+0x03, 0xDA, 0x7D, 0x20, 0xE4, 0xFF, 0x02, 0x7A,
-+0xEE, 0x7D, 0x01, 0xAF, 0x65, 0x02, 0x63, 0xA2,
-+0xE5, 0x67, 0x90, 0x82, 0x9D, 0x93, 0xFF, 0x22,
-+0xF5, 0x82, 0xE4, 0x34, 0x90, 0xF5, 0x83, 0x22,
-+0x90, 0x90, 0x55, 0xE0, 0xFE, 0xA3, 0xE0, 0x22,
-+0x90, 0x8A, 0x7E, 0xE0, 0x54, 0xF7, 0xF0, 0x22,
-+0x90, 0x90, 0x05, 0x74, 0x06, 0xF0, 0xA3, 0x22,
-+0xFF, 0x12, 0x02, 0x06, 0xFE, 0x54, 0x0F, 0x22,
-+0x12, 0x02, 0x06, 0xC4, 0x54, 0x0F, 0xFF, 0x22,
-+0x73, 0xD3
-+};
-+
-+u32 array_length_mp_8703b_fw_nic = 20290;
-+
-+#ifdef CONFIG_WOWLAN
-+
-+u8 array_mp_8703b_fw_wowlan[] = {
-+0xB2, 0x03, 0x30, 0x00, 0x0B, 0x00, 0x00, 0x00,
-+0x06, 0x11, 0x10, 0x25, 0x02, 0x5A, 0x02, 0x00,
-+0x25, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x02, 0x86, 0x9E, 0x02, 0xB7, 0xF3, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xAD, 0x8A, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xBF, 0xEA, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xB7, 0xF4, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xB8, 0x44, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x02, 0xBF, 0xE9, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x02, 0x87, 0x35, 0x02, 0x8A, 0xB4, 0x02, 0x80,
-+0x86, 0x02, 0x80, 0x89, 0x02, 0x80, 0x8C, 0x02,
-+0xA9, 0xB1, 0x02, 0xAF, 0x7F, 0x02, 0x80, 0x95,
-+0x02, 0x80, 0x98, 0x02, 0x80, 0x9B, 0x02, 0x80,
-+0x9E, 0x02, 0x80, 0xA1, 0x02, 0x80, 0xA4, 0x02,
-+0x80, 0xA7, 0x02, 0x80, 0xAA, 0x02, 0x80, 0xAD,
-+0x02, 0x80, 0xB0, 0x02, 0x80, 0xB3, 0x02, 0x80,
-+0xB6, 0x02, 0x80, 0xB9, 0x02, 0x80, 0xBC, 0x02,
-+0x80, 0xBF, 0x02, 0x80, 0xC2, 0x02, 0x80, 0xC5,
-+0x02, 0x80, 0xC8, 0x02, 0x80, 0xCB, 0x02, 0x80,
-+0xCE, 0x02, 0x80, 0xD1, 0x02, 0xC7, 0xAA, 0x02,
-+0x80, 0xD7, 0x02, 0x80, 0xDA, 0x02, 0x80, 0xDD,
-+0x02, 0x80, 0xE0, 0x02, 0x80, 0xE3, 0x02, 0x80,
-+0xE6, 0x02, 0x80, 0xE9, 0x02, 0x80, 0xEC, 0x00,
-+0x00, 0x00, 0x02, 0x80, 0xF2, 0x00, 0x00, 0x00,
-+0x02, 0x80, 0xF8, 0x02, 0x80, 0xFB, 0x02, 0x80,
-+0xFE, 0x02, 0x81, 0x01, 0x02, 0x81, 0x04, 0x02,
-+0x81, 0x07, 0x02, 0x81, 0x0A, 0x02, 0x81, 0x0D,
-+0x02, 0x81, 0x10, 0x02, 0x81, 0x13, 0x02, 0x81,
-+0x16, 0x02, 0x81, 0x19, 0x02, 0x81, 0x1C, 0x02,
-+0x81, 0x1F, 0x02, 0x81, 0x22, 0x02, 0x81, 0x25,
-+0x02, 0x81, 0x28, 0x02, 0x81, 0x2B, 0x02, 0x81,
-+0x2E, 0x02, 0x81, 0x31, 0x02, 0xBD, 0x6B, 0x02,
-+0xBD, 0xB0, 0x02, 0x97, 0x28, 0x02, 0x90, 0xE6,
-+0x02, 0x81, 0x40, 0x02, 0xAB, 0x0E, 0x02, 0xD7,
-+0x4A, 0x02, 0x81, 0x49, 0x02, 0x81, 0x4C, 0x02,
-+0x81, 0x4F, 0x02, 0x81, 0x52, 0x02, 0x81, 0x55,
-+0x02, 0x81, 0x58, 0x02, 0x81, 0x5B, 0x02, 0x91,
-+0x00, 0x02, 0x81, 0x61, 0x02, 0x81, 0x64, 0x02,
-+0xC2, 0x0A, 0x02, 0x81, 0x6A, 0x02, 0x81, 0x6D,
-+0x02, 0xC3, 0xD3, 0x02, 0x81, 0x73, 0x02, 0x81,
-+0x76, 0x02, 0x81, 0x79, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF,
-+0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+0xC2, 0xAF, 0x80, 0xFE, 0x32, 0x12, 0x81, 0xE4,
-+0x85, 0xD0, 0x0B, 0x75, 0xD0, 0x08, 0xAA, 0xE0,
-+0xC2, 0x8C, 0xE5, 0x8A, 0x24, 0x67, 0xF5, 0x8A,
-+0xE5, 0x8C, 0x34, 0x79, 0xF5, 0x8C, 0xD2, 0x8C,
-+0xEC, 0x24, 0x87, 0xF8, 0xE6, 0xBC, 0x02, 0x02,
-+0x74, 0xFF, 0xC3, 0x95, 0x81, 0xB4, 0x40, 0x00,
-+0x40, 0xCE, 0x79, 0x03, 0x78, 0x80, 0x16, 0xE6,
-+0x08, 0x70, 0x0B, 0xC2, 0xAF, 0xE6, 0x30, 0xE1,
-+0x03, 0x44, 0x18, 0xF6, 0xD2, 0xAF, 0x08, 0xD9,
-+0xED, 0xEA, 0x8B, 0xD0, 0x22, 0xE5, 0x0C, 0xFF,
-+0x23, 0x24, 0x81, 0xF8, 0x0F, 0x08, 0x08, 0xBF,
-+0x03, 0x04, 0x7F, 0x00, 0x78, 0x81, 0xE6, 0x30,
-+0xE4, 0xF2, 0x00, 0xE5, 0x0C, 0xC3, 0x9F, 0x50,
-+0x20, 0x05, 0x0C, 0x74, 0x86, 0x25, 0x0C, 0xF8,
-+0xE6, 0xFD, 0xA6, 0x81, 0x08, 0xE6, 0xAE, 0x0C,
-+0xBE, 0x02, 0x02, 0x74, 0xFF, 0xCD, 0xF8, 0xE8,
-+0x6D, 0x60, 0xE0, 0x08, 0xE6, 0xC0, 0xE0, 0x80,
-+0xF6, 0xE5, 0x0C, 0xD3, 0x9F, 0x40, 0x27, 0xE5,
-+0x0C, 0x24, 0x87, 0xF8, 0xE6, 0xAE, 0x0C, 0xBE,
-+0x02, 0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xCD,
-+0xF8, 0xE5, 0x81, 0x6D, 0x60, 0x06, 0xD0, 0xE0,
-+0xF6, 0x18, 0x80, 0xF5, 0xE5, 0x0C, 0x24, 0x86,
-+0xC8, 0xF6, 0x15, 0x0C, 0x80, 0xD3, 0xE5, 0x0C,
-+0x23, 0x24, 0x81, 0xF8, 0x7F, 0x04, 0xC2, 0xAF,
-+0xE6, 0x30, 0xE0, 0x03, 0x10, 0xE2, 0x0C, 0x7F,
-+0x00, 0x30, 0xE1, 0x07, 0x30, 0xE3, 0x04, 0x7F,
-+0x08, 0x54, 0xF4, 0x54, 0x7C, 0xC6, 0xD2, 0xAF,
-+0x54, 0x80, 0x42, 0x07, 0x22, 0x78, 0x86, 0xA6,
-+0x81, 0x74, 0x02, 0x60, 0x06, 0xFF, 0x08, 0x76,
-+0xFF, 0xDF, 0xFB, 0x7F, 0x03, 0xE4, 0x78, 0x80,
-+0xF6, 0x08, 0xF6, 0x08, 0xDF, 0xFA, 0x78, 0x81,
-+0x76, 0x30, 0x90, 0x87, 0x2A, 0x74, 0x01, 0x93,
-+0xC0, 0xE0, 0xE4, 0x93, 0xC0, 0xE0, 0x43, 0x89,
-+0x01, 0x75, 0x8A, 0x60, 0x75, 0x8C, 0x79, 0xD2,
-+0x8C, 0xD2, 0xAF, 0x22, 0x02, 0xEF, 0xD3, 0x94,
-+0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0x74, 0x81,
-+0x2F, 0x2F, 0xF8, 0xE6, 0x20, 0xE5, 0xF4, 0xC2,
-+0xAF, 0xE6, 0x44, 0x30, 0xF6, 0xD2, 0xAF, 0xAE,
-+0x0C, 0xEE, 0xC3, 0x9F, 0x50, 0x21, 0x0E, 0x74,
-+0x86, 0x2E, 0xF8, 0xE6, 0xF9, 0x08, 0xE6, 0x18,
-+0xBE, 0x02, 0x02, 0x74, 0xFF, 0xFD, 0xED, 0x69,
-+0x60, 0x09, 0x09, 0xE7, 0x19, 0x19, 0xF7, 0x09,
-+0x09, 0x80, 0xF3, 0x16, 0x16, 0x80, 0xDA, 0xEE,
-+0xD3, 0x9F, 0x40, 0x04, 0x05, 0x81, 0x05, 0x81,
-+0xEE, 0xD3, 0x9F, 0x40, 0x22, 0x74, 0x86, 0x2E,
-+0xF8, 0x08, 0xE6, 0xF9, 0xEE, 0xB5, 0x0C, 0x02,
-+0xA9, 0x81, 0x18, 0x06, 0x06, 0xE6, 0xFD, 0xED,
-+0x69, 0x60, 0x09, 0x19, 0x19, 0xE7, 0x09, 0x09,
-+0xF7, 0x19, 0x80, 0xF3, 0x1E, 0x80, 0xD9, 0xEF,
-+0x24, 0x86, 0xF8, 0xE6, 0x04, 0xF8, 0xEF, 0x2F,
-+0x04, 0x90, 0x87, 0x2A, 0x93, 0xF6, 0x08, 0xEF,
-+0x2F, 0x93, 0xF6, 0x7F, 0x00, 0x22, 0xEF, 0xD3,
-+0x94, 0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0xEF,
-+0x23, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE5, 0xF4,
-+0xC2, 0xAF, 0xE6, 0x54, 0x8C, 0xF6, 0xD2, 0xAF,
-+0xE5, 0x0C, 0xB5, 0x07, 0x0A, 0x74, 0x86, 0x2F,
-+0xF8, 0xE6, 0xF5, 0x81, 0x02, 0x82, 0x2D, 0x50,
-+0x2E, 0x74, 0x87, 0x2F, 0xF8, 0xE6, 0xBF, 0x02,
-+0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xF9, 0x74,
-+0x86, 0x2F, 0xF8, 0xFB, 0xE6, 0xFC, 0xE9, 0x6C,
-+0x60, 0x08, 0xA8, 0x05, 0xE7, 0xF6, 0x1D, 0x19,
-+0x80, 0xF4, 0xA8, 0x03, 0xA6, 0x05, 0x1F, 0xE5,
-+0x0C, 0xB5, 0x07, 0xE3, 0x7F, 0x00, 0x22, 0x74,
-+0x87, 0x2F, 0xF8, 0xE6, 0xFD, 0x18, 0x86, 0x01,
-+0x0F, 0x74, 0x86, 0x2F, 0xF8, 0xA6, 0x01, 0x08,
-+0x86, 0x04, 0xE5, 0x0C, 0xB5, 0x07, 0x02, 0xAC,
-+0x81, 0xED, 0x6C, 0x60, 0x08, 0x0D, 0x09, 0xA8,
-+0x05, 0xE6, 0xF7, 0x80, 0xF4, 0xE5, 0x0C, 0xB5,
-+0x07, 0xDE, 0x89, 0x81, 0x7F, 0x00, 0x22, 0xEF,
-+0xD3, 0x94, 0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22,
-+0xEF, 0x23, 0x24, 0x81, 0xF8, 0xC2, 0xAF, 0xE6,
-+0x30, 0xE5, 0x05, 0x30, 0xE0, 0x02, 0xD2, 0xE4,
-+0xD2, 0xE2, 0xC6, 0xD2, 0xAF, 0x7F, 0x00, 0x30,
-+0xE2, 0x01, 0x0F, 0x02, 0x82, 0x2C, 0x8F, 0xF0,
-+0xE4, 0xFF, 0xFE, 0xE5, 0x0C, 0x23, 0x24, 0x80,
-+0xF8, 0xC2, 0xA9, 0x30, 0xF7, 0x0D, 0x7F, 0x08,
-+0xE6, 0x60, 0x0B, 0x2D, 0xF6, 0x60, 0x30, 0x50,
-+0x2E, 0x80, 0x07, 0x30, 0xF1, 0x06, 0xED, 0xF6,
-+0x60, 0x25, 0x7E, 0x02, 0x08, 0x30, 0xF0, 0x10,
-+0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x23, 0x0E, 0x30,
-+0xE2, 0x0C, 0xD2, 0xAF, 0x7F, 0x04, 0x80, 0x12,
-+0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x13, 0x54, 0xEC,
-+0x4E, 0xF6, 0xD2, 0xAF, 0x02, 0x82, 0x2D, 0x7F,
-+0x08, 0x08, 0xEF, 0x44, 0x83, 0xF4, 0xC2, 0xAF,
-+0x56, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x4F, 0xFF,
-+0x22, 0xEF, 0x2B, 0xFF, 0xEE, 0x3A, 0xFE, 0xED,
-+0x39, 0xFD, 0xEC, 0x38, 0xFC, 0x22, 0xEF, 0x5B,
-+0xFF, 0xEE, 0x5A, 0xFE, 0xED, 0x59, 0xFD, 0xEC,
-+0x58, 0xFC, 0x22, 0xEF, 0x4B, 0xFF, 0xEE, 0x4A,
-+0xFE, 0xED, 0x49, 0xFD, 0xEC, 0x48, 0xFC, 0x22,
-+0xE0, 0xF8, 0xA3, 0xE0, 0xF9, 0xA3, 0xE0, 0xFA,
-+0xA3, 0xE0, 0xFB, 0x22, 0xE0, 0xFB, 0xA3, 0xE0,
-+0xFA, 0xA3, 0xE0, 0xF9, 0x22, 0xEB, 0xF0, 0xA3,
-+0xEA, 0xF0, 0xA3, 0xE9, 0xF0, 0x22, 0xD0, 0x83,
-+0xD0, 0x82, 0xF8, 0xE4, 0x93, 0x70, 0x12, 0x74,
-+0x01, 0x93, 0x70, 0x0D, 0xA3, 0xA3, 0x93, 0xF8,
-+0x74, 0x01, 0x93, 0xF5, 0x82, 0x88, 0x83, 0xE4,
-+0x73, 0x74, 0x02, 0x93, 0x68, 0x60, 0xEF, 0xA3,
-+0xA3, 0xA3, 0x80, 0xDF, 0xE3, 0xF5, 0xF0, 0x09,
-+0xE2, 0x08, 0xB5, 0xF0, 0x6B, 0xDF, 0xF5, 0x80,
-+0x67, 0xE3, 0xF5, 0xF0, 0x09, 0xE6, 0x08, 0xB5,
-+0xF0, 0x5E, 0xDF, 0xF5, 0x80, 0x5A, 0x87, 0xF0,
-+0x09, 0xE6, 0x08, 0xB5, 0xF0, 0x52, 0xDF, 0xF6,
-+0x80, 0x4E, 0x87, 0xF0, 0x09, 0xE2, 0x08, 0xB5,
-+0xF0, 0x46, 0xDF, 0xF6, 0x80, 0x42, 0x88, 0x82,
-+0x8C, 0x83, 0x87, 0xF0, 0x09, 0xE0, 0xA3, 0xB5,
-+0xF0, 0x36, 0xDF, 0xF6, 0x80, 0x32, 0x88, 0x82,
-+0x8C, 0x83, 0x87, 0xF0, 0x09, 0xE4, 0x93, 0xA3,
-+0xB5, 0xF0, 0x25, 0xDF, 0xF5, 0x80, 0x21, 0x88,
-+0x82, 0x8C, 0x83, 0xE3, 0xF5, 0xF0, 0x09, 0xE0,
-+0xA3, 0xB5, 0xF0, 0x14, 0xDF, 0xF5, 0x80, 0x10,
-+0x88, 0x82, 0x8C, 0x83, 0xE3, 0xF5, 0xF0, 0x09,
-+0xE4, 0x93, 0xA3, 0xB5, 0xF0, 0x02, 0xDF, 0xF4,
-+0x02, 0x86, 0x23, 0x80, 0x87, 0x80, 0xE9, 0x80,
-+0x90, 0x80, 0xD4, 0x80, 0x3E, 0x80, 0x15, 0x80,
-+0x6E, 0x80, 0x7E, 0x80, 0x9D, 0x80, 0xB7, 0x80,
-+0x8D, 0x80, 0xA3, 0x80, 0x51, 0x80, 0x74, 0x80,
-+0x3C, 0x02, 0x86, 0x2F, 0x89, 0x82, 0x8A, 0x83,
-+0xEC, 0xFA, 0xE4, 0x93, 0xF5, 0xF0, 0xA3, 0xC8,
-+0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xE4,
-+0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5,
-+0x83, 0xCC, 0xB5, 0xF0, 0x76, 0xDF, 0xE3, 0xDE,
-+0xE1, 0x80, 0x70, 0x89, 0x82, 0x8A, 0x83, 0xE4,
-+0x93, 0xF5, 0xF0, 0xA3, 0xE2, 0x08, 0xB5, 0xF0,
-+0x62, 0xDF, 0xF4, 0x80, 0x5E, 0x89, 0x82, 0x8A,
-+0x83, 0xE0, 0xF5, 0xF0, 0xA3, 0xE6, 0x08, 0xB5,
-+0xF0, 0x51, 0xDF, 0xF5, 0x80, 0x4D, 0x89, 0x82,
-+0x8A, 0x83, 0xE0, 0xF5, 0xF0, 0xA3, 0xE2, 0x08,
-+0xB5, 0xF0, 0x40, 0xDF, 0xF5, 0x80, 0x3C, 0x89,
-+0x82, 0x8A, 0x83, 0xE4, 0x93, 0xF5, 0xF0, 0xA3,
-+0xE6, 0x08, 0xB5, 0xF0, 0x2E, 0xDF, 0xF4, 0x80,
-+0x2A, 0x80, 0x02, 0x80, 0x57, 0x89, 0x82, 0x8A,
-+0x83, 0xEC, 0xFA, 0xE4, 0x93, 0xF5, 0xF0, 0xA3,
-+0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC,
-+0xE0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5,
-+0x83, 0xCC, 0xB5, 0xF0, 0x06, 0xDF, 0xE4, 0xDE,
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-+0x79, 0x22, 0xF9, 0xE4, 0x3A, 0x8B, 0x1B, 0xF5,
-+0x1C, 0x89, 0x1D, 0x75, 0x1E, 0x04, 0x7B, 0x01,
-+0x7A, 0x94, 0x79, 0x27, 0x12, 0x68, 0xAB, 0x90,
-+0x94, 0x21, 0xE0, 0x75, 0xF0, 0x08, 0xA4, 0x22,
-+0xF0, 0xA3, 0xEF, 0xF0, 0x74, 0x02, 0x2D, 0xF5,
-+0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x54,
-+0x0F, 0x33, 0x33, 0x33, 0x54, 0xF8, 0xFF, 0x74,
-+0x03, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5,
-+0x83, 0xE0, 0x54, 0x03, 0x22, 0xE0, 0xFF, 0xAE,
-+0x05, 0x74, 0x18, 0x2E, 0xF5, 0x82, 0xE4, 0x34,
-+0xFC, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x00, 0x8B,
-+0xE0, 0xD3, 0x94, 0x03, 0x74, 0x10, 0x2E, 0xF5,
-+0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0x74, 0x04,
-+0xF0, 0x22, 0x90, 0x93, 0x8F, 0xE0, 0x2F, 0xFF,
-+0x90, 0x93, 0x8E, 0xE0, 0x34, 0x00, 0xFE, 0x90,
-+0x94, 0x12, 0xF0, 0xA3, 0x22, 0x90, 0x93, 0x8B,
-+0xE0, 0xFF, 0x24, 0x20, 0xF5, 0x82, 0xE4, 0x34,
-+0x91, 0xF5, 0x83, 0xE0, 0xFE, 0x22, 0x90, 0x8A,
-+0x75, 0xE0, 0x24, 0x01, 0xFF, 0x90, 0x8A, 0x74,
-+0xE0, 0x34, 0x00, 0xFE, 0xC3, 0x22, 0x90, 0x90,
-+0x04, 0xE0, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x22,
-+0x90, 0x8F, 0xB2, 0xA3, 0xE0, 0x24, 0x04, 0xF5,
-+0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x22,
-+0xEE, 0x8F, 0xF0, 0x12, 0x02, 0xE7, 0x90, 0x8A,
-+0x74, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0x90,
-+0x8F, 0xAE, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22,
-+0x90, 0x8A, 0x95, 0xE0, 0xFF, 0xA3, 0xE0, 0xFD,
-+0x90, 0x8A, 0x9C, 0xE0, 0xFB, 0x22, 0xE0, 0x90,
-+0x01, 0xBA, 0xF0, 0x90, 0x8A, 0x85, 0xE0, 0x90,
-+0x01, 0xBB, 0x22, 0x90, 0x93, 0x67, 0xE0, 0xFD,
-+0x90, 0x93, 0x66, 0xE0, 0x2D, 0x22, 0xFF, 0xEC,
-+0x3E, 0x90, 0x93, 0x6D, 0xF0, 0xA3, 0xEF, 0xF0,
-+0x22, 0x90, 0x94, 0x5D, 0xE0, 0xC3, 0x13, 0x90,
-+0xFD, 0x10, 0xF0, 0x22, 0xCF, 0x34, 0x00, 0x90,
-+0x93, 0x69, 0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0x90,
-+0x90, 0x04, 0xE0, 0x13, 0x13, 0x22, 0xFD, 0x12,
-+0x7A, 0xDD, 0x90, 0x93, 0x89, 0xEF, 0xF0, 0x22,
-+0x75, 0x1C, 0x91, 0x75, 0x1D, 0x1E, 0x75, 0x1E,
-+0x02, 0x22, 0xF0, 0xEE, 0x54, 0x08, 0xFE, 0xEF,
-+0x54, 0xF7, 0x4E, 0x22, 0xD2, 0xAF, 0xC2, 0xAF,
-+0x90, 0x89, 0x7E, 0xE0, 0xFF, 0x22, 0x54, 0x10,
-+0xFD, 0xEF, 0x54, 0xEF, 0x4D, 0xFF, 0x22, 0x54,
-+0x40, 0xFD, 0xEF, 0x54, 0xBF, 0x4D, 0xFF, 0x22,
-+0x54, 0x04, 0xFD, 0xEF, 0x54, 0xFB, 0x4D, 0xFF,
-+0x22, 0xF0, 0xEE, 0x54, 0x80, 0xFE, 0xEF, 0x54,
-+0x7F, 0x22, 0x90, 0x8F, 0xAE, 0xE0, 0xFC, 0xA3,
-+0xE0, 0xFD, 0x22, 0x90, 0x8F, 0xB0, 0xE0, 0xFE,
-+0xA3, 0xE0, 0xFF, 0x22, 0xF0, 0xA3, 0xEF, 0xF0,
-+0x90, 0x02, 0x87, 0xE0, 0x22, 0x90, 0x01, 0x1F,
-+0xE0, 0xFE, 0x90, 0x01, 0x1E, 0x22, 0x90, 0x93,
-+0x67, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0x90,
-+0x94, 0x81, 0xE0, 0xFE, 0xA3, 0xE0, 0x22, 0x24,
-+0x06, 0xFD, 0x12, 0x52, 0xBD, 0xEF, 0x22, 0x12,
-+0x7A, 0xA5, 0x90, 0x94, 0xA4, 0xE0, 0x22, 0x00,
-+0xB0, 0xD4
-+};
-+
-+u32 array_length_mp_8703b_fw_wowlan = 23074;
-+
-+#endif /*CONFIG_WOWLAN*/
-+
-+#endif
-+
-+#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/hal8703b_fw.h b/drivers/staging/rtl8723cs/hal/rtl8703b/hal8703b_fw.h
-new file mode 100644
-index 000000000000..0eeb656df975
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/hal8703b_fw.h
-@@ -0,0 +1,40 @@
-+/******************************************************************************
-+*
-+* Copyright(c) 2012 - 2017 Realtek Corporation.
-+*
-+* This program is free software; you can redistribute it and/or modify it
-+* under the terms of version 2 of the GNU General Public License as
-+* published by the Free Software Foundation.
-+*
-+* This program is distributed in the hope that it will be useful, but WITHOUT
-+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+* more details.
-+*
-+******************************************************************************/
-+
-+#ifdef CONFIG_RTL8703B
-+
-+#ifndef _FW_HEADER_8703B_H
-+#define _FW_HEADER_8703B_H
-+
-+#ifdef LOAD_FW_HEADER_FROM_DRIVER
-+#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))
-+extern u8 array_mp_8703b_fw_ap[19994];
-+extern u32 array_length_mp_8703b_fw_ap;
-+#endif
-+
-+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))
-+extern u8 array_mp_8703b_fw_nic[20290];
-+extern u32 array_length_mp_8703b_fw_nic;
-+#ifdef CONFIG_WOWLAN
-+extern u8 array_mp_8703b_fw_wowlan[23074];
-+extern u32 array_length_mp_8703b_fw_wowlan;
-+#endif /*CONFIG_WOWLAN*/
-+#endif
-+#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */
-+
-+#endif
-+
-+#endif
-+
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_cmd.c b/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_cmd.c
-new file mode 100644
-index 000000000000..6ed40ac07f71
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_cmd.c
-@@ -0,0 +1,507 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTL8703B_CMD_C_
-+
-+#include <rtl8703b_hal.h>
-+#include "hal_com_h2c.h"
-+
-+#define MAX_H2C_BOX_NUMS	4
-+#define MESSAGE_BOX_SIZE		4
-+
-+#define RTL8703B_MAX_CMD_LEN	7
-+#define RTL8703B_EX_MESSAGE_BOX_SIZE	4
-+
-+static u8 _is_fw_read_cmd_down(_adapter *padapter, u8 msgbox_num)
-+{
-+	u8	read_down = _FALSE;
-+	int	retry_cnts = 100;
-+
-+	u8 valid;
-+
-+	/* RTW_INFO(" _is_fw_read_cmd_down ,reg_1cc(%x),msg_box(%d)...\n",rtw_read8(padapter,REG_HMETFR),msgbox_num); */
-+
-+	do {
-+		valid = rtw_read8(padapter, REG_HMETFR) & BIT(msgbox_num);
-+		if (0 == valid)
-+			read_down = _TRUE;
-+		else
-+			rtw_msleep_os(1);
-+	} while ((!read_down) && (retry_cnts--));
-+
-+	return read_down;
-+
-+}
-+
-+
-+/*****************************************
-+* H2C Msg format :
-+*| 31 - 8		|7-5	| 4 - 0	|
-+*| h2c_msg	|Class	|CMD_ID	|
-+*| 31-0						|
-+*| Ext msg					|
-+*
-+******************************************/
-+s32 FillH2CCmd8703B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
-+{
-+	u8 h2c_box_num;
-+	u8 h2c[RTL8703B_MAX_CMD_LEN + 1] = {0};
-+	u32	msgbox_addr;
-+	u32 msgbox_ex_addr = 0;
-+	PHAL_DATA_TYPE pHalData;
-+	u32	h2c_cmd = 0;
-+	u32	h2c_cmd_ex = 0;
-+	s32 ret = _FAIL;
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+
-+	padapter = GET_PRIMARY_ADAPTER(padapter);
-+	pHalData = GET_HAL_DATA(padapter);
-+#ifdef DBG_CHECK_FW_PS_STATE
-+#ifdef DBG_CHECK_FW_PS_STATE_H2C
-+	if (rtw_fw_ps_state(padapter) == _FAIL) {
-+		RTW_INFO("%s: h2c doesn't leave 32k ElementID=%02x\n", __FUNCTION__, ElementID);
-+		pdbgpriv->dbg_h2c_leave32k_fail_cnt++;
-+	}
-+
-+	/* RTW_INFO("H2C ElementID=%02x , pHalData->LastHMEBoxNum=%02x\n", ElementID, pHalData->LastHMEBoxNum); */
-+#endif /* DBG_CHECK_FW_PS_STATE_H2C */
-+#endif /* DBG_CHECK_FW_PS_STATE */
-+	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL);
-+
-+	if (!pCmdBuffer)
-+		goto exit;
-+	if (CmdLen > RTL8703B_MAX_CMD_LEN)
-+		goto exit;
-+	if (rtw_is_surprise_removed(padapter))
-+		goto exit;
-+
-+	h2c[0] = ElementID;
-+	_rtw_memcpy(h2c + 1, pCmdBuffer, CmdLen);
-+
-+	/* pay attention to if  race condition happened in  H2C cmd setting. */
-+	do {
-+		h2c_box_num = pHalData->LastHMEBoxNum;
-+
-+		if (!_is_fw_read_cmd_down(padapter, h2c_box_num)) {
-+			RTW_INFO(" fw read cmd failed...\n");
-+#ifdef DBG_CHECK_FW_PS_STATE
-+			RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
-+				, rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
-+#endif /* DBG_CHECK_FW_PS_STATE */
-+			/* RTW_INFO(" 0x1c0: 0x%8x\n", rtw_read32(padapter, 0x1c0)); */
-+			/* RTW_INFO(" 0x1c4: 0x%8x\n", rtw_read32(padapter, 0x1c4)); */
-+			goto exit;
-+		}
-+
-+		/* Write Ext command (byte 4~7) */
-+		msgbox_ex_addr = REG_HMEBOX_EXT0_8703B + (h2c_box_num * RTL8703B_EX_MESSAGE_BOX_SIZE);
-+		_rtw_memcpy((u8 *)(&h2c_cmd_ex), h2c + 4, RTL8703B_EX_MESSAGE_BOX_SIZE);
-+		h2c_cmd_ex = le32_to_cpu(h2c_cmd_ex);
-+		rtw_write32(padapter, msgbox_ex_addr, h2c_cmd_ex);
-+
-+		/* Write command (byte 0~3) */
-+		msgbox_addr = REG_HMEBOX_0_8703B + (h2c_box_num * MESSAGE_BOX_SIZE);
-+		_rtw_memcpy((u8 *)(&h2c_cmd), h2c, 4);
-+		h2c_cmd = le32_to_cpu(h2c_cmd);
-+		rtw_write32(padapter, msgbox_addr, h2c_cmd);
-+
-+		/* RTW_INFO("MSG_BOX:%d, CmdLen(%d), CmdID(0x%x), reg:0x%x =>h2c_cmd:0x%.8x, reg:0x%x =>h2c_cmd_ex:0x%.8x\n" */
-+		/*	,pHalData->LastHMEBoxNum , CmdLen, ElementID, msgbox_addr, h2c_cmd, msgbox_ex_addr, h2c_cmd_ex); */
-+
-+		pHalData->LastHMEBoxNum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS;
-+
-+	} while (0);
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+
-+	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL);
-+
-+
-+	return ret;
-+}
-+
-+/*
-+ * Description: Get the reserved page number in Tx packet buffer.
-+ * Retrun value: the page number.
-+ * 2012.08.09, by tynli.
-+ *   */
-+u8 GetTxBufferRsvdPageNum8703B(_adapter *padapter, bool wowlan)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	u8	RsvdPageNum = 0;
-+	/* default reseved 1 page for the IC type which is undefined. */
-+	u8	TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8703B;
-+
-+	rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&TxPageBndy);
-+
-+	RsvdPageNum = LAST_ENTRY_OF_TX_PKT_BUFFER_8703B - TxPageBndy + 1;
-+
-+	return RsvdPageNum;
-+}
-+
-+void rtl8703b_set_FwPwrMode_cmd(PADAPTER padapter, u8 psmode)
-+{
-+	u8 smart_ps = 0;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	u8 u1H2CPwrModeParm[H2C_PWRMODE_LEN] = {0};
-+	u8 PowerState = 0, awake_intvl = 1, rlbm = 0;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *wdinfo = &(padapter->wdinfo);
-+#endif /* CONFIG_P2P */
-+	u8 allQueueUAPSD = 0;
-+
-+
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+	if (psmode == PS_MODE_DTIM)
-+		psmode = PS_MODE_MAX;
-+#endif /* CONFIG_PLATFORM_INTEL_BYT */
-+
-+
-+	if (pwrpriv->dtim > 0)
-+		RTW_INFO("%s(): FW LPS mode = %d, SmartPS=%d, dtim=%d\n", __func__, psmode, pwrpriv->smart_ps, pwrpriv->dtim);
-+	else
-+		RTW_INFO("%s(): FW LPS mode = %d, SmartPS=%d\n", __func__, psmode, pwrpriv->smart_ps);
-+
-+	if (psmode == PS_MODE_MIN) {
-+		rlbm = 0;
-+		awake_intvl = 2;
-+		smart_ps = pwrpriv->smart_ps;
-+	} else if (psmode == PS_MODE_MAX) {
-+		rlbm = 1;
-+		awake_intvl = 2;
-+		smart_ps = pwrpriv->smart_ps;
-+	} else if (psmode == PS_MODE_DTIM) { /* For WOWLAN LPS, DTIM = (awake_intvl - 1) */
-+		if (pwrpriv->dtim > 0 && pwrpriv->dtim < 16)
-+			awake_intvl = pwrpriv->dtim + 1; /* DTIM = (awake_intvl - 1) */
-+		else
-+			awake_intvl = 4;/* DTIM=3 */
-+
-+
-+		rlbm = 2;
-+		smart_ps = pwrpriv->smart_ps;
-+	} else {
-+		rlbm = 2;
-+		awake_intvl = 4;
-+		smart_ps = pwrpriv->smart_ps;
-+	}
-+
-+#ifdef CONFIG_P2P
-+	if (!rtw_p2p_chk_state(wdinfo, P2P_STATE_NONE)) {
-+		awake_intvl = 2;
-+		rlbm = 1;
-+	}
-+#endif /* CONFIG_P2P */
-+
-+	if (padapter->registrypriv.wifi_spec == 1) {
-+		awake_intvl = 2;
-+		rlbm = 1;
-+	}
-+
-+	if (psmode > 0) {
-+#ifdef CONFIG_BT_COEXIST
-+		if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
-+			PowerState = rtw_btcoex_RpwmVal(padapter);
-+		else
-+#endif /* CONFIG_BT_COEXIST */
-+			PowerState = 0x00;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
-+	} else 
-+		PowerState = 0x0C;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */
-+
-+	SET_8703B_H2CCMD_PWRMODE_PARM_MODE(u1H2CPwrModeParm, (psmode > 0) ? 1 : 0);
-+	SET_8703B_H2CCMD_PWRMODE_PARM_SMART_PS(u1H2CPwrModeParm, smart_ps);
-+	SET_8703B_H2CCMD_PWRMODE_PARM_RLBM(u1H2CPwrModeParm, rlbm);
-+	SET_8703B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1H2CPwrModeParm, awake_intvl);
-+	SET_8703B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1H2CPwrModeParm, allQueueUAPSD);
-+	SET_8703B_H2CCMD_PWRMODE_PARM_PWR_STATE(u1H2CPwrModeParm, PowerState);
-+
-+#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_RecordPwrMode(padapter, u1H2CPwrModeParm, H2C_PWRMODE_LEN);
-+#endif /* CONFIG_BT_COEXIST */
-+
-+	RTW_DBG_DUMP("u1H2CPwrModeParm:", u1H2CPwrModeParm, H2C_PWRMODE_LEN);
-+
-+	FillH2CCmd8703B(padapter, H2C_8703B_SET_PWR_MODE, H2C_PWRMODE_LEN, u1H2CPwrModeParm);
-+}
-+
-+void rtl8703b_set_FwPsTuneParam_cmd(PADAPTER padapter)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	u8 u1H2CPsTuneParm[H2C_PSTUNEPARAM_LEN] = {0};
-+	u8 bcn_to_limit = 10; /* 10 * 100 * awakeinterval (ms) */
-+	u8 dtim_timeout = 5; /* ms */ /* wait broadcast data timer */
-+	u8 ps_timeout = 20;  /* ms */ /* Keep awake when tx */
-+	u8 dtim_period = 3;
-+
-+	/* RTW_INFO("%s(): FW LPS mode = %d\n", __func__, psmode); */
-+
-+	SET_8703B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(u1H2CPsTuneParm, bcn_to_limit);
-+	SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(u1H2CPsTuneParm, dtim_timeout);
-+	SET_8703B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(u1H2CPsTuneParm, ps_timeout);
-+	SET_8703B_H2CCMD_PSTUNE_PARM_ADOPT(u1H2CPsTuneParm, 1);
-+	SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(u1H2CPsTuneParm, dtim_period);
-+
-+	RTW_DBG_DUMP("u1H2CPsTuneParm:", u1H2CPsTuneParm, H2C_PSTUNEPARAM_LEN);
-+
-+	FillH2CCmd8703B(padapter, H2C_8703B_PS_TUNING_PARA, H2C_PSTUNEPARAM_LEN, u1H2CPsTuneParm);
-+}
-+
-+void rtl8703b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param)
-+{
-+	u8 u1H2CBtMpOperParm[H2C_BTMP_OPER_LEN] = {0};
-+
-+
-+	RTW_INFO("%s: idx=%d ver=%d reqnum=%d param1=0x%02x param2=0x%02x\n", __FUNCTION__, idx, ver, reqnum, param[0], param[1]);
-+
-+	SET_8703B_H2CCMD_BT_MPOPER_VER(u1H2CBtMpOperParm, ver);
-+	SET_8703B_H2CCMD_BT_MPOPER_REQNUM(u1H2CBtMpOperParm, reqnum);
-+	SET_8703B_H2CCMD_BT_MPOPER_IDX(u1H2CBtMpOperParm, idx);
-+	SET_8703B_H2CCMD_BT_MPOPER_PARAM1(u1H2CBtMpOperParm, param[0]);
-+	SET_8703B_H2CCMD_BT_MPOPER_PARAM2(u1H2CBtMpOperParm, param[1]);
-+	SET_8703B_H2CCMD_BT_MPOPER_PARAM3(u1H2CBtMpOperParm, param[2]);
-+
-+	RTW_DBG_DUMP("u1H2CBtMpOperParm:", u1H2CBtMpOperParm, H2C_BTMP_OPER_LEN);
-+
-+	FillH2CCmd8703B(padapter, H2C_8703B_BT_MP_OPER, H2C_BTMP_OPER_LEN, u1H2CBtMpOperParm);
-+}
-+
-+void rtl8703b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param)
-+{
-+	/* u8 cmd_param; */ /* BIT0:enable, BIT1:NoConnect32k */
-+
-+	RTW_INFO("%s()\n", __func__);
-+
-+	FillH2CCmd8703B(padapter, H2C_8703B_INACTIVE_PS_, 1, &cmd_param);
-+
-+}
-+
-+void rtl8703b_download_rsvd_page(PADAPTER padapter, u8 mstatus)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	BOOLEAN		bcn_valid = _FALSE;
-+	u8	DLBcnCount = 0;
-+	u32 poll = 0;
-+	u8 RegFwHwTxQCtrl;
-+
-+
-+	RTW_INFO("+" FUNC_ADPT_FMT ": hw_port=%d mstatus(%x)\n",
-+		 FUNC_ADPT_ARG(padapter), get_hw_port(padapter), mstatus);
-+
-+	if (mstatus == RT_MEDIA_CONNECT) {
-+		u8 bcn_ctrl = rtw_read8(padapter, REG_BCN_CTRL);
-+		BOOLEAN bRecover = _FALSE;
-+		u8 v8;
-+
-+		/* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */
-+		/* Suggested by filen. Added by tynli. */
-+		rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000 | pmlmeinfo->aid));
-+
-+		/* set REG_CR bit 8 */
-+		v8 = rtw_read8(padapter, REG_CR + 1);
-+		v8 |= BIT(0); /* ENSWBCN */
-+		rtw_write8(padapter,  REG_CR + 1, v8);
-+
-+		/* Disable Hw protection for a time which revserd for Hw sending beacon. */
-+		/* Fix download reserved page packet fail that access collision with the protection time. */
-+		/* 2010.05.11. Added by tynli. */
-+		rtw_write8(padapter, REG_BCN_CTRL, (bcn_ctrl & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);
-+
-+		/* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */
-+		RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2);
-+		if (RegFwHwTxQCtrl & BIT(6))
-+			bRecover = _TRUE;
-+
-+		/* To tell Hw the packet is not a real beacon frame. */
-+		RegFwHwTxQCtrl &= ~BIT(6);
-+		rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, RegFwHwTxQCtrl);
-+
-+		/* Clear beacon valid check bit. */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
-+
-+		DLBcnCount = 0;
-+		poll = 0;
-+		do {
-+			/* download rsvd page. */
-+			rtw_hal_set_fw_rsvd_page(padapter, _FALSE);
-+			DLBcnCount++;
-+			do {
-+				rtw_yield_os();
-+				/* rtw_mdelay_os(10); */
-+				/* check rsvd page download OK. */
-+				rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bcn_valid));
-+				poll++;
-+			} while (!bcn_valid && (poll % 10) != 0 && !RTW_CANNOT_RUN(padapter));
-+
-+		} while (!bcn_valid && DLBcnCount <= 100 && !RTW_CANNOT_RUN(padapter));
-+
-+		if (RTW_CANNOT_RUN(padapter))
-+			;
-+		else if (!bcn_valid)
-+			RTW_ERR(ADPT_FMT": 1 DL RSVD page failed! DLBcnCount:%u, poll:%u\n",
-+				 ADPT_ARG(padapter) , DLBcnCount, poll);
-+		else {
-+			struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
-+
-+			pwrctl->fw_psmode_iface_id = padapter->iface_id;
-+			rtw_hal_set_fw_rsvd_page(padapter, _TRUE);
-+			RTW_INFO(ADPT_FMT": 1 DL RSVD page success! DLBcnCount:%u, poll:%u\n",
-+				 ADPT_ARG(padapter), DLBcnCount, poll);
-+		}
-+
-+		/* restore bcn_ctrl */
-+		rtw_write8(padapter, REG_BCN_CTRL, bcn_ctrl);
-+
-+		/* To make sure that if there exists an adapter which would like to send beacon. */
-+		/* If exists, the origianl value of 0x422[6] will be 1, we should check this to */
-+		/* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
-+		/* the beacon cannot be sent by HW. */
-+		/* 2010.06.23. Added by tynli. */
-+		if (bRecover) {
-+			RegFwHwTxQCtrl |= BIT(6);
-+			rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, RegFwHwTxQCtrl);
-+		}
-+
-+		/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
-+#ifndef CONFIG_PCI_HCI
-+		v8 = rtw_read8(padapter, REG_CR + 1);
-+		v8 &= ~BIT(0); /* ~ENSWBCN */
-+		rtw_write8(padapter, REG_CR + 1, v8);
-+#endif
-+	}
-+
-+}
-+
-+
-+void rtl8703b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus)
-+{
-+	if (mstatus == 1)
-+		rtl8703b_download_rsvd_page(padapter, RT_MEDIA_CONNECT);
-+}
-+
-+#if 0
-+void rtl8703b_set_FwAPReqRPT_cmd(PADAPTER padapter, u32 need_ack)
-+{
-+	u8 u1H2CApReqRptParm[H2C_AP_REQ_TXRPT_LEN] = {0};
-+	u8 macid1 = 1, macid2 = 0;
-+
-+	RTW_INFO("%s(): need_ack = %d\n", __func__, need_ack);
-+
-+	SET_8703B_H2CCMD_APREQRPT_PARM_MACID1(u1H2CApReqRptParm, macid1);
-+	SET_8703B_H2CCMD_APREQRPT_PARM_MACID2(u1H2CApReqRptParm, macid2);
-+
-+	RTW_DBG_DUMP("u1H2CApReqRptParm:", u1H2CApReqRptParm, H2C_AP_REQ_TXRPT_LEN);
-+	FillH2CCmd8703B(padapter, H2C_8703B_AP_REQ_TXRPT, H2C_AP_REQ_TXRPT_LEN, u1H2CApReqRptParm);
-+}
-+
-+void rtl8703b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack)
-+{
-+	rtl8703b_set_FwAPReqRPT_cmd(padapter, need_ack);
-+}
-+#endif
-+
-+#ifdef CONFIG_BT_COEXIST
-+void rtl8703b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter)
-+{
-+	rtl8703b_download_rsvd_page(padapter, RT_MEDIA_CONNECT);
-+}
-+#endif /* CONFIG_BT_COEXIST */
-+
-+#ifdef CONFIG_P2P
-+void rtl8703b_set_p2p_ps_offload_cmd(_adapter *padapter, u8 p2p_ps_state)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct pwrctrl_priv		*pwrpriv = adapter_to_pwrctl(padapter);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	struct P2P_PS_Offload_t	*p2p_ps_offload = (struct P2P_PS_Offload_t *)(&pHalData->p2p_ps_offload);
-+	u8	i;
-+
-+
-+#if 1
-+	switch (p2p_ps_state) {
-+	case P2P_PS_DISABLE:
-+		RTW_INFO("P2P_PS_DISABLE\n");
-+		_rtw_memset(p2p_ps_offload, 0 , 1);
-+		break;
-+	case P2P_PS_ENABLE:
-+		RTW_INFO("P2P_PS_ENABLE\n");
-+		/* update CTWindow value. */
-+		if (pwdinfo->ctwindow > 0) {
-+			p2p_ps_offload->CTWindow_En = 1;
-+			rtw_write8(padapter, REG_P2P_CTWIN, pwdinfo->ctwindow);
-+		}
-+
-+		/* hw only support 2 set of NoA */
-+		for (i = 0 ; i < pwdinfo->noa_num ; i++) {
-+			/* To control the register setting for which NOA */
-+			rtw_write8(padapter, REG_NOA_DESC_SEL, (i << 4));
-+			if (i == 0)
-+				p2p_ps_offload->NoA0_En = 1;
-+			else
-+				p2p_ps_offload->NoA1_En = 1;
-+
-+			/* config P2P NoA Descriptor Register */
-+			/* RTW_INFO("%s(): noa_duration = %x\n",__FUNCTION__,pwdinfo->noa_duration[i]); */
-+			rtw_write32(padapter, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]);
-+
-+			/* RTW_INFO("%s(): noa_interval = %x\n",__FUNCTION__,pwdinfo->noa_interval[i]); */
-+			rtw_write32(padapter, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]);
-+
-+			/* RTW_INFO("%s(): start_time = %x\n",__FUNCTION__,pwdinfo->noa_start_time[i]); */
-+			rtw_write32(padapter, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]);
-+
-+			/* RTW_INFO("%s(): noa_count = %x\n",__FUNCTION__,pwdinfo->noa_count[i]); */
-+			rtw_write8(padapter, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]);
-+		}
-+
-+		if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) {
-+			/* rst p2p circuit */
-+			rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4));
-+
-+			p2p_ps_offload->Offload_En = 1;
-+
-+			if (pwdinfo->role == P2P_ROLE_GO) {
-+				p2p_ps_offload->role = 1;
-+				p2p_ps_offload->AllStaSleep = 0;
-+			} else
-+				p2p_ps_offload->role = 0;
-+
-+			p2p_ps_offload->discovery = 0;
-+		}
-+		break;
-+	case P2P_PS_SCAN:
-+		RTW_INFO("P2P_PS_SCAN\n");
-+		p2p_ps_offload->discovery = 1;
-+		break;
-+	case P2P_PS_SCAN_DONE:
-+		RTW_INFO("P2P_PS_SCAN_DONE\n");
-+		p2p_ps_offload->discovery = 0;
-+		pwdinfo->p2p_ps_state = P2P_PS_ENABLE;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	FillH2CCmd8703B(padapter, H2C_8703B_P2P_PS_OFFLOAD, 1, (u8 *)p2p_ps_offload);
-+#endif
-+
-+
-+}
-+#endif /* CONFIG_P2P */
-+
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_dm.c b/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_dm.c
-new file mode 100644
-index 000000000000..fece396bb4d7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_dm.c
-@@ -0,0 +1,307 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/* ************************************************************
-+ * Description:
-+ *
-+ * This file is for 92CE/92CU dynamic mechanism only
-+ *
-+ *
-+ * ************************************************************ */
-+#define _RTL8703B_DM_C_
-+
-+/* ************************************************************
-+ * include files
-+ * ************************************************************ */
-+#include <rtl8703b_hal.h>
-+
-+/* ************************************************************
-+ * Global var
-+ * ************************************************************ */
-+#ifdef CONFIG_SUPPORT_HW_WPS_PBC
-+static void dm_CheckPbcGPIO(_adapter *padapter)
-+{
-+	u8	tmp1byte;
-+	u8	bPbcPressed = _FALSE;
-+
-+	if (!padapter->registrypriv.hw_wps_pbc)
-+		return;
-+
-+#ifdef CONFIG_USB_HCI
-+	tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
-+	tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT);
-+	rtw_write8(padapter, GPIO_IO_SEL, tmp1byte);	/* enable GPIO[2] as output mode */
-+
-+	tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
-+	rtw_write8(padapter,  GPIO_IN, tmp1byte);		/* reset the floating voltage level */
-+
-+	tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
-+	tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
-+	rtw_write8(padapter, GPIO_IO_SEL, tmp1byte);	/* enable GPIO[2] as input mode */
-+
-+	tmp1byte = rtw_read8(padapter, GPIO_IN);
-+
-+	if (tmp1byte == 0xff)
-+		return ;
-+
-+	if (tmp1byte & HAL_8192C_HW_GPIO_WPS_BIT)
-+		bPbcPressed = _TRUE;
-+#else
-+	tmp1byte = rtw_read8(padapter, GPIO_IN);
-+
-+	if (tmp1byte == 0xff || padapter->init_adpt_in_progress)
-+		return ;
-+
-+	if ((tmp1byte & HAL_8192C_HW_GPIO_WPS_BIT) == 0)
-+		bPbcPressed = _TRUE;
-+#endif
-+
-+	if (_TRUE == bPbcPressed) {
-+		/* Here we only set bPbcPressed to true */
-+		/* After trigger PBC, the variable will be set to false */
-+		RTW_INFO("CheckPbcGPIO - PBC is pressed\n");
-+		rtw_request_wps_pbc_event(padapter);
-+	}
-+}
-+#endif /* #ifdef CONFIG_SUPPORT_HW_WPS_PBC */
-+
-+
-+#ifdef CONFIG_PCI_HCI
-+/*
-+ *	Description:
-+ *		Perform interrupt migration dynamically to reduce CPU utilization.
-+ *
-+ *	Assumption:
-+ *		1. Do not enable migration under WIFI test.
-+ *
-+ *	Created by Roger, 2010.03.05.
-+ *   */
-+void
-+dm_InterruptMigration(
-+		PADAPTER	Adapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);
-+	BOOLEAN			bCurrentIntMt, bCurrentACIntDisable;
-+	BOOLEAN			IntMtToSet = _FALSE;
-+	BOOLEAN			ACIntToSet = _FALSE;
-+
-+
-+	/* Retrieve current interrupt migration and Tx four ACs IMR settings first. */
-+	bCurrentIntMt = pHalData->bInterruptMigration;
-+	bCurrentACIntDisable = pHalData->bDisableTxInt;
-+
-+	/*  */
-+	/* <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics */
-+	/* when interrupt migration is set before. 2010.03.05. */
-+	/*  */
-+	if (!Adapter->registrypriv.wifi_spec &&
-+	    (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) &&
-+	    pmlmepriv->LinkDetectInfo.bHigherBusyTraffic) {
-+		IntMtToSet = _TRUE;
-+
-+		/* To check whether we should disable Tx interrupt or not. */
-+		if (pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic)
-+			ACIntToSet = _TRUE;
-+	}
-+
-+	/* Update current settings. */
-+	if (bCurrentIntMt != IntMtToSet) {
-+		RTW_INFO("%s(): Update interrrupt migration(%d)\n", __FUNCTION__, IntMtToSet);
-+		if (IntMtToSet) {
-+			/*  */
-+			/* <Roger_Notes> Set interrrupt migration timer and corresponging Tx/Rx counter. */
-+			/* timer 25ns*0xfa0=100us for 0xf packets. */
-+			/* 2010.03.05. */
-+			/*  */
-+			rtw_write32(Adapter, REG_INT_MIG, 0xff000fa0);/* 0x306:Rx, 0x307:Tx */
-+			pHalData->bInterruptMigration = IntMtToSet;
-+		} else {
-+			/* Reset all interrupt migration settings. */
-+			rtw_write32(Adapter, REG_INT_MIG, 0);
-+			pHalData->bInterruptMigration = IntMtToSet;
-+		}
-+	}
-+
-+#if 0
-+	if (bCurrentACIntDisable != ACIntToSet) {
-+		RTW_INFO("%s(): Update AC interrrupt(%d)\n", __FUNCTION__, ACIntToSet);
-+		if (ACIntToSet) { /*  Disable four ACs interrupts. */
-+			/* */
-+			/*  <Roger_Notes> Disable VO, VI, BE and BK four AC interrupts to gain more efficient CPU utilization. */
-+			/*  When extremely highly Rx OK occurs, we will disable Tx interrupts. */
-+			/*  2010.03.05. */
-+			/* */
-+			UpdateInterruptMask8192CE(Adapter, 0, RT_AC_INT_MASKS);
-+			pHalData->bDisableTxInt = ACIntToSet;
-+		} else { /*  Enable four ACs interrupts. */
-+			UpdateInterruptMask8192CE(Adapter, RT_AC_INT_MASKS, 0);
-+			pHalData->bDisableTxInt = ACIntToSet;
-+		}
-+	}
-+#endif
-+
-+}
-+
-+#endif
-+
-+/*
-+ * Initialize GPIO setting registers
-+ *   */
-+#ifdef CONFIG_USB_HCI
-+static void
-+dm_InitGPIOSetting(
-+		PADAPTER	Adapter
-+)
-+{
-+	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(Adapter);
-+
-+	u8	tmp1byte;
-+
-+	tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG);
-+	tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT);
-+
-+	rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte);
-+}
-+#endif
-+/* ************************************************************
-+ * functions
-+ * ************************************************************ */
-+static void Init_ODM_ComInfo_8703b(PADAPTER	Adapter)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
-+	u8	cut_ver, fab_ver;
-+
-+	Init_ODM_ComInfo(Adapter);
-+
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, pHalData->PackageType);
-+
-+	fab_ver = ODM_TSMC;
-+	cut_ver = GET_CVID_CUT_VERSION(pHalData->version_id);
-+
-+	RTW_INFO("%s(): Fv=%d Cv=%d\n", __func__, fab_ver, cut_ver);
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_FAB_VER, fab_ver);
-+	odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_CUT_VER, cut_ver);
-+}
-+
-+void
-+rtl8703b_InitHalDm(
-+		PADAPTER	Adapter
-+)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
-+
-+#ifdef CONFIG_USB_HCI
-+	dm_InitGPIOSetting(Adapter);
-+#endif
-+	rtw_phydm_init(Adapter);
-+}
-+
-+void
-+rtl8703b_HalDmWatchDog(
-+		PADAPTER	Adapter
-+)
-+{
-+	BOOLEAN		bFwCurrentInPSMode = _FALSE;
-+	u8 bFwPSAwake = _TRUE;
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);
-+	u8 in_lps = _FALSE;
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	/* #if MP_DRIVER */
-+	if (Adapter->registrypriv.mp_mode == 1 && Adapter->mppriv.mp_dm == 0) /* for MP power tracking */
-+		return;
-+	/* #endif */
-+#endif
-+
-+	if (!rtw_is_hw_init_completed(Adapter))
-+		goto skip_dm;
-+
-+#ifdef CONFIG_LPS
-+	bFwCurrentInPSMode = pwrpriv->bFwCurrentInPSMode;
-+	rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, &bFwPSAwake);
-+#endif
-+
-+#ifdef CONFIG_P2P
-+	/* Fw is under p2p powersaving mode, driver should stop dynamic mechanism. */
-+	/* modifed by thomas. 2011.06.11. */
-+	if (Adapter->wdinfo.p2p_ps_mode)
-+		bFwPSAwake = _FALSE;
-+#endif /* CONFIG_P2P */
-+
-+
-+	if ((rtw_is_hw_init_completed(Adapter))
-+	    && ((!bFwCurrentInPSMode) && bFwPSAwake)) {
-+
-+		rtw_hal_check_rxfifo_full(Adapter);
-+		/*  */
-+		/* Dynamically switch RTS/CTS protection. */
-+		/*  */
-+
-+#ifdef CONFIG_PCI_HCI
-+		/* 20100630 Joseph: Disable Interrupt Migration mechanism temporarily because it degrades Rx throughput. */
-+		/* Tx Migration settings. */
-+		/* dm_InterruptMigration(Adapter); */
-+
-+		/* if(Adapter->HalFunc.TxCheckStuckHandler(Adapter)) */
-+		/*	PlatformScheduleWorkItem(&(GET_HAL_DATA(Adapter)->HalResetWorkItem)); */
-+#endif
-+	}
-+
-+#ifdef CONFIG_DISABLE_ODM
-+	goto skip_dm;
-+#endif
-+#ifdef CONFIG_LPS
-+	if (pwrpriv->bLeisurePs && bFwCurrentInPSMode && pwrpriv->pwr_mode != PS_MODE_ACTIVE)
-+		in_lps = _TRUE;
-+#endif
-+
-+	rtw_phydm_watchdog(Adapter, in_lps);
-+
-+skip_dm:
-+
-+	/* Check GPIO to determine current RF on/off and Pbc status. */
-+	/* Check Hardware Radio ON/OFF or not */
-+	/* if(Adapter->MgntInfo.PowerSaveControl.bGpioRfSw) */
-+	/* { */
-+	/* RTPRINT(FPWR, PWRHW, ("dm_CheckRfCtrlGPIO\n")); */
-+	/*	dm_CheckRfCtrlGPIO(Adapter); */
-+	/* } */
-+#ifdef CONFIG_SUPPORT_HW_WPS_PBC
-+	dm_CheckPbcGPIO(Adapter);
-+#endif
-+	return;
-+}
-+
-+void rtl8703b_init_dm_priv(PADAPTER Adapter)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+	struct dm_struct		*podmpriv = &pHalData->odmpriv;
-+	Init_ODM_ComInfo_8703b(Adapter);
-+	odm_init_all_timers(podmpriv);
-+
-+}
-+
-+void rtl8703b_deinit_dm_priv(PADAPTER Adapter)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+	struct dm_struct		*podmpriv = &pHalData->odmpriv;
-+
-+	odm_cancel_all_timers(podmpriv);
-+
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_hal_init.c b/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_hal_init.c
-new file mode 100644
-index 000000000000..dbbd42f128e8
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_hal_init.c
-@@ -0,0 +1,5565 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _HAL_INIT_C_
-+
-+#include <rtl8703b_hal.h>
-+#include "hal_com_h2c.h"
-+#include <hal_com.h>
-+#include "hal8703b_fw.h"
-+#define FW_DOWNLOAD_SIZE_8703B 8192
-+
-+static void
-+_FWDownloadEnable(
-+		PADAPTER		padapter,
-+		BOOLEAN			enable
-+)
-+{
-+	u8	tmp, count = 0;
-+
-+	if (enable) {
-+		/* 8051 enable */
-+		tmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
-+		rtw_write8(padapter, REG_SYS_FUNC_EN + 1, tmp | 0x04);
-+
-+		tmp = rtw_read8(padapter, REG_MCUFWDL);
-+		rtw_write8(padapter, REG_MCUFWDL, tmp | 0x01);
-+
-+		do {
-+			tmp = rtw_read8(padapter, REG_MCUFWDL);
-+			if (tmp & 0x01)
-+				break;
-+			rtw_write8(padapter, REG_MCUFWDL, tmp | 0x01);
-+			rtw_msleep_os(1);
-+		} while (count++ < 100);
-+		if (count > 0)
-+			RTW_INFO("%s: !!!!!!!!Write 0x80 Fail!: count = %d\n", __func__, count);
-+
-+		/* 8051 reset */
-+		tmp = rtw_read8(padapter, REG_MCUFWDL + 2);
-+		rtw_write8(padapter, REG_MCUFWDL + 2, tmp & 0xf7);
-+	} else {
-+		/* MCU firmware download disable. */
-+		tmp = rtw_read8(padapter, REG_MCUFWDL);
-+		rtw_write8(padapter, REG_MCUFWDL, tmp & 0xfe);
-+	}
-+}
-+
-+static int
-+_BlockWrite(
-+			PADAPTER	padapter,
-+			void			*buffer,
-+			u32			buffSize
-+)
-+{
-+	int ret = _SUCCESS;
-+
-+	u32			blockSize_p1 = 4;	/* (Default) Phase #1 : PCI muse use 4-byte write to download FW */
-+	u32			blockSize_p2 = 8;	/* Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */
-+	u32			blockSize_p3 = 1;	/* Phase #3 : Use 1-byte, the remnant of FW image. */
-+	u32			blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;
-+	u32			remainSize_p1 = 0, remainSize_p2 = 0;
-+	u8			*bufferPtr	= (u8 *)buffer;
-+	u32			i = 0, offset = 0;
-+#ifdef CONFIG_PCI_HCI
-+	u8			remainFW[4] = {0, 0, 0, 0};
-+	u8			*p = NULL;
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	blockSize_p1 = 254;
-+#endif
-+
-+	/*	printk("====>%s %d\n", __func__, __LINE__); */
-+
-+	/* 3 Phase #1 */
-+	blockCount_p1 = buffSize / blockSize_p1;
-+	remainSize_p1 = buffSize % blockSize_p1;
-+
-+
-+
-+	for (i = 0; i < blockCount_p1; i++) {
-+#ifdef CONFIG_USB_HCI
-+		ret = rtw_writeN(padapter, (FW_8703B_START_ADDRESS + i * blockSize_p1), blockSize_p1, (bufferPtr + i * blockSize_p1));
-+#else
-+		ret = rtw_write32(padapter, (FW_8703B_START_ADDRESS + i * blockSize_p1), le32_to_cpu(*((u32 *)(bufferPtr + i * blockSize_p1))));
-+#endif
-+		if (ret == _FAIL) {
-+			printk("====>%s %d i:%d\n", __func__, __LINE__, i);
-+			goto exit;
-+		}
-+	}
-+
-+#ifdef CONFIG_PCI_HCI
-+	p = (u8 *)((u32 *)(bufferPtr + blockCount_p1 * blockSize_p1));
-+	if (remainSize_p1) {
-+		switch (remainSize_p1) {
-+		case 0:
-+			break;
-+		case 3:
-+			remainFW[2] = *(p + 2);
-+		case 2:
-+			remainFW[1] = *(p + 1);
-+		case 1:
-+			remainFW[0] = *(p);
-+			ret = rtw_write32(padapter, (FW_8703B_START_ADDRESS + blockCount_p1 * blockSize_p1),
-+					  le32_to_cpu(*(u32 *)remainFW));
-+		}
-+		return ret;
-+	}
-+#endif
-+
-+	/* 3 Phase #2 */
-+	if (remainSize_p1) {
-+		offset = blockCount_p1 * blockSize_p1;
-+
-+		blockCount_p2 = remainSize_p1 / blockSize_p2;
-+		remainSize_p2 = remainSize_p1 % blockSize_p2;
-+
-+
-+
-+#ifdef CONFIG_USB_HCI
-+		for (i = 0; i < blockCount_p2; i++) {
-+			ret = rtw_writeN(padapter, (FW_8703B_START_ADDRESS + offset + i * blockSize_p2), blockSize_p2, (bufferPtr + offset + i * blockSize_p2));
-+
-+			if (ret == _FAIL)
-+				goto exit;
-+		}
-+#endif
-+	}
-+
-+	/* 3 Phase #3 */
-+	if (remainSize_p2) {
-+		offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2);
-+
-+		blockCount_p3 = remainSize_p2 / blockSize_p3;
-+
-+
-+		for (i = 0 ; i < blockCount_p3 ; i++) {
-+			ret = rtw_write8(padapter, (FW_8703B_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
-+
-+			if (ret == _FAIL) {
-+				printk("====>%s %d i:%d\n", __func__, __LINE__, i);
-+				goto exit;
-+			}
-+		}
-+	}
-+exit:
-+	return ret;
-+}
-+
-+static int
-+_PageWrite(
-+			PADAPTER	padapter,
-+			u32			page,
-+			void			*buffer,
-+			u32			size
-+)
-+{
-+	u8 value8;
-+	u8 u8Page = (u8)(page & 0x07) ;
-+
-+	value8 = (rtw_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | u8Page ;
-+	rtw_write8(padapter, REG_MCUFWDL + 2, value8);
-+
-+	return _BlockWrite(padapter, buffer, size);
-+}
-+#ifdef CONFIG_PCI_HCI
-+static void
-+_FillDummy(
-+	u8		*pFwBuf,
-+	u32	*pFwLen
-+)
-+{
-+	u32	FwLen = *pFwLen;
-+	u8	remain = (u8)(FwLen % 4);
-+	remain = (remain == 0) ? 0 : (4 - remain);
-+
-+	while (remain > 0) {
-+		pFwBuf[FwLen] = 0;
-+		FwLen++;
-+		remain--;
-+	}
-+
-+	*pFwLen = FwLen;
-+}
-+#endif
-+static int
-+_WriteFW(
-+			PADAPTER	padapter,
-+			void			*buffer,
-+			u32			size
-+)
-+{
-+	/* Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */
-+	int ret = _SUCCESS;
-+	u32	pageNums, remainSize ;
-+	u32	page, offset;
-+	u8		*bufferPtr = (u8 *)buffer;
-+
-+#ifdef CONFIG_PCI_HCI
-+	/* 20100120 Joseph: Add for 88CE normal chip. */
-+	/* Fill in zero to make firmware image to dword alignment. */
-+	_FillDummy(bufferPtr, &size);
-+#endif
-+
-+	pageNums = size / MAX_DLFW_PAGE_SIZE ;
-+	/* RT_ASSERT((pageNums <= 4), ("Page numbers should not greater then 4\n")); */
-+	remainSize = size % MAX_DLFW_PAGE_SIZE;
-+
-+	for (page = 0; page < pageNums; page++) {
-+		offset = page * MAX_DLFW_PAGE_SIZE;
-+		ret = _PageWrite(padapter, page, bufferPtr + offset, MAX_DLFW_PAGE_SIZE);
-+
-+		if (ret == _FAIL) {
-+			printk("====>%s %d\n", __func__, __LINE__);
-+			goto exit;
-+		}
-+	}
-+	if (remainSize) {
-+		offset = pageNums * MAX_DLFW_PAGE_SIZE;
-+		page = pageNums;
-+		ret = _PageWrite(padapter, page, bufferPtr + offset, remainSize);
-+
-+		if (ret == _FAIL) {
-+			printk("====>%s %d\n", __func__, __LINE__);
-+			goto exit;
-+		}
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+void _8051Reset8703(PADAPTER padapter)
-+{
-+	u8 cpu_rst;
-+	u8 io_rst;
-+
-+#if 0
-+	io_rst = rtw_read8(padapter, REG_RSV_CTRL);
-+	rtw_write8(padapter, REG_RSV_CTRL, io_rst & (~BIT1));
-+#endif
-+
-+	/* Reset 8051(WLMCU) IO wrapper */
-+	/* 0x1c[8] = 0 */
-+	/* Suggested by Isaac@SD1 and Gimmy@SD1, coding by Lucas@20130624 */
-+	io_rst = rtw_read8(padapter, REG_RSV_CTRL + 1);
-+	io_rst &= ~BIT(0);
-+	rtw_write8(padapter, REG_RSV_CTRL + 1, io_rst);
-+
-+	cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
-+	cpu_rst &= ~BIT(2);
-+	rtw_write8(padapter, REG_SYS_FUNC_EN + 1, cpu_rst);
-+
-+#if 0
-+	io_rst = rtw_read8(padapter, REG_RSV_CTRL);
-+	rtw_write8(padapter, REG_RSV_CTRL, io_rst & (~BIT1));
-+#endif
-+
-+	/* Enable 8051 IO wrapper	 */
-+	/* 0x1c[8] = 1 */
-+	io_rst = rtw_read8(padapter, REG_RSV_CTRL + 1);
-+	io_rst |= BIT(0);
-+	rtw_write8(padapter, REG_RSV_CTRL + 1, io_rst);
-+
-+	cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
-+	cpu_rst |= BIT(2);
-+	rtw_write8(padapter, REG_SYS_FUNC_EN + 1, cpu_rst);
-+
-+	RTW_INFO("%s: Finish\n", __FUNCTION__);
-+}
-+
-+static s32 polling_fwdl_chksum(_adapter *adapter, u32 min_cnt, u32 timeout_ms)
-+{
-+	s32 ret = _FAIL;
-+	u32 value32;
-+	systime start = rtw_get_current_time();
-+	u32 cnt = 0;
-+
-+	/* polling CheckSum report */
-+	do {
-+		cnt++;
-+		value32 = rtw_read32(adapter, REG_MCUFWDL);
-+		if (value32 & FWDL_ChkSum_rpt || RTW_CANNOT_IO(adapter))
-+			break;
-+		rtw_yield_os();
-+	} while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
-+
-+	if (!(value32 & FWDL_ChkSum_rpt))
-+		goto exit;
-+
-+	if (rtw_fwdl_test_trigger_chksum_fail())
-+		goto exit;
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	RTW_INFO("%s: Checksum report %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", __FUNCTION__
-+		, (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), value32);
-+
-+	return ret;
-+}
-+
-+static s32 _FWFreeToGo(_adapter *adapter, u32 min_cnt, u32 timeout_ms)
-+{
-+	s32 ret = _FAIL;
-+	u32	value32;
-+	systime start = rtw_get_current_time();
-+	u32 cnt = 0;
-+	u32 value_to_check = 0;
-+	u32 value_expected = (MCUFWDL_RDY | FWDL_ChkSum_rpt | WINTINI_RDY | RAM_DL_SEL);
-+
-+	value32 = rtw_read32(adapter, REG_MCUFWDL);
-+	value32 |= MCUFWDL_RDY;
-+	value32 &= ~WINTINI_RDY;
-+	rtw_write32(adapter, REG_MCUFWDL, value32);
-+
-+	_8051Reset8703(adapter);
-+
-+	/*  polling for FW ready */
-+	do {
-+		cnt++;
-+		value32 = rtw_read32(adapter, REG_MCUFWDL);
-+		value_to_check = value32 & value_expected;
-+		if ((value_to_check == value_expected) || RTW_CANNOT_IO(adapter))
-+			break;
-+		rtw_yield_os();
-+	} while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
-+
-+	if (value_to_check != value_expected)
-+		goto exit;
-+
-+	if (rtw_fwdl_test_trigger_wintint_rdy_fail())
-+		goto exit;
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	RTW_INFO("%s: Polling FW ready %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", __FUNCTION__
-+		, (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), value32);
-+
-+	return ret;
-+}
-+
-+#define IS_FW_81xxC(padapter)	(((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
-+
-+void rtl8703b_FirmwareSelfReset(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	u8	u1bTmp;
-+	u8	Delay = 100;
-+
-+	if (!(IS_FW_81xxC(padapter) &&
-+	      ((pHalData->firmware_version < 0x21) ||
-+	       (pHalData->firmware_version == 0x21 &&
-+		pHalData->firmware_sub_version < 0x01)))) { /* after 88C Fw v33.1 */
-+		/* 0x1cf=0x20. Inform 8051 to reset. 2009.12.25. tynli_test */
-+		rtw_write8(padapter, REG_HMETFR + 3, 0x20);
-+
-+		u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
-+		while (u1bTmp & BIT2) {
-+			Delay--;
-+			if (Delay == 0)
-+				break;
-+			rtw_udelay_os(50);
-+			u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
-+		}
-+
-+		if (Delay == 0) {
-+			/* force firmware reset */
-+			u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
-+			rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp & (~BIT2));
-+		}
-+	}
-+}
-+
-+#ifdef CONFIG_FILE_FWIMG
-+	extern char *rtw_fw_file_path;
-+	extern char *rtw_fw_wow_file_path;
-+	#ifdef CONFIG_MP_INCLUDED
-+		extern char *rtw_fw_mp_bt_file_path;
-+	#endif /* CONFIG_MP_INCLUDED */
-+	u8 FwBuffer[FW_8703B_SIZE];
-+#endif /* CONFIG_FILE_FWIMG */
-+
-+#ifdef CONFIG_MP_INCLUDED
-+int _WriteBTFWtoTxPktBuf8703B(
-+			PADAPTER	Adapter,
-+			void			*buffer,
-+			u32			FwBufLen,
-+			u8			times
-+)
-+{
-+	int			rtStatus = _SUCCESS;
-+	/* u32				value32; */
-+	/* u8				numHQ, numLQ, numPubQ; */ /* , txpktbuf_bndy; */
-+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
-+	/* PMGNT_INFO		pMgntInfo = &(Adapter->MgntInfo); */
-+	u8				BcnValidReg;
-+	u8				count = 0, DLBcnCount = 0;
-+	u8 *FwbufferPtr = (u8 *)buffer;
-+	/* PRT_TCB 			pTcb, ptempTcb; */
-+	/* PRT_TX_LOCAL_BUFFER pBuf; */
-+
-+	u8 *ReservedPagePacket = NULL;
-+	u8 *pGenBufReservedPagePacket = NULL;
-+	u32				TotalPktLen, txpktbuf_bndy;
-+	/* u8				tmpReg422; */
-+	/* u8				u1bTmp; */
-+	u8			*pframe;
-+	struct xmit_priv	*pxmitpriv = &(Adapter->xmitpriv);
-+	struct xmit_frame	*pmgntframe;
-+	struct pkt_attrib	*pattrib;
-+	u8			txdesc_offset = TXDESC_OFFSET;
-+	u8			val8, RegFwHwTxQCtrl;
-+#ifdef CONFIG_PCI_HCI
-+	u8			u1bTmp;
-+#endif
-+
-+#if 1/* #ifdef CONFIG_PCI_HCI */
-+	TotalPktLen = FwBufLen;
-+#else
-+	TotalPktLen = FwBufLen + pHalData->HWDescHeadLength;
-+#endif
-+
-+	if ((TotalPktLen + TXDESC_OFFSET) > MAX_CMDBUF_SZ) {
-+		RTW_INFO(" WARNING %s => Total packet len = %d > MAX_CMDBUF_SZ:%d\n"
-+			, __FUNCTION__, (TotalPktLen + TXDESC_OFFSET), MAX_CMDBUF_SZ);
-+		return _FAIL;
-+	}
-+
-+	pGenBufReservedPagePacket = rtw_zmalloc(TotalPktLen);/* GetGenTempBuffer (Adapter, TotalPktLen); */
-+	if (!pGenBufReservedPagePacket)
-+		return _FAIL;
-+
-+	ReservedPagePacket = (u8 *)pGenBufReservedPagePacket;
-+
-+	_rtw_memset(ReservedPagePacket, 0, TotalPktLen);
-+
-+#if 1/* #ifdef CONFIG_PCI_HCI */
-+	_rtw_memcpy(ReservedPagePacket, FwbufferPtr, FwBufLen);
-+
-+#else
-+	PlatformMoveMemory(ReservedPagePacket + Adapter->HWDescHeadLength , FwbufferPtr, FwBufLen);
-+#endif
-+
-+	/* --------------------------------------------------------- */
-+	/* 1. Pause BCN */
-+	/* --------------------------------------------------------- */
-+	/* Set REG_CR bit 8. DMA beacon by SW. */
-+#ifdef CONFIG_PCI_HCI
-+	u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR + 1);
-+	PlatformEFIOWrite1Byte(Adapter,  REG_CR + 1, (u1bTmp | BIT0));
-+#else
-+	/* Remove for temparaily because of the code on v2002 is not sync to MERGE_TMEP for USB/SDIO. */
-+	/* De not remove this part on MERGE_TEMP. by tynli. */
-+#endif
-+
-+	/* Disable Hw protection for a time which revserd for Hw sending beacon. */
-+	/* Fix download reserved page packet fail that access collision with the protection time. */
-+	/* 2010.05.11. Added by tynli. */
-+	val8 = rtw_read8(Adapter, REG_BCN_CTRL);
-+	val8 &= ~EN_BCN_FUNCTION;
-+	val8 |= DIS_TSF_UDT;
-+	rtw_write8(Adapter, REG_BCN_CTRL, val8);
-+
-+#if 0/* #ifdef CONFIG_PCI_HCI */
-+	tmpReg422 = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2);
-+	if (tmpReg422 & BIT6)
-+		bRecover = TRUE;
-+	PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2,  tmpReg422 & (~BIT6));
-+#else
-+	/* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */
-+	RegFwHwTxQCtrl = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2);
-+	PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2, RegFwHwTxQCtrl & (~BIT6));
-+#endif
-+
-+	/* --------------------------------------------------------- */
-+	/* 2. Adjust LLT table to an even boundary. */
-+	/* --------------------------------------------------------- */
-+#if 0/* #ifdef CONFIG_SDIO_HCI */
-+	txpktbuf_bndy = 10; /* rsvd page start address should be an even value.														 */
-+	rtStatus =	InitLLTTable8703BS(Adapter, txpktbuf_bndy);
-+	if (RT_STATUS_SUCCESS != rtStatus) {
-+		RTW_INFO("_CheckWLANFwPatchBTFwReady_8703B(): Failed to init LLT!\n");
-+		return RT_STATUS_FAILURE;
-+	}
-+
-+	/* Init Tx boundary. */
-+	PlatformEFIOWrite1Byte(Adapter, REG_DWBCN0_CTRL_8703B + 1, (u8)txpktbuf_bndy);
-+#endif
-+
-+
-+	/* --------------------------------------------------------- */
-+	/* 3. Write Fw to Tx packet buffer by reseverd page. */
-+	/* --------------------------------------------------------- */
-+	do {
-+		/* download rsvd page. */
-+		/* Clear beacon valid check bit. */
-+		BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2);
-+		PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 2, BcnValidReg & (~BIT(0)));
-+
-+		/* BT patch is big, we should set 0x209 < 0x40 suggested from Gimmy */
-+
-+		PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 1, (0x90 - 0x20 * (times - 1)));
-+		RTW_INFO("0x209:0x%x\n", PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 1));
-+
-+#if 0
-+		/* Acquice TX spin lock before GetFwBuf and send the packet to prevent system deadlock. */
-+		/* Advertised by Roger. Added by tynli. 2010.02.22. */
-+		PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
-+		if (MgntGetFWBuffer(Adapter, &pTcb, &pBuf)) {
-+			PlatformMoveMemory(pBuf->Buffer.VirtualAddress, ReservedPagePacket, TotalPktLen);
-+			CmdSendPacket(Adapter, pTcb, pBuf, TotalPktLen, DESC_PACKET_TYPE_NORMAL, FALSE);
-+		} else
-+			dbgdump("SetFwRsvdPagePkt(): MgntGetFWBuffer FAIL!!!!!!!!.\n");
-+		PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
-+#else
-+		/*---------------------------------------------------------
-+		tx reserved_page_packet
-+		----------------------------------------------------------*/
-+		pmgntframe = rtw_alloc_cmdxmitframe(pxmitpriv);
-+		if (pmgntframe == NULL) {
-+			rtStatus = _FAIL;
-+			goto exit;
-+		}
-+		/* update attribute */
-+		pattrib = &pmgntframe->attrib;
-+		update_mgntframe_attrib(Adapter, pattrib);
-+
-+		pattrib->qsel = QSLT_BEACON;
-+		pattrib->pktlen = pattrib->last_txcmdsz = FwBufLen ;
-+
-+		/* _rtw_memset(pmgntframe->buf_addr, 0, TotalPktLen+txdesc_size); */
-+		/* pmgntframe->buf_addr = ReservedPagePacket ; */
-+
-+		_rtw_memcpy((u8 *)(pmgntframe->buf_addr + txdesc_offset), ReservedPagePacket, FwBufLen);
-+		RTW_INFO("[%d]===>TotalPktLen + TXDESC_OFFSET TotalPacketLen:%d\n", DLBcnCount, (FwBufLen + txdesc_offset));
-+
-+#ifdef CONFIG_PCI_HCI
-+		dump_mgntframe(Adapter, pmgntframe);
-+#else
-+		dump_mgntframe_and_wait(Adapter, pmgntframe, 100);
-+#endif
-+
-+#endif
-+#if 1
-+		/* check rsvd page download OK. */
-+		BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2);
-+		while (!(BcnValidReg & BIT(0)) && count < 200) {
-+			count++;
-+			/* PlatformSleepUs(10); */
-+			rtw_msleep_os(1);
-+			BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2);
-+		}
-+		DLBcnCount++;
-+		/* RTW_INFO("##0x208:%08x,0x210=%08x\n",PlatformEFIORead4Byte(Adapter, REG_TDECTRL),PlatformEFIORead4Byte(Adapter, 0x210)); */
-+
-+		PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 2, BcnValidReg);
-+
-+	} while ((!(BcnValidReg & BIT(0))) && DLBcnCount < 5);
-+
-+
-+#endif
-+	if (DLBcnCount >= 5) {
-+		RTW_INFO(" check rsvd page download OK DLBcnCount =%d\n", DLBcnCount);
-+		rtStatus = _FAIL;
-+		goto exit;
-+	}
-+
-+	if (!(BcnValidReg & BIT(0))) {
-+		RTW_INFO("_WriteFWtoTxPktBuf(): 1 Download RSVD page failed!\n");
-+		rtStatus = _FAIL;
-+		goto exit;
-+	}
-+
-+	/* --------------------------------------------------------- */
-+	/* 4. Set Tx boundary to the initial value */
-+	/* --------------------------------------------------------- */
-+
-+
-+	/* --------------------------------------------------------- */
-+	/* 5. Reset beacon setting to the initial value. */
-+	/*	 After _CheckWLANFwPatchBTFwReady(). */
-+	/* --------------------------------------------------------- */
-+
-+exit:
-+
-+	if (pGenBufReservedPagePacket) {
-+		RTW_INFO("_WriteBTFWtoTxPktBuf8703B => rtw_mfree pGenBufReservedPagePacket!\n");
-+		rtw_mfree((u8 *)pGenBufReservedPagePacket, TotalPktLen);
-+	}
-+	return rtStatus;
-+}
-+
-+
-+
-+/*
-+ * Description: Determine the contents of H2C BT_FW_PATCH Command sent to FW.
-+ * 2011.10.20 by tynli
-+ *   */
-+void
-+SetFwBTFwPatchCmd(
-+	PADAPTER	Adapter,
-+	u16		FwSize
-+)
-+{
-+	u8 u1BTFwPatchParm[H2C_BT_FW_PATCH_LEN] = {0};
-+	u8 addr0 = 0;
-+	u8 addr1 = 0xa0;
-+	u8 addr2 = 0x10;
-+	u8 addr3 = 0x80;
-+
-+
-+	SET_8703B_H2CCMD_BT_FW_PATCH_SIZE(u1BTFwPatchParm, FwSize);
-+	SET_8703B_H2CCMD_BT_FW_PATCH_ADDR0(u1BTFwPatchParm, addr0);
-+	SET_8703B_H2CCMD_BT_FW_PATCH_ADDR1(u1BTFwPatchParm, addr1);
-+	SET_8703B_H2CCMD_BT_FW_PATCH_ADDR2(u1BTFwPatchParm, addr2);
-+	SET_8703B_H2CCMD_BT_FW_PATCH_ADDR3(u1BTFwPatchParm, addr3);
-+
-+	FillH2CCmd8703B(Adapter, H2C_8703B_BT_FW_PATCH, H2C_BT_FW_PATCH_LEN, u1BTFwPatchParm);
-+
-+}
-+
-+void
-+SetFwBTPwrCmd(
-+	PADAPTER	Adapter,
-+	u8	PwrIdx
-+)
-+{
-+	u8		u1BTPwrIdxParm[H2C_FORCE_BT_TXPWR_LEN] = {0};
-+
-+	SET_8703B_H2CCMD_BT_PWR_IDX(u1BTPwrIdxParm, PwrIdx);
-+
-+
-+	FillH2CCmd8703B(Adapter, H2C_8703B_FORCE_BT_TXPWR, H2C_FORCE_BT_TXPWR_LEN, u1BTPwrIdxParm);
-+}
-+
-+/*
-+ * Description: WLAN Fw will write BT Fw to BT XRAM and signal driver.
-+ *
-+ * 2011.10.20. by tynli.
-+ *   */
-+int
-+_CheckWLANFwPatchBTFwReady(
-+	PADAPTER Adapter,
-+	BOOLEAN bRecover
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	u32	count = 0;
-+	u8	u1bTmp;
-+	int ret = _FAIL;
-+
-+	/* --------------------------------------------------------- */
-+	/* Check if BT FW patch procedure is ready. */
-+	/* --------------------------------------------------------- */
-+	do {
-+		u1bTmp = PlatformEFIORead1Byte(Adapter, REG_HMEBOX_DBG_0_8703B);
-+		if ((u1bTmp & BIT6) || (u1bTmp & BIT7)) {
-+			ret = _SUCCESS;
-+			break;
-+		}
-+
-+		count++;
-+		rtw_msleep_os(50); /* 50ms */
-+	} while (!((u1bTmp & BIT6) || (u1bTmp & BIT7)) && count < 50);
-+
-+
-+
-+
-+	/* --------------------------------------------------------- */
-+	/* Reset beacon setting to the initial value. */
-+	/* --------------------------------------------------------- */
-+#if 0/* #ifdef CONFIG_PCI_HCI */
-+	if (LLT_table_init(Adapter, FALSE, 0) == RT_STATUS_FAILURE) {
-+		dbgdump("Init self define for BT Fw patch LLT table fail.\n");
-+		/* return RT_STATUS_FAILURE; */
-+	}
-+#endif
-+	u1bTmp = rtw_read8(Adapter, REG_BCN_CTRL);
-+	u1bTmp |= EN_BCN_FUNCTION;
-+	u1bTmp &= ~DIS_TSF_UDT;
-+	rtw_write8(Adapter, REG_BCN_CTRL, u1bTmp);
-+
-+	/* To make sure that if there exists an adapter which would like to send beacon. */
-+	/* If exists, the origianl value of 0x422[6] will be 1, we should check this to */
-+	/* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
-+	/* the beacon cannot be sent by HW. */
-+	/* 2010.06.23. Added by tynli. */
-+	if (bRecover) {
-+		u1bTmp = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2);
-+		PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2, (u1bTmp | BIT6));
-+	}
-+
-+	/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
-+	u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR + 1);
-+	PlatformEFIOWrite1Byte(Adapter, REG_CR + 1, (u1bTmp & (~BIT0)));
-+
-+	return ret;
-+}
-+
-+int ReservedPage_Compare(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware, u32 BTPatchSize)
-+{
-+	u8 temp, ret, lastBTsz;
-+	u32 u1bTmp = 0, address_start = 0, count = 0, i = 0;
-+	u8	*myBTFwBuffer = NULL;
-+
-+	myBTFwBuffer = rtw_zmalloc(BTPatchSize);
-+	if (myBTFwBuffer == NULL) {
-+		RTW_INFO("%s can't be executed due to the failed malloc.\n", __FUNCTION__);
-+		Adapter->mppriv.bTxBufCkFail = _TRUE;
-+		return _FALSE;
-+	}
-+
-+	temp = rtw_read8(Adapter, 0x209);
-+
-+	address_start = (temp * 128) / 8;
-+
-+	rtw_write32(Adapter, 0x140, 0x00000000);
-+	rtw_write32(Adapter, 0x144, 0x00000000);
-+	rtw_write32(Adapter, 0x148, 0x00000000);
-+
-+	rtw_write8(Adapter, 0x106, 0x69);
-+
-+	for (i = 0; i < (BTPatchSize / 8); i++) {
-+		rtw_write32(Adapter, 0x140, address_start + 5 + i) ;
-+
-+		/* polling until reg 0x140[23]=1; */
-+		do {
-+			u1bTmp = rtw_read32(Adapter, 0x140);
-+			if (u1bTmp & BIT(23)) {
-+				ret = _SUCCESS;
-+				break;
-+			}
-+			count++;
-+			RTW_INFO("0x140=%x, wait for 10 ms (%d) times.\n", u1bTmp, count);
-+			rtw_msleep_os(10); /* 10ms */
-+		} while (!(u1bTmp & BIT(23)) && count < 50);
-+
-+		myBTFwBuffer[i * 8 + 0] = rtw_read8(Adapter, 0x144);
-+		myBTFwBuffer[i * 8 + 1] = rtw_read8(Adapter, 0x145);
-+		myBTFwBuffer[i * 8 + 2] = rtw_read8(Adapter, 0x146);
-+		myBTFwBuffer[i * 8 + 3] = rtw_read8(Adapter, 0x147);
-+		myBTFwBuffer[i * 8 + 4] = rtw_read8(Adapter, 0x148);
-+		myBTFwBuffer[i * 8 + 5] = rtw_read8(Adapter, 0x149);
-+		myBTFwBuffer[i * 8 + 6] = rtw_read8(Adapter, 0x14a);
-+		myBTFwBuffer[i * 8 + 7] = rtw_read8(Adapter, 0x14b);
-+	}
-+
-+	rtw_write32(Adapter, 0x140, address_start + 5 + BTPatchSize / 8) ;
-+
-+	lastBTsz = BTPatchSize % 8;
-+
-+	/* polling until reg 0x140[23]=1; */
-+	u1bTmp = 0;
-+	count = 0;
-+	do {
-+		u1bTmp = rtw_read32(Adapter, 0x140);
-+		if (u1bTmp & BIT(23)) {
-+			ret = _SUCCESS;
-+			break;
-+		}
-+		count++;
-+		RTW_INFO("0x140=%x, wait for 10 ms (%d) times.\n", u1bTmp, count);
-+		rtw_msleep_os(10); /* 10ms */
-+	} while (!(u1bTmp & BIT(23)) && count < 50);
-+
-+	for (i = 0; i < lastBTsz; i++)
-+		myBTFwBuffer[(BTPatchSize / 8) * 8 + i] = rtw_read8(Adapter, (0x144 + i));
-+
-+
-+	for (i = 0; i < BTPatchSize; i++) {
-+		if (myBTFwBuffer[i] != pFirmware->szFwBuffer[i]) {
-+			RTW_INFO(" In direct myBTFwBuffer[%d]=%x , pFirmware->szFwBuffer=%x\n", i, myBTFwBuffer[i], pFirmware->szFwBuffer[i]);
-+			Adapter->mppriv.bTxBufCkFail = _TRUE;
-+			break;
-+		}
-+	}
-+
-+	if (myBTFwBuffer != NULL)
-+		rtw_mfree(myBTFwBuffer, BTPatchSize);
-+
-+	return _TRUE;
-+}
-+
-+/* As the size of bt firmware is more than 16k which is too big for some platforms, we divide it
-+ * into four parts to transfer. The last parameter of _WriteBTFWtoTxPktBuf8703B is used to indicate
-+ * the location of every part. We call the first 4096 byte of bt firmware as part 1, the second 4096
-+ * part as part 2, the third 4096 part as part 3, the remain as part 4. First we transform the part
-+ * 4 and set the register 0x209 to 0x90, then the 32 bytes description are added to the head of part
-+ * 4, and those bytes are putted at the location 0x90. Second we transform the part 3 and set the
-+ * register 0x209 to 0x70. The 32 bytes description and part 3(4196 bytes) are putted at the location
-+ * 0x70. It can contain 4196 bytes between 0x70 and 0x90. So the last 32 bytes os part 3 will cover the
-+ * 32 bytes description of part4. Using this method, we can put the whole bt firmware to 0x30 and only
-+ * has 32 bytes descrption at the head of part 1.
-+*/
-+s32 FirmwareDownloadBT(PADAPTER padapter, PRT_MP_FIRMWARE pFirmware)
-+{
-+	s32 rtStatus;
-+	u8 *pBTFirmwareBuf;
-+	u32 BTFirmwareLen;
-+	u8 download_time;
-+	s8 i;
-+	BOOLEAN bRecover = _FALSE;
-+
-+	rtStatus = _SUCCESS;
-+	pBTFirmwareBuf = NULL;
-+	BTFirmwareLen = 0;
-+
-+#if 0
-+	/*  */
-+	/* Patch BT Fw. Download BT RAM code to Tx packet buffer. */
-+	/*  */
-+	if (padapter->bBTFWReady) {
-+		RTW_INFO("%s: BT Firmware is ready!!\n", __FUNCTION__);
-+		return _FAIL;
-+	}
-+
-+#ifdef CONFIG_FILE_FWIMG
-+	if (rtw_is_file_readable(rtw_fw_mp_bt_file_path) == _TRUE) {
-+		RTW_INFO("%s: accquire MP BT FW from file:%s\n", __FUNCTION__, rtw_fw_mp_bt_file_path);
-+
-+		rtStatus = rtw_retrieve_from_file(rtw_fw_mp_bt_file_path, FwBuffer, FW_8703B_SIZE);
-+		BTFirmwareLen = rtStatus >= 0 ? rtStatus : 0;
-+		pBTFirmwareBuf = FwBuffer;
-+	} else
-+#endif /* CONFIG_FILE_FWIMG */
-+	{
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+		RTW_INFO("%s: Download MP BT FW from header\n", __FUNCTION__);
-+
-+		pBTFirmwareBuf = (u8 *)Rtl8703BFwBTImgArray;
-+		BTFirmwareLen = Rtl8703BFwBTImgArrayLength;
-+		pFirmware->szFwBuffer = pBTFirmwareBuf;
-+		pFirmware->ulFwLength = BTFirmwareLen;
-+#endif /* CONFIG_EMBEDDED_FWIMG */
-+	}
-+
-+	RTW_INFO("%s: MP BT Firmware size=%d\n", __FUNCTION__, BTFirmwareLen);
-+
-+	/* for h2c cam here should be set to  true */
-+	GET_HAL_DATA(padapter)->bFWReady = _TRUE;
-+
-+	download_time = (BTFirmwareLen + 4095) / 4096;
-+	RTW_INFO("%s: download_time is %d\n", __FUNCTION__, download_time);
-+
-+	if (PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2) & BIT6)
-+		bRecover = TRUE;
-+
-+	/* Download BT patch Fw. */
-+	for (i = (download_time - 1); i >= 0; i--) {
-+		if (i == (download_time - 1)) {
-+			rtStatus = _WriteBTFWtoTxPktBuf8703B(padapter, pBTFirmwareBuf + (4096 * i), (BTFirmwareLen - (4096 * i)), 1);
-+			RTW_INFO("%s: start %d, len %d, time 1\n", __FUNCTION__, 4096 * i, BTFirmwareLen - (4096 * i));
-+		} else {
-+			rtStatus = _WriteBTFWtoTxPktBuf8703B(padapter, pBTFirmwareBuf + (4096 * i), 4096, (download_time - i));
-+			RTW_INFO("%s: start %d, len 4096, time %d\n", __FUNCTION__, 4096 * i, download_time - i);
-+		}
-+
-+		if (rtStatus != _SUCCESS) {
-+			RTW_INFO("%s: BT Firmware download to Tx packet buffer fail!\n", __FUNCTION__);
-+			padapter->bBTFWReady = _FALSE;
-+			return rtStatus;
-+		}
-+	}
-+
-+	ReservedPage_Compare(padapter, pFirmware, BTFirmwareLen);
-+
-+	padapter->bBTFWReady = _TRUE;
-+	SetFwBTFwPatchCmd(padapter, (u16)BTFirmwareLen);
-+	rtStatus = _CheckWLANFwPatchBTFwReady(padapter, bRecover);
-+
-+	RTW_INFO("<===%s: return %s!\n", __FUNCTION__, rtStatus == _SUCCESS ? "SUCCESS" : "FAIL");
-+#endif
-+
-+	return rtStatus;
-+}
-+#endif /* CONFIG_MP_INCLUDED */
-+
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+void rtl8703b_cal_txdesc_chksum(struct tx_desc *ptxdesc)
-+{
-+	u16	*usPtr = (u16 *)ptxdesc;
-+	u32 count;
-+	u32 index;
-+	u16 checksum = 0;
-+
-+
-+	/* Clear first */
-+	ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
-+
-+	/* checksume is always calculated by first 32 bytes, */
-+	/* and it doesn't depend on TX DESC length. */
-+	/* Thomas,Lucas@SD4,20130515 */
-+	count = 16;
-+
-+	for (index = 0; index < count; index++)
-+		checksum ^= le16_to_cpu(*(usPtr + index));
-+
-+	ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff);
-+}
-+#endif
-+
-+#ifdef CONFIG_SDIO_HCI
-+u8 send_fw_packet(PADAPTER padapter, u8 *pRam_code, u32 length)
-+{
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct xmit_buf xmit_buf_tmp;
-+	struct submit_ctx sctx_tmp;
-+	u8 *pTx_data_buffer = NULL;
-+	u8 *pTmp_buffer = NULL;
-+	u32 modify_ram_size;
-+	u32 tmp_size, tmp_value;
-+	u8 value8;
-+	u32 i, counter;
-+	u8	bRet;
-+	u32	dwDataLength, writeLength;
-+
-+	/* Due to SDIO can not send 32K packet */
-+	if (FW_DOWNLOAD_SIZE_8703B == length)
-+		length--;
-+
-+	modify_ram_size = length << 2;
-+	pTx_data_buffer = rtw_zmalloc(modify_ram_size);
-+
-+	if (NULL == pTx_data_buffer) {
-+		RTW_INFO("Allocate buffer fail!!\n");
-+		return _FALSE;
-+	}
-+
-+	_rtw_memset(pTx_data_buffer, 0, modify_ram_size);
-+
-+	/* Transfer to new format */
-+	tmp_size = length >> 1;
-+	for (i = 0; i <= tmp_size; i++) {
-+		*(pTx_data_buffer + i * 8) = *(pRam_code + i * 2);
-+		*(pTx_data_buffer + i * 8 + 1) = *(pRam_code + i * 2 + 1);
-+	}
-+
-+	/* Gen TX_DESC */
-+	_rtw_memset(pTx_data_buffer, 0, TXDESC_SIZE);
-+	pTmp_buffer = pTx_data_buffer;
-+#if 0
-+	pTmp_buffer->qsel = BcnQsel;
-+	pTmp_buffer->txpktsize = modify_ram_size - TXDESC_SIZE;
-+	pTmp_buffer->offset = TXDESC_SIZE;
-+#else
-+	SET_TX_DESC_QUEUE_SEL_8703B(pTmp_buffer, QSLT_BEACON);
-+	SET_TX_DESC_PKT_SIZE_8703B(pTmp_buffer, modify_ram_size - TXDESC_SIZE);
-+	SET_TX_DESC_OFFSET_8703B(pTmp_buffer, TXDESC_SIZE);
-+#endif
-+	rtl8703b_cal_txdesc_chksum((struct tx_desc *)pTmp_buffer);
-+
-+
-+	/* Send packet */
-+#if 0
-+	dwDataLength = modify_ram_size;
-+	overlap.Offset = 0;
-+	overlap.OffsetHigh = 0;
-+	overlap.hEvent = CreateEvent(NULL, FALSE, FALSE, NULL);
-+	bRet = WriteFile(HalVari.hFile_Queue[TX_BCNQ]->handle, pTx_data_buffer, dwDataLength, &writeLength, &overlap);
-+	if (WaitForSingleObject(overlap.hEvent, INFINITE) == WAIT_OBJECT_0) {
-+
-+		GetOverlappedResult(HalVari.hFile_Queue[TX_BCNQ]->handle, &overlap, &writeLength, FALSE);
-+		if (writeLength != dwDataLength) {
-+			TCHAR editbuf[100];
-+			sprintf(editbuf, "DL FW Length Err: Write length error:bRet %d writeLength %ld dwDataLength %ld, Error Code:%ld", bRet, writeLength, dwDataLength, GetLastError());
-+			AfxMessageBox(editbuf, MB_OK | MB_ICONERROR);
-+			return FALSE;
-+		}
-+	}
-+	CloseHandle(overlap.hEvent);
-+#else
-+	xmit_buf_tmp.pdata = pTx_data_buffer;
-+	xmit_buf_tmp.len = modify_ram_size;
-+	rtw_sctx_init(&sctx_tmp, 10);
-+	xmit_buf_tmp.sctx = &sctx_tmp;
-+	if (rtw_write_port(padapter, pdvobjpriv->Queue2Pipe[BCN_QUEUE_INX], xmit_buf_tmp.len, (u8 *)&xmit_buf_tmp) == _FAIL) {
-+		RTW_INFO("rtw_write_port fail\n");
-+		return _FAIL;
-+	}
-+#endif
-+
-+	/* check if DMA is OK */
-+	counter = 100;
-+	do {
-+		if (0 == counter) {
-+			RTW_INFO("DMA time out!!\n");
-+			return _FALSE;
-+		}
-+		value8 = rtw_read8(padapter, REG_DWBCN0_CTRL_8703B + 2);
-+		counter--;
-+	} while (0 == (value8 & BIT(0)));
-+
-+	rtw_write8(padapter, REG_DWBCN0_CTRL_8703B + 2, value8);
-+
-+	/* Modify ram code by IO method */
-+	tmp_value = rtw_read8(padapter, REG_MCUFWDL + 1);
-+	/* Disable DMA */
-+	rtw_write8(padapter, REG_MCUFWDL + 1, (u8)tmp_value & ~(BIT(5)));
-+	tmp_value = (tmp_value >> 6) << 1;
-+	/* Set page start address */
-+	rtw_write8(padapter, REG_MCUFWDL + 2, (rtw_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | tmp_value);
-+	tmp_size = TXDESC_SIZE >> 2; /* 10bytes */
-+#if 0
-+	IO_Func.WriteRegister(0x1000, (u16)tmp_size, pRam_code);
-+#else
-+	_BlockWrite(padapter, pRam_code, tmp_size);
-+#endif
-+
-+	if (pTmp_buffer != NULL)
-+		rtw_mfree((u8 *)pTmp_buffer, modify_ram_size);
-+
-+	return _TRUE;
-+}
-+#endif /* CONFIG_SDIO_HCI */
-+
-+/*
-+ *	Description:
-+ *		Download 8192C firmware code.
-+ *
-+ *   */
-+s32 rtl8703b_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw)
-+{
-+	s32	rtStatus = _SUCCESS;
-+	u8 write_fw = 0;
-+	systime fwdl_start_time;
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	u8			*FwImage;
-+	u32			FwImageLen;
-+	u8			*pFwImageFileName;
-+#ifdef CONFIG_WOWLAN
-+	u8			*FwImageWoWLAN;
-+	u32			FwImageWoWLANLen;
-+#endif
-+	u8			*pucMappedFile = NULL;
-+	PRT_FIRMWARE_8703B	pFirmware = NULL;
-+	PRT_8703B_FIRMWARE_HDR		pFwHdr = NULL;
-+	u8			*pFirmwareBuf;
-+	u32			FirmwareLen;
-+#ifdef CONFIG_FILE_FWIMG
-+	u8 *fwfilepath;
-+#endif /* CONFIG_FILE_FWIMG */
-+	u8			value8;
-+	u16			value16;
-+	u32			value32;
-+	u8			dma_iram_sel;
-+	u16		new_chk_sum = 0;
-+	u32		send_pkt_size, pkt_size_tmp;
-+	u32		mem_offset;
-+	u32			counter;
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+
-+
-+	pFirmware = (PRT_FIRMWARE_8703B)rtw_zmalloc(sizeof(RT_FIRMWARE_8703B));
-+
-+	if (!pFirmware) {
-+		rtStatus = _FAIL;
-+		goto exit;
-+	}
-+
-+	{
-+		u8 tmp_ps = 0, tmp_rf = 0;
-+		tmp_ps = rtw_read8(padapter, 0xa3);
-+		tmp_ps &= 0xf8;
-+		tmp_ps |= 0x02;
-+		/* 1. write 0xA3[:2:0] = 3b'010 */
-+		rtw_write8(padapter, 0xa3, tmp_ps);
-+		/* 2. read power_state = 0xA0[1:0] */
-+		tmp_ps = rtw_read8(padapter, 0xa0);
-+		tmp_ps &= 0x03;
-+		if (tmp_ps != 0x01) {
-+			RTW_INFO(FUNC_ADPT_FMT" tmp_ps=%x\n", FUNC_ADPT_ARG(padapter), tmp_ps);
-+			pdbgpriv->dbg_downloadfw_pwr_state_cnt++;
-+		}
-+	}
-+
-+#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_PreLoadFirmware(padapter);
-+#endif /* CONFIG_BT_COEXIST */
-+
-+#ifdef CONFIG_FILE_FWIMG
-+#ifdef CONFIG_WOWLAN
-+	if (bUsedWoWLANFw)
-+		fwfilepath = rtw_fw_wow_file_path;
-+	else
-+#endif /* CONFIG_WOWLAN */
-+	{
-+		fwfilepath = rtw_fw_file_path;
-+	}
-+#endif /* CONFIG_FILE_FWIMG */
-+
-+#ifdef CONFIG_FILE_FWIMG
-+	if (rtw_is_file_readable(fwfilepath) == _TRUE) {
-+		RTW_INFO("%s accquire FW from file:%s\n", __FUNCTION__, fwfilepath);
-+		pFirmware->eFWSource = FW_SOURCE_IMG_FILE;
-+	} else
-+#endif /* CONFIG_FILE_FWIMG */
-+	{
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+		pFirmware->eFWSource = FW_SOURCE_HEADER_FILE;
-+#else /* !CONFIG_EMBEDDED_FWIMG */
-+		pFirmware->eFWSource = FW_SOURCE_IMG_FILE; /* We should decided by Reg. */
-+#endif /* !CONFIG_EMBEDDED_FWIMG */
-+	}
-+
-+	switch (pFirmware->eFWSource) {
-+	case FW_SOURCE_IMG_FILE:
-+#ifdef CONFIG_FILE_FWIMG
-+		rtStatus = rtw_retrieve_from_file(fwfilepath, FwBuffer, FW_8703B_SIZE);
-+		pFirmware->ulFwLength = rtStatus >= 0 ? rtStatus : 0;
-+		pFirmware->szFwBuffer = FwBuffer;
-+#endif /* CONFIG_FILE_FWIMG */
-+		break;
-+
-+	case FW_SOURCE_HEADER_FILE:
-+		if (bUsedWoWLANFw) {
-+		#ifdef CONFIG_WOWLAN
-+			if (pwrpriv->wowlan_mode) {
-+				pFirmware->szFwBuffer = array_mp_8703b_fw_wowlan;
-+				pFirmware->ulFwLength = array_length_mp_8703b_fw_wowlan;
-+
-+				RTW_INFO(" ===> %s fw: %s, size: %d\n",
-+					 __FUNCTION__, "WoWLAN",
-+					 pFirmware->ulFwLength);
-+			}
-+		#endif /*CONFIG_WOWLAN*/
-+
-+		#ifdef CONFIG_AP_WOWLAN
-+			if (pwrpriv->wowlan_ap_mode) {
-+				pFirmware->szFwBuffer = array_mp_8703b_fw_ap;
-+				pFirmware->ulFwLength = array_length_mp_8703b_fw_ap;
-+
-+				RTW_INFO(" ===> %s fw: %s, size: %d\n",
-+					 __FUNCTION__, "AP_WoWLAN",
-+					 pFirmware->ulFwLength);
-+			}
-+		#endif /* CONFIG_AP_WOWLAN */
-+		} else {
-+			pFirmware->szFwBuffer = array_mp_8703b_fw_nic;
-+			pFirmware->ulFwLength = array_length_mp_8703b_fw_nic;
-+			RTW_INFO("%s fw: %s, size: %d\n", __FUNCTION__, "FW_NIC", pFirmware->ulFwLength);
-+		}
-+		break;
-+	}
-+
-+	if ((pFirmware->ulFwLength - 32) > FW_8703B_SIZE) {
-+		rtStatus = _FAIL;
-+		RTW_ERR("Firmware size:%u exceed %u\n", pFirmware->ulFwLength, FW_8703B_SIZE);
-+		goto exit;
-+	}
-+
-+	pFirmwareBuf = pFirmware->szFwBuffer;
-+	FirmwareLen = pFirmware->ulFwLength;
-+
-+	/* To Check Fw header. Added by tynli. 2009.12.04. */
-+	pFwHdr = (PRT_8703B_FIRMWARE_HDR)pFirmwareBuf;
-+
-+	pHalData->firmware_version =  le16_to_cpu(pFwHdr->Version);
-+	pHalData->firmware_sub_version = le16_to_cpu(pFwHdr->Subversion);
-+	pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature);
-+
-+	RTW_INFO("%s: fw_ver=%x fw_subver=%04x sig=0x%x, Month=%02x, Date=%02x, Hour=%02x, Minute=%02x\n",
-+		__FUNCTION__, pHalData->firmware_version, pHalData->firmware_sub_version, pHalData->FirmwareSignature
-+		 , pFwHdr->Month, pFwHdr->Date, pFwHdr->Hour, pFwHdr->Minute);
-+
-+	if (IS_FW_HEADER_EXIST_8703B(pFwHdr)) {
-+		RTW_INFO("%s(): Shift for fw header!\n", __FUNCTION__);
-+		/* Shift 32 bytes for FW header */
-+		pFirmwareBuf = pFirmwareBuf + 32;
-+		FirmwareLen = FirmwareLen - 32;
-+	}
-+
-+	fwdl_start_time = rtw_get_current_time();
-+
-+#if 1
-+	RTW_INFO("%s by IO write!\n", __FUNCTION__);
-+
-+
-+	/* To check if FW already exists before download FW */
-+	if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) {
-+		rtw_write8(padapter, REG_MCUFWDL, 0x00);
-+		_8051Reset8703(padapter);
-+	}
-+
-+	_FWDownloadEnable(padapter, _TRUE);
-+
-+	while (!RTW_CANNOT_IO(padapter)
-+	       && (write_fw++ < 3 || rtw_get_passing_time_ms(fwdl_start_time) < 500)) {
-+		/* reset FWDL chksum */
-+		rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL) | FWDL_ChkSum_rpt);
-+
-+		rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen);
-+		if (rtStatus != _SUCCESS)
-+			continue;
-+
-+		rtStatus = polling_fwdl_chksum(padapter, 5, 50);
-+		if (rtStatus == _SUCCESS)
-+			break;
-+	}
-+#else
-+	RTW_INFO("%s by Tx pkt write!\n", __FUNCTION__);
-+
-+	if ((rtw_read8(padapter, REG_MCUFWDL) & MCUFWDL_RDY) == 0) {
-+		/* DLFW use HIQ only */
-+		value32 = 0xFF | BIT(31);
-+		rtw_write32(padapter, REG_RQPN, value32);
-+
-+		/* Set beacon boundary to TXFIFO header */
-+		rtw_write8(padapter, REG_BCNQ_BDNY, 0);
-+		rtw_write16(padapter, REG_DWBCN0_CTRL_8703B + 1, BIT(8));
-+
-+		/* SDIO need read this register before send packet */
-+		rtw_read32(padapter, 0x10250020);
-+
-+		_FWDownloadEnable(padapter, _TRUE);
-+
-+		/* Get original check sum */
-+		new_chk_sum = *(pFirmwareBuf + FirmwareLen - 2) | ((u16)*(pFirmwareBuf + FirmwareLen - 1) << 8);
-+
-+		/* Send ram code flow */
-+		dma_iram_sel = 0;
-+		mem_offset = 0;
-+		pkt_size_tmp = FirmwareLen;
-+		while (0 != pkt_size_tmp) {
-+			if (pkt_size_tmp >= FW_DOWNLOAD_SIZE_8703B) {
-+				send_pkt_size = FW_DOWNLOAD_SIZE_8703B;
-+				/* Modify check sum value */
-+				new_chk_sum = (u16)(new_chk_sum ^ (((send_pkt_size - 1) << 2) - TXDESC_SIZE));
-+			} else {
-+				send_pkt_size = pkt_size_tmp;
-+				new_chk_sum = (u16)(new_chk_sum ^ ((send_pkt_size << 2) - TXDESC_SIZE));
-+
-+			}
-+
-+			if (send_pkt_size == pkt_size_tmp) {
-+				/* last partition packet, write new check sum to ram code file */
-+				*(pFirmwareBuf + FirmwareLen - 2) = new_chk_sum & 0xFF;
-+				*(pFirmwareBuf + FirmwareLen - 1) = (new_chk_sum & 0xFF00) >> 8;
-+			}
-+
-+			/* IRAM select */
-+			rtw_write8(padapter, REG_MCUFWDL + 1, (rtw_read8(padapter, REG_MCUFWDL + 1) & 0x3F) | (dma_iram_sel << 6));
-+			/* Enable DMA */
-+			rtw_write8(padapter, REG_MCUFWDL + 1, rtw_read8(padapter, REG_MCUFWDL + 1) | BIT(5));
-+
-+			if (_FALSE == send_fw_packet(padapter, pFirmwareBuf + mem_offset, send_pkt_size)) {
-+				RTW_INFO("%s: Send FW fail !\n", __FUNCTION__);
-+				rtStatus = _FAIL;
-+				goto DLFW_FAIL;
-+			}
-+
-+			dma_iram_sel++;
-+			mem_offset += send_pkt_size;
-+			pkt_size_tmp -= send_pkt_size;
-+		}
-+	} else {
-+		RTW_INFO("%s: Downlad FW fail since MCUFWDL_RDY is not set!\n", __FUNCTION__);
-+		rtStatus = _FAIL;
-+		goto DLFW_FAIL;
-+	}
-+#endif
-+
-+	_FWDownloadEnable(padapter, _FALSE);
-+
-+	rtStatus = _FWFreeToGo(padapter, 10, 200);
-+	if (_SUCCESS != rtStatus)
-+		goto DLFW_FAIL;
-+
-+	RTW_INFO("%s: DLFW OK !\n", __FUNCTION__);
-+
-+DLFW_FAIL:
-+	if (rtStatus == _FAIL) {
-+		/* Disable FWDL_EN */
-+		value8 = rtw_read8(padapter, REG_MCUFWDL);
-+		value8 = (value8 & ~(BIT(0)) & ~(BIT(1)));
-+		rtw_write8(padapter, REG_MCUFWDL, value8);
-+	}
-+
-+	RTW_INFO("%s %s. write_fw:%u, %dms\n"
-+		 , __FUNCTION__, (rtStatus == _SUCCESS) ? "success" : "fail"
-+		 , write_fw
-+		 , rtw_get_passing_time_ms(fwdl_start_time)
-+		);
-+
-+exit:
-+	if (pFirmware)
-+		rtw_mfree((u8 *)pFirmware, sizeof(RT_FIRMWARE_8703B));
-+
-+	rtl8703b_InitializeFirmwareVars(padapter);
-+
-+	RTW_INFO(" <=== %s()\n", __FUNCTION__);
-+
-+	return rtStatus;
-+}
-+
-+void rtl8703b_InitializeFirmwareVars(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+
-+	/* Init Fw LPS related. */
-+	adapter_to_pwrctl(padapter)->bFwCurrentInPSMode = _FALSE;
-+
-+	/* Init H2C cmd. */
-+	rtw_write8(padapter, REG_HMETFR, 0x0f);
-+
-+	/* Init H2C counter. by tynli. 2009.12.09. */
-+	pHalData->LastHMEBoxNum = 0;
-+	/*	pHalData->H2CQueueHead = 0;
-+	 *	pHalData->H2CQueueTail = 0;
-+	 *	pHalData->H2CStopInsertQueue = _FALSE; */
-+}
-+
-+/* ***********************************************************
-+ *				Efuse related code
-+ * *********************************************************** */
-+static u8
-+hal_EfuseSwitchToBank(
-+	PADAPTER	padapter,
-+	u8			bank,
-+	u8			bPseudoTest)
-+{
-+	u8 bRet = _FALSE;
-+	u32 value32 = 0;
-+#ifdef HAL_EFUSE_MEMORY
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+	PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
-+#endif
-+
-+
-+	RTW_INFO("%s: Efuse switch bank to %d\n", __FUNCTION__, bank);
-+	if (bPseudoTest) {
-+#ifdef HAL_EFUSE_MEMORY
-+		pEfuseHal->fakeEfuseBank = bank;
-+#else
-+		fakeEfuseBank = bank;
-+#endif
-+		bRet = _TRUE;
-+	} else {
-+		value32 = rtw_read32(padapter, EFUSE_TEST);
-+		bRet = _TRUE;
-+		switch (bank) {
-+		case 0:
-+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
-+			break;
-+		case 1:
-+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);
-+			break;
-+		case 2:
-+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);
-+			break;
-+		case 3:
-+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);
-+			break;
-+		default:
-+			value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
-+			bRet = _FALSE;
-+			break;
-+		}
-+		rtw_write32(padapter, EFUSE_TEST, value32);
-+	}
-+
-+	return bRet;
-+}
-+
-+static void
-+Hal_GetEfuseDefinition(
-+	PADAPTER	padapter,
-+	u8			efuseType,
-+	u8			type,
-+	void		*pOut,
-+	u8			bPseudoTest)
-+{
-+	switch (type) {
-+	case TYPE_EFUSE_MAX_SECTION: {
-+		u8 *pMax_section;
-+		pMax_section = (u8 *)pOut;
-+
-+		if (efuseType == EFUSE_WIFI)
-+			*pMax_section = EFUSE_MAX_SECTION_8703B;
-+		else
-+			*pMax_section = EFUSE_BT_MAX_SECTION;
-+	}
-+	break;
-+
-+	case TYPE_EFUSE_REAL_CONTENT_LEN: {
-+		u16 *pu2Tmp;
-+		pu2Tmp = (u16 *)pOut;
-+
-+		if (efuseType == EFUSE_WIFI)
-+			*pu2Tmp = EFUSE_REAL_CONTENT_LEN_8703B;
-+		else
-+			*pu2Tmp = EFUSE_BT_REAL_CONTENT_LEN;
-+	}
-+	break;
-+
-+	case TYPE_AVAILABLE_EFUSE_BYTES_BANK: {
-+		u16	*pu2Tmp;
-+		pu2Tmp = (u16 *)pOut;
-+
-+		if (efuseType == EFUSE_WIFI)
-+			*pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8703B - EFUSE_OOB_PROTECT_BYTES);
-+		else
-+			*pu2Tmp = (EFUSE_BT_REAL_BANK_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK);
-+	}
-+	break;
-+
-+	case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL: {
-+		u16 *pu2Tmp;
-+		pu2Tmp = (u16 *)pOut;
-+
-+		if (efuseType == EFUSE_WIFI)
-+			*pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8703B - EFUSE_OOB_PROTECT_BYTES);
-+		else
-+			*pu2Tmp = (EFUSE_BT_REAL_CONTENT_LEN - (EFUSE_PROTECT_BYTES_BANK * 3));
-+	}
-+	break;
-+
-+	case TYPE_EFUSE_MAP_LEN: {
-+		u16 *pu2Tmp;
-+		pu2Tmp = (u16 *)pOut;
-+
-+		if (efuseType == EFUSE_WIFI)
-+			*pu2Tmp = EFUSE_MAP_LEN_8703B;
-+		else
-+			*pu2Tmp = EFUSE_BT_MAP_LEN;
-+	}
-+	break;
-+
-+	case TYPE_EFUSE_PROTECT_BYTES_BANK: {
-+		u8 *pu1Tmp;
-+		pu1Tmp = (u8 *)pOut;
-+
-+		if (efuseType == EFUSE_WIFI)
-+			*pu1Tmp = EFUSE_OOB_PROTECT_BYTES;
-+		else
-+			*pu1Tmp = EFUSE_PROTECT_BYTES_BANK;
-+	}
-+	break;
-+
-+	case TYPE_EFUSE_CONTENT_LEN_BANK: {
-+		u16 *pu2Tmp;
-+		pu2Tmp = (u16 *)pOut;
-+
-+		if (efuseType == EFUSE_WIFI)
-+			*pu2Tmp = EFUSE_REAL_CONTENT_LEN_8703B;
-+		else
-+			*pu2Tmp = EFUSE_BT_REAL_BANK_CONTENT_LEN;
-+	}
-+	break;
-+
-+	default: {
-+		u8 *pu1Tmp;
-+		pu1Tmp = (u8 *)pOut;
-+		*pu1Tmp = 0;
-+	}
-+	break;
-+	}
-+}
-+
-+#define VOLTAGE_V25		0x03
-+#define LDOE25_SHIFT	28
-+
-+/* *****************************************************************
-+ *	The following is for compile ok
-+ *	That should be merged with the original in the future
-+ * ***************************************************************** */
-+#define EFUSE_ACCESS_ON_8703			0x69	/* For RTL8703 only. */
-+#define EFUSE_ACCESS_OFF_8703			0x00	/* For RTL8703 only. */
-+#define REG_EFUSE_ACCESS_8703			0x00CF	/* Efuse access protection for RTL8703 */
-+
-+/* ***************************************************************** */
-+static void Hal_BT_EfusePowerSwitch(
-+	PADAPTER	padapter,
-+	u8			bWrite,
-+	u8			PwrState)
-+{
-+	u8 tempval;
-+	if (PwrState == _TRUE) {
-+		/* enable BT power cut */
-+		/* 0x6A[14] = 1 */
-+		tempval = rtw_read8(padapter, 0x6B);
-+		tempval |= BIT(6);
-+		rtw_write8(padapter, 0x6B, tempval);
-+
-+		/* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay */
-+		/* So don't wirte 0x6A[14]=1 and 0x6A[15]=0 together! */
-+		rtw_usleep_os(100);
-+		/* disable BT output isolation */
-+		/* 0x6A[15] = 0 */
-+		tempval = rtw_read8(padapter, 0x6B);
-+		tempval &= ~BIT(7);
-+		rtw_write8(padapter, 0x6B, tempval);
-+	} else {
-+		/* enable BT output isolation */
-+		/* 0x6A[15] = 1 */
-+		tempval = rtw_read8(padapter, 0x6B);
-+		tempval |= BIT(7);
-+		rtw_write8(padapter, 0x6B, tempval);
-+
-+		/* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay */
-+		/* So don't wirte 0x6A[14]=1 and 0x6A[15]=0 together! */
-+
-+		/* disable BT power cut */
-+		/* 0x6A[14] = 1 */
-+		tempval = rtw_read8(padapter, 0x6B);
-+		tempval &= ~BIT(6);
-+		rtw_write8(padapter, 0x6B, tempval);
-+	}
-+
-+}
-+static void
-+Hal_EfusePowerSwitch(
-+	PADAPTER	padapter,
-+	u8			bWrite,
-+	u8			PwrState)
-+{
-+	u8	tempval;
-+	u16	tmpV16;
-+
-+
-+	if (PwrState == _TRUE) {
-+		/* enable BT power cut 0x6A[14] = 1*/
-+		tempval = rtw_read8(padapter, 0x6B);
-+		tempval |= BIT(6);
-+		rtw_write8(padapter, 0x6B, tempval);
-+#ifdef CONFIG_SDIO_HCI
-+		/* To avoid cannot access efuse regsiters after disable/enable several times during DTM test. */
-+		/* Suggested by SD1 IsaacHsu. 2013.07.08, added by tynli. */
-+		tempval = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL);
-+		if (tempval & BIT(0)) { /* SDIO local register is suspend */
-+			u8 count = 0;
-+
-+
-+			tempval &= ~BIT(0);
-+			rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL, tempval);
-+
-+			/* check 0x86[1:0]=10'2h, wait power state to leave suspend */
-+			do {
-+				tempval = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL);
-+				tempval &= 0x3;
-+				if (tempval == 0x02)
-+					break;
-+
-+				count++;
-+				if (count >= 100)
-+					break;
-+
-+				rtw_mdelay_os(10);
-+			} while (1);
-+
-+			if (count >= 100) {
-+				RTW_INFO(FUNC_ADPT_FMT ": Leave SDIO local register suspend fail! Local 0x86=%#X\n",
-+					 FUNC_ADPT_ARG(padapter), tempval);
-+			} else {
-+				RTW_INFO(FUNC_ADPT_FMT ": Leave SDIO local register suspend OK! Local 0x86=%#X\n",
-+					 FUNC_ADPT_ARG(padapter), tempval);
-+			}
-+		}
-+#endif /* CONFIG_SDIO_HCI */
-+
-+		rtw_write8(padapter, REG_EFUSE_ACCESS_8703, EFUSE_ACCESS_ON_8703);
-+
-+		/* Reset: 0x0000h[28], default valid */
-+		tmpV16 =  rtw_read16(padapter, REG_SYS_FUNC_EN);
-+		if (!(tmpV16 & FEN_ELDR)) {
-+			tmpV16 |= FEN_ELDR ;
-+			rtw_write16(padapter, REG_SYS_FUNC_EN, tmpV16);
-+		}
-+
-+		/* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */
-+		tmpV16 = rtw_read16(padapter, REG_SYS_CLKR);
-+		if ((!(tmpV16 & LOADER_CLK_EN))  || (!(tmpV16 & ANA8M))) {
-+			tmpV16 |= (LOADER_CLK_EN | ANA8M) ;
-+			rtw_write16(padapter, REG_SYS_CLKR, tmpV16);
-+		}
-+
-+		if (bWrite == _TRUE) {
-+			/* Enable LDO 2.5V before read/write action */
-+			tempval = rtw_read8(padapter, EFUSE_TEST + 3);
-+			tempval &= 0x0F;
-+			/*tempval |= (VOLTAGE_V25 << 4);*/
-+			tempval |= 0x70; /* 0x34[30:28] = 0b'111,  Use LDO 2.25V, Suggested by SD1 Morris & Victor*/
-+			rtw_write8(padapter, EFUSE_TEST + 3, (tempval | 0x80));
-+
-+			/* rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); */
-+		}
-+	} else {
-+
-+		/*enable BT output isolation 0x6A[15] = 1 */
-+		tempval = rtw_read8(padapter, 0x6B);
-+		tempval |= BIT(7);
-+		rtw_write8(padapter, 0x6B, tempval);
-+
-+		rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
-+
-+		if (bWrite == _TRUE) {
-+			/* Disable LDO 2.5V after read/write action */
-+			tempval = rtw_read8(padapter, EFUSE_TEST + 3);
-+			rtw_write8(padapter, EFUSE_TEST + 3, (tempval & 0x7F));
-+		}
-+
-+	}
-+}
-+
-+static void
-+hal_ReadEFuse_WiFi(
-+	PADAPTER	padapter,
-+	u16			_offset,
-+	u16			_size_byte,
-+	u8			*pbuf,
-+	u8			bPseudoTest)
-+{
-+#ifdef HAL_EFUSE_MEMORY
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
-+#endif
-+	u8	*efuseTbl = NULL;
-+	u16	eFuse_Addr = 0;
-+	u8	offset, wden;
-+	u8	efuseHeader, efuseExtHdr, efuseData;
-+	u16	i, total, used;
-+	u8	efuse_usage = 0;
-+
-+	/* RTW_INFO("YJ: ====>%s():_offset=%d _size_byte=%d bPseudoTest=%d\n", __func__, _offset, _size_byte, bPseudoTest); */
-+	/*  */
-+	/* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
-+	/*  */
-+	if ((_offset + _size_byte) > EFUSE_MAX_MAP_LEN) {
-+		RTW_INFO("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __FUNCTION__, _offset, _size_byte);
-+		return;
-+	}
-+
-+	efuseTbl = (u8 *)rtw_malloc(EFUSE_MAX_MAP_LEN);
-+	if (efuseTbl == NULL) {
-+		RTW_INFO("%s: alloc efuseTbl fail!\n", __FUNCTION__);
-+		return;
-+	}
-+	/* 0xff will be efuse default value instead of 0x00. */
-+	_rtw_memset(efuseTbl, 0xFF, EFUSE_MAX_MAP_LEN);
-+
-+
-+#ifdef CONFIG_RTW_DEBUG
-+	if (0) {
-+		for (i = 0; i < 256; i++)
-+			/* ReadEFuseByte(padapter, i, &efuseTbl[i], _FALSE); */
-+			efuse_OneByteRead(padapter, i, &efuseTbl[i], _FALSE);
-+		RTW_INFO("Efuse Content:\n");
-+		for (i = 0; i < 256; i++) {
-+			if (i % 16 == 0)
-+				printk("\n");
-+			printk("%02X ", efuseTbl[i]);
-+		}
-+		printk("\n");
-+	}
-+#endif
-+
-+
-+	/* switch bank back to bank 0 for later BT and wifi use. */
-+	hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
-+
-+	while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
-+		/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */
-+		efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
-+		if (efuseHeader == 0xFF) {
-+			RTW_INFO("%s: data end at address=%#x\n", __FUNCTION__, eFuse_Addr - 1);
-+			break;
-+		}
-+		/* RTW_INFO("%s: efuse[0x%X]=0x%02X\n", __FUNCTION__, eFuse_Addr-1, efuseHeader); */
-+
-+		/* Check PG header for section num. */
-+		if (EXT_HEADER(efuseHeader)) {	/* extended header */
-+			offset = GET_HDR_OFFSET_2_0(efuseHeader);
-+			/* RTW_INFO("%s: extended header offset=0x%X\n", __FUNCTION__, offset); */
-+
-+			/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */
-+			efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
-+			/* RTW_INFO("%s: efuse[0x%X]=0x%02X\n", __FUNCTION__, eFuse_Addr-1, efuseExtHdr); */
-+			if (ALL_WORDS_DISABLED(efuseExtHdr))
-+				continue;
-+
-+			offset |= ((efuseExtHdr & 0xF0) >> 1);
-+			wden = (efuseExtHdr & 0x0F);
-+		} else {
-+			offset = ((efuseHeader >> 4) & 0x0f);
-+			wden = (efuseHeader & 0x0f);
-+		}
-+		/* RTW_INFO("%s: Offset=%d Worden=0x%X\n", __FUNCTION__, offset, wden); */
-+
-+		if (offset < EFUSE_MAX_SECTION_8703B) {
-+			u16 addr;
-+			/* Get word enable value from PG header
-+			* 			RTW_INFO("%s: Offset=%d Worden=0x%X\n", __FUNCTION__, offset, wden); */
-+
-+			addr = offset * PGPKT_DATA_SIZE;
-+			for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
-+				/* Check word enable condition in the section */
-+				if (!(wden & (0x01 << i))) {
-+					efuseData = 0;
-+					/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
-+					efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
-+					/*					RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr-1, efuseData); */
-+					efuseTbl[addr] = efuseData;
-+
-+					efuseData = 0;
-+					/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
-+					efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
-+					/*					RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr-1, efuseData); */
-+					efuseTbl[addr + 1] = efuseData;
-+				}
-+				addr += 2;
-+			}
-+		} else {
-+			RTW_ERR("%s: offset(%d) is illegal!!\n", __FUNCTION__, offset);
-+			eFuse_Addr += Efuse_CalculateWordCnts(wden) * 2;
-+		}
-+	}
-+
-+	/* Copy from Efuse map to output pointer memory!!! */
-+	for (i = 0; i < _size_byte; i++)
-+		pbuf[i] = efuseTbl[_offset + i];
-+
-+	/* Calculate Efuse utilization */
-+	total = 0;
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
-+	used = eFuse_Addr - 1;
-+	if (total)
-+		efuse_usage = (u8)((used * 100) / total);
-+	else
-+		efuse_usage = 100;
-+	if (bPseudoTest) {
-+#ifdef HAL_EFUSE_MEMORY
-+		pEfuseHal->fakeEfuseUsedBytes = used;
-+#else
-+		fakeEfuseUsedBytes = used;
-+#endif
-+	} else {
-+		rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&used);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_USAGE, (u8 *)&efuse_usage);
-+	}
-+
-+	if (efuseTbl)
-+		rtw_mfree(efuseTbl, EFUSE_MAX_MAP_LEN);
-+}
-+
-+static void
-+hal_ReadEFuse_BT(
-+	PADAPTER	padapter,
-+	u16			_offset,
-+	u16			_size_byte,
-+	u8			*pbuf,
-+	u8			bPseudoTest
-+)
-+{
-+#ifdef HAL_EFUSE_MEMORY
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
-+#endif
-+	u8	*efuseTbl;
-+	u8	bank;
-+	u16	eFuse_Addr;
-+	u8	efuseHeader, efuseExtHdr, efuseData;
-+	u8	offset, wden;
-+	u16	i, total, used;
-+	u8	efuse_usage;
-+
-+
-+	/*  */
-+	/* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
-+	/*  */
-+	if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) {
-+		RTW_INFO("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __FUNCTION__, _offset, _size_byte);
-+		return;
-+	}
-+
-+	efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN);
-+	if (efuseTbl == NULL) {
-+		RTW_INFO("%s: efuseTbl malloc fail!\n", __FUNCTION__);
-+		return;
-+	}
-+	/* 0xff will be efuse default value instead of 0x00. */
-+	_rtw_memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
-+
-+	total = 0;
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total, bPseudoTest);
-+
-+	for (bank = 1; bank < 3; bank++) { /* 8703b Max bake 0~2 */
-+		if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) {
-+			RTW_INFO("%s: hal_EfuseSwitchToBank Fail!!\n", __FUNCTION__);
-+			goto exit;
-+		}
-+
-+		eFuse_Addr = 0;
-+
-+		while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
-+			/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */
-+			efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
-+			if (efuseHeader == 0xFF)
-+				break;
-+			RTW_INFO("%s: efuse[%#X]=0x%02x (header)\n", __FUNCTION__, (((bank - 1) * EFUSE_REAL_CONTENT_LEN_8703B) + eFuse_Addr - 1), efuseHeader);
-+
-+			/* Check PG header for section num. */
-+			if (EXT_HEADER(efuseHeader)) {	/* extended header */
-+				offset = GET_HDR_OFFSET_2_0(efuseHeader);
-+				RTW_INFO("%s: extended header offset_2_0=0x%X\n", __FUNCTION__, offset);
-+
-+				/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */
-+				efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
-+				RTW_INFO("%s: efuse[%#X]=0x%02x (ext header)\n", __FUNCTION__, (((bank - 1) * EFUSE_REAL_CONTENT_LEN_8703B) + eFuse_Addr - 1), efuseExtHdr);
-+				if (ALL_WORDS_DISABLED(efuseExtHdr))
-+					continue;
-+
-+				offset |= ((efuseExtHdr & 0xF0) >> 1);
-+				wden = (efuseExtHdr & 0x0F);
-+			} else {
-+				offset = ((efuseHeader >> 4) & 0x0f);
-+				wden = (efuseHeader & 0x0f);
-+			}
-+
-+			if (offset < EFUSE_BT_MAX_SECTION) {
-+				u16 addr;
-+
-+				/* Get word enable value from PG header */
-+				RTW_INFO("%s: Offset=%d Worden=%#X\n", __FUNCTION__, offset, wden);
-+
-+				addr = offset * PGPKT_DATA_SIZE;
-+				for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
-+					/* Check word enable condition in the section */
-+					if (!(wden & (0x01 << i))) {
-+						efuseData = 0;
-+						/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
-+						efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
-+						RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr - 1, efuseData);
-+						efuseTbl[addr] = efuseData;
-+
-+						efuseData = 0;
-+						/* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
-+						efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
-+						RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr - 1, efuseData);
-+						efuseTbl[addr + 1] = efuseData;
-+					}
-+					addr += 2;
-+				}
-+			} else {
-+				RTW_INFO("%s: offset(%d) is illegal!!\n", __FUNCTION__, offset);
-+				eFuse_Addr += Efuse_CalculateWordCnts(wden) * 2;
-+			}
-+		}
-+
-+		if ((eFuse_Addr - 1) < total) {
-+			RTW_INFO("%s: bank(%d) data end at %#x\n", __FUNCTION__, bank, eFuse_Addr - 1);
-+			break;
-+		}
-+	}
-+
-+	/* switch bank back to bank 0 for later BT and wifi use. */
-+	hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
-+
-+	/* Copy from Efuse map to output pointer memory!!! */
-+	for (i = 0; i < _size_byte; i++)
-+		pbuf[i] = efuseTbl[_offset + i];
-+
-+	/*  */
-+	/* Calculate Efuse utilization. */
-+	/*  */
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
-+	used = (EFUSE_BT_REAL_BANK_CONTENT_LEN * (bank - 1)) + eFuse_Addr - 1;
-+	RTW_INFO("%s: bank(%d) data end at %#x ,used =%d\n", __FUNCTION__, bank, eFuse_Addr - 1, used);
-+	efuse_usage = (u8)((used * 100) / total);
-+	if (bPseudoTest) {
-+#ifdef HAL_EFUSE_MEMORY
-+		pEfuseHal->fakeBTEfuseUsedBytes = used;
-+#else
-+		fakeBTEfuseUsedBytes = used;
-+#endif
-+	} else {
-+		rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&used);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_USAGE, (u8 *)&efuse_usage);
-+	}
-+
-+exit:
-+	if (efuseTbl)
-+		rtw_mfree(efuseTbl, EFUSE_BT_MAP_LEN);
-+}
-+
-+static void
-+Hal_ReadEFuse(
-+	PADAPTER	padapter,
-+	u8			efuseType,
-+	u16			_offset,
-+	u16			_size_byte,
-+	u8			*pbuf,
-+	u8			bPseudoTest)
-+{
-+	if (efuseType == EFUSE_WIFI)
-+		hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf, bPseudoTest);
-+	else
-+		hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf, bPseudoTest);
-+}
-+
-+static u16
-+hal_EfuseGetCurrentSize_WiFi(
-+	PADAPTER	padapter,
-+	u8			bPseudoTest)
-+{
-+#ifdef HAL_EFUSE_MEMORY
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
-+#endif
-+	u16	efuse_addr = 0;
-+	u16 start_addr = 0; /* for debug */
-+	u8	hoffset = 0, hworden = 0;
-+	u8	efuse_data, word_cnts = 0;
-+	u32 count = 0; /* for debug */
-+
-+
-+	if (bPseudoTest) {
-+#ifdef HAL_EFUSE_MEMORY
-+		efuse_addr = (u16)pEfuseHal->fakeEfuseUsedBytes;
-+#else
-+		efuse_addr = (u16)fakeEfuseUsedBytes;
-+#endif
-+	} else
-+		rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
-+	start_addr = efuse_addr;
-+	RTW_INFO("%s: start_efuse_addr=0x%X\n", __FUNCTION__, efuse_addr);
-+
-+	/* switch bank back to bank 0 for later BT and wifi use. */
-+	hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
-+
-+#if 0 /* for debug test */
-+	efuse_OneByteRead(padapter, 0x1FF, &efuse_data, bPseudoTest);
-+	RTW_INFO(FUNC_ADPT_FMT ": efuse raw 0x1FF=0x%02X\n",
-+		 FUNC_ADPT_ARG(padapter), efuse_data);
-+	efuse_data = 0xFF;
-+#endif /* for debug test */
-+
-+	count = 0;
-+	while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
-+#if 1
-+		if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == _FALSE) {
-+			RTW_ERR("%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __FUNCTION__, efuse_addr);
-+			goto error;
-+		}
-+#else
-+		ReadEFuseByte(padapter, efuse_addr, &efuse_data, bPseudoTest);
-+#endif
-+
-+		if (efuse_data == 0xFF)
-+			break;
-+
-+		if ((start_addr != 0) && (efuse_addr == start_addr)) {
-+			count++;
-+			RTW_INFO(FUNC_ADPT_FMT ": [WARNING] efuse raw 0x%X=0x%02X not 0xFF!!(%d times)\n",
-+				FUNC_ADPT_ARG(padapter), efuse_addr, efuse_data, count);
-+
-+			efuse_data = 0xFF;
-+			if (count < 4) {
-+				/* try again! */
-+
-+				if (count > 2) {
-+					/* try again form address 0 */
-+					efuse_addr = 0;
-+					start_addr = 0;
-+				}
-+
-+				continue;
-+			}
-+
-+			goto error;
-+		}
-+
-+		if (EXT_HEADER(efuse_data)) {
-+			hoffset = GET_HDR_OFFSET_2_0(efuse_data);
-+			efuse_addr++;
-+			efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
-+			if (ALL_WORDS_DISABLED(efuse_data))
-+				continue;
-+
-+			hoffset |= ((efuse_data & 0xF0) >> 1);
-+			hworden = efuse_data & 0x0F;
-+		} else {
-+			hoffset = (efuse_data >> 4) & 0x0F;
-+			hworden = efuse_data & 0x0F;
-+		}
-+
-+		word_cnts = Efuse_CalculateWordCnts(hworden);
-+		efuse_addr += (word_cnts * 2) + 1;
-+	}
-+
-+	if (bPseudoTest) {
-+#ifdef HAL_EFUSE_MEMORY
-+		pEfuseHal->fakeEfuseUsedBytes = efuse_addr;
-+#else
-+		fakeEfuseUsedBytes = efuse_addr;
-+#endif
-+	} else
-+		rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
-+
-+	goto exit;
-+
-+error:
-+	/* report max size to prevent wirte efuse */
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_addr, bPseudoTest);
-+
-+exit:
-+	RTW_INFO("%s: CurrentSize=%d\n", __FUNCTION__, efuse_addr);
-+
-+	return efuse_addr;
-+}
-+
-+static u16
-+hal_EfuseGetCurrentSize_BT(
-+	PADAPTER	padapter,
-+	u8			bPseudoTest)
-+{
-+#ifdef HAL_EFUSE_MEMORY
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
-+#endif
-+	u16 btusedbytes;
-+	u16	efuse_addr;
-+	u8	bank, startBank;
-+	u8	hoffset = 0, hworden = 0;
-+	u8	efuse_data, word_cnts = 0;
-+	u16	retU2 = 0;
-+	u8 bContinual = _TRUE;
-+
-+
-+	if (bPseudoTest) {
-+#ifdef HAL_EFUSE_MEMORY
-+		btusedbytes = pEfuseHal->fakeBTEfuseUsedBytes;
-+#else
-+		btusedbytes = fakeBTEfuseUsedBytes;
-+#endif
-+	} else {
-+		btusedbytes = 0;
-+		rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&btusedbytes);
-+	}
-+	efuse_addr = (u16)((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN));
-+	startBank = (u8)(1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN));
-+
-+	RTW_INFO("%s: start from bank=%d addr=0x%X\n", __FUNCTION__, startBank, efuse_addr);
-+
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2, bPseudoTest);
-+
-+	for (bank = startBank; bank < 3; bank++) {
-+		if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) {
-+			RTW_ERR("%s: switch bank(%d) Fail!!\n", __FUNCTION__, bank);
-+			/* bank = EFUSE_MAX_BANK; */
-+			break;
-+		}
-+
-+		/* only when bank is switched we have to reset the efuse_addr. */
-+		if (bank != startBank)
-+			efuse_addr = 0;
-+#if 1
-+
-+		while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
-+			if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == _FALSE) {
-+				RTW_ERR("%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __FUNCTION__, efuse_addr);
-+				/* bank = EFUSE_MAX_BANK; */
-+				break;
-+			}
-+			RTW_INFO("%s: efuse_OneByteRead ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank);
-+
-+			if (efuse_data == 0xFF)
-+				break;
-+
-+			if (EXT_HEADER(efuse_data)) {
-+				hoffset = GET_HDR_OFFSET_2_0(efuse_data);
-+				efuse_addr++;
-+				efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
-+				RTW_INFO("%s: efuse_OneByteRead EXT_HEADER ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank);
-+
-+				if (ALL_WORDS_DISABLED(efuse_data)) {
-+					efuse_addr++;
-+					continue;
-+				}
-+
-+				/*				hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); */
-+				hoffset |= ((efuse_data & 0xF0) >> 1);
-+				hworden = efuse_data & 0x0F;
-+			} else {
-+				hoffset = (efuse_data >> 4) & 0x0F;
-+				hworden =  efuse_data & 0x0F;
-+			}
-+
-+			RTW_INFO(FUNC_ADPT_FMT": Offset=%d Worden=%#X\n",
-+				 FUNC_ADPT_ARG(padapter), hoffset, hworden);
-+
-+			word_cnts = Efuse_CalculateWordCnts(hworden);
-+			/* read next header */
-+			efuse_addr += (word_cnts * 2) + 1;
-+		}
-+#else
-+		while (bContinual &&
-+		       efuse_OneByteRead(padapter, efuse_addr , &efuse_data, bPseudoTest) &&
-+		       AVAILABLE_EFUSE_ADDR(efuse_addr)) {
-+			if (efuse_data != 0xFF) {
-+				if ((efuse_data & 0x1F) == 0x0F) {	/* extended header */
-+					hoffset = efuse_data;
-+					efuse_addr++;
-+					efuse_OneByteRead(padapter, efuse_addr , &efuse_data, bPseudoTest);
-+					if ((efuse_data & 0x0F) == 0x0F) {
-+						efuse_addr++;
-+						continue;
-+					} else {
-+						hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
-+						hworden = efuse_data & 0x0F;
-+					}
-+				} else {
-+					hoffset = (efuse_data >> 4) & 0x0F;
-+					hworden =  efuse_data & 0x0F;
-+				}
-+				word_cnts = Efuse_CalculateWordCnts(hworden);
-+				/* read next header							 */
-+				efuse_addr = efuse_addr + (word_cnts * 2) + 1;
-+			} else
-+				bContinual = _FALSE ;
-+		}
-+#endif
-+
-+
-+		/* Check if we need to check next bank efuse */
-+		if (efuse_addr < retU2) {
-+			break;/* don't need to check next bank. */
-+		}
-+	}
-+#if 0
-+	retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
-+	if (bPseudoTest) {
-+#ifdef HAL_EFUSE_MEMORY
-+		pEfuseHal->fakeBTEfuseUsedBytes = retU2;
-+#else
-+		fakeBTEfuseUsedBytes = retU2;
-+#endif
-+	} else
-+		rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&retU2);
-+#else
-+	retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
-+	if (bPseudoTest) {
-+		pEfuseHal->fakeBTEfuseUsedBytes = retU2;
-+		/* RT_DISP(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT92C(), already use %u bytes\n", pEfuseHal->fakeBTEfuseUsedBytes)); */
-+	} else {
-+		pEfuseHal->BTEfuseUsedBytes = retU2;
-+		/* RT_DISP(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT92C(), already use %u bytes\n", pEfuseHal->BTEfuseUsedBytes)); */
-+	}
-+#endif
-+
-+	RTW_INFO("%s: CurrentSize=%d\n", __FUNCTION__, retU2);
-+	return retU2;
-+}
-+
-+static u16
-+Hal_EfuseGetCurrentSize(
-+	PADAPTER	pAdapter,
-+	u8			efuseType,
-+	u8			bPseudoTest)
-+{
-+	u16	ret = 0;
-+
-+	if (efuseType == EFUSE_WIFI)
-+		ret = hal_EfuseGetCurrentSize_WiFi(pAdapter, bPseudoTest);
-+	else
-+		ret = hal_EfuseGetCurrentSize_BT(pAdapter, bPseudoTest);
-+
-+	return ret;
-+}
-+
-+static u8
-+Hal_EfuseWordEnableDataWrite(
-+	PADAPTER	padapter,
-+	u16			efuse_addr,
-+	u8			word_en,
-+	u8			*data,
-+	u8			bPseudoTest)
-+{
-+	u16	tmpaddr = 0;
-+	u16	start_addr = efuse_addr;
-+	u8	badworden = 0x0F;
-+	u8	tmpdata[PGPKT_DATA_SIZE];
-+
-+
-+	/*	RTW_INFO("%s: efuse_addr=%#x word_en=%#x\n", __FUNCTION__, efuse_addr, word_en); */
-+	_rtw_memset(tmpdata, 0xFF, PGPKT_DATA_SIZE);
-+
-+	if (!(word_en & BIT(0))) {
-+		tmpaddr = start_addr;
-+		efuse_OneByteWrite(padapter, start_addr++, data[0], bPseudoTest);
-+		efuse_OneByteWrite(padapter, start_addr++, data[1], bPseudoTest);
-+		phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
-+		efuse_OneByteRead(padapter, tmpaddr, &tmpdata[0], bPseudoTest);
-+		efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[1], bPseudoTest);
-+		phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
-+		if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))
-+			badworden &= (~BIT(0));
-+	}
-+	if (!(word_en & BIT(1))) {
-+		tmpaddr = start_addr;
-+		efuse_OneByteWrite(padapter, start_addr++, data[2], bPseudoTest);
-+		efuse_OneByteWrite(padapter, start_addr++, data[3], bPseudoTest);
-+		phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
-+		efuse_OneByteRead(padapter, tmpaddr, &tmpdata[2], bPseudoTest);
-+		efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[3], bPseudoTest);
-+		phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
-+		if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))
-+			badworden &= (~BIT(1));
-+	}
-+	if (!(word_en & BIT(2))) {
-+		tmpaddr = start_addr;
-+		efuse_OneByteWrite(padapter, start_addr++, data[4], bPseudoTest);
-+		efuse_OneByteWrite(padapter, start_addr++, data[5], bPseudoTest);
-+		phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
-+		efuse_OneByteRead(padapter, tmpaddr, &tmpdata[4], bPseudoTest);
-+		efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[5], bPseudoTest);
-+		phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
-+		if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))
-+			badworden &= (~BIT(2));
-+	}
-+	if (!(word_en & BIT(3))) {
-+		tmpaddr = start_addr;
-+		efuse_OneByteWrite(padapter, start_addr++, data[6], bPseudoTest);
-+		efuse_OneByteWrite(padapter, start_addr++, data[7], bPseudoTest);
-+		phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
-+		efuse_OneByteRead(padapter, tmpaddr, &tmpdata[6], bPseudoTest);
-+		efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[7], bPseudoTest);
-+		phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
-+		if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))
-+			badworden &= (~BIT(3));
-+	}
-+
-+	return badworden;
-+}
-+
-+static s32
-+Hal_EfusePgPacketRead(
-+	PADAPTER	padapter,
-+	u8			offset,
-+	u8			*data,
-+	u8			bPseudoTest)
-+{
-+	u8	bDataEmpty = _TRUE;
-+	u8	efuse_data, word_cnts = 0;
-+	u16	efuse_addr = 0;
-+	u8	hoffset = 0, hworden = 0;
-+	u8	i;
-+	u8	max_section = 0;
-+	s32	ret;
-+
-+
-+	if (data == NULL)
-+		return _FALSE;
-+
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, &max_section, bPseudoTest);
-+	if (offset > max_section) {
-+		RTW_INFO("%s: Packet offset(%d) is illegal(>%d)!\n", __FUNCTION__, offset, max_section);
-+		return _FALSE;
-+	}
-+
-+	_rtw_memset(data, 0xFF, PGPKT_DATA_SIZE);
-+	ret = _TRUE;
-+
-+	/*  */
-+	/* <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. */
-+	/* Skip dummy parts to prevent unexpected data read from Efuse. */
-+	/* By pass right now. 2009.02.19. */
-+	/*  */
-+	while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
-+		if (efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest) == _FALSE) {
-+			ret = _FALSE;
-+			break;
-+		}
-+
-+		if (efuse_data == 0xFF)
-+			break;
-+
-+		if (EXT_HEADER(efuse_data)) {
-+			hoffset = GET_HDR_OFFSET_2_0(efuse_data);
-+			efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
-+			if (ALL_WORDS_DISABLED(efuse_data)) {
-+				RTW_INFO("%s: Error!! All words disabled!\n", __FUNCTION__);
-+				continue;
-+			}
-+
-+			hoffset |= ((efuse_data & 0xF0) >> 1);
-+			hworden = efuse_data & 0x0F;
-+		} else {
-+			hoffset = (efuse_data >> 4) & 0x0F;
-+			hworden =  efuse_data & 0x0F;
-+		}
-+
-+		if (hoffset == offset) {
-+			for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
-+				/* Check word enable condition in the section */
-+				if (!(hworden & (0x01 << i))) {
-+					/* ReadEFuseByte(padapter, efuse_addr++, &efuse_data, bPseudoTest); */
-+					efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
-+					/*					RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, efuse_addr+tmpidx, efuse_data); */
-+					data[i * 2] = efuse_data;
-+
-+					/* ReadEFuseByte(padapter, efuse_addr++, &efuse_data, bPseudoTest); */
-+					efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
-+					/*					RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, efuse_addr+tmpidx, efuse_data); */
-+					data[(i * 2) + 1] = efuse_data;
-+				}
-+			}
-+		} else {
-+			word_cnts = Efuse_CalculateWordCnts(hworden);
-+			efuse_addr += word_cnts * 2;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+static u8
-+hal_EfusePgCheckAvailableAddr(
-+	PADAPTER	pAdapter,
-+	u8			efuseType,
-+	u8		bPseudoTest)
-+{
-+	u16	max_available = 0;
-+	u16 current_size;
-+
-+
-+	EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &max_available, bPseudoTest);
-+	/*	RTW_INFO("%s: max_available=%d\n", __FUNCTION__, max_available); */
-+
-+	current_size = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest);
-+	if (current_size >= max_available) {
-+		RTW_INFO("%s: Error!! current_size(%d)>max_available(%d)\n", __FUNCTION__, current_size, max_available);
-+		return _FALSE;
-+	}
-+	return _TRUE;
-+}
-+
-+static void
-+hal_EfuseConstructPGPkt(
-+	u8				offset,
-+	u8				word_en,
-+	u8				*pData,
-+	PPGPKT_STRUCT	pTargetPkt)
-+{
-+	_rtw_memset(pTargetPkt->data, 0xFF, PGPKT_DATA_SIZE);
-+	pTargetPkt->offset = offset;
-+	pTargetPkt->word_en = word_en;
-+	efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
-+	pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
-+}
-+
-+#if 0
-+static u8
-+wordEnMatched(
-+	PPGPKT_STRUCT	pTargetPkt,
-+	PPGPKT_STRUCT	pCurPkt,
-+	u8				*pWden)
-+{
-+	u8	match_word_en = 0x0F;	/* default all words are disabled */
-+	u8	i;
-+
-+	/* check if the same words are enabled both target and current PG packet */
-+	if (((pTargetPkt->word_en & BIT(0)) == 0) &&
-+	    ((pCurPkt->word_en & BIT(0)) == 0)) {
-+		match_word_en &= ~BIT(0);				/* enable word 0 */
-+	}
-+	if (((pTargetPkt->word_en & BIT(1)) == 0) &&
-+	    ((pCurPkt->word_en & BIT(1)) == 0)) {
-+		match_word_en &= ~BIT(1);				/* enable word 1 */
-+	}
-+	if (((pTargetPkt->word_en & BIT(2)) == 0) &&
-+	    ((pCurPkt->word_en & BIT(2)) == 0)) {
-+		match_word_en &= ~BIT(2);				/* enable word 2 */
-+	}
-+	if (((pTargetPkt->word_en & BIT(3)) == 0) &&
-+	    ((pCurPkt->word_en & BIT(3)) == 0)) {
-+		match_word_en &= ~BIT(3);				/* enable word 3 */
-+	}
-+
-+	*pWden = match_word_en;
-+
-+	if (match_word_en != 0xf)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+static u8
-+hal_EfuseCheckIfDatafollowed(
-+	PADAPTER		pAdapter,
-+	u8				word_cnts,
-+	u16				startAddr,
-+	u8				bPseudoTest)
-+{
-+	u8 bRet = _FALSE;
-+	u8 i, efuse_data;
-+
-+	for (i = 0; i < (word_cnts * 2); i++) {
-+		if (efuse_OneByteRead(pAdapter, (startAddr + i) , &efuse_data, bPseudoTest) == _FALSE) {
-+			RTW_INFO("%s: efuse_OneByteRead FAIL!!\n", __FUNCTION__);
-+			bRet = _TRUE;
-+			break;
-+		}
-+
-+		if (efuse_data != 0xFF) {
-+			bRet = _TRUE;
-+			break;
-+		}
-+	}
-+
-+	return bRet;
-+}
-+#endif
-+
-+static u8
-+hal_EfusePartialWriteCheck(
-+	PADAPTER		padapter,
-+	u8				efuseType,
-+	u16				*pAddr,
-+	PPGPKT_STRUCT	pTargetPkt,
-+	u8				bPseudoTest)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	PEFUSE_HAL		pEfuseHal = &pHalData->EfuseHal;
-+	u8	bRet = _FALSE;
-+	u16	startAddr = 0, efuse_max_available_len = 0, efuse_max = 0;
-+	u8	efuse_data = 0;
-+#if 0
-+	u8	i, cur_header = 0;
-+	u8	new_wden = 0, matched_wden = 0, badworden = 0;
-+	PGPKT_STRUCT	curPkt;
-+#endif
-+
-+
-+	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, bPseudoTest);
-+	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, &efuse_max, bPseudoTest);
-+
-+	if (efuseType == EFUSE_WIFI) {
-+		if (bPseudoTest) {
-+#ifdef HAL_EFUSE_MEMORY
-+			startAddr = (u16)pEfuseHal->fakeEfuseUsedBytes;
-+#else
-+			startAddr = (u16)fakeEfuseUsedBytes;
-+#endif
-+		} else
-+			rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
-+	} else {
-+		if (bPseudoTest) {
-+#ifdef HAL_EFUSE_MEMORY
-+			startAddr = (u16)pEfuseHal->fakeBTEfuseUsedBytes;
-+#else
-+			startAddr = (u16)fakeBTEfuseUsedBytes;
-+#endif
-+		} else
-+			rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&startAddr);
-+	}
-+	startAddr %= efuse_max;
-+	RTW_INFO("%s: startAddr=%#X\n", __FUNCTION__, startAddr);
-+
-+	while (1) {
-+		if (startAddr >= efuse_max_available_len) {
-+			bRet = _FALSE;
-+			RTW_INFO("%s: startAddr(%d) >= efuse_max_available_len(%d)\n",
-+				__FUNCTION__, startAddr, efuse_max_available_len);
-+			break;
-+		}
-+
-+		if (efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) {
-+#if 1
-+			bRet = _FALSE;
-+			RTW_INFO("%s: Something Wrong! last bytes(%#X=0x%02X) is not 0xFF\n",
-+				 __FUNCTION__, startAddr, efuse_data);
-+			break;
-+#else
-+			if (EXT_HEADER(efuse_data)) {
-+				cur_header = efuse_data;
-+				startAddr++;
-+				efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest);
-+				if (ALL_WORDS_DISABLED(efuse_data)) {
-+					RTW_INFO("%s: Error condition, all words disabled!", __FUNCTION__);
-+					bRet = _FALSE;
-+					break;
-+				} else {
-+					curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
-+					curPkt.word_en = efuse_data & 0x0F;
-+				}
-+			} else {
-+				cur_header  =  efuse_data;
-+				curPkt.offset = (cur_header >> 4) & 0x0F;
-+				curPkt.word_en = cur_header & 0x0F;
-+			}
-+
-+			curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en);
-+			/* if same header is found but no data followed */
-+			/* write some part of data followed by the header. */
-+			if ((curPkt.offset == pTargetPkt->offset) &&
-+			    (hal_EfuseCheckIfDatafollowed(padapter, curPkt.word_cnts, startAddr + 1, bPseudoTest) == _FALSE) &&
-+			    wordEnMatched(pTargetPkt, &curPkt, &matched_wden) == _TRUE) {
-+				RTW_INFO("%s: Need to partial write data by the previous wrote header\n", __FUNCTION__);
-+				/* Here to write partial data */
-+				badworden = Efuse_WordEnableDataWrite(padapter, startAddr + 1, matched_wden, pTargetPkt->data, bPseudoTest);
-+				if (badworden != 0x0F) {
-+					u32	PgWriteSuccess = 0;
-+					/* if write fail on some words, write these bad words again */
-+					if (efuseType == EFUSE_WIFI)
-+						PgWriteSuccess = Efuse_PgPacketWrite(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
-+					else
-+						PgWriteSuccess = Efuse_PgPacketWrite_BT(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
-+
-+					if (!PgWriteSuccess) {
-+						bRet = _FALSE;	/* write fail, return */
-+						break;
-+					}
-+				}
-+				/* partial write ok, update the target packet for later use */
-+				for (i = 0; i < 4; i++) {
-+					if ((matched_wden & (0x1 << i)) == 0) {	/* this word has been written */
-+						pTargetPkt->word_en |= (0x1 << i);	/* disable the word */
-+					}
-+				}
-+				pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
-+			}
-+			/* read from next header */
-+			startAddr = startAddr + (curPkt.word_cnts * 2) + 1;
-+#endif
-+		} else {
-+			/* not used header, 0xff */
-+			*pAddr = startAddr;
-+			/*			RTW_INFO("%s: Started from unused header offset=%d\n", __FUNCTION__, startAddr)); */
-+			bRet = _TRUE;
-+			break;
-+		}
-+	}
-+
-+	return bRet;
-+}
-+
-+BOOLEAN
-+hal_EfuseFixHeaderProcess(
-+			PADAPTER			pAdapter,
-+			u8					efuseType,
-+			PPGPKT_STRUCT		pFixPkt,
-+			u16 					*pAddr,
-+			BOOLEAN				bPseudoTest
-+)
-+{
-+	u8	originaldata[8], badworden=0;
-+	u16	efuse_addr=*pAddr;
-+	u32	PgWriteSuccess=0;
-+
-+	 _rtw_memset((void *)originaldata, 0xff, 8);
-+
-+	if (Efuse_PgPacketRead(pAdapter, pFixPkt->offset, originaldata, bPseudoTest)) {
-+		badworden = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr+1, pFixPkt->word_en, originaldata, bPseudoTest);
-+
-+		if (badworden != 0xf) {
-+
-+			PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest);
-+			if (!PgWriteSuccess)
-+				return FALSE;
-+			else
-+				efuse_addr = Hal_EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest);
-+		} else {
-+			efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1;
-+		}
-+	} else {
-+		efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1;
-+	}
-+
-+	*pAddr = efuse_addr;
-+	return TRUE;
-+}
-+
-+static u8
-+hal_EfusePgPacketWrite1ByteHeader(
-+	PADAPTER		pAdapter,
-+	u8				efuseType,
-+	u16				*pAddr,
-+	PPGPKT_STRUCT	pTargetPkt,
-+	u8				bPseudoTest)
-+{
-+	u8	bRet = _FALSE;
-+	u8	pg_header = 0, tmp_header = 0;
-+	u16	efuse_addr = *pAddr;
-+	u8	repeatcnt = 0;
-+
-+
-+	/*	RTW_INFO("%s\n", __FUNCTION__); */
-+	pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en;
-+
-+	efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
-+
-+	phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 0);
-+
-+	efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
-+
-+	phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 1);
-+
-+	while (tmp_header == 0xFF || pg_header != tmp_header) {
-+		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
-+				RTW_ERR("retry %d times fail!!\n", repeatcnt);
-+			return _FALSE;
-+		}
-+		efuse_OneByteWrite(pAdapter,efuse_addr, pg_header, bPseudoTest);
-+		efuse_OneByteRead(pAdapter,efuse_addr, &tmp_header, bPseudoTest);
-+		RTW_ERR("===>%s: Keep %d-th retrying,pg_header = 0x%X tmp_header = 0x%X\n", __FUNCTION__,repeatcnt, pg_header, tmp_header);
-+	}
-+
-+	if (pg_header == tmp_header)
-+		bRet = _TRUE;
-+	else {
-+		PGPKT_STRUCT	fixPkt;
-+
-+		RTW_ERR(" pg_header(0x%X) != tmp_header(0x%X)\n", pg_header, tmp_header);
-+		RTW_ERR("Error condition for fixed PG packet, need to cover the existed data: (Addr, Data) = (0x%X, 0x%X)\n",
-+						efuse_addr, tmp_header);
-+		fixPkt.offset = (tmp_header>>4) & 0x0F;
-+		fixPkt.word_en = tmp_header & 0x0F;
-+		fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
-+		if (!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
-+		return _FALSE;
-+	}
-+
-+	*pAddr = efuse_addr;
-+
-+	return _TRUE;
-+}
-+
-+static u8
-+hal_EfusePgPacketWrite2ByteHeader(
-+	PADAPTER		padapter,
-+	u8				efuseType,
-+	u16				*pAddr,
-+	PPGPKT_STRUCT	pTargetPkt,
-+	u8				bPseudoTest)
-+{
-+	u16	efuse_addr, efuse_max_available_len = 0;
-+	u8	pg_header = 0, tmp_header = 0, pg_header_temp = 0;
-+	u8	repeatcnt = 0;
-+
-+
-+	/*	RTW_INFO("%s\n", __FUNCTION__); */
-+	EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &efuse_max_available_len, bPseudoTest);
-+
-+	efuse_addr = *pAddr;
-+
-+	if (efuse_addr >= efuse_max_available_len) {
-+		RTW_INFO("%s: addr(%d) over avaliable(%d)!!\n", __FUNCTION__, efuse_addr, efuse_max_available_len);
-+		return _FALSE;
-+	}
-+
-+	while (efuse_addr < efuse_max_available_len) {
-+	pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
-+		efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
-+		phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
-+		efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
-+		phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
-+
-+		while (tmp_header == 0xFF || pg_header != tmp_header) {
-+		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
-+				RTW_INFO("%s, Repeat over limit for pg_header!!\n", __FUNCTION__);
-+			return _FALSE;
-+		}
-+
-+			efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
-+			efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
-+	}
-+
-+		/*to write ext_header*/
-+		if (tmp_header == pg_header) {
-+	efuse_addr++;
-+			pg_header_temp = pg_header;
-+	pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
-+
-+		efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
-+			phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
-+		efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
-+			phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
-+
-+			while (tmp_header == 0xFF || pg_header != tmp_header) {
-+		if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
-+					RTW_INFO("%s, Repeat over limit for ext_header!!\n", __FUNCTION__);
-+			return _FALSE;
-+		}
-+
-+				efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
-+				efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
-+			}
-+
-+			if ((tmp_header & 0x0F) == 0x0F) {
-+				if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
-+					RTW_INFO("Repeat over limit for word_en!!\n");
-+					return _FALSE;
-+				} else {
-+					efuse_addr++;
-+					continue;
-+				}
-+			} else if (pg_header != tmp_header) {
-+				PGPKT_STRUCT	fixPkt;
-+				RTW_ERR("Error, efuse_PgPacketWrite2ByteHeader(), offset PG fail, need to cover the existed data!!\n");
-+				RTW_ERR("Error condition for offset PG fail, need to cover the existed data\n");
-+				fixPkt.offset = ((pg_header_temp & 0xE0) >> 5) | ((tmp_header & 0xF0) >> 1);
-+				fixPkt.word_en = tmp_header & 0x0F;
-+				fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
-+				if (!hal_EfuseFixHeaderProcess(padapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
-+		return _FALSE;
-+			} else
-+				break;
-+		} else if ((tmp_header & 0x1F) == 0x0F) {/*wrong extended header*/
-+			efuse_addr += 2;
-+			continue;
-+		}
-+	}
-+
-+	*pAddr = efuse_addr;
-+
-+	return _TRUE;
-+}
-+
-+static u8
-+hal_EfusePgPacketWriteHeader(
-+	PADAPTER		padapter,
-+	u8				efuseType,
-+	u16				*pAddr,
-+	PPGPKT_STRUCT	pTargetPkt,
-+	u8				bPseudoTest)
-+{
-+	u8 bRet = _FALSE;
-+
-+	if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
-+		bRet = hal_EfusePgPacketWrite2ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
-+	else
-+		bRet = hal_EfusePgPacketWrite1ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
-+
-+	return bRet;
-+}
-+
-+static u8
-+hal_EfusePgPacketWriteData(
-+	PADAPTER		pAdapter,
-+	u8				efuseType,
-+	u16				*pAddr,
-+	PPGPKT_STRUCT	pTargetPkt,
-+	u8				bPseudoTest)
-+{
-+	u16	efuse_addr;
-+	u8	badworden;
-+	u8	PgWriteSuccess = 0;
-+
-+
-+	efuse_addr = *pAddr;
-+	badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr + 1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
-+	if (badworden == 0x0F) {
-+		RTW_INFO("%s: OK!!\n", __FUNCTION__);
-+			return _TRUE;
-+		} else {	/* Reorganize other pg packet */
-+			RTW_ERR ("Error, efuse_PgPacketWriteData(), wirte data fail!!\n");
-+			RTW_ERR ("efuse_PgPacketWriteData Fail!!\n");
-+			PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
-+			if (!PgWriteSuccess)
-+				return FALSE;
-+			else
-+				return TRUE;
-+		}
-+
-+	return _TRUE;
-+}
-+
-+static s32
-+Hal_EfusePgPacketWrite(
-+	PADAPTER	padapter,
-+	u8			offset,
-+	u8			word_en,
-+	u8			*pData,
-+	u8			bPseudoTest)
-+{
-+	PGPKT_STRUCT targetPkt;
-+	u16 startAddr = 0;
-+	u8 efuseType = EFUSE_WIFI;
-+
-+	if (!hal_EfusePgCheckAvailableAddr(padapter, efuseType, bPseudoTest))
-+		return _FALSE;
-+
-+	hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
-+
-+	if (!hal_EfusePartialWriteCheck(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
-+		return _FALSE;
-+
-+	if (!hal_EfusePgPacketWriteHeader(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
-+		return _FALSE;
-+
-+	if (!hal_EfusePgPacketWriteData(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
-+		return _FALSE;
-+
-+	return _TRUE;
-+}
-+
-+static u8
-+Hal_EfusePgPacketWrite_BT(
-+	PADAPTER	pAdapter,
-+	u8			offset,
-+	u8			word_en,
-+	u8			*pData,
-+	u8			bPseudoTest)
-+{
-+	PGPKT_STRUCT targetPkt;
-+	u16 startAddr = 0;
-+	u8 efuseType = EFUSE_BT;
-+
-+	if (!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest))
-+		return _FALSE;
-+
-+	hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
-+
-+	if (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
-+		return _FALSE;
-+
-+	if (!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
-+		return _FALSE;
-+
-+	if (!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
-+		return _FALSE;
-+
-+	return _TRUE;
-+}
-+
-+
-+static void read_chip_version_8703b(PADAPTER padapter)
-+{
-+	u32				value32;
-+	HAL_DATA_TYPE	*pHalData;
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	value32 = rtw_read32(padapter, REG_SYS_CFG);
-+	pHalData->version_id.ICType = CHIP_8703B;
-+	pHalData->version_id.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
-+	pHalData->version_id.RFType = RF_TYPE_1T1R;
-+	pHalData->version_id.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
-+	pHalData->version_id.CUTVersion = (value32 & CHIP_VER_RTL_MASK) >> CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
-+
-+	/* For regulator mode. by tynli. 2011.01.14 */
-+	pHalData->RegulatorMode = ((value32 & SPS_SEL) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
-+
-+	value32 = rtw_read32(padapter, REG_GPIO_OUTSTS);
-+	pHalData->version_id.ROMVer = ((value32 & RF_RL_ID) >> 20);	/* ROM code version. */
-+
-+	/* For multi-function consideration. Added by Roger, 2010.10.06. */
-+	pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
-+	value32 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
-+	pHalData->MultiFunc |= ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0);
-+	pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0);
-+	pHalData->MultiFunc |= ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0);
-+	pHalData->PolarityCtl = ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT);
-+
-+
-+#if 0
-+	/*  mark for chage to use efuse */
-+	if (IS_B_CUT(pHalData->version_id) || IS_C_CUT(pHalData->version_id)) {
-+		RTW_INFO(" IS_B/C_CUT SWR up 1 level !!!!!!!!!!!!!!!!!\n");
-+		phy_set_mac_reg(padapter, 0x14, BIT23 | BIT22 | BIT21 | BIT20, 0x5); /* MAC reg 0x14[23:20] = 4b'0101 (SWR 1.220V) */
-+	} else if (IS_D_CUT(pHalData->version_id))
-+		RTW_INFO(" IS_D_CUT SKIP SWR !!!!!!!!!!!!!!!!!\n");
-+#endif
-+
-+#if 1
-+	dump_chip_info(pHalData->version_id);
-+#endif
-+
-+}
-+
-+
-+void rtl8703b_InitBeaconParameters(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+	u16 val16;
-+	u8 val8;
-+
-+
-+	val8 = DIS_TSF_UDT;
-+	val16 = val8 | (val8 << 8); /* port0 and port1 */
-+#ifdef CONFIG_BT_COEXIST
-+	/* Enable prot0 beacon function for PSTDMA */
-+	val16 |= EN_BCN_FUNCTION;
-+#endif
-+	rtw_write16(padapter, REG_BCN_CTRL, val16);
-+
-+	/* TBTT setup time */
-+	rtw_write8(padapter, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME);
-+
-+	/* TBTT hold time: 0x540[19:8] */
-+	rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);
-+	rtw_write8(padapter, REG_TBTT_PROHIBIT + 2,
-+		(rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));
-+
-+	/* Firmware will control REG_DRVERLYINT when power saving is enable, */
-+	/* so don't set this register on STA mode. */
-+	if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _FALSE)
-+		rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8703B); /* 5ms */
-+	rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8703B); /* 2ms */
-+
-+	/* Suggested by designer timchen. Change beacon AIFS to the largest number */
-+	/* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */
-+	rtw_write16(padapter, REG_BCNTCFG, 0x4413);
-+
-+}
-+
-+void rtl8703b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode)
-+{
-+#ifdef CONFIG_ADHOC_WORKAROUND_SETTING
-+	rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF);
-+#else
-+	/* rtw_write8(Adapter, REG_BCN_MAX_ERR, (InfraMode ? 0xFF : 0x10)); */
-+#endif
-+}
-+
-+void	_InitBurstPktLen_8703BS(PADAPTER Adapter)
-+{
-+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
-+
-+	rtw_write8(Adapter, 0x4c7, rtw_read8(Adapter, 0x4c7) | BIT(7)); /* enable single pkt ampdu */
-+	rtw_write8(Adapter, REG_RX_PKT_LIMIT_8703B, 0x18);		/* for VHT packet length 11K */
-+	rtw_write8(Adapter, REG_MAX_AGGR_NUM_8703B, 0x1F);
-+	rtw_write8(Adapter, REG_PIFS_8703B, 0x00);
-+	rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8703B, rtw_read8(Adapter, REG_FWHW_TXQ_CTRL) & (~BIT(7)));
-+	if (pHalData->AMPDUBurstMode)
-+		rtw_write8(Adapter, REG_AMPDU_BURST_MODE_8703B,  0x5F);
-+	rtw_write8(Adapter, REG_AMPDU_MAX_TIME_8703B, 0x70);
-+
-+	/* ARFB table 9 for 11ac 5G 2SS */
-+	rtw_write32(Adapter, REG_ARFR0_8703B, 0x00000010);
-+	if (IS_NORMAL_CHIP(pHalData->version_id))
-+		rtw_write32(Adapter, REG_ARFR0_8703B + 4, 0xfffff000);
-+	else
-+		rtw_write32(Adapter, REG_ARFR0_8703B + 4, 0x3e0ff000);
-+
-+	/* ARFB table 10 for 11ac 5G 1SS */
-+	rtw_write32(Adapter, REG_ARFR1_8703B, 0x00000010);
-+	rtw_write32(Adapter, REG_ARFR1_8703B + 4, 0x003ff000);
-+}
-+
-+void _InitLTECoex_8703BS(PADAPTER Adapter)
-+{
-+	/* LTE COEX setting */
-+	rtw_write16(Adapter, REG_LTECOEX_WRITE_DATA, 0x7700);
-+	rtw_write32(Adapter, REG_LTECOEX_CTRL, 0xc0020038);
-+	rtw_write8(Adapter, 0x73, 0x04);
-+}
-+
-+void _InitMacAPLLSetting_8703B(PADAPTER Adapter)
-+{
-+	u16 RegValue;
-+
-+	RegValue = rtw_read16(Adapter, REG_AFE_CTRL_4_8703B);
-+	RegValue |= BIT(4);
-+	RegValue |= BIT(15);
-+	rtw_write16(Adapter, REG_AFE_CTRL_4_8703B, RegValue);
-+}
-+
-+
-+static void _BeaconFunctionEnable(PADAPTER padapter, u8 Enable, u8 Linked)
-+{
-+	rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
-+	rtw_write8(padapter, REG_RD_CTRL + 1, 0x6F);
-+}
-+
-+static void rtl8703b_SetBeaconRelatedRegisters(PADAPTER padapter)
-+{
-+	u8 val8;
-+	u32 value32;
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
-+	u32 bcn_ctrl_reg;
-+
-+	/* reset TSF, enable update TSF, correcting TSF On Beacon */
-+
-+	/* REG_MBSSID_BCN_SPACE */
-+	/* REG_BCNDMATIM */
-+	/* REG_ATIMWND */
-+	/* REG_TBTT_PROHIBIT */
-+	/* REG_DRVERLYINT */
-+	/* REG_BCN_MAX_ERR */
-+	/* REG_BCNTCFG */ /* (0x510) */
-+	/* REG_DUAL_TSF_RST */
-+	/* REG_BCN_CTRL */ /* (0x550) */
-+
-+
-+	bcn_ctrl_reg = REG_BCN_CTRL;
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (padapter->hw_port == HW_PORT1)
-+		bcn_ctrl_reg = REG_BCN_CTRL_1;
-+#endif
-+
-+	/*  */
-+	/* ATIM window */
-+	/*  */
-+	rtw_write16(padapter, REG_ATIMWND, 2);
-+
-+	/*  */
-+	/* Beacon interval (in unit of TU). */
-+	/*  */
-+	rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)&pmlmeinfo->bcn_interval);
-+
-+	rtl8703b_InitBeaconParameters(padapter);
-+
-+	rtw_write8(padapter, REG_SLOT, 0x09);
-+
-+	/*  */
-+	/* Reset TSF Timer to zero, added by Roger. 2008.06.24 */
-+	/*  */
-+	value32 = rtw_read32(padapter, REG_TCR);
-+	value32 &= ~TSFRST;
-+	rtw_write32(padapter, REG_TCR, value32);
-+
-+	value32 |= TSFRST;
-+	rtw_write32(padapter, REG_TCR, value32);
-+
-+	/* NOTE: Fix test chip's bug (about contention windows's randomness) */
-+	if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE | WIFI_MESH_STATE) == _TRUE) {
-+		rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
-+		rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
-+	}
-+
-+	_BeaconFunctionEnable(padapter, _TRUE, _TRUE);
-+
-+	ResumeTxBeacon(padapter);
-+	val8 = rtw_read8(padapter, bcn_ctrl_reg);
-+	val8 |= DIS_BCNQ_SUB;
-+	rtw_write8(padapter, bcn_ctrl_reg, val8);
-+}
-+
-+void hal_notch_filter_8703b(_adapter *adapter, bool enable)
-+{
-+	if (enable) {
-+		RTW_INFO("Enable notch filter\n");
-+		rtw_write8(adapter, rOFDM0_RxDSP + 1, rtw_read8(adapter, rOFDM0_RxDSP + 1) | BIT1);
-+	} else {
-+		RTW_INFO("Disable notch filter\n");
-+		rtw_write8(adapter, rOFDM0_RxDSP + 1, rtw_read8(adapter, rOFDM0_RxDSP + 1) & ~BIT1);
-+	}
-+}
-+
-+/*
-+ * Description: In normal chip, we should send some packet to Hw which will be used by Fw
-+ *			in FW LPS mode. The function is to fill the Tx descriptor of this packets, then
-+ *			Fw can tell Hw to send these packet derectly.
-+ * Added by tynli. 2009.10.15.
-+ *
-+ * type1:pspoll, type2:null */
-+void rtl8703b_fill_fake_txdesc(
-+	PADAPTER	padapter,
-+	u8			*pDesc,
-+	u32			BufferLen,
-+	u8			IsPsPoll,
-+	u8			IsBTQosNull,
-+	u8			bDataFrame)
-+{
-+	/* Clear all status */
-+	_rtw_memset(pDesc, 0, TXDESC_SIZE);
-+
-+	SET_TX_DESC_FIRST_SEG_8703B(pDesc, 1); /* bFirstSeg; */
-+	SET_TX_DESC_LAST_SEG_8703B(pDesc, 1); /* bLastSeg; */
-+
-+	SET_TX_DESC_OFFSET_8703B(pDesc, 0x28); /* Offset = 32 */
-+
-+	SET_TX_DESC_PKT_SIZE_8703B(pDesc, BufferLen); /* Buffer size + command header */
-+	SET_TX_DESC_QUEUE_SEL_8703B(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */
-+
-+	/* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */
-+	if (_TRUE == IsPsPoll)
-+		SET_TX_DESC_NAV_USE_HDR_8703B(pDesc, 1);
-+	else {
-+		SET_TX_DESC_HWSEQ_EN_8703B(pDesc, 1); /* Hw set sequence number */
-+		SET_TX_DESC_HWSEQ_SEL_8703B(pDesc, 0);
-+	}
-+
-+	if (_TRUE == IsBTQosNull)
-+		SET_TX_DESC_BT_INT_8703B(pDesc, 1);
-+
-+	SET_TX_DESC_USE_RATE_8703B(pDesc, 1); /* use data rate which is set by Sw */
-+	SET_TX_DESC_OWN_8703B((u8 *)pDesc, 1);
-+
-+	SET_TX_DESC_TX_RATE_8703B(pDesc, DESC8703B_RATE1M);
-+
-+	/*  */
-+	/* Encrypt the data frame if under security mode excepct null data. Suggested by CCW. */
-+	/*  */
-+	if (_TRUE == bDataFrame) {
-+		u32 EncAlg;
-+
-+		EncAlg = padapter->securitypriv.dot11PrivacyAlgrthm;
-+		switch (EncAlg) {
-+		case _NO_PRIVACY_:
-+			SET_TX_DESC_SEC_TYPE_8703B(pDesc, 0x0);
-+			break;
-+		case _WEP40_:
-+		case _WEP104_:
-+		case _TKIP_:
-+			SET_TX_DESC_SEC_TYPE_8703B(pDesc, 0x1);
-+			break;
-+		case _SMS4_:
-+			SET_TX_DESC_SEC_TYPE_8703B(pDesc, 0x2);
-+			break;
-+		case _AES_:
-+			SET_TX_DESC_SEC_TYPE_8703B(pDesc, 0x3);
-+			break;
-+		default:
-+			SET_TX_DESC_SEC_TYPE_8703B(pDesc, 0x0);
-+			break;
-+		}
-+	}
-+
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	/* USB interface drop packet if the checksum of descriptor isn't correct. */
-+	/* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */
-+	rtl8703b_cal_txdesc_chksum((struct tx_desc *)pDesc);
-+#endif
-+}
-+
-+void rtl8703b_InitAntenna_Selection(PADAPTER padapter)
-+{
-+#if 0
-+	PHAL_DATA_TYPE pHalData;
-+	u8 val;
-+
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+#if 0
-+	val = rtw_read8(padapter, REG_LEDCFG2);
-+	/* Let 8051 take control antenna settting */
-+	val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
-+	rtw_write8(padapter, REG_LEDCFG2, val);
-+#else
-+	/* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */
-+	/* TODO:  A better solution is configure it according EFUSE during the run-time. */
-+	phy_set_mac_reg(padapter, 0x64, BIT20, 0x0);		/* 0x66[4]=0	 */
-+	phy_set_mac_reg(padapter, 0x64, BIT24, 0x0);		/* 0x66[8]=0 */
-+	phy_set_mac_reg(padapter, 0x40, BIT4, 0x0);		   /* 0x40[4]=0	 */
-+	phy_set_mac_reg(padapter, 0x40, BIT3, 0x1);		   /* 0x40[3]=1	 */
-+	phy_set_mac_reg(padapter, 0x4C, BIT24, 0x1);      /* 0x4C[24:23]=10 */
-+	phy_set_mac_reg(padapter, 0x4C, BIT23, 0x0);      /* 0x4C[24:23]=10 */
-+	phy_set_bb_reg(padapter, 0x944, BIT1 | BIT0, 0x3);   /* 0x944[1:0]=11	 */
-+	phy_set_bb_reg(padapter, 0x930, bMaskByte0, 0x77);   /* 0x930[7:0]=77	  */
-+	phy_set_mac_reg(padapter, 0x38, BIT11, 0x1);       /* 0x38[11]=1 */
-+#endif
-+#endif
-+}
-+
-+void rtl8703b_CheckAntenna_Selection(PADAPTER padapter)
-+{
-+#if 0
-+	PHAL_DATA_TYPE pHalData;
-+	u8 val;
-+
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	val = rtw_read8(padapter, REG_LEDCFG2);
-+	/* Let 8051 take control antenna settting */
-+	if (!(val & BIT(7))) {
-+		val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
-+		rtw_write8(padapter, REG_LEDCFG2, val);
-+	}
-+#endif
-+}
-+void rtl8703b_DeinitAntenna_Selection(PADAPTER padapter)
-+{
-+#if 0
-+	PHAL_DATA_TYPE pHalData;
-+	u8 val;
-+
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	val = rtw_read8(padapter, REG_LEDCFG2);
-+	/* Let 8051 take control antenna settting */
-+	val &= ~BIT(7); /* DPDT_SEL_EN, clear 0x4C[23] */
-+	rtw_write8(padapter, REG_LEDCFG2, val);
-+#endif
-+}
-+
-+void init_hal_spec_8703b(_adapter *adapter)
-+{
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+
-+	hal_spec->ic_name = "rtl8703b";
-+	hal_spec->macid_num = 16;
-+	hal_spec->sec_cam_ent_num = 16;
-+	hal_spec->sec_cap = 0;
-+	hal_spec->macid_cap = MACID_DROP_INDIRECT;
-+	hal_spec->macid_txrpt = 0x8100;
-+	hal_spec->macid_txrpt_pgsz = 16;
-+
-+	hal_spec->rfpath_num_2g = 1;
-+	hal_spec->rfpath_num_5g = 0;
-+	hal_spec->rf_reg_path_num = hal_spec->rf_reg_path_avail_num = 1;
-+	hal_spec->rf_reg_trx_path_bmp = 0x11;
-+	hal_spec->max_tx_cnt = 1;
-+
-+	hal_spec->tx_nss_num = 1;
-+	hal_spec->rx_nss_num = 1;
-+	hal_spec->band_cap = BAND_CAP_2G;
-+	hal_spec->bw_cap = BW_CAP_20M | BW_CAP_40M;
-+	hal_spec->port_num = 2;
-+	hal_spec->proto_cap = PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N;
-+
-+	hal_spec->txgi_max = 63;
-+	hal_spec->txgi_pdbm = 2;
-+
-+	hal_spec->wl_func = 0
-+			    | WL_FUNC_P2P
-+			    | WL_FUNC_MIRACAST
-+			    | WL_FUNC_TDLS
-+			    ;
-+
-+	hal_spec->tx_aclt_unit_factor = 1;
-+
-+	hal_spec->pg_txpwr_saddr = 0x10;
-+	hal_spec->pg_txgi_diff_factor = 1;
-+
-+	rtw_macid_ctl_init_sleep_reg(adapter_to_macidctl(adapter)
-+		, REG_MACID_SLEEP, 0, 0, 0);
-+}
-+
-+void rtl8703b_init_default_value(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+	u8 i;
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	/* init default value */
-+	pHalData->fw_ractrl = _FALSE;
-+	if (!adapter_to_pwrctl(padapter)->bkeepfwalive)
-+		pHalData->LastHMEBoxNum = 0;
-+
-+	/* init phydm default value */
-+	pHalData->bIQKInitialized = _FALSE;
-+
-+	/* init Efuse variables */
-+	pHalData->EfuseUsedBytes = 0;
-+	pHalData->EfuseUsedPercentage = 0;
-+#ifdef HAL_EFUSE_MEMORY
-+	pHalData->EfuseHal.fakeEfuseBank = 0;
-+	pHalData->EfuseHal.fakeEfuseUsedBytes = 0;
-+	_rtw_memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE);
-+	_rtw_memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN);
-+	_rtw_memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
-+	pHalData->EfuseHal.BTEfuseUsedBytes = 0;
-+	pHalData->EfuseHal.BTEfuseUsedPercentage = 0;
-+	_rtw_memset(pHalData->EfuseHal.BTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE);
-+	_rtw_memset(pHalData->EfuseHal.BTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
-+	_rtw_memset(pHalData->EfuseHal.BTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
-+	pHalData->EfuseHal.fakeBTEfuseUsedBytes = 0;
-+	_rtw_memset(pHalData->EfuseHal.fakeBTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE);
-+	_rtw_memset(pHalData->EfuseHal.fakeBTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
-+	_rtw_memset(pHalData->EfuseHal.fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
-+#endif
-+}
-+
-+u8 GetEEPROMSize8703B(PADAPTER padapter)
-+{
-+	u8 size = 0;
-+	u32	cr;
-+
-+	cr = rtw_read16(padapter, REG_9346CR);
-+	/* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */
-+	size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
-+
-+	RTW_INFO("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46");
-+
-+	return size;
-+}
-+
-+/* -------------------------------------------------------------------------
-+ *
-+ * LLT R/W/Init function
-+ *
-+ * ------------------------------------------------------------------------- */
-+s32 rtl8703b_InitLLTTable(PADAPTER padapter)
-+{
-+	systime start;
-+	u32 passing_time;
-+	u32 val32;
-+	s32 ret;
-+
-+
-+	ret = _FAIL;
-+
-+	val32 = rtw_read32(padapter, REG_AUTO_LLT);
-+	val32 |= BIT_AUTO_INIT_LLT;
-+	rtw_write32(padapter, REG_AUTO_LLT, val32);
-+
-+	start = rtw_get_current_time();
-+
-+	do {
-+		val32 = rtw_read32(padapter, REG_AUTO_LLT);
-+		if (!(val32 & BIT_AUTO_INIT_LLT)) {
-+			ret = _SUCCESS;
-+			break;
-+		}
-+
-+		passing_time = rtw_get_passing_time_ms(start);
-+		if (passing_time > 1000) {
-+			RTW_INFO("%s: FAIL!! REG_AUTO_LLT(0x%X)=%08x\n",
-+				 __FUNCTION__, REG_AUTO_LLT, val32);
-+			break;
-+		}
-+
-+		rtw_usleep_os(2);
-+	} while (1);
-+
-+	return ret;
-+}
-+
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+void _DisableGPIO(PADAPTER	padapter)
-+{
-+#if 0
-+	/* **************************************
-+	 * j. GPIO_PIN_CTRL 0x44[31:0]=0x000
-+	 * k.Value = GPIO_PIN_CTRL[7:0]
-+	 * l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8);  write external PIN level
-+	 * m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
-+	 * n. LEDCFG 0x4C[15:0] = 0x8080
-+	 * ************************************** */
-+#endif
-+	u8	value8;
-+	u16	value16;
-+	u32	value32;
-+	u32	u4bTmp;
-+
-+
-+	/* 1. Disable GPIO[7:0] */
-+	rtw_write16(padapter, REG_GPIO_PIN_CTRL + 2, 0x0000);
-+	value32 = rtw_read32(padapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
-+	u4bTmp = value32 & 0x000000FF;
-+	value32 |= ((u4bTmp << 8) | 0x00FF0000);
-+	rtw_write32(padapter, REG_GPIO_PIN_CTRL, value32);
-+
-+
-+	/* 2. Disable GPIO[10:8] */
-+	rtw_write8(padapter, REG_MAC_PINMUX_CFG, 0x00);
-+	value16 = rtw_read16(padapter, REG_GPIO_IO_SEL) & 0xFF0F;
-+	value8 = (u8)(value16 & 0x000F);
-+	value16 |= ((value8 << 4) | 0x0780);
-+	rtw_write16(padapter, REG_GPIO_IO_SEL, value16);
-+
-+
-+	/* 3. Disable LED0 & 1 */
-+	rtw_write16(padapter, REG_LEDCFG0, 0x8080);
-+
-+} /* end of _DisableGPIO() */
-+
-+void _DisableRFAFEAndResetBB8703B(PADAPTER padapter)
-+{
-+#if 0
-+	/* *************************************
-+	 * a.	TXPAUSE 0x522[7:0] = 0xFF              Pause MAC TX queue
-+	 * b.	RF path 0 offset 0x00 = 0x00              disable RF
-+	 * c.	APSD_CTRL 0x600[7:0] = 0x40
-+	 * d.	SYS_FUNC_EN 0x02[7:0] = 0x16		 reset BB state machine
-+	 * e.	SYS_FUNC_EN 0x02[7:0] = 0x14		 reset BB state machine
-+	 * ************************************** */
-+#endif
-+	enum rf_path eRFPath = RF_PATH_A, value8 = 0;
-+
-+	rtw_write8(padapter, REG_TXPAUSE, 0xFF);
-+
-+	phy_set_rf_reg(padapter, eRFPath, 0x0, bMaskByte0, 0x0);
-+
-+	value8 |= APSDOFF;
-+	rtw_write8(padapter, REG_APSD_CTRL, value8);/* 0x40 */
-+
-+	/* Set BB reset at first */
-+	value8 = 0 ;
-+	value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
-+	rtw_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x16 */
-+
-+	/* Set global reset. */
-+	value8 &= ~FEN_BB_GLB_RSTn;
-+	rtw_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x14 */
-+
-+	/* 2010/08/12 MH We need to set BB/GLBAL reset to save power for SS mode. */
-+
-+}
-+
-+void _DisableRFAFEAndResetBB(PADAPTER padapter)
-+{
-+	_DisableRFAFEAndResetBB8703B(padapter);
-+}
-+
-+void _ResetDigitalProcedure1_8703B(PADAPTER padapter, BOOLEAN bWithoutHWSM)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	if (IS_FW_81xxC(padapter) && (pHalData->firmware_version <= 0x20)) {
-+#if 0
-+#if 0
-+		/* **************************** */
-+		/* f.	SYS_FUNC_EN 0x03[7:0]=0x54		  reset MAC register, DCORE */
-+		/* g.	MCUFWDL 0x80[7:0]=0				  reset MCU ready status
-+		* ***************************** */
-+#endif
-+		u32	value32 = 0;
-+		rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54);
-+		rtw_write8(padapter, REG_MCUFWDL, 0);
-+#else
-+#if 0
-+		/* **************************** */
-+		/* f.	MCUFWDL 0x80[7:0]=0				  reset MCU ready status */
-+		/* g.	SYS_FUNC_EN 0x02[10]= 0			  reset MCU register, (8051 reset) */
-+		/* h.	SYS_FUNC_EN 0x02[15-12]= 5		  reset MAC register, DCORE */
-+		/* i.     SYS_FUNC_EN 0x02[10]= 1			  enable MCU register, (8051 enable) */
-+		/* ***************************** */
-+#endif
-+		u16 valu16 = 0;
-+		rtw_write8(padapter, REG_MCUFWDL, 0);
-+
-+		valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN);
-+		rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));/* reset MCU ,8051 */
-+
-+		valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN) & 0x0FFF;
-+		rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 | (FEN_HWPDN | FEN_ELDR))); /* reset MAC */
-+
-+		valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN);
-+		rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));/* enable MCU ,8051 */
-+#endif
-+	} else {
-+		u8 retry_cnts = 0;
-+
-+		/* 2010/08/12 MH For USB SS, we can not stop 8051 when we are trying to */
-+		/* enter IPS/HW&SW radio off. For S3/S4/S5/Disable, we can stop 8051 because */
-+		/* we will init FW when power on again. */
-+		/* if(!pDevice->RegUsbSS) */
-+		{	/* If we want to SS mode, we can not reset 8051. */
-+			if (rtw_read8(padapter, REG_MCUFWDL) & BIT1) {
-+				/* IF fw in RAM code, do reset */
-+
-+
-+				if (pHalData->bFWReady) {
-+					/* 2010/08/25 MH Accordign to RD alfred's suggestion, we need to disable other */
-+					/* HRCV INT to influence 8051 reset. */
-+					rtw_write8(padapter, REG_FWIMR, 0x20);
-+					/* 2011/02/15 MH According to Alex's suggestion, close mask to prevent incorrect FW write operation. */
-+					rtw_write8(padapter, REG_FTIMR, 0x00);
-+					rtw_write8(padapter, REG_FSIMR, 0x00);
-+
-+					rtw_write8(padapter, REG_HMETFR + 3, 0x20); /* 8051 reset by self */
-+
-+					while ((retry_cnts++ < 100) && (FEN_CPUEN & rtw_read16(padapter, REG_SYS_FUNC_EN))) {
-+						rtw_udelay_os(50);/* us */
-+						/* 2010/08/25 For test only We keep on reset 5051 to prevent fail. */
-+						/* rtw_write8(padapter, REG_HMETFR+3, 0x20); */ /* 8051 reset by self */
-+					}
-+					/*					RT_ASSERT((retry_cnts < 100), ("8051 reset failed!\n")); */
-+
-+					if (retry_cnts >= 100) {
-+						/* if 8051 reset fail we trigger GPIO 0 for LA */
-+						/* rtw_write32(	padapter, */
-+						/*						REG_GPIO_PIN_CTRL, */
-+						/*						0x00010100); */
-+						/* 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly. */
-+						rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x50);	/* Reset MAC and Enable 8051 */
-+						rtw_mdelay_os(10);
-+					}
-+
-+				}
-+			}
-+
-+			rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54);	/* Reset MAC and Enable 8051 */
-+			rtw_write8(padapter, REG_MCUFWDL, 0);
-+		}
-+	}
-+
-+	/* if(pDevice->RegUsbSS) */
-+	/* bWithoutHWSM = TRUE;	 */ /* Sugest by Filen and Issau. */
-+
-+	if (bWithoutHWSM) {
-+		/* HAL_DATA_TYPE		*pHalData	= GET_HAL_DATA(padapter); */
-+#if 0
-+		/* **************************** */
-+		/* Without HW auto state machine */
-+		/* g.	SYS_CLKR 0x08[15:0] = 0x30A3			 disable MAC clock */
-+		/* h.	AFE_PLL_CTRL 0x28[7:0] = 0x80			 disable AFE PLL */
-+		/* i.	AFE_XTAL_CTRL 0x24[15:0] = 0x880F		 gated AFE DIG_CLOCK */
-+		/* j.	SYS_ISO_CTRL 0x00[7:0] = 0xF9			  isolated digital to PON */
-+		/* ***************************** */
-+#endif
-+		/* rtw_write16(padapter, REG_SYS_CLKR, 0x30A3); */
-+		/* if(!pDevice->RegUsbSS) */
-+		/* 2011/01/26 MH SD4 Scott suggest to fix UNC-B cut bug. */
-+		rtw_write16(padapter, REG_SYS_CLKR, 0x70A3);  /* modify to 0x70A3 by Scott. */
-+		rtw_write8(padapter, REG_AFE_PLL_CTRL, 0x80);
-+		rtw_write16(padapter, REG_AFE_XTAL_CTRL, 0x880F);
-+		/* if(!pDevice->RegUsbSS) */
-+		rtw_write8(padapter, REG_SYS_ISO_CTRL, 0xF9);
-+	} else {
-+		/* Disable all RF/BB power */
-+		rtw_write8(padapter, REG_RF_CTRL, 0x00);
-+	}
-+
-+}
-+
-+void _ResetDigitalProcedure1(PADAPTER padapter, BOOLEAN bWithoutHWSM)
-+{
-+	_ResetDigitalProcedure1_8703B(padapter, bWithoutHWSM);
-+}
-+
-+void _ResetDigitalProcedure2(PADAPTER padapter)
-+{
-+	/* HAL_DATA_TYPE		*pHalData	= GET_HAL_DATA(padapter); */
-+#if 0
-+	/* ****************************
-+	 * k.	SYS_FUNC_EN 0x03[7:0] = 0x44			  disable ELDR runction
-+	 * l.	SYS_CLKR 0x08[15:0] = 0x3083			  disable ELDR clock
-+	 * m.	SYS_ISO_CTRL 0x01[7:0] = 0x83			  isolated ELDR to PON
-+	 * ***************************** */
-+#endif
-+	/* rtw_write8(padapter, REG_SYS_FUNC_EN+1, 0x44); */ /* marked by Scott. */
-+	/* 2011/01/26 MH SD4 Scott suggest to fix UNC-B cut bug. */
-+	rtw_write16(padapter, REG_SYS_CLKR, 0x70a3); /* modify to 0x70a3 by Scott. */
-+	rtw_write8(padapter, REG_SYS_ISO_CTRL + 1, 0x82); /* modify to 0x82 by Scott. */
-+}
-+
-+void _DisableAnalog(PADAPTER padapter, BOOLEAN bWithoutHWSM)
-+{
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
-+	u16 value16 = 0;
-+	u8 value8 = 0;
-+
-+
-+	if (bWithoutHWSM) {
-+#if 0
-+		/* **************************** */
-+		/* n.	LDOA15_CTRL 0x20[7:0] = 0x04		  disable A15 power */
-+		/* o.	LDOV12D_CTRL 0x21[7:0] = 0x54		  disable digital core power */
-+		/* r.	When driver call disable, the ASIC will turn off remaining clock automatically */
-+		/* ***************************** */
-+#endif
-+
-+		rtw_write8(padapter, REG_LDOA15_CTRL, 0x04);
-+		/* rtw_write8(padapter, REG_LDOV12D_CTRL, 0x54); */
-+
-+		value8 = rtw_read8(padapter, REG_LDOV12D_CTRL);
-+		value8 &= (~LDV12_EN);
-+		rtw_write8(padapter, REG_LDOV12D_CTRL, value8);
-+	}
-+
-+#if 0
-+	/* **************************** */
-+	/* h.	SPS0_CTRL 0x11[7:0] = 0x23			 enter PFM mode */
-+	/* i.	APS_FSMCO 0x04[15:0] = 0x4802		  set USB suspend */
-+	/* ***************************** */
-+#endif
-+	value8 = 0x23;
-+
-+	rtw_write8(padapter, REG_SPS0_CTRL, value8);
-+
-+	if (bWithoutHWSM) {
-+		/* value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN); */
-+		/* 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically. */
-+		/* Becasue suspend operatione need the asistance of 8051 to wait for 3ms. */
-+		value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
-+	} else
-+		value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
-+
-+	rtw_write16(padapter, REG_APS_FSMCO, value16);/* 0x4802 */
-+
-+	rtw_write8(padapter, REG_RSV_CTRL, 0x0e);
-+
-+#if 0
-+	/* tynli_test for suspend mode. */
-+	if (!bWithoutHWSM)
-+		rtw_write8(padapter, 0xfe10, 0x19);
-+#endif
-+
-+}
-+
-+/* HW Auto state machine */
-+s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU)
-+{
-+	int rtStatus = _SUCCESS;
-+
-+
-+	if (RTW_CANNOT_RUN(padapter))
-+		return rtStatus;
-+
-+	/* ==== RF Off Sequence ==== */
-+	_DisableRFAFEAndResetBB(padapter);
-+
-+	/* ==== Reset digital sequence   ====== */
-+	_ResetDigitalProcedure1(padapter, _FALSE);
-+
-+	/* ==== Pull GPIO PIN to balance level and LED control ====== */
-+	_DisableGPIO(padapter);
-+
-+	/* ==== Disable analog sequence === */
-+	_DisableAnalog(padapter, _FALSE);
-+
-+
-+	return rtStatus;
-+}
-+
-+/* without HW Auto state machine */
-+s32 CardDisableWithoutHWSM(PADAPTER padapter)
-+{
-+	s32 rtStatus = _SUCCESS;
-+
-+
-+	if (RTW_CANNOT_RUN(padapter))
-+		return rtStatus;
-+
-+
-+	/* ==== RF Off Sequence ==== */
-+	_DisableRFAFEAndResetBB(padapter);
-+
-+	/* ==== Reset digital sequence   ====== */
-+	_ResetDigitalProcedure1(padapter, _TRUE);
-+
-+	/* ==== Pull GPIO PIN to balance level and LED control ====== */
-+	_DisableGPIO(padapter);
-+
-+	/* ==== Reset digital sequence   ====== */
-+	_ResetDigitalProcedure2(padapter);
-+
-+	/* ==== Disable analog sequence === */
-+	_DisableAnalog(padapter, _TRUE);
-+
-+	return rtStatus;
-+}
-+#endif /* CONFIG_USB_HCI || CONFIG_SDIO_HCI || CONFIG_GSPI_HCI */
-+
-+void
-+Hal_InitPGData(
-+	PADAPTER	padapter,
-+	u8			*PROMContent)
-+{
-+
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	u32			i;
-+	u16			value16;
-+
-+	if (_FALSE == pHalData->bautoload_fail_flag) {
-+		/* autoload OK.
-+		*		if (IS_BOOT_FROM_EEPROM(padapter)) */
-+		if (_TRUE == pHalData->EepromOrEfuse) {
-+			/* Read all Content from EEPROM or EFUSE. */
-+			for (i = 0; i < HWSET_MAX_SIZE_8703B; i += 2) {
-+				/*				value16 = EF2Byte(ReadEEprom(pAdapter, (u16) (i>>1)));
-+				 *				*((u16*)(&PROMContent[i])) = value16; */
-+			}
-+		} else {
-+			/* Read EFUSE real map to shadow. */
-+			EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE);
-+		}
-+	} else {
-+		/* autoload fail */
-+		/*		pHalData->AutoloadFailFlag = _TRUE; */
-+		/* update to default value 0xFF */
-+		if (_FALSE == pHalData->EepromOrEfuse)
-+			EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE);
-+	}
-+
-+#ifdef CONFIG_EFUSE_CONFIG_FILE
-+	if (check_phy_efuse_tx_power_info_valid(padapter) == _FALSE) {
-+		if (Hal_readPGDataFromConfigFile(padapter) != _SUCCESS)
-+			RTW_ERR("invalid phy efuse and read from file fail, will use driver default!!\n");
-+	}
-+#endif
-+}
-+
-+void
-+Hal_EfuseParseIDCode(
-+		PADAPTER	padapter,
-+		u8			*hwinfo
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	u16			EEPROMId;
-+
-+
-+	/* Checl 0x8129 again for making sure autoload status!! */
-+	EEPROMId = le16_to_cpu(*((u16 *)hwinfo));
-+	if (EEPROMId != RTL_EEPROM_ID) {
-+		RTW_INFO("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
-+		pHalData->bautoload_fail_flag = _TRUE;
-+	} else
-+		pHalData->bautoload_fail_flag = _FALSE;
-+
-+}
-+void
-+Hal_EfuseParseTxPowerInfo_8703B(
-+		PADAPTER		padapter,
-+		u8			*PROMContent,
-+		BOOLEAN			AutoLoadFail
-+)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+
-+	pHalData->txpwr_pg_mode = TXPWR_PG_WITH_PWR_IDX;
-+
-+	/* 2010/10/19 MH Add Regulator recognize for CU. */
-+	if (!AutoLoadFail) {
-+		pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_8703B] & 0x7);	/* bit0~2 */
-+		if (PROMContent[EEPROM_RF_BOARD_OPTION_8703B] == 0xFF)
-+			pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION & 0x7);	/* bit0~2 */
-+	} else
-+		pHalData->EEPROMRegulatory = 0;
-+}
-+
-+void
-+Hal_EfuseParseBoardType_8703B(
-+		PADAPTER	Adapter,
-+		u8			*PROMContent,
-+		BOOLEAN		AutoloadFail
-+)
-+{
-+
-+
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+
-+	if (!AutoloadFail) {
-+		pHalData->InterfaceSel = (PROMContent[EEPROM_RF_BOARD_OPTION_8703B] & 0xE0) >> 5;
-+		if (PROMContent[EEPROM_RF_BOARD_OPTION_8703B] == 0xFF)
-+			pHalData->InterfaceSel = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5;
-+	} else
-+		pHalData->InterfaceSel = 0;
-+
-+}
-+
-+void
-+Hal_EfuseParseBTCoexistInfo_8703B(
-+	PADAPTER			padapter,
-+	u8			*hwinfo,
-+	BOOLEAN			AutoLoadFail
-+)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	u8			tempval;
-+	u32			tmpu4;
-+
-+	if (!AutoLoadFail) {
-+		tmpu4 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
-+		if (tmpu4 & BT_FUNC_EN)
-+			pHalData->EEPROMBluetoothCoexist = _TRUE;
-+		else
-+			pHalData->EEPROMBluetoothCoexist = _FALSE;
-+
-+		pHalData->EEPROMBluetoothType = BT_RTL8703B;
-+
-+		tempval = hwinfo[EEPROM_RF_BT_SETTING_8703B];
-+		if (tempval != 0xFF) {
-+			pHalData->EEPROMBluetoothAntNum = tempval & BIT(0);
-+#ifdef CONFIG_USB_HCI
-+			/*if(rtw_get_intf_type(padapter) == RTW_USB)*/
-+			pHalData->ant_path = RF_PATH_B; /* s0 */
-+#else /* SDIO or PCIE */
-+			/* EFUSE_0xC3[6] == 0, S1(Main)-RF_PATH_A; */
-+			/* EFUSE_0xC3[6] == 1, S0(Aux)-RF_PATH_B */
-+			pHalData->ant_path = (tempval & BIT(6)) ? RF_PATH_B : RF_PATH_A;
-+#endif
-+		} else {
-+			pHalData->EEPROMBluetoothAntNum = Ant_x1;
-+#ifdef CONFIG_USB_HCI
-+			pHalData->ant_path = RF_PATH_B;/* s0 */
-+#else
-+			pHalData->ant_path = RF_PATH_A;
-+#endif
-+		}
-+	} else {
-+		if (padapter->registrypriv.mp_mode == 1)
-+			pHalData->EEPROMBluetoothCoexist = _TRUE;
-+		else
-+			pHalData->EEPROMBluetoothCoexist = _FALSE;
-+		pHalData->EEPROMBluetoothType = BT_RTL8703B;
-+		pHalData->EEPROMBluetoothAntNum = Ant_x1;
-+#ifdef CONFIG_USB_HCI
-+		pHalData->ant_path = RF_PATH_B;/* s0 */
-+#else
-+		pHalData->ant_path = RF_PATH_A;
-+#endif
-+	}
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if (padapter->registrypriv.ant_num > 0) {
-+		RTW_INFO("%s: Apply driver defined antenna number(%d) to replace origin(%d)\n",
-+			 __FUNCTION__,
-+			 padapter->registrypriv.ant_num,
-+			 pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);
-+
-+		switch (padapter->registrypriv.ant_num) {
-+		case 1:
-+			pHalData->EEPROMBluetoothAntNum = Ant_x1;
-+			break;
-+		case 2:
-+			pHalData->EEPROMBluetoothAntNum = Ant_x2;
-+			break;
-+		default:
-+			RTW_INFO("%s: Discard invalid driver defined antenna number(%d)!\n",
-+				 __FUNCTION__, padapter->registrypriv.ant_num);
-+			break;
-+		}
-+	}
-+#endif /* CONFIG_BT_COEXIST */
-+
-+	RTW_INFO("%s: %s BT-coex, ant_num=%d\n",
-+		 __FUNCTION__,
-+		pHalData->EEPROMBluetoothCoexist == _TRUE ? "Enable" : "Disable",
-+		 pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);
-+}
-+
-+void
-+Hal_EfuseParseEEPROMVer_8703B(
-+		PADAPTER		padapter,
-+		u8			*hwinfo,
-+		BOOLEAN			AutoLoadFail
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	if (!AutoLoadFail)
-+		pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8703B];
-+	else
-+		pHalData->EEPROMVersion = 1;
-+}
-+
-+void
-+Hal_EfuseParseVoltage_8703B(
-+		PADAPTER		pAdapter,
-+		u8			*hwinfo,
-+		BOOLEAN	AutoLoadFail
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+
-+	/* _rtw_memcpy(pHalData->adjuseVoltageVal, &hwinfo[EEPROM_Voltage_ADDR_8703B], 1); */
-+	RTW_INFO("%s hwinfo[EEPROM_Voltage_ADDR_8703B] =%02x\n", __func__, hwinfo[EEPROM_Voltage_ADDR_8703B]);
-+	pHalData->adjuseVoltageVal = (hwinfo[EEPROM_Voltage_ADDR_8703B] & 0xf0) >> 4 ;
-+	RTW_INFO("%s pHalData->adjuseVoltageVal =%x\n", __func__, pHalData->adjuseVoltageVal);
-+}
-+
-+void
-+Hal_EfuseParseChnlPlan_8703B(
-+		PADAPTER		padapter,
-+		u8			*hwinfo,
-+		BOOLEAN			AutoLoadFail
-+)
-+{
-+	hal_com_config_channel_plan(
-+		padapter
-+		, hwinfo ? &hwinfo[EEPROM_COUNTRY_CODE_8703B] : NULL
-+		, hwinfo ? hwinfo[EEPROM_ChannelPlan_8703B] : 0xFF
-+		, padapter->registrypriv.alpha2
-+		, padapter->registrypriv.channel_plan
-+		, AutoLoadFail
-+	);
-+}
-+
-+void
-+Hal_EfuseParseCustomerID_8703B(
-+		PADAPTER		padapter,
-+		u8			*hwinfo,
-+		BOOLEAN			AutoLoadFail
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	if (!AutoLoadFail)
-+		pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8703B];
-+	else
-+		pHalData->EEPROMCustomerID = 0;
-+}
-+
-+void
-+Hal_EfuseParseAntennaDiversity_8703B(
-+		PADAPTER		pAdapter,
-+		u8				*hwinfo,
-+		BOOLEAN			AutoLoadFail
-+)
-+{
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(pAdapter);
-+	struct registry_priv	*registry_par = &pAdapter->registrypriv;
-+
-+	if (pHalData->EEPROMBluetoothAntNum == Ant_x1)
-+		pHalData->AntDivCfg = 0;
-+	else {
-+		if (registry_par->antdiv_cfg == 2) /* 0:OFF , 1:ON, 2:By EFUSE */
-+			pHalData->AntDivCfg = 1;
-+		else
-+			pHalData->AntDivCfg = registry_par->antdiv_cfg;
-+	}
-+
-+	/* If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. */
-+	if (registry_par->antdiv_type == 0) {
-+		pHalData->TRxAntDivType = hwinfo[EEPROM_RFE_OPTION_8703B];
-+		if (pHalData->TRxAntDivType == 0xFF)
-+			pHalData->TRxAntDivType = S0S1_SW_ANTDIV;/* GetRegAntDivType(pAdapter); */
-+		else if (pHalData->TRxAntDivType == 0x10)
-+			pHalData->TRxAntDivType = S0S1_SW_ANTDIV; /* intrnal switch S0S1 */
-+		else if (pHalData->TRxAntDivType == 0x11)
-+			pHalData->TRxAntDivType = S0S1_SW_ANTDIV; /* intrnal switch S0S1 */
-+		else
-+			RTW_INFO("%s: efuse[0x%x]=0x%02x is unknown type\n",
-+				__FUNCTION__, EEPROM_RFE_OPTION_8703B, pHalData->TRxAntDivType);
-+	} else {
-+		pHalData->TRxAntDivType = registry_par->antdiv_type ;/* GetRegAntDivType(pAdapter); */
-+	}
-+
-+	RTW_INFO("%s: AntDivCfg=%d, AntDivType=%d\n",
-+		 __FUNCTION__, pHalData->AntDivCfg, pHalData->TRxAntDivType);
-+#endif
-+}
-+
-+void
-+Hal_EfuseParseXtal_8703B(
-+		PADAPTER		pAdapter,
-+		u8			*hwinfo,
-+		BOOLEAN		AutoLoadFail
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+
-+	if (!AutoLoadFail) {
-+		pHalData->crystal_cap = hwinfo[EEPROM_XTAL_8703B];
-+		if (pHalData->crystal_cap == 0xFF)
-+			pHalData->crystal_cap = EEPROM_Default_CrystalCap_8703B;	   /* what value should 8812 set? */
-+	} else
-+		pHalData->crystal_cap = EEPROM_Default_CrystalCap_8703B;
-+}
-+
-+
-+void
-+Hal_EfuseParseThermalMeter_8703B(
-+	PADAPTER	padapter,
-+	u8			*PROMContent,
-+	u8			AutoLoadFail
-+)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+
-+	/*  */
-+	/* ThermalMeter from EEPROM */
-+	/*  */
-+	if (_FALSE == AutoLoadFail)
-+		pHalData->eeprom_thermal_meter = PROMContent[EEPROM_THERMAL_METER_8703B];
-+	else
-+		pHalData->eeprom_thermal_meter = EEPROM_Default_ThermalMeter_8703B;
-+
-+	if ((pHalData->eeprom_thermal_meter == 0xff) || (_TRUE == AutoLoadFail)) {
-+		pHalData->odmpriv.rf_calibrate_info.is_apk_thermal_meter_ignore = _TRUE;
-+		pHalData->eeprom_thermal_meter = EEPROM_Default_ThermalMeter_8703B;
-+	}
-+
-+}
-+
-+
-+void Hal_ReadRFGainOffset(
-+			PADAPTER		Adapter,
-+			u8			*PROMContent,
-+			BOOLEAN		AutoloadFail)
-+{
-+#ifdef CONFIG_RF_POWER_TRIM
-+
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	struct kfree_data_t *kfree_data = &pHalData->kfree_data;
-+	u8 pg_pwrtrim = 0xFF, pg_therm = 0xFF;
-+
-+	RTW_INFO("%s,  Pwr Trim Enable config:%d\n", __func__, Adapter->registrypriv.RegPwrTrimEnable);
-+
-+	if ((Adapter->registrypriv.RegPwrTrimEnable == 1) || !AutoloadFail) {
-+		efuse_OneByteRead(Adapter, PPG_BB_GAIN_2G_TXA_OFFSET_8703B, &pg_pwrtrim, _FALSE);
-+		efuse_OneByteRead(Adapter, PPG_THERMAL_OFFSET_8703B, &pg_therm, _FALSE);
-+
-+		kfree_data->bb_gain[BB_GAIN_2G][RF_PATH_A]
-+			= KFREE_BB_GAIN_2G_TX_OFFSET(pg_pwrtrim & PPG_BB_GAIN_2G_TX_OFFSET_MASK);
-+		kfree_data->thermal
-+			= KFREE_THERMAL_OFFSET(pg_therm & PPG_THERMAL_OFFSET_MASK);
-+
-+		if (GET_PG_KFREE_ON_8703B(PROMContent) && PROMContent[0xc1] != 0xff)
-+			kfree_data->flag |= KFREE_FLAG_ON;
-+		if (GET_PG_KFREE_THERMAL_K_ON_8703B(PROMContent) && PROMContent[0xc8] != 0xff)
-+			kfree_data->flag |= KFREE_FLAG_THERMAL_K_ON;
-+	}
-+
-+	if (Adapter->registrypriv.RegPwrTrimEnable == 1) {
-+		kfree_data->flag |= KFREE_FLAG_ON;
-+		kfree_data->flag |= KFREE_FLAG_THERMAL_K_ON;
-+	}
-+
-+	if (kfree_data->flag & KFREE_FLAG_THERMAL_K_ON)
-+		pHalData->eeprom_thermal_meter += kfree_data->thermal;
-+
-+	RTW_INFO("kfree flag:%u\n", kfree_data->flag);
-+	if (Adapter->registrypriv.RegPwrTrimEnable == 1 || kfree_data->flag & KFREE_FLAG_ON)
-+		RTW_INFO("bb_gain:%d\n", kfree_data->bb_gain[BB_GAIN_2G][RF_PATH_A]);
-+	if (Adapter->registrypriv.RegPwrTrimEnable == 1 || kfree_data->flag & KFREE_FLAG_THERMAL_K_ON)
-+		RTW_INFO("thermal:%d\n", kfree_data->thermal);
-+
-+#endif /*CONFIG_RF_POWER_TRIM */
-+
-+}
-+
-+
-+u8
-+BWMapping_8703B(
-+		PADAPTER		Adapter,
-+		struct pkt_attrib	*pattrib
-+)
-+{
-+	u8	BWSettingOfDesc = 0;
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+
-+	/* RTW_INFO("BWMapping pHalData->current_channel_bw %d, pattrib->bwmode %d\n",pHalData->current_channel_bw,pattrib->bwmode); */
-+
-+	if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
-+		if (pattrib->bwmode == CHANNEL_WIDTH_80)
-+			BWSettingOfDesc = 2;
-+		else if (pattrib->bwmode == CHANNEL_WIDTH_40)
-+			BWSettingOfDesc = 1;
-+		else
-+			BWSettingOfDesc = 0;
-+	} else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
-+		if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80))
-+			BWSettingOfDesc = 1;
-+		else
-+			BWSettingOfDesc = 0;
-+	} else
-+		BWSettingOfDesc = 0;
-+
-+	/* if(pTcb->bBTTxPacket) */
-+	/*	BWSettingOfDesc = 0; */
-+
-+	return BWSettingOfDesc;
-+}
-+
-+u8	SCMapping_8703B(PADAPTER Adapter, struct pkt_attrib *pattrib)
-+{
-+	u8	SCSettingOfDesc = 0;
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+
-+	/* RTW_INFO("SCMapping: pHalData->current_channel_bw %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d\n",pHalData->current_channel_bw,pHalData->nCur80MhzPrimeSC,pHalData->nCur40MhzPrimeSC); */
-+
-+	if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
-+		if (pattrib->bwmode == CHANNEL_WIDTH_80)
-+			SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
-+		else if (pattrib->bwmode == CHANNEL_WIDTH_40) {
-+			if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
-+				SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ;
-+			else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
-+				SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ;
-+			else
-+				RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
-+		} else {
-+			if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
-+				SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
-+			else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
-+				SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
-+			else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
-+				SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
-+			else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
-+				SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
-+			else
-+				RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
-+		}
-+	} else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
-+		/* RTW_INFO("SCMapping: HT Case: pHalData->current_channel_bw %d, pHalData->nCur40MhzPrimeSC %d\n",pHalData->current_channel_bw,pHalData->nCur40MhzPrimeSC); */
-+
-+		if (pattrib->bwmode == CHANNEL_WIDTH_40)
-+			SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
-+		else if (pattrib->bwmode == CHANNEL_WIDTH_20) {
-+			if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
-+				SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
-+			else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
-+				SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
-+			else
-+				SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
-+		}
-+	} else
-+		SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
-+
-+	return SCSettingOfDesc;
-+}
-+
-+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc)
-+{
-+	if ((pattrib->encrypt > 0) && (!pattrib->bswenc)
-+	    && (pattrib->bmc_camid != INVALID_SEC_MAC_CAM_ID)) {
-+
-+		SET_TX_DESC_EN_DESC_ID_8703B(ptxdesc, 1);
-+		SET_TX_DESC_MACID_8703B(ptxdesc, pattrib->bmc_camid);
-+	}
-+}
-+
-+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc)
-+{
-+	SET_TX_DESC_USE_RATE_8703B(ptxdesc, 1);
-+	SET_TX_DESC_TX_RATE_8703B(ptxdesc, MRateToHwRate(pattrib->rate));
-+	SET_TX_DESC_DISABLE_FB_8703B(ptxdesc, 1);
-+}
-+
-+static u8 fill_txdesc_sectype(struct pkt_attrib *pattrib)
-+{
-+	u8 sectype = 0;
-+	if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
-+		switch (pattrib->encrypt) {
-+		/* SEC_TYPE */
-+		case _WEP40_:
-+		case _WEP104_:
-+		case _TKIP_:
-+		case _TKIP_WTMIC_:
-+			sectype = 1;
-+			break;
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+		case _SMS4_:
-+			sectype = 2;
-+			break;
-+#endif
-+		case _AES_:
-+			sectype = 3;
-+			break;
-+
-+		case _NO_PRIVACY_:
-+		default:
-+			break;
-+		}
-+	}
-+	return sectype;
-+}
-+
-+static void fill_txdesc_vcs_8703b(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
-+{
-+	/* RTW_INFO("cvs_mode=%d\n", pattrib->vcs_mode); */
-+
-+	if (pattrib->vcs_mode) {
-+		switch (pattrib->vcs_mode) {
-+		case RTS_CTS:
-+			SET_TX_DESC_RTS_ENABLE_8703B(ptxdesc, 1);
-+			SET_TX_DESC_HW_RTS_ENABLE_8703B(ptxdesc, 1);
-+			break;
-+
-+		case CTS_TO_SELF:
-+			SET_TX_DESC_CTS2SELF_8703B(ptxdesc, 1);
-+			break;
-+
-+		case NONE_VCS:
-+		default:
-+			break;
-+		}
-+
-+		SET_TX_DESC_RTS_RATE_8703B(ptxdesc, 8); /* RTS Rate=24M */
-+		SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(ptxdesc, 0xF);
-+
-+		if (padapter->mlmeextpriv.mlmext_info.preamble_mode == PREAMBLE_SHORT)
-+			SET_TX_DESC_RTS_SHORT_8703B(ptxdesc, 1);
-+
-+		/* Set RTS BW */
-+		if (pattrib->ht_en)
-+			SET_TX_DESC_RTS_SC_8703B(ptxdesc, SCMapping_8703B(padapter, pattrib));
-+	}
-+}
-+
-+static void fill_txdesc_phy_8703b(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
-+{
-+	/* RTW_INFO("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset); */
-+
-+	if (pattrib->ht_en) {
-+		SET_TX_DESC_DATA_BW_8703B(ptxdesc, BWMapping_8703B(padapter, pattrib));
-+		SET_TX_DESC_DATA_SC_8703B(ptxdesc, SCMapping_8703B(padapter, pattrib));
-+	}
-+}
-+
-+static void rtl8703b_fill_default_txdesc(
-+	struct xmit_frame *pxmitframe,
-+	u8 *pbuf)
-+{
-+	PADAPTER padapter;
-+	HAL_DATA_TYPE *pHalData;
-+	struct mlme_ext_priv *pmlmeext;
-+	struct mlme_ext_info *pmlmeinfo;
-+	struct pkt_attrib *pattrib;
-+	s32 bmcst;
-+
-+	_rtw_memset(pbuf, 0, TXDESC_SIZE);
-+
-+	padapter = pxmitframe->padapter;
-+	pHalData = GET_HAL_DATA(padapter);
-+	pmlmeext = &padapter->mlmeextpriv;
-+	pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	pattrib = &pxmitframe->attrib;
-+	bmcst = IS_MCAST(pattrib->ra);
-+
-+	if (pxmitframe->frame_tag == DATA_FRAMETAG) {
-+		u8 drv_userate = 0;
-+
-+		SET_TX_DESC_MACID_8703B(pbuf, pattrib->mac_id);
-+		SET_TX_DESC_RATE_ID_8703B(pbuf, pattrib->raid);
-+		SET_TX_DESC_QUEUE_SEL_8703B(pbuf, pattrib->qsel);
-+		SET_TX_DESC_SEQ_8703B(pbuf, pattrib->seqnum);
-+
-+		SET_TX_DESC_SEC_TYPE_8703B(pbuf, fill_txdesc_sectype(pattrib));
-+
-+		if (bmcst)
-+			fill_txdesc_force_bmc_camid(pattrib, pbuf);
-+
-+		fill_txdesc_vcs_8703b(padapter, pattrib, pbuf);
-+
-+#ifdef CONFIG_P2P
-+		if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) {
-+			if (pattrib->icmp_pkt == 1 && padapter->registrypriv.wifi_spec == 1)
-+				drv_userate = 1;
-+		}
-+#endif
-+
-+		if ((pattrib->ether_type != 0x888e) &&
-+		    (pattrib->ether_type != 0x0806) &&
-+		    (pattrib->ether_type != 0x88B4) &&
-+		    (pattrib->dhcp_pkt != 1) &&
-+		    (drv_userate != 1)
-+#ifdef CONFIG_AUTO_AP_MODE
-+		    && (pattrib->pctrl != _TRUE)
-+#endif
-+		   ) {
-+			/* Non EAP & ARP & DHCP type data packet */
-+
-+			if (pattrib->ampdu_en == _TRUE) {
-+				SET_TX_DESC_AGG_ENABLE_8703B(pbuf, 1);
-+				SET_TX_DESC_MAX_AGG_NUM_8703B(pbuf, 0x1F);
-+				SET_TX_DESC_AMPDU_DENSITY_8703B(pbuf, pattrib->ampdu_spacing);
-+			} else
-+				SET_TX_DESC_AGG_BREAK_8703B(pbuf, 1);
-+
-+			fill_txdesc_phy_8703b(padapter, pattrib, pbuf);
-+
-+			SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(pbuf, 0x1F);
-+
-+			if (pHalData->fw_ractrl == _FALSE) {
-+				SET_TX_DESC_USE_RATE_8703B(pbuf, 1);
-+
-+				if (pHalData->INIDATA_RATE[pattrib->mac_id] & BIT(7))
-+					SET_TX_DESC_DATA_SHORT_8703B(pbuf, 1);
-+
-+				SET_TX_DESC_TX_RATE_8703B(pbuf, pHalData->INIDATA_RATE[pattrib->mac_id] & 0x7F);
-+			}
-+
-+			if (bmcst)
-+				fill_txdesc_bmc_tx_rate(pattrib, pbuf);
-+
-+			/* modify data rate by iwpriv */
-+			if (padapter->fix_rate != 0xFF) {
-+				SET_TX_DESC_USE_RATE_8703B(pbuf, 1);
-+				if (padapter->fix_rate & BIT(7))
-+					SET_TX_DESC_DATA_SHORT_8703B(pbuf, 1);
-+				SET_TX_DESC_TX_RATE_8703B(pbuf, padapter->fix_rate & 0x7F);
-+				if (!padapter->data_fb)
-+					SET_TX_DESC_DISABLE_FB_8703B(pbuf, 1);
-+			}
-+
-+			if (pattrib->ldpc)
-+				SET_TX_DESC_DATA_LDPC_8703B(pbuf, 1);
-+
-+			if (pattrib->stbc)
-+				SET_TX_DESC_DATA_STBC_8703B(pbuf, 1);
-+
-+#ifdef CONFIG_CMCC_TEST
-+			SET_TX_DESC_DATA_SHORT_8703B(pbuf, 1); /* use cck short premble */
-+#endif
-+		} else {
-+			/* EAP data packet and ARP packet. */
-+			/* Use the 1M data rate to send the EAP/ARP packet. */
-+			/* This will maybe make the handshake smooth. */
-+
-+			SET_TX_DESC_AGG_BREAK_8703B(pbuf, 1);
-+			SET_TX_DESC_USE_RATE_8703B(pbuf, 1);
-+			if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
-+				SET_TX_DESC_DATA_SHORT_8703B(pbuf, 1);
-+#ifdef CONFIG_IP_R_MONITOR
-+			if((pattrib->ether_type == ETH_P_ARP) &&
-+				(IsSupportedTxOFDM(padapter->registrypriv.wireless_mode))) 
-+				SET_TX_DESC_TX_RATE_8703B(pbuf, MRateToHwRate(IEEE80211_OFDM_RATE_6MB));
-+			 else
-+#endif/*CONFIG_IP_R_MONITOR*/
-+				SET_TX_DESC_TX_RATE_8703B(pbuf, MRateToHwRate(pmlmeext->tx_rate));
-+
-+			RTW_INFO(FUNC_ADPT_FMT ": SP Packet(0x%04X) rate=0x%x SeqNum = %d\n",
-+				FUNC_ADPT_ARG(padapter), pattrib->ether_type, MRateToHwRate(pmlmeext->tx_rate), pattrib->seqnum);
-+		}
-+
-+#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+		SET_TX_DESC_USB_TXAGG_NUM_8703B(pbuf, pxmitframe->agg_num);
-+#endif
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_XMIT_ACK
-+		/* CCX-TXRPT ack for xmit mgmt frames. */
-+		if (pxmitframe->ack_report) {
-+#ifdef DBG_CCX
-+			RTW_INFO("%s set spe_rpt\n", __func__);
-+#endif
-+			SET_TX_DESC_SPE_RPT_8703B(pbuf, 1);
-+			SET_TX_DESC_SW_DEFINE_8703B(pbuf, (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no));
-+		}
-+#endif /* CONFIG_XMIT_ACK */
-+#endif
-+	} else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {
-+
-+		SET_TX_DESC_MACID_8703B(pbuf, pattrib->mac_id);
-+		SET_TX_DESC_QUEUE_SEL_8703B(pbuf, pattrib->qsel);
-+		SET_TX_DESC_RATE_ID_8703B(pbuf, pattrib->raid);
-+		SET_TX_DESC_SEQ_8703B(pbuf, pattrib->seqnum);
-+		SET_TX_DESC_USE_RATE_8703B(pbuf, 1);
-+
-+		SET_TX_DESC_MBSSID_8703B(pbuf, pattrib->mbssid & 0xF);
-+
-+		SET_TX_DESC_RETRY_LIMIT_ENABLE_8703B(pbuf, 1);
-+		if (pattrib->retry_ctrl == _TRUE)
-+			SET_TX_DESC_DATA_RETRY_LIMIT_8703B(pbuf, 6);
-+		else
-+			SET_TX_DESC_DATA_RETRY_LIMIT_8703B(pbuf, 12);
-+
-+		SET_TX_DESC_TX_RATE_8703B(pbuf, MRateToHwRate(pattrib->rate));
-+
-+#ifdef CONFIG_XMIT_ACK
-+		/* CCX-TXRPT ack for xmit mgmt frames. */
-+		if (pxmitframe->ack_report) {
-+#ifdef DBG_CCX
-+			RTW_INFO("%s set spe_rpt\n", __FUNCTION__);
-+#endif
-+			SET_TX_DESC_SPE_RPT_8703B(pbuf, 1);
-+			SET_TX_DESC_SW_DEFINE_8703B(pbuf, (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no));
-+		}
-+#endif /* CONFIG_XMIT_ACK */
-+	} else if (pxmitframe->frame_tag == TXAGG_FRAMETAG) {
-+	}
-+#ifdef CONFIG_MP_INCLUDED
-+	else if (pxmitframe->frame_tag == MP_FRAMETAG) {
-+		fill_txdesc_for_mp(padapter, pbuf);
-+	}
-+#endif
-+	else {
-+
-+		SET_TX_DESC_MACID_8703B(pbuf, pattrib->mac_id);
-+		SET_TX_DESC_RATE_ID_8703B(pbuf, pattrib->raid);
-+		SET_TX_DESC_QUEUE_SEL_8703B(pbuf, pattrib->qsel);
-+		SET_TX_DESC_SEQ_8703B(pbuf, pattrib->seqnum);
-+		SET_TX_DESC_USE_RATE_8703B(pbuf, 1);
-+		SET_TX_DESC_TX_RATE_8703B(pbuf, MRateToHwRate(pmlmeext->tx_rate));
-+	}
-+
-+	SET_TX_DESC_PKT_SIZE_8703B(pbuf, pattrib->last_txcmdsz);
-+
-+	{
-+		u8 pkt_offset, offset;
-+
-+		pkt_offset = 0;
-+		offset = TXDESC_SIZE;
-+#ifdef CONFIG_USB_HCI
-+		pkt_offset = pxmitframe->pkt_offset;
-+		offset += (pxmitframe->pkt_offset >> 3);
-+#endif /* CONFIG_USB_HCI */
-+
-+#ifdef CONFIG_TX_EARLY_MODE
-+		if (pxmitframe->frame_tag == DATA_FRAMETAG) {
-+			pkt_offset = 1;
-+			offset += EARLY_MODE_INFO_SIZE;
-+		}
-+#endif /* CONFIG_TX_EARLY_MODE */
-+
-+		SET_TX_DESC_PKT_OFFSET_8703B(pbuf, pkt_offset);
-+		SET_TX_DESC_OFFSET_8703B(pbuf, offset);
-+	}
-+
-+	if (bmcst)
-+		SET_TX_DESC_BMC_8703B(pbuf, 1);
-+
-+	/* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */
-+	/* (1) The sequence number of each non-Qos frame / broadcast / multicast / */
-+	/* mgnt frame should be controled by Hw because Fw will also send null data */
-+	/* which we cannot control when Fw LPS enable. */
-+	/* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */
-+	/* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */
-+	/* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */
-+	/* 2010.06.23. Added by tynli. */
-+	if (!pattrib->qos_en)
-+		SET_TX_DESC_HWSEQ_EN_8703B(pbuf, 1);
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	if (!bmcst && pattrib->psta)
-+		odm_set_tx_ant_by_tx_info(adapter_to_phydm(padapter), pbuf, pattrib->psta->cmn.mac_id);
-+#endif
-+}
-+
-+/*
-+ *	Description:
-+ *
-+ *	Parameters:
-+ *		pxmitframe	xmitframe
-+ *		pbuf		where to fill tx desc
-+ */
-+void rtl8703b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
-+{
-+	rtl8703b_fill_default_txdesc(pxmitframe, pbuf);
-+
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	rtl8703b_cal_txdesc_chksum((struct tx_desc *)pbuf);
-+#endif
-+}
-+
-+static void hw_var_set_monitor(PADAPTER adapter, u8 variable, u8 *val)
-+{
-+#ifdef CONFIG_WIFI_MONITOR
-+	u32 tmp_32bit;
-+	struct net_device *ndev = adapter->pnetdev;
-+	struct mon_reg_backup *mon = &GET_HAL_DATA(adapter)->mon_backup;
-+
-+	mon->known_rcr = 1;
-+	rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)& mon->rcr);
-+
-+	/* Receive all type */
-+	tmp_32bit = RCR_AAP | RCR_APP_PHYST_RXFF;
-+
-+	if (ndev->type == ARPHRD_IEEE80211_RADIOTAP) {
-+		/* Append FCS */
-+		tmp_32bit |= RCR_APPFCS;
-+	}
-+
-+	rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)& tmp_32bit);
-+
-+	/* Receive all data frames */
-+	mon->known_rxfilter = 1;
-+	mon->rxfilter0 = rtw_read16(adapter, REG_RXFLTMAP0_8703B);
-+	mon->rxfilter1 = rtw_read16(adapter, REG_RXFLTMAP1_8703B);
-+	mon->rxfilter2 = rtw_read16(adapter, REG_RXFLTMAP2_8703B);
-+	rtw_write16(adapter, REG_RXFLTMAP0_8703B, 0xFFFF);
-+	rtw_write16(adapter, REG_RXFLTMAP1_8703B, 0xFFFF);
-+	rtw_write16(adapter, REG_RXFLTMAP2_8703B, 0xFFFF);
-+#endif /* CONFIG_WIFI_MONITOR */
-+}
-+
-+static void hw_var_set_opmode(PADAPTER padapter, u8 variable, u8 *val)
-+{
-+	u8 val8;
-+	u8 mode = *((u8 *)val);
-+	static u8 isMonitor = _FALSE;
-+
-+	HAL_DATA_TYPE			*pHalData = GET_HAL_DATA(padapter);
-+
-+	if (isMonitor == _TRUE) {
-+#ifdef CONFIG_WIFI_MONITOR
-+		struct mon_reg_backup *backup = &GET_HAL_DATA(padapter)->mon_backup;
-+
-+		if (backup->known_rcr) {
-+			backup->known_rcr = 0;
-+			rtw_hal_set_hwreg(padapter, HW_VAR_RCR, (u8 *)&backup->rcr);
-+			rtw_hal_rcr_set_chk_bssid(padapter, MLME_ACTION_NONE);
-+		}
-+		if (backup->known_rxfilter) {
-+			backup->known_rxfilter = 0;
-+			rtw_write16(padapter, REG_RXFLTMAP0_8703B, backup->rxfilter0);
-+			rtw_write16(padapter, REG_RXFLTMAP1_8703B, backup->rxfilter1);
-+			rtw_write16(padapter, REG_RXFLTMAP2_8703B, backup->rxfilter2);
-+		}
-+#endif /* CONFIG_WIFI_MONITOR */
-+		isMonitor = _FALSE;
-+	}
-+
-+	if (mode == _HW_STATE_MONITOR_) {
-+		isMonitor = _TRUE;
-+		/* set net_type */
-+		Set_MSR(padapter, _HW_STATE_NOLINK_);
-+
-+		hw_var_set_monitor(padapter, variable, val);
-+		return;
-+	}
-+	rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (padapter->hw_port == HW_PORT1) {
-+		/* disable Port1 TSF update */
-+		rtw_iface_disable_tsf_update(padapter);
-+
-+		Set_MSR(padapter, mode);
-+
-+		RTW_INFO("#### %s()-%d hw_port(%d) mode=%d ####\n",
-+			 __func__, __LINE__, padapter->hw_port, mode);
-+
-+		if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
-+			if (!rtw_mi_get_ap_num(padapter) && !rtw_mi_get_mesh_num(padapter)) {
-+				StopTxBeacon(padapter);
-+#ifdef CONFIG_PCI_HCI
-+				UpdateInterruptMask8703BE(padapter, 0, 0, RT_BCN_INT_MASKS, 0);
-+#else /* !CONFIG_PCI_HCI */
-+#ifdef CONFIG_INTERRUPT_BASED_TXBCN
-+
-+#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
-+				rtw_write8(padapter, REG_DRVERLYINT, 0x05);/* restore early int time to 5ms */
-+				UpdateInterruptMask8703BU(padapter, _TRUE, 0, IMR_BCNDMAINT0_8703B);
-+#endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
-+
-+#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
-+				UpdateInterruptMask8703BU(padapter, _TRUE , 0, (IMR_TXBCN0ERR_8703B | IMR_TXBCN0OK_8703B));
-+#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
-+
-+#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
-+#endif /* !CONFIG_PCI_HCI */
-+			}
-+
-+			/* disable atim wnd and disable beacon function */
-+			rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | DIS_ATIM);
-+		} else if (mode == _HW_STATE_ADHOC_) {
-+			ResumeTxBeacon(padapter);
-+			rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
-+		} else if (mode == _HW_STATE_AP_) {
-+#ifdef CONFIG_PCI_HCI
-+			UpdateInterruptMask8703BE(padapter, RT_BCN_INT_MASKS, 0, 0, 0);
-+#else /* !CONFIG_PCI_HCI */
-+#ifdef CONFIG_INTERRUPT_BASED_TXBCN
-+
-+#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
-+			UpdateInterruptMask8703BU(padapter, _TRUE, IMR_BCNDMAINT0_8703B, 0);
-+#endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
-+
-+#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
-+			UpdateInterruptMask8703BU(padapter, _TRUE, (IMR_TXBCN0ERR_8703B | IMR_TXBCN0OK_8703B), 0);
-+#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
-+
-+#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
-+#endif /* !CONFIG_PCI_HCI */
-+
-+			rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | DIS_BCNQ_SUB);
-+
-+			/* enable to rx data frame				 */
-+			rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
-+			/* enable to rx ps-poll */
-+			rtw_write16(padapter, REG_RXFLTMAP1, 0x0400);
-+
-+			/* Beacon Control related register for first time */
-+			rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms		 */
-+
-+			/* rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); */
-+			rtw_write8(padapter, REG_ATIMWND_1, 0x0a); /* 10ms for port1 */
-+
-+			rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
-+
-+			/* reset TSF2	 */
-+			rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(1));
-+
-+			/* enable BCN1 Function for if2 */
-+			/* don't enable update TSF1 for if2 (due to TSF update when beacon/probe rsp are received) */
-+			rtw_write8(padapter, REG_BCN_CTRL_1, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
-+
-+			/* SW_BCN_SEL - Port1 */
-+			/* rtw_write8(Adapter, REG_DWBCN1_CTRL_8192E+2, rtw_read8(Adapter, REG_DWBCN1_CTRL_8192E+2)|BIT4); */
-+			rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
-+
-+			/* select BCN on port 1 */
-+			rtw_write8(padapter, REG_CCK_CHECK_8703B,
-+				(rtw_read8(padapter, REG_CCK_CHECK_8703B) | BIT_BCN_PORT_SEL));
-+
-+			if (!rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_ASSOC_SUCCESS)) {
-+				val8 = rtw_read8(padapter, REG_BCN_CTRL);
-+				val8 &= ~EN_BCN_FUNCTION;
-+				rtw_write8(padapter, REG_BCN_CTRL, val8);
-+			}
-+
-+			/* BCN1 TSF will sync to BCN0 TSF with offset(0x518) if if1_sta linked */
-+			/* rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1)|BIT(5)); */
-+			/* rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(3)); */
-+
-+			/* dis BCN0 ATIM  WND if if1 is station */
-+			rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) | DIS_ATIM);
-+
-+#ifdef CONFIG_TSF_RESET_OFFLOAD
-+			/* Reset TSF for STA+AP concurrent mode */
-+			if (DEV_STA_LD_NUM(adapter_to_dvobj(padapter))) {
-+				if (rtw_hal_reset_tsf(padapter, HW_PORT1) == _FAIL)
-+					RTW_INFO("ERROR! %s()-%d: Reset port1 TSF fail\n",
-+						 __FUNCTION__, __LINE__);
-+			}
-+#endif /* CONFIG_TSF_RESET_OFFLOAD */
-+		}
-+	} else /* else for port0 */
-+#endif /* CONFIG_CONCURRENT_MODE */
-+	{
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM /*For Port0 - MBSS CAM*/
-+		hw_var_set_opmode_mbid(padapter, mode);
-+#else
-+		/* disable Port0 TSF update */
-+		rtw_iface_disable_tsf_update(padapter);
-+
-+		/* set net_type */
-+		Set_MSR(padapter, mode);
-+		RTW_INFO("#### %s() -%d hw_port(0) mode = %d ####\n", __func__, __LINE__, mode);
-+
-+		if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
-+#ifdef CONFIG_CONCURRENT_MODE
-+			if (!rtw_mi_get_ap_num(padapter) && !rtw_mi_get_mesh_num(padapter))
-+#endif /* CONFIG_CONCURRENT_MODE */
-+			{
-+				StopTxBeacon(padapter);
-+#ifdef CONFIG_PCI_HCI
-+				UpdateInterruptMask8703BE(padapter, 0, 0, RT_BCN_INT_MASKS, 0);
-+#else /* !CONFIG_PCI_HCI */
-+#ifdef CONFIG_INTERRUPT_BASED_TXBCN
-+#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
-+				rtw_write8(padapter, REG_DRVERLYINT, 0x05); /* restore early int time to 5ms */
-+				UpdateInterruptMask8812AU(padapter, _TRUE, 0, IMR_BCNDMAINT0_8703B);
-+#endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
-+
-+#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
-+				UpdateInterruptMask8812AU(padapter, _TRUE , 0, (IMR_TXBCN0ERR_8703B | IMR_TXBCN0OK_8703B));
-+#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
-+
-+#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
-+#endif /* !CONFIG_PCI_HCI */
-+			}
-+
-+			/* disable atim wnd */
-+			rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_ATIM);
-+			/* rtw_write8(padapter,REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION); */
-+		} else if (mode == _HW_STATE_ADHOC_) {
-+			ResumeTxBeacon(padapter);
-+			rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
-+		} else if (mode == _HW_STATE_AP_) {
-+#ifdef CONFIG_PCI_HCI
-+			UpdateInterruptMask8703BE(padapter, RT_BCN_INT_MASKS, 0, 0, 0);
-+#else /* !CONFIG_PCI_HCI */
-+#ifdef CONFIG_INTERRUPT_BASED_TXBCN
-+#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
-+			UpdateInterruptMask8703BU(padapter, _TRUE , IMR_BCNDMAINT0_8703B, 0);
-+#endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
-+
-+#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
-+			UpdateInterruptMask8703BU(padapter, _TRUE , (IMR_TXBCN0ERR_8703B | IMR_TXBCN0OK_8703B), 0);
-+#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
-+
-+#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
-+#endif
-+
-+			rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | DIS_BCNQ_SUB);
-+
-+			/* enable to rx data frame */
-+			rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
-+			/* enable to rx ps-poll */
-+			rtw_write16(padapter, REG_RXFLTMAP1, 0x0400);
-+
-+			/* Beacon Control related register for first time */
-+			rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms			 */
-+
-+			/* rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); */
-+			rtw_write8(padapter, REG_ATIMWND, 0x0a); /* 10ms */
-+
-+			rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
-+
-+			/* reset TSF */
-+			rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
-+
-+			/* enable BCN0 Function for if1 */
-+			/* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */
-+			rtw_write8(padapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
-+
-+			/* SW_BCN_SEL - Port0 */
-+			/* rtw_write8(Adapter, REG_DWBCN1_CTRL_8192E+2, rtw_read8(Adapter, REG_DWBCN1_CTRL_8192E+2) & ~BIT4); */
-+			rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
-+
-+			/* select BCN on port 0 */
-+			rtw_write8(padapter, REG_CCK_CHECK_8703B,
-+				(rtw_read8(padapter, REG_CCK_CHECK_8703B) & ~BIT_BCN_PORT_SEL));
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+			if (!rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_ASSOC_SUCCESS)) {
-+				val8 = rtw_read8(padapter, REG_BCN_CTRL_1);
-+				val8 &= ~EN_BCN_FUNCTION;
-+				rtw_write8(padapter, REG_BCN_CTRL_1, val8);
-+			}
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+			/* dis BCN1 ATIM  WND if if2 is station */
-+			val8 = rtw_read8(padapter, REG_BCN_CTRL_1);
-+			val8 |= DIS_ATIM;
-+			rtw_write8(padapter, REG_BCN_CTRL_1, val8);
-+#ifdef CONFIG_TSF_RESET_OFFLOAD
-+			/* Reset TSF for STA+AP concurrent mode */
-+			if (DEV_STA_LD_NUM(adapter_to_dvobj(padapter))) {
-+				if (rtw_hal_reset_tsf(padapter, HW_PORT0) == _FAIL)
-+					RTW_INFO("ERROR! %s()-%d: Reset port0 TSF fail\n",
-+						 __FUNCTION__, __LINE__);
-+			}
-+#endif /* CONFIG_TSF_RESET_OFFLOAD */
-+		}
-+#endif
-+	}
-+}
-+
-+void CCX_FwC2HTxRpt_8703b(PADAPTER padapter, u8 *pdata, u8 len)
-+{
-+	u8 seq_no;
-+
-+#define	GET_8703B_C2H_TX_RPT_LIFE_TIME_OVER(_Header)	LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
-+#define	GET_8703B_C2H_TX_RPT_RETRY_OVER(_Header)	LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
-+
-+	/* RTW_INFO("%s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", __func__,  */
-+	/*		*pdata, *(pdata+1), *(pdata+2), *(pdata+3), *(pdata+4), *(pdata+5), *(pdata+6), *(pdata+7)); */
-+
-+	seq_no = *(pdata + 6);
-+
-+#ifdef CONFIG_XMIT_ACK
-+	if (GET_8703B_C2H_TX_RPT_RETRY_OVER(pdata) | GET_8703B_C2H_TX_RPT_LIFE_TIME_OVER(pdata))
-+		rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
-+	/*
-+		else if(seq_no != padapter->xmitpriv.seq_no) {
-+			RTW_INFO("tx_seq_no=%d, rpt_seq_no=%d\n", padapter->xmitpriv.seq_no, seq_no);
-+			rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
-+		}
-+	*/
-+	else
-+		rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
-+#endif
-+}
-+
-+static s32 c2h_handler_8703b(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
-+{
-+	s32 ret = _SUCCESS;
-+
-+	switch (id) {
-+	case C2H_CCX_TX_RPT:
-+		CCX_FwC2HTxRpt_8703b(adapter, payload, plen);
-+		break;
-+	default:
-+		ret = _FAIL;
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+u8 SetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);
-+	u8 ret = _SUCCESS;
-+	u8 val8;
-+	u16 val16;
-+	u32 val32;
-+
-+
-+	switch (variable) {
-+	case HW_VAR_SET_OPMODE:
-+		hw_var_set_opmode(padapter, variable, val);
-+		break;
-+
-+	case HW_VAR_BASIC_RATE:
-+		rtw_var_set_basic_rate(padapter, val);
-+	break;
-+
-+	case HW_VAR_TXPAUSE:
-+		rtw_write8(padapter, REG_TXPAUSE, *val);
-+		break;
-+
-+	case HW_VAR_SLOT_TIME:
-+		rtw_write8(padapter, REG_SLOT, *val);
-+		break;
-+
-+	case HW_VAR_RESP_SIFS:
-+#if 0
-+		/* SIFS for OFDM Data ACK */
-+		rtw_write8(padapter, REG_SIFS_CTX + 1, val[0]);
-+		/* SIFS for OFDM consecutive tx like CTS data! */
-+		rtw_write8(padapter, REG_SIFS_TRX + 1, val[1]);
-+
-+		rtw_write8(padapter, REG_SPEC_SIFS + 1, val[0]);
-+		rtw_write8(padapter, REG_MAC_SPEC_SIFS + 1, val[0]);
-+
-+		/* 20100719 Joseph: Revise SIFS setting due to Hardware register definition change. */
-+		rtw_write8(padapter, REG_R2T_SIFS + 1, val[0]);
-+		rtw_write8(padapter, REG_T2T_SIFS + 1, val[0]);
-+
-+#else
-+		/* SIFS_Timer = 0x0a0a0808; */
-+		/* RESP_SIFS for CCK */
-+		rtw_write8(padapter, REG_RESP_SIFS_CCK, val[0]); /* SIFS_T2T_CCK (0x08) */
-+		rtw_write8(padapter, REG_RESP_SIFS_CCK + 1, val[1]); /* SIFS_R2T_CCK(0x08) */
-+		/* RESP_SIFS for OFDM */
-+		rtw_write8(padapter, REG_RESP_SIFS_OFDM, val[2]); /* SIFS_T2T_OFDM (0x0a) */
-+		rtw_write8(padapter, REG_RESP_SIFS_OFDM + 1, val[3]); /* SIFS_R2T_OFDM(0x0a) */
-+#endif
-+		break;
-+
-+	case HW_VAR_ACK_PREAMBLE: {
-+		u8 regTmp;
-+		u8 bShortPreamble = *val;
-+
-+		/* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
-+		/* regTmp = (pHalData->nCur40MhzPrimeSC)<<5; */
-+		regTmp = 0;
-+		if (bShortPreamble)
-+			regTmp |= 0x80;
-+		rtw_write8(padapter, REG_RRSR + 2, regTmp);
-+	}
-+	break;
-+
-+	case HW_VAR_CAM_INVALID_ALL:
-+		rtw_write32(padapter, REG_CAMCMD, BIT(31) | BIT(30));
-+		break;
-+
-+	case HW_VAR_AC_PARAM_VO:
-+		rtw_write32(padapter, REG_EDCA_VO_PARAM, *((u32 *)val));
-+		break;
-+
-+	case HW_VAR_AC_PARAM_VI:
-+		rtw_write32(padapter, REG_EDCA_VI_PARAM, *((u32 *)val));
-+		break;
-+
-+	case HW_VAR_AC_PARAM_BE:
-+		pHalData->ac_param_be = ((u32 *)(val))[0];
-+		rtw_write32(padapter, REG_EDCA_BE_PARAM, *((u32 *)val));
-+		break;
-+
-+	case HW_VAR_AC_PARAM_BK:
-+		rtw_write32(padapter, REG_EDCA_BK_PARAM, *((u32 *)val));
-+		break;
-+
-+	case HW_VAR_ACM_CTRL: {
-+		u8 ctrl = *((u8 *)val);
-+		u8 hwctrl = 0;
-+
-+		if (ctrl != 0) {
-+			hwctrl |= AcmHw_HwEn;
-+
-+			if (ctrl & BIT(3)) /* BE */
-+				hwctrl |= AcmHw_BeqEn;
-+
-+			if (ctrl & BIT(2)) /* VI */
-+				hwctrl |= AcmHw_ViqEn;
-+
-+			if (ctrl & BIT(1)) /* VO */
-+				hwctrl |= AcmHw_VoqEn;
-+		}
-+
-+		RTW_INFO("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl);
-+		rtw_write8(padapter, REG_ACMHWCTRL, hwctrl);
-+	}
-+	break;
-+#ifdef CONFIG_80211N_HT
-+	case HW_VAR_AMPDU_FACTOR: {
-+		u32	AMPDULen = (*((u8 *)val));
-+
-+		if (AMPDULen < HT_AGG_SIZE_32K)
-+			AMPDULen = (0x2000 << (*((u8 *)val))) - 1;
-+		else
-+			AMPDULen = 0x7fff;
-+
-+		rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8703B, AMPDULen);
-+	}
-+	break;
-+#endif /* CONFIG_80211N_HT */
-+	case HW_VAR_H2C_FW_PWRMODE: {
-+		u8 psmode = *val;
-+
-+		/* if (psmode != PS_MODE_ACTIVE)	{ */
-+		/*	rtl8703b_set_lowpwr_lps_cmd(padapter, _TRUE); */
-+		/* } else { */
-+		/*	rtl8703b_set_lowpwr_lps_cmd(padapter, _FALSE); */
-+		/* } */
-+		rtl8703b_set_FwPwrMode_cmd(padapter, psmode);
-+	}
-+	break;
-+	case HW_VAR_H2C_PS_TUNE_PARAM:
-+		rtl8703b_set_FwPsTuneParam_cmd(padapter);
-+		break;
-+
-+	case HW_VAR_H2C_FW_JOINBSSRPT:
-+		rtl8703b_set_FwJoinBssRpt_cmd(padapter, *val);
-+		break;
-+	case HW_VAR_DL_RSVD_PAGE:
-+#ifdef CONFIG_BT_COEXIST
-+		if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
-+			rtl8703b_download_BTCoex_AP_mode_rsvd_page(padapter);
-+		else
-+#endif /* CONFIG_BT_COEXIST */
-+		{
-+			rtl8703b_download_rsvd_page(padapter, RT_MEDIA_CONNECT);
-+		}
-+		break;
-+
-+#ifdef CONFIG_P2P
-+	case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
-+		rtl8703b_set_p2p_ps_offload_cmd(padapter, *val);
-+		break;
-+#endif /* CONFIG_P2P */
-+
-+	case HW_VAR_EFUSE_USAGE:
-+		pHalData->EfuseUsedPercentage = *val;
-+		break;
-+
-+	case HW_VAR_EFUSE_BYTES:
-+		pHalData->EfuseUsedBytes = *((u16 *)val);
-+		break;
-+
-+	case HW_VAR_EFUSE_BT_USAGE:
-+#ifdef HAL_EFUSE_MEMORY
-+		pHalData->EfuseHal.BTEfuseUsedPercentage = *val;
-+#endif
-+		break;
-+
-+	case HW_VAR_EFUSE_BT_BYTES:
-+#ifdef HAL_EFUSE_MEMORY
-+		pHalData->EfuseHal.BTEfuseUsedBytes = *((u16 *)val);
-+#else
-+		BTEfuseUsedBytes = *((u16 *)val);
-+#endif
-+		break;
-+
-+	case HW_VAR_FIFO_CLEARN_UP: {
-+#define RW_RELEASE_EN		BIT(18)
-+#define RXDMA_IDLE			BIT(17)
-+
-+		struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+		u8 trycnt = 100;
-+
-+		/* pause tx */
-+		rtw_write8(padapter, REG_TXPAUSE, 0xff);
-+
-+		/* keep sn */
-+		padapter->xmitpriv.nqos_ssn = rtw_read16(padapter, REG_NQOS_SEQ);
-+
-+		if (pwrpriv->bkeepfwalive != _TRUE) {
-+			/* RX DMA stop */
-+			val32 = rtw_read32(padapter, REG_RXPKT_NUM);
-+			val32 |= RW_RELEASE_EN;
-+			rtw_write32(padapter, REG_RXPKT_NUM, val32);
-+			do {
-+				val32 = rtw_read32(padapter, REG_RXPKT_NUM);
-+				val32 &= RXDMA_IDLE;
-+				if (val32)
-+					break;
-+
-+				RTW_INFO("%s: [HW_VAR_FIFO_CLEARN_UP] val=%x times:%d\n", __FUNCTION__, val32, trycnt);
-+			} while (--trycnt);
-+			if (trycnt == 0)
-+				RTW_INFO("[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed......\n");
-+
-+			/* RQPN Load 0 */
-+			rtw_write16(padapter, REG_RQPN_NPQ, 0);
-+			rtw_write32(padapter, REG_RQPN, 0x80000000);
-+			rtw_mdelay_os(2);
-+		}
-+	}
-+	break;
-+
-+	case HW_VAR_RESTORE_HW_SEQ:
-+		/* restore Sequence No. */
-+		rtw_write8(padapter, 0x4dc, padapter->xmitpriv.nqos_ssn);
-+		break;
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	case HW_VAR_CHECK_TXBUF: {
-+		u32 i;
-+		u8 RetryLimit = 0x01;
-+		u32 reg_200, reg_204;
-+
-+		val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);
-+		rtw_write16(padapter, REG_RETRY_LIMIT, val16);
-+
-+		for (i = 0; i < 200; i++) { /* polling 200x10=2000 msec  */
-+			reg_200 = rtw_read32(padapter, 0x200);
-+			reg_204 = rtw_read32(padapter, 0x204);
-+			if (reg_200 != reg_204) {
-+				/* RTW_INFO("packet in tx packet buffer - 0x204=%x, 0x200=%x (%d)\n", rtw_read32(padapter, 0x204), rtw_read32(padapter, 0x200), i); */
-+				rtw_msleep_os(10);
-+			} else {
-+				RTW_INFO("[HW_VAR_CHECK_TXBUF] no packet in tx packet buffer (%d)\n", i);
-+				break;
-+			}
-+		}
-+
-+		if (reg_200 != reg_204)
-+			RTW_INFO("packets in tx buffer - 0x204=%x, 0x200=%x\n", reg_204, reg_200);
-+
-+		RetryLimit = RL_VAL_STA;
-+		val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);
-+		rtw_write16(padapter, REG_RETRY_LIMIT, val16);
-+	}
-+	break;
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+	case HW_VAR_NAV_UPPER: {
-+		u32 usNavUpper = *((u32 *)val);
-+
-+		if (usNavUpper > HAL_NAV_UPPER_UNIT_8703B * 0xFF) {
-+			break;
-+		}
-+
-+		/* The value of ((usNavUpper + HAL_NAV_UPPER_UNIT_8703B - 1) / HAL_NAV_UPPER_UNIT_8703B) */
-+		/* is getting the upper integer. */
-+		usNavUpper = (usNavUpper + HAL_NAV_UPPER_UNIT_8703B - 1) / HAL_NAV_UPPER_UNIT_8703B;
-+		rtw_write8(padapter, REG_NAV_UPPER, (u8)usNavUpper);
-+	}
-+	break;
-+
-+	case HW_VAR_BCN_VALID:
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (padapter->hw_port == HW_PORT1) {
-+			val8 = rtw_read8(padapter,  REG_DWBCN1_CTRL_8703B + 2);
-+			val8 |= BIT(0);
-+			rtw_write8(padapter, REG_DWBCN1_CTRL_8703B + 2, val8);
-+		} else
-+#endif /* CONFIG_CONCURRENT_MODE */
-+		{
-+			/* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */
-+			val8 = rtw_read8(padapter, REG_TDECTRL + 2);
-+			val8 |= BIT(0);
-+			rtw_write8(padapter, REG_TDECTRL + 2, val8);
-+		}
-+		break;
-+
-+	case HW_VAR_DL_BCN_SEL:
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (padapter->hw_port == HW_PORT1) {
-+			/* SW_BCN_SEL - Port1 */
-+			val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8703B + 2);
-+			val8 |= BIT(4);
-+			rtw_write8(padapter, REG_DWBCN1_CTRL_8703B + 2, val8);
-+		} else
-+#endif /* CONFIG_CONCURRENT_MODE */
-+		{
-+			/* SW_BCN_SEL - Port0 */
-+			val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8703B + 2);
-+			val8 &= ~BIT(4);
-+			rtw_write8(padapter, REG_DWBCN1_CTRL_8703B + 2, val8);
-+		}
-+		break;
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+	case HW_SET_GPIO_WL_CTRL: {
-+		u8 enable = *val;
-+		u8 value = rtw_read8(padapter, 0x4e);
-+		if (enable && (value & BIT(6))) {
-+			value &= ~BIT(6);
-+			rtw_write8(padapter, 0x4e, value);
-+		} else if (enable == _FALSE) {
-+			value |= BIT(6);
-+			rtw_write8(padapter, 0x4e, value);
-+		}
-+		RTW_INFO("%s: set WL control, 0x4E=0x%02X\n",
-+			 __func__, rtw_read8(padapter, 0x4e));
-+	}
-+	break;
-+#endif
-+
-+	default:
-+		ret = SetHwReg(padapter, variable, val);
-+		break;
-+	}
-+
-+	return ret;
-+}
-+#ifdef CONFIG_PROC_DEBUG
-+struct qinfo_8703b {
-+	u32 head:8;
-+	u32 pkt_num:7;
-+	u32 tail:8;
-+	u32 ac:2;
-+	u32 macid:7;
-+};
-+
-+struct bcn_qinfo_8703b {
-+	u16 head:8;
-+	u16 pkt_num:8;
-+};
-+
-+void dump_qinfo_8703b(void *sel, struct qinfo_8703b *info, const char *tag)
-+{
-+	/* if (info->pkt_num) */
-+	RTW_PRINT_SEL(sel, "%shead:0x%02x, tail:0x%02x, pkt_num:%u, macid:%u, ac:%u\n"
-+		, tag ? tag : "", info->head, info->tail, info->pkt_num, info->macid, info->ac
-+		     );
-+}
-+
-+void dump_bcn_qinfo_8703b(void *sel, struct bcn_qinfo_8703b *info, const char *tag)
-+{
-+	/* if (info->pkt_num) */
-+	RTW_PRINT_SEL(sel, "%shead:0x%02x, pkt_num:%u\n"
-+		      , tag ? tag : "", info->head, info->pkt_num
-+		     );
-+}
-+
-+void dump_mac_qinfo_8703b(void *sel, _adapter *adapter)
-+{
-+	u32 q0_info;
-+	u32 q1_info;
-+	u32 q2_info;
-+	u32 q3_info;
-+	u32 q4_info;
-+	u32 q5_info;
-+	u32 q6_info;
-+	u32 q7_info;
-+	u32 mg_q_info;
-+	u32 hi_q_info;
-+	u16 bcn_q_info;
-+
-+	q0_info = rtw_read32(adapter, REG_Q0_INFO);
-+	q1_info = rtw_read32(adapter, REG_Q1_INFO);
-+	q2_info = rtw_read32(adapter, REG_Q2_INFO);
-+	q3_info = rtw_read32(adapter, REG_Q3_INFO);
-+	q4_info = rtw_read32(adapter, REG_Q4_INFO);
-+	q5_info = rtw_read32(adapter, REG_Q5_INFO);
-+	q6_info = rtw_read32(adapter, REG_Q6_INFO);
-+	q7_info = rtw_read32(adapter, REG_Q7_INFO);
-+	mg_q_info = rtw_read32(adapter, REG_MGQ_INFO);
-+	hi_q_info = rtw_read32(adapter, REG_HGQ_INFO);
-+	bcn_q_info = rtw_read16(adapter, REG_BCNQ_INFO);
-+
-+	dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q0_info, "Q0 ");
-+	dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q1_info, "Q1 ");
-+	dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q2_info, "Q2 ");
-+	dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q3_info, "Q3 ");
-+	dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q4_info, "Q4 ");
-+	dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q5_info, "Q5 ");
-+	dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q6_info, "Q6 ");
-+	dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q7_info, "Q7 ");
-+	dump_qinfo_8703b(sel, (struct qinfo_8703b *)&mg_q_info, "MG ");
-+	dump_qinfo_8703b(sel, (struct qinfo_8703b *)&hi_q_info, "HI ");
-+	dump_bcn_qinfo_8703b(sel, (struct bcn_qinfo_8703b *)&bcn_q_info, "BCN ");
-+}
-+
-+static void dump_mac_txfifo_8703b(void *sel, _adapter *adapter)
-+{
-+	u32 rqpn, rqpn_npq;
-+	u32 hpq, lpq, npq, epq, pubq;
-+
-+	rqpn = rtw_read32(adapter, REG_FIFOPAGE);
-+	rqpn_npq = rtw_read32(adapter, REG_RQPN_NPQ);
-+
-+	hpq = (rqpn & 0xFF);
-+	lpq = ((rqpn & 0xFF00)>>8);
-+	pubq = ((rqpn & 0xFF0000)>>16);
-+	npq = ((rqpn_npq & 0xFF00)>>8);
-+	epq = ((rqpn_npq & 0xFF000000)>>24);
-+
-+	RTW_PRINT_SEL(sel, "Tx: available page num: ");
-+	if ((hpq == 0xEA) && (hpq == lpq) && (hpq == pubq))
-+		RTW_PRINT_SEL(sel, "N/A (reg val = 0xea)\n");
-+	else
-+		RTW_PRINT_SEL(sel, "HPQ: %d, LPQ: %d, NPQ: %d, EPQ: %d, PUBQ: %d\n"
-+			, hpq, lpq, npq, epq, pubq);
-+}
-+#endif
-+
-+void GetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+	u8 val8;
-+	u16 val16;
-+	u32 val32;
-+
-+
-+	switch (variable) {
-+	case HW_VAR_TXPAUSE:
-+		*val = rtw_read8(padapter, REG_TXPAUSE);
-+		break;
-+
-+	case HW_VAR_BCN_VALID:
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (padapter->hw_port == HW_PORT1) {
-+			val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8703B + 2);
-+			*val = (BIT(0) & val8) ? _TRUE : _FALSE;
-+		} else
-+#endif
-+		{
-+			/* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */
-+			val8 = rtw_read8(padapter, REG_TDECTRL + 2);
-+			*val = (BIT(0) & val8) ? _TRUE : _FALSE;
-+		}
-+		break;
-+
-+	case HW_VAR_EFUSE_USAGE:
-+		*val = pHalData->EfuseUsedPercentage;
-+		break;
-+
-+	case HW_VAR_EFUSE_BYTES:
-+		*((u16 *)val) = pHalData->EfuseUsedBytes;
-+		break;
-+
-+	case HW_VAR_EFUSE_BT_USAGE:
-+#ifdef HAL_EFUSE_MEMORY
-+		*val = pHalData->EfuseHal.BTEfuseUsedPercentage;
-+#endif
-+		break;
-+
-+	case HW_VAR_EFUSE_BT_BYTES:
-+#ifdef HAL_EFUSE_MEMORY
-+		*((u16 *)val) = pHalData->EfuseHal.BTEfuseUsedBytes;
-+#else
-+		*((u16 *)val) = BTEfuseUsedBytes;
-+#endif
-+		break;
-+
-+	case HW_VAR_CHK_HI_QUEUE_EMPTY:
-+		val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
-+		*val = (val16 & BIT(10)) ? _TRUE : _FALSE;
-+		break;
-+	case HW_VAR_CHK_MGQ_CPU_EMPTY:
-+		val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
-+		*val = (val16 & BIT(8)) ? _TRUE : _FALSE;
-+		break;
-+#ifdef CONFIG_WOWLAN
-+	case HW_VAR_RPWM_TOG:
-+		*val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1) & BIT7;
-+		break;
-+	case HW_VAR_WAKEUP_REASON:
-+		*val = rtw_read8(padapter, REG_WOWLAN_WAKE_REASON);
-+		if (*val == 0xEA)
-+			*val = 0;
-+		break;
-+	case HW_VAR_SYS_CLKR:
-+		*val = rtw_read8(padapter, REG_SYS_CLKR);
-+		break;
-+#endif
-+#ifdef CONFIG_PROC_DEBUG
-+	case HW_VAR_DUMP_MAC_QUEUE_INFO:
-+		dump_mac_qinfo_8703b(val, padapter);
-+		break;
-+	case HW_VAR_DUMP_MAC_TXFIFO:
-+		dump_mac_txfifo_8703b(val, padapter);
-+		break;
-+#endif
-+	default:
-+		GetHwReg(padapter, variable, val);
-+		break;
-+	}
-+}
-+
-+/*
-+ *	Description:
-+ *		Change default setting of specified variable.
-+ */
-+u8 SetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+	u8 bResult;
-+
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	bResult = _SUCCESS;
-+
-+	switch (variable) {
-+	default:
-+		bResult = SetHalDefVar(padapter, variable, pval);
-+		break;
-+	}
-+
-+	return bResult;
-+}
-+
-+void hal_ra_info_dump(_adapter *padapter , void *sel)
-+{
-+	int i;
-+	u8 mac_id;
-+	u32 cmd;
-+	u32 ra_info1, ra_info2, bw_set;
-+	u32 rate_mask1, rate_mask2;
-+	u8 curr_tx_rate, curr_tx_sgi, hight_rate, lowest_rate;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	HAL_DATA_TYPE *HalData = GET_HAL_DATA(padapter);
-+
-+	for (i = 0; i < macid_ctl->num; i++) {
-+
-+		if (rtw_macid_is_used(macid_ctl, i) && !rtw_macid_is_bmc(macid_ctl, i)) {
-+
-+			mac_id = (u8) i;
-+			_RTW_PRINT_SEL(sel , "============ RA status check  Mac_id:%d ===================\n", mac_id);
-+
-+			cmd = 0x40000100 | mac_id;
-+			rtw_write32(padapter, REG_HMEBOX_DBG_2_8703B, cmd);
-+			rtw_msleep_os(10);
-+			ra_info1 = rtw_read32(padapter, 0x2F0);
-+			curr_tx_sgi = rtw_get_current_tx_sgi(padapter, macid_ctl->sta[mac_id]);
-+			curr_tx_rate = rtw_get_current_tx_rate(padapter, macid_ctl->sta[mac_id]);
-+
-+			_RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] =>cur_tx_rate= %s,cur_sgi:%d\n", ra_info1, HDATA_RATE(curr_tx_rate), curr_tx_sgi);
-+			_RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] => PWRSTS = 0x%02x\n", ra_info1, (ra_info1 >> 8)  & 0x07);
-+
-+			cmd = 0x40000400 | mac_id;
-+			rtw_write32(padapter, REG_HMEBOX_DBG_2_8703B, cmd);
-+			rtw_msleep_os(10);
-+			ra_info1 = rtw_read32(padapter, 0x2F0);
-+			ra_info2 = rtw_read32(padapter, 0x2F4);
-+			rate_mask1 = rtw_read32(padapter, 0x2F8);
-+			rate_mask2 = rtw_read32(padapter, 0x2FC);
-+			hight_rate = ra_info2 & 0xFF;
-+			lowest_rate = (ra_info2 >> 8)  & 0xFF;
-+			bw_set = (ra_info1 >> 8)  & 0xFF;
-+
-+			_RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] => VHT_EN=0x%02x, ", ra_info1, (ra_info1 >> 24) & 0xFF);
-+
-+
-+			switch (bw_set) {
-+
-+			case CHANNEL_WIDTH_20:
-+				_RTW_PRINT_SEL(sel , "BW_setting=20M\n");
-+				break;
-+
-+			case CHANNEL_WIDTH_40:
-+				_RTW_PRINT_SEL(sel , "BW_setting=40M\n");
-+				break;
-+
-+			case CHANNEL_WIDTH_80:
-+				_RTW_PRINT_SEL(sel , "BW_setting=80M\n");
-+				break;
-+
-+			case CHANNEL_WIDTH_160:
-+				_RTW_PRINT_SEL(sel , "BW_setting=160M\n");
-+				break;
-+
-+			default:
-+				_RTW_PRINT_SEL(sel , "BW_setting=0x%02x\n", bw_set);
-+				break;
-+
-+			}
-+
-+			_RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] =>RSSI=%d, DISRA=0x%02x\n",
-+				       ra_info1,
-+				       ra_info1 & 0xFF,
-+				       (ra_info1 >> 16) & 0xFF);
-+
-+			_RTW_PRINT_SEL(sel , "[ ra_info2:0x%08x ] =>hight_rate=%s, lowest_rate=%s, SGI=0x%02x, RateID=%d\n",
-+				       ra_info2,
-+				       HDATA_RATE(hight_rate),
-+				       HDATA_RATE(lowest_rate),
-+				       (ra_info2 >> 16) & 0xFF,
-+				       (ra_info2 >> 24) & 0xFF);
-+
-+			_RTW_PRINT_SEL(sel , "rate_mask2=0x%08x, rate_mask1=0x%08x\n", rate_mask2, rate_mask1);
-+
-+		}
-+	}
-+}
-+
-+/*
-+ *	Description:
-+ *		Query setting of specified variable.
-+ */
-+u8 GetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+	u8 bResult;
-+
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	bResult = _SUCCESS;
-+
-+	switch (variable) {
-+	case HAL_DEF_MAX_RECVBUF_SZ:
-+		*((u32 *)pval) = MAX_RECVBUF_SZ;
-+		break;
-+
-+	case HAL_DEF_RX_PACKET_OFFSET:
-+		*((u32 *)pval) = RXDESC_SIZE + DRVINFO_SZ * 8;
-+		break;
-+
-+	case HW_VAR_MAX_RX_AMPDU_FACTOR:
-+		/* Stanley@BB.SD3 suggests 16K can get stable performance */
-+		/* The experiment was done on SDIO interface */
-+		/* coding by Lucas@20130730 */
-+		*(HT_CAP_AMPDU_FACTOR *)pval = MAX_AMPDU_FACTOR_16K;
-+		break;
-+	case HW_VAR_BEST_AMPDU_DENSITY:
-+		*((u32 *)pval) = AMPDU_DENSITY_VALUE_7;
-+		break;
-+	case HAL_DEF_TX_LDPC:
-+	case HAL_DEF_RX_LDPC:
-+		*((u8 *)pval) = _FALSE;
-+		break;
-+	case HAL_DEF_RX_STBC:
-+		*((u8 *)pval) = 1;
-+		break;
-+	case HAL_DEF_EXPLICIT_BEAMFORMER:
-+	case HAL_DEF_EXPLICIT_BEAMFORMEE:
-+		*((u8 *)pval) = _FALSE;
-+		break;
-+
-+	case HW_DEF_RA_INFO_DUMP:
-+		hal_ra_info_dump(padapter, pval);
-+		break;
-+
-+	case HAL_DEF_TX_PAGE_BOUNDARY:
-+		if (!padapter->registrypriv.wifi_spec)
-+			*(u8 *)pval = TX_PAGE_BOUNDARY_8703B;
-+		else
-+			*(u8 *)pval = WMM_NORMAL_TX_PAGE_BOUNDARY_8703B;
-+		break;
-+	case HAL_DEF_TX_PAGE_SIZE:
-+		*((u32 *)pval) = PAGE_SIZE_128;
-+		break;
-+	case HAL_DEF_RX_DMA_SZ_WOW:
-+		*(u32 *)pval = RX_DMA_SIZE_8703B - RESV_FMWF;
-+		break;
-+	case HAL_DEF_RX_DMA_SZ:
-+		*(u32 *)pval = RX_DMA_BOUNDARY_8703B + 1;
-+		break;
-+	case HAL_DEF_RX_PAGE_SIZE:
-+		*((u32 *)pval) = 8;
-+		break;
-+	default:
-+		bResult = GetHalDefVar(padapter, variable, pval);
-+		break;
-+	}
-+
-+	return bResult;
-+}
-+
-+#ifdef CONFIG_WOWLAN
-+void Hal_DetectWoWMode(PADAPTER pAdapter)
-+{
-+	adapter_to_pwrctl(pAdapter)->bSupportRemoteWakeup = _TRUE;
-+	RTW_INFO("%s\n", __func__);
-+}
-+#endif /* CONFIG_WOWLAN */
-+
-+void rtl8703b_start_thread(_adapter *padapter)
-+{
-+#if (defined CONFIG_SDIO_HCI) || (defined CONFIG_GSPI_HCI)
-+#ifndef CONFIG_SDIO_TX_TASKLET
-+	struct xmit_priv *xmitpriv = &padapter->xmitpriv;
-+
-+	if (xmitpriv->SdioXmitThread == NULL) {
-+		RTW_INFO(FUNC_ADPT_FMT " start RTWHALXT\n", FUNC_ADPT_ARG(padapter));
-+		xmitpriv->SdioXmitThread = kthread_run(rtl8703bs_xmit_thread, padapter, "RTWHALXT");
-+		if (IS_ERR(xmitpriv->SdioXmitThread)) {
-+			RTW_ERR("%s: start rtl8703bs_xmit_thread FAIL!!\n", __func__);
-+			xmitpriv->SdioXmitThread = NULL;
-+		}
-+	}
-+#endif
-+#endif
-+}
-+
-+void rtl8703b_stop_thread(_adapter *padapter)
-+{
-+#if (defined CONFIG_SDIO_HCI) || (defined CONFIG_GSPI_HCI)
-+#ifndef CONFIG_SDIO_TX_TASKLET
-+	struct xmit_priv *xmitpriv = &padapter->xmitpriv;
-+
-+	/* stop xmit_buf_thread */
-+	if (xmitpriv->SdioXmitThread) {
-+		_rtw_up_sema(&xmitpriv->SdioXmitSema);
-+		rtw_thread_stop(xmitpriv->SdioXmitThread);
-+		xmitpriv->SdioXmitThread = NULL;
-+	}
-+#endif
-+#endif
-+}
-+
-+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
-+extern void check_bt_status_work(void *data);
-+void rtl8703bs_init_checkbthang_workqueue(_adapter *adapter)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
-+	adapter->priv_checkbt_wq = alloc_workqueue("sdio_wq", 0, 0);
-+#else
-+	adapter->priv_checkbt_wq = create_workqueue("sdio_wq");
-+#endif
-+	INIT_DELAYED_WORK(&adapter->checkbt_work, (void *)check_bt_status_work);
-+}
-+
-+void rtl8703bs_free_checkbthang_workqueue(_adapter *adapter)
-+{
-+	if (adapter->priv_checkbt_wq) {
-+		cancel_delayed_work_sync(&adapter->checkbt_work);
-+		flush_workqueue(adapter->priv_checkbt_wq);
-+		destroy_workqueue(adapter->priv_checkbt_wq);
-+		adapter->priv_checkbt_wq = NULL;
-+	}
-+}
-+
-+void rtl8703bs_cancle_checkbthang_workqueue(_adapter *adapter)
-+{
-+	if (adapter->priv_checkbt_wq)
-+		cancel_delayed_work_sync(&adapter->checkbt_work);
-+}
-+
-+void rtl8703bs_hal_check_bt_hang(_adapter *adapter)
-+{
-+	if (adapter->priv_checkbt_wq)
-+		queue_delayed_work(adapter->priv_checkbt_wq, &(adapter->checkbt_work), 0);
-+}
-+#endif
-+
-+void rtl8703b_set_hal_ops(struct hal_ops *pHalFunc)
-+{
-+	pHalFunc->dm_init = &rtl8703b_init_dm_priv;
-+	pHalFunc->dm_deinit = &rtl8703b_deinit_dm_priv;
-+
-+	pHalFunc->read_chip_version = read_chip_version_8703b;
-+
-+	pHalFunc->set_chnl_bw_handler = &PHY_SetSwChnlBWMode8703B;
-+
-+	pHalFunc->set_tx_power_level_handler = &PHY_SetTxPowerLevel8703B;
-+	pHalFunc->set_tx_power_index_handler = PHY_SetTxPowerIndex_8703B;
-+	pHalFunc->get_tx_power_index_handler = hal_com_get_txpwr_idx;
-+
-+	pHalFunc->hal_dm_watchdog = &rtl8703b_HalDmWatchDog;
-+
-+	pHalFunc->SetBeaconRelatedRegistersHandler = &rtl8703b_SetBeaconRelatedRegisters;
-+
-+	pHalFunc->run_thread = &rtl8703b_start_thread;
-+	pHalFunc->cancel_thread = &rtl8703b_stop_thread;
-+
-+	pHalFunc->read_bbreg = &PHY_QueryBBReg_8703B;
-+	pHalFunc->write_bbreg = &PHY_SetBBReg_8703B;
-+	pHalFunc->read_rfreg = &PHY_QueryRFReg_8703B;
-+	pHalFunc->write_rfreg = &PHY_SetRFReg_8703B;
-+
-+	/* Efuse related function */
-+	pHalFunc->BTEfusePowerSwitch = &Hal_BT_EfusePowerSwitch;
-+	pHalFunc->EfusePowerSwitch = &Hal_EfusePowerSwitch;
-+	pHalFunc->ReadEFuse = &Hal_ReadEFuse;
-+	pHalFunc->EFUSEGetEfuseDefinition = &Hal_GetEfuseDefinition;
-+	pHalFunc->EfuseGetCurrentSize = &Hal_EfuseGetCurrentSize;
-+	pHalFunc->Efuse_PgPacketRead = &Hal_EfusePgPacketRead;
-+	pHalFunc->Efuse_PgPacketWrite = &Hal_EfusePgPacketWrite;
-+	pHalFunc->Efuse_WordEnableDataWrite = &Hal_EfuseWordEnableDataWrite;
-+	pHalFunc->Efuse_PgPacketWrite_BT = &Hal_EfusePgPacketWrite_BT;
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	pHalFunc->sreset_init_value = &sreset_init_value;
-+	pHalFunc->sreset_reset_value = &sreset_reset_value;
-+	pHalFunc->silentreset = &sreset_reset;
-+	pHalFunc->sreset_xmit_status_check = &rtl8703b_sreset_xmit_status_check;
-+	pHalFunc->sreset_linked_status_check  = &rtl8703b_sreset_linked_status_check;
-+	pHalFunc->sreset_get_wifi_status  = &sreset_get_wifi_status;
-+	pHalFunc->sreset_inprogress = &sreset_inprogress;
-+#endif
-+	pHalFunc->GetHalODMVarHandler = GetHalODMVar;
-+	pHalFunc->SetHalODMVarHandler = SetHalODMVar;
-+
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+	pHalFunc->xmit_thread_handler = &hal_xmit_handler;
-+#endif
-+	pHalFunc->hal_notch_filter = &hal_notch_filter_8703b;
-+
-+	pHalFunc->c2h_handler = c2h_handler_8703b;
-+
-+	pHalFunc->fill_h2c_cmd = &FillH2CCmd8703B;
-+	pHalFunc->fill_fake_txdesc = &rtl8703b_fill_fake_txdesc;
-+	pHalFunc->fw_dl = &rtl8703b_FirmwareDownload;
-+	pHalFunc->hal_get_tx_buff_rsvd_page_num = &GetTxBufferRsvdPageNum8703B;
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_phycfg.c b/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_phycfg.c
-new file mode 100644
-index 000000000000..b786c18a7b66
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_phycfg.c
-@@ -0,0 +1,1282 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTL8703B_PHYCFG_C_
-+
-+#include <rtl8703b_hal.h>
-+
-+
-+/*---------------------------Define Local Constant---------------------------*/
-+/* Channel switch:The size of command tables for switch channel*/
-+#define MAX_PRECMD_CNT 16
-+#define MAX_RFDEPENDCMD_CNT 16
-+#define MAX_POSTCMD_CNT 16
-+
-+#define MAX_DOZE_WAITING_TIMES_9x 64
-+
-+/*---------------------------Define Local Constant---------------------------*/
-+
-+
-+/*------------------------Define global variable-----------------------------*/
-+
-+/*------------------------Define local variable------------------------------*/
-+
-+
-+/*--------------------Define export function prototype-----------------------*/
-+/* Please refer to header file
-+ *--------------------Define export function prototype-----------------------*/
-+
-+/*----------------------------Function Body----------------------------------*/
-+/*
-+ * 1. BB register R/W API
-+ *   */
-+
-+/**
-+* Function:	phy_CalculateBitShift
-+*
-+* OverView:	Get shifted position of the BitMask
-+*
-+* Input:
-+*			u32		BitMask,
-+*
-+* Output:	none
-+* Return:		u32		Return the shift bit bit position of the mask
-+*/
-+static	u32
-+phy_CalculateBitShift(
-+	u32 BitMask
-+)
-+{
-+	u32 i;
-+
-+	for (i = 0; i <= 31; i++) {
-+		if (((BitMask >> i) &  0x1) == 1)
-+			break;
-+	}
-+
-+	return i;
-+}
-+
-+
-+/**
-+* Function:	PHY_QueryBBReg
-+*
-+* OverView:	Read "sepcific bits" from BB register
-+*
-+* Input:
-+*			PADAPTER		Adapter,
-+*			u32			RegAddr,		//The target address to be readback
-+*			u32			BitMask		//The target bit position in the target address
-+*										//to be readback
-+* Output:	None
-+* Return:		u32			Data			//The readback register value
-+* Note:		This function is equal to "GetRegSetting" in PHY programming guide
-+*/
-+u32
-+PHY_QueryBBReg_8703B(
-+		PADAPTER	Adapter,
-+		u32		RegAddr,
-+		u32		BitMask
-+)
-+{
-+	u32	ReturnValue = 0, OriginalValue, BitShift;
-+	u16	BBWaitCounter = 0;
-+
-+#if (DISABLE_BB_RF == 1)
-+	return 0;
-+#endif
-+
-+
-+	OriginalValue = rtw_read32(Adapter, RegAddr);
-+	BitShift = phy_CalculateBitShift(BitMask);
-+	ReturnValue = (OriginalValue & BitMask) >> BitShift;
-+
-+	return ReturnValue;
-+
-+}
-+
-+
-+/**
-+* Function:	PHY_SetBBReg
-+*
-+* OverView:	Write "Specific bits" to BB register (page 8~)
-+*
-+* Input:
-+*			PADAPTER		Adapter,
-+*			u32			RegAddr,		//The target address to be modified
-+*			u32			BitMask		//The target bit position in the target address
-+*										//to be modified
-+*			u32			Data			//The new register value in the target bit position
-+*										//of the target address
-+*
-+* Output:	None
-+* Return:		None
-+* Note:		This function is equal to "PutRegSetting" in PHY programming guide
-+*/
-+
-+void
-+PHY_SetBBReg_8703B(
-+		PADAPTER	Adapter,
-+		u32		RegAddr,
-+		u32		BitMask,
-+		u32		Data
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData		= GET_HAL_DATA(Adapter);
-+	/* u16			BBWaitCounter	= 0; */
-+	u32			OriginalValue, BitShift;
-+
-+#if (DISABLE_BB_RF == 1)
-+	return;
-+#endif
-+
-+
-+	if (BitMask != bMaskDWord) { /* if not "double word" write */
-+		OriginalValue = rtw_read32(Adapter, RegAddr);
-+		BitShift = phy_CalculateBitShift(BitMask);
-+		Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
-+	}
-+
-+	rtw_write32(Adapter, RegAddr, Data);
-+
-+}
-+
-+
-+/*
-+ * 2. RF register R/W API
-+ *   */
-+static	u32
-+phy_RFSerialRead_8703B(
-+		PADAPTER			Adapter,
-+		enum rf_path			eRFPath,
-+		u32				Offset
-+)
-+{
-+	u32						retValue = 0;
-+	HAL_DATA_TYPE				*pHalData = GET_HAL_DATA(Adapter);
-+	BB_REGISTER_DEFINITION_T	*pPhyReg = &pHalData->PHYRegDef[eRFPath];
-+	u32						NewOffset;
-+	u32						tmplong, tmplong2;
-+	u8					RfPiEnable = 0;
-+	u32						MaskforPhySet = 0;
-+	int i = 0;
-+
-+	_enter_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
-+	/*  */
-+	/* Make sure RF register offset is correct */
-+	/*  */
-+	Offset &= 0xff;
-+
-+	NewOffset = Offset;
-+
-+	if (eRFPath == RF_PATH_A) {
-+		tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
-+		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;	/* T65 RF */
-+		phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
-+	} else {
-+		tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord);
-+		tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge;	/* T65 RF */
-+		phy_set_bb_reg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
-+	}
-+
-+	tmplong2 = phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord);
-+	phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
-+	phy_set_bb_reg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
-+
-+	rtw_udelay_os(10);
-+
-+	for (i = 0; i < 2; i++)
-+		rtw_udelay_os(MAX_STALL_TIME);
-+	rtw_udelay_os(10);
-+
-+	if (eRFPath == RF_PATH_A)
-+		RfPiEnable = (u8)phy_query_bb_reg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT8);
-+	else if (eRFPath == RF_PATH_B)
-+		RfPiEnable = (u8)phy_query_bb_reg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT8);
-+
-+	if (RfPiEnable) {
-+		/* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
-+		retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData);
-+
-+		/* RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue)); */
-+	} else {
-+		/* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
-+		retValue = phy_query_bb_reg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData);
-+
-+		/* RT_DISP(FINIT, INIT_RF,("Readback from RF-SI : 0x%x\n", retValue)); */
-+	}
-+	_exit_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL);
-+	return retValue;
-+
-+}
-+
-+/**
-+* Function:	phy_RFSerialWrite_8703B
-+*
-+* OverView:	Write data to RF register (page 8~)
-+*
-+* Input:
-+*			PADAPTER		Adapter,
-+			enum rf_path			eRFPath,	//Radio path of A/B/C/D
-+*			u32			Offset,		//The target address to be read
-+*			u32			Data			//The new register Data in the target bit position
-+*										//of the target to be read
-+*
-+* Output:	None
-+* Return:		None
-+* Note:		Threre are three types of serial operations:
-+*			1. Software serial write
-+*			2. Hardware LSSI-Low Speed Serial Interface
-+*			3. Hardware HSSI-High speed
-+*			serial write. Driver need to implement (1) and (2).
-+*			This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
-+ *
-+ * Note:		  For RF8256 only
-+ *			 The total count of RTL8256(Zebra4) register is around 36 bit it only employs
-+ *			 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
-+ *			 to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
-+ *			 programming guide" for more details.
-+ *			 Thus, we define a sub-finction for RTL8526 register address conversion
-+ *		       ===========================================================
-+ *			 Register Mode		RegCTL[1]		RegCTL[0]		Note
-+ *								(Reg00[12])		(Reg00[10])
-+ *		       ===========================================================
-+ *			 Reg_Mode0				0				x			Reg 0 ~15(0x0 ~ 0xf)
-+ *		       ------------------------------------------------------------------
-+ *			 Reg_Mode1				1				0			Reg 16 ~30(0x1 ~ 0xf)
-+ *		       ------------------------------------------------------------------
-+ *			 Reg_Mode2				1				1			Reg 31 ~ 45(0x1 ~ 0xf)
-+ *		       ------------------------------------------------------------------
-+ *
-+ *	2008/09/02	MH	Add 92S RF definition
-+ *
-+ *
-+ *
-+*/
-+static	void
-+phy_RFSerialWrite_8703B(
-+		PADAPTER			Adapter,
-+		enum rf_path			eRFPath,
-+		u32				Offset,
-+		u32				Data
-+)
-+{
-+	u32						DataAndAddr = 0;
-+	HAL_DATA_TYPE				*pHalData = GET_HAL_DATA(Adapter);
-+	BB_REGISTER_DEFINITION_T	*pPhyReg = &pHalData->PHYRegDef[eRFPath];
-+	u32						NewOffset;
-+
-+	Offset &= 0xff;
-+
-+	/*  */
-+	/* Shadow Update */
-+	/*  */
-+	/* PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); */
-+
-+	/*  */
-+	/* Switch page for 8256 RF IC */
-+	/*  */
-+	NewOffset = Offset;
-+
-+	/*  */
-+	/* Put write addr in [5:0]  and write data in [31:16] */
-+	/*  */
-+	/* DataAndAddr = (Data<<16) | (NewOffset&0x3f); */
-+	DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff;	/* T65 RF */
-+
-+	/*  */
-+	/* Write Operation */
-+	/*  */
-+	phy_set_bb_reg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
-+	/* RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */
-+
-+}
-+
-+
-+/**
-+* Function:	PHY_QueryRFReg
-+*
-+* OverView:	Query "Specific bits" to RF register (page 8~)
-+*
-+* Input:
-+*			PADAPTER		Adapter,
-+			enum rf_path			eRFPath,	//Radio path of A/B/C/D
-+*			u32			RegAddr,		//The target address to be read
-+*			u32			BitMask		//The target bit position in the target address
-+*										//to be read
-+*
-+* Output:	None
-+* Return:		u32			Readback value
-+* Note:		This function is equal to "GetRFRegSetting" in PHY programming guide
-+*/
-+u32
-+PHY_QueryRFReg_8703B(
-+		PADAPTER			Adapter,
-+		enum rf_path			eRFPath,
-+		u32				RegAddr,
-+		u32				BitMask
-+)
-+{
-+	u32 Original_Value, Readback_Value, BitShift;
-+
-+#if (DISABLE_BB_RF == 1)
-+	return 0;
-+#endif
-+
-+	Original_Value = phy_RFSerialRead_8703B(Adapter, eRFPath, RegAddr);
-+
-+	BitShift =  phy_CalculateBitShift(BitMask);
-+	Readback_Value = (Original_Value & BitMask) >> BitShift;
-+
-+	return Readback_Value;
-+}
-+
-+/**
-+* Function:	PHY_SetRFReg
-+*
-+* OverView:	Write "Specific bits" to RF register (page 8~)
-+*
-+* Input:
-+*			PADAPTER		Adapter,
-+			enum rf_path			eRFPath,	//Radio path of A/B/C/D
-+*			u32			RegAddr,		//The target address to be modified
-+*			u32			BitMask		//The target bit position in the target address
-+*										//to be modified
-+*			u32			Data			//The new register Data in the target bit position
-+*										//of the target address
-+*
-+* Output:	None
-+* Return:		None
-+* Note:		This function is equal to "PutRFRegSetting" in PHY programming guide
-+*/
-+void
-+PHY_SetRFReg_8703B(
-+		PADAPTER			Adapter,
-+		enum rf_path				eRFPath,
-+		u32				RegAddr,
-+		u32				BitMask,
-+		u32				Data
-+)
-+{
-+	u32		Original_Value, BitShift;
-+
-+#if (DISABLE_BB_RF == 1)
-+	return;
-+#endif
-+
-+	/* RF data is 12 bits only */
-+	if (BitMask != bRFRegOffsetMask) {
-+		Original_Value = phy_RFSerialRead_8703B(Adapter, eRFPath, RegAddr);
-+		BitShift =  phy_CalculateBitShift(BitMask);
-+		Data = ((Original_Value & (~BitMask)) | (Data << BitShift));
-+	}
-+
-+	phy_RFSerialWrite_8703B(Adapter, eRFPath, RegAddr, Data);
-+}
-+
-+
-+/*
-+ * 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
-+ *   */
-+
-+
-+/*-----------------------------------------------------------------------------
-+ * Function:    PHY_MACConfig8192C
-+ *
-+ * Overview:	Condig MAC by header file or parameter file.
-+ *
-+ * Input:       NONE
-+ *
-+ * Output:      NONE
-+ *
-+ * Return:      NONE
-+ *
-+ * Revised History:
-+ *  When		Who		Remark
-+ *  08/12/2008	MHC		Create Version 0.
-+ *
-+ *---------------------------------------------------------------------------*/
-+s32 PHY_MACConfig8703B(PADAPTER Adapter)
-+{
-+	int		rtStatus = _SUCCESS;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+
-+	/*  */
-+	/* Config MAC */
-+	/*  */
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+	rtStatus = phy_ConfigMACWithParaFile(Adapter, PHY_FILE_MAC_REG);
-+	if (rtStatus == _FAIL)
-+#endif
-+	{
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+		odm_config_mac_with_header_file(&pHalData->odmpriv);
-+		rtStatus = _SUCCESS;
-+#endif/* CONFIG_EMBEDDED_FWIMG */
-+	}
-+
-+	return rtStatus;
-+}
-+
-+/**
-+* Function:	phy_InitBBRFRegisterDefinition
-+*
-+* OverView:	Initialize Register definition offset for Radio Path A/B/C/D
-+*
-+* Input:
-+*			PADAPTER		Adapter,
-+*
-+* Output:	None
-+* Return:		None
-+* Note:		The initialization value is constant and it should never be changes
-+*/
-+static	void
-+phy_InitBBRFRegisterDefinition(
-+		PADAPTER		Adapter
-+)
-+{
-+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
-+
-+	/* RF Interface Sowrtware Control */
-+	pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */
-+	pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
-+
-+	/* RF Interface Output (and Enable) */
-+	pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */
-+	pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */
-+
-+	/* RF Interface (Output and)  Enable */
-+	pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
-+	pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
-+
-+	pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
-+	pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
-+
-+	pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  /* wire control parameter2 */
-+	pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  /* wire control parameter2 */
-+
-+	/* Tranceiver Readback LSSI/HSPI mode */
-+	pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
-+	pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
-+	pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
-+	pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
-+
-+}
-+
-+static	int
-+phy_BB8703b_Config_ParaFile(
-+		PADAPTER	Adapter
-+)
-+{
-+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
-+	int			rtStatus = _SUCCESS;
-+
-+	/*  */
-+	/* 1. Read PHY_REG.TXT BB INIT!! */
-+	/*  */
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+	if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_PHY_REG, CONFIG_BB_PHY_REG) == _FAIL)
-+#endif
-+	{
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+		if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
-+			rtStatus = _FAIL;
-+#endif
-+	}
-+
-+	if (rtStatus != _SUCCESS) {
-+		RTW_INFO("%s():Write BB Reg Fail!!", __func__);
-+		goto phy_BB8190_Config_ParaFile_Fail;
-+	}
-+
-+#if MP_DRIVER == 1
-+	if (Adapter->registrypriv.mp_mode == 1) {
-+		/*  */
-+		/* 1.1 Read PHY_REG_MP.TXT BB INIT!! */
-+		/*  */
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+		if (phy_ConfigBBWithMpParaFile(Adapter, PHY_FILE_PHY_REG_MP) == _FAIL)
-+#endif
-+		{
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+			if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_PHY_REG_MP))
-+				rtStatus = _FAIL;
-+#endif
-+		}
-+
-+		if (rtStatus != _SUCCESS) {
-+			RTW_INFO("%s():Write BB Reg MP Fail!!", __func__);
-+			goto phy_BB8190_Config_ParaFile_Fail;
-+		}
-+	}
-+#endif	/*  #if (MP_DRIVER == 1) */
-+
-+	/*  */
-+	/* 2. Read BB AGC table Initialization */
-+	/*  */
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+	if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_AGC_TAB, CONFIG_BB_AGC_TAB) == _FAIL)
-+#endif
-+	{
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+		if (HAL_STATUS_SUCCESS != odm_config_bb_with_header_file(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
-+			rtStatus = _FAIL;
-+#endif
-+	}
-+
-+	if (rtStatus != _SUCCESS) {
-+		RTW_INFO("%s():AGC Table Fail\n", __func__);
-+		goto phy_BB8190_Config_ParaFile_Fail;
-+	}
-+
-+phy_BB8190_Config_ParaFile_Fail:
-+
-+	return rtStatus;
-+}
-+
-+
-+int
-+PHY_BBConfig8703B(
-+		PADAPTER	Adapter
-+)
-+{
-+	int	rtStatus = _SUCCESS;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	u16	RegVal;
-+	u8	TmpU1B = 0;
-+	u8	value8;
-+ 
-+	phy_InitBBRFRegisterDefinition(Adapter);
-+
-+	/* Enable BB and RF */
-+	RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
-+ 
-+	RegVal |= BIT13 | FEN_BB_GLB_RSTn | FEN_BBRSTB;
-+	rtw_write16(Adapter, REG_SYS_FUNC_EN, RegVal);
-+	
-+	rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
-+
-+	rtw_usleep_os(10);
-+
-+	phy_set_rf_reg(Adapter, RF_PATH_A, 0x1, 0xfffff, 0x780);
-+
-+#if 0
-+	/* 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. */
-+	rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83);
-+	rtw_write8(Adapter, REG_AFE_PLL_CTRL + 1, 0xdb);
-+#endif
-+
-+
-+
-+	rtw_write8(Adapter, REG_AFE_XTAL_CTRL + 1, 0x80);
-+
-+	/*  */
-+	/* Config BB and AGC */
-+	/*  */
-+	rtStatus = phy_BB8703b_Config_ParaFile(Adapter);
-+
-+	if (rtw_phydm_set_crystal_cap(Adapter, pHalData->crystal_cap) == _FALSE) {
-+		RTW_ERR("Init crystal_cap failed\n");
-+		rtw_warn_on(1);
-+		rtStatus = _FAIL;
-+	}
-+
-+	return rtStatus;
-+}
-+
-+void phy_LCK_8703B(
-+		PADAPTER	Adapter
-+)
-+{
-+	phy_set_rf_reg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0);
-+	phy_set_rf_reg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x8C01);
-+	rtw_mdelay_os(200);
-+	phy_set_rf_reg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0);
-+}
-+
-+#if 0
-+/* Block & Path enable */
-+#define		rOFDMCCKEN_Jaguar 		0x808 /* OFDM/CCK block enable */
-+#define		bOFDMEN_Jaguar			0x20000000
-+#define		bCCKEN_Jaguar			0x10000000
-+#define		rRxPath_Jaguar			0x808	/* Rx antenna */
-+#define		bRxPath_Jaguar			0xff
-+#define		rTxPath_Jaguar			0x80c	/* Tx antenna */
-+#define		bTxPath_Jaguar			0x0fffffff
-+#define		rCCK_RX_Jaguar			0xa04	/* for cck rx path selection */
-+#define		bCCK_RX_Jaguar			0x0c000000
-+#define		rVhtlen_Use_Lsig_Jaguar	0x8c3	/* Use LSIG for VHT length */
-+void
-+PHY_BB8703B_Config_1T(
-+	PADAPTER Adapter
-+)
-+{
-+	/* BB OFDM RX Path_A */
-+	phy_set_bb_reg(Adapter, rRxPath_Jaguar, bRxPath_Jaguar, 0x11);
-+	/* BB OFDM TX Path_A */
-+	phy_set_bb_reg(Adapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
-+	/* BB CCK R/Rx Path_A */
-+	phy_set_bb_reg(Adapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
-+	/* MCS support */
-+	phy_set_bb_reg(Adapter, 0x8bc, 0xc0000060, 0x4);
-+	/* RF Path_B HSSI OFF */
-+	phy_set_bb_reg(Adapter, 0xe00, 0xf, 0x4);
-+	/* RF Path_B Power Down */
-+	phy_set_bb_reg(Adapter, 0xe90, bMaskDWord, 0);
-+	/* ADDA Path_B OFF */
-+	phy_set_bb_reg(Adapter, 0xe60, bMaskDWord, 0);
-+	phy_set_bb_reg(Adapter, 0xe64, bMaskDWord, 0);
-+}
-+#endif
-+
-+int
-+PHY_RFConfig8703B(
-+		PADAPTER	Adapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	int		rtStatus = _SUCCESS;
-+
-+	/*  */
-+	/* RF config */
-+	/*  */
-+	rtStatus = PHY_RF6052_Config8703B(Adapter);
-+
-+	phy_LCK_8703B(Adapter);
-+	/* PHY_BB8703B_Config_1T(Adapter); */
-+
-+	return rtStatus;
-+}
-+
-+/*-----------------------------------------------------------------------------
-+ * Function:    PHY_ConfigRFWithParaFile()
-+ *
-+ * Overview:    This function read RF parameters from general file format, and do RF 3-wire
-+ *
-+ * Input:	PADAPTER			Adapter
-+ *			ps1Byte				pFileName
-+ *			enum rf_path				eRFPath
-+ *
-+ * Output:      NONE
-+ *
-+ * Return:      RT_STATUS_SUCCESS: configuration file exist
-+ *
-+ * Note:		Delay may be required for RF configuration
-+ *---------------------------------------------------------------------------*/
-+int
-+PHY_ConfigRFWithParaFile_8703B(
-+		PADAPTER			Adapter,
-+		u8				*pFileName,
-+	enum rf_path				eRFPath
-+)
-+{
-+	return _SUCCESS;
-+}
-+
-+/**************************************************************************************************************
-+ *   Description:
-+ *       The low-level interface to set TxAGC , called by both MP and Normal Driver.
-+ *
-+ *                                                                                    <20120830, Kordan>
-+ **************************************************************************************************************/
-+
-+void
-+PHY_SetTxPowerIndex_8703B(
-+		PADAPTER			Adapter,
-+		u32					PowerIndex,
-+		enum rf_path			RFPath,
-+		u8					Rate
-+)
-+{
-+	if (RFPath == RF_PATH_A || RFPath == RF_PATH_B) {
-+		switch (Rate) {
-+		case MGN_1M:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_CCK1_Mcs32,      bMaskByte1, PowerIndex);
-+			break;
-+		case MGN_2M:
-+			phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex);
-+			break;
-+		case MGN_5_5M:
-+			phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex);
-+			break;
-+		case MGN_11M:
-+			phy_set_bb_reg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex);
-+			break;
-+
-+		case MGN_6M:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex);
-+			break;
-+		case MGN_9M:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex);
-+			break;
-+		case MGN_12M:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex);
-+			break;
-+		case MGN_18M:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex);
-+			break;
-+
-+		case MGN_24M:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex);
-+			break;
-+		case MGN_36M:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex);
-+			break;
-+		case MGN_48M:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex);
-+			break;
-+		case MGN_54M:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex);
-+			break;
-+
-+		case MGN_MCS0:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex);
-+			break;
-+		case MGN_MCS1:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex);
-+			break;
-+		case MGN_MCS2:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex);
-+			break;
-+		case MGN_MCS3:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex);
-+			break;
-+
-+		case MGN_MCS4:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex);
-+			break;
-+		case MGN_MCS5:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex);
-+			break;
-+		case MGN_MCS6:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex);
-+			break;
-+		case MGN_MCS7:
-+			phy_set_bb_reg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex);
-+			break;
-+
-+		default:
-+			RTW_INFO("Invalid Rate!!\n");
-+			break;
-+		}
-+	}
-+}
-+
-+void
-+PHY_SetTxPowerLevel8703B(
-+		PADAPTER		Adapter,
-+		u8				Channel
-+)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+	u8				cur_antenna;
-+	enum rf_path		RFPath = RF_PATH_A;
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	rtw_hal_get_odm_var(Adapter, HAL_ODM_ANTDIV_SELECT, &cur_antenna, NULL);
-+
-+	if (pHalData->AntDivCfg)  /* antenna diversity Enable */
-+		RFPath = ((cur_antenna == MAIN_ANT) ? RF_PATH_A : RF_PATH_B);
-+	else   /* antenna diversity disable */
-+#endif
-+		RFPath = pHalData->ant_path;
-+
-+
-+
-+	phy_set_tx_power_level_by_path(Adapter, Channel, RFPath);
-+
-+}
-+
-+/* <20130321, VincentLan> A workaround to eliminate the 2440MHz & 2480MHz spur of 8703B. (Asked by Rock.) */
-+void
-+phy_SpurCalibration_8703B(
-+		PADAPTER					pAdapter,
-+		u8						ToChannel,
-+		u8						threshold
-+)
-+{
-+	u32 		freq[6] = {0xFCCD, 0xFC4D, 0xFFCD, 0xFF4D, 0xFCCD, 0xFF9A}; /* {chnl 5, 6, 7, 8, 13, 14} */
-+	u8		idx = 0;
-+	u8		b_doNotch = FALSE;
-+	u8		initial_gain;
-+	BOOLEAN		bHW_Ctrl = FALSE, bSW_Ctrl = FALSE, bHW_Ctrl_S1 = FALSE, bSW_Ctrl_S1 = FALSE;
-+	u32		reg948;
-+
-+	/* add for notch */
-+	u32				wlan_channel, CurrentChannel, Is40MHz;
-+	HAL_DATA_TYPE		*pHalData	= GET_HAL_DATA(pAdapter);
-+	/* PMGNT_INFO			pMgntInfo = &(pAdapter->MgntInfo); */
-+	struct dm_struct		*pDM_Odm = &(pHalData->odmpriv);
-+	/* struct dm_struct			*pDM_Odm = &pHalData->DM_OutSrc; */
-+
-+	/* check threshold */
-+	if (threshold <= 0x0)
-+		threshold = 0x16;
-+
-+	RTW_INFO("===>phy_SpurCalibration_8703B: Channel = %d\n", ToChannel);
-+
-+	if (ToChannel == 5)
-+		idx = 0;
-+	else if (ToChannel == 6)
-+		idx = 1;
-+	else if (ToChannel == 7)
-+		idx = 2;
-+	else if (ToChannel == 8)
-+		idx = 3;
-+	else if (ToChannel == 13)
-+		idx = 4;
-+	else if (ToChannel == 14)
-+		idx = 5;
-+	else
-+		idx = 10;
-+
-+	reg948 = phy_query_bb_reg(pAdapter, rS0S1_PathSwitch, bMaskDWord);
-+	if ((reg948 & BIT6) == 0x0)
-+		bSW_Ctrl = TRUE;
-+	else
-+		bHW_Ctrl = TRUE;
-+
-+	if (bHW_Ctrl)
-+		bHW_Ctrl_S1 = (phy_query_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT4 | BIT3) == 0x1) ? TRUE : FALSE;
-+	else if (bSW_Ctrl)
-+		bSW_Ctrl_S1 = ((reg948 & BIT9) == 0x0) ? TRUE : FALSE;
-+
-+	/* If wlan at S1 (both HW control & SW control) and current channel=5,6,7,8,13,14 */
-+	if ((bHW_Ctrl_S1 || bSW_Ctrl_S1) && (idx <= 5)) {
-+		initial_gain = (u8)(odm_get_bb_reg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0) & 0x7f);
-+		odm_write_dig(pDM_Odm, 0x30);
-+		phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccf000c0);		/* disable 3-wire */
-+
-+		phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]);				/* Setup PSD */
-+		phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, 0x400000 | freq[idx]); /* Start PSD	 */
-+
-+		rtw_msleep_os(30);
-+
-+		if (phy_query_bb_reg(pAdapter, rFPGA0_PSDReport, bMaskDWord) >= threshold)
-+			b_doNotch = TRUE;
-+
-+		phy_set_bb_reg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); /* turn off PSD */
-+		phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccc000c0);	/* enable 3-wire */
-+		odm_write_dig(pDM_Odm, initial_gain);
-+	}
-+
-+	/* --- Notch Filter --- Asked by Rock	 */
-+	if (b_doNotch) {
-+		CurrentChannel = odm_get_rf_reg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
-+		wlan_channel   = CurrentChannel & 0x0f;						    /* Get center frequency */
-+
-+		switch (wlan_channel) {							    				/* Set notch filter				 */
-+		case 5:
-+		case 13:
-+			odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0xB);
-+			odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1);                    /* enable notch filter */
-+			odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x06000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1);                   /* enable CSI mask */
-+			break;
-+		case 6:
-+			odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x4);
-+			odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1);                   /* enable notch filter */
-+			odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000600);
-+			odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1);                   /* enable CSI mask */
-+			break;
-+		case 7:
-+			odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x3);
-+			odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1);                   /* enable notch filter */
-+			odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x06000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1);                  /* enable CSI mask */
-+			break;
-+		case 8:
-+			odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0xA);
-+			odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1);                   /* enable notch filter */
-+			odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000380);
-+			odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1);                  /* enable CSI mask */
-+			break;
-+		case 14:
-+			odm_set_bb_reg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x5);
-+			odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x1);                   /* enable notch filter */
-+			odm_set_bb_reg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000);
-+			odm_set_bb_reg(pDM_Odm, 0xD4C, bMaskDWord, 0x00180000);
-+			odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x1);                   /* enable CSI mask */
-+			break;
-+		default:
-+			odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x0);				/* disable notch filter */
-+			odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x0);                  /* disable CSI mask	function */
-+			break;
-+		} /* switch(wlan_channel)	 */
-+		return;
-+	}
-+
-+	odm_set_bb_reg(pDM_Odm, 0xC40, BIT9, 0x0);                     /* disable notch filter */
-+	odm_set_bb_reg(pDM_Odm, 0xD2C, BIT28, 0x0);                    /* disable CSI mask */
-+
-+}
-+
-+void
-+phy_SetRegBW_8703B(
-+		PADAPTER		Adapter,
-+	enum channel_width	CurrentBW
-+)
-+{
-+	u16	RegRfMod_BW, u2tmp = 0;
-+	RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8703B);
-+
-+	switch (CurrentBW) {
-+	case CHANNEL_WIDTH_20:
-+		rtw_write16(Adapter, REG_TRXPTCL_CTL_8703B, (RegRfMod_BW & 0xFE7F)); /* BIT 7 = 0, BIT 8 = 0 */
-+		break;
-+
-+	case CHANNEL_WIDTH_40:
-+		u2tmp = RegRfMod_BW | BIT7;
-+		rtw_write16(Adapter, REG_TRXPTCL_CTL_8703B, (u2tmp & 0xFEFF)); /* BIT 7 = 1, BIT 8 = 0 */
-+		break;
-+
-+	case CHANNEL_WIDTH_80:
-+		u2tmp = RegRfMod_BW | BIT8;
-+		rtw_write16(Adapter, REG_TRXPTCL_CTL_8703B, (u2tmp & 0xFF7F)); /* BIT 7 = 0, BIT 8 = 1 */
-+		break;
-+
-+	default:
-+		RTW_INFO("phy_PostSetBWMode8703B():	unknown Bandwidth: %#X\n", CurrentBW);
-+		break;
-+	}
-+}
-+
-+u8
-+phy_GetSecondaryChnl_8703B(
-+		PADAPTER	Adapter
-+)
-+{
-+	u8	SCSettingOf40 = 0, SCSettingOf20 = 0;
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+
-+	if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
-+		if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
-+			SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
-+		else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
-+			SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
-+
-+
-+		if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
-+			SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
-+		else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
-+			SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
-+		else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
-+			SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
-+		else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
-+			SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
-+
-+	} else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
-+
-+		if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
-+			SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
-+		else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
-+			SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
-+
-+	}
-+
-+	return (SCSettingOf40 << 4) | SCSettingOf20;
-+}
-+
-+void
-+phy_PostSetBwMode8703B(
-+		PADAPTER	Adapter
-+)
-+{
-+	u8			SubChnlNum = 0;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	u8			u1TmpVal = 0;
-+
-+	/* 3 Set Reg668 Reg440 BW */
-+	phy_SetRegBW_8703B(Adapter, pHalData->current_channel_bw);
-+
-+	/* 3 Set Reg483 */
-+	SubChnlNum = phy_GetSecondaryChnl_8703B(Adapter);
-+	rtw_write8(Adapter, REG_DATA_SC_8703B, SubChnlNum);
-+
-+	/* 3 */
-+	/* 3 */ /* <2>Set PHY related register */
-+	/* 3 */
-+	switch (pHalData->current_channel_bw) {
-+	/* 20 MHz channel*/
-+	case CHANNEL_WIDTH_20:
-+		phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
-+
-+		phy_set_bb_reg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
-+
-+		/*			phy_set_bb_reg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); */
-+
-+		phy_set_bb_reg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31 | BIT30), 0x0);
-+
-+		/* 8703B new Add */
-+		phy_set_bb_reg(Adapter, pHalData->RegForRecover[2].offset, bMaskDWord, pHalData->RegForRecover[2].value);
-+		phy_set_bb_reg(Adapter, pHalData->RegForRecover[3].offset, bMaskDWord, pHalData->RegForRecover[3].value);
-+		phy_set_rf_reg(Adapter, RF_PATH_A, pHalData->RegForRecover[4].offset, bRFRegOffsetMask, pHalData->RegForRecover[4].value);
-+
-+		break;
-+
-+
-+	/* 40 MHz channel*/
-+	case CHANNEL_WIDTH_40:
-+		phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
-+
-+		phy_set_bb_reg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
-+
-+		/* 8703B new Add*/
-+		phy_set_bb_reg(Adapter, rBBrx_DFIR, bMaskDWord, 0x40100000);
-+		phy_set_bb_reg(Adapter, rOFDM0_XATxAFE, bMaskDWord, 0x51F60000);
-+		phy_set_rf_reg(Adapter, RF_PATH_A, 0x1E, bRFRegOffsetMask, 0x00C4C);
-+
-+		/* Set Control channel to upper or lower. These settings are required only for 40MHz*/
-+		phy_set_bb_reg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1));
-+
-+		phy_set_bb_reg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
-+
-+		phy_set_bb_reg(Adapter, 0x818, (BIT26 | BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
-+
-+		u1TmpVal = rtw_read8(Adapter, REG_DATA_SC_8703B);
-+		u1TmpVal &= 0xF0;
-+		u1TmpVal |= ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
-+		rtw_write8(Adapter, REG_DATA_SC_8703B, u1TmpVal);
-+
-+		break;
-+
-+
-+
-+	default:
-+		break;
-+
-+	}
-+
-+	/* 3<3>Set RF related register */
-+	PHY_RF6052SetBandwidth8703B(Adapter, pHalData->current_channel_bw);
-+}
-+
-+void
-+phy_SwChnl8703B(
-+		PADAPTER					pAdapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
-+	u8			channelToSW = pHalData->current_channel;
-+	u8		i = 0;
-+
-+	if (pHalData->rf_chip == RF_PSEUDO_11N) {
-+		RTW_INFO("phy_SwChnl8703B: return for PSEUDO\n");
-+		return;
-+	}
-+
-+	pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW);
-+	phy_set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
-+	phy_set_rf_reg(pAdapter, RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
-+
-+	/* BB Setting for some channels (requested by BB Neil) */
-+	switch (channelToSW) {
-+	case 14:
-+		/*Channel 14 in CCK, need to set 0xA26~0xA29 to 0 */
-+		phy_set_bb_reg(pAdapter, rCCK0_TxFilter2, bMaskHWord, 0);
-+		phy_set_bb_reg(pAdapter, rCCK0_DebugPort, bMaskLWord, 0);
-+		break;
-+	default:
-+		/*Normal setting for 8703B, just recover to the default setting. */
-+		/*This hardcore values refer to the parameter which BB team gave. */
-+		for (i = 0 ; i < 2 ; ++i)
-+			phy_set_bb_reg(pAdapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
-+	}
-+
-+	phy_SpurCalibration_8703B(pAdapter, channelToSW, 0x16);
-+
-+	RTW_INFO("===>phy_SwChnl8703B: Channel = %d\n", channelToSW);
-+}
-+
-+void
-+phy_SwChnlAndSetBwMode8703B(
-+	PADAPTER		Adapter
-+)
-+{
-+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
-+
-+	if (Adapter->bNotifyChannelChange) {
-+		RTW_INFO("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n",
-+			 __FUNCTION__,
-+			 pHalData->bSwChnl,
-+			 pHalData->current_channel,
-+			 pHalData->bSetChnlBW,
-+			 pHalData->current_channel_bw);
-+	}
-+
-+	if (RTW_CANNOT_RUN(Adapter))
-+		return;
-+
-+	if (pHalData->bSwChnl) {
-+		phy_SwChnl8703B(Adapter);
-+		pHalData->bSwChnl = _FALSE;
-+	}
-+
-+	if (pHalData->bSetChnlBW) {
-+		phy_PostSetBwMode8703B(Adapter);
-+		pHalData->bSetChnlBW = _FALSE;
-+	}
-+
-+	if (pHalData->bNeedIQK == _TRUE) {
-+		if (pHalData->neediqk_24g == _TRUE) {
-+
-+			halrf_iqk_trigger(&pHalData->odmpriv, _FALSE);
-+			pHalData->bIQKInitialized = _TRUE;
-+			pHalData->neediqk_24g = _FALSE;
-+		}
-+		pHalData->bNeedIQK = _FALSE;
-+	}
-+
-+	rtw_hal_set_tx_power_level(Adapter, pHalData->current_channel);
-+}
-+
-+void
-+PHY_HandleSwChnlAndSetBW8703B(
-+		PADAPTER			Adapter,
-+		BOOLEAN				bSwitchChannel,
-+		BOOLEAN				bSetBandWidth,
-+		u8					ChannelNum,
-+		enum channel_width	ChnlWidth,
-+		EXTCHNL_OFFSET	ExtChnlOffsetOf40MHz,
-+		EXTCHNL_OFFSET	ExtChnlOffsetOf80MHz,
-+		u8					CenterFrequencyIndex1
-+)
-+{
-+	/* static BOOLEAN		bInitialzed = _FALSE; */
-+	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(Adapter);
-+	u8					tmpChannel = pHalData->current_channel;
-+	enum channel_width	tmpBW = pHalData->current_channel_bw;
-+	u8					tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC;
-+	u8					tmpnCur80MhzPrimeSC = pHalData->nCur80MhzPrimeSC;
-+	u8					tmpCenterFrequencyIndex1 = pHalData->CurrentCenterFrequencyIndex1;
-+	struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
-+
-+	/* RTW_INFO("=> PHY_HandleSwChnlAndSetBW8812: bSwitchChannel %d, bSetBandWidth %d\n",bSwitchChannel,bSetBandWidth); */
-+
-+	/* check is swchnl or setbw */
-+	if (!bSwitchChannel && !bSetBandWidth) {
-+		RTW_INFO("PHY_HandleSwChnlAndSetBW8812:  not switch channel and not set bandwidth\n");
-+		return;
-+	}
-+
-+	/* skip change for channel or bandwidth is the same */
-+	if (bSwitchChannel) {
-+		/* if(pHalData->current_channel != ChannelNum) */
-+		{
-+			if (HAL_IsLegalChannel(Adapter, ChannelNum))
-+				pHalData->bSwChnl = _TRUE;
-+		}
-+	}
-+
-+	if (bSetBandWidth) {
-+#if 0
-+		if (bInitialzed == _FALSE) {
-+			bInitialzed = _TRUE;
-+			pHalData->bSetChnlBW = _TRUE;
-+		} else if ((pHalData->current_channel_bw != ChnlWidth) || (pHalData->nCur40MhzPrimeSC != ExtChnlOffsetOf40MHz) || (pHalData->CurrentCenterFrequencyIndex1 != CenterFrequencyIndex1))
-+			pHalData->bSetChnlBW = _TRUE;
-+#else
-+		pHalData->bSetChnlBW = _TRUE;
-+#endif
-+	}
-+
-+	if (!pHalData->bSetChnlBW && !pHalData->bSwChnl) {
-+		/* RTW_INFO("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n",pHalData->bSwChnl,pHalData->bSetChnlBW); */
-+		return;
-+	}
-+
-+
-+	if (pHalData->bSwChnl) {
-+		pHalData->current_channel = ChannelNum;
-+		pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
-+	}
-+
-+
-+	if (pHalData->bSetChnlBW) {
-+		pHalData->current_channel_bw = ChnlWidth;
-+#if 0
-+		if (ExtChnlOffsetOf40MHz == EXTCHNL_OFFSET_LOWER)
-+			pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
-+		else if (ExtChnlOffsetOf40MHz == EXTCHNL_OFFSET_UPPER)
-+			pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
-+		else
-+			pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+
-+		if (ExtChnlOffsetOf80MHz == EXTCHNL_OFFSET_LOWER)
-+			pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
-+		else if (ExtChnlOffsetOf80MHz == EXTCHNL_OFFSET_UPPER)
-+			pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
-+		else
-+			pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+#else
-+		pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;
-+		pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz;
-+#endif
-+
-+		pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;
-+	}
-+
-+	/* Switch workitem or set timer to do switch channel or setbandwidth operation */
-+	if (!RTW_CANNOT_RUN(Adapter))
-+		phy_SwChnlAndSetBwMode8703B(Adapter);
-+	else {
-+		if (pHalData->bSwChnl) {
-+			pHalData->current_channel = tmpChannel;
-+			pHalData->CurrentCenterFrequencyIndex1 = tmpChannel;
-+		}
-+		if (pHalData->bSetChnlBW) {
-+			pHalData->current_channel_bw = tmpBW;
-+			pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC;
-+			pHalData->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC;
-+			pHalData->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1;
-+		}
-+	}
-+
-+	/* RTW_INFO("Channel %d ChannelBW %d ",pHalData->current_channel, pHalData->current_channel_bw); */
-+	/* RTW_INFO("40MhzPrimeSC %d 80MhzPrimeSC %d ",pHalData->nCur40MhzPrimeSC, pHalData->nCur80MhzPrimeSC); */
-+	/* RTW_INFO("CenterFrequencyIndex1 %d\n",pHalData->CurrentCenterFrequencyIndex1); */
-+
-+	/* RTW_INFO("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n",pHalData->bSwChnl,pHalData->bSetChnlBW); */
-+
-+}
-+
-+void
-+PHY_SetSwChnlBWMode8703B(
-+		PADAPTER			Adapter,
-+		u8					channel,
-+		enum channel_width	Bandwidth,
-+		u8					Offset40,
-+		u8					Offset80
-+)
-+{
-+	/* RTW_INFO("%s()===>\n",__FUNCTION__); */
-+
-+	PHY_HandleSwChnlAndSetBW8703B(Adapter, _TRUE, _TRUE, channel, Bandwidth, Offset40, Offset80, channel);
-+
-+	/* RTW_INFO("<==%s()\n",__FUNCTION__); */
-+}
-\ No newline at end of file
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_rf6052.c b/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_rf6052.c
-new file mode 100644
-index 000000000000..198589f52891
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_rf6052.c
-@@ -0,0 +1,232 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/******************************************************************************
-+ *
-+ *
-+ * Module:	rtl8192c_rf6052.c	( Source C File)
-+ *
-+ * Note:	Provide RF 6052 series relative API.
-+ *
-+ * Function:
-+ *
-+ * Export:
-+ *
-+ * Abbrev:
-+ *
-+ * History:
-+ * Data			Who		Remark
-+ *
-+ * 09/25/2008	MHC		Create initial version.
-+ * 11/05/2008	MHC		Add API for tw power setting.
-+ *
-+ *
-+******************************************************************************/
-+
-+#include <rtl8703b_hal.h>
-+
-+/*---------------------------Define Local Constant---------------------------*/
-+/*---------------------------Define Local Constant---------------------------*/
-+
-+
-+/*------------------------Define global variable-----------------------------*/
-+/*------------------------Define global variable-----------------------------*/
-+
-+
-+/*------------------------Define local variable------------------------------*/
-+#ifdef CONFIG_RF_SHADOW_RW
-+/* 2008/11/20 MH For Debug only, RF
-+ * static	RF_SHADOW_T	RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0}; */
-+static	RF_SHADOW_T	RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
-+#endif
-+/*------------------------Define local variable------------------------------*/
-+
-+/*-----------------------------------------------------------------------------
-+ * Function:    PHY_RF6052SetBandwidth()
-+ *
-+ * Overview:    This function is called by SetBWModeCallback8190Pci() only
-+ *
-+ * Input:       PADAPTER				Adapter
-+ *			WIRELESS_BANDWIDTH_E	Bandwidth	//20M or 40M
-+ *
-+ * Output:      NONE
-+ *
-+ * Return:      NONE
-+ *
-+ * Note:		For RF type 0222D
-+ *---------------------------------------------------------------------------*/
-+void
-+PHY_RF6052SetBandwidth8703B(
-+		PADAPTER				Adapter,
-+		enum channel_width		Bandwidth)	/* 20M or 40M */
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+
-+	switch (Bandwidth) {
-+	case CHANNEL_WIDTH_20:
-+		pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11);
-+		phy_set_rf_reg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
-+		phy_set_rf_reg(Adapter, RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
-+		break;
-+
-+	case CHANNEL_WIDTH_40:
-+		pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10);
-+		phy_set_rf_reg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
-+		phy_set_rf_reg(Adapter, RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+}
-+
-+static int
-+phy_RF6052_Config_ParaFile(
-+		PADAPTER		Adapter
-+)
-+{
-+	u32					u4RegValue = 0;
-+	enum rf_path			eRFPath;
-+	BB_REGISTER_DEFINITION_T	*pPhyReg;
-+
-+	int					rtStatus = _SUCCESS;
-+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter);
-+
-+	/* 3 */ /* ----------------------------------------------------------------- */
-+	/* 3 */ /* <2> Initialize RF */
-+	/* 3 */ /* ----------------------------------------------------------------- */
-+	for (eRFPath = RF_PATH_A; eRFPath < hal_spec->rf_reg_path_num; eRFPath++) {
-+
-+		pPhyReg = &pHalData->PHYRegDef[eRFPath];
-+
-+		/*----Store original RFENV control type----*/
-+		switch (eRFPath) {
-+		case RF_PATH_A:
-+		case RF_PATH_C:
-+			u4RegValue = phy_query_bb_reg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
-+			break;
-+		case RF_PATH_B:
-+		case RF_PATH_D:
-+			u4RegValue = phy_query_bb_reg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16);
-+			break;
-+		default:
-+			RTW_ERR("Invalid rf_path:%d\n", eRFPath);
-+			break;
-+		}
-+
-+		/*----Set RF_ENV enable----*/
-+		phy_set_bb_reg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1);
-+		rtw_udelay_os(1);/* PlatformStallExecution(1); */
-+
-+		/*----Set RF_ENV output high----*/
-+		phy_set_bb_reg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
-+		rtw_udelay_os(1);/* PlatformStallExecution(1); */
-+
-+		/* Set bit number of Address and Data for RF register */
-+		phy_set_bb_reg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);	/* Set 1 to 4 bits for 8255 */
-+		rtw_udelay_os(1);/* PlatformStallExecution(1); */
-+
-+		phy_set_bb_reg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);	/* Set 0 to 12  bits for 8255 */
-+		rtw_udelay_os(1);/* PlatformStallExecution(1); */
-+
-+		/*----Initialize RF fom connfiguration file----*/
-+		switch (eRFPath) {
-+		case RF_PATH_A:
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+			if (PHY_ConfigRFWithParaFile(Adapter, PHY_FILE_RADIO_A, eRFPath) == _FAIL)
-+#endif
-+			{
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+				if (odm_config_rf_with_header_file(&pHalData->odmpriv, CONFIG_RF_RADIO, eRFPath) == HAL_STATUS_FAILURE)
-+					rtStatus = _FAIL;
-+#endif
-+			}
-+			break;
-+		case RF_PATH_B:
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+			if (PHY_ConfigRFWithParaFile(Adapter, PHY_FILE_RADIO_B, eRFPath) == _FAIL)
-+#endif
-+			{
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+				if (odm_config_rf_with_header_file(&pHalData->odmpriv, CONFIG_RF_RADIO, eRFPath) == HAL_STATUS_FAILURE)
-+					rtStatus = _FAIL;
-+#endif
-+			}
-+			break;
-+		case RF_PATH_C:
-+			break;
-+		case RF_PATH_D:
-+			break;
-+		default:
-+			RTW_ERR("Invalid rf_path:%d\n", eRFPath);
-+			break;
-+		}
-+
-+		/*----Restore RFENV control type----*/;
-+		switch (eRFPath) {
-+		case RF_PATH_A:
-+		case RF_PATH_C:
-+			phy_set_bb_reg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
-+			break;
-+		case RF_PATH_B:
-+		case RF_PATH_D:
-+			phy_set_bb_reg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16, u4RegValue);
-+			break;
-+		default:
-+			RTW_ERR("Invalid rf_path:%d\n", eRFPath);
-+			break;
-+		}
-+
-+		if (rtStatus != _SUCCESS) {
-+			goto phy_RF6052_Config_ParaFile_Fail;
-+		}
-+
-+	}
-+
-+	/* 3 ----------------------------------------------------------------- */
-+	/* 3 Configuration of Tx Power Tracking */
-+	/* 3 ----------------------------------------------------------------- */
-+
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+	if (PHY_ConfigRFWithTxPwrTrackParaFile(Adapter, PHY_FILE_TXPWR_TRACK) == _FAIL)
-+#endif
-+	{
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+		odm_config_rf_with_tx_pwr_track_header_file(&pHalData->odmpriv);
-+#endif
-+	}
-+
-+	return rtStatus;
-+
-+phy_RF6052_Config_ParaFile_Fail:
-+	return rtStatus;
-+}
-+
-+
-+int
-+PHY_RF6052_Config8703B(
-+		PADAPTER		Adapter)
-+{
-+	int					rtStatus = _SUCCESS;
-+
-+	/*  */
-+	/* Config BB and RF */
-+	/*  */
-+	rtStatus = phy_RF6052_Config_ParaFile(Adapter);
-+	return rtStatus;
-+}
-+
-+/* End of HalRf6052.c */
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_rxdesc.c b/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_rxdesc.c
-new file mode 100644
-index 000000000000..a8c4c58820bf
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_rxdesc.c
-@@ -0,0 +1,63 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTL8703B_REDESC_C_
-+
-+#include <rtl8703b_hal.h>
-+
-+void rtl8703b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc)
-+{
-+	struct rx_pkt_attrib *pattrib;
-+
-+
-+	pattrib = &precvframe->u.hdr.attrib;
-+	_rtw_memset(pattrib, 0, sizeof(struct rx_pkt_attrib));
-+
-+	pattrib->pkt_len = (u16)GET_RX_STATUS_DESC_PKT_LEN_8703B(pdesc);
-+	pattrib->pkt_rpt_type = GET_RX_STATUS_DESC_RPT_SEL_8703B(pdesc) ? C2H_PACKET : NORMAL_RX;
-+
-+	if (pattrib->pkt_rpt_type == NORMAL_RX) {
-+		/* Offset 0 */
-+		pattrib->crc_err = (u8)GET_RX_STATUS_DESC_CRC32_8703B(pdesc);
-+		pattrib->icv_err = (u8)GET_RX_STATUS_DESC_ICV_8703B(pdesc);
-+		pattrib->drvinfo_sz = (u8)GET_RX_STATUS_DESC_DRVINFO_SIZE_8703B(pdesc) << 3;
-+		pattrib->encrypt = (u8)GET_RX_STATUS_DESC_SECURITY_8703B(pdesc);
-+		pattrib->qos = (u8)GET_RX_STATUS_DESC_QOS_8703B(pdesc);
-+		pattrib->shift_sz = (u8)GET_RX_STATUS_DESC_SHIFT_8703B(pdesc);
-+		pattrib->physt = (u8)GET_RX_STATUS_DESC_PHY_STATUS_8703B(pdesc);
-+		pattrib->bdecrypted = (u8)GET_RX_STATUS_DESC_SWDEC_8703B(pdesc) ? 0 : 1;
-+
-+		/* Offset 4 */
-+		pattrib->priority = (u8)GET_RX_STATUS_DESC_TID_8703B(pdesc);
-+		pattrib->amsdu = (u8)GET_RX_STATUS_DESC_AMSDU_8703B(pdesc);
-+		pattrib->mdata = (u8)GET_RX_STATUS_DESC_MORE_DATA_8703B(pdesc);
-+		pattrib->mfrag = (u8)GET_RX_STATUS_DESC_MORE_FRAG_8703B(pdesc);
-+
-+		/* Offset 8 */
-+		pattrib->seq_num = (u16)GET_RX_STATUS_DESC_SEQ_8703B(pdesc);
-+		pattrib->frag_num = (u8)GET_RX_STATUS_DESC_FRAG_8703B(pdesc);
-+
-+		/* Offset 12 */
-+		pattrib->data_rate = (u8)GET_RX_STATUS_DESC_RX_RATE_8703B(pdesc);
-+
-+		/* Offset 16 */
-+		pattrib->sgi = (u8)GET_RX_STATUS_DESC_SPLCP_8703B(pdesc);
-+		pattrib->ldpc = (u8)GET_RX_STATUS_DESC_LDPC_8703B(pdesc);
-+		pattrib->stbc = (u8)GET_RX_STATUS_DESC_STBC_8703B(pdesc);
-+		pattrib->bw = (u8)GET_RX_STATUS_DESC_BW_8703B(pdesc);
-+
-+		/* Offset 20 */
-+		/* pattrib->tsfl=(u8)GET_RX_STATUS_DESC_TSFL_8703B(pdesc); */
-+	}
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_sreset.c b/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_sreset.c
-new file mode 100644
-index 000000000000..4a7ab4c83b15
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/rtl8703b_sreset.c
-@@ -0,0 +1,100 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTL8703B_SRESET_C_
-+
-+#include <rtl8703b_hal.h>
-+
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+void rtl8703b_sreset_xmit_status_check(_adapter *padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
-+
-+	systime current_time;
-+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
-+	unsigned int diff_time;
-+	u32 txdma_status;
-+
-+	txdma_status = rtw_read32(padapter, REG_TXDMA_STATUS);
-+	if (txdma_status != 0x00 && txdma_status != 0xeaeaeaea) {
-+		RTW_INFO("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
-+		rtw_hal_sreset_reset(padapter);
-+	}
-+
-+#ifdef CONFIG_USB_HCI
-+	/* total xmit irp = 4 */
-+	/* RTW_INFO("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt); */
-+	/* if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1) */
-+	current_time = rtw_get_current_time();
-+
-+	if (0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
-+
-+		diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time);
-+
-+		if (diff_time > 2000) {
-+			if (psrtpriv->last_tx_complete_time == 0)
-+				psrtpriv->last_tx_complete_time = current_time;
-+			else {
-+				diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);
-+				if (diff_time > 4000) {
-+
-+					/* padapter->Wifi_Error_Status = WIFI_TX_HANG; */
-+					RTW_INFO("%s tx hang %s\n", __FUNCTION__,
-+						(rtw_odm_adaptivity_needed(padapter)) ? "ODM_BB_ADAPTIVITY" : "");
-+
-+					if (!rtw_odm_adaptivity_needed(padapter))
-+						rtw_hal_sreset_reset(padapter);
-+				}
-+			}
-+		}
-+	}
-+#endif /*  #ifdef CONFIG_USB_HCI */
-+
-+	if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {
-+		psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
-+		rtw_hal_sreset_reset(padapter);
-+		return;
-+	}
-+}
-+
-+void rtl8703b_sreset_linked_status_check(_adapter *padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
-+#if 0
-+	u32 regc50, regc58, reg824, reg800;
-+	regc50 = rtw_read32(padapter, 0xc50);
-+	regc58 = rtw_read32(padapter, 0xc58);
-+	reg824 = rtw_read32(padapter, 0x824);
-+	reg800 = rtw_read32(padapter, 0x800);
-+	if (((regc50 & 0xFFFFFF00) != 0x69543400) ||
-+	    ((regc58 & 0xFFFFFF00) != 0x69543400) ||
-+	    (((reg824 & 0xFFFFFF00) != 0x00390000) && (((reg824 & 0xFFFFFF00) != 0x80390000))) ||
-+	    (((reg800 & 0xFFFFFF00) != 0x03040000) && ((reg800 & 0xFFFFFF00) != 0x83040000))) {
-+		RTW_INFO("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__,
-+			 regc50, regc58, reg824, reg800);
-+		rtw_hal_sreset_reset(padapter);
-+	}
-+#endif
-+
-+	if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
-+		psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
-+		rtw_hal_sreset_reset(padapter);
-+		return;
-+	}
-+}
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/rtl8703bs_led.c b/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/rtl8703bs_led.c
-new file mode 100644
-index 000000000000..f6047ef79952
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/rtl8703bs_led.c
-@@ -0,0 +1,123 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTL8703BS_LED_C_
-+
-+#include "rtl8703b_hal.h"
-+#ifdef CONFIG_RTW_SW_LED
-+
-+/* ********************************************************************************
-+ * LED object.
-+ * ******************************************************************************** */
-+
-+
-+/* ********************************************************************************
-+ *	Prototype of protected function.
-+ * ******************************************************************************** */
-+
-+/* ********************************************************************************
-+ * LED_819xUsb routines.
-+ * ******************************************************************************** */
-+
-+/*
-+ *	Description:
-+ *		Turn on LED according to LedPin specified.
-+ *   */
-+void
-+SwLedOn_8703BS(
-+	_adapter			*padapter,
-+	PLED_SDIO		pLed
-+)
-+{
-+	u8	LedCfg;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	if (RTW_CANNOT_RUN(padapter))
-+		return;
-+
-+	pLed->bLedOn = _TRUE;
-+
-+}
-+
-+
-+/*
-+ *	Description:
-+ *		Turn off LED according to LedPin specified.
-+ *   */
-+void
-+SwLedOff_8703BS(
-+	_adapter			*padapter,
-+	PLED_SDIO		pLed
-+)
-+{
-+	u8	LedCfg;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	if (RTW_CANNOT_RUN(padapter))
-+		goto exit;
-+
-+exit:
-+	pLed->bLedOn = _FALSE;
-+
-+}
-+
-+/* ********************************************************************************
-+ * Interface to manipulate LED objects.
-+ * ******************************************************************************** */
-+
-+/* ********************************************************************************
-+ * Default LED behavior.
-+ * ******************************************************************************** */
-+
-+/*
-+ *	Description:
-+ *		Initialize all LED_871x objects.
-+ *   */
-+void
-+rtl8703bs_InitSwLeds(
-+	_adapter	*padapter
-+)
-+{
-+#if 0
-+	struct led_priv *pledpriv = adapter_to_led(padapter);
-+
-+	pledpriv->LedControlHandler = LedControlSDIO;
-+
-+	pledpriv->SwLedOn = SwLedOn_8703BS;
-+	pledpriv->SwLedOff = SwLedOff_8703BS;
-+
-+	InitLed871x(padapter, &(pledpriv->SwLed0), LED_PIN_LED0);
-+
-+	InitLed871x(padapter, &(pledpriv->SwLed1), LED_PIN_LED1);
-+#endif
-+}
-+
-+
-+/*
-+ *	Description:
-+ *		DeInitialize all LED_819xUsb objects.
-+ *   */
-+void
-+rtl8703bs_DeInitSwLeds(
-+	_adapter	*padapter
-+)
-+{
-+#if 0
-+	struct led_priv	*ledpriv = adapter_to_led(padapter);
-+
-+	DeInitLed871x(&(ledpriv->SwLed0));
-+	DeInitLed871x(&(ledpriv->SwLed1));
-+#endif
-+}
-+#endif
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/rtl8703bs_recv.c b/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/rtl8703bs_recv.c
-new file mode 100644
-index 000000000000..28f715679844
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/rtl8703bs_recv.c
-@@ -0,0 +1,476 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTL8703BS_RECV_C_
-+
-+#include <rtl8703b_hal.h>
-+
-+#ifdef CONFIG_SDIO_RX_COPY
-+s32 rtl8703bs_recv_hdl(_adapter *padapter)
-+{
-+	PHAL_DATA_TYPE		pHalData;
-+	struct recv_priv		*precvpriv;
-+	struct recv_buf	*precvbuf;
-+	union recv_frame		*precvframe;
-+	struct recv_frame_hdr	*phdr;
-+	struct rx_pkt_attrib	*pattrib;
-+	u8	*ptr;
-+	u32	pkt_len, pkt_offset;
-+	u8	rx_report_sz = 0;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	precvpriv = &padapter->recvpriv;
-+
-+	do {
-+		precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue);
-+		if (NULL == precvbuf)
-+			break;
-+
-+		ptr = precvbuf->pdata;
-+
-+		while (ptr < precvbuf->ptail) {
-+			precvframe = rtw_alloc_recvframe(&precvpriv->free_recv_queue);
-+			if (precvframe == NULL) {
-+				RTW_INFO("%s: no enough recv frame!\n", __FUNCTION__);
-+				rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
-+
-+				return RTW_RFRAME_UNAVAIL;   
-+			}
-+
-+			/* rx desc parsing */
-+			rtl8703b_query_rx_desc_status(precvframe, ptr);
-+
-+			pattrib = &precvframe->u.hdr.attrib;
-+
-+			/* fix Hardware RX data error, drop whole recv_buffer */
-+			if (!rtw_hal_rcr_check(padapter, RCR_ACRC32) && pattrib->crc_err) {
-+#if !(MP_DRIVER == 1)
-+				RTW_INFO("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__);
-+#endif
-+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
-+				break;
-+			}
-+
-+			rx_report_sz = RXDESC_SIZE + pattrib->drvinfo_sz;
-+			pkt_offset = rx_report_sz + pattrib->shift_sz + pattrib->pkt_len;
-+
-+			if ((ptr + pkt_offset) > precvbuf->ptail) {
-+				RTW_INFO("%s()-%d: : next pkt len(%p,%d) exceed ptail(%p)!\n", __FUNCTION__, __LINE__, ptr, pkt_offset, precvbuf->ptail);
-+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
-+				break;
-+			}
-+
-+			if ((pattrib->crc_err) || (pattrib->icv_err)) {
-+#ifdef CONFIG_MP_INCLUDED
-+				if (padapter->registrypriv.mp_mode == 1) {
-+					if ((check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _TRUE)) { /* &&(padapter->mppriv.check_mp_pkt == 0)) */
-+						if (pattrib->crc_err == 1)
-+							padapter->mppriv.rx_crcerrpktcount++;
-+					}
-+				} else
-+#endif
-+				{
-+					RTW_INFO("%s: crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err);
-+				}
-+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
-+			} else {
-+#ifdef CONFIG_RX_PACKET_APPEND_FCS
-+				if (check_fwstate(&padapter->mlmepriv, WIFI_MONITOR_STATE) == _FALSE)
-+					if ((pattrib->pkt_rpt_type == NORMAL_RX) && rtw_hal_rcr_check(padapter, RCR_APPFCS))
-+						pattrib->pkt_len -= IEEE80211_FCS_LEN;
-+#endif
-+
-+				if (rtw_os_alloc_recvframe(padapter, precvframe,
-+					(ptr + rx_report_sz + pattrib->shift_sz), precvbuf->pskb) == _FAIL) {
-+					rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
-+					break;
-+				}
-+				recvframe_put(precvframe, pattrib->pkt_len);
-+				/* recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); */
-+
-+				/* move to drv info position */
-+				ptr += RXDESC_SIZE;
-+
-+				/* update drv info */
-+				if (rtw_hal_rcr_check(padapter, RCR_APP_BA_SSN)) {
-+					/* rtl8703s_update_bassn(padapter, pdrvinfo); */
-+					ptr += 4;
-+				}
-+
-+				if (pattrib->pkt_rpt_type == NORMAL_RX) {
-+					/* skip the rx packet with abnormal length */
-+					if (pattrib->pkt_len < 14 || pattrib->pkt_len > 8192) {
-+						RTW_INFO("skip abnormal rx packet(%d)\n", pattrib->pkt_len);
-+						rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
-+						break;
-+					}
-+
-+					pre_recv_entry(precvframe, pattrib->physt ? ptr : NULL);
-+
-+				} else {
-+#ifdef CONFIG_FW_C2H_PKT
-+					if (pattrib->pkt_rpt_type == C2H_PACKET)
-+						rtw_hal_c2h_pkt_pre_hdl(padapter, precvframe->u.hdr.rx_data, pattrib->pkt_len);
-+					else {
-+						RTW_INFO("%s: [WARNNING] RX type(%d) not be handled!\n",
-+							__FUNCTION__, pattrib->pkt_rpt_type);
-+					}
-+#endif
-+					rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
-+				}
-+			}
-+
-+			pkt_offset = _RND8(pkt_offset);
-+			precvbuf->pdata += pkt_offset;
-+			ptr = precvbuf->pdata;
-+			precvframe = NULL;
-+		}
-+
-+		rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
-+	} while (1);
-+
-+#ifdef CONFIG_RTW_NAPI
-+#ifdef CONFIG_RTW_NAPI_V2
-+	if (padapter->registrypriv.en_napi) {
-+		struct dvobj_priv *d;
-+		struct _ADAPTER *a;
-+		u8 i;
-+
-+		d = adapter_to_dvobj(padapter);
-+		for (i = 0; i < d->iface_nums; i++) {
-+			a = d->padapters[i];
-+			if (rtw_if_up(a) == _TRUE)
-+				napi_schedule(&a->napi);
-+	
-+		}
-+	}
-+#endif /* CONFIG_RTW_NAPI_V2 */
-+#endif /* CONFIG_RTW_NAPI */
-+	
-+	return _SUCCESS;
-+}
-+
-+static void rtl8703bs_recv_tasklet(void *priv)
-+{
-+	_adapter *adapter = (_adapter *)priv;
-+	s32 ret;
-+
-+	ret = rtl8703bs_recv_hdl(adapter);
-+	if (ret == RTW_RFRAME_UNAVAIL
-+		|| ret == RTW_RFRAME_PKT_UNAVAIL
-+	) {
-+		/* schedule again and hope recvframe/packet is available next time. */
-+	#ifdef PLATFORM_LINUX
-+		tasklet_schedule(&adapter->recvpriv.recv_tasklet);
-+	#endif
-+	}
-+}
-+#else
-+static void rtl8703bs_recv_tasklet(void *priv)
-+{
-+	PADAPTER				padapter;
-+	PHAL_DATA_TYPE			pHalData;
-+	struct recv_priv		*precvpriv;
-+	struct recv_buf		*precvbuf;
-+	union recv_frame		*precvframe;
-+	struct recv_frame_hdr	*phdr;
-+	struct rx_pkt_attrib	*pattrib;
-+	u8		*ptr;
-+	_pkt		*ppkt;
-+	u32		pkt_offset;
-+
-+	padapter = (PADAPTER)priv;
-+	pHalData = GET_HAL_DATA(padapter);
-+	precvpriv = &padapter->recvpriv;
-+
-+	do {
-+		precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue);
-+		if (NULL == precvbuf)
-+			break;
-+
-+		ptr = precvbuf->pdata;
-+
-+		while (ptr < precvbuf->ptail) {
-+			precvframe = rtw_alloc_recvframe(&precvpriv->free_recv_queue);
-+			if (precvframe == NULL) {
-+				rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
-+
-+				/* The case of can't allocte recvframe should be temporary, */
-+				/* schedule again and hope recvframe is available next time. */
-+#ifdef PLATFORM_LINUX
-+				tasklet_schedule(&precvpriv->recv_tasklet);
-+#endif
-+				return;
-+			}
-+
-+			phdr = &precvframe->u.hdr;
-+			pattrib = &phdr->attrib;
-+
-+			rtl8703b_query_rx_desc_status(precvframe, ptr);
-+
-+#if 0
-+			{
-+				int i, len = 64;
-+				u8 *pptr = ptr;
-+
-+				if ((*(pptr + RXDESC_SIZE + pattrib->drvinfo_sz) != 0x80) && (*(pptr + RXDESC_SIZE + pattrib->drvinfo_sz) != 0x40)) {
-+					RTW_INFO("##############RxDESC###############\n");
-+					for (i = 0; i < 32; i = i + 16)
-+						RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(pptr + i),
-+							*(pptr + i + 1), *(pptr + i + 2) , *(pptr + i + 3) , *(pptr + i + 4), *(pptr + i + 5), *(pptr + i + 6), *(pptr + i + 7), *(pptr + i + 8),
-+							*(pptr + i + 9), *(pptr + i + 10),
-+							*(pptr + i + 11), *(pptr + i + 12), *(pptr + i + 13), *(pptr + i + 14), *(pptr + i + 15));
-+
-+					if (pattrib->pkt_len < 100)
-+						len = pattrib->pkt_len;
-+					pptr = ptr + RXDESC_SIZE + pattrib->drvinfo_sz;
-+					RTW_INFO("##############Len=%d###############\n", pattrib->pkt_len);
-+					for (i = 0; i < len; i = i + 16)
-+						RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(pptr + i),
-+							*(pptr + i + 1), *(pptr + i + 2) , *(pptr + i + 3) , *(pptr + i + 4), *(pptr + i + 5), *(pptr + i + 6), *(pptr + i + 7), *(pptr + i + 8),
-+							*(pptr + i + 9), *(pptr + i + 10),
-+							*(pptr + i + 11), *(pptr + i + 12), *(pptr + i + 13), *(pptr + i + 14), *(pptr + i + 15));
-+					RTW_INFO("#############################\n");
-+				}
-+			}
-+#endif
-+
-+			/* fix Hardware RX data error, drop whole recv_buffer */
-+			if (!rtw_hal_rcr_check(padapter, RCR_ACRC32) && pattrib->crc_err) {
-+				RTW_INFO("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__);
-+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
-+				break;
-+			}
-+
-+			pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->pkt_len;
-+#if 0 /* reduce check to speed up */
-+			if ((ptr + pkt_offset) > precvbuf->ptail) {
-+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
-+				break;
-+			}
-+#endif
-+
-+			if ((pattrib->crc_err) || (pattrib->icv_err)) {
-+#ifdef CONFIG_MP_INCLUDED
-+				if (padapter->registrypriv.mp_mode == 1) {
-+					if ((check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _TRUE)) { /* &&(padapter->mppriv.check_mp_pkt == 0)) */
-+						if (pattrib->crc_err == 1)
-+							padapter->mppriv.rx_crcerrpktcount++;
-+					}
-+				} else
-+#endif
-+				{
-+					RTW_INFO("%s: crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err);
-+				}
-+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
-+			} else {
-+				ppkt = rtw_skb_clone(precvbuf->pskb);
-+				if (ppkt == NULL) {
-+					RTW_INFO("%s: no enough memory to allocate SKB!\n", __FUNCTION__);
-+					rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
-+					rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
-+
-+					/* The case of can't allocte skb is serious and may never be recovered, */
-+					/* once bDriverStopped is enable, this task should be stopped. */
-+					if (!rtw_is_drv_stopped(padapter)) {
-+#ifdef PLATFORM_LINUX
-+						tasklet_schedule(&precvpriv->recv_tasklet);
-+#endif
-+					}
-+
-+					return;
-+				}
-+
-+				phdr->pkt = ppkt;
-+				phdr->len = 0;
-+				phdr->rx_head = precvbuf->phead;
-+				phdr->rx_data = phdr->rx_tail = precvbuf->pdata;
-+				phdr->rx_end = precvbuf->pend;
-+				recvframe_put(precvframe, pkt_offset);
-+				recvframe_pull(precvframe, RXDESC_SIZE + pattrib->drvinfo_sz);
-+				skb_pull(ppkt, RXDESC_SIZE + pattrib->drvinfo_sz);
-+
-+#ifdef CONFIG_RX_PACKET_APPEND_FCS
-+				if (check_fwstate(&padapter->mlmepriv, WIFI_MONITOR_STATE) == _FALSE) {
-+					if ((pattrib->pkt_rpt_type == NORMAL_RX) && rtw_hal_rcr_check(padapter, RCR_APPFCS)) {
-+						recvframe_pull_tail(precvframe, IEEE80211_FCS_LEN);
-+						pattrib->pkt_len -= IEEE80211_FCS_LEN;
-+						ppkt->len = pattrib->pkt_len;
-+					}
-+				}
-+#endif
-+
-+				/* move to drv info position */
-+				ptr += RXDESC_SIZE;
-+
-+				/* update drv info */
-+				if (rtw_hal_rcr_check(padapter, RCR_APP_BA_SSN)) {
-+					/* rtl8703s_update_bassn(padapter, pdrvinfo); */
-+					ptr += 4;
-+				}
-+
-+				if (pattrib->pkt_rpt_type == NORMAL_RX)
-+					pre_recv_entry(precvframe, pattrib->physt ? ptr : NULL);
-+				else {
-+#ifdef CONFIG_FW_C2H_PKT
-+					if (pattrib->pkt_rpt_type == C2H_PACKET)
-+						rtw_hal_c2h_pkt_pre_hdl(padapter, precvframe->u.hdr.rx_data, pattrib->pkt_len);
-+					else {
-+						RTW_INFO("%s: [WARNNING] RX type(%d) not be handled!\n",
-+							__FUNCTION__, pattrib->pkt_rpt_type);
-+					}
-+#endif
-+					rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
-+				}
-+			}
-+
-+			pkt_offset = _RND8(pkt_offset);
-+			precvbuf->pdata += pkt_offset;
-+			ptr = precvbuf->pdata;
-+		}
-+
-+		rtw_skb_free(precvbuf->pskb);
-+		precvbuf->pskb = NULL;
-+		rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
-+	} while (1);
-+}
-+#endif
-+
-+/*
-+ * Initialize recv private variable for hardware dependent
-+ * 1. recv buf
-+ * 2. recv tasklet
-+ *
-+ */
-+s32 rtl8703bs_init_recv_priv(PADAPTER padapter)
-+{
-+	struct registry_priv *regsty = adapter_to_regsty(padapter);
-+	s32			res;
-+	u32			i, n;
-+	struct recv_priv	*precvpriv;
-+	struct recv_buf		*precvbuf;
-+
-+
-+	res = _SUCCESS;
-+	precvpriv = &padapter->recvpriv;
-+
-+	/* 3 1. init recv buffer */
-+	_rtw_init_queue(&precvpriv->free_recv_buf_queue);
-+	_rtw_init_queue(&precvpriv->recv_buf_pending_queue);
-+
-+	n = regsty->recvbuf_nr * sizeof(struct recv_buf) + 4;
-+	precvpriv->pallocated_recv_buf = rtw_zmalloc(n);
-+	if (precvpriv->pallocated_recv_buf == NULL) {
-+		res = _FAIL;
-+		goto exit;
-+	}
-+
-+	precvpriv->precv_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4);
-+
-+	/* init each recv buffer */
-+	precvbuf = (struct recv_buf *)precvpriv->precv_buf;
-+	for (i = 0; i < regsty->recvbuf_nr; i++) {
-+		res = sdio_initrecvbuf(precvbuf, padapter);
-+		if (res == _FAIL)
-+			break;
-+
-+		res = rtw_os_recvbuf_resource_alloc(padapter, precvbuf, MAX_RECVBUF_SZ);
-+		if (res == _FAIL) {
-+			sdio_freerecvbuf(precvbuf);
-+			break;
-+		}
-+
-+		rtw_list_insert_tail(&precvbuf->list, &precvpriv->free_recv_buf_queue.queue);
-+
-+		precvbuf++;
-+	}
-+	precvpriv->free_recv_buf_queue_cnt = i;
-+
-+	if (res == _FAIL)
-+		goto initbuferror;
-+
-+	/* 3 2. init tasklet */
-+#ifdef PLATFORM_LINUX
-+	tasklet_init(&precvpriv->recv_tasklet,
-+		     (void(*)(unsigned long))rtl8703bs_recv_tasklet,
-+		     (unsigned long)padapter);
-+#endif
-+
-+	goto exit;
-+
-+initbuferror:
-+	precvbuf = (struct recv_buf *)precvpriv->precv_buf;
-+	if (precvbuf) {
-+		n = precvpriv->free_recv_buf_queue_cnt;
-+		precvpriv->free_recv_buf_queue_cnt = 0;
-+		for (i = 0; i < n ; i++) {
-+			rtw_list_delete(&precvbuf->list);
-+			rtw_os_recvbuf_resource_free(padapter, precvbuf);
-+			sdio_freerecvbuf(precvbuf);
-+			precvbuf++;
-+		}
-+		precvpriv->precv_buf = NULL;
-+	}
-+
-+	if (precvpriv->pallocated_recv_buf) {
-+		n = regsty->recvbuf_nr * sizeof(struct recv_buf) + 4;
-+		rtw_mfree(precvpriv->pallocated_recv_buf, n);
-+		precvpriv->pallocated_recv_buf = NULL;
-+	}
-+
-+exit:
-+	return res;
-+}
-+
-+/*
-+ * Free recv private variable of hardware dependent
-+ * 1. recv buf
-+ * 2. recv tasklet
-+ *
-+ */
-+void rtl8703bs_free_recv_priv(PADAPTER padapter)
-+{
-+	struct registry_priv *regsty = &padapter->registrypriv;
-+	u32			i, n;
-+	struct recv_priv	*precvpriv;
-+	struct recv_buf		*precvbuf;
-+
-+
-+	precvpriv = &padapter->recvpriv;
-+
-+	/* 3 1. kill tasklet */
-+#ifdef PLATFORM_LINUX
-+	tasklet_kill(&precvpriv->recv_tasklet);
-+#endif
-+
-+	/* 3 2. free all recv buffers */
-+	precvbuf = (struct recv_buf *)precvpriv->precv_buf;
-+	if (precvbuf) {
-+		n = regsty->recvbuf_nr;
-+		precvpriv->free_recv_buf_queue_cnt = 0;
-+		for (i = 0; i < n ; i++) {
-+			rtw_list_delete(&precvbuf->list);
-+			rtw_os_recvbuf_resource_free(padapter, precvbuf);
-+			sdio_freerecvbuf(precvbuf);
-+			precvbuf++;
-+		}
-+		precvpriv->precv_buf = NULL;
-+	}
-+
-+	if (precvpriv->pallocated_recv_buf) {
-+		n = regsty->recvbuf_nr * sizeof(struct recv_buf) + 4;
-+		rtw_mfree(precvpriv->pallocated_recv_buf, n);
-+		precvpriv->pallocated_recv_buf = NULL;
-+	}
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/rtl8703bs_xmit.c b/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/rtl8703bs_xmit.c
-new file mode 100644
-index 000000000000..439787011b50
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/rtl8703bs_xmit.c
-@@ -0,0 +1,739 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTL8703BS_XMIT_C_
-+
-+#include <rtl8703b_hal.h>
-+
-+static u8 rtw_sdio_wait_enough_TxOQT_space(PADAPTER padapter, u8 agg_num)
-+{
-+	u32 n = 0;
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+
-+	while (pHalData->SdioTxOQTFreeSpace < agg_num) {
-+		if (RTW_CANNOT_RUN(padapter)) {
-+			RTW_INFO("%s: bSurpriseRemoved or bDriverStopped (wait TxOQT)\n", __func__);
-+			return _FALSE;
-+		}
-+
-+		HalQueryTxOQTBufferStatus8703BSdio(padapter);
-+
-+		if ((++n % 60) == 0) {
-+			if ((n % 300) == 0) {
-+				RTW_INFO("%s(%d): QOT free space(%d), agg_num: %d\n",
-+					__func__, n, pHalData->SdioTxOQTFreeSpace, agg_num);
-+			}
-+			rtw_msleep_os(1);
-+			/* yield(); */
-+		}
-+	}
-+
-+	pHalData->SdioTxOQTFreeSpace -= agg_num;
-+
-+	/* if (n > 1) */
-+	/*	++priv->pshare->nr_out_of_txoqt_space; */
-+
-+	return _TRUE;
-+}
-+
-+s32 _dequeue_writeport(PADAPTER padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct xmit_buf *pxmitbuf;
-+	u8	PageIdx = 0;
-+	u32	deviceId;
-+#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+	u8	bUpdatePageNum = _FALSE;
-+#else
-+	u32	polling_num = 0;
-+#endif
-+
-+	pxmitbuf = select_and_dequeue_pending_xmitbuf(padapter);
-+
-+	if (pxmitbuf == NULL)
-+		return _TRUE;
-+
-+	deviceId = ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr);
-+
-+	/* translate fifo addr to queue index */
-+	switch (deviceId) {
-+	case WLAN_TX_HIQ_DEVICE_ID:
-+		PageIdx = HI_QUEUE_IDX;
-+		break;
-+
-+	case WLAN_TX_MIQ_DEVICE_ID:
-+		PageIdx = MID_QUEUE_IDX;
-+		break;
-+
-+	case WLAN_TX_LOQ_DEVICE_ID:
-+		PageIdx = LOW_QUEUE_IDX;
-+		break;
-+	}
-+
-+query_free_page:
-+	/* check if hardware tx fifo page is enough */
-+	if (_FALSE == rtw_hal_sdio_query_tx_freepage(padapter, PageIdx, pxmitbuf->pg_num)) {
-+		if (RTW_CANNOT_RUN(padapter))
-+			goto free_xmitbuf;
-+#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+		if (!bUpdatePageNum) {
-+			/* Total number of page is NOT available, so update current FIFO status */
-+			HalQueryTxBufferStatus8703BSdio(padapter);
-+			bUpdatePageNum = _TRUE;
-+			goto query_free_page;
-+		} else {
-+			bUpdatePageNum = _FALSE;
-+			enqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf);
-+			return _TRUE;
-+		}
-+#else /* CONFIG_SDIO_TX_ENABLE_AVAL_INT */
-+		polling_num++;
-+		if ((polling_num % 10) == 0) {
-+			/* RTW_INFO("%s: FIFO starvation!(%d) len=%d agg=%d page=(R)%d(A)%d\n", */
-+			/*	__func__, polling_num, pxmitbuf->len, pxmitbuf->agg_num, pframe->pg_num, freePage[PageIdx] + freePage[PUBLIC_QUEUE_IDX]); */
-+			enqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf);
-+			rtw_usleep_os(50);
-+			return _FALSE;
-+		}
-+
-+		/* Total number of page is NOT available, so update current FIFO status */
-+		HalQueryTxBufferStatus8703BSdio(padapter);
-+		goto query_free_page;
-+#endif /* CONFIG_SDIO_TX_ENABLE_AVAL_INT */
-+	}
-+
-+	if (rtw_sdio_wait_enough_TxOQT_space(padapter, pxmitbuf->agg_num) == _FALSE)
-+		goto free_xmitbuf;
-+
-+#ifdef CONFIG_CHECK_LEAVE_LPS
-+	#ifdef CONFIG_LPS_CHK_BY_TP
-+	if (!adapter_to_pwrctl(padapter)->lps_chk_by_tp)
-+	#endif
-+		traffic_check_for_leave_lps(padapter, _TRUE, pxmitbuf->agg_num);
-+#endif
-+
-+	rtw_write_port(padapter, deviceId, pxmitbuf->len, (u8 *)pxmitbuf);
-+
-+	rtw_hal_sdio_update_tx_freepage(padapter, PageIdx, pxmitbuf->pg_num);
-+
-+free_xmitbuf:
-+	/* rtw_free_xmitframe(pxmitpriv, pframe); */
-+	/* pxmitbuf->priv_data = NULL; */
-+	rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
-+
-+#if 0 /* improve TX/RX throughput balance */
-+	{
-+		PSDIO_DATA psdio;
-+		struct sdio_func *func;
-+		static u8 i = 0;
-+		u32 sdio_hisr;
-+		u8 j;
-+
-+		psdio = &adapter_to_dvobj(padapter)->intf_data;
-+		func = psdio->func;
-+
-+		if (i == 2) {
-+			j = 0;
-+			while (j < 10) {
-+				sdio_hisr = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HISR);
-+				sdio_hisr &= GET_HAL_DATA(padapter)->sdio_himr;
-+				if (sdio_hisr & SDIO_HISR_RX_REQUEST) {
-+					sdio_claim_host(func);
-+					sd_int_hdl(GET_PRIMARY_ADAPTER(padapter));
-+					sdio_release_host(func);
-+				} else
-+					break;
-+				j++;
-+			}
-+			i = 0;
-+		} else
-+			i++;
-+	}
-+#endif
-+
-+#ifdef CONFIG_SDIO_TX_TASKLET
-+	tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
-+#endif
-+
-+	return _FALSE;
-+}
-+
-+/*
-+ * Description
-+ *	Transmit xmitbuf to hardware tx fifo
-+ *
-+ * Return
-+ *	_SUCCESS	ok
-+ *	_FAIL		something error
-+ */
-+s32 rtl8703bs_xmit_buf_handler(PADAPTER padapter)
-+{
-+	struct xmit_priv *pxmitpriv;
-+	u8	queue_empty;
-+	s32	ret;
-+
-+
-+	pxmitpriv = &padapter->xmitpriv;
-+
-+	ret = _rtw_down_sema(&pxmitpriv->xmit_sema);
-+	if (_FAIL == ret) {
-+		RTW_ERR("%s: down SdioXmitBufSema fail!\n", __FUNCTION__);
-+		return _FAIL;
-+	}
-+
-+	if (RTW_CANNOT_RUN(padapter)) {
-+		RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n",
-+			FUNC_ADPT_ARG(padapter),
-+			rtw_is_drv_stopped(padapter) ? "True" : "False",
-+			rtw_is_surprise_removed(padapter) ? "True" : "False");
-+		return _FAIL;
-+	}
-+
-+	if (rtw_mi_check_pending_xmitbuf(padapter) == 0)
-+		return _SUCCESS;
-+
-+#ifdef CONFIG_LPS_LCLK
-+	ret = rtw_register_tx_alive(padapter);
-+	if (ret != _SUCCESS)
-+		return _SUCCESS;
-+#endif
-+
-+	do {
-+		queue_empty = rtw_mi_dequeue_writeport(padapter);
-+	} while (!queue_empty);
-+
-+#ifdef CONFIG_LPS_LCLK
-+	rtw_unregister_tx_alive(padapter);
-+#endif
-+
-+	return _SUCCESS;
-+}
-+
-+/*
-+ * Description:
-+ *	Aggregation packets and send to hardware
-+ *
-+ * Return:
-+ *	0	Success
-+ *	-1	Hardware resource(TX FIFO) not ready
-+ *	-2	Software resource(xmitbuf) not ready
-+ */
-+static s32 xmit_xmitframes(PADAPTER padapter, struct xmit_priv *pxmitpriv)
-+{
-+	s32 err, ret;
-+	u32 k = 0;
-+	struct hw_xmit *hwxmits, *phwxmit;
-+	u8 no_res, idx, hwentry;
-+	_irqL irql;
-+	struct tx_servq *ptxservq;
-+	_list *sta_plist, *sta_phead, *frame_plist, *frame_phead;
-+	struct xmit_frame *pxmitframe;
-+	_queue *pframe_queue;
-+	struct xmit_buf *pxmitbuf;
-+	u32 txlen, max_xmit_len, page_size;
-+	u8 txdesc_size = TXDESC_SIZE;
-+	int inx[4];
-+	u8 pre_qsel = 0xFF, next_qsel = 0xFF;
-+	u8 single_sta_in_queue = _FALSE;
-+
-+	err = 0;
-+	no_res = _FALSE;
-+	hwxmits = pxmitpriv->hwxmits;
-+	hwentry = pxmitpriv->hwxmit_entry;
-+	ptxservq = NULL;
-+	pxmitframe = NULL;
-+	pframe_queue = NULL;
-+	pxmitbuf = NULL;
-+	rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE 
-+	/* dump management frame directly */
-+	do {
-+		pxmitframe = rtw_dequeue_mgmt_xframe(pxmitpriv);
-+		if (pxmitframe)
-+			padapter->hal_func.mgnt_xmit(padapter, pxmitframe);
-+	} while (pxmitframe != NULL);
-+
-+	hwentry--;
-+#endif
-+
-+	if (padapter->registrypriv.wifi_spec == 1) {
-+		for (idx = 0; idx < 4; idx++)
-+			inx[idx] = pxmitpriv->wmm_para_seq[idx];
-+	} else {
-+		inx[0] = 0;
-+		inx[1] = 1;
-+		inx[2] = 2;
-+		inx[3] = 3;
-+	}
-+
-+	/* 0(VO), 1(VI), 2(BE), 3(BK) */
-+	for (idx = 0; idx < hwentry; idx++) {
-+		phwxmit = hwxmits + inx[idx];
-+
-+		if ((check_pending_xmitbuf(pxmitpriv) == _TRUE) && (padapter->mlmepriv.LinkDetectInfo.bHigherBusyTxTraffic == _TRUE)) {
-+			if ((phwxmit->accnt > 0) && (phwxmit->accnt < 5)) {
-+				err = -2;
-+				break;
-+			}
-+		}
-+
-+		max_xmit_len = rtw_hal_get_sdio_tx_max_length(padapter, inx[idx]);
-+
-+		_enter_critical_bh(&pxmitpriv->lock, &irql);
-+
-+		sta_phead = get_list_head(phwxmit->sta_queue);
-+		sta_plist = get_next(sta_phead);
-+		/* because stop_sta_xmit may delete sta_plist at any time */
-+		/* so we should add lock here, or while loop can not exit */
-+
-+		single_sta_in_queue = rtw_end_of_queue_search(sta_phead, get_next(sta_plist));
-+
-+		while (rtw_end_of_queue_search(sta_phead, sta_plist) == _FALSE) {
-+			ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending);
-+			sta_plist = get_next(sta_plist);
-+
-+#ifdef DBG_XMIT_BUF
-+			RTW_INFO("%s idx:%d hwxmit_pkt_num:%d ptxservq_pkt_num:%d\n", __func__, idx, phwxmit->accnt, ptxservq->qcnt);
-+			RTW_INFO("%s free_xmit_extbuf_cnt=%d free_xmitbuf_cnt=%d free_xmitframe_cnt=%d\n",
-+				__func__, pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xmitbuf_cnt,
-+				 pxmitpriv->free_xmitframe_cnt);
-+#endif
-+			pframe_queue = &ptxservq->sta_pending;
-+
-+			frame_phead = get_list_head(pframe_queue);
-+
-+			while (rtw_is_list_empty(frame_phead) == _FALSE) {
-+				frame_plist = get_next(frame_phead);
-+				pxmitframe = LIST_CONTAINOR(frame_plist, struct xmit_frame, list);
-+
-+				/* check xmit_buf size enough or not */
-+				txlen = txdesc_size + rtw_wlan_pkt_size(pxmitframe);
-+				next_qsel = pxmitframe->attrib.qsel;
-+				if ((NULL == pxmitbuf) ||
-+				    (pxmitbuf->pg_num + PageNum(txlen, page_size) > PageNum(max_xmit_len, page_size))
-+				    || (k >= (rtw_hal_sdio_max_txoqt_free_space(padapter) - 1))
-+				    || ((k != 0) && (_FAIL == rtw_hal_busagg_qsel_check(padapter, pre_qsel, next_qsel)))
-+				   ) {
-+					if (pxmitbuf) {
-+						/* pxmitbuf->priv_data will be NULL, and will crash here */
-+						if (pxmitbuf->len > 0 && pxmitbuf->priv_data) {
-+							struct xmit_frame *pframe;
-+							pframe = (struct xmit_frame *)pxmitbuf->priv_data;
-+							pframe->agg_num = k;
-+							pxmitbuf->agg_num = k;
-+							rtl8703b_update_txdesc(pframe, pframe->buf_addr);
-+							rtw_free_xmitframe(pxmitpriv, pframe);
-+							pxmitbuf->priv_data = NULL;
-+							enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
-+							/* can not yield under lock */
-+
-+							/* rtw_yield_os(); */
-+							if (single_sta_in_queue == _FALSE) {
-+								/* break the loop in case there is more than one sta in this ac queue */
-+								pxmitbuf = NULL;
-+								err = -3;
-+								break;
-+							}
-+						} else
-+							rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
-+					}
-+
-+					pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
-+					if (pxmitbuf == NULL) {
-+#ifdef DBG_XMIT_BUF
-+						RTW_ERR("%s: xmit_buf is not enough!\n", __FUNCTION__);
-+#endif
-+						err = -2;
-+#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+						_rtw_up_sema(&(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.xmit_sema));
-+#endif
-+						break;
-+					}
-+					k = 0;
-+				}
-+
-+				/* ok to send, remove frame from queue */
-+#ifdef CONFIG_AP_MODE
-+				if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
-+					if ((pxmitframe->attrib.psta->state & WIFI_SLEEP_STATE) &&
-+					    (pxmitframe->attrib.triggered == 0)) {
-+						RTW_INFO("%s: one not triggered pkt in queue when this STA sleep,"
-+							" break and goto next sta\n", __func__);
-+						break;
-+					}
-+				}
-+#endif
-+				rtw_list_delete(&pxmitframe->list);
-+				ptxservq->qcnt--;
-+				phwxmit->accnt--;
-+
-+				if (k == 0) {
-+					pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
-+					pxmitbuf->priv_data = (u8 *)pxmitframe;
-+				}
-+
-+				/* coalesce the xmitframe to xmitbuf */
-+				pxmitframe->pxmitbuf = pxmitbuf;
-+				pxmitframe->buf_addr = pxmitbuf->ptail;
-+
-+				ret = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
-+				if (ret == _FAIL) {
-+					RTW_ERR("%s: coalesce FAIL!", __FUNCTION__);
-+					/* Todo: error handler */
-+				} else {
-+					k++;
-+					if (k != 1)
-+						rtl8703b_update_txdesc(pxmitframe, pxmitframe->buf_addr);
-+					rtw_count_tx_stats(padapter, pxmitframe, pxmitframe->attrib.last_txcmdsz);
-+					pre_qsel = pxmitframe->attrib.qsel;
-+					txlen = txdesc_size + pxmitframe->attrib.last_txcmdsz;
-+					pxmitframe->pg_num = (txlen + 127) / 128;
-+					pxmitbuf->pg_num += (txlen + 127) / 128;
-+					/* if (k != 1) */
-+					/*	((struct xmit_frame*)pxmitbuf->priv_data)->pg_num += pxmitframe->pg_num; */
-+					pxmitbuf->ptail += _RND(txlen, 8); /* round to 8 bytes alignment */
-+					pxmitbuf->len = _RND(pxmitbuf->len, 8) + txlen;
-+				}
-+
-+				if (k != 1)
-+					rtw_free_xmitframe(pxmitpriv, pxmitframe);
-+				pxmitframe = NULL;
-+			}
-+
-+			if (_rtw_queue_empty(pframe_queue) == _TRUE)
-+				rtw_list_delete(&ptxservq->tx_pending);
-+			else if (err == -3) {
-+				/* Re-arrange the order of stations in this ac queue to balance the service for these stations */
-+				rtw_list_delete(&ptxservq->tx_pending);
-+				rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmit->sta_queue));
-+			}
-+
-+			if (err)
-+				break;
-+		}
-+		_exit_critical_bh(&pxmitpriv->lock, &irql);
-+
-+		/* dump xmit_buf to hw tx fifo */
-+		if (pxmitbuf) {
-+
-+			if (pxmitbuf->len > 0) {
-+				struct xmit_frame *pframe;
-+				pframe = (struct xmit_frame *)pxmitbuf->priv_data;
-+				pframe->agg_num = k;
-+				pxmitbuf->agg_num = k;
-+				rtl8703b_update_txdesc(pframe, pframe->buf_addr);
-+				rtw_free_xmitframe(pxmitpriv, pframe);
-+				pxmitbuf->priv_data = NULL;
-+				enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
-+				rtw_yield_os();
-+			} else
-+				rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
-+			pxmitbuf = NULL;
-+		}
-+
-+		if (err == -2)
-+			break;
-+	}
-+
-+	return err;
-+}
-+
-+/*
-+ * Description
-+ *	Transmit xmitframe from queue
-+ *
-+ * Return
-+ *	_SUCCESS	ok
-+ *	_FAIL		something error
-+ */
-+s32 rtl8703bs_xmit_handler(PADAPTER padapter)
-+{
-+	struct xmit_priv *pxmitpriv;
-+	s32 ret;
-+	_irqL irql;
-+
-+
-+	pxmitpriv = &padapter->xmitpriv;
-+
-+	ret = _rtw_down_sema(&pxmitpriv->SdioXmitSema);
-+	if (_FAIL == ret) {
-+		RTW_ERR("%s: down sema fail!\n", __FUNCTION__);
-+		return _FAIL;
-+	}
-+
-+next:
-+	if (RTW_CANNOT_RUN(padapter)) {
-+		RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n",
-+			FUNC_ADPT_ARG(padapter),
-+			rtw_is_drv_stopped(padapter) ? "True" : "False",
-+			rtw_is_surprise_removed(padapter) ? "True" : "False");
-+		return _FAIL;
-+	}
-+
-+	_enter_critical_bh(&pxmitpriv->lock, &irql);
-+	ret = rtw_txframes_pending(padapter);
-+	_exit_critical_bh(&pxmitpriv->lock, &irql);
-+	if (ret == 0)
-+		return _SUCCESS;
-+
-+	/* dequeue frame and write to hardware */
-+
-+	ret = xmit_xmitframes(padapter, pxmitpriv);
-+	if (ret == -2) {
-+		/* here sleep 1ms will cause big TP loss of TX */
-+		/* from 50+ to 40+ */
-+		if (padapter->registrypriv.wifi_spec)
-+			rtw_msleep_os(1);
-+		else
-+#ifdef CONFIG_REDUCE_TX_CPU_LOADING
-+			rtw_msleep_os(1);
-+#else
-+			rtw_usleep_os(50);
-+#endif
-+		goto next;
-+	}
-+
-+	_enter_critical_bh(&pxmitpriv->lock, &irql);
-+	ret = rtw_txframes_pending(padapter);
-+	_exit_critical_bh(&pxmitpriv->lock, &irql);
-+	if (ret == 1) {
-+#ifdef CONFIG_REDUCE_TX_CPU_LOADING
-+		rtw_msleep_os(1);
-+#endif
-+		goto next;
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+thread_return rtl8703bs_xmit_thread(thread_context context)
-+{
-+	s32 ret;
-+	PADAPTER padapter;
-+	struct xmit_priv *pxmitpriv;
-+	u8 thread_name[20] = {0};
-+
-+
-+	ret = _SUCCESS;
-+	padapter = (PADAPTER)context;
-+	pxmitpriv = &padapter->xmitpriv;
-+
-+	rtw_sprintf(thread_name, 20, "RTWHALXT-"ADPT_FMT, ADPT_ARG(padapter));
-+	thread_enter(thread_name);
-+
-+	RTW_INFO("start "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+
-+	do {
-+		ret = rtl8703bs_xmit_handler(padapter);
-+		flush_signals_thread();
-+	} while (_SUCCESS == ret);
-+
-+	RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter));
-+
-+	rtw_thread_wait_stop();
-+
-+	return 0;
-+}
-+
-+s32 rtl8703bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe)
-+{
-+	s32 ret = _SUCCESS;
-+	struct pkt_attrib *pattrib;
-+	struct xmit_buf *pxmitbuf;
-+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
-+	u8 *pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	u8 txdesc_size = TXDESC_SIZE;
-+
-+
-+	pattrib = &pmgntframe->attrib;
-+	pxmitbuf = pmgntframe->pxmitbuf;
-+
-+	rtl8703b_update_txdesc(pmgntframe, pmgntframe->buf_addr);
-+
-+	pxmitbuf->len = txdesc_size + pattrib->last_txcmdsz;
-+	/* pmgntframe->pg_num = (pxmitbuf->len + 127)/128; // 128 is tx page size */
-+	pxmitbuf->pg_num = (pxmitbuf->len + 127) / 128; /* 128 is tx page size */
-+	pxmitbuf->ptail = pmgntframe->buf_addr + pxmitbuf->len;
-+	pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pmgntframe);
-+
-+	rtw_count_tx_stats(padapter, pmgntframe, pattrib->last_txcmdsz);
-+
-+	rtw_free_xmitframe(pxmitpriv, pmgntframe);
-+
-+	pxmitbuf->priv_data = NULL;
-+
-+	if (get_frame_sub_type(pframe) == WIFI_BEACON) { /* dump beacon directly */
-+		ret = rtw_write_port(padapter, pdvobjpriv->Queue2Pipe[pxmitbuf->ff_hwaddr], pxmitbuf->len, (u8 *)pxmitbuf);
-+		if (ret != _SUCCESS)
-+			rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_WRITE_PORT_ERR);
-+
-+		rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
-+	} else
-+		enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
-+
-+	return ret;
-+}
-+
-+/*
-+ * Description:
-+ *	Handle xmitframe(packet) come from rtw_xmit()
-+ *
-+ * Return:
-+ *	_TRUE	dump packet directly ok
-+ *	_FALSE	enqueue, temporary can't transmit packets to hardware
-+ */
-+s32 rtl8703bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe)
-+{
-+	struct xmit_priv *pxmitpriv;
-+	_irqL irql;
-+	s32 err;
-+
-+
-+	pxmitframe->attrib.qsel = pxmitframe->attrib.priority;
-+	pxmitpriv = &padapter->xmitpriv;
-+
-+#ifdef CONFIG_80211N_HT
-+	if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
-+	    (pxmitframe->attrib.ether_type != 0x0806) &&
-+	    (pxmitframe->attrib.ether_type != 0x888e) &&
-+	    (pxmitframe->attrib.dhcp_pkt != 1)) {
-+		rtw_issue_addbareq_cmd(padapter, pxmitframe, _TRUE);
-+	}
-+#endif
-+
-+	_enter_critical_bh(&pxmitpriv->lock, &irql);
-+	err = rtw_xmitframe_enqueue(padapter, pxmitframe);
-+	_exit_critical_bh(&pxmitpriv->lock, &irql);
-+	if (err != _SUCCESS) {
-+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
-+
-+		pxmitpriv->tx_drop++;
-+		return _TRUE;
-+	}
-+
-+	_rtw_up_sema(&pxmitpriv->SdioXmitSema);
-+
-+	return _FALSE;
-+}
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE 
-+s32 rtl8703bs_hal_mgmt_xmitframe_enqueue(PADAPTER adapter, struct xmit_frame *pxmitframe)
-+{
-+	struct xmit_priv *pxmitpriv;
-+	s32 ret;
-+
-+	pxmitpriv = &adapter->xmitpriv;
-+
-+	ret = rtw_mgmt_xmitframe_enqueue(adapter, pxmitframe);
-+	if (ret != _SUCCESS) {
-+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
-+		pxmitpriv->tx_drop++;
-+		return _FALSE;
-+	}
-+
-+#ifdef CONFIG_SDIO_TX_TASKLET
-+	tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
-+#else
-+	_rtw_up_sema(&pxmitpriv->SdioXmitSema);
-+#endif
-+
-+	return _TRUE;
-+}
-+#endif
-+
-+s32	rtl8703bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
-+{
-+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
-+	s32 err;
-+
-+	err = rtw_xmitframe_enqueue(padapter, pxmitframe);
-+	if (err != _SUCCESS) {
-+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
-+
-+		pxmitpriv->tx_drop++;
-+	} else {
-+#ifdef CONFIG_SDIO_TX_TASKLET
-+		tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
-+#else
-+		_rtw_up_sema(&pxmitpriv->SdioXmitSema);
-+#endif
-+	}
-+
-+	return err;
-+
-+}
-+
-+/*
-+ * Return
-+ *	_SUCCESS	start thread ok
-+ *	_FAIL		start thread fail
-+ *
-+ */
-+s32 rtl8703bs_init_xmit_priv(PADAPTER padapter)
-+{
-+	struct xmit_priv *xmitpriv = &padapter->xmitpriv;
-+	PHAL_DATA_TYPE phal;
-+
-+
-+	phal = GET_HAL_DATA(padapter);
-+
-+	_rtw_spinlock_init(&phal->SdioTxFIFOFreePageLock);
-+	_rtw_init_sema(&xmitpriv->SdioXmitSema, 0);
-+
-+	return _SUCCESS;
-+}
-+
-+void rtl8703bs_free_xmit_priv(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE phal;
-+	struct xmit_priv *pxmitpriv;
-+	struct xmit_buf *pxmitbuf;
-+	_queue *pqueue;
-+	_list *plist, *phead;
-+	_list tmplist;
-+	_irqL irql;
-+
-+
-+	phal = GET_HAL_DATA(padapter);
-+	pxmitpriv = &padapter->xmitpriv;
-+	pqueue = &pxmitpriv->pending_xmitbuf_queue;
-+	phead = get_list_head(pqueue);
-+	_rtw_init_listhead(&tmplist);
-+
-+	_enter_critical_bh(&pqueue->lock, &irql);
-+	if (_rtw_queue_empty(pqueue) == _FALSE) {
-+		/* Insert tmplist to end of queue, and delete phead */
-+		/* then tmplist become head of queue. */
-+		rtw_list_insert_tail(&tmplist, phead);
-+		rtw_list_delete(phead);
-+	}
-+	_exit_critical_bh(&pqueue->lock, &irql);
-+
-+	phead = &tmplist;
-+	while (rtw_is_list_empty(phead) == _FALSE) {
-+		plist = get_next(phead);
-+		rtw_list_delete(plist);
-+
-+		pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
-+		rtw_free_xmitframe(pxmitpriv, (struct xmit_frame *)pxmitbuf->priv_data);
-+		pxmitbuf->priv_data = NULL;
-+		rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
-+	}
-+
-+	_rtw_spinlock_free(&phal->SdioTxFIFOFreePageLock);
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/sdio_halinit.c b/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/sdio_halinit.c
-new file mode 100644
-index 000000000000..18c50d6fd2a4
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/sdio_halinit.c
-@@ -0,0 +1,1668 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _SDIO_HALINIT_C_
-+
-+#include <rtl8703b_hal.h>
-+#include "hal_com_h2c.h"
-+
-+/*
-+ * Description:
-+ *	Call power on sequence to enable card
-+ *
-+ * Return:
-+ *	_SUCCESS	enable success
-+ *	_FAIL		enable fail
-+ */
-+static u8 CardEnable(PADAPTER padapter)
-+{
-+	u8 bMacPwrCtrlOn;
-+	u8 ret = _FAIL;
-+
-+
-+	bMacPwrCtrlOn = _FALSE;
-+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+	if (bMacPwrCtrlOn == _FALSE) {
-+		/* RSV_CTRL 0x1C[7:0] = 0x00 */
-+		/* unlock ISO/CLK/Power control register */
-+		rtw_write8(padapter, REG_RSV_CTRL, 0x0);
-+
-+		ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_card_enable_flow);
-+		if (ret == _SUCCESS) {
-+			u8 bMacPwrCtrlOn = _TRUE;
-+			rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+		}
-+	} else
-+		ret = _SUCCESS;
-+
-+	return ret;
-+}
-+
-+/* static */
-+u32 _InitPowerOn_8703BS(PADAPTER padapter)
-+{
-+	u8 value8;
-+	u16 value16;
-+	u32 value32;
-+	u8 ret;
-+	u8 pwron_chk_cnt = 0;
-+	/*	u8 bMacPwrCtrlOn; */
-+
-+_init_power_on:
-+
-+#if 1
-+	/* all of these MUST be configured before power on */
-+#ifdef CONFIG_XTAL_26M
-+	/* Config PLL Reference CLK, */
-+	/* Change crystal to 26M, APLL_FREF_SEL = 4b'0101 */
-+	/* APLL_FREF_SEL[0]=1b'1 */
-+	value8 = rtw_read8(padapter, REG_AFE_PLL_CTRL);
-+	value8 |= BIT(2);
-+	rtw_write8(padapter, REG_AFE_PLL_CTRL, value8);
-+	/* APLL_FREF_SEL[2:1]=2b'10 */
-+	value8 = rtw_read8(padapter, REG_AFE_CTRL_4_8703B + 1);
-+	value8 &= ~(BIT(1) | BIT(0));
-+	value8 |= BIT(1);
-+	rtw_write16(padapter, REG_AFE_CTRL_4_8703B + 1, value8);
-+	/* APLL_FREF_SEL[3]=1b'0 */
-+	value8 = rtw_read8(padapter, REG_AFE_CTRL_4_8703B);
-+	value8 &= ~BIT(7);
-+	rtw_write16(padapter, REG_AFE_CTRL_4_8703B, value8);
-+#endif /* CONFIG_XTAL_26M */
-+
-+#ifdef CONFIG_EXT_CLK
-+	/* Use external crystal(XTAL) */
-+	value8 = rtw_read8(padapter, REG_PAD_CTRL1_8703B + 2);
-+	value8 |=  BIT(7);
-+	rtw_write8(padapter, REG_PAD_CTRL1_8703B + 2, value8);
-+
-+	/* CLK_REQ High active or Low Active */
-+	/* Request GPIO polarity: */
-+	/* 0: low active */
-+	/* 1: high active */
-+	value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL + 1);
-+	value8 |= BIT(5);
-+	rtw_write8(padapter, REG_MULTI_FUNC_CTRL + 1, value8);
-+#endif /* CONFIG_EXT_CLK */
-+#endif /* all of these MUST be configured before power on */
-+
-+	/* only cmd52 can be used before power on(card enable) */
-+	ret = CardEnable(padapter);
-+	if (ret == _FALSE) {
-+		return _FAIL;
-+	}
-+
-+	/* Radio-Off Pin Trigger */
-+	value8 = rtw_read8(padapter, REG_GPIO_INTM + 1);
-+	value8 |= BIT(1); /* Enable falling edge triggering interrupt */
-+	rtw_write8(padapter, REG_GPIO_INTM + 1, value8);
-+	value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2 + 1);
-+	value8 |= BIT(1);
-+	rtw_write8(padapter, REG_GPIO_IO_SEL_2 + 1, value8);
-+
-+	/* Enable power down and GPIO interrupt */
-+	value16 = rtw_read16(padapter, REG_APS_FSMCO);
-+	value16 |= EnPDN; /* Enable HW power down and RF on */
-+	rtw_write16(padapter, REG_APS_FSMCO, value16);
-+
-+	/* Enable CMD53 R/W Operation
-+	*	bMacPwrCtrlOn = _TRUE;
-+	*	rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); */
-+
-+	rtw_write8(padapter, REG_CR, 0x00);
-+	/* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
-+	value16 = rtw_read16(padapter, REG_CR);
-+	value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
-+		    | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
-+	rtw_write16(padapter, REG_CR, value16);
-+
-+
-+	/* PowerOnCheck() */
-+	ret = sdio_power_on_check(padapter);
-+	pwron_chk_cnt++;
-+	if (_FAIL == ret) {
-+		if (pwron_chk_cnt > 1) {
-+			RTW_INFO("Failed to init Power On!\n");
-+			return _FAIL;
-+		}
-+		RTW_INFO("Power on Fail! do it again\n");
-+		goto _init_power_on;
-+	}
-+
-+	return _SUCCESS;
-+}
-+#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+/* Tx Page FIFO threshold */
-+static void _init_available_page_threshold(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ)
-+{
-+	u16	HQ_threshold, NQ_threshold, LQ_threshold;
-+
-+	HQ_threshold = (numPubQ + numHQ + 1) >> 1;
-+	HQ_threshold |= (HQ_threshold << 8);
-+
-+	NQ_threshold = (numPubQ + numNQ + 1) >> 1;
-+	NQ_threshold |= (NQ_threshold << 8);
-+
-+	LQ_threshold = (numPubQ + numLQ + 1) >> 1;
-+	LQ_threshold |= (LQ_threshold << 8);
-+
-+	rtw_write16(padapter, 0x218, HQ_threshold);
-+	rtw_write16(padapter, 0x21A, NQ_threshold);
-+	rtw_write16(padapter, 0x21C, LQ_threshold);
-+	RTW_INFO("%s(): Enable Tx FIFO Page Threshold H:0x%x,N:0x%x,L:0x%x\n", __FUNCTION__, HQ_threshold, NQ_threshold, LQ_threshold);
-+}
-+#endif
-+static void _InitQueueReservedPage(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
-+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+	u32			outEPNum	= (u32)pHalData->OutEpNumber;
-+	u32			numHQ		= 0;
-+	u32			numLQ		= 0;
-+	u32			numNQ		= 0;
-+	u32			numPubQ;
-+	u32			value32;
-+	u8			value8;
-+	BOOLEAN			bWiFiConfig	= pregistrypriv->wifi_spec;
-+
-+	if (pHalData->OutEpQueueSel & TX_SELE_HQ)
-+		numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8703B : NORMAL_PAGE_NUM_HPQ_8703B;
-+
-+	if (pHalData->OutEpQueueSel & TX_SELE_LQ)
-+		numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8703B : NORMAL_PAGE_NUM_LPQ_8703B;
-+
-+	/* NOTE: This step shall be proceed before writting REG_RQPN. */
-+	if (pHalData->OutEpQueueSel & TX_SELE_NQ)
-+		numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8703B : NORMAL_PAGE_NUM_NPQ_8703B;
-+
-+	numPubQ = TX_TOTAL_PAGE_NUMBER_8703B - numHQ - numLQ - numNQ;
-+
-+	value8 = (u8)_NPQ(numNQ);
-+	rtw_write8(padapter, REG_RQPN_NPQ, value8);
-+
-+	/* TX DMA */
-+	value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
-+	rtw_write32(padapter, REG_RQPN, value32);
-+
-+	rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ, SDIO_TX_DIV_NUM);
-+
-+#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+	_init_available_page_threshold(padapter, numHQ, numNQ, numLQ, numPubQ);
-+#endif
-+}
-+
-+static void _InitTxBufferBoundary(PADAPTER padapter)
-+{
-+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+#ifdef CONFIG_CONCURRENT_MODE
-+	u8 val8;
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+	/* u16	txdmactrl; */
-+	u8	txpktbuf_bndy;
-+
-+	if (!pregistrypriv->wifi_spec)
-+		txpktbuf_bndy = TX_PAGE_BOUNDARY_8703B;
-+	else {
-+		/* for WMM */
-+		txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8703B;
-+	}
-+
-+	rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8703B, txpktbuf_bndy);
-+	rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8703B, txpktbuf_bndy);
-+	rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8703B, txpktbuf_bndy);
-+	rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
-+	rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	val8 = txpktbuf_bndy + BCNQ_PAGE_NUM_8703B + WOWLAN_PAGE_NUM_8703B;
-+	rtw_write8(padapter, REG_BCNQ1_BDNY, val8);
-+	rtw_write8(padapter, REG_DWBCN1_CTRL_8703B + 1, val8); /* BCN1_HEAD */
-+
-+	val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8703B + 2);
-+	val8 |= BIT(1); /* BIT1- BIT_SW_BCN_SEL_EN */
-+	rtw_write8(padapter, REG_DWBCN1_CTRL_8703B + 2, val8);
-+#endif /* CONFIG_CONCURRENT_MODE */
-+}
-+
-+static void
-+_InitNormalChipRegPriority(
-+		PADAPTER	Adapter,
-+		u16		beQ,
-+		u16		bkQ,
-+		u16		viQ,
-+		u16		voQ,
-+		u16		mgtQ,
-+		u16		hiQ
-+)
-+{
-+	u16 value16		= (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
-+
-+	value16 |=	_TXDMA_BEQ_MAP(beQ)	| _TXDMA_BKQ_MAP(bkQ) |
-+			_TXDMA_VIQ_MAP(viQ)	| _TXDMA_VOQ_MAP(voQ) |
-+			_TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
-+
-+	rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
-+}
-+
-+static void
-+_InitNormalChipOneOutEpPriority(
-+		PADAPTER Adapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
-+
-+	u16	value = 0;
-+	switch (pHalData->OutEpQueueSel) {
-+	case TX_SELE_HQ:
-+		value = QUEUE_HIGH;
-+		break;
-+	case TX_SELE_LQ:
-+		value = QUEUE_LOW;
-+		break;
-+	case TX_SELE_NQ:
-+		value = QUEUE_NORMAL;
-+		break;
-+	default:
-+		/* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
-+		break;
-+	}
-+
-+	_InitNormalChipRegPriority(Adapter,
-+				   value,
-+				   value,
-+				   value,
-+				   value,
-+				   value,
-+				   value
-+				  );
-+
-+}
-+
-+static void
-+_InitNormalChipTwoOutEpPriority(
-+		PADAPTER Adapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
-+	struct registry_priv *pregistrypriv = &Adapter->registrypriv;
-+	u16			beQ, bkQ, viQ, voQ, mgtQ, hiQ;
-+
-+
-+	u16	valueHi = 0;
-+	u16	valueLow = 0;
-+
-+	switch (pHalData->OutEpQueueSel) {
-+	case (TX_SELE_HQ | TX_SELE_LQ):
-+		valueHi = QUEUE_HIGH;
-+		valueLow = QUEUE_LOW;
-+		break;
-+	case (TX_SELE_NQ | TX_SELE_LQ):
-+		valueHi = QUEUE_NORMAL;
-+		valueLow = QUEUE_LOW;
-+		break;
-+	case (TX_SELE_HQ | TX_SELE_NQ):
-+		valueHi = QUEUE_HIGH;
-+		valueLow = QUEUE_NORMAL;
-+		break;
-+	default:
-+		/* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
-+		break;
-+	}
-+
-+	if (!pregistrypriv->wifi_spec) {
-+		beQ		= valueLow;
-+		bkQ		= valueLow;
-+		viQ		= valueHi;
-+		voQ		= valueHi;
-+		mgtQ	= valueHi;
-+		hiQ		= valueHi;
-+	} else { /* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
-+		beQ		= valueLow;
-+		bkQ		= valueHi;
-+		viQ		= valueHi;
-+		voQ		= valueLow;
-+		mgtQ	= valueHi;
-+		hiQ		= valueHi;
-+	}
-+
-+	_InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
-+
-+}
-+
-+static void
-+_InitNormalChipThreeOutEpPriority(
-+		PADAPTER padapter
-+)
-+{
-+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+	u16			beQ, bkQ, viQ, voQ, mgtQ, hiQ;
-+
-+	if (!pregistrypriv->wifi_spec) { /* typical setting */
-+		beQ		= QUEUE_LOW;
-+		bkQ		= QUEUE_LOW;
-+		viQ		= QUEUE_NORMAL;
-+		voQ		= QUEUE_HIGH;
-+		mgtQ	= QUEUE_HIGH;
-+		hiQ		= QUEUE_HIGH;
-+	} else { /* for WMM */
-+		beQ		= QUEUE_LOW;
-+		bkQ		= QUEUE_NORMAL;
-+		viQ		= QUEUE_NORMAL;
-+		voQ		= QUEUE_HIGH;
-+		mgtQ	= QUEUE_HIGH;
-+		hiQ		= QUEUE_HIGH;
-+	}
-+	_InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
-+}
-+
-+static void
-+_InitNormalChipQueuePriority(
-+		PADAPTER Adapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
-+
-+	switch (pHalData->OutEpNumber) {
-+	case 1:
-+		_InitNormalChipOneOutEpPriority(Adapter);
-+		break;
-+	case 2:
-+		_InitNormalChipTwoOutEpPriority(Adapter);
-+		break;
-+	case 3:
-+		_InitNormalChipThreeOutEpPriority(Adapter);
-+		break;
-+	default:
-+		/* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
-+		break;
-+	}
-+
-+
-+}
-+
-+static void _InitQueuePriority(PADAPTER padapter)
-+{
-+	_InitNormalChipQueuePriority(padapter);
-+}
-+
-+static void _InitPageBoundary(PADAPTER padapter)
-+{
-+	/* RX Page Boundary */
-+	u16 rxff_bndy = RX_DMA_BOUNDARY_8703B;
-+
-+	rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
-+}
-+
-+static void _InitTransferPageSize(PADAPTER padapter)
-+{
-+	/* Tx page size is always 128. */
-+
-+	u8 value8;
-+	value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
-+	rtw_write8(padapter, REG_PBP, value8);
-+}
-+
-+void _InitDriverInfoSize(PADAPTER padapter, u8 drvInfoSize)
-+{
-+	rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
-+}
-+
-+void _InitNetworkType(PADAPTER padapter)
-+{
-+	u32 value32;
-+
-+	value32 = rtw_read32(padapter, REG_CR);
-+
-+	/* TODO: use the other function to set network type
-+	*	value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */
-+	value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
-+
-+	rtw_write32(padapter, REG_CR, value32);
-+}
-+
-+void _InitWMACSetting(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+	u16 value16;
-+	u32 rcr;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	rcr = 0
-+		| RCR_APM | RCR_AM | RCR_AB
-+		| RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF
-+		| RCR_HTC_LOC_CTRL
-+		| RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC
-+		#ifdef CONFIG_MAC_LOOPBACK_DRIVER
-+		| RCR_AAP
-+		| RCR_ADD3 | RCR_APWRMGT | RCR_ACRC32 | RCR_ADF
-+		#endif
-+		;
-+	rtw_hal_set_hwreg(padapter, HW_VAR_RCR, (u8 *)&rcr);
-+
-+	/* Accept all multicast address */
-+	rtw_write32(padapter, REG_MAR, 0xFFFFFFFF);
-+	rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF);
-+
-+	/* Accept all data frames */
-+	value16 = 0xFFFF;
-+	rtw_write16(padapter, REG_RXFLTMAP2, value16);
-+
-+	/* 2010.09.08 hpfan */
-+	/* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */
-+	/* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */
-+	value16 = 0x400;
-+	rtw_write16(padapter, REG_RXFLTMAP1, value16);
-+
-+	/* Accept all management frames */
-+	value16 = 0xFFFF;
-+	rtw_write16(padapter, REG_RXFLTMAP0, value16);
-+}
-+
-+void _InitAdaptiveCtrl(PADAPTER padapter)
-+{
-+	u16	value16;
-+	u32	value32;
-+
-+	/* Response Rate Set */
-+	value32 = rtw_read32(padapter, REG_RRSR);
-+	value32 &= ~RATE_BITMAP_ALL;
-+	value32 |= RATE_RRSR_CCK_ONLY_1M;
-+
-+	rtw_phydm_set_rrsr(padapter, value32, TRUE);
-+
-+
-+	/* CF-END Threshold */
-+	/* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
-+
-+	/* SIFS (used in NAV) */
-+	value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
-+	rtw_write16(padapter, REG_SPEC_SIFS, value16);
-+
-+	/* Retry Limit */
-+	value16 = BIT_LRL(RL_VAL_STA) | BIT_SRL(RL_VAL_STA);
-+	rtw_write16(padapter, REG_RETRY_LIMIT, value16);
-+}
-+
-+void _InitEDCA(PADAPTER padapter)
-+{
-+	/* Set Spec SIFS (used in NAV) */
-+	rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
-+	rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
-+
-+	/* Set SIFS for CCK */
-+	rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
-+
-+	/* Set SIFS for OFDM */
-+	rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
-+
-+	/* TXOP */
-+	rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
-+	rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
-+	rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
-+	rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
-+}
-+
-+void _InitRetryFunction(PADAPTER padapter)
-+{
-+	u8	value8;
-+
-+	value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
-+	value8 |= EN_AMPDU_RTY_NEW;
-+	rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
-+
-+	/* Set ACK timeout */
-+	rtw_write8(padapter, REG_ACKTO, 0x40);
-+}
-+
-+static void HalRxAggr8703BSdio(PADAPTER padapter)
-+{
-+	struct registry_priv *pregistrypriv;
-+	u8	valueDMATimeout;
-+	u8	valueDMAPageCount;
-+
-+
-+	pregistrypriv = &padapter->registrypriv;
-+
-+	if (pregistrypriv->wifi_spec) {
-+		/* 2010.04.27 hpfan */
-+		/* Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer */
-+		/* Timeout value is calculated by 34 / (2^n) */
-+		valueDMATimeout = 0x06;
-+		valueDMAPageCount = 0x06;
-+	} else {
-+		/* 20130530, Isaac@SD1 suggest 3 kinds of parameter */
-+#if 1
-+		/* TX/RX Balance */
-+		valueDMATimeout = 0x06;
-+		valueDMAPageCount = 0x06;
-+#endif
-+#if 0
-+		/* TX/RX Balance, but TCP ack may be late */
-+		valueDMATimeout = 0x16;
-+		valueDMAPageCount = 0x06;
-+#endif
-+#if 0
-+		/* RX Best */
-+		valueDMATimeout = 0x16;
-+		valueDMAPageCount = 0x08;
-+#endif
-+	}
-+
-+#ifdef CONFIG_DONT_CARE_TP
-+	valueDMATimeout = 0x0f;
-+	valueDMAPageCount = 0x04;  /* RxAggUpthreshold = [4]*1K bytes+1.5k.  since RxAggUpthreshold+SzAmsdu(3839)<MaxRxBuffSize(8k), MaxvalueDMAPageCount=4. */
-+#endif
-+	rtw_write8(padapter, REG_RXDMA_AGG_PG_TH + 1, valueDMATimeout);
-+	rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount);
-+}
-+
-+void sdio_AggSettingRxUpdate(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE *pHalData;
-+	u8 valueDMA;
-+	u8 valueRxAggCtrl = 0;
-+	u8 aggBurstNum = 3;  /* 0:1, 1:2, 2:3, 3:4 */
-+	u8 aggBurstSize = 0;  /* 0:1K, 1:512Byte, 2:256Byte... */
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
-+	valueDMA |= RXDMA_AGG_EN;
-+	rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
-+
-+	valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
-+	valueRxAggCtrl |= ((aggBurstNum << 2) & 0x0C);
-+	valueRxAggCtrl |= ((aggBurstSize << 4) & 0x30);
-+	rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8703B, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */
-+}
-+
-+void _initSdioAggregationSetting(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	/* Tx aggregation setting
-+	*	sdio_AggSettingTxUpdate(padapter); */
-+
-+	/* Rx aggregation setting */
-+	HalRxAggr8703BSdio(padapter);
-+
-+	sdio_AggSettingRxUpdate(padapter);
-+}
-+#if 0
-+static void _RXAggrSwitch(PADAPTER padapter, u8 enable)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+	u8 valueDMA;
-+	u8 valueRxAggCtrl;
-+
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
-+	valueRxAggCtrl = rtw_read8(padapter, REG_RXDMA_MODE_CTRL_8703B);
-+
-+	if (_TRUE == enable) {
-+		valueDMA |= RXDMA_AGG_EN;
-+		valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
-+	} else {
-+		valueDMA &= ~RXDMA_AGG_EN;
-+		valueRxAggCtrl &= ~RXDMA_AGG_MODE_EN;
-+	}
-+
-+	rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
-+	rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8703B, valueRxAggCtrl);
-+}
-+#endif
-+void _InitInterrupt(PADAPTER padapter)
-+{
-+	/* HISR - turn all off */
-+	rtw_write32(padapter, REG_HISR, 0);
-+
-+	/* HIMR - turn all off */
-+	rtw_write32(padapter, REG_HIMR, 0);
-+
-+	/*  */
-+	/* Initialize and enable SDIO Host Interrupt. */
-+	/*  */
-+	InitInterrupt8703BSdio(padapter);
-+
-+	/*  */
-+	/* Initialize system Host Interrupt. */
-+	/*  */
-+	InitSysInterrupt8703BSdio(padapter);
-+}
-+
-+void _InitRDGSetting(PADAPTER padapter)
-+{
-+	rtw_write8(padapter, REG_RD_CTRL, 0xFF);
-+	rtw_write16(padapter, REG_RD_NAV_NXT, 0x200);
-+	rtw_write8(padapter, REG_RD_RESP_PKT_TH, 0x05);
-+}
-+
-+static void _InitRFType(PADAPTER padapter)
-+{
-+	struct registry_priv *pregpriv = &padapter->registrypriv;
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+
-+#if	DISABLE_BB_RF
-+	pHalData->rf_chip	= RF_PSEUDO_11N;
-+	return;
-+#endif
-+	pHalData->rf_chip	= RF_6052;
-+
-+	RTW_INFO("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
-+}
-+
-+/* Set CCK and OFDM Block "ON" */
-+#if 0
-+static void _BBTurnOnBlock(PADAPTER padapter)
-+{
-+#if (DISABLE_BB_RF)
-+	return;
-+#endif
-+
-+	phy_set_bb_reg(padapter, rFPGA0_RFMOD, bCCKEn, 0x1);
-+	phy_set_bb_reg(padapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
-+}
-+#endif
-+
-+void _InitBBRegBackup_8703BS(PADAPTER	Adapter)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+
-+	/* For Channel 1~11 (Default Value)*/
-+	pHalData->RegForRecover[0].offset = rCCK0_TxFilter2;
-+	pHalData->RegForRecover[0].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[0].offset, bMaskDWord);
-+
-+	pHalData->RegForRecover[1].offset = rCCK0_DebugPort;
-+	pHalData->RegForRecover[1].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[1].offset, bMaskDWord);
-+
-+	/* For 20 MHz	(Default Value)*/
-+	pHalData->RegForRecover[2].offset = rBBrx_DFIR;
-+	pHalData->RegForRecover[2].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[2].offset, bMaskDWord);
-+
-+	pHalData->RegForRecover[3].offset = rOFDM0_XATxAFE;
-+	pHalData->RegForRecover[3].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[3].offset, bMaskDWord);
-+
-+	pHalData->RegForRecover[4].offset = 0x1E;
-+	pHalData->RegForRecover[4].value = phy_query_rf_reg(Adapter, RF_PATH_A, pHalData->RegForRecover[4].offset, bRFRegOffsetMask);
-+}
-+
-+/*
-+ * 2010/08/09 MH Add for power down check.
-+ *   */
-+static BOOLEAN HalDetectPwrDownMode(PADAPTER Adapter)
-+{
-+	u8 tmpvalue;
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
-+
-+
-+	EFUSE_ShadowRead(Adapter, 1, EEPROM_FEATURE_OPTION_8703B, (u32 *)&tmpvalue);
-+
-+	/* 2010/08/25 MH INF priority > PDN Efuse value. */
-+	if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
-+		pHalData->pwrdown = _TRUE;
-+	else
-+		pHalData->pwrdown = _FALSE;
-+
-+	RTW_INFO("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
-+
-+	return pHalData->pwrdown;
-+}	/* HalDetectPwrDownMode */
-+
-+static u32 rtl8703bs_hal_init(PADAPTER padapter)
-+{
-+	s32 ret;
-+	PHAL_DATA_TYPE pHalData;
-+	struct pwrctrl_priv *pwrctrlpriv;
-+	struct registry_priv *pregistrypriv;
-+	struct sreset_priv *psrtpriv;
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+	rt_rf_power_state eRfPowerStateToSet;
-+	u32 NavUpper = WiFiNavUpperUs;
-+	u8 u1bTmp;
-+	u16 value16;
-+	u8 typeid;
-+	u32 u4Tmp;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	psrtpriv = &pHalData->srestpriv;
-+	pwrctrlpriv = adapter_to_pwrctl(padapter);
-+	pregistrypriv = &padapter->registrypriv;
-+
-+#ifdef CONFIG_SWLPS_IN_IPS
-+	if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE) {
-+		u8 val8, bMacPwrCtrlOn = _TRUE;
-+
-+		RTW_INFO("%s: run LPS flow in IPS\n", __FUNCTION__);
-+
-+		/* ser rpwm */
-+		val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
-+		val8 &= 0x80;
-+		val8 += 0x80;
-+		val8 |= BIT(6);
-+		rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
-+
-+		adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
-+
-+		rtw_mdelay_os(5); /* wait set rpwm already */
-+
-+		ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_leave_swlps_flow);
-+		if (ret == _FALSE) {
-+			RTW_INFO("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
-+			return _FAIL;
-+		}
-+
-+		rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+
-+		pHalData->LastHMEBoxNum = 0;
-+
-+#ifdef CONFIG_BT_COEXIST
-+		rtw_btcoex_HAL_Initialize(padapter, _FALSE);
-+#else
-+		rtw_btcoex_HAL_Initialize(padapter, _TRUE);
-+#endif /* CONFIG_BT_COEXIST */
-+
-+		return _SUCCESS;
-+	}
-+#elif defined(CONFIG_FWLPS_IN_IPS)
-+	if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE
-+	    && adapter_to_pwrctl(padapter)->pre_ips_type == 0) {
-+		systime start_time;
-+		u8 cpwm_orig, cpwm_now;
-+		u8 val8, bMacPwrCtrlOn = _TRUE;
-+
-+		RTW_INFO("%s: Leaving IPS in FWLPS state\n", __FUNCTION__);
-+
-+		/* for polling cpwm */
-+		cpwm_orig = 0;
-+		rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
-+
-+		/* ser rpwm */
-+		val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
-+		val8 &= 0x80;
-+		val8 += 0x80;
-+		val8 |= BIT(6);
-+		rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
-+		RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
-+		adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
-+
-+		/* do polling cpwm */
-+		start_time = rtw_get_current_time();
-+		do {
-+
-+			rtw_mdelay_os(1);
-+
-+			rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
-+			if ((cpwm_orig ^ cpwm_now) & 0x80) {
-+#ifdef DBG_CHECK_FW_PS_STATE
-+				RTW_INFO("%s: polling cpwm ok when leaving IPS in FWLPS state, cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x\n"
-+					, __FUNCTION__, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR));
-+#endif /* DBG_CHECK_FW_PS_STATE */
-+				break;
-+			}
-+
-+			if (rtw_get_passing_time_ms(start_time) > 100) {
-+				RTW_INFO("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __FUNCTION__);
-+				break;
-+			}
-+		} while (1);
-+
-+		rtl8703b_set_FwPwrModeInIPS_cmd(padapter, 0);
-+
-+		rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+
-+#ifdef CONFIG_BT_COEXIST
-+		rtw_btcoex_HAL_Initialize(padapter, _FALSE);
-+#else
-+		rtw_btcoex_HAL_Initialize(padapter, _TRUE);
-+#endif /* CONFIG_BT_COEXIST */
-+
-+#ifdef DBG_CHECK_FW_PS_STATE
-+		if (rtw_fw_ps_state(padapter) == _FAIL) {
-+			RTW_INFO("after hal init, fw ps state in 32k\n");
-+			pdbgpriv->dbg_ips_drvopen_fail_cnt++;
-+		}
-+#endif /* DBG_CHECK_FW_PS_STATE */
-+		return _SUCCESS;
-+	}
-+#endif /* CONFIG_SWLPS_IN_IPS */
-+
-+	/* Disable Interrupt first.
-+	*	rtw_hal_disable_interrupt(padapter); */
-+
-+	if (rtw_read8(padapter, REG_MCUFWDL) == 0xc6)
-+		RTW_INFO("FW exist before power on!!\n");
-+	else
-+		RTW_INFO("FW does not exist before power on!!\n");
-+#ifdef DBG_CHECK_FW_PS_STATE
-+	if (rtw_fw_ps_state(padapter) == _FAIL) {
-+		RTW_INFO("check fw_ps_state fail before PowerOn!\n");
-+		pdbgpriv->dbg_ips_drvopen_fail_cnt++;
-+	}
-+#endif
-+	ret = rtw_hal_power_on(padapter);
-+	if (_FAIL == ret) {
-+		return _FAIL;
-+	}
-+	RTW_INFO("Power on ok!\n");
-+#ifdef DBG_CHECK_FW_PS_STATE
-+	if (rtw_fw_ps_state(padapter) == _FAIL) {
-+		RTW_INFO("check fw_ps_state fail after PowerOn!\n");
-+		pdbgpriv->dbg_ips_drvopen_fail_cnt++;
-+	}
-+#endif
-+
-+	rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
-+
-+	if (padapter->registrypriv.mp_mode == 0) {
-+		ret = rtl8703b_FirmwareDownload(padapter, _FALSE);
-+		if (ret != _SUCCESS) {
-+			pHalData->bFWReady = _FALSE;
-+			pHalData->fw_ractrl = _FALSE;
-+			return ret;
-+		} else {
-+			pHalData->bFWReady = _TRUE;
-+			pHalData->fw_ractrl = _TRUE;
-+		}
-+	}
-+
-+	/*	SIC_Init(padapter); */
-+
-+	if (pwrctrlpriv->reg_rfoff == _TRUE)
-+		pwrctrlpriv->rf_pwrstate = rf_off;
-+
-+	/* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
-+	/* HW GPIO pin. Before PHY_RFConfig8192C. */
-+	HalDetectPwrDownMode(padapter);
-+
-+	/* Set RF type for BB/RF configuration */
-+	_InitRFType(padapter);
-+
-+	/* Save target channel */
-+	/* <Roger_Notes> Current Channel will be updated again later. */
-+	pHalData->current_channel = 6;
-+
-+#if (HAL_MAC_ENABLE == 1)
-+	ret = PHY_MACConfig8703B(padapter);
-+	if (ret != _SUCCESS) {
-+		return ret;
-+	}
-+#endif
-+	/*  */
-+	/* d. Initialize BB related configurations. */
-+	/*  */
-+#if (HAL_BB_ENABLE == 1)
-+	ret = PHY_BBConfig8703B(padapter);
-+	if (ret != _SUCCESS) {
-+		return ret;
-+	}
-+
-+#endif
-+
-+	/* If RF is on, we need to init RF. Otherwise, skip the procedure. */
-+	/* We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */
-+	/* if(pHalData->eRFPowerState == eRfOn) */
-+	{
-+#if (HAL_RF_ENABLE == 1)
-+		ret = PHY_RFConfig8703B(padapter);
-+		if (ret != _SUCCESS) {
-+			return ret;
-+		}
-+#endif
-+	}
-+
-+	_InitBBRegBackup_8703BS(padapter);
-+
-+	_InitMacAPLLSetting_8703B(padapter);
-+
-+	/*  */
-+	/* Joseph Note: Keep RfRegChnlVal for later use. */
-+	/*  */
-+	pHalData->RfRegChnlVal[0] = phy_query_rf_reg(padapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
-+	pHalData->RfRegChnlVal[1] = phy_query_rf_reg(padapter, RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask);
-+
-+#if 0
-+	/* Specially add for FWDL by Tx pkt write. Reset Tx/Rx DMA since the Tx boundary setting
-+		is changed during FW download */
-+	rtw_write8(padapter, REG_CR, 0x00);
-+	rtw_write8(padapter, REG_CR, 0xFF);
-+#endif
-+
-+	/* if (!pHalData->bMACFuncEnable) { */
-+	_InitQueueReservedPage(padapter);
-+	_InitTxBufferBoundary(padapter);
-+
-+	/* init LLT after tx buffer boundary is defined */
-+	ret = rtl8703b_InitLLTTable(padapter);
-+	if (_SUCCESS != ret) {
-+		RTW_INFO("%s: Failed to init LLT Table!\n", __FUNCTION__);
-+		return _FAIL;
-+	}
-+	/* } */
-+	_InitQueuePriority(padapter);
-+	_InitPageBoundary(padapter);
-+	_InitTransferPageSize(padapter);
-+
-+	/* Get Rx PHY status in order to report RSSI and others. */
-+	_InitDriverInfoSize(padapter, DRVINFO_SZ);
-+	_InitNetworkType(padapter);
-+	_InitWMACSetting(padapter);
-+	_InitAdaptiveCtrl(padapter);
-+	_InitEDCA(padapter);
-+	_InitRetryFunction(padapter);
-+	_initSdioAggregationSetting(padapter);
-+
-+	rtl8703b_InitBeaconParameters(padapter);
-+	rtl8703b_InitBeaconMaxError(padapter, _TRUE);
-+	_InitInterrupt(padapter);
-+	_InitBurstPktLen_8703BS(padapter);
-+
-+#if 0
-+	/* 8703B new ADD */
-+	_InitLTECoex_8703BS(padapter);
-+#endif
-+
-+	/* YJ,TODO */
-+	rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8703B, 0x3);	/* CCA */
-+	rtw_write8(padapter, 0x976, 0);	/* hpfan_todo: 2nd CCA related */
-+
-+	invalidate_cam_all(padapter);
-+
-+	rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
-+		CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
-+
-+	rtl8703b_InitAntenna_Selection(padapter);
-+
-+	/*  */
-+	/* Disable BAR, suggested by Scott */
-+	/* 2010.04.09 add by hpfan */
-+	/*  */
-+	rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
-+
-+	/* HW SEQ CTRL */
-+	/* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
-+	rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
-+
-+
-+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
-+	u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN);
-+	u1bTmp &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
-+	rtw_write8(padapter, REG_SYS_FUNC_EN, u1bTmp);
-+
-+	rtw_write8(padapter, REG_RD_CTRL, 0x0F);
-+	rtw_write8(padapter, REG_RD_CTRL + 1, 0xCF);
-+	rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, 0x80);
-+	rtw_write32(padapter, REG_CR, 0x0b0202ff);
-+#endif
-+
-+	/*  */
-+	/* Configure SDIO TxRx Control to enable Rx DMA timer masking. */
-+	/* 2010.02.24. */
-+	/*  */
-+	rtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, 0);
-+
-+
-+	rtl8703b_InitHalDm(padapter);
-+
-+	/* dbg_print("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm); */
-+
-+	/* if(pHalData->SwBeaconType < HAL92CSDIO_DEFAULT_BEACON_TYPE) */ /* The lowest Beacon Type that HW can support */
-+	/*		pHalData->SwBeaconType = HAL92CSDIO_DEFAULT_BEACON_TYPE; */
-+
-+	/*  */
-+	/* Update current Tx FIFO page status. */
-+	/*  */
-+	HalQueryTxBufferStatus8703BSdio(padapter);
-+	HalQueryTxOQTBufferStatus8703BSdio(padapter);
-+	pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
-+
-+	/* Enable MACTXEN/MACRXEN block */
-+	u1bTmp = rtw_read8(padapter, REG_CR);
-+	u1bTmp |= (MACTXEN | MACRXEN);
-+	rtw_write8(padapter, REG_CR, u1bTmp);
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
-+
-+#ifdef CONFIG_XMIT_ACK
-+	/* ack for xmit mgmt frames. */
-+	rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12));
-+#endif /* CONFIG_XMIT_ACK	 */
-+
-+	/*	pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */
-+
-+#if (MP_DRIVER == 1)
-+	if (padapter->registrypriv.mp_mode == 1) {
-+		padapter->mppriv.channel = pHalData->current_channel;
-+		MPT_InitializeAdapter(padapter, padapter->mppriv.channel);
-+	} else
-+#endif /* #if (MP_DRIVER == 1) */
-+	{
-+		pwrctrlpriv->rf_pwrstate = rf_on;
-+
-+		/*phy_lc_calibrate_8703b(&pHalData->odmpriv);*/
-+		halrf_lck_trigger(&pHalData->odmpriv);
-+
-+		pHalData->neediqk_24g = _TRUE;
-+
-+		odm_txpowertracking_check(&pHalData->odmpriv);
-+	}
-+
-+#ifdef CONFIG_BT_COEXIST
-+	/* Init BT hw config.*/
-+	if (padapter->registrypriv.mp_mode == 1)
-+		rtw_btcoex_HAL_Initialize(padapter, _TRUE);
-+	else
-+		rtw_btcoex_HAL_Initialize(padapter, _FALSE);
-+#endif
-+
-+
-+	return _SUCCESS;
-+}
-+
-+static void CardDisableRTL8703BSdio(PADAPTER padapter)
-+{
-+	u8		u1bTmp;
-+	u16		u2bTmp;
-+	u32		u4bTmp;
-+	u8		bMacPwrCtrlOn;
-+	u8		ret = _FAIL;
-+
-+	/* Run LPS WL RFOFF flow */
-+	ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_enter_lps_flow);
-+	if (ret == _FAIL)
-+		RTW_ERR("%s: run RF OFF flow fail!\n", __func__);
-+
-+	/*	==== Reset digital sequence   ====== */
-+
-+	u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
-+	if ((u1bTmp & RAM_DL_SEL) && GET_HAL_DATA(padapter)->bFWReady) /* 8051 RAM code */
-+		rtl8703b_FirmwareSelfReset(padapter);
-+
-+	/* Reset MCU 0x2[10]=0. Suggested by Filen. 2011.01.26. by tynli. */
-+	u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
-+	u1bTmp &= ~BIT(2);	/* 0x2[10], FEN_CPUEN */
-+	rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp);
-+
-+	/* MCUFWDL 0x80[1:0]=0 */
-+	/* reset MCU ready status */
-+	rtw_write8(padapter, REG_MCUFWDL, 0);
-+
-+	/* Reset MCU IO Wrapper, added by Roger, 2011.08.30 */
-+	u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
-+	u1bTmp &= ~BIT(0);
-+	rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
-+	u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
-+	u1bTmp |= BIT(0);
-+	rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
-+
-+	/*	==== Reset digital sequence end ====== */
-+
-+	bMacPwrCtrlOn = _FALSE;	/* Disable CMD53 R/W */
-+	ret = _FALSE;
-+	rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+	ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_card_disable_flow);
-+	if (ret == _FALSE)
-+		RTW_ERR("%s: run CARD DISABLE flow fail!\n", __func__);
-+
-+	GET_HAL_DATA(padapter)->bFWReady = _FALSE;
-+}
-+
-+static u32 rtl8703bs_hal_deinit(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	if (padapter->registrypriv.mp_mode == 1)
-+		MPT_DeInitAdapter(padapter);
-+#endif
-+
-+	if (rtw_is_hw_init_completed(padapter)) {
-+#ifdef CONFIG_SWLPS_IN_IPS
-+		if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE) {
-+			u8	bMacPwrCtrlOn;
-+			u8 ret =  _TRUE;
-+
-+			RTW_INFO("%s: run LPS flow in IPS\n", __FUNCTION__);
-+
-+			rtw_write32(padapter, 0x130, 0x0);
-+			rtw_write32(padapter, 0x138, 0x100);
-+			rtw_write8(padapter, 0x13d, 0x1);
-+
-+
-+			bMacPwrCtrlOn = _FALSE;	/* Disable CMD53 R/W	 */
-+			rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+
-+			ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_enter_swlps_flow);
-+			if (ret == _FALSE) {
-+				RTW_INFO("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
-+				return _FAIL;
-+			}
-+		} else
-+#elif defined(CONFIG_FWLPS_IN_IPS)
-+		if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE) {
-+			if (padapter->netif_up == _TRUE) {
-+				int cnt = 0;
-+				u8 val8 = 0;
-+
-+				RTW_INFO("%s: issue H2C to FW when entering IPS\n", __FUNCTION__);
-+
-+				rtl8703b_set_FwPwrModeInIPS_cmd(padapter, 0x1);
-+				/* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */
-+				do {
-+					val8 = rtw_read8(padapter, REG_HMETFR);
-+					cnt++;
-+					RTW_INFO("%s  polling REG_HMETFR=0x%x, cnt=%d\n", __FUNCTION__, val8, cnt);
-+					rtw_mdelay_os(10);
-+				} while (cnt < 100 && (val8 != 0));
-+				/* H2C done, enter 32k */
-+				if (val8 == 0) {
-+					/* ser rpwm to enter 32k */
-+					val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
-+					val8 += 0x80;
-+					val8 |= BIT(0);
-+					rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
-+					RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
-+					adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
-+					cnt = val8 = 0;
-+					do {
-+						val8 = rtw_read8(padapter, REG_CR);
-+						cnt++;
-+						RTW_INFO("%s  polling 0x100=0x%x, cnt=%d\n", __FUNCTION__, val8, cnt);
-+						rtw_mdelay_os(10);
-+					} while (cnt < 100 && (val8 != 0xEA));
-+#ifdef DBG_CHECK_FW_PS_STATE
-+					if (val8 != 0xEA)
-+						RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
-+							, rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
-+#endif /* DBG_CHECK_FW_PS_STATE */
-+				} else {
-+					RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
-+						, rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
-+				}
-+
-+				RTW_INFO("polling done when entering IPS, check result : 0x100=0x%x, cnt=%d, MAC_1cc=0x%02x\n"
-+					, rtw_read8(padapter, REG_CR), cnt, rtw_read8(padapter, REG_HMETFR));
-+
-+				adapter_to_pwrctl(padapter)->pre_ips_type = 0;
-+
-+			} else {
-+				pdbgpriv->dbg_carddisable_cnt++;
-+#ifdef DBG_CHECK_FW_PS_STATE
-+				if (rtw_fw_ps_state(padapter) == _FAIL) {
-+					RTW_INFO("card disable should leave 32k\n");
-+					pdbgpriv->dbg_carddisable_error_cnt++;
-+				}
-+#endif /* DBG_CHECK_FW_PS_STATE */
-+				rtw_hal_power_off(padapter);
-+
-+				adapter_to_pwrctl(padapter)->pre_ips_type = 1;
-+			}
-+
-+		} else
-+#endif /* CONFIG_SWLPS_IN_IPS */
-+		{
-+			pdbgpriv->dbg_carddisable_cnt++;
-+#ifdef DBG_CHECK_FW_PS_STATE
-+			if (rtw_fw_ps_state(padapter) == _FAIL) {
-+				RTW_INFO("card disable should leave 32k\n");
-+				pdbgpriv->dbg_carddisable_error_cnt++;
-+			}
-+#endif /* DBG_CHECK_FW_PS_STATE */
-+			rtw_hal_power_off(padapter);
-+		}
-+	} else
-+		pdbgpriv->dbg_deinit_fail_cnt++;
-+
-+	return _SUCCESS;
-+}
-+static void rtl8703bs_init_default_value(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	rtl8703b_init_default_value(padapter);
-+
-+	/* interface related variable */
-+	pHalData->SdioRxFIFOCnt = 0;
-+}
-+
-+static void rtl8703bs_interface_configure(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
-+	struct dvobj_priv		*pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+	BOOLEAN		bWiFiConfig	= pregistrypriv->wifi_spec;
-+
-+
-+	pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
-+	pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
-+	pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
-+
-+	if (bWiFiConfig)
-+		pHalData->OutEpNumber = 2;
-+	else
-+		pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
-+
-+	switch (pHalData->OutEpNumber) {
-+	case 3:
-+		pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
-+		break;
-+	case 2:
-+		pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
-+		break;
-+	case 1:
-+		pHalData->OutEpQueueSel = TX_SELE_HQ;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
-+}
-+
-+/*
-+ *	Description:
-+ *		We should set Efuse cell selection to WiFi cell in default.
-+ *
-+ *	Assumption:
-+ *		PASSIVE_LEVEL
-+ *
-+ *	Added by Roger, 2010.11.23.
-+ *   */
-+static void
-+_EfuseCellSel(
-+		PADAPTER	padapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	u32			value32;
-+
-+	/* if(INCLUDE_MULTI_FUNC_BT(padapter)) */
-+	{
-+		value32 = rtw_read32(padapter, EFUSE_TEST);
-+		value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
-+		rtw_write32(padapter, EFUSE_TEST, value32);
-+	}
-+}
-+
-+static void
-+_ReadRFType(
-+		PADAPTER	Adapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+
-+#if DISABLE_BB_RF
-+	pHalData->rf_chip = RF_PSEUDO_11N;
-+#else
-+	pHalData->rf_chip = RF_6052;
-+#endif
-+}
-+
-+static u8
-+_ReadEfuseInfo8703BS(
-+		PADAPTER			padapter
-+)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+	u8			*hwinfo = NULL;
-+	u8 ret = _FAIL;
-+
-+	/*  */
-+	/* This part read and parse the eeprom/efuse content */
-+	/*  */
-+
-+	if (sizeof(pHalData->efuse_eeprom_data) < HWSET_MAX_SIZE_8703B)
-+		RTW_INFO("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8703B!\n");
-+
-+	hwinfo = pHalData->efuse_eeprom_data;
-+
-+	Hal_InitPGData(padapter, hwinfo);
-+
-+	Hal_EfuseParseIDCode(padapter, hwinfo);
-+	Hal_EfuseParseEEPROMVer_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
-+	hal_config_macaddr(padapter, pHalData->bautoload_fail_flag);
-+	Hal_EfuseParseTxPowerInfo_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
-+	Hal_EfuseParseBoardType_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
-+
-+	/*  */
-+	/* Read Bluetooth co-exist and initialize */
-+	/*  */
-+	Hal_EfuseParseBTCoexistInfo_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
-+	Hal_EfuseParseChnlPlan_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
-+	Hal_EfuseParseXtal_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
-+	Hal_EfuseParseThermalMeter_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
-+	Hal_EfuseParseAntennaDiversity_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
-+	Hal_EfuseParseCustomerID_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
-+
-+	Hal_EfuseParseVoltage_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
-+
-+#ifdef CONFIG_WOWLAN
-+	Hal_DetectWoWMode(padapter);
-+#endif
-+
-+	Hal_ReadRFGainOffset(padapter, hwinfo, pHalData->bautoload_fail_flag);
-+
-+	/* set coex. ant info once efuse parsing is done */
-+	rtw_btcoex_set_ant_info(padapter);
-+
-+	if (hal_read_mac_hidden_rpt(padapter) != _SUCCESS)
-+		goto exit;
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+static u8 _ReadPROMContent(
-+		PADAPTER		padapter
-+)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+	u8			eeValue;
-+	u8 ret = _FAIL;
-+
-+	eeValue = rtw_read8(padapter, REG_9346CR);
-+	/* To check system boot selection. */
-+	pHalData->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
-+	pHalData->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
-+
-+
-+	/*	pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */
-+
-+	if (_ReadEfuseInfo8703BS(padapter) != _SUCCESS)
-+		goto exit;
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+static void
-+_InitOtherVariable(
-+		PADAPTER		Adapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+
-+
-+	/* if(Adapter->bInHctTest){ */
-+	/*	pMgntInfo->PowerSaveControl.bInactivePs = FALSE; */
-+	/*	pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE; */
-+	/*	pMgntInfo->PowerSaveControl.bLeisurePs = FALSE; */
-+	/*	pMgntInfo->keepAliveLevel = 0; */
-+	/* } */
-+
-+
-+
-+}
-+
-+/*
-+ *	Description:
-+ *		Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
-+ *
-+ *	Assumption:
-+ *		PASSIVE_LEVEL (SDIO interface)
-+ *
-+ *   */
-+static u8 ReadAdapterInfo8703BS(PADAPTER padapter)
-+{
-+	u8 ret = _FAIL;
-+	u8 val8;
-+
-+	val8 = rtw_read8(padapter, 0x4e);
-+	RTW_INFO("%s, 0x4e=0x%x\n", __func__, val8);
-+	val8 |= BIT(6);
-+	rtw_write8(padapter, 0x4e, val8);
-+
-+	/* Read EEPROM size before call any EEPROM function */
-+	padapter->EepromAddressSize = GetEEPROMSize8703B(padapter);
-+
-+	_EfuseCellSel(padapter);
-+	_ReadRFType(padapter);
-+	if (_ReadPROMContent(padapter) != _SUCCESS)
-+		goto exit;
-+
-+	_InitOtherVariable(padapter);
-+
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+	{ /* for BT, let BT can control ANT when wifi disable */
-+		u32 val32;
-+		RTW_INFO("%s, 0x4c=0x%x\n", __func__, rtw_read32(padapter, 0x4c));
-+		val32 = rtw_read32(padapter, 0x64);
-+		RTW_INFO("%s, 0x64=0x%x\n", __func__, val32);
-+		val32 |= BIT(13);
-+		rtw_write32(padapter, 0x64, val32);
-+		RTW_INFO("%s, 0x64=0x%x\n", __func__, rtw_read32(padapter, 0x64));
-+	}
-+#endif /* CONFIG_PLATFORM_INTEL_BYT */
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+/*
-+ * If variable not handled here,
-+ * some variables will be processed in SetHwReg8703B()
-+ */
-+u8 SetHwReg8703BS(PADAPTER padapter, u8 variable, u8 *val)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+	u8 ret = _SUCCESS;
-+	u8 val8;
-+
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	switch (variable) {
-+	case HW_VAR_SET_RPWM:
-+		/* rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) */
-+		/* BIT0 value - 1: 32k, 0:40MHz. */
-+		/* BIT6 value - 1: report cpwm value after success set, 0:do not report. */
-+		/* BIT7 value - Toggle bit change. */
-+	{
-+		val8 = *val;
-+		val8 &= 0xC1;
-+		rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
-+	}
-+	break;
-+	case HW_VAR_SET_REQ_FW_PS:
-+	/* 1. driver write 0x8f[4]=1  */ { /* request fw ps state (only can write bit4) */
-+		u8 req_fw_ps = 0;
-+		req_fw_ps = rtw_read8(padapter, 0x8f);
-+		req_fw_ps |= 0x10;
-+		rtw_write8(padapter, 0x8f, req_fw_ps);
-+	}
-+	break;
-+	case HW_VAR_RXDMA_AGG_PG_TH:
-+		#if 0
-+		val8 = *val;
-+
-+		/* TH=1 => invalidate RX DMA aggregation */
-+		/* TH=0 => validate RX DMA aggregation, use init value. */
-+		if (val8 == 0) {
-+			/* enable RXDMA aggregation */
-+			/* _RXAggrSwitch(padapter, _TRUE); */
-+		} else {
-+			/* disable RXDMA aggregation */
-+			/* _RXAggrSwitch(padapter, _FALSE); */
-+		}
-+		#endif
-+		break;
-+	default:
-+		ret = SetHwReg8703B(padapter, variable, val);
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+/*
-+ * If variable not handled here,
-+ * some variables will be processed in GetHwReg8703B()
-+ */
-+void GetHwReg8703BS(PADAPTER padapter, u8 variable, u8 *val)
-+{
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+
-+
-+	switch (variable) {
-+	case HW_VAR_CPWM:
-+		*val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8703B);
-+		break;
-+
-+	case HW_VAR_FW_PS_STATE: {
-+		/* 3. read dword 0x88               */ /* driver read fw ps state */
-+		*((u16 *)val) = rtw_read16(padapter, 0x88);
-+	}
-+	break;
-+	default:
-+		GetHwReg8703B(padapter, variable, val);
-+		break;
-+	}
-+
-+}
-+
-+/*
-+ *	Description:
-+ *		Query setting of specified variable.
-+ *   */
-+u8
-+GetHalDefVar8703BSDIO(
-+		PADAPTER				Adapter,
-+		HAL_DEF_VARIABLE		eVariable,
-+		void						*pValue
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
-+	u8			bResult = _SUCCESS;
-+
-+	switch (eVariable) {
-+	case HAL_DEF_IS_SUPPORT_ANT_DIV:
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+		*((u8 *)pValue) = _FALSE;
-+#endif
-+		break;
-+
-+	case HW_VAR_MAX_RX_AMPDU_FACTOR:
-+		/* Stanley@BB.SD3 suggests 16K can get stable performance */
-+		/* coding by Lucas@20130730 */
-+		*(HT_CAP_AMPDU_FACTOR *)pValue = MAX_AMPDU_FACTOR_16K;
-+		break;
-+	default:
-+		bResult = GetHalDefVar8703B(Adapter, eVariable, pValue);
-+		break;
-+	}
-+
-+	return bResult;
-+}
-+
-+/*
-+ *	Description:
-+ *		Change default setting of specified variable.
-+ *   */
-+u8
-+SetHalDefVar8703BSDIO(
-+		PADAPTER				Adapter,
-+		HAL_DEF_VARIABLE		eVariable,
-+		void						*pValue
-+)
-+{
-+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
-+	u8			bResult = _SUCCESS;
-+
-+	switch (eVariable) {
-+	default:
-+		bResult = SetHalDefVar8703B(Adapter, eVariable, pValue);
-+		break;
-+	}
-+
-+	return bResult;
-+}
-+
-+void rtl8703bs_set_hal_ops(PADAPTER padapter)
-+{
-+	struct hal_ops *pHalFunc = &padapter->hal_func;
-+
-+
-+	rtl8703b_set_hal_ops(pHalFunc);
-+
-+	pHalFunc->hal_power_on = &_InitPowerOn_8703BS;
-+	pHalFunc->hal_power_off = &CardDisableRTL8703BSdio;
-+
-+
-+	pHalFunc->hal_init = &rtl8703bs_hal_init;
-+	pHalFunc->hal_deinit = &rtl8703bs_hal_deinit;
-+
-+	pHalFunc->init_xmit_priv = &rtl8703bs_init_xmit_priv;
-+	pHalFunc->free_xmit_priv = &rtl8703bs_free_xmit_priv;
-+
-+	pHalFunc->init_recv_priv = &rtl8703bs_init_recv_priv;
-+	pHalFunc->free_recv_priv = &rtl8703bs_free_recv_priv;
-+#ifdef CONFIG_RECV_THREAD_MODE 
-+		pHalFunc->recv_hdl = rtl8703bs_recv_hdl;
-+#endif /* CONFIG_RECV_THREAD_MODE */	
-+#ifdef CONFIG_RTW_SW_LED
-+	pHalFunc->InitSwLeds = &rtl8703bs_InitSwLeds;
-+	pHalFunc->DeInitSwLeds = &rtl8703bs_DeInitSwLeds;
-+#endif
-+	pHalFunc->init_default_value = &rtl8703bs_init_default_value;
-+	pHalFunc->intf_chip_configure = &rtl8703bs_interface_configure;
-+	pHalFunc->read_adapter_info = &ReadAdapterInfo8703BS;
-+
-+	pHalFunc->enable_interrupt = &EnableInterrupt8703BSdio;
-+	pHalFunc->disable_interrupt = &DisableInterrupt8703BSdio;
-+	pHalFunc->check_ips_status = &CheckIPSStatus;
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+	pHalFunc->clear_interrupt = &ClearInterrupt8703BSdio;
-+#endif
-+	pHalFunc->set_hw_reg_handler = &SetHwReg8703BS;
-+	pHalFunc->GetHwRegHandler = &GetHwReg8703BS;
-+	pHalFunc->get_hal_def_var_handler = &GetHalDefVar8703BSDIO;
-+	pHalFunc->SetHalDefVarHandler = &SetHalDefVar8703BSDIO;
-+
-+	pHalFunc->hal_xmit = &rtl8703bs_hal_xmit;
-+	pHalFunc->mgnt_xmit = &rtl8703bs_mgnt_xmit;
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	pHalFunc->hal_mgmt_xmitframe_enqueue = &rtl8703bs_hal_mgmt_xmitframe_enqueue;
-+#endif
-+	pHalFunc->hal_xmitframe_enqueue = &rtl8703bs_hal_xmitframe_enqueue;
-+
-+#ifdef CONFIG_HOSTAPD_MLME
-+	pHalFunc->hostap_mgnt_xmit_entry = NULL;
-+#endif
-+
-+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
-+	pHalFunc->hal_init_checkbthang_workqueue = &rtl8703bs_init_checkbthang_workqueue;
-+	pHalFunc->hal_free_checkbthang_workqueue = &rtl8703bs_free_checkbthang_workqueue;
-+	pHalFunc->hal_cancle_checkbthang_workqueue = &rtl8703bs_cancle_checkbthang_workqueue;
-+	pHalFunc->hal_checke_bt_hang = &rtl8703bs_hal_check_bt_hang;
-+#endif
-+
-+}
-diff --git a/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/sdio_ops.c b/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/sdio_ops.c
-new file mode 100644
-index 000000000000..0f8cfb856473
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/hal/rtl8703b/sdio/sdio_ops.c
-@@ -0,0 +1,1669 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _SDIO_OPS_C_
-+
-+#include <rtl8703b_hal.h>
-+
-+/* #define SDIO_DEBUG_IO 1 */
-+
-+
-+/*
-+ * Description:
-+ *	The following mapping is for SDIO host local register space.
-+ *
-+ * Creadted by Roger, 2011.01.31.
-+ *   */
-+static void HalSdioGetCmdAddr8703BSdio(
-+		PADAPTER			padapter,
-+		u8				DeviceID,
-+		u32				Addr,
-+		u32				*pCmdAddr
-+)
-+{
-+	switch (DeviceID) {
-+	case SDIO_LOCAL_DEVICE_ID:
-+		*pCmdAddr = ((SDIO_LOCAL_DEVICE_ID << 13) | (Addr & SDIO_LOCAL_MSK));
-+		break;
-+
-+	case WLAN_IOREG_DEVICE_ID:
-+		*pCmdAddr = ((WLAN_IOREG_DEVICE_ID << 13) | (Addr & WLAN_IOREG_MSK));
-+		break;
-+
-+	case WLAN_TX_HIQ_DEVICE_ID:
-+		*pCmdAddr = ((WLAN_TX_HIQ_DEVICE_ID << 13) | (Addr & WLAN_FIFO_MSK));
-+		break;
-+
-+	case WLAN_TX_MIQ_DEVICE_ID:
-+		*pCmdAddr = ((WLAN_TX_MIQ_DEVICE_ID << 13) | (Addr & WLAN_FIFO_MSK));
-+		break;
-+
-+	case WLAN_TX_LOQ_DEVICE_ID:
-+		*pCmdAddr = ((WLAN_TX_LOQ_DEVICE_ID << 13) | (Addr & WLAN_FIFO_MSK));
-+		break;
-+
-+	case WLAN_RX0FF_DEVICE_ID:
-+		*pCmdAddr = ((WLAN_RX0FF_DEVICE_ID << 13) | (Addr & WLAN_RX0FF_MSK));
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+static u8 get_deviceid(u32 addr)
-+{
-+	u8 devideId;
-+	u16 pseudoId;
-+
-+
-+	pseudoId = (u16)(addr >> 16);
-+	switch (pseudoId) {
-+	case 0x1025:
-+		devideId = SDIO_LOCAL_DEVICE_ID;
-+		break;
-+
-+	case 0x1026:
-+		devideId = WLAN_IOREG_DEVICE_ID;
-+		break;
-+
-+	/*		case 0x1027:
-+	 *			devideId = SDIO_FIRMWARE_FIFO;
-+	 *			break; */
-+
-+	case 0x1031:
-+		devideId = WLAN_TX_HIQ_DEVICE_ID;
-+		break;
-+
-+	case 0x1032:
-+		devideId = WLAN_TX_MIQ_DEVICE_ID;
-+		break;
-+
-+	case 0x1033:
-+		devideId = WLAN_TX_LOQ_DEVICE_ID;
-+		break;
-+
-+	case 0x1034:
-+		devideId = WLAN_RX0FF_DEVICE_ID;
-+		break;
-+
-+	default:
-+		/*			devideId = (u8)((addr >> 13) & 0xF); */
-+		devideId = WLAN_IOREG_DEVICE_ID;
-+		break;
-+	}
-+
-+	return devideId;
-+}
-+
-+/*
-+ * Ref:
-+ *	HalSdioGetCmdAddr8703BSdio()
-+ */
-+static u32 _cvrt2ftaddr(const u32 addr, u8 *pdeviceId, u16 *poffset)
-+{
-+	u8 deviceId;
-+	u16 offset;
-+	u32 ftaddr;
-+
-+
-+	deviceId = get_deviceid(addr);
-+	offset = 0;
-+
-+	switch (deviceId) {
-+	case SDIO_LOCAL_DEVICE_ID:
-+		offset = addr & SDIO_LOCAL_MSK;
-+		break;
-+
-+	case WLAN_TX_HIQ_DEVICE_ID:
-+	case WLAN_TX_MIQ_DEVICE_ID:
-+	case WLAN_TX_LOQ_DEVICE_ID:
-+		offset = addr & WLAN_FIFO_MSK;
-+		break;
-+
-+	case WLAN_RX0FF_DEVICE_ID:
-+		offset = addr & WLAN_RX0FF_MSK;
-+		break;
-+
-+	case WLAN_IOREG_DEVICE_ID:
-+	default:
-+		deviceId = WLAN_IOREG_DEVICE_ID;
-+		offset = addr & WLAN_IOREG_MSK;
-+		break;
-+	}
-+	ftaddr = (deviceId << 13) | offset;
-+
-+	if (pdeviceId)
-+		*pdeviceId = deviceId;
-+	if (poffset)
-+		*poffset = offset;
-+
-+	return ftaddr;
-+}
-+
-+u8 sdio_read8(struct intf_hdl *pintfhdl, u32 addr)
-+{
-+	u32 ftaddr;
-+	u8 val;
-+
-+	ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
-+	val = sd_read8(pintfhdl, ftaddr, NULL);
-+
-+
-+	return val;
-+}
-+
-+u16 sdio_read16(struct intf_hdl *pintfhdl, u32 addr)
-+{
-+	u32 ftaddr;
-+	u16 val;
-+
-+	ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
-+	val = 0;
-+	sd_cmd52_read(pintfhdl, ftaddr, 2, (u8 *)&val);
-+	val = le16_to_cpu(val);
-+
-+
-+	return val;
-+}
-+
-+u32 sdio_read32(struct intf_hdl *pintfhdl, u32 addr)
-+{
-+	PADAPTER padapter;
-+	u8 bMacPwrCtrlOn;
-+	u8 deviceId;
-+	u16 offset;
-+	u32 ftaddr;
-+	u8 shift;
-+	u32 val;
-+	s32 err;
-+
-+
-+	padapter = pintfhdl->padapter;
-+	ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset);
-+
-+	bMacPwrCtrlOn = _FALSE;
-+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+	if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100))
-+	    || (_FALSE == bMacPwrCtrlOn)
-+#ifdef CONFIG_LPS_LCLK
-+	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
-+#endif
-+	   ) {
-+		val = 0;
-+		err = sd_cmd52_read(pintfhdl, ftaddr, 4, (u8 *)&val);
-+#ifdef SDIO_DEBUG_IO
-+		if (!err) {
-+#endif
-+			val = le32_to_cpu(val);
-+			return val;
-+#ifdef SDIO_DEBUG_IO
-+		}
-+
-+		RTW_ERR("%s: Mac Power off, Read FAIL(%d)! addr=0x%x\n", __func__, err, addr);
-+		return SDIO_ERR_VAL32;
-+#endif
-+	}
-+
-+	/* 4 bytes alignment */
-+	shift = ftaddr & 0x3;
-+	if (shift == 0)
-+		val = sd_read32(pintfhdl, ftaddr, NULL);
-+	else {
-+		u8 *ptmpbuf;
-+
-+		ptmpbuf = (u8 *)rtw_malloc(8);
-+		if (NULL == ptmpbuf) {
-+			RTW_ERR("%s: Allocate memory FAIL!(size=8) addr=0x%x\n", __func__, addr);
-+			return SDIO_ERR_VAL32;
-+		}
-+
-+		ftaddr &= ~(u16)0x3;
-+		sd_read(pintfhdl, ftaddr, 8, ptmpbuf);
-+		_rtw_memcpy(&val, ptmpbuf + shift, 4);
-+		val = le32_to_cpu(val);
-+
-+		rtw_mfree(ptmpbuf, 8);
-+	}
-+
-+
-+	return val;
-+}
-+
-+s32 sdio_readN(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pbuf)
-+{
-+	PADAPTER padapter;
-+	u8 bMacPwrCtrlOn;
-+	u8 deviceId;
-+	u16 offset;
-+	u32 ftaddr;
-+	u8 shift;
-+	s32 err;
-+
-+
-+	padapter = pintfhdl->padapter;
-+	err = 0;
-+
-+	ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset);
-+
-+	bMacPwrCtrlOn = _FALSE;
-+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+	if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100))
-+	    || (_FALSE == bMacPwrCtrlOn)
-+#ifdef CONFIG_LPS_LCLK
-+	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
-+#endif
-+	   ) {
-+		err = sd_cmd52_read(pintfhdl, ftaddr, cnt, pbuf);
-+		return err;
-+	}
-+
-+	/* 4 bytes alignment */
-+	shift = ftaddr & 0x3;
-+	if (shift == 0)
-+		err = sd_read(pintfhdl, ftaddr, cnt, pbuf);
-+	else {
-+		u8 *ptmpbuf;
-+		u32 n;
-+
-+		ftaddr &= ~(u16)0x3;
-+		n = cnt + shift;
-+		ptmpbuf = rtw_malloc(n);
-+		if (NULL == ptmpbuf)
-+			return -1;
-+		err = sd_read(pintfhdl, ftaddr, n, ptmpbuf);
-+		if (!err)
-+			_rtw_memcpy(pbuf, ptmpbuf + shift, cnt);
-+		rtw_mfree(ptmpbuf, n);
-+	}
-+
-+
-+	return err;
-+}
-+
-+s32 sdio_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
-+{
-+	u32 ftaddr;
-+	s32 err;
-+
-+	ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
-+	err = 0;
-+	sd_write8(pintfhdl, ftaddr, val, &err);
-+
-+
-+	return err;
-+}
-+
-+s32 sdio_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
-+{
-+	u32 ftaddr;
-+	u8 shift;
-+	s32 err;
-+
-+	ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
-+	val = cpu_to_le16(val);
-+	err = sd_cmd52_write(pintfhdl, ftaddr, 2, (u8 *)&val);
-+
-+
-+	return err;
-+}
-+
-+s32 sdio_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
-+{
-+	PADAPTER padapter;
-+	u8 bMacPwrCtrlOn;
-+	u8 deviceId;
-+	u16 offset;
-+	u32 ftaddr;
-+	u8 shift;
-+	s32 err;
-+
-+
-+	padapter = pintfhdl->padapter;
-+	err = 0;
-+
-+	ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset);
-+
-+	bMacPwrCtrlOn = _FALSE;
-+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+	if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100))
-+	    || (_FALSE == bMacPwrCtrlOn)
-+#ifdef CONFIG_LPS_LCLK
-+	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
-+#endif
-+	   ) {
-+		val = cpu_to_le32(val);
-+		err = sd_cmd52_write(pintfhdl, ftaddr, 4, (u8 *)&val);
-+		return err;
-+	}
-+
-+	/* 4 bytes alignment */
-+	shift = ftaddr & 0x3;
-+#if 1
-+	if (shift == 0)
-+		sd_write32(pintfhdl, ftaddr, val, &err);
-+	else {
-+		val = cpu_to_le32(val);
-+		err = sd_cmd52_write(pintfhdl, ftaddr, 4, (u8 *)&val);
-+	}
-+#else
-+	if (shift == 0)
-+		sd_write32(pintfhdl, ftaddr, val, &err);
-+	else {
-+		u8 *ptmpbuf;
-+
-+		ptmpbuf = (u8 *)rtw_malloc(8);
-+		if (NULL == ptmpbuf)
-+			return -1;
-+
-+		ftaddr &= ~(u16)0x3;
-+		err = sd_read(pintfhdl, ftaddr, 8, ptmpbuf);
-+		if (err) {
-+			rtw_mfree(ptmpbuf, 8);
-+			return err;
-+		}
-+		val = cpu_to_le32(val);
-+		_rtw_memcpy(ptmpbuf + shift, &val, 4);
-+		err = sd_write(pintfhdl, ftaddr, 8, ptmpbuf);
-+
-+		rtw_mfree(ptmpbuf, 8);
-+	}
-+#endif
-+
-+
-+	return err;
-+}
-+
-+s32 sdio_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pbuf)
-+{
-+	PADAPTER padapter;
-+	u8 bMacPwrCtrlOn;
-+	u8 deviceId;
-+	u16 offset;
-+	u32 ftaddr;
-+	u8 shift;
-+	s32 err;
-+
-+
-+	padapter = pintfhdl->padapter;
-+	err = 0;
-+
-+	ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset);
-+
-+	bMacPwrCtrlOn = _FALSE;
-+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+	if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100))
-+	    || (_FALSE == bMacPwrCtrlOn)
-+#ifdef CONFIG_LPS_LCLK
-+	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
-+#endif
-+	   ) {
-+		err = sd_cmd52_write(pintfhdl, ftaddr, cnt, pbuf);
-+		return err;
-+	}
-+
-+	shift = ftaddr & 0x3;
-+	if (shift == 0)
-+		err = sd_write(pintfhdl, ftaddr, cnt, pbuf);
-+	else {
-+		u8 *ptmpbuf;
-+		u32 n;
-+
-+		ftaddr &= ~(u16)0x3;
-+		n = cnt + shift;
-+		ptmpbuf = rtw_malloc(n);
-+		if (NULL == ptmpbuf)
-+			return -1;
-+		err = sd_read(pintfhdl, ftaddr, 4, ptmpbuf);
-+		if (err) {
-+			rtw_mfree(ptmpbuf, n);
-+			return err;
-+		}
-+		_rtw_memcpy(ptmpbuf + shift, pbuf, cnt);
-+		err = sd_write(pintfhdl, ftaddr, n, ptmpbuf);
-+		rtw_mfree(ptmpbuf, n);
-+	}
-+
-+
-+	return err;
-+}
-+
-+u8 sdio_f0_read8(struct intf_hdl *pintfhdl, u32 addr)
-+{
-+	u32 ftaddr;
-+	u8 val;
-+
-+	val = sd_f0_read8(pintfhdl, addr, NULL);
-+
-+
-+	return val;
-+}
-+
-+void sdio_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
-+{
-+	s32 err;
-+
-+
-+	err = sdio_readN(pintfhdl, addr, cnt, rmem);
-+
-+}
-+
-+void sdio_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem)
-+{
-+
-+	sdio_writeN(pintfhdl, addr, cnt, wmem);
-+
-+}
-+
-+/*
-+ * Description:
-+ *	Read from RX FIFO
-+ *	Round read size to block size,
-+ *	and make sure data transfer will be done in one command.
-+ *
-+ * Parameters:
-+ *	pintfhdl	a pointer of intf_hdl
-+ *	addr		port ID
-+ *	cnt			size to read
-+ *	rmem		address to put data
-+ *
-+ * Return:
-+ *	_SUCCESS(1)		Success
-+ *	_FAIL(0)		Fail
-+ */
-+static u32 sdio_read_port(
-+	struct intf_hdl *pintfhdl,
-+	u32 addr,
-+	u32 cnt,
-+	u8 *mem)
-+{
-+	PADAPTER padapter;
-+	PHAL_DATA_TYPE phal;
-+	u32 oldcnt;
-+#ifdef SDIO_DYNAMIC_ALLOC_MEM
-+	u8 *oldmem;
-+#endif
-+	s32 err;
-+
-+
-+	padapter = pintfhdl->padapter;
-+	phal = GET_HAL_DATA(padapter);
-+
-+	HalSdioGetCmdAddr8703BSdio(padapter, addr, phal->SdioRxFIFOCnt++, &addr);
-+
-+	oldcnt = cnt;
-+	cnt = rtw_sdio_cmd53_align_size(adapter_to_dvobj(padapter), cnt);
-+
-+	if (oldcnt != cnt) {
-+#ifdef SDIO_DYNAMIC_ALLOC_MEM
-+		oldmem = mem;
-+		mem = rtw_malloc(cnt);
-+		if (mem == NULL) {
-+			RTW_WARN("%s: allocate memory %d bytes fail!\n", __func__, cnt);
-+			mem = oldmem;
-+			oldmem == NULL;
-+		}
-+#else
-+		/* in this case, caller should gurante the buffer is big enough */
-+		/* to receive data after alignment */
-+#endif
-+	}
-+
-+	err = _sd_read(pintfhdl, addr, cnt, mem);
-+
-+#ifdef SDIO_DYNAMIC_ALLOC_MEM
-+	if ((oldcnt != cnt) && (oldmem)) {
-+		_rtw_memcpy(oldmem, mem, oldcnt);
-+		rtw_mfree(mem, cnt);
-+	}
-+#endif
-+
-+	if (err)
-+		return _FAIL;
-+	return _SUCCESS;
-+}
-+
-+/*
-+ * Description:
-+ *	Write to TX FIFO
-+ *	Align write size block size,
-+ *	and make sure data could be written in one command.
-+ *
-+ * Parameters:
-+ *	pintfhdl	a pointer of intf_hdl
-+ *	addr		port ID
-+ *	cnt			size to write
-+ *	wmem		data pointer to write
-+ *
-+ * Return:
-+ *	_SUCCESS(1)		Success
-+ *	_FAIL(0)		Fail
-+ */
-+static u32 sdio_write_port(
-+	struct intf_hdl *pintfhdl,
-+	u32 addr,
-+	u32 cnt,
-+	u8 *mem)
-+{
-+	PADAPTER padapter;
-+	s32 err;
-+	struct xmit_buf *xmitbuf = (struct xmit_buf *)mem;
-+
-+	padapter = pintfhdl->padapter;
-+
-+	if (!rtw_is_hw_init_completed(padapter)) {
-+		RTW_INFO("%s [addr=0x%x cnt=%d] padapter->hw_init_completed == _FALSE\n", __func__, addr, cnt);
-+		return _FAIL;
-+	}
-+
-+	cnt = _RND4(cnt);
-+	HalSdioGetCmdAddr8703BSdio(padapter, addr, cnt >> 2, &addr);
-+
-+	cnt = rtw_sdio_cmd53_align_size(adapter_to_dvobj(padapter), cnt);
-+
-+	err = sd_write(pintfhdl, addr, cnt, xmitbuf->pdata);
-+
-+	rtw_sctx_done_err(&xmitbuf->sctx,
-+		  err ? RTW_SCTX_DONE_WRITE_PORT_ERR : RTW_SCTX_DONE_SUCCESS);
-+
-+	if (err)
-+		return _FAIL;
-+	return _SUCCESS;
-+}
-+
-+void sdio_set_intf_ops(_adapter *padapter, struct _io_ops *pops)
-+{
-+
-+	pops->_read8 = &sdio_read8;
-+	pops->_read16 = &sdio_read16;
-+	pops->_read32 = &sdio_read32;
-+	pops->_read_mem = &sdio_read_mem;
-+	pops->_read_port = &sdio_read_port;
-+
-+	pops->_write8 = &sdio_write8;
-+	pops->_write16 = &sdio_write16;
-+	pops->_write32 = &sdio_write32;
-+	pops->_writeN = &sdio_writeN;
-+	pops->_write_mem = &sdio_write_mem;
-+	pops->_write_port = &sdio_write_port;
-+
-+	pops->_sd_f0_read8 = sdio_f0_read8;
-+
-+}
-+
-+/*
-+ * Todo: align address to 4 bytes.
-+ */
-+s32 _sdio_local_read(
-+	PADAPTER	padapter,
-+	u32			addr,
-+	u32			cnt,
-+	u8			*pbuf)
-+{
-+	struct intf_hdl *pintfhdl;
-+	u8 bMacPwrCtrlOn;
-+	s32 err;
-+	u8 *ptmpbuf;
-+	u32 n;
-+
-+
-+	pintfhdl = &padapter->iopriv.intf;
-+
-+	HalSdioGetCmdAddr8703BSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
-+
-+	bMacPwrCtrlOn = _FALSE;
-+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+	if (_FALSE == bMacPwrCtrlOn) {
-+		err = _sd_cmd52_read(pintfhdl, addr, cnt, pbuf);
-+		return err;
-+	}
-+
-+	n = RND4(cnt);
-+	ptmpbuf = (u8 *)rtw_malloc(n);
-+	if (!ptmpbuf)
-+		return -1;
-+
-+	err = _sd_read(pintfhdl, addr, n, ptmpbuf);
-+	if (!err)
-+		_rtw_memcpy(pbuf, ptmpbuf, cnt);
-+
-+	if (ptmpbuf)
-+		rtw_mfree(ptmpbuf, n);
-+
-+	return err;
-+}
-+
-+/*
-+ * Todo: align address to 4 bytes.
-+ */
-+s32 sdio_local_read(
-+	PADAPTER	padapter,
-+	u32			addr,
-+	u32			cnt,
-+	u8			*pbuf)
-+{
-+	struct intf_hdl *pintfhdl;
-+	u8 bMacPwrCtrlOn;
-+	s32 err;
-+	u8 *ptmpbuf;
-+	u32 n;
-+
-+	pintfhdl = &padapter->iopriv.intf;
-+
-+	HalSdioGetCmdAddr8703BSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
-+
-+	bMacPwrCtrlOn = _FALSE;
-+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+	if ((_FALSE == bMacPwrCtrlOn)
-+#ifdef CONFIG_LPS_LCLK
-+	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
-+#endif
-+	   ) {
-+		err = sd_cmd52_read(pintfhdl, addr, cnt, pbuf);
-+		return err;
-+	}
-+
-+	n = RND4(cnt);
-+	ptmpbuf = (u8 *)rtw_malloc(n);
-+	if (!ptmpbuf)
-+		return -1;
-+
-+	err = sd_read(pintfhdl, addr, n, ptmpbuf);
-+	if (!err)
-+		_rtw_memcpy(pbuf, ptmpbuf, cnt);
-+
-+	if (ptmpbuf)
-+		rtw_mfree(ptmpbuf, n);
-+
-+	return err;
-+}
-+
-+/*
-+ * Todo: align address to 4 bytes.
-+ */
-+s32 _sdio_local_write(
-+	PADAPTER	padapter,
-+	u32			addr,
-+	u32			cnt,
-+	u8			*pbuf)
-+{
-+	struct intf_hdl *pintfhdl;
-+	u8 bMacPwrCtrlOn;
-+	s32 err;
-+	u8 *ptmpbuf;
-+
-+	if (addr & 0x3)
-+		RTW_INFO("%s, address must be 4 bytes alignment\n", __FUNCTION__);
-+
-+	if (cnt  & 0x3)
-+		RTW_INFO("%s, size must be the multiple of 4\n", __FUNCTION__);
-+
-+	pintfhdl = &padapter->iopriv.intf;
-+
-+	HalSdioGetCmdAddr8703BSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
-+
-+	bMacPwrCtrlOn = _FALSE;
-+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+	if ((_FALSE == bMacPwrCtrlOn)
-+#ifdef CONFIG_LPS_LCLK
-+	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
-+#endif
-+	   ) {
-+		err = _sd_cmd52_write(pintfhdl, addr, cnt, pbuf);
-+		return err;
-+	}
-+
-+	ptmpbuf = (u8 *)rtw_malloc(cnt);
-+	if (!ptmpbuf)
-+		return -1;
-+
-+	_rtw_memcpy(ptmpbuf, pbuf, cnt);
-+
-+	err = _sd_write(pintfhdl, addr, cnt, ptmpbuf);
-+
-+	if (ptmpbuf)
-+		rtw_mfree(ptmpbuf, cnt);
-+
-+	return err;
-+}
-+
-+/*
-+ * Todo: align address to 4 bytes.
-+ */
-+s32 sdio_local_write(
-+	PADAPTER	padapter,
-+	u32		addr,
-+	u32		cnt,
-+	u8		*pbuf)
-+{
-+	struct intf_hdl *pintfhdl;
-+	u8 bMacPwrCtrlOn;
-+	s32 err;
-+	u8 *ptmpbuf;
-+
-+	if (addr & 0x3)
-+		RTW_INFO("%s, address must be 4 bytes alignment\n", __FUNCTION__);
-+
-+	if (cnt  & 0x3)
-+		RTW_INFO("%s, size must be the multiple of 4\n", __FUNCTION__);
-+
-+	pintfhdl = &padapter->iopriv.intf;
-+
-+	HalSdioGetCmdAddr8703BSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
-+
-+	bMacPwrCtrlOn = _FALSE;
-+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+	if ((_FALSE == bMacPwrCtrlOn)
-+#ifdef CONFIG_LPS_LCLK
-+	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
-+#endif
-+	   ) {
-+		err = sd_cmd52_write(pintfhdl, addr, cnt, pbuf);
-+		return err;
-+	}
-+
-+	ptmpbuf = (u8 *)rtw_malloc(cnt);
-+	if (!ptmpbuf)
-+		return -1;
-+
-+	_rtw_memcpy(ptmpbuf, pbuf, cnt);
-+
-+	err = sd_write(pintfhdl, addr, cnt, ptmpbuf);
-+
-+	if (ptmpbuf)
-+		rtw_mfree(ptmpbuf, cnt);
-+
-+	return err;
-+}
-+
-+u8 SdioLocalCmd52Read1Byte(PADAPTER padapter, u32 addr)
-+{
-+	u8 val = 0;
-+	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
-+
-+	HalSdioGetCmdAddr8703BSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
-+	sd_cmd52_read(pintfhdl, addr, 1, &val);
-+
-+	return val;
-+}
-+
-+u16 SdioLocalCmd52Read2Byte(PADAPTER padapter, u32 addr)
-+{
-+	u16 val = 0;
-+	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
-+
-+	HalSdioGetCmdAddr8703BSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
-+	sd_cmd52_read(pintfhdl, addr, 2, (u8 *)&val);
-+
-+	val = le16_to_cpu(val);
-+
-+	return val;
-+}
-+
-+u32 SdioLocalCmd52Read4Byte(PADAPTER padapter, u32 addr)
-+{
-+	u32 val = 0;
-+	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
-+
-+	HalSdioGetCmdAddr8703BSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
-+	sd_cmd52_read(pintfhdl, addr, 4, (u8 *)&val);
-+
-+	val = le32_to_cpu(val);
-+
-+	return val;
-+}
-+
-+u32 SdioLocalCmd53Read4Byte(PADAPTER padapter, u32 addr)
-+{
-+
-+	u8 bMacPwrCtrlOn;
-+	u32 val = 0;
-+	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
-+
-+	HalSdioGetCmdAddr8703BSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
-+	bMacPwrCtrlOn = _FALSE;
-+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+	if ((_FALSE == bMacPwrCtrlOn)
-+#ifdef CONFIG_LPS_LCLK
-+	    || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode)
-+#endif
-+	   ) {
-+		sd_cmd52_read(pintfhdl, addr, 4, (u8 *)&val);
-+		val = le32_to_cpu(val);
-+	} else
-+		val = sd_read32(pintfhdl, addr, NULL);
-+
-+	return val;
-+}
-+
-+void SdioLocalCmd52Write1Byte(PADAPTER padapter, u32 addr, u8 v)
-+{
-+	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
-+
-+	HalSdioGetCmdAddr8703BSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
-+	sd_cmd52_write(pintfhdl, addr, 1, &v);
-+}
-+
-+void SdioLocalCmd52Write2Byte(PADAPTER padapter, u32 addr, u16 v)
-+{
-+	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
-+
-+	HalSdioGetCmdAddr8703BSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
-+	v = cpu_to_le16(v);
-+	sd_cmd52_write(pintfhdl, addr, 2, (u8 *)&v);
-+}
-+
-+void SdioLocalCmd52Write4Byte(PADAPTER padapter, u32 addr, u32 v)
-+{
-+	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
-+	HalSdioGetCmdAddr8703BSdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
-+	v = cpu_to_le32(v);
-+	sd_cmd52_write(pintfhdl, addr, 4, (u8 *)&v);
-+}
-+
-+#if 0
-+void
-+DumpLoggedInterruptHistory8703Sdio(
-+	PADAPTER		padapter
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	u32				DebugLevel = DBG_LOUD;
-+
-+	if (DBG_Var.DbgPrintIsr == 0)
-+		return;
-+
-+	DBG_ChkDrvResource(padapter);
-+
-+
-+}
-+
-+void
-+LogInterruptHistory8703Sdio(
-+	PADAPTER			padapter,
-+	PRT_ISR_CONTENT	pIsrContent
-+)
-+{
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_RX_REQUEST_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_RX_REQUEST))
-+		pHalData->InterruptLog.nISR_RX_REQUEST++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_AVAL_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_AVAL))
-+		pHalData->InterruptLog.nISR_AVAL++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_TXERR_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_TXERR))
-+		pHalData->InterruptLog.nISR_TXERR++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_RXERR_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_RXERR))
-+		pHalData->InterruptLog.nISR_RXERR++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_TXFOVW_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_TXFOVW))
-+		pHalData->InterruptLog.nISR_TXFOVW++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_RXFOVW_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_RXFOVW))
-+		pHalData->InterruptLog.nISR_RXFOVW++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_TXBCNOK_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_TXBCNOK))
-+		pHalData->InterruptLog.nISR_TXBCNOK++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_TXBCNERR_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_TXBCNERR))
-+		pHalData->InterruptLog.nISR_TXBCNERR++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_BCNERLY_INT_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_BCNERLY_INT))
-+		pHalData->InterruptLog.nISR_BCNERLY_INT++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_C2HCMD_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_C2HCMD))
-+		pHalData->InterruptLog.nISR_C2HCMD++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_CPWM1_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_CPWM1))
-+		pHalData->InterruptLog.nISR_CPWM1++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_CPWM2_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_CPWM2))
-+		pHalData->InterruptLog.nISR_CPWM2++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_HSISR_IND_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_HSISR_IND))
-+		pHalData->InterruptLog.nISR_HSISR_IND++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_GTINT3_IND_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_GTINT3_IND))
-+		pHalData->InterruptLog.nISR_GTINT3_IND++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_GTINT4_IND_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_GTINT4_IND))
-+		pHalData->InterruptLog.nISR_GTINT4_IND++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_PSTIMEOUT_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_PSTIMEOUT))
-+		pHalData->InterruptLog.nISR_PSTIMEOUT++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_OCPINT_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_OCPINT))
-+		pHalData->InterruptLog.nISR_OCPINT++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_ATIMEND_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_ATIMEND))
-+		pHalData->InterruptLog.nISR_ATIMEND++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_ATIMEND_E_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_ATIMEND_E))
-+		pHalData->InterruptLog.nISR_ATIMEND_E++;
-+	if ((pHalData->IntrMask[0] & SDIO_HIMR_CTWEND_MSK) &&
-+	    (pIsrContent->IntArray[0] & SDIO_HISR_CTWEND))
-+		pHalData->InterruptLog.nISR_CTWEND++;
-+
-+}
-+
-+void
-+DumpHardwareProfile8703Sdio(
-+		PADAPTER		padapter
-+)
-+{
-+	DumpLoggedInterruptHistory8703Sdio(padapter);
-+}
-+#endif
-+
-+static s32 ReadInterrupt8703BSdio(PADAPTER padapter, u32 *phisr)
-+{
-+	u32 hisr, himr;
-+	u8 val8, hisr_len;
-+
-+
-+	if (phisr == NULL)
-+		return _FALSE;
-+
-+	himr = GET_HAL_DATA(padapter)->sdio_himr;
-+
-+	/* decide how many bytes need to be read */
-+	hisr_len = 0;
-+	while (himr) {
-+		hisr_len++;
-+		himr >>= 8;
-+	}
-+
-+	hisr = 0;
-+	while (hisr_len != 0) {
-+		hisr_len--;
-+		val8 = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HISR + hisr_len);
-+		hisr |= (val8 << (8 * hisr_len));
-+	}
-+
-+	*phisr = hisr;
-+
-+	return _TRUE;
-+}
-+
-+/*
-+ *	Description:
-+ *		Initialize SDIO Host Interrupt Mask configuration variables for future use.
-+ *
-+ *	Assumption:
-+ *		Using SDIO Local register ONLY for configuration.
-+ *
-+ *	Created by Roger, 2011.02.11.
-+ *   */
-+void InitInterrupt8703BSdio(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	pHalData->sdio_himr = (u32)(\
-+				    SDIO_HIMR_RX_REQUEST_MSK			|
-+#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+				    SDIO_HIMR_AVAL_MSK					|
-+#endif
-+				    /*								SDIO_HIMR_TXERR_MSK				|
-+				     *								SDIO_HIMR_RXERR_MSK				|
-+				     *								SDIO_HIMR_TXFOVW_MSK				|
-+				     *								SDIO_HIMR_RXFOVW_MSK				|
-+				     *								SDIO_HIMR_TXBCNOK_MSK				|
-+				     *								SDIO_HIMR_TXBCNERR_MSK			|
-+				     *								SDIO_HIMR_BCNERLY_INT_MSK			|
-+				     *								SDIO_HIMR_C2HCMD_MSK				| */
-+#if defined(CONFIG_LPS_LCLK) && !defined(CONFIG_DETECT_CPWM_BY_POLLING)
-+				    SDIO_HIMR_CPWM1_MSK				|
-+#endif /* CONFIG_LPS_LCLK && !CONFIG_DETECT_CPWM_BY_POLLING */
-+#ifdef CONFIG_WOWLAN
-+				    SDIO_HIMR_CPWM2_MSK				|
-+#endif
-+				    /*								SDIO_HIMR_HSISR_IND_MSK			|
-+				     *								SDIO_HIMR_GTINT3_IND_MSK			|
-+				     *								SDIO_HIMR_GTINT4_IND_MSK			|
-+				     *								SDIO_HIMR_PSTIMEOUT_MSK			|
-+				     *								SDIO_HIMR_OCPINT_MSK				|
-+				     *								SDIO_HIMR_ATIMEND_MSK				|
-+				     *								SDIO_HIMR_ATIMEND_E_MSK			|
-+				     *								SDIO_HIMR_CTWEND_MSK				| */
-+				    0);
-+}
-+
-+/*
-+ *	Description:
-+ *		Initialize System Host Interrupt Mask configuration variables for future use.
-+ *
-+ *	Created by Roger, 2011.08.03.
-+ *   */
-+void InitSysInterrupt8703BSdio(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	pHalData->SysIntrMask = (\
-+				 /*							HSIMR_GPIO12_0_INT_EN			|
-+				  *							HSIMR_SPS_OCP_INT_EN			|
-+				  *							HSIMR_RON_INT_EN				|
-+				  *							HSIMR_PDNINT_EN				|
-+				  *							HSIMR_GPIO9_INT_EN				| */
-+				 0);
-+}
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+/*
-+ *	Description:
-+ *		Clear corresponding SDIO Host ISR interrupt service.
-+ *
-+ *	Assumption:
-+ *		Using SDIO Local register ONLY for configuration.
-+ *
-+ *	Created by Roger, 2011.02.11.
-+ *   */
-+void ClearInterrupt8703BSdio(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+	u8 *clear;
-+
-+
-+	if (rtw_is_surprise_removed(padapter))
-+		return;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+	clear = rtw_zmalloc(4);
-+
-+	/* Clear corresponding HISR Content if needed */
-+	*(u32 *)clear = cpu_to_le32(pHalData->sdio_hisr & MASK_SDIO_HISR_CLEAR);
-+	if (*(u32 *)clear) {
-+		/* Perform write one clear operation */
-+		sdio_local_write(padapter, SDIO_REG_HISR, 4, clear);
-+	}
-+
-+	rtw_mfree(clear, 4);
-+}
-+#endif
-+
-+/*
-+ *	Description:
-+ *		Clear corresponding system Host ISR interrupt service.
-+ *
-+ *
-+ *	Created by Roger, 2011.02.11.
-+ *   */
-+void ClearSysInterrupt8703BSdio(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+	u32 clear;
-+
-+
-+	if (rtw_is_surprise_removed(padapter))
-+		return;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	/* Clear corresponding HISR Content if needed */
-+	clear = pHalData->SysIntrStatus & MASK_HSISR_CLEAR;
-+	if (clear) {
-+		/* Perform write one clear operation */
-+		rtw_write32(padapter, REG_HSISR, clear);
-+	}
-+}
-+
-+/*
-+ *	Description:
-+ *		Enalbe SDIO Host Interrupt Mask configuration on SDIO local domain.
-+ *
-+ *	Assumption:
-+ *		1. Using SDIO Local register ONLY for configuration.
-+ *		2. PASSIVE LEVEL
-+ *
-+ *	Created by Roger, 2011.02.11.
-+ *   */
-+void EnableInterrupt8703BSdio(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE pHalData;
-+	u32 himr;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	himr = cpu_to_le32(pHalData->sdio_himr);
-+	sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
-+
-+
-+	/* Update current system IMR settings */
-+	himr = rtw_read32(padapter, REG_HSIMR);
-+	rtw_write32(padapter, REG_HSIMR, himr | pHalData->SysIntrMask);
-+
-+
-+	/*  */
-+	/* <Roger_Notes> There are some C2H CMDs have been sent before system interrupt is enabled, e.g., C2H, CPWM. */
-+	/* So we need to clear all C2H events that FW has notified, otherwise FW won't schedule any commands anymore. */
-+	/* 2011.10.19. */
-+	/*  */
-+	rtw_write8(padapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
-+}
-+
-+/*
-+ *	Description:
-+ *		Disable SDIO Host IMR configuration to mask unnecessary interrupt service.
-+ *
-+ *	Assumption:
-+ *		Using SDIO Local register ONLY for configuration.
-+ *
-+ *	Created by Roger, 2011.02.11.
-+ *   */
-+void DisableInterrupt8703BSdio(PADAPTER padapter)
-+{
-+	u32 himr;
-+
-+	himr = cpu_to_le32(SDIO_HIMR_DISABLED);
-+	sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
-+
-+}
-+
-+/*
-+ *	Description:
-+ *		Using 0x100 to check the power status of FW.
-+ *
-+ *	Assumption:
-+ *		Using SDIO Local register ONLY for configuration.
-+ *
-+ *	Created by Isaac, 2013.09.10.
-+ *   */
-+u8 CheckIPSStatus(PADAPTER padapter)
-+{
-+	RTW_INFO("%s(): Read 0x100=0x%02x 0x86=0x%02x\n", __func__,
-+		 rtw_read8(padapter, 0x100), rtw_read8(padapter, 0x86));
-+
-+	if (rtw_read8(padapter, 0x100) == 0xEA)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+#ifdef CONFIG_WOWLAN
-+void DisableInterruptButCpwm28703BSdio(PADAPTER padapter)
-+{
-+	u32 himr, tmp;
-+
-+	sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
-+	RTW_INFO("DisableInterruptButCpwm28703BSdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp);
-+
-+	himr = cpu_to_le32(SDIO_HIMR_DISABLED) | SDIO_HIMR_CPWM2_MSK;
-+	sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
-+
-+	sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
-+	RTW_INFO("DisableInterruptButCpwm28703BSdio(): Read again SDIO_REG_HIMR: 0x%08x\n", tmp);
-+}
-+#endif /* CONFIG_WOWLAN
-+ *
-+ *	Description:
-+ *		Update SDIO Host Interrupt Mask configuration on SDIO local domain.
-+ *
-+ *	Assumption:
-+ *		1. Using SDIO Local register ONLY for configuration.
-+ *		2. PASSIVE LEVEL
-+ *
-+ *	Created by Roger, 2011.02.11.
-+ *   */
-+void UpdateInterruptMask8703BSdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR)
-+{
-+	HAL_DATA_TYPE *pHalData;
-+
-+	pHalData = GET_HAL_DATA(padapter);
-+
-+	if (AddMSR)
-+		pHalData->sdio_himr |= AddMSR;
-+
-+	if (RemoveMSR)
-+		pHalData->sdio_himr &= (~RemoveMSR);
-+
-+	DisableInterrupt8703BSdio(padapter);
-+	EnableInterrupt8703BSdio(padapter);
-+}
-+
-+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
-+static void sd_recv_loopback(PADAPTER padapter, u32 size)
-+{
-+	PLOOPBACKDATA ploopback;
-+	u32 readsize, allocsize;
-+	u8 *preadbuf;
-+
-+
-+	readsize = size;
-+	RTW_INFO("%s: read size=%d\n", __func__, readsize);
-+	allocsize = _RND(readsize, rtw_sdio_get_block_size(adapter_to_dvobj(padapter)));
-+
-+	ploopback = padapter->ploopback;
-+	if (ploopback) {
-+		ploopback->rxsize = readsize;
-+		preadbuf = ploopback->rxbuf;
-+	} else {
-+		preadbuf = rtw_malloc(allocsize);
-+		if (preadbuf == NULL) {
-+			RTW_INFO("%s: malloc fail size=%d\n", __func__, allocsize);
-+			return;
-+		}
-+	}
-+
-+	/*	rtw_read_port(padapter, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf); */
-+	sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf);
-+
-+	if (ploopback)
-+		_rtw_up_sema(&ploopback->sema);
-+	else {
-+		u32 i;
-+
-+		RTW_INFO("%s: drop pkt\n", __func__);
-+		for (i = 0; i < readsize; i += 4) {
-+			RTW_INFO("%08X", *(u32 *)(preadbuf + i));
-+			if ((i + 4) & 0x1F)
-+				printk(" ");
-+			else
-+				printk("\n");
-+		}
-+		printk("\n");
-+		rtw_mfree(preadbuf, allocsize);
-+	}
-+}
-+#endif /* CONFIG_MAC_LOOPBACK_DRIVER */
-+
-+#ifdef CONFIG_SDIO_RX_COPY
-+static u32 sd_recv_rxfifo(PADAPTER padapter, u32 size, struct recv_buf **recvbuf_ret)
-+{
-+	u32 readsize, ret;
-+	u8 *preadbuf;
-+	struct recv_priv *precvpriv;
-+	struct recv_buf	*precvbuf;
-+
-+
-+#if 0
-+	readsize = size;
-+#else
-+	/* Patch for some SDIO Host 4 bytes issue */
-+	/* ex. RK3188 */
-+	readsize = RND4(size);
-+#endif
-+
-+	/* 3 1. alloc recvbuf */
-+	precvpriv = &padapter->recvpriv;
-+	precvbuf = rtw_dequeue_recvbuf(&precvpriv->free_recv_buf_queue);
-+	if (precvbuf == NULL) {
-+		RTW_INFO("%s: recvbuf unavailable\n", __func__); //No free rece_buffer.
-+		ret = RTW_RBUF_UNAVAIL;
-+		goto exit;
-+	}
-+
-+	/* 3 2. alloc skb */
-+	if (precvbuf->pskb == NULL) {
-+		SIZE_PTR tmpaddr = 0;
-+		SIZE_PTR alignment = 0;
-+
-+		precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
-+		if (precvbuf->pskb == NULL) {
-+			RTW_INFO("%s: alloc_skb fail! read=%d\n", __FUNCTION__, readsize);
-+			rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
-+			ret = RTW_RBUF_PKT_UNAVAIL;
-+			goto exit;
-+		}
-+
-+		precvbuf->pskb->dev = padapter->pnetdev;
-+
-+		tmpaddr = (SIZE_PTR)precvbuf->pskb->data;
-+		alignment = tmpaddr & (RECVBUFF_ALIGN_SZ - 1);
-+		skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
-+	}
-+
-+	/* 3 3. read data from rxfifo */
-+	preadbuf = precvbuf->pskb->data;
-+	/*	rtw_read_port(padapter, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf); */
-+	ret = sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf);
-+	if (ret == _FAIL) {
-+		rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
-+		goto exit;
-+	}
-+
-+	/* 3 4. init recvbuf */
-+	precvbuf->len = size;
-+	precvbuf->phead = precvbuf->pskb->head;
-+	precvbuf->pdata = precvbuf->pskb->data;
-+	skb_set_tail_pointer(precvbuf->pskb, size);
-+	precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
-+	precvbuf->pend = skb_end_pointer(precvbuf->pskb);
-+
-+	*recvbuf_ret = precvbuf;
-+	exit:
-+		return ret;	
-+}
-+#else /* !CONFIG_SDIO_RX_COPY */
-+static struct recv_buf *sd_recv_rxfifo(PADAPTER padapter, u32 size)
-+{
-+	u32 readsize, allocsize, ret;
-+	u8 *preadbuf;
-+	_pkt *ppkt;
-+	struct recv_priv *precvpriv;
-+	struct recv_buf	*precvbuf;
-+
-+
-+#if 0
-+	readsize = size;
-+#else
-+	/* Patch for some SDIO Host 4 bytes issue */
-+	/* ex. RK3188 */
-+	readsize = RND4(size);
-+#endif
-+
-+	/* 3 1. alloc skb */
-+	/* align to block size */
-+	allocsize = rtw_sdio_cmd53_align_size(adapter_to_dvobj(padapter), readsize);
-+
-+	ppkt = rtw_skb_alloc(allocsize);
-+
-+	if (ppkt == NULL) {
-+		return NULL;
-+	}
-+
-+	/* 3 2. read data from rxfifo */
-+	preadbuf = skb_put(ppkt, size);
-+	/*	rtw_read_port(padapter, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf); */
-+	ret = sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf);
-+	if (ret == _FAIL) {
-+		rtw_skb_free(ppkt);
-+		return NULL;
-+	}
-+
-+	/* 3 3. alloc recvbuf */
-+	precvpriv = &padapter->recvpriv;
-+	precvbuf = rtw_dequeue_recvbuf(&precvpriv->free_recv_buf_queue);
-+	if (precvbuf == NULL) {
-+		rtw_skb_free(ppkt);
-+		RTW_ERR("%s: alloc recvbuf FAIL!\n", __FUNCTION__);
-+		return NULL;
-+	}
-+
-+	/* 3 4. init recvbuf */
-+	precvbuf->pskb = ppkt;
-+
-+	precvbuf->len = ppkt->len;
-+
-+	precvbuf->phead = ppkt->head;
-+	precvbuf->pdata = ppkt->data;
-+	precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
-+	precvbuf->pend = skb_end_pointer(precvbuf->pskb);
-+
-+	return precvbuf;
-+}
-+#endif /* !CONFIG_SDIO_RX_COPY */
-+
-+static void sd_rxhandler(PADAPTER padapter, struct recv_buf *precvbuf)
-+{
-+	struct recv_priv *precvpriv;
-+	_queue *ppending_queue;
-+
-+
-+	precvpriv = &padapter->recvpriv;
-+	ppending_queue = &precvpriv->recv_buf_pending_queue;
-+
-+	/* 3 1. enqueue recvbuf */
-+	rtw_enqueue_recvbuf(precvbuf, ppending_queue);//rx thread dequeue pending
-+
-+
-+	/* 3 2. trigger recv hdl */
-+#ifdef CONFIG_RECV_THREAD_MODE
-+		_rtw_up_sema(&precvpriv->recv_sema);
-+#else
-+	#ifdef PLATFORM_LINUX
-+	tasklet_schedule(&precvpriv->recv_tasklet);
-+	#endif /* PLATFORM_LINUX */
-+#endif /* CONFIG_RECV_THREAD_MODE */
-+}
-+
-+void sd_int_dpc(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE phal;
-+	struct dvobj_priv *dvobj;
-+	struct intf_hdl *pintfhdl = &padapter->iopriv.intf;
-+	struct pwrctrl_priv *pwrctl;
-+
-+
-+	phal = GET_HAL_DATA(padapter);
-+	dvobj = adapter_to_dvobj(padapter);
-+	pwrctl = dvobj_to_pwrctl(dvobj);
-+
-+#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+	if (phal->sdio_hisr & SDIO_HISR_AVAL) {
-+		/* _irqL irql; */
-+		u8	freepage[4];
-+
-+		_sdio_local_read(padapter, SDIO_REG_FREE_TXPG, 4, freepage);
-+		/* _enter_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql); */
-+		/* _rtw_memcpy(phal->SdioTxFIFOFreePage, freepage, 4); */
-+		/* _exit_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql); */
-+		/* RTW_INFO("SDIO_HISR_AVAL, Tx Free Page = 0x%x%x%x%x\n", */
-+		/*	freepage[0], */
-+		/*	freepage[1], */
-+		/*	freepage[2], */
-+		/*	freepage[3]); */
-+		_rtw_up_sema(&(padapter->xmitpriv.xmit_sema));
-+	}
-+#endif
-+	if (phal->sdio_hisr & SDIO_HISR_CPWM1) {
-+		struct reportpwrstate_parm report;
-+
-+#ifdef CONFIG_LPS_RPWM_TIMER
-+		_cancel_timer_ex(&(pwrctl->pwr_rpwm_timer));
-+#endif /* CONFIG_LPS_RPWM_TIMER */
-+
-+		report.state = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HCPWM1_8703B);
-+
-+#ifdef CONFIG_LPS_LCLK
-+		/* cpwm_int_hdl(padapter, &report); */
-+		_set_workitem(&(pwrctl->cpwm_event));
-+#endif
-+	}
-+
-+	if (phal->sdio_hisr & SDIO_HISR_TXERR) {
-+		u8 *status;
-+		u32 addr;
-+
-+		status = rtw_malloc(4);
-+		if (status) {
-+			addr = REG_TXDMA_STATUS;
-+			HalSdioGetCmdAddr8703BSdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr);
-+			_sd_read(pintfhdl, addr, 4, status);
-+			_sd_write(pintfhdl, addr, 4, status);
-+			RTW_INFO("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32 *)status));
-+			rtw_mfree(status, 4);
-+		} else
-+			RTW_INFO("%s: SDIO_HISR_TXERR, but can't allocate memory to read status!\n", __func__);
-+	}
-+
-+	if (phal->sdio_hisr & SDIO_HISR_TXBCNOK)
-+		RTW_INFO("%s: SDIO_HISR_TXBCNOK\n", __func__);
-+
-+	if (phal->sdio_hisr & SDIO_HISR_TXBCNERR)
-+		RTW_INFO("%s: SDIO_HISR_TXBCNERR\n", __func__);
-+
-+#ifdef CONFIG_FW_C2H_REG
-+	if (phal->sdio_hisr & SDIO_HISR_C2HCMD) {
-+		RTW_INFO("%s: C2H Command\n", __func__);
-+		sd_c2h_hisr_hdl(padapter);
-+	}
-+#endif
-+
-+	if (phal->sdio_hisr & SDIO_HISR_RXFOVW)
-+		RTW_INFO("%s: Rx Overflow\n", __func__);
-+	if (phal->sdio_hisr & SDIO_HISR_RXERR)
-+		RTW_INFO("%s: Rx Error\n", __func__);
-+
-+	if (phal->sdio_hisr & SDIO_HISR_RX_REQUEST) {
-+		struct recv_buf *precvbuf = NULL;
-+		int alloc_fail_time = 0;
-+		u32 hisr = 0, rx_cnt = 0, ret = 0;
-+
-+	/*		RTW_INFO("%s: RX Request, size=%d\n", __func__, phal->SdioRxFIFOSize); */
-+		phal->sdio_hisr ^= SDIO_HISR_RX_REQUEST;
-+		do {
-+			phal->SdioRxFIFOSize = SdioLocalCmd52Read2Byte(padapter, SDIO_REG_RX0_REQ_LEN);
-+			if (phal->SdioRxFIFOSize != 0) {
-+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
-+				sd_recv_loopback(padapter, phal->SdioRxFIFOSize);
-+#else
-+				ret = sd_recv_rxfifo(padapter, phal->SdioRxFIFOSize, &precvbuf);
-+				if (precvbuf) {
-+					//RTW_INFO("phal->SdioRxFIFOSize:%d\n", phal->SdioRxFIFOSize);
-+					sd_rxhandler(padapter, precvbuf);
-+					phal->SdioRxFIFOSize = 0;
-+					rx_cnt++;
-+				} else {
-+					alloc_fail_time++;
-+					if (ret == RTW_RBUF_UNAVAIL || ret == RTW_RBUF_PKT_UNAVAIL)
-+						rtw_msleep_os(10);
-+					else {
-+					RTW_INFO("%s: recv fail!(time=%d)\n", __func__, alloc_fail_time);
-+						phal->SdioRxFIFOSize = 0;
-+					}
-+					if (alloc_fail_time >= 10 && rx_cnt != 0)
-+						break;
-+				}
-+#endif
-+			} else
-+				break;
-+
-+			hisr = 0;
-+			ReadInterrupt8703BSdio(padapter, &hisr);
-+			hisr &= SDIO_HISR_RX_REQUEST;
-+			if (!hisr)
-+				break;
-+		} while (1);
-+
-+		if (alloc_fail_time == 10)
-+			RTW_INFO("%s: exit because recv failed more than 10 times!\n", __func__);
-+	}
-+}
-+
-+void sd_int_hdl(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE phal;
-+
-+
-+	if (RTW_CANNOT_RUN(padapter))
-+		return;
-+
-+	phal = GET_HAL_DATA(padapter);
-+
-+	phal->sdio_hisr = 0;
-+	ReadInterrupt8703BSdio(padapter, &phal->sdio_hisr);
-+
-+	if (phal->sdio_hisr & phal->sdio_himr) {
-+		u32 v32;
-+
-+		phal->sdio_hisr &= phal->sdio_himr;
-+
-+		/* clear HISR */
-+		v32 = phal->sdio_hisr & MASK_SDIO_HISR_CLEAR;
-+		if (v32)
-+			SdioLocalCmd52Write4Byte(padapter, SDIO_REG_HISR, v32);
-+
-+		sd_int_dpc(padapter);
-+	}
-+}
-+
-+/*
-+ *	Description:
-+ *		Query SDIO Local register to query current the number of Free TxPacketBuffer page.
-+ *
-+ *	Assumption:
-+ *		1. Running at PASSIVE_LEVEL
-+ *		2. RT_TX_SPINLOCK is NOT acquired.
-+ *
-+ *	Created by Roger, 2011.01.28.
-+ *   */
-+u8 HalQueryTxBufferStatus8703BSdio(PADAPTER padapter)
-+{
-+	PHAL_DATA_TYPE phal;
-+	u32 NumOfFreePage;
-+	/* _irqL irql; */
-+
-+
-+	phal = GET_HAL_DATA(padapter);
-+
-+	NumOfFreePage = SdioLocalCmd53Read4Byte(padapter, SDIO_REG_FREE_TXPG);
-+
-+	/* _enter_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql); */
-+	_rtw_memcpy(phal->SdioTxFIFOFreePage, &NumOfFreePage, 4);
-+	/* _exit_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql); */
-+
-+	return _TRUE;
-+}
-+
-+/*
-+ *	Description:
-+ *		Query SDIO Local register to get the current number of TX OQT Free Space.
-+ *   */
-+u8 HalQueryTxOQTBufferStatus8703BSdio(PADAPTER padapter)
-+{
-+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
-+	pHalData->SdioTxOQTFreeSpace = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_OQT_FREE_PG);
-+	return _TRUE;
-+}
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+u8 RecvOnePkt(PADAPTER padapter)
-+{
-+	struct recv_buf *precvbuf;
-+	struct dvobj_priv *psddev;
-+	PSDIO_DATA psdio_data;
-+	struct sdio_func *func;
-+	u32 tmp = 0;
-+	u16 len = 0;
-+	u8 res = _FALSE;
-+
-+	if (padapter == NULL) {
-+		RTW_ERR("%s: padapter is NULL!\n", __func__);
-+		return _FALSE;
-+	}
-+
-+	psddev = adapter_to_dvobj(padapter);
-+	psdio_data = &psddev->intf_data;
-+	func = psdio_data->func;
-+
-+	/* If RX_DMA is not idle, receive one pkt from DMA */
-+	res = sdio_local_read(padapter,
-+			  SDIO_REG_RX0_REQ_LEN, 4, (u8 *)&tmp);
-+	len = le16_to_cpu(tmp);
-+	RTW_INFO("+%s: size: %d+\n", __func__, len);
-+
-+	if (len) {
-+		sdio_claim_host(func);
-+		res = sd_recv_rxfifo(padapter, len, &precvbuf);
-+
-+		if (precvbuf) {
-+			/* printk("Completed Recv One Pkt.\n"); */
-+			sd_rxhandler(padapter, precvbuf);
-+			res = _TRUE;
-+		} else
-+			res = _FALSE;
-+		sdio_release_host(func);
-+	}
-+	RTW_INFO("-%s-\n", __func__);
-+	return res;
-+}
-+#endif /* CONFIG_WOWLAN */
-+
-diff --git a/drivers/staging/rtl8723cs/ifcfg-wlan0 b/drivers/staging/rtl8723cs/ifcfg-wlan0
-new file mode 100644
-index 000000000000..7ecb7ae62c7f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/ifcfg-wlan0
-@@ -0,0 +1,4 @@
-+#DHCP client
-+DEVICE=wlan0
-+BOOTPROTO=dhcp
-+ONBOOT=yes
-\ No newline at end of file
-diff --git a/drivers/staging/rtl8723cs/include/Hal8188EPhyCfg.h b/drivers/staging/rtl8723cs/include/Hal8188EPhyCfg.h
-new file mode 100644
-index 000000000000..38983f75134f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8188EPhyCfg.h
-@@ -0,0 +1,249 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8188EPHYCFG_H__
-+#define __INC_HAL8188EPHYCFG_H__
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+#define LOOP_LIMIT				5
-+#define MAX_STALL_TIME			50		/* us */
-+#define AntennaDiversityValue		0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
-+#define MAX_TXPWR_IDX_NMODE_92S	63
-+#define Reset_Cnt_Limit			3
-+
-+#ifdef CONFIG_PCI_HCI
-+	#define MAX_AGGR_NUM	0x0B
-+#else
-+	#define MAX_AGGR_NUM	0x07
-+#endif /* CONFIG_PCI_HCI */
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+#define	MAX_TX_COUNT_8188E			1
-+
-+/* BB/RF related */
-+
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+
-+/*------------------------Export global variable----------------------------*/
-+/*------------------------Export global variable----------------------------*/
-+
-+
-+/*------------------------Export Marco Definition---------------------------*/
-+/*------------------------Export Marco Definition---------------------------*/
-+
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+/*
-+ * BB and RF register read/write
-+ *   */
-+u32	PHY_QueryBBReg8188E(PADAPTER	Adapter,
-+				u32		RegAddr,
-+				u32		BitMask);
-+void	PHY_SetBBReg8188E(PADAPTER	Adapter,
-+				u32		RegAddr,
-+				u32		BitMask,
-+				u32		Data);
-+u32	PHY_QueryRFReg8188E(PADAPTER	Adapter,
-+				enum rf_path		eRFPath,
-+				u32				RegAddr,
-+				u32				BitMask);
-+void	PHY_SetRFReg8188E(PADAPTER		Adapter,
-+				enum rf_path		eRFPath,
-+				u32				RegAddr,
-+				u32				BitMask,
-+				u32				Data);
-+
-+/*
-+ * Initialization related function
-+ */
-+/* MAC/BB/RF HAL config */
-+int	PHY_MACConfig8188E(PADAPTER	Adapter);
-+int	PHY_BBConfig8188E(PADAPTER	Adapter);
-+int	PHY_RFConfig8188E(PADAPTER	Adapter);
-+
-+/* RF config */
-+int	rtl8188e_PHY_ConfigRFWithParaFile( PADAPTER Adapter, u8 *pFileName, enum rf_path eRFPath);
-+
-+/*
-+ * RF Power setting
-+ */
-+/* extern	BOOLEAN	PHY_SetRFPowerState(PADAPTER			Adapter,
-+ *										RT_RF_POWER_STATE	eRFPowerState); */
-+
-+/*
-+ * BB TX Power R/W
-+ *   */
-+void	PHY_SetTxPowerLevel8188E(PADAPTER		Adapter,
-+					u8			channel);
-+
-+void
-+PHY_SetTxPowerIndex_8188E(
-+		PADAPTER			Adapter,
-+		u32					PowerIndex,
-+		enum rf_path			RFPath,
-+		u8					Rate
-+);
-+
-+s8 phy_get_txpwr_target_extra_bias_8188e(_adapter *adapter, enum rf_path rfpath
-+	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch);
-+
-+/*
-+ * Switch bandwidth for 8192S
-+ */
-+/* extern	void	PHY_SetBWModeCallback8192C(PRT_TIMER		pTimer	); */
-+void	PHY_SetBWMode8188E(PADAPTER			pAdapter,
-+				enum channel_width	ChnlWidth,
-+				unsigned char	Offset);
-+
-+/*
-+ * Set FW CMD IO for 8192S.
-+ */
-+/* extern	BOOLEAN HalSetIO8192C(PADAPTER			Adapter,
-+ *								IO_TYPE				IOType); */
-+
-+/*
-+ * Set A2 entry to fw for 8192S
-+ *   */
-+extern	void FillA2Entry8192C(PADAPTER			Adapter,
-+				u8				index,
-+				u8				*val);
-+
-+
-+/*
-+ * channel switch related funciton
-+ */
-+/* extern	void	PHY_SwChnlCallback8192C(PRT_TIMER		pTimer	); */
-+void	PHY_SwChnl8188E(PADAPTER		pAdapter,
-+				u8			channel);
-+
-+void
-+PHY_SetSwChnlBWMode8188E(
-+		PADAPTER			Adapter,
-+		u8					channel,
-+		enum channel_width	Bandwidth,
-+		u8					Offset40,
-+		u8					Offset80
-+);
-+
-+void
-+PHY_SetRFEReg_8188E(
-+		PADAPTER		Adapter
-+);
-+/*
-+ * BB/MAC/RF other monitor API
-+ *   */
-+void phy_set_rf_path_switch_8188e(struct dm_struct	*phydm, bool		bMain);
-+
-+extern	void
-+PHY_SwitchEphyParameter(
-+		PADAPTER			Adapter
-+);
-+
-+extern	void
-+PHY_EnableHostClkReq(
-+		PADAPTER			Adapter
-+);
-+
-+BOOLEAN
-+SetAntennaConfig92C(
-+		PADAPTER	Adapter,
-+		u8		DefaultAnt
-+);
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+
-+/*
-+ * Initialization related function
-+ *
-+ * MAC/BB/RF HAL config */
-+/* extern s32 PHY_MACConfig8723(PADAPTER padapter);
-+ * s32 PHY_BBConfig8723(PADAPTER padapter);
-+ * s32 PHY_RFConfig8723(PADAPTER padapter); */
-+
-+
-+
-+/* ******************************************************************
-+ * Note: If SIC_ENABLE under PCIE, because of the slow operation
-+ *	you should
-+ * 	2) "#define RTL8723_FPGA_VERIFICATION	1"				in Precomp.h.WlanE.Windows
-+ * 	3) "#define RTL8190_Download_Firmware_From_Header	0"	in Precomp.h.WlanE.Windows if needed.
-+ *   */
-+#if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)
-+	#define	SIC_ENABLE				1
-+	#define	SIC_HW_SUPPORT		1
-+#else
-+	#define	SIC_ENABLE				0
-+	#define	SIC_HW_SUPPORT		0
-+#endif
-+/* ****************************************************************** */
-+
-+
-+#define	SIC_MAX_POLL_CNT		5
-+
-+#if (SIC_HW_SUPPORT == 1)
-+	#define	SIC_CMD_READY			0
-+	#define	SIC_CMD_PREWRITE		0x1
-+	#if (RTL8188E_SUPPORT == 1)
-+		#define	SIC_CMD_WRITE			0x40
-+		#define	SIC_CMD_PREREAD		0x2
-+		#define	SIC_CMD_READ			0x80
-+		#define	SIC_CMD_INIT			0xf0
-+		#define	SIC_INIT_VAL			0xff
-+
-+		#define	SIC_INIT_REG			0x1b7
-+		#define	SIC_CMD_REG			0x1EB		/* 1byte */
-+		#define	SIC_ADDR_REG			0x1E8		/* 1b4~1b5, 2 bytes */
-+		#define	SIC_DATA_REG			0x1EC		/* 1b0~1b3 */
-+	#else
-+		#define	SIC_CMD_WRITE			0x11
-+		#define	SIC_CMD_PREREAD		0x2
-+		#define	SIC_CMD_READ			0x12
-+		#define	SIC_CMD_INIT			0x1f
-+		#define	SIC_INIT_VAL			0xff
-+
-+		#define	SIC_INIT_REG			0x1b7
-+		#define	SIC_CMD_REG			0x1b6		/* 1byte */
-+		#define	SIC_ADDR_REG			0x1b4		/* 1b4~1b5, 2 bytes */
-+		#define	SIC_DATA_REG			0x1b0		/* 1b0~1b3 */
-+	#endif
-+#else
-+	#define	SIC_CMD_READY			0
-+	#define	SIC_CMD_WRITE			1
-+	#define	SIC_CMD_READ			2
-+
-+	#if (RTL8188E_SUPPORT == 1)
-+		#define	SIC_CMD_REG			0x1EB		/* 1byte */
-+		#define	SIC_ADDR_REG			0x1E8		/* 1b9~1ba, 2 bytes */
-+		#define	SIC_DATA_REG			0x1EC		/* 1bc~1bf */
-+	#else
-+		#define	SIC_CMD_REG			0x1b8		/* 1byte */
-+		#define	SIC_ADDR_REG			0x1b9		/* 1b9~1ba, 2 bytes */
-+		#define	SIC_DATA_REG			0x1bc		/* 1bc~1bf */
-+	#endif
-+#endif
-+
-+#if (SIC_ENABLE == 1)
-+	void SIC_Init( PADAPTER Adapter);
-+#endif
-+
-+
-+#endif /* __INC_HAL8192CPHYCFG_H */
-diff --git a/drivers/staging/rtl8723cs/include/Hal8188EPhyReg.h b/drivers/staging/rtl8723cs/include/Hal8188EPhyReg.h
-new file mode 100644
-index 000000000000..2eab8313aa5d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8188EPhyReg.h
-@@ -0,0 +1,1100 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8188EPHYREG_H__
-+#define __INC_HAL8188EPHYREG_H__
-+/*--------------------------Define Parameters-------------------------------*/
-+/*
-+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
-+ * 3. RF register 0x00-2E
-+ * 4. Bit Mask for BB/RF register
-+ * 5. Other defintion for BB/RF R/W
-+ *   */
-+
-+
-+/*
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 1. Page1(0x100)
-+ *   */
-+#define		rPMAC_Reset					0x100
-+#define		rPMAC_TxStart				0x104
-+#define		rPMAC_TxLegacySIG			0x108
-+#define		rPMAC_TxHTSIG1				0x10c
-+#define		rPMAC_TxHTSIG2				0x110
-+#define		rPMAC_PHYDebug				0x114
-+#define		rPMAC_TxPacketNum			0x118
-+#define		rPMAC_TxIdle					0x11c
-+#define		rPMAC_TxMACHeader0			0x120
-+#define		rPMAC_TxMACHeader1			0x124
-+#define		rPMAC_TxMACHeader2			0x128
-+#define		rPMAC_TxMACHeader3			0x12c
-+#define		rPMAC_TxMACHeader4			0x130
-+#define		rPMAC_TxMACHeader5			0x134
-+#define		rPMAC_TxDataType				0x138
-+#define		rPMAC_TxRandomSeed			0x13c
-+#define		rPMAC_CCKPLCPPreamble		0x140
-+#define		rPMAC_CCKPLCPHeader			0x144
-+#define		rPMAC_CCKCRC16				0x148
-+#define		rPMAC_OFDMRxCRC32OK		0x170
-+#define		rPMAC_OFDMRxCRC32Er		0x174
-+#define		rPMAC_OFDMRxParityEr			0x178
-+#define		rPMAC_OFDMRxCRC8Er			0x17c
-+#define		rPMAC_CCKCRxRC16Er			0x180
-+#define		rPMAC_CCKCRxRC32Er			0x184
-+#define		rPMAC_CCKCRxRC32OK			0x188
-+#define		rPMAC_TxStatus				0x18c
-+
-+/*
-+ * 2. Page2(0x200)
-+ *
-+ * The following two definition are only used for USB interface. */
-+#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
-+#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
-+
-+/*
-+ * 3. Page8(0x800)
-+ *   */
-+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
-+
-+#define		rFPGA0_TxInfo					0x804	/* Status report?? */
-+#define		rFPGA0_PSDFunction			0x808
-+
-+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
-+
-+#define		rFPGA0_RFTiming1				0x810	/* Useless now */
-+#define		rFPGA0_RFTiming2				0x814
-+
-+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
-+#define		rFPGA0_XA_HSSIParameter2		0x824
-+#define		rFPGA0_XB_HSSIParameter1		0x828
-+#define		rFPGA0_XB_HSSIParameter2		0x82c
-+
-+#define		rFPGA0_XA_LSSIParameter		0x840
-+#define		rFPGA0_XB_LSSIParameter		0x844
-+
-+#define		rFPGA0_RFWakeUpParameter	0x850	/* Useless now */
-+#define		rFPGA0_RFSleepUpParameter		0x854
-+
-+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
-+#define		rFPGA0_XCD_SwitchControl		0x85c
-+
-+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
-+#define		rFPGA0_XB_RFInterfaceOE		0x864
-+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
-+#define		rFPGA0_XCD_RFInterfaceSW		0x874
-+
-+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
-+#define		rFPGA0_XCD_RFParameter		0x87c
-+
-+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
-+#define		rFPGA0_AnalogParameter2		0x884
-+#define		rFPGA0_AnalogParameter3		0x888
-+#define		rFPGA0_AdDaClockEn			0x888	/* enable ad/da clock1 for dual-phy */
-+#define		rFPGA0_AnalogParameter4		0x88c
-+
-+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
-+#define		rFPGA0_XB_LSSIReadBack		0x8a4
-+#define		rFPGA0_XC_LSSIReadBack		0x8a8
-+#define		rFPGA0_XD_LSSIReadBack		0x8ac
-+
-+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
-+#define		TransceiverA_HSPI_Readback		0x8b8	/* Transceiver A HSPI Readback */
-+#define		TransceiverB_HSPI_Readback		0x8bc	/* Transceiver B HSPI Readback */
-+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
-+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
-+
-+/*
-+ * 4. Page9(0x900)
-+ *   */
-+#define		rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
-+
-+#define		rFPGA1_TxBlock				0x904	/* Useless now */
-+#define		rFPGA1_DebugSelect			0x908	/* Useless now */
-+#define		rFPGA1_TxInfo					0x90c	/* Useless now */ /* Status report?? */
-+
-+/*
-+ * 5. PageA(0xA00)
-+ *
-+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
-+#define		rCCK0_System					0xa00
-+
-+#define		rCCK0_AFESetting				0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
-+#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
-+
-+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
-+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
-+
-+#define		rCCK0_RxHP					0xa14
-+
-+#define		rCCK0_DSPParameter1			0xa18	/* Timing recovery & Channel estimation threshold */
-+#define		rCCK0_DSPParameter2			0xa1c	/* SQ threshold */
-+
-+#define		rCCK0_TxFilter1				0xa20
-+#define		rCCK0_TxFilter2				0xa24
-+#define		rCCK0_DebugPort				0xa28	/* debug port and Tx filter3 */
-+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
-+#define		rCCK0_TRSSIReport			0xa50
-+#define		rCCK0_RxReport            			0xa54  /* 0xa57 */
-+#define		rCCK0_FACounterLower      		0xa5c  /* 0xa5b */
-+#define		rCCK0_FACounterUpper      		0xa58  /* 0xa5c */
-+
-+/*
-+ * PageB(0xB00)
-+ *   */
-+#define		rPdp_AntA					0xb00
-+#define		rPdp_AntA_4				0xb04
-+#define		rConfig_Pmpd_AntA			0xb28
-+#define		rConfig_ram64x16				0xb2c
-+#define		rConfig_AntA					0xb68
-+#define		rConfig_AntB					0xb6c
-+#define		rPdp_AntB					0xb70
-+#define		rPdp_AntB_4					0xb74
-+#define		rConfig_Pmpd_AntB			0xb98
-+#define		rAPK							0xbd8
-+
-+
-+
-+/*
-+ * 6. PageC(0xC00)
-+ *   */
-+#define		rOFDM0_LSTF					0xc00
-+
-+#define		rOFDM0_TRxPathEnable			0xc04
-+#define		rOFDM0_TRMuxPar				0xc08
-+#define		rOFDM0_TRSWIsolation			0xc0c
-+
-+#define		rOFDM0_XARxAFE				0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
-+#define		rOFDM0_XARxIQImbalance    		0xc14  /* RxIQ imblance matrix */
-+#define		rOFDM0_XBRxAFE			0xc18
-+#define		rOFDM0_XBRxIQImbalance		0xc1c
-+#define		rOFDM0_XCRxAFE			0xc20
-+#define		rOFDM0_XCRxIQImbalance		0xc24
-+#define		rOFDM0_XDRxAFE			0xc28
-+#define		rOFDM0_XDRxIQImbalance		0xc2c
-+
-+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
-+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
-+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
-+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
-+
-+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
-+#define		rOFDM0_CFOandDAGC			0xc44  /* CFO & DAGC */
-+#define		rOFDM0_CCADropThreshold		0xc48 /* CCA Drop threshold */
-+#define		rOFDM0_ECCAThreshold			0xc4c /* energy CCA */
-+
-+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
-+#define		rOFDM0_XAAGCCore2			0xc54
-+#define		rOFDM0_XBAGCCore1			0xc58
-+#define		rOFDM0_XBAGCCore2			0xc5c
-+#define		rOFDM0_XCAGCCore1			0xc60
-+#define		rOFDM0_XCAGCCore2			0xc64
-+#define		rOFDM0_XDAGCCore1			0xc68
-+#define		rOFDM0_XDAGCCore2			0xc6c
-+
-+#define		rOFDM0_AGCParameter1		0xc70
-+#define		rOFDM0_AGCParameter2		0xc74
-+#define		rOFDM0_AGCRSSITable			0xc78
-+#define		rOFDM0_HTSTFAGC				0xc7c
-+
-+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
-+#define		rOFDM0_XATxAFE				0xc84
-+#define		rOFDM0_XBTxIQImbalance		0xc88
-+#define		rOFDM0_XBTxAFE				0xc8c
-+#define		rOFDM0_XCTxIQImbalance		0xc90
-+#define		rOFDM0_XCTxAFE			0xc94
-+#define		rOFDM0_XDTxIQImbalance		0xc98
-+#define		rOFDM0_XDTxAFE				0xc9c
-+
-+#define		rOFDM0_RxIQExtAnta			0xca0
-+#define		rOFDM0_TxCoeff1				0xca4
-+#define		rOFDM0_TxCoeff2				0xca8
-+#define		rOFDM0_TxCoeff3				0xcac
-+#define		rOFDM0_TxCoeff4				0xcb0
-+#define		rOFDM0_TxCoeff5				0xcb4
-+#define		rOFDM0_TxCoeff6				0xcb8
-+#define		rOFDM0_RxHPParameter		0xce0
-+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
-+#define		rOFDM0_FrameSync			0xcf0
-+#define		rOFDM0_DFSReport			0xcf4
-+
-+
-+/*
-+ * 7. PageD(0xD00)
-+ *   */
-+#define		rOFDM1_LSTF					0xd00
-+#define		rOFDM1_TRxPathEnable			0xd04
-+
-+#define		rOFDM1_CFO					0xd08	/* No setting now */
-+#define		rOFDM1_CSI1					0xd10
-+#define		rOFDM1_SBD					0xd14
-+#define		rOFDM1_CSI2					0xd18
-+#define		rOFDM1_CFOTracking			0xd2c
-+#define		rOFDM1_TRxMesaure1			0xd34
-+#define		rOFDM1_IntfDet				0xd3c
-+#define		rOFDM1_csi_fix_mask1				0xd40
-+#define		rOFDM1_csi_fix_mask2				0xd44
-+#define		rOFDM1_PseudoNoiseStateAB	0xd50
-+#define		rOFDM1_PseudoNoiseStateCD	0xd54
-+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
-+
-+#define		rOFDM_PHYCounter1			0xda0  /* cca, parity fail */
-+#define		rOFDM_PHYCounter2			0xda4  /* rate illegal, crc8 fail */
-+#define		rOFDM_PHYCounter3			0xda8  /* MCS not support */
-+
-+#define		rOFDM_ShortCFOAB			0xdac	/* No setting now */
-+#define		rOFDM_ShortCFOCD			0xdb0
-+#define		rOFDM_LongCFOAB				0xdb4
-+#define		rOFDM_LongCFOCD				0xdb8
-+#define		rOFDM_TailCFOAB				0xdbc
-+#define		rOFDM_TailCFOCD				0xdc0
-+#define		rOFDM_PWMeasure1		0xdc4
-+#define		rOFDM_PWMeasure2		0xdc8
-+#define		rOFDM_BWReport				0xdcc
-+#define		rOFDM_AGCReport				0xdd0
-+#define		rOFDM_RxSNR				0xdd4
-+#define		rOFDM_RxEVMCSI				0xdd8
-+#define		rOFDM_SIGReport				0xddc
-+
-+
-+/*
-+ * 8. PageE(0xE00)
-+ *   */
-+#define		rTxAGC_A_Rate18_06			0xe00
-+#define		rTxAGC_A_Rate54_24			0xe04
-+#define		rTxAGC_A_CCK1_Mcs32			0xe08
-+#define		rTxAGC_A_Mcs03_Mcs00		0xe10
-+#define		rTxAGC_A_Mcs07_Mcs04		0xe14
-+#define		rTxAGC_A_Mcs11_Mcs08		0xe18
-+#define		rTxAGC_A_Mcs15_Mcs12		0xe1c
-+
-+#define		rTxAGC_B_Rate18_06			0x830
-+#define		rTxAGC_B_Rate54_24			0x834
-+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
-+#define		rTxAGC_B_Mcs03_Mcs00		0x83c
-+#define		rTxAGC_B_Mcs07_Mcs04		0x848
-+#define		rTxAGC_B_Mcs11_Mcs08		0x84c
-+#define		rTxAGC_B_Mcs15_Mcs12		0x868
-+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
-+
-+#define		rFPGA0_IQK					0xe28
-+#define		rTx_IQK_Tone_A				0xe30
-+#define		rRx_IQK_Tone_A				0xe34
-+#define		rTx_IQK_PI_A					0xe38
-+#define		rRx_IQK_PI_A					0xe3c
-+
-+#define		rTx_IQK						0xe40
-+#define		rRx_IQK						0xe44
-+#define		rIQK_AGC_Pts					0xe48
-+#define		rIQK_AGC_Rsp					0xe4c
-+#define		rTx_IQK_Tone_B				0xe50
-+#define		rRx_IQK_Tone_B				0xe54
-+#define		rTx_IQK_PI_B					0xe58
-+#define		rRx_IQK_PI_B					0xe5c
-+#define		rIQK_AGC_Cont				0xe60
-+
-+#define		rBlue_Tooth					0xe6c
-+#define		rRx_Wait_CCA					0xe70
-+#define		rTx_CCK_RFON					0xe74
-+#define		rTx_CCK_BBON				0xe78
-+#define		rTx_OFDM_RFON				0xe7c
-+#define		rTx_OFDM_BBON				0xe80
-+#define		rTx_To_Rx					0xe84
-+#define		rTx_To_Tx					0xe88
-+#define		rRx_CCK						0xe8c
-+
-+#define		rTx_Power_Before_IQK_A		0xe94
-+#define		rTx_Power_After_IQK_A			0xe9c
-+
-+#define		rRx_Power_Before_IQK_A		0xea0
-+#define		rRx_Power_Before_IQK_A_2		0xea4
-+#define		rRx_Power_After_IQK_A			0xea8
-+#define		rRx_Power_After_IQK_A_2		0xeac
-+
-+#define		rTx_Power_Before_IQK_B		0xeb4
-+#define		rTx_Power_After_IQK_B			0xebc
-+
-+#define		rRx_Power_Before_IQK_B		0xec0
-+#define		rRx_Power_Before_IQK_B_2		0xec4
-+#define		rRx_Power_After_IQK_B			0xec8
-+#define		rRx_Power_After_IQK_B_2		0xecc
-+
-+#define		rRx_OFDM					0xed0
-+#define		rRx_Wait_RIFS				0xed4
-+#define		rRx_TO_Rx					0xed8
-+#define		rStandby						0xedc
-+#define		rSleep						0xee0
-+#define		rPMPD_ANAEN				0xeec
-+
-+/*
-+ * 7. RF Register 0x00-0x2E (RF 8256)
-+ * RF-0222D 0x00-3F
-+ *
-+ * Zebra1 */
-+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
-+#define		rZebra1_TRxEnable1			0x1
-+#define		rZebra1_TRxEnable2			0x2
-+#define		rZebra1_AGC					0x4
-+#define		rZebra1_ChargePump			0x5
-+#define		rZebra1_Channel				0x7	/* RF channel switch */
-+
-+/* #endif */
-+#define		rZebra1_TxGain				0x8	/* Useless now */
-+#define		rZebra1_TxLPF					0x9
-+#define		rZebra1_RxLPF					0xb
-+#define		rZebra1_RxHPFCorner			0xc
-+
-+/* Zebra4 */
-+#define		rGlobalCtrl					0	/* Useless now */
-+#define		rRTL8256_TxLPF				19
-+#define		rRTL8256_RxLPF				11
-+
-+/* RTL8258 */
-+#define		rRTL8258_TxLPF				0x11	/* Useless now */
-+#define		rRTL8258_RxLPF				0x13
-+#define		rRTL8258_RSSILPF				0xa
-+
-+/*
-+ * RL6052 Register definition
-+ *   */
-+#define		RF_AC						0x00	/*  */
-+
-+#define		RF_IQADJ_G1					0x01	/*  */
-+#define		RF_IQADJ_G2					0x02	/*  */
-+
-+#define		RF_POW_TRSW				0x05	/*  */
-+
-+#define		RF_GAIN_RX					0x06	/*  */
-+#define		RF_GAIN_TX					0x07	/*  */
-+
-+#define		RF_TXM_IDAC					0x08	/*  */
-+#define		RF_IPA_G						0x09	/*  */
-+#define		RF_TXBIAS_G					0x0A
-+#define		RF_TXPA_AG					0x0B
-+#define		RF_IPA_A						0x0C	/*  */
-+#define		RF_TXBIAS_A					0x0D
-+#define		RF_BS_PA_APSET_G9_G11		0x0E
-+#define		RF_BS_IQGEN					0x0F	/*  */
-+
-+#define		RF_MODE1					0x10	/*  */
-+#define		RF_MODE2					0x11	/*  */
-+
-+#define		RF_RX_AGC_HP				0x12	/*  */
-+#define		RF_TX_AGC					0x13	/*  */
-+#define		RF_BIAS						0x14	/*  */
-+#define		RF_IPA						0x15	/*  */
-+#define		RF_TXBIAS					0x16
-+#define		RF_POW_ABILITY				0x17	/*  */
-+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
-+#define		RF_TOP						0x19	/*  */
-+
-+#define		RF_RX_G1					0x1A	/*  */
-+#define		RF_RX_G2					0x1B	/*  */
-+
-+#define		RF_RX_BB2					0x1C	/*  */
-+#define		RF_RX_BB1					0x1D	/*  */
-+
-+#define		RF_RCK1						0x1E	/*  */
-+#define		RF_RCK2						0x1F	/*  */
-+
-+#define		RF_TX_G1						0x20	/*  */
-+#define		RF_TX_G2						0x21	/*  */
-+#define		RF_TX_G3						0x22	/*  */
-+
-+#define		RF_TX_BB1					0x23	/*  */
-+
-+#define		RF_T_METER_88E					0x42	/*  */
-+#define		RF_T_METER					0x24	/*  */
-+
-+#define		RF_SYN_G1					0x25	/* RF TX Power control */
-+#define		RF_SYN_G2					0x26	/* RF TX Power control */
-+#define		RF_SYN_G3					0x27	/* RF TX Power control */
-+#define		RF_SYN_G4					0x28	/* RF TX Power control */
-+#define		RF_SYN_G5					0x29	/* RF TX Power control */
-+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
-+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
-+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
-+
-+#define		RF_RCK_OS					0x30	/* RF TX PA control */
-+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
-+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
-+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
-+#define		RF_TX_BIAS_A					0x35
-+#define		RF_TX_BIAS_D					0x36
-+#define		RF_LOBF_9					0x38
-+#define		RF_RXRF_A3					0x3C	/*	 */
-+#define		RF_TRSW						0x3F
-+
-+#define		RF_TXRF_A2					0x41
-+#define		RF_TXPA_G4					0x46
-+#define		RF_TXPA_A4					0x4B
-+#define	RF_0x52					0x52
-+#define		RF_WE_LUT					0xEF
-+
-+
-+/*
-+ * Bit Mask
-+ *
-+ * 1. Page1(0x100) */
-+#define		bBBResetB					0x100	/* Useless now? */
-+#define		bGlobalResetB					0x200
-+#define		bOFDMTxStart					0x4
-+#define		bCCKTxStart					0x8
-+#define		bCRC32Debug					0x100
-+#define		bPMACLoopback				0x10
-+#define		bTxLSIG						0xffffff
-+#define		bOFDMTxRate					0xf
-+#define		bOFDMTxReserved				0x10
-+#define		bOFDMTxLength				0x1ffe0
-+#define		bOFDMTxParity				0x20000
-+#define		bTxHTSIG1					0xffffff
-+#define		bTxHTMCSRate				0x7f
-+#define		bTxHTBW						0x80
-+#define		bTxHTLength					0xffff00
-+#define		bTxHTSIG2					0xffffff
-+#define		bTxHTSmoothing				0x1
-+#define		bTxHTSounding				0x2
-+#define		bTxHTReserved				0x4
-+#define		bTxHTAggreation				0x8
-+#define		bTxHTSTBC					0x30
-+#define		bTxHTAdvanceCoding			0x40
-+#define		bTxHTShortGI					0x80
-+#define		bTxHTNumberHT_LTF			0x300
-+#define		bTxHTCRC8					0x3fc00
-+#define		bCounterReset				0x10000
-+#define		bNumOfOFDMTx				0xffff
-+#define		bNumOfCCKTx					0xffff0000
-+#define		bTxIdleInterval				0xffff
-+#define		bOFDMService					0xffff0000
-+#define		bTxMACHeader				0xffffffff
-+#define		bTxDataInit					0xff
-+#define		bTxHTMode					0x100
-+#define		bTxDataType					0x30000
-+#define		bTxRandomSeed				0xffffffff
-+#define		bCCKTxPreamble				0x1
-+#define		bCCKTxSFD					0xffff0000
-+#define		bCCKTxSIG					0xff
-+#define		bCCKTxService					0xff00
-+#define		bCCKLengthExt					0x8000
-+#define		bCCKTxLength					0xffff0000
-+#define		bCCKTxCRC16					0xffff
-+#define		bCCKTxStatus					0x1
-+#define		bOFDMTxStatus				0x2
-+
-+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
-+
-+/* 2. Page8(0x800) */
-+#define		bRFMOD						0x1	/* Reg 0x800 rFPGA0_RFMOD */
-+#define		bJapanMode					0x2
-+#define		bCCKTxSC						0x30
-+#define		bCCKEn						0x1000000
-+#define		bOFDMEn					0x2000000
-+
-+#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
-+#define		bOFDMTxDACPhase		0x40000
-+#define		bXATxAGC				0x3f
-+
-+#define		bAntennaSelect			0x0300
-+
-+#define		bXBTxAGC                  				0xf00	/* Reg 80c rFPGA0_TxGainStage */
-+#define		bXCTxAGC				0xf000
-+#define		bXDTxAGC				0xf0000
-+
-+#define		bPAStart                  				0xf0000000	/* Useless now */
-+#define		bTRStart				0x00f00000
-+#define		bRFStart				0x0000f000
-+#define		bBBStart				0x000000f0
-+#define		bBBCCKStart			0x0000000f
-+#define		bPAEnd                    				0xf          /* Reg0x814 */
-+#define		bTREnd				0x0f000000
-+#define		bRFEnd				0x000f0000
-+#define		bCCAMask                  				0x000000f0   /* T2R */
-+#define		bR2RCCAMask			0x00000f00
-+#define		bHSSI_R2TDelay			0xf8000000
-+#define		bHSSI_T2RDelay			0xf80000
-+#define		bContTxHSSI               			0x400     /* chane gain at continue Tx */
-+#define		bIGFromCCK			0x200
-+#define		bAGCAddress			0x3f
-+#define		bRxHPTx				0x7000
-+#define		bRxHPT2R				0x38000
-+#define		bRxHPCCKIni			0xc0000
-+#define		bAGCTxCode			0xc00000
-+#define		bAGCRxCode			0x300000
-+
-+#define		b3WireDataLength          			0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
-+#define		b3WireAddressLength		0x400
-+
-+#define		b3WireRFPowerDown         		0x1	/* Useless now
-+ * #define bHWSISelect		0x8 */
-+#define		b5GPAPEPolarity			0x40000000
-+#define		b2GPAPEPolarity			0x80000000
-+#define		bRFSW_TxDefaultAnt		0x3
-+#define		bRFSW_TxOptionAnt		0x30
-+#define		bRFSW_RxDefaultAnt		0x300
-+#define		bRFSW_RxOptionAnt		0x3000
-+#define		bRFSI_3WireData			0x1
-+#define		bRFSI_3WireClock			0x2
-+#define		bRFSI_3WireLoad			0x4
-+#define		bRFSI_3WireRW			0x8
-+#define		bRFSI_3Wire			0xf
-+
-+#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
-+
-+#define		bRFSI_TRSW                		0x20	/* Useless now */
-+#define		bRFSI_TRSWB		0x40
-+#define		bRFSI_ANTSW		0x100
-+#define		bRFSI_ANTSWB		0x200
-+#define		bRFSI_PAPE			0x400
-+#define		bRFSI_PAPE5G		0x800
-+#define		bBandSelect			0x1
-+#define		bHTSIG2_GI			0x80
-+#define		bHTSIG2_Smoothing		0x01
-+#define		bHTSIG2_Sounding		0x02
-+#define		bHTSIG2_Aggreaton		0x08
-+#define		bHTSIG2_STBC		0x30
-+#define		bHTSIG2_AdvCoding		0x40
-+#define		bHTSIG2_NumOfHTLTF	0x300
-+#define		bHTSIG2_CRC8		0x3fc
-+#define		bHTSIG1_MCS		0x7f
-+#define		bHTSIG1_BandWidth		0x80
-+#define		bHTSIG1_HTLength		0xffff
-+#define		bLSIG_Rate			0xf
-+#define		bLSIG_Reserved		0x10
-+#define		bLSIG_Length		0x1fffe
-+#define		bLSIG_Parity			0x20
-+#define		bCCKRxPhase		0x4
-+
-+#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
-+
-+#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
-+
-+#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
-+
-+#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
-+#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
-+#define		bRegulator0Standby		0x1
-+#define		bRegulatorPLLStandby	0x2
-+#define		bRegulator1Standby		0x4
-+#define		bPLLPowerUp		0x8
-+#define		bDPLLPowerUp		0x10
-+#define		bDA10PowerUp		0x20
-+#define		bAD7PowerUp		0x200
-+#define		bDA6PowerUp		0x2000
-+#define		bXtalPowerUp		0x4000
-+#define		b40MDClkPowerUP	0x8000
-+#define		bDA6DebugMode		0x20000
-+#define		bDA6Swing			0x380000
-+
-+#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
-+
-+#define		b80MClkDelay              		0x18000000	/* Useless */
-+#define		bAFEWatchDogEnable	0x20000000
-+
-+#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
-+#define		bXtalCap23			0x3
-+#define		bXtalCap92x				0x0f000000
-+#define		bXtalCap			0x0f000000
-+
-+#define		bIntDifClkEnable          		0x400	/* Useless */
-+#define		bExtSigClkEnable		0x800
-+#define		bBandgapMbiasPowerUp	0x10000
-+#define		bAD11SHGain		0xc0000
-+#define		bAD11InputRange		0x700000
-+#define		bAD11OPCurrent		0x3800000
-+#define		bIPathLoopback		0x4000000
-+#define		bQPathLoopback		0x8000000
-+#define		bAFELoopback		0x10000000
-+#define		bDA10Swing		0x7e0
-+#define		bDA10Reverse		0x800
-+#define		bDAClkSource		0x1000
-+#define		bAD7InputRange		0x6000
-+#define		bAD7Gain			0x38000
-+#define		bAD7OutputCMMode	0x40000
-+#define		bAD7InputCMMode	0x380000
-+#define		bAD7Current		0xc00000
-+#define		bRegulatorAdjust		0x7000000
-+#define		bAD11PowerUpAtTx	0x1
-+#define		bDA10PSAtTx		0x10
-+#define		bAD11PowerUpAtRx	0x100
-+#define		bDA10PSAtRx		0x1000
-+#define		bCCKRxAGCFormat		0x200
-+#define		bPSDFFTSamplepPoint	0xc000
-+#define		bPSDAverageNum		0x3000
-+#define		bIQPathControl		0xc00
-+#define		bPSDFreq			0x3ff
-+#define		bPSDAntennaPath		0x30
-+#define		bPSDIQSwitch		0x40
-+#define		bPSDRxTrigger		0x400000
-+#define		bPSDTxTrigger		0x80000000
-+#define		bPSDSineToneScale		0x7f000000
-+#define		bPSDReport		0xffff
-+
-+/* 3. Page9(0x900) */
-+#define		bOFDMTxSC                 		0x30000000	/* Useless */
-+#define		bCCKTxOn			0x1
-+#define		bOFDMTxOn		0x2
-+#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
-+#define		bDebugItem                		0xff   /* reset debug page and LWord */
-+#define		bAntL				0x10
-+#define		bAntNonHT			0x100
-+#define		bAntHT1			0x1000
-+#define		bAntHT2			0x10000
-+#define		bAntHT1S1			0x100000
-+#define		bAntNonHTS1		0x1000000
-+
-+/* 4. PageA(0xA00) */
-+#define		bCCKBBMode                		0x3	/* Useless */
-+#define		bCCKTxPowerSaving		0x80
-+#define		bCCKRxPowerSaving		0x40
-+
-+#define		bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
-+
-+#define		bCCKScramble              		0x8	/* Useless */
-+#define		bCCKAntDiversity			0x8000
-+#define		bCCKCarrierRecovery		0x4000
-+#define		bCCKTxRate			0x3000
-+#define		bCCKDCCancel		0x0800
-+#define		bCCKISICancel		0x0400
-+#define		bCCKMatchFilter		0x0200
-+#define		bCCKEqualizer		0x0100
-+#define		bCCKPreambleDetect		0x800000
-+#define		bCCKFastFalseCCA		0x400000
-+#define		bCCKChEstStart		0x300000
-+#define		bCCKCCACount		0x080000
-+#define		bCCKcs_lim			0x070000
-+#define		bCCKBistMode		0x80000000
-+#define		bCCKCCAMask		0x40000000
-+#define		bCCKTxDACPhase		0x4
-+#define		bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
-+#define		bCCKr_cp_mode0		0x0100
-+#define		bCCKTxDCOffset		0xf0
-+#define		bCCKRxDCOffset		0xf
-+#define		bCCKCCAMode		0xc000
-+#define		bCCKFalseCS_lim		0x3f00
-+#define		bCCKCS_ratio		0xc00000
-+#define		bCCKCorgBit_sel		0x300000
-+#define		bCCKPD_lim		0x0f0000
-+#define		bCCKNewCCA		0x80000000
-+#define		bCCKRxHPofIG		0x8000
-+#define		bCCKRxIG			0x7f00
-+#define		bCCKLNAPolarity		0x800000
-+#define		bCCKRx1stGain		0x7f0000
-+#define		bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
-+#define		bCCKRxAGCSatLevel		0x1f000000
-+#define		bCCKRxAGCSatCount		0xe0
-+#define		bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
-+#define		bCCKFixedRxAGC		0x8000
-+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
-+#define		bCCKAntennaPolarity		0x2000
-+#define		bCCKTxFilterType		0x0c00
-+#define		bCCKRxAGCReportType		0x0300
-+#define		bCCKRxDAGCEn		0x80000000
-+#define		bCCKRxDAGCPeriod		0x20000000
-+#define		bCCKRxDAGCSatLevel		0x1f000000
-+#define		bCCKTimingRecovery		0x800000
-+#define		bCCKTxC0			0x3f0000
-+#define		bCCKTxC1			0x3f000000
-+#define		bCCKTxC2			0x3f
-+#define		bCCKTxC3			0x3f00
-+#define		bCCKTxC4			0x3f0000
-+#define		bCCKTxC5			0x3f000000
-+#define		bCCKTxC6			0x3f
-+#define		bCCKTxC7			0x3f00
-+#define		bCCKDebugPort		0xff0000
-+#define		bCCKDACDebug		0x0f000000
-+#define		bCCKFalseAlarmEnable	0x8000
-+#define		bCCKFalseAlarmRead	0x4000
-+#define		bCCKTRSSI			0x7f
-+#define		bCCKRxAGCReport		0xfe
-+#define		bCCKRxReport_AntSel	0x80000000
-+#define		bCCKRxReport_MFOff	0x40000000
-+#define		bCCKRxRxReport_SQLoss	0x20000000
-+#define		bCCKRxReport_Pktloss	0x10000000
-+#define		bCCKRxReport_Lockedbit	0x08000000
-+#define		bCCKRxReport_RateError	0x04000000
-+#define		bCCKRxReport_RxRate	0x03000000
-+#define		bCCKRxFACounterLower	0xff
-+#define		bCCKRxFACounterUpper	0xff000000
-+#define		bCCKRxHPAGCStart		0xe000
-+#define		bCCKRxHPAGCFinal		0x1c00
-+#define		bCCKRxFalseAlarmEnable	0x8000
-+#define		bCCKFACounterFreeze	0x4000
-+#define		bCCKTxPathSel		0x10000000
-+#define		bCCKDefaultRxPath		0xc000000
-+#define		bCCKOptionRxPath		0x3000000
-+
-+/* 5. PageC(0xC00) */
-+#define		bNumOfSTF                			0x3	/* Useless */
-+#define		bShift_L			0xc0
-+#define		bGI_TH			0xc
-+#define		bRxPathA			0x1
-+#define		bRxPathB			0x2
-+#define		bRxPathC			0x4
-+#define		bRxPathD			0x8
-+#define		bTxPathA			0x1
-+#define		bTxPathB			0x2
-+#define		bTxPathC			0x4
-+#define		bTxPathD			0x8
-+#define		bTRSSIFreq			0x200
-+#define		bADCBackoff			0x3000
-+#define		bDFIRBackoff			0xc000
-+#define		bTRSSILatchPhase		0x10000
-+#define		bRxIDCOffset			0xff
-+#define		bRxQDCOffset		0xff00
-+#define		bRxDFIRMode		0x1800000
-+#define		bRxDCNFType		0xe000000
-+#define		bRXIQImb_A		0x3ff
-+#define		bRXIQImb_B			0xfc00
-+#define		bRXIQImb_C			0x3f0000
-+#define		bRXIQImb_D		0xffc00000
-+#define		bDC_dc_Notch		0x60000
-+#define		bRxNBINotch		0x1f000000
-+#define		bPD_TH			0xf
-+#define		bPD_TH_Opt2		0xc000
-+#define		bPWED_TH			0x700
-+#define		bIfMF_Win_L		0x800
-+#define		bPD_Option			0x1000
-+#define		bMF_Win_L			0xe000
-+#define		bBW_Search_L		0x30000
-+#define		bwin_enh_L			0xc0000
-+#define		bBW_TH			0x700000
-+#define		bED_TH2			0x3800000
-+#define		bBW_option			0x4000000
-+#define		bRatio_TH			0x18000000
-+#define		bWindow_L			0xe0000000
-+#define		bSBD_Option		0x1
-+#define		bFrame_TH			0x1c
-+#define		bFS_Option			0x60
-+#define		bDC_Slope_check		0x80
-+#define		bFGuard_Counter_DC_L	0xe00
-+#define		bFrame_Weight_Short	0x7000
-+#define		bSub_Tune			0xe00000
-+#define		bFrame_DC_Length		0xe000000
-+#define		bSBD_start_offset		0x30000000
-+#define		bFrame_TH_2		0x7
-+#define		bFrame_GI2_TH		0x38
-+#define		bGI2_Sync_en		0x40
-+#define		bSarch_Short_Early		0x300
-+#define		bSarch_Short_Late		0xc00
-+#define		bSarch_GI2_Late		0x70000
-+#define		bCFOAntSum		0x1
-+#define		bCFOAcc			0x2
-+#define		bCFOStartOffset		0xc
-+#define		bCFOLookBack		0x70
-+#define		bCFOSumWeight		0x80
-+#define		bDAGCEnable		0x10000
-+#define		bTXIQImb_A			0x3ff
-+#define		bTXIQImb_B			0xfc00
-+#define		bTXIQImb_C			0x3f0000
-+#define		bTXIQImb_D			0xffc00000
-+#define		bTxIDCOffset			0xff
-+#define		bTxQDCOffset		0xff00
-+#define		bTxDFIRMode		0x10000
-+#define		bTxPesudoNoiseOn		0x4000000
-+#define		bTxPesudoNoise_A		0xff
-+#define		bTxPesudoNoise_B		0xff00
-+#define		bTxPesudoNoise_C		0xff0000
-+#define		bTxPesudoNoise_D		0xff000000
-+#define		bCCADropOption		0x20000
-+#define		bCCADropThres		0xfff00000
-+#define		bEDCCA_H			0xf
-+#define		bEDCCA_L			0xf0
-+#define		bLambda_ED		0x300
-+#define		bRxInitialGain			0x7f
-+#define		bRxAntDivEn		0x80
-+#define		bRxAGCAddressForLNA	0x7f00
-+#define		bRxHighPowerFlow		0x8000
-+#define		bRxAGCFreezeThres		0xc0000
-+#define		bRxFreezeStep_AGC1	0x300000
-+#define		bRxFreezeStep_AGC2	0xc00000
-+#define		bRxFreezeStep_AGC3	0x3000000
-+#define		bRxFreezeStep_AGC0	0xc000000
-+#define		bRxRssi_Cmp_En		0x10000000
-+#define		bRxQuickAGCEn		0x20000000
-+#define		bRxAGCFreezeThresMode	0x40000000
-+#define		bRxOverFlowCheckType	0x80000000
-+#define		bRxAGCShift			0x7f
-+#define		bTRSW_Tri_Only		0x80
-+#define		bPowerThres		0x300
-+#define		bRxAGCEn			0x1
-+#define		bRxAGCTogetherEn		0x2
-+#define		bRxAGCMin		0x4
-+#define		bRxHP_Ini			0x7
-+#define		bRxHP_TRLNA		0x70
-+#define		bRxHP_RSSI			0x700
-+#define		bRxHP_BBP1		0x7000
-+#define		bRxHP_BBP2		0x70000
-+#define		bRxHP_BBP3		0x700000
-+#define		bRSSI_H                  			0x7f0000     /* the threshold for high power */
-+#define		bRSSI_Gen                			0x7f000000   /* the threshold for ant diversity */
-+#define		bRxSettle_TRSW		0x7
-+#define		bRxSettle_LNA		0x38
-+#define		bRxSettle_RSSI		0x1c0
-+#define		bRxSettle_BBP		0xe00
-+#define		bRxSettle_RxHP		0x7000
-+#define		bRxSettle_AntSW_RSSI	0x38000
-+#define		bRxSettle_AntSW		0xc0000
-+#define		bRxProcessTime_DAGC	0x300000
-+#define		bRxSettle_HSSI		0x400000
-+#define		bRxProcessTime_BBPPW	0x800000
-+#define		bRxAntennaPowerShift	0x3000000
-+#define		bRSSITableSelect		0xc000000
-+#define		bRxHP_Final			0x7000000
-+#define		bRxHTSettle_BBP		0x7
-+#define		bRxHTSettle_HSSI		0x8
-+#define		bRxHTSettle_RxHP		0x70
-+#define		bRxHTSettle_BBPPW		0x80
-+#define		bRxHTSettle_Idle		0x300
-+#define		bRxHTSettle_Reserved	0x1c00
-+#define		bRxHTRxHPEn		0x8000
-+#define		bRxHTAGCFreezeThres	0x30000
-+#define		bRxHTAGCTogetherEn	0x40000
-+#define		bRxHTAGCMin		0x80000
-+#define		bRxHTAGCEn		0x100000
-+#define		bRxHTDAGCEn		0x200000
-+#define		bRxHTRxHP_BBP		0x1c00000
-+#define		bRxHTRxHP_Final		0xe0000000
-+#define		bRxPWRatioTH		0x3
-+#define		bRxPWRatioEn		0x4
-+#define		bRxMFHold			0x3800
-+#define		bRxPD_Delay_TH1		0x38
-+#define		bRxPD_Delay_TH2		0x1c0
-+#define		bRxPD_DC_COUNT_MAX	0x600
-+/* #define bRxMF_Hold               0x3800 */
-+#define		bRxPD_Delay_TH		0x8000
-+#define		bRxProcess_Delay		0xf0000
-+#define		bRxSearchrange_GI2_Early	0x700000
-+#define		bRxFrame_Guard_Counter_L	0x3800000
-+#define		bRxSGI_Guard_L		0xc000000
-+#define		bRxSGI_Search_L		0x30000000
-+#define		bRxSGI_TH			0xc0000000
-+#define		bDFSCnt0			0xff
-+#define		bDFSCnt1			0xff00
-+#define		bDFSFlag			0xf0000
-+#define		bMFWeightSum		0x300000
-+#define		bMinIdxTH			0x7f000000
-+#define		bDAFormat			0x40000
-+#define		bTxChEmuEnable		0x01000000
-+#define		bTRSWIsolation_A		0x7f
-+#define		bTRSWIsolation_B		0x7f00
-+#define		bTRSWIsolation_C		0x7f0000
-+#define		bTRSWIsolation_D		0x7f000000
-+#define		bExtLNAGain		0x7c00
-+
-+/* 6. PageE(0xE00) */
-+#define		bSTBCEn                  			0x4	/* Useless */
-+#define		bAntennaMapping		0x10
-+#define		bNss			0x20
-+#define		bCFOAntSumD		0x200
-+#define		bPHYCounterReset		0x8000000
-+#define		bCFOReportGet		0x4000000
-+#define		bOFDMContinueTx		0x10000000
-+#define		bOFDMSingleCarrier		0x20000000
-+#define		bOFDMSingleTone		0x40000000
-+/* #define bRxPath1                 0x01 */
-+/* #define bRxPath2                 0x02 */
-+/* #define bRxPath3                 0x04 */
-+/* #define bRxPath4                 0x08 */
-+/* #define bTxPath1                 0x10 */
-+/* #define bTxPath2                 0x20 */
-+#define		bHTDetect			0x100
-+#define		bCFOEn			0x10000
-+#define		bCFOValue			0xfff00000
-+#define		bSigTone_Re			0x3f
-+#define		bSigTone_Im			0x7f00
-+#define		bCounter_CCA		0xffff
-+#define		bCounter_ParityFail		0xffff0000
-+#define		bCounter_RateIllegal		0xffff
-+#define		bCounter_CRC8Fail		0xffff0000
-+#define		bCounter_MCSNoSupport	0xffff
-+#define		bCounter_FastSync		0xffff
-+#define		bShortCFO			0xfff
-+#define		bShortCFOTLength         		12   /* total */
-+#define		bShortCFOFLength         		11   /* fraction */
-+#define		bLongCFO			0x7ff
-+#define		bLongCFOTLength		11
-+#define		bLongCFOFLength		11
-+#define		bTailCFO			0x1fff
-+#define		bTailCFOTLength		13
-+#define		bTailCFOFLength		12
-+#define		bmax_en_pwdB		0xffff
-+#define		bCC_power_dB		0xffff0000
-+#define		bnoise_pwdB		0xffff
-+#define		bPowerMeasTLength	10
-+#define		bPowerMeasFLength	3
-+#define		bRx_HT_BW		0x1
-+#define		bRxSC			0x6
-+#define		bRx_HT			0x8
-+#define		bNB_intf_det_on		0x1
-+#define		bIntf_win_len_cfg		0x30
-+#define		bNB_Intf_TH_cfg		0x1c0
-+#define		bRFGain			0x3f
-+#define		bTableSel			0x40
-+#define		bTRSW			0x80
-+#define		bRxSNR_A			0xff
-+#define		bRxSNR_B			0xff00
-+#define		bRxSNR_C			0xff0000
-+#define		bRxSNR_D			0xff000000
-+#define		bSNREVMTLength		8
-+#define		bSNREVMFLength		1
-+#define		bCSI1st			0xff
-+#define		bCSI2nd			0xff00
-+#define		bRxEVM1st			0xff0000
-+#define		bRxEVM2nd		0xff000000
-+#define		bSIGEVM			0xff
-+#define		bPWDB			0xff00
-+#define		bSGIEN			0x10000
-+
-+#define		bSFactorQAM1             		0xf	/* Useless */
-+#define		bSFactorQAM2		0xf0
-+#define		bSFactorQAM3		0xf00
-+#define		bSFactorQAM4		0xf000
-+#define		bSFactorQAM5		0xf0000
-+#define		bSFactorQAM6		0xf0000
-+#define		bSFactorQAM7		0xf00000
-+#define		bSFactorQAM8		0xf000000
-+#define		bSFactorQAM9		0xf0000000
-+#define		bCSIScheme			0x100000
-+
-+#define		bNoiseLvlTopSet          		0x3	/* Useless */
-+#define		bChSmooth			0x4
-+#define		bChSmoothCfg1		0x38
-+#define		bChSmoothCfg2		0x1c0
-+#define		bChSmoothCfg3		0xe00
-+#define		bChSmoothCfg4		0x7000
-+#define		bMRCMode		0x800000
-+#define		bTHEVMCfg			0x7000000
-+
-+#define		bLoopFitType             			0x1	/* Useless */
-+#define		bUpdCFO			0x40
-+#define		bUpdCFOOffData		0x80
-+#define		bAdvUpdCFO		0x100
-+#define		bAdvTimeCtrl		0x800
-+#define		bUpdClko			0x1000
-+#define		bFC				0x6000
-+#define		bTrackingMode		0x8000
-+#define		bPhCmpEnable		0x10000
-+#define		bUpdClkoLTF			0x20000
-+#define		bComChCFO		0x40000
-+#define		bCSIEstiMode		0x80000
-+#define		bAdvUpdEqz		0x100000
-+#define		bUChCfg			0x7000000
-+#define		bUpdEqz			0x8000000
-+
-+/* Rx Pseduo noise */
-+#define		bRxPesudoNoiseOn         		0x20000000	/* Useless */
-+#define		bRxPesudoNoise_A		0xff
-+#define		bRxPesudoNoise_B		0xff00
-+#define		bRxPesudoNoise_C		0xff0000
-+#define		bRxPesudoNoise_D		0xff000000
-+#define		bPesudoNoiseState_A	0xffff
-+#define		bPesudoNoiseState_B	0xffff0000
-+#define		bPesudoNoiseState_C		0xffff
-+#define		bPesudoNoiseState_D	0xffff0000
-+
-+/* 7. RF Register
-+ * Zebra1 */
-+#define		bZebra1_HSSIEnable        		0x8		/* Useless */
-+#define		bZebra1_TRxControl		0xc00
-+#define		bZebra1_TRxGainSetting	0x07f
-+#define		bZebra1_RxCorner		0xc00
-+#define		bZebra1_TxChargePump	0x38
-+#define		bZebra1_RxChargePump	0x7
-+#define		bZebra1_ChannelNum	0xf80
-+#define		bZebra1_TxLPFBW		0x400
-+#define		bZebra1_RxLPFBW		0x600
-+
-+/* Zebra4 */
-+#define		bRTL8256RegModeCtrl1      	0x100	/* Useless */
-+#define		bRTL8256RegModeCtrl0	0x40
-+#define		bRTL8256_TxLPFBW	0x18
-+#define		bRTL8256_RxLPFBW	0x600
-+
-+/* RTL8258 */
-+#define		bRTL8258_TxLPFBW          	0xc	/* Useless */
-+#define		bRTL8258_RxLPFBW	0xc00
-+#define		bRTL8258_RSSILPFBW	0xc0
-+
-+
-+/*
-+ * Other Definition
-+ *   */
-+
-+/* byte endable for sb_write */
-+#define		bByte0                    			0x1	/* Useless */
-+#define		bByte1			0x2
-+#define		bByte2			0x4
-+#define		bByte3			0x8
-+#define		bWord0			0x3
-+#define		bWord1			0xc
-+#define		bDWord			0xf
-+
-+/* for PutRegsetting & GetRegSetting BitMask */
-+#define		bMaskByte0                		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
-+#define		bMaskByte1		0xff00
-+#define		bMaskByte2		0xff0000
-+#define		bMaskByte3		0xff000000
-+#define		bMaskHWord		0xffff0000
-+#define		bMaskLWord		0x0000ffff
-+#define		bMaskDWord		0xffffffff
-+#define		bMaskH3Bytes				0xffffff00
-+#define		bMask12Bits				0xfff
-+#define		bMaskH4Bits				0xf0000000
-+#define		bMaskOFDM_D			0xffc00000
-+#define		bMaskCCK				0x3f3f3f3f
-+
-+
-+
-+#define		bEnable                   0x1	/* Useless */
-+#define		bDisable                  0x0
-+
-+#define		LeftAntenna               			0x0	/* Useless */
-+#define		RightAntenna		0x1
-+
-+#define		tCheckTxStatus            		500   /* 500ms */ /* Useless */
-+#define		tUpdateRxCounter          		100   /* 100ms */
-+
-+#define		rateCCK     				0	/* Useless */
-+#define		rateOFDM				1
-+#define		rateHT					2
-+
-+/* define Register-End */
-+#define		bPMAC_End                 		0x1ff	/* Useless */
-+#define		bFPGAPHY0_End		0x8ff
-+#define		bFPGAPHY1_End		0x9ff
-+#define		bCCKPHY0_End		0xaff
-+#define		bOFDMPHY0_End		0xcff
-+#define		bOFDMPHY1_End		0xdff
-+
-+/* define max debug item in each debug page
-+ * #define bMaxItem_FPGA_PHY0        0x9
-+ * #define bMaxItem_FPGA_PHY1        0x3
-+ * #define bMaxItem_PHY_11B          0x16
-+ * #define bMaxItem_OFDM_PHY0        0x29
-+ * #define bMaxItem_OFDM_PHY1        0x0 */
-+
-+#define		bPMACControl              		0x0		/* Useless */
-+#define		bWMACControl		0x1
-+#define		bWNICControl		0x2
-+
-+#define		PathA                     			0x0	/* Useless */
-+#define		PathB			0x1
-+#define		PathC			0x2
-+#define		PathD			0x3
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8188EPwrSeq.h b/drivers/staging/rtl8723cs/include/Hal8188EPwrSeq.h
-new file mode 100644
-index 000000000000..46c61abacb92
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8188EPwrSeq.h
-@@ -0,0 +1,170 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+#ifndef __HAL8188EPWRSEQ_H__
-+#define __HAL8188EPWRSEQ_H__
-+
-+#include "HalPwrSeqCmd.h"
-+
-+/*
-+	Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
-+	There are 6 HW Power States:
-+	0: POFF--Power Off
-+	1: PDN--Power Down
-+	2: CARDEMU--Card Emulation
-+	3: ACT--Active Mode
-+	4: LPS--Low Power State
-+	5: SUS--Suspend
-+
-+	The transision from different states are defined below
-+	TRANS_CARDEMU_TO_ACT
-+	TRANS_ACT_TO_CARDEMU
-+	TRANS_CARDEMU_TO_SUS
-+	TRANS_SUS_TO_CARDEMU
-+	TRANS_CARDEMU_TO_PDN
-+	TRANS_ACT_TO_LPS
-+	TRANS_LPS_TO_ACT
-+
-+	TRANS_END
-+
-+    PWR SEQ Version: rtl8188E_PwrSeq_V09.h
-+*/
-+#define	RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS	10
-+#define	RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS	10
-+#define	RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS	10
-+#define	RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS	10
-+#define	RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS	10
-+#define	RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS	10
-+#define	RTL8188E_TRANS_ACT_TO_LPS_STEPS	15
-+#define	RTL8188E_TRANS_LPS_TO_ACT_STEPS	15
-+#define	RTL8188E_TRANS_END_STEPS	1
-+
-+
-+#define RTL8188E_TRANS_CARDEMU_TO_ACT														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0}, /* 0x02[1:0] = 0	reset BB*/			\
-+	{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/	\
-+
-+#define RTL8188E_TRANS_ACT_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
-+
-+#define RTL8188E_TRANS_CARDEMU_TO_SUS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT7}, /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */	\
-+	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */	\
-+	{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register  0xfe10[4]=1 */	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8188E_TRANS_SUS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
-+
-+#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*  0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */	\
-+	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */	\
-+	{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register  0xfe10[4]=1 */	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
-+
-+#define RTL8188E_TRANS_CARDEMU_TO_PDN												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
-+
-+#define RTL8188E_TRANS_PDN_TO_CARDEMU												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
-+
-+	/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
-+#define RTL8188E_TRANS_ACT_TO_LPS														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/	\
-+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
-+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
-+
-+
-+#define RTL8188E_TRANS_LPS_TO_ACT															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
-+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
-+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
-+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
-+
-+#define RTL8188E_TRANS_END															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
-+
-+
-+	extern WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
-+
-+#endif /* __HAL8188EPWRSEQ_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/Hal8188FPhyCfg.h b/drivers/staging/rtl8723cs/include/Hal8188FPhyCfg.h
-new file mode 100644
-index 000000000000..1bc60dc527d6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8188FPhyCfg.h
-@@ -0,0 +1,120 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8188FPHYCFG_H__
-+#define __INC_HAL8188FPHYCFG_H__
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+#define LOOP_LIMIT				5
-+#define MAX_STALL_TIME			50		/* us */
-+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
-+#define MAX_TXPWR_IDX_NMODE_92S	63
-+#define Reset_Cnt_Limit			3
-+
-+#ifdef CONFIG_PCI_HCI
-+	#define MAX_AGGR_NUM	0x0B
-+#else
-+	#define MAX_AGGR_NUM	0x07
-+#endif /* CONFIG_PCI_HCI */
-+
-+
-+/*--------------------------Define Parameters End-------------------------------*/
-+
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+/*------------------------------Define structure End----------------------------*/
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+u32
-+PHY_QueryBBReg_8188F(
-+		PADAPTER	Adapter,
-+		u32		RegAddr,
-+		u32		BitMask
-+);
-+
-+void
-+PHY_SetBBReg_8188F(
-+		PADAPTER	Adapter,
-+		u32		RegAddr,
-+		u32		BitMask,
-+		u32		Data
-+);
-+
-+u32
-+PHY_QueryRFReg_8188F(
-+		PADAPTER			Adapter,
-+		enum rf_path			eRFPath,
-+		u32				RegAddr,
-+		u32				BitMask
-+);
-+
-+void
-+PHY_SetRFReg_8188F(
-+		PADAPTER			Adapter,
-+		enum rf_path			eRFPath,
-+		u32				RegAddr,
-+		u32				BitMask,
-+		u32				Data
-+);
-+
-+/* MAC/BB/RF HAL config */
-+int PHY_BBConfig8188F(PADAPTER	Adapter);
-+
-+int PHY_RFConfig8188F(PADAPTER	Adapter);
-+
-+s32 PHY_MACConfig8188F(PADAPTER padapter);
-+
-+int
-+PHY_ConfigRFWithParaFile_8188F(
-+		PADAPTER			Adapter,
-+		u8					*pFileName,
-+	enum rf_path				eRFPath
-+);
-+
-+void
-+PHY_SetTxPowerIndex_8188F(
-+		PADAPTER			Adapter,
-+		u32					PowerIndex,
-+		enum rf_path			RFPath,
-+		u8					Rate
-+);
-+
-+void
-+PHY_SetTxPowerLevel8188F(
-+		PADAPTER		Adapter,
-+		u8			channel
-+);
-+
-+void rtl8188f_set_txpwr_done(_adapter *adapter);
-+
-+void
-+PHY_SetSwChnlBWMode8188F(
-+		PADAPTER			Adapter,
-+		u8					channel,
-+		enum channel_width	Bandwidth,
-+		u8					Offset40,
-+		u8					Offset80
-+);
-+
-+void phy_set_rf_path_switch_8188f(
-+		struct		dm_struct *phydm,
-+		bool		bMain
-+);
-+
-+void BBTurnOnBlock_8188F(_adapter *adapter);
-+
-+/*--------------------------Exported Function prototype End---------------------*/
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8188FPhyReg.h b/drivers/staging/rtl8723cs/include/Hal8188FPhyReg.h
-new file mode 100644
-index 000000000000..a831faade96d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8188FPhyReg.h
-@@ -0,0 +1,1165 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8188FPHYREG_H__
-+#define __INC_HAL8188FPHYREG_H__
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+/* ************************************************************
-+ * Regsiter offset definition
-+ * ************************************************************ */
-+
-+/*
-+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
-+ * 3. RF register 0x00-2E
-+ * 4. Bit Mask for BB/RF register
-+ * 5. Other defintion for BB/RF R/W
-+ *   */
-+
-+
-+/*
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 1. Page1(0x100)
-+ *   */
-+#define		rPMAC_Reset					0x100
-+#define		rPMAC_TxStart					0x104
-+#define		rPMAC_TxLegacySIG				0x108
-+#define		rPMAC_TxHTSIG1				0x10c
-+#define		rPMAC_TxHTSIG2				0x110
-+#define		rPMAC_PHYDebug				0x114
-+#define		rPMAC_TxPacketNum				0x118
-+#define		rPMAC_TxIdle					0x11c
-+#define		rPMAC_TxMACHeader0			0x120
-+#define		rPMAC_TxMACHeader1			0x124
-+#define		rPMAC_TxMACHeader2			0x128
-+#define		rPMAC_TxMACHeader3			0x12c
-+#define		rPMAC_TxMACHeader4			0x130
-+#define		rPMAC_TxMACHeader5			0x134
-+#define		rPMAC_TxDataType				0x138
-+#define		rPMAC_TxRandomSeed			0x13c
-+#define		rPMAC_CCKPLCPPreamble			0x140
-+#define		rPMAC_CCKPLCPHeader			0x144
-+#define		rPMAC_CCKCRC16				0x148
-+#define		rPMAC_OFDMRxCRC32OK			0x170
-+#define		rPMAC_OFDMRxCRC32Er			0x174
-+#define		rPMAC_OFDMRxParityEr			0x178
-+#define		rPMAC_OFDMRxCRC8Er			0x17c
-+#define		rPMAC_CCKCRxRC16Er			0x180
-+#define		rPMAC_CCKCRxRC32Er			0x184
-+#define		rPMAC_CCKCRxRC32OK			0x188
-+#define		rPMAC_TxStatus					0x18c
-+
-+/*
-+ * 2. Page2(0x200)
-+ *
-+ * The following two definition are only used for USB interface. */
-+#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
-+#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
-+
-+/*
-+ * 3. Page8(0x800)
-+ *   */
-+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
-+
-+#define		rFPGA0_TxInfo				0x804	/* Status report?? */
-+#define		rFPGA0_PSDFunction			0x808
-+
-+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
-+
-+#define		rFPGA0_RFTiming1			0x810	/* Useless now */
-+#define		rFPGA0_RFTiming2			0x814
-+
-+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
-+#define		rFPGA0_XA_HSSIParameter2		0x824
-+#define		rFPGA0_XB_HSSIParameter1		0x828
-+#define		rFPGA0_XB_HSSIParameter2		0x82c
-+#define		rTxAGC_B_Rate18_06				0x830
-+#define		rTxAGC_B_Rate54_24				0x834
-+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
-+#define		rTxAGC_B_Mcs03_Mcs00			0x83c
-+
-+#define		rTxAGC_B_Mcs07_Mcs04			0x848
-+#define		rTxAGC_B_Mcs11_Mcs08			0x84c
-+
-+#define		rFPGA0_XA_LSSIParameter		0x840
-+#define		rFPGA0_XB_LSSIParameter		0x844
-+
-+#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
-+#define		rFPGA0_RFSleepUpParameter		0x854
-+
-+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
-+#define		rFPGA0_XCD_SwitchControl		0x85c
-+
-+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
-+#define		rFPGA0_XB_RFInterfaceOE		0x864
-+
-+#define		rTxAGC_B_Mcs15_Mcs12			0x868
-+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
-+
-+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
-+#define		rFPGA0_XCD_RFInterfaceSW		0x874
-+
-+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
-+#define		rFPGA0_XCD_RFParameter		0x87c
-+
-+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
-+#define		rFPGA0_AnalogParameter2		0x884
-+#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
-+#define		rFPGA0_AnalogParameter4		0x88c
-+
-+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
-+#define		rFPGA0_XB_LSSIReadBack		0x8a4
-+#define		rFPGA0_XC_LSSIReadBack		0x8a8
-+#define		rFPGA0_XD_LSSIReadBack		0x8ac
-+
-+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
-+#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
-+#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
-+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
-+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
-+
-+/*
-+ * 4. Page9(0x900)
-+ *   */
-+#define		rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
-+
-+#define		rFPGA1_TxBlock				0x904	/* Useless now */
-+#define		rFPGA1_DebugSelect			0x908	/* Useless now */
-+#define		rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
-+#define	rS0S1_PathSwitch			0x948
-+
-+/*
-+ * 5. PageA(0xA00)
-+ *
-+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
-+#define		rCCK0_System				0xa00
-+
-+#define		rCCK0_AFESetting			0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
-+#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
-+
-+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
-+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
-+
-+#define		rCCK0_RxHP					0xa14
-+
-+#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
-+#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
-+
-+#define		rCCK0_TxFilter1				0xa20
-+#define		rCCK0_TxFilter2				0xa24
-+#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
-+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
-+#define		rCCK0_TRSSIReport		0xa50
-+#define		rCCK0_RxReport            		0xa54  /* 0xa57 */
-+#define		rCCK0_FACounterLower      	0xa5c  /* 0xa5b */
-+#define		rCCK0_FACounterUpper      	0xa58  /* 0xa5c
-+ *
-+ * PageB(0xB00)
-+ *   */
-+#define		rPdp_AntA				0xb00
-+#define		rPdp_AntA_4				0xb04
-+#define		rConfig_Pmpd_AntA			0xb28
-+#define		rConfig_AntA				0xb68
-+#define		rConfig_AntB				0xb6c
-+#define		rPdp_AntB					0xb70
-+#define		rPdp_AntB_4				0xb74
-+#define		rConfig_Pmpd_AntB			0xb98
-+#define		rAPK						0xbd8
-+
-+/*
-+ * 6. PageC(0xC00)
-+ *   */
-+#define		rOFDM0_LSTF				0xc00
-+
-+#define		rOFDM0_TRxPathEnable		0xc04
-+#define		rOFDM0_TRMuxPar			0xc08
-+#define		rOFDM0_TRSWIsolation		0xc0c
-+
-+#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
-+#define		rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
-+#define		rOFDM0_XBRxAFE		0xc18
-+#define		rOFDM0_XBRxIQImbalance	0xc1c
-+#define		rOFDM0_XCRxAFE		0xc20
-+#define		rOFDM0_XCRxIQImbalance	0xc24
-+#define		rOFDM0_XDRxAFE		0xc28
-+#define		rOFDM0_XDRxIQImbalance	0xc2c
-+
-+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
-+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
-+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
-+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
-+
-+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
-+#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
-+#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
-+#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
-+
-+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
-+#define		rOFDM0_XAAGCCore2			0xc54
-+#define		rOFDM0_XBAGCCore1			0xc58
-+#define		rOFDM0_XBAGCCore2			0xc5c
-+#define		rOFDM0_XCAGCCore1			0xc60
-+#define		rOFDM0_XCAGCCore2			0xc64
-+#define		rOFDM0_XDAGCCore1			0xc68
-+#define		rOFDM0_XDAGCCore2			0xc6c
-+
-+#define		rOFDM0_AGCParameter1			0xc70
-+#define		rOFDM0_AGCParameter2			0xc74
-+#define		rOFDM0_AGCRSSITable			0xc78
-+#define		rOFDM0_HTSTFAGC				0xc7c
-+
-+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
-+#define		rOFDM0_XATxAFE				0xc84
-+#define		rOFDM0_XBTxIQImbalance		0xc88
-+#define		rOFDM0_XBTxAFE				0xc8c
-+#define		rOFDM0_XCTxIQImbalance		0xc90
-+#define		rOFDM0_XCTxAFE			0xc94
-+#define		rOFDM0_XDTxIQImbalance		0xc98
-+#define		rOFDM0_XDTxAFE				0xc9c
-+
-+#define		rOFDM0_RxIQExtAnta			0xca0
-+#define		rOFDM0_TxCoeff1				0xca4
-+#define		rOFDM0_TxCoeff2				0xca8
-+#define		rOFDM0_TxCoeff3				0xcac
-+#define		rOFDM0_TxCoeff4				0xcb0
-+#define		rOFDM0_TxCoeff5				0xcb4
-+#define		rOFDM0_TxCoeff6				0xcb8
-+#define		rOFDM0_RxHPParameter			0xce0
-+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
-+#define		rOFDM0_FrameSync				0xcf0
-+#define		rOFDM0_DFSReport				0xcf4
-+
-+/*
-+ * 7. PageD(0xD00)
-+ *   */
-+#define		rOFDM1_LSTF					0xd00
-+#define		rOFDM1_TRxPathEnable			0xd04
-+
-+#define		rOFDM1_CFO						0xd08	/* No setting now */
-+#define		rOFDM1_CSI1					0xd10
-+#define		rOFDM1_SBD						0xd14
-+#define		rOFDM1_CSI2					0xd18
-+#define		rOFDM1_CFOTracking			0xd2c
-+#define		rOFDM1_TRxMesaure1			0xd34
-+#define		rOFDM1_IntfDet					0xd3c
-+#define		rOFDM1_PseudoNoiseStateAB		0xd50
-+#define		rOFDM1_PseudoNoiseStateCD		0xd54
-+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
-+
-+#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
-+#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
-+#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
-+
-+#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
-+#define		rOFDM_ShortCFOCD				0xdb0
-+#define		rOFDM_LongCFOAB				0xdb4
-+#define		rOFDM_LongCFOCD				0xdb8
-+#define		rOFDM_TailCFOAB				0xdbc
-+#define		rOFDM_TailCFOCD				0xdc0
-+#define		rOFDM_PWMeasure1		0xdc4
-+#define		rOFDM_PWMeasure2		0xdc8
-+#define		rOFDM_BWReport				0xdcc
-+#define		rOFDM_AGCReport				0xdd0
-+#define		rOFDM_RxSNR					0xdd4
-+#define		rOFDM_RxEVMCSI				0xdd8
-+#define		rOFDM_SIGReport				0xddc
-+
-+
-+/*
-+ * 8. PageE(0xE00)
-+ *   */
-+#define		rTxAGC_A_Rate18_06			0xe00
-+#define		rTxAGC_A_Rate54_24			0xe04
-+#define		rTxAGC_A_CCK1_Mcs32			0xe08
-+#define		rTxAGC_A_Mcs03_Mcs00			0xe10
-+#define		rTxAGC_A_Mcs07_Mcs04			0xe14
-+#define		rTxAGC_A_Mcs11_Mcs08			0xe18
-+#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
-+
-+#define		rFPGA0_IQK					0xe28
-+#define		rTx_IQK_Tone_A				0xe30
-+#define		rRx_IQK_Tone_A				0xe34
-+#define		rTx_IQK_PI_A					0xe38
-+#define		rRx_IQK_PI_A					0xe3c
-+
-+#define		rTx_IQK						0xe40
-+#define		rRx_IQK						0xe44
-+#define		rIQK_AGC_Pts					0xe48
-+#define		rIQK_AGC_Rsp					0xe4c
-+#define		rTx_IQK_Tone_B				0xe50
-+#define		rRx_IQK_Tone_B				0xe54
-+#define		rTx_IQK_PI_B					0xe58
-+#define		rRx_IQK_PI_B					0xe5c
-+#define		rIQK_AGC_Cont				0xe60
-+
-+#define		rBlue_Tooth					0xe6c
-+#define		rRx_Wait_CCA					0xe70
-+#define		rTx_CCK_RFON					0xe74
-+#define		rTx_CCK_BBON				0xe78
-+#define		rTx_OFDM_RFON				0xe7c
-+#define		rTx_OFDM_BBON				0xe80
-+#define		rTx_To_Rx					0xe84
-+#define		rTx_To_Tx					0xe88
-+#define		rRx_CCK						0xe8c
-+
-+#define		rTx_Power_Before_IQK_A		0xe94
-+#define		rTx_Power_After_IQK_A			0xe9c
-+
-+#define		rRx_Power_Before_IQK_A		0xea0
-+#define		rRx_Power_Before_IQK_A_2		0xea4
-+#define		rRx_Power_After_IQK_A			0xea8
-+#define		rRx_Power_After_IQK_A_2		0xeac
-+
-+#define		rTx_Power_Before_IQK_B		0xeb4
-+#define		rTx_Power_After_IQK_B			0xebc
-+
-+#define		rRx_Power_Before_IQK_B		0xec0
-+#define		rRx_Power_Before_IQK_B_2		0xec4
-+#define		rRx_Power_After_IQK_B			0xec8
-+#define		rRx_Power_After_IQK_B_2		0xecc
-+
-+#define		rRx_OFDM					0xed0
-+#define		rRx_Wait_RIFS				0xed4
-+#define		rRx_TO_Rx					0xed8
-+#define		rStandby						0xedc
-+#define		rSleep						0xee0
-+#define		rPMPD_ANAEN				0xeec
-+
-+/*
-+ * 7. RF Register 0x00-0x2E (RF 8256)
-+ * RF-0222D 0x00-3F
-+ *
-+ * Zebra1 */
-+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
-+#define		rZebra1_TRxEnable1				0x1
-+#define		rZebra1_TRxEnable2				0x2
-+#define		rZebra1_AGC					0x4
-+#define		rZebra1_ChargePump			0x5
-+#define		rZebra1_Channel				0x7	/* RF channel switch */
-+
-+/* #endif */
-+#define		rZebra1_TxGain					0x8	/* Useless now */
-+#define		rZebra1_TxLPF					0x9
-+#define		rZebra1_RxLPF					0xb
-+#define		rZebra1_RxHPFCorner			0xc
-+
-+/* Zebra4 */
-+#define		rGlobalCtrl						0	/* Useless now */
-+#define		rRTL8256_TxLPF					19
-+#define		rRTL8256_RxLPF					11
-+
-+/* RTL8258 */
-+#define		rRTL8258_TxLPF					0x11	/* Useless now */
-+#define		rRTL8258_RxLPF					0x13
-+#define		rRTL8258_RSSILPF				0xa
-+
-+/*
-+ * RL6052 Register definition
-+ *   */
-+#define		RF_AC						0x00	/*  */
-+
-+#define		RF_IQADJ_G1				0x01	/*  */
-+#define		RF_IQADJ_G2				0x02	/*  */
-+#define		RF_BS_PA_APSET_G1_G4		0x03
-+#define		RF_BS_PA_APSET_G5_G8		0x04
-+#define		RF_POW_TRSW				0x05	/*  */
-+
-+#define		RF_GAIN_RX					0x06	/*  */
-+#define		RF_GAIN_TX					0x07	/*  */
-+
-+#define		RF_TXM_IDAC				0x08	/*  */
-+#define		RF_IPA_G					0x09	/*  */
-+#define		RF_TXBIAS_G				0x0A
-+#define		RF_TXPA_AG					0x0B
-+#define		RF_IPA_A					0x0C	/*  */
-+#define		RF_TXBIAS_A				0x0D
-+#define		RF_BS_PA_APSET_G9_G11	0x0E
-+#define		RF_BS_IQGEN				0x0F	/*  */
-+
-+#define		RF_MODE1					0x10	/*  */
-+#define		RF_MODE2					0x11	/*  */
-+
-+#define		RF_RX_AGC_HP				0x12	/*  */
-+#define		RF_TX_AGC					0x13	/*  */
-+#define		RF_BIAS						0x14	/*  */
-+#define		RF_IPA						0x15	/*  */
-+#define		RF_TXBIAS					0x16
-+#define		RF_POW_ABILITY			0x17	/*  */
-+#define		RF_MODE_AG				0x18	/*  */
-+#define		rRfChannel					0x18	/* RF channel and BW switch */
-+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
-+#define		RF_TOP						0x19	/*  */
-+
-+#define		RF_RX_G1					0x1A	/*  */
-+#define		RF_RX_G2					0x1B	/*  */
-+
-+#define		RF_RX_BB2					0x1C	/*  */
-+#define		RF_RX_BB1					0x1D	/*  */
-+
-+#define		RF_RCK1					0x1E	/*  */
-+#define		RF_RCK2					0x1F	/*  */
-+
-+#define		RF_TX_G1					0x20	/*  */
-+#define		RF_TX_G2					0x21	/*  */
-+#define		RF_TX_G3					0x22	/*  */
-+
-+#define		RF_TX_BB1					0x23	/*  */
-+
-+#define		RF_T_METER					0x24	/*  */
-+
-+#define		RF_SYN_G1					0x25	/* RF TX Power control */
-+#define		RF_SYN_G2					0x26	/* RF TX Power control */
-+#define		RF_SYN_G3					0x27	/* RF TX Power control */
-+#define		RF_SYN_G4					0x28	/* RF TX Power control */
-+#define		RF_SYN_G5					0x29	/* RF TX Power control */
-+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
-+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
-+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
-+
-+#define		RF_RCK_OS					0x30	/* RF TX PA control */
-+
-+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
-+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
-+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
-+#define	RF_TX_BIAS_A				0x35
-+#define	RF_TX_BIAS_D				0x36
-+#define	RF_LOBF_9					0x38
-+#define 	RF_RXRF_A3					0x3C	/*	 */
-+#define	RF_TRSW					0x3F
-+
-+#define	RF_TXRF_A2					0x41
-+#define	RF_TXPA_G4					0x46
-+#define	RF_TXPA_A4					0x4B
-+#define	RF_0x52					0x52
-+#define		RF_RXG_MIX_SWBW				0x87
-+#define		RF_DBG_LP_RX2				0xDF
-+#define	RF_WE_LUT					0xEF
-+#define	RF_S0S1					0xB0
-+
-+#define RF_TX_GAIN_OFFSET_8188F(_val) (abs((_val)) | (((_val) > 0) ? BIT5 : 0))
-+
-+/*
-+ * Bit Mask
-+ *
-+ * 1. Page1(0x100) */
-+#define		bBBResetB						0x100	/* Useless now? */
-+#define		bGlobalResetB					0x200
-+#define		bOFDMTxStart					0x4
-+#define		bCCKTxStart						0x8
-+#define		bCRC32Debug					0x100
-+#define		bPMACLoopback					0x10
-+#define		bTxLSIG							0xffffff
-+#define		bOFDMTxRate					0xf
-+#define		bOFDMTxReserved				0x10
-+#define		bOFDMTxLength					0x1ffe0
-+#define		bOFDMTxParity					0x20000
-+#define		bTxHTSIG1						0xffffff
-+#define		bTxHTMCSRate					0x7f
-+#define		bTxHTBW						0x80
-+#define		bTxHTLength					0xffff00
-+#define		bTxHTSIG2						0xffffff
-+#define		bTxHTSmoothing					0x1
-+#define		bTxHTSounding					0x2
-+#define		bTxHTReserved					0x4
-+#define		bTxHTAggreation				0x8
-+#define		bTxHTSTBC						0x30
-+#define		bTxHTAdvanceCoding			0x40
-+#define		bTxHTShortGI					0x80
-+#define		bTxHTNumberHT_LTF			0x300
-+#define		bTxHTCRC8						0x3fc00
-+#define		bCounterReset					0x10000
-+#define		bNumOfOFDMTx					0xffff
-+#define		bNumOfCCKTx					0xffff0000
-+#define		bTxIdleInterval					0xffff
-+#define		bOFDMService					0xffff0000
-+#define		bTxMACHeader					0xffffffff
-+#define		bTxDataInit						0xff
-+#define		bTxHTMode						0x100
-+#define		bTxDataType					0x30000
-+#define		bTxRandomSeed					0xffffffff
-+#define		bCCKTxPreamble					0x1
-+#define		bCCKTxSFD						0xffff0000
-+#define		bCCKTxSIG						0xff
-+#define		bCCKTxService					0xff00
-+#define		bCCKLengthExt					0x8000
-+#define		bCCKTxLength					0xffff0000
-+#define		bCCKTxCRC16					0xffff
-+#define		bCCKTxStatus					0x1
-+#define		bOFDMTxStatus					0x2
-+
-+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
-+
-+/* 2. Page8(0x800) */
-+#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
-+#define		bJapanMode						0x2
-+#define		bCCKTxSC						0x30
-+#define		bCCKEn							0x1000000
-+#define		bOFDMEn						0x2000000
-+
-+#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
-+#define		bOFDMTxDACPhase		0x40000
-+#define		bXATxAGC			0x3f
-+
-+#define		bAntennaSelect		0x0300
-+
-+#define		bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
-+#define		bXCTxAGC			0xf000
-+#define		bXDTxAGC			0xf0000
-+
-+#define		bPAStart                  			0xf0000000	/* Useless now */
-+#define		bTRStart			0x00f00000
-+#define		bRFStart			0x0000f000
-+#define		bBBStart			0x000000f0
-+#define		bBBCCKStart		0x0000000f
-+#define		bPAEnd                    			0xf          /* Reg0x814 */
-+#define		bTREnd			0x0f000000
-+#define		bRFEnd			0x000f0000
-+#define		bCCAMask                  			0x000000f0   /* T2R */
-+#define		bR2RCCAMask		0x00000f00
-+#define		bHSSI_R2TDelay		0xf8000000
-+#define		bHSSI_T2RDelay		0xf80000
-+#define		bContTxHSSI               		0x400     /* chane gain at continue Tx */
-+#define		bIGFromCCK		0x200
-+#define		bAGCAddress		0x3f
-+#define		bRxHPTx			0x7000
-+#define		bRxHPT2R			0x38000
-+#define		bRxHPCCKIni		0xc0000
-+#define		bAGCTxCode		0xc00000
-+#define		bAGCRxCode		0x300000
-+
-+#define		b3WireDataLength          		0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
-+#define		b3WireAddressLength		0x400
-+
-+#define		b3WireRFPowerDown         		0x1	/* Useless now
-+ * #define bHWSISelect		0x8 */
-+#define		b5GPAPEPolarity		0x40000000
-+#define		b2GPAPEPolarity		0x80000000
-+#define		bRFSW_TxDefaultAnt		0x3
-+#define		bRFSW_TxOptionAnt		0x30
-+#define		bRFSW_RxDefaultAnt		0x300
-+#define		bRFSW_RxOptionAnt		0x3000
-+#define		bRFSI_3WireData		0x1
-+#define		bRFSI_3WireClock		0x2
-+#define		bRFSI_3WireLoad		0x4
-+#define		bRFSI_3WireRW		0x8
-+#define		bRFSI_3Wire			0xf
-+
-+#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
-+
-+#define		bRFSI_TRSW                		0x20	/* Useless now */
-+#define		bRFSI_TRSWB		0x40
-+#define		bRFSI_ANTSW		0x100
-+#define		bRFSI_ANTSWB		0x200
-+#define		bRFSI_PAPE			0x400
-+#define		bRFSI_PAPE5G		0x800
-+#define		bBandSelect			0x1
-+#define		bHTSIG2_GI			0x80
-+#define		bHTSIG2_Smoothing		0x01
-+#define		bHTSIG2_Sounding		0x02
-+#define		bHTSIG2_Aggreaton		0x08
-+#define		bHTSIG2_STBC		0x30
-+#define		bHTSIG2_AdvCoding		0x40
-+#define		bHTSIG2_NumOfHTLTF	0x300
-+#define		bHTSIG2_CRC8		0x3fc
-+#define		bHTSIG1_MCS		0x7f
-+#define		bHTSIG1_BandWidth		0x80
-+#define		bHTSIG1_HTLength		0xffff
-+#define		bLSIG_Rate			0xf
-+#define		bLSIG_Reserved		0x10
-+#define		bLSIG_Length		0x1fffe
-+#define		bLSIG_Parity			0x20
-+#define		bCCKRxPhase		0x4
-+
-+#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
-+
-+#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
-+
-+#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
-+
-+#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
-+#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
-+#define		bRegulator0Standby		0x1
-+#define		bRegulatorPLLStandby		0x2
-+#define		bRegulator1Standby		0x4
-+#define		bPLLPowerUp		0x8
-+#define		bDPLLPowerUp		0x10
-+#define		bDA10PowerUp		0x20
-+#define		bAD7PowerUp		0x200
-+#define		bDA6PowerUp		0x2000
-+#define		bXtalPowerUp		0x4000
-+#define		b40MDClkPowerUP		0x8000
-+#define		bDA6DebugMode		0x20000
-+#define		bDA6Swing			0x380000
-+
-+#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
-+
-+#define		b80MClkDelay              		0x18000000	/* Useless */
-+#define		bAFEWatchDogEnable		0x20000000
-+
-+#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
-+#define		bXtalCap23			0x3
-+#define		bXtalCap92x					0x0f000000
-+#define		bXtalCap			0x0f000000
-+
-+#define		bIntDifClkEnable          		0x400	/* Useless */
-+#define		bExtSigClkEnable		0x800
-+#define		bBandgapMbiasPowerUp	0x10000
-+#define		bAD11SHGain		0xc0000
-+#define		bAD11InputRange		0x700000
-+#define		bAD11OPCurrent		0x3800000
-+#define		bIPathLoopback		0x4000000
-+#define		bQPathLoopback		0x8000000
-+#define		bAFELoopback		0x10000000
-+#define		bDA10Swing		0x7e0
-+#define		bDA10Reverse		0x800
-+#define		bDAClkSource		0x1000
-+#define		bAD7InputRange		0x6000
-+#define		bAD7Gain			0x38000
-+#define		bAD7OutputCMMode		0x40000
-+#define		bAD7InputCMMode		0x380000
-+#define		bAD7Current			0xc00000
-+#define		bRegulatorAdjust		0x7000000
-+#define		bAD11PowerUpAtTx		0x1
-+#define		bDA10PSAtTx		0x10
-+#define		bAD11PowerUpAtRx		0x100
-+#define		bDA10PSAtRx		0x1000
-+#define		bCCKRxAGCFormat		0x200
-+#define		bPSDFFTSamplepPoint		0xc000
-+#define		bPSDAverageNum		0x3000
-+#define		bIQPathControl		0xc00
-+#define		bPSDFreq			0x3ff
-+#define		bPSDAntennaPath		0x30
-+#define		bPSDIQSwitch		0x40
-+#define		bPSDRxTrigger		0x400000
-+#define		bPSDTxTrigger		0x80000000
-+#define		bPSDSineToneScale		0x7f000000
-+#define		bPSDReport			0xffff
-+
-+/* 3. Page9(0x900) */
-+#define		bOFDMTxSC                 		0x30000000	/* Useless */
-+#define		bCCKTxOn			0x1
-+#define		bOFDMTxOn		0x2
-+#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
-+#define		bDebugItem                		0xff   /* reset debug page and LWord */
-+#define		bAntL			0x10
-+#define		bAntNonHT				0x100
-+#define		bAntHT1			0x1000
-+#define		bAntHT2			0x10000
-+#define		bAntHT1S1			0x100000
-+#define		bAntNonHTS1		0x1000000
-+
-+/* 4. PageA(0xA00) */
-+#define		bCCKBBMode				0x3	/* Useless */
-+#define		bCCKTxPowerSaving		0x80
-+#define		bCCKRxPowerSaving		0x40
-+
-+#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
-+
-+#define		bCCKScramble			0x8	/* Useless */
-+#define		bCCKAntDiversity		0x8000
-+#define		bCCKCarrierRecovery		0x4000
-+#define		bCCKTxRate				0x3000
-+#define		bCCKDCCancel			0x0800
-+#define		bCCKISICancel			0x0400
-+#define		bCCKMatchFilter			0x0200
-+#define		bCCKEqualizer			0x0100
-+#define		bCCKPreambleDetect		0x800000
-+#define		bCCKFastFalseCCA		0x400000
-+#define		bCCKChEstStart			0x300000
-+#define		bCCKCCACount			0x080000
-+#define		bCCKcs_lim				0x070000
-+#define		bCCKBistMode			0x80000000
-+#define		bCCKCCAMask			0x40000000
-+#define		bCCKTxDACPhase		0x4
-+#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
-+#define		bCCKr_cp_mode0		0x0100
-+#define		bCCKTxDCOffset			0xf0
-+#define		bCCKRxDCOffset			0xf
-+#define		bCCKCCAMode			0xc000
-+#define		bCCKFalseCS_lim			0x3f00
-+#define		bCCKCS_ratio			0xc00000
-+#define		bCCKCorgBit_sel			0x300000
-+#define		bCCKPD_lim				0x0f0000
-+#define		bCCKNewCCA			0x80000000
-+#define		bCCKRxHPofIG			0x8000
-+#define		bCCKRxIG				0x7f00
-+#define		bCCKLNAPolarity			0x800000
-+#define		bCCKRx1stGain			0x7f0000
-+#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
-+#define		bCCKRxAGCSatLevel		0x1f000000
-+#define		bCCKRxAGCSatCount		0xe0
-+#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
-+#define		bCCKFixedRxAGC			0x8000
-+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
-+#define		bCCKAntennaPolarity		0x2000
-+#define		bCCKTxFilterType		0x0c00
-+#define		bCCKRxAGCReportType	0x0300
-+#define		bCCKRxDAGCEn			0x80000000
-+#define		bCCKRxDAGCPeriod		0x20000000
-+#define		bCCKRxDAGCSatLevel		0x1f000000
-+#define		bCCKTimingRecovery		0x800000
-+#define		bCCKTxC0				0x3f0000
-+#define		bCCKTxC1				0x3f000000
-+#define		bCCKTxC2				0x3f
-+#define		bCCKTxC3				0x3f00
-+#define		bCCKTxC4				0x3f0000
-+#define		bCCKTxC5				0x3f000000
-+#define		bCCKTxC6				0x3f
-+#define		bCCKTxC7				0x3f00
-+#define		bCCKDebugPort			0xff0000
-+#define		bCCKDACDebug			0x0f000000
-+#define		bCCKFalseAlarmEnable	0x8000
-+#define		bCCKFalseAlarmRead		0x4000
-+#define		bCCKTRSSI				0x7f
-+#define		bCCKRxAGCReport		0xfe
-+#define		bCCKRxReport_AntSel	0x80000000
-+#define		bCCKRxReport_MFOff		0x40000000
-+#define		bCCKRxRxReport_SQLoss	0x20000000
-+#define		bCCKRxReport_Pktloss	0x10000000
-+#define		bCCKRxReport_Lockedbit	0x08000000
-+#define		bCCKRxReport_RateError	0x04000000
-+#define		bCCKRxReport_RxRate	0x03000000
-+#define		bCCKRxFACounterLower	0xff
-+#define		bCCKRxFACounterUpper	0xff000000
-+#define		bCCKRxHPAGCStart		0xe000
-+#define		bCCKRxHPAGCFinal		0x1c00
-+#define		bCCKRxFalseAlarmEnable	0x8000
-+#define		bCCKFACounterFreeze	0x4000
-+#define		bCCKTxPathSel			0x10000000
-+#define		bCCKDefaultRxPath		0xc000000
-+#define		bCCKOptionRxPath		0x3000000
-+
-+/* 5. PageC(0xC00) */
-+#define		bNumOfSTF				0x3	/* Useless */
-+#define		bShift_L					0xc0
-+#define		bGI_TH					0xc
-+#define		bRxPathA				0x1
-+#define		bRxPathB				0x2
-+#define		bRxPathC				0x4
-+#define		bRxPathD				0x8
-+#define		bTxPathA				0x1
-+#define		bTxPathB				0x2
-+#define		bTxPathC				0x4
-+#define		bTxPathD				0x8
-+#define		bTRSSIFreq				0x200
-+#define		bADCBackoff				0x3000
-+#define		bDFIRBackoff			0xc000
-+#define		bTRSSILatchPhase		0x10000
-+#define		bRxIDCOffset			0xff
-+#define		bRxQDCOffset			0xff00
-+#define		bRxDFIRMode			0x1800000
-+#define		bRxDCNFType			0xe000000
-+#define		bRXIQImb_A				0x3ff
-+#define		bRXIQImb_B				0xfc00
-+#define		bRXIQImb_C				0x3f0000
-+#define		bRXIQImb_D				0xffc00000
-+#define		bDC_dc_Notch			0x60000
-+#define		bRxNBINotch			0x1f000000
-+#define		bPD_TH					0xf
-+#define		bPD_TH_Opt2			0xc000
-+#define		bPWED_TH				0x700
-+#define		bIfMF_Win_L			0x800
-+#define		bPD_Option				0x1000
-+#define		bMF_Win_L				0xe000
-+#define		bBW_Search_L			0x30000
-+#define		bwin_enh_L				0xc0000
-+#define		bBW_TH					0x700000
-+#define		bED_TH2				0x3800000
-+#define		bBW_option				0x4000000
-+#define		bRatio_TH				0x18000000
-+#define		bWindow_L				0xe0000000
-+#define		bSBD_Option				0x1
-+#define		bFrame_TH				0x1c
-+#define		bFS_Option				0x60
-+#define		bDC_Slope_check		0x80
-+#define		bFGuard_Counter_DC_L	0xe00
-+#define		bFrame_Weight_Short	0x7000
-+#define		bSub_Tune				0xe00000
-+#define		bFrame_DC_Length		0xe000000
-+#define		bSBD_start_offset		0x30000000
-+#define		bFrame_TH_2			0x7
-+#define		bFrame_GI2_TH			0x38
-+#define		bGI2_Sync_en			0x40
-+#define		bSarch_Short_Early		0x300
-+#define		bSarch_Short_Late		0xc00
-+#define		bSarch_GI2_Late		0x70000
-+#define		bCFOAntSum				0x1
-+#define		bCFOAcc				0x2
-+#define		bCFOStartOffset			0xc
-+#define		bCFOLookBack			0x70
-+#define		bCFOSumWeight			0x80
-+#define		bDAGCEnable			0x10000
-+#define		bTXIQImb_A				0x3ff
-+#define		bTXIQImb_B				0xfc00
-+#define		bTXIQImb_C				0x3f0000
-+#define		bTXIQImb_D				0xffc00000
-+#define		bTxIDCOffset			0xff
-+#define		bTxQDCOffset			0xff00
-+#define		bTxDFIRMode			0x10000
-+#define		bTxPesudoNoiseOn		0x4000000
-+#define		bTxPesudoNoise_A		0xff
-+#define		bTxPesudoNoise_B		0xff00
-+#define		bTxPesudoNoise_C		0xff0000
-+#define		bTxPesudoNoise_D		0xff000000
-+#define		bCCADropOption			0x20000
-+#define		bCCADropThres			0xfff00000
-+#define		bEDCCA_H				0xf
-+#define		bEDCCA_L				0xf0
-+#define		bLambda_ED			0x300
-+#define		bRxInitialGain			0x7f
-+#define		bRxAntDivEn				0x80
-+#define		bRxAGCAddressForLNA	0x7f00
-+#define		bRxHighPowerFlow		0x8000
-+#define		bRxAGCFreezeThres		0xc0000
-+#define		bRxFreezeStep_AGC1	0x300000
-+#define		bRxFreezeStep_AGC2	0xc00000
-+#define		bRxFreezeStep_AGC3	0x3000000
-+#define		bRxFreezeStep_AGC0	0xc000000
-+#define		bRxRssi_Cmp_En			0x10000000
-+#define		bRxQuickAGCEn			0x20000000
-+#define		bRxAGCFreezeThresMode	0x40000000
-+#define		bRxOverFlowCheckType	0x80000000
-+#define		bRxAGCShift				0x7f
-+#define		bTRSW_Tri_Only			0x80
-+#define		bPowerThres			0x300
-+#define		bRxAGCEn				0x1
-+#define		bRxAGCTogetherEn		0x2
-+#define		bRxAGCMin				0x4
-+#define		bRxHP_Ini				0x7
-+#define		bRxHP_TRLNA			0x70
-+#define		bRxHP_RSSI				0x700
-+#define		bRxHP_BBP1				0x7000
-+#define		bRxHP_BBP2				0x70000
-+#define		bRxHP_BBP3				0x700000
-+#define		bRSSI_H					0x7f0000     /* the threshold for high power */
-+#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
-+#define		bRxSettle_TRSW			0x7
-+#define		bRxSettle_LNA			0x38
-+#define		bRxSettle_RSSI			0x1c0
-+#define		bRxSettle_BBP			0xe00
-+#define		bRxSettle_RxHP			0x7000
-+#define		bRxSettle_AntSW_RSSI	0x38000
-+#define		bRxSettle_AntSW		0xc0000
-+#define		bRxProcessTime_DAGC	0x300000
-+#define		bRxSettle_HSSI			0x400000
-+#define		bRxProcessTime_BBPPW	0x800000
-+#define		bRxAntennaPowerShift	0x3000000
-+#define		bRSSITableSelect		0xc000000
-+#define		bRxHP_Final				0x7000000
-+#define		bRxHTSettle_BBP			0x7
-+#define		bRxHTSettle_HSSI		0x8
-+#define		bRxHTSettle_RxHP		0x70
-+#define		bRxHTSettle_BBPPW		0x80
-+#define		bRxHTSettle_Idle		0x300
-+#define		bRxHTSettle_Reserved	0x1c00
-+#define		bRxHTRxHPEn			0x8000
-+#define		bRxHTAGCFreezeThres	0x30000
-+#define		bRxHTAGCTogetherEn	0x40000
-+#define		bRxHTAGCMin			0x80000
-+#define		bRxHTAGCEn				0x100000
-+#define		bRxHTDAGCEn			0x200000
-+#define		bRxHTRxHP_BBP			0x1c00000
-+#define		bRxHTRxHP_Final		0xe0000000
-+#define		bRxPWRatioTH			0x3
-+#define		bRxPWRatioEn			0x4
-+#define		bRxMFHold				0x3800
-+#define		bRxPD_Delay_TH1		0x38
-+#define		bRxPD_Delay_TH2		0x1c0
-+#define		bRxPD_DC_COUNT_MAX	0x600
-+/* #define bRxMF_Hold               0x3800 */
-+#define		bRxPD_Delay_TH			0x8000
-+#define		bRxProcess_Delay		0xf0000
-+#define		bRxSearchrange_GI2_Early	0x700000
-+#define		bRxFrame_Guard_Counter_L	0x3800000
-+#define		bRxSGI_Guard_L			0xc000000
-+#define		bRxSGI_Search_L		0x30000000
-+#define		bRxSGI_TH				0xc0000000
-+#define		bDFSCnt0				0xff
-+#define		bDFSCnt1				0xff00
-+#define		bDFSFlag				0xf0000
-+#define		bMFWeightSum			0x300000
-+#define		bMinIdxTH				0x7f000000
-+#define		bDAFormat				0x40000
-+#define		bTxChEmuEnable		0x01000000
-+#define		bTRSWIsolation_A		0x7f
-+#define		bTRSWIsolation_B		0x7f00
-+#define		bTRSWIsolation_C		0x7f0000
-+#define		bTRSWIsolation_D		0x7f000000
-+#define		bExtLNAGain				0x7c00
-+
-+/* 6. PageE(0xE00) */
-+#define		bSTBCEn				0x4	/* Useless */
-+#define		bAntennaMapping		0x10
-+#define		bNss					0x20
-+#define		bCFOAntSumD			0x200
-+#define		bPHYCounterReset		0x8000000
-+#define		bCFOReportGet			0x4000000
-+#define		bOFDMContinueTx		0x10000000
-+#define		bOFDMSingleCarrier		0x20000000
-+#define		bOFDMSingleTone		0x40000000
-+/* #define bRxPath1                 0x01 */
-+/* #define bRxPath2                 0x02 */
-+/* #define bRxPath3                 0x04 */
-+/* #define bRxPath4                 0x08 */
-+/* #define bTxPath1                 0x10 */
-+/* #define bTxPath2                 0x20 */
-+#define		bHTDetect			0x100
-+#define		bCFOEn				0x10000
-+#define		bCFOValue			0xfff00000
-+#define		bSigTone_Re		0x3f
-+#define		bSigTone_Im		0x7f00
-+#define		bCounter_CCA		0xffff
-+#define		bCounter_ParityFail	0xffff0000
-+#define		bCounter_RateIllegal		0xffff
-+#define		bCounter_CRC8Fail	0xffff0000
-+#define		bCounter_MCSNoSupport	0xffff
-+#define		bCounter_FastSync	0xffff
-+#define		bShortCFO			0xfff
-+#define		bShortCFOTLength	12   /* total */
-+#define		bShortCFOFLength	11   /* fraction */
-+#define		bLongCFO			0x7ff
-+#define		bLongCFOTLength	11
-+#define		bLongCFOFLength	11
-+#define		bTailCFO			0x1fff
-+#define		bTailCFOTLength		13
-+#define		bTailCFOFLength		12
-+#define		bmax_en_pwdB		0xffff
-+#define		bCC_power_dB		0xffff0000
-+#define		bnoise_pwdB		0xffff
-+#define		bPowerMeasTLength	10
-+#define		bPowerMeasFLength	3
-+#define		bRx_HT_BW			0x1
-+#define		bRxSC				0x6
-+#define		bRx_HT				0x8
-+#define		bNB_intf_det_on		0x1
-+#define		bIntf_win_len_cfg	0x30
-+#define		bNB_Intf_TH_cfg		0x1c0
-+#define		bRFGain				0x3f
-+#define		bTableSel			0x40
-+#define		bTRSW				0x80
-+#define		bRxSNR_A			0xff
-+#define		bRxSNR_B			0xff00
-+#define		bRxSNR_C			0xff0000
-+#define		bRxSNR_D			0xff000000
-+#define		bSNREVMTLength		8
-+#define		bSNREVMFLength		1
-+#define		bCSI1st				0xff
-+#define		bCSI2nd				0xff00
-+#define		bRxEVM1st			0xff0000
-+#define		bRxEVM2nd			0xff000000
-+#define		bSIGEVM			0xff
-+#define		bPWDB				0xff00
-+#define		bSGIEN				0x10000
-+
-+#define		bSFactorQAM1		0xf	/* Useless */
-+#define		bSFactorQAM2		0xf0
-+#define		bSFactorQAM3		0xf00
-+#define		bSFactorQAM4		0xf000
-+#define		bSFactorQAM5		0xf0000
-+#define		bSFactorQAM6		0xf0000
-+#define		bSFactorQAM7		0xf00000
-+#define		bSFactorQAM8		0xf000000
-+#define		bSFactorQAM9		0xf0000000
-+#define		bCSIScheme			0x100000
-+
-+#define		bNoiseLvlTopSet		0x3	/* Useless */
-+#define		bChSmooth			0x4
-+#define		bChSmoothCfg1		0x38
-+#define		bChSmoothCfg2		0x1c0
-+#define		bChSmoothCfg3		0xe00
-+#define		bChSmoothCfg4		0x7000
-+#define		bMRCMode			0x800000
-+#define		bTHEVMCfg			0x7000000
-+
-+#define		bLoopFitType		0x1	/* Useless */
-+#define		bUpdCFO			0x40
-+#define		bUpdCFOOffData		0x80
-+#define		bAdvUpdCFO			0x100
-+#define		bAdvTimeCtrl		0x800
-+#define		bUpdClko			0x1000
-+#define		bFC					0x6000
-+#define		bTrackingMode		0x8000
-+#define		bPhCmpEnable		0x10000
-+#define		bUpdClkoLTF		0x20000
-+#define		bComChCFO			0x40000
-+#define		bCSIEstiMode		0x80000
-+#define		bAdvUpdEqz			0x100000
-+#define		bUChCfg				0x7000000
-+#define		bUpdEqz			0x8000000
-+
-+/* Rx Pseduo noise */
-+#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
-+#define		bRxPesudoNoise_A		0xff
-+#define		bRxPesudoNoise_B		0xff00
-+#define		bRxPesudoNoise_C		0xff0000
-+#define		bRxPesudoNoise_D		0xff000000
-+#define		bPesudoNoiseState_A	0xffff
-+#define		bPesudoNoiseState_B	0xffff0000
-+#define		bPesudoNoiseState_C	0xffff
-+#define		bPesudoNoiseState_D	0xffff0000
-+
-+/* 7. RF Register
-+ * Zebra1 */
-+#define		bZebra1_HSSIEnable		0x8		/* Useless */
-+#define		bZebra1_TRxControl		0xc00
-+#define		bZebra1_TRxGainSetting	0x07f
-+#define		bZebra1_RxCorner		0xc00
-+#define		bZebra1_TxChargePump	0x38
-+#define		bZebra1_RxChargePump	0x7
-+#define		bZebra1_ChannelNum	0xf80
-+#define		bZebra1_TxLPFBW		0x400
-+#define		bZebra1_RxLPFBW		0x600
-+
-+/* Zebra4 */
-+#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
-+#define		bRTL8256RegModeCtrl0	0x40
-+#define		bRTL8256_TxLPFBW		0x18
-+#define		bRTL8256_RxLPFBW		0x600
-+
-+/* RTL8258 */
-+#define		bRTL8258_TxLPFBW		0xc	/* Useless */
-+#define		bRTL8258_RxLPFBW		0xc00
-+#define		bRTL8258_RSSILPFBW	0xc0
-+
-+
-+/*
-+ * Other Definition
-+ *   */
-+
-+/* byte endable for sb_write */
-+#define		bByte0				0x1	/* Useless */
-+#define		bByte1				0x2
-+#define		bByte2				0x4
-+#define		bByte3				0x8
-+#define		bWord0				0x3
-+#define		bWord1				0xc
-+#define		bDWord				0xf
-+
-+/* for PutRegsetting & GetRegSetting BitMask */
-+#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
-+#define		bMaskByte1			0xff00
-+#define		bMaskByte2			0xff0000
-+#define		bMaskByte3			0xff000000
-+#define		bMaskHWord		0xffff0000
-+#define		bMaskLWord			0x0000ffff
-+#define		bMaskDWord		0xffffffff
-+#define		bMaskH3Bytes		0xffffff00
-+#define		bMask12Bits			0xfff
-+#define		bMaskH4Bits			0xf0000000
-+#define		bMaskOFDM_D		0xffc00000
-+#define		bMaskCCK			0x3f3f3f3f
-+
-+
-+#define		bEnable			0x1	/* Useless */
-+#define		bDisable		0x0
-+
-+#define		LeftAntenna		0x0	/* Useless */
-+#define		RightAntenna	0x1
-+
-+#define		tCheckTxStatus		500   /* 500ms */ /* Useless */
-+#define		tUpdateRxCounter	100   /* 100ms */
-+
-+#define		rateCCK		0	/* Useless */
-+#define		rateOFDM	1
-+#define		rateHT		2
-+
-+/* define Register-End */
-+#define		bPMAC_End			0x1ff	/* Useless */
-+#define		bFPGAPHY0_End		0x8ff
-+#define		bFPGAPHY1_End		0x9ff
-+#define		bCCKPHY0_End		0xaff
-+#define		bOFDMPHY0_End		0xcff
-+#define		bOFDMPHY1_End		0xdff
-+
-+/* define max debug item in each debug page
-+ * #define bMaxItem_FPGA_PHY0        0x9
-+ * #define bMaxItem_FPGA_PHY1        0x3
-+ * #define bMaxItem_PHY_11B          0x16
-+ * #define bMaxItem_OFDM_PHY0        0x29
-+ * #define bMaxItem_OFDM_PHY1        0x0 */
-+
-+#define		bPMACControl		0x0		/* Useless */
-+#define		bWMACControl		0x1
-+#define		bWNICControl		0x2
-+
-+#define		PathA			0x0	/* Useless */
-+#define		PathB			0x1
-+#define		PathC			0x2
-+#define		PathD			0x3
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+
-+/* BB Register Definition
-+ *
-+ * 4. Page9(0x900)
-+ *   */
-+#define rDPDT_control				0x92c
-+#define rfe_ctrl_anta_src				0x930
-+#define rS0S1_PathSwitch			0x948
-+#define	BBrx_DFIR						0x954
-+#define AGC_table_select				0xb2c
-+
-+/*
-+ * PageB(0xB00)
-+ *   */
-+#define rPdp_AntA						0xb00
-+#define rPdp_AntA_4						0xb04
-+#define rPdp_AntA_8						0xb08
-+#define rPdp_AntA_C						0xb0c
-+#define rPdp_AntA_10					0xb10
-+#define rPdp_AntA_14					0xb14
-+#define rPdp_AntA_18					0xb18
-+#define rPdp_AntA_1C					0xb1c
-+#define rPdp_AntA_20					0xb20
-+#define rPdp_AntA_24					0xb24
-+
-+#define rConfig_Pmpd_AntA				0xb28
-+#define rConfig_ram64x16				0xb2c
-+
-+#define rBndA							0xb30
-+#define rHssiPar						0xb34
-+
-+#define rConfig_AntA					0xb68
-+#define rConfig_AntB					0xb6c
-+
-+#define rPdp_AntB						0xb70
-+#define rPdp_AntB_4						0xb74
-+#define rPdp_AntB_8						0xb78
-+#define rPdp_AntB_C						0xb7c
-+#define rPdp_AntB_10					0xb80
-+#define rPdp_AntB_14					0xb84
-+#define rPdp_AntB_18					0xb88
-+#define rPdp_AntB_1C					0xb8c
-+#define rPdp_AntB_20					0xb90
-+#define rPdp_AntB_24					0xb94
-+
-+#define rConfig_Pmpd_AntB				0xb98
-+
-+#define rBndB							0xba0
-+
-+#define rAPK							0xbd8
-+#define rPm_Rx0_AntA					0xbdc
-+#define rPm_Rx1_AntA					0xbe0
-+#define rPm_Rx2_AntA					0xbe4
-+#define rPm_Rx3_AntA					0xbe8
-+#define rPm_Rx0_AntB					0xbec
-+#define rPm_Rx1_AntB					0xbf0
-+#define rPm_Rx2_AntB					0xbf4
-+#define rPm_Rx3_AntB					0xbf8
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8188FPwrSeq.h b/drivers/staging/rtl8723cs/include/Hal8188FPwrSeq.h
-new file mode 100644
-index 000000000000..5cad428fdd0b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8188FPwrSeq.h
-@@ -0,0 +1,212 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef REALTEK_POWER_SEQUENCE_8188F
-+#define REALTEK_POWER_SEQUENCE_8188F
-+
-+#include "HalPwrSeqCmd.h"
-+
-+/*
-+	Check document WM-20130815-JackieLau-RTL8188F_Power_Architecture v08.vsd
-+	There are 6 HW Power States:
-+	0: POFF--Power Off
-+	1: PDN--Power Down
-+	2: CARDEMU--Card Emulation
-+	3: ACT--Active Mode
-+	4: LPS--Low Power State
-+	5: SUS--Suspend
-+
-+	The transision from different states are defined below
-+	TRANS_CARDEMU_TO_ACT
-+	TRANS_ACT_TO_CARDEMU
-+	TRANS_CARDEMU_TO_SUS
-+	TRANS_SUS_TO_CARDEMU
-+	TRANS_CARDEMU_TO_PDN
-+	TRANS_ACT_TO_LPS
-+	TRANS_LPS_TO_ACT
-+
-+	TRANS_END
-+*/
-+#define	RTL8188F_TRANS_CARDEMU_TO_ACT_STEPS	13
-+#define	RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS	15
-+#define	RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS	14
-+#define	RTL8188F_TRANS_SUS_TO_CARDEMU_STEPS	15
-+#define	RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS	15
-+#define	RTL8188F_TRANS_PDN_TO_CARDEMU_STEPS	15
-+#define	RTL8188F_TRANS_ACT_TO_LPS_STEPS		11
-+#define	RTL8188F_TRANS_LPS_TO_ACT_STEPS		13
-+#define	RTL8188F_TRANS_ACT_TO_SWLPS_STEPS		21
-+#define	RTL8188F_TRANS_SWLPS_TO_ACT_STEPS		14
-+#define	RTL8188F_TRANS_END_STEPS		1
-+
-+
-+#define RTL8188F_TRANS_CARDEMU_TO_ACT														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT3), 0},/*  0x4[11]=1'b0 disable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* 0x4[8]=1 polling until return 0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	 \
-+	{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x35}, /*0x27<=35 to reduce RF noise*/
-+
-+#define RTL8188F_TRANS_ACT_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
-+	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
-+	{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x34}, /*0x27 <= 34, xtal_qsel = 0 to xtal bring up*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
-+
-+#define RTL8188F_TRANS_CARDEMU_TO_SUS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /*0x07 = 0x00 , SOP option to disable BG/MB*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ \
-+	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
-+
-+#define RTL8188F_TRANS_SUS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/	\
-+	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
-+
-+#define RTL8188F_TRANS_CARDEMU_TO_CARDDIS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /*0x07 = 0x00 , SOP option to disable BG/MB*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ \
-+	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
-+
-+#define RTL8188F_TRANS_CARDDIS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/	\
-+	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
-+
-+
-+#define RTL8188F_TRANS_CARDEMU_TO_PDN												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
-+
-+#define RTL8188F_TRANS_PDN_TO_CARDEMU												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
-+
-+#define RTL8188F_TRANS_ACT_TO_LPS														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*set RPWM IMR*/	\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
-+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
-+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
-+
-+
-+#define RTL8188F_TRANS_LPS_TO_ACT															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84},  /*SDIO RPWM*/\
-+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
-+	{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x35},/*xtal_qsel = 1 for low noise*/	\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
-+	{0x002B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x1c, 0x1c},   /*.	0x2b[4:2] = 3b'111	to enable BB, AFE clock*/\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0},  /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
-+
-+
-+#define RTL8188F_TRANS_ACT_TO_SWLPS														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*set RPWM IMR*/	\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
-+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
-+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
-+	{0x002b, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x1C, 0x00},/*0x2b[4:2]<=0 to gated BB, AFE clock*/	\
-+	{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x34},/*xtal_qsel = 0 for bring up*/	\
-+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x00},/* sdio LPS option*/	\
-+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x83},/* usb LPS option, open bandgap, xtal*/	\
-+	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /* 0xC4[5]<=0, digital LDO no standby mode*/	\
-+	{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /* 0xC4[7]<=1, on domain voltage adjust*/	\
-+	{0x00a7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0xe0}, /* low power LPS enable for sdio*/	\
-+	{0x00a7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0xe4}, /* low power LPS enable for usb*/	\
-+	{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* enable WL_LPS_EN*/
-+
-+
-+#define RTL8188F_TRANS_SWLPS_TO_ACT															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1, enable security engine*/\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
-+	{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x09}, /*.	reset MAC rx state machine*/\
-+	{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x86}, /*.	reset MAC rx state machine*/\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/	\
-+	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/	\
-+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/	\
-+	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/	\
-+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/	\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */	\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
-+
-+#define RTL8188F_TRANS_END															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
-+
-+
-+	extern WLAN_PWR_CFG rtl8188F_power_on_flow[RTL8188F_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188F_radio_off_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188F_card_disable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188F_card_enable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188F_suspend_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188F_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188F_resume_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188F_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188F_hwpdn_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188F_enter_lps_flow[RTL8188F_TRANS_ACT_TO_LPS_STEPS + RTL8188F_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188F_leave_lps_flow[RTL8188F_TRANS_LPS_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188F_enter_swlps_flow[RTL8188F_TRANS_ACT_TO_SWLPS_STEPS + RTL8188F_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8188F_leave_swlps_flow[RTL8188F_TRANS_SWLPS_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8192EPhyCfg.h b/drivers/staging/rtl8723cs/include/Hal8192EPhyCfg.h
-new file mode 100644
-index 000000000000..021d95335d2b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8192EPhyCfg.h
-@@ -0,0 +1,136 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2012 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8192EPHYCFG_H__
-+#define __INC_HAL8192EPHYCFG_H__
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+#define LOOP_LIMIT				5
-+#define MAX_STALL_TIME			50		/* us */
-+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
-+#define MAX_TXPWR_IDX_NMODE_92S	63
-+#define Reset_Cnt_Limit			3
-+
-+#ifdef CONFIG_PCI_HCI
-+	#define MAX_AGGR_NUM	0x0B
-+#else
-+	#define MAX_AGGR_NUM	0x07
-+#endif /* CONFIG_PCI_HCI */
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+/* BB/RF related */
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+
-+/*------------------------Export global variable----------------------------*/
-+/*------------------------Export global variable----------------------------*/
-+
-+
-+/*------------------------Export Marco Definition---------------------------*/
-+/*------------------------Export Marco Definition---------------------------*/
-+
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+/*
-+ * BB and RF register read/write
-+ *   */
-+u32	PHY_QueryBBReg8192E(PADAPTER	Adapter,
-+				u32			RegAddr,
-+				u32			BitMask);
-+void	PHY_SetBBReg8192E(PADAPTER		Adapter,
-+				u32			RegAddr,
-+				u32			BitMask,
-+				u32			Data);
-+u32	PHY_QueryRFReg8192E(PADAPTER	Adapter,
-+				enum rf_path	eRFPath,
-+				u32			RegAddr,
-+				u32			BitMask);
-+void	PHY_SetRFReg8192E(PADAPTER		Adapter,
-+				enum rf_path	eRFPath,
-+				u32			RegAddr,
-+				u32			BitMask,
-+				u32			Data);
-+
-+/*
-+ * Initialization related function
-+ *
-+ * MAC/BB/RF HAL config */
-+int	PHY_MACConfig8192E(PADAPTER	Adapter);
-+int	PHY_BBConfig8192E(PADAPTER	Adapter);
-+int	PHY_RFConfig8192E(PADAPTER	Adapter);
-+
-+/* RF config */
-+
-+
-+/*
-+ * BB TX Power R/W
-+ *   */
-+void	PHY_SetTxPowerLevel8192E(PADAPTER	Adapter, u8	channel);
-+
-+void
-+PHY_SetTxPowerIndex_8192E(
-+		PADAPTER			Adapter,
-+		u32					PowerIndex,
-+		enum rf_path			RFPath,
-+		u8					Rate
-+);
-+
-+/*
-+ * channel switch related funciton
-+ *   */
-+void
-+PHY_SetSwChnlBWMode8192E(
-+		PADAPTER			Adapter,
-+		u8					channel,
-+		enum channel_width	Bandwidth,
-+		u8					Offset40,
-+		u8					Offset80
-+);
-+
-+void
-+PHY_SetRFEReg_8192E(
-+		PADAPTER		Adapter
-+);
-+
-+void
-+phy_SpurCalibration_8192E(
-+		PADAPTER			Adapter,
-+		enum spur_cal_method	method
-+);
-+void PHY_SpurCalibration_8192E( PADAPTER Adapter);
-+
-+#ifdef CONFIG_SPUR_CAL_NBI
-+void
-+phy_SpurCalibration_8192E_NBI(
-+		PADAPTER			Adapter
-+);
-+#endif
-+/*
-+ * BB/MAC/RF other monitor API
-+ *   */
-+
-+void
-+phy_set_rf_path_switch_8192e(
-+		struct dm_struct		*phydm,
-+		bool		bMain
-+);
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+#endif /* __INC_HAL8192CPHYCFG_H */
-diff --git a/drivers/staging/rtl8723cs/include/Hal8192EPhyReg.h b/drivers/staging/rtl8723cs/include/Hal8192EPhyReg.h
-new file mode 100644
-index 000000000000..30b771111164
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8192EPhyReg.h
-@@ -0,0 +1,1146 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2012 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*****************************************************************************
-+ *	Copyright(c) 2008,  RealTEK Technology Inc. All Right Reserved.
-+ *
-+ * Module:	__INC_HAL8192SPHYREG_H
-+ *
-+ *
-+ * Note:	1. Define PMAC/BB register map
-+ *			2. Define RF register map
-+ *			3. PMAC/BB register bit mask.
-+ *			4. RF reg bit mask.
-+ *			5. Other BB/RF relative definition.
-+ *
-+ *
-+ * Export:	Constants, macro, functions(API), global variables(None).
-+ *
-+ * Abbrev:
-+ *
-+ * History:
-+ *		Data		Who		Remark
-+ *      08/07/2007  MHC	1. Porting from 9x series PHYCFG.h.
-+ *							2. Reorganize code architecture.
-+ *	09/25/2008	MH		1. Add RL6052 register definition
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8192EPHYREG_H
-+#define __INC_HAL8192EPHYREG_H
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+/* ************************************************************
-+ * 8192S Regsiter offset definition
-+ * ************************************************************ */
-+
-+/*
-+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
-+ * 3. RF register 0x00-2E
-+ * 4. Bit Mask for BB/RF register
-+ * 5. Other defintion for BB/RF R/W
-+ *   */
-+
-+
-+/*
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 1. Page1(0x100)
-+ *   */
-+#define		rPMAC_Reset					0x100
-+#define		rPMAC_TxStart				0x104
-+#define		rPMAC_TxLegacySIG			0x108
-+#define		rPMAC_TxHTSIG1				0x10c
-+#define		rPMAC_TxHTSIG2				0x110
-+#define		rPMAC_PHYDebug				0x114
-+#define		rPMAC_TxPacketNum			0x118
-+#define		rPMAC_TxIdle					0x11c
-+#define		rPMAC_TxMACHeader0			0x120
-+#define		rPMAC_TxMACHeader1			0x124
-+#define		rPMAC_TxMACHeader2			0x128
-+#define		rPMAC_TxMACHeader3			0x12c
-+#define		rPMAC_TxMACHeader4			0x130
-+#define		rPMAC_TxMACHeader5			0x134
-+#define		rPMAC_TxDataType				0x138
-+#define		rPMAC_TxRandomSeed			0x13c
-+#define		rPMAC_CCKPLCPPreamble		0x140
-+#define		rPMAC_CCKPLCPHeader			0x144
-+#define		rPMAC_CCKCRC16				0x148
-+#define		rPMAC_OFDMRxCRC32OK		0x170
-+#define		rPMAC_OFDMRxCRC32Er		0x174
-+#define		rPMAC_OFDMRxParityEr			0x178
-+#define		rPMAC_OFDMRxCRC8Er			0x17c
-+#define		rPMAC_CCKCRxRC16Er			0x180
-+#define		rPMAC_CCKCRxRC32Er			0x184
-+#define		rPMAC_CCKCRxRC32OK			0x188
-+#define		rPMAC_TxStatus				0x18c
-+
-+
-+/*
-+ * 3. Page8(0x800)
-+ *   */
-+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
-+
-+#define		rFPGA0_TxInfo					0x804	/* Status report?? */
-+#define		rFPGA0_PSDFunction			0x808
-+
-+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
-+
-+#define		rFPGA0_RFTiming1				0x810	/* Useless now */
-+#define		rFPGA0_RFTiming2				0x814
-+
-+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
-+#define		rFPGA0_XA_HSSIParameter2		0x824
-+#define		rFPGA0_XB_HSSIParameter1		0x828
-+#define		rFPGA0_XB_HSSIParameter2		0x82c
-+
-+#define		rFPGA0_XA_LSSIParameter		0x840
-+#define		rFPGA0_XB_LSSIParameter		0x844
-+
-+#define		rFPGA0_RFWakeUpParameter	0x850	/* Useless now */
-+#define		rFPGA0_RFSleepUpParameter		0x854
-+
-+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
-+#define		rFPGA0_XCD_SwitchControl		0x85c
-+
-+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
-+#define		rFPGA0_XB_RFInterfaceOE		0x864
-+
-+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
-+#define		rFPGA0_XCD_RFInterfaceSW		0x874
-+
-+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
-+#define		rFPGA0_XCD_RFParameter		0x87c
-+
-+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
-+#define		rFPGA0_AnalogParameter2		0x884
-+#define		rFPGA0_AnalogParameter3		0x888
-+#define		rFPGA0_AdDaClockEn			0x888	/* enable ad/da clock1 for dual-phy */
-+#define		rFPGA0_AnalogParameter4		0x88c
-+
-+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
-+#define		rFPGA0_XB_LSSIReadBack		0x8a4
-+#define		rFPGA0_XC_LSSIReadBack		0x8a8
-+#define		rFPGA0_XD_LSSIReadBack		0x8ac
-+
-+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
-+#define		TransceiverA_HSPI_Readback		0x8b8	/* Transceiver A HSPI Readback */
-+#define		TransceiverB_HSPI_Readback		0x8bc	/* Transceiver B HSPI Readback */
-+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
-+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
-+
-+/*
-+ * 4. Page9(0x900)
-+ *   */
-+#define		rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
-+
-+#define		rFPGA1_TxBlock				0x904	/* Useless now */
-+#define		rFPGA1_DebugSelect			0x908	/* Useless now */
-+#define		rFPGA1_TxInfo					0x90c	/* Useless now */ /* Status report?? */
-+
-+/*
-+ * 5. PageA(0xA00)
-+ *
-+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
-+#define		rCCK0_System					0xa00
-+
-+#define		rCCK0_AFESetting				0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
-+#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
-+
-+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
-+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
-+
-+#define		rCCK0_RxHP					0xa14
-+
-+#define		rCCK0_DSPParameter1			0xa18	/* Timing recovery & Channel estimation threshold */
-+#define		rCCK0_DSPParameter2			0xa1c	/* SQ threshold */
-+
-+#define		rCCK0_TxFilter1				0xa20
-+#define		rCCK0_TxFilter2				0xa24
-+#define		rCCK0_DebugPort				0xa28	/* debug port and Tx filter3 */
-+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
-+#define		rCCK0_TRSSIReport			0xa50
-+#define		rCCK0_RxReport            			0xa54  /* 0xa57 */
-+#define		rCCK0_FACounterLower      		0xa5c  /* 0xa5b */
-+#define		rCCK0_FACounterUpper      		0xa58  /* 0xa5c */
-+
-+/*
-+ * PageB(0xB00)
-+ *   */
-+#define		rPdp_AntA					0xb00
-+#define		rPdp_AntA_4				0xb04
-+#define		rConfig_Pmpd_AntA			0xb28
-+#define		rConfig_ram64x16				0xb2c
-+
-+#define		rConfig_AntA					0xb68
-+#define		rConfig_AntB					0xb6c
-+#define		rPdp_AntB					0xb70
-+#define		rPdp_AntB_4					0xb74
-+#define		rConfig_Pmpd_AntB			0xb98
-+#define		rAPK							0xbd8
-+
-+
-+
-+/*
-+ * 6. PageC(0xC00)
-+ *   */
-+#define		rOFDM0_LSTF					0xc00
-+
-+#define		rOFDM0_TRxPathEnable			0xc04
-+#define		rOFDM0_TRMuxPar				0xc08
-+#define		rOFDM0_TRSWIsolation			0xc0c
-+
-+#define		rOFDM0_XARxAFE				0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
-+#define		rOFDM0_XARxIQImbalance    		0xc14  /* RxIQ imblance matrix */
-+#define		rOFDM0_XBRxAFE			0xc18
-+#define		rOFDM0_XBRxIQImbalance		0xc1c
-+#define		rOFDM0_XCRxAFE			0xc20
-+#define		rOFDM0_XCRxIQImbalance		0xc24
-+#define		rOFDM0_XDRxAFE			0xc28
-+#define		rOFDM0_XDRxIQImbalance		0xc2c
-+
-+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
-+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
-+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
-+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
-+
-+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
-+#define		rOFDM0_CFOandDAGC			0xc44  /* CFO & DAGC */
-+#define		rOFDM0_CCADropThreshold		0xc48 /* CCA Drop threshold */
-+#define		rOFDM0_ECCAThreshold			0xc4c /* energy CCA */
-+
-+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
-+#define		rOFDM0_XAAGCCore2			0xc54
-+#define		rOFDM0_XBAGCCore1			0xc58
-+#define		rOFDM0_XBAGCCore2			0xc5c
-+#define		rOFDM0_XCAGCCore1			0xc60
-+#define		rOFDM0_XCAGCCore2			0xc64
-+#define		rOFDM0_XDAGCCore1			0xc68
-+#define		rOFDM0_XDAGCCore2			0xc6c
-+
-+#define		rOFDM0_AGCParameter1		0xc70
-+#define		rOFDM0_AGCParameter2		0xc74
-+#define		rOFDM0_AGCRSSITable			0xc78
-+#define		rOFDM0_HTSTFAGC				0xc7c
-+
-+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
-+#define		rOFDM0_XATxAFE				0xc84
-+#define		rOFDM0_XBTxIQImbalance		0xc88
-+#define		rOFDM0_XBTxAFE				0xc8c
-+#define		rOFDM0_XCTxIQImbalance		0xc90
-+#define		rOFDM0_XCTxAFE			0xc94
-+#define		rOFDM0_XDTxIQImbalance		0xc98
-+#define		rOFDM0_XDTxAFE				0xc9c
-+
-+#define		rOFDM0_RxIQExtAnta			0xca0
-+#define		rOFDM0_TxCoeff1				0xca4
-+#define		rOFDM0_TxCoeff2				0xca8
-+#define		rOFDM0_TxCoeff3				0xcac
-+#define		rOFDM0_TxCoeff4				0xcb0
-+#define		rOFDM0_TxCoeff5				0xcb4
-+#define		rOFDM0_RxHPParameter		0xce0
-+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
-+#define		rOFDM0_FrameSync			0xcf0
-+#define		rOFDM0_DFSReport			0xcf4
-+
-+
-+/*
-+ * 7. PageD(0xD00)
-+ *   */
-+#define		rOFDM1_LSTF					0xd00
-+#define		rOFDM1_TRxPathEnable			0xd04
-+
-+#define		rOFDM1_CFO					0xd08	/* No setting now */
-+#define		rOFDM1_CSI1					0xd10
-+#define		rOFDM1_SBD					0xd14
-+#define		rOFDM1_CSI2					0xd18
-+#define		rOFDM1_CFOTracking			0xd2c
-+#define		rOFDM1_TRxMesaure1			0xd34
-+#define		rOFDM1_IntfDet				0xd3c
-+#define		rOFDM1_PseudoNoiseStateAB	0xd50
-+#define		rOFDM1_PseudoNoiseStateCD	0xd54
-+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
-+
-+#define		rOFDM_PHYCounter1			0xda0  /* cca, parity fail */
-+#define		rOFDM_PHYCounter2			0xda4  /* rate illegal, crc8 fail */
-+#define		rOFDM_PHYCounter3			0xda8  /* MCS not support */
-+
-+#define		rOFDM_ShortCFOAB			0xdac	/* No setting now */
-+#define		rOFDM_ShortCFOCD			0xdb0
-+#define		rOFDM_LongCFOAB				0xdb4
-+#define		rOFDM_LongCFOCD				0xdb8
-+#define		rOFDM_TailCFOAB				0xdbc
-+#define		rOFDM_TailCFOCD				0xdc0
-+#define		rOFDM_PWMeasure1		0xdc4
-+#define		rOFDM_PWMeasure2		0xdc8
-+#define		rOFDM_BWReport				0xdcc
-+#define		rOFDM_AGCReport				0xdd0
-+#define		rOFDM_RxSNR				0xdd4
-+#define		rOFDM_RxEVMCSI				0xdd8
-+#define		rOFDM_SIGReport				0xddc
-+
-+
-+/*
-+ * 8. PageE(0xE00)
-+ *   */
-+#define		rTxAGC_A_Rate18_06			0xe00
-+#define		rTxAGC_A_Rate54_24			0xe04
-+#define		rTxAGC_A_CCK1_Mcs32			0xe08
-+#define		rTxAGC_A_Mcs03_Mcs00		0xe10
-+#define		rTxAGC_A_Mcs07_Mcs04		0xe14
-+#define		rTxAGC_A_Mcs11_Mcs08		0xe18
-+#define		rTxAGC_A_Mcs15_Mcs12		0xe1c
-+
-+#define		rTxAGC_B_Rate18_06			0x830
-+#define		rTxAGC_B_Rate54_24			0x834
-+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
-+#define		rTxAGC_B_Mcs03_Mcs00		0x83c
-+#define		rTxAGC_B_Mcs07_Mcs04		0x848
-+#define		rTxAGC_B_Mcs11_Mcs08		0x84c
-+#define		rTxAGC_B_Mcs15_Mcs12		0x868
-+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
-+
-+#define		rFPGA0_IQK					0xe28
-+#define		rTx_IQK_Tone_A				0xe30
-+#define		rRx_IQK_Tone_A				0xe34
-+#define		rTx_IQK_PI_A					0xe38
-+#define		rRx_IQK_PI_A					0xe3c
-+
-+#define		rTx_IQK						0xe40
-+#define		rRx_IQK						0xe44
-+#define		rIQK_AGC_Pts					0xe48
-+#define		rIQK_AGC_Rsp					0xe4c
-+#define		rTx_IQK_Tone_B				0xe50
-+#define		rRx_IQK_Tone_B				0xe54
-+#define		rTx_IQK_PI_B					0xe58
-+#define		rRx_IQK_PI_B					0xe5c
-+#define		rIQK_AGC_Cont				0xe60
-+
-+#define		rBlue_Tooth					0xe6c
-+#define		rRx_Wait_CCA					0xe70
-+#define		rTx_CCK_RFON					0xe74
-+#define		rTx_CCK_BBON				0xe78
-+#define		rTx_OFDM_RFON				0xe7c
-+#define		rTx_OFDM_BBON				0xe80
-+#define		rTx_To_Rx					0xe84
-+#define		rTx_To_Tx					0xe88
-+#define		rRx_CCK						0xe8c
-+
-+#define		rTx_Power_Before_IQK_A		0xe94
-+#define		rTx_Power_After_IQK_A			0xe9c
-+
-+#define		rRx_Power_Before_IQK_A		0xea0
-+#define		rRx_Power_Before_IQK_A_2		0xea4
-+#define		rRx_Power_After_IQK_A			0xea8
-+#define		rRx_Power_After_IQK_A_2		0xeac
-+
-+#define		rTx_Power_Before_IQK_B		0xeb4
-+#define		rTx_Power_After_IQK_B			0xebc
-+
-+#define		rRx_Power_Before_IQK_B		0xec0
-+#define		rRx_Power_Before_IQK_B_2		0xec4
-+#define		rRx_Power_After_IQK_B			0xec8
-+#define		rRx_Power_After_IQK_B_2		0xecc
-+
-+#define		rRx_OFDM					0xed0
-+#define		rRx_Wait_RIFS				0xed4
-+#define		rRx_TO_Rx					0xed8
-+#define		rStandby						0xedc
-+#define		rSleep						0xee0
-+#define		rPMPD_ANAEN				0xeec
-+
-+/*
-+ * 7. RF Register 0x00-0x2E (RF 8256)
-+ * RF-0222D 0x00-3F
-+ *
-+ * Zebra1 */
-+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
-+#define		rZebra1_TRxEnable1			0x1
-+#define		rZebra1_TRxEnable2			0x2
-+#define		rZebra1_AGC					0x4
-+#define		rZebra1_ChargePump			0x5
-+#define		rZebra1_Channel				0x7	/* RF channel switch */
-+
-+/* #endif */
-+#define		rZebra1_TxGain				0x8	/* Useless now */
-+#define		rZebra1_TxLPF					0x9
-+#define		rZebra1_RxLPF					0xb
-+#define		rZebra1_RxHPFCorner			0xc
-+
-+/* Zebra4 */
-+#define		rGlobalCtrl					0	/* Useless now */
-+#define		rRTL8256_TxLPF				19
-+#define		rRTL8256_RxLPF				11
-+
-+/* RTL8258 */
-+#define		rRTL8258_TxLPF				0x11	/* Useless now */
-+#define		rRTL8258_RxLPF				0x13
-+#define		rRTL8258_RSSILPF				0xa
-+
-+/*
-+ * RL6052 Register definition
-+ *   */
-+#define		RF_AC						0x00	/*  */
-+
-+#define		RF_IQADJ_G1					0x01	/*  */
-+#define		RF_IQADJ_G2					0x02	/*  */
-+
-+#define		RF_POW_TRSW				0x05	/*  */
-+
-+#define		RF_GAIN_RX					0x06	/*  */
-+#define		RF_GAIN_TX					0x07	/*  */
-+
-+#define		RF_TXM_IDAC					0x08	/*  */
-+#define		RF_IPA_G						0x09	/*  */
-+#define		RF_TXBIAS_G					0x0A
-+#define		RF_TXPA_AG					0x0B
-+#define		RF_IPA_A						0x0C	/*  */
-+#define		RF_TXBIAS_A					0x0D
-+#define		RF_BS_PA_APSET_G9_G11		0x0E
-+#define		RF_BS_IQGEN					0x0F	/*  */
-+
-+#define		RF_MODE1					0x10	/*  */
-+#define		RF_MODE2					0x11	/*  */
-+
-+#define		RF_RX_AGC_HP				0x12	/*  */
-+#define		RF_TX_AGC					0x13	/*  */
-+#define		RF_BIAS						0x14	/*  */
-+#define		RF_IPA						0x15	/*  */
-+#define		RF_TXBIAS					0x16
-+#define		RF_POW_ABILITY				0x17	/*  */
-+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
-+#define		RF_TOP						0x19	/*  */
-+
-+#define		RF_RX_G1					0x1A	/*  */
-+#define		RF_RX_G2					0x1B	/*  */
-+
-+#define		RF_RX_BB2					0x1C	/*  */
-+#define		RF_RX_BB1					0x1D	/*  */
-+
-+#define		RF_RCK1						0x1E	/*  */
-+#define		RF_RCK2						0x1F	/*  */
-+
-+#define		RF_TX_G1						0x20	/*  */
-+#define		RF_TX_G2						0x21	/*  */
-+#define		RF_TX_G3						0x22	/*  */
-+
-+#define		RF_TX_BB1					0x23	/*  */
-+
-+#define		RF_T_METER_8192E			0x42	/*  */
-+#define		RF_T_METER_88E				0x42
-+#define		RF_T_METER					0x24	/*  */
-+
-+/* #endif */
-+
-+#define		RF_SYN_G1					0x25	/* RF TX Power control */
-+#define		RF_SYN_G2					0x26	/* RF TX Power control */
-+#define		RF_SYN_G3					0x27	/* RF TX Power control */
-+#define		RF_SYN_G4					0x28	/* RF TX Power control */
-+#define		RF_SYN_G5					0x29	/* RF TX Power control */
-+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
-+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
-+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
-+
-+#define		RF_RCK_OS					0x30	/* RF TX PA control */
-+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
-+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
-+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
-+#define		RF_TX_BIAS_A					0x35
-+#define		RF_TX_BIAS_D					0x36
-+#define		RF_LOBF_9					0x38
-+#define		RF_RXRF_A3					0x3C	/*	 */
-+#define		RF_TRSW						0x3F
-+
-+#define		RF_TXRF_A2					0x41
-+#define		RF_TXPA_G4					0x46
-+#define		RF_TXPA_A4					0x4B
-+#define		RF_0x52						0x52
-+#define		RF_LDO						0xB1
-+#define		RF_WE_LUT					0xEF
-+
-+
-+/*
-+ * Bit Mask
-+ *
-+ * 1. Page1(0x100) */
-+#define		bBBResetB					0x100	/* Useless now? */
-+#define		bGlobalResetB					0x200
-+#define		bOFDMTxStart					0x4
-+#define		bCCKTxStart					0x8
-+#define		bCRC32Debug					0x100
-+#define		bPMACLoopback				0x10
-+#define		bTxLSIG						0xffffff
-+#define		bOFDMTxRate					0xf
-+#define		bOFDMTxReserved				0x10
-+#define		bOFDMTxLength				0x1ffe0
-+#define		bOFDMTxParity				0x20000
-+#define		bTxHTSIG1					0xffffff
-+#define		bTxHTMCSRate				0x7f
-+#define		bTxHTBW						0x80
-+#define		bTxHTLength					0xffff00
-+#define		bTxHTSIG2					0xffffff
-+#define		bTxHTSmoothing				0x1
-+#define		bTxHTSounding				0x2
-+#define		bTxHTReserved				0x4
-+#define		bTxHTAggreation				0x8
-+#define		bTxHTSTBC					0x30
-+#define		bTxHTAdvanceCoding			0x40
-+#define		bTxHTShortGI					0x80
-+#define		bTxHTNumberHT_LTF			0x300
-+#define		bTxHTCRC8					0x3fc00
-+#define		bCounterReset				0x10000
-+#define		bNumOfOFDMTx				0xffff
-+#define		bNumOfCCKTx					0xffff0000
-+#define		bTxIdleInterval				0xffff
-+#define		bOFDMService					0xffff0000
-+#define		bTxMACHeader				0xffffffff
-+#define		bTxDataInit					0xff
-+#define		bTxHTMode					0x100
-+#define		bTxDataType					0x30000
-+#define		bTxRandomSeed				0xffffffff
-+#define		bCCKTxPreamble				0x1
-+#define		bCCKTxSFD					0xffff0000
-+#define		bCCKTxSIG					0xff
-+#define		bCCKTxService					0xff00
-+#define		bCCKLengthExt					0x8000
-+#define		bCCKTxLength					0xffff0000
-+#define		bCCKTxCRC16					0xffff
-+#define		bCCKTxStatus					0x1
-+#define		bOFDMTxStatus				0x2
-+
-+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
-+#define		RF_TX_GAIN_OFFSET_8192E(_val)		((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
-+
-+
-+/* 2. Page8(0x800) */
-+#define		bRFMOD						0x1	/* Reg 0x800 rFPGA0_RFMOD */
-+#define		bJapanMode					0x2
-+#define		bCCKTxSC						0x30
-+#define		bCCKEn						0x1000000
-+#define		bOFDMEn					0x2000000
-+
-+#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
-+#define		bOFDMTxDACPhase		0x40000
-+#define		bXATxAGC				0x3f
-+
-+#define		bAntennaSelect			0x0300
-+
-+#define		bXBTxAGC                  				0xf00	/* Reg 80c rFPGA0_TxGainStage */
-+#define		bXCTxAGC				0xf000
-+#define		bXDTxAGC				0xf0000
-+
-+#define		bPAStart                  				0xf0000000	/* Useless now */
-+#define		bTRStart				0x00f00000
-+#define		bRFStart				0x0000f000
-+#define		bBBStart				0x000000f0
-+#define		bBBCCKStart			0x0000000f
-+#define		bPAEnd                    				0xf          /* Reg0x814 */
-+#define		bTREnd				0x0f000000
-+#define		bRFEnd				0x000f0000
-+#define		bCCAMask                  				0x000000f0   /* T2R */
-+#define		bR2RCCAMask			0x00000f00
-+#define		bHSSI_R2TDelay			0xf8000000
-+#define		bHSSI_T2RDelay			0xf80000
-+#define		bContTxHSSI               			0x400     /* chane gain at continue Tx */
-+#define		bIGFromCCK			0x200
-+#define		bAGCAddress			0x3f
-+#define		bRxHPTx				0x7000
-+#define		bRxHPT2R				0x38000
-+#define		bRxHPCCKIni			0xc0000
-+#define		bAGCTxCode			0xc00000
-+#define		bAGCRxCode			0x300000
-+
-+#define		b3WireDataLength          			0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
-+#define		b3WireAddressLength		0x400
-+
-+#define		b3WireRFPowerDown         		0x1	/* Useless now
-+ * #define bHWSISelect		0x8 */
-+#define		b5GPAPEPolarity			0x40000000
-+#define		b2GPAPEPolarity			0x80000000
-+#define		bRFSW_TxDefaultAnt		0x3
-+#define		bRFSW_TxOptionAnt		0x30
-+#define		bRFSW_RxDefaultAnt		0x300
-+#define		bRFSW_RxOptionAnt		0x3000
-+#define		bRFSI_3WireData			0x1
-+#define		bRFSI_3WireClock			0x2
-+#define		bRFSI_3WireLoad			0x4
-+#define		bRFSI_3WireRW			0x8
-+#define		bRFSI_3Wire			0xf
-+
-+#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
-+
-+#define		bRFSI_TRSW                		0x20	/* Useless now */
-+#define		bRFSI_TRSWB		0x40
-+#define		bRFSI_ANTSW		0x100
-+#define		bRFSI_ANTSWB		0x200
-+#define		bRFSI_PAPE			0x400
-+#define		bRFSI_PAPE5G		0x800
-+#define		bBandSelect			0x1
-+#define		bHTSIG2_GI			0x80
-+#define		bHTSIG2_Smoothing		0x01
-+#define		bHTSIG2_Sounding		0x02
-+#define		bHTSIG2_Aggreaton		0x08
-+#define		bHTSIG2_STBC		0x30
-+#define		bHTSIG2_AdvCoding		0x40
-+#define		bHTSIG2_NumOfHTLTF	0x300
-+#define		bHTSIG2_CRC8		0x3fc
-+#define		bHTSIG1_MCS		0x7f
-+#define		bHTSIG1_BandWidth		0x80
-+#define		bHTSIG1_HTLength		0xffff
-+#define		bLSIG_Rate			0xf
-+#define		bLSIG_Reserved		0x10
-+#define		bLSIG_Length		0x1fffe
-+#define		bLSIG_Parity			0x20
-+#define		bCCKRxPhase		0x4
-+
-+#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
-+
-+#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
-+
-+#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
-+
-+#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
-+#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
-+#define		bRegulator0Standby		0x1
-+#define		bRegulatorPLLStandby	0x2
-+#define		bRegulator1Standby		0x4
-+#define		bPLLPowerUp		0x8
-+#define		bDPLLPowerUp		0x10
-+#define		bDA10PowerUp		0x20
-+#define		bAD7PowerUp		0x200
-+#define		bDA6PowerUp		0x2000
-+#define		bXtalPowerUp		0x4000
-+#define		b40MDClkPowerUP	0x8000
-+#define		bDA6DebugMode		0x20000
-+#define		bDA6Swing			0x380000
-+
-+#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
-+
-+#define		b80MClkDelay              		0x18000000	/* Useless */
-+#define		bAFEWatchDogEnable	0x20000000
-+
-+#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
-+#define		bXtalCap23			0x3
-+#define		bXtalCap92x				0x0f000000
-+#define		bXtalCap			0x0f000000
-+
-+#define		bIntDifClkEnable          		0x400	/* Useless */
-+#define		bExtSigClkEnable		0x800
-+#define		bBandgapMbiasPowerUp	0x10000
-+#define		bAD11SHGain		0xc0000
-+#define		bAD11InputRange		0x700000
-+#define		bAD11OPCurrent		0x3800000
-+#define		bIPathLoopback		0x4000000
-+#define		bQPathLoopback		0x8000000
-+#define		bAFELoopback		0x10000000
-+#define		bDA10Swing		0x7e0
-+#define		bDA10Reverse		0x800
-+#define		bDAClkSource		0x1000
-+#define		bAD7InputRange		0x6000
-+#define		bAD7Gain			0x38000
-+#define		bAD7OutputCMMode	0x40000
-+#define		bAD7InputCMMode	0x380000
-+#define		bAD7Current		0xc00000
-+#define		bRegulatorAdjust		0x7000000
-+#define		bAD11PowerUpAtTx	0x1
-+#define		bDA10PSAtTx		0x10
-+#define		bAD11PowerUpAtRx	0x100
-+#define		bDA10PSAtRx		0x1000
-+#define		bCCKRxAGCFormat		0x200
-+#define		bPSDFFTSamplepPoint	0xc000
-+#define		bPSDAverageNum		0x3000
-+#define		bIQPathControl		0xc00
-+#define		bPSDFreq			0x3ff
-+#define		bPSDAntennaPath		0x30
-+#define		bPSDIQSwitch		0x40
-+#define		bPSDRxTrigger		0x400000
-+#define		bPSDTxTrigger		0x80000000
-+#define		bPSDSineToneScale		0x7f000000
-+#define		bPSDReport		0xffff
-+
-+/* 3. Page9(0x900) */
-+#define		bOFDMTxSC                 		0x30000000	/* Useless */
-+#define		bCCKTxOn			0x1
-+#define		bOFDMTxOn		0x2
-+#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
-+#define		bDebugItem                		0xff   /* reset debug page and LWord */
-+#define		bAntL				0x10
-+#define		bAntNonHT			0x100
-+#define		bAntHT1			0x1000
-+#define		bAntHT2			0x10000
-+#define		bAntHT1S1			0x100000
-+#define		bAntNonHTS1		0x1000000
-+
-+/* 4. PageA(0xA00) */
-+#define		bCCKBBMode                		0x3	/* Useless */
-+#define		bCCKTxPowerSaving		0x80
-+#define		bCCKRxPowerSaving		0x40
-+
-+#define		bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
-+
-+#define		bCCKScramble              		0x8	/* Useless */
-+#define		bCCKAntDiversity			0x8000
-+#define		bCCKCarrierRecovery		0x4000
-+#define		bCCKTxRate			0x3000
-+#define		bCCKDCCancel		0x0800
-+#define		bCCKISICancel		0x0400
-+#define		bCCKMatchFilter		0x0200
-+#define		bCCKEqualizer		0x0100
-+#define		bCCKPreambleDetect		0x800000
-+#define		bCCKFastFalseCCA		0x400000
-+#define		bCCKChEstStart		0x300000
-+#define		bCCKCCACount		0x080000
-+#define		bCCKcs_lim			0x070000
-+#define		bCCKBistMode		0x80000000
-+#define		bCCKCCAMask		0x40000000
-+#define		bCCKTxDACPhase		0x4
-+#define		bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
-+#define		bCCKr_cp_mode0		0x0100
-+#define		bCCKTxDCOffset		0xf0
-+#define		bCCKRxDCOffset		0xf
-+#define		bCCKCCAMode		0xc000
-+#define		bCCKFalseCS_lim		0x3f00
-+#define		bCCKCS_ratio		0xc00000
-+#define		bCCKCorgBit_sel		0x300000
-+#define		bCCKPD_lim		0x0f0000
-+#define		bCCKNewCCA		0x80000000
-+#define		bCCKRxHPofIG		0x8000
-+#define		bCCKRxIG			0x7f00
-+#define		bCCKLNAPolarity		0x800000
-+#define		bCCKRx1stGain		0x7f0000
-+#define		bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
-+#define		bCCKRxAGCSatLevel		0x1f000000
-+#define		bCCKRxAGCSatCount		0xe0
-+#define		bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
-+#define		bCCKFixedRxAGC		0x8000
-+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
-+#define		bCCKAntennaPolarity		0x2000
-+#define		bCCKTxFilterType		0x0c00
-+#define		bCCKRxAGCReportType		0x0300
-+#define		bCCKRxDAGCEn		0x80000000
-+#define		bCCKRxDAGCPeriod		0x20000000
-+#define		bCCKRxDAGCSatLevel		0x1f000000
-+#define		bCCKTimingRecovery		0x800000
-+#define		bCCKTxC0			0x3f0000
-+#define		bCCKTxC1			0x3f000000
-+#define		bCCKTxC2			0x3f
-+#define		bCCKTxC3			0x3f00
-+#define		bCCKTxC4			0x3f0000
-+#define		bCCKTxC5			0x3f000000
-+#define		bCCKTxC6			0x3f
-+#define		bCCKTxC7			0x3f00
-+#define		bCCKDebugPort		0xff0000
-+#define		bCCKDACDebug		0x0f000000
-+#define		bCCKFalseAlarmEnable	0x8000
-+#define		bCCKFalseAlarmRead	0x4000
-+#define		bCCKTRSSI			0x7f
-+#define		bCCKRxAGCReport		0xfe
-+#define		bCCKRxReport_AntSel	0x80000000
-+#define		bCCKRxReport_MFOff	0x40000000
-+#define		bCCKRxRxReport_SQLoss	0x20000000
-+#define		bCCKRxReport_Pktloss	0x10000000
-+#define		bCCKRxReport_Lockedbit	0x08000000
-+#define		bCCKRxReport_RateError	0x04000000
-+#define		bCCKRxReport_RxRate	0x03000000
-+#define		bCCKRxFACounterLower	0xff
-+#define		bCCKRxFACounterUpper	0xff000000
-+#define		bCCKRxHPAGCStart		0xe000
-+#define		bCCKRxHPAGCFinal		0x1c00
-+#define		bCCKRxFalseAlarmEnable	0x8000
-+#define		bCCKFACounterFreeze	0x4000
-+#define		bCCKTxPathSel		0x10000000
-+#define		bCCKDefaultRxPath		0xc000000
-+#define		bCCKOptionRxPath		0x3000000
-+
-+/* 5. PageC(0xC00) */
-+#define		bNumOfSTF                			0x3	/* Useless */
-+#define		bShift_L			0xc0
-+#define		bGI_TH			0xc
-+#define		bRxPathA			0x1
-+#define		bRxPathB			0x2
-+#define		bRxPathC			0x4
-+#define		bRxPathD			0x8
-+#define		bTxPathA			0x1
-+#define		bTxPathB			0x2
-+#define		bTxPathC			0x4
-+#define		bTxPathD			0x8
-+#define		bTRSSIFreq			0x200
-+#define		bADCBackoff			0x3000
-+#define		bDFIRBackoff			0xc000
-+#define		bTRSSILatchPhase		0x10000
-+#define		bRxIDCOffset			0xff
-+#define		bRxQDCOffset		0xff00
-+#define		bRxDFIRMode		0x1800000
-+#define		bRxDCNFType		0xe000000
-+#define		bRXIQImb_A		0x3ff
-+#define		bRXIQImb_B			0xfc00
-+#define		bRXIQImb_C			0x3f0000
-+#define		bRXIQImb_D		0xffc00000
-+#define		bDC_dc_Notch		0x60000
-+#define		bRxNBINotch		0x1f000000
-+#define		bPD_TH			0xf
-+#define		bPD_TH_Opt2		0xc000
-+#define		bPWED_TH			0x700
-+#define		bIfMF_Win_L		0x800
-+#define		bPD_Option			0x1000
-+#define		bMF_Win_L			0xe000
-+#define		bBW_Search_L		0x30000
-+#define		bwin_enh_L			0xc0000
-+#define		bBW_TH			0x700000
-+#define		bED_TH2			0x3800000
-+#define		bBW_option			0x4000000
-+#define		bRatio_TH			0x18000000
-+#define		bWindow_L			0xe0000000
-+#define		bSBD_Option		0x1
-+#define		bFrame_TH			0x1c
-+#define		bFS_Option			0x60
-+#define		bDC_Slope_check		0x80
-+#define		bFGuard_Counter_DC_L	0xe00
-+#define		bFrame_Weight_Short	0x7000
-+#define		bSub_Tune			0xe00000
-+#define		bFrame_DC_Length		0xe000000
-+#define		bSBD_start_offset		0x30000000
-+#define		bFrame_TH_2		0x7
-+#define		bFrame_GI2_TH		0x38
-+#define		bGI2_Sync_en		0x40
-+#define		bSarch_Short_Early		0x300
-+#define		bSarch_Short_Late		0xc00
-+#define		bSarch_GI2_Late		0x70000
-+#define		bCFOAntSum		0x1
-+#define		bCFOAcc			0x2
-+#define		bCFOStartOffset		0xc
-+#define		bCFOLookBack		0x70
-+#define		bCFOSumWeight		0x80
-+#define		bDAGCEnable		0x10000
-+#define		bTXIQImb_A			0x3ff
-+#define		bTXIQImb_B			0xfc00
-+#define		bTXIQImb_C			0x3f0000
-+#define		bTXIQImb_D			0xffc00000
-+#define		bTxIDCOffset			0xff
-+#define		bTxQDCOffset		0xff00
-+#define		bTxDFIRMode		0x10000
-+#define		bTxPesudoNoiseOn		0x4000000
-+#define		bTxPesudoNoise_A		0xff
-+#define		bTxPesudoNoise_B		0xff00
-+#define		bTxPesudoNoise_C		0xff0000
-+#define		bTxPesudoNoise_D		0xff000000
-+#define		bCCADropOption		0x20000
-+#define		bCCADropThres		0xfff00000
-+#define		bEDCCA_H			0xf
-+#define		bEDCCA_L			0xf0
-+#define		bLambda_ED		0x300
-+#define		bRxInitialGain			0x7f
-+#define		bRxAntDivEn		0x80
-+#define		bRxAGCAddressForLNA	0x7f00
-+#define		bRxHighPowerFlow		0x8000
-+#define		bRxAGCFreezeThres		0xc0000
-+#define		bRxFreezeStep_AGC1	0x300000
-+#define		bRxFreezeStep_AGC2	0xc00000
-+#define		bRxFreezeStep_AGC3	0x3000000
-+#define		bRxFreezeStep_AGC0	0xc000000
-+#define		bRxRssi_Cmp_En		0x10000000
-+#define		bRxQuickAGCEn		0x20000000
-+#define		bRxAGCFreezeThresMode	0x40000000
-+#define		bRxOverFlowCheckType	0x80000000
-+#define		bRxAGCShift			0x7f
-+#define		bTRSW_Tri_Only		0x80
-+#define		bPowerThres		0x300
-+#define		bRxAGCEn			0x1
-+#define		bRxAGCTogetherEn		0x2
-+#define		bRxAGCMin		0x4
-+#define		bRxHP_Ini			0x7
-+#define		bRxHP_TRLNA		0x70
-+#define		bRxHP_RSSI			0x700
-+#define		bRxHP_BBP1		0x7000
-+#define		bRxHP_BBP2		0x70000
-+#define		bRxHP_BBP3		0x700000
-+#define		bRSSI_H                  			0x7f0000     /* the threshold for high power */
-+#define		bRSSI_Gen                			0x7f000000   /* the threshold for ant diversity */
-+#define		bRxSettle_TRSW		0x7
-+#define		bRxSettle_LNA		0x38
-+#define		bRxSettle_RSSI		0x1c0
-+#define		bRxSettle_BBP		0xe00
-+#define		bRxSettle_RxHP		0x7000
-+#define		bRxSettle_AntSW_RSSI	0x38000
-+#define		bRxSettle_AntSW		0xc0000
-+#define		bRxProcessTime_DAGC	0x300000
-+#define		bRxSettle_HSSI		0x400000
-+#define		bRxProcessTime_BBPPW	0x800000
-+#define		bRxAntennaPowerShift	0x3000000
-+#define		bRSSITableSelect		0xc000000
-+#define		bRxHP_Final			0x7000000
-+#define		bRxHTSettle_BBP		0x7
-+#define		bRxHTSettle_HSSI		0x8
-+#define		bRxHTSettle_RxHP		0x70
-+#define		bRxHTSettle_BBPPW		0x80
-+#define		bRxHTSettle_Idle		0x300
-+#define		bRxHTSettle_Reserved	0x1c00
-+#define		bRxHTRxHPEn		0x8000
-+#define		bRxHTAGCFreezeThres	0x30000
-+#define		bRxHTAGCTogetherEn	0x40000
-+#define		bRxHTAGCMin		0x80000
-+#define		bRxHTAGCEn		0x100000
-+#define		bRxHTDAGCEn		0x200000
-+#define		bRxHTRxHP_BBP		0x1c00000
-+#define		bRxHTRxHP_Final		0xe0000000
-+#define		bRxPWRatioTH		0x3
-+#define		bRxPWRatioEn		0x4
-+#define		bRxMFHold			0x3800
-+#define		bRxPD_Delay_TH1		0x38
-+#define		bRxPD_Delay_TH2		0x1c0
-+#define		bRxPD_DC_COUNT_MAX	0x600
-+/* #define bRxMF_Hold               0x3800 */
-+#define		bRxPD_Delay_TH		0x8000
-+#define		bRxProcess_Delay		0xf0000
-+#define		bRxSearchrange_GI2_Early	0x700000
-+#define		bRxFrame_Guard_Counter_L	0x3800000
-+#define		bRxSGI_Guard_L		0xc000000
-+#define		bRxSGI_Search_L		0x30000000
-+#define		bRxSGI_TH			0xc0000000
-+#define		bDFSCnt0			0xff
-+#define		bDFSCnt1			0xff00
-+#define		bDFSFlag			0xf0000
-+#define		bMFWeightSum		0x300000
-+#define		bMinIdxTH			0x7f000000
-+#define		bDAFormat			0x40000
-+#define		bTxChEmuEnable		0x01000000
-+#define		bTRSWIsolation_A		0x7f
-+#define		bTRSWIsolation_B		0x7f00
-+#define		bTRSWIsolation_C		0x7f0000
-+#define		bTRSWIsolation_D		0x7f000000
-+#define		bExtLNAGain		0x7c00
-+
-+/* 6. PageE(0xE00) */
-+#define		bSTBCEn                  			0x4	/* Useless */
-+#define		bAntennaMapping		0x10
-+#define		bNss			0x20
-+#define		bCFOAntSumD		0x200
-+#define		bPHYCounterReset		0x8000000
-+#define		bCFOReportGet		0x4000000
-+#define		bOFDMContinueTx		0x10000000
-+#define		bOFDMSingleCarrier		0x20000000
-+#define		bOFDMSingleTone		0x40000000
-+/* #define bRxPath1                 0x01 */
-+/* #define bRxPath2                 0x02 */
-+/* #define bRxPath3                 0x04 */
-+/* #define bRxPath4                 0x08 */
-+/* #define bTxPath1                 0x10 */
-+/* #define bTxPath2                 0x20 */
-+#define		bHTDetect			0x100
-+#define		bCFOEn			0x10000
-+#define		bCFOValue			0xfff00000
-+#define		bSigTone_Re			0x3f
-+#define		bSigTone_Im			0x7f00
-+#define		bCounter_CCA		0xffff
-+#define		bCounter_ParityFail		0xffff0000
-+#define		bCounter_RateIllegal		0xffff
-+#define		bCounter_CRC8Fail		0xffff0000
-+#define		bCounter_MCSNoSupport	0xffff
-+#define		bCounter_FastSync		0xffff
-+#define		bShortCFO			0xfff
-+#define		bShortCFOTLength         		12   /* total */
-+#define		bShortCFOFLength         		11   /* fraction */
-+#define		bLongCFO			0x7ff
-+#define		bLongCFOTLength		11
-+#define		bLongCFOFLength		11
-+#define		bTailCFO			0x1fff
-+#define		bTailCFOTLength		13
-+#define		bTailCFOFLength		12
-+#define		bmax_en_pwdB		0xffff
-+#define		bCC_power_dB		0xffff0000
-+#define		bnoise_pwdB		0xffff
-+#define		bPowerMeasTLength	10
-+#define		bPowerMeasFLength	3
-+#define		bRx_HT_BW		0x1
-+#define		bRxSC			0x6
-+#define		bRx_HT			0x8
-+#define		bNB_intf_det_on		0x1
-+#define		bIntf_win_len_cfg		0x30
-+#define		bNB_Intf_TH_cfg		0x1c0
-+#define		bRFGain			0x3f
-+#define		bTableSel			0x40
-+#define		bTRSW			0x80
-+#define		bRxSNR_A			0xff
-+#define		bRxSNR_B			0xff00
-+#define		bRxSNR_C			0xff0000
-+#define		bRxSNR_D			0xff000000
-+#define		bSNREVMTLength		8
-+#define		bSNREVMFLength		1
-+#define		bCSI1st			0xff
-+#define		bCSI2nd			0xff00
-+#define		bRxEVM1st			0xff0000
-+#define		bRxEVM2nd		0xff000000
-+#define		bSIGEVM			0xff
-+#define		bPWDB			0xff00
-+#define		bSGIEN			0x10000
-+
-+#define		bSFactorQAM1             		0xf	/* Useless */
-+#define		bSFactorQAM2		0xf0
-+#define		bSFactorQAM3		0xf00
-+#define		bSFactorQAM4		0xf000
-+#define		bSFactorQAM5		0xf0000
-+#define		bSFactorQAM6		0xf0000
-+#define		bSFactorQAM7		0xf00000
-+#define		bSFactorQAM8		0xf000000
-+#define		bSFactorQAM9		0xf0000000
-+#define		bCSIScheme			0x100000
-+
-+#define		bNoiseLvlTopSet          		0x3	/* Useless */
-+#define		bChSmooth			0x4
-+#define		bChSmoothCfg1		0x38
-+#define		bChSmoothCfg2		0x1c0
-+#define		bChSmoothCfg3		0xe00
-+#define		bChSmoothCfg4		0x7000
-+#define		bMRCMode		0x800000
-+#define		bTHEVMCfg			0x7000000
-+
-+#define		bLoopFitType             			0x1	/* Useless */
-+#define		bUpdCFO			0x40
-+#define		bUpdCFOOffData		0x80
-+#define		bAdvUpdCFO		0x100
-+#define		bAdvTimeCtrl		0x800
-+#define		bUpdClko			0x1000
-+#define		bFC				0x6000
-+#define		bTrackingMode		0x8000
-+#define		bPhCmpEnable		0x10000
-+#define		bUpdClkoLTF			0x20000
-+#define		bComChCFO		0x40000
-+#define		bCSIEstiMode		0x80000
-+#define		bAdvUpdEqz		0x100000
-+#define		bUChCfg			0x7000000
-+#define		bUpdEqz			0x8000000
-+
-+/* Rx Pseduo noise */
-+#define		bRxPesudoNoiseOn         		0x20000000	/* Useless */
-+#define		bRxPesudoNoise_A		0xff
-+#define		bRxPesudoNoise_B		0xff00
-+#define		bRxPesudoNoise_C		0xff0000
-+#define		bRxPesudoNoise_D		0xff000000
-+#define		bPesudoNoiseState_A	0xffff
-+#define		bPesudoNoiseState_B	0xffff0000
-+#define		bPesudoNoiseState_C		0xffff
-+#define		bPesudoNoiseState_D	0xffff0000
-+
-+/* 7. RF Register
-+ * Zebra1 */
-+#define		bZebra1_HSSIEnable        		0x8		/* Useless */
-+#define		bZebra1_TRxControl		0xc00
-+#define		bZebra1_TRxGainSetting	0x07f
-+#define		bZebra1_RxCorner		0xc00
-+#define		bZebra1_TxChargePump	0x38
-+#define		bZebra1_RxChargePump	0x7
-+#define		bZebra1_ChannelNum	0xf80
-+#define		bZebra1_TxLPFBW		0x400
-+#define		bZebra1_RxLPFBW		0x600
-+
-+/* Zebra4 */
-+#define		bRTL8256RegModeCtrl1      	0x100	/* Useless */
-+#define		bRTL8256RegModeCtrl0	0x40
-+#define		bRTL8256_TxLPFBW	0x18
-+#define		bRTL8256_RxLPFBW	0x600
-+
-+/* RTL8258 */
-+#define		bRTL8258_TxLPFBW          	0xc	/* Useless */
-+#define		bRTL8258_RxLPFBW	0xc00
-+#define		bRTL8258_RSSILPFBW	0xc0
-+
-+
-+/*
-+ * Other Definition
-+ *   */
-+
-+/* byte endable for sb_write */
-+#define		bByte0                    			0x1	/* Useless */
-+#define		bByte1			0x2
-+#define		bByte2			0x4
-+#define		bByte3			0x8
-+#define		bWord0			0x3
-+#define		bWord1			0xc
-+#define		bDWord			0xf
-+
-+/* for PutRegsetting & GetRegSetting BitMask */
-+#define		bMaskByte0                		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
-+#define		bMaskByte1		0xff00
-+#define		bMaskByte2		0xff0000
-+#define		bMaskByte3		0xff000000
-+#define		bMaskHWord		0xffff0000
-+#define		bMaskLWord		0x0000ffff
-+#define		bMaskDWord		0xffffffff
-+#define		bMaskH3Bytes				0xffffff00
-+#define		bMask12Bits				0xfff
-+#define		bMaskH4Bits				0xf0000000
-+#define		bMaskOFDM_D			0xffc00000
-+#define		bMaskCCK				0x3f3f3f3f
-+
-+/* for PutRFRegsetting & GetRFRegSetting BitMask
-+ * #define		bMask12Bits               0xfffff */	/* RF Reg mask bits
-+ * #define		bMask20Bits               0xfffff */	/* RF Reg mask bits T65 RF */
-+#define		bRFRegOffsetMask			0xfffff
-+
-+#define		bEnable                   0x1	/* Useless */
-+#define		bDisable                  0x0
-+
-+#define		LeftAntenna               			0x0	/* Useless */
-+#define		RightAntenna		0x1
-+
-+#define		tCheckTxStatus            		500   /* 500ms */ /* Useless */
-+#define		tUpdateRxCounter          		100   /* 100ms */
-+
-+#define		rateCCK     				0	/* Useless */
-+#define		rateOFDM				1
-+#define		rateHT					2
-+
-+/* define Register-End */
-+#define		bPMAC_End                 		0x1ff	/* Useless */
-+#define		bFPGAPHY0_End		0x8ff
-+#define		bFPGAPHY1_End		0x9ff
-+#define		bCCKPHY0_End		0xaff
-+#define		bOFDMPHY0_End		0xcff
-+#define		bOFDMPHY1_End		0xdff
-+
-+/* define max debug item in each debug page
-+ * #define bMaxItem_FPGA_PHY0        0x9
-+ * #define bMaxItem_FPGA_PHY1        0x3
-+ * #define bMaxItem_PHY_11B          0x16
-+ * #define bMaxItem_OFDM_PHY0        0x29
-+ * #define bMaxItem_OFDM_PHY1        0x0 */
-+
-+#define		bPMACControl              		0x0		/* Useless */
-+#define		bWMACControl		0x1
-+#define		bWNICControl		0x2
-+
-+#define		PathA                     			0x0	/* Useless */
-+#define		PathB			0x1
-+#define		PathC			0x2
-+#define		PathD			0x3
-+
-+
-+/* RSSI Dump Message */
-+#define		rA_RSSIDump_92E			0xcb0
-+#define		rB_RSSIDump_92E			0xcb1
-+#define		rS1_RXevmDump_92E			0xcb2
-+#define		rS2_RXevmDump_92E			0xcb3
-+#define		rA_RXsnrDump_92E			0xcb4
-+#define		rB_RXsnrDump_92E			0xcb5
-+#define		rA_CfoShortDump_92E		0xcb6
-+#define		rB_CfoShortDump_92E		0xcb8
-+#define	rA_CfoLongDump_92E			0xcba
-+#define		rB_CfoLongDump_92E			0xcbc
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+
-+#endif /* __INC_HAL8188EPHYREG_H */
-diff --git a/drivers/staging/rtl8723cs/include/Hal8192EPwrSeq.h b/drivers/staging/rtl8723cs/include/Hal8192EPwrSeq.h
-new file mode 100644
-index 000000000000..1f2ba8722572
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8192EPwrSeq.h
-@@ -0,0 +1,169 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2012 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef REALTEK_POWER_SEQUENCE_8192E
-+#define REALTEK_POWER_SEQUENCE_8192E
-+
-+#include "HalPwrSeqCmd.h"
-+/*
-+	Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd
-+	There are 6 HW Power States:
-+	0: POFF--Power Off
-+	1: PDN--Power Down
-+	2: CARDEMU--Card Emulation
-+	3: ACT--Active Mode
-+	4: LPS--Low Power State
-+	5: SUS--Suspend
-+
-+	The transision from different states are defined below
-+	TRANS_CARDEMU_TO_ACT
-+	TRANS_ACT_TO_CARDEMU
-+	TRANS_CARDEMU_TO_SUS
-+	TRANS_SUS_TO_CARDEMU
-+	TRANS_CARDEMU_TO_PDN
-+	TRANS_ACT_TO_LPS
-+	TRANS_LPS_TO_ACT
-+
-+	TRANS_END
-+*/
-+#define	RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS	18
-+#define	RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS	18
-+#define	RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS	18
-+#define	RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS	18
-+#define	RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS	18
-+#define	RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS	18
-+#define	RTL8192E_TRANS_ACT_TO_LPS_STEPS	23
-+#define	RTL8192E_TRANS_LPS_TO_ACT_STEPS	23
-+#define	RTL8192E_TRANS_END_STEPS	1
-+
-+
-+#define RTL8192E_TRANS_CARDEMU_TO_ACT														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
-+
-+
-+#define RTL8192E_TRANS_ACT_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
-+	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
-+
-+
-+#define RTL8192E_TRANS_CARDEMU_TO_SUS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8192E_TRANS_SUS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
-+
-+#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
-+	{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*Unlock small LDO Register*/	\
-+	{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*Disable small LDO*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8192E_TRANS_CARDDIS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*Enable small LDO*/	\
-+	{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*Lock small LDO Register*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
-+
-+
-+#define RTL8192E_TRANS_CARDEMU_TO_PDN												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
-+
-+#define RTL8192E_TRANS_PDN_TO_CARDEMU												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
-+
-+#define RTL8192E_TRANS_ACT_TO_LPS														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
-+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
-+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
-+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
-+
-+
-+#define RTL8192E_TRANS_LPS_TO_ACT															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM, For Repeatly In and out, Taggle bit should be changed*/\
-+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
-+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/\
-+	{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*Clear ISR*/
-+
-+#define RTL8192E_TRANS_END															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
-+
-+
-+	extern WLAN_PWR_CFG rtl8192E_power_on_flow[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8192E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8192E_radio_off_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8192E_card_disable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8192E_card_enable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8192E_suspend_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8192E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8192E_resume_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8192E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8192E_hwpdn_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8192E_enter_lps_flow[RTL8192E_TRANS_ACT_TO_LPS_STEPS + RTL8192E_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8192E_leave_lps_flow[RTL8192E_TRANS_LPS_TO_ACT_STEPS + RTL8192E_TRANS_END_STEPS];
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8192FPhyCfg.h b/drivers/staging/rtl8723cs/include/Hal8192FPhyCfg.h
-new file mode 100644
-index 000000000000..dd9fdcc09159
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8192FPhyCfg.h
-@@ -0,0 +1,115 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8192FPHYCFG_H__
-+#define __INC_HAL8192FPHYCFG_H__
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+#define LOOP_LIMIT				5
-+#define MAX_STALL_TIME			50		/* us */
-+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
-+#define MAX_TXPWR_IDX_NMODE_92S	63
-+#define Reset_Cnt_Limit			3
-+
-+#ifdef CONFIG_PCI_HCI
-+	#define MAX_AGGR_NUM	0x0B
-+#else
-+	#define MAX_AGGR_NUM	0x07
-+#endif /* CONFIG_PCI_HCI */
-+
-+
-+/*--------------------------Define Parameters End-------------------------------*/
-+
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+/*------------------------------Define structure End----------------------------*/
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+u32
-+PHY_QueryBBReg_8192F(
-+		PADAPTER	Adapter,
-+		u32		RegAddr,
-+		u32		BitMask
-+);
-+
-+void
-+PHY_SetBBReg_8192F(
-+		PADAPTER	Adapter,
-+		u32		RegAddr,
-+		u32		BitMask,
-+		u32		Data
-+);
-+
-+u32
-+PHY_QueryRFReg_8192F(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				RegAddr,
-+		u32				BitMask
-+);
-+
-+void
-+PHY_SetRFReg_8192F(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				RegAddr,
-+		u32				BitMask,
-+		u32				Data
-+);
-+
-+/* MAC/BB/RF HAL config */
-+int PHY_BBConfig8192F(PADAPTER	Adapter	);
-+
-+int PHY_RFConfig8192F(PADAPTER	Adapter);
-+
-+s32 PHY_MACConfig8192F(PADAPTER padapter);
-+
-+int
-+PHY_ConfigRFWithParaFile_8192F(
-+		PADAPTER			Adapter,
-+		u8				*pFileName,
-+	enum rf_path				eRFPath
-+);
-+
-+void
-+PHY_SetTxPowerIndex_8192F(
-+		PADAPTER			Adapter,
-+		u32					PowerIndex,
-+		enum rf_path			RFPath,
-+		u8					Rate
-+);
-+
-+void
-+PHY_SetTxPowerLevel8192F(
-+		PADAPTER		Adapter,
-+		u8			channel
-+);
-+
-+void
-+PHY_SetSwChnlBWMode8192F(
-+		PADAPTER			Adapter,
-+		u8					channel,
-+		enum channel_width	Bandwidth,
-+		u8					Offset40,
-+		u8					Offset80
-+);
-+
-+void phy_set_rf_path_switch_8192f(
-+		PADAPTER	pAdapter,
-+		bool		bMain
-+);
-+/*--------------------------Exported Function prototype End---------------------*/
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8192FPhyReg.h b/drivers/staging/rtl8723cs/include/Hal8192FPhyReg.h
-new file mode 100644
-index 000000000000..b82f7f98696d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8192FPhyReg.h
-@@ -0,0 +1,1134 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8192FPHYREG_H__
-+#define __INC_HAL8192FPHYREG_H__
-+
-+#define		rSYM_WLBT_PAPE_SEL		0x64
-+/*
-+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
-+ * 3. RF register 0x00-2E
-+ * 4. Bit Mask for BB/RF register
-+ * 5. Other definition for BB/RF R/W
-+ *   */
-+
-+
-+/*
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 1. Page1(0x100)
-+ *   */
-+#define		rPMAC_Reset					0x100
-+#define		rPMAC_TxStart					0x104
-+#define		rPMAC_TxLegacySIG				0x108
-+#define		rPMAC_TxHTSIG1				0x10c
-+#define		rPMAC_TxHTSIG2				0x110
-+#define		rPMAC_PHYDebug				0x114
-+#define		rPMAC_TxPacketNum				0x118
-+#define		rPMAC_TxIdle					0x11c
-+#define		rPMAC_TxMACHeader0			0x120
-+#define		rPMAC_TxMACHeader1			0x124
-+#define		rPMAC_TxMACHeader2			0x128
-+#define		rPMAC_TxMACHeader3			0x12c
-+#define		rPMAC_TxMACHeader4			0x130
-+#define		rPMAC_TxMACHeader5			0x134
-+#define		rPMAC_TxDataType				0x138
-+#define		rPMAC_TxRandomSeed			0x13c
-+#define		rPMAC_CCKPLCPPreamble			0x140
-+#define		rPMAC_CCKPLCPHeader			0x144
-+#define		rPMAC_CCKCRC16				0x148
-+#define		rPMAC_OFDMRxCRC32OK			0x170
-+#define		rPMAC_OFDMRxCRC32Er			0x174
-+#define		rPMAC_OFDMRxParityEr			0x178
-+#define		rPMAC_OFDMRxCRC8Er			0x17c
-+#define		rPMAC_CCKCRxRC16Er			0x180
-+#define		rPMAC_CCKCRxRC32Er			0x184
-+#define		rPMAC_CCKCRxRC32OK			0x188
-+#define		rPMAC_TxStatus					0x18c
-+
-+/*
-+ * 2. Page2(0x200)
-+ *
-+ * The following two definition are only used for USB interface. */
-+#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
-+#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
-+
-+/*
-+ * 3. Page8(0x800)
-+ *   */
-+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC // RF BW Setting?? */
-+
-+#define		rFPGA0_TxInfo				0x804	/* Status report?? */
-+#define		rFPGA0_PSDFunction			0x808
-+
-+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
-+
-+#define		rFPGA0_RFTiming1			0x810	/* Useless now */
-+#define		rFPGA0_RFTiming2			0x814
-+
-+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
-+#define		rFPGA0_XA_HSSIParameter2		0x824
-+#define		rFPGA0_XB_HSSIParameter1		0x828
-+#define		rFPGA0_XB_HSSIParameter2		0x82c
-+#define		rTxAGC_B_Rate18_06				0x830
-+#define		rTxAGC_B_Rate54_24				0x834
-+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
-+#define		rTxAGC_B_Mcs03_Mcs00			0x83c
-+
-+#define		rTxAGC_B_Mcs07_Mcs04			0x848
-+#define		rTxAGC_B_Mcs11_Mcs08			0x84c
-+
-+#define		rFPGA0_XA_LSSIParameter		0x840
-+#define		rFPGA0_XB_LSSIParameter		0x844
-+
-+#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
-+#define		rFPGA0_RFSleepUpParameter		0x854
-+
-+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
-+#define		rFPGA0_XCD_SwitchControl		0x85c
-+
-+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
-+#define		rFPGA0_XB_RFInterfaceOE		0x864
-+
-+#define		rTxAGC_B_Mcs15_Mcs12			0x868
-+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
-+
-+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
-+#define		rFPGA0_XCD_RFInterfaceSW		0x874
-+
-+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
-+#define		rFPGA0_XCD_RFParameter		0x87c
-+
-+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
-+#define		rFPGA0_AnalogParameter2		0x884
-+#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
-+#define		rFPGA0_AnalogParameter4		0x88c
-+
-+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
-+#define		rFPGA0_XB_LSSIReadBack		0x8a4
-+#define		rFPGA0_XC_LSSIReadBack		0x8a8
-+#define		rFPGA0_XD_LSSIReadBack		0x8ac
-+
-+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
-+#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
-+#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
-+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now // RF Interface Readback Value */
-+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
-+
-+/*
-+ * 4. Page9(0x900)
-+ *   */
-+#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC // RF BW Setting?? */
-+#define	rFPGA1_TxBlock				0x904	/* Useless now */
-+#define	rFPGA1_DebugSelect			0x908	/* Useless now */
-+#define	rFPGA1_TxInfo				0x90c	/* Useless now // Status report?? */
-+#define	rDPDT_control				0x92c
-+#define	rfe_ctrl_anta_src				0x930
-+#define	rS0S1_PathSwitch			0x948
-+#define	rBBrx_DFIR					0x954
-+
-+/*
-+ * 5. PageA(0xA00)
-+ *
-+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
-+#define		rCCK0_System				0xa00
-+
-+#define		rCCK0_AFESetting			0xa04	/* Disable init gain now // Select RX path by RSSI */
-+#define		rCCK0_CCA					0xa08	/* Disable init gain now // Init gain */
-+
-+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
-+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
-+
-+#define		rCCK0_RxHP					0xa14
-+
-+#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
-+#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
-+
-+#define		rCCK0_TxFilter1				0xa20
-+#define		rCCK0_TxFilter2				0xa24
-+#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
-+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
-+#define		rCCK0_TRSSIReport		0xa50
-+#define		rCCK0_RxReport			0xa54  /* 0xa57 */
-+#define		rCCK0_FACounterLower		0xa5c  /* 0xa5b */
-+#define		rCCK0_FACounterUpper		0xa58  /* 0xa5c */
-+
-+/*
-+ * PageB(0xB00)
-+ *   */
-+#define rPdp_AntA						0xb00
-+#define rPdp_AntA_4						0xb04
-+#define rPdp_AntA_8						0xb08
-+#define rPdp_AntA_C						0xb0c
-+#define rPdp_AntA_10					0xb10
-+#define rPdp_AntA_14					0xb14
-+#define rPdp_AntA_18					0xb18
-+#define rPdp_AntA_1C					0xb1c
-+#define rPdp_AntA_20					0xb20
-+#define rPdp_AntA_24					0xb24
-+
-+#define rConfig_Pmpd_AntA				0xb28
-+#define rConfig_ram64x16				0xb2c
-+
-+#define rBndA							0xb30
-+#define rHssiPar						0xb34
-+
-+#define rConfig_AntA					0xb68
-+#define rConfig_AntB					0xb6c
-+
-+#define rPdp_AntB						0xb70
-+#define rPdp_AntB_4						0xb74
-+#define rPdp_AntB_8						0xb78
-+#define rPdp_AntB_C						0xb7c
-+#define rPdp_AntB_10					0xb80
-+#define rPdp_AntB_14					0xb84
-+#define rPdp_AntB_18					0xb88
-+#define rPdp_AntB_1C					0xb8c
-+#define rPdp_AntB_20					0xb90
-+#define rPdp_AntB_24					0xb94
-+
-+#define rConfig_Pmpd_AntB				0xb98
-+
-+#define rBndB							0xba0
-+
-+#define rAPK							0xbd8
-+#define rPm_Rx0_AntA					0xbdc
-+#define rPm_Rx1_AntA					0xbe0
-+#define rPm_Rx2_AntA					0xbe4
-+#define rPm_Rx3_AntA					0xbe8
-+#define rPm_Rx0_AntB					0xbec
-+#define rPm_Rx1_AntB					0xbf0
-+#define rPm_Rx2_AntB					0xbf4
-+#define rPm_Rx3_AntB					0xbf8
-+/*
-+ * 6. PageC(0xC00)
-+ *   */
-+#define		rOFDM0_LSTF				0xc00
-+
-+#define		rOFDM0_TRxPathEnable		0xc04
-+#define		rOFDM0_TRMuxPar			0xc08
-+#define		rOFDM0_TRSWIsolation		0xc0c
-+
-+#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
-+#define		rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imbalance matrix */
-+#define		rOFDM0_XBRxAFE		0xc18
-+#define		rOFDM0_XBRxIQImbalance	0xc1c
-+#define		rOFDM0_XCRxAFE		0xc20
-+#define		rOFDM0_XCRxIQImbalance	0xc24
-+#define		rOFDM0_XDRxAFE		0xc28
-+#define		rOFDM0_XDRxIQImbalance	0xc2c
-+
-+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	// DM tune init gain */
-+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
-+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
-+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
-+
-+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
-+#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
-+#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
-+#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
-+
-+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
-+#define		rOFDM0_XAAGCCore2			0xc54
-+#define		rOFDM0_XBAGCCore1			0xc58
-+#define		rOFDM0_XBAGCCore2			0xc5c
-+#define		rOFDM0_XCAGCCore1			0xc60
-+#define		rOFDM0_XCAGCCore2			0xc64
-+#define		rOFDM0_XDAGCCore1			0xc68
-+#define		rOFDM0_XDAGCCore2			0xc6c
-+
-+#define		rOFDM0_AGCParameter1			0xc70
-+#define		rOFDM0_AGCParameter2			0xc74
-+#define		rOFDM0_AGCRSSITable			0xc78
-+#define		rOFDM0_HTSTFAGC				0xc7c
-+
-+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
-+#define		rOFDM0_XATxAFE				0xc84
-+#define		rOFDM0_XBTxIQImbalance		0xc88
-+#define		rOFDM0_XBTxAFE				0xc8c
-+#define		rOFDM0_XCTxIQImbalance		0xc90
-+#define		rOFDM0_XCTxAFE			0xc94
-+#define		rOFDM0_XDTxIQImbalance		0xc98
-+#define		rOFDM0_XDTxAFE				0xc9c
-+
-+#define		rOFDM0_RxIQExtAnta			0xca0
-+#define		rOFDM0_TxCoeff1				0xca4
-+#define		rOFDM0_TxCoeff2				0xca8
-+#define		rOFDM0_TxCoeff3				0xcac
-+#define		rOFDM0_TxCoeff4				0xcb0
-+#define		rOFDM0_TxCoeff5				0xcb4
-+#define		rOFDM0_TxCoeff6				0xcb8
-+#define		rOFDM0_RxHPParameter			0xce0
-+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
-+#define		rOFDM0_FrameSync				0xcf0
-+#define		rOFDM0_DFSReport				0xcf4
-+
-+/*
-+ * 7. PageD(0xD00)
-+ *   */
-+#define		rOFDM1_LSTF					0xd00
-+#define		rOFDM1_TRxPathEnable			0xd04
-+
-+#define		rOFDM1_CFO						0xd08	/* No setting now */
-+#define		rOFDM1_CSI1					0xd10
-+#define		rOFDM1_SBD						0xd14
-+#define		rOFDM1_CSI2					0xd18
-+#define		rOFDM1_CFOTracking			0xd2c
-+#define		rOFDM1_TRxMesaure1			0xd34
-+#define		rOFDM1_IntfDet					0xd3c
-+#define		rOFDM1_PseudoNoiseStateAB		0xd50
-+#define		rOFDM1_PseudoNoiseStateCD		0xd54
-+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
-+
-+#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
-+#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
-+#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
-+
-+#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
-+#define		rOFDM_ShortCFOCD				0xdb0
-+#define		rOFDM_LongCFOAB				0xdb4
-+#define		rOFDM_LongCFOCD				0xdb8
-+#define		rOFDM_TailCFOAB				0xdbc
-+#define		rOFDM_TailCFOCD				0xdc0
-+#define		rOFDM_PWMeasure1		0xdc4
-+#define		rOFDM_PWMeasure2		0xdc8
-+#define		rOFDM_BWReport				0xdcc
-+#define		rOFDM_AGCReport				0xdd0
-+#define		rOFDM_RxSNR					0xdd4
-+#define		rOFDM_RxEVMCSI				0xdd8
-+#define		rOFDM_SIGReport				0xddc
-+
-+
-+/*
-+ * 8. PageE(0xE00)
-+ *   */
-+#define		rTxAGC_A_Rate18_06			0xe00
-+#define		rTxAGC_A_Rate54_24			0xe04
-+#define		rTxAGC_A_CCK1_Mcs32			0xe08
-+#define		rTxAGC_A_Mcs03_Mcs00			0xe10
-+#define		rTxAGC_A_Mcs07_Mcs04			0xe14
-+#define		rTxAGC_A_Mcs11_Mcs08			0xe18
-+#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
-+
-+#define		rFPGA0_IQK					0xe28
-+#define		rTx_IQK_Tone_A				0xe30
-+#define		rRx_IQK_Tone_A				0xe34
-+#define		rTx_IQK_PI_A					0xe38
-+#define		rRx_IQK_PI_A					0xe3c
-+
-+#define		rTx_IQK						0xe40
-+#define		rRx_IQK						0xe44
-+#define		rIQK_AGC_Pts					0xe48
-+#define		rIQK_AGC_Rsp					0xe4c
-+#define		rTx_IQK_Tone_B				0xe50
-+#define		rRx_IQK_Tone_B				0xe54
-+#define		rTx_IQK_PI_B					0xe58
-+#define		rRx_IQK_PI_B					0xe5c
-+#define		rIQK_AGC_Cont				0xe60
-+
-+#define		rBlue_Tooth					0xe6c
-+#define		rRx_Wait_CCA					0xe70
-+#define		rTx_CCK_RFON					0xe74
-+#define		rTx_CCK_BBON				0xe78
-+#define		rTx_OFDM_RFON				0xe7c
-+#define		rTx_OFDM_BBON				0xe80
-+#define		rTx_To_Rx					0xe84
-+#define		rTx_To_Tx					0xe88
-+#define		rRx_CCK						0xe8c
-+
-+#define		rTx_Power_Before_IQK_A		0xe94
-+#define		rTx_Power_After_IQK_A			0xe9c
-+
-+#define		rRx_Power_Before_IQK_A		0xea0
-+#define		rRx_Power_Before_IQK_A_2		0xea4
-+#define		rRx_Power_After_IQK_A			0xea8
-+#define		rRx_Power_After_IQK_A_2		0xeac
-+
-+#define		rTx_Power_Before_IQK_B		0xeb4
-+#define		rTx_Power_After_IQK_B			0xebc
-+
-+#define		rRx_Power_Before_IQK_B		0xec0
-+#define		rRx_Power_Before_IQK_B_2		0xec4
-+#define		rRx_Power_After_IQK_B			0xec8
-+#define		rRx_Power_After_IQK_B_2		0xecc
-+
-+#define		rRx_OFDM					0xed0
-+#define		rRx_Wait_RIFS				0xed4
-+#define		rRx_TO_Rx					0xed8
-+#define		rStandby						0xedc
-+#define		rSleep						0xee0
-+#define		rPMPD_ANAEN				0xeec
-+
-+/*
-+ * 7. RF Register 0x00-0x2E (RF 8256)
-+ * RF-0222D 0x00-3F
-+ *
-+ * Zebra1 */
-+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
-+#define		rZebra1_TRxEnable1				0x1
-+#define		rZebra1_TRxEnable2				0x2
-+#define		rZebra1_AGC					0x4
-+#define		rZebra1_ChargePump			0x5
-+#define		rZebra1_Channel				0x7	/* RF channel switch */
-+
-+/* #endif */
-+#define		rZebra1_TxGain					0x8	/* Useless now */
-+#define		rZebra1_TxLPF					0x9
-+#define		rZebra1_RxLPF					0xb
-+#define		rZebra1_RxHPFCorner			0xc
-+
-+/* Zebra4 */
-+#define		rGlobalCtrl						0	/* Useless now */
-+#define		rRTL8256_TxLPF					19
-+#define		rRTL8256_RxLPF					11
-+
-+/* RTL8258 */
-+#define		rRTL8258_TxLPF					0x11	/* Useless now */
-+#define		rRTL8258_RxLPF					0x13
-+#define		rRTL8258_RSSILPF				0xa
-+
-+/*
-+ * RL6052 Register definition
-+ *   */
-+#define		RF_AC						0x00	/* */
-+
-+#define		RF_IQADJ_G1				0x01	/* */
-+#define		RF_IQADJ_G2				0x02	/* */
-+#define		RF_BS_PA_APSET_G1_G4		0x03
-+#define		RF_BS_PA_APSET_G5_G8		0x04
-+#define		RF_POW_TRSW				0x05	/* */
-+
-+#define		RF_GAIN_RX					0x06	/* */
-+#define		RF_GAIN_TX					0x07	/* */
-+
-+#define		RF_TXM_IDAC				0x08	/* */
-+#define		RF_IPA_G					0x09	/* */
-+#define		RF_TXBIAS_G				0x0A
-+#define		RF_TXPA_AG					0x0B
-+#define		RF_IPA_A					0x0C	/* */
-+#define		RF_TXBIAS_A				0x0D
-+#define		RF_BS_PA_APSET_G9_G11	0x0E
-+#define		RF_BS_IQGEN				0x0F	/* */
-+
-+#define		RF_MODE1					0x10	/* */
-+#define		RF_MODE2					0x11	/* */
-+
-+#define		RF_RX_AGC_HP				0x12	/* */
-+#define		RF_TX_AGC					0x13	/* */
-+#define		RF_BIAS						0x14	/* */
-+#define		RF_IPA						0x15	/* */
-+#define		RF_TXBIAS					0x16
-+#define		RF_POW_ABILITY			0x17	/* */
-+#define		RF_MODE_AG				0x18	/* */
-+#define		rRfChannel					0x18	/* RF channel and BW switch */
-+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
-+#define		RF_TOP						0x19	/* */
-+
-+#define		RF_RX_G1					0x1A	/* */
-+#define		RF_RX_G2					0x1B	/* */
-+
-+#define		RF_RX_BB2					0x1C	/* */
-+#define		RF_RX_BB1					0x1D	/* */
-+
-+#define		RF_RCK1					0x1E	/* */
-+#define		RF_RCK2					0x1F	/* */
-+
-+#define		RF_TX_G1					0x20	/* */
-+#define		RF_TX_G2					0x21	/* */
-+#define		RF_TX_G3					0x22	/* */
-+
-+#define		RF_TX_BB1					0x23	/* */
-+
-+#define		RF_T_METER					0x24	/* */
-+
-+#define		RF_SYN_G1					0x25	/* RF TX Power control */
-+#define		RF_SYN_G2					0x26	/* RF TX Power control */
-+#define		RF_SYN_G3					0x27	/* RF TX Power control */
-+#define		RF_SYN_G4					0x28	/* RF TX Power control */
-+#define		RF_SYN_G5					0x29	/* RF TX Power control */
-+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
-+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
-+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
-+
-+#define		RF_RCK_OS					0x30	/* RF TX PA control */
-+
-+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
-+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
-+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
-+#define	RF_TX_BIAS_A				0x35
-+#define	RF_TX_BIAS_D				0x36
-+#define	RF_LOBF_9					0x38
-+#define	RF_RXRF_A3					0x3C	/*	 */
-+#define	RF_TRSW					0x3F
-+
-+#define	RF_TXRF_A2					0x41
-+#define	RF_T_METER_88E				0x42
-+#define	RF_TXPA_G4					0x46
-+#define	RF_TXPA_A4					0x4B
-+#define	RF_0x52					0x52
-+#define	RF_WE_LUT					0xEF
-+#define	RF_S0S1					0xB0
-+
-+/*
-+ * Bit Mask
-+ *
-+ * 1. Page1(0x100) */
-+#define		bBBResetB						0x100	/* Useless now? */
-+#define		bGlobalResetB					0x200
-+#define		bOFDMTxStart					0x4
-+#define		bCCKTxStart						0x8
-+#define		bCRC32Debug					0x100
-+#define		bPMACLoopback					0x10
-+#define		bTxLSIG							0xffffff
-+#define		bOFDMTxRate					0xf
-+#define		bOFDMTxReserved				0x10
-+#define		bOFDMTxLength					0x1ffe0
-+#define		bOFDMTxParity					0x20000
-+#define		bTxHTSIG1						0xffffff
-+#define		bTxHTMCSRate					0x7f
-+#define		bTxHTBW						0x80
-+#define		bTxHTLength					0xffff00
-+#define		bTxHTSIG2						0xffffff
-+#define		bTxHTSmoothing					0x1
-+#define		bTxHTSounding					0x2
-+#define		bTxHTReserved					0x4
-+#define		bTxHTAggreation				0x8
-+#define		bTxHTSTBC						0x30
-+#define		bTxHTAdvanceCoding			0x40
-+#define		bTxHTShortGI					0x80
-+#define		bTxHTNumberHT_LTF			0x300
-+#define		bTxHTCRC8						0x3fc00
-+#define		bCounterReset					0x10000
-+#define		bNumOfOFDMTx					0xffff
-+#define		bNumOfCCKTx					0xffff0000
-+#define		bTxIdleInterval					0xffff
-+#define		bOFDMService					0xffff0000
-+#define		bTxMACHeader					0xffffffff
-+#define		bTxDataInit						0xff
-+#define		bTxHTMode						0x100
-+#define		bTxDataType					0x30000
-+#define		bTxRandomSeed					0xffffffff
-+#define		bCCKTxPreamble					0x1
-+#define		bCCKTxSFD						0xffff0000
-+#define		bCCKTxSIG						0xff
-+#define		bCCKTxService					0xff00
-+#define		bCCKLengthExt					0x8000
-+#define		bCCKTxLength					0xffff0000
-+#define		bCCKTxCRC16					0xffff
-+#define		bCCKTxStatus					0x1
-+#define		bOFDMTxStatus					0x2
-+
-+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
-+#define		RF_TX_GAIN_OFFSET_8192F(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0))
-+
-+/* 2. Page8(0x800) */
-+#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
-+#define		bJapanMode						0x2
-+#define		bCCKTxSC						0x30
-+#define		bCCKEn							0x1000000
-+#define		bOFDMEn						0x2000000
-+
-+#define		bOFDMRxADCPhase           0x10000	/* Useless now */
-+#define		bOFDMTxDACPhase		0x40000
-+#define		bXATxAGC			0x3f
-+
-+#define		bAntennaSelect		0x0300
-+
-+#define		bXBTxAGC                 0xf00	/* Reg 80c rFPGA0_TxGainStage */
-+#define		bXCTxAGC			0xf000
-+#define		bXDTxAGC			0xf0000
-+
-+#define		bPAStart                 0xf0000000	/* Useless now */
-+#define		bTRStart			0x00f00000
-+#define		bRFStart			0x0000f000
-+#define		bBBStart			0x000000f0
-+#define		bBBCCKStart		0x0000000f
-+#define		bPAEnd                    0xf          /* Reg0x814 */
-+#define		bTREnd			0x0f000000
-+#define		bRFEnd			0x000f0000
-+#define		bCCAMask                  0x000000f0   /* T2R */
-+#define		bR2RCCAMask		0x00000f00
-+#define		bHSSI_R2TDelay		0xf8000000
-+#define		bHSSI_T2RDelay		0xf80000
-+#define		bContTxHSSI              0x400     /* chane gain at continue Tx */
-+#define		bIGFromCCK		0x200
-+#define		bAGCAddress		0x3f
-+#define		bRxHPTx			0x7000
-+#define		bRxHPT2R			0x38000
-+#define		bRxHPCCKIni		0xc0000
-+#define		bAGCTxCode		0xc00000
-+#define		bAGCRxCode		0x300000
-+
-+#define		b3WireDataLength         0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
-+#define		b3WireAddressLength		0x400
-+
-+#define		b3WireRFPowerDown         0x1	/* Useless now
-+ * #define bHWSISelect		0x8 */
-+#define		b5GPAPEPolarity		0x40000000
-+#define		b2GPAPEPolarity		0x80000000
-+#define		bRFSW_TxDefaultAnt		0x3
-+#define		bRFSW_TxOptionAnt		0x30
-+#define		bRFSW_RxDefaultAnt		0x300
-+#define		bRFSW_RxOptionAnt		0x3000
-+#define		bRFSI_3WireData		0x1
-+#define		bRFSI_3WireClock		0x2
-+#define		bRFSI_3WireLoad		0x4
-+#define		bRFSI_3WireRW		0x8
-+#define		bRFSI_3Wire			0xf
-+
-+#define		bRFSI_RFENV              0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
-+
-+#define		bRFSI_TRSW               0x20	/* Useless now */
-+#define		bRFSI_TRSWB		0x40
-+#define		bRFSI_ANTSW		0x100
-+#define		bRFSI_ANTSWB		0x200
-+#define		bRFSI_PAPE			0x400
-+#define		bRFSI_PAPE5G		0x800
-+#define		bBandSelect			0x1
-+#define		bHTSIG2_GI			0x80
-+#define		bHTSIG2_Smoothing		0x01
-+#define		bHTSIG2_Sounding		0x02
-+#define		bHTSIG2_Aggreaton		0x08
-+#define		bHTSIG2_STBC		0x30
-+#define		bHTSIG2_AdvCoding		0x40
-+#define		bHTSIG2_NumOfHTLTF	0x300
-+#define		bHTSIG2_CRC8		0x3fc
-+#define		bHTSIG1_MCS		0x7f
-+#define		bHTSIG1_BandWidth		0x80
-+#define		bHTSIG1_HTLength		0xffff
-+#define		bLSIG_Rate			0xf
-+#define		bLSIG_Reserved		0x10
-+#define		bLSIG_Length		0x1fffe
-+#define		bLSIG_Parity			0x20
-+#define		bCCKRxPhase		0x4
-+
-+#define		bLSSIReadAddress          0x7f800000   /* T65 RF */
-+
-+#define		bLSSIReadEdge             0x80000000   /* LSSI "Read" edge signal */
-+
-+#define		bLSSIReadBackData         0xfffff		/* T65 RF */
-+
-+#define		bLSSIReadOKFlag           0x1000	/* Useless now */
-+#define		bCCKSampleRate            0x8       /* 0: 44MHz, 1:88MHz     */
-+#define		bRegulator0Standby		0x1
-+#define		bRegulatorPLLStandby		0x2
-+#define		bRegulator1Standby		0x4
-+#define		bPLLPowerUp		0x8
-+#define		bDPLLPowerUp		0x10
-+#define		bDA10PowerUp		0x20
-+#define		bAD7PowerUp		0x200
-+#define		bDA6PowerUp		0x2000
-+#define		bXtalPowerUp		0x4000
-+#define		b40MDClkPowerUP		0x8000
-+#define		bDA6DebugMode		0x20000
-+#define		bDA6Swing			0x380000
-+
-+#define		bADClkPhase               0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
-+
-+#define		b80MClkDelay              0x18000000	/* Useless */
-+#define		bAFEWatchDogEnable		0x20000000
-+
-+#define		bXtalCap01                0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
-+#define		bXtalCap23			0x3
-+#define		bXtalCap92x					0x0f000000
-+#define		bXtalCap			0x0f000000
-+
-+#define		bIntDifClkEnable          0x400	/* Useless */
-+#define		bExtSigClkEnable		0x800
-+#define		bBandgapMbiasPowerUp	0x10000
-+#define		bAD11SHGain		0xc0000
-+#define		bAD11InputRange		0x700000
-+#define		bAD11OPCurrent		0x3800000
-+#define		bIPathLoopback		0x4000000
-+#define		bQPathLoopback		0x8000000
-+#define		bAFELoopback		0x10000000
-+#define		bDA10Swing		0x7e0
-+#define		bDA10Reverse		0x800
-+#define		bDAClkSource		0x1000
-+#define		bAD7InputRange		0x6000
-+#define		bAD7Gain			0x38000
-+#define		bAD7OutputCMMode		0x40000
-+#define		bAD7InputCMMode		0x380000
-+#define		bAD7Current			0xc00000
-+#define		bRegulatorAdjust		0x7000000
-+#define		bAD11PowerUpAtTx		0x1
-+#define		bDA10PSAtTx		0x10
-+#define		bAD11PowerUpAtRx		0x100
-+#define		bDA10PSAtRx		0x1000
-+#define		bCCKRxAGCFormat		0x200
-+#define		bPSDFFTSamplepPoint		0xc000
-+#define		bPSDAverageNum		0x3000
-+#define		bIQPathControl		0xc00
-+#define		bPSDFreq			0x3ff
-+#define		bPSDAntennaPath		0x30
-+#define		bPSDIQSwitch		0x40
-+#define		bPSDRxTrigger		0x400000
-+#define		bPSDTxTrigger		0x80000000
-+#define		bPSDSineToneScale		0x7f000000
-+#define		bPSDReport			0xffff
-+
-+/* 3. Page9(0x900) */
-+#define		bOFDMTxSC                 0x30000000	/* Useless */
-+#define		bCCKTxOn			0x1
-+#define		bOFDMTxOn		0x2
-+#define		bDebugPage                0xfff  /* reset debug page and also HWord, LWord */
-+#define		bDebugItem                0xff   /* reset debug page and LWord */
-+#define		bAntL			0x10
-+#define		bAntNonHT				0x100
-+#define		bAntHT1			0x1000
-+#define		bAntHT2			0x10000
-+#define		bAntHT1S1			0x100000
-+#define		bAntNonHTS1		0x1000000
-+
-+/* 4. PageA(0xA00) */
-+#define		bCCKBBMode				0x3	/* Useless */
-+#define		bCCKTxPowerSaving		0x80
-+#define		bCCKRxPowerSaving		0x40
-+
-+#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
-+
-+#define		bCCKScramble			0x8	/* Useless */
-+#define		bCCKAntDiversity		0x8000
-+#define		bCCKCarrierRecovery		0x4000
-+#define		bCCKTxRate				0x3000
-+#define		bCCKDCCancel			0x0800
-+#define		bCCKISICancel			0x0400
-+#define		bCCKMatchFilter			0x0200
-+#define		bCCKEqualizer			0x0100
-+#define		bCCKPreambleDetect		0x800000
-+#define		bCCKFastFalseCCA		0x400000
-+#define		bCCKChEstStart			0x300000
-+#define		bCCKCCACount			0x080000
-+#define		bCCKcs_lim				0x070000
-+#define		bCCKBistMode			0x80000000
-+#define		bCCKCCAMask			0x40000000
-+#define		bCCKTxDACPhase		0x4
-+#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
-+#define		bCCKr_cp_mode0		0x0100
-+#define		bCCKTxDCOffset			0xf0
-+#define		bCCKRxDCOffset			0xf
-+#define		bCCKCCAMode			0xc000
-+#define		bCCKFalseCS_lim			0x3f00
-+#define		bCCKCS_ratio			0xc00000
-+#define		bCCKCorgBit_sel			0x300000
-+#define		bCCKPD_lim				0x0f0000
-+#define		bCCKNewCCA			0x80000000
-+#define		bCCKRxHPofIG			0x8000
-+#define		bCCKRxIG				0x7f00
-+#define		bCCKLNAPolarity			0x800000
-+#define		bCCKRx1stGain			0x7f0000
-+#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
-+#define		bCCKRxAGCSatLevel		0x1f000000
-+#define		bCCKRxAGCSatCount		0xe0
-+#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
-+#define		bCCKFixedRxAGC			0x8000
-+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
-+#define		bCCKAntennaPolarity		0x2000
-+#define		bCCKTxFilterType		0x0c00
-+#define		bCCKRxAGCReportType	0x0300
-+#define		bCCKRxDAGCEn			0x80000000
-+#define		bCCKRxDAGCPeriod		0x20000000
-+#define		bCCKRxDAGCSatLevel		0x1f000000
-+#define		bCCKTimingRecovery		0x800000
-+#define		bCCKTxC0				0x3f0000
-+#define		bCCKTxC1				0x3f000000
-+#define		bCCKTxC2				0x3f
-+#define		bCCKTxC3				0x3f00
-+#define		bCCKTxC4				0x3f0000
-+#define		bCCKTxC5				0x3f000000
-+#define		bCCKTxC6				0x3f
-+#define		bCCKTxC7				0x3f00
-+#define		bCCKDebugPort			0xff0000
-+#define		bCCKDACDebug			0x0f000000
-+#define		bCCKFalseAlarmEnable	0x8000
-+#define		bCCKFalseAlarmRead		0x4000
-+#define		bCCKTRSSI				0x7f
-+#define		bCCKRxAGCReport		0xfe
-+#define		bCCKRxReport_AntSel	0x80000000
-+#define		bCCKRxReport_MFOff		0x40000000
-+#define		bCCKRxRxReport_SQLoss	0x20000000
-+#define		bCCKRxReport_Pktloss	0x10000000
-+#define		bCCKRxReport_Lockedbit	0x08000000
-+#define		bCCKRxReport_RateError	0x04000000
-+#define		bCCKRxReport_RxRate	0x03000000
-+#define		bCCKRxFACounterLower	0xff
-+#define		bCCKRxFACounterUpper	0xff000000
-+#define		bCCKRxHPAGCStart		0xe000
-+#define		bCCKRxHPAGCFinal		0x1c00
-+#define		bCCKRxFalseAlarmEnable	0x8000
-+#define		bCCKFACounterFreeze	0x4000
-+#define		bCCKTxPathSel			0x10000000
-+#define		bCCKDefaultRxPath		0xc000000
-+#define		bCCKOptionRxPath		0x3000000
-+
-+/* 5. PageC(0xC00) */
-+#define		bNumOfSTF				0x3	/* Useless */
-+#define		bShift_L					0xc0
-+#define		bGI_TH					0xc
-+#define		bRxPathA				0x1
-+#define		bRxPathB				0x2
-+#define		bRxPathC				0x4
-+#define		bRxPathD				0x8
-+#define		bTxPathA				0x1
-+#define		bTxPathB				0x2
-+#define		bTxPathC				0x4
-+#define		bTxPathD				0x8
-+#define		bTRSSIFreq				0x200
-+#define		bADCBackoff				0x3000
-+#define		bDFIRBackoff			0xc000
-+#define		bTRSSILatchPhase		0x10000
-+#define		bRxIDCOffset			0xff
-+#define		bRxQDCOffset			0xff00
-+#define		bRxDFIRMode			0x1800000
-+#define		bRxDCNFType			0xe000000
-+#define		bRXIQImb_A				0x3ff
-+#define		bRXIQImb_B				0xfc00
-+#define		bRXIQImb_C				0x3f0000
-+#define		bRXIQImb_D				0xffc00000
-+#define		bDC_dc_Notch			0x60000
-+#define		bRxNBINotch			0x1f000000
-+#define		bPD_TH					0xf
-+#define		bPD_TH_Opt2			0xc000
-+#define		bPWED_TH				0x700
-+#define		bIfMF_Win_L			0x800
-+#define		bPD_Option				0x1000
-+#define		bMF_Win_L				0xe000
-+#define		bBW_Search_L			0x30000
-+#define		bwin_enh_L				0xc0000
-+#define		bBW_TH					0x700000
-+#define		bED_TH2				0x3800000
-+#define		bBW_option				0x4000000
-+#define		bRatio_TH				0x18000000
-+#define		bWindow_L				0xe0000000
-+#define		bSBD_Option				0x1
-+#define		bFrame_TH				0x1c
-+#define		bFS_Option				0x60
-+#define		bDC_Slope_check		0x80
-+#define		bFGuard_Counter_DC_L	0xe00
-+#define		bFrame_Weight_Short	0x7000
-+#define		bSub_Tune				0xe00000
-+#define		bFrame_DC_Length		0xe000000
-+#define		bSBD_start_offset		0x30000000
-+#define		bFrame_TH_2			0x7
-+#define		bFrame_GI2_TH			0x38
-+#define		bGI2_Sync_en			0x40
-+#define		bSarch_Short_Early		0x300
-+#define		bSarch_Short_Late		0xc00
-+#define		bSarch_GI2_Late		0x70000
-+#define		bCFOAntSum				0x1
-+#define		bCFOAcc				0x2
-+#define		bCFOStartOffset			0xc
-+#define		bCFOLookBack			0x70
-+#define		bCFOSumWeight			0x80
-+#define		bDAGCEnable			0x10000
-+#define		bTXIQImb_A				0x3ff
-+#define		bTXIQImb_B				0xfc00
-+#define		bTXIQImb_C				0x3f0000
-+#define		bTXIQImb_D				0xffc00000
-+#define		bTxIDCOffset			0xff
-+#define		bTxQDCOffset			0xff00
-+#define		bTxDFIRMode			0x10000
-+#define		bTxPesudoNoiseOn		0x4000000
-+#define		bTxPesudoNoise_A		0xff
-+#define		bTxPesudoNoise_B		0xff00
-+#define		bTxPesudoNoise_C		0xff0000
-+#define		bTxPesudoNoise_D		0xff000000
-+#define		bCCADropOption			0x20000
-+#define		bCCADropThres			0xfff00000
-+#define		bEDCCA_H				0xf
-+#define		bEDCCA_L				0xf0
-+#define		bLambda_ED			0x300
-+#define		bRxInitialGain			0x7f
-+#define		bRxAntDivEn				0x80
-+#define		bRxAGCAddressForLNA	0x7f00
-+#define		bRxHighPowerFlow		0x8000
-+#define		bRxAGCFreezeThres		0xc0000
-+#define		bRxFreezeStep_AGC1	0x300000
-+#define		bRxFreezeStep_AGC2	0xc00000
-+#define		bRxFreezeStep_AGC3	0x3000000
-+#define		bRxFreezeStep_AGC0	0xc000000
-+#define		bRxRssi_Cmp_En			0x10000000
-+#define		bRxQuickAGCEn			0x20000000
-+#define		bRxAGCFreezeThresMode	0x40000000
-+#define		bRxOverFlowCheckType	0x80000000
-+#define		bRxAGCShift				0x7f
-+#define		bTRSW_Tri_Only			0x80
-+#define		bPowerThres			0x300
-+#define		bRxAGCEn				0x1
-+#define		bRxAGCTogetherEn		0x2
-+#define		bRxAGCMin				0x4
-+#define		bRxHP_Ini				0x7
-+#define		bRxHP_TRLNA			0x70
-+#define		bRxHP_RSSI				0x700
-+#define		bRxHP_BBP1				0x7000
-+#define		bRxHP_BBP2				0x70000
-+#define		bRxHP_BBP3				0x700000
-+#define		bRSSI_H					0x7f0000     /* the threshold for high power */
-+#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
-+#define		bRxSettle_TRSW			0x7
-+#define		bRxSettle_LNA			0x38
-+#define		bRxSettle_RSSI			0x1c0
-+#define		bRxSettle_BBP			0xe00
-+#define		bRxSettle_RxHP			0x7000
-+#define		bRxSettle_AntSW_RSSI	0x38000
-+#define		bRxSettle_AntSW		0xc0000
-+#define		bRxProcessTime_DAGC	0x300000
-+#define		bRxSettle_HSSI			0x400000
-+#define		bRxProcessTime_BBPPW	0x800000
-+#define		bRxAntennaPowerShift	0x3000000
-+#define		bRSSITableSelect		0xc000000
-+#define		bRxHP_Final				0x7000000
-+#define		bRxHTSettle_BBP			0x7
-+#define		bRxHTSettle_HSSI		0x8
-+#define		bRxHTSettle_RxHP		0x70
-+#define		bRxHTSettle_BBPPW		0x80
-+#define		bRxHTSettle_Idle		0x300
-+#define		bRxHTSettle_Reserved	0x1c00
-+#define		bRxHTRxHPEn			0x8000
-+#define		bRxHTAGCFreezeThres	0x30000
-+#define		bRxHTAGCTogetherEn	0x40000
-+#define		bRxHTAGCMin			0x80000
-+#define		bRxHTAGCEn				0x100000
-+#define		bRxHTDAGCEn			0x200000
-+#define		bRxHTRxHP_BBP			0x1c00000
-+#define		bRxHTRxHP_Final		0xe0000000
-+#define		bRxPWRatioTH			0x3
-+#define		bRxPWRatioEn			0x4
-+#define		bRxMFHold				0x3800
-+#define		bRxPD_Delay_TH1		0x38
-+#define		bRxPD_Delay_TH2		0x1c0
-+#define		bRxPD_DC_COUNT_MAX	0x600
-+/* #define bRxMF_Hold               0x3800 */
-+#define		bRxPD_Delay_TH			0x8000
-+#define		bRxProcess_Delay		0xf0000
-+#define		bRxSearchrange_GI2_Early	0x700000
-+#define		bRxFrame_Guard_Counter_L	0x3800000
-+#define		bRxSGI_Guard_L			0xc000000
-+#define		bRxSGI_Search_L		0x30000000
-+#define		bRxSGI_TH				0xc0000000
-+#define		bDFSCnt0				0xff
-+#define		bDFSCnt1				0xff00
-+#define		bDFSFlag				0xf0000
-+#define		bMFWeightSum			0x300000
-+#define		bMinIdxTH				0x7f000000
-+#define		bDAFormat				0x40000
-+#define		bTxChEmuEnable		0x01000000
-+#define		bTRSWIsolation_A		0x7f
-+#define		bTRSWIsolation_B		0x7f00
-+#define		bTRSWIsolation_C		0x7f0000
-+#define		bTRSWIsolation_D		0x7f000000
-+#define		bExtLNAGain				0x7c00
-+
-+/* 6. PageE(0xE00) */
-+#define		bSTBCEn				0x4	/* Useless */
-+#define		bAntennaMapping		0x10
-+#define		bNss					0x20
-+#define		bCFOAntSumD			0x200
-+#define		bPHYCounterReset		0x8000000
-+#define		bCFOReportGet			0x4000000
-+#define		bOFDMContinueTx		0x10000000
-+#define		bOFDMSingleCarrier		0x20000000
-+#define		bOFDMSingleTone		0x40000000
-+/* #define bRxPath1                 0x01 */
-+/* #define bRxPath2                 0x02 */
-+/* #define bRxPath3                 0x04 */
-+/* #define bRxPath4                 0x08 */
-+/* #define bTxPath1                 0x10 */
-+/* #define bTxPath2                 0x20 */
-+#define		bHTDetect			0x100
-+#define		bCFOEn				0x10000
-+#define		bCFOValue			0xfff00000
-+#define		bSigTone_Re		0x3f
-+#define		bSigTone_Im		0x7f00
-+#define		bCounter_CCA		0xffff
-+#define		bCounter_ParityFail	0xffff0000
-+#define		bCounter_RateIllegal		0xffff
-+#define		bCounter_CRC8Fail	0xffff0000
-+#define		bCounter_MCSNoSupport	0xffff
-+#define		bCounter_FastSync	0xffff
-+#define		bShortCFO			0xfff
-+#define		bShortCFOTLength	12   /* total */
-+#define		bShortCFOFLength	11   /* fraction */
-+#define		bLongCFO			0x7ff
-+#define		bLongCFOTLength	11
-+#define		bLongCFOFLength	11
-+#define		bTailCFO			0x1fff
-+#define		bTailCFOTLength		13
-+#define		bTailCFOFLength		12
-+#define		bmax_en_pwdB		0xffff
-+#define		bCC_power_dB		0xffff0000
-+#define		bnoise_pwdB		0xffff
-+#define		bPowerMeasTLength	10
-+#define		bPowerMeasFLength	3
-+#define		bRx_HT_BW			0x1
-+#define		bRxSC				0x6
-+#define		bRx_HT				0x8
-+#define		bNB_intf_det_on		0x1
-+#define		bIntf_win_len_cfg	0x30
-+#define		bNB_Intf_TH_cfg		0x1c0
-+#define		bRFGain				0x3f
-+#define		bTableSel			0x40
-+#define		bTRSW				0x80
-+#define		bRxSNR_A			0xff
-+#define		bRxSNR_B			0xff00
-+#define		bRxSNR_C			0xff0000
-+#define		bRxSNR_D			0xff000000
-+#define		bSNREVMTLength		8
-+#define		bSNREVMFLength		1
-+#define		bCSI1st				0xff
-+#define		bCSI2nd				0xff00
-+#define		bRxEVM1st			0xff0000
-+#define		bRxEVM2nd			0xff000000
-+#define		bSIGEVM			0xff
-+#define		bPWDB				0xff00
-+#define		bSGIEN				0x10000
-+
-+#define		bSFactorQAM1		0xf	/* Useless */
-+#define		bSFactorQAM2		0xf0
-+#define		bSFactorQAM3		0xf00
-+#define		bSFactorQAM4		0xf000
-+#define		bSFactorQAM5		0xf0000
-+#define		bSFactorQAM6		0xf0000
-+#define		bSFactorQAM7		0xf00000
-+#define		bSFactorQAM8		0xf000000
-+#define		bSFactorQAM9		0xf0000000
-+#define		bCSIScheme			0x100000
-+
-+#define		bNoiseLvlTopSet		0x3	/* Useless */
-+#define		bChSmooth			0x4
-+#define		bChSmoothCfg1		0x38
-+#define		bChSmoothCfg2		0x1c0
-+#define		bChSmoothCfg3		0xe00
-+#define		bChSmoothCfg4		0x7000
-+#define		bMRCMode			0x800000
-+#define		bTHEVMCfg			0x7000000
-+
-+#define		bLoopFitType		0x1	/* Useless */
-+#define		bUpdCFO			0x40
-+#define		bUpdCFOOffData		0x80
-+#define		bAdvUpdCFO			0x100
-+#define		bAdvTimeCtrl		0x800
-+#define		bUpdClko			0x1000
-+#define		bFC					0x6000
-+#define		bTrackingMode		0x8000
-+#define		bPhCmpEnable		0x10000
-+#define		bUpdClkoLTF		0x20000
-+#define		bComChCFO			0x40000
-+#define		bCSIEstiMode		0x80000
-+#define		bAdvUpdEqz			0x100000
-+#define		bUChCfg				0x7000000
-+#define		bUpdEqz			0x8000000
-+
-+/* Rx Pseduo noise */
-+#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
-+#define		bRxPesudoNoise_A		0xff
-+#define		bRxPesudoNoise_B		0xff00
-+#define		bRxPesudoNoise_C		0xff0000
-+#define		bRxPesudoNoise_D		0xff000000
-+#define		bPesudoNoiseState_A	0xffff
-+#define		bPesudoNoiseState_B	0xffff0000
-+#define		bPesudoNoiseState_C	0xffff
-+#define		bPesudoNoiseState_D	0xffff0000
-+
-+/* 7. RF Register
-+ * Zebra1 */
-+#define		bZebra1_HSSIEnable		0x8		/* Useless */
-+#define		bZebra1_TRxControl		0xc00
-+#define		bZebra1_TRxGainSetting	0x07f
-+#define		bZebra1_RxCorner		0xc00
-+#define		bZebra1_TxChargePump	0x38
-+#define		bZebra1_RxChargePump	0x7
-+#define		bZebra1_ChannelNum	0xf80
-+#define		bZebra1_TxLPFBW		0x400
-+#define		bZebra1_RxLPFBW		0x600
-+
-+/* Zebra4 */
-+#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
-+#define		bRTL8256RegModeCtrl0	0x40
-+#define		bRTL8256_TxLPFBW		0x18
-+#define		bRTL8256_RxLPFBW		0x600
-+
-+/* RTL8258 */
-+#define		bRTL8258_TxLPFBW		0xc	/* Useless */
-+#define		bRTL8258_RxLPFBW		0xc00
-+#define		bRTL8258_RSSILPFBW	0xc0
-+
-+
-+/*
-+ * Other Definition
-+ *   */
-+
-+/* byte endable for sb_write */
-+#define		bByte0				0x1	/* Useless */
-+#define		bByte1				0x2
-+#define		bByte2				0x4
-+#define		bByte3				0x8
-+#define		bWord0				0x3
-+#define		bWord1				0xc
-+#define		bDWord				0xf
-+
-+/* for PutRegsetting & GetRegSetting BitMask */
-+#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
-+#define		bMaskByte1			0xff00
-+#define		bMaskByte2			0xff0000
-+#define		bMaskByte3			0xff000000
-+#define		bMaskHWord		0xffff0000
-+#define		bMaskLWord			0x0000ffff
-+#define		bMaskDWord		0xffffffff
-+#define		bMaskH3Bytes		0xffffff00
-+#define		bMask12Bits			0xfff
-+#define		bMaskH4Bits			0xf0000000
-+#define		bMaskOFDM_D		0xffc00000
-+#define		bMaskCCK			0x3f3f3f3f
-+
-+
-+#define		bEnable			0x1	/* Useless */
-+#define		bDisable		0x0
-+
-+#define		LeftAntenna		0x0	/* Useless */
-+#define		RightAntenna	0x1
-+
-+#define		tCheckTxStatus		500   /* 500ms // Useless */
-+#define		tUpdateRxCounter	100   /* 100ms */
-+
-+#define		rateCCK		0	/* Useless */
-+#define		rateOFDM	1
-+#define		rateHT		2
-+
-+/* define Register-End */
-+#define		bPMAC_End			0x1ff	/* Useless */
-+#define		bFPGAPHY0_End		0x8ff
-+#define		bFPGAPHY1_End		0x9ff
-+#define		bCCKPHY0_End		0xaff
-+#define		bOFDMPHY0_End		0xcff
-+#define		bOFDMPHY1_End		0xdff
-+
-+/* define max debug item in each debug page
-+ * #define bMaxItem_FPGA_PHY0        0x9
-+ * #define bMaxItem_FPGA_PHY1        0x3
-+ * #define bMaxItem_PHY_11B          0x16
-+ * #define bMaxItem_OFDM_PHY0        0x29
-+ * #define bMaxItem_OFDM_PHY1        0x0 */
-+
-+#define		bPMACControl		0x0		/* Useless */
-+#define		bWMACControl		0x1
-+#define		bWNICControl		0x2
-+
-+#define		PathA			0x0	/* Useless */
-+#define		PathB			0x1
-+#define		PathC			0x2
-+#define		PathD			0x3
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8192FPwrSeq.h b/drivers/staging/rtl8723cs/include/Hal8192FPwrSeq.h
-new file mode 100644
-index 000000000000..2b0bdc7e3e2a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8192FPwrSeq.h
-@@ -0,0 +1,220 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef REALTEK_POWER_SEQUENCE_8192F
-+#define REALTEK_POWER_SEQUENCE_8192F
-+#define POWER_SEQUENCE_8192F_VER 04
-+/* #include "PwrSeqCmd.h" */
-+#include "HalPwrSeqCmd.h"
-+
-+/*
-+	Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd
-+	There are 6 HW Power States:
-+	0: POFF--Power Off
-+	1: PDN--Power Down
-+	2: CARDEMU--Card Emulation
-+	3: ACT--Active Mode
-+	4: LPS--Low Power State
-+	5: SUS--Suspend
-+
-+	The transition from different states are defined below
-+	TRANS_CARDEMU_TO_ACT
-+	TRANS_ACT_TO_CARDEMU
-+	TRANS_CARDEMU_TO_SUS
-+	TRANS_SUS_TO_CARDEMU
-+	TRANS_CARDEMU_TO_PDN
-+	TRANS_ACT_TO_LPS
-+	TRANS_LPS_TO_ACT
-+
-+	TRANS_END
-+*/
-+#define	RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS	38
-+#define	RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS	8
-+#define	RTL8192F_TRANS_CARDEMU_TO_SUS_STEPS	7
-+#define	RTL8192F_TRANS_SUS_TO_CARDEMU_STEPS	5
-+#define	RTL8192F_TRANS_CARDEMU_TO_CARDDIS_STEPS	8
-+#define	RTL8192F_TRANS_CARDDIS_TO_CARDEMU_STEPS	8
-+#define	RTL8192F_TRANS_CARDEMU_TO_PDN_STEPS	4
-+#define	RTL8192F_TRANS_PDN_TO_CARDEMU_STEPS	1
-+#define	RTL8192F_TRANS_ACT_TO_LPS_STEPS		13
-+#define	RTL8192F_TRANS_LPS_TO_ACT_STEPS		11	
-+#define	RTL8192F_TRANS_END_STEPS	1
-+
-+
-+#define RTL8192F_TRANS_CARDEMU_TO_ACT 														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/	\
-+	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
-+	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
-+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
-+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
-+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, (BIT1|BIT0), 0}, \
-+	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/* SWR OCP enable 0x10[18]=1*/ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
-+	{0x007f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x7c[31]=1,LDO has max output capability*/ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
-+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \
-+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
-+	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 data mode*/\
-+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
-+	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
-+	{0x0068, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/*RF HW ON/OFF Enable*/\
-+	{0x001C, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/*Register Lock Disable*/\
-+	{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
-+	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S1*/\
-+	{0x007B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S0*/\
-+	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/*enable RF path S1*/\
-+	{0x007B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/*enalbe RF path S0*/\
-+	{0x0097, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*AFE_Ctrl*/\
-+	{0x00DC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xCC},/*AFE_Ctrl*/\
-+	{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x18, 0x00},/*AFE_Ctrl 0x24[4:3]=00 for xtal gmn*/\
-+	{0x1050, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[7:0] Pull down software register*/\
-+	{0x1051, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[15:8] Pull down software register*/\
-+	{0x1052, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[23:16] Pull down software register*/\
-+	{0x1053, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[31:24] Pull down software register*/\
-+	{0x105B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_B[7:0] Pull down software register*/\
-+	{0x001C, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*Register Lock Enable*/\
-+	{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT7|BIT6), 0x3},/*set HCI Power sequence state delay time:0*/
-+
-+	
-+#define RTL8192F_TRANS_ACT_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x2[0]=0 Reset BB,RF enter Power Down mode*/ \
-+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/ \
-+	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x10[18] = 0 to disable ocp*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
-+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
-+
-+
-+#define RTL8192F_TRANS_CARDEMU_TO_SUS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 USB|SDIO SOP option to disable BG/MB/ACK/SWR*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8192F_TRANS_SUS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
-+	
-+
-+#define RTL8192F_TRANS_CARDEMU_TO_CARDDIS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend*/	\
-+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8192F_TRANS_CARDDIS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/	\
-+	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x10[18] = 1 to enable ocp*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
-+
-+
-+#define RTL8192F_TRANS_CARDEMU_TO_PDN												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
-+
-+#define RTL8192F_TRANS_PDN_TO_CARDEMU												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
-+
-+#define RTL8192F_TRANS_ACT_TO_LPS														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
-+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
-+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
-+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
-+
-+
-+#define RTL8192F_TRANS_LPS_TO_ACT															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
-+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
-+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0 	 switch TSF to 40M*/\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
-+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
-+ 
-+#define RTL8192F_TRANS_END															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
-+
-+
-+extern WLAN_PWR_CFG rtl8192F_power_on_flow[RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8192F_radio_off_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8192F_card_disable_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_CARDDIS_STEPS+RTL8192F_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8192F_card_enable_flow[RTL8192F_TRANS_CARDDIS_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8192F_suspend_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192F_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8192F_resume_flow[RTL8192F_TRANS_SUS_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8192F_hwpdn_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192F_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8192F_enter_lps_flow[RTL8192F_TRANS_ACT_TO_LPS_STEPS+RTL8192F_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8192F_leave_lps_flow[RTL8192F_TRANS_LPS_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8703BPhyCfg.h b/drivers/staging/rtl8723cs/include/Hal8703BPhyCfg.h
-new file mode 100644
-index 000000000000..57a421a031fd
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8703BPhyCfg.h
-@@ -0,0 +1,116 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8703BPHYCFG_H__
-+#define __INC_HAL8703BPHYCFG_H__
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+#define LOOP_LIMIT				5
-+#define MAX_STALL_TIME			50		/* us */
-+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
-+#define MAX_TXPWR_IDX_NMODE_92S	63
-+#define Reset_Cnt_Limit			3
-+
-+#ifdef CONFIG_PCI_HCI
-+	#define MAX_AGGR_NUM	0x0B
-+#else
-+	#define MAX_AGGR_NUM	0x07
-+#endif /* CONFIG_PCI_HCI */
-+
-+
-+/*--------------------------Define Parameters End-------------------------------*/
-+
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+/*------------------------------Define structure End----------------------------*/
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+u32
-+PHY_QueryBBReg_8703B(
-+		PADAPTER	Adapter,
-+		u32		RegAddr,
-+		u32		BitMask
-+);
-+
-+void
-+PHY_SetBBReg_8703B(
-+		PADAPTER	Adapter,
-+		u32		RegAddr,
-+		u32		BitMask,
-+		u32		Data
-+);
-+
-+u32
-+PHY_QueryRFReg_8703B(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				RegAddr,
-+		u32				BitMask
-+);
-+
-+void
-+PHY_SetRFReg_8703B(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				RegAddr,
-+		u32				BitMask,
-+		u32				Data
-+);
-+
-+/* MAC/BB/RF HAL config */
-+int PHY_BBConfig8703B(PADAPTER	Adapter);
-+
-+int PHY_RFConfig8703B(PADAPTER	Adapter);
-+
-+s32 PHY_MACConfig8703B(PADAPTER padapter);
-+
-+int
-+PHY_ConfigRFWithParaFile_8703B(
-+		PADAPTER			Adapter,
-+		u8					*pFileName,
-+	enum rf_path				eRFPath
-+);
-+
-+void
-+PHY_SetTxPowerIndex_8703B(
-+		PADAPTER			Adapter,
-+		u32					PowerIndex,
-+		enum rf_path			RFPath,
-+		u8					Rate
-+);
-+
-+void
-+PHY_SetTxPowerLevel8703B(
-+		PADAPTER		Adapter,
-+		u8			channel
-+);
-+
-+void
-+PHY_SetSwChnlBWMode8703B(
-+		PADAPTER			Adapter,
-+		u8					channel,
-+		enum channel_width	Bandwidth,
-+		u8					Offset40,
-+		u8					Offset80
-+);
-+
-+void phy_set_rf_path_switch_8703b(
-+		struct dm_struct		*phydm,
-+		bool		bMain
-+);
-+
-+/*--------------------------Exported Function prototype End---------------------*/
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8703BPhyReg.h b/drivers/staging/rtl8723cs/include/Hal8703BPhyReg.h
-new file mode 100644
-index 000000000000..881a13cfac87
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8703BPhyReg.h
-@@ -0,0 +1,1133 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8703BPHYREG_H__
-+#define __INC_HAL8703BPHYREG_H__
-+
-+#define		rSYM_WLBT_PAPE_SEL		0x64
-+/*
-+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
-+ * 3. RF register 0x00-2E
-+ * 4. Bit Mask for BB/RF register
-+ * 5. Other defintion for BB/RF R/W
-+ *   */
-+
-+
-+/*
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 1. Page1(0x100)
-+ *   */
-+#define		rPMAC_Reset					0x100
-+#define		rPMAC_TxStart					0x104
-+#define		rPMAC_TxLegacySIG				0x108
-+#define		rPMAC_TxHTSIG1				0x10c
-+#define		rPMAC_TxHTSIG2				0x110
-+#define		rPMAC_PHYDebug				0x114
-+#define		rPMAC_TxPacketNum				0x118
-+#define		rPMAC_TxIdle					0x11c
-+#define		rPMAC_TxMACHeader0			0x120
-+#define		rPMAC_TxMACHeader1			0x124
-+#define		rPMAC_TxMACHeader2			0x128
-+#define		rPMAC_TxMACHeader3			0x12c
-+#define		rPMAC_TxMACHeader4			0x130
-+#define		rPMAC_TxMACHeader5			0x134
-+#define		rPMAC_TxDataType				0x138
-+#define		rPMAC_TxRandomSeed			0x13c
-+#define		rPMAC_CCKPLCPPreamble			0x140
-+#define		rPMAC_CCKPLCPHeader			0x144
-+#define		rPMAC_CCKCRC16				0x148
-+#define		rPMAC_OFDMRxCRC32OK			0x170
-+#define		rPMAC_OFDMRxCRC32Er			0x174
-+#define		rPMAC_OFDMRxParityEr			0x178
-+#define		rPMAC_OFDMRxCRC8Er			0x17c
-+#define		rPMAC_CCKCRxRC16Er			0x180
-+#define		rPMAC_CCKCRxRC32Er			0x184
-+#define		rPMAC_CCKCRxRC32OK			0x188
-+#define		rPMAC_TxStatus					0x18c
-+
-+/*
-+ * 2. Page2(0x200)
-+ *
-+ * The following two definition are only used for USB interface. */
-+#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
-+#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
-+
-+/*
-+ * 3. Page8(0x800)
-+ *   */
-+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
-+
-+#define		rFPGA0_TxInfo				0x804	/* Status report?? */
-+#define		rFPGA0_PSDFunction			0x808
-+
-+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
-+
-+#define		rFPGA0_RFTiming1			0x810	/* Useless now */
-+#define		rFPGA0_RFTiming2			0x814
-+
-+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
-+#define		rFPGA0_XA_HSSIParameter2		0x824
-+#define		rFPGA0_XB_HSSIParameter1		0x828
-+#define		rFPGA0_XB_HSSIParameter2		0x82c
-+#define		rTxAGC_B_Rate18_06				0x830
-+#define		rTxAGC_B_Rate54_24				0x834
-+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
-+#define		rTxAGC_B_Mcs03_Mcs00			0x83c
-+
-+#define		rTxAGC_B_Mcs07_Mcs04			0x848
-+#define		rTxAGC_B_Mcs11_Mcs08			0x84c
-+
-+#define		rFPGA0_XA_LSSIParameter		0x840
-+#define		rFPGA0_XB_LSSIParameter		0x844
-+
-+#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
-+#define		rFPGA0_RFSleepUpParameter		0x854
-+
-+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
-+#define		rFPGA0_XCD_SwitchControl		0x85c
-+
-+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
-+#define		rFPGA0_XB_RFInterfaceOE		0x864
-+
-+#define		rTxAGC_B_Mcs15_Mcs12			0x868
-+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
-+
-+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
-+#define		rFPGA0_XCD_RFInterfaceSW		0x874
-+
-+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
-+#define		rFPGA0_XCD_RFParameter		0x87c
-+
-+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
-+#define		rFPGA0_AnalogParameter2		0x884
-+#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
-+#define		rFPGA0_AnalogParameter4		0x88c
-+
-+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
-+#define		rFPGA0_XB_LSSIReadBack		0x8a4
-+#define		rFPGA0_XC_LSSIReadBack		0x8a8
-+#define		rFPGA0_XD_LSSIReadBack		0x8ac
-+
-+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
-+#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
-+#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
-+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
-+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
-+
-+/*
-+ * 4. Page9(0x900)
-+ *   */
-+#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
-+#define	rFPGA1_TxBlock				0x904	/* Useless now */
-+#define	rFPGA1_DebugSelect			0x908	/* Useless now */
-+#define	rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
-+#define	rDPDT_control				0x92c
-+#define	rfe_ctrl_anta_src				0x930
-+#define	rS0S1_PathSwitch			0x948
-+#define	rBBrx_DFIR					0x954
-+
-+/*
-+ * 5. PageA(0xA00)
-+ *
-+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
-+#define		rCCK0_System				0xa00
-+
-+#define		rCCK0_AFESetting			0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
-+#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
-+
-+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
-+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
-+
-+#define		rCCK0_RxHP					0xa14
-+
-+#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
-+#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
-+
-+#define		rCCK0_TxFilter1				0xa20
-+#define		rCCK0_TxFilter2				0xa24
-+#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
-+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
-+#define		rCCK0_TRSSIReport		0xa50
-+#define		rCCK0_RxReport            		0xa54  /* 0xa57 */
-+#define		rCCK0_FACounterLower      	0xa5c  /* 0xa5b */
-+#define		rCCK0_FACounterUpper      	0xa58  /* 0xa5c */
-+
-+/*
-+ * PageB(0xB00)
-+ *   */
-+#define rPdp_AntA						0xb00
-+#define rPdp_AntA_4						0xb04
-+#define rPdp_AntA_8						0xb08
-+#define rPdp_AntA_C						0xb0c
-+#define rPdp_AntA_10					0xb10
-+#define rPdp_AntA_14					0xb14
-+#define rPdp_AntA_18					0xb18
-+#define rPdp_AntA_1C					0xb1c
-+#define rPdp_AntA_20					0xb20
-+#define rPdp_AntA_24					0xb24
-+
-+#define rConfig_Pmpd_AntA				0xb28
-+#define rConfig_ram64x16				0xb2c
-+
-+#define rBndA							0xb30
-+#define rHssiPar						0xb34
-+
-+#define rConfig_AntA					0xb68
-+#define rConfig_AntB					0xb6c
-+
-+#define rPdp_AntB						0xb70
-+#define rPdp_AntB_4						0xb74
-+#define rPdp_AntB_8						0xb78
-+#define rPdp_AntB_C						0xb7c
-+#define rPdp_AntB_10					0xb80
-+#define rPdp_AntB_14					0xb84
-+#define rPdp_AntB_18					0xb88
-+#define rPdp_AntB_1C					0xb8c
-+#define rPdp_AntB_20					0xb90
-+#define rPdp_AntB_24					0xb94
-+
-+#define rConfig_Pmpd_AntB				0xb98
-+
-+#define rBndB							0xba0
-+
-+#define rAPK							0xbd8
-+#define rPm_Rx0_AntA					0xbdc
-+#define rPm_Rx1_AntA					0xbe0
-+#define rPm_Rx2_AntA					0xbe4
-+#define rPm_Rx3_AntA					0xbe8
-+#define rPm_Rx0_AntB					0xbec
-+#define rPm_Rx1_AntB					0xbf0
-+#define rPm_Rx2_AntB					0xbf4
-+#define rPm_Rx3_AntB					0xbf8
-+/*
-+ * 6. PageC(0xC00)
-+ *   */
-+#define		rOFDM0_LSTF				0xc00
-+
-+#define		rOFDM0_TRxPathEnable		0xc04
-+#define		rOFDM0_TRMuxPar			0xc08
-+#define		rOFDM0_TRSWIsolation		0xc0c
-+
-+#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
-+#define		rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
-+#define		rOFDM0_XBRxAFE		0xc18
-+#define		rOFDM0_XBRxIQImbalance	0xc1c
-+#define		rOFDM0_XCRxAFE		0xc20
-+#define		rOFDM0_XCRxIQImbalance	0xc24
-+#define		rOFDM0_XDRxAFE		0xc28
-+#define		rOFDM0_XDRxIQImbalance	0xc2c
-+
-+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
-+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
-+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
-+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
-+
-+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
-+#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
-+#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
-+#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
-+
-+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
-+#define		rOFDM0_XAAGCCore2			0xc54
-+#define		rOFDM0_XBAGCCore1			0xc58
-+#define		rOFDM0_XBAGCCore2			0xc5c
-+#define		rOFDM0_XCAGCCore1			0xc60
-+#define		rOFDM0_XCAGCCore2			0xc64
-+#define		rOFDM0_XDAGCCore1			0xc68
-+#define		rOFDM0_XDAGCCore2			0xc6c
-+
-+#define		rOFDM0_AGCParameter1			0xc70
-+#define		rOFDM0_AGCParameter2			0xc74
-+#define		rOFDM0_AGCRSSITable			0xc78
-+#define		rOFDM0_HTSTFAGC				0xc7c
-+
-+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
-+#define		rOFDM0_XATxAFE				0xc84
-+#define		rOFDM0_XBTxIQImbalance		0xc88
-+#define		rOFDM0_XBTxAFE				0xc8c
-+#define		rOFDM0_XCTxIQImbalance		0xc90
-+#define		rOFDM0_XCTxAFE			0xc94
-+#define		rOFDM0_XDTxIQImbalance		0xc98
-+#define		rOFDM0_XDTxAFE				0xc9c
-+
-+#define		rOFDM0_RxIQExtAnta			0xca0
-+#define		rOFDM0_TxCoeff1				0xca4
-+#define		rOFDM0_TxCoeff2				0xca8
-+#define		rOFDM0_TxCoeff3				0xcac
-+#define		rOFDM0_TxCoeff4				0xcb0
-+#define		rOFDM0_TxCoeff5				0xcb4
-+#define		rOFDM0_TxCoeff6				0xcb8
-+#define		rOFDM0_RxHPParameter			0xce0
-+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
-+#define		rOFDM0_FrameSync				0xcf0
-+#define		rOFDM0_DFSReport				0xcf4
-+
-+/*
-+ * 7. PageD(0xD00)
-+ *   */
-+#define		rOFDM1_LSTF					0xd00
-+#define		rOFDM1_TRxPathEnable			0xd04
-+
-+#define		rOFDM1_CFO						0xd08	/* No setting now */
-+#define		rOFDM1_CSI1					0xd10
-+#define		rOFDM1_SBD						0xd14
-+#define		rOFDM1_CSI2					0xd18
-+#define		rOFDM1_CFOTracking			0xd2c
-+#define		rOFDM1_TRxMesaure1			0xd34
-+#define		rOFDM1_IntfDet					0xd3c
-+#define		rOFDM1_PseudoNoiseStateAB		0xd50
-+#define		rOFDM1_PseudoNoiseStateCD		0xd54
-+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
-+
-+#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
-+#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
-+#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
-+
-+#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
-+#define		rOFDM_ShortCFOCD				0xdb0
-+#define		rOFDM_LongCFOAB				0xdb4
-+#define		rOFDM_LongCFOCD				0xdb8
-+#define		rOFDM_TailCFOAB				0xdbc
-+#define		rOFDM_TailCFOCD				0xdc0
-+#define		rOFDM_PWMeasure1		0xdc4
-+#define		rOFDM_PWMeasure2		0xdc8
-+#define		rOFDM_BWReport				0xdcc
-+#define		rOFDM_AGCReport				0xdd0
-+#define		rOFDM_RxSNR					0xdd4
-+#define		rOFDM_RxEVMCSI				0xdd8
-+#define		rOFDM_SIGReport				0xddc
-+
-+
-+/*
-+ * 8. PageE(0xE00)
-+ *   */
-+#define		rTxAGC_A_Rate18_06			0xe00
-+#define		rTxAGC_A_Rate54_24			0xe04
-+#define		rTxAGC_A_CCK1_Mcs32			0xe08
-+#define		rTxAGC_A_Mcs03_Mcs00			0xe10
-+#define		rTxAGC_A_Mcs07_Mcs04			0xe14
-+#define		rTxAGC_A_Mcs11_Mcs08			0xe18
-+#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
-+
-+#define		rFPGA0_IQK					0xe28
-+#define		rTx_IQK_Tone_A				0xe30
-+#define		rRx_IQK_Tone_A				0xe34
-+#define		rTx_IQK_PI_A					0xe38
-+#define		rRx_IQK_PI_A					0xe3c
-+
-+#define		rTx_IQK						0xe40
-+#define		rRx_IQK						0xe44
-+#define		rIQK_AGC_Pts					0xe48
-+#define		rIQK_AGC_Rsp					0xe4c
-+#define		rTx_IQK_Tone_B				0xe50
-+#define		rRx_IQK_Tone_B				0xe54
-+#define		rTx_IQK_PI_B					0xe58
-+#define		rRx_IQK_PI_B					0xe5c
-+#define		rIQK_AGC_Cont				0xe60
-+
-+#define		rBlue_Tooth					0xe6c
-+#define		rRx_Wait_CCA					0xe70
-+#define		rTx_CCK_RFON					0xe74
-+#define		rTx_CCK_BBON				0xe78
-+#define		rTx_OFDM_RFON				0xe7c
-+#define		rTx_OFDM_BBON				0xe80
-+#define		rTx_To_Rx					0xe84
-+#define		rTx_To_Tx					0xe88
-+#define		rRx_CCK						0xe8c
-+
-+#define		rTx_Power_Before_IQK_A		0xe94
-+#define		rTx_Power_After_IQK_A			0xe9c
-+
-+#define		rRx_Power_Before_IQK_A		0xea0
-+#define		rRx_Power_Before_IQK_A_2		0xea4
-+#define		rRx_Power_After_IQK_A			0xea8
-+#define		rRx_Power_After_IQK_A_2		0xeac
-+
-+#define		rTx_Power_Before_IQK_B		0xeb4
-+#define		rTx_Power_After_IQK_B			0xebc
-+
-+#define		rRx_Power_Before_IQK_B		0xec0
-+#define		rRx_Power_Before_IQK_B_2		0xec4
-+#define		rRx_Power_After_IQK_B			0xec8
-+#define		rRx_Power_After_IQK_B_2		0xecc
-+
-+#define		rRx_OFDM					0xed0
-+#define		rRx_Wait_RIFS				0xed4
-+#define		rRx_TO_Rx					0xed8
-+#define		rStandby						0xedc
-+#define		rSleep						0xee0
-+#define		rPMPD_ANAEN				0xeec
-+
-+/*
-+ * 7. RF Register 0x00-0x2E (RF 8256)
-+ * RF-0222D 0x00-3F
-+ *
-+ * Zebra1 */
-+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
-+#define		rZebra1_TRxEnable1				0x1
-+#define		rZebra1_TRxEnable2				0x2
-+#define		rZebra1_AGC					0x4
-+#define		rZebra1_ChargePump			0x5
-+#define		rZebra1_Channel				0x7	/* RF channel switch */
-+
-+/* #endif */
-+#define		rZebra1_TxGain					0x8	/* Useless now */
-+#define		rZebra1_TxLPF					0x9
-+#define		rZebra1_RxLPF					0xb
-+#define		rZebra1_RxHPFCorner			0xc
-+
-+/* Zebra4 */
-+#define		rGlobalCtrl						0	/* Useless now */
-+#define		rRTL8256_TxLPF					19
-+#define		rRTL8256_RxLPF					11
-+
-+/* RTL8258 */
-+#define		rRTL8258_TxLPF					0x11	/* Useless now */
-+#define		rRTL8258_RxLPF					0x13
-+#define		rRTL8258_RSSILPF				0xa
-+
-+/*
-+ * RL6052 Register definition
-+ *   */
-+#define		RF_AC						0x00	/*  */
-+
-+#define		RF_IQADJ_G1				0x01	/*  */
-+#define		RF_IQADJ_G2				0x02	/*  */
-+#define		RF_BS_PA_APSET_G1_G4		0x03
-+#define		RF_BS_PA_APSET_G5_G8		0x04
-+#define		RF_POW_TRSW				0x05	/*  */
-+
-+#define		RF_GAIN_RX					0x06	/*  */
-+#define		RF_GAIN_TX					0x07	/*  */
-+
-+#define		RF_TXM_IDAC				0x08	/*  */
-+#define		RF_IPA_G					0x09	/*  */
-+#define		RF_TXBIAS_G				0x0A
-+#define		RF_TXPA_AG					0x0B
-+#define		RF_IPA_A					0x0C	/*  */
-+#define		RF_TXBIAS_A				0x0D
-+#define		RF_BS_PA_APSET_G9_G11	0x0E
-+#define		RF_BS_IQGEN				0x0F	/*  */
-+
-+#define		RF_MODE1					0x10	/*  */
-+#define		RF_MODE2					0x11	/*  */
-+
-+#define		RF_RX_AGC_HP				0x12	/*  */
-+#define		RF_TX_AGC					0x13	/*  */
-+#define		RF_BIAS						0x14	/*  */
-+#define		RF_IPA						0x15	/*  */
-+#define		RF_TXBIAS					0x16
-+#define		RF_POW_ABILITY			0x17	/*  */
-+#define		RF_MODE_AG				0x18	/*  */
-+#define		rRfChannel					0x18	/* RF channel and BW switch */
-+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
-+#define		RF_TOP						0x19	/*  */
-+
-+#define		RF_RX_G1					0x1A	/*  */
-+#define		RF_RX_G2					0x1B	/*  */
-+
-+#define		RF_RX_BB2					0x1C	/*  */
-+#define		RF_RX_BB1					0x1D	/*  */
-+
-+#define		RF_RCK1					0x1E	/*  */
-+#define		RF_RCK2					0x1F	/*  */
-+
-+#define		RF_TX_G1					0x20	/*  */
-+#define		RF_TX_G2					0x21	/*  */
-+#define		RF_TX_G3					0x22	/*  */
-+
-+#define		RF_TX_BB1					0x23	/*  */
-+
-+#define		RF_T_METER					0x24	/*  */
-+
-+#define		RF_SYN_G1					0x25	/* RF TX Power control */
-+#define		RF_SYN_G2					0x26	/* RF TX Power control */
-+#define		RF_SYN_G3					0x27	/* RF TX Power control */
-+#define		RF_SYN_G4					0x28	/* RF TX Power control */
-+#define		RF_SYN_G5					0x29	/* RF TX Power control */
-+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
-+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
-+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
-+
-+#define		RF_RCK_OS					0x30	/* RF TX PA control */
-+
-+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
-+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
-+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
-+#define	RF_TX_BIAS_A				0x35
-+#define	RF_TX_BIAS_D				0x36
-+#define	RF_LOBF_9					0x38
-+#define 	RF_RXRF_A3					0x3C	/*	 */
-+#define	RF_TRSW					0x3F
-+
-+#define	RF_TXRF_A2					0x41
-+#define	RF_TXPA_G4					0x46
-+#define	RF_TXPA_A4					0x4B
-+#define	RF_0x52					0x52
-+#define	RF_WE_LUT					0xEF
-+#define	RF_S0S1					0xB0
-+
-+/*
-+ * Bit Mask
-+ *
-+ * 1. Page1(0x100) */
-+#define		bBBResetB						0x100	/* Useless now? */
-+#define		bGlobalResetB					0x200
-+#define		bOFDMTxStart					0x4
-+#define		bCCKTxStart						0x8
-+#define		bCRC32Debug					0x100
-+#define		bPMACLoopback					0x10
-+#define		bTxLSIG							0xffffff
-+#define		bOFDMTxRate					0xf
-+#define		bOFDMTxReserved				0x10
-+#define		bOFDMTxLength					0x1ffe0
-+#define		bOFDMTxParity					0x20000
-+#define		bTxHTSIG1						0xffffff
-+#define		bTxHTMCSRate					0x7f
-+#define		bTxHTBW						0x80
-+#define		bTxHTLength					0xffff00
-+#define		bTxHTSIG2						0xffffff
-+#define		bTxHTSmoothing					0x1
-+#define		bTxHTSounding					0x2
-+#define		bTxHTReserved					0x4
-+#define		bTxHTAggreation				0x8
-+#define		bTxHTSTBC						0x30
-+#define		bTxHTAdvanceCoding			0x40
-+#define		bTxHTShortGI					0x80
-+#define		bTxHTNumberHT_LTF			0x300
-+#define		bTxHTCRC8						0x3fc00
-+#define		bCounterReset					0x10000
-+#define		bNumOfOFDMTx					0xffff
-+#define		bNumOfCCKTx					0xffff0000
-+#define		bTxIdleInterval					0xffff
-+#define		bOFDMService					0xffff0000
-+#define		bTxMACHeader					0xffffffff
-+#define		bTxDataInit						0xff
-+#define		bTxHTMode						0x100
-+#define		bTxDataType					0x30000
-+#define		bTxRandomSeed					0xffffffff
-+#define		bCCKTxPreamble					0x1
-+#define		bCCKTxSFD						0xffff0000
-+#define		bCCKTxSIG						0xff
-+#define		bCCKTxService					0xff00
-+#define		bCCKLengthExt					0x8000
-+#define		bCCKTxLength					0xffff0000
-+#define		bCCKTxCRC16					0xffff
-+#define		bCCKTxStatus					0x1
-+#define		bOFDMTxStatus					0x2
-+
-+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
-+#define	RF_TX_GAIN_OFFSET_8703B(_val) (abs((_val)) | (((_val) > 0) ? BIT5 : 0))
-+
-+/* 2. Page8(0x800) */
-+#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
-+#define		bJapanMode						0x2
-+#define		bCCKTxSC						0x30
-+#define		bCCKEn							0x1000000
-+#define		bOFDMEn						0x2000000
-+
-+#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
-+#define		bOFDMTxDACPhase		0x40000
-+#define		bXATxAGC			0x3f
-+
-+#define		bAntennaSelect		0x0300
-+
-+#define		bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
-+#define		bXCTxAGC			0xf000
-+#define		bXDTxAGC			0xf0000
-+
-+#define		bPAStart                  			0xf0000000	/* Useless now */
-+#define		bTRStart			0x00f00000
-+#define		bRFStart			0x0000f000
-+#define		bBBStart			0x000000f0
-+#define		bBBCCKStart		0x0000000f
-+#define		bPAEnd                    			0xf          /* Reg0x814 */
-+#define		bTREnd			0x0f000000
-+#define		bRFEnd			0x000f0000
-+#define		bCCAMask                  			0x000000f0   /* T2R */
-+#define		bR2RCCAMask		0x00000f00
-+#define		bHSSI_R2TDelay		0xf8000000
-+#define		bHSSI_T2RDelay		0xf80000
-+#define		bContTxHSSI               		0x400     /* chane gain at continue Tx */
-+#define		bIGFromCCK		0x200
-+#define		bAGCAddress		0x3f
-+#define		bRxHPTx			0x7000
-+#define		bRxHPT2R			0x38000
-+#define		bRxHPCCKIni		0xc0000
-+#define		bAGCTxCode		0xc00000
-+#define		bAGCRxCode		0x300000
-+
-+#define		b3WireDataLength          		0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
-+#define		b3WireAddressLength		0x400
-+
-+#define		b3WireRFPowerDown         		0x1	/* Useless now
-+ * #define bHWSISelect		0x8 */
-+#define		b5GPAPEPolarity		0x40000000
-+#define		b2GPAPEPolarity		0x80000000
-+#define		bRFSW_TxDefaultAnt		0x3
-+#define		bRFSW_TxOptionAnt		0x30
-+#define		bRFSW_RxDefaultAnt		0x300
-+#define		bRFSW_RxOptionAnt		0x3000
-+#define		bRFSI_3WireData		0x1
-+#define		bRFSI_3WireClock		0x2
-+#define		bRFSI_3WireLoad		0x4
-+#define		bRFSI_3WireRW		0x8
-+#define		bRFSI_3Wire			0xf
-+
-+#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
-+
-+#define		bRFSI_TRSW                		0x20	/* Useless now */
-+#define		bRFSI_TRSWB		0x40
-+#define		bRFSI_ANTSW		0x100
-+#define		bRFSI_ANTSWB		0x200
-+#define		bRFSI_PAPE			0x400
-+#define		bRFSI_PAPE5G		0x800
-+#define		bBandSelect			0x1
-+#define		bHTSIG2_GI			0x80
-+#define		bHTSIG2_Smoothing		0x01
-+#define		bHTSIG2_Sounding		0x02
-+#define		bHTSIG2_Aggreaton		0x08
-+#define		bHTSIG2_STBC		0x30
-+#define		bHTSIG2_AdvCoding		0x40
-+#define		bHTSIG2_NumOfHTLTF	0x300
-+#define		bHTSIG2_CRC8		0x3fc
-+#define		bHTSIG1_MCS		0x7f
-+#define		bHTSIG1_BandWidth		0x80
-+#define		bHTSIG1_HTLength		0xffff
-+#define		bLSIG_Rate			0xf
-+#define		bLSIG_Reserved		0x10
-+#define		bLSIG_Length		0x1fffe
-+#define		bLSIG_Parity			0x20
-+#define		bCCKRxPhase		0x4
-+
-+#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
-+
-+#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
-+
-+#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
-+
-+#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
-+#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
-+#define		bRegulator0Standby		0x1
-+#define		bRegulatorPLLStandby		0x2
-+#define		bRegulator1Standby		0x4
-+#define		bPLLPowerUp		0x8
-+#define		bDPLLPowerUp		0x10
-+#define		bDA10PowerUp		0x20
-+#define		bAD7PowerUp		0x200
-+#define		bDA6PowerUp		0x2000
-+#define		bXtalPowerUp		0x4000
-+#define		b40MDClkPowerUP		0x8000
-+#define		bDA6DebugMode		0x20000
-+#define		bDA6Swing			0x380000
-+
-+#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
-+
-+#define		b80MClkDelay              		0x18000000	/* Useless */
-+#define		bAFEWatchDogEnable		0x20000000
-+
-+#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
-+#define		bXtalCap23			0x3
-+#define		bXtalCap92x					0x0f000000
-+#define		bXtalCap			0x0f000000
-+
-+#define		bIntDifClkEnable          		0x400	/* Useless */
-+#define		bExtSigClkEnable		0x800
-+#define		bBandgapMbiasPowerUp	0x10000
-+#define		bAD11SHGain		0xc0000
-+#define		bAD11InputRange		0x700000
-+#define		bAD11OPCurrent		0x3800000
-+#define		bIPathLoopback		0x4000000
-+#define		bQPathLoopback		0x8000000
-+#define		bAFELoopback		0x10000000
-+#define		bDA10Swing		0x7e0
-+#define		bDA10Reverse		0x800
-+#define		bDAClkSource		0x1000
-+#define		bAD7InputRange		0x6000
-+#define		bAD7Gain			0x38000
-+#define		bAD7OutputCMMode		0x40000
-+#define		bAD7InputCMMode		0x380000
-+#define		bAD7Current			0xc00000
-+#define		bRegulatorAdjust		0x7000000
-+#define		bAD11PowerUpAtTx		0x1
-+#define		bDA10PSAtTx		0x10
-+#define		bAD11PowerUpAtRx		0x100
-+#define		bDA10PSAtRx		0x1000
-+#define		bCCKRxAGCFormat		0x200
-+#define		bPSDFFTSamplepPoint		0xc000
-+#define		bPSDAverageNum		0x3000
-+#define		bIQPathControl		0xc00
-+#define		bPSDFreq			0x3ff
-+#define		bPSDAntennaPath		0x30
-+#define		bPSDIQSwitch		0x40
-+#define		bPSDRxTrigger		0x400000
-+#define		bPSDTxTrigger		0x80000000
-+#define		bPSDSineToneScale		0x7f000000
-+#define		bPSDReport			0xffff
-+
-+/* 3. Page9(0x900) */
-+#define		bOFDMTxSC                 		0x30000000	/* Useless */
-+#define		bCCKTxOn			0x1
-+#define		bOFDMTxOn		0x2
-+#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
-+#define		bDebugItem                		0xff   /* reset debug page and LWord */
-+#define		bAntL			0x10
-+#define		bAntNonHT				0x100
-+#define		bAntHT1			0x1000
-+#define		bAntHT2			0x10000
-+#define		bAntHT1S1			0x100000
-+#define		bAntNonHTS1		0x1000000
-+
-+/* 4. PageA(0xA00) */
-+#define		bCCKBBMode				0x3	/* Useless */
-+#define		bCCKTxPowerSaving		0x80
-+#define		bCCKRxPowerSaving		0x40
-+
-+#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
-+
-+#define		bCCKScramble			0x8	/* Useless */
-+#define		bCCKAntDiversity		0x8000
-+#define		bCCKCarrierRecovery		0x4000
-+#define		bCCKTxRate				0x3000
-+#define		bCCKDCCancel			0x0800
-+#define		bCCKISICancel			0x0400
-+#define		bCCKMatchFilter			0x0200
-+#define		bCCKEqualizer			0x0100
-+#define		bCCKPreambleDetect		0x800000
-+#define		bCCKFastFalseCCA		0x400000
-+#define		bCCKChEstStart			0x300000
-+#define		bCCKCCACount			0x080000
-+#define		bCCKcs_lim				0x070000
-+#define		bCCKBistMode			0x80000000
-+#define		bCCKCCAMask			0x40000000
-+#define		bCCKTxDACPhase		0x4
-+#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
-+#define		bCCKr_cp_mode0		0x0100
-+#define		bCCKTxDCOffset			0xf0
-+#define		bCCKRxDCOffset			0xf
-+#define		bCCKCCAMode			0xc000
-+#define		bCCKFalseCS_lim			0x3f00
-+#define		bCCKCS_ratio			0xc00000
-+#define		bCCKCorgBit_sel			0x300000
-+#define		bCCKPD_lim				0x0f0000
-+#define		bCCKNewCCA			0x80000000
-+#define		bCCKRxHPofIG			0x8000
-+#define		bCCKRxIG				0x7f00
-+#define		bCCKLNAPolarity			0x800000
-+#define		bCCKRx1stGain			0x7f0000
-+#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
-+#define		bCCKRxAGCSatLevel		0x1f000000
-+#define		bCCKRxAGCSatCount		0xe0
-+#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
-+#define		bCCKFixedRxAGC			0x8000
-+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
-+#define		bCCKAntennaPolarity		0x2000
-+#define		bCCKTxFilterType		0x0c00
-+#define		bCCKRxAGCReportType	0x0300
-+#define		bCCKRxDAGCEn			0x80000000
-+#define		bCCKRxDAGCPeriod		0x20000000
-+#define		bCCKRxDAGCSatLevel		0x1f000000
-+#define		bCCKTimingRecovery		0x800000
-+#define		bCCKTxC0				0x3f0000
-+#define		bCCKTxC1				0x3f000000
-+#define		bCCKTxC2				0x3f
-+#define		bCCKTxC3				0x3f00
-+#define		bCCKTxC4				0x3f0000
-+#define		bCCKTxC5				0x3f000000
-+#define		bCCKTxC6				0x3f
-+#define		bCCKTxC7				0x3f00
-+#define		bCCKDebugPort			0xff0000
-+#define		bCCKDACDebug			0x0f000000
-+#define		bCCKFalseAlarmEnable	0x8000
-+#define		bCCKFalseAlarmRead		0x4000
-+#define		bCCKTRSSI				0x7f
-+#define		bCCKRxAGCReport		0xfe
-+#define		bCCKRxReport_AntSel	0x80000000
-+#define		bCCKRxReport_MFOff		0x40000000
-+#define		bCCKRxRxReport_SQLoss	0x20000000
-+#define		bCCKRxReport_Pktloss	0x10000000
-+#define		bCCKRxReport_Lockedbit	0x08000000
-+#define		bCCKRxReport_RateError	0x04000000
-+#define		bCCKRxReport_RxRate	0x03000000
-+#define		bCCKRxFACounterLower	0xff
-+#define		bCCKRxFACounterUpper	0xff000000
-+#define		bCCKRxHPAGCStart		0xe000
-+#define		bCCKRxHPAGCFinal		0x1c00
-+#define		bCCKRxFalseAlarmEnable	0x8000
-+#define		bCCKFACounterFreeze	0x4000
-+#define		bCCKTxPathSel			0x10000000
-+#define		bCCKDefaultRxPath		0xc000000
-+#define		bCCKOptionRxPath		0x3000000
-+
-+/* 5. PageC(0xC00) */
-+#define		bNumOfSTF				0x3	/* Useless */
-+#define		bShift_L					0xc0
-+#define		bGI_TH					0xc
-+#define		bRxPathA				0x1
-+#define		bRxPathB				0x2
-+#define		bRxPathC				0x4
-+#define		bRxPathD				0x8
-+#define		bTxPathA				0x1
-+#define		bTxPathB				0x2
-+#define		bTxPathC				0x4
-+#define		bTxPathD				0x8
-+#define		bTRSSIFreq				0x200
-+#define		bADCBackoff				0x3000
-+#define		bDFIRBackoff			0xc000
-+#define		bTRSSILatchPhase		0x10000
-+#define		bRxIDCOffset			0xff
-+#define		bRxQDCOffset			0xff00
-+#define		bRxDFIRMode			0x1800000
-+#define		bRxDCNFType			0xe000000
-+#define		bRXIQImb_A				0x3ff
-+#define		bRXIQImb_B				0xfc00
-+#define		bRXIQImb_C				0x3f0000
-+#define		bRXIQImb_D				0xffc00000
-+#define		bDC_dc_Notch			0x60000
-+#define		bRxNBINotch			0x1f000000
-+#define		bPD_TH					0xf
-+#define		bPD_TH_Opt2			0xc000
-+#define		bPWED_TH				0x700
-+#define		bIfMF_Win_L			0x800
-+#define		bPD_Option				0x1000
-+#define		bMF_Win_L				0xe000
-+#define		bBW_Search_L			0x30000
-+#define		bwin_enh_L				0xc0000
-+#define		bBW_TH					0x700000
-+#define		bED_TH2				0x3800000
-+#define		bBW_option				0x4000000
-+#define		bRatio_TH				0x18000000
-+#define		bWindow_L				0xe0000000
-+#define		bSBD_Option				0x1
-+#define		bFrame_TH				0x1c
-+#define		bFS_Option				0x60
-+#define		bDC_Slope_check		0x80
-+#define		bFGuard_Counter_DC_L	0xe00
-+#define		bFrame_Weight_Short	0x7000
-+#define		bSub_Tune				0xe00000
-+#define		bFrame_DC_Length		0xe000000
-+#define		bSBD_start_offset		0x30000000
-+#define		bFrame_TH_2			0x7
-+#define		bFrame_GI2_TH			0x38
-+#define		bGI2_Sync_en			0x40
-+#define		bSarch_Short_Early		0x300
-+#define		bSarch_Short_Late		0xc00
-+#define		bSarch_GI2_Late		0x70000
-+#define		bCFOAntSum				0x1
-+#define		bCFOAcc				0x2
-+#define		bCFOStartOffset			0xc
-+#define		bCFOLookBack			0x70
-+#define		bCFOSumWeight			0x80
-+#define		bDAGCEnable			0x10000
-+#define		bTXIQImb_A				0x3ff
-+#define		bTXIQImb_B				0xfc00
-+#define		bTXIQImb_C				0x3f0000
-+#define		bTXIQImb_D				0xffc00000
-+#define		bTxIDCOffset			0xff
-+#define		bTxQDCOffset			0xff00
-+#define		bTxDFIRMode			0x10000
-+#define		bTxPesudoNoiseOn		0x4000000
-+#define		bTxPesudoNoise_A		0xff
-+#define		bTxPesudoNoise_B		0xff00
-+#define		bTxPesudoNoise_C		0xff0000
-+#define		bTxPesudoNoise_D		0xff000000
-+#define		bCCADropOption			0x20000
-+#define		bCCADropThres			0xfff00000
-+#define		bEDCCA_H				0xf
-+#define		bEDCCA_L				0xf0
-+#define		bLambda_ED			0x300
-+#define		bRxInitialGain			0x7f
-+#define		bRxAntDivEn				0x80
-+#define		bRxAGCAddressForLNA	0x7f00
-+#define		bRxHighPowerFlow		0x8000
-+#define		bRxAGCFreezeThres		0xc0000
-+#define		bRxFreezeStep_AGC1	0x300000
-+#define		bRxFreezeStep_AGC2	0xc00000
-+#define		bRxFreezeStep_AGC3	0x3000000
-+#define		bRxFreezeStep_AGC0	0xc000000
-+#define		bRxRssi_Cmp_En			0x10000000
-+#define		bRxQuickAGCEn			0x20000000
-+#define		bRxAGCFreezeThresMode	0x40000000
-+#define		bRxOverFlowCheckType	0x80000000
-+#define		bRxAGCShift				0x7f
-+#define		bTRSW_Tri_Only			0x80
-+#define		bPowerThres			0x300
-+#define		bRxAGCEn				0x1
-+#define		bRxAGCTogetherEn		0x2
-+#define		bRxAGCMin				0x4
-+#define		bRxHP_Ini				0x7
-+#define		bRxHP_TRLNA			0x70
-+#define		bRxHP_RSSI				0x700
-+#define		bRxHP_BBP1				0x7000
-+#define		bRxHP_BBP2				0x70000
-+#define		bRxHP_BBP3				0x700000
-+#define		bRSSI_H					0x7f0000     /* the threshold for high power */
-+#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
-+#define		bRxSettle_TRSW			0x7
-+#define		bRxSettle_LNA			0x38
-+#define		bRxSettle_RSSI			0x1c0
-+#define		bRxSettle_BBP			0xe00
-+#define		bRxSettle_RxHP			0x7000
-+#define		bRxSettle_AntSW_RSSI	0x38000
-+#define		bRxSettle_AntSW		0xc0000
-+#define		bRxProcessTime_DAGC	0x300000
-+#define		bRxSettle_HSSI			0x400000
-+#define		bRxProcessTime_BBPPW	0x800000
-+#define		bRxAntennaPowerShift	0x3000000
-+#define		bRSSITableSelect		0xc000000
-+#define		bRxHP_Final				0x7000000
-+#define		bRxHTSettle_BBP			0x7
-+#define		bRxHTSettle_HSSI		0x8
-+#define		bRxHTSettle_RxHP		0x70
-+#define		bRxHTSettle_BBPPW		0x80
-+#define		bRxHTSettle_Idle		0x300
-+#define		bRxHTSettle_Reserved	0x1c00
-+#define		bRxHTRxHPEn			0x8000
-+#define		bRxHTAGCFreezeThres	0x30000
-+#define		bRxHTAGCTogetherEn	0x40000
-+#define		bRxHTAGCMin			0x80000
-+#define		bRxHTAGCEn				0x100000
-+#define		bRxHTDAGCEn			0x200000
-+#define		bRxHTRxHP_BBP			0x1c00000
-+#define		bRxHTRxHP_Final		0xe0000000
-+#define		bRxPWRatioTH			0x3
-+#define		bRxPWRatioEn			0x4
-+#define		bRxMFHold				0x3800
-+#define		bRxPD_Delay_TH1		0x38
-+#define		bRxPD_Delay_TH2		0x1c0
-+#define		bRxPD_DC_COUNT_MAX	0x600
-+/* #define bRxMF_Hold               0x3800 */
-+#define		bRxPD_Delay_TH			0x8000
-+#define		bRxProcess_Delay		0xf0000
-+#define		bRxSearchrange_GI2_Early	0x700000
-+#define		bRxFrame_Guard_Counter_L	0x3800000
-+#define		bRxSGI_Guard_L			0xc000000
-+#define		bRxSGI_Search_L		0x30000000
-+#define		bRxSGI_TH				0xc0000000
-+#define		bDFSCnt0				0xff
-+#define		bDFSCnt1				0xff00
-+#define		bDFSFlag				0xf0000
-+#define		bMFWeightSum			0x300000
-+#define		bMinIdxTH				0x7f000000
-+#define		bDAFormat				0x40000
-+#define		bTxChEmuEnable		0x01000000
-+#define		bTRSWIsolation_A		0x7f
-+#define		bTRSWIsolation_B		0x7f00
-+#define		bTRSWIsolation_C		0x7f0000
-+#define		bTRSWIsolation_D		0x7f000000
-+#define		bExtLNAGain				0x7c00
-+
-+/* 6. PageE(0xE00) */
-+#define		bSTBCEn				0x4	/* Useless */
-+#define		bAntennaMapping		0x10
-+#define		bNss					0x20
-+#define		bCFOAntSumD			0x200
-+#define		bPHYCounterReset		0x8000000
-+#define		bCFOReportGet			0x4000000
-+#define		bOFDMContinueTx		0x10000000
-+#define		bOFDMSingleCarrier		0x20000000
-+#define		bOFDMSingleTone		0x40000000
-+/* #define bRxPath1                 0x01 */
-+/* #define bRxPath2                 0x02 */
-+/* #define bRxPath3                 0x04 */
-+/* #define bRxPath4                 0x08 */
-+/* #define bTxPath1                 0x10 */
-+/* #define bTxPath2                 0x20 */
-+#define		bHTDetect			0x100
-+#define		bCFOEn				0x10000
-+#define		bCFOValue			0xfff00000
-+#define		bSigTone_Re		0x3f
-+#define		bSigTone_Im		0x7f00
-+#define		bCounter_CCA		0xffff
-+#define		bCounter_ParityFail	0xffff0000
-+#define		bCounter_RateIllegal		0xffff
-+#define		bCounter_CRC8Fail	0xffff0000
-+#define		bCounter_MCSNoSupport	0xffff
-+#define		bCounter_FastSync	0xffff
-+#define		bShortCFO			0xfff
-+#define		bShortCFOTLength	12   /* total */
-+#define		bShortCFOFLength	11   /* fraction */
-+#define		bLongCFO			0x7ff
-+#define		bLongCFOTLength	11
-+#define		bLongCFOFLength	11
-+#define		bTailCFO			0x1fff
-+#define		bTailCFOTLength		13
-+#define		bTailCFOFLength		12
-+#define		bmax_en_pwdB		0xffff
-+#define		bCC_power_dB		0xffff0000
-+#define		bnoise_pwdB		0xffff
-+#define		bPowerMeasTLength	10
-+#define		bPowerMeasFLength	3
-+#define		bRx_HT_BW			0x1
-+#define		bRxSC				0x6
-+#define		bRx_HT				0x8
-+#define		bNB_intf_det_on		0x1
-+#define		bIntf_win_len_cfg	0x30
-+#define		bNB_Intf_TH_cfg		0x1c0
-+#define		bRFGain				0x3f
-+#define		bTableSel			0x40
-+#define		bTRSW				0x80
-+#define		bRxSNR_A			0xff
-+#define		bRxSNR_B			0xff00
-+#define		bRxSNR_C			0xff0000
-+#define		bRxSNR_D			0xff000000
-+#define		bSNREVMTLength		8
-+#define		bSNREVMFLength		1
-+#define		bCSI1st				0xff
-+#define		bCSI2nd				0xff00
-+#define		bRxEVM1st			0xff0000
-+#define		bRxEVM2nd			0xff000000
-+#define		bSIGEVM			0xff
-+#define		bPWDB				0xff00
-+#define		bSGIEN				0x10000
-+
-+#define		bSFactorQAM1		0xf	/* Useless */
-+#define		bSFactorQAM2		0xf0
-+#define		bSFactorQAM3		0xf00
-+#define		bSFactorQAM4		0xf000
-+#define		bSFactorQAM5		0xf0000
-+#define		bSFactorQAM6		0xf0000
-+#define		bSFactorQAM7		0xf00000
-+#define		bSFactorQAM8		0xf000000
-+#define		bSFactorQAM9		0xf0000000
-+#define		bCSIScheme			0x100000
-+
-+#define		bNoiseLvlTopSet		0x3	/* Useless */
-+#define		bChSmooth			0x4
-+#define		bChSmoothCfg1		0x38
-+#define		bChSmoothCfg2		0x1c0
-+#define		bChSmoothCfg3		0xe00
-+#define		bChSmoothCfg4		0x7000
-+#define		bMRCMode			0x800000
-+#define		bTHEVMCfg			0x7000000
-+
-+#define		bLoopFitType		0x1	/* Useless */
-+#define		bUpdCFO			0x40
-+#define		bUpdCFOOffData		0x80
-+#define		bAdvUpdCFO			0x100
-+#define		bAdvTimeCtrl		0x800
-+#define		bUpdClko			0x1000
-+#define		bFC					0x6000
-+#define		bTrackingMode		0x8000
-+#define		bPhCmpEnable		0x10000
-+#define		bUpdClkoLTF		0x20000
-+#define		bComChCFO			0x40000
-+#define		bCSIEstiMode		0x80000
-+#define		bAdvUpdEqz			0x100000
-+#define		bUChCfg				0x7000000
-+#define		bUpdEqz			0x8000000
-+
-+/* Rx Pseduo noise */
-+#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
-+#define		bRxPesudoNoise_A		0xff
-+#define		bRxPesudoNoise_B		0xff00
-+#define		bRxPesudoNoise_C		0xff0000
-+#define		bRxPesudoNoise_D		0xff000000
-+#define		bPesudoNoiseState_A	0xffff
-+#define		bPesudoNoiseState_B	0xffff0000
-+#define		bPesudoNoiseState_C	0xffff
-+#define		bPesudoNoiseState_D	0xffff0000
-+
-+/* 7. RF Register
-+ * Zebra1 */
-+#define		bZebra1_HSSIEnable		0x8		/* Useless */
-+#define		bZebra1_TRxControl		0xc00
-+#define		bZebra1_TRxGainSetting	0x07f
-+#define		bZebra1_RxCorner		0xc00
-+#define		bZebra1_TxChargePump	0x38
-+#define		bZebra1_RxChargePump	0x7
-+#define		bZebra1_ChannelNum	0xf80
-+#define		bZebra1_TxLPFBW		0x400
-+#define		bZebra1_RxLPFBW		0x600
-+
-+/* Zebra4 */
-+#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
-+#define		bRTL8256RegModeCtrl0	0x40
-+#define		bRTL8256_TxLPFBW		0x18
-+#define		bRTL8256_RxLPFBW		0x600
-+
-+/* RTL8258 */
-+#define		bRTL8258_TxLPFBW		0xc	/* Useless */
-+#define		bRTL8258_RxLPFBW		0xc00
-+#define		bRTL8258_RSSILPFBW	0xc0
-+
-+
-+/*
-+ * Other Definition
-+ *   */
-+
-+/* byte endable for sb_write */
-+#define		bByte0				0x1	/* Useless */
-+#define		bByte1				0x2
-+#define		bByte2				0x4
-+#define		bByte3				0x8
-+#define		bWord0				0x3
-+#define		bWord1				0xc
-+#define		bDWord				0xf
-+
-+/* for PutRegsetting & GetRegSetting BitMask */
-+#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
-+#define		bMaskByte1			0xff00
-+#define		bMaskByte2			0xff0000
-+#define		bMaskByte3			0xff000000
-+#define		bMaskHWord		0xffff0000
-+#define		bMaskLWord			0x0000ffff
-+#define		bMaskDWord		0xffffffff
-+#define		bMaskH3Bytes		0xffffff00
-+#define		bMask12Bits			0xfff
-+#define		bMaskH4Bits			0xf0000000
-+#define		bMaskOFDM_D		0xffc00000
-+#define		bMaskCCK			0x3f3f3f3f
-+
-+
-+#define		bEnable			0x1	/* Useless */
-+#define		bDisable		0x0
-+
-+#define		LeftAntenna		0x0	/* Useless */
-+#define		RightAntenna	0x1
-+
-+#define		tCheckTxStatus		500   /* 500ms */ /* Useless */
-+#define		tUpdateRxCounter	100   /* 100ms */
-+
-+#define		rateCCK		0	/* Useless */
-+#define		rateOFDM	1
-+#define		rateHT		2
-+
-+/* define Register-End */
-+#define		bPMAC_End			0x1ff	/* Useless */
-+#define		bFPGAPHY0_End		0x8ff
-+#define		bFPGAPHY1_End		0x9ff
-+#define		bCCKPHY0_End		0xaff
-+#define		bOFDMPHY0_End		0xcff
-+#define		bOFDMPHY1_End		0xdff
-+
-+/* define max debug item in each debug page
-+ * #define bMaxItem_FPGA_PHY0        0x9
-+ * #define bMaxItem_FPGA_PHY1        0x3
-+ * #define bMaxItem_PHY_11B          0x16
-+ * #define bMaxItem_OFDM_PHY0        0x29
-+ * #define bMaxItem_OFDM_PHY1        0x0 */
-+
-+#define		bPMACControl		0x0		/* Useless */
-+#define		bWMACControl		0x1
-+#define		bWNICControl		0x2
-+
-+#define		PathA			0x0	/* Useless */
-+#define		PathB			0x1
-+#define		PathC			0x2
-+#define		PathD			0x3
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8703BPwrSeq.h b/drivers/staging/rtl8723cs/include/Hal8703BPwrSeq.h
-new file mode 100644
-index 000000000000..0dac13ee34a9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8703BPwrSeq.h
-@@ -0,0 +1,198 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef REALTEK_POWER_SEQUENCE_8703B
-+#define REALTEK_POWER_SEQUENCE_8703B
-+
-+#include "HalPwrSeqCmd.h"
-+
-+/*
-+	Check document WM-20140402-JackieLau-RTL8703B_Power_Architecture v09.vsd
-+	There are 6 HW Power States:
-+	0: POFF--Power Off
-+	1: PDN--Power Down
-+	2: CARDEMU--Card Emulation
-+	3: ACT--Active Mode
-+	4: LPS--Low Power State
-+	5: SUS--Suspend
-+
-+	The transision from different states are defined below
-+	TRANS_CARDEMU_TO_ACT
-+	TRANS_ACT_TO_CARDEMU
-+	TRANS_CARDEMU_TO_SUS
-+	TRANS_SUS_TO_CARDEMU
-+	TRANS_CARDEMU_TO_PDN
-+	TRANS_ACT_TO_LPS
-+	TRANS_LPS_TO_ACT
-+
-+	TRANS_END
-+*/
-+#define	RTL8703B_TRANS_CARDEMU_TO_ACT_STEPS	23
-+#define	RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS	15
-+#define	RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS	15
-+#define	RTL8703B_TRANS_SUS_TO_CARDEMU_STEPS	15
-+#define	RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS	15
-+#define	RTL8703B_TRANS_PDN_TO_CARDEMU_STEPS	15
-+#define	RTL8703B_TRANS_ACT_TO_LPS_STEPS		15
-+#define	RTL8703B_TRANS_LPS_TO_ACT_STEPS		15
-+#define	RTL8703B_TRANS_END_STEPS		1
-+
-+
-+#define RTL8703B_TRANS_CARDEMU_TO_ACT														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \
-+	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
-+	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
-+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/	\
-+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */	\
-+	{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 , BIT3},/* enabled usb resume */	\
-+	{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 , 0},/* disable usb resume */	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
-+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
-+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/	\
-+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
-+	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
-+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
-+	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
-+	{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
-+	{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\
-+	{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
-+
-+
-+#define RTL8703B_TRANS_ACT_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
-+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
-+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\
-+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
-+
-+
-+#define RTL8703B_TRANS_CARDEMU_TO_SUS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8703B_TRANS_SUS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
-+
-+#define RTL8703B_TRANS_CARDEMU_TO_CARDDIS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
-+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8703B_TRANS_CARDDIS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
-+
-+
-+#define RTL8703B_TRANS_CARDEMU_TO_PDN												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
-+
-+#define RTL8703B_TRANS_PDN_TO_CARDEMU												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
-+
-+#define RTL8703B_TRANS_ACT_TO_LPS														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
-+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
-+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
-+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
-+
-+
-+#define RTL8703B_TRANS_LPS_TO_ACT															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
-+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
-+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
-+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
-+
-+#define RTL8703B_TRANS_END															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
-+
-+
-+	extern WLAN_PWR_CFG rtl8703B_power_on_flow[RTL8703B_TRANS_CARDEMU_TO_ACT_STEPS + RTL8703B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8703B_radio_off_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8703B_card_disable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8703B_card_enable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8703B_suspend_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8703B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8703B_resume_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8703B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8703B_hwpdn_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8703B_enter_lps_flow[RTL8703B_TRANS_ACT_TO_LPS_STEPS + RTL8703B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8703B_leave_lps_flow[RTL8703B_TRANS_LPS_TO_ACT_STEPS + RTL8703B_TRANS_END_STEPS];
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8710BPhyCfg.h b/drivers/staging/rtl8723cs/include/Hal8710BPhyCfg.h
-new file mode 100644
-index 000000000000..3c5808e92ae8
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8710BPhyCfg.h
-@@ -0,0 +1,111 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8710BPHYCFG_H__
-+#define __INC_HAL8710BPHYCFG_H__
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+#define LOOP_LIMIT				5
-+#define MAX_STALL_TIME			50		/* us */
-+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
-+#define MAX_TXPWR_IDX_NMODE_92S	63
-+#define Reset_Cnt_Limit			3
-+
-+#ifdef CONFIG_PCI_HCI
-+	#define MAX_AGGR_NUM	0x0B
-+#else
-+	#define MAX_AGGR_NUM	0x07
-+#endif /* CONFIG_PCI_HCI */
-+
-+
-+/*--------------------------Define Parameters End-------------------------------*/
-+
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+/*------------------------------Define structure End----------------------------*/
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+u32
-+PHY_QueryBBReg_8710B(
-+		PADAPTER	Adapter,
-+		u32		RegAddr,
-+		u32		BitMask
-+);
-+
-+void
-+PHY_SetBBReg_8710B(
-+		PADAPTER	Adapter,
-+		u32		RegAddr,
-+		u32		BitMask,
-+		u32		Data
-+);
-+
-+u32
-+PHY_QueryRFReg_8710B(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				RegAddr,
-+		u32				BitMask
-+);
-+
-+void
-+PHY_SetRFReg_8710B(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				RegAddr,
-+		u32				BitMask,
-+		u32				Data
-+);
-+
-+/* MAC/BB/RF HAL config */
-+int PHY_BBConfig8710B(PADAPTER	Adapter);
-+
-+int PHY_RFConfig8710B(PADAPTER	Adapter);
-+
-+s32 PHY_MACConfig8710B(PADAPTER padapter);
-+
-+int
-+PHY_ConfigRFWithParaFile_8710B(
-+		PADAPTER			Adapter,
-+		u8				*pFileName,
-+	enum rf_path				eRFPath
-+);
-+
-+void
-+PHY_SetTxPowerIndex_8710B(
-+		PADAPTER			Adapter,
-+		u32					PowerIndex,
-+		enum rf_path			RFPath,
-+		u8					Rate
-+);
-+
-+void
-+PHY_SetTxPowerLevel8710B(
-+		PADAPTER		Adapter,
-+		u8			channel
-+);
-+
-+void
-+PHY_SetSwChnlBWMode8710B(
-+		PADAPTER			Adapter,
-+		u8					channel,
-+		enum channel_width	Bandwidth,
-+		u8					Offset40,
-+		u8					Offset80
-+);
-+
-+/*--------------------------Exported Function prototype End---------------------*/
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8710BPhyReg.h b/drivers/staging/rtl8723cs/include/Hal8710BPhyReg.h
-new file mode 100644
-index 000000000000..337e03207fed
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8710BPhyReg.h
-@@ -0,0 +1,1134 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8710BPHYREG_H__
-+#define __INC_HAL8710BPHYREG_H__
-+
-+#define		rSYM_WLBT_PAPE_SEL		0x64
-+/*
-+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
-+ * 3. RF register 0x00-2E
-+ * 4. Bit Mask for BB/RF register
-+ * 5. Other definition for BB/RF R/W
-+ *   */
-+
-+
-+/*
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 1. Page1(0x100)
-+ *   */
-+#define		rPMAC_Reset					0x100
-+#define		rPMAC_TxStart					0x104
-+#define		rPMAC_TxLegacySIG				0x108
-+#define		rPMAC_TxHTSIG1				0x10c
-+#define		rPMAC_TxHTSIG2				0x110
-+#define		rPMAC_PHYDebug				0x114
-+#define		rPMAC_TxPacketNum				0x118
-+#define		rPMAC_TxIdle					0x11c
-+#define		rPMAC_TxMACHeader0			0x120
-+#define		rPMAC_TxMACHeader1			0x124
-+#define		rPMAC_TxMACHeader2			0x128
-+#define		rPMAC_TxMACHeader3			0x12c
-+#define		rPMAC_TxMACHeader4			0x130
-+#define		rPMAC_TxMACHeader5			0x134
-+#define		rPMAC_TxDataType				0x138
-+#define		rPMAC_TxRandomSeed			0x13c
-+#define		rPMAC_CCKPLCPPreamble			0x140
-+#define		rPMAC_CCKPLCPHeader			0x144
-+#define		rPMAC_CCKCRC16				0x148
-+#define		rPMAC_OFDMRxCRC32OK			0x170
-+#define		rPMAC_OFDMRxCRC32Er			0x174
-+#define		rPMAC_OFDMRxParityEr			0x178
-+#define		rPMAC_OFDMRxCRC8Er			0x17c
-+#define		rPMAC_CCKCRxRC16Er			0x180
-+#define		rPMAC_CCKCRxRC32Er			0x184
-+#define		rPMAC_CCKCRxRC32OK			0x188
-+#define		rPMAC_TxStatus					0x18c
-+
-+/*
-+ * 2. Page2(0x200)
-+ *
-+ * The following two definition are only used for USB interface. */
-+#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
-+#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
-+
-+/*
-+ * 3. Page8(0x800)
-+ *   */
-+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC // RF BW Setting?? */
-+
-+#define		rFPGA0_TxInfo				0x804	/* Status report?? */
-+#define		rFPGA0_PSDFunction			0x808
-+
-+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
-+
-+#define		rFPGA0_RFTiming1			0x810	/* Useless now */
-+#define		rFPGA0_RFTiming2			0x814
-+
-+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
-+#define		rFPGA0_XA_HSSIParameter2		0x824
-+#define		rFPGA0_XB_HSSIParameter1		0x828
-+#define		rFPGA0_XB_HSSIParameter2		0x82c
-+#define		rTxAGC_B_Rate18_06				0x830
-+#define		rTxAGC_B_Rate54_24				0x834
-+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
-+#define		rTxAGC_B_Mcs03_Mcs00			0x83c
-+
-+#define		rTxAGC_B_Mcs07_Mcs04			0x848
-+#define		rTxAGC_B_Mcs11_Mcs08			0x84c
-+
-+#define		rFPGA0_XA_LSSIParameter		0x840
-+#define		rFPGA0_XB_LSSIParameter		0x844
-+
-+#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
-+#define		rFPGA0_RFSleepUpParameter		0x854
-+
-+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
-+#define		rFPGA0_XCD_SwitchControl		0x85c
-+
-+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
-+#define		rFPGA0_XB_RFInterfaceOE		0x864
-+
-+#define		rTxAGC_B_Mcs15_Mcs12			0x868
-+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
-+
-+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
-+#define		rFPGA0_XCD_RFInterfaceSW		0x874
-+
-+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
-+#define		rFPGA0_XCD_RFParameter		0x87c
-+
-+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
-+#define		rFPGA0_AnalogParameter2		0x884
-+#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
-+#define		rFPGA0_AnalogParameter4		0x88c
-+
-+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
-+#define		rFPGA0_XB_LSSIReadBack		0x8a4
-+#define		rFPGA0_XC_LSSIReadBack		0x8a8
-+#define		rFPGA0_XD_LSSIReadBack		0x8ac
-+
-+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
-+#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
-+#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
-+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now // RF Interface Readback Value */
-+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
-+
-+/*
-+ * 4. Page9(0x900)
-+ *   */
-+#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC // RF BW Setting?? */
-+#define	rFPGA1_TxBlock				0x904	/* Useless now */
-+#define	rFPGA1_DebugSelect			0x908	/* Useless now */
-+#define	rFPGA1_TxInfo				0x90c	/* Useless now // Status report?? */
-+#define	rDPDT_control				0x92c
-+#define	rfe_ctrl_anta_src				0x930
-+#define	rS0S1_PathSwitch			0x948
-+#define	rBBrx_DFIR					0x954
-+
-+/*
-+ * 5. PageA(0xA00)
-+ *
-+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
-+#define		rCCK0_System				0xa00
-+
-+#define		rCCK0_AFESetting			0xa04	/* Disable init gain now // Select RX path by RSSI */
-+#define		rCCK0_CCA					0xa08	/* Disable init gain now // Init gain */
-+
-+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
-+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
-+
-+#define		rCCK0_RxHP					0xa14
-+
-+#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
-+#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
-+
-+#define		rCCK0_TxFilter1				0xa20
-+#define		rCCK0_TxFilter2				0xa24
-+#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
-+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
-+#define		rCCK0_TRSSIReport		0xa50
-+#define		rCCK0_RxReport			0xa54  /* 0xa57 */
-+#define		rCCK0_FACounterLower		0xa5c  /* 0xa5b */
-+#define		rCCK0_FACounterUpper		0xa58  /* 0xa5c */
-+
-+/*
-+ * PageB(0xB00)
-+ *   */
-+#define rPdp_AntA						0xb00
-+#define rPdp_AntA_4						0xb04
-+#define rPdp_AntA_8						0xb08
-+#define rPdp_AntA_C						0xb0c
-+#define rPdp_AntA_10					0xb10
-+#define rPdp_AntA_14					0xb14
-+#define rPdp_AntA_18					0xb18
-+#define rPdp_AntA_1C					0xb1c
-+#define rPdp_AntA_20					0xb20
-+#define rPdp_AntA_24					0xb24
-+
-+#define rConfig_Pmpd_AntA				0xb28
-+#define rConfig_ram64x16				0xb2c
-+
-+#define rBndA							0xb30
-+#define rHssiPar						0xb34
-+
-+#define rConfig_AntA					0xb68
-+#define rConfig_AntB					0xb6c
-+
-+#define rPdp_AntB						0xb70
-+#define rPdp_AntB_4						0xb74
-+#define rPdp_AntB_8						0xb78
-+#define rPdp_AntB_C						0xb7c
-+#define rPdp_AntB_10					0xb80
-+#define rPdp_AntB_14					0xb84
-+#define rPdp_AntB_18					0xb88
-+#define rPdp_AntB_1C					0xb8c
-+#define rPdp_AntB_20					0xb90
-+#define rPdp_AntB_24					0xb94
-+
-+#define rConfig_Pmpd_AntB				0xb98
-+
-+#define rBndB							0xba0
-+
-+#define rAPK							0xbd8
-+#define rPm_Rx0_AntA					0xbdc
-+#define rPm_Rx1_AntA					0xbe0
-+#define rPm_Rx2_AntA					0xbe4
-+#define rPm_Rx3_AntA					0xbe8
-+#define rPm_Rx0_AntB					0xbec
-+#define rPm_Rx1_AntB					0xbf0
-+#define rPm_Rx2_AntB					0xbf4
-+#define rPm_Rx3_AntB					0xbf8
-+/*
-+ * 6. PageC(0xC00)
-+ *   */
-+#define		rOFDM0_LSTF				0xc00
-+
-+#define		rOFDM0_TRxPathEnable		0xc04
-+#define		rOFDM0_TRMuxPar			0xc08
-+#define		rOFDM0_TRSWIsolation		0xc0c
-+
-+#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
-+#define		rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imbalance matrix */
-+#define		rOFDM0_XBRxAFE		0xc18
-+#define		rOFDM0_XBRxIQImbalance	0xc1c
-+#define		rOFDM0_XCRxAFE		0xc20
-+#define		rOFDM0_XCRxIQImbalance	0xc24
-+#define		rOFDM0_XDRxAFE		0xc28
-+#define		rOFDM0_XDRxIQImbalance	0xc2c
-+
-+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	// DM tune init gain */
-+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
-+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
-+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
-+
-+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
-+#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
-+#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
-+#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
-+
-+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
-+#define		rOFDM0_XAAGCCore2			0xc54
-+#define		rOFDM0_XBAGCCore1			0xc58
-+#define		rOFDM0_XBAGCCore2			0xc5c
-+#define		rOFDM0_XCAGCCore1			0xc60
-+#define		rOFDM0_XCAGCCore2			0xc64
-+#define		rOFDM0_XDAGCCore1			0xc68
-+#define		rOFDM0_XDAGCCore2			0xc6c
-+
-+#define		rOFDM0_AGCParameter1			0xc70
-+#define		rOFDM0_AGCParameter2			0xc74
-+#define		rOFDM0_AGCRSSITable			0xc78
-+#define		rOFDM0_HTSTFAGC				0xc7c
-+
-+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
-+#define		rOFDM0_XATxAFE				0xc84
-+#define		rOFDM0_XBTxIQImbalance		0xc88
-+#define		rOFDM0_XBTxAFE				0xc8c
-+#define		rOFDM0_XCTxIQImbalance		0xc90
-+#define		rOFDM0_XCTxAFE			0xc94
-+#define		rOFDM0_XDTxIQImbalance		0xc98
-+#define		rOFDM0_XDTxAFE				0xc9c
-+
-+#define		rOFDM0_RxIQExtAnta			0xca0
-+#define		rOFDM0_TxCoeff1				0xca4
-+#define		rOFDM0_TxCoeff2				0xca8
-+#define		rOFDM0_TxCoeff3				0xcac
-+#define		rOFDM0_TxCoeff4				0xcb0
-+#define		rOFDM0_TxCoeff5				0xcb4
-+#define		rOFDM0_TxCoeff6				0xcb8
-+#define		rOFDM0_RxHPParameter			0xce0
-+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
-+#define		rOFDM0_FrameSync				0xcf0
-+#define		rOFDM0_DFSReport				0xcf4
-+
-+/*
-+ * 7. PageD(0xD00)
-+ *   */
-+#define		rOFDM1_LSTF					0xd00
-+#define		rOFDM1_TRxPathEnable			0xd04
-+
-+#define		rOFDM1_CFO						0xd08	/* No setting now */
-+#define		rOFDM1_CSI1					0xd10
-+#define		rOFDM1_SBD						0xd14
-+#define		rOFDM1_CSI2					0xd18
-+#define		rOFDM1_CFOTracking			0xd2c
-+#define		rOFDM1_TRxMesaure1			0xd34
-+#define		rOFDM1_IntfDet					0xd3c
-+#define		rOFDM1_PseudoNoiseStateAB		0xd50
-+#define		rOFDM1_PseudoNoiseStateCD		0xd54
-+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
-+
-+#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
-+#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
-+#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
-+
-+#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
-+#define		rOFDM_ShortCFOCD				0xdb0
-+#define		rOFDM_LongCFOAB				0xdb4
-+#define		rOFDM_LongCFOCD				0xdb8
-+#define		rOFDM_TailCFOAB				0xdbc
-+#define		rOFDM_TailCFOCD				0xdc0
-+#define		rOFDM_PWMeasure1		0xdc4
-+#define		rOFDM_PWMeasure2		0xdc8
-+#define		rOFDM_BWReport				0xdcc
-+#define		rOFDM_AGCReport				0xdd0
-+#define		rOFDM_RxSNR					0xdd4
-+#define		rOFDM_RxEVMCSI				0xdd8
-+#define		rOFDM_SIGReport				0xddc
-+
-+
-+/*
-+ * 8. PageE(0xE00)
-+ *   */
-+#define		rTxAGC_A_Rate18_06			0xe00
-+#define		rTxAGC_A_Rate54_24			0xe04
-+#define		rTxAGC_A_CCK1_Mcs32			0xe08
-+#define		rTxAGC_A_Mcs03_Mcs00			0xe10
-+#define		rTxAGC_A_Mcs07_Mcs04			0xe14
-+#define		rTxAGC_A_Mcs11_Mcs08			0xe18
-+#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
-+
-+#define		rFPGA0_IQK					0xe28
-+#define		rTx_IQK_Tone_A				0xe30
-+#define		rRx_IQK_Tone_A				0xe34
-+#define		rTx_IQK_PI_A					0xe38
-+#define		rRx_IQK_PI_A					0xe3c
-+
-+#define		rTx_IQK						0xe40
-+#define		rRx_IQK						0xe44
-+#define		rIQK_AGC_Pts					0xe48
-+#define		rIQK_AGC_Rsp					0xe4c
-+#define		rTx_IQK_Tone_B				0xe50
-+#define		rRx_IQK_Tone_B				0xe54
-+#define		rTx_IQK_PI_B					0xe58
-+#define		rRx_IQK_PI_B					0xe5c
-+#define		rIQK_AGC_Cont				0xe60
-+
-+#define		rBlue_Tooth					0xe6c
-+#define		rRx_Wait_CCA					0xe70
-+#define		rTx_CCK_RFON					0xe74
-+#define		rTx_CCK_BBON				0xe78
-+#define		rTx_OFDM_RFON				0xe7c
-+#define		rTx_OFDM_BBON				0xe80
-+#define		rTx_To_Rx					0xe84
-+#define		rTx_To_Tx					0xe88
-+#define		rRx_CCK						0xe8c
-+
-+#define		rTx_Power_Before_IQK_A		0xe94
-+#define		rTx_Power_After_IQK_A			0xe9c
-+
-+#define		rRx_Power_Before_IQK_A		0xea0
-+#define		rRx_Power_Before_IQK_A_2		0xea4
-+#define		rRx_Power_After_IQK_A			0xea8
-+#define		rRx_Power_After_IQK_A_2		0xeac
-+
-+#define		rTx_Power_Before_IQK_B		0xeb4
-+#define		rTx_Power_After_IQK_B			0xebc
-+
-+#define		rRx_Power_Before_IQK_B		0xec0
-+#define		rRx_Power_Before_IQK_B_2		0xec4
-+#define		rRx_Power_After_IQK_B			0xec8
-+#define		rRx_Power_After_IQK_B_2		0xecc
-+
-+#define		rRx_OFDM					0xed0
-+#define		rRx_Wait_RIFS				0xed4
-+#define		rRx_TO_Rx					0xed8
-+#define		rStandby						0xedc
-+#define		rSleep						0xee0
-+#define		rPMPD_ANAEN				0xeec
-+
-+/*
-+ * 7. RF Register 0x00-0x2E (RF 8256)
-+ * RF-0222D 0x00-3F
-+ *
-+ * Zebra1 */
-+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
-+#define		rZebra1_TRxEnable1				0x1
-+#define		rZebra1_TRxEnable2				0x2
-+#define		rZebra1_AGC					0x4
-+#define		rZebra1_ChargePump			0x5
-+#define		rZebra1_Channel				0x7	/* RF channel switch */
-+
-+/* #endif */
-+#define		rZebra1_TxGain					0x8	/* Useless now */
-+#define		rZebra1_TxLPF					0x9
-+#define		rZebra1_RxLPF					0xb
-+#define		rZebra1_RxHPFCorner			0xc
-+
-+/* Zebra4 */
-+#define		rGlobalCtrl						0	/* Useless now */
-+#define		rRTL8256_TxLPF					19
-+#define		rRTL8256_RxLPF					11
-+
-+/* RTL8258 */
-+#define		rRTL8258_TxLPF					0x11	/* Useless now */
-+#define		rRTL8258_RxLPF					0x13
-+#define		rRTL8258_RSSILPF				0xa
-+
-+/*
-+ * RL6052 Register definition
-+ *   */
-+#define		RF_AC						0x00	/* */
-+
-+#define		RF_IQADJ_G1				0x01	/* */
-+#define		RF_IQADJ_G2				0x02	/* */
-+#define		RF_BS_PA_APSET_G1_G4		0x03
-+#define		RF_BS_PA_APSET_G5_G8		0x04
-+#define		RF_POW_TRSW				0x05	/* */
-+
-+#define		RF_GAIN_RX					0x06	/* */
-+#define		RF_GAIN_TX					0x07	/* */
-+
-+#define		RF_TXM_IDAC				0x08	/* */
-+#define		RF_IPA_G					0x09	/* */
-+#define		RF_TXBIAS_G				0x0A
-+#define		RF_TXPA_AG					0x0B
-+#define		RF_IPA_A					0x0C	/* */
-+#define		RF_TXBIAS_A				0x0D
-+#define		RF_BS_PA_APSET_G9_G11	0x0E
-+#define		RF_BS_IQGEN				0x0F	/* */
-+
-+#define		RF_MODE1					0x10	/* */
-+#define		RF_MODE2					0x11	/* */
-+
-+#define		RF_RX_AGC_HP				0x12	/* */
-+#define		RF_TX_AGC					0x13	/* */
-+#define		RF_BIAS						0x14	/* */
-+#define		RF_IPA						0x15	/* */
-+#define		RF_TXBIAS					0x16
-+#define		RF_POW_ABILITY			0x17	/* */
-+#define		RF_MODE_AG				0x18	/* */
-+#define		rRfChannel					0x18	/* RF channel and BW switch */
-+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
-+#define		RF_TOP						0x19	/* */
-+
-+#define		RF_RX_G1					0x1A	/* */
-+#define		RF_RX_G2					0x1B	/* */
-+
-+#define		RF_RX_BB2					0x1C	/* */
-+#define		RF_RX_BB1					0x1D	/* */
-+
-+#define		RF_RCK1					0x1E	/* */
-+#define		RF_RCK2					0x1F	/* */
-+
-+#define		RF_TX_G1					0x20	/* */
-+#define		RF_TX_G2					0x21	/* */
-+#define		RF_TX_G3					0x22	/* */
-+
-+#define		RF_TX_BB1					0x23	/* */
-+
-+#define		RF_T_METER					0x24	/* */
-+
-+#define		RF_SYN_G1					0x25	/* RF TX Power control */
-+#define		RF_SYN_G2					0x26	/* RF TX Power control */
-+#define		RF_SYN_G3					0x27	/* RF TX Power control */
-+#define		RF_SYN_G4					0x28	/* RF TX Power control */
-+#define		RF_SYN_G5					0x29	/* RF TX Power control */
-+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
-+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
-+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
-+
-+#define		RF_RCK_OS					0x30	/* RF TX PA control */
-+
-+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
-+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
-+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
-+#define	RF_TX_BIAS_A				0x35
-+#define	RF_TX_BIAS_D				0x36
-+#define	RF_LOBF_9					0x38
-+#define	RF_RXRF_A3					0x3C	/*	 */
-+#define	RF_TRSW					0x3F
-+
-+#define	RF_TXRF_A2					0x41
-+#define	RF_T_METER_88E				0x42
-+#define	RF_TXPA_G4					0x46
-+#define	RF_TXPA_A4					0x4B
-+#define	RF_0x52					0x52
-+#define	RF_WE_LUT					0xEF
-+#define	RF_S0S1					0xB0
-+
-+/*
-+ * Bit Mask
-+ *
-+ * 1. Page1(0x100) */
-+#define		bBBResetB						0x100	/* Useless now? */
-+#define		bGlobalResetB					0x200
-+#define		bOFDMTxStart					0x4
-+#define		bCCKTxStart						0x8
-+#define		bCRC32Debug					0x100
-+#define		bPMACLoopback					0x10
-+#define		bTxLSIG							0xffffff
-+#define		bOFDMTxRate					0xf
-+#define		bOFDMTxReserved				0x10
-+#define		bOFDMTxLength					0x1ffe0
-+#define		bOFDMTxParity					0x20000
-+#define		bTxHTSIG1						0xffffff
-+#define		bTxHTMCSRate					0x7f
-+#define		bTxHTBW						0x80
-+#define		bTxHTLength					0xffff00
-+#define		bTxHTSIG2						0xffffff
-+#define		bTxHTSmoothing					0x1
-+#define		bTxHTSounding					0x2
-+#define		bTxHTReserved					0x4
-+#define		bTxHTAggreation				0x8
-+#define		bTxHTSTBC						0x30
-+#define		bTxHTAdvanceCoding			0x40
-+#define		bTxHTShortGI					0x80
-+#define		bTxHTNumberHT_LTF			0x300
-+#define		bTxHTCRC8						0x3fc00
-+#define		bCounterReset					0x10000
-+#define		bNumOfOFDMTx					0xffff
-+#define		bNumOfCCKTx					0xffff0000
-+#define		bTxIdleInterval					0xffff
-+#define		bOFDMService					0xffff0000
-+#define		bTxMACHeader					0xffffffff
-+#define		bTxDataInit						0xff
-+#define		bTxHTMode						0x100
-+#define		bTxDataType					0x30000
-+#define		bTxRandomSeed					0xffffffff
-+#define		bCCKTxPreamble					0x1
-+#define		bCCKTxSFD						0xffff0000
-+#define		bCCKTxSIG						0xff
-+#define		bCCKTxService					0xff00
-+#define		bCCKLengthExt					0x8000
-+#define		bCCKTxLength					0xffff0000
-+#define		bCCKTxCRC16					0xffff
-+#define		bCCKTxStatus					0x1
-+#define		bOFDMTxStatus					0x2
-+
-+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
-+#define		RF_TX_GAIN_OFFSET_8710B(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0))
-+
-+/* 2. Page8(0x800) */
-+#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
-+#define		bJapanMode						0x2
-+#define		bCCKTxSC						0x30
-+#define		bCCKEn							0x1000000
-+#define		bOFDMEn						0x2000000
-+
-+#define		bOFDMRxADCPhase           0x10000	/* Useless now */
-+#define		bOFDMTxDACPhase		0x40000
-+#define		bXATxAGC			0x3f
-+
-+#define		bAntennaSelect		0x0300
-+
-+#define		bXBTxAGC                 0xf00	/* Reg 80c rFPGA0_TxGainStage */
-+#define		bXCTxAGC			0xf000
-+#define		bXDTxAGC			0xf0000
-+
-+#define		bPAStart                 0xf0000000	/* Useless now */
-+#define		bTRStart			0x00f00000
-+#define		bRFStart			0x0000f000
-+#define		bBBStart			0x000000f0
-+#define		bBBCCKStart		0x0000000f
-+#define		bPAEnd                    0xf          /* Reg0x814 */
-+#define		bTREnd			0x0f000000
-+#define		bRFEnd			0x000f0000
-+#define		bCCAMask                  0x000000f0   /* T2R */
-+#define		bR2RCCAMask		0x00000f00
-+#define		bHSSI_R2TDelay		0xf8000000
-+#define		bHSSI_T2RDelay		0xf80000
-+#define		bContTxHSSI              0x400     /* chane gain at continue Tx */
-+#define		bIGFromCCK		0x200
-+#define		bAGCAddress		0x3f
-+#define		bRxHPTx			0x7000
-+#define		bRxHPT2R			0x38000
-+#define		bRxHPCCKIni		0xc0000
-+#define		bAGCTxCode		0xc00000
-+#define		bAGCRxCode		0x300000
-+
-+#define		b3WireDataLength         0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
-+#define		b3WireAddressLength		0x400
-+
-+#define		b3WireRFPowerDown         0x1	/* Useless now
-+ * #define bHWSISelect		0x8 */
-+#define		b5GPAPEPolarity		0x40000000
-+#define		b2GPAPEPolarity		0x80000000
-+#define		bRFSW_TxDefaultAnt		0x3
-+#define		bRFSW_TxOptionAnt		0x30
-+#define		bRFSW_RxDefaultAnt		0x300
-+#define		bRFSW_RxOptionAnt		0x3000
-+#define		bRFSI_3WireData		0x1
-+#define		bRFSI_3WireClock		0x2
-+#define		bRFSI_3WireLoad		0x4
-+#define		bRFSI_3WireRW		0x8
-+#define		bRFSI_3Wire			0xf
-+
-+#define		bRFSI_RFENV              0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
-+
-+#define		bRFSI_TRSW               0x20	/* Useless now */
-+#define		bRFSI_TRSWB		0x40
-+#define		bRFSI_ANTSW		0x100
-+#define		bRFSI_ANTSWB		0x200
-+#define		bRFSI_PAPE			0x400
-+#define		bRFSI_PAPE5G		0x800
-+#define		bBandSelect			0x1
-+#define		bHTSIG2_GI			0x80
-+#define		bHTSIG2_Smoothing		0x01
-+#define		bHTSIG2_Sounding		0x02
-+#define		bHTSIG2_Aggreaton		0x08
-+#define		bHTSIG2_STBC		0x30
-+#define		bHTSIG2_AdvCoding		0x40
-+#define		bHTSIG2_NumOfHTLTF	0x300
-+#define		bHTSIG2_CRC8		0x3fc
-+#define		bHTSIG1_MCS		0x7f
-+#define		bHTSIG1_BandWidth		0x80
-+#define		bHTSIG1_HTLength		0xffff
-+#define		bLSIG_Rate			0xf
-+#define		bLSIG_Reserved		0x10
-+#define		bLSIG_Length		0x1fffe
-+#define		bLSIG_Parity			0x20
-+#define		bCCKRxPhase		0x4
-+
-+#define		bLSSIReadAddress          0x7f800000   /* T65 RF */
-+
-+#define		bLSSIReadEdge             0x80000000   /* LSSI "Read" edge signal */
-+
-+#define		bLSSIReadBackData         0xfffff		/* T65 RF */
-+
-+#define		bLSSIReadOKFlag           0x1000	/* Useless now */
-+#define		bCCKSampleRate            0x8       /* 0: 44MHz, 1:88MHz     */
-+#define		bRegulator0Standby		0x1
-+#define		bRegulatorPLLStandby		0x2
-+#define		bRegulator1Standby		0x4
-+#define		bPLLPowerUp		0x8
-+#define		bDPLLPowerUp		0x10
-+#define		bDA10PowerUp		0x20
-+#define		bAD7PowerUp		0x200
-+#define		bDA6PowerUp		0x2000
-+#define		bXtalPowerUp		0x4000
-+#define		b40MDClkPowerUP		0x8000
-+#define		bDA6DebugMode		0x20000
-+#define		bDA6Swing			0x380000
-+
-+#define		bADClkPhase               0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
-+
-+#define		b80MClkDelay              0x18000000	/* Useless */
-+#define		bAFEWatchDogEnable		0x20000000
-+
-+#define		bXtalCap01                0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
-+#define		bXtalCap23			0x3
-+#define		bXtalCap92x					0x0f000000
-+#define		bXtalCap			0x0f000000
-+
-+#define		bIntDifClkEnable          0x400	/* Useless */
-+#define		bExtSigClkEnable		0x800
-+#define		bBandgapMbiasPowerUp	0x10000
-+#define		bAD11SHGain		0xc0000
-+#define		bAD11InputRange		0x700000
-+#define		bAD11OPCurrent		0x3800000
-+#define		bIPathLoopback		0x4000000
-+#define		bQPathLoopback		0x8000000
-+#define		bAFELoopback		0x10000000
-+#define		bDA10Swing		0x7e0
-+#define		bDA10Reverse		0x800
-+#define		bDAClkSource		0x1000
-+#define		bAD7InputRange		0x6000
-+#define		bAD7Gain			0x38000
-+#define		bAD7OutputCMMode		0x40000
-+#define		bAD7InputCMMode		0x380000
-+#define		bAD7Current			0xc00000
-+#define		bRegulatorAdjust		0x7000000
-+#define		bAD11PowerUpAtTx		0x1
-+#define		bDA10PSAtTx		0x10
-+#define		bAD11PowerUpAtRx		0x100
-+#define		bDA10PSAtRx		0x1000
-+#define		bCCKRxAGCFormat		0x200
-+#define		bPSDFFTSamplepPoint		0xc000
-+#define		bPSDAverageNum		0x3000
-+#define		bIQPathControl		0xc00
-+#define		bPSDFreq			0x3ff
-+#define		bPSDAntennaPath		0x30
-+#define		bPSDIQSwitch		0x40
-+#define		bPSDRxTrigger		0x400000
-+#define		bPSDTxTrigger		0x80000000
-+#define		bPSDSineToneScale		0x7f000000
-+#define		bPSDReport			0xffff
-+
-+/* 3. Page9(0x900) */
-+#define		bOFDMTxSC                 0x30000000	/* Useless */
-+#define		bCCKTxOn			0x1
-+#define		bOFDMTxOn		0x2
-+#define		bDebugPage                0xfff  /* reset debug page and also HWord, LWord */
-+#define		bDebugItem                0xff   /* reset debug page and LWord */
-+#define		bAntL			0x10
-+#define		bAntNonHT				0x100
-+#define		bAntHT1			0x1000
-+#define		bAntHT2			0x10000
-+#define		bAntHT1S1			0x100000
-+#define		bAntNonHTS1		0x1000000
-+
-+/* 4. PageA(0xA00) */
-+#define		bCCKBBMode				0x3	/* Useless */
-+#define		bCCKTxPowerSaving		0x80
-+#define		bCCKRxPowerSaving		0x40
-+
-+#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
-+
-+#define		bCCKScramble			0x8	/* Useless */
-+#define		bCCKAntDiversity		0x8000
-+#define		bCCKCarrierRecovery		0x4000
-+#define		bCCKTxRate				0x3000
-+#define		bCCKDCCancel			0x0800
-+#define		bCCKISICancel			0x0400
-+#define		bCCKMatchFilter			0x0200
-+#define		bCCKEqualizer			0x0100
-+#define		bCCKPreambleDetect		0x800000
-+#define		bCCKFastFalseCCA		0x400000
-+#define		bCCKChEstStart			0x300000
-+#define		bCCKCCACount			0x080000
-+#define		bCCKcs_lim				0x070000
-+#define		bCCKBistMode			0x80000000
-+#define		bCCKCCAMask			0x40000000
-+#define		bCCKTxDACPhase		0x4
-+#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
-+#define		bCCKr_cp_mode0		0x0100
-+#define		bCCKTxDCOffset			0xf0
-+#define		bCCKRxDCOffset			0xf
-+#define		bCCKCCAMode			0xc000
-+#define		bCCKFalseCS_lim			0x3f00
-+#define		bCCKCS_ratio			0xc00000
-+#define		bCCKCorgBit_sel			0x300000
-+#define		bCCKPD_lim				0x0f0000
-+#define		bCCKNewCCA			0x80000000
-+#define		bCCKRxHPofIG			0x8000
-+#define		bCCKRxIG				0x7f00
-+#define		bCCKLNAPolarity			0x800000
-+#define		bCCKRx1stGain			0x7f0000
-+#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
-+#define		bCCKRxAGCSatLevel		0x1f000000
-+#define		bCCKRxAGCSatCount		0xe0
-+#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
-+#define		bCCKFixedRxAGC			0x8000
-+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
-+#define		bCCKAntennaPolarity		0x2000
-+#define		bCCKTxFilterType		0x0c00
-+#define		bCCKRxAGCReportType	0x0300
-+#define		bCCKRxDAGCEn			0x80000000
-+#define		bCCKRxDAGCPeriod		0x20000000
-+#define		bCCKRxDAGCSatLevel		0x1f000000
-+#define		bCCKTimingRecovery		0x800000
-+#define		bCCKTxC0				0x3f0000
-+#define		bCCKTxC1				0x3f000000
-+#define		bCCKTxC2				0x3f
-+#define		bCCKTxC3				0x3f00
-+#define		bCCKTxC4				0x3f0000
-+#define		bCCKTxC5				0x3f000000
-+#define		bCCKTxC6				0x3f
-+#define		bCCKTxC7				0x3f00
-+#define		bCCKDebugPort			0xff0000
-+#define		bCCKDACDebug			0x0f000000
-+#define		bCCKFalseAlarmEnable	0x8000
-+#define		bCCKFalseAlarmRead		0x4000
-+#define		bCCKTRSSI				0x7f
-+#define		bCCKRxAGCReport		0xfe
-+#define		bCCKRxReport_AntSel	0x80000000
-+#define		bCCKRxReport_MFOff		0x40000000
-+#define		bCCKRxRxReport_SQLoss	0x20000000
-+#define		bCCKRxReport_Pktloss	0x10000000
-+#define		bCCKRxReport_Lockedbit	0x08000000
-+#define		bCCKRxReport_RateError	0x04000000
-+#define		bCCKRxReport_RxRate	0x03000000
-+#define		bCCKRxFACounterLower	0xff
-+#define		bCCKRxFACounterUpper	0xff000000
-+#define		bCCKRxHPAGCStart		0xe000
-+#define		bCCKRxHPAGCFinal		0x1c00
-+#define		bCCKRxFalseAlarmEnable	0x8000
-+#define		bCCKFACounterFreeze	0x4000
-+#define		bCCKTxPathSel			0x10000000
-+#define		bCCKDefaultRxPath		0xc000000
-+#define		bCCKOptionRxPath		0x3000000
-+
-+/* 5. PageC(0xC00) */
-+#define		bNumOfSTF				0x3	/* Useless */
-+#define		bShift_L					0xc0
-+#define		bGI_TH					0xc
-+#define		bRxPathA				0x1
-+#define		bRxPathB				0x2
-+#define		bRxPathC				0x4
-+#define		bRxPathD				0x8
-+#define		bTxPathA				0x1
-+#define		bTxPathB				0x2
-+#define		bTxPathC				0x4
-+#define		bTxPathD				0x8
-+#define		bTRSSIFreq				0x200
-+#define		bADCBackoff				0x3000
-+#define		bDFIRBackoff			0xc000
-+#define		bTRSSILatchPhase		0x10000
-+#define		bRxIDCOffset			0xff
-+#define		bRxQDCOffset			0xff00
-+#define		bRxDFIRMode			0x1800000
-+#define		bRxDCNFType			0xe000000
-+#define		bRXIQImb_A				0x3ff
-+#define		bRXIQImb_B				0xfc00
-+#define		bRXIQImb_C				0x3f0000
-+#define		bRXIQImb_D				0xffc00000
-+#define		bDC_dc_Notch			0x60000
-+#define		bRxNBINotch			0x1f000000
-+#define		bPD_TH					0xf
-+#define		bPD_TH_Opt2			0xc000
-+#define		bPWED_TH				0x700
-+#define		bIfMF_Win_L			0x800
-+#define		bPD_Option				0x1000
-+#define		bMF_Win_L				0xe000
-+#define		bBW_Search_L			0x30000
-+#define		bwin_enh_L				0xc0000
-+#define		bBW_TH					0x700000
-+#define		bED_TH2				0x3800000
-+#define		bBW_option				0x4000000
-+#define		bRatio_TH				0x18000000
-+#define		bWindow_L				0xe0000000
-+#define		bSBD_Option				0x1
-+#define		bFrame_TH				0x1c
-+#define		bFS_Option				0x60
-+#define		bDC_Slope_check		0x80
-+#define		bFGuard_Counter_DC_L	0xe00
-+#define		bFrame_Weight_Short	0x7000
-+#define		bSub_Tune				0xe00000
-+#define		bFrame_DC_Length		0xe000000
-+#define		bSBD_start_offset		0x30000000
-+#define		bFrame_TH_2			0x7
-+#define		bFrame_GI2_TH			0x38
-+#define		bGI2_Sync_en			0x40
-+#define		bSarch_Short_Early		0x300
-+#define		bSarch_Short_Late		0xc00
-+#define		bSarch_GI2_Late		0x70000
-+#define		bCFOAntSum				0x1
-+#define		bCFOAcc				0x2
-+#define		bCFOStartOffset			0xc
-+#define		bCFOLookBack			0x70
-+#define		bCFOSumWeight			0x80
-+#define		bDAGCEnable			0x10000
-+#define		bTXIQImb_A				0x3ff
-+#define		bTXIQImb_B				0xfc00
-+#define		bTXIQImb_C				0x3f0000
-+#define		bTXIQImb_D				0xffc00000
-+#define		bTxIDCOffset			0xff
-+#define		bTxQDCOffset			0xff00
-+#define		bTxDFIRMode			0x10000
-+#define		bTxPesudoNoiseOn		0x4000000
-+#define		bTxPesudoNoise_A		0xff
-+#define		bTxPesudoNoise_B		0xff00
-+#define		bTxPesudoNoise_C		0xff0000
-+#define		bTxPesudoNoise_D		0xff000000
-+#define		bCCADropOption			0x20000
-+#define		bCCADropThres			0xfff00000
-+#define		bEDCCA_H				0xf
-+#define		bEDCCA_L				0xf0
-+#define		bLambda_ED			0x300
-+#define		bRxInitialGain			0x7f
-+#define		bRxAntDivEn				0x80
-+#define		bRxAGCAddressForLNA	0x7f00
-+#define		bRxHighPowerFlow		0x8000
-+#define		bRxAGCFreezeThres		0xc0000
-+#define		bRxFreezeStep_AGC1	0x300000
-+#define		bRxFreezeStep_AGC2	0xc00000
-+#define		bRxFreezeStep_AGC3	0x3000000
-+#define		bRxFreezeStep_AGC0	0xc000000
-+#define		bRxRssi_Cmp_En			0x10000000
-+#define		bRxQuickAGCEn			0x20000000
-+#define		bRxAGCFreezeThresMode	0x40000000
-+#define		bRxOverFlowCheckType	0x80000000
-+#define		bRxAGCShift				0x7f
-+#define		bTRSW_Tri_Only			0x80
-+#define		bPowerThres			0x300
-+#define		bRxAGCEn				0x1
-+#define		bRxAGCTogetherEn		0x2
-+#define		bRxAGCMin				0x4
-+#define		bRxHP_Ini				0x7
-+#define		bRxHP_TRLNA			0x70
-+#define		bRxHP_RSSI				0x700
-+#define		bRxHP_BBP1				0x7000
-+#define		bRxHP_BBP2				0x70000
-+#define		bRxHP_BBP3				0x700000
-+#define		bRSSI_H					0x7f0000     /* the threshold for high power */
-+#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
-+#define		bRxSettle_TRSW			0x7
-+#define		bRxSettle_LNA			0x38
-+#define		bRxSettle_RSSI			0x1c0
-+#define		bRxSettle_BBP			0xe00
-+#define		bRxSettle_RxHP			0x7000
-+#define		bRxSettle_AntSW_RSSI	0x38000
-+#define		bRxSettle_AntSW		0xc0000
-+#define		bRxProcessTime_DAGC	0x300000
-+#define		bRxSettle_HSSI			0x400000
-+#define		bRxProcessTime_BBPPW	0x800000
-+#define		bRxAntennaPowerShift	0x3000000
-+#define		bRSSITableSelect		0xc000000
-+#define		bRxHP_Final				0x7000000
-+#define		bRxHTSettle_BBP			0x7
-+#define		bRxHTSettle_HSSI		0x8
-+#define		bRxHTSettle_RxHP		0x70
-+#define		bRxHTSettle_BBPPW		0x80
-+#define		bRxHTSettle_Idle		0x300
-+#define		bRxHTSettle_Reserved	0x1c00
-+#define		bRxHTRxHPEn			0x8000
-+#define		bRxHTAGCFreezeThres	0x30000
-+#define		bRxHTAGCTogetherEn	0x40000
-+#define		bRxHTAGCMin			0x80000
-+#define		bRxHTAGCEn				0x100000
-+#define		bRxHTDAGCEn			0x200000
-+#define		bRxHTRxHP_BBP			0x1c00000
-+#define		bRxHTRxHP_Final		0xe0000000
-+#define		bRxPWRatioTH			0x3
-+#define		bRxPWRatioEn			0x4
-+#define		bRxMFHold				0x3800
-+#define		bRxPD_Delay_TH1		0x38
-+#define		bRxPD_Delay_TH2		0x1c0
-+#define		bRxPD_DC_COUNT_MAX	0x600
-+/* #define bRxMF_Hold               0x3800 */
-+#define		bRxPD_Delay_TH			0x8000
-+#define		bRxProcess_Delay		0xf0000
-+#define		bRxSearchrange_GI2_Early	0x700000
-+#define		bRxFrame_Guard_Counter_L	0x3800000
-+#define		bRxSGI_Guard_L			0xc000000
-+#define		bRxSGI_Search_L		0x30000000
-+#define		bRxSGI_TH				0xc0000000
-+#define		bDFSCnt0				0xff
-+#define		bDFSCnt1				0xff00
-+#define		bDFSFlag				0xf0000
-+#define		bMFWeightSum			0x300000
-+#define		bMinIdxTH				0x7f000000
-+#define		bDAFormat				0x40000
-+#define		bTxChEmuEnable		0x01000000
-+#define		bTRSWIsolation_A		0x7f
-+#define		bTRSWIsolation_B		0x7f00
-+#define		bTRSWIsolation_C		0x7f0000
-+#define		bTRSWIsolation_D		0x7f000000
-+#define		bExtLNAGain				0x7c00
-+
-+/* 6. PageE(0xE00) */
-+#define		bSTBCEn				0x4	/* Useless */
-+#define		bAntennaMapping		0x10
-+#define		bNss					0x20
-+#define		bCFOAntSumD			0x200
-+#define		bPHYCounterReset		0x8000000
-+#define		bCFOReportGet			0x4000000
-+#define		bOFDMContinueTx		0x10000000
-+#define		bOFDMSingleCarrier		0x20000000
-+#define		bOFDMSingleTone		0x40000000
-+/* #define bRxPath1                 0x01 */
-+/* #define bRxPath2                 0x02 */
-+/* #define bRxPath3                 0x04 */
-+/* #define bRxPath4                 0x08 */
-+/* #define bTxPath1                 0x10 */
-+/* #define bTxPath2                 0x20 */
-+#define		bHTDetect			0x100
-+#define		bCFOEn				0x10000
-+#define		bCFOValue			0xfff00000
-+#define		bSigTone_Re		0x3f
-+#define		bSigTone_Im		0x7f00
-+#define		bCounter_CCA		0xffff
-+#define		bCounter_ParityFail	0xffff0000
-+#define		bCounter_RateIllegal		0xffff
-+#define		bCounter_CRC8Fail	0xffff0000
-+#define		bCounter_MCSNoSupport	0xffff
-+#define		bCounter_FastSync	0xffff
-+#define		bShortCFO			0xfff
-+#define		bShortCFOTLength	12   /* total */
-+#define		bShortCFOFLength	11   /* fraction */
-+#define		bLongCFO			0x7ff
-+#define		bLongCFOTLength	11
-+#define		bLongCFOFLength	11
-+#define		bTailCFO			0x1fff
-+#define		bTailCFOTLength		13
-+#define		bTailCFOFLength		12
-+#define		bmax_en_pwdB		0xffff
-+#define		bCC_power_dB		0xffff0000
-+#define		bnoise_pwdB		0xffff
-+#define		bPowerMeasTLength	10
-+#define		bPowerMeasFLength	3
-+#define		bRx_HT_BW			0x1
-+#define		bRxSC				0x6
-+#define		bRx_HT				0x8
-+#define		bNB_intf_det_on		0x1
-+#define		bIntf_win_len_cfg	0x30
-+#define		bNB_Intf_TH_cfg		0x1c0
-+#define		bRFGain				0x3f
-+#define		bTableSel			0x40
-+#define		bTRSW				0x80
-+#define		bRxSNR_A			0xff
-+#define		bRxSNR_B			0xff00
-+#define		bRxSNR_C			0xff0000
-+#define		bRxSNR_D			0xff000000
-+#define		bSNREVMTLength		8
-+#define		bSNREVMFLength		1
-+#define		bCSI1st				0xff
-+#define		bCSI2nd				0xff00
-+#define		bRxEVM1st			0xff0000
-+#define		bRxEVM2nd			0xff000000
-+#define		bSIGEVM			0xff
-+#define		bPWDB				0xff00
-+#define		bSGIEN				0x10000
-+
-+#define		bSFactorQAM1		0xf	/* Useless */
-+#define		bSFactorQAM2		0xf0
-+#define		bSFactorQAM3		0xf00
-+#define		bSFactorQAM4		0xf000
-+#define		bSFactorQAM5		0xf0000
-+#define		bSFactorQAM6		0xf0000
-+#define		bSFactorQAM7		0xf00000
-+#define		bSFactorQAM8		0xf000000
-+#define		bSFactorQAM9		0xf0000000
-+#define		bCSIScheme			0x100000
-+
-+#define		bNoiseLvlTopSet		0x3	/* Useless */
-+#define		bChSmooth			0x4
-+#define		bChSmoothCfg1		0x38
-+#define		bChSmoothCfg2		0x1c0
-+#define		bChSmoothCfg3		0xe00
-+#define		bChSmoothCfg4		0x7000
-+#define		bMRCMode			0x800000
-+#define		bTHEVMCfg			0x7000000
-+
-+#define		bLoopFitType		0x1	/* Useless */
-+#define		bUpdCFO			0x40
-+#define		bUpdCFOOffData		0x80
-+#define		bAdvUpdCFO			0x100
-+#define		bAdvTimeCtrl		0x800
-+#define		bUpdClko			0x1000
-+#define		bFC					0x6000
-+#define		bTrackingMode		0x8000
-+#define		bPhCmpEnable		0x10000
-+#define		bUpdClkoLTF		0x20000
-+#define		bComChCFO			0x40000
-+#define		bCSIEstiMode		0x80000
-+#define		bAdvUpdEqz			0x100000
-+#define		bUChCfg				0x7000000
-+#define		bUpdEqz			0x8000000
-+
-+/* Rx Pseduo noise */
-+#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
-+#define		bRxPesudoNoise_A		0xff
-+#define		bRxPesudoNoise_B		0xff00
-+#define		bRxPesudoNoise_C		0xff0000
-+#define		bRxPesudoNoise_D		0xff000000
-+#define		bPesudoNoiseState_A	0xffff
-+#define		bPesudoNoiseState_B	0xffff0000
-+#define		bPesudoNoiseState_C	0xffff
-+#define		bPesudoNoiseState_D	0xffff0000
-+
-+/* 7. RF Register
-+ * Zebra1 */
-+#define		bZebra1_HSSIEnable		0x8		/* Useless */
-+#define		bZebra1_TRxControl		0xc00
-+#define		bZebra1_TRxGainSetting	0x07f
-+#define		bZebra1_RxCorner		0xc00
-+#define		bZebra1_TxChargePump	0x38
-+#define		bZebra1_RxChargePump	0x7
-+#define		bZebra1_ChannelNum	0xf80
-+#define		bZebra1_TxLPFBW		0x400
-+#define		bZebra1_RxLPFBW		0x600
-+
-+/* Zebra4 */
-+#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
-+#define		bRTL8256RegModeCtrl0	0x40
-+#define		bRTL8256_TxLPFBW		0x18
-+#define		bRTL8256_RxLPFBW		0x600
-+
-+/* RTL8258 */
-+#define		bRTL8258_TxLPFBW		0xc	/* Useless */
-+#define		bRTL8258_RxLPFBW		0xc00
-+#define		bRTL8258_RSSILPFBW	0xc0
-+
-+
-+/*
-+ * Other Definition
-+ *   */
-+
-+/* byte endable for sb_write */
-+#define		bByte0				0x1	/* Useless */
-+#define		bByte1				0x2
-+#define		bByte2				0x4
-+#define		bByte3				0x8
-+#define		bWord0				0x3
-+#define		bWord1				0xc
-+#define		bDWord				0xf
-+
-+/* for PutRegsetting & GetRegSetting BitMask */
-+#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
-+#define		bMaskByte1			0xff00
-+#define		bMaskByte2			0xff0000
-+#define		bMaskByte3			0xff000000
-+#define		bMaskHWord		0xffff0000
-+#define		bMaskLWord			0x0000ffff
-+#define		bMaskDWord		0xffffffff
-+#define		bMaskH3Bytes		0xffffff00
-+#define		bMask12Bits			0xfff
-+#define		bMaskH4Bits			0xf0000000
-+#define		bMaskOFDM_D		0xffc00000
-+#define		bMaskCCK			0x3f3f3f3f
-+
-+
-+#define		bEnable			0x1	/* Useless */
-+#define		bDisable		0x0
-+
-+#define		LeftAntenna		0x0	/* Useless */
-+#define		RightAntenna	0x1
-+
-+#define		tCheckTxStatus		500   /* 500ms // Useless */
-+#define		tUpdateRxCounter	100   /* 100ms */
-+
-+#define		rateCCK		0	/* Useless */
-+#define		rateOFDM	1
-+#define		rateHT		2
-+
-+/* define Register-End */
-+#define		bPMAC_End			0x1ff	/* Useless */
-+#define		bFPGAPHY0_End		0x8ff
-+#define		bFPGAPHY1_End		0x9ff
-+#define		bCCKPHY0_End		0xaff
-+#define		bOFDMPHY0_End		0xcff
-+#define		bOFDMPHY1_End		0xdff
-+
-+/* define max debug item in each debug page
-+ * #define bMaxItem_FPGA_PHY0        0x9
-+ * #define bMaxItem_FPGA_PHY1        0x3
-+ * #define bMaxItem_PHY_11B          0x16
-+ * #define bMaxItem_OFDM_PHY0        0x29
-+ * #define bMaxItem_OFDM_PHY1        0x0 */
-+
-+#define		bPMACControl		0x0		/* Useless */
-+#define		bWMACControl		0x1
-+#define		bWNICControl		0x2
-+
-+#define		PathA			0x0	/* Useless */
-+#define		PathB			0x1
-+#define		PathC			0x2
-+#define		PathD			0x3
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8710BPwrSeq.h b/drivers/staging/rtl8723cs/include/Hal8710BPwrSeq.h
-new file mode 100644
-index 000000000000..31ad29c794c5
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8710BPwrSeq.h
-@@ -0,0 +1,167 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef REALTEK_POWER_SEQUENCE_8710B
-+#define REALTEK_POWER_SEQUENCE_8710B
-+
-+/* #include "PwrSeqCmd.h" */
-+#include "HalPwrSeqCmd.h"
-+
-+/*
-+	Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd
-+	There are 6 HW Power States:
-+	0: POFF--Power Off
-+	1: PDN--Power Down
-+	2: CARDEMU--Card Emulation
-+	3: ACT--Active Mode
-+	4: LPS--Low Power State
-+	5: SUS--Suspend
-+
-+	The transition from different states are defined below
-+	TRANS_CARDEMU_TO_ACT
-+	TRANS_ACT_TO_CARDEMU
-+	TRANS_CARDEMU_TO_SUS
-+	TRANS_SUS_TO_CARDEMU
-+	TRANS_CARDEMU_TO_PDN
-+	TRANS_ACT_TO_LPS
-+	TRANS_LPS_TO_ACT
-+
-+	TRANS_END
-+*/
-+#define RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS 5
-+#define RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS 4
-+#define RTL8710B_TRANS_CARDEMU_TO_SUS_STEPS 7
-+#define RTL8710B_TRANS_SUS_TO_CARDEMU_STEPS 15
-+#define RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS 15
-+#define RTL8710B_TRANS_PDN_TO_CARDEMU_STEPS 15
-+#define RTL8710B_TRANS_ACT_TO_LPS_STEPS 	15
-+#define RTL8710B_TRANS_LPS_TO_ACT_STEPS 	15	
-+#define RTL8710B_TRANS_ACT_TO_SWLPS_STEPS		22
-+#define RTL8710B_TRANS_SWLPS_TO_ACT_STEPS		15
-+#define RTL8710B_TRANS_END_STEPS		1
-+
-+
-+#define RTL8710B_TRANS_CARDEMU_TO_ACT 														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x005D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*AFE power mode selection:1:  LDO mode ,0:  Power-cut mode*/\
-+	{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\
-+	{0x0056, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x0E},\
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ 
-+
-+	
-+#define RTL8710B_TRANS_ACT_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1|BIT2), 0},/*0x04[24:26] = 0 turn off RF*/	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1), 0},/*0x04[16:17] = 0 BB reset*/	\
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x20[1] = 1 turn off MAC by HW state machine*/	\
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x20[1] = 0 polling until return 0 to disable*/ \
-+
-+
-+#define RTL8710B_TRANS_CARDEMU_TO_SUS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8710B_TRANS_SUS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
-+	
-+
-+#define RTL8710B_TRANS_CARDEMU_TO_CARDDIS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
-+
-+#define RTL8710B_TRANS_CARDDIS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+
-+
-+#define RTL8710B_TRANS_CARDEMU_TO_PDN												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
-+
-+#define RTL8710B_TRANS_PDN_TO_CARDEMU												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
-+
-+#define RTL8710B_TRANS_ACT_TO_LPS														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
-+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
-+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
-+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	
-+
-+
-+#define RTL8710B_TRANS_LPS_TO_ACT															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
-+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
-+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0 	 switch TSF to 40M*/\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
-+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
-+ 
-+#define RTL8710B_TRANS_END															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
-+
-+
-+extern WLAN_PWR_CFG rtl8710B_power_on_flow[RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8710B_radio_off_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8710B_card_disable_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8710B_card_enable_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8710B_suspend_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8710B_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8710B_resume_flow[RTL8710B_TRANS_SUS_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8710B_hwpdn_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8710B_enter_lps_flow[RTL8710B_TRANS_ACT_TO_LPS_STEPS+RTL8710B_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8710B_leave_lps_flow[RTL8710B_TRANS_LPS_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8723BPhyCfg.h b/drivers/staging/rtl8723cs/include/Hal8723BPhyCfg.h
-new file mode 100644
-index 000000000000..0f59b8b243ec
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8723BPhyCfg.h
-@@ -0,0 +1,116 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8723BPHYCFG_H__
-+#define __INC_HAL8723BPHYCFG_H__
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+#define LOOP_LIMIT				5
-+#define MAX_STALL_TIME			50		/* us */
-+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
-+#define MAX_TXPWR_IDX_NMODE_92S	63
-+#define Reset_Cnt_Limit			3
-+
-+#ifdef CONFIG_PCI_HCI
-+	#define MAX_AGGR_NUM	0x0B
-+#else
-+	#define MAX_AGGR_NUM	0x07
-+#endif /* CONFIG_PCI_HCI */
-+
-+
-+/*--------------------------Define Parameters End-------------------------------*/
-+
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+/*------------------------------Define structure End----------------------------*/
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+u32
-+PHY_QueryBBReg_8723B(
-+		PADAPTER	Adapter,
-+		u32		RegAddr,
-+		u32		BitMask
-+);
-+
-+void
-+PHY_SetBBReg_8723B(
-+		PADAPTER	Adapter,
-+		u32		RegAddr,
-+		u32		BitMask,
-+		u32		Data
-+);
-+
-+u32
-+PHY_QueryRFReg_8723B(
-+		PADAPTER			Adapter,
-+		enum rf_path			eRFPath,
-+		u32				RegAddr,
-+		u32				BitMask
-+);
-+
-+void
-+PHY_SetRFReg_8723B(
-+		PADAPTER			Adapter,
-+		enum rf_path			eRFPath,
-+		u32				RegAddr,
-+		u32				BitMask,
-+		u32				Data
-+);
-+
-+/* MAC/BB/RF HAL config */
-+int PHY_BBConfig8723B(PADAPTER	Adapter);
-+
-+int PHY_RFConfig8723B(PADAPTER	Adapter);
-+
-+s32 PHY_MACConfig8723B(PADAPTER padapter);
-+
-+int
-+PHY_ConfigRFWithParaFile_8723B(
-+		PADAPTER			Adapter,
-+		u8					*pFileName,
-+	enum rf_path				eRFPath
-+);
-+
-+void
-+PHY_SetTxPowerIndex_8723B(
-+		PADAPTER			Adapter,
-+		u32					PowerIndex,
-+		enum rf_path			RFPath,
-+		u8					Rate
-+);
-+
-+void
-+PHY_SetTxPowerLevel8723B(
-+		PADAPTER		Adapter,
-+		u8			channel
-+);
-+
-+void
-+PHY_SetSwChnlBWMode8723B(
-+		PADAPTER			Adapter,
-+		u8					channel,
-+		enum channel_width	Bandwidth,
-+		u8					Offset40,
-+		u8					Offset80
-+);
-+
-+void phy_set_rf_path_switch_8723b(
-+		struct dm_struct		*phydm,
-+		bool		bMain
-+);
-+
-+/*--------------------------Exported Function prototype End---------------------*/
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8723BPhyReg.h b/drivers/staging/rtl8723cs/include/Hal8723BPhyReg.h
-new file mode 100644
-index 000000000000..ce485c2ab4be
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8723BPhyReg.h
-@@ -0,0 +1,1131 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8723BPHYREG_H__
-+#define __INC_HAL8723BPHYREG_H__
-+
-+#define		rSYM_WLBT_PAPE_SEL		0x64
-+/*
-+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
-+ * 3. RF register 0x00-2E
-+ * 4. Bit Mask for BB/RF register
-+ * 5. Other defintion for BB/RF R/W
-+ *   */
-+
-+
-+/*
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 1. Page1(0x100)
-+ *   */
-+#define		rPMAC_Reset					0x100
-+#define		rPMAC_TxStart					0x104
-+#define		rPMAC_TxLegacySIG				0x108
-+#define		rPMAC_TxHTSIG1				0x10c
-+#define		rPMAC_TxHTSIG2				0x110
-+#define		rPMAC_PHYDebug				0x114
-+#define		rPMAC_TxPacketNum				0x118
-+#define		rPMAC_TxIdle					0x11c
-+#define		rPMAC_TxMACHeader0			0x120
-+#define		rPMAC_TxMACHeader1			0x124
-+#define		rPMAC_TxMACHeader2			0x128
-+#define		rPMAC_TxMACHeader3			0x12c
-+#define		rPMAC_TxMACHeader4			0x130
-+#define		rPMAC_TxMACHeader5			0x134
-+#define		rPMAC_TxDataType				0x138
-+#define		rPMAC_TxRandomSeed			0x13c
-+#define		rPMAC_CCKPLCPPreamble			0x140
-+#define		rPMAC_CCKPLCPHeader			0x144
-+#define		rPMAC_CCKCRC16				0x148
-+#define		rPMAC_OFDMRxCRC32OK			0x170
-+#define		rPMAC_OFDMRxCRC32Er			0x174
-+#define		rPMAC_OFDMRxParityEr			0x178
-+#define		rPMAC_OFDMRxCRC8Er			0x17c
-+#define		rPMAC_CCKCRxRC16Er			0x180
-+#define		rPMAC_CCKCRxRC32Er			0x184
-+#define		rPMAC_CCKCRxRC32OK			0x188
-+#define		rPMAC_TxStatus					0x18c
-+
-+/*
-+ * 2. Page2(0x200)
-+ *
-+ * The following two definition are only used for USB interface. */
-+#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
-+#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
-+
-+/*
-+ * 3. Page8(0x800)
-+ *   */
-+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
-+
-+#define		rFPGA0_TxInfo				0x804	/* Status report?? */
-+#define		rFPGA0_PSDFunction			0x808
-+
-+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
-+
-+#define		rFPGA0_RFTiming1			0x810	/* Useless now */
-+#define		rFPGA0_RFTiming2			0x814
-+
-+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
-+#define		rFPGA0_XA_HSSIParameter2		0x824
-+#define		rFPGA0_XB_HSSIParameter1		0x828
-+#define		rFPGA0_XB_HSSIParameter2		0x82c
-+#define		rTxAGC_B_Rate18_06				0x830
-+#define		rTxAGC_B_Rate54_24				0x834
-+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
-+#define		rTxAGC_B_Mcs03_Mcs00			0x83c
-+
-+#define		rTxAGC_B_Mcs07_Mcs04			0x848
-+#define		rTxAGC_B_Mcs11_Mcs08			0x84c
-+
-+#define		rFPGA0_XA_LSSIParameter		0x840
-+#define		rFPGA0_XB_LSSIParameter		0x844
-+
-+#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
-+#define		rFPGA0_RFSleepUpParameter		0x854
-+
-+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
-+#define		rFPGA0_XCD_SwitchControl		0x85c
-+
-+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
-+#define		rFPGA0_XB_RFInterfaceOE		0x864
-+
-+#define		rTxAGC_B_Mcs15_Mcs12			0x868
-+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
-+
-+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
-+#define		rFPGA0_XCD_RFInterfaceSW		0x874
-+
-+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
-+#define		rFPGA0_XCD_RFParameter		0x87c
-+
-+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
-+#define		rFPGA0_AnalogParameter2		0x884
-+#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
-+#define		rFPGA0_AnalogParameter4		0x88c
-+
-+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
-+#define		rFPGA0_XB_LSSIReadBack		0x8a4
-+#define		rFPGA0_XC_LSSIReadBack		0x8a8
-+#define		rFPGA0_XD_LSSIReadBack		0x8ac
-+
-+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
-+#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
-+#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
-+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
-+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
-+
-+/*
-+ * 4. Page9(0x900)
-+ *   */
-+#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
-+#define	rFPGA1_TxBlock				0x904	/* Useless now */
-+#define	rFPGA1_DebugSelect			0x908	/* Useless now */
-+#define	rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
-+#define	rDPDT_control				0x92c
-+#define	rfe_ctrl_anta_src				0x930
-+#define	rS0S1_PathSwitch			0x948
-+
-+/*
-+ * 5. PageA(0xA00)
-+ *
-+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
-+#define		rCCK0_System				0xa00
-+
-+#define		rCCK0_AFESetting			0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
-+#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
-+
-+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
-+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
-+
-+#define		rCCK0_RxHP					0xa14
-+
-+#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
-+#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
-+
-+#define		rCCK0_TxFilter1				0xa20
-+#define		rCCK0_TxFilter2				0xa24
-+#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
-+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
-+#define		rCCK0_TRSSIReport		0xa50
-+#define		rCCK0_RxReport            		0xa54  /* 0xa57 */
-+#define		rCCK0_FACounterLower      	0xa5c  /* 0xa5b */
-+#define		rCCK0_FACounterUpper      	0xa58  /* 0xa5c */
-+
-+/*
-+ * PageB(0xB00)
-+ *   */
-+#define rPdp_AntA						0xb00
-+#define rPdp_AntA_4						0xb04
-+#define rPdp_AntA_8						0xb08
-+#define rPdp_AntA_C						0xb0c
-+#define rPdp_AntA_10					0xb10
-+#define rPdp_AntA_14					0xb14
-+#define rPdp_AntA_18					0xb18
-+#define rPdp_AntA_1C					0xb1c
-+#define rPdp_AntA_20					0xb20
-+#define rPdp_AntA_24					0xb24
-+
-+#define rConfig_Pmpd_AntA				0xb28
-+#define rConfig_ram64x16				0xb2c
-+
-+#define rBndA							0xb30
-+#define rHssiPar						0xb34
-+
-+#define rConfig_AntA					0xb68
-+#define rConfig_AntB					0xb6c
-+
-+#define rPdp_AntB						0xb70
-+#define rPdp_AntB_4						0xb74
-+#define rPdp_AntB_8						0xb78
-+#define rPdp_AntB_C						0xb7c
-+#define rPdp_AntB_10					0xb80
-+#define rPdp_AntB_14					0xb84
-+#define rPdp_AntB_18					0xb88
-+#define rPdp_AntB_1C					0xb8c
-+#define rPdp_AntB_20					0xb90
-+#define rPdp_AntB_24					0xb94
-+
-+#define rConfig_Pmpd_AntB				0xb98
-+
-+#define rBndB							0xba0
-+
-+#define rAPK							0xbd8
-+#define rPm_Rx0_AntA					0xbdc
-+#define rPm_Rx1_AntA					0xbe0
-+#define rPm_Rx2_AntA					0xbe4
-+#define rPm_Rx3_AntA					0xbe8
-+#define rPm_Rx0_AntB					0xbec
-+#define rPm_Rx1_AntB					0xbf0
-+#define rPm_Rx2_AntB					0xbf4
-+#define rPm_Rx3_AntB					0xbf8
-+/*
-+ * 6. PageC(0xC00)
-+ *   */
-+#define		rOFDM0_LSTF				0xc00
-+
-+#define		rOFDM0_TRxPathEnable		0xc04
-+#define		rOFDM0_TRMuxPar			0xc08
-+#define		rOFDM0_TRSWIsolation		0xc0c
-+
-+#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
-+#define		rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
-+#define		rOFDM0_XBRxAFE		0xc18
-+#define		rOFDM0_XBRxIQImbalance	0xc1c
-+#define		rOFDM0_XCRxAFE		0xc20
-+#define		rOFDM0_XCRxIQImbalance	0xc24
-+#define		rOFDM0_XDRxAFE		0xc28
-+#define		rOFDM0_XDRxIQImbalance	0xc2c
-+
-+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
-+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
-+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
-+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
-+
-+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
-+#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
-+#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
-+#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
-+
-+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
-+#define		rOFDM0_XAAGCCore2			0xc54
-+#define		rOFDM0_XBAGCCore1			0xc58
-+#define		rOFDM0_XBAGCCore2			0xc5c
-+#define		rOFDM0_XCAGCCore1			0xc60
-+#define		rOFDM0_XCAGCCore2			0xc64
-+#define		rOFDM0_XDAGCCore1			0xc68
-+#define		rOFDM0_XDAGCCore2			0xc6c
-+
-+#define		rOFDM0_AGCParameter1			0xc70
-+#define		rOFDM0_AGCParameter2			0xc74
-+#define		rOFDM0_AGCRSSITable			0xc78
-+#define		rOFDM0_HTSTFAGC				0xc7c
-+
-+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
-+#define		rOFDM0_XATxAFE				0xc84
-+#define		rOFDM0_XBTxIQImbalance		0xc88
-+#define		rOFDM0_XBTxAFE				0xc8c
-+#define		rOFDM0_XCTxIQImbalance		0xc90
-+#define		rOFDM0_XCTxAFE			0xc94
-+#define		rOFDM0_XDTxIQImbalance		0xc98
-+#define		rOFDM0_XDTxAFE				0xc9c
-+
-+#define		rOFDM0_RxIQExtAnta			0xca0
-+#define		rOFDM0_TxCoeff1				0xca4
-+#define		rOFDM0_TxCoeff2				0xca8
-+#define		rOFDM0_TxCoeff3				0xcac
-+#define		rOFDM0_TxCoeff4				0xcb0
-+#define		rOFDM0_TxCoeff5				0xcb4
-+#define		rOFDM0_TxCoeff6				0xcb8
-+#define		rOFDM0_RxHPParameter			0xce0
-+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
-+#define		rOFDM0_FrameSync				0xcf0
-+#define		rOFDM0_DFSReport				0xcf4
-+
-+/*
-+ * 7. PageD(0xD00)
-+ *   */
-+#define		rOFDM1_LSTF					0xd00
-+#define		rOFDM1_TRxPathEnable			0xd04
-+
-+#define		rOFDM1_CFO						0xd08	/* No setting now */
-+#define		rOFDM1_CSI1					0xd10
-+#define		rOFDM1_SBD						0xd14
-+#define		rOFDM1_CSI2					0xd18
-+#define		rOFDM1_CFOTracking			0xd2c
-+#define		rOFDM1_TRxMesaure1			0xd34
-+#define		rOFDM1_IntfDet					0xd3c
-+#define		rOFDM1_PseudoNoiseStateAB		0xd50
-+#define		rOFDM1_PseudoNoiseStateCD		0xd54
-+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
-+
-+#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
-+#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
-+#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
-+
-+#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
-+#define		rOFDM_ShortCFOCD				0xdb0
-+#define		rOFDM_LongCFOAB				0xdb4
-+#define		rOFDM_LongCFOCD				0xdb8
-+#define		rOFDM_TailCFOAB				0xdbc
-+#define		rOFDM_TailCFOCD				0xdc0
-+#define		rOFDM_PWMeasure1		0xdc4
-+#define		rOFDM_PWMeasure2		0xdc8
-+#define		rOFDM_BWReport				0xdcc
-+#define		rOFDM_AGCReport				0xdd0
-+#define		rOFDM_RxSNR					0xdd4
-+#define		rOFDM_RxEVMCSI				0xdd8
-+#define		rOFDM_SIGReport				0xddc
-+
-+
-+/*
-+ * 8. PageE(0xE00)
-+ *   */
-+#define		rTxAGC_A_Rate18_06			0xe00
-+#define		rTxAGC_A_Rate54_24			0xe04
-+#define		rTxAGC_A_CCK1_Mcs32			0xe08
-+#define		rTxAGC_A_Mcs03_Mcs00			0xe10
-+#define		rTxAGC_A_Mcs07_Mcs04			0xe14
-+#define		rTxAGC_A_Mcs11_Mcs08			0xe18
-+#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
-+
-+#define		rFPGA0_IQK					0xe28
-+#define		rTx_IQK_Tone_A				0xe30
-+#define		rRx_IQK_Tone_A				0xe34
-+#define		rTx_IQK_PI_A					0xe38
-+#define		rRx_IQK_PI_A					0xe3c
-+
-+#define		rTx_IQK						0xe40
-+#define		rRx_IQK						0xe44
-+#define		rIQK_AGC_Pts					0xe48
-+#define		rIQK_AGC_Rsp					0xe4c
-+#define		rTx_IQK_Tone_B				0xe50
-+#define		rRx_IQK_Tone_B				0xe54
-+#define		rTx_IQK_PI_B					0xe58
-+#define		rRx_IQK_PI_B					0xe5c
-+#define		rIQK_AGC_Cont				0xe60
-+
-+#define		rBlue_Tooth					0xe6c
-+#define		rRx_Wait_CCA					0xe70
-+#define		rTx_CCK_RFON					0xe74
-+#define		rTx_CCK_BBON				0xe78
-+#define		rTx_OFDM_RFON				0xe7c
-+#define		rTx_OFDM_BBON				0xe80
-+#define		rTx_To_Rx					0xe84
-+#define		rTx_To_Tx					0xe88
-+#define		rRx_CCK						0xe8c
-+
-+#define		rTx_Power_Before_IQK_A		0xe94
-+#define		rTx_Power_After_IQK_A			0xe9c
-+
-+#define		rRx_Power_Before_IQK_A		0xea0
-+#define		rRx_Power_Before_IQK_A_2		0xea4
-+#define		rRx_Power_After_IQK_A			0xea8
-+#define		rRx_Power_After_IQK_A_2		0xeac
-+
-+#define		rTx_Power_Before_IQK_B		0xeb4
-+#define		rTx_Power_After_IQK_B			0xebc
-+
-+#define		rRx_Power_Before_IQK_B		0xec0
-+#define		rRx_Power_Before_IQK_B_2		0xec4
-+#define		rRx_Power_After_IQK_B			0xec8
-+#define		rRx_Power_After_IQK_B_2		0xecc
-+
-+#define		rRx_OFDM					0xed0
-+#define		rRx_Wait_RIFS				0xed4
-+#define		rRx_TO_Rx					0xed8
-+#define		rStandby						0xedc
-+#define		rSleep						0xee0
-+#define		rPMPD_ANAEN				0xeec
-+
-+/*
-+ * 7. RF Register 0x00-0x2E (RF 8256)
-+ * RF-0222D 0x00-3F
-+ *
-+ * Zebra1 */
-+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
-+#define		rZebra1_TRxEnable1				0x1
-+#define		rZebra1_TRxEnable2				0x2
-+#define		rZebra1_AGC					0x4
-+#define		rZebra1_ChargePump			0x5
-+#define		rZebra1_Channel				0x7	/* RF channel switch */
-+
-+/* #endif */
-+#define		rZebra1_TxGain					0x8	/* Useless now */
-+#define		rZebra1_TxLPF					0x9
-+#define		rZebra1_RxLPF					0xb
-+#define		rZebra1_RxHPFCorner			0xc
-+
-+/* Zebra4 */
-+#define		rGlobalCtrl						0	/* Useless now */
-+#define		rRTL8256_TxLPF					19
-+#define		rRTL8256_RxLPF					11
-+
-+/* RTL8258 */
-+#define		rRTL8258_TxLPF					0x11	/* Useless now */
-+#define		rRTL8258_RxLPF					0x13
-+#define		rRTL8258_RSSILPF				0xa
-+
-+/*
-+ * RL6052 Register definition
-+ *   */
-+#define		RF_AC						0x00	/*  */
-+
-+#define		RF_IQADJ_G1				0x01	/*  */
-+#define		RF_IQADJ_G2				0x02	/*  */
-+#define		RF_BS_PA_APSET_G1_G4		0x03
-+#define		RF_BS_PA_APSET_G5_G8		0x04
-+#define		RF_POW_TRSW				0x05	/*  */
-+
-+#define		RF_GAIN_RX					0x06	/*  */
-+#define		RF_GAIN_TX					0x07	/*  */
-+
-+#define		RF_TXM_IDAC				0x08	/*  */
-+#define		RF_IPA_G					0x09	/*  */
-+#define		RF_TXBIAS_G				0x0A
-+#define		RF_TXPA_AG					0x0B
-+#define		RF_IPA_A					0x0C	/*  */
-+#define		RF_TXBIAS_A				0x0D
-+#define		RF_BS_PA_APSET_G9_G11	0x0E
-+#define		RF_BS_IQGEN				0x0F	/*  */
-+
-+#define		RF_MODE1					0x10	/*  */
-+#define		RF_MODE2					0x11	/*  */
-+
-+#define		RF_RX_AGC_HP				0x12	/*  */
-+#define		RF_TX_AGC					0x13	/*  */
-+#define		RF_BIAS						0x14	/*  */
-+#define		RF_IPA						0x15	/*  */
-+#define		RF_TXBIAS					0x16
-+#define		RF_POW_ABILITY			0x17	/*  */
-+#define		RF_MODE_AG				0x18	/*  */
-+#define		rRfChannel					0x18	/* RF channel and BW switch */
-+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
-+#define		RF_TOP						0x19	/*  */
-+
-+#define		RF_RX_G1					0x1A	/*  */
-+#define		RF_RX_G2					0x1B	/*  */
-+
-+#define		RF_RX_BB2					0x1C	/*  */
-+#define		RF_RX_BB1					0x1D	/*  */
-+
-+#define		RF_RCK1					0x1E	/*  */
-+#define		RF_RCK2					0x1F	/*  */
-+
-+#define		RF_TX_G1					0x20	/*  */
-+#define		RF_TX_G2					0x21	/*  */
-+#define		RF_TX_G3					0x22	/*  */
-+
-+#define		RF_TX_BB1					0x23	/*  */
-+
-+#define		RF_T_METER					0x24	/*  */
-+
-+#define		RF_SYN_G1					0x25	/* RF TX Power control */
-+#define		RF_SYN_G2					0x26	/* RF TX Power control */
-+#define		RF_SYN_G3					0x27	/* RF TX Power control */
-+#define		RF_SYN_G4					0x28	/* RF TX Power control */
-+#define		RF_SYN_G5					0x29	/* RF TX Power control */
-+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
-+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
-+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
-+
-+#define		RF_RCK_OS					0x30	/* RF TX PA control */
-+
-+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
-+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
-+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
-+#define	RF_TX_BIAS_A				0x35
-+#define	RF_TX_BIAS_D				0x36
-+#define	RF_LOBF_9					0x38
-+#define 	RF_RXRF_A3					0x3C	/*	 */
-+#define	RF_TRSW					0x3F
-+
-+#define	RF_TXRF_A2					0x41
-+#define	RF_TXPA_G4					0x46
-+#define	RF_TXPA_A4					0x4B
-+#define	RF_0x52					0x52
-+#define	RF_WE_LUT					0xEF
-+#define	RF_S0S1					0xB0
-+
-+/*
-+ * Bit Mask
-+ *
-+ * 1. Page1(0x100) */
-+#define		bBBResetB						0x100	/* Useless now? */
-+#define		bGlobalResetB					0x200
-+#define		bOFDMTxStart					0x4
-+#define		bCCKTxStart						0x8
-+#define		bCRC32Debug					0x100
-+#define		bPMACLoopback					0x10
-+#define		bTxLSIG							0xffffff
-+#define		bOFDMTxRate					0xf
-+#define		bOFDMTxReserved				0x10
-+#define		bOFDMTxLength					0x1ffe0
-+#define		bOFDMTxParity					0x20000
-+#define		bTxHTSIG1						0xffffff
-+#define		bTxHTMCSRate					0x7f
-+#define		bTxHTBW						0x80
-+#define		bTxHTLength					0xffff00
-+#define		bTxHTSIG2						0xffffff
-+#define		bTxHTSmoothing					0x1
-+#define		bTxHTSounding					0x2
-+#define		bTxHTReserved					0x4
-+#define		bTxHTAggreation				0x8
-+#define		bTxHTSTBC						0x30
-+#define		bTxHTAdvanceCoding			0x40
-+#define		bTxHTShortGI					0x80
-+#define		bTxHTNumberHT_LTF			0x300
-+#define		bTxHTCRC8						0x3fc00
-+#define		bCounterReset					0x10000
-+#define		bNumOfOFDMTx					0xffff
-+#define		bNumOfCCKTx					0xffff0000
-+#define		bTxIdleInterval					0xffff
-+#define		bOFDMService					0xffff0000
-+#define		bTxMACHeader					0xffffffff
-+#define		bTxDataInit						0xff
-+#define		bTxHTMode						0x100
-+#define		bTxDataType					0x30000
-+#define		bTxRandomSeed					0xffffffff
-+#define		bCCKTxPreamble					0x1
-+#define		bCCKTxSFD						0xffff0000
-+#define		bCCKTxSIG						0xff
-+#define		bCCKTxService					0xff00
-+#define		bCCKLengthExt					0x8000
-+#define		bCCKTxLength					0xffff0000
-+#define		bCCKTxCRC16					0xffff
-+#define		bCCKTxStatus					0x1
-+#define		bOFDMTxStatus					0x2
-+
-+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
-+
-+/* 2. Page8(0x800) */
-+#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
-+#define		bJapanMode						0x2
-+#define		bCCKTxSC						0x30
-+#define		bCCKEn							0x1000000
-+#define		bOFDMEn						0x2000000
-+
-+#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
-+#define		bOFDMTxDACPhase		0x40000
-+#define		bXATxAGC			0x3f
-+
-+#define		bAntennaSelect		0x0300
-+
-+#define		bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
-+#define		bXCTxAGC			0xf000
-+#define		bXDTxAGC			0xf0000
-+
-+#define		bPAStart                  			0xf0000000	/* Useless now */
-+#define		bTRStart			0x00f00000
-+#define		bRFStart			0x0000f000
-+#define		bBBStart			0x000000f0
-+#define		bBBCCKStart		0x0000000f
-+#define		bPAEnd                    			0xf          /* Reg0x814 */
-+#define		bTREnd			0x0f000000
-+#define		bRFEnd			0x000f0000
-+#define		bCCAMask                  			0x000000f0   /* T2R */
-+#define		bR2RCCAMask		0x00000f00
-+#define		bHSSI_R2TDelay		0xf8000000
-+#define		bHSSI_T2RDelay		0xf80000
-+#define		bContTxHSSI               		0x400     /* chane gain at continue Tx */
-+#define		bIGFromCCK		0x200
-+#define		bAGCAddress		0x3f
-+#define		bRxHPTx			0x7000
-+#define		bRxHPT2R			0x38000
-+#define		bRxHPCCKIni		0xc0000
-+#define		bAGCTxCode		0xc00000
-+#define		bAGCRxCode		0x300000
-+
-+#define		b3WireDataLength          		0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
-+#define		b3WireAddressLength		0x400
-+
-+#define		b3WireRFPowerDown         		0x1	/* Useless now
-+ * #define bHWSISelect		0x8 */
-+#define		b5GPAPEPolarity		0x40000000
-+#define		b2GPAPEPolarity		0x80000000
-+#define		bRFSW_TxDefaultAnt		0x3
-+#define		bRFSW_TxOptionAnt		0x30
-+#define		bRFSW_RxDefaultAnt		0x300
-+#define		bRFSW_RxOptionAnt		0x3000
-+#define		bRFSI_3WireData		0x1
-+#define		bRFSI_3WireClock		0x2
-+#define		bRFSI_3WireLoad		0x4
-+#define		bRFSI_3WireRW		0x8
-+#define		bRFSI_3Wire			0xf
-+
-+#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
-+
-+#define		bRFSI_TRSW                		0x20	/* Useless now */
-+#define		bRFSI_TRSWB		0x40
-+#define		bRFSI_ANTSW		0x100
-+#define		bRFSI_ANTSWB		0x200
-+#define		bRFSI_PAPE			0x400
-+#define		bRFSI_PAPE5G		0x800
-+#define		bBandSelect			0x1
-+#define		bHTSIG2_GI			0x80
-+#define		bHTSIG2_Smoothing		0x01
-+#define		bHTSIG2_Sounding		0x02
-+#define		bHTSIG2_Aggreaton		0x08
-+#define		bHTSIG2_STBC		0x30
-+#define		bHTSIG2_AdvCoding		0x40
-+#define		bHTSIG2_NumOfHTLTF	0x300
-+#define		bHTSIG2_CRC8		0x3fc
-+#define		bHTSIG1_MCS		0x7f
-+#define		bHTSIG1_BandWidth		0x80
-+#define		bHTSIG1_HTLength		0xffff
-+#define		bLSIG_Rate			0xf
-+#define		bLSIG_Reserved		0x10
-+#define		bLSIG_Length		0x1fffe
-+#define		bLSIG_Parity			0x20
-+#define		bCCKRxPhase		0x4
-+
-+#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
-+
-+#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
-+
-+#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
-+
-+#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
-+#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
-+#define		bRegulator0Standby		0x1
-+#define		bRegulatorPLLStandby		0x2
-+#define		bRegulator1Standby		0x4
-+#define		bPLLPowerUp		0x8
-+#define		bDPLLPowerUp		0x10
-+#define		bDA10PowerUp		0x20
-+#define		bAD7PowerUp		0x200
-+#define		bDA6PowerUp		0x2000
-+#define		bXtalPowerUp		0x4000
-+#define		b40MDClkPowerUP		0x8000
-+#define		bDA6DebugMode		0x20000
-+#define		bDA6Swing			0x380000
-+
-+#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
-+
-+#define		b80MClkDelay              		0x18000000	/* Useless */
-+#define		bAFEWatchDogEnable		0x20000000
-+
-+#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
-+#define		bXtalCap23			0x3
-+#define		bXtalCap92x					0x0f000000
-+#define		bXtalCap			0x0f000000
-+
-+#define		bIntDifClkEnable          		0x400	/* Useless */
-+#define		bExtSigClkEnable		0x800
-+#define		bBandgapMbiasPowerUp	0x10000
-+#define		bAD11SHGain		0xc0000
-+#define		bAD11InputRange		0x700000
-+#define		bAD11OPCurrent		0x3800000
-+#define		bIPathLoopback		0x4000000
-+#define		bQPathLoopback		0x8000000
-+#define		bAFELoopback		0x10000000
-+#define		bDA10Swing		0x7e0
-+#define		bDA10Reverse		0x800
-+#define		bDAClkSource		0x1000
-+#define		bAD7InputRange		0x6000
-+#define		bAD7Gain			0x38000
-+#define		bAD7OutputCMMode		0x40000
-+#define		bAD7InputCMMode		0x380000
-+#define		bAD7Current			0xc00000
-+#define		bRegulatorAdjust		0x7000000
-+#define		bAD11PowerUpAtTx		0x1
-+#define		bDA10PSAtTx		0x10
-+#define		bAD11PowerUpAtRx		0x100
-+#define		bDA10PSAtRx		0x1000
-+#define		bCCKRxAGCFormat		0x200
-+#define		bPSDFFTSamplepPoint		0xc000
-+#define		bPSDAverageNum		0x3000
-+#define		bIQPathControl		0xc00
-+#define		bPSDFreq			0x3ff
-+#define		bPSDAntennaPath		0x30
-+#define		bPSDIQSwitch		0x40
-+#define		bPSDRxTrigger		0x400000
-+#define		bPSDTxTrigger		0x80000000
-+#define		bPSDSineToneScale		0x7f000000
-+#define		bPSDReport			0xffff
-+
-+/* 3. Page9(0x900) */
-+#define		bOFDMTxSC                 		0x30000000	/* Useless */
-+#define		bCCKTxOn			0x1
-+#define		bOFDMTxOn		0x2
-+#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
-+#define		bDebugItem                		0xff   /* reset debug page and LWord */
-+#define		bAntL			0x10
-+#define		bAntNonHT				0x100
-+#define		bAntHT1			0x1000
-+#define		bAntHT2			0x10000
-+#define		bAntHT1S1			0x100000
-+#define		bAntNonHTS1		0x1000000
-+
-+/* 4. PageA(0xA00) */
-+#define		bCCKBBMode				0x3	/* Useless */
-+#define		bCCKTxPowerSaving		0x80
-+#define		bCCKRxPowerSaving		0x40
-+
-+#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
-+
-+#define		bCCKScramble			0x8	/* Useless */
-+#define		bCCKAntDiversity		0x8000
-+#define		bCCKCarrierRecovery		0x4000
-+#define		bCCKTxRate				0x3000
-+#define		bCCKDCCancel			0x0800
-+#define		bCCKISICancel			0x0400
-+#define		bCCKMatchFilter			0x0200
-+#define		bCCKEqualizer			0x0100
-+#define		bCCKPreambleDetect		0x800000
-+#define		bCCKFastFalseCCA		0x400000
-+#define		bCCKChEstStart			0x300000
-+#define		bCCKCCACount			0x080000
-+#define		bCCKcs_lim				0x070000
-+#define		bCCKBistMode			0x80000000
-+#define		bCCKCCAMask			0x40000000
-+#define		bCCKTxDACPhase		0x4
-+#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
-+#define		bCCKr_cp_mode0		0x0100
-+#define		bCCKTxDCOffset			0xf0
-+#define		bCCKRxDCOffset			0xf
-+#define		bCCKCCAMode			0xc000
-+#define		bCCKFalseCS_lim			0x3f00
-+#define		bCCKCS_ratio			0xc00000
-+#define		bCCKCorgBit_sel			0x300000
-+#define		bCCKPD_lim				0x0f0000
-+#define		bCCKNewCCA			0x80000000
-+#define		bCCKRxHPofIG			0x8000
-+#define		bCCKRxIG				0x7f00
-+#define		bCCKLNAPolarity			0x800000
-+#define		bCCKRx1stGain			0x7f0000
-+#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
-+#define		bCCKRxAGCSatLevel		0x1f000000
-+#define		bCCKRxAGCSatCount		0xe0
-+#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
-+#define		bCCKFixedRxAGC			0x8000
-+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
-+#define		bCCKAntennaPolarity		0x2000
-+#define		bCCKTxFilterType		0x0c00
-+#define		bCCKRxAGCReportType	0x0300
-+#define		bCCKRxDAGCEn			0x80000000
-+#define		bCCKRxDAGCPeriod		0x20000000
-+#define		bCCKRxDAGCSatLevel		0x1f000000
-+#define		bCCKTimingRecovery		0x800000
-+#define		bCCKTxC0				0x3f0000
-+#define		bCCKTxC1				0x3f000000
-+#define		bCCKTxC2				0x3f
-+#define		bCCKTxC3				0x3f00
-+#define		bCCKTxC4				0x3f0000
-+#define		bCCKTxC5				0x3f000000
-+#define		bCCKTxC6				0x3f
-+#define		bCCKTxC7				0x3f00
-+#define		bCCKDebugPort			0xff0000
-+#define		bCCKDACDebug			0x0f000000
-+#define		bCCKFalseAlarmEnable	0x8000
-+#define		bCCKFalseAlarmRead		0x4000
-+#define		bCCKTRSSI				0x7f
-+#define		bCCKRxAGCReport		0xfe
-+#define		bCCKRxReport_AntSel	0x80000000
-+#define		bCCKRxReport_MFOff		0x40000000
-+#define		bCCKRxRxReport_SQLoss	0x20000000
-+#define		bCCKRxReport_Pktloss	0x10000000
-+#define		bCCKRxReport_Lockedbit	0x08000000
-+#define		bCCKRxReport_RateError	0x04000000
-+#define		bCCKRxReport_RxRate	0x03000000
-+#define		bCCKRxFACounterLower	0xff
-+#define		bCCKRxFACounterUpper	0xff000000
-+#define		bCCKRxHPAGCStart		0xe000
-+#define		bCCKRxHPAGCFinal		0x1c00
-+#define		bCCKRxFalseAlarmEnable	0x8000
-+#define		bCCKFACounterFreeze	0x4000
-+#define		bCCKTxPathSel			0x10000000
-+#define		bCCKDefaultRxPath		0xc000000
-+#define		bCCKOptionRxPath		0x3000000
-+
-+/* 5. PageC(0xC00) */
-+#define		bNumOfSTF				0x3	/* Useless */
-+#define		bShift_L					0xc0
-+#define		bGI_TH					0xc
-+#define		bRxPathA				0x1
-+#define		bRxPathB				0x2
-+#define		bRxPathC				0x4
-+#define		bRxPathD				0x8
-+#define		bTxPathA				0x1
-+#define		bTxPathB				0x2
-+#define		bTxPathC				0x4
-+#define		bTxPathD				0x8
-+#define		bTRSSIFreq				0x200
-+#define		bADCBackoff				0x3000
-+#define		bDFIRBackoff			0xc000
-+#define		bTRSSILatchPhase		0x10000
-+#define		bRxIDCOffset			0xff
-+#define		bRxQDCOffset			0xff00
-+#define		bRxDFIRMode			0x1800000
-+#define		bRxDCNFType			0xe000000
-+#define		bRXIQImb_A				0x3ff
-+#define		bRXIQImb_B				0xfc00
-+#define		bRXIQImb_C				0x3f0000
-+#define		bRXIQImb_D				0xffc00000
-+#define		bDC_dc_Notch			0x60000
-+#define		bRxNBINotch			0x1f000000
-+#define		bPD_TH					0xf
-+#define		bPD_TH_Opt2			0xc000
-+#define		bPWED_TH				0x700
-+#define		bIfMF_Win_L			0x800
-+#define		bPD_Option				0x1000
-+#define		bMF_Win_L				0xe000
-+#define		bBW_Search_L			0x30000
-+#define		bwin_enh_L				0xc0000
-+#define		bBW_TH					0x700000
-+#define		bED_TH2				0x3800000
-+#define		bBW_option				0x4000000
-+#define		bRatio_TH				0x18000000
-+#define		bWindow_L				0xe0000000
-+#define		bSBD_Option				0x1
-+#define		bFrame_TH				0x1c
-+#define		bFS_Option				0x60
-+#define		bDC_Slope_check		0x80
-+#define		bFGuard_Counter_DC_L	0xe00
-+#define		bFrame_Weight_Short	0x7000
-+#define		bSub_Tune				0xe00000
-+#define		bFrame_DC_Length		0xe000000
-+#define		bSBD_start_offset		0x30000000
-+#define		bFrame_TH_2			0x7
-+#define		bFrame_GI2_TH			0x38
-+#define		bGI2_Sync_en			0x40
-+#define		bSarch_Short_Early		0x300
-+#define		bSarch_Short_Late		0xc00
-+#define		bSarch_GI2_Late		0x70000
-+#define		bCFOAntSum				0x1
-+#define		bCFOAcc				0x2
-+#define		bCFOStartOffset			0xc
-+#define		bCFOLookBack			0x70
-+#define		bCFOSumWeight			0x80
-+#define		bDAGCEnable			0x10000
-+#define		bTXIQImb_A				0x3ff
-+#define		bTXIQImb_B				0xfc00
-+#define		bTXIQImb_C				0x3f0000
-+#define		bTXIQImb_D				0xffc00000
-+#define		bTxIDCOffset			0xff
-+#define		bTxQDCOffset			0xff00
-+#define		bTxDFIRMode			0x10000
-+#define		bTxPesudoNoiseOn		0x4000000
-+#define		bTxPesudoNoise_A		0xff
-+#define		bTxPesudoNoise_B		0xff00
-+#define		bTxPesudoNoise_C		0xff0000
-+#define		bTxPesudoNoise_D		0xff000000
-+#define		bCCADropOption			0x20000
-+#define		bCCADropThres			0xfff00000
-+#define		bEDCCA_H				0xf
-+#define		bEDCCA_L				0xf0
-+#define		bLambda_ED			0x300
-+#define		bRxInitialGain			0x7f
-+#define		bRxAntDivEn				0x80
-+#define		bRxAGCAddressForLNA	0x7f00
-+#define		bRxHighPowerFlow		0x8000
-+#define		bRxAGCFreezeThres		0xc0000
-+#define		bRxFreezeStep_AGC1	0x300000
-+#define		bRxFreezeStep_AGC2	0xc00000
-+#define		bRxFreezeStep_AGC3	0x3000000
-+#define		bRxFreezeStep_AGC0	0xc000000
-+#define		bRxRssi_Cmp_En			0x10000000
-+#define		bRxQuickAGCEn			0x20000000
-+#define		bRxAGCFreezeThresMode	0x40000000
-+#define		bRxOverFlowCheckType	0x80000000
-+#define		bRxAGCShift				0x7f
-+#define		bTRSW_Tri_Only			0x80
-+#define		bPowerThres			0x300
-+#define		bRxAGCEn				0x1
-+#define		bRxAGCTogetherEn		0x2
-+#define		bRxAGCMin				0x4
-+#define		bRxHP_Ini				0x7
-+#define		bRxHP_TRLNA			0x70
-+#define		bRxHP_RSSI				0x700
-+#define		bRxHP_BBP1				0x7000
-+#define		bRxHP_BBP2				0x70000
-+#define		bRxHP_BBP3				0x700000
-+#define		bRSSI_H					0x7f0000     /* the threshold for high power */
-+#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
-+#define		bRxSettle_TRSW			0x7
-+#define		bRxSettle_LNA			0x38
-+#define		bRxSettle_RSSI			0x1c0
-+#define		bRxSettle_BBP			0xe00
-+#define		bRxSettle_RxHP			0x7000
-+#define		bRxSettle_AntSW_RSSI	0x38000
-+#define		bRxSettle_AntSW		0xc0000
-+#define		bRxProcessTime_DAGC	0x300000
-+#define		bRxSettle_HSSI			0x400000
-+#define		bRxProcessTime_BBPPW	0x800000
-+#define		bRxAntennaPowerShift	0x3000000
-+#define		bRSSITableSelect		0xc000000
-+#define		bRxHP_Final				0x7000000
-+#define		bRxHTSettle_BBP			0x7
-+#define		bRxHTSettle_HSSI		0x8
-+#define		bRxHTSettle_RxHP		0x70
-+#define		bRxHTSettle_BBPPW		0x80
-+#define		bRxHTSettle_Idle		0x300
-+#define		bRxHTSettle_Reserved	0x1c00
-+#define		bRxHTRxHPEn			0x8000
-+#define		bRxHTAGCFreezeThres	0x30000
-+#define		bRxHTAGCTogetherEn	0x40000
-+#define		bRxHTAGCMin			0x80000
-+#define		bRxHTAGCEn				0x100000
-+#define		bRxHTDAGCEn			0x200000
-+#define		bRxHTRxHP_BBP			0x1c00000
-+#define		bRxHTRxHP_Final		0xe0000000
-+#define		bRxPWRatioTH			0x3
-+#define		bRxPWRatioEn			0x4
-+#define		bRxMFHold				0x3800
-+#define		bRxPD_Delay_TH1		0x38
-+#define		bRxPD_Delay_TH2		0x1c0
-+#define		bRxPD_DC_COUNT_MAX	0x600
-+/* #define bRxMF_Hold               0x3800 */
-+#define		bRxPD_Delay_TH			0x8000
-+#define		bRxProcess_Delay		0xf0000
-+#define		bRxSearchrange_GI2_Early	0x700000
-+#define		bRxFrame_Guard_Counter_L	0x3800000
-+#define		bRxSGI_Guard_L			0xc000000
-+#define		bRxSGI_Search_L		0x30000000
-+#define		bRxSGI_TH				0xc0000000
-+#define		bDFSCnt0				0xff
-+#define		bDFSCnt1				0xff00
-+#define		bDFSFlag				0xf0000
-+#define		bMFWeightSum			0x300000
-+#define		bMinIdxTH				0x7f000000
-+#define		bDAFormat				0x40000
-+#define		bTxChEmuEnable		0x01000000
-+#define		bTRSWIsolation_A		0x7f
-+#define		bTRSWIsolation_B		0x7f00
-+#define		bTRSWIsolation_C		0x7f0000
-+#define		bTRSWIsolation_D		0x7f000000
-+#define		bExtLNAGain				0x7c00
-+
-+/* 6. PageE(0xE00) */
-+#define		bSTBCEn				0x4	/* Useless */
-+#define		bAntennaMapping		0x10
-+#define		bNss					0x20
-+#define		bCFOAntSumD			0x200
-+#define		bPHYCounterReset		0x8000000
-+#define		bCFOReportGet			0x4000000
-+#define		bOFDMContinueTx		0x10000000
-+#define		bOFDMSingleCarrier		0x20000000
-+#define		bOFDMSingleTone		0x40000000
-+/* #define bRxPath1                 0x01 */
-+/* #define bRxPath2                 0x02 */
-+/* #define bRxPath3                 0x04 */
-+/* #define bRxPath4                 0x08 */
-+/* #define bTxPath1                 0x10 */
-+/* #define bTxPath2                 0x20 */
-+#define		bHTDetect			0x100
-+#define		bCFOEn				0x10000
-+#define		bCFOValue			0xfff00000
-+#define		bSigTone_Re		0x3f
-+#define		bSigTone_Im		0x7f00
-+#define		bCounter_CCA		0xffff
-+#define		bCounter_ParityFail	0xffff0000
-+#define		bCounter_RateIllegal		0xffff
-+#define		bCounter_CRC8Fail	0xffff0000
-+#define		bCounter_MCSNoSupport	0xffff
-+#define		bCounter_FastSync	0xffff
-+#define		bShortCFO			0xfff
-+#define		bShortCFOTLength	12   /* total */
-+#define		bShortCFOFLength	11   /* fraction */
-+#define		bLongCFO			0x7ff
-+#define		bLongCFOTLength	11
-+#define		bLongCFOFLength	11
-+#define		bTailCFO			0x1fff
-+#define		bTailCFOTLength		13
-+#define		bTailCFOFLength		12
-+#define		bmax_en_pwdB		0xffff
-+#define		bCC_power_dB		0xffff0000
-+#define		bnoise_pwdB		0xffff
-+#define		bPowerMeasTLength	10
-+#define		bPowerMeasFLength	3
-+#define		bRx_HT_BW			0x1
-+#define		bRxSC				0x6
-+#define		bRx_HT				0x8
-+#define		bNB_intf_det_on		0x1
-+#define		bIntf_win_len_cfg	0x30
-+#define		bNB_Intf_TH_cfg		0x1c0
-+#define		bRFGain				0x3f
-+#define		bTableSel			0x40
-+#define		bTRSW				0x80
-+#define		bRxSNR_A			0xff
-+#define		bRxSNR_B			0xff00
-+#define		bRxSNR_C			0xff0000
-+#define		bRxSNR_D			0xff000000
-+#define		bSNREVMTLength		8
-+#define		bSNREVMFLength		1
-+#define		bCSI1st				0xff
-+#define		bCSI2nd				0xff00
-+#define		bRxEVM1st			0xff0000
-+#define		bRxEVM2nd			0xff000000
-+#define		bSIGEVM			0xff
-+#define		bPWDB				0xff00
-+#define		bSGIEN				0x10000
-+
-+#define		bSFactorQAM1		0xf	/* Useless */
-+#define		bSFactorQAM2		0xf0
-+#define		bSFactorQAM3		0xf00
-+#define		bSFactorQAM4		0xf000
-+#define		bSFactorQAM5		0xf0000
-+#define		bSFactorQAM6		0xf0000
-+#define		bSFactorQAM7		0xf00000
-+#define		bSFactorQAM8		0xf000000
-+#define		bSFactorQAM9		0xf0000000
-+#define		bCSIScheme			0x100000
-+
-+#define		bNoiseLvlTopSet		0x3	/* Useless */
-+#define		bChSmooth			0x4
-+#define		bChSmoothCfg1		0x38
-+#define		bChSmoothCfg2		0x1c0
-+#define		bChSmoothCfg3		0xe00
-+#define		bChSmoothCfg4		0x7000
-+#define		bMRCMode			0x800000
-+#define		bTHEVMCfg			0x7000000
-+
-+#define		bLoopFitType		0x1	/* Useless */
-+#define		bUpdCFO			0x40
-+#define		bUpdCFOOffData		0x80
-+#define		bAdvUpdCFO			0x100
-+#define		bAdvTimeCtrl		0x800
-+#define		bUpdClko			0x1000
-+#define		bFC					0x6000
-+#define		bTrackingMode		0x8000
-+#define		bPhCmpEnable		0x10000
-+#define		bUpdClkoLTF		0x20000
-+#define		bComChCFO			0x40000
-+#define		bCSIEstiMode		0x80000
-+#define		bAdvUpdEqz			0x100000
-+#define		bUChCfg				0x7000000
-+#define		bUpdEqz			0x8000000
-+
-+/* Rx Pseduo noise */
-+#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
-+#define		bRxPesudoNoise_A		0xff
-+#define		bRxPesudoNoise_B		0xff00
-+#define		bRxPesudoNoise_C		0xff0000
-+#define		bRxPesudoNoise_D		0xff000000
-+#define		bPesudoNoiseState_A	0xffff
-+#define		bPesudoNoiseState_B	0xffff0000
-+#define		bPesudoNoiseState_C	0xffff
-+#define		bPesudoNoiseState_D	0xffff0000
-+
-+/* 7. RF Register
-+ * Zebra1 */
-+#define		bZebra1_HSSIEnable		0x8		/* Useless */
-+#define		bZebra1_TRxControl		0xc00
-+#define		bZebra1_TRxGainSetting	0x07f
-+#define		bZebra1_RxCorner		0xc00
-+#define		bZebra1_TxChargePump	0x38
-+#define		bZebra1_RxChargePump	0x7
-+#define		bZebra1_ChannelNum	0xf80
-+#define		bZebra1_TxLPFBW		0x400
-+#define		bZebra1_RxLPFBW		0x600
-+
-+/* Zebra4 */
-+#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
-+#define		bRTL8256RegModeCtrl0	0x40
-+#define		bRTL8256_TxLPFBW		0x18
-+#define		bRTL8256_RxLPFBW		0x600
-+
-+/* RTL8258 */
-+#define		bRTL8258_TxLPFBW		0xc	/* Useless */
-+#define		bRTL8258_RxLPFBW		0xc00
-+#define		bRTL8258_RSSILPFBW	0xc0
-+
-+
-+/*
-+ * Other Definition
-+ *   */
-+
-+/* byte endable for sb_write */
-+#define		bByte0				0x1	/* Useless */
-+#define		bByte1				0x2
-+#define		bByte2				0x4
-+#define		bByte3				0x8
-+#define		bWord0				0x3
-+#define		bWord1				0xc
-+#define		bDWord				0xf
-+
-+/* for PutRegsetting & GetRegSetting BitMask */
-+#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
-+#define		bMaskByte1			0xff00
-+#define		bMaskByte2			0xff0000
-+#define		bMaskByte3			0xff000000
-+#define		bMaskHWord		0xffff0000
-+#define		bMaskLWord			0x0000ffff
-+#define		bMaskDWord		0xffffffff
-+#define		bMaskH3Bytes		0xffffff00
-+#define		bMask12Bits			0xfff
-+#define		bMaskH4Bits			0xf0000000
-+#define		bMaskOFDM_D		0xffc00000
-+#define		bMaskCCK			0x3f3f3f3f
-+
-+
-+#define		bEnable			0x1	/* Useless */
-+#define		bDisable		0x0
-+
-+#define		LeftAntenna		0x0	/* Useless */
-+#define		RightAntenna	0x1
-+
-+#define		tCheckTxStatus		500   /* 500ms */ /* Useless */
-+#define		tUpdateRxCounter	100   /* 100ms */
-+
-+#define		rateCCK		0	/* Useless */
-+#define		rateOFDM	1
-+#define		rateHT		2
-+
-+/* define Register-End */
-+#define		bPMAC_End			0x1ff	/* Useless */
-+#define		bFPGAPHY0_End		0x8ff
-+#define		bFPGAPHY1_End		0x9ff
-+#define		bCCKPHY0_End		0xaff
-+#define		bOFDMPHY0_End		0xcff
-+#define		bOFDMPHY1_End		0xdff
-+
-+/* define max debug item in each debug page
-+ * #define bMaxItem_FPGA_PHY0        0x9
-+ * #define bMaxItem_FPGA_PHY1        0x3
-+ * #define bMaxItem_PHY_11B          0x16
-+ * #define bMaxItem_OFDM_PHY0        0x29
-+ * #define bMaxItem_OFDM_PHY1        0x0 */
-+
-+#define		bPMACControl		0x0		/* Useless */
-+#define		bWMACControl		0x1
-+#define		bWNICControl		0x2
-+
-+#define		PathA			0x0	/* Useless */
-+#define		PathB			0x1
-+#define		PathC			0x2
-+#define		PathD			0x3
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8723BPwrSeq.h b/drivers/staging/rtl8723cs/include/Hal8723BPwrSeq.h
-new file mode 100644
-index 000000000000..1aec885cbb1d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8723BPwrSeq.h
-@@ -0,0 +1,246 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef REALTEK_POWER_SEQUENCE_8723B
-+#define REALTEK_POWER_SEQUENCE_8723B
-+
-+#include "HalPwrSeqCmd.h"
-+
-+/*
-+	Check document WM-20130815-JackieLau-RTL8723B_Power_Architecture v08.vsd
-+	There are 6 HW Power States:
-+	0: POFF--Power Off
-+	1: PDN--Power Down
-+	2: CARDEMU--Card Emulation
-+	3: ACT--Active Mode
-+	4: LPS--Low Power State
-+	5: SUS--Suspend
-+
-+	The transision from different states are defined below
-+	TRANS_CARDEMU_TO_ACT
-+	TRANS_ACT_TO_CARDEMU
-+	TRANS_CARDEMU_TO_SUS
-+	TRANS_SUS_TO_CARDEMU
-+	TRANS_CARDEMU_TO_PDN
-+	TRANS_ACT_TO_LPS
-+	TRANS_LPS_TO_ACT
-+
-+	TRANS_END
-+*/
-+#define	RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS	26
-+#define	RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS	15
-+#define	RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS	15
-+#define	RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS	15
-+#define	RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS	15
-+#define	RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS	15
-+#define	RTL8723B_TRANS_ACT_TO_LPS_STEPS		15
-+#define	RTL8723B_TRANS_LPS_TO_ACT_STEPS		15
-+#define	RTL8723B_TRANS_ACT_TO_SWLPS_STEPS		22
-+#define	RTL8723B_TRANS_SWLPS_TO_ACT_STEPS		15
-+#define	RTL8723B_TRANS_END_STEPS		1
-+
-+
-+#define RTL8723B_TRANS_CARDEMU_TO_ACT														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \
-+	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
-+	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
-+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/	\
-+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
-+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
-+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/	\
-+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
-+	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
-+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
-+	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
-+	{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
-+	{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\
-+	{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
-+
-+
-+#define RTL8723B_TRANS_ACT_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
-+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
-+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\
-+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
-+
-+
-+#define RTL8723B_TRANS_CARDEMU_TO_SUS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8723B_TRANS_SUS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
-+
-+#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
-+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
-+
-+
-+#define RTL8723B_TRANS_CARDEMU_TO_PDN												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
-+
-+#define RTL8723B_TRANS_PDN_TO_CARDEMU												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
-+
-+#define RTL8723B_TRANS_ACT_TO_LPS														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
-+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
-+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
-+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
-+
-+
-+#define RTL8723B_TRANS_LPS_TO_ACT															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
-+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
-+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
-+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
-+
-+
-+#define RTL8723B_TRANS_ACT_TO_SWLPS														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable 32 K source*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/	\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*disable security engine*/	\
-+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x40},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
-+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TSF*/	\
-+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/	\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*Reset MCUFWDL register*/	\
-+	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/	\
-+	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*Reset CPU IO Wrapper*/	\
-+	{0x0287, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*polling RXFF packet number = 0 */	\
-+	{0x0286, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA idle */	\
-+	{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Clear FW RPWM interrupt */\
-+	{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW RPWM interrupt source*/\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to 32K*/\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF stable*/\
-+	{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW LPS*/	\
-+	{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/*polling FW LPS ready */
-+
-+
-+#define RTL8723B_TRANS_SWLPS_TO_ACT															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*switch TSF to 32K*/\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1, enable security engine*/\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
-+	{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x09}, /*.	reset MAC rx state machine*/\
-+	{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x86}, /*.	reset MAC rx state machine*/\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/	\
-+	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/	\
-+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/	\
-+	{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/	\
-+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/	\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */	\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
-+
-+#define RTL8723B_TRANS_END															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
-+
-+
-+	extern WLAN_PWR_CFG rtl8723B_power_on_flow[RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723B_radio_off_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723B_card_disable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723B_card_enable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723B_suspend_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723B_resume_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723B_hwpdn_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723B_enter_lps_flow[RTL8723B_TRANS_ACT_TO_LPS_STEPS + RTL8723B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723B_leave_lps_flow[RTL8723B_TRANS_LPS_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723B_enter_swlps_flow[RTL8723B_TRANS_ACT_TO_SWLPS_STEPS + RTL8723B_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723B_leave_swlps_flow[RTL8723B_TRANS_SWLPS_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8723DPhyCfg.h b/drivers/staging/rtl8723cs/include/Hal8723DPhyCfg.h
-new file mode 100644
-index 000000000000..b8924355138b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8723DPhyCfg.h
-@@ -0,0 +1,115 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8723DPHYCFG_H__
-+#define __INC_HAL8723DPHYCFG_H__
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+#define LOOP_LIMIT				5
-+#define MAX_STALL_TIME			50		/* us */
-+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
-+#define MAX_TXPWR_IDX_NMODE_92S	63
-+#define Reset_Cnt_Limit			3
-+
-+#ifdef CONFIG_PCI_HCI
-+	#define MAX_AGGR_NUM	0x0B
-+#else
-+	#define MAX_AGGR_NUM	0x07
-+#endif /* CONFIG_PCI_HCI */
-+
-+
-+/*--------------------------Define Parameters End-------------------------------*/
-+
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+/*------------------------------Define structure End----------------------------*/
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+u32
-+PHY_QueryBBReg_8723D(
-+		PADAPTER	Adapter,
-+		u32		RegAddr,
-+		u32		BitMask
-+);
-+
-+void
-+PHY_SetBBReg_8723D(
-+		PADAPTER	Adapter,
-+		u32		RegAddr,
-+		u32		BitMask,
-+		u32		Data
-+);
-+
-+u32
-+PHY_QueryRFReg_8723D(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				RegAddr,
-+		u32				BitMask
-+);
-+
-+void
-+PHY_SetRFReg_8723D(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				RegAddr,
-+		u32				BitMask,
-+		u32				Data
-+);
-+
-+/* MAC/BB/RF HAL config */
-+int PHY_BBConfig8723D(PADAPTER	Adapter);
-+
-+int PHY_RFConfig8723D(PADAPTER	Adapter);
-+
-+s32 PHY_MACConfig8723D(PADAPTER padapter);
-+
-+int
-+PHY_ConfigRFWithParaFile_8723D(
-+		PADAPTER			Adapter,
-+		u8				*pFileName,
-+	enum rf_path				eRFPath
-+);
-+
-+void
-+PHY_SetTxPowerIndex_8723D(
-+		PADAPTER			Adapter,
-+		u32					PowerIndex,
-+		enum rf_path			RFPath,
-+		u8					Rate
-+);
-+
-+void
-+PHY_SetTxPowerLevel8723D(
-+		PADAPTER		Adapter,
-+		u8			channel
-+);
-+
-+void
-+PHY_SetSwChnlBWMode8723D(
-+		PADAPTER			Adapter,
-+		u8					channel,
-+		enum channel_width	Bandwidth,
-+		u8					Offset40,
-+		u8					Offset80
-+);
-+
-+void phy_set_rf_path_switch_8723d(
-+		struct dm_struct		*phydm,
-+		bool		bMain
-+);
-+/*--------------------------Exported Function prototype End---------------------*/
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8723DPhyReg.h b/drivers/staging/rtl8723cs/include/Hal8723DPhyReg.h
-new file mode 100644
-index 000000000000..036144a388bb
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8723DPhyReg.h
-@@ -0,0 +1,1134 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8723DPHYREG_H__
-+#define __INC_HAL8723DPHYREG_H__
-+
-+#define		rSYM_WLBT_PAPE_SEL		0x64
-+/*
-+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
-+ * 3. RF register 0x00-2E
-+ * 4. Bit Mask for BB/RF register
-+ * 5. Other definition for BB/RF R/W
-+ *   */
-+
-+
-+/*
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 1. Page1(0x100)
-+ *   */
-+#define		rPMAC_Reset					0x100
-+#define		rPMAC_TxStart					0x104
-+#define		rPMAC_TxLegacySIG				0x108
-+#define		rPMAC_TxHTSIG1				0x10c
-+#define		rPMAC_TxHTSIG2				0x110
-+#define		rPMAC_PHYDebug				0x114
-+#define		rPMAC_TxPacketNum				0x118
-+#define		rPMAC_TxIdle					0x11c
-+#define		rPMAC_TxMACHeader0			0x120
-+#define		rPMAC_TxMACHeader1			0x124
-+#define		rPMAC_TxMACHeader2			0x128
-+#define		rPMAC_TxMACHeader3			0x12c
-+#define		rPMAC_TxMACHeader4			0x130
-+#define		rPMAC_TxMACHeader5			0x134
-+#define		rPMAC_TxDataType				0x138
-+#define		rPMAC_TxRandomSeed			0x13c
-+#define		rPMAC_CCKPLCPPreamble			0x140
-+#define		rPMAC_CCKPLCPHeader			0x144
-+#define		rPMAC_CCKCRC16				0x148
-+#define		rPMAC_OFDMRxCRC32OK			0x170
-+#define		rPMAC_OFDMRxCRC32Er			0x174
-+#define		rPMAC_OFDMRxParityEr			0x178
-+#define		rPMAC_OFDMRxCRC8Er			0x17c
-+#define		rPMAC_CCKCRxRC16Er			0x180
-+#define		rPMAC_CCKCRxRC32Er			0x184
-+#define		rPMAC_CCKCRxRC32OK			0x188
-+#define		rPMAC_TxStatus					0x18c
-+
-+/*
-+ * 2. Page2(0x200)
-+ *
-+ * The following two definition are only used for USB interface. */
-+#define		RF_BB_CMD_ADDR				0x02c0	/* RF/BB read/write command address. */
-+#define		RF_BB_CMD_DATA				0x02c4	/* RF/BB read/write command data. */
-+
-+/*
-+ * 3. Page8(0x800)
-+ *   */
-+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC // RF BW Setting?? */
-+
-+#define		rFPGA0_TxInfo				0x804	/* Status report?? */
-+#define		rFPGA0_PSDFunction			0x808
-+
-+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
-+
-+#define		rFPGA0_RFTiming1			0x810	/* Useless now */
-+#define		rFPGA0_RFTiming2			0x814
-+
-+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
-+#define		rFPGA0_XA_HSSIParameter2		0x824
-+#define		rFPGA0_XB_HSSIParameter1		0x828
-+#define		rFPGA0_XB_HSSIParameter2		0x82c
-+#define		rTxAGC_B_Rate18_06				0x830
-+#define		rTxAGC_B_Rate54_24				0x834
-+#define		rTxAGC_B_CCK1_55_Mcs32		0x838
-+#define		rTxAGC_B_Mcs03_Mcs00			0x83c
-+
-+#define		rTxAGC_B_Mcs07_Mcs04			0x848
-+#define		rTxAGC_B_Mcs11_Mcs08			0x84c
-+
-+#define		rFPGA0_XA_LSSIParameter		0x840
-+#define		rFPGA0_XB_LSSIParameter		0x844
-+
-+#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
-+#define		rFPGA0_RFSleepUpParameter		0x854
-+
-+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
-+#define		rFPGA0_XCD_SwitchControl		0x85c
-+
-+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
-+#define		rFPGA0_XB_RFInterfaceOE		0x864
-+
-+#define		rTxAGC_B_Mcs15_Mcs12			0x868
-+#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c
-+
-+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
-+#define		rFPGA0_XCD_RFInterfaceSW		0x874
-+
-+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
-+#define		rFPGA0_XCD_RFParameter		0x87c
-+
-+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
-+#define		rFPGA0_AnalogParameter2		0x884
-+#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
-+#define		rFPGA0_AnalogParameter4		0x88c
-+
-+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
-+#define		rFPGA0_XB_LSSIReadBack		0x8a4
-+#define		rFPGA0_XC_LSSIReadBack		0x8a8
-+#define		rFPGA0_XD_LSSIReadBack		0x8ac
-+
-+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
-+#define		TransceiverA_HSPI_Readback	0x8b8	/* Transceiver A HSPI Readback */
-+#define		TransceiverB_HSPI_Readback	0x8bc	/* Transceiver B HSPI Readback */
-+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now // RF Interface Readback Value */
-+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
-+
-+/*
-+ * 4. Page9(0x900)
-+ *   */
-+#define	rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC // RF BW Setting?? */
-+#define	rFPGA1_TxBlock				0x904	/* Useless now */
-+#define	rFPGA1_DebugSelect			0x908	/* Useless now */
-+#define	rFPGA1_TxInfo				0x90c	/* Useless now // Status report?? */
-+#define	rDPDT_control				0x92c
-+#define	rfe_ctrl_anta_src				0x930
-+#define	rS0S1_PathSwitch			0x948
-+#define	rBBrx_DFIR					0x954
-+
-+/*
-+ * 5. PageA(0xA00)
-+ *
-+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
-+#define		rCCK0_System				0xa00
-+
-+#define		rCCK0_AFESetting			0xa04	/* Disable init gain now // Select RX path by RSSI */
-+#define		rCCK0_CCA					0xa08	/* Disable init gain now // Init gain */
-+
-+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
-+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
-+
-+#define		rCCK0_RxHP					0xa14
-+
-+#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
-+#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
-+
-+#define		rCCK0_TxFilter1				0xa20
-+#define		rCCK0_TxFilter2				0xa24
-+#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
-+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
-+#define		rCCK0_TRSSIReport		0xa50
-+#define		rCCK0_RxReport			0xa54  /* 0xa57 */
-+#define		rCCK0_FACounterLower		0xa5c  /* 0xa5b */
-+#define		rCCK0_FACounterUpper		0xa58  /* 0xa5c */
-+
-+/*
-+ * PageB(0xB00)
-+ *   */
-+#define rPdp_AntA						0xb00
-+#define rPdp_AntA_4						0xb04
-+#define rPdp_AntA_8						0xb08
-+#define rPdp_AntA_C						0xb0c
-+#define rPdp_AntA_10					0xb10
-+#define rPdp_AntA_14					0xb14
-+#define rPdp_AntA_18					0xb18
-+#define rPdp_AntA_1C					0xb1c
-+#define rPdp_AntA_20					0xb20
-+#define rPdp_AntA_24					0xb24
-+
-+#define rConfig_Pmpd_AntA				0xb28
-+#define rConfig_ram64x16				0xb2c
-+
-+#define rBndA							0xb30
-+#define rHssiPar						0xb34
-+
-+#define rConfig_AntA					0xb68
-+#define rConfig_AntB					0xb6c
-+
-+#define rPdp_AntB						0xb70
-+#define rPdp_AntB_4						0xb74
-+#define rPdp_AntB_8						0xb78
-+#define rPdp_AntB_C						0xb7c
-+#define rPdp_AntB_10					0xb80
-+#define rPdp_AntB_14					0xb84
-+#define rPdp_AntB_18					0xb88
-+#define rPdp_AntB_1C					0xb8c
-+#define rPdp_AntB_20					0xb90
-+#define rPdp_AntB_24					0xb94
-+
-+#define rConfig_Pmpd_AntB				0xb98
-+
-+#define rBndB							0xba0
-+
-+#define rAPK							0xbd8
-+#define rPm_Rx0_AntA					0xbdc
-+#define rPm_Rx1_AntA					0xbe0
-+#define rPm_Rx2_AntA					0xbe4
-+#define rPm_Rx3_AntA					0xbe8
-+#define rPm_Rx0_AntB					0xbec
-+#define rPm_Rx1_AntB					0xbf0
-+#define rPm_Rx2_AntB					0xbf4
-+#define rPm_Rx3_AntB					0xbf8
-+/*
-+ * 6. PageC(0xC00)
-+ *   */
-+#define		rOFDM0_LSTF				0xc00
-+
-+#define		rOFDM0_TRxPathEnable		0xc04
-+#define		rOFDM0_TRMuxPar			0xc08
-+#define		rOFDM0_TRSWIsolation		0xc0c
-+
-+#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
-+#define		rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imbalance matrix */
-+#define		rOFDM0_XBRxAFE		0xc18
-+#define		rOFDM0_XBRxIQImbalance	0xc1c
-+#define		rOFDM0_XCRxAFE		0xc20
-+#define		rOFDM0_XCRxIQImbalance	0xc24
-+#define		rOFDM0_XDRxAFE		0xc28
-+#define		rOFDM0_XDRxIQImbalance	0xc2c
-+
-+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	// DM tune init gain */
-+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
-+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
-+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
-+
-+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
-+#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
-+#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
-+#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
-+
-+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG */
-+#define		rOFDM0_XAAGCCore2			0xc54
-+#define		rOFDM0_XBAGCCore1			0xc58
-+#define		rOFDM0_XBAGCCore2			0xc5c
-+#define		rOFDM0_XCAGCCore1			0xc60
-+#define		rOFDM0_XCAGCCore2			0xc64
-+#define		rOFDM0_XDAGCCore1			0xc68
-+#define		rOFDM0_XDAGCCore2			0xc6c
-+
-+#define		rOFDM0_AGCParameter1			0xc70
-+#define		rOFDM0_AGCParameter2			0xc74
-+#define		rOFDM0_AGCRSSITable			0xc78
-+#define		rOFDM0_HTSTFAGC				0xc7c
-+
-+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
-+#define		rOFDM0_XATxAFE				0xc84
-+#define		rOFDM0_XBTxIQImbalance		0xc88
-+#define		rOFDM0_XBTxAFE				0xc8c
-+#define		rOFDM0_XCTxIQImbalance		0xc90
-+#define		rOFDM0_XCTxAFE			0xc94
-+#define		rOFDM0_XDTxIQImbalance		0xc98
-+#define		rOFDM0_XDTxAFE				0xc9c
-+
-+#define		rOFDM0_RxIQExtAnta			0xca0
-+#define		rOFDM0_TxCoeff1				0xca4
-+#define		rOFDM0_TxCoeff2				0xca8
-+#define		rOFDM0_TxCoeff3				0xcac
-+#define		rOFDM0_TxCoeff4				0xcb0
-+#define		rOFDM0_TxCoeff5				0xcb4
-+#define		rOFDM0_TxCoeff6				0xcb8
-+#define		rOFDM0_RxHPParameter			0xce0
-+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
-+#define		rOFDM0_FrameSync				0xcf0
-+#define		rOFDM0_DFSReport				0xcf4
-+
-+/*
-+ * 7. PageD(0xD00)
-+ *   */
-+#define		rOFDM1_LSTF					0xd00
-+#define		rOFDM1_TRxPathEnable			0xd04
-+
-+#define		rOFDM1_CFO						0xd08	/* No setting now */
-+#define		rOFDM1_CSI1					0xd10
-+#define		rOFDM1_SBD						0xd14
-+#define		rOFDM1_CSI2					0xd18
-+#define		rOFDM1_CFOTracking			0xd2c
-+#define		rOFDM1_TRxMesaure1			0xd34
-+#define		rOFDM1_IntfDet					0xd3c
-+#define		rOFDM1_PseudoNoiseStateAB		0xd50
-+#define		rOFDM1_PseudoNoiseStateCD		0xd54
-+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
-+
-+#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
-+#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
-+#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
-+
-+#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
-+#define		rOFDM_ShortCFOCD				0xdb0
-+#define		rOFDM_LongCFOAB				0xdb4
-+#define		rOFDM_LongCFOCD				0xdb8
-+#define		rOFDM_TailCFOAB				0xdbc
-+#define		rOFDM_TailCFOCD				0xdc0
-+#define		rOFDM_PWMeasure1		0xdc4
-+#define		rOFDM_PWMeasure2		0xdc8
-+#define		rOFDM_BWReport				0xdcc
-+#define		rOFDM_AGCReport				0xdd0
-+#define		rOFDM_RxSNR					0xdd4
-+#define		rOFDM_RxEVMCSI				0xdd8
-+#define		rOFDM_SIGReport				0xddc
-+
-+
-+/*
-+ * 8. PageE(0xE00)
-+ *   */
-+#define		rTxAGC_A_Rate18_06			0xe00
-+#define		rTxAGC_A_Rate54_24			0xe04
-+#define		rTxAGC_A_CCK1_Mcs32			0xe08
-+#define		rTxAGC_A_Mcs03_Mcs00			0xe10
-+#define		rTxAGC_A_Mcs07_Mcs04			0xe14
-+#define		rTxAGC_A_Mcs11_Mcs08			0xe18
-+#define		rTxAGC_A_Mcs15_Mcs12			0xe1c
-+
-+#define		rFPGA0_IQK					0xe28
-+#define		rTx_IQK_Tone_A				0xe30
-+#define		rRx_IQK_Tone_A				0xe34
-+#define		rTx_IQK_PI_A					0xe38
-+#define		rRx_IQK_PI_A					0xe3c
-+
-+#define		rTx_IQK						0xe40
-+#define		rRx_IQK						0xe44
-+#define		rIQK_AGC_Pts					0xe48
-+#define		rIQK_AGC_Rsp					0xe4c
-+#define		rTx_IQK_Tone_B				0xe50
-+#define		rRx_IQK_Tone_B				0xe54
-+#define		rTx_IQK_PI_B					0xe58
-+#define		rRx_IQK_PI_B					0xe5c
-+#define		rIQK_AGC_Cont				0xe60
-+
-+#define		rBlue_Tooth					0xe6c
-+#define		rRx_Wait_CCA					0xe70
-+#define		rTx_CCK_RFON					0xe74
-+#define		rTx_CCK_BBON				0xe78
-+#define		rTx_OFDM_RFON				0xe7c
-+#define		rTx_OFDM_BBON				0xe80
-+#define		rTx_To_Rx					0xe84
-+#define		rTx_To_Tx					0xe88
-+#define		rRx_CCK						0xe8c
-+
-+#define		rTx_Power_Before_IQK_A		0xe94
-+#define		rTx_Power_After_IQK_A			0xe9c
-+
-+#define		rRx_Power_Before_IQK_A		0xea0
-+#define		rRx_Power_Before_IQK_A_2		0xea4
-+#define		rRx_Power_After_IQK_A			0xea8
-+#define		rRx_Power_After_IQK_A_2		0xeac
-+
-+#define		rTx_Power_Before_IQK_B		0xeb4
-+#define		rTx_Power_After_IQK_B			0xebc
-+
-+#define		rRx_Power_Before_IQK_B		0xec0
-+#define		rRx_Power_Before_IQK_B_2		0xec4
-+#define		rRx_Power_After_IQK_B			0xec8
-+#define		rRx_Power_After_IQK_B_2		0xecc
-+
-+#define		rRx_OFDM					0xed0
-+#define		rRx_Wait_RIFS				0xed4
-+#define		rRx_TO_Rx					0xed8
-+#define		rStandby						0xedc
-+#define		rSleep						0xee0
-+#define		rPMPD_ANAEN				0xeec
-+
-+/*
-+ * 7. RF Register 0x00-0x2E (RF 8256)
-+ * RF-0222D 0x00-3F
-+ *
-+ * Zebra1 */
-+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
-+#define		rZebra1_TRxEnable1				0x1
-+#define		rZebra1_TRxEnable2				0x2
-+#define		rZebra1_AGC					0x4
-+#define		rZebra1_ChargePump			0x5
-+#define		rZebra1_Channel				0x7	/* RF channel switch */
-+
-+/* #endif */
-+#define		rZebra1_TxGain					0x8	/* Useless now */
-+#define		rZebra1_TxLPF					0x9
-+#define		rZebra1_RxLPF					0xb
-+#define		rZebra1_RxHPFCorner			0xc
-+
-+/* Zebra4 */
-+#define		rGlobalCtrl						0	/* Useless now */
-+#define		rRTL8256_TxLPF					19
-+#define		rRTL8256_RxLPF					11
-+
-+/* RTL8258 */
-+#define		rRTL8258_TxLPF					0x11	/* Useless now */
-+#define		rRTL8258_RxLPF					0x13
-+#define		rRTL8258_RSSILPF				0xa
-+
-+/*
-+ * RL6052 Register definition
-+ *   */
-+#define		RF_AC						0x00	/* */
-+
-+#define		RF_IQADJ_G1				0x01	/* */
-+#define		RF_IQADJ_G2				0x02	/* */
-+#define		RF_BS_PA_APSET_G1_G4		0x03
-+#define		RF_BS_PA_APSET_G5_G8		0x04
-+#define		RF_POW_TRSW				0x05	/* */
-+
-+#define		RF_GAIN_RX					0x06	/* */
-+#define		RF_GAIN_TX					0x07	/* */
-+
-+#define		RF_TXM_IDAC				0x08	/* */
-+#define		RF_IPA_G					0x09	/* */
-+#define		RF_TXBIAS_G				0x0A
-+#define		RF_TXPA_AG					0x0B
-+#define		RF_IPA_A					0x0C	/* */
-+#define		RF_TXBIAS_A				0x0D
-+#define		RF_BS_PA_APSET_G9_G11	0x0E
-+#define		RF_BS_IQGEN				0x0F	/* */
-+
-+#define		RF_MODE1					0x10	/* */
-+#define		RF_MODE2					0x11	/* */
-+
-+#define		RF_RX_AGC_HP				0x12	/* */
-+#define		RF_TX_AGC					0x13	/* */
-+#define		RF_BIAS						0x14	/* */
-+#define		RF_IPA						0x15	/* */
-+#define		RF_TXBIAS					0x16
-+#define		RF_POW_ABILITY			0x17	/* */
-+#define		RF_MODE_AG				0x18	/* */
-+#define		rRfChannel					0x18	/* RF channel and BW switch */
-+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
-+#define		RF_TOP						0x19	/* */
-+
-+#define		RF_RX_G1					0x1A	/* */
-+#define		RF_RX_G2					0x1B	/* */
-+
-+#define		RF_RX_BB2					0x1C	/* */
-+#define		RF_RX_BB1					0x1D	/* */
-+
-+#define		RF_RCK1					0x1E	/* */
-+#define		RF_RCK2					0x1F	/* */
-+
-+#define		RF_TX_G1					0x20	/* */
-+#define		RF_TX_G2					0x21	/* */
-+#define		RF_TX_G3					0x22	/* */
-+
-+#define		RF_TX_BB1					0x23	/* */
-+
-+#define		RF_T_METER					0x24	/* */
-+
-+#define		RF_SYN_G1					0x25	/* RF TX Power control */
-+#define		RF_SYN_G2					0x26	/* RF TX Power control */
-+#define		RF_SYN_G3					0x27	/* RF TX Power control */
-+#define		RF_SYN_G4					0x28	/* RF TX Power control */
-+#define		RF_SYN_G5					0x29	/* RF TX Power control */
-+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
-+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
-+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
-+
-+#define		RF_RCK_OS					0x30	/* RF TX PA control */
-+
-+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
-+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
-+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
-+#define	RF_TX_BIAS_A				0x35
-+#define	RF_TX_BIAS_D				0x36
-+#define	RF_LOBF_9					0x38
-+#define	RF_RXRF_A3					0x3C	/*	 */
-+#define	RF_TRSW					0x3F
-+
-+#define	RF_TXRF_A2					0x41
-+#define	RF_T_METER_88E				0x42
-+#define	RF_TXPA_G4					0x46
-+#define	RF_TXPA_A4					0x4B
-+#define	RF_0x52					0x52
-+#define	RF_WE_LUT					0xEF
-+#define	RF_S0S1					0xB0
-+
-+/*
-+ * Bit Mask
-+ *
-+ * 1. Page1(0x100) */
-+#define		bBBResetB						0x100	/* Useless now? */
-+#define		bGlobalResetB					0x200
-+#define		bOFDMTxStart					0x4
-+#define		bCCKTxStart						0x8
-+#define		bCRC32Debug					0x100
-+#define		bPMACLoopback					0x10
-+#define		bTxLSIG							0xffffff
-+#define		bOFDMTxRate					0xf
-+#define		bOFDMTxReserved				0x10
-+#define		bOFDMTxLength					0x1ffe0
-+#define		bOFDMTxParity					0x20000
-+#define		bTxHTSIG1						0xffffff
-+#define		bTxHTMCSRate					0x7f
-+#define		bTxHTBW						0x80
-+#define		bTxHTLength					0xffff00
-+#define		bTxHTSIG2						0xffffff
-+#define		bTxHTSmoothing					0x1
-+#define		bTxHTSounding					0x2
-+#define		bTxHTReserved					0x4
-+#define		bTxHTAggreation				0x8
-+#define		bTxHTSTBC						0x30
-+#define		bTxHTAdvanceCoding			0x40
-+#define		bTxHTShortGI					0x80
-+#define		bTxHTNumberHT_LTF			0x300
-+#define		bTxHTCRC8						0x3fc00
-+#define		bCounterReset					0x10000
-+#define		bNumOfOFDMTx					0xffff
-+#define		bNumOfCCKTx					0xffff0000
-+#define		bTxIdleInterval					0xffff
-+#define		bOFDMService					0xffff0000
-+#define		bTxMACHeader					0xffffffff
-+#define		bTxDataInit						0xff
-+#define		bTxHTMode						0x100
-+#define		bTxDataType					0x30000
-+#define		bTxRandomSeed					0xffffffff
-+#define		bCCKTxPreamble					0x1
-+#define		bCCKTxSFD						0xffff0000
-+#define		bCCKTxSIG						0xff
-+#define		bCCKTxService					0xff00
-+#define		bCCKLengthExt					0x8000
-+#define		bCCKTxLength					0xffff0000
-+#define		bCCKTxCRC16					0xffff
-+#define		bCCKTxStatus					0x1
-+#define		bOFDMTxStatus					0x2
-+
-+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
-+#define		RF_TX_GAIN_OFFSET_8723D(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0))
-+
-+/* 2. Page8(0x800) */
-+#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
-+#define		bJapanMode						0x2
-+#define		bCCKTxSC						0x30
-+#define		bCCKEn							0x1000000
-+#define		bOFDMEn						0x2000000
-+
-+#define		bOFDMRxADCPhase           0x10000	/* Useless now */
-+#define		bOFDMTxDACPhase		0x40000
-+#define		bXATxAGC			0x3f
-+
-+#define		bAntennaSelect		0x0300
-+
-+#define		bXBTxAGC                 0xf00	/* Reg 80c rFPGA0_TxGainStage */
-+#define		bXCTxAGC			0xf000
-+#define		bXDTxAGC			0xf0000
-+
-+#define		bPAStart                 0xf0000000	/* Useless now */
-+#define		bTRStart			0x00f00000
-+#define		bRFStart			0x0000f000
-+#define		bBBStart			0x000000f0
-+#define		bBBCCKStart		0x0000000f
-+#define		bPAEnd                    0xf          /* Reg0x814 */
-+#define		bTREnd			0x0f000000
-+#define		bRFEnd			0x000f0000
-+#define		bCCAMask                  0x000000f0   /* T2R */
-+#define		bR2RCCAMask		0x00000f00
-+#define		bHSSI_R2TDelay		0xf8000000
-+#define		bHSSI_T2RDelay		0xf80000
-+#define		bContTxHSSI              0x400     /* chane gain at continue Tx */
-+#define		bIGFromCCK		0x200
-+#define		bAGCAddress		0x3f
-+#define		bRxHPTx			0x7000
-+#define		bRxHPT2R			0x38000
-+#define		bRxHPCCKIni		0xc0000
-+#define		bAGCTxCode		0xc00000
-+#define		bAGCRxCode		0x300000
-+
-+#define		b3WireDataLength         0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
-+#define		b3WireAddressLength		0x400
-+
-+#define		b3WireRFPowerDown         0x1	/* Useless now
-+ * #define bHWSISelect		0x8 */
-+#define		b5GPAPEPolarity		0x40000000
-+#define		b2GPAPEPolarity		0x80000000
-+#define		bRFSW_TxDefaultAnt		0x3
-+#define		bRFSW_TxOptionAnt		0x30
-+#define		bRFSW_RxDefaultAnt		0x300
-+#define		bRFSW_RxOptionAnt		0x3000
-+#define		bRFSI_3WireData		0x1
-+#define		bRFSI_3WireClock		0x2
-+#define		bRFSI_3WireLoad		0x4
-+#define		bRFSI_3WireRW		0x8
-+#define		bRFSI_3Wire			0xf
-+
-+#define		bRFSI_RFENV              0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
-+
-+#define		bRFSI_TRSW               0x20	/* Useless now */
-+#define		bRFSI_TRSWB		0x40
-+#define		bRFSI_ANTSW		0x100
-+#define		bRFSI_ANTSWB		0x200
-+#define		bRFSI_PAPE			0x400
-+#define		bRFSI_PAPE5G		0x800
-+#define		bBandSelect			0x1
-+#define		bHTSIG2_GI			0x80
-+#define		bHTSIG2_Smoothing		0x01
-+#define		bHTSIG2_Sounding		0x02
-+#define		bHTSIG2_Aggreaton		0x08
-+#define		bHTSIG2_STBC		0x30
-+#define		bHTSIG2_AdvCoding		0x40
-+#define		bHTSIG2_NumOfHTLTF	0x300
-+#define		bHTSIG2_CRC8		0x3fc
-+#define		bHTSIG1_MCS		0x7f
-+#define		bHTSIG1_BandWidth		0x80
-+#define		bHTSIG1_HTLength		0xffff
-+#define		bLSIG_Rate			0xf
-+#define		bLSIG_Reserved		0x10
-+#define		bLSIG_Length		0x1fffe
-+#define		bLSIG_Parity			0x20
-+#define		bCCKRxPhase		0x4
-+
-+#define		bLSSIReadAddress          0x7f800000   /* T65 RF */
-+
-+#define		bLSSIReadEdge             0x80000000   /* LSSI "Read" edge signal */
-+
-+#define		bLSSIReadBackData         0xfffff		/* T65 RF */
-+
-+#define		bLSSIReadOKFlag           0x1000	/* Useless now */
-+#define		bCCKSampleRate            0x8       /* 0: 44MHz, 1:88MHz     */
-+#define		bRegulator0Standby		0x1
-+#define		bRegulatorPLLStandby		0x2
-+#define		bRegulator1Standby		0x4
-+#define		bPLLPowerUp		0x8
-+#define		bDPLLPowerUp		0x10
-+#define		bDA10PowerUp		0x20
-+#define		bAD7PowerUp		0x200
-+#define		bDA6PowerUp		0x2000
-+#define		bXtalPowerUp		0x4000
-+#define		b40MDClkPowerUP		0x8000
-+#define		bDA6DebugMode		0x20000
-+#define		bDA6Swing			0x380000
-+
-+#define		bADClkPhase               0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
-+
-+#define		b80MClkDelay              0x18000000	/* Useless */
-+#define		bAFEWatchDogEnable		0x20000000
-+
-+#define		bXtalCap01                0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
-+#define		bXtalCap23			0x3
-+#define		bXtalCap92x					0x0f000000
-+#define		bXtalCap			0x0f000000
-+
-+#define		bIntDifClkEnable          0x400	/* Useless */
-+#define		bExtSigClkEnable		0x800
-+#define		bBandgapMbiasPowerUp	0x10000
-+#define		bAD11SHGain		0xc0000
-+#define		bAD11InputRange		0x700000
-+#define		bAD11OPCurrent		0x3800000
-+#define		bIPathLoopback		0x4000000
-+#define		bQPathLoopback		0x8000000
-+#define		bAFELoopback		0x10000000
-+#define		bDA10Swing		0x7e0
-+#define		bDA10Reverse		0x800
-+#define		bDAClkSource		0x1000
-+#define		bAD7InputRange		0x6000
-+#define		bAD7Gain			0x38000
-+#define		bAD7OutputCMMode		0x40000
-+#define		bAD7InputCMMode		0x380000
-+#define		bAD7Current			0xc00000
-+#define		bRegulatorAdjust		0x7000000
-+#define		bAD11PowerUpAtTx		0x1
-+#define		bDA10PSAtTx		0x10
-+#define		bAD11PowerUpAtRx		0x100
-+#define		bDA10PSAtRx		0x1000
-+#define		bCCKRxAGCFormat		0x200
-+#define		bPSDFFTSamplepPoint		0xc000
-+#define		bPSDAverageNum		0x3000
-+#define		bIQPathControl		0xc00
-+#define		bPSDFreq			0x3ff
-+#define		bPSDAntennaPath		0x30
-+#define		bPSDIQSwitch		0x40
-+#define		bPSDRxTrigger		0x400000
-+#define		bPSDTxTrigger		0x80000000
-+#define		bPSDSineToneScale		0x7f000000
-+#define		bPSDReport			0xffff
-+
-+/* 3. Page9(0x900) */
-+#define		bOFDMTxSC                 0x30000000	/* Useless */
-+#define		bCCKTxOn			0x1
-+#define		bOFDMTxOn		0x2
-+#define		bDebugPage                0xfff  /* reset debug page and also HWord, LWord */
-+#define		bDebugItem                0xff   /* reset debug page and LWord */
-+#define		bAntL			0x10
-+#define		bAntNonHT				0x100
-+#define		bAntHT1			0x1000
-+#define		bAntHT2			0x10000
-+#define		bAntHT1S1			0x100000
-+#define		bAntNonHTS1		0x1000000
-+
-+/* 4. PageA(0xA00) */
-+#define		bCCKBBMode				0x3	/* Useless */
-+#define		bCCKTxPowerSaving		0x80
-+#define		bCCKRxPowerSaving		0x40
-+
-+#define		bCCKSideBand			0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
-+
-+#define		bCCKScramble			0x8	/* Useless */
-+#define		bCCKAntDiversity		0x8000
-+#define		bCCKCarrierRecovery		0x4000
-+#define		bCCKTxRate				0x3000
-+#define		bCCKDCCancel			0x0800
-+#define		bCCKISICancel			0x0400
-+#define		bCCKMatchFilter			0x0200
-+#define		bCCKEqualizer			0x0100
-+#define		bCCKPreambleDetect		0x800000
-+#define		bCCKFastFalseCCA		0x400000
-+#define		bCCKChEstStart			0x300000
-+#define		bCCKCCACount			0x080000
-+#define		bCCKcs_lim				0x070000
-+#define		bCCKBistMode			0x80000000
-+#define		bCCKCCAMask			0x40000000
-+#define		bCCKTxDACPhase		0x4
-+#define		bCCKRxADCPhase		0x20000000   /* r_rx_clk */
-+#define		bCCKr_cp_mode0		0x0100
-+#define		bCCKTxDCOffset			0xf0
-+#define		bCCKRxDCOffset			0xf
-+#define		bCCKCCAMode			0xc000
-+#define		bCCKFalseCS_lim			0x3f00
-+#define		bCCKCS_ratio			0xc00000
-+#define		bCCKCorgBit_sel			0x300000
-+#define		bCCKPD_lim				0x0f0000
-+#define		bCCKNewCCA			0x80000000
-+#define		bCCKRxHPofIG			0x8000
-+#define		bCCKRxIG				0x7f00
-+#define		bCCKLNAPolarity			0x800000
-+#define		bCCKRx1stGain			0x7f0000
-+#define		bCCKRFExtend			0x20000000 /* CCK Rx Iinital gain polarity */
-+#define		bCCKRxAGCSatLevel		0x1f000000
-+#define		bCCKRxAGCSatCount		0xe0
-+#define		bCCKRxRFSettle			0x1f       /* AGCsamp_dly */
-+#define		bCCKFixedRxAGC			0x8000
-+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
-+#define		bCCKAntennaPolarity		0x2000
-+#define		bCCKTxFilterType		0x0c00
-+#define		bCCKRxAGCReportType	0x0300
-+#define		bCCKRxDAGCEn			0x80000000
-+#define		bCCKRxDAGCPeriod		0x20000000
-+#define		bCCKRxDAGCSatLevel		0x1f000000
-+#define		bCCKTimingRecovery		0x800000
-+#define		bCCKTxC0				0x3f0000
-+#define		bCCKTxC1				0x3f000000
-+#define		bCCKTxC2				0x3f
-+#define		bCCKTxC3				0x3f00
-+#define		bCCKTxC4				0x3f0000
-+#define		bCCKTxC5				0x3f000000
-+#define		bCCKTxC6				0x3f
-+#define		bCCKTxC7				0x3f00
-+#define		bCCKDebugPort			0xff0000
-+#define		bCCKDACDebug			0x0f000000
-+#define		bCCKFalseAlarmEnable	0x8000
-+#define		bCCKFalseAlarmRead		0x4000
-+#define		bCCKTRSSI				0x7f
-+#define		bCCKRxAGCReport		0xfe
-+#define		bCCKRxReport_AntSel	0x80000000
-+#define		bCCKRxReport_MFOff		0x40000000
-+#define		bCCKRxRxReport_SQLoss	0x20000000
-+#define		bCCKRxReport_Pktloss	0x10000000
-+#define		bCCKRxReport_Lockedbit	0x08000000
-+#define		bCCKRxReport_RateError	0x04000000
-+#define		bCCKRxReport_RxRate	0x03000000
-+#define		bCCKRxFACounterLower	0xff
-+#define		bCCKRxFACounterUpper	0xff000000
-+#define		bCCKRxHPAGCStart		0xe000
-+#define		bCCKRxHPAGCFinal		0x1c00
-+#define		bCCKRxFalseAlarmEnable	0x8000
-+#define		bCCKFACounterFreeze	0x4000
-+#define		bCCKTxPathSel			0x10000000
-+#define		bCCKDefaultRxPath		0xc000000
-+#define		bCCKOptionRxPath		0x3000000
-+
-+/* 5. PageC(0xC00) */
-+#define		bNumOfSTF				0x3	/* Useless */
-+#define		bShift_L					0xc0
-+#define		bGI_TH					0xc
-+#define		bRxPathA				0x1
-+#define		bRxPathB				0x2
-+#define		bRxPathC				0x4
-+#define		bRxPathD				0x8
-+#define		bTxPathA				0x1
-+#define		bTxPathB				0x2
-+#define		bTxPathC				0x4
-+#define		bTxPathD				0x8
-+#define		bTRSSIFreq				0x200
-+#define		bADCBackoff				0x3000
-+#define		bDFIRBackoff			0xc000
-+#define		bTRSSILatchPhase		0x10000
-+#define		bRxIDCOffset			0xff
-+#define		bRxQDCOffset			0xff00
-+#define		bRxDFIRMode			0x1800000
-+#define		bRxDCNFType			0xe000000
-+#define		bRXIQImb_A				0x3ff
-+#define		bRXIQImb_B				0xfc00
-+#define		bRXIQImb_C				0x3f0000
-+#define		bRXIQImb_D				0xffc00000
-+#define		bDC_dc_Notch			0x60000
-+#define		bRxNBINotch			0x1f000000
-+#define		bPD_TH					0xf
-+#define		bPD_TH_Opt2			0xc000
-+#define		bPWED_TH				0x700
-+#define		bIfMF_Win_L			0x800
-+#define		bPD_Option				0x1000
-+#define		bMF_Win_L				0xe000
-+#define		bBW_Search_L			0x30000
-+#define		bwin_enh_L				0xc0000
-+#define		bBW_TH					0x700000
-+#define		bED_TH2				0x3800000
-+#define		bBW_option				0x4000000
-+#define		bRatio_TH				0x18000000
-+#define		bWindow_L				0xe0000000
-+#define		bSBD_Option				0x1
-+#define		bFrame_TH				0x1c
-+#define		bFS_Option				0x60
-+#define		bDC_Slope_check		0x80
-+#define		bFGuard_Counter_DC_L	0xe00
-+#define		bFrame_Weight_Short	0x7000
-+#define		bSub_Tune				0xe00000
-+#define		bFrame_DC_Length		0xe000000
-+#define		bSBD_start_offset		0x30000000
-+#define		bFrame_TH_2			0x7
-+#define		bFrame_GI2_TH			0x38
-+#define		bGI2_Sync_en			0x40
-+#define		bSarch_Short_Early		0x300
-+#define		bSarch_Short_Late		0xc00
-+#define		bSarch_GI2_Late		0x70000
-+#define		bCFOAntSum				0x1
-+#define		bCFOAcc				0x2
-+#define		bCFOStartOffset			0xc
-+#define		bCFOLookBack			0x70
-+#define		bCFOSumWeight			0x80
-+#define		bDAGCEnable			0x10000
-+#define		bTXIQImb_A				0x3ff
-+#define		bTXIQImb_B				0xfc00
-+#define		bTXIQImb_C				0x3f0000
-+#define		bTXIQImb_D				0xffc00000
-+#define		bTxIDCOffset			0xff
-+#define		bTxQDCOffset			0xff00
-+#define		bTxDFIRMode			0x10000
-+#define		bTxPesudoNoiseOn		0x4000000
-+#define		bTxPesudoNoise_A		0xff
-+#define		bTxPesudoNoise_B		0xff00
-+#define		bTxPesudoNoise_C		0xff0000
-+#define		bTxPesudoNoise_D		0xff000000
-+#define		bCCADropOption			0x20000
-+#define		bCCADropThres			0xfff00000
-+#define		bEDCCA_H				0xf
-+#define		bEDCCA_L				0xf0
-+#define		bLambda_ED			0x300
-+#define		bRxInitialGain			0x7f
-+#define		bRxAntDivEn				0x80
-+#define		bRxAGCAddressForLNA	0x7f00
-+#define		bRxHighPowerFlow		0x8000
-+#define		bRxAGCFreezeThres		0xc0000
-+#define		bRxFreezeStep_AGC1	0x300000
-+#define		bRxFreezeStep_AGC2	0xc00000
-+#define		bRxFreezeStep_AGC3	0x3000000
-+#define		bRxFreezeStep_AGC0	0xc000000
-+#define		bRxRssi_Cmp_En			0x10000000
-+#define		bRxQuickAGCEn			0x20000000
-+#define		bRxAGCFreezeThresMode	0x40000000
-+#define		bRxOverFlowCheckType	0x80000000
-+#define		bRxAGCShift				0x7f
-+#define		bTRSW_Tri_Only			0x80
-+#define		bPowerThres			0x300
-+#define		bRxAGCEn				0x1
-+#define		bRxAGCTogetherEn		0x2
-+#define		bRxAGCMin				0x4
-+#define		bRxHP_Ini				0x7
-+#define		bRxHP_TRLNA			0x70
-+#define		bRxHP_RSSI				0x700
-+#define		bRxHP_BBP1				0x7000
-+#define		bRxHP_BBP2				0x70000
-+#define		bRxHP_BBP3				0x700000
-+#define		bRSSI_H					0x7f0000     /* the threshold for high power */
-+#define		bRSSI_Gen				0x7f000000   /* the threshold for ant diversity */
-+#define		bRxSettle_TRSW			0x7
-+#define		bRxSettle_LNA			0x38
-+#define		bRxSettle_RSSI			0x1c0
-+#define		bRxSettle_BBP			0xe00
-+#define		bRxSettle_RxHP			0x7000
-+#define		bRxSettle_AntSW_RSSI	0x38000
-+#define		bRxSettle_AntSW		0xc0000
-+#define		bRxProcessTime_DAGC	0x300000
-+#define		bRxSettle_HSSI			0x400000
-+#define		bRxProcessTime_BBPPW	0x800000
-+#define		bRxAntennaPowerShift	0x3000000
-+#define		bRSSITableSelect		0xc000000
-+#define		bRxHP_Final				0x7000000
-+#define		bRxHTSettle_BBP			0x7
-+#define		bRxHTSettle_HSSI		0x8
-+#define		bRxHTSettle_RxHP		0x70
-+#define		bRxHTSettle_BBPPW		0x80
-+#define		bRxHTSettle_Idle		0x300
-+#define		bRxHTSettle_Reserved	0x1c00
-+#define		bRxHTRxHPEn			0x8000
-+#define		bRxHTAGCFreezeThres	0x30000
-+#define		bRxHTAGCTogetherEn	0x40000
-+#define		bRxHTAGCMin			0x80000
-+#define		bRxHTAGCEn				0x100000
-+#define		bRxHTDAGCEn			0x200000
-+#define		bRxHTRxHP_BBP			0x1c00000
-+#define		bRxHTRxHP_Final		0xe0000000
-+#define		bRxPWRatioTH			0x3
-+#define		bRxPWRatioEn			0x4
-+#define		bRxMFHold				0x3800
-+#define		bRxPD_Delay_TH1		0x38
-+#define		bRxPD_Delay_TH2		0x1c0
-+#define		bRxPD_DC_COUNT_MAX	0x600
-+/* #define bRxMF_Hold               0x3800 */
-+#define		bRxPD_Delay_TH			0x8000
-+#define		bRxProcess_Delay		0xf0000
-+#define		bRxSearchrange_GI2_Early	0x700000
-+#define		bRxFrame_Guard_Counter_L	0x3800000
-+#define		bRxSGI_Guard_L			0xc000000
-+#define		bRxSGI_Search_L		0x30000000
-+#define		bRxSGI_TH				0xc0000000
-+#define		bDFSCnt0				0xff
-+#define		bDFSCnt1				0xff00
-+#define		bDFSFlag				0xf0000
-+#define		bMFWeightSum			0x300000
-+#define		bMinIdxTH				0x7f000000
-+#define		bDAFormat				0x40000
-+#define		bTxChEmuEnable		0x01000000
-+#define		bTRSWIsolation_A		0x7f
-+#define		bTRSWIsolation_B		0x7f00
-+#define		bTRSWIsolation_C		0x7f0000
-+#define		bTRSWIsolation_D		0x7f000000
-+#define		bExtLNAGain				0x7c00
-+
-+/* 6. PageE(0xE00) */
-+#define		bSTBCEn				0x4	/* Useless */
-+#define		bAntennaMapping		0x10
-+#define		bNss					0x20
-+#define		bCFOAntSumD			0x200
-+#define		bPHYCounterReset		0x8000000
-+#define		bCFOReportGet			0x4000000
-+#define		bOFDMContinueTx		0x10000000
-+#define		bOFDMSingleCarrier		0x20000000
-+#define		bOFDMSingleTone		0x40000000
-+/* #define bRxPath1                 0x01 */
-+/* #define bRxPath2                 0x02 */
-+/* #define bRxPath3                 0x04 */
-+/* #define bRxPath4                 0x08 */
-+/* #define bTxPath1                 0x10 */
-+/* #define bTxPath2                 0x20 */
-+#define		bHTDetect			0x100
-+#define		bCFOEn				0x10000
-+#define		bCFOValue			0xfff00000
-+#define		bSigTone_Re		0x3f
-+#define		bSigTone_Im		0x7f00
-+#define		bCounter_CCA		0xffff
-+#define		bCounter_ParityFail	0xffff0000
-+#define		bCounter_RateIllegal		0xffff
-+#define		bCounter_CRC8Fail	0xffff0000
-+#define		bCounter_MCSNoSupport	0xffff
-+#define		bCounter_FastSync	0xffff
-+#define		bShortCFO			0xfff
-+#define		bShortCFOTLength	12   /* total */
-+#define		bShortCFOFLength	11   /* fraction */
-+#define		bLongCFO			0x7ff
-+#define		bLongCFOTLength	11
-+#define		bLongCFOFLength	11
-+#define		bTailCFO			0x1fff
-+#define		bTailCFOTLength		13
-+#define		bTailCFOFLength		12
-+#define		bmax_en_pwdB		0xffff
-+#define		bCC_power_dB		0xffff0000
-+#define		bnoise_pwdB		0xffff
-+#define		bPowerMeasTLength	10
-+#define		bPowerMeasFLength	3
-+#define		bRx_HT_BW			0x1
-+#define		bRxSC				0x6
-+#define		bRx_HT				0x8
-+#define		bNB_intf_det_on		0x1
-+#define		bIntf_win_len_cfg	0x30
-+#define		bNB_Intf_TH_cfg		0x1c0
-+#define		bRFGain				0x3f
-+#define		bTableSel			0x40
-+#define		bTRSW				0x80
-+#define		bRxSNR_A			0xff
-+#define		bRxSNR_B			0xff00
-+#define		bRxSNR_C			0xff0000
-+#define		bRxSNR_D			0xff000000
-+#define		bSNREVMTLength		8
-+#define		bSNREVMFLength		1
-+#define		bCSI1st				0xff
-+#define		bCSI2nd				0xff00
-+#define		bRxEVM1st			0xff0000
-+#define		bRxEVM2nd			0xff000000
-+#define		bSIGEVM			0xff
-+#define		bPWDB				0xff00
-+#define		bSGIEN				0x10000
-+
-+#define		bSFactorQAM1		0xf	/* Useless */
-+#define		bSFactorQAM2		0xf0
-+#define		bSFactorQAM3		0xf00
-+#define		bSFactorQAM4		0xf000
-+#define		bSFactorQAM5		0xf0000
-+#define		bSFactorQAM6		0xf0000
-+#define		bSFactorQAM7		0xf00000
-+#define		bSFactorQAM8		0xf000000
-+#define		bSFactorQAM9		0xf0000000
-+#define		bCSIScheme			0x100000
-+
-+#define		bNoiseLvlTopSet		0x3	/* Useless */
-+#define		bChSmooth			0x4
-+#define		bChSmoothCfg1		0x38
-+#define		bChSmoothCfg2		0x1c0
-+#define		bChSmoothCfg3		0xe00
-+#define		bChSmoothCfg4		0x7000
-+#define		bMRCMode			0x800000
-+#define		bTHEVMCfg			0x7000000
-+
-+#define		bLoopFitType		0x1	/* Useless */
-+#define		bUpdCFO			0x40
-+#define		bUpdCFOOffData		0x80
-+#define		bAdvUpdCFO			0x100
-+#define		bAdvTimeCtrl		0x800
-+#define		bUpdClko			0x1000
-+#define		bFC					0x6000
-+#define		bTrackingMode		0x8000
-+#define		bPhCmpEnable		0x10000
-+#define		bUpdClkoLTF		0x20000
-+#define		bComChCFO			0x40000
-+#define		bCSIEstiMode		0x80000
-+#define		bAdvUpdEqz			0x100000
-+#define		bUChCfg				0x7000000
-+#define		bUpdEqz			0x8000000
-+
-+/* Rx Pseduo noise */
-+#define		bRxPesudoNoiseOn		0x20000000	/* Useless */
-+#define		bRxPesudoNoise_A		0xff
-+#define		bRxPesudoNoise_B		0xff00
-+#define		bRxPesudoNoise_C		0xff0000
-+#define		bRxPesudoNoise_D		0xff000000
-+#define		bPesudoNoiseState_A	0xffff
-+#define		bPesudoNoiseState_B	0xffff0000
-+#define		bPesudoNoiseState_C	0xffff
-+#define		bPesudoNoiseState_D	0xffff0000
-+
-+/* 7. RF Register
-+ * Zebra1 */
-+#define		bZebra1_HSSIEnable		0x8		/* Useless */
-+#define		bZebra1_TRxControl		0xc00
-+#define		bZebra1_TRxGainSetting	0x07f
-+#define		bZebra1_RxCorner		0xc00
-+#define		bZebra1_TxChargePump	0x38
-+#define		bZebra1_RxChargePump	0x7
-+#define		bZebra1_ChannelNum	0xf80
-+#define		bZebra1_TxLPFBW		0x400
-+#define		bZebra1_RxLPFBW		0x600
-+
-+/* Zebra4 */
-+#define		bRTL8256RegModeCtrl1	0x100	/* Useless */
-+#define		bRTL8256RegModeCtrl0	0x40
-+#define		bRTL8256_TxLPFBW		0x18
-+#define		bRTL8256_RxLPFBW		0x600
-+
-+/* RTL8258 */
-+#define		bRTL8258_TxLPFBW		0xc	/* Useless */
-+#define		bRTL8258_RxLPFBW		0xc00
-+#define		bRTL8258_RSSILPFBW	0xc0
-+
-+
-+/*
-+ * Other Definition
-+ *   */
-+
-+/* byte endable for sb_write */
-+#define		bByte0				0x1	/* Useless */
-+#define		bByte1				0x2
-+#define		bByte2				0x4
-+#define		bByte3				0x8
-+#define		bWord0				0x3
-+#define		bWord1				0xc
-+#define		bDWord				0xf
-+
-+/* for PutRegsetting & GetRegSetting BitMask */
-+#define		bMaskByte0			0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
-+#define		bMaskByte1			0xff00
-+#define		bMaskByte2			0xff0000
-+#define		bMaskByte3			0xff000000
-+#define		bMaskHWord		0xffff0000
-+#define		bMaskLWord			0x0000ffff
-+#define		bMaskDWord		0xffffffff
-+#define		bMaskH3Bytes		0xffffff00
-+#define		bMask12Bits			0xfff
-+#define		bMaskH4Bits			0xf0000000
-+#define		bMaskOFDM_D		0xffc00000
-+#define		bMaskCCK			0x3f3f3f3f
-+
-+
-+#define		bEnable			0x1	/* Useless */
-+#define		bDisable		0x0
-+
-+#define		LeftAntenna		0x0	/* Useless */
-+#define		RightAntenna	0x1
-+
-+#define		tCheckTxStatus		500   /* 500ms // Useless */
-+#define		tUpdateRxCounter	100   /* 100ms */
-+
-+#define		rateCCK		0	/* Useless */
-+#define		rateOFDM	1
-+#define		rateHT		2
-+
-+/* define Register-End */
-+#define		bPMAC_End			0x1ff	/* Useless */
-+#define		bFPGAPHY0_End		0x8ff
-+#define		bFPGAPHY1_End		0x9ff
-+#define		bCCKPHY0_End		0xaff
-+#define		bOFDMPHY0_End		0xcff
-+#define		bOFDMPHY1_End		0xdff
-+
-+/* define max debug item in each debug page
-+ * #define bMaxItem_FPGA_PHY0        0x9
-+ * #define bMaxItem_FPGA_PHY1        0x3
-+ * #define bMaxItem_PHY_11B          0x16
-+ * #define bMaxItem_OFDM_PHY0        0x29
-+ * #define bMaxItem_OFDM_PHY1        0x0 */
-+
-+#define		bPMACControl		0x0		/* Useless */
-+#define		bWMACControl		0x1
-+#define		bWNICControl		0x2
-+
-+#define		PathA			0x0	/* Useless */
-+#define		PathB			0x1
-+#define		PathC			0x2
-+#define		PathD			0x3
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8723DPwrSeq.h b/drivers/staging/rtl8723cs/include/Hal8723DPwrSeq.h
-new file mode 100644
-index 000000000000..60cb53b27bd1
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8723DPwrSeq.h
-@@ -0,0 +1,206 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef REALTEK_POWER_SEQUENCE_8723D
-+#define REALTEK_POWER_SEQUENCE_8723D
-+
-+/* #include "PwrSeqCmd.h" */
-+#include "HalPwrSeqCmd.h"
-+
-+/*
-+	Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd
-+	There are 6 HW Power States:
-+	0: POFF--Power Off
-+	1: PDN--Power Down
-+	2: CARDEMU--Card Emulation
-+	3: ACT--Active Mode
-+	4: LPS--Low Power State
-+	5: SUS--Suspend
-+
-+	The transition from different states are defined below
-+	TRANS_CARDEMU_TO_ACT
-+	TRANS_ACT_TO_CARDEMU
-+	TRANS_CARDEMU_TO_SUS
-+	TRANS_SUS_TO_CARDEMU
-+	TRANS_CARDEMU_TO_PDN
-+	TRANS_ACT_TO_LPS
-+	TRANS_LPS_TO_ACT
-+
-+	TRANS_END
-+*/
-+#define	RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS	27
-+#define	RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS	8
-+#define	RTL8723D_TRANS_CARDEMU_TO_SUS_STEPS	7
-+#define	RTL8723D_TRANS_SUS_TO_CARDEMU_STEPS	5
-+#define	RTL8723D_TRANS_CARDEMU_TO_CARDDIS_STEPS	8
-+#define	RTL8723D_TRANS_CARDDIS_TO_CARDEMU_STEPS	7
-+#define	RTL8723D_TRANS_CARDEMU_TO_PDN_STEPS	4
-+#define	RTL8723D_TRANS_PDN_TO_CARDEMU_STEPS	1
-+#define	RTL8723D_TRANS_ACT_TO_LPS_STEPS		13
-+#define	RTL8723D_TRANS_LPS_TO_ACT_STEPS		11
-+#define	RTL8723D_TRANS_END_STEPS	1
-+
-+
-+#define RTL8723D_TRANS_CARDEMU_TO_ACT														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/	\
-+	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
-+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
-+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)},/* Disable USB suspend */	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},/* wait till 0x04[17] = 1    power ready*/	\
-+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0},/* Enable USB suspend */	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* release WLON reset  0x04[16]=1*/ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0}, \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* disable HWPDN 0x04[15]=0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},/* disable WL suspend*/ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* polling until return 0*/ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},/**/ \
-+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},/* Enable WL control XTAL setting*/ \
-+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable falling edge triggering interrupt*/\
-+	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable GPIO9 interrupt mode*/\
-+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Enable GPIO9 input mode*/\
-+	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/*Enable HSISR GPIO[C:0] interrupt*/\
-+	{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable HSISR GPIO9 interrupt*/\
-+	{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)},/*For GPIO9 internal pull high setting by test chip*/\
-+	{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},/*For GPIO9 internal pull high setting*/\
-+	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S1*/\
-+	{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S0*/\
-+	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/*enable RF path S1*/\
-+	{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/*enalbe RF path S0*/\
-+
-+
-+#define RTL8723D_TRANS_ACT_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
-+	/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x2[0]=0 Reset BB, RF enter Power Down mode*/ \
-+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Enable rising edge triggering interrupt*/ \
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* release WLON reset  0x04[16]=1*/ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
-+	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0},/* Enable BT control XTAL setting*/\
-+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
-+
-+
-+#define RTL8723D_TRANS_CARDEMU_TO_SUS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
-+
-+#define RTL8723D_TRANS_SUS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ \
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
-+
-+
-+#define RTL8723D_TRANS_CARDEMU_TO_CARDDIS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, /*0x04[10] = 1, enable SW LPS*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend*/	\
-+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
-+
-+#define RTL8723D_TRANS_CARDDIS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ \
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\
-+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
-+
-+
-+#define RTL8723D_TRANS_CARDEMU_TO_PDN												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
-+
-+#define RTL8723D_TRANS_PDN_TO_CARDEMU												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
-+
-+#define RTL8723D_TRANS_ACT_TO_LPS														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
-+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/*CCK and OFDM are disabled, and clock are gated*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/	\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \
-+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
-+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},/*Respond TxOK to scheduler*/	\
-+
-+
-+#define RTL8723D_TRANS_LPS_TO_ACT															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
-+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
-+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*.	0x08[4] = 0  switch TSF to 40M*/\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
-+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, /*.	0x101[1] = 1*/\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
-+
-+#define RTL8723D_TRANS_END															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/								\
-+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
-+
-+
-+	extern WLAN_PWR_CFG rtl8723D_power_on_flow[RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723D_radio_off_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723D_card_disable_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_CARDDIS_STEPS + RTL8723D_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723D_card_enable_flow[RTL8723D_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723D_suspend_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723D_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723D_resume_flow[RTL8723D_TRANS_SUS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723D_hwpdn_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723D_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723D_enter_lps_flow[RTL8723D_TRANS_ACT_TO_LPS_STEPS + RTL8723D_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723D_leave_lps_flow[RTL8723D_TRANS_LPS_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8723PwrSeq.h b/drivers/staging/rtl8723cs/include/Hal8723PwrSeq.h
-new file mode 100644
-index 000000000000..22de83375e66
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8723PwrSeq.h
-@@ -0,0 +1,183 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL8723PWRSEQ_H__
-+#define __HAL8723PWRSEQ_H__
-+/*
-+	Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
-+	There are 6 HW Power States:
-+	0: POFF--Power Off
-+	1: PDN--Power Down
-+	2: CARDEMU--Card Emulation
-+	3: ACT--Active Mode
-+	4: LPS--Low Power State
-+	5: SUS--Suspend
-+
-+	The transision from different states are defined below
-+	TRANS_CARDEMU_TO_ACT
-+	TRANS_ACT_TO_CARDEMU
-+	TRANS_CARDEMU_TO_SUS
-+	TRANS_SUS_TO_CARDEMU
-+	TRANS_CARDEMU_TO_PDN
-+	TRANS_ACT_TO_LPS
-+	TRANS_LPS_TO_ACT
-+
-+	TRANS_END
-+*/
-+#include "HalPwrSeqCmd.h"
-+
-+#define	RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS	15
-+#define	RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS	15
-+#define	RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS	15
-+#define	RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS	15
-+#define	RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS	15
-+#define	RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS	15
-+#define	RTL8723A_TRANS_ACT_TO_LPS_STEPS	15
-+#define	RTL8723A_TRANS_LPS_TO_ACT_STEPS	15
-+#define	RTL8723A_TRANS_END_STEPS	1
-+
-+
-+#define RTL8723A_TRANS_CARDEMU_TO_ACT														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \
-+	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
-+	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
-+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
-+	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\
-+
-+#define RTL8723A_TRANS_ACT_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
-+	{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
-+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/   \
-+
-+
-+#define RTL8723A_TRANS_CARDEMU_TO_SUS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8723A_TRANS_SUS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
-+
-+#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
-+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
-+
-+
-+#define RTL8723A_TRANS_CARDEMU_TO_PDN												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
-+
-+#define RTL8723A_TRANS_PDN_TO_CARDEMU												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
-+
-+#define RTL8723A_TRANS_ACT_TO_LPS														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
-+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
-+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
-+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
-+
-+
-+#define RTL8723A_TRANS_LPS_TO_ACT															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
-+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
-+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
-+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
-+
-+#define RTL8723A_TRANS_END															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
-+
-+
-+	extern WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS + RTL8723A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8812PhyCfg.h b/drivers/staging/rtl8723cs/include/Hal8812PhyCfg.h
-new file mode 100644
-index 000000000000..69c70d30e8ec
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8812PhyCfg.h
-@@ -0,0 +1,134 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8812PHYCFG_H__
-+#define __INC_HAL8812PHYCFG_H__
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+#define LOOP_LIMIT				5
-+#define MAX_STALL_TIME			50		/* us */
-+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
-+#define MAX_TXPWR_IDX_NMODE_92S	63
-+#define Reset_Cnt_Limit			3
-+
-+
-+#ifdef CONFIG_PCI_HCI
-+	#define MAX_AGGR_NUM	0x0B
-+#else
-+	#define MAX_AGGR_NUM	0x07
-+#endif /* CONFIG_PCI_HCI */
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+
-+/* BB/RF related */
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+
-+/*------------------------Export global variable----------------------------*/
-+/*------------------------Export global variable----------------------------*/
-+
-+
-+/*------------------------Export Marco Definition---------------------------*/
-+/*------------------------Export Marco Definition---------------------------*/
-+
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+/*
-+ * BB and RF register read/write
-+ *   */
-+u32	PHY_QueryBBReg8812(PADAPTER	Adapter,
-+				u32			RegAddr,
-+				u32			BitMask);
-+void	PHY_SetBBReg8812(PADAPTER		Adapter,
-+				u32			RegAddr,
-+				u32			BitMask,
-+				u32			Data);
-+u32	PHY_QueryRFReg8812(PADAPTER	Adapter,
-+				enum rf_path	eRFPath,
-+				u32			RegAddr,
-+				u32			BitMask);
-+void	PHY_SetRFReg8812(PADAPTER		Adapter,
-+				enum rf_path	eRFPath,
-+				u32			RegAddr,
-+				u32			BitMask,
-+				u32			Data);
-+
-+/*
-+ * Initialization related function
-+ *
-+ * MAC/BB/RF HAL config */
-+int	PHY_MACConfig8812(PADAPTER	Adapter);
-+int	PHY_BBConfig8812(PADAPTER	Adapter);
-+void	PHY_BB8812_Config_1T(PADAPTER	Adapter);
-+int	PHY_RFConfig8812(PADAPTER	Adapter);
-+
-+/* RF config */
-+
-+s32
-+PHY_SwitchWirelessBand8812(
-+		PADAPTER		Adapter,
-+		u8			Band
-+);
-+
-+/*
-+ * BB TX Power R/W
-+ *   */
-+void	PHY_SetTxPowerLevel8812(PADAPTER	Adapter, u8	Channel);
-+
-+bool phy_get_txpwr_target_skip_by_rate_8812a(_adapter *adapter, enum MGN_RATE rate);
-+
-+u32 phy_get_tx_bb_swing_8812a(
-+		PADAPTER	Adapter,
-+		BAND_TYPE	Band,
-+		enum rf_path	RFPath
-+);
-+
-+void
-+PHY_SetTxPowerIndex_8812A(
-+		PADAPTER		Adapter,
-+		u32				PowerIndex,
-+		enum rf_path		RFPath,
-+		u8				Rate
-+);
-+
-+/*
-+ * channel switch related funciton
-+ *   */
-+void
-+PHY_SetSwChnlBWMode8812(
-+		PADAPTER			Adapter,
-+		u8					channel,
-+		enum channel_width	Bandwidth,
-+		u8					Offset40,
-+		u8					Offset80
-+);
-+
-+/*
-+ * BB/MAC/RF other monitor API
-+ *   */
-+
-+void
-+phy_set_rf_path_switch_8812a(
-+		struct dm_struct		*phydm,
-+		bool		bMain
-+);
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+#endif /* __INC_HAL8192CPHYCFG_H */
-diff --git a/drivers/staging/rtl8723cs/include/Hal8812PhyReg.h b/drivers/staging/rtl8723cs/include/Hal8812PhyReg.h
-new file mode 100644
-index 000000000000..521ebb202346
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8812PhyReg.h
-@@ -0,0 +1,735 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8812PHYREG_H__
-+#define __INC_HAL8812PHYREG_H__
-+/*--------------------------Define Parameters-------------------------------*/
-+/*
-+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
-+ * 3. RF register 0x00-2E
-+ * 4. Bit Mask for BB/RF register
-+ * 5. Other defintion for BB/RF R/W
-+ *   */
-+
-+
-+/* BB Register Definition */
-+
-+#define rCCAonSec_Jaguar		0x838
-+#define rPwed_TH_Jaguar			0x830
-+
-+/* BW and sideband setting */
-+#define rBWIndication_Jaguar		0x834
-+#define rL1PeakTH_Jaguar			0x848
-+#define rFPGA0_XA_LSSIReadBack	0x8a0	/*Tranceiver LSSI Readback*/
-+#define rRFMOD_Jaguar			0x8ac	/* RF mode */
-+#define rADC_Buf_Clk_Jaguar		0x8c4
-+#define rRFECTRL_Jaguar			0x900
-+#define bRFMOD_Jaguar			0xc3
-+#define rCCK_System_Jaguar		0xa00   /* for cck sideband */
-+#define bCCK_System_Jaguar		0x10
-+
-+/* Block & Path enable */
-+#define rOFDMCCKEN_Jaguar 		0x808 /* OFDM/CCK block enable */
-+#define bOFDMEN_Jaguar			0x20000000
-+#define bCCKEN_Jaguar			0x10000000
-+#define rRxPath_Jaguar			0x808	/* Rx antenna */
-+#define bRxPath_Jaguar			0xff
-+#define rTxPath_Jaguar			0x80c	/* Tx antenna */
-+#define bTxPath_Jaguar			0x0fffffff
-+#define rCCK_RX_Jaguar			0xa04	/* for cck rx path selection */
-+#define bCCK_RX_Jaguar			0x0c000000
-+#define rVhtlen_Use_Lsig_Jaguar	0x8c3	/* Use LSIG for VHT length */
-+
-+/* RF read/write-related */
-+#define rHSSIRead_Jaguar			0x8b0  /* RF read addr */
-+#define bHSSIRead_addr_Jaguar		0xff
-+#define bHSSIRead_trigger_Jaguar	0x100
-+#define rA_PIRead_Jaguar			0xd04 /* RF readback with PI */
-+#define rB_PIRead_Jaguar			0xd44 /* RF readback with PI */
-+#define rA_SIRead_Jaguar			0xd08 /* RF readback with SI */
-+#define rB_SIRead_Jaguar			0xd48 /* RF readback with SI */
-+#define rRead_data_Jaguar			0xfffff
-+#define rA_LSSIWrite_Jaguar			0xc90 /* RF write addr */
-+#define rB_LSSIWrite_Jaguar			0xe90 /* RF write addr */
-+#define bLSSIWrite_data_Jaguar		0x000fffff
-+#define bLSSIWrite_addr_Jaguar		0x0ff00000
-+
-+
-+
-+/* YN: mask the following register definition temporarily */
-+#define rFPGA0_XA_RFInterfaceOE			0x860	/* RF Channel switch */
-+#define rFPGA0_XB_RFInterfaceOE			0x864
-+
-+#define rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
-+#define rFPGA0_XCD_RFInterfaceSW		0x874
-+
-+/* #define rFPGA0_XAB_RFParameter		0x878 */	/* RF Parameter
-+ * #define rFPGA0_XCD_RFParameter		0x87c */
-+
-+/* #define rFPGA0_AnalogParameter1		0x880 */	/* Crystal cap setting RF-R/W protection for parameter4??
-+ * #define rFPGA0_AnalogParameter2		0x884
-+ * #define rFPGA0_AnalogParameter3		0x888
-+ * #define rFPGA0_AdDaClockEn			0x888 */	/* enable ad/da clock1 for dual-phy
-+ * #define rFPGA0_AnalogParameter4		0x88c */
-+
-+
-+/* CCK TX scaling */
-+#define rCCK_TxFilter1_Jaguar		0xa20
-+#define bCCK_TxFilter1_C0_Jaguar	0x00ff0000
-+#define bCCK_TxFilter1_C1_Jaguar		0xff000000
-+#define rCCK_TxFilter2_Jaguar		0xa24
-+#define bCCK_TxFilter2_C2_Jaguar		0x000000ff
-+#define bCCK_TxFilter2_C3_Jaguar		0x0000ff00
-+#define bCCK_TxFilter2_C4_Jaguar		0x00ff0000
-+#define bCCK_TxFilter2_C5_Jaguar		0xff000000
-+#define rCCK_TxFilter3_Jaguar		0xa28
-+#define bCCK_TxFilter3_C6_Jaguar		0x000000ff
-+#define bCCK_TxFilter3_C7_Jaguar		0x0000ff00
-+
-+
-+/* YN: mask the following register definition temporarily
-+ * #define rPdp_AntA					0xb00
-+ * #define rPdp_AntA_4				0xb04
-+ * #define rConfig_Pmpd_AntA			0xb28
-+ * #define rConfig_AntA					0xb68
-+ * #define rConfig_AntB					0xb6c
-+ * #define rPdp_AntB					0xb70
-+ * #define rPdp_AntB_4					0xb74
-+ * #define rConfig_Pmpd_AntB			0xb98
-+ * #define rAPK							0xbd8 */
-+
-+/* RXIQC */
-+#define rA_RxIQC_AB_Jaguar    	0xc10  /* RxIQ imblance matrix coeff. A & B */
-+#define rA_RxIQC_CD_Jaguar    	0xc14  /* RxIQ imblance matrix coeff. C & D */
-+#define rA_TxScale_Jaguar 		0xc1c  /* Pah_A TX scaling factor */
-+#define rB_TxScale_Jaguar 		0xe1c  /* Path_B TX scaling factor */
-+#define rB_RxIQC_AB_Jaguar    	0xe10  /* RxIQ imblance matrix coeff. A & B */
-+#define rB_RxIQC_CD_Jaguar    	0xe14  /* RxIQ imblance matrix coeff. C & D */
-+#define b_RxIQC_AC_Jaguar		0x02ff  /* bit mask for IQC matrix element A & C */
-+#define b_RxIQC_BD_Jaguar		0x02ff0000 /* bit mask for IQC matrix element A & C */
-+
-+
-+/* DIG-related */
-+#define rA_IGI_Jaguar				0xc50	/* Initial Gain for path-A */
-+#define rB_IGI_Jaguar				0xe50	/* Initial Gain for path-B */
-+#define rOFDM_FalseAlarm1_Jaguar	0xf48  /* counter for break */
-+#define rOFDM_FalseAlarm2_Jaguar	0xf4c  /* counter for spoofing */
-+#define rCCK_FalseAlarm_Jaguar        	0xa5c /* counter for cck false alarm */
-+#define b_FalseAlarm_Jaguar			0xffff
-+#define rCCK_CCA_Jaguar				0xa08	/* cca threshold */
-+#define bCCK_CCA_Jaguar				0x00ff0000
-+
-+/* Tx Power Ttraining-related */
-+#define rA_TxPwrTraing_Jaguar		0xc54
-+#define rB_TxPwrTraing_Jaguar		0xe54
-+
-+/* Report-related */
-+#define rOFDM_ShortCFOAB_Jaguar	0xf60
-+#define rOFDM_LongCFOAB_Jaguar		0xf64
-+#define rOFDM_EndCFOAB_Jaguar		0xf70
-+#define rOFDM_AGCReport_Jaguar		0xf84
-+#define rOFDM_RxSNR_Jaguar			0xf88
-+#define rOFDM_RxEVMCSI_Jaguar		0xf8c
-+#define rOFDM_SIGReport_Jaguar		0xf90
-+
-+/* Misc functions */
-+#define rEDCCA_Jaguar				0x8a4 /* EDCCA */
-+#define bEDCCA_Jaguar				0xffff
-+#define rAGC_table_Jaguar			0x82c   /* AGC tabel select */
-+#define bAGC_table_Jaguar			0x3
-+#define b_sel5g_Jaguar    				0x1000 /* sel5g */
-+#define b_LNA_sw_Jaguar				0x8000 /* HW/WS control for LNA */
-+#define rFc_area_Jaguar				0x860   /* fc_area */
-+#define bFc_area_Jaguar				0x1ffe000
-+#define rSingleTone_ContTx_Jaguar	0x914
-+
-+/* RFE */
-+#define rA_RFE_Pinmux_Jaguar	0xcb0  /* Path_A RFE cotrol pinmux */
-+#define rB_RFE_Pinmux_Jaguar	0xeb0 /* Path_B RFE control pinmux */
-+#define rA_RFE_Inv_Jaguar		0xcb4  /* Path_A RFE cotrol   */
-+#define rB_RFE_Inv_Jaguar		0xeb4 /* Path_B RFE control */
-+#define rA_RFE_Jaguar			0xcb8  /* Path_A RFE cotrol   */
-+#define rB_RFE_Jaguar			0xeb8 /* Path_B RFE control */
-+#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
-+#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
-+#define r_ANTSEL_SW_Jaguar		0x900 /* ANTSEL SW Control */
-+#define bMask_RFEInv_Jaguar		0x3ff00000
-+#define bMask_AntselPathFollow_Jaguar 0x00030000
-+
-+/* TX AGC */
-+#define rTxAGC_A_CCK11_CCK1_JAguar				0xc20
-+#define rTxAGC_A_Ofdm18_Ofdm6_JAguar				0xc24
-+#define rTxAGC_A_Ofdm54_Ofdm24_JAguar			0xc28
-+#define rTxAGC_A_MCS3_MCS0_JAguar					0xc2c
-+#define rTxAGC_A_MCS7_MCS4_JAguar					0xc30
-+#define rTxAGC_A_MCS11_MCS8_JAguar				0xc34
-+#define rTxAGC_A_MCS15_MCS12_JAguar				0xc38
-+#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar	0xc3c
-+#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar	0xc40
-+#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar	0xc44
-+#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar	0xc48
-+#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar	0xc4c
-+#define rTxAGC_B_CCK11_CCK1_JAguar				0xe20
-+#define rTxAGC_B_Ofdm18_Ofdm6_JAguar				0xe24
-+#define rTxAGC_B_Ofdm54_Ofdm24_JAguar			0xe28
-+#define rTxAGC_B_MCS3_MCS0_JAguar					0xe2c
-+#define rTxAGC_B_MCS7_MCS4_JAguar					0xe30
-+#define rTxAGC_B_MCS11_MCS8_JAguar				0xe34
-+#define rTxAGC_B_MCS15_MCS12_JAguar				0xe38
-+#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar		0xe3c
-+#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar		0xe40
-+#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar		0xe44
-+#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar		0xe48
-+#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar		0xe4c
-+#define bTxAGC_byte0_Jaguar							0xff
-+#define bTxAGC_byte1_Jaguar							0xff00
-+#define bTxAGC_byte2_Jaguar							0xff0000
-+#define bTxAGC_byte3_Jaguar							0xff000000
-+
-+/* IQK YN: temporaily mask this part
-+ * #define rFPGA0_IQK					0xe28
-+ * #define rTx_IQK_Tone_A				0xe30
-+ * #define rRx_IQK_Tone_A				0xe34
-+ * #define rTx_IQK_PI_A					0xe38
-+ * #define rRx_IQK_PI_A					0xe3c */
-+
-+/* #define rTx_IQK						0xe40 */
-+/* #define rRx_IQK						0xe44 */
-+/* #define rIQK_AGC_Pts					0xe48 */
-+/* #define rIQK_AGC_Rsp					0xe4c */
-+/* #define rTx_IQK_Tone_B				0xe50 */
-+/* #define rRx_IQK_Tone_B				0xe54 */
-+/* #define rTx_IQK_PI_B					0xe58 */
-+/* #define rRx_IQK_PI_B					0xe5c */
-+/* #define rIQK_AGC_Cont				0xe60 */
-+
-+
-+/* AFE-related */
-+#define rA_AFEPwr1_Jaguar					0xc60 /* dynamic AFE power control */
-+#define rA_AFEPwr2_Jaguar					0xc64 /* dynamic AFE power control */
-+#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar	0xc68
-+#define rA_Tx_CCKBBON_OFDMRFON_Jaguar	0xc6c
-+#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar		0xc70
-+#define rA_Tx2Tx_RXCCK_Jaguar				0xc74
-+#define rA_Rx_OFDM_WaitRIFS_Jaguar			0xc78
-+#define rA_Rx2Rx_BT_Jaguar					0xc7c
-+#define rA_sleep_nav_Jaguar					0xc80
-+#define rA_pmpd_Jaguar						0xc84
-+#define rB_AFEPwr1_Jaguar					0xe60 /* dynamic AFE power control */
-+#define rB_AFEPwr2_Jaguar					0xe64 /* dynamic AFE power control */
-+#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar	0xe68
-+#define rB_Tx_CCKBBON_OFDMRFON_Jaguar	0xe6c
-+#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar		0xe70
-+#define rB_Tx2Tx_RXCCK_Jaguar				0xe74
-+#define rB_Rx_OFDM_WaitRIFS_Jaguar			0xe78
-+#define rB_Rx2Rx_BT_Jaguar					0xe7c
-+#define rB_sleep_nav_Jaguar					0xe80
-+#define rB_pmpd_Jaguar						0xe84
-+
-+
-+/* YN: mask these registers temporaily
-+ * #define rTx_Power_Before_IQK_A		0xe94
-+ * #define rTx_Power_After_IQK_A			0xe9c */
-+
-+/* #define rRx_Power_Before_IQK_A		0xea0 */
-+/* #define rRx_Power_Before_IQK_A_2		0xea4 */
-+/* #define rRx_Power_After_IQK_A			0xea8 */
-+/* #define rRx_Power_After_IQK_A_2		0xeac */
-+
-+/* #define rTx_Power_Before_IQK_B		0xeb4 */
-+/* #define rTx_Power_After_IQK_B			0xebc */
-+
-+/* #define rRx_Power_Before_IQK_B		0xec0 */
-+/* #define rRx_Power_Before_IQK_B_2		0xec4 */
-+/* #define rRx_Power_After_IQK_B			0xec8 */
-+/* #define rRx_Power_After_IQK_B_2		0xecc */
-+
-+
-+/* RSSI Dump */
-+#define rA_RSSIDump_Jaguar			0xBF0
-+#define rB_RSSIDump_Jaguar			0xBF1
-+#define rS1_RXevmDump_Jaguar		0xBF4
-+#define rS2_RXevmDump_Jaguar		0xBF5
-+#define rA_RXsnrDump_Jaguar		0xBF6
-+#define rB_RXsnrDump_Jaguar		0xBF7
-+#define rA_CfoShortDump_Jaguar		0xBF8
-+#define rB_CfoShortDump_Jaguar		0xBFA
-+#define rA_CfoLongDump_Jaguar		0xBEC
-+#define rB_CfoLongDump_Jaguar		0xBEE
-+
-+
-+/* RF Register
-+ *   */
-+#define RF_AC_Jaguar				0x00	/*  */
-+#define RF_RF_Top_Jaguar			0x07	/*  */
-+#define RF_TXLOK_Jaguar				0x08	/*  */
-+#define RF_TXAPK_Jaguar				0x0B
-+#define RF_CHNLBW_Jaguar 			0x18	/* RF channel and BW switch */
-+#define RF_RCK1_Jaguar				0x1c	/*  */
-+#define RF_RCK2_Jaguar				0x1d
-+#define RF_RCK3_Jaguar			0x1e
-+#define RF_ModeTableAddr			0x30
-+#define RF_ModeTableData0			0x31
-+#define RF_ModeTableData1			0x32
-+#define RF_TxLCTank_Jaguar	0x54
-+#define RF_APK_Jaguar				0x63
-+#define RF_LCK						0xB4
-+#define RF_WeLut_Jaguar				0xEF
-+
-+#define bRF_CHNLBW_MOD_AG_Jaguar	0x70300
-+#define bRF_CHNLBW_BW				0xc00
-+
-+
-+/*
-+ * RL6052 Register definition
-+ *   */
-+#define RF_AC						0x00	/*  */
-+#define RF_IPA_A					0x0C	/*  */
-+#define RF_TXBIAS_A					0x0D
-+#define RF_BS_PA_APSET_G9_G11		0x0E
-+#define RF_MODE1					0x10	/*  */
-+#define RF_MODE2					0x11	/*  */
-+#define RF_CHNLBW					0x18	/* RF channel and BW switch */
-+#define RF_RCK_OS					0x30	/* RF TX PA control */
-+#define RF_TXPA_G1					0x31	/* RF TX PA control */
-+#define RF_TXPA_G2					0x32	/* RF TX PA control */
-+#define RF_TXPA_G3					0x33	/* RF TX PA control */
-+#define RF_0x52						0x52
-+#define RF_WE_LUT					0xEF
-+
-+#define RF_TX_GAIN_OFFSET_8812A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
-+#define RF_TX_GAIN_OFFSET_8821A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
-+
-+/*
-+ * Bit Mask
-+ *
-+ * 1. Page1(0x100) */
-+#define bBBResetB					0x100	/* Useless now? */
-+#define bGlobalResetB				0x200
-+#define bOFDMTxStart				0x4
-+#define bCCKTxStart					0x8
-+#define bCRC32Debug					0x100
-+#define bPMACLoopback				0x10
-+#define bTxLSIG						0xffffff
-+#define bOFDMTxRate					0xf
-+#define bOFDMTxReserved			0x10
-+#define bOFDMTxLength				0x1ffe0
-+#define bOFDMTxParity				0x20000
-+#define bTxHTSIG1					0xffffff
-+#define bTxHTMCSRate				0x7f
-+#define bTxHTBW						0x80
-+#define bTxHTLength					0xffff00
-+#define bTxHTSIG2					0xffffff
-+#define bTxHTSmoothing				0x1
-+#define bTxHTSounding				0x2
-+#define bTxHTReserved				0x4
-+#define bTxHTAggreation				0x8
-+#define bTxHTSTBC					0x30
-+#define bTxHTAdvanceCoding			0x40
-+#define bTxHTShortGI					0x80
-+#define bTxHTNumberHT_LTF			0x300
-+#define bTxHTCRC8					0x3fc00
-+#define bCounterReset				0x10000
-+#define bNumOfOFDMTx				0xffff
-+#define bNumOfCCKTx					0xffff0000
-+#define bTxIdleInterval				0xffff
-+#define bOFDMService				0xffff0000
-+#define bTxMACHeader				0xffffffff
-+#define bTxDataInit					0xff
-+#define bTxHTMode					0x100
-+#define bTxDataType					0x30000
-+#define bTxRandomSeed				0xffffffff
-+#define bCCKTxPreamble				0x1
-+#define bCCKTxSFD					0xffff0000
-+#define bCCKTxSIG					0xff
-+#define bCCKTxService				0xff00
-+#define bCCKLengthExt				0x8000
-+#define bCCKTxLength				0xffff0000
-+#define bCCKTxCRC16					0xffff
-+#define bCCKTxStatus					0x1
-+#define bOFDMTxStatus				0x2
-+
-+
-+/*
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 1. Page1(0x100)
-+ *   */
-+#define rPMAC_Reset					0x100
-+#define rPMAC_TxStart				0x104
-+#define rPMAC_TxLegacySIG			0x108
-+#define rPMAC_TxHTSIG1				0x10c
-+#define rPMAC_TxHTSIG2				0x110
-+#define rPMAC_PHYDebug				0x114
-+#define rPMAC_TxPacketNum			0x118
-+#define rPMAC_TxIdle					0x11c
-+#define rPMAC_TxMACHeader0			0x120
-+#define rPMAC_TxMACHeader1			0x124
-+#define rPMAC_TxMACHeader2			0x128
-+#define rPMAC_TxMACHeader3			0x12c
-+#define rPMAC_TxMACHeader4			0x130
-+#define rPMAC_TxMACHeader5			0x134
-+#define rPMAC_TxDataType			0x138
-+#define rPMAC_TxRandomSeed		0x13c
-+#define rPMAC_CCKPLCPPreamble		0x140
-+#define rPMAC_CCKPLCPHeader		0x144
-+#define rPMAC_CCKCRC16				0x148
-+#define rPMAC_OFDMRxCRC32OK		0x170
-+#define rPMAC_OFDMRxCRC32Er		0x174
-+#define rPMAC_OFDMRxParityEr		0x178
-+#define rPMAC_OFDMRxCRC8Er			0x17c
-+#define rPMAC_CCKCRxRC16Er			0x180
-+#define rPMAC_CCKCRxRC32Er			0x184
-+#define rPMAC_CCKCRxRC32OK			0x188
-+#define rPMAC_TxStatus				0x18c
-+
-+/*
-+ * 3. Page8(0x800)
-+ *   */
-+#define rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
-+
-+#define rFPGA0_TxInfo				0x804	/* Status report?? */
-+#define rFPGA0_PSDFunction			0x808
-+#define rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
-+
-+#define rFPGA0_XA_HSSIParameter1	0x820	/* RF 3 wire register */
-+#define rFPGA0_XA_HSSIParameter2	0x824
-+#define rFPGA0_XB_HSSIParameter1	0x828
-+#define rFPGA0_XB_HSSIParameter2	0x82c
-+
-+#define rFPGA0_XAB_SwitchControl	0x858	/* RF Channel switch */
-+#define rFPGA0_XCD_SwitchControl	0x85c
-+
-+#define rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
-+#define rFPGA0_XCD_RFParameter		0x87c
-+
-+#define rFPGA0_AnalogParameter1	0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
-+#define rFPGA0_AnalogParameter2	0x884
-+#define rFPGA0_AnalogParameter3	0x888
-+#define rFPGA0_AdDaClockEn			0x888	/* enable ad/da clock1 for dual-phy */
-+#define rFPGA0_AnalogParameter4	0x88c
-+#define rFPGA0_XB_LSSIReadBack		0x8a4
-+#define rFPGA0_XCD_RFPara	0x8b4
-+
-+/*
-+ * 4. Page9(0x900)
-+ *   */
-+#define rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
-+
-+#define rFPGA1_TxBlock				0x904	/* Useless now */
-+#define rFPGA1_DebugSelect			0x908	/* Useless now */
-+#define rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
-+
-+/*
-+ * PageA(0xA00)
-+ *   */
-+#define rCCK0_System				0xa00
-+#define rCCK0_AFESetting				0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
-+#define	rCCK0_DSPParameter2			0xa1c	/* SQ threshold */
-+#define rCCK0_TxFilter1				0xa20
-+#define rCCK0_TxFilter2				0xa24
-+#define rCCK0_DebugPort				0xa28	/* debug port and Tx filter3 */
-+#define	rCCK0_FalseAlarmReport			0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
-+
-+/*
-+ * PageB(0xB00)
-+ *   */
-+#define rPdp_AntA				0xb00
-+#define rPdp_AntA_4				0xb04
-+#define rConfig_Pmpd_AntA			0xb28
-+#define rConfig_AntA					0xb68
-+#define rConfig_AntB					0xb6c
-+#define rPdp_AntB					0xb70
-+#define rPdp_AntB_4					0xb74
-+#define rConfig_Pmpd_AntB			0xb98
-+#define rAPK							0xbd8
-+
-+/*
-+ * 6. PageC(0xC00)
-+ *   */
-+#define rOFDM0_LSTF					0xc00
-+
-+#define rOFDM0_TRxPathEnable		0xc04
-+#define rOFDM0_TRMuxPar			0xc08
-+#define rOFDM0_TRSWIsolation		0xc0c
-+
-+#define rOFDM0_XARxAFE				0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
-+#define rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
-+#define rOFDM0_XBRxAFE		0xc18
-+#define rOFDM0_XBRxIQImbalance	0xc1c
-+#define rOFDM0_XCRxAFE		0xc20
-+#define rOFDM0_XCRxIQImbalance	0xc24
-+#define rOFDM0_XDRxAFE		0xc28
-+#define rOFDM0_XDRxIQImbalance	0xc2c
-+
-+#define rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
-+#define rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
-+#define rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
-+#define rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
-+
-+#define rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
-+#define rOFDM0_CFOandDAGC			0xc44  /* CFO & DAGC */
-+#define rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
-+#define rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
-+
-+#define rOFDM0_XAAGCCore1			0xc50	/* DIG */
-+#define rOFDM0_XAAGCCore2			0xc54
-+#define rOFDM0_XBAGCCore1			0xc58
-+#define rOFDM0_XBAGCCore2			0xc5c
-+#define rOFDM0_XCAGCCore1			0xc60
-+#define rOFDM0_XCAGCCore2			0xc64
-+#define rOFDM0_XDAGCCore1			0xc68
-+#define rOFDM0_XDAGCCore2			0xc6c
-+
-+#define rOFDM0_AGCParameter1		0xc70
-+#define rOFDM0_AGCParameter2		0xc74
-+#define rOFDM0_AGCRSSITable		0xc78
-+#define rOFDM0_HTSTFAGC			0xc7c
-+
-+#define rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
-+#define rOFDM0_XATxAFE				0xc84
-+#define rOFDM0_XBTxIQImbalance		0xc88
-+#define rOFDM0_XBTxAFE				0xc8c
-+#define rOFDM0_XCTxIQImbalance		0xc90
-+#define rOFDM0_XCTxAFE		0xc94
-+#define rOFDM0_XDTxIQImbalance		0xc98
-+#define rOFDM0_XDTxAFE				0xc9c
-+
-+#define rOFDM0_RxIQExtAnta			0xca0
-+#define rOFDM0_TxCoeff1				0xca4
-+#define rOFDM0_TxCoeff2				0xca8
-+#define rOFDM0_TxCoeff3				0xcac
-+#define rOFDM0_TxCoeff4				0xcb0
-+#define rOFDM0_TxCoeff5				0xcb4
-+#define rOFDM0_TxCoeff6				0xcb8
-+#define rOFDM0_RxHPParameter		0xce0
-+#define rOFDM0_TxPseudoNoiseWgt	0xce4
-+#define rOFDM0_FrameSync			0xcf0
-+#define rOFDM0_DFSReport			0xcf4
-+
-+/*
-+ * 7. PageD(0xD00)
-+ *   */
-+#define rOFDM1_LSTF					0xd00
-+#define rOFDM1_TRxPathEnable		0xd04
-+
-+/*
-+ * 8. PageE(0xE00)
-+ *   */
-+#define rTxAGC_A_Rate18_06			0xe00
-+#define rTxAGC_A_Rate54_24			0xe04
-+#define rTxAGC_A_CCK1_Mcs32		0xe08
-+#define rTxAGC_A_Mcs03_Mcs00		0xe10
-+#define rTxAGC_A_Mcs07_Mcs04		0xe14
-+#define rTxAGC_A_Mcs11_Mcs08		0xe18
-+#define rTxAGC_A_Mcs15_Mcs12		0xe1c
-+
-+#define rTxAGC_B_Rate18_06			0x830
-+#define rTxAGC_B_Rate54_24			0x834
-+#define rTxAGC_B_CCK1_55_Mcs32	0x838
-+#define rTxAGC_B_Mcs03_Mcs00		0x83c
-+#define rTxAGC_B_Mcs07_Mcs04		0x848
-+#define rTxAGC_B_Mcs11_Mcs08		0x84c
-+#define rTxAGC_B_Mcs15_Mcs12		0x868
-+#define rTxAGC_B_CCK11_A_CCK2_11	0x86c
-+
-+#define rFPGA0_IQK					0xe28
-+#define rTx_IQK_Tone_A				0xe30
-+#define rRx_IQK_Tone_A				0xe34
-+#define rTx_IQK_PI_A				0xe38
-+#define rRx_IQK_PI_A				0xe3c
-+
-+#define rTx_IQK						0xe40
-+#define rRx_IQK						0xe44
-+#define rIQK_AGC_Pts					0xe48
-+#define rIQK_AGC_Rsp				0xe4c
-+#define rTx_IQK_Tone_B				0xe50
-+#define rRx_IQK_Tone_B				0xe54
-+#define rTx_IQK_PI_B					0xe58
-+#define rRx_IQK_PI_B					0xe5c
-+#define rIQK_AGC_Cont				0xe60
-+
-+#define rBlue_Tooth					0xe6c
-+#define rRx_Wait_CCA				0xe70
-+#define rTx_CCK_RFON				0xe74
-+#define rTx_CCK_BBON				0xe78
-+#define rTx_OFDM_RFON				0xe7c
-+#define rTx_OFDM_BBON				0xe80
-+#define rTx_To_Rx					0xe84
-+#define rTx_To_Tx					0xe88
-+#define rRx_CCK						0xe8c
-+
-+#define rTx_Power_Before_IQK_A		0xe94
-+#define rTx_Power_After_IQK_A		0xe9c
-+
-+#define rRx_Power_Before_IQK_A		0xea0
-+#define rRx_Power_Before_IQK_A_2	0xea4
-+#define rRx_Power_After_IQK_A		0xea8
-+#define rRx_Power_After_IQK_A_2		0xeac
-+
-+#define rTx_Power_Before_IQK_B		0xeb4
-+#define rTx_Power_After_IQK_B		0xebc
-+
-+#define rRx_Power_Before_IQK_B		0xec0
-+#define rRx_Power_Before_IQK_B_2	0xec4
-+#define rRx_Power_After_IQK_B		0xec8
-+#define rRx_Power_After_IQK_B_2		0xecc
-+
-+#define rRx_OFDM					0xed0
-+#define rRx_Wait_RIFS				0xed4
-+#define rRx_TO_Rx					0xed8
-+#define rStandby						0xedc
-+#define rSleep						0xee0
-+#define rPMPD_ANAEN				0xeec
-+
-+
-+/* 2. Page8(0x800) */
-+#define bRFMOD						0x1	/* Reg 0x800 rFPGA0_RFMOD */
-+#define bJapanMode					0x2
-+#define bCCKTxSC					0x30
-+#define bCCKEn						0x1000000
-+#define bOFDMEn						0x2000000
-+#define bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
-+#define bXCTxAGC			0xf000
-+#define bXDTxAGC			0xf0000
-+
-+/* 4. PageA(0xA00) */
-+#define bCCKBBMode                			0x3	/* Useless */
-+#define bCCKTxPowerSaving		0x80
-+#define bCCKRxPowerSaving		0x40
-+
-+#define bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
-+
-+#define bCCKScramble              		0x8	/* Useless */
-+#define bCCKAntDiversity			0x8000
-+#define bCCKCarrierRecovery		0x4000
-+#define bCCKTxRate			0x3000
-+#define bCCKDCCancel			0x0800
-+#define bCCKISICancel			0x0400
-+#define bCCKMatchFilter		0x0200
-+#define bCCKEqualizer			0x0100
-+#define bCCKPreambleDetect		0x800000
-+#define bCCKFastFalseCCA		0x400000
-+#define bCCKChEstStart		0x300000
-+#define bCCKCCACount		0x080000
-+#define bCCKcs_lim			0x070000
-+#define bCCKBistMode			0x80000000
-+#define bCCKCCAMask			0x40000000
-+#define bCCKTxDACPhase		0x4
-+#define bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
-+#define bCCKr_cp_mode0		0x0100
-+#define bCCKTxDCOffset		0xf0
-+#define bCCKRxDCOffset		0xf
-+#define bCCKCCAMode			0xc000
-+#define bCCKFalseCS_lim		0x3f00
-+#define bCCKCS_ratio			0xc00000
-+#define bCCKCorgBit_sel		0x300000
-+#define bCCKPD_lim			0x0f0000
-+#define bCCKNewCCA		0x80000000
-+#define bCCKRxHPofIG		0x8000
-+#define bCCKRxIG			0x7f00
-+#define bCCKLNAPolarity		0x800000
-+#define bCCKRx1stGain		0x7f0000
-+#define bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
-+#define bCCKRxAGCSatLevel		0x1f000000
-+#define bCCKRxAGCSatCount		0xe0
-+#define bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
-+#define bCCKFixedRxAGC		0x8000
-+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
-+#define bCCKAntennaPolarity		0x2000
-+#define bCCKTxFilterType		0x0c00
-+#define bCCKRxAGCReportType		0x0300
-+#define bCCKRxDAGCEn		0x80000000
-+#define bCCKRxDAGCPeriod		0x20000000
-+#define bCCKRxDAGCSatLevel		0x1f000000
-+#define bCCKTimingRecovery		0x800000
-+#define bCCKTxC0			0x3f0000
-+#define bCCKTxC1			0x3f000000
-+#define bCCKTxC2			0x3f
-+#define bCCKTxC3			0x3f00
-+#define bCCKTxC4			0x3f0000
-+#define bCCKTxC5			0x3f000000
-+#define bCCKTxC6			0x3f
-+#define bCCKTxC7			0x3f00
-+#define bCCKDebugPort		0xff0000
-+#define bCCKDACDebug		0x0f000000
-+#define bCCKFalseAlarmEnable		0x8000
-+#define bCCKFalseAlarmRead		0x4000
-+#define bCCKTRSSI			0x7f
-+#define bCCKRxAGCReport		0xfe
-+#define bCCKRxReport_AntSel		0x80000000
-+#define bCCKRxReport_MFOff		0x40000000
-+#define bCCKRxRxReport_SQLoss	0x20000000
-+#define bCCKRxReport_Pktloss		0x10000000
-+#define bCCKRxReport_Lockedbit	0x08000000
-+#define bCCKRxReport_RateError	0x04000000
-+#define bCCKRxReport_RxRate		0x03000000
-+#define bCCKRxFACounterLower	0xff
-+#define bCCKRxFACounterUpper	0xff000000
-+#define bCCKRxHPAGCStart		0xe000
-+#define bCCKRxHPAGCFinal		0x1c00
-+#define bCCKRxFalseAlarmEnable	0x8000
-+#define bCCKFACounterFreeze		0x4000
-+#define bCCKTxPathSel		0x10000000
-+#define bCCKDefaultRxPath		0xc000000
-+#define bCCKOptionRxPath		0x3000000
-+
-+/* 6. PageE(0xE00) */
-+#define bSTBCEn                  			0x4	/* Useless */
-+#define bAntennaMapping		0x10
-+#define bNss				0x20
-+#define bCFOAntSumD		0x200
-+#define bPHYCounterReset		0x8000000
-+#define bCFOReportGet			0x4000000
-+#define bOFDMContinueTx		0x10000000
-+#define bOFDMSingleCarrier		0x20000000
-+#define bOFDMSingleTone		0x40000000
-+
-+
-+/*
-+ * Other Definition
-+ *   */
-+
-+#define bEnable                   0x1	/* Useless */
-+#define bDisable                  0x0
-+
-+/* byte endable for srwrite */
-+#define bByte0                    		0x1	/* Useless */
-+#define bByte1		0x2
-+#define bByte2		0x4
-+#define bByte3		0x8
-+#define bWord0		0x3
-+#define bWord1		0xc
-+#define bDWord		0xf
-+
-+/* for PutRegsetting & GetRegSetting BitMask */
-+#define bMaskByte0                		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
-+#define bMaskByte1		0xff00
-+#define bMaskByte2		0xff0000
-+#define bMaskByte3		0xff000000
-+#define bMaskHWord	0xffff0000
-+#define bMaskLWord		0x0000ffff
-+#define bMaskDWord	0xffffffff
-+#define bMaskH3Bytes				0xffffff00
-+#define bMask12Bits				0xfff
-+#define bMaskH4Bits				0xf0000000
-+#define bMaskOFDM_D			0xffc00000
-+#define bMaskCCK				0x3f3f3f3f
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8812PwrSeq.h b/drivers/staging/rtl8723cs/include/Hal8812PwrSeq.h
-new file mode 100644
-index 000000000000..498faf8114ae
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8812PwrSeq.h
-@@ -0,0 +1,208 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+#ifndef __HAL8812PWRSEQ_H__
-+#define __HAL8812PWRSEQ_H__
-+
-+#include "HalPwrSeqCmd.h"
-+
-+/*
-+	Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
-+	There are 6 HW Power States:
-+	0: POFF--Power Off
-+	1: PDN--Power Down
-+	2: CARDEMU--Card Emulation
-+	3: ACT--Active Mode
-+	4: LPS--Low Power State
-+	5: SUS--Suspend
-+
-+	The transision from different states are defined below
-+	TRANS_CARDEMU_TO_ACT
-+	TRANS_ACT_TO_CARDEMU
-+	TRANS_CARDEMU_TO_SUS
-+	TRANS_SUS_TO_CARDEMU
-+	TRANS_CARDEMU_TO_PDN
-+	TRANS_ACT_TO_LPS
-+	TRANS_LPS_TO_ACT
-+
-+	TRANS_END
-+*/
-+#define	RTL8812_TRANS_CARDEMU_TO_ACT_STEPS	15
-+#define	RTL8812_TRANS_ACT_TO_CARDEMU_STEPS	15
-+#define	RTL8812_TRANS_CARDEMU_TO_SUS_STEPS	15
-+#define	RTL8812_TRANS_SUS_TO_CARDEMU_STEPS	15
-+#define	RTL8812_TRANS_CARDEMU_TO_PDN_STEPS	15
-+#define	RTL8812_TRANS_PDN_TO_CARDEMU_STEPS	15
-+#define	RTL8812_TRANS_ACT_TO_LPS_STEPS	15
-+#define	RTL8812_TRANS_LPS_TO_ACT_STEPS	15
-+#define	RTL8812_TRANS_END_STEPS	1
-+
-+
-+#define RTL8812_TRANS_CARDEMU_TO_ACT														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
-+	/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, disable HWPDN 0x04[15]=0*/ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/   \
-+	{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x24[1] Choose the type of buffer after xosc: nand*/   \
-+	{0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /* 0x28[33] Choose the type of buffer after xosc: nand*/
-+
-+#define RTL8812_TRANS_ACT_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4	turn off 3-wire */	\
-+	{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4	turn off 3-wire */	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0	 RESET BB, CLOSE RF */	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
-+	/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},//0x1F[7:0] = 0 turn off RF*/	\
-+	/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},//0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/	\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */	\
-+	/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0}, //  0x02[1:0] = 0	reset BB */	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
-+
-+#define RTL8812_TRANS_CARDEMU_TO_SUS													\
-+	/* format */								\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\
-+	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\
-+	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */	\
-+	{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */	\
-+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */	\
-+	{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */	\
-+	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */	\
-+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */	\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'11 enable WL suspend for PCIe*/
-+
-+#define RTL8812_TRANS_SUS_TO_CARDEMU													\
-+	/* format */								\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/   \
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */	\
-+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */	\
-+	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */	\
-+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */	\
-+	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
-+
-+#define RTL8812_TRANS_CARDEMU_TO_CARDDIS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	/**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/	\
-+	/**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/	\
-+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 8051*/	\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/	\
-+	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\
-+	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\
-+	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */	\
-+	{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */	\
-+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */	\
-+	{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */	\
-+	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */	\
-+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */	\
-+	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/*0x12[0] = 0 force PFM mode */	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */	\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
-+	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x01f[1]=0 , disable RFC_0  control  REG_RF_CTRL_8812 */	\
-+	{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x076[1]=0 , disable RFC_1  control REG_OPT_CTRL_8812 +2 */	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'01 enable WL suspend*/
-+
-+#define RTL8812_TRANS_CARDDIS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/                       \
-+	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x12[0] = 1 force PWM mode */	\
-+	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */	\
-+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */	\
-+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */	\
-+	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/	\
-+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x03[2] = 1, enable 8051*/	\
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/  \
-+	{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /* 0x24[1] Choose the type of buffer after xosc: schmitt trigger*/ \
-+	{0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x28[33] Choose the type of buffer after xosc: schmitt trigger*/
-+
-+
-+#define RTL8812_TRANS_CARDEMU_TO_PDN												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
-+
-+#define RTL8812_TRANS_PDN_TO_CARDEMU												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
-+
-+#define RTL8812_TRANS_ACT_TO_LPS														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/		\
-+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4	turn off 3-wire */	\
-+	{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4	turn off 3-wire */	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/			\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/		\
-+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
-+
-+
-+#define RTL8812_TRANS_LPS_TO_ACT															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/	\
-+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/	\
-+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/	\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/	\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/			\
-+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/	\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/					\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/	\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
-+
-+#define RTL8812_TRANS_END																\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/		\
-+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
-+
-+
-+extern WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS + RTL8812_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];
-+
-+#endif /* __HAL8812PWRSEQ_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/Hal8814PhyCfg.h b/drivers/staging/rtl8723cs/include/Hal8814PhyCfg.h
-new file mode 100644
-index 000000000000..0fdc340774c1
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8814PhyCfg.h
-@@ -0,0 +1,236 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8814PHYCFG_H__
-+#define __INC_HAL8814PHYCFG_H__
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+#define LOOP_LIMIT				5
-+#define MAX_STALL_TIME			50		/* us */
-+#define AntennaDiversityValue	0x80	/* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
-+#define MAX_TXPWR_IDX_NMODE_92S	63
-+#define Reset_Cnt_Limit			3
-+
-+
-+#ifdef CONFIG_PCI_HCI
-+	#define MAX_AGGR_NUM	0x0B
-+#else
-+	#define MAX_AGGR_NUM	0x07
-+#endif /* CONFIG_PCI_HCI */
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+
-+/* BB/RF related */
-+
-+#define	SIC_ENABLE				0
-+
-+/*------------------------------Define structure----------------------------*/
-+
-+
-+/*------------------------Export global variable----------------------------*/
-+/*------------------------Export global variable----------------------------*/
-+
-+
-+/*------------------------Export Marco Definition---------------------------*/
-+/*------------------------Export Marco Definition---------------------------*/
-+
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+/* 1. BB register R/W API */
-+
-+extern	u32
-+PHY_QueryBBReg8814A(PADAPTER	Adapter,
-+			u32		RegAddr,
-+			u32		BitMask);
-+
-+
-+void
-+PHY_SetBBReg8814A(PADAPTER	Adapter,
-+			u32		RegAddr,
-+			u32		BitMask,
-+			u32		Data);
-+
-+
-+extern	u32
-+PHY_QueryRFReg8814A(PADAPTER			Adapter,
-+			enum rf_path	eRFPath,
-+			u32			RegAddr,
-+			u32			BitMask);
-+
-+
-+void
-+PHY_SetRFReg8814A(PADAPTER			Adapter,
-+			enum rf_path		eRFPath,
-+			u32				RegAddr,
-+			u32				BitMask,
-+			u32				Data);
-+
-+/* 1 3. Initial BB/RF config by reading MAC/BB/RF txt. */
-+s32
-+phy_BB8814A_Config_ParaFile(
-+		PADAPTER	Adapter
-+);
-+
-+void
-+PHY_ConfigBB_8814A(
-+		PADAPTER	Adapter
-+);
-+
-+
-+void
-+phy_ADC_CLK_8814A(
-+		PADAPTER	Adapter
-+);
-+
-+s32
-+PHY_RFConfig8814A(
-+		PADAPTER	Adapter
-+);
-+
-+/*
-+ * RF Power setting
-+ *
-+ * BOOLEAN	PHY_SetRFPowerState8814A(PADAPTER Adapter, rt_rf_power_state	eRFPowerState); */
-+
-+/* 1 5. Tx  Power setting API */
-+
-+void
-+PHY_SetTxPowerLevel8814(
-+		PADAPTER		Adapter,
-+		u8			Channel
-+);
-+
-+u8
-+phy_get_tx_power_index_8814a(
-+		PADAPTER		Adapter,
-+		enum rf_path		RFPath,
-+		u8				Rate,
-+		enum channel_width BandWidth,
-+		u8				Channel
-+);
-+
-+void
-+PHY_SetTxPowerIndex_8814A(
-+		PADAPTER		Adapter,
-+		u32				PowerIndex,
-+		enum rf_path		RFPath,
-+		u8				Rate
-+);
-+
-+u32
-+PHY_GetTxBBSwing_8814A(
-+		PADAPTER	Adapter,
-+		BAND_TYPE	Band,
-+		enum rf_path	RFPath
-+);
-+
-+
-+
-+/* 1 6. Channel setting API */
-+#if 0
-+void
-+PHY_SwChnlTimerCallback8814A(
-+		struct timer_list		*p_timer
-+);
-+#endif
-+void
-+PHY_SwChnlWorkItemCallback8814A(
-+		void *pContext
-+);
-+
-+
-+void
-+HAL_HandleSwChnl8814A(
-+		PADAPTER	pAdapter,
-+		u8		channel
-+);
-+
-+void
-+PHY_SwChnlSynchronously8814A(PADAPTER		pAdapter,
-+				u8			channel);
-+
-+void
-+PHY_HandleSwChnlAndSetBW8814A(
-+		PADAPTER			Adapter,
-+		BOOLEAN				bSwitchChannel,
-+		BOOLEAN				bSetBandWidth,
-+		u8					ChannelNum,
-+		enum channel_width	ChnlWidth,
-+		u8					ChnlOffsetOf40MHz,
-+		u8					ChnlOffsetOf80MHz,
-+		u8					CenterFrequencyIndex1
-+);
-+
-+
-+BOOLEAN
-+PHY_QueryRFPathSwitch_8814A(PADAPTER	pAdapter);
-+
-+
-+
-+#if (USE_WORKITEM)
-+void
-+RtCheckForHangWorkItemCallback8814A(
-+		void *pContext
-+);
-+#endif
-+
-+BOOLEAN
-+SetAntennaConfig8814A(
-+		PADAPTER	Adapter,
-+		u8		DefaultAnt
-+);
-+
-+void
-+PHY_SetRFEReg8814A(
-+		PADAPTER		Adapter,
-+		BOOLEAN		bInit,
-+		u8		Band
-+);
-+
-+
-+s32
-+PHY_SwitchWirelessBand8814A(
-+		PADAPTER		 Adapter,
-+		u8		Band
-+);
-+
-+void
-+PHY_SetIO_8814A(
-+	PADAPTER		pAdapter
-+);
-+
-+void
-+PHY_SetSwChnlBWMode8814(
-+		PADAPTER			Adapter,
-+		u8					channel,
-+		enum channel_width	Bandwidth,
-+		u8					Offset40,
-+		u8					Offset80
-+);
-+
-+s32 PHY_MACConfig8814(PADAPTER Adapter);
-+int PHY_BBConfig8814(PADAPTER	Adapter);
-+void PHY_Set_SecCCATH_by_RXANT_8814A(PADAPTER	pAdapter, u32 ulAntennaRx);
-+
-+
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+#endif /* __INC_HAL8192CPHYCFG_H */
-diff --git a/drivers/staging/rtl8723cs/include/Hal8814PhyReg.h b/drivers/staging/rtl8723cs/include/Hal8814PhyReg.h
-new file mode 100644
-index 000000000000..21851a8988b7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8814PhyReg.h
-@@ -0,0 +1,863 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_HAL8814PHYREG_H__
-+#define __INC_HAL8814PHYREG_H__
-+/*--------------------------Define Parameters-------------------------------*/
-+/*
-+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
-+ * 3. RF register 0x00-2E
-+ * 4. Bit Mask for BB/RF register
-+ * 5. Other defintion for BB/RF R/W
-+ *   */
-+
-+
-+/* BB Register Definition */
-+
-+#define rCCAonSec_Jaguar		0x838
-+#define rPwed_TH_Jaguar			0x830
-+#define rL1_Weight_Jaguar		0x840
-+#define	r_L1_SBD_start_time		0x844
-+
-+/* BW and sideband setting */
-+#define rBWIndication_Jaguar		0x834
-+#define rL1PeakTH_Jaguar		0x848
-+#define rRFMOD_Jaguar			0x8ac	/* RF mode */
-+#define rADC_Buf_Clk_Jaguar		0x8c4
-+#define	rADC_Buf_40_Clk_Jaguar2		0x8c8
-+#define rRFECTRL_Jaguar			0x900
-+#define bRFMOD_Jaguar			0xc3
-+#define rCCK_System_Jaguar		0xa00   /* for cck sideband */
-+#define bCCK_System_Jaguar		0x10
-+
-+/* Block & Path enable */
-+#define rOFDMCCKEN_Jaguar 		0x808 /* OFDM/CCK block enable */
-+#define bOFDMEN_Jaguar			0x20000000
-+#define bCCKEN_Jaguar			0x10000000
-+#define rRxPath_Jaguar			0x808	/* Rx antenna */
-+#define bRxPath_Jaguar			0xff
-+#define rTxPath_Jaguar			0x80c	/* Tx antenna */
-+#define bTxPath_Jaguar			0x0fffffff
-+#define rCCK_RX_Jaguar			0xa04	/* for cck rx path selection */
-+#define bCCK_RX_Jaguar			0x0c000000
-+#define rVhtlen_Use_Lsig_Jaguar	0x8c3	/* Use LSIG for VHT length */
-+
-+#define	rRxPath_Jaguar2				0xa04	/* Rx antenna */
-+#define	rTxAnt_1Nsts_Jaguar2		0x93c	/* Tx antenna for 1Nsts */
-+#define	rTxAnt_23Nsts_Jaguar2		0x940	/* Tx antenna for 2Nsts and 3Nsts */
-+
-+
-+/* RF read/write-related */
-+#define rHSSIRead_Jaguar			0x8b0  /* RF read addr */
-+#define bHSSIRead_addr_Jaguar		0xff
-+#define bHSSIRead_trigger_Jaguar	0x100
-+#define rA_PIRead_Jaguar			0xd04 /* RF readback with PI */
-+#define rB_PIRead_Jaguar			0xd44 /* RF readback with PI */
-+#define rA_SIRead_Jaguar			0xd08 /* RF readback with SI */
-+#define rB_SIRead_Jaguar			0xd48 /* RF readback with SI */
-+#define rRead_data_Jaguar			0xfffff
-+#define rA_LSSIWrite_Jaguar			0xc90 /* RF write addr */
-+#define rB_LSSIWrite_Jaguar			0xe90 /* RF write addr */
-+#define bLSSIWrite_data_Jaguar		0x000fffff
-+#define bLSSIWrite_addr_Jaguar		0x0ff00000
-+
-+#define	rC_PIRead_Jaguar2			0xd84 /* RF readback with PI */
-+#define	rD_PIRead_Jaguar2			0xdC4 /* RF readback with PI */
-+#define	rC_SIRead_Jaguar2			0xd88 /* RF readback with SI */
-+#define	rD_SIRead_Jaguar2			0xdC8 /* RF readback with SI */
-+#define	rC_LSSIWrite_Jaguar2		0x1890 /* RF write addr */
-+#define	rD_LSSIWrite_Jaguar2		0x1A90 /* RF write addr */
-+
-+
-+/* YN: mask the following register definition temporarily */
-+#define rFPGA0_XA_RFInterfaceOE			0x860	/* RF Channel switch */
-+#define rFPGA0_XB_RFInterfaceOE			0x864
-+
-+#define rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
-+#define rFPGA0_XCD_RFInterfaceSW		0x874
-+
-+/* #define rFPGA0_XAB_RFParameter		0x878 */	/* RF Parameter
-+ * #define rFPGA0_XCD_RFParameter		0x87c */
-+
-+/* #define rFPGA0_AnalogParameter1		0x880 */	/* Crystal cap setting RF-R/W protection for parameter4??
-+ * #define rFPGA0_AnalogParameter2		0x884
-+ * #define rFPGA0_AnalogParameter3		0x888
-+ * #define rFPGA0_AdDaClockEn			0x888 */	/* enable ad/da clock1 for dual-phy
-+ * #define rFPGA0_AnalogParameter4		0x88c */
-+
-+
-+/* CCK TX scaling */
-+#define rCCK_TxFilter1_Jaguar		0xa20
-+#define bCCK_TxFilter1_C0_Jaguar	0x00ff0000
-+#define bCCK_TxFilter1_C1_Jaguar		0xff000000
-+#define rCCK_TxFilter2_Jaguar		0xa24
-+#define bCCK_TxFilter2_C2_Jaguar		0x000000ff
-+#define bCCK_TxFilter2_C3_Jaguar		0x0000ff00
-+#define bCCK_TxFilter2_C4_Jaguar		0x00ff0000
-+#define bCCK_TxFilter2_C5_Jaguar		0xff000000
-+#define rCCK_TxFilter3_Jaguar		0xa28
-+#define bCCK_TxFilter3_C6_Jaguar		0x000000ff
-+#define bCCK_TxFilter3_C7_Jaguar		0x0000ff00
-+/* NBI & CSI Mask setting */
-+#define	rCSI_Mask_Setting1_Jaguar	0x874
-+#define	rCSI_Fix_Mask0_Jaguar		0x880
-+#define	rCSI_Fix_Mask1_Jaguar		0x884
-+#define	rCSI_Fix_Mask2_Jaguar		0x888
-+#define	rCSI_Fix_Mask3_Jaguar		0x88c
-+#define	rCSI_Fix_Mask4_Jaguar		0x890
-+#define	rCSI_Fix_Mask5_Jaguar		0x894
-+#define	rCSI_Fix_Mask6_Jaguar		0x898
-+#define	rCSI_Fix_Mask7_Jaguar		0x89c
-+#define	rNBI_Setting_Jaguar			0x87c
-+
-+
-+/* YN: mask the following register definition temporarily
-+ * #define rPdp_AntA					0xb00
-+ * #define rPdp_AntA_4				0xb04
-+ * #define rConfig_Pmpd_AntA			0xb28
-+ * #define rConfig_AntA					0xb68
-+ * #define rConfig_AntB					0xb6c
-+ * #define rPdp_AntB					0xb70
-+ * #define rPdp_AntB_4					0xb74
-+ * #define rConfig_Pmpd_AntB			0xb98
-+ * #define rAPK							0xbd8 */
-+
-+/* RXIQC */
-+#define rA_RxIQC_AB_Jaguar    	0xc10  /* RxIQ imblance matrix coeff. A & B */
-+#define rA_RxIQC_CD_Jaguar    	0xc14  /* RxIQ imblance matrix coeff. C & D */
-+#define rA_TxScale_Jaguar 		0xc1c  /* Pah_A TX scaling factor */
-+#define rB_TxScale_Jaguar 		0xe1c  /* Path_B TX scaling factor */
-+#define rB_RxIQC_AB_Jaguar    	0xe10  /* RxIQ imblance matrix coeff. A & B */
-+#define rB_RxIQC_CD_Jaguar    	0xe14  /* RxIQ imblance matrix coeff. C & D */
-+#define b_RxIQC_AC_Jaguar		0x02ff  /* bit mask for IQC matrix element A & C */
-+#define b_RxIQC_BD_Jaguar		0x02ff0000 /* bit mask for IQC matrix element A & C */
-+
-+#define	rC_TxScale_Jaguar2 		0x181c  /* Pah_C TX scaling factor */
-+#define	rD_TxScale_Jaguar2 		0x1A1c  /* Path_D TX scaling factor */
-+#define	rRF_TxGainOffset		0x55
-+
-+/* DIG-related */
-+#define rA_IGI_Jaguar				0xc50	/* Initial Gain for path-A */
-+#define rB_IGI_Jaguar				0xe50	/* Initial Gain for path-B */
-+#define	rC_IGI_Jaguar2				0x1850	/* Initial Gain for path-C */
-+#define	rD_IGI_Jaguar2				0x1A50	/* Initial Gain for path-D */
-+
-+#define rOFDM_FalseAlarm1_Jaguar	0xf48  /* counter for break */
-+#define rOFDM_FalseAlarm2_Jaguar	0xf4c  /* counter for spoofing */
-+#define rCCK_FalseAlarm_Jaguar        	0xa5c /* counter for cck false alarm */
-+#define b_FalseAlarm_Jaguar			0xffff
-+#define rCCK_CCA_Jaguar				0xa08	/* cca threshold */
-+#define bCCK_CCA_Jaguar				0x00ff0000
-+
-+/* Tx Power Ttraining-related */
-+#define rA_TxPwrTraing_Jaguar		0xc54
-+#define rB_TxPwrTraing_Jaguar		0xe54
-+
-+/* Report-related */
-+#define rOFDM_ShortCFOAB_Jaguar	0xf60
-+#define rOFDM_LongCFOAB_Jaguar		0xf64
-+#define rOFDM_EndCFOAB_Jaguar		0xf70
-+#define rOFDM_AGCReport_Jaguar		0xf84
-+#define rOFDM_RxSNR_Jaguar			0xf88
-+#define rOFDM_RxEVMCSI_Jaguar		0xf8c
-+#define rOFDM_SIGReport_Jaguar		0xf90
-+
-+/* Misc functions */
-+#define rEDCCA_Jaguar				0x8a4 /* EDCCA */
-+#define bEDCCA_Jaguar				0xffff
-+#define rAGC_table_Jaguar			0x82c   /* AGC tabel select */
-+#define bAGC_table_Jaguar			0x3
-+#define b_sel5g_Jaguar    				0x1000 /* sel5g */
-+#define b_LNA_sw_Jaguar				0x8000 /* HW/WS control for LNA */
-+#define rFc_area_Jaguar				0x860   /* fc_area */
-+#define bFc_area_Jaguar				0x1ffe000
-+#define rSingleTone_ContTx_Jaguar	0x914
-+
-+#define	rAGC_table_Jaguar2			0x958	/* AGC tabel select */
-+#define	rDMA_trigger_Jaguar2		0x95C	/* ADC sample mode */
-+
-+
-+/* RFE */
-+#define rA_RFE_Pinmux_Jaguar	0xcb0  /* Path_A RFE cotrol pinmux */
-+#define rB_RFE_Pinmux_Jaguar	0xeb0 /* Path_B RFE control pinmux */
-+#define rA_RFE_Inv_Jaguar		0xcb4  /* Path_A RFE cotrol   */
-+#define rB_RFE_Inv_Jaguar		0xeb4 /* Path_B RFE control */
-+#define rA_RFE_Jaguar			0xcb8  /* Path_A RFE cotrol   */
-+#define rB_RFE_Jaguar			0xeb8 /* Path_B RFE control */
-+#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
-+#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
-+#define r_ANTSEL_SW_Jaguar		0x900 /* ANTSEL SW Control */
-+#define bMask_RFEInv_Jaguar		0x3ff00000
-+#define bMask_AntselPathFollow_Jaguar 0x00030000
-+
-+#define	rC_RFE_Pinmux_Jaguar	0x18B4	/* Path_C RFE cotrol pinmux */
-+#define	rD_RFE_Pinmux_Jaguar	0x1AB4	/* Path_D RFE cotrol pinmux */
-+#define	rA_RFE_Sel_Jaguar2		0x1990
-+
-+
-+
-+/* TX AGC */
-+#define rTxAGC_A_CCK11_CCK1_JAguar				0xc20
-+#define rTxAGC_A_Ofdm18_Ofdm6_JAguar				0xc24
-+#define rTxAGC_A_Ofdm54_Ofdm24_JAguar			0xc28
-+#define rTxAGC_A_MCS3_MCS0_JAguar					0xc2c
-+#define rTxAGC_A_MCS7_MCS4_JAguar					0xc30
-+#define rTxAGC_A_MCS11_MCS8_JAguar				0xc34
-+#define rTxAGC_A_MCS15_MCS12_JAguar				0xc38
-+#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar	0xc3c
-+#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar	0xc40
-+#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar	0xc44
-+#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar	0xc48
-+#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar	0xc4c
-+#define rTxAGC_B_CCK11_CCK1_JAguar				0xe20
-+#define rTxAGC_B_Ofdm18_Ofdm6_JAguar				0xe24
-+#define rTxAGC_B_Ofdm54_Ofdm24_JAguar			0xe28
-+#define rTxAGC_B_MCS3_MCS0_JAguar					0xe2c
-+#define rTxAGC_B_MCS7_MCS4_JAguar					0xe30
-+#define rTxAGC_B_MCS11_MCS8_JAguar				0xe34
-+#define rTxAGC_B_MCS15_MCS12_JAguar				0xe38
-+#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar		0xe3c
-+#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar		0xe40
-+#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar		0xe44
-+#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar		0xe48
-+#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar		0xe4c
-+#define bTxAGC_byte0_Jaguar							0xff
-+#define bTxAGC_byte1_Jaguar							0xff00
-+#define bTxAGC_byte2_Jaguar							0xff0000
-+#define bTxAGC_byte3_Jaguar							0xff000000
-+
-+
-+/* TX AGC */
-+#define		rTxAGC_A_CCK11_CCK1_Jaguar2	0xc20
-+#define		rTxAGC_A_Ofdm18_Ofdm6_Jaguar2	0xc24
-+#define		rTxAGC_A_Ofdm54_Ofdm24_Jaguar2	0xc28
-+#define		rTxAGC_A_MCS3_MCS0_Jaguar2	0xc2c
-+#define		rTxAGC_A_MCS7_MCS4_Jaguar2	0xc30
-+#define		rTxAGC_A_MCS11_MCS8_Jaguar2	0xc34
-+#define		rTxAGC_A_MCS15_MCS12_Jaguar2	0xc38
-+#define		rTxAGC_A_MCS19_MCS16_Jaguar2	0xcd8
-+#define		rTxAGC_A_MCS23_MCS20_Jaguar2	0xcdc
-+#define		rTxAGC_A_Nss1Index3_Nss1Index0_Jaguar2	0xc3c
-+#define		rTxAGC_A_Nss1Index7_Nss1Index4_Jaguar2	0xc40
-+#define		rTxAGC_A_Nss2Index1_Nss1Index8_Jaguar2	0xc44
-+#define		rTxAGC_A_Nss2Index5_Nss2Index2_Jaguar2	0xc48
-+#define		rTxAGC_A_Nss2Index9_Nss2Index6_Jaguar2	0xc4c
-+#define		rTxAGC_A_Nss3Index3_Nss3Index0_Jaguar2	0xce0
-+#define		rTxAGC_A_Nss3Index7_Nss3Index4_Jaguar2	0xce4
-+#define		rTxAGC_A_Nss3Index9_Nss3Index8_Jaguar2	0xce8
-+#define		rTxAGC_B_CCK11_CCK1_Jaguar2	0xe20
-+#define		rTxAGC_B_Ofdm18_Ofdm6_Jaguar2	0xe24
-+#define		rTxAGC_B_Ofdm54_Ofdm24_Jaguar2	0xe28
-+#define		rTxAGC_B_MCS3_MCS0_Jaguar2	0xe2c
-+#define		rTxAGC_B_MCS7_MCS4_Jaguar2	0xe30
-+#define		rTxAGC_B_MCS11_MCS8_Jaguar2	0xe34
-+#define		rTxAGC_B_MCS15_MCS12_Jaguar2	0xe38
-+#define		rTxAGC_B_MCS19_MCS16_Jaguar2	0xed8
-+#define		rTxAGC_B_MCS23_MCS20_Jaguar2	0xedc
-+#define		rTxAGC_B_Nss1Index3_Nss1Index0_Jaguar2	0xe3c
-+#define		rTxAGC_B_Nss1Index7_Nss1Index4_Jaguar2	0xe40
-+#define		rTxAGC_B_Nss2Index1_Nss1Index8_Jaguar2	0xe44
-+#define		rTxAGC_B_Nss2Index5_Nss2Index2_Jaguar2	0xe48
-+#define		rTxAGC_B_Nss2Index9_Nss2Index6_Jaguar2	0xe4c
-+#define		rTxAGC_B_Nss3Index3_Nss3Index0_Jaguar2	0xee0
-+#define		rTxAGC_B_Nss3Index7_Nss3Index4_Jaguar2	0xee4
-+#define		rTxAGC_B_Nss3Index9_Nss3Index8_Jaguar2	0xee8
-+#define		rTxAGC_C_CCK11_CCK1_Jaguar2	0x1820
-+#define		rTxAGC_C_Ofdm18_Ofdm6_Jaguar2	0x1824
-+#define		rTxAGC_C_Ofdm54_Ofdm24_Jaguar2	0x1828
-+#define		rTxAGC_C_MCS3_MCS0_Jaguar2	0x182c
-+#define		rTxAGC_C_MCS7_MCS4_Jaguar2	0x1830
-+#define		rTxAGC_C_MCS11_MCS8_Jaguar2	0x1834
-+#define		rTxAGC_C_MCS15_MCS12_Jaguar2	0x1838
-+#define		rTxAGC_C_MCS19_MCS16_Jaguar2	0x18d8
-+#define		rTxAGC_C_MCS23_MCS20_Jaguar2	0x18dc
-+#define		rTxAGC_C_Nss1Index3_Nss1Index0_Jaguar2	0x183c
-+#define		rTxAGC_C_Nss1Index7_Nss1Index4_Jaguar2	0x1840
-+#define		rTxAGC_C_Nss2Index1_Nss1Index8_Jaguar2	0x1844
-+#define		rTxAGC_C_Nss2Index5_Nss2Index2_Jaguar2	0x1848
-+#define		rTxAGC_C_Nss2Index9_Nss2Index6_Jaguar2	0x184c
-+#define		rTxAGC_C_Nss3Index3_Nss3Index0_Jaguar2	0x18e0
-+#define		rTxAGC_C_Nss3Index7_Nss3Index4_Jaguar2	0x18e4
-+#define		rTxAGC_C_Nss3Index9_Nss3Index8_Jaguar2	0x18e8
-+#define		rTxAGC_D_CCK11_CCK1_Jaguar2	0x1a20
-+#define		rTxAGC_D_Ofdm18_Ofdm6_Jaguar2	0x1a24
-+#define		rTxAGC_D_Ofdm54_Ofdm24_Jaguar2	0x1a28
-+#define		rTxAGC_D_MCS3_MCS0_Jaguar2	0x1a2c
-+#define		rTxAGC_D_MCS7_MCS4_Jaguar2	0x1a30
-+#define		rTxAGC_D_MCS11_MCS8_Jaguar2	0x1a34
-+#define		rTxAGC_D_MCS15_MCS12_Jaguar2	0x1a38
-+#define		rTxAGC_D_MCS19_MCS16_Jaguar2	0x1ad8
-+#define		rTxAGC_D_MCS23_MCS20_Jaguar2	0x1adc
-+#define		rTxAGC_D_Nss1Index3_Nss1Index0_Jaguar2	0x1a3c
-+#define		rTxAGC_D_Nss1Index7_Nss1Index4_Jaguar2	0x1a40
-+#define		rTxAGC_D_Nss2Index1_Nss1Index8_Jaguar2	0x1a44
-+#define		rTxAGC_D_Nss2Index5_Nss2Index2_Jaguar2	0x1a48
-+#define		rTxAGC_D_Nss2Index9_Nss2Index6_Jaguar2	0x1a4c
-+#define		rTxAGC_D_Nss3Index3_Nss3Index0_Jaguar2	0x1ae0
-+#define		rTxAGC_D_Nss3Index7_Nss3Index4_Jaguar2	0x1ae4
-+#define		rTxAGC_D_Nss3Index9_Nss3Index8_Jaguar2	0x1ae8
-+/* IQK YN: temporaily mask this part
-+ * #define rFPGA0_IQK					0xe28
-+ * #define rTx_IQK_Tone_A				0xe30
-+ * #define rRx_IQK_Tone_A				0xe34
-+ * #define rTx_IQK_PI_A					0xe38
-+ * #define rRx_IQK_PI_A					0xe3c */
-+
-+/* #define rTx_IQK						0xe40 */
-+/* #define rRx_IQK						0xe44 */
-+/* #define rIQK_AGC_Pts					0xe48 */
-+/* #define rIQK_AGC_Rsp					0xe4c */
-+/* #define rTx_IQK_Tone_B				0xe50 */
-+/* #define rRx_IQK_Tone_B				0xe54 */
-+/* #define rTx_IQK_PI_B					0xe58 */
-+/* #define rRx_IQK_PI_B					0xe5c */
-+/* #define rIQK_AGC_Cont				0xe60 */
-+
-+
-+/* AFE-related */
-+#define rA_AFEPwr1_Jaguar					0xc60 /* dynamic AFE power control */
-+#define rA_AFEPwr2_Jaguar					0xc64 /* dynamic AFE power control */
-+#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar	0xc68
-+#define rA_Tx_CCKBBON_OFDMRFON_Jaguar	0xc6c
-+#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar		0xc70
-+#define rA_Tx2Tx_RXCCK_Jaguar				0xc74
-+#define rA_Rx_OFDM_WaitRIFS_Jaguar			0xc78
-+#define rA_Rx2Rx_BT_Jaguar					0xc7c
-+#define rA_sleep_nav_Jaguar					0xc80
-+#define rA_pmpd_Jaguar						0xc84
-+#define rB_AFEPwr1_Jaguar					0xe60 /* dynamic AFE power control */
-+#define rB_AFEPwr2_Jaguar					0xe64 /* dynamic AFE power control */
-+#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar	0xe68
-+#define rB_Tx_CCKBBON_OFDMRFON_Jaguar	0xe6c
-+#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar		0xe70
-+#define rB_Tx2Tx_RXCCK_Jaguar				0xe74
-+#define rB_Rx_OFDM_WaitRIFS_Jaguar			0xe78
-+#define rB_Rx2Rx_BT_Jaguar					0xe7c
-+#define rB_sleep_nav_Jaguar					0xe80
-+#define rB_pmpd_Jaguar						0xe84
-+
-+
-+/* YN: mask these registers temporaily
-+ * #define rTx_Power_Before_IQK_A		0xe94
-+ * #define rTx_Power_After_IQK_A			0xe9c */
-+
-+/* #define rRx_Power_Before_IQK_A		0xea0 */
-+/* #define rRx_Power_Before_IQK_A_2		0xea4 */
-+/* #define rRx_Power_After_IQK_A			0xea8 */
-+/* #define rRx_Power_After_IQK_A_2		0xeac */
-+
-+/* #define rTx_Power_Before_IQK_B		0xeb4 */
-+/* #define rTx_Power_After_IQK_B			0xebc */
-+
-+/* #define rRx_Power_Before_IQK_B		0xec0 */
-+/* #define rRx_Power_Before_IQK_B_2		0xec4 */
-+/* #define rRx_Power_After_IQK_B			0xec8 */
-+/* #define rRx_Power_After_IQK_B_2		0xecc */
-+
-+
-+/* RSSI Dump */
-+#define rA_RSSIDump_Jaguar			0xBF0
-+#define rB_RSSIDump_Jaguar			0xBF1
-+#define rS1_RXevmDump_Jaguar		0xBF4
-+#define rS2_RXevmDump_Jaguar		0xBF5
-+#define rA_RXsnrDump_Jaguar		0xBF6
-+#define rB_RXsnrDump_Jaguar		0xBF7
-+#define rA_CfoShortDump_Jaguar		0xBF8
-+#define rB_CfoShortDump_Jaguar		0xBFA
-+#define rA_CfoLongDump_Jaguar		0xBEC
-+#define rB_CfoLongDump_Jaguar		0xBEE
-+
-+
-+/* RF Register
-+ *   */
-+#define RF_AC_Jaguar				0x00	/*  */
-+#define RF_RF_Top_Jaguar			0x07	/*  */
-+#define RF_TXLOK_Jaguar				0x08	/*  */
-+#define RF_TXAPK_Jaguar				0x0B
-+#define RF_CHNLBW_Jaguar 			0x18	/* RF channel and BW switch */
-+#define RF_RCK1_Jaguar				0x1c	/*  */
-+#define RF_RCK2_Jaguar				0x1d
-+#define RF_RCK3_Jaguar			0x1e
-+#define RF_ModeTableAddr			0x30
-+#define RF_ModeTableData0			0x31
-+#define RF_ModeTableData1			0x32
-+#define RF_TxLCTank_Jaguar	0x54
-+#define RF_APK_Jaguar				0x63
-+#define RF_LCK						0xB4
-+#define RF_WeLut_Jaguar				0xEF
-+
-+#define bRF_CHNLBW_MOD_AG_Jaguar	0x70300
-+#define bRF_CHNLBW_BW				0xc00
-+
-+
-+/*
-+ * RL6052 Register definition
-+ *   */
-+#define RF_AC						0x00	/*  */
-+#define RF_IPA_A					0x0C	/*  */
-+#define RF_TXBIAS_A					0x0D
-+#define RF_BS_PA_APSET_G9_G11		0x0E
-+#define RF_MODE1					0x10	/*  */
-+#define RF_MODE2					0x11	/*  */
-+#define RF_CHNLBW					0x18	/* RF channel and BW switch */
-+#define RF_RCK_OS					0x30	/* RF TX PA control */
-+#define RF_TXPA_G1					0x31	/* RF TX PA control */
-+#define RF_TXPA_G2					0x32	/* RF TX PA control */
-+#define RF_TXPA_G3					0x33	/* RF TX PA control */
-+#define RF_0x52						0x52
-+#define RF_WE_LUT					0xEF
-+
-+/*
-+ * Bit Mask
-+ *
-+ * 1. Page1(0x100) */
-+#define bBBResetB					0x100	/* Useless now? */
-+#define bGlobalResetB				0x200
-+#define bOFDMTxStart				0x4
-+#define bCCKTxStart					0x8
-+#define bCRC32Debug					0x100
-+#define bPMACLoopback				0x10
-+#define bTxLSIG						0xffffff
-+#define bOFDMTxRate					0xf
-+#define bOFDMTxReserved			0x10
-+#define bOFDMTxLength				0x1ffe0
-+#define bOFDMTxParity				0x20000
-+#define bTxHTSIG1					0xffffff
-+#define bTxHTMCSRate				0x7f
-+#define bTxHTBW						0x80
-+#define bTxHTLength					0xffff00
-+#define bTxHTSIG2					0xffffff
-+#define bTxHTSmoothing				0x1
-+#define bTxHTSounding				0x2
-+#define bTxHTReserved				0x4
-+#define bTxHTAggreation				0x8
-+#define bTxHTSTBC					0x30
-+#define bTxHTAdvanceCoding			0x40
-+#define bTxHTShortGI					0x80
-+#define bTxHTNumberHT_LTF			0x300
-+#define bTxHTCRC8					0x3fc00
-+#define bCounterReset				0x10000
-+#define bNumOfOFDMTx				0xffff
-+#define bNumOfCCKTx					0xffff0000
-+#define bTxIdleInterval				0xffff
-+#define bOFDMService				0xffff0000
-+#define bTxMACHeader				0xffffffff
-+#define bTxDataInit					0xff
-+#define bTxHTMode					0x100
-+#define bTxDataType					0x30000
-+#define bTxRandomSeed				0xffffffff
-+#define bCCKTxPreamble				0x1
-+#define bCCKTxSFD					0xffff0000
-+#define bCCKTxSIG					0xff
-+#define bCCKTxService				0xff00
-+#define bCCKLengthExt				0x8000
-+#define bCCKTxLength				0xffff0000
-+#define bCCKTxCRC16					0xffff
-+#define bCCKTxStatus					0x1
-+#define bOFDMTxStatus				0x2
-+
-+
-+/*
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 1. Page1(0x100)
-+ *   */
-+#define rPMAC_Reset					0x100
-+#define rPMAC_TxStart				0x104
-+#define rPMAC_TxLegacySIG			0x108
-+#define rPMAC_TxHTSIG1				0x10c
-+#define rPMAC_TxHTSIG2				0x110
-+#define rPMAC_PHYDebug				0x114
-+#define rPMAC_TxPacketNum			0x118
-+#define rPMAC_TxIdle					0x11c
-+#define rPMAC_TxMACHeader0			0x120
-+#define rPMAC_TxMACHeader1			0x124
-+#define rPMAC_TxMACHeader2			0x128
-+#define rPMAC_TxMACHeader3			0x12c
-+#define rPMAC_TxMACHeader4			0x130
-+#define rPMAC_TxMACHeader5			0x134
-+#define rPMAC_TxDataType			0x138
-+#define rPMAC_TxRandomSeed		0x13c
-+#define rPMAC_CCKPLCPPreamble		0x140
-+#define rPMAC_CCKPLCPHeader		0x144
-+#define rPMAC_CCKCRC16				0x148
-+#define rPMAC_OFDMRxCRC32OK		0x170
-+#define rPMAC_OFDMRxCRC32Er		0x174
-+#define rPMAC_OFDMRxParityEr		0x178
-+#define rPMAC_OFDMRxCRC8Er			0x17c
-+#define rPMAC_CCKCRxRC16Er			0x180
-+#define rPMAC_CCKCRxRC32Er			0x184
-+#define rPMAC_CCKCRxRC32OK			0x188
-+#define rPMAC_TxStatus				0x18c
-+
-+/*
-+ * 3. Page8(0x800)
-+ *   */
-+#define rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
-+
-+#define rFPGA0_TxInfo				0x804	/* Status report?? */
-+#define rFPGA0_PSDFunction			0x808
-+#define rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
-+
-+#define rFPGA0_XA_HSSIParameter1	0x820	/* RF 3 wire register */
-+#define rFPGA0_XA_HSSIParameter2	0x824
-+#define rFPGA0_XB_HSSIParameter1	0x828
-+#define rFPGA0_XB_HSSIParameter2	0x82c
-+
-+#define	rFPGA0_XA_LSSIParameter		0x840
-+#define	rFPGA0_XB_LSSIParameter		0x844
-+
-+#define rFPGA0_XAB_SwitchControl	0x858	/* RF Channel switch */
-+#define rFPGA0_XCD_SwitchControl	0x85c
-+
-+#define rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
-+#define rFPGA0_XCD_RFParameter		0x87c
-+
-+#define rFPGA0_AnalogParameter1	0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
-+#define rFPGA0_AnalogParameter2	0x884
-+#define rFPGA0_AnalogParameter3	0x888
-+#define rFPGA0_AdDaClockEn			0x888	/* enable ad/da clock1 for dual-phy */
-+#define rFPGA0_AnalogParameter4	0x88c
-+
-+#define	rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
-+#define	rFPGA0_XB_LSSIReadBack		0x8a4
-+#define	rFPGA0_XC_LSSIReadBack		0x8a8
-+#define	rFPGA0_XD_LSSIReadBack		0x8ac
-+
-+#define rFPGA0_XCD_RFPara	0x8b4
-+#define	rFPGA0_PSDReport				0x8b4	/* Useless now */
-+#define	TransceiverA_HSPI_Readback		0x8b8	/* Transceiver A HSPI Readback */
-+#define	TransceiverB_HSPI_Readback		0x8bc	/* Transceiver B HSPI Readback */
-+#define	rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
-+#define	rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
-+
-+/*
-+ * 4. Page9(0x900)
-+ *   */
-+#define rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
-+#define	REG_BB_TX_PATH_SEL_1_8814A		0x93c
-+#define	REG_BB_TX_PATH_SEL_2_8814A		0x940
-+#define rFPGA1_TxBlock				0x904	/* Useless now */
-+#define rFPGA1_DebugSelect			0x908	/* Useless now */
-+#define rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
-+/*Page 19 for TxBF*/
-+#define	REG_BB_TXBF_ANT_SET_BF1_8814A	0x19ac
-+#define	REG_BB_TXBF_ANT_SET_BF0_8814A	0x19b4
-+/*
-+ * PageA(0xA00)
-+ *   */
-+#define rCCK0_System				0xa00
-+#define rCCK0_AFESetting				0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
-+#define	rCCK0_DSPParameter2			0xa1c	/* SQ threshold */
-+#define rCCK0_TxFilter1				0xa20
-+#define rCCK0_TxFilter2				0xa24
-+#define rCCK0_DebugPort				0xa28	/* debug port and Tx filter3 */
-+#define	rCCK0_FalseAlarmReport			0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
-+
-+/*
-+ * PageB(0xB00)
-+ *   */
-+#define rPdp_AntA				0xb00
-+#define rPdp_AntA_4				0xb04
-+#define rConfig_Pmpd_AntA			0xb28
-+#define rConfig_AntA					0xb68
-+#define rConfig_AntB					0xb6c
-+#define rPdp_AntB					0xb70
-+#define rPdp_AntB_4					0xb74
-+#define rConfig_Pmpd_AntB			0xb98
-+#define rAPK							0xbd8
-+
-+/*
-+ * 6. PageC(0xC00)
-+ *   */
-+#define rOFDM0_LSTF					0xc00
-+
-+#define rOFDM0_TRxPathEnable		0xc04
-+#define rOFDM0_TRMuxPar			0xc08
-+#define rOFDM0_TRSWIsolation		0xc0c
-+
-+#define rOFDM0_XARxAFE				0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
-+#define rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
-+#define rOFDM0_XBRxAFE		0xc18
-+#define rOFDM0_XBRxIQImbalance	0xc1c
-+#define rOFDM0_XCRxAFE		0xc20
-+#define rOFDM0_XCRxIQImbalance	0xc24
-+#define rOFDM0_XDRxAFE		0xc28
-+#define rOFDM0_XDRxIQImbalance	0xc2c
-+
-+#define rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
-+#define rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
-+#define rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
-+#define rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
-+
-+#define rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
-+#define rOFDM0_CFOandDAGC			0xc44  /* CFO & DAGC */
-+#define rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
-+#define rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
-+
-+#define rOFDM0_XAAGCCore1			0xc50	/* DIG */
-+#define rOFDM0_XAAGCCore2			0xc54
-+#define rOFDM0_XBAGCCore1			0xc58
-+#define rOFDM0_XBAGCCore2			0xc5c
-+#define rOFDM0_XCAGCCore1			0xc60
-+#define rOFDM0_XCAGCCore2			0xc64
-+#define rOFDM0_XDAGCCore1			0xc68
-+#define rOFDM0_XDAGCCore2			0xc6c
-+
-+#define rOFDM0_AGCParameter1		0xc70
-+#define rOFDM0_AGCParameter2		0xc74
-+#define rOFDM0_AGCRSSITable		0xc78
-+#define rOFDM0_HTSTFAGC			0xc7c
-+
-+#define rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
-+#define rOFDM0_XATxAFE				0xc84
-+#define rOFDM0_XBTxIQImbalance		0xc88
-+#define rOFDM0_XBTxAFE				0xc8c
-+#define rOFDM0_XCTxIQImbalance		0xc90
-+#define rOFDM0_XCTxAFE		0xc94
-+#define rOFDM0_XDTxIQImbalance		0xc98
-+#define rOFDM0_XDTxAFE				0xc9c
-+
-+#define rOFDM0_RxIQExtAnta			0xca0
-+#define rOFDM0_TxCoeff1				0xca4
-+#define rOFDM0_TxCoeff2				0xca8
-+#define rOFDM0_TxCoeff3				0xcac
-+#define rOFDM0_TxCoeff4				0xcb0
-+#define rOFDM0_TxCoeff5				0xcb4
-+#define rOFDM0_TxCoeff6				0xcb8
-+#define rOFDM0_RxHPParameter		0xce0
-+#define rOFDM0_TxPseudoNoiseWgt	0xce4
-+#define rOFDM0_FrameSync			0xcf0
-+#define rOFDM0_DFSReport			0xcf4
-+
-+/*
-+ * 7. PageD(0xD00)
-+ *   */
-+#define rOFDM1_LSTF					0xd00
-+#define rOFDM1_TRxPathEnable		0xd04
-+
-+/*
-+ * 8. PageE(0xE00)
-+ *   */
-+#define rTxAGC_A_Rate18_06			0xe00
-+#define rTxAGC_A_Rate54_24			0xe04
-+#define rTxAGC_A_CCK1_Mcs32		0xe08
-+#define rTxAGC_A_Mcs03_Mcs00		0xe10
-+#define rTxAGC_A_Mcs07_Mcs04		0xe14
-+#define rTxAGC_A_Mcs11_Mcs08		0xe18
-+#define rTxAGC_A_Mcs15_Mcs12		0xe1c
-+
-+#define rTxAGC_B_Rate18_06			0x830
-+#define rTxAGC_B_Rate54_24			0x834
-+#define rTxAGC_B_CCK1_55_Mcs32	0x838
-+#define rTxAGC_B_Mcs03_Mcs00		0x83c
-+#define rTxAGC_B_Mcs07_Mcs04		0x848
-+#define rTxAGC_B_Mcs11_Mcs08		0x84c
-+#define rTxAGC_B_Mcs15_Mcs12		0x868
-+#define rTxAGC_B_CCK11_A_CCK2_11	0x86c
-+
-+#define rFPGA0_IQK					0xe28
-+#define rTx_IQK_Tone_A				0xe30
-+#define rRx_IQK_Tone_A				0xe34
-+#define rTx_IQK_PI_A				0xe38
-+#define rRx_IQK_PI_A				0xe3c
-+
-+#define rTx_IQK						0xe40
-+#define rRx_IQK						0xe44
-+#define rIQK_AGC_Pts					0xe48
-+#define rIQK_AGC_Rsp				0xe4c
-+#define rTx_IQK_Tone_B				0xe50
-+#define rRx_IQK_Tone_B				0xe54
-+#define rTx_IQK_PI_B					0xe58
-+#define rRx_IQK_PI_B					0xe5c
-+#define rIQK_AGC_Cont				0xe60
-+
-+#define rBlue_Tooth					0xe6c
-+#define rRx_Wait_CCA				0xe70
-+#define rTx_CCK_RFON				0xe74
-+#define rTx_CCK_BBON				0xe78
-+#define rTx_OFDM_RFON				0xe7c
-+#define rTx_OFDM_BBON				0xe80
-+#define rTx_To_Rx					0xe84
-+#define rTx_To_Tx					0xe88
-+#define rRx_CCK						0xe8c
-+
-+#define rTx_Power_Before_IQK_A		0xe94
-+#define rTx_Power_After_IQK_A		0xe9c
-+
-+#define rRx_Power_Before_IQK_A		0xea0
-+#define rRx_Power_Before_IQK_A_2	0xea4
-+#define rRx_Power_After_IQK_A		0xea8
-+#define rRx_Power_After_IQK_A_2		0xeac
-+
-+#define rTx_Power_Before_IQK_B		0xeb4
-+#define rTx_Power_After_IQK_B		0xebc
-+
-+#define rRx_Power_Before_IQK_B		0xec0
-+#define rRx_Power_Before_IQK_B_2	0xec4
-+#define rRx_Power_After_IQK_B		0xec8
-+#define rRx_Power_After_IQK_B_2		0xecc
-+
-+#define rRx_OFDM					0xed0
-+#define rRx_Wait_RIFS				0xed4
-+#define rRx_TO_Rx					0xed8
-+#define rStandby						0xedc
-+#define rSleep						0xee0
-+#define rPMPD_ANAEN				0xeec
-+
-+
-+/* 2. Page8(0x800) */
-+#define bRFMOD						0x1	/* Reg 0x800 rFPGA0_RFMOD */
-+#define bJapanMode					0x2
-+#define bCCKTxSC					0x30
-+#define bCCKEn						0x1000000
-+#define bOFDMEn						0x2000000
-+#define bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
-+#define bXCTxAGC			0xf000
-+#define bXDTxAGC			0xf0000
-+
-+/* 4. PageA(0xA00) */
-+#define bCCKBBMode                			0x3	/* Useless */
-+#define bCCKTxPowerSaving		0x80
-+#define bCCKRxPowerSaving		0x40
-+
-+#define bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
-+
-+#define bCCKScramble              		0x8	/* Useless */
-+#define bCCKAntDiversity			0x8000
-+#define bCCKCarrierRecovery		0x4000
-+#define bCCKTxRate			0x3000
-+#define bCCKDCCancel			0x0800
-+#define bCCKISICancel			0x0400
-+#define bCCKMatchFilter		0x0200
-+#define bCCKEqualizer			0x0100
-+#define bCCKPreambleDetect		0x800000
-+#define bCCKFastFalseCCA		0x400000
-+#define bCCKChEstStart		0x300000
-+#define bCCKCCACount		0x080000
-+#define bCCKcs_lim			0x070000
-+#define bCCKBistMode			0x80000000
-+#define bCCKCCAMask			0x40000000
-+#define bCCKTxDACPhase		0x4
-+#define bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
-+#define bCCKr_cp_mode0		0x0100
-+#define bCCKTxDCOffset		0xf0
-+#define bCCKRxDCOffset		0xf
-+#define bCCKCCAMode			0xc000
-+#define bCCKFalseCS_lim		0x3f00
-+#define bCCKCS_ratio			0xc00000
-+#define bCCKCorgBit_sel		0x300000
-+#define bCCKPD_lim			0x0f0000
-+#define bCCKNewCCA		0x80000000
-+#define bCCKRxHPofIG		0x8000
-+#define bCCKRxIG			0x7f00
-+#define bCCKLNAPolarity		0x800000
-+#define bCCKRx1stGain		0x7f0000
-+#define bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
-+#define bCCKRxAGCSatLevel		0x1f000000
-+#define bCCKRxAGCSatCount		0xe0
-+#define bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
-+#define bCCKFixedRxAGC		0x8000
-+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
-+#define bCCKAntennaPolarity		0x2000
-+#define bCCKTxFilterType		0x0c00
-+#define bCCKRxAGCReportType		0x0300
-+#define bCCKRxDAGCEn		0x80000000
-+#define bCCKRxDAGCPeriod		0x20000000
-+#define bCCKRxDAGCSatLevel		0x1f000000
-+#define bCCKTimingRecovery		0x800000
-+#define bCCKTxC0			0x3f0000
-+#define bCCKTxC1			0x3f000000
-+#define bCCKTxC2			0x3f
-+#define bCCKTxC3			0x3f00
-+#define bCCKTxC4			0x3f0000
-+#define bCCKTxC5			0x3f000000
-+#define bCCKTxC6			0x3f
-+#define bCCKTxC7			0x3f00
-+#define bCCKDebugPort		0xff0000
-+#define bCCKDACDebug		0x0f000000
-+#define bCCKFalseAlarmEnable		0x8000
-+#define bCCKFalseAlarmRead		0x4000
-+#define bCCKTRSSI			0x7f
-+#define bCCKRxAGCReport		0xfe
-+#define bCCKRxReport_AntSel		0x80000000
-+#define bCCKRxReport_MFOff		0x40000000
-+#define bCCKRxRxReport_SQLoss	0x20000000
-+#define bCCKRxReport_Pktloss		0x10000000
-+#define bCCKRxReport_Lockedbit	0x08000000
-+#define bCCKRxReport_RateError	0x04000000
-+#define bCCKRxReport_RxRate		0x03000000
-+#define bCCKRxFACounterLower	0xff
-+#define bCCKRxFACounterUpper	0xff000000
-+#define bCCKRxHPAGCStart		0xe000
-+#define bCCKRxHPAGCFinal		0x1c00
-+#define bCCKRxFalseAlarmEnable	0x8000
-+#define bCCKFACounterFreeze		0x4000
-+#define bCCKTxPathSel		0x10000000
-+#define bCCKDefaultRxPath		0xc000000
-+#define bCCKOptionRxPath		0x3000000
-+
-+#define		RF_T_METER_88E				0x42
-+
-+/* 6. PageE(0xE00) */
-+#define bSTBCEn                  			0x4	/* Useless */
-+#define bAntennaMapping		0x10
-+#define bNss				0x20
-+#define bCFOAntSumD		0x200
-+#define bPHYCounterReset		0x8000000
-+#define bCFOReportGet			0x4000000
-+#define bOFDMContinueTx		0x10000000
-+#define bOFDMSingleCarrier		0x20000000
-+#define bOFDMSingleTone		0x40000000
-+
-+
-+/*
-+ * Other Definition
-+ *   */
-+
-+#define bEnable                   0x1	/* Useless */
-+#define bDisable                  0x0
-+
-+/* byte endable for srwrite */
-+#define bByte0                    		0x1	/* Useless */
-+#define bByte1		0x2
-+#define bByte2		0x4
-+#define bByte3		0x8
-+#define bWord0		0x3
-+#define bWord1		0xc
-+#define bDWord		0xf
-+
-+/* for PutRegsetting & GetRegSetting BitMask */
-+#define bMaskByte0                		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
-+#define bMaskByte1		0xff00
-+#define bMaskByte2		0xff0000
-+#define bMaskByte3		0xff000000
-+#define bMaskHWord	0xffff0000
-+#define bMaskLWord		0x0000ffff
-+#define bMaskDWord	0xffffffff
-+#define bMaskH3Bytes				0xffffff00
-+#define bMask12Bits				0xfff
-+#define bMaskH4Bits				0xf0000000
-+#define bMaskOFDM_D			0xffc00000
-+#define bMaskCCK				0x3f3f3f3f
-+#define bMask7bits				0x7f
-+#define bMaskByte2HighNibble			0x00f00000
-+#define bMaskByte3LowNibble				0x0f000000
-+#define bMaskL3Bytes			0x00ffffff
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/Hal8814PwrSeq.h b/drivers/staging/rtl8723cs/include/Hal8814PwrSeq.h
-new file mode 100644
-index 000000000000..0138850c91e1
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8814PwrSeq.h
-@@ -0,0 +1,231 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+#ifndef __HAL8814PWRSEQ_H__
-+#define __HAL8814PWRSEQ_H__
-+
-+#include "HalPwrSeqCmd.h"
-+
-+/*
-+	Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
-+	There are 6 HW Power States:
-+	0: POFF--Power Off
-+	1: PDN--Power Down
-+	2: CARDEMU--Card Emulation
-+	3: ACT--Active Mode
-+	4: LPS--Low Power State
-+	5: SUS--Suspend
-+
-+	The transision from different states are defined below
-+	TRANS_CARDEMU_TO_ACT
-+	TRANS_ACT_TO_CARDEMU
-+	TRANS_CARDEMU_TO_SUS
-+	TRANS_SUS_TO_CARDEMU
-+	TRANS_CARDEMU_TO_PDN
-+	TRANS_ACT_TO_LPS
-+	TRANS_LPS_TO_ACT
-+
-+	TRANS_END
-+*/
-+#define	RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS	16
-+#define	RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS	20
-+#define	RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS	17
-+#define	RTL8814A_TRANS_SUS_TO_CARDEMU_STEPS	15
-+#define	RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS	17
-+#define	RTL8814A_TRANS_PDN_TO_CARDEMU_STEPS	16
-+#define	RTL8814A_TRANS_ACT_TO_LPS_STEPS	20
-+#define	RTL8814A_TRANS_LPS_TO_ACT_STEPS	15
-+#define	RTL8814A_TRANS_END_STEPS	1
-+
-+
-+#define RTL8814A_TRANS_CARDEMU_TO_ACT														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
-+	{0x002B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* ??0x28[24]=1, enable pll phase select*/ \
-+	{0x0015, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT3 | BIT2 | BIT1), (BIT3 | BIT2 | BIT1)},/* 0x14[11:9]=3'b111, OCP current threshold = 1.5A */ \
-+	{0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0E, 0x08},/* 0x2C[11:9]=3'b100, select lpf R3 */ \
-+	{0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x70, 0x50},/* 0x2C[14:12]=3'b101, select lpf Rs*/ \
-+	{0x007B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x78[30]=1'b1, SDM order select*/ \
-+	/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, */ /* disable HWPDN 0x04[15]=0*/ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/	\
-+	{0x00F0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* */	\
-+	{0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x30, 0x20},/* */	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/
-+
-+#define RTL8814A_TRANS_ACT_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4	turn off 3-wire */	\
-+	{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4	turn off 3-wire */	\
-+	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},  /* 0x2[0] = 0	 RESET BB, CLOSE RF */	\
-+	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/	\
-+	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
-+	{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},  /* 0x2[0] = 0	 RESET BB, CLOSE RF */	\
-+	{0x0002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/	\
-+	{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
-+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},  /*0x1F[7:0] = 0 turn off RF*/	\
-+	/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},*/  /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x28},   /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/	\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},   /*0x8[1] = 0 ANA clk = 500k */	\
-+	/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0},*/   /*  0x02[1:0] = 0	reset BB */	\
-+	{0x0066, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},   /*0x66[7]=0, disable ckreq for gpio7 output SUS */	\
-+	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},   /*0x41[4]=0, disable sic for gpio7 output SUS */	\
-+	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},   /*0x42[1]=0, disable ckout for gpio7 output SUS */	\
-+	{0x004e, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},   /*0x4E[5]=1, disable LED2 for gpio7 output SUS */	\
-+	{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},   /*0x41[0]=0, disable uart for gpio7 output SUS */	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
-+
-+#define RTL8814A_TRANS_CARDEMU_TO_SUS													\
-+	/* format */								\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0c},\
-+	{0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0E},\
-+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x07},/* gpio11 input mode, gpio10~8 output mode */	\
-+	{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */	\
-+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */	\
-+	{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */	\
-+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x14[13] = 1 turn on ZCD */	\
-+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x14[14] =1 trun on ZCD */	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */	\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */	\
-+	{0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */	\
-+	{0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend */
-+
-+#define RTL8814A_TRANS_SUS_TO_CARDEMU													\
-+	/* format */								\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0 enable WL suspend*/   \
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */	\
-+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x14[14] =0 trun off ZCD */	\
-+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x14[13] = 0 turn off ZCD */	\
-+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */	\
-+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
-+
-+#define RTL8814A_TRANS_CARDEMU_TO_CARDDIS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	/**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/	\
-+	/**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/	\
-+	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 3081*/	\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x01}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/	\
-+	{0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x30}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/	\
-+	/*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},*/   \
-+	/*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},*/   \
-+	/*{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},*/  /* gpio11 input mode, gpio10~8 output mode */	\
-+	{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */	\
-+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */	\
-+	{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */	\
-+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x15[6] =1 trun on ZCD output */	\
-+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x15[5] = 1 turn on ZCD */	\
-+	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*0x12[6] = 0 force PFM mode */	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */	\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */	\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
-+	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x01f[1]=0 , disable RFC_0  control  REG_RF_CTRL_8814A */	\
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x020[1]=0 , disable RFC_1  control  REG_RF_CTRL_8814A */	\
-+	{0x0021, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x021[1]=0 , disable RFC_2  control  REG_RF_CTRL_8814A */	\
-+	{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x076[1]=0 , disable RFC_3  control REG_OPT_CTRL_8814A +2 */	\
-+	{0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */	\
-+	{0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend*/
-+
-+#define RTL8814A_TRANS_CARDDIS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/                       \
-+	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*0x12[6] = 1 force PWM mode */	\
-+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x15[5] = 0 turn off ZCD */	\
-+	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x15[6] =0 trun off ZCD output */	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */	\
-+	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */	\
-+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /* gpio11 input mode, gpio10~8 input mode */ \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0, enable WL suspend*/	\
-+	/*{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x03[2] = 1, enable 3081*/	\
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/		\
-+	{0x0071, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*0x70[10] = 0, CPHY_MBIAS_EN disable*/
-+
-+
-+#define RTL8814A_TRANS_CARDEMU_TO_PDN												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
-+
-+#define RTL8814A_TRANS_PDN_TO_CARDEMU												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
-+
-+#define RTL8814A_TRANS_ACT_TO_LPS														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/		\
-+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4	turn off 3-wire */	\
-+	{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4	turn off 3-wire */	\
-+	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/	\
-+	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
-+	{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/	\
-+	{0x0002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},  /* Whole BB is reset*/			\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/			\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/		\
-+	{0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/
-+
-+
-+#define RTL8814A_TRANS_LPS_TO_ACT															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/	\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/	\
-+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/	\
-+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /* Delay*/	\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/	\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /* Polling 0x109[7]=0  TSF in 40M*/			\
-+	/*{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, */ /*.	??0x29[7:6] = 2b'00	 enable BB clock*/	\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/					\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/	\
-+	{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/	\
-+	{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x1002[1:0] = 2b'11	 enable BB macro*/	\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
-+
-+#define RTL8814A_TRANS_END																\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/		\
-+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
-+
-+
-+extern WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS + RTL8814A_TRANS_END_STEPS];
-+extern WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];
-+
-+#endif /* __HAL8814PWRSEQ_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/Hal8821APwrSeq.h b/drivers/staging/rtl8723cs/include/Hal8821APwrSeq.h
-new file mode 100644
-index 000000000000..568b8e5fc1e9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/Hal8821APwrSeq.h
-@@ -0,0 +1,200 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef REALTEK_POWER_SEQUENCE_8821
-+#define REALTEK_POWER_SEQUENCE_8821
-+
-+#include "HalPwrSeqCmd.h"
-+
-+/*
-+	Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
-+	There are 6 HW Power States:
-+	0: POFF--Power Off
-+	1: PDN--Power Down
-+	2: CARDEMU--Card Emulation
-+	3: ACT--Active Mode
-+	4: LPS--Low Power State
-+	5: SUS--Suspend
-+
-+	The transision from different states are defined below
-+	TRANS_CARDEMU_TO_ACT
-+	TRANS_ACT_TO_CARDEMU
-+	TRANS_CARDEMU_TO_SUS
-+	TRANS_SUS_TO_CARDEMU
-+	TRANS_CARDEMU_TO_PDN
-+	TRANS_ACT_TO_LPS
-+	TRANS_LPS_TO_ACT
-+
-+	TRANS_END
-+*/
-+#define	RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS	25
-+#define	RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS	15
-+#define	RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS	15
-+#define	RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS	15
-+#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS	15
-+#define	RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS	15
-+#define	RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS	15
-+#define	RTL8821A_TRANS_ACT_TO_LPS_STEPS	15
-+#define	RTL8821A_TRANS_LPS_TO_ACT_STEPS	15
-+#define	RTL8821A_TRANS_END_STEPS	1
-+
-+
-+#define RTL8821A_TRANS_CARDEMU_TO_ACT														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/   \
-+	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/	\
-+	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/   \
-+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/	\
-+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1    power ready*/	\
-+	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */	\
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/	\
-+	{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */\
-+	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5 | BIT4), (BIT5 | BIT4)},/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */\
-+	{0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/\
-+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
-+	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
-+	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
-+	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
-+	{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
-+	{0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A},/*0x7A = 0x3A start BT*/\
-+	{0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82 },/* 0x2C[23:12]=0x820 ; XTAL trim */ \
-+	{0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 },/* 0x10[6]=1 ; MP·s¼W¹ï©ó0x2Cªº±±¨îÅv¡A¶·§â0x10[6]³]¬°1¤~¯àÅýWLAN±±¨î */ \
-+
-+
-+#define RTL8821A_TRANS_ACT_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/	\
-+	{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
-+	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset  0x04[16]=1*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
-+	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/   \
-+	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/   \
-+
-+
-+#define RTL8821A_TRANS_CARDEMU_TO_SUS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8821A_TRANS_SUS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
-+
-+#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/	\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/	\
-+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/   \
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
-+
-+#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU													\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/	\
-+	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
-+	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/   \
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/   \
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
-+
-+
-+#define RTL8821A_TRANS_CARDEMU_TO_PDN												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/   \
-+	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/   \
-+	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
-+
-+#define RTL8821A_TRANS_PDN_TO_CARDEMU												\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
-+
-+#define RTL8821A_TRANS_ACT_TO_LPS														\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/	\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/	\
-+	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/	\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/	\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/	\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/	\
-+	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/	\
-+	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/	\
-+
-+
-+#define RTL8821A_TRANS_LPS_TO_ACT															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
-+	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
-+	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
-+	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*.	0x08[4] = 0		 switch TSF to 40M*/\
-+	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0  TSF in 40M*/\
-+	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*.	0x29[7:6] = 2b'00	 enable BB clock*/\
-+	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*.	0x101[1] = 1*/\
-+	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/\
-+	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*.	0x02[1:0] = 2b'11	 enable BB macro*/\
-+	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*.	0x522 = 0*/
-+
-+#define RTL8821A_TRANS_END															\
-+	/* format */																\
-+	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/								\
-+	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
-+
-+
-+	extern WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS + RTL8821A_TRANS_END_STEPS];
-+	extern WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/HalPwrSeqCmd.h b/drivers/staging/rtl8723cs/include/HalPwrSeqCmd.h
-new file mode 100644
-index 000000000000..f67ed22d1fc9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/HalPwrSeqCmd.h
-@@ -0,0 +1,130 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HALPWRSEQCMD_H__
-+#define __HALPWRSEQCMD_H__
-+
-+#include <drv_types.h>
-+
-+/*---------------------------------------------*/
-+/* 3 The value of cmd: 4 bits
-+ *---------------------------------------------*/
-+#define PWR_CMD_READ			0x00
-+/* offset: the read register offset
-+ * msk: the mask of the read value
-+ * value: N/A, left by 0
-+ * note: dirver shall implement this function by read & msk */
-+
-+#define PWR_CMD_WRITE			0x01
-+/* offset: the read register offset
-+ * msk: the mask of the write bits
-+ * value: write value
-+ * note: driver shall implement this cmd by read & msk after write */
-+
-+#define PWR_CMD_POLLING			0x02
-+/* offset: the read register offset
-+ * msk: the mask of the polled value
-+ * value: the value to be polled, masked by the msd field.
-+ * note: driver shall implement this cmd by
-+ * do {
-+ * if( (Read(offset) & msk) == (value & msk) )
-+ * break;
-+ * } while(not timeout); */
-+
-+#define PWR_CMD_DELAY			0x03
-+/* offset: the value to delay
-+ * msk: N/A
-+ * value: the unit of delay, 0: us, 1: ms */
-+
-+#define PWR_CMD_END				0x04
-+/* offset: N/A
-+ * msk: N/A
-+ * value: N/A */
-+
-+/*---------------------------------------------*/
-+/* 3 The value of base: 4 bits
-+ *---------------------------------------------
-+    * define the base address of each block */
-+#define PWR_BASEADDR_MAC		0x00
-+#define PWR_BASEADDR_USB		0x01
-+#define PWR_BASEADDR_PCIE		0x02
-+#define PWR_BASEADDR_SDIO		0x03
-+
-+/*---------------------------------------------*/
-+/* 3 The value of interface_msk: 4 bits
-+ *---------------------------------------------*/
-+#define	PWR_INTF_SDIO_MSK		BIT(0)
-+#define	PWR_INTF_USB_MSK		BIT(1)
-+#define	PWR_INTF_PCI_MSK		BIT(2)
-+#define	PWR_INTF_ALL_MSK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
-+
-+/*---------------------------------------------*/
-+/* 3 The value of fab_msk: 4 bits
-+ *---------------------------------------------*/
-+#define	PWR_FAB_TSMC_MSK		BIT(0)
-+#define	PWR_FAB_UMC_MSK			BIT(1)
-+#define	PWR_FAB_ALL_MSK			(BIT(0) | BIT(1) | BIT(2) | BIT(3))
-+
-+/*---------------------------------------------*/
-+/* 3 The value of cut_msk: 8 bits
-+ *---------------------------------------------*/
-+#define	PWR_CUT_TESTCHIP_MSK	BIT(0)
-+#define	PWR_CUT_A_MSK			BIT(1)
-+#define	PWR_CUT_B_MSK			BIT(2)
-+#define	PWR_CUT_C_MSK			BIT(3)
-+#define	PWR_CUT_D_MSK			BIT(4)
-+#define	PWR_CUT_E_MSK			BIT(5)
-+#define	PWR_CUT_F_MSK			BIT(6)
-+#define	PWR_CUT_G_MSK			BIT(7)
-+#define	PWR_CUT_ALL_MSK			0xFF
-+
-+
-+typedef enum _PWRSEQ_CMD_DELAY_UNIT_ {
-+	PWRSEQ_DELAY_US,
-+	PWRSEQ_DELAY_MS,
-+} PWRSEQ_DELAY_UNIT;
-+
-+typedef struct _WL_PWR_CFG_ {
-+	u16 offset;
-+	u8 cut_msk;
-+	u8 fab_msk:4;
-+	u8 interface_msk:4;
-+	u8 base:4;
-+	u8 cmd:4;
-+	u8 msk;
-+	u8 value;
-+} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
-+
-+
-+#define GET_PWR_CFG_OFFSET(__PWR_CMD)		((__PWR_CMD).offset)
-+#define GET_PWR_CFG_CUT_MASK(__PWR_CMD)		((__PWR_CMD).cut_msk)
-+#define GET_PWR_CFG_FAB_MASK(__PWR_CMD)		((__PWR_CMD).fab_msk)
-+#define GET_PWR_CFG_INTF_MASK(__PWR_CMD)	((__PWR_CMD).interface_msk)
-+#define GET_PWR_CFG_BASE(__PWR_CMD)			((__PWR_CMD).base)
-+#define GET_PWR_CFG_CMD(__PWR_CMD)			((__PWR_CMD).cmd)
-+#define GET_PWR_CFG_MASK(__PWR_CMD)			((__PWR_CMD).msk)
-+#define GET_PWR_CFG_VALUE(__PWR_CMD)		((__PWR_CMD).value)
-+
-+
-+/* ********************************************************************************
-+ *	Prototype of protected function.
-+ * ******************************************************************************** */
-+u8 HalPwrSeqCmdParsing(
-+	PADAPTER		padapter,
-+	u8				CutVersion,
-+	u8				FabVersion,
-+	u8				InterfaceType,
-+	WLAN_PWR_CFG	PwrCfgCmd[]);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/HalVerDef.h b/drivers/staging/rtl8723cs/include/HalVerDef.h
-new file mode 100644
-index 000000000000..d4e40670aba7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/HalVerDef.h
-@@ -0,0 +1,209 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_VERSION_DEF_H__
-+#define __HAL_VERSION_DEF_H__
-+
-+#define TRUE	_TRUE
-+#define FALSE	_FALSE
-+
-+/* HAL_IC_TYPE_E */
-+typedef enum tag_HAL_IC_Type_Definition {
-+	CHIP_8192S	=	0,
-+	CHIP_8188C	=	1,
-+	CHIP_8192C	=	2,
-+	CHIP_8192D	=	3,
-+	CHIP_8723A	=	4,
-+	CHIP_8188E	=	5,
-+	CHIP_8812	=	6,
-+	CHIP_8821	=	7,
-+	CHIP_8723B	=	8,
-+	CHIP_8192E	=	9,
-+	CHIP_8814A	=	10,
-+	CHIP_8703B	=	11,
-+	CHIP_8188F	=	12,
-+	CHIP_8822B	=	13,
-+	CHIP_8723D	=	14,
-+	CHIP_8821C	=	15,
-+	CHIP_8710B	=	16,
-+	CHIP_8192F	=	17,
-+	CHIP_8188GTV =	18,
-+	CHIP_8822C	=	19,
-+	CHIP_8814B	=	20,
-+	CHIP_8723F	=	21,
-+} HAL_IC_TYPE_E;
-+
-+/* HAL_CHIP_TYPE_E */
-+typedef enum tag_HAL_CHIP_Type_Definition {
-+	TEST_CHIP		=	0,
-+	NORMAL_CHIP	=	1,
-+	FPGA			=	2,
-+} HAL_CHIP_TYPE_E;
-+
-+/* HAL_CUT_VERSION_E */
-+typedef enum tag_HAL_Cut_Version_Definition {
-+	A_CUT_VERSION		=	0,
-+	B_CUT_VERSION		=	1,
-+	C_CUT_VERSION		=	2,
-+	D_CUT_VERSION		=	3,
-+	E_CUT_VERSION		=	4,
-+	F_CUT_VERSION		=	5,
-+	G_CUT_VERSION		=	6,
-+	H_CUT_VERSION		=	7,
-+	I_CUT_VERSION		=	8,
-+	J_CUT_VERSION		=	9,
-+	K_CUT_VERSION		=	10,
-+} HAL_CUT_VERSION_E;
-+
-+/* HAL_Manufacturer */
-+typedef enum tag_HAL_Manufacturer_Version_Definition {
-+	CHIP_VENDOR_TSMC	=	0,
-+	CHIP_VENDOR_UMC	=	1,
-+	CHIP_VENDOR_SMIC	=	2,
-+} HAL_VENDOR_E;
-+
-+typedef enum tag_HAL_RF_Type_Definition {
-+	RF_TYPE_1T1R	=	0,
-+	RF_TYPE_1T2R	=	1,
-+	RF_TYPE_2T2R	=	2,
-+	RF_TYPE_2T3R	=	3,
-+	RF_TYPE_2T4R	=	4,
-+	RF_TYPE_3T3R	=	5,
-+	RF_TYPE_3T4R	=	6,
-+	RF_TYPE_4T4R	=	7,
-+} HAL_RF_TYPE_E;
-+
-+typedef	struct tag_HAL_VERSION {
-+	HAL_IC_TYPE_E		ICType;
-+	HAL_CHIP_TYPE_E		ChipType;
-+	HAL_CUT_VERSION_E	CUTVersion;
-+	HAL_VENDOR_E		VendorType;
-+	HAL_RF_TYPE_E		RFType;
-+	u8					ROMVer;
-+} HAL_VERSION, *PHAL_VERSION;
-+
-+/* VERSION_8192C			VersionID;
-+ * HAL_VERSION			VersionID; */
-+
-+/* Get element */
-+#define GET_CVID_IC_TYPE(version)			((HAL_IC_TYPE_E)(((HAL_VERSION)version).ICType))
-+#define GET_CVID_CHIP_TYPE(version)			((HAL_CHIP_TYPE_E)(((HAL_VERSION)version).ChipType))
-+#define GET_CVID_RF_TYPE(version)			((HAL_RF_TYPE_E)(((HAL_VERSION)version).RFType))
-+#define GET_CVID_MANUFACTUER(version)		((HAL_VENDOR_E)(((HAL_VERSION)version).VendorType))
-+#define GET_CVID_CUT_VERSION(version)		((HAL_CUT_VERSION_E)(((HAL_VERSION)version).CUTVersion))
-+#define GET_CVID_ROM_VERSION(version)		((((HAL_VERSION)version).ROMVer) & ROM_VERSION_MASK)
-+
-+/* ----------------------------------------------------------------------------
-+ * Common Macro. --
-+ * ----------------------------------------------------------------------------
-+ * HAL_VERSION VersionID */
-+
-+/* HAL_IC_TYPE_E */
-+#if 0
-+	#define IS_81XXC(version)				(((GET_CVID_IC_TYPE(version) == CHIP_8192C) || (GET_CVID_IC_TYPE(version) == CHIP_8188C)) ? TRUE : FALSE)
-+	#define IS_8723_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8723A) ? TRUE : FALSE)
-+	#define IS_92D(version)					((GET_CVID_IC_TYPE(version) == CHIP_8192D) ? TRUE : FALSE)
-+#endif
-+
-+#define IS_8188E(version)					((GET_CVID_IC_TYPE(version) == CHIP_8188E) ? TRUE : FALSE)
-+#define IS_8188F(version)					((GET_CVID_IC_TYPE(version) == CHIP_8188F) ? TRUE : FALSE)
-+#define IS_8188GTV(version)					((GET_CVID_IC_TYPE(version) == CHIP_8188GTV) ? TRUE : FALSE)
-+#define IS_8192E(version)					((GET_CVID_IC_TYPE(version) == CHIP_8192E) ? TRUE : FALSE)
-+#define IS_8812_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8812) ? TRUE : FALSE)
-+#define IS_8821_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8821) ? TRUE : FALSE)
-+#define IS_8814A_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8814A) ? TRUE : FALSE)
-+#define IS_8723B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8723B) ? TRUE : FALSE)
-+#define IS_8703B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8703B) ? TRUE : FALSE)
-+#define IS_8822B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8822B) ? TRUE : FALSE)
-+#define IS_8821C_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8821C) ? TRUE : FALSE)
-+#define IS_8723D_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8723D) ? TRUE : FALSE)
-+#define IS_8710B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8710B) ? TRUE : FALSE)
-+#define IS_8822C_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8822C) ? TRUE : FALSE)
-+#define IS_8814B_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8814B) ? TRUE : FALSE)
-+#define IS_8723F_SERIES(version)			((GET_CVID_IC_TYPE(version) == CHIP_8723F) ? TRUE : FALSE)
-+
-+#define IS_8192F_SERIES(version)\
-+	((GET_CVID_IC_TYPE(version) == CHIP_8192F) ? TRUE : FALSE)
-+/* HAL_CHIP_TYPE_E */
-+#define IS_TEST_CHIP(version)			((GET_CVID_CHIP_TYPE(version) == TEST_CHIP) ? TRUE : FALSE)
-+#define IS_NORMAL_CHIP(version)			((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE)
-+
-+/* HAL_CUT_VERSION_E */
-+#define IS_A_CUT(version)				((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_B_CUT(version)				((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_C_CUT(version)				((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_D_CUT(version)				((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_E_CUT(version)				((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_F_CUT(version)				((GET_CVID_CUT_VERSION(version) == F_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_I_CUT(version)				((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_J_CUT(version)				((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? TRUE : FALSE)
-+#define IS_K_CUT(version)				((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? TRUE : FALSE)
-+
-+/* HAL_VENDOR_E */
-+#define IS_CHIP_VENDOR_TSMC(version)	((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC) ? TRUE : FALSE)
-+#define IS_CHIP_VENDOR_UMC(version)	((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC) ? TRUE : FALSE)
-+#define IS_CHIP_VENDOR_SMIC(version)	((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_SMIC) ? TRUE : FALSE)
-+
-+/* HAL_RF_TYPE_E */
-+#define IS_1T1R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R) ? TRUE : FALSE)
-+#define IS_1T2R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? TRUE : FALSE)
-+#define IS_2T2R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? TRUE : FALSE)
-+#define IS_2T3R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_2T3R) ? TRUE : FALSE)
-+#define IS_2T4R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_2T4R) ? TRUE : FALSE)
-+#define IS_3T3R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_3T3R) ? TRUE : FALSE)
-+#define IS_3T4R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_3T4R) ? TRUE : FALSE)
-+#define IS_4T4R(version)					((GET_CVID_RF_TYPE(version) == RF_TYPE_4T4R) ? TRUE : FALSE)
-+
-+
-+
-+/* ----------------------------------------------------------------------------
-+ * Chip version Macro. --
-+ * ---------------------------------------------------------------------------- */
-+#if 0
-+	#define IS_81XXC_TEST_CHIP(version)		((IS_81XXC(version) && (!IS_NORMAL_CHIP(version))) ? TRUE : FALSE)
-+
-+	#define IS_92C_SERIAL(version)					((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
-+	#define IS_81xxC_VENDOR_UMC_A_CUT(version)	(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
-+	#define IS_81xxC_VENDOR_UMC_B_CUT(version)	(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
-+	#define IS_81xxC_VENDOR_UMC_C_CUT(version)	(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
-+
-+	#define IS_NORMAL_CHIP92D(version)		((IS_92D(version)) ? ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE) : FALSE)
-+
-+	#define IS_92D_SINGLEPHY(version)		((IS_92D(version)) ? (IS_2T2R(version) ? TRUE : FALSE) : FALSE)
-+	#define IS_92D_C_CUT(version)			((IS_92D(version)) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE)
-+	#define IS_92D_D_CUT(version)			((IS_92D(version)) ? (IS_D_CUT(version) ? TRUE : FALSE) : FALSE)
-+	#define IS_92D_E_CUT(version)			((IS_92D(version)) ? (IS_E_CUT(version) ? TRUE : FALSE) : FALSE)
-+
-+	#define IS_8723A_A_CUT(version)				((IS_8723_SERIES(version)) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE)
-+	#define IS_8723A_B_CUT(version)				((IS_8723_SERIES(version)) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE)
-+#endif
-+#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)		((IS_8188E(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE)
-+#define IS_VENDOR_8812A_TEST_CHIP(_Adapter)		((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
-+#define IS_VENDOR_8812A_MP_CHIP(_Adapter)		((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
-+#define IS_VENDOR_8812A_C_CUT(_Adapter)			((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE)
-+
-+#define IS_VENDOR_8821A_TEST_CHIP(_Adapter)	((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
-+#define IS_VENDOR_8821A_MP_CHIP(_Adapter)		((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
-+
-+#define IS_VENDOR_8192E_B_CUT(_Adapter)		((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == B_CUT_VERSION) ? TRUE : FALSE)
-+
-+#define IS_VENDOR_8723B_TEST_CHIP(_Adapter)	((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
-+#define IS_VENDOR_8723B_MP_CHIP(_Adapter)		((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
-+
-+#define IS_VENDOR_8703B_TEST_CHIP(_Adapter)	((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
-+#define IS_VENDOR_8703B_MP_CHIP(_Adapter)		((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
-+#define IS_VENDOR_8814A_TEST_CHIP(_Adapter)	((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
-+#define IS_VENDOR_8814A_MP_CHIP(_Adapter)		((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/autoconf.h b/drivers/staging/rtl8723cs/include/autoconf.h
-new file mode 100644
-index 000000000000..35dfd7b24e3c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/autoconf.h
-@@ -0,0 +1,290 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*
-+ * Public General Config
-+ */
-+#define AUTOCONF_INCLUDED
-+
-+#define RTL871X_MODULE_NAME "8723CS"
-+#define DRV_NAME "rtl8723cs"
-+
-+#ifndef CONFIG_RTL8703B
-+#define CONFIG_RTL8703B
-+#endif
-+#define CONFIG_SDIO_HCI
-+
-+#define PLATFORM_LINUX
-+
-+
-+/*
-+ * Wi-Fi Functions Config
-+ */
-+#define CONFIG_80211N_HT
-+#define CONFIG_RECV_REORDERING_CTRL
-+
-+/* #define CONFIG_IOCTL_CFG80211 */		/* Set from Makefile */
-+#ifdef CONFIG_IOCTL_CFG80211
-+	/*
-+	 * Indecate new sta asoc through cfg80211_new_sta
-+	 * If kernel version >= 3.2 or
-+	 * version < 3.2 but already apply cfg80211 patch,
-+	 * RTW_USE_CFG80211_STA_EVENT must be defiend!
-+	 */
-+	/* #define RTW_USE_CFG80211_STA_EVENT */ /* Indecate new sta asoc through cfg80211_new_sta */
-+	#ifndef CONFIG_PLATFORM_INTEL_BYT
-+	#define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
-+	#endif /* !CONFIG_PLATFORM_INTEL_BYT */
-+	/* #define CONFIG_DEBUG_CFG80211 */
-+	#define CONFIG_SET_SCAN_DENY_TIMER
-+#endif
-+
-+#ifdef CONFIG_AP_MODE
-+	#define CONFIG_NATIVEAP_MLME
-+	#ifndef CONFIG_NATIVEAP_MLME
-+		#define CONFIG_HOSTAPD_MLME
-+	#endif
-+	/* #define CONFIG_FIND_BEST_CHANNEL */
-+#endif
-+
-+#ifdef CONFIG_P2P
-+	/* Added by Albert 20110812
-+	The CONFIG_WFD is for supporting the Wi-Fi display */
-+	#define CONFIG_WFD
-+
-+	#define CONFIG_P2P_REMOVE_GROUP_INFO
-+
-+	/* #define CONFIG_DBG_P2P */
-+	#define CONFIG_P2P_PS
-+	#define CONFIG_P2P_OP_CHK_SOCIAL_CH
-+	#define CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT  /* replace CONFIG_P2P_CHK_INVITE_CH_LIST flag */
-+	/*#define CONFIG_P2P_INVITE_IOT*/
-+#endif
-+
-+/* Added by Kurt 20110511 */
-+#ifdef CONFIG_TDLS
-+	#define CONFIG_TDLS_DRIVER_SETUP
-+	/* #ifndef CONFIG_WFD
-+		#define CONFIG_WFD
-+	#endif */
-+	/* #define CONFIG_TDLS_AUTOSETUP */
-+	#define CONFIG_TDLS_AUTOCHECKALIVE
-+	/* #define CONFIG_TDLS_CH_SW */	/* Enable this flag only when we confirm that TDLS CH SW is supported in FW */
-+#endif
-+
-+/* #define CONFIG_CONCURRENT_MODE */	/* Set from Makefile */
-+#ifdef CONFIG_CONCURRENT_MODE
-+	#define CONFIG_RUNTIME_PORT_SWITCH
-+	/* #define DBG_RUNTIME_PORT_SWITCH */
-+
-+
-+	#ifndef CONFIG_RUNTIME_PORT_SWITCH
-+		#define CONFIG_TSF_RESET_OFFLOAD			/* For 2 PORT TSF SYNC. */
-+	#endif
-+	/* #define DBG_RUNTIME_PORT_SWITCH */
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+/*
-+ * Hareware/Firmware Related Config
-+ */
-+/* #define CONFIG_BT_COEXIST */	/* Set from Makefile */
-+/* #define CONFIG_ANTENNA_DIVERSITY */
-+/* #define SUPPORT_HW_RFOFF_DETECTED */
-+
-+/*#define CONFIG_RTW_LED*/
-+#ifdef CONFIG_RTW_LED
-+	/*#define CONFIG_RTW_SW_LED*/
-+#endif /* CONFIG_RTW_LED */
-+
-+#define CONFIG_XMIT_ACK
-+#ifdef CONFIG_XMIT_ACK
-+	#define CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-+#endif
-+
-+#define CONFIG_RF_POWER_TRIM
-+
-+#define DISABLE_BB_RF	0
-+
-+#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable, */
-+
-+
-+/*
-+ * Interface Related Config
-+ */
-+#define CONFIG_TX_AGGREGATION
-+#define CONFIG_SDIO_RX_COPY
-+#define CONFIG_XMIT_THREAD_MODE
-+/* #define CONFIG_SDIO_TX_ENABLE_AVAL_INT */
-+#define CONFIG_RECV_THREAD_MODE
-+
-+/*
-+ * Others
-+ */
-+/* #define CONFIG_MAC_LOOPBACK_DRIVER */
-+
-+#define CONFIG_SKB_COPY	/* for amsdu */
-+
-+#define CONFIG_NEW_SIGNAL_STAT_PROCESS
-+
-+#define CONFIG_EMBEDDED_FWIMG
-+
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+	#define	LOAD_FW_HEADER_FROM_DRIVER
-+#endif
-+/* #define CONFIG_FILE_FWIMG */
-+
-+#define CONFIG_LONG_DELAY_ISSUE
-+/* #define CONFIG_PATCH_JOIN_WRONG_CHANNEL */
-+
-+
-+/*
-+ * Auto Config Section
-+ */
-+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
-+#undef CONFIG_IOCTL_CFG80211
-+#undef CONFIG_AP_MODE
-+#undef CONFIG_NATIVEAP_MLME
-+#undef CONFIG_POWER_SAVING
-+#undef CONFIG_BT_COEXIST
-+#undef CONFIG_ANTENNA_DIVERSITY
-+#undef SUPPORT_HW_RFOFF_DETECTED
-+#endif
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	#define MP_DRIVER	1
-+	#define CONFIG_MP_IWPRIV_SUPPORT
-+	/* disable unnecessary functions for MP */
-+	/* #undef CONFIG_POWER_SAVING
-+	#undef CONFIG_BT_COEXIST
-+	#undef CONFIG_ANTENNA_DIVERSITY
-+	#undef SUPPORT_HW_RFOFF_DETECTED */
-+#else /* !CONFIG_MP_INCLUDED */
-+	#define MP_DRIVER	0
-+	#undef CONFIG_MP_IWPRIV_SUPPORT
-+#endif /* !CONFIG_MP_INCLUDED */
-+
-+#ifdef CONFIG_POWER_SAVING
-+	#define CONFIG_IPS
-+	#define CONFIG_LPS
-+
-+	#if defined(CONFIG_LPS) && (defined(CONFIG_GSPI_HCI) || defined(CONFIG_SDIO_HCI))
-+	#define CONFIG_LPS_LCLK
-+	#endif
-+
-+	#ifdef CONFIG_LPS
-+		#define CONFIG_CHECK_LEAVE_LPS
-+		#ifndef CONFIG_PLATFORM_INTEL_BYT
-+		#define CONFIG_LPS_SLOW_TRANSITION
-+		#endif /* !CONFIG_PLATFORM_INTEL_BYT */
-+	#endif
-+
-+	#ifdef CONFIG_LPS_LCLK
-+	#define CONFIG_DETECT_CPWM_BY_POLLING
-+	#define CONFIG_LPS_RPWM_TIMER
-+	#if defined(CONFIG_LPS_RPWM_TIMER) || defined(CONFIG_DETECT_CPWM_BY_POLLING)
-+	#define LPS_RPWM_WAIT_MS 300
-+	#endif
-+	#define CONFIG_LPS_LCLK_WD_TIMER /* Watch Dog timer in LPS LCLK */
-+	#endif
-+
-+	#ifdef CONFIG_IPS
-+	#define CONFIG_IPS_CHECK_IN_WD /* Do IPS Check in WatchDog. */
-+	/* #define CONFIG_SWLPS_IN_IPS */ /* Do SW LPS flow when entering and leaving IPS */
-+	/* #define CONFIG_FWLPS_IN_IPS */ /* issue H2C command to let FW do LPS when entering IPS */
-+	#endif
-+#endif /* CONFIG_POWER_SAVING */
-+
-+#ifdef CONFIG_BT_COEXIST
-+	/* for ODM and outsrc BT-Coex */
-+	#ifndef CONFIG_LPS
-+		#define CONFIG_LPS	/* download reserved page to FW */
-+	#endif
-+#endif /* !CONFIG_BT_COEXIST */
-+
-+#ifdef CONFIG_WOWLAN
-+	/* #define CONFIG_GTK_OL */
-+	/* #define CONFIG_ARP_KEEP_ALIVE */
-+#endif /* CONFIG_WOWLAN */
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+	#ifndef WAKEUP_GPIO_IDX
-+		#define WAKEUP_GPIO_IDX	8	/* WIFI Chip Side */
-+	#endif /* !WAKEUP_GPIO_IDX */
-+#endif /* CONFIG_GPIO_WAKEUP */
-+
-+
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+#define CONFIG_HW_ANTENNA_DIVERSITY
-+#endif
-+
-+#ifdef CONFIG_RTW_NAPI
-+/*#define CONFIG_RTW_NAPI_DYNAMIC*/
-+#define CONFIG_RTW_NAPI_V2
-+#endif
-+
-+/*
-+ * Platform dependent
-+ */
-+#ifdef CONFIG_PLATFORM_SPRD
-+
-+#undef CONFIG_SDIO_RX_COPY
-+
-+#ifdef ANDROID_2X
-+
-+#define CONFIG_SDIO_RX_COPY
-+
-+#else /*  !ANDROID_2X */
-+	#undef CONFIG_WOWLAN
-+	#undef CONFIG_WOWLAN_8723
-+	/* #define CONFIG_SDIO_RX_COPY */
-+	/* #define CONFIG_LINKED_LCOK */
-+	#define CONFIG_AUTH_DIRECT_WITHOUT_BCN
-+	/* #define CONFIG_DISCONNECT_H2CWAY */
-+	/* #define CONFIG_DONT_CARE_TP */
-+	#define CONFIG_LOW_PWR_LPS
-+	/* #define CONFIG_CMCC_TEST */
-+
-+	/* 1) LPS unit is only 102 ms, it's not
-+	a good idear to retry it use timer,
-+	2) we must wait ACK, or lots of IO
-+	is not allowed under 32k, because
-+	this will cause hw hang */
-+	#undef CONFIG_LPS_RPWM_TIMER
-+	#define CONFIG_WAIT_PS_ACK
-+	#define CONFIG_SOFTAP_11N
-+	#define CONFIG_CHECK_BT_HANG
-+
-+	/* #define CONFIG_8703BS_TEST */
-+#endif /* !ANDROID_2X */
-+
-+#endif /* CONFIG_PLATFORM_SPRD */
-+
-+
-+/*
-+ * Debug Related Config
-+ */
-+#ifdef CONFIG_RTW_DEBUG
-+#define DBG	1	/* for ODM & BTCOEX debug */
-+#else /* !CONFIG_RTW_DEBUG */
-+#define DBG	0	/* for ODM & BTCOEX debug */
-+#endif /* !CONFIG_RTW_DEBUG */
-+
-+#define DBG_CONFIG_ERROR_DETECT
-+/* #define DBG_XMIT_BUF */
-+/* #define DBG_XMIT_BUF_EXT */
-+#define DBG_CHECK_FW_PS_STATE
-+#define DBG_CHECK_FW_PS_STATE_H2C
-+/* #define CONFIG_FW_C2H_DEBUG */
-+#define	DBG_RX_DFRAME_RAW_DATA
-diff --git a/drivers/staging/rtl8723cs/include/basic_types.h b/drivers/staging/rtl8723cs/include/basic_types.h
-new file mode 100644
-index 000000000000..45e513156e2f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/basic_types.h
-@@ -0,0 +1,357 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __BASIC_TYPES_H__
-+#define __BASIC_TYPES_H__
-+
-+
-+#define SUCCESS	0
-+#define FAIL	(-1)
-+
-+#ifndef TRUE
-+	#define _TRUE	1
-+#else
-+	#define _TRUE	TRUE
-+#endif
-+
-+#ifndef FALSE
-+	#define _FALSE	0
-+#else
-+	#define _FALSE	FALSE
-+#endif
-+
-+#ifdef PLATFORM_WINDOWS
-+
-+	typedef signed char s8;
-+	typedef unsigned char u8;
-+
-+	typedef signed short s16;
-+	typedef unsigned short u16;
-+
-+	typedef signed long s32;
-+	typedef unsigned long u32;
-+
-+	typedef unsigned int	uint;
-+	typedef	signed int		sint;
-+
-+
-+	typedef signed long long s64;
-+	typedef unsigned long long u64;
-+
-+	#ifdef NDIS50_MINIPORT
-+
-+		#define NDIS_MAJOR_VERSION       5
-+		#define NDIS_MINOR_VERSION       0
-+
-+	#endif
-+
-+	#ifdef NDIS51_MINIPORT
-+
-+		#define NDIS_MAJOR_VERSION       5
-+		#define NDIS_MINOR_VERSION       1
-+
-+	#endif
-+
-+	typedef NDIS_PROC proc_t;
-+
-+	typedef LONG atomic_t;
-+
-+#endif
-+
-+
-+#ifdef PLATFORM_LINUX
-+	#include <linux/version.h>
-+	#include <linux/types.h>
-+	#include <linux/module.h>
-+	#include <linux/kernel.h>
-+	#include <linux/init.h>
-+	#include <linux/utsname.h>
-+
-+	typedef	signed int sint;
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))
-+typedef _Bool bool;
-+
-+enum {
-+	false	= 0,
-+	true	= 1
-+};
-+#endif
-+
-+	typedef void (*proc_t)(void *);
-+
-+	typedef	__kernel_size_t	SIZE_T;
-+	typedef	__kernel_ssize_t	SSIZE_T;
-+	#define FIELD_OFFSET(s, field)	((SSIZE_T)&((s *)(0))->field)
-+
-+#define NDIS_OID uint
-+#endif /*PLATFORM_LINUX*/
-+
-+
-+#ifdef PLATFORM_FREEBSD
-+
-+	typedef signed char s8;
-+	typedef unsigned char u8;
-+
-+	typedef signed short s16;
-+	typedef unsigned short u16;
-+
-+	typedef signed int s32;
-+	typedef unsigned int u32;
-+
-+	typedef unsigned int	uint;
-+	typedef	signed int		sint;
-+	typedef long atomic_t;
-+
-+	typedef signed long long s64;
-+	typedef unsigned long long u64;
-+
-+	typedef u32 dma_addr_t;
-+
-+	typedef void (*proc_t)(void *);
-+
-+	typedef unsigned int __kernel_size_t;
-+	typedef int __kernel_ssize_t;
-+
-+	typedef	__kernel_size_t	SIZE_T;
-+	typedef	__kernel_ssize_t	SSIZE_T;
-+	#define FIELD_OFFSET(s, field)	((SSIZE_T)&((s *)(0))->field)
-+
-+#endif
-+
-+#define MEM_ALIGNMENT_OFFSET	(sizeof (SIZE_T))
-+#define MEM_ALIGNMENT_PADDING	(sizeof(SIZE_T) - 1)
-+
-+#define SIZE_PTR SIZE_T
-+#define SSIZE_PTR SSIZE_T
-+
-+/*
-+* Continuous bits starting from least significant bit
-+* Example:
-+* BIT_LEN_MASK_32(0) => 0x00000000
-+* BIT_LEN_MASK_32(1) => 0x00000001
-+* BIT_LEN_MASK_32(2) => 0x00000003
-+* BIT_LEN_MASK_32(32) => 0xFFFFFFFF
-+*/
-+#define BIT_LEN_MASK_32(__BitLen) ((u32)(0xFFFFFFFF >> (32 - (__BitLen))))
-+#define BIT_LEN_MASK_16(__BitLen) ((u16)(0xFFFF >> (16 - (__BitLen))))
-+#define BIT_LEN_MASK_8(__BitLen) ((u8)(0xFF >> (8 - (__BitLen))))
-+
-+/*
-+* Continuous bits starting from least significant bit
-+* Example:
-+* BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
-+* BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
-+*/
-+#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ((u32)(BIT_LEN_MASK_32(__BitLen) << (__BitOffset)))
-+#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ((u16)(BIT_LEN_MASK_16(__BitLen) << (__BitOffset)))
-+#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ((u8)(BIT_LEN_MASK_8(__BitLen) << (__BitOffset)))
-+
-+/*
-+* Convert LE data to host byte order
-+*/
-+#define EF1Byte (u8)
-+#define EF2Byte le16_to_cpu
-+#define EF4Byte le32_to_cpu
-+
-+/*
-+* Read LE data from memory to host byte order
-+*/
-+#define ReadLE4Byte(_ptr)	le32_to_cpu(*((u32 *)(_ptr)))
-+#define ReadLE2Byte(_ptr)	le16_to_cpu(*((u16 *)(_ptr)))
-+#define ReadLE1Byte(_ptr)	(*((u8 *)(_ptr)))
-+
-+/*
-+* Read BE data from memory to host byte order
-+*/
-+#define ReadBEE4Byte(_ptr)	be32_to_cpu(*((u32 *)(_ptr)))
-+#define ReadBE2Byte(_ptr)	be16_to_cpu(*((u16 *)(_ptr)))
-+#define ReadBE1Byte(_ptr)	(*((u8 *)(_ptr)))
-+
-+/*
-+* Write host byte order data to memory in LE order
-+*/
-+#define WriteLE4Byte(_ptr, _val)	((*((u32 *)(_ptr))) = cpu_to_le32(_val))
-+#define WriteLE2Byte(_ptr, _val)	((*((u16 *)(_ptr))) = cpu_to_le16(_val))
-+#define WriteLE1Byte(_ptr, _val)	((*((u8 *)(_ptr))) = ((u8)(_val)))
-+
-+/*
-+* Write host byte order data to memory in BE order
-+*/
-+#define WriteBE4Byte(_ptr, _val)	((*((u32 *)(_ptr))) = cpu_to_be32(_val))
-+#define WriteBE2Byte(_ptr, _val)	((*((u16 *)(_ptr))) = cpu_to_be16(_val))
-+#define WriteBE1Byte(_ptr, _val)	((*((u8 *)(_ptr))) = ((u8)(_val)))
-+
-+/*
-+* Return 4-byte value in host byte ordering from 4-byte pointer in litten-endian system.
-+*/
-+#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) (le32_to_cpu(*((u32 *)(__pStart))))
-+#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) (le16_to_cpu(*((u16 *)(__pStart))))
-+#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart))))
-+
-+/*
-+* Return 4-byte value in host byte ordering from 4-byte pointer in big-endian system.
-+*/
-+#define BE_P4BYTE_TO_HOST_4BYTE(__pStart) (be32_to_cpu(*((u32 *)(__pStart))))
-+#define BE_P2BYTE_TO_HOST_2BYTE(__pStart) (be16_to_cpu(*((u16 *)(__pStart))))
-+#define BE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart))))
-+
-+/*
-+* Translate subfield (continuous bits in little-endian) of 4-byte value in LE byte to
-+* 4-byte value in host byte ordering.
-+*/
-+#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
-+	((LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen))
-+
-+#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
-+	((LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen))
-+
-+#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
-+	((LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen))
-+
-+/*
-+* Translate subfield (continuous bits in big-endian) of 4-byte value in BE byte to
-+* 4-byte value in host byte ordering.
-+*/
-+#define BE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
-+	((BE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen))
-+
-+#define BE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
-+	((BE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen))
-+
-+#define BE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
-+	((BE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen))
-+
-+/*
-+* Mask subfield (continuous bits in little-endian) of 4-byte value in LE byte oredering
-+* and return the result in 4-byte value in host byte ordering.
-+*/
-+#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
-+	(LE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)))
-+
-+#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
-+	(LE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen)))
-+
-+#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
-+	(LE_P1BYTE_TO_HOST_1BYTE(__pStart) & ((u8)(~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen))))
-+
-+/*
-+* Mask subfield (continuous bits in big-endian) of 4-byte value in BE byte oredering
-+* and return the result in 4-byte value in host byte ordering.
-+*/
-+#define BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
-+	(BE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)))
-+
-+#define BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
-+	(BE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen)))
-+
-+#define BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
-+	(BE_P1BYTE_TO_HOST_1BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen)))
-+
-+/*
-+* Set subfield of little-endian 4-byte value to specified value.
-+*/
-+#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
-+	do { \
-+		if (__BitOffset == 0 && __BitLen == 32) \
-+			WriteLE4Byte(__pStart, __Value); \
-+		else { \
-+			WriteLE4Byte(__pStart, \
-+				LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
-+				| \
-+				((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \
-+			); \
-+		} \
-+	} while (0)
-+
-+#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
-+	do { \
-+		if (__BitOffset == 0 && __BitLen == 16) \
-+			WriteLE2Byte(__pStart, __Value); \
-+		else { \
-+			WriteLE2Byte(__pStart, \
-+				LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
-+				| \
-+				((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \
-+			); \
-+		} \
-+	} while (0)
-+
-+#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
-+	do { \
-+		if (__BitOffset == 0 && __BitLen == 8) \
-+			WriteLE1Byte(__pStart, __Value); \
-+		else { \
-+			WriteLE1Byte(__pStart, \
-+				LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
-+				| \
-+				((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \
-+			); \
-+		} \
-+	} while (0)
-+
-+/*
-+* Set subfield of big-endian 4-byte value to specified value.
-+*/
-+#define SET_BITS_TO_BE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
-+	do { \
-+		if (__BitOffset == 0 && __BitLen == 32) \
-+			WriteBE4Byte(__pStart, __Value); \
-+		else { \
-+			WriteBE4Byte(__pStart, \
-+				BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
-+				| \
-+				((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \
-+			); \
-+		} \
-+	} while (0)
-+
-+#define SET_BITS_TO_BE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
-+	do { \
-+		if (__BitOffset == 0 && __BitLen == 16) \
-+			WriteBE2Byte(__pStart, __Value); \
-+		else { \
-+			WriteBE2Byte(__pStart, \
-+				BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
-+				| \
-+				((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \
-+			); \
-+		} \
-+	} while (0)
-+
-+#define SET_BITS_TO_BE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
-+	do { \
-+		if (__BitOffset == 0 && __BitLen == 8) \
-+			WriteBE1Byte(__pStart, __Value); \
-+		else { \
-+			WriteBE1Byte(__pStart, \
-+				BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
-+				| \
-+				((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \
-+			); \
-+		} \
-+	} while (0)
-+
-+/* Get the N-bytes aligment offset from the current length */
-+#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))
-+
-+typedef unsigned char	BOOLEAN, *PBOOLEAN, boolean;
-+
-+#define TEST_FLAG(__Flag, __testFlag)		(((__Flag) & (__testFlag)) != 0)
-+#define SET_FLAG(__Flag, __setFlag)			((__Flag) |= __setFlag)
-+#define CLEAR_FLAG(__Flag, __clearFlag)		((__Flag) &= ~(__clearFlag))
-+#define CLEAR_FLAGS(__Flag)					((__Flag) = 0)
-+#define TEST_FLAGS(__Flag, __testFlags)		(((__Flag) & (__testFlags)) == (__testFlags))
-+
-+#endif /* __BASIC_TYPES_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/byteorder/big_endian.h b/drivers/staging/rtl8723cs/include/byteorder/big_endian.h
-new file mode 100644
-index 000000000000..6b1dc449e578
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/byteorder/big_endian.h
-@@ -0,0 +1,82 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H
-+#define _LINUX_BYTEORDER_BIG_ENDIAN_H
-+
-+#ifndef __BIG_ENDIAN
-+	#define __BIG_ENDIAN 4321
-+#endif
-+#ifndef __BIG_ENDIAN_BITFIELD
-+	#define __BIG_ENDIAN_BITFIELD
-+#endif
-+
-+#include <byteorder/swab.h>
-+
-+#define __constant_htonl(x) ((__u32)(x))
-+#define __constant_ntohl(x) ((__u32)(x))
-+#define __constant_htons(x) ((__u16)(x))
-+#define __constant_ntohs(x) ((__u16)(x))
-+#define __constant_cpu_to_le64(x) ___constant_swab64((x))
-+#define __constant_le64_to_cpu(x) ___constant_swab64((x))
-+#define __constant_cpu_to_le32(x) ___constant_swab32((x))
-+#define __constant_le32_to_cpu(x) ___constant_swab32((x))
-+#define __constant_cpu_to_le16(x) ___constant_swab16((x))
-+#define __constant_le16_to_cpu(x) ___constant_swab16((x))
-+#define __constant_cpu_to_be64(x) ((__u64)(x))
-+#define __constant_be64_to_cpu(x) ((__u64)(x))
-+#define __constant_cpu_to_be32(x) ((__u32)(x))
-+#define __constant_be32_to_cpu(x) ((__u32)(x))
-+#define __constant_cpu_to_be16(x) ((__u16)(x))
-+#define __constant_be16_to_cpu(x) ((__u16)(x))
-+#define __cpu_to_le64(x) __swab64((x))
-+#define __le64_to_cpu(x) __swab64((x))
-+#define __cpu_to_le32(x) __swab32((x))
-+#define __le32_to_cpu(x) __swab32((x))
-+#define __cpu_to_le16(x) __swab16((x))
-+#define __le16_to_cpu(x) __swab16((x))
-+#define __cpu_to_be64(x) ((__u64)(x))
-+#define __be64_to_cpu(x) ((__u64)(x))
-+#define __cpu_to_be32(x) ((__u32)(x))
-+#define __be32_to_cpu(x) ((__u32)(x))
-+#define __cpu_to_be16(x) ((__u16)(x))
-+#define __be16_to_cpu(x) ((__u16)(x))
-+#define __cpu_to_le64p(x) __swab64p((x))
-+#define __le64_to_cpup(x) __swab64p((x))
-+#define __cpu_to_le32p(x) __swab32p((x))
-+#define __le32_to_cpup(x) __swab32p((x))
-+#define __cpu_to_le16p(x) __swab16p((x))
-+#define __le16_to_cpup(x) __swab16p((x))
-+#define __cpu_to_be64p(x) (*(__u64 *)(x))
-+#define __be64_to_cpup(x) (*(__u64 *)(x))
-+#define __cpu_to_be32p(x) (*(__u32 *)(x))
-+#define __be32_to_cpup(x) (*(__u32 *)(x))
-+#define __cpu_to_be16p(x) (*(__u16 *)(x))
-+#define __be16_to_cpup(x) (*(__u16 *)(x))
-+#define __cpu_to_le64s(x) __swab64s((x))
-+#define __le64_to_cpus(x) __swab64s((x))
-+#define __cpu_to_le32s(x) __swab32s((x))
-+#define __le32_to_cpus(x) __swab32s((x))
-+#define __cpu_to_le16s(x) __swab16s((x))
-+#define __le16_to_cpus(x) __swab16s((x))
-+#define __cpu_to_be64s(x) do {} while (0)
-+#define __be64_to_cpus(x) do {} while (0)
-+#define __cpu_to_be32s(x) do {} while (0)
-+#define __be32_to_cpus(x) do {} while (0)
-+#define __cpu_to_be16s(x) do {} while (0)
-+#define __be16_to_cpus(x) do {} while (0)
-+
-+#include <byteorder/generic.h>
-+
-+#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */
-diff --git a/drivers/staging/rtl8723cs/include/byteorder/generic.h b/drivers/staging/rtl8723cs/include/byteorder/generic.h
-new file mode 100644
-index 000000000000..f85114bf796c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/byteorder/generic.h
-@@ -0,0 +1,207 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _LINUX_BYTEORDER_GENERIC_H
-+#define _LINUX_BYTEORDER_GENERIC_H
-+
-+/*
-+ * linux/byteorder_generic.h
-+ * Generic Byte-reordering support
-+ *
-+ * Francois-Rene Rideau <fare@tunes.org> 19970707
-+ *    gathered all the good ideas from all asm-foo/byteorder.h into one file,
-+ *    cleaned them up.
-+ *    I hope it is compliant with non-GCC compilers.
-+ *    I decided to put __BYTEORDER_HAS_U64__ in byteorder.h,
-+ *    because I wasn't sure it would be ok to put it in types.h
-+ *    Upgraded it to 2.1.43
-+ * Francois-Rene Rideau <fare@tunes.org> 19971012
-+ *    Upgraded it to 2.1.57
-+ *    to please Linus T., replaced huge #ifdef's between little/big endian
-+ *    by nestedly #include'd files.
-+ * Francois-Rene Rideau <fare@tunes.org> 19971205
-+ *    Made it to 2.1.71; now a facelift:
-+ *    Put files under include/linux/byteorder/
-+ *    Split swab from generic support.
-+ *
-+ * TODO:
-+ *   = Regular kernel maintainers could also replace all these manual
-+ *    byteswap macros that remain, disseminated among drivers,
-+ *    after some grep or the sources...
-+ *   = Linus might want to rename all these macros and files to fit his taste,
-+ *    to fit his personal naming scheme.
-+ *   = it seems that a few drivers would also appreciate
-+ *    nybble swapping support...
-+ *   = every architecture could add their byteswap macro in asm/byteorder.h
-+ *    see how some architectures already do (i386, alpha, ppc, etc)
-+ *   = cpu_to_beXX and beXX_to_cpu might some day need to be well
-+ *    distinguished throughout the kernel. This is not the case currently,
-+ *    since little endian, big endian, and pdp endian machines needn't it.
-+ *    But this might be the case for, say, a port of Linux to 20/21 bit
-+ *    architectures (and F21 Linux addict around?).
-+ */
-+
-+/*
-+ * The following macros are to be defined by <asm/byteorder.h>:
-+ *
-+ * Conversion of long and short int between network and host format
-+ *	ntohl(__u32 x)
-+ *	ntohs(__u16 x)
-+ *	htonl(__u32 x)
-+ *	htons(__u16 x)
-+ * It seems that some programs (which? where? or perhaps a standard? POSIX?)
-+ * might like the above to be functions, not macros (why?).
-+ * if that's true, then detect them, and take measures.
-+ * Anyway, the measure is: define only ___ntohl as a macro instead,
-+ * and in a separate file, have
-+ * unsigned long inline ntohl(x){return ___ntohl(x);}
-+ *
-+ * The same for constant arguments
-+ *	__constant_ntohl(__u32 x)
-+ *	__constant_ntohs(__u16 x)
-+ *	__constant_htonl(__u32 x)
-+ *	__constant_htons(__u16 x)
-+ *
-+ * Conversion of XX-bit integers (16- 32- or 64-)
-+ * between native CPU format and little/big endian format
-+ * 64-bit stuff only defined for proper architectures
-+ *	cpu_to_[bl]eXX(__uXX x)
-+ *	[bl]eXX_to_cpu(__uXX x)
-+ *
-+ * The same, but takes a pointer to the value to convert
-+ *	cpu_to_[bl]eXXp(__uXX x)
-+ *	[bl]eXX_to_cpup(__uXX x)
-+ *
-+ * The same, but change in situ
-+ *	cpu_to_[bl]eXXs(__uXX x)
-+ *	[bl]eXX_to_cpus(__uXX x)
-+ *
-+ * See asm-foo/byteorder.h for examples of how to provide
-+ * architecture-optimized versions
-+ *
-+ */
-+
-+
-+#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) || defined(PLATFORM_FREEBSD)
-+	/*
-+	* inside the kernel, we can use nicknames;
-+	* outside of it, we must avoid POSIX namespace pollution...
-+	*/
-+	#define cpu_to_le64 __cpu_to_le64
-+	#define le64_to_cpu __le64_to_cpu
-+	#define cpu_to_le32 __cpu_to_le32
-+	#define le32_to_cpu __le32_to_cpu
-+	#define cpu_to_le16 __cpu_to_le16
-+	#define le16_to_cpu __le16_to_cpu
-+	#define cpu_to_be64 __cpu_to_be64
-+	#define be64_to_cpu __be64_to_cpu
-+	#define cpu_to_be32 __cpu_to_be32
-+	#define be32_to_cpu __be32_to_cpu
-+	#define cpu_to_be16 __cpu_to_be16
-+	#define be16_to_cpu __be16_to_cpu
-+	#define cpu_to_le64p __cpu_to_le64p
-+	#define le64_to_cpup __le64_to_cpup
-+	#define cpu_to_le32p __cpu_to_le32p
-+	#define le32_to_cpup __le32_to_cpup
-+	#define cpu_to_le16p __cpu_to_le16p
-+	#define le16_to_cpup __le16_to_cpup
-+	#define cpu_to_be64p __cpu_to_be64p
-+	#define be64_to_cpup __be64_to_cpup
-+	#define cpu_to_be32p __cpu_to_be32p
-+	#define be32_to_cpup __be32_to_cpup
-+	#define cpu_to_be16p __cpu_to_be16p
-+	#define be16_to_cpup __be16_to_cpup
-+	#define cpu_to_le64s __cpu_to_le64s
-+	#define le64_to_cpus __le64_to_cpus
-+	#define cpu_to_le32s __cpu_to_le32s
-+	#define le32_to_cpus __le32_to_cpus
-+	#define cpu_to_le16s __cpu_to_le16s
-+	#define le16_to_cpus __le16_to_cpus
-+	#define cpu_to_be64s __cpu_to_be64s
-+	#define be64_to_cpus __be64_to_cpus
-+	#define cpu_to_be32s __cpu_to_be32s
-+	#define be32_to_cpus __be32_to_cpus
-+	#define cpu_to_be16s __cpu_to_be16s
-+	#define be16_to_cpus __be16_to_cpus
-+#endif
-+
-+
-+/*
-+ * Handle ntohl and suches. These have various compatibility
-+ * issues - like we want to give the prototype even though we
-+ * also have a macro for them in case some strange program
-+ * wants to take the address of the thing or something..
-+ *
-+ * Note that these used to return a "long" in libc5, even though
-+ * long is often 64-bit these days.. Thus the casts.
-+ *
-+ * They have to be macros in order to do the constant folding
-+ * correctly - if the argument passed into a inline function
-+ * it is no longer constant according to gcc..
-+ */
-+
-+#undef ntohl
-+#undef ntohs
-+#undef htonl
-+#undef htons
-+
-+/*
-+ * Do the prototypes. Somebody might want to take the
-+ * address or some such sick thing..
-+ */
-+#if defined(PLATFORM_LINUX) || (defined(__GLIBC__) && __GLIBC__ >= 2)
-+	extern __u32			ntohl(__u32);
-+	extern __u32			htonl(__u32);
-+#else /* defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) */
-+	#ifndef PLATFORM_FREEBSD
-+		extern unsigned long int	ntohl(unsigned long int);
-+		extern unsigned long int	htonl(unsigned long int);
-+	#endif
-+#endif
-+#ifndef PLATFORM_FREEBSD
-+	extern unsigned short int	ntohs(unsigned short int);
-+	extern unsigned short int	htons(unsigned short int);
-+#endif
-+
-+#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) || defined(PLATFORM_MPIXEL)
-+
-+	#define ___htonl(x) __cpu_to_be32(x)
-+	#define ___htons(x) __cpu_to_be16(x)
-+	#define ___ntohl(x) __be32_to_cpu(x)
-+	#define ___ntohs(x) __be16_to_cpu(x)
-+
-+	#if defined(PLATFORM_LINUX) || (defined(__GLIBC__) && __GLIBC__ >= 2)
-+		#define htonl(x) ___htonl(x)
-+		#define ntohl(x) ___ntohl(x)
-+	#else
-+		#define htonl(x) ((unsigned long)___htonl(x))
-+		#define ntohl(x) ((unsigned long)___ntohl(x))
-+	#endif
-+	#define htons(x) ___htons(x)
-+	#define ntohs(x) ___ntohs(x)
-+
-+#endif /* OPTIMIZE */
-+
-+
-+#if defined(PLATFORM_WINDOWS)
-+
-+	#define htonl(x) __cpu_to_be32(x)
-+	#define ntohl(x) __be32_to_cpu(x)
-+	#define htons(x) __cpu_to_be16(x)
-+	#define ntohs(x) __be16_to_cpu(x)
-+
-+
-+#endif
-+
-+#endif /* _LINUX_BYTEORDER_GENERIC_H */
-diff --git a/drivers/staging/rtl8723cs/include/byteorder/little_endian.h b/drivers/staging/rtl8723cs/include/byteorder/little_endian.h
-new file mode 100644
-index 000000000000..c4b64512f296
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/byteorder/little_endian.h
-@@ -0,0 +1,84 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H
-+#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H
-+
-+#ifndef __LITTLE_ENDIAN
-+	#define __LITTLE_ENDIAN 1234
-+#endif
-+#ifndef __LITTLE_ENDIAN_BITFIELD
-+	#define __LITTLE_ENDIAN_BITFIELD
-+#endif
-+
-+#include <byteorder/swab.h>
-+
-+#ifndef __constant_htonl
-+	#define __constant_htonl(x) ___constant_swab32((x))
-+	#define __constant_ntohl(x) ___constant_swab32((x))
-+	#define __constant_htons(x) ___constant_swab16((x))
-+	#define __constant_ntohs(x) ___constant_swab16((x))
-+	#define __constant_cpu_to_le64(x) ((__u64)(x))
-+	#define __constant_le64_to_cpu(x) ((__u64)(x))
-+	#define __constant_cpu_to_le32(x) ((__u32)(x))
-+	#define __constant_le32_to_cpu(x) ((__u32)(x))
-+	#define __constant_cpu_to_le16(x) ((__u16)(x))
-+	#define __constant_le16_to_cpu(x) ((__u16)(x))
-+	#define __constant_cpu_to_be64(x) ___constant_swab64((x))
-+	#define __constant_be64_to_cpu(x) ___constant_swab64((x))
-+	#define __constant_cpu_to_be32(x) ___constant_swab32((x))
-+	#define __constant_be32_to_cpu(x) ___constant_swab32((x))
-+	#define __constant_cpu_to_be16(x) ___constant_swab16((x))
-+	#define __constant_be16_to_cpu(x) ___constant_swab16((x))
-+	#define __cpu_to_le64(x) ((__u64)(x))
-+	#define __le64_to_cpu(x) ((__u64)(x))
-+	#define __cpu_to_le32(x) ((__u32)(x))
-+	#define __le32_to_cpu(x) ((__u32)(x))
-+	#define __cpu_to_le16(x) ((__u16)(x))
-+	#define __le16_to_cpu(x) ((__u16)(x))
-+	#define __cpu_to_be64(x) __swab64((x))
-+	#define __be64_to_cpu(x) __swab64((x))
-+	#define __cpu_to_be32(x) __swab32((x))
-+	#define __be32_to_cpu(x) __swab32((x))
-+	#define __cpu_to_be16(x) __swab16((x))
-+	#define __be16_to_cpu(x) __swab16((x))
-+	#define __cpu_to_le64p(x) (*(__u64 *)(x))
-+	#define __le64_to_cpup(x) (*(__u64 *)(x))
-+	#define __cpu_to_le32p(x) (*(__u32 *)(x))
-+	#define __le32_to_cpup(x) (*(__u32 *)(x))
-+	#define __cpu_to_le16p(x) (*(__u16 *)(x))
-+	#define __le16_to_cpup(x) (*(__u16 *)(x))
-+	#define __cpu_to_be64p(x) __swab64p((x))
-+	#define __be64_to_cpup(x) __swab64p((x))
-+	#define __cpu_to_be32p(x) __swab32p((x))
-+	#define __be32_to_cpup(x) __swab32p((x))
-+	#define __cpu_to_be16p(x) __swab16p((x))
-+	#define __be16_to_cpup(x) __swab16p((x))
-+	#define __cpu_to_le64s(x) do {} while (0)
-+	#define __le64_to_cpus(x) do {} while (0)
-+	#define __cpu_to_le32s(x) do {} while (0)
-+	#define __le32_to_cpus(x) do {} while (0)
-+	#define __cpu_to_le16s(x) do {} while (0)
-+	#define __le16_to_cpus(x) do {} while (0)
-+	#define __cpu_to_be64s(x) __swab64s((x))
-+	#define __be64_to_cpus(x) __swab64s((x))
-+	#define __cpu_to_be32s(x) __swab32s((x))
-+	#define __be32_to_cpus(x) __swab32s((x))
-+	#define __cpu_to_be16s(x) __swab16s((x))
-+	#define __be16_to_cpus(x) __swab16s((x))
-+#endif /* __constant_htonl */
-+
-+#include <byteorder/generic.h>
-+
-+#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */
-diff --git a/drivers/staging/rtl8723cs/include/byteorder/swab.h b/drivers/staging/rtl8723cs/include/byteorder/swab.h
-new file mode 100644
-index 000000000000..a8dd46bd3a60
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/byteorder/swab.h
-@@ -0,0 +1,136 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _LINUX_BYTEORDER_SWAB_H
-+#define _LINUX_BYTEORDER_SWAB_H
-+
-+#if !defined(CONFIG_PLATFORM_MSTAR)
-+#ifndef __u16
-+	typedef unsigned short __u16;
-+#endif
-+
-+#ifndef __u32
-+	typedef unsigned int	__u32;
-+#endif
-+
-+#ifndef __u8
-+	typedef unsigned char __u8;
-+#endif
-+
-+#ifndef __u64
-+	typedef unsigned long long	__u64;
-+#endif
-+
-+
-+__inline static __u16  ___swab16(__u16 x)
-+{
-+	__u16 __x = x;
-+	return
-+		 (__u16)(
-+			 (((__u16)(__x)&(__u16)0x00ffU) << 8) |
-+			 (((__u16)(__x)&(__u16)0xff00U) >> 8));
-+
-+}
-+
-+__inline static __u32  ___swab32(__u32 x)
-+{
-+	__u32 __x = (x);
-+	return  (__u32)(
-+			(((__u32)(__x)&(__u32)0x000000ffUL) << 24) |
-+			(((__u32)(__x)&(__u32)0x0000ff00UL) <<  8) |
-+			(((__u32)(__x)&(__u32)0x00ff0000UL) >>  8) |
-+			(((__u32)(__x)&(__u32)0xff000000UL) >> 24));
-+}
-+
-+__inline static __u64  ___swab64(__u64 x)
-+{
-+	__u64 __x = (x);
-+
-+	return
-+		 (__u64)(\
-+		 (__u64)(((__u64)(__x)&(__u64)0x00000000000000ffULL) << 56) | \
-+		 (__u64)(((__u64)(__x)&(__u64)0x000000000000ff00ULL) << 40) | \
-+		 (__u64)(((__u64)(__x)&(__u64)0x0000000000ff0000ULL) << 24) | \
-+		 (__u64)(((__u64)(__x)&(__u64)0x00000000ff000000ULL) <<  8) | \
-+		 (__u64)(((__u64)(__x)&(__u64)0x000000ff00000000ULL) >>  8) | \
-+		 (__u64)(((__u64)(__x)&(__u64)0x0000ff0000000000ULL) >> 24) | \
-+		 (__u64)(((__u64)(__x)&(__u64)0x00ff000000000000ULL) >> 40) | \
-+		 (__u64)(((__u64)(__x)&(__u64)0xff00000000000000ULL) >> 56));
-+	\
-+}
-+#endif /* CONFIG_PLATFORM_MSTAR */
-+
-+#ifndef __arch__swab16
-+__inline static __u16 __arch__swab16(__u16 x)
-+{
-+	return ___swab16(x);
-+}
-+
-+#endif
-+
-+#ifndef __arch__swab32
-+__inline static __u32 __arch__swab32(__u32 x)
-+{
-+	__u32 __tmp = (x) ;
-+	return ___swab32(__tmp);
-+}
-+#endif
-+
-+#ifndef __arch__swab64
-+
-+__inline static __u64 __arch__swab64(__u64 x)
-+{
-+	__u64 __tmp = (x) ;
-+	return ___swab64(__tmp);
-+}
-+
-+
-+#endif
-+
-+#ifndef __swab16
-+	#define __swab16(x) __fswab16(x)
-+	#define __swab32(x) __fswab32(x)
-+	#define __swab64(x) __fswab64(x)
-+#endif /* __swab16 */
-+
-+#ifdef PLATFORM_FREEBSD
-+	__inline static __u16 __fswab16(__u16 x)
-+#else
-+	__inline static const __u16 __fswab16(__u16 x)
-+#endif /* PLATFORM_FREEBSD */
-+{
-+	return __arch__swab16(x);
-+}
-+#ifdef PLATFORM_FREEBSD
-+	__inline static __u32 __fswab32(__u32 x)
-+#else
-+	__inline static const __u32 __fswab32(__u32 x)
-+#endif /* PLATFORM_FREEBSD */
-+{
-+	return __arch__swab32(x);
-+}
-+
-+#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS)
-+	#define swab16 __swab16
-+	#define swab32 __swab32
-+	#define swab64 __swab64
-+	#define swab16p __swab16p
-+	#define swab32p __swab32p
-+	#define swab64p __swab64p
-+	#define swab16s __swab16s
-+	#define swab32s __swab32s
-+	#define swab64s __swab64s
-+#endif
-+
-+#endif /* _LINUX_BYTEORDER_SWAB_H */
-diff --git a/drivers/staging/rtl8723cs/include/byteorder/swabb.h b/drivers/staging/rtl8723cs/include/byteorder/swabb.h
-new file mode 100644
-index 000000000000..634519a0b826
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/byteorder/swabb.h
-@@ -0,0 +1,151 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _LINUX_BYTEORDER_SWABB_H
-+#define _LINUX_BYTEORDER_SWABB_H
-+
-+/*
-+ * linux/byteorder/swabb.h
-+ * SWAp Bytes Bizarrely
-+ *	swaHHXX[ps]?(foo)
-+ *
-+ * Support for obNUXIous pdp-endian and other bizarre architectures.
-+ * Will Linux ever run on such ancient beasts? if not, this file
-+ * will be but a programming pearl. Still, it's a reminder that we
-+ * shouldn't be making too many assumptions when trying to be portable.
-+ *
-+ */
-+
-+/*
-+ * Meaning of the names I chose (vaxlinux people feel free to correct them):
-+ * swahw32	swap 16-bit half-words in a 32-bit word
-+ * swahb32	swap 8-bit halves of each 16-bit half-word in a 32-bit word
-+ *
-+ * No 64-bit support yet. I don't know NUXI conventions for long longs.
-+ * I guarantee it will be a mess when it's there, though :->
-+ * It will be even worse if there are conflicting 64-bit conventions.
-+ * Hopefully, no one ever used 64-bit objects on NUXI machines.
-+ *
-+ */
-+
-+#define ___swahw32(x) \
-+	({ \
-+		__u32 __x = (x); \
-+		((__u32)(\
-+			 (((__u32)(__x) & (__u32)0x0000ffffUL) << 16) | \
-+			 (((__u32)(__x) & (__u32)0xffff0000UL) >> 16))); \
-+	})
-+#define ___swahb32(x) \
-+	({ \
-+		__u32 __x = (x); \
-+		((__u32)(\
-+			 (((__u32)(__x) & (__u32)0x00ff00ffUL) << 8) | \
-+			 (((__u32)(__x) & (__u32)0xff00ff00UL) >> 8))); \
-+	})
-+
-+#define ___constant_swahw32(x) \
-+	((__u32)(\
-+		 (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \
-+		 (((__u32)(x) & (__u32)0xffff0000UL) >> 16)))
-+#define ___constant_swahb32(x) \
-+	((__u32)(\
-+		 (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \
-+		 (((__u32)(x) & (__u32)0xff00ff00UL) >> 8)))
-+
-+/*
-+ * provide defaults when no architecture-specific optimization is detected
-+ */
-+#ifndef __arch__swahw32
-+	#define __arch__swahw32(x) ___swahw32(x)
-+#endif
-+#ifndef __arch__swahb32
-+	#define __arch__swahb32(x) ___swahb32(x)
-+#endif
-+
-+#ifndef __arch__swahw32p
-+	#define __arch__swahw32p(x) __swahw32(*(x))
-+#endif
-+#ifndef __arch__swahb32p
-+	#define __arch__swahb32p(x) __swahb32(*(x))
-+#endif
-+
-+#ifndef __arch__swahw32s
-+	#define __arch__swahw32s(x) do { *(x) = __swahw32p((x)); } while (0)
-+#endif
-+#ifndef __arch__swahb32s
-+	#define __arch__swahb32s(x) do { *(x) = __swahb32p((x)); } while (0)
-+#endif
-+
-+
-+/*
-+ * Allow constant folding
-+ */
-+#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__)
-+#  define __swahw32(x) \
-+	(__builtin_constant_p((__u32)(x)) ? \
-+	 ___swahw32((x)) : \
-+	 __fswahw32((x)))
-+#  define __swahb32(x) \
-+	(__builtin_constant_p((__u32)(x)) ? \
-+	 ___swahb32((x)) : \
-+	 __fswahb32((x)))
-+#else
-+#  define __swahw32(x) __fswahw32(x)
-+#  define __swahb32(x) __fswahb32(x)
-+#endif /* OPTIMIZE */
-+
-+
-+__inline static__ __const__ __u32 __fswahw32(__u32 x)
-+{
-+	return __arch__swahw32(x);
-+}
-+__inline static__ __u32 __swahw32p(__u32 *x)
-+{
-+	return __arch__swahw32p(x);
-+}
-+__inline static__ void __swahw32s(__u32 *addr)
-+{
-+	__arch__swahw32s(addr);
-+}
-+
-+
-+__inline static__ __const__ __u32 __fswahb32(__u32 x)
-+{
-+	return __arch__swahb32(x);
-+}
-+__inline static__ __u32 __swahb32p(__u32 *x)
-+{
-+	return __arch__swahb32p(x);
-+}
-+__inline static__ void __swahb32s(__u32 *addr)
-+{
-+	__arch__swahb32s(addr);
-+}
-+
-+#ifdef __BYTEORDER_HAS_U64__
-+	/*
-+	* Not supported yet
-+	*/
-+#endif /* __BYTEORDER_HAS_U64__ */
-+
-+#if defined(PLATFORM_LINUX)
-+	#define swahw32 __swahw32
-+	#define swahb32 __swahb32
-+	#define swahw32p __swahw32p
-+	#define swahb32p __swahb32p
-+	#define swahw32s __swahw32s
-+	#define swahb32s __swahb32s
-+#endif
-+
-+#endif /* _LINUX_BYTEORDER_SWABB_H */
-diff --git a/drivers/staging/rtl8723cs/include/circ_buf.h b/drivers/staging/rtl8723cs/include/circ_buf.h
-new file mode 100644
-index 000000000000..7a5b8ef1a202
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/circ_buf.h
-@@ -0,0 +1,23 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __CIRC_BUF_H_
-+#define __CIRC_BUF_H_ 1
-+
-+#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1))
-+
-+#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
-+
-+#endif //_CIRC_BUF_H_
-+
-diff --git a/drivers/staging/rtl8723cs/include/cmd_osdep.h b/drivers/staging/rtl8723cs/include/cmd_osdep.h
-new file mode 100644
-index 000000000000..e4ba2b6d3b62
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/cmd_osdep.h
-@@ -0,0 +1,26 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __CMD_OSDEP_H_
-+#define __CMD_OSDEP_H_
-+
-+
-+extern sint _rtw_init_cmd_priv(struct	cmd_priv *pcmdpriv);
-+extern sint _rtw_init_evt_priv(struct evt_priv *pevtpriv);
-+extern void _rtw_free_evt_priv(struct	evt_priv *pevtpriv);
-+extern void _rtw_free_cmd_priv(struct	cmd_priv *pcmdpriv);
-+extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head);
-+extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/cmn_info/rtw_sta_info.h b/drivers/staging/rtl8723cs/include/cmn_info/rtw_sta_info.h
-new file mode 100644
-index 000000000000..d4de0e50be23
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/cmn_info/rtw_sta_info.h
-@@ -0,0 +1,279 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
-+ *
-+ *
-+ ******************************************************************************/
-+
-+ /*This header file is for all driver teams to use the same station info.
-+If you want to change this file please make sure notify all driver teams maintainers.*/
-+
-+/*Created by YuChen 20170301*/
-+
-+#ifndef __INC_RTW_STA_INFO_H
-+#define __INC_RTW_STA_INFO_H
-+
-+/*--------------------Define ---------------------------------------*/
-+
-+#define STA_DM_CTRL_ACTIVE			BIT(0)
-+#define STA_DM_CTRL_CFO_TRACKING	BIT(1)
-+
-+#ifdef CONFIG_BEAMFORMING
-+#define	BEAMFORMING_HT_BEAMFORMER_ENABLE	BIT(0)	/*Declare sta support beamformer*/
-+#define	BEAMFORMING_HT_BEAMFORMEE_ENABLE	BIT(1)	/*Declare sta support beamformee*/
-+#define	BEAMFORMING_HT_BEAMFORMER_TEST		BIT(2)	/*Transmiting Beamforming no matter the target supports it or not*/
-+#define	BEAMFORMING_HT_BEAMFORMER_STEER_NUM		(BIT(4)|BIT(5))		/*Sta Bfer's capability*/
-+#define	BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP	(BIT(6)|BIT(7))		/*Sta BFee's capability*/
-+
-+#define	BEAMFORMING_VHT_BEAMFORMER_ENABLE	BIT(0)	/*Declare sta support beamformer*/
-+#define	BEAMFORMING_VHT_BEAMFORMEE_ENABLE	BIT(1)	/*Declare sta support beamformee*/
-+#define	BEAMFORMING_VHT_MU_MIMO_AP_ENABLE	BIT(2)	/*Declare sta support MU beamformer*/
-+#define	BEAMFORMING_VHT_MU_MIMO_STA_ENABLE	BIT(3)	/*Declare sta support MU beamformer*/
-+#define	BEAMFORMING_VHT_BEAMFORMER_TEST		BIT(4)	/*Transmiting Beamforming no matter the target supports it or not*/
-+#define	BEAMFORMING_VHT_BEAMFORMER_STS_CAP		(BIT(8)|BIT(9)|BIT(10))		/*Sta BFee's capability*/
-+#define	BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM	(BIT(12)|BIT(13)|BIT(14))	/*Sta Bfer's capability*/
-+#endif
-+
-+#define HT_STBC_EN	BIT(0)
-+#define VHT_STBC_EN	BIT(1)
-+
-+#define HT_LDPC_EN	BIT(0)
-+#define VHT_LDPC_EN	BIT(1)
-+
-+#define	SM_PS_STATIC	0
-+#define	SM_PS_DYNAMIC	1
-+#define	SM_PS_INVALID	2
-+#define	SM_PS_DISABLE	3
-+
-+
-+/*cmn_sta_info.ra_sta_info.txrx_state*/
-+#define	TX_STATE				0
-+#define	RX_STATE				1
-+#define	BI_DIRECTION_STATE	2
-+
-+/*--------------------Define Enum-----------------------------------*/
-+enum channel_width {
-+	CHANNEL_WIDTH_20		= 0,
-+	CHANNEL_WIDTH_40		= 1,
-+	CHANNEL_WIDTH_80		= 2,
-+	CHANNEL_WIDTH_160		= 3,
-+	CHANNEL_WIDTH_80_80	= 4,
-+	CHANNEL_WIDTH_5		= 5,
-+	CHANNEL_WIDTH_10	= 6,
-+	CHANNEL_WIDTH_MAX	= 7,
-+};
-+
-+enum rf_type {
-+	RF_1T1R			= 0,
-+	RF_1T2R			= 1,
-+	RF_2T2R			= 2,
-+	RF_2T3R			= 3,
-+	RF_2T4R			= 4,
-+	RF_3T3R			= 5,
-+	RF_3T4R			= 6,
-+	RF_4T4R			= 7,
-+	RF_4T3R			= 8,
-+	RF_4T2R			= 9,
-+	RF_4T1R			= 10,
-+	RF_3T2R			= 11,
-+	RF_3T1R			= 12,
-+	RF_2T1R			= 13,
-+	RF_1T4R			= 14,
-+	RF_1T3R			= 15,
-+	RF_TYPE_MAX,
-+};
-+
-+enum bb_path {
-+	BB_PATH_NON = 0,
-+	BB_PATH_A = 0x00000001,
-+	BB_PATH_B = 0x00000002,
-+	BB_PATH_C = 0x00000004,
-+	BB_PATH_D = 0x00000008,
-+
-+	BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
-+	BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
-+	BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
-+	BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
-+	BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
-+	BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
-+
-+	BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
-+	BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
-+	BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
-+	BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
-+
-+	BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
-+	BB_PATH_AUTO = 0xff /*for path diversity*/
-+};
-+
-+enum rf_path {
-+	RF_PATH_A = 0,
-+	RF_PATH_B = 1,
-+	RF_PATH_C = 2,
-+	RF_PATH_D = 3,
-+	RF_PATH_AB,
-+	RF_PATH_AC,
-+	RF_PATH_AD,
-+	RF_PATH_BC,
-+	RF_PATH_BD,
-+	RF_PATH_CD,
-+	RF_PATH_ABC,
-+	RF_PATH_ABD,
-+	RF_PATH_ACD,
-+	RF_PATH_BCD,
-+	RF_PATH_ABCD,
-+};
-+
-+enum rf_syn {
-+	RF_SYN0 = 0,
-+	RF_SYN1 = 1,
-+};
-+
-+enum rfc_mode {
-+	rfc_4x4 = 0,
-+	rfc_2x2 = 1,
-+};
-+
-+enum wireless_set {
-+	WIRELESS_CCK	= 0x00000001,
-+	WIRELESS_OFDM	= 0x00000002,
-+	WIRELESS_HT	= 0x00000004,
-+	WIRELESS_VHT	= 0x00000008,
-+};
-+
-+/*--------------------Define MACRO---------------------------------*/
-+
-+/*--------------------Define Struct-----------------------------------*/
-+
-+#ifdef CONFIG_BEAMFORMING
-+struct bf_cmn_info {
-+	u8	ht_beamform_cap;		/*Sta capablity*/
-+	u16	vht_beamform_cap;		/*Sta capablity*/
-+	u16	p_aid;
-+	u8	g_id;
-+};
-+#endif
-+struct rssi_info {
-+	s8		rssi;
-+	s8		rssi_cck;
-+	s8		rssi_ofdm;
-+	u8		packet_map;
-+	u8		ofdm_pkt_cnt;
-+	u8		cck_pkt_cnt;
-+	u16		cck_sum_power;
-+	u8		is_send_rssi;
-+	u8		valid_bit;
-+	s16		rssi_acc;	/*accumulate RSSI for per packet MA sum*/
-+};
-+
-+struct ra_sta_info {
-+	u8	rate_id;			/*[PHYDM] ratr_idx*/
-+	u8	rssi_level;			/*[PHYDM]*/
-+	u8	is_first_connect:1;		/*[PHYDM] CE: ra_rpt_linked, AP: H2C_rssi_rpt*/
-+	u8	is_support_sgi:1;		/*[driver]*/
-+	u8	is_vht_enable:2;		/*[driver]*/
-+	u8	disable_ra:1;			/*[driver]*/
-+	u8	disable_pt:1;			/*[driver] remove is_disable_power_training*/
-+	u8	txrx_state:2;			/*[PHYDM] 0: Tx, 1:Rx, 2:bi-direction*/
-+	u8	is_noisy:1;			/*[PHYDM]*/
-+	u8	curr_tx_rate;			/*[PHYDM] FW->Driver*/
-+	enum channel_width	ra_bw_mode;	/*[Driver] max bandwidth, for RA only*/
-+	enum channel_width	curr_tx_bw;	/*[PHYDM] FW->Driver*/
-+	u8	curr_retry_ratio;		/*[PHYDM] FW->Driver*/
-+	u64	ramask;
-+};
-+
-+struct dtp_info {
-+	u8	dyn_tx_power;	/*Dynamic Tx power offset*/
-+	u8	last_tx_power;
-+	boolean	sta_is_alive;
-+	u8	sta_tx_high_power_lvl:4;
-+	u8	sta_last_dtp_lvl:4;
-+};
-+
-+struct cmn_sta_info {
-+	u16	dm_ctrl;			/*[Driver]*/
-+	enum channel_width	bw_mode;	/*[Driver] max support BW*/
-+	u8	mac_id;				/*[Driver]*/
-+	u8	mac_addr[6];			/*[Driver]*/
-+	u16	aid;				/*[Driver]*/
-+	enum rf_type mimo_type;			/*[Driver] sta XTXR*/
-+	struct rssi_info	rssi_stat;	/*[PHYDM]*/
-+	struct ra_sta_info	ra_info;	/*[Driver&PHYDM]*/
-+	u16	tx_moving_average_tp;		/*[Driver] tx average MBps*/
-+	u16	rx_moving_average_tp;		/*[Driver] rx average MBps*/
-+	u8	stbc_en:2;			/*[Driver] really transmitt STBC*/
-+	u8	ldpc_en:2;			/*[Driver] really transmitt LDPC*/
-+	enum wireless_set	support_wireless_set;/*[Driver]*/
-+#ifdef CONFIG_BEAMFORMING
-+	struct bf_cmn_info	bf_info;	/*[Driver]*/
-+#endif
-+	u8	sm_ps:2;			/*[Driver]*/
-+	struct dtp_info dtp_stat;		/*[PHYDM] Dynamic Tx power offset*/
-+	/*u8		pw2cca_over_TH_cnt;*/
-+	/*u8		total_pw2cca_cnt;*/
-+};
-+
-+struct phydm_phyinfo_fw_struct {
-+	u8		rx_rssi[4];	/* RSSI in 0~100 index */
-+};
-+
-+struct phydm_phyinfo_struct {
-+	boolean		physts_rpt_valid; /* @if physts_rpt_valid is false, please ignore the parsing result in this structure*/
-+	u8		rx_pwdb_all;
-+	u8		signal_quality;				/* OFDM: signal_quality=rx_mimo_signal_quality[0], CCK: signal qualityin 0-100 index. */
-+	u8		rx_mimo_signal_strength[4];	/* RSSI in 0~100 index */
-+	s8		rx_mimo_signal_quality[4];		/* OFDM: per-path's EVM translate to 0~100% , no used for CCK*/
-+	u8		rx_mimo_evm_dbm[4];			/* per-path's original EVM (dbm) */
-+	s16		cfo_short[4];					/* per-path's cfo_short */
-+	s16		cfo_tail[4];					/* per-path's cfo_tail */
-+	s8		rx_power;					/* in dBm Translate from PWdB */
-+	s8		recv_signal_power;			/* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */
-+	u8		bt_rx_rssi_percentage;
-+	u8		signal_strength;				/* in 0-100 index. */
-+	s8		rx_pwr[4];					/* per-path's pwdb */
-+	s8		rx_snr[4];					/* per-path's SNR	*/
-+	u8		ant_idx[4];	/*per-path's antenna index*/
-+/*ODM_PHY_STATUS_NEW_TYPE_SUPPORT*/
-+	u8		rx_count:2;					/* RX path counter---*/
-+	u8		band_width:3;
-+	u8		rxsc:4;						/* sub-channel---*/
-+	u8		channel;						/* channel number---*/
-+	u8		is_mu_packet:1;				/* is MU packet or not---boolean*/
-+	u8		is_beamformed:1;				/* BF packet---boolean*/
-+	u8		cnt_pw2cca;
-+	u8		cnt_cca2agc_rdy;
-+/*ODM_PHY_STATUS_NEW_TYPE_SUPPORT*/
-+	u8		rx_cck_evm;
-+};
-+
-+struct phydm_perpkt_info_struct {
-+	u8		data_rate;
-+	u8		station_id;
-+	u8		is_cck_rate: 1;
-+	u8		rate_ss:3;			/*spatial stream of data rate*/
-+	u8		is_packet_match_bssid:1;	/*boolean*/
-+	u8		is_packet_to_self:1;		/*boolean*/
-+	u8		is_packet_beacon:1;		/*boolean*/
-+	u8		is_to_self:1;				/*boolean*/
-+	u8		ppdu_cnt;
-+};
-+
-+/*--------------------Export global variable----------------------------*/
-+
-+/*--------------------Function declaration-----------------------------*/
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/custom_gpio.h b/drivers/staging/rtl8723cs/include/custom_gpio.h
-new file mode 100644
-index 000000000000..3c67735d689a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/custom_gpio.h
-@@ -0,0 +1,34 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __CUSTOM_GPIO_H__
-+#define __CUSTOM_GPIO_H___
-+
-+#include <drv_conf.h>
-+#include <osdep_service.h>
-+
-+typedef enum cust_gpio_modes {
-+	WLAN_PWDN_ON,
-+	WLAN_PWDN_OFF,
-+	WLAN_POWER_ON,
-+	WLAN_POWER_OFF,
-+	WLAN_BT_PWDN_ON,
-+	WLAN_BT_PWDN_OFF
-+} cust_gpio_modes_t;
-+
-+extern int rtw_wifi_gpio_init(void);
-+extern int rtw_wifi_gpio_deinit(void);
-+extern void rtw_wifi_gpio_wlan_ctrl(int onoff);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/drv_conf.h b/drivers/staging/rtl8723cs/include/drv_conf.h
-new file mode 100644
-index 000000000000..5b528680380f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/drv_conf.h
-@@ -0,0 +1,793 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __DRV_CONF_H__
-+#define __DRV_CONF_H__
-+#include "autoconf.h"
-+#include "hal_ic_cfg.h"
-+
-+#define CONFIG_RSSI_PRIORITY
-+
-+/* 
-+ * RTW_BUSY_DENY_SCAN control if scan would be denied by busy traffic.
-+ * When this defined, BUSY_TRAFFIC_SCAN_DENY_PERIOD would be used to judge if 
-+ * scan request coming from scan UI. Scan request from scan UI would be
-+ * exception and never be denied by busy traffic.
-+ */
-+#define RTW_BUSY_DENY_SCAN
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	#ifndef CONFIG_AP
-+		#define CONFIG_AP
-+	#endif
-+	#ifndef CONFIG_CONCURRENT_MODE
-+		#define CONFIG_CONCURRENT_MODE
-+	#endif
-+	#ifndef CONFIG_BR_EXT
-+		#define CONFIG_BR_EXT
-+	#endif
-+	#ifndef CONFIG_RTW_REPEATER_SON_ID
-+		#define CONFIG_RTW_REPEATER_SON_ID			0x02040608
-+	#endif
-+	//#define CONFIG_RTW_REPEATER_SON_ROOT
-+        #ifndef CONFIG_RTW_REPEATER_SON_ROOT
-+		#undef CONFIG_ROAMING_FLAG
-+        	#define CONFIG_ROAMING_FLAG	0x7
-+        #endif
-+	#undef CONFIG_POWER_SAVING
-+#endif
-+
-+#if defined(CONFIG_MCC_MODE) && (!defined(CONFIG_CONCURRENT_MODE))
-+
-+	#error "Enable CONCURRENT_MODE before enable MCC MODE\n"
-+
-+#endif
-+
-+#if defined(CONFIG_MCC_MODE) && defined(CONFIG_BT_COEXIST)
-+
-+	#error "Disable BT COEXIST before enable MCC MODE\n"
-+
-+#endif
-+
-+#if defined(CONFIG_MCC_MODE) && defined(CONFIG_TDLS)
-+
-+	#error "Disable TDLS before enable MCC MODE\n"
-+
-+#endif
-+
-+#if defined(CONFIG_RTW_80211R) && !defined(CONFIG_LAYER2_ROAMING)
-+
-+	#error "Enable CONFIG_LAYER2_ROAMING before enable CONFIG_RTW_80211R\n"
-+
-+#endif
-+
-+/* Default enable single wiphy if driver ver >= 5.9 */
-+#define RTW_SINGLE_WIPHY
-+
-+#ifdef CONFIG_RTW_ANDROID
-+
-+	#include <linux/version.h>
-+	
-+	#ifndef CONFIG_IOCTL_CFG80211
-+	#define CONFIG_IOCTL_CFG80211
-+	#endif
-+	
-+	#ifndef RTW_USE_CFG80211_STA_EVENT
-+	#define RTW_USE_CFG80211_STA_EVENT
-+	#endif
-+
-+	#if (CONFIG_RTW_ANDROID > 4)
-+	#ifndef CONFIG_RADIO_WORK
-+	#define CONFIG_RADIO_WORK
-+	#endif
-+	#endif
-+
-+	#if (CONFIG_RTW_ANDROID <= 7)
-+		#ifdef RTW_SINGLE_WIPHY
-+		#undef RTW_SINGLE_WIPHY
-+		#endif
-+	#endif
-+
-+	#if (CONFIG_RTW_ANDROID >= 8)
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,0))
-+		#ifndef CONFIG_RTW_WIFI_HAL
-+		#define CONFIG_RTW_WIFI_HAL
-+		#endif
-+		#else
-+ 		#error "Linux kernel version is too old\n"
-+		#endif
-+	#endif
-+
-+	#ifdef CONFIG_RTW_WIFI_HAL
-+	#ifndef CONFIG_RTW_WIFI_HAL_DEBUG
-+	//#define CONFIG_RTW_WIFI_HAL_DEBUG
-+	#endif
-+	#ifndef CONFIG_RTW_CFGVENDOR_LLSTATS
-+	#define CONFIG_RTW_CFGVENDOR_LLSTATS
-+	#endif
-+	#if (CONFIG_RTW_ANDROID < 11)
-+	#ifndef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+	#define CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+	#endif
-+	#endif
-+	#ifndef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
-+	#define CONFIG_RTW_CFGVENDOR_RSSIMONITOR
-+	#endif
-+	#ifndef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
-+	#define CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
-+	#endif
-+	#if (CONFIG_RTW_ANDROID >= 10)
-+	#ifndef CONFIG_RTW_CFGVENDOR_WIFI_OFFLOAD
-+	//#define CONFIG_RTW_CFGVENDOR_WIFI_OFFLOAD
-+	#endif
-+	#ifndef CONFIG_RTW_HOSTAPD_ACS
-+	#define CONFIG_RTW_HOSTAPD_ACS
-+	#endif
-+	#ifndef CONFIG_KERNEL_PATCH_EXTERNAL_AUTH
-+	#define CONFIG_KERNEL_PATCH_EXTERNAL_AUTH
-+	#endif
-+	#ifndef CONFIG_RTW_ABORT_SCAN
-+	#define CONFIG_RTW_ABORT_SCAN
-+	#endif
-+	#endif
-+	#endif // CONFIG_RTW_WIFI_HAL
-+
-+
-+	/* Some Android build will restart the UI while non-printable ascii is passed
-+	* between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID
-+	* for Android here. If you are sure there is no risk on your system about this,
-+	* mask this macro define to support non-printable ascii ssid.
-+	* #define CONFIG_VALIDATE_SSID */
-+
-+	/* Android expect dbm as the rx signal strength unit */
-+	#define CONFIG_SIGNAL_DISPLAY_DBM
-+#endif // CONFIG_RTW_ANDROID
-+
-+/*
-+#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(CONFIG_RESUME_IN_WORKQUEUE)
-+	#warning "You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
-+	#undef CONFIG_RESUME_IN_WORKQUEUE
-+#endif
-+
-+#if defined(CONFIG_ANDROID_POWER) && defined(CONFIG_RESUME_IN_WORKQUEUE)
-+	#warning "You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
-+	#undef CONFIG_RESUME_IN_WORKQUEUE
-+#endif
-+*/
-+
-+/* About USB VENDOR REQ */
-+#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
-+	#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically"
-+	#define CONFIG_USB_VENDOR_REQ_MUTEX
-+#endif
-+#if defined(CONFIG_VENDOR_REQ_RETRY) &&  !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
-+	#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically"
-+	#define CONFIG_USB_VENDOR_REQ_MUTEX
-+#endif
-+
-+#ifdef CONFIG_WIFI_MONITOR
-+	/*	#define CONFIG_MONITOR_MODE_XMIT	*/
-+#endif
-+
-+#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
-+	#ifndef CONFIG_WIFI_MONITOR
-+		#define CONFIG_WIFI_MONITOR
-+	#endif
-+	#ifdef CONFIG_POWER_SAVING
-+		#undef CONFIG_POWER_SAVING
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
-+	#ifdef CONFIG_POWER_SAVING
-+		#undef CONFIG_POWER_SAVING
-+	#endif
-+	#ifdef CONFIG_BEAMFORMING
-+		#undef CONFIG_BEAMFORMING
-+	#endif
-+#endif
-+
-+#ifndef CONFIG_RTW_DATA_BMC_TO_UC
-+#define CONFIG_RTW_DATA_BMC_TO_UC 0
-+#endif
-+
-+#ifdef CONFIG_AP_MODE
-+	#define CONFIG_LIMITED_AP_NUM 1
-+
-+	#ifndef CONFIG_RTW_AP_DATA_BMC_TO_UC
-+	#define CONFIG_RTW_AP_DATA_BMC_TO_UC 1
-+	#endif
-+	#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+	#undef CONFIG_RTW_DATA_BMC_TO_UC
-+	#define CONFIG_RTW_DATA_BMC_TO_UC 1
-+	#endif
-+	#ifndef CONFIG_RTW_AP_SRC_B2U_FLAGS
-+	#define CONFIG_RTW_AP_SRC_B2U_FLAGS 0x8 /* see RTW_AP_B2U_XXX */
-+	#endif
-+	#ifndef CONFIG_RTW_AP_FWD_B2U_FLAGS
-+	#define CONFIG_RTW_AP_FWD_B2U_FLAGS 0x8 /* see RTW_AP_B2U_XXX */
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+	#ifndef CONFIG_AP_MODE
-+	#error "enable CONFIG_RTW_MULTI_AP without CONFIG_AP_MODE"
-+	#endif
-+	#ifndef CONFIG_RTW_WDS
-+	#define CONFIG_RTW_WDS
-+	#endif
-+	#ifndef CONFIG_RTW_UNASOC_STA_MODE_OF_STYPE
-+	#define CONFIG_RTW_UNASOC_STA_MODE_OF_STYPE {2, 1} /* BMC:2 for all, NMY_UC:1 for interested target */
-+	#endif
-+	#ifndef CONFIG_RTW_NLRTW
-+	#define CONFIG_RTW_NLRTW
-+	#endif
-+	#ifndef CONFIG_RTW_WNM
-+	#define CONFIG_RTW_WNM
-+	#endif
-+	#ifndef CONFIG_RTW_80211K
-+	#define CONFIG_RTW_80211K
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTW_MESH
-+	#ifndef CONFIG_RTW_MESH_ACNODE_PREVENT
-+	#define CONFIG_RTW_MESH_ACNODE_PREVENT 1
-+	#endif
-+
-+	#ifndef CONFIG_RTW_MESH_OFFCH_CAND
-+	#define CONFIG_RTW_MESH_OFFCH_CAND 1
-+	#endif
-+
-+	#ifndef CONFIG_RTW_MESH_PEER_BLACKLIST
-+	#define CONFIG_RTW_MESH_PEER_BLACKLIST 1
-+	#endif
-+
-+	#ifndef CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	#define CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST 1
-+	#endif
-+	#ifndef CONFIG_RTW_MESH_CTO_MGATE_CARRIER
-+	#define CONFIG_RTW_MESH_CTO_MGATE_CARRIER CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	#endif
-+
-+	#ifndef CONFIG_RTW_MPM_TX_IES_SYNC_BSS
-+	#define CONFIG_RTW_MPM_TX_IES_SYNC_BSS 1
-+	#endif
-+	#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS
-+		#ifndef CONFIG_RTW_MESH_AEK
-+		#define CONFIG_RTW_MESH_AEK
-+		#endif
-+	#endif
-+
-+	#ifndef CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+	#define CONFIG_RTW_MESH_DATA_BMC_TO_UC 1
-+	#endif
-+	#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+	#undef CONFIG_RTW_DATA_BMC_TO_UC
-+	#define CONFIG_RTW_DATA_BMC_TO_UC 1
-+	#endif
-+	#ifndef CONFIG_RTW_MSRC_B2U_FLAGS
-+	#define CONFIG_RTW_MSRC_B2U_FLAGS 0x0 /* see RTW_MESH_B2U_XXX */
-+	#endif
-+	#ifndef CONFIG_RTW_MFWD_B2U_FLAGS
-+	#define CONFIG_RTW_MFWD_B2U_FLAGS 0x2 /* see RTW_MESH_B2U_XXX */
-+	#endif
-+#endif
-+
-+#if !defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE)
-+#define CONFIG_SCAN_BACKOP
-+#endif
-+
-+#define RTW_SCAN_SPARSE_MIRACAST 1
-+#define RTW_SCAN_SPARSE_BG 0
-+#define RTW_SCAN_SPARSE_ROAMING_ACTIVE 1
-+
-+#ifndef CONFIG_TX_AC_LIFETIME
-+#define CONFIG_TX_AC_LIFETIME 1
-+#endif
-+#ifndef CONFIG_TX_ACLT_FLAGS
-+#define CONFIG_TX_ACLT_FLAGS 0x00
-+#endif
-+#ifndef CONFIG_TX_ACLT_CONF_DEFAULT
-+#define CONFIG_TX_ACLT_CONF_DEFAULT {0x0, 1024 * 1000, 1024 * 1000}
-+#endif
-+#ifndef CONFIG_TX_ACLT_CONF_AP_M2U
-+#define CONFIG_TX_ACLT_CONF_AP_M2U {0xF, 256 * 1000, 256 * 1000}
-+#endif
-+#ifndef CONFIG_TX_ACLT_CONF_MESH
-+#define CONFIG_TX_ACLT_CONF_MESH {0xF, 256 * 1000, 256 * 1000}
-+#endif
-+
-+#ifndef CONFIG_RTW_HIQ_FILTER
-+	#define CONFIG_RTW_HIQ_FILTER 1
-+#endif
-+
-+#ifndef CONFIG_RTW_ADAPTIVITY_EN
-+	#define CONFIG_RTW_ADAPTIVITY_EN 0
-+#endif
-+
-+#ifndef CONFIG_RTW_ADAPTIVITY_MODE
-+	#define CONFIG_RTW_ADAPTIVITY_MODE 0
-+#endif
-+
-+#ifndef CONFIG_RTW_ADAPTIVITY_TH_L2H_INI
-+	#define CONFIG_RTW_ADAPTIVITY_TH_L2H_INI 0
-+#endif
-+
-+#ifndef CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF
-+	#define CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF 0
-+#endif
-+
-+#ifndef CONFIG_RTW_EXCL_CHS
-+	#define CONFIG_RTW_EXCL_CHS {0}
-+#endif
-+
-+#ifndef CONFIG_IEEE80211_BAND_5GHZ
-+	#if defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8821C) \
-+		|| defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) \
-+		|| defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8814B) || defined(CONFIG_RTL8723F)
-+	#define CONFIG_IEEE80211_BAND_5GHZ 1
-+	#else
-+	#define CONFIG_IEEE80211_BAND_5GHZ 0
-+	#endif
-+#endif
-+
-+#ifndef CONFIG_DFS
-+#define CONFIG_DFS 1
-+#endif
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS && defined(CONFIG_AP_MODE)
-+	#if !defined(CONFIG_DFS_SLAVE_WITH_RADAR_DETECT)
-+	#define CONFIG_DFS_SLAVE_WITH_RADAR_DETECT 0
-+	#endif
-+	#if !defined(CONFIG_DFS_MASTER) || CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
-+	#define CONFIG_DFS_MASTER
-+	#endif
-+	#if defined(CONFIG_DFS_MASTER) && !defined(CONFIG_RTW_DFS_REGION_DOMAIN)
-+	#define CONFIG_RTW_DFS_REGION_DOMAIN 0
-+	#endif
-+#else
-+	#undef CONFIG_DFS_MASTER
-+	#undef CONFIG_RTW_DFS_REGION_DOMAIN
-+	#define CONFIG_RTW_DFS_REGION_DOMAIN 0
-+	#undef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
-+	#define CONFIG_DFS_SLAVE_WITH_RADAR_DETECT 0
-+#endif
-+
-+#ifndef CONFIG_TXPWR_BY_RATE_EN
-+#define CONFIG_TXPWR_BY_RATE_EN 2 /* by efuse */
-+#endif
-+#ifndef CONFIG_TXPWR_LIMIT_EN
-+#define CONFIG_TXPWR_LIMIT_EN 2 /* by efuse */
-+#endif
-+
-+#ifndef CONFIG_RTW_CHPLAN
-+#define CONFIG_RTW_CHPLAN 0xFF /* RTW_CHPLAN_UNSPECIFIED */
-+#endif
-+
-+/* compatible with old fashion configuration */
-+#if defined(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY)
-+	#undef CONFIG_TXPWR_BY_RATE_EN
-+	#undef CONFIG_TXPWR_LIMIT_EN
-+	#define CONFIG_TXPWR_BY_RATE_EN 1
-+	#define CONFIG_TXPWR_LIMIT_EN 1
-+#elif defined(CONFIG_CALIBRATE_TX_POWER_TO_MAX)
-+	#undef CONFIG_TXPWR_BY_RATE_EN
-+	#undef CONFIG_TXPWR_LIMIT_EN
-+	#define CONFIG_TXPWR_BY_RATE_EN 1
-+	#define CONFIG_TXPWR_LIMIT_EN 0
-+#endif
-+
-+#ifndef RTW_DEF_MODULE_REGULATORY_CERT
-+	#define RTW_DEF_MODULE_REGULATORY_CERT 0
-+#endif
-+
-+#if RTW_DEF_MODULE_REGULATORY_CERT
-+	#ifdef CONFIG_REGD_SRC_FROM_OS
-+	#error "CONFIG_REGD_SRC_FROM_OS is not supported when enable RTW_DEF_MODULE_REGULATORY_CERT"
-+	#endif
-+	/* force enable TX power by rate and TX power limit */
-+	#undef CONFIG_TXPWR_BY_RATE_EN
-+	#undef CONFIG_TXPWR_LIMIT_EN
-+	#define CONFIG_TXPWR_BY_RATE_EN 1
-+	#define CONFIG_TXPWR_LIMIT_EN 1
-+#endif
-+
-+#if !CONFIG_TXPWR_LIMIT && CONFIG_TXPWR_LIMIT_EN
-+	#undef CONFIG_TXPWR_LIMIT
-+	#define CONFIG_TXPWR_LIMIT 1
-+#endif
-+
-+#ifndef CONFIG_RTW_REGD_SRC
-+#define CONFIG_RTW_REGD_SRC 1 /* 0:RTK_PRIV, 1:OS */
-+#endif
-+
-+#define CONFIG_IOCTL_WEXT
-+
-+#ifdef CONFIG_RTW_IPCAM_APPLICATION
-+	#undef CONFIG_TXPWR_BY_RATE_EN
-+	#define CONFIG_TXPWR_BY_RATE_EN 1
-+	#define CONFIG_RTW_CUSTOMIZE_BEEDCA		0x0000431C
-+	#define CONFIG_RTW_CUSTOMIZE_BWMODE		0x00
-+	#define CONFIG_RTW_CUSTOMIZE_RLSTA		0x30
-+	#define CONFIG_CHECK_SPECIFIC_IE_CONTENT
-+	#ifdef CONFIG_CUSTOMER_EZVIZ_CHIME2
-+		#undef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-+	#endif
-+#if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B)
-+	#define CONFIG_RTW_TX_NPATH_EN		/*	mutually incompatible with STBC_TX & Beamformer	*/
-+#endif
-+#endif
-+/* #define CONFIG_RTW_TOKEN_BASED_XMIT */
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	#define NR_TBTX_SLOT			4
-+	#define NR_MAXSTA_INSLOT		5
-+	#define TBTX_TX_DURATION		30
-+	
-+	#define MAX_TXPAUSE_DURATION	(TBTX_TX_DURATION*NR_TBTX_SLOT)
-+#endif
-+
-+/*#define CONFIG_EXTEND_LOWRATE_TXOP			*/
-+
-+#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS
-+	#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS {0xFF, 0xFF, 0xFF, 0xFF}
-+#endif
-+#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS
-+	#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS {0xFF, 0xFF, 0xFF, 0xFF}
-+#endif
-+#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS
-+	#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS {0xFF, 0xFF, 0xFF, 0xFF}
-+#endif
-+#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS
-+	#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS {0xFF, 0xFF, 0xFF, 0xFF}
-+#endif
-+
-+#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_A
-+	#define CONFIG_RTW_TARGET_TX_PWR_2G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
-+#endif
-+
-+#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_B
-+	#define CONFIG_RTW_TARGET_TX_PWR_2G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
-+#endif
-+
-+#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_C
-+	#define CONFIG_RTW_TARGET_TX_PWR_2G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
-+#endif
-+
-+#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_D
-+	#define CONFIG_RTW_TARGET_TX_PWR_2G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
-+#endif
-+
-+#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_A
-+	#define CONFIG_RTW_TARGET_TX_PWR_5G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1}
-+#endif
-+
-+#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_B
-+	#define CONFIG_RTW_TARGET_TX_PWR_5G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1}
-+#endif
-+
-+#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_C
-+	#define CONFIG_RTW_TARGET_TX_PWR_5G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1}
-+#endif
-+
-+#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_D
-+	#define CONFIG_RTW_TARGET_TX_PWR_5G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1}
-+#endif
-+
-+#ifndef CONFIG_RTW_ANTENNA_GAIN
-+#define CONFIG_RTW_ANTENNA_GAIN 0x7FFF /* == UNSPECIFIED_MBM */
-+#endif
-+
-+#ifndef CONFIG_RTW_AMPLIFIER_TYPE_2G
-+	#define CONFIG_RTW_AMPLIFIER_TYPE_2G 0
-+#endif
-+
-+#ifndef CONFIG_RTW_AMPLIFIER_TYPE_5G
-+	#define CONFIG_RTW_AMPLIFIER_TYPE_5G 0
-+#endif
-+
-+#ifndef CONFIG_RTW_RFE_TYPE
-+	#define CONFIG_RTW_RFE_TYPE 64
-+#endif
-+
-+#ifndef CONFIG_RTW_GLNA_TYPE
-+	#define CONFIG_RTW_GLNA_TYPE 0
-+#endif
-+
-+#ifndef CONFIG_RTW_PLL_REF_CLK_SEL
-+	#define CONFIG_RTW_PLL_REF_CLK_SEL 0x0F
-+#endif
-+
-+#ifndef CONFIG_IFACE_NUMBER
-+	#ifdef CONFIG_CONCURRENT_MODE
-+		#define CONFIG_IFACE_NUMBER	2
-+	#else
-+		#define CONFIG_IFACE_NUMBER	1
-+	#endif
-+#endif
-+
-+#ifndef CONFIG_CONCURRENT_MODE
-+	#if (CONFIG_IFACE_NUMBER > 1)
-+		#error "CONFIG_IFACE_NUMBER over 1,but CONFIG_CONCURRENT_MODE not defined"
-+	#endif
-+#endif
-+
-+#if (CONFIG_IFACE_NUMBER == 0)
-+	#error "CONFIG_IFACE_NUMBER cound not be 0 !!"
-+#endif
-+
-+#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8188F) || \
-+defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8192F) || \
-+defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8710B) || \
-+defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D)
-+#define CONFIG_HWMPCAP_GEN1
-+#elif defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || \
-+defined(CONFIG_RTL8723F) /*|| defined(CONFIG_RTL8814A)*/
-+#define CONFIG_HWMPCAP_GEN2
-+#elif defined(CONFIG_RTL8814B) /*Address CAM - 128*/
-+#define CONFIG_HWMPCAP_GEN3
-+#endif
-+
-+#if defined(CONFIG_HWMPCAP_GEN1) && (CONFIG_IFACE_NUMBER > 2) 
-+	#ifdef CONFIG_POWER_SAVING
-+	/*#warning "Disable PS when CONFIG_IFACE_NUMBER > 2"*/
-+	#undef CONFIG_POWER_SAVING
-+	#endif
-+
-+	#ifdef CONFIG_WOWLAN
-+	#error "This IC can't support MI and WoWLan at the same time"
-+	#endif
-+#endif
-+
-+#if defined(CONFIG_HWMPCAP_GEN1) && (CONFIG_IFACE_NUMBER > 3)
-+        #error " This IC can't support over 3 interfaces !!"
-+#endif
-+
-+#if (CONFIG_IFACE_NUMBER > 4)
-+	#error "Not support over 4 interfaces yet !!"
-+#endif
-+
-+#if (CONFIG_IFACE_NUMBER > 8)	/*IFACE_ID_MAX*/
-+	#error "HW count not support over 8 interfaces !!"
-+#endif
-+
-+#if (CONFIG_IFACE_NUMBER > 2)
-+	#ifndef CONFIG_HWMPCAP_GEN3
-+		#define CONFIG_MI_WITH_MBSSID_CAM
-+	#endif
-+
-+	#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+		#define CONFIG_MBSSID_CAM
-+		#if defined(CONFIG_RUNTIME_PORT_SWITCH)
-+			#undef CONFIG_RUNTIME_PORT_SWITCH
-+		#endif
-+	#endif
-+
-+	#ifdef CONFIG_AP_MODE
-+		#undef CONFIG_LIMITED_AP_NUM
-+		#define CONFIG_LIMITED_AP_NUM	2
-+
-+		#define CONFIG_SUPPORT_MULTI_BCN
-+
-+		#define CONFIG_SWTIMER_BASED_TXBCN
-+
-+		#ifdef CONFIG_HWMPCAP_GEN2 /*CONFIG_RTL8822B/CONFIG_RTL8821C/CONFIG_RTL8822C*/
-+		#define CONFIG_FW_HANDLE_TXBCN
-+
-+		#ifdef CONFIG_FW_HANDLE_TXBCN
-+			#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+				#undef CONFIG_SWTIMER_BASED_TXBCN
-+			#endif
-+			#undef CONFIG_LIMITED_AP_NUM
-+			#define CONFIG_LIMITED_AP_NUM	4
-+		#endif
-+
-+		#endif /*CONFIG_HWMPCAP_GEN2*/
-+
-+		#ifdef CONFIG_HWMPCAP_GEN3
-+			#define CONFIG_PORT_BASED_TXBCN
-+			#undef CONFIG_SUPPORT_MULTI_BCN
-+			#undef CONFIG_SWTIMER_BASED_TXBCN
-+			#undef CONFIG_LIMITED_AP_NUM
-+			#define CONFIG_LIMITED_AP_NUM	4
-+			#ifdef CONFIG_PCI_HCI
-+			#define CONFIG_PORT_BASED_HIQ	/* 8814BU doesn't support */
-+			#endif
-+		#endif
-+	#endif /*CONFIG_AP_MODE*/
-+
-+	#ifdef CONFIG_HWMPCAP_GEN2 /*CONFIG_RTL8822B/CONFIG_RTL8821C/CONFIG_RTL8822C*/
-+	#define CONFIG_CLIENT_PORT_CFG
-+	#define CONFIG_NEW_NETDEV_HDL
-+	#endif/*CONFIG_HWMPCAP_GEN2*/
-+#endif/*(CONFIG_IFACE_NUMBER > 2)*/
-+
-+#if defined(CONFIG_MI_UNIQUE_MACADDR_BIT)
-+	#if !defined(CONFIG_MI_WITH_MBSSID_CAM)
-+		#error "CONFIG_MI_UNIQUE_MACADDR_BIT should not be used without multiple interface !!"
-+	#endif
-+	#if (CONFIG_MI_UNIQUE_MACADDR_BIT < 24) || ( 47 < CONFIG_MI_UNIQUE_MACADDR_BIT)
-+		#error "CONFIG_MI_UNIQUE_MACADDR_BIT should be the bit in NIC specific mac address(BIT[24:47] !!"
-+	#endif
-+#endif
-+
-+#define MACID_NUM_SW_LIMIT 32
-+#define SEC_CAM_ENT_NUM_SW_LIMIT 32
-+
-+#ifdef SEC_DEFAULT_KEY_SEARCH
-+	#if (CONFIG_IFACE_NUMBER >= 2)
-+		#error "Default Key Search only work with only one interface case!"
-+	#endif
-+#endif
-+
-+#if defined(CONFIG_WOWLAN) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B))
-+	#define CONFIG_WOW_PATTERN_HW_CAM
-+#endif
-+
-+#ifndef CONFIG_TSF_UPDATE_PAUSE_FACTOR
-+#define CONFIG_TSF_UPDATE_PAUSE_FACTOR 200
-+#endif
-+
-+#ifndef CONFIG_TSF_UPDATE_RESTORE_FACTOR
-+#define CONFIG_TSF_UPDATE_RESTORE_FACTOR 5
-+#endif
-+
-+/*
-+	Mark CONFIG_DEAUTH_BEFORE_CONNECT by Arvin 2015/07/20
-+	If the failure of Wi-Fi connection is due to some irregular disconnection behavior (like unplug dongle,
-+	power down etc.) in last time, we can unmark this flag to avoid some unpredictable response from AP.
-+*/
-+/*#define CONFIG_DEAUTH_BEFORE_CONNECT */
-+
-+/*#define CONFIG_WEXT_DONT_JOIN_BYSSID	*/
-+/* #include <rtl871x_byteorder.h> */
-+
-+
-+/*#define CONFIG_DOSCAN_IN_BUSYTRAFFIC	*/
-+/*#define CONFIG_PHDYM_FW_FIXRATE		*/	/*	Another way to fix tx rate	*/
-+
-+/*Don't release SDIO irq in suspend/resume procedure*/
-+#define CONFIG_RTW_SDIO_KEEP_IRQ	0
-+
-+/*
-+ * Add by Lucas@2016/02/15
-+ * For RX Aggregation
-+ */
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_RX_AGGREGATION)
-+	#define RTW_RX_AGGREGATION
-+#endif /* CONFIG_SDIO_HCI || CONFIG_USB_RX_AGGREGATION */
-+
-+#ifdef CONFIG_RTW_HOSTAPD_ACS
-+	#ifndef CONFIG_RTW_ACS
-+		#define CONFIG_RTW_ACS
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTW_80211K
-+	#ifndef CONFIG_RTW_ACS
-+		#define CONFIG_RTW_ACS
-+	#endif
-+#endif /*CONFIG_RTW_80211K*/
-+
-+#ifdef DBG_CONFIG_ERROR_RESET
-+#ifndef CONFIG_IPS
-+#define CONFIG_IPS
-+#endif
-+#endif
-+
-+/* IPS */
-+#ifndef RTW_IPS_MODE
-+	#if defined(CONFIG_IPS)
-+		#define RTW_IPS_MODE 1
-+	#else
-+		#define RTW_IPS_MODE 0
-+	#endif
-+#endif /* !RTW_IPS_MODE */
-+
-+#if (RTW_IPS_MODE > 1 || RTW_IPS_MODE < 0)
-+	#error "The CONFIG_IPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\n"
-+#endif
-+
-+/* LPS */
-+#ifndef RTW_LPS_MODE
-+	#if defined(CONFIG_LPS_PG) || defined(CONFIG_LPS_PG_DDMA)
-+		#define RTW_LPS_MODE 3
-+	#elif defined(CONFIG_LPS_LCLK)
-+		#define RTW_LPS_MODE 2
-+	#elif defined(CONFIG_LPS)
-+		#define RTW_LPS_MODE 1
-+	#else
-+		#define RTW_LPS_MODE 0
-+	#endif 
-+#endif /* !RTW_LPS_MODE */
-+
-+#if (RTW_LPS_MODE > 3 || RTW_LPS_MODE < 0)
-+	#error "The CONFIG_LPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\n"
-+#endif
-+
-+#ifndef RTW_LPS_1T1R
-+#define RTW_LPS_1T1R 0
-+#endif
-+
-+#ifndef RTW_WOW_LPS_1T1R
-+#define RTW_WOW_LPS_1T1R 0
-+#endif
-+
-+/* WOW LPS */
-+#ifndef RTW_WOW_LPS_MODE
-+	#if defined(CONFIG_LPS_PG) || defined(CONFIG_LPS_PG_DDMA)
-+		#define RTW_WOW_LPS_MODE 3
-+	#elif defined(CONFIG_LPS_LCLK)
-+		#define RTW_WOW_LPS_MODE 2
-+	#elif defined(CONFIG_LPS)
-+		#define RTW_WOW_LPS_MODE 1
-+	#else
-+		#define RTW_WOW_LPS_MODE 0
-+	#endif
-+#endif /* !RTW_WOW_LPS_MODE */
-+
-+#if (RTW_WOW_LPS_MODE > 3 || RTW_WOW_LPS_MODE < 0)
-+	#error "The RTW_WOW_LPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\n"
-+#endif
-+
-+#ifdef RTW_REDUCE_SCAN_SWITCH_CH_TIME
-+#ifndef CONFIG_RTL8822B
-+	#error "Only 8822B support RTW_REDUCE_SCAN_SWITCH_CH_TIME"
-+#endif
-+	#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
-+		#define RTW_CHANNEL_SWITCH_OFFLOAD
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+#ifndef CONFIG_WOWLAN
-+	#error "WAR OFFLOAD is part of WOWLAN"
-+#endif
-+#endif
-+
-+#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
-+#ifndef CONFIG_WOWLAN
-+	#error "mDNS OFFLOAD is part of WOWLAN"
-+#endif
-+#ifndef CONFIG_WAR_OFFLOAD
-+	#define CONFIG_WAR_OFFLOAD
-+#endif
-+#endif
-+
-+#define CONFIG_RTW_TPT_MODE 
-+
-+#ifdef CONFIG_PCI_BCN_POLLING
-+#define CONFIG_BCN_ICF
-+#endif 
-+
-+#ifndef CONFIG_RTW_MGMT_QUEUE
-+	#define CONFIG_RTW_MGMT_QUEUE
-+#endif
-+
-+#ifndef CONFIG_PCI_MSI
-+#define CONFIG_RTW_PCI_MSI_DISABLE
-+#endif
-+
-+#if defined(CONFIG_PCI_DYNAMIC_ASPM_L1_LATENCY) ||	\
-+    defined(CONFIG_PCI_DYNAMIC_ASPM_LINK_CTRL)
-+#define CONFIG_PCI_DYNAMIC_ASPM
-+#endif
-+
-+#if 0
-+/* Debug related compiler flags */
-+#define DBG_THREAD_PID	/* Add thread pid to debug message prefix */
-+#define DBG_CPU_INFO	/* Add CPU info to debug message prefix */
-+#endif
-+
-+#endif /* __DRV_CONF_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/drv_types.h b/drivers/staging/rtl8723cs/include/drv_types.h
-new file mode 100644
-index 000000000000..7422236324e2
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/drv_types.h
-@@ -0,0 +1,2036 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*-------------------------------------------------------------------------------
-+
-+	For type defines and data structure defines
-+
-+--------------------------------------------------------------------------------*/
-+
-+
-+#ifndef __DRV_TYPES_H__
-+#define __DRV_TYPES_H__
-+
-+#include <drv_conf.h>
-+#include <basic_types.h>
-+#include <osdep_service.h>
-+#include <rtw_byteorder.h>
-+#include <wlan_bssdef.h>
-+#include <wifi.h>
-+#include <ieee80211.h>
-+#ifdef CONFIG_ARP_KEEP_ALIVE
-+	#include <net/neighbour.h>
-+	#include <net/arp.h>
-+#endif
-+
-+#ifdef PLATFORM_OS_XP
-+	#include <drv_types_xp.h>
-+#endif
-+
-+#ifdef PLATFORM_OS_CE
-+	#include <drv_types_ce.h>
-+#endif
-+
-+#ifdef PLATFORM_LINUX
-+	#include <drv_types_linux.h>
-+#endif
-+
-+enum _NIC_VERSION {
-+
-+	RTL8711_NIC,
-+	RTL8712_NIC,
-+	RTL8713_NIC,
-+	RTL8716_NIC
-+
-+};
-+
-+typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER;
-+
-+#include <rtw_debug.h>
-+#include <cmn_info/rtw_sta_info.h>
-+#include <rtw_rf.h>
-+#include "../core/rtw_chplan.h"
-+
-+#ifdef CONFIG_80211N_HT
-+	#include <rtw_ht.h>
-+#endif
-+
-+#ifdef CONFIG_80211AC_VHT
-+	#include <rtw_vht.h>
-+#endif
-+
-+#include <rtw_cmd.h>
-+#include <cmd_osdep.h>
-+#include <rtw_security.h>
-+#include <rtw_xmit.h>
-+#include <xmit_osdep.h>
-+#include <rtw_recv.h>
-+#include <rtw_rm.h>
-+
-+#ifdef CONFIG_BEAMFORMING
-+	#include <rtw_beamforming.h>
-+#endif
-+
-+#include <recv_osdep.h>
-+#include <rtw_efuse.h>
-+#include <rtw_sreset.h>
-+#include <hal_intf.h>
-+#include <hal_com.h>
-+#include<hal_com_h2c.h>
-+#include <hal_com_led.h>
-+#include "../hal/hal_dm.h"
-+#include <rtw_qos.h>
-+#include <rtw_pwrctrl.h>
-+#ifdef CONFIG_RTW_80211R
-+#include <rtw_ft.h>
-+#endif
-+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
-+#include <rtw_wnm.h>
-+#endif
-+#ifdef CONFIG_RTW_MBO
-+#include <rtw_mbo.h>
-+#endif
-+#include <rtw_mlme.h>
-+#include <mlme_osdep.h>
-+#include <rtw_io.h>
-+#include <rtw_ioctl.h>
-+#include <rtw_ioctl_set.h>
-+#include <rtw_ioctl_query.h>
-+#include <osdep_intf.h>
-+#include <rtw_eeprom.h>
-+#include <sta_info.h>
-+#include <rtw_event.h>
-+#include <rtw_mlme_ext.h>
-+#include <rtw_mi.h>
-+#include <rtw_ap.h>
-+#ifdef CONFIG_RTW_WDS
-+#include "../core/wds/rtw_wds.h"
-+#endif
-+#ifdef CONFIG_RTW_MESH
-+#include "../core/mesh/rtw_mesh.h"
-+#endif
-+#ifdef CONFIG_WIFI_MONITOR
-+#include "../core/monitor/rtw_radiotap.h"
-+#endif
-+#include <rtw_efuse.h>
-+#include <rtw_version.h>
-+#include <rtw_odm.h>
-+
-+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
-+	#include <rtw_mem.h>
-+#endif
-+
-+#include <rtw_p2p.h>
-+
-+#ifdef CONFIG_TDLS
-+	#include <rtw_tdls.h>
-+#endif /* CONFIG_TDLS */
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	#include <rtw_wapi.h>
-+#endif /* CONFIG_WAPI_SUPPORT */
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	#include <rtw_mp.h>
-+#endif /* CONFIG_MP_INCLUDED */
-+
-+#ifdef CONFIG_BR_EXT
-+	#include <rtw_br_ext.h>
-+#endif /* CONFIG_BR_EXT */
-+
-+#ifdef CONFIG_IOL
-+	#include <rtw_iol.h>
-+#endif /* CONFIG_IOL */
-+
-+#include <ip.h>
-+#include <if_ether.h>
-+#include <ethernet.h>
-+#include <circ_buf.h>
-+
-+#include <rtw_android.h>
-+
-+#include <rtw_btcoex_wifionly.h>
-+#include <rtw_btcoex.h>
-+
-+#ifdef CONFIG_MCC_MODE
-+	#include <rtw_mcc.h>
-+#endif /*CONFIG_MCC_MODE */
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	#include <rtw_rson.h>
-+#endif /*CONFIG_RTW_REPEATER_SON */
-+
-+#include <rtw_roch.h>
-+
-+#define SPEC_DEV_ID_NONE BIT(0)
-+#define SPEC_DEV_ID_DISABLE_HT BIT(1)
-+#define SPEC_DEV_ID_ENABLE_PS BIT(2)
-+#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3)
-+#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4)
-+#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5)
-+
-+struct specific_device_id {
-+
-+	u32		flags;
-+
-+	u16		idVendor;
-+	u16		idProduct;
-+
-+};
-+
-+struct registry_priv {
-+	u8	chip_version;
-+	u8	rfintfs;
-+	u8	lbkmode;
-+	u8	hci;
-+	NDIS_802_11_SSID	ssid;
-+	u8	network_mode;	/* infra, ad-hoc, auto */
-+	u8	channel;/* ad-hoc support requirement */
-+	u8	wireless_mode;/* A, B, G, auto */
-+	u8	scan_mode;/* active, passive */
-+	u8	radio_enable;
-+	u8	preamble;/* long, short, auto */
-+	u8	vrtl_carrier_sense;/* Enable, Disable, Auto */
-+	u8	vcs_type;/* RTS/CTS, CTS-to-self */
-+	u16	rts_thresh;
-+	u16  frag_thresh;
-+	u8	adhoc_tx_pwr;
-+	u8	soft_ap;
-+	u8	power_mgnt;
-+	u8	ips_mode;
-+	u8	lps_level;
-+#ifdef CONFIG_LPS_1T1R
-+	u8	lps_1t1r;
-+#endif
-+	u8	lps_chk_by_tp;
-+#ifdef CONFIG_WOWLAN
-+	u8	wow_power_mgnt;
-+	u8	wow_lps_level;
-+	#ifdef CONFIG_LPS_1T1R
-+	u8	wow_lps_1t1r;
-+	#endif
-+#endif /* CONFIG_WOWLAN */
-+	u8	smart_ps;
-+#ifdef CONFIG_WMMPS_STA
-+	u8	wmm_smart_ps;
-+#endif /* CONFIG_WMMPS_STA */
-+	u8   usb_rxagg_mode;
-+	u8	dynamic_agg_enable;
-+	u8	long_retry_lmt;
-+	u8	short_retry_lmt;
-+	u16	busy_thresh;
-+	u16	max_bss_cnt;
-+	u8	ack_policy;
-+	u8	mp_mode;
-+#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
-+	u8 mp_customer_str;
-+#endif
-+	u8  mp_dm;
-+	u8	software_encrypt;
-+	u8	software_decrypt;
-+#ifdef CONFIG_TX_EARLY_MODE
-+	u8   early_mode;
-+#endif
-+#ifdef CONFIG_NARROWBAND_SUPPORTING
-+	u8	rtw_nb_config;
-+#endif
-+	u8	acm_method;
-+	/* WMM */
-+	u8	wmm_enable;
-+#ifdef CONFIG_WMMPS_STA
-+	/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */
-+	u8	uapsd_max_sp_len;
-+	/* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */
-+	u8	uapsd_ac_enable;
-+#endif /* CONFIG_WMMPS_STA */
-+
-+	WLAN_BSSID_EX    dev_network;
-+
-+#if CONFIG_TX_AC_LIFETIME
-+	u8 tx_aclt_flags;
-+	struct tx_aclt_conf_t tx_aclt_confs[TX_ACLT_CONF_NUM];
-+#endif
-+
-+	u8 tx_bw_mode;
-+#ifdef CONFIG_AP_MODE
-+	u8 bmc_tx_rate;
-+	#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+	u8 ap_src_b2u_flags;
-+	u8 ap_fwd_b2u_flags;
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTW_MESH
-+	#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+	u8 msrc_b2u_flags;
-+	u8 mfwd_b2u_flags;
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_80211N_HT
-+	u8	ht_enable;
-+	/* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz */
-+	/* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 */
-+	/* 0x21 means enable 2.4G 40MHz & 5G 80MHz */
-+	u8	bw_mode;
-+	u8	ampdu_enable;/* for tx */
-+	u8	rx_stbc;
-+	u8	rx_ampdu_amsdu;/* Rx A-MPDU Supports A-MSDU is permitted */
-+	u8	tx_ampdu_amsdu;/* Tx A-MPDU Supports A-MSDU is permitted */
-+	u8	tx_quick_addba_req;
-+	u8 rx_ampdu_sz_limit_by_nss_bw[4][4]; /* 1~4SS, BW20~BW160 */
-+	/* Short GI support Bit Map */
-+	/* BIT0 - 20MHz, 1: support, 0: non-support */
-+	/* BIT1 - 40MHz, 1: support, 0: non-support */
-+	/* BIT2 - 80MHz, 1: support, 0: non-support */
-+	/* BIT3 - 160MHz, 1: support, 0: non-support */
-+	u8	short_gi;
-+	/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */
-+	u8	ldpc_cap;
-+	/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */
-+	u8	stbc_cap;
-+	#if defined(CONFIG_RTW_TX_NPATH_EN)
-+	u8	tx_npath;
-+	#endif
-+	#if defined(CONFIG_RTW_PATH_DIV)
-+	u8 path_div;
-+	#endif
-+	/*
-+	 * BIT0: Enable VHT SU Beamformer
-+	 * BIT1: Enable VHT SU Beamformee
-+	 * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer
-+	 * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee
-+	 * BIT4: Enable HT Beamformer
-+	 * BIT5: Enable HT Beamformee
-+	 */
-+	u8	beamform_cap;
-+	u8	beamformer_rf_num;
-+	u8	beamformee_rf_num;
-+#endif /* CONFIG_80211N_HT */
-+
-+#ifdef CONFIG_80211AC_VHT
-+	u8	vht_enable; /* 0:disable, 1:enable, 2:auto */
-+	u8	vht_24g_enable; /* 0:disable, 1:enable */
-+	u8	ampdu_factor;
-+	u8 vht_rx_mcs_map[2];
-+#endif /* CONFIG_80211AC_VHT */
-+
-+	u8	low_power ;
-+
-+	u8	wifi_spec;/* !turbo_mode */
-+
-+	u8 trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp, 0: not specified */
-+	u8 tx_path_lmt; /* limit of TX path number, 0: not specified */
-+	u8 rx_path_lmt; /* limit of TX path number, 0: not specified */
-+	u8 tx_nss;
-+	u8 rx_nss;
-+
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+	enum regd_src_t regd_src;
-+#endif
-+	char alpha2[2];
-+	u8	channel_plan;
-+	u8	excl_chs[MAX_CHANNEL_NUM];
-+	u8	full_ch_in_p2p_handshake; /* 0: reply only softap channel, 1: reply full channel list*/
-+
-+#ifdef CONFIG_BT_COEXIST
-+	u8	btcoex;
-+	u8	bt_iso;
-+	u8	bt_sco;
-+	u8	bt_ampdu;
-+	u8	ant_num;
-+	u8	single_ant_path;
-+#endif
-+	BOOLEAN	bAcceptAddbaReq;
-+
-+	u8	antdiv_cfg;
-+	u8	antdiv_type;
-+	u8	drv_ant_band_switch;
-+
-+	u8	switch_usb_mode;
-+
-+	u8	usbss_enable;/* 0:disable,1:enable */
-+	u8	hwpdn_mode;/* 0:disable,1:enable,2:decide by EFUSE config */
-+	u8	hwpwrp_detect;/* 0:disable,1:enable */
-+
-+	u8	hw_wps_pbc;/* 0:disable,1:enable */
-+
-+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
-+	char	adaptor_info_caching_file_path[PATH_LENGTH_MAX];
-+#endif
-+
-+#ifdef CONFIG_LAYER2_ROAMING
-+	u8	max_roaming_times; /* the max number driver will try to roaming */
-+#endif
-+
-+#ifdef CONFIG_IOL
-+	u8 fw_iol; /* enable iol without other concern */
-+#endif
-+
-+#ifdef CONFIG_80211D
-+	u8 enable80211d;
-+#endif
-+
-+	u8 ifname[16];
-+	u8 if2name[16];
-+
-+	u8 notch_filter;
-+
-+	/* for pll reference clock selction */
-+	u8 pll_ref_clk_sel;
-+
-+	/* define for tx power adjust */
-+#if CONFIG_TXPWR_LIMIT
-+	u8	RegEnableTxPowerLimit;
-+#endif
-+	u8	RegEnableTxPowerByRate;
-+
-+	u8 target_tx_pwr_valid;
-+	s8 target_tx_pwr_2g[RF_PATH_MAX][RATE_SECTION_NUM];
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	s8 target_tx_pwr_5g[RF_PATH_MAX][RATE_SECTION_NUM - 1];
-+#endif
-+	s16 antenna_gain;
-+
-+	u8 tsf_update_pause_factor;
-+	u8 tsf_update_restore_factor;
-+
-+	s8	TxBBSwing_2G;
-+	s8	TxBBSwing_5G;
-+	u8	AmplifierType_2G;
-+	u8	AmplifierType_5G;
-+	u8	bEn_RFE;
-+	u8	RFE_Type;
-+	u8	PowerTracking_Type;
-+	u8	GLNA_Type;
-+	u8  check_fw_ps;
-+	u8	RegPwrTrimEnable;
-+
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+	u8	load_phy_file;
-+	u8	RegDecryptCustomFile;
-+#endif
-+#ifdef CONFIG_CONCURRENT_MODE
-+	u8 virtual_iface_num;
-+#ifdef CONFIG_P2P
-+	u8 sel_p2p_iface;
-+#endif
-+#endif
-+	u8 qos_opt_enable;
-+
-+	u8 hiq_filter;
-+	u8 adaptivity_en;
-+	u8 adaptivity_mode;
-+	s8 adaptivity_th_l2h_ini;
-+	s8 adaptivity_th_edcca_hl_diff;
-+
-+	u8 boffefusemask;
-+	BOOLEAN bFileMaskEfuse;
-+	BOOLEAN bBTFileMaskEfuse;
-+#ifdef CONFIG_RTW_ACS
-+	u8 acs_auto_scan;
-+	u8 acs_mode;
-+#endif
-+
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+	u8 nm_mode;
-+#endif
-+	u32	reg_rxgain_offset_2g;
-+	u32	reg_rxgain_offset_5gl;
-+	u32	reg_rxgain_offset_5gm;
-+	u32	reg_rxgain_offset_5gh;
-+
-+#ifdef CONFIG_DFS_MASTER
-+	u8 dfs_region_domain;
-+#endif
-+
-+#ifdef CONFIG_MCC_MODE
-+	u8 en_mcc;
-+	u32 rtw_mcc_single_tx_cri;
-+	u32 rtw_mcc_ap_bw20_target_tx_tp;
-+	u32 rtw_mcc_ap_bw40_target_tx_tp;
-+	u32 rtw_mcc_ap_bw80_target_tx_tp;
-+	u32 rtw_mcc_sta_bw20_target_tx_tp;
-+	u32 rtw_mcc_sta_bw40_target_tx_tp;
-+	u32 rtw_mcc_sta_bw80_target_tx_tp;
-+	s8 rtw_mcc_policy_table_idx;
-+	u8 rtw_mcc_duration;
-+	u8 rtw_mcc_enable_runtime_duration;
-+	u8 rtw_mcc_phydm_offload;
-+#endif /* CONFIG_MCC_MODE */
-+
-+#ifdef CONFIG_RTW_NAPI
-+	u8 en_napi;
-+#ifdef CONFIG_RTW_NAPI_DYNAMIC
-+	u32 napi_threshold;	/* unit: Mbps */
-+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
-+#ifdef CONFIG_RTW_GRO
-+	u8 en_gro;
-+#endif /* CONFIG_RTW_GRO */
-+#endif /* CONFIG_RTW_NAPI */
-+
-+#ifdef CONFIG_WOWLAN
-+	u8 wowlan_enable;
-+	u8 wakeup_event;
-+	u8 suspend_type;
-+#endif
-+
-+	u8 recvbuf_nr;
-+
-+#ifdef CONFIG_SUPPORT_TRX_SHARED
-+	u8 trx_share_mode;
-+#endif
-+	u8 check_hw_status;
-+	u8 wowlan_sta_mix_mode;
-+
-+#ifdef CONFIG_PCI_HCI
-+	u32 pci_aspm_config;
-+	u32 pci_dynamic_aspm_linkctrl;
-+#endif
-+
-+	u8 iqk_fw_offload;
-+	u8 ch_switch_offload;
-+
-+#ifdef CONFIG_TDLS
-+	u8 en_tdls;
-+#endif
-+
-+#ifdef CONFIG_ADVANCE_OTA
-+	u8	adv_ota;
-+#endif
-+
-+#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
-+	u8 fw_param_init;
-+#endif
-+#ifdef CONFIG_DYNAMIC_SOML
-+	u8 dyn_soml_en;
-+	u8 dyn_soml_train_num;
-+	u8 dyn_soml_interval;
-+	u8 dyn_soml_period;
-+	u8 dyn_soml_delay;
-+#endif
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+	u8 fw_tbtt_rpt;
-+#endif
-+
-+#ifdef DBG_LA_MODE
-+	u8 la_mode_en;
-+#endif
-+	u32 phydm_ability;
-+	u32 halrf_ability;
-+#ifdef CONFIG_TDMADIG
-+	u8 tdmadig_en;
-+	u8 tdmadig_mode;
-+	u8 tdmadig_dynamic;
-+#endif/*CONFIG_TDMADIG*/
-+	u8 en_dyn_rrsr;
-+	u32 set_rrsr_value;
-+#ifdef CONFIG_RTW_MESH
-+	u8 peer_alive_based_preq;
-+#endif
-+
-+#ifdef RTW_BUSY_DENY_SCAN
-+	/*
-+	 * scan_interval_thr means scan interval threshold which is used to
-+	 * judge if user is in scan page or not.
-+	 * If scan interval < scan_interval_thr we guess user is in scan page,
-+	 * and driver won't deny any scan request at that time.
-+	 * Its default value comes from compiler flag
-+	 * BUSY_TRAFFIC_SCAN_DENY_PERIOD, and unit is ms.
-+	 */
-+	u32 scan_interval_thr;
-+#endif
-+
-+#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY
-+	u8 rtw_8822c_xcap_overwrite;
-+#endif
-+#ifdef CONFIG_RTW_MULTI_AP
-+	u8 unassoc_sta_mode_of_stype[UNASOC_STA_SRC_NUM];
-+	u16 max_unassoc_sta_cnt;
-+#endif
-+};
-+
-+/* For registry parameters */
-+#define RGTRY_OFT(field) ((u32)FIELD_OFFSET(struct registry_priv, field))
-+#define RGTRY_SZ(field)   sizeof(((struct registry_priv *) 0)->field)
-+
-+#define GetRegAmplifierType2G(_Adapter)	(_Adapter->registrypriv.AmplifierType_2G)
-+#define GetRegAmplifierType5G(_Adapter)	(_Adapter->registrypriv.AmplifierType_5G)
-+
-+#define GetRegTxBBSwing_2G(_Adapter)	(_Adapter->registrypriv.TxBBSwing_2G)
-+#define GetRegTxBBSwing_5G(_Adapter)	(_Adapter->registrypriv.TxBBSwing_5G)
-+
-+#define GetRegbENRFEType(_Adapter)	(_Adapter->registrypriv.bEn_RFE)
-+#define GetRegRFEType(_Adapter)	(_Adapter->registrypriv.RFE_Type)
-+#define GetRegGLNAType(_Adapter)	(_Adapter->registrypriv.GLNA_Type)
-+#define GetRegPowerTrackingType(_Adapter)	(_Adapter->registrypriv.PowerTracking_Type)
-+
-+#define WOWLAN_IS_STA_MIX_MODE(_Adapter)	(_Adapter->registrypriv.wowlan_sta_mix_mode)
-+#define BSSID_OFT(field) ((u32)FIELD_OFFSET(WLAN_BSSID_EX, field))
-+#define BSSID_SZ(field)   sizeof(((PWLAN_BSSID_EX) 0)->field)
-+
-+#define BW_MODE_2G(bw_mode) ((bw_mode) & 0x0F)
-+#define BW_MODE_5G(bw_mode) ((bw_mode) >> 4)
-+#ifdef CONFIG_80211N_HT
-+#define REGSTY_BW_2G(regsty) BW_MODE_2G((regsty)->bw_mode)
-+#define REGSTY_BW_5G(regsty) BW_MODE_5G((regsty)->bw_mode)
-+#else
-+#define REGSTY_BW_2G(regsty) CHANNEL_WIDTH_20
-+#define REGSTY_BW_5G(regsty) CHANNEL_WIDTH_20
-+#endif
-+#define REGSTY_IS_BW_2G_SUPPORT(regsty, bw) (REGSTY_BW_2G((regsty)) >= (bw))
-+#define REGSTY_IS_BW_5G_SUPPORT(regsty, bw) (REGSTY_BW_5G((regsty)) >= (bw))
-+
-+#ifdef CONFIG_80211AC_VHT
-+#define REGSTY_IS_11AC_ENABLE(regsty) ((regsty)->vht_enable != 0)
-+#define REGSTY_IS_11AC_AUTO(regsty) ((regsty)->vht_enable == 2)
-+#define REGSTY_IS_11AC_24G_ENABLE(regsty) ((regsty)->vht_24g_enable != 0)
-+#else
-+#define REGSTY_IS_11AC_ENABLE(regsty) 0
-+#define REGSTY_IS_11AC_AUTO(regsty) 0
-+#define REGSTY_IS_11AC_24G_ENABLE(regsty) 0
-+#endif
-+
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+#define REGSTY_REGD_SRC_FROM_OS(regsty) ((regsty)->regd_src == REGD_SRC_OS)
-+#else
-+#define REGSTY_REGD_SRC_FROM_OS(regsty) 0
-+#endif
-+
-+typedef struct rtw_if_operations {
-+	int __must_check (*read)(struct dvobj_priv *d, unsigned int addr, void *buf,
-+				size_t len, bool fixed);
-+	int __must_check (*write)(struct dvobj_priv *d, unsigned int addr, void *buf,
-+				 size_t len, bool fixed);
-+} RTW_IF_OPS, *PRTW_IF_OPS;
-+
-+#ifdef CONFIG_SDIO_HCI
-+	#include <drv_types_sdio.h>
-+	#define INTF_DATA	SDIO_DATA
-+	#define INTF_OPS	PRTW_IF_OPS
-+#elif defined(CONFIG_GSPI_HCI)
-+	#include <drv_types_gspi.h>
-+	#define INTF_DATA GSPI_DATA
-+#elif defined(CONFIG_PCI_HCI)
-+	#include <drv_types_pci.h>
-+#endif
-+
-+#define get_hw_port(adapter) (adapter->hw_port)
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	#define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER)
-+	#define is_vir_adapter(adapter) (adapter->adapter_type == VIRTUAL_ADAPTER)
-+#else
-+	#define is_primary_adapter(adapter) (1)
-+	#define is_vir_adapter(adapter) (0)
-+#endif
-+#define GET_PRIMARY_ADAPTER(padapter) (((_adapter *)padapter)->dvobj->padapters[IFACE_ID0])
-+#define GET_IFACE_NUMS(padapter) (((_adapter *)padapter)->dvobj->iface_nums)
-+#define GET_ADAPTER(padapter, iface_id) (((_adapter *)padapter)->dvobj->padapters[iface_id])
-+
-+#define GetDefaultAdapter(padapter)	padapter
-+
-+enum _IFACE_ID {
-+	IFACE_ID0, /*PRIMARY_ADAPTER*/
-+	IFACE_ID1,
-+	IFACE_ID2,
-+	IFACE_ID3,
-+	IFACE_ID4,
-+	IFACE_ID5,
-+	IFACE_ID6,
-+	IFACE_ID7,
-+	IFACE_ID_MAX,
-+};
-+
-+#define VIF_START_ID	1
-+
-+#ifdef CONFIG_DBG_COUNTER
-+
-+struct rx_logs {
-+	u32 intf_rx;
-+	u32 intf_rx_err_recvframe;
-+	u32 intf_rx_err_skb;
-+	u32 intf_rx_report;
-+	u32 core_rx;
-+	u32 core_rx_pre;
-+	u32 core_rx_pre_ver_err;
-+	u32 core_rx_pre_mgmt;
-+	u32 core_rx_pre_mgmt_err_80211w;
-+	u32 core_rx_pre_mgmt_err;
-+	u32 core_rx_pre_ctrl;
-+	u32 core_rx_pre_ctrl_err;
-+	u32 core_rx_pre_data;
-+	u32 core_rx_pre_data_wapi_seq_err;
-+	u32 core_rx_pre_data_wapi_key_err;
-+	u32 core_rx_pre_data_handled;
-+	u32 core_rx_pre_data_err;
-+	u32 core_rx_pre_data_unknown;
-+	u32 core_rx_pre_unknown;
-+	u32 core_rx_enqueue;
-+	u32 core_rx_dequeue;
-+	u32 core_rx_post;
-+	u32 core_rx_post_decrypt;
-+	u32 core_rx_post_decrypt_wep;
-+	u32 core_rx_post_decrypt_tkip;
-+	u32 core_rx_post_decrypt_aes;
-+	u32 core_rx_post_decrypt_wapi;
-+	u32 core_rx_post_decrypt_gcmp;
-+	u32 core_rx_post_decrypt_hw;
-+	u32 core_rx_post_decrypt_unknown;
-+	u32 core_rx_post_decrypt_err;
-+	u32 core_rx_post_defrag_err;
-+	u32 core_rx_post_portctrl_err;
-+	u32 core_rx_post_indicate;
-+	u32 core_rx_post_indicate_in_oder;
-+	u32 core_rx_post_indicate_reoder;
-+	u32 core_rx_post_indicate_err;
-+	u32 os_indicate;
-+	u32 os_indicate_ap_mcast;
-+	u32 os_indicate_ap_forward;
-+	u32 os_indicate_ap_self;
-+	u32 os_indicate_err;
-+	u32 os_netif_ok;
-+	u32 os_netif_err;
-+};
-+
-+struct tx_logs {
-+	u32 os_tx;
-+	u32 os_tx_err_up;
-+	u32 os_tx_err_xmit;
-+	u32 os_tx_m2u;
-+	u32 os_tx_m2u_ignore_fw_linked;
-+	u32 os_tx_m2u_ignore_self;
-+	u32 os_tx_m2u_entry;
-+	u32 os_tx_m2u_entry_err_xmit;
-+	u32 os_tx_m2u_entry_err_skb;
-+	u32 os_tx_m2u_stop;
-+	u32 core_tx;
-+	u32 core_tx_err_pxmitframe;
-+	u32 core_tx_err_brtx;
-+	u32 core_tx_upd_attrib;
-+	u32 core_tx_upd_attrib_adhoc;
-+	u32 core_tx_upd_attrib_sta;
-+	u32 core_tx_upd_attrib_ap;
-+	u32 core_tx_upd_attrib_unknown;
-+	u32 core_tx_upd_attrib_dhcp;
-+	u32 core_tx_upd_attrib_icmp;
-+	u32 core_tx_upd_attrib_active;
-+	u32 core_tx_upd_attrib_err_ucast_sta;
-+	u32 core_tx_upd_attrib_err_ucast_ap_link;
-+	u32 core_tx_upd_attrib_err_sta;
-+	u32 core_tx_upd_attrib_err_link;
-+	u32 core_tx_upd_attrib_err_sec;
-+	u32 core_tx_ap_enqueue_warn_fwstate;
-+	u32 core_tx_ap_enqueue_warn_sta;
-+	u32 core_tx_ap_enqueue_warn_nosta;
-+	u32 core_tx_ap_enqueue_warn_link;
-+	u32 core_tx_ap_enqueue_warn_trigger;
-+	u32 core_tx_ap_enqueue_mcast;
-+	u32 core_tx_ap_enqueue_ucast;
-+	u32 core_tx_ap_enqueue;
-+	u32 intf_tx;
-+	u32 intf_tx_pending_ac;
-+	u32 intf_tx_pending_fw_under_survey;
-+	u32 intf_tx_pending_fw_under_linking;
-+	u32 intf_tx_pending_xmitbuf;
-+	u32 intf_tx_enqueue;
-+	u32 core_tx_enqueue;
-+	u32 core_tx_enqueue_class;
-+	u32 core_tx_enqueue_class_err_sta;
-+	u32 core_tx_enqueue_class_err_nosta;
-+	u32 core_tx_enqueue_class_err_fwlink;
-+	u32 intf_tx_direct;
-+	u32 intf_tx_direct_err_coalesce;
-+	u32 intf_tx_dequeue;
-+	u32 intf_tx_dequeue_err_coalesce;
-+	u32 intf_tx_dump_xframe;
-+	u32 intf_tx_dump_xframe_err_txdesc;
-+	u32 intf_tx_dump_xframe_err_port;
-+};
-+
-+struct int_logs {
-+	u32 all;
-+	u32 err;
-+	u32 tbdok;
-+	u32 tbder;
-+	u32 bcnderr;
-+	u32 bcndma;
-+	u32 bcndma_e;
-+	u32 rx;
-+	u32 rx_rdu;
-+	u32 rx_fovw;
-+	u32 txfovw;
-+	u32 mgntok;
-+	u32 highdok;
-+	u32 bkdok;
-+	u32 bedok;
-+	u32 vidok;
-+	u32 vodok;
-+};
-+
-+#endif /* CONFIG_DBG_COUNTER */
-+
-+struct debug_priv {
-+	u32 dbg_sdio_free_irq_error_cnt;
-+	u32 dbg_sdio_alloc_irq_error_cnt;
-+	u32 dbg_sdio_free_irq_cnt;
-+	u32 dbg_sdio_alloc_irq_cnt;
-+	u32 dbg_sdio_deinit_error_cnt;
-+	u32 dbg_sdio_init_error_cnt;
-+	u32 dbg_suspend_error_cnt;
-+	u32 dbg_suspend_cnt;
-+	u32 dbg_resume_cnt;
-+	u32 dbg_resume_error_cnt;
-+	u32 dbg_deinit_fail_cnt;
-+	u32 dbg_carddisable_cnt;
-+	u32 dbg_carddisable_error_cnt;
-+	u32 dbg_ps_insuspend_cnt;
-+	u32	dbg_dev_unload_inIPS_cnt;
-+	u32 dbg_wow_leave_ps_fail_cnt;
-+	u32 dbg_scan_pwr_state_cnt;
-+	u32 dbg_downloadfw_pwr_state_cnt;
-+	u32 dbg_fw_read_ps_state_fail_cnt;
-+	u32 dbg_leave_ips_fail_cnt;
-+	u32 dbg_leave_lps_fail_cnt;
-+	u32 dbg_h2c_leave32k_fail_cnt;
-+	u32 dbg_diswow_dload_fw_fail_cnt;
-+	u32 dbg_enwow_dload_fw_fail_cnt;
-+	u32 dbg_ips_drvopen_fail_cnt;
-+	u32 dbg_poll_fail_cnt;
-+	u32 dbg_rpwm_toogle_cnt;
-+	u32 dbg_rpwm_timeout_fail_cnt;
-+	u32 dbg_sreset_cnt;
-+	u32 dbg_fw_mem_dl_error_cnt;
-+	u64 dbg_rx_fifo_last_overflow;
-+	u64 dbg_rx_fifo_curr_overflow;
-+	u64 dbg_rx_fifo_diff_overflow;
-+};
-+
-+struct rtw_traffic_statistics {
-+	/* tx statistics */
-+	u64	tx_bytes;
-+	u64	tx_pkts;
-+	u64	tx_drop;
-+	u64	cur_tx_bytes;
-+	u64	last_tx_bytes;
-+	u32	cur_tx_tp; /* Tx throughput in Mbps. */
-+
-+	/* rx statistics */
-+	u64	rx_bytes;
-+	u64	rx_pkts;
-+	u64	rx_drop;
-+	u64	cur_rx_bytes;
-+	u64	last_rx_bytes;
-+	u32	cur_rx_tp; /* Rx throughput in Mbps. */
-+};
-+
-+#define SEC_CAP_CHK_BMC	BIT0
-+#define SEC_CAP_CHK_EXTRA_SEC	BIT1 /* 256 bit */
-+#define SEC_CAP_CHK_WRITE_CAM_NEW_RULE	BIT2
-+
-+#define MACID_DROP BIT0
-+#define MACID_DROP_INDIRECT BIT1
-+
-+#define SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH	BIT0
-+
-+struct sec_cam_bmp {
-+	u32 m0;
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
-+	u32 m1;
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
-+	u32 m2;
-+#endif
-+#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
-+	u32 m3;
-+#endif
-+};
-+
-+struct cam_ctl_t {
-+	_lock lock;
-+
-+	u8 sec_cap;
-+	u32 flags;
-+
-+	u8 num;
-+	struct sec_cam_bmp used;
-+
-+	_mutex sec_cam_access_mutex;
-+};
-+
-+struct sec_cam_ent {
-+	u16 ctrl;
-+	u8 mac[ETH_ALEN];
-+	u8 key[16];
-+};
-+
-+#define KEY_FMT "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
-+#define KEY_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \
-+	((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \
-+	((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15]
-+
-+#define RTW_DEFAULT_MGMT_MACID 1
-+
-+struct macid_bmp {
-+	u32 m0;
-+#if (MACID_NUM_SW_LIMIT > 32)
-+	u32 m1;
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 64)
-+	u32 m2;
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 96)
-+	u32 m3;
-+#endif
-+};
-+
-+#ifdef CONFIG_CLIENT_PORT_CFG
-+struct clt_port_t{
-+	_lock lock;
-+	u8 bmp;
-+	s8 num;
-+};
-+#define get_clt_num(adapter) (adapter_to_dvobj(adapter)->clt_port.num)
-+#endif
-+
-+struct macid_ctl_t {
-+	_lock lock;
-+	u8 num;
-+	struct macid_bmp used;
-+	struct macid_bmp bmc;
-+	struct macid_bmp if_g[CONFIG_IFACE_NUMBER];
-+	struct macid_bmp ch_g[2]; /* 2 ch concurrency */
-+
-+	u8 iface_bmc[CONFIG_IFACE_NUMBER]; /* bmc TX macid for each iface*/
-+
-+	u8 h2c_msr[MACID_NUM_SW_LIMIT];
-+	u8 bw[MACID_NUM_SW_LIMIT];
-+	u8 vht_en[MACID_NUM_SW_LIMIT];
-+	u32 rate_bmp0[MACID_NUM_SW_LIMIT];
-+	u32 rate_bmp1[MACID_NUM_SW_LIMIT];
-+	u8 op_num[H2C_MSR_ROLE_MAX]; /* number of macid having h2c_msr's OPMODE = 1 for specific ROLE */
-+
-+	struct sta_info *sta[MACID_NUM_SW_LIMIT]; /* corresponding stainfo when macid is not shared */
-+	u8 macid_cap;
-+	/* macid sleep registers */
-+#ifdef CONFIG_PROTSEL_MACSLEEP
-+	u16 reg_sleep_ctrl;
-+	u16 reg_sleep_info;
-+	u16 reg_drop_ctrl;
-+	u16 reg_drop_info;
-+#else
-+	u16 reg_sleep_m0;
-+	u16 reg_drop_m0;
-+#if (MACID_NUM_SW_LIMIT > 32)
-+	u16 reg_sleep_m1;
-+	u16 reg_drop_m1;
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 64)
-+	u16 reg_sleep_m2;
-+	u16 reg_drop_m2;
-+#endif
-+#if (MACID_NUM_SW_LIMIT > 96)
-+	u16 reg_sleep_m3;
-+	u16 reg_drop_m3;
-+#endif
-+#endif
-+	u16 macid_txrpt;
-+	u8 macid_txrpt_pgsz;
-+};
-+
-+/* used for rf_ctl_t.rate_bmp_cck_ofdm */
-+#define RATE_BMP_CCK		0x000F
-+#define RATE_BMP_OFDM		0xFFF0
-+#define RATE_BMP_HAS_CCK(_bmp_cck_ofdm)		(_bmp_cck_ofdm & RATE_BMP_CCK)
-+#define RATE_BMP_HAS_OFDM(_bmp_cck_ofdm)	(_bmp_cck_ofdm & RATE_BMP_OFDM)
-+#define RATE_BMP_GET_CCK(_bmp_cck_ofdm)		(_bmp_cck_ofdm & RATE_BMP_CCK)
-+#define RATE_BMP_GET_OFDM(_bmp_cck_ofdm)	((_bmp_cck_ofdm & RATE_BMP_OFDM) >> 4)
-+
-+/* used for rf_ctl_t.rate_bmp_ht_by_bw */
-+#define RATE_BMP_HT_1SS		0x000000FF
-+#define RATE_BMP_HT_2SS		0x0000FF00
-+#define RATE_BMP_HT_3SS		0x00FF0000
-+#define RATE_BMP_HT_4SS		0xFF000000
-+#define RATE_BMP_HAS_HT_1SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_1SS)
-+#define RATE_BMP_HAS_HT_2SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_2SS)
-+#define RATE_BMP_HAS_HT_3SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_3SS)
-+#define RATE_BMP_HAS_HT_4SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_4SS)
-+#define RATE_BMP_GET_HT_1SS(_bmp_ht)		(_bmp_ht & RATE_BMP_HT_1SS)
-+#define RATE_BMP_GET_HT_2SS(_bmp_ht)		((_bmp_ht & RATE_BMP_HT_2SS) >> 8)
-+#define RATE_BMP_GET_HT_3SS(_bmp_ht)		((_bmp_ht & RATE_BMP_HT_3SS) >> 16)
-+#define RATE_BMP_GET_HT_4SS(_bmp_ht)		((_bmp_ht & RATE_BMP_HT_4SS) >> 24)
-+
-+/* used for rf_ctl_t.rate_bmp_vht_by_bw */
-+#define RATE_BMP_VHT_1SS	0x00000003FF
-+#define RATE_BMP_VHT_2SS	0x00000FFC00
-+#define RATE_BMP_VHT_3SS	0x003FF00000
-+#define RATE_BMP_VHT_4SS	0xFFC0000000
-+#define RATE_BMP_HAS_VHT_1SS(_bmp_vht)		(_bmp_vht & RATE_BMP_VHT_1SS)
-+#define RATE_BMP_HAS_VHT_2SS(_bmp_vht)		(_bmp_vht & RATE_BMP_VHT_2SS)
-+#define RATE_BMP_HAS_VHT_3SS(_bmp_vht)		(_bmp_vht & RATE_BMP_VHT_3SS)
-+#define RATE_BMP_HAS_VHT_4SS(_bmp_vht)		(_bmp_vht & RATE_BMP_VHT_4SS)
-+#define RATE_BMP_GET_VHT_1SS(_bmp_vht)		((u16)(_bmp_vht & RATE_BMP_VHT_1SS))
-+#define RATE_BMP_GET_VHT_2SS(_bmp_vht)		((u16)((_bmp_vht & RATE_BMP_VHT_2SS) >> 10))
-+#define RATE_BMP_GET_VHT_3SS(_bmp_vht)		((u16)((_bmp_vht & RATE_BMP_VHT_3SS) >> 20))
-+#define RATE_BMP_GET_VHT_4SS(_bmp_vht)		((u16)((_bmp_vht & RATE_BMP_VHT_4SS) >> 30))
-+
-+#define TXPWR_LMT_REF_VHT_FROM_HT	BIT0
-+#define TXPWR_LMT_REF_HT_FROM_VHT	BIT1
-+
-+#define TXPWR_LMT_HAS_CCK_1T	BIT0
-+#define TXPWR_LMT_HAS_CCK_2T	BIT1
-+#define TXPWR_LMT_HAS_CCK_3T	BIT2
-+#define TXPWR_LMT_HAS_CCK_4T	BIT3
-+#define TXPWR_LMT_HAS_OFDM_1T	BIT4
-+#define TXPWR_LMT_HAS_OFDM_2T	BIT5
-+#define TXPWR_LMT_HAS_OFDM_3T	BIT6
-+#define TXPWR_LMT_HAS_OFDM_4T	BIT7
-+
-+#define OFFCHS_NONE			0
-+#define OFFCHS_LEAVING_OP	1
-+#define OFFCHS_LEAVE_OP		2
-+#define OFFCHS_BACKING_OP	3
-+
-+#define TPC_MODE_DISABLE	0
-+#define TPC_MODE_MANUAL		1
-+#define TPC_MODE_INVALID	2	/* keep last */
-+
-+#define TPC_MANUAL_CONSTRAINT_MAX 600 /* mB */
-+
-+struct rf_ctl_t {
-+	enum regd_src_t regd_src;
-+	const struct country_chplan *country_ent;
-+	u8 ChannelPlan;
-+	u8 max_chan_nums;
-+	RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM];
-+	struct op_class_pref_t **spt_op_class_ch;
-+	u8 cap_spt_op_class_num;
-+	u8 reg_spt_op_class_num;
-+	u8 cur_spt_op_class_num;
-+	struct p2p_channels channel_list;
-+#ifdef CONFIG_RTW_MBO
-+	struct npref_ch_rtp ch_rtp;
-+#endif
-+
-+	s16 antenna_gain; /* mBi */
-+
-+	u8 op_class;
-+	u8 op_ch;
-+	s16 op_txpwr_max; /* EIRP in mBm */
-+	u8 if_op_class[CONFIG_IFACE_NUMBER];
-+	u8 if_op_ch[CONFIG_IFACE_NUMBER];
-+
-+	_mutex offch_mutex;
-+	u8 offch_state;
-+
-+	/* used for debug or by tx power limit */
-+	u16 rate_bmp_cck_ofdm;		/* 20MHz */
-+	u32 rate_bmp_ht_by_bw[2];	/* 20MHz, 40MHz. 4SS supported */
-+	u64 rate_bmp_vht_by_bw[4];	/* 20MHz, 40MHz, 80MHz, 160MHz. 4SS supported */
-+
-+#if CONFIG_TXPWR_LIMIT
-+	u8 highest_ht_rate_bw_bmp;
-+	u8 highest_vht_rate_bw_bmp;
-+
-+	_mutex txpwr_lmt_mutex;
-+	_list reg_exc_list;
-+	u8 regd_exc_num;
-+	_list txpwr_lmt_list;
-+	u8 txpwr_regd_num;
-+	const char *regd_name;
-+
-+	u8 txpwr_lmt_2g_cck_ofdm_state;
-+	#if CONFIG_IEEE80211_BAND_5GHZ
-+	u8 txpwr_lmt_5g_cck_ofdm_state;
-+	u8 txpwr_lmt_5g_20_40_ref;
-+	#endif
-+#endif
-+	u8 tpc_mode;
-+	u16 tpc_manual_constraint; /* mB */
-+
-+	bool ch_sel_within_same_band;
-+
-+#if CONFIG_DFS
-+	u8 csa_ch;
-+	u8 csa_switch_cnt;
-+	u8 csa_ch_offset;
-+	u8 csa_ch_width;
-+	u8 csa_ch_freq_seg0; /* Channel Center Frequency Segment 0 */
-+	u8 csa_ch_freq_seg1; /* Channel Center Frequency Segment 1 */
-+
-+#ifdef CONFIG_DFS_MASTER
-+	u8 dfs_region_domain;
-+	_timer radar_detect_timer;
-+	bool radar_detect_by_others;
-+	u8 radar_detect_enabled;
-+	bool radar_detected;
-+
-+	u8 radar_detect_ch;
-+	u8 radar_detect_bw;
-+	u8 radar_detect_offset;
-+
-+	systime cac_start_time;
-+	systime cac_end_time;
-+	u8 cac_force_stop;
-+
-+#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
-+	u8 dfs_slave_with_rd;
-+#endif
-+	u8 dfs_ch_sel_e_flags;
-+	u8 dfs_ch_sel_d_flags;
-+
-+	u8 dbg_dfs_fake_radar_detect_cnt;
-+	u8 dbg_dfs_radar_detect_trigger_non;
-+	u8 dbg_dfs_choose_dfs_ch_first;
-+#endif /* CONFIG_DFS_MASTER */
-+#endif /* CONFIG_DFS */
-+};
-+
-+struct wow_ctl_t {
-+	u8 wow_cap;
-+};
-+
-+#define WOW_CAP_TKIP_OL BIT0
-+
-+#define RTW_CAC_STOPPED 0
-+#ifdef CONFIG_DFS_MASTER
-+#define IS_CAC_STOPPED(rfctl) ((rfctl)->cac_end_time == RTW_CAC_STOPPED)
-+#define IS_CH_WAITING(rfctl) (!IS_CAC_STOPPED(rfctl) && rtw_time_after((rfctl)->cac_end_time, rtw_get_current_time()))
-+#define IS_UNDER_CAC(rfctl) (IS_CH_WAITING(rfctl) && rtw_time_after(rtw_get_current_time(), (rfctl)->cac_start_time))
-+#define IS_RADAR_DETECTED(rfctl) ((rfctl)->radar_detected)
-+#else
-+#define IS_CAC_STOPPED(rfctl) 1
-+#define IS_CH_WAITING(rfctl) 0
-+#define IS_UNDER_CAC(rfctl) 0
-+#define IS_RADAR_DETECTED(rfctl) 0
-+#endif /* CONFIG_DFS_MASTER */
-+
-+#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
-+#define IS_DFS_SLAVE_WITH_RD(rfctl) ((rfctl)->dfs_slave_with_rd)
-+#else
-+#define IS_DFS_SLAVE_WITH_RD(rfctl) 0
-+#endif
-+
-+#ifdef CONFIG_MBSSID_CAM
-+#define TOTAL_MBID_CAM_NUM	8
-+#define INVALID_CAM_ID			0xFF
-+struct mbid_cam_ctl_t {
-+	_lock lock;
-+	u8 bitmap;
-+	ATOMIC_T mbid_entry_num;
-+};
-+struct mbid_cam_cache {
-+	u8 iface_id;
-+	/*u8 role;*/ /*WIFI_STATION_STATE or WIFI_AP_STATE*/
-+	u8 mac_addr[ETH_ALEN];
-+};
-+#endif /*CONFIG_MBSSID_CAM*/
-+
-+#ifdef RTW_HALMAC
-+struct halmac_indicator {
-+	struct submit_ctx *sctx;
-+	u8 *buffer;
-+	u32 buf_size;
-+	u32 ret_size;
-+	u32 status;
-+};
-+
-+struct halmacpriv {
-+	/* flags */
-+#ifdef CONFIG_SDIO_HCI
-+	/*
-+	 * Indirect Access for SDIO,
-+	 * 0:default, 1:enable, 2:disable
-+	 */
-+	u8 sdio_io_indir;
-+#endif /* CONFIG_SDIO_HCI */
-+
-+	/* For asynchronous functions */
-+	struct halmac_indicator *indicator;
-+
-+	/* Hardware parameters */
-+#ifdef CONFIG_SDIO_HCI
-+	/* Store hardware tx queue page number setting */
-+	u16 txpage[HW_QUEUE_ENTRY];
-+#endif /* CONFIG_SDIO_HCI */
-+};
-+#endif /* RTW_HALMAC */
-+
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+/*info for H2C-0x2C*/
-+struct dft_info {
-+	u8 port_id;
-+	u8 mac_id;
-+};
-+#endif
-+
-+#ifdef CONFIG_HW_P0_TSF_SYNC
-+struct tsf_info {
-+	u8 sync_port;/*port_x's tsf sync to port_0*/
-+	u8 offset; /*tsf timer offset*/
-+};
-+#endif
-+
-+struct protsel {
-+	_mutex mutex;		/* protect this structure */
-+	ATOMIC_T refcnt;	/* reference count */
-+	u32 sel;		/* save the last sel port */
-+};
-+
-+#ifdef CONFIG_RTL8814B
-+#define MAX_BULKOUT_NUM 7
-+#ifdef CONFIG_USB_HCI
-+#define MAX_ENDPOINT_NUM 8
-+#endif
-+#else
-+#define MAX_BULKOUT_NUM 4
-+#ifdef CONFIG_USB_HCI
-+#define MAX_ENDPOINT_NUM 6
-+#endif
-+#endif
-+
-+struct dvobj_priv {
-+	/*-------- below is common data --------*/
-+	u8	chip_type;
-+	u8	HardwareType;
-+	u8	interface_type;/*USB,SDIO,SPI,PCI*/
-+
-+	ATOMIC_T	bSurpriseRemoved;
-+	ATOMIC_T	bDriverStopped;
-+
-+	s32	processing_dev_remove;
-+
-+	struct debug_priv drv_dbg;
-+
-+	_mutex hw_init_mutex;
-+	_mutex h2c_fwcmd_mutex;
-+
-+	_mutex ioctrl_mutex;
-+
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+	_mutex customer_str_mutex;
-+	struct submit_ctx *customer_str_sctx;
-+	u8 customer_str[RTW_CUSTOMER_STR_LEN];
-+#endif
-+
-+	_mutex setch_mutex;
-+	_mutex setbw_mutex;
-+	_mutex rf_read_reg_mutex;
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+	_mutex sd_indirect_access_mutex;
-+#endif
-+
-+#ifdef CONFIG_SYSON_INDIRECT_ACCESS
-+	_mutex syson_indirect_access_mutex;	/* System On Reg R/W */
-+#endif
-+
-+	unsigned char	oper_channel; /* saved channel info when call set_channel_bw */
-+	unsigned char	oper_bwmode;
-+	unsigned char	oper_ch_offset;/* PRIME_CHNL_OFFSET */
-+	systime on_oper_ch_time;
-+
-+	u8 union_ch;
-+	u8 union_bw;
-+	u8 union_offset;
-+	/* backup values when union_ch is set to 0 */
-+	u8 union_ch_bak;
-+	u8 union_bw_bak;
-+	u8 union_offset_bak;
-+
-+	_adapter *padapters[CONFIG_IFACE_NUMBER];/*IFACE_ID_MAX*/
-+	u8 iface_nums; /* total number of ifaces used runtime */
-+	struct mi_state iface_state;
-+
-+#ifdef CONFIG_AP_MODE
-+	#ifdef CONFIG_SUPPORT_MULTI_BCN
-+	u8		nr_ap_if; /* total interface number of ap /go /mesh / nan mode. */
-+	u16		inter_bcn_space; /* unit:ms */
-+	_queue	ap_if_q;
-+	u8		vap_map;
-+	u8		fw_bcn_offload;
-+	u8		vap_tbtt_rpt_map;
-+	#endif /*CONFIG_SUPPORT_MULTI_BCN*/
-+	#ifdef CONFIG_RTW_REPEATER_SON
-+	struct rtw_rson_struct  rson_data;
-+	#endif
-+#endif
-+#ifdef CONFIG_CLIENT_PORT_CFG
-+	struct clt_port_t clt_port;
-+#endif
-+
-+#ifdef CONFIG_HW_P0_TSF_SYNC
-+	struct tsf_info p0_tsf;
-+#endif
-+	systime periodic_tsf_update_etime;
-+	_timer periodic_tsf_update_end_timer;
-+
-+	struct macid_ctl_t macid_ctl;
-+
-+	struct cam_ctl_t cam_ctl;
-+	struct sec_cam_ent cam_cache[SEC_CAM_ENT_NUM_SW_LIMIT];
-+	
-+	struct wow_ctl_t wow_ctl;
-+
-+#ifdef CONFIG_MBSSID_CAM
-+	struct mbid_cam_ctl_t mbid_cam_ctl;
-+	struct mbid_cam_cache mbid_cam_cache[TOTAL_MBID_CAM_NUM];
-+#endif
-+
-+	struct rf_ctl_t rf_ctl;
-+
-+#if CONFIG_TX_AC_LIFETIME
-+	struct tx_aclt_conf_t tx_aclt_force_val;
-+	u8 tx_aclt_flags;
-+	struct tx_aclt_conf_t tx_aclt_confs[TX_ACLT_CONF_NUM];
-+#endif
-+
-+	/* In /Out Pipe information */
-+	int	RtInPipe[2];
-+	int	RtOutPipe[MAX_BULKOUT_NUM];
-+	u8	Queue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */
-+
-+	u8	irq_alloc;
-+	ATOMIC_T continual_io_error;
-+
-+	ATOMIC_T disable_func;
-+
-+	u8 xmit_block;
-+	_lock xmit_block_lock;
-+
-+	struct pwrctrl_priv pwrctl_priv;
-+
-+	struct rtw_traffic_statistics	traffic_stat;
-+
-+#ifdef PLATFORM_LINUX
-+	_thread_hdl_ rtnl_lock_holder;
-+
-+	#if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY)
-+	struct wiphy *wiphy;
-+	#endif
-+#endif /* PLATFORM_LINUX */
-+
-+#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+	_timer txbcn_timer;
-+#endif
-+	_timer dynamic_chk_timer; /* dynamic/periodic check timer */
-+	
-+#ifdef CONFIG_RTW_NAPI_DYNAMIC
-+	u8 en_napi_dynamic;
-+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
-+
-+#ifdef RTW_HALMAC
-+	void *halmac;
-+	struct halmacpriv hmpriv;
-+#endif /* RTW_HALMAC */
-+
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+	/*info for H2C-0x2C*/
-+	struct dft_info dft;
-+#endif
-+
-+#ifdef CONFIG_RTW_WIFI_HAL
-+	u32 nodfs;
-+#endif
-+
-+	/*-------- below is for SDIO INTERFACE --------*/
-+
-+#ifdef INTF_DATA
-+	INTF_DATA intf_data;
-+#endif
-+#ifdef INTF_OPS
-+	INTF_OPS intf_ops;
-+#endif
-+
-+#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+	u8 tx_aval_int_thr_mode;/* if 0=>threhold set by reques(default) ;if 1=>fixed by proc; if 2: fixed by sdio_tx_max_len */
-+	u8 tx_aval_int_thr_value;
-+#endif/*CONFIG_SDIO_TX_ENABLE_AVAL_INT*/
-+
-+	/*-------- below is for USB INTERFACE --------*/
-+
-+#ifdef CONFIG_USB_HCI
-+
-+	u8	usb_speed; /* 1.1, 2.0 or 3.0 */
-+	u8	nr_endpoint;
-+	u8	RtNumInPipes;
-+	u8	RtNumOutPipes;
-+	int	ep_num[MAX_ENDPOINT_NUM]; /* endpoint number */
-+
-+	int	RegUsbSS;
-+
-+	_sema	usb_suspend_sema;
-+
-+#ifdef CONFIG_USB_VENDOR_REQ_MUTEX
-+	_mutex  usb_vendor_req_mutex;
-+#endif
-+
-+#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
-+	u8 *usb_alloc_vendor_req_buf;
-+	u8 *usb_vendor_req_buf;
-+#endif
-+
-+#ifdef PLATFORM_LINUX
-+	struct usb_interface *pusbintf;
-+	struct usb_device *pusbdev;
-+#endif/* PLATFORM_LINUX */
-+
-+#ifdef PLATFORM_FREEBSD
-+	struct usb_interface *pusbintf;
-+	struct usb_device *pusbdev;
-+#endif/* PLATFORM_FREEBSD */
-+
-+#endif/* CONFIG_USB_HCI */
-+
-+	/*-------- below is for PCIE INTERFACE --------*/
-+
-+#ifdef CONFIG_PCI_HCI
-+
-+#ifdef PLATFORM_LINUX
-+	struct pci_dev *ppcidev;
-+
-+	/* PCI MEM map */
-+	unsigned long	pci_mem_end;	/* shared mem end	*/
-+	unsigned long	pci_mem_start;	/* shared mem start	*/
-+
-+	/* PCI IO map */
-+	unsigned long	pci_base_addr;	/* device I/O address	*/
-+
-+#ifdef CONFIG_PLATFORM_RTK129X
-+	unsigned long	ctrl_start;
-+	/* PCI MASK addr */
-+	unsigned long	mask_addr;
-+
-+	/* PCI TRANSLATE addr */
-+	unsigned long	tran_addr;
-+
-+	_lock   io_reg_lock;
-+#endif
-+
-+	/* PciBridge */
-+	struct pci_priv	pcipriv;
-+
-+	unsigned int irq; /* get from pci_dev.irq, store to net_device.irq */
-+	u16	irqline;
-+	u8	irq_enabled;
-+	RT_ISR_CONTENT	isr_content;
-+	_lock	irq_th_lock;
-+
-+	u8	bdma64;
-+#endif/* PLATFORM_LINUX */
-+
-+#endif/* CONFIG_PCI_HCI */
-+
-+#ifdef CONFIG_MCC_MODE
-+	struct mcc_obj_priv mcc_objpriv;
-+#endif /*CONFIG_MCC_MODE */
-+
-+#ifdef CONFIG_RTW_TPT_MODE
-+	u8 tpt_mode; /* RTK T/P Testing Mode, 0:default mode */
-+	u32 edca_be_ul;
-+	u32 edca_be_dl;
-+#endif 
-+	/* also for RTK T/P Testing Mode */ 
-+	u8 scan_deny;
-+
-+	/* protect sel to safely access */
-+#ifdef CONFIG_PROTSEL_PORT
-+	struct protsel protsel_port;
-+#endif
-+#ifdef CONFIG_PROTSEL_ATIMDTIM
-+	struct protsel protsel_atimdtim;
-+#endif
-+#ifdef CONFIG_PROTSEL_MACSLEEP
-+	struct protsel protsel_macsleep;
-+#endif
-+#ifdef CONFIG_WOWLAN
-+	u8  bcn_ctrl_clint3_bf_suspend;
-+	u16 rxfltmap2_bf_suspend;
-+	u8	lifetime_en;
-+	u32	pkt_lifetime;
-+	u32 rcr_bf_suspend;
-+	u32 cr_ext_bf_suspend;
-+#endif /* CONFIG_WOWLAN */
-+};
-+
-+#define DEV_STA_NUM(_dvobj)			MSTATE_STA_NUM(&((_dvobj)->iface_state))
-+#define DEV_STA_LD_NUM(_dvobj)		MSTATE_STA_LD_NUM(&((_dvobj)->iface_state))
-+#define DEV_STA_LG_NUM(_dvobj)		MSTATE_STA_LG_NUM(&((_dvobj)->iface_state))
-+#define DEV_TDLS_LD_NUM(_dvobj)		MSTATE_TDLS_LD_NUM(&((_dvobj)->iface_state))
-+#define DEV_AP_NUM(_dvobj)			MSTATE_AP_NUM(&((_dvobj)->iface_state))
-+#define DEV_AP_STARTING_NUM(_dvobj)	MSTATE_AP_STARTING_NUM(&((_dvobj)->iface_state))
-+#define DEV_AP_LD_NUM(_dvobj)		MSTATE_AP_LD_NUM(&((_dvobj)->iface_state))
-+#define DEV_ADHOC_NUM(_dvobj)		MSTATE_ADHOC_NUM(&((_dvobj)->iface_state))
-+#define DEV_ADHOC_LD_NUM(_dvobj)	MSTATE_ADHOC_LD_NUM(&((_dvobj)->iface_state))
-+#define DEV_MESH_NUM(_dvobj)		MSTATE_MESH_NUM(&((_dvobj)->iface_state))
-+#define DEV_MESH_LD_NUM(_dvobj)		MSTATE_MESH_LD_NUM(&((_dvobj)->iface_state))
-+#define DEV_P2P_DV_NUM(_dvobj)		MSTATE_P2P_DV_NUM(&((_dvobj)->iface_state))
-+#define DEV_P2P_GC_NUM(_dvobj)		MSTATE_P2P_GC_NUM(&((_dvobj)->iface_state))
-+#define DEV_P2P_GO_NUM(_dvobj)		MSTATE_P2P_GO_NUM(&((_dvobj)->iface_state))
-+#define DEV_SCAN_NUM(_dvobj)		MSTATE_SCAN_NUM(&((_dvobj)->iface_state))
-+#define DEV_WPS_NUM(_dvobj)			MSTATE_WPS_NUM(&((_dvobj)->iface_state))
-+#define DEV_ROCH_NUM(_dvobj)		MSTATE_ROCH_NUM(&((_dvobj)->iface_state))
-+#define DEV_MGMT_TX_NUM(_dvobj)		MSTATE_MGMT_TX_NUM(&((_dvobj)->iface_state))
-+
-+#define DEV_U_CH(_dvobj)			((_dvobj)->union_ch)
-+#define DEV_U_BW(_dvobj)			((_dvobj)->union_bw)
-+#define DEV_U_OFFSET(_dvobj)		((_dvobj)->union_offset)
-+
-+#define dvobj_to_pwrctl(dvobj) (&(dvobj->pwrctl_priv))
-+#define pwrctl_to_dvobj(pwrctl) container_of(pwrctl, struct dvobj_priv, pwrctl_priv)
-+#define dvobj_to_macidctl(dvobj) (&(dvobj->macid_ctl))
-+#define dvobj_to_sec_camctl(dvobj) (&(dvobj->cam_ctl))
-+#define dvobj_to_regsty(dvobj) (&(dvobj->padapters[IFACE_ID0]->registrypriv))
-+#if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY)
-+#define dvobj_to_wiphy(dvobj) ((dvobj)->wiphy)
-+#endif
-+#define dvobj_to_rfctl(dvobj) (&(dvobj->rf_ctl))
-+#define rfctl_to_dvobj(rfctl) container_of((rfctl), struct dvobj_priv, rf_ctl)
-+
-+static inline void dev_set_surprise_removed(struct dvobj_priv *dvobj)
-+{
-+	ATOMIC_SET(&dvobj->bSurpriseRemoved, _TRUE);
-+}
-+static inline void dev_clr_surprise_removed(struct dvobj_priv *dvobj)
-+{
-+	ATOMIC_SET(&dvobj->bSurpriseRemoved, _FALSE);
-+}
-+static inline void dev_set_drv_stopped(struct dvobj_priv *dvobj)
-+{
-+	ATOMIC_SET(&dvobj->bDriverStopped, _TRUE);
-+}
-+static inline void dev_clr_drv_stopped(struct dvobj_priv *dvobj)
-+{
-+	ATOMIC_SET(&dvobj->bDriverStopped, _FALSE);
-+}
-+#define dev_is_surprise_removed(dvobj)	(ATOMIC_READ(&dvobj->bSurpriseRemoved) == _TRUE)
-+#define dev_is_drv_stopped(dvobj)		(ATOMIC_READ(&dvobj->bDriverStopped) == _TRUE)
-+
-+#ifdef PLATFORM_LINUX
-+static inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
-+{
-+	/* todo: get interface type from dvobj and the return the dev accordingly */
-+#ifdef RTW_DVOBJ_CHIP_HW_TYPE
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	return &dvobj->pusbintf->dev;
-+#endif
-+#ifdef CONFIG_SDIO_HCI
-+	return &dvobj->intf_data.func->dev;
-+#endif
-+#ifdef CONFIG_GSPI_HCI
-+	return &dvobj->intf_data.func->dev;
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+	return &dvobj->ppcidev->dev;
-+#endif
-+}
-+#endif
-+
-+_adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj);
-+_adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj);
-+_adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr);
-+#define dvobj_get_primary_adapter(dvobj)	((dvobj)->padapters[IFACE_ID0])
-+
-+enum _hw_port {
-+	HW_PORT0,
-+	HW_PORT1,
-+	HW_PORT2,
-+	HW_PORT3,
-+	HW_PORT4,
-+	MAX_HW_PORT,
-+};
-+
-+#ifdef CONFIG_CLIENT_PORT_CFG
-+enum _client_port {
-+	CLT_PORT0 = HW_PORT1,
-+	CLT_PORT1 = HW_PORT2,
-+	CLT_PORT2 = HW_PORT3,
-+	CLT_PORT3 = HW_PORT4,
-+	CLT_PORT_INVALID = HW_PORT0,
-+};
-+
-+#define MAX_CLIENT_PORT_NUM	4
-+#define get_clt_port(adapter) (adapter->client_port)
-+#endif
-+
-+enum _ADAPTER_TYPE {
-+	PRIMARY_ADAPTER,
-+	VIRTUAL_ADAPTER,
-+	MAX_ADAPTER = 0xFF,
-+};
-+
-+typedef enum _DRIVER_STATE {
-+	DRIVER_NORMAL = 0,
-+	DRIVER_DISAPPEAR = 1,
-+	DRIVER_REPLACE_DONGLE = 2,
-+} DRIVER_STATE;
-+
-+#ifdef CONFIG_RTW_NAPI
-+enum _NAPI_STATE {
-+	NAPI_DISABLE = 0,
-+	NAPI_ENABLE = 1,
-+};
-+#endif
-+
-+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
-+typedef struct loopbackdata {
-+	_sema	sema;
-+	_thread_hdl_ lbkthread;
-+	u8 bstop;
-+	u32 cnt;
-+	u16 size;
-+	u16 txsize;
-+	u8 txbuf[0x8000];
-+	u16 rxsize;
-+	u8 rxbuf[0x8000];
-+	u8 msg[100];
-+
-+} LOOPBACKDATA, *PLOOPBACKDATA;
-+#endif
-+
-+#define ADAPTER_TX_BW_2G(adapter) BW_MODE_2G((adapter)->driver_tx_bw_mode)
-+#define ADAPTER_TX_BW_5G(adapter) BW_MODE_5G((adapter)->driver_tx_bw_mode)
-+
-+struct _ADAPTER {
-+	int	DriverState;/* for disable driver using module, use dongle to replace module. */
-+	int	pid[3];/* process id from UI, 0:wps, 1:hostapd, 2:dhcpcd */
-+	int	bDongle;/* build-in module or external dongle */
-+
-+	#if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN)
-+	_list	list;
-+	u8 vap_id;
-+	#endif
-+	struct dvobj_priv *dvobj;
-+	struct	mlme_priv mlmepriv;
-+	struct	mlme_ext_priv mlmeextpriv;
-+	struct	cmd_priv	cmdpriv;
-+	struct	evt_priv	evtpriv;
-+
-+#ifdef CONFIG_RTW_80211K
-+	struct	rm_priv		rmpriv;
-+#endif
-+	/* struct	io_queue	*pio_queue; */
-+	struct	io_priv	iopriv;
-+	struct	xmit_priv	xmitpriv;
-+	struct	recv_priv	recvpriv;
-+	struct	sta_priv	stapriv;
-+	struct	security_priv	securitypriv;
-+	_lock   security_key_mutex; /* add for CONFIG_IEEE80211W, none 11w also can use */
-+	struct	registry_priv	registrypriv;
-+
-+#ifdef CONFIG_RTW_NAPI
-+	struct	napi_struct napi;
-+	u8	napi_state;
-+#endif
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	struct	mp_priv	mppriv;
-+#endif
-+
-+#ifdef CONFIG_AP_MODE
-+	struct	hostapd_priv	*phostapdpriv;
-+#endif
-+
-+#if defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_IOCTL_CFG80211)
-+	struct roch_info rochinfo;
-+#endif
-+
-+	u32	setband;
-+	ATOMIC_T bandskip;
-+
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	wdinfo;
-+#endif /* CONFIG_P2P */
-+
-+#ifdef CONFIG_TDLS
-+	struct tdls_info	tdlsinfo;
-+#endif /* CONFIG_TDLS */
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	u8	WapiSupport;
-+	RT_WAPI_T	wapiInfo;
-+#endif
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	u8	rtw_rson_scanstage;
-+#endif
-+
-+#ifdef CONFIG_WFD
-+	struct wifi_display_info wfd_info;
-+#endif /* CONFIG_WFD */
-+
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+	struct bt_coex_info coex_info;
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+
-+	ERROR_CODE		LastError; /* <20130613, Kordan> Only the functions associated with MP records the error code by now. */
-+
-+	void *HalData;
-+	u32 hal_data_sz;
-+	struct hal_ops	hal_func;
-+
-+	u32	IsrContent;
-+	u32	ImrContent;
-+
-+	u8	EepromAddressSize;
-+	u8	bDriverIsGoingToUnload;
-+	u8	init_adpt_in_progress;
-+	u8	bHaltInProgress;
-+#ifdef CONFIG_GPIO_API
-+	u8	pre_gpio_pin;
-+	struct gpio_int_priv {
-+		u8 interrupt_mode;
-+		u8 interrupt_enable_mask;
-+		void (*callback[8])(u8 level);
-+	} gpiointpriv;
-+#endif
-+	_thread_hdl_ cmdThread;
-+#ifdef CONFIG_EVENT_THREAD_MODE
-+	_thread_hdl_ evtThread;
-+#endif
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+	_thread_hdl_ xmitThread;
-+#endif
-+#ifdef CONFIG_RECV_THREAD_MODE
-+	_thread_hdl_ recvThread;
-+#endif
-+	u8 registered;
-+
-+	void (*intf_start)(_adapter *adapter);
-+	void (*intf_stop)(_adapter *adapter);
-+
-+#ifdef PLATFORM_LINUX
-+	_nic_hdl pnetdev;
-+	char old_ifname[IFNAMSIZ];
-+	u8 ndev_unregistering;
-+	int bup;
-+	struct net_device_stats stats;
-+	struct iw_statistics iwstats;
-+	struct proc_dir_entry *dir_dev;/* for proc directory */
-+	struct proc_dir_entry *dir_odm;
-+
-+#ifdef CONFIG_MCC_MODE
-+	struct proc_dir_entry *dir_mcc;
-+#endif /* CONFIG_MCC_MODE */
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	struct wireless_dev *rtw_wdev;
-+	struct rtw_wdev_priv wdev_data;
-+
-+#if !defined(RTW_SINGLE_WIPHY)
-+	struct wiphy *wiphy;
-+#endif
-+
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+	void *cmap_bss_status_evt;
-+	u32 cmap_bss_status_evt_len;
-+	u8 cmap_unassoc_sta_measure_en;
-+#endif
-+
-+#endif /* PLATFORM_LINUX */
-+
-+#ifdef PLATFORM_FREEBSD
-+	_nic_hdl pifp;
-+	int bup;
-+	_lock glock;
-+#endif /* PLATFORM_FREEBSD */
-+	u8 mac_addr[ETH_ALEN];
-+	int net_closed;
-+
-+	u8 netif_up;
-+
-+	u8 bLinkInfoDump;
-+	/*	Added by Albert 2012/10/26 */
-+	/*	The driver will show up the desired channel number when this flag is 1. */
-+	u8 bNotifyChannelChange;
-+	u8 bsta_tp_dump;
-+#ifdef CONFIG_P2P
-+	/*	Added by Albert 2012/12/06 */
-+	/*	The driver will show the current P2P status when the upper application reads it. */
-+	u8 bShowGetP2PState;
-+#endif
-+
-+	u8 isprimary; /* is primary adapter or not */
-+	/* notes:
-+	**	if isprimary is true, the adapter_type value is 0, iface_id is IFACE_ID0 for PRIMARY_ADAPTER
-+	**	if isprimary is false, the adapter_type value is 1, iface_id is IFACE_ID1 for VIRTUAL_ADAPTER
-+	**	refer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff.*/
-+	u8 adapter_type;/*be used in  Multi-interface to recognize whether is PRIMARY_ADAPTER  or not(PRIMARY_ADAPTER/VIRTUAL_ADAPTER) .*/
-+	u8 hw_port; /*interface port type, it depends on HW port */
-+
-+	#ifdef CONFIG_CLIENT_PORT_CFG
-+	u8 client_id;
-+	u8 client_port;
-+	#endif
-+	/*struct tsf_info tsf;*//*reserve define for 8814B*/
-+
-+	/*extend to support multi interface*/
-+	u8 iface_id;
-+
-+#ifdef CONFIG_BR_EXT
-+	_lock					br_ext_lock;
-+	/* unsigned int			macclone_completed; */
-+	struct nat25_network_db_entry	*nethash[NAT25_HASH_SIZE];
-+	int				pppoe_connection_in_progress;
-+	unsigned char			pppoe_addr[MACADDRLEN];
-+	unsigned char			scdb_mac[MACADDRLEN];
-+	unsigned char			scdb_ip[4];
-+	struct nat25_network_db_entry	*scdb_entry;
-+	unsigned char			br_mac[MACADDRLEN];
-+	unsigned char			br_ip[4];
-+
-+	struct br_ext_info		ethBrExtInfo;
-+#endif /* CONFIG_BR_EXT */
-+
-+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
-+	PLOOPBACKDATA ploopback;
-+#endif
-+#ifdef CONFIG_AP_MODE
-+	u8 bmc_tx_rate;
-+	#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+	u8 b2u_flags_ap_src;
-+	u8 b2u_flags_ap_fwd;
-+	#endif
-+#endif
-+
-+	/* for debug purpose */
-+	u8 fix_rate;
-+	u8 fix_bw;
-+	u8 data_fb; /* data rate fallback, valid only when fix_rate is not 0xff */
-+	u8 power_offset;
-+	u8 driver_tx_bw_mode;
-+	u8 rsvd_page_offset;
-+	u8 rsvd_page_num;
-+	u8 ch_clm_ratio;
-+	u8 ch_nhm_ratio;
-+#ifdef CONFIG_SUPPORT_FIFO_DUMP
-+	u8 fifo_sel;
-+	u32 fifo_addr;
-+	u32 fifo_size;
-+#endif
-+
-+	u8 driver_vcs_en; /* Enable=1, Disable=0 driver control vrtl_carrier_sense for tx */
-+	u8 driver_vcs_type;/* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */
-+	u8 driver_ampdu_spacing;/* driver control AMPDU Density for peer sta's rx */
-+	u8 driver_rx_ampdu_factor;/* 0xff: disable drv ctrl, 0:8k, 1:16k, 2:32k, 3:64k; */
-+	u8 driver_rx_ampdu_spacing;  /* driver control Rx AMPDU Density */
-+	u8 fix_rx_ampdu_accept;
-+	u8 fix_rx_ampdu_size; /* 0~127, TODO:consider each sta and each TID */
-+#ifdef CONFIG_TX_AMSDU
-+	u8 tx_amsdu;
-+	u16 tx_amsdu_rate;
-+#endif
-+	u8 driver_tx_max_agg_num; /*fix tx desc max agg num , 0xff: disable drv ctrl*/
-+#ifdef DBG_RX_COUNTER_DUMP
-+	u8 dump_rx_cnt_mode;/*BIT0:drv,BIT1:mac,BIT2:phy*/
-+	u32 drv_rx_cnt_ok;
-+	u32 drv_rx_cnt_crcerror;
-+	u32 drv_rx_cnt_drop;
-+#endif
-+
-+#ifdef CONFIG_DBG_COUNTER
-+	struct rx_logs rx_logs;
-+	struct tx_logs tx_logs;
-+	struct int_logs int_logs;
-+#endif
-+
-+#ifdef CONFIG_MCC_MODE
-+	struct mcc_adapter_priv mcc_adapterpriv;
-+#endif /* CONFIG_MCC_MODE */
-+
-+#ifdef CONFIG_RTW_WDS
-+	bool use_wds; /* for STA, AP mode */
-+
-+	/* for STA mode */
-+	struct rtw_wds_gptr_table *wds_gpt_records;
-+	ATOMIC_T wds_gpt_record_num;
-+
-+	/* for AP mode */
-+	#ifdef CONFIG_AP_MODE
-+	struct rtw_wds_table *wds_paths;
-+	ATOMIC_T wds_path_num;
-+	#endif
-+#endif /* CONFIG_RTW_WDS */
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+	u8 multi_ap;
-+	u8 ch_util_threshold;
-+#endif
-+
-+#ifdef CONFIG_RTW_MESH
-+	struct rtw_mesh_cfg mesh_cfg;
-+	struct rtw_mesh_info mesh_info;
-+	_timer mesh_path_timer;
-+	_timer mesh_path_root_timer;
-+	_timer mesh_atlm_param_req_timer; /* airtime link metrics param request timer */
-+	_workitem mesh_work;
-+	unsigned long wrkq_flags;
-+#endif /* CONFIG_RTW_MESH */
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	ATOMIC_T tbtx_tx_pause;
-+	ATOMIC_T tbtx_remove_tx_pause;
-+	u8 tbtx_capability;
-+	u32	tbtx_duration;
-+#endif /* CONFIG_RTW_TOKEN_BASED_XMIT */
-+
-+#ifdef RTW_SIMPLE_CONFIG
-+	u8 rtw_simple_config;
-+#endif
-+};
-+
-+#define adapter_to_dvobj(adapter) ((adapter)->dvobj)
-+#define adapter_to_regsty(adapter) dvobj_to_regsty(adapter_to_dvobj((adapter)))
-+#define adapter_to_pwrctl(adapter) dvobj_to_pwrctl(adapter_to_dvobj((adapter)))
-+#define adapter_wdev_data(adapter) (&((adapter)->wdev_data))
-+#if defined(RTW_SINGLE_WIPHY)
-+#define adapter_to_wiphy(adapter) dvobj_to_wiphy(adapter_to_dvobj(adapter))
-+#else
-+#define adapter_to_wiphy(adapter) ((adapter)->wiphy)
-+#endif
-+
-+#define adapter_to_rfctl(adapter) dvobj_to_rfctl(adapter_to_dvobj((adapter)))
-+#define adapter_to_macidctl(adapter) dvobj_to_macidctl(adapter_to_dvobj((adapter)))
-+
-+#ifdef CONFIG_RTW_WDS
-+#define adapter_use_wds(adapter) (adapter->use_wds)
-+#define adapter_set_use_wds(adapter, en) do { \
-+		(adapter)->use_wds = (en) ? 1 : 0; \
-+		RTW_INFO(FUNC_ADPT_FMT" set use_wds=%d\n", FUNC_ADPT_ARG(adapter), (adapter)->use_wds); \
-+	} while (0)
-+#else
-+#define adapter_use_wds(adapter) 0
-+#endif
-+
-+#define adapter_mac_addr(adapter) (adapter->mac_addr)
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+#define adapter_pno_mac_addr(adapter) \
-+	((adapter_wdev_data(adapter))->pno_mac_addr)
-+#endif
-+
-+#define adapter_to_chset(adapter) (adapter_to_rfctl((adapter))->channel_set)
-+
-+#define mlme_to_adapter(mlme) container_of((mlme), struct _ADAPTER, mlmepriv)
-+#define tdls_info_to_adapter(tdls) container_of((tdls), struct _ADAPTER, tdlsinfo)
-+
-+#define rtw_get_chip_type(adapter) (((PADAPTER)adapter)->dvobj->chip_type)
-+#define rtw_get_hw_type(adapter) (((PADAPTER)adapter)->dvobj->HardwareType)
-+#define rtw_get_intf_type(adapter) (((PADAPTER)adapter)->dvobj->interface_type)
-+
-+#define rtw_get_mi_nums(adapter) (((PADAPTER)adapter)->dvobj->iface_nums)
-+
-+static inline void rtw_set_surprise_removed(_adapter *padapter)
-+{
-+	dev_set_surprise_removed(adapter_to_dvobj(padapter));
-+}
-+static inline void rtw_clr_surprise_removed(_adapter *padapter)
-+{
-+	dev_clr_surprise_removed(adapter_to_dvobj(padapter));
-+}
-+static inline void rtw_set_drv_stopped(_adapter *padapter)
-+{
-+	dev_set_drv_stopped(adapter_to_dvobj(padapter));
-+}
-+static inline void rtw_clr_drv_stopped(_adapter *padapter)
-+{
-+	dev_clr_drv_stopped(adapter_to_dvobj(padapter));
-+}
-+#define rtw_is_surprise_removed(padapter)	(dev_is_surprise_removed(adapter_to_dvobj(padapter)))
-+#define rtw_is_drv_stopped(padapter)		(dev_is_drv_stopped(adapter_to_dvobj(padapter)))
-+
-+/*
-+ * Function disabled.
-+ *   */
-+#define DF_TX_BIT		BIT0			/*write_port_cancel*/
-+#define DF_RX_BIT		BIT1			/*read_port_cancel*/
-+#define DF_IO_BIT		BIT2
-+
-+/* #define RTW_DISABLE_FUNC(padapter, func) (ATOMIC_ADD(&adapter_to_dvobj(padapter)->disable_func, (func))) */
-+/* #define RTW_ENABLE_FUNC(padapter, func) (ATOMIC_SUB(&adapter_to_dvobj(padapter)->disable_func, (func))) */
-+__inline static void RTW_DISABLE_FUNC(_adapter *padapter, int func_bit)
-+{
-+	int	df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func);
-+	df |= func_bit;
-+	ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df);
-+}
-+
-+__inline static void RTW_ENABLE_FUNC(_adapter *padapter, int func_bit)
-+{
-+	int	df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func);
-+	df &= ~(func_bit);
-+	ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df);
-+}
-+
-+#define RTW_CANNOT_RUN(padapter) \
-+	(rtw_is_surprise_removed(padapter) || \
-+	 rtw_is_drv_stopped(padapter))
-+
-+#define RTW_IS_FUNC_DISABLED(padapter, func_bit) (ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func) & (func_bit))
-+
-+#define RTW_CANNOT_IO(padapter) \
-+	(rtw_is_surprise_removed(padapter) || \
-+	 RTW_IS_FUNC_DISABLED((padapter), DF_IO_BIT))
-+
-+#define RTW_CANNOT_RX(padapter) \
-+	(RTW_CANNOT_RUN(padapter) || \
-+	 RTW_IS_FUNC_DISABLED((padapter), DF_RX_BIT))
-+
-+#define RTW_CANNOT_TX(padapter) \
-+	(RTW_CANNOT_RUN(padapter) || \
-+	 RTW_IS_FUNC_DISABLED((padapter), DF_TX_BIT))
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+int rtw_parse_ssid_list_tlv(char **list_str, pno_ssid_t *ssid, int max, int *bytes_left);
-+int rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num,
-+		    int pno_time, int pno_repeat, int pno_freq_expo_max);
-+#ifdef CONFIG_PNO_SET_DEBUG
-+	void rtw_dev_pno_debug(struct net_device *net);
-+#endif /* CONFIG_PNO_SET_DEBUG */
-+#endif /* CONFIG_PNO_SUPPORT */
-+
-+int rtw_suspend_free_assoc_resource(_adapter *padapter);
-+#ifdef CONFIG_WOWLAN
-+	int rtw_suspend_wow(_adapter *padapter);
-+	int rtw_resume_process_wow(_adapter *padapter);
-+#endif
-+
-+/* HCI Related header file */
-+#ifdef CONFIG_USB_HCI
-+	#include <usb_osintf.h>
-+	#include <usb_ops.h>
-+	#include <usb_hal.h>
-+#endif
-+
-+#ifdef CONFIG_SDIO_HCI
-+	#include <sdio_osintf.h>
-+	#include <sdio_ops.h>
-+	#include <sdio_hal.h>
-+#endif
-+
-+#ifdef CONFIG_GSPI_HCI
-+	#include <gspi_osintf.h>
-+	#include <gspi_ops.h>
-+	#include <gspi_hal.h>
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	#include <pci_osintf.h>
-+	#include <pci_ops.h>
-+	#include <pci_hal.h>
-+#endif
-+
-+#endif /* __DRV_TYPES_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/drv_types_ce.h b/drivers/staging/rtl8723cs/include/drv_types_ce.h
-new file mode 100644
-index 000000000000..c00dea8e6b35
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/drv_types_ce.h
-@@ -0,0 +1,86 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __DRV_TYPES_CE_H__
-+#define __DRV_TYPES_CE_H__
-+
-+#include <drv_conf.h>
-+#include <osdep_service.h>
-+
-+#include <Sdcardddk.h>
-+
-+#define MAX_ACTIVE_REG_PATH 256
-+
-+#define MAX_MCAST_LIST_NUM					32
-+
-+
-+
-+/* for ioctl */
-+#define MAKE_DRIVER_VERSION(_MainVer, _MinorVer)	((((u32)(_MainVer))<<16)+_MinorVer)
-+
-+#define NIC_HEADER_SIZE				14			/* !< can be moved to typedef.h */
-+#define NIC_MAX_PACKET_SIZE			1514		/* !< can be moved to typedef.h */
-+#define NIC_MAX_SEND_PACKETS			10		/* max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h */
-+#define NIC_VENDOR_DRIVER_VERSION       MAKE_DRIVER_VERSION(0, 001)	/* !< can be moved to typedef.h */
-+#define NIC_MAX_PACKET_SIZE			1514		/* !< can be moved to typedef.h */
-+
-+typedef struct _MP_REG_ENTRY {
-+
-+	NDIS_STRING		RegName;	/* variable name text */
-+	BOOLEAN			bRequired;	/* 1->required, 0->optional */
-+
-+	u8			Type;		/* NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString */
-+	uint			FieldOffset;	/* offset to MP_ADAPTER field */
-+	uint			FieldSize;	/* size (in bytes) of the field */
-+
-+#ifdef UNDER_AMD64
-+	u64			Default;
-+#else
-+	u32			Default;		/* default value to use */
-+#endif
-+
-+	u32			Min;			/* minimum value allowed */
-+	u32			Max;		/* maximum value allowed */
-+} MP_REG_ENTRY, *PMP_REG_ENTRY;
-+
-+#ifdef CONFIG_USB_HCI
-+typedef struct _USB_EXTENSION {
-+	LPCUSB_FUNCS    _lpUsbFuncs;
-+	USB_HANDLE	    _hDevice;
-+	PVOID		    pAdapter;
-+
-+#if 0
-+	USB_ENDPOINT_DESCRIPTOR		_endpACLIn;
-+	USB_ENDPOINT_DESCRIPTOR		_endpACLOutHigh;
-+	USB_ENDPOINT_DESCRIPTOR		_endpACLOutNormal;
-+
-+	USB_PIPE        pPipeIn;
-+	USB_PIPE        pPipeOutNormal;
-+	USB_PIPE        pPipeOutHigh;
-+#endif
-+
-+} USB_EXTENSION, *PUSB_EXTENSION;
-+#endif
-+
-+
-+typedef struct _OCTET_STRING {
-+	u8      *Octet;
-+	u16      Length;
-+} OCTET_STRING, *POCTET_STRING;
-+
-+
-+
-+
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/drv_types_gspi.h b/drivers/staging/rtl8723cs/include/drv_types_gspi.h
-new file mode 100644
-index 000000000000..c22c4972232d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/drv_types_gspi.h
-@@ -0,0 +1,49 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __DRV_TYPES_GSPI_H__
-+#define __DRV_TYPES_GSPI_H__
-+
-+/* SPI Header Files */
-+#ifdef PLATFORM_LINUX
-+	#include <linux/platform_device.h>
-+	#include <linux/spi/spi.h>
-+	#include <linux/gpio.h>
-+	/* #include <mach/ldo.h> */
-+	#include <asm/mach-types.h>
-+	#include <asm/gpio.h>
-+	#include <asm/io.h>
-+	#include <mach/board.h>
-+	#include <mach/hardware.h>
-+	#include <mach/irqs.h>
-+	#include <custom_gpio.h>
-+#endif
-+
-+
-+typedef struct gspi_data {
-+	u8  func_number;
-+
-+	u8  tx_block_mode;
-+	u8  rx_block_mode;
-+	u32 block_transfer_len;
-+
-+#ifdef PLATFORM_LINUX
-+	struct spi_device *func;
-+
-+	struct workqueue_struct *priv_wq;
-+	struct delayed_work irq_work;
-+#endif
-+} GSPI_DATA, *PGSPI_DATA;
-+
-+#endif /*  #ifndef __DRV_TYPES_GSPI_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/drv_types_linux.h b/drivers/staging/rtl8723cs/include/drv_types_linux.h
-new file mode 100644
-index 000000000000..91ca68b39c26
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/drv_types_linux.h
-@@ -0,0 +1,19 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __DRV_TYPES_LINUX_H__
-+#define __DRV_TYPES_LINUX_H__
-+
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/drv_types_pci.h b/drivers/staging/rtl8723cs/include/drv_types_pci.h
-new file mode 100644
-index 000000000000..2c550ecc0bed
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/drv_types_pci.h
-@@ -0,0 +1,60 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __DRV_TYPES_PCI_H__
-+#define __DRV_TYPES_PCI_H__
-+
-+#ifdef PLATFORM_LINUX
-+	#include <linux/pci.h>
-+#endif
-+
-+#define	INTEL_VENDOR_ID				0x8086
-+#define	SIS_VENDOR_ID					0x1039
-+#define	ATI_VENDOR_ID					0x1002
-+#define	ATI_DEVICE_ID					0x7914
-+#define	AMD_VENDOR_ID					0x1022
-+
-+#define PCI_VENDER_ID_REALTEK		0x10ec
-+
-+enum aspm_mode {
-+	ASPM_MODE_UND,
-+	ASPM_MODE_PERF,
-+	ASPM_MODE_PS,
-+	ASPM_MODE_DEF,
-+};
-+
-+struct pci_priv {
-+	BOOLEAN		pci_clk_req;
-+
-+	u8	pciehdr_offset;
-+
-+	u8	linkctrl_reg;
-+	u8	pcibridge_linkctrlreg;
-+
-+	u8	amd_l1_patch;
-+
-+#ifdef CONFIG_PCI_DYNAMIC_ASPM
-+	u8	aspm_mode;
-+#endif
-+};
-+
-+typedef struct _RT_ISR_CONTENT {
-+	union {
-+		u32			IntArray[2];
-+		u32			IntReg4Byte;
-+		u16			IntReg2Byte;
-+	};
-+} RT_ISR_CONTENT, *PRT_ISR_CONTENT;
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/drv_types_sdio.h b/drivers/staging/rtl8723cs/include/drv_types_sdio.h
-new file mode 100644
-index 000000000000..29006d981aa3
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/drv_types_sdio.h
-@@ -0,0 +1,94 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __DRV_TYPES_SDIO_H__
-+#define __DRV_TYPES_SDIO_H__
-+
-+/* SDIO Header Files */
-+#ifdef PLATFORM_LINUX
-+	#include <linux/mmc/sdio_func.h>
-+	#include <linux/mmc/sdio_ids.h>
-+	#include <linux/mmc/host.h>
-+	#include <linux/mmc/card.h>
-+
-+	#ifdef CONFIG_PLATFORM_SPRD
-+		#include <linux/gpio.h>
-+		#include <custom_gpio.h>
-+	#endif /* CONFIG_PLATFORM_SPRD */
-+#endif
-+
-+#define RTW_SDIO_CLK_33M	33000000
-+#define RTW_SDIO_CLK_40M	40000000
-+#define RTW_SDIO_CLK_80M	80000000
-+#define RTW_SDIO_CLK_160M	160000000
-+
-+typedef struct sdio_data {
-+	u8  func_number;
-+
-+	u8  tx_block_mode;
-+	u8  rx_block_mode;
-+	u32 block_transfer_len;
-+
-+#ifdef PLATFORM_LINUX
-+	struct mmc_card *card;
-+	struct sdio_func	*func;
-+	_thread_hdl_ sys_sdio_irq_thd;
-+	unsigned int clock;
-+	unsigned int timing;
-+	u8	sd3_bus_mode;
-+#endif
-+
-+#ifdef DBG_SDIO
-+#ifdef PLATFORM_LINUX
-+	struct proc_dir_entry *proc_sdio_dbg;
-+#endif /* PLATFORM_LINUX */
-+
-+	u32 cmd52_err_cnt;	/* CMD52 I/O error count */
-+	u32 cmd53_err_cnt;	/* CMD53 I/O error count */
-+
-+#if (DBG_SDIO >= 1)
-+	u32 reg_dump_mark;	/* reg dump at specific error count */
-+#endif /* DBG_SDIO >= 1 */
-+
-+#if (DBG_SDIO >= 2)
-+	u8 *dbg_msg;		/* Messages for debug */
-+	u8 dbg_msg_size;
-+	u8 *reg_mac;		/* Device MAC register, 0x0~0x800 */
-+	u8 *reg_mac_ext;	/* Device MAC extend register, 0x1000~0x1800 */
-+	u8 *reg_local;		/* Device SDIO local register, 0x0~0xFF */
-+	u8 *reg_cia;		/* SDIO CIA(CCCR, FBR and etc.), 0x0~0x1FF */
-+#endif /* DBG_SDIO >= 2 */
-+
-+#if (DBG_SDIO >= 3)
-+	u8 dbg_enable;		/* 0/1: disable/enable debug mode */
-+	u8 err_stop;		/* Stop(surprise remove) when I/O error happen */
-+	u8 err_test;		/* Simulate error happen */
-+	u8 err_test_triggered;	/* Simulate error already triggered */
-+#endif /* DBG_SDIO >= 3 */
-+#endif /* DBG_SDIO */
-+} SDIO_DATA, *PSDIO_DATA;
-+
-+#define dvobj_to_sdio_func(d)	((d)->intf_data.func)
-+
-+#define RTW_SDIO_ADDR_CMD52_BIT		(1<<17)
-+#define RTW_SDIO_ADDR_CMD52_GEN(a)	(a | RTW_SDIO_ADDR_CMD52_BIT)
-+#define RTW_SDIO_ADDR_CMD52_CLR(a)	(a&~RTW_SDIO_ADDR_CMD52_BIT)
-+#define RTW_SDIO_ADDR_CMD52_CHK(a)	(a&RTW_SDIO_ADDR_CMD52_BIT ? 1 : 0)
-+
-+#define RTW_SDIO_ADDR_F0_BIT		(1<<18)
-+#define RTW_SDIO_ADDR_F0_GEN(a)		(a | RTW_SDIO_ADDR_F0_BIT)
-+#define RTW_SDIO_ADDR_F0_CLR(a)		(a&~RTW_SDIO_ADDR_F0_BIT)
-+#define RTW_SDIO_ADDR_F0_CHK(a)		(a&RTW_SDIO_ADDR_F0_BIT ? 1 : 0)
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/drv_types_xp.h b/drivers/staging/rtl8723cs/include/drv_types_xp.h
-new file mode 100644
-index 000000000000..81c45047ae11
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/drv_types_xp.h
-@@ -0,0 +1,88 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __DRV_TYPES_XP_H__
-+#define __DRV_TYPES_XP_H__
-+
-+#include <drv_conf.h>
-+#include <osdep_service.h>
-+
-+
-+
-+#define MAX_MCAST_LIST_NUM					32
-+
-+
-+
-+/* for ioctl */
-+#define MAKE_DRIVER_VERSION(_MainVer, _MinorVer)	((((u32)(_MainVer))<<16)+_MinorVer)
-+
-+#define NIC_HEADER_SIZE				14			/* !< can be moved to typedef.h */
-+#define NIC_MAX_PACKET_SIZE			1514		/* !< can be moved to typedef.h */
-+#define NIC_MAX_SEND_PACKETS			10		/* max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h */
-+#define NIC_VENDOR_DRIVER_VERSION       MAKE_DRIVER_VERSION(0, 001)	/* !< can be moved to typedef.h */
-+#define NIC_MAX_PACKET_SIZE			1514		/* !< can be moved to typedef.h */
-+
-+
-+#undef ON_VISTA
-+/* added by Jackson */
-+#ifndef ON_VISTA
-+	/*
-+	* Bus driver versions
-+	*   */
-+
-+	#define SDBUS_DRIVER_VERSION_1          0x100
-+	#define SDBUS_DRIVER_VERSION_2          0x200
-+
-+	#define    SDP_FUNCTION_TYPE	4
-+	#define    SDP_BUS_DRIVER_VERSION 5
-+	#define    SDP_BUS_WIDTH 6
-+	#define    SDP_BUS_CLOCK 7
-+	#define    SDP_BUS_INTERFACE_CONTROL 8
-+	#define    SDP_HOST_BLOCK_LENGTH 9
-+	#define    SDP_FUNCTION_BLOCK_LENGTH 10
-+	#define    SDP_FN0_BLOCK_LENGTH 11
-+	#define    SDP_FUNCTION_INT_ENABLE 12
-+#endif
-+
-+
-+typedef struct _MP_REG_ENTRY {
-+
-+	NDIS_STRING		RegName;	/* variable name text */
-+	BOOLEAN			bRequired;	/* 1->required, 0->optional */
-+
-+	u8			Type;		/* NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString */
-+	uint			FieldOffset;	/* offset to MP_ADAPTER field */
-+	uint			FieldSize;	/* size (in bytes) of the field */
-+
-+#ifdef UNDER_AMD64
-+	u64			Default;
-+#else
-+	u32			Default;		/* default value to use */
-+#endif
-+
-+	u32			Min;			/* minimum value allowed */
-+	u32			Max;		/* maximum value allowed */
-+} MP_REG_ENTRY, *PMP_REG_ENTRY;
-+
-+
-+typedef struct _OCTET_STRING {
-+	u8      *Octet;
-+	u16      Length;
-+} OCTET_STRING, *POCTET_STRING;
-+
-+
-+
-+
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/ethernet.h b/drivers/staging/rtl8723cs/include/ethernet.h
-new file mode 100644
-index 000000000000..ef518cc4171d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/ethernet.h
-@@ -0,0 +1,36 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*! \file */
-+#ifndef __INC_ETHERNET_H
-+#define __INC_ETHERNET_H
-+
-+#define ETHERNET_ADDRESS_LENGTH				6		/* !< Ethernet Address Length */
-+#define ETHERNET_HEADER_SIZE				14		/* !< Ethernet Header Length */
-+#define LLC_HEADER_SIZE						6		/* !< LLC Header Length */
-+#define TYPE_LENGTH_FIELD_SIZE				2		/* !< Type/Length Size */
-+#define MINIMUM_ETHERNET_PACKET_SIZE		60		/* !< Minimum Ethernet Packet Size */
-+#define MAXIMUM_ETHERNET_PACKET_SIZE		1514	/* !< Maximum Ethernet Packet Size */
-+
-+#define RT_ETH_IS_MULTICAST(_pAddr)	((((u8 *)(_pAddr))[0]&0x01) != 0)		/* !< Is Multicast Address? */
-+#define RT_ETH_IS_BROADCAST(_pAddr)	(\
-+		((u8 *)(_pAddr))[0] == 0xff	&&		\
-+		((u8 *)(_pAddr))[1] == 0xff	&&		\
-+		((u8 *)(_pAddr))[2] == 0xff	&&		\
-+		((u8 *)(_pAddr))[3] == 0xff	&&		\
-+		((u8 *)(_pAddr))[4] == 0xff	&&		\
-+		((u8 *)(_pAddr))[5] == 0xff)	/* !< Is Broadcast Address? */
-+
-+
-+#endif /*  #ifndef __INC_ETHERNET_H */
-diff --git a/drivers/staging/rtl8723cs/include/gspi_hal.h b/drivers/staging/rtl8723cs/include/gspi_hal.h
-new file mode 100644
-index 000000000000..6da0f071d499
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/gspi_hal.h
-@@ -0,0 +1,30 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __GSPI_HAL_H__
-+#define __GSPI_HAL_H__
-+
-+
-+void spi_int_dpc(PADAPTER padapter, u32 sdio_hisr);
-+u8 rtw_set_hal_ops(_adapter *padapter);
-+
-+#ifdef CONFIG_RTL8188E
-+	void rtl8188es_set_hal_ops(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8723B
-+	void rtl8723bs_set_hal_ops(PADAPTER padapter);
-+#endif
-+
-+#endif /* __GSPI_HAL_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/gspi_ops.h b/drivers/staging/rtl8723cs/include/gspi_ops.h
-new file mode 100644
-index 000000000000..bcfaad2e0bba
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/gspi_ops.h
-@@ -0,0 +1,180 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __GSPI_OPS_H__
-+#define __GSPI_OPS_H__
-+
-+/* follwing defination is based on
-+ * GSPI spec of RTL8723, we temp
-+ * suppose that it will be the same
-+ * for diff chips of GSPI, if not
-+ * we should move it to HAL folder */
-+#define SPI_LOCAL_DOMAIN				0x0
-+#define WLAN_IOREG_DOMAIN			0x8
-+#define FW_FIFO_DOMAIN				0x4
-+#define TX_HIQ_DOMAIN					0xc
-+#define TX_MIQ_DOMAIN					0xd
-+#define TX_LOQ_DOMAIN					0xe
-+#define RX_RXFIFO_DOMAIN				0x1f
-+
-+/* IO Bus domain address mapping */
-+#define DEFUALT_OFFSET					0x0
-+#define SPI_LOCAL_OFFSET				0x10250000
-+#define WLAN_IOREG_OFFSET			0x10260000
-+#define FW_FIFO_OFFSET				0x10270000
-+#define TX_HIQ_OFFSET					0x10310000
-+#define TX_MIQ_OFFSET					0x1032000
-+#define TX_LOQ_OFFSET					0x10330000
-+#define RX_RXOFF_OFFSET				0x10340000
-+
-+/* SPI Local registers */
-+#define SPI_REG_TX_CTRL					0x0000 /* SPI Tx Control */
-+#define SPI_REG_STATUS_RECOVERY		0x0004
-+#define SPI_REG_INT_TIMEOUT			0x0006
-+#define SPI_REG_HIMR					0x0014 /* SPI Host Interrupt Mask */
-+#define SPI_REG_HISR					0x0018 /* SPI Host Interrupt Service Routine */
-+#define SPI_REG_RX0_REQ_LEN			0x001C /* RXDMA Request Length */
-+#define SPI_REG_FREE_TXPG				0x0020 /* Free Tx Buffer Page */
-+#define SPI_REG_HCPWM1					0x0024 /* HCI Current Power Mode 1 */
-+#define SPI_REG_HCPWM2					0x0026 /* HCI Current Power Mode 2 */
-+#define SPI_REG_HTSFR_INFO				0x0030 /* HTSF Informaion */
-+#define SPI_REG_HRPWM1					0x0080 /* HCI Request Power Mode 1 */
-+#define SPI_REG_HRPWM2					0x0082 /* HCI Request Power Mode 2 */
-+#define SPI_REG_HPS_CLKR				0x0084 /* HCI Power Save Clock */
-+#define SPI_REG_HSUS_CTRL				0x0086 /* SPI HCI Suspend Control */
-+#define SPI_REG_HIMR_ON				0x0090 /* SPI Host Extension Interrupt Mask Always */
-+#define SPI_REG_HISR_ON				0x0091 /* SPI Host Extension Interrupt Status Always */
-+#define SPI_REG_CFG						0x00F0 /* SPI Configuration Register */
-+
-+#define SPI_TX_CTRL				(SPI_REG_TX_CTRL | SPI_LOCAL_OFFSET)
-+#define SPI_STATUS_RECOVERY			(SPI_REG_STATUS_RECOVERY | SPI_LOCAL_OFFSET)
-+#define SPI_INT_TIMEOUT					(SPI_REG_INT_TIMEOUT | SPI_LOCAL_OFFSET)
-+#define SPI_HIMR				(SPI_REG_HIMR | SPI_LOCAL_OFFSET)
-+#define SPI_HISR				(SPI_REG_HISR | SPI_LOCAL_OFFSET)
-+#define SPI_RX0_REQ_LEN_1_BYTE		(SPI_REG_RX0_REQ_LEN | SPI_LOCAL_OFFSET)
-+#define SPI_FREE_TXPG			(SPI_REG_FREE_TXPG | SPI_LOCAL_OFFSET)
-+
-+#define	SPI_HIMR_DISABLED				0
-+
-+/* SPI HIMR MASK diff with SDIO */
-+#define SPI_HISR_RX_REQUEST			BIT(0)
-+#define SPI_HISR_AVAL					BIT(1)
-+#define SPI_HISR_TXERR					BIT(2)
-+#define SPI_HISR_RXERR					BIT(3)
-+#define SPI_HISR_TXFOVW				BIT(4)
-+#define SPI_HISR_RXFOVW				BIT(5)
-+#define SPI_HISR_TXBCNOK				BIT(6)
-+#define SPI_HISR_TXBCNERR				BIT(7)
-+#define SPI_HISR_BCNERLY_INT			BIT(16)
-+#define SPI_HISR_ATIMEND				BIT(17)
-+#define SPI_HISR_ATIMEND_E				BIT(18)
-+#define SPI_HISR_CTWEND				BIT(19)
-+#define SPI_HISR_C2HCMD				BIT(20)
-+#define SPI_HISR_CPWM1					BIT(21)
-+#define SPI_HISR_CPWM2					BIT(22)
-+#define SPI_HISR_HSISR_IND				BIT(23)
-+#define SPI_HISR_GTINT3_IND				BIT(24)
-+#define SPI_HISR_GTINT4_IND				BIT(25)
-+#define SPI_HISR_PSTIMEOUT				BIT(26)
-+#define SPI_HISR_OCPINT					BIT(27)
-+#define SPI_HISR_TSF_BIT32_TOGGLE		BIT(29)
-+
-+#define MASK_SPI_HISR_CLEAR		(SPI_HISR_TXERR |\
-+		SPI_HISR_RXERR |\
-+		SPI_HISR_TXFOVW |\
-+		SPI_HISR_RXFOVW |\
-+		SPI_HISR_TXBCNOK |\
-+		SPI_HISR_TXBCNERR |\
-+		SPI_HISR_C2HCMD |\
-+		SPI_HISR_CPWM1 |\
-+		SPI_HISR_CPWM2 |\
-+		SPI_HISR_HSISR_IND |\
-+		SPI_HISR_GTINT3_IND |\
-+		SPI_HISR_GTINT4_IND |\
-+		SPI_HISR_PSTIMEOUT |\
-+		SPI_HISR_OCPINT)
-+
-+#define REG_LEN_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)/* (x<<(unsigned int)24) */
-+#define REG_ADDR_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)/* (x<<(unsigned int)16) */
-+#define REG_DOMAIN_ID_FORMAT(pcmd, x) 		SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */
-+#define REG_FUN_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */
-+#define REG_RW_FORMAT(pcmd, x) 				SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */
-+
-+#define FIFO_LEN_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)/* (x<<(unsigned int)24)
-+ * #define FIFO_ADDR_FORMAT(pcmd,x) 			SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x) */ /* (x<<(unsigned int)16) */
-+#define FIFO_DOMAIN_ID_FORMAT(pcmd, x) 	SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */
-+#define FIFO_FUN_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */
-+#define FIFO_RW_FORMAT(pcmd, x) 			SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */
-+
-+
-+/* get status dword0 */
-+#define GET_STATUS_PUB_PAGE_NUM(status)		LE_BITS_TO_4BYTE(status, 24, 8)
-+#define GET_STATUS_HI_PAGE_NUM(status)		LE_BITS_TO_4BYTE(status, 18, 6)
-+#define GET_STATUS_MID_PAGE_NUM(status)		LE_BITS_TO_4BYTE(status, 12, 6)
-+#define GET_STATUS_LOW_PAGE_NUM(status)		LE_BITS_TO_4BYTE(status, 6, 6)
-+#define GET_STATUS_HISR_HI6BIT(status)			LE_BITS_TO_4BYTE(status, 0, 6)
-+
-+/* get status dword1 */
-+#define GET_STATUS_HISR_MID8BIT(status)		LE_BITS_TO_4BYTE(status + 4, 24, 8)
-+#define GET_STATUS_HISR_LOW8BIT(status)		LE_BITS_TO_4BYTE(status + 4, 16, 8)
-+#define GET_STATUS_ERROR(status)				LE_BITS_TO_4BYTE(status + 4, 17, 1)
-+#define GET_STATUS_INT(status)				LE_BITS_TO_4BYTE(status + 4, 16, 1)
-+#define GET_STATUS_RX_LENGTH(status)			LE_BITS_TO_4BYTE(status + 4, 0, 16)
-+
-+
-+#define RXDESC_SIZE	24
-+
-+
-+struct spi_more_data {
-+	unsigned long more_data;
-+	unsigned long len;
-+};
-+
-+#ifdef CONFIG_RTL8188E
-+	void rtl8188es_set_hal_ops(PADAPTER padapter);
-+	#define set_hal_ops rtl8188es_set_hal_ops
-+#endif
-+extern void spi_set_chip_endian(PADAPTER padapter);
-+extern unsigned int spi_write8_endian(ADAPTER *Adapter, unsigned int addr, unsigned int buf, u32 big);
-+extern void spi_set_intf_ops(_adapter *padapter, struct _io_ops *pops);
-+extern void spi_set_chip_endian(PADAPTER padapter);
-+extern void InitInterrupt8723ASdio(PADAPTER padapter);
-+extern void InitSysInterrupt8723ASdio(PADAPTER padapter);
-+extern void EnableInterrupt8723ASdio(PADAPTER padapter);
-+extern void DisableInterrupt8723ASdio(PADAPTER padapter);
-+extern void spi_int_hdl(PADAPTER padapter);
-+extern u8 HalQueryTxBufferStatus8723ASdio(PADAPTER padapter);
-+#ifdef CONFIG_RTL8723B
-+	extern void InitInterrupt8723BSdio(PADAPTER padapter);
-+	extern void InitSysInterrupt8723BSdio(PADAPTER padapter);
-+	extern void EnableInterrupt8723BSdio(PADAPTER padapter);
-+	extern void DisableInterrupt8723BSdio(PADAPTER padapter);
-+	extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8188E
-+	extern void InitInterrupt8188EGspi(PADAPTER padapter);
-+	extern void EnableInterrupt8188EGspi(PADAPTER padapter);
-+	extern void DisableInterrupt8188EGspi(PADAPTER padapter);
-+	extern void UpdateInterruptMask8188EGspi(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
-+	extern u8 HalQueryTxBufferStatus8189EGspi(PADAPTER padapter);
-+	extern u8 HalQueryTxOQTBufferStatus8189EGspi(PADAPTER padapter);
-+	extern void ClearInterrupt8188EGspi(PADAPTER padapter);
-+	extern u8 CheckIPSStatus(PADAPTER padapter);
-+#endif /* CONFIG_RTL8188E */
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+	extern u8 RecvOnePkt(PADAPTER padapter);
-+#endif /* CONFIG_WOWLAN */
-+
-+#endif /* __GSPI_OPS_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/gspi_ops_linux.h b/drivers/staging/rtl8723cs/include/gspi_ops_linux.h
-new file mode 100644
-index 000000000000..0ba263de8fd7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/gspi_ops_linux.h
-@@ -0,0 +1,18 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __SDIO_OPS_LINUX_H__
-+#define __SDIO_OPS_LINUX_H__
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/gspi_osintf.h b/drivers/staging/rtl8723cs/include/gspi_osintf.h
-new file mode 100644
-index 000000000000..a94e656793af
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/gspi_osintf.h
-@@ -0,0 +1,19 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __SDIO_OSINTF_H__
-+#define __SDIO_OSINTF_H__
-+
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/h2clbk.h b/drivers/staging/rtl8723cs/include/h2clbk.h
-new file mode 100644
-index 000000000000..4df14b98d1e0
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/h2clbk.h
-@@ -0,0 +1,26 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+#define _H2CLBK_H_
-+
-+
-+void _lbk_cmd(PADAPTER Adapter);
-+
-+void _lbk_rsp(PADAPTER Adapter);
-+
-+void _lbk_evt(PADAPTER Adapter);
-+
-+void h2c_event_callback(unsigned char *dev, unsigned char *pbuf);
-diff --git a/drivers/staging/rtl8723cs/include/hal_btcoex.h b/drivers/staging/rtl8723cs/include/hal_btcoex.h
-new file mode 100644
-index 000000000000..a2e125ec8146
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_btcoex.h
-@@ -0,0 +1,108 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_BTCOEX_H__
-+#define __HAL_BTCOEX_H__
-+
-+#include <drv_types.h>
-+
-+/* Some variables can't get from outsrc BT-Coex,
-+ * so we need to save here */
-+typedef struct _BT_COEXIST {
-+	u8 bBtExist;
-+	u8 btTotalAntNum;
-+	u8 btChipType;
-+	u8 bInitlized;
-+	u8 btAntisolation;
-+} BT_COEXIST, *PBT_COEXIST;
-+
-+void DBG_BT_INFO(u8 *dbgmsg);
-+
-+void hal_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist);
-+u8 hal_btcoex_IsBtExist(PADAPTER padapter);
-+u8 hal_btcoex_IsBtDisabled(PADAPTER);
-+void hal_btcoex_SetChipType(PADAPTER padapter, u8 chipType);
-+void hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum);
-+
-+u8 hal_btcoex_Initialize(PADAPTER padapter);
-+void hal_btcoex_PowerOnSetting(PADAPTER padapter);
-+void hal_btcoex_AntInfoSetting(PADAPTER padapter);
-+void hal_btcoex_PowerOffSetting(PADAPTER padapter);
-+void hal_btcoex_PreLoadFirmware(PADAPTER padapter);
-+void hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly);
-+
-+void hal_btcoex_IpsNotify(PADAPTER padapter, u8 type);
-+void hal_btcoex_LpsNotify(PADAPTER padapter, u8 type);
-+void hal_btcoex_ScanNotify(PADAPTER padapter, u8 type);
-+void hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action);
-+void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus);
-+void hal_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType);
-+void hal_btcoex_IQKNotify(PADAPTER padapter, u8 state);
-+void hal_btcoex_WLRFKNotify(PADAPTER padapter, u8 path, u8 type, u8 state);
-+void hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf);
-+void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf);
-+void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state);
-+void hal_btcoex_HaltNotify(PADAPTER padapter, u8 do_halt);
-+void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter);
-+
-+void hal_btcoex_Hanlder(PADAPTER padapter);
-+
-+s32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter);
-+s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter);
-+u32 hal_btcoex_GetAMPDUSize(PADAPTER padapter);
-+void hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual);
-+void hal_btcoex_set_policy_control(PADAPTER padapter, u8 btc_policy);
-+u8 hal_btcoex_1Ant(PADAPTER padapter);
-+u8 hal_btcoex_IsBtControlLps(PADAPTER);
-+u8 hal_btcoex_IsLpsOn(PADAPTER);
-+u8 hal_btcoex_RpwmVal(PADAPTER);
-+u8 hal_btcoex_LpsVal(PADAPTER);
-+u32 hal_btcoex_GetRaMask(PADAPTER);
-+u8 hal_btcoex_query_reduced_wl_pwr_lvl(PADAPTER padapter);
-+void hal_btcoex_set_reduced_wl_pwr_lvl(PADAPTER padapter, u8 val);
-+void hal_btcoex_do_reduce_wl_pwr_lvl(PADAPTER padapter);
-+void hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen);
-+void hal_btcoex_DisplayBtCoexInfo(PADAPTER, u8 *pbuf, u32 bufsize);
-+void hal_btcoex_SetDBG(PADAPTER, u32 *pDbgModule);
-+u32 hal_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize);
-+u8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER);
-+u8 hal_btcoex_IsBtLinkExist(PADAPTER);
-+void hal_btcoex_SetBtPatchVersion(PADAPTER, u16 btHciVer, u16 btPatchVer);
-+void hal_btcoex_SetHciVersion(PADAPTER, u16 hciVersion);
-+void hal_btcoex_SendScanNotify(PADAPTER, u8 type);
-+void hal_btcoex_StackUpdateProfileInfo(void);
-+void hal_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON);
-+void hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype);
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+	int hal_btcoex_AntIsolationConfig_ParaFile(PADAPTER	Adapter, char *pFileName);
-+	int hal_btcoex_ParseAntIsolationConfigFile(PADAPTER Adapter, char	*buffer);
-+#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
-+u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data);
-+u16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val);
-+void hal_btcoex_set_rfe_type(u8 type);
-+void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type);
-+void hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length);
-+void hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id);
-+u16 hal_btcoex_btset_testode(PADAPTER padapter, u8 type);
-+
-+#ifdef CONFIG_RF4CE_COEXIST
-+void hal_btcoex_set_rf4ce_link_state(u8 state);
-+u8 hal_btcoex_get_rf4ce_link_state(void);
-+#endif
-+
-+#ifdef CONFIG_SDIO_HCI
-+#include <hal_sdio_coex.h>	/* sdio multi coex */
-+#endif
-+
-+#endif /* !__HAL_BTCOEX_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/hal_btcoex_wifionly.h b/drivers/staging/rtl8723cs/include/hal_btcoex_wifionly.h
-new file mode 100644
-index 000000000000..407698baa3dc
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_btcoex_wifionly.h
-@@ -0,0 +1,89 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HALBTC_WIFIONLY_H__
-+#define __HALBTC_WIFIONLY_H__
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+/* Define the ICs that support wifi only cfg in coex. codes */
-+#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) \
-+|| defined(CONFIG_RTL8723F)
-+#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 1
-+#else
-+#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 0
-+#endif
-+
-+/* Define the ICs that support hal btc common file structure */
-+#if defined(CONFIG_RTL8822C) || (defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8723F)&& defined(CONFIG_BT_COEXIST))
-+#define CONFIG_BTCOEX_SUPPORT_BTC_CMN 1
-+#else
-+#define CONFIG_BTCOEX_SUPPORT_BTC_CMN 0
-+#endif
-+
-+#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)
-+
-+typedef enum _WIFIONLY_CHIP_INTERFACE {
-+	WIFIONLY_INTF_UNKNOWN	= 0,
-+	WIFIONLY_INTF_PCI		= 1,
-+	WIFIONLY_INTF_USB		= 2,
-+	WIFIONLY_INTF_SDIO		= 3,
-+	WIFIONLY_INTF_MAX
-+} WIFIONLY_CHIP_INTERFACE, *PWIFIONLY_CHIP_INTERFACE;
-+
-+typedef enum _WIFIONLY_CUSTOMER_ID {
-+	CUSTOMER_NORMAL			= 0,
-+	CUSTOMER_HP_1			= 1
-+} WIFIONLY_CUSTOMER_ID, *PWIFIONLY_CUSTOMER_ID;
-+
-+struct wifi_only_haldata {
-+	u16		customer_id;
-+	u8		efuse_pg_antnum;
-+	u8		efuse_pg_antpath;
-+	u8		rfe_type;
-+	u8		ant_div_cfg;
-+};
-+
-+struct wifi_only_cfg {
-+	void *Adapter;
-+	struct wifi_only_haldata	haldata_info;
-+	WIFIONLY_CHIP_INTERFACE	chip_interface;
-+};
-+
-+void halwifionly_write1byte(void *pwifionlyContext, u32 RegAddr, u8 Data);
-+void halwifionly_write2byte(void *pwifionlyContext, u32 RegAddr, u16 Data);
-+void halwifionly_write4byte(void *pwifionlyContext, u32 RegAddr, u32 Data);
-+u8 halwifionly_read1byte(void *pwifionlyContext, u32 RegAddr);
-+u16 halwifionly_read2byte(void *pwifionlyContext, u32 RegAddr);
-+u32 halwifionly_read4byte(void *pwifionlyContext, u32 RegAddr);
-+void halwifionly_bitmaskwrite1byte(void *pwifionlyContext, u32 regAddr, u8 bitMask, u8 data);
-+void halwifionly_phy_set_rf_reg(void *pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
-+void halwifionly_phy_set_bb_reg(void *pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data);
-+void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter);
-+void hal_btcoex_wifionly_scan_notify(PADAPTER padapter);
-+void hal_btcoex_wifionly_connect_notify(PADAPTER padapter);
-+void hal_btcoex_wifionly_hw_config(PADAPTER padapter);
-+void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter);
-+void hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter);
-+#else
-+#define hal_btcoex_wifionly_switchband_notify(padapter)
-+#define hal_btcoex_wifionly_scan_notify(padapter)
-+#define hal_btcoex_wifionly_connect_notify(padapter)
-+#define hal_btcoex_wifionly_hw_config(padapter)
-+#define hal_btcoex_wifionly_initlizevariables(padapter)
-+#define hal_btcoex_wifionly_AntInfoSetting(padapter)
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/hal_com.h b/drivers/staging/rtl8723cs/include/hal_com.h
-new file mode 100644
-index 000000000000..dcafbafd8b1b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_com.h
-@@ -0,0 +1,736 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_COMMON_H__
-+#define __HAL_COMMON_H__
-+
-+#include "HalVerDef.h"
-+#include "hal_pg.h"
-+#include "hal_phy.h"
-+#include "hal_phy_reg.h"
-+#include "hal_com_reg.h"
-+#include "hal_com_phycfg.h"
-+#include "../hal/hal_com_c2h.h"
-+
-+/*------------------------------ Tx Desc definition Macro ------------------------*/
-+/* #pragma mark -- Tx Desc related definition. -- */
-+/* ----------------------------------------------------------------------------
-+ * -----------------------------------------------------------
-+ *	Rate
-+ * -----------------------------------------------------------
-+ * CCK Rates, TxHT = 0 */
-+#define DESC_RATE1M					0x00
-+#define DESC_RATE2M					0x01
-+#define DESC_RATE5_5M				0x02
-+#define DESC_RATE11M				0x03
-+
-+/* OFDM Rates, TxHT = 0 */
-+#define DESC_RATE6M					0x04
-+#define DESC_RATE9M					0x05
-+#define DESC_RATE12M				0x06
-+#define DESC_RATE18M				0x07
-+#define DESC_RATE24M				0x08
-+#define DESC_RATE36M				0x09
-+#define DESC_RATE48M				0x0a
-+#define DESC_RATE54M				0x0b
-+
-+/* MCS Rates, TxHT = 1 */
-+#define DESC_RATEMCS0				0x0c
-+#define DESC_RATEMCS1				0x0d
-+#define DESC_RATEMCS2				0x0e
-+#define DESC_RATEMCS3				0x0f
-+#define DESC_RATEMCS4				0x10
-+#define DESC_RATEMCS5				0x11
-+#define DESC_RATEMCS6				0x12
-+#define DESC_RATEMCS7				0x13
-+#define DESC_RATEMCS8				0x14
-+#define DESC_RATEMCS9				0x15
-+#define DESC_RATEMCS10				0x16
-+#define DESC_RATEMCS11				0x17
-+#define DESC_RATEMCS12				0x18
-+#define DESC_RATEMCS13				0x19
-+#define DESC_RATEMCS14				0x1a
-+#define DESC_RATEMCS15				0x1b
-+#define DESC_RATEMCS16				0x1C
-+#define DESC_RATEMCS17				0x1D
-+#define DESC_RATEMCS18				0x1E
-+#define DESC_RATEMCS19				0x1F
-+#define DESC_RATEMCS20				0x20
-+#define DESC_RATEMCS21				0x21
-+#define DESC_RATEMCS22				0x22
-+#define DESC_RATEMCS23				0x23
-+#define DESC_RATEMCS24				0x24
-+#define DESC_RATEMCS25				0x25
-+#define DESC_RATEMCS26				0x26
-+#define DESC_RATEMCS27				0x27
-+#define DESC_RATEMCS28				0x28
-+#define DESC_RATEMCS29				0x29
-+#define DESC_RATEMCS30				0x2A
-+#define DESC_RATEMCS31				0x2B
-+#define DESC_RATEVHTSS1MCS0		0x2C
-+#define DESC_RATEVHTSS1MCS1		0x2D
-+#define DESC_RATEVHTSS1MCS2		0x2E
-+#define DESC_RATEVHTSS1MCS3		0x2F
-+#define DESC_RATEVHTSS1MCS4		0x30
-+#define DESC_RATEVHTSS1MCS5		0x31
-+#define DESC_RATEVHTSS1MCS6		0x32
-+#define DESC_RATEVHTSS1MCS7		0x33
-+#define DESC_RATEVHTSS1MCS8		0x34
-+#define DESC_RATEVHTSS1MCS9		0x35
-+#define DESC_RATEVHTSS2MCS0		0x36
-+#define DESC_RATEVHTSS2MCS1		0x37
-+#define DESC_RATEVHTSS2MCS2		0x38
-+#define DESC_RATEVHTSS2MCS3		0x39
-+#define DESC_RATEVHTSS2MCS4		0x3A
-+#define DESC_RATEVHTSS2MCS5		0x3B
-+#define DESC_RATEVHTSS2MCS6		0x3C
-+#define DESC_RATEVHTSS2MCS7		0x3D
-+#define DESC_RATEVHTSS2MCS8		0x3E
-+#define DESC_RATEVHTSS2MCS9		0x3F
-+#define DESC_RATEVHTSS3MCS0		0x40
-+#define DESC_RATEVHTSS3MCS1		0x41
-+#define DESC_RATEVHTSS3MCS2		0x42
-+#define DESC_RATEVHTSS3MCS3		0x43
-+#define DESC_RATEVHTSS3MCS4		0x44
-+#define DESC_RATEVHTSS3MCS5		0x45
-+#define DESC_RATEVHTSS3MCS6		0x46
-+#define DESC_RATEVHTSS3MCS7		0x47
-+#define DESC_RATEVHTSS3MCS8		0x48
-+#define DESC_RATEVHTSS3MCS9		0x49
-+#define DESC_RATEVHTSS4MCS0		0x4A
-+#define DESC_RATEVHTSS4MCS1		0x4B
-+#define DESC_RATEVHTSS4MCS2		0x4C
-+#define DESC_RATEVHTSS4MCS3		0x4D
-+#define DESC_RATEVHTSS4MCS4		0x4E
-+#define DESC_RATEVHTSS4MCS5		0x4F
-+#define DESC_RATEVHTSS4MCS6		0x50
-+#define DESC_RATEVHTSS4MCS7		0x51
-+#define DESC_RATEVHTSS4MCS8		0x52
-+#define DESC_RATEVHTSS4MCS9		0x53
-+#define DESC_RATE_NUM			0x54
-+
-+#define IS_CCK_HRATE(_rate)		((_rate) <= DESC_RATE11M)
-+#define IS_OFDM_HRATE(_rate)	((_rate) >= DESC_RATE6M && (_rate) <= DESC_RATE54M)
-+#define IS_LEGACY_HRATE(_rate)	((_rate) <= DESC_RATE54M)
-+#define IS_HT_HRATE(_rate)		((_rate) >= DESC_RATEMCS0 && (_rate) <= DESC_RATEMCS31)
-+#define IS_VHT_HRATE(_rate)		((_rate) >= DESC_RATEVHTSS1MCS0 && (_rate) <= DESC_RATEVHTSS4MCS9)
-+
-+#define IS_HT1SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS0 && (_rate) <= DESC_RATEMCS7)
-+#define IS_HT2SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS8 && (_rate) <= DESC_RATEMCS15)
-+#define IS_HT3SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS16 && (_rate) <= DESC_RATEMCS23)
-+#define IS_HT4SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS24 && (_rate) <= DESC_RATEMCS31)
-+
-+#define IS_VHT1SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS1MCS0 && (_rate) <= DESC_RATEVHTSS1MCS9)
-+#define IS_VHT2SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS2MCS0 && (_rate) <= DESC_RATEVHTSS2MCS9)
-+#define IS_VHT3SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS3MCS0 && (_rate) <= DESC_RATEVHTSS3MCS9)
-+#define IS_VHT4SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS4MCS0 && (_rate) <= DESC_RATEVHTSS4MCS9)
-+
-+#define IS_1SS_HRATE(_rate)	(IS_CCK_HRATE((_rate)) || IS_OFDM_HRATE((_rate)) || IS_HT1SS_HRATE((_rate)) || IS_VHT1SS_HRATE((_rate)))
-+#define IS_2SS_HRATE(_rate)	(IS_HT2SS_HRATE((_rate)) || IS_VHT2SS_HRATE((_rate)))
-+#define IS_3SS_HRATE(_rate)	(IS_HT3SS_HRATE((_rate)) || IS_VHT3SS_HRATE((_rate)))
-+#define IS_4SS_HRATE(_rate)	(IS_HT4SS_HRATE((_rate)) || IS_VHT4SS_HRATE((_rate)))
-+
-+#define HRARE_SS_NUM(_rate) (IS_1SS_HRATE(_rate) ? 1 : (IS_2SS_HRATE(_rate) ? 2 : (IS_3SS_HRATE(_rate) ? 3 : (IS_4SS_HRATE(_rate) ? 4 : 0))))
-+
-+extern const char * const _HDATA_RATE[];
-+#define HDATA_RATE(rate) ((rate) >= DESC_RATE_NUM ? _HDATA_RATE[DESC_RATE_NUM] : _HDATA_RATE[rate])
-+
-+enum {
-+	UP_LINK,
-+	DOWN_LINK,
-+};
-+typedef enum _RT_MEDIA_STATUS {
-+	RT_MEDIA_DISCONNECT = 0,
-+	RT_MEDIA_CONNECT       = 1
-+} RT_MEDIA_STATUS;
-+
-+#define MAX_DLFW_PAGE_SIZE			4096	/* @ page : 4k bytes */
-+typedef enum _FIRMWARE_SOURCE {
-+	FW_SOURCE_IMG_FILE = 0,
-+	FW_SOURCE_HEADER_FILE = 1,		/* from header file */
-+} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
-+
-+typedef enum _CH_SW_USE_CASE {
-+	CH_SW_USE_CASE_TDLS		= 0,
-+	CH_SW_USE_CASE_MCC		= 1
-+} CH_SW_USE_CASE;
-+
-+typedef enum _WAKEUP_REASON{
-+	RX_PAIRWISEKEY					= 0x01,
-+	RX_GTK							= 0x02,
-+	RX_FOURWAY_HANDSHAKE			= 0x03,
-+	RX_DISASSOC						= 0x04,
-+	RX_DEAUTH						= 0x08,
-+	RX_ARP_REQUEST					= 0x09,
-+	FW_DECISION_DISCONNECT			= 0x10,
-+	RX_MAGIC_PKT					= 0x21,
-+	RX_UNICAST_PKT					= 0x22,
-+	RX_PATTERN_PKT					= 0x23,
-+	RTD3_SSID_MATCH					= 0x24,
-+	RX_REALWOW_V2_WAKEUP_PKT		= 0x30,
-+	RX_REALWOW_V2_ACK_LOST			= 0x31,
-+	ENABLE_FAIL_DMA_IDLE			= 0x40,
-+	ENABLE_FAIL_DMA_PAUSE			= 0x41,
-+	RTIME_FAIL_DMA_IDLE				= 0x42,
-+	RTIME_FAIL_DMA_PAUSE			= 0x43,
-+	RX_PNO							= 0x55,
-+	#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+	WOW_KEEPALIVE_ACK_TIMEOUT	= 0x60,
-+	WOW_KEEPALIVE_WAKE 			= 0x61,
-+	#endif/*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+	AP_OFFLOAD_WAKEUP				= 0x66,
-+	CLK_32K_UNLOCK					= 0xFD,
-+	CLK_32K_LOCK					= 0xFE
-+}WAKEUP_REASON;
-+
-+typedef enum _BCN_EARLY_INT_CASE{
-+	TDLS_BCN_ERLY_ON,
-+	TDLS_BCN_ERLY_OFF
-+}BCN_EARLY_INT_CASE;
-+
-+/*
-+ * Queue Select Value in TxDesc
-+ *   */
-+#define QSLT_BK							0x2/* 0x01 */
-+#define QSLT_BE							0x0
-+#define QSLT_VI							0x5/* 0x4 */
-+#define QSLT_VO							0x7/* 0x6 */
-+#define QSLT_BEACON						0x10
-+#define QSLT_HIGH						0x11
-+#define QSLT_MGNT						0x12
-+#define QSLT_CMD						0x13
-+
-+/* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
-+ * #define MAX_TX_QUEUE		9 */
-+
-+#define TX_SELE_HQ			BIT(0)		/* High Queue */
-+#define TX_SELE_LQ			BIT(1)		/* Low Queue */
-+#define TX_SELE_NQ			BIT(2)		/* Normal Queue */
-+#define TX_SELE_EQ			BIT(3)		/* Extern Queue */
-+
-+#define PageNum_128(_Len)		(u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
-+#define PageNum_256(_Len)		(u32)(((_Len)>>8) + ((_Len) & 0xFF ? 1 : 0))
-+#define PageNum_512(_Len)		(u32)(((_Len)>>9) + ((_Len) & 0x1FF ? 1 : 0))
-+#define PageNum(_Len, _Size)		(u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1 : 0))
-+
-+struct dbg_rx_counter {
-+	u32	rx_pkt_ok;
-+	u32	rx_pkt_crc_error;
-+	u32	rx_pkt_drop;
-+	u32	rx_ofdm_fa;
-+	u32	rx_cck_fa;
-+	u32	rx_ht_fa;
-+};
-+
-+u8 rtw_hal_get_port(_adapter *adapter);
-+
-+#ifdef CONFIG_MBSSID_CAM
-+	/*#define DBG_MBID_CAM_DUMP*/
-+
-+	void rtw_mbid_cam_init(struct dvobj_priv *dvobj);
-+	void rtw_mbid_cam_deinit(struct dvobj_priv *dvobj);
-+	void rtw_mbid_cam_reset(_adapter *adapter);
-+	u8 rtw_get_max_mbid_cam_id(_adapter *adapter);
-+	u8 rtw_get_mbid_cam_entry_num(_adapter *adapter);
-+	int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name , _adapter *adapter);
-+	int rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter);
-+	void rtw_mi_set_mbid_cam(_adapter *adapter);
-+	u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr);
-+	void rtw_ap_set_mbid_num(_adapter *adapter, u8 ap_num);
-+	void rtw_mbid_cam_enable(_adapter *adapter);
-+#endif
-+
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+	void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr);
-+	void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr);
-+	#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+	u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval);
-+	#endif
-+	void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode);
-+#endif
-+
-+void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
-+void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
-+void rtw_reset_mac_rx_counters(_adapter *padapter);
-+void rtw_reset_phy_rx_counters(_adapter *padapter);
-+void rtw_reset_phy_trx_ok_counters(_adapter *padapter);
-+
-+#ifdef DBG_RX_COUNTER_DUMP
-+	#define DUMP_DRV_RX_COUNTER	BIT0
-+	#define DUMP_MAC_RX_COUNTER	BIT1
-+	#define DUMP_PHY_RX_COUNTER	BIT2
-+	#define DUMP_DRV_TRX_COUNTER_DATA	BIT3
-+
-+	void rtw_dump_phy_rxcnts_preprocess(_adapter *padapter, u8 rx_cnt_mode);
-+	void rtw_dump_rx_counters(_adapter *padapter);
-+#endif
-+
-+void dump_chip_info(HAL_VERSION	ChipVersion);
-+
-+#define BAND_CAP_2G			BIT0
-+#define BAND_CAP_5G			BIT1
-+#define BAND_CAP_BIT_NUM	2
-+
-+#define BW_CAP_5M		BIT0
-+#define BW_CAP_10M		BIT1
-+#define BW_CAP_20M		BIT2
-+#define BW_CAP_40M		BIT3
-+#define BW_CAP_80M		BIT4
-+#define BW_CAP_160M		BIT5
-+#define BW_CAP_80_80M	BIT6
-+#define BW_CAP_BIT_NUM	7
-+
-+#define PROTO_CAP_11B		BIT0
-+#define PROTO_CAP_11G		BIT1
-+#define PROTO_CAP_11N		BIT2
-+#define PROTO_CAP_11AC		BIT3
-+#define PROTO_CAP_BIT_NUM	4
-+
-+#define WL_FUNC_P2P			BIT0
-+#define WL_FUNC_MIRACAST	BIT1
-+#define WL_FUNC_TDLS		BIT2
-+#define WL_FUNC_FTM			BIT3
-+#define WL_FUNC_BIT_NUM		4
-+
-+#define TBTT_PROHIBIT_SETUP_TIME 0x04 /* 128us, unit is 32us */
-+#define TBTT_PROHIBIT_HOLD_TIME 0x80 /* 4ms, unit is 32us*/
-+#define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 /* 3.2ms unit is 32us*/
-+
-+int hal_spec_init(_adapter *adapter);
-+void dump_hal_spec(void *sel, _adapter *adapter);
-+
-+bool hal_chk_band_cap(_adapter *adapter, u8 cap);
-+bool hal_chk_bw_cap(_adapter *adapter, u8 cap);
-+bool hal_chk_proto_cap(_adapter *adapter, u8 cap);
-+bool hal_is_band_support(_adapter *adapter, u8 band);
-+bool hal_is_bw_support(_adapter *adapter, u8 bw);
-+bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode);
-+bool hal_is_mimo_support(_adapter *adapter);
-+u8 hal_largest_bw(_adapter *adapter, u8 in_bw);
-+
-+bool hal_chk_wl_func(_adapter *adapter, u8 func);
-+
-+void hal_com_config_channel_plan(
-+		PADAPTER padapter,
-+		char *hw_alpha2,
-+		u8 hw_chplan,
-+		char *sw_alpha2,
-+		u8 sw_chplan,
-+		BOOLEAN AutoLoadFail
-+);
-+
-+int hal_config_macaddr(_adapter *adapter, bool autoload_fail);
-+#ifdef RTW_HALMAC
-+void rtw_hal_hw_port_enable(_adapter *adapter);
-+void rtw_hal_hw_port_disable(_adapter *adapter);
-+#endif
-+
-+BOOLEAN
-+HAL_IsLegalChannel(
-+		PADAPTER	Adapter,
-+		u32			Channel
-+);
-+
-+u8 MRateToHwRate(enum MGN_RATE rate);
-+
-+u8 hw_rate_to_m_rate(u8 hw_rate);
-+#ifdef CONFIG_RTW_DEBUG
-+void dump_hw_rate_map_test(void *sel);
-+#endif
-+
-+void	HalSetBrateCfg(
-+		PADAPTER		Adapter,
-+		u8			*mBratesOS,
-+		u16			*pBrateCfg);
-+
-+BOOLEAN
-+Hal_MappingOutPipe(
-+		PADAPTER	pAdapter,
-+		u8		NumOutPipe
-+);
-+
-+void rtw_dump_fw_info(void *sel, _adapter *adapter);
-+void rtw_restore_hw_port_cfg(_adapter *adapter);
-+void rtw_mi_set_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/
-+void rtw_hal_dump_macaddr(void *sel, _adapter *adapter);
-+
-+void rtw_init_hal_com_default_value(PADAPTER Adapter);
-+
-+#ifdef CONFIG_FW_C2H_REG
-+void c2h_evt_clear(_adapter *adapter);
-+s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf);
-+#endif
-+
-+#ifdef CONFIG_FW_C2H_PKT
-+void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len);
-+void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len);
-+#endif
-+
-+u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type);
-+
-+void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta);
-+s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta);
-+s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta);
-+void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta);
-+
-+/* access HW only */
-+u32 rtw_sec_read_cam(_adapter *adapter, u8 addr);
-+void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata);
-+void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key);
-+void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
-+void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id);
-+bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id);
-+
-+u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit);
-+
-+u8 rtw_hal_rcr_add(_adapter *adapter, u32 add);
-+u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear);
-+void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action);
-+void rtw_hal_rcr_set_chk_bssid_act_non(_adapter *adapter);
-+
-+void rtw_iface_enable_tsf_update(_adapter *adapter);
-+void rtw_iface_disable_tsf_update(_adapter *adapter);
-+void rtw_hal_periodic_tsf_update_chk(_adapter *adapter);
-+void rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx);
-+
-+#if CONFIG_TX_AC_LIFETIME
-+#define TX_ACLT_CONF_DEFAULT	0
-+#define TX_ACLT_CONF_AP_M2U		1
-+#define TX_ACLT_CONF_MESH		2
-+#define TX_ACLT_CONF_NUM		3
-+
-+extern const char *const _tx_aclt_conf_str[];
-+#define tx_aclt_conf_str(conf) (((conf) >= TX_ACLT_CONF_NUM) ? _tx_aclt_conf_str[TX_ACLT_CONF_NUM] : _tx_aclt_conf_str[(conf)])
-+
-+struct tx_aclt_conf_t {
-+	u8 en;
-+	u32 vo_vi;
-+	u32 be_bk;
-+};
-+
-+void dump_tx_aclt_force_val(void *sel, struct dvobj_priv *dvobj);
-+void rtw_hal_set_tx_aclt_force_val(_adapter *adapter, struct tx_aclt_conf_t *input, u8 arg_num);
-+void dump_tx_aclt_confs(void *sel, struct dvobj_priv *dvobj);
-+void rtw_hal_set_tx_aclt_conf(_adapter *adapter, u8 conf_idx, struct tx_aclt_conf_t *input, u8 arg_num);
-+void rtw_hal_update_tx_aclt(_adapter *adapter);
-+#endif
-+
-+void hw_var_port_switch(_adapter *adapter);
-+void rtw_var_set_basic_rate(PADAPTER padapter, u8 *val);
-+u8 SetHwReg(PADAPTER padapter, u8 variable, u8 *val);
-+void GetHwReg(PADAPTER padapter, u8 variable, u8 *val);
-+void rtw_hal_check_rxfifo_full(_adapter *adapter);
-+void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid);
-+
-+u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
-+u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
-+
-+u32
-+MapCharToHexDigit(
-+		char	chTmp
-+);
-+
-+BOOLEAN
-+GetHexValueFromString(
-+			char		*szStr,
-+			u32			*pu4bVal,
-+			u32			*pu4bMove
-+);
-+
-+BOOLEAN
-+GetFractionValueFromString(
-+			char	*szStr,
-+			u8		*pInteger,
-+			u8		*pFraction,
-+			u32		*pu4bMove
-+);
-+
-+BOOLEAN
-+IsCommentString(
-+			char		*szStr
-+);
-+
-+BOOLEAN
-+ParseQualifiedString(
-+		char *In,
-+		u32 *Start,
-+		char *Out,
-+		char LeftQualifier,
-+		char RightQualifier
-+);
-+
-+BOOLEAN
-+GetU1ByteIntegerFromStringInDecimal(
-+			char *Str,
-+			u8 *pInt
-+);
-+
-+BOOLEAN
-+isAllSpaceOrTab(
-+	u8	*data,
-+	u8	size
-+);
-+
-+void linked_info_dump(_adapter *padapter, u8 benable);
-+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
-+	void rtw_get_raw_rssi_info(void *sel, _adapter *padapter);
-+	void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel);
-+#endif
-+
-+#ifdef DBG_RX_DFRAME_RAW_DATA
-+	void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel);
-+#endif
-+void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe);
-+#define		HWSET_MAX_SIZE			1024
-+
-+#ifdef CONFIG_EFUSE_CONFIG_FILE
-+u32 Hal_readPGDataFromConfigFile(PADAPTER padapter);
-+u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr);
-+#endif /* CONFIG_EFUSE_CONFIG_FILE */
-+
-+int hal_efuse_macaddr_offset(_adapter *adapter);
-+int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr);
-+void rtw_dump_cur_efuse(PADAPTER padapter);
-+
-+#ifdef CONFIG_RF_POWER_TRIM
-+	void rtw_bb_rf_gain_offset(_adapter *padapter);
-+#endif /*CONFIG_RF_POWER_TRIM*/
-+
-+void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer);
-+u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel);
-+
-+u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta);
-+u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta);
-+#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
-+void rtw_hal_set_pathb_phase(_adapter *adapter, u8 phase_idx);
-+#endif
-+void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished);
-+u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter);
-+
-+#ifdef CONFIG_TSF_RESET_OFFLOAD
-+int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port);
-+#endif
-+u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port);
-+
-+#ifdef CONFIG_TDLS
-+	#ifdef CONFIG_TDLS_CH_SW
-+		s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode);
-+	#endif
-+#endif
-+#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
-+s32 rtw_hal_set_wifi_btc_port_id_cmd(_adapter *adapter);
-+#endif
-+
-+void rtw_lps_state_chk(_adapter *adapter, u8 ps_mode);
-+
-+#ifdef CONFIG_GPIO_API
-+	u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num);
-+	int rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh);
-+	int rtw_hal_config_gpio(_adapter *adapter, u8 gpio_num, bool isOutput);
-+	int rtw_hal_register_gpio_interrupt(_adapter *adapter, int gpio_num, void(*callback)(u8 level));
-+	int rtw_hal_disable_gpio_interrupt(_adapter *adapter, int gpio_num);
-+#endif
-+
-+s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode);
-+void rtw_hal_ch_sw_iqk_info_backup(_adapter *adapter);
-+void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case);
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable);
-+void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval);
-+void rtw_hal_set_input_gpio(_adapter *padapter, u8 index);
-+#define GPIO_OUTPUT_LOW		0
-+#define GPIO_OUTPUT_HIGH	1
-+#endif
-+
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+	extern char *rtw_phy_file_path;
-+	extern char rtw_phy_para_file_path[PATH_LENGTH_MAX];
-+	#define GetLineFromBuffer(buffer)   strsep(&buffer, "\r\n")
-+#endif
-+
-+void update_IOT_info(_adapter *padapter);
-+#ifdef CONFIG_RTS_FULL_BW
-+void rtw_set_rts_bw(_adapter *padapter);
-+#endif/*CONFIG_RTS_FULL_BW*/
-+
-+void ResumeTxBeacon(_adapter *padapter);
-+void StopTxBeacon(_adapter *padapter);
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	u8	rtw_hal_antdiv_before_linked(_adapter *padapter);
-+	void	rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
-+#endif
-+
-+#ifdef DBG_SEC_CAM_MOVE
-+	void rtw_hal_move_sta_gk_to_dk(_adapter *adapter);
-+	void rtw_hal_read_sta_dk_key(_adapter *adapter, u8 key_id);
-+#endif
-+
-+#ifdef CONFIG_LPS_PG
-+#define LPSPG_RSVD_PAGE_SET_MACID(_rsvd_pag, _value)		SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 0, 8, _value)/*used macid*/
-+#define LPSPG_RSVD_PAGE_SET_MBSSCAMID(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 8, 8, _value)/*used BSSID CAM entry*/
-+#define LPSPG_RSVD_PAGE_SET_PMC_NUM(_rsvd_pag, _value)		SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 16, 8, _value)/*Max used Pattern Match CAM entry*/
-+#define LPSPG_RSVD_PAGE_SET_MU_RAID_GID(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 24, 8, _value)/*Max MU rate table Group ID*/
-+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 0, 8, _value)/*used Security CAM entry number*/
-+#define LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 8, 8, _value)/*Txbuf used page number for fw offload*/
-+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID1(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 0, 8, _value)/*used Security CAM entry -1*/
-+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID2(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 8, 8, _value)/*used Security CAM entry -2*/
-+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID3(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 16, 8, _value)/*used Security CAM entry -3*/
-+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID4(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 24, 8, _value)/*used Security CAM entry -4*/
-+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID5(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 0, 8, _value)/*used Security CAM entry -5*/
-+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID6(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 8, 8, _value)/*used Security CAM entry -6*/
-+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID7(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 16, 8, _value)/*used Security CAM entry -7*/
-+#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID8(_rsvd_pag, _value)	SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 24, 8, _value)/*used Security CAM entry -8*/
-+enum lps_pg_hdl_id {
-+	LPS_PG_INFO_CFG = 0,
-+	LPS_PG_REDLEMEM,
-+	LPS_PG_PHYDM_DIS,
-+	LPS_PG_PHYDM_EN,
-+};
-+
-+u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter);
-+u8 rtw_hal_set_lps_pg_info(_adapter *adapter);
-+#endif
-+
-+int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size);
-+void rtw_hal_construct_beacon(_adapter *padapter, u8 *pframe, u32 *pLength);
-+void rtw_hal_construct_NullFunctionData(PADAPTER, u8 *pframe, u32 *pLength,
-+				u8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave);
-+
-+bool _rtw_wow_chk_cap(_adapter *adapter, u8 cap);
-+#ifdef CONFIG_WOWLAN
-+struct rtl_wow_pattern {
-+	u16	crc;
-+	u8	type;
-+	u32	mask[4];
-+};
-+void rtw_wow_pattern_cam_dump(_adapter *adapter);
-+
-+void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx);
-+#ifdef CONFIG_WOW_PATTERN_HW_CAM
-+void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct  rtl_wow_pattern *context);
-+#endif
-+
-+struct rtw_ndp_info {
-+	u8 enable:1;
-+	u8 check_remote_ip:1; /* Need to Check Sender IP or not */
-+	u8 rsvd:6;
-+	u8 num_of_target_ip; /* Number of Check IP which NA query IP */
-+	u8 target_link_addr[6]; /* DUT's MAC address */
-+	u8 remote_ipv6_addr[16]; /* Just respond IP */
-+	u8 target_ipv6_addr[16]; /* target IP */
-+};
-+#define REMOTE_INFO_CTRL_SET_VALD_EN(target, _value) \
-+	SET_BITS_TO_LE_4BYTE(target + 0, 0, 8, _value)
-+#define REMOTE_INFO_CTRL_SET_PTK_EN(target, _value) \
-+	SET_BITS_TO_LE_4BYTE(target + 1, 0, 1, _value)
-+#define REMOTE_INFO_CTRL_SET_GTK_EN(target, _value) \
-+	SET_BITS_TO_LE_4BYTE(target + 1, 1, 1, _value)
-+#define REMOTE_INFO_CTRL_SET_GTK_IDX(target, _value) \
-+	SET_BITS_TO_LE_4BYTE(target + 2, 0, 8, _value)
-+#endif /*CONFIG_WOWLAN*/
-+
-+#ifdef CONFIG_PROC_DEBUG
-+void rtw_dump_phy_cap(void *sel, _adapter *adapter);
-+#endif
-+void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num);
-+#ifdef CONFIG_SUPPORT_FIFO_DUMP
-+void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size);
-+#endif
-+
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id);
-+s32 rtw_set_default_port_id(_adapter *adapter);
-+s32 rtw_set_ps_rsvd_page(_adapter *adapter);
-+
-+#define get_dft_portid(adapter) (adapter_to_dvobj(adapter)->dft.port_id)
-+#define get_dft_macid(adapter) (adapter_to_dvobj(adapter)->dft.mac_id)
-+
-+/*void rtw_search_default_port(_adapter *adapter);*/
-+#endif
-+
-+#ifdef CONFIG_P2P_PS
-+#ifdef RTW_HALMAC
-+void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state);
-+#endif
-+#endif
-+
-+#ifdef RTW_CHANNEL_SWITCH_OFFLOAD
-+void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw);
-+#endif
-+
-+s16 translate_dbm_to_percentage(s16 signal);
-+
-+#ifdef CONFIG_SUPPORT_MULTI_BCN
-+void rtw_ap_multi_bcn_cfg(_adapter *adapter);
-+#endif
-+
-+#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+#ifdef CONFIG_BCN_RECOVERY
-+u8 rtw_ap_bcn_recovery(_adapter *padapter);
-+#endif
-+#ifdef CONFIG_BCN_XMIT_PROTECT
-+u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms);
-+#endif
-+#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
-+
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+void rtw_ap_mbid_bcn_en(_adapter *adapter, u8 mbcn_id);
-+void rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 mbcn_id);
-+#endif
-+
-+void rtw_hal_get_trx_path(struct dvobj_priv *d, enum rf_type *type,
-+			 enum bb_path *tx, enum bb_path *rx);
-+#ifdef CONFIG_BEAMFORMING
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+void rtw_hal_beamforming_config_csirate(PADAPTER adapter);
-+#endif
-+#endif
-+
-+u8 phy_get_capable_tx_num(_adapter *adapter, enum MGN_RATE rate);
-+u8 phy_get_current_tx_num(_adapter *adapter, enum MGN_RATE rate);
-+
-+#ifdef CONFIG_RTL8812A
-+u8 * rtw_hal_set_8812a_vendor_ie(_adapter *padapter , u8 *pframe ,uint *frlen );
-+#endif
-+
-+#ifdef CONFIG_PROTSEL_PORT
-+void rtw_enter_protsel_port(_adapter *padapter, u8 port_sel);
-+bool rtw_assert_protsel_port(_adapter *padapter, u32 addr, u8 len);
-+void rtw_leave_protsel_port(_adapter *padapter);
-+#else
-+static inline void rtw_enter_protsel_port(_adapter *padapter, u8 port_sel) {}
-+static inline bool rtw_assert_protsel_port(_adapter *padapter, u32 addr, u8 len) {return true; }
-+static inline void rtw_leave_protsel_port(_adapter *padapter) {}
-+#endif
-+#ifdef CONFIG_PROTSEL_ATIMDTIM
-+void rtw_enter_protsel_atimdtim(_adapter *padapter, u8 port_sel);
-+bool rtw_assert_protsel_atimdtim(_adapter *padapter, u32 addr, u8 len);
-+void rtw_leave_protsel_atimdtim(_adapter *padapter);
-+#else
-+static inline void rtw_enter_protsel_atimdtim(_adapter *padapter, u8 port_sel) {}
-+static inline bool rtw_assert_protsel_atimdtim(_adapter *padapter, u32 addr, u8 len) {return true; }
-+static inline void rtw_leave_protsel_atimdtim(_adapter *padapter) {}
-+#endif
-+#ifdef CONFIG_PROTSEL_MACSLEEP
-+void rtw_enter_protsel_macsleep(_adapter *padapter, u8 sel);
-+bool rtw_assert_protsel_macsleep(_adapter *padapter, u32 addr, u8 len);
-+void rtw_leave_protsel_macsleep(_adapter *padapter);
-+#else
-+static inline void rtw_enter_protsel_macsleep(_adapter *padapter, u8 port_sel) {}
-+static inline bool rtw_assert_protsel_macsleep(_adapter *padapter, u32 addr, u8 len) {return true; }
-+static inline void rtw_leave_protsel_macsleep(_adapter *padapter) {}
-+#endif
-+#endif /* __HAL_COMMON_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/hal_com_h2c.h b/drivers/staging/rtl8723cs/include/hal_com_h2c.h
-new file mode 100644
-index 000000000000..c9db477b0b17
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_com_h2c.h
-@@ -0,0 +1,817 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __COMMON_H2C_H__
-+#define __COMMON_H2C_H__
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
-+ * ---------------------------------------------------------------------------------------------------------
-+ * 88e, 8723b, 8812, 8821, 92e use the same FW code base */
-+enum h2c_cmd {
-+	/* Common Class: 000 */
-+	H2C_RSVD_PAGE = 0x00,
-+	H2C_MEDIA_STATUS_RPT = 0x01,
-+	H2C_SCAN_ENABLE = 0x02,
-+	H2C_KEEP_ALIVE = 0x03,
-+	H2C_DISCON_DECISION = 0x04,
-+	H2C_PSD_OFFLOAD = 0x05,
-+	H2C_CUSTOMER_STR_REQ = 0x06,
-+	H2C_TXPWR_IDX_OFFLOAD = 0x07,
-+	H2C_AP_OFFLOAD = 0x08,
-+	H2C_BCN_RSVDPAGE = 0x09,
-+	H2C_PROBERSP_RSVDPAGE = 0x0A,
-+	H2C_FCS_RSVDPAGE = 0x10,
-+	H2C_FCS_INFO = 0x11,
-+	H2C_AP_WOW_GPIO_CTRL = 0x13,
-+#ifdef CONFIG_MCC_MODE
-+	H2C_MCC_RQT_TSF = 0x15,
-+	H2C_MCC_MACID_BITMAP = 0x16,
-+	H2C_MCC_LOCATION = 0x10,
-+	H2C_MCC_CTRL_V2 = 0x17,
-+	H2C_MCC_CTRL = 0x18,
-+	H2C_MCC_TIME_SETTING = 0x19,
-+	H2C_MCC_IQK_PARAM = 0x1A,
-+#endif /* CONFIG_MCC_MODE */
-+	H2C_CHNL_SWITCH_OPER_OFFLOAD = 0x1C,
-+	H2C_SINGLE_CHANNELSWITCH_V2 = 0x1D,
-+
-+	/* PoweSave Class: 001 */
-+	H2C_SET_PWR_MODE = 0x20,
-+	H2C_PS_TUNING_PARA = 0x21,
-+	H2C_PS_TUNING_PARA2 = 0x22,
-+	H2C_P2P_LPS_PARAM = 0x23,
-+	H2C_P2P_PS_OFFLOAD = 0x24,
-+	H2C_PS_SCAN_ENABLE = 0x25,
-+	H2C_SAP_PS_ = 0x26,
-+	H2C_INACTIVE_PS_ = 0x27, /* Inactive_PS */
-+	H2C_FWLPS_IN_IPS_ = 0x28,
-+#ifdef CONFIG_LPS_POFF
-+	H2C_LPS_POFF_CTRL = 0x29,
-+	H2C_LPS_POFF_PARAM = 0x2A,
-+#endif
-+#ifdef CONFIG_LPS_PG
-+	H2C_LPS_PG_INFO = 0x2B,
-+#endif
-+
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+	H2C_DEFAULT_PORT_ID = 0x2C,
-+#endif
-+	/* Dynamic Mechanism Class: 010 */
-+	H2C_MACID_CFG = 0x40,
-+	H2C_TXBF = 0x41,
-+	H2C_RSSI_SETTING = 0x42,
-+	H2C_AP_REQ_TXRPT = 0x43,
-+	H2C_INIT_RATE_COLLECT = 0x44,
-+	H2C_IQ_CALIBRATION	= 0x45,
-+
-+	H2C_RA_MASK_3SS = 0x46,/* for 8814A */
-+	H2C_RA_PARA_ADJUST = 0x47,/* CONFIG_RA_DBG_CMD */
-+	H2C_DYNAMIC_TX_PATH = 0x48,/* for 8814A */
-+
-+	H2C_FW_TRACE_EN = 0x49,
-+#ifdef RTW_PER_CMD_SUPPORT_FW
-+	H2C_REQ_PER_RPT = 0x4e,
-+#endif
-+	/* BT Class: 011 */
-+	H2C_B_TYPE_TDMA = 0x60,
-+	H2C_BT_INFO = 0x61,
-+	H2C_FORCE_BT_TXPWR = 0x62,
-+	H2C_BT_IGNORE_WLANACT = 0x63,
-+	H2C_DAC_SWING_VALUE = 0x64,
-+	H2C_ANT_SEL_RSV = 0x65,
-+	H2C_WL_OPMODE = 0x66,
-+	H2C_BT_MP_OPER = 0x67,
-+	H2C_BT_CONTROL = 0x68,
-+	H2C_BT_WIFI_CTRL = 0x69,
-+	H2C_BT_FW_PATCH = 0x6A,
-+#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
-+	H2C_BTC_WL_PORT_ID = 0x71,
-+#endif
-+	/* WOWLAN Class: 100 */
-+	H2C_WOWLAN = 0x80,
-+	H2C_REMOTE_WAKE_CTRL = 0x81,
-+	H2C_AOAC_GLOBAL_INFO = 0x82,
-+	H2C_AOAC_RSVD_PAGE = 0x83,
-+	H2C_AOAC_RSVD_PAGE2 = 0x84,
-+	H2C_D0_SCAN_OFFLOAD_CTRL = 0x85,
-+	H2C_D0_SCAN_OFFLOAD_INFO = 0x86,
-+	H2C_CHNL_SWITCH_OFFLOAD = 0x87,
-+	H2C_AOAC_RSVDPAGE3 = 0x88,
-+	H2C_GPIO_CUSTOM = 0x89,
-+	H2C_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
-+	H2C_P2P_OFFLOAD = 0x8B,
-+	H2C_WAR_OFFLOAD = 0x8D,
-+	H2C_WAROFLD_RSVDPAGE1 = 0x8E,
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+	H2C_UDP_KEEPALIVE = 0x90,
-+#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+	H2C_FW_BCN_OFFLOAD = 0xBA,
-+#endif
-+#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
-+	H2C_FW_CRC5_SEARCH = 0xBB,
-+#endif
-+	H2C_RESET_TSF = 0xC0,
-+#ifdef CONFIG_FW_CORRECT_BCN
-+	H2C_BCNHWSEQ = 0xC5,
-+#endif
-+	H2C_CUSTOMER_STR_W1 = 0xC6,
-+	H2C_CUSTOMER_STR_W2 = 0xC7,
-+	H2C_CUSTOMER_STR_W3 = 0xC8,
-+	H2C_BT_UNKNOWN_DEVICE_WA = 0xD1,
-+#ifdef DBG_FW_DEBUG_MSG_PKT
-+	H2C_FW_DBG_MSG_PKT = 0xE1,
-+#endif /*DBG_FW_DEBUG_MSG_PKT*/
-+	H2C_MAXID,
-+};
-+
-+#define H2C_INACTIVE_PS_LEN		4
-+#define H2C_RSVDPAGE_LOC_LEN		5
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+#define H2C_DEFAULT_PORT_ID_LEN		2
-+#define H2C_MEDIA_STATUS_RPT_LEN		4
-+#else
-+#define H2C_MEDIA_STATUS_RPT_LEN		3
-+#endif
-+#define H2C_GPIO_CUSTOM_LEN		3
-+#define H2C_KEEP_ALIVE_CTRL_LEN	2
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+#define H2C_KEEP_ALIVE_PATTERN_LEN	7
-+#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+#define H2C_DISCON_DECISION_LEN		3
-+#define H2C_AP_OFFLOAD_LEN		3
-+#define H2C_AP_WOW_GPIO_CTRL_LEN	4
-+#define H2C_AP_PS_LEN			2
-+#define H2C_PWRMODE_LEN			7
-+#define H2C_PSTUNEPARAM_LEN			4
-+#define H2C_MACID_CFG_LEN		7
-+#define H2C_BTMP_OPER_LEN			5
-+#define H2C_WOWLAN_LEN			7
-+#define H2C_REMOTE_WAKE_CTRL_LEN	3
-+#define H2C_AOAC_GLOBAL_INFO_LEN	2
-+#define H2C_AOAC_RSVDPAGE_LOC_LEN	7
-+#define H2C_SCAN_OFFLOAD_CTRL_LEN	4
-+#define H2C_BT_FW_PATCH_LEN			6
-+#define H2C_RSSI_SETTING_LEN		4
-+#define H2C_AP_REQ_TXRPT_LEN		3
-+#define H2C_FORCE_BT_TXPWR_LEN		3
-+#define H2C_BCN_RSVDPAGE_LEN		5
-+#define H2C_PROBERSP_RSVDPAGE_LEN	5
-+#define H2C_P2PRSVDPAGE_LOC_LEN	5
-+#define H2C_P2P_OFFLOAD_LEN	3
-+#ifdef CONFIG_MCC_MODE
-+	#define H2C_MCC_CTRL_LEN			7
-+#ifdef CONFIG_MCC_MODE_V2
-+	#define H2C_MCC_LOCATION_LEN		7
-+#else
-+	#define H2C_MCC_LOCATION_LEN		3
-+#endif
-+	#define H2C_MCC_MACID_BITMAP_LEN	6
-+	#define H2C_MCC_RQT_TSF_LEN		1
-+	#define H2C_MCC_TIME_SETTING_LEN		6
-+	#define H2C_MCC_IQK_PARAM_LEN		7
-+#endif /* CONFIG_MCC_MODE */
-+#ifdef CONFIG_LPS_PG
-+#ifdef CONFIG_RTL8822C
-+	#define H2C_LPS_PG_INFO_LEN		4
-+#else
-+	#define H2C_LPS_PG_INFO_LEN		2
-+#endif
-+	#define H2C_LPSPG_LEN			16
-+#endif
-+#ifdef CONFIG_LPS_POFF
-+	#define H2C_LPS_POFF_CTRL_LEN		1
-+	#define H2C_LPS_POFF_PARAM_LEN		5
-+#endif
-+
-+#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
-+#define H2C_BTC_WL_PORT_ID_LEN	1
-+#endif
-+
-+#ifdef DBG_FW_DEBUG_MSG_PKT
-+	#define H2C_FW_DBG_MSG_PKT_LEN	2
-+#endif /*DBG_FW_DEBUG_MSG_PKT*/
-+
-+#define H2C_SINGLE_CHANNELSWITCH_V2_LEN 3
-+#define H2C_BT_UNKNOWN_DEVICE_WA_LEN 1
-+
-+#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
-+#define H2C_FW_CRC5_SEARCH_LEN	7
-+#endif
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+#define	H2C_WAR_OFFLOAD_LEN			3
-+#define	H2C_WAROFLD_RSVDPAGE1_LEN	6
-+#endif /* CONFIG_WAR_OFFLOAD */
-+
-+
-+#define eq_mac_addr(a, b)						(((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0)
-+#define cp_mac_addr(des, src)					((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5])
-+#define cpIpAddr(des, src)					((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3])
-+#define cpIpv6Addr(des, src)                                   ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5], (des)[6] = (src)[6], (des)[7] = (src)[7], (des)[8] = (src)[8], (des)[9] = (src)[9], (des)[10] = (src)[10], (des)[11] = (src)[11], (des)[12] = (src)[12], (des)[13] = (src)[13], (des)[14] = (src)[14], (des)[15] = (src)[15])
-+
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+#define FW_WOWLAN_FUN_EN				BIT(0)
-+#define FW_WOWLAN_PATTERN_MATCH			BIT(1)
-+#define FW_WOWLAN_MAGIC_PKT				BIT(2)
-+#define FW_WOWLAN_UNICAST				BIT(3)
-+#define FW_WOWLAN_ALL_PKT_DROP			BIT(4)
-+#define FW_WOWLAN_GPIO_ACTIVE			BIT(5)
-+#define FW_WOWLAN_REKEY_WAKEUP			BIT(6)
-+#define FW_WOWLAN_DEAUTH_WAKEUP			BIT(7)
-+
-+#define FW_WOWLAN_GPIO_WAKEUP_EN		BIT(0)
-+#define FW_FW_PARSE_MAGIC_PKT			BIT(1)
-+
-+#define FW_REMOTE_WAKE_CTRL_EN			BIT(0)
-+#define FW_REALWOWLAN_EN				BIT(5)
-+
-+#define FW_WOWLAN_KEEP_ALIVE_EN			BIT(0)
-+#define FW_ADOPT_USER					BIT(1)
-+#define FW_WOWLAN_KEEP_ALIVE_PKT_TYPE	BIT(2)
-+
-+#define FW_REMOTE_WAKE_CTRL_EN			BIT(0)
-+#define FW_ARP_EN						BIT(1)
-+#define FW_REALWOWLAN_EN				BIT(5)
-+#define FW_WOW_FW_UNICAST_EN			BIT(7)
-+
-+#define FW_IPS_DISABLE_BBRF		BIT(0)
-+#define FW_IPS_WRC				BIT(1)
-+
-+#endif /* CONFIG_WOWLAN */
-+
-+/* _RSVDPAGE_LOC_CMD_0x00 */
-+#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+/* _MEDIA_STATUS_RPT_PARM_CMD_0x01 */
-+#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
-+#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 1, 1, (__Value))
-+#define SET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 2, 1, (__Value))
-+#define SET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 3, 1, (__Value))
-+#define SET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 4, 4, (__Value))
-+#define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value))
-+#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 2, 0, 8, (__Value))
-+#define SET_H2CCMD_MSRRPT_PARM_PORT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 3, 0, 3, (__Value))
-+
-+#define GET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd)		LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 0, 1)
-+#define GET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd)		LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 2, 1)
-+#define GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd)	LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 3, 1)
-+#define GET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd)			LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 4, 4)
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+#define SET_IPHDR_VERSION(__pHeader, __Value)				WriteLE1Byte(((u8 *)(__pHeader)) + 0, __Value)
-+#define SET_IPHDR_DSCP(__pHeader, __Value)					WriteLE1Byte(((u8 *)(__pHeader)) + 1, __Value)
-+#define SET_IPHDR_TOTAL_LEN(__pHeader, __Value)			WriteLE2Byte(((u8 *)(__pHeader)) + 2, __Value)
-+#define SET_IPHDR_IDENTIFIER(__pHeader, __Value)			WriteLE2Byte(((u8 *)(__pHeader)) + 4, __Value)
-+#define SET_IPHDR_FLAGS(__pHeader, __Value)				WriteLE1Byte(((u8 *)(__pHeader)) + 6, __Value)
-+#define SET_IPHDR_FRAG_OFFSET(__pHeader, __Value)			WriteLE1Byte(((u8 *)(__pHeader)) + 7, __Value)
-+#define SET_IPHDR_TTL(__pHeader, __Value)					WriteLE1Byte(((u8 *)(__pHeader)) + 8, __Value)
-+#define SET_IPHDR_PROTOCOL(__pHeader, __Value)			WriteLE1Byte(((u8 *)(__pHeader)) + 9, __Value)
-+#define SET_IPHDR_HDR_CHECKSUM(__pHeader, __Value)		WriteLE2Byte(((u8 *)(__pHeader)) + 10, __Value)
-+#define SET_IPHDR_SRC_IP_ADDR(__pHeader, __Value)			cpIpAddr(((u8 *)(__pHeader))+12, (u8 *)(__Value))
-+#define SET_IPHDR_DST_IP_ADDR(__pHeader, __Value)			cpIpAddr(((u8 *)(__pHeader))+16, (u8 *)(__Value))
-+#define SET_UDP_SRC_PORT(__pHeader, __Value)	WriteLE2Byte(((u8 *)(__pHeader)) + 0, __Value)
-+#define SET_UDP_DST_PORT(__pHeader, __Value)	WriteLE2Byte(((u8 *)(__pHeader)) + 2, __Value)
-+#define SET_UDP_LEN(__pHeader, __Value)			WriteLE2Byte(((u8 *)(__pHeader)) + 4, __Value)
-+#define SET_UDP_CHECKSUM(__pHeader, __Value)			WriteLE2Byte(((u8 *)(__pHeader)) + 6, __Value)
-+
-+#define SET_MDNS_HDR_FLAG(__pHeader, __Value)		WriteLE1Byte(((u8 *)(__pHeader)) + 2, __Value)
-+
-+#endif /* CONFIG_WAR_OFFLOAD */
-+
-+#ifdef CONFIG_OFFLOAD_MDNS_V6
-+#define SET_IPHDRV6_VERSION(__pHeader, __Value)                     SET_BITS_TO_LE_1BYTE(__pHeader, 4, 4, __Value)
-+#define SET_IPHDRV6_TRAFFIC_CLASS(__pHeader, __Value)               SET_BITS_TO_LE_2BYTE(__pHeader, 4, 8, __Value)
-+#define SET_IPHDRV6_FLOW_LABEL(__pHeader, __Value)                  SET_BITS_TO_LE_4BYTE(__pHeader, 12, 20, __Value)
-+#define SET_IPHDRV6_PAYLOAD_LENGTH(__pHeader, __Value)              SET_BITS_TO_LE_2BYTE(((u8 *)(__pHeader)) + 4, 0, 16, __Value)
-+#define SET_IPHDRV6_NEXT_HEADER(__pHeader, __Value)                 SET_BITS_TO_LE_1BYTE((__pHeader) + 6, 0, 8, __Value)
-+#define SET_IPHDRV6_HOP_LIMIT(__pHeader, __Value)                   SET_BITS_TO_LE_1BYTE((__pHeader) + 7, 0, 8, __Value)
-+#define SET_IPHDRV6_SRC_IP_ADDR(__pHeader, __Value)                 cpIpv6Addr((u8 *)(__pHeader) + 8, (u8 *)(__Value))
-+#define SET_IPHDRV6_DST_IP_ADDR(__pHeader, __Value)                 cpIpv6Addr((u8 *)(__pHeader) + 24, (u8 *)(__Value))
-+#endif
-+
-+
-+
-+#define H2C_MSR_ROLE_RSVD	0
-+#define H2C_MSR_ROLE_STA	1
-+#define H2C_MSR_ROLE_AP		2
-+#define H2C_MSR_ROLE_GC		3
-+#define H2C_MSR_ROLE_GO		4
-+#define H2C_MSR_ROLE_TDLS	5
-+#define H2C_MSR_ROLE_ADHOC	6
-+#define H2C_MSR_ROLE_MESH	7
-+#define H2C_MSR_ROLE_MAX	8
-+
-+extern const char *const _h2c_msr_role_str[];
-+#define h2c_msr_role_str(role) (((role) >= H2C_MSR_ROLE_MAX) ? _h2c_msr_role_str[H2C_MSR_ROLE_MAX] : _h2c_msr_role_str[(role)])
-+
-+#define H2C_MSR_FMT "%s %s%s"
-+#define H2C_MSR_ARG(h2c_msr) \
-+	GET_H2CCMD_MSRRPT_PARM_OPMODE((h2c_msr)) ? " C" : "", \
-+	h2c_msr_role_str(GET_H2CCMD_MSRRPT_PARM_ROLE((h2c_msr))), \
-+	GET_H2CCMD_MSRRPT_PARM_MIRACAST((h2c_msr)) ? (GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK((h2c_msr)) ? " MSINK" : " MSRC") : ""
-+
-+s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end);
-+s32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid);
-+s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, u8 macid_end);
-+
-+/* _KEEP_ALIVE_CMD_0x03 */
-+#define SET_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 3, __Value)
-+#define SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+
-+/* _DISCONNECT_DECISION_CMD_0x04 */
-+#define SET_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_H2CCMD_DISCONDECISION_PARM_TRY_BCN_FAIL_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_H2CCMD_DISCONDECISION_PARM_DISCONNECT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
-+#define SET_H2CCMD_DISCONDECISION_PORT_NUM(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 3, __Value)
-+#define SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
-+#define SET_H2CCMD_DISCONDECISION_PARM_TRY_OK_BCN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+
-+/*UDP_KEEP_ALIVE 0x90*/
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+/*data 0*/
-+#define SET_H2CCMD_UDP_KEEP_ALIVE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value);
-+#define SET_H2CCMD_UDP_KEEP_ALIVE_PACKET_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 7, __Value);
-+/*data 1*/
-+#define SET_H2CCMD_UDP_KEEP_ALIVE_ACK_PATTERN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value);
-+#define SET_H2CCMD_UDP_KEEP_ALIVE_ACK_PATTERN_idx(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 7, __Value);
-+/*data 2*/
-+#define SET_H2CCMD_UDP_KEEP_ALIVE_WAKE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value);
-+#define SET_H2CCMD_UDP_KEEP_ALIVE_WAKE_PATTERN_idx(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value);
-+/*data3*/
-+#define SET_H2CCMD_UDP_KEEP_ALIVE_PERIOD_LOW_BIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value);
-+/*data4*/
-+#define SET_H2CCMD_UDP_KEEP_ALIVE_PERIOD_HI_BIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value);
-+/*data5*/
-+#define SET_H2CCMD_UDP_KEEP_ALIVE_RETRY_INTERVAL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value);
-+/*data6*/
-+#define SET_H2CCMD_UDP_KEEP_ALIVE_RETRY_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value);
-+#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+#define RTW_CUSTOMER_STR_LEN 16
-+#define RTW_CUSTOMER_STR_FMT "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x"
-+#define RTW_CUSTOMER_STR_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \
-+	((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \
-+	((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15]
-+
-+/* H2C_CUSTOMER_STR_REQ  0x06 */
-+#define H2C_CUSTOMER_STR_REQ_LEN 1
-+#define SET_H2CCMD_CUSTOMER_STR_REQ_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
-+s32 rtw_hal_h2c_customer_str_req(_adapter *adapter);
-+s32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs);
-+
-+/* H2C_CUSTOMER_STR_W1 0xC6 */
-+#define H2C_CUSTOMER_STR_W1_LEN 7
-+#define SET_H2CCMD_CUSTOMER_STR_W1_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
-+#define H2CCMD_CUSTOMER_STR_W1_BYTE0(__pH2CCmd)				(((u8 *)(__pH2CCmd)) + 1)
-+
-+/* H2C_CUSTOMER_STR_W2 0xC7 */
-+#define H2C_CUSTOMER_STR_W2_LEN 7
-+#define SET_H2CCMD_CUSTOMER_STR_W2_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
-+#define H2CCMD_CUSTOMER_STR_W2_BYTE6(__pH2CCmd)				(((u8 *)(__pH2CCmd)) + 1)
-+
-+/* H2C_CUSTOMER_STR_W3 0xC8 */
-+#define H2C_CUSTOMER_STR_W3_LEN 5
-+#define SET_H2CCMD_CUSTOMER_STR_W3_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
-+#define H2CCMD_CUSTOMER_STR_W3_BYTE12(__pH2CCmd)			(((u8 *)(__pH2CCmd)) + 1)
-+s32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs);
-+s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs);
-+#endif /* CONFIG_RTW_CUSTOMER_STR */
-+
-+#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
-+#define H2C_TXPWR_IDX_OFFLOAD_LEN 4
-+#define SET_H2CCMD_TXPWR_IDX_CCK(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_H2CCMD_TXPWR_IDX_OFDM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd + 1, 0, 8, __Value)
-+#define SET_H2CCMD_TXPWR_IDX_HT1SS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd + 2, 0, 8, __Value)
-+#define SET_H2CCMD_TXPWR_IDX_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd + 3, 0, 1, __Value)
-+#endif
-+
-+/* _AP_Offload 0x08 */
-+#define SET_H2CCMD_AP_WOWLAN_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+/* _BCN_RsvdPage	0x09 */
-+#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_BCN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+/* _Probersp_RsvdPage 0x0a */
-+#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_ProbeRsp(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+/* _Probersp_RsvdPage 0x13 */
-+
-+#define SET_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
-+#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
-+#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
-+#define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+#define GET_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)							LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
-+/* _PWR_MOD_CMD_0x20 */
-+
-+#define SET_H2CCMD_AP_WOW_GPIO_CTRL_INDEX(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
-+#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
-+#define SET_H2CCMD_AP_WOW_GPIO_CTRL_PLUS(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
-+#define SET_H2CCMD_AP_WOW_GPIO_CTRL_HIGH_ACTIVE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
-+#define SET_H2CCMD_AP_WOW_GPIO_CTRL_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
-+#define SET_H2CCMD_AP_WOW_GPIO_CTRL_DURATION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_DURATION(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+/* _AP_PS 0x26 */
-+#define SET_H2CCMD_AP_WOW_PS_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_H2CCMD_AP_WOW_PS_32K_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_H2CCMD_AP_WOW_PS_RF(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_H2CCMD_AP_WOW_PS_DURATION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+
-+/* INACTIVE_PS 0x27, duration unit is TBTT */
-+#define SET_H2CCMD_INACTIVE_PS_EN(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_H2CCMD_INACTIVE_IGNORE_PS(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_H2CCMD_INACTIVE_PERIOD_SCAN_EN(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_H2CCMD_INACTIVE_DISBBRF(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
-+#define SET_H2CCMD_INACTIVE_PORT_NUM(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 3, __Value)	
-+#define SET_H2CCMD_INACTIVE_PS_FREQ(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd + 1, 0, 8, __Value)
-+#define SET_H2CCMD_INACTIVE_PS_DURATION(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd + 2, 0, 8, __Value)
-+#define SET_H2CCMD_INACTIVE_PS_PERIOD_SCAN_TIME(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd + 3, 0, 8, __Value)
-+
-+#ifdef CONFIG_LPS_POFF
-+/*PARTIAL OFF Control 0x29*/
-+#define SET_H2CCMD_LPS_POFF_CTRL_EN(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+/*PARTIAL OFF PARAM   0x2A*/
-+#define SET_H2CCMD_LPS_POFF_PARAM_RDVLD(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_H2CCMD_LPS_POFF_PARAM_WRVLD(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_H2CCMD_LPS_POFF_PARAM_STARTADDL(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_H2CCMD_LPS_POFF_PARAM_STARTADDH(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
-+#define SET_H2CCMD_LPS_POFF_PARAM_ENDADDL(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+#define SET_H2CCMD_LPS_POFF_PARAM_ENDADDH(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
-+#endif
-+
-+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
-+/* DEFAULT PORT ID 0x2C*/
-+#define SET_H2CCMD_DFTPID_PORT_ID(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 8, (__Value))
-+#define SET_H2CCMD_DFTPID_MAC_ID(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value))
-+#endif
-+
-+#ifdef CONFIG_MCC_MODE
-+/* MCC LOC CMD 0x10 */
-+#define SET_H2CCMD_MCC_RSVDPAGE_LOC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 0, 1, __Value)
-+#define SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 4, 4, __Value)
-+#define SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 4, 0, 8, __Value)
-+
-+/* MCC RQT TSF 0x15 */
-+#define SET_H2CCMD_MCC_RQT_TSFX(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
-+#define SET_H2CCMD_MCC_RQT_TSFY(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
-+
-+/* MCC MAC ID CMD 0x16 */
-+#define SET_H2CCMD_MCC_MACID_BITMAP_L(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_H2CCMD_MCC_MACID_BITMAP_H(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+
-+/* NEW MCC CTRL CMD 0x17 */
-+#define SET_H2CCMD_MCC_CTRL_V2_ORDER(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
-+#define SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
-+#define SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 4, __Value)
-+#define SET_H2CCMD_MCC_CTRL_V2_BW(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 4, __Value)
-+#define SET_H2CCMD_MCC_CTRL_V2_DURATION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_H2CCMD_MCC_CTRL_V2_ROLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 3, __Value)			
-+#define SET_H2CCMD_MCC_CTRL_V2_INCURCH(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)
-+#define SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value)
-+#define SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value)
-+#define SET_H2CCMD_MCC_CTRL_V2_C2HRPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 6, 2, __Value)
-+#define SET_H2CCMD_MCC_CTRL_V2_TSFX(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 4, __Value)
-+#define SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 4, 4, __Value)
-+#define SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value)
-+
-+
-+/* MCC CTRL CMD 0x18 */
-+#define SET_H2CCMD_MCC_CTRL_ORDER(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
-+#define SET_H2CCMD_MCC_CTRL_TOTALNUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
-+#define SET_H2CCMD_MCC_CTRL_CHIDX(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_H2CCMD_MCC_CTRL_BW(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)
-+#define SET_H2CCMD_MCC_CTRL_BW40SC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 3, __Value)
-+#define SET_H2CCMD_MCC_CTRL_BW80SC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 5, 3, __Value)
-+#define SET_H2CCMD_MCC_CTRL_DURATION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_H2CCMD_MCC_CTRL_ROLE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 3, __Value)
-+#define SET_H2CCMD_MCC_CTRL_INCURCH(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)
-+#define SET_H2CCMD_MCC_CTRL_RSVD0(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 4, __Value)
-+#define SET_H2CCMD_MCC_CTRL_RSVD1(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
-+#define SET_H2CCMD_MCC_CTRL_RFETYPE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 4, __Value)
-+#define SET_H2CCMD_MCC_CTRL_DISTXNULL(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 4, 1, __Value)
-+#define SET_H2CCMD_MCC_CTRL_C2HRPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 5, 2, __Value)
-+#define SET_H2CCMD_MCC_CTRL_CHSCAN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value)
-+
-+/* MCC Time CMD 0x19 */
-+#define SET_H2CCMD_MCC_TIME_SETTING_FW_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 7, __Value)
-+#define SET_H2CCMD_MCC_TIME_SETTING_START_TIME(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define  SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 4, __Value)
-+#define  SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 4, __Value)
-+#define  SET_H2CCMD_MCC_TIME_SETTING_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 1, __Value)
-+#define  SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 1, 7, __Value)
-+
-+/* MCC IQK CMD 0x1A */
-+#define SET_H2CCMD_MCC_IQK_READY(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_H2CCMD_MCC_IQK_ORDER(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 4, __Value)
-+#define SET_H2CCMD_MCC_IQK_PATH(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 2, __Value)
-+#define SET_H2CCMD_MCC_IQK_RX_L(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_H2CCMD_MCC_IQK_RX_M1(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)
-+#define SET_H2CCMD_MCC_IQK_RX_M2(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 6, __Value)
-+#define SET_H2CCMD_MCC_IQK_RX_H(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 4, __Value)
-+#define SET_H2CCMD_MCC_IQK_TX_L(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+#define SET_H2CCMD_MCC_IQK_TX_M1(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 3, __Value)
-+#define SET_H2CCMD_MCC_IQK_TX_M2(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 3, 5, __Value)
-+#define SET_H2CCMD_MCC_IQK_TX_H(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 6, __Value)
-+#endif /* CONFIG_MCC_MODE */
-+
-+/* CHNL SWITCH OPER OFFLOAD 0x1C */
-+#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_CH_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_MODE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 2, __Value)
-+#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_40M_SC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 2, 3, __Value)
-+#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 5, 3, __Value)
-+#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 0, 4, __Value)
-+
-+/* H2C_SINGLE_CHANNELSWITCH_V2 = 0x1D */
-+#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_CENTRAL_CH_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_PRIMARY_CH_IDX(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 4, __Value)
-+#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_BW(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 4, 4, __Value)
-+#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_PWR_IDX_UPDATE_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 0, 1, __Value)
-+#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_IQK_UPDATE_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 1, 1, __Value)
-+#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_CH_IDX(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 4, 4, __Value)
-+
-+#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
-+#define SET_H2CCMD_BTC_WL_PORT_ID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
-+#endif
-+
-+/* _WoWLAN PARAM_CMD_0x80 */
-+#define SET_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 7, __Value)
-+#define SET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 7, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 1, 7, __Value)
-+#define SET_H2CCMD_WOWLAN_DISABLE_UPHY(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_HST2DEV_EN(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 1, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_GPIO_DURATION_MS(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_CHANGE_UNIT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_UNIT_FOR_UPHY_DISABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_TAKE_PDN_UPHY_DIS_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_DEV2HST_EN(__pH2CCmd, __Value) 	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 7, 1, __Value)
-+#define SET_H2CCMD_WOWLAN_TIME_FOR_UPHY_DISABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
-+#define SET_H2CCMD_WOWLAN_RISE_HST2DEV(__pH2CCmd, __Value) 	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 2, 1, __Value)
-+
-+/* _REMOTE_WAKEUP_CMD_0x81 */
-+#define SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
-+#define SET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
-+#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
-+#define SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 1, __Value)
-+#define SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 2, 1, __Value)
-+#define SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 3, 1, __Value)
-+
-+#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 1, __Value)
-+#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 1, __Value)
-+
-+/* AOAC_GLOBAL_INFO_0x82 */
-+#define SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+
-+/* AOAC_RSVDPAGE_LOC_0x83 */
-+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
-+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+#ifdef CONFIG_GTK_OL
-+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
-+#endif /* CONFIG_GTK_OL */
-+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NDP_INFO(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 8, __Value)
-+
-+/* AOAC_RSVDPAGE_2_0x84 */
-+
-+/* AOAC_RSVDPAGE_3_0x88 */
-+#ifdef CONFIG_PNO_SUPPORT
-+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
-+#endif
-+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_AOAC_REPORT(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 8, __Value)
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+/* D0_Scan_Offload_Info_0x86 */
-+#define SET_H2CCMD_AOAC_NLO_FUN_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd), 3, 1, __Value)
-+#define SET_H2CCMD_AOAC_NLO_IPS_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd), 4, 1, __Value)
-+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#endif /* CONFIG_PNO_SUPPORT */
-+
-+/* _GPIO_CUSTOM_CMD_0x89 */
-+#define SET_H2CCMD_CUSTOMERID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_H2CCMD_SPECIAL_WAKE_REASON(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_H2CCMD_CUSTOM_WAKE_REASON(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 1, __Value)
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+/* P2P_RsvdPage_0x8a */
-+#define SET_H2CCMD_RSVDPAGE_LOC_P2P_BCN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_H2CCMD_RSVDPAGE_LOC_P2P_PROBE_RSP(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_H2CCMD_RSVDPAGE_LOC_P2P_NEGO_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_H2CCMD_RSVDPAGE_LOC_P2P_INVITE_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_H2CCMD_RSVDPAGE_LOC_P2P_PD_RSP(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+#endif /* CONFIG_P2P_WOWLAN */
-+
-+#ifdef CONFIG_LPS_PG
-+#define SET_H2CCMD_LPSPG_SEC_CAM_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)/*SecurityCAM_En*/
-+#define SET_H2CCMD_LPSPG_MBID_CAM_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)/*BSSIDCAM_En*/
-+#define SET_H2CCMD_LPSPG_PMC_CAM_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)/*PatternMatchCAM_En*/
-+#define SET_H2CCMD_LPSPG_MACID_SEARCH_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)/*MACIDSearch_En*/
-+#define SET_H2CCMD_LPSPG_TXSC_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)/*TXSC_En*/
-+#define SET_H2CCMD_LPSPG_MU_RATE_TB_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)/*MURateTable_En*/
-+#define SET_H2CCMD_LPSPG_LOC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)/*Loc_LPS_PG*/
-+#define SET_H2CCMD_LPSPG_DPK_INFO_LOC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)/*Loc_LPS_PG_DPK_info*/
-+#define SET_H2CCMD_LPSPG_IQK_INFO_LOC(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 0, 8, __Value)/*Loc_IQK_result*/
-+#endif
-+
-+#if defined(CONFIG_RTL8822C) && defined(CONFIG_SUPPORT_DYNAMIC_TXPWR)
-+#define SET_H2CCMD_FW_CRC5_SEARCH_EN(cmd, v)	\
-+	SET_BITS_TO_LE_1BYTE((cmd), 0, 1, (v));
-+#define SET_H2CCMD_FW_CRC5_SEARCH_MACID(cmd, v)	\
-+	SET_BITS_TO_LE_1BYTE((cmd), 1, 7, (v));
-+#define SET_H2CCMD_FW_CRC5_SEARCH_MAC(cmd, mac)	\
-+	do {		\
-+		int __offset = 0;	\
-+		for (__offset = 0; __offset < ETH_ALEN; __offset++)	\
-+			SET_BITS_TO_LE_1BYTE((u8 *)(cmd + __offset), 0, 8, *((u8 *)(mac + __offset)));	\
-+	} while(0)
-+#endif
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+/* WarOffload_Info_0x8D */
-+#define SET_H2CCMD_WAR_CFG_EN(__pH2CCmd, __Value)               SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_H2CCMD_WAR_CFG_ARP_RSP_EN(__pH2CCmd, __Value)       SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_H2CCMD_WAR_CFG_MDNSV4_RSP_EN(__pH2CCmd, __Value)   SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 1, __Value)
-+#define SET_H2CCMD_WAR_CFG_MDNSV6_RSP_EN(__pH2CCmd, __Value)   SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 3, 1, __Value)
-+#define SET_H2CCMD_WAR_CFG_MDNSV4_WAKE_EN(__pH2CCmd, __Value)   SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 6, 1, __Value)
-+#define SET_H2CCMD_WAR_CFG_MDNSV6_WAKE_EN(__pH2CCmd, __Value)   SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 7, 1, __Value)
-+
-+/* H2C_WAROFLD_RSVDPAGE1 */
-+#define SET_H2CCMD_WAROFLD_RSVDPAGE1_LOC_PARM(__pH2CCmd, __Value)  SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
-+#endif /* CONFIG_WAR_OFFLOAD */
-+
-+
-+/* BT_UNKNOWN_DEVICE_WA_0xD1 */
-+#define SET_H2CCMD_BT_UNKNOWN_DEVICE_WA_HANG_CHK_EN(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_H2CCMD_BT_UNKNOWN_DEVICE_WA_FORCE_IB_EN(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_H2CCMD_BT_UNKNOWN_DEVICE_WA_HWID_CHK_EN(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_H2CCMD_BT_UNKNOWN_DEVICE_WA_ONE_TIME_CHK(__pH2CCmd, __Value) \
-+	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
-+
-+#ifdef DBG_FW_DEBUG_MSG_PKT
-+#define SET_H2CCMD_FW_DBG_MSG_PKT_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)/*sniffer_dbg_en*/
-+#define SET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) /*loc_debug_packet*/
-+#endif /*DBG_FW_DEBUG_MSG_PKT*/
-+
-+#ifdef DBG_RSVD_PAGE_CFG
-+#define RSVD_PAGE_CFG(ops, v1, v2, v3)	\
-+	RTW_INFO("=== [RSVD][%s]-NeedPage:%d, TotalPageNum:%d TotalPacketLen:%d ===\n",	\
-+		ops, v1, v2, v3)
-+#else
-+#define RSVD_PAGE_CFG(ops, v1, v2, v3) do {} while (0)
-+#endif
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * -------------------------------------------    Structure    --------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+typedef struct _RSVDPAGE_LOC {
-+	u8 LocProbeRsp;
-+	u8 LocPsPoll;
-+	u8 LocNullData;
-+	u8 LocQosNull;
-+	u8 LocBTQosNull;
-+#ifdef CONFIG_WOWLAN
-+	u8 LocRemoteCtrlInfo;
-+	u8 LocArpRsp;
-+	u8 LocNbrAdv;
-+	u8 LocGTKRsp;
-+	u8 LocGTKInfo;
-+	u8 LocProbeReq;
-+	u8 LocNetList;
-+#ifdef CONFIG_GTK_OL
-+	u8 LocGTKEXTMEM;
-+#endif /* CONFIG_GTK_OL */
-+	u8 LocNDPInfo;
-+	u8 LocAOACReport;
-+#ifdef CONFIG_PNO_SUPPORT
-+	u8 LocPNOInfo;
-+	u8 LocScanInfo;
-+	u8 LocSSIDInfo;
-+	u8 LocProbePacket;
-+#endif /* CONFIG_PNO_SUPPORT */
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+	u8 LocKeepAlive;
-+#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+#ifdef CONFIG_WAR_OFFLOAD
-+	u8 LocIpParm;
-+#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
-+	u8 LocMdnsPara;
-+	u8 LocMdnsv4;
-+	u8 LocMdnsv6;
-+#endif /* defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) */
-+#endif /* CONFIG_WAR_OFFLOAD */
-+
-+#endif /* CONFIG_WOWLAN	 */
-+	u8 LocApOffloadBCN;
-+#ifdef CONFIG_P2P_WOWLAN
-+	u8 LocP2PBeacon;
-+	u8 LocP2PProbeRsp;
-+	u8 LocNegoRsp;
-+	u8 LocInviteRsp;
-+	u8 LocPDRsp;
-+#endif /* CONFIG_P2P_WOWLAN */
-+#ifdef DBG_FW_DEBUG_MSG_PKT
-+	u8 loc_fw_dbg_msg_pkt;
-+#endif /*DBG_FW_DEBUG_MSG_PKT*/
-+} RSVDPAGE_LOC, *PRSVDPAGE_LOC;
-+
-+struct rsvd_page_cache_t {
-+	char *name;
-+	u8 loc;
-+	u8 page_num;
-+	u8 *data;
-+	u32 size;
-+};
-+
-+bool rsvd_page_cache_update_all(struct rsvd_page_cache_t *cache, u8 loc
-+	, u8 txdesc_len, u32 page_size, u8 *info, u32 info_len);
-+bool rsvd_page_cache_update_data(struct rsvd_page_cache_t *cache, u8 *info
-+	, u32 info_len);
-+void rsvd_page_cache_free_data(struct rsvd_page_cache_t *cache);
-+void rsvd_page_cache_free(struct rsvd_page_cache_t *cache);
-+
-+#endif
-+#ifdef CONFIG_WOWLAN
-+void dump_TX_FIFO(PADAPTER padapter, u8 page_num, u16 page_size);
-+#endif
-+u8 rtw_hal_set_fw_media_status_cmd(_adapter *adapter, u8 mstatus, u8 macid);
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+	/* WOW command function */
-+	void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable);
-+	#ifdef CONFIG_P2P_WOWLAN
-+		/* H2C 0x8A */
-+		u8 rtw_hal_set_FwP2PRsvdPage_cmd(_adapter *adapter, PRSVDPAGE_LOC rsvdpageloc);
-+		/* H2C 0x8B */
-+		u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter);
-+	#endif /* CONFIG_P2P_WOWLAN */
-+#endif
-+
-+#ifdef RTW_PER_CMD_SUPPORT_FW
-+u8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid,
-+			       u8 rpt_type, u32 macid_bitmap);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/hal_com_led.h b/drivers/staging/rtl8723cs/include/hal_com_led.h
-new file mode 100644
-index 000000000000..379c4fdd107f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_com_led.h
-@@ -0,0 +1,437 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_COMMON_LED_H_
-+#define __HAL_COMMON_LED_H_
-+
-+#define NO_LED 0
-+#define HW_LED 1
-+
-+#ifdef CONFIG_RTW_LED
-+#define MSECS(t)        (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000)
-+
-+/* ********************************************************************************
-+ *	LED Behavior Constant.
-+ * ********************************************************************************
-+ * Default LED behavior.
-+ *   */
-+#define LED_BLINK_NORMAL_INTERVAL	100
-+#define LED_BLINK_SLOWLY_INTERVAL	200
-+#define LED_BLINK_LONG_INTERVAL	400
-+#define LED_INITIAL_INTERVAL		1800
-+
-+/* LED Customerization */
-+
-+/* NETTRONIX */
-+#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX	100
-+#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX	2000
-+
-+/* PORNET */
-+#define LED_BLINK_SLOWLY_INTERVAL_PORNET	1000
-+#define LED_BLINK_NORMAL_INTERVAL_PORNET	100
-+#define LED_BLINK_FAST_INTERVAL_BITLAND		30
-+
-+/* AzWave. */
-+#define LED_CM2_BLINK_ON_INTERVAL		250
-+#define LED_CM2_BLINK_OFF_INTERVAL		4750
-+#define LED_CM8_BLINK_OFF_INTERVAL		3750	/* for QMI */
-+
-+/* RunTop */
-+#define LED_RunTop_BLINK_INTERVAL		300
-+
-+/* ALPHA */
-+#define LED_BLINK_NO_LINK_INTERVAL_ALPHA	1000
-+#define LED_BLINK_NO_LINK_INTERVAL_ALPHA_500MS 500 /* add by ylb 20121012 for customer led for alpha */
-+#define LED_BLINK_LINK_INTERVAL_ALPHA		500	/* 500 */
-+#define LED_BLINK_SCAN_INTERVAL_ALPHA		180	/* 150 */
-+#define LED_BLINK_FASTER_INTERVAL_ALPHA		50
-+#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA	5000
-+
-+/* 111122 by hpfan: Customized for Xavi */
-+#define LED_CM11_BLINK_INTERVAL			300
-+#define LED_CM11_LINK_ON_INTERVEL		3000
-+
-+/* Netgear */
-+#define LED_BLINK_LINK_INTERVAL_NETGEAR		500
-+#define LED_BLINK_LINK_SLOWLY_INTERVAL_NETGEAR		1000
-+
-+#define LED_WPS_BLINK_OFF_INTERVAL_NETGEAR		100
-+#define LED_WPS_BLINK_ON_INTERVAL_NETGEAR		500
-+
-+/* Belkin AC950 */
-+#define LED_BLINK_LINK_INTERVAL_ON_BELKIN		200
-+#define LED_BLINK_LINK_INTERVAL_OFF_BELKIN		100
-+#define LED_BLINK_ERROR_INTERVAL_BELKIN		100
-+
-+/* by chiyokolin for Azurewave */
-+#define LED_CM12_BLINK_INTERVAL_5Mbps		160
-+#define LED_CM12_BLINK_INTERVAL_10Mbps		80
-+#define LED_CM12_BLINK_INTERVAL_20Mbps		50
-+#define LED_CM12_BLINK_INTERVAL_40Mbps		40
-+#define LED_CM12_BLINK_INTERVAL_80Mbps		30
-+#define LED_CM12_BLINK_INTERVAL_MAXMbps		25
-+
-+/* Dlink */
-+#define	LED_BLINK_NO_LINK_INTERVAL		1000
-+#define	LED_BLINK_LINK_IDEL_INTERVAL		100
-+
-+#define	LED_BLINK_SCAN_ON_INTERVAL		30
-+#define	LED_BLINK_SCAN_OFF_INTERVAL		300
-+
-+#define LED_WPS_BLINK_ON_INTERVAL_DLINK		30
-+#define LED_WPS_BLINK_OFF_INTERVAL_DLINK			300
-+#define LED_WPS_BLINK_LINKED_ON_INTERVAL_DLINK			5000
-+
-+/* ********************************************************************************
-+ * LED object.
-+ * ******************************************************************************** */
-+
-+typedef enum _LED_CTL_MODE {
-+	LED_CTL_POWER_ON = 1,
-+	LED_CTL_LINK = 2,
-+	LED_CTL_NO_LINK = 3,
-+	LED_CTL_TX = 4, /* unspecific data TX, including single & group addressed */
-+	LED_CTL_RX = 5, /* unspecific data RX, including single & group addressed */
-+	LED_CTL_UC_TX = 6, /* single addressed data TX */
-+	LED_CTL_UC_RX = 7, /* single addressed data RX */
-+	LED_CTL_BMC_TX = 8, /* group addressed data TX */
-+	LED_CTL_BMC_RX = 9, /* group addressed data RX */
-+	LED_CTL_SITE_SURVEY = 10,
-+	LED_CTL_POWER_OFF = 11,
-+	LED_CTL_START_TO_LINK = 12,
-+	LED_CTL_START_WPS = 13,
-+	LED_CTL_STOP_WPS = 14,
-+	LED_CTL_START_WPS_BOTTON = 15, /* added for runtop */
-+	LED_CTL_STOP_WPS_FAIL = 16, /* added for ALPHA	 */
-+	LED_CTL_STOP_WPS_FAIL_OVERLAP = 17, /* added for BELKIN */
-+	LED_CTL_CONNECTION_NO_TRANSFER = 18,
-+} LED_CTL_MODE;
-+
-+typedef	enum _LED_STATE {
-+	LED_UNKNOWN = 0,
-+	RTW_LED_ON = 1,
-+	RTW_LED_OFF = 2,
-+	LED_BLINK_NORMAL = 3,
-+	LED_BLINK_SLOWLY = 4,
-+	LED_BLINK_POWER_ON = 5,
-+	LED_BLINK_SCAN = 6,	/* LED is blinking during scanning period, the # of times to blink is depend on time for scanning. */
-+	LED_BLINK_NO_LINK = 7, /* LED is blinking during no link state. */
-+	LED_BLINK_StartToBlink = 8, /* Customzied for Sercomm Printer Server case */
-+	LED_BLINK_TXRX = 9,
-+	LED_BLINK_WPS = 10,	/* LED is blinkg during WPS communication */
-+	LED_BLINK_WPS_STOP = 11,	/* for ALPHA */
-+	LED_BLINK_WPS_STOP_OVERLAP = 12,	/* for BELKIN */
-+	LED_BLINK_RUNTOP = 13,	/* Customized for RunTop */
-+	LED_BLINK_CAMEO = 14,
-+	LED_BLINK_XAVI = 15,
-+	LED_BLINK_ALWAYS_ON = 16,
-+	LED_BLINK_LINK_IN_PROCESS = 17,  /* Customized for Belkin AC950 */
-+	LED_BLINK_AUTH_ERROR = 18,  /* Customized for Belkin AC950 */
-+	LED_BLINK_Azurewave_5Mbps = 19,
-+	LED_BLINK_Azurewave_10Mbps = 20,
-+	LED_BLINK_Azurewave_20Mbps = 21,
-+	LED_BLINK_Azurewave_40Mbps = 22,
-+	LED_BLINK_Azurewave_80Mbps = 23,
-+	LED_BLINK_Azurewave_MAXMbps = 24,
-+	LED_BLINK_LINK_IDEL = 25,
-+	LED_BLINK_WPS_LINKED = 26,
-+} LED_STATE;
-+
-+typedef enum _LED_PIN {
-+	LED_PIN_GPIO0,
-+	LED_PIN_LED0,
-+	LED_PIN_LED1,
-+	LED_PIN_LED2
-+} LED_PIN;
-+
-+
-+/* ********************************************************************************
-+ * PCIE LED Definition.
-+ * ******************************************************************************** */
-+#ifdef CONFIG_PCI_HCI
-+typedef	enum _LED_STRATEGY_PCIE {
-+	/* start from 2 */
-+	SW_LED_MODE_UC_TRX_ONLY = 2,
-+	SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
-+	SW_LED_MODE1, /* SW control for PCI Express */
-+	SW_LED_MODE2, /* SW control for Cameo. */
-+	SW_LED_MODE3, /* SW contorl for RunTop. */
-+	SW_LED_MODE4, /* SW control for Netcore */
-+	SW_LED_MODE5, /* added by vivi, for led new mode, DLINK */
-+	SW_LED_MODE6, /* added by vivi, for led new mode, PRONET */
-+	SW_LED_MODE7, /* added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec */
-+	SW_LED_MODE8, /* added by chiyokolin, for QMI */
-+	SW_LED_MODE9, /* added by chiyokolin, for BITLAND-LENOVO, PCI Express Minicard Spec Rev.1.1	 */
-+	SW_LED_MODE10, /* added by chiyokolin, for Edimax-ASUS */
-+	SW_LED_MODE11,	/* added by hpfan, for Xavi */
-+	SW_LED_MODE12,	/* added by chiyokolin, for Azurewave */
-+} LED_STRATEGY_PCIE, *PLED_STRATEGY_PCIE;
-+
-+typedef struct _LED_PCIE {
-+	PADAPTER		padapter;
-+
-+	LED_PIN			LedPin;	/* Identify how to implement this SW led. */
-+
-+	LED_STATE		CurrLedState; /* Current LED state. */
-+	BOOLEAN			bLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */
-+
-+	BOOLEAN			bLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
-+	BOOLEAN			bLedWPSBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
-+
-+	BOOLEAN			bLedSlowBlinkInProgress;/* added by vivi, for led new mode */
-+	u32				BlinkTimes; /* Number of times to toggle led state for blinking. */
-+	LED_STATE		BlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */
-+
-+	_timer			BlinkTimer; /* Timer object for led blinking. */
-+} LED_PCIE, *PLED_PCIE;
-+
-+typedef struct _LED_PCIE	LED_DATA, *PLED_DATA;
-+typedef enum _LED_STRATEGY_PCIE	LED_STRATEGY, *PLED_STRATEGY;
-+
-+void
-+LedControlPCIE(
-+		PADAPTER		Adapter,
-+		LED_CTL_MODE		LedAction
-+);
-+
-+void
-+gen_RefreshLedState(
-+		PADAPTER		Adapter);
-+
-+/* ********************************************************************************
-+ * USB  LED Definition.
-+ * ******************************************************************************** */
-+#elif defined(CONFIG_USB_HCI)
-+
-+#define IS_LED_WPS_BLINKING(_LED_USB)	(((PLED_USB)_LED_USB)->CurrLedState == LED_BLINK_WPS \
-+		|| ((PLED_USB)_LED_USB)->CurrLedState == LED_BLINK_WPS_STOP \
-+		|| ((PLED_USB)_LED_USB)->bLedWPSBlinkInProgress)
-+
-+#define IS_LED_BLINKING(_LED_USB)	(((PLED_USB)_LED_USB)->bLedWPSBlinkInProgress \
-+		|| ((PLED_USB)_LED_USB)->bLedScanBlinkInProgress)
-+
-+
-+typedef	enum _LED_STRATEGY_USB {
-+	/* start from 2 */
-+	SW_LED_MODE_UC_TRX_ONLY = 2,
-+	SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
-+	SW_LED_MODE1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */
-+	SW_LED_MODE2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */
-+	SW_LED_MODE3, /* SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. */
-+	SW_LED_MODE4, /* for Edimax / Belkin */
-+	SW_LED_MODE5, /* for Sercomm / Belkin	 */
-+	SW_LED_MODE6,	/* for 88CU minicard, porting from ce SW_LED_MODE7 */
-+	SW_LED_MODE7,	/* for Netgear special requirement */
-+	SW_LED_MODE8, /* for LC */
-+	SW_LED_MODE9, /* for Belkin AC950 */
-+	SW_LED_MODE10, /* for Netgear A6200V2 */
-+	SW_LED_MODE11, /* for Edimax / ASUS */
-+	SW_LED_MODE12, /* for WNC/NEC */
-+	SW_LED_MODE13, /* for Netgear A6100, 8811Au */
-+	SW_LED_MODE14, /* for Buffalo, DNI, 8811Au */
-+	SW_LED_MODE15, /* for DLINK,  8811Au/8812AU	 */
-+} LED_STRATEGY_USB, *PLED_STRATEGY_USB;
-+
-+
-+typedef struct _LED_USB {
-+	PADAPTER			padapter;
-+
-+	LED_PIN				LedPin;	/* Identify how to implement this SW led. */
-+
-+	LED_STATE			CurrLedState; /* Current LED state. */
-+	BOOLEAN				bLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */
-+
-+	BOOLEAN				bSWLedCtrl;
-+
-+	BOOLEAN				bLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
-+	/* ALPHA, added by chiyoko, 20090106 */
-+	BOOLEAN				bLedNoLinkBlinkInProgress;
-+	BOOLEAN				bLedLinkBlinkInProgress;
-+	BOOLEAN				bLedStartToLinkBlinkInProgress;
-+	BOOLEAN				bLedScanBlinkInProgress;
-+	BOOLEAN				bLedWPSBlinkInProgress;
-+
-+	u32					BlinkTimes; /* Number of times to toggle led state for blinking. */
-+	u8					BlinkCounter; /* Added for turn off overlap led after blinking a while, by page, 20120821 */
-+	LED_STATE			BlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */
-+
-+	_timer				BlinkTimer; /* Timer object for led blinking. */
-+
-+	_workitem			BlinkWorkItem; /* Workitem used by BlinkTimer to manipulate H/W to blink LED.' */
-+} LED_USB, *PLED_USB;
-+
-+typedef struct _LED_USB	LED_DATA, *PLED_DATA;
-+typedef enum _LED_STRATEGY_USB	LED_STRATEGY, *PLED_STRATEGY;
-+#ifdef CONFIG_RTW_SW_LED
-+void
-+LedControlUSB(
-+		PADAPTER		Adapter,
-+		LED_CTL_MODE		LedAction
-+);
-+#endif
-+
-+
-+/* ********************************************************************************
-+ * SDIO LED Definition.
-+ * ******************************************************************************** */
-+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+
-+#define IS_LED_WPS_BLINKING(_LED_SDIO)	(((PLED_SDIO)_LED_SDIO)->CurrLedState == LED_BLINK_WPS \
-+		|| ((PLED_SDIO)_LED_SDIO)->CurrLedState == LED_BLINK_WPS_STOP \
-+		|| ((PLED_SDIO)_LED_SDIO)->bLedWPSBlinkInProgress)
-+
-+#define IS_LED_BLINKING(_LED_SDIO)	(((PLED_SDIO)_LED_SDIO)->bLedWPSBlinkInProgress \
-+		|| ((PLED_SDIO)_LED_SDIO)->bLedScanBlinkInProgress)
-+
-+
-+typedef	enum _LED_STRATEGY_SDIO {
-+	/* start from 2 */
-+	SW_LED_MODE_UC_TRX_ONLY = 2,
-+	SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
-+	SW_LED_MODE1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */
-+	SW_LED_MODE2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */
-+	SW_LED_MODE3, /* SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. */
-+	SW_LED_MODE4, /* for Edimax / Belkin */
-+	SW_LED_MODE5, /* for Sercomm / Belkin	 */
-+	SW_LED_MODE6,	/* for 88CU minicard, porting from ce SW_LED_MODE7 */
-+} LED_STRATEGY_SDIO, *PLED_STRATEGY_SDIO;
-+
-+typedef struct _LED_SDIO {
-+	PADAPTER			padapter;
-+
-+	LED_PIN				LedPin;	/* Identify how to implement this SW led. */
-+
-+	LED_STATE			CurrLedState; /* Current LED state. */
-+	BOOLEAN				bLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */
-+
-+	BOOLEAN				bSWLedCtrl;
-+
-+	BOOLEAN				bLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
-+	/* ALPHA, added by chiyoko, 20090106 */
-+	BOOLEAN				bLedNoLinkBlinkInProgress;
-+	BOOLEAN				bLedLinkBlinkInProgress;
-+	BOOLEAN				bLedStartToLinkBlinkInProgress;
-+	BOOLEAN				bLedScanBlinkInProgress;
-+	BOOLEAN				bLedWPSBlinkInProgress;
-+
-+	u32					BlinkTimes; /* Number of times to toggle led state for blinking. */
-+	LED_STATE			BlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */
-+
-+	_timer				BlinkTimer; /* Timer object for led blinking. */
-+
-+	_workitem			BlinkWorkItem; /* Workitem used by BlinkTimer to manipulate H/W to blink LED. */
-+} LED_SDIO, *PLED_SDIO;
-+
-+typedef struct _LED_SDIO	LED_DATA, *PLED_DATA;
-+typedef enum _LED_STRATEGY_SDIO	LED_STRATEGY, *PLED_STRATEGY;
-+
-+void
-+LedControlSDIO(
-+		PADAPTER		Adapter,
-+		LED_CTL_MODE		LedAction
-+);
-+
-+#endif
-+
-+struct led_priv {
-+	LED_STRATEGY		LedStrategy;
-+#ifdef CONFIG_RTW_SW_LED
-+	LED_DATA			SwLed0;
-+	LED_DATA			SwLed1;
-+	LED_DATA			SwLed2;
-+	u8					bRegUseLed;
-+	u8 iface_en_mask;
-+	u32 ctl_en_mask[CONFIG_IFACE_NUMBER];
-+	void (*LedControlHandler)(_adapter *padapter, LED_CTL_MODE LedAction);
-+	void (*SwLedOn)(_adapter *padapter, PLED_DATA pLed);
-+	void (*SwLedOff)(_adapter *padapter, PLED_DATA pLed);
-+#endif
-+};
-+
-+#define SwLedOn(adapter, pLed) \
-+	do { \
-+		if (adapter_to_led(adapter)->SwLedOn) \
-+			adapter_to_led(adapter)->SwLedOn((adapter), (pLed)); \
-+	} while (0)
-+
-+#define SwLedOff(adapter, pLed) \
-+	do { \
-+		if (adapter_to_led(adapter)->SwLedOff) \
-+			adapter_to_led(adapter)->SwLedOff((adapter), (pLed)); \
-+	} while (0)
-+
-+void BlinkTimerCallback(void *data);
-+void BlinkWorkItemCallback(_workitem *work);
-+
-+void ResetLedStatus(PLED_DATA pLed);
-+
-+void
-+InitLed(
-+	_adapter			*padapter,
-+	PLED_DATA		pLed,
-+	LED_PIN			LedPin
-+);
-+
-+void
-+DeInitLed(
-+	PLED_DATA		pLed
-+);
-+
-+/* hal... */
-+extern void BlinkHandler(PLED_DATA	pLed);
-+void dump_led_config(void *sel, _adapter *adapter);
-+void rtw_led_set_strategy(_adapter *adapter, u8 strategy);
-+#endif /* CONFIG_RTW_LED */
-+
-+#if defined(CONFIG_RTW_LED)
-+#define rtw_led_get_strategy(adapter) (adapter_to_led(adapter)->LedStrategy)
-+#else
-+#define rtw_led_get_strategy(adapter) NO_LED
-+#endif
-+
-+#define IS_NO_LED_STRATEGY(s) ((s) == NO_LED)
-+#define IS_HW_LED_STRATEGY(s) ((s) == HW_LED)
-+#define IS_SW_LED_STRATEGY(s) ((s) != NO_LED && (s) != HW_LED)
-+
-+#if defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED)
-+
-+#ifndef CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
-+#define CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY 0
-+#endif
-+
-+#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
-+void rtw_sw_led_blink_uc_trx_only(LED_DATA *led);
-+void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl);
-+#endif
-+void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl);
-+void rtw_led_tx_control(_adapter *adapter, const u8 *da);
-+void rtw_led_rx_control(_adapter *adapter, const u8 *da);
-+void rtw_led_set_iface_en(_adapter *adapter, u8 en);
-+void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask);
-+void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask);
-+void rtw_led_set_ctl_en_mask_primary(_adapter *adapter);
-+void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter);
-+#else
-+#define rtw_led_control(adapter, ctl) do {} while (0)
-+#define rtw_led_tx_control(adapter, da) do {} while (0)
-+#define rtw_led_rx_control(adapter, da) do {} while (0)
-+#define rtw_led_set_iface_en(adapter, en) do {} while (0)
-+#define rtw_led_set_iface_en_mask(adapter, mask) do {} while (0)
-+#define rtw_led_set_ctl_en_mask(adapter, ctl_mask) do {} while (0)
-+#define rtw_led_set_ctl_en_mask_primary(adapter) do {} while (0)
-+#define rtw_led_set_ctl_en_mask_virtual(adapter) do {} while (0)
-+#endif /* defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED) */
-+
-+#endif /*__HAL_COMMON_LED_H_*/
-+
-diff --git a/drivers/staging/rtl8723cs/include/hal_com_phycfg.h b/drivers/staging/rtl8723cs/include/hal_com_phycfg.h
-new file mode 100644
-index 000000000000..b6e74a743359
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_com_phycfg.h
-@@ -0,0 +1,341 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_COM_PHYCFG_H__
-+#define __HAL_COM_PHYCFG_H__
-+
-+#ifndef DBG_TX_POWER_IDX
-+#define DBG_TX_POWER_IDX 0
-+#endif
-+
-+#define		PathA                     			0x0	/* Useless */
-+#define		PathB			0x1
-+#define		PathC			0x2
-+#define		PathD			0x3
-+
-+typedef enum _RF_TX_NUM {
-+	RF_1TX = 0,
-+	RF_2TX,
-+	RF_3TX,
-+	RF_4TX,
-+	RF_MAX_TX_NUM,
-+	RF_TX_NUM_NONIMPLEMENT,
-+} RF_TX_NUM;
-+
-+enum txpwr_pg_mode {
-+	TXPWR_PG_WITH_PWR_IDX,
-+	TXPWR_PG_WITH_TSSI_OFFSET,
-+	TXPWR_PG_UNKNOWN, /* keep last */
-+};
-+
-+/*------------------------------Define structure----------------------------*/
-+typedef struct _BB_REGISTER_DEFINITION {
-+	u32 rfintfs;			/* set software control: */
-+	/*		0x870~0x877[8 bytes] */
-+
-+	u32 rfintfo; 			/* output data: */
-+	/*		0x860~0x86f [16 bytes] */
-+
-+	u32 rfintfe; 			/* output enable: */
-+	/*		0x860~0x86f [16 bytes] */
-+
-+	u32 rf3wireOffset;	/* LSSI data: */
-+	/*		0x840~0x84f [16 bytes] */
-+
-+	u32 rfHSSIPara2;	/* wire parameter control2 :  */
-+	/*		0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */
-+
-+	u32 rfLSSIReadBack;	/* LSSI RF readback data SI mode */
-+	/*		0x8a0~0x8af [16 bytes] */
-+
-+	u32 rfLSSIReadBackPi;	/* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */
-+
-+} BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
-+
-+
-+/* ---------------------------------------------------------------------- */
-+
-+extern const char *const _txpwr_pg_mode_str[];
-+#define txpwr_pg_mode_str(_mode) (((_mode) >= TXPWR_PG_UNKNOWN) ? _txpwr_pg_mode_str[TXPWR_PG_UNKNOWN] : _txpwr_pg_mode_str[(_mode)])
-+
-+u8 phy_get_target_txpwr(
-+		PADAPTER		Adapter,
-+		u8				Band,
-+		u8				RfPath,
-+		RATE_SECTION	RateSection
-+);
-+
-+void
-+PHY_GetRateValuesOfTxPowerByRate(
-+		PADAPTER pAdapter,
-+		u32 RegAddr,
-+		u32 BitMask,
-+		u32 Value,
-+		u8 *Rate,
-+		s8 *PwrByRateVal,
-+		u8 *RateNum
-+);
-+
-+u8 phy_get_rate_idx_of_txpwr_by_rate(enum MGN_RATE rate);
-+
-+void
-+phy_set_tx_power_index_by_rate_section(
-+		PADAPTER		pAdapter,
-+		enum rf_path		RFPath,
-+		u8				Channel,
-+		u8				RateSection
-+);
-+
-+s8 phy_get_txpwr_by_rate(_adapter *adapter
-+	, BAND_TYPE band, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate);
-+
-+s16 phy_get_txpwr_by_rate_single_mbm(_adapter *adapter
-+	, BAND_TYPE band, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate, bool eirp);
-+s16 phy_get_txpwr_by_rate_total_mbm(_adapter *adapter
-+	, BAND_TYPE band, RATE_SECTION rs, enum MGN_RATE rate, bool cap, bool eirp);
-+
-+s16 phy_get_txpwr_by_rate_single_max_mbm(_adapter *adapter, BAND_TYPE band, enum rf_path rfpath, bool eirp);
-+s16 phy_get_txpwr_by_rate_total_max_mbm(_adapter *adapter, BAND_TYPE band, bool cap, bool eirp);
-+
-+void
-+phy_set_tx_power_level_by_path(
-+		PADAPTER	Adapter,
-+		u8			channel,
-+		u8			path
-+);
-+
-+void
-+PHY_InitTxPowerByRate(
-+		PADAPTER	pAdapter
-+);
-+
-+void
-+phy_store_tx_power_by_rate(
-+		PADAPTER	pAdapter,
-+		u32			Band,
-+		u32			RfPath,
-+		u32			TxNum,
-+		u32			RegAddr,
-+		u32			BitMask,
-+		u32			Data
-+);
-+
-+void
-+PHY_TxPowerByRateConfiguration(
-+	  PADAPTER			pAdapter
-+);
-+
-+bool phy_chk_ch_setting_consistency(_adapter *adapter, u8 ch);
-+
-+#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+u8 phy_get_pg_txpwr_idx(_adapter *pAdapter
-+	, enum rf_path RFPath, RATE_SECTION rs, u8 ntx_idx
-+	, enum channel_width BandWidth, u8 band, u8 Channel);
-+#endif
-+
-+#if CONFIG_TXPWR_LIMIT
-+s8 phy_get_txpwr_lmt(_adapter *adapter
-+	, const char *regd_name
-+	, BAND_TYPE band, enum channel_width bw
-+	, u8 tlrs, u8 ntx_idx, u8 cch, u8 lock
-+);
-+
-+s8 phy_get_txpwr_lmt_diff(_adapter *adapter
-+	, const char *regd_name
-+	, BAND_TYPE band, enum channel_width bw
-+	, u8 rfpath, u8 rs, u8 tlrs, u8 ntx_idx, u8 cch, u8 lock
-+);
-+
-+s8 phy_get_txpwr_lmt_sub_chs(_adapter *adapter
-+	, const char *regd_name
-+	, BAND_TYPE band, enum channel_width bw
-+	, u8 rfpath, u8 rate, u8 ntx_idx, u8 cch, u8 opch, bool reg_max
-+);
-+#else
-+#define phy_get_txpwr_lmt(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)
-+#define phy_get_txpwr_lmt_diff(adapter, regd_name, band, bw, rfpath, rs, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)
-+#define phy_get_txpwr_lmt_sub_chs(adapter, regd_name, band, bw, rfpath, rate, ntx_idx, cch, opch, reg_max) (GET_HAL_SPEC(adapter)->txgi_max)
-+#endif /* CONFIG_TXPWR_LIMIT */
-+
-+void dump_txpwr_tpc_settings(void *sel, _adapter *adapter);
-+void dump_txpwr_antenna_gain(void *sel, _adapter *adapter);
-+
-+s8 phy_get_txpwr_target(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate, u8 ntx_idx
-+	, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch, bool reg_max, struct txpwr_idx_comp *tic);
-+s8 phy_get_txpwr_amends(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate, u8 ntx_idx
-+	, enum channel_width bw, BAND_TYPE band, u8 cch, struct txpwr_idx_comp *tic);
-+#ifdef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
-+s8 phy_get_tssi_txpwr_by_rate_ref(_adapter *adapter, enum rf_path path
-+	, enum channel_width bw, u8 cch, u8 opch);
-+#endif
-+u8 hal_com_get_txpwr_idx(_adapter *adapter, enum rf_path rfpath
-+	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
-+	, struct txpwr_idx_comp *tic);
-+
-+s16 phy_get_txpwr_single_mbm(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate
-+	, enum channel_width bw, u8 cch, u8 opch, bool reg_max, bool eirp, struct txpwr_idx_comp *tic);
-+s16 phy_get_txpwr_total_mbm(_adapter *adapter, RATE_SECTION rs, u8 rate
-+	, enum channel_width bw, u8 cch, u8 opch, bool reg_max, bool eirp, struct txpwr_idx_comp *tic);
-+
-+s16 phy_get_txpwr_single_max_mbm(_adapter *adapter, u8 rfpath
-+	, enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht, bool reg_max, bool eirp);
-+s16 phy_get_txpwr_total_max_mbm(_adapter *adapter
-+	, enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht, bool reg_max, bool eirp);
-+
-+s8
-+phy_get_tx_power_final_absolute_value(_adapter *adapter, u8 rfpath, u8 rate,
-+				      enum channel_width bw, u8 channel);
-+
-+s8
-+PHY_GetTxPowerTrackingOffset(
-+	PADAPTER	pAdapter,
-+	enum rf_path	RFPath,
-+	u8			Rate
-+);
-+
-+struct txpwr_idx_comp {
-+	u8 ntx_idx;
-+	s8 target;
-+	s8 base;
-+
-+	/* for target */
-+	s8 by_rate;
-+	s8 btc;
-+	s8 extra;
-+	s8 utarget;
-+	s8 rlimit; /* regulatory limit w/o HAL consideration */
-+	s8 limit; /* limit from RTK private (regulatory limit w/ HAL consideration) */
-+	s8 ulimit; /* user limit */
-+	s8 tpc;
-+
-+	/* for amends */
-+	s8 tpt;
-+	s8 dpd;
-+};
-+
-+u8 phy_get_tx_power_index_ex(_adapter *adapter
-+	, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate
-+	, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch);
-+
-+u8
-+phy_get_tx_power_index(
-+		PADAPTER			pAdapter,
-+		enum rf_path			RFPath,
-+		u8					Rate,
-+		enum channel_width	BandWidth,
-+		u8					Channel
-+);
-+
-+void
-+PHY_SetTxPowerIndex(
-+		PADAPTER		pAdapter,
-+		u32				PowerIndex,
-+		enum rf_path		RFPath,
-+		u8				Rate
-+);
-+
-+bool phy_is_txpwr_user_mbm_valid(_adapter *adapter, s16 mbm);
-+bool phy_is_txpwr_user_target_specified(_adapter *adapter);
-+
-+void dump_tx_power_index_inline(void *sel, _adapter *adapter, u8 rfpath
-+	, enum channel_width bw, u8 cch, enum MGN_RATE rate, u8 pwr_idx, struct txpwr_idx_comp *tic);
-+#ifdef CONFIG_PROC_DEBUG
-+void dump_tx_power_idx_title(void *sel, _adapter *adapter
-+	, enum channel_width bw, u8 cch, u8 opch);
-+void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath
-+	, RATE_SECTION rs, enum channel_width bw, u8 cch, u8 opch);
-+void dump_tx_power_idx(void *sel, _adapter *adapter
-+	, enum channel_width bw, u8 cch, u8 opch);
-+void dump_txpwr_total_dbm_title(void *sel, _adapter *adapter
-+	, enum channel_width bw, u8 cch, u8 opch);
-+void dump_txpwr_total_dbm_by_rs(void *sel, _adapter *adapter, u8 rs
-+	, enum channel_width bw, u8 cch, u8 opch);
-+void dump_txpwr_total_dbm(void *sel, _adapter *adapter
-+	, enum channel_width bw, u8 cch, u8 opch);
-+#endif
-+
-+bool phy_is_tx_power_limit_needed(_adapter *adapter);
-+bool phy_is_tx_power_by_rate_needed(_adapter *adapter);
-+int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file);
-+#if CONFIG_TXPWR_LIMIT
-+int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file);
-+#endif
-+void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file);
-+void phy_reload_tx_power_ext_info(_adapter *adapter);
-+void phy_reload_default_tx_power_ext_info(_adapter *adapter);
-+
-+const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter);
-+
-+#ifdef CONFIG_EFUSE_CONFIG_FILE
-+int check_phy_efuse_tx_power_info_valid(_adapter *adapter);
-+#endif
-+
-+#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt);
-+void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt);
-+
-+void hal_load_txpwr_info(_adapter *adapter);
-+#endif
-+
-+#ifdef CONFIG_PROC_DEBUG
-+void dump_tx_power_ext_info(void *sel, _adapter *adapter);
-+void dump_target_tx_power(void *sel, _adapter *adapter);
-+void dump_tx_power_by_rate(void *sel, _adapter *adapter);
-+#endif
-+
-+int rtw_get_phy_file_path(_adapter *adapter, const char *file_name);
-+
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+#define MAC_FILE_FW_NIC			"FW_NIC.bin"
-+#define MAC_FILE_FW_WW_IMG		"FW_WoWLAN.bin"
-+#define PHY_FILE_MAC_REG		"MAC_REG.txt"
-+
-+#define PHY_FILE_AGC_TAB		"AGC_TAB.txt"
-+#define PHY_FILE_PHY_REG		"PHY_REG.txt"
-+#define PHY_FILE_PHY_REG_MP		"PHY_REG_MP.txt"
-+#define PHY_FILE_PHY_REG_PG		"PHY_REG_PG.txt"
-+
-+#define PHY_FILE_RADIO_A		"RadioA.txt"
-+#define PHY_FILE_RADIO_B		"RadioB.txt"
-+#define PHY_FILE_RADIO_C		"RadioC.txt"
-+#define PHY_FILE_RADIO_D		"RadioD.txt"
-+#define PHY_FILE_TXPWR_TRACK	"TxPowerTrack.txt"
-+#define PHY_FILE_TXPWR_LMT		"TXPWR_LMT.txt"
-+
-+#define PHY_FILE_WIFI_ANT_ISOLATION	"wifi_ant_isolation.txt"
-+
-+#define MAX_PARA_FILE_BUF_LEN	32768 /* 32k */
-+
-+#define LOAD_MAC_PARA_FILE				BIT0
-+#define LOAD_BB_PARA_FILE					BIT1
-+#define LOAD_BB_PG_PARA_FILE				BIT2
-+#define LOAD_BB_MP_PARA_FILE				BIT3
-+#define LOAD_RF_PARA_FILE					BIT4
-+#define LOAD_RF_TXPWR_TRACK_PARA_FILE	BIT5
-+#define LOAD_RF_TXPWR_LMT_PARA_FILE		BIT6
-+
-+int phy_ConfigMACWithParaFile(PADAPTER	Adapter, char	*pFileName);
-+int phy_ConfigBBWithParaFile(PADAPTER	Adapter, char	*pFileName, u32	ConfigType);
-+int phy_ConfigBBWithPgParaFile(PADAPTER	Adapter, const char *pFileName);
-+int phy_ConfigBBWithMpParaFile(PADAPTER	Adapter, char	*pFileName);
-+int PHY_ConfigRFWithParaFile(PADAPTER	Adapter, char	*pFileName, enum rf_path	eRFPath);
-+int PHY_ConfigRFWithTxPwrTrackParaFile(PADAPTER	Adapter, char	*pFileName);
-+#if CONFIG_TXPWR_LIMIT
-+int PHY_ConfigRFWithPowerLimitTableParaFile(PADAPTER	Adapter, const char *pFileName);
-+#endif
-+void phy_free_filebuf_mask(_adapter *padapter, u8 mask);
-+void phy_free_filebuf(_adapter *padapter);
-+#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
-+u8 phy_check_under_survey_ch(_adapter *adapter);
-+#endif /* __HAL_COMMON_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/hal_com_reg.h b/drivers/staging/rtl8723cs/include/hal_com_reg.h
-new file mode 100644
-index 000000000000..353a0f505650
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_com_reg.h
-@@ -0,0 +1,1890 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_COMMON_REG_H__
-+#define __HAL_COMMON_REG_H__
-+
-+
-+#define MAC_ADDR_LEN				6
-+
-+#define HAL_NAV_UPPER_UNIT		128		/* micro-second */
-+
-+/* 8188E PKT_BUFF_ACCESS_CTRL value */
-+#define TXPKT_BUF_SELECT				0x69
-+#define RXPKT_BUF_SELECT				0xA5
-+#define TXREPORT_BUF_SELECT			0x7F
-+#define DISABLE_TRXPKT_BUF_ACCESS		0x0
-+
-+#ifndef RTW_HALMAC
-+/* ************************************************************
-+*
-+* ************************************************************ */
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0000h ~ 0x00FFh	System Configuration
-+*
-+* ----------------------------------------------------- */
-+#define REG_SYS_ISO_CTRL				0x0000
-+#define REG_SYS_FUNC_EN				0x0002
-+#define REG_APS_FSMCO					0x0004
-+#define REG_SYS_CLKR					0x0008
-+#define REG_SYS_CLK_CTRL				REG_SYS_CLKR
-+#define REG_9346CR						0x000A
-+#define REG_SYS_EEPROM_CTRL			0x000A
-+#define REG_EE_VPD						0x000C
-+#define REG_AFE_MISC					0x0010
-+#define REG_SPS0_CTRL					0x0011
-+#define REG_SPS0_CTRL_6					0x0016
-+#define REG_POWER_OFF_IN_PROCESS		0x0017
-+#define REG_SPS_OCP_CFG				0x0018
-+#define REG_RSV_CTRL					0x001C
-+#define REG_RF_CTRL						0x001F
-+#define REG_LDOA15_CTRL				0x0020
-+#define REG_LDOV12D_CTRL				0x0021
-+#define REG_LDOHCI12_CTRL				0x0022
-+#define REG_LPLDO_CTRL					0x0023
-+#define REG_AFE_XTAL_CTRL				0x0024
-+#define REG_AFE_LDO_CTRL				0x0027 /* 1.5v for 8188EE test chip, 1.4v for MP chip */
-+#define REG_AFE_PLL_CTRL				0x0028
-+#define REG_MAC_PHY_CTRL				0x002c /* for 92d, DMDP, SMSP, DMSP contrl */
-+#define REG_APE_PLL_CTRL_EXT			0x002c
-+#define REG_EFUSE_CTRL					0x0030
-+#define REG_EFUSE_TEST					0x0034
-+#define REG_PWR_DATA					0x0038
-+#define REG_CAL_TIMER					0x003C
-+#define REG_ACLK_MON					0x003E
-+#define REG_GPIO_MUXCFG				0x0040
-+#define REG_GPIO_IO_SEL					0x0042
-+#define REG_MAC_PINMUX_CFG			0x0043
-+#define REG_GPIO_PIN_CTRL				0x0044
-+#define REG_GPIO_INTM					0x0048
-+#define REG_LEDCFG0						0x004C
-+#define REG_LEDCFG1						0x004D
-+#define REG_LEDCFG2						0x004E
-+#define REG_LEDCFG3						0x004F
-+#define REG_FSIMR						0x0050
-+#define REG_FSISR						0x0054
-+#define REG_HSIMR						0x0058
-+#define REG_HSISR						0x005c
-+#define REG_GPIO_PIN_CTRL_2			0x0060 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
-+#define REG_GPIO_IO_SEL_2				0x0062 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
-+#define REG_PAD_CTRL_1				0x0064
-+#define REG_MULTI_FUNC_CTRL			0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */
-+#define REG_GSSR						0x006c
-+#define REG_AFE_XTAL_CTRL_EXT			0x0078 /* RTL8188E */
-+#define REG_XCK_OUT_CTRL				0x007c /* RTL8188E */
-+#define REG_MCUFWDL					0x0080
-+#define REG_WOL_EVENT					0x0081 /* RTL8188E */
-+#define REG_MCUTSTCFG					0x0084
-+#define REG_FDHM0						0x0088
-+#define REG_HOST_SUSP_CNT				0x00BC	/* RTL8192C Host suspend counter on FPGA platform */
-+#define REG_SYSTEM_ON_CTRL			0x00CC	/* For 8723AE Reset after S3 */
-+#define REG_EFUSE_ACCESS				0x00CF	/* Efuse access protection for RTL8723 */
-+#define REG_BIST_SCAN					0x00D0
-+#define REG_BIST_RPT					0x00D4
-+#define REG_BIST_ROM_RPT				0x00D8
-+#define REG_USB_SIE_INTF				0x00E0
-+#define REG_PCIE_MIO_INTF				0x00E4
-+#define REG_PCIE_MIO_INTD				0x00E8
-+#define REG_HPON_FSM					0x00EC
-+#define REG_SYS_CFG						0x00F0
-+#define REG_GPIO_OUTSTS				0x00F4	/* For RTL8723 only. */
-+#define REG_TYPE_ID						0x00FC
-+
-+/*
-+* 2010/12/29 MH Add for 92D
-+*   */
-+#define REG_MAC_PHY_CTRL_NORMAL		0x00f8
-+
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+*
-+* ----------------------------------------------------- */
-+#define REG_CR							0x0100
-+#define REG_PBP							0x0104
-+#define REG_PKT_BUFF_ACCESS_CTRL		0x0106
-+#define REG_TRXDMA_CTRL				0x010C
-+#define REG_TRXFF_BNDY					0x0114
-+#define REG_TRXFF_STATUS				0x0118
-+#define REG_RXFF_PTR					0x011C
-+#define REG_HIMR						0x0120
-+#define REG_FE1IMR						0x0120
-+#define REG_HISR							0x0124
-+#define REG_HIMRE						0x0128
-+#define REG_HISRE						0x012C
-+#define REG_CPWM						0x012F
-+#define REG_FWIMR						0x0130
-+#define REG_FWISR						0x0134
-+#define REG_FTIMR						0x0138
-+#define REG_FTISR						0x013C /* RTL8192C */
-+#define REG_PKTBUF_DBG_CTRL			0x0140
-+#define REG_RXPKTBUF_CTRL				(REG_PKTBUF_DBG_CTRL+2)
-+#define REG_PKTBUF_DBG_DATA_L			0x0144
-+#define REG_PKTBUF_DBG_DATA_H		0x0148
-+
-+#define REG_TC0_CTRL					0x0150
-+#define REG_TC1_CTRL					0x0154
-+#define REG_TC2_CTRL					0x0158
-+#define REG_TC3_CTRL					0x015C
-+#define REG_TC4_CTRL					0x0160
-+#define REG_TCUNIT_BASE				0x0164
-+#define REG_MBIST_START				0x0174
-+#define REG_MBIST_DONE					0x0178
-+#define REG_MBIST_FAIL					0x017C
-+#define REG_32K_CTRL					0x0194 /* RTL8188E */
-+#define REG_C2HEVT_MSG_NORMAL		0x01A0
-+#define REG_C2HEVT_CLEAR				0x01AF
-+#define REG_MCUTST_1					0x01c0
-+#define REG_MCUTST_WOWLAN			0x01C7	/* Defined after 8188E series. */
-+#define REG_FMETHR						0x01C8
-+#define REG_HMETFR						0x01CC
-+#define REG_HMEBOX_0					0x01D0
-+#define REG_HMEBOX_1					0x01D4
-+#define REG_HMEBOX_2					0x01D8
-+#define REG_HMEBOX_3					0x01DC
-+#define REG_LLT_INIT					0x01E0
-+#define REG_HMEBOX_EXT_0				0x01F0
-+#define REG_HMEBOX_EXT_1				0x01F4
-+#define REG_HMEBOX_EXT_2				0x01F8
-+#define REG_HMEBOX_EXT_3				0x01FC
-+
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0200h ~ 0x027Fh	TXDMA Configuration
-+*
-+* ----------------------------------------------------- */
-+#define REG_RQPN						0x0200
-+#define REG_FIFOPAGE					0x0204
-+#define REG_TDECTRL						0x0208
-+#define REG_TXDMA_OFFSET_CHK			0x020C
-+#define REG_TXDMA_STATUS				0x0210
-+#define REG_RQPN_NPQ					0x0214
-+#define REG_TQPNT1						0x0218
-+#define REG_TQPNT2						0x021C
-+#define REG_AUTO_LLT					0x0224
-+
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0280h ~ 0x02FFh	RXDMA Configuration
-+*
-+* ----------------------------------------------------- */
-+#define REG_RXDMA_AGG_PG_TH			0x0280
-+#define REG_RXPKT_NUM					0x0284
-+#define REG_RXDMA_STATUS				0x0288
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0300h ~ 0x03FFh	PCIe
-+*
-+* ----------------------------------------------------- */
-+#ifndef CONFIG_TRX_BD_ARCH	/* prevent CONFIG_TRX_BD_ARCH to use old registers */
-+
-+#define REG_PCIE_CTRL_REG				0x0300
-+#define REG_INT_MIG					0x0304	/* Interrupt Migration */
-+#define REG_BCNQ_DESA					0x0308	/* TX Beacon Descriptor Address */
-+#define REG_HQ_DESA					0x0310	/* TX High Queue Descriptor Address */
-+#define REG_MGQ_DESA					0x0318	/* TX Manage Queue Descriptor Address */
-+#define REG_VOQ_DESA					0x0320	/* TX VO Queue Descriptor Address */
-+#define REG_VIQ_DESA					0x0328	/* TX VI Queue Descriptor Address */
-+#define REG_BEQ_DESA					0x0330	/* TX BE Queue Descriptor Address */
-+#define REG_BKQ_DESA					0x0338	/* TX BK Queue Descriptor Address */
-+#define REG_RX_DESA					0x0340	/* RX Queue Descriptor Address */
-+/* sherry added for DBI Read/Write  20091126 */
-+#define REG_DBI_WDATA					0x0348	/*  Backdoor REG for Access Configuration */
-+#define REG_DBI_RDATA					0x034C	/* Backdoor REG for Access Configuration */
-+#define REG_DBI_CTRL					0x0350	/* Backdoor REG for Access Configuration */
-+#define REG_DBI_FLAG					0x0352	/* Backdoor REG for Access Configuration */
-+#define REG_MDIO					0x0354	/* MDIO for Access PCIE PHY */
-+#define REG_DBG_SEL					0x0360	/* Debug Selection Register */
-+#define REG_WATCH_DOG					0x0368
-+#define REG_RX_RXBD_NUM					0x0382
-+
-+/* RTL8723 series ------------------------------- */
-+#define REG_PCIE_HISR_EN				0x0394	/* PCIE Local Interrupt Enable Register */
-+#define REG_PCIE_HISR					0x03A0
-+#define REG_PCIE_HISRE					0x03A4
-+#define REG_PCIE_HIMR					0x03A8
-+#define REG_PCIE_HIMRE					0x03AC
-+
-+#endif /* !CONFIG_TRX_BD_ARCH */
-+
-+#define REG_USB_HIMR					0xFE38
-+#define REG_USB_HIMRE					0xFE3C
-+#define REG_USB_HISR					0xFE78
-+#define REG_USB_HISRE					0xFE7C
-+
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0400h ~ 0x047Fh	Protocol Configuration
-+*
-+* ----------------------------------------------------- */
-+
-+/* 92C, 92D */
-+#define REG_VOQ_INFO	0x0400
-+#define REG_VIQ_INFO	0x0404
-+#define REG_BEQ_INFO	0x0408
-+#define REG_BKQ_INFO	0x040C
-+
-+/* 88E, 8723A, 8812A, 8821A, 92E, 8723B */
-+#define REG_Q0_INFO	0x400
-+#define REG_Q1_INFO	0x404
-+#define REG_Q2_INFO	0x408
-+#define REG_Q3_INFO	0x40C
-+
-+#define REG_MGQ_INFO	0x0410
-+#define REG_HGQ_INFO	0x0414
-+#define REG_BCNQ_INFO	0x0418
-+#define REG_TXPKT_EMPTY				0x041A
-+#define REG_CPU_MGQ_INFORMATION		0x041C
-+#define REG_FWHW_TXQ_CTRL				0x0420
-+#define REG_HWSEQ_CTRL					0x0423
-+#define REG_BCNQ_BDNY					0x0424
-+#define REG_MGQ_BDNY					0x0425
-+#define REG_LIFETIME_EN					0x0426
-+#define REG_MULTI_BCNQ_OFFSET			0x0427
-+#define REG_SPEC_SIFS					0x0428
-+#define REG_RETRY_LIMIT					0x042A
-+#define REG_DARFRC						0x0430
-+#define REG_RARFRC						0x0438
-+#define REG_RRSR						0x0440
-+#define REG_ARFR0						0x0444
-+#define REG_ARFR1						0x0448
-+#define REG_ARFR2						0x044C
-+#define REG_ARFR3						0x0450
-+#define REG_CCK_CHECK					0x0454
-+#define REG_BCNQ1_BDNY					0x0457
-+
-+#define REG_AGGLEN_LMT					0x0458
-+#define REG_AMPDU_MIN_SPACE			0x045C
-+#define REG_WMAC_LBK_BF_HD			0x045D
-+#define REG_FAST_EDCA_CTRL				0x0460
-+#define REG_RD_RESP_PKT_TH				0x0463
-+
-+/* 8723A, 8812A, 8821A, 92E, 8723B */
-+#define REG_Q4_INFO	0x468
-+#define REG_Q5_INFO	0x46C
-+#define REG_Q6_INFO	0x470
-+#define REG_Q7_INFO	0x474
-+
-+#define REG_INIRTS_RATE_SEL				0x0480
-+#define REG_INIDATA_RATE_SEL			0x0484
-+
-+/* 8723B, 92E, 8812A, 8821A*/
-+#define REG_MACID_SLEEP_3				0x0484
-+#define REG_MACID_SLEEP_1				0x0488
-+
-+#define REG_POWER_STAGE1				0x04B4
-+#define REG_POWER_STAGE2				0x04B8
-+#define REG_PKT_LIFE_TIME			0x04C0
-+#define REG_PKT_LIFE_TIME_VO_VI		0x04C0
-+#define REG_PKT_LIFE_TIME_BE_BK		0x04C2
-+#define REG_STBC_SETTING				0x04C4
-+#define REG_QUEUE_CTRL					0x04C6
-+#define REG_SINGLE_AMPDU_CTRL			0x04c7
-+#define REG_PROT_MODE_CTRL			0x04C8
-+#define REG_MAX_AGGR_NUM				0x04CA
-+#define REG_RTS_MAX_AGGR_NUM			0x04CB
-+#define REG_BAR_MODE_CTRL				0x04CC
-+#define REG_RA_TRY_RATE_AGG_LMT		0x04CF
-+
-+/* 8723A */
-+#define REG_MACID_DROP	0x04D0
-+
-+/* 88E */
-+#define REG_EARLY_MODE_CONTROL	0x04D0
-+
-+/* 8723B, 92E, 8812A, 8821A */
-+#define REG_MACID_SLEEP_2	0x04D0
-+
-+/* 8723A, 8723B, 92E, 8812A, 8821A */
-+#define REG_MACID_SLEEP	0x04D4
-+
-+#define REG_NQOS_SEQ					0x04DC
-+#define REG_HW_SEQ0						0x04D8
-+#define REG_HW_SEQ1						0x04DA
-+#define REG_HW_SEQ2						0x04DC
-+#define REG_HW_SEQ3						0x04DE
-+
-+#define REG_QOS_SEQ					0x04DE
-+#define REG_NEED_CPU_HANDLE			0x04E0
-+#define REG_PKT_LOSE_RPT				0x04E1
-+#define REG_PTCL_ERR_STATUS			0x04E2
-+#define REG_TX_RPT_CTRL					0x04EC
-+#define REG_TX_RPT_TIME					0x04F0	/* 2 byte */
-+#define REG_DUMMY						0x04FC
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0500h ~ 0x05FFh	EDCA Configuration
-+*
-+* ----------------------------------------------------- */
-+#define REG_EDCA_VO_PARAM				0x0500
-+#define REG_EDCA_VI_PARAM				0x0504
-+#define REG_EDCA_BE_PARAM				0x0508
-+#define REG_EDCA_BK_PARAM				0x050C
-+#define REG_BCNTCFG						0x0510
-+#define REG_PIFS							0x0512
-+#define REG_RDG_PIFS					0x0513
-+#define REG_SIFS_CTX					0x0514
-+#define REG_SIFS_TRX					0x0516
-+#define REG_TSFTR_SYN_OFFSET			0x0518
-+#define REG_AGGR_BREAK_TIME			0x051A
-+#define REG_SLOT						0x051B
-+#define REG_TX_PTCL_CTRL				0x0520
-+#define REG_TXPAUSE						0x0522
-+#define REG_DIS_TXREQ_CLR				0x0523
-+#define REG_RD_CTRL						0x0524
-+/*
-+* Format for offset 540h-542h:
-+*	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
-+*	[7:4]:   Reserved.
-+*	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
-+*	[23:20]: Reserved
-+* Description:
-+*	              |
-+*      |<--Setup--|--Hold------------>|
-+*   --------------|----------------------
-+*                 |
-+*                TBTT
-+* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
-+* Described by Designer Tim and Bruce, 2011-01-14.
-+*   */
-+#define REG_TBTT_PROHIBIT				0x0540
-+#define REG_RD_NAV_NXT					0x0544
-+#define REG_NAV_PROT_LEN				0x0546
-+#define REG_BCN_CTRL					0x0550
-+#define REG_BCN_CTRL_1					0x0551
-+#define REG_MBID_NUM					0x0552
-+#define REG_DUAL_TSF_RST				0x0553
-+#define REG_MBSSID_BCN_SPACE			0x0554
-+#define REG_DRVERLYINT					0x0558
-+#define REG_BCNDMATIM					0x0559
-+#define REG_ATIMWND					0x055A
-+#define REG_USTIME_TSF					0x055C
-+#define REG_BCN_MAX_ERR				0x055D
-+#define REG_RXTSF_OFFSET_CCK			0x055E
-+#define REG_RXTSF_OFFSET_OFDM			0x055F
-+#define REG_TSFTR						0x0560
-+#define REG_TSFTR1						0x0568	/* HW Port 1 TSF Register */
-+#define REG_ATIMWND_1					0x0570
-+#define REG_P2P_CTWIN					0x0572 /* 1 Byte long (in unit of TU) */
-+#define REG_PSTIMER						0x0580
-+#define REG_TIMER0						0x0584
-+#define REG_TIMER1						0x0588
-+#define REG_HIQ_NO_LMT_EN				0x05A7
-+#define REG_ACMHWCTRL					0x05C0
-+#define REG_NOA_DESC_SEL				0x05CF
-+#define REG_NOA_DESC_DURATION		0x05E0
-+#define REG_NOA_DESC_INTERVAL			0x05E4
-+#define REG_NOA_DESC_START			0x05E8
-+#define REG_NOA_DESC_COUNT			0x05EC
-+
-+#define REG_DMC							0x05F0	/* Dual MAC Co-Existence Register */
-+#define REG_SCH_TX_CMD					0x05F8
-+
-+#define REG_FW_RESET_TSF_CNT_1		0x05FC
-+#define REG_FW_RESET_TSF_CNT_0		0x05FD
-+#define REG_FW_BCN_DIS_CNT			0x05FE
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0600h ~ 0x07FFh	WMAC Configuration
-+*
-+* ----------------------------------------------------- */
-+#define REG_APSD_CTRL					0x0600
-+#define REG_BWOPMODE					0x0603
-+#define REG_TCR							0x0604
-+#define REG_RCR							0x0608
-+#define REG_RX_PKT_LIMIT				0x060C
-+#define REG_RX_DLK_TIME				0x060D
-+#define REG_RX_DRVINFO_SZ				0x060F
-+
-+#define REG_MACID						0x0610
-+#define REG_BSSID						0x0618
-+#define REG_MAR							0x0620
-+#define REG_MBIDCAMCFG_1				0x0628
-+#define REG_MBIDCAMCFG_2				0x062C
-+
-+#define REG_PNO_STATUS					0x0631
-+#define REG_USTIME_EDCA				0x0638
-+#define REG_MAC_SPEC_SIFS				0x063A
-+/* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */
-+#define REG_RESP_SIFS_CCK				0x063C	/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
-+#define REG_RESP_SIFS_OFDM                    0x063E	/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
-+
-+#define REG_ACKTO						0x0640
-+#define REG_CTS2TO						0x0641
-+#define REG_EIFS							0x0642
-+
-+/*REG_TCR*/
-+#define BIT_PWRBIT_OW_EN BIT(7)
-+
-+/* RXERR_RPT */
-+#define RXERR_TYPE_OFDM_PPDU			0
-+#define RXERR_TYPE_OFDM_FALSE_ALARM	1
-+#define RXERR_TYPE_OFDM_MPDU_OK		2
-+#define RXERR_TYPE_OFDM_MPDU_FAIL	3
-+#define RXERR_TYPE_CCK_PPDU			4
-+#define RXERR_TYPE_CCK_FALSE_ALARM	5
-+#define RXERR_TYPE_CCK_MPDU_OK		6
-+#define RXERR_TYPE_CCK_MPDU_FAIL		7
-+#define RXERR_TYPE_HT_PPDU				8
-+#define RXERR_TYPE_HT_FALSE_ALARM	9
-+#define RXERR_TYPE_HT_MPDU_TOTAL		10
-+#define RXERR_TYPE_HT_MPDU_OK			11
-+#define RXERR_TYPE_HT_MPDU_FAIL		12
-+#define RXERR_TYPE_RX_FULL_DROP		15
-+
-+#define RXERR_COUNTER_MASK			0xFFFFF
-+#define RXERR_RPT_RST					BIT(27)
-+#define _RXERR_RPT_SEL(type)			((type) << 28)
-+
-+/*
-+* Note:
-+*	The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is
-+*	always too small, but the WiFi TestPlan test by 25,000 microseconds of NAV through sending
-+*	CTS in the air. We must update this value greater than 25,000 microseconds to pass the item.
-+*	The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented
-+*	by SD1 Scott.
-+* By Bruce, 2011-07-18.
-+*   */
-+#define REG_NAV_UPPER					0x0652	/* unit of 128 */
-+
-+/* WMA, BA, CCX */
-+#define REG_NAV_CTRL					0x0650
-+#define REG_BACAMCMD					0x0654
-+#define REG_BACAMCONTENT				0x0658
-+#define REG_LBDLY						0x0660
-+#define REG_FWDLY						0x0661
-+#define REG_RXERR_RPT					0x0664
-+#define REG_WMAC_TRXPTCL_CTL			0x0668
-+
-+/* Security */
-+#define REG_CAMCMD						0x0670
-+#define REG_CAMWRITE					0x0674
-+#define REG_CAMREAD					0x0678
-+#define REG_CAMDBG						0x067C
-+#define REG_SECCFG						0x0680
-+
-+/* Power */
-+#define REG_WOW_CTRL					0x0690
-+#define REG_PS_RX_INFO					0x0692
-+#define REG_WMMPS_UAPSD_TID			0x0693
-+#define REG_WKFMCAM_CMD				0x0698
-+#define REG_WKFMCAM_NUM				REG_WKFMCAM_CMD
-+#define REG_WKFMCAM_RWD				0x069C
-+#define REG_RXFLTMAP0					0x06A0
-+#define REG_RXFLTMAP1					0x06A2
-+#define REG_RXFLTMAP2					0x06A4
-+#define REG_BCN_PSR_RPT				0x06A8
-+#define REG_BT_COEX_TABLE				0x06C0
-+
-+#define BIT_WKFCAM_WE					BIT(16)
-+#define BIT_WKFCAM_POLLING_V1				BIT(31)
-+#define BIT_WKFCAM_CLR_V1				BIT(30)
-+#define BIT_SHIFT_WKFCAM_ADDR_V2			8
-+#define BIT_MASK_WKFCAM_ADDR_V2			0xff
-+#define BIT_WKFCAM_ADDR_V2(x)				(((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)
-+
-+/* Hardware Port 1 */
-+#define REG_MACID1						0x0700
-+#define REG_BSSID1						0x0708
-+
-+/* Enable/Disable Port 0 and Port 1 for Specific ICs (ex. 8192F)*/
-+#define REG_WLAN_ACT_MASK_CTRL_1		0x076C
-+
-+/* GPIO Control */
-+#define REG_SW_GPIO_SHARE_CTRL_0		0x1038
-+#define REG_SW_GPIO_SHARE_CTRL_1		0x103C
-+#define REG_SW_GPIO_A_OUT				0x1040
-+#define REG_SW_GPIO_A_OEN				0x1044
-+#define REG_SW_GPIO_B_OEN				0x1058
-+#define REG_SW_GPIO_B_OUT				0x105C
-+
-+/* Hardware Port 2 */
-+#define REG_MACID2						0x1620
-+#define REG_BSSID2						0x1628
-+/* Hardware Port 3*/
-+#define REG_MACID3						0x1630
-+#define REG_BSSID3						0x1638
-+/* Hardware Port 4 */
-+#define REG_MACID4						0x1640
-+#define REG_BSSID4						0x1648
-+
-+
-+#define REG_CR_EXT						0x1100
-+
-+/* -----------------------------------------------------
-+*
-+*	0xFE00h ~ 0xFE55h	USB Configuration
-+*
-+* ----------------------------------------------------- */
-+#define REG_USB_INFO					0xFE17
-+#define REG_USB_SPECIAL_OPTION		0xFE55
-+#define REG_USB_DMA_AGG_TO			0xFE5B
-+#define REG_USB_AGG_TO					0xFE5C
-+#define REG_USB_AGG_TH					0xFE5D
-+
-+#define REG_USB_HRPWM					0xFE58
-+#define REG_USB_HCPWM					0xFE57
-+
-+/* for 92DU high_Queue low_Queue Normal_Queue select */
-+#define REG_USB_High_NORMAL_Queue_Select_MAC0	0xFE44
-+/* #define REG_USB_LOW_Queue_Select_MAC0		0xFE45 */
-+#define REG_USB_High_NORMAL_Queue_Select_MAC1	0xFE47
-+/* #define REG_USB_LOW_Queue_Select_MAC1		0xFE48 */
-+
-+/* For test chip */
-+#define REG_TEST_USB_TXQS				0xFE48
-+#define REG_TEST_SIE_VID				0xFE60		/* 0xFE60~0xFE61 */
-+#define REG_TEST_SIE_PID				0xFE62		/* 0xFE62~0xFE63 */
-+#define REG_TEST_SIE_OPTIONAL			0xFE64
-+#define REG_TEST_SIE_CHIRP_K			0xFE65
-+#define REG_TEST_SIE_PHY				0xFE66		/* 0xFE66~0xFE6B */
-+#define REG_TEST_SIE_MAC_ADDR			0xFE70		/* 0xFE70~0xFE75 */
-+#define REG_TEST_SIE_STRING			0xFE80		/* 0xFE80~0xFEB9 */
-+
-+
-+/* For normal chip */
-+#define REG_NORMAL_SIE_VID				0xFE60		/* 0xFE60~0xFE61 */
-+#define REG_NORMAL_SIE_PID				0xFE62		/* 0xFE62~0xFE63 */
-+#define REG_NORMAL_SIE_OPTIONAL		0xFE64
-+#define REG_NORMAL_SIE_EP				0xFE65		/* 0xFE65~0xFE67 */
-+#define REG_NORMAL_SIE_PHY			0xFE68		/* 0xFE68~0xFE6B */
-+#define REG_NORMAL_SIE_OPTIONAL2		0xFE6C
-+#define REG_NORMAL_SIE_GPS_EP			0xFE6D		/* 0xFE6D, for RTL8723 only. */
-+#define REG_NORMAL_SIE_MAC_ADDR		0xFE70		/* 0xFE70~0xFE75 */
-+#define REG_NORMAL_SIE_STRING			0xFE80		/* 0xFE80~0xFEDF */
-+
-+
-+/* -----------------------------------------------------
-+*
-+*	Redifine 8192C register definition for compatibility
-+*
-+* ----------------------------------------------------- */
-+
-+/* TODO: use these definition when using REG_xxx naming rule.
-+* NOTE: DO NOT Remove these definition. Use later. */
-+
-+#define EFUSE_CTRL				REG_EFUSE_CTRL		/* E-Fuse Control. */
-+#define EFUSE_TEST				REG_EFUSE_TEST		/* E-Fuse Test. */
-+#define MSR						(REG_CR + 2)		/* Media Status register */
-+/* #define ISR						REG_HISR */
-+#define MSR1						REG_CR_EXT
-+
-+#define TSFR						REG_TSFTR			/* Timing Sync Function Timer Register. */
-+#define TSFR1					REG_TSFTR1			/* HW Port 1 TSF Register */
-+
-+#define PBP						REG_PBP
-+
-+/* Redifine MACID register, to compatible prior ICs. */
-+#define IDR0						REG_MACID			/* MAC ID Register, Offset 0x0050-0x0053 */
-+#define IDR4						(REG_MACID + 4)		/* MAC ID Register, Offset 0x0054-0x0055 */
-+
-+/* Unused register */
-+#define UnusedRegister			0x1BF
-+#define DCAM					UnusedRegister
-+#define PSR						UnusedRegister
-+#define BBAddr					UnusedRegister
-+#define PhyDataR					UnusedRegister
-+
-+/* Min Spacing related settings. */
-+#define MAX_MSS_DENSITY_2T			0x13
-+#define MAX_MSS_DENSITY_1T			0x0A
-+
-+/* ----------------------------------------------------------------------------
-+* 8192C Cmd9346CR bits					(Offset 0xA, 16bit)
-+* ---------------------------------------------------------------------------- */
-+#define CmdEEPROM_En				BIT(5)	 /* EEPROM enable when set 1 */
-+#define CmdEERPOMSEL				BIT(4)	/* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */
-+#define Cmd9346CR_9356SEL			BIT(4)
-+
-+/* ----------------------------------------------------------------------------
-+* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte)
-+* ---------------------------------------------------------------------------- */
-+#define GPIOSEL_GPIO				0
-+#define GPIOSEL_ENBT				BIT(5)
-+
-+/* ----------------------------------------------------------------------------
-+* 8192C GPIO PIN Control Register (offset 0x44, 4 byte)
-+* ---------------------------------------------------------------------------- */
-+#define GPIO_IN					REG_GPIO_PIN_CTRL		/* GPIO pins input value */
-+#define GPIO_OUT				(REG_GPIO_PIN_CTRL+1)	/* GPIO pins output value */
-+#define GPIO_IO_SEL				(REG_GPIO_PIN_CTRL+2)	/* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */
-+#define GPIO_MOD				(REG_GPIO_PIN_CTRL+3)
-+
-+/* ----------------------------------------------------------------------------
-+* 8811A GPIO PIN Control Register (offset 0x60, 4 byte)
-+* ---------------------------------------------------------------------------- */
-+#define GPIO_IN_8811A			REG_GPIO_PIN_CTRL_2		/* GPIO pins input value */
-+#define GPIO_OUT_8811A			(REG_GPIO_PIN_CTRL_2+1)	/* GPIO pins output value */
-+#define GPIO_IO_SEL_8811A		(REG_GPIO_PIN_CTRL_2+2)	/* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */
-+#define GPIO_MOD_8811A			(REG_GPIO_PIN_CTRL_2+3)
-+
-+/* ----------------------------------------------------------------------------
-+* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte)
-+* ---------------------------------------------------------------------------- */
-+#define HSIMR_GPIO12_0_INT_EN			BIT(0)
-+#define HSIMR_SPS_OCP_INT_EN			BIT(5)
-+#define HSIMR_RON_INT_EN				BIT(6)
-+#define HSIMR_PDN_INT_EN				BIT(7)
-+#define HSIMR_GPIO9_INT_EN				BIT(25)
-+
-+/* ----------------------------------------------------------------------------
-+* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte)
-+* ---------------------------------------------------------------------------- */
-+#define HSISR_GPIO12_0_INT				BIT(0)
-+#define HSISR_SPS_OCP_INT				BIT(5)
-+#define HSISR_RON_INT					BIT(6)
-+#define HSISR_PDNINT					BIT(7)
-+#define HSISR_GPIO9_INT					BIT(25)
-+
-+/* ----------------------------------------------------------------------------
-+* 8192C (MSR) Media Status Register	(Offset 0x4C, 8 bits)
-+* ---------------------------------------------------------------------------- */
-+/*
-+Network Type
-+00: No link
-+01: Link in ad hoc network
-+10: Link in infrastructure network
-+11: AP mode
-+Default: 00b.
-+*/
-+#define MSR_NOLINK				0x00
-+#define MSR_ADHOC				0x01
-+#define MSR_INFRA				0x02
-+#define MSR_AP					0x03
-+
-+/* ----------------------------------------------------------------------------
-+* USB INTR CONTENT
-+* ---------------------------------------------------------------------------- */
-+#define USB_C2H_CMDID_OFFSET					0
-+#define USB_C2H_SEQ_OFFSET					1
-+#define USB_C2H_EVENT_OFFSET					2
-+#define USB_INTR_CPWM_OFFSET					16
-+#define USB_INTR_CONTENT_C2H_OFFSET			0
-+#define USB_INTR_CONTENT_CPWM1_OFFSET		16
-+#define USB_INTR_CONTENT_CPWM2_OFFSET		20
-+#define USB_INTR_CONTENT_HISR_OFFSET			48
-+#define USB_INTR_CONTENT_HISRE_OFFSET		52
-+#define USB_INTR_CONTENT_LENGTH				56
-+
-+
-+/* WOL bit information */
-+#define HAL92C_WOL_PTK_UPDATE_EVENT		BIT(0)
-+#define HAL92C_WOL_GTK_UPDATE_EVENT		BIT(1)
-+#define HAL92C_WOL_DISASSOC_EVENT		BIT(2)
-+#define HAL92C_WOL_DEAUTH_EVENT			BIT(3)
-+#define HAL92C_WOL_FW_DISCONNECT_EVENT	BIT(4)
-+
-+
-+/*----------------------------------------------------------------------------
-+**      REG_CCK_CHECK						(offset 0x454)
-+------------------------------------------------------------------------------*/
-+#define BIT_BCN_PORT_SEL		BIT(5)
-+#define BIT_EN_BCN_PKT_REL		BIT(6)
-+
-+#endif /* RTW_HALMAC */
-+
-+/* ----------------------------------------------------------------------------
-+* Response Rate Set Register	(offset 0x440, 24bits)
-+* ---------------------------------------------------------------------------- */
-+#define RRSR_1M					BIT(0)
-+#define RRSR_2M					BIT(1)
-+#define RRSR_5_5M				BIT(2)
-+#define RRSR_11M				BIT(3)
-+#define RRSR_6M					BIT(4)
-+#define RRSR_9M					BIT(5)
-+#define RRSR_12M				BIT(6)
-+#define RRSR_18M				BIT(7)
-+#define RRSR_24M				BIT(8)
-+#define RRSR_36M				BIT(9)
-+#define RRSR_48M				BIT(10)
-+#define RRSR_54M				BIT(11)
-+#define RRSR_MCS0				BIT(12)
-+#define RRSR_MCS1				BIT(13)
-+#define RRSR_MCS2				BIT(14)
-+#define RRSR_MCS3				BIT(15)
-+#define RRSR_MCS4				BIT(16)
-+#define RRSR_MCS5				BIT(17)
-+#define RRSR_MCS6				BIT(18)
-+#define RRSR_MCS7				BIT(19)
-+
-+#define RRSR_CCK_RATES (RRSR_11M | RRSR_5_5M | RRSR_2M | RRSR_1M)
-+#define RRSR_OFDM_RATES (RRSR_54M | RRSR_48M | RRSR_36M | RRSR_24M | RRSR_18M | RRSR_12M | RRSR_9M | RRSR_6M)
-+
-+/* ----------------------------------------------------------------------------
-+ * Rate Definition
-+ * ---------------------------------------------------------------------------- */
-+/* CCK */
-+#define	RATR_1M					0x00000001
-+#define	RATR_2M					0x00000002
-+#define	RATR_55M					0x00000004
-+#define	RATR_11M					0x00000008
-+/* OFDM		 */
-+#define	RATR_6M					0x00000010
-+#define	RATR_9M					0x00000020
-+#define	RATR_12M					0x00000040
-+#define	RATR_18M					0x00000080
-+#define	RATR_24M					0x00000100
-+#define	RATR_36M					0x00000200
-+#define	RATR_48M					0x00000400
-+#define	RATR_54M					0x00000800
-+/* MCS 1 Spatial Stream	 */
-+#define	RATR_MCS0					0x00001000
-+#define	RATR_MCS1					0x00002000
-+#define	RATR_MCS2					0x00004000
-+#define	RATR_MCS3					0x00008000
-+#define	RATR_MCS4					0x00010000
-+#define	RATR_MCS5					0x00020000
-+#define	RATR_MCS6					0x00040000
-+#define	RATR_MCS7					0x00080000
-+/* MCS 2 Spatial Stream */
-+#define	RATR_MCS8					0x00100000
-+#define	RATR_MCS9					0x00200000
-+#define	RATR_MCS10					0x00400000
-+#define	RATR_MCS11					0x00800000
-+#define	RATR_MCS12					0x01000000
-+#define	RATR_MCS13					0x02000000
-+#define	RATR_MCS14					0x04000000
-+#define	RATR_MCS15					0x08000000
-+
-+/* CCK */
-+#define RATE_1M					BIT(0)
-+#define RATE_2M					BIT(1)
-+#define RATE_5_5M				BIT(2)
-+#define RATE_11M				BIT(3)
-+/* OFDM */
-+#define RATE_6M					BIT(4)
-+#define RATE_9M					BIT(5)
-+#define RATE_12M				BIT(6)
-+#define RATE_18M				BIT(7)
-+#define RATE_24M				BIT(8)
-+#define RATE_36M				BIT(9)
-+#define RATE_48M				BIT(10)
-+#define RATE_54M				BIT(11)
-+/* MCS 1 Spatial Stream */
-+#define RATE_MCS0				BIT(12)
-+#define RATE_MCS1				BIT(13)
-+#define RATE_MCS2				BIT(14)
-+#define RATE_MCS3				BIT(15)
-+#define RATE_MCS4				BIT(16)
-+#define RATE_MCS5				BIT(17)
-+#define RATE_MCS6				BIT(18)
-+#define RATE_MCS7				BIT(19)
-+/* MCS 2 Spatial Stream */
-+#define RATE_MCS8				BIT(20)
-+#define RATE_MCS9				BIT(21)
-+#define RATE_MCS10				BIT(22)
-+#define RATE_MCS11				BIT(23)
-+#define RATE_MCS12				BIT(24)
-+#define RATE_MCS13				BIT(25)
-+#define RATE_MCS14				BIT(26)
-+#define RATE_MCS15				BIT(27)
-+
-+
-+/* ALL CCK Rate */
-+#define	RATE_ALL_CCK				(RATR_1M | RATR_2M | RATR_55M | RATR_11M)
-+#define	RATE_ALL_OFDM_AG			(RATR_6M | RATR_9M | RATR_12M | RATR_18M | RATR_24M|\
-+	RATR_36M | RATR_48M | RATR_54M)
-+#define	RATE_ALL_OFDM_1SS			(RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | RATR_MCS3 |\
-+	RATR_MCS4 | RATR_MCS5 | RATR_MCS6 | RATR_MCS7)
-+#define	RATE_ALL_OFDM_2SS			(RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | RATR_MCS11|\
-+	RATR_MCS12 | RATR_MCS13 | RATR_MCS14 | RATR_MCS15)
-+
-+#define RATE_BITMAP_ALL			0xFFFFF
-+
-+/* Only use CCK 1M rate for ACK */
-+#define RATE_RRSR_CCK_ONLY_1M		0xFFFF1
-+#define RATE_RRSR_WITHOUT_CCK		0xFFFF0
-+
-+/* ----------------------------------------------------------------------------
-+ * BW_OPMODE bits				(Offset 0x603, 8bit)
-+ * ---------------------------------------------------------------------------- */
-+#define BW_OPMODE_20MHZ			BIT(2)
-+#define BW_OPMODE_5G				BIT(1)
-+
-+/* ----------------------------------------------------------------------------
-+ * CAM Config Setting (offset 0x680, 1 byte)
-+ * ----------------------------------------------------------------------------			 */
-+#define CAM_VALID				BIT(15)
-+#define CAM_NOTVALID			0x0000
-+#define CAM_USEDK				BIT(5)
-+
-+#define CAM_CONTENT_COUNT	8
-+
-+#define CAM_NONE				0x0
-+#define CAM_WEP40				0x01
-+#define CAM_TKIP				0x02
-+#define CAM_AES					0x04
-+#define CAM_WEP104				0x05
-+#define CAM_SMS4				0x6
-+
-+#define TOTAL_CAM_ENTRY		32
-+#define HALF_CAM_ENTRY			16
-+
-+#define CAM_CONFIG_USEDK		_TRUE
-+#define CAM_CONFIG_NO_USEDK	_FALSE
-+
-+#define CAM_WRITE				BIT(16)
-+#define CAM_READ				0x00000000
-+#define CAM_POLLINIG			BIT(31)
-+
-+/*
-+ * 10. Power Save Control Registers
-+ *   */
-+#define WOW_PMEN				BIT(0) /* Power management Enable. */
-+#define WOW_WOMEN				BIT(1) /* WoW function on or off. */
-+#define WOW_MAGIC				BIT(2) /* Magic packet */
-+#define WOW_UWF				BIT(3) /* Unicast Wakeup frame. */
-+
-+/*
-+ * 12. Host Interrupt Status Registers
-+ *
-+ * ----------------------------------------------------------------------------
-+ * 8190 IMR/ISR bits
-+ * ---------------------------------------------------------------------------- */
-+#define IMR8190_DISABLED		0x0
-+#define IMR_DISABLED			0x0
-+/* IMR DW0 Bit 0-31 */
-+#define IMR_BCNDMAINT6			BIT(31)		/* Beacon DMA Interrupt 6 */
-+#define IMR_BCNDMAINT5			BIT(30)		/* Beacon DMA Interrupt 5 */
-+#define IMR_BCNDMAINT4			BIT(29)		/* Beacon DMA Interrupt 4 */
-+#define IMR_BCNDMAINT3			BIT(28)		/* Beacon DMA Interrupt 3 */
-+#define IMR_BCNDMAINT2			BIT(27)		/* Beacon DMA Interrupt 2 */
-+#define IMR_BCNDMAINT1			BIT(26)		/* Beacon DMA Interrupt 1 */
-+#define IMR_BCNDOK8				BIT(25)		/* Beacon Queue DMA OK Interrupt 8 */
-+#define IMR_BCNDOK7				BIT(24)		/* Beacon Queue DMA OK Interrupt 7 */
-+#define IMR_BCNDOK6				BIT(23)		/* Beacon Queue DMA OK Interrupt 6 */
-+#define IMR_BCNDOK5				BIT(22)		/* Beacon Queue DMA OK Interrupt 5 */
-+#define IMR_BCNDOK4				BIT(21)		/* Beacon Queue DMA OK Interrupt 4 */
-+#define IMR_BCNDOK3				BIT(20)		/* Beacon Queue DMA OK Interrupt 3 */
-+#define IMR_BCNDOK2				BIT(19)		/* Beacon Queue DMA OK Interrupt 2 */
-+#define IMR_BCNDOK1				BIT(18)		/* Beacon Queue DMA OK Interrupt 1 */
-+#define IMR_TIMEOUT2			BIT(17)		/* Timeout interrupt 2 */
-+#define IMR_TIMEOUT1			BIT(16)		/* Timeout interrupt 1 */
-+#define IMR_TXFOVW				BIT(15)		/* Transmit FIFO Overflow */
-+#define IMR_PSTIMEOUT			BIT(14)		/* Power save time out interrupt */
-+#define IMR_BcnInt				BIT(13)		/* Beacon DMA Interrupt 0 */
-+#define IMR_RXFOVW				BIT(12)		/* Receive FIFO Overflow */
-+#define IMR_RDU					BIT(11)		/* Receive Descriptor Unavailable */
-+#define IMR_ATIMEND				BIT(10)		/* For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. */
-+#define IMR_BDOK				BIT(9)		/* Beacon Queue DMA OK Interrupt */
-+#define IMR_HIGHDOK				BIT(8)		/* High Queue DMA OK Interrupt */
-+#define IMR_TBDOK				BIT(7)		/* Transmit Beacon OK interrupt */
-+#define IMR_MGNTDOK			BIT(6)		/* Management Queue DMA OK Interrupt */
-+#define IMR_TBDER				BIT(5)		/* For 92C, Transmit Beacon Error Interrupt */
-+#define IMR_BKDOK				BIT(4)		/* AC_BK DMA OK Interrupt */
-+#define IMR_BEDOK				BIT(3)		/* AC_BE DMA OK Interrupt */
-+#define IMR_VIDOK				BIT(2)		/* AC_VI DMA OK Interrupt */
-+#define IMR_VODOK				BIT(1)		/* AC_VO DMA Interrupt */
-+#define IMR_ROK					BIT(0)		/* Receive DMA OK Interrupt */
-+
-+/* 13. Host Interrupt Status Extension Register	 (Offset: 0x012C-012Eh) */
-+#define IMR_TSF_BIT32_TOGGLE	BIT(15)
-+#define IMR_BcnInt_E				BIT(12)
-+#define IMR_TXERR				BIT(11)
-+#define IMR_RXERR				BIT(10)
-+#define IMR_C2HCMD				BIT(9)
-+#define IMR_CPWM				BIT(8)
-+/* RSVD [2-7] */
-+#define IMR_OCPINT				BIT(1)
-+#define IMR_WLANOFF			BIT(0)
-+
-+/* ----------------------------------------------------------------------------
-+ * 8723E series PCIE Host IMR/ISR bit
-+ * ---------------------------------------------------------------------------- */
-+/* IMR DW0 Bit 0-31 */
-+#define PHIMR_TIMEOUT2				BIT(31)
-+#define PHIMR_TIMEOUT1				BIT(30)
-+#define PHIMR_PSTIMEOUT			BIT(29)
-+#define PHIMR_GTINT4				BIT(28)
-+#define PHIMR_GTINT3				BIT(27)
-+#define PHIMR_TXBCNERR				BIT(26)
-+#define PHIMR_TXBCNOK				BIT(25)
-+#define PHIMR_TSF_BIT32_TOGGLE	BIT(24)
-+#define PHIMR_BCNDMAINT3			BIT(23)
-+#define PHIMR_BCNDMAINT2			BIT(22)
-+#define PHIMR_BCNDMAINT1			BIT(21)
-+#define PHIMR_BCNDMAINT0			BIT(20)
-+#define PHIMR_BCNDOK3				BIT(19)
-+#define PHIMR_BCNDOK2				BIT(18)
-+#define PHIMR_BCNDOK1				BIT(17)
-+#define PHIMR_BCNDOK0				BIT(16)
-+#define PHIMR_HSISR_IND_ON			BIT(15)
-+#define PHIMR_BCNDMAINT_E			BIT(14)
-+#define PHIMR_ATIMEND_E			BIT(13)
-+#define PHIMR_ATIM_CTW_END		BIT(12)
-+#define PHIMR_HISRE_IND			BIT(11)	/* RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) */
-+#define PHIMR_C2HCMD				BIT(10)
-+#define PHIMR_CPWM2				BIT(9)
-+#define PHIMR_CPWM					BIT(8)
-+#define PHIMR_HIGHDOK				BIT(7)		/* High Queue DMA OK Interrupt */
-+#define PHIMR_MGNTDOK				BIT(6)		/* Management Queue DMA OK Interrupt */
-+#define PHIMR_BKDOK					BIT(5)		/* AC_BK DMA OK Interrupt */
-+#define PHIMR_BEDOK					BIT(4)		/* AC_BE DMA OK Interrupt */
-+#define PHIMR_VIDOK					BIT(3)		/* AC_VI DMA OK Interrupt */
-+#define PHIMR_VODOK				BIT(2)		/* AC_VO DMA Interrupt */
-+#define PHIMR_RDU					BIT(1)		/* Receive Descriptor Unavailable */
-+#define PHIMR_ROK					BIT(0)		/* Receive DMA OK Interrupt */
-+
-+/* PCIE Host Interrupt Status Extension bit */
-+#define PHIMR_BCNDMAINT7			BIT(23)
-+#define PHIMR_BCNDMAINT6			BIT(22)
-+#define PHIMR_BCNDMAINT5			BIT(21)
-+#define PHIMR_BCNDMAINT4			BIT(20)
-+#define PHIMR_BCNDOK7				BIT(19)
-+#define PHIMR_BCNDOK6				BIT(18)
-+#define PHIMR_BCNDOK5				BIT(17)
-+#define PHIMR_BCNDOK4				BIT(16)
-+/* bit12 15: RSVD */
-+#define PHIMR_TXERR					BIT(11)
-+#define PHIMR_RXERR					BIT(10)
-+#define PHIMR_TXFOVW				BIT(9)
-+#define PHIMR_RXFOVW				BIT(8)
-+/* bit2-7: RSVD */
-+#define PHIMR_OCPINT				BIT(1)
-+/* bit0: RSVD */
-+
-+#define UHIMR_TIMEOUT2				BIT(31)
-+#define UHIMR_TIMEOUT1				BIT(30)
-+#define UHIMR_PSTIMEOUT			BIT(29)
-+#define UHIMR_GTINT4				BIT(28)
-+#define UHIMR_GTINT3				BIT(27)
-+#define UHIMR_TXBCNERR				BIT(26)
-+#define UHIMR_TXBCNOK				BIT(25)
-+#define UHIMR_TSF_BIT32_TOGGLE	BIT(24)
-+#define UHIMR_BCNDMAINT3			BIT(23)
-+#define UHIMR_BCNDMAINT2			BIT(22)
-+#define UHIMR_BCNDMAINT1			BIT(21)
-+#define UHIMR_BCNDMAINT0			BIT(20)
-+#define UHIMR_BCNDOK3				BIT(19)
-+#define UHIMR_BCNDOK2				BIT(18)
-+#define UHIMR_BCNDOK1				BIT(17)
-+#define UHIMR_BCNDOK0				BIT(16)
-+#define UHIMR_HSISR_IND			BIT(15)
-+#define UHIMR_BCNDMAINT_E			BIT(14)
-+/* RSVD	BIT(13) */
-+#define UHIMR_CTW_END				BIT(12)
-+/* RSVD	BIT(11) */
-+#define UHIMR_C2HCMD				BIT(10)
-+#define UHIMR_CPWM2				BIT(9)
-+#define UHIMR_CPWM					BIT(8)
-+#define UHIMR_HIGHDOK				BIT(7)		/* High Queue DMA OK Interrupt */
-+#define UHIMR_MGNTDOK				BIT(6)		/* Management Queue DMA OK Interrupt */
-+#define UHIMR_BKDOK				BIT(5)		/* AC_BK DMA OK Interrupt */
-+#define UHIMR_BEDOK				BIT(4)		/* AC_BE DMA OK Interrupt */
-+#define UHIMR_VIDOK					BIT(3)		/* AC_VI DMA OK Interrupt */
-+#define UHIMR_VODOK				BIT(2)		/* AC_VO DMA Interrupt */
-+#define UHIMR_RDU					BIT(1)		/* Receive Descriptor Unavailable */
-+#define UHIMR_ROK					BIT(0)		/* Receive DMA OK Interrupt */
-+
-+/* USB Host Interrupt Status Extension bit */
-+#define UHIMR_BCNDMAINT7			BIT(23)
-+#define UHIMR_BCNDMAINT6			BIT(22)
-+#define UHIMR_BCNDMAINT5			BIT(21)
-+#define UHIMR_BCNDMAINT4			BIT(20)
-+#define UHIMR_BCNDOK7				BIT(19)
-+#define UHIMR_BCNDOK6				BIT(18)
-+#define UHIMR_BCNDOK5				BIT(17)
-+#define UHIMR_BCNDOK4				BIT(16)
-+/* bit14-15: RSVD */
-+#define UHIMR_ATIMEND_E			BIT(13)
-+#define UHIMR_ATIMEND				BIT(12)
-+#define UHIMR_TXERR					BIT(11)
-+#define UHIMR_RXERR					BIT(10)
-+#define UHIMR_TXFOVW				BIT(9)
-+#define UHIMR_RXFOVW				BIT(8)
-+/* bit2-7: RSVD */
-+#define UHIMR_OCPINT				BIT(1)
-+/* bit0: RSVD */
-+
-+
-+#define HAL_NIC_UNPLUG_ISR			0xFFFFFFFF	/* The value when the NIC is unplugged for PCI. */
-+#define HAL_NIC_UNPLUG_PCI_ISR		0xEAEAEAEA	/* The value when the NIC is unplugged for PCI in PCI interrupt (page 3). */
-+
-+/* ----------------------------------------------------------------------------
-+ * 8188 IMR/ISR bits
-+ * ---------------------------------------------------------------------------- */
-+#define IMR_DISABLED_88E			0x0
-+/* IMR DW0(0x0060-0063) Bit 0-31 */
-+#define IMR_TXCCK_88E				BIT(30)		/* TXRPT interrupt when CCX bit of the packet is set	 */
-+#define IMR_PSTIMEOUT_88E			BIT(29)		/* Power Save Time Out Interrupt */
-+#define IMR_GTINT4_88E				BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
-+#define IMR_GTINT3_88E				BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
-+#define IMR_TBDER_88E				BIT(26)		/* Transmit Beacon0 Error			 */
-+#define IMR_TBDOK_88E				BIT(25)		/* Transmit Beacon0 OK			 */
-+#define IMR_TSF_BIT32_TOGGLE_88E	BIT(24)		/* TSF Timer BIT32 toggle indication interrupt			 */
-+#define IMR_BCNDMAINT0_88E		BIT(20)		/* Beacon DMA Interrupt 0			 */
-+#define IMR_BCNDERR0_88E			BIT(16)		/* Beacon Queue DMA Error 0 */
-+#define IMR_HSISR_IND_ON_INT_88E	BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)			 */
-+#define IMR_BCNDMAINT_E_88E		BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
-+#define IMR_ATIMEND_88E			BIT(12)		/* CTWidnow End or ATIM Window End */
-+#define IMR_HISR1_IND_INT_88E		BIT(11)		/* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */
-+#define IMR_C2HCMD_88E				BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
-+#define IMR_CPWM2_88E				BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
-+#define IMR_CPWM_88E				BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
-+#define IMR_HIGHDOK_88E			BIT(7)			/* High Queue DMA OK	 */
-+#define IMR_MGNTDOK_88E			BIT(6)			/* Management Queue DMA OK	 */
-+#define IMR_BKDOK_88E				BIT(5)			/* AC_BK DMA OK		 */
-+#define IMR_BEDOK_88E				BIT(4)			/* AC_BE DMA OK	 */
-+#define IMR_VIDOK_88E				BIT(3)			/* AC_VI DMA OK		 */
-+#define IMR_VODOK_88E				BIT(2)			/* AC_VO DMA OK	 */
-+#define IMR_RDU_88E					BIT(1)			/* Rx Descriptor Unavailable	 */
-+#define IMR_ROK_88E					BIT(0)			/* Receive DMA OK */
-+
-+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
-+#define IMR_BCNDMAINT7_88E		BIT(27)		/* Beacon DMA Interrupt 7 */
-+#define IMR_BCNDMAINT6_88E		BIT(26)		/* Beacon DMA Interrupt 6 */
-+#define IMR_BCNDMAINT5_88E		BIT(25)		/* Beacon DMA Interrupt 5 */
-+#define IMR_BCNDMAINT4_88E		BIT(24)		/* Beacon DMA Interrupt 4 */
-+#define IMR_BCNDMAINT3_88E		BIT(23)		/* Beacon DMA Interrupt 3 */
-+#define IMR_BCNDMAINT2_88E		BIT(22)		/* Beacon DMA Interrupt 2 */
-+#define IMR_BCNDMAINT1_88E		BIT(21)		/* Beacon DMA Interrupt 1 */
-+#define IMR_BCNDOK7_88E			BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
-+#define IMR_BCNDOK6_88E			BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
-+#define IMR_BCNDOK5_88E			BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
-+#define IMR_BCNDOK4_88E			BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
-+#define IMR_BCNDOK3_88E			BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
-+#define IMR_BCNDOK2_88E			BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
-+#define IMR_BCNDOK1_88E			BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
-+#define IMR_ATIMEND_E_88E			BIT(13)		/* ATIM Window End Extension for Win7 */
-+#define IMR_TXERR_88E				BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
-+#define IMR_RXERR_88E				BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
-+#define IMR_TXFOVW_88E				BIT(9)			/* Transmit FIFO Overflow */
-+#define IMR_RXFOVW_88E				BIT(8)			/* Receive FIFO Overflow */
-+
-+/*===================================================================
-+=====================================================================
-+Here the register defines are for 92C. When the define is as same with 92C,
-+we will use the 92C's define for the consistency
-+So the following defines for 92C is not entire!!!!!!
-+=====================================================================
-+=====================================================================*/
-+/*
-+Based on Datasheet V33---090401
-+Register Summary
-+Current IOREG MAP
-+0x0000h ~ 0x00FFh   System Configuration (256 Bytes)
-+0x0100h ~ 0x01FFh   MACTOP General Configuration (256 Bytes)
-+0x0200h ~ 0x027Fh   TXDMA Configuration (128 Bytes)
-+0x0280h ~ 0x02FFh   RXDMA Configuration (128 Bytes)
-+0x0300h ~ 0x03FFh   PCIE EMAC Reserved Region (256 Bytes)
-+0x0400h ~ 0x04FFh   Protocol Configuration (256 Bytes)
-+0x0500h ~ 0x05FFh   EDCA Configuration (256 Bytes)
-+0x0600h ~ 0x07FFh   WMAC Configuration (512 Bytes)
-+0x2000h ~ 0x3FFFh   8051 FW Download Region (8196 Bytes)
-+*/
-+/* ---------------------------------------------------------------------------- */
-+/*		 8192C (TXPAUSE) transmission pause 	(Offset 0x522, 8 bits) */
-+/* ---------------------------------------------------------------------------- */
-+/* Note:
-+*	The the bits of stoping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong,
-+*	the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3.
-+*	8723 and 88E may be not correct either in the eralier version. Confirmed with DD Tim.
-+* By Bruce, 2011-09-22. */
-+#define StopBecon		BIT(6)
-+#define StopHigh			BIT(5)
-+#define StopMgt			BIT(4)
-+#define StopBK			BIT(3)
-+#define StopBE			BIT(2)
-+#define StopVI			BIT(1)
-+#define StopVO			BIT(0)
-+
-+/* ----------------------------------------------------------------------------
-+ * 8192C (RCR) Receive Configuration Register	(Offset 0x608, 32 bits)
-+ * ---------------------------------------------------------------------------- */
-+#define RCR_APPFCS				BIT(31)	/* WMAC append FCS after pauload */
-+#define RCR_APP_MIC				BIT(30)	/* MACRX will retain the MIC at the bottom of the packet. */
-+#define RCR_APP_ICV				BIT(29)	/* MACRX will retain the ICV at the bottom of the packet. */
-+#define RCR_APP_PHYST_RXFF		BIT(28)	/* PHY Status is appended before RX packet in RXFF */
-+#define RCR_APP_BA_SSN			BIT(27)	/* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */
-+#define RCR_VHT_DACK			BIT(26)	/* This bit to control response type for vht single mpdu data packet. 1. ACK as response 0. BA as response */
-+#define RCR_TCPOFLD_EN			BIT(25)	/* Enable TCP checksum offload */
-+#define RCR_ENMBID				BIT(24)	/* Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. */
-+#define RCR_LSIGEN				BIT(23)	/* Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. */
-+#define RCR_MFBEN				BIT(22)	/* Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. */
-+#define RCR_DISCHKPPDLLEN		BIT(21)	/* Do not check PPDU while the PPDU length is smaller than 14 byte. */
-+#define RCR_PKTCTL_DLEN			BIT(20)	/* While rx path dead lock occurs, reset rx path */
-+#define RCR_DISGCLK				BIT(19)	/* Disable macrx clock gating control (no used) */
-+#define RCR_TIM_PARSER_EN		BIT(18)	/* RX Beacon TIM Parser. */
-+#define RCR_BC_MD_EN			BIT(17)	/* Broadcast data packet more data bit check interrupt enable.*/
-+#define RCR_UC_MD_EN			BIT(16)	/* Unicast data packet more data bit check interrupt enable. */
-+#define RCR_RXSK_PERPKT			BIT(15)	/* Executing key search per MPDU */
-+#define RCR_HTC_LOC_CTRL		BIT(14)	/* MFC<--HTC = 1 MFC-->HTC = 0 */
-+#define RCR_AMF					BIT(13)	/* Accept management type frame */
-+#define RCR_ACF					BIT(12)	/* Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */
-+#define RCR_ADF					BIT(11)	/* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */
-+#define RCR_DISDECMYPKT			BIT(10)	/* This bit determines whether hw need to do decryption.1: If A1 match, do decryption.0: Do decryption. */
-+#define RCR_AICV					BIT(9)		/* Accept ICV error packet */
-+#define RCR_ACRC32				BIT(8)		/* Accept CRC32 error packet */
-+#define RCR_CBSSID_BCN			BIT(7)		/* Accept BSSID match packet (Rx beacon, probe rsp) */
-+#define RCR_CBSSID_DATA		BIT(6)		/* Accept BSSID match packet (Data) */
-+#define RCR_APWRMGT			BIT(5)		/* Accept power management packet */
-+#define RCR_ADD3				BIT(4)		/* Accept address 3 match packet */
-+#define RCR_AB					BIT(3)		/* Accept broadcast packet */
-+#define RCR_AM					BIT(2)		/* Accept multicast packet */
-+#define RCR_APM					BIT(1)		/* Accept physical match packet */
-+#define RCR_AAP					BIT(0)		/* Accept all unicast packet */
-+
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0000h ~ 0x00FFh	System Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* 2 SYS_ISO_CTRL */
-+#define ISO_MD2PP				BIT(0)
-+#define ISO_UA2USB				BIT(1)
-+#define ISO_UD2CORE				BIT(2)
-+#define ISO_PA2PCIE				BIT(3)
-+#define ISO_PD2CORE				BIT(4)
-+#define ISO_IP2MAC				BIT(5)
-+#define ISO_DIOP					BIT(6)
-+#define ISO_DIOE					BIT(7)
-+#define ISO_EB2CORE				BIT(8)
-+#define ISO_DIOR					BIT(9)
-+#define PWC_EV12V				BIT(15)
-+
-+
-+/* 2 SYS_FUNC_EN */
-+#define FEN_BBRSTB				BIT(0)
-+#define FEN_BB_GLB_RSTn		BIT(1)
-+#define FEN_USBA				BIT(2)
-+#define FEN_UPLL				BIT(3)
-+#define FEN_USBD				BIT(4)
-+#define FEN_DIO_PCIE			BIT(5)
-+#define FEN_PCIEA				BIT(6)
-+#define FEN_PPLL					BIT(7)
-+#define FEN_PCIED				BIT(8)
-+#define FEN_DIOE				BIT(9)
-+#define FEN_CPUEN				BIT(10)
-+#define FEN_DCORE				BIT(11)
-+#define FEN_ELDR				BIT(12)
-+#define FEN_EN_25_1				BIT(13)
-+#define FEN_HWPDN				BIT(14)
-+#define FEN_MREGEN				BIT(15)
-+
-+/* 2 APS_FSMCO */
-+#define PFM_LDALL				BIT(0)
-+#define PFM_ALDN				BIT(1)
-+#define PFM_LDKP				BIT(2)
-+#define PFM_WOWL				BIT(3)
-+#define EnPDN					BIT(4)
-+#define PDN_PL					BIT(5)
-+#define APFM_ONMAC				BIT(8)
-+#define APFM_OFF				BIT(9)
-+#define APFM_RSM				BIT(10)
-+#define AFSM_HSUS				BIT(11)
-+#define AFSM_PCIE				BIT(12)
-+#define APDM_MAC				BIT(13)
-+#define APDM_HOST				BIT(14)
-+#define APDM_HPDN				BIT(15)
-+#define RDY_MACON				BIT(16)
-+#define SUS_HOST				BIT(17)
-+#define ROP_ALD					BIT(20)
-+#define ROP_PWR					BIT(21)
-+#define ROP_SPS					BIT(22)
-+#define SOP_MRST				BIT(25)
-+#define SOP_FUSE				BIT(26)
-+#define SOP_ABG					BIT(27)
-+#define SOP_AMB					BIT(28)
-+#define SOP_RCK					BIT(29)
-+#define SOP_A8M					BIT(30)
-+#define XOP_BTCK				BIT(31)
-+
-+/* 2 SYS_CLKR */
-+#define ANAD16V_EN				BIT(0)
-+#define ANA8M					BIT(1)
-+#define MACSLP					BIT(4)
-+#define LOADER_CLK_EN			BIT(5)
-+
-+
-+/* 2 9346CR /REG_SYS_EEPROM_CTRL */
-+#define BOOT_FROM_EEPROM		BIT(4)
-+#define EEPROMSEL				BIT(4)
-+#define EEPROM_EN				BIT(5)
-+
-+
-+/* 2 RF_CTRL */
-+#define RF_EN					BIT(0)
-+#define RF_RSTB					BIT(1)
-+#define RF_SDMRSTB				BIT(2)
-+
-+
-+/* 2 LDOV12D_CTRL */
-+#define LDV12_EN				BIT(0)
-+#define LDV12_SDBY				BIT(1)
-+#define LPLDO_HSM				BIT(2)
-+#define LPLDO_LSM_DIS			BIT(3)
-+#define _LDV12_VADJ(x)			(((x) & 0xF) << 4)
-+
-+
-+
-+/* 2 EFUSE_TEST (For RTL8723 partially) */
-+#define EF_TRPT					BIT(7)
-+#define EF_CELL_SEL				(BIT(8) | BIT(9)) /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
-+#define LDOE25_EN				BIT(31)
-+#define EFUSE_SEL(x)				(((x) & 0x3) << 8)
-+#define EFUSE_SEL_MASK			0x300
-+#define EFUSE_WIFI_SEL_0		0x0
-+#define EFUSE_BT_SEL_0			0x1
-+#define EFUSE_BT_SEL_1			0x2
-+#define EFUSE_BT_SEL_2			0x3
-+
-+/* 2 REG_GPIO_INTM				(Offset 0x0048) */
-+#define BIT_EXTWOL_EN 			BIT(16)
-+
-+/* 2 REG_LED_CFG				(Offset 0x004C) */
-+#define BIT_SW_SPDT_SEL			BIT(22)
-+
-+/* 2 REG_SW_GPIO_SHARE_CTRL_0	(Offset 0x1038) */
-+#define BIT_BTGP_WAKE_LOC		(BIT(10) | BIT(11))
-+#define BIT_SW_GPIO_FUNC 		BIT(0)
-+
-+/* 2 REG_SW_GPIO_SHARE_CTRL_1	(Offset 0x103C) */
-+#define 	BIT_WLMAC_DBG_LOC	(BIT(9) | BIT(10))
-+#define 	BIT_WL_GPIO_SEL		(BIT(30) | BIT(31))
-+
-+/* 2 8051FWDL
-+ * 2 MCUFWDL */
-+#define MCUFWDL_EN				BIT(0)
-+#define MCUFWDL_RDY			BIT(1)
-+#define FWDL_ChkSum_rpt		BIT(2)
-+#define MACINI_RDY				BIT(3)
-+#define BBINI_RDY				BIT(4)
-+#define RFINI_RDY				BIT(5)
-+#define WINTINI_RDY				BIT(6)
-+#define RAM_DL_SEL				BIT(7)
-+#define CPU_DL_READY			BIT(15) /* add flag  by gw for fw download ready 20130826 */
-+#define ROM_DLEN				BIT(19)
-+#define CPRST					BIT(23)
-+
-+
-+/* 2 REG_SYS_CFG */
-+#define XCLK_VLD				BIT(0)
-+#define ACLK_VLD				BIT(1)
-+#define UCLK_VLD				BIT(2)
-+#define PCLK_VLD				BIT(3)
-+#define PCIRSTB					BIT(4)
-+#define V15_VLD					BIT(5)
-+#define SW_OFFLOAD_EN			BIT(7)
-+#define SIC_IDLE					BIT(8)
-+#define BD_MAC2					BIT(9)
-+#define BD_MAC1					BIT(10)
-+#define IC_MACPHY_MODE		BIT(11)
-+#define CHIP_VER				(BIT(12) | BIT(13) | BIT(14) | BIT(15))
-+#define BT_FUNC					BIT(16)
-+#define VENDOR_ID				BIT(19)
-+#define EXT_VENDOR_ID			(BIT(18) | BIT(19)) /* Currently only for RTL8723B */
-+#define PAD_HWPD_IDN			BIT(22)
-+#define TRP_VAUX_EN				BIT(23)	/* RTL ID */
-+#define TRP_BT_EN				BIT(24)
-+#define BD_PKG_SEL				BIT(25)
-+#define BD_HCI_SEL				BIT(26)
-+#define TYPE_ID					BIT(27)
-+#define RF_TYPE_ID				BIT(27)
-+
-+#define RTL_ID					BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */
-+#define SPS_SEL					BIT(24) /* 1:LDO regulator mode; 0:Switching regulator mode */
-+
-+
-+#define CHIP_VER_RTL_MASK		0xF000	/* Bit 12 ~ 15 */
-+#define CHIP_VER_RTL_SHIFT		12
-+#define EXT_VENDOR_ID_SHIFT	18
-+
-+/* 2 REG_GPIO_OUTSTS (For RTL8723 only) */
-+#define EFS_HCI_SEL				(BIT(0) | BIT(1))
-+#define PAD_HCI_SEL				(BIT(2) | BIT(3))
-+#define HCI_SEL					(BIT(4) | BIT(5))
-+#define PKG_SEL_HCI				BIT(6)
-+#define FEN_GPS					BIT(7)
-+#define FEN_BT					BIT(8)
-+#define FEN_WL					BIT(9)
-+#define FEN_PCI					BIT(10)
-+#define FEN_USB					BIT(11)
-+#define BTRF_HWPDN_N			BIT(12)
-+#define WLRF_HWPDN_N			BIT(13)
-+#define PDN_BT_N				BIT(14)
-+#define PDN_GPS_N				BIT(15)
-+#define BT_CTL_HWPDN			BIT(16)
-+#define GPS_CTL_HWPDN			BIT(17)
-+#define PPHY_SUSB				BIT(20)
-+#define UPHY_SUSB				BIT(21)
-+#define PCI_SUSEN				BIT(22)
-+#define USB_SUSEN				BIT(23)
-+#define RF_RL_ID					(BIT(31) | BIT(30) | BIT(29) | BIT(28))
-+
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* 2 Function Enable Registers
-+ * 2 CR */
-+#define HCI_TXDMA_EN			BIT(0)
-+#define HCI_RXDMA_EN			BIT(1)
-+#define TXDMA_EN				BIT(2)
-+#define RXDMA_EN				BIT(3)
-+#define PROTOCOL_EN				BIT(4)
-+#define SCHEDULE_EN				BIT(5)
-+#define MACTXEN					BIT(6)
-+#define MACRXEN					BIT(7)
-+#define ENSWBCN					BIT(8)
-+#define ENSEC					BIT(9)
-+#define CALTMR_EN				BIT(10)	/* 32k CAL TMR enable */
-+
-+/* Network type */
-+#define _NETTYPE(x)				(((x) & 0x3) << 16)
-+#define MASK_NETTYPE			0x30000
-+#define NT_NO_LINK				0x0
-+#define NT_LINK_AD_HOC			0x1
-+#define NT_LINK_AP				0x2
-+#define NT_AS_AP				0x3
-+
-+/* 2 PBP - Page Size Register */
-+#define GET_RX_PAGE_SIZE(value)			((value) & 0xF)
-+#define GET_TX_PAGE_SIZE(value)			(((value) & 0xF0) >> 4)
-+#define _PSRX_MASK				0xF
-+#define _PSTX_MASK				0xF0
-+#define _PSRX(x)				(x)
-+#define _PSTX(x)				((x) << 4)
-+
-+#define PBP_64					0x0
-+#define PBP_128					0x1
-+#define PBP_256					0x2
-+#define PBP_512					0x3
-+#define PBP_1024				0x4
-+
-+
-+/* 2 TX/RXDMA */
-+#define RXDMA_ARBBW_EN		BIT(0)
-+#define RXSHFT_EN				BIT(1)
-+#define RXDMA_AGG_EN			BIT(2)
-+#define QS_VO_QUEUE			BIT(8)
-+#define QS_VI_QUEUE				BIT(9)
-+#define QS_BE_QUEUE			BIT(10)
-+#define QS_BK_QUEUE			BIT(11)
-+#define QS_MANAGER_QUEUE		BIT(12)
-+#define QS_HIGH_QUEUE			BIT(13)
-+
-+#define HQSEL_VOQ				BIT(0)
-+#define HQSEL_VIQ				BIT(1)
-+#define HQSEL_BEQ				BIT(2)
-+#define HQSEL_BKQ				BIT(3)
-+#define HQSEL_MGTQ				BIT(4)
-+#define HQSEL_HIQ				BIT(5)
-+
-+/* For normal driver, 0x10C */
-+#define _TXDMA_CMQ_MAP(x)			(((x) & 0x3) << 16)
-+#define _TXDMA_HIQ_MAP(x)			(((x) & 0x3) << 14)
-+#define _TXDMA_MGQ_MAP(x)			(((x) & 0x3) << 12)
-+#define _TXDMA_BKQ_MAP(x)			(((x) & 0x3) << 10)
-+#define _TXDMA_BEQ_MAP(x)			(((x) & 0x3) << 8)
-+#define _TXDMA_VIQ_MAP(x)			(((x) & 0x3) << 6)
-+#define _TXDMA_VOQ_MAP(x)			(((x) & 0x3) << 4)
-+
-+#define QUEUE_EXTRA				0
-+#define QUEUE_LOW				1
-+#define QUEUE_NORMAL			2
-+#define QUEUE_HIGH				3
-+#define QUEUE_EXTRA_1			4
-+#define QUEUE_EXTRA_2			5
-+
-+/* 2 TRXFF_BNDY */
-+
-+
-+/* 2 LLT_INIT */
-+#define _LLT_NO_ACTIVE				0x0
-+#define _LLT_WRITE_ACCESS			0x1
-+#define _LLT_READ_ACCESS			0x2
-+
-+#define _LLT_INIT_DATA(x)			((x) & 0xFF)
-+#define _LLT_INIT_ADDR(x)			(((x) & 0xFF) << 8)
-+#define _LLT_OP(x)					(((x) & 0x3) << 30)
-+#define _LLT_OP_VALUE(x)			(((x) >> 30) & 0x3)
-+
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+/* 2 RQPN */
-+#define _HPQ(x)					((x) & 0xFF)
-+#define _LPQ(x)					(((x) & 0xFF) << 8)
-+#define _PUBQ(x)					(((x) & 0xFF) << 16)
-+#define _NPQ(x)					((x) & 0xFF)			/* NOTE: in RQPN_NPQ register */
-+#define _EPQ(x)					(((x) & 0xFF) << 16)	/* NOTE: in RQPN_EPQ register */
-+
-+
-+#define HPQ_PUBLIC_DIS			BIT(24)
-+#define LPQ_PUBLIC_DIS			BIT(25)
-+#define LD_RQPN					BIT(31)
-+
-+
-+/* 2 TDECTL */
-+#define BLK_DESC_NUM_SHIFT			4
-+#define BLK_DESC_NUM_MASK			0xF
-+
-+
-+/* 2 TXDMA_OFFSET_CHK */
-+#define DROP_DATA_EN				BIT(9)
-+
-+/* 2 AUTO_LLT */
-+#define BIT_SHIFT_TXPKTNUM 24
-+#define BIT_MASK_TXPKTNUM 0xff
-+#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM)
-+
-+#define BIT_TDE_DBG_SEL BIT(23)
-+#define BIT_AUTO_INIT_LLT BIT(16)
-+
-+#define BIT_SHIFT_Tx_OQT_free_space 8
-+#define BIT_MASK_Tx_OQT_free_space 0xff
-+#define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space)
-+
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0120h ~ 0x0123h	RX DMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define BIT_FS_RXDONE_INT_EN				BIT(16)
-+
-+
-+/* REG_RXPKT_NUM				(Offset 0x0284) */
-+#define BIT_RW_RELEASE_EN				BIT(18)
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0280h ~ 0x028Bh	RX DMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* 2 REG_RXDMA_CONTROL, 0x0286h
-+ * Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before
-+ * this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear.
-+ * #define RXPKT_RELEASE_POLL			BIT(0)
-+ * Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in
-+ * this bit. FW can start releasing packets after RXDMA entering idle mode.
-+ * #define RXDMA_IDLE					BIT(1)
-+ * When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host
-+ * completed, and stop DMA packet to host. RXDMA will then report Default: 0;
-+ * #define RW_RELEASE_EN				BIT(2) */
-+
-+/* 2 REG_RXPKT_NUM, 0x0284 */
-+#define	RXPKT_RELEASE_POLL	BIT(16)
-+#define	RXDMA_IDLE				BIT(17)
-+#define	RW_RELEASE_EN			BIT(18)
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0400h ~ 0x047Fh	Protocol Configuration
-+ *
-+ * ----------------------------------------------------- */
-+/* 2 FWHW_TXQ_CTRL */
-+#define EN_AMPDU_RTY_NEW			BIT(7)
-+
-+
-+/* 2 SPEC SIFS */
-+#define _SPEC_SIFS_CCK(x)			((x) & 0xFF)
-+#define _SPEC_SIFS_OFDM(x)			(((x) & 0xFF) << 8)
-+
-+/* 2 RL */
-+#define BIT_SHIFT_SRL 8
-+#define BIT_MASK_SRL 0x3f
-+#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL)
-+
-+#define BIT_SHIFT_LRL 0
-+#define BIT_MASK_LRL 0x3f
-+#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL)
-+
-+#define	RL_VAL_AP					7
-+#ifdef CONFIG_RTW_CUSTOMIZE_RLSTA
-+#define	RL_VAL_STA					CONFIG_RTW_CUSTOMIZE_RLSTA
-+#else
-+#define	RL_VAL_STA					0x30
-+#endif
-+/* -----------------------------------------------------
-+ *
-+ *	0x0500h ~ 0x05FFh	EDCA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* 2 EDCA setting */
-+#define AC_PARAM_TXOP_LIMIT_OFFSET		16
-+#define AC_PARAM_ECW_MAX_OFFSET			12
-+#define AC_PARAM_ECW_MIN_OFFSET			8
-+#define AC_PARAM_AIFS_OFFSET				0
-+
-+/* 2 BCN_CTRL */
-+#define EN_TXBCN_RPT			BIT(2)
-+#define EN_BCN_FUNCTION		BIT(3)
-+#define STOP_BCNQ				BIT(6)
-+#define DIS_RX_BSSID_FIT		BIT(6)
-+
-+#define DIS_ATIM					BIT(0)
-+#define DIS_BCNQ_SUB			BIT(1)
-+#define DIS_TSF_UDT				BIT(4)
-+
-+/* 2 ACMHWCTRL */
-+#define AcmHw_HwEn				BIT(0)
-+#define AcmHw_VoqEn			BIT(1)
-+#define AcmHw_ViqEn				BIT(2)
-+#define AcmHw_BeqEn			BIT(3)
-+#define AcmHw_VoqStatus		BIT(5)
-+#define AcmHw_ViqStatus			BIT(6)
-+#define AcmHw_BeqStatus		BIT(7)
-+
-+/* 2 */ /* REG_DUAL_TSF_RST (0x553) */
-+#define DUAL_TSF_RST_P2P		BIT(4)
-+
-+/* 2 */ /* REG_NOA_DESC_SEL (0x5CF) */
-+#define NOA_DESC_SEL_0			0
-+#define NOA_DESC_SEL_1			BIT(4)
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0600h ~ 0x07FFh	WMAC Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* 2 APSD_CTRL */
-+#define APSDOFF					BIT(6)
-+
-+/* 2 TCR */
-+#define TSFRST					BIT(0)
-+#define DIS_GCLK					BIT(1)
-+#define PAD_SEL					BIT(2)
-+#define PWR_ST					BIT(6)
-+#define PWRBIT_OW_EN			BIT(7)
-+#define ACRC						BIT(8)
-+#define CFENDFORM				BIT(9)
-+#define ICV						BIT(10)
-+
-+
-+/* 2 RCR */
-+#define AAP						BIT(0)
-+#define APM						BIT(1)
-+#define AM						BIT(2)
-+#define AB						BIT(3)
-+#define ADD3						BIT(4)
-+#define APWRMGT				BIT(5)
-+#define CBSSID					BIT(6)
-+#define CBSSID_DATA				BIT(6)
-+#define CBSSID_BCN				BIT(7)
-+#define ACRC32					BIT(8)
-+#define AICV						BIT(9)
-+#define ADF						BIT(11)
-+#define ACF						BIT(12)
-+#define AMF						BIT(13)
-+#define HTC_LOC_CTRL			BIT(14)
-+#define UC_DATA_EN				BIT(16)
-+#define BM_DATA_EN				BIT(17)
-+#define MFBEN					BIT(22)
-+#define LSIGEN					BIT(23)
-+#define EnMBID					BIT(24)
-+#define FORCEACK				BIT(26)
-+#define APP_BASSN				BIT(27)
-+#define APP_PHYSTS				BIT(28)
-+#define APP_ICV					BIT(29)
-+#define APP_MIC					BIT(30)
-+#define APP_FCS					BIT(31)
-+
-+
-+/* 2 SECCFG */
-+#define SCR_TxUseDK				BIT(0)			/* Force Tx Use Default Key */
-+#define SCR_RxUseDK				BIT(1)			/* Force Rx Use Default Key */
-+#define SCR_TxEncEnable			BIT(2)			/* Enable Tx Encryption */
-+#define SCR_RxDecEnable			BIT(3)			/* Enable Rx Decryption */
-+#define SCR_SKByA2				BIT(4)			/* Search kEY BY A2 */
-+#define SCR_NoSKMC				BIT(5)			/* No Key Search Multicast */
-+#define SCR_TXBCUSEDK			BIT(6)			/* Force Tx Broadcast packets Use Default Key */
-+#define SCR_RXBCUSEDK			BIT(7)			/* Force Rx Broadcast packets Use Default Key */
-+#define SCR_CHK_KEYID			BIT(8)
-+#define SCR_CHK_BMC				BIT(9)			/* add option to support a2+keyid+bcm */
-+
-+/*REG_MBIDCAMCFG           (Offset 0x0628/0x62C)*/
-+#define BIT_MBIDCAM_POLL		BIT(31)
-+#define BIT_MBIDCAM_WT_EN		BIT(30)
-+
-+#define MBIDCAM_ADDR_MASK		0x1F
-+#define MBIDCAM_ADDR_SHIFT		24
-+
-+#define BIT_MBIDCAM_VALID		BIT(23)
-+#define BIT_LSIC_TXOP_EN		BIT(17)
-+#define BIT_CTS_EN				BIT(16)
-+
-+/*REG_RXFLTMAP1 (Offset 0x6A2)*/
-+#define BIT_CTRLFLT10EN	BIT(10) /*PS-POLL*/
-+
-+/*REG_WLAN_ACT_MASK_CTRL_1	(Offset 0x76C)*/
-+#define EN_PORT_0_FUNCTION		BIT(12)
-+#define EN_PORT_1_FUNCTION		BIT(13)
-+
-+/* -----------------------------------------------------
-+ *
-+ *	SDIO Bus Specification
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* I/O bus domain address mapping */
-+#define SDIO_LOCAL_BASE		0x10250000
-+#define WLAN_IOREG_BASE		0x10260000
-+#define FIRMWARE_FIFO_BASE	0x10270000
-+#define TX_HIQ_BASE				0x10310000
-+#define TX_MIQ_BASE				0x10320000
-+#define TX_LOQ_BASE				0x10330000
-+#define TX_EPQ_BASE				0x10350000
-+#define RX_RX0FF_BASE			0x10340000
-+
-+/* SDIO host local register space mapping. */
-+#define SDIO_LOCAL_MSK				0x0FFF
-+#define WLAN_IOREG_MSK		0x7FFF
-+#define WLAN_FIFO_MSK			      	0x1FFF	/* Aggregation Length[12:0] */
-+#define WLAN_RX0FF_MSK				0x0003
-+
-+#define SDIO_WITHOUT_REF_DEVICE_ID	0	/* Without reference to the SDIO Device ID */
-+#define SDIO_LOCAL_DEVICE_ID           		0	/* 0b[16], 000b[15:13] */
-+#define WLAN_TX_HIQ_DEVICE_ID			4	/* 0b[16], 100b[15:13] */
-+#define WLAN_TX_MIQ_DEVICE_ID 		5	/* 0b[16], 101b[15:13] */
-+#define WLAN_TX_LOQ_DEVICE_ID 		6	/* 0b[16], 110b[15:13] */
-+#define WLAN_TX_EXQ_DEVICE_ID		3	/* 0b[16], 011b[15:13] */
-+#define WLAN_RX0FF_DEVICE_ID 			7	/* 0b[16], 111b[15:13] */
-+#define WLAN_IOREG_DEVICE_ID 			8	/* 1b[16] */
-+
-+/* SDIO Tx Free Page Index */
-+#define HI_QUEUE_IDX			0
-+#define MID_QUEUE_IDX			1
-+#define LOW_QUEUE_IDX				2
-+#define PUBLIC_QUEUE_IDX			3
-+
-+#define SDIO_MAX_TX_QUEUE			3		/* HIQ, MIQ and LOQ */
-+#define SDIO_MAX_RX_QUEUE			1
-+
-+#define SDIO_REG_TX_CTRL			0x0000 /* SDIO Tx Control */
-+#define SDIO_REG_TIMEOUT			0x0002/*SDIO status timeout*/
-+#define SDIO_REG_HIMR				0x0014 /* SDIO Host Interrupt Mask */
-+#define SDIO_REG_HISR				0x0018 /* SDIO Host Interrupt Service Routine */
-+#define SDIO_REG_HCPWM			0x0019 /* HCI Current Power Mode */
-+#define SDIO_REG_RX0_REQ_LEN		0x001C /* RXDMA Request Length */
-+#define SDIO_REG_OQT_FREE_PG		0x001E /* OQT Free Page */
-+#define SDIO_REG_FREE_TXPG			0x0020 /* Free Tx Buffer Page */
-+#define SDIO_REG_HCPWM1			0x0024 /* HCI Current Power Mode 1 */
-+#define SDIO_REG_HCPWM2			0x0026 /* HCI Current Power Mode 2 */
-+#define SDIO_REG_FREE_TXPG_SEQ	0x0028 /* Free Tx Page Sequence */
-+#define SDIO_REG_HTSFR_INFO		0x0030 /* HTSF Informaion */
-+#define SDIO_REG_HRPWM1			0x0080 /* HCI Request Power Mode 1 */
-+#define SDIO_REG_HRPWM2			0x0082 /* HCI Request Power Mode 2 */
-+#define SDIO_REG_HPS_CLKR			0x0084 /* HCI Power Save Clock */
-+#define SDIO_REG_HSUS_CTRL			0x0086 /* SDIO HCI Suspend Control */
-+#define SDIO_REG_HIMR_ON			0x0090 /* SDIO Host Extension Interrupt Mask Always */
-+#define SDIO_REG_HISR_ON			0x0091 /* SDIO Host Extension Interrupt Status Always */
-+
-+#define SDIO_HIMR_DISABLED			0
-+
-+/* RTL8723/RTL8188E SDIO Host Interrupt Mask Register */
-+#define SDIO_HIMR_RX_REQUEST_MSK		BIT(0)
-+#define SDIO_HIMR_AVAL_MSK			BIT(1)
-+#define SDIO_HIMR_TXERR_MSK			BIT(2)
-+#define SDIO_HIMR_RXERR_MSK			BIT(3)
-+#define SDIO_HIMR_TXFOVW_MSK			BIT(4)
-+#define SDIO_HIMR_RXFOVW_MSK			BIT(5)
-+#define SDIO_HIMR_TXBCNOK_MSK			BIT(6)
-+#define SDIO_HIMR_TXBCNERR_MSK		BIT(7)
-+#define SDIO_HIMR_BCNERLY_INT_MSK		BIT(16)
-+#define SDIO_HIMR_C2HCMD_MSK			BIT(17)
-+#define SDIO_HIMR_CPWM1_MSK			BIT(18)
-+#define SDIO_HIMR_CPWM2_MSK			BIT(19)
-+#define SDIO_HIMR_HSISR_IND_MSK		BIT(20)
-+#define SDIO_HIMR_GTINT3_IND_MSK		BIT(21)
-+#define SDIO_HIMR_GTINT4_IND_MSK		BIT(22)
-+#define SDIO_HIMR_PSTIMEOUT_MSK		BIT(23)
-+#define SDIO_HIMR_OCPINT_MSK			BIT(24)
-+#define SDIO_HIMR_ATIMEND_MSK			BIT(25)
-+#define SDIO_HIMR_ATIMEND_E_MSK		BIT(26)
-+#define SDIO_HIMR_CTWEND_MSK			BIT(27)
-+
-+/* RTL8188E SDIO Specific */
-+#define SDIO_HIMR_MCU_ERR_MSK			BIT(28)
-+#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK		BIT(29)
-+
-+/* SDIO Host Interrupt Service Routine */
-+#define SDIO_HISR_RX_REQUEST			BIT(0)
-+#define SDIO_HISR_AVAL					BIT(1)
-+#define SDIO_HISR_TXERR					BIT(2)
-+#define SDIO_HISR_RXERR					BIT(3)
-+#define SDIO_HISR_TXFOVW				BIT(4)
-+#define SDIO_HISR_RXFOVW				BIT(5)
-+#define SDIO_HISR_TXBCNOK				BIT(6)
-+#define SDIO_HISR_TXBCNERR				BIT(7)
-+#define SDIO_HISR_BCNERLY_INT			BIT(16)
-+#define SDIO_HISR_C2HCMD				BIT(17)
-+#define SDIO_HISR_CPWM1				BIT(18)
-+#define SDIO_HISR_CPWM2				BIT(19)
-+#define SDIO_HISR_HSISR_IND			BIT(20)
-+#define SDIO_HISR_GTINT3_IND			BIT(21)
-+#define SDIO_HISR_GTINT4_IND			BIT(22)
-+#define SDIO_HISR_PSTIMEOUT			BIT(23)
-+#define SDIO_HISR_OCPINT				BIT(24)
-+#define SDIO_HISR_ATIMEND				BIT(25)
-+#define SDIO_HISR_ATIMEND_E			BIT(26)
-+#define SDIO_HISR_CTWEND				BIT(27)
-+
-+/* RTL8188E SDIO Specific */
-+#define SDIO_HISR_MCU_ERR				BIT(28)
-+#define SDIO_HISR_TSF_BIT32_TOGGLE	BIT(29)
-+
-+#define MASK_SDIO_HISR_CLEAR		(SDIO_HISR_TXERR |\
-+		SDIO_HISR_RXERR |\
-+		SDIO_HISR_TXFOVW |\
-+		SDIO_HISR_RXFOVW |\
-+		SDIO_HISR_TXBCNOK |\
-+		SDIO_HISR_TXBCNERR |\
-+		SDIO_HISR_C2HCMD |\
-+		SDIO_HISR_CPWM1 |\
-+		SDIO_HISR_CPWM2 |\
-+		SDIO_HISR_HSISR_IND |\
-+		SDIO_HISR_GTINT3_IND |\
-+		SDIO_HISR_GTINT4_IND |\
-+		SDIO_HISR_PSTIMEOUT |\
-+		SDIO_HISR_OCPINT)
-+
-+/* SDIO HCI Suspend Control Register */
-+#define HCI_RESUME_PWR_RDY			BIT(1)
-+#define HCI_SUS_CTRL					BIT(0)
-+
-+/* SDIO Tx FIFO related */
-+#define SDIO_TX_FREE_PG_QUEUE			4	/* The number of Tx FIFO free page */
-+#define SDIO_TX_FIFO_PAGE_SZ			128
-+
-+/* indirect access */
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+#define SDIO_REG_INDIRECT_REG_CFG		0x40
-+#define SDIO_REG_INDIRECT_REG_DATA	0x44
-+#define SET_INDIRECT_REG_ADDR(_cmd, _addr)	SET_BITS_TO_LE_2BYTE(((u8 *)(_cmd)) + 0, 0, 16, (_addr))
-+#define SET_INDIRECT_REG_SIZE_1BYTE(_cmd)		SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 0)
-+#define SET_INDIRECT_REG_SIZE_2BYTE(_cmd)		SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 1)
-+#define SET_INDIRECT_REG_SIZE_4BYTE(_cmd)		SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 2)
-+#define SET_INDIRECT_REG_WRITE(_cmd)			SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 2, 1, 1)
-+#define SET_INDIRECT_REG_READ(_cmd)			SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 3, 1, 1)
-+#define GET_INDIRECT_REG_RDY(_cmd)			LE_BITS_TO_1BYTE(((u8 *)(_cmd)) + 2, 4, 1)
-+#endif/*CONFIG_SDIO_INDIRECT_ACCESS*/
-+
-+#ifdef CONFIG_SDIO_HCI
-+	#define MAX_TX_AGG_PACKET_NUMBER	0x8
-+#else
-+	#define MAX_TX_AGG_PACKET_NUMBER	0xFF
-+	#define MAX_TX_AGG_PACKET_NUMBER_8812	64
-+#endif
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0xFE00h ~ 0xFE55h	USB Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* 2 USB Information (0xFE17) */
-+#define USB_IS_HIGH_SPEED			0
-+#define USB_IS_FULL_SPEED			1
-+#define USB_SPEED_MASK				BIT(5)
-+
-+#define USB_NORMAL_SIE_EP_MASK	0xF
-+#define USB_NORMAL_SIE_EP_SHIFT	4
-+
-+/* 2 Special Option */
-+#define USB_AGG_EN				BIT(3)
-+
-+/* 0; Use interrupt endpoint to upload interrupt pkt
-+ * 1; Use bulk endpoint to upload interrupt pkt, */
-+#define INT_BULK_SEL			BIT(4)
-+
-+/* 2REG_C2HEVT_CLEAR */
-+#define C2H_EVT_HOST_CLOSE		0x00	/* Set by driver and notify FW that the driver has read the C2H command message */
-+#define C2H_EVT_FW_CLOSE		0xFF	/* Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */
-+
-+
-+/* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */
-+#define WL_HWPDN_EN			BIT(0)	/* Enable GPIO[9] as WiFi HW PDn source */
-+#define WL_HWPDN_SL			BIT(1)	/* WiFi HW PDn polarity control */
-+#define WL_FUNC_EN				BIT(2)	/* WiFi function enable */
-+#define WL_HWROF_EN			BIT(3)	/* Enable GPIO[9] as WiFi RF HW PDn source */
-+#define BT_HWPDN_EN			BIT(16)	/* Enable GPIO[11] as BT HW PDn source */
-+#define BT_HWPDN_SL			BIT(17)	/* BT HW PDn polarity control */
-+#define BT_FUNC_EN				BIT(18)	/* BT function enable */
-+#define BT_HWROF_EN			BIT(19)	/* Enable GPIO[11] as BT/GPS RF HW PDn source */
-+#define GPS_HWPDN_EN			BIT(20)	/* Enable GPIO[10] as GPS HW PDn source */
-+#define GPS_HWPDN_SL			BIT(21)	/* GPS HW PDn polarity control */
-+#define GPS_FUNC_EN			BIT(22)	/* GPS function enable */
-+
-+/* 3 REG_LIFECTRL_CTRL */
-+#define HAL92C_EN_PKT_LIFE_TIME_BK		BIT(3)
-+#define HAL92C_EN_PKT_LIFE_TIME_BE		BIT(2)
-+#define HAL92C_EN_PKT_LIFE_TIME_VI		BIT(1)
-+#define HAL92C_EN_PKT_LIFE_TIME_VO		BIT(0)
-+
-+#define HAL92C_MSDU_LIFE_TIME_UNIT		128	/* in us, said by Tim. */
-+
-+/* 2 8192D PartNo. */
-+#define PARTNO_92D_NIC							(BIT7 | BIT6)
-+#define PARTNO_92D_NIC_REMARK				(BIT5 | BIT4)
-+#define PARTNO_SINGLE_BAND_VS				BIT(3)
-+#define PARTNO_SINGLE_BAND_VS_REMARK		BIT(1)
-+#define PARTNO_CONCURRENT_BAND_VC			(BIT3 | BIT2)
-+#define PARTNO_CONCURRENT_BAND_VC_REMARK	(BIT1 | BIT0)
-+
-+/* ********************************************************
-+ * General definitions
-+ * ******************************************************** */
-+
-+#ifdef CONFIG_USB_HCI
-+	#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter)	(175)
-+#else
-+	#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter)	(IS_VENDOR_8188E_I_CUT_SERIES(__Adapter) ? 255 : 175)
-+#endif
-+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8812			255
-+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B		255
-+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C		255
-+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8703B		255
-+#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC	127
-+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188F		255
-+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188GTV		255
-+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723D		255
-+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8710B		255
-+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192F		255
-+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723F		255
-+#define POLLING_LLT_THRESHOLD				20
-+#if defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI)
-+	#define POLLING_READY_TIMEOUT_COUNT		6000
-+#else
-+	#define POLLING_READY_TIMEOUT_COUNT		1000
-+#endif
-+
-+
-+/* GPIO BIT */
-+#define	HAL_8812A_HW_GPIO_WPS_BIT	BIT(2)
-+#define	HAL_8192C_HW_GPIO_WPS_BIT	BIT(2)
-+#define	HAL_8192EU_HW_GPIO_WPS_BIT	BIT(7)
-+#define	HAL_8188E_HW_GPIO_WPS_BIT	BIT(7)
-+
-+#endif /* __HAL_COMMON_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/hal_data.h b/drivers/staging/rtl8723cs/include/hal_data.h
-new file mode 100644
-index 000000000000..3262436bfdb5
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_data.h
-@@ -0,0 +1,881 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_DATA_H__
-+#define __HAL_DATA_H__
-+
-+#if 1/* def  CONFIG_SINGLE_IMG */
-+
-+#include "../hal/phydm/phydm_precomp.h"
-+#ifdef CONFIG_BT_COEXIST
-+	#include <hal_btcoex.h>
-+#endif
-+	#include <hal_btcoex_wifionly.h>
-+
-+#ifdef CONFIG_SDIO_HCI
-+	#include <hal_sdio.h>
-+#endif
-+#ifdef CONFIG_GSPI_HCI
-+	#include <hal_gspi.h>
-+#endif
-+
-+#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)
-+#include "../hal/hal_dm_acs.h"
-+#endif
-+
-+/*
-+ * <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
-+ *   */
-+typedef enum _RT_MULTI_FUNC {
-+	RT_MULTI_FUNC_NONE	= 0x00,
-+	RT_MULTI_FUNC_WIFI	= 0x01,
-+	RT_MULTI_FUNC_BT		= 0x02,
-+	RT_MULTI_FUNC_GPS	= 0x04,
-+} RT_MULTI_FUNC, *PRT_MULTI_FUNC;
-+/*
-+ * <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
-+ *   */
-+typedef enum _RT_POLARITY_CTL {
-+	RT_POLARITY_LOW_ACT	= 0,
-+	RT_POLARITY_HIGH_ACT	= 1,
-+} RT_POLARITY_CTL, *PRT_POLARITY_CTL;
-+
-+/* For RTL8723 regulator mode. by tynli. 2011.01.14. */
-+typedef enum _RT_REGULATOR_MODE {
-+	RT_SWITCHING_REGULATOR	= 0,
-+	RT_LDO_REGULATOR			= 1,
-+} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
-+
-+/*
-+ * Interface type.
-+ *   */
-+typedef	enum _INTERFACE_SELECT_PCIE {
-+	INTF_SEL0_SOLO_MINICARD			= 0,		/* WiFi solo-mCard */
-+	INTF_SEL1_BT_COMBO_MINICARD		= 1,		/* WiFi+BT combo-mCard */
-+	INTF_SEL2_PCIe						= 2,		/* PCIe Card */
-+} INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE;
-+
-+
-+typedef	enum _INTERFACE_SELECT_USB {
-+	INTF_SEL0_USB 				= 0,		/* USB */
-+	INTF_SEL1_USB_High_Power  	= 1,		/* USB with high power PA */
-+	INTF_SEL2_MINICARD		  	= 2,		/* Minicard */
-+	INTF_SEL3_USB_Solo 		= 3,		/* USB solo-Slim module */
-+	INTF_SEL4_USB_Combo		= 4,		/* USB Combo-Slim module */
-+	INTF_SEL5_USB_Combo_MF	= 5,		/* USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card */
-+} INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB;
-+
-+typedef enum _RT_AMPDU_BRUST_MODE {
-+	RT_AMPDU_BRUST_NONE		= 0,
-+	RT_AMPDU_BRUST_92D		= 1,
-+	RT_AMPDU_BRUST_88E		= 2,
-+	RT_AMPDU_BRUST_8812_4	= 3,
-+	RT_AMPDU_BRUST_8812_8	= 4,
-+	RT_AMPDU_BRUST_8812_12	= 5,
-+	RT_AMPDU_BRUST_8812_15	= 6,
-+	RT_AMPDU_BRUST_8723B		= 7,
-+} RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE;
-+
-+/* Tx Power Limit Table Size */
-+#define MAX_REGULATION_NUM						4
-+#define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE	4
-+#define MAX_2_4G_BANDWIDTH_NUM					2
-+#define MAX_RATE_SECTION_NUM						10
-+#define MAX_5G_BANDWIDTH_NUM						4
-+
-+#define NUM_OF_TARGET_TXPWR_2G	10 /* CCK:1, OFDM:1, HT:4, VHT:4 */
-+#define NUM_OF_TARGET_TXPWR_5G	9 /* OFDM:1, HT:4, VHT:4 */
-+
-+#ifdef RTW_RX_AGGREGATION
-+typedef enum _RX_AGG_MODE {
-+	RX_AGG_DISABLE,
-+	RX_AGG_DMA,
-+	RX_AGG_USB,
-+	RX_AGG_MIX
-+} RX_AGG_MODE;
-+
-+/* #define MAX_RX_DMA_BUFFER_SIZE	10240 */		/* 10K for 8192C RX DMA buffer */
-+
-+#endif /* RTW_RX_AGGREGATION */
-+
-+/* E-Fuse */
-+#ifdef CONFIG_RTL8188E
-+	#define EFUSE_MAP_SIZE	512
-+#endif
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
-+	#define EFUSE_MAP_SIZE	512
-+#endif
-+#ifdef CONFIG_RTL8192E
-+	#define EFUSE_MAP_SIZE	512
-+#endif
-+#ifdef CONFIG_RTL8723B
-+	#define EFUSE_MAP_SIZE	512
-+#endif
-+#ifdef CONFIG_RTL8814A
-+	#define EFUSE_MAP_SIZE	512
-+#endif
-+#ifdef CONFIG_RTL8703B
-+	#define EFUSE_MAP_SIZE	512
-+#endif
-+#ifdef CONFIG_RTL8723D
-+	#define EFUSE_MAP_SIZE	512
-+#endif
-+#ifdef CONFIG_RTL8188F
-+	#define EFUSE_MAP_SIZE	512
-+#endif
-+#ifdef CONFIG_RTL8188GTV
-+	#define EFUSE_MAP_SIZE	512
-+#endif
-+#ifdef CONFIG_RTL8710B
-+	#define EFUSE_MAP_SIZE	512
-+#endif
-+#ifdef CONFIG_RTL8192F
-+	#define EFUSE_MAP_SIZE	512
-+#endif
-+
-+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814B)
-+	#define EFUSE_MAX_SIZE	1024
-+#elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8710B)
-+	#define EFUSE_MAX_SIZE	256
-+#else
-+	#define EFUSE_MAX_SIZE	512
-+#endif
-+/* end of E-Fuse */
-+
-+#define Mac_OFDM_OK			0x00000000
-+#define Mac_OFDM_Fail		0x10000000
-+#define Mac_OFDM_FasleAlarm	0x20000000
-+#define Mac_CCK_OK			0x30000000
-+#define Mac_CCK_Fail		0x40000000
-+#define Mac_CCK_FasleAlarm	0x50000000
-+#define Mac_HT_OK			0x60000000
-+#define Mac_HT_Fail			0x70000000
-+#define Mac_HT_FasleAlarm	0x90000000
-+#define Mac_DropPacket		0xA0000000
-+
-+#ifdef CONFIG_RF_POWER_TRIM
-+#if defined(CONFIG_RTL8723B)
-+	#define REG_RF_BB_GAIN_OFFSET	0x7f
-+	#define RF_GAIN_OFFSET_MASK		0xfffff
-+#elif defined(CONFIG_RTL8188E)
-+	#define REG_RF_BB_GAIN_OFFSET	0x55
-+	#define RF_GAIN_OFFSET_MASK		0xfffff
-+#else
-+	#define REG_RF_BB_GAIN_OFFSET	0x55
-+	#define RF_GAIN_OFFSET_MASK		0xfffff
-+#endif /* CONFIG_RTL8723B */
-+#endif /*CONFIG_RF_POWER_TRIM*/
-+
-+/* For store initial value of BB register */
-+typedef struct _BB_INIT_REGISTER {
-+	u16	offset;
-+	u32	value;
-+
-+} BB_INIT_REGISTER, *PBB_INIT_REGISTER;
-+
-+#define PAGE_SIZE_128	128
-+#define PAGE_SIZE_256	256
-+#define PAGE_SIZE_512	512
-+
-+#define HCI_SUS_ENTER		0
-+#define HCI_SUS_LEAVING		1
-+#define HCI_SUS_LEAVE		2
-+#define HCI_SUS_ENTERING	3
-+#define HCI_SUS_ERR			4
-+
-+#define EFUSE_FILE_UNUSED 0
-+#define EFUSE_FILE_FAILED 1
-+#define EFUSE_FILE_LOADED 2
-+
-+#define MACADDR_FILE_UNUSED 0
-+#define MACADDR_FILE_FAILED 1
-+#define MACADDR_FILE_LOADED 2
-+
-+#define MAX_IQK_INFO_BACKUP_CHNL_NUM	5
-+#define MAX_IQK_INFO_BACKUP_REG_NUM		10
-+
-+struct kfree_data_t {
-+	u8 flag;
-+	s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX];
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	s8 pa_bias_5g[RF_PATH_MAX];
-+	s8 pad_bias_5g[RF_PATH_MAX];
-+#endif
-+	s8 thermal;
-+};
-+
-+bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data);
-+
-+struct hal_spec_t {
-+	char *ic_name;
-+	u8 macid_num;
-+
-+	u8 sec_cam_ent_num;
-+	u8 sec_cap;
-+	u8 wow_cap;
-+	u8 macid_cap;
-+	u16 macid_txrpt;
-+	u8 macid_txrpt_pgsz;
-+
-+	u8 rfpath_num_2g:4;	/* used for tx power index path */
-+	u8 rfpath_num_5g:4;	/* used for tx power index path */
-+	u8 rf_reg_path_num;
-+	u8 rf_reg_path_avail_num;
-+	u8 rf_reg_trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp */
-+	u8 max_tx_cnt;
-+
-+	u8 tx_nss_num:4;
-+	u8 rx_nss_num:4;
-+
-+	u8 band_cap;	/* value of BAND_CAP_XXX */
-+	u8 bw_cap;		/* value of BW_CAP_XXX */
-+	u8 port_num;
-+	u8 proto_cap;	/* value of PROTO_CAP_XXX */
-+
-+	u8 txgi_max; /* maximum tx power gain index */
-+	u8 txgi_pdbm; /* tx power gain index per dBm */
-+
-+	u8 wl_func;		/* value of WL_FUNC_XXX */
-+
-+	u8 tx_aclt_unit_factor; /* how many 32us */
-+
-+	u8 rx_tsf_filter:1;
-+
-+	u8 pg_txpwr_saddr; /* starting address of PG tx power info */
-+	u8 pg_txgi_diff_factor; /* PG tx power gain index diff to tx power gain index */
-+
-+	u8 hci_type;	/* value of HCI Type */
-+};
-+
-+#define HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) ((_spec)->rfpath_num_2g > (_path))
-+#define HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) ((_spec)->rfpath_num_5g > (_path))
-+#define HAL_SPEC_CHK_RF_PATH(_spec, _band, _path) ( \
-+	_band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \
-+	_band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0)
-+
-+#ifdef CONFIG_PHY_CAPABILITY_QUERY
-+struct phy_spec_t {
-+	u32 trx_cap;
-+	u32 stbc_cap;
-+	u32 ldpc_cap;
-+	u32 txbf_param;
-+	u32 txbf_cap;
-+};
-+#endif
-+struct hal_iqk_reg_backup {
-+	u8 central_chnl;
-+	u8 bw_mode;
-+	u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM];
-+};
-+
-+
-+typedef struct hal_p2p_ps_para {
-+	/*DW0*/
-+	u8  offload_en:1;
-+	u8  role:1;
-+	u8  ctwindow_en:1;
-+	u8  noa_en:1;
-+	u8  noa_sel:1;
-+	u8  all_sta_sleep:1;
-+	u8  discovery:1;
-+	u8  disable_close_rf:1;
-+	u8  p2p_port_id;
-+	u8  p2p_group;
-+	u8  p2p_macid;
-+
-+	/*DW1*/
-+	u8 ctwindow_length;
-+	u8 rsvd3;
-+	u8 rsvd4;
-+	u8 rsvd5;
-+
-+	/*DW2*/
-+	u32 noa_duration_para;
-+
-+	/*DW3*/
-+	u32 noa_interval_para;
-+
-+	/*DW4*/
-+	u32 noa_start_time_para;
-+
-+	/*DW5*/
-+	u32 noa_count_para;
-+} HAL_P2P_PS_PARA, *PHAL_P2P_PS_PARA;
-+
-+#define TXPWR_LMT_RS_CCK	0
-+#define TXPWR_LMT_RS_OFDM	1
-+#define TXPWR_LMT_RS_HT		2
-+#define TXPWR_LMT_RS_VHT	3
-+#define TXPWR_LMT_RS_NUM	4
-+
-+#define TXPWR_LMT_RS_NUM_2G	4 /* CCK, OFDM, HT, VHT */
-+#define TXPWR_LMT_RS_NUM_5G	3 /* OFDM, HT, VHT */
-+
-+#if CONFIG_TXPWR_LIMIT
-+extern const char *const _txpwr_lmt_rs_str[];
-+#define txpwr_lmt_rs_str(rs) (((rs) >= TXPWR_LMT_RS_NUM) ? _txpwr_lmt_rs_str[TXPWR_LMT_RS_NUM] : _txpwr_lmt_rs_str[(rs)])
-+
-+struct txpwr_lmt_ent {
-+	_list list;
-+
-+	s8 lmt_2g[MAX_2_4G_BANDWIDTH_NUM]
-+		[TXPWR_LMT_RS_NUM_2G]
-+		[CENTER_CH_2G_NUM]
-+		[MAX_TX_COUNT];
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	s8 lmt_5g[MAX_5G_BANDWIDTH_NUM]
-+		[TXPWR_LMT_RS_NUM_5G]
-+		[CENTER_CH_5G_ALL_NUM]
-+		[MAX_TX_COUNT];
-+#endif
-+
-+	char regd_name[0];
-+};
-+#endif /* CONFIG_TXPWR_LIMIT */
-+
-+typedef struct hal_com_data {
-+	HAL_VERSION			version_id;
-+	RT_MULTI_FUNC		MultiFunc; /* For multi-function consideration. */
-+	RT_POLARITY_CTL		PolarityCtl; /* For Wifi PDn Polarity control. */
-+	RT_REGULATOR_MODE	RegulatorMode; /* switching regulator or LDO */
-+	u8	hw_init_completed;
-+	/****** FW related ******/
-+	u32 firmware_size;
-+	u16 firmware_version;
-+	u16	FirmwareVersionRev;
-+	u16 firmware_sub_version;
-+	u16	FirmwareSignature;
-+	u8	RegFWOffload;
-+	u8	bFWReady;
-+	u8	bBTFWReady;
-+	u8	fw_ractrl;
-+	u8	LastHMEBoxNum;	/* H2C - for host message to fw */
-+#ifdef CONFIG_LPS_1T1R
-+	u8 lps_1t1r;
-+#endif
-+
-+	/****** current WIFI_PHY values ******/
-+	WIRELESS_MODE	CurrentWirelessMode;
-+	enum channel_width current_channel_bw;
-+	BAND_TYPE		current_band_type;	/* 0:2.4G, 1:5G */
-+	u8				current_channel;
-+	u8				cch_20;
-+	u8				cch_40;
-+	u8				cch_80;
-+	u8				CurrentCenterFrequencyIndex1;
-+	u8				nCur40MhzPrimeSC;	/* Control channel sub-carrier */
-+	u8				nCur80MhzPrimeSC;   /* used for primary 40MHz of 80MHz mode */
-+	BOOLEAN		bSwChnlAndSetBWInProgress;
-+	u8				bDisableSWChannelPlan; /* flag of disable software change channel plan	 */
-+	u16				BasicRateSet;
-+	u32				ReceiveConfig;
-+#ifdef CONFIG_WIFI_MONITOR
-+	struct mon_reg_backup		mon_backup; /* used for switching back from monitor mode */
-+#endif /* CONFIG_WIFI_MONITOR */
-+	u8				rx_tsf_addr_filter_config; /* for 8822B/8821C USE */
-+	BOOLEAN			bSwChnl;
-+	BOOLEAN			bSetChnlBW;
-+	BOOLEAN			bSWToBW40M;
-+	BOOLEAN			bSWToBW80M;
-+	BOOLEAN			bChnlBWInitialized;
-+
-+#ifdef CONFIG_RTW_ACS
-+	struct auto_chan_sel acs;
-+#endif
-+#ifdef CONFIG_BCN_RECOVERY
-+	u8 issue_bcn_fail;
-+#endif /*CONFIG_BCN_RECOVERY*/
-+
-+	/****** rf_ctrl *****/
-+	u8	rf_chip;
-+
-+	u8 trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp */
-+	u8	rf_type;	/*enum rf_type , is RF_PATH - GET_HAL_RFPATH*/
-+	u8	NumTotalRFPath; /*GET_HAL_RFPATH_NUM*/
-+	u8 max_tx_cnt;
-+	u8	tx_nss; /*tx Spatial Streams - GET_HAL_TX_NSS*/
-+	u8	rx_nss; /*rx Spatial Streams - GET_HAL_RX_NSS*/
-+	u8 txpath_cap_num_nss[4]; /* capable path num for NSS TX, [0] for 1SS, [3] for 4SS */
-+
-+	u8	PackageType;
-+	u8	antenna_test;
-+
-+	/* runtime TRX path setting */
-+	enum bb_path txpath; /* TX path bmp */
-+	enum bb_path rxpath; /* RX path bmp */
-+	enum bb_path txpath_nss[4]; /* path bmp for NSS TX, [0] for 1SS, [3] for 4SS */
-+	u8 txpath_num_nss[4]; /* path num for NSS TX, [0] for 1SS, [3] for 4SS */
-+
-+	/****** Debug ******/
-+	u16	ForcedDataRate;	/* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */
-+	u8	bDumpRxPkt;
-+	u8	bDumpTxPkt;
-+	u8	dis_turboedca; /* 1: disable turboedca, 
-+						  2: disable turboedca and setting EDCA parameter based on the input parameter*/
-+	u32 edca_param_mode;
-+
-+	/****** EEPROM setting.******/
-+	u8	bautoload_fail_flag;
-+	u8	efuse_file_status;
-+	u8	macaddr_file_status;
-+	u8	EepromOrEfuse;
-+	u8	efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/
-+	u8	InterfaceSel; /* board type kept in eFuse */
-+	u16	CustomerID;
-+
-+	u16	EEPROMVID;
-+	u16	EEPROMSVID;
-+#ifdef CONFIG_USB_HCI
-+	u8	EEPROMUsbSwitch;
-+	u16	EEPROMPID;
-+	u16	EEPROMSDID;
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+	u16	EEPROMDID;
-+	u16	EEPROMSMID;
-+#endif
-+
-+	u8	EEPROMCustomerID;
-+	u8	EEPROMSubCustomerID;
-+	u8	EEPROMVersion;
-+	u8	EEPROMRegulatory;
-+	u8	eeprom_thermal_meter;
-+	u8	EEPROMBluetoothCoexist;
-+	u8	EEPROMBluetoothType;
-+	u8	EEPROMBluetoothAntNum;
-+	u8	EEPROMBluetoothAntIsolation;
-+	u8	EEPROMBluetoothRadioShared;
-+	u8	EEPROMMACAddr[ETH_ALEN];
-+
-+	u8 eeprom_trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp. 0x00:not specified */
-+	u8 eeprom_max_tx_cnt; /* 0: not specified */
-+
-+	u8	tx_bbswing_24G;
-+	u8	tx_bbswing_5G;
-+	u8	efuse0x3d7;	/* efuse[0x3D7] */
-+	u8	efuse0x3d8;	/* efuse[0x3D8] */
-+
-+#ifdef CONFIG_RF_POWER_TRIM
-+	u8	EEPROMRFGainOffset;
-+	u8	EEPROMRFGainVal;
-+	struct kfree_data_t kfree_data;
-+#endif /*CONFIG_RF_POWER_TRIM*/
-+
-+#ifdef CONFIG_RTL8814A
-+	u32	BackUp_BB_REG_4_2nd_CCA[3];
-+#endif
-+#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \
-+	defined(CONFIG_RTL8723D) || \
-+	defined(CONFIG_RTL8192F)
-+
-+	u8	adjuseVoltageVal;
-+	u8	need_restore;
-+#endif
-+	u8	EfuseUsedPercentage;
-+	u16	EfuseUsedBytes;
-+	/*u8		EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/
-+	EFUSE_HAL	EfuseHal;
-+
-+	u8 txpwr_pg_mode; /* enum txpwr_pg_mode */
-+
-+	/*---------------------------------------------------------------------------------*/
-+#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	/* 2.4G TX power info for target TX power*/
-+	u8	Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
-+	u8	Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
-+	s8	CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+	s8	OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+	s8	BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+	s8	BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+
-+	/* 5G TX power info for target TX power*/
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	u8	Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM];
-+	u8	Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM];
-+	s8	OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+	s8	BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+	s8	BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+	s8	BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
-+#endif
-+#endif /* CONFIG_TXPWR_PG_WITH_PWR_IDX */
-+
-+	u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND]
-+		[TX_PWR_BY_RATE_NUM_RF];
-+
-+	s8	TxPwrByRate[TX_PWR_BY_RATE_NUM_BAND]
-+		[TX_PWR_BY_RATE_NUM_RF]
-+		[TX_PWR_BY_RATE_NUM_RATE];
-+
-+	/* Store the target power for each rate section and rf path */
-+	u8	target_txpwr_2g[TX_PWR_BY_RATE_NUM_RF]
-+		[NUM_OF_TARGET_TXPWR_2G];
-+	u8	target_txpwr_5g[TX_PWR_BY_RATE_NUM_RF]
-+		[NUM_OF_TARGET_TXPWR_5G];
-+
-+	bool set_entire_txpwr;
-+
-+#if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) \
-+    || defined(CONFIG_RTL8723F)
-+	u32 txagc_set_buf;
-+#endif
-+
-+#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
-+	u8 txpwr_idx_offload_buf[3]; /* for CCK, OFDM, HT1SS */
-+	struct submit_ctx txpwr_idx_offload_sctx;
-+#endif
-+
-+	u8	txpwr_by_rate_loaded:1;
-+	u8	txpwr_by_rate_from_file:1;
-+	u8	txpwr_limit_loaded:1;
-+	u8	txpwr_limit_from_file:1;
-+
-+	/* Read/write are allow for following hardware information variables	 */
-+	u8	crystal_cap;
-+
-+	u8	PAType_2G;
-+	u8	PAType_5G;
-+	u8	LNAType_2G;
-+	u8	LNAType_5G;
-+	u8	ExternalPA_2G;
-+	u8	ExternalLNA_2G;
-+	u8	external_pa_5g;
-+	u8	external_lna_5g;
-+	u16	TypeGLNA;
-+	u16	TypeGPA;
-+	u16	TypeALNA;
-+	u16	TypeAPA;
-+	u16	rfe_type;
-+
-+	u8	bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
-+	u32	ac_param_be; /* Original parameter for BE, use for EDCA turbo.	*/
-+	u8	is_turbo_edca;
-+	u8	prv_traffic_idx;
-+	BB_REGISTER_DEFINITION_T	PHYRegDef[MAX_RF_PATH];	/* Radio A/B/C/D */
-+
-+	u32	RfRegChnlVal[MAX_RF_PATH];
-+
-+	/* RDG enable */
-+	BOOLEAN	 bRDGEnable;
-+
-+	#if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+	u32 RegRRSR;
-+	#endif
-+
-+	/****** antenna diversity ******/
-+	u8	AntDivCfg;
-+	u8	with_extenal_ant_switch;
-+	u8	b_fix_tx_ant;
-+	u8	AntDetection;
-+	u8	TRxAntDivType;
-+	u8	ant_path; /* for 8723B s0/s1 selection	 */
-+	u32	antenna_tx_path;					/* Antenna path Tx */
-+	u32	AntennaRxPath;					/* Antenna path Rx */
-+	u8 sw_antdiv_bl_state;
-+
-+	/******** PHY DM & DM Section **********/
-+	_lock		IQKSpinLock;
-+	u8			INIDATA_RATE[MACID_NUM_SW_LIMIT];
-+
-+	struct dm_struct	 odmpriv;
-+	u64			bk_rf_ability;
-+	u8			bIQKInitialized;
-+	u8			bNeedIQK;
-+	u8			neediqk_24g;
-+	u8			IQK_MP_Switch;
-+	u8			bScanInProcess;
-+	u8			phydm_init_result; /*BB and RF para match or not*/
-+	/******** PHY DM & DM Section **********/
-+
-+
-+
-+	/* 2010/08/09 MH Add CU power down mode. */
-+	BOOLEAN		pwrdown;
-+
-+#ifdef CONFIG_P2P
-+#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
-+	u16 p2p_ps_offload;
-+#else
-+	u8	p2p_ps_offload;
-+#endif
-+#endif
-+	/* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
-+	u8	bMacPwrCtrlOn;
-+	u8 hci_sus_state;
-+
-+	u8	RegIQKFWOffload;
-+	struct submit_ctx	iqk_sctx;
-+	u8 ch_switch_offload;
-+	struct submit_ctx chsw_sctx;
-+
-+	RT_AMPDU_BRUST		AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */
-+
-+	u8	OutEpQueueSel;
-+	u8	OutEpNumber;
-+
-+#ifdef RTW_RX_AGGREGATION
-+	RX_AGG_MODE rxagg_mode;
-+
-+	/* For RX Aggregation DMA Mode */
-+	u8 rxagg_dma_size;
-+	u8 rxagg_dma_timeout;
-+#endif /* RTW_RX_AGGREGATION */
-+
-+	bool intf_start;
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	/*  */
-+	/* For SDIO Interface HAL related */
-+	/*  */
-+
-+	/*  */
-+	/* SDIO ISR Related */
-+	/*
-+	*	u32			IntrMask[1];
-+	*	u32			IntrMaskToSet[1];
-+	*	LOG_INTERRUPT		InterruptLog; */
-+	u32			sdio_himr;
-+	u32			sdio_hisr;
-+#ifndef RTW_HALMAC
-+	/*  */
-+	/* SDIO Tx FIFO related. */
-+	/*  */
-+	/* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */
-+#ifdef CONFIG_RTL8192F
-+	u16			SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
-+#else
-+	u8			SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
-+#endif/*CONFIG_RTL8192F*/
-+#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+	u8			sdio_avail_int_en_q;
-+#endif
-+	_lock		SdioTxFIFOFreePageLock;
-+	u8			SdioTxOQTMaxFreeSpace;
-+	u8			SdioTxOQTFreeSpace;
-+#else /* RTW_HALMAC */
-+	u16			SdioTxOQTFreeSpace;
-+#endif /* RTW_HALMAC */
-+
-+	/*  */
-+	/* SDIO Rx FIFO related. */
-+	/*  */
-+	u8			SdioRxFIFOCnt;
-+#if defined (CONFIG_RTL8822C) || defined (CONFIG_RTL8192F)
-+	u32			SdioRxFIFOSize;
-+#else
-+	u16			SdioRxFIFOSize;
-+#endif
-+
-+#ifndef RTW_HALMAC
-+	u32			sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */
-+#else
-+#ifdef CONFIG_RTL8821C
-+	u16			tx_high_page;
-+	u16			tx_low_page;
-+	u16			tx_normal_page;
-+	u16			tx_extra_page;
-+	u16			tx_pub_page;
-+	u8			max_oqt_size;
-+	#ifdef XMIT_BUF_SIZE
-+	u32			max_xmit_size_vovi;
-+	u32			max_xmit_size_bebk;
-+	#endif /*XMIT_BUF_SIZE*/
-+	u16			max_xmit_page;
-+	u16			max_xmit_page_vo;
-+	u16			max_xmit_page_vi;
-+	u16			max_xmit_page_be;
-+	u16			max_xmit_page_bk;
-+
-+#endif /*#ifdef CONFIG_RTL8821C*/
-+#endif /* !RTW_HALMAC */
-+#endif /* CONFIG_SDIO_HCI */
-+
-+#ifdef CONFIG_USB_HCI
-+
-+	/* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */
-+	BOOLEAN		UsbRxHighSpeedMode;
-+	BOOLEAN		UsbTxVeryHighSpeedMode;
-+	u32			UsbBulkOutSize;
-+	BOOLEAN		bSupportUSB3;
-+	u8			usb_intf_start;
-+
-+	/* Interrupt relatd register information. */
-+	u32			IntArray[3];/* HISR0,HISR1,HSISR */
-+	u32			IntrMask[3];
-+#ifdef CONFIG_USB_TX_AGGREGATION
-+	u8			UsbTxAggMode;
-+	u8			UsbTxAggDescNum;
-+#endif /* CONFIG_USB_TX_AGGREGATION */
-+
-+#ifdef CONFIG_USB_RX_AGGREGATION
-+	u16			HwRxPageSize;				/* Hardware setting */
-+
-+	/* For RX Aggregation USB Mode */
-+	u8			rxagg_usb_size;
-+	u8			rxagg_usb_timeout;
-+#endif/* CONFIG_USB_RX_AGGREGATION */
-+#endif /* CONFIG_USB_HCI */
-+
-+
-+#ifdef CONFIG_PCI_HCI
-+	/*  */
-+	/* EEPROM setting. */
-+	/*  */
-+	u32			TransmitConfig;
-+	u32			IntrMaskToSet[2];
-+	u32			IntArray[4];
-+	u32			IntrMask[4];
-+	u32			SysIntArray[1];
-+	u32			SysIntrMask[1];
-+	u32			IntrMaskReg[2];
-+	u32			IntrMaskDefault[4];
-+
-+	u32			pci_backdoor_ctrl;
-+
-+	u8			bDefaultAntenna;
-+
-+	u8			bInterruptMigration;
-+	u8			bDisableTxInt;
-+
-+	u16			RxTag;
-+#endif /* CONFIG_PCI_HCI */
-+
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	struct sreset_priv srestpriv;
-+#endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
-+
-+#ifdef CONFIG_BT_COEXIST
-+	/* For bluetooth co-existance */
-+	BT_COEXIST		bt_coexist;
-+#endif /* CONFIG_BT_COEXIST */
-+
-+#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \
-+	|| defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D)|| defined(CONFIG_RTL8192F)
-+#ifndef CONFIG_PCI_HCI	/* mutual exclusive with PCI -- so they're SDIO and GSPI */
-+	/* Interrupt relatd register information. */
-+	u32			SysIntrStatus;
-+	u32			SysIntrMask;
-+#endif
-+#endif /*endif CONFIG_RTL8723B	*/
-+
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+	char	para_file_buf[MAX_PARA_FILE_BUF_LEN];
-+	char *mac_reg;
-+	u32	mac_reg_len;
-+	char *bb_phy_reg;
-+	u32	bb_phy_reg_len;
-+	char *bb_agc_tab;
-+	u32	bb_agc_tab_len;
-+	char *bb_phy_reg_pg;
-+	u32	bb_phy_reg_pg_len;
-+	char *bb_phy_reg_mp;
-+	u32	bb_phy_reg_mp_len;
-+	char *rf_radio_a;
-+	u32	rf_radio_a_len;
-+	char *rf_radio_b;
-+	u32	rf_radio_b_len;
-+	char *rf_tx_pwr_track;
-+	u32	rf_tx_pwr_track_len;
-+	char *rf_tx_pwr_lmt;
-+	u32	rf_tx_pwr_lmt_len;
-+#endif
-+
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+	struct noise_monitor nm;
-+#endif
-+
-+	struct hal_spec_t hal_spec;
-+#ifdef CONFIG_PHY_CAPABILITY_QUERY
-+	struct phy_spec_t phy_spec;
-+#endif
-+	u8	RfKFreeEnable;
-+	u8	RfKFree_ch_group;
-+	BOOLEAN				bCCKinCH14;
-+	BB_INIT_REGISTER	RegForRecover[5];
-+
-+#if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN)
-+	BOOLEAN bCorrectBCN;
-+#endif
-+#ifdef CONFIG_RTL8814A
-+	u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/
-+	u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/
-+#endif
-+	struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM];
-+
-+#ifdef RTW_HALMAC
-+	u16 drv_rsvd_page_number;
-+#endif
-+
-+#ifdef CONFIG_BEAMFORMING
-+	u8 backup_snd_ptcl_ctrl;
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+	struct beamforming_info beamforming_info;
-+#endif /* RTW_BEAMFORMING_VERSION_2 */
-+#endif /* CONFIG_BEAMFORMING */
-+
-+	u8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/
-+	u8 phydm_op_mode;
-+
-+	u8 in_cta_test;
-+
-+#ifdef CONFIG_RTW_LED
-+	struct led_priv led;
-+#endif
-+	/* for multi channel case (ex: MCC/TDLS) */
-+	u8 multi_ch_switch_mode;
-+	
-+#ifdef CONFIG_RTL8814B
-+	u8 dma_ch_map[32];	/* TXDESC qsel maximum size */
-+#endif
-+
-+} HAL_DATA_COMMON, *PHAL_DATA_COMMON;
-+
-+typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;
-+#define GET_HAL_DATA(__pAdapter)		((HAL_DATA_TYPE *)(((struct _ADAPTER*)__pAdapter)->HalData))
-+#define GET_HAL_SPEC(__pAdapter)			(&(GET_HAL_DATA((__pAdapter))->hal_spec))
-+#define adapter_to_led(adapter) (&(GET_HAL_DATA(adapter)->led))
-+
-+#define RT_GetInterfaceSelection(_Adapter)		(GET_HAL_DATA(_Adapter)->InterfaceSel)
-+
-+#define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data))
-+
-+#define	SUPPORT_HW_RADIO_DETECT(Adapter)	(RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \
-+		RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo || \
-+		RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo)
-+
-+#define get_hal_mac_addr(adapter)				(GET_HAL_DATA(adapter)->EEPROMMACAddr)
-+#define is_boot_from_eeprom(adapter)			(GET_HAL_DATA(adapter)->EepromOrEfuse)
-+#define rtw_get_hw_init_completed(adapter)		(GET_HAL_DATA(adapter)->hw_init_completed)
-+#define rtw_set_hw_init_completed(adapter, cmp)	(GET_HAL_DATA(adapter)->hw_init_completed = cmp)
-+#define rtw_is_hw_init_completed(adapter)		(GET_HAL_DATA(adapter)->hw_init_completed == _TRUE)
-+
-+/* refer to (hal_data->version_id.RFType / registrypriv->rf_path / 8814a from efuse or registrypriv)*/
-+#define GET_HAL_RFPATH(adapter)			(GET_HAL_DATA(adapter)->rf_type)
-+#define GET_HAL_RFPATH_NUM(adapter)		(GET_HAL_DATA(adapter)->NumTotalRFPath)
-+#define GET_HAL_TX_PATH_BMP(adapter)	((GET_HAL_DATA(adapter)->trx_path_bmp & 0xF0) >> 4)
-+#define GET_HAL_RX_PATH_BMP(adapter)	(GET_HAL_DATA(adapter)->trx_path_bmp & 0x0F)
-+
-+/* refer to (registrypriv-> tx_nss,rx_nss / hal_spec->tx_nss_num,rx_nss_num)*/
-+#define GET_HAL_TX_NSS(adapter)			(GET_HAL_DATA(adapter)->tx_nss)
-+#define GET_HAL_RX_NSS(adapter)			(GET_HAL_DATA(adapter)->rx_nss)
-+
-+#endif
-+
-+#ifdef RTW_HALMAC
-+int rtw_halmac_deinit_adapter(struct dvobj_priv *);
-+#endif /* RTW_HALMAC */
-+
-+#endif /* __HAL_DATA_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/hal_gspi.h b/drivers/staging/rtl8723cs/include/hal_gspi.h
-new file mode 100644
-index 000000000000..51d491cdb505
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_gspi.h
-@@ -0,0 +1,26 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_GSPI_H_
-+#define __HAL_GSPI_H_
-+
-+#define ffaddr2deviceId(pdvobj, addr)	(pdvobj->Queue2Pipe[addr])
-+
-+u8 rtw_hal_gspi_max_txoqt_free_space(_adapter *padapter);
-+u8 rtw_hal_gspi_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
-+void rtw_hal_gspi_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
-+void rtw_hal_set_gspi_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ);
-+u32 rtw_hal_get_gspi_tx_max_length(PADAPTER padapter, u8 queue_idx);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/hal_ic_cfg.h b/drivers/staging/rtl8723cs/include/hal_ic_cfg.h
-new file mode 100644
-index 000000000000..02779bd8c94a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_ic_cfg.h
-@@ -0,0 +1,710 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_IC_CFG_H__
-+#define __HAL_IC_CFG_H__
-+
-+#define RTL8188E_SUPPORT				0
-+#define RTL8812A_SUPPORT				0
-+#define RTL8821A_SUPPORT				0
-+#define RTL8723B_SUPPORT				0
-+#define RTL8723D_SUPPORT				0
-+#define RTL8723F_SUPPORT				0
-+#define RTL8192E_SUPPORT				0
-+#define RTL8192F_SUPPORT				0
-+#define RTL8814A_SUPPORT				0
-+#define RTL8195A_SUPPORT				0
-+#define RTL8197F_SUPPORT				0
-+#define RTL8703B_SUPPORT				0
-+#define RTL8188F_SUPPORT				0
-+#define RTL8822B_SUPPORT				0
-+#define RTL8821B_SUPPORT				0
-+#define RTL8821C_SUPPORT				0
-+#define RTL8710B_SUPPORT				0
-+#define RTL8814B_SUPPORT				0
-+#define RTL8824B_SUPPORT				0
-+#define RTL8198F_SUPPORT				0
-+#define RTL8195B_SUPPORT				0
-+#define RTL8822C_SUPPORT				0
-+#define RTL8721D_SUPPORT				0
-+#define RTL8812F_SUPPORT				0
-+#define RTL8197G_SUPPORT				0
-+#define RTL8710C_SUPPORT				0
-+
-+
-+/*#if (RTL8188E_SUPPORT==1)*/
-+#define RATE_ADAPTIVE_SUPPORT			0
-+#define POWER_TRAINING_ACTIVE			0
-+
-+#ifdef CONFIG_MULTIDRV
-+#endif
-+
-+#ifdef CONFIG_RTL8188E
-+	#undef RTL8188E_SUPPORT
-+	#undef RATE_ADAPTIVE_SUPPORT
-+	#undef POWER_TRAINING_ACTIVE
-+
-+	#define RTL8188E_SUPPORT				1
-+	#define RATE_ADAPTIVE_SUPPORT			1
-+	#define POWER_TRAINING_ACTIVE			1
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	#undef RTL8812A_SUPPORT
-+	#define RTL8812A_SUPPORT				1
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif
-+	#ifdef CONFIG_BEAMFORMING
-+		#define CONFIG_BEAMFORMER_FW_NDPA
-+		#define BEAMFORMING_SUPPORT		1	/*for phydm beamforming*/
-+		#define SUPPORT_MU_BF				0
-+	#endif /*CONFIG_BEAMFORMING*/
-+	#define CONFIG_RTS_FULL_BW
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8821A
-+	#undef RTL8821A_SUPPORT
-+	#define RTL8821A_SUPPORT				1
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif
-+	#ifdef CONFIG_BEAMFORMING
-+		#define CONFIG_BEAMFORMER_FW_NDPA
-+		#define BEAMFORMING_SUPPORT		1	/*for phydm beamforming*/
-+		#define SUPPORT_MU_BF				0
-+	#endif
-+	#define CONFIG_RTS_FULL_BW
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	#undef RTL8192E_SUPPORT
-+	#define RTL8192E_SUPPORT				1
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif
-+	#define CONFIG_RTS_FULL_BW
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8192F
-+	#undef RTL8192F_SUPPORT
-+	#define RTL8192F_SUPPORT				1
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif
-+	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
-+		#define CONFIG_RTW_MAC_HIDDEN_RPT
-+	#endif
-+	/*#define CONFIG_AMPDU_PRETX_CD*/
-+	/*#define DBG_LA_MODE*/
-+	#ifdef CONFIG_P2P_PS
-+		#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
-+	#endif
-+	#define CONFIG_RTS_FULL_BW
-+/*	#define CONFIG_NARROWBAND_SUPPORTING	*/
-+	#ifdef CONFIG_NARROWBAND_SUPPORTING
-+		#define CONFIG_NB_VALUE		RTW_NB_CONFIG_NONE	/*RTW_NB_CONFIG_WIDTH_10 or RTW_NB_CONFIG_WIDTH_5	*/
-+	#endif
-+	#ifdef CONFIG_WOWLAN
-+		#define CONFIG_WOW_PATTERN_IN_TXFIFO
-+	#endif
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+	#define CONFIG_STOP_RESUME_BCN_BY_TXPAUSE /*to fixed no bcn issue*/
-+#endif
-+
-+#ifdef CONFIG_RTL8723B
-+	#undef RTL8723B_SUPPORT
-+	#define RTL8723B_SUPPORT				1
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif
-+	#define CONFIG_RTS_FULL_BW
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	#undef RTL8723D_SUPPORT
-+	#define RTL8723D_SUPPORT				1
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif
-+	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
-+		#define CONFIG_RTW_MAC_HIDDEN_RPT
-+	#endif
-+	#ifndef CONFIG_RTW_CUSTOMER_STR
-+		#define CONFIG_RTW_CUSTOMER_STR
-+	#endif
-+	#define CONFIG_RTS_FULL_BW
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	#undef RTL8814A_SUPPORT
-+	#define RTL8814A_SUPPORT				1
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif
-+	#define CONFIG_FW_CORRECT_BCN
-+	#ifdef CONFIG_BEAMFORMING
-+		#define BEAMFORMING_SUPPORT		1	/*for phydm beamforming*/
-+		#define SUPPORT_MU_BF				0
-+	#endif
-+	#define CONFIG_RTS_FULL_BW
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+	#undef RTL8703B_SUPPORT
-+	#define RTL8703B_SUPPORT				1
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif
-+	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
-+		#define CONFIG_RTW_MAC_HIDDEN_RPT
-+	#endif
-+	#define CONFIG_RTS_FULL_BW
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8188F
-+	#undef RTL8188F_SUPPORT
-+	#define RTL8188F_SUPPORT				1
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif
-+	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
-+		#define CONFIG_RTW_MAC_HIDDEN_RPT
-+	#endif
-+	#ifndef CONFIG_RTW_CUSTOMER_STR
-+		#define CONFIG_RTW_CUSTOMER_STR
-+	#endif
-+	#define CONFIG_RTS_FULL_BW
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8188GTV
-+	#undef RTL8188F_SUPPORT
-+	#define RTL8188F_SUPPORT				1
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif
-+	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
-+		#define CONFIG_RTW_MAC_HIDDEN_RPT
-+	#endif
-+	#ifndef CONFIG_RTW_CUSTOMER_STR
-+		#define CONFIG_RTW_CUSTOMER_STR
-+	#endif
-+	#define CONFIG_RTS_FULL_BW
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+
-+	#if defined(CONFIG_USB_HCI) && !defined(CONFIG_FW_OFFLOAD_SET_TXPWR_IDX)
-+	#define CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	#undef RTL8822B_SUPPORT
-+	#define RTL8822B_SUPPORT				1
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif /* CONFIG_FW_C2H_PKT */
-+	#define RTW_TX_PA_BIAS	/* Adjust TX PA Bias from eFuse */
-+	#define RTW_AMPDU_AGG_RETRY_AND_NEW
-+
-+	#ifdef CONFIG_WOWLAN
-+		#define CONFIG_GTK_OL
-+		/*#define CONFIG_ARP_KEEP_ALIVE*/
-+
-+		#ifdef CONFIG_GPIO_WAKEUP
-+			#ifndef WAKEUP_GPIO_IDX
-+				#define WAKEUP_GPIO_IDX	6	/* WIFI Chip Side */
-+			#endif /* !WAKEUP_GPIO_IDX */
-+		#endif /* CONFIG_GPIO_WAKEUP */
-+	#endif /* CONFIG_WOWLAN */
-+
-+	#ifdef CONFIG_CONCURRENT_MODE
-+		#define CONFIG_AP_PORT_SWAP
-+		#define CONFIG_FW_MULTI_PORT_SUPPORT
-+	#endif /* CONFIG_CONCURRENT_MODE */
-+
-+	/*
-+	 * Beamforming related definition
-+	 */
-+	/* Only support new beamforming mechanism */
-+	#ifdef CONFIG_BEAMFORMING
-+		#define RTW_BEAMFORMING_VERSION_2
-+	#endif /* CONFIG_BEAMFORMING */
-+
-+	#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
-+		#define CONFIG_RTW_MAC_HIDDEN_RPT
-+	#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
-+
-+	#ifndef DBG_RX_DFRAME_RAW_DATA
-+		#define DBG_RX_DFRAME_RAW_DATA
-+	#endif /* DBG_RX_DFRAME_RAW_DATA */
-+
-+	#ifndef RTW_IQK_FW_OFFLOAD
-+		#define RTW_IQK_FW_OFFLOAD
-+	#endif /* RTW_IQK_FW_OFFLOAD */
-+
-+	/* Checksum offload feature */
-+	/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/
-+	#if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG)
-+		#define CONFIG_RTW_NETIF_SG
-+	#endif
-+	#define CONFIG_TCP_CSUM_OFFLOAD_RX
-+
-+	#define CONFIG_ADVANCE_OTA
-+
-+	#ifdef CONFIG_MCC_MODE
-+		#define CONFIG_MCC_MODE_V2
-+		#define CONFIG_MCC_PHYDM_OFFLOAD
-+	#endif /* CONFIG_MCC_MODE */
-+
-+	#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
-+		#define CONFIG_TDLS_CH_SW_V2
-+	#endif
-+
-+	#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
-+		#ifdef CONFIG_TDLS_CH_SW_V2
-+			#define RTW_CHANNEL_SWITCH_OFFLOAD
-+		#endif
-+	#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
-+
-+	#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)
-+		/* Supported since fw v22.1 */
-+		#define RTW_PER_CMD_SUPPORT_FW
-+	#endif /* RTW_PER_CMD_SUPPORT_FW */
-+	#define CONFIG_SUPPORT_FIFO_DUMP
-+	#define CONFIG_HW_P0_TSF_SYNC
-+	#define CONFIG_BCN_RECV_TIME
-+	#ifdef CONFIG_P2P_PS
-+		#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
-+	#endif
-+	#define CONFIG_RTS_FULL_BW
-+
-+	#ifdef CONFIG_LPS
-+		#define CONFIG_LPS_ACK	/* Supported after FW v30 & v27.9 */
-+	#endif
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+#endif /* CONFIG_RTL8822B */
-+
-+#ifdef CONFIG_RTL8822C
-+	#undef RTL8822C_SUPPORT
-+	#define RTL8822C_SUPPORT				1
-+	/*#define DBG_LA_MODE*/
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif /* CONFIG_FW_C2H_PKT */
-+	#define RTW_TX_PA_BIAS	/* Adjust TX PA Bias from eFuse */
-+
-+	#ifdef CONFIG_WOWLAN
-+		#define CONFIG_GTK_OL
-+		/*#define CONFIG_ARP_KEEP_ALIVE*/
-+
-+		#ifdef CONFIG_GPIO_WAKEUP
-+			#ifndef WAKEUP_GPIO_IDX
-+				#define WAKEUP_GPIO_IDX	6	/* WIFI Chip Side */
-+			#endif /* !WAKEUP_GPIO_IDX */
-+		#endif /* CONFIG_GPIO_WAKEUP */
-+	#endif /* CONFIG_WOWLAN */
-+
-+	#ifdef CONFIG_CONCURRENT_MODE
-+		#define CONFIG_AP_PORT_SWAP
-+		#define CONFIG_FW_MULTI_PORT_SUPPORT
-+	#endif /* CONFIG_CONCURRENT_MODE */
-+
-+	/*
-+	 * Beamforming related definition
-+	 */
-+	/* Only support new beamforming mechanism */
-+	#ifdef CONFIG_BEAMFORMING
-+		#define RTW_BEAMFORMING_VERSION_2
-+	#endif /* CONFIG_BEAMFORMING */
-+
-+	#ifdef CONFIG_NO_FW
-+		#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
-+			#undef CONFIG_RTW_MAC_HIDDEN_RPT
-+		#endif
-+	#else
-+		#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
-+			#define CONFIG_RTW_MAC_HIDDEN_RPT
-+		#endif
-+	#endif
-+
-+	#ifndef DBG_RX_DFRAME_RAW_DATA
-+		#define DBG_RX_DFRAME_RAW_DATA
-+	#endif /* DBG_RX_DFRAME_RAW_DATA */
-+
-+	#ifndef RTW_IQK_FW_OFFLOAD
-+		/* #define RTW_IQK_FW_OFFLOAD */
-+	#endif /* RTW_IQK_FW_OFFLOAD */
-+	#define CONFIG_ADVANCE_OTA
-+
-+	#ifdef CONFIG_MCC_MODE
-+		#define CONFIG_MCC_MODE_V2
-+		#define CONFIG_MCC_PHYDM_OFFLOAD
-+	#endif /* CONFIG_MCC_MODE */
-+
-+	#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
-+		#define CONFIG_TDLS_CH_SW_V2
-+	#endif
-+
-+	#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
-+		#ifdef CONFIG_TDLS_CH_SW_V2
-+			#define RTW_CHANNEL_SWITCH_OFFLOAD
-+		#endif
-+	#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
-+
-+	#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)
-+		/* Supported since fw v22.1 */
-+		#define RTW_PER_CMD_SUPPORT_FW
-+	#endif /* RTW_PER_CMD_SUPPORT_FW */
-+	#define CONFIG_SUPPORT_FIFO_DUMP
-+	#define CONFIG_HW_P0_TSF_SYNC
-+	#define CONFIG_BCN_RECV_TIME
-+
-+	/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/
-+	#if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG)
-+		#define CONFIG_RTW_NETIF_SG
-+	#endif
-+	#define CONFIG_TCP_CSUM_OFFLOAD_RX
-+
-+	#ifdef CONFIG_P2P_PS
-+		#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
-+	#endif
-+	#define CONFIG_RTS_FULL_BW
-+	
-+	#ifdef CONFIG_LPS
-+		#define CONFIG_LPS_ACK	/* Supported after FW v07 */
-+		#define CONFIG_LPS_1T1R /* Supported after FW v07 */
-+	#endif
-+
-+	#define CONFIG_BT_EFUSE_MASK
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+	#ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
-+	#define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
-+	#endif
-+
-+	#define CONFIG_RTL8822C_XCAP_NEW_POLICY
-+
-+	#define CONFIG_SUPPORT_DYNAMIC_TXPWR
-+#endif /* CONFIG_RTL8822C */
-+
-+#ifdef CONFIG_RTL8821C
-+	#undef RTL8821C_SUPPORT
-+	#define RTL8821C_SUPPORT				1
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif
-+	#ifdef CONFIG_NO_FW
-+		#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
-+			#undef CONFIG_RTW_MAC_HIDDEN_RPT
-+		#endif
-+	#else
-+		#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
-+			#define CONFIG_RTW_MAC_HIDDEN_RPT
-+		#endif
-+	#endif
-+	#define LOAD_FW_HEADER_FROM_DRIVER
-+	#define CONFIG_PHY_CAPABILITY_QUERY
-+	#ifdef CONFIG_CONCURRENT_MODE
-+	#define CONFIG_AP_PORT_SWAP
-+	#define CONFIG_FW_MULTI_PORT_SUPPORT
-+	#endif
-+	#define CONFIG_SUPPORT_FIFO_DUMP
-+	#ifndef RTW_IQK_FW_OFFLOAD
-+		#define RTW_IQK_FW_OFFLOAD
-+	#endif /* RTW_IQK_FW_OFFLOAD */
-+	/*#define CONFIG_AMPDU_PRETX_CD*/
-+	/*#define DBG_PRE_TX_HANG*/
-+
-+	/* Beamforming related definition */
-+	/* Only support new beamforming mechanism */
-+	#ifdef CONFIG_BEAMFORMING
-+		#define RTW_BEAMFORMING_VERSION_2
-+	#endif /* CONFIG_BEAMFORMING */
-+	#define CONFIG_HW_P0_TSF_SYNC
-+	#define CONFIG_BCN_RECV_TIME
-+	#ifdef CONFIG_P2P_PS
-+		#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
-+	#endif
-+	#define CONFIG_RTS_FULL_BW
-+
-+	#ifdef CONFIG_LPS
-+		/* #define CONFIG_LPS_ACK */	/* Supported after FW v25 */
-+	#endif
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+
-+	#define CONFIG_BT_EFUSE_MASK
-+#endif /*CONFIG_RTL8821C*/
-+
-+#ifdef CONFIG_RTL8710B
-+	#undef RTL8710B_SUPPORT
-+	#define RTL8710B_SUPPORT				1
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif
-+	#define CONFIG_RTS_FULL_BW
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8814B
-+	#undef RTL8814B_SUPPORT
-+	#define RTL8814B_SUPPORT				1
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif /* CONFIG_FW_C2H_PKT */
-+	#define RTW_TX_PA_BIAS	/* Adjust TX PA Bias from eFuse */
-+	#define RTW_AMPDU_AGG_RETRY_AND_NEW
-+
-+	#ifdef CONFIG_WOWLAN
-+		#define CONFIG_GTK_OL
-+		/*#define CONFIG_ARP_KEEP_ALIVE*/
-+
-+		#ifdef CONFIG_GPIO_WAKEUP
-+			#ifndef WAKEUP_GPIO_IDX
-+				#define WAKEUP_GPIO_IDX	6	/* WIFI Chip Side */
-+			#endif /* !WAKEUP_GPIO_IDX */
-+		#endif /* CONFIG_GPIO_WAKEUP */
-+	#endif /* CONFIG_WOWLAN */
-+
-+	#ifdef CONFIG_CONCURRENT_MODE
-+		/*#define CONFIG_AP_PORT_SWAP*/
-+		#define CONFIG_FW_MULTI_PORT_SUPPORT
-+	#endif /* CONFIG_CONCURRENT_MODE */
-+
-+	/*
-+	 * Beamforming related definition
-+	 */
-+	/* Only support new beamforming mechanism */
-+	#ifdef CONFIG_BEAMFORMING
-+		#define RTW_BEAMFORMING_VERSION_2
-+	#endif /* CONFIG_BEAMFORMING */
-+
-+	#ifndef DBG_RX_DFRAME_RAW_DATA
-+		#define DBG_RX_DFRAME_RAW_DATA
-+	#endif /* DBG_RX_DFRAME_RAW_DATA */
-+
-+	#ifndef RTW_IQK_FW_OFFLOAD
-+		#define RTW_IQK_FW_OFFLOAD
-+	#endif /* RTW_IQK_FW_OFFLOAD */
-+
-+	/* Checksum offload feature */
-+	/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/ /* not ready */
-+	#define CONFIG_TCP_CSUM_OFFLOAD_RX
-+
-+	#define CONFIG_ADVANCE_OTA
-+
-+	#ifdef CONFIG_MCC_MODE
-+		#define CONFIG_MCC_MODE_V2
-+		#define CONFIG_MCC_PHYDM_OFFLOAD
-+	#endif /* CONFIG_MCC_MODE */
-+
-+	#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
-+		#define CONFIG_TDLS_CH_SW_V2
-+	#endif
-+
-+	#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
-+		#ifdef CONFIG_TDLS_CH_SW_V2
-+			#define RTW_CHANNEL_SWITCH_OFFLOAD
-+		#endif
-+	#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
-+
-+	#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)
-+		/* Supported since fw v22.1 */
-+		#define RTW_PER_CMD_SUPPORT_FW
-+	#endif /* RTW_PER_CMD_SUPPORT_FW */
-+	#define CONFIG_SUPPORT_FIFO_DUMP
-+	#define CONFIG_HW_P0_TSF_SYNC
-+	#define CONFIG_BCN_RECV_TIME
-+	#ifdef CONFIG_P2P_PS
-+		#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
-+	#endif
-+	#define CONFIG_RTS_FULL_BW
-+
-+	#define CONFIG_PROTSEL_PORT
-+	#define CONFIG_PROTSEL_ATIMDTIM
-+	#define CONFIG_PROTSEL_MACSLEEP
-+
-+	#define CONFIG_HAS_HW_VAR_BCN_CTRL_ADDR
-+	#define CONFIG_HAS_HW_VAR_BCN_FUNC
-+	#define CONFIG_HAS_HW_VAR_MLME_DISCONNECT
-+	#define CONFIG_HAS_HW_VAR_MLME_JOIN
-+	#define CONFIG_HAS_HW_VAR_CORRECT_TSF
-+	#define CONFIG_HAS_TX_BEACON_PAUSE
-+
-+	#define CONFIG_RTW_TX_NPATH_EN		/* 8814B is always 4TX */
-+
-+	#ifdef CONFIG_LPS
-+		#define CONFIG_LPS_ACK	/* Supported after FW v04 */
-+	#endif
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+	#ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
-+	#define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
-+	#endif
-+#endif /* CONFIG_RTL8814B */
-+#ifdef CONFIG_RTL8723F
-+	#undef RTL8723F_SUPPORT
-+	#define RTL8723F_SUPPORT				1
-+
-+	/* Use HALMAC architecture, necessary for 8723F */
-+	#define RTW_HALMAC
-+
-+	/*#define DBG_LA_MODE*/
-+
-+	#ifndef CONFIG_FW_C2H_PKT
-+		#define CONFIG_FW_C2H_PKT
-+	#endif /* CONFIG_FW_C2H_PKT */
-+
-+	#define RTW_TX_PA_BIAS	/* Adjust TX PA Bias from eFuse */
-+
-+	#ifdef CONFIG_WOWLAN
-+		#define CONFIG_WOW_PATTERN_IN_TXFIFO
-+	#endif
-+
-+#if 0 /* todo: 8723F , need to check in the future */
-+	#ifdef CONFIG_WOWLAN
-+		#define CONFIG_GTK_OL
-+		/*#define CONFIG_ARP_KEEP_ALIVE*/
-+
-+		#ifdef CONFIG_GPIO_WAKEUP
-+			#ifndef WAKEUP_GPIO_IDX
-+				#define WAKEUP_GPIO_IDX	6	/* WIFI Chip Side */
-+			#endif /* !WAKEUP_GPIO_IDX */
-+		#endif /* CONFIG_GPIO_WAKEUP */
-+	#endif /* CONFIG_WOWLAN */
-+#endif
-+
-+	#ifdef CONFIG_CONCURRENT_MODE
-+		#define CONFIG_AP_PORT_SWAP
-+		#define CONFIG_FW_MULTI_PORT_SUPPORT
-+	#endif /* CONFIG_CONCURRENT_MODE */
-+
-+	#ifdef CONFIG_NO_FW
-+		#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
-+			#undef CONFIG_RTW_MAC_HIDDEN_RPT
-+		#endif
-+	#else
-+		#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
-+			#define CONFIG_RTW_MAC_HIDDEN_RPT
-+		#endif
-+	#endif
-+
-+	#ifndef DBG_RX_DFRAME_RAW_DATA
-+		#define DBG_RX_DFRAME_RAW_DATA
-+	#endif /* DBG_RX_DFRAME_RAW_DATA */
-+
-+	/*#define RTW_IQK_FW_OFFLOAD*/
-+	#define CONFIG_ADVANCE_OTA
-+
-+	#ifdef CONFIG_MCC_MODE
-+		#define CONFIG_MCC_MODE_V2
-+		#define CONFIG_MCC_PHYDM_OFFLOAD
-+	#endif /* CONFIG_MCC_MODE */
-+
-+	#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
-+		#define CONFIG_TDLS_CH_SW_V2
-+	#endif
-+
-+	#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
-+		#ifdef CONFIG_TDLS_CH_SW_V2
-+			#define RTW_CHANNEL_SWITCH_OFFLOAD
-+		#endif
-+	#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
-+
-+	#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)
-+		/* Supported since fw v22.1 */
-+		#define RTW_PER_CMD_SUPPORT_FW
-+	#endif /* RTW_PER_CMD_SUPPORT_FW */
-+	#define CONFIG_SUPPORT_FIFO_DUMP
-+	#define CONFIG_HW_P0_TSF_SYNC
-+	#define CONFIG_BCN_RECV_TIME
-+
-+	/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/
-+	#if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG)
-+		#define CONFIG_RTW_NETIF_SG
-+	#endif
-+	#define CONFIG_TCP_CSUM_OFFLOAD_RX
-+
-+	#ifdef CONFIG_P2P_PS
-+		#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
-+	#endif
-+
-+	#define CONFIG_RTS_FULL_BW
-+	
-+	#ifdef CONFIG_LPS
-+		#define CONFIG_LPS_ACK
-+	#endif
-+
-+	#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#define CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	#endif
-+	#ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
-+	#define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
-+	#endif
-+#endif /* CONFIG_RTL8723F */
-+#endif /*__HAL_IC_CFG_H__*/
-diff --git a/drivers/staging/rtl8723cs/include/hal_intf.h b/drivers/staging/rtl8723cs/include/hal_intf.h
-new file mode 100644
-index 000000000000..945f19a9ed50
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_intf.h
-@@ -0,0 +1,909 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_INTF_H__
-+#define __HAL_INTF_H__
-+
-+
-+enum RTL871X_HCI_TYPE {
-+	RTW_PCIE	= BIT0,
-+	RTW_USB	= BIT1,
-+	RTW_SDIO	= BIT2,
-+	RTW_GSPI	= BIT3,
-+};
-+
-+enum _CHIP_TYPE {
-+
-+	NULL_CHIP_TYPE,
-+	RTL8188E,
-+	RTL8192E,
-+	RTL8812,
-+	RTL8821, /* RTL8811 */
-+	RTL8723B,
-+	RTL8814A,
-+	RTL8703B,
-+	RTL8188F,
-+	RTL8188GTV,
-+	RTL8822B,
-+	RTL8723D,
-+	RTL8821C,
-+	RTL8710B,
-+	RTL8192F,
-+	RTL8822C,
-+	RTL8814B,
-+	RTL8723F,
-+	MAX_CHIP_TYPE
-+};
-+
-+#ifdef RTW_HALMAC
-+enum fw_mem {
-+	FW_EMEM,
-+	FW_IMEM,
-+	FW_DMEM,
-+};
-+#endif
-+
-+extern const u32 _chip_type_to_odm_ic_type[];
-+#define chip_type_to_odm_ic_type(chip_type) (((chip_type) >= MAX_CHIP_TYPE) ? _chip_type_to_odm_ic_type[MAX_CHIP_TYPE] : _chip_type_to_odm_ic_type[(chip_type)])
-+
-+typedef enum _HAL_HW_TIMER_TYPE {
-+	HAL_TIMER_NONE = 0,
-+	HAL_TIMER_TXBF = 1,
-+	HAL_TIMER_EARLYMODE = 2,
-+} HAL_HW_TIMER_TYPE, *PHAL_HW_TIMER_TYPE;
-+
-+
-+typedef enum _HW_VARIABLES {
-+	HW_VAR_MEDIA_STATUS,
-+	HW_VAR_SET_OPMODE,
-+	HW_VAR_MAC_ADDR,
-+	HW_VAR_BSSID,
-+	HW_VAR_INIT_RTS_RATE,
-+	HW_VAR_BASIC_RATE,
-+	HW_VAR_TXPAUSE,
-+	HW_VAR_BCN_FUNC,
-+	HW_VAR_BCN_CTRL_ADDR,
-+	HW_VAR_CORRECT_TSF,
-+	HW_VAR_RCR,
-+	HW_VAR_MLME_DISCONNECT,
-+	HW_VAR_MLME_SITESURVEY,
-+	HW_VAR_MLME_JOIN,
-+	HW_VAR_ON_RCR_AM,
-+	HW_VAR_OFF_RCR_AM,
-+	HW_VAR_BEACON_INTERVAL,
-+	HW_VAR_SLOT_TIME,
-+	HW_VAR_RESP_SIFS,
-+	HW_VAR_ACK_PREAMBLE,
-+	HW_VAR_SEC_CFG,
-+	HW_VAR_SEC_DK_CFG,
-+	HW_VAR_BCN_VALID,
-+	HW_VAR_FREECNT,
-+
-+	/* PHYDM odm->SupportAbility */
-+	HW_VAR_CAM_EMPTY_ENTRY,
-+	HW_VAR_CAM_INVALID_ALL,
-+	HW_VAR_AC_PARAM_VO,
-+	HW_VAR_AC_PARAM_VI,
-+	HW_VAR_AC_PARAM_BE,
-+	HW_VAR_AC_PARAM_BK,
-+	HW_VAR_ACM_CTRL,
-+#ifdef CONFIG_WMMPS_STA
-+	HW_VAR_UAPSD_TID,
-+#endif /* CONFIG_WMMPS_STA */
-+	HW_VAR_AMPDU_MIN_SPACE,
-+#ifdef CONFIG_80211N_HT
-+	HW_VAR_AMPDU_FACTOR,
-+#endif /* CONFIG_80211N_HT */
-+	HW_VAR_RXDMA_AGG_PG_TH,
-+	HW_VAR_SET_RPWM,
-+	HW_VAR_CPWM,
-+	HW_VAR_H2C_FW_PWRMODE,
-+	HW_VAR_H2C_FW_PWRMODE_RFON_CTRL,
-+	HW_VAR_H2C_INACTIVE_IPS,
-+	HW_VAR_H2C_PS_TUNE_PARAM,
-+	HW_VAR_H2C_FW_JOINBSSRPT,
-+	HW_VAR_FWLPS_RF_ON,
-+	HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
-+#ifdef CONFIG_LPS_POFF
-+	HW_VAR_LPS_POFF_INIT,
-+	HW_VAR_LPS_POFF_DEINIT,
-+	HW_VAR_LPS_POFF_SET_MODE,
-+	HW_VAR_LPS_POFF_WOW_EN,
-+#endif
-+#ifdef CONFIG_LPS_PG
-+	HW_VAR_LPS_PG_HANDLE,
-+#endif
-+	HW_VAR_TRIGGER_GPIO_0,
-+	HW_VAR_BT_SET_COEXIST,
-+	HW_VAR_BT_ISSUE_DELBA,
-+	HW_VAR_SWITCH_EPHY_WoWLAN,
-+	HW_VAR_EFUSE_USAGE,
-+	HW_VAR_EFUSE_BYTES,
-+	HW_VAR_EFUSE_BT_USAGE,
-+	HW_VAR_EFUSE_BT_BYTES,
-+	HW_VAR_FIFO_CLEARN_UP,
-+	HW_VAR_RESTORE_HW_SEQ,
-+	HW_VAR_CHECK_TXBUF,
-+	HW_VAR_PCIE_STOP_TX_DMA,
-+	HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
-+	HW_VAR_HCI_SUS_STATE,
-+	/* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */
-+	/* Unit in microsecond. 0 means disable this function. */
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+	HW_VAR_WOWLAN,
-+	HW_VAR_WAKEUP_REASON,
-+#endif
-+	HW_VAR_RPWM_TOG,
-+#ifdef CONFIG_GPIO_WAKEUP
-+	HW_VAR_WOW_OUTPUT_GPIO,
-+	HW_VAR_WOW_INPUT_GPIO,
-+	HW_SET_GPIO_WL_CTRL,
-+#endif
-+	HW_VAR_SYS_CLKR,
-+	HW_VAR_NAV_UPPER,
-+	HW_VAR_RPT_TIMER_SETTING,
-+	HW_VAR_TX_RPT_MAX_MACID,
-+	HW_VAR_CHK_HI_QUEUE_EMPTY,
-+	HW_VAR_CHK_MGQ_CPU_EMPTY,
-+	HW_VAR_DL_BCN_SEL,
-+	HW_VAR_AMPDU_MAX_TIME,
-+	HW_VAR_WIRELESS_MODE,
-+	HW_VAR_USB_MODE,
-+	HW_VAR_PORT_SWITCH,
-+	HW_VAR_PORT_CFG,
-+	HW_VAR_DO_IQK,
-+	HW_VAR_DM_IN_LPS_LCLK,/*flag CONFIG_LPS_LCLK_WD_TIMER*/
-+	HW_VAR_SET_REQ_FW_PS,
-+	HW_VAR_FW_PS_STATE,
-+	HW_VAR_SOUNDING_ENTER,
-+	HW_VAR_SOUNDING_LEAVE,
-+	HW_VAR_SOUNDING_RATE,
-+	HW_VAR_SOUNDING_STATUS,
-+	HW_VAR_SOUNDING_FW_NDPA,
-+	HW_VAR_SOUNDING_CLK,
-+	HW_VAR_SOUNDING_SET_GID_TABLE,
-+	HW_VAR_SOUNDING_CSI_REPORT,
-+	/*Add by YuChen for TXBF HW timer*/
-+	HW_VAR_HW_REG_TIMER_INIT,
-+	HW_VAR_HW_REG_TIMER_RESTART,
-+	HW_VAR_HW_REG_TIMER_START,
-+	HW_VAR_HW_REG_TIMER_STOP,
-+	/*Add by YuChen for TXBF HW timer*/
-+	HW_VAR_DL_RSVD_PAGE,
-+	HW_VAR_MACID_LINK,
-+	HW_VAR_MACID_NOLINK,
-+	HW_VAR_DUMP_MAC_QUEUE_INFO,
-+	HW_VAR_ASIX_IOT,
-+#ifdef CONFIG_MBSSID_CAM
-+	HW_VAR_MBSSID_CAM_WRITE,
-+	HW_VAR_MBSSID_CAM_CLEAR,
-+	HW_VAR_RCR_MBSSID_EN,
-+#endif
-+	HW_VAR_EN_HW_UPDATE_TSF,
-+	HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO,
-+	HW_VAR_CH_SW_IQK_INFO_BACKUP,
-+	HW_VAR_CH_SW_IQK_INFO_RESTORE,
-+
-+	HW_VAR_DBI,
-+	HW_VAR_MDIO,
-+	HW_VAR_L1OFF_CAPABILITY,
-+	HW_VAR_L1OFF_NIC_SUPPORT,
-+	HW_VAR_BCN_EARLY_C2H_RPT,
-+	HW_VAR_SET_DRV_ERLY_INT,
-+	HW_VAR_DUMP_MAC_TXFIFO,
-+	HW_VAR_PWR_CMD,
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+	HW_VAR_BCN_HEAD_SEL,
-+#endif
-+	HW_VAR_SET_SOML_PARAM,
-+	HW_VAR_ENABLE_RX_BAR,
-+	HW_VAR_TSF_AUTO_SYNC,
-+	HW_VAR_LPS_STATE_CHK,
-+	HW_VAR_LPS_RFON_CHK,
-+	#ifdef CONFIG_RTS_FULL_BW
-+	HW_VAR_SET_RTS_BW,
-+	#endif
-+#if defined(CONFIG_PCI_HCI)
-+	HW_VAR_ENSWBCN,
-+#endif
-+#ifdef CONFIG_WOWLAN
-+	HW_VAR_VENDOR_WOW_MODE,
-+#endif /* CONFIG_WOWLAN */
-+} HW_VARIABLES;
-+
-+typedef enum _HAL_DEF_VARIABLE {
-+	HAL_DEF_UNDERCORATEDSMOOTHEDPWDB,
-+	HAL_DEF_IS_SUPPORT_ANT_DIV,
-+	HAL_DEF_DRVINFO_SZ,
-+	HAL_DEF_MAX_RECVBUF_SZ,
-+	HAL_DEF_RX_PACKET_OFFSET,
-+	HAL_DEF_RX_DMA_SZ_WOW,
-+	HAL_DEF_RX_DMA_SZ,
-+	HAL_DEF_RX_PAGE_SIZE,
-+	HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */
-+	HAL_DEF_RA_DECISION_RATE,
-+	HAL_DEF_RA_SGI,
-+	HAL_DEF_PT_PWR_STATUS,
-+	HAL_DEF_TX_LDPC,				/* LDPC support */
-+	HAL_DEF_RX_LDPC,				/* LDPC support */
-+	HAL_DEF_TX_STBC,				/* TX STBC support */
-+	HAL_DEF_RX_STBC,				/* RX STBC support */
-+	HAL_DEF_EXPLICIT_BEAMFORMER,/* Explicit  Compressed Steering Capable */
-+	HAL_DEF_EXPLICIT_BEAMFORMEE,/* Explicit Compressed Beamforming Feedback Capable */
-+	HAL_DEF_VHT_MU_BEAMFORMER,	/* VHT MU Beamformer support */
-+	HAL_DEF_VHT_MU_BEAMFORMEE,	/* VHT MU Beamformee support */
-+	HAL_DEF_BEAMFORMER_CAP,
-+	HAL_DEF_BEAMFORMEE_CAP,
-+	HW_VAR_MAX_RX_AMPDU_FACTOR,
-+	HW_DEF_RA_INFO_DUMP,
-+	HAL_DEF_DBG_DUMP_TXPKT,
-+
-+	HAL_DEF_TX_PAGE_SIZE,
-+	HAL_DEF_TX_PAGE_BOUNDARY,
-+	HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN,
-+	HAL_DEF_TX_BUFFER_LAST_ENTRY,
-+	HAL_DEF_ANT_DETECT,/* to do for 8723a */
-+	HAL_DEF_PCI_ASPM_OSC, /* Support for ASPM OSC, added by Roger, 2013.03.27. */
-+	HAL_DEF_EFUSE_USAGE,	/* Get current EFUSE utilization. 2008.12.19. Added by Roger. */
-+	HAL_DEF_EFUSE_BYTES,
-+	HW_VAR_BEST_AMPDU_DENSITY,
-+} HAL_DEF_VARIABLE;
-+
-+typedef enum _HAL_ODM_VARIABLE {
-+	HAL_ODM_STA_INFO,
-+	HAL_ODM_P2P_STATE,
-+	HAL_ODM_WIFI_DISPLAY_STATE,
-+	HAL_ODM_REGULATION,
-+	HAL_ODM_INITIAL_GAIN,
-+	HAL_ODM_RX_INFO_DUMP,
-+	HAL_ODM_RX_Dframe_INFO,
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	HAL_ODM_ANTDIV_SELECT
-+#endif
-+} HAL_ODM_VARIABLE;
-+
-+typedef enum _HAL_INTF_PS_FUNC {
-+	HAL_USB_SELECT_SUSPEND,
-+	HAL_MAX_ID,
-+} HAL_INTF_PS_FUNC;
-+
-+typedef s32(*c2h_id_filter)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
-+
-+struct txpwr_idx_comp;
-+
-+struct hal_ops {
-+	/*** initialize section ***/
-+	void	(*read_chip_version)(_adapter *padapter);
-+	void	(*init_default_value)(_adapter *padapter);
-+	void	(*intf_chip_configure)(_adapter *padapter);
-+	u8	(*read_adapter_info)(_adapter *padapter);
-+	u32(*hal_power_on)(_adapter *padapter);
-+	void	(*hal_power_off)(_adapter *padapter);
-+	u32(*hal_init)(_adapter *padapter);
-+	u32(*hal_deinit)(_adapter *padapter);
-+	void	(*dm_init)(_adapter *padapter);
-+	void	(*dm_deinit)(_adapter *padapter);
-+
-+	/*** xmit section ***/
-+	s32(*init_xmit_priv)(_adapter *padapter);
-+	void	(*free_xmit_priv)(_adapter *padapter);
-+	s32(*hal_xmit)(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	/*
-+	 * mgnt_xmit should be implemented to run in interrupt context
-+	 */
-+	s32(*mgnt_xmit)(_adapter *padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32(*hal_mgmt_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32(*hal_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+	s32(*xmit_thread_handler)(_adapter *padapter);
-+#endif
-+	void	(*run_thread)(_adapter *padapter);
-+	void	(*cancel_thread)(_adapter *padapter);
-+
-+	/*** recv section ***/
-+	s32(*init_recv_priv)(_adapter *padapter);
-+	void	(*free_recv_priv)(_adapter *padapter);
-+#ifdef CONFIG_RECV_THREAD_MODE
-+	s32 (*recv_hdl)(_adapter *adapter);
-+#endif
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
-+	u32(*inirp_init)(_adapter *padapter);
-+	u32(*inirp_deinit)(_adapter *padapter);
-+#endif
-+	/*** interrupt hdl section ***/
-+	void	(*enable_interrupt)(_adapter *padapter);
-+	void	(*disable_interrupt)(_adapter *padapter);
-+	u8(*check_ips_status)(_adapter *padapter);
-+#if defined(CONFIG_PCI_HCI)
-+	s32(*interrupt_handler)(_adapter *padapter);
-+	void (*unmap_beacon_icf)(_adapter *padapter);
-+#endif
-+
-+#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
-+	void	(*interrupt_handler)(_adapter *padapter, u16 pkt_len, u8 *pbuf);
-+#endif
-+
-+#if defined(CONFIG_PCI_HCI)
-+	void	(*irp_reset)(_adapter *padapter);
-+#endif
-+
-+	/*** DM section ***/
-+#ifdef CONFIG_RTW_SW_LED
-+	void	(*InitSwLeds)(_adapter *padapter);
-+	void	(*DeInitSwLeds)(_adapter *padapter);
-+#endif
-+	void	(*set_chnl_bw_handler)(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80);
-+
-+	void (*set_tx_power_level_handler)(_adapter *adapter, u8 channel);
-+	void (*set_txpwr_done)(_adapter *adapter);
-+	void (*set_tx_power_index_handler)(_adapter *adapter, u32 powerindex, enum rf_path rfpath, u8 rate);
-+
-+	u8 (*get_tx_power_index_handler)(_adapter *adapter, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate
-+		, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch, struct txpwr_idx_comp *tic);
-+	s8 (*get_txpwr_target_extra_bias)(_adapter *adapter, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch);
-+
-+	void	(*hal_dm_watchdog)(_adapter *padapter);
-+
-+	u8	(*set_hw_reg_handler)(_adapter *padapter, u8	variable, u8 *val);
-+
-+	void	(*GetHwRegHandler)(_adapter *padapter, u8	variable, u8 *val);
-+
-+
-+
-+	u8 (*get_hal_def_var_handler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
-+
-+	u8(*SetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
-+
-+	void	(*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);
-+	void	(*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet);
-+
-+	void	(*SetBeaconRelatedRegistersHandler)(_adapter *padapter);
-+
-+	u8(*interface_ps_func)(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
-+
-+	u32(*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask);
-+	void	(*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
-+	u32 (*read_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask);
-+	void	(*write_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
-+#ifdef CONFIG_SYSON_INDIRECT_ACCESS
-+	u32 (*read_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask);
-+	void (*write_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
-+#endif
-+	void (*read_wmmedca_reg)(_adapter *padapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params);
-+	
-+#ifdef CONFIG_HOSTAPD_MLME
-+	s32(*hostap_mgnt_xmit_entry)(_adapter *padapter, _pkt *pkt);
-+#endif
-+
-+	void (*EfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);
-+	void (*BTEfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);
-+	void (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest);
-+	void (*EFUSEGetEfuseDefinition)(_adapter *padapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);
-+	u16(*EfuseGetCurrentSize)(_adapter *padapter, u8 efuseType, BOOLEAN bPseudoTest);
-+	int	(*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
-+	int	(*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
-+	u8(*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
-+	BOOLEAN(*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
-+#if defined(CONFIG_RTL8710B)
-+	BOOLEAN(*efuse_indirect_read4)(_adapter *padapter, u16 regaddr, u8 *value);
-+#endif
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	void (*sreset_init_value)(_adapter *padapter);
-+	void (*sreset_reset_value)(_adapter *padapter);
-+	void (*silentreset)(_adapter *padapter);
-+	void (*sreset_xmit_status_check)(_adapter *padapter);
-+	void (*sreset_linked_status_check)(_adapter *padapter);
-+	u8(*sreset_get_wifi_status)(_adapter *padapter);
-+	bool (*sreset_inprogress)(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_IOL
-+	int (*IOL_exec_cmds_sync)(_adapter *padapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
-+#endif
-+
-+	void (*hal_notch_filter)(_adapter *adapter, bool enable);
-+#ifdef RTW_HALMAC
-+	void (*hal_mac_c2h_handler)(_adapter *adapter, u8 *pbuf, u16 length);
-+#else
-+	s32(*c2h_handler)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
-+#endif
-+	void (*reqtxrpt)(_adapter *padapter, u8 macid);
-+	s32(*fill_h2c_cmd)(PADAPTER, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
-+	void (*fill_fake_txdesc)(PADAPTER, u8 *pDesc, u32 BufferLen,
-+				 u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
-+	s32(*fw_dl)(_adapter *adapter, u8 wowlan);
-+#ifdef RTW_HALMAC
-+	s32 (*fw_mem_dl)(_adapter *adapter, enum fw_mem mem);
-+#endif
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_PCI_HCI)
-+	void (*clear_interrupt)(_adapter *padapter);
-+#endif
-+	u8(*hal_get_tx_buff_rsvd_page_num)(_adapter *adapter, bool wowlan);
-+#ifdef CONFIG_GPIO_API
-+	void (*update_hisr_hsisr_ind)(PADAPTER padapter, u32 flag);
-+	int (*hal_gpio_func_check)(_adapter *padapter, u8 gpio_num);
-+	void (*hal_gpio_multi_func_reset)(_adapter *padapter, u8 gpio_num);
-+#endif
-+#ifdef CONFIG_FW_CORRECT_BCN
-+	void (*fw_correct_bcn)(PADAPTER padapter);
-+#endif
-+
-+#ifdef RTW_HALMAC
-+	u8(*init_mac_register)(PADAPTER);
-+	u8(*init_phy)(PADAPTER);
-+#endif /* RTW_HALMAC */
-+
-+#ifdef CONFIG_PCI_HCI
-+	void (*hal_set_l1ssbackdoor_handler)(_adapter *padapter, u8 enable);
-+#endif
-+
-+#ifdef CONFIG_RFKILL_POLL
-+	bool (*hal_radio_onoff_check)(_adapter *adapter, u8 *valid);
-+#endif
-+#ifdef CONFIG_PCI_TX_POLLING
-+	void (*tx_poll_handler)(_adapter *adapter);
-+#endif
-+};
-+
-+typedef	enum _RT_EEPROM_TYPE {
-+	EEPROM_93C46,
-+	EEPROM_93C56,
-+	EEPROM_BOOT_EFUSE,
-+} RT_EEPROM_TYPE, *PRT_EEPROM_TYPE;
-+
-+
-+
-+#define RF_CHANGE_BY_INIT	0
-+#define RF_CHANGE_BY_IPS	BIT28
-+#define RF_CHANGE_BY_PS	BIT29
-+#define RF_CHANGE_BY_HW	BIT30
-+#define RF_CHANGE_BY_SW	BIT31
-+
-+typedef enum _HARDWARE_TYPE {
-+	HARDWARE_TYPE_RTL8188EE,
-+	HARDWARE_TYPE_RTL8188EU,
-+	HARDWARE_TYPE_RTL8188ES,
-+	/*	NEW_GENERATION_IC */
-+	HARDWARE_TYPE_RTL8192EE,
-+	HARDWARE_TYPE_RTL8192EU,
-+	HARDWARE_TYPE_RTL8192ES,
-+	HARDWARE_TYPE_RTL8812E,
-+	HARDWARE_TYPE_RTL8812AU,
-+	HARDWARE_TYPE_RTL8811AU,
-+	HARDWARE_TYPE_RTL8821E,
-+	HARDWARE_TYPE_RTL8821U,
-+	HARDWARE_TYPE_RTL8821S,
-+	HARDWARE_TYPE_RTL8723BE,
-+	HARDWARE_TYPE_RTL8723BU,
-+	HARDWARE_TYPE_RTL8723BS,
-+	HARDWARE_TYPE_RTL8814AE,
-+	HARDWARE_TYPE_RTL8814AU,
-+	HARDWARE_TYPE_RTL8814AS,
-+	HARDWARE_TYPE_RTL8821BE,
-+	HARDWARE_TYPE_RTL8821BU,
-+	HARDWARE_TYPE_RTL8821BS,
-+	HARDWARE_TYPE_RTL8822BE,
-+	HARDWARE_TYPE_RTL8822BU,
-+	HARDWARE_TYPE_RTL8822BS,
-+	HARDWARE_TYPE_RTL8703BE,
-+	HARDWARE_TYPE_RTL8703BU,
-+	HARDWARE_TYPE_RTL8703BS,
-+	HARDWARE_TYPE_RTL8188FE,
-+	HARDWARE_TYPE_RTL8188FU,
-+	HARDWARE_TYPE_RTL8188FS,
-+	HARDWARE_TYPE_RTL8188GTVU,
-+	HARDWARE_TYPE_RTL8188GTVS,
-+	HARDWARE_TYPE_RTL8723DE,
-+	HARDWARE_TYPE_RTL8723DU,
-+	HARDWARE_TYPE_RTL8723DS,
-+	HARDWARE_TYPE_RTL8821CE,
-+	HARDWARE_TYPE_RTL8821CU,
-+	HARDWARE_TYPE_RTL8821CS,
-+	HARDWARE_TYPE_RTL8710BU,
-+	HARDWARE_TYPE_RTL8192FS,
-+	HARDWARE_TYPE_RTL8192FU,
-+	HARDWARE_TYPE_RTL8192FE,
-+	HARDWARE_TYPE_RTL8822CE,
-+	HARDWARE_TYPE_RTL8822CU,
-+	HARDWARE_TYPE_RTL8822CS,
-+	HARDWARE_TYPE_RTL8814BE,
-+	HARDWARE_TYPE_RTL8814BU,
-+	HARDWARE_TYPE_RTL8814BS,
-+	HARDWARE_TYPE_RTL8723FU,
-+	HARDWARE_TYPE_RTL8723FS,
-+	HARDWARE_TYPE_MAX,
-+} HARDWARE_TYPE;
-+
-+#define IS_NEW_GENERATION_IC(_Adapter)	(rtw_get_hw_type(_Adapter) >= HARDWARE_TYPE_RTL8192EE)
-+/*
-+ * RTL8188E Series
-+ *   */
-+#define IS_HARDWARE_TYPE_8188EE(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EE)
-+#define IS_HARDWARE_TYPE_8188EU(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EU)
-+#define IS_HARDWARE_TYPE_8188ES(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188ES)
-+#define	IS_HARDWARE_TYPE_8188E(_Adapter)	\
-+	(IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter))
-+
-+/* RTL8812 Series */
-+#define IS_HARDWARE_TYPE_8812E(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812E)
-+#define IS_HARDWARE_TYPE_8812AU(_Adapter)	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812AU)
-+#define IS_HARDWARE_TYPE_8812(_Adapter)			\
-+	(IS_HARDWARE_TYPE_8812E(_Adapter) || IS_HARDWARE_TYPE_8812AU(_Adapter))
-+
-+/* RTL8821 Series */
-+#define IS_HARDWARE_TYPE_8821E(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821E)
-+#define IS_HARDWARE_TYPE_8811AU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU)
-+#define IS_HARDWARE_TYPE_8821U(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821U || \
-+		rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU)
-+#define IS_HARDWARE_TYPE_8821S(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821S)
-+#define IS_HARDWARE_TYPE_8821(_Adapter)			\
-+	(IS_HARDWARE_TYPE_8821E(_Adapter) || IS_HARDWARE_TYPE_8821U(_Adapter) || IS_HARDWARE_TYPE_8821S(_Adapter))
-+
-+#define IS_HARDWARE_TYPE_JAGUAR(_Adapter)		\
-+	(IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter))
-+
-+/* RTL8192E Series */
-+#define IS_HARDWARE_TYPE_8192EE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EE)
-+#define IS_HARDWARE_TYPE_8192EU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EU)
-+#define IS_HARDWARE_TYPE_8192ES(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192ES)
-+
-+#define IS_HARDWARE_TYPE_8192E(_Adapter)		\
-+	(IS_HARDWARE_TYPE_8192EE(_Adapter) || IS_HARDWARE_TYPE_8192EU(_Adapter) || IS_HARDWARE_TYPE_8192ES(_Adapter))
-+
-+#define IS_HARDWARE_TYPE_8723BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BE)
-+#define IS_HARDWARE_TYPE_8723BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BU)
-+#define IS_HARDWARE_TYPE_8723BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BS)
-+
-+#define IS_HARDWARE_TYPE_8723B(_Adapter) \
-+	(IS_HARDWARE_TYPE_8723BE(_Adapter) || IS_HARDWARE_TYPE_8723BU(_Adapter) || IS_HARDWARE_TYPE_8723BS(_Adapter))
-+
-+/* RTL8814A Series */
-+#define IS_HARDWARE_TYPE_8814AE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AE)
-+#define IS_HARDWARE_TYPE_8814AU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AU)
-+#define IS_HARDWARE_TYPE_8814AS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AS)
-+
-+#define IS_HARDWARE_TYPE_8814A(_Adapter)		\
-+	(IS_HARDWARE_TYPE_8814AE(_Adapter) || IS_HARDWARE_TYPE_8814AU(_Adapter) || IS_HARDWARE_TYPE_8814AS(_Adapter))
-+
-+/* RTL8703B Series */
-+#define IS_HARDWARE_TYPE_8703BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BE)
-+#define IS_HARDWARE_TYPE_8703BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BS)
-+#define IS_HARDWARE_TYPE_8703BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BU)
-+#define	IS_HARDWARE_TYPE_8703B(_Adapter)			\
-+	(IS_HARDWARE_TYPE_8703BE(_Adapter) || IS_HARDWARE_TYPE_8703BU(_Adapter) || IS_HARDWARE_TYPE_8703BS(_Adapter))
-+
-+/* RTL8723D Series */
-+#define IS_HARDWARE_TYPE_8723DE(_Adapter)\
-+	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DE)
-+#define IS_HARDWARE_TYPE_8723DS(_Adapter)\
-+	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DS)
-+#define IS_HARDWARE_TYPE_8723DU(_Adapter)\
-+	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DU)
-+#define	IS_HARDWARE_TYPE_8723D(_Adapter)\
-+	(IS_HARDWARE_TYPE_8723DE(_Adapter) || \
-+	 IS_HARDWARE_TYPE_8723DU(_Adapter) || \
-+	 IS_HARDWARE_TYPE_8723DS(_Adapter))
-+
-+/* RTL8192F Series */
-+#define IS_HARDWARE_TYPE_8192FS(_Adapter)\
-+	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FS)
-+#define IS_HARDWARE_TYPE_8192FU(_Adapter)\
-+	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FU)	
-+#define IS_HARDWARE_TYPE_8192FE(_Adapter)\
-+	(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FE)	
-+#define	IS_HARDWARE_TYPE_8192F(_Adapter)\
-+	(IS_HARDWARE_TYPE_8192FS(_Adapter) ||\
-+	 IS_HARDWARE_TYPE_8192FU(_Adapter) ||\
-+	 IS_HARDWARE_TYPE_8192FE(_Adapter))
-+
-+/* RTL8188F Series */
-+#define IS_HARDWARE_TYPE_8188FE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FE)
-+#define IS_HARDWARE_TYPE_8188FS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FS)
-+#define IS_HARDWARE_TYPE_8188FU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FU)
-+#define	IS_HARDWARE_TYPE_8188F(_Adapter)			\
-+	(IS_HARDWARE_TYPE_8188FE(_Adapter) || IS_HARDWARE_TYPE_8188FU(_Adapter) || IS_HARDWARE_TYPE_8188FS(_Adapter))
-+
-+#define IS_HARDWARE_TYPE_8188GTVU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVU)
-+#define IS_HARDWARE_TYPE_8188GTVS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVS)
-+#define	IS_HARDWARE_TYPE_8188GTV(_Adapter)			\
-+	(IS_HARDWARE_TYPE_8188GTVU(_Adapter) || IS_HARDWARE_TYPE_8188GTVS(_Adapter))
-+
-+/* RTL8710B Series */
-+#define IS_HARDWARE_TYPE_8710BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8710BU)
-+#define IS_HARDWARE_TYPE_8710B(_Adapter) (IS_HARDWARE_TYPE_8710BU(_Adapter))
-+
-+#define IS_HARDWARE_TYPE_8821BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BE)
-+#define IS_HARDWARE_TYPE_8821BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BU)
-+#define IS_HARDWARE_TYPE_8821BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BS)
-+
-+#define IS_HARDWARE_TYPE_8821B(_Adapter)		\
-+	(IS_HARDWARE_TYPE_8821BE(_Adapter) || IS_HARDWARE_TYPE_8821BU(_Adapter) || IS_HARDWARE_TYPE_8821BS(_Adapter))
-+
-+#define IS_HARDWARE_TYPE_8822BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BE)
-+#define IS_HARDWARE_TYPE_8822BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BU)
-+#define IS_HARDWARE_TYPE_8822BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BS)
-+#define IS_HARDWARE_TYPE_8822B(_Adapter)		\
-+	(IS_HARDWARE_TYPE_8822BE(_Adapter) || IS_HARDWARE_TYPE_8822BU(_Adapter) || IS_HARDWARE_TYPE_8822BS(_Adapter))
-+
-+#define IS_HARDWARE_TYPE_8821CE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CE)
-+#define IS_HARDWARE_TYPE_8821CU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CU)
-+#define IS_HARDWARE_TYPE_8821CS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CS)
-+#define IS_HARDWARE_TYPE_8821C(_Adapter)		\
-+	(IS_HARDWARE_TYPE_8821CE(_Adapter) || IS_HARDWARE_TYPE_8821CU(_Adapter) || IS_HARDWARE_TYPE_8821CS(_Adapter))
-+
-+#define IS_HARDWARE_TYPE_8822CE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CE)
-+#define IS_HARDWARE_TYPE_8822CU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CU)
-+#define IS_HARDWARE_TYPE_8822CS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CS)
-+#define IS_HARDWARE_TYPE_8822C(_Adapter)		\
-+	(IS_HARDWARE_TYPE_8822CE(_Adapter) || IS_HARDWARE_TYPE_8822CU(_Adapter) || IS_HARDWARE_TYPE_8822CS(_Adapter))
-+
-+#define IS_HARDWARE_TYPE_8814BE(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BE)
-+#define IS_HARDWARE_TYPE_8814BU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BU)
-+#define IS_HARDWARE_TYPE_8814BS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BS)
-+#define IS_HARDWARE_TYPE_8814B(_Adapter)		\
-+		(IS_HARDWARE_TYPE_8814BE(_Adapter) || IS_HARDWARE_TYPE_8814BU(_Adapter) || IS_HARDWARE_TYPE_8814BS(_Adapter))
-+
-+#define IS_HARDWARE_TYPE_8723FU(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723FU)
-+#define IS_HARDWARE_TYPE_8723FS(_Adapter)		(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723FS)
-+#define IS_HARDWARE_TYPE_8723F(_Adapter)		\
-+		(IS_HARDWARE_TYPE_8723FU(_Adapter) || IS_HARDWARE_TYPE_8723FS(_Adapter))
-+
-+#define IS_HARDWARE_TYPE_JAGUAR2(_Adapter)		\
-+	(IS_HARDWARE_TYPE_8814A(_Adapter) || IS_HARDWARE_TYPE_8821B(_Adapter) || IS_HARDWARE_TYPE_8822B(_Adapter) || IS_HARDWARE_TYPE_8821C(_Adapter))
-+
-+#define IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter)		\
-+	(IS_HARDWARE_TYPE_JAGUAR(_Adapter) || IS_HARDWARE_TYPE_JAGUAR2(_Adapter))
-+
-+#define IS_HARDWARE_TYPE_JAGUAR3(_Adapter)		\
-+	(IS_HARDWARE_TYPE_8814B(_Adapter) || IS_HARDWARE_TYPE_8822C(_Adapter))
-+
-+#define IS_HARDWARE_TYPE_JAGUAR3_11N(_Adapter)	IS_HARDWARE_TYPE_8723F(_Adapter)
-+
-+#define IS_HARDWARE_TYPE_JAGUAR_ALL(_Adapter)		\
-+	(IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter) || IS_HARDWARE_TYPE_JAGUAR3(_Adapter))
-+
-+
-+typedef enum _wowlan_subcode {
-+	WOWLAN_ENABLE			= 0,
-+	WOWLAN_DISABLE			= 1,
-+	WOWLAN_AP_ENABLE		= 2,
-+	WOWLAN_AP_DISABLE		= 3,
-+	WOWLAN_PATTERN_CLEAN		= 4
-+} wowlan_subcode;
-+
-+struct wowlan_ioctl_param {
-+	unsigned int subcode;
-+	unsigned int subcode_value;
-+	unsigned int wakeup_reason;
-+};
-+
-+u8 rtw_hal_data_init(_adapter *padapter);
-+void rtw_hal_data_deinit(_adapter *padapter);
-+
-+void rtw_hal_def_value_init(_adapter *padapter);
-+
-+void	rtw_hal_free_data(_adapter *padapter);
-+
-+void rtw_hal_dm_init(_adapter *padapter);
-+void rtw_hal_dm_deinit(_adapter *padapter);
-+#ifdef CONFIG_RTW_SW_LED
-+void rtw_hal_sw_led_init(_adapter *padapter);
-+void rtw_hal_sw_led_deinit(_adapter *padapter);
-+#endif
-+u32 rtw_hal_power_on(_adapter *padapter);
-+void rtw_hal_power_off(_adapter *padapter);
-+
-+uint rtw_hal_init(_adapter *padapter);
-+#ifdef CONFIG_NEW_NETDEV_HDL
-+uint rtw_hal_iface_init(_adapter *adapter);
-+#endif
-+
-+enum rf_type rtw_chip_rftype_to_hal_rftype(_adapter *adapter, u8 limit);
-+void dump_hal_runtime_trx_mode(void *sel, _adapter *adapter);
-+void dump_hal_trx_mode(void *sel, _adapter *adapter);
-+u8 rtw_hal_rfpath_init(_adapter *adapter);
-+u8 rtw_hal_trxnss_init(_adapter *adapter);
-+
-+uint rtw_hal_deinit(_adapter *padapter);
-+void rtw_hal_stop(_adapter *padapter);
-+u8 rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val);
-+void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val);
-+
-+void rtw_hal_chip_configure(_adapter *padapter);
-+u8 rtw_hal_read_chip_info(_adapter *padapter);
-+void rtw_hal_read_chip_version(_adapter *padapter);
-+
-+u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
-+u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
-+
-+void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet);
-+void	rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);
-+
-+void rtw_hal_enable_interrupt(_adapter *padapter);
-+void rtw_hal_disable_interrupt(_adapter *padapter);
-+
-+u8 rtw_hal_check_ips_status(_adapter *padapter);
-+
-+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
-+	u32	rtw_hal_inirp_init(_adapter *padapter);
-+	u32	rtw_hal_inirp_deinit(_adapter *padapter);
-+#endif
-+
-+#if defined(CONFIG_PCI_HCI)
-+	void	rtw_hal_irp_reset(_adapter *padapter);
-+void	rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data);
-+u8	rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr);
-+void	rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data);
-+u16	rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr);
-+u8	rtw_hal_pci_l1off_nic_support(_adapter *padapter);
-+u8	rtw_hal_pci_l1off_capability(_adapter *padapter);
-+#endif
-+
-+u8	rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+s32	rtw_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+s32	rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+s32	rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
-+s32	rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
-+
-+s32	rtw_hal_init_xmit_priv(_adapter *padapter);
-+void	rtw_hal_free_xmit_priv(_adapter *padapter);
-+
-+s32	rtw_hal_init_recv_priv(_adapter *padapter);
-+void	rtw_hal_free_recv_priv(_adapter *padapter);
-+
-+void rtw_hal_update_ra_mask(struct sta_info *psta);
-+
-+void	rtw_hal_start_thread(_adapter *padapter);
-+void	rtw_hal_stop_thread(_adapter *padapter);
-+
-+void rtw_hal_bcn_related_reg_setting(_adapter *padapter);
-+
-+u32	rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask);
-+void	rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
-+u32	rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask);
-+void	rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
-+
-+
-+#define phy_query_bb_reg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask))
-+#define phy_set_bb_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (BitMask), (Data))
-+#define phy_query_rf_reg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask))
-+#define phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
-+
-+#ifdef CONFIG_SYSON_INDIRECT_ACCESS
-+u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask);
-+void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
-+#define hal_query_syson_reg(Adapter, RegAddr, BitMask) rtw_hal_read_syson_reg((Adapter), (RegAddr), (BitMask))
-+#define hal_set_syson_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_syson_reg((Adapter), (RegAddr), (BitMask), (Data))
-+#endif
-+
-+#define phy_set_mac_reg	phy_set_bb_reg
-+#define phy_query_mac_reg phy_query_bb_reg
-+
-+#if defined(CONFIG_PCI_HCI)
-+	s32	rtw_hal_interrupt_handler(_adapter *padapter);
-+	void	rtw_hal_unmap_beacon_icf(_adapter *padapter);
-+#endif
-+#if  defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
-+	void	rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf);
-+#endif
-+
-+void	rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80);
-+void	rtw_hal_dm_watchdog(_adapter *padapter);
-+void	rtw_hal_dm_watchdog_in_lps(_adapter *padapter);
-+
-+#ifdef CONFIG_HOSTAPD_MLME
-+	s32	rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
-+#endif
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+void rtw_hal_sreset_init(_adapter *padapter);
-+void rtw_hal_sreset_reset(_adapter *padapter);
-+void rtw_hal_sreset_reset_value(_adapter *padapter);
-+void rtw_hal_sreset_xmit_status_check(_adapter *padapter);
-+void rtw_hal_sreset_linked_status_check(_adapter *padapter);
-+u8   rtw_hal_sreset_get_wifi_status(_adapter *padapter);
-+bool rtw_hal_sreset_inprogress(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_IOL
-+int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
-+#endif
-+
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+s32 rtw_hal_xmit_thread_handler(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RECV_THREAD_MODE
-+s32 rtw_hal_recv_hdl(_adapter *adapter);
-+#endif
-+
-+void rtw_hal_notch_filter(_adapter *adapter, bool enable);
-+
-+#ifdef CONFIG_FW_C2H_REG
-+bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload);
-+bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf);
-+s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf);
-+#endif
-+
-+#ifdef CONFIG_FW_C2H_PKT
-+bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload);
-+#endif
-+
-+s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
-+#ifndef RTW_HALMAC
-+s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
-+s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
-+#endif
-+
-+s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter);
-+
-+s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid);
-+s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid);
-+s32 rtw_hal_macid_sleep_all_used(_adapter *adapter);
-+s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter);
-+
-+s32 rtw_hal_macid_drop(_adapter *adapter, u8 macid);
-+s32 rtw_hal_macid_undrop(_adapter *adapter, u8 macid);
-+
-+s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
-+void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,
-+			      u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
-+u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan);
-+
-+#ifdef CONFIG_GPIO_API
-+void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag);
-+int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num);
-+void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num);
-+#endif
-+#ifdef CONFIG_FW_CORRECT_BCN
-+void rtw_hal_fw_correct_bcn(_adapter *padapter);
-+#endif
-+s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan);
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+	void rtw_hal_clear_interrupt(_adapter *padapter);
-+#endif
-+
-+void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel);
-+void rtw_hal_update_txpwr_level(_adapter *adapter);
-+void rtw_hal_set_txpwr_done(_adapter *adapter);
-+void rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex
-+	, enum rf_path rfpath, u8 rate);
-+
-+u8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath
-+	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
-+	, struct txpwr_idx_comp *tic);
-+s8 rtw_hal_get_txpwr_target_extra_bias(_adapter *adapter, enum rf_path rfpath
-+	, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch);
-+
-+u8 rtw_hal_ops_check(_adapter *padapter);
-+
-+#ifdef RTW_HALMAC
-+	u8 rtw_hal_init_mac_register(PADAPTER);
-+	u8 rtw_hal_init_phy(PADAPTER);
-+s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem);
-+#endif /* RTW_HALMAC */
-+
-+#ifdef CONFIG_RFKILL_POLL
-+bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid);
-+#endif
-+
-+#endif /* __HAL_INTF_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/hal_pg.h b/drivers/staging/rtl8723cs/include/hal_pg.h
-new file mode 100644
-index 000000000000..2df6a399cd92
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_pg.h
-@@ -0,0 +1,997 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __HAL_PG_H__
-+#define __HAL_PG_H__
-+
-+#define PPG_BB_GAIN_2G_TX_OFFSET_MASK	0x0F
-+#define PPG_BB_GAIN_2G_TXB_OFFSET_MASK	0xF0
-+
-+#define PPG_BB_GAIN_5G_TX_OFFSET_MASK	0x1F
-+#define PPG_THERMAL_OFFSET_MASK			0x1F
-+#define KFREE_BB_GAIN_2G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))
-+#define KFREE_BB_GAIN_2G_TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg_v) >> 5) : (-((_ppg_v) >> 5))))
-+#define KFREE_BB_GAIN_5G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))
-+#define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))
-+
-+/* ****************************************************
-+ *			EEPROM/Efuse PG Offset for 88EE/88EU/88ES
-+ * **************************************************** */
-+#define EEPROM_ChannelPlan_88E					0xB8
-+#define EEPROM_XTAL_88E						0xB9
-+#define EEPROM_THERMAL_METER_88E				0xBA
-+#define EEPROM_IQK_LCK_88E						0xBB
-+
-+#define EEPROM_RF_BOARD_OPTION_88E			0xC1
-+#define EEPROM_RF_FEATURE_OPTION_88E			0xC2
-+#define EEPROM_RF_BT_SETTING_88E				0xC3
-+#define EEPROM_VERSION_88E						0xC4
-+#define EEPROM_CustomID_88E					0xC5
-+#define EEPROM_RF_ANTENNA_OPT_88E			0xC9
-+#define EEPROM_COUNTRY_CODE_88E				0xCB
-+
-+/* RTL88EE */
-+#define EEPROM_MAC_ADDR_88EE					0xD0
-+#define EEPROM_VID_88EE						0xD6
-+#define EEPROM_DID_88EE						0xD8
-+#define EEPROM_SVID_88EE						0xDA
-+#define EEPROM_SMID_88EE						0xDC
-+
-+/* RTL88EU */
-+#define EEPROM_MAC_ADDR_88EU					0xD7
-+#define EEPROM_VID_88EU						0xD0
-+#define EEPROM_PID_88EU						0xD2
-+#define EEPROM_USB_OPTIONAL_FUNCTION0		0xD4 /* 8188EU, 8192EU, 8812AU is the same */
-+#define EEPROM_USB_OPTIONAL_FUNCTION0_8811AU 0x104
-+
-+/* RTL88ES */
-+#define EEPROM_MAC_ADDR_88ES					0x11A
-+/* ****************************************************
-+ *			EEPROM/Efuse PG Offset for 8192EE/8192EU/8192ES
-+ * **************************************************** */
-+#define GET_PG_KFREE_ON_8192E(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
-+#define GET_PG_KFREE_THERMAL_K_ON_8192E(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
-+
-+#define PPG_BB_GAIN_2G_TXA_OFFSET_8192E	0x1F6
-+#define PPG_THERMAL_OFFSET_8192E		0x1F5
-+
-+#define	EEPROM_ChannelPlan_8192E				0xB8
-+#define	EEPROM_XTAL_8192E						0xB9
-+#define	EEPROM_THERMAL_METER_8192E			0xBA
-+#define	EEPROM_IQK_LCK_8192E					0xBB
-+#define	EEPROM_2G_5G_PA_TYPE_8192E			0xBC
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8192E	0xBD
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8192E	0xBF
-+
-+#define	EEPROM_RF_BOARD_OPTION_8192E		0xC1
-+#define	EEPROM_RF_FEATURE_OPTION_8192E		0xC2
-+#define	EEPROM_RF_BT_SETTING_8192E			0xC3
-+#define	EEPROM_VERSION_8192E					0xC4
-+#define	EEPROM_CustomID_8192E				0xC5
-+#define	EEPROM_TX_BBSWING_2G_8192E			0xC6
-+#define	EEPROM_TX_BBSWING_5G_8192E			0xC7
-+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8192E	0xC8
-+#define	EEPROM_RF_ANTENNA_OPT_8192E			0xC9
-+#define	EEPROM_RFE_OPTION_8192E				0xCA
-+#define	EEPROM_RFE_OPTION_8188E				0xCA
-+#define EEPROM_COUNTRY_CODE_8192E			0xCB
-+
-+/* RTL8192EE */
-+#define	EEPROM_MAC_ADDR_8192EE				0xD0
-+#define	EEPROM_VID_8192EE						0xD6
-+#define	EEPROM_DID_8192EE						0xD8
-+#define	EEPROM_SVID_8192EE					0xDA
-+#define	EEPROM_SMID_8192EE					0xDC
-+
-+/* RTL8192EU */
-+#define	EEPROM_MAC_ADDR_8192EU				0xD7
-+#define	EEPROM_VID_8192EU						0xD0
-+#define	EEPROM_PID_8192EU						0xD2
-+#define	EEPROM_PA_TYPE_8192EU		0xBC
-+#define	EEPROM_LNA_TYPE_2G_8192EU	0xBD
-+#define	EEPROM_LNA_TYPE_5G_8192EU	0xBF
-+
-+/* RTL8192ES */
-+#define	EEPROM_MAC_ADDR_8192ES				0x11A
-+/* ****************************************************
-+ *			EEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS
-+ * *****************************************************/
-+#define EEPROM_USB_MODE_8812					0x08
-+
-+#define EEPROM_ChannelPlan_8812				0xB8
-+#define EEPROM_XTAL_8812						0xB9
-+#define EEPROM_THERMAL_METER_8812			0xBA
-+#define EEPROM_IQK_LCK_8812					0xBB
-+#define EEPROM_2G_5G_PA_TYPE_8812			0xBC
-+#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8812	0xBD
-+#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8812	0xBF
-+
-+#define EEPROM_RF_BOARD_OPTION_8812			0xC1
-+#define EEPROM_RF_FEATURE_OPTION_8812		0xC2
-+#define EEPROM_RF_BT_SETTING_8812				0xC3
-+#define EEPROM_VERSION_8812					0xC4
-+#define EEPROM_CustomID_8812					0xC5
-+#define EEPROM_TX_BBSWING_2G_8812			0xC6
-+#define EEPROM_TX_BBSWING_5G_8812			0xC7
-+#define EEPROM_TX_PWR_CALIBRATE_RATE_8812	0xC8
-+#define EEPROM_RF_ANTENNA_OPT_8812			0xC9
-+#define EEPROM_RFE_OPTION_8812				0xCA
-+#define EEPROM_COUNTRY_CODE_8812			0xCB
-+
-+/* RTL8812AE */
-+#define EEPROM_MAC_ADDR_8812AE				0xD0
-+#define EEPROM_VID_8812AE						0xD6
-+#define EEPROM_DID_8812AE						0xD8
-+#define EEPROM_SVID_8812AE						0xDA
-+#define EEPROM_SMID_8812AE					0xDC
-+
-+/* RTL8812AU */
-+#define EEPROM_MAC_ADDR_8812AU				0xD7
-+#define EEPROM_VID_8812AU						0xD0
-+#define EEPROM_PID_8812AU						0xD2
-+#define EEPROM_PA_TYPE_8812AU					0xBC
-+#define EEPROM_LNA_TYPE_2G_8812AU			0xBD
-+#define EEPROM_LNA_TYPE_5G_8812AU			0xBF
-+
-+/* RTL8814AU */
-+#define	EEPROM_MAC_ADDR_8814AU				0xD8
-+#define	EEPROM_VID_8814AU						0xD0
-+#define	EEPROM_PID_8814AU						0xD2
-+#define	EEPROM_PA_TYPE_8814AU				0xBC
-+#define	EEPROM_LNA_TYPE_2G_8814AU			0xBD
-+#define	EEPROM_LNA_TYPE_5G_8814AU			0xBF
-+
-+/* RTL8814AE */
-+#define EEPROM_MAC_ADDR_8814AE				0xD0
-+#define EEPROM_VID_8814AE						0xD6
-+#define EEPROM_DID_8814AE						0xD8
-+#define EEPROM_SVID_8814AE						0xDA
-+#define EEPROM_SMID_8814AE					0xDC
-+
-+/* ****************************************************
-+ *			EEPROM/Efuse PG Offset for 8814AU
-+ * **************************************************** */
-+#define GET_PG_KFREE_ON_8814A(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1)
-+#define GET_PG_KFREE_THERMAL_K_ON_8814A(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
-+#define GET_PG_TX_POWER_TRACKING_MODE_8814A(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 6, 2)
-+
-+#define KFREE_GAIN_DATA_LENGTH_8814A	22
-+
-+#define PPG_BB_GAIN_2G_TXBA_OFFSET_8814A	0x3EE
-+
-+#define PPG_THERMAL_OFFSET_8814A		0x3EF
-+
-+#define EEPROM_USB_MODE_8814A				0x0E
-+#define EEPROM_ChannelPlan_8814				0xB8
-+#define EEPROM_XTAL_8814					0xB9
-+#define EEPROM_THERMAL_METER_8814			0xBA
-+#define	EEPROM_IQK_LCK_8814					0xBB
-+
-+
-+#define EEPROM_PA_TYPE_8814					0xBC
-+#define EEPROM_LNA_TYPE_AB_2G_8814			0xBD
-+#define	EEPROM_LNA_TYPE_CD_2G_8814			0xBE
-+#define EEPROM_LNA_TYPE_AB_5G_8814			0xBF
-+#define EEPROM_LNA_TYPE_CD_5G_8814			0xC0
-+#define	EEPROM_RF_BOARD_OPTION_8814			0xC1
-+#define	EEPROM_RF_BT_SETTING_8814			0xC3
-+#define	EEPROM_VERSION_8814					0xC4
-+#define	EEPROM_CustomID_8814				0xC5
-+#define	EEPROM_TX_BBSWING_2G_8814			0xC6
-+#define	EEPROM_TX_BBSWING_5G_8814			0xC7
-+#define EEPROM_TRX_ANTENNA_OPTION_8814		0xC9
-+#define	EEPROM_RFE_OPTION_8814				0xCA
-+#define EEPROM_COUNTRY_CODE_8814			0xCB
-+
-+/*Extra Info for 8814A Initial Gain Fine Tune  suggested by Willis, JIRA: MP123*/
-+#define	EEPROM_IG_OFFSET_4_AB_2G_8814A				0x120
-+#define	EEPROM_IG_OFFSET_4_CD_2G_8814A				0x121
-+#define	EEPROM_IG_OFFSET_4_AB_5GL_8814A				0x122
-+#define	EEPROM_IG_OFFSET_4_CD_5GL_8814A				0x123
-+#define	EEPROM_IG_OFFSET_4_AB_5GM_8814A				0x124
-+#define	EEPROM_IG_OFFSET_4_CD_5GM_8814A				0x125
-+#define	EEPROM_IG_OFFSET_4_AB_5GH_8814A				0x126
-+#define	EEPROM_IG_OFFSET_4_CD_5GH_8814A				0x127
-+
-+/* ****************************************************
-+ *			EEPROM/Efuse PG Offset for 8821AE/8821AU/8821AS
-+ * **************************************************** */
-+
-+#define GET_PG_KFREE_ON_8821A(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1)
-+#define GET_PG_KFREE_THERMAL_K_ON_8821A(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
-+
-+#define PPG_BB_GAIN_2G_TXA_OFFSET_8821A		0x1F6
-+#define PPG_THERMAL_OFFSET_8821A			0x1F5
-+#define PPG_BB_GAIN_5GLB1_TXA_OFFSET_8821A	0x1F4
-+#define PPG_BB_GAIN_5GLB2_TXA_OFFSET_8821A	0x1F3
-+#define PPG_BB_GAIN_5GMB1_TXA_OFFSET_8821A	0x1F2
-+#define PPG_BB_GAIN_5GMB2_TXA_OFFSET_8821A	0x1F1
-+#define PPG_BB_GAIN_5GHB_TXA_OFFSET_8821A	0x1F0
-+
-+#define EEPROM_ChannelPlan_8821				0xB8
-+#define EEPROM_XTAL_8821						0xB9
-+#define EEPROM_THERMAL_METER_8821			0xBA
-+#define EEPROM_IQK_LCK_8821					0xBB
-+
-+
-+#define EEPROM_RF_BOARD_OPTION_8821			0xC1
-+#define EEPROM_RF_FEATURE_OPTION_8821		0xC2
-+#define EEPROM_RF_BT_SETTING_8821				0xC3
-+#define EEPROM_VERSION_8821					0xC4
-+#define EEPROM_CustomID_8821					0xC5
-+#define EEPROM_RF_ANTENNA_OPT_8821			0xC9
-+
-+/* RTL8821AE */
-+#define EEPROM_MAC_ADDR_8821AE				0xD0
-+#define EEPROM_VID_8821AE						0xD6
-+#define EEPROM_DID_8821AE						0xD8
-+#define EEPROM_SVID_8821AE						0xDA
-+#define EEPROM_SMID_8821AE					0xDC
-+
-+/* RTL8821AU */
-+#define EEPROM_PA_TYPE_8821AU					0xBC
-+#define EEPROM_LNA_TYPE_8821AU				0xBF
-+
-+/* RTL8821AS */
-+#define EEPROM_MAC_ADDR_8821AS				0x11A
-+
-+/* RTL8821AU */
-+#define EEPROM_MAC_ADDR_8821AU				0x107
-+#define EEPROM_VID_8821AU						0x100
-+#define EEPROM_PID_8821AU						0x102
-+
-+
-+/* ****************************************************
-+ *			EEPROM/Efuse PG Offset for 8192 SE/SU
-+ * **************************************************** */
-+#define EEPROM_VID_92SE						0x0A
-+#define EEPROM_DID_92SE						0x0C
-+#define EEPROM_SVID_92SE						0x0E
-+#define EEPROM_SMID_92SE						0x10
-+
-+#define EEPROM_MAC_ADDR_92S					0x12
-+
-+#define EEPROM_TSSI_A_92SE						0x74
-+#define EEPROM_TSSI_B_92SE						0x75
-+
-+#define EEPROM_Version_92SE					0x7C
-+
-+
-+#define EEPROM_VID_92SU						0x08
-+#define EEPROM_PID_92SU						0x0A
-+
-+#define EEPROM_Version_92SU					0x50
-+#define EEPROM_TSSI_A_92SU						0x6b
-+#define EEPROM_TSSI_B_92SU						0x6c
-+
-+/* ====================================================
-+	EEPROM/Efuse PG Offset for 8188FE/8188FU/8188FS
-+   ====================================================
-+ */
-+
-+#define GET_PG_KFREE_ON_8188F(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
-+#define GET_PG_KFREE_THERMAL_K_ON_8188F(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
-+
-+#define PPG_BB_GAIN_2G_TXA_OFFSET_8188F	0xEE
-+#define PPG_THERMAL_OFFSET_8188F		0xEF
-+
-+#define	EEPROM_ChannelPlan_8188F			0xB8
-+#define	EEPROM_XTAL_8188F					0xB9
-+#define	EEPROM_THERMAL_METER_8188F			0xBA
-+#define	EEPROM_IQK_LCK_8188F				0xBB
-+#define	EEPROM_2G_5G_PA_TYPE_8188F			0xBC
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8188F	0xBD
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8188F	0xBF
-+
-+#define	EEPROM_RF_BOARD_OPTION_8188F		0xC1
-+#define	EEPROM_FEATURE_OPTION_8188F			0xC2
-+#define	EEPROM_RF_BT_SETTING_8188F			0xC3
-+#define	EEPROM_VERSION_8188F				0xC4
-+#define	EEPROM_CustomID_8188F				0xC5
-+#define	EEPROM_TX_BBSWING_2G_8188F			0xC6
-+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8188F	0xC8
-+#define	EEPROM_RF_ANTENNA_OPT_8188F			0xC9
-+#define	EEPROM_RFE_OPTION_8188F				0xCA
-+#define EEPROM_COUNTRY_CODE_8188F			0xCB
-+#define EEPROM_CUSTOMER_ID_8188F			0x7F
-+#define EEPROM_SUBCUSTOMER_ID_8188F			0x59
-+
-+/* RTL8188FU */
-+#define EEPROM_MAC_ADDR_8188FU				0xD7
-+#define EEPROM_VID_8188FU					0xD0
-+#define EEPROM_PID_8188FU					0xD2
-+#define EEPROM_PA_TYPE_8188FU				0xBC
-+#define EEPROM_LNA_TYPE_2G_8188FU			0xBD
-+#define EEPROM_USB_OPTIONAL_FUNCTION0_8188FU 0xD4
-+
-+/* RTL8188FS */
-+#define	EEPROM_MAC_ADDR_8188FS				0x11A
-+#define EEPROM_Voltage_ADDR_8188F			0x8
-+
-+/* ====================================================
-+	EEPROM/Efuse PG Offset for 8188GTV/8188GTVS
-+   ====================================================
-+ */
-+
-+#define GET_PG_KFREE_ON_8188GTV(_pg_m)				LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
-+#define GET_PG_KFREE_THERMAL_K_ON_8188GTV(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
-+
-+#define PPG_BB_GAIN_2G_TXA_OFFSET_8188GTV	0xEE
-+#define PPG_THERMAL_OFFSET_8188GTV			0xEF
-+
-+#define	EEPROM_ChannelPlan_8188GTV				0xB8
-+#define	EEPROM_XTAL_8188GTV						0xB9
-+#define	EEPROM_THERMAL_METER_8188GTV			0xBA
-+#define	EEPROM_IQK_LCK_8188GTV					0xBB
-+#define	EEPROM_2G_5G_PA_TYPE_8188GTV			0xBC
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8188GTV		0xBD
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8188GTV		0xBF
-+
-+#define	EEPROM_RF_BOARD_OPTION_8188GTV			0xC1
-+#define	EEPROM_FEATURE_OPTION_8188GTV			0xC2
-+#define	EEPROM_RF_BT_SETTING_8188GTV			0xC3
-+#define	EEPROM_VERSION_8188GTV					0xC4
-+#define	EEPROM_CustomID_8188GTV					0xC5
-+#define	EEPROM_TX_BBSWING_2G_8188GTV			0xC6
-+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8188GTV	0xC8
-+#define	EEPROM_RF_ANTENNA_OPT_8188GTV			0xC9
-+#define	EEPROM_RFE_OPTION_8188GTV				0xCA
-+#define EEPROM_COUNTRY_CODE_8188GTV				0xCB
-+#define EEPROM_CUSTOMER_ID_8188GTV				0x7F
-+#define EEPROM_SUBCUSTOMER_ID_8188GTV			0x59
-+
-+/* RTL8188GTVU */
-+#define EEPROM_MAC_ADDR_8188GTVU				0xD7
-+#define EEPROM_VID_8188GTVU						0xD0
-+#define EEPROM_PID_8188GTVU						0xD2
-+#define EEPROM_PA_TYPE_8188GTVU					0xBC
-+#define EEPROM_LNA_TYPE_2G_8188GTVU				0xBD
-+#define EEPROM_USB_OPTIONAL_FUNCTION0_8188GTVU	0xD4
-+
-+/* RTL8188GTVS */
-+#define	EEPROM_MAC_ADDR_8188GTVS				0x11A
-+#define EEPROM_Voltage_ADDR_8188GTV				0x8
-+
-+/* ****************************************************
-+ *			EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS
-+ * *****************************************************/
-+#define	EEPROM_ChannelPlan_8723B				0xB8
-+#define	EEPROM_XTAL_8723B						0xB9
-+#define	EEPROM_THERMAL_METER_8723B			0xBA
-+#define	EEPROM_IQK_LCK_8723B					0xBB
-+#define	EEPROM_2G_5G_PA_TYPE_8723B			0xBC
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8723B	0xBD
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8723B	0xBF
-+
-+#define	EEPROM_RF_BOARD_OPTION_8723B		0xC1
-+#define	EEPROM_FEATURE_OPTION_8723B			0xC2
-+#define	EEPROM_RF_BT_SETTING_8723B			0xC3
-+#define	EEPROM_VERSION_8723B					0xC4
-+#define	EEPROM_CustomID_8723B				0xC5
-+#define	EEPROM_TX_BBSWING_2G_8723B			0xC6
-+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8723B	0xC8
-+#define	EEPROM_RF_ANTENNA_OPT_8723B		0xC9
-+#define	EEPROM_RFE_OPTION_8723B				0xCA
-+#define EEPROM_COUNTRY_CODE_8723B			0xCB
-+
-+/* RTL8723BE */
-+#define EEPROM_MAC_ADDR_8723BE				0xD0
-+#define EEPROM_VID_8723BE						0xD6
-+#define EEPROM_DID_8723BE						0xD8
-+#define EEPROM_SVID_8723BE						0xDA
-+#define EEPROM_SMID_8723BE						0xDC
-+
-+/* RTL8723BU */
-+#define EEPROM_MAC_ADDR_8723BU				0x107
-+#define EEPROM_VID_8723BU						0x100
-+#define EEPROM_PID_8723BU						0x102
-+#define EEPROM_PA_TYPE_8723BU					0xBC
-+#define EEPROM_LNA_TYPE_2G_8723BU				0xBD
-+
-+
-+/* RTL8723BS */
-+#define	EEPROM_MAC_ADDR_8723BS				0x11A
-+#define EEPROM_Voltage_ADDR_8723B			0x8
-+
-+/* ****************************************************
-+ *			EEPROM/Efuse PG Offset for 8703B
-+ * **************************************************** */
-+#define GET_PG_KFREE_ON_8703B(_pg_m)			LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
-+#define GET_PG_KFREE_THERMAL_K_ON_8703B(_pg_m)	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
-+
-+#define PPG_BB_GAIN_2G_TXA_OFFSET_8703B	0xEE
-+#define PPG_THERMAL_OFFSET_8703B		0xEF
-+
-+#define	EEPROM_ChannelPlan_8703B				0xB8
-+#define	EEPROM_XTAL_8703B					0xB9
-+#define	EEPROM_THERMAL_METER_8703B			0xBA
-+#define	EEPROM_IQK_LCK_8703B					0xBB
-+#define	EEPROM_2G_5G_PA_TYPE_8703B			0xBC
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8703B	0xBD
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8703B	0xBF
-+
-+#define	EEPROM_RF_BOARD_OPTION_8703B		0xC1
-+#define	EEPROM_FEATURE_OPTION_8703B			0xC2
-+#define	EEPROM_RF_BT_SETTING_8703B			0xC3
-+#define	EEPROM_VERSION_8703B					0xC4
-+#define	EEPROM_CustomID_8703B					0xC5
-+#define	EEPROM_TX_BBSWING_2G_8703B			0xC6
-+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8703B	0xC8
-+#define	EEPROM_RF_ANTENNA_OPT_8703B		0xC9
-+#define	EEPROM_RFE_OPTION_8703B				0xCA
-+#define EEPROM_COUNTRY_CODE_8703B			0xCB
-+
-+/* RTL8703BU */
-+#define EEPROM_MAC_ADDR_8703BU                          0x107
-+#define EEPROM_VID_8703BU                               0x100
-+#define EEPROM_PID_8703BU                               0x102
-+#define EEPROM_USB_OPTIONAL_FUNCTION0_8703BU            0x104
-+#define EEPROM_PA_TYPE_8703BU                           0xBC
-+#define EEPROM_LNA_TYPE_2G_8703BU                       0xBD
-+
-+/* RTL8703BS */
-+#define	EEPROM_MAC_ADDR_8703BS				0x11A
-+#define	EEPROM_Voltage_ADDR_8703B			0x8
-+
-+/*
-+ * ====================================================
-+ *	EEPROM/Efuse PG Offset for 8822B
-+ * ====================================================
-+ */
-+#define	EEPROM_ChannelPlan_8822B		0xB8
-+#define	EEPROM_XTAL_8822B			0xB9
-+#define	EEPROM_THERMAL_METER_8822B		0xBA
-+#define	EEPROM_IQK_LCK_8822B			0xBB
-+#define	EEPROM_2G_5G_PA_TYPE_8822B		0xBC
-+/* PATH A & PATH B */
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B	0xBD
-+/* PATH C & PATH D */
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8822B	0xBE
-+/* PATH A & PATH B */
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B	0xBF
-+/* PATH C & PATH D */
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8822B	0xC0
-+
-+#define	EEPROM_RF_BOARD_OPTION_8822B		0xC1
-+#define	EEPROM_FEATURE_OPTION_8822B		0xC2
-+#define	EEPROM_RF_BT_SETTING_8822B		0xC3
-+#define	EEPROM_VERSION_8822B			0xC4
-+#define	EEPROM_CustomID_8822B			0xC5
-+#define	EEPROM_TX_BBSWING_2G_8822B		0xC6
-+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8822B	0xC8
-+#define	EEPROM_RF_ANTENNA_OPT_8822B		0xC9
-+#define	EEPROM_RFE_OPTION_8822B			0xCA
-+#define EEPROM_COUNTRY_CODE_8822B		0xCB
-+
-+/* RTL8822BU */
-+#define EEPROM_MAC_ADDR_8822BU			0x107
-+#define EEPROM_VID_8822BU			0x100
-+#define EEPROM_PID_8822BU			0x102
-+#define EEPROM_USB_OPTIONAL_FUNCTION0_8822BU	0x104
-+#define EEPROM_USB_MODE_8822BU			0x06
-+
-+/* RTL8822BS */
-+#define	EEPROM_MAC_ADDR_8822BS			0x11A
-+
-+/* RTL8822BE */
-+#define	EEPROM_MAC_ADDR_8822BE			0xD0
-+/*
-+ * ====================================================
-+ *	EEPROM/Efuse PG Offset for 8821C
-+ * ====================================================
-+ */
-+#define	EEPROM_CHANNEL_PLAN_8821C		0xB8
-+#define	EEPROM_XTAL_8821C			0xB9
-+#define	EEPROM_THERMAL_METER_8821C		0xBA
-+#define	EEPROM_IQK_LCK_8821C			0xBB
-+#define	EEPROM_2G_5G_PA_TYPE_8821C		0xBC
-+/* PATH A & PATH B */
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8821C	0xBD
-+/* PATH C & PATH D */
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8821C	0xBE
-+/* PATH A & PATH B */
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8821C	0xBF
-+/* PATH C & PATH D */
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8821C	0xC0
-+
-+#define	EEPROM_RF_BOARD_OPTION_8821C		0xC1
-+#define	EEPROM_FEATURE_OPTION_8821C		0xC2
-+#define	EEPROM_RF_BT_SETTING_8821C		0xC3
-+#define	EEPROM_VERSION_8821C			0xC4
-+#define	EEPROM_CUSTOMER_ID_8821C			0xC5
-+#define	EEPROM_TX_BBSWING_2G_8821C		0xC6
-+#define	EEPROM_TX_BBSWING_5G_8821C		0xC7
-+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8821C	0xC8
-+#define	EEPROM_RF_ANTENNA_OPT_8821C		0xC9
-+#define	EEPROM_RFE_OPTION_8821C			0xCA
-+#define EEPROM_COUNTRY_CODE_8821C		0xCB
-+
-+/* RTL8821CU */
-+#define EEPROM_MAC_ADDR_8821CU			0x107
-+#define EEPROM_VID_8821CU					0x100
-+#define EEPROM_PID_8821CU					0x102
-+#define EEPROM_USB_OPTIONAL_FUNCTION0_8821CU	0x104
-+#define EEPROM_USB_MODE_8821CU			0x06
-+
-+/* RTL8821CS */
-+#define	EEPROM_MAC_ADDR_8821CS			0x11A
-+
-+/* RTL8821CE */
-+#define	EEPROM_MAC_ADDR_8821CE			0xD0
-+/* ****************************************************
-+ *	EEPROM/Efuse PG Offset for 8723D
-+ * **************************************************** */
-+#define GET_PG_KFREE_ON_8723D(_pg_m)	\
-+	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
-+#define GET_PG_KFREE_THERMAL_K_ON_8723D(_pg_m)	\
-+	LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
-+
-+#define PPG_8723D_S1	0
-+#define PPG_8723D_S0	1
-+
-+#define PPG_BB_GAIN_2G_TXA_OFFSET_8723D		0xEE
-+#define PPG_BB_GAIN_2G_TX_OFFSET_8723D		0x1EE
-+#define PPG_THERMAL_OFFSET_8723D		0xEF
-+
-+#define	EEPROM_ChannelPlan_8723D		0xB8
-+#define	EEPROM_XTAL_8723D			0xB9
-+#define	EEPROM_THERMAL_METER_8723D		0xBA
-+#define	EEPROM_IQK_LCK_8723D			0xBB
-+#define	EEPROM_2G_5G_PA_TYPE_8723D		0xBC
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8723D	0xBD
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8723D	0xBF
-+
-+#define	EEPROM_RF_BOARD_OPTION_8723D		0xC1
-+#define	EEPROM_FEATURE_OPTION_8723D		0xC2
-+#define	EEPROM_RF_BT_SETTING_8723D		0xC3
-+#define	EEPROM_VERSION_8723D			0xC4
-+#define	EEPROM_CustomID_8723D			0xC5
-+#define	EEPROM_TX_BBSWING_2G_8723D		0xC6
-+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8723D	0xC8
-+#define	EEPROM_RF_ANTENNA_OPT_8723D		0xC9
-+#define	EEPROM_RFE_OPTION_8723D			0xCA
-+#define EEPROM_COUNTRY_CODE_8723D		0xCB
-+
-+/* RTL8723DE */
-+#define EEPROM_MAC_ADDR_8723DE              0xD0
-+#define EEPROM_VID_8723DE                   0xD6
-+#define EEPROM_DID_8723DE                   0xD8
-+#define EEPROM_SVID_8723DE                  0xDA
-+#define EEPROM_SMID_8723DE                  0xDC
-+
-+/* RTL8723DU */
-+#define EEPROM_MAC_ADDR_8723DU                  0x107
-+#define EEPROM_VID_8723DU                       0x100
-+#define EEPROM_PID_8723DU                       0x102
-+#define EEPROM_USB_OPTIONAL_FUNCTION0_8723DU    0x104
-+
-+/* RTL8723BS */
-+#define	EEPROM_MAC_ADDR_8723DS			0x11A
-+#define	EEPROM_Voltage_ADDR_8723D		0x8
-+
-+/*
-+ * ====================================================
-+ *	EEPROM/Efuse PG Offset for 8822C
-+ * ====================================================
-+ */
-+#define	EEPROM_TX_PWR_INX_8822C			0x10
-+#define	EEPROM_ChannelPlan_8822C		0xB8
-+#define	EEPROM_XTAL_B9_8822C			0xB9
-+#define	EEPROM_IQK_LCK_8822C			0xBB
-+#define	EEPROM_2G_5G_PA_TYPE_8822C		0xBC
-+/* PATH A & PATH B */
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C	0xBD
-+/* PATH C & PATH D */
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8822C	0xBE
-+/* PATH A & PATH B */
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C	0xBF
-+/* PATH C & PATH D */
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8822C	0xC0
-+
-+#define	EEPROM_RF_BOARD_OPTION_8822C		0xC1
-+#define	EEPROM_FEATURE_OPTION_8822C		0xC2
-+#define	EEPROM_RF_BT_SETTING_8822C		0xC3
-+#define	EEPROM_VERSION_8822C			0xC4
-+#define	EEPROM_CustomID_8822C			0xC5
-+#define	EEPROM_TX_BBSWING_2G_8822C		0xC6
-+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8822C	0xC8
-+#define	EEPROM_RF_ANTENNA_OPT_8822C		0xC9
-+#define	EEPROM_RFE_OPTION_8822C			0xCA
-+#define EEPROM_COUNTRY_CODE_8822C		0xCB
-+#define	EEPROM_THERMAL_METER_A_8822C		0xD0
-+#define	EEPROM_THERMAL_METER_B_8822C		0xD1
-+
-+#define	EEPROM_XTAL_110_8822C			0x110
-+#define	EEPROM_XTAL_111_8822C			0x111
-+
-+/* RTL8822CU */
-+#define EEPROM_MAC_ADDR_8822CU			0x157
-+#define EEPROM_VID_8822CU			0x100
-+#define EEPROM_PID_8822CU			0x102
-+#define EEPROM_USB_OPTIONAL_FUNCTION0_8822CU	0x104
-+#define EEPROM_USB_MODE_8822CU			0x06
-+
-+/* RTL8822CS */
-+#define	EEPROM_MAC_ADDR_8822CS			0x16A
-+
-+/* RTL8822CE */
-+#define	EEPROM_MAC_ADDR_8822CE			0x120
-+
-+/* ****************************************************
-+ *	EEPROM/Efuse PG Offset for 8192F
-+ * **************************************************** */
-+#define	EEPROM_ChannelPlan_8192F			0xB8
-+#define	EEPROM_XTAL_8192F					0xB9
-+#define	EEPROM_THERMAL_METER_8192F			0xBA
-+#define	EEPROM_IQK_LCK_8192F				0xBB
-+#define	EEPROM_2G_5G_PA_TYPE_8192F			0xBC
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8192F	0xBD
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8192F	0xBF
-+
-+#define	EEPROM_RF_BOARD_OPTION_8192F		0xC1
-+#define	EEPROM_FEATURE_OPTION_8192F			0xC2
-+#define	EEPROM_RF_BT_SETTING_8192F			0xC3
-+#define	EEPROM_VERSION_8192F				0xC4
-+#define	EEPROM_CustomID_8192F				0xC5
-+#define	EEPROM_TX_BBSWING_2G_8192F			0xC6
-+#define	EEPROM_TX_BBSWING_5G_8192F			0xC7
-+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8192F	0xC8
-+#define	EEPROM_RF_ANTENNA_OPT_8192F			0xC9
-+#define	EEPROM_RFE_OPTION_8192F				0xCA
-+#define EEPROM_COUNTRY_CODE_8192F			0xCB
-+/*RTL8192FS*/
-+#define	EEPROM_MAC_ADDR_8192FS				0x11A
-+#define EEPROM_Voltage_ADDR_8192F			0x8
-+/* RTL8192FU */
-+#define EEPROM_MAC_ADDR_8192FU					0x107
-+#define EEPROM_VID_8192FU							0x100
-+#define EEPROM_PID_8192FU							0x102
-+#define EEPROM_USB_OPTIONAL_FUNCTION0_8192FU	0x104
-+/* RTL8192FE */
-+#define EEPROM_MAC_ADDR_8192FE					0xD0
-+#define EEPROM_VID_8192FE							0xD6
-+#define EEPROM_DID_8192FE							0xD8
-+#define EEPROM_SVID_8192FE							0xDA
-+#define EEPROM_SMID_8192FE						0xDC
-+
-+/* ****************************************************
-+ *	EEPROM/Efuse PG Offset for 8710B
-+ * **************************************************** */
-+#define RTL_EEPROM_ID_8710B 					0x8195
-+#define EEPROM_Default_ThermalMeter_8710B		0x1A
-+
-+#define	EEPROM_CHANNEL_PLAN_8710B			0xC8
-+#define	EEPROM_XTAL_8710B					0xC9
-+#define	EEPROM_THERMAL_METER_8710B			0xCA
-+#define	EEPROM_IQK_LCK_8710B					0xCB
-+#define	EEPROM_2G_5G_PA_TYPE_8710B			0xCC
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_8710B	0xCD
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_8710B	0xCF
-+#define 	EEPROM_TX_KFREE_8710B				0xEE    //Physical  Efuse Address
-+#define 	EEPROM_THERMAL_8710B				0xEF    //Physical  Efuse Address
-+#define 	EEPROM_PACKAGE_TYPE_8710B			0xF8    //Physical  Efuse Address
-+
-+#define EEPROM_RF_BOARD_OPTION_8710B		0x131
-+#define EEPROM_RF_FEATURE_OPTION_8710B		0x132
-+#define EEPROM_RF_BT_SETTING_8710B			0x133
-+#define EEPROM_VERSION_8710B					0x134
-+#define EEPROM_CUSTOM_ID_8710B				0x135
-+#define EEPROM_TX_BBSWING_2G_8710B			0x136
-+#define EEPROM_TX_BBSWING_5G_8710B			0x137
-+#define EEPROM_TX_PWR_CALIBRATE_RATE_8710B	0x138
-+#define EEPROM_RF_ANTENNA_OPT_8710B			0x139
-+#define EEPROM_RFE_OPTION_8710B				0x13A
-+#define EEPROM_COUNTRY_CODE_8710B			0x13B
-+#define EEPROM_COUNTRY_CODE_2_8710B			0x13C
-+
-+#define EEPROM_MAC_ADDR_8710B 				0x11A
-+#define EEPROM_VID_8710BU						0x1C0
-+#define EEPROM_PID_8710BU						0x1C2
-+
-+/* ****************************************************
-+ *	EEPROM/Efuse PG Offset for 8814B
-+ * **************************************************** */
-+
-+#define	EEPROM_USB_MODE_8814BU			0x06
-+/* 0x10 ~ 0x63 = TX power area. */
-+#define	EEPROM_TX_PWR_INX_8814B			0x10
-+#define	EEPROM_ChannelPlan_8814B		0xB8
-+#define	EEPROM_XTAL_8814B			0xB9
-+#define	EEPROM_IQK_LCK_8814B			0xBB
-+
-+#define	EEPROM_RF_BOARD_OPTION_8814B		0xC1
-+#define	EEPROM_RF_FEATURE_OPTION_8814B		0xC2
-+#define	EEPROM_RF_BT_SETTING_8814B		0xC3
-+#define	EEPROM_VERSION_8814B			0xC4
-+#define	EEPROM_CustomID_8814B			0xC5
-+#define	EEPROM_TX_BBSWING_2G_8814B		0xC6
-+#define	EEPROM_TX_BBSWING_5G_8814B		0xC7
-+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8814B	0xC8
-+#define	EEPROM_RF_ANTENNA_OPT_8814B		0xC9
-+#define	EEPROM_RFE_OPTION_8814B			0xCA
-+#define	EEPROM_COUNTRY_CODE_8814B		0xCB
-+
-+#define	EEPROM_THERMAL_METER_A_8814B		0xD0
-+#define	EEPROM_THERMAL_METER_B_8814B		0xD1
-+#define	EEPROM_THERMAL_METER_C_8814B		0xD2
-+#define	EEPROM_THERMAL_METER_D_8814B		0xD3
-+
-+#define	EEPROM_MAC_ADDR_8814BE			0x120
-+#define	EEPROM_VID_8814B			0x126
-+#define	EEPROM_DID_8814B			0x128
-+#define	EEPROM_SVID_8814B			0x12A
-+#define	EEPROM_SMID_8814B			0x12C
-+
-+/* RTL8814BU */
-+#define EEPROM_MAC_ADDR_8814BU			0x157
-+#define EEPROM_VID_8814BU			0x150
-+#define EEPROM_PID_8814BU			0x152
-+#define EEPROM_USB_OPTIONAL_FUNCTION0_8814BU	0x154
-+
-+/*
-+ * ====================================================
-+ *	EEPROM/Efuse PG Offset for 8723F
-+ * ====================================================
-+ */
-+#define	EEPROM_TX_PWR_INX_8723F			0x10
-+#define	EEPROM_ChannelPlan_8723F		0xB8
-+#define	EEPROM_XTAL_B9_8723F			0xB9
-+#define	EEPROM_THERMAL_METER_8723F		0xBA
-+#define	EEPROM_IQK_LCK_8723F			0xBB
-+#define	EEPROM_2G_5G_PA_TYPE_8723F		0xBC
-+/* PATH A & PATH B */
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8723F	0xBD
-+/* PATH C & PATH D */
-+#define	EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8723F	0xBE
-+/* PATH A & PATH B */
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8723F	0xBF
-+/* PATH C & PATH D */
-+#define	EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8723F	0xC0
-+
-+#define	EEPROM_RF_BOARD_OPTION_8723F		0xC1
-+#define	EEPROM_FEATURE_OPTION_8723F		0xC2
-+#define	EEPROM_RF_BT_SETTING_8723F		0xC3
-+#define	EEPROM_VERSION_8723F			0xC4
-+#define	EEPROM_CustomID_8723F			0xC5
-+#define	EEPROM_TX_BBSWING_2G_8723F		0xC6
-+#define	EEPROM_TX_PWR_CALIBRATE_RATE_8723F	0xC8
-+#define	EEPROM_RF_ANTENNA_OPT_8723F		0xC9
-+#define	EEPROM_RFE_OPTION_8723F			0xCA
-+#define 	EEPROM_COUNTRY_CODE_8723F		0xCB
-+
-+/* RTL8723FU */
-+#define EEPROM_MAC_ADDR_8723FU			0x108
-+#define EEPROM_VID_8723FU			0x100
-+#define EEPROM_PID_8723FU			0x102
-+#define EEPROM_USB_OPTIONAL_FUNCTION0_8723FU	0x104
-+#define EEPROM_USB_MODE_8723FU			0x03
-+
-+/* RTL8723FS */
-+#define	EEPROM_MAC_ADDR_8723FS			0x11A
-+
-+/* ****************************************************
-+ *			EEPROM/Efuse Value Type
-+ * **************************************************** */
-+#define EETYPE_TX_PWR							0x0
-+#define EETYPE_MAX_RFE_8192F					0x31
-+/* ****************************************************
-+ *			EEPROM/Efuse Default Value
-+ * **************************************************** */
-+#define EEPROM_CID_DEFAULT					0x0
-+#define EEPROM_CID_DEFAULT_EXT				0xFF /* Reserved for Realtek */
-+#define EEPROM_CID_TOSHIBA						0x4
-+#define EEPROM_CID_CCX							0x10
-+#define EEPROM_CID_QMI							0x0D
-+#define EEPROM_CID_WHQL						0xFE
-+
-+#define EEPROM_CHANNEL_PLAN_FCC				0x0
-+#define EEPROM_CHANNEL_PLAN_IC				0x1
-+#define EEPROM_CHANNEL_PLAN_ETSI				0x2
-+#define EEPROM_CHANNEL_PLAN_SPAIN			0x3
-+#define EEPROM_CHANNEL_PLAN_FRANCE			0x4
-+#define EEPROM_CHANNEL_PLAN_MKK				0x5
-+#define EEPROM_CHANNEL_PLAN_MKK1				0x6
-+#define EEPROM_CHANNEL_PLAN_ISRAEL			0x7
-+#define EEPROM_CHANNEL_PLAN_TELEC			0x8
-+#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN	0x9
-+#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13	0xA
-+#define EEPROM_CHANNEL_PLAN_NCC_TAIWAN		0xB
-+#define EEPROM_CHANNEL_PLAN_CHIAN			0XC
-+#define EEPROM_CHANNEL_PLAN_SINGAPORE_INDIA_MEXICO  0XD
-+#define EEPROM_CHANNEL_PLAN_KOREA			0xE
-+#define EEPROM_CHANNEL_PLAN_TURKEY	0xF
-+#define EEPROM_CHANNEL_PLAN_JAPAN	0x10
-+#define EEPROM_CHANNEL_PLAN_FCC_NO_DFS		0x11
-+#define EEPROM_CHANNEL_PLAN_JAPAN_NO_DFS	0x12
-+#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_5G	0x13
-+#define EEPROM_CHANNEL_PLAN_TAIWAN_NO_DFS	0x14
-+
-+#define EEPROM_USB_OPTIONAL1					0xE
-+#define EEPROM_CHANNEL_PLAN_BY_HW_MASK		0x80
-+
-+#define RTL_EEPROM_ID							0x8129
-+#define EEPROM_Default_TSSI						0x0
-+#define EEPROM_Default_BoardType				0x02
-+#define EEPROM_Default_ThermalMeter			0x12
-+#define EEPROM_Default_ThermalMeter_92SU		0x7
-+#define EEPROM_Default_ThermalMeter_88E		0x18
-+#define EEPROM_Default_ThermalMeter_8812		0x18
-+#define	EEPROM_Default_ThermalMeter_8192E			0x1A
-+#define	EEPROM_Default_ThermalMeter_8723B		0x18
-+#define	EEPROM_Default_ThermalMeter_8703B		0x18
-+#define	EEPROM_Default_ThermalMeter_8723D		0x18
-+#define	EEPROM_Default_ThermalMeter_8188F		0x18
-+#define	EEPROM_Default_ThermalMeter_8188GTV		0x18
-+#define EEPROM_Default_ThermalMeter_8814A		0x18
-+#define	EEPROM_Default_ThermalMeter_8192F		0x1A
-+#define EEPROM_Default_ThermalMeter_8814B		0x20
-+
-+#define EEPROM_Default_CrystalCap				0x0
-+#define EEPROM_Default_CrystalCap_8723A		0x20
-+#define EEPROM_Default_CrystalCap_88E			0x20
-+#define EEPROM_Default_CrystalCap_8812			0x20
-+#define EEPROM_Default_CrystalCap_8814			0x20
-+#define EEPROM_Default_CrystalCap_8192E			0x20
-+#define EEPROM_Default_CrystalCap_8723B			0x20
-+#define EEPROM_Default_CrystalCap_8703B			0x20
-+#define EEPROM_Default_CrystalCap_8723D			0x20
-+#define EEPROM_Default_CrystalCap_8723F			0x3F
-+#define EEPROM_Default_CrystalCap_8188F			0x20
-+#define EEPROM_Default_CrystalCap_8188GTV		0x20
-+#define EEPROM_Default_CrystalCap_8192F			0x20
-+#define EEPROM_Default_CrystalCap_B9_8822C		0x3F
-+#define EEPROM_Default_CrystalCap_110_8822C		0x40
-+#define EEPROM_Default_CrystalCap_111_8822C		0x40
-+#define EEPROM_Default_CrystalCap_8814B			0x40
-+#define EEPROM_Default_CrystalFreq				0x0
-+#define EEPROM_Default_TxPowerLevel_92C		0x22
-+#define EEPROM_Default_TxPowerLevel_2G			0x2C
-+#define EEPROM_Default_TxPowerLevel_5G			0x22
-+#define EEPROM_Default_TxPowerLevel			0x22
-+#define EEPROM_Default_HT40_2SDiff				0x0
-+#define EEPROM_Default_HT20_Diff				2
-+#define EEPROM_Default_LegacyHTTxPowerDiff		0x3
-+#define EEPROM_Default_LegacyHTTxPowerDiff_92C	0x3
-+#define EEPROM_Default_LegacyHTTxPowerDiff_92D	0x4
-+#define EEPROM_Default_HT40_PwrMaxOffset		0
-+#define EEPROM_Default_HT20_PwrMaxOffset		0
-+
-+#define EEPROM_Default_PID						0x1234
-+#define EEPROM_Default_VID						0x5678
-+#define EEPROM_Default_CustomerID				0xAB
-+#define EEPROM_Default_CustomerID_8188E		0x00
-+#define EEPROM_Default_SubCustomerID			0xCD
-+#define EEPROM_Default_Version					0
-+
-+#define EEPROM_Default_externalPA_C9		0x00
-+#define EEPROM_Default_externalPA_CC		0xFF
-+#define EEPROM_Default_internalPA_SP3T_C9	0xAA
-+#define EEPROM_Default_internalPA_SP3T_CC	0xAF
-+#define EEPROM_Default_internalPA_SPDT_C9	0xAA
-+#ifdef CONFIG_PCI_HCI
-+	#define EEPROM_Default_internalPA_SPDT_CC	0xA0
-+#else
-+	#define EEPROM_Default_internalPA_SPDT_CC	0xFA
-+#endif
-+#define EEPROM_Default_PAType						0
-+#define EEPROM_Default_LNAType						0
-+
-+/* New EFUSE default value */
-+#define EEPROM_DEFAULT_CHANNEL_PLAN		0x7F
-+#define EEPROM_DEFAULT_BOARD_OPTION		0x00
-+#define EEPROM_DEFAULT_RFE_OPTION_8192E 0xFF
-+#define EEPROM_DEFAULT_RFE_OPTION_8188E 0xFF
-+#define EEPROM_DEFAULT_RFE_OPTION		0x04
-+#define EEPROM_DEFAULT_FEATURE_OPTION	0x00
-+#define EEPROM_DEFAULT_BT_OPTION			0x10
-+
-+
-+#define EEPROM_DEFAULT_TX_CALIBRATE_RATE	0x00
-+
-+/* PCIe related */
-+#define	EEPROM_PCIE_DEV_CAP_01				0xE0 /* Express device capability in PCIe configuration space, i.e., map to offset 0x74 */
-+#define	EEPROM_PCIE_DEV_CAP_02				0xE1 /* Express device capability in PCIe configuration space, i.e., map to offset 0x75 */
-+
-+
-+/*
-+ * For VHT series TX power by rate table.
-+ * VHT TX power by rate off setArray =
-+ * Band:-2G&5G = 0 / 1
-+ * RF: at most 4*4 = ABCD=0/1/2/3
-+ * CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
-+ *   */
-+#define TX_PWR_BY_RATE_NUM_BAND			2
-+#define TX_PWR_BY_RATE_NUM_RF			4
-+#define TX_PWR_BY_RATE_NUM_RATE			84
-+
-+#define TXPWR_LMT_MAX_RF				4
-+
-+/* ----------------------------------------------------------------------------
-+ * EEPROM/EFUSE data structure definition.
-+ * ---------------------------------------------------------------------------- */
-+
-+/* For 88E new structure */
-+
-+/*
-+2.4G:
-+{
-+{1,2},
-+{3,4,5},
-+{6,7,8},
-+{9,10,11},
-+{12,13},
-+{14}
-+}
-+
-+5G:
-+{
-+{36,38,40},
-+{44,46,48},
-+{52,54,56},
-+{60,62,64},
-+{100,102,104},
-+{108,110,112},
-+{116,118,120},
-+{124,126,128},
-+{132,134,136},
-+{140,142,144},
-+{149,151,153},
-+{157,159,161},
-+{173,175,177},
-+}
-+*/
-+#define	MAX_RF_PATH				4
-+#define RF_PATH_MAX				MAX_RF_PATH
-+#define	MAX_CHNL_GROUP_24G		6
-+#define	MAX_CHNL_GROUP_5G		14
-+
-+/* It must always set to 4, otherwise read efuse table sequence will be wrong. */
-+#define	MAX_TX_COUNT				4
-+
-+typedef	enum _BT_Ant_NUM {
-+	Ant_x2	= 0,
-+	Ant_x1	= 1
-+} BT_Ant_NUM, *PBT_Ant_NUM;
-+
-+typedef	enum _BT_CoType {
-+	BT_2WIRE		= 0,
-+	BT_ISSC_3WIRE	= 1,
-+	BT_ACCEL		= 2,
-+	BT_CSR_BC4		= 3,
-+	BT_CSR_BC8		= 4,
-+	BT_RTL8756		= 5,
-+	BT_RTL8723A		= 6,
-+	BT_RTL8821		= 7,
-+	BT_RTL8723B		= 8,
-+	BT_RTL8192E		= 9,
-+	BT_RTL8814A		= 10,
-+	BT_RTL8812A		= 11,
-+	BT_RTL8703B		= 12,
-+	BT_RTL8822B		= 13,
-+	BT_RTL8723D		= 14,
-+	BT_RTL8821C		= 15,
-+	BT_RTL8192F		= 16,
-+	BT_RTL8822C		= 17,
-+	BT_RTL8814B		= 18,
-+	BT_RTL8723F		= 19,
-+} BT_CoType, *PBT_CoType;
-+
-+typedef	enum _BT_RadioShared {
-+	BT_Radio_Shared	= 0,
-+	BT_Radio_Individual	= 1,
-+} BT_RadioShared, *PBT_RadioShared;
-+
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/hal_phy.h b/drivers/staging/rtl8723cs/include/hal_phy.h
-new file mode 100644
-index 000000000000..35f901a4968d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_phy.h
-@@ -0,0 +1,234 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_PHY_H__
-+#define __HAL_PHY_H__
-+
-+
-+#if DISABLE_BB_RF
-+	#define	HAL_FW_ENABLE				0
-+	#define	HAL_MAC_ENABLE			0
-+	#define	HAL_BB_ENABLE				0
-+	#define	HAL_RF_ENABLE				0
-+#else /* FPGA_PHY and ASIC */
-+	#define	HAL_FW_ENABLE				1
-+	#define	HAL_MAC_ENABLE			1
-+	#define	HAL_BB_ENABLE				1
-+	#define	HAL_RF_ENABLE				1
-+#endif
-+
-+#define	RF6052_MAX_TX_PWR			0x3F
-+#define	RF6052_MAX_REG_88E			0xFF
-+#define	RF6052_MAX_REG_92C			0x7F
-+
-+#define	RF6052_MAX_REG	\
-+	((RF6052_MAX_REG_88E > RF6052_MAX_REG_92C) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C)
-+
-+#define GET_RF6052_REAL_MAX_REG(_Adapter)	\
-+	(IS_HARDWARE_TYPE_8188E(_Adapter) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C)
-+
-+#define	RF6052_MAX_PATH				2
-+
-+/*
-+ * Antenna detection method, i.e., using single tone detection or RSSI reported from each antenna detected.
-+ * Added by Roger, 2013.05.22.
-+ *   */
-+#define ANT_DETECT_BY_SINGLE_TONE	BIT0
-+#define ANT_DETECT_BY_RSSI				BIT1
-+#define IS_ANT_DETECT_SUPPORT_SINGLE_TONE(__Adapter)		((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_SINGLE_TONE)
-+#define IS_ANT_DETECT_SUPPORT_RSSI(__Adapter)		((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_RSSI)
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+typedef	enum _RF_CHIP {
-+	RF_CHIP_MIN = 0,	/* 0 */
-+	RF_8225 = 1,			/* 1 11b/g RF for verification only */
-+	RF_8256 = 2,			/* 2 11b/g/n */
-+	RF_8258 = 3,			/* 3 11a/b/g/n RF */
-+	RF_6052 = 4,			/* 4 11b/g/n RF */
-+	RF_PSEUDO_11N = 5,	/* 5, It is a temporality RF. */
-+	RF_CHIP_MAX
-+} RF_CHIP_E, *PRF_CHIP_E;
-+
-+typedef enum _ANTENNA_PATH {
-+	ANTENNA_NONE	= 0,
-+	ANTENNA_D		= 1,
-+	ANTENNA_C		= 2,
-+	ANTENNA_CD	= 3,
-+	ANTENNA_B		= 4,
-+	ANTENNA_BD	= 5,
-+	ANTENNA_BC	= 6,
-+	ANTENNA_BCD	= 7,
-+	ANTENNA_A		= 8,
-+	ANTENNA_AD	= 9,
-+	ANTENNA_AC	= 10,
-+	ANTENNA_ACD	= 11,
-+	ANTENNA_AB	= 12,
-+	ANTENNA_ABD	= 13,
-+	ANTENNA_ABC	= 14,
-+	ANTENNA_ABCD	= 15
-+} ANTENNA_PATH;
-+
-+typedef enum _RF_CONTENT {
-+	radioa_txt = 0x1000,
-+	radiob_txt = 0x1001,
-+	radioc_txt = 0x1002,
-+	radiod_txt = 0x1003
-+} RF_CONTENT;
-+
-+typedef enum _BaseBand_Config_Type {
-+	BaseBand_Config_PHY_REG = 0,			/* Radio Path A */
-+	BaseBand_Config_AGC_TAB = 1,			/* Radio Path B */
-+	BaseBand_Config_AGC_TAB_2G = 2,
-+	BaseBand_Config_AGC_TAB_5G = 3,
-+	BaseBand_Config_PHY_REG_PG
-+} BaseBand_Config_Type, *PBaseBand_Config_Type;
-+
-+typedef enum _HW_BLOCK {
-+	HW_BLOCK_MAC = 0,
-+	HW_BLOCK_PHY0 = 1,
-+	HW_BLOCK_PHY1 = 2,
-+	HW_BLOCK_RF = 3,
-+	HW_BLOCK_MAXIMUM = 4, /* Never use this */
-+} HW_BLOCK_E, *PHW_BLOCK_E;
-+
-+typedef enum _WIRELESS_MODE {
-+	WIRELESS_MODE_UNKNOWN = 0x00,
-+	WIRELESS_MODE_A = 0x01,
-+	WIRELESS_MODE_B = 0x02,
-+	WIRELESS_MODE_G = 0x04,
-+	WIRELESS_MODE_AUTO = 0x08,
-+	WIRELESS_MODE_N_24G = 0x10,
-+	WIRELESS_MODE_N_5G = 0x20,
-+	WIRELESS_MODE_AC_5G = 0x40,
-+	WIRELESS_MODE_AC_24G  = 0x80,
-+	WIRELESS_MODE_AC_ONLY  = 0x100,
-+} WIRELESS_MODE;
-+
-+typedef enum _SwChnlCmdID {
-+	CmdID_End,
-+	CmdID_SetTxPowerLevel,
-+	CmdID_BBRegWrite10,
-+	CmdID_WritePortUlong,
-+	CmdID_WritePortUshort,
-+	CmdID_WritePortUchar,
-+	CmdID_RF_WriteReg,
-+} SwChnlCmdID;
-+
-+typedef struct _SwChnlCmd {
-+	SwChnlCmdID	CmdID;
-+	u32				Para1;
-+	u32				Para2;
-+	u32				msDelay;
-+} SwChnlCmd;
-+
-+typedef struct _R_ANTENNA_SELECT_OFDM {
-+	u32			r_tx_antenna:4;
-+	u32			r_ant_l:4;
-+	u32			r_ant_non_ht:4;
-+	u32			r_ant_ht1:4;
-+	u32			r_ant_ht2:4;
-+	u32			r_ant_ht_s1:4;
-+	u32			r_ant_non_ht_s1:4;
-+	u32			OFDM_TXSC:2;
-+	u32			Reserved:2;
-+} R_ANTENNA_SELECT_OFDM;
-+
-+typedef struct _R_ANTENNA_SELECT_CCK {
-+	u8			r_cckrx_enable_2:2;
-+	u8			r_cckrx_enable:2;
-+	u8			r_ccktx_enable:4;
-+} R_ANTENNA_SELECT_CCK;
-+
-+
-+/*--------------------------Exported Function prototype---------------------*/
-+u32
-+PHY_CalculateBitShift(
-+	u32 BitMask
-+);
-+
-+#ifdef CONFIG_RF_SHADOW_RW
-+typedef struct RF_Shadow_Compare_Map {
-+	/* Shadow register value */
-+	u32		Value;
-+	/* Compare or not flag */
-+	u8		Compare;
-+	/* Record If it had ever modified unpredicted */
-+	u8		ErrorOrNot;
-+	/* Recorver Flag */
-+	u8		Recorver;
-+	/*  */
-+	u8		Driver_Write;
-+} RF_SHADOW_T;
-+
-+u32
-+PHY_RFShadowRead(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				Offset);
-+
-+void
-+PHY_RFShadowWrite(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				Offset,
-+		u32				Data);
-+
-+BOOLEAN
-+PHY_RFShadowCompare(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				Offset);
-+
-+void
-+PHY_RFShadowRecorver(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				Offset);
-+
-+void
-+PHY_RFShadowCompareAll(
-+		PADAPTER		Adapter);
-+
-+void
-+PHY_RFShadowRecorverAll(
-+		PADAPTER		Adapter);
-+
-+void
-+PHY_RFShadowCompareFlagSet(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				Offset,
-+		u8				Type);
-+
-+void
-+PHY_RFShadowRecorverFlagSet(
-+		PADAPTER		Adapter,
-+		enum rf_path		eRFPath,
-+		u32				Offset,
-+		u8				Type);
-+
-+void
-+PHY_RFShadowCompareFlagSetAll(
-+		PADAPTER		Adapter);
-+
-+void
-+PHY_RFShadowRecorverFlagSetAll(
-+		PADAPTER		Adapter);
-+
-+void
-+PHY_RFShadowRefresh(
-+		PADAPTER		Adapter);
-+#endif /*#CONFIG_RF_SHADOW_RW*/
-+#endif /* __HAL_COMMON_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/hal_phy_reg.h b/drivers/staging/rtl8723cs/include/hal_phy_reg.h
-new file mode 100644
-index 000000000000..13d77ab415ed
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_phy_reg.h
-@@ -0,0 +1,270 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_PHY_REG_H__
-+#define __HAL_PHY_REG_H__
-+
-+/* for PutRFRegsetting & GetRFRegSetting BitMask*/
-+#define		bRFRegOffsetMask	0xfffff
-+
-+/* alias for phydm coding style */
-+#define REG_OFDM_0_XA_TX_IQ_IMBALANCE	rOFDM0_XATxIQImbalance
-+#define REG_OFDM_0_ECCA_THRESHOLD		rOFDM0_ECCAThreshold
-+#define REG_FPGA0_XB_LSSI_READ_BACK		rFPGA0_XB_LSSIReadBack
-+#define REG_FPGA0_TX_GAIN_STAGE			rFPGA0_TxGainStage
-+#define REG_OFDM_0_XA_AGC_CORE1			rOFDM0_XAAGCCore1
-+#define REG_OFDM_0_XB_AGC_CORE1			rOFDM0_XBAGCCore1
-+#define REG_A_TX_SCALE_JAGUAR			rA_TxScale_Jaguar
-+#define REG_B_TX_SCALE_JAGUAR			rB_TxScale_Jaguar
-+
-+#define REG_FPGA0_XAB_RF_INTERFACE_SW	rFPGA0_XAB_RFInterfaceSW
-+#define REG_FPGA0_XAB_RF_PARAMETER	rFPGA0_XAB_RFParameter
-+#define REG_FPGA0_XA_HSSI_PARAMETER1	rFPGA0_XA_HSSIParameter1
-+#define REG_FPGA0_XA_LSSI_PARAMETER	rFPGA0_XA_LSSIParameter
-+#define REG_FPGA0_XA_RF_INTERFACE_OE	rFPGA0_XA_RFInterfaceOE
-+#define REG_FPGA0_XB_HSSI_PARAMETER1	rFPGA0_XB_HSSIParameter1
-+#define REG_FPGA0_XB_LSSI_PARAMETER	rFPGA0_XB_LSSIParameter
-+#define REG_FPGA0_XB_LSSI_READ_BACK	rFPGA0_XB_LSSIReadBack
-+#define REG_FPGA0_XB_RF_INTERFACE_OE	rFPGA0_XB_RFInterfaceOE
-+#define REG_FPGA0_XCD_RF_INTERFACE_SW	rFPGA0_XCD_RFInterfaceSW
-+#define REG_FPGA0_XCD_SWITCH_CONTROL	rFPGA0_XCD_SwitchControl
-+#define REG_FPGA1_TX_BLOCK	rFPGA1_TxBlock
-+#define REG_FPGA1_TX_INFO	rFPGA1_TxInfo
-+#define REG_IQK_AGC_CONT	rIQK_AGC_Cont
-+#define REG_IQK_AGC_PTS	rIQK_AGC_Pts
-+#define REG_IQK_AGC_RSP	rIQK_AGC_Rsp
-+#define REG_OFDM_0_AGC_RSSI_TABLE	rOFDM0_AGCRSSITable
-+#define REG_OFDM_0_ECCA_THRESHOLD	rOFDM0_ECCAThreshold
-+#define REG_OFDM_0_RX_IQ_EXT_ANTA	rOFDM0_RxIQExtAnta
-+#define REG_OFDM_0_TR_MUX_PAR	rOFDM0_TRMuxPar
-+#define REG_OFDM_0_TRX_PATH_ENABLE	rOFDM0_TRxPathEnable
-+#define REG_OFDM_0_XA_AGC_CORE1	rOFDM0_XAAGCCore1
-+#define REG_OFDM_0_XA_RX_IQ_IMBALANCE	rOFDM0_XARxIQImbalance
-+#define REG_OFDM_0_XA_TX_IQ_IMBALANCE	rOFDM0_XATxIQImbalance
-+#define REG_OFDM_0_XB_AGC_CORE1	rOFDM0_XBAGCCore1
-+#define REG_OFDM_0_XB_RX_IQ_IMBALANCE	rOFDM0_XBRxIQImbalance
-+#define REG_OFDM_0_XB_TX_IQ_IMBALANCE	rOFDM0_XBTxIQImbalance
-+#define REG_OFDM_0_XC_TX_AFE	rOFDM0_XCTxAFE
-+#define REG_OFDM_0_XD_TX_AFE	rOFDM0_XDTxAFE
-+
-+/*#define REG_A_CFO_LONG_DUMP_92E	rA_CfoLongDump_92E*/
-+#define REG_A_CFO_LONG_DUMP_JAGUAR	rA_CfoLongDump_Jaguar
-+/*#define REG_A_CFO_SHORT_DUMP_92E	rA_CfoShortDump_92E*/
-+#define REG_A_CFO_SHORT_DUMP_JAGUAR	rA_CfoShortDump_Jaguar
-+#define REG_A_RFE_PINMUX_JAGUAR	rA_RFE_Pinmux_Jaguar
-+/*#define REG_A_RSSI_DUMP_92E	rA_RSSIDump_92E*/
-+#define REG_A_RSSI_DUMP_JAGUAR	rA_RSSIDump_Jaguar
-+/*#define REG_A_RX_SNR_DUMP_92E	rA_RXsnrDump_92E*/
-+#define REG_A_RX_SNR_DUMP_JAGUAR	rA_RXsnrDump_Jaguar
-+/*#define REG_A_TX_AGC	rA_TXAGC*/
-+#define REG_A_TX_SCALE_JAGUAR	rA_TxScale_Jaguar
-+#define REG_BW_INDICATION_JAGUAR	rBWIndication_Jaguar
-+/*#define REG_B_BBSWING	rB_BBSWING*/
-+/*#define REG_B_CFO_LONG_DUMP_92E	rB_CfoLongDump_92E*/
-+#define REG_B_CFO_LONG_DUMP_JAGUAR	rB_CfoLongDump_Jaguar
-+/*#define REG_B_CFO_SHORT_DUMP_92E	rB_CfoShortDump_92E*/
-+#define REG_B_CFO_SHORT_DUMP_JAGUAR	rB_CfoShortDump_Jaguar
-+/*#define REG_B_RSSI_DUMP_92E	rB_RSSIDump_92E*/
-+#define REG_B_RSSI_DUMP_JAGUAR	rB_RSSIDump_Jaguar
-+/*#define REG_B_RX_SNR_DUMP_92E	rB_RXsnrDump_92E*/
-+#define REG_B_RX_SNR_DUMP_JAGUAR	rB_RXsnrDump_Jaguar
-+/*#define REG_B_TX_AGC	rB_TXAGC*/
-+#define REG_B_TX_SCALE_JAGUAR	rB_TxScale_Jaguar
-+#define REG_BLUE_TOOTH	rBlue_Tooth
-+#define REG_CCK_0_AFE_SETTING	rCCK0_AFESetting
-+/*#define REG_C_BBSWING	rC_BBSWING*/
-+/*#define REG_C_TX_AGC	rC_TXAGC*/
-+#define REG_C_TX_SCALE_JAGUAR2	rC_TxScale_Jaguar2
-+#define REG_CONFIG_ANT_A	rConfig_AntA
-+#define REG_CONFIG_ANT_B	rConfig_AntB
-+#define REG_CONFIG_PMPD_ANT_A	rConfig_Pmpd_AntA
-+#define REG_CONFIG_PMPD_ANT_B	rConfig_Pmpd_AntB
-+#define REG_DPDT_CONTROL	rDPDT_control
-+/*#define REG_D_BBSWING	rD_BBSWING*/
-+/*#define REG_D_TX_AGC	rD_TXAGC*/
-+#define REG_D_TX_SCALE_JAGUAR2	rD_TxScale_Jaguar2
-+#define REG_FPGA0_ANALOG_PARAMETER4	rFPGA0_AnalogParameter4
-+#define REG_FPGA0_IQK	rFPGA0_IQK
-+#define REG_FPGA0_PSD_FUNCTION	rFPGA0_PSDFunction
-+#define REG_FPGA0_PSD_REPORT	rFPGA0_PSDReport
-+#define REG_FPGA0_RFMOD	rFPGA0_RFMOD
-+#define REG_FPGA0_TX_GAIN_STAGE	rFPGA0_TxGainStage
-+#define REG_FPGA0_XAB_RF_INTERFACE_SW	rFPGA0_XAB_RFInterfaceSW
-+#define REG_FPGA0_XAB_RF_PARAMETER	rFPGA0_XAB_RFParameter
-+#define REG_FPGA0_XA_HSSI_PARAMETER1	rFPGA0_XA_HSSIParameter1
-+#define REG_FPGA0_XA_LSSI_PARAMETER	rFPGA0_XA_LSSIParameter
-+#define REG_FPGA0_XA_RF_INTERFACE_OE	rFPGA0_XA_RFInterfaceOE
-+#define REG_FPGA0_XB_HSSI_PARAMETER1	rFPGA0_XB_HSSIParameter1
-+#define REG_FPGA0_XB_LSSI_PARAMETER	rFPGA0_XB_LSSIParameter
-+#define REG_FPGA0_XB_LSSI_READ_BACK	rFPGA0_XB_LSSIReadBack
-+#define REG_FPGA0_XB_RF_INTERFACE_OE	rFPGA0_XB_RFInterfaceOE
-+#define REG_FPGA0_XCD_RF_INTERFACE_SW	rFPGA0_XCD_RFInterfaceSW
-+#define REG_FPGA0_XCD_SWITCH_CONTROL	rFPGA0_XCD_SwitchControl
-+#define REG_FPGA1_TX_BLOCK	rFPGA1_TxBlock
-+#define REG_FPGA1_TX_INFO	rFPGA1_TxInfo
-+#define REG_IQK_AGC_CONT	rIQK_AGC_Cont
-+#define REG_IQK_AGC_PTS	rIQK_AGC_Pts
-+#define REG_IQK_AGC_RSP	rIQK_AGC_Rsp
-+#define REG_OFDM_0_AGC_RSSI_TABLE	rOFDM0_AGCRSSITable
-+#define REG_OFDM_0_ECCA_THRESHOLD	rOFDM0_ECCAThreshold
-+#define REG_OFDM_0_RX_IQ_EXT_ANTA	rOFDM0_RxIQExtAnta
-+#define REG_OFDM_0_TR_MUX_PAR	rOFDM0_TRMuxPar
-+#define REG_OFDM_0_TRX_PATH_ENABLE	rOFDM0_TRxPathEnable
-+#define REG_OFDM_0_XA_AGC_CORE1	rOFDM0_XAAGCCore1
-+#define REG_OFDM_0_XA_RX_IQ_IMBALANCE	rOFDM0_XARxIQImbalance
-+#define REG_OFDM_0_XA_TX_IQ_IMBALANCE	rOFDM0_XATxIQImbalance
-+#define REG_OFDM_0_XB_AGC_CORE1	rOFDM0_XBAGCCore1
-+#define REG_OFDM_0_XB_RX_IQ_IMBALANCE	rOFDM0_XBRxIQImbalance
-+#define REG_OFDM_0_XB_TX_IQ_IMBALANCE	rOFDM0_XBTxIQImbalance
-+#define REG_OFDM_0_XC_TX_AFE	rOFDM0_XCTxAFE
-+#define REG_OFDM_0_XD_TX_AFE	rOFDM0_XDTxAFE
-+#define REG_PMPD_ANAEN	rPMPD_ANAEN
-+#define REG_PDP_ANT_A	rPdp_AntA
-+#define REG_PDP_ANT_A_4	rPdp_AntA_4
-+#define REG_PDP_ANT_B	rPdp_AntB
-+#define REG_PDP_ANT_B_4	rPdp_AntB_4
-+#define REG_PWED_TH_JAGUAR	rPwed_TH_Jaguar
-+#define REG_RX_CCK	rRx_CCK
-+#define REG_RX_IQK	rRx_IQK
-+#define REG_RX_IQK_PI_A	rRx_IQK_PI_A
-+#define REG_RX_IQK_PI_B	rRx_IQK_PI_B
-+#define REG_RX_IQK_TONE_A	rRx_IQK_Tone_A
-+#define REG_RX_IQK_TONE_B	rRx_IQK_Tone_B
-+#define REG_RX_OFDM	rRx_OFDM
-+#define REG_RX_POWER_AFTER_IQK_A_2	rRx_Power_After_IQK_A_2
-+#define REG_RX_POWER_AFTER_IQK_B_2	rRx_Power_After_IQK_B_2
-+#define REG_RX_POWER_BEFORE_IQK_A_2	rRx_Power_Before_IQK_A_2
-+#define REG_RX_POWER_BEFORE_IQK_B_2	rRx_Power_Before_IQK_B_2
-+#define REG_RX_TO_RX	rRx_TO_Rx
-+#define REG_RX_WAIT_CCA	rRx_Wait_CCA
-+#define REG_RX_WAIT_RIFS	rRx_Wait_RIFS
-+#define REG_S0_S1_PATH_SWITCH	rS0S1_PathSwitch
-+/*#define REG_S1_RXEVM_DUMP_92E	rS1_RXevmDump_92E*/
-+#define REG_S1_RXEVM_DUMP_JAGUAR	rS1_RXevmDump_Jaguar
-+/*#define REG_S2_RXEVM_DUMP_92E	rS2_RXevmDump_92E*/
-+#define REG_S2_RXEVM_DUMP_JAGUAR	rS2_RXevmDump_Jaguar
-+#define REG_SYM_WLBT_PAPE_SEL	rSYM_WLBT_PAPE_SEL
-+#define REG_SINGLE_TONE_CONT_TX_JAGUAR	rSingleTone_ContTx_Jaguar
-+#define REG_SLEEP	rSleep
-+#define REG_STANDBY	rStandby
-+#define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR	rTxAGC_A_CCK11_CCK1_JAguar
-+#define REG_TX_AGC_A_CCK_1_MCS32	rTxAGC_A_CCK1_Mcs32
-+#define REG_TX_AGC_A_MCS11_MCS8_JAGUAR	rTxAGC_A_MCS11_MCS8_JAguar
-+#define REG_TX_AGC_A_MCS15_MCS12_JAGUAR	rTxAGC_A_MCS15_MCS12_JAguar
-+#define REG_TX_AGC_A_MCS19_MCS16_JAGUAR	rTxAGC_A_MCS19_MCS16_JAguar
-+#define REG_TX_AGC_A_MCS23_MCS20_JAGUAR	rTxAGC_A_MCS23_MCS20_JAguar
-+#define REG_TX_AGC_A_MCS3_MCS0_JAGUAR	rTxAGC_A_MCS3_MCS0_JAguar
-+#define REG_TX_AGC_A_MCS7_MCS4_JAGUAR	rTxAGC_A_MCS7_MCS4_JAguar
-+#define REG_TX_AGC_A_MCS03_MCS00	rTxAGC_A_Mcs03_Mcs00
-+#define REG_TX_AGC_A_MCS07_MCS04	rTxAGC_A_Mcs07_Mcs04
-+#define REG_TX_AGC_A_MCS11_MCS08	rTxAGC_A_Mcs11_Mcs08
-+#define REG_TX_AGC_A_MCS15_MCS12	rTxAGC_A_Mcs15_Mcs12
-+#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	rTxAGC_A_Nss1Index3_Nss1Index0_JAguar
-+#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	rTxAGC_A_Nss1Index7_Nss1Index4_JAguar
-+#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	rTxAGC_A_Nss2Index1_Nss1Index8_JAguar
-+#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	rTxAGC_A_Nss2Index5_Nss2Index2_JAguar
-+#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	rTxAGC_A_Nss2Index9_Nss2Index6_JAguar
-+#define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	rTxAGC_A_Nss3Index3_Nss3Index0_JAguar
-+#define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	rTxAGC_A_Nss3Index7_Nss3Index4_JAguar
-+#define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	rTxAGC_A_Nss3Index9_Nss3Index8_JAguar
-+#define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR	rTxAGC_A_Ofdm18_Ofdm6_JAguar
-+#define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR	rTxAGC_A_Ofdm54_Ofdm24_JAguar
-+#define REG_TX_AGC_A_RATE18_06	rTxAGC_A_Rate18_06
-+#define REG_TX_AGC_A_RATE54_24	rTxAGC_A_Rate54_24
-+#define REG_TX_AGC_B_CCK_11_A_CCK_2_11	rTxAGC_B_CCK11_A_CCK2_11
-+#define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR	rTxAGC_B_CCK11_CCK1_JAguar
-+#define REG_TX_AGC_B_CCK_1_55_MCS32	rTxAGC_B_CCK1_55_Mcs32
-+#define REG_TX_AGC_B_MCS11_MCS8_JAGUAR	rTxAGC_B_MCS11_MCS8_JAguar
-+#define REG_TX_AGC_B_MCS15_MCS12_JAGUAR	rTxAGC_B_MCS15_MCS12_JAguar
-+#define REG_TX_AGC_B_MCS19_MCS16_JAGUAR	rTxAGC_B_MCS19_MCS16_JAguar
-+#define REG_TX_AGC_B_MCS23_MCS20_JAGUAR	rTxAGC_B_MCS23_MCS20_JAguar
-+#define REG_TX_AGC_B_MCS3_MCS0_JAGUAR	rTxAGC_B_MCS3_MCS0_JAguar
-+#define REG_TX_AGC_B_MCS7_MCS4_JAGUAR	rTxAGC_B_MCS7_MCS4_JAguar
-+#define REG_TX_AGC_B_MCS03_MCS00	rTxAGC_B_Mcs03_Mcs00
-+#define REG_TX_AGC_B_MCS07_MCS04	rTxAGC_B_Mcs07_Mcs04
-+#define REG_TX_AGC_B_MCS11_MCS08	rTxAGC_B_Mcs11_Mcs08
-+#define REG_TX_AGC_B_MCS15_MCS12	rTxAGC_B_Mcs15_Mcs12
-+#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	rTxAGC_B_Nss1Index3_Nss1Index0_JAguar
-+#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	rTxAGC_B_Nss1Index7_Nss1Index4_JAguar
-+#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	rTxAGC_B_Nss2Index1_Nss1Index8_JAguar
-+#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	rTxAGC_B_Nss2Index5_Nss2Index2_JAguar
-+#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	rTxAGC_B_Nss2Index9_Nss2Index6_JAguar
-+#define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	rTxAGC_B_Nss3Index3_Nss3Index0_JAguar
-+#define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	rTxAGC_B_Nss3Index7_Nss3Index4_JAguar
-+#define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	rTxAGC_B_Nss3Index9_Nss3Index8_JAguar
-+#define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR	rTxAGC_B_Ofdm18_Ofdm6_JAguar
-+#define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR	rTxAGC_B_Ofdm54_Ofdm24_JAguar
-+#define REG_TX_AGC_B_RATE18_06	rTxAGC_B_Rate18_06
-+#define REG_TX_AGC_B_RATE54_24	rTxAGC_B_Rate54_24
-+#define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR	rTxAGC_C_CCK11_CCK1_JAguar
-+#define REG_TX_AGC_C_MCS11_MCS8_JAGUAR	rTxAGC_C_MCS11_MCS8_JAguar
-+#define REG_TX_AGC_C_MCS15_MCS12_JAGUAR	rTxAGC_C_MCS15_MCS12_JAguar
-+#define REG_TX_AGC_C_MCS19_MCS16_JAGUAR	rTxAGC_C_MCS19_MCS16_JAguar
-+#define REG_TX_AGC_C_MCS23_MCS20_JAGUAR	rTxAGC_C_MCS23_MCS20_JAguar
-+#define REG_TX_AGC_C_MCS3_MCS0_JAGUAR	rTxAGC_C_MCS3_MCS0_JAguar
-+#define REG_TX_AGC_C_MCS7_MCS4_JAGUAR	rTxAGC_C_MCS7_MCS4_JAguar
-+#define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	rTxAGC_C_Nss1Index3_Nss1Index0_JAguar
-+#define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	rTxAGC_C_Nss1Index7_Nss1Index4_JAguar
-+#define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	rTxAGC_C_Nss2Index1_Nss1Index8_JAguar
-+#define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	rTxAGC_C_Nss2Index5_Nss2Index2_JAguar
-+#define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	rTxAGC_C_Nss2Index9_Nss2Index6_JAguar
-+#define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	rTxAGC_C_Nss3Index3_Nss3Index0_JAguar
-+#define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	rTxAGC_C_Nss3Index7_Nss3Index4_JAguar
-+#define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	rTxAGC_C_Nss3Index9_Nss3Index8_JAguar
-+#define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR	rTxAGC_C_Ofdm18_Ofdm6_JAguar
-+#define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR	rTxAGC_C_Ofdm54_Ofdm24_JAguar
-+#define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR	rTxAGC_D_CCK11_CCK1_JAguar
-+#define REG_TX_AGC_D_MCS11_MCS8_JAGUAR	rTxAGC_D_MCS11_MCS8_JAguar
-+#define REG_TX_AGC_D_MCS15_MCS12_JAGUAR	rTxAGC_D_MCS15_MCS12_JAguar
-+#define REG_TX_AGC_D_MCS19_MCS16_JAGUAR	rTxAGC_D_MCS19_MCS16_JAguar
-+#define REG_TX_AGC_D_MCS23_MCS20_JAGUAR	rTxAGC_D_MCS23_MCS20_JAguar
-+#define REG_TX_AGC_D_MCS3_MCS0_JAGUAR	rTxAGC_D_MCS3_MCS0_JAguar
-+#define REG_TX_AGC_D_MCS7_MCS4_JAGUAR	rTxAGC_D_MCS7_MCS4_JAguar
-+#define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR	rTxAGC_D_Nss1Index3_Nss1Index0_JAguar
-+#define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR	rTxAGC_D_Nss1Index7_Nss1Index4_JAguar
-+#define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR	rTxAGC_D_Nss2Index1_Nss1Index8_JAguar
-+#define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR	rTxAGC_D_Nss2Index5_Nss2Index2_JAguar
-+#define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR	rTxAGC_D_Nss2Index9_Nss2Index6_JAguar
-+#define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR	rTxAGC_D_Nss3Index3_Nss3Index0_JAguar
-+#define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR	rTxAGC_D_Nss3Index7_Nss3Index4_JAguar
-+#define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR	rTxAGC_D_Nss3Index9_Nss3Index8_JAguar
-+#define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR	rTxAGC_D_Ofdm18_Ofdm6_JAguar
-+#define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR	rTxAGC_D_Ofdm54_Ofdm24_JAguar
-+#define REG_TX_PATH_JAGUAR	rTxPath_Jaguar
-+#define REG_TX_CCK_BBON	rTx_CCK_BBON
-+#define REG_TX_CCK_RFON	rTx_CCK_RFON
-+#define REG_TX_IQK	rTx_IQK
-+#define REG_TX_IQK_PI_A	rTx_IQK_PI_A
-+#define REG_TX_IQK_PI_B	rTx_IQK_PI_B
-+#define REG_TX_IQK_TONE_A	rTx_IQK_Tone_A
-+#define REG_TX_IQK_TONE_B	rTx_IQK_Tone_B
-+#define REG_TX_OFDM_BBON	rTx_OFDM_BBON
-+#define REG_TX_OFDM_RFON	rTx_OFDM_RFON
-+#define REG_TX_POWER_AFTER_IQK_A	rTx_Power_After_IQK_A
-+#define REG_TX_POWER_AFTER_IQK_B	rTx_Power_After_IQK_B
-+#define REG_TX_POWER_BEFORE_IQK_A	rTx_Power_Before_IQK_A
-+#define REG_TX_POWER_BEFORE_IQK_B	rTx_Power_Before_IQK_B
-+#define REG_TX_TO_RX	rTx_To_Rx
-+#define REG_TX_TO_TX	rTx_To_Tx
-+#define REG_APK	rAPK
-+#define REG_ANTSEL_SW_JAGUAR	r_ANTSEL_SW_Jaguar
-+
-+#define rf_welut_jaguar	RF_WeLut_Jaguar
-+#define rf_mode_table_addr	RF_ModeTableAddr
-+#define rf_mode_table_data0	RF_ModeTableData0
-+#define rf_mode_table_data1	RF_ModeTableData1
-+
-+#define RX_SMOOTH_FACTOR	Rx_Smooth_Factor
-+
-+#endif /* __HAL_PHY_REG_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/hal_sdio.h b/drivers/staging/rtl8723cs/include/hal_sdio.h
-new file mode 100644
-index 000000000000..dbdbdca437d6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_sdio.h
-@@ -0,0 +1,95 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __HAL_SDIO_H_
-+#define __HAL_SDIO_H_
-+
-+#define ffaddr2deviceId(pdvobj, addr)	(pdvobj->Queue2Pipe[addr])
-+
-+#ifndef RTW_HALMAC
-+extern const char *_sdio_tx_queue_str[];
-+#define sdio_tx_queue_str(_page_idx) (_page_idx >= SDIO_MAX_TX_QUEUE ? "UNKNOWN" : _sdio_tx_queue_str[_page_idx])
-+#endif
-+
-+u8 rtw_hal_sdio_max_txoqt_free_space(_adapter *padapter);
-+u8 rtw_hal_sdio_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
-+void rtw_hal_sdio_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
-+void rtw_hal_set_sdio_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ, u8 div_num);
-+u32 rtw_hal_get_sdio_tx_max_length(PADAPTER padapter, u8 queue_idx);
-+bool sdio_power_on_check(PADAPTER padapter);
-+
-+#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) ||defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8723D)
-+void rtw_hal_sdio_avail_page_threshold_init(_adapter *adapter);
-+void rtw_hal_sdio_avail_page_threshold_en(_adapter *adapter, u8 qidx, u8 pg_num);
-+#endif
-+#endif /* CONFIG_SDIO_TX_ENABLE_AVAL_INT */
-+
-+#ifdef CONFIG_FW_C2H_REG
-+void sd_c2h_hisr_hdl(_adapter *adapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8188F) || defined (CONFIG_RTL8188GTV) || defined (CONFIG_RTL8192F) || defined(CONFIG_RTL8723D)
-+#define SDIO_LOCAL_CMD_ADDR(addr) ((SDIO_LOCAL_DEVICE_ID << 13) | ((addr) & SDIO_LOCAL_MSK))
-+#endif
-+
-+#ifdef CONFIG_SDIO_CHK_HCI_RESUME
-+bool sdio_chk_hci_resume(struct intf_hdl *pintfhdl);
-+void sdio_chk_hci_suspend(struct intf_hdl *pintfhdl);
-+#else
-+#define sdio_chk_hci_resume(pintfhdl) _FALSE
-+#define sdio_chk_hci_suspend(pintfhdl) do {} while (0)
-+#endif /* CONFIG_SDIO_CHK_HCI_RESUME */
-+
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+/* program indirect access register in sdio local to read/write page0 registers */
-+s32 sdio_iread(PADAPTER padapter, u32 addr, u8 size, u8 *v);
-+s32 sdio_iwrite(PADAPTER padapter, u32 addr, u8 size, u8 *v);
-+u8 sdio_iread8(struct intf_hdl *pintfhdl, u32 addr);
-+u16 sdio_iread16(struct intf_hdl *pintfhdl, u32 addr);
-+u32 sdio_iread32(struct intf_hdl *pintfhdl, u32 addr);
-+s32 sdio_iwrite8(struct intf_hdl *pintfhdl, u32 addr, u8 val);
-+s32 sdio_iwrite16(struct intf_hdl *pintfhdl, u32 addr, u16 val);
-+s32 sdio_iwrite32(struct intf_hdl *pintfhdl, u32 addr, u32 val);
-+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
-+u32 cmd53_4byte_alignment(struct intf_hdl *pintfhdl, u32 addr);
-+
-+#ifndef CONFIG_SDIO_TX_TASKLET
-+#ifdef SDIO_FREE_XMIT_BUF_SEMA
-+void _rtw_sdio_free_xmitbuf_sema_up(struct xmit_priv *xmit);
-+void _rtw_sdio_free_xmitbuf_sema_down(struct xmit_priv *xmit);
-+#ifdef DBG_SDIO_FREE_XMIT_BUF_SEMA
-+void dbg_rtw_sdio_free_xmitbuf_sema_up(struct xmit_priv *xmit, const char *caller);
-+void dbg_rtw_sdio_free_xmitbuf_sema_down(struct xmit_priv *xmit, const char *caller);
-+#define rtw_sdio_free_xmitbuf_sema_up(_xmit) dbg_rtw_sdio_free_xmitbuf_sema_up(_xmit, __func__)
-+#define rtw_sdio_free_xmitbuf_sema_down(_xmit) dbg_rtw_sdio_free_xmitbuf_sema_down(_xmit, __func__)
-+#else
-+#define rtw_sdio_free_xmitbuf_sema_up(_xmit) _rtw_sdio_free_xmitbuf_sema_up(_xmit)
-+#define rtw_sdio_free_xmitbuf_sema_down(_xmit) _rtw_sdio_free_xmitbuf_sema_down(_xmit)
-+#endif /* DBG_SDIO_FREE_XMIT_BUF_SEMA */
-+#endif /* SDIO_FREE_XMIT_BUF_SEMA */
-+#endif /* !CONFIG_SDIO_TX_TASKLET */
-+
-+s32 sdio_initrecvbuf(struct recv_buf *recvbuf, _adapter *adapter);
-+void sdio_freerecvbuf(struct recv_buf *recvbuf);
-+
-+#ifdef CONFIG_SDIO_RECVBUF_PWAIT
-+void dump_recvbuf_pwait_conf(void *sel, struct recv_priv *recvpriv);
-+#ifdef CONFIG_SDIO_RECVBUF_PWAIT_RUNTIME_ADJUST
-+int recvbuf_pwait_config_req(struct recv_priv *recvpriv, enum rtw_pwait_type type, s32 time, s32 cnt_lmt);
-+int recvbuf_pwait_config_hdl(struct recv_priv *recvpriv, struct recv_buf *rbuf);
-+#endif /* CONFIG_SDIO_RECVBUF_PWAIT_RUNTIME_ADJUST */
-+#endif /* CONFIG_SDIO_RECVBUF_PWAIT */
-+
-+#endif /* __HAL_SDIO_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/hal_sdio_coex.h b/drivers/staging/rtl8723cs/include/hal_sdio_coex.h
-new file mode 100644
-index 000000000000..ce41b9988b23
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/hal_sdio_coex.h
-@@ -0,0 +1,41 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 Realtek Corporation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
-+ *
-+ *
-+ ******************************************************************************/
-+#ifndef __HAL_SDIO_COEX_H__
-+#define __HAL_SDIO_COEX_H__
-+
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_SDIO_MULTI_FUNCTION_COEX
-+
-+enum { /* for sdio multi-func. coex */
-+	SDIO_MULTI_WIFI = 0,
-+	SDIO_MULTI_BT,
-+	SDIO_MULTI_NUM
-+};
-+
-+bool ex_hal_sdio_multi_if_bus_available(PADAPTER adapter);
-+
-+#else
-+
-+#define ex_hal_sdio_multi_if_bus_available(adapter) TRUE
-+
-+#endif  /* CONFIG_SDIO_MULTI_FUNCTION_COEX */
-+#endif  /* !__HAL_SDIO_COEX_H__ */
-+
-diff --git a/drivers/staging/rtl8723cs/include/ieee80211.h b/drivers/staging/rtl8723cs/include/ieee80211.h
-new file mode 100644
-index 000000000000..61083d144935
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/ieee80211.h
-@@ -0,0 +1,2000 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __IEEE80211_H
-+#define __IEEE80211_H
-+
-+#define MGMT_QUEUE_NUM 5
-+
-+#define ETH_ALEN	6
-+#define ETH_TYPE_LEN		2
-+#define PAYLOAD_TYPE_LEN	1
-+
-+#define NET80211_TU_TO_US	1024		/* unit:us */
-+#define DEFAULT_BCN_INTERVAL 100 /* 100 ms */
-+
-+#ifdef CONFIG_AP_MODE
-+
-+#define RTL_IOCTL_HOSTAPD (SIOCDEVPRIVATE + 2)
-+
-+/* RTL871X_IOCTL_HOSTAPD ioctl() cmd: */
-+enum {
-+	RTL871X_HOSTAPD_FLUSH = 1,
-+	RTL871X_HOSTAPD_ADD_STA = 2,
-+	RTL871X_HOSTAPD_REMOVE_STA = 3,
-+	RTL871X_HOSTAPD_GET_INFO_STA = 4,
-+	/* REMOVED: PRISM2_HOSTAPD_RESET_TXEXC_STA = 5, */
-+	RTL871X_HOSTAPD_GET_WPAIE_STA = 5,
-+	RTL871X_SET_ENCRYPTION = 6,
-+	RTL871X_GET_ENCRYPTION = 7,
-+	RTL871X_HOSTAPD_SET_FLAGS_STA = 8,
-+	RTL871X_HOSTAPD_GET_RID = 9,
-+	RTL871X_HOSTAPD_SET_RID = 10,
-+	RTL871X_HOSTAPD_SET_ASSOC_AP_ADDR = 11,
-+	RTL871X_HOSTAPD_SET_GENERIC_ELEMENT = 12,
-+	RTL871X_HOSTAPD_MLME = 13,
-+	RTL871X_HOSTAPD_SCAN_REQ = 14,
-+	RTL871X_HOSTAPD_STA_CLEAR_STATS = 15,
-+	RTL871X_HOSTAPD_SET_BEACON = 16,
-+	RTL871X_HOSTAPD_SET_WPS_BEACON = 17,
-+	RTL871X_HOSTAPD_SET_WPS_PROBE_RESP = 18,
-+	RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP = 19,
-+	RTL871X_HOSTAPD_SET_HIDDEN_SSID = 20,
-+	RTL871X_HOSTAPD_SET_MACADDR_ACL = 21,
-+	RTL871X_HOSTAPD_ACL_ADD_STA = 22,
-+	RTL871X_HOSTAPD_ACL_REMOVE_STA = 23,
-+};
-+#endif /* CONFIG_AP_MODE */
-+
-+/* STA flags */
-+#define WLAN_STA_AUTH BIT(0)
-+#define WLAN_STA_ASSOC BIT(1)
-+#define WLAN_STA_PS BIT(2)
-+#define WLAN_STA_TIM BIT(3)
-+#define WLAN_STA_PERM BIT(4)
-+#define WLAN_STA_AUTHORIZED BIT(5)
-+#define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */
-+#define WLAN_STA_SHORT_PREAMBLE BIT(7)
-+#define WLAN_STA_PREAUTH BIT(8)
-+#define WLAN_STA_WME BIT(9)
-+#define WLAN_STA_MFP BIT(10)
-+#define WLAN_STA_HT BIT(11)
-+#define WLAN_STA_WPS BIT(12)
-+#define WLAN_STA_MAYBE_WPS BIT(13)
-+#define WLAN_STA_VHT BIT(14)
-+#define WLAN_STA_WDS BIT(15)
-+#define WLAN_STA_MULTI_AP BIT(16)
-+#define WLAN_STA_NONERP BIT(31)
-+
-+#define IEEE_CMD_SET_WPA_PARAM			1
-+#define IEEE_CMD_SET_WPA_IE				2
-+#define IEEE_CMD_SET_ENCRYPTION			3
-+#define IEEE_CMD_MLME						4
-+
-+#define IEEE_PARAM_WPA_ENABLED				1
-+#define IEEE_PARAM_TKIP_COUNTERMEASURES		2
-+#define IEEE_PARAM_DROP_UNENCRYPTED			3
-+#define IEEE_PARAM_PRIVACY_INVOKED			4
-+#define IEEE_PARAM_AUTH_ALGS					5
-+#define IEEE_PARAM_IEEE_802_1X				6
-+#define IEEE_PARAM_WPAX_SELECT				7
-+
-+#define AUTH_ALG_OPEN_SYSTEM			0x1
-+#define AUTH_ALG_SHARED_KEY			0x2
-+#define AUTH_ALG_LEAP				0x00000004
-+
-+#define IEEE_MLME_STA_DEAUTH				1
-+#define IEEE_MLME_STA_DISASSOC			2
-+
-+#define IEEE_CRYPT_ERR_UNKNOWN_ALG			2
-+#define IEEE_CRYPT_ERR_UNKNOWN_ADDR			3
-+#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED		4
-+#define IEEE_CRYPT_ERR_KEY_SET_FAILED			5
-+#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED		6
-+#define IEEE_CRYPT_ERR_CARD_CONF_FAILED		7
-+
-+
-+#define	IEEE_CRYPT_ALG_NAME_LEN			16
-+
-+#define WPA_CIPHER_NONE	BIT(0)
-+#define WPA_CIPHER_WEP40	BIT(1)
-+#define WPA_CIPHER_WEP104 BIT(2)
-+#define WPA_CIPHER_TKIP	BIT(3)
-+#define WPA_CIPHER_CCMP	BIT(4)
-+#define WPA_CIPHER_GCMP	BIT(5)
-+#define WPA_CIPHER_GCMP_256	BIT(6)
-+#define WPA_CIPHER_CCMP_256	BIT(7)
-+#define WPA_CIPHER_BIP_CMAC_128	BIT(8)
-+#define WPA_CIPHER_BIP_GMAC_128	BIT(9)
-+#define WPA_CIPHER_BIP_GMAC_256	BIT(10)
-+#define WPA_CIPHER_BIP_CMAC_256	BIT(11)
-+
-+
-+#define WPA_SELECTOR_LEN 4
-+extern u8 RTW_WPA_OUI_TYPE[] ;
-+extern u16 RTW_WPA_VERSION ;
-+extern u8 WPA_AUTH_KEY_MGMT_NONE[];
-+extern u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[];
-+extern u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[];
-+extern u8 WPA_CIPHER_SUITE_NONE[];
-+extern u8 WPA_CIPHER_SUITE_WEP40[];
-+extern u8 WPA_CIPHER_SUITE_TKIP[];
-+extern u8 WPA_CIPHER_SUITE_WRAP[];
-+extern u8 WPA_CIPHER_SUITE_CCMP[];
-+extern u8 RSN_CIPHER_SUITE_GCMP[];
-+extern u8 RSN_CIPHER_SUITE_GCMP_256[];
-+extern u8 RSN_CIPHER_SUITE_CCMP_256[];
-+extern u8 WPA_CIPHER_SUITE_WEP104[];
-+
-+
-+#define RSN_HEADER_LEN 4
-+#define RSN_SELECTOR_LEN 4
-+
-+extern u16 RSN_VERSION_BSD;
-+extern u8 RSN_CIPHER_SUITE_NONE[];
-+extern u8 RSN_CIPHER_SUITE_WEP40[];
-+extern u8 RSN_CIPHER_SUITE_TKIP[];
-+extern u8 RSN_CIPHER_SUITE_WRAP[];
-+extern u8 RSN_CIPHER_SUITE_CCMP[];
-+extern u8 RSN_CIPHER_SUITE_WEP104[];
-+
-+/* AKM suite type */
-+extern u8 WLAN_AKM_8021X[];
-+extern u8 WLAN_AKM_PSK[];
-+extern u8 WLAN_AKM_FT_8021X[];
-+extern u8 WLAN_AKM_FT_PSK[];
-+extern u8 WLAN_AKM_8021X_SHA256[];
-+extern u8 WLAN_AKM_PSK_SHA256[];
-+extern u8 WLAN_AKM_TDLS[];
-+extern u8 WLAN_AKM_SAE[];
-+extern u8 WLAN_AKM_FT_OVER_SAE[];
-+extern u8 WLAN_AKM_8021X_SUITE_B[];
-+extern u8 WLAN_AKM_8021X_SUITE_B_192[];
-+extern u8 WLAN_AKM_FILS_SHA256[];
-+extern u8 WLAN_AKM_FILS_SHA384[];
-+extern u8 WLAN_AKM_FT_FILS_SHA256[];
-+extern u8 WLAN_AKM_FT_FILS_SHA384[];
-+
-+#define WLAN_AKM_TYPE_8021X BIT(0)
-+#define WLAN_AKM_TYPE_PSK BIT(1)
-+#define WLAN_AKM_TYPE_FT_8021X BIT(2)
-+#define WLAN_AKM_TYPE_FT_PSK BIT(3)
-+#define WLAN_AKM_TYPE_8021X_SHA256 BIT(4)
-+#define WLAN_AKM_TYPE_PSK_SHA256 BIT(5)
-+#define WLAN_AKM_TYPE_TDLS BIT(6)
-+#define WLAN_AKM_TYPE_SAE BIT(7)
-+#define WLAN_AKM_TYPE_FT_OVER_SAE BIT(8)
-+#define WLAN_AKM_TYPE_8021X_SUITE_B BIT(9)
-+#define WLAN_AKM_TYPE_8021X_SUITE_B_192 BIT(10)
-+#define WLAN_AKM_TYPE_FILS_SHA256 BIT(11)
-+#define WLAN_AKM_TYPE_FILS_SHA384 BIT(12)
-+#define WLAN_AKM_TYPE_FT_FILS_SHA256 BIT(13)
-+#define WLAN_AKM_TYPE_FT_FILS_SHA384 BIT(14)
-+
-+/* IEEE 802.11i */
-+#define PMKID_LEN 16
-+#define PMK_LEN 32
-+#define PMK_LEN_SUITE_B_192 48
-+#define PMK_LEN_MAX 48
-+#define WPA_REPLAY_COUNTER_LEN 8
-+#define WPA_NONCE_LEN 32
-+#define WPA_KEY_RSC_LEN 8
-+#define WPA_GMK_LEN 32
-+#define WPA_GTK_MAX_LEN 32
-+
-+/* IEEE 802.11, 8.5.2 EAPOL-Key frames */
-+#define WPA_KEY_INFO_TYPE_MASK ((u16) (BIT(0) | BIT(1) | BIT(2)))
-+#define WPA_KEY_INFO_TYPE_AKM_DEFINED 0
-+#define WPA_KEY_INFO_TYPE_HMAC_MD5_RC4 BIT(0)
-+#define WPA_KEY_INFO_TYPE_HMAC_SHA1_AES BIT(1)
-+#define WPA_KEY_INFO_TYPE_AES_128_CMAC 3
-+#define WPA_KEY_INFO_KEY_TYPE BIT(3) /* 1 = Pairwise, 0 = Group key */
-+/* bit4..5 is used in WPA, but is reserved in IEEE 802.11i/RSN */
-+#define WPA_KEY_INFO_KEY_INDEX_MASK (BIT(4) | BIT(5))
-+#define WPA_KEY_INFO_KEY_INDEX_SHIFT 4
-+#define WPA_KEY_INFO_INSTALL BIT(6) /* pairwise */
-+#define WPA_KEY_INFO_TXRX BIT(6) /* group */
-+#define WPA_KEY_INFO_ACK BIT(7)
-+#define WPA_KEY_INFO_MIC BIT(8)
-+#define WPA_KEY_INFO_SECURE BIT(9)
-+#define WPA_KEY_INFO_ERROR BIT(10)
-+#define WPA_KEY_INFO_REQUEST BIT(11)
-+#define WPA_KEY_INFO_ENCR_KEY_DATA BIT(12) /* IEEE 802.11i/RSN only */
-+#define WPA_KEY_INFO_SMK_MESSAGE BIT(13)
-+
-+struct ieee802_1x_hdr {
-+	u8 version;
-+	u8 type;
-+	u16 length;
-+	/* followed by length octets of data */
-+};
-+
-+struct wpa_eapol_key {
-+	u8 type;
-+	/* Note: key_info, key_length, and key_data_length are unaligned */
-+	u8 key_info[2]; /* big endian */
-+	u8 key_length[2]; /* big endian */
-+	u8 replay_counter[WPA_REPLAY_COUNTER_LEN];
-+	u8 key_nonce[WPA_NONCE_LEN];
-+	u8 key_iv[16];
-+	u8 key_rsc[WPA_KEY_RSC_LEN];
-+	u8 key_id[8]; /* Reserved in IEEE 802.11i/RSN */
-+	u8 key_mic[16];
-+	u8 key_data_length[2]; /* big endian */
-+	/* followed by key_data_length bytes of key_data */
-+};
-+
-+typedef enum _RATEID_IDX_ {
-+	RATEID_IDX_BGN_40M_2SS = 0,
-+	RATEID_IDX_BGN_40M_1SS = 1,
-+	RATEID_IDX_BGN_20M_2SS_BN = 2,
-+	RATEID_IDX_BGN_20M_1SS_BN = 3,
-+	RATEID_IDX_GN_N2SS = 4,
-+	RATEID_IDX_GN_N1SS = 5,
-+	RATEID_IDX_BG = 6,
-+	RATEID_IDX_G = 7,
-+	RATEID_IDX_B = 8,
-+	RATEID_IDX_VHT_2SS = 9,
-+	RATEID_IDX_VHT_1SS = 10,
-+	RATEID_IDX_MIX1 = 11,
-+	RATEID_IDX_MIX2 = 12,
-+	RATEID_IDX_VHT_3SS = 13,
-+	RATEID_IDX_BGN_3SS = 14,
-+	RATEID_IDX_BGN_4SS = 15,
-+	RATEID_IDX_VHT_4SS = 16,
-+} RATEID_IDX, *PRATEID_IDX;
-+
-+typedef enum _RATR_TABLE_MODE {
-+	RATR_INX_WIRELESS_NGB = 0,	/* BGN 40 Mhz 2SS 1SS */
-+	RATR_INX_WIRELESS_NG = 1,		/* GN or N */
-+	RATR_INX_WIRELESS_NB = 2,		/* BGN 20 Mhz 2SS 1SS  or BN */
-+	RATR_INX_WIRELESS_N = 3,
-+	RATR_INX_WIRELESS_GB = 4,
-+	RATR_INX_WIRELESS_G = 5,
-+	RATR_INX_WIRELESS_B = 6,
-+	RATR_INX_WIRELESS_MC = 7,
-+	RATR_INX_WIRELESS_AC_N = 8,
-+} RATR_TABLE_MODE, *PRATR_TABLE_MODE;
-+
-+
-+enum NETWORK_TYPE {
-+	WIRELESS_INVALID = 0,
-+	/* Sub-Element */
-+	WIRELESS_11B = BIT(0), /* tx: cck only , rx: cck only, hw: cck */
-+	WIRELESS_11G = BIT(1), /* tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm */
-+	WIRELESS_11A = BIT(2), /* tx: ofdm only, rx: ofdm only, hw: ofdm only */
-+	WIRELESS_11_24N = BIT(3), /* tx: MCS only, rx: MCS & cck, hw: MCS & cck */
-+	WIRELESS_11_5N = BIT(4), /* tx: MCS only, rx: MCS & ofdm, hw: ofdm only */
-+	WIRELESS_AUTO = BIT(5),
-+	WIRELESS_11AC = BIT(6),
-+
-+	/* Combination */
-+	/* Type for current wireless mode */
-+	WIRELESS_11BG = (WIRELESS_11B | WIRELESS_11G), /* tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm */
-+	WIRELESS_11G_24N = (WIRELESS_11G | WIRELESS_11_24N), /* tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm */
-+	WIRELESS_11A_5N = (WIRELESS_11A | WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */
-+	WIRELESS_11B_24N = (WIRELESS_11B | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */
-+	WIRELESS_11BG_24N = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */
-+	WIRELESS_11_24AC = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11AC),
-+	WIRELESS_11_5AC = (WIRELESS_11A | WIRELESS_11AC),
-+
-+
-+	/* Type for registry default wireless mode */
-+	WIRELESS_11AGN = (WIRELESS_11A | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */
-+	WIRELESS_11ABGN = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N),
-+	WIRELESS_MODE_24G = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N),
-+	WIRELESS_MODE_5G = (WIRELESS_11A | WIRELESS_11_5N | WIRELESS_11AC),
-+	WIRELESS_MODE_MAX = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N | WIRELESS_11AC),
-+};
-+
-+#define SUPPORTED_24G_NETTYPE_MSK WIRELESS_MODE_24G
-+#define SUPPORTED_5G_NETTYPE_MSK WIRELESS_MODE_5G
-+
-+#define IsLegacyOnly(NetType)  ((NetType) == ((NetType) & (WIRELESS_11BG | WIRELESS_11A)))
-+
-+#define IsSupported24G(NetType) ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? _TRUE : _FALSE)
-+#define is_supported_5g(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? _TRUE : _FALSE)
-+
-+#define IsEnableHWCCK(NetType) IsSupported24G(NetType)
-+#define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11_24N | SUPPORTED_5G_NETTYPE_MSK) ? _TRUE : _FALSE)
-+
-+#define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType)
-+#define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType)
-+#define IsSupportedRxHT(NetType) IsEnableHWOFDM(NetType)
-+
-+#define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE)
-+#define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11A) ? _TRUE : _FALSE)
-+#define is_supported_ht(NetType) ((NetType) & (WIRELESS_11_24N | WIRELESS_11_5N) ? _TRUE : _FALSE)
-+
-+#define is_supported_vht(NetType) ((NetType) & (WIRELESS_11AC) ? _TRUE : _FALSE)
-+
-+
-+
-+
-+
-+typedef struct ieee_param {
-+	u32 cmd;
-+	u8 sta_addr[ETH_ALEN];
-+	union {
-+		struct {
-+			u8 name;
-+			u32 value;
-+		} wpa_param;
-+		struct {
-+			u32 len;
-+			u8 reserved[32];
-+			u8 data[0];
-+		} wpa_ie;
-+		struct {
-+			int command;
-+			int reason_code;
-+		} mlme;
-+		struct {
-+			u8 alg[IEEE_CRYPT_ALG_NAME_LEN];
-+			u8 set_tx;
-+			u32 err;
-+			u8 idx;
-+			u8 seq[8]; /* sequence counter (set: RX, get: TX) */
-+			u16 key_len;
-+			u8 key[0];
-+		} crypt;
-+#ifdef CONFIG_AP_MODE
-+		struct {
-+			u16 aid;
-+			u16 capability;
-+			int flags;
-+			u8 tx_supp_rates[16];
-+			struct rtw_ieee80211_ht_cap ht_cap;
-+		} add_sta;
-+		struct {
-+			u8	reserved[2];/* for set max_num_sta */
-+			u8	buf[0];
-+		} bcn_ie;
-+#endif
-+
-+	} u;
-+} ieee_param;
-+
-+#ifdef CONFIG_AP_MODE
-+typedef struct ieee_param_ex {
-+	u32 cmd;
-+	u8 sta_addr[ETH_ALEN];
-+	u8 data[0];
-+} ieee_param_ex;
-+
-+struct sta_data {
-+	u16 aid;
-+	u16 capability;
-+	int flags;
-+	u32 sta_set;
-+	u8 tx_supp_rates[16];
-+	u32 tx_supp_rates_len;
-+	struct rtw_ieee80211_ht_cap ht_cap;
-+	u64	rx_pkts;
-+	u64	rx_bytes;
-+	u64	rx_drops;
-+	u64	tx_pkts;
-+	u64	tx_bytes;
-+	u64	tx_drops;
-+};
-+#endif
-+
-+
-+#if WIRELESS_EXT < 17
-+	#define IW_QUAL_QUAL_INVALID   0x10
-+	#define IW_QUAL_LEVEL_INVALID  0x20
-+	#define IW_QUAL_NOISE_INVALID  0x40
-+	#define IW_QUAL_QUAL_UPDATED   0x1
-+	#define IW_QUAL_LEVEL_UPDATED  0x2
-+	#define IW_QUAL_NOISE_UPDATED  0x4
-+#endif
-+
-+#define IEEE80211_DATA_LEN		2304
-+/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section
-+   6.2.1.1.2.
-+
-+   The figure in section 7.1.2 suggests a body size of up to 2312
-+   bytes is allowed, which is a bit confusing, I suspect this
-+   represents the 2304 bytes of real data, plus a possible 8 bytes of
-+   WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */
-+
-+
-+#define IEEE80211_HLEN			30
-+#define IEEE80211_FRAME_LEN		(IEEE80211_DATA_LEN + IEEE80211_HLEN)
-+
-+
-+/* this is stolen from ipw2200 driver */
-+#define IEEE_IBSS_MAC_HASH_SIZE 31
-+
-+struct ieee_ibss_seq {
-+	u8 mac[ETH_ALEN];
-+	u16 seq_num;
-+	u16 frag_num;
-+	unsigned long packet_time;
-+	_list	list;
-+};
-+
-+#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
-+
-+struct rtw_ieee80211_hdr {
-+	u16 frame_ctl;
-+	u16 duration_id;
-+	u8 addr1[ETH_ALEN];
-+	u8 addr2[ETH_ALEN];
-+	u8 addr3[ETH_ALEN];
-+	u16 seq_ctl;
-+	u8 addr4[ETH_ALEN];
-+} __attribute__((packed));
-+
-+struct rtw_ieee80211_hdr_3addr {
-+	u16 frame_ctl;
-+	u16 duration_id;
-+	u8 addr1[ETH_ALEN];
-+	u8 addr2[ETH_ALEN];
-+	u8 addr3[ETH_ALEN];
-+	u16 seq_ctl;
-+} __attribute__((packed));
-+
-+
-+struct rtw_ieee80211_hdr_qos {
-+	u16 frame_ctl;
-+	u16 duration_id;
-+	u8 addr1[ETH_ALEN];
-+	u8 addr2[ETH_ALEN];
-+	u8 addr3[ETH_ALEN];
-+	u16 seq_ctl;
-+	u8 addr4[ETH_ALEN];
-+	u16	qc;
-+}  __attribute__((packed));
-+
-+struct rtw_ieee80211_hdr_3addr_qos {
-+	u16 frame_ctl;
-+	u16 duration_id;
-+	u8 addr1[ETH_ALEN];
-+	u8 addr2[ETH_ALEN];
-+	u8 addr3[ETH_ALEN];
-+	u16 seq_ctl;
-+	u16     qc;
-+}  __attribute__((packed));
-+
-+struct eapol {
-+	u8 snap[6];
-+	u16 ethertype;
-+	u8 version;
-+	u8 type;
-+	u16 length;
-+} __attribute__((packed));
-+
-+struct rtw_ieee80211s_hdr {
-+	u8 flags;
-+	u8 ttl;
-+	u32 seqnum;
-+	u8 eaddr1[ETH_ALEN];
-+	u8 eaddr2[ETH_ALEN];
-+} __attribute__((packed));
-+
-+/**
-+ * struct rtw_ieee80211_rann_ie
-+ *
-+ * This structure refers to "Root Announcement information element"
-+ */
-+ struct rtw_ieee80211_rann_ie {
-+	u8 rann_flags;
-+	u8 rann_hopcount;
-+	u8 rann_ttl;
-+	u8 rann_addr[ETH_ALEN];
-+	u32 rann_seq;
-+	u32 rann_interval;
-+	u32 rann_metric;
-+} __attribute__((packed));
-+#endif
-+
-+/* Some IEEE 802.11x packet types are corresponding to parsing_eapol_packet() */
-+enum eap_type {
-+	EAP_PACKET = 0,
-+	NON_EAPOL,
-+	EAPOL_START,
-+	EAPOL_LOGOFF,
-+	EAPOL_KEY,
-+	EAPOL_ENCAP_ASF_ALERT,
-+	EAPOL_PACKET,
-+	EAPOL_WPA_GROUP_KEY_1_2,
-+	EAPOL_WPA_GROUP_KEY_2_2,
-+	EAPOL_1_4,
-+	EAPOL_2_4,
-+	EAPOL_3_4,
-+	EAPOL_4_4,
-+};
-+
-+#define IEEE80211_3ADDR_LEN 24
-+#define IEEE80211_4ADDR_LEN 30
-+#define IEEE80211_FCS_LEN    4
-+
-+#define MIN_FRAG_THRESHOLD     256U
-+#define	MAX_FRAG_THRESHOLD     2346U
-+
-+/* Frame control field constants */
-+#define RTW_IEEE80211_FCTL_VERS		0x0003
-+#define RTW_IEEE80211_FCTL_FTYPE		0x000c
-+#define RTW_IEEE80211_FCTL_STYPE		0x00f0
-+#define RTW_IEEE80211_FCTL_TODS		0x0100
-+#define RTW_IEEE80211_FCTL_FROMDS	0x0200
-+#define RTW_IEEE80211_FCTL_MOREFRAGS	0x0400
-+#define RTW_IEEE80211_FCTL_RETRY		0x0800
-+#define RTW_IEEE80211_FCTL_PM		0x1000
-+#define RTW_IEEE80211_FCTL_MOREDATA	0x2000
-+#define RTW_IEEE80211_FCTL_PROTECTED	0x4000
-+#define RTW_IEEE80211_FCTL_ORDER		0x8000
-+#define RTW_IEEE80211_FCTL_CTL_EXT	0x0f00
-+
-+#define RTW_IEEE80211_FTYPE_MGMT		0x0000
-+#define RTW_IEEE80211_FTYPE_CTL		0x0004
-+#define RTW_IEEE80211_FTYPE_DATA		0x0008
-+#define RTW_IEEE80211_FTYPE_EXT		0x000c
-+
-+/* management */
-+#define RTW_IEEE80211_STYPE_ASSOC_REQ	0x0000
-+#define RTW_IEEE80211_STYPE_ASSOC_RESP	0x0010
-+#define RTW_IEEE80211_STYPE_REASSOC_REQ	0x0020
-+#define RTW_IEEE80211_STYPE_REASSOC_RESP	0x0030
-+#define RTW_IEEE80211_STYPE_PROBE_REQ	0x0040
-+#define RTW_IEEE80211_STYPE_PROBE_RESP	0x0050
-+#define RTW_IEEE80211_STYPE_BEACON		0x0080
-+#define RTW_IEEE80211_STYPE_ATIM		0x0090
-+#define RTW_IEEE80211_STYPE_DISASSOC	0x00A0
-+#define RTW_IEEE80211_STYPE_AUTH		0x00B0
-+#define RTW_IEEE80211_STYPE_DEAUTH		0x00C0
-+#define RTW_IEEE80211_STYPE_ACTION		0x00D0
-+
-+/* control */
-+#define RTW_IEEE80211_STYPE_CTL_EXT		0x0060
-+#define RTW_IEEE80211_STYPE_BACK_REQ		0x0080
-+#define RTW_IEEE80211_STYPE_BACK		0x0090
-+#define RTW_IEEE80211_STYPE_PSPOLL		0x00A0
-+#define RTW_IEEE80211_STYPE_RTS		0x00B0
-+#define RTW_IEEE80211_STYPE_CTS		0x00C0
-+#define RTW_IEEE80211_STYPE_ACK		0x00D0
-+#define RTW_IEEE80211_STYPE_CFEND		0x00E0
-+#define RTW_IEEE80211_STYPE_CFENDACK		0x00F0
-+
-+/* data */
-+#define RTW_IEEE80211_STYPE_DATA		0x0000
-+#define RTW_IEEE80211_STYPE_DATA_CFACK	0x0010
-+#define RTW_IEEE80211_STYPE_DATA_CFPOLL	0x0020
-+#define RTW_IEEE80211_STYPE_DATA_CFACKPOLL	0x0030
-+#define RTW_IEEE80211_STYPE_NULLFUNC	0x0040
-+#define RTW_IEEE80211_STYPE_CFACK		0x0050
-+#define RTW_IEEE80211_STYPE_CFPOLL		0x0060
-+#define RTW_IEEE80211_STYPE_CFACKPOLL	0x0070
-+#define RTW_IEEE80211_STYPE_QOS_DATA		0x0080
-+#define RTW_IEEE80211_STYPE_QOS_DATA_CFACK		0x0090
-+#define RTW_IEEE80211_STYPE_QOS_DATA_CFPOLL		0x00A0
-+#define RTW_IEEE80211_STYPE_QOS_DATA_CFACKPOLL	0x00B0
-+#define RTW_IEEE80211_STYPE_QOS_NULLFUNC	0x00C0
-+#define RTW_IEEE80211_STYPE_QOS_CFACK		0x00D0
-+#define RTW_IEEE80211_STYPE_QOS_CFPOLL		0x00E0
-+#define RTW_IEEE80211_STYPE_QOS_CFACKPOLL	0x00F0
-+
-+/* sequence control field */
-+#define RTW_IEEE80211_SCTL_FRAG	0x000F
-+#define RTW_IEEE80211_SCTL_SEQ	0xFFF0
-+
-+
-+#define RTW_ERP_INFO_NON_ERP_PRESENT BIT(0)
-+#define RTW_ERP_INFO_USE_PROTECTION BIT(1)
-+#define RTW_ERP_INFO_BARKER_PREAMBLE_MODE BIT(2)
-+
-+/* QoS,QOS */
-+#define NORMAL_ACK			0
-+#define NO_ACK				1
-+#define NON_EXPLICIT_ACK	2
-+#define BLOCK_ACK			3
-+
-+#ifndef ETH_P_PAE
-+	#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */
-+#endif /* ETH_P_PAE */
-+
-+#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */
-+
-+#define ETH_P_ECONET	0x0018
-+
-+#ifndef ETH_P_80211_RAW
-+	#define ETH_P_80211_RAW (ETH_P_ECONET + 1)
-+#endif
-+
-+/* IEEE 802.11 defines */
-+
-+#define P80211_OUI_LEN 3
-+
-+#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
-+
-+struct ieee80211_snap_hdr {
-+
-+	u8    dsap;   /* always 0xAA */
-+	u8    ssap;   /* always 0xAA */
-+	u8    ctrl;   /* always 0x03 */
-+	u8    oui[P80211_OUI_LEN];    /* organizational universal id */
-+
-+} __attribute__((packed));
-+
-+#endif
-+
-+#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
-+
-+#define WLAN_FC_GET_TYPE(fc) ((fc) & RTW_IEEE80211_FCTL_FTYPE)
-+#define WLAN_FC_GET_STYPE(fc) ((fc) & RTW_IEEE80211_FCTL_STYPE)
-+
-+#define WLAN_QC_GET_TID(qc) ((qc) & 0x0f)
-+
-+#define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG)
-+#define WLAN_GET_SEQ_SEQ(seq)  ((seq) & RTW_IEEE80211_SCTL_SEQ)
-+
-+/* Authentication algorithms */
-+#define WLAN_AUTH_OPEN 0
-+#define WLAN_AUTH_SHARED_KEY 1
-+#define WLAN_AUTH_SAE 3
-+
-+#define WLAN_AUTH_CHALLENGE_LEN 128
-+
-+#define WLAN_CAPABILITY_BSS (1<<0)
-+#define WLAN_CAPABILITY_IBSS (1<<1)
-+#define WLAN_CAPABILITY_CF_POLLABLE (1<<2)
-+#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3)
-+#define WLAN_CAPABILITY_PRIVACY (1<<4)
-+#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5)
-+#define WLAN_CAPABILITY_PBCC (1<<6)
-+#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7)
-+#define WLAN_CAPABILITY_SHORT_SLOT (1<<10)
-+
-+/* Status codes */
-+#define WLAN_STATUS_SUCCESS 0
-+#define WLAN_STATUS_UNSPECIFIED_FAILURE 1
-+#define WLAN_STATUS_CAPS_UNSUPPORTED 10
-+#define WLAN_STATUS_REASSOC_NO_ASSOC 11
-+#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12
-+#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13
-+#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14
-+#define WLAN_STATUS_CHALLENGE_FAIL 15
-+#define WLAN_STATUS_AUTH_TIMEOUT 16
-+#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17
-+#define WLAN_STATUS_ASSOC_DENIED_RATES 18
-+/* 802.11b */
-+#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19
-+#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20
-+#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21
-+
-+/* Reason codes */
-+#define WLAN_REASON_UNSPECIFIED 1
-+#define WLAN_REASON_PREV_AUTH_NOT_VALID 2
-+#define WLAN_REASON_DEAUTH_LEAVING 3
-+#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4
-+#define WLAN_REASON_DISASSOC_AP_BUSY 5
-+#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6
-+#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7
-+#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8
-+#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9
-+#define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23
-+#define WLAN_REASON_MESH_PEER_CANCELED 52
-+#define WLAN_REASON_MESH_MAX_PEERS 53
-+#define WLAN_REASON_MESH_CONFIG 54
-+#define WLAN_REASON_MESH_CLOSE 55
-+#define WLAN_REASON_MESH_MAX_RETRIES 56 
-+#define WLAN_REASON_MESH_CONFIRM_TIMEOUT 57
-+#define WLAN_REASON_MESH_INVALID_GTK 58
-+#define WLAN_REASON_MESH_INCONSISTENT_PARAM 59
-+#define WLAN_REASON_MESH_INVALID_SECURITY 60
-+#define WLAN_REASON_MESH_PATH_NOPROXY 61
-+#define WLAN_REASON_MESH_PATH_NOFORWARD 62
-+#define WLAN_REASON_MESH_PATH_DEST_UNREACHABLE 63
-+#define WLAN_REASON_MAC_EXISTS_IN_MBSS 64
-+#define WLAN_REASON_MESH_CHAN_REGULATORY 65
-+#define WLAN_REASON_MESH_CHAN 66
-+#define WLAN_REASON_SA_QUERY_TIMEOUT 65532
-+#define WLAN_REASON_ACTIVE_ROAM 65533
-+#define WLAN_REASON_JOIN_WRONG_CHANNEL       65534
-+#define WLAN_REASON_EXPIRATION_CHK 65535
-+
-+#define WLAN_REASON_IS_PRIVATE(reason) ( \
-+	reason == WLAN_REASON_EXPIRATION_CHK \
-+	|| reason == WLAN_REASON_JOIN_WRONG_CHANNEL \
-+	|| reason == WLAN_REASON_ACTIVE_ROAM \
-+	|| reason == WLAN_REASON_SA_QUERY_TIMEOUT \
-+	)
-+
-+/* Information Element IDs */
-+#define WLAN_EID_SSID 0
-+#define WLAN_EID_SUPP_RATES 1
-+#define WLAN_EID_FH_PARAMS 2
-+#define WLAN_EID_DS_PARAMS 3
-+#define WLAN_EID_CF_PARAMS 4
-+#define WLAN_EID_TIM 5
-+#define WLAN_EID_IBSS_PARAMS 6
-+#define WLAN_EID_CHALLENGE 16
-+/* EIDs defined by IEEE 802.11h - START */
-+#define WLAN_EID_PWR_CONSTRAINT 32
-+#define WLAN_EID_PWR_CAPABILITY 33
-+#define WLAN_EID_TPC_REQUEST 34
-+#define WLAN_EID_TPC_REPORT 35
-+#define WLAN_EID_SUPPORTED_CHANNELS 36
-+#define WLAN_EID_CHANNEL_SWITCH 37
-+#define WLAN_EID_MEASURE_REQUEST 38
-+#define WLAN_EID_MEASURE_REPORT 39
-+#define WLAN_EID_QUITE 40
-+#define WLAN_EID_IBSS_DFS 41
-+/* EIDs defined by IEEE 802.11h - END */
-+#define WLAN_EID_ERP_INFO 42
-+#define WLAN_EID_HT_CAP 45
-+#define WLAN_EID_RSN 48
-+#define WLAN_EID_EXT_SUPP_RATES 50
-+#define WLAN_EID_MOBILITY_DOMAIN 54
-+#define WLAN_EID_FAST_BSS_TRANSITION 55
-+#define WLAN_EID_TIMEOUT_INTERVAL 56
-+#define WLAN_EID_RIC_DATA 57
-+#define WLAN_EID_HT_OPERATION 61
-+#define WLAN_EID_SECONDARY_CHANNEL_OFFSET 62
-+#define WLAN_EID_20_40_BSS_COEXISTENCE 72
-+#define WLAN_EID_20_40_BSS_INTOLERANT 73
-+#define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74
-+#define WLAN_EID_MMIE 76
-+#define WLAN_EID_MESH_CONFIG 113
-+#define WLAN_EID_MESH_ID 114
-+#define WLAN_EID_MPM 117
-+#define	WLAN_EID_RANN 126
-+#define	WLAN_EID_PREQ 130
-+#define	WLAN_EID_PREP 131
-+#define	WLAN_EID_PERR 132
-+#define WLAN_EID_AMPE 139
-+#define WLAN_EID_MIC 140
-+#define WLAN_EID_VENDOR_SPECIFIC 221
-+#define WLAN_EID_GENERIC (WLAN_EID_VENDOR_SPECIFIC)
-+#define WLAN_EID_VHT_CAPABILITY 191
-+#define WLAN_EID_VHT_OPERATION 192
-+#define WLAN_EID_WIDE_BANDWIDTH_CHANNEL_SWITCH 194
-+#define WLAN_EID_CHANNEL_SWITCH_WRAPPER 196
-+#define WLAN_EID_VHT_OP_MODE_NOTIFY 199
-+#define WLAN_EID_EXTENSION 255
-+#define WLAN_EID_EXT_OWE_DH_PARAM 32
-+
-+#define IEEE80211_MGMT_HDR_LEN 24
-+#define IEEE80211_DATA_HDR3_LEN 24
-+#define IEEE80211_DATA_HDR4_LEN 30
-+
-+
-+#define IEEE80211_STATMASK_SIGNAL (1<<0)
-+#define IEEE80211_STATMASK_RSSI (1<<1)
-+#define IEEE80211_STATMASK_NOISE (1<<2)
-+#define IEEE80211_STATMASK_RATE (1<<3)
-+#define IEEE80211_STATMASK_WEMASK 0x7
-+
-+
-+#define IEEE80211_CCK_MODULATION    (1<<0)
-+#define IEEE80211_OFDM_MODULATION   (1<<1)
-+
-+#define IEEE80211_24GHZ_BAND     (1<<0)
-+#define IEEE80211_52GHZ_BAND     (1<<1)
-+
-+#define IEEE80211_CCK_RATE_LEN		4
-+#define IEEE80211_NUM_OFDM_RATESLEN	8
-+
-+
-+
-+#define IEEE80211_CCK_RATE_1MB		        0x02
-+#define IEEE80211_CCK_RATE_2MB		        0x04
-+#define IEEE80211_CCK_RATE_5MB		        0x0B
-+#define IEEE80211_CCK_RATE_11MB		        0x16
-+#define IEEE80211_OFDM_RATE_LEN		8
-+#define IEEE80211_OFDM_RATE_6MB		        0x0C
-+#define IEEE80211_OFDM_RATE_9MB		        0x12
-+#define IEEE80211_OFDM_RATE_12MB		0x18
-+#define IEEE80211_OFDM_RATE_18MB		0x24
-+#define IEEE80211_OFDM_RATE_24MB		0x30
-+#define IEEE80211_PBCC_RATE_22MB		0x2C
-+#define IEEE80211_FREAK_RATE_22_5MB		0x2D
-+#define IEEE80211_OFDM_RATE_36MB		0x48
-+#define IEEE80211_OFDM_RATE_48MB		0x60
-+#define IEEE80211_OFDM_RATE_54MB		0x6C
-+#define IEEE80211_BASIC_RATE_MASK		0x80
-+
-+#define IEEE80211_CCK_RATE_1MB_MASK		(1<<0)
-+#define IEEE80211_CCK_RATE_2MB_MASK		(1<<1)
-+#define IEEE80211_CCK_RATE_5MB_MASK		(1<<2)
-+#define IEEE80211_CCK_RATE_11MB_MASK		(1<<3)
-+#define IEEE80211_OFDM_RATE_6MB_MASK		(1<<4)
-+#define IEEE80211_OFDM_RATE_9MB_MASK		(1<<5)
-+#define IEEE80211_OFDM_RATE_12MB_MASK		(1<<6)
-+#define IEEE80211_OFDM_RATE_18MB_MASK		(1<<7)
-+#define IEEE80211_OFDM_RATE_24MB_MASK		(1<<8)
-+#define IEEE80211_OFDM_RATE_36MB_MASK		(1<<9)
-+#define IEEE80211_OFDM_RATE_48MB_MASK		(1<<10)
-+#define IEEE80211_OFDM_RATE_54MB_MASK		(1<<11)
-+
-+#define IEEE80211_CCK_RATES_MASK	        0x0000000F
-+#define IEEE80211_CCK_BASIC_RATES_MASK	(IEEE80211_CCK_RATE_1MB_MASK | \
-+		IEEE80211_CCK_RATE_2MB_MASK)
-+#define IEEE80211_CCK_DEFAULT_RATES_MASK	(IEEE80211_CCK_BASIC_RATES_MASK | \
-+		IEEE80211_CCK_RATE_5MB_MASK | \
-+		IEEE80211_CCK_RATE_11MB_MASK)
-+
-+#define IEEE80211_OFDM_RATES_MASK		0x00000FF0
-+#define IEEE80211_OFDM_BASIC_RATES_MASK	(IEEE80211_OFDM_RATE_6MB_MASK | \
-+		IEEE80211_OFDM_RATE_12MB_MASK | \
-+		IEEE80211_OFDM_RATE_24MB_MASK)
-+#define IEEE80211_OFDM_DEFAULT_RATES_MASK	(IEEE80211_OFDM_BASIC_RATES_MASK | \
-+		IEEE80211_OFDM_RATE_9MB_MASK  | \
-+		IEEE80211_OFDM_RATE_18MB_MASK | \
-+		IEEE80211_OFDM_RATE_36MB_MASK | \
-+		IEEE80211_OFDM_RATE_48MB_MASK | \
-+		IEEE80211_OFDM_RATE_54MB_MASK)
-+#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \
-+				      IEEE80211_CCK_DEFAULT_RATES_MASK)
-+
-+#define IEEE80211_NUM_OFDM_RATES	    8
-+#define IEEE80211_NUM_CCK_RATES	            4
-+#define IEEE80211_OFDM_SHIFT_MASK_A         4
-+
-+
-+enum MGN_RATE {
-+	MGN_1M		= 0x02,
-+	MGN_2M		= 0x04,
-+	MGN_5_5M	= 0x0B,
-+	MGN_6M		= 0x0C,
-+	MGN_9M		= 0x12,
-+	MGN_11M	= 0x16,
-+	MGN_12M	= 0x18,
-+	MGN_18M	= 0x24,
-+	MGN_24M	= 0x30,
-+	MGN_36M	= 0x48,
-+	MGN_48M	= 0x60,
-+	MGN_54M	= 0x6C,
-+	MGN_MCS32	= 0x7F,
-+	MGN_MCS0,
-+	MGN_MCS1,
-+	MGN_MCS2,
-+	MGN_MCS3,
-+	MGN_MCS4,
-+	MGN_MCS5,
-+	MGN_MCS6,
-+	MGN_MCS7,
-+	MGN_MCS8,
-+	MGN_MCS9,
-+	MGN_MCS10,
-+	MGN_MCS11,
-+	MGN_MCS12,
-+	MGN_MCS13,
-+	MGN_MCS14,
-+	MGN_MCS15,
-+	MGN_MCS16,
-+	MGN_MCS17,
-+	MGN_MCS18,
-+	MGN_MCS19,
-+	MGN_MCS20,
-+	MGN_MCS21,
-+	MGN_MCS22,
-+	MGN_MCS23,
-+	MGN_MCS24,
-+	MGN_MCS25,
-+	MGN_MCS26,
-+	MGN_MCS27,
-+	MGN_MCS28,
-+	MGN_MCS29,
-+	MGN_MCS30,
-+	MGN_MCS31,
-+	MGN_VHT1SS_MCS0,
-+	MGN_VHT1SS_MCS1,
-+	MGN_VHT1SS_MCS2,
-+	MGN_VHT1SS_MCS3,
-+	MGN_VHT1SS_MCS4,
-+	MGN_VHT1SS_MCS5,
-+	MGN_VHT1SS_MCS6,
-+	MGN_VHT1SS_MCS7,
-+	MGN_VHT1SS_MCS8,
-+	MGN_VHT1SS_MCS9,
-+	MGN_VHT2SS_MCS0,
-+	MGN_VHT2SS_MCS1,
-+	MGN_VHT2SS_MCS2,
-+	MGN_VHT2SS_MCS3,
-+	MGN_VHT2SS_MCS4,
-+	MGN_VHT2SS_MCS5,
-+	MGN_VHT2SS_MCS6,
-+	MGN_VHT2SS_MCS7,
-+	MGN_VHT2SS_MCS8,
-+	MGN_VHT2SS_MCS9,
-+	MGN_VHT3SS_MCS0,
-+	MGN_VHT3SS_MCS1,
-+	MGN_VHT3SS_MCS2,
-+	MGN_VHT3SS_MCS3,
-+	MGN_VHT3SS_MCS4,
-+	MGN_VHT3SS_MCS5,
-+	MGN_VHT3SS_MCS6,
-+	MGN_VHT3SS_MCS7,
-+	MGN_VHT3SS_MCS8,
-+	MGN_VHT3SS_MCS9,
-+	MGN_VHT4SS_MCS0,
-+	MGN_VHT4SS_MCS1,
-+	MGN_VHT4SS_MCS2,
-+	MGN_VHT4SS_MCS3,
-+	MGN_VHT4SS_MCS4,
-+	MGN_VHT4SS_MCS5,
-+	MGN_VHT4SS_MCS6,
-+	MGN_VHT4SS_MCS7,
-+	MGN_VHT4SS_MCS8,
-+	MGN_VHT4SS_MCS9,
-+	MGN_UNKNOWN
-+};
-+
-+#define IS_HT_RATE(_rate)	((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS31)
-+#define IS_VHT_RATE(_rate)	((_rate) >= MGN_VHT1SS_MCS0 && (_rate) <= MGN_VHT4SS_MCS9)
-+#define IS_CCK_RATE(_rate)	((_rate) == MGN_1M || (_rate) == MGN_2M || (_rate) == MGN_5_5M || (_rate) == MGN_11M)
-+#define IS_OFDM_RATE(_rate)	((_rate) >= MGN_6M && (_rate) <= MGN_54M  && (_rate) != MGN_11M)
-+
-+#define IS_HT1SS_RATE(_rate) ((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS7)
-+#define IS_HT2SS_RATE(_rate) ((_rate) >= MGN_MCS8 && (_rate) <= MGN_MCS15)
-+#define IS_HT3SS_RATE(_rate) ((_rate) >= MGN_MCS16 && (_rate) <= MGN_MCS23)
-+#define IS_HT4SS_RATE(_rate) ((_rate) >= MGN_MCS24 && (_rate) <= MGN_MCS31)
-+
-+#define IS_VHT1SS_RATE(_rate) ((_rate) >= MGN_VHT1SS_MCS0 && (_rate) <= MGN_VHT1SS_MCS9)
-+#define IS_VHT2SS_RATE(_rate) ((_rate) >= MGN_VHT2SS_MCS0 && (_rate) <= MGN_VHT2SS_MCS9)
-+#define IS_VHT3SS_RATE(_rate) ((_rate) >= MGN_VHT3SS_MCS0 && (_rate) <= MGN_VHT3SS_MCS9)
-+#define IS_VHT4SS_RATE(_rate) ((_rate) >= MGN_VHT4SS_MCS0 && (_rate) <= MGN_VHT4SS_MCS9)
-+
-+#define IS_1T_RATE(_rate)	(IS_CCK_RATE((_rate)) || IS_OFDM_RATE((_rate)) || IS_HT1SS_RATE((_rate)) || IS_VHT1SS_RATE((_rate)))
-+#define IS_2T_RATE(_rate)	(IS_HT2SS_RATE((_rate)) || IS_VHT2SS_RATE((_rate)))
-+#define IS_3T_RATE(_rate)	(IS_HT3SS_RATE((_rate)) || IS_VHT3SS_RATE((_rate)))
-+#define IS_4T_RATE(_rate)	(IS_HT4SS_RATE((_rate)) || IS_VHT4SS_RATE((_rate)))
-+
-+const char *MGN_RATE_STR(enum MGN_RATE rate);
-+
-+typedef enum _RATE_SECTION {
-+	CCK = 0,
-+	OFDM = 1,
-+	HT_MCS0_MCS7 = 2,
-+	HT_MCS8_MCS15 = 3,
-+	HT_MCS16_MCS23 = 4,
-+	HT_MCS24_MCS31 = 5,
-+	HT_1SS = HT_MCS0_MCS7,
-+	HT_2SS = HT_MCS8_MCS15,
-+	HT_3SS = HT_MCS16_MCS23,
-+	HT_4SS = HT_MCS24_MCS31,
-+	VHT_1SSMCS0_1SSMCS9 = 6,
-+	VHT_2SSMCS0_2SSMCS9 = 7,
-+	VHT_3SSMCS0_3SSMCS9 = 8,
-+	VHT_4SSMCS0_4SSMCS9 = 9,
-+	VHT_1SS = VHT_1SSMCS0_1SSMCS9,
-+	VHT_2SS = VHT_2SSMCS0_2SSMCS9,
-+	VHT_3SS = VHT_3SSMCS0_3SSMCS9,
-+	VHT_4SS = VHT_4SSMCS0_4SSMCS9,
-+	RATE_SECTION_NUM,
-+} RATE_SECTION;
-+
-+RATE_SECTION mgn_rate_to_rs(enum MGN_RATE rate);
-+
-+const char *rate_section_str(u8 section);
-+
-+#define IS_CCK_RATE_SECTION(section) ((section) == CCK)
-+#define IS_OFDM_RATE_SECTION(section) ((section) == OFDM)
-+#define IS_HT_RATE_SECTION(section) ((section) >= HT_1SS && (section) <= HT_4SS)
-+#define IS_VHT_RATE_SECTION(section) ((section) >= VHT_1SS && (section) <= VHT_4SS)
-+
-+#define IS_1T_RATE_SECTION(section) ((section) == CCK || (section) == OFDM || (section) == HT_1SS || (section) == VHT_1SS)
-+#define IS_2T_RATE_SECTION(section) ((section) == HT_2SS || (section) == VHT_2SS)
-+#define IS_3T_RATE_SECTION(section) ((section) == HT_3SS || (section) == VHT_3SS)
-+#define IS_4T_RATE_SECTION(section) ((section) == HT_4SS || (section) == VHT_4SS)
-+
-+extern u8 mgn_rates_cck[];
-+extern u8 mgn_rates_ofdm[];
-+extern u8 mgn_rates_mcs0_7[];
-+extern u8 mgn_rates_mcs8_15[];
-+extern u8 mgn_rates_mcs16_23[];
-+extern u8 mgn_rates_mcs24_31[];
-+extern u8 mgn_rates_vht1ss[];
-+extern u8 mgn_rates_vht2ss[];
-+extern u8 mgn_rates_vht3ss[];
-+extern u8 mgn_rates_vht4ss[];
-+
-+struct rate_section_ent {
-+	u8 tx_num; /* value of RF_TX_NUM */
-+	u8 rate_num;
-+	u8 *rates;
-+};
-+
-+extern struct rate_section_ent rates_by_sections[];
-+
-+#define rate_section_to_tx_num(section) (rates_by_sections[(section)].tx_num)
-+#define rate_section_rate_num(section) (rates_by_sections[(section)].rate_num)
-+
-+/* NOTE: This data is for statistical purposes; not all hardware provides this
-+ *       information for frames received.  Not setting these will not cause
-+ *       any adverse affects. */
-+struct ieee80211_rx_stats {
-+	/* u32 mac_time[2]; */
-+	s8 rssi;
-+	u8 signal;
-+	u8 noise;
-+	u8 received_channel;
-+	u16 rate; /* in 100 kbps */
-+	/* u8 control; */
-+	u8 mask;
-+	u8 freq;
-+	u16 len;
-+};
-+
-+/* IEEE 802.11 requires that STA supports concurrent reception of at least
-+ * three fragmented frames. This define can be increased to support more
-+ * concurrent frames, but it should be noted that each entry can consume about
-+ * 2 kB of RAM and increasing cache size will slow down frame reassembly. */
-+#define IEEE80211_FRAG_CACHE_LEN 4
-+
-+struct ieee80211_frag_entry {
-+	u32 first_frag_time;
-+	uint seq;
-+	uint last_frag;
-+	uint qos;   /* jackson */
-+	uint tid;	/* jackson */
-+	struct sk_buff *skb;
-+	u8 src_addr[ETH_ALEN];
-+	u8 dst_addr[ETH_ALEN];
-+};
-+
-+#ifndef PLATFORM_FREEBSD /* Baron BSD has already defined */
-+struct ieee80211_stats {
-+	uint tx_unicast_frames;
-+	uint tx_multicast_frames;
-+	uint tx_fragments;
-+	uint tx_unicast_octets;
-+	uint tx_multicast_octets;
-+	uint tx_deferred_transmissions;
-+	uint tx_single_retry_frames;
-+	uint tx_multiple_retry_frames;
-+	uint tx_retry_limit_exceeded;
-+	uint tx_discards;
-+	uint rx_unicast_frames;
-+	uint rx_multicast_frames;
-+	uint rx_fragments;
-+	uint rx_unicast_octets;
-+	uint rx_multicast_octets;
-+	uint rx_fcs_errors;
-+	uint rx_discards_no_buffer;
-+	uint tx_discards_wrong_sa;
-+	uint rx_discards_undecryptable;
-+	uint rx_message_in_msg_fragments;
-+	uint rx_message_in_bad_msg_fragments;
-+};
-+#endif /* PLATFORM_FREEBSD */
-+struct ieee80211_softmac_stats {
-+	uint rx_ass_ok;
-+	uint rx_ass_err;
-+	uint rx_probe_rq;
-+	uint tx_probe_rs;
-+	uint tx_beacons;
-+	uint rx_auth_rq;
-+	uint rx_auth_rs_ok;
-+	uint rx_auth_rs_err;
-+	uint tx_auth_rq;
-+	uint no_auth_rs;
-+	uint no_ass_rs;
-+	uint tx_ass_rq;
-+	uint rx_ass_rq;
-+	uint tx_probe_rq;
-+	uint reassoc;
-+	uint swtxstop;
-+	uint swtxawake;
-+};
-+
-+#define SEC_KEY_1         (1<<0)
-+#define SEC_KEY_2         (1<<1)
-+#define SEC_KEY_3         (1<<2)
-+#define SEC_KEY_4         (1<<3)
-+#define SEC_ACTIVE_KEY    (1<<4)
-+#define SEC_AUTH_MODE     (1<<5)
-+#define SEC_UNICAST_GROUP (1<<6)
-+#define SEC_LEVEL         (1<<7)
-+#define SEC_ENABLED       (1<<8)
-+
-+#define SEC_LEVEL_0      0 /* None */
-+#define SEC_LEVEL_1      1 /* WEP 40 and 104 bit */
-+#define SEC_LEVEL_2      2 /* Level 1 + TKIP */
-+#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */
-+#define SEC_LEVEL_3      4 /* Level 2 + CCMP */
-+
-+#define WEP_KEYS 4
-+#define WEP_KEY_LEN 13
-+#define BIP_MAX_KEYID 5
-+#define BIP_AAD_SIZE  20
-+
-+#if defined(PLATFORM_LINUX)
-+struct ieee80211_security {
-+	u16 active_key:2,
-+	    enabled:1,
-+	    auth_mode:2,
-+	    auth_algo:4,
-+	    unicast_uses_group:1;
-+	u8 key_sizes[WEP_KEYS];
-+	u8 keys[WEP_KEYS][WEP_KEY_LEN];
-+	u8 level;
-+	u16 flags;
-+} __attribute__((packed));
-+
-+#endif
-+
-+/*
-+
-+ 802.11 data frame from AP
-+
-+      ,-------------------------------------------------------------------.
-+Bytes |  2   |  2   |    6    |    6    |    6    |  2   | 0..2312 |   4  |
-+      |------|------|---------|---------|---------|------|---------|------|
-+Desc. | ctrl | dura |  DA/RA  |   TA    |    SA   | Sequ |  frame  |  fcs |
-+      |      | tion | (BSSID) |         |         | ence |  data   |      |
-+      `-------------------------------------------------------------------'
-+
-+Total: 28-2340 bytes
-+
-+*/
-+
-+struct ieee80211_header_data {
-+	u16 frame_ctl;
-+	u16 duration_id;
-+	u8 addr1[6];
-+	u8 addr2[6];
-+	u8 addr3[6];
-+	u16 seq_ctrl;
-+};
-+
-+#define BEACON_PROBE_SSID_ID_POSITION 12
-+
-+/* Management Frame Information Element Types */
-+#define MFIE_TYPE_SSID       0
-+#define MFIE_TYPE_RATES      1
-+#define MFIE_TYPE_FH_SET     2
-+#define MFIE_TYPE_DS_SET     3
-+#define MFIE_TYPE_CF_SET     4
-+#define MFIE_TYPE_TIM        5
-+#define MFIE_TYPE_IBSS_SET   6
-+#define MFIE_TYPE_CHALLENGE  16
-+#define MFIE_TYPE_ERP        42
-+#define MFIE_TYPE_RSN	     48
-+#define MFIE_TYPE_RATES_EX   50
-+#define MFIE_TYPE_GENERIC    221
-+
-+#if defined(PLATFORM_LINUX)
-+struct ieee80211_info_element_hdr {
-+	u8 id;
-+	u8 len;
-+} __attribute__((packed));
-+
-+struct ieee80211_info_element {
-+	u8 id;
-+	u8 len;
-+	u8 data[0];
-+} __attribute__((packed));
-+#endif
-+
-+
-+/*
-+ * These are the data types that can make up management packets
-+ *
-+	u16 auth_algorithm;
-+	u16 auth_sequence;
-+	u16 beacon_interval;
-+	u16 capability;
-+	u8 current_ap[ETH_ALEN];
-+	u16 listen_interval;
-+	struct {
-+		u16 association_id:14, reserved:2;
-+	} __attribute__ ((packed));
-+	u32 time_stamp[2];
-+	u16 reason;
-+	u16 status;
-+*/
-+
-+#define IEEE80211_DEFAULT_TX_ESSID "Penguin"
-+#define IEEE80211_DEFAULT_BASIC_RATE 10
-+
-+
-+#if defined(PLATFORM_LINUX)
-+struct ieee80211_authentication {
-+	struct ieee80211_header_data header;
-+	u16 algorithm;
-+	u16 transaction;
-+	u16 status;
-+	/* struct ieee80211_info_element_hdr info_element; */
-+} __attribute__((packed));
-+
-+
-+struct ieee80211_probe_response {
-+	struct ieee80211_header_data header;
-+	u32 time_stamp[2];
-+	u16 beacon_interval;
-+	u16 capability;
-+	struct ieee80211_info_element info_element;
-+} __attribute__((packed));
-+
-+struct ieee80211_probe_request {
-+	struct ieee80211_header_data header;
-+	/*struct ieee80211_info_element info_element;*/
-+} __attribute__((packed));
-+
-+struct ieee80211_assoc_request_frame {
-+	struct rtw_ieee80211_hdr_3addr header;
-+	u16 capability;
-+	u16 listen_interval;
-+	/* u8 current_ap[ETH_ALEN]; */
-+	struct ieee80211_info_element_hdr info_element;
-+} __attribute__((packed));
-+
-+struct ieee80211_assoc_response_frame {
-+	struct rtw_ieee80211_hdr_3addr header;
-+	u16 capability;
-+	u16 status;
-+	u16 aid;
-+	/*	struct ieee80211_info_element info_element;  supported rates  */
-+} __attribute__((packed));
-+#endif
-+
-+struct ieee80211_txb {
-+	u8 nr_frags;
-+	u8 encrypted;
-+	u16 reserved;
-+	u16 frag_size;
-+	u16 payload_size;
-+	struct sk_buff *fragments[0];
-+};
-+
-+
-+/* SWEEP TABLE ENTRIES NUMBER*/
-+#define MAX_SWEEP_TAB_ENTRIES		  42
-+#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET  7
-+/* MAX_RATES_LENGTH needs to be 12.  The spec says 8, and many APs
-+ * only use 8, and then use extended rates for the remaining supported
-+ * rates.  Other APs, however, stick all of their supported rates on the
-+ * main rates information element... */
-+#define MAX_RATES_LENGTH                  ((u8)12)
-+#define MAX_RATES_EX_LENGTH               ((u8)16)
-+#define MAX_NETWORK_COUNT                  128
-+#define IEEE80211_SOFTMAC_SCAN_TIME	  400
-+/* (HZ / 2) */
-+#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2)
-+
-+#define CRC_LENGTH                 4U
-+
-+#define MAX_WPA_IE_LEN (256)
-+#define MAX_WPS_IE_LEN (512)
-+#define MAX_OWE_IE_LEN (128)
-+#define MAX_P2P_IE_LEN (256)
-+#define MAX_WFD_IE_LEN (128)
-+
-+#define NETWORK_EMPTY_ESSID (1<<0)
-+#define NETWORK_HAS_OFDM    (1<<1)
-+#define NETWORK_HAS_CCK     (1<<2)
-+
-+#define IEEE80211_DTIM_MBCAST 4
-+#define IEEE80211_DTIM_UCAST 2
-+#define IEEE80211_DTIM_VALID 1
-+#define IEEE80211_DTIM_INVALID 0
-+
-+#define IEEE80211_PS_DISABLED 0
-+#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST
-+#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST
-+#define IW_ESSID_MAX_SIZE 32
-+#if 0
-+struct ieee80211_network {
-+	/* These entries are used to identify a unique network */
-+	u8 bssid[ETH_ALEN];
-+	u8 channel;
-+	/* Ensure null-terminated for any debug msgs */
-+	u8 ssid[IW_ESSID_MAX_SIZE + 1];
-+	u8 ssid_len;
-+	u8	rssi;	/* relative signal strength */
-+	u8	sq;		/* signal quality */
-+
-+	/* These are network statistics */
-+	/* struct ieee80211_rx_stats stats; */
-+	u16 capability;
-+	u16	aid;
-+	u8 rates[MAX_RATES_LENGTH];
-+	u8 rates_len;
-+	u8 rates_ex[MAX_RATES_EX_LENGTH];
-+	u8 rates_ex_len;
-+
-+	u8 edca_parmsets[18];
-+
-+	u8 mode;
-+	u8 flags;
-+	u8 time_stamp[8];
-+	u16 beacon_interval;
-+	u16 listen_interval;
-+	u16 atim_window;
-+	u8 wpa_ie[MAX_WPA_IE_LEN];
-+	size_t wpa_ie_len;
-+	u8 rsn_ie[MAX_WPA_IE_LEN];
-+	size_t rsn_ie_len;
-+	u8 country[6];
-+	u8 dtim_period;
-+	u8 dtim_data;
-+	u8 power_constraint;
-+	u8 qosinfo;
-+	u8 qbssload[5];
-+	u8 network_type;
-+	int join_res;
-+	unsigned long	last_scanned;
-+};
-+#endif
-+/*
-+join_res:
-+-1: authentication fail
-+-2: association fail
-+> 0: TID
-+*/
-+
-+#ifndef PLATFORM_FREEBSD /* Baron BSD has already defined */
-+
-+enum ieee80211_state {
-+
-+	/* the card is not linked at all */
-+	IEEE80211_NOLINK = 0,
-+
-+	/* IEEE80211_ASSOCIATING* are for BSS client mode
-+	 * the driver shall not perform RX filtering unless
-+	 * the state is LINKED.
-+	 * The driver shall just check for the state LINKED and
-+	 * defaults to NOLINK for ALL the other states (including
-+	 * LINKED_SCANNING)
-+	 */
-+
-+	/* the association procedure will start (wq scheduling)*/
-+	IEEE80211_ASSOCIATING,
-+	IEEE80211_ASSOCIATING_RETRY,
-+
-+	/* the association procedure is sending AUTH request*/
-+	IEEE80211_ASSOCIATING_AUTHENTICATING,
-+
-+	/* the association procedure has successfully authentcated
-+	 * and is sending association request
-+	 */
-+	IEEE80211_ASSOCIATING_AUTHENTICATED,
-+
-+	/* the link is ok. the card associated to a BSS or linked
-+	 * to a ibss cell or acting as an AP and creating the bss
-+	 */
-+	IEEE80211_LINKED,
-+
-+	/* same as LINKED, but the driver shall apply RX filter
-+	 * rules as we are in NO_LINK mode. As the card is still
-+	 * logically linked, but it is doing a syncro site survey
-+	 * then it will be back to LINKED state.
-+	 */
-+	IEEE80211_LINKED_SCANNING,
-+
-+};
-+#endif /* PLATFORM_FREEBSD */
-+
-+#define DEFAULT_MAX_SCAN_AGE (15 * HZ)
-+#define DEFAULT_FTS 2346
-+#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
-+#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5]
-+#define MAC_SFMT "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx"
-+#define MAC_SARG(x) ((u8*)(x)),((u8*)(x)) + 1,((u8*)(x)) + 2,((u8*)(x)) + 3,((u8*)(x)) + 4,((u8*)(x)) + 5
-+#define IP_FMT "%d.%d.%d.%d"
-+#define IP_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3]
-+#define PORT_FMT "%u"
-+#define PORT_ARG(x) ntohs(*((u16 *)(x)))
-+
-+#define is_multicast_mac_addr(Addr) ((((Addr[0]) & 0x01) == 0x01) && ((Addr[0]) != 0xff))
-+#define is_broadcast_mac_addr(Addr) ((((Addr[0]) & 0xff) == 0xff) && (((Addr[1]) & 0xff) == 0xff) && \
-+	(((Addr[2]) & 0xff) == 0xff) && (((Addr[3]) & 0xff) == 0xff) && (((Addr[4]) & 0xff) == 0xff) && \
-+				     (((Addr[5]) & 0xff) == 0xff))
-+#define is_zero_mac_addr(Addr)	((Addr[0] == 0x00) && (Addr[1] == 0x00) && (Addr[2] == 0x00) &&   \
-+                (Addr[3] == 0x00) && (Addr[4] == 0x00) && (Addr[5] == 0x00))
-+
-+
-+#define CFG_IEEE80211_RESERVE_FCS (1<<0)
-+#define CFG_IEEE80211_COMPUTE_FCS (1<<1)
-+
-+typedef struct tx_pending_t {
-+	int frag;
-+	struct ieee80211_txb *txb;
-+} tx_pending_t;
-+
-+
-+
-+#define TID_NUM	16
-+
-+#define IEEE_A            (1<<0)
-+#define IEEE_B            (1<<1)
-+#define IEEE_G            (1<<2)
-+#define IEEE_MODE_MASK    (IEEE_A | IEEE_B | IEEE_G)
-+
-+/* Baron move to ieee80211.c */
-+int ieee80211_is_empty_essid(const char *essid, int essid_len);
-+int ieee80211_get_hdrlen(u16 fc);
-+
-+#if 0
-+	/* Action frame categories (IEEE 802.11-2007, 7.3.1.11, Table 7-24) */
-+	#define WLAN_ACTION_SPECTRUM_MGMT 0
-+	#define WLAN_ACTION_QOS 1
-+	#define WLAN_ACTION_DLS 2
-+	#define WLAN_ACTION_BLOCK_ACK 3
-+	#define WLAN_ACTION_RADIO_MEASUREMENT 5
-+	#define WLAN_ACTION_FT 6
-+	#define WLAN_ACTION_SA_QUERY 8
-+	#define WLAN_ACTION_WMM 17
-+#endif
-+
-+
-+/* Action category code */
-+enum rtw_ieee80211_category {
-+	RTW_WLAN_CATEGORY_SPECTRUM_MGMT = 0,
-+	RTW_WLAN_CATEGORY_QOS = 1,
-+	RTW_WLAN_CATEGORY_DLS = 2,
-+	RTW_WLAN_CATEGORY_BACK = 3,
-+	RTW_WLAN_CATEGORY_PUBLIC = 4, /* IEEE 802.11 public action frames */
-+	RTW_WLAN_CATEGORY_RADIO_MEAS = 5,
-+	RTW_WLAN_CATEGORY_FT = 6,
-+	RTW_WLAN_CATEGORY_HT = 7,
-+	RTW_WLAN_CATEGORY_SA_QUERY = 8,
-+	RTW_WLAN_CATEGORY_WNM = 10,
-+	RTW_WLAN_CATEGORY_UNPROTECTED_WNM = 11, /* add for CONFIG_IEEE80211W, none 11w also can use */
-+	RTW_WLAN_CATEGORY_TDLS = 12,
-+	RTW_WLAN_CATEGORY_MESH = 13,
-+	RTW_WLAN_CATEGORY_MULTIHOP = 14,
-+	RTW_WLAN_CATEGORY_SELF_PROTECTED = 15,
-+	RTW_WLAN_CATEGORY_WMM = 17,
-+	RTW_WLAN_CATEGORY_VHT = 21,
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	RTW_WLAN_CATEGORY_TBTX = 25,
-+#endif
-+	RTW_WLAN_CATEGORY_P2P = 0x7f,/* P2P action frames */
-+};
-+
-+#define CATEGORY_IS_GROUP_PRIVACY(cat) \
-+	(cat == RTW_WLAN_CATEGORY_MESH || cat == RTW_WLAN_CATEGORY_MULTIHOP)
-+
-+#define CATEGORY_IS_NON_ROBUST(cat) \
-+	(cat == RTW_WLAN_CATEGORY_PUBLIC \
-+	|| cat == RTW_WLAN_CATEGORY_HT \
-+	|| cat == RTW_WLAN_CATEGORY_UNPROTECTED_WNM \
-+	|| cat == RTW_WLAN_CATEGORY_SELF_PROTECTED \
-+	|| cat == RTW_WLAN_CATEGORY_VHT \
-+	|| cat == RTW_WLAN_CATEGORY_P2P)
-+
-+#define CATEGORY_IS_ROBUST(cat) !CATEGORY_IS_NON_ROBUST(cat)
-+
-+/* SPECTRUM_MGMT action code */
-+enum rtw_ieee80211_spectrum_mgmt_actioncode {
-+	RTW_WLAN_ACTION_SPCT_MSR_REQ = 0,
-+	RTW_WLAN_ACTION_SPCT_MSR_RPRT = 1,
-+	RTW_WLAN_ACTION_SPCT_TPC_REQ = 2,
-+	RTW_WLAN_ACTION_SPCT_TPC_RPRT = 3,
-+	RTW_WLAN_ACTION_SPCT_CHL_SWITCH = 4,
-+	RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
-+};
-+
-+/* SELF_PROTECTED action code */
-+enum rtw_ieee80211_self_protected_actioncode {
-+	RTW_ACT_SELF_PROTECTED_RSVD = 0,
-+	RTW_ACT_SELF_PROTECTED_MESH_OPEN = 1,
-+	RTW_ACT_SELF_PROTECTED_MESH_CONF = 2,
-+	RTW_ACT_SELF_PROTECTED_MESH_CLOSE = 3,
-+	RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM = 4,
-+	RTW_ACT_SELF_PROTECTED_MESH_GK_ACK = 5,
-+	RTW_ACT_SELF_PROTECTED_NUM,
-+};
-+
-+/* MESH action code */
-+enum rtw_ieee80211_mesh_actioncode {
-+	RTW_ACT_MESH_LINK_METRIC_REPORT,
-+	RTW_ACT_MESH_HWMP_PATH_SELECTION,
-+	RTW_ACT_MESH_GATE_ANNOUNCEMENT,
-+	RTW_ACT_MESH_CONGESTION_CONTROL_NOTIFICATION,
-+	RTW_ACT_MESH_MCCA_SETUP_REQUEST,
-+	RTW_ACT_MESH_MCCA_SETUP_REPLY,
-+	RTW_ACT_MESH_MCCA_ADVERTISEMENT_REQUEST,
-+	RTW_ACT_MESH_MCCA_ADVERTISEMENT,
-+	RTW_ACT_MESH_MCCA_TEARDOWN,
-+	RTW_ACT_MESH_TBTT_ADJUSTMENT_REQUEST,
-+	RTW_ACT_MESH_TBTT_ADJUSTMENT_RESPONSE,
-+};
-+
-+enum _PUBLIC_ACTION {
-+	ACT_PUBLIC_BSSCOEXIST = 0, /* 20/40 BSS Coexistence */
-+	ACT_PUBLIC_DSE_ENABLE = 1,
-+	ACT_PUBLIC_DSE_DEENABLE = 2,
-+	ACT_PUBLIC_DSE_REG_LOCATION = 3,
-+	ACT_PUBLIC_EXT_CHL_SWITCH = 4,
-+	ACT_PUBLIC_DSE_MSR_REQ = 5,
-+	ACT_PUBLIC_DSE_MSR_RPRT = 6,
-+	ACT_PUBLIC_MP = 7, /* Measurement Pilot */
-+	ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8,
-+	ACT_PUBLIC_VENDOR = 9, /* for WIFI_DIRECT */
-+	ACT_PUBLIC_GAS_INITIAL_REQ = 10,
-+	ACT_PUBLIC_GAS_INITIAL_RSP = 11,
-+	ACT_PUBLIC_GAS_COMEBACK_REQ = 12,
-+	ACT_PUBLIC_GAS_COMEBACK_RSP = 13,
-+	ACT_PUBLIC_TDLS_DISCOVERY_RSP = 14,
-+	ACT_PUBLIC_LOCATION_TRACK = 15,
-+	ACT_PUBLIC_QAB_REQ,
-+	ACT_PUBLIC_QAB_RSP,
-+	ACT_PUBLIC_QMF_POLICY,
-+	ACT_PUBLIC_QMF_POLICY_CHANGE,
-+	ACT_PUBLIC_QLOAD_REQ,
-+	ACT_PUBLIC_QLOAD_REPORT,
-+	ACT_PUBLIC_HCCA_TXOP_ADV,
-+	ACT_PUBLIC_HCCA_TXOP_RSP,
-+	ACT_PUBLIC_PUBLIC_KEY,
-+	ACT_PUBLIC_CH_AVAILABILITY_QUERY,
-+	ACT_PUBLIC_CH_SCHEDULE_MGMT,
-+	ACT_PUBLIC_CONTACT_VERI_SIGNAL,
-+	ACT_PUBLIC_GDD_ENABLE_REQ,
-+	ACT_PUBLIC_GDD_ENABLE_RSP,
-+	ACT_PUBLIC_NETWORK_CH_CONTROL,
-+	ACT_PUBLIC_WHITE_SPACE_MAP_ANN,
-+	ACT_PUBLIC_FTM_REQ,
-+	ACT_PUBLIC_FTM,
-+	ACT_PUBLIC_MAX
-+};
-+
-+#ifdef CONFIG_TDLS
-+enum TDLS_ACTION_FIELD {
-+	TDLS_SETUP_REQUEST = 0,
-+	TDLS_SETUP_RESPONSE = 1,
-+	TDLS_SETUP_CONFIRM = 2,
-+	TDLS_TEARDOWN = 3,
-+	TDLS_PEER_TRAFFIC_INDICATION = 4,
-+	TDLS_CHANNEL_SWITCH_REQUEST = 5,
-+	TDLS_CHANNEL_SWITCH_RESPONSE = 6,
-+	TDLS_PEER_PSM_REQUEST = 7,
-+	TDLS_PEER_PSM_RESPONSE = 8,
-+	TDLS_PEER_TRAFFIC_RESPONSE = 9,
-+	TDLS_DISCOVERY_REQUEST = 10,
-+	TDLS_DISCOVERY_RESPONSE = 14,	/* it's used in public action frame */
-+};
-+
-+#define	TUNNELED_PROBE_REQ	15
-+#define	TUNNELED_PROBE_RSP	16
-+#endif /* CONFIG_TDLS */
-+
-+/* BACK action code */
-+enum rtw_ieee80211_back_actioncode {
-+	RTW_WLAN_ACTION_ADDBA_REQ = 0,
-+	RTW_WLAN_ACTION_ADDBA_RESP = 1,
-+	RTW_WLAN_ACTION_DELBA = 2,
-+};
-+
-+/* HT features action code */
-+enum rtw_ieee80211_ht_actioncode {
-+	RTW_WLAN_ACTION_HT_NOTI_CHNL_WIDTH = 0,
-+	RTW_WLAN_ACTION_HT_SM_PS = 1,
-+	RTW_WLAN_ACTION_HT_PSMP = 2,
-+	RTW_WLAN_ACTION_HT_SET_PCO_PHASE = 3,
-+	RTW_WLAN_ACTION_HT_CSI = 4,
-+	RTW_WLAN_ACTION_HT_NON_COMPRESS_BEAMFORMING = 5,
-+	RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING = 6,
-+	RTW_WLAN_ACTION_HT_ASEL_FEEDBACK = 7,
-+};
-+
-+/* BACK (block-ack) parties */
-+enum rtw_ieee80211_back_parties {
-+	RTW_WLAN_BACK_RECIPIENT = 0,
-+	RTW_WLAN_BACK_INITIATOR = 1,
-+	RTW_WLAN_BACK_TIMER = 2,
-+};
-+
-+/*20/40 BSS Coexistence element */
-+#define RTW_WLAN_20_40_BSS_COEX_INFO_REQ            BIT(0)
-+#define RTW_WLAN_20_40_BSS_COEX_40MHZ_INTOL         BIT(1)
-+#define RTW_WLAN_20_40_BSS_COEX_20MHZ_WIDTH_REQ     BIT(2)
-+#define RTW_WLAN_20_40_BSS_COEX_OBSS_EXEMPT_REQ     BIT(3)
-+#define RTW_WLAN_20_40_BSS_COEX_OBSS_EXEMPT_GRNT    BIT(4)
-+
-+/* VHT features action code */
-+enum rtw_ieee80211_vht_actioncode {
-+	RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING = 0,
-+	RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT = 1,
-+	RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION = 2,
-+};
-+
-+#define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs)
-+				* 00:50:F2 */
-+#ifndef PLATFORM_FREEBSD /* Baron BSD has defined */
-+	#define WME_OUI_TYPE 2
-+#endif /* PLATFORM_FREEBSD */
-+#define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0
-+#define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1
-+#define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2
-+#define WME_VERSION 1
-+
-+#define WME_ACTION_CODE_SETUP_REQUEST 0
-+#define WME_ACTION_CODE_SETUP_RESPONSE 1
-+#define WME_ACTION_CODE_TEARDOWN 2
-+
-+#define WME_SETUP_RESPONSE_STATUS_ADMISSION_ACCEPTED 0
-+#define WME_SETUP_RESPONSE_STATUS_INVALID_PARAMETERS 1
-+#define WME_SETUP_RESPONSE_STATUS_REFUSED 3
-+
-+#define WME_TSPEC_DIRECTION_UPLINK 0
-+#define WME_TSPEC_DIRECTION_DOWNLINK 1
-+#define WME_TSPEC_DIRECTION_BI_DIRECTIONAL 3
-+
-+
-+#define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+#define OUI_REALTEK	0x00e04c /* Realtek */
-+#endif
-+#define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */
-+
-+enum rtw_ieee80211_rann_flags {
-+	RTW_RANN_FLAG_IS_GATE = 1 << 0,
-+};
-+
-+/**
-+ * enum rtw_ieee80211_preq_flags - mesh PREQ element flags
-+ *
-+ * @RTW_IEEE80211_PREQ_IS_GATE_FLAG: Gate Announcement subfield
-+ * @RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG: proactive PREP subfield
-+ */
-+enum rtw_ieee80211_preq_flags {
-+	RTW_IEEE80211_PREQ_IS_GATE_FLAG = 1 << 0,
-+	RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG	= 1 << 2,
-+};
-+
-+/**
-+ * enum rtw_ieee80211_preq_target_flags - mesh PREQ element per target flags
-+ *
-+ * @RTW_IEEE80211_PREQ_TO_FLAG: target only subfield
-+ * @RTW_IEEE80211_PREQ_USN_FLAG: unknown target HWMP sequence number subfield
-+ */
-+enum rtw_ieee80211_preq_target_flags {
-+	RTW_IEEE80211_PREQ_TO_FLAG	= 1<<0,
-+	RTW_IEEE80211_PREQ_USN_FLAG	= 1<<2,
-+};
-+
-+/**
-+ * enum rtw_ieee80211_root_mode_identifier - root mesh STA mode identifier
-+ *
-+ * These attribute are used by dot11MeshHWMPRootMode to set root mesh STA mode
-+ *
-+ * @RTW_IEEE80211_ROOTMODE_NO_ROOT: the mesh STA is not a root mesh STA (default)
-+ * @RTW_IEEE80211_ROOTMODE_ROOT: the mesh STA is a root mesh STA if greater than
-+ *	this value
-+ * @RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP: the mesh STA is a root mesh STA supports
-+ *	the proactive PREQ with proactive PREP subfield set to 0
-+ * @RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP: the mesh STA is a root mesh STA
-+ *	supports the proactive PREQ with proactive PREP subfield set to 1
-+ * @RTW_IEEE80211_PROACTIVE_RANN: the mesh STA is a root mesh STA supports
-+ *	the proactive RANN
-+ */
-+enum rtw_ieee80211_root_mode_identifier {
-+	RTW_IEEE80211_ROOTMODE_NO_ROOT = 0,
-+	RTW_IEEE80211_ROOTMODE_ROOT = 1,
-+	RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP = 2,
-+	RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP = 3,
-+	RTW_IEEE80211_PROACTIVE_RANN = 4,
-+};
-+
-+/**
-+ * enum rtw_ieee80211_channel_flags - channel flags
-+ *
-+ * Channel flags set by the regulatory control code.
-+ *
-+ * @RTW_IEEE80211_CHAN_DISABLED: This channel is disabled.
-+ * @RTW_IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted
-+ *      on this channel.
-+ * @RTW_IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel.
-+ * @RTW_IEEE80211_CHAN_RADAR: Radar detection is required on this channel.
-+ * @RTW_IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel
-+ *      is not permitted.
-+ * @RTW_IEEE80211_CHAN_NO_HT40MINUS: extension channel below this channel
-+ *      is not permitted.
-+ */
-+enum rtw_ieee80211_channel_flags {
-+	RTW_IEEE80211_CHAN_DISABLED         = 1 << 0,
-+	RTW_IEEE80211_CHAN_PASSIVE_SCAN     = 1 << 1,
-+	RTW_IEEE80211_CHAN_NO_IBSS          = 1 << 2,
-+	RTW_IEEE80211_CHAN_RADAR            = 1 << 3,
-+	RTW_IEEE80211_CHAN_NO_HT40PLUS      = 1 << 4,
-+	RTW_IEEE80211_CHAN_NO_HT40MINUS     = 1 << 5,
-+};
-+
-+#define RTW_IEEE80211_CHAN_NO_HT40 \
-+	(RTW_IEEE80211_CHAN_NO_HT40PLUS | RTW_IEEE80211_CHAN_NO_HT40MINUS)
-+
-+/* Represent channel details, subset of ieee80211_channel */
-+struct rtw_ieee80211_channel {
-+	/* enum ieee80211_band band; */
-+	/* u16 center_freq; */
-+	u16 hw_value;
-+	u32 flags;
-+	/* int max_antenna_gain; */
-+	/* int max_power; */
-+	/* int max_reg_power; */
-+	/* bool beacon_found; */
-+	/* u32 orig_flags; */
-+	/* int orig_mag; */
-+	/* int orig_mpwr; */
-+};
-+
-+#define CHAN_FMT \
-+	/*"band:%d, "*/ \
-+	/*"center_freq:%u, "*/ \
-+	"hw_value:%u, " \
-+	"flags:0x%08x" \
-+	/*"max_antenna_gain:%d\n"*/ \
-+	/*"max_power:%d\n"*/ \
-+	/*"max_reg_power:%d\n"*/ \
-+	/*"beacon_found:%u\n"*/ \
-+	/*"orig_flags:0x%08x\n"*/ \
-+	/*"orig_mag:%d\n"*/ \
-+	/*"orig_mpwr:%d\n"*/
-+
-+#define CHAN_ARG(channel) \
-+	/*(channel)->band*/ \
-+	/*, (channel)->center_freq*/ \
-+	(channel)->hw_value \
-+	, (channel)->flags \
-+	/*, (channel)->max_antenna_gain*/ \
-+	/*, (channel)->max_power*/ \
-+	/*, (channel)->max_reg_power*/ \
-+	/*, (channel)->beacon_found*/ \
-+	/*, (channel)->orig_flags*/ \
-+	/*, (channel)->orig_mag*/ \
-+	/*, (channel)->orig_mpwr*/ \
-+
-+/* Parsed Information Elements */
-+struct rtw_ieee802_11_elems {
-+	u8 *ssid;
-+	u8 ssid_len;
-+	u8 *supp_rates;
-+	u8 supp_rates_len;
-+	u8 *fh_params;
-+	u8 fh_params_len;
-+	u8 *ds_params;
-+	u8 ds_params_len;
-+	u8 *cf_params;
-+	u8 cf_params_len;
-+	u8 *tim;
-+	u8 tim_len;
-+	u8 *ibss_params;
-+	u8 ibss_params_len;
-+	u8 *challenge;
-+	u8 challenge_len;
-+	u8 *erp_info;
-+	u8 erp_info_len;
-+	u8 *ext_supp_rates;
-+	u8 ext_supp_rates_len;
-+	u8 *wpa_ie;
-+	u8 wpa_ie_len;
-+	u8 *rsn_ie;
-+	u8 rsn_ie_len;
-+	u8 *wme;
-+	u8 wme_len;
-+	u8 *wme_tspec;
-+	u8 wme_tspec_len;
-+	u8 *wps_ie;
-+	u8 wps_ie_len;
-+	u8 *power_cap;
-+	u8 power_cap_len;
-+	u8 *supp_channels;
-+	u8 supp_channels_len;
-+	u8 *mdie;
-+	u8 mdie_len;
-+	u8 *ftie;
-+	u8 ftie_len;
-+	u8 *timeout_int;
-+	u8 timeout_int_len;
-+	u8 *ht_capabilities;
-+	u8 ht_capabilities_len;
-+	u8 *ht_operation;
-+	u8 ht_operation_len;
-+	u8 *vendor_ht_cap;
-+	u8 vendor_ht_cap_len;
-+	u8 *vht_capabilities;
-+	u8 vht_capabilities_len;
-+	u8 *vht_operation;
-+	u8 vht_operation_len;
-+	u8 *vht_op_mode_notify;
-+	u8 vht_op_mode_notify_len;
-+	u8 *rm_en_cap;
-+	u8 rm_en_cap_len;
-+#ifdef CONFIG_RTW_MESH
-+	u8 *preq;
-+	u8 preq_len;
-+	u8 *prep;
-+	u8 prep_len;
-+	u8 *perr;
-+	u8 perr_len;
-+	u8 *rann;
-+	u8 rann_len;
-+#endif
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	u8 *tbtx_cap;
-+	u8 tbtx_cap_len;
-+#endif
-+};
-+
-+typedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes;
-+
-+ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len,
-+				struct rtw_ieee802_11_elems *elems,
-+				int show_errors);
-+
-+u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen);
-+u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, const u8 *source, uint *frlen);
-+
-+enum secondary_ch_offset {
-+	SCN = 0, /* no secondary channel */
-+	SCA = 1, /* secondary channel above */
-+	SCB = 3,  /* secondary channel below */
-+};
-+u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset);
-+u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset);
-+u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, u8 new_ch, u8 ch_switch_cnt);
-+u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset);
-+u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence);
-+
-+u8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit);
-+u8 rtw_update_rate_bymode(WLAN_BSSID_EX *pbss_network, u32 mode);
-+
-+u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen);
-+int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len);
-+
-+void rtw_set_supported_rate(u8 *SupportedRates, uint mode) ;
-+
-+#define GET_RSN_CAP_MFP_OPTION(cap)	LE_BITS_TO_2BYTE(((u8 *)(cap)), 6, 2)
-+
-+#define MFP_NO			0
-+#define MFP_INVALID		1
-+#define MFP_OPTIONAL	2
-+#define MFP_REQUIRED	3
-+
-+struct rsne_info {
-+	u8 *gcs;
-+	u16 pcs_cnt;
-+	u8 *pcs_list;
-+	u16 akm_cnt;
-+	u8 *akm_list;
-+	u8 *cap;
-+	u16 pmkid_cnt;
-+	u8 *pmkid_list;
-+	u8 *gmcs;
-+
-+	u8 err;
-+};
-+int rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info);
-+
-+unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit);
-+unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit);
-+int rtw_get_wpa_cipher_suite(u8 *s);
-+int rtw_get_rsn_cipher_suite(u8 *s);
-+int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len);
-+int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, u32 *akm);
-+int rtw_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *gmcs, u32 *akm, u8 *mfp_opt);
-+
-+int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u16 *wpa_len);
-+
-+u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen);
-+u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, enum bss_type frame_type);
-+u8 *rtw_get_wps_ie(const u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen);
-+u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_attr, u32 *len_attr);
-+u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_content, uint *len_content);
-+
-+u8 *rtw_get_owe_ie(const u8 *in_ie, uint in_len, u8 *owe_ie, uint *owe_ielen);
-+
-+/**
-+ * for_each_ie - iterate over continuous IEs
-+ * @ie:
-+ * @buf:
-+ * @buf_len:
-+ */
-+#define for_each_ie(ie, buf, buf_len) \
-+	for (ie = (void *)buf; (((u8 *)ie) - ((u8 *)buf) + 1) < buf_len; ie = (void *)(((u8 *)ie) + *(((u8 *)ie)+1) + 2))
-+
-+void dump_ies(void *sel, const u8 *buf, u32 buf_len);
-+#ifdef CONFIG_RTW_DEBUG
-+
-+#ifdef CONFIG_80211N_HT
-+#define HT_SC_OFFSET_MAX 4
-+extern const char *const _ht_sc_offset_str[];
-+#define ht_sc_offset_str(sc) (((sc) >= HT_SC_OFFSET_MAX) ? _ht_sc_offset_str[2] : _ht_sc_offset_str[(sc)])
-+
-+void dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len);
-+#endif
-+
-+void dump_wps_ie(void *sel, const u8 *ie, u32 ie_len);
-+#endif	/*	CONFIG_RTW_DEBUG	*/
-+
-+void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht);
-+
-+void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht);
-+
-+bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a
-+	, u8 ch_b, u8 bw_b, u8 offset_b);
-+void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset
-+	, u8 *g_ch, u8 *g_bw, u8 *g_offset);
-+
-+#ifdef CONFIG_P2P
-+u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len);
-+int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie);
-+#ifdef CONFIG_RTW_DEBUG
-+void dump_p2p_ie(void *sel, const u8 *ie, u32 ie_len);
-+#endif
-+u8 *rtw_get_p2p_ie(const u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen);
-+u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr);
-+u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content);
-+u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr);
-+uint rtw_del_p2p_ie(u8 *ies, uint ies_len_ori, const char *msg);
-+uint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id);
-+u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen);
-+void rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex);
-+void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id);
-+#endif	/*	CONFIG_P2P	*/
-+
-+uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg);
-+void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex);
-+#ifdef CONFIG_WFD
-+#ifdef CONFIG_RTW_DEBUG
-+void dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len);
-+#endif
-+u8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen);
-+u8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr);
-+u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content);
-+uint rtw_del_wfd_attr(u8 *ie, uint ielen_ori, u8 attr_id);
-+u8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ielen);
-+void rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id);
-+#endif
-+
-+#define MULTI_AP_SUB_ELEM_TYPE 0x06
-+#define MULTI_AP_TEAR_DOWN BIT(4)
-+#define MULTI_AP_FRONTHAUL_BSS BIT(5)
-+#define MULTI_AP_BACKHAUL_BSS BIT(6)
-+#define MULTI_AP_BACKHAUL_STA BIT(7)
-+#ifdef CONFIG_RTW_MULTI_AP
-+void dump_multi_ap_ie(void *sel, const u8 *ie, u32 ie_len);
-+u8 rtw_get_multi_ap_ie_ext(const u8 *ies, int ies_len);
-+u8 *rtw_set_multi_ap_ie_ext(u8 *pbuf, uint *frlen, u8 val);
-+#endif
-+
-+uint	rtw_get_rateset_len(u8	*rateset);
-+
-+struct registry_priv;
-+int rtw_generate_ie(struct registry_priv *pregistrypriv);
-+
-+int rtw_get_bit_value_from_ieee_value(u8 val);
-+
-+uint	rtw_is_cckrates_included(u8 *rate);
-+
-+uint	rtw_is_cckratesonly_included(u8 *rate);
-+uint rtw_get_cckrate_size(u8 *rate,u32 rate_length);
-+int rtw_check_network_type(unsigned char *rate, int ratelen, int channel);
-+
-+u8 rtw_check_invalid_mac_address(u8 *mac_addr, u8 check_local_bit);
-+void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr);
-+
-+u16 rtw_ht_mcs_rate(u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate);
-+u8	rtw_ht_mcsset_to_nss(u8 *supp_mcs_set);
-+u32	rtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss);
-+u8 rtw_ht_cap_get_rx_nss(u8 *ht_cap);
-+u8 rtw_ht_cap_get_tx_nss(u8 *ht_cap);
-+
-+int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8 *category, u8 *action);
-+const char *action_public_str(u8 action);
-+
-+u8 key_2char2num(u8 hch, u8 lch);
-+u8 str_2char2num(u8 hch, u8 lch);
-+void macstr2num(u8 *dst, u8 *src);
-+u8 convert_ip_addr(u8 hch, u8 mch, u8 lch);
-+int wifirate2_ratetbl_inx(unsigned char rate);
-+
-+
-+#endif /* IEEE80211_H */
-diff --git a/drivers/staging/rtl8723cs/include/ieee80211_ext.h b/drivers/staging/rtl8723cs/include/ieee80211_ext.h
-new file mode 100644
-index 000000000000..4965863c4173
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/ieee80211_ext.h
-@@ -0,0 +1,312 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __IEEE80211_EXT_H
-+#define __IEEE80211_EXT_H
-+
-+#include <drv_conf.h>
-+#include <osdep_service.h>
-+#include <drv_types.h>
-+
-+#define WMM_OUI_TYPE 2
-+#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0
-+#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1
-+#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2
-+#define WMM_VERSION 1
-+
-+#define WPA_PROTO_WPA BIT(0)
-+#define WPA_PROTO_RSN BIT(1)
-+
-+#define WPA_KEY_MGMT_IEEE8021X BIT(0)
-+#define WPA_KEY_MGMT_PSK BIT(1)
-+#define WPA_KEY_MGMT_NONE BIT(2)
-+#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)
-+#define WPA_KEY_MGMT_WPA_NONE BIT(4)
-+
-+
-+#define WPA_CAPABILITY_PREAUTH BIT(0)
-+#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6)
-+#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9)
-+
-+
-+#define PMKID_LEN 16
-+
-+
-+#ifdef PLATFORM_LINUX
-+struct wpa_ie_hdr {
-+	u8 elem_id;
-+	u8 len;
-+	u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
-+	u8 version[2]; /* little endian */
-+} __attribute__((packed));
-+
-+struct rsn_ie_hdr {
-+	u8 elem_id; /* WLAN_EID_RSN */
-+	u8 len;
-+	u8 version[2]; /* little endian */
-+} __attribute__((packed));
-+
-+struct wme_ac_parameter {
-+#if defined(CONFIG_LITTLE_ENDIAN)
-+	/* byte 1 */
-+	u8	aifsn:4,
-+	     acm:1,
-+	     aci:2,
-+	     reserved:1;
-+
-+	/* byte 2 */
-+	u8	eCWmin:4,
-+	     eCWmax:4;
-+#elif defined(CONFIG_BIG_ENDIAN)
-+	/* byte 1 */
-+	u8	reserved:1,
-+	     aci:2,
-+	     acm:1,
-+	     aifsn:4;
-+
-+	/* byte 2 */
-+	u8	eCWmax:4,
-+	     eCWmin:4;
-+#else
-+#error	"Please fix <endian.h>"
-+#endif
-+
-+	/* bytes 3 & 4 */
-+	u16 txopLimit;
-+} __attribute__((packed));
-+
-+struct wme_parameter_element {
-+	/* required fields for WME version 1 */
-+	u8 oui[3];
-+	u8 oui_type;
-+	u8 oui_subtype;
-+	u8 version;
-+	u8 acInfo;
-+	u8 reserved;
-+	struct wme_ac_parameter ac[4];
-+
-+} __attribute__((packed));
-+
-+#endif
-+
-+#define WPA_PUT_LE16(a, val)			\
-+	do {					\
-+		(a)[1] = ((u16) (val)) >> 8;	\
-+		(a)[0] = ((u16) (val)) & 0xff;	\
-+	} while (0)
-+
-+#define WPA_PUT_BE32(a, val)					\
-+	do {							\
-+		(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
-+		(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
-+		(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
-+		(a)[3] = (u8) (((u32) (val)) & 0xff);		\
-+	} while (0)
-+
-+#define WPA_PUT_LE32(a, val)					\
-+	do {							\
-+		(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
-+		(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
-+		(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
-+		(a)[0] = (u8) (((u32) (val)) & 0xff);		\
-+	} while (0)
-+
-+#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))
-+/* #define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val)) */
-+
-+
-+
-+/* Action category code */
-+enum ieee80211_category {
-+	WLAN_CATEGORY_SPECTRUM_MGMT = 0,
-+	WLAN_CATEGORY_QOS = 1,
-+	WLAN_CATEGORY_DLS = 2,
-+	WLAN_CATEGORY_BACK = 3,
-+	WLAN_CATEGORY_HT = 7,
-+	WLAN_CATEGORY_WMM = 17,
-+};
-+
-+/* SPECTRUM_MGMT action code */
-+enum ieee80211_spectrum_mgmt_actioncode {
-+	WLAN_ACTION_SPCT_MSR_REQ = 0,
-+	WLAN_ACTION_SPCT_MSR_RPRT = 1,
-+	WLAN_ACTION_SPCT_TPC_REQ = 2,
-+	WLAN_ACTION_SPCT_TPC_RPRT = 3,
-+	WLAN_ACTION_SPCT_CHL_SWITCH = 4,
-+	WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
-+};
-+
-+/* BACK action code */
-+enum ieee80211_back_actioncode {
-+	WLAN_ACTION_ADDBA_REQ = 0,
-+	WLAN_ACTION_ADDBA_RESP = 1,
-+	WLAN_ACTION_DELBA = 2,
-+};
-+
-+/* HT features action code */
-+enum ieee80211_ht_actioncode {
-+	WLAN_ACTION_NOTIFY_CH_WIDTH = 0,
-+	WLAN_ACTION_SM_PS = 1,
-+	WLAN_ACTION_PSPM = 2,
-+	WLAN_ACTION_PCO_PHASE = 3,
-+	WLAN_ACTION_MIMO_CSI_MX = 4,
-+	WLAN_ACTION_MIMO_NONCP_BF = 5,
-+	WLAN_ACTION_MIMP_CP_BF = 6,
-+	WLAN_ACTION_ASEL_INDICATES_FB = 7,
-+	WLAN_ACTION_HI_INFO_EXCHG = 8,
-+};
-+
-+/* BACK (block-ack) parties */
-+enum ieee80211_back_parties {
-+	WLAN_BACK_RECIPIENT = 0,
-+	WLAN_BACK_INITIATOR = 1,
-+	WLAN_BACK_TIMER = 2,
-+};
-+
-+#ifdef PLATFORM_LINUX
-+
-+struct ieee80211_mgmt {
-+	u16 frame_control;
-+	u16 duration;
-+	u8 da[6];
-+	u8 sa[6];
-+	u8 bssid[6];
-+	u16 seq_ctrl;
-+	union {
-+		struct {
-+			u16 auth_alg;
-+			u16 auth_transaction;
-+			u16 status_code;
-+			/* possibly followed by Challenge text */
-+			u8 variable[0];
-+		}  __attribute__((packed)) auth;
-+		struct {
-+			u16 reason_code;
-+		}  __attribute__((packed)) deauth;
-+		struct {
-+			u16 capab_info;
-+			u16 listen_interval;
-+			/* followed by SSID and Supported rates */
-+			u8 variable[0];
-+		}  __attribute__((packed)) assoc_req;
-+		struct {
-+			u16 capab_info;
-+			u16 status_code;
-+			u16 aid;
-+			/* followed by Supported rates */
-+			u8 variable[0];
-+		}  __attribute__((packed)) assoc_resp, reassoc_resp;
-+		struct {
-+			u16 capab_info;
-+			u16 listen_interval;
-+			u8 current_ap[6];
-+			/* followed by SSID and Supported rates */
-+			u8 variable[0];
-+		}  __attribute__((packed)) reassoc_req;
-+		struct {
-+			u16 reason_code;
-+		}  __attribute__((packed)) disassoc;
-+		struct {
-+			__le64 timestamp;
-+			u16 beacon_int;
-+			u16 capab_info;
-+			/* followed by some of SSID, Supported rates,
-+			 * FH Params, DS Params, CF Params, IBSS Params, TIM */
-+			u8 variable[0];
-+		}  __attribute__((packed)) beacon;
-+		struct {
-+			/* only variable items: SSID, Supported rates */
-+			u8 variable[0];
-+		}  __attribute__((packed)) probe_req;
-+		struct {
-+			__le64 timestamp;
-+			u16 beacon_int;
-+			u16 capab_info;
-+			/* followed by some of SSID, Supported rates,
-+			 * FH Params, DS Params, CF Params, IBSS Params */
-+			u8 variable[0];
-+		}  __attribute__((packed)) probe_resp;
-+		struct {
-+			u8 category;
-+			union {
-+				struct {
-+					u8 action_code;
-+					u8 dialog_token;
-+					u8 status_code;
-+					u8 variable[0];
-+				}  __attribute__((packed)) wme_action;
-+#if 0
-+				struct {
-+					u8 action_code;
-+					u8 element_id;
-+					u8 length;
-+					struct ieee80211_channel_sw_ie sw_elem;
-+				}  __attribute__((packed)) chan_switch;
-+				struct {
-+					u8 action_code;
-+					u8 dialog_token;
-+					u8 element_id;
-+					u8 length;
-+					struct ieee80211_msrment_ie msr_elem;
-+				}  __attribute__((packed)) measurement;
-+#endif
-+				struct {
-+					u8 action_code;
-+					u8 dialog_token;
-+					u16 capab;
-+					u16 timeout;
-+					u16 start_seq_num;
-+				}  __attribute__((packed)) addba_req;
-+				struct {
-+					u8 action_code;
-+					u8 dialog_token;
-+					u16 status;
-+					u16 capab;
-+					u16 timeout;
-+				}  __attribute__((packed)) addba_resp;
-+				struct {
-+					u8 action_code;
-+					u16 params;
-+					u16 reason_code;
-+				}  __attribute__((packed)) delba;
-+				struct {
-+					u8 action_code;
-+					/* capab_info for open and confirm,
-+					 * reason for close
-+					 */
-+					u16 aux;
-+					/* Followed in plink_confirm by status
-+					 * code, AID and supported rates,
-+					 * and directly by supported rates in
-+					 * plink_open and plink_close
-+					 */
-+					u8 variable[0];
-+				}  __attribute__((packed)) plink_action;
-+				struct {
-+					u8 action_code;
-+					u8 variable[0];
-+				}  __attribute__((packed)) mesh_action;
-+			} __attribute__((packed)) u;
-+		}  __attribute__((packed)) action;
-+	} __attribute__((packed)) u;
-+} __attribute__((packed));
-+
-+#endif
-+
-+/* mgmt header + 1 byte category code */
-+#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u)
-+
-+
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/if_ether.h b/drivers/staging/rtl8723cs/include/if_ether.h
-new file mode 100644
-index 000000000000..a3007c4ab22d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/if_ether.h
-@@ -0,0 +1,106 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef _LINUX_IF_ETHER_H
-+#define _LINUX_IF_ETHER_H
-+
-+/*
-+ *	IEEE 802.3 Ethernet magic constants.  The frame sizes omit the preamble
-+ *	and FCS/CRC (frame check sequence).
-+ */
-+
-+#define ETH_ALEN	6		/* Octets in one ethernet addr	 */
-+#define ETH_HLEN	14		/* Total octets in header.	 */
-+#define ETH_ZLEN	60		/* Min. octets in frame sans FCS */
-+#define ETH_DATA_LEN	1500		/* Max. octets in payload	 */
-+#define ETH_FRAME_LEN	1514		/* Max. octets in frame sans FCS */
-+
-+/*
-+ *	These are the defined Ethernet Protocol ID's.
-+ */
-+
-+#define ETH_P_LOOP	0x0060		/* Ethernet Loopback packet	*/
-+#define ETH_P_PUP	0x0200		/* Xerox PUP packet		*/
-+#define ETH_P_PUPAT	0x0201		/* Xerox PUP Addr Trans packet	*/
-+#define ETH_P_IP	0x0800		/* Internet Protocol packet	*/
-+#define ETH_P_X25	0x0805		/* CCITT X.25			*/
-+#define ETH_P_ARP	0x0806		/* Address Resolution packet	*/
-+#define	ETH_P_BPQ	0x08FF		/* G8BPQ AX.25 Ethernet Packet	[ NOT AN OFFICIALLY REGISTERED ID ] */
-+#define ETH_P_IEEEPUP	0x0a00		/* Xerox IEEE802.3 PUP packet */
-+#define ETH_P_IEEEPUPAT	0x0a01		/* Xerox IEEE802.3 PUP Addr Trans packet */
-+#define ETH_P_DEC       0x6000          /* DEC Assigned proto          */
-+#define ETH_P_DNA_DL    0x6001          /* DEC DNA Dump/Load           */
-+#define ETH_P_DNA_RC    0x6002          /* DEC DNA Remote Console      */
-+#define ETH_P_DNA_RT    0x6003          /* DEC DNA Routing             */
-+#define ETH_P_LAT       0x6004          /* DEC LAT                     */
-+#define ETH_P_DIAG      0x6005          /* DEC Diagnostics             */
-+#define ETH_P_CUST      0x6006          /* DEC Customer use            */
-+#define ETH_P_SCA       0x6007          /* DEC Systems Comms Arch      */
-+#define ETH_P_RARP      0x8035		/* Reverse Addr Res packet	*/
-+#define ETH_P_ATALK	0x809B		/* Appletalk DDP		*/
-+#define ETH_P_AARP	0x80F3		/* Appletalk AARP		*/
-+#define ETH_P_8021Q	0x8100          /* 802.1Q VLAN Extended Header */
-+#define ETH_P_IPX	0x8137		/* IPX over DIX			*/
-+#define ETH_P_IPV6	0x86DD		/* IPv6 over bluebook		*/
-+#define ETH_P_PPP_DISC	0x8863		/* PPPoE discovery messages    */
-+#define ETH_P_PPP_SES	0x8864		/* PPPoE session messages	*/
-+#define ETH_P_ATMMPOA	0x884c		/* MultiProtocol Over ATM	*/
-+#define ETH_P_ATMFATE	0x8884		/* Frame-based ATM Transport
-+					 * over Ethernet
-+					 */
-+
-+/*
-+ *	Non DIX types. Won't clash for 1500 types.
-+ */
-+
-+#define ETH_P_802_3	0x0001		/* Dummy type for 802.3 frames */
-+#define ETH_P_AX25	0x0002		/* Dummy protocol id for AX.25 */
-+#define ETH_P_ALL	0x0003		/* Every packet (be careful!!!) */
-+#define ETH_P_802_2	0x0004		/* 802.2 frames 		*/
-+#define ETH_P_SNAP	0x0005		/* Internal only		*/
-+#define ETH_P_DDCMP     0x0006          /* DEC DDCMP: Internal only    */
-+#define ETH_P_WAN_PPP   0x0007          /* Dummy type for WAN PPP frames*/
-+#define ETH_P_PPP_MP    0x0008          /* Dummy type for PPP MP frames */
-+#define ETH_P_LOCALTALK 0x0009		/* Localtalk pseudo type 	*/
-+#define ETH_P_PPPTALK	0x0010		/* Dummy type for Atalk over PPP*/
-+#define ETH_P_TR_802_2	0x0011		/* 802.2 frames 		*/
-+#define ETH_P_MOBITEX	0x0015		/* Mobitex (kaz@cafe.net)	*/
-+#define ETH_P_CONTROL	0x0016		/* Card specific control frames */
-+#define ETH_P_IRDA	0x0017		/* Linux-IrDA			*/
-+#define ETH_P_ECONET	0x0018		/* Acorn Econet			*/
-+
-+/*
-+ *	This is an Ethernet frame header.
-+ */
-+
-+struct ethhdr {
-+	unsigned char	h_dest[ETH_ALEN];	/* destination eth addr	*/
-+	unsigned char	h_source[ETH_ALEN];	/* source ether addr	*/
-+	unsigned short	h_proto;		/* packet type ID field	*/
-+};
-+
-+struct _vlan {
-+	unsigned short       h_vlan_TCI;                /* Encapsulates priority and VLAN ID */
-+	unsigned short       h_vlan_encapsulated_proto;
-+};
-+
-+
-+
-+#define get_vlan_id(pvlan) ((ntohs((unsigned short)pvlan->h_vlan_TCI)) & 0xfff)
-+#define get_vlan_priority(pvlan) ((ntohs((unsigned short)pvlan->h_vlan_TCI))>>13)
-+#define get_vlan_encap_proto(pvlan) (ntohs((unsigned short)pvlan->h_vlan_encapsulated_proto))
-+
-+
-+#endif	/* _LINUX_IF_ETHER_H */
-diff --git a/drivers/staging/rtl8723cs/include/ip.h b/drivers/staging/rtl8723cs/include/ip.h
-new file mode 100644
-index 000000000000..4feb98fb072a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/ip.h
-@@ -0,0 +1,135 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _LINUX_IP_H
-+#define _LINUX_IP_H
-+
-+/* SOL_IP socket options */
-+
-+#define IPTOS_TOS_MASK		0x1E
-+#define IPTOS_TOS(tos)		((tos)&IPTOS_TOS_MASK)
-+#define	IPTOS_LOWDELAY		0x10
-+#define	IPTOS_THROUGHPUT	0x08
-+#define	IPTOS_RELIABILITY	0x04
-+#define	IPTOS_MINCOST		0x02
-+
-+#define IPTOS_PREC_MASK		0xE0
-+#define IPTOS_PREC(tos)		((tos)&IPTOS_PREC_MASK)
-+#define IPTOS_PREC_NETCONTROL           0xe0
-+#define IPTOS_PREC_INTERNETCONTROL      0xc0
-+#define IPTOS_PREC_CRITIC_ECP           0xa0
-+#define IPTOS_PREC_FLASHOVERRIDE        0x80
-+#define IPTOS_PREC_FLASH                0x60
-+#define IPTOS_PREC_IMMEDIATE            0x40
-+#define IPTOS_PREC_PRIORITY             0x20
-+#define IPTOS_PREC_ROUTINE              0x00
-+
-+
-+/* IP options */
-+#define IPOPT_COPY		0x80
-+#define IPOPT_CLASS_MASK	0x60
-+#define IPOPT_NUMBER_MASK	0x1f
-+
-+#define	IPOPT_COPIED(o)		((o)&IPOPT_COPY)
-+#define	IPOPT_CLASS(o)		((o)&IPOPT_CLASS_MASK)
-+#define	IPOPT_NUMBER(o)		((o)&IPOPT_NUMBER_MASK)
-+
-+#define	IPOPT_CONTROL		0x00
-+#define	IPOPT_RESERVED1		0x20
-+#define	IPOPT_MEASUREMENT	0x40
-+#define	IPOPT_RESERVED2		0x60
-+
-+#define IPOPT_END	(0 | IPOPT_CONTROL)
-+#define IPOPT_NOOP	(1 | IPOPT_CONTROL)
-+#define IPOPT_SEC	(2 | IPOPT_CONTROL | IPOPT_COPY)
-+#define IPOPT_LSRR	(3 | IPOPT_CONTROL | IPOPT_COPY)
-+#define IPOPT_TIMESTAMP	(4 | IPOPT_MEASUREMENT)
-+#define IPOPT_RR	(7 | IPOPT_CONTROL)
-+#define IPOPT_SID	(8 | IPOPT_CONTROL | IPOPT_COPY)
-+#define IPOPT_SSRR	(9 | IPOPT_CONTROL | IPOPT_COPY)
-+#define IPOPT_RA	(20 | IPOPT_CONTROL | IPOPT_COPY)
-+
-+#define IPVERSION	4
-+#define MAXTTL		255
-+#define IPDEFTTL	64
-+
-+/* struct timestamp, struct route and MAX_ROUTES are removed.
-+
-+   REASONS: it is clear that nobody used them because:
-+   - MAX_ROUTES value was wrong.
-+   - "struct route" was wrong.
-+   - "struct timestamp" had fatally misaligned bitfields and was completely unusable.
-+ */
-+
-+#define IPOPT_OPTVAL 0
-+#define IPOPT_OLEN   1
-+#define IPOPT_OFFSET 2
-+#define IPOPT_MINOFF 4
-+#define MAX_IPOPTLEN 40
-+#define IPOPT_NOP IPOPT_NOOP
-+#define IPOPT_EOL IPOPT_END
-+#define IPOPT_TS  IPOPT_TIMESTAMP
-+
-+#define	IPOPT_TS_TSONLY		0		/* timestamps only */
-+#define	IPOPT_TS_TSANDADDR	1		/* timestamps and addresses */
-+#define	IPOPT_TS_PRESPEC	3		/* specified modules only */
-+
-+#ifdef PLATFORM_LINUX
-+
-+struct ip_options {
-+	__u32		faddr;				/* Saved first hop address */
-+	unsigned char	optlen;
-+	unsigned char srr;
-+	unsigned char rr;
-+	unsigned char ts;
-+	unsigned char is_setbyuser:1,			/* Set by setsockopt?			*/
-+		 is_data:1,			/* Options in __data, rather than skb	*/
-+		 is_strictroute:1,		/* Strict source route			*/
-+		 srr_is_hit:1,			/* Packet destination addr was our one	*/
-+		 is_changed:1,			/* IP checksum more not valid		*/
-+		 rr_needaddr:1,			/* Need to record addr of outgoing dev	*/
-+		 ts_needtime:1,			/* Need to record timestamp		*/
-+		 ts_needaddr:1;			/* Need to record addr of outgoing dev */
-+	unsigned char router_alert;
-+	unsigned char __pad1;
-+	unsigned char __pad2;
-+	unsigned char __data[0];
-+};
-+
-+#define optlength(opt) (sizeof(struct ip_options) + opt->optlen)
-+#endif
-+
-+struct iphdr {
-+#if defined(__LITTLE_ENDIAN_BITFIELD)
-+	__u8	ihl:4,
-+		version:4;
-+#elif defined (__BIG_ENDIAN_BITFIELD)
-+	__u8	version:4,
-+		ihl:4;
-+#else
-+#error	"Please fix <asm/byteorder.h>"
-+#endif
-+	__u8	tos;
-+	__u16	tot_len;
-+	__u16	id;
-+	__u16	frag_off;
-+	__u8	ttl;
-+	__u8	protocol;
-+	__u16	check;
-+	__u32	saddr;
-+	__u32	daddr;
-+	/*The options start here. */
-+};
-+
-+#endif	/* _LINUX_IP_H */
-diff --git a/drivers/staging/rtl8723cs/include/linux/wireless.h b/drivers/staging/rtl8723cs/include/linux/wireless.h
-new file mode 100644
-index 000000000000..c7f4a6c9b66a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/linux/wireless.h
-@@ -0,0 +1,87 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef _LINUX_WIRELESS_H
-+#define _LINUX_WIRELESS_H
-+
-+/***************************** INCLUDES *****************************/
-+
-+#if 0
-+	#include <linux/types.h>		/* for __u* and __s* typedefs */
-+	#include <linux/socket.h>		/* for "struct sockaddr" et al	*/
-+	#include <linux/if.h>			/* for IFNAMSIZ and co... */
-+#else
-+	#define __user
-+	/* typedef uint16_t	__u16; */
-+	#include <sys/socket.h>			/* for "struct sockaddr" et al	*/
-+	#include <net/if.h>			/* for IFNAMSIZ and co... */
-+#endif
-+
-+/****************************** TYPES ******************************/
-+#ifdef CONFIG_COMPAT
-+struct compat_iw_point {
-+	compat_caddr_t pointer;
-+	__u16 length;
-+	__u16 flags;
-+};
-+#endif
-+/* --------------------------- SUBTYPES --------------------------- */
-+/*
-+ *	For all data larger than 16 octets, we need to use a
-+ *	pointer to memory allocated in user space.
-+ */
-+struct	iw_point {
-+	void __user	*pointer;	/* Pointer to the data  (in user space) */
-+	__u16		length;		/* number of fields or size in bytes */
-+	__u16		flags;		/* Optional params */
-+};
-+
-+
-+/* ------------------------ IOCTL REQUEST ------------------------ */
-+/*
-+ * This structure defines the payload of an ioctl, and is used
-+ * below.
-+ *
-+ * Note that this structure should fit on the memory footprint
-+ * of iwreq (which is the same as ifreq), which mean a max size of
-+ * 16 octets = 128 bits. Warning, pointers might be 64 bits wide...
-+ * You should check this when increasing the structures defined
-+ * above in this file...
-+ */
-+union	iwreq_data {
-+	/* Config - generic */
-+	char		name[IFNAMSIZ];
-+	/* Name : used to verify the presence of  wireless extensions.
-+	 * Name of the protocol/provider... */
-+
-+	struct iw_point	data;		/* Other large parameters */
-+};
-+
-+/*
-+ * The structure to exchange data for ioctl.
-+ * This structure is the same as 'struct ifreq', but (re)defined for
-+ * convenience...
-+ * Do I need to remind you about structure size (32 octets) ?
-+ */
-+struct	iwreq {
-+	union {
-+		char	ifrn_name[IFNAMSIZ];	/* if name, e.g. "eth0" */
-+	} ifr_ifrn;
-+
-+	/* Data part (defined just above) */
-+	union	iwreq_data	u;
-+};
-+
-+#endif	/* _LINUX_WIRELESS_H */
-diff --git a/drivers/staging/rtl8723cs/include/mlme_osdep.h b/drivers/staging/rtl8723cs/include/mlme_osdep.h
-new file mode 100644
-index 000000000000..131eb092560f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/mlme_osdep.h
-@@ -0,0 +1,25 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef	__MLME_OSDEP_H_
-+#define __MLME_OSDEP_H_
-+
-+extern void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated);
-+extern void rtw_os_indicate_connect(_adapter *adapter);
-+void rtw_os_indicate_scan_done(_adapter *padapter, bool aborted);
-+extern void rtw_report_sec_ie(_adapter *adapter, u8 authmode, u8 *sec_ie);
-+
-+void rtw_reset_securitypriv(_adapter *adapter);
-+
-+#endif /* _MLME_OSDEP_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/nic_spec.h b/drivers/staging/rtl8723cs/include/nic_spec.h
-new file mode 100644
-index 000000000000..913ef9ba801a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/nic_spec.h
-@@ -0,0 +1,41 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+#ifndef __NIC_SPEC_H__
-+#define __NIC_SPEC_H__
-+
-+#include <drv_conf.h>
-+
-+#define RTL8711_MCTRL_		(0x20000)
-+#define RTL8711_UART_		(0x30000)
-+#define RTL8711_TIMER_		(0x40000)
-+#define RTL8711_FINT_		(0x50000)
-+#define RTL8711_HINT_		(0x50000)
-+#define RTL8711_GPIO_		(0x60000)
-+#define RTL8711_WLANCTRL_	(0x200000)
-+#define RTL8711_WLANFF_		(0xe00000)
-+#define RTL8711_HCICTRL_	(0x600000)
-+#define RTL8711_SYSCFG_		(0x620000)
-+#define RTL8711_SYSCTRL_	(0x620000)
-+#define RTL8711_MCCTRL_		(0x020000)
-+
-+
-+#include <rtl8711_regdef.h>
-+
-+#include <rtl8711_bitdef.h>
-+
-+
-+#endif /* __RTL8711_SPEC_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/osdep_intf.h b/drivers/staging/rtl8723cs/include/osdep_intf.h
-new file mode 100644
-index 000000000000..63e535ee5ab7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/osdep_intf.h
-@@ -0,0 +1,143 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __OSDEP_INTF_H_
-+#define __OSDEP_INTF_H_
-+
-+
-+struct intf_priv {
-+
-+	u8 *intf_dev;
-+	u32	max_iosz;	/* USB2.0: 128, USB1.1: 64, SDIO:64 */
-+	u32	max_xmitsz; /* USB2.0: unlimited, SDIO:512 */
-+	u32	max_recvsz; /* USB2.0: unlimited, SDIO:512 */
-+
-+	volatile u8 *io_rwmem;
-+	volatile u8 *allocated_io_rwmem;
-+	u32	io_wsz; /* unit: 4bytes */
-+	u32	io_rsz;/* unit: 4bytes */
-+	u8 intf_status;
-+
-+	void (*_bus_io)(u8 *priv);
-+
-+	/*
-+	Under Sync. IRP (SDIO/USB)
-+	A protection mechanism is necessary for the io_rwmem(read/write protocol)
-+
-+	Under Async. IRP (SDIO/USB)
-+	The protection mechanism is through the pending queue.
-+	*/
-+
-+	_mutex ioctl_mutex;
-+
-+
-+#ifdef PLATFORM_LINUX
-+#ifdef CONFIG_USB_HCI
-+	/* when in USB, IO is through interrupt in/out endpoints */
-+	struct usb_device	*udev;
-+	PURB	piorw_urb;
-+	u8 io_irp_cnt;
-+	u8 bio_irp_pending;
-+	_sema io_retevt;
-+	_timer	io_timer;
-+	u8 bio_irp_timeout;
-+	u8 bio_timer_cancel;
-+#endif
-+#endif
-+
-+};
-+
-+struct dvobj_priv *devobj_init(void);
-+void devobj_deinit(struct dvobj_priv *pdvobj);
-+
-+u8 rtw_init_drv_sw(_adapter *padapter);
-+u8 rtw_free_drv_sw(_adapter *padapter);
-+u8 rtw_reset_drv_sw(_adapter *padapter);
-+void rtw_dev_unload(PADAPTER padapter);
-+
-+u32 rtw_start_drv_threads(_adapter *padapter);
-+void rtw_stop_drv_threads(_adapter *padapter);
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+void rtw_cancel_dynamic_chk_timer(_adapter *padapter);
-+#endif
-+void rtw_cancel_all_timer(_adapter *padapter);
-+
-+uint loadparam(_adapter *adapter);
-+
-+#ifdef PLATFORM_LINUX
-+int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
-+
-+int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname);
-+struct net_device *rtw_init_netdev(_adapter *padapter);
-+
-+void rtw_os_ndev_free(_adapter *adapter);
-+int rtw_os_ndev_init(_adapter *adapter, const char *name);
-+void rtw_os_ndev_deinit(_adapter *adapter);
-+void rtw_os_ndev_unregister(_adapter *adapter);
-+void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj);
-+int rtw_os_ndevs_init(struct dvobj_priv *dvobj);
-+void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj);
-+
-+u16 rtw_os_recv_select_queue(u8 *msdu, enum rtw_rx_llc_hdl llc_hdl);
-+
-+int rtw_ndev_notifier_register(void);
-+void rtw_ndev_notifier_unregister(void);
-+void rtw_inetaddr_notifier_register(void);
-+void rtw_inetaddr_notifier_unregister(void);
-+
-+#include "../os_dep/linux/rtw_proc.h"
-+#include "../os_dep/linux/nlrtw.h"
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+#include "../os_dep/linux/custom_multiap_intfs/custom_multiap_intfs.h"
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	#include "../os_dep/linux/ioctl_cfg80211.h"
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+u8 rtw_rtnl_lock_needed(struct dvobj_priv *dvobj);
-+void rtw_set_rtnl_lock_holder(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl);
-+
-+#endif /* PLATFORM_LINUX */
-+
-+
-+#ifdef PLATFORM_FREEBSD
-+extern int rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
-+#endif
-+
-+void rtw_ips_dev_unload(_adapter *padapter);
-+
-+#ifdef CONFIG_IPS
-+int rtw_ips_pwr_up(_adapter *padapter);
-+void rtw_ips_pwr_down(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+struct _io_ops;
-+struct dvobj_priv;
-+_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, void (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops));
-+void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj);
-+void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj);
-+#endif
-+
-+void rtw_ndev_destructor(_nic_hdl ndev);
-+#ifdef CONFIG_ARP_KEEP_ALIVE
-+int rtw_gw_addr_query(_adapter *padapter);
-+#endif
-+
-+int rtw_suspend_common(_adapter *padapter);
-+int rtw_resume_common(_adapter *padapter);
-+
-+#endif /* _OSDEP_INTF_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/osdep_service.h b/drivers/staging/rtl8723cs/include/osdep_service.h
-new file mode 100644
-index 000000000000..4ec16b564f0f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/osdep_service.h
-@@ -0,0 +1,887 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __OSDEP_SERVICE_H_
-+#define __OSDEP_SERVICE_H_
-+
-+
-+#define _FAIL					0
-+#define _SUCCESS				1
-+#define RTW_RX_HANDLED			2
-+#define RTW_RFRAME_UNAVAIL		3
-+#define RTW_RFRAME_PKT_UNAVAIL	4
-+#define RTW_RBUF_UNAVAIL		5
-+#define RTW_RBUF_PKT_UNAVAIL	6
-+#define RTW_SDIO_READ_PORT_FAIL	7
-+#define RTW_ALREADY				8
-+#define RTW_RA_RESOLVING		9
-+#define RTW_BMC_NO_NEED			10
-+#define RTW_XBUF_UNAVAIL		11
-+#define RTW_TX_BALANCE			12
-+#define RTW_TX_WAIT_MORE_FRAME	13
-+#define RTW_QUEUE_MGMT 14
-+
-+/* #define RTW_STATUS_TIMEDOUT -110 */
-+
-+#undef _TRUE
-+#define _TRUE		1
-+
-+#undef _FALSE
-+#define _FALSE		0
-+
-+
-+#ifdef PLATFORM_FREEBSD
-+	#include <osdep_service_bsd.h>
-+#endif
-+
-+#ifdef PLATFORM_LINUX
-+	#include <linux/version.h>
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0))
-+	#include <linux/sched/signal.h>
-+	#include <linux/sched/types.h>
-+#endif
-+	#include <osdep_service_linux.h>
-+	#include <drv_types_linux.h>
-+#endif
-+
-+#ifdef PLATFORM_OS_XP
-+	#include <osdep_service_xp.h>
-+	#include <drv_types_xp.h>
-+#endif
-+
-+#ifdef PLATFORM_OS_CE
-+	#include <osdep_service_ce.h>
-+	#include <drv_types_ce.h>
-+#endif
-+
-+/* #include <rtw_byteorder.h> */
-+
-+#ifndef BIT
-+	#define BIT(x)	(1 << (x))
-+#endif
-+#ifndef BIT_ULL
-+#define BIT_ULL(x)	(1ULL << (x))
-+#endif
-+
-+#define CHECK_BIT(a, b) (!!((a) & (b)))
-+
-+#define BIT0	0x00000001
-+#define BIT1	0x00000002
-+#define BIT2	0x00000004
-+#define BIT3	0x00000008
-+#define BIT4	0x00000010
-+#define BIT5	0x00000020
-+#define BIT6	0x00000040
-+#define BIT7	0x00000080
-+#define BIT8	0x00000100
-+#define BIT9	0x00000200
-+#define BIT10	0x00000400
-+#define BIT11	0x00000800
-+#define BIT12	0x00001000
-+#define BIT13	0x00002000
-+#define BIT14	0x00004000
-+#define BIT15	0x00008000
-+#define BIT16	0x00010000
-+#define BIT17	0x00020000
-+#define BIT18	0x00040000
-+#define BIT19	0x00080000
-+#define BIT20	0x00100000
-+#define BIT21	0x00200000
-+#define BIT22	0x00400000
-+#define BIT23	0x00800000
-+#define BIT24	0x01000000
-+#define BIT25	0x02000000
-+#define BIT26	0x04000000
-+#define BIT27	0x08000000
-+#define BIT28	0x10000000
-+#define BIT29	0x20000000
-+#define BIT30	0x40000000
-+#define BIT31	0x80000000
-+#define BIT32	0x0100000000
-+#define BIT33	0x0200000000
-+#define BIT34	0x0400000000
-+#define BIT35	0x0800000000
-+#define BIT36	0x1000000000
-+
-+#ifndef GENMASK
-+#define GENMASK(h, l) \
-+	(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
-+#endif
-+
-+extern int RTW_STATUS_CODE(int error_code);
-+
-+#ifndef RTK_DMP_PLATFORM
-+	#define CONFIG_USE_VMALLOC
-+#endif
-+
-+/* flags used for rtw_mstat_update() */
-+enum mstat_f {
-+	/* type: 0x00ff */
-+	MSTAT_TYPE_VIR = 0x00,
-+	MSTAT_TYPE_PHY = 0x01,
-+	MSTAT_TYPE_SKB = 0x02,
-+	MSTAT_TYPE_USB = 0x03,
-+	MSTAT_TYPE_MAX = 0x04,
-+
-+	/* func: 0xff00 */
-+	MSTAT_FUNC_UNSPECIFIED = 0x00 << 8,
-+	MSTAT_FUNC_IO = 0x01 << 8,
-+	MSTAT_FUNC_TX_IO = 0x02 << 8,
-+	MSTAT_FUNC_RX_IO = 0x03 << 8,
-+	MSTAT_FUNC_TX = 0x04 << 8,
-+	MSTAT_FUNC_RX = 0x05 << 8,
-+	MSTAT_FUNC_CFG_VENDOR = 0x06 << 8,
-+	MSTAT_FUNC_MAX = 0x07 << 8,
-+};
-+
-+#define mstat_tf_idx(flags) ((flags) & 0xff)
-+#define mstat_ff_idx(flags) (((flags) & 0xff00) >> 8)
-+
-+typedef enum mstat_status {
-+	MSTAT_ALLOC_SUCCESS = 0,
-+	MSTAT_ALLOC_FAIL,
-+	MSTAT_FREE
-+} MSTAT_STATUS;
-+
-+#ifdef DBG_MEM_ALLOC
-+void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz);
-+void rtw_mstat_dump(void *sel);
-+bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size);
-+void *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
-+void *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
-+void dbg_rtw_vmfree(void *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line);
-+void *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
-+void *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
-+void dbg_rtw_mfree(void *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line);
-+
-+struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, const int line);
-+void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
-+struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
-+struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
-+int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
-+#ifdef CONFIG_RTW_NAPI
-+int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
-+#ifdef CONFIG_RTW_GRO
-+gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
-+#endif
-+#endif /* CONFIG_RTW_NAPI */
-+void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line);
-+#ifdef CONFIG_USB_HCI
-+void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, const int line);
-+void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, const int line);
-+#endif /* CONFIG_USB_HCI */
-+
-+#ifdef CONFIG_USE_VMALLOC
-+#define rtw_vmalloc(sz)			dbg_rtw_vmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
-+#define rtw_zvmalloc(sz)			dbg_rtw_zvmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
-+#define rtw_vmfree(pbuf, sz)		dbg_rtw_vmfree((pbuf), (sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
-+#define rtw_vmalloc_f(sz, mstat_f)			dbg_rtw_vmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
-+#define rtw_zvmalloc_f(sz, mstat_f)		dbg_rtw_zvmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
-+#define rtw_vmfree_f(pbuf, sz, mstat_f)	dbg_rtw_vmfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
-+#else /* CONFIG_USE_VMALLOC */
-+#define rtw_vmalloc(sz)			dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
-+#define rtw_zvmalloc(sz)			dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
-+#define rtw_vmfree(pbuf, sz)		dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
-+#define rtw_vmalloc_f(sz, mstat_f)			dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
-+#define rtw_zvmalloc_f(sz, mstat_f)		dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
-+#define rtw_vmfree_f(pbuf, sz, mstat_f)	dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
-+#endif /* CONFIG_USE_VMALLOC */
-+#define rtw_malloc(sz)			dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
-+#define rtw_zmalloc(sz)			dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
-+#define rtw_mfree(pbuf, sz)		dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
-+#define rtw_malloc_f(sz, mstat_f)			dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
-+#define rtw_zmalloc_f(sz, mstat_f)			dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
-+#define rtw_mfree_f(pbuf, sz, mstat_f)		dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
-+
-+#define rtw_skb_alloc(size)	dbg_rtw_skb_alloc((size), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+#define rtw_skb_free(skb)	dbg_rtw_skb_free((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+#define rtw_skb_alloc_f(size, mstat_f)	dbg_rtw_skb_alloc((size), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+#define rtw_skb_free_f(skb, mstat_f)	dbg_rtw_skb_free((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+#define rtw_skb_copy(skb)	dbg_rtw_skb_copy((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+#define rtw_skb_clone(skb)	dbg_rtw_skb_clone((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+#define rtw_skb_copy_f(skb, mstat_f)	dbg_rtw_skb_copy((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+#define rtw_skb_clone_f(skb, mstat_f)	dbg_rtw_skb_clone((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+#define rtw_netif_rx(ndev, skb)	dbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+#ifdef CONFIG_RTW_NAPI
-+#define rtw_netif_receive_skb(ndev, skb) dbg_rtw_netif_receive_skb(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+#ifdef CONFIG_RTW_GRO
-+#define rtw_napi_gro_receive(napi, skb) dbg_rtw_napi_gro_receive(napi, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+#endif
-+#endif /* CONFIG_RTW_NAPI */
-+#define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+#ifdef CONFIG_USB_HCI
-+#define rtw_usb_buffer_alloc(dev, size, dma)		dbg_rtw_usb_buffer_alloc((dev), (size), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
-+#define rtw_usb_buffer_free(dev, size, addr, dma)	dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
-+#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f)			dbg_rtw_usb_buffer_alloc((dev), (size), (dma), ((mstat_f) & 0xff00) | MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
-+#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f)	dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), ((mstat_f) & 0xff00) | MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
-+#endif /* CONFIG_USB_HCI */
-+
-+#else /* DBG_MEM_ALLOC */
-+#define rtw_mstat_update(flag, status, sz) do {} while (0)
-+#define rtw_mstat_dump(sel) do {} while (0)
-+#define match_mstat_sniff_rules(flags, size) _FALSE
-+void *_rtw_vmalloc(u32 sz);
-+void *_rtw_zvmalloc(u32 sz);
-+void _rtw_vmfree(void *pbuf, u32 sz);
-+void *_rtw_zmalloc(u32 sz);
-+void *_rtw_malloc(u32 sz);
-+void _rtw_mfree(void *pbuf, u32 sz);
-+
-+struct sk_buff *_rtw_skb_alloc(u32 sz);
-+void _rtw_skb_free(struct sk_buff *skb);
-+struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb);
-+struct sk_buff *_rtw_skb_clone(struct sk_buff *skb);
-+int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb);
-+#ifdef CONFIG_RTW_NAPI
-+int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb);
-+#ifdef CONFIG_RTW_GRO
-+gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb);
-+#endif
-+#endif /* CONFIG_RTW_NAPI */
-+void _rtw_skb_queue_purge(struct sk_buff_head *list);
-+
-+#ifdef CONFIG_USB_HCI
-+void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma);
-+void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma);
-+#endif /* CONFIG_USB_HCI */
-+
-+#ifdef CONFIG_USE_VMALLOC
-+#define rtw_vmalloc(sz)			_rtw_vmalloc((sz))
-+#define rtw_zvmalloc(sz)			_rtw_zvmalloc((sz))
-+#define rtw_vmfree(pbuf, sz)		_rtw_vmfree((pbuf), (sz))
-+#define rtw_vmalloc_f(sz, mstat_f)			_rtw_vmalloc((sz))
-+#define rtw_zvmalloc_f(sz, mstat_f)		_rtw_zvmalloc((sz))
-+#define rtw_vmfree_f(pbuf, sz, mstat_f)	_rtw_vmfree((pbuf), (sz))
-+#else /* CONFIG_USE_VMALLOC */
-+#define rtw_vmalloc(sz)			_rtw_malloc((sz))
-+#define rtw_zvmalloc(sz)			_rtw_zmalloc((sz))
-+#define rtw_vmfree(pbuf, sz)		_rtw_mfree((pbuf), (sz))
-+#define rtw_vmalloc_f(sz, mstat_f)			_rtw_malloc((sz))
-+#define rtw_zvmalloc_f(sz, mstat_f)		_rtw_zmalloc((sz))
-+#define rtw_vmfree_f(pbuf, sz, mstat_f)	_rtw_mfree((pbuf), (sz))
-+#endif /* CONFIG_USE_VMALLOC */
-+#define rtw_malloc(sz)			_rtw_malloc((sz))
-+#define rtw_zmalloc(sz)			_rtw_zmalloc((sz))
-+#define rtw_mfree(pbuf, sz)		_rtw_mfree((pbuf), (sz))
-+#define rtw_malloc_f(sz, mstat_f)			_rtw_malloc((sz))
-+#define rtw_zmalloc_f(sz, mstat_f)			_rtw_zmalloc((sz))
-+#define rtw_mfree_f(pbuf, sz, mstat_f)		_rtw_mfree((pbuf), (sz))
-+
-+#define rtw_skb_alloc(size) _rtw_skb_alloc((size))
-+#define rtw_skb_free(skb) _rtw_skb_free((skb))
-+#define rtw_skb_alloc_f(size, mstat_f)	_rtw_skb_alloc((size))
-+#define rtw_skb_free_f(skb, mstat_f)	_rtw_skb_free((skb))
-+#define rtw_skb_copy(skb)	_rtw_skb_copy((skb))
-+#define rtw_skb_clone(skb)	_rtw_skb_clone((skb))
-+#define rtw_skb_copy_f(skb, mstat_f)	_rtw_skb_copy((skb))
-+#define rtw_skb_clone_f(skb, mstat_f)	_rtw_skb_clone((skb))
-+#define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb)
-+#ifdef CONFIG_RTW_NAPI
-+#define rtw_netif_receive_skb(ndev, skb) _rtw_netif_receive_skb(ndev, skb)
-+#ifdef CONFIG_RTW_GRO
-+#define rtw_napi_gro_receive(napi, skb) _rtw_napi_gro_receive(napi, skb)
-+#endif
-+#endif /* CONFIG_RTW_NAPI */
-+#define rtw_skb_queue_purge(sk_buff_head) _rtw_skb_queue_purge(sk_buff_head)
-+#ifdef CONFIG_USB_HCI
-+#define rtw_usb_buffer_alloc(dev, size, dma) _rtw_usb_buffer_alloc((dev), (size), (dma))
-+#define rtw_usb_buffer_free(dev, size, addr, dma) _rtw_usb_buffer_free((dev), (size), (addr), (dma))
-+#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) _rtw_usb_buffer_alloc((dev), (size), (dma))
-+#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) _rtw_usb_buffer_free((dev), (size), (addr), (dma))
-+#endif /* CONFIG_USB_HCI */
-+#endif /* DBG_MEM_ALLOC */
-+
-+extern void	*rtw_malloc2d(int h, int w, size_t size);
-+extern void	rtw_mfree2d(void *pbuf, int h, int w, int size);
-+
-+void rtw_os_pkt_free(_pkt *pkt);
-+_pkt *rtw_os_pkt_copy(_pkt *pkt);
-+void *rtw_os_pkt_data(_pkt *pkt);
-+u32 rtw_os_pkt_len(_pkt *pkt);
-+
-+extern void	_rtw_memcpy(void *dec, const void *sour, u32 sz);
-+extern void _rtw_memmove(void *dst, const void *src, u32 sz);
-+extern int	_rtw_memcmp(const void *dst, const void *src, u32 sz);
-+extern int _rtw_memcmp2(const void *dst, const void *src, u32 sz);
-+extern void	_rtw_memset(void *pbuf, int c, u32 sz);
-+
-+extern void	_rtw_init_listhead(_list *list);
-+extern u32	rtw_is_list_empty(_list *phead);
-+extern void	rtw_list_insert_head(_list *plist, _list *phead);
-+extern void	rtw_list_insert_tail(_list *plist, _list *phead);
-+void rtw_list_splice(_list *list, _list *head);
-+void rtw_list_splice_init(_list *list, _list *head);
-+void rtw_list_splice_tail(_list *list, _list *head);
-+
-+#ifndef PLATFORM_FREEBSD
-+extern void	rtw_list_delete(_list *plist);
-+#endif /* PLATFORM_FREEBSD */
-+
-+void rtw_hlist_head_init(rtw_hlist_head *h);
-+void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h);
-+void rtw_hlist_del(rtw_hlist_node *n);
-+void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h);
-+void rtw_hlist_del_rcu(rtw_hlist_node *n);
-+
-+extern void	_rtw_init_sema(_sema *sema, int init_val);
-+extern void	_rtw_free_sema(_sema	*sema);
-+extern void	_rtw_up_sema(_sema	*sema);
-+extern u32	_rtw_down_sema(_sema *sema);
-+extern void	_rtw_mutex_init(_mutex *pmutex);
-+extern void	_rtw_mutex_free(_mutex *pmutex);
-+#ifndef PLATFORM_FREEBSD
-+extern void	_rtw_spinlock_init(_lock *plock);
-+#endif /* PLATFORM_FREEBSD */
-+extern void	_rtw_spinlock_free(_lock *plock);
-+extern void	_rtw_spinlock(_lock	*plock);
-+extern void	_rtw_spinunlock(_lock	*plock);
-+extern void	_rtw_spinlock_ex(_lock	*plock);
-+extern void	_rtw_spinunlock_ex(_lock	*plock);
-+
-+extern void	_rtw_init_queue(_queue *pqueue);
-+extern void _rtw_deinit_queue(_queue *pqueue);
-+extern u32	_rtw_queue_empty(_queue	*pqueue);
-+extern u32	rtw_end_of_queue_search(_list *queue, _list *pelement);
-+
-+extern systime _rtw_get_current_time(void);
-+extern u32	_rtw_systime_to_ms(systime stime);
-+extern systime _rtw_ms_to_systime(u32 ms);
-+extern systime _rtw_us_to_systime(u32 us);
-+extern s32	_rtw_get_passing_time_ms(systime start);
-+extern s32 _rtw_get_remaining_time_ms(systime end);
-+extern s32	_rtw_get_time_interval_ms(systime start, systime end);
-+extern bool _rtw_time_after(systime a, systime b);
-+
-+#ifdef DBG_SYSTIME
-+#define rtw_get_current_time() ({systime __stime = _rtw_get_current_time(); __stime;})
-+#define rtw_systime_to_ms(stime) ({u32 __ms = _rtw_systime_to_ms(stime); typecheck(systime, stime); __ms;})
-+#define rtw_ms_to_systime(ms) ({systime __stime = _rtw_ms_to_systime(ms); __stime;})
-+#define rtw_us_to_systime(us) ({systime __stime = _rtw_us_to_systime(us); __stime;})
-+#define rtw_get_passing_time_ms(start) ({u32 __ms = _rtw_get_passing_time_ms(start); typecheck(systime, start); __ms;})
-+#define rtw_get_remaining_time_ms(end) ({u32 __ms = _rtw_get_remaining_time_ms(end); typecheck(systime, end); __ms;})
-+#define rtw_get_time_interval_ms(start, end) ({u32 __ms = _rtw_get_time_interval_ms(start, end); typecheck(systime, start); typecheck(systime, end); __ms;})
-+#define rtw_time_after(a,b) ({bool __r = _rtw_time_after(a,b); typecheck(systime, a); typecheck(systime, b); __r;})
-+#define rtw_time_before(a,b) ({bool __r = _rtw_time_after(b, a); typecheck(systime, a); typecheck(systime, b); __r;})
-+#else
-+#define rtw_get_current_time() _rtw_get_current_time()
-+#define rtw_systime_to_ms(stime) _rtw_systime_to_ms(stime)
-+#define rtw_ms_to_systime(ms) _rtw_ms_to_systime(ms)
-+#define rtw_us_to_systime(us) _rtw_us_to_systime(us)
-+#define rtw_get_passing_time_ms(start) _rtw_get_passing_time_ms(start)
-+#define rtw_get_remaining_time_ms(end) _rtw_get_remaining_time_ms(end)
-+#define rtw_get_time_interval_ms(start, end) _rtw_get_time_interval_ms(start, end)
-+#define rtw_time_after(a,b) _rtw_time_after(a,b)
-+#define rtw_time_before(a,b) _rtw_time_after(b,a)
-+#endif
-+
-+sysptime rtw_sptime_get(void);
-+sysptime rtw_sptime_set(s64 secs, const u32 nsecs);
-+sysptime rtw_sptime_zero(void);
-+
-+int rtw_sptime_cmp(const sysptime cmp1, const sysptime cmp2);
-+bool rtw_sptime_eql(const sysptime cmp1, const sysptime cmp2);
-+bool rtw_sptime_is_zero(const sysptime sptime);
-+sysptime rtw_sptime_sub(const sysptime lhs, const sysptime rhs);
-+sysptime rtw_sptime_add(const sysptime lhs, const sysptime rhs);
-+
-+s64 rtw_sptime_to_ms(const sysptime sptime);
-+sysptime rtw_ms_to_sptime(u64 ms);
-+s64 rtw_sptime_to_us(const sysptime sptime);
-+sysptime rtw_us_to_sptime(u64 us);
-+s64 rtw_sptime_to_ns(const sysptime sptime);
-+sysptime rtw_ns_to_sptime(u64 ns);
-+
-+s64 rtw_sptime_diff_ms(const sysptime start, const sysptime end);
-+s64 rtw_sptime_pass_ms(const sysptime start);
-+s64 rtw_sptime_diff_us(const sysptime start, const sysptime end);
-+s64 rtw_sptime_pass_us(const sysptime start);
-+s64 rtw_sptime_diff_ns(const sysptime start, const sysptime end);
-+s64 rtw_sptime_pass_ns(const sysptime start);
-+
-+extern void	rtw_sleep_schedulable(int ms);
-+
-+extern void	rtw_msleep_os(int ms);
-+extern void	rtw_usleep_os(int us);
-+
-+extern u32	rtw_atoi(u8 *s);
-+
-+#ifdef DBG_DELAY_OS
-+#define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__)
-+#define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__)
-+extern void _rtw_mdelay_os(int ms, const char *func, const int line);
-+extern void _rtw_udelay_os(int us, const char *func, const int line);
-+#else
-+extern void	rtw_mdelay_os(int ms);
-+extern void	rtw_udelay_os(int us);
-+#endif
-+
-+extern void rtw_yield_os(void);
-+
-+enum rtw_pwait_type {
-+	RTW_PWAIT_TYPE_MSLEEP,
-+	RTW_PWAIT_TYPE_USLEEP,
-+	RTW_PWAIT_TYPE_YIELD,
-+	RTW_PWAIT_TYPE_MDELAY,
-+	RTW_PWAIT_TYPE_UDELAY,
-+
-+	RTW_PWAIT_TYPE_NUM,
-+};
-+
-+#define RTW_PWAIT_TYPE_VALID(type) (type < RTW_PWAIT_TYPE_NUM)
-+
-+struct rtw_pwait_conf {
-+	enum rtw_pwait_type type;
-+	s32 wait_time;
-+	s32 wait_cnt_lmt;
-+};
-+
-+struct rtw_pwait_ctx {
-+	struct rtw_pwait_conf conf;
-+	s32 wait_cnt;
-+	void (*wait_hdl)(int us);
-+};
-+
-+extern const char *_rtw_pwait_type_str[];
-+#define rtw_pwait_type_str(type) (RTW_PWAIT_TYPE_VALID(type) ? _rtw_pwait_type_str[type] : _rtw_pwait_type_str[RTW_PWAIT_TYPE_NUM])
-+
-+#define rtw_pwctx_reset(pwctx) (pwctx)->wait_cnt = 0
-+#define rtw_pwctx_wait(pwctx) do { (pwctx)->wait_hdl((pwctx)->conf.wait_time); (pwctx)->wait_cnt++; } while(0)
-+#define rtw_pwctx_waited(pwctx) ((pwctx)->wait_cnt)
-+#define rtw_pwctx_exceed(pwctx) ((pwctx)->conf.wait_cnt_lmt >= 0 && (pwctx)->wait_cnt >= (pwctx)->conf.wait_cnt_lmt)
-+
-+int rtw_pwctx_config(struct rtw_pwait_ctx *pwctx, enum rtw_pwait_type type, s32 time, s32 cnt_lmt);
-+
-+extern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx);
-+
-+
-+__inline static unsigned char _cancel_timer_ex(_timer *ptimer)
-+{
-+	u8 bcancelled;
-+
-+	_cancel_timer(ptimer, &bcancelled);
-+
-+	return bcancelled;
-+}
-+
-+static __inline void thread_enter(char *name)
-+{
-+#ifdef PLATFORM_LINUX
-+	allow_signal(SIGTERM);
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	printf("%s", "RTKTHREAD_enter");
-+#endif
-+}
-+void thread_exit(_completion *comp);
-+void _rtw_init_completion(_completion *comp);
-+void _rtw_wait_for_comp_timeout(_completion *comp);
-+void _rtw_wait_for_comp(_completion *comp);
-+
-+static inline bool rtw_thread_stop(_thread_hdl_ th)
-+{
-+#ifdef PLATFORM_LINUX
-+	return kthread_stop(th);
-+#endif
-+}
-+static inline void rtw_thread_wait_stop(void)
-+{
-+#ifdef PLATFORM_LINUX
-+	#if 0
-+	while (!kthread_should_stop())
-+		rtw_msleep_os(10);
-+	#else
-+	set_current_state(TASK_INTERRUPTIBLE);
-+	while (!kthread_should_stop()) {
-+		schedule();
-+		set_current_state(TASK_INTERRUPTIBLE);
-+	}
-+	__set_current_state(TASK_RUNNING);
-+	#endif
-+#endif
-+}
-+
-+__inline static void flush_signals_thread(void)
-+{
-+#ifdef PLATFORM_LINUX
-+	if (signal_pending(current))
-+		flush_signals(current);
-+#endif
-+}
-+
-+__inline static _OS_STATUS res_to_status(sint res)
-+{
-+
-+#if defined(PLATFORM_LINUX) || defined (PLATFORM_MPIXEL) || defined (PLATFORM_FREEBSD)
-+	return res;
-+#endif
-+
-+#ifdef PLATFORM_WINDOWS
-+
-+	if (res == _SUCCESS)
-+		return NDIS_STATUS_SUCCESS;
-+	else
-+		return NDIS_STATUS_FAILURE;
-+
-+#endif
-+
-+}
-+
-+__inline static void rtw_dump_stack(void)
-+{
-+#ifdef PLATFORM_LINUX
-+	dump_stack();
-+#endif
-+}
-+
-+#ifdef PLATFORM_LINUX
-+#define rtw_warn_on(condition) WARN_ON(condition)
-+#else
-+#define rtw_warn_on(condition) do {} while (0)
-+#endif
-+
-+__inline static int rtw_bug_check(void *parg1, void *parg2, void *parg3, void *parg4)
-+{
-+	int ret = _TRUE;
-+
-+#ifdef PLATFORM_WINDOWS
-+	if (((uint)parg1) <= 0x7fffffff ||
-+	    ((uint)parg2) <= 0x7fffffff ||
-+	    ((uint)parg3) <= 0x7fffffff ||
-+	    ((uint)parg4) <= 0x7fffffff) {
-+		ret = _FALSE;
-+		KeBugCheckEx(0x87110000, (ULONG_PTR)parg1, (ULONG_PTR)parg2, (ULONG_PTR)parg3, (ULONG_PTR)parg4);
-+	}
-+#endif
-+
-+	return ret;
-+
-+}
-+#ifdef PLATFORM_LINUX
-+#define RTW_DIV_ROUND_UP(n, d)	DIV_ROUND_UP(n, d)
-+#else /* !PLATFORM_LINUX */
-+#define RTW_DIV_ROUND_UP(n, d)	(((n) + (d - 1)) / d)
-+#endif /* !PLATFORM_LINUX */
-+
-+#define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r))
-+#define RND4(x)	(((x >> 2) + (((x & 3) == 0) ? 0 : 1)) << 2)
-+
-+__inline static u32 _RND4(u32 sz)
-+{
-+
-+	u32	val;
-+
-+	val = ((sz >> 2) + ((sz & 3) ? 1 : 0)) << 2;
-+
-+	return val;
-+
-+}
-+
-+__inline static u32 _RND8(u32 sz)
-+{
-+
-+	u32	val;
-+
-+	val = ((sz >> 3) + ((sz & 7) ? 1 : 0)) << 3;
-+
-+	return val;
-+
-+}
-+
-+__inline static u32 _RND128(u32 sz)
-+{
-+
-+	u32	val;
-+
-+	val = ((sz >> 7) + ((sz & 127) ? 1 : 0)) << 7;
-+
-+	return val;
-+
-+}
-+
-+__inline static u32 _RND256(u32 sz)
-+{
-+
-+	u32	val;
-+
-+	val = ((sz >> 8) + ((sz & 255) ? 1 : 0)) << 8;
-+
-+	return val;
-+
-+}
-+
-+__inline static u32 _RND512(u32 sz)
-+{
-+
-+	u32	val;
-+
-+	val = ((sz >> 9) + ((sz & 511) ? 1 : 0)) << 9;
-+
-+	return val;
-+
-+}
-+
-+__inline static u32 bitshift(u32 bitmask)
-+{
-+	u32 i;
-+
-+	for (i = 0; i <= 31; i++)
-+		if (((bitmask >> i) &  0x1) == 1)
-+			break;
-+
-+	return i;
-+}
-+
-+static inline int largest_bit(u32 bitmask)
-+{
-+	int i;
-+
-+	for (i = 31; i >= 0; i--)
-+		if (bitmask & BIT(i))
-+			break;
-+
-+	return i;
-+}
-+
-+static inline int largest_bit_64(u64 bitmask)
-+{
-+	int i;
-+
-+	for (i = 63; i >= 0; i--)
-+		if (bitmask & BIT_ULL(i))
-+			break;
-+
-+	return i;
-+}
-+
-+#define rtw_abs(a) (a < 0 ? -a : a)
-+#define rtw_min(a, b) ((a > b) ? b : a)
-+#define rtw_max(a, b) ((a > b) ? a : b)
-+#define rtw_is_range_a_in_b(hi_a, lo_a, hi_b, lo_b) (((hi_a) <= (hi_b)) && ((lo_a) >= (lo_b)))
-+#define rtw_is_range_overlap(hi_a, lo_a, hi_b, lo_b) (((hi_a) > (lo_b)) && ((lo_a) < (hi_b)))
-+
-+#ifndef MAC_FMT
-+#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
-+#endif
-+#ifndef MAC_ARG
-+#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5]
-+#endif
-+
-+bool rtw_macaddr_is_larger(const u8 *a, const u8 *b);
-+
-+extern void rtw_suspend_lock_init(void);
-+extern void rtw_suspend_lock_uninit(void);
-+extern void rtw_lock_suspend(void);
-+extern void rtw_unlock_suspend(void);
-+extern void rtw_lock_suspend_timeout(u32 timeout_ms);
-+extern void rtw_lock_traffic_suspend_timeout(u32 timeout_ms);
-+extern void rtw_resume_lock_suspend(void);
-+extern void rtw_resume_unlock_suspend(void);
-+#ifdef CONFIG_AP_WOWLAN
-+extern void rtw_softap_lock_suspend(void);
-+extern void rtw_softap_unlock_suspend(void);
-+#endif
-+
-+extern void rtw_set_bit(int nr, unsigned long *addr);
-+extern void rtw_clear_bit(int nr, unsigned long *addr);
-+extern int rtw_test_and_clear_bit(int nr, unsigned long *addr);
-+
-+extern void ATOMIC_SET(ATOMIC_T *v, int i);
-+extern int ATOMIC_READ(ATOMIC_T *v);
-+extern void ATOMIC_ADD(ATOMIC_T *v, int i);
-+extern void ATOMIC_SUB(ATOMIC_T *v, int i);
-+extern void ATOMIC_INC(ATOMIC_T *v);
-+extern void ATOMIC_DEC(ATOMIC_T *v);
-+extern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i);
-+extern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i);
-+extern int ATOMIC_INC_RETURN(ATOMIC_T *v);
-+extern int ATOMIC_DEC_RETURN(ATOMIC_T *v);
-+extern bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u);
-+
-+/* File operation APIs, just for linux now */
-+extern int rtw_is_dir_readable(const char *path);
-+extern int rtw_is_file_readable(const char *path);
-+extern int rtw_is_file_readable_with_size(const char *path, u32 *sz);
-+extern int rtw_readable_file_sz_chk(const char *path, u32 sz);
-+extern int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz);
-+extern int rtw_store_to_file(const char *path, u8 *buf, u32 sz);
-+
-+
-+#ifndef PLATFORM_FREEBSD
-+extern void rtw_free_netdev(struct net_device *netdev);
-+#endif /* PLATFORM_FREEBSD */
-+
-+
-+extern u64 rtw_modular64(u64 x, u64 y);
-+extern u64 rtw_division64(u64 x, u64 y);
-+extern u32 rtw_random32(void);
-+
-+/* Macros for handling unaligned memory accesses */
-+
-+#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1]))
-+#define RTW_PUT_BE16(a, val)			\
-+	do {					\
-+		(a)[0] = ((u16) (val)) >> 8;	\
-+		(a)[1] = ((u16) (val)) & 0xff;	\
-+	} while (0)
-+
-+#define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0]))
-+#define RTW_PUT_LE16(a, val)			\
-+	do {					\
-+		(a)[1] = ((u16) (val)) >> 8;	\
-+		(a)[0] = ((u16) (val)) & 0xff;	\
-+	} while (0)
-+
-+#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \
-+			 ((u32) (a)[2]))
-+#define RTW_PUT_BE24(a, val)					\
-+	do {							\
-+		(a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
-+		(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
-+		(a)[2] = (u8) (((u32) (val)) & 0xff);		\
-+	} while (0)
-+
-+#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \
-+			 (((u32) (a)[2]) << 8) | ((u32) (a)[3]))
-+#define RTW_PUT_BE32(a, val)					\
-+	do {							\
-+		(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
-+		(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
-+		(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
-+		(a)[3] = (u8) (((u32) (val)) & 0xff);		\
-+	} while (0)
-+
-+#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \
-+			 (((u32) (a)[1]) << 8) | ((u32) (a)[0]))
-+#define RTW_PUT_LE32(a, val)					\
-+	do {							\
-+		(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
-+		(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
-+		(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
-+		(a)[0] = (u8) (((u32) (val)) & 0xff);		\
-+	} while (0)
-+
-+#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \
-+			 (((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \
-+			 (((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \
-+			 (((u64) (a)[6]) << 8) | ((u64) (a)[7]))
-+#define RTW_PUT_BE64(a, val)				\
-+	do {						\
-+		(a)[0] = (u8) (((u64) (val)) >> 56);	\
-+		(a)[1] = (u8) (((u64) (val)) >> 48);	\
-+		(a)[2] = (u8) (((u64) (val)) >> 40);	\
-+		(a)[3] = (u8) (((u64) (val)) >> 32);	\
-+		(a)[4] = (u8) (((u64) (val)) >> 24);	\
-+		(a)[5] = (u8) (((u64) (val)) >> 16);	\
-+		(a)[6] = (u8) (((u64) (val)) >> 8);	\
-+		(a)[7] = (u8) (((u64) (val)) & 0xff);	\
-+	} while (0)
-+
-+#define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \
-+			 (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \
-+			 (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \
-+			 (((u64) (a)[1]) << 8) | ((u64) (a)[0]))
-+#define RTW_PUT_LE64(a, val)					\
-+	do {							\
-+		(a)[7] = (u8) ((((u64) (val)) >> 56) & 0xff);	\
-+		(a)[6] = (u8) ((((u64) (val)) >> 48) & 0xff);	\
-+		(a)[5] = (u8) ((((u64) (val)) >> 40) & 0xff);	\
-+		(a)[4] = (u8) ((((u64) (val)) >> 32) & 0xff);	\
-+		(a)[3] = (u8) ((((u64) (val)) >> 24) & 0xff);	\
-+		(a)[2] = (u8) ((((u64) (val)) >> 16) & 0xff);	\
-+		(a)[1] = (u8) ((((u64) (val)) >> 8) & 0xff);	\
-+		(a)[0] = (u8) (((u64) (val)) & 0xff);		\
-+	} while (0)
-+
-+void rtw_buf_free(u8 **buf, u32 *buf_len);
-+void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len);
-+
-+struct rtw_cbuf {
-+	u32 write;
-+	u32 read;
-+	u32 size;
-+	void *bufs[0];
-+};
-+
-+bool rtw_cbuf_full(struct rtw_cbuf *cbuf);
-+bool rtw_cbuf_empty(struct rtw_cbuf *cbuf);
-+bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf);
-+void *rtw_cbuf_pop(struct rtw_cbuf *cbuf);
-+struct rtw_cbuf *rtw_cbuf_alloc(u32 size);
-+void rtw_cbuf_free(struct rtw_cbuf *cbuf);
-+
-+struct map_seg_t {
-+	u16 sa;
-+	u16 len;
-+	u8 *c;
-+};
-+
-+struct map_t {
-+	u16 len;
-+	u16 seg_num;
-+	u8 init_value;
-+	struct map_seg_t *segs;
-+};
-+
-+#define MAPSEG_ARRAY_ENT(_sa, _len, _c, arg...) \
-+	{ .sa = _sa, .len = _len, .c = (u8[_len]){ _c, ##arg}, }
-+
-+#define MAPSEG_PTR_ENT(_sa, _len, _p) \
-+	{ .sa = _sa, .len = _len, .c = _p, }
-+
-+#define MAP_ENT(_len, _seg_num, _init_v, _seg, arg...) \
-+	{ .len = _len, .seg_num = _seg_num, .init_value = _init_v, .segs = (struct map_seg_t[_seg_num]){ _seg, ##arg}, }
-+
-+int map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf);
-+u8 map_read8(const struct map_t *map, u16 offset);
-+
-+struct blacklist_ent {
-+	_list list;
-+	u8 addr[ETH_ALEN];
-+	systime exp_time;
-+};
-+
-+#ifdef CONFIG_RTW_MESH
-+int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms);
-+int rtw_blacklist_del(_queue *blist, const u8 *addr);
-+int rtw_blacklist_search(_queue *blist, const u8 *addr);
-+void rtw_blacklist_flush(_queue *blist);
-+void dump_blacklist(void *sel, _queue *blist, const char *title);
-+#endif
-+
-+/* String handler */
-+
-+BOOLEAN is_null(char c);
-+BOOLEAN is_all_null(char *c, int len);
-+BOOLEAN is_eol(char c);
-+BOOLEAN is_space(char c);
-+BOOLEAN IsHexDigit(char chTmp);
-+BOOLEAN is_alpha(char chTmp);
-+char alpha_to_upper(char c);
-+
-+int hex2num_i(char c);
-+int hex2byte_i(const char *hex);
-+int hexstr2bin(const char *hex, u8 *buf, size_t len);
-+
-+int hwaddr_aton_i(const char *txt, u8 *addr);
-+
-+/*
-+ * Write formatted output to sized buffer
-+ */
-+#ifdef PLATFORM_LINUX
-+#define rtw_sprintf(buf, size, format, arg...)	snprintf(buf, size, format, ##arg)
-+#else /* !PLATFORM_LINUX */
-+#error "NOT DEFINE \"rtw_sprintf\"!!"
-+#endif /* !PLATFORM_LINUX */
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/osdep_service_bsd.h b/drivers/staging/rtl8723cs/include/osdep_service_bsd.h
-new file mode 100644
-index 000000000000..f8f15d6fd2f9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/osdep_service_bsd.h
-@@ -0,0 +1,757 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __OSDEP_BSD_SERVICE_H_
-+#define __OSDEP_BSD_SERVICE_H_
-+
-+
-+#include <sys/cdefs.h>
-+#include <sys/types.h>
-+#include <sys/systm.h>
-+#include <sys/param.h>
-+#include <sys/sockio.h>
-+#include <sys/sysctl.h>
-+#include <sys/lock.h>
-+#include <sys/mutex.h>
-+#include <sys/mbuf.h>
-+#include <sys/kernel.h>
-+#include <sys/socket.h>
-+#include <sys/systm.h>
-+#include <sys/malloc.h>
-+#include <sys/module.h>
-+#include <sys/bus.h>
-+#include <sys/endian.h>
-+#include <sys/kdb.h>
-+#include <sys/kthread.h>
-+#include <sys/malloc.h>
-+#include <sys/time.h>
-+#include <machine/atomic.h>
-+#include <machine/bus.h>
-+#include <machine/resource.h>
-+#include <sys/rman.h>
-+
-+#include <net/bpf.h>
-+#include <net/if.h>
-+#include <net/if_arp.h>
-+#include <net/ethernet.h>
-+#include <net/if_dl.h>
-+#include <net/if_media.h>
-+#include <net/if_types.h>
-+#include <net/route.h>
-+
-+
-+#include <netinet/in.h>
-+#include <netinet/in_systm.h>
-+#include <netinet/in_var.h>
-+#include <netinet/if_ether.h>
-+#include <if_ether.h>
-+
-+#include <net80211/ieee80211_var.h>
-+#include <net80211/ieee80211_regdomain.h>
-+#include <net80211/ieee80211_radiotap.h>
-+#include <net80211/ieee80211_ratectl.h>
-+
-+#include <dev/usb/usb.h>
-+#include <dev/usb/usbdi.h>
-+#include "usbdevs.h"
-+
-+#define	USB_DEBUG_VAR rum_debug
-+#include <dev/usb/usb_debug.h>
-+
-+#if 1 //Baron porting from linux, it's all temp solution, needs to check again
-+#include <sys/sema.h>
-+#include <sys/pcpu.h> /* XXX for PCPU_GET */
-+//	typedef struct 	semaphore _sema;
-+	typedef struct 	sema _sema;
-+//	typedef	spinlock_t	_lock;
-+	typedef	struct mtx	_lock;
-+	typedef struct mtx 		_mutex;
-+	typedef struct rtw_timer_list _timer;
-+	struct list_head {
-+	struct list_head *next, *prev;
-+	};
-+	struct	__queue	{
-+		struct	list_head	queue;	
-+		_lock	lock;
-+	};
-+
-+	typedef	struct mbuf _pkt;
-+	typedef struct mbuf	_buffer;
-+	
-+	typedef struct	__queue	_queue;
-+	typedef struct	list_head	_list;
-+	typedef	int	_OS_STATUS;
-+	//typedef u32	_irqL;
-+	typedef unsigned long _irqL;
-+	typedef	struct	ifnet * _nic_hdl;
-+	
-+	typedef pid_t		_thread_hdl_;
-+//	typedef struct thread		_thread_hdl_;
-+	typedef void		thread_return;
-+	typedef void*	thread_context;
-+
-+	typedef void timer_hdl_return;
-+	typedef void* timer_hdl_context;
-+	typedef struct work_struct _workitem;
-+	typedef struct task _tasklet;
-+
-+#define   KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
-+/* emulate a modern version */
-+#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35)
-+
-+#define WIRELESS_EXT -1
-+#define HZ hz
-+#define spin_lock_irqsave mtx_lock_irqsave
-+#define spin_lock_bh mtx_lock_irqsave
-+#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));}
-+//#define IFT_RTW	0xf9 //ifnet allocate type for RTW
-+#define free_netdev if_free
-+#define LIST_CONTAINOR(ptr, type, member) \
-+        ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
-+#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n))
-+/* 
-+ * Linux timers are emulated using FreeBSD callout functions
-+ * (and taskqueue functionality).
-+ *
-+ * Currently no timer stats functionality.
-+ *
-+ * See (linux_compat) processes.c
-+ *
-+ */
-+struct rtw_timer_list {
-+	struct callout callout;
-+	void (*function)(void *);
-+	void *arg;
-+};
-+
-+struct workqueue_struct;
-+struct work_struct;
-+typedef void (*work_func_t)(struct work_struct *work);
-+/* Values for the state of an item of work (work_struct) */
-+typedef enum work_state {
-+        WORK_STATE_UNSET = 0,
-+        WORK_STATE_CALLOUT_PENDING = 1,
-+        WORK_STATE_TASK_PENDING = 2,
-+        WORK_STATE_WORK_CANCELLED = 3        
-+} work_state_t;
-+
-+struct work_struct {
-+        struct task task; /* FreeBSD task */
-+        work_state_t state; /* the pending or otherwise state of work. */
-+        work_func_t func;       
-+};
-+#define spin_unlock_irqrestore mtx_unlock_irqrestore
-+#define spin_unlock_bh mtx_unlock_irqrestore
-+#define mtx_unlock_irqrestore(lock,x)    mtx_unlock(lock);
-+extern void	_rtw_spinlock_init(_lock *plock);
-+
-+//modify private structure to match freebsd
-+#define BITS_PER_LONG 32
-+union ktime {
-+	s64	tv64;
-+#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR)
-+	struct {
-+#ifdef __BIG_ENDIAN
-+	s32	sec, nsec;
-+#else
-+	s32	nsec, sec;
-+#endif
-+	} tv;
-+#endif
-+};
-+#define kmemcheck_bitfield_begin(name)
-+#define kmemcheck_bitfield_end(name)
-+#define CHECKSUM_NONE 0
-+typedef unsigned char *sk_buff_data_t;
-+typedef union ktime ktime_t;		/* Kill this */
-+
-+void rtw_mtx_lock(_lock *plock);
-+	
-+void rtw_mtx_unlock(_lock *plock);
-+
-+/** 
-+ *	struct sk_buff - socket buffer
-+ *	@next: Next buffer in list
-+ *	@prev: Previous buffer in list
-+ *	@sk: Socket we are owned by
-+ *	@tstamp: Time we arrived
-+ *	@dev: Device we arrived on/are leaving by
-+ *	@transport_header: Transport layer header
-+ *	@network_header: Network layer header
-+ *	@mac_header: Link layer header
-+ *	@_skb_refdst: destination entry (with norefcount bit)
-+ *	@sp: the security path, used for xfrm
-+ *	@cb: Control buffer. Free for use by every layer. Put private vars here
-+ *	@len: Length of actual data
-+ *	@data_len: Data length
-+ *	@mac_len: Length of link layer header
-+ *	@hdr_len: writable header length of cloned skb
-+ *	@csum: Checksum (must include start/offset pair)
-+ *	@csum_start: Offset from skb->head where checksumming should start
-+ *	@csum_offset: Offset from csum_start where checksum should be stored
-+ *	@local_df: allow local fragmentation
-+ *	@cloned: Head may be cloned (check refcnt to be sure)
-+ *	@nohdr: Payload reference only, must not modify header
-+ *	@pkt_type: Packet class
-+ *	@fclone: skbuff clone status
-+ *	@ip_summed: Driver fed us an IP checksum
-+ *	@priority: Packet queueing priority
-+ *	@users: User count - see {datagram,tcp}.c
-+ *	@protocol: Packet protocol from driver
-+ *	@truesize: Buffer size 
-+ *	@head: Head of buffer
-+ *	@data: Data head pointer
-+ *	@tail: Tail pointer
-+ *	@end: End pointer
-+ *	@destructor: Destruct function
-+ *	@mark: Generic packet mark
-+ *	@nfct: Associated connection, if any
-+ *	@ipvs_property: skbuff is owned by ipvs
-+ *	@peeked: this packet has been seen already, so stats have been
-+ *		done for it, don't do them again
-+ *	@nf_trace: netfilter packet trace flag
-+ *	@nfctinfo: Relationship of this skb to the connection
-+ *	@nfct_reasm: netfilter conntrack re-assembly pointer
-+ *	@nf_bridge: Saved data about a bridged frame - see br_netfilter.c
-+ *	@skb_iif: ifindex of device we arrived on
-+ *	@rxhash: the packet hash computed on receive
-+ *	@queue_mapping: Queue mapping for multiqueue devices
-+ *	@tc_index: Traffic control index
-+ *	@tc_verd: traffic control verdict
-+ *	@ndisc_nodetype: router type (from link layer)
-+ *	@dma_cookie: a cookie to one of several possible DMA operations
-+ *		done by skb DMA functions
-+ *	@secmark: security marking
-+ *	@vlan_tci: vlan tag control information
-+ */
-+
-+struct sk_buff {
-+	/* These two members must be first. */
-+	struct sk_buff		*next;
-+	struct sk_buff		*prev;
-+
-+	ktime_t			tstamp;
-+
-+	struct sock		*sk;
-+	//struct net_device	*dev;
-+	struct ifnet *dev;
-+
-+	/*
-+	 * This is the control buffer. It is free to use for every
-+	 * layer. Please put your private variables there. If you
-+	 * want to keep them across layers you have to do a skb_clone()
-+	 * first. This is owned by whoever has the skb queued ATM.
-+	 */
-+	char			cb[48] __aligned(8);
-+
-+	unsigned long		_skb_refdst;
-+#ifdef CONFIG_XFRM
-+	struct	sec_path	*sp;
-+#endif
-+	unsigned int		len,
-+				data_len;
-+	u16			mac_len,
-+				hdr_len;
-+	union {
-+		u32		csum;
-+		struct {
-+			u16	csum_start;
-+			u16	csum_offset;
-+		}smbol2;
-+	}smbol1;
-+	u32			priority;
-+	kmemcheck_bitfield_begin(flags1);
-+	u8			local_df:1,
-+				cloned:1,
-+				ip_summed:2,
-+				nohdr:1,
-+				nfctinfo:3;
-+	u8			pkt_type:3,
-+				fclone:2,
-+				ipvs_property:1,
-+				peeked:1,
-+				nf_trace:1;
-+	kmemcheck_bitfield_end(flags1);
-+	u16			protocol;
-+
-+	void			(*destructor)(struct sk_buff *skb);
-+#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
-+	struct nf_conntrack	*nfct;
-+	struct sk_buff		*nfct_reasm;
-+#endif
-+#ifdef CONFIG_BRIDGE_NETFILTER
-+	struct nf_bridge_info	*nf_bridge;
-+#endif
-+
-+	int			skb_iif;
-+#ifdef CONFIG_NET_SCHED
-+	u16			tc_index;	/* traffic control index */
-+#ifdef CONFIG_NET_CLS_ACT
-+	u16			tc_verd;	/* traffic control verdict */
-+#endif
-+#endif
-+
-+	u32			rxhash;
-+
-+	kmemcheck_bitfield_begin(flags2);
-+	u16			queue_mapping:16;
-+#ifdef CONFIG_IPV6_NDISC_NODETYPE
-+	u8			ndisc_nodetype:2,
-+				deliver_no_wcard:1;
-+#else
-+	u8			deliver_no_wcard:1;
-+#endif
-+	kmemcheck_bitfield_end(flags2);
-+
-+	/* 0/14 bit hole */
-+
-+#ifdef CONFIG_NET_DMA
-+	dma_cookie_t		dma_cookie;
-+#endif
-+#ifdef CONFIG_NETWORK_SECMARK
-+	u32			secmark;
-+#endif
-+	union {
-+		u32		mark;
-+		u32		dropcount;
-+	}symbol3;
-+
-+	u16			vlan_tci;
-+
-+	sk_buff_data_t		transport_header;
-+	sk_buff_data_t		network_header;
-+	sk_buff_data_t		mac_header;
-+	/* These elements must be at the end, see alloc_skb() for details.  */
-+	sk_buff_data_t		tail;
-+	sk_buff_data_t		end;
-+	unsigned char		*head,
-+				*data;
-+	unsigned int		truesize;
-+	atomic_t		users;
-+};
-+struct sk_buff_head {
-+	/* These two members must be first. */
-+	struct sk_buff	*next;
-+	struct sk_buff	*prev;
-+
-+	u32		qlen;
-+	_lock	lock;
-+};
-+#define skb_tail_pointer(skb)	skb->tail
-+static inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len)
-+{
-+	unsigned char *tmp = skb_tail_pointer(skb);
-+	//SKB_LINEAR_ASSERT(skb);
-+	skb->tail += len;
-+	skb->len  += len;
-+	return tmp;
-+}
-+
-+static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len)
-+{
-+	skb->len -= len;
-+	if(skb->len < skb->data_len)
-+		printf("%s(),%d,error!\n",__FUNCTION__,__LINE__);
-+	return skb->data += len;
-+}
-+static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len)
-+{
-+	#ifdef PLATFORM_FREEBSD
-+	return __skb_pull(skb, len);
-+	#else
-+	return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len);
-+	#endif //PLATFORM_FREEBSD
-+}
-+static inline u32 skb_queue_len(const struct sk_buff_head *list_)
-+{
-+	return list_->qlen;
-+}
-+static inline void __skb_insert(struct sk_buff *newsk,
-+				struct sk_buff *prev, struct sk_buff *next,
-+				struct sk_buff_head *list)
-+{
-+	newsk->next = next;
-+	newsk->prev = prev;
-+	next->prev  = prev->next = newsk;
-+	list->qlen++;
-+}
-+static inline void __skb_queue_before(struct sk_buff_head *list,
-+				      struct sk_buff *next,
-+				      struct sk_buff *newsk)
-+{
-+	__skb_insert(newsk, next->prev, next, list);
-+}
-+static inline void skb_queue_tail(struct sk_buff_head *list,
-+				   struct sk_buff *newsk)
-+{
-+	mtx_lock(&list->lock);
-+	__skb_queue_before(list, (struct sk_buff *)list, newsk);
-+	mtx_unlock(&list->lock);
-+}
-+static inline struct sk_buff *skb_peek(struct sk_buff_head *list_)
-+{
-+	struct sk_buff *list = ((struct sk_buff *)list_)->next;
-+	if (list == (struct sk_buff *)list_)
-+		list = NULL;
-+	return list;
-+}
-+static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list)
-+{
-+	struct sk_buff *next, *prev;
-+
-+	list->qlen--;
-+	next	   = skb->next;
-+	prev	   = skb->prev;
-+	skb->next  = skb->prev = NULL;
-+	next->prev = prev;
-+	prev->next = next;
-+}
-+
-+static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list)
-+{
-+	mtx_lock(&list->lock);
-+
-+	struct sk_buff *skb = skb_peek(list);
-+	if (skb)
-+		__skb_unlink(skb, list);
-+
-+	mtx_unlock(&list->lock);
-+
-+	return skb;
-+}
-+static inline void skb_reserve(struct sk_buff *skb, int len)
-+{
-+	skb->data += len;
-+	skb->tail += len;
-+}
-+static inline void __skb_queue_head_init(struct sk_buff_head *list)
-+{
-+	list->prev = list->next = (struct sk_buff *)list;
-+	list->qlen = 0;
-+}
-+/*
-+ * This function creates a split out lock class for each invocation;
-+ * this is needed for now since a whole lot of users of the skb-queue
-+ * infrastructure in drivers have different locking usage (in hardirq)
-+ * than the networking core (in softirq only). In the long run either the
-+ * network layer or drivers should need annotation to consolidate the
-+ * main types of usage into 3 classes.
-+ */
-+static inline void skb_queue_head_init(struct sk_buff_head *list)
-+{
-+	_rtw_spinlock_init(&list->lock);
-+	__skb_queue_head_init(list);
-+}
-+unsigned long copy_from_user(void *to, const void *from, unsigned long n);
-+unsigned long copy_to_user(void *to, const void *from, unsigned long n);
-+struct sk_buff * dev_alloc_skb(unsigned int size);
-+struct sk_buff *skb_clone(const struct sk_buff *skb);
-+void dev_kfree_skb_any(struct sk_buff *skb);
-+#endif //Baron porting from linux, it's all temp solution, needs to check again
-+
-+
-+#if 1 // kenny add Linux compatibility code for Linux USB driver
-+#include <dev/usb/usb_compat_linux.h>
-+
-+#define __init		// __attribute ((constructor))
-+#define __exit		// __attribute ((destructor))
-+
-+/*
-+ * Definitions for module_init and module_exit macros.
-+ *
-+ * These macros will use the SYSINIT framework to call a specified
-+ * function (with no arguments) on module loading or unloading.
-+ * 
-+ */
-+
-+void module_init_exit_wrapper(void *arg);
-+
-+#define module_init(initfn)                             \
-+        SYSINIT(mod_init_ ## initfn,                    \
-+                SI_SUB_KLD, SI_ORDER_FIRST,             \
-+                module_init_exit_wrapper, initfn)
-+
-+#define module_exit(exitfn)                             \
-+        SYSUNINIT(mod_exit_ ## exitfn,                  \
-+                  SI_SUB_KLD, SI_ORDER_ANY,             \
-+                  module_init_exit_wrapper, exitfn)
-+
-+/*
-+ * The usb_register and usb_deregister functions are used to register
-+ * usb drivers with the usb subsystem. 
-+ */
-+int usb_register(struct usb_driver *driver);
-+int usb_deregister(struct usb_driver *driver);
-+
-+/*
-+ * usb_get_dev and usb_put_dev - increment/decrement the reference count 
-+ * of the usb device structure.
-+ *
-+ * Original body of usb_get_dev:
-+ *
-+ *       if (dev)
-+ *               get_device(&dev->dev);
-+ *       return dev;
-+ *
-+ * Reference counts are not currently used in this compatibility
-+ * layer. So these functions will do nothing.
-+ */
-+static inline struct usb_device *
-+usb_get_dev(struct usb_device *dev)
-+{
-+        return dev;
-+}
-+
-+static inline void 
-+usb_put_dev(struct usb_device *dev)
-+{
-+        return;
-+}
-+
-+
-+// rtw_usb_compat_linux
-+int rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags);
-+int rtw_usb_unlink_urb(struct urb *urb);
-+int rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe);
-+int rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe,
-+    uint8_t request, uint8_t requesttype,
-+    uint16_t value, uint16_t index, void *data,
-+    uint16_t size, usb_timeout_t timeout);
-+int rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index);
-+int rtw_usb_setup_endpoint(struct usb_device *dev,
-+    struct usb_host_endpoint *uhe, usb_size_t bufsize);
-+struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags);
-+struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep);
-+struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index);
-+struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no);
-+void *rtw_usbd_get_intfdata(struct usb_interface *intf);
-+void rtw_usb_linux_register(void *arg);
-+void rtw_usb_linux_deregister(void *arg);
-+void rtw_usb_linux_free_device(struct usb_device *dev);
-+void rtw_usb_free_urb(struct urb *urb);
-+void rtw_usb_init_urb(struct urb *urb);
-+void rtw_usb_kill_urb(struct urb *urb);
-+void rtw_usb_set_intfdata(struct usb_interface *intf, void *data);
-+void rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev,
-+    struct usb_host_endpoint *uhe, void *buf,
-+    int length, usb_complete_t callback, void *arg);
-+int rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe,
-+    void *data, int len, uint16_t *pactlen, usb_timeout_t timeout);
-+void *usb_get_intfdata(struct usb_interface *intf);
-+int usb_linux_init_endpoints(struct usb_device *udev);
-+
-+
-+
-+typedef struct urb *  PURB;
-+
-+typedef unsigned gfp_t;
-+#define __GFP_WAIT      ((gfp_t)0x10u)  /* Can wait and reschedule? */
-+#define __GFP_HIGH      ((gfp_t)0x20u)  /* Should access emergency pools? */
-+#define __GFP_IO        ((gfp_t)0x40u)  /* Can start physical IO? */
-+#define __GFP_FS        ((gfp_t)0x80u)  /* Can call down to low-level FS? */
-+#define __GFP_COLD      ((gfp_t)0x100u) /* Cache-cold page required */
-+#define __GFP_NOWARN    ((gfp_t)0x200u) /* Suppress page allocation failure warning */
-+#define __GFP_REPEAT    ((gfp_t)0x400u) /* Retry the allocation.  Might fail */
-+#define __GFP_NOFAIL    ((gfp_t)0x800u) /* Retry for ever.  Cannot fail */
-+#define __GFP_NORETRY   ((gfp_t)0x1000u)/* Do not retry.  Might fail */
-+#define __GFP_NO_GROW   ((gfp_t)0x2000u)/* Slab internal usage */
-+#define __GFP_COMP      ((gfp_t)0x4000u)/* Add compound page metadata */
-+#define __GFP_ZERO      ((gfp_t)0x8000u)/* Return zeroed page on success */
-+#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */
-+#define __GFP_HARDWALL   ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */
-+
-+/* This equals 0, but use constants in case they ever change */
-+#define GFP_NOWAIT      (GFP_ATOMIC & ~__GFP_HIGH)
-+/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */
-+#define GFP_ATOMIC      (__GFP_HIGH)
-+#define GFP_NOIO        (__GFP_WAIT)
-+#define GFP_NOFS        (__GFP_WAIT | __GFP_IO)
-+#define GFP_KERNEL      (__GFP_WAIT | __GFP_IO | __GFP_FS)
-+#define GFP_USER        (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL)
-+#define GFP_HIGHUSER    (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \
-+                         __GFP_HIGHMEM)
-+
-+
-+#endif // kenny add Linux compatibility code for Linux USB
-+
-+__inline static _list *get_next(_list	*list)
-+{
-+	return list->next;
-+}	
-+
-+__inline static _list	*get_list_head(_queue	*queue)
-+{
-+	return (&(queue->queue));
-+}
-+
-+	
-+#define LIST_CONTAINOR(ptr, type, member) \
-+        ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))	
-+
-+        
-+__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
-+{
-+	spin_lock_irqsave(plock, *pirqL);
-+}
-+
-+__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
-+{
-+	spin_unlock_irqrestore(plock, *pirqL);
-+}
-+
-+__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL)
-+{
-+	spin_lock_irqsave(plock, *pirqL);
-+}
-+
-+__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL)
-+{
-+	spin_unlock_irqrestore(plock, *pirqL);
-+}
-+
-+__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
-+{
-+	spin_lock_bh(plock, *pirqL);
-+}
-+
-+__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
-+{
-+	spin_unlock_bh(plock, *pirqL);
-+}
-+
-+__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
-+{
-+
-+		mtx_lock(pmutex);
-+
-+}
-+
-+
-+__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
-+{
-+
-+		mtx_unlock(pmutex);
-+
-+}
-+static inline void __list_del(struct list_head * prev, struct list_head * next)
-+{
-+	next->prev = prev;
-+	prev->next = next;
-+}
-+static inline void INIT_LIST_HEAD(struct list_head *list)
-+{
-+	list->next = list;
-+	list->prev = list;
-+}
-+__inline static void rtw_list_delete(_list *plist)
-+{
-+	__list_del(plist->prev, plist->next);
-+	INIT_LIST_HEAD(plist);
-+}
-+
-+static inline void timer_hdl(void *ctx)
-+{
-+	_timer *timer = (_timer *)ctx;
-+
-+	rtw_mtx_lock(NULL);
-+	if (callout_pending(&timer->callout)) {
-+		/* callout was reset */
-+		rtw_mtx_unlock(NULL);
-+		return;
-+	}
-+
-+	if (!callout_active(&timer->callout)) {
-+		/* callout was stopped */
-+		rtw_mtx_unlock(NULL);
-+		return;
-+	}
-+
-+	callout_deactivate(&timer->callout);
-+
-+	timer->function(timer->arg);
-+
-+	rtw_mtx_unlock(NULL);
-+}
-+
-+static inline void _init_timer(_timer *ptimer, _nic_hdl padapter, void *pfunc, void *cntx)
-+{
-+	ptimer->function = pfunc;
-+	ptimer->arg = cntx;
-+	callout_init(&ptimer->callout, CALLOUT_MPSAFE);
-+}
-+
-+__inline static void _set_timer(_timer *ptimer,u32 delay_time)
-+{	
-+	if (ptimer->function && ptimer->arg) {
-+		rtw_mtx_lock(NULL);
-+		callout_reset(&ptimer->callout, delay_time, timer_hdl, ptimer);
-+		rtw_mtx_unlock(NULL);
-+	}
-+}
-+
-+__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
-+{
-+	rtw_mtx_lock(NULL);
-+	callout_drain(&ptimer->callout);
-+	rtw_mtx_unlock(NULL);
-+	*bcancelled = 1; /* assume an pending timer to be canceled */
-+}
-+
-+__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
-+{
-+	printf("%s Not implement yet! \n",__FUNCTION__);
-+}
-+
-+__inline static void _set_workitem(_workitem *pwork)
-+{
-+	printf("%s Not implement yet! \n",__FUNCTION__);
-+//	schedule_work(pwork);
-+}
-+
-+//
-+// Global Mutex: can only be used at PASSIVE level.
-+//
-+
-+#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \
-+{                                                               \
-+}
-+
-+#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \
-+{                                                               \
-+}
-+
-+#define ATOMIC_INIT(i)  { (i) }
-+
-+static __inline void thread_enter(char *name);
-+
-+//Atomic integer operations
-+typedef uint32_t ATOMIC_T ;
-+
-+#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc)
-+
-+#define rtw_free_netdev(netdev) if_free((netdev))
-+
-+#define NDEV_FMT "%s"
-+#define NDEV_ARG(ndev) ""
-+#define ADPT_FMT "%s"
-+#define ADPT_ARG(adapter) ""
-+#define FUNC_NDEV_FMT "%s"
-+#define FUNC_NDEV_ARG(ndev) __func__
-+#define FUNC_ADPT_FMT "%s"
-+#define FUNC_ADPT_ARG(adapter) __func__
-+
-+#define STRUCT_PACKED
-+
-+#endif
-+
-diff --git a/drivers/staging/rtl8723cs/include/osdep_service_ce.h b/drivers/staging/rtl8723cs/include/osdep_service_ce.h
-new file mode 100644
-index 000000000000..2bf65ef4741d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/osdep_service_ce.h
-@@ -0,0 +1,200 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __OSDEP_CE_SERVICE_H_
-+#define __OSDEP_CE_SERVICE_H_
-+
-+
-+#include <ndis.h>
-+#include <ntddndis.h>
-+
-+#ifdef CONFIG_SDIO_HCI
-+#include "SDCardDDK.h"
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+#include <usbdi.h>
-+#endif
-+
-+typedef HANDLE 	_sema;
-+typedef	LIST_ENTRY	_list;
-+typedef NDIS_STATUS _OS_STATUS;
-+
-+typedef NDIS_SPIN_LOCK	_lock;
-+
-+typedef HANDLE 		_rwlock; //Mutex
-+
-+typedef u32	_irqL;
-+
-+typedef NDIS_HANDLE  _nic_hdl;
-+
-+struct rtw_timer_list {
-+	NDIS_MINIPORT_TIMER ndis_timer;
-+	void (*function)(void *);
-+	void *arg;
-+};
-+
-+struct	__queue	{
-+	LIST_ENTRY	queue;
-+	_lock	lock;
-+};
-+
-+typedef	NDIS_PACKET	_pkt;
-+typedef NDIS_BUFFER	_buffer;
-+typedef struct	__queue	_queue;
-+
-+typedef HANDLE 	_thread_hdl_;
-+typedef DWORD thread_return;
-+typedef void*	thread_context;
-+typedef NDIS_WORK_ITEM _workitem;
-+
-+
-+
-+#define SEMA_UPBND	(0x7FFFFFFF)   //8192
-+
-+__inline static _list *get_prev(_list	*list)
-+{
-+	return list->Blink;
-+}
-+	
-+__inline static _list *get_next(_list	*list)
-+{
-+	return list->Flink;
-+}
-+
-+__inline static _list	*get_list_head(_queue	*queue)
-+{
-+	return (&(queue->queue));
-+}
-+
-+#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
-+
-+__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
-+{
-+	NdisAcquireSpinLock(plock);
-+}
-+
-+__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
-+{
-+	NdisReleaseSpinLock(plock);
-+}
-+
-+__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
-+{
-+	NdisDprAcquireSpinLock(plock);	
-+}
-+
-+__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
-+{
-+	NdisDprReleaseSpinLock(plock);	
-+}
-+
-+
-+__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
-+{
-+	WaitForSingleObject(*prwlock, INFINITE );
-+
-+}
-+
-+__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
-+{
-+	ReleaseMutex(*prwlock);
-+}
-+
-+__inline static void rtw_list_delete(_list *plist)
-+{
-+	RemoveEntryList(plist);
-+	InitializeListHead(plist);
-+}
-+
-+static inline void timer_hdl(
-+	IN PVOID SystemSpecific1,
-+	IN PVOID FunctionContext,
-+	IN PVOID SystemSpecific2,
-+	IN PVOID SystemSpecific3)
-+{
-+	_timer *timer = (_timer *)FunctionContext;
-+
-+	timer->function(timer->arg);
-+}
-+
-+static inline void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)
-+{
-+	ptimer->function = pfunc;
-+	ptimer->arg = cntx;
-+	NdisMInitializeTimer(&ptimer->ndis_timer, nic_hdl, timer_hdl, ptimer);
-+}
-+
-+static inline void _set_timer(_timer *ptimer, u32 delay_time)
-+{
-+	NdisMSetTimer(ptimer, delay_time);
-+}
-+
-+static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)
-+{
-+	NdisMCancelTimer(ptimer, bcancelled);
-+}
-+
-+__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
-+{
-+
-+	NdisInitializeWorkItem(pwork, pfunc, cntx);
-+}
-+
-+__inline static void _set_workitem(_workitem *pwork)
-+{
-+	NdisScheduleWorkItem(pwork);
-+}
-+
-+#define ATOMIC_INIT(i)  { (i) }
-+
-+//
-+// Global Mutex: can only be used at PASSIVE level.
-+//
-+
-+#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \
-+{                                                               \
-+    while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
-+    {                                                           \
-+        NdisInterlockedDecrement((PULONG)&(_MutexCounter));        \
-+        NdisMSleep(10000);                          \
-+    }                                                           \
-+}
-+
-+#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \
-+{                                                               \
-+    NdisInterlockedDecrement((PULONG)&(_MutexCounter));              \
-+}
-+
-+// limitation of path length
-+#define PATH_LENGTH_MAX MAX_PATH
-+
-+//Atomic integer operations
-+#define ATOMIC_T LONG
-+
-+#define NDEV_FMT "%s"
-+#define NDEV_ARG(ndev) ""
-+#define ADPT_FMT "%s"
-+#define ADPT_ARG(adapter) ""
-+#define FUNC_NDEV_FMT "%s"
-+#define FUNC_NDEV_ARG(ndev) __func__
-+#define FUNC_ADPT_FMT "%s"
-+#define FUNC_ADPT_ARG(adapter) __func__
-+
-+#define STRUCT_PACKED
-+
-+
-+#endif
-+
-diff --git a/drivers/staging/rtl8723cs/include/osdep_service_linux.h b/drivers/staging/rtl8723cs/include/osdep_service_linux.h
-new file mode 100644
-index 000000000000..fca4cf6e714a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/osdep_service_linux.h
-@@ -0,0 +1,564 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __OSDEP_LINUX_SERVICE_H_
-+#define __OSDEP_LINUX_SERVICE_H_
-+
-+#include <linux/version.h>
-+#include <linux/spinlock.h>
-+#include <linux/compiler.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/init.h>
-+#include <linux/slab.h>
-+#include <linux/module.h>
-+#include <linux/namei.h>
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 5))
-+	#include <linux/kref.h>
-+#endif
-+/* #include <linux/smp_lock.h> */
-+#include <linux/netdevice.h>
-+#include <linux/inetdevice.h>
-+#include <linux/skbuff.h>
-+#include <linux/circ_buf.h>
-+#include <asm/uaccess.h>
-+#include <asm/byteorder.h>
-+#include <asm/atomic.h>
-+#include <asm/io.h>
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
-+	#include <asm/semaphore.h>
-+#else
-+	#include <linux/semaphore.h>
-+#endif
-+#include <linux/sem.h>
-+#include <linux/sched.h>
-+#include <linux/etherdevice.h>
-+#include <linux/wireless.h>
-+#include <net/iw_handler.h>
-+#include <net/addrconf.h>
-+#include <linux/if_arp.h>
-+#include <linux/rtnetlink.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>	/* for struct tasklet_struct */
-+#include <linux/ip.h>
-+#include <linux/kthread.h>
-+#include <linux/list.h>
-+#include <linux/vmalloc.h>
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0))
-+	#include <uapi/linux/sched/types.h>
-+#endif
-+
-+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 5, 41))
-+	#include <linux/tqueue.h>
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
-+	#include <uapi/linux/limits.h>
-+#else
-+	#include <linux/limits.h>
-+#endif
-+
-+#ifdef RTK_DMP_PLATFORM
-+	#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))
-+		#include <linux/pageremap.h>
-+	#endif
-+	#include <asm/io.h>
-+#endif
-+
-+#ifdef CONFIG_NET_RADIO
-+	#define CONFIG_WIRELESS_EXT
-+#endif
-+
-+/* Monitor mode */
-+#include <net/ieee80211_radiotap.h>
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
-+	#include <linux/ieee80211.h>
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25) && \
-+	 LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29))
-+	#define CONFIG_IEEE80211_HT_ADDT_INFO
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	/*	#include <linux/ieee80211.h> */
-+	#include <net/cfg80211.h>
-+#else
-+	#ifdef CONFIG_REGD_SRC_FROM_OS
-+	#error "CONFIG_REGD_SRC_FROM_OS requires CONFIG_IOCTL_CFG80211"
-+	#endif
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+
-+#ifdef CONFIG_HAS_EARLYSUSPEND
-+	#include <linux/earlysuspend.h>
-+#endif /* CONFIG_HAS_EARLYSUSPEND */
-+
-+#ifdef CONFIG_EFUSE_CONFIG_FILE
-+	#include <linux/fs.h>
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	#include <linux/usb.h>
-+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 21))
-+		#include <linux/usb_ch9.h>
-+	#else
-+		#include <linux/usb/ch9.h>
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+	#include <net/sock.h>
-+	#include <net/tcp.h>
-+	#include <linux/udp.h>
-+	#include <linux/in.h>
-+	#include <linux/netlink.h>
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+
-+#ifdef CONFIG_USB_HCI
-+	typedef struct urb   *PURB;
-+#endif
-+
-+#if defined(CONFIG_RTW_GRO) && (!defined(CONFIG_RTW_NAPI))
-+
-+	#error "Enable NAPI before enable GRO\n"
-+
-+#endif
-+
-+
-+#if (KERNEL_VERSION(2, 6, 29) > LINUX_VERSION_CODE && defined(CONFIG_RTW_NAPI))
-+
-+	#undef CONFIG_RTW_NAPI
-+	/*#warning "Linux Kernel version too old to support NAPI (should newer than 2.6.29)\n"*/
-+
-+#endif
-+
-+#if (KERNEL_VERSION(2, 6, 33) > LINUX_VERSION_CODE && defined(CONFIG_RTW_GRO))
-+
-+	#undef CONFIG_RTW_GRO
-+	/*#warning "Linux Kernel version too old to support GRO(should newer than 2.6.33)\n"*/
-+
-+#endif
-+
-+typedef struct	semaphore _sema;
-+typedef	spinlock_t	_lock;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
-+	typedef struct mutex		_mutex;
-+#else
-+	typedef struct semaphore	_mutex;
-+#endif
-+struct rtw_timer_list {
-+	struct timer_list timer;
-+	void (*function)(void *);
-+	void *arg;
-+};
-+
-+typedef struct rtw_timer_list _timer;
-+typedef struct completion _completion;
-+
-+struct	__queue	{
-+	struct	list_head	queue;
-+	_lock	lock;
-+};
-+
-+typedef	struct sk_buff	_pkt;
-+typedef unsigned char	_buffer;
-+
-+typedef struct	__queue	_queue;
-+typedef struct	list_head	_list;
-+
-+/* hlist */
-+typedef struct	hlist_head	rtw_hlist_head;
-+typedef struct	hlist_node	rtw_hlist_node;
-+
-+/* RCU */
-+typedef struct rcu_head rtw_rcu_head;
-+#define rtw_rcu_dereference(p) rcu_dereference((p))
-+#define rtw_rcu_dereference_protected(p, c) rcu_dereference_protected(p, c)
-+#define rtw_rcu_assign_pointer(p, v) rcu_assign_pointer((p), (v))
-+#define rtw_rcu_read_lock() rcu_read_lock()
-+#define rtw_rcu_read_unlock() rcu_read_unlock()
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34))
-+#define rtw_rcu_access_pointer(p) rcu_access_pointer(p)
-+#endif
-+
-+/* rhashtable */
-+#include "../os_dep/linux/rtw_rhashtable.h"
-+
-+typedef	int	_OS_STATUS;
-+/* typedef u32	_irqL; */
-+typedef unsigned long _irqL;
-+typedef	struct	net_device *_nic_hdl;
-+
-+typedef void		*_thread_hdl_;
-+typedef int		thread_return;
-+typedef void	*thread_context;
-+
-+typedef void timer_hdl_return;
-+typedef void *timer_hdl_context;
-+
-+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
-+	typedef struct work_struct _workitem;
-+#else
-+	typedef struct tq_struct _workitem;
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
-+	#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
-+#endif
-+
-+typedef unsigned long systime;
-+typedef ktime_t sysptime;
-+typedef struct tasklet_struct _tasklet;
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22))
-+/* Porting from linux kernel, for compatible with old kernel. */
-+static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb)
-+{
-+	return skb->tail;
-+}
-+
-+static inline void skb_reset_tail_pointer(struct sk_buff *skb)
-+{
-+	skb->tail = skb->data;
-+}
-+
-+static inline void skb_set_tail_pointer(struct sk_buff *skb, const int offset)
-+{
-+	skb->tail = skb->data + offset;
-+}
-+
-+static inline unsigned char *skb_end_pointer(const struct sk_buff *skb)
-+{
-+	return skb->end;
-+}
-+#endif
-+
-+__inline static void rtw_list_delete(_list *plist)
-+{
-+	list_del_init(plist);
-+}
-+
-+__inline static _list *get_next(_list	*list)
-+{
-+	return list->next;
-+}
-+
-+#define LIST_CONTAINOR(ptr, type, member) \
-+	((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
-+
-+#define rtw_list_first_entry(ptr, type, member) list_first_entry(ptr, type, member)
-+
-+#define rtw_hlist_for_each_entry(pos, head, member) hlist_for_each_entry(pos, head, member)
-+#define rtw_hlist_for_each_safe(pos, n, head) hlist_for_each_safe(pos, n, head)
-+#define rtw_hlist_entry(ptr, type, member) hlist_entry(ptr, type, member)
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
-+#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, n, head, member)
-+#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, head, member)
-+#else
-+#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, np, n, head, member)
-+#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, node, head, member)
-+#endif
-+
-+__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
-+{
-+	spin_lock_irqsave(plock, *pirqL);
-+}
-+
-+__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
-+{
-+	spin_unlock_irqrestore(plock, *pirqL);
-+}
-+
-+__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL)
-+{
-+	spin_lock_irqsave(plock, *pirqL);
-+}
-+
-+__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL)
-+{
-+	spin_unlock_irqrestore(plock, *pirqL);
-+}
-+
-+__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
-+{
-+	spin_lock_bh(plock);
-+}
-+
-+__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
-+{
-+	spin_unlock_bh(plock);
-+}
-+
-+__inline static void enter_critical_bh(_lock *plock)
-+{
-+	spin_lock_bh(plock);
-+}
-+
-+__inline static void exit_critical_bh(_lock *plock)
-+{
-+	spin_unlock_bh(plock);
-+}
-+
-+__inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
-+{
-+	int ret = 0;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
-+	/* mutex_lock(pmutex); */
-+	ret = mutex_lock_interruptible(pmutex);
-+#else
-+	ret = down_interruptible(pmutex);
-+#endif
-+	return ret;
-+}
-+
-+
-+__inline static int _enter_critical_mutex_lock(_mutex *pmutex, _irqL *pirqL)
-+{
-+	int ret = 0;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
-+	mutex_lock(pmutex);
-+#else
-+	down(pmutex);
-+#endif
-+	return ret;
-+}
-+
-+__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
-+	mutex_unlock(pmutex);
-+#else
-+	up(pmutex);
-+#endif
-+}
-+
-+__inline static _list	*get_list_head(_queue	*queue)
-+{
-+	return &(queue->queue);
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
-+static inline void timer_hdl(struct timer_list *in_timer)
-+#else
-+static inline void timer_hdl(unsigned long cntx)
-+#endif
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
-+	_timer *ptimer = from_timer(ptimer, in_timer, timer);
-+#else
-+	_timer *ptimer = (_timer *)cntx;
-+#endif
-+	ptimer->function(ptimer->arg);
-+}
-+
-+__inline static void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)
-+{
-+	ptimer->function = pfunc;
-+	ptimer->arg = cntx;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
-+	timer_setup(&ptimer->timer, timer_hdl, 0);
-+#else
-+	/* setup_timer(ptimer, pfunc,(u32)cntx);	 */
-+	ptimer->timer.function = timer_hdl;
-+	ptimer->timer.data = (unsigned long)ptimer;
-+	init_timer(&ptimer->timer);
-+#endif
-+}
-+
-+__inline static void _set_timer(_timer *ptimer, u32 delay_time)
-+{
-+	mod_timer(&ptimer->timer , (jiffies + (delay_time * HZ / 1000)));
-+}
-+
-+__inline static void _cancel_timer(_timer *ptimer, u8 *bcancelled)
-+{
-+	*bcancelled = del_timer_sync(&ptimer->timer) == 1 ? 1 : 0;
-+}
-+
-+__inline static void _cancel_timer_async(_timer *ptimer)
-+{
-+	del_timer(&ptimer->timer);
-+}
-+
-+static inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20))
-+	INIT_WORK(pwork, pfunc);
-+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
-+	INIT_WORK(pwork, pfunc, pwork);
-+#else
-+	INIT_TQUEUE(pwork, pfunc, pwork);
-+#endif
-+}
-+
-+__inline static void _set_workitem(_workitem *pwork)
-+{
-+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
-+	schedule_work(pwork);
-+#else
-+	schedule_task(pwork);
-+#endif
-+}
-+
-+__inline static void _cancel_workitem_sync(_workitem *pwork)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22))
-+	cancel_work_sync(pwork);
-+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
-+	flush_scheduled_work();
-+#else
-+	flush_scheduled_tasks();
-+#endif
-+}
-+/*
-+ * Global Mutex: can only be used at PASSIVE level.
-+ *   */
-+
-+#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \
-+	{                                                               \
-+		while (atomic_inc_return((atomic_t *)&(_MutexCounter)) != 1) { \
-+			atomic_dec((atomic_t *)&(_MutexCounter));        \
-+			msleep(10);                          \
-+		}                                                           \
-+	}
-+
-+#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \
-+	{                                                               \
-+		atomic_dec((atomic_t *)&(_MutexCounter));        \
-+	}
-+
-+static inline int rtw_netif_queue_stopped(struct net_device *pnetdev)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	return (netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) &&
-+		netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) &&
-+		netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) &&
-+		netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3)));
-+#else
-+	return netif_queue_stopped(pnetdev);
-+#endif
-+}
-+
-+static inline void rtw_netif_wake_queue(struct net_device *pnetdev)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	netif_tx_wake_all_queues(pnetdev);
-+#else
-+	netif_wake_queue(pnetdev);
-+#endif
-+}
-+
-+static inline void rtw_netif_start_queue(struct net_device *pnetdev)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	netif_tx_start_all_queues(pnetdev);
-+#else
-+	netif_start_queue(pnetdev);
-+#endif
-+}
-+
-+static inline void rtw_netif_stop_queue(struct net_device *pnetdev)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	netif_tx_stop_all_queues(pnetdev);
-+#else
-+	netif_stop_queue(pnetdev);
-+#endif
-+}
-+static inline void rtw_netif_device_attach(struct net_device *pnetdev)
-+{
-+	netif_device_attach(pnetdev);
-+}
-+static inline void rtw_netif_device_detach(struct net_device *pnetdev)
-+{
-+	netif_device_detach(pnetdev);
-+}
-+static inline void rtw_netif_carrier_on(struct net_device *pnetdev)
-+{
-+	netif_carrier_on(pnetdev);
-+}
-+static inline void rtw_netif_carrier_off(struct net_device *pnetdev)
-+{
-+	netif_carrier_off(pnetdev);
-+}
-+
-+static inline int rtw_merge_string(char *dst, int dst_len, const char *src1, const char *src2)
-+{
-+	int	len = 0;
-+	len += snprintf(dst + len, dst_len - len, "%s", src1);
-+	len += snprintf(dst + len, dst_len - len, "%s", src2);
-+
-+	return len;
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
-+	#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)), (sig), 1)
-+#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
-+	#define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1)
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
-+
-+
-+/* Suspend lock prevent system from going suspend */
-+#ifdef CONFIG_WAKELOCK
-+	#include <linux/wakelock.h>
-+#elif defined(CONFIG_ANDROID_POWER)
-+	#include <linux/android_power.h>
-+#endif
-+
-+/* limitation of path length */
-+#define PATH_LENGTH_MAX PATH_MAX
-+
-+/* Atomic integer operations */
-+#define ATOMIC_T atomic_t
-+
-+#define rtw_netdev_priv(netdev) (((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv)
-+
-+#define NDEV_FMT "%s"
-+#define NDEV_ARG(ndev) ndev->name
-+#define ADPT_FMT "%s"
-+#define ADPT_ARG(adapter) (adapter->pnetdev ? adapter->pnetdev->name : NULL)
-+#define FUNC_NDEV_FMT "%s(%s)"
-+#define FUNC_NDEV_ARG(ndev) __func__, ndev->name
-+#define FUNC_ADPT_FMT "%s(%s)"
-+#define FUNC_ADPT_ARG(adapter) __func__, (adapter->pnetdev ? adapter->pnetdev->name : NULL)
-+
-+struct rtw_netdev_priv_indicator {
-+	void *priv;
-+	u32 sizeof_priv;
-+};
-+struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv);
-+extern struct net_device *rtw_alloc_etherdev(int sizeof_priv);
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
-+#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(name)
-+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
-+#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(ndev->nd_net, name)
-+#else
-+#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(dev_net(ndev), name)
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
-+#define rtw_get_bridge_ndev_by_name(name) dev_get_by_name(name)
-+#else
-+#define rtw_get_bridge_ndev_by_name(name) dev_get_by_name(&init_net, name)
-+#endif
-+
-+#define STRUCT_PACKED __attribute__ ((packed))
-+
-+
-+#endif /* __OSDEP_LINUX_SERVICE_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/osdep_service_xp.h b/drivers/staging/rtl8723cs/include/osdep_service_xp.h
-new file mode 100644
-index 000000000000..57e6f314e20d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/osdep_service_xp.h
-@@ -0,0 +1,210 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __OSDEP_LINUX_SERVICE_H_
-+#define __OSDEP_LINUX_SERVICE_H_
-+
-+	#include <ndis.h>
-+	#include <ntddk.h>
-+	#include <ntddndis.h>
-+	#include <ntdef.h>
-+
-+#ifdef CONFIG_USB_HCI
-+	#include <usb.h>
-+	#include <usbioctl.h>
-+	#include <usbdlib.h>
-+#endif
-+
-+	typedef KSEMAPHORE 	_sema;
-+	typedef	LIST_ENTRY	_list;
-+	typedef NDIS_STATUS _OS_STATUS;
-+	
-+
-+	typedef NDIS_SPIN_LOCK	_lock;
-+
-+	typedef KMUTEX 			_mutex;
-+
-+	typedef KIRQL	_irqL;
-+
-+	// USB_PIPE for WINCE , but handle can be use just integer under windows
-+	typedef NDIS_HANDLE  _nic_hdl;
-+
-+	struct rtw_timer_list {
-+		NDIS_MINIPORT_TIMER ndis_timer;
-+		void (*function)(void *);
-+		void *arg;
-+	};
-+
-+	struct	__queue	{
-+		LIST_ENTRY	queue;	
-+		_lock	lock;
-+	};
-+
-+	typedef	NDIS_PACKET	_pkt;
-+	typedef NDIS_BUFFER	_buffer;
-+	typedef struct	__queue	_queue;
-+	
-+	typedef PKTHREAD _thread_hdl_;
-+	typedef void	thread_return;
-+	typedef void* thread_context;
-+
-+	typedef NDIS_WORK_ITEM _workitem;
-+
-+
-+	#define HZ			10000000
-+	#define SEMA_UPBND	(0x7FFFFFFF)   //8192
-+	
-+__inline static _list *get_next(_list	*list)
-+{
-+	return list->Flink;
-+}	
-+
-+__inline static _list	*get_list_head(_queue	*queue)
-+{
-+	return (&(queue->queue));
-+}
-+	
-+
-+#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
-+     
-+
-+__inline static _enter_critical(_lock *plock, _irqL *pirqL)
-+{
-+	NdisAcquireSpinLock(plock);	
-+}
-+
-+__inline static _exit_critical(_lock *plock, _irqL *pirqL)
-+{
-+	NdisReleaseSpinLock(plock);	
-+}
-+
-+
-+__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
-+{
-+	NdisDprAcquireSpinLock(plock);	
-+}
-+
-+__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
-+{
-+	NdisDprReleaseSpinLock(plock);	
-+}
-+
-+__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
-+{
-+	NdisDprAcquireSpinLock(plock);
-+}
-+
-+__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
-+{
-+	NdisDprReleaseSpinLock(plock);
-+}
-+
-+__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
-+{
-+	KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL);
-+}
-+
-+
-+__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
-+{
-+	KeReleaseMutex(pmutex, FALSE);
-+}
-+
-+
-+__inline static void rtw_list_delete(_list *plist)
-+{
-+	RemoveEntryList(plist);
-+	InitializeListHead(plist);	
-+}
-+
-+static inline void timer_hdl(
-+	IN PVOID SystemSpecific1,
-+	IN PVOID FunctionContext,
-+	IN PVOID SystemSpecific2,
-+	IN PVOID SystemSpecific3)
-+{
-+	_timer *timer = (_timer *)FunctionContext;
-+
-+	timer->function(timer->arg);
-+}
-+
-+static inline void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)
-+{
-+	ptimer->function = pfunc;
-+	ptimer->arg = cntx;
-+	NdisMInitializeTimer(&ptimer->ndis_timer, nic_hdl, timer_hdl, ptimer);
-+}
-+
-+static inline void _set_timer(_timer *ptimer, u32 delay_time)
-+{
-+	NdisMSetTimer(ptimer, delay_time);
-+}
-+
-+static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)
-+{
-+	NdisMCancelTimer(ptimer, bcancelled);
-+}
-+
-+__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
-+{
-+
-+	NdisInitializeWorkItem(pwork, pfunc, cntx);
-+}
-+
-+__inline static void _set_workitem(_workitem *pwork)
-+{
-+	NdisScheduleWorkItem(pwork);
-+}
-+
-+
-+#define ATOMIC_INIT(i)  { (i) }
-+
-+//
-+// Global Mutex: can only be used at PASSIVE level.
-+//
-+
-+#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter)                              \
-+{                                                               \
-+    while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
-+    {                                                           \
-+        NdisInterlockedDecrement((PULONG)&(_MutexCounter));        \
-+        NdisMSleep(10000);                          \
-+    }                                                           \
-+}
-+
-+#define RELEASE_GLOBAL_MUTEX(_MutexCounter)                              \
-+{                                                               \
-+    NdisInterlockedDecrement((PULONG)&(_MutexCounter));              \
-+}
-+
-+// limitation of path length
-+#define PATH_LENGTH_MAX MAX_PATH
-+
-+//Atomic integer operations
-+#define ATOMIC_T LONG
-+
-+
-+#define NDEV_FMT "%s"
-+#define NDEV_ARG(ndev) ""
-+#define ADPT_FMT "%s"
-+#define ADPT_ARG(adapter) ""
-+#define FUNC_NDEV_FMT "%s"
-+#define FUNC_NDEV_ARG(ndev) __func__
-+#define FUNC_ADPT_FMT "%s"
-+#define FUNC_ADPT_ARG(adapter) __func__
-+
-+#define STRUCT_PACKED
-+
-+#endif
-+
-diff --git a/drivers/staging/rtl8723cs/include/pci_hal.h b/drivers/staging/rtl8723cs/include/pci_hal.h
-new file mode 100644
-index 000000000000..6eac311a13d1
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/pci_hal.h
-@@ -0,0 +1,60 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __PCI_HAL_H__
-+#define __PCI_HAL_H__
-+
-+#ifdef CONFIG_RTL8188E
-+	void rtl8188ee_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+	void rtl8812ae_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8192E)
-+	void rtl8192ee_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8192F)
-+	void rtl8192fe_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8723B
-+	void rtl8723be_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	void rtl8723de_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	void rtl8814ae_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	void rtl8822be_set_hal_ops(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8822C
-+	void rtl8822ce_set_hal_ops(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8814B
-+	void rtl8814be_set_hal_ops(PADAPTER padapter);
-+#endif
-+
-+u8 rtw_set_hal_ops(_adapter *padapter);
-+
-+#endif /* __PCIE_HAL_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/pci_ops.h b/drivers/staging/rtl8723cs/include/pci_ops.h
-new file mode 100644
-index 000000000000..7b95fde04a7c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/pci_ops.h
-@@ -0,0 +1,116 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __PCI_OPS_H_
-+#define __PCI_OPS_H_
-+
-+
-+#ifdef CONFIG_RTL8188E
-+	u32	rtl8188ee_init_desc_ring(_adapter *padapter);
-+	u32	rtl8188ee_free_desc_ring(_adapter *padapter);
-+	void	rtl8188ee_reset_desc_ring(_adapter *padapter);
-+	int	rtl8188ee_interrupt(PADAPTER Adapter);
-+	void	rtl8188ee_xmit_tasklet(void *priv);
-+	void	rtl8188ee_recv_tasklet(void *priv);
-+	void	rtl8188ee_prepare_bcn_tasklet(void *priv);
-+	void	rtl8188ee_set_intf_ops(struct _io_ops	*pops);
-+	void	rtw8188ee_unmap_beacon_icf(_adapter *padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+	u32	rtl8812ae_init_desc_ring(_adapter *padapter);
-+	u32	rtl8812ae_free_desc_ring(_adapter *padapter);
-+	void	rtl8812ae_reset_desc_ring(_adapter *padapter);
-+	int	rtl8812ae_interrupt(PADAPTER Adapter);
-+	void	rtl8812ae_xmit_tasklet(void *priv);
-+	void	rtl8812ae_recv_tasklet(void *priv);
-+	void	rtl8812ae_prepare_bcn_tasklet(void *priv);
-+	void	rtl8812ae_set_intf_ops(struct _io_ops	*pops);
-+	void	rtw8812ae_unmap_beacon_icf(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+	u32	rtl8192ee_init_desc_ring(_adapter *padapter);
-+	u32	rtl8192ee_free_desc_ring(_adapter *padapter);
-+	void	rtl8192ee_reset_desc_ring(_adapter *padapter);
-+	void	rtl8192ee_recv_tasklet(void *priv);
-+	void	rtl8192ee_prepare_bcn_tasklet(void *priv);
-+	int	rtl8192ee_interrupt(PADAPTER Adapter);
-+	void	rtl8192ee_set_intf_ops(struct _io_ops	*pops);
-+	void	rtw8192ee_unmap_beacon_icf(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8192F
-+	u32	rtl8192fe_init_desc_ring(_adapter *padapter);
-+	u32	rtl8192fe_free_desc_ring(_adapter *padapter);
-+	void	rtl8192fe_reset_desc_ring(_adapter *padapter);
-+	int	rtl8192fe_interrupt(PADAPTER Adapter);
-+	void	rtl8192fe_recv_tasklet(void *priv);
-+	void	rtl8192fe_prepare_bcn_tasklet(void *priv);
-+	void	rtl8192fe_set_intf_ops(struct _io_ops	*pops);
-+	u8 check_tx_desc_resource(_adapter *padapter, int prio);
-+	void	rtl8192fe_unmap_beacon_icf(PADAPTER Adapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8723B
-+	u32	rtl8723be_init_desc_ring(_adapter *padapter);
-+	u32	rtl8723be_free_desc_ring(_adapter *padapter);
-+	void	rtl8723be_reset_desc_ring(_adapter *padapter);
-+	int	rtl8723be_interrupt(PADAPTER Adapter);
-+	void	rtl8723be_recv_tasklet(void *priv);
-+	void	rtl8723be_prepare_bcn_tasklet(void *priv);
-+	void	rtl8723be_set_intf_ops(struct _io_ops	*pops);
-+	void	rtl8723be_unmap_beacon_icf(PADAPTER Adapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	u32	rtl8723de_init_desc_ring(_adapter *padapter);
-+	u32	rtl8723de_free_desc_ring(_adapter *padapter);
-+	void	rtl8723de_reset_desc_ring(_adapter *padapter);
-+	int	rtl8723de_interrupt(PADAPTER Adapter);
-+	void	rtl8723de_recv_tasklet(void *priv);
-+	void	rtl8723de_prepare_bcn_tasklet(void *priv);
-+	void	rtl8723de_set_intf_ops(struct _io_ops	*pops);
-+	u8 check_tx_desc_resource(_adapter *padapter, int prio);
-+	void 	rtl8723de_unmap_beacon_icf(PADAPTER Adapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+	u32	rtl8814ae_init_desc_ring(_adapter *padapter);
-+	u32	rtl8814ae_free_desc_ring(_adapter *padapter);
-+	void	rtl8814ae_reset_desc_ring(_adapter *padapter);
-+	int	rtl8814ae_interrupt(PADAPTER Adapter);
-+	void	rtl8814ae_xmit_tasklet(void *priv);
-+	void	rtl8814ae_recv_tasklet(void *priv);
-+	void	rtl8814ae_prepare_bcn_tasklet(void *priv);
-+	void	rtl8814ae_set_intf_ops(struct _io_ops	*pops);
-+	void	rtl8814ae_unmap_beacon_icf(PADAPTER Adapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	void rtl8822be_set_intf_ops(struct _io_ops *pops);
-+#endif
-+
-+#ifdef CONFIG_RTL8821C
-+	void rtl8821ce_set_intf_ops(struct _io_ops *pops);
-+#endif
-+
-+#ifdef CONFIG_RTL8822C
-+	void rtl8822ce_set_intf_ops(struct _io_ops *pops);
-+#endif
-+
-+#ifdef CONFIG_RTL8814B
-+	void rtl8814be_set_intf_ops(struct _io_ops *pops);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/pci_osintf.h b/drivers/staging/rtl8723cs/include/pci_osintf.h
-new file mode 100644
-index 000000000000..077064a725bc
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/pci_osintf.h
-@@ -0,0 +1,66 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __PCI_OSINTF_H
-+#define __PCI_OSINTF_H
-+
-+#ifdef CONFIG_PLATFORM_RTK129X
-+#define PCIE_SLOT1_MEM_START	0x9804F000
-+#define PCIE_SLOT1_MEM_LEN	0x1000
-+#define PCIE_SLOT1_CTRL_START	0x9804EC00
-+
-+#define PCIE_SLOT2_MEM_START	0x9803C000
-+#define PCIE_SLOT2_MEM_LEN	0x1000
-+#define PCIE_SLOT2_CTRL_START	0x9803BC00
-+
-+#define PCIE_MASK_OFFSET	0x100 /* mask offset from CTRL_START */
-+#define PCIE_TRANSLATE_OFFSET	0x104 /* translate offset from CTRL_START */
-+#endif
-+
-+#define PCI_BC_CLK_REQ		BIT0
-+#define PCI_BC_ASPM_L0s		BIT1
-+#define PCI_BC_ASPM_L1		BIT2
-+#define PCI_BC_ASPM_L1Off	BIT3
-+//#define PCI_BC_ASPM_LTR	BIT4
-+//#define PCI_BC_ASPM_OBFF	BIT5
-+
-+void	PlatformClearPciPMEStatus(PADAPTER Adapter);
-+void	rtw_pci_aspm_config(_adapter *padapter);
-+void	rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 eanble);
-+#ifdef CONFIG_PCI_DYNAMIC_ASPM
-+void rtw_pci_set_aspm_lnkctl(_adapter *padapter, u8 mode);
-+void rtw_pci_set_l1_latency(_adapter *padapter, u8 mode);
-+
-+static inline void rtw_pci_dynamic_aspm_set_mode(_adapter *padapter, u8 mode)
-+{
-+	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct pci_priv	*pcipriv = &(pdvobjpriv->pcipriv);
-+
-+	if (mode == pcipriv->aspm_mode)
-+		return;
-+
-+	pcipriv->aspm_mode = mode;
-+
-+#ifdef CONFIG_PCI_DYNAMIC_ASPM_LINK_CTRL
-+	rtw_pci_set_aspm_lnkctl(padapter, mode);
-+#endif
-+#ifdef CONFIG_PCI_DYNAMIC_ASPM_L1_LATENCY
-+	rtw_pci_set_l1_latency(padapter, mode);
-+#endif
-+}
-+#else
-+#define rtw_pci_dynamic_aspm_set_mode(adapter, mode)
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/recv_osdep.h b/drivers/staging/rtl8723cs/include/recv_osdep.h
-new file mode 100644
-index 000000000000..4521c007f0a0
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/recv_osdep.h
-@@ -0,0 +1,70 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RECV_OSDEP_H_
-+#define __RECV_OSDEP_H_
-+
-+
-+extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter);
-+extern void _rtw_free_recv_priv(struct recv_priv *precvpriv);
-+
-+
-+extern s32  rtw_recv_entry(union recv_frame *precv_frame);
-+void rtw_rframe_set_os_pkt(union recv_frame *rframe);
-+extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame);
-+extern void rtw_recv_returnpacket(_nic_hdl cnxt, _pkt *preturnedpkt);
-+
-+#ifdef CONFIG_WIFI_MONITOR
-+extern int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame);
-+#endif /* CONFIG_WIFI_MONITOR */
-+
-+#ifdef CONFIG_HOSTAPD_MLME
-+extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame);
-+#endif
-+
-+struct sta_info;
-+extern void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup);
-+
-+
-+int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter);
-+int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe);
-+void rtw_os_recv_resource_free(struct recv_priv *precvpriv);
-+
-+
-+int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb);
-+int rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pcloneframe, _pkt *pskb);
-+void rtw_os_free_recvframe(union recv_frame *precvframe);
-+
-+
-+int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf, u32 size);
-+int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf);
-+
-+_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa
-+	, u8 *msdu ,u16 msdu_len, enum rtw_rx_llc_hdl llc_hdl);
-+void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe);
-+
-+void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf);
-+
-+#ifdef PLATFORM_LINUX
-+#ifdef CONFIG_RTW_NAPI
-+#include <linux/netdevice.h>	/* struct napi_struct */
-+
-+int rtw_recv_napi_poll(struct napi_struct *, int budget);
-+#ifdef CONFIG_RTW_NAPI_DYNAMIC
-+void dynamic_napi_th_chk (_adapter *adapter);
-+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
-+#endif /* CONFIG_RTW_NAPI */
-+#endif /* PLATFORM_LINUX */
-+
-+#endif /*  */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188e_cmd.h b/drivers/staging/rtl8723cs/include/rtl8188e_cmd.h
-new file mode 100644
-index 000000000000..aba0bec14769
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188e_cmd.h
-@@ -0,0 +1,165 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188E_CMD_H__
-+#define __RTL8188E_CMD_H__
-+
-+#if 0
-+enum cmd_msg_element_id {
-+	NONE_CMDMSG_EID,
-+	AP_OFFLOAD_EID = 0,
-+	SET_PWRMODE_EID = 1,
-+	JOINBSS_RPT_EID = 2,
-+	RSVD_PAGE_EID = 3,
-+	RSSI_4_EID = 4,
-+	RSSI_SETTING_EID = 5,
-+	MACID_CONFIG_EID = 6,
-+	MACID_PS_MODE_EID = 7,
-+	P2P_PS_OFFLOAD_EID = 8,
-+	SELECTIVE_SUSPEND_ROF_CMD = 9,
-+	P2P_PS_CTW_CMD_EID = 32,
-+	MAX_CMDMSG_EID
-+};
-+#else
-+typedef enum _RTL8188E_H2C_CMD_ID {
-+	/* Class Common */
-+	H2C_COM_RSVD_PAGE			= 0x00,
-+	H2C_COM_MEDIA_STATUS_RPT	= 0x01,
-+	H2C_COM_SCAN					= 0x02,
-+	H2C_COM_KEEP_ALIVE			= 0x03,
-+	H2C_COM_DISCNT_DECISION		= 0x04,
-+#ifndef CONFIG_WOWLAN
-+	H2C_COM_WWLAN				= 0x05,
-+#endif
-+	H2C_COM_INIT_OFFLOAD			= 0x06,
-+	H2C_COM_REMOTE_WAKE_CTL	= 0x07,
-+	H2C_COM_AP_OFFLOAD			= 0x08,
-+	H2C_COM_BCN_RSVD_PAGE		= 0x09,
-+	H2C_COM_PROB_RSP_RSVD_PAGE	= 0x0A,
-+
-+	/* Class PS */
-+	H2C_PS_PWR_MODE				= 0x20,
-+	H2C_PS_TUNE_PARA				= 0x21,
-+	H2C_PS_TUNE_PARA_2			= 0x22,
-+	H2C_PS_LPS_PARA				= 0x23,
-+	H2C_PS_P2P_OFFLOAD			= 0x24,
-+
-+	/* Class DM */
-+	H2C_DM_MACID_CFG				= 0x40,
-+	H2C_DM_TXBF					= 0x41,
-+	H2C_RSSI_REPORT				= 0x42,
-+	/* Class BT */
-+	H2C_BT_COEX_MASK				= 0x60,
-+	H2C_BT_COEX_GPIO_MODE		= 0x61,
-+	H2C_BT_DAC_SWING_VAL			= 0x62,
-+	H2C_BT_PSD_RST				= 0x63,
-+
-+	/* Class Remote WakeUp */
-+#ifdef CONFIG_WOWLAN
-+	H2C_COM_WWLAN				= 0x80,
-+	H2C_COM_REMOTE_WAKE_CTRL	= 0x81,
-+	H2C_COM_AOAC_GLOBAL_INFO	= 0x82,
-+	H2C_COM_AOAC_RSVD_PAGE		= 0x83,
-+#endif
-+
-+	/* Class */
-+	/* H2C_RESET_TSF				=0xc0, */
-+} RTL8188E_H2C_CMD_ID;
-+
-+#endif
-+
-+
-+struct cmd_msg_parm {
-+	u8 eid; /* element id */
-+	u8 sz; /* sz */
-+	u8 buf[6];
-+};
-+
-+enum {
-+	PWRS
-+};
-+
-+typedef struct _SETPWRMODE_PARM {
-+	u8 Mode;/* 0:Active,1:LPS,2:WMMPS */
-+	/* u8 RLBM:4; */ /* 0:Min,1:Max,2: User define */
-+	u8 SmartPS_RLBM;/* LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData */
-+	u8 AwakeInterval;	/* unit: beacon interval */
-+	u8 bAllQueueUAPSD;
-+	u8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */
-+} SETPWRMODE_PARM, *PSETPWRMODE_PARM;
-+
-+struct H2C_SS_RFOFF_PARAM {
-+	u8 ROFOn; /* 1: on, 0:off */
-+	u16 gpio_period; /* unit: 1024 us */
-+} __attribute__((packed));
-+
-+
-+typedef struct JOINBSSRPT_PARM_88E {
-+	u8 OpMode;	/* RT_MEDIA_STATUS */
-+#ifdef CONFIG_WOWLAN
-+	u8 MacID;       /* MACID */
-+#endif /* CONFIG_WOWLAN */
-+} JOINBSSRPT_PARM_88E, *PJOINBSSRPT_PARM_88E;
-+
-+#if 0
-+/* move to hal_com_h2c.h */
-+typedef struct _RSVDPAGE_LOC_88E {
-+	u8 LocProbeRsp;
-+	u8 LocPsPoll;
-+	u8 LocNullData;
-+	u8 LocQosNull;
-+	u8 LocBTQosNull;
-+#ifdef CONFIG_WOWLAN
-+	u8 LocRemoteCtrlInfo;
-+	u8 LocArpRsp;
-+	u8 LocNbrAdv;
-+	u8 LocGTKRsp;
-+	u8 LocGTKInfo;
-+	u8 LocProbeReq;
-+	u8 LocNetList;
-+#endif /* CONFIG_WOWLAN	 */
-+} RSVDPAGE_LOC_88E, *PRSVDPAGE_LOC_88E;
-+#endif
-+
-+/* host message to firmware cmd */
-+void rtl8188e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
-+void rtl8188e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
-+s32 FillH2CCmd_88E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
-+/* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */
-+u8 GetTxBufferRsvdPageNum8188E(_adapter *padapter, bool wowlan);
-+
-+
-+#ifdef CONFIG_P2P
-+	void rtl8188e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
-+#endif /* CONFIG_P2P */
-+
-+/* #define H2C_8188E_RSVDPAGE_LOC_LEN      5 */
-+/* #define H2C_8188E_AOAC_RSVDPAGE_LOC_LEN 7 */
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
-+ * ---------------------------------------------------------------------------------------------------------
-+ *   */
-+#if 0
-+	/* move to hal_com_h2c.h
-+	* _RSVDPAGE_LOC_CMD_0x00 */
-+	#define SET_8188E_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)     SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+	#define SET_8188E_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)            SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+	#define SET_8188E_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)     SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+	#define SET_8188E_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)     SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+	/*  AOAC_RSVDPAGE_LOC_0x83 */
-+	#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value)        SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
-+	#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value)                  SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#endif
-+#endif/* __RTL8188E_CMD_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188e_dm.h b/drivers/staging/rtl8723cs/include/rtl8188e_dm.h
-new file mode 100644
-index 000000000000..457ae9bcab1f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188e_dm.h
-@@ -0,0 +1,27 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188E_DM_H__
-+#define __RTL8188E_DM_H__
-+
-+void rtl8188e_init_dm_priv(PADAPTER Adapter);
-+void rtl8188e_deinit_dm_priv(PADAPTER Adapter);
-+void rtl8188e_InitHalDm(PADAPTER Adapter);
-+void rtl8188e_HalDmWatchDog(PADAPTER Adapter);
-+
-+/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
-+
-+/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188e_hal.h b/drivers/staging/rtl8723cs/include/rtl8188e_hal.h
-new file mode 100644
-index 000000000000..9665896d57ed
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188e_hal.h
-@@ -0,0 +1,321 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188E_HAL_H__
-+#define __RTL8188E_HAL_H__
-+
-+/* #include "hal_com.h" */
-+#include "hal_data.h"
-+
-+/* include HAL Related header after HAL Related compiling flags */
-+#include "rtl8188e_spec.h"
-+#include "Hal8188EPhyReg.h"
-+#include "Hal8188EPhyCfg.h"
-+#include "rtl8188e_rf.h"
-+#include "rtl8188e_dm.h"
-+#include "rtl8188e_recv.h"
-+#include "rtl8188e_xmit.h"
-+#include "rtl8188e_cmd.h"
-+#include "rtl8188e_led.h"
-+#include "Hal8188EPwrSeq.h"
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	#include "rtl8188e_sreset.h"
-+#endif
-+
-+/* --------------------------------------------------------------------- */
-+/*		RTL8188E Power Configuration CMDs for USB/SDIO/PCIE interfaces */
-+/* --------------------------------------------------------------------- */
-+#define Rtl8188E_NIC_PWR_ON_FLOW				rtl8188E_power_on_flow
-+#define Rtl8188E_NIC_RF_OFF_FLOW				rtl8188E_radio_off_flow
-+#define Rtl8188E_NIC_DISABLE_FLOW				rtl8188E_card_disable_flow
-+#define Rtl8188E_NIC_ENABLE_FLOW				rtl8188E_card_enable_flow
-+#define Rtl8188E_NIC_SUSPEND_FLOW				rtl8188E_suspend_flow
-+#define Rtl8188E_NIC_RESUME_FLOW				rtl8188E_resume_flow
-+#define Rtl8188E_NIC_PDN_FLOW					rtl8188E_hwpdn_flow
-+#define Rtl8188E_NIC_LPS_ENTER_FLOW			rtl8188E_enter_lps_flow
-+#define Rtl8188E_NIC_LPS_LEAVE_FLOW			rtl8188E_leave_lps_flow
-+
-+
-+#if 1 /* download firmware related data structure */
-+#define MAX_FW_8188E_SIZE			0x8000 /* 32768, 32k / 16384, 16k */
-+
-+#define FW_8188E_SIZE				0x4000 /* 16384, 16k */
-+#define FW_8188E_SIZE_2			0x8000 /* 32768, 32k */
-+
-+#define FW_8188E_START_ADDRESS	0x1000
-+#define FW_8188E_END_ADDRESS		0x1FFF /* 0x5FFF */
-+
-+
-+#define IS_FW_HEADER_EXIST_88E(_pFwHdr)	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x88E0)
-+
-+typedef struct _RT_FIRMWARE_8188E {
-+	FIRMWARE_SOURCE	eFWSource;
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+	u8			*szFwBuffer;
-+#else
-+	u8			szFwBuffer[MAX_FW_8188E_SIZE];
-+#endif
-+	u32			ulFwLength;
-+} RT_FIRMWARE_8188E, *PRT_FIRMWARE_8188E;
-+
-+/*
-+ * This structure must be cared byte-ordering
-+ *   */
-+
-+typedef struct _RT_8188E_FIRMWARE_HDR {
-+	/* 8-byte alinment required */
-+
-+	/* --- LONG WORD 0 ---- */
-+	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
-+	u8		Category;	/* AP/NIC and USB/PCI */
-+	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
-+	u16		Version;		/* FW Version */
-+	u8		Subversion;	/* FW Subversion, default 0x00 */
-+	u16		Rsvd1;
-+
-+
-+	/* --- LONG WORD 1 ---- */
-+	u8		Month;	/* Release time Month field */
-+	u8		Date;	/* Release time Date field */
-+	u8		Hour;	/* Release time Hour field */
-+	u8		Minute;	/* Release time Minute field */
-+	u16		RamCodeSize;	/* The size of RAM code */
-+	u8		Foundry;
-+	u8		Rsvd2;
-+
-+	/* --- LONG WORD 2 ---- */
-+	u32		SvnIdx;	/* The SVN entry index */
-+	u32		Rsvd3;
-+
-+	/* --- LONG WORD 3 ---- */
-+	u32		Rsvd4;
-+	u32		Rsvd5;
-+} RT_8188E_FIRMWARE_HDR, *PRT_8188E_FIRMWARE_HDR;
-+#endif /* download firmware related data structure */
-+
-+
-+#define DRIVER_EARLY_INT_TIME_8188E			0x05
-+#define BCN_DMA_ATIME_INT_TIME_8188E		0x02
-+
-+
-+/* #define MAX_RX_DMA_BUFFER_SIZE_88E	      0x2400 */ /* 9k for 88E nornal chip , */ /* MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */
-+#ifdef CONFIG_USB_HCI
-+	#define RX_DMA_SIZE_88E(__Adapter) 0x2800
-+#else
-+	#define RX_DMA_SIZE_88E(__Adapter) ((!IS_VENDOR_8188E_I_CUT_SERIES(__Adapter))?0x2800:0x4000)
-+#endif
-+
-+#ifdef CONFIG_WOWLAN
-+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
-+#else
-+	#define RESV_FMWF	0
-+#endif
-+
-+#define RX_DMA_RESERVD_FW_FEATURE	0x200 /* for tx report (64*8) */
-+
-+#define MAX_RX_DMA_BUFFER_SIZE_88E(__Adapter) (RX_DMA_SIZE_88E(__Adapter)-RX_DMA_RESERVD_FW_FEATURE)
-+
-+#define MAX_TX_REPORT_BUFFER_SIZE			0x0400 /* 1k */
-+
-+#define PAGE_SIZE_TX_88E PAGE_SIZE_128
-+/* Note: We will divide number of page equally for each queue other than public queue!
-+ * 22k = 22528 bytes = 176 pages (@page =  128 bytes)
-+ * BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_88E
-+ * 1 ps-poll / 1 null-data /1 prob_rsp /1 QOS null-data = 4 pages */
-+
-+#define BCNQ_PAGE_NUM_88E		(MAX_BEACON_LEN / PAGE_SIZE_TX_88E + 4) /*0x09*/
-+
-+/* For WoWLan , more reserved page */
-+#ifdef CONFIG_WOWLAN
-+	#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+	#define WOWLAN_KEEP_ALIVE_PAGE 0x02 /*for keep alive packet*/
-+	#else
-+	#define WOWLAN_KEEP_ALIVE_PAGE	0x00
-+	#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+	/* 1 ArpRsp + 2 NbrAdv + 2 NDPInfo + 1 RCI + 1 AOAC = 7 pages */
-+	#define WOWLAN_PAGE_NUM_88E	(0x07+ WOWLAN_KEEP_ALIVE_PAGE)
-+#else
-+	#define WOWLAN_PAGE_NUM_88E	0x00
-+#endif
-+
-+/* Note:
-+Tx FIFO Size : previous CUT:22K /I_CUT after:32KB
-+Tx page Size : 128B
-+Total page numbers : 176(0xB0) / 256(0x100)
-+*/
-+#ifdef CONFIG_USB_HCI
-+	#define TOTAL_PAGE_NUMBER_88E(_Adapter) (0xB0 - 1)
-+#else
-+	#define TOTAL_PAGE_NUMBER_88E(_Adapter)	((IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)?0x100:0xB0) - 1)/* must reserved 1 page for dma issue */
-+#endif
-+#define TX_TOTAL_PAGE_NUMBER_88E(_Adapter)	(TOTAL_PAGE_NUMBER_88E(_Adapter) - BCNQ_PAGE_NUM_88E - WOWLAN_PAGE_NUM_88E)
-+#define TX_PAGE_BOUNDARY_88E(_Adapter)		(TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1) /* beacon header start address */
-+
-+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_88E(_Adapter)	TX_TOTAL_PAGE_NUMBER_88E(_Adapter)
-+#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E(_Adapter)		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1)
-+
-+/* For Normal Chip Setting
-+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723B */
-+#define NORMAL_PAGE_NUM_HPQ_88E		0x0
-+#define NORMAL_PAGE_NUM_LPQ_88E		0x09
-+#define NORMAL_PAGE_NUM_NPQ_88E		0x0
-+
-+/* Note: For Normal Chip Setting, modify later */
-+#define WMM_NORMAL_PAGE_NUM_HPQ_88E		0x29
-+#define WMM_NORMAL_PAGE_NUM_LPQ_88E		0x1C
-+#define WMM_NORMAL_PAGE_NUM_NPQ_88E		0x1C
-+
-+
-+/* -------------------------------------------------------------------------
-+ *	Chip specific
-+ * ------------------------------------------------------------------------- */
-+#define CHIP_BONDING_IDENTIFIER(_value)	(((_value)>>22) & 0x3)
-+#define CHIP_BONDING_92C_1T2R	0x1
-+#define CHIP_BONDING_88C_USB_MCARD	0x2
-+#define CHIP_BONDING_88C_USB_HP	0x1
-+
-+/* -------------------------------------------------------------------------
-+ *	Channel Plan
-+ * ------------------------------------------------------------------------- */
-+
-+
-+#define EFUSE_REAL_CONTENT_LEN		512
-+#define EFUSE_MAP_LEN				128
-+#define EFUSE_MAX_SECTION			16
-+#define EFUSE_IC_ID_OFFSET			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
-+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN)
-+/*
-+ * <Roger_Notes>
-+ * To prevent out of boundary programming case,
-+ * leave 1byte and program full section
-+ * 9bytes + 1byt + 5bytes and pre 1byte.
-+ * For worst case:
-+ * | 1byte|----8bytes----|1byte|--5bytes--|
-+ * |         |            Reserved(14bytes)	      |
-+ *   */
-+#define EFUSE_OOB_PROTECT_BYTES 		15	/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
-+
-+#define		EFUSE_REAL_CONTENT_LEN_88E	256
-+#define		EFUSE_MAP_LEN_88E		512
-+#define		EFUSE_MAX_SECTION_88E		64
-+#define		EFUSE_MAX_WORD_UNIT_88E		4
-+#define		EFUSE_IC_ID_OFFSET_88E			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
-+#define		AVAILABLE_EFUSE_ADDR_88E(addr)	(addr < EFUSE_REAL_CONTENT_LEN_88E)
-+/* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
-+ * 9bytes + 1byt + 5bytes and pre 1byte.
-+ * For worst case:
-+ * | 2byte|----8bytes----|1byte|--7bytes--|  */ /* 92D */
-+#define 		EFUSE_OOB_PROTECT_BYTES_88E	18	/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
-+#define		EFUSE_PROTECT_BYTES_BANK_88E	16
-+
-+
-+/* ********************************************************
-+ *			EFUSE for BT definition
-+ * ******************************************************** */
-+#define EFUSE_BT_REAL_CONTENT_LEN		1536	/* 512*3 */
-+#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
-+#define EFUSE_BT_MAX_SECTION			128		/* 1024/8 */
-+
-+#define EFUSE_PROTECT_BYTES_BANK		16
-+
-+#define INCLUDE_MULTI_FUNC_BT(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
-+#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
-+
-+/* #define IS_MULTI_FUNC_CHIP(_Adapter)	(((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */
-+
-+/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */
-+
-+#ifdef CONFIG_PCI_HCI
-+	/* according to the define in the rtw_xmit.h, rtw_recv.h */
-+	#define TX_DESC_NUM_8188EE  TXDESC_NUM   /* 128 */
-+	#ifdef CONFIG_CONCURRENT_MODE
-+		/*#define BE_QUEUE_TX_DESC_NUM_8188EE  (TXDESC_NUM<<1)*/		/* 256 */
-+		#define BE_QUEUE_TX_DESC_NUM_8188EE  ((TXDESC_NUM<<1)+(TXDESC_NUM>>1))    /* 320 */
-+		/*#define BE_QUEUE_TX_DESC_NUM_8188EE  ((TXDESC_NUM<<1)+TXDESC_NUM)*/    /* 384 */
-+	#else
-+		#define BE_QUEUE_TX_DESC_NUM_8188EE  TXDESC_NUM /* 128 */
-+		/*#define BE_QUEUE_TX_DESC_NUM_8188EE  (TXDESC_NUM+(TXDESC_NUM>>1)) */ /* 192 */
-+	#endif
-+
-+	void InterruptRecognized8188EE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
-+	void UpdateInterruptMask8188EE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
-+#endif /* CONFIG_PCI_HCI */
-+
-+/* rtl8188e_hal_init.c */
-+
-+s32 rtl8188e_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
-+void _8051Reset88E(PADAPTER padapter);
-+void rtl8188e_InitializeFirmwareVars(PADAPTER padapter);
-+
-+
-+s32 InitLLTTable(PADAPTER padapter, u8 txpktbuf_bndy);
-+
-+/* EFuse */
-+u8 GetEEPROMSize8188E(PADAPTER padapter);
-+void Hal_InitPGData88E(PADAPTER padapter);
-+void Hal_EfuseParseIDCode88E(PADAPTER padapter, u8 *hwinfo);
-+void Hal_ReadTxPowerInfo88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
-+
-+void Hal_EfuseParseEEPROMVer88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void rtl8188e_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseCustomerID88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_ReadAntennaDiversity88E(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
-+void Hal_ReadThermalMeter_88E(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN	AutoloadFail);
-+void Hal_EfuseParseXtal_8188E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseBoardType88E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_ReadPowerSavingMode88E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_ReadPAType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+void Hal_ReadAmplifierType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+void Hal_ReadRFEType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+
-+BOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter);
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+	void Hal_DetectWoWMode(PADAPTER pAdapter);
-+#endif /* CONFIG_WOWLAN */
-+
-+
-+#ifdef CONFIG_RF_POWER_TRIM
-+	void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+#endif /*CONFIG_RF_POWER_TRIM*/
-+
-+
-+void InitBeaconParameters_8188e(_adapter *adapter);
-+void SetBeaconRelatedRegisters8188E(PADAPTER padapter);
-+
-+void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc);
-+void init_hal_spec_8188e(_adapter *adapter);
-+
-+void rtl8188e_start_thread(_adapter *padapter);
-+void rtl8188e_stop_thread(_adapter *padapter);
-+
-+void rtw_IOL_cmd_tx_pkt_buf_dump(ADAPTER *Adapter, int data_len);
-+#ifdef CONFIG_IOL_EFUSE_PATCH
-+	s32 rtl8188e_iol_efuse_patch(PADAPTER padapter);
-+#endif/* CONFIG_IOL_EFUSE_PATCH */
-+void _InitTransferPageSize(PADAPTER padapter);
-+
-+u8 SetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val);
-+void GetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val);
-+
-+u8
-+GetHalDefVar8188E(
-+		PADAPTER				Adapter,
-+		HAL_DEF_VARIABLE		eVariable,
-+		void						*pValue
-+);
-+#ifdef CONFIG_GPIO_API
-+int rtl8188e_GpioFuncCheck(PADAPTER adapter, u8 gpio_num);
-+#endif
-+#endif /* __RTL8188E_HAL_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188e_led.h b/drivers/staging/rtl8723cs/include/rtl8188e_led.h
-new file mode 100644
-index 000000000000..ef054675024a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188e_led.h
-@@ -0,0 +1,37 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188E_LED_H__
-+#define __RTL8188E_LED_H__
-+
-+#ifdef CONFIG_RTW_SW_LED
-+
-+/* ********************************************************************************
-+ * Interface to manipulate LED objects.
-+ * ******************************************************************************** */
-+#ifdef CONFIG_USB_HCI
-+	void rtl8188eu_InitSwLeds(PADAPTER padapter);
-+	void rtl8188eu_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+	void rtl8188ee_InitSwLeds(PADAPTER padapter);
-+	void rtl8188ee_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	void rtl8188es_InitSwLeds(PADAPTER padapter);
-+	void rtl8188es_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+
-+#endif
-+#endif /*CONFIG_RTW_SW_LED*/
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188e_recv.h b/drivers/staging/rtl8723cs/include/rtl8188e_recv.h
-new file mode 100644
-index 000000000000..31058c1b11dc
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188e_recv.h
-@@ -0,0 +1,156 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188E_RECV_H__
-+#define __RTL8188E_RECV_H__
-+
-+#define RECV_BLK_SZ 512
-+#define RECV_BLK_CNT 16
-+#define RECV_BLK_TH RECV_BLK_CNT
-+
-+#if defined(CONFIG_USB_HCI)
-+	#ifndef MAX_RECVBUF_SZ
-+		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
-+			/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
-+			/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
-+			/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
-+			#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
-+			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
-+		#else
-+			#define MAX_RECVBUF_SZ (4000) /* about 4K */
-+		#endif
-+	#endif /* !MAX_RECVBUF_SZ */
-+
-+#elif defined(CONFIG_PCI_HCI)
-+	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
-+	/*	#define MAX_RECVBUF_SZ (9100) */
-+	/* #else */
-+	#define MAX_RECVBUF_SZ (4000) /* about 4K
-+	* #endif */
-+
-+
-+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+
-+	#define MAX_RECVBUF_SZ (10240)
-+
-+#endif
-+
-+/* Rx smooth factor */
-+#define	Rx_Smooth_Factor (20)
-+
-+#define TX_RPT1_PKT_LEN 8
-+
-+typedef struct rxreport_8188e {
-+	/* Offset 0 */
-+	u32 pktlen:14;
-+	u32 crc32:1;
-+	u32 icverr:1;
-+	u32 drvinfosize:4;
-+	u32 security:3;
-+	u32 qos:1;
-+	u32 shift:2;
-+	u32 physt:1;
-+	u32 swdec:1;
-+	u32 ls:1;
-+	u32 fs:1;
-+	u32 eor:1;
-+	u32 own:1;
-+
-+	/* Offset 4 */
-+	u32 macid:5;
-+	u32 tid:4;
-+	u32 hwrsvd:4;
-+	u32 amsdu:1;
-+	u32 paggr:1;
-+	u32 faggr:1;
-+	u32 a1fit:4;
-+	u32 a2fit:4;
-+	u32 pam:1;
-+	u32 pwr:1;
-+	u32 md:1;
-+	u32 mf:1;
-+	u32 type:2;
-+	u32 mc:1;
-+	u32 bc:1;
-+
-+	/* Offset 8 */
-+	u32 seq:12;
-+	u32 frag:4;
-+	u32 nextpktlen:14;
-+	u32 nextind:1;
-+	u32 rsvd0831:1;
-+
-+	/* Offset 12 */
-+	u32 rxmcs:6;
-+	u32 rxht:1;
-+	u32 gf:1;
-+	u32 splcp:1;
-+	u32 bw:1;
-+	u32 htc:1;
-+	u32 eosp:1;
-+	u32 bssidfit:2;
-+	u32 rpt_sel:2;
-+	u32 rsvd1216:13;
-+	u32 pattern_match:1;
-+	u32 unicastwake:1;
-+	u32 magicwake:1;
-+
-+	/* Offset 16 */
-+	/*
-+	u32 pattern0match:1;
-+	u32 pattern1match:1;
-+	u32 pattern2match:1;
-+	u32 pattern3match:1;
-+	u32 pattern4match:1;
-+	u32 pattern5match:1;
-+	u32 pattern6match:1;
-+	u32 pattern7match:1;
-+	u32 pattern8match:1;
-+	u32 pattern9match:1;
-+	u32 patternamatch:1;
-+	u32 patternbmatch:1;
-+	u32 patterncmatch:1;
-+	u32 rsvd1613:19;
-+	*/
-+	u32 rsvd16;
-+
-+	/* Offset 20 */
-+	u32 tsfl;
-+
-+	/* Offset 24 */
-+	u32 bassn:12;
-+	u32 bavld:1;
-+	u32 rsvd2413:19;
-+} RXREPORT, *PRXREPORT;
-+
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	s32 rtl8188es_init_recv_priv(PADAPTER padapter);
-+	void rtl8188es_free_recv_priv(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	void rtl8188eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
-+	s32 rtl8188eu_init_recv_priv(PADAPTER padapter);
-+	void rtl8188eu_free_recv_priv(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8188ee_init_recv_priv(PADAPTER padapter);
-+	void rtl8188ee_free_recv_priv(PADAPTER padapter);
-+#endif
-+
-+void rtl8188e_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *prxstat);
-+
-+#endif /* __RTL8188E_RECV_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188e_rf.h b/drivers/staging/rtl8723cs/include/rtl8188e_rf.h
-new file mode 100644
-index 000000000000..8dc413e1dddf
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188e_rf.h
-@@ -0,0 +1,27 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188E_RF_H__
-+#define __RTL8188E_RF_H__
-+
-+
-+
-+int	PHY_RF6052_Config8188E(PADAPTER		Adapter);
-+void		rtl8188e_RF_ChangeTxPath(PADAPTER	Adapter,
-+			u16		DataRate);
-+void		rtl8188e_PHY_RF6052SetBandwidth(
-+		PADAPTER				Adapter,
-+		enum channel_width		Bandwidth);
-+
-+#endif/* __RTL8188E_RF_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188e_spec.h b/drivers/staging/rtl8723cs/include/rtl8188e_spec.h
-new file mode 100644
-index 000000000000..802659a5fd07
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188e_spec.h
-@@ -0,0 +1,159 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188E_SPEC_H__
-+#define __RTL8188E_SPEC_H__
-+
-+
-+/* ************************************************************
-+ * 8188E Regsiter offset definition
-+ * ************************************************************ */
-+
-+
-+/* ************************************************************
-+ *
-+ * ************************************************************ */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0000h ~ 0x00FFh	System Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_BB_PAD_CTRL				0x0064
-+#define REG_HMEBOX_E0					0x0088
-+#define REG_HMEBOX_E1					0x008A
-+#define REG_HMEBOX_E2					0x008C
-+#define REG_HMEBOX_E3					0x008E
-+#define REG_HMEBOX_EXT_0				0x01F0
-+#define REG_HMEBOX_EXT_1				0x01F4
-+#define REG_HMEBOX_EXT_2				0x01F8
-+#define REG_HMEBOX_EXT_3				0x01FC
-+#define REG_HIMR_88E					0x00B0 /* RTL8188E */
-+#define REG_HISR_88E					0x00B4 /* RTL8188E */
-+#define REG_HIMRE_88E					0x00B8 /* RTL8188E */
-+#define REG_HISRE_88E					0x00BC /* RTL8188E */
-+
-+#define	REG_DBI_WDATA_8188E				0x0348	/* DBI Write data */
-+#define	REG_DBI_RDATA_8188E				0x034C	/* DBI Read data */
-+#define	REG_DBI_ADDR_8188E				0x0350	/* DBI Address */
-+#define	REG_DBI_FLAG_8188E				0x0352	/* DBI Read/Write Flag */
-+#define	REG_MDIO_WDATA_8188E				0x0354	/* MDIO for Write PCIE PHY */
-+#define	REG_MDIO_RDATA_8188E				0x0356	/* MDIO for Reads PCIE PHY */
-+#define	REG_MDIO_CTL_8188E				0x0358	/* MDIO for Control */
-+
-+#define REG_MACID_NO_LINK_0			0x0484
-+#define REG_MACID_NO_LINK_1			0x0488
-+#define REG_MACID_PAUSE_0			0x048c
-+#define REG_MACID_PAUSE_1			0x0490
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_PKTBUF_DBG_ADDR			(REG_PKTBUF_DBG_CTRL)
-+#define REG_RXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+2)
-+#define REG_TXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+3)
-+#define REG_WOWLAN_WAKE_REASON		REG_MCUTST_WOWLAN
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0300h ~ 0x03FFh	PCIe
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_PCIE_HRPWM_8188E		0x0361	/* PCIe RPWM */
-+#define REG_PCIE_HCPWM_8188E		0x0363	/* PCIe CPWM */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0400h ~ 0x047Fh	Protocol Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#ifdef CONFIG_WOWLAN
-+	#define REG_TXPKTBUF_IV_LOW             0x01a4
-+	#define REG_TXPKTBUF_IV_HIGH            0x01a8
-+#endif
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0500h ~ 0x05FFh	EDCA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0600h ~ 0x07FFh	WMAC Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#ifdef CONFIG_RF_POWER_TRIM
-+	#define EEPROM_RF_GAIN_OFFSET			0xC1
-+	#define EEPROM_RF_GAIN_VAL				0xF6
-+	#define EEPROM_THERMAL_OFFSET			0xF5
-+#endif /*CONFIG_RF_POWER_TRIM*/
-+/* ----------------------------------------------------------------------------
-+ * 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits)
-+ * ----------------------------------------------------------------------------
-+ * IOL config for REG_FDHM0(Reg0x88) */
-+#define CMD_INIT_LLT					BIT0
-+#define CMD_READ_EFUSE_MAP		BIT1
-+#define CMD_EFUSE_PATCH			BIT2
-+#define CMD_IOCONFIG				BIT3
-+#define CMD_INIT_LLT_ERR			BIT4
-+#define CMD_READ_EFUSE_MAP_ERR	BIT5
-+#define CMD_EFUSE_PATCH_ERR		BIT6
-+#define CMD_IOCONFIG_ERR			BIT7
-+
-+/* -----------------------------------------------------
-+ *
-+ *	Redifine register definition for compatibility
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* TODO: use these definition when using REG_xxx naming rule.
-+ * NOTE: DO NOT Remove these definition. Use later. */
-+#define ISR_88E				REG_HISR_88E
-+
-+#ifdef CONFIG_PCI_HCI
-+	/* #define IMR_RX_MASK		(IMR_ROK_88E|IMR_RDU_88E|IMR_RXFOVW_88E) */
-+	#define IMR_TX_MASK			(IMR_VODOK_88E | IMR_VIDOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E | IMR_MGNTDOK_88E | IMR_HIGHDOK_88E | IMR_BCNDERR0_88E)
-+
-+	#ifdef CONFIG_CONCURRENT_MODE
-+		#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E | IMR_BCNDMAINT_E_88E)
-+	#else
-+		#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E)
-+	#endif
-+
-+	#define RT_AC_INT_MASKS	(IMR_VIDOK_88E | IMR_VODOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E)
-+#endif
-+
-+/* ----------------------------------------------------------------------------
-+ * 8192C EEPROM/EFUSE share register definition.
-+ * ---------------------------------------------------------------------------- */
-+
-+#define EFUSE_ACCESS_ON			0x69	/* For RTL8723 only. */
-+#define EFUSE_ACCESS_OFF			0x00	/* For RTL8723 only. */
-+
-+#endif /* __RTL8188E_SPEC_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188e_sreset.h b/drivers/staging/rtl8723cs/include/rtl8188e_sreset.h
-new file mode 100644
-index 000000000000..f4ec2d88c327
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188e_sreset.h
-@@ -0,0 +1,24 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8188E_SRESET_H_
-+#define _RTL8188E_SRESET_H_
-+
-+#include <rtw_sreset.h>
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	extern void rtl8188e_sreset_xmit_status_check(_adapter *padapter);
-+	extern void rtl8188e_sreset_linked_status_check(_adapter *padapter);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188e_xmit.h b/drivers/staging/rtl8723cs/include/rtl8188e_xmit.h
-new file mode 100644
-index 000000000000..bf8bf36047bc
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188e_xmit.h
-@@ -0,0 +1,302 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188E_XMIT_H__
-+#define __RTL8188E_XMIT_H__
-+
-+
-+
-+
-+/* For 88e early mode */
-+#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
-+#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
-+#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
-+#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
-+#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
-+#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
-+#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
-+
-+/*
-+ * defined for TX DESC Operation
-+ *   */
-+
-+#define MAX_TID (15)
-+
-+/* OFFSET 0 */
-+#define OFFSET_SZ	0
-+#define OFFSET_SHT	16
-+#define BMC		BIT(24)
-+#define LSG		BIT(26)
-+#define FSG		BIT(27)
-+#define OWN		BIT(31)
-+
-+
-+/* OFFSET 4 */
-+#define PKT_OFFSET_SZ		0
-+#define QSEL_SHT			8
-+#define RATE_ID_SHT			16
-+#define NAVUSEHDR			BIT(20)
-+#define SEC_TYPE_SHT		22
-+#define PKT_OFFSET_SHT		26
-+
-+/* OFFSET 8 */
-+#define AGG_EN				BIT(12)
-+#define AGG_BK					BIT(16)
-+#define AMPDU_DENSITY_SHT	20
-+#define ANTSEL_A			BIT(24)
-+#define ANTSEL_B			BIT(25)
-+#define TX_ANT_CCK_SHT		26
-+#define TX_ANTL_SHT			28
-+#define TX_ANT_HT_SHT		30
-+
-+/* OFFSET 12 */
-+#define SEQ_SHT				16
-+#define EN_HWSEQ			BIT(31)
-+
-+/* OFFSET 16 */
-+#define	QOS                          BIT(6)
-+#define	HW_SSN				BIT(7)
-+#define	USERATE			BIT(8)
-+#define	DISDATAFB			BIT(10)
-+#define   CTS_2_SELF			BIT(11)
-+#define	RTS_EN				BIT(12)
-+#define	HW_RTS_EN			BIT(13)
-+#define	DATA_SHORT			BIT(24)
-+#define	PWR_STATUS_SHT	15
-+#define	DATA_SC_SHT		20
-+#define	DATA_BW			BIT(25)
-+
-+/* OFFSET 20 */
-+#define	RTY_LMT_EN			BIT(17)
-+
-+
-+/* OFFSET 20 */
-+#define SGI					BIT(6)
-+#define USB_TXAGG_NUM_SHT	24
-+
-+typedef struct txdesc_88e {
-+	/* Offset 0 */
-+	u32 pktlen:16;
-+	u32 offset:8;
-+	u32 bmc:1;
-+	u32 htc:1;
-+	u32 ls:1;
-+	u32 fs:1;
-+	u32 linip:1;
-+	u32 noacm:1;
-+	u32 gf:1;
-+	u32 own:1;
-+
-+	/* Offset 4 */
-+	u32 macid:6;
-+	u32 rsvd0406:2;
-+	u32 qsel:5;
-+	u32 rd_nav_ext:1;
-+	u32 lsig_txop_en:1;
-+	u32 pifs:1;
-+	u32 rate_id:4;
-+	u32 navusehdr:1;
-+	u32 en_desc_id:1;
-+	u32 sectype:2;
-+	u32 rsvd0424:2;
-+	u32 pkt_offset:5;	/* unit: 8 bytes */
-+	u32 rsvd0431:1;
-+
-+	/* Offset 8 */
-+	u32 rts_rc:6;
-+	u32 data_rc:6;
-+	u32 agg_en:1;
-+	u32 rd_en:1;
-+	u32 bar_rty_th:2;
-+	u32 bk:1;
-+	u32 morefrag:1;
-+	u32 raw:1;
-+	u32 ccx:1;
-+	u32 ampdu_density:3;
-+	u32 bt_null:1;
-+	u32 ant_sel_a:1;
-+	u32 ant_sel_b:1;
-+	u32 tx_ant_cck:2;
-+	u32 tx_antl:2;
-+	u32 tx_ant_ht:2;
-+
-+	/* Offset 12 */
-+	u32 nextheadpage:8;
-+	u32 tailpage:8;
-+	u32 seq:12;
-+	u32 cpu_handle:1;
-+	u32 tag1:1;
-+	u32 trigger_int:1;
-+	u32 hwseq_en:1;
-+
-+	/* Offset 16 */
-+	u32 rtsrate:5;
-+	u32 ap_dcfe:1;
-+	u32 hwseq_sel:2;
-+	u32 userate:1;
-+	u32 disrtsfb:1;
-+	u32 disdatafb:1;
-+	u32 cts2self:1;
-+	u32 rtsen:1;
-+	u32 hw_rts_en:1;
-+	u32 port_id:1;
-+	u32 pwr_status:3;
-+	u32 wait_dcts:1;
-+	u32 cts2ap_en:1;
-+	u32 data_sc:2;
-+	u32 data_stbc:2;
-+	u32 data_short:1;
-+	u32 data_bw:1;
-+	u32 rts_short:1;
-+	u32 rts_bw:1;
-+	u32 rts_sc:2;
-+	u32 vcs_stbc:2;
-+
-+	/* Offset 20 */
-+	u32 datarate:6;
-+	u32 sgi:1;
-+	u32 try_rate:1;
-+	u32 data_ratefb_lmt:5;
-+	u32 rts_ratefb_lmt:4;
-+	u32 rty_lmt_en:1;
-+	u32 data_rt_lmt:6;
-+	u32 usb_txagg_num:8;
-+
-+	/* Offset 24 */
-+	u32 txagg_a:5;
-+	u32 txagg_b:5;
-+	u32 use_max_len:1;
-+	u32 max_agg_num:5;
-+	u32 mcsg1_max_len:4;
-+	u32 mcsg2_max_len:4;
-+	u32 mcsg3_max_len:4;
-+	u32 mcs7_sgi_max_len:4;
-+
-+	/* Offset 28 */
-+	u32 checksum:16;	/* TxBuffSize(PCIe)/CheckSum(USB) */
-+	u32 sw0:8; /* offset 30 */
-+	u32 sw1:4;
-+	u32 mcs15_sgi_max_len:4;
-+} TXDESC_8188E, *PTXDESC_8188E;
-+
-+#define txdesc_set_ccx_sw_88e(txdesc, value) \
-+	do { \
-+		((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \
-+		((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \
-+	} while (0)
-+
-+struct txrpt_ccx_88e {
-+	/* offset 0 */
-+	u8 tag1:1;
-+	u8 pkt_num:3;
-+	u8 txdma_underflow:1;
-+	u8 int_bt:1;
-+	u8 int_tri:1;
-+	u8 int_ccx:1;
-+
-+	/* offset 1 */
-+	u8 mac_id:6;
-+	u8 pkt_ok:1;
-+	u8 bmc:1;
-+
-+	/* offset 2 */
-+	u8 retry_cnt:6;
-+	u8 lifetime_over:1;
-+	u8 retry_over:1;
-+
-+	/* offset 3 */
-+	u8 ccx_qtime0;
-+	u8 ccx_qtime1;
-+
-+	/* offset 5 */
-+	u8 final_data_rate;
-+
-+	/* offset 6 */
-+	u8 sw1:4;
-+	u8 qsel:4;
-+
-+	/* offset 7 */
-+	u8 sw0;
-+};
-+
-+#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
-+#define txrpt_ccx_qtime_88e(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
-+
-+#define SET_TX_DESC_SEC_TYPE_8188E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
-+
-+void rtl8188e_fill_fake_txdesc(PADAPTER	padapter, u8 *pDesc, u32 BufferLen,
-+			       u8 IsPsPoll, u8	IsBTQosNull, u8 bDataFrame);
-+void rtl8188e_cal_txdesc_chksum(struct tx_desc	*ptxdesc);
-+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	s32 rtl8188es_init_xmit_priv(PADAPTER padapter);
-+	void rtl8188es_free_xmit_priv(PADAPTER padapter);
-+	s32 rtl8188es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8188es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8188es_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	rtl8188es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	thread_return rtl8188es_xmit_thread(thread_context context);
-+	s32 rtl8188es_xmit_buf_handler(PADAPTER padapter);
-+
-+	#ifdef CONFIG_SDIO_TX_TASKLET
-+		void rtl8188es_xmit_tasklet(void *priv);
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	s32 rtl8188eu_init_xmit_priv(PADAPTER padapter);
-+	void rtl8188eu_free_xmit_priv(PADAPTER padapter);
-+	s32 rtl8188eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8188eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8188eu_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	rtl8188eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8188eu_xmit_buf_handler(PADAPTER padapter);
-+	void rtl8188eu_xmit_tasklet(void *priv);
-+	s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8188ee_init_xmit_priv(PADAPTER padapter);
-+	void rtl8188ee_free_xmit_priv(PADAPTER padapter);
-+	void	rtl8188ee_xmitframe_resume(_adapter *padapter);
-+	s32 rtl8188ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8188ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8188ee_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	rtl8188ee_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	void rtl8188ee_xmit_tasklet(void *priv);
-+#endif
-+
-+
-+
-+#ifdef CONFIG_TX_EARLY_MODE
-+	void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+#endif
-+
-+#ifdef CONFIG_XMIT_ACK
-+	void dump_txrpt_ccx_88e(void *buf);
-+	void handle_txrpt_ccx_88e(_adapter *adapter, u8 *buf);
-+#else
-+	#define dump_txrpt_ccx_88e(buf) do {} while (0)
-+	#define handle_txrpt_ccx_88e(adapter, buf) do {} while (0)
-+#endif /* CONFIG_XMIT_ACK */
-+
-+void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
-+#endif /* __RTL8188E_XMIT_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188f_cmd.h b/drivers/staging/rtl8723cs/include/rtl8188f_cmd.h
-new file mode 100644
-index 000000000000..6f33708e93cc
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188f_cmd.h
-@@ -0,0 +1,200 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188F_CMD_H__
-+#define __RTL8188F_CMD_H__
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+enum h2c_cmd_8188F {
-+	/* Common Class: 000 */
-+	H2C_8188F_RSVD_PAGE = 0x00,
-+	H2C_8188F_MEDIA_STATUS_RPT = 0x01,
-+	H2C_8188F_SCAN_ENABLE = 0x02,
-+	H2C_8188F_KEEP_ALIVE = 0x03,
-+	H2C_8188F_DISCON_DECISION = 0x04,
-+	H2C_8188F_PSD_OFFLOAD = 0x05,
-+	H2C_8188F_AP_OFFLOAD = 0x08,
-+	H2C_8188F_BCN_RSVDPAGE = 0x09,
-+	H2C_8188F_PROBERSP_RSVDPAGE = 0x0A,
-+	H2C_8188F_FCS_RSVDPAGE = 0x10,
-+	H2C_8188F_FCS_INFO = 0x11,
-+	H2C_8188F_AP_WOW_GPIO_CTRL = 0x13,
-+
-+	/* PoweSave Class: 001 */
-+	H2C_8188F_SET_PWR_MODE = 0x20,
-+	H2C_8188F_PS_TUNING_PARA = 0x21,
-+	H2C_8188F_PS_TUNING_PARA2 = 0x22,
-+	H2C_8188F_P2P_LPS_PARAM = 0x23,
-+	H2C_8188F_P2P_PS_OFFLOAD = 0x24,
-+	H2C_8188F_PS_SCAN_ENABLE = 0x25,
-+	H2C_8188F_SAP_PS_ = 0x26,
-+	H2C_8188F_INACTIVE_PS_ = 0x27, /* Inactive_PS */
-+	H2C_8188F_FWLPS_IN_IPS_ = 0x28,
-+
-+	/* Dynamic Mechanism Class: 010 */
-+	H2C_8188F_MACID_CFG = 0x40,
-+	H2C_8188F_TXBF = 0x41,
-+	H2C_8188F_RSSI_SETTING = 0x42,
-+	H2C_8188F_AP_REQ_TXRPT = 0x43,
-+	H2C_8188F_INIT_RATE_COLLECT = 0x44,
-+	H2C_8188F_RA_PARA_ADJUST = 0x46,
-+
-+	/* BT Class: 011 */
-+	H2C_8188F_B_TYPE_TDMA = 0x60,
-+	H2C_8188F_BT_INFO = 0x61,
-+	H2C_8188F_FORCE_BT_TXPWR = 0x62,
-+	H2C_8188F_BT_IGNORE_WLANACT = 0x63,
-+	H2C_8188F_DAC_SWING_VALUE = 0x64,
-+	H2C_8188F_ANT_SEL_RSV = 0x65,
-+	H2C_8188F_WL_OPMODE = 0x66,
-+	H2C_8188F_BT_MP_OPER = 0x67,
-+	H2C_8188F_BT_CONTROL = 0x68,
-+	H2C_8188F_BT_WIFI_CTRL = 0x69,
-+	H2C_8188F_BT_FW_PATCH = 0x6A,
-+	H2C_8188F_BT_WLAN_CALIBRATION = 0x6D,
-+
-+	/* WOWLAN Class: 100 */
-+	H2C_8188F_WOWLAN = 0x80,
-+	H2C_8188F_REMOTE_WAKE_CTRL = 0x81,
-+	H2C_8188F_AOAC_GLOBAL_INFO = 0x82,
-+	H2C_8188F_AOAC_RSVD_PAGE = 0x83,
-+	H2C_8188F_AOAC_RSVD_PAGE2 = 0x84,
-+	H2C_8188F_D0_SCAN_OFFLOAD_CTRL = 0x85,
-+	H2C_8188F_D0_SCAN_OFFLOAD_INFO = 0x86,
-+	H2C_8188F_CHNL_SWITCH_OFFLOAD = 0x87,
-+	H2C_8188F_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
-+	H2C_8188F_P2P_OFFLOAD = 0x8B,
-+
-+	H2C_8188F_RESET_TSF = 0xC0,
-+	H2C_8188F_MAXID,
-+};
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
-+ * ---------------------------------------------------------------------------------------------------------
-+ * _RSVDPAGE_LOC_CMD_0x00 */
-+#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+/* _KEEP_ALIVE_CMD_0x03 */
-+#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_8188F_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_8188F_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+
-+/* _DISCONNECT_DECISION_CMD_0x04 */
-+#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_8188F_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
-+
-+/* _PWR_MOD_CMD_0x20 */
-+#define SET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
-+#define SET_8188F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
-+#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
-+#define SET_8188F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+#define GET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
-+
-+/* _PS_TUNE_PARAM_CMD_0x21 */
-+#define SET_8188F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
-+#define SET_8188F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
-+#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+
-+/* _MACID_CFG_CMD_0x40 */
-+#define SET_8188F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
-+#define SET_8188F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
-+#define SET_8188F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
-+#define SET_8188F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
-+#define SET_8188F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
-+#define SET_8188F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
-+#define SET_8188F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
-+#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
-+
-+/* _RSSI_SETTING_CMD_0x42 */
-+#define SET_8188F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
-+#define SET_8188F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+
-+/* _AP_REQ_TXRPT_CMD_0x43 */
-+#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+
-+/* _FORCE_BT_TXPWR_CMD_0x62 */
-+#define SET_8188F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+
-+/* _FORCE_BT_MP_OPER_CMD_0x67 */
-+#define SET_8188F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
-+#define SET_8188F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
-+#define SET_8188F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
-+
-+/* _BT_FW_PATCH_0x6A */
-+#define SET_8188F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
-+#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
-+
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * -------------------------------------------    Structure    --------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    Function Statement     --------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+/* host message to firmware cmd */
-+void rtl8188f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
-+void rtl8188f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
-+void rtl8188f_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
-+/* s32 rtl8188f_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
-+void rtl8188f_set_FwPsTuneParam_cmd(PADAPTER padapter);
-+void rtl8188f_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
-+void rtl8188f_download_rsvd_page(PADAPTER padapter, u8 mstatus);
-+#ifdef CONFIG_BT_COEXIST
-+	void rtl8188f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
-+#endif /* CONFIG_BT_COEXIST */
-+#ifdef CONFIG_P2P
-+void rtl8188f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
-+#endif /* CONFIG_P2P */
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+void rtl8188f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
-+#endif
-+
-+void rtl8188f_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
-+
-+s32 FillH2CCmd8188F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
-+u8 GetTxBufferRsvdPageNum8188F(_adapter *padapter, bool wowlan);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188f_dm.h b/drivers/staging/rtl8723cs/include/rtl8188f_dm.h
-new file mode 100644
-index 000000000000..342ade9a515c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188f_dm.h
-@@ -0,0 +1,39 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188F_DM_H__
-+#define __RTL8188F_DM_H__
-+/* ************************************************************
-+ * Description:
-+ *
-+ * This file is for 8188F dynamic mechanism only
-+ *
-+ *
-+ * ************************************************************ */
-+
-+/* ************************************************************
-+ * structure and define
-+ * ************************************************************ */
-+
-+/* ************************************************************
-+ * function prototype
-+ * ************************************************************ */
-+
-+void rtl8188f_init_dm_priv(PADAPTER padapter);
-+void rtl8188f_deinit_dm_priv(PADAPTER padapter);
-+
-+void rtl8188f_InitHalDm(PADAPTER padapter);
-+void rtl8188f_HalDmWatchDog(PADAPTER padapter);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188f_hal.h b/drivers/staging/rtl8723cs/include/rtl8188f_hal.h
-new file mode 100644
-index 000000000000..5db99a41e50b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188f_hal.h
-@@ -0,0 +1,260 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188F_HAL_H__
-+#define __RTL8188F_HAL_H__
-+
-+#include "hal_data.h"
-+
-+#include "rtl8188f_spec.h"
-+#include "rtl8188f_rf.h"
-+#include "rtl8188f_dm.h"
-+#include "rtl8188f_recv.h"
-+#include "rtl8188f_xmit.h"
-+#include "rtl8188f_cmd.h"
-+#include "rtl8188f_led.h"
-+#include "Hal8188FPwrSeq.h"
-+#include "Hal8188FPhyReg.h"
-+#include "Hal8188FPhyCfg.h"
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+#include "rtl8188f_sreset.h"
-+#endif
-+
-+#define FW_8188F_SIZE			0x8000
-+#define FW_8188F_START_ADDRESS	0x1000
-+#define FW_8188F_END_ADDRESS		0x1FFF /* 0x5FFF */
-+
-+#define IS_FW_HEADER_EXIST_8188F(_pFwHdr)	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x88F0)
-+
-+typedef struct _RT_FIRMWARE {
-+	FIRMWARE_SOURCE	eFWSource;
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+	u8			*szFwBuffer;
-+#else
-+	u8			szFwBuffer[FW_8188F_SIZE];
-+#endif
-+	u32			ulFwLength;
-+} RT_FIRMWARE_8188F, *PRT_FIRMWARE_8188F;
-+
-+/*
-+ * This structure must be cared byte-ordering
-+ *
-+ * Added by tynli. 2009.12.04. */
-+typedef struct _RT_8188F_FIRMWARE_HDR {
-+	/* 8-byte alinment required */
-+
-+	/* --- LONG WORD 0 ---- */
-+	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
-+	u8		Category;	/* AP/NIC and USB/PCI */
-+	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
-+	u16		Version;		/* FW Version */
-+	u16		Subversion;	/* FW Subversion, default 0x00 */
-+
-+	/* --- LONG WORD 1 ---- */
-+	u8		Month;	/* Release time Month field */
-+	u8		Date;	/* Release time Date field */
-+	u8		Hour;	/* Release time Hour field */
-+	u8		Minute;	/* Release time Minute field */
-+	u16		RamCodeSize;	/* The size of RAM code */
-+	u16		Rsvd2;
-+
-+	/* --- LONG WORD 2 ---- */
-+	u32		SvnIdx;	/* The SVN entry index */
-+	u32		Rsvd3;
-+
-+	/* --- LONG WORD 3 ---- */
-+	u32		Rsvd4;
-+	u32		Rsvd5;
-+} RT_8188F_FIRMWARE_HDR, *PRT_8188F_FIRMWARE_HDR;
-+
-+#define DRIVER_EARLY_INT_TIME_8188F		0x05
-+#define BCN_DMA_ATIME_INT_TIME_8188F		0x02
-+
-+/* for 8188F
-+ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
-+#define PAGE_SIZE_TX_8188F			128
-+#define PAGE_SIZE_RX_8188F			8
-+
-+#define RX_DMA_SIZE_8188F			0x4000	/* 16K */
-+#ifdef CONFIG_FW_C2H_DEBUG
-+	#define RX_DMA_RESERVED_SIZE_8188F	0x100	/* 256B, reserved for c2h debug message */
-+#else
-+	#define RX_DMA_RESERVED_SIZE_8188F	0x80	/* 128B, reserved for tx report */
-+#endif
-+
-+#ifdef CONFIG_WOWLAN
-+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
-+#else
-+	#define RESV_FMWF	0
-+#endif
-+
-+#define RX_DMA_BOUNDARY_8188F		(RX_DMA_SIZE_8188F - RX_DMA_RESERVED_SIZE_8188F - 1)
-+
-+/* Note: We will divide number of page equally for each queue other than public queue! */
-+
-+/* For General Reserved Page Number(Beacon Queue is reserved page)
-+ * BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_8188F,
-+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1, CTS-2-SELF / LTE QoS Null */
-+
-+#define BCNQ_PAGE_NUM_8188F		(MAX_BEACON_LEN / PAGE_SIZE_TX_8188F + 6) /*0x08*/
-+
-+/* For WoWLan , more reserved page
-+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt:1 ,PNO: 6
-+ * NS offload:2 NDP info: 1
-+ */
-+#ifdef CONFIG_WOWLAN
-+	#define WOWLAN_PAGE_NUM_8188F	0x0b
-+#else
-+	#define WOWLAN_PAGE_NUM_8188F	0x00
-+#endif
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+#undef WOWLAN_PAGE_NUM_8188F
-+#define WOWLAN_PAGE_NUM_8188F	0x15
-+#endif
-+
-+#ifdef CONFIG_AP_WOWLAN
-+#define AP_WOWLAN_PAGE_NUM_8188F	0x02
-+#endif
-+
-+#define TX_TOTAL_PAGE_NUMBER_8188F	(0xFF - BCNQ_PAGE_NUM_8188F - WOWLAN_PAGE_NUM_8188F)
-+#define TX_PAGE_BOUNDARY_8188F		(TX_TOTAL_PAGE_NUMBER_8188F + 1)
-+
-+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F	TX_TOTAL_PAGE_NUMBER_8188F
-+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8188F		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F + 1)
-+
-+/* For Normal Chip Setting
-+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8188F */
-+#define NORMAL_PAGE_NUM_HPQ_8188F		0x0C
-+#define NORMAL_PAGE_NUM_LPQ_8188F		0x02
-+#define NORMAL_PAGE_NUM_NPQ_8188F		0x02
-+
-+/* Note: For Normal Chip Setting, modify later */
-+#define WMM_NORMAL_PAGE_NUM_HPQ_8188F		0x30
-+#define WMM_NORMAL_PAGE_NUM_LPQ_8188F		0x20
-+#define WMM_NORMAL_PAGE_NUM_NPQ_8188F		0x20
-+
-+
-+#include "HalVerDef.h"
-+#include "hal_com.h"
-+
-+#define EFUSE_OOB_PROTECT_BYTES (34 + 1)
-+
-+#define HAL_EFUSE_MEMORY
-+
-+#define HWSET_MAX_SIZE_8188F			512
-+#define EFUSE_REAL_CONTENT_LEN_8188F	256
-+#define EFUSE_MAP_LEN_8188F				512
-+#define EFUSE_MAX_SECTION_8188F			(EFUSE_MAP_LEN_8188F / 8)
-+
-+#define EFUSE_IC_ID_OFFSET			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
-+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8188F)
-+
-+#define EFUSE_ACCESS_ON			0x69	/* For RTL8188 only. */
-+#define EFUSE_ACCESS_OFF			0x00	/* For RTL8188 only. */
-+
-+/* ********************************************************
-+ *			EFUSE for BT definition
-+ * ******************************************************** */
-+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
-+#define EFUSE_BT_REAL_CONTENT_LEN		1536	/* 512*3 */
-+#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
-+#define EFUSE_BT_MAX_SECTION			128		/* 1024/8 */
-+
-+#define EFUSE_PROTECT_BYTES_BANK		16
-+
-+#define INCLUDE_MULTI_FUNC_BT(_Adapter)		(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
-+#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
-+
-+/* rtl8188a_hal_init.c */
-+s32 rtl8188f_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
-+void rtl8188f_FirmwareSelfReset(PADAPTER padapter);
-+void rtl8188f_InitializeFirmwareVars(PADAPTER padapter);
-+
-+void rtl8188f_InitAntenna_Selection(PADAPTER padapter);
-+void rtl8188f_DeinitAntenna_Selection(PADAPTER padapter);
-+void rtl8188f_CheckAntenna_Selection(PADAPTER padapter);
-+void rtl8188f_init_default_value(PADAPTER padapter);
-+
-+s32 rtl8188f_InitLLTTable(PADAPTER padapter);
-+
-+s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
-+s32 CardDisableWithoutHWSM(PADAPTER padapter);
-+
-+/* EFuse */
-+u8 GetEEPROMSize8188F(PADAPTER padapter);
-+void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
-+void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
-+void Hal_EfuseParseTxPowerInfo_8188F(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
-+/* void Hal_EfuseParseBTCoexistInfo_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); */
-+void Hal_EfuseParseEEPROMVer_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseChnlPlan_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseCustomerID_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParsePowerSavingMode_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseAntennaDiversity_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseXtal_8188F(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
-+void Hal_EfuseParseThermalMeter_8188F(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
-+void Hal_EfuseParseKFreeData_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+
-+#if 0 /* Do not need for rtl8188f */
-+void Hal_EfuseParseVoltage_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
-+#endif
-+
-+void rtl8188f_set_pll_ref_clk_sel(_adapter *adapter, u8 sel);
-+
-+void rtl8188f_set_hal_ops(struct hal_ops *pHalFunc);
-+void init_hal_spec_8188f(_adapter *adapter);
-+u8 SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val);
-+void GetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val);
-+u8 SetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+u8 GetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+
-+/* register */
-+void rtl8188f_InitBeaconParameters(PADAPTER padapter);
-+void rtl8188f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
-+void	_InitBurstPktLen_8188FS(PADAPTER Adapter);
-+void _8051Reset8188(PADAPTER padapter);
-+#ifdef CONFIG_WOWLAN
-+void Hal_DetectWoWMode(PADAPTER pAdapter);
-+#endif /* CONFIG_WOWLAN */
-+
-+void rtl8188f_start_thread(_adapter *padapter);
-+void rtl8188f_stop_thread(_adapter *padapter);
-+
-+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
-+	void rtl8188fs_init_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8188fs_free_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8188fs_cancle_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8188fs_hal_check_bt_hang(_adapter *adapter);
-+#endif
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
-+#endif
-+
-+#ifdef CONFIG_MP_INCLUDED
-+int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
-+#endif
-+
-+void CCX_FwC2HTxRpt_8188f(PADAPTER padapter, u8 *pdata, u8 len);
-+
-+u8 MRateToHwRate8188F(u8  rate);
-+u8 HwRateToMRate8188F(u8	 rate);
-+
-+#ifdef CONFIG_PCI_HCI
-+BOOLEAN	InterruptRecognized8188FE(PADAPTER Adapter);
-+void	UpdateInterruptMask8188FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188f_led.h b/drivers/staging/rtl8723cs/include/rtl8188f_led.h
-new file mode 100644
-index 000000000000..ef5d1a7761a8
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188f_led.h
-@@ -0,0 +1,45 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188F_LED_H__
-+#define __RTL8188F_LED_H__
-+#ifdef CONFIG_RTW_SW_LED
-+
-+#include <drv_conf.h>
-+#include <osdep_service.h>
-+#include <drv_types.h>
-+
-+
-+/* ********************************************************************************
-+ * Interface to manipulate LED objects.
-+ * ******************************************************************************** */
-+#ifdef CONFIG_USB_HCI
-+void rtl8188fu_InitSwLeds(PADAPTER padapter);
-+void rtl8188fu_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_SDIO_HCI
-+void rtl8188fs_InitSwLeds(PADAPTER padapter);
-+void rtl8188fs_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_GSPI_HCI
-+void rtl8188fs_InitSwLeds(PADAPTER padapter);
-+void rtl8188fs_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+void rtl8188fe_InitSwLeds(PADAPTER padapter);
-+void rtl8188fe_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+
-+#endif
-+#endif/*CONFIG_RTW_SW_LED*/
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188f_recv.h b/drivers/staging/rtl8723cs/include/rtl8188f_recv.h
-new file mode 100644
-index 000000000000..44b51fdbb9ca
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188f_recv.h
-@@ -0,0 +1,64 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188F_RECV_H__
-+#define __RTL8188F_RECV_H__
-+
-+#if defined(CONFIG_USB_HCI)
-+	#ifndef MAX_RECVBUF_SZ
-+
-+		#ifdef CONFIG_MINIMAL_MEMORY_USAGE
-+			#define MAX_RECVBUF_SZ (4000) /* about 4K */
-+		#else
-+			#ifdef CONFIG_PLATFORM_HISILICON
-+				#define MAX_RECVBUF_SZ (16384) /* 16k */
-+			#else
-+				#define MAX_RECVBUF_SZ (32768) /* 32k */
-+			#endif
-+			/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
-+			/* #define MAX_RECVBUF_SZ (10240)  */ /* 10K */
-+			/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
-+			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k		 */
-+		#endif
-+	#endif /* !MAX_RECVBUF_SZ */
-+#elif defined(CONFIG_PCI_HCI)
-+	#define MAX_RECVBUF_SZ (4000) /* about 4K */
-+#elif defined(CONFIG_SDIO_HCI)
-+	/* minmum 4K, multiple of 8-byte is required, multiple of sdio block size is prefered */
-+	#define MAX_RECVBUF_SZ _RND(RX_DMA_BOUNDARY_8188F + 1, 8)
-+#endif /* CONFIG_SDIO_HCI */
-+
-+/* Rx smooth factor */
-+#define	Rx_Smooth_Factor (20)
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+s32 rtl8188fs_init_recv_priv(PADAPTER padapter);
-+void rtl8188fs_free_recv_priv(PADAPTER padapter);
-+s32 rtl8188fs_recv_hdl(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+int rtl8188fu_init_recv_priv(_adapter *padapter);
-+void rtl8188fu_free_recv_priv(_adapter *padapter);
-+void rtl8188fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+s32 rtl8188fe_init_recv_priv(PADAPTER padapter);
-+void rtl8188fe_free_recv_priv(PADAPTER padapter);
-+#endif
-+
-+void rtl8188f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
-+
-+#endif /* __RTL8188F_RECV_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188f_rf.h b/drivers/staging/rtl8723cs/include/rtl8188f_rf.h
-new file mode 100644
-index 000000000000..a0338313b580
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188f_rf.h
-@@ -0,0 +1,25 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188F_RF_H__
-+#define __RTL8188F_RF_H__
-+
-+int	PHY_RF6052_Config8188F(PADAPTER		Adapter);
-+
-+void
-+PHY_RF6052SetBandwidth8188F(
-+		PADAPTER				Adapter,
-+		enum channel_width		Bandwidth);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188f_spec.h b/drivers/staging/rtl8723cs/include/rtl8188f_spec.h
-new file mode 100644
-index 000000000000..d947ba800627
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188f_spec.h
-@@ -0,0 +1,275 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188F_SPEC_H__
-+#define __RTL8188F_SPEC_H__
-+
-+#include <drv_conf.h>
-+
-+
-+#define HAL_NAV_UPPER_UNIT_8188F		128		/* micro-second */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0000h ~ 0x00FFh	System Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_RSV_CTRL_8188F				0x001C	/* 3 Byte */
-+#define REG_BT_WIFI_ANTENNA_SWITCH_8188F	0x0038
-+#define REG_HSISR_8188F					0x005c
-+#define REG_PAD_CTRL1_8188F		0x0064
-+#define REG_AFE_CTRL_4_8188F		0x0078
-+#define REG_HMEBOX_DBG_0_8188F	0x0088
-+#define REG_HMEBOX_DBG_1_8188F	0x008A
-+#define REG_HMEBOX_DBG_2_8188F	0x008C
-+#define REG_HMEBOX_DBG_3_8188F	0x008E
-+#define REG_HIMR0_8188F					0x00B0
-+#define REG_HISR0_8188F					0x00B4
-+#define REG_HIMR1_8188F					0x00B8
-+#define REG_HISR1_8188F					0x00BC
-+#define REG_PMC_DBG_CTRL2_8188F			0x00CC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_C2HEVT_CMD_ID_8188F	0x01A0
-+#define REG_C2HEVT_CMD_LEN_8188F	0x01AE
-+#define REG_WOWLAN_WAKE_REASON 0x01C7
-+#define REG_WOWLAN_GTK_DBG1	0x630
-+#define REG_WOWLAN_GTK_DBG2	0x634
-+
-+#define REG_HMEBOX_EXT0_8188F			0x01F0
-+#define REG_HMEBOX_EXT1_8188F			0x01F4
-+#define REG_HMEBOX_EXT2_8188F			0x01F8
-+#define REG_HMEBOX_EXT3_8188F			0x01FC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_RXDMA_CONTROL_8188F		0x0286 /* Control the RX DMA. */
-+#define REG_RXDMA_MODE_CTRL_8188F		0x0290
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0300h ~ 0x03FFh	PCIe
-+ *
-+ * ----------------------------------------------------- */
-+#define	REG_PCIE_CTRL_REG_8188F		0x0300
-+#define	REG_INT_MIG_8188F				0x0304	/* Interrupt Migration */
-+#define	REG_BCNQ_DESA_8188F			0x0308	/* TX Beacon Descriptor Address */
-+#define	REG_HQ_DESA_8188F				0x0310	/* TX High Queue Descriptor Address */
-+#define	REG_MGQ_DESA_8188F			0x0318	/* TX Manage Queue Descriptor Address */
-+#define	REG_VOQ_DESA_8188F			0x0320	/* TX VO Queue Descriptor Address */
-+#define	REG_VIQ_DESA_8188F				0x0328	/* TX VI Queue Descriptor Address */
-+#define	REG_BEQ_DESA_8188F			0x0330	/* TX BE Queue Descriptor Address */
-+#define	REG_BKQ_DESA_8188F			0x0338	/* TX BK Queue Descriptor Address */
-+#define	REG_RX_DESA_8188F				0x0340	/* RX Queue	Descriptor Address */
-+#define	REG_DBI_WDATA_8188F			0x0348	/* DBI Write Data */
-+#define	REG_DBI_RDATA_8188F			0x034C	/* DBI Read Data */
-+#define	REG_DBI_ADDR_8188F				0x0350	/* DBI Address */
-+#define	REG_DBI_FLAG_8188F				0x0352	/* DBI Read/Write Flag */
-+#define	REG_MDIO_WDATA_8188F		0x0354	/* MDIO for Write PCIE PHY */
-+#define	REG_MDIO_RDATA_8188F			0x0356	/* MDIO for Reads PCIE PHY */
-+#define	REG_MDIO_CTL_8188F			0x0358	/* MDIO for Control */
-+#define	REG_DBG_SEL_8188F				0x0360	/* Debug Selection Register */
-+#define	REG_PCIE_HRPWM_8188F			0x0361	/* PCIe RPWM */
-+#define	REG_PCIE_HCPWM_8188F			0x0363	/* PCIe CPWM */
-+#define	REG_PCIE_MULTIFET_CTRL_8188F	0x036A	/* PCIE Multi-Fethc Control */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0400h ~ 0x047Fh	Protocol Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_TXPKTBUF_BCNQ_BDNY_8188F	0x0424
-+#define REG_TXPKTBUF_MGQ_BDNY_8188F	0x0425
-+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F	0x045D
-+#ifdef CONFIG_WOWLAN
-+#define REG_TXPKTBUF_IV_LOW             0x0484
-+#define REG_TXPKTBUF_IV_HIGH            0x0488
-+#endif
-+#define REG_AMPDU_BURST_MODE_8188F	0x04BC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0500h ~ 0x05FFh	EDCA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_SECONDARY_CCA_CTRL_8188F	0x0577
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0600h ~ 0x07FFh	WMAC Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+
-+/* ************************************************************
-+ * SDIO Bus Specification
-+ * ************************************************************ */
-+
-+/* -----------------------------------------------------
-+ * SDIO CMD Address Mapping
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ * I/O bus domain (Host)
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ * SDIO register
-+ * ----------------------------------------------------- */
-+#define SDIO_REG_HIQ_FREEPG_8188F		0x0020
-+#define SDIO_REG_MID_FREEPG_8188F		0x0022
-+#define SDIO_REG_LOW_FREEPG_8188F		0x0024
-+#define SDIO_REG_PUB_FREEPG_8188F		0x0026
-+#define SDIO_REG_EXQ_FREEPG_8188F		0x0028
-+#define SDIO_REG_AC_OQT_FREEPG_8188F	0x002A
-+#define SDIO_REG_NOAC_OQT_FREEPG_8188F	0x002B
-+
-+#define SDIO_REG_HCPWM1_8188F			0x0038
-+
-+/* ****************************************************************************
-+ *	8188 Regsiter Bit and Content definition
-+ * **************************************************************************** */
-+
-+/* 2 HSISR
-+ * interrupt mask which needs to clear */
-+#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
-+		HSISR_SPS_OCP_INT |\
-+		HSISR_RON_INT |\
-+		HSISR_PDNINT |\
-+		HSISR_GPIO9_INT)
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define BIT_USB_RXDMA_AGG_EN	BIT(31)
-+#define RXDMA_AGG_MODE_EN		BIT(1)
-+
-+#ifdef CONFIG_WOWLAN
-+#define RXPKT_RELEASE_POLL		BIT(16)
-+#define RXDMA_IDLE				BIT(17)
-+#define RW_RELEASE_EN			BIT(18)
-+#endif
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0400h ~ 0x047Fh	Protocol Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* ----------------------------------------------------------------------------
-+ * 8188F REG_CCK_CHECK						(offset 0x454)
-+ * ---------------------------------------------------------------------------- */
-+#define BIT_BCN_PORT_SEL		BIT(5)
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0500h ~ 0x05FFh	EDCA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0600h ~ 0x07FFh	WMAC Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* ----------------------------------------------------------------------------
-+ * 8195 IMR/ISR bits						(offset 0xB0,  8bits)
-+ * ---------------------------------------------------------------------------- */
-+#define	IMR_DISABLED_8188F					0
-+/* IMR DW0(0x00B0-00B3) Bit 0-31 */
-+#define	IMR_TIMER2_8188F					BIT(31)		/* Timeout interrupt 2 */
-+#define	IMR_TIMER1_8188F					BIT(30)		/* Timeout interrupt 1	 */
-+#define	IMR_PSTIMEOUT_8188F				BIT(29)		/* Power Save Time Out Interrupt */
-+#define	IMR_GTINT4_8188F					BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
-+#define	IMR_GTINT3_8188F					BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
-+#define	IMR_TXBCN0ERR_8188F				BIT(26)		/* Transmit Beacon0 Error			 */
-+#define	IMR_TXBCN0OK_8188F				BIT(25)		/* Transmit Beacon0 OK			 */
-+#define	IMR_TSF_BIT32_TOGGLE_8188F		BIT(24)		/* TSF Timer BIT(32) toggle indication interrupt			 */
-+#define	IMR_BCNDMAINT0_8188F				BIT(20)		/* Beacon DMA Interrupt 0			 */
-+#define	IMR_BCNDERR0_8188F				BIT(16)		/* Beacon Queue DMA OK0			 */
-+#define	IMR_HSISR_IND_ON_INT_8188F		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
-+#define	IMR_BCNDMAINT_E_8188F			BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
-+#define	IMR_ATIMEND_8188F				BIT(12)		/* CTWidnow End or ATIM Window End */
-+#define	IMR_C2HCMD_8188F					BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
-+#define	IMR_CPWM2_8188F					BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
-+#define	IMR_CPWM_8188F					BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
-+#define	IMR_HIGHDOK_8188F				BIT(7)			/* High Queue DMA OK	 */
-+#define	IMR_MGNTDOK_8188F				BIT(6)			/* Management Queue DMA OK	 */
-+#define	IMR_BKDOK_8188F					BIT(5)			/* AC_BK DMA OK		 */
-+#define	IMR_BEDOK_8188F					BIT(4)			/* AC_BE DMA OK	 */
-+#define	IMR_VIDOK_8188F					BIT(3)			/* AC_VI DMA OK		 */
-+#define	IMR_VODOK_8188F					BIT(2)			/* AC_VO DMA OK	 */
-+#define	IMR_RDU_8188F					BIT(1)			/* Rx Descriptor Unavailable	 */
-+#define	IMR_ROK_8188F					BIT(0)			/* Receive DMA OK */
-+
-+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
-+#define	IMR_BCNDMAINT7_8188F				BIT(27)		/* Beacon DMA Interrupt 7 */
-+#define	IMR_BCNDMAINT6_8188F				BIT(26)		/* Beacon DMA Interrupt 6 */
-+#define	IMR_BCNDMAINT5_8188F				BIT(25)		/* Beacon DMA Interrupt 5 */
-+#define	IMR_BCNDMAINT4_8188F				BIT(24)		/* Beacon DMA Interrupt 4 */
-+#define	IMR_BCNDMAINT3_8188F				BIT(23)		/* Beacon DMA Interrupt 3 */
-+#define	IMR_BCNDMAINT2_8188F				BIT(22)		/* Beacon DMA Interrupt 2 */
-+#define	IMR_BCNDMAINT1_8188F				BIT(21)		/* Beacon DMA Interrupt 1 */
-+#define	IMR_BCNDOK7_8188F					BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
-+#define	IMR_BCNDOK6_8188F					BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
-+#define	IMR_BCNDOK5_8188F					BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
-+#define	IMR_BCNDOK4_8188F					BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
-+#define	IMR_BCNDOK3_8188F					BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
-+#define	IMR_BCNDOK2_8188F					BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
-+#define	IMR_BCNDOK1_8188F					BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
-+#define	IMR_ATIMEND_E_8188F				BIT(13)		/* ATIM Window End Extension for Win7 */
-+#define	IMR_TXERR_8188F					BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
-+#define	IMR_RXERR_8188F					BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
-+#define	IMR_TXFOVW_8188F					BIT(9)			/* Transmit FIFO Overflow */
-+#define	IMR_RXFOVW_8188F					BIT(8)			/* Receive FIFO Overflow */
-+
-+#ifdef CONFIG_PCI_HCI
-+/* #define IMR_RX_MASK		(IMR_ROK_8188F|IMR_RDU_8188F|IMR_RXFOVW_8188F) */
-+#define IMR_TX_MASK			(IMR_VODOK_8188F | IMR_VIDOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F | IMR_MGNTDOK_8188F | IMR_HIGHDOK_8188F)
-+
-+#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8188F | IMR_TXBCN0OK_8188F | IMR_TXBCN0ERR_8188F | IMR_BCNDERR0_8188F)
-+
-+#define RT_AC_INT_MASKS	(IMR_VIDOK_8188F | IMR_VODOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F)
-+#endif
-+
-+#endif /* __RTL8188F_SPEC_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188f_sreset.h b/drivers/staging/rtl8723cs/include/rtl8188f_sreset.h
-new file mode 100644
-index 000000000000..fe56567e7396
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188f_sreset.h
-@@ -0,0 +1,24 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8188F_SRESET_H_
-+#define _RTL8188F_SRESET_H_
-+
-+#include <rtw_sreset.h>
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+extern void rtl8188f_sreset_xmit_status_check(_adapter *padapter);
-+extern void rtl8188f_sreset_linked_status_check(_adapter *padapter);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8188f_xmit.h b/drivers/staging/rtl8723cs/include/rtl8188f_xmit.h
-new file mode 100644
-index 000000000000..7dafd9e415e1
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8188f_xmit.h
-@@ -0,0 +1,340 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8188F_XMIT_H__
-+#define __RTL8188F_XMIT_H__
-+
-+
-+#define MAX_TID (15)
-+
-+
-+#ifndef __INC_HAL8188FDESC_H
-+#define __INC_HAL8188FDESC_H
-+
-+#define RX_STATUS_DESC_SIZE_8188F		24
-+#define RX_DRV_INFO_SIZE_UNIT_8188F 8
-+
-+
-+/* DWORD 0 */
-+#define SET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
-+#define SET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
-+#define SET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
-+
-+#define GET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
-+#define GET_RX_STATUS_DESC_CRC32_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
-+#define GET_RX_STATUS_DESC_ICV_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
-+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
-+#define GET_RX_STATUS_DESC_SECURITY_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
-+#define GET_RX_STATUS_DESC_QOS_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
-+#define GET_RX_STATUS_DESC_SHIFT_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
-+#define GET_RX_STATUS_DESC_PHY_STATUS_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
-+#define GET_RX_STATUS_DESC_SWDEC_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
-+#define GET_RX_STATUS_DESC_LAST_SEG_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
-+#define GET_RX_STATUS_DESC_FIRST_SEG_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
-+#define GET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
-+#define GET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
-+
-+/* DWORD 1 */
-+#define GET_RX_STATUS_DESC_MACID_8188F(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
-+#define GET_RX_STATUS_DESC_TID_8188F(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
-+#define GET_RX_STATUS_DESC_AMSDU_8188F(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
-+#define GET_RX_STATUS_DESC_RXID_MATCH_8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
-+#define GET_RX_STATUS_DESC_PAGGR_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
-+#define GET_RX_STATUS_DESC_A1_FIT_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
-+#define GET_RX_STATUS_DESC_CHKERR_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
-+#define GET_RX_STATUS_DESC_IPVER_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
-+#define GET_RX_STATUS_DESC_IS_TCPUDP__8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
-+#define GET_RX_STATUS_DESC_CHK_VLD_8188F(__pRxDesc)	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
-+#define GET_RX_STATUS_DESC_PAM_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
-+#define GET_RX_STATUS_DESC_PWR_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
-+#define GET_RX_STATUS_DESC_MORE_DATA_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
-+#define GET_RX_STATUS_DESC_MORE_FRAG_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
-+#define GET_RX_STATUS_DESC_TYPE_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
-+#define GET_RX_STATUS_DESC_MC_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
-+#define GET_RX_STATUS_DESC_BC_8188F(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
-+
-+/* DWORD 2 */
-+#define GET_RX_STATUS_DESC_SEQ_8188F(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
-+#define GET_RX_STATUS_DESC_FRAG_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
-+#define GET_RX_STATUS_DESC_RX_IS_QOS_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
-+#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8188F(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
-+#define GET_RX_STATUS_DESC_RPT_SEL_8188F(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
-+
-+/* DWORD 3 */
-+#define GET_RX_STATUS_DESC_RX_RATE_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
-+#define GET_RX_STATUS_DESC_HTC_8188F(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
-+#define GET_RX_STATUS_DESC_EOSP_8188F(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
-+#define GET_RX_STATUS_DESC_BSSID_FIT_8188F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
-+#ifdef CONFIG_USB_RX_AGGREGATION
-+#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8188F(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
-+#endif
-+#define GET_RX_STATUS_DESC_PATTERN_MATCH_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
-+#define GET_RX_STATUS_DESC_UNICAST_MATCH_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
-+#define GET_RX_STATUS_DESC_MAGIC_MATCH_8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
-+
-+/* DWORD 6 */
-+#define GET_RX_STATUS_DESC_SPLCP_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
-+#define GET_RX_STATUS_DESC_LDPC_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
-+#define GET_RX_STATUS_DESC_STBC_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
-+#define GET_RX_STATUS_DESC_BW_8188F(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
-+
-+/* DWORD 5 */
-+#define GET_RX_STATUS_DESC_TSFL_8188F(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
-+
-+#define GET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
-+#define GET_RX_STATUS_DESC_BUFF_ADDR64_8188F(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
-+
-+#define SET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
-+
-+
-+/* Dword 0 */
-+#define GET_TX_DESC_OWN_8188F(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
-+
-+#define SET_TX_DESC_PKT_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
-+#define SET_TX_DESC_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
-+#define SET_TX_DESC_BMC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
-+#define SET_TX_DESC_HTC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
-+#define SET_TX_DESC_LAST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
-+#define SET_TX_DESC_FIRST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
-+#define SET_TX_DESC_LINIP_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
-+#define SET_TX_DESC_NO_ACM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
-+#define SET_TX_DESC_GF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
-+#define SET_TX_DESC_OWN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
-+
-+/* Dword 1 */
-+#define SET_TX_DESC_MACID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
-+#define SET_TX_DESC_QUEUE_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
-+#define SET_TX_DESC_RDG_NAV_EXT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
-+#define SET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
-+#define SET_TX_DESC_PIFS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
-+#define SET_TX_DESC_RATE_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
-+#define SET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
-+#define SET_TX_DESC_SEC_TYPE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
-+#define SET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
-+
-+
-+/* Dword 2 */
-+#define SET_TX_DESC_PAID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
-+#define SET_TX_DESC_CCA_RTS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
-+#define SET_TX_DESC_AGG_ENABLE_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
-+#define SET_TX_DESC_RDG_ENABLE_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
-+#define SET_TX_DESC_AGG_BREAK_8188F(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
-+#define SET_TX_DESC_MORE_FRAG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
-+#define SET_TX_DESC_RAW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
-+#define SET_TX_DESC_SPE_RPT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
-+#define SET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
-+#define SET_TX_DESC_BT_INT_8188F(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
-+#define SET_TX_DESC_GID_8188F(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
-+
-+
-+/* Dword 3 */
-+#define SET_TX_DESC_WHEADER_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
-+#define SET_TX_DESC_CHK_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
-+#define SET_TX_DESC_EARLY_MODE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
-+#define SET_TX_DESC_HWSEQ_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
-+#define SET_TX_DESC_USE_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
-+#define SET_TX_DESC_DISABLE_RTS_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
-+#define SET_TX_DESC_DISABLE_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
-+#define SET_TX_DESC_CTS2SELF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
-+#define SET_TX_DESC_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
-+#define SET_TX_DESC_HW_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
-+#define SET_TX_DESC_NAV_USE_HDR_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
-+#define SET_TX_DESC_USE_MAX_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
-+#define SET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
-+#define SET_TX_DESC_NDPA_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
-+#define SET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
-+
-+/* Dword 4 */
-+#define SET_TX_DESC_TX_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
-+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
-+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
-+#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
-+#define SET_TX_DESC_DATA_RETRY_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
-+#define SET_TX_DESC_RTS_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
-+
-+
-+/* Dword 5 */
-+#define SET_TX_DESC_DATA_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
-+#define SET_TX_DESC_DATA_SHORT_8188F(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
-+#define SET_TX_DESC_DATA_BW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
-+#define SET_TX_DESC_DATA_LDPC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
-+#define SET_TX_DESC_DATA_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
-+#define SET_TX_DESC_CTROL_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
-+#define SET_TX_DESC_RTS_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
-+#define SET_TX_DESC_RTS_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
-+
-+
-+/* Dword 6 */
-+#define SET_TX_DESC_SW_DEFINE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
-+#define SET_TX_DESC_MBSSID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
-+#define SET_TX_DESC_ANTSEL_A_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
-+#define SET_TX_DESC_ANTSEL_B_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
-+#define SET_TX_DESC_ANTSEL_C_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
-+#define SET_TX_DESC_ANTSEL_D_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
-+
-+/* Dword 7 */
-+#ifdef CONFIG_PCI_HCI
-+#define SET_TX_DESC_TX_BUFFER_SIZE_8188F(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+#endif
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
-+#define SET_TX_DESC_TX_DESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+#endif
-+#define SET_TX_DESC_USB_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
-+#ifdef CONFIG_SDIO_HCI
-+#define SET_TX_DESC_SDIO_TXSEQ_8188F(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
-+#endif
-+
-+/* Dword 8 */
-+#define SET_TX_DESC_HWSEQ_EN_8188F(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
-+
-+/* Dword 9 */
-+#define SET_TX_DESC_SEQ_8188F(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
-+
-+/* Dword 10 */
-+#define SET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
-+#define GET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc)	LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
-+
-+/* Dword 11 */
-+#define SET_TX_DESC_NEXT_DESC_ADDRESS_8188F(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
-+
-+
-+#define SET_EARLYMODE_PKTNUM_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
-+#define SET_EARLYMODE_LEN0_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
-+#define SET_EARLYMODE_LEN1_1_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
-+#define SET_EARLYMODE_LEN1_2_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
-+#define SET_EARLYMODE_LEN2_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
-+#define SET_EARLYMODE_LEN3_8188F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
-+
-+#endif
-+/* -----------------------------------------------------------
-+ *
-+ *	Rate
-+ *
-+ * -----------------------------------------------------------
-+ * CCK Rates, TxHT = 0 */
-+#define DESC8188F_RATE1M				0x00
-+#define DESC8188F_RATE2M				0x01
-+#define DESC8188F_RATE5_5M				0x02
-+#define DESC8188F_RATE11M				0x03
-+
-+/* OFDM Rates, TxHT = 0 */
-+#define DESC8188F_RATE6M				0x04
-+#define DESC8188F_RATE9M				0x05
-+#define DESC8188F_RATE12M				0x06
-+#define DESC8188F_RATE18M				0x07
-+#define DESC8188F_RATE24M				0x08
-+#define DESC8188F_RATE36M				0x09
-+#define DESC8188F_RATE48M				0x0a
-+#define DESC8188F_RATE54M				0x0b
-+
-+/* MCS Rates, TxHT = 1 */
-+#define DESC8188F_RATEMCS0				0x0c
-+#define DESC8188F_RATEMCS1				0x0d
-+#define DESC8188F_RATEMCS2				0x0e
-+#define DESC8188F_RATEMCS3				0x0f
-+#define DESC8188F_RATEMCS4				0x10
-+#define DESC8188F_RATEMCS5				0x11
-+#define DESC8188F_RATEMCS6				0x12
-+#define DESC8188F_RATEMCS7				0x13
-+#define DESC8188F_RATEMCS8				0x14
-+#define DESC8188F_RATEMCS9				0x15
-+#define DESC8188F_RATEMCS10		0x16
-+#define DESC8188F_RATEMCS11		0x17
-+#define DESC8188F_RATEMCS12		0x18
-+#define DESC8188F_RATEMCS13		0x19
-+#define DESC8188F_RATEMCS14		0x1a
-+#define DESC8188F_RATEMCS15		0x1b
-+#define DESC8188F_RATEVHTSS1MCS0		0x2c
-+#define DESC8188F_RATEVHTSS1MCS1		0x2d
-+#define DESC8188F_RATEVHTSS1MCS2		0x2e
-+#define DESC8188F_RATEVHTSS1MCS3		0x2f
-+#define DESC8188F_RATEVHTSS1MCS4		0x30
-+#define DESC8188F_RATEVHTSS1MCS5		0x31
-+#define DESC8188F_RATEVHTSS1MCS6		0x32
-+#define DESC8188F_RATEVHTSS1MCS7		0x33
-+#define DESC8188F_RATEVHTSS1MCS8		0x34
-+#define DESC8188F_RATEVHTSS1MCS9		0x35
-+#define DESC8188F_RATEVHTSS2MCS0		0x36
-+#define DESC8188F_RATEVHTSS2MCS1		0x37
-+#define DESC8188F_RATEVHTSS2MCS2		0x38
-+#define DESC8188F_RATEVHTSS2MCS3		0x39
-+#define DESC8188F_RATEVHTSS2MCS4		0x3a
-+#define DESC8188F_RATEVHTSS2MCS5		0x3b
-+#define DESC8188F_RATEVHTSS2MCS6		0x3c
-+#define DESC8188F_RATEVHTSS2MCS7		0x3d
-+#define DESC8188F_RATEVHTSS2MCS8		0x3e
-+#define DESC8188F_RATEVHTSS2MCS9		0x3f
-+
-+
-+#define	RX_HAL_IS_CCK_RATE_8188F(pDesc)\
-+	(GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE1M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE2M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE5_5M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE11M)
-+
-+
-+void rtl8188f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
-+void rtl8188f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
-+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+s32 rtl8188fs_init_xmit_priv(PADAPTER padapter);
-+void rtl8188fs_free_xmit_priv(PADAPTER padapter);
-+s32 rtl8188fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+s32 rtl8188fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+s32 rtl8188fs_hal_mgmt_xmitframe_enqueue(PADAPTER, struct xmit_frame *);
-+#endif
-+s32	rtl8188fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+s32 rtl8188fs_xmit_buf_handler(PADAPTER padapter);
-+thread_return rtl8188fs_xmit_thread(thread_context context);
-+#define hal_xmit_handler rtl8188fs_xmit_buf_handler
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+s32 rtl8188fu_xmit_buf_handler(PADAPTER padapter);
-+#define hal_xmit_handler rtl8188fu_xmit_buf_handler
-+#endif
-+
-+s32 rtl8188fu_init_xmit_priv(PADAPTER padapter);
-+void rtl8188fu_free_xmit_priv(PADAPTER padapter);
-+s32 rtl8188fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+s32 rtl8188fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+s32 rtl8188fu_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+s32	 rtl8188fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */
-+void rtl8188fu_xmit_tasklet(void *priv);
-+s32 rtl8188fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+s32 rtl8188fe_init_xmit_priv(PADAPTER padapter);
-+void rtl8188fe_free_xmit_priv(PADAPTER padapter);
-+struct xmit_buf *rtl8188fe_dequeue_xmitbuf(struct rtw_tx_ring *ring);
-+void	rtl8188fe_xmitframe_resume(_adapter *padapter);
-+s32 rtl8188fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+s32 rtl8188fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+s32	rtl8188fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+void rtl8188fe_xmit_tasklet(void *priv);
-+#endif
-+
-+u8	BWMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib);
-+u8	SCMapping_8188F(PADAPTER Adapter, struct pkt_attrib	*pattrib);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192e_cmd.h b/drivers/staging/rtl8723cs/include/rtl8192e_cmd.h
-new file mode 100644
-index 000000000000..a9c8be840992
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192e_cmd.h
-@@ -0,0 +1,141 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2012 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192E_CMD_H__
-+#define __RTL8192E_CMD_H__
-+
-+typedef enum _RTL8192E_H2C_CMD {
-+	H2C_8192E_RSVDPAGE	= 0x00,
-+	H2C_8192E_MSRRPT	= 0x01,
-+	H2C_8192E_SCAN		= 0x02,
-+	H2C_8192E_KEEP_ALIVE_CTRL = 0x03,
-+	H2C_8192E_DISCONNECT_DECISION = 0x04,
-+	H2C_8192E_INIT_OFFLOAD = 0x06,
-+	H2C_8192E_AP_OFFLOAD = 0x08,
-+	H2C_8192E_BCN_RSVDPAGE = 0x09,
-+	H2C_8192E_PROBERSP_RSVDPAGE = 0x0a,
-+
-+	H2C_8192E_AP_WOW_GPIO_CTRL = 0x13,
-+
-+	H2C_8192E_SETPWRMODE = 0x20,
-+	H2C_8192E_PS_TUNING_PARA = 0x21,
-+	H2C_8192E_PS_TUNING_PARA2 = 0x22,
-+	H2C_8192E_PS_LPS_PARA = 0x23,
-+	H2C_8192E_P2P_PS_OFFLOAD = 0x24,
-+	H2C_8192E_SAP_PS = 0x26,
-+	H2C_8192E_RA_MASK = 0x40,
-+	H2C_8192E_RSSI_REPORT = 0x42,
-+	H2C_8192E_RA_PARA_ADJUST = 0x46,
-+
-+	H2C_8192E_WO_WLAN = 0x80,
-+	H2C_8192E_REMOTE_WAKE_CTRL = 0x81,
-+	H2C_8192E_AOAC_GLOBAL_INFO = 0x82,
-+	H2C_8192E_AOAC_RSVDPAGE = 0x83,
-+
-+	/* Not defined in new 88E H2C CMD Format */
-+	H2C_8192E_SELECTIVE_SUSPEND_ROF_CMD,
-+	H2C_8192E_P2P_PS_MODE,
-+	H2C_8192E_PSD_RESULT,
-+	MAX_8192E_H2CCMD
-+} RTL8192E_H2C_CMD;
-+
-+struct cmd_msg_parm {
-+	u8 eid; /* element id */
-+	u8 sz; /* sz */
-+	u8 buf[6];
-+};
-+
-+enum {
-+	PWRS
-+};
-+
-+typedef struct _SETPWRMODE_PARM {
-+	u8 Mode;/* 0:Active,1:LPS,2:WMMPS */
-+	/* u8 RLBM:4; */ /* 0:Min,1:Max,2: User define */
-+	u8 SmartPS_RLBM;/* LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData */
-+	u8 AwakeInterval;	/* unit: beacon interval */
-+	u8 bAllQueueUAPSD;
-+	u8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */
-+} SETPWRMODE_PARM, *PSETPWRMODE_PARM;
-+
-+struct H2C_SS_RFOFF_PARAM {
-+	u8 ROFOn; /* 1: on, 0:off */
-+	u16 gpio_period; /* unit: 1024 us */
-+} __attribute__((packed));
-+
-+
-+typedef struct JOINBSSRPT_PARM_92E {
-+	u8 OpMode;	/* RT_MEDIA_STATUS */
-+#ifdef CONFIG_WOWLAN
-+	u8 MacID;       /* MACID */
-+#endif /* CONFIG_WOWLAN */
-+} JOINBSSRPT_PARM_92E, *PJOINBSSRPT_PARM_92E;
-+
-+/* move to hal_com_h2c.h
-+typedef struct _RSVDPAGE_LOC_92E {
-+	u8 LocProbeRsp;
-+	u8 LocPsPoll;
-+	u8 LocNullData;
-+	u8 LocQosNull;
-+	u8 LocBTQosNull;
-+} RSVDPAGE_LOC_92E, *PRSVDPAGE_LOC_92E;
-+*/
-+
-+
-+/* _SETPWRMODE_PARM */
-+#define SET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8192E_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
-+#define SET_8192E_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
-+#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8192E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
-+#define SET_8192E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+#define GET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)						LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
-+
-+/* _P2P_PS_OFFLOAD */
-+#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
-+#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
-+#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
-+
-+
-+/* host message to firmware cmd */
-+void rtl8192e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
-+void rtl8192e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
-+s32 FillH2CCmd_8192E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
-+u8 GetTxBufferRsvdPageNum8192E(_adapter *padapter, bool wowlan);
-+/* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */
-+s32 c2h_handler_8192e(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
-+#ifdef CONFIG_BT_COEXIST
-+	void rtl8192e_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
-+#endif /* CONFIG_BT_COEXIST */
-+#ifdef CONFIG_P2P_PS
-+	void rtl8192e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
-+#endif /* CONFIG_P2P */
-+
-+/* / TX Feedback Content */
-+#define	USEC_UNIT_FOR_8192E_C2H_TX_RPT_QUEUE_TIME			256
-+
-+#define	GET_8192E_C2H_TX_RPT_QUEUE_SELECT(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 0, 5)
-+#define	GET_8192E_C2H_TX_RPT_PKT_BROCAST(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 5, 1)
-+#define	GET_8192E_C2H_TX_RPT_LIFE_TIME_OVER(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
-+#define	GET_8192E_C2H_TX_RPT_RETRY_OVER(_Header)				LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
-+#define	GET_8192E_C2H_TX_RPT_MAC_ID(_Header)					LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
-+#define	GET_8192E_C2H_TX_RPT_DATA_RETRY_CNT(_Header)		LE_BITS_TO_1BYTE((_Header + 2), 0, 6)
-+#define	GET_8192E_C2H_TX_RPT_QUEUE_TIME(_Header)				LE_BITS_TO_2BYTE((_Header + 3), 0, 16)	/* In unit of 256 microseconds. */
-+#define	GET_8192E_C2H_TX_RPT_FINAL_DATA_RATE(_Header)		LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
-+
-+#endif /* __RTL8192E_CMD_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192e_dm.h b/drivers/staging/rtl8723cs/include/rtl8192e_dm.h
-new file mode 100644
-index 000000000000..0a65a1be370d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192e_dm.h
-@@ -0,0 +1,28 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2012 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192E_DM_H__
-+#define __RTL8192E_DM_H__
-+
-+
-+void rtl8192e_init_dm_priv(PADAPTER Adapter);
-+void rtl8192e_deinit_dm_priv(PADAPTER Adapter);
-+void rtl8192e_InitHalDm(PADAPTER Adapter);
-+void rtl8192e_HalDmWatchDog(PADAPTER Adapter);
-+
-+/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
-+
-+/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192e_hal.h b/drivers/staging/rtl8723cs/include/rtl8192e_hal.h
-new file mode 100644
-index 000000000000..417147dabe78
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192e_hal.h
-@@ -0,0 +1,330 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2012 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192E_HAL_H__
-+#define __RTL8192E_HAL_H__
-+
-+/* #include "hal_com.h" */
-+
-+#include "hal_data.h"
-+
-+/* include HAL Related header after HAL Related compiling flags */
-+#include "rtl8192e_spec.h"
-+#include "rtl8192e_rf.h"
-+#include "rtl8192e_dm.h"
-+#include "rtl8192e_recv.h"
-+#include "rtl8192e_xmit.h"
-+#include "rtl8192e_cmd.h"
-+#include "rtl8192e_led.h"
-+#include "Hal8192EPwrSeq.h"
-+#include "Hal8192EPhyReg.h"
-+#include "Hal8192EPhyCfg.h"
-+
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	#include "rtl8192e_sreset.h"
-+#endif
-+
-+/* ---------------------------------------------------------------------
-+ *		RTL8192E Power Configuration CMDs for PCIe interface
-+ * --------------------------------------------------------------------- */
-+#define Rtl8192E_NIC_PWR_ON_FLOW				rtl8192E_power_on_flow
-+#define Rtl8192E_NIC_RF_OFF_FLOW				rtl8192E_radio_off_flow
-+#define Rtl8192E_NIC_DISABLE_FLOW				rtl8192E_card_disable_flow
-+#define Rtl8192E_NIC_ENABLE_FLOW				rtl8192E_card_enable_flow
-+#define Rtl8192E_NIC_SUSPEND_FLOW				rtl8192E_suspend_flow
-+#define Rtl8192E_NIC_RESUME_FLOW				rtl8192E_resume_flow
-+#define Rtl8192E_NIC_PDN_FLOW					rtl8192E_hwpdn_flow
-+#define Rtl8192E_NIC_LPS_ENTER_FLOW			rtl8192E_enter_lps_flow
-+#define Rtl8192E_NIC_LPS_LEAVE_FLOW			rtl8192E_leave_lps_flow
-+
-+
-+#if 1 /* download firmware related data structure */
-+#define FW_SIZE_8192E			0x8000 /* Compatible with RTL8192e Maximal RAM code size 32k */
-+#define FW_START_ADDRESS		0x1000
-+#define FW_END_ADDRESS			0x5FFF
-+
-+
-+#define IS_FW_HEADER_EXIST_8192E(_pFwHdr)	((GET_FIRMWARE_HDR_SIGNATURE_8192E(_pFwHdr) & 0xFFF0) == 0x92E0)
-+
-+
-+
-+typedef struct _RT_FIRMWARE_8192E {
-+	FIRMWARE_SOURCE	eFWSource;
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+	u8			*szFwBuffer;
-+#else
-+	u8			szFwBuffer[FW_SIZE_8192E];
-+#endif
-+	u32			ulFwLength;
-+} RT_FIRMWARE_8192E, *PRT_FIRMWARE_8192E;
-+
-+/*
-+ * This structure must be cared byte-ordering
-+ *
-+ * Added by tynli. 2009.12.04. */
-+
-+/* *****************************************************
-+ *					Firmware Header(8-byte alinment required)
-+ * *****************************************************
-+ * --- LONG WORD 0 ---- */
-+#define GET_FIRMWARE_HDR_SIGNATURE_8192E(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 0, 16) /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
-+#define GET_FIRMWARE_HDR_CATEGORY_8192E(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */
-+#define GET_FIRMWARE_HDR_FUNCTION_8192E(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
-+#define GET_FIRMWARE_HDR_VERSION_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */
-+#define GET_FIRMWARE_HDR_SUB_VER_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */
-+#define GET_FIRMWARE_HDR_RSVD1_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8)
-+
-+/* --- LONG WORD 1 ---- */
-+#define GET_FIRMWARE_HDR_MONTH_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) /* Release time Month field */
-+#define GET_FIRMWARE_HDR_DATE_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) /* Release time Date field */
-+#define GET_FIRMWARE_HDR_HOUR_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)/* Release time Hour field */
-+#define GET_FIRMWARE_HDR_MINUTE_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)/* Release time Minute field */
-+#define GET_FIRMWARE_HDR_ROMCODE_SIZE_8192E(__FwHdr)	LE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)/* The size of RAM code */
-+#define GET_FIRMWARE_HDR_RSVD2_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+12, 16, 16)
-+
-+/* --- LONG WORD 2 ---- */
-+#define GET_FIRMWARE_HDR_SVN_IDX_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)/* The SVN entry index */
-+#define GET_FIRMWARE_HDR_RSVD3_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+20, 0, 32)
-+
-+/* --- LONG WORD 3 ---- */
-+#define GET_FIRMWARE_HDR_RSVD4_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 0, 32)
-+#define GET_FIRMWARE_HDR_RSVD5_8192E(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)
-+
-+#endif /* download firmware related data structure */
-+
-+#define DRIVER_EARLY_INT_TIME_8192E		0x05
-+#define BCN_DMA_ATIME_INT_TIME_8192E		0x02
-+#define RX_DMA_SIZE_8192E					0x4000	/* 16K*/
-+
-+#ifdef CONFIG_WOWLAN
-+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
-+#else
-+	#define RESV_FMWF	0
-+#endif
-+
-+#ifdef CONFIG_FW_C2H_DEBUG
-+	#define RX_DMA_RESERVED_SIZE_8192E	0x100	/* 256B, reserved for c2h debug message*/
-+#else
-+	#define RX_DMA_RESERVED_SIZE_8192E	0x40	/* 64B, reserved for c2h event(16bytes) or ccx(8 Bytes)*/
-+#endif
-+#define MAX_RX_DMA_BUFFER_SIZE_8192E		(RX_DMA_SIZE_8192E-RX_DMA_RESERVED_SIZE_8192E)	/*RX 16K*/
-+
-+
-+#define PAGE_SIZE_TX_92E	PAGE_SIZE_256
-+
-+/* For General Reserved Page Number(Beacon Queue is reserved page)
-+ * if (CONFIG_2BCN_EN) Beacon:4, PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1
-+ * Beacon: MAX_BEACON_LEN / PAGE_SIZE_TX_92E
-+ * PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1,CTS-2-SELF / LTE QoS Null*/
-+
-+#define RSVD_PAGE_NUM_8192E		(MAX_BEACON_LEN / PAGE_SIZE_TX_92E + 6) /*0x08*/
-+/* For WoWLan , more reserved page
-+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6
-+ * NS offload: 2 NDP info: 1
-+ */
-+#ifdef CONFIG_WOWLAN
-+	#define WOWLAN_PAGE_NUM_8192E	0x0b
-+#else
-+	#define WOWLAN_PAGE_NUM_8192E	0x00
-+#endif
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+	#undef WOWLAN_PAGE_NUM_8192E
-+	#define WOWLAN_PAGE_NUM_8192E	0x0d
-+#endif
-+
-+/* Note:
-+Tx FIFO Size : 64KB
-+Tx page Size : 256B
-+Total page numbers : 256(0x100)
-+*/
-+
-+#define	TOTAL_RSVD_PAGE_NUMBER_8192E	(RSVD_PAGE_NUM_8192E + WOWLAN_PAGE_NUM_8192E)
-+
-+#define	TOTAL_PAGE_NUMBER_8192E	(0x100)
-+#define	TX_TOTAL_PAGE_NUMBER_8192E	(TOTAL_PAGE_NUMBER_8192E - TOTAL_RSVD_PAGE_NUMBER_8192E)
-+
-+#define	TX_PAGE_BOUNDARY_8192E	(TX_TOTAL_PAGE_NUMBER_8192E) /* beacon header start address */
-+
-+
-+#define RSVD_PKT_LEN_92E	(TOTAL_RSVD_PAGE_NUMBER_8192E * PAGE_SIZE_TX_92E)
-+
-+#define TX_PAGE_LOAD_FW_BOUNDARY_8192E		0x47 /* 0xA5 */
-+#define TX_PAGE_BOUNDARY_WOWLAN_8192E		0xE0
-+
-+/* For Normal Chip Setting
-+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_92C */
-+
-+#define NORMAL_PAGE_NUM_HPQ_8192E			0x10
-+#define NORMAL_PAGE_NUM_LPQ_8192E			0x10
-+#define NORMAL_PAGE_NUM_NPQ_8192E			0x10
-+#define NORMAL_PAGE_NUM_EPQ_8192E			0x00
-+
-+
-+/* Note: For WMM Normal Chip Setting ,modify later */
-+#define WMM_NORMAL_PAGE_NUM_HPQ_8192E		NORMAL_PAGE_NUM_HPQ_8192E
-+#define WMM_NORMAL_PAGE_NUM_LPQ_8192E		NORMAL_PAGE_NUM_LPQ_8192E
-+#define WMM_NORMAL_PAGE_NUM_NPQ_8192E		NORMAL_PAGE_NUM_NPQ_8192E
-+
-+
-+/* -------------------------------------------------------------------------
-+ *	Chip specific
-+ * ------------------------------------------------------------------------- */
-+
-+/* pic buffer descriptor */
-+#define RTL8192EE_SEG_NUM			TX_BUFFER_SEG_NUM
-+#define TX_DESC_NUM_92E			128
-+#define RX_DESC_NUM_92E			128
-+
-+/* -------------------------------------------------------------------------
-+ *	Channel Plan
-+ * ------------------------------------------------------------------------- */
-+
-+#define		HWSET_MAX_SIZE_8192E			512
-+
-+#define		EFUSE_REAL_CONTENT_LEN_8192E	512
-+
-+#define		EFUSE_MAP_LEN_8192E			512
-+#define		EFUSE_MAX_SECTION_8192E		64
-+#define		EFUSE_MAX_WORD_UNIT_8192E		4
-+#define		EFUSE_IC_ID_OFFSET_8192E		506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
-+#define		AVAILABLE_EFUSE_ADDR_8192E(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8192E)
-+/*
-+ * <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
-+ * 9bytes + 1byt + 5bytes and pre 1byte.
-+ * For worst case:
-+ * | 1byte|----8bytes----|1byte|--5bytes--|
-+ * |         |            Reserved(14bytes)	      |
-+ *   */
-+#define		EFUSE_OOB_PROTECT_BYTES_8192E 		15	/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
-+
-+
-+
-+/* ********************************************************
-+ *			EFUSE for BT definition
-+ * ******************************************************** */
-+#define		EFUSE_BT_REAL_BANK_CONTENT_LEN_8192E	512
-+#define		EFUSE_BT_REAL_CONTENT_LEN_8192E			1024	/* 512*2 */
-+#define		EFUSE_BT_MAP_LEN_8192E					1024	/* 1k bytes */
-+#define		EFUSE_BT_MAX_SECTION_8192E				128		/* 1024/8 */
-+
-+#define		EFUSE_PROTECT_BYTES_BANK_8192E			16
-+#define		EFUSE_MAX_BANK_8192E					3
-+/* *********************************************************** */
-+
-+#define INCLUDE_MULTI_FUNC_BT(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
-+#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
-+
-+/* #define IS_MULTI_FUNC_CHIP(_Adapter)	(((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */
-+
-+/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */
-+
-+/* rtl8812_hal_init.c */
-+void	_8051Reset8192E(PADAPTER padapter);
-+s32	FirmwareDownload8192E(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw);
-+void	InitializeFirmwareVars8192E(PADAPTER padapter);
-+
-+s32	InitLLTTable8192E(PADAPTER padapter, u8 txpktbuf_bndy);
-+
-+/* EFuse */
-+u8	GetEEPROMSize8192E(PADAPTER padapter);
-+void	hal_InitPGData_8192E(PADAPTER padapter, u8 *PROMContent);
-+void	Hal_EfuseParseIDCode8192E(PADAPTER padapter, u8 *hwinfo);
-+void	Hal_ReadPROMVersion8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void	Hal_ReadPowerSavingMode8192E(PADAPTER padapter, u8	*hwinfo, BOOLEAN	AutoLoadFail);
-+void	Hal_ReadTxPowerInfo8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
-+void	Hal_ReadBoardType8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void	Hal_ReadThermalMeter_8192E(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN	AutoloadFail);
-+void	Hal_ReadChannelPlan8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void	Hal_EfuseParseXtal_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void	Hal_ReadAntennaDiversity8192E(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
-+void	Hal_ReadPAType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+void	Hal_ReadAmplifierType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+void	Hal_ReadRFEType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+void	Hal_EfuseParseBTCoexistInfo8192E(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void	Hal_EfuseParseKFreeData_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+
-+u8 Hal_CrystalAFEAdjust(_adapter *Adapter);
-+
-+BOOLEAN HalDetectPwrDownMode8192E(PADAPTER Adapter);
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+	void Hal_DetectWoWMode(PADAPTER pAdapter);
-+#endif /* CONFIG_WOWLAN */
-+
-+/***********************************************************/
-+/* RTL8192E-MAC Setting */
-+void _InitQueueReservedPage_8192E(PADAPTER Adapter);
-+void _InitQueuePriority_8192E(PADAPTER Adapter);
-+void _InitTxBufferBoundary_8192E(PADAPTER Adapter, u8 txpktbuf_bndy);
-+void _InitPageBoundary_8192E(PADAPTER Adapter);
-+/* void _InitTransferPageSize_8192E(PADAPTER Adapter); */
-+void _InitDriverInfoSize_8192E(PADAPTER Adapter, u8 drvInfoSize);
-+void _InitRDGSetting_8192E(PADAPTER Adapter);
-+void _InitID_8192E(PADAPTER Adapter);
-+void _InitNetworkType_8192E(PADAPTER Adapter);
-+void _InitWMACSetting_8192E(PADAPTER Adapter);
-+void _InitAdaptiveCtrl_8192E(PADAPTER Adapter);
-+void _InitEDCA_8192E(PADAPTER Adapter);
-+void _InitRetryFunction_8192E(PADAPTER Adapter);
-+void _BBTurnOnBlock_8192E(PADAPTER Adapter);
-+void _InitBeaconParameters_8192E(PADAPTER Adapter);
-+void _InitBeaconMaxError_8192E(
-+		PADAPTER	Adapter,
-+		BOOLEAN		InfraMode
-+);
-+void SetBeaconRelatedRegisters8192E(PADAPTER padapter);
-+void hal_ReadRFType_8192E(PADAPTER	Adapter);
-+/* RTL8192E-MAC Setting
-+ ***********************************************************/
-+
-+u8 SetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val);
-+void GetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val);
-+u8
-+SetHalDefVar8192E(
-+		PADAPTER				Adapter,
-+		HAL_DEF_VARIABLE		eVariable,
-+		void						*pValue
-+);
-+u8
-+GetHalDefVar8192E(
-+		PADAPTER				Adapter,
-+		HAL_DEF_VARIABLE		eVariable,
-+		void						*pValue
-+);
-+
-+void rtl8192e_set_hal_ops(struct hal_ops *pHalFunc);
-+void init_hal_spec_8192e(_adapter *adapter);
-+void rtl8192e_init_default_value(_adapter *padapter);
-+
-+void rtl8192e_start_thread(_adapter *padapter);
-+void rtl8192e_stop_thread(_adapter *padapter);
-+
-+#ifdef CONFIG_PCI_HCI
-+	BOOLEAN	InterruptRecognized8192EE(PADAPTER Adapter);
-+	u16	get_txbd_rw_reg(u16 ff_hwaddr);
-+#endif
-+
-+#ifdef CONFIG_SDIO_HCI
-+	#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+		void _init_available_page_threshold(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ);
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_BT_COEXIST
-+	void rtl8192e_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
-+#endif
-+
-+#endif /* __RTL8192E_HAL_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192e_led.h b/drivers/staging/rtl8723cs/include/rtl8192e_led.h
-new file mode 100644
-index 000000000000..3d795c4055a8
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192e_led.h
-@@ -0,0 +1,36 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2012 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192E_LED_H__
-+#define __RTL8192E_LED_H__
-+
-+#ifdef CONFIG_RTW_SW_LED
-+/* ********************************************************************************
-+ * Interface to manipulate LED objects.
-+ * ******************************************************************************** */
-+#ifdef CONFIG_USB_HCI
-+	void rtl8192eu_InitSwLeds(PADAPTER padapter);
-+	void rtl8192eu_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+	void rtl8192ee_InitSwLeds(PADAPTER padapter);
-+	void rtl8192ee_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_SDIO_HCI
-+	void rtl8192es_InitSwLeds(PADAPTER padapter);
-+	void rtl8192es_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+
-+#endif
-+#endif/*CONFIG_RTW_SW_LED*/
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192e_recv.h b/drivers/staging/rtl8723cs/include/rtl8192e_recv.h
-new file mode 100644
-index 000000000000..c19a98080835
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192e_recv.h
-@@ -0,0 +1,175 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2012 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192E_RECV_H__
-+#define __RTL8192E_RECV_H__
-+
-+#if defined(CONFIG_USB_HCI)
-+
-+	#ifndef MAX_RECVBUF_SZ
-+		#ifdef CONFIG_MINIMAL_MEMORY_USAGE
-+			#define MAX_RECVBUF_SZ (4000) /* about 4K */
-+		#else
-+			#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
-+				#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/
-+			#elif defined(CONFIG_PLATFORM_HISILICON)
-+				#define MAX_RECVBUF_SZ (16384) /* 16k */
-+			#else
-+				#define MAX_RECVBUF_SZ (32768) /* 32k */
-+			#endif
-+			/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
-+			/* #define MAX_RECVBUF_SZ (10240)  */ /* 10K */
-+			/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
-+			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k		 */
-+			#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
-+				#undef MAX_RECVBUF_SZ
-+				#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
-+			#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
-+		#endif
-+	#endif /* !MAX_RECVBUF_SZ */
-+
-+#elif defined(CONFIG_PCI_HCI)
-+	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
-+	/*	#define MAX_RECVBUF_SZ (9100) */
-+	/* #else */
-+	#define MAX_RECVBUF_SZ (4000) /* about 4K
-+	* #endif */
-+
-+
-+#elif defined(CONFIG_SDIO_HCI)
-+
-+	#define MAX_RECVBUF_SZ (16384)
-+
-+#endif
-+
-+
-+/* Rx smooth factor */
-+#define Rx_Smooth_Factor (20)
-+
-+/* *************
-+ * [1] Rx Buffer Descriptor (for PCIE) buffer descriptor architecture
-+ * DWORD 0 */
-+#define SET_RX_BUFFER_DESC_DATA_LENGTH_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
-+#define SET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
-+#define SET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
-+#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
-+
-+#define GET_RX_BUFFER_DESC_OWN_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
-+#define GET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
-+#define GET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
-+#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
-+
-+
-+/* DWORD 1 */
-+#define SET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
-+#define GET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 32)
-+
-+/* DWORD 2 */
-+#define SET_RX_BUFFER_PHYSICAL_HIGH_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
-+
-+/* *************
-+ * [2] Rx Descriptor
-+ * DWORD 0 */
-+#define GET_RX_STATUS_DESC_PKT_LEN_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
-+#define GET_RX_STATUS_DESC_CRC32_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
-+#define GET_RX_STATUS_DESC_ICVERR_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
-+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
-+#define GET_RX_STATUS_DESC_SECURITY_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
-+#define GET_RX_STATUS_DESC_QOS_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
-+#define GET_RX_STATUS_DESC_SHIFT_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
-+#define GET_RX_STATUS_DESC_PHY_STATUS_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
-+#define GET_RX_STATUS_DESC_SWDEC_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
-+#define GET_RX_STATUS_DESC_EOR_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
-+#define GET_RX_STATUS_DESC_OWN_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
-+
-+
-+#define SET_RX_STATUS_DESC_PKT_LEN_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
-+#define SET_RX_STATUS_DESC_EOR_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
-+#define SET_RX_STATUS_DESC_OWN_92E(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
-+
-+/* DWORD 1 */
-+#define GET_RX_STATUS_DESC_MACID_92E(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
-+#define GET_RX_STATUS_DESC_TID_92E(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
-+#define GET_RX_STATUS_DESC_MACID_VLD_92E(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 12, 1)
-+#define GET_RX_STATUS_DESC_AMSDU_92E(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
-+#define GET_RX_STATUS_DESC_RXID_MATCH_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
-+#define GET_RX_STATUS_DESC_PAGGR_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 15, 1)
-+#define GET_RX_STATUS_DESC_A1_FITS_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 16, 4)
-+#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHKERR_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 20, 1)
-+#define GET_RX_STATUS_DESC_TCPOFFLOAD_IPVER_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 21, 1)
-+#define GET_RX_STATUS_DESC_TCPOFFLOAD_IS_TCPUDP_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 22, 1)
-+#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHK_VLD_92E(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 23, 1)
-+#define GET_RX_STATUS_DESC_PAM_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 24, 1)
-+#define GET_RX_STATUS_DESC_PWR_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 1)
-+#define GET_RX_STATUS_DESC_MORE_DATA_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 26, 1)
-+#define GET_RX_STATUS_DESC_MORE_FRAG_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 27, 1)
-+#define GET_RX_STATUS_DESC_TYPE_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 2)
-+#define GET_RX_STATUS_DESC_MC_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 1)
-+#define GET_RX_STATUS_DESC_BC_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 31, 1)
-+
-+/* DWORD 2 */
-+#define GET_RX_STATUS_DESC_SEQ_92E(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
-+#define GET_RX_STATUS_DESC_FRAG_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
-+#define GET_RX_STATUS_DESC_RX_IS_QOS_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
-+
-+#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
-+#define GET_RX_STATUS_DESC_HWRSVD_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 24, 4)
-+#define GET_RX_STATUS_DESC_FCS_OK_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
-+#define GET_RX_STATUS_DESC_RPT_SEL_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
-+
-+/* DWORD 3 */
-+#define GET_RX_STATUS_DESC_RX_RATE_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
-+#define GET_RX_STATUS_DESC_HTC_92E(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
-+#define GET_RX_STATUS_DESC_EOSP_92E(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
-+#define GET_RX_STATUS_DESC_BSSID_FIT_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
-+#define GET_RX_STATUS_DESC_DMA_AGG_NUM_92E(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
-+
-+#define GET_RX_STATUS_DESC_PATTERN_MATCH_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
-+#define GET_RX_STATUS_DESC_UNICAST_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
-+#define GET_RX_STATUS_DESC_MAGIC_WAKE_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
-+
-+/* DWORD 6 */
-+#define GET_RX_STATUS_DESC_SPLCP_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
-+#define GET_RX_STATUS_DESC_LDPC_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
-+#define GET_RX_STATUS_DESC_STBC_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
-+#define GET_RX_STATUS_DESC_BW_92E(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
-+
-+
-+/* DWORD 5 */
-+#define GET_RX_STATUS_DESC_TSFL_92E(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
-+
-+#define GET_RX_STATUS_DESC_BUFF_ADDR_92E(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
-+#define GET_RX_STATUS_DESC_BUFF_ADDR64_92E(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
-+
-+
-+#ifdef CONFIG_SDIO_HCI
-+	s32 rtl8192es_init_recv_priv(PADAPTER padapter);
-+	void rtl8192es_free_recv_priv(PADAPTER padapter);
-+	s32 rtl8192es_recv_hdl(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	void rtl8192eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
-+	s32 rtl8192eu_init_recv_priv(PADAPTER padapter);
-+	void rtl8192eu_free_recv_priv(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8192ee_init_recv_priv(PADAPTER padapter);
-+	void rtl8192ee_free_recv_priv(PADAPTER padapter);
-+#endif
-+
-+void rtl8192e_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
-+
-+#endif /* __RTL8192E_RECV_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192e_rf.h b/drivers/staging/rtl8723cs/include/rtl8192e_rf.h
-new file mode 100644
-index 000000000000..77dca747e8fd
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192e_rf.h
-@@ -0,0 +1,28 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2012 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192E_RF_H__
-+#define __RTL8192E_RF_H__
-+
-+void
-+PHY_RF6052SetBandwidth8192E(
-+		PADAPTER				Adapter,
-+		enum channel_width		Bandwidth);
-+
-+
-+int
-+PHY_RF6052_Config_8192E(
-+		PADAPTER	Adapter);
-+
-+#endif/* __RTL8192E_RF_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192e_spec.h b/drivers/staging/rtl8723cs/include/rtl8192e_spec.h
-new file mode 100644
-index 000000000000..c9b2b41e6e48
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192e_spec.h
-@@ -0,0 +1,313 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2012 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192E_SPEC_H__
-+#define __RTL8192E_SPEC_H__
-+
-+#include <drv_conf.h>
-+
-+#define HAL_NAV_UPPER_UNIT_8192E		128		/* micro-second */
-+
-+/* ************************************************************
-+ * 8192E Regsiter offset definition
-+ * ************************************************************ */
-+
-+/* ************************************************************
-+ *
-+ * ************************************************************ */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0000h ~ 0x00FFh	System Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_SYS_SWR_CTRL1_8192E		0x0010	/* 1 Byte        */
-+#define REG_SYS_SWR_CTRL2_8192E		0x0014	/* 1 Byte      */
-+#define REG_AFE_CTRL1_8192E			0x0024
-+#define REG_AFE_CTRL2_8192E			0x0028
-+#define REG_AFE_CTRL3_8192E			0x002c
-+
-+#define REG_PAD_CTRL1_8192E			0x0064
-+#define REG_SDIO_CTRL_8192E			0x0070
-+#define REG_OPT_CTRL_8192E				0x0074
-+#define REG_RF_B_CTRL_8192E			0x0076
-+#define REG_AFE_CTRL4_8192E			0x0078
-+#define REG_LDO_SWR_CTRL				0x007C
-+#define REG_FW_DRV_MSG_8192E			0x0088
-+#define REG_HMEBOX_E2_E3_8192E		0x008C
-+#define REG_HIMR0_8192E				0x00B0
-+#define REG_HISR0_8192E					0x00B4
-+#define REG_HIMR1_8192E					0x00B8
-+#define REG_HISR1_8192E					0x00BC
-+
-+#define REG_SYS_CFG1_8192E				0x00F0
-+#define REG_SYS_CFG2_8192E				0x00FC
-+/* -----------------------------------------------------
-+ *
-+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_PKTBUF_DBG_ADDR			(REG_PKTBUF_DBG_CTRL)
-+#define REG_RXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+2)
-+#define REG_TXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+3)
-+#define REG_WOWLAN_WAKE_REASON		REG_MCUTST_WOWLAN
-+
-+#define REG_RSVD3_8192E					0x0168
-+#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
-+#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
-+#define REG_C2HEVT_CMD_LEN_88XX		0x01AE
-+
-+#define REG_HMEBOX_EXT0_8192E			0x01F0
-+#define REG_HMEBOX_EXT1_8192E			0x01F4
-+#define REG_HMEBOX_EXT2_8192E			0x01F8
-+#define REG_HMEBOX_EXT3_8192E			0x01FC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_DWBCN0_CTRL             0x0208
-+#define REG_DWBCN1_CTRL             0x0228
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_RXDMA_8192E					0x0290
-+#define REG_EARLY_MODE_CONTROL_8192E		0x02BC
-+
-+#define REG_RSVD5_8192E					0x02F0
-+#define REG_RSVD6_8192E					0x02F4
-+#define REG_RSVD7_8192E					0x02F8
-+#define REG_RSVD8_8192E					0x02FC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0300h ~ 0x03FFh	PCIe
-+ *
-+ * ----------------------------------------------------- */
-+#define	REG_PCIE_CTRL_REG_8192E			0x0300
-+#define	REG_INT_MIG_8192E					0x0304	/* Interrupt Migration */
-+#define	REG_BCNQ_TXBD_DESA_8192E		0x0308	/* TX Beacon Descriptor Address */
-+#define	REG_MGQ_TXBD_DESA_8192E			0x0310	/* TX Manage Queue Descriptor Address */
-+#define	REG_VOQ_TXBD_DESA_8192E			0x0318	/* TX VO Queue Descriptor Address */
-+#define	REG_VIQ_TXBD_DESA_8192E			0x0320	/* TX VI Queue Descriptor Address */
-+#define	REG_BEQ_TXBD_DESA_8192E			0x0328	/* TX BE Queue Descriptor Address */
-+#define	REG_BKQ_TXBD_DESA_8192E			0x0330	/* TX BK Queue Descriptor Address */
-+#define	REG_RXQ_RXBD_DESA_8192E			0x0338	/* RX Queue	Descriptor Address */
-+#define	REG_HI0Q_TXBD_DESA_8192E			0x0340
-+#define	REG_HI1Q_TXBD_DESA_8192E			0x0348
-+#define	REG_HI2Q_TXBD_DESA_8192E			0x0350
-+#define	REG_HI3Q_TXBD_DESA_8192E			0x0358
-+#define	REG_HI4Q_TXBD_DESA_8192E			0x0360
-+#define	REG_HI5Q_TXBD_DESA_8192E			0x0368
-+#define	REG_HI6Q_TXBD_DESA_8192E			0x0370
-+#define	REG_HI7Q_TXBD_DESA_8192E			0x0378
-+#define	REG_MGQ_TXBD_NUM_8192E			0x0380
-+#define	REG_RX_RXBD_NUM_8192E			0x0382
-+#define	REG_VOQ_TXBD_NUM_8192E			0x0384
-+#define	REG_VIQ_TXBD_NUM_8192E			0x0386
-+#define	REG_BEQ_TXBD_NUM_8192E			0x0388
-+#define	REG_BKQ_TXBD_NUM_8192E			0x038A
-+#define	REG_HI0Q_TXBD_NUM_8192E			0x038C
-+#define	REG_HI1Q_TXBD_NUM_8192E			0x038E
-+#define	REG_HI2Q_TXBD_NUM_8192E			0x0390
-+#define	REG_HI3Q_TXBD_NUM_8192E			0x0392
-+#define	REG_HI4Q_TXBD_NUM_8192E			0x0394
-+#define	REG_HI5Q_TXBD_NUM_8192E			0x0396
-+#define	REG_HI6Q_TXBD_NUM_8192E			0x0398
-+#define	REG_HI7Q_TXBD_NUM_8192E			0x039A
-+#define	REG_TSFTIMER_HCI_8192E			0x039C
-+
-+/* Read Write Point */
-+#define	REG_VOQ_TXBD_IDX_8192E			0x03A0
-+#define	REG_VIQ_TXBD_IDX_8192E			0x03A4
-+#define	REG_BEQ_TXBD_IDX_8192E			0x03A8
-+#define	REG_BKQ_TXBD_IDX_8192E			0x03AC
-+#define	REG_MGQ_TXBD_IDX_8192E			0x03B0
-+#define	REG_RXQ_TXBD_IDX_8192E			0x03B4
-+#define	REG_HI0Q_TXBD_IDX_8192E			0x03B8
-+#define	REG_HI1Q_TXBD_IDX_8192E			0x03BC
-+#define	REG_HI2Q_TXBD_IDX_8192E			0x03C0
-+#define	REG_HI3Q_TXBD_IDX_8192E			0x03C4
-+#define	REG_HI4Q_TXBD_IDX_8192E			0x03C8
-+#define	REG_HI5Q_TXBD_IDX_8192E			0x03CC
-+#define	REG_HI6Q_TXBD_IDX_8192E			0x03D0
-+#define	REG_HI7Q_TXBD_IDX_8192E			0x03D4
-+
-+#define	REG_PCIE_HCPWM_8192EE			0x03D8 /* ?????? */
-+#define	REG_PCIE_HRPWM_8192EE			0x03DC	/* PCIe RPWM */ /* ?????? */
-+#define	REG_DBI_WDATA_V1_8192E			0x03E8
-+#define	REG_DBI_RDATA_V1_8192E			0x03EC
-+#define	REG_DBI_FLAG_V1_8192E				0x03F0
-+#define	REG_MDIO_V1_8192E					0x3F4
-+#define	REG_PCIE_MIX_CFG_8192E				0x3F8
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0400h ~ 0x047Fh	Protocol Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_TXBF_CTRL_8192E				0x042C
-+#define REG_ARFR0_8192E					0x0444
-+#define REG_ARFR1_8192E					0x044C
-+#define REG_CCK_CHECK_8192E				0x0454
-+#define REG_AMPDU_MAX_TIME_8192E			0x0456
-+#define REG_BCNQ1_BDNY_8192E				0x0457
-+
-+#define REG_AMPDU_MAX_LENGTH_8192E	0x0458
-+#define REG_WMAC_LBK_BUF_HD_8192E			0x045D
-+#define REG_NDPA_OPT_CTRL_8192E		0x045F
-+#define REG_DATA_SC_8192E				0x0483
-+#ifdef CONFIG_WOWLAN
-+	#define REG_TXPKTBUF_IV_LOW             0x0484
-+	#define REG_TXPKTBUF_IV_HIGH            0x0488
-+#endif
-+#define REG_ARFR2_8192E					0x048C
-+#define REG_ARFR3_8192E					0x0494
-+#define REG_TXRPT_START_OFFSET			0x04AC
-+#define REG_AMPDU_BURST_MODE_8192E	0x04BC
-+#define REG_HT_SINGLE_AMPDU_8192E		0x04C7
-+#define REG_MACID_PKT_DROP0_8192E		0x04D0
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0500h ~ 0x05FFh	EDCA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_CTWND_8192E					0x0572
-+#define REG_SECONDARY_CCA_CTRL_8192E	0x0577
-+#define REG_SCH_TXCMD_8192E			0x05F8
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0600h ~ 0x07FFh	WMAC Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_MAC_CR_8192E				0x0600
-+
-+#define REG_MAC_TX_SM_STATE_8192E		0x06B4
-+
-+/* Power */
-+#define REG_BFMER0_INFO_8192E			0x06E4
-+#define REG_BFMER1_INFO_8192E			0x06EC
-+#define REG_CSI_RPT_PARAM_BW20_8192E	0x06F4
-+#define REG_CSI_RPT_PARAM_BW40_8192E	0x06F8
-+#define REG_CSI_RPT_PARAM_BW80_8192E	0x06FC
-+
-+/* Hardware Port 2 */
-+#define REG_BFMEE_SEL_8192E				0x0714
-+#define REG_SND_PTCL_CTRL_8192E		0x0718
-+
-+
-+/* -----------------------------------------------------
-+ *
-+ *	Redifine register definition for compatibility
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* TODO: use these definition when using REG_xxx naming rule.
-+ * NOTE: DO NOT Remove these definition. Use later. */
-+#define	ISR_8192E							REG_HISR0_8192E
-+
-+/* ----------------------------------------------------------------------------
-+ * 8192E IMR/ISR bits						(offset 0xB0,  8bits)
-+ * ---------------------------------------------------------------------------- */
-+#define	IMR_DISABLED_8192E					0
-+/* IMR DW0(0x00B0-00B3) Bit 0-31 */
-+#define	IMR_TIMER2_8192E					BIT(31)		/* Timeout interrupt 2 */
-+#define	IMR_TIMER1_8192E					BIT(30)		/* Timeout interrupt 1	 */
-+#define	IMR_PSTIMEOUT_8192E				BIT(29)		/* Power Save Time Out Interrupt */
-+#define	IMR_GTINT4_8192E					BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
-+#define	IMR_GTINT3_8192E					BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
-+#define	IMR_TXBCN0ERR_8192E				BIT(26)		/* Transmit Beacon0 Error			 */
-+#define	IMR_TXBCN0OK_8192E					BIT(25)		/* Transmit Beacon0 OK			 */
-+#define	IMR_TSF_BIT32_TOGGLE_8192E		BIT(24)		/* TSF Timer BIT(32) toggle indication interrupt			 */
-+#define	IMR_BCNDMAINT0_8192E				BIT(20)		/* Beacon DMA Interrupt 0			 */
-+#define	IMR_BCNDERR0_8192E					BIT(16)		/* Beacon Queue DMA OK0			 */
-+#define	IMR_HSISR_IND_ON_INT_8192E		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
-+#define	IMR_BCNDMAINT_E_8192E				BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
-+#define	IMR_ATIMEND_8192E					BIT(12)		/* CTWidnow End or ATIM Window End */
-+#define	IMR_C2HCMD_8192E					BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
-+#define	IMR_CPWM2_8192E					BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
-+#define	IMR_CPWM_8192E						BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
-+#define	IMR_HIGHDOK_8192E					BIT(7)			/* High Queue DMA OK	 */
-+#define	IMR_MGNTDOK_8192E					BIT(6)			/* Management Queue DMA OK	 */
-+#define	IMR_BKDOK_8192E					BIT(5)			/* AC_BK DMA OK		 */
-+#define	IMR_BEDOK_8192E					BIT(4)			/* AC_BE DMA OK	 */
-+#define	IMR_VIDOK_8192E					BIT(3)			/* AC_VI DMA OK		 */
-+#define	IMR_VODOK_8192E					BIT(2)			/* AC_VO DMA OK	 */
-+#define	IMR_RDU_8192E						BIT(1)			/* Rx Descriptor Unavailable	 */
-+#define	IMR_ROK_8192E						BIT(0)			/* Receive DMA OK */
-+
-+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
-+#define	IMR_BCNDMAINT7_8192E				BIT(27)		/* Beacon DMA Interrupt 7 */
-+#define	IMR_BCNDMAINT6_8192E				BIT(26)		/* Beacon DMA Interrupt 6 */
-+#define	IMR_BCNDMAINT5_8192E				BIT(25)		/* Beacon DMA Interrupt 5 */
-+#define	IMR_BCNDMAINT4_8192E				BIT(24)		/* Beacon DMA Interrupt 4 */
-+#define	IMR_BCNDMAINT3_8192E				BIT(23)		/* Beacon DMA Interrupt 3 */
-+#define	IMR_BCNDMAINT2_8192E				BIT(22)		/* Beacon DMA Interrupt 2 */
-+#define	IMR_BCNDMAINT1_8192E				BIT(21)		/* Beacon DMA Interrupt 1 */
-+#define	IMR_BCNDOK7_8192E					BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
-+#define	IMR_BCNDOK6_8192E					BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
-+#define	IMR_BCNDOK5_8192E					BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
-+#define	IMR_BCNDOK4_8192E					BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
-+#define	IMR_BCNDOK3_8192E					BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
-+#define	IMR_BCNDOK2_8192E					BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
-+#define	IMR_BCNDOK1_8192E					BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
-+#define	IMR_ATIMEND_E_8192E				BIT(13)		/* ATIM Window End Extension for Win7 */
-+#define	IMR_TXERR_8192E					BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
-+#define	IMR_RXERR_8192E					BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
-+#define	IMR_TXFOVW_8192E					BIT(9)			/* Transmit FIFO Overflow */
-+#define	IMR_RXFOVW_8192E					BIT(8)			/* Receive FIFO Overflow */
-+
-+/* ----------------------------------------------------------------------------
-+ * 8192E Auto LLT bits						(offset 0x224,  8bits)
-+ * ----------------------------------------------------------------------------
-+ * 224 REG_AUTO_LLT
-+ * move to hal_com_reg.h */
-+
-+/* ----------------------------------------------------------------------------
-+ * 8192E Auto LLT bits						(offset 0x290,  32bits)
-+ * ---------------------------------------------------------------------------- */
-+#define BIT_DMA_MODE			BIT(1)
-+#define BIT_USB_RXDMA_AGG_EN	BIT(31)
-+
-+/* ----------------------------------------------------------------------------
-+ * 8192E REG_SYS_CFG1						(offset 0xF0,  32bits)
-+ * ---------------------------------------------------------------------------- */
-+#define BIT_SPSLDO_SEL			BIT(24)
-+
-+
-+/* ----------------------------------------------------------------------------
-+ * 8192E REG_CCK_CHECK						(offset 0x454,  8bits)
-+ * ---------------------------------------------------------------------------- */
-+#define BIT_BCN_PORT_SEL		BIT(5)
-+
-+/* ****************************************************************************
-+ * Regsiter Bit and Content definition
-+ * **************************************************************************** */
-+
-+/* 2 ACMHWCTRL 0x05C0 */
-+#define	AcmHw_HwEn_8192E				BIT(0)
-+#define	AcmHw_VoqEn_8192E				BIT(1)
-+#define	AcmHw_ViqEn_8192E				BIT(2)
-+#define	AcmHw_BeqEn_8192E				BIT(3)
-+#define	AcmHw_VoqStatus_8192E			BIT(5)
-+#define	AcmHw_ViqStatus_8192E			BIT(6)
-+#define	AcmHw_BeqStatus_8192E			BIT(7)
-+
-+#endif /* __RTL8192E_SPEC_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192e_sreset.h b/drivers/staging/rtl8723cs/include/rtl8192e_sreset.h
-new file mode 100644
-index 000000000000..78109aea468f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192e_sreset.h
-@@ -0,0 +1,24 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2012 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL88812A_SRESET_H_
-+#define _RTL8812A_SRESET_H_
-+
-+#include <rtw_sreset.h>
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	extern void rtl8192e_sreset_xmit_status_check(_adapter *padapter);
-+	extern void rtl8192e_sreset_linked_status_check(_adapter *padapter);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192e_xmit.h b/drivers/staging/rtl8723cs/include/rtl8192e_xmit.h
-new file mode 100644
-index 000000000000..f84c6faf1922
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192e_xmit.h
-@@ -0,0 +1,457 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2012 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192E_XMIT_H__
-+#define __RTL8192E_XMIT_H__
-+
-+typedef struct txdescriptor_8192e {
-+	/* Offset 0 */
-+	u32 pktlen:16;
-+	u32 offset:8;
-+	u32 bmc:1;
-+	u32 htc:1;
-+	u32 ls:1;
-+	u32 fs:1;
-+	u32 linip:1;
-+	u32 noacm:1;
-+	u32 gf:1;
-+	u32 own:1;
-+
-+	/* Offset 4 */
-+	u32 macid:6;
-+	u32 rsvd0406:2;
-+	u32 qsel:5;
-+	u32 rd_nav_ext:1;
-+	u32 lsig_txop_en:1;
-+	u32 pifs:1;
-+	u32 rate_id:4;
-+	u32 navusehdr:1;
-+	u32 en_desc_id:1;
-+	u32 sectype:2;
-+	u32 rsvd0424:2;
-+	u32 pkt_offset:5;	/* unit: 8 bytes */
-+	u32 rsvd0431:1;
-+
-+	/* Offset 8 */
-+	u32 rts_rc:6;
-+	u32 data_rc:6;
-+	u32 agg_en:1;
-+	u32 rd_en:1;
-+	u32 bar_rty_th:2;
-+	u32 bk:1;
-+	u32 morefrag:1;
-+	u32 raw:1;
-+	u32 ccx:1;
-+	u32 ampdu_density:3;
-+	u32 bt_null:1;
-+	u32 ant_sel_a:1;
-+	u32 ant_sel_b:1;
-+	u32 tx_ant_cck:2;
-+	u32 tx_antl:2;
-+	u32 tx_ant_ht:2;
-+
-+	/* Offset 12 */
-+	u32 nextheadpage:8;
-+	u32 tailpage:8;
-+	u32 seq:12;
-+	u32 cpu_handle:1;
-+	u32 tag1:1;
-+	u32 trigger_int:1;
-+	u32 hwseq_en:1;
-+
-+	/* Offset 16 */
-+	u32 rtsrate:5;
-+	u32 ap_dcfe:1;
-+	u32 hwseq_sel:2;
-+	u32 userate:1;
-+	u32 disrtsfb:1;
-+	u32 disdatafb:1;
-+	u32 cts2self:1;
-+	u32 rtsen:1;
-+	u32 hw_rts_en:1;
-+	u32 port_id:1;
-+	u32 pwr_status:3;
-+	u32 wait_dcts:1;
-+	u32 cts2ap_en:1;
-+	u32 data_sc:2;
-+	u32 data_stbc:2;
-+	u32 data_short:1;
-+	u32 data_bw:1;
-+	u32 rts_short:1;
-+	u32 rts_bw:1;
-+	u32 rts_sc:2;
-+	u32 vcs_stbc:2;
-+
-+	/* Offset 20 */
-+	u32 datarate:6;
-+	u32 sgi:1;
-+	u32 try_rate:1;
-+	u32 data_ratefb_lmt:5;
-+	u32 rts_ratefb_lmt:4;
-+	u32 rty_lmt_en:1;
-+	u32 data_rt_lmt:6;
-+	u32 usb_txagg_num:8;
-+
-+	/* Offset 24 */
-+	u32 txagg_a:5;
-+	u32 txagg_b:5;
-+	u32 use_max_len:1;
-+	u32 max_agg_num:5;
-+	u32 mcsg1_max_len:4;
-+	u32 mcsg2_max_len:4;
-+	u32 mcsg3_max_len:4;
-+	u32 mcs7_sgi_max_len:4;
-+
-+	/* Offset 28 */
-+	u32 checksum:16;	/* TxBuffSize(PCIe)/CheckSum(USB) */
-+	u32 mcsg4_max_len:4;
-+	u32 mcsg5_max_len:4;
-+	u32 mcsg6_max_len:4;
-+	u32 mcs15_sgi_max_len:4;
-+} TXDESC_8192E, *PTXDESC_8192E;
-+
-+
-+
-+/* For 88e early mode */
-+#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
-+#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
-+#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
-+#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
-+#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
-+#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
-+#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
-+
-+/*
-+ * defined for TX DESC Operation
-+ *   */
-+
-+#define MAX_TID (15)
-+
-+/* OFFSET 0 */
-+#define OFFSET_SZ	0
-+#define OFFSET_SHT	16
-+#define BMC		BIT(24)
-+#define LSG		BIT(26)
-+#define FSG		BIT(27)
-+#define OWN		BIT(31)
-+
-+
-+/* OFFSET 4 */
-+#define PKT_OFFSET_SZ		0
-+#define QSEL_SHT			8
-+#define RATE_ID_SHT			16
-+#define NAVUSEHDR			BIT(20)
-+#define SEC_TYPE_SHT		22
-+#define PKT_OFFSET_SHT		26
-+
-+/* OFFSET 8 */
-+#define AGG_EN				BIT(12)
-+#define AGG_BK					BIT(16)
-+#define AMPDU_DENSITY_SHT	20
-+#define ANTSEL_A			BIT(24)
-+#define ANTSEL_B			BIT(25)
-+#define TX_ANT_CCK_SHT		26
-+#define TX_ANTL_SHT			28
-+#define TX_ANT_HT_SHT		30
-+
-+/* OFFSET 12 */
-+#define SEQ_SHT				16
-+#define EN_HWSEQ			BIT(31)
-+
-+/* OFFSET 16 */
-+#define	QOS                          BIT(6)
-+#define	HW_SSN				BIT(7)
-+#define	USERATE			BIT(8)
-+#define	DISDATAFB			BIT(10)
-+#define   CTS_2_SELF			BIT(11)
-+#define	RTS_EN				BIT(12)
-+#define	HW_RTS_EN			BIT(13)
-+#define	DATA_SHORT			BIT(24)
-+#define	PWR_STATUS_SHT	15
-+#define	DATA_SC_SHT		20
-+#define	DATA_BW			BIT(25)
-+
-+/* OFFSET 20 */
-+#define	RTY_LMT_EN			BIT(17)
-+
-+
-+/* OFFSET 20 */
-+#define SGI					BIT(6)
-+#define USB_TXAGG_NUM_SHT	24
-+
-+
-+/* *****Tx Desc Buffer content */
-+
-+/* config element for each tx buffer
-+ *
-+#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 0, 16, __Valeu)
-+#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 31, 1, __Valeu)
-+#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+4, 0, 32, __Valeu)
-+#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)
-+*/
-+#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
-+#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
-+#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
-+#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)
-+
-+
-+/* Dword 0 */
-+#define SET_TX_BUFF_DESC_LEN_0_92E(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
-+#define SET_TX_BUFF_DESC_PSB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
-+#define SET_TX_BUFF_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
-+/* Dword 1 */
-+#define SET_TX_BUFF_DESC_ADDR_LOW_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
-+#define GET_TX_DESC_TX_BUFFER_ADDRESS_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
-+
-+
-+/* Dword 2 */
-+#define SET_TX_BUFF_DESC_ADDR_HIGH_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value)
-+/* Dword 3, RESERVED */
-+
-+
-+/* *****Tx Desc content
-+ * Dword 0 */
-+#define SET_TX_DESC_PKT_SIZE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
-+#define SET_TX_DESC_OFFSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
-+#define SET_TX_DESC_BMC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
-+#define SET_TX_DESC_HTC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
-+#define SET_TX_DESC_LAST_SEG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
-+#define SET_TX_DESC_FIRST_SEG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
-+#define SET_TX_DESC_LINIP_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
-+#define SET_TX_DESC_NO_ACM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
-+#define SET_TX_DESC_GF_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
-+#define SET_TX_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
-+#define GET_TX_DESC_OWN_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
-+
-+/* Dword 1 */
-+#define SET_TX_DESC_MACID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
-+#define SET_TX_DESC_QUEUE_SEL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
-+#define SET_TX_DESC_RDG_NAV_EXT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
-+#define SET_TX_DESC_LSIG_TXOP_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
-+#define SET_TX_DESC_PIFS_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
-+#define SET_TX_DESC_RATE_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
-+#define SET_TX_DESC_EN_DESC_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
-+#define SET_TX_DESC_SEC_TYPE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
-+#define SET_TX_DESC_PKT_OFFSET_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
-+#define SET_TX_DESC_MORE_DATA_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
-+#define SET_TX_DESC_TXOP_PS_CAP_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 30, 1, __Value)
-+#define SET_TX_DESC_TXOP_PS_MODE_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 31, 1, __Value)
-+
-+
-+/* Dword 2 */
-+#define SET_TX_DESC_PAID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
-+#define SET_TX_DESC_CCA_RTS_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
-+#define SET_TX_DESC_AGG_ENABLE_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
-+#define SET_TX_DESC_RDG_ENABLE_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
-+#define SET_TX_DESC_NULL_0_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
-+#define SET_TX_DESC_NULL_1_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
-+#define SET_TX_DESC_BK_92E(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
-+#define SET_TX_DESC_MORE_FRAG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
-+#define SET_TX_DESC_RAW_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
-+#define GET_TX_DESC_MORE_FRAG_92E(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc+8, 17, 1)
-+#define SET_TX_DESC_SPE_RPT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
-+#define SET_TX_DESC_AMPDU_DENSITY_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
-+#define SET_TX_DESC_BT_NULL_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
-+#define SET_TX_DESC_GID_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
-+
-+
-+/* Dword 3 */
-+#define SET_TX_DESC_WHEADER_LEN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
-+#define SET_TX_DESC_CHK_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
-+#define SET_TX_DESC_EARLY_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
-+#define SET_TX_DESC_HWSEQ_SEL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
-+#define SET_TX_DESC_USE_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
-+#define SET_TX_DESC_DISABLE_RTS_FB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
-+#define SET_TX_DESC_DISABLE_FB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
-+#define SET_TX_DESC_CTS2SELF_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
-+#define SET_TX_DESC_RTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
-+#define SET_TX_DESC_HW_RTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
-+#define SET_TX_DESC_HW_PORT_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)
-+#define SET_TX_DESC_NAV_USE_HDR_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
-+#define SET_TX_DESC_USE_MAX_LEN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
-+#define SET_TX_DESC_MAX_AGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
-+#define SET_TX_DESC_NDPA_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
-+#define SET_TX_DESC_AMPDU_MAX_TIME_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
-+
-+/* Dword 4 */
-+#define SET_TX_DESC_TX_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
-+#define SET_TX_DESC_TRY_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
-+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
-+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
-+#define SET_TX_DESC_RETRY_LIMIT_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
-+#define SET_TX_DESC_DATA_RETRY_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
-+#define SET_TX_DESC_RTS_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
-+#define SET_TX_DESC_PCTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
-+#define SET_TX_DESC_PCTS_MASK_IDX_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
-+
-+
-+/* Dword 5 */
-+#define SET_TX_DESC_DATA_SC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
-+#define SET_TX_DESC_DATA_SHORT_92E(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
-+#define SET_TX_DESC_DATA_BW_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
-+#define SET_TX_DESC_DATA_LDPC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
-+#define SET_TX_DESC_DATA_STBC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
-+#define SET_TX_DESC_VCS_STBC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
-+#define SET_TX_DESC_RTS_SHORT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
-+#define SET_TX_DESC_RTS_SC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
-+#define SET_TX_DESC_TX_ANT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value)
-+#define SET_TX_DESC_TX_POWER_0_PSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
-+
-+/* Dword 6 */
-+#define SET_TX_DESC_SW_DEFINE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
-+#define SET_TX_DESC_MBSSID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
-+#define SET_TX_DESC_ANTSEL_A_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
-+#define SET_TX_DESC_ANTSEL_B_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
-+#define SET_TX_DESC_ANTSEL_C_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
-+#define SET_TX_DESC_ANTSEL_D_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
-+
-+/* Dword 7 */
-+#ifdef CONFIG_PCI_HCI
-+	#define SET_TX_DESC_TX_BUFFER_SIZE_92E(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+#endif
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
-+	#define SET_TX_DESC_TX_DESC_CHECKSUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+#endif
-+#define SET_TX_DESC_USB_TXAGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
-+
-+
-+/* #define SET_TX_DESC_HWSEQ_EN_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) */
-+/* Dword 8 */
-+
-+#define SET_TX_DESC_RTS_RC_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
-+#define SET_TX_DESC_BAR_RTY_TH_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
-+#define SET_TX_DESC_DATA_RC_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
-+#define SET_TX_DESC_EN_HWSEQ_92E(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
-+#define SET_TX_DESC_NEXT_HEAD_PAGE_92E(__pTxDesc, __Value)(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
-+#define SET_TX_DESC_TAIL_PAGE_92E(__pTxDesc, __Value)(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
-+
-+/* Dword 9 */
-+#define SET_TX_DESC_PADDING_LENGTH_92E(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
-+#define SET_TX_DESC_TXBF_PATH_92E(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 11, 1, __Value)
-+#define SET_TX_DESC_SEQ_92E(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
-+#define SET_TX_DESC_FINAL_DATA_RATE_92E(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
-+
-+
-+#define SET_EARLYMODE_PKTNUM_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
-+#define SET_EARLYMODE_LEN0_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
-+#define SET_EARLYMODE_LEN1_1_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
-+#define SET_EARLYMODE_LEN1_2_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
-+#define SET_EARLYMODE_LEN2_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,  __Value)
-+#define SET_EARLYMODE_LEN3_92E(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
-+
-+void rtl8192e_cal_txdesc_chksum(u8 *ptxdesc);
-+
-+#ifdef CONFIG_USB_HCI
-+	s32 rtl8192eu_init_xmit_priv(PADAPTER padapter);
-+	void rtl8192eu_free_xmit_priv(PADAPTER padapter);
-+	s32 rtl8192eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8192eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8192eu_hal_mgmt_xmitframe_enqueue(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	rtl8192eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8192eu_xmit_buf_handler(PADAPTER padapter);
-+	#define hal_xmit_handler rtl8192eu_xmit_buf_handler
-+	void rtl8192eu_xmit_tasklet(void *priv);
-+	s32 rtl8192eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8192ee_init_xmit_priv(PADAPTER padapter);
-+	void rtl8192ee_free_xmit_priv(PADAPTER padapter);
-+	struct xmit_buf *rtl8192ee_dequeue_xmitbuf(struct rtw_tx_ring *ring);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8192ee_hal_mgmt_xmitframe_enqueue(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	rtl8192ee_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	void	rtl8192ee_xmitframe_resume(_adapter *padapter);
-+	s32 rtl8192ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8192ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+	void rtl8192ee_xmit_tasklet(void *priv);
-+#endif
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	s32 rtl8192es_init_xmit_priv(PADAPTER padapter);
-+	void rtl8192es_free_xmit_priv(PADAPTER padapter);
-+
-+	s32 rtl8192es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8192es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8192es_hal_mgmt_xmitframe_enqueue(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	rtl8192es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	thread_return rtl8192es_xmit_thread(thread_context context);
-+	s32 rtl8192es_xmit_buf_handler(PADAPTER padapter);
-+
-+	#ifdef CONFIG_SDIO_TX_TASKLET
-+		void rtl8192es_xmit_tasklet(void *priv);
-+	#endif
-+#endif
-+
-+struct txrpt_ccx_92e {
-+	/* offset 0 */
-+	u8 tag1:1;
-+	u8 pkt_num:3;
-+	u8 txdma_underflow:1;
-+	u8 int_bt:1;
-+	u8 int_tri:1;
-+	u8 int_ccx:1;
-+
-+	/* offset 1 */
-+	u8 mac_id:6;
-+	u8 pkt_ok:1;
-+	u8 bmc:1;
-+
-+	/* offset 2 */
-+	u8 retry_cnt:6;
-+	u8 lifetime_over:1;
-+	u8 retry_over:1;
-+
-+	/* offset 3 */
-+	u8 ccx_qtime0;
-+	u8 ccx_qtime1;
-+
-+	/* offset 5 */
-+	u8 final_data_rate;
-+
-+	/* offset 6 */
-+	u8 sw1:4;
-+	u8 qsel:4;
-+
-+	/* offset 7 */
-+	u8 sw0;
-+};
-+
-+#ifdef CONFIG_TX_EARLY_MODE
-+	void UpdateEarlyModeInfo8192E(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+#endif
-+s32	rtl8192e_init_xmit_priv(_adapter *padapter);
-+void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, u8 *ptxdesc);
-+
-+void rtl8192e_fill_fake_txdesc(PADAPTER	padapter, u8 *pDesc, u32 BufferLen,
-+			       u8 IsPsPoll, u8	IsBTQosNull, u8 bDataFrame);
-+void rtl8192e_cal_txdesc_chksum(u8 *ptxdesc);
-+
-+u8	BWMapping_92E(PADAPTER Adapter, struct pkt_attrib *pattrib);
-+u8	SCMapping_92E(PADAPTER Adapter, struct pkt_attrib	*pattrib);
-+void fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void fill_txdesc_vcs(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+
-+void fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void rtl8192e_fixed_rate(_adapter *padapter, u8 *ptxdesc);
-+
-+#endif /* __RTL8192E_XMIT_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192f_cmd.h b/drivers/staging/rtl8723cs/include/rtl8192f_cmd.h
-new file mode 100644
-index 000000000000..44ea6707b79e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192f_cmd.h
-@@ -0,0 +1,213 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192F_CMD_H__
-+#define __RTL8192F_CMD_H__
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+enum h2c_cmd_8192F {
-+	/* Common Class: 000 */
-+	H2C_8192F_RSVD_PAGE = 0x00,
-+	H2C_8192F_MEDIA_STATUS_RPT = 0x01,
-+	H2C_8192F_SCAN_ENABLE = 0x02,
-+	H2C_8192F_KEEP_ALIVE = 0x03,
-+	H2C_8192F_DISCON_DECISION = 0x04,	
-+	H2C_8192F_PSD_OFFLOAD = 0x05,	
-+	H2C_8192F_AP_OFFLOAD = 0x08,	
-+	H2C_8192F_BCN_RSVDPAGE = 0x09,	
-+	H2C_8192F_PROBERSP_RSVDPAGE = 0x0A,	
-+	H2C_8192F_FCS_RSVDPAGE = 0x10,	
-+	H2C_8192F_FCS_INFO = 0x11,	
-+	H2C_8192F_AP_WOW_GPIO_CTRL = 0x13,
-+
-+	/* PoweSave Class: 001 */
-+	H2C_8192F_SET_PWR_MODE = 0x20,
-+	H2C_8192F_PS_TUNING_PARA = 0x21,
-+	H2C_8192F_PS_TUNING_PARA2 = 0x22,
-+	H2C_8192F_P2P_LPS_PARAM = 0x23,	
-+	H2C_8192F_P2P_PS_OFFLOAD = 0x24,	
-+	H2C_8192F_PS_SCAN_ENABLE = 0x25,	
-+	H2C_8192F_SAP_PS_ = 0x26,
-+	H2C_8192F_INACTIVE_PS_ = 0x27,/* Inactive_PS */
-+	H2C_8192F_FWLPS_IN_IPS_ = 0x28,
-+
-+	/* Dynamic Mechanism Class: 010 */
-+	H2C_8192F_MACID_CFG = 0x40,	
-+	H2C_8192F_TXBF = 0x41,	
-+	H2C_8192F_RSSI_SETTING = 0x42,	
-+	H2C_8192F_AP_REQ_TXRPT = 0x43,	
-+	H2C_8192F_INIT_RATE_COLLECT = 0x44,	
-+	H2C_8192F_RA_PARA_ADJUST = 0x46,
-+
-+	/* BT Class: 011 */
-+	H2C_8192F_B_TYPE_TDMA = 0x60,
-+	H2C_8192F_BT_INFO = 0x61,
-+	H2C_8192F_FORCE_BT_TXPWR = 0x62,
-+	H2C_8192F_BT_IGNORE_WLANACT = 0x63,
-+	H2C_8192F_DAC_SWING_VALUE = 0x64,
-+	H2C_8192F_ANT_SEL_RSV = 0x65,
-+	H2C_8192F_WL_OPMODE = 0x66,
-+	H2C_8192F_BT_MP_OPER = 0x67,
-+	H2C_8192F_BT_CONTROL = 0x68,
-+	H2C_8192F_BT_WIFI_CTRL = 0x69,
-+	H2C_8192F_BT_FW_PATCH = 0x6A,
-+	H2C_8192F_BT_WLAN_CALIBRATION = 0x6D,
-+
-+	/* WOWLAN Class: 100 */
-+	H2C_8192F_WOWLAN = 0x80,
-+	H2C_8192F_REMOTE_WAKE_CTRL = 0x81,
-+	H2C_8192F_AOAC_GLOBAL_INFO = 0x82,	
-+	H2C_8192F_AOAC_RSVD_PAGE = 0x83,	
-+	H2C_8192F_AOAC_RSVD_PAGE2 = 0x84,
-+	H2C_8192F_D0_SCAN_OFFLOAD_CTRL = 0x85,
-+	H2C_8192F_D0_SCAN_OFFLOAD_INFO = 0x86,
-+	H2C_8192F_CHNL_SWITCH_OFFLOAD = 0x87,
-+	H2C_8192F_P2P_OFFLOAD_RSVD_PAGE = 0x8A,	
-+	H2C_8192F_P2P_OFFLOAD = 0x8B,
-+
-+	H2C_8192F_RESET_TSF = 0xC0,
-+	H2C_8192F_MAXID,
-+};
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
-+ * ---------------------------------------------------------------------------------------------------------
-+ * _RSVDPAGE_LOC_CMD_0x00 */
-+#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+/*_MEDIA_STATUS_RPT_PARM_CMD_0x01*/
-+#define SET_8192F_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
-+/* _PWR_MOD_CMD_0x20 */
-+#define SET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
-+#define SET_8192F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
-+#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
-+#define SET_8192F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+#define GET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
-+
-+/* _PS_TUNE_PARAM_CMD_0x21 */
-+#define SET_8192F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
-+#define SET_8192F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
-+#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+
-+/* _MACID_CFG_CMD_0x40 */
-+#define SET_8192F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
-+#define SET_8192F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
-+#define SET_8192F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
-+#define SET_8192F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
-+#define SET_8192F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
-+#define SET_8192F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
-+#define SET_8192F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
-+#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
-+
-+/* _RSSI_SETTING_CMD_0x42 */
-+#define SET_8192F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
-+#define SET_8192F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+
-+/* _AP_REQ_TXRPT_CMD_0x43 */
-+#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+
-+/* _FORCE_BT_TXPWR_CMD_0x62 */
-+#define SET_8192F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+
-+/* _FORCE_BT_MP_OPER_CMD_0x67 */
-+#define SET_8192F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
-+#define SET_8192F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
-+#define SET_8192F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
-+
-+/* _BT_FW_PATCH_0x6A */
-+#define SET_8192F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
-+#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * -------------------------------------------    Structure    --------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    Function Statement     --------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+/* host message to firmware cmd */
-+void rtl8192f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
-+void rtl8192f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
-+/* s32 rtl8192f__set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
-+void rtl8192f_set_FwPsTuneParam_cmd(PADAPTER padapter);
-+void rtl8192f_download_rsvd_page(PADAPTER padapter, u8 mstatus);
-+#ifdef CONFIG_BT_COEXIST
-+void rtl8192f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
-+#endif /* CONFIG_BT_COEXIST */
-+#ifdef CONFIG_P2P
-+void rtl8192f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
-+#endif /* CONFIG_P2P */
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+void rtl8192f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
-+#endif
-+
-+/*	AP_REQ_TXREP_CMD 0x43	*/
-+#define SET_8192F_H2CCMD_TXREP_PARM_STA1(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_TXREP_PARM_STA2(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_8192F_H2CCMD_TXREP_PARM_RTY(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)
-+
-+/*		C2H_AP_REQ_TXRPT		*/
-+#define	GET_8192F_C2H_TC2H_APREQ_TXRPT_MACID1(_Header)				LE_BITS_TO_1BYTE((_Header + 0), 0, 8)
-+#define	GET_8192F_C2H_TC2H_APREQ_TXRPT_TXOK1(_Header)				LE_BITS_TO_2BYTE((_Header + 1), 0, 16)
-+#define	GET_8192F_C2H_TC2H_APREQ_TXRPT_TXFAIL1(_Header)				LE_BITS_TO_2BYTE((_Header + 3), 0, 16)
-+#define	GET_8192F_C2H_TC2H_APREQ_TXRPT_INIRATE1(_Header)			LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
-+#define	GET_8192F_C2H_TC2H_APREQ_TXRPT_MACID2(_Header)				LE_BITS_TO_1BYTE((_Header + 6), 0, 8)
-+#define	GET_8192F_C2H_TC2H_APREQ_TXRPT_TXOK2(_Header)				LE_BITS_TO_2BYTE((_Header + 7), 0, 16)
-+#define	GET_8192F_C2H_TC2H_APREQ_TXRPT_TXFAIL2(_Header)				LE_BITS_TO_2BYTE((_Header + 9), 0, 16)
-+#define	GET_8192F_C2H_TC2H_APREQ_TXRPT_INIRATE2(_Header)			LE_BITS_TO_1BYTE((_Header + 11), 0, 8)
-+
-+/*		C2H_SPC_STAT			*/
-+#define	GET_8192F_C2H_SPC_STAT_IDX(_Header)					LE_BITS_TO_1BYTE((_Header + 0), 0, 8)
-+	/*	Tip :TYPE_A data3 is msb and data0 is lsb	*/
-+#define	GET_8192F_C2H_SPC_STAT_TYPEA_RETRY(_Header)				LE_BITS_TO_4BYTE((_Header + 1), 0, 32)
-+#define	GET_8192F_C2H_SPC_STAT_TYPEB_PKT1(_Header)				LE_BITS_TO_2BYTE((_Header + 1), 0, 16)
-+#define	GET_8192F_C2H_SPC_STAT_TYPEB_RETRY1(_Header)				LE_BITS_TO_2BYTE((_Header + 3), 0, 16)
-+#define	GET_8192F_C2H_SPC_STAT_TYPEB_PKT2(_Header)				LE_BITS_TO_2BYTE((_Header + 5), 0, 16)
-+#define	GET_8192F_C2H_SPC_STAT_TYPEB_RETRY2(_Header)				LE_BITS_TO_2BYTE((_Header + 7), 0, 16)
-+
-+void rtl8192f_req_txrpt_cmd(PADAPTER, u8 macid);
-+s32 FillH2CCmd8192F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
-+u8 GetTxBufferRsvdPageNum8192F(_adapter *padapter, bool wowlan);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192f_dm.h b/drivers/staging/rtl8723cs/include/rtl8192f_dm.h
-new file mode 100644
-index 000000000000..43e6396abdf6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192f_dm.h
-@@ -0,0 +1,27 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2012 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192F_DM_H__
-+#define __RTL8192F_DM_H__
-+
-+void rtl8192f_init_dm_priv(PADAPTER Adapter);
-+void rtl8192f_deinit_dm_priv(PADAPTER Adapter);
-+void rtl8192f_InitHalDm(PADAPTER Adapter);
-+void rtl8192f_HalDmWatchDog(PADAPTER Adapter);
-+
-+/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
-+
-+/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192f_hal.h b/drivers/staging/rtl8723cs/include/rtl8192f_hal.h
-new file mode 100644
-index 000000000000..6772f626482b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192f_hal.h
-@@ -0,0 +1,321 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192F_HAL_H__
-+#define __RTL8192F_HAL_H__
-+
-+#include "hal_data.h"
-+
-+#include "rtl8192f_spec.h"
-+#include "rtl8192f_rf.h"
-+#include "rtl8192f_dm.h"
-+#include "rtl8192f_recv.h"
-+#include "rtl8192f_xmit.h"
-+#include "rtl8192f_cmd.h"
-+#include "rtl8192f_led.h"
-+#include "Hal8192FPwrSeq.h"
-+#include "Hal8192FPhyReg.h"
-+#include "Hal8192FPhyCfg.h"
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+#include "rtl8192f_sreset.h"
-+#endif
-+#ifdef CONFIG_LPS_POFF
-+	#include "rtl8192f_lps_poff.h"
-+#endif
-+
-+#define FW_8192F_SIZE		0x8000
-+#define FW_8192F_START_ADDRESS	0x4000
-+#define FW_8192F_END_ADDRESS	0x5000 /* brian_zhang@realsil.com.cn */
-+
-+#define IS_FW_HEADER_EXIST_8192F(_pFwHdr)\
-+	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x92F0)
-+
-+typedef struct _RT_FIRMWARE {
-+	FIRMWARE_SOURCE	eFWSource;
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+	u8			*szFwBuffer;
-+#else
-+	u8			szFwBuffer[FW_8192F_SIZE];
-+#endif
-+	u32			ulFwLength;
-+} RT_FIRMWARE_8192F, *PRT_FIRMWARE_8192F;
-+
-+/*
-+ * This structure must be cared byte-ordering
-+ *
-+ * Added by tynli. 2009.12.04. */
-+typedef struct _RT_8192F_FIRMWARE_HDR {
-+	/* 8-byte alinment required */
-+
-+	/* --- LONG WORD 0 ---- */
-+	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
-+	u8		Category;	/* AP/NIC and USB/PCI */
-+	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
-+	u16		Version;		/* FW Version */
-+	u16		Subversion;	/* FW Subversion, default 0x00 */
-+
-+	/* --- LONG WORD 1 ---- */
-+	u8		Month;	/* Release time Month field */
-+	u8		Date;	/* Release time Date field */
-+	u8		Hour;	/* Release time Hour field */
-+	u8		Minute;	/* Release time Minute field */
-+	u16		RamCodeSize;	/* The size of RAM code */
-+	u16		Rsvd2;
-+
-+	/* --- LONG WORD 2 ---- */
-+	u32		SvnIdx;	/* The SVN entry index */
-+	u32		Rsvd3;
-+
-+	/* --- LONG WORD 3 ---- */
-+	u32		Rsvd4;
-+	u32		Rsvd5;
-+} RT_8192F_FIRMWARE_HDR, *PRT_8192F_FIRMWARE_HDR;
-+#define DRIVER_EARLY_INT_TIME_8192F		0x05
-+#define BCN_DMA_ATIME_INT_TIME_8192F		0x02
-+/* for 8192F
-+ * TX 64K, RX 16K, Page size 256B for TX*/
-+#define PAGE_SIZE_TX_8192F			256
-+#define PAGE_SIZE_RX_8192F			8
-+#define TX_DMA_SIZE_8192F			0x10000/* 64K(TX) */
-+#define RX_DMA_SIZE_8192F			0x4000/* 16K(RX) */
-+#ifdef CONFIG_WOWLAN
-+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
-+#else
-+	#define RESV_FMWF	0
-+#endif
-+
-+#ifdef CONFIG_FW_C2H_DEBUG
-+	#define RX_DMA_RESERVED_SIZE_8192F	0x100	/* 256B, reserved for c2h debug message */
-+#else
-+	#define RX_DMA_RESERVED_SIZE_8192F	0xc0	/* 192B, reserved for tx report 24*8=192*/
-+#endif
-+#define RX_DMA_BOUNDARY_8192F\
-+	(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F - 1)
-+
-+
-+/* Note: We will divide number of page equally for each queue other than public queue! */
-+
-+/* For General Reserved Page Number(Beacon Queue is reserved page)
-+ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8192F
-+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
-+#define BCNQ_PAGE_NUM_8192F		(MAX_BEACON_LEN/PAGE_SIZE_TX_8192F + 6) /*0x08*/
-+
-+
-+/* For WoWLan , more reserved page
-+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
-+ * NS offload: 2 NDP info: 1
-+ */
-+#ifdef CONFIG_WOWLAN
-+	#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+	#define WOWLAN_KEEP_ALIVE_PAGE 0x02 /*for keep alive packet*/
-+	#else
-+	#define WOWLAN_KEEP_ALIVE_PAGE	0x00
-+	#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+	/* 7 pages for wow rsvd page + 2 pages for pattern */
-+	#define WOWLAN_PAGE_NUM_8192F	(0x09 + WOWLAN_KEEP_ALIVE_PAGE)
-+#else
-+	#define WOWLAN_PAGE_NUM_8192F	0x00
-+#endif
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+	#undef WOWLAN_PAGE_NUM_8192F
-+	#define WOWLAN_PAGE_NUM_8192F	0x15
-+#endif
-+
-+#ifdef CONFIG_AP_WOWLAN
-+	#define AP_WOWLAN_PAGE_NUM_8192F	0x02
-+#endif
-+
-+#ifdef DBG_LA_MODE
-+	#define LA_MODE_PAGE_NUM 0xE0
-+#endif
-+
-+#define MAX_RX_DMA_BUFFER_SIZE_8192F	(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F)
-+
-+#ifdef DBG_LA_MODE
-+	#define TX_TOTAL_PAGE_NUMBER_8192F	(0xFF - LA_MODE_PAGE_NUM)
-+#else
-+	#define TX_TOTAL_PAGE_NUMBER_8192F	(0xFF - BCNQ_PAGE_NUM_8192F - WOWLAN_PAGE_NUM_8192F)
-+#endif
-+
-+#define TX_PAGE_BOUNDARY_8192F		(TX_TOTAL_PAGE_NUMBER_8192F + 1)
-+
-+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F \
-+	TX_TOTAL_PAGE_NUMBER_8192F
-+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8192F \
-+	(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F + 1)
-+
-+/* For Normal Chip Setting
-+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192F */
-+#define NORMAL_PAGE_NUM_HPQ_8192F		0x8
-+#define NORMAL_PAGE_NUM_LPQ_8192F		0x8
-+#define NORMAL_PAGE_NUM_NPQ_8192F		0x8
-+#define NORMAL_PAGE_NUM_EPQ_8192F		0x00
-+
-+/* Note: For Normal Chip Setting, modify later */
-+#define WMM_NORMAL_PAGE_NUM_HPQ_8192F		0x30
-+#define WMM_NORMAL_PAGE_NUM_LPQ_8192F		0x20
-+#define WMM_NORMAL_PAGE_NUM_NPQ_8192F		0x20
-+#define WMM_NORMAL_PAGE_NUM_EPQ_8192F		0x00
-+
-+
-+#include "HalVerDef.h"
-+#include "hal_com.h"
-+
-+#define EFUSE_OOB_PROTECT_BYTES 56 /*0x1C8~0x1FF*/
-+
-+#define HAL_EFUSE_MEMORY
-+#define HWSET_MAX_SIZE_8192F                512
-+#define EFUSE_REAL_CONTENT_LEN_8192F        512
-+#define EFUSE_MAP_LEN_8192F                 512
-+#define EFUSE_MAX_SECTION_8192F            64
-+
-+/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
-+#define EFUSE_IC_ID_OFFSET			506
-+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8192F)
-+
-+#define EFUSE_ACCESS_ON		0x69
-+#define EFUSE_ACCESS_OFF	0x00
-+
-+/* ********************************************************
-+ *			EFUSE for BT definition
-+ * ******************************************************** */
-+#define BANK_NUM			1
-+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
-+#define EFUSE_BT_REAL_CONTENT_LEN	1536/*512 * 3 */
-+/*	(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)*/
-+#define EFUSE_BT_MAP_LEN		1024	/* 1k bytes */
-+#define EFUSE_BT_MAX_SECTION		128 /* 1024/8 */
-+#define EFUSE_PROTECT_BYTES_BANK	16
-+
-+typedef enum tag_Package_Definition {
-+	PACKAGE_DEFAULT,
-+	PACKAGE_QFN32,
-+	PACKAGE_QFN40,
-+	PACKAGE_QFN46
-+} PACKAGE_TYPE_E;
-+
-+#define INCLUDE_MULTI_FUNC_BT(_Adapter) \
-+	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
-+#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
-+	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
-+
-+#ifdef CONFIG_FILE_FWIMG
-+	extern char *rtw_fw_file_path;
-+	extern char *rtw_fw_wow_file_path;
-+	#ifdef CONFIG_MP_INCLUDED
-+		extern char *rtw_fw_mp_bt_file_path;
-+	#endif /* CONFIG_MP_INCLUDED */
-+#endif /* CONFIG_FILE_FWIMG */
-+
-+/* rtl8192f_hal_init.c */
-+s32 rtl8192f_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
-+void rtl8192f_FirmwareSelfReset(PADAPTER padapter);
-+void rtl8192f_InitializeFirmwareVars(PADAPTER padapter);
-+
-+void rtl8192f_InitAntenna_Selection(PADAPTER padapter);
-+void rtl8192f_DeinitAntenna_Selection(PADAPTER padapter);
-+void rtl8192f_CheckAntenna_Selection(PADAPTER padapter);
-+void rtl8192f_init_default_value(PADAPTER padapter);
-+
-+s32 rtl8192f_InitLLTTable(PADAPTER padapter);
-+
-+s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
-+s32 CardDisableWithoutHWSM(PADAPTER padapter);
-+
-+/* EFuse */
-+u8 GetEEPROMSize8192F(PADAPTER padapter);
-+void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
-+void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
-+void Hal_EfuseParseTxPowerInfo_8192F(PADAPTER padapter,
-+					u8 *PROMContent, BOOLEAN AutoLoadFail);
-+#ifdef CONFIG_BT_COEXIST
-+void Hal_EfuseParseBTCoexistInfo_8192F(PADAPTER padapter,
-+				       u8 *hwinfo, BOOLEAN AutoLoadFail);
-+#endif /* CONFIG_BT_COEXIST */
-+void Hal_EfuseParseEEPROMVer_8192F(PADAPTER padapter,
-+				   u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseChnlPlan_8192F(PADAPTER padapter,
-+				  u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseCustomerID_8192F(PADAPTER padapter,
-+				    u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseAntennaDiversity_8192F(PADAPTER padapter,
-+		u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseXtal_8192F(PADAPTER pAdapter,
-+			      u8 *hwinfo, u8 AutoLoadFail);
-+void Hal_EfuseParseThermalMeter_8192F(PADAPTER padapter,
-+				      u8 *hwinfo, u8 AutoLoadFail);
-+void Hal_EfuseParseVoltage_8192F(PADAPTER pAdapter,
-+				 u8 *hwinfo, BOOLEAN	AutoLoadFail);
-+void Hal_EfuseParseBoardType_8192F(PADAPTER Adapter,
-+				   u8	*PROMContent, BOOLEAN AutoloadFail);
-+u8	Hal_ReadRFEType_8192F(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+void rtl8192f_set_hal_ops(struct hal_ops *pHalFunc);
-+void init_hal_spec_8192f(_adapter *adapter);
-+u8 SetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val);
-+void GetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val);
-+u8 SetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+u8 GetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+
-+/* register */
-+void rtl8192f_InitBeaconParameters(PADAPTER padapter);
-+void rtl8192f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
-+
-+void _InitMacAPLLSetting_8192F(PADAPTER Adapter);
-+void _8051Reset8192F(PADAPTER padapter);
-+#ifdef CONFIG_WOWLAN
-+	void Hal_DetectWoWMode(PADAPTER pAdapter);
-+#endif /* CONFIG_WOWLAN */
-+
-+void rtl8192f_start_thread(_adapter *padapter);
-+void rtl8192f_stop_thread(_adapter *padapter);
-+
-+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
-+	void rtl8192fs_init_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8192fs_free_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8192fs_cancle_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8192fs_hal_check_bt_hang(_adapter *adapter);
-+#endif
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
-+#endif
-+#ifdef CONFIG_MP_INCLUDED
-+int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
-+#endif
-+void CCX_FwC2HTxRpt_8192f(PADAPTER padapter, u8 *pdata, u8 len);
-+
-+u8 MRateToHwRate8192F(u8 rate);
-+u8 HwRateToMRate8192F(u8 rate);
-+
-+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
-+	void check_bt_status_work(void *data);
-+#endif
-+
-+
-+void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc);
-+
-+#ifdef CONFIG_AMPDU_PRETX_CD
-+void rtl8192f_pretx_cd_config(_adapter *adapter);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	BOOLEAN	InterruptRecognized8192FE(PADAPTER Adapter);
-+	void	UpdateInterruptMask8192FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
-+	void InitMAC_TRXBD_8192FE(PADAPTER Adapter);
-+
-+	u16 get_txbd_rw_reg(u16 ff_hwaddr);
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192f_led.h b/drivers/staging/rtl8723cs/include/rtl8192f_led.h
-new file mode 100644
-index 000000000000..0dbb27cd023e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192f_led.h
-@@ -0,0 +1,59 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192F_LED_H__
-+#define __RTL8192F_LED_H__
-+
-+#include <drv_conf.h>
-+#include <osdep_service.h>
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_RTW_SW_LED
-+/* ********************************************************************************
-+ * Interface to manipulate LED objects.
-+ * ******************************************************************************** */
-+#ifdef CONFIG_USB_HCI
-+/** REG_LED_CFG (0x4C) **/
-+/* LED0 GPIO Enable, 0: disable, 1: enable*/
-+#define LED0_GPIO_ENABLE_8192FU (BIT21)
-+/* LED0 Disabled for analog signal usage, 0:Enable (output mode), 1: disable (input mode) */
-+#define LED0_DISABLE_ANALOGSIGNAL_8192FU (BIT7)
-+/* LED0 software value, 0: turn off, 1:turn on */
-+#define LED0_SW_VALUE_8192FU (BIT3)
-+
-+/** REG_GPIO_MUXCFG (0x40) **/
-+/* Enable LED[1:0] for RFE CTRL[7:6], 0: BT, 1: Wi-Fi */
-+#define ENABLE_LED0_AND_LED1_CTRL_BY_WIFI_8192FU (BIT3)
-+
-+/** REG_SW_GPIO_SHARE_CTRL_0 (0x1038) **/
-+/* LED Output PIN Location, 0: GPIOA_0, 1:GPIOB_4*/
-+#define LED_OUTPUT_PIN_LOCATION_8192FU (BIT16)
-+
-+u8 rtl8192fu_CfgLed0Hw(PADAPTER padapter);
-+void rtl8192fu_InitSwLeds(PADAPTER padapter);
-+void rtl8192fu_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_SDIO_HCI
-+void rtl8192fs_InitSwLeds(PADAPTER padapter);
-+void rtl8192fs_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+void rtl8192fe_InitSwLeds(PADAPTER padapter);
-+void rtl8192fe_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#endif /*#ifdef CONFIG_RTW_SW_LED*/
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192f_recv.h b/drivers/staging/rtl8723cs/include/rtl8192f_recv.h
-new file mode 100644
-index 000000000000..9fb931a7fa69
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192f_recv.h
-@@ -0,0 +1,107 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192F_RECV_H__
-+#define __RTL8192F_RECV_H__
-+
-+#define RECV_BLK_SZ 512
-+#define RECV_BLK_CNT 16
-+#define RECV_BLK_TH RECV_BLK_CNT
-+
-+#if defined(CONFIG_USB_HCI)
-+
-+	#ifndef MAX_RECVBUF_SZ
-+		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
-+			/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
-+			/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
-+			/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
-+			#ifdef CONFIG_PLATFORM_MSTAR
-+				#define MAX_RECVBUF_SZ (8192) /* 8K */
-+			#else
-+				#define MAX_RECVBUF_SZ (32768) /* 32k */
-+			#endif
-+			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
-+		#else
-+			#define MAX_RECVBUF_SZ (4000) /* about 4K */
-+		#endif
-+	#endif /* !MAX_RECVBUF_SZ */
-+
-+#elif defined(CONFIG_PCI_HCI)
-+	#define MAX_RECVBUF_SZ (4000) /* about 4K */
-+
-+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+
-+	#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8192F + 1)
-+
-+#endif
-+
-+/* Rx smooth factor */
-+#define	Rx_Smooth_Factor (20)
-+
-+#ifdef CONFIG_SDIO_HCI
-+	#ifndef CONFIG_SDIO_RX_COPY
-+		#undef MAX_RECVBUF_SZ
-+		#define MAX_RECVBUF_SZ	(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F)
-+	#endif /* !CONFIG_SDIO_RX_COPY */
-+#endif /* CONFIG_SDIO_HCI */
-+
-+/*-----------------------------------------------------------------*/
-+/*	RTL8192F RX BUFFER DESC                                      */
-+/*-----------------------------------------------------------------*/
-+/*DWORD 0*/
-+#define SET_RX_BUFFER_DESC_DATA_LENGTH_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
-+#define SET_RX_BUFFER_DESC_LS_8192F(__pRxStatusDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
-+#define SET_RX_BUFFER_DESC_FS_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
-+#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
-+
-+#define GET_RX_BUFFER_DESC_OWN_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
-+#define GET_RX_BUFFER_DESC_LS_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
-+#define GET_RX_BUFFER_DESC_FS_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
-+#ifdef USING_RX_TAG
-+	#define GET_RX_BUFFER_DESC_RX_TAG_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)
-+#else
-+	#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8192F(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
-+#endif
-+
-+/*DWORD 1*/
-+#define SET_RX_BUFFER_PHYSICAL_LOW_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
-+
-+/*DWORD 2*/
-+#ifdef CONFIG_64BIT_DMA
-+	#define SET_RX_BUFFER_PHYSICAL_HIGH_8192F(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
-+#else
-+	#define SET_RX_BUFFER_PHYSICAL_HIGH_8192F(__pRxStatusDesc, __Value)
-+#endif
-+
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	s32 rtl8192fs_init_recv_priv(PADAPTER padapter);
-+	void rtl8192fs_free_recv_priv(PADAPTER padapter);
-+	s32 rtl8192fs_recv_hdl(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	int rtl8192fu_init_recv_priv(_adapter *padapter);
-+	void rtl8192fu_free_recv_priv(_adapter *padapter);
-+	void rtl8192fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8192fe_init_recv_priv(_adapter *padapter);
-+	void rtl8192fe_free_recv_priv(_adapter *padapter);
-+#endif
-+
-+void rtl8192f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
-+
-+#endif /* __RTL8192F_RECV_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192f_rf.h b/drivers/staging/rtl8723cs/include/rtl8192f_rf.h
-new file mode 100644
-index 000000000000..f9adc7c8a162
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192f_rf.h
-@@ -0,0 +1,91 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2012 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192F_RF_H__
-+#define __RTL8192F_RF_H__
-+
-+/*default*/
-+/*#define CONFIG_8192F_DRV_DIS*/
-+/*AP*/
-+#define CONFIG_8192F_TYPE3_DRV_DIS
-+#define CONFIG_8192F_TYPE4_DRV_DIS
-+/*unused*/
-+#define CONFIG_8192F_TYPE18_DRV_DIS
-+#define CONFIG_8192F_TYPE19_DRV_DIS
-+#define CONFIG_8192F_TYPE20_DRV_DIS
-+#define CONFIG_8192F_TYPE21_DRV_DIS
-+#define CONFIG_8192F_TYPE22_DRV_DIS
-+#define CONFIG_8192F_TYPE23_DRV_DIS
-+#define CONFIG_8192F_TYPE24_DRV_DIS
-+#define CONFIG_8192F_TYPE25_DRV_DIS
-+#define CONFIG_8192F_TYPE26_DRV_DIS
-+#define CONFIG_8192F_TYPE27_DRV_DIS
-+#define CONFIG_8192F_TYPE28_DRV_DIS
-+#define CONFIG_8192F_TYPE29_DRV_DIS
-+#define CONFIG_8192F_TYPE30_DRV_DIS
-+#define CONFIG_8192F_TYPE31_DRV_DIS
-+
-+
-+#ifdef CONFIG_SDIO_HCI /**/
-+/*usb*/
-+#define CONFIG_8192F_TYPE1_DRV_DIS
-+#define CONFIG_8192F_TYPE5_DRV_DIS
-+#define CONFIG_8192F_TYPE10_DRV_DIS
-+#define CONFIG_8192F_TYPE13_DRV_DIS
-+#define CONFIG_8192F_TYPE14_DRV_DIS
-+/*pcie*/
-+#define CONFIG_8192F_TYPE0_DRV_DIS
-+#define CONFIG_8192F_TYPE6_DRV_DIS
-+#define CONFIG_8192F_TYPE7_DRV_DIS
-+#define CONFIG_8192F_TYPE8_DRV_DIS
-+#define CONFIG_8192F_TYPE9_DRV_DIS
-+#define CONFIG_8192F_TYPE12_DRV_DIS
-+#define CONFIG_8192F_TYPE15_DRV_DIS
-+#define CONFIG_8192F_TYPE16_DRV_DIS
-+#define CONFIG_8192F_TYPE17_DRV_DIS
-+#endif/*CONFIG_SDIO_HCI*/
-+
-+#ifdef CONFIG_USB_HCI
-+/*sdio*/
-+#define CONFIG_8192F_TYPE2_DRV_DIS
-+#define CONFIG_8192F_TYPE11_DRV_DIS
-+/*pcie*/
-+#define CONFIG_8192F_TYPE0_DRV_DIS
-+#define CONFIG_8192F_TYPE6_DRV_DIS
-+#define CONFIG_8192F_TYPE7_DRV_DIS
-+#define CONFIG_8192F_TYPE8_DRV_DIS
-+#define CONFIG_8192F_TYPE9_DRV_DIS
-+#define CONFIG_8192F_TYPE12_DRV_DIS
-+#define CONFIG_8192F_TYPE15_DRV_DIS
-+#define CONFIG_8192F_TYPE16_DRV_DIS
-+#define CONFIG_8192F_TYPE17_DRV_DIS
-+#endif/*CONFIG_USB_HCI*/
-+
-+#ifdef CONFIG_PCI_HCI
-+/*sdio*/
-+#define CONFIG_8192F_TYPE2_DRV_DIS
-+#define CONFIG_8192F_TYPE11_DRV_DIS
-+/*usb*/
-+#define CONFIG_8192F_TYPE1_DRV_DIS
-+#define CONFIG_8192F_TYPE5_DRV_DIS
-+#define CONFIG_8192F_TYPE10_DRV_DIS
-+#define CONFIG_8192F_TYPE13_DRV_DIS
-+#define CONFIG_8192F_TYPE14_DRV_DIS
-+#endif/*CONFIG_PCI_HCI*/
-+
-+int PHY_RF6052_Config8192F(PADAPTER pdapter);
-+
-+void PHY_RF6052SetBandwidth8192F(PADAPTER Adapter, enum channel_width Bandwidth);
-+
-+#endif/* __RTL8192F_RF_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192f_spec.h b/drivers/staging/rtl8723cs/include/rtl8192f_spec.h
-new file mode 100644
-index 000000000000..b34d94483c48
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192f_spec.h
-@@ -0,0 +1,541 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192F_SPEC_H__
-+#define __RTL8192F_SPEC_H__
-+
-+#include <drv_conf.h>
-+
-+
-+#define HAL_NAV_UPPER_UNIT_8192F		128		/* micro-second */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0000h ~ 0x00FFh	System Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_SYS_ISO_CTRL_8192F			0x0000	/* 2 Byte */
-+#define REG_SYS_FUNC_EN_8192F			0x0002	/* 2 Byte */
-+#define REG_APS_FSMCO_8192F			0x0004	/* 4 Byte */
-+#define REG_SYS_CLKR_8192F				0x0008	/* 2 Byte */
-+#define REG_9346CR_8192F				0x000A	/* 2 Byte */
-+#define REG_EE_VPD_8192F				0x000C	/* 2 Byte */
-+#define REG_AFE_MISC_8192F				0x0010	/* 1 Byte */
-+#define REG_SPS0_CTRL_8192F				0x0011	/* 7 Byte */
-+#define REG_SPS_OCP_CFG_8192F			0x0018	/* 4 Byte */
-+#define REG_RSV_CTRL_8192F				0x001C	/* 3 Byte */
-+#define REG_RF_CTRL_8192F				0x001F	/* 1 Byte */
-+#define REG_LPLDO_CTRL_8192F			0x0023	/* 1 Byte */
-+#define REG_AFE_XTAL_CTRL_8192F		0x0024	/* 4 Byte */
-+#define REG_AFE_PLL_CTRL_8192F			0x0028	/* 4 Byte */
-+#define REG_MAC_PLL_CTRL_EXT_8192F		0x002c	/* 4 Byte */
-+#define REG_EFUSE_CTRL_8192F			0x0030
-+#define REG_EFUSE_TEST_8192F			0x0034
-+#define REG_PWR_DATA_8192F				0x0038
-+#define REG_CAL_TIMER_8192F				0x003C
-+#define REG_ACLK_MON_8192F				0x003E
-+#define REG_GPIO_MUXCFG_8192F			0x0040
-+#define REG_GPIO_IO_SEL_8192F			0x0042
-+#define REG_MAC_PINMUX_CFG_8192F		0x0043
-+#define REG_GPIO_PIN_CTRL_8192F			0x0044
-+#define REG_GPIO_INTM_8192F				0x0048
-+#define REG_LEDCFG0_8192F				0x004C
-+#define REG_LEDCFG1_8192F				0x004D
-+#define REG_LEDCFG2_8192F				0x004E
-+#define REG_LEDCFG3_8192F				0x004F
-+#define REG_FSIMR_8192F					0x0050
-+#define REG_FSISR_8192F					0x0054
-+#define REG_HSIMR_8192F					0x0058
-+#define REG_HSISR_8192F					0x005c
-+#define REG_GPIO_EXT_CTRL				0x0060
-+#define REG_PAD_CTRL1_8192F		0x0064
-+#define REG_MULTI_FUNC_CTRL_8192F		0x0068
-+#define REG_GPIO_STATUS_8192F			0x006C
-+#define REG_SDIO_CTRL_8192F				0x0070
-+#define REG_OPT_CTRL_8192F				0x0074
-+#define REG_AFE_CTRL_4_8192F		0x0078
-+#define REG_MCUFWDL_8192F				0x0080
-+#define REG_8051FW_CTRL_8192F			0x0080
-+#define REG_HMEBOX_DBG_0_8192F	0x0088
-+#define REG_HMEBOX_DBG_1_8192F	0x008A
-+#define REG_HMEBOX_DBG_2_8192F	0x008C
-+#define REG_HMEBOX_DBG_3_8192F	0x008E
-+#define REG_WLLPS_CTRL		0x0090
-+#define REG_HIMR0_8192F					0x00B0
-+#define REG_HISR0_8192F				0x00B4
-+#define REG_HIMR1_8192F					0x00B8
-+#define REG_HISR1_8192F					0x00BC
-+#define REG_PMC_DBG_CTRL2_8192F			0x00CC
-+#define	REG_EFUSE_BURN_GNT_8192F		0x00CF
-+#define REG_HPON_FSM_8192F				0x00EC
-+#define REG_SYS_CFG1_8192F				0x00F0
-+#define REG_SYS_CFG2_8192F				0x00FC
-+#define REG_ROM_VERSION					0x00FD
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_CR_8192F						0x0100
-+#define REG_PBP_8192F					0x0104
-+#define REG_PKT_BUFF_ACCESS_CTRL_8192F	0x0106
-+#define REG_TRXDMA_CTRL_8192F			0x010C
-+#define REG_TRXFF_BNDY_8192F			0x0114
-+#define REG_TRXFF_STATUS_8192F			0x0118
-+#define REG_RXFF_PTR_8192F				0x011C
-+#define REG_CPWM_8192F					0x012C
-+#define REG_FWIMR_8192F					0x0130
-+#define REG_FWISR_8192F					0x0134
-+#define REG_FTIMR_8192F					0x0138
-+#define REG_PKTBUF_DBG_CTRL_8192F		0x0140
-+#define REG_RXPKTBUF_CTRL_8192F		0x0142
-+#define REG_PKTBUF_DBG_DATA_L_8192F	0x0144
-+#define REG_PKTBUF_DBG_DATA_H_8192F	0x0148
-+
-+#define REG_TC0_CTRL_8192F				0x0150
-+#define REG_TC1_CTRL_8192F				0x0154
-+#define REG_TC2_CTRL_8192F				0x0158
-+#define REG_TC3_CTRL_8192F				0x015C
-+#define REG_TC4_CTRL_8192F				0x0160
-+#define REG_TCUNIT_BASE_8192F			0x0164
-+#define REG_RSVD3_8192F					0x0168
-+#define REG_C2HEVT_CMD_ID_8192F	0x01A0
-+#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
-+#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
-+#define REG_C2HEVT_CMD_LEN_8192F        0x01AE
-+#define REG_C2HEVT_CLEAR_8192F			0x01AF
-+#define REG_TXBUF_WKCAM_OFFSET			0x01B1  /* RTL8192F */
-+#define REG_MCUTST_1_8192F				0x01C0
-+#define REG_WOWLAN_WAKE_REASON 0x01C7
-+#define REG_FMETHR_8192F				0x01C8
-+#define REG_HMETFR_8192F				0x01CC
-+#define REG_HMEBOX_0_8192F				0x01D0
-+#define REG_HMEBOX_1_8192F				0x01D4
-+#define REG_HMEBOX_2_8192F				0x01D8
-+#define REG_HMEBOX_3_8192F				0x01DC
-+#define REG_LLT_INIT_8192F				0x01E0
-+#define REG_HMEBOX_EXT0_8192F			0x01F0
-+#define REG_HMEBOX_EXT1_8192F			0x01F4
-+#define REG_HMEBOX_EXT2_8192F			0x01F8
-+#define REG_HMEBOX_EXT3_8192F			0x01FC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_RQPN_8192F					0x0200
-+#define REG_FIFOPAGE_8192F				0x0204
-+#define REG_DWBCN0_CTRL_8192F			REG_TDECTRL
-+#define REG_TXDMA_OFFSET_CHK_8192F	0x020C
-+#define REG_TXDMA_STATUS_8192F		0x0210
-+#define REG_RQPN_NPQ_8192F			0x0214
-+#define REG_DWBCN1_CTRL_8192F			0x0228
-+#define REG_RQPN_EXQ1_EXQ2			0x0230
-+#define REG_TQPNT3_V1_8192F			0x0234
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_RXDMA_AGG_PG_TH_8192F		0x0280
-+#define REG_FW_UPD_RDPTR_8192F		0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
-+#define REG_RXDMA_CONTROL_8192F		0x0286 /* Control the RX DMA. */
-+#define REG_RXDMA_STATUS_8192F			0x0288
-+#define REG_RXDMA_MODE_CTRL_8192F		0x0290
-+#define REG_EARLY_MODE_CONTROL_8192F	0x02BC
-+#define REG_RSVD5_8192F					0x02F0
-+#define REG_RSVD6_8192F					0x02F4
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0300h ~ 0x03FFh	PCIe
-+ *
-+ * ----------------------------------------------------- */
-+#define	REG_PCIE_CTRL_REG_8192F		0x0300
-+#define	REG_INT_MIG_8192F				0x0304	/* Interrupt Migration */
-+#define	REG_BCNQ_TXBD_DESA_8192F		0x0308	/* TX Beacon Descriptor Address */
-+#define	REG_MGQ_TXBD_DESA_8192F			0x0310	/* TX Manage Queue Descriptor Address */
-+#define	REG_VOQ_TXBD_DESA_8192F			0x0318	/* TX VO Queue Descriptor Address */
-+#define	REG_VIQ_TXBD_DESA_8192F			0x0320	/* TX VI Queue Descriptor Address */
-+#define	REG_BEQ_TXBD_DESA_8192F			0x0328	/* TX BE Queue Descriptor Address */
-+#define	REG_BKQ_TXBD_DESA_8192F			0x0330	/* TX BK Queue Descriptor Address */
-+#define	REG_RXQ_RXBD_DESA_8192F			0x0338	/* RX Queue	Descriptor Address */
-+#define REG_HI0Q_TXBD_DESA_8192F		0x0340
-+#define REG_HI1Q_TXBD_DESA_8192F		0x0348
-+#define REG_HI2Q_TXBD_DESA_8192F		0x0350
-+#define REG_HI3Q_TXBD_DESA_8192F		0x0358
-+#define REG_HI4Q_TXBD_DESA_8192F		0x0360
-+#define REG_HI5Q_TXBD_DESA_8192F		0x0368
-+#define REG_HI6Q_TXBD_DESA_8192F		0x0370
-+#define REG_HI7Q_TXBD_DESA_8192F		0x0378
-+#define	REG_MGQ_TXBD_NUM_8192F			0x0380
-+#define	REG_RX_RXBD_NUM_8192F			0x0382
-+#define	REG_VOQ_TXBD_NUM_8192F			0x0384
-+#define	REG_VIQ_TXBD_NUM_8192F			0x0386
-+#define	REG_BEQ_TXBD_NUM_8192F			0x0388
-+#define	REG_BKQ_TXBD_NUM_8192F			0x038A
-+#define	REG_HI0Q_TXBD_NUM_8192F			0x038C
-+#define	REG_HI1Q_TXBD_NUM_8192F			0x038E
-+#define	REG_HI2Q_TXBD_NUM_8192F			0x0390
-+#define	REG_HI3Q_TXBD_NUM_8192F			0x0392
-+#define	REG_HI4Q_TXBD_NUM_8192F			0x0394
-+#define	REG_HI5Q_TXBD_NUM_8192F			0x0396
-+#define	REG_HI6Q_TXBD_NUM_8192F			0x0398
-+#define	REG_HI7Q_TXBD_NUM_8192F			0x039A
-+#define	REG_TSFTIMER_HCI_8192F			0x039C
-+#define	REG_BD_RW_PTR_CLR_8192F			0x039C
-+
-+/* Read Write Point */
-+#define	REG_VOQ_TXBD_IDX_8192F			0x03A0
-+#define	REG_VIQ_TXBD_IDX_8192F			0x03A4
-+#define	REG_BEQ_TXBD_IDX_8192F			0x03A8
-+#define	REG_BKQ_TXBD_IDX_8192F			0x03AC
-+#define	REG_MGQ_TXBD_IDX_8192F			0x03B0
-+#define	REG_RXQ_TXBD_IDX_8192F			0x03B4
-+#define	REG_HI0Q_TXBD_IDX_8192F			0x03B8
-+#define	REG_HI1Q_TXBD_IDX_8192F			0x03BC
-+#define	REG_HI2Q_TXBD_IDX_8192F			0x03C0
-+#define	REG_HI3Q_TXBD_IDX_8192F			0x03C4
-+#define	REG_HI4Q_TXBD_IDX_8192F			0x03C8
-+#define	REG_HI5Q_TXBD_IDX_8192F			0x03CC
-+#define	REG_HI6Q_TXBD_IDX_8192F			0x03D0
-+#define	REG_HI7Q_TXBD_IDX_8192F			0x03D4
-+#define	REG_DBI_WDATA_V1_8192F			0x03E8
-+#define	REG_DBI_RDATA_V1_8192F			0x03EC
-+#define	REG_DBI_FLAG_V1_8192F			0x03F0
-+#define REG_MDIO_V1_8192F			0x03F4
-+#define REG_HCI_MIX_CFG_8192F			0x03FC
-+#define REG_PCIE_HCPWM_8192FE				0x03D8
-+#define REG_PCIE_HRPWM_8192FE				0x03DC
-+#define REG_PCIE_MIX_CFG_8192F				0x03F8
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0400h ~ 0x047Fh	Protocol Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_QUEUELIST_INFO0_8192F		0x0400
-+#define REG_QUEUELIST_INFO1_8192F		0x0404
-+#define REG_QUEUELIST_INFO2_8192F		0x0414
-+#define REG_TXPKT_EMPTY_8192F			0x0418
-+
-+#define REG_FWHW_TXQ_CTRL_8192F		0x0420
-+#define REG_HWSEQ_CTRL_8192F			0x0423
-+#define REG_TXPKTBUF_BCNQ_BDNY_8192F	0x0424
-+#define REG_TXPKTBUF_MGQ_BDNY_8192F	0x0425
-+#define REG_LIFECTRL_CTRL_8192F			0x0426
-+#define REG_MULTI_BCNQ_OFFSET_8192F	0x0427
-+#define REG_SPEC_SIFS_8192F				0x0428
-+#define REG_RL_8192F						0x042A
-+#define REG_TXBF_CTRL_8192F				0x042C
-+#define REG_DARFRC_8192F				0x0430
-+#define REG_RARFRC_8192F				0x0438
-+#define REG_RRSR_8192F					0x0440
-+#define REG_ARFR0_8192F					0x0444
-+#define REG_ARFR1_8192F					0x044C
-+#define REG_CCK_CHECK_8192F				0x0454
-+#define REG_AMPDU_MAX_TIME_8192F		0x0456
-+#define REG_TXPKTBUF_BCNQ_BDNY1_8192F	0x0457
-+
-+#define REG_AMPDU_MAX_LENGTH_8192F	0x0458
-+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8192F	0x045D
-+#define REG_NDPA_OPT_CTRL_8192F		0x045F
-+#define REG_FAST_EDCA_CTRL_8192F		0x0460
-+#define REG_RD_RESP_PKT_TH_8192F		0x0463
-+#define REG_DATA_SC_8192F				0x0483
-+#define REG_TXRPT_START_OFFSET		0x04AC
-+#define REG_POWER_STAGE1_8192F		0x04B4
-+#define REG_POWER_STAGE2_8192F		0x04B8
-+#define REG_AMPDU_BURST_MODE_8192F	0x04BC
-+#define REG_PKT_VO_VI_LIFE_TIME_8192F	0x04C0
-+#define REG_PKT_BE_BK_LIFE_TIME_8192F	0x04C2
-+#define REG_STBC_SETTING_8192F			0x04C4
-+#define REG_HT_SINGLE_AMPDU_8192F		0x04C7
-+#define REG_PROT_MODE_CTRL_8192F		0x04C8
-+#define REG_MAX_AGGR_NUM_8192F		0x04CA
-+#define REG_RTS_MAX_AGGR_NUM_8192F	0x04CB
-+#define REG_BAR_MODE_CTRL_8192F		0x04CC
-+#define REG_RA_TRY_RATE_AGG_LMT_8192F	0x04CF
-+#define REG_MACID_PKT_DROP0_8192F		0x04D0
-+#define REG_MACID_PKT_SLEEP_8192F		0x04D4
-+#define REG_PRECNT_CTRL_8192F			0x04E5
-+/* -----------------------------------------------------
-+ *
-+ *	0x0500h ~ 0x05FFh	EDCA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_EDCA_VO_PARAM_8192F		0x0500
-+#define REG_EDCA_VI_PARAM_8192F		0x0504
-+#define REG_EDCA_BE_PARAM_8192F		0x0508
-+#define REG_EDCA_BK_PARAM_8192F		0x050C
-+#define REG_BCNTCFG_8192F				0x0510
-+#define REG_PIFS_8192F					0x0512
-+#define REG_RDG_PIFS_8192F				0x0513
-+#define REG_SIFS_CTX_8192F				0x0514
-+#define REG_SIFS_TRX_8192F				0x0516
-+#define REG_AGGR_BREAK_TIME_8192F		0x051A
-+#define REG_SLOT_8192F					0x051B
-+#define REG_TX_PTCL_CTRL_8192F			0x0520
-+#define REG_TXPAUSE_8192F				0x0522
-+#define REG_DIS_TXREQ_CLR_8192F		0x0523
-+#define REG_RD_CTRL_8192F				0x0524
-+/*
-+ * Format for offset 540h-542h:
-+ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
-+ *	[7:4]:   Reserved.
-+ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
-+ *	[23:20]: Reserved
-+ * Description:
-+ *	              |
-+ * |<--Setup--|--Hold------------>|
-+ *	--------------|----------------------
-+ * |
-+ * TBTT
-+ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
-+ * Described by Designer Tim and Bruce, 2011-01-14.
-+ *   */
-+#define REG_TBTT_PROHIBIT_8192F			0x0540
-+#define REG_RD_NAV_NXT_8192F			0x0544
-+#define REG_NAV_PROT_LEN_8192F			0x0546
-+#define REG_BCN_CTRL_8192F				0x0550
-+#define REG_BCN_CTRL_1_8192F			0x0551
-+#define REG_MBID_NUM_8192F				0x0552
-+#define REG_DUAL_TSF_RST_8192F			0x0553
-+#define REG_BCN_INTERVAL_8192F			0x0554
-+#define REG_DRVERLYINT_8192F			0x0558
-+#define REG_BCNDMATIM_8192F			0x0559
-+#define REG_ATIMWND_8192F				0x055A
-+#define REG_USTIME_TSF_8192F			0x055C
-+#define REG_BCN_MAX_ERR_8192F			0x055D
-+#define REG_RXTSF_OFFSET_CCK_8192F		0x055E
-+#define REG_RXTSF_OFFSET_OFDM_8192F	0x055F	
-+#define REG_TSFTR_8192F					0x0560
-+#define REG_CTWND_8192F					0x0572
-+#define REG_SECONDARY_CCA_CTRL_8192F	0x0577
-+#define REG_PSTIMER_8192F				0x0580
-+#define REG_TIMER0_8192F				0x0584
-+#define REG_TIMER1_8192F				0x0588
-+#define REG_ACMHWCTRL_8192F			0x05C0
-+#define REG_SCH_TXCMD_8192F			0x05F8
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0600h ~ 0x07FFh	WMAC Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_MAC_CR_8192F				0x0600
-+#define REG_TCR_8192F					0x0604
-+#define REG_RCR_8192F					0x0608
-+#define REG_RX_PKT_LIMIT_8192F			0x060C
-+#define REG_RX_DLK_TIME_8192F			0x060D
-+#define REG_RX_DRVINFO_SZ_8192F	0x060F
-+
-+#define REG_MACID_8192F					0x0610
-+#define REG_BSSID_8192F					0x0618
-+#define REG_MAR_8192F					0x0620
-+#define REG_MBIDCAMCFG_8192F			0x0628
-+
-+
-+#define REG_USTIME_EDCA_8192F			0x0638
-+#define REG_MAC_SPEC_SIFS_8192F		0x063A
-+#define REG_RESP_SIFP_CCK_8192F			0x063C
-+#define REG_RESP_SIFS_OFDM_8192F		0x063E
-+#define REG_ACKTO_8192F					0x0640
-+#define REG_CTS2TO_8192F				0x0641
-+#define REG_EIFS_8192F					0x0642
-+
-+#define REG_NAV_UPPER_8192F			0x0652	/* unit of 128*/
-+#define REG_TRXPTCL_CTL_8192F			0x0668
-+
-+/* Security*/
-+#define REG_CAMCMD_8192F				0x0670
-+#define REG_CAMWRITE_8192F				0x0674
-+#define REG_CAMREAD_8192F				0x0678
-+#define REG_CAMDBG_8192F				0x067C
-+#define REG_SECCFG_8192F				0x0680
-+
-+/* Power */
-+#define REG_WOW_CTRL_8192F				0x0690
-+#define REG_PS_RX_INFO_8192F			0x0692
-+#define REG_UAPSD_TID_8192F				0x0693
-+#define REG_WKFMCAM_CMD_8192F			0x0698
-+#define REG_WKFMCAM_NUM_8192F			0x0698
-+#define REG_WKFMCAM_RWD_8192F			0x069C
-+#define REG_RXFLTMAP0_8192F				0x06A0
-+#define REG_RXFLTMAP1_8192F				0x06A2
-+#define REG_RXFLTMAP2_8192F				0x06A4
-+#define REG_BCN_PSR_RPT_8192F			0x06A8
-+#define REG_BT_COEX_TABLE_8192F		0x06C0
-+#define REG_BFMER0_INFO_8192F			0x06E4
-+#define REG_BFMER1_INFO_8192F			0x06EC
-+#define REG_CSI_RPT_PARAM_BW20_8192F	0x06F4
-+#define REG_CSI_RPT_PARAM_BW40_8192F	0x06F8
-+#define REG_CSI_RPT_PARAM_BW80_8192F	0x06FC
-+
-+/* Hardware Port 2 */
-+#define REG_MACID1_8192F				0x0700
-+#define REG_BSSID1_8192F				0x0708
-+#define REG_BFMEE_SEL_8192F				0x0714
-+#define REG_SND_PTCL_CTRL_8192F		0x0718
-+
-+/* LTR */
-+#define REG_LTR_CTRL_BASIC_8192F		0x07A4
-+#define REG_LTR_IDLE_LATENCY_V1_8192F		0x0798
-+#define REG_LTR_ACTIVE_LATENCY_V1_8192F	0x079C
-+
-+/* GPIO Control */
-+#define REG_SW_GPIO_SHARE_CTRL_8192F_0	0x1038
-+#define REG_SW_GPIO_SHARE_CTRL_8192F_1	0x103c
-+#define REG_SW_GPIO_A_OUT_8192F			0x1040
-+#define REG_SW_GPIO_A_OEN_8192F			0x1044
-+
-+/* ************************************************************
-+ * SDIO Bus Specification
-+ * ************************************************************ */
-+
-+/* -----------------------------------------------------
-+ * SDIO CMD Address Mapping
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ * I/O bus domain (Host)
-+ * ----------------------------------------------------- */
-+/*SDIO Host Interrupt Mask Register */
-+#define SDIO_HIMR_CRCERR_MSK			BIT(31)
-+/* SDIO Host Interrupt Service Routine */
-+#define SDIO_HISR_HEISR_IND_INT		BIT(28)
-+#define SDIO_HISR_HSISR2_IND_INT		BIT(29)
-+#define SDIO_HISR_HSISR3_IND_INT		BIT(30)
-+#define SDIO_HISR_SDIO_CRCERR			BIT(31)
-+/* -----------------------------------------------------
-+ * SDIO register
-+ * ----------------------------------------------------- */
-+#define SDIO_REG_HCPWM1_8192F	0x038/* HCI Current Power Mode 1 */
-+#define SDIO_REG_FREE_TXPG1_8192F		0x0020 /* Free Tx Buffer Page1*/
-+#define SDIO_REG_FREE_TXPG2_8192F		0x0024 /* Free Tx Buffer Page1*/
-+#define SDIO_REG_FREE_TXPG3_8192F		0x0028
-+#define SDIO_REG_AC_OQT_FREEPG_8192F		0x002A
-+#define SDIO_REG_NOAC_OQT_FREEPG_8192F		0x002B
-+/* ****************************************************************************
-+ *	8192F Regsiter Bit and Content definition
-+ * **************************************************************************** */
-+
-+#define BIT_USB_RXDMA_AGG_EN	BIT(31)
-+#define RXDMA_AGG_MODE_EN		BIT(1)
-+
-+#ifdef CONFIG_WOWLAN
-+	#define RXPKT_RELEASE_POLL		BIT(16)
-+	#define RXDMA_IDLE				BIT(17)
-+	#define RW_RELEASE_EN			BIT(18)
-+#endif
-+
-+#ifdef CONFIG_AMPDU_PRETX_CD
-+/*#define BIT_ERRORHDL_INT			BIT(2)*/
-+/*#define BIT_MACTX_ERR_3			BIT(4)*/
-+#define BIT_PRE_TX_CMD_8192F		BIT(6)
-+#define BIT_EN_PRECNT_8192F		BIT(11)
-+#endif
-+/* SDIO Host Interrupt Service Routine */
-+#define SDIO_HISR_HEISR_IND_INT	BIT(28)
-+#define SDIO_HISR_HSISR2_IND_INT	BIT(29)
-+#define SDIO_HISR_HSISR3_IND_INT	BIT(30)
-+#define SDIO_HISR_SDIO_CRCERR		BIT(31)
-+
-+/* PCIE Host Interrupt Mask Register (HIMR) */
-+#ifdef CONFIG_PCI_HCI
-+/* ----------------------------------------------------------------------------
-+ *   * 8192F IMR/ISR bits							(offset 0xB0,  8bits)
-+ *     * ---------------------------------------------------------------------------- */
-+
-+#define IMR_DISABLED_8192F					0
-+/* IMR DW0(0x00B0-00B3) Bit 0-31 */
-+#define IMR_TIMER2_8192F					BIT(31)         /* Timeout interrupt 2 */
-+#define IMR_TIMER1_8192F					BIT(30)		/* Timeout interrupt 1 */
-+#define IMR_PSTIMEOUT_8192F				BIT(29)		/* Power Save Time Out Interrupt */
-+#define IMR_GTINT4_8192F					BIT(28)		/* When GTIMER4 expires, this bit is set to 1 */
-+#define IMR_GTINT3_8192F					BIT(27)		/* When GTIMER3 expires, this bit is set to 1 */
-+#define IMR_TXBCN0ERR_8192F				BIT(26)		/* Transmit Beacon0 Error */
-+#define IMR_TXBCN0OK_8192F				BIT(25)		/* Transmit Beacon0 OK */
-+#define IMR_TSF_BIT32_TOGGLE_8192F		BIT(24)		/* TSF Timer BIT32 toggle indication interrupt */
-+#define IMR_BCNDMAINT0_8192F				BIT(20)		/* Beacon DMA Interrupt 0 */
-+#define IMR_BCNDERR0_8192F				BIT(16)		/* Beacon Queue DMA OK0 */
-+#define IMR_HSISR_IND_ON_INT_8192F		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
-+#define IMR_BCNDMAINT_E_8192F				BIT(14)		/* Beacon DMA Interrupt Extension for Win7 */
-+#define IMR_ATIMEND_8192F					BIT(12)         /* CTWidnow End or ATIM Window End */
-+#define IMR_C2HCMD_8192F					BIT(10)		/* CPU to Host Command INT status, Write 1 clear */
-+#define IMR_CPWM2_8192F					BIT(9)          /* CPU power mode exchange INT status, Write 1 clear */
-+#define IMR_CPWM_8192F						BIT(8)		/* CPU power mode exchange INT status, Write 1 clear */
-+#define IMR_HIGHDOK_8192F					BIT(7)		/* High Queue DMA OK */
-+#define IMR_MGNTDOK_8192F					BIT(6)		/* Management Queue DMA OK */
-+#define IMR_BKDOK_8192F					BIT(5)		/* AC_BK DMA OK */
-+#define IMR_BEDOK_8192F					BIT(4)		/* AC_BE DMA OK */
-+#define IMR_VIDOK_8192F					BIT(3)		/* AC_VI DMA OK */
-+#define IMR_VODOK_8192F					BIT(2)		/* AC_VO DMA OK */
-+#define IMR_RDU_8192F						BIT(1)		/* Rx Descriptor Unavailable */
-+#define IMR_ROK_8192F						BIT(0)		/* Receive DMA OK */
-+
-+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
-+#define IMR_MCUERR_8192F					BIT(28)
-+#define IMR_BCNDMAINT7_8192F				BIT(27) 		/* Beacon DMA Interrupt 7 */
-+#define IMR_BCNDMAINT6_8192F				BIT(26)		/* Beacon DMA Interrupt 6 */
-+#define IMR_BCNDMAINT5_8192F				BIT(25)		/* Beacon DMA Interrupt 5 */
-+#define IMR_BCNDMAINT4_8192F				BIT(24)		/* Beacon DMA Interrupt 4 */
-+#define IMR_BCNDMAINT3_8192F				BIT(23)		/* Beacon DMA Interrupt 3 */
-+#define IMR_BCNDMAINT2_8192F				BIT(22)		/* Beacon DMA Interrupt 2 */
-+#define IMR_BCNDMAINT1_8192F 				BIT(21)		/* Beacon DMA Interrupt 1 */
-+#define IMR_BCNDOK7_8192F 					BIT(20)		/* Beacon Queue DMA OK Interrup 7 */
-+#define IMR_BCNDOK6_8192F					BIT(19) 		/* Beacon Queue DMA OK Interrup 6 */
-+#define IMR_BCNDOK5_8192F					BIT(18)		/* Beacon Queue DMA OK Interrup 5 */
-+#define IMR_BCNDOK4_8192F					BIT(17)		/* Beacon Queue DMA OK Interrup 4 */
-+#define IMR_BCNDOK3_8192F					BIT(16)		/* Beacon Queue DMA OK Interrup 3 */
-+#define IMR_BCNDOK2_8192F					BIT(15)		/* Beacon Queue DMA OK Interrup 2 */
-+#define IMR_BCNDOK1_8192F					BIT(14)		/* Beacon Queue DMA OK Interrup 1 */
-+#define IMR_ATIMEND_E_8192F				BIT(13)		/* ATIM Window End Extension for Win7 */
-+#define IMR_TXERR_8192F					BIT(11)		/* Tx Error Flag Interrupt status, write 1 clear. */
-+#define IMR_RXERR_8192F					BIT(10)		/* Rx Error Flag INT status, Write 1 clear */
-+#define IMR_TXFOVW_8192F					BIT(9)		/* Transmit FIFO Overflow */
-+#define IMR_RXFOVW_8192F 					BIT(8)		/* Receive FIFO Overflow */
-+
-+/* #define IMR_RX_MASK			(IMR_ROK_8192F|IMR_RDU_8192F|IMR_RXFOVW_8192F) */
-+#define IMR_TX_MASK			(IMR_VODOK_8192F | IMR_VIDOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F | IMR_MGNTDOK_8192F | IMR_HIGHDOK_8192F)
-+#define RT_BCN_INT_MASKS		(IMR_BCNDMAINT0_8192F | IMR_TXBCN0OK_8192F | IMR_TXBCN0ERR_8192F | IMR_BCNDERR0_8192F)
-+#define RT_AC_INT_MASKS		(IMR_VIDOK_8192F | IMR_VODOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F)
-+#endif /* CONFIG_PCI_HCI */
-+
-+/* 2 HSISR
-+ * interrupt mask which needs to clear */
-+#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
-+		HSISR_SPS_OCP_INT |\
-+		HSISR_RON_INT |\
-+		HSISR_PDNINT |\
-+		HSISR_GPIO9_INT)
-+
-+#define _TXDMA_HIQ_MAP_8192F(x)			(((x) & 0x7) << 19)
-+#define _TXDMA_MGQ_MAP_8192F(x)			(((x) & 0x7) << 16)
-+#define _TXDMA_BKQ_MAP_8192F(x)			(((x) & 0x7) << 13)
-+#define _TXDMA_BEQ_MAP_8192F(x)			(((x) & 0x7) << 10)
-+#define _TXDMA_VIQ_MAP_8192F(x)			(((x) & 0x7) << 7)
-+#define _TXDMA_VOQ_MAP_8192F(x)			(((x) & 0x7) << 4)
-+
-+/*mac queue info*/
-+#define QUEUE_TOTAL_NUM	20/*reg414h : 0~f ac queue 0x10~0x13MGQ HIQ BCNQ CMDQ*/
-+#define QUEUE_ACQ_NUM		16 
-+#define QUEUE_INDEX_MGQ		0x10
-+#define QUEUE_INDEX_HIQ		0x11
-+#define QUEUE_INDEX_BCNQ	0x12
-+#define QUEUE_INDEX_CMDQ	0x13
-+#endif /* __RTL8192F_SPEC_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192f_sreset.h b/drivers/staging/rtl8723cs/include/rtl8192f_sreset.h
-new file mode 100644
-index 000000000000..cf881c43184c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192f_sreset.h
-@@ -0,0 +1,24 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8192F_SRESET_H_
-+#define _RTL8192F_SRESET_H_
-+
-+#include <rtw_sreset.h>
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	extern void rtl8192f_sreset_xmit_status_check(_adapter *padapter);
-+	extern void rtl8192f_sreset_linked_status_check(_adapter *padapter);
-+#endif /* DBG_CONFIG_ERROR_DETECT */
-+#endif /* _RTL8192F_SRESET_H_ */
-\ No newline at end of file
-diff --git a/drivers/staging/rtl8723cs/include/rtl8192f_xmit.h b/drivers/staging/rtl8723cs/include/rtl8192f_xmit.h
-new file mode 100644
-index 000000000000..1763f57632fb
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8192f_xmit.h
-@@ -0,0 +1,538 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8192F_XMIT_H__
-+#define __RTL8192F_XMIT_H__
-+
-+
-+#define MAX_TID (15)
-+
-+
-+#ifndef __INC_HAL8192FDESC_H
-+#define __INC_HAL8192FDESC_H
-+
-+#define RX_STATUS_DESC_SIZE_8192F		24
-+#define RX_DRV_INFO_SIZE_UNIT_8192F 	8
-+
-+
-+/* DWORD 0 */
-+#define SET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
-+#define SET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
-+#define SET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
-+
-+#define GET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
-+#define GET_RX_STATUS_DESC_CRC32_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
-+#define GET_RX_STATUS_DESC_ICV_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
-+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
-+#define GET_RX_STATUS_DESC_SECURITY_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
-+#define GET_RX_STATUS_DESC_QOS_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
-+#define GET_RX_STATUS_DESC_SHIFT_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
-+#define GET_RX_STATUS_DESC_PHY_STATUS_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
-+#define GET_RX_STATUS_DESC_SWDEC_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
-+#define GET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
-+#define GET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
-+
-+/* DWORD 1 */
-+#define GET_RX_STATUS_DESC_MACID_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
-+#define GET_RX_STATUS_DESC_TID_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
-+#define GET_RX_STATUS_DESC_AMSDU_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
-+#define GET_RX_STATUS_DESC_RXID_MATCH_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
-+#define GET_RX_STATUS_DESC_PAGGR_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
-+#define GET_RX_STATUS_DESC_A1_FIT_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
-+#define GET_RX_STATUS_DESC_CHKERR_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
-+#define GET_RX_STATUS_DESC_IPVER_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
-+#define GET_RX_STATUS_DESC_IS_TCPUDP__8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
-+#define GET_RX_STATUS_DESC_CHK_VLD_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
-+#define GET_RX_STATUS_DESC_PAM_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
-+#define GET_RX_STATUS_DESC_PWR_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
-+#define GET_RX_STATUS_DESC_MORE_DATA_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
-+#define GET_RX_STATUS_DESC_MORE_FRAG_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
-+#define GET_RX_STATUS_DESC_TYPE_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
-+#define GET_RX_STATUS_DESC_MC_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
-+#define GET_RX_STATUS_DESC_BC_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
-+
-+/* DWORD 2 */
-+#define GET_RX_STATUS_DESC_SEQ_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
-+#define GET_RX_STATUS_DESC_FRAG_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
-+#define GET_RX_STATUS_DESC_RX_IS_QOS_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
-+#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
-+#define GET_RX_STATUS_DESC_RPT_SEL_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
-+#define GET_RX_STATUS_DESC_FCS_OK_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
-+
-+/* DWORD 3 */
-+#define GET_RX_STATUS_DESC_RX_RATE_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
-+#define GET_RX_STATUS_DESC_HTC_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
-+#define GET_RX_STATUS_DESC_EOSP_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
-+#define GET_RX_STATUS_DESC_BSSID_FIT_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
-+#ifdef CONFIG_USB_RX_AGGREGATION
-+#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
-+#endif
-+#define GET_RX_STATUS_DESC_PATTERN_MATCH_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
-+#define GET_RX_STATUS_DESC_UNICAST_MATCH_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
-+#define GET_RX_STATUS_DESC_MAGIC_MATCH_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
-+
-+/* DWORD 6 */
-+#define GET_RX_STATUS_DESC_MATCH_ID_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)
-+
-+/* DWORD 5 */
-+#define GET_RX_STATUS_DESC_TSFL_8192F(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
-+
-+#define GET_RX_STATUS_DESC_BUFF_ADDR64_8192F(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
-+
-+
-+
-+/* Dword 0, rsvd: bit26, bit28 */
-+#define GET_TX_DESC_OWN_8192F(__pTxDesc)\
-+	LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
-+
-+#define SET_TX_DESC_PKT_SIZE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
-+#define SET_TX_DESC_OFFSET_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
-+#define SET_TX_DESC_BMC_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
-+#define SET_TX_DESC_HTC_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
-+#define SET_TX_DESC_AMSDU_PAD_EN_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
-+#define SET_TX_DESC_NO_ACM_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
-+#define SET_TX_DESC_GF_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
-+
-+/* Dword 1 */
-+#define SET_TX_DESC_MACID_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
-+#define SET_TX_DESC_QUEUE_SEL_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
-+#define SET_TX_DESC_RDG_NAV_EXT_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
-+#define SET_TX_DESC_LSIG_TXOP_EN_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
-+#define SET_TX_DESC_PIFS_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
-+#define SET_TX_DESC_RATE_ID_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
-+#define SET_TX_DESC_EN_DESC_ID_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
-+#define SET_TX_DESC_SEC_TYPE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
-+#define SET_TX_DESC_PKT_OFFSET_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
-+#define SET_TX_DESC_MORE_DATA_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
-+
-+/* Dword 2 ADD HW_DIG*/
-+#define SET_TX_DESC_PAID_92F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value)
-+#define SET_TX_DESC_CCA_RTS_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
-+#define SET_TX_DESC_AGG_ENABLE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
-+#define SET_TX_DESC_RDG_ENABLE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
-+#define SET_TX_DESC_NULL0_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
-+#define SET_TX_DESC_NULL1_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
-+#define SET_TX_DESC_BK_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
-+#define SET_TX_DESC_MORE_FRAG_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
-+#define SET_TX_DESC_RAW_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
-+#define SET_TX_DESC_CCX_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
-+#define SET_TX_DESC_AMPDU_DENSITY_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
-+#define SET_TX_DESC_BT_INT_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
-+#define SET_TX_DESC_HW_DIG_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 7, __Value)
-+
-+/* Dword 3 */
-+#define SET_TX_DESC_HWSEQ_SEL_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
-+#define SET_TX_DESC_USE_RATE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
-+#define SET_TX_DESC_DISABLE_RTS_FB_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
-+#define SET_TX_DESC_DISABLE_FB_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
-+#define SET_TX_DESC_CTS2SELF_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
-+#define SET_TX_DESC_RTS_ENABLE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
-+#define SET_TX_DESC_HW_RTS_ENABLE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
-+#define SET_TX_DESC_CHK_EN_92F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)
-+#define SET_TX_DESC_NAV_USE_HDR_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
-+#define SET_TX_DESC_USE_MAX_LEN_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
-+#define SET_TX_DESC_MAX_AGG_NUM_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
-+#define SET_TX_DESC_NDPA_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
-+#define SET_TX_DESC_AMPDU_MAX_TIME_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
-+
-+/* Dword 4 */
-+#define SET_TX_DESC_TX_RATE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
-+#define SET_TX_DESC_TX_TRY_RATE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
-+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
-+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
-+#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
-+#define SET_TX_DESC_DATA_RETRY_LIMIT_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
-+#define SET_TX_DESC_RTS_RATE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
-+#define SET_TX_DESC_PCTS_EN_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
-+#define SET_TX_DESC_PCTS_MASK_IDX_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
-+
-+/* Dword 5 */
-+#define SET_TX_DESC_DATA_SC_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
-+#define SET_TX_DESC_DATA_SHORT_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
-+#define SET_TX_DESC_DATA_BW_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
-+#define SET_TX_DESC_DATA_LDPC_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
-+#define SET_TX_DESC_DATA_STBC_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
-+#define SET_TX_DESC_RTS_STBC_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
-+#define SET_TX_DESC_RTS_SHORT_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
-+#define SET_TX_DESC_RTS_SC_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
-+#define SET_TX_DESC_PORT_ID_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 21, 1, __Value)
-+#define SET_TX_DESC_DROP_ID_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 22, 2, __Value)
-+#define SET_TX_DESC_PATH_A_EN_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)
-+#define SET_TX_DESC_PATH_B_EN_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 25, 1, __Value)
-+#define SET_TX_DESC_TXPWR_OF_SET_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
-+
-+/* Dword 6 */
-+#define SET_TX_DESC_SW_DEFINE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
-+#define SET_TX_DESC_MBSSID_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
-+#define SET_TX_DESC_RF_SEL_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
-+
-+/* Dword 7 */
-+#ifdef CONFIG_PCI_HCI
-+#define SET_TX_DESC_TX_BUFFER_SIZE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+#define SET_TX_DESC_TX_DESC_CHECKSUM_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+#endif
-+
-+#ifdef CONFIG_SDIO_HCI
-+#define SET_TX_DESC_TX_TIMESTAMP_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
-+#endif
-+
-+#define SET_TX_DESC_USB_TXAGG_NUM_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
-+
-+/* Dword 8 */
-+#define SET_TX_DESC_RTS_RC_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
-+#define SET_TX_DESC_BAR_RC_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
-+#define SET_TX_DESC_DATA_RC_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
-+#define SET_TX_DESC_HWSEQ_EN_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
-+#define SET_TX_DESC_NEXTHEADPAGE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
-+#define SET_TX_DESC_TAILPAGE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
-+
-+/* Dword 9 */
-+#define SET_TX_DESC_PADDING_LEN_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
-+#define SET_TX_DESC_SEQ_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
-+#define SET_TX_DESC_FINAL_DATA_RATE_8192F(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
-+
-+
-+#define SET_EARLYMODE_PKTNUM_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
-+#define SET_EARLYMODE_LEN0_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
-+#define SET_EARLYMODE_LEN1_1_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
-+#define SET_EARLYMODE_LEN1_2_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
-+#define SET_EARLYMODE_LEN2_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
-+#define SET_EARLYMODE_LEN3_8192F(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
-+
-+
-+/*-----------------------------------------------------------------*/
-+/*	RTL8192F TX BUFFER DESC                                      */
-+/*-----------------------------------------------------------------*/
-+#ifdef CONFIG_64BIT_DMA
-+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
-+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
-+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
-+	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
-+#else
-+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
-+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
-+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
-+	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu)	/* 64 BIT mode only */
-+#endif
-+/* ********************************************************* */
-+
-+/* 64 bits  -- 32 bits */
-+/* =======     ======= */
-+/* Dword 0     0 */
-+#define SET_TX_BUFF_DESC_LEN_0_8192F(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
-+#define SET_TX_BUFF_DESC_PSB_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
-+#define SET_TX_BUFF_DESC_OWN_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
-+
-+/* Dword 1     1 */
-+#define SET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
-+#define GET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
-+/* Dword 2     NA */
-+#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)
-+#ifdef CONFIG_64BIT_DMA
-+	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
-+#else
-+	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) 0
-+#endif
-+/* Dword 3     NA */
-+/* RESERVED 0 */
-+/* Dword 4     2 */
-+#define SET_TX_BUFF_DESC_LEN_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)
-+#define SET_TX_BUFF_DESC_AMSDU_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)
-+/* Dword 5     3 */
-+#define SET_TX_BUFF_DESC_ADDR_LOW_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)
-+/* Dword 6     NA */
-+#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)
-+/* Dword 7     NA */
-+/*RESERVED 0 */
-+/* Dword 8     4 */
-+#define SET_TX_BUFF_DESC_LEN_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)
-+#define SET_TX_BUFF_DESC_AMSDU_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)
-+/* Dword 9     5 */
-+#define SET_TX_BUFF_DESC_ADDR_LOW_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)
-+/* Dword 10    NA */
-+#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)
-+/* Dword 11    NA */
-+/*RESERVED 0 */
-+/* Dword 12    6 */
-+#define SET_TX_BUFF_DESC_LEN_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)
-+#define SET_TX_BUFF_DESC_AMSDU_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)
-+/* Dword 13    7 */
-+#define SET_TX_BUFF_DESC_ADDR_LOW_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)
-+/* Dword 14    NA */
-+#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)
-+/* Dword 15    NA */
-+/*RESERVED 0 */
-+
-+
-+#endif
-+/* -----------------------------------------------------------
-+ *
-+ *	Rate
-+ *
-+ * -----------------------------------------------------------
-+ * CCK Rates, TxHT = 0 */
-+#define DESC8192F_RATE1M				0x00
-+#define DESC8192F_RATE2M				0x01
-+#define DESC8192F_RATE5_5M				0x02
-+#define DESC8192F_RATE11M				0x03
-+
-+/* OFDM Rates, TxHT = 0 */
-+#define DESC8192F_RATE6M				0x04
-+#define DESC8192F_RATE9M				0x05
-+#define DESC8192F_RATE12M				0x06
-+#define DESC8192F_RATE18M				0x07
-+#define DESC8192F_RATE24M				0x08
-+#define DESC8192F_RATE36M				0x09
-+#define DESC8192F_RATE48M				0x0a
-+#define DESC8192F_RATE54M				0x0b
-+
-+/* MCS Rates, TxHT = 1 */
-+#define DESC8192F_RATEMCS0				0x0c
-+#define DESC8192F_RATEMCS1				0x0d
-+#define DESC8192F_RATEMCS2				0x0e
-+#define DESC8192F_RATEMCS3				0x0f
-+#define DESC8192F_RATEMCS4				0x10
-+#define DESC8192F_RATEMCS5				0x11
-+#define DESC8192F_RATEMCS6				0x12
-+#define DESC8192F_RATEMCS7				0x13
-+#define DESC8192F_RATEMCS8				0x14
-+#define DESC8192F_RATEMCS9				0x15
-+#define DESC8192F_RATEMCS10		0x16
-+#define DESC8192F_RATEMCS11		0x17
-+#define DESC8192F_RATEMCS12		0x18
-+#define DESC8192F_RATEMCS13		0x19
-+#define DESC8192F_RATEMCS14		0x1a
-+#define DESC8192F_RATEMCS15		0x1b
-+#define DESC8192F_RATEVHTSS1MCS0		0x2c
-+#define DESC8192F_RATEVHTSS1MCS1		0x2d
-+#define DESC8192F_RATEVHTSS1MCS2		0x2e
-+#define DESC8192F_RATEVHTSS1MCS3		0x2f
-+#define DESC8192F_RATEVHTSS1MCS4		0x30
-+#define DESC8192F_RATEVHTSS1MCS5		0x31
-+#define DESC8192F_RATEVHTSS1MCS6		0x32
-+#define DESC8192F_RATEVHTSS1MCS7		0x33
-+#define DESC8192F_RATEVHTSS1MCS8		0x34
-+#define DESC8192F_RATEVHTSS1MCS9		0x35
-+#define DESC8192F_RATEVHTSS2MCS0		0x36
-+#define DESC8192F_RATEVHTSS2MCS1		0x37
-+#define DESC8192F_RATEVHTSS2MCS2		0x38
-+#define DESC8192F_RATEVHTSS2MCS3		0x39
-+#define DESC8192F_RATEVHTSS2MCS4		0x3a
-+#define DESC8192F_RATEVHTSS2MCS5		0x3b
-+#define DESC8192F_RATEVHTSS2MCS6		0x3c
-+#define DESC8192F_RATEVHTSS2MCS7		0x3d
-+#define DESC8192F_RATEVHTSS2MCS8		0x3e
-+#define DESC8192F_RATEVHTSS2MCS9		0x3f
-+
-+
-+#define	RX_HAL_IS_CCK_RATE_8192F(pDesc)\
-+	(GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE1M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE2M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE5_5M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE11M)
-+
-+#ifdef CONFIG_TRX_BD_ARCH
-+	struct tx_desc;
-+#endif
-+
-+void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc);
-+void rtl8192f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
-+void rtl8192f_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
-+void rtl8192f_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
-+void rtl8192f_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
-+void rtl8192f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
-+
-+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	s32 rtl8192fs_init_xmit_priv(PADAPTER padapter);
-+	void rtl8192fs_free_xmit_priv(PADAPTER padapter);
-+	s32 rtl8192fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8192fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8192fs_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	rtl8192fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8192fs_xmit_buf_handler(PADAPTER padapter);
-+	thread_return rtl8192fs_xmit_thread(thread_context context);
-+	#define hal_xmit_handler rtl8192fs_xmit_buf_handler
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	s32 rtl8192fu_init_xmit_priv(PADAPTER padapter);
-+	void rtl8192fu_free_xmit_priv(PADAPTER padapter);
-+	s32 rtl8192fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8192fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8192fu_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	 rtl8192fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8192fu_xmit_buf_handler(PADAPTER padapter);
-+	#define hal_xmit_handler rtl8192fu_xmit_buf_handler
-+	void rtl8192fu_xmit_tasklet(void *priv);
-+	s32 rtl8192fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+	void _dbg_dump_tx_info(_adapter	*padapter,int frame_tag,struct tx_desc *ptxdesc);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8192fe_init_xmit_priv(PADAPTER padapter);
-+	void rtl8192fe_free_xmit_priv(PADAPTER padapter);
-+	struct xmit_buf *rtl8192fe_dequeue_xmitbuf(struct rtw_tx_ring *ring);
-+	void    rtl8192fe_xmitframe_resume(_adapter *padapter);
-+	s32 rtl8192fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8192fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8192fe_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32     rtl8192fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	void rtl8192fe_xmit_tasklet(void *priv);
-+#endif
-+
-+u8	BWMapping_8192F(PADAPTER Adapter, struct pkt_attrib *pattrib);
-+u8	SCMapping_8192F(PADAPTER Adapter, struct pkt_attrib	*pattrib);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8703b_cmd.h b/drivers/staging/rtl8723cs/include/rtl8703b_cmd.h
-new file mode 100644
-index 000000000000..522a3bcb7a68
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8703b_cmd.h
-@@ -0,0 +1,199 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8703B_CMD_H__
-+#define __RTL8703B_CMD_H__
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+enum h2c_cmd_8703B {
-+	/* Common Class: 000 */
-+	H2C_8703B_RSVD_PAGE = 0x00,
-+	H2C_8703B_MEDIA_STATUS_RPT = 0x01,
-+	H2C_8703B_SCAN_ENABLE = 0x02,
-+	H2C_8703B_KEEP_ALIVE = 0x03,
-+	H2C_8703B_DISCON_DECISION = 0x04,
-+	H2C_8703B_PSD_OFFLOAD = 0x05,
-+	H2C_8703B_AP_OFFLOAD = 0x08,
-+	H2C_8703B_BCN_RSVDPAGE = 0x09,
-+	H2C_8703B_PROBERSP_RSVDPAGE = 0x0A,
-+	H2C_8703B_FCS_RSVDPAGE = 0x10,
-+	H2C_8703B_FCS_INFO = 0x11,
-+	H2C_8703B_AP_WOW_GPIO_CTRL = 0x13,
-+
-+	/* PoweSave Class: 001 */
-+	H2C_8703B_SET_PWR_MODE = 0x20,
-+	H2C_8703B_PS_TUNING_PARA = 0x21,
-+	H2C_8703B_PS_TUNING_PARA2 = 0x22,
-+	H2C_8703B_P2P_LPS_PARAM = 0x23,
-+	H2C_8703B_P2P_PS_OFFLOAD = 0x24,
-+	H2C_8703B_PS_SCAN_ENABLE = 0x25,
-+	H2C_8703B_SAP_PS_ = 0x26,
-+	H2C_8703B_INACTIVE_PS_ = 0x27, /* Inactive_PS */
-+	H2C_8703B_FWLPS_IN_IPS_ = 0x28,
-+
-+	/* Dynamic Mechanism Class: 010 */
-+	H2C_8703B_MACID_CFG = 0x40,
-+	H2C_8703B_TXBF = 0x41,
-+	H2C_8703B_RSSI_SETTING = 0x42,
-+	H2C_8703B_AP_REQ_TXRPT = 0x43,
-+	H2C_8703B_INIT_RATE_COLLECT = 0x44,
-+	H2C_8703B_RA_PARA_ADJUST = 0x46,
-+
-+	/* BT Class: 011 */
-+	H2C_8703B_B_TYPE_TDMA = 0x60,
-+	H2C_8703B_BT_INFO = 0x61,
-+	H2C_8703B_FORCE_BT_TXPWR = 0x62,
-+	H2C_8703B_BT_IGNORE_WLANACT = 0x63,
-+	H2C_8703B_DAC_SWING_VALUE = 0x64,
-+	H2C_8703B_ANT_SEL_RSV = 0x65,
-+	H2C_8703B_WL_OPMODE = 0x66,
-+	H2C_8703B_BT_MP_OPER = 0x67,
-+	H2C_8703B_BT_CONTROL = 0x68,
-+	H2C_8703B_BT_WIFI_CTRL = 0x69,
-+	H2C_8703B_BT_FW_PATCH = 0x6A,
-+	H2C_8703B_BT_WLAN_CALIBRATION = 0x6D,
-+
-+	/* WOWLAN Class: 100 */
-+	H2C_8703B_WOWLAN = 0x80,
-+	H2C_8703B_REMOTE_WAKE_CTRL = 0x81,
-+	H2C_8703B_AOAC_GLOBAL_INFO = 0x82,
-+	H2C_8703B_AOAC_RSVD_PAGE = 0x83,
-+	H2C_8703B_AOAC_RSVD_PAGE2 = 0x84,
-+	H2C_8703B_D0_SCAN_OFFLOAD_CTRL = 0x85,
-+	H2C_8703B_D0_SCAN_OFFLOAD_INFO = 0x86,
-+	H2C_8703B_CHNL_SWITCH_OFFLOAD = 0x87,
-+	H2C_8703B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
-+	H2C_8703B_P2P_OFFLOAD = 0x8B,
-+
-+	H2C_8703B_RESET_TSF = 0xC0,
-+	H2C_8703B_MAXID,
-+};
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
-+ * ---------------------------------------------------------------------------------------------------------
-+ * _RSVDPAGE_LOC_CMD_0x00 */
-+#define SET_8703B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+/* _KEEP_ALIVE_CMD_0x03 */
-+#define SET_8703B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_8703B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_8703B_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_8703B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+
-+/* _DISCONNECT_DECISION_CMD_0x04 */
-+#define SET_8703B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_8703B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_8703B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
-+
-+/* _PWR_MOD_CMD_0x20 */
-+#define SET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
-+#define SET_8703B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
-+#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
-+#define SET_8703B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+#define GET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
-+
-+/* _PS_TUNE_PARAM_CMD_0x21 */
-+#define SET_8703B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
-+#define SET_8703B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
-+#define SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+
-+/* _MACID_CFG_CMD_0x40 */
-+#define SET_8703B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
-+#define SET_8703B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
-+#define SET_8703B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
-+#define SET_8703B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
-+#define SET_8703B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
-+#define SET_8703B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
-+#define SET_8703B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
-+#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
-+
-+/* _RSSI_SETTING_CMD_0x42 */
-+#define SET_8703B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
-+#define SET_8703B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+
-+/* _AP_REQ_TXRPT_CMD_0x43 */
-+#define SET_8703B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+
-+/* _FORCE_BT_TXPWR_CMD_0x62 */
-+#define SET_8703B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+
-+/* _FORCE_BT_MP_OPER_CMD_0x67 */
-+#define SET_8703B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
-+#define SET_8703B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
-+#define SET_8703B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
-+
-+/* _BT_FW_PATCH_0x6A */
-+#define SET_8703B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
-+#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * -------------------------------------------    Structure    --------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    Function Statement     --------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+/* host message to firmware cmd */
-+void rtl8703b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
-+void rtl8703b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
-+void rtl8703b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
-+/* s32 rtl8703b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
-+void rtl8703b_set_FwPsTuneParam_cmd(PADAPTER padapter);
-+void rtl8703b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
-+void rtl8703b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
-+#ifdef CONFIG_BT_COEXIST
-+	void rtl8703b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
-+#endif /* CONFIG_BT_COEXIST */
-+#ifdef CONFIG_P2P
-+	void rtl8703b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
-+#endif /* CONFIG_P2P */
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+	void rtl8703b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
-+#endif
-+
-+void rtl8703b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
-+
-+s32 FillH2CCmd8703B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
-+u8 GetTxBufferRsvdPageNum8703B(_adapter *padapter, bool wowlan);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8703b_dm.h b/drivers/staging/rtl8723cs/include/rtl8703b_dm.h
-new file mode 100644
-index 000000000000..912c7da079ea
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8703b_dm.h
-@@ -0,0 +1,39 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8703B_DM_H__
-+#define __RTL8703B_DM_H__
-+/* ************************************************************
-+ * Description:
-+ *
-+ * This file is for 8703B dynamic mechanism only
-+ *
-+ *
-+ * ************************************************************ */
-+
-+/* ************************************************************
-+ * structure and define
-+ * ************************************************************ */
-+
-+/* ************************************************************
-+ * function prototype
-+ * ************************************************************ */
-+
-+void rtl8703b_init_dm_priv(PADAPTER padapter);
-+void rtl8703b_deinit_dm_priv(PADAPTER padapter);
-+
-+void rtl8703b_InitHalDm(PADAPTER padapter);
-+void rtl8703b_HalDmWatchDog(PADAPTER padapter);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8703b_hal.h b/drivers/staging/rtl8723cs/include/rtl8703b_hal.h
-new file mode 100644
-index 000000000000..4a83abf458ab
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8703b_hal.h
-@@ -0,0 +1,266 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8703B_HAL_H__
-+#define __RTL8703B_HAL_H__
-+
-+#include "hal_data.h"
-+
-+#include "rtl8703b_spec.h"
-+#include "rtl8703b_rf.h"
-+#include "rtl8703b_dm.h"
-+#include "rtl8703b_recv.h"
-+#include "rtl8703b_xmit.h"
-+#include "rtl8703b_cmd.h"
-+#include "rtl8703b_led.h"
-+#include "Hal8703BPwrSeq.h"
-+#include "Hal8703BPhyReg.h"
-+#include "Hal8703BPhyCfg.h"
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	#include "rtl8703b_sreset.h"
-+#endif
-+
-+#define FW_8703B_SIZE			0x8000
-+#define FW_8703B_START_ADDRESS	0x1000
-+#define FW_8703B_END_ADDRESS		0x1FFF /* 0x5FFF */
-+
-+#define IS_FW_HEADER_EXIST_8703B(_pFwHdr)	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x03B0)
-+
-+typedef struct _RT_FIRMWARE {
-+	FIRMWARE_SOURCE	eFWSource;
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+	u8			*szFwBuffer;
-+#else
-+	u8			szFwBuffer[FW_8703B_SIZE];
-+#endif
-+	u32			ulFwLength;
-+} RT_FIRMWARE_8703B, *PRT_FIRMWARE_8703B;
-+
-+/*
-+ * This structure must be cared byte-ordering
-+ *
-+ * Added by tynli. 2009.12.04. */
-+typedef struct _RT_8703B_FIRMWARE_HDR {
-+	/* 8-byte alinment required */
-+
-+	/* --- LONG WORD 0 ---- */
-+	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
-+	u8		Category;	/* AP/NIC and USB/PCI */
-+	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
-+	u16		Version;		/* FW Version */
-+	u16		Subversion;	/* FW Subversion, default 0x00 */
-+
-+	/* --- LONG WORD 1 ---- */
-+	u8		Month;	/* Release time Month field */
-+	u8		Date;	/* Release time Date field */
-+	u8		Hour;	/* Release time Hour field */
-+	u8		Minute;	/* Release time Minute field */
-+	u16		RamCodeSize;	/* The size of RAM code */
-+	u16		Rsvd2;
-+
-+	/* --- LONG WORD 2 ---- */
-+	u32		SvnIdx;	/* The SVN entry index */
-+	u32		Rsvd3;
-+
-+	/* --- LONG WORD 3 ---- */
-+	u32		Rsvd4;
-+	u32		Rsvd5;
-+} RT_8703B_FIRMWARE_HDR, *PRT_8703B_FIRMWARE_HDR;
-+
-+#define DRIVER_EARLY_INT_TIME_8703B		0x05
-+#define BCN_DMA_ATIME_INT_TIME_8703B		0x02
-+
-+/* for 8703B
-+ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
-+#define PAGE_SIZE_TX_8703B			128
-+#define PAGE_SIZE_RX_8703B			8
-+
-+#define TX_DMA_SIZE_8703B			0x8000	/* 32K(TX) */
-+#define RX_DMA_SIZE_8703B			0x4000	/* 16K(RX) */
-+
-+#ifdef CONFIG_WOWLAN
-+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
-+#else
-+	#define RESV_FMWF	0
-+#endif
-+
-+#ifdef CONFIG_FW_C2H_DEBUG
-+	#define RX_DMA_RESERVED_SIZE_8703B	0x100	/* 256B, reserved for c2h debug message */
-+#else
-+	#define RX_DMA_RESERVED_SIZE_8703B	0x80	/* 128B, reserved for tx report */
-+#endif
-+#define RX_DMA_BOUNDARY_8703B		(RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B - 1)
-+
-+
-+/* Note: We will divide number of page equally for each queue other than public queue! */
-+
-+/* For General Reserved Page Number(Beacon Queue is reserved page)
-+ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8703B
-+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
-+
-+#define BCNQ_PAGE_NUM_8703B		(MAX_BEACON_LEN/PAGE_SIZE_TX_8703B + 6) /*0x08*/
-+
-+/* For WoWLan , more reserved page
-+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1 PNO: 6
-+ * NS offload: 2NDP info: 1
-+ */
-+#ifdef CONFIG_WOWLAN
-+	#define WOWLAN_PAGE_NUM_8703B	0x0b
-+#else
-+	#define WOWLAN_PAGE_NUM_8703B	0x00
-+#endif
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+	#undef WOWLAN_PAGE_NUM_8703B
-+	#define WOWLAN_PAGE_NUM_8703B	0x15
-+#endif
-+
-+#ifdef CONFIG_AP_WOWLAN
-+	#define AP_WOWLAN_PAGE_NUM_8703B	0x02
-+#endif
-+
-+#define TX_TOTAL_PAGE_NUMBER_8703B	(0xFF - BCNQ_PAGE_NUM_8703B - WOWLAN_PAGE_NUM_8703B)
-+#define TX_PAGE_BOUNDARY_8703B		(TX_TOTAL_PAGE_NUMBER_8703B + 1)
-+
-+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B	TX_TOTAL_PAGE_NUMBER_8703B
-+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8703B		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B + 1)
-+
-+/* For Normal Chip Setting
-+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8703B */
-+#define NORMAL_PAGE_NUM_HPQ_8703B		0x0C
-+#define NORMAL_PAGE_NUM_LPQ_8703B		0x02
-+#define NORMAL_PAGE_NUM_NPQ_8703B		0x02
-+
-+/* Note: For Normal Chip Setting, modify later */
-+#define WMM_NORMAL_PAGE_NUM_HPQ_8703B		0x30
-+#define WMM_NORMAL_PAGE_NUM_LPQ_8703B		0x20
-+#define WMM_NORMAL_PAGE_NUM_NPQ_8703B		0x20
-+
-+
-+#include "HalVerDef.h"
-+#include "hal_com.h"
-+
-+#define EFUSE_OOB_PROTECT_BYTES		15
-+
-+#define HAL_EFUSE_MEMORY
-+
-+#define HWSET_MAX_SIZE_8703B			256
-+#define EFUSE_REAL_CONTENT_LEN_8703B		256
-+#define EFUSE_MAP_LEN_8703B				512
-+#define EFUSE_MAX_SECTION_8703B			64
-+
-+#define EFUSE_IC_ID_OFFSET			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
-+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8703B)
-+
-+#define EFUSE_ACCESS_ON			0x69
-+#define EFUSE_ACCESS_OFF			0x00
-+
-+/* ********************************************************
-+ *			EFUSE for BT definition
-+ * ******************************************************** */
-+#define BANK_NUM		1
-+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	128
-+#define EFUSE_BT_REAL_CONTENT_LEN		(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
-+#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
-+#define EFUSE_BT_MAX_SECTION			(EFUSE_BT_MAP_LEN / 8)
-+#define EFUSE_PROTECT_BYTES_BANK		16
-+
-+typedef enum tag_Package_Definition {
-+	PACKAGE_DEFAULT,
-+	PACKAGE_QFN68,
-+	PACKAGE_TFBGA90,
-+	PACKAGE_TFBGA80,
-+	PACKAGE_TFBGA79
-+} PACKAGE_TYPE_E;
-+
-+#define INCLUDE_MULTI_FUNC_BT(_Adapter)		(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
-+#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
-+
-+/* rtl8703b_hal_init.c */
-+s32 rtl8703b_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
-+void rtl8703b_FirmwareSelfReset(PADAPTER padapter);
-+void rtl8703b_InitializeFirmwareVars(PADAPTER padapter);
-+
-+void rtl8703b_InitAntenna_Selection(PADAPTER padapter);
-+void rtl8703b_DeinitAntenna_Selection(PADAPTER padapter);
-+void rtl8703b_CheckAntenna_Selection(PADAPTER padapter);
-+void rtl8703b_init_default_value(PADAPTER padapter);
-+
-+s32 rtl8703b_InitLLTTable(PADAPTER padapter);
-+
-+s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
-+s32 CardDisableWithoutHWSM(PADAPTER padapter);
-+
-+/* EFuse */
-+u8 GetEEPROMSize8703B(PADAPTER padapter);
-+void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
-+void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
-+void Hal_EfuseParseTxPowerInfo_8703B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseBTCoexistInfo_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseEEPROMVer_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseChnlPlan_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseCustomerID_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseAntennaDiversity_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseXtal_8703B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
-+void Hal_EfuseParseThermalMeter_8703B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
-+void Hal_EfuseParseVoltage_8703B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
-+void Hal_EfuseParseBoardType_8703B(PADAPTER Adapter,	u8	*PROMContent, BOOLEAN AutoloadFail);
-+
-+void rtl8703b_set_hal_ops(struct hal_ops *pHalFunc);
-+void init_hal_spec_8703b(_adapter *adapter);
-+u8 SetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val);
-+void GetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val);
-+u8 SetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+u8 GetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+
-+/* register */
-+void rtl8703b_InitBeaconParameters(PADAPTER padapter);
-+void rtl8703b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
-+void	_InitBurstPktLen_8703BS(PADAPTER Adapter);
-+void _InitLTECoex_8703BS(PADAPTER Adapter);
-+void _InitMacAPLLSetting_8703B(PADAPTER Adapter);
-+void _8051Reset8703(PADAPTER padapter);
-+#ifdef CONFIG_WOWLAN
-+	void Hal_DetectWoWMode(PADAPTER pAdapter);
-+#endif /* CONFIG_WOWLAN */
-+
-+void rtl8703b_start_thread(_adapter *padapter);
-+void rtl8703b_stop_thread(_adapter *padapter);
-+
-+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
-+	void rtl8703bs_init_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8703bs_free_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8703bs_cancle_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8703bs_hal_check_bt_hang(_adapter *adapter);
-+#endif
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
-+#endif
-+#ifdef CONFIG_MP_INCLUDED
-+int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
-+#endif
-+void CCX_FwC2HTxRpt_8703b(PADAPTER padapter, u8 *pdata, u8 len);
-+
-+u8 MRateToHwRate8703B(u8  rate);
-+u8 HwRateToMRate8703B(u8	 rate);
-+
-+void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+
-+#ifdef CONFIG_PCI_HCI
-+	BOOLEAN	InterruptRecognized8703BE(PADAPTER Adapter);
-+	void	UpdateInterruptMask8703BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8703b_led.h b/drivers/staging/rtl8723cs/include/rtl8703b_led.h
-new file mode 100644
-index 000000000000..99e590d31bc5
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8703b_led.h
-@@ -0,0 +1,44 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8703B_LED_H__
-+#define __RTL8703B_LED_H__
-+
-+#include <drv_conf.h>
-+#include <osdep_service.h>
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_RTW_SW_LED
-+/* ********************************************************************************
-+ * Interface to manipulate LED objects.
-+ * ******************************************************************************** */
-+#ifdef CONFIG_USB_HCI
-+	void rtl8703bu_InitSwLeds(PADAPTER padapter);
-+	void rtl8703bu_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_SDIO_HCI
-+	void rtl8703bs_InitSwLeds(PADAPTER padapter);
-+	void rtl8703bs_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_GSPI_HCI
-+	void rtl8703bs_InitSwLeds(PADAPTER padapter);
-+	void rtl8703bs_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+	void rtl8703be_InitSwLeds(PADAPTER padapter);
-+	void rtl8703be_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+
-+#endif/*CONFIG_RTW_SW_LED*/
-+#endif /*__RTL8703B_LED_H__*/
-diff --git a/drivers/staging/rtl8723cs/include/rtl8703b_recv.h b/drivers/staging/rtl8723cs/include/rtl8703b_recv.h
-new file mode 100644
-index 000000000000..92bc452b813d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8703b_recv.h
-@@ -0,0 +1,83 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8703B_RECV_H__
-+#define __RTL8703B_RECV_H__
-+
-+#define RECV_BLK_SZ 512
-+#define RECV_BLK_CNT 16
-+#define RECV_BLK_TH RECV_BLK_CNT
-+
-+#if defined(CONFIG_USB_HCI)
-+
-+	#ifndef MAX_RECVBUF_SZ
-+		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
-+			/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
-+			/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
-+			/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
-+			#ifdef CONFIG_PLATFORM_MSTAR
-+				#define MAX_RECVBUF_SZ (8192) /* 8K */
-+			#else
-+				#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
-+			#endif
-+			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
-+		#else
-+			#define MAX_RECVBUF_SZ (4000) /* about 4K */
-+		#endif
-+	#endif /* !MAX_RECVBUF_SZ */
-+
-+#elif defined(CONFIG_PCI_HCI)
-+	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
-+	/*	#define MAX_RECVBUF_SZ (9100) */
-+	/* #else */
-+	#define MAX_RECVBUF_SZ (4000) /* about 4K
-+	* #endif */
-+
-+
-+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+
-+	#define MAX_RECVBUF_SZ (RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B)
-+
-+#endif
-+
-+/* Rx smooth factor */
-+#define	Rx_Smooth_Factor (20)
-+
-+#ifdef CONFIG_SDIO_HCI
-+	#ifndef CONFIG_SDIO_RX_COPY
-+		#undef MAX_RECVBUF_SZ
-+		#define MAX_RECVBUF_SZ	(RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B)
-+	#endif /* !CONFIG_SDIO_RX_COPY */
-+#endif /* CONFIG_SDIO_HCI */
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	s32 rtl8703bs_init_recv_priv(PADAPTER padapter);
-+	void rtl8703bs_free_recv_priv(PADAPTER padapter);
-+	s32 rtl8703bs_recv_hdl(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	int rtl8703bu_init_recv_priv(_adapter *padapter);
-+	void rtl8703bu_free_recv_priv(_adapter *padapter);
-+	void rtl8703bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8703be_init_recv_priv(PADAPTER padapter);
-+	void rtl8703be_free_recv_priv(PADAPTER padapter);
-+#endif
-+
-+void rtl8703b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
-+
-+#endif /* __RTL8703B_RECV_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8703b_rf.h b/drivers/staging/rtl8723cs/include/rtl8703b_rf.h
-new file mode 100644
-index 000000000000..4148276bf4cb
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8703b_rf.h
-@@ -0,0 +1,25 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8703B_RF_H__
-+#define __RTL8703B_RF_H__
-+
-+int	PHY_RF6052_Config8703B(PADAPTER		Adapter);
-+
-+void
-+PHY_RF6052SetBandwidth8703B(
-+		PADAPTER				Adapter,
-+		enum channel_width		Bandwidth);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8703b_spec.h b/drivers/staging/rtl8723cs/include/rtl8703b_spec.h
-new file mode 100644
-index 000000000000..633b23b1bf10
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8703b_spec.h
-@@ -0,0 +1,464 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8703B_SPEC_H__
-+#define __RTL8703B_SPEC_H__
-+
-+#include <drv_conf.h>
-+
-+
-+#define HAL_NAV_UPPER_UNIT_8703B		128		/* micro-second */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0000h ~ 0x00FFh	System Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_SYS_ISO_CTRL_8703B			0x0000	/* 2 Byte */
-+#define REG_SYS_FUNC_EN_8703B			0x0002	/* 2 Byte */
-+#define REG_APS_FSMCO_8703B			0x0004	/* 4 Byte */
-+#define REG_SYS_CLKR_8703B				0x0008	/* 2 Byte */
-+#define REG_9346CR_8703B				0x000A	/* 2 Byte */
-+#define REG_EE_VPD_8703B				0x000C	/* 2 Byte */
-+#define REG_AFE_MISC_8703B				0x0010	/* 1 Byte */
-+#define REG_SPS0_CTRL_8703B				0x0011	/* 7 Byte */
-+#define REG_SPS_OCP_CFG_8703B			0x0018	/* 4 Byte */
-+#define REG_RSV_CTRL_8703B				0x001C	/* 3 Byte */
-+#define REG_RF_CTRL_8703B				0x001F	/* 1 Byte */
-+#define REG_LPLDO_CTRL_8703B			0x0023	/* 1 Byte */
-+#define REG_AFE_XTAL_CTRL_8703B		0x0024	/* 4 Byte */
-+#define REG_AFE_PLL_CTRL_8703B			0x0028	/* 4 Byte */
-+#define REG_MAC_PLL_CTRL_EXT_8703B		0x002c	/* 4 Byte */
-+#define REG_EFUSE_CTRL_8703B			0x0030
-+#define REG_EFUSE_TEST_8703B			0x0034
-+#define REG_PWR_DATA_8703B				0x0038
-+#define REG_CAL_TIMER_8703B				0x003C
-+#define REG_ACLK_MON_8703B				0x003E
-+#define REG_GPIO_MUXCFG_8703B			0x0040
-+#define REG_GPIO_IO_SEL_8703B			0x0042
-+#define REG_MAC_PINMUX_CFG_8703B		0x0043
-+#define REG_GPIO_PIN_CTRL_8703B			0x0044
-+#define REG_GPIO_INTM_8703B				0x0048
-+#define REG_LEDCFG0_8703B				0x004C
-+#define REG_LEDCFG1_8703B				0x004D
-+#define REG_LEDCFG2_8703B				0x004E
-+#define REG_LEDCFG3_8703B				0x004F
-+#define REG_FSIMR_8703B					0x0050
-+#define REG_FSISR_8703B					0x0054
-+#define REG_HSIMR_8703B					0x0058
-+#define REG_HSISR_8703B					0x005c
-+#define REG_GPIO_EXT_CTRL				0x0060
-+#define REG_PAD_CTRL1_8703B		0x0064
-+#define REG_MULTI_FUNC_CTRL_8703B		0x0068
-+#define REG_GPIO_STATUS_8703B			0x006C
-+#define REG_SDIO_CTRL_8703B				0x0070
-+#define REG_OPT_CTRL_8703B				0x0074
-+#define REG_AFE_CTRL_4_8703B		0x0078
-+#define REG_MCUFWDL_8703B				0x0080
-+#define REG_HMEBOX_DBG_0_8703B	0x0088
-+#define REG_HMEBOX_DBG_1_8703B	0x008A
-+#define REG_HMEBOX_DBG_2_8703B	0x008C
-+#define REG_HMEBOX_DBG_3_8703B	0x008E
-+#define REG_HIMR0_8703B					0x00B0
-+#define REG_HISR0_8703B					0x00B4
-+#define REG_HIMR1_8703B					0x00B8
-+#define REG_HISR1_8703B					0x00BC
-+#define REG_PMC_DBG_CTRL2_8703B			0x00CC
-+#define	REG_EFUSE_BURN_GNT_8703B		0x00CF
-+#define REG_HPON_FSM_8703B				0x00EC
-+#define REG_SYS_CFG_8703B				0x00F0
-+#define REG_SYS_CFG1_8703B				0x00FC
-+#define REG_ROM_VERSION					0x00FD
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_C2HEVT_CMD_ID_8703B	0x01A0
-+#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
-+#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
-+#define REG_C2HEVT_CMD_LEN_8703B        0x01AE
-+#define REG_C2HEVT_CMD_LEN_88XX		REG_C2HEVT_CMD_LEN_8703B
-+#define REG_C2HEVT_CLEAR_8703B			0x01AF
-+#define REG_MCUTST_1_8703B				0x01C0
-+#define REG_WOWLAN_WAKE_REASON 0x01C7
-+#define REG_FMETHR_8703B				0x01C8
-+#define REG_HMETFR_8703B				0x01CC
-+#define REG_HMEBOX_0_8703B				0x01D0
-+#define REG_HMEBOX_1_8703B				0x01D4
-+#define REG_HMEBOX_2_8703B				0x01D8
-+#define REG_HMEBOX_3_8703B				0x01DC
-+#define REG_LLT_INIT_8703B				0x01E0
-+#define REG_HMEBOX_EXT0_8703B			0x01F0
-+#define REG_HMEBOX_EXT1_8703B			0x01F4
-+#define REG_HMEBOX_EXT2_8703B			0x01F8
-+#define REG_HMEBOX_EXT3_8703B			0x01FC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_RQPN_8703B					0x0200
-+#define REG_FIFOPAGE_8703B				0x0204
-+#define REG_DWBCN0_CTRL_8703B			REG_TDECTRL
-+#define REG_TXDMA_OFFSET_CHK_8703B	0x020C
-+#define REG_TXDMA_STATUS_8703B		0x0210
-+#define REG_RQPN_NPQ_8703B			0x0214
-+#define REG_DWBCN1_CTRL_8703B			0x0228
-+
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_RXDMA_AGG_PG_TH_8703B		0x0280
-+#define REG_FW_UPD_RDPTR_8703B		0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
-+#define REG_RXDMA_CONTROL_8703B		0x0286 /* Control the RX DMA. */
-+#define REG_RXPKT_NUM_8703B			0x0287 /* The number of packets in RXPKTBUF.	 */
-+#define REG_RXDMA_STATUS_8703B			0x0288
-+#define REG_RXDMA_MODE_CTRL_8703B		0x0290
-+#define REG_EARLY_MODE_CONTROL_8703B	0x02BC
-+#define REG_RSVD5_8703B					0x02F0
-+#define REG_RSVD6_8703B					0x02F4
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0300h ~ 0x03FFh	PCIe
-+ *
-+ * ----------------------------------------------------- */
-+#define	REG_PCIE_CTRL_REG_8703B		0x0300
-+#define	REG_INT_MIG_8703B				0x0304	/* Interrupt Migration */
-+#define	REG_BCNQ_DESA_8703B			0x0308	/* TX Beacon Descriptor Address */
-+#define	REG_HQ_DESA_8703B				0x0310	/* TX High Queue Descriptor Address */
-+#define	REG_MGQ_DESA_8703B			0x0318	/* TX Manage Queue Descriptor Address */
-+#define	REG_VOQ_DESA_8703B			0x0320	/* TX VO Queue Descriptor Address */
-+#define	REG_VIQ_DESA_8703B				0x0328	/* TX VI Queue Descriptor Address */
-+#define	REG_BEQ_DESA_8703B			0x0330	/* TX BE Queue Descriptor Address */
-+#define	REG_BKQ_DESA_8703B			0x0338	/* TX BK Queue Descriptor Address */
-+#define	REG_RX_DESA_8703B				0x0340	/* RX Queue	Descriptor Address */
-+#define	REG_DBI_WDATA_8703B			0x0348	/* DBI Write Data */
-+#define	REG_DBI_RDATA_8703B			0x034C	/* DBI Read Data */
-+#define	REG_DBI_ADDR_8703B				0x0350	/* DBI Address */
-+#define	REG_DBI_FLAG_8703B				0x0352	/* DBI Read/Write Flag */
-+#define	REG_MDIO_WDATA_8703B		0x0354	/* MDIO for Write PCIE PHY */
-+#define	REG_MDIO_RDATA_8703B			0x0356	/* MDIO for Reads PCIE PHY */
-+#define	REG_MDIO_CTL_8703B			0x0358	/* MDIO for Control */
-+#define	REG_DBG_SEL_8703B				0x0360	/* Debug Selection Register */
-+#define	REG_PCIE_HRPWM_8703B			0x0361	/* PCIe RPWM */
-+#define	REG_PCIE_HCPWM_8703B			0x0363	/* PCIe CPWM */
-+#define	REG_PCIE_MULTIFET_CTRL_8703B	0x036A	/* PCIE Multi-Fethc Control */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0400h ~ 0x047Fh	Protocol Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_VOQ_INFORMATION_8703B		0x0400
-+#define REG_VIQ_INFORMATION_8703B		0x0404
-+#define REG_BEQ_INFORMATION_8703B		0x0408
-+#define REG_BKQ_INFORMATION_8703B		0x040C
-+#define REG_MGQ_INFORMATION_8703B		0x0410
-+#define REG_HGQ_INFORMATION_8703B		0x0414
-+#define REG_BCNQ_INFORMATION_8703B	0x0418
-+#define REG_TXPKT_EMPTY_8703B			0x041A
-+
-+#define REG_FWHW_TXQ_CTRL_8703B		0x0420
-+#define REG_HWSEQ_CTRL_8703B			0x0423
-+#define REG_TXPKTBUF_BCNQ_BDNY_8703B	0x0424
-+#define REG_TXPKTBUF_MGQ_BDNY_8703B	0x0425
-+#define REG_LIFECTRL_CTRL_8703B			0x0426
-+#define REG_MULTI_BCNQ_OFFSET_8703B	0x0427
-+#define REG_SPEC_SIFS_8703B				0x0428
-+#define REG_RL_8703B						0x042A
-+#define REG_TXBF_CTRL_8703B				0x042C
-+#define REG_DARFRC_8703B				0x0430
-+#define REG_RARFRC_8703B				0x0438
-+#define REG_RRSR_8703B					0x0440
-+#define REG_ARFR0_8703B					0x0444
-+#define REG_ARFR1_8703B					0x044C
-+#define REG_CCK_CHECK_8703B				0x0454
-+#define REG_AMPDU_MAX_TIME_8703B		0x0456
-+#define REG_TXPKTBUF_BCNQ_BDNY1_8703B	0x0457
-+
-+#define REG_AMPDU_MAX_LENGTH_8703B	0x0458
-+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8703B	0x045D
-+#define REG_NDPA_OPT_CTRL_8703B		0x045F
-+#define REG_FAST_EDCA_CTRL_8703B		0x0460
-+#define REG_RD_RESP_PKT_TH_8703B		0x0463
-+#define REG_DATA_SC_8703B				0x0483
-+#ifdef CONFIG_WOWLAN
-+	#define REG_TXPKTBUF_IV_LOW             0x0484
-+	#define REG_TXPKTBUF_IV_HIGH            0x0488
-+#endif
-+#define REG_TXRPT_START_OFFSET		0x04AC
-+#define REG_POWER_STAGE1_8703B		0x04B4
-+#define REG_POWER_STAGE2_8703B		0x04B8
-+#define REG_AMPDU_BURST_MODE_8703B	0x04BC
-+#define REG_PKT_VO_VI_LIFE_TIME_8703B	0x04C0
-+#define REG_PKT_BE_BK_LIFE_TIME_8703B	0x04C2
-+#define REG_STBC_SETTING_8703B			0x04C4
-+#define REG_HT_SINGLE_AMPDU_8703B		0x04C7
-+#define REG_PROT_MODE_CTRL_8703B		0x04C8
-+#define REG_MAX_AGGR_NUM_8703B		0x04CA
-+#define REG_RTS_MAX_AGGR_NUM_8703B	0x04CB
-+#define REG_BAR_MODE_CTRL_8703B		0x04CC
-+#define REG_RA_TRY_RATE_AGG_LMT_8703B	0x04CF
-+#define REG_MACID_PKT_DROP0_8703B		0x04D0
-+#define REG_MACID_PKT_SLEEP_8703B		0x04D4
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0500h ~ 0x05FFh	EDCA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_EDCA_VO_PARAM_8703B		0x0500
-+#define REG_EDCA_VI_PARAM_8703B		0x0504
-+#define REG_EDCA_BE_PARAM_8703B		0x0508
-+#define REG_EDCA_BK_PARAM_8703B		0x050C
-+#define REG_BCNTCFG_8703B				0x0510
-+#define REG_PIFS_8703B					0x0512
-+#define REG_RDG_PIFS_8703B				0x0513
-+#define REG_SIFS_CTX_8703B				0x0514
-+#define REG_SIFS_TRX_8703B				0x0516
-+#define REG_AGGR_BREAK_TIME_8703B		0x051A
-+#define REG_SLOT_8703B					0x051B
-+#define REG_TX_PTCL_CTRL_8703B			0x0520
-+#define REG_TXPAUSE_8703B				0x0522
-+#define REG_DIS_TXREQ_CLR_8703B		0x0523
-+#define REG_RD_CTRL_8703B				0x0524
-+/*
-+ * Format for offset 540h-542h:
-+ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
-+ *	[7:4]:   Reserved.
-+ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
-+ *	[23:20]: Reserved
-+ * Description:
-+ *	              |
-+ * |<--Setup--|--Hold------------>|
-+ *	--------------|----------------------
-+ * |
-+ * TBTT
-+ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
-+ * Described by Designer Tim and Bruce, 2011-01-14.
-+ *   */
-+#define REG_TBTT_PROHIBIT_8703B			0x0540
-+#define REG_RD_NAV_NXT_8703B			0x0544
-+#define REG_NAV_PROT_LEN_8703B			0x0546
-+#define REG_BCN_CTRL_8703B				0x0550
-+#define REG_BCN_CTRL_1_8703B			0x0551
-+#define REG_MBID_NUM_8703B				0x0552
-+#define REG_DUAL_TSF_RST_8703B			0x0553
-+#define REG_BCN_INTERVAL_8703B			0x0554
-+#define REG_DRVERLYINT_8703B			0x0558
-+#define REG_BCNDMATIM_8703B			0x0559
-+#define REG_ATIMWND_8703B				0x055A
-+#define REG_USTIME_TSF_8703B			0x055C
-+#define REG_BCN_MAX_ERR_8703B			0x055D
-+#define REG_RXTSF_OFFSET_CCK_8703B		0x055E
-+#define REG_RXTSF_OFFSET_OFDM_8703B	0x055F
-+#define REG_TSFTR_8703B					0x0560
-+#define REG_CTWND_8703B					0x0572
-+#define REG_SECONDARY_CCA_CTRL_8703B	0x0577
-+#define REG_PSTIMER_8703B				0x0580
-+#define REG_TIMER0_8703B				0x0584
-+#define REG_TIMER1_8703B				0x0588
-+#define REG_ACMHWCTRL_8703B			0x05C0
-+#define REG_SCH_TXCMD_8703B			0x05F8
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0600h ~ 0x07FFh	WMAC Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_MAC_CR_8703B				0x0600
-+#define REG_TCR_8703B					0x0604
-+#define REG_RCR_8703B					0x0608
-+#define REG_RX_PKT_LIMIT_8703B			0x060C
-+#define REG_RX_DLK_TIME_8703B			0x060D
-+#define REG_RX_DRVINFO_SZ_8703B		0x060F
-+
-+#define REG_MACID_8703B					0x0610
-+#define REG_BSSID_8703B					0x0618
-+#define REG_MAR_8703B					0x0620
-+#define REG_MBIDCAMCFG_8703B			0x0628
-+#define REG_WOWLAN_GTK_DBG1	0x630
-+#define REG_WOWLAN_GTK_DBG2	0x634
-+
-+#define REG_USTIME_EDCA_8703B			0x0638
-+#define REG_MAC_SPEC_SIFS_8703B		0x063A
-+#define REG_RESP_SIFP_CCK_8703B			0x063C
-+#define REG_RESP_SIFS_OFDM_8703B		0x063E
-+#define REG_ACKTO_8703B					0x0640
-+#define REG_CTS2TO_8703B				0x0641
-+#define REG_EIFS_8703B					0x0642
-+
-+#define REG_NAV_UPPER_8703B			0x0652	/* unit of 128 */
-+#define REG_TRXPTCL_CTL_8703B			0x0668
-+
-+/* Security */
-+#define REG_CAMCMD_8703B				0x0670
-+#define REG_CAMWRITE_8703B				0x0674
-+#define REG_CAMREAD_8703B				0x0678
-+#define REG_CAMDBG_8703B				0x067C
-+#define REG_SECCFG_8703B				0x0680
-+
-+/* Power */
-+#define REG_WOW_CTRL_8703B				0x0690
-+#define REG_PS_RX_INFO_8703B			0x0692
-+#define REG_UAPSD_TID_8703B				0x0693
-+#define REG_WKFMCAM_CMD_8703B			0x0698
-+#define REG_WKFMCAM_NUM_8703B			0x0698
-+#define REG_WKFMCAM_RWD_8703B			0x069C
-+#define REG_RXFLTMAP0_8703B				0x06A0
-+#define REG_RXFLTMAP1_8703B				0x06A2
-+#define REG_RXFLTMAP2_8703B				0x06A4
-+#define REG_BCN_PSR_RPT_8703B			0x06A8
-+#define REG_BT_COEX_TABLE_8703B		0x06C0
-+#define REG_BFMER0_INFO_8703B			0x06E4
-+#define REG_BFMER1_INFO_8703B			0x06EC
-+#define REG_CSI_RPT_PARAM_BW20_8703B	0x06F4
-+#define REG_CSI_RPT_PARAM_BW40_8703B	0x06F8
-+#define REG_CSI_RPT_PARAM_BW80_8703B	0x06FC
-+
-+/* Hardware Port 2 */
-+#define REG_MACID1_8703B				0x0700
-+#define REG_BSSID1_8703B				0x0708
-+#define REG_BFMEE_SEL_8703B				0x0714
-+#define REG_SND_PTCL_CTRL_8703B		0x0718
-+
-+/* LTE_COEX */
-+#define REG_LTECOEX_CTRL			0x07C0
-+#define REG_LTECOEX_WRITE_DATA		0x07C4
-+#define REG_LTECOEX_READ_DATA		0x07C8
-+#define REG_LTECOEX_PATH_CONTROL	0x70
-+
-+/* ************************************************************
-+ * SDIO Bus Specification
-+ * ************************************************************ */
-+
-+/* -----------------------------------------------------
-+ * SDIO CMD Address Mapping
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ * I/O bus domain (Host)
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ * SDIO register
-+ * ----------------------------------------------------- */
-+#define SDIO_REG_HCPWM1_8703B	0x025 /* HCI Current Power Mode 1 */
-+
-+
-+/* ****************************************************************************
-+ *	8703 Regsiter Bit and Content definition
-+ * **************************************************************************** */
-+
-+#define BIT_USB_RXDMA_AGG_EN	BIT(31)
-+#define RXDMA_AGG_MODE_EN		BIT(1)
-+
-+#ifdef CONFIG_WOWLAN
-+	#define RXPKT_RELEASE_POLL		BIT(16)
-+	#define RXDMA_IDLE				BIT(17)
-+	#define RW_RELEASE_EN			BIT(18)
-+#endif
-+
-+/* 2 HSISR
-+ * interrupt mask which needs to clear */
-+#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
-+		HSISR_SPS_OCP_INT |\
-+		HSISR_RON_INT |\
-+		HSISR_PDNINT |\
-+		HSISR_GPIO9_INT)
-+
-+
-+/* ----------------------------------------------------------------------------
-+ * 8703B REG_CCK_CHECK						(offset 0x454)
-+ * ---------------------------------------------------------------------------- */
-+#define BIT_BCN_PORT_SEL		BIT(5)
-+
-+#ifdef CONFIG_RF_POWER_TRIM
-+
-+	#ifdef CONFIG_RTL8703B
-+		#define EEPROM_RF_GAIN_OFFSET			0xC1
-+	#endif
-+
-+	#define EEPROM_RF_GAIN_VAL				0x1F6
-+#endif /*CONFIG_RF_POWER_TRIM*/
-+
-+
-+/* ----------------------------------------------------------------------------
-+ * 8195 IMR/ISR bits						(offset 0xB0,  8bits)
-+ * ---------------------------------------------------------------------------- */
-+#define	IMR_DISABLED_8703B					0
-+/* IMR DW0(0x00B0-00B3) Bit 0-31 */
-+#define	IMR_TIMER2_8703B					BIT(31)		/* Timeout interrupt 2 */
-+#define	IMR_TIMER1_8703B					BIT(30)		/* Timeout interrupt 1	 */
-+#define	IMR_PSTIMEOUT_8703B				BIT(29)		/* Power Save Time Out Interrupt */
-+#define	IMR_GTINT4_8703B					BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
-+#define	IMR_GTINT3_8703B					BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
-+#define	IMR_TXBCN0ERR_8703B				BIT(26)		/* Transmit Beacon0 Error			 */
-+#define	IMR_TXBCN0OK_8703B				BIT(25)		/* Transmit Beacon0 OK			 */
-+#define	IMR_TSF_BIT32_TOGGLE_8703B		BIT(24)		/* TSF Timer BIT32 toggle indication interrupt			 */
-+#define	IMR_BCNDMAINT0_8703B				BIT(20)		/* Beacon DMA Interrupt 0			 */
-+#define	IMR_BCNDERR0_8703B				BIT(16)		/* Beacon Queue DMA OK0			 */
-+#define	IMR_HSISR_IND_ON_INT_8703B		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
-+#define	IMR_BCNDMAINT_E_8703B			BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
-+#define	IMR_ATIMEND_8703B				BIT(12)		/* CTWidnow End or ATIM Window End */
-+#define	IMR_C2HCMD_8703B					BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
-+#define	IMR_CPWM2_8703B					BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
-+#define	IMR_CPWM_8703B					BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
-+#define	IMR_HIGHDOK_8703B				BIT(7)			/* High Queue DMA OK	 */
-+#define	IMR_MGNTDOK_8703B				BIT(6)			/* Management Queue DMA OK	 */
-+#define	IMR_BKDOK_8703B					BIT(5)			/* AC_BK DMA OK		 */
-+#define	IMR_BEDOK_8703B					BIT(4)			/* AC_BE DMA OK	 */
-+#define	IMR_VIDOK_8703B					BIT(3)			/* AC_VI DMA OK		 */
-+#define	IMR_VODOK_8703B					BIT(2)			/* AC_VO DMA OK	 */
-+#define	IMR_RDU_8703B					BIT(1)			/* Rx Descriptor Unavailable	 */
-+#define	IMR_ROK_8703B					BIT(0)			/* Receive DMA OK */
-+
-+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
-+#define	IMR_BCNDMAINT7_8703B				BIT(27)		/* Beacon DMA Interrupt 7 */
-+#define	IMR_BCNDMAINT6_8703B				BIT(26)		/* Beacon DMA Interrupt 6 */
-+#define	IMR_BCNDMAINT5_8703B				BIT(25)		/* Beacon DMA Interrupt 5 */
-+#define	IMR_BCNDMAINT4_8703B				BIT(24)		/* Beacon DMA Interrupt 4 */
-+#define	IMR_BCNDMAINT3_8703B				BIT(23)		/* Beacon DMA Interrupt 3 */
-+#define	IMR_BCNDMAINT2_8703B				BIT(22)		/* Beacon DMA Interrupt 2 */
-+#define	IMR_BCNDMAINT1_8703B				BIT(21)		/* Beacon DMA Interrupt 1 */
-+#define	IMR_BCNDOK7_8703B					BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
-+#define	IMR_BCNDOK6_8703B					BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
-+#define	IMR_BCNDOK5_8703B					BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
-+#define	IMR_BCNDOK4_8703B					BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
-+#define	IMR_BCNDOK3_8703B					BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
-+#define	IMR_BCNDOK2_8703B					BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
-+#define	IMR_BCNDOK1_8703B					BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
-+#define	IMR_ATIMEND_E_8703B				BIT(13)		/* ATIM Window End Extension for Win7 */
-+#define	IMR_TXERR_8703B					BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
-+#define	IMR_RXERR_8703B					BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
-+#define	IMR_TXFOVW_8703B					BIT(9)			/* Transmit FIFO Overflow */
-+#define	IMR_RXFOVW_8703B					BIT(8)			/* Receive FIFO Overflow */
-+
-+#ifdef CONFIG_PCI_HCI
-+	/* #define IMR_RX_MASK		(IMR_ROK_8703B|IMR_RDU_8703B|IMR_RXFOVW_8703B) */
-+	#define IMR_TX_MASK			(IMR_VODOK_8703B | IMR_VIDOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B | IMR_MGNTDOK_8703B | IMR_HIGHDOK_8703B)
-+
-+	#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8703B | IMR_TXBCN0OK_8703B | IMR_TXBCN0ERR_8703B | IMR_BCNDERR0_8703B)
-+
-+	#define RT_AC_INT_MASKS	(IMR_VIDOK_8703B | IMR_VODOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B)
-+#endif
-+
-+#endif /* __RTL8703B_SPEC_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8703b_sreset.h b/drivers/staging/rtl8723cs/include/rtl8703b_sreset.h
-new file mode 100644
-index 000000000000..5fe53cf414a1
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8703b_sreset.h
-@@ -0,0 +1,24 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8703B_SRESET_H_
-+#define _RTL8703B_SRESET_H_
-+
-+#include <rtw_sreset.h>
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	extern void rtl8703b_sreset_xmit_status_check(_adapter *padapter);
-+	extern void rtl8703b_sreset_linked_status_check(_adapter *padapter);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8703b_xmit.h b/drivers/staging/rtl8723cs/include/rtl8703b_xmit.h
-new file mode 100644
-index 000000000000..9ec00a66a564
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8703b_xmit.h
-@@ -0,0 +1,342 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8703B_XMIT_H__
-+#define __RTL8703B_XMIT_H__
-+
-+
-+#define MAX_TID (15)
-+
-+
-+#ifndef __INC_HAL8703BDESC_H
-+	#define __INC_HAL8703BDESC_H
-+
-+	#define RX_STATUS_DESC_SIZE_8703B		24
-+	#define RX_DRV_INFO_SIZE_UNIT_8703B 8
-+
-+
-+	/* DWORD 0 */
-+	#define SET_RX_STATUS_DESC_PKT_LEN_8703B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
-+	#define SET_RX_STATUS_DESC_EOR_8703B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
-+	#define SET_RX_STATUS_DESC_OWN_8703B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
-+
-+	#define GET_RX_STATUS_DESC_PKT_LEN_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
-+	#define GET_RX_STATUS_DESC_CRC32_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
-+	#define GET_RX_STATUS_DESC_ICV_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
-+	#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
-+	#define GET_RX_STATUS_DESC_SECURITY_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
-+	#define GET_RX_STATUS_DESC_QOS_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
-+	#define GET_RX_STATUS_DESC_SHIFT_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
-+	#define GET_RX_STATUS_DESC_PHY_STATUS_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
-+	#define GET_RX_STATUS_DESC_SWDEC_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
-+	#define GET_RX_STATUS_DESC_LAST_SEG_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
-+	#define GET_RX_STATUS_DESC_FIRST_SEG_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
-+	#define GET_RX_STATUS_DESC_EOR_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
-+	#define GET_RX_STATUS_DESC_OWN_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
-+
-+	/* DWORD 1 */
-+	#define GET_RX_STATUS_DESC_MACID_8703B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
-+	#define GET_RX_STATUS_DESC_TID_8703B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
-+	#define GET_RX_STATUS_DESC_AMSDU_8703B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
-+	#define GET_RX_STATUS_DESC_RXID_MATCH_8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
-+	#define GET_RX_STATUS_DESC_PAGGR_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
-+	#define GET_RX_STATUS_DESC_A1_FIT_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
-+	#define GET_RX_STATUS_DESC_CHKERR_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
-+	#define GET_RX_STATUS_DESC_IPVER_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
-+	#define GET_RX_STATUS_DESC_IS_TCPUDP__8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
-+	#define GET_RX_STATUS_DESC_CHK_VLD_8703B(__pRxDesc)	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
-+	#define GET_RX_STATUS_DESC_PAM_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
-+	#define GET_RX_STATUS_DESC_PWR_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
-+	#define GET_RX_STATUS_DESC_MORE_DATA_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
-+	#define GET_RX_STATUS_DESC_MORE_FRAG_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
-+	#define GET_RX_STATUS_DESC_TYPE_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
-+	#define GET_RX_STATUS_DESC_MC_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
-+	#define GET_RX_STATUS_DESC_BC_8703B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
-+
-+	/* DWORD 2 */
-+	#define GET_RX_STATUS_DESC_SEQ_8703B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
-+	#define GET_RX_STATUS_DESC_FRAG_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
-+	#define GET_RX_STATUS_DESC_RX_IS_QOS_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
-+	#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8703B(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
-+	#define GET_RX_STATUS_DESC_RPT_SEL_8703B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
-+
-+	/* DWORD 3 */
-+	#define GET_RX_STATUS_DESC_RX_RATE_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
-+	#define GET_RX_STATUS_DESC_HTC_8703B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
-+	#define GET_RX_STATUS_DESC_EOSP_8703B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
-+	#define GET_RX_STATUS_DESC_BSSID_FIT_8703B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
-+	#ifdef CONFIG_USB_RX_AGGREGATION
-+		#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8703B(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
-+	#endif
-+	#define GET_RX_STATUS_DESC_PATTERN_MATCH_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
-+	#define GET_RX_STATUS_DESC_UNICAST_MATCH_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
-+	#define GET_RX_STATUS_DESC_MAGIC_MATCH_8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
-+
-+	/* DWORD 6 */
-+	#define GET_RX_STATUS_DESC_SPLCP_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
-+	#define GET_RX_STATUS_DESC_LDPC_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
-+	#define GET_RX_STATUS_DESC_STBC_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
-+	#define GET_RX_STATUS_DESC_BW_8703B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
-+
-+	/* DWORD 5 */
-+	#define GET_RX_STATUS_DESC_TSFL_8703B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
-+
-+	#define GET_RX_STATUS_DESC_BUFF_ADDR_8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
-+	#define GET_RX_STATUS_DESC_BUFF_ADDR64_8703B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
-+
-+	#define SET_RX_STATUS_DESC_BUFF_ADDR_8703B(__pRxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
-+
-+
-+	/* Dword 0 */
-+	#define GET_TX_DESC_OWN_8703B(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
-+
-+	#define SET_TX_DESC_PKT_SIZE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
-+	#define SET_TX_DESC_OFFSET_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
-+	#define SET_TX_DESC_BMC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
-+	#define SET_TX_DESC_HTC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
-+	#define SET_TX_DESC_LAST_SEG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
-+	#define SET_TX_DESC_FIRST_SEG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
-+	#define SET_TX_DESC_LINIP_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
-+	#define SET_TX_DESC_NO_ACM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
-+	#define SET_TX_DESC_GF_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
-+	#define SET_TX_DESC_OWN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
-+
-+	/* Dword 1 */
-+	#define SET_TX_DESC_MACID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
-+	#define SET_TX_DESC_QUEUE_SEL_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
-+	#define SET_TX_DESC_RDG_NAV_EXT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
-+	#define SET_TX_DESC_LSIG_TXOP_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
-+	#define SET_TX_DESC_PIFS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
-+	#define SET_TX_DESC_RATE_ID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
-+	#define SET_TX_DESC_EN_DESC_ID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
-+	#define SET_TX_DESC_SEC_TYPE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
-+	#define SET_TX_DESC_PKT_OFFSET_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
-+
-+
-+	/* Dword 2 */
-+	#define SET_TX_DESC_PAID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
-+	#define SET_TX_DESC_CCA_RTS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
-+	#define SET_TX_DESC_AGG_ENABLE_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
-+	#define SET_TX_DESC_RDG_ENABLE_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
-+	#define SET_TX_DESC_AGG_BREAK_8703B(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
-+	#define SET_TX_DESC_MORE_FRAG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
-+	#define SET_TX_DESC_RAW_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
-+	#define SET_TX_DESC_SPE_RPT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
-+	#define SET_TX_DESC_AMPDU_DENSITY_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
-+	#define SET_TX_DESC_BT_INT_8703B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
-+	#define SET_TX_DESC_GID_8703B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
-+
-+
-+	/* Dword 3 */
-+	#define SET_TX_DESC_WHEADER_LEN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
-+	#define SET_TX_DESC_CHK_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
-+	#define SET_TX_DESC_EARLY_MODE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
-+	#define SET_TX_DESC_HWSEQ_SEL_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
-+	#define SET_TX_DESC_USE_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
-+	#define SET_TX_DESC_DISABLE_RTS_FB_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
-+	#define SET_TX_DESC_DISABLE_FB_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
-+	#define SET_TX_DESC_CTS2SELF_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
-+	#define SET_TX_DESC_RTS_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
-+	#define SET_TX_DESC_HW_RTS_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
-+	#define SET_TX_DESC_NAV_USE_HDR_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
-+	#define SET_TX_DESC_USE_MAX_LEN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
-+	#define SET_TX_DESC_MAX_AGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
-+	#define SET_TX_DESC_NDPA_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
-+	#define SET_TX_DESC_AMPDU_MAX_TIME_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
-+
-+	/* Dword 4 */
-+	#define SET_TX_DESC_TX_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
-+	#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
-+	#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
-+	#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
-+	#define SET_TX_DESC_DATA_RETRY_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
-+	#define SET_TX_DESC_RTS_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
-+
-+
-+	/* Dword 5 */
-+	#define SET_TX_DESC_DATA_SC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
-+	#define SET_TX_DESC_DATA_SHORT_8703B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
-+	#define SET_TX_DESC_DATA_BW_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
-+	#define SET_TX_DESC_DATA_LDPC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
-+	#define SET_TX_DESC_DATA_STBC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
-+	#define SET_TX_DESC_CTROL_STBC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
-+	#define SET_TX_DESC_RTS_SHORT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
-+	#define SET_TX_DESC_RTS_SC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
-+
-+
-+	/* Dword 6 */
-+	#define SET_TX_DESC_SW_DEFINE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
-+	#define SET_TX_DESC_MBSSID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
-+	#define SET_TX_DESC_ANTSEL_A_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
-+	#define SET_TX_DESC_ANTSEL_B_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
-+	#define SET_TX_DESC_ANTSEL_C_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
-+	#define SET_TX_DESC_ANTSEL_D_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
-+
-+	/* Dword 7 */
-+	#ifdef CONFIG_PCI_HCI
-+		#define SET_TX_DESC_TX_BUFFER_SIZE_8703B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+	#endif /*CONFIG_PCI_HCI*/
-+	#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
-+		#define SET_TX_DESC_TX_DESC_CHECKSUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+	#endif
-+	#define SET_TX_DESC_USB_TXAGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
-+	#ifdef CONFIG_SDIO_HCI
-+		#define SET_TX_DESC_SDIO_TXSEQ_8703B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
-+	#endif
-+
-+	/* Dword 8 */
-+	#define SET_TX_DESC_HWSEQ_EN_8703B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
-+
-+	/* Dword 9 */
-+	#define SET_TX_DESC_SEQ_8703B(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
-+
-+	/* Dword 10 */
-+	#define SET_TX_DESC_TX_BUFFER_ADDRESS_8703B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
-+	#define GET_TX_DESC_TX_BUFFER_ADDRESS_8703B(__pTxDesc)	LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
-+
-+	/* Dword 11 */
-+	#define SET_TX_DESC_NEXT_DESC_ADDRESS_8703B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
-+
-+
-+	#define SET_EARLYMODE_PKTNUM_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
-+	#define SET_EARLYMODE_LEN0_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
-+	#define SET_EARLYMODE_LEN1_1_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
-+	#define SET_EARLYMODE_LEN1_2_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
-+	#define SET_EARLYMODE_LEN2_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
-+	#define SET_EARLYMODE_LEN3_8703B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
-+
-+#endif
-+/* -----------------------------------------------------------
-+ *
-+ *	Rate
-+ *
-+ * -----------------------------------------------------------
-+ * CCK Rates, TxHT = 0 */
-+#define DESC8703B_RATE1M				0x00
-+#define DESC8703B_RATE2M				0x01
-+#define DESC8703B_RATE5_5M				0x02
-+#define DESC8703B_RATE11M				0x03
-+
-+/* OFDM Rates, TxHT = 0 */
-+#define DESC8703B_RATE6M				0x04
-+#define DESC8703B_RATE9M				0x05
-+#define DESC8703B_RATE12M				0x06
-+#define DESC8703B_RATE18M				0x07
-+#define DESC8703B_RATE24M				0x08
-+#define DESC8703B_RATE36M				0x09
-+#define DESC8703B_RATE48M				0x0a
-+#define DESC8703B_RATE54M				0x0b
-+
-+/* MCS Rates, TxHT = 1 */
-+#define DESC8703B_RATEMCS0				0x0c
-+#define DESC8703B_RATEMCS1				0x0d
-+#define DESC8703B_RATEMCS2				0x0e
-+#define DESC8703B_RATEMCS3				0x0f
-+#define DESC8703B_RATEMCS4				0x10
-+#define DESC8703B_RATEMCS5				0x11
-+#define DESC8703B_RATEMCS6				0x12
-+#define DESC8703B_RATEMCS7				0x13
-+#define DESC8703B_RATEMCS8				0x14
-+#define DESC8703B_RATEMCS9				0x15
-+#define DESC8703B_RATEMCS10		0x16
-+#define DESC8703B_RATEMCS11		0x17
-+#define DESC8703B_RATEMCS12		0x18
-+#define DESC8703B_RATEMCS13		0x19
-+#define DESC8703B_RATEMCS14		0x1a
-+#define DESC8703B_RATEMCS15		0x1b
-+#define DESC8703B_RATEVHTSS1MCS0		0x2c
-+#define DESC8703B_RATEVHTSS1MCS1		0x2d
-+#define DESC8703B_RATEVHTSS1MCS2		0x2e
-+#define DESC8703B_RATEVHTSS1MCS3		0x2f
-+#define DESC8703B_RATEVHTSS1MCS4		0x30
-+#define DESC8703B_RATEVHTSS1MCS5		0x31
-+#define DESC8703B_RATEVHTSS1MCS6		0x32
-+#define DESC8703B_RATEVHTSS1MCS7		0x33
-+#define DESC8703B_RATEVHTSS1MCS8		0x34
-+#define DESC8703B_RATEVHTSS1MCS9		0x35
-+#define DESC8703B_RATEVHTSS2MCS0		0x36
-+#define DESC8703B_RATEVHTSS2MCS1		0x37
-+#define DESC8703B_RATEVHTSS2MCS2		0x38
-+#define DESC8703B_RATEVHTSS2MCS3		0x39
-+#define DESC8703B_RATEVHTSS2MCS4		0x3a
-+#define DESC8703B_RATEVHTSS2MCS5		0x3b
-+#define DESC8703B_RATEVHTSS2MCS6		0x3c
-+#define DESC8703B_RATEVHTSS2MCS7		0x3d
-+#define DESC8703B_RATEVHTSS2MCS8		0x3e
-+#define DESC8703B_RATEVHTSS2MCS9		0x3f
-+
-+
-+#define	RX_HAL_IS_CCK_RATE_8703B(pDesc)\
-+	(GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE1M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE2M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE5_5M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE11M)
-+
-+
-+void rtl8703b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
-+void rtl8703b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
-+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	s32 rtl8703bs_init_xmit_priv(PADAPTER padapter);
-+	void rtl8703bs_free_xmit_priv(PADAPTER padapter);
-+	s32 rtl8703bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8703bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8703bs_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	rtl8703bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8703bs_xmit_buf_handler(PADAPTER padapter);
-+	thread_return rtl8703bs_xmit_thread(thread_context context);
-+	#define hal_xmit_handler rtl8703bs_xmit_buf_handler
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	s32 rtl8703bu_xmit_buf_handler(PADAPTER padapter);
-+	#define hal_xmit_handler rtl8703bu_xmit_buf_handler
-+
-+
-+	s32 rtl8703bu_init_xmit_priv(PADAPTER padapter);
-+	void rtl8703bu_free_xmit_priv(PADAPTER padapter);
-+	s32 rtl8703bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8703bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8703bu_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	 rtl8703bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */
-+	void rtl8703bu_xmit_tasklet(void *priv);
-+	s32 rtl8703bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+	void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8703be_init_xmit_priv(PADAPTER padapter);
-+	void rtl8703be_free_xmit_priv(PADAPTER padapter);
-+	struct xmit_buf *rtl8703be_dequeue_xmitbuf(struct rtw_tx_ring *ring);
-+	void	rtl8703be_xmitframe_resume(_adapter *padapter);
-+	s32 rtl8703be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8703be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8703be_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	rtl8703be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	void rtl8703be_xmit_tasklet(void *priv);
-+#endif
-+
-+u8	BWMapping_8703B(PADAPTER Adapter, struct pkt_attrib *pattrib);
-+u8	SCMapping_8703B(PADAPTER Adapter, struct pkt_attrib	*pattrib);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8710b_cmd.h b/drivers/staging/rtl8723cs/include/rtl8710b_cmd.h
-new file mode 100644
-index 000000000000..0237d18ea82e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8710b_cmd.h
-@@ -0,0 +1,169 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8710B_CMD_H__
-+#define __RTL8710B_CMD_H__
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+enum h2c_cmd_8710B {
-+	/* Common Class: 000 */
-+	H2C_8710B_RSVD_PAGE = 0x00,
-+	H2C_8710B_MEDIA_STATUS_RPT = 0x01,
-+	H2C_8710B_SCAN_ENABLE = 0x02,
-+	H2C_8710B_KEEP_ALIVE = 0x03,
-+	H2C_8710B_DISCON_DECISION = 0x04,
-+	H2C_8710B_PSD_OFFLOAD = 0x05,
-+	H2C_8710B_AP_OFFLOAD = 0x08,
-+	H2C_8710B_BCN_RSVDPAGE = 0x09,
-+	H2C_8710B_PROBERSP_RSVDPAGE = 0x0A,
-+	H2C_8710B_FCS_RSVDPAGE = 0x10,
-+	H2C_8710B_FCS_INFO = 0x11,
-+	H2C_8710B_AP_WOW_GPIO_CTRL = 0x13,
-+
-+	/* PoweSave Class: 001 */
-+	H2C_8710B_SET_PWR_MODE = 0x20,
-+	H2C_8710B_PS_TUNING_PARA = 0x21,
-+	H2C_8710B_PS_TUNING_PARA2 = 0x22,
-+	H2C_8710B_P2P_LPS_PARAM = 0x23,
-+	H2C_8710B_P2P_PS_OFFLOAD = 0x24,
-+	H2C_8710B_PS_SCAN_ENABLE = 0x25,
-+	H2C_8710B_SAP_PS_ = 0x26,
-+	H2C_8710B_INACTIVE_PS_ = 0x27, /* Inactive_PS */
-+	H2C_8710B_FWLPS_IN_IPS_ = 0x28,
-+
-+	/* Dynamic Mechanism Class: 010 */
-+	H2C_8710B_MACID_CFG = 0x40,
-+	H2C_8710B_TXBF = 0x41,
-+	H2C_8710B_RSSI_SETTING = 0x42,
-+	H2C_8710B_AP_REQ_TXRPT = 0x43,
-+	H2C_8710B_INIT_RATE_COLLECT = 0x44,
-+	H2C_8710B_RA_PARA_ADJUST = 0x46,
-+
-+	/* WOWLAN Class: 100 */
-+	H2C_8710B_WOWLAN = 0x80,
-+	H2C_8710B_REMOTE_WAKE_CTRL = 0x81,
-+	H2C_8710B_AOAC_GLOBAL_INFO = 0x82,
-+	H2C_8710B_AOAC_RSVD_PAGE = 0x83,
-+	H2C_8710B_AOAC_RSVD_PAGE2 = 0x84,
-+	H2C_8710B_D0_SCAN_OFFLOAD_CTRL = 0x85,
-+	H2C_8710B_D0_SCAN_OFFLOAD_INFO = 0x86,
-+	H2C_8710B_CHNL_SWITCH_OFFLOAD = 0x87,
-+	H2C_8710B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
-+	H2C_8710B_P2P_OFFLOAD = 0x8B,
-+
-+	H2C_8710B_RESET_TSF = 0xC0,
-+	H2C_8710B_MAXID,
-+};
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
-+ * ---------------------------------------------------------------------------------------------------------
-+ * _RSVDPAGE_LOC_CMD_0x00 */
-+#define SET_8710B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+/* _PWR_MOD_CMD_0x20 */
-+#define SET_8710B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
-+#define SET_8710B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
-+#define SET_8710B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
-+#define SET_8710B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+#define GET_8710B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
-+
-+/* _PS_TUNE_PARAM_CMD_0x21 */
-+#define SET_8710B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
-+#define SET_8710B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
-+#define SET_8710B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+
-+/* _MACID_CFG_CMD_0x40 */
-+#define SET_8710B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
-+#define SET_8710B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
-+#define SET_8710B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
-+#define SET_8710B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
-+#define SET_8710B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
-+#define SET_8710B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
-+#define SET_8710B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
-+#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
-+
-+/* _RSSI_SETTING_CMD_0x42 */
-+#define SET_8710B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
-+#define SET_8710B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+
-+/* _AP_REQ_TXRPT_CMD_0x43 */
-+#define SET_8710B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+
-+/* _FORCE_BT_TXPWR_CMD_0x62 */
-+#define SET_8710B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+
-+/* _FORCE_BT_MP_OPER_CMD_0x67 */
-+#define SET_8710B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
-+#define SET_8710B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
-+#define SET_8710B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
-+
-+/* _BT_FW_PATCH_0x6A */
-+#define SET_8710B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
-+#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * -------------------------------------------    Structure    --------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    Function Statement     --------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+/* host message to firmware cmd */
-+void rtl8710b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
-+void rtl8710b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
-+/* s32 rtl8710b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
-+void rtl8710b_set_FwPsTuneParam_cmd(PADAPTER padapter);
-+void rtl8710b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
-+#ifdef CONFIG_BT_COEXIST
-+	void rtl8710b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
-+#endif /* CONFIG_BT_COEXIST */
-+#ifdef CONFIG_P2P
-+	void rtl8710b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
-+#endif /* CONFIG_P2P */
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+	void rtl8710b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
-+#endif
-+
-+s32 FillH2CCmd8710B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
-+u8 GetTxBufferRsvdPageNum8710B(_adapter *padapter, bool wowlan);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8710b_dm.h b/drivers/staging/rtl8723cs/include/rtl8710b_dm.h
-new file mode 100644
-index 000000000000..9a131ba05df3
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8710b_dm.h
-@@ -0,0 +1,39 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8710B_DM_H__
-+#define __RTL8710B_DM_H__
-+/* ************************************************************
-+ * Description:
-+ *
-+ * This file is for 8710B dynamic mechanism only
-+ *
-+ *
-+ * ************************************************************ */
-+
-+/* ************************************************************
-+ * structure and define
-+ * ************************************************************ */
-+
-+/* ************************************************************
-+ * function prototype
-+ * ************************************************************ */
-+
-+void rtl8710b_init_dm_priv(PADAPTER padapter);
-+void rtl8710b_deinit_dm_priv(PADAPTER padapter);
-+
-+void rtl8710b_InitHalDm(PADAPTER padapter);
-+void rtl8710b_HalDmWatchDog(PADAPTER padapter);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8710b_hal.h b/drivers/staging/rtl8723cs/include/rtl8710b_hal.h
-new file mode 100644
-index 000000000000..332112b3196c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8710b_hal.h
-@@ -0,0 +1,277 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8710B_HAL_H__
-+#define __RTL8710B_HAL_H__
-+
-+#include "hal_data.h"
-+
-+#include "rtl8710b_spec.h"
-+#include "rtl8710b_rf.h"
-+#include "rtl8710b_dm.h"
-+#include "rtl8710b_recv.h"
-+#include "rtl8710b_xmit.h"
-+#include "rtl8710b_cmd.h"
-+#include "rtl8710b_led.h"
-+#include "Hal8710BPwrSeq.h"
-+#include "Hal8710BPhyReg.h"
-+#include "Hal8710BPhyCfg.h"
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	#include "rtl8710b_sreset.h"
-+#endif
-+#ifdef CONFIG_LPS_POFF
-+	#include "rtl8710b_lps_poff.h"
-+#endif
-+
-+#define FW_8710B_SIZE		0x8000
-+#define FW_8710B_START_ADDRESS	0x1000
-+#define FW_8710B_END_ADDRESS	0x1FFF /* 0x5FFF */
-+
-+typedef struct _RT_FIRMWARE {
-+	FIRMWARE_SOURCE	eFWSource;
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+	u8			*szFwBuffer;
-+#else
-+	u8			szFwBuffer[FW_8710B_SIZE];
-+#endif
-+	u32			ulFwLength;
-+} RT_FIRMWARE_8710B, *PRT_FIRMWARE_8710B;
-+
-+/*
-+ * This structure must be cared byte-ordering
-+ *
-+ * Added by tynli. 2009.12.04. */
-+typedef struct _RT_8710B_FIRMWARE_HDR {
-+	/* 8-byte alinment required */
-+
-+	/* --- LONG WORD 0 ---- */
-+	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
-+	u8		Category;	/* AP/NIC and USB/PCI */
-+	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
-+	u16		Version;		/* FW Version */
-+	u16		Subversion;	/* FW Subversion, default 0x00 */
-+
-+	/* --- LONG WORD 1 ---- */
-+	u8		Month;	/* Release time Month field */
-+	u8		Date;	/* Release time Date field */
-+	u8		Hour;	/* Release time Hour field */
-+	u8		Minute;	/* Release time Minute field */
-+	u16		RamCodeSize;	/* The size of RAM code */
-+	u16		Rsvd2;
-+
-+	/* --- LONG WORD 2 ---- */
-+	u32		SvnIdx;	/* The SVN entry index */
-+	u32		Rsvd3;
-+
-+	/* --- LONG WORD 3 ---- */
-+	u32		Rsvd4;
-+	u32		Rsvd5;
-+} RT_8710B_FIRMWARE_HDR, *PRT_8710B_FIRMWARE_HDR;
-+
-+#define DRIVER_EARLY_INT_TIME_8710B		0x05
-+#define BCN_DMA_ATIME_INT_TIME_8710B		0x02
-+
-+/* for 8710B
-+ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
-+#define PAGE_SIZE_TX_8710B			128
-+#define PAGE_SIZE_RX_8710B			8
-+
-+#define TX_DMA_SIZE_8710B			0x8000	/* 32K(TX) */
-+#define RX_DMA_SIZE_8710B			0x4000	/* 16K(RX) */
-+
-+#ifdef CONFIG_WOWLAN
-+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
-+#else
-+	#define RESV_FMWF	0
-+#endif
-+
-+#ifdef CONFIG_FW_C2H_DEBUG
-+	#define RX_DMA_RESERVED_SIZE_8710B	0x100	/* 256B, reserved for c2h debug message */
-+#else
-+	#define RX_DMA_RESERVED_SIZE_8710B	0x80	/* 128B, reserved for tx report */
-+#endif
-+#define RX_DMA_BOUNDARY_8710B\
-+	(RX_DMA_SIZE_8710B - RX_DMA_RESERVED_SIZE_8710B - 1)
-+
-+
-+/* Note: We will divide number of page equally for each queue other than public queue! */
-+
-+/* For General Reserved Page Number(Beacon Queue is reserved page)
-+ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8710B
-+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
-+#define BCNQ_PAGE_NUM_8710B	(MAX_BEACON_LEN/PAGE_SIZE_TX_8710B + 6) /*0x08*/
-+
-+
-+/* For WoWLan , more reserved page
-+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
-+ * NS offload: 2 NDP info: 1
-+ */
-+#ifdef CONFIG_WOWLAN
-+	#define WOWLAN_PAGE_NUM_8710B	0x0b
-+#else
-+	#define WOWLAN_PAGE_NUM_8710B	0x00
-+#endif
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+	#undef WOWLAN_PAGE_NUM_8710B
-+	#define WOWLAN_PAGE_NUM_8710B	0x15
-+#endif
-+
-+#ifdef CONFIG_AP_WOWLAN
-+	#define AP_WOWLAN_PAGE_NUM_8710B	0x02
-+#endif
-+
-+#define TX_TOTAL_PAGE_NUMBER_8710B\
-+	(0xFF - BCNQ_PAGE_NUM_8710B -WOWLAN_PAGE_NUM_8710B)
-+#define TX_PAGE_BOUNDARY_8710B		(TX_TOTAL_PAGE_NUMBER_8710B + 1)
-+
-+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8710B	TX_TOTAL_PAGE_NUMBER_8710B
-+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8710B\
-+	(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8710B + 1)
-+
-+/* For Normal Chip Setting
-+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8710B */
-+#define NORMAL_PAGE_NUM_HPQ_8710B		0x0C
-+#define NORMAL_PAGE_NUM_LPQ_8710B		0x02
-+#define NORMAL_PAGE_NUM_NPQ_8710B		0x02
-+#define NORMAL_PAGE_NUM_EPQ_8710B		0x04
-+
-+/* Note: For Normal Chip Setting, modify later */
-+#define WMM_NORMAL_PAGE_NUM_HPQ_8710B		0x30
-+#define WMM_NORMAL_PAGE_NUM_LPQ_8710B		0x20
-+#define WMM_NORMAL_PAGE_NUM_NPQ_8710B		0x20
-+#define WMM_NORMAL_PAGE_NUM_EPQ_8710B		0x00
-+
-+
-+#include "HalVerDef.h"
-+#include "hal_com.h"
-+
-+#define EFUSE_OOB_PROTECT_BYTES (96 + 1)
-+
-+#define HAL_EFUSE_MEMORY
-+#define HWSET_MAX_SIZE_8710B                512
-+#define EFUSE_REAL_CONTENT_LEN_8710B        512
-+#define EFUSE_MAP_LEN_8710B                 512
-+#define EFUSE_MAX_SECTION_8710B             64
-+
-+/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
-+#define EFUSE_IC_ID_OFFSET			506
-+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8710B)
-+
-+#define EFUSE_ACCESS_ON	0x69
-+#define EFUSE_ACCESS_OFF	0x00
-+
-+#define   PACKAGE_QFN32_S           0
-+#define   PACKAGE_QFN48M_S        1    //definiton 8188GU Dongle Package, Efuse Physical Address 0xF8 = 0xFE
-+#define   PACKAGE_QFN48_S  	       2
-+#define   PACKAGE_QFN64_S  	       3     
-+#define   PACKAGE_QFN32_U  		4    
-+#define   PACKAGE_QFN48M_U  	5   //definiton 8188GU Dongle Package, Efuse Physical Address 0xF8 = 0xEE
-+#define   PACKAGE_QFN48_U  		6 
-+#define   PACKAGE_QFN68_U  		7
-+
-+typedef enum _PACKAGE_TYPE_E
-+{
-+    PACKAGE_DEFAULT,
-+    PACKAGE_QFN68,
-+    PACKAGE_TFBGA90,
-+    PACKAGE_TFBGA80,
-+    PACKAGE_TFBGA79
-+}PACKAGE_TYPE_E;
-+
-+#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
-+	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
-+
-+#ifdef CONFIG_FILE_FWIMG
-+	extern char *rtw_fw_file_path;
-+	extern char *rtw_fw_wow_file_path;
-+	#ifdef CONFIG_MP_INCLUDED
-+		extern char *rtw_fw_mp_bt_file_path;
-+	#endif /* CONFIG_MP_INCLUDED */
-+#endif /* CONFIG_FILE_FWIMG */
-+
-+/* rtl8710b_hal_init.c */
-+s32 rtl8710b_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
-+void rtl8710b_FirmwareSelfReset(PADAPTER padapter);
-+void rtl8710b_InitializeFirmwareVars(PADAPTER padapter);
-+
-+void rtl8710b_InitAntenna_Selection(PADAPTER padapter);
-+void rtl8710b_DeinitAntenna_Selection(PADAPTER padapter);
-+void rtl8710b_CheckAntenna_Selection(PADAPTER padapter);
-+void rtl8710b_init_default_value(PADAPTER padapter);
-+
-+
-+u32 indirect_read32_8710b(PADAPTER padapter, u32 regaddr);
-+void indirect_write32_8710b(PADAPTER padapter, u32 regaddr, u32 data);
-+u32 hal_query_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask);
-+void hal_set_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask, u32 data);
-+#define HAL_SetSYSOnReg hal_set_syson_reg_8710b
-+
-+
-+/* EFuse */
-+u8 GetEEPROMSize8710B(PADAPTER padapter);
-+
-+#if 0
-+void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
-+void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
-+void Hal_EfuseParseTxPowerInfo_8710B(PADAPTER padapter,
-+				     u8 *PROMContent, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseEEPROMVer_8710B(PADAPTER padapter,
-+				   u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParsePackageType_8710B(PADAPTER pAdapter,
-+				     u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseChnlPlan_8710B(PADAPTER padapter,
-+				  u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseCustomerID_8710B(PADAPTER padapter,
-+				    u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseAntennaDiversity_8710B(PADAPTER padapter,
-+		u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseXtal_8710B(PADAPTER pAdapter,
-+			      u8 *hwinfo, u8 AutoLoadFail);
-+void Hal_EfuseParseThermalMeter_8710B(PADAPTER padapter,
-+				      u8 *hwinfo, u8 AutoLoadFail);
-+void Hal_EfuseParseBoardType_8710B(PADAPTER Adapter,
-+				   u8	*PROMContent, BOOLEAN AutoloadFail);
-+#endif
-+
-+void rtl8710b_set_hal_ops(struct hal_ops *pHalFunc);
-+void init_hal_spec_8710b(_adapter *adapter);
-+u8 SetHwReg8710B(PADAPTER padapter, u8 variable, u8 *val);
-+void GetHwReg8710B(PADAPTER padapter, u8 variable, u8 *val);
-+u8 SetHalDefVar8710B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+u8 GetHalDefVar8710B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+
-+/* register */
-+void rtl8710b_InitBeaconParameters(PADAPTER padapter);
-+void rtl8710b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
-+void _8051Reset8710(PADAPTER padapter);
-+
-+void rtl8710b_start_thread(_adapter *padapter);
-+void rtl8710b_stop_thread(_adapter *padapter);
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
-+#endif
-+
-+void CCX_FwC2HTxRpt_8710b(PADAPTER padapter, u8 *pdata, u8 len);
-+
-+u8 MRateToHwRate8710B(u8 rate);
-+u8 HwRateToMRate8710B(u8 rate);
-+
-+#ifdef CONFIG_USB_HCI
-+	void rtl8710b_cal_txdesc_chksum(struct tx_desc *ptxdesc);
-+#endif
-+
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8710b_led.h b/drivers/staging/rtl8723cs/include/rtl8710b_led.h
-new file mode 100644
-index 000000000000..8ca346d7ad35
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8710b_led.h
-@@ -0,0 +1,44 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8710B_LED_H__
-+#define __RTL8710B_LED_H__
-+
-+#include <drv_conf.h>
-+#include <osdep_service.h>
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_RTW_SW_LED
-+/* ********************************************************************************
-+ * Interface to manipulate LED objects.
-+ * ******************************************************************************** */
-+#ifdef CONFIG_USB_HCI
-+	void rtl8710bu_InitSwLeds(PADAPTER padapter);
-+	void rtl8710bu_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_SDIO_HCI
-+	void rtl8710bs_InitSwLeds(PADAPTER padapter);
-+	void rtl8710bs_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_GSPI_HCI
-+	void rtl8710bs_InitSwLeds(PADAPTER padapter);
-+	void rtl8710bs_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+	void rtl8710be_InitSwLeds(PADAPTER padapter);
-+	void rtl8710be_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+
-+#endif /*#ifdef CONFIG_RTW_SW_LED*/
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8710b_lps_poff.h b/drivers/staging/rtl8723cs/include/rtl8710b_lps_poff.h
-new file mode 100644
-index 000000000000..ea9c60e8f700
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8710b_lps_poff.h
-@@ -0,0 +1,56 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/******************************************** CONST  ************************/
-+#define NUM_OF_REGISTER_BANK	13
-+#define NUM_OF_TOTAL_DWORD (NUM_OF_REGISTER_BANK * 64)
-+#define TOTAL_LEN_FOR_HIOE ((NUM_OF_TOTAL_DWORD + 1) * 8)
-+#define LPS_POFF_STATIC_FILE_LEN (TOTAL_LEN_FOR_HIOE + TXDESC_SIZE)
-+#define LPS_POFF_DYNAMIC_FILE_LEN	(512 + TXDESC_SIZE)
-+/******************************************** CONST  ************************/
-+
-+/******************************************** MACRO   ************************/
-+/* HOIE Entry Definition */
-+#define SET_HOIE_ENTRY_LOW_DATA(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE),	0, 16, __Value)
-+#define SET_HOIE_ENTRY_HIGH_DATA(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE), 16, 16, __Value)
-+#define SET_HOIE_ENTRY_MODE_SELECT(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 0, 1, __Value)
-+#define SET_HOIE_ENTRY_ADDRESS(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 1, 14, __Value)
-+#define SET_HOIE_ENTRY_BYTE_MASK(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 15, 4, __Value)
-+#define SET_HOIE_ENTRY_IO_LOCK(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 19, 1, __Value)
-+#define SET_HOIE_ENTRY_RD_EN(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 20, 1, __Value)
-+#define SET_HOIE_ENTRY_WR_EN(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 21, 1, __Value)
-+#define SET_HOIE_ENTRY_RAW_RW(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 22, 1, __Value)
-+#define SET_HOIE_ENTRY_RAW(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 23, 1, __Value)
-+#define SET_HOIE_ENTRY_IO_DELAY(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 24, 8, __Value)
-+
-+/*********************Function Definition*******************************************/
-+void rtl8710b_lps_poff_init(PADAPTER padapter);
-+void rtl8710b_lps_poff_deinit(PADAPTER padapter);
-+bool rtl8710b_lps_poff_get_txbndy_status(PADAPTER padapter);
-+void rtl8710b_lps_poff_h2c_ctrl(PADAPTER padapter, u8 enable);
-+void rtl8710b_lps_poff_set_ps_mode(PADAPTER padapter, bool bEnterLPS);
-+bool rtl8710b_lps_poff_get_status(PADAPTER padapter);
-+void rtl8710b_lps_poff_wow(PADAPTER padapter);
-diff --git a/drivers/staging/rtl8723cs/include/rtl8710b_recv.h b/drivers/staging/rtl8723cs/include/rtl8710b_recv.h
-new file mode 100644
-index 000000000000..ca0b8f8e75ae
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8710b_recv.h
-@@ -0,0 +1,81 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8710B_RECV_H__
-+#define __RTL8710B_RECV_H__
-+
-+#define RECV_BLK_SZ 512
-+#define RECV_BLK_CNT 16
-+#define RECV_BLK_TH RECV_BLK_CNT
-+
-+#if defined(CONFIG_USB_HCI)
-+	#ifndef MAX_RECVBUF_SZ
-+		#ifdef CONFIG_MINIMAL_MEMORY_USAGE
-+			#define MAX_RECVBUF_SZ (4000) /* about 4K */
-+		#else
-+			#ifdef CONFIG_PLATFORM_MSTAR
-+				#define MAX_RECVBUF_SZ (8192) /* 8K */
-+				#elif defined(CONFIG_PLATFORM_HISILICON)
-+				#define MAX_RECVBUF_SZ (16384) /* 16k */
-+			#else
-+				#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
-+				/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
-+				/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
-+				/* #define MAX_RECVBUF_SZ (10240)  */ /* 10K */
-+				/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
-+			#endif
-+		#endif
-+	#endif /* !MAX_RECVBUF_SZ */
-+#endif
-+
-+/* Rx smooth factor */
-+#define	Rx_Smooth_Factor (20)
-+
-+/*-----------------------------------------------------------------*/
-+/*	RTL8710B RX BUFFER DESC                                      */
-+/*-----------------------------------------------------------------*/
-+/*DWORD 0*/
-+#define SET_RX_BUFFER_DESC_DATA_LENGTH_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
-+#define SET_RX_BUFFER_DESC_LS_8710B(__pRxStatusDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
-+#define SET_RX_BUFFER_DESC_FS_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
-+#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
-+
-+#define GET_RX_BUFFER_DESC_OWN_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
-+#define GET_RX_BUFFER_DESC_LS_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
-+#define GET_RX_BUFFER_DESC_FS_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
-+#ifdef USING_RX_TAG
-+	#define GET_RX_BUFFER_DESC_RX_TAG_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)
-+#else
-+	#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8710B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
-+#endif
-+
-+/*DWORD 1*/
-+#define SET_RX_BUFFER_PHYSICAL_LOW_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
-+
-+/*DWORD 2*/
-+#ifdef CONFIG_64BIT_DMA
-+	#define SET_RX_BUFFER_PHYSICAL_HIGH_8710B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
-+#else
-+	#define SET_RX_BUFFER_PHYSICAL_HIGH_8710B(__pRxStatusDesc, __Value)
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	int rtl8710bu_init_recv_priv(_adapter *padapter);
-+	void rtl8710bu_free_recv_priv(_adapter *padapter);
-+	void rtl8710bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
-+#endif
-+
-+void rtl8710b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
-+
-+#endif /* __RTL8710B_RECV_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8710b_rf.h b/drivers/staging/rtl8723cs/include/rtl8710b_rf.h
-new file mode 100644
-index 000000000000..0b5cee616616
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8710b_rf.h
-@@ -0,0 +1,20 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8710B_RF_H__
-+#define __RTL8710B_RF_H__
-+
-+int PHY_RF6052_Config8710B(PADAPTER pdapter);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8710b_spec.h b/drivers/staging/rtl8723cs/include/rtl8710b_spec.h
-new file mode 100644
-index 000000000000..309c3eeb4362
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8710b_spec.h
-@@ -0,0 +1,481 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8710B_SPEC_H__
-+#define __RTL8710B_SPEC_H__
-+
-+#include <drv_conf.h>
-+
-+
-+#define HAL_NAV_UPPER_UNIT_8710B		128		/* micro-second */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0000h ~ 0x00FFh	System Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_SYS_ISO_CTRL_8710B			0x0000	/* 2 Byte */
-+#define REG_APS_FSMCO_8710B			0x0004	/* 4 Byte */
-+#define REG_SYS_CLKR_8710B				0x0008	/* 2 Byte */
-+#define REG_9346CR_8710B				0x000A	/* 2 Byte */
-+#define REG_EE_VPD_8710B				0x000C	/* 2 Byte */
-+#define REG_AFE_MISC_8710B				0x0010	/* 1 Byte */
-+#define REG_SPS0_CTRL_8710B				0x0011	/* 7 Byte */
-+#define REG_SPS_OCP_CFG_8710B			0x0018	/* 4 Byte */
-+#define REG_RSV_CTRL_8710B				0x001C	/* 3 Byte */
-+#define REG_RF_CTRL_8710B				0x001F	/* 1 Byte */
-+#define REG_LPLDO_CTRL_8710B			0x0023	/* 1 Byte */
-+#define REG_AFE_XTAL_CTRL_8710B		0x0024	/* 4 Byte */
-+#define REG_AFE_PLL_CTRL_8710B			0x0028	/* 4 Byte */
-+#define REG_MAC_PLL_CTRL_EXT_8710B		0x002c	/* 4 Byte */
-+#define REG_EFUSE_CTRL_8710B			0x0030
-+#define REG_EFUSE_TEST_8710B			0x0034
-+#define REG_PWR_DATA_8710B				0x0038
-+#define REG_CAL_TIMER_8710B				0x003C
-+#define REG_ACLK_MON_8710B				0x003E
-+#define REG_GPIO_MUXCFG_8710B			0x0040
-+#define REG_GPIO_IO_SEL_8710B			0x0042
-+#define REG_MAC_PINMUX_CFG_8710B		0x0043
-+#define REG_GPIO_PIN_CTRL_8710B			0x0044
-+#define REG_GPIO_INTM_8710B				0x0048
-+#define REG_LEDCFG0_8710B				0x004C
-+#define REG_LEDCFG1_8710B				0x004D
-+#define REG_LEDCFG2_8710B				0x004E
-+#define REG_LEDCFG3_8710B				0x004F
-+#define REG_FSIMR_8710B					0x0050
-+#define REG_FSISR_8710B					0x0054
-+#define REG_HSIMR_8710B					0x0058
-+#define REG_HSISR_8710B					0x005c
-+#define REG_GPIO_EXT_CTRL				0x0060
-+#define REG_PAD_CTRL1_8710B		0x0064
-+#define REG_MULTI_FUNC_CTRL_8710B		0x0068
-+#define REG_GPIO_STATUS_8710B			0x006C
-+#define REG_SDIO_CTRL_8710B				0x0070
-+#define REG_OPT_CTRL_8710B				0x0074
-+#define REG_AFE_CTRL_4_8710B		0x0078
-+#define REG_MCUFWDL_8710B				0x0080
-+#define REG_8051FW_CTRL_8710B			0x0080
-+#define REG_HMEBOX_DBG_0_8710B	0x0088
-+#define REG_HMEBOX_DBG_1_8710B	0x008A
-+#define REG_HMEBOX_DBG_2_8710B	0x008C
-+#define REG_HMEBOX_DBG_3_8710B	0x008E
-+#define REG_WLLPS_CTRL		0x0090
-+
-+#define REG_PMC_DBG_CTRL2_8710B			0x00CC
-+#define	REG_EFUSE_BURN_GNT_8710B		0x00CF
-+#define REG_HPON_FSM_8710B				0x00EC
-+#define REG_SYS_CFG1_8710B				0x00F0
-+#define REG_SYS_CFG_8710B				0x00FC
-+#define REG_ROM_VERSION					0x00FD
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_C2HEVT_CMD_ID_8710B	0x01A0
-+#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
-+#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
-+#define REG_C2HEVT_CMD_LEN_8710B        0x01AE
-+#define REG_C2HEVT_CLEAR_8710B			0x01AF
-+#define REG_MCUTST_1_8710B				0x01C0
-+#define REG_WOWLAN_WAKE_REASON 0x01C7
-+#define REG_FMETHR_8710B				0x01C8
-+#define REG_HMETFR_8710B				0x01CC
-+#define REG_HMEBOX_0_8710B				0x01D0
-+#define REG_HMEBOX_1_8710B				0x01D4
-+#define REG_HMEBOX_2_8710B				0x01D8
-+#define REG_HMEBOX_3_8710B				0x01DC
-+#define REG_LLT_INIT_8710B				0x01E0
-+#define REG_HMEBOX_EXT0_8710B			0x01F0
-+#define REG_HMEBOX_EXT1_8710B			0x01F4
-+#define REG_HMEBOX_EXT2_8710B			0x01F8
-+#define REG_HMEBOX_EXT3_8710B			0x01FC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_RQPN_8710B					0x0200
-+#define REG_FIFOPAGE_8710B				0x0204
-+#define REG_DWBCN0_CTRL_8710B			REG_TDECTRL
-+#define REG_TXDMA_OFFSET_CHK_8710B	0x020C
-+#define REG_TXDMA_STATUS_8710B		0x0210
-+#define REG_RQPN_NPQ_8710B			0x0214
-+#define REG_DWBCN1_CTRL_8710B			0x0228
-+
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_RXDMA_AGG_PG_TH_8710B		0x0280
-+#define REG_FW_UPD_RDPTR_8710B		0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
-+#define REG_RXDMA_CONTROL_8710B		0x0286 /* Control the RX DMA. */
-+#define REG_RXDMA_STATUS_8710B			0x0288
-+#define REG_RXDMA_MODE_CTRL_8710B		0x0290
-+#define REG_EARLY_MODE_CONTROL_8710B	0x02BC
-+#define REG_RSVD5_8710B					0x02F0
-+#define REG_RSVD6_8710B					0x02F4
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0300h ~ 0x03FFh	PCIe
-+ *
-+ * ----------------------------------------------------- */
-+#define	REG_PCIE_CTRL_REG_8710B			0x0300
-+#define	REG_INT_MIG_8710B				0x0304	/* Interrupt Migration */
-+#define	REG_BCNQ_TXBD_DESA_8710B		0x0308	/* TX Beacon Descriptor Address */
-+#define	REG_MGQ_TXBD_DESA_8710B			0x0310	/* TX Manage Queue Descriptor Address */
-+#define	REG_VOQ_TXBD_DESA_8710B			0x0318	/* TX VO Queue Descriptor Address */
-+#define	REG_VIQ_TXBD_DESA_8710B			0x0320	/* TX VI Queue Descriptor Address */
-+#define	REG_BEQ_TXBD_DESA_8710B			0x0328	/* TX BE Queue Descriptor Address */
-+#define	REG_BKQ_TXBD_DESA_8710B			0x0330	/* TX BK Queue Descriptor Address */
-+#define	REG_RXQ_RXBD_DESA_8710B			0x0338	/* RX Queue	Descriptor Address */
-+#define REG_HI0Q_TXBD_DESA_8710B		0x0340
-+#define REG_HI1Q_TXBD_DESA_8710B		0x0348
-+#define REG_HI2Q_TXBD_DESA_8710B		0x0350
-+#define REG_HI3Q_TXBD_DESA_8710B		0x0358
-+#define REG_HI4Q_TXBD_DESA_8710B		0x0360
-+#define REG_HI5Q_TXBD_DESA_8710B		0x0368
-+#define REG_HI6Q_TXBD_DESA_8710B		0x0370
-+#define REG_HI7Q_TXBD_DESA_8710B		0x0378
-+#define	REG_MGQ_TXBD_NUM_8710B			0x0380
-+#define	REG_RX_RXBD_NUM_8710B			0x0382
-+#define	REG_VOQ_TXBD_NUM_8710B			0x0384
-+#define	REG_VIQ_TXBD_NUM_8710B			0x0386
-+#define	REG_BEQ_TXBD_NUM_8710B			0x0388
-+#define	REG_BKQ_TXBD_NUM_8710B			0x038A
-+#define	REG_HI0Q_TXBD_NUM_8710B			0x038C
-+#define	REG_HI1Q_TXBD_NUM_8710B			0x038E
-+#define	REG_HI2Q_TXBD_NUM_8710B			0x0390
-+#define	REG_HI3Q_TXBD_NUM_8710B			0x0392
-+#define	REG_HI4Q_TXBD_NUM_8710B			0x0394
-+#define	REG_HI5Q_TXBD_NUM_8710B			0x0396
-+#define	REG_HI6Q_TXBD_NUM_8710B			0x0398
-+#define	REG_HI7Q_TXBD_NUM_8710B			0x039A
-+#define	REG_TSFTIMER_HCI_8710B			0x039C
-+#define	REG_BD_RW_PTR_CLR_8710B			0x039C
-+
-+/* Read Write Point */
-+#define	REG_VOQ_TXBD_IDX_8710B			0x03A0
-+#define	REG_VIQ_TXBD_IDX_8710B			0x03A4
-+#define	REG_BEQ_TXBD_IDX_8710B			0x03A8
-+#define	REG_BKQ_TXBD_IDX_8710B			0x03AC
-+#define	REG_MGQ_TXBD_IDX_8710B			0x03B0
-+#define	REG_RXQ_TXBD_IDX_8710B			0x03B4
-+#define	REG_HI0Q_TXBD_IDX_8710B			0x03B8
-+#define	REG_HI1Q_TXBD_IDX_8710B			0x03BC
-+#define	REG_HI2Q_TXBD_IDX_8710B			0x03C0
-+#define	REG_HI3Q_TXBD_IDX_8710B			0x03C4
-+#define	REG_HI4Q_TXBD_IDX_8710B			0x03C8
-+#define	REG_HI5Q_TXBD_IDX_8710B			0x03CC
-+#define	REG_HI6Q_TXBD_IDX_8710B			0x03D0
-+#define	REG_HI7Q_TXBD_IDX_8710B			0x03D4
-+
-+#define	REG_PCIE_HCPWM_8710BE			0x03D8 /* ?????? */
-+#define	REG_PCIE_HRPWM_8710BE			0x03DC	/* PCIe RPWM  ?????? */
-+#define	REG_DBI_WDATA_V1_8710B			0x03E8
-+#define	REG_DBI_RDATA_V1_8710B			0x03EC
-+#define	REG_DBI_FLAG_V1_8710B			0x03F0
-+#define REG_MDIO_V1_8710B				0x03F4
-+#define REG_PCIE_MIX_CFG_8710B			0x03F8
-+#define REG_HCI_MIX_CFG_8710B			0x03FC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0400h ~ 0x047Fh	Protocol Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_VOQ_INFORMATION_8710B		0x0400
-+#define REG_VIQ_INFORMATION_8710B		0x0404
-+#define REG_BEQ_INFORMATION_8710B		0x0408
-+#define REG_BKQ_INFORMATION_8710B		0x040C
-+#define REG_MGQ_INFORMATION_8710B		0x0410
-+#define REG_HGQ_INFORMATION_8710B		0x0414
-+#define REG_BCNQ_INFORMATION_8710B	0x0418
-+#define REG_TXPKT_EMPTY_8710B			0x041A
-+
-+#define REG_FWHW_TXQ_CTRL_8710B		0x0420
-+#define REG_HWSEQ_CTRL_8710B			0x0423
-+#define REG_TXPKTBUF_BCNQ_BDNY_8710B	0x0424
-+#define REG_TXPKTBUF_MGQ_BDNY_8710B	0x0425
-+#define REG_LIFECTRL_CTRL_8710B			0x0426
-+#define REG_MULTI_BCNQ_OFFSET_8710B	0x0427
-+#define REG_SPEC_SIFS_8710B				0x0428
-+#define REG_RL_8710B						0x042A
-+#define REG_TXBF_CTRL_8710B				0x042C
-+#define REG_DARFRC_8710B				0x0430
-+#define REG_RARFRC_8710B				0x0438
-+#define REG_RRSR_8710B					0x0440
-+#define REG_ARFR0_8710B					0x0444
-+#define REG_ARFR1_8710B					0x044C
-+#define REG_CCK_CHECK_8710B				0x0454
-+#define REG_AMPDU_MAX_TIME_8710B		0x0456
-+#define REG_TXPKTBUF_BCNQ_BDNY1_8710B	0x0457
-+
-+#define REG_AMPDU_MAX_LENGTH_8710B	0x0458
-+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8710B	0x045D
-+#define REG_NDPA_OPT_CTRL_8710B		0x045F
-+#define REG_FAST_EDCA_CTRL_8710B		0x0460
-+#define REG_RD_RESP_PKT_TH_8710B		0x0463
-+#define REG_DATA_SC_8710B				0x0483
-+#ifdef CONFIG_WOWLAN
-+	#define REG_TXPKTBUF_IV_LOW             0x0484
-+	#define REG_TXPKTBUF_IV_HIGH            0x0488
-+#endif
-+#define REG_TXRPT_START_OFFSET		0x04AC
-+#define REG_POWER_STAGE1_8710B		0x04B4
-+#define REG_POWER_STAGE2_8710B		0x04B8
-+#define REG_AMPDU_BURST_MODE_8710B	0x04BC
-+#define REG_PKT_VO_VI_LIFE_TIME_8710B	0x04C0
-+#define REG_PKT_BE_BK_LIFE_TIME_8710B	0x04C2
-+#define REG_STBC_SETTING_8710B			0x04C4
-+#define REG_HT_SINGLE_AMPDU_8710B		0x04C7
-+#define REG_PROT_MODE_CTRL_8710B		0x04C8
-+#define REG_MAX_AGGR_NUM_8710B		0x04CA
-+#define REG_RTS_MAX_AGGR_NUM_8710B	0x04CB
-+#define REG_BAR_MODE_CTRL_8710B		0x04CC
-+#define REG_RA_TRY_RATE_AGG_LMT_8710B	0x04CF
-+#define REG_MACID_PKT_DROP0_8710B		0x04D0
-+#define REG_MACID_PKT_SLEEP_8710B		0x04D4
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0500h ~ 0x05FFh	EDCA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_EDCA_VO_PARAM_8710B		0x0500
-+#define REG_EDCA_VI_PARAM_8710B		0x0504
-+#define REG_EDCA_BE_PARAM_8710B		0x0508
-+#define REG_EDCA_BK_PARAM_8710B		0x050C
-+#define REG_BCNTCFG_8710B				0x0510
-+#define REG_PIFS_8710B					0x0512
-+#define REG_RDG_PIFS_8710B				0x0513
-+#define REG_SIFS_CTX_8710B				0x0514
-+#define REG_SIFS_TRX_8710B				0x0516
-+#define REG_AGGR_BREAK_TIME_8710B		0x051A
-+#define REG_SLOT_8710B					0x051B
-+#define REG_TX_PTCL_CTRL_8710B			0x0520
-+#define REG_TXPAUSE_8710B				0x0522
-+#define REG_DIS_TXREQ_CLR_8710B		0x0523
-+#define REG_RD_CTRL_8710B				0x0524
-+/*
-+ * Format for offset 540h-542h:
-+ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
-+ *	[7:4]:   Reserved.
-+ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
-+ *	[23:20]: Reserved
-+ * Description:
-+ *	              |
-+ * |<--Setup--|--Hold------------>|
-+ *	--------------|----------------------
-+ * |
-+ * TBTT
-+ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
-+ * Described by Designer Tim and Bruce, 2011-01-14.
-+ *   */
-+#define REG_TBTT_PROHIBIT_8710B			0x0540
-+#define REG_RD_NAV_NXT_8710B			0x0544
-+#define REG_NAV_PROT_LEN_8710B			0x0546
-+#define REG_BCN_CTRL_8710B				0x0550
-+#define REG_BCN_CTRL_1_8710B			0x0551
-+#define REG_MBID_NUM_8710B				0x0552
-+#define REG_DUAL_TSF_RST_8710B			0x0553
-+#define REG_BCN_INTERVAL_8710B			0x0554
-+#define REG_DRVERLYINT_8710B			0x0558
-+#define REG_BCNDMATIM_8710B			0x0559
-+#define REG_ATIMWND_8710B				0x055A
-+#define REG_USTIME_TSF_8710B			0x055C
-+#define REG_BCN_MAX_ERR_8710B			0x055D
-+#define REG_RXTSF_OFFSET_CCK_8710B		0x055E
-+#define REG_RXTSF_OFFSET_OFDM_8710B	0x055F
-+#define REG_TSFTR_8710B					0x0560
-+#define REG_CTWND_8710B					0x0572
-+#define REG_SECONDARY_CCA_CTRL_8710B	0x0577
-+#define REG_PSTIMER_8710B				0x0580
-+#define REG_TIMER0_8710B				0x0584
-+#define REG_TIMER1_8710B				0x0588
-+#define REG_ACMHWCTRL_8710B			0x05C0
-+#define REG_SCH_TXCMD_8710B			0x05F8
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0600h ~ 0x07FFh	WMAC Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_MAC_CR_8710B				0x0600
-+#define REG_TCR_8710B					0x0604
-+#define REG_RCR_8710B					0x0608
-+#define REG_RX_PKT_LIMIT_8710B			0x060C
-+#define REG_RX_DLK_TIME_8710B			0x060D
-+#define REG_RX_DRVINFO_SZ_8710B		0x060F
-+
-+#define REG_MACID_8710B					0x0610
-+#define REG_BSSID_8710B					0x0618
-+#define REG_MAR_8710B					0x0620
-+#define REG_MBIDCAMCFG_8710B			0x0628
-+#define REG_WOWLAN_GTK_DBG1	0x630
-+#define REG_WOWLAN_GTK_DBG2	0x634
-+
-+#define REG_USTIME_EDCA_8710B			0x0638
-+#define REG_MAC_SPEC_SIFS_8710B		0x063A
-+#define REG_RESP_SIFP_CCK_8710B			0x063C
-+#define REG_RESP_SIFS_OFDM_8710B		0x063E
-+#define REG_ACKTO_8710B					0x0640
-+#define REG_CTS2TO_8710B				0x0641
-+#define REG_EIFS_8710B					0x0642
-+
-+#define REG_NAV_UPPER_8710B			0x0652	/* unit of 128 */
-+#define REG_TRXPTCL_CTL_8710B			0x0668
-+
-+/* Security */
-+#define REG_CAMCMD_8710B				0x0670
-+#define REG_CAMWRITE_8710B				0x0674
-+#define REG_CAMREAD_8710B				0x0678
-+#define REG_CAMDBG_8710B				0x067C
-+#define REG_SECCFG_8710B				0x0680
-+
-+/* Power */
-+#define REG_WOW_CTRL_8710B				0x0690
-+#define REG_PS_RX_INFO_8710B			0x0692
-+#define REG_UAPSD_TID_8710B				0x0693
-+#define REG_WKFMCAM_CMD_8710B			0x0698
-+#define REG_WKFMCAM_NUM_8710B			0x0698
-+#define REG_WKFMCAM_RWD_8710B			0x069C
-+#define REG_RXFLTMAP0_8710B				0x06A0
-+#define REG_RXFLTMAP1_8710B				0x06A2
-+#define REG_RXFLTMAP2_8710B				0x06A4
-+#define REG_BCN_PSR_RPT_8710B			0x06A8
-+#define REG_BT_COEX_TABLE_8710B		0x06C0
-+#define REG_BFMER0_INFO_8710B			0x06E4
-+#define REG_BFMER1_INFO_8710B			0x06EC
-+#define REG_CSI_RPT_PARAM_BW20_8710B	0x06F4
-+#define REG_CSI_RPT_PARAM_BW40_8710B	0x06F8
-+#define REG_CSI_RPT_PARAM_BW80_8710B	0x06FC
-+
-+/* Hardware Port 2 */
-+#define REG_MACID1_8710B				0x0700
-+#define REG_BSSID1_8710B				0x0708
-+#define REG_BFMEE_SEL_8710B				0x0714
-+#define REG_SND_PTCL_CTRL_8710B		0x0718
-+
-+/* LTR */
-+#define REG_LTR_CTRL_BASIC_8710B		0x07A4
-+#define REG_LTR_IDLE_LATENCY_V1_8710B		0x0798
-+#define REG_LTR_ACTIVE_LATENCY_V1_8710B		0x079C
-+
-+/* LTE_COEX */
-+#define REG_LTECOEX_CTRL			0x07C0
-+#define REG_LTECOEX_WRITE_DATA		0x07C4
-+#define REG_LTECOEX_READ_DATA		0x07C8
-+#define REG_LTECOEX_PATH_CONTROL	0x70
-+
-+/* Other */
-+#define REG_USB_ACCESS_TIMEOUT 0xFE4C
-+
-+/* -----------------------------------------------------
-+ * SYSON_REG_SPEC
-+ * ----------------------------------------------------- */
-+#define SYSON_REG_BASE_ADDR_8710B 0x40000000
-+#define REG_SYS_XTAL_CTRL0	0x0060
-+#define REG_SYS_SYSTEM_CFG0 0x1F0
-+#define REG_SYS_SYSTEM_CFG1 0x1F4
-+#define REG_SYS_SYSTEM_CFG2 0x1F8
-+#define REG_SYS_EEPROM_CTRL0 0x0E0
-+
-+
-+/* -----------------------------------------------------
-+ * Indirect_R/W_SPEC
-+ * ----------------------------------------------------- */
-+#define NORMAL_REG_READ_OFFSET 0x83000000
-+#define NORMAL_REG_WRITE_OFFSET 0x84000000
-+#define EFUSE_READ_OFFSET 0x85000000
-+#define EFUSE_WRITE_OFFSET 0x86000000
-+
-+
-+/* -----------------------------------------------------
-+ * PAGE0_WLANON_REG_SPEC
-+ * ----------------------------------------------------- */
-+#define PAGE0_OFFSET 0x0 // WLANON_PAGE0_REG needs to add an offset.
-+
-+
-+
-+/* ****************************************************************************
-+ *	8723 Regsiter Bit and Content definition
-+ * **************************************************************************** */
-+ 
-+ /* -----------------------------------------------------
-+ * REG_SYS_SYSTEM_CFG0 
-+ * ----------------------------------------------------- */
-+#define BIT_RTL_ID_8710B BIT(16)
-+
-+#define BIT_MASK_CHIP_VER_8710B 0xf
-+#define BIT_GET_CHIP_VER_8710B(x) ((x) & BIT_MASK_CHIP_VER_8710B)
-+
-+#define BIT_SHIFT_VENDOR_ID_8710B 4
-+#define BIT_MASK_VENDOR_ID_8710B 0xf
-+#define BIT_GET_VENDOR_ID_8710B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8710B) & BIT_MASK_VENDOR_ID_8710B)
-+
-+ /* -----------------------------------------------------
-+ * REG_SYS_SYSTEM_CFG1 
-+ * ----------------------------------------------------- */
-+#define BIT_SPSLDO_SEL_8710B BIT(25)
-+
-+ /* -----------------------------------------------------
-+ * REG_SYS_SYSTEM_CFG2 
-+ * ----------------------------------------------------- */
-+#define BIT_MASK_RF_RL_ID_8710B 0xf
-+#define BIT_GET_RF_RL_ID_8710B(x) ((x) & BIT_MASK_RF_RL_ID_8710B)
-+
-+ /* -----------------------------------------------------
-+ * REG_SYS_SYSTEM_CFG2 
-+ * ----------------------------------------------------- */
-+#define BIT_EERPOMSEL_8710B BIT(4)
-+#define BIT_AUTOLOAD_SUS_8710B BIT(5)
-+
-+
-+ /* -----------------------------------------------------
-+ * Other
-+ * ----------------------------------------------------- */
-+
-+
-+#define BIT_USB_RXDMA_AGG_EN	BIT(31)
-+#define RXDMA_AGG_MODE_EN		BIT(1)
-+
-+#ifdef CONFIG_WOWLAN
-+	#define RXPKT_RELEASE_POLL		BIT(16)
-+	#define RXDMA_IDLE				BIT(17)
-+	#define RW_RELEASE_EN			BIT(18)
-+#endif
-+
-+/* 2 HSISR
-+ * interrupt mask which needs to clear */
-+#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
-+		HSISR_SPS_OCP_INT |\
-+		HSISR_RON_INT |\
-+		HSISR_PDNINT |\
-+		HSISR_GPIO9_INT)
-+
-+#ifdef CONFIG_RF_POWER_TRIM
-+	#ifdef CONFIG_RTL8710B
-+		#define EEPROM_RF_GAIN_OFFSET			0xC1
-+	#endif
-+
-+	#define EEPROM_RF_GAIN_VAL				0x1F6
-+#endif /*CONFIG_RF_POWER_TRIM*/
-+
-+#endif /* __RTL8710B_SPEC_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8710b_sreset.h b/drivers/staging/rtl8723cs/include/rtl8710b_sreset.h
-new file mode 100644
-index 000000000000..ac5c64edd345
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8710b_sreset.h
-@@ -0,0 +1,24 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8710B_SRESET_H_
-+#define _RTL8710B_SRESET_H_
-+
-+#include <rtw_sreset.h>
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	extern void rtl8710b_sreset_xmit_status_check(_adapter *padapter);
-+	extern void rtl8710b_sreset_linked_status_check(_adapter *padapter);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8710b_xmit.h b/drivers/staging/rtl8723cs/include/rtl8710b_xmit.h
-new file mode 100644
-index 000000000000..b3ec6f58042e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8710b_xmit.h
-@@ -0,0 +1,523 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8710B_XMIT_H__
-+#define __RTL8710B_XMIT_H__
-+
-+
-+#define MAX_TID (15)
-+
-+
-+#ifndef __INC_HAL8710BDESC_H
-+#define __INC_HAL8710BDESC_H
-+
-+#define RX_STATUS_DESC_SIZE_8710B		24
-+#define RX_DRV_INFO_SIZE_UNIT_8710B 8
-+
-+
-+/* DWORD 0 */
-+#define SET_RX_STATUS_DESC_PKT_LEN_8710B(__pRxStatusDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
-+#define SET_RX_STATUS_DESC_EOR_8710B(__pRxStatusDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
-+#define SET_RX_STATUS_DESC_OWN_8710B(__pRxStatusDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
-+
-+#define GET_RX_STATUS_DESC_PKT_LEN_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
-+#define GET_RX_STATUS_DESC_CRC32_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
-+#define GET_RX_STATUS_DESC_ICV_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
-+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
-+#define GET_RX_STATUS_DESC_SECURITY_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
-+#define GET_RX_STATUS_DESC_QOS_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
-+#define GET_RX_STATUS_DESC_SHIFT_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
-+#define GET_RX_STATUS_DESC_PHY_STATUS_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
-+#define GET_RX_STATUS_DESC_SWDEC_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
-+#define GET_RX_STATUS_DESC_EOR_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
-+#define GET_RX_STATUS_DESC_OWN_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
-+
-+/* DWORD 1 */
-+#define GET_RX_STATUS_DESC_MACID_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
-+#define GET_RX_STATUS_DESC_TID_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
-+#define GET_RX_STATUS_DESC_AMSDU_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
-+#define GET_RX_STATUS_DESC_RXID_MATCH_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
-+#define GET_RX_STATUS_DESC_PAGGR_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
-+#define GET_RX_STATUS_DESC_A1_FIT_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
-+#define GET_RX_STATUS_DESC_CHKERR_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
-+#define GET_RX_STATUS_DESC_IPVER_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
-+#define GET_RX_STATUS_DESC_IS_TCPUDP__8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
-+#define GET_RX_STATUS_DESC_CHK_VLD_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
-+#define GET_RX_STATUS_DESC_PAM_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
-+#define GET_RX_STATUS_DESC_PWR_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
-+#define GET_RX_STATUS_DESC_MORE_DATA_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
-+#define GET_RX_STATUS_DESC_MORE_FRAG_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
-+#define GET_RX_STATUS_DESC_TYPE_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
-+#define GET_RX_STATUS_DESC_MC_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
-+#define GET_RX_STATUS_DESC_BC_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
-+
-+/* DWORD 2 */
-+#define GET_RX_STATUS_DESC_SEQ_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
-+#define GET_RX_STATUS_DESC_FRAG_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
-+#define GET_RX_STATUS_DESC_RX_IS_QOS_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
-+#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
-+#define GET_RX_STATUS_DESC_RPT_SEL_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
-+#define GET_RX_STATUS_DESC_FCS_OK_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
-+
-+/* DWORD 3 */
-+#define GET_RX_STATUS_DESC_RX_RATE_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
-+#define GET_RX_STATUS_DESC_HTC_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
-+#define GET_RX_STATUS_DESC_EOSP_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
-+#define GET_RX_STATUS_DESC_BSSID_FIT_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
-+#ifdef CONFIG_USB_RX_AGGREGATION
-+#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
-+#endif
-+#define GET_RX_STATUS_DESC_PATTERN_MATCH_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
-+#define GET_RX_STATUS_DESC_UNICAST_MATCH_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
-+#define GET_RX_STATUS_DESC_MAGIC_MATCH_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
-+
-+/* DWORD 6 */
-+#define GET_RX_STATUS_DESC_MATCH_ID_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)
-+
-+/* DWORD 5 */
-+#define GET_RX_STATUS_DESC_TSFL_8710B(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
-+
-+#define GET_RX_STATUS_DESC_BUFF_ADDR_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
-+#define GET_RX_STATUS_DESC_BUFF_ADDR64_8710B(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
-+
-+#define SET_RX_STATUS_DESC_BUFF_ADDR_8710B(__pRxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
-+
-+
-+/* Dword 0, rsvd: bit26, bit28 */
-+#define GET_TX_DESC_OWN_8710B(__pTxDesc)\
-+	LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
-+
-+#define SET_TX_DESC_PKT_SIZE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
-+#define SET_TX_DESC_OFFSET_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
-+#define SET_TX_DESC_BMC_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
-+#define SET_TX_DESC_HTC_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
-+#define SET_TX_DESC_AMSDU_PAD_EN_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
-+#define SET_TX_DESC_NO_ACM_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
-+#define SET_TX_DESC_GF_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
-+
-+/* Dword 1 */
-+#define SET_TX_DESC_MACID_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
-+#define SET_TX_DESC_QUEUE_SEL_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
-+#define SET_TX_DESC_RDG_NAV_EXT_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
-+#define SET_TX_DESC_LSIG_TXOP_EN_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
-+#define SET_TX_DESC_PIFS_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
-+#define SET_TX_DESC_RATE_ID_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
-+#define SET_TX_DESC_EN_DESC_ID_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
-+#define SET_TX_DESC_SEC_TYPE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
-+#define SET_TX_DESC_PKT_OFFSET_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
-+#define SET_TX_DESC_MORE_DATA_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
-+
-+/* Dword 2  remove P_AID, G_ID field*/
-+#define SET_TX_DESC_CCA_RTS_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
-+#define SET_TX_DESC_AGG_ENABLE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
-+#define SET_TX_DESC_RDG_ENABLE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
-+#define SET_TX_DESC_NULL0_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
-+#define SET_TX_DESC_NULL1_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
-+#define SET_TX_DESC_BK_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
-+#define SET_TX_DESC_MORE_FRAG_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
-+#define SET_TX_DESC_RAW_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
-+#define SET_TX_DESC_CCX_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
-+#define SET_TX_DESC_AMPDU_DENSITY_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
-+#define SET_TX_DESC_BT_INT_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
-+#define SET_TX_DESC_FTM_EN_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value)
-+
-+/* Dword 3 */
-+#define SET_TX_DESC_NAV_USE_HDR_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
-+#define SET_TX_DESC_HWSEQ_SEL_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
-+#define SET_TX_DESC_USE_RATE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
-+#define SET_TX_DESC_DISABLE_RTS_FB_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
-+#define SET_TX_DESC_DISABLE_FB_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
-+#define SET_TX_DESC_CTS2SELF_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
-+#define SET_TX_DESC_RTS_ENABLE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
-+#define SET_TX_DESC_HW_RTS_ENABLE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
-+#define SET_TX_DESC_PORT_ID_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value)
-+#define SET_TX_DESC_USE_MAX_LEN_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
-+#define SET_TX_DESC_MAX_AGG_NUM_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
-+#define SET_TX_DESC_AMPDU_MAX_TIME_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
-+
-+/* Dword 4 */
-+#define SET_TX_DESC_TX_RATE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
-+#define SET_TX_DESC_TX_TRY_RATE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
-+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
-+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
-+#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
-+#define SET_TX_DESC_DATA_RETRY_LIMIT_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
-+#define SET_TX_DESC_RTS_RATE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
-+#define SET_TX_DESC_PCTS_EN_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
-+#define SET_TX_DESC_PCTS_MASK_IDX_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
-+
-+/* Dword 5 */
-+#define SET_TX_DESC_DATA_SC_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
-+#define SET_TX_DESC_DATA_SHORT_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
-+#define SET_TX_DESC_DATA_BW_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
-+#define SET_TX_DESC_DATA_STBC_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
-+#define SET_TX_DESC_RTS_STBC_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
-+#define SET_TX_DESC_RTS_SHORT_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
-+#define SET_TX_DESC_RTS_SC_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
-+#define SET_TX_DESC_PATH_A_EN_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)
-+#define SET_TX_DESC_TXPWR_OF_SET_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
-+
-+/* Dword 6 */
-+#define SET_TX_DESC_SW_DEFINE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
-+#define SET_TX_DESC_MBSSID_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
-+#define SET_TX_DESC_RF_SEL_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
-+
-+/* Dword 7 */
-+#ifdef CONFIG_PCI_HCI
-+#define SET_TX_DESC_TX_BUFFER_SIZE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+#define SET_TX_DESC_TX_DESC_CHECKSUM_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+#endif
-+
-+#ifdef CONFIG_SDIO_HCI
-+#define SET_TX_DESC_TX_TIMESTAMP_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
-+#endif
-+
-+#define SET_TX_DESC_USB_TXAGG_NUM_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
-+
-+/* Dword 8 */
-+#define SET_TX_DESC_RTS_RC_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
-+#define SET_TX_DESC_BAR_RC_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
-+#define SET_TX_DESC_DATA_RC_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
-+#define SET_TX_DESC_HWSEQ_EN_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
-+#define SET_TX_DESC_NEXTHEADPAGE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
-+#define SET_TX_DESC_TAILPAGE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
-+
-+/* Dword 9 */
-+#define SET_TX_DESC_PADDING_LEN_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
-+#define SET_TX_DESC_SEQ_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
-+#define SET_TX_DESC_FINAL_DATA_RATE_8710B(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
-+
-+
-+#define SET_EARLYMODE_PKTNUM_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
-+#define SET_EARLYMODE_LEN0_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
-+#define SET_EARLYMODE_LEN1_1_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
-+#define SET_EARLYMODE_LEN1_2_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
-+#define SET_EARLYMODE_LEN2_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
-+#define SET_EARLYMODE_LEN3_8710B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
-+
-+
-+/*-----------------------------------------------------------------*/
-+/*	RTL8710B TX BUFFER DESC                                      */
-+/*-----------------------------------------------------------------*/
-+#ifdef CONFIG_64BIT_DMA
-+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
-+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
-+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
-+	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
-+#else
-+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
-+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
-+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
-+	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu)	/* 64 BIT mode only */
-+#endif
-+/* ********************************************************* */
-+
-+/* 64 bits  -- 32 bits */
-+/* =======     ======= */
-+/* Dword 0     0 */
-+#define SET_TX_BUFF_DESC_LEN_0_8710B(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
-+#define SET_TX_BUFF_DESC_PSB_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
-+#define SET_TX_BUFF_DESC_OWN_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
-+
-+/* Dword 1     1 */
-+#define SET_TX_BUFF_DESC_ADDR_LOW_0_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
-+#define GET_TX_BUFF_DESC_ADDR_LOW_0_8710B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
-+/* Dword 2     NA */
-+#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)
-+#ifdef CONFIG_64BIT_DMA
-+	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
-+#else
-+	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc) 0
-+#endif
-+/* Dword 3     NA */
-+/* RESERVED 0 */
-+/* Dword 4     2 */
-+#define SET_TX_BUFF_DESC_LEN_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)
-+#define SET_TX_BUFF_DESC_AMSDU_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)
-+/* Dword 5     3 */
-+#define SET_TX_BUFF_DESC_ADDR_LOW_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)
-+/* Dword 6     NA */
-+#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)
-+/* Dword 7     NA */
-+/*RESERVED 0 */
-+/* Dword 8     4 */
-+#define SET_TX_BUFF_DESC_LEN_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)
-+#define SET_TX_BUFF_DESC_AMSDU_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)
-+/* Dword 9     5 */
-+#define SET_TX_BUFF_DESC_ADDR_LOW_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)
-+/* Dword 10    NA */
-+#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)
-+/* Dword 11    NA */
-+/*RESERVED 0 */
-+/* Dword 12    6 */
-+#define SET_TX_BUFF_DESC_LEN_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)
-+#define SET_TX_BUFF_DESC_AMSDU_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)
-+/* Dword 13    7 */
-+#define SET_TX_BUFF_DESC_ADDR_LOW_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)
-+/* Dword 14    NA */
-+#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)
-+/* Dword 15    NA */
-+/*RESERVED 0 */
-+
-+
-+#endif
-+/* -----------------------------------------------------------
-+ *
-+ *	Rate
-+ *
-+ * -----------------------------------------------------------
-+ * CCK Rates, TxHT = 0 */
-+#define DESC8710B_RATE1M				0x00
-+#define DESC8710B_RATE2M				0x01
-+#define DESC8710B_RATE5_5M				0x02
-+#define DESC8710B_RATE11M				0x03
-+
-+/* OFDM Rates, TxHT = 0 */
-+#define DESC8710B_RATE6M				0x04
-+#define DESC8710B_RATE9M				0x05
-+#define DESC8710B_RATE12M				0x06
-+#define DESC8710B_RATE18M				0x07
-+#define DESC8710B_RATE24M				0x08
-+#define DESC8710B_RATE36M				0x09
-+#define DESC8710B_RATE48M				0x0a
-+#define DESC8710B_RATE54M				0x0b
-+
-+/* MCS Rates, TxHT = 1 */
-+#define DESC8710B_RATEMCS0				0x0c
-+#define DESC8710B_RATEMCS1				0x0d
-+#define DESC8710B_RATEMCS2				0x0e
-+#define DESC8710B_RATEMCS3				0x0f
-+#define DESC8710B_RATEMCS4				0x10
-+#define DESC8710B_RATEMCS5				0x11
-+#define DESC8710B_RATEMCS6				0x12
-+#define DESC8710B_RATEMCS7				0x13
-+#define DESC8710B_RATEMCS8				0x14
-+#define DESC8710B_RATEMCS9				0x15
-+#define DESC8710B_RATEMCS10		0x16
-+#define DESC8710B_RATEMCS11		0x17
-+#define DESC8710B_RATEMCS12		0x18
-+#define DESC8710B_RATEMCS13		0x19
-+#define DESC8710B_RATEMCS14		0x1a
-+#define DESC8710B_RATEMCS15		0x1b
-+#define DESC8710B_RATEVHTSS1MCS0		0x2c
-+#define DESC8710B_RATEVHTSS1MCS1		0x2d
-+#define DESC8710B_RATEVHTSS1MCS2		0x2e
-+#define DESC8710B_RATEVHTSS1MCS3		0x2f
-+#define DESC8710B_RATEVHTSS1MCS4		0x30
-+#define DESC8710B_RATEVHTSS1MCS5		0x31
-+#define DESC8710B_RATEVHTSS1MCS6		0x32
-+#define DESC8710B_RATEVHTSS1MCS7		0x33
-+#define DESC8710B_RATEVHTSS1MCS8		0x34
-+#define DESC8710B_RATEVHTSS1MCS9		0x35
-+#define DESC8710B_RATEVHTSS2MCS0		0x36
-+#define DESC8710B_RATEVHTSS2MCS1		0x37
-+#define DESC8710B_RATEVHTSS2MCS2		0x38
-+#define DESC8710B_RATEVHTSS2MCS3		0x39
-+#define DESC8710B_RATEVHTSS2MCS4		0x3a
-+#define DESC8710B_RATEVHTSS2MCS5		0x3b
-+#define DESC8710B_RATEVHTSS2MCS6		0x3c
-+#define DESC8710B_RATEVHTSS2MCS7		0x3d
-+#define DESC8710B_RATEVHTSS2MCS8		0x3e
-+#define DESC8710B_RATEVHTSS2MCS9		0x3f
-+
-+
-+#define	RX_HAL_IS_CCK_RATE_8710B(pDesc)\
-+	(GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE1M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE2M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE5_5M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE11M)
-+
-+#ifdef CONFIG_TRX_BD_ARCH
-+	struct tx_desc;
-+#endif
-+
-+void rtl8710b_cal_txdesc_chksum(struct tx_desc *ptxdesc);
-+void rtl8710b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
-+void rtl8710b_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
-+void rtl8710b_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
-+void rtl8710b_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
-+void rtl8710b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
-+
-+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	s32 rtl8710bs_init_xmit_priv(PADAPTER padapter);
-+	void rtl8710bs_free_xmit_priv(PADAPTER padapter);
-+	s32 rtl8710bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8710bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+	s32	rtl8710bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8710bs_xmit_buf_handler(PADAPTER padapter);
-+	thread_return rtl8710bs_xmit_thread(thread_context context);
-+	#define hal_xmit_handler rtl8710bs_xmit_buf_handler
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	s32 rtl8710bu_xmit_buf_handler(PADAPTER padapter);
-+	#define hal_xmit_handler rtl8710bu_xmit_buf_handler
-+	s32 rtl8710bu_init_xmit_priv(PADAPTER padapter);
-+	void rtl8710bu_free_xmit_priv(PADAPTER padapter);
-+	s32 rtl8710bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8710bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8710bu_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	 rtl8710bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	void rtl8710bu_xmit_tasklet(void *priv);
-+	s32 rtl8710bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+	void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8710be_init_xmit_priv(PADAPTER padapter);
-+	void rtl8710be_free_xmit_priv(PADAPTER padapter);
-+	struct xmit_buf *rtl8710be_dequeue_xmitbuf(struct rtw_tx_ring *ring);
-+	void	rtl8710be_xmitframe_resume(_adapter *padapter);
-+	s32 rtl8710be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8710be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+	s32	rtl8710be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	void rtl8710be_xmit_tasklet(void *priv);
-+#endif
-+
-+u8	BWMapping_8710B(PADAPTER Adapter, struct pkt_attrib *pattrib);
-+u8	SCMapping_8710B(PADAPTER Adapter, struct pkt_attrib	*pattrib);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723b_cmd.h b/drivers/staging/rtl8723cs/include/rtl8723b_cmd.h
-new file mode 100644
-index 000000000000..d4da95640791
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723b_cmd.h
-@@ -0,0 +1,199 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723B_CMD_H__
-+#define __RTL8723B_CMD_H__
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+enum h2c_cmd_8723B {
-+	/* Common Class: 000 */
-+	H2C_8723B_RSVD_PAGE = 0x00,
-+	H2C_8723B_MEDIA_STATUS_RPT = 0x01,
-+	H2C_8723B_SCAN_ENABLE = 0x02,
-+	H2C_8723B_KEEP_ALIVE = 0x03,
-+	H2C_8723B_DISCON_DECISION = 0x04,
-+	H2C_8723B_PSD_OFFLOAD = 0x05,
-+	H2C_8723B_AP_OFFLOAD = 0x08,
-+	H2C_8723B_BCN_RSVDPAGE = 0x09,
-+	H2C_8723B_PROBERSP_RSVDPAGE = 0x0A,
-+	H2C_8723B_FCS_RSVDPAGE = 0x10,
-+	H2C_8723B_FCS_INFO = 0x11,
-+	H2C_8723B_AP_WOW_GPIO_CTRL = 0x13,
-+
-+	/* PoweSave Class: 001 */
-+	H2C_8723B_SET_PWR_MODE = 0x20,
-+	H2C_8723B_PS_TUNING_PARA = 0x21,
-+	H2C_8723B_PS_TUNING_PARA2 = 0x22,
-+	H2C_8723B_P2P_LPS_PARAM = 0x23,
-+	H2C_8723B_P2P_PS_OFFLOAD = 0x24,
-+	H2C_8723B_PS_SCAN_ENABLE = 0x25,
-+	H2C_8723B_SAP_PS_ = 0x26,
-+	H2C_8723B_INACTIVE_PS_ = 0x27, /* Inactive_PS */
-+	H2C_8723B_FWLPS_IN_IPS_ = 0x28,
-+
-+	/* Dynamic Mechanism Class: 010 */
-+	H2C_8723B_MACID_CFG = 0x40,
-+	H2C_8723B_TXBF = 0x41,
-+	H2C_8723B_RSSI_SETTING = 0x42,
-+	H2C_8723B_AP_REQ_TXRPT = 0x43,
-+	H2C_8723B_INIT_RATE_COLLECT = 0x44,
-+	H2C_8723B_RA_PARA_ADJUST = 0x46,
-+
-+	/* BT Class: 011 */
-+	H2C_8723B_B_TYPE_TDMA = 0x60,
-+	H2C_8723B_BT_INFO = 0x61,
-+	H2C_8723B_FORCE_BT_TXPWR = 0x62,
-+	H2C_8723B_BT_IGNORE_WLANACT = 0x63,
-+	H2C_8723B_DAC_SWING_VALUE = 0x64,
-+	H2C_8723B_ANT_SEL_RSV = 0x65,
-+	H2C_8723B_WL_OPMODE = 0x66,
-+	H2C_8723B_BT_MP_OPER = 0x67,
-+	H2C_8723B_BT_CONTROL = 0x68,
-+	H2C_8723B_BT_WIFI_CTRL = 0x69,
-+	H2C_8723B_BT_FW_PATCH = 0x6A,
-+	H2C_8723B_BT_WLAN_CALIBRATION = 0x6D,
-+
-+	/* WOWLAN Class: 100 */
-+	H2C_8723B_WOWLAN = 0x80,
-+	H2C_8723B_REMOTE_WAKE_CTRL = 0x81,
-+	H2C_8723B_AOAC_GLOBAL_INFO = 0x82,
-+	H2C_8723B_AOAC_RSVD_PAGE = 0x83,
-+	H2C_8723B_AOAC_RSVD_PAGE2 = 0x84,
-+	H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85,
-+	H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86,
-+	H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87,
-+	H2C_8723B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
-+	H2C_8723B_P2P_OFFLOAD = 0x8B,
-+
-+	H2C_8723B_RESET_TSF = 0xC0,
-+	H2C_8723B_MAXID,
-+};
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
-+ * ---------------------------------------------------------------------------------------------------------
-+ * _RSVDPAGE_LOC_CMD_0x00 */
-+#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+/* _KEEP_ALIVE_CMD_0x03 */
-+#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_8723B_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_8723B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+
-+/* _DISCONNECT_DECISION_CMD_0x04 */
-+#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_8723B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
-+
-+/* _PWR_MOD_CMD_0x20 */
-+#define SET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
-+#define SET_8723B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
-+#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
-+#define SET_8723B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+#define GET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
-+
-+/* _PS_TUNE_PARAM_CMD_0x21 */
-+#define SET_8723B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
-+#define SET_8723B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
-+#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+
-+/* _MACID_CFG_CMD_0x40 */
-+#define SET_8723B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
-+#define SET_8723B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
-+#define SET_8723B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
-+#define SET_8723B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
-+#define SET_8723B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
-+#define SET_8723B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
-+#define SET_8723B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
-+#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
-+
-+/* _RSSI_SETTING_CMD_0x42 */
-+#define SET_8723B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
-+#define SET_8723B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+
-+/* _AP_REQ_TXRPT_CMD_0x43 */
-+#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+
-+/* _FORCE_BT_TXPWR_CMD_0x62 */
-+#define SET_8723B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+
-+/* _FORCE_BT_MP_OPER_CMD_0x67 */
-+#define SET_8723B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
-+#define SET_8723B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
-+#define SET_8723B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
-+
-+/* _BT_FW_PATCH_0x6A */
-+#define SET_8723B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
-+#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * -------------------------------------------    Structure    --------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    Function Statement     --------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+/* host message to firmware cmd */
-+void rtl8723b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
-+void rtl8723b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
-+void rtl8723b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
-+/* s32 rtl8723b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
-+void rtl8723b_set_FwPsTuneParam_cmd(PADAPTER padapter);
-+void rtl8723b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
-+void rtl8723b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
-+#ifdef CONFIG_BT_COEXIST
-+	void rtl8723b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
-+#endif /* CONFIG_BT_COEXIST */
-+#ifdef CONFIG_P2P
-+	void rtl8723b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
-+#endif /* CONFIG_P2P */
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+	void rtl8723b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
-+#endif
-+
-+void rtl8723b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
-+
-+s32 FillH2CCmd8723B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
-+u8 GetTxBufferRsvdPageNum8723B(_adapter *padapter, bool wowlan);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723b_dm.h b/drivers/staging/rtl8723cs/include/rtl8723b_dm.h
-new file mode 100644
-index 000000000000..ea517175f0bd
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723b_dm.h
-@@ -0,0 +1,38 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723B_DM_H__
-+#define __RTL8723B_DM_H__
-+/* ************************************************************
-+ * Description:
-+ *
-+ * This file is for 8723B dynamic mechanism only
-+ *
-+ *
-+ * ************************************************************ */
-+
-+/* ************************************************************
-+ * structure and define
-+ * ************************************************************ */
-+
-+/* ************************************************************
-+ * function prototype
-+ * ************************************************************ */
-+
-+void rtl8723b_init_dm_priv(PADAPTER padapter);
-+void rtl8723b_deinit_dm_priv(PADAPTER padapter);
-+
-+void rtl8723b_InitHalDm(PADAPTER padapter);
-+void rtl8723b_HalDmWatchDog(PADAPTER padapter);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723b_hal.h b/drivers/staging/rtl8723cs/include/rtl8723b_hal.h
-new file mode 100644
-index 000000000000..8483502464b8
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723b_hal.h
-@@ -0,0 +1,274 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723B_HAL_H__
-+#define __RTL8723B_HAL_H__
-+
-+#include "hal_data.h"
-+
-+#include "rtl8723b_spec.h"
-+#include "rtl8723b_rf.h"
-+#include "rtl8723b_dm.h"
-+#include "rtl8723b_recv.h"
-+#include "rtl8723b_xmit.h"
-+#include "rtl8723b_cmd.h"
-+#include "rtl8723b_led.h"
-+#include "Hal8723BPwrSeq.h"
-+#include "Hal8723BPhyReg.h"
-+#include "Hal8723BPhyCfg.h"
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	#include "rtl8723b_sreset.h"
-+#endif
-+
-+#define FW_8723B_SIZE			0x8000
-+#define FW_8723B_START_ADDRESS	0x1000
-+#define FW_8723B_END_ADDRESS		0x1FFF /* 0x5FFF */
-+
-+#define IS_FW_HEADER_EXIST_8723B(_pFwHdr)	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x5300)
-+
-+typedef struct _RT_FIRMWARE {
-+	FIRMWARE_SOURCE	eFWSource;
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+	u8			*szFwBuffer;
-+#else
-+	u8			szFwBuffer[FW_8723B_SIZE];
-+#endif
-+	u32			ulFwLength;
-+} RT_FIRMWARE_8723B, *PRT_FIRMWARE_8723B;
-+
-+/*
-+ * This structure must be cared byte-ordering
-+ *
-+ * Added by tynli. 2009.12.04. */
-+typedef struct _RT_8723B_FIRMWARE_HDR {
-+	/* 8-byte alinment required */
-+
-+	/* --- LONG WORD 0 ---- */
-+	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
-+	u8		Category;	/* AP/NIC and USB/PCI */
-+	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
-+	u16		Version;		/* FW Version */
-+	u16		Subversion;	/* FW Subversion, default 0x00 */
-+
-+	/* --- LONG WORD 1 ---- */
-+	u8		Month;	/* Release time Month field */
-+	u8		Date;	/* Release time Date field */
-+	u8		Hour;	/* Release time Hour field */
-+	u8		Minute;	/* Release time Minute field */
-+	u16		RamCodeSize;	/* The size of RAM code */
-+	u16		Rsvd2;
-+
-+	/* --- LONG WORD 2 ---- */
-+	u32		SvnIdx;	/* The SVN entry index */
-+	u32		Rsvd3;
-+
-+	/* --- LONG WORD 3 ---- */
-+	u32		Rsvd4;
-+	u32		Rsvd5;
-+} RT_8723B_FIRMWARE_HDR, *PRT_8723B_FIRMWARE_HDR;
-+
-+#define DRIVER_EARLY_INT_TIME_8723B		0x05
-+#define BCN_DMA_ATIME_INT_TIME_8723B		0x02
-+
-+/* for 8723B
-+ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
-+#define PAGE_SIZE_TX_8723B			128
-+#define PAGE_SIZE_RX_8723B			8
-+
-+#define TX_DMA_SIZE_8723B			0x8000	/* 32K(TX) */
-+#define RX_DMA_SIZE_8723B			0x4000	/* 16K(RX) */
-+
-+#ifdef CONFIG_WOWLAN
-+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
-+#else
-+	#define RESV_FMWF	0
-+#endif
-+
-+#ifdef CONFIG_FW_C2H_DEBUG
-+	#define RX_DMA_RESERVED_SIZE_8723B	0x100	/* 256B, reserved for c2h debug message */
-+#else
-+	#define RX_DMA_RESERVED_SIZE_8723B	0x80	/* 128B, reserved for tx report */
-+#endif
-+#define RX_DMA_BOUNDARY_8723B		(RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B - 1)
-+
-+
-+/* Note: We will divide number of page equally for each queue other than public queue! */
-+
-+/* For General Reserved Page Number(Beacon Queue is reserved page)
-+ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8723B
-+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
-+#define BCNQ_PAGE_NUM_8723B		(MAX_BEACON_LEN / PAGE_SIZE_TX_8723B + 6) /*0x08*/
-+
-+
-+/* For WoWLan , more reserved page
-+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6
-+ * NS offload: 2 NDP info: 1
-+ */
-+#ifdef CONFIG_WOWLAN
-+	#define WOWLAN_PAGE_NUM_8723B	0x0b
-+#else
-+	#define WOWLAN_PAGE_NUM_8723B	0x00
-+#endif
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+	#undef WOWLAN_PAGE_NUM_8723B
-+	#define WOWLAN_PAGE_NUM_8723B	0x15
-+#endif
-+
-+#ifdef CONFIG_AP_WOWLAN
-+	#define AP_WOWLAN_PAGE_NUM_8723B	0x02
-+#endif
-+
-+#define TX_TOTAL_PAGE_NUMBER_8723B	(0xFF - BCNQ_PAGE_NUM_8723B - WOWLAN_PAGE_NUM_8723B)
-+#define TX_PAGE_BOUNDARY_8723B		(TX_TOTAL_PAGE_NUMBER_8723B + 1)
-+
-+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B	TX_TOTAL_PAGE_NUMBER_8723B
-+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8723B		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B + 1)
-+
-+/* For Normal Chip Setting
-+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723B */
-+#define NORMAL_PAGE_NUM_HPQ_8723B		0x0C
-+#define NORMAL_PAGE_NUM_LPQ_8723B		0x02
-+#define NORMAL_PAGE_NUM_NPQ_8723B		0x02
-+#define NORMAL_PAGE_NUM_EPQ_8723B		0x04
-+
-+/* Note: For Normal Chip Setting, modify later */
-+#define WMM_NORMAL_PAGE_NUM_HPQ_8723B		0x30
-+#define WMM_NORMAL_PAGE_NUM_LPQ_8723B		0x20
-+#define WMM_NORMAL_PAGE_NUM_NPQ_8723B		0x20
-+#define WMM_NORMAL_PAGE_NUM_EPQ_8723B		0x00
-+
-+
-+#include "HalVerDef.h"
-+#include "hal_com.h"
-+
-+#define EFUSE_OOB_PROTECT_BYTES		15
-+
-+#define HAL_EFUSE_MEMORY
-+
-+#define HWSET_MAX_SIZE_8723B			512
-+#define EFUSE_REAL_CONTENT_LEN_8723B		512
-+#define EFUSE_MAP_LEN_8723B				512
-+#define EFUSE_MAX_SECTION_8723B			64
-+
-+#define EFUSE_IC_ID_OFFSET			506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
-+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8723B)
-+
-+#define EFUSE_ACCESS_ON			0x69	/* For RTL8723 only. */
-+#define EFUSE_ACCESS_OFF			0x00	/* For RTL8723 only. */
-+
-+/* ********************************************************
-+ *			EFUSE for BT definition
-+ * ******************************************************** */
-+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
-+#define EFUSE_BT_REAL_CONTENT_LEN		1536	/* 512*3 */
-+#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
-+#define EFUSE_BT_MAX_SECTION			128		/* 1024/8 */
-+
-+#define EFUSE_PROTECT_BYTES_BANK		16
-+
-+typedef enum tag_Package_Definition {
-+	PACKAGE_DEFAULT,
-+	PACKAGE_QFN68,
-+	PACKAGE_TFBGA90,
-+	PACKAGE_TFBGA80,
-+	PACKAGE_TFBGA79
-+} PACKAGE_TYPE_E;
-+
-+#define INCLUDE_MULTI_FUNC_BT(_Adapter)		(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
-+#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
-+
-+/* rtl8723a_hal_init.c */
-+s32 rtl8723b_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
-+void rtl8723b_FirmwareSelfReset(PADAPTER padapter);
-+void rtl8723b_InitializeFirmwareVars(PADAPTER padapter);
-+
-+void rtl8723b_InitAntenna_Selection(PADAPTER padapter);
-+void rtl8723b_DeinitAntenna_Selection(PADAPTER padapter);
-+void rtl8723b_CheckAntenna_Selection(PADAPTER padapter);
-+void rtl8723b_init_default_value(PADAPTER padapter);
-+
-+s32 rtl8723b_InitLLTTable(PADAPTER padapter);
-+
-+s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
-+s32 CardDisableWithoutHWSM(PADAPTER padapter);
-+
-+/* EFuse */
-+u8 GetEEPROMSize8723B(PADAPTER padapter);
-+void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
-+void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
-+void Hal_EfuseParseTxPowerInfo_8723B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseBTCoexistInfo_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseEEPROMVer_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseChnlPlan_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseCustomerID_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseAntennaDiversity_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseXtal_8723B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
-+void Hal_EfuseParseThermalMeter_8723B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
-+void Hal_EfuseParsePackageType_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseVoltage_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
-+void Hal_EfuseParseBoardType_8723B(PADAPTER Adapter,	u8	*PROMContent, BOOLEAN AutoloadFail);
-+
-+void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc);
-+void init_hal_spec_8723b(_adapter *adapter);
-+u8 SetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val);
-+void GetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val);
-+u8 SetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+u8 GetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+
-+/* register */
-+void rtl8723b_InitBeaconParameters(PADAPTER padapter);
-+void rtl8723b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
-+void	_InitBurstPktLen_8723BS(PADAPTER Adapter);
-+void _8051Reset8723(PADAPTER padapter);
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+	void Hal_DetectWoWMode(PADAPTER pAdapter);
-+#endif /* CONFIG_WOWLAN */
-+
-+void rtl8723b_start_thread(_adapter *padapter);
-+void rtl8723b_stop_thread(_adapter *padapter);
-+
-+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
-+	void rtl8723bs_init_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8723bs_free_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8723bs_cancle_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8723bs_hal_check_bt_hang(_adapter *adapter);
-+#endif
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
-+#endif
-+#ifdef CONFIG_MP_INCLUDED
-+int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
-+#endif
-+void CCX_FwC2HTxRpt_8723b(PADAPTER padapter, u8 *pdata, u8 len);
-+
-+u8 MRateToHwRate8723B(u8  rate);
-+u8 HwRateToMRate8723B(u8	 rate);
-+
-+#ifdef CONFIG_RF_POWER_TRIM
-+	void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+#endif /*CONFIG_RF_POWER_TRIM*/
-+
-+#ifdef CONFIG_PCI_HCI
-+	BOOLEAN	InterruptRecognized8723BE(PADAPTER Adapter);
-+	void	UpdateInterruptMask8723BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
-+#endif
-+
-+#ifdef CONFIG_GPIO_API
-+int rtl8723b_GpioFuncCheck(PADAPTER adapter, u8 gpio_num);
-+void rtl8723b_GpioMultiFuncReset(PADAPTER adapter, u8 gpio_num);
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723b_led.h b/drivers/staging/rtl8723cs/include/rtl8723b_led.h
-new file mode 100644
-index 000000000000..6b772cceb7ec
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723b_led.h
-@@ -0,0 +1,44 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723B_LED_H__
-+#define __RTL8723B_LED_H__
-+
-+#include <drv_conf.h>
-+#include <osdep_service.h>
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_RTW_SW_LED
-+/* ********************************************************************************
-+ * Interface to manipulate LED objects.
-+ * ******************************************************************************** */
-+#ifdef CONFIG_USB_HCI
-+	void rtl8723bu_InitSwLeds(PADAPTER padapter);
-+	void rtl8723bu_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_SDIO_HCI
-+	void rtl8723bs_InitSwLeds(PADAPTER padapter);
-+	void rtl8723bs_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_GSPI_HCI
-+	void rtl8723bs_InitSwLeds(PADAPTER padapter);
-+	void rtl8723bs_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+	void rtl8723be_InitSwLeds(PADAPTER padapter);
-+	void rtl8723be_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+
-+#endif
-+#endif/*CONFIG_RTW_SW_LED*/
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723b_recv.h b/drivers/staging/rtl8723cs/include/rtl8723b_recv.h
-new file mode 100644
-index 000000000000..5e92713a5522
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723b_recv.h
-@@ -0,0 +1,82 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723B_RECV_H__
-+#define __RTL8723B_RECV_H__
-+
-+#define RECV_BLK_SZ 512
-+#define RECV_BLK_CNT 16
-+#define RECV_BLK_TH RECV_BLK_CNT
-+
-+#if defined(CONFIG_USB_HCI)
-+
-+	#ifndef MAX_RECVBUF_SZ
-+		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
-+			/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
-+			/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
-+			/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
-+			#ifdef CONFIG_PLATFORM_MSTAR
-+				#define MAX_RECVBUF_SZ (8192) /* 8K */
-+			#else
-+				#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
-+			#endif
-+			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
-+		#else
-+			#define MAX_RECVBUF_SZ (4000) /* about 4K */
-+		#endif
-+	#endif /* !MAX_RECVBUF_SZ */
-+
-+#elif defined(CONFIG_PCI_HCI)
-+	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
-+	/*	#define MAX_RECVBUF_SZ (9100) */
-+	/* #else */
-+	#define MAX_RECVBUF_SZ (4000) /* about 4K
-+	* #endif */
-+
-+
-+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+
-+	#define MAX_RECVBUF_SZ  (RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B)
-+
-+#endif
-+
-+/* Rx smooth factor */
-+#define	Rx_Smooth_Factor (20)
-+
-+#ifdef CONFIG_SDIO_HCI
-+	#ifndef CONFIG_SDIO_RX_COPY
-+		#undef MAX_RECVBUF_SZ
-+		#define MAX_RECVBUF_SZ	(RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B)
-+	#endif /* !CONFIG_SDIO_RX_COPY */
-+#endif /* CONFIG_SDIO_HCI */
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	s32 rtl8723bs_init_recv_priv(PADAPTER padapter);
-+	void rtl8723bs_free_recv_priv(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	int rtl8723bu_init_recv_priv(_adapter *padapter);
-+	void rtl8723bu_free_recv_priv(_adapter *padapter);
-+	void rtl8723bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8723be_init_recv_priv(PADAPTER padapter);
-+	void rtl8723be_free_recv_priv(PADAPTER padapter);
-+#endif
-+
-+void rtl8723b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
-+
-+#endif /* __RTL8723B_RECV_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723b_rf.h b/drivers/staging/rtl8723cs/include/rtl8723b_rf.h
-new file mode 100644
-index 000000000000..040c16647f33
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723b_rf.h
-@@ -0,0 +1,25 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723B_RF_H__
-+#define __RTL8723B_RF_H__
-+
-+int	PHY_RF6052_Config8723B(PADAPTER		Adapter);
-+
-+void
-+PHY_RF6052SetBandwidth8723B(
-+		PADAPTER				Adapter,
-+		enum channel_width		Bandwidth);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723b_spec.h b/drivers/staging/rtl8723cs/include/rtl8723b_spec.h
-new file mode 100644
-index 000000000000..b0fb4aa41d17
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723b_spec.h
-@@ -0,0 +1,280 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723B_SPEC_H__
-+#define __RTL8723B_SPEC_H__
-+
-+#include <drv_conf.h>
-+
-+
-+#define HAL_NAV_UPPER_UNIT_8723B		128		/* micro-second */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0000h ~ 0x00FFh	System Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_RSV_CTRL_8723B				0x001C	/* 3 Byte */
-+#define REG_BT_WIFI_ANTENNA_SWITCH_8723B	0x0038
-+#define REG_HSISR_8723B					0x005c
-+#define REG_PAD_CTRL1_8723B		0x0064
-+#define REG_AFE_CTRL_4_8723B		0x0078
-+#define REG_HMEBOX_DBG_0_8723B	0x0088
-+#define REG_HMEBOX_DBG_1_8723B	0x008A
-+#define REG_HMEBOX_DBG_2_8723B	0x008C
-+#define REG_HMEBOX_DBG_3_8723B	0x008E
-+#define REG_HIMR0_8723B					0x00B0
-+#define REG_HISR0_8723B					0x00B4
-+#define REG_HIMR1_8723B					0x00B8
-+#define REG_HISR1_8723B					0x00BC
-+#define REG_PMC_DBG_CTRL2_8723B			0x00CC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_C2HEVT_CMD_ID_8723B	0x01A0
-+#define REG_C2HEVT_CMD_LEN_8723B	0x01AE
-+#define REG_WOWLAN_WAKE_REASON 0x01C7
-+#define REG_WOWLAN_GTK_DBG1	0x630
-+#define REG_WOWLAN_GTK_DBG2	0x634
-+
-+#define REG_HMEBOX_EXT0_8723B			0x01F0
-+#define REG_HMEBOX_EXT1_8723B			0x01F4
-+#define REG_HMEBOX_EXT2_8723B			0x01F8
-+#define REG_HMEBOX_EXT3_8723B			0x01FC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_RXDMA_CONTROL_8723B		0x0286 /* Control the RX DMA. */
-+#define REG_RXDMA_MODE_CTRL_8723B		0x0290
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0300h ~ 0x03FFh	PCIe
-+ *
-+ * ----------------------------------------------------- */
-+#define	REG_PCIE_CTRL_REG_8723B		0x0300
-+#define	REG_INT_MIG_8723B				0x0304	/* Interrupt Migration */
-+#define	REG_BCNQ_DESA_8723B			0x0308	/* TX Beacon Descriptor Address */
-+#define	REG_HQ_DESA_8723B				0x0310	/* TX High Queue Descriptor Address */
-+#define	REG_MGQ_DESA_8723B			0x0318	/* TX Manage Queue Descriptor Address */
-+#define	REG_VOQ_DESA_8723B			0x0320	/* TX VO Queue Descriptor Address */
-+#define	REG_VIQ_DESA_8723B				0x0328	/* TX VI Queue Descriptor Address */
-+#define	REG_BEQ_DESA_8723B			0x0330	/* TX BE Queue Descriptor Address */
-+#define	REG_BKQ_DESA_8723B			0x0338	/* TX BK Queue Descriptor Address */
-+#define	REG_RX_DESA_8723B				0x0340	/* RX Queue	Descriptor Address */
-+#define	REG_DBI_WDATA_8723B			0x0348	/* DBI Write Data */
-+#define	REG_DBI_RDATA_8723B			0x034C	/* DBI Read Data */
-+#define	REG_DBI_ADDR_8723B				0x0350	/* DBI Address */
-+#define	REG_DBI_FLAG_8723B				0x0352	/* DBI Read/Write Flag */
-+#define	REG_MDIO_WDATA_8723B		0x0354	/* MDIO for Write PCIE PHY */
-+#define	REG_MDIO_RDATA_8723B			0x0356	/* MDIO for Reads PCIE PHY */
-+#define	REG_MDIO_CTL_8723B			0x0358	/* MDIO for Control */
-+#define	REG_DBG_SEL_8723B				0x0360	/* Debug Selection Register */
-+#define	REG_PCIE_HRPWM_8723B			0x0361	/* PCIe RPWM */
-+#define	REG_PCIE_HCPWM_8723B			0x0363	/* PCIe CPWM */
-+#define	REG_PCIE_MULTIFET_CTRL_8723B	0x036A	/* PCIE Multi-Fethc Control */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0400h ~ 0x047Fh	Protocol Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_TXPKTBUF_BCNQ_BDNY_8723B	0x0424
-+#define REG_TXPKTBUF_MGQ_BDNY_8723B	0x0425
-+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B	0x045D
-+#ifdef CONFIG_WOWLAN
-+	#define REG_TXPKTBUF_IV_LOW             0x0484
-+	#define REG_TXPKTBUF_IV_HIGH            0x0488
-+#endif
-+#define REG_AMPDU_BURST_MODE_8723B	0x04BC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0500h ~ 0x05FFh	EDCA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_SECONDARY_CCA_CTRL_8723B	0x0577
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0600h ~ 0x07FFh	WMAC Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+
-+/* ************************************************************
-+ * SDIO Bus Specification
-+ * ************************************************************ */
-+
-+/* -----------------------------------------------------
-+ * SDIO CMD Address Mapping
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ * I/O bus domain (Host)
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ * SDIO register
-+ * ----------------------------------------------------- */
-+#define SDIO_REG_HCPWM1_8723B	0x025 /* HCI Current Power Mode 1 */
-+
-+
-+/* ****************************************************************************
-+ *	8723 Regsiter Bit and Content definition
-+ * **************************************************************************** */
-+
-+/* 2 HSISR
-+ * interrupt mask which needs to clear */
-+#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
-+		HSISR_SPS_OCP_INT |\
-+		HSISR_RON_INT |\
-+		HSISR_PDNINT |\
-+		HSISR_GPIO9_INT)
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#undef IS_E_CUT
-+#define IS_E_CUT(version)		FALSE
-+#undef IS_F_CUT
-+#define IS_F_CUT(version)		((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define BIT_USB_RXDMA_AGG_EN	BIT(31)
-+#define RXDMA_AGG_MODE_EN		BIT(1)
-+
-+#ifdef CONFIG_WOWLAN
-+	#define RXPKT_RELEASE_POLL		BIT(16)
-+	#define RXDMA_IDLE				BIT(17)
-+	#define RW_RELEASE_EN			BIT(18)
-+#endif
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0400h ~ 0x047Fh	Protocol Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* ----------------------------------------------------------------------------
-+ * 8723B REG_CCK_CHECK						(offset 0x454)
-+ * ---------------------------------------------------------------------------- */
-+#define BIT_BCN_PORT_SEL		BIT(5)
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0500h ~ 0x05FFh	EDCA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0600h ~ 0x07FFh	WMAC Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#ifdef CONFIG_RF_POWER_TRIM
-+
-+	#ifdef CONFIG_RTL8723B
-+		#define EEPROM_RF_GAIN_OFFSET			0xC1
-+	#endif
-+
-+	#define EEPROM_RF_GAIN_VAL				0x1F6
-+#endif /*CONFIG_RF_POWER_TRIM*/
-+
-+
-+/* ----------------------------------------------------------------------------
-+ * 8195 IMR/ISR bits						(offset 0xB0,  8bits)
-+ * ---------------------------------------------------------------------------- */
-+#define	IMR_DISABLED_8723B					0
-+/* IMR DW0(0x00B0-00B3) Bit 0-31 */
-+#define	IMR_TIMER2_8723B					BIT(31)		/* Timeout interrupt 2 */
-+#define	IMR_TIMER1_8723B					BIT(30)		/* Timeout interrupt 1	 */
-+#define	IMR_PSTIMEOUT_8723B				BIT(29)		/* Power Save Time Out Interrupt */
-+#define	IMR_GTINT4_8723B					BIT(28)		/* When GTIMER4 expires, this bit is set to 1	 */
-+#define	IMR_GTINT3_8723B					BIT(27)		/* When GTIMER3 expires, this bit is set to 1	 */
-+#define	IMR_TXBCN0ERR_8723B				BIT(26)		/* Transmit Beacon0 Error			 */
-+#define	IMR_TXBCN0OK_8723B				BIT(25)		/* Transmit Beacon0 OK			 */
-+#define	IMR_TSF_BIT32_TOGGLE_8723B		BIT(24)		/* TSF Timer BIT(32) toggle indication interrupt			 */
-+#define	IMR_BCNDMAINT0_8723B				BIT(20)		/* Beacon DMA Interrupt 0			 */
-+#define	IMR_BCNDERR0_8723B				BIT(16)		/* Beacon Queue DMA OK0			 */
-+#define	IMR_HSISR_IND_ON_INT_8723B		BIT(15)		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
-+#define	IMR_BCNDMAINT_E_8723B			BIT(14)		/* Beacon DMA Interrupt Extension for Win7			 */
-+#define	IMR_ATIMEND_8723B				BIT(12)		/* CTWidnow End or ATIM Window End */
-+#define	IMR_C2HCMD_8723B					BIT(10)		/* CPU to Host Command INT Status, Write 1 clear	 */
-+#define	IMR_CPWM2_8723B					BIT(9)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
-+#define	IMR_CPWM_8723B					BIT(8)			/* CPU power Mode exchange INT Status, Write 1 clear	 */
-+#define	IMR_HIGHDOK_8723B				BIT(7)			/* High Queue DMA OK	 */
-+#define	IMR_MGNTDOK_8723B				BIT(6)			/* Management Queue DMA OK	 */
-+#define	IMR_BKDOK_8723B					BIT(5)			/* AC_BK DMA OK		 */
-+#define	IMR_BEDOK_8723B					BIT(4)			/* AC_BE DMA OK	 */
-+#define	IMR_VIDOK_8723B					BIT(3)			/* AC_VI DMA OK		 */
-+#define	IMR_VODOK_8723B					BIT(2)			/* AC_VO DMA OK	 */
-+#define	IMR_RDU_8723B					BIT(1)			/* Rx Descriptor Unavailable	 */
-+#define	IMR_ROK_8723B					BIT(0)			/* Receive DMA OK */
-+
-+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
-+#define	IMR_BCNDMAINT7_8723B				BIT(27)		/* Beacon DMA Interrupt 7 */
-+#define	IMR_BCNDMAINT6_8723B				BIT(26)		/* Beacon DMA Interrupt 6 */
-+#define	IMR_BCNDMAINT5_8723B				BIT(25)		/* Beacon DMA Interrupt 5 */
-+#define	IMR_BCNDMAINT4_8723B				BIT(24)		/* Beacon DMA Interrupt 4 */
-+#define	IMR_BCNDMAINT3_8723B				BIT(23)		/* Beacon DMA Interrupt 3 */
-+#define	IMR_BCNDMAINT2_8723B				BIT(22)		/* Beacon DMA Interrupt 2 */
-+#define	IMR_BCNDMAINT1_8723B				BIT(21)		/* Beacon DMA Interrupt 1 */
-+#define	IMR_BCNDOK7_8723B					BIT(20)		/* Beacon Queue DMA OK Interrupt 7 */
-+#define	IMR_BCNDOK6_8723B					BIT(19)		/* Beacon Queue DMA OK Interrupt 6 */
-+#define	IMR_BCNDOK5_8723B					BIT(18)		/* Beacon Queue DMA OK Interrupt 5 */
-+#define	IMR_BCNDOK4_8723B					BIT(17)		/* Beacon Queue DMA OK Interrupt 4 */
-+#define	IMR_BCNDOK3_8723B					BIT(16)		/* Beacon Queue DMA OK Interrupt 3 */
-+#define	IMR_BCNDOK2_8723B					BIT(15)		/* Beacon Queue DMA OK Interrupt 2 */
-+#define	IMR_BCNDOK1_8723B					BIT(14)		/* Beacon Queue DMA OK Interrupt 1 */
-+#define	IMR_ATIMEND_E_8723B				BIT(13)		/* ATIM Window End Extension for Win7 */
-+#define	IMR_TXERR_8723B					BIT(11)		/* Tx Error Flag Interrupt Status, write 1 clear. */
-+#define	IMR_RXERR_8723B					BIT(10)		/* Rx Error Flag INT Status, Write 1 clear */
-+#define	IMR_TXFOVW_8723B					BIT(9)			/* Transmit FIFO Overflow */
-+#define	IMR_RXFOVW_8723B					BIT(8)			/* Receive FIFO Overflow */
-+
-+#ifdef CONFIG_PCI_HCI
-+	/* #define IMR_RX_MASK		(IMR_ROK_8723B|IMR_RDU_8723B|IMR_RXFOVW_8723B) */
-+	#define IMR_TX_MASK			(IMR_VODOK_8723B | IMR_VIDOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B | IMR_MGNTDOK_8723B | IMR_HIGHDOK_8723B)
-+
-+	#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8723B | IMR_TXBCN0OK_8723B | IMR_TXBCN0ERR_8723B | IMR_BCNDERR0_8723B)
-+
-+	#define RT_AC_INT_MASKS	(IMR_VIDOK_8723B | IMR_VODOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B)
-+#endif
-+
-+#endif /* __RTL8723B_SPEC_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723b_sreset.h b/drivers/staging/rtl8723cs/include/rtl8723b_sreset.h
-new file mode 100644
-index 000000000000..c97f2648ac60
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723b_sreset.h
-@@ -0,0 +1,24 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8723B_SRESET_H_
-+#define _RTL8723B_SRESET_H_
-+
-+#include <rtw_sreset.h>
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	extern void rtl8723b_sreset_xmit_status_check(_adapter *padapter);
-+	extern void rtl8723b_sreset_linked_status_check(_adapter *padapter);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723b_xmit.h b/drivers/staging/rtl8723cs/include/rtl8723b_xmit.h
-new file mode 100644
-index 000000000000..51691e931c67
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723b_xmit.h
-@@ -0,0 +1,342 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723B_XMIT_H__
-+#define __RTL8723B_XMIT_H__
-+
-+
-+#define MAX_TID (15)
-+
-+
-+#ifndef __INC_HAL8723BDESC_H
-+	#define __INC_HAL8723BDESC_H
-+
-+	#define RX_STATUS_DESC_SIZE_8723B		24
-+	#define RX_DRV_INFO_SIZE_UNIT_8723B 8
-+
-+
-+	/* DWORD 0 */
-+	#define SET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
-+	#define SET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
-+	#define SET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
-+
-+	#define GET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
-+	#define GET_RX_STATUS_DESC_CRC32_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
-+	#define GET_RX_STATUS_DESC_ICV_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
-+	#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
-+	#define GET_RX_STATUS_DESC_SECURITY_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
-+	#define GET_RX_STATUS_DESC_QOS_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
-+	#define GET_RX_STATUS_DESC_SHIFT_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
-+	#define GET_RX_STATUS_DESC_PHY_STATUS_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
-+	#define GET_RX_STATUS_DESC_SWDEC_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
-+	#define GET_RX_STATUS_DESC_LAST_SEG_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
-+	#define GET_RX_STATUS_DESC_FIRST_SEG_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
-+	#define GET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
-+	#define GET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
-+
-+	/* DWORD 1 */
-+	#define GET_RX_STATUS_DESC_MACID_8723B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
-+	#define GET_RX_STATUS_DESC_TID_8723B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
-+	#define GET_RX_STATUS_DESC_AMSDU_8723B(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
-+	#define GET_RX_STATUS_DESC_RXID_MATCH_8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
-+	#define GET_RX_STATUS_DESC_PAGGR_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
-+	#define GET_RX_STATUS_DESC_A1_FIT_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
-+	#define GET_RX_STATUS_DESC_CHKERR_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
-+	#define GET_RX_STATUS_DESC_IPVER_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
-+	#define GET_RX_STATUS_DESC_IS_TCPUDP__8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
-+	#define GET_RX_STATUS_DESC_CHK_VLD_8723B(__pRxDesc)	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
-+	#define GET_RX_STATUS_DESC_PAM_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
-+	#define GET_RX_STATUS_DESC_PWR_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
-+	#define GET_RX_STATUS_DESC_MORE_DATA_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
-+	#define GET_RX_STATUS_DESC_MORE_FRAG_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
-+	#define GET_RX_STATUS_DESC_TYPE_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
-+	#define GET_RX_STATUS_DESC_MC_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
-+	#define GET_RX_STATUS_DESC_BC_8723B(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
-+
-+	/* DWORD 2 */
-+	#define GET_RX_STATUS_DESC_SEQ_8723B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
-+	#define GET_RX_STATUS_DESC_FRAG_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
-+	#define GET_RX_STATUS_DESC_RX_IS_QOS_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
-+	#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723B(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
-+	#define GET_RX_STATUS_DESC_RPT_SEL_8723B(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
-+
-+	/* DWORD 3 */
-+	#define GET_RX_STATUS_DESC_RX_RATE_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
-+	#define GET_RX_STATUS_DESC_HTC_8723B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
-+	#define GET_RX_STATUS_DESC_EOSP_8723B(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
-+	#define GET_RX_STATUS_DESC_BSSID_FIT_8723B(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
-+	#ifdef CONFIG_USB_RX_AGGREGATION
-+		#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723B(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
-+	#endif
-+	#define GET_RX_STATUS_DESC_PATTERN_MATCH_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
-+	#define GET_RX_STATUS_DESC_UNICAST_MATCH_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
-+	#define GET_RX_STATUS_DESC_MAGIC_MATCH_8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
-+
-+	/* DWORD 6 */
-+	#define GET_RX_STATUS_DESC_SPLCP_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
-+	#define GET_RX_STATUS_DESC_LDPC_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
-+	#define GET_RX_STATUS_DESC_STBC_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
-+	#define GET_RX_STATUS_DESC_BW_8723B(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
-+
-+	/* DWORD 5 */
-+	#define GET_RX_STATUS_DESC_TSFL_8723B(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
-+
-+	#define GET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
-+	#define GET_RX_STATUS_DESC_BUFF_ADDR64_8723B(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
-+
-+	#define SET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
-+
-+
-+	/* Dword 0 */
-+	#define GET_TX_DESC_OWN_8723B(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
-+
-+	#define SET_TX_DESC_PKT_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
-+	#define SET_TX_DESC_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
-+	#define SET_TX_DESC_BMC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
-+	#define SET_TX_DESC_HTC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
-+	#define SET_TX_DESC_LAST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
-+	#define SET_TX_DESC_FIRST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
-+	#define SET_TX_DESC_LINIP_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
-+	#define SET_TX_DESC_NO_ACM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
-+	#define SET_TX_DESC_GF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
-+	#define SET_TX_DESC_OWN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
-+
-+	/* Dword 1 */
-+	#define SET_TX_DESC_MACID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
-+	#define SET_TX_DESC_QUEUE_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
-+	#define SET_TX_DESC_RDG_NAV_EXT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
-+	#define SET_TX_DESC_LSIG_TXOP_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
-+	#define SET_TX_DESC_PIFS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
-+	#define SET_TX_DESC_RATE_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
-+	#define SET_TX_DESC_EN_DESC_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
-+	#define SET_TX_DESC_SEC_TYPE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
-+	#define SET_TX_DESC_PKT_OFFSET_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
-+
-+
-+	/* Dword 2 */
-+	#define SET_TX_DESC_PAID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
-+	#define SET_TX_DESC_CCA_RTS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
-+	#define SET_TX_DESC_AGG_ENABLE_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
-+	#define SET_TX_DESC_RDG_ENABLE_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
-+	#define SET_TX_DESC_AGG_BREAK_8723B(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
-+	#define SET_TX_DESC_MORE_FRAG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
-+	#define SET_TX_DESC_RAW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
-+	#define SET_TX_DESC_SPE_RPT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
-+	#define SET_TX_DESC_AMPDU_DENSITY_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
-+	#define SET_TX_DESC_BT_INT_8723B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
-+	#define SET_TX_DESC_GID_8723B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
-+
-+
-+	/* Dword 3 */
-+	#define SET_TX_DESC_WHEADER_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
-+	#define SET_TX_DESC_CHK_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
-+	#define SET_TX_DESC_EARLY_MODE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
-+	#define SET_TX_DESC_HWSEQ_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
-+	#define SET_TX_DESC_USE_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
-+	#define SET_TX_DESC_DISABLE_RTS_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
-+	#define SET_TX_DESC_DISABLE_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
-+	#define SET_TX_DESC_CTS2SELF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
-+	#define SET_TX_DESC_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
-+	#define SET_TX_DESC_HW_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
-+	#define SET_TX_DESC_NAV_USE_HDR_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
-+	#define SET_TX_DESC_USE_MAX_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
-+	#define SET_TX_DESC_MAX_AGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
-+	#define SET_TX_DESC_NDPA_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
-+	#define SET_TX_DESC_AMPDU_MAX_TIME_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
-+
-+	/* Dword 4 */
-+	#define SET_TX_DESC_TX_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
-+	#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
-+	#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
-+	#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
-+	#define SET_TX_DESC_DATA_RETRY_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
-+	#define SET_TX_DESC_RTS_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
-+
-+
-+	/* Dword 5 */
-+	#define SET_TX_DESC_DATA_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
-+	#define SET_TX_DESC_DATA_SHORT_8723B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
-+	#define SET_TX_DESC_DATA_BW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
-+	#define SET_TX_DESC_DATA_LDPC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
-+	#define SET_TX_DESC_DATA_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
-+	#define SET_TX_DESC_CTROL_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
-+	#define SET_TX_DESC_RTS_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
-+	#define SET_TX_DESC_RTS_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
-+
-+
-+	/* Dword 6 */
-+	#define SET_TX_DESC_SW_DEFINE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
-+	#define SET_TX_DESC_MBSSID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
-+	#define SET_TX_DESC_ANTSEL_A_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
-+	#define SET_TX_DESC_ANTSEL_B_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
-+	#define SET_TX_DESC_ANTSEL_C_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
-+	#define SET_TX_DESC_ANTSEL_D_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
-+
-+	/* Dword 7 */
-+	#ifdef CONFIG_PCI_HCI
-+		#define SET_TX_DESC_TX_BUFFER_SIZE_8723B(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+	#endif
-+	#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
-+		#define SET_TX_DESC_TX_DESC_CHECKSUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+	#endif
-+	#define SET_TX_DESC_USB_TXAGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
-+	#ifdef CONFIG_SDIO_HCI
-+		#define SET_TX_DESC_SDIO_TXSEQ_8723B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
-+	#endif
-+
-+	/* Dword 8 */
-+	#define SET_TX_DESC_HWSEQ_EN_8723B(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
-+
-+	/* Dword 9 */
-+	#define SET_TX_DESC_SEQ_8723B(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
-+
-+	/* Dword 10 */
-+	#define SET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
-+	#define GET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc)	LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
-+
-+	/* Dword 11 */
-+	#define SET_TX_DESC_NEXT_DESC_ADDRESS_8723B(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
-+
-+
-+	#define SET_EARLYMODE_PKTNUM_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
-+	#define SET_EARLYMODE_LEN0_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
-+	#define SET_EARLYMODE_LEN1_1_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
-+	#define SET_EARLYMODE_LEN1_2_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
-+	#define SET_EARLYMODE_LEN2_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
-+	#define SET_EARLYMODE_LEN3_8723B(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
-+
-+#endif
-+/* -----------------------------------------------------------
-+ *
-+ *	Rate
-+ *
-+ * -----------------------------------------------------------
-+ * CCK Rates, TxHT = 0 */
-+#define DESC8723B_RATE1M				0x00
-+#define DESC8723B_RATE2M				0x01
-+#define DESC8723B_RATE5_5M				0x02
-+#define DESC8723B_RATE11M				0x03
-+
-+/* OFDM Rates, TxHT = 0 */
-+#define DESC8723B_RATE6M				0x04
-+#define DESC8723B_RATE9M				0x05
-+#define DESC8723B_RATE12M				0x06
-+#define DESC8723B_RATE18M				0x07
-+#define DESC8723B_RATE24M				0x08
-+#define DESC8723B_RATE36M				0x09
-+#define DESC8723B_RATE48M				0x0a
-+#define DESC8723B_RATE54M				0x0b
-+
-+/* MCS Rates, TxHT = 1 */
-+#define DESC8723B_RATEMCS0				0x0c
-+#define DESC8723B_RATEMCS1				0x0d
-+#define DESC8723B_RATEMCS2				0x0e
-+#define DESC8723B_RATEMCS3				0x0f
-+#define DESC8723B_RATEMCS4				0x10
-+#define DESC8723B_RATEMCS5				0x11
-+#define DESC8723B_RATEMCS6				0x12
-+#define DESC8723B_RATEMCS7				0x13
-+#define DESC8723B_RATEMCS8				0x14
-+#define DESC8723B_RATEMCS9				0x15
-+#define DESC8723B_RATEMCS10		0x16
-+#define DESC8723B_RATEMCS11		0x17
-+#define DESC8723B_RATEMCS12		0x18
-+#define DESC8723B_RATEMCS13		0x19
-+#define DESC8723B_RATEMCS14		0x1a
-+#define DESC8723B_RATEMCS15		0x1b
-+#define DESC8723B_RATEVHTSS1MCS0		0x2c
-+#define DESC8723B_RATEVHTSS1MCS1		0x2d
-+#define DESC8723B_RATEVHTSS1MCS2		0x2e
-+#define DESC8723B_RATEVHTSS1MCS3		0x2f
-+#define DESC8723B_RATEVHTSS1MCS4		0x30
-+#define DESC8723B_RATEVHTSS1MCS5		0x31
-+#define DESC8723B_RATEVHTSS1MCS6		0x32
-+#define DESC8723B_RATEVHTSS1MCS7		0x33
-+#define DESC8723B_RATEVHTSS1MCS8		0x34
-+#define DESC8723B_RATEVHTSS1MCS9		0x35
-+#define DESC8723B_RATEVHTSS2MCS0		0x36
-+#define DESC8723B_RATEVHTSS2MCS1		0x37
-+#define DESC8723B_RATEVHTSS2MCS2		0x38
-+#define DESC8723B_RATEVHTSS2MCS3		0x39
-+#define DESC8723B_RATEVHTSS2MCS4		0x3a
-+#define DESC8723B_RATEVHTSS2MCS5		0x3b
-+#define DESC8723B_RATEVHTSS2MCS6		0x3c
-+#define DESC8723B_RATEVHTSS2MCS7		0x3d
-+#define DESC8723B_RATEVHTSS2MCS8		0x3e
-+#define DESC8723B_RATEVHTSS2MCS9		0x3f
-+
-+
-+#define	RX_HAL_IS_CCK_RATE_8723B(pDesc)\
-+	(GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE1M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE2M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE5_5M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE11M)
-+
-+
-+void rtl8723b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
-+void rtl8723b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
-+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	s32 rtl8723bs_init_xmit_priv(PADAPTER padapter);
-+	void rtl8723bs_free_xmit_priv(PADAPTER padapter);
-+	s32 rtl8723bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8723bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8723bs_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	rtl8723bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8723bs_xmit_buf_handler(PADAPTER padapter);
-+	thread_return rtl8723bs_xmit_thread(thread_context context);
-+	#define hal_xmit_handler rtl8723bs_xmit_buf_handler
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	s32 rtl8723bu_xmit_buf_handler(PADAPTER padapter);
-+	#define hal_xmit_handler rtl8723bu_xmit_buf_handler
-+
-+
-+	s32 rtl8723bu_init_xmit_priv(PADAPTER padapter);
-+	void rtl8723bu_free_xmit_priv(PADAPTER padapter);
-+	s32 rtl8723bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8723bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8723bu_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	 rtl8723bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */
-+	void rtl8723bu_xmit_tasklet(void *priv);
-+	s32 rtl8723bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+	void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8723be_init_xmit_priv(PADAPTER padapter);
-+	void rtl8723be_free_xmit_priv(PADAPTER padapter);
-+	struct xmit_buf *rtl8723be_dequeue_xmitbuf(struct rtw_tx_ring *ring);
-+	void	rtl8723be_xmitframe_resume(_adapter *padapter);
-+	s32 rtl8723be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8723be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8723be_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	rtl8723be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	void rtl8723be_xmit_tasklet(void *priv);
-+#endif
-+
-+u8	BWMapping_8723B(PADAPTER Adapter, struct pkt_attrib *pattrib);
-+u8	SCMapping_8723B(PADAPTER Adapter, struct pkt_attrib	*pattrib);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723d_cmd.h b/drivers/staging/rtl8723cs/include/rtl8723d_cmd.h
-new file mode 100644
-index 000000000000..9c65b4b9e039
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723d_cmd.h
-@@ -0,0 +1,183 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723D_CMD_H__
-+#define __RTL8723D_CMD_H__
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    H2C CMD DEFINITION    ------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+enum h2c_cmd_8723D {
-+	/* Common Class: 000 */
-+	H2C_8723D_RSVD_PAGE = 0x00,
-+	H2C_8723D_MEDIA_STATUS_RPT = 0x01,
-+	H2C_8723D_SCAN_ENABLE = 0x02,
-+	H2C_8723D_KEEP_ALIVE = 0x03,
-+	H2C_8723D_DISCON_DECISION = 0x04,
-+	H2C_8723D_PSD_OFFLOAD = 0x05,
-+	H2C_8723D_AP_OFFLOAD = 0x08,
-+	H2C_8723D_BCN_RSVDPAGE = 0x09,
-+	H2C_8723D_PROBERSP_RSVDPAGE = 0x0A,
-+	H2C_8723D_FCS_RSVDPAGE = 0x10,
-+	H2C_8723D_FCS_INFO = 0x11,
-+	H2C_8723D_AP_WOW_GPIO_CTRL = 0x13,
-+
-+	/* PoweSave Class: 001 */
-+	H2C_8723D_SET_PWR_MODE = 0x20,
-+	H2C_8723D_PS_TUNING_PARA = 0x21,
-+	H2C_8723D_PS_TUNING_PARA2 = 0x22,
-+	H2C_8723D_P2P_LPS_PARAM = 0x23,
-+	H2C_8723D_P2P_PS_OFFLOAD = 0x24,
-+	H2C_8723D_PS_SCAN_ENABLE = 0x25,
-+	H2C_8723D_SAP_PS_ = 0x26,
-+	H2C_8723D_INACTIVE_PS_ = 0x27, /* Inactive_PS */
-+	H2C_8723D_FWLPS_IN_IPS_ = 0x28,
-+
-+	/* Dynamic Mechanism Class: 010 */
-+	H2C_8723D_MACID_CFG = 0x40,
-+	H2C_8723D_TXBF = 0x41,
-+	H2C_8723D_RSSI_SETTING = 0x42,
-+	H2C_8723D_AP_REQ_TXRPT = 0x43,
-+	H2C_8723D_INIT_RATE_COLLECT = 0x44,
-+	H2C_8723D_RA_PARA_ADJUST = 0x46,
-+
-+	/* BT Class: 011 */
-+	H2C_8723D_B_TYPE_TDMA = 0x60,
-+	H2C_8723D_BT_INFO = 0x61,
-+	H2C_8723D_FORCE_BT_TXPWR = 0x62,
-+	H2C_8723D_BT_IGNORE_WLANACT = 0x63,
-+	H2C_8723D_DAC_SWING_VALUE = 0x64,
-+	H2C_8723D_ANT_SEL_RSV = 0x65,
-+	H2C_8723D_WL_OPMODE = 0x66,
-+	H2C_8723D_BT_MP_OPER = 0x67,
-+	H2C_8723D_BT_CONTROL = 0x68,
-+	H2C_8723D_BT_WIFI_CTRL = 0x69,
-+	H2C_8723D_BT_FW_PATCH = 0x6A,
-+	H2C_8723D_BT_WLAN_CALIBRATION = 0x6D,
-+
-+	/* WOWLAN Class: 100 */
-+	H2C_8723D_WOWLAN = 0x80,
-+	H2C_8723D_REMOTE_WAKE_CTRL = 0x81,
-+	H2C_8723D_AOAC_GLOBAL_INFO = 0x82,
-+	H2C_8723D_AOAC_RSVD_PAGE = 0x83,
-+	H2C_8723D_AOAC_RSVD_PAGE2 = 0x84,
-+	H2C_8723D_D0_SCAN_OFFLOAD_CTRL = 0x85,
-+	H2C_8723D_D0_SCAN_OFFLOAD_INFO = 0x86,
-+	H2C_8723D_CHNL_SWITCH_OFFLOAD = 0x87,
-+	H2C_8723D_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
-+	H2C_8723D_P2P_OFFLOAD = 0x8B,
-+
-+	H2C_8723D_RESET_TSF = 0xC0,
-+	H2C_8723D_MAXID,
-+};
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    H2C CMD CONTENT    --------------------------------------------------
-+ * ---------------------------------------------------------------------------------------------------------
-+ * _RSVDPAGE_LOC_CMD_0x00 */
-+#define SET_8723D_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+/* _PWR_MOD_CMD_0x20 */
-+#define SET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
-+#define SET_8723D_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
-+#define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
-+#define SET_8723D_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+#define GET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
-+
-+/* _PS_TUNE_PARAM_CMD_0x21 */
-+#define SET_8723D_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
-+#define SET_8723D_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
-+#define SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+
-+/* _MACID_CFG_CMD_0x40 */
-+#define SET_8723D_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
-+#define SET_8723D_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
-+#define SET_8723D_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
-+#define SET_8723D_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
-+#define SET_8723D_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
-+#define SET_8723D_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
-+#define SET_8723D_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
-+#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
-+
-+/* _RSSI_SETTING_CMD_0x42 */
-+#define SET_8723D_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
-+#define SET_8723D_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+
-+/* _AP_REQ_TXRPT_CMD_0x43 */
-+#define SET_8723D_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+
-+/* _FORCE_BT_TXPWR_CMD_0x62 */
-+#define SET_8723D_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+
-+/* _FORCE_BT_MP_OPER_CMD_0x67 */
-+#define SET_8723D_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
-+#define SET_8723D_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
-+#define SET_8723D_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value)							SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
-+
-+/* _BT_FW_PATCH_0x6A */
-+#define SET_8723D_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
-+#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * -------------------------------------------    Structure    --------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+
-+/* ---------------------------------------------------------------------------------------------------------
-+ * ----------------------------------    Function Statement     --------------------------------------------------
-+ * --------------------------------------------------------------------------------------------------------- */
-+
-+/* host message to firmware cmd */
-+void rtl8723d_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
-+void rtl8723d_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
-+/* s32 rtl8723d_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
-+void rtl8723d_set_FwPsTuneParam_cmd(PADAPTER padapter);
-+void rtl8723d_download_rsvd_page(PADAPTER padapter, u8 mstatus);
-+#ifdef CONFIG_BT_COEXIST
-+	void rtl8723d_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
-+#endif /* CONFIG_BT_COEXIST */
-+#ifdef CONFIG_P2P
-+	void rtl8723d_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
-+#endif /* CONFIG_P2P */
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+	void rtl8723d_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
-+#endif
-+
-+s32 FillH2CCmd8723D(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
-+u8 GetTxBufferRsvdPageNum8723D(_adapter *padapter, bool wowlan);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723d_dm.h b/drivers/staging/rtl8723cs/include/rtl8723d_dm.h
-new file mode 100644
-index 000000000000..0612f0620e79
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723d_dm.h
-@@ -0,0 +1,39 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723D_DM_H__
-+#define __RTL8723D_DM_H__
-+/* ************************************************************
-+ * Description:
-+ *
-+ * This file is for 8723D dynamic mechanism only
-+ *
-+ *
-+ * ************************************************************ */
-+
-+/* ************************************************************
-+ * structure and define
-+ * ************************************************************ */
-+
-+/* ************************************************************
-+ * function prototype
-+ * ************************************************************ */
-+
-+void rtl8723d_init_dm_priv(PADAPTER padapter);
-+void rtl8723d_deinit_dm_priv(PADAPTER padapter);
-+
-+void rtl8723d_InitHalDm(PADAPTER padapter);
-+void rtl8723d_HalDmWatchDog(PADAPTER padapter);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723d_hal.h b/drivers/staging/rtl8723cs/include/rtl8723d_hal.h
-new file mode 100644
-index 000000000000..d18e9abc9973
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723d_hal.h
-@@ -0,0 +1,303 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723D_HAL_H__
-+#define __RTL8723D_HAL_H__
-+
-+#include "hal_data.h"
-+
-+#include "rtl8723d_spec.h"
-+#include "rtl8723d_rf.h"
-+#include "rtl8723d_dm.h"
-+#include "rtl8723d_recv.h"
-+#include "rtl8723d_xmit.h"
-+#include "rtl8723d_cmd.h"
-+#include "rtl8723d_led.h"
-+#include "Hal8723DPwrSeq.h"
-+#include "Hal8723DPhyReg.h"
-+#include "Hal8723DPhyCfg.h"
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	#include "rtl8723d_sreset.h"
-+#endif
-+#ifdef CONFIG_LPS_POFF
-+	#include "rtl8723d_lps_poff.h"
-+#endif
-+
-+#define FW_8723D_SIZE		0x8000
-+#define FW_8723D_START_ADDRESS	0x1000
-+#define FW_8723D_END_ADDRESS	0x1FFF /* 0x5FFF */
-+
-+#define IS_FW_HEADER_EXIST_8723D(_pFwHdr)\
-+	((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x23D0)
-+
-+typedef struct _RT_FIRMWARE {
-+	FIRMWARE_SOURCE	eFWSource;
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+	u8			*szFwBuffer;
-+#else
-+	u8			szFwBuffer[FW_8723D_SIZE];
-+#endif
-+	u32			ulFwLength;
-+} RT_FIRMWARE_8723D, *PRT_FIRMWARE_8723D;
-+
-+/*
-+ * This structure must be cared byte-ordering
-+ *
-+ * Added by tynli. 2009.12.04. */
-+typedef struct _RT_8723D_FIRMWARE_HDR {
-+	/* 8-byte alinment required */
-+
-+	/* --- LONG WORD 0 ---- */
-+	u16		Signature;	/* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
-+	u8		Category;	/* AP/NIC and USB/PCI */
-+	u8		Function;	/* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
-+	u16		Version;		/* FW Version */
-+	u16		Subversion;	/* FW Subversion, default 0x00 */
-+
-+	/* --- LONG WORD 1 ---- */
-+	u8		Month;	/* Release time Month field */
-+	u8		Date;	/* Release time Date field */
-+	u8		Hour;	/* Release time Hour field */
-+	u8		Minute;	/* Release time Minute field */
-+	u16		RamCodeSize;	/* The size of RAM code */
-+	u16		Rsvd2;
-+
-+	/* --- LONG WORD 2 ---- */
-+	u32		SvnIdx;	/* The SVN entry index */
-+	u32		Rsvd3;
-+
-+	/* --- LONG WORD 3 ---- */
-+	u32		Rsvd4;
-+	u32		Rsvd5;
-+} RT_8723D_FIRMWARE_HDR, *PRT_8723D_FIRMWARE_HDR;
-+
-+#define DRIVER_EARLY_INT_TIME_8723D		0x05
-+#define BCN_DMA_ATIME_INT_TIME_8723D		0x02
-+
-+/* for 8723D
-+ * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
-+#define PAGE_SIZE_TX_8723D			128
-+#define PAGE_SIZE_RX_8723D			8
-+
-+#define TX_DMA_SIZE_8723D			0x8000	/* 32K(TX) */
-+#define RX_DMA_SIZE_8723D			0x4000	/* 16K(RX) */
-+
-+#ifdef CONFIG_WOWLAN
-+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
-+#else
-+	#define RESV_FMWF	0
-+#endif
-+
-+#ifdef CONFIG_FW_C2H_DEBUG
-+	#define RX_DMA_RESERVED_SIZE_8723D	0x100	/* 256B, reserved for c2h debug message */
-+#else
-+	#define RX_DMA_RESERVED_SIZE_8723D	0x80	/* 128B, reserved for tx report */
-+#endif
-+#define RX_DMA_BOUNDARY_8723D\
-+	(RX_DMA_SIZE_8723D - RX_DMA_RESERVED_SIZE_8723D - 1)
-+
-+
-+/* Note: We will divide number of page equally for each queue other than public queue! */
-+
-+/* For General Reserved Page Number(Beacon Queue is reserved page)
-+ * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8723D
-+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
-+
-+#define BCNQ_PAGE_NUM_8723D		(MAX_BEACON_LEN/PAGE_SIZE_TX_8723D + 6) /*0x08*/
-+
-+/* For WoWLan , more reserved page
-+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
-+ * NS offload: 2 NDP info: 1
-+ */
-+#ifdef CONFIG_WOWLAN
-+	#define WOWLAN_PAGE_NUM_8723D	0x0b
-+#else
-+	#define WOWLAN_PAGE_NUM_8723D	0x00
-+#endif
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+	#undef WOWLAN_PAGE_NUM_8723D
-+	#define WOWLAN_PAGE_NUM_8723D	0x15
-+#endif
-+
-+#ifdef CONFIG_AP_WOWLAN
-+	#define AP_WOWLAN_PAGE_NUM_8723D	0x02
-+#endif
-+
-+#define TX_TOTAL_PAGE_NUMBER_8723D\
-+	(0xFF - BCNQ_PAGE_NUM_8723D - WOWLAN_PAGE_NUM_8723D)
-+#define TX_PAGE_BOUNDARY_8723D		(TX_TOTAL_PAGE_NUMBER_8723D + 1)
-+
-+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723D	TX_TOTAL_PAGE_NUMBER_8723D
-+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8723D\
-+	(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723D + 1)
-+
-+/* For Normal Chip Setting
-+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723D */
-+#define NORMAL_PAGE_NUM_HPQ_8723D		0x0C
-+#define NORMAL_PAGE_NUM_LPQ_8723D		0x02
-+#define NORMAL_PAGE_NUM_NPQ_8723D		0x02
-+#define NORMAL_PAGE_NUM_EPQ_8723D		0x04
-+
-+/* Note: For Normal Chip Setting, modify later */
-+#define WMM_NORMAL_PAGE_NUM_HPQ_8723D		0x30
-+#define WMM_NORMAL_PAGE_NUM_LPQ_8723D		0x20
-+#define WMM_NORMAL_PAGE_NUM_NPQ_8723D		0x20
-+#define WMM_NORMAL_PAGE_NUM_EPQ_8723D		0x00
-+
-+
-+#include "HalVerDef.h"
-+#include "hal_com.h"
-+
-+#define EFUSE_OOB_PROTECT_BYTES (96 + 1)
-+
-+#define HAL_EFUSE_MEMORY
-+#define HWSET_MAX_SIZE_8723D                512
-+#define EFUSE_REAL_CONTENT_LEN_8723D        512
-+#define EFUSE_MAP_LEN_8723D                 512
-+#define EFUSE_MAX_SECTION_8723D             64
-+
-+/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
-+#define EFUSE_IC_ID_OFFSET			506
-+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8723D)
-+
-+#define EFUSE_ACCESS_ON		0x69
-+#define EFUSE_ACCESS_OFF	0x00
-+
-+/* ********************************************************
-+ *			EFUSE for BT definition
-+ * ******************************************************** */
-+#define BANK_NUM			1
-+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	128
-+#define EFUSE_BT_REAL_CONTENT_LEN	\
-+	(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
-+#define EFUSE_BT_MAP_LEN		1024	/* 1k bytes */
-+#define EFUSE_BT_MAX_SECTION		(EFUSE_BT_MAP_LEN / 8)
-+#define EFUSE_PROTECT_BYTES_BANK	16
-+
-+typedef enum tag_Package_Definition {
-+	PACKAGE_DEFAULT,
-+	PACKAGE_QFN68,
-+	PACKAGE_TFBGA90,
-+	PACKAGE_TFBGA80,
-+	PACKAGE_TFBGA79
-+} PACKAGE_TYPE_E;
-+
-+#define INCLUDE_MULTI_FUNC_BT(_Adapter) \
-+	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
-+#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
-+	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
-+
-+#ifdef CONFIG_FILE_FWIMG
-+	extern char *rtw_fw_file_path;
-+	extern char *rtw_fw_wow_file_path;
-+	#ifdef CONFIG_MP_INCLUDED
-+		extern char *rtw_fw_mp_bt_file_path;
-+	#endif /* CONFIG_MP_INCLUDED */
-+#endif /* CONFIG_FILE_FWIMG */
-+
-+/* rtl8723d_hal_init.c */
-+s32 rtl8723d_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw);
-+void rtl8723d_FirmwareSelfReset(PADAPTER padapter);
-+void rtl8723d_InitializeFirmwareVars(PADAPTER padapter);
-+
-+void rtl8723d_InitAntenna_Selection(PADAPTER padapter);
-+void rtl8723d_DeinitAntenna_Selection(PADAPTER padapter);
-+void rtl8723d_CheckAntenna_Selection(PADAPTER padapter);
-+void rtl8723d_init_default_value(PADAPTER padapter);
-+
-+s32 rtl8723d_InitLLTTable(PADAPTER padapter);
-+
-+s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
-+s32 CardDisableWithoutHWSM(PADAPTER padapter);
-+
-+/* EFuse */
-+u8 GetEEPROMSize8723D(PADAPTER padapter);
-+void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
-+void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
-+void Hal_EfuseParseTxPowerInfo_8723D(PADAPTER padapter,
-+				     u8 *PROMContent, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseBTCoexistInfo_8723D(PADAPTER padapter,
-+				       u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseEEPROMVer_8723D(PADAPTER padapter,
-+				   u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseChnlPlan_8723D(PADAPTER padapter,
-+				  u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseCustomerID_8723D(PADAPTER padapter,
-+				    u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseAntennaDiversity_8723D(PADAPTER padapter,
-+		u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void Hal_EfuseParseXtal_8723D(PADAPTER pAdapter,
-+			      u8 *hwinfo, u8 AutoLoadFail);
-+void Hal_EfuseParseThermalMeter_8723D(PADAPTER padapter,
-+				      u8 *hwinfo, u8 AutoLoadFail);
-+void Hal_EfuseParseVoltage_8723D(PADAPTER pAdapter,
-+				 u8 *hwinfo, BOOLEAN	AutoLoadFail);
-+void Hal_EfuseParseBoardType_8723D(PADAPTER Adapter,
-+				   u8	*PROMContent, BOOLEAN AutoloadFail);
-+
-+void rtl8723d_set_hal_ops(struct hal_ops *pHalFunc);
-+void init_hal_spec_8723d(_adapter *adapter);
-+u8 SetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val);
-+void GetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val);
-+u8 SetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+u8 GetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+
-+/* register */
-+void rtl8723d_InitBeaconParameters(PADAPTER padapter);
-+void rtl8723d_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
-+void _InitMacAPLLSetting_8723D(PADAPTER Adapter);
-+void _8051Reset8723(PADAPTER padapter);
-+#ifdef CONFIG_WOWLAN
-+	void Hal_DetectWoWMode(PADAPTER pAdapter);
-+#endif /* CONFIG_WOWLAN */
-+
-+void rtl8723d_start_thread(_adapter *padapter);
-+void rtl8723d_stop_thread(_adapter *padapter);
-+
-+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
-+	void rtl8723ds_init_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8723ds_free_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8723ds_cancle_checkbthang_workqueue(_adapter *adapter);
-+	void rtl8723ds_hal_check_bt_hang(_adapter *adapter);
-+#endif
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+	void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
-+#endif
-+#ifdef CONFIG_MP_INCLUDED
-+int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
-+#endif
-+void CCX_FwC2HTxRpt_8723d(PADAPTER padapter, u8 *pdata, u8 len);
-+
-+u8 MRateToHwRate8723D(u8 rate);
-+u8 HwRateToMRate8723D(u8 rate);
-+
-+void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+
-+#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
-+	void check_bt_status_work(void *data);
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	BOOLEAN	InterruptRecognized8723DE(PADAPTER Adapter);
-+	void	UpdateInterruptMask8723DE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
-+	u16 get_txbd_rw_reg(u16 ff_hwaddr);
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723d_led.h b/drivers/staging/rtl8723cs/include/rtl8723d_led.h
-new file mode 100644
-index 000000000000..1905e8bed02c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723d_led.h
-@@ -0,0 +1,44 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723D_LED_H__
-+#define __RTL8723D_LED_H__
-+
-+#include <drv_conf.h>
-+#include <osdep_service.h>
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_RTW_SW_LED
-+/* ********************************************************************************
-+ * Interface to manipulate LED objects.
-+ * ******************************************************************************** */
-+#ifdef CONFIG_USB_HCI
-+	void rtl8723du_InitSwLeds(PADAPTER padapter);
-+	void rtl8723du_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_SDIO_HCI
-+	void rtl8723ds_InitSwLeds(PADAPTER padapter);
-+	void rtl8723ds_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_GSPI_HCI
-+	void rtl8723ds_InitSwLeds(PADAPTER padapter);
-+	void rtl8723ds_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+	void rtl8723de_InitSwLeds(PADAPTER padapter);
-+	void rtl8723de_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+
-+#endif /*#ifdef CONFIG_RTW_SW_LED*/
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723d_lps_poff.h b/drivers/staging/rtl8723cs/include/rtl8723d_lps_poff.h
-new file mode 100644
-index 000000000000..138a0ca66732
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723d_lps_poff.h
-@@ -0,0 +1,56 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+/******************************************** CONST  ************************/
-+#define NUM_OF_REGISTER_BANK	13
-+#define NUM_OF_TOTAL_DWORD (NUM_OF_REGISTER_BANK * 64)
-+#define TOTAL_LEN_FOR_HIOE ((NUM_OF_TOTAL_DWORD + 1) * 8)
-+#define LPS_POFF_STATIC_FILE_LEN (TOTAL_LEN_FOR_HIOE + TXDESC_SIZE)
-+#define LPS_POFF_DYNAMIC_FILE_LEN	(512 + TXDESC_SIZE)
-+/******************************************** CONST  ************************/
-+
-+/******************************************** MACRO   ************************/
-+/* HOIE Entry Definition */
-+#define SET_HOIE_ENTRY_LOW_DATA(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE),	0, 16, __Value)
-+#define SET_HOIE_ENTRY_HIGH_DATA(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE), 16, 16, __Value)
-+#define SET_HOIE_ENTRY_MODE_SELECT(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 0, 1, __Value)
-+#define SET_HOIE_ENTRY_ADDRESS(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 1, 14, __Value)
-+#define SET_HOIE_ENTRY_BYTE_MASK(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 15, 4, __Value)
-+#define SET_HOIE_ENTRY_IO_LOCK(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 19, 1, __Value)
-+#define SET_HOIE_ENTRY_RD_EN(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 20, 1, __Value)
-+#define SET_HOIE_ENTRY_WR_EN(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 21, 1, __Value)
-+#define SET_HOIE_ENTRY_RAW_RW(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 22, 1, __Value)
-+#define SET_HOIE_ENTRY_RAW(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 23, 1, __Value)
-+#define SET_HOIE_ENTRY_IO_DELAY(__pHOIE, __Value) \
-+	SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 24, 8, __Value)
-+
-+/*********************Function Definition*******************************************/
-+void rtl8723d_lps_poff_init(PADAPTER padapter);
-+void rtl8723d_lps_poff_deinit(PADAPTER padapter);
-+bool rtl8723d_lps_poff_get_txbndy_status(PADAPTER padapter);
-+void rtl8723d_lps_poff_h2c_ctrl(PADAPTER padapter, u8 enable);
-+void rtl8723d_lps_poff_set_ps_mode(PADAPTER padapter, bool bEnterLPS);
-+bool rtl8723d_lps_poff_get_status(PADAPTER padapter);
-+void rtl8723d_lps_poff_wow(PADAPTER padapter);
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723d_recv.h b/drivers/staging/rtl8723cs/include/rtl8723d_recv.h
-new file mode 100644
-index 000000000000..f19ad6904a22
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723d_recv.h
-@@ -0,0 +1,112 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723D_RECV_H__
-+#define __RTL8723D_RECV_H__
-+
-+#define RECV_BLK_SZ 512
-+#define RECV_BLK_CNT 16
-+#define RECV_BLK_TH RECV_BLK_CNT
-+
-+#if defined(CONFIG_USB_HCI)
-+
-+	#ifndef MAX_RECVBUF_SZ
-+		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
-+			/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
-+			/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
-+			/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
-+			#ifdef CONFIG_PLATFORM_MSTAR
-+				#define MAX_RECVBUF_SZ (8192) /* 8K */
-+			#else
-+				#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
-+			#endif
-+			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
-+		#else
-+			#define MAX_RECVBUF_SZ (4000) /* about 4K */
-+		#endif
-+	#endif /* !MAX_RECVBUF_SZ */
-+
-+#elif defined(CONFIG_PCI_HCI)
-+	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
-+	/*	#define MAX_RECVBUF_SZ (9100) */
-+	/* #else */
-+	#define MAX_RECVBUF_SZ (4000) /* about 4K
-+	* #endif */
-+
-+
-+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+
-+	#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8723D + 1)
-+
-+#endif
-+
-+/* Rx smooth factor */
-+#define	Rx_Smooth_Factor (20)
-+
-+#ifdef CONFIG_SDIO_HCI
-+	#ifndef CONFIG_SDIO_RX_COPY
-+		#undef MAX_RECVBUF_SZ
-+		#define MAX_RECVBUF_SZ	(RX_DMA_SIZE_8723D - RX_DMA_RESERVED_SIZE_8723D)
-+	#endif /* !CONFIG_SDIO_RX_COPY */
-+#endif /* CONFIG_SDIO_HCI */
-+
-+/*-----------------------------------------------------------------*/
-+/*	RTL8723D RX BUFFER DESC                                      */
-+/*-----------------------------------------------------------------*/
-+/*DWORD 0*/
-+#define SET_RX_BUFFER_DESC_DATA_LENGTH_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
-+#define SET_RX_BUFFER_DESC_LS_8723D(__pRxStatusDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
-+#define SET_RX_BUFFER_DESC_FS_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
-+#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
-+
-+#define GET_RX_BUFFER_DESC_OWN_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
-+#define GET_RX_BUFFER_DESC_LS_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
-+#define GET_RX_BUFFER_DESC_FS_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
-+#ifdef USING_RX_TAG
-+	#define GET_RX_BUFFER_DESC_RX_TAG_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)
-+#else
-+	#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8723D(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
-+#endif
-+
-+/*DWORD 1*/
-+#define SET_RX_BUFFER_PHYSICAL_LOW_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
-+
-+/*DWORD 2*/
-+#ifdef CONFIG_64BIT_DMA
-+	#define SET_RX_BUFFER_PHYSICAL_HIGH_8723D(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
-+#else
-+	#define SET_RX_BUFFER_PHYSICAL_HIGH_8723D(__pRxStatusDesc, __Value)
-+#endif
-+
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	s32 rtl8723ds_init_recv_priv(PADAPTER padapter);
-+	void rtl8723ds_free_recv_priv(PADAPTER padapter);
-+	s32 rtl8723ds_recv_hdl(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	int rtl8723du_init_recv_priv(_adapter *padapter);
-+	void rtl8723du_free_recv_priv(_adapter *padapter);
-+	void rtl8723du_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8723de_init_recv_priv(PADAPTER padapter);
-+	void rtl8723de_free_recv_priv(PADAPTER padapter);
-+#endif
-+
-+void rtl8723d_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
-+
-+#endif /* __RTL8723D_RECV_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723d_rf.h b/drivers/staging/rtl8723cs/include/rtl8723d_rf.h
-new file mode 100644
-index 000000000000..4a0a7cfb8747
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723d_rf.h
-@@ -0,0 +1,21 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723D_RF_H__
-+#define __RTL8723D_RF_H__
-+
-+int PHY_RF6052_Config8723D(PADAPTER pdapter);
-+
-+void PHY_RF6052SetBandwidth8723D(PADAPTER Adapter, enum channel_width Bandwidth);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723d_spec.h b/drivers/staging/rtl8723cs/include/rtl8723d_spec.h
-new file mode 100644
-index 000000000000..5106b23b7722
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723d_spec.h
-@@ -0,0 +1,447 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723D_SPEC_H__
-+#define __RTL8723D_SPEC_H__
-+
-+#include <drv_conf.h>
-+
-+
-+#define HAL_NAV_UPPER_UNIT_8723D		128		/* micro-second */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0000h ~ 0x00FFh	System Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_SYS_ISO_CTRL_8723D			0x0000	/* 2 Byte */
-+#define REG_SYS_FUNC_EN_8723D			0x0002	/* 2 Byte */
-+#define REG_APS_FSMCO_8723D			0x0004	/* 4 Byte */
-+#define REG_SYS_CLKR_8723D				0x0008	/* 2 Byte */
-+#define REG_9346CR_8723D				0x000A	/* 2 Byte */
-+#define REG_EE_VPD_8723D				0x000C	/* 2 Byte */
-+#define REG_AFE_MISC_8723D				0x0010	/* 1 Byte */
-+#define REG_SPS0_CTRL_8723D				0x0011	/* 7 Byte */
-+#define REG_SPS_OCP_CFG_8723D			0x0018	/* 4 Byte */
-+#define REG_RSV_CTRL_8723D				0x001C	/* 3 Byte */
-+#define REG_RF_CTRL_8723D				0x001F	/* 1 Byte */
-+#define REG_LPLDO_CTRL_8723D			0x0023	/* 1 Byte */
-+#define REG_AFE_XTAL_CTRL_8723D		0x0024	/* 4 Byte */
-+#define REG_AFE_PLL_CTRL_8723D			0x0028	/* 4 Byte */
-+#define REG_MAC_PLL_CTRL_EXT_8723D		0x002c	/* 4 Byte */
-+#define REG_EFUSE_CTRL_8723D			0x0030
-+#define REG_EFUSE_TEST_8723D			0x0034
-+#define REG_PWR_DATA_8723D				0x0038
-+#define REG_CAL_TIMER_8723D				0x003C
-+#define REG_ACLK_MON_8723D				0x003E
-+#define REG_GPIO_MUXCFG_8723D			0x0040
-+#define REG_GPIO_IO_SEL_8723D			0x0042
-+#define REG_MAC_PINMUX_CFG_8723D		0x0043
-+#define REG_GPIO_PIN_CTRL_8723D			0x0044
-+#define REG_GPIO_INTM_8723D				0x0048
-+#define REG_LEDCFG0_8723D				0x004C
-+#define REG_LEDCFG1_8723D				0x004D
-+#define REG_LEDCFG2_8723D				0x004E
-+#define REG_LEDCFG3_8723D				0x004F
-+#define REG_FSIMR_8723D					0x0050
-+#define REG_FSISR_8723D					0x0054
-+#define REG_HSIMR_8723D					0x0058
-+#define REG_HSISR_8723D					0x005c
-+#define REG_GPIO_EXT_CTRL				0x0060
-+#define REG_PAD_CTRL1_8723D		0x0064
-+#define REG_MULTI_FUNC_CTRL_8723D		0x0068
-+#define REG_GPIO_STATUS_8723D			0x006C
-+#define REG_SDIO_CTRL_8723D				0x0070
-+#define REG_OPT_CTRL_8723D				0x0074
-+#define REG_AFE_CTRL_4_8723D		0x0078
-+#define REG_MCUFWDL_8723D				0x0080
-+#define REG_8051FW_CTRL_8723D			0x0080
-+#define REG_HMEBOX_DBG_0_8723D	0x0088
-+#define REG_HMEBOX_DBG_1_8723D	0x008A
-+#define REG_HMEBOX_DBG_2_8723D	0x008C
-+#define REG_HMEBOX_DBG_3_8723D	0x008E
-+#define REG_WLLPS_CTRL		0x0090
-+#define REG_HIMR0_8723D					0x00B0
-+#define REG_HISR0_8723D					0x00B4
-+#define REG_HIMR1_8723D					0x00B8
-+#define REG_HISR1_8723D					0x00BC
-+#define REG_PMC_DBG_CTRL2_8723D			0x00CC
-+#define	REG_EFUSE_BURN_GNT_8723D		0x00CF
-+#define REG_HPON_FSM_8723D				0x00EC
-+#define REG_SYS_CFG1_8723D				0x00F0
-+#define REG_SYS_CFG_8723D				0x00FC
-+#define REG_ROM_VERSION					0x00FD
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_C2HEVT_CMD_ID_8723D	0x01A0
-+#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
-+#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
-+#define REG_C2HEVT_CMD_LEN_8723D        0x01AE
-+#define REG_C2HEVT_CLEAR_8723D			0x01AF
-+#define REG_MCUTST_1_8723D				0x01C0
-+#define REG_WOWLAN_WAKE_REASON 0x01C7
-+#define REG_FMETHR_8723D				0x01C8
-+#define REG_HMETFR_8723D				0x01CC
-+#define REG_HMEBOX_0_8723D				0x01D0
-+#define REG_HMEBOX_1_8723D				0x01D4
-+#define REG_HMEBOX_2_8723D				0x01D8
-+#define REG_HMEBOX_3_8723D				0x01DC
-+#define REG_LLT_INIT_8723D				0x01E0
-+#define REG_HMEBOX_EXT0_8723D			0x01F0
-+#define REG_HMEBOX_EXT1_8723D			0x01F4
-+#define REG_HMEBOX_EXT2_8723D			0x01F8
-+#define REG_HMEBOX_EXT3_8723D			0x01FC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_RQPN_8723D					0x0200
-+#define REG_FIFOPAGE_8723D				0x0204
-+#define REG_DWBCN0_CTRL_8723D			REG_TDECTRL
-+#define REG_TXDMA_OFFSET_CHK_8723D	0x020C
-+#define REG_TXDMA_STATUS_8723D		0x0210
-+#define REG_RQPN_NPQ_8723D			0x0214
-+#define REG_DWBCN1_CTRL_8723D			0x0228
-+
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_RXDMA_AGG_PG_TH_8723D		0x0280
-+#define REG_FW_UPD_RDPTR_8723D		0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
-+#define REG_RXDMA_CONTROL_8723D		0x0286 /* Control the RX DMA. */
-+#define REG_RXDMA_STATUS_8723D			0x0288
-+#define REG_RXDMA_MODE_CTRL_8723D		0x0290
-+#define REG_EARLY_MODE_CONTROL_8723D	0x02BC
-+#define REG_RSVD5_8723D					0x02F0
-+#define REG_RSVD6_8723D					0x02F4
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0300h ~ 0x03FFh	PCIe
-+ *
-+ * ----------------------------------------------------- */
-+#define	REG_PCIE_CTRL_REG_8723D			0x0300
-+#define	REG_INT_MIG_8723D				0x0304	/* Interrupt Migration */
-+#define	REG_BCNQ_TXBD_DESA_8723D		0x0308	/* TX Beacon Descriptor Address */
-+#define	REG_MGQ_TXBD_DESA_8723D			0x0310	/* TX Manage Queue Descriptor Address */
-+#define	REG_VOQ_TXBD_DESA_8723D			0x0318	/* TX VO Queue Descriptor Address */
-+#define	REG_VIQ_TXBD_DESA_8723D			0x0320	/* TX VI Queue Descriptor Address */
-+#define	REG_BEQ_TXBD_DESA_8723D			0x0328	/* TX BE Queue Descriptor Address */
-+#define	REG_BKQ_TXBD_DESA_8723D			0x0330	/* TX BK Queue Descriptor Address */
-+#define	REG_RXQ_RXBD_DESA_8723D			0x0338	/* RX Queue	Descriptor Address */
-+#define REG_HI0Q_TXBD_DESA_8723D		0x0340
-+#define REG_HI1Q_TXBD_DESA_8723D		0x0348
-+#define REG_HI2Q_TXBD_DESA_8723D		0x0350
-+#define REG_HI3Q_TXBD_DESA_8723D		0x0358
-+#define REG_HI4Q_TXBD_DESA_8723D		0x0360
-+#define REG_HI5Q_TXBD_DESA_8723D		0x0368
-+#define REG_HI6Q_TXBD_DESA_8723D		0x0370
-+#define REG_HI7Q_TXBD_DESA_8723D		0x0378
-+#define	REG_MGQ_TXBD_NUM_8723D			0x0380
-+#define	REG_RX_RXBD_NUM_8723D			0x0382
-+#define	REG_VOQ_TXBD_NUM_8723D			0x0384
-+#define	REG_VIQ_TXBD_NUM_8723D			0x0386
-+#define	REG_BEQ_TXBD_NUM_8723D			0x0388
-+#define	REG_BKQ_TXBD_NUM_8723D			0x038A
-+#define	REG_HI0Q_TXBD_NUM_8723D			0x038C
-+#define	REG_HI1Q_TXBD_NUM_8723D			0x038E
-+#define	REG_HI2Q_TXBD_NUM_8723D			0x0390
-+#define	REG_HI3Q_TXBD_NUM_8723D			0x0392
-+#define	REG_HI4Q_TXBD_NUM_8723D			0x0394
-+#define	REG_HI5Q_TXBD_NUM_8723D			0x0396
-+#define	REG_HI6Q_TXBD_NUM_8723D			0x0398
-+#define	REG_HI7Q_TXBD_NUM_8723D			0x039A
-+#define	REG_TSFTIMER_HCI_8723D			0x039C
-+#define	REG_BD_RW_PTR_CLR_8723D			0x039C
-+
-+/* Read Write Point */
-+#define	REG_VOQ_TXBD_IDX_8723D			0x03A0
-+#define	REG_VIQ_TXBD_IDX_8723D			0x03A4
-+#define	REG_BEQ_TXBD_IDX_8723D			0x03A8
-+#define	REG_BKQ_TXBD_IDX_8723D			0x03AC
-+#define	REG_MGQ_TXBD_IDX_8723D			0x03B0
-+#define	REG_RXQ_TXBD_IDX_8723D			0x03B4
-+#define	REG_HI0Q_TXBD_IDX_8723D			0x03B8
-+#define	REG_HI1Q_TXBD_IDX_8723D			0x03BC
-+#define	REG_HI2Q_TXBD_IDX_8723D			0x03C0
-+#define	REG_HI3Q_TXBD_IDX_8723D			0x03C4
-+#define	REG_HI4Q_TXBD_IDX_8723D			0x03C8
-+#define	REG_HI5Q_TXBD_IDX_8723D			0x03CC
-+#define	REG_HI6Q_TXBD_IDX_8723D			0x03D0
-+#define	REG_HI7Q_TXBD_IDX_8723D			0x03D4
-+
-+#define	REG_PCIE_HCPWM_8723DE			0x03D8 /* ?????? */
-+#define	REG_PCIE_HRPWM_8723DE			0x03DC	/* PCIe RPWM  ?????? */
-+#define	REG_DBI_WDATA_V1_8723D			0x03E8
-+#define	REG_DBI_RDATA_V1_8723D			0x03EC
-+#define	REG_DBI_FLAG_V1_8723D			0x03F0
-+#define REG_MDIO_V1_8723D				0x03F4
-+#define REG_PCIE_MIX_CFG_8723D			0x03F8
-+#define REG_HCI_MIX_CFG_8723D			0x03FC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0400h ~ 0x047Fh	Protocol Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_VOQ_INFORMATION_8723D		0x0400
-+#define REG_VIQ_INFORMATION_8723D		0x0404
-+#define REG_BEQ_INFORMATION_8723D		0x0408
-+#define REG_BKQ_INFORMATION_8723D		0x040C
-+#define REG_MGQ_INFORMATION_8723D		0x0410
-+#define REG_HGQ_INFORMATION_8723D		0x0414
-+#define REG_BCNQ_INFORMATION_8723D	0x0418
-+#define REG_TXPKT_EMPTY_8723D			0x041A
-+
-+#define REG_FWHW_TXQ_CTRL_8723D		0x0420
-+#define REG_HWSEQ_CTRL_8723D			0x0423
-+#define REG_TXPKTBUF_BCNQ_BDNY_8723D	0x0424
-+#define REG_TXPKTBUF_MGQ_BDNY_8723D	0x0425
-+#define REG_LIFECTRL_CTRL_8723D			0x0426
-+#define REG_MULTI_BCNQ_OFFSET_8723D	0x0427
-+#define REG_SPEC_SIFS_8723D				0x0428
-+#define REG_RL_8723D						0x042A
-+#define REG_TXBF_CTRL_8723D				0x042C
-+#define REG_DARFRC_8723D				0x0430
-+#define REG_RARFRC_8723D				0x0438
-+#define REG_RRSR_8723D					0x0440
-+#define REG_ARFR0_8723D					0x0444
-+#define REG_ARFR1_8723D					0x044C
-+#define REG_CCK_CHECK_8723D				0x0454
-+#define REG_AMPDU_MAX_TIME_8723D		0x0456
-+#define REG_TXPKTBUF_BCNQ_BDNY1_8723D	0x0457
-+
-+#define REG_AMPDU_MAX_LENGTH_8723D	0x0458
-+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D	0x045D
-+#define REG_NDPA_OPT_CTRL_8723D		0x045F
-+#define REG_FAST_EDCA_CTRL_8723D		0x0460
-+#define REG_RD_RESP_PKT_TH_8723D		0x0463
-+#define REG_DATA_SC_8723D				0x0483
-+#ifdef CONFIG_WOWLAN
-+	#define REG_TXPKTBUF_IV_LOW             0x0484
-+	#define REG_TXPKTBUF_IV_HIGH            0x0488
-+#endif
-+#define REG_TXRPT_START_OFFSET		0x04AC
-+#define REG_POWER_STAGE1_8723D		0x04B4
-+#define REG_POWER_STAGE2_8723D		0x04B8
-+#define REG_AMPDU_BURST_MODE_8723D	0x04BC
-+#define REG_PKT_VO_VI_LIFE_TIME_8723D	0x04C0
-+#define REG_PKT_BE_BK_LIFE_TIME_8723D	0x04C2
-+#define REG_STBC_SETTING_8723D			0x04C4
-+#define REG_HT_SINGLE_AMPDU_8723D		0x04C7
-+#define REG_PROT_MODE_CTRL_8723D		0x04C8
-+#define REG_MAX_AGGR_NUM_8723D		0x04CA
-+#define REG_RTS_MAX_AGGR_NUM_8723D	0x04CB
-+#define REG_BAR_MODE_CTRL_8723D		0x04CC
-+#define REG_RA_TRY_RATE_AGG_LMT_8723D	0x04CF
-+#define REG_MACID_PKT_DROP0_8723D		0x04D0
-+#define REG_MACID_PKT_SLEEP_8723D		0x04D4
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0500h ~ 0x05FFh	EDCA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_EDCA_VO_PARAM_8723D		0x0500
-+#define REG_EDCA_VI_PARAM_8723D		0x0504
-+#define REG_EDCA_BE_PARAM_8723D		0x0508
-+#define REG_EDCA_BK_PARAM_8723D		0x050C
-+#define REG_BCNTCFG_8723D				0x0510
-+#define REG_PIFS_8723D					0x0512
-+#define REG_RDG_PIFS_8723D				0x0513
-+#define REG_SIFS_CTX_8723D				0x0514
-+#define REG_SIFS_TRX_8723D				0x0516
-+#define REG_AGGR_BREAK_TIME_8723D		0x051A
-+#define REG_SLOT_8723D					0x051B
-+#define REG_TX_PTCL_CTRL_8723D			0x0520
-+#define REG_TXPAUSE_8723D				0x0522
-+#define REG_DIS_TXREQ_CLR_8723D		0x0523
-+#define REG_RD_CTRL_8723D				0x0524
-+/*
-+ * Format for offset 540h-542h:
-+ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
-+ *	[7:4]:   Reserved.
-+ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
-+ *	[23:20]: Reserved
-+ * Description:
-+ *	              |
-+ * |<--Setup--|--Hold------------>|
-+ *	--------------|----------------------
-+ * |
-+ * TBTT
-+ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
-+ * Described by Designer Tim and Bruce, 2011-01-14.
-+ *   */
-+#define REG_TBTT_PROHIBIT_8723D			0x0540
-+#define REG_RD_NAV_NXT_8723D			0x0544
-+#define REG_NAV_PROT_LEN_8723D			0x0546
-+#define REG_BCN_CTRL_8723D				0x0550
-+#define REG_BCN_CTRL_1_8723D			0x0551
-+#define REG_MBID_NUM_8723D				0x0552
-+#define REG_DUAL_TSF_RST_8723D			0x0553
-+#define REG_BCN_INTERVAL_8723D			0x0554
-+#define REG_DRVERLYINT_8723D			0x0558
-+#define REG_BCNDMATIM_8723D			0x0559
-+#define REG_ATIMWND_8723D				0x055A
-+#define REG_USTIME_TSF_8723D			0x055C
-+#define REG_BCN_MAX_ERR_8723D			0x055D
-+#define REG_RXTSF_OFFSET_CCK_8723D		0x055E
-+#define REG_RXTSF_OFFSET_OFDM_8723D	0x055F
-+#define REG_TSFTR_8723D					0x0560
-+#define REG_CTWND_8723D					0x0572
-+#define REG_SECONDARY_CCA_CTRL_8723D	0x0577
-+#define REG_PSTIMER_8723D				0x0580
-+#define REG_TIMER0_8723D				0x0584
-+#define REG_TIMER1_8723D				0x0588
-+#define REG_ACMHWCTRL_8723D			0x05C0
-+#define REG_SCH_TXCMD_8723D			0x05F8
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0600h ~ 0x07FFh	WMAC Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_MAC_CR_8723D				0x0600
-+#define REG_TCR_8723D					0x0604
-+#define REG_RCR_8723D					0x0608
-+#define REG_RX_PKT_LIMIT_8723D			0x060C
-+#define REG_RX_DLK_TIME_8723D			0x060D
-+#define REG_RX_DRVINFO_SZ_8723D		0x060F
-+
-+#define REG_MACID_8723D					0x0610
-+#define REG_BSSID_8723D					0x0618
-+#define REG_MAR_8723D					0x0620
-+#define REG_MBIDCAMCFG_8723D			0x0628
-+#define REG_WOWLAN_GTK_DBG1	0x630
-+#define REG_WOWLAN_GTK_DBG2	0x634
-+
-+#define REG_USTIME_EDCA_8723D			0x0638
-+#define REG_MAC_SPEC_SIFS_8723D		0x063A
-+#define REG_RESP_SIFP_CCK_8723D			0x063C
-+#define REG_RESP_SIFS_OFDM_8723D		0x063E
-+#define REG_ACKTO_8723D					0x0640
-+#define REG_CTS2TO_8723D				0x0641
-+#define REG_EIFS_8723D					0x0642
-+
-+#define REG_NAV_UPPER_8723D			0x0652	/* unit of 128 */
-+#define REG_TRXPTCL_CTL_8723D			0x0668
-+
-+/* Security */
-+#define REG_CAMCMD_8723D				0x0670
-+#define REG_CAMWRITE_8723D				0x0674
-+#define REG_CAMREAD_8723D				0x0678
-+#define REG_CAMDBG_8723D				0x067C
-+#define REG_SECCFG_8723D				0x0680
-+
-+/* Power */
-+#define REG_WOW_CTRL_8723D				0x0690
-+#define REG_PS_RX_INFO_8723D			0x0692
-+#define REG_UAPSD_TID_8723D				0x0693
-+#define REG_WKFMCAM_CMD_8723D			0x0698
-+#define REG_WKFMCAM_NUM_8723D			0x0698
-+#define REG_WKFMCAM_RWD_8723D			0x069C
-+#define REG_RXFLTMAP0_8723D				0x06A0
-+#define REG_RXFLTMAP1_8723D				0x06A2
-+#define REG_RXFLTMAP2_8723D				0x06A4
-+#define REG_BCN_PSR_RPT_8723D			0x06A8
-+#define REG_BT_COEX_TABLE_8723D		0x06C0
-+#define REG_BFMER0_INFO_8723D			0x06E4
-+#define REG_BFMER1_INFO_8723D			0x06EC
-+#define REG_CSI_RPT_PARAM_BW20_8723D	0x06F4
-+#define REG_CSI_RPT_PARAM_BW40_8723D	0x06F8
-+#define REG_CSI_RPT_PARAM_BW80_8723D	0x06FC
-+
-+/* Hardware Port 2 */
-+#define REG_MACID1_8723D				0x0700
-+#define REG_BSSID1_8723D				0x0708
-+#define REG_BFMEE_SEL_8723D				0x0714
-+#define REG_SND_PTCL_CTRL_8723D		0x0718
-+
-+/* LTR */
-+#define REG_LTR_CTRL_BASIC_8723D		0x07A4
-+#define REG_LTR_IDLE_LATENCY_V1_8723D		0x0798
-+#define REG_LTR_ACTIVE_LATENCY_V1_8723D		0x079C
-+
-+/* LTE_COEX */
-+#define REG_LTECOEX_CTRL			0x07C0
-+#define REG_LTECOEX_WRITE_DATA		0x07C4
-+#define REG_LTECOEX_READ_DATA		0x07C8
-+#define REG_LTECOEX_PATH_CONTROL	0x70
-+
-+/* ************************************************************
-+ * SDIO Bus Specification
-+ * ************************************************************ */
-+
-+/* -----------------------------------------------------
-+ * SDIO CMD Address Mapping
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ * I/O bus domain (Host)
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ * SDIO register
-+ * ----------------------------------------------------- */
-+#define SDIO_REG_HCPWM1_8723D	0x025 /* HCI Current Power Mode 1 */
-+
-+
-+/* ****************************************************************************
-+ *	8723 Regsiter Bit and Content definition
-+ * **************************************************************************** */
-+
-+#define BIT_USB_RXDMA_AGG_EN	BIT(31)
-+#define RXDMA_AGG_MODE_EN		BIT(1)
-+
-+#ifdef CONFIG_WOWLAN
-+	#define RXPKT_RELEASE_POLL		BIT(16)
-+	#define RXDMA_IDLE				BIT(17)
-+	#define RW_RELEASE_EN			BIT(18)
-+#endif
-+
-+/* 2 HSISR
-+ * interrupt mask which needs to clear */
-+#define MASK_HSISR_CLEAR		(HSISR_GPIO12_0_INT |\
-+		HSISR_SPS_OCP_INT |\
-+		HSISR_RON_INT |\
-+		HSISR_PDNINT |\
-+		HSISR_GPIO9_INT)
-+
-+#ifdef CONFIG_RF_POWER_TRIM
-+	#ifdef CONFIG_RTL8723D
-+		#define EEPROM_RF_GAIN_OFFSET			0xC1
-+	#endif
-+
-+	#define EEPROM_RF_GAIN_VAL				0x1F6
-+#endif /*CONFIG_RF_POWER_TRIM*/
-+
-+#ifdef CONFIG_PCI_HCI
-+	/* #define IMR_RX_MASK		(IMR_ROK_8723D|IMR_RDU_8723D|IMR_RXFOVW_8723D) */
-+	#define IMR_TX_MASK			(IMR_VODOK_8723D | IMR_VIDOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D | IMR_MGNTDOK_8723D | IMR_HIGHDOK_8723D)
-+
-+	#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8723D | IMR_TXBCN0OK_8723D | IMR_TXBCN0ERR_8723D | IMR_BCNDERR0_8723D)
-+
-+	#define RT_AC_INT_MASKS	(IMR_VIDOK_8723D | IMR_VODOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D)
-+#endif
-+
-+#endif /* __RTL8723D_SPEC_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723d_sreset.h b/drivers/staging/rtl8723cs/include/rtl8723d_sreset.h
-new file mode 100644
-index 000000000000..db75dba73e32
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723d_sreset.h
-@@ -0,0 +1,24 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8723D_SRESET_H_
-+#define _RTL8723D_SRESET_H_
-+
-+#include <rtw_sreset.h>
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	extern void rtl8723d_sreset_xmit_status_check(_adapter *padapter);
-+	extern void rtl8723d_sreset_linked_status_check(_adapter *padapter);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723d_xmit.h b/drivers/staging/rtl8723cs/include/rtl8723d_xmit.h
-new file mode 100644
-index 000000000000..91fb52c20f00
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723d_xmit.h
-@@ -0,0 +1,530 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8723D_XMIT_H__
-+#define __RTL8723D_XMIT_H__
-+
-+
-+#define MAX_TID (15)
-+
-+
-+#ifndef __INC_HAL8723DDESC_H
-+#define __INC_HAL8723DDESC_H
-+
-+#define RX_STATUS_DESC_SIZE_8723D		24
-+#define RX_DRV_INFO_SIZE_UNIT_8723D 8
-+
-+
-+/* DWORD 0 */
-+#define SET_RX_STATUS_DESC_PKT_LEN_8723D(__pRxStatusDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
-+#define SET_RX_STATUS_DESC_EOR_8723D(__pRxStatusDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
-+#define SET_RX_STATUS_DESC_OWN_8723D(__pRxStatusDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
-+
-+#define GET_RX_STATUS_DESC_PKT_LEN_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
-+#define GET_RX_STATUS_DESC_CRC32_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
-+#define GET_RX_STATUS_DESC_ICV_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
-+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
-+#define GET_RX_STATUS_DESC_SECURITY_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
-+#define GET_RX_STATUS_DESC_QOS_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
-+#define GET_RX_STATUS_DESC_SHIFT_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
-+#define GET_RX_STATUS_DESC_PHY_STATUS_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
-+#define GET_RX_STATUS_DESC_SWDEC_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
-+#define GET_RX_STATUS_DESC_EOR_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
-+#define GET_RX_STATUS_DESC_OWN_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
-+
-+/* DWORD 1 */
-+#define GET_RX_STATUS_DESC_MACID_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
-+#define GET_RX_STATUS_DESC_TID_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
-+#define GET_RX_STATUS_DESC_AMSDU_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
-+#define GET_RX_STATUS_DESC_RXID_MATCH_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
-+#define GET_RX_STATUS_DESC_PAGGR_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
-+#define GET_RX_STATUS_DESC_A1_FIT_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
-+#define GET_RX_STATUS_DESC_CHKERR_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
-+#define GET_RX_STATUS_DESC_IPVER_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
-+#define GET_RX_STATUS_DESC_IS_TCPUDP__8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
-+#define GET_RX_STATUS_DESC_CHK_VLD_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
-+#define GET_RX_STATUS_DESC_PAM_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
-+#define GET_RX_STATUS_DESC_PWR_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
-+#define GET_RX_STATUS_DESC_MORE_DATA_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
-+#define GET_RX_STATUS_DESC_MORE_FRAG_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
-+#define GET_RX_STATUS_DESC_TYPE_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
-+#define GET_RX_STATUS_DESC_MC_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
-+#define GET_RX_STATUS_DESC_BC_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
-+
-+/* DWORD 2 */
-+#define GET_RX_STATUS_DESC_SEQ_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
-+#define GET_RX_STATUS_DESC_FRAG_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
-+#define GET_RX_STATUS_DESC_RX_IS_QOS_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
-+#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
-+#define GET_RX_STATUS_DESC_RPT_SEL_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
-+#define GET_RX_STATUS_DESC_FCS_OK_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
-+
-+/* DWORD 3 */
-+#define GET_RX_STATUS_DESC_RX_RATE_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
-+#define GET_RX_STATUS_DESC_HTC_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
-+#define GET_RX_STATUS_DESC_EOSP_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
-+#define GET_RX_STATUS_DESC_BSSID_FIT_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
-+#ifdef CONFIG_USB_RX_AGGREGATION
-+#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
-+#endif
-+#define GET_RX_STATUS_DESC_PATTERN_MATCH_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
-+#define GET_RX_STATUS_DESC_UNICAST_MATCH_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
-+#define GET_RX_STATUS_DESC_MAGIC_MATCH_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
-+
-+/* DWORD 6 */
-+#define GET_RX_STATUS_DESC_MATCH_ID_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)
-+
-+/* DWORD 5 */
-+#define GET_RX_STATUS_DESC_TSFL_8723D(__pRxStatusDesc) \
-+	LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
-+
-+#define GET_RX_STATUS_DESC_BUFF_ADDR_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
-+#define GET_RX_STATUS_DESC_BUFF_ADDR64_8723D(__pRxDesc) \
-+	LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
-+
-+#define SET_RX_STATUS_DESC_BUFF_ADDR_8723D(__pRxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
-+
-+
-+/* Dword 0, rsvd: bit26, bit28 */
-+#define GET_TX_DESC_OWN_8723D(__pTxDesc)\
-+	LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
-+
-+#define SET_TX_DESC_PKT_SIZE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
-+#define SET_TX_DESC_OFFSET_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
-+#define SET_TX_DESC_BMC_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
-+#define SET_TX_DESC_HTC_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
-+#define SET_TX_DESC_AMSDU_PAD_EN_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
-+#define SET_TX_DESC_NO_ACM_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
-+#define SET_TX_DESC_GF_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
-+
-+/* Dword 1 */
-+#define SET_TX_DESC_MACID_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
-+#define SET_TX_DESC_QUEUE_SEL_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
-+#define SET_TX_DESC_RDG_NAV_EXT_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
-+#define SET_TX_DESC_LSIG_TXOP_EN_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
-+#define SET_TX_DESC_PIFS_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
-+#define SET_TX_DESC_RATE_ID_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
-+#define SET_TX_DESC_EN_DESC_ID_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
-+#define SET_TX_DESC_SEC_TYPE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
-+#define SET_TX_DESC_PKT_OFFSET_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
-+#define SET_TX_DESC_MORE_DATA_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
-+
-+/* Dword 2  remove P_AID, G_ID field*/
-+#define SET_TX_DESC_CCA_RTS_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
-+#define SET_TX_DESC_AGG_ENABLE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
-+#define SET_TX_DESC_RDG_ENABLE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
-+#define SET_TX_DESC_NULL0_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
-+#define SET_TX_DESC_NULL1_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
-+#define SET_TX_DESC_BK_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
-+#define SET_TX_DESC_MORE_FRAG_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
-+#define SET_TX_DESC_RAW_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
-+#define SET_TX_DESC_CCX_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
-+#define SET_TX_DESC_AMPDU_DENSITY_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
-+#define SET_TX_DESC_BT_INT_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
-+#define SET_TX_DESC_FTM_EN_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value)
-+
-+/* Dword 3 */
-+#define SET_TX_DESC_HWSEQ_SEL_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
-+#define SET_TX_DESC_USE_RATE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
-+#define SET_TX_DESC_DISABLE_RTS_FB_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
-+#define SET_TX_DESC_DISABLE_FB_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
-+#define SET_TX_DESC_CTS2SELF_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
-+#define SET_TX_DESC_RTS_ENABLE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
-+#define SET_TX_DESC_HW_RTS_ENABLE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
-+#define SET_TX_DESC_PORT_ID_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value)
-+#define SET_TX_DESC_NAV_USE_HDR_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
-+#define SET_TX_DESC_USE_MAX_LEN_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
-+#define SET_TX_DESC_MAX_AGG_NUM_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
-+#define SET_TX_DESC_AMPDU_MAX_TIME_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
-+
-+/* Dword 4 */
-+#define SET_TX_DESC_TX_RATE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
-+#define SET_TX_DESC_TX_TRY_RATE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
-+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
-+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
-+#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
-+#define SET_TX_DESC_DATA_RETRY_LIMIT_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
-+#define SET_TX_DESC_RTS_RATE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
-+#define SET_TX_DESC_PCTS_EN_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
-+#define SET_TX_DESC_PCTS_MASK_IDX_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
-+
-+/* Dword 5 */
-+#define SET_TX_DESC_DATA_SC_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
-+#define SET_TX_DESC_DATA_SHORT_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
-+#define SET_TX_DESC_DATA_BW_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
-+#define SET_TX_DESC_DATA_STBC_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
-+#define SET_TX_DESC_RTS_STBC_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
-+#define SET_TX_DESC_RTS_SHORT_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
-+#define SET_TX_DESC_RTS_SC_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
-+#define SET_TX_DESC_PATH_A_EN_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)
-+#define SET_TX_DESC_TXPWR_OF_SET_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
-+
-+/* Dword 6 */
-+#define SET_TX_DESC_SW_DEFINE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
-+#define SET_TX_DESC_MBSSID_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
-+#define SET_TX_DESC_RF_SEL_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
-+
-+/* Dword 7 */
-+#ifdef CONFIG_PCI_HCI
-+#define SET_TX_DESC_TX_BUFFER_SIZE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+#define SET_TX_DESC_TX_DESC_CHECKSUM_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+#endif
-+
-+#ifdef CONFIG_SDIO_HCI
-+#define SET_TX_DESC_TX_TIMESTAMP_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
-+#endif
-+
-+#define SET_TX_DESC_USB_TXAGG_NUM_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
-+
-+/* Dword 8 */
-+#define SET_TX_DESC_RTS_RC_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
-+#define SET_TX_DESC_BAR_RC_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
-+#define SET_TX_DESC_DATA_RC_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
-+#define SET_TX_DESC_HWSEQ_EN_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
-+#define SET_TX_DESC_NEXTHEADPAGE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
-+#define SET_TX_DESC_TAILPAGE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
-+
-+/* Dword 9 */
-+#define SET_TX_DESC_PADDING_LEN_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
-+#define SET_TX_DESC_SEQ_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
-+#define SET_TX_DESC_FINAL_DATA_RATE_8723D(__pTxDesc, __Value) \
-+	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
-+
-+
-+#define SET_EARLYMODE_PKTNUM_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
-+#define SET_EARLYMODE_LEN0_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
-+#define SET_EARLYMODE_LEN1_1_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
-+#define SET_EARLYMODE_LEN1_2_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
-+#define SET_EARLYMODE_LEN2_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,	__Value)
-+#define SET_EARLYMODE_LEN3_8723D(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
-+
-+
-+/*-----------------------------------------------------------------*/
-+/*	RTL8723D TX BUFFER DESC                                      */
-+/*-----------------------------------------------------------------*/
-+#ifdef CONFIG_64BIT_DMA
-+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
-+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
-+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
-+	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
-+#else
-+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
-+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
-+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
-+	#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu)	/* 64 BIT mode only */
-+#endif
-+/* ********************************************************* */
-+
-+/* 64 bits  -- 32 bits */
-+/* =======     ======= */
-+/* Dword 0     0 */
-+#define SET_TX_BUFF_DESC_LEN_0_8723D(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
-+#define SET_TX_BUFF_DESC_PSB_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
-+#define SET_TX_BUFF_DESC_OWN_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
-+
-+/* Dword 1     1 */
-+#define SET_TX_BUFF_DESC_ADDR_LOW_0_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
-+#define GET_TX_BUFF_DESC_ADDR_LOW_0_8723D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
-+/* Dword 2     NA */
-+#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)
-+#ifdef CONFIG_64BIT_DMA
-+	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
-+#else
-+	#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc) 0
-+#endif
-+/* Dword 3     NA */
-+/* RESERVED 0 */
-+/* Dword 4     2 */
-+#define SET_TX_BUFF_DESC_LEN_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)
-+#define SET_TX_BUFF_DESC_AMSDU_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)
-+/* Dword 5     3 */
-+#define SET_TX_BUFF_DESC_ADDR_LOW_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)
-+/* Dword 6     NA */
-+#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)
-+/* Dword 7     NA */
-+/*RESERVED 0 */
-+/* Dword 8     4 */
-+#define SET_TX_BUFF_DESC_LEN_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)
-+#define SET_TX_BUFF_DESC_AMSDU_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)
-+/* Dword 9     5 */
-+#define SET_TX_BUFF_DESC_ADDR_LOW_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)
-+/* Dword 10    NA */
-+#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)
-+/* Dword 11    NA */
-+/*RESERVED 0 */
-+/* Dword 12    6 */
-+#define SET_TX_BUFF_DESC_LEN_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)
-+#define SET_TX_BUFF_DESC_AMSDU_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)
-+/* Dword 13    7 */
-+#define SET_TX_BUFF_DESC_ADDR_LOW_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)
-+/* Dword 14    NA */
-+#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)
-+/* Dword 15    NA */
-+/*RESERVED 0 */
-+
-+
-+#endif
-+/* -----------------------------------------------------------
-+ *
-+ *	Rate
-+ *
-+ * -----------------------------------------------------------
-+ * CCK Rates, TxHT = 0 */
-+#define DESC8723D_RATE1M				0x00
-+#define DESC8723D_RATE2M				0x01
-+#define DESC8723D_RATE5_5M				0x02
-+#define DESC8723D_RATE11M				0x03
-+
-+/* OFDM Rates, TxHT = 0 */
-+#define DESC8723D_RATE6M				0x04
-+#define DESC8723D_RATE9M				0x05
-+#define DESC8723D_RATE12M				0x06
-+#define DESC8723D_RATE18M				0x07
-+#define DESC8723D_RATE24M				0x08
-+#define DESC8723D_RATE36M				0x09
-+#define DESC8723D_RATE48M				0x0a
-+#define DESC8723D_RATE54M				0x0b
-+
-+/* MCS Rates, TxHT = 1 */
-+#define DESC8723D_RATEMCS0				0x0c
-+#define DESC8723D_RATEMCS1				0x0d
-+#define DESC8723D_RATEMCS2				0x0e
-+#define DESC8723D_RATEMCS3				0x0f
-+#define DESC8723D_RATEMCS4				0x10
-+#define DESC8723D_RATEMCS5				0x11
-+#define DESC8723D_RATEMCS6				0x12
-+#define DESC8723D_RATEMCS7				0x13
-+#define DESC8723D_RATEMCS8				0x14
-+#define DESC8723D_RATEMCS9				0x15
-+#define DESC8723D_RATEMCS10		0x16
-+#define DESC8723D_RATEMCS11		0x17
-+#define DESC8723D_RATEMCS12		0x18
-+#define DESC8723D_RATEMCS13		0x19
-+#define DESC8723D_RATEMCS14		0x1a
-+#define DESC8723D_RATEMCS15		0x1b
-+#define DESC8723D_RATEVHTSS1MCS0		0x2c
-+#define DESC8723D_RATEVHTSS1MCS1		0x2d
-+#define DESC8723D_RATEVHTSS1MCS2		0x2e
-+#define DESC8723D_RATEVHTSS1MCS3		0x2f
-+#define DESC8723D_RATEVHTSS1MCS4		0x30
-+#define DESC8723D_RATEVHTSS1MCS5		0x31
-+#define DESC8723D_RATEVHTSS1MCS6		0x32
-+#define DESC8723D_RATEVHTSS1MCS7		0x33
-+#define DESC8723D_RATEVHTSS1MCS8		0x34
-+#define DESC8723D_RATEVHTSS1MCS9		0x35
-+#define DESC8723D_RATEVHTSS2MCS0		0x36
-+#define DESC8723D_RATEVHTSS2MCS1		0x37
-+#define DESC8723D_RATEVHTSS2MCS2		0x38
-+#define DESC8723D_RATEVHTSS2MCS3		0x39
-+#define DESC8723D_RATEVHTSS2MCS4		0x3a
-+#define DESC8723D_RATEVHTSS2MCS5		0x3b
-+#define DESC8723D_RATEVHTSS2MCS6		0x3c
-+#define DESC8723D_RATEVHTSS2MCS7		0x3d
-+#define DESC8723D_RATEVHTSS2MCS8		0x3e
-+#define DESC8723D_RATEVHTSS2MCS9		0x3f
-+
-+
-+#define	RX_HAL_IS_CCK_RATE_8723D(pDesc)\
-+	(GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE1M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE2M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE5_5M || \
-+	 GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE11M)
-+
-+#ifdef CONFIG_TRX_BD_ARCH
-+	struct tx_desc;
-+#endif
-+
-+void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc);
-+void rtl8723d_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
-+void rtl8723d_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
-+void rtl8723d_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
-+void rtl8723d_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
-+void rtl8723d_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
-+
-+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	s32 rtl8723ds_init_xmit_priv(PADAPTER padapter);
-+	void rtl8723ds_free_xmit_priv(PADAPTER padapter);
-+	s32 rtl8723ds_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8723ds_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8723ds_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	rtl8723ds_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8723ds_xmit_buf_handler(PADAPTER padapter);
-+	thread_return rtl8723ds_xmit_thread(thread_context context);
-+	#define hal_xmit_handler rtl8723ds_xmit_buf_handler
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	s32 rtl8723du_xmit_buf_handler(PADAPTER padapter);
-+	#define hal_xmit_handler rtl8723du_xmit_buf_handler
-+	s32 rtl8723du_init_xmit_priv(PADAPTER padapter);
-+	void rtl8723du_free_xmit_priv(PADAPTER padapter);
-+	s32 rtl8723du_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8723du_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8723du_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	 rtl8723du_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	void rtl8723du_xmit_tasklet(void *priv);
-+	s32 rtl8723du_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+	void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, struct tx_desc *ptxdesc);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8723de_init_xmit_priv(PADAPTER padapter);
-+	void rtl8723de_free_xmit_priv(PADAPTER padapter);
-+	struct xmit_buf *rtl8723de_dequeue_xmitbuf(struct rtw_tx_ring *ring);
-+	void	rtl8723de_xmitframe_resume(_adapter *padapter);
-+	s32 rtl8723de_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8723de_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8723de_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	rtl8723de_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	void rtl8723de_xmit_tasklet(void *priv);
-+#endif
-+
-+u8	BWMapping_8723D(PADAPTER Adapter, struct pkt_attrib *pattrib);
-+u8	SCMapping_8723D(PADAPTER Adapter, struct pkt_attrib	*pattrib);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723f_hal.h b/drivers/staging/rtl8723cs/include/rtl8723f_hal.h
-new file mode 100644
-index 000000000000..ff95cbee349b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723f_hal.h
-@@ -0,0 +1,262 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8723F_HAL_H_
-+#define _RTL8723F_HAL_H_
-+
-+#include <osdep_service.h>		/* BIT(x) */
-+#include <drv_types.h>			/* PADAPTER */
-+#include "../hal/halmac/halmac_api.h"	/* MAC REG definition */
-+
-+#define MAX_RECVBUF_SZ		16384	/* 16KB (RX_FIFO_SIZE_8723F), TX: 32KB */
-+
-+/*
-+ * MAC Register definition
-+ */
-+#define REG_LEDCFG0		REG_LED_CFG_8723F	/* rtw_mp.c */
-+#define MSR			(REG_CR_8723F + 2)	/* rtw_mp.c & hal_com.c */
-+#define MSR1			REG_CR_EXT_8723F	/* rtw_mp.c & hal_com.c */
-+#define REG_C2HEVT_MSG_NORMAL	0x1A0			/* hal_com.c */
-+#define REG_C2HEVT_CLEAR	0x1AF			/* hal_com.c */
-+#define REG_BCN_CTRL_1		REG_BCN_CTRL_CLINT0_8723F	/* hal_com.c */
-+
-+#define REG_WOWLAN_WAKE_REASON	0x01C7 /* hal_com.c */
-+#define REG_GPIO_PIN_CTRL_2 		REG_GPIO_EXT_CTRL_8723F	/* hal_com.c */
-+#define REG_FIFOPAGE 				REG_FIFOPAGE_INFO_8723F /* hal_com.c */
-+#define REG_RXPKTBUF_CTRL 			REG_PKTBUF_DBG_CTRL_8723F /* hal_com.c */
-+#define REG_WKFMCAM_NUM 			REG_WKFMCAM_CMD_8723F /* hal_com.c */
-+#define REG_RSV_CTRL 				REG_REG_ACCESS_CTRL_8723F /* hal_com.c */
-+#define REG_CAMCMD					REG_KEYCAMCMD_8723F /* hal_com.c */
-+#define REG_CAMWRITE				REG_KEYCAM_WD_8723F /* hal_com.c */
-+
-+#define BIT_AUTO_SYNC_BY_TBTT 		BIT_EN_TSFAUTO_SYNC_8723F /* hal_com.c */
-+#define BIT_DIS_ATIM_ROOT_8723F  	23 /* REG_HIQ_NO_LMT_EN_V2[23], disable ATIM ROOT */
-+#define BIT_SECCAM_POLLING_8723F	BIT_KEYCAM_POLLING_8723F /* rtl8723f_ops.c */
-+#define BIT_GET_NETYPE2				BIT_GET_P2_NETSTATE_8723F /* hal_halmac.c */
-+#define BIT_GET_NETYPE3				BIT_GET_P3_NETSTATE_8723F /* hal_halmac.c */
-+#define BIT_GET_NETYPE4				BIT_GET_P4_NETSTATE_8723F /* hal_halmac.c */
-+
-+#ifdef CONFIG_WOW_PATTERN_IN_TXFIFO
-+/* todo: 8723F , need to check in the future */
-+#define REG_TXBUF_WKCAM_OFFSET 0x1B4 //BIT_TXBUF_WKCAM_OFFSET [24:12]
-+#define REG_PKT_BUFF_ACCESS_CTRL 	0x106 /* hal_com.c */
-+#endif
-+
-+/* RXERR_RPT, for rtw_mp.c */
-+#define RXERR_TYPE_OFDM_PPDU		0
-+#define RXERR_TYPE_OFDM_FALSE_ALARM	2
-+#define RXERR_TYPE_OFDM_MPDU_OK		0
-+#define RXERR_TYPE_OFDM_MPDU_FAIL	1
-+#define RXERR_TYPE_CCK_PPDU		3
-+#define RXERR_TYPE_CCK_FALSE_ALARM	5
-+#define RXERR_TYPE_CCK_MPDU_OK		3
-+#define RXERR_TYPE_CCK_MPDU_FAIL	4
-+#define RXERR_TYPE_HT_PPDU		8
-+#define RXERR_TYPE_HT_FALSE_ALARM	9
-+#define RXERR_TYPE_HT_MPDU_TOTAL	6
-+#define RXERR_TYPE_HT_MPDU_OK		6
-+#define RXERR_TYPE_HT_MPDU_FAIL		7
-+#define RXERR_TYPE_RX_FULL_DROP		10
-+
-+#define RXERR_COUNTER_MASK		BIT_MASK_RPT_COUNTER_8723F
-+#define RXERR_RPT_RST			BIT_RXERR_RPT_RST_8723F
-+#define _RXERR_RPT_SEL(type)		(BIT_RXERR_RPT_SEL_V1_3_0_8723F(type) \
-+					| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8723F : 0))
-+
-+/*
-+ * BB Register definition
-+ */
-+#define rPMAC_Reset			0x100	/* hal_mp.c */
-+
-+#define	rFPGA0_RFMOD			0x800
-+#define rFPGA0_TxInfo			0x804
-+#define rOFDMCCKEN_Jaguar		0x808	/* hal_mp.c */
-+#define rFPGA0_TxGainStage		0x80C	/* phydm only */
-+#define rFPGA0_XA_HSSIParameter1	0x820	/* hal_mp.c */
-+#define rFPGA0_XA_HSSIParameter2	0x824	/* hal_mp.c */
-+#define rFPGA0_XB_HSSIParameter1	0x828	/* hal_mp.c */
-+#define rFPGA0_XB_HSSIParameter2	0x82C	/* hal_mp.c */
-+#define rTxAGC_B_Rate18_06		0x830
-+#define rTxAGC_B_Rate54_24		0x834
-+#define rTxAGC_B_CCK1_55_Mcs32		0x838
-+#define rCCAonSec_Jaguar		0x838	/* hal_mp.c */
-+#define rTxAGC_B_Mcs03_Mcs00		0x83C
-+#define rTxAGC_B_Mcs07_Mcs04		0x848
-+#define rTxAGC_B_Mcs11_Mcs08		0x84C
-+#define rFPGA0_XA_RFInterfaceOE		0x860
-+#define rFPGA0_XB_RFInterfaceOE		0x864
-+#define rTxAGC_B_Mcs15_Mcs12		0x868
-+#define rTxAGC_B_CCK11_A_CCK2_11	0x86C
-+#define rFPGA0_XAB_RFInterfaceSW	0x870
-+#define rFPGA0_XAB_RFParameter		0x878
-+#define rFPGA0_AnalogParameter4		0x88C	/* hal_mp.c & phydm */
-+#define rFPGA0_XB_LSSIReadBack		0x8A4	/* phydm */
-+#define rHSSIRead_Jaguar		0x8B0	/* RF read addr (rtl8723f_phy.c) */
-+
-+#define rC_TxScale_Jaguar2		0x181C  /* Pah_C TX scaling factor (hal_mp.c) */
-+#define rC_IGI_Jaguar2			0x1850	/* Initial Gain for path-C (hal_mp.c) */
-+
-+#define rFPGA1_TxInfo			0x90C	/* hal_mp.c */
-+#define rSingleTone_ContTx_Jaguar	0x914	/* hal_mp.c */
-+/* TX BeamForming */
-+#define REG_BB_TX_PATH_SEL_1_8723F	0x93C	/* rtl8723f_phy.c */
-+#define REG_BB_TX_PATH_SEL_2_8723F	0x940	/* rtl8723f_phy.c */
-+
-+/* TX BeamForming */
-+#define REG_BB_TXBF_ANT_SET_BF1_8723F	0x19AC	/* rtl8723f_phy.c */
-+#define REG_BB_TXBF_ANT_SET_BF0_8723F	0x19B4	/* rtl8723f_phy.c */
-+
-+#define rCCK0_System			0xA00
-+#define rCCK0_AFESetting		0xA04
-+
-+#define rCCK0_DSPParameter2		0xA1C
-+#define rCCK0_TxFilter1			0xA20
-+#define rCCK0_TxFilter2			0xA24
-+#define rCCK0_DebugPort			0xA28
-+#define rCCK0_FalseAlarmReport		0xA2C
-+
-+#define rD_TxScale_Jaguar2		0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */
-+#define rD_IGI_Jaguar2			0x1A50	/* Initial Gain for path-D (hal_mp.c) */
-+
-+#define rOFDM0_TRxPathEnable		0xC04
-+#define rOFDM0_TRMuxPar			0xC08
-+#define rA_TxScale_Jaguar		0xC1C	/* Pah_A TX scaling factor (hal_mp.c) */
-+#define rOFDM0_RxDetector1		0xC30	/* rtw_mp.c */
-+#define rOFDM0_ECCAThreshold		0xC4C	/* phydm only */
-+#define rOFDM0_XAAGCCore1		0xC50	/* phydm only */
-+#define rA_IGI_Jaguar			0xC50	/* Initial Gain for path-A (hal_mp.c) */
-+#define rOFDM0_XBAGCCore1		0xC58	/* phydm only */
-+#define rOFDM0_XATxIQImbalance		0xC80	/* phydm only */
-+#define rA_LSSIWrite_Jaguar		0xC90	/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
-+
-+#define rOFDM1_LSTF			0xD00
-+#define rOFDM1_TRxPathEnable		0xD04	/* hal_mp.c */
-+#define rA_PIRead_Jaguar		0xD04	/* RF readback with PI (rtl8723f_phy.c) */
-+#define rA_SIRead_Jaguar		0xD08	/* RF readback with SI (rtl8723f_phy.c) */
-+#define rB_PIRead_Jaguar		0xD44	/* RF readback with PI (rtl8723f_phy.c) */
-+#define rB_SIRead_Jaguar		0xD48	/* RF readback with SI (rtl8723f_phy.c) */
-+
-+#define rTxAGC_A_Rate18_06		0xE00
-+#define rTxAGC_A_Rate54_24		0xE04
-+#define rTxAGC_A_CCK1_Mcs32		0xE08
-+#define rTxAGC_A_Mcs03_Mcs00		0xE10
-+#define rTxAGC_A_Mcs07_Mcs04		0xE14
-+#define rTxAGC_A_Mcs11_Mcs08		0xE18
-+#define rTxAGC_A_Mcs15_Mcs12		0xE1C
-+#define rB_TxScale_Jaguar		0xE1C	/* Path_B TX scaling factor (hal_mp.c) */
-+#define rB_IGI_Jaguar			0xE50	/* Initial Gain for path-B (hal_mp.c) */
-+#define rB_LSSIWrite_Jaguar		0xE90	/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
-+/* RFE */
-+#define rA_RFE_Pinmux_Jaguar		0xCB0	/* hal_mp.c */
-+#define rB_RFE_Pinmux_Jaguar		0xEB0	/* Path_B RFE control pinmux */
-+#define rA_RFE_Inv_Jaguar		0xCB4	/* Path_A RFE cotrol */  
-+#define rB_RFE_Inv_Jaguar		0xEB4	/* Path_B RFE control */
-+#define rA_RFE_Jaguar			0xCB8 	/* Path_A RFE cotrol */  
-+#define rB_RFE_Jaguar			0xEB8	/* Path_B RFE control */
-+#define rA_RFE_Inverse_Jaguar		0xCBC	/* Path_A RFE control inverse */
-+#define rB_RFE_Inverse_Jaguar		0xEBC	/* Path_B RFE control inverse */
-+#define r_ANTSEL_SW_Jaguar		0x900	/* ANTSEL SW Control */
-+#define bMask_RFEInv_Jaguar		0x3FF00000
-+#define bMask_AntselPathFollow_Jaguar	0x00030000
-+
-+#define rC_RFE_Pinmux_Jaguar		0x18B4	/* Path_C RFE cotrol pinmux*/
-+#define rD_RFE_Pinmux_Jaguar		0x1AB4	/* Path_D RFE cotrol pinmux*/
-+#define rA_RFE_Sel_Jaguar2		0x1990
-+
-+/* Page1(0x100) */
-+#define bBBResetB			0x100
-+
-+/* Page8(0x800) */
-+#define bCCKEn				0x1000000
-+#define bOFDMEn				0x2000000
-+/* Reg 0x80C rFPGA0_TxGainStage */
-+#define bXBTxAGC			0xF00
-+#define bXCTxAGC			0xF000
-+#define bXDTxAGC			0xF0000
-+
-+/* PageA(0xA00) */
-+#define bCCKBBMode			0x3
-+
-+#define bCCKScramble			0x8
-+#define bCCKTxRate			0x3000
-+
-+/* General */
-+#define bMaskByte0		0xFF		/* mp, rtw_odm.c & phydm */
-+#define bMaskByte1		0xFF00		/* hal_mp.c & phydm */
-+#define bMaskByte2		0xFF0000	/* hal_mp.c & phydm */
-+#define bMaskByte3		0xFF000000	/* hal_mp.c & phydm */
-+#define bMaskHWord		0xFFFF0000	/* hal_com.c, rtw_mp.c */
-+#define bMaskLWord		0x0000FFFF	/* mp, hal_com.c & phydm */
-+#define bMaskDWord		0xFFFFFFFF	/* mp, hal, rtw_odm.c & phydm */
-+
-+#define bEnable			0x1		/* hal_mp.c, rtw_mp.c */
-+#define bDisable		0x0		/* rtw_mp.c */
-+
-+#define MAX_STALL_TIME		50		/* unit: us, hal_com_phycfg.c */
-+
-+#define Rx_Smooth_Factor	20		/* phydm only */
-+
-+/*
-+ * RF Register definition
-+ */
-+#define RF_AC			0x00
-+#define RF_AC_Jaguar		0x00	/* hal_mp.c */
-+#define RF_CHNLBW		0x18	/* rtl8723f_phy.c */
-+#define RF_ModeTableAddr	0x30	/* rtl8723f_phy.c */
-+#define RF_ModeTableData0	0x31	/* rtl8723f_phy.c */
-+#define RF_ModeTableData1	0x32	/* rtl8723f_phy.c */
-+#define RF_0x52			0x52
-+#define RF_WeLut_Jaguar		0xEF	/* rtl8723f_phy.c */
-+
-+/* rtw_lps_state_chk() @hal_com.c */
-+#define BIT_PWRBIT_OW_EN	BIT_WMAC_TCR_PWRMGT_CTL_8723F
-+
-+
-+/* 
-+* Structure 
-+*/
-+struct qinfo_8723f {
-+	u32 head:8;
-+	u32 pkt_num:7;
-+	u32 tail:8;
-+	u32 ac:2;
-+	u32 macid:7;
-+};
-+
-+struct bcn_qinfo_8723f {
-+	u16 head:8;
-+	u16 pkt_num:8;
-+};
-+
-+
-+/* 
-+* General Functions 
-+*/
-+void rtl8723f_init_hal_spec(PADAPTER);				/* hal/hal_com.c */
-+
-+#ifdef CONFIG_MP_INCLUDED
-+/* MP Functions */
-+#include <rtw_mp.h>		/* struct mp_priv */
-+void rtl8723f_prepare_mp_txdesc(PADAPTER, struct mp_priv *);	/* rtw_mp.c */
-+void rtl8723f_mp_config_rfpath(PADAPTER);			/* hal_mp.c */
-+#endif
-+void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
-+
-+#ifdef CONFIG_USB_HCI
-+#include <rtl8723fu_hal.h>
-+#elif defined(CONFIG_SDIO_HCI)
-+#include <rtl8723fs_hal.h>
-+#endif
-+
-+#endif /* _RTL8723F_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723fs_hal.h b/drivers/staging/rtl8723cs/include/rtl8723fs_hal.h
-new file mode 100644
-index 000000000000..f1b938af6cc0
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723fs_hal.h
-@@ -0,0 +1,31 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8723FS_HAL_H_
-+#define _RTL8723FS_HAL_H_
-+
-+#include <drv_types.h>		/* PADAPTER */
-+
-+/* rtl8723fs_ops.c */
-+void rtl8723fs_set_hal_ops(PADAPTER);
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+void rtl8723fs_disable_interrupt_but_cpwm2(PADAPTER adapter);
-+#endif
-+
-+/* rtl8723fs_xmit.c */
-+s32 rtl8723fs_dequeue_writeport(PADAPTER);
-+#define _dequeue_writeport(a)	rtl8723fs_dequeue_writeport(a)
-+
-+#endif /* _RTL8723FS_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8723fu_hal.h b/drivers/staging/rtl8723cs/include/rtl8723fu_hal.h
-new file mode 100644
-index 000000000000..69de77600bbc
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8723fu_hal.h
-@@ -0,0 +1,61 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8723FU_HAL_H_
-+#define _RTL8723FU_HAL_H_
-+
-+#ifdef CONFIG_USB_HCI
-+	#include <drv_types.h>		/* PADAPTER */
-+
-+	#ifdef CONFIG_USB_HCI
-+		#ifdef USB_PACKET_OFFSET_SZ
-+			#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)
-+		#else
-+			#define PACKET_OFFSET_SZ (8)
-+		#endif
-+		#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
-+	#endif
-+
-+	/* undefine MAX_RECVBUF_SZ from rtl8723f_hal.h  */
-+	#ifdef MAX_RECVBUF_SZ
-+		#undef MAX_RECVBUF_SZ
-+	#endif
-+
-+	/* recv_buffer must be large than usb agg size */
-+	#ifndef MAX_RECVBUF_SZ
-+		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
-+			#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
-+				#define MAX_RECVBUF_SZ (15360) /* 15k */
-+				#elif defined(CONFIG_PLATFORM_HISILICON)
-+				/* use 16k to workaround for HISILICON platform */
-+				#define MAX_RECVBUF_SZ (16384)
-+			#else
-+				#define MAX_RECVBUF_SZ (32768)
-+			#endif
-+		#else
-+			#define MAX_RECVBUF_SZ (4000)
-+		#endif
-+	#endif /* !MAX_RECVBUF_SZ */
-+
-+	/* rtl8723fu_ops.c */
-+	void rtl8723fu_set_hal_ops(PADAPTER padapter);
-+	void rtl8723fu_set_hw_type(struct dvobj_priv *pdvobj);
-+
-+	/* rtl8723fu_io.c */
-+	void rtl8723fu_set_intf_ops(struct _io_ops *pops);
-+
-+#endif /* CONFIG_USB_HCI */
-+
-+
-+#endif /* _RTL8723FU_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8812a_cmd.h b/drivers/staging/rtl8723cs/include/rtl8812a_cmd.h
-new file mode 100644
-index 000000000000..4a3473683bb7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8812a_cmd.h
-@@ -0,0 +1,152 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8812A_CMD_H__
-+#define __RTL8812A_CMD_H__
-+
-+typedef enum _RTL8812_H2C_CMD {
-+	H2C_8812_RSVDPAGE = 0,
-+	H2C_8812_MSRRPT = 1,
-+	H2C_8812_SCAN = 2,
-+	H2C_8812_KEEP_ALIVE_CTRL = 3,
-+	H2C_8812_DISCONNECT_DECISION = 4,
-+
-+	H2C_8812_INIT_OFFLOAD = 6,
-+	H2C_8812_AP_OFFLOAD = 8,
-+	H2C_8812_BCN_RSVDPAGE = 9,
-+	H2C_8812_PROBERSP_RSVDPAGE = 10,
-+
-+	H2C_8812_SETPWRMODE = 0x20,
-+	H2C_8812_PS_TUNING_PARA = 0x21,
-+	H2C_8812_PS_TUNING_PARA2 = 0x22,
-+	H2C_8812_PS_LPS_PARA = 0x23,
-+	H2C_8812_P2P_PS_OFFLOAD = 0x24,
-+	H2C_8812_INACTIVE_PS = 0x27,
-+	H2C_8812_RA_MASK = 0x40,
-+	H2C_8812_TxBF = 0x41,
-+	H2C_8812_RSSI_REPORT = 0x42,
-+	H2C_8812_IQ_CALIBRATION = 0x45,
-+	H2C_8812_RA_PARA_ADJUST = 0x46,
-+
-+	H2C_8812_BT_FW_PATCH = 0x6a,
-+
-+	H2C_8812_WO_WLAN = 0x80,
-+	H2C_8812_REMOTE_WAKE_CTRL = 0x81,
-+	H2C_8812_AOAC_GLOBAL_INFO = 0x82,
-+	H2C_8812_AOAC_RSVDPAGE = 0x83,
-+	H2C_8812_FW_SWCHANNL = 0x87,
-+
-+	H2C_8812_TSF_RESET = 0xC0,
-+
-+	MAX_8812_H2CCMD
-+} RTL8812_H2C_CMD;
-+
-+struct cmd_msg_parm {
-+	u8 eid; /* element id */
-+	u8 sz; /* sz */
-+	u8 buf[6];
-+};
-+
-+enum {
-+	PWRS
-+};
-+
-+struct H2C_SS_RFOFF_PARAM {
-+	u8 ROFOn; /* 1: on, 0:off */
-+	u16 gpio_period; /* unit: 1024 us */
-+} __attribute__((packed));
-+
-+
-+
-+/* _RSVDPAGE_LOC_CMD0 */
-+#define SET_8812_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8812_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_8812_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8812_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8812_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+/* _SETPWRMODE_PARM */
-+#define SET_8812_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8812_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
-+#define SET_8812_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
-+#define SET_8812_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8812_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8812_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
-+#define SET_8812_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+#define GET_8812_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)							LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
-+
-+/* _P2P_PS_OFFLOAD */
-+#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
-+#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
-+#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
-+#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
-+
-+
-+void	set_ra_ldpc_8812(struct cmn_sta_info *cmn_sta_info, BOOLEAN bLDPC);
-+
-+/* host message to firmware cmd */
-+s32 fill_h2c_cmd_8812(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
-+void rtl8812_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode);
-+void rtl8812_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
-+u8 rtl8812_set_rssi_cmd(PADAPTER padapter, u8 *param);
-+void rtl8812_set_wowlan_cmd(_adapter *padapter, u8 enable);
-+u8 GetTxBufferRsvdPageNum8812(_adapter *padapter, bool wowlan);
-+
-+#ifdef CONFIG_BT_COEXIST
-+void rtl8812a_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
-+#endif /* CONFIG_BT_COEXIST */
-+#ifdef CONFIG_P2P_PS
-+void rtl8812_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
-+#endif /* CONFIG_P2P */
-+
-+#ifdef CONFIG_FWLPS_IN_IPS
-+void rtl8812_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
-+#endif
-+
-+/* ------------------------------------
-+ * C2H format
-+ * ------------------------------------ */
-+
-+/* TX Beamforming */
-+#define GET_8812_C2H_TXBF_ORIGINATE(_Header)			LE_BITS_TO_1BYTE(_Header, 0, 8)
-+#define GET_8812_C2H_TXBF_MACID(_Header)				LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
-+
-+
-+
-+/* / TX Feedback Content */
-+#define	USEC_UNIT_FOR_8812_C2H_TX_RPT_QUEUE_TIME			256
-+
-+#define	GET_8812_C2H_TX_RPT_QUEUE_SELECT(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 0, 5)
-+#define	GET_8812_C2H_TX_RPT_PKT_BROCAST(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 5, 1)
-+#define	GET_8812_C2H_TX_RPT_LIFE_TIME_OVER(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
-+#define	GET_8812_C2H_TX_RPT_RETRY_OVER(_Header)				LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
-+#define	GET_8812_C2H_TX_RPT_MAC_ID(_Header)					LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
-+#define	GET_8812_C2H_TX_RPT_DATA_RETRY_CNT(_Header)		LE_BITS_TO_1BYTE((_Header + 2), 0, 6)
-+#define	GET_8812_C2H_TX_RPT_QUEUE_TIME(_Header)				LE_BITS_TO_2BYTE((_Header + 3), 0, 16)	/* In unit of 256 microseconds. */
-+#define	GET_8812_C2H_TX_RPT_FINAL_DATA_RATE(_Header)		LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
-+
-+/* BT_FW_PATCH */
-+#define SET_8812_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value)					SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
-+#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+4, 0, 8, __Value)
-+#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+5, 0, 8, __Value)
-+
-+s32 c2h_handler_8812a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
-+
-+#endif/* __RTL8812A_CMD_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8812a_dm.h b/drivers/staging/rtl8723cs/include/rtl8812a_dm.h
-new file mode 100644
-index 000000000000..21a9abaa6118
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8812a_dm.h
-@@ -0,0 +1,27 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8812A_DM_H__
-+#define __RTL8812A_DM_H__
-+
-+void rtl8812_init_dm_priv(PADAPTER Adapter);
-+void rtl8812_deinit_dm_priv(PADAPTER Adapter);
-+void rtl8812_InitHalDm(PADAPTER Adapter);
-+void rtl8812_HalDmWatchDog(PADAPTER Adapter);
-+
-+/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
-+
-+/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8812a_hal.h b/drivers/staging/rtl8723cs/include/rtl8812a_hal.h
-new file mode 100644
-index 000000000000..3082c67c9e25
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8812a_hal.h
-@@ -0,0 +1,369 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8812A_HAL_H__
-+#define __RTL8812A_HAL_H__
-+
-+/* #include "hal_com.h" */
-+#include "hal_data.h"
-+
-+/* include HAL Related header after HAL Related compiling flags */
-+#include "rtl8812a_spec.h"
-+#include "rtl8812a_rf.h"
-+#include "rtl8812a_dm.h"
-+#include "rtl8812a_recv.h"
-+#include "rtl8812a_xmit.h"
-+#include "rtl8812a_cmd.h"
-+#include "rtl8812a_led.h"
-+#include "Hal8812PwrSeq.h"
-+#include "Hal8821APwrSeq.h" /* for 8821A/8811A */
-+#include "Hal8812PhyReg.h"
-+#include "Hal8812PhyCfg.h"
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+#include "rtl8812a_sreset.h"
-+#endif
-+
-+/* ---------------------------------------------------------------------
-+ *		RTL8812 Power Configuration CMDs for PCIe interface
-+ * --------------------------------------------------------------------- */
-+#define Rtl8812_NIC_PWR_ON_FLOW				rtl8812_power_on_flow
-+#define Rtl8812_NIC_RF_OFF_FLOW				rtl8812_radio_off_flow
-+#define Rtl8812_NIC_DISABLE_FLOW				rtl8812_card_disable_flow
-+#define Rtl8812_NIC_ENABLE_FLOW				rtl8812_card_enable_flow
-+#define Rtl8812_NIC_SUSPEND_FLOW				rtl8812_suspend_flow
-+#define Rtl8812_NIC_RESUME_FLOW				rtl8812_resume_flow
-+#define Rtl8812_NIC_PDN_FLOW					rtl8812_hwpdn_flow
-+#define Rtl8812_NIC_LPS_ENTER_FLOW			rtl8812_enter_lps_flow
-+#define Rtl8812_NIC_LPS_LEAVE_FLOW				rtl8812_leave_lps_flow
-+
-+/* ---------------------------------------------------------------------
-+ *		RTL8821 Power Configuration CMDs for PCIe interface
-+ * --------------------------------------------------------------------- */
-+#define Rtl8821A_NIC_PWR_ON_FLOW				rtl8821A_power_on_flow
-+#define Rtl8821A_NIC_RF_OFF_FLOW				rtl8821A_radio_off_flow
-+#define Rtl8821A_NIC_DISABLE_FLOW				rtl8821A_card_disable_flow
-+#define Rtl8821A_NIC_ENABLE_FLOW				rtl8821A_card_enable_flow
-+#define Rtl8821A_NIC_SUSPEND_FLOW				rtl8821A_suspend_flow
-+#define Rtl8821A_NIC_RESUME_FLOW				rtl8821A_resume_flow
-+#define Rtl8821A_NIC_PDN_FLOW					rtl8821A_hwpdn_flow
-+#define Rtl8821A_NIC_LPS_ENTER_FLOW			rtl8821A_enter_lps_flow
-+#define Rtl8821A_NIC_LPS_LEAVE_FLOW			rtl8821A_leave_lps_flow
-+
-+
-+#if 1 /* download firmware related data structure */
-+#define FW_SIZE_8812			0x8000 /* Compatible with RTL8723 Maximal RAM code size 24K.   modified to 32k, TO compatible with 92d maximal fw size 32k */
-+#define FW_START_ADDRESS		0x1000
-+#define FW_END_ADDRESS		0x5FFF
-+
-+
-+
-+typedef struct _RT_FIRMWARE_8812 {
-+	FIRMWARE_SOURCE	eFWSource;
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+	u8			*szFwBuffer;
-+#else
-+	u8			szFwBuffer[FW_SIZE_8812];
-+#endif
-+	u32			ulFwLength;
-+} RT_FIRMWARE_8812, *PRT_FIRMWARE_8812;
-+
-+/*
-+ * This structure must be cared byte-ordering
-+ *
-+ * Added by tynli. 2009.12.04. */
-+#define IS_FW_HEADER_EXIST_8812(_pFwHdr)	((GET_FIRMWARE_HDR_SIGNATURE_8812(_pFwHdr) & 0xFFF0) == 0x9500)
-+
-+#define IS_FW_HEADER_EXIST_8821(_pFwHdr)	((GET_FIRMWARE_HDR_SIGNATURE_8812(_pFwHdr) & 0xFFF0) == 0x2100)
-+/* *****************************************************
-+ *					Firmware Header(8-byte alinment required)
-+ * *****************************************************
-+ * --- LONG WORD 0 ---- */
-+#define GET_FIRMWARE_HDR_SIGNATURE_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 0, 16) /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
-+#define GET_FIRMWARE_HDR_CATEGORY_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */
-+#define GET_FIRMWARE_HDR_FUNCTION_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
-+#define GET_FIRMWARE_HDR_VERSION_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */
-+#define GET_FIRMWARE_HDR_SUB_VER_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */
-+#define GET_FIRMWARE_HDR_RSVD1_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8)
-+
-+/* --- LONG WORD 1 ---- */
-+#define GET_FIRMWARE_HDR_MONTH_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) /* Release time Month field */
-+#define GET_FIRMWARE_HDR_DATE_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) /* Release time Date field */
-+#define GET_FIRMWARE_HDR_HOUR_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)/* Release time Hour field */
-+#define GET_FIRMWARE_HDR_MINUTE_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)/* Release time Minute field */
-+#define GET_FIRMWARE_HDR_ROMCODE_SIZE_8812(__FwHdr)	LE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)/* The size of RAM code */
-+#define GET_FIRMWARE_HDR_RSVD2_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+12, 16, 16)
-+
-+/* --- LONG WORD 2 ---- */
-+#define GET_FIRMWARE_HDR_SVN_IDX_8812(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)/* The SVN entry index */
-+#define GET_FIRMWARE_HDR_RSVD3_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+20, 0, 32)
-+
-+/* --- LONG WORD 3 ---- */
-+#define GET_FIRMWARE_HDR_RSVD4_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 0, 32)
-+#define GET_FIRMWARE_HDR_RSVD5_8812(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)
-+
-+#endif /* download firmware related data structure */
-+
-+
-+#define DRIVER_EARLY_INT_TIME_8812		0x05
-+#define BCN_DMA_ATIME_INT_TIME_8812		0x02
-+
-+/* for 8812
-+ * TX 128K, RX 16K, Page size 512B for TX, 128B for RX */
-+#define MAX_RX_DMA_BUFFER_SIZE_8812	0x3E80 /* RX 16K */
-+
-+#ifdef CONFIG_WOWLAN
-+	#define RESV_FMWF	(WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
-+#else
-+	#define RESV_FMWF	0
-+#endif
-+
-+#ifdef CONFIG_FW_C2H_DEBUG
-+	#define RX_DMA_RESERVED_SIZE_8812	0x100	/* 256B, reserved for c2h debug message */
-+#else
-+	#define RX_DMA_RESERVED_SIZE_8812	0x0	/* 0B */
-+#endif
-+#define RX_DMA_BOUNDARY_8812		(MAX_RX_DMA_BUFFER_SIZE_8812 - RX_DMA_RESERVED_SIZE_8812 - 1)
-+
-+#define PAGE_SIZE_TX_8812A PAGE_SIZE_512
-+
-+/* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8812A
-+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
-+#define BCNQ_PAGE_NUM_8812		(MAX_BEACON_LEN / PAGE_SIZE_TX_8812A + 6) /*0x07*/
-+
-+/* For WoWLan , more reserved page
-+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, AOAC rpt: 1,PNO: 6
-+ * NS offload: 1 NDP info: 1
-+ */
-+#ifdef CONFIG_WOWLAN
-+	#define WOWLAN_PAGE_NUM_8812	0x08
-+#else
-+	#define WOWLAN_PAGE_NUM_8812	0x00
-+#endif
-+
-+
-+#ifdef CONFIG_BEAMFORMER_FW_NDPA
-+	#define FW_NDPA_PAGE_NUM	0x02
-+#else
-+	#define FW_NDPA_PAGE_NUM	0x00
-+#endif
-+
-+#ifdef DBG_FW_DEBUG_MSG_PKT
-+	#define FW_DBG_MSG_PKT_PAGE_NUM_8812	0x01
-+#else
-+	#define FW_DBG_MSG_PKT_PAGE_NUM_8812	0x00
-+#endif /*DBG_FW_DEBUG_MSG_PKT*/
-+
-+#define TX_TOTAL_PAGE_NUMBER_8812	(0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 - FW_NDPA_PAGE_NUM - FW_DBG_MSG_PKT_PAGE_NUM_8812)
-+#define TX_PAGE_BOUNDARY_8812			(TX_TOTAL_PAGE_NUMBER_8812 + 1)
-+
-+#define TX_PAGE_BOUNDARY_WOWLAN_8812		(0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 + 1)
-+
-+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8812	TX_TOTAL_PAGE_NUMBER_8812
-+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8812		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8812 + 1)
-+
-+/* For Normal Chip Setting
-+ * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8812 */
-+#define NORMAL_PAGE_NUM_LPQ_8812				0x10
-+#define NORMAL_PAGE_NUM_HPQ_8812			0x10
-+#define NORMAL_PAGE_NUM_NPQ_8812			0x00
-+
-+#define WMM_NORMAL_PAGE_NUM_HPQ_8812		0x30
-+#define WMM_NORMAL_PAGE_NUM_LPQ_8812		0x20
-+#define WMM_NORMAL_PAGE_NUM_NPQ_8812		0x20
-+
-+
-+/* for 8821A
-+ * TX 64K, RX 16K, Page size 256B for TX, 128B for RX */
-+#define PAGE_SIZE_TX_8821A					256
-+#define PAGE_SIZE_RX_8821A					128
-+
-+#define MAX_RX_DMA_BUFFER_SIZE_8821			0x3E80 /* RX 16K */
-+
-+#ifdef CONFIG_FW_C2H_DEBUG
-+	#define RX_DMA_RESERVED_SIZE_8821	0x100	/* 256B, reserved for c2h debug message */
-+#else
-+	#define RX_DMA_RESERVED_SIZE_8821	0x0	/* 0B */
-+#endif
-+#define RX_DMA_BOUNDARY_8821		(MAX_RX_DMA_BUFFER_SIZE_8821 - RX_DMA_RESERVED_SIZE_8821 - 1)
-+
-+/* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8821A
-+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
-+
-+#define BCNQ_PAGE_NUM_8821		(MAX_BEACON_LEN / PAGE_SIZE_TX_8821A + 6) /*0x08*/
-+
-+
-+/* For WoWLan , more reserved page
-+ * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, PNO: 6 */
-+#ifdef CONFIG_WOWLAN
-+	#define WOWLAN_PAGE_NUM_8821	0x06
-+#else
-+	#define WOWLAN_PAGE_NUM_8821	0x00
-+#endif
-+
-+#define TX_TOTAL_PAGE_NUMBER_8821	(0xFF - BCNQ_PAGE_NUM_8821 - WOWLAN_PAGE_NUM_8821)
-+#define TX_PAGE_BOUNDARY_8821				(TX_TOTAL_PAGE_NUMBER_8821 + 1)
-+/* #define TX_PAGE_BOUNDARY_WOWLAN_8821		0xE0 */
-+
-+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8821	TX_TOTAL_PAGE_NUMBER_8821
-+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8821		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8821 + 1)
-+
-+
-+/* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
-+#define NORMAL_PAGE_NUM_LPQ_8821			0x08/* 0x10 */
-+#define NORMAL_PAGE_NUM_HPQ_8821		0x08/* 0x10 */
-+#define NORMAL_PAGE_NUM_NPQ_8821		0x00
-+#define NORMAL_PAGE_NUM_EPQ_8821			0x04
-+
-+#define WMM_NORMAL_PAGE_NUM_HPQ_8821		0x30
-+#define WMM_NORMAL_PAGE_NUM_LPQ_8821		0x20
-+#define WMM_NORMAL_PAGE_NUM_NPQ_8821		0x20
-+#define WMM_NORMAL_PAGE_NUM_EPQ_8821		0x00
-+
-+#define MCC_NORMAL_PAGE_NUM_HPQ_8821		0x10
-+#define MCC_NORMAL_PAGE_NUM_LPQ_8821		0x10
-+#define MCC_NORMAL_PAGE_NUM_NPQ_8821		0x10
-+
-+#define	EFUSE_HIDDEN_812AU					0
-+#define	EFUSE_HIDDEN_812AU_VS				1
-+#define	EFUSE_HIDDEN_812AU_VL				2
-+#define	EFUSE_HIDDEN_812AU_VN				3
-+
-+#if 0
-+#define EFUSE_REAL_CONTENT_LEN_JAGUAR		1024
-+#define HWSET_MAX_SIZE_JAGUAR					1024
-+#else
-+#define EFUSE_REAL_CONTENT_LEN_JAGUAR		512
-+#define HWSET_MAX_SIZE_JAGUAR					512
-+#endif
-+
-+#define EFUSE_MAX_BANK_8812A					2
-+#define EFUSE_MAP_LEN_JAGUAR					512
-+#define EFUSE_MAX_SECTION_JAGUAR				64
-+#define EFUSE_MAX_WORD_UNIT_JAGUAR			4
-+#define EFUSE_IC_ID_OFFSET_JAGUAR				506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
-+#define AVAILABLE_EFUSE_ADDR_8812(addr)	(addr < EFUSE_REAL_CONTENT_LEN_JAGUAR)
-+/* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
-+ * 9bytes + 1byt + 5bytes and pre 1byte.
-+ * For worst case:
-+ * | 2byte|----8bytes----|1byte|--7bytes--|  */ /* 92D */
-+#define EFUSE_OOB_PROTECT_BYTES_JAGUAR		18	/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
-+#define EFUSE_PROTECT_BYTES_BANK_JAGUAR		16
-+
-+#define INCLUDE_MULTI_FUNC_BT(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
-+#define INCLUDE_MULTI_FUNC_GPS(_Adapter)	(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
-+
-+/* #define IS_MULTI_FUNC_CHIP(_Adapter)	(((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */
-+
-+/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */
-+#define HAL_EFUSE_MEMORY
-+
-+/* ********************************************************
-+ *			EFUSE for BT definition
-+ * ******************************************************** */
-+#define BANK_NUM			2
-+#define EFUSE_BT_REAL_BANK_CONTENT_LEN	512
-+#define EFUSE_BT_REAL_CONTENT_LEN	\
-+	(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
-+#define EFUSE_BT_MAP_LEN		1024	/* 1k bytes */
-+#define EFUSE_BT_MAX_SECTION		(EFUSE_BT_MAP_LEN / 8)
-+#define EFUSE_PROTECT_BYTES_BANK	16
-+
-+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_BT_REAL_CONTENT_LEN)
-+
-+#ifdef CONFIG_FILE_FWIMG
-+extern char *rtw_fw_file_path;
-+#ifdef CONFIG_WOWLAN
-+extern char *rtw_fw_wow_file_path;
-+#endif
-+#ifdef CONFIG_MP_INCLUDED
-+extern char *rtw_fw_mp_bt_file_path;
-+#endif
-+#endif
-+
-+
-+/* rtl8812_hal_init.c */
-+void	_8051Reset8812(PADAPTER padapter);
-+s32	FirmwareDownload8812(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw);
-+void	InitializeFirmwareVars8812(PADAPTER padapter);
-+
-+s32	_LLTWrite_8812A(PADAPTER Adapter, u32 address, u32 data);
-+s32	InitLLTTable8812A(PADAPTER padapter, u8 txpktbuf_bndy);
-+void InitRDGSetting8812A(PADAPTER padapter);
-+
-+void CheckAutoloadState8812A(PADAPTER padapter);
-+
-+/* EFuse */
-+u8	GetEEPROMSize8812A(PADAPTER padapter);
-+void InitPGData8812A(PADAPTER padapter);
-+void	Hal_EfuseParseIDCode8812A(PADAPTER padapter, u8 *hwinfo);
-+void	Hal_ReadPROMVersion8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void	Hal_ReadTxPowerInfo8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
-+void	Hal_ReadBoardType8812A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void	Hal_ReadThermalMeter_8812A(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN	AutoloadFail);
-+void	Hal_ReadChannelPlan8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void	Hal_EfuseParseXtal_8812A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void	Hal_ReadAntennaDiversity8812A(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
-+void	Hal_ReadAmplifierType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+void	Hal_ReadPAType_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+void	Hal_ReadRFEType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+void	Hal_EfuseParseBTCoexistInfo8812A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void	hal_ReadUsbType_8812AU(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+#ifdef CONFIG_MP_INCLUDED
-+int	FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
-+#endif
-+void	Hal_ReadRemoteWakeup_8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+
-+BOOLEAN HalDetectPwrDownMode8812(PADAPTER Adapter);
-+void Hal_EfuseParseKFreeData_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+
-+#ifdef CONFIG_WOWLAN
-+void Hal_DetectWoWMode(PADAPTER pAdapter);
-+#endif /* CONFIG_WOWLAN */
-+
-+void _InitBeaconParameters_8812A(PADAPTER padapter);
-+void SetBeaconRelatedRegisters8812A(PADAPTER padapter);
-+
-+void ReadRFType8812A(PADAPTER padapter);
-+void InitDefaultValue8821A(PADAPTER padapter);
-+
-+u8 SetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval);
-+void GetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval);
-+u8 SetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+u8 GetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+void rtl8812_set_hal_ops(struct hal_ops *pHalFunc);
-+void init_hal_spec_8812a(_adapter *adapter);
-+void init_hal_spec_8821a(_adapter *adapter);
-+
-+u32 upload_txpktbuf_8812au(_adapter *adapter, u8 *buf, u32 buflen);
-+
-+void rtl8812_start_thread(PADAPTER padapter);
-+void rtl8812_stop_thread(PADAPTER padapter);
-+
-+#ifdef CONFIG_PCI_HCI
-+BOOLEAN	InterruptRecognized8812AE(PADAPTER Adapter);
-+void	UpdateInterruptMask8812AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
-+void	InitTRXDescHwAddress8812AE(PADAPTER Adapter);
-+#endif
-+
-+#ifdef CONFIG_BT_COEXIST
-+void rtl8812a_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
-+#endif
-+
-+void
-+Hal_PatchwithJaguar_8812(
-+		PADAPTER				Adapter,
-+		RT_MEDIA_STATUS		MediaStatus
-+);
-+
-+#endif /* __RTL8188E_HAL_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8812a_led.h b/drivers/staging/rtl8723cs/include/rtl8812a_led.h
-new file mode 100644
-index 000000000000..30c676e526f3
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8812a_led.h
-@@ -0,0 +1,41 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8812A_LED_H__
-+#define __RTL8812A_LED_H__
-+#ifdef CONFIG_RTW_LED
-+#ifdef CONFIG_RTW_SW_LED
-+/* ********************************************************************************
-+ * Interface to manipulate LED objects.
-+ * ******************************************************************************** */
-+#ifdef CONFIG_USB_HCI
-+void rtl8812au_InitSwLeds(PADAPTER padapter);
-+void rtl8812au_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+void rtl8812ae_InitSwLeds(PADAPTER padapter);
-+void rtl8812ae_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#ifdef CONFIG_SDIO_HCI
-+void rtl8821as_InitSwLeds(PADAPTER padapter);
-+void rtl8821as_DeInitSwLeds(PADAPTER padapter);
-+#endif
-+#endif/*CONFIG_RTW_SW_LED*/
-+#endif/*#ifdef CONFIG_RTW_LED*/
-+
-+#ifdef CONFIG_SDIO_HCI
-+void rtl8821as_init_led_circuit(PADAPTER adapter);
-+#endif
-+
-+#endif /*__RTL8812A_LED_H__*/
-diff --git a/drivers/staging/rtl8723cs/include/rtl8812a_recv.h b/drivers/staging/rtl8723cs/include/rtl8812a_recv.h
-new file mode 100644
-index 000000000000..5fa06e512baf
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8812a_recv.h
-@@ -0,0 +1,149 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8812A_RECV_H__
-+#define __RTL8812A_RECV_H__
-+
-+#if defined(CONFIG_USB_HCI)
-+
-+	#ifndef MAX_RECVBUF_SZ
-+		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
-+			#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
-+				#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/
-+			#else
-+				#define MAX_RECVBUF_SZ (32768)  /*32k*/
-+			#endif
-+			/* #define MAX_RECVBUF_SZ (24576) */ /* 24k */
-+			/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
-+			/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
-+			/* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */
-+			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
-+			#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
-+				#undef MAX_RECVBUF_SZ
-+				#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
-+			#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
-+		#else
-+			#define MAX_RECVBUF_SZ (4000) /* about 4K */
-+		#endif
-+	#endif /* !MAX_RECVBUF_SZ */
-+
-+#elif defined(CONFIG_PCI_HCI)
-+	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
-+	/*	#define MAX_RECVBUF_SZ (9100) */
-+	/* #else */
-+	#define MAX_RECVBUF_SZ (4000) /* about 4K
-+	* #endif */
-+
-+
-+#elif defined(CONFIG_SDIO_HCI)
-+
-+	#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8821 + 1)
-+
-+#endif
-+
-+
-+/* Rx smooth factor */
-+#define Rx_Smooth_Factor (20)
-+
-+/* DWORD 0 */
-+#define SET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
-+#define SET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
-+#define SET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
-+
-+#define GET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
-+#define GET_RX_STATUS_DESC_CRC32_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
-+#define GET_RX_STATUS_DESC_ICV_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
-+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8812(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
-+#define GET_RX_STATUS_DESC_SECURITY_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
-+#define GET_RX_STATUS_DESC_QOS_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
-+#define GET_RX_STATUS_DESC_SHIFT_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
-+#define GET_RX_STATUS_DESC_PHY_STATUS_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
-+#define GET_RX_STATUS_DESC_SWDEC_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
-+#define GET_RX_STATUS_DESC_LAST_SEG_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
-+#define GET_RX_STATUS_DESC_FIRST_SEG_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
-+#define GET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
-+#define GET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
-+
-+/* DWORD 1 */
-+#define GET_RX_STATUS_DESC_MACID_8812(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
-+#define GET_RX_STATUS_DESC_TID_8812(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
-+#define GET_RX_STATUS_DESC_AMSDU_8812(__pRxDesc)					LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
-+#define GET_RX_STATUS_DESC_RXID_MATCH_8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
-+#define GET_RX_STATUS_DESC_PAGGR_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
-+#define GET_RX_STATUS_DESC_A1_FIT_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
-+#define GET_RX_STATUS_DESC_CHKERR_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
-+#define GET_RX_STATUS_DESC_IPVER_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
-+#define GET_RX_STATUS_DESC_IS_TCPUDP__8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
-+#define GET_RX_STATUS_DESC_CHK_VLD_8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
-+#define GET_RX_STATUS_DESC_PAM_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
-+#define GET_RX_STATUS_DESC_PWR_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
-+#define GET_RX_STATUS_DESC_MORE_DATA_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
-+#define GET_RX_STATUS_DESC_MORE_FRAG_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
-+#define GET_RX_STATUS_DESC_TYPE_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
-+#define GET_RX_STATUS_DESC_MC_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
-+#define GET_RX_STATUS_DESC_BC_8812(__pRxDesc)				LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
-+
-+/* DWORD 2 */
-+#define GET_RX_STATUS_DESC_SEQ_8812(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
-+#define GET_RX_STATUS_DESC_FRAG_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
-+#define GET_RX_STATUS_DESC_RX_IS_QOS_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
-+#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8812(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
-+#define GET_RX_STATUS_DESC_RPT_SEL_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
-+
-+/* DWORD 3 */
-+#define GET_RX_STATUS_DESC_RX_RATE_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
-+#define GET_RX_STATUS_DESC_HTC_8812(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
-+#define GET_RX_STATUS_DESC_EOSP_8812(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
-+#define GET_RX_STATUS_DESC_BSSID_FIT_8812(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
-+#ifdef CONFIG_USB_RX_AGGREGATION
-+#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8812(__pRxStatusDesc)	LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
-+#endif
-+#define GET_RX_STATUS_DESC_PATTERN_MATCH_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
-+#define GET_RX_STATUS_DESC_UNICAST_MATCH_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
-+#define GET_RX_STATUS_DESC_MAGIC_MATCH_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
-+
-+/* DWORD 6 */
-+#define GET_RX_STATUS_DESC_SPLCP_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
-+#define GET_RX_STATUS_DESC_LDPC_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
-+#define GET_RX_STATUS_DESC_STBC_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
-+#define GET_RX_STATUS_DESC_BW_8812(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
-+
-+/* DWORD 5 */
-+#define GET_RX_STATUS_DESC_TSFL_8812(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
-+
-+#define GET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
-+#define GET_RX_STATUS_DESC_BUFF_ADDR64_8812(__pRxDesc)		LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
-+
-+#define SET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
-+
-+
-+#ifdef CONFIG_SDIO_HCI
-+s32 InitRecvPriv8821AS(PADAPTER padapter);
-+void FreeRecvPriv8821AS(PADAPTER padapter);
-+#endif /* CONFIG_SDIO_HCI */
-+
-+#ifdef CONFIG_USB_HCI
-+void rtl8812au_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
-+s32 rtl8812au_init_recv_priv(PADAPTER padapter);
-+void rtl8812au_free_recv_priv(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+s32 rtl8812ae_init_recv_priv(PADAPTER padapter);
-+void rtl8812ae_free_recv_priv(PADAPTER padapter);
-+#endif
-+
-+void rtl8812_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
-+
-+#endif /* __RTL8812A_RECV_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8812a_rf.h b/drivers/staging/rtl8723cs/include/rtl8812a_rf.h
-new file mode 100644
-index 000000000000..c5d9aaee3fad
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8812a_rf.h
-@@ -0,0 +1,28 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8812A_RF_H__
-+#define __RTL8812A_RF_H__
-+
-+void
-+PHY_RF6052SetBandwidth8812(
-+		PADAPTER				Adapter,
-+		enum channel_width		Bandwidth);
-+
-+
-+int
-+PHY_RF6052_Config_8812(
-+		PADAPTER	Adapter);
-+
-+#endif/* __RTL8188E_RF_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8812a_spec.h b/drivers/staging/rtl8723cs/include/rtl8812a_spec.h
-new file mode 100644
-index 000000000000..37ba2472296c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8812a_spec.h
-@@ -0,0 +1,263 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8812A_SPEC_H__
-+#define __RTL8812A_SPEC_H__
-+
-+#include <drv_conf.h>
-+
-+
-+/* ************************************************************
-+* 8812 Regsiter offset definition
-+* ************************************************************ */
-+
-+/* ************************************************************
-+*
-+* ************************************************************ */
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0000h ~ 0x00FFh	System Configuration
-+*
-+* ----------------------------------------------------- */
-+#define REG_SYS_CLKR_8812A				0x0008
-+#define REG_AFE_PLL_CTRL_8812A		0x0028
-+#define REG_HSIMR_8812					0x0058
-+#define REG_HSISR_8812					0x005c
-+#define REG_GPIO_EXT_CTRL				0x0060
-+#define REG_GPIO_STATUS_8812			0x006C
-+#define REG_SDIO_CTRL_8812				0x0070
-+#define REG_OPT_CTRL_8812				0x0074
-+#define REG_RF_B_CTRL_8812				0x0076
-+#define REG_FW_DRV_MSG_8812			0x0088
-+#define REG_HMEBOX_E2_E3_8812			0x008C
-+#define REG_HIMR0_8812					0x00B0
-+#define REG_HISR0_8812					0x00B4
-+#define REG_HIMR1_8812					0x00B8
-+#define REG_HISR1_8812					0x00BC
-+#define REG_EFUSE_BURN_GNT_8812		0x00CF
-+#define REG_SYS_CFG1_8812				0x00FC
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+*
-+* ----------------------------------------------------- */
-+#define REG_CR_8812A					0x100
-+#define REG_PKTBUF_DBG_ADDR			(REG_PKTBUF_DBG_CTRL)
-+#define REG_RXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+2)
-+#define REG_TXPKTBUF_DBG				(REG_PKTBUF_DBG_CTRL+3)
-+#define REG_WOWLAN_WAKE_REASON			REG_MCUTST_WOWLAN
-+
-+#define REG_RSVD3_8812					0x0168
-+#define REG_C2HEVT_CMD_SEQ_88XX		0x01A1
-+#define REG_C2hEVT_CMD_CONTENT_88XX	0x01A2
-+#define REG_C2HEVT_CMD_LEN_88XX		0x01AE
-+
-+#define REG_HMEBOX_EXT0_8812			0x01F0
-+#define REG_HMEBOX_EXT1_8812			0x01F4
-+#define REG_HMEBOX_EXT2_8812			0x01F8
-+#define REG_HMEBOX_EXT3_8812			0x01FC
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0200h ~ 0x027Fh	TXDMA Configuration
-+*
-+* ----------------------------------------------------- */
-+#define REG_DWBCN0_CTRL_8812				REG_TDECTRL
-+#define REG_DWBCN1_CTRL_8812				0x0228
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0280h ~ 0x02FFh	RXDMA Configuration
-+*
-+* ----------------------------------------------------- */
-+#define REG_TDECTRL_8812A				0x0208
-+#define REG_RXDMA_CONTROL_8812A		0x0286		/*Control the RX DMA.*/
-+#define REG_RXDMA_PRO_8812			0x0290
-+#define REG_EARLY_MODE_CONTROL_8812	0x02BC
-+#define REG_RSVD5_8812					0x02F0
-+#define REG_RSVD6_8812					0x02F4
-+#define REG_RSVD7_8812					0x02F8
-+#define REG_RSVD8_8812					0x02FC
-+
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0300h ~ 0x03FFh	PCIe
-+*
-+* ----------------------------------------------------- */
-+#define	REG_PCIE_CTRL_REG_8812A			0x0300
-+#define	REG_DBI_WDATA_8812			0x0348	/* DBI Write Data */
-+#define	REG_DBI_RDATA_8812			0x034C	/* DBI Read Data */
-+#define	REG_DBI_ADDR_8812			0x0350	/* DBI Address */
-+#define	REG_DBI_FLAG_8812			0x0352	/* DBI Read/Write Flag */
-+#define	REG_MDIO_WDATA_8812			0x0354	/* MDIO for Write PCIE PHY */
-+#define	REG_MDIO_RDATA_8812			0x0356	/* MDIO for Reads PCIE PHY */
-+#define	REG_MDIO_CTL_8812			0x0358	/* MDIO for Control */
-+#define REG_PCIE_HRPWM_8812A			0x0361  /* PCIe RPWM */
-+#define REG_PCIE_HCPWM_8812A			0x0363  /* PCIe CPWM */
-+
-+#define	REG_PCIE_MULTIFET_CTRL_8812	0x036A	/* PCIE Multi-Fethc Control */
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0400h ~ 0x047Fh	Protocol Configuration
-+*
-+* ----------------------------------------------------- */
-+#define REG_TXPKT_EMPTY_8812A			0x041A
-+#define REG_FWHW_TXQ_CTRL_8812A		0x0420
-+#define REG_TXBF_CTRL_8812A			0x042C
-+#define REG_ARFR0_8812					0x0444
-+#define REG_ARFR1_8812					0x044C
-+#define REG_CCK_CHECK_8812				0x0454
-+#define REG_AMPDU_MAX_TIME_8812		0x0456
-+#define REG_TXPKTBUF_BCNQ_BDNY1_8812	0x0457
-+
-+#define REG_AMPDU_MAX_LENGTH_8812	0x0458
-+#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8812	0x045D
-+#define REG_NDPA_OPT_CTRL_8812A		0x045F
-+#define REG_DATA_SC_8812				0x0483
-+#ifdef CONFIG_WOWLAN
-+#define REG_TXPKTBUF_IV_LOW             0x0484
-+#define REG_TXPKTBUF_IV_HIGH            0x0488
-+#endif
-+#define REG_ARFR2_8812					0x048C
-+#define REG_ARFR3_8812					0x0494
-+#define REG_TXRPT_START_OFFSET		0x04AC
-+#define REG_AMPDU_BURST_MODE_8812	0x04BC
-+#define REG_HT_SINGLE_AMPDU_8812		0x04C7
-+#define REG_MACID_PKT_DROP0_8812		0x04D0
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0500h ~ 0x05FFh	EDCA Configuration
-+*
-+* ----------------------------------------------------- */
-+#define REG_TXPAUSE_8812A				0x0522
-+#define REG_CTWND_8812					0x0572
-+#define REG_SECONDARY_CCA_CTRL_8812	0x0577
-+#define REG_SCH_TXCMD_8812A			0x05F8
-+
-+/* -----------------------------------------------------
-+*
-+*	0x0600h ~ 0x07FFh	WMAC Configuration
-+*
-+* ----------------------------------------------------- */
-+#define REG_MAC_CR_8812				0x0600
-+
-+#define REG_MAC_TX_SM_STATE_8812		0x06B4
-+
-+/* Power */
-+#define REG_BFMER0_INFO_8812A			0x06E4
-+#define REG_BFMER1_INFO_8812A			0x06EC
-+#define REG_CSI_RPT_PARAM_BW20_8812A	0x06F4
-+#define REG_CSI_RPT_PARAM_BW40_8812A	0x06F8
-+#define REG_CSI_RPT_PARAM_BW80_8812A	0x06FC
-+
-+/* Hardware Port 2 */
-+#define REG_BFMEE_SEL_8812A			0x0714
-+#define REG_SND_PTCL_CTRL_8812A		0x0718
-+
-+
-+/* -----------------------------------------------------
-+*
-+*	Redifine register definition for compatibility
-+*
-+* ----------------------------------------------------- */
-+
-+/* TODO: use these definition when using REG_xxx naming rule.
-+* NOTE: DO NOT Remove these definition. Use later. */
-+#define	ISR_8812							REG_HISR0_8812
-+
-+/* ----------------------------------------------------------------------------
-+* 8195 IMR/ISR bits						(offset 0xB0,  8bits)
-+* ---------------------------------------------------------------------------- */
-+#define	IMR_DISABLED_8812					0
-+/* IMR DW0(0x00B0-00B3) Bit 0-31 */
-+#define	IMR_TIMER2_8812					BIT31		/* Timeout interrupt 2 */
-+#define	IMR_TIMER1_8812					BIT30		/* Timeout interrupt 1	 */
-+#define	IMR_PSTIMEOUT_8812				BIT29		/* Power Save Time Out Interrupt */
-+#define	IMR_GTINT4_8812					BIT28		/* When GTIMER4 expires, this bit is set to 1	 */
-+#define	IMR_GTINT3_8812					BIT27		/* When GTIMER3 expires, this bit is set to 1	 */
-+#define	IMR_TXBCN0ERR_8812				BIT26		/* Transmit Beacon0 Error			 */
-+#define	IMR_TXBCN0OK_8812					BIT25		/* Transmit Beacon0 OK			 */
-+#define	IMR_TSF_BIT32_TOGGLE_8812		BIT24		/* TSF Timer BIT32 toggle indication interrupt			 */
-+#define	IMR_BCNDMAINT0_8812				BIT20		/* Beacon DMA Interrupt 0			 */
-+#define	IMR_BCNDERR0_8812					BIT16		/* Beacon Queue DMA OK0			 */
-+#define	IMR_HSISR_IND_ON_INT_8812		BIT15		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
-+#define	IMR_BCNDMAINT_E_8812				BIT14		/* Beacon DMA Interrupt Extension for Win7			 */
-+#define	IMR_ATIMEND_8812					BIT12		/* CTWidnow End or ATIM Window End */
-+#define	IMR_C2HCMD_8812					BIT10		/* CPU to Host Command INT Status, Write 1 clear	 */
-+#define	IMR_CPWM2_8812					BIT9			/* CPU power Mode exchange INT Status, Write 1 clear	 */
-+#define	IMR_CPWM_8812						BIT8			/* CPU power Mode exchange INT Status, Write 1 clear	 */
-+#define	IMR_HIGHDOK_8812					BIT7			/* High Queue DMA OK	 */
-+#define	IMR_MGNTDOK_8812					BIT6			/* Management Queue DMA OK	 */
-+#define	IMR_BKDOK_8812					BIT5			/* AC_BK DMA OK		 */
-+#define	IMR_BEDOK_8812					BIT4			/* AC_BE DMA OK	 */
-+#define	IMR_VIDOK_8812					BIT3			/* AC_VI DMA OK		 */
-+#define	IMR_VODOK_8812					BIT2			/* AC_VO DMA OK	 */
-+#define	IMR_RDU_8812						BIT1			/* Rx Descriptor Unavailable	 */
-+#define	IMR_ROK_8812						BIT0			/* Receive DMA OK */
-+
-+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
-+#define	IMR_BCNDMAINT7_8812				BIT27		/* Beacon DMA Interrupt 7 */
-+#define	IMR_BCNDMAINT6_8812				BIT26		/* Beacon DMA Interrupt 6 */
-+#define	IMR_BCNDMAINT5_8812				BIT25		/* Beacon DMA Interrupt 5 */
-+#define	IMR_BCNDMAINT4_8812				BIT24		/* Beacon DMA Interrupt 4 */
-+#define	IMR_BCNDMAINT3_8812				BIT23		/* Beacon DMA Interrupt 3 */
-+#define	IMR_BCNDMAINT2_8812				BIT22		/* Beacon DMA Interrupt 2 */
-+#define	IMR_BCNDMAINT1_8812				BIT21		/* Beacon DMA Interrupt 1 */
-+#define	IMR_BCNDOK7_8812					BIT20		/* Beacon Queue DMA OK Interrup 7 */
-+#define	IMR_BCNDOK6_8812					BIT19		/* Beacon Queue DMA OK Interrup 6 */
-+#define	IMR_BCNDOK5_8812					BIT18		/* Beacon Queue DMA OK Interrup 5 */
-+#define	IMR_BCNDOK4_8812					BIT17		/* Beacon Queue DMA OK Interrup 4 */
-+#define	IMR_BCNDOK3_8812					BIT16		/* Beacon Queue DMA OK Interrup 3 */
-+#define	IMR_BCNDOK2_8812					BIT15		/* Beacon Queue DMA OK Interrup 2 */
-+#define	IMR_BCNDOK1_8812					BIT14		/* Beacon Queue DMA OK Interrup 1 */
-+#define	IMR_ATIMEND_E_8812				BIT13		/* ATIM Window End Extension for Win7 */
-+#define	IMR_TXERR_8812					BIT11		/* Tx Error Flag Interrupt Status, write 1 clear. */
-+#define	IMR_RXERR_8812					BIT10		/* Rx Error Flag INT Status, Write 1 clear */
-+#define	IMR_TXFOVW_8812					BIT9			/* Transmit FIFO Overflow */
-+#define	IMR_RXFOVW_8812					BIT8			/* Receive FIFO Overflow */
-+
-+
-+#ifdef CONFIG_PCI_HCI
-+/* #define IMR_RX_MASK		(IMR_ROK_8812|IMR_RDU_8812|IMR_RXFOVW_8812) */
-+#define IMR_TX_MASK			(IMR_VODOK_8812 | IMR_VIDOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812 | IMR_MGNTDOK_8812 | IMR_HIGHDOK_8812)
-+
-+#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8812 | IMR_TXBCN0OK_8812 | IMR_TXBCN0ERR_8812 | IMR_BCNDERR0_8812)
-+
-+#define RT_AC_INT_MASKS	(IMR_VIDOK_8812 | IMR_VODOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812)
-+#endif
-+
-+
-+/* ****************************************************************************
-+* Regsiter Bit and Content definition
-+* **************************************************************************** */
-+
-+/* 2 ACMHWCTRL 0x05C0 */
-+#define	AcmHw_HwEn_8812				BIT(0)
-+#define	AcmHw_VoqEn_8812				BIT(1)
-+#define	AcmHw_ViqEn_8812				BIT(2)
-+#define	AcmHw_BeqEn_8812				BIT(3)
-+#define	AcmHw_VoqStatus_8812			BIT(5)
-+#define	AcmHw_ViqStatus_8812			BIT(6)
-+#define	AcmHw_BeqStatus_8812			BIT(7)
-+
-+#endif /* __RTL8812A_SPEC_H__ */
-+
-+#ifdef CONFIG_RTL8821A
-+#include "rtl8821a_spec.h"
-+#endif /* CONFIG_RTL8821A */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8812a_sreset.h b/drivers/staging/rtl8723cs/include/rtl8812a_sreset.h
-new file mode 100644
-index 000000000000..d4bbd5867b24
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8812a_sreset.h
-@@ -0,0 +1,24 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL88812A_SRESET_H_
-+#define _RTL8812A_SRESET_H_
-+
-+#include <rtw_sreset.h>
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+extern void rtl8812_sreset_xmit_status_check(_adapter *padapter);
-+extern void rtl8812_sreset_linked_status_check(_adapter *padapter);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8812a_xmit.h b/drivers/staging/rtl8723cs/include/rtl8812a_xmit.h
-new file mode 100644
-index 000000000000..32bf20fadcfd
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8812a_xmit.h
-@@ -0,0 +1,371 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8812A_XMIT_H__
-+#define __RTL8812A_XMIT_H__
-+
-+
-+/* For 88e early mode */
-+#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
-+#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
-+#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
-+#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
-+#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
-+#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
-+#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
-+
-+/*
-+ * defined for TX DESC Operation
-+ *   */
-+
-+#define MAX_TID (15)
-+
-+/* OFFSET 0 */
-+#define OFFSET_SZ	0
-+#define OFFSET_SHT	16
-+#define BMC			BIT(24)
-+#define LSG			BIT(26)
-+#define FSG			BIT(27)
-+#define OWN		BIT(31)
-+
-+
-+/* OFFSET 4 */
-+#define PKT_OFFSET_SZ		0
-+#define QSEL_SHT			8
-+#define RATE_ID_SHT			16
-+#define NAVUSEHDR			BIT(20)
-+#define SEC_TYPE_SHT		22
-+#define PKT_OFFSET_SHT		26
-+
-+/* OFFSET 8 */
-+#define AGG_EN				BIT(12)
-+#define AGG_BK				BIT(16)
-+#define AMPDU_DENSITY_SHT	20
-+#define ANTSEL_A			BIT(24)
-+#define ANTSEL_B			BIT(25)
-+#define TX_ANT_CCK_SHT		26
-+#define TX_ANTL_SHT			28
-+#define TX_ANT_HT_SHT		30
-+
-+/* OFFSET 12 */
-+#define SEQ_SHT				16
-+#define EN_HWSEQ			BIT(31)
-+
-+/* OFFSET 16 */
-+#define QOS					BIT(6)
-+#define	HW_SSN				BIT(7)
-+#define USERATE				BIT(8)
-+#define DISDATAFB			BIT(10)
-+#define CTS_2_SELF			BIT(11)
-+#define	RTS_EN				BIT(12)
-+#define	HW_RTS_EN			BIT(13)
-+#define DATA_SHORT			BIT(24)
-+#define PWR_STATUS_SHT	15
-+#define DATA_SC_SHT		20
-+#define DATA_BW				BIT(25)
-+
-+/* OFFSET 20 */
-+#define	RTY_LMT_EN			BIT(17)
-+
-+/* OFFSET 20 */
-+#define SGI					BIT(6)
-+#define USB_TXAGG_NUM_SHT	24
-+
-+typedef struct txdescriptor_8812 {
-+	/* Offset 0 */
-+	u32 pktlen:16;
-+	u32 offset:8;
-+	u32 bmc:1;
-+	u32 htc:1;
-+	u32 ls:1;
-+	u32 fs:1;
-+	u32 linip:1;
-+	u32 noacm:1;
-+	u32 gf:1;
-+	u32 own:1;
-+
-+	/* Offset 4 */
-+	u32 macid:6;
-+	u32 rsvd0406:2;
-+	u32 qsel:5;
-+	u32 rd_nav_ext:1;
-+	u32 lsig_txop_en:1;
-+	u32 pifs:1;
-+	u32 rate_id:4;
-+	u32 navusehdr:1;
-+	u32 en_desc_id:1;
-+	u32 sectype:2;
-+	u32 rsvd0424:2;
-+	u32 pkt_offset:5;	/* unit: 8 bytes */
-+	u32 rsvd0431:1;
-+
-+	/* Offset 8 */
-+	u32 rts_rc:6;
-+	u32 data_rc:6;
-+	u32 agg_en:1;
-+	u32 rd_en:1;
-+	u32 bar_rty_th:2;
-+	u32 bk:1;
-+	u32 morefrag:1;
-+	u32 raw:1;
-+	u32 ccx:1;
-+	u32 ampdu_density:3;
-+	u32 bt_null:1;
-+	u32 ant_sel_a:1;
-+	u32 ant_sel_b:1;
-+	u32 tx_ant_cck:2;
-+	u32 tx_antl:2;
-+	u32 tx_ant_ht:2;
-+
-+	/* Offset 12 */
-+	u32 nextheadpage:8;
-+	u32 tailpage:8;
-+	u32 seq:12;
-+	u32 cpu_handle:1;
-+	u32 tag1:1;
-+	u32 trigger_int:1;
-+	u32 hwseq_en:1;
-+
-+	/* Offset 16 */
-+	u32 rtsrate:5;
-+	u32 ap_dcfe:1;
-+	u32 hwseq_sel:2;
-+	u32 userate:1;
-+	u32 disrtsfb:1;
-+	u32 disdatafb:1;
-+	u32 cts2self:1;
-+	u32 rtsen:1;
-+	u32 hw_rts_en:1;
-+	u32 port_id:1;
-+	u32 pwr_status:3;
-+	u32 wait_dcts:1;
-+	u32 cts2ap_en:1;
-+	u32 data_sc:2;
-+	u32 data_stbc:2;
-+	u32 data_short:1;
-+	u32 data_bw:1;
-+	u32 rts_short:1;
-+	u32 rts_bw:1;
-+	u32 rts_sc:2;
-+	u32 vcs_stbc:2;
-+
-+	/* Offset 20 */
-+	u32 datarate:6;
-+	u32 sgi:1;
-+	u32 try_rate:1;
-+	u32 data_ratefb_lmt:5;
-+	u32 rts_ratefb_lmt:4;
-+	u32 rty_lmt_en:1;
-+	u32 data_rt_lmt:6;
-+	u32 usb_txagg_num:8;
-+
-+	/* Offset 24 */
-+	u32 txagg_a:5;
-+	u32 txagg_b:5;
-+	u32 use_max_len:1;
-+	u32 max_agg_num:5;
-+	u32 mcsg1_max_len:4;
-+	u32 mcsg2_max_len:4;
-+	u32 mcsg3_max_len:4;
-+	u32 mcs7_sgi_max_len:4;
-+
-+	/* Offset 28 */
-+	u32 checksum:16;	/* TxBuffSize(PCIe)/CheckSum(USB) */
-+	u32 mcsg4_max_len:4;
-+	u32 mcsg5_max_len:4;
-+	u32 mcsg6_max_len:4;
-+	u32 mcs15_sgi_max_len:4;
-+
-+	/* Offset 32 */
-+	u32 rsvd32;
-+
-+	/* Offset 36 */
-+	u32 rsvd36;
-+} TXDESC_8812, *PTXDESC_8812;
-+
-+
-+/* Dword 0 */
-+#define GET_TX_DESC_OWN_8812(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
-+#define SET_TX_DESC_PKT_SIZE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
-+#define SET_TX_DESC_OFFSET_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
-+#define SET_TX_DESC_BMC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
-+#define SET_TX_DESC_HTC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
-+#define SET_TX_DESC_LAST_SEG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
-+#define SET_TX_DESC_FIRST_SEG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
-+#define SET_TX_DESC_LINIP_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
-+#define SET_TX_DESC_NO_ACM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
-+#define SET_TX_DESC_GF_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
-+#define SET_TX_DESC_OWN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
-+
-+/* Dword 1 */
-+#define SET_TX_DESC_MACID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
-+#define SET_TX_DESC_QUEUE_SEL_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
-+#define SET_TX_DESC_RDG_NAV_EXT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
-+#define SET_TX_DESC_LSIG_TXOP_EN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
-+#define SET_TX_DESC_PIFS_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
-+#define SET_TX_DESC_RATE_ID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
-+#define SET_TX_DESC_EN_DESC_ID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
-+#define SET_TX_DESC_SEC_TYPE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
-+#define SET_TX_DESC_PKT_OFFSET_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
-+
-+/* Dword 2 */
-+#define SET_TX_DESC_PAID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
-+#define SET_TX_DESC_CCA_RTS_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
-+#define SET_TX_DESC_AGG_ENABLE_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
-+#define SET_TX_DESC_RDG_ENABLE_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
-+#define SET_TX_DESC_AGG_BREAK_8812(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
-+#define SET_TX_DESC_MORE_FRAG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
-+#define SET_TX_DESC_RAW_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
-+#define SET_TX_DESC_SPE_RPT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
-+#define SET_TX_DESC_AMPDU_DENSITY_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
-+#define SET_TX_DESC_BT_INT_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
-+#define SET_TX_DESC_GID_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
-+
-+/* Dword 3 */
-+#define SET_TX_DESC_WHEADER_LEN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
-+#define SET_TX_DESC_CHK_EN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
-+#define SET_TX_DESC_EARLY_MODE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
-+#define SET_TX_DESC_HWSEQ_SEL_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
-+#define SET_TX_DESC_USE_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
-+#define SET_TX_DESC_DISABLE_RTS_FB_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
-+#define SET_TX_DESC_DISABLE_FB_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
-+#define SET_TX_DESC_CTS2SELF_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
-+#define SET_TX_DESC_RTS_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
-+#define SET_TX_DESC_HW_RTS_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
-+#define SET_TX_DESC_NAV_USE_HDR_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
-+#define SET_TX_DESC_USE_MAX_LEN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
-+#define SET_TX_DESC_MAX_AGG_NUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
-+#define SET_TX_DESC_NDPA_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
-+#define SET_TX_DESC_AMPDU_MAX_TIME_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
-+
-+/* Dword 4 */
-+#define SET_TX_DESC_TX_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
-+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
-+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
-+#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
-+#define SET_TX_DESC_DATA_RETRY_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
-+#define SET_TX_DESC_RTS_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
-+
-+/* Dword 5 */
-+#define SET_TX_DESC_DATA_SC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
-+#define SET_TX_DESC_DATA_SHORT_8812(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
-+#define SET_TX_DESC_DATA_BW_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
-+#define SET_TX_DESC_DATA_LDPC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
-+#define SET_TX_DESC_DATA_STBC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
-+#define SET_TX_DESC_CTROL_STBC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
-+#define SET_TX_DESC_RTS_SHORT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
-+#define SET_TX_DESC_RTS_SC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
-+#define SET_TX_DESC_TX_ANT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value)
-+
-+/* Dword 6 */
-+#define SET_TX_DESC_SW_DEFINE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
-+#define SET_TX_DESC_ANTSEL_A_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
-+#define SET_TX_DESC_ANTSEL_B_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
-+#define SET_TX_DESC_ANTSEL_C_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
-+#define SET_TX_DESC_ANTSEL_D_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
-+#define SET_TX_DESC_MBSSID_8821(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
-+
-+/* Dword 7 */
-+#define SET_TX_DESC_TX_BUFFER_SIZE_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+#define SET_TX_DESC_TX_DESC_CHECKSUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+#define SET_TX_DESC_USB_TXAGG_NUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
-+#ifdef CONFIG_SDIO_HCI
-+#define SET_TX_DESC_SDIO_TXSEQ_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
-+#endif
-+
-+/* Dword 8 */
-+#define SET_TX_DESC_HWSEQ_EN_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
-+
-+/* Dword 9 */
-+#define SET_TX_DESC_SEQ_8812(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
-+
-+/* Dword 10 */
-+#define SET_TX_DESC_TX_BUFFER_ADDRESS_8812(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
-+#define GET_TX_DESC_TX_BUFFER_ADDRESS_8812(__pTxDesc)	LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
-+
-+/* Dword 11 */
-+#define SET_TX_DESC_NEXT_DESC_ADDRESS_8812(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
-+
-+
-+#define SET_EARLYMODE_PKTNUM_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
-+#define SET_EARLYMODE_LEN0_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
-+#define SET_EARLYMODE_LEN1_1_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
-+#define SET_EARLYMODE_LEN1_2_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
-+#define SET_EARLYMODE_LEN2_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,  __Value)
-+#define SET_EARLYMODE_LEN3_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
-+
-+#ifdef CONFIG_TX_EARLY_MODE
-+	#define USB_DUMMY_OFFSET		2
-+#else
-+	#define USB_DUMMY_OFFSET		1
-+#endif
-+#define USB_DUMMY_LENGTH		(USB_DUMMY_OFFSET * PACKET_OFFSET_SZ)
-+
-+
-+void rtl8812a_cal_txdesc_chksum(u8 *ptxdesc);
-+void rtl8812a_fill_fake_txdesc(PADAPTER	padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8	IsBTQosNull, u8 bDataFrame);
-+void rtl8812a_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void rtl8812a_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void rtl8812a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+
-+#ifdef CONFIG_USB_HCI
-+s32 rtl8812au_init_xmit_priv(PADAPTER padapter);
-+void rtl8812au_free_xmit_priv(PADAPTER padapter);
-+s32 rtl8812au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+s32 rtl8812au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+s32 rtl8812au_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+s32	 rtl8812au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+s32 rtl8812au_xmit_buf_handler(PADAPTER padapter);
-+void rtl8812au_xmit_tasklet(void *priv);
-+s32 rtl8812au_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+s32 rtl8812ae_init_xmit_priv(PADAPTER padapter);
-+void rtl8812ae_free_xmit_priv(PADAPTER padapter);
-+struct xmit_buf *rtl8812ae_dequeue_xmitbuf(struct rtw_tx_ring *ring);
-+void	rtl8812ae_xmitframe_resume(_adapter *padapter);
-+s32 rtl8812ae_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+s32 rtl8812ae_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+s32 rtl8812ae_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+s32	rtl8812ae_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+void rtl8812ae_xmit_tasklet(void *priv);
-+
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+s32 rtl8812ae_xmit_buf_handler(_adapter *padapter);
-+#endif
-+
-+#endif
-+
-+#ifdef CONFIG_TX_EARLY_MODE
-+void UpdateEarlyModeInfo8812(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+#endif
-+
-+void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, u8 *ptxdesc);
-+
-+u8	BWMapping_8812(PADAPTER Adapter, struct pkt_attrib *pattrib);
-+
-+u8	SCMapping_8812(PADAPTER Adapter, struct pkt_attrib	*pattrib);
-+
-+#endif /* __RTL8812_XMIT_H__ */
-+
-+#ifdef CONFIG_RTL8821A
-+#include "rtl8821a_xmit.h"
-+#endif /* CONFIG_RTL8821A */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8814a_cmd.h b/drivers/staging/rtl8723cs/include/rtl8814a_cmd.h
-new file mode 100644
-index 000000000000..02ed2111eb00
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8814a_cmd.h
-@@ -0,0 +1,161 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8814A_CMD_H__
-+#define __RTL8814A_CMD_H__
-+#include "hal_com_h2c.h"
-+
-+/* _RSVDPAGE_LOC_CMD0 */
-+#define SET_8814A_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+/* _SETPWRMODE_PARM */
-+#define SET_8814A_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
-+#define SET_8814A_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
-+#define SET_8814A_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
-+#define SET_8814A_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+#define GET_8814A_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd)					LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
-+
-+
-+/* _WoWLAN PARAM_CMD5 */
-+#define SET_8814A_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_8814A_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_8814A_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_8814A_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
-+#define SET_8814A_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
-+#define SET_8814A_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
-+#define SET_8814A_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
-+#define SET_8814A_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
-+#define SET_8814A_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value)					SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+
-+
-+/* WLANINFO_PARM */
-+#define SET_8814A_H2CCMD_WLANINFO_PARM_OPMODE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_WLANINFO_PARM_CHANNEL(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_WLANINFO_PARM_BW40MHZ(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+
-+/* _REMOTE_WAKEUP_CMD7 */
-+#define SET_8814A_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_8814A_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
-+
-+
-+/* _AP_OFFLOAD_CMD8 */
-+#define SET_8814A_H2CCMD_AP_OFFLOAD_ON(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_AP_OFFLOAD_HIDDEN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_AP_OFFLOAD_DENYANY(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_AP_OFFLOAD_WAKEUP_EVT_RPT(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+
-+/* _PWR_MOD_CMD20 */
-+#define SET_88E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_88E_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
-+#define SET_88E_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
-+#define SET_88E_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
-+#define SET_88E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
-+#define SET_88E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
-+
-+/*	AP_REQ_TXREP_CMD 0x43	*/
-+#define SET_8814A_H2CCMD_TXREP_PARM_STA1(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_TXREP_PARM_STA2(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+#define SET_8814A_H2CCMD_TXREP_PARM_RTY(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)
-+
-+/*		C2H_AP_REQ_TXRPT		*/
-+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_MACID1(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 0, 8)
-+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_TXOK1(_Header)			LE_BITS_TO_2BYTE((_Header + 1), 0, 16)
-+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_TXFAIL1(_Header)			LE_BITS_TO_2BYTE((_Header + 3), 0, 16)
-+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_INIRATE1(_Header)		LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
-+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_MACID2(_Header)			LE_BITS_TO_1BYTE((_Header + 6), 0, 8)
-+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_TXOK2(_Header)			LE_BITS_TO_2BYTE((_Header + 7), 0, 16)
-+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_TXFAIL2(_Header)			LE_BITS_TO_2BYTE((_Header + 9), 0, 16)
-+#define	GET_8814A_C2H_TC2H_APREQ_TXRPT_INIRATE2(_Header)		LE_BITS_TO_1BYTE((_Header + 11), 0, 8)
-+
-+/*		C2H_SPC_STAT			*/
-+#define	GET_8814A_C2H_SPC_STAT_IDX(_Header)						LE_BITS_TO_1BYTE((_Header + 0), 0, 8)
-+	/*	Tip :TYPE_A data3 is msb and data0 is lsb	*/
-+#define	GET_8814A_C2H_SPC_STAT_TYPEA_RETRY(_Header)				LE_BITS_TO_4BYTE((_Header + 1), 0, 32)
-+#define	GET_8814A_C2H_SPC_STAT_TYPEB_PKT1(_Header)				LE_BITS_TO_2BYTE((_Header + 1), 0, 16)
-+#define	GET_8814A_C2H_SPC_STAT_TYPEB_RETRY1(_Header)			LE_BITS_TO_2BYTE((_Header + 3), 0, 16)
-+#define	GET_8814A_C2H_SPC_STAT_TYPEB_PKT2(_Header)				LE_BITS_TO_2BYTE((_Header + 5), 0, 16)
-+#define	GET_8814A_C2H_SPC_STAT_TYPEB_RETRY2(_Header)			LE_BITS_TO_2BYTE((_Header + 7), 0, 16)
-+
-+/*BCNHWSEQ*/
-+#define SET_8814A_H2CCMD_BCNHWSEQ_EN(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 1, __Value)
-+#define SET_8814A_H2CCMD_BCNHWSEQ_BCN_NUMBER(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 1, 3, __Value)
-+#define SET_8814A_H2CCMD_BCNHWSEQ_HWSEQ(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 6, 1, __Value)
-+#define SET_8814A_H2CCMD_BCNHWSEQ_EXHWSEQ(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd), 7, 1, __Value)
-+#define SET_8814A_H2CCMD_BCNHWSEQ_PAGE(__pH2CCmd, __Value)	SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
-+void rtl8814_fw_update_beacon_cmd(_adapter *padapter);
-+
-+/* TX Beamforming */
-+#define GET_8814A_C2H_TXBF_ORIGINATE(_Header)			LE_BITS_TO_1BYTE(_Header, 0, 8)
-+#define GET_8814A_C2H_TXBF_MACID(_Header)				LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
-+
-+
-+
-+/* / TX Feedback Content */
-+#define	USEC_UNIT_FOR_8814A_C2H_TX_RPT_QUEUE_TIME			256
-+
-+#define	GET_8814A_C2H_TX_RPT_QUEUE_SELECT(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 0, 5)
-+#define	GET_8814A_C2H_TX_RPT_PKT_BROCAST(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 5, 1)
-+#define	GET_8814A_C2H_TX_RPT_LIFE_TIME_OVER(_Header)			LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
-+#define	GET_8814A_C2H_TX_RPT_RETRY_OVER(_Header)				LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
-+#define	GET_8814A_C2H_TX_RPT_MAC_ID(_Header)					LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
-+#define	GET_8814A_C2H_TX_RPT_DATA_RETRY_CNT(_Header)		LE_BITS_TO_1BYTE((_Header + 2), 0, 6)
-+#define	GET_8814A_C2H_TX_RPT_QUEUE_TIME(_Header)				LE_BITS_TO_2BYTE((_Header + 3), 0, 16)	/* In unit of 256 microseconds. */
-+#define	GET_8814A_C2H_TX_RPT_FINAL_DATA_RATE(_Header)		LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
-+
-+
-+/* _P2P_PS_OFFLOAD */
-+#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
-+#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value)				SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
-+#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
-+#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
-+#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
-+#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value)		SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
-+#define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value)			SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
-+
-+s32 FillH2CCmd_8814(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
-+void rtl8814_set_wowlan_cmd(_adapter *padapter, u8 enable);
-+void rtl8814_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
-+void rtl8814_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode);
-+u8 GetTxBufferRsvdPageNum8814(_adapter *padapter, bool wowlan);
-+void rtl8814_req_txrpt_cmd(PADAPTER padapter, u8 macid);
-+
-+void rtl8814a_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
-+
-+void
-+Set_RA_LDPC_8814(
-+	struct sta_info	*psta,
-+	BOOLEAN			bLDPC
-+);
-+
-+s32 c2h_handler_8814a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
-+
-+#ifdef CONFIG_BT_COEXIST
-+void rtl8814a_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
-+#endif /* CONFIG_BT_COEXIST */
-+#ifdef CONFIG_P2P_PS
-+	void rtl8814_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
-+#endif /* CONFIG_P2P */
-+
-+#endif/* __RTL8814A_CMD_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8814a_dm.h b/drivers/staging/rtl8723cs/include/rtl8814a_dm.h
-new file mode 100644
-index 000000000000..9762c1b411b1
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8814a_dm.h
-@@ -0,0 +1,23 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8814A_DM_H__
-+#define __RTL8814A_DM_H__
-+
-+void rtl8814_init_dm_priv(PADAPTER Adapter);
-+void rtl8814_deinit_dm_priv(PADAPTER Adapter);
-+void rtl8814_InitHalDm(PADAPTER Adapter);
-+void rtl8814_HalDmWatchDog(PADAPTER Adapter);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8814a_hal.h b/drivers/staging/rtl8723cs/include/rtl8814a_hal.h
-new file mode 100644
-index 000000000000..fb11eb71625e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8814a_hal.h
-@@ -0,0 +1,329 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8814A_HAL_H__
-+#define __RTL8814A_HAL_H__
-+
-+/* #include "hal_com.h" */
-+#include "hal_data.h"
-+
-+/* include HAL Related header after HAL Related compiling flags */
-+#include "rtl8814a_spec.h"
-+#include "rtl8814a_rf.h"
-+#include "rtl8814a_dm.h"
-+#include "rtl8814a_recv.h"
-+#include "rtl8814a_xmit.h"
-+#include "rtl8814a_cmd.h"
-+#include "rtl8814a_led.h"
-+#include "Hal8814PwrSeq.h"
-+#include "Hal8814PhyReg.h"
-+#include "Hal8814PhyCfg.h"
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	#include "rtl8814a_sreset.h"
-+#endif /* DBG_CONFIG_ERROR_DETECT */
-+
-+enum {
-+	VOLTAGE_V25						= 0x03,
-+	LDOE25_SHIFT					= 28 ,
-+};
-+/* max. iram is 64k , max dmen is 32k. Total = 96k = 0x18000*/
-+#define FW_SIZE							0x18000
-+#define FW_START_ADDRESS   0x1000
-+typedef struct _RT_FIRMWARE_8814 {
-+	FIRMWARE_SOURCE	eFWSource;
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+	u8			*szFwBuffer;
-+#else
-+	u8			szFwBuffer[FW_SIZE];
-+#endif
-+	u32			ulFwLength;
-+} RT_FIRMWARE_8814, *PRT_FIRMWARE_8814;
-+
-+#define PAGE_SIZE_TX_8814	PAGE_SIZE_128
-+/* BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_8814
-+ * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
-+
-+#define BCNQ_PAGE_NUM_8814		(MAX_BEACON_LEN / PAGE_SIZE_TX_8814 + 6) /*0x08*/
-+
-+#define Rtl8814A_NIC_PWR_ON_FLOW				rtl8814A_power_on_flow
-+#define Rtl8814A_NIC_RF_OFF_FLOW				rtl8814A_radio_off_flow
-+#define Rtl8814A_NIC_DISABLE_FLOW				rtl8814A_card_disable_flow
-+#define Rtl8814A_NIC_ENABLE_FLOW				rtl8814A_card_enable_flow
-+#define Rtl8814A_NIC_SUSPEND_FLOW				rtl8814A_suspend_flow
-+#define Rtl8814A_NIC_RESUME_FLOW				rtl8814A_resume_flow
-+#define Rtl8814A_NIC_PDN_FLOW					rtl8814A_hwpdn_flow
-+#define Rtl8814A_NIC_LPS_ENTER_FLOW			rtl8814A_enter_lps_flow
-+#define Rtl8814A_NIC_LPS_LEAVE_FLOW			rtl8814A_leave_lps_flow
-+
-+/* *****************************************************
-+ *				New	Firmware Header(8-byte alinment required)
-+ * *****************************************************
-+ * --- LONG WORD 0 ---- */
-+#define GET_FIRMWARE_HDR_SIGNATURE_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 0, 16)
-+#define GET_FIRMWARE_HDR_CATEGORY_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */
-+#define GET_FIRMWARE_HDR_FUNCTION_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
-+#define GET_FIRMWARE_HDR_VERSION_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */
-+#define GET_FIRMWARE_HDR_SUB_VER_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */
-+#define GET_FIRMWARE_HDR_SUB_IDX_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8) /* FW Subversion Index */
-+
-+/* --- LONG WORD 1 ---- */
-+#define GET_FIRMWARE_HDR_SVN_IDX_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+8, 0, 32)/* The SVN entry index */
-+#define GET_FIRMWARE_HDR_RSVD1_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+12, 0, 32)
-+
-+/* --- LONG WORD 2 ---- */
-+#define GET_FIRMWARE_HDR_MONTH_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+16, 0, 8) /* Release time Month field */
-+#define GET_FIRMWARE_HDR_DATE_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+16, 8, 8) /* Release time Date field */
-+#define GET_FIRMWARE_HDR_HOUR_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+16, 16, 8)/* Release time Hour field */
-+#define GET_FIRMWARE_HDR_MINUTE_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+16, 24, 8)/* Release time Minute field */
-+#define GET_FIRMWARE_HDR_YEAR_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+20, 0, 16)/* Release time Year field */
-+#define GET_FIRMWARE_HDR_FOUNDRY_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+20, 16, 8)/* Release time Foundry field */
-+#define GET_FIRMWARE_HDR_RSVD2_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+20, 24, 8)
-+
-+/* --- LONG WORD 3 ---- */
-+#define GET_FIRMWARE_HDR_MEM_UASGE_DL_FROM_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+24, 0, 1)
-+#define GET_FIRMWARE_HDR_MEM_UASGE_BOOT_FROM_3081(__FwHdr)	LE_BITS_TO_4BYTE(__FwHdr+24, 1, 1)
-+#define GET_FIRMWARE_HDR_MEM_UASGE_BOOT_LOADER_3081(__FwHdr)LE_BITS_TO_4BYTE(__FwHdr+24, 2, 1)
-+#define GET_FIRMWARE_HDR_MEM_UASGE_IRAM_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 3, 1)
-+#define GET_FIRMWARE_HDR_MEM_UASGE_ERAM_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 4, 1)
-+#define GET_FIRMWARE_HDR_MEM_UASGE_RSVD4_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+24, 5, 3)
-+#define GET_FIRMWARE_HDR_RSVD3_3081(__FwHdr)					LE_BITS_TO_4BYTE(__FwHdr+24, 8, 8)
-+#define GET_FIRMWARE_HDR_BOOT_LOADER_SZ_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+24, 16, 16)
-+#define GET_FIRMWARE_HDR_RSVD5_3081(__FwHdr)					LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)
-+
-+/* --- LONG WORD 4 ---- */
-+#define GET_FIRMWARE_HDR_TOTAL_DMEM_SZ_3081(__FwHdr)	LE_BITS_TO_4BYTE(__FwHdr+36, 0, 32)
-+#define GET_FIRMWARE_HDR_FW_CFG_SZ_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+36, 0, 16)
-+#define GET_FIRMWARE_HDR_FW_ATTR_SZ_3081(__FwHdr)		LE_BITS_TO_4BYTE(__FwHdr+36, 16, 16)
-+
-+/* --- LONG WORD 5 ---- */
-+#define GET_FIRMWARE_HDR_IROM_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+40, 0, 32)
-+#define GET_FIRMWARE_HDR_EROM_3081(__FwHdr)				LE_BITS_TO_4BYTE(__FwHdr+44, 0, 32)
-+
-+/* --- LONG WORD 6 ---- */
-+#define GET_FIRMWARE_HDR_IRAM_SZ_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+48, 0, 32)
-+#define GET_FIRMWARE_HDR_ERAM_SZ_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+52, 0, 32)
-+
-+/* --- LONG WORD 7 ---- */
-+#define GET_FIRMWARE_HDR_RSVD6_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+56, 0, 32)
-+#define GET_FIRMWARE_HDR_RSVD7_3081(__FwHdr)			LE_BITS_TO_4BYTE(__FwHdr+60, 0, 32)
-+
-+
-+
-+/*
-+ * 2013/08/16 MH MOve from SDIO.h for common use.
-+ *   */
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
-+	#define TRX_SHARE_MODE_8814A				0	/* TRX Buffer Share Index */
-+	#define BASIC_RXFF_SIZE_8814A				24576/* Basic RXFF Size is 24K = 24*1024 Unit: Byte */
-+	#define TRX_SHARE_BUFF_UNIT_8814A			65536/* TRX Share Buffer unit Size 64K = 64*1024 Unit: Byte */
-+	#define TRX_SHARE_BUFF_UNIT_PAGE_8814A	(TRX_SHARE_BUFF_UNIT_8814A/PAGE_SIZE_8814A)/* 512 Pages */
-+
-+	/* Origin: */
-+	#define  HPQ_PGNUM_8814A					0x20	/* High Queue */
-+	#define  LPQ_PGNUM_8814A					0x20	/* Low Queue */
-+	#define  NPQ_PGNUM_8814A					0x20	/* Normal Queue */
-+	#define  EPQ_PGNUM_8814A					0x20	/* Extra Queue */
-+
-+#else	/*  #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) */
-+
-+	#define  HPQ_PGNUM_8814A		20
-+	#define  NPQ_PGNUM_8814A		20
-+	#define  LPQ_PGNUM_8814A		20 /* 1972 */
-+	#define  EPQ_PGNUM_8814A		20
-+	#define  BCQ_PGNUM_8814A		32
-+
-+#endif /* #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) */
-+
-+#ifdef CONFIG_WOWLAN
-+	#define WOWLAN_PAGE_NUM_8814	0x06
-+#else
-+	#define WOWLAN_PAGE_NUM_8814	0x00
-+#endif
-+
-+#define PAGE_SIZE_8814A						128/* TXFF Page Size, Unit: Byte */
-+#define MAX_RX_DMA_BUFFER_SIZE_8814A		0x5C00	/* BASIC_RXFF_SIZE_8814A + TRX_SHARE_MODE_8814A * TRX_SHARE_BUFF_UNIT_8814A */ /* Basic RXFF Size + ShareBuffer Size */
-+#define TX_PAGE_BOUNDARY_8814A			TXPKT_PGNUM_8814A	/* Need to enlarge boundary, by KaiYuan */
-+#define TX_PAGE_BOUNDARY_WOWLAN_8814A	TXPKT_PGNUM_8814A	/* TODO: 20130415 KaiYuan Check this value later */
-+
-+#ifdef CONFIG_FW_C2H_DEBUG
-+	#define RX_DMA_RESERVED_SIZE_8814A	0x100	/* 256B, reserved for c2h debug message */
-+#else
-+	#define RX_DMA_RESERVED_SIZE_8814A	0x0	/* 0B */
-+#endif
-+#define RX_DMA_BOUNDARY_8814A		(MAX_RX_DMA_BUFFER_SIZE_8814A - RX_DMA_RESERVED_SIZE_8814A - 1)
-+
-+#define  TOTAL_PGNUM_8814A		2048
-+#define  TXPKT_PGNUM_8814A		(2048 - BCNQ_PAGE_NUM_8814-WOWLAN_PAGE_NUM_8814)
-+#define  PUB_PGNUM_8814A		(TXPKT_PGNUM_8814A-HPQ_PGNUM_8814A-NPQ_PGNUM_8814A-LPQ_PGNUM_8814A-EPQ_PGNUM_8814A)
-+
-+/* Note: For WMM Normal Chip Setting ,modify later */
-+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8814A	TX_PAGE_BOUNDARY_8814A
-+#define WMM_NORMAL_TX_PAGE_BOUNDARY_8814A		(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8814A + 1)
-+
-+#define DRIVER_EARLY_INT_TIME_8814		0x05
-+#define BCN_DMA_ATIME_INT_TIME_8814		0x02
-+
-+
-+#define MAX_PAGE_SIZE			4096	/* @ page : 4k bytes */
-+
-+#define EFUSE_MAX_SECTION_JAGUAR				64
-+
-+#define	HWSET_MAX_SIZE_8814A			512
-+
-+#define	EFUSE_REAL_CONTENT_LEN_8814A	1024
-+#define	EFUSE_MAX_BANK_8814A		2
-+
-+#define	EFUSE_MAP_LEN_8814A			512
-+#define	EFUSE_MAX_SECTION_8814A		64
-+#define	EFUSE_MAX_WORD_UNIT_8814A		4
-+#define	EFUSE_PROTECT_BYTES_BANK_8814A		16
-+
-+#define	EFUSE_IC_ID_OFFSET_8814A		506	/* For some inferiority IC purpose. added by Roger, 2009.09.02. */
-+#define AVAILABLE_EFUSE_ADDR_8814A(addr)	(addr < EFUSE_REAL_CONTENT_LEN_8814A)
-+
-+/*-------------------------------------------------------------------------
-+Chip specific
-+-------------------------------------------------------------------------*/
-+
-+/* pic buffer descriptor */
-+#if 1 /* according to the define in the rtw_xmit.h, rtw_recv.h */
-+	#define RTL8814AE_SEG_NUM  TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */
-+	#define TX_DESC_NUM_8814A  TX_BD_NUM   /* 128 */
-+	#define RX_DESC_NUM_8814A  PCI_MAX_RX_COUNT /* 128 */
-+	#ifdef CONFIG_CONCURRENT_MODE
-+		#define BE_QUEUE_TX_DESC_NUM_8814A  (TX_BD_NUM<<1)    /* 256 */
-+	#else
-+		#define BE_QUEUE_TX_DESC_NUM_8814A  (TX_BD_NUM+(TX_BD_NUM>>1)) /* 192 */
-+	#endif
-+#else
-+	#define RTL8814AE_SEG_NUM  TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */
-+	#define TX_DESC_NUM_8814A  128 /* 1024//2048 change by ylb 20130624 */
-+	#define RX_DESC_NUM_8814A  128 /* 1024 //512 change by ylb 20130624 */
-+#endif
-+
-+/* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
-+ * 9bytes + 1byt + 5bytes and pre 1byte.
-+ * For worst case:
-+ * | 1byte|----8bytes----|1byte|--5bytes--|
-+ * |         |            Reserved(14bytes)	      |
-+ *   */
-+#define	EFUSE_OOB_PROTECT_BYTES		15	/* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
-+
-+#ifdef CONFIG_FILE_FWIMG
-+extern char *rtw_fw_file_path;
-+#ifdef CONFIG_WOWLAN
-+extern char *rtw_fw_wow_file_path;
-+#endif
-+#ifdef CONFIG_MP_INCLUDED
-+extern char *rtw_fw_mp_bt_file_path;
-+#endif /* CONFIG_MP_INCLUDED */
-+#endif /* CONFIG_FILE_FWIMG */
-+
-+/* rtl8814_hal_init.c */
-+s32 FirmwareDownload8814A(PADAPTER	Adapter, BOOLEAN bUsedWoWLANFw);
-+void	InitializeFirmwareVars8814(PADAPTER padapter);
-+
-+void
-+Hal_InitEfuseVars_8814A(
-+		PADAPTER	Adapter
-+);
-+
-+s32 InitLLTTable8814A(
-+		PADAPTER	Adapter
-+);
-+
-+
-+void InitRDGSetting8814A(PADAPTER padapter);
-+
-+/* void CheckAutoloadState8812A(PADAPTER padapter); */
-+
-+/* EFuse */
-+u8	GetEEPROMSize8814A(PADAPTER padapter);
-+void hal_InitPGData_8814A(
-+		PADAPTER padapter,
-+		u8 *PROMContent
-+);
-+
-+void	hal_ReadPROMVersion8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void	hal_ReadTxPowerInfo8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN	AutoLoadFail);
-+void	hal_ReadBoardType8814A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void	hal_ReadThermalMeter_8814A(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN	AutoloadFail);
-+void	hal_ReadChannelPlan8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void	hal_EfuseParseXtal_8814A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+void	hal_ReadAntennaDiversity8814A(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
-+void	hal_Read_TRX_antenna_8814A(PADAPTER	Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+void hal_ReadAmplifierType_8814A(
-+		PADAPTER		Adapter
-+);
-+void hal_ReadPAType_8814A(
-+		PADAPTER	Adapter,
-+		u8			*PROMContent,
-+		BOOLEAN		AutoloadFail,
-+		u8		*pPAType,
-+		u8		*pLNAType
-+);
-+
-+void hal_GetRxGainOffset_8814A(
-+	PADAPTER	Adapter,
-+	u8 			*PROMContent,
-+	BOOLEAN		AutoloadFail
-+);
-+void Hal_EfuseParseKFreeData_8814A(
-+			PADAPTER		Adapter,
-+			u8				*PROMContent,
-+			BOOLEAN			AutoloadFail);
-+void	hal_ReadRFEType_8814A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+void	hal_EfuseParseBTCoexistInfo8814A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+
-+/* void	hal_ReadUsbType_8812AU(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
-+ * int	FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); */
-+void	hal_ReadRemoteWakeup_8814A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
-+u8	MgntQuery_NssTxRate(u16 Rate);
-+
-+/* BOOLEAN HalDetectPwrDownMode8812(PADAPTER Adapter); */
-+
-+#ifdef CONFIG_WOWLAN
-+	void Hal_DetectWoWMode(PADAPTER pAdapter);
-+#endif /* CONFIG_WOWLAN */
-+
-+void _InitBeaconParameters_8814A(PADAPTER padapter);
-+void SetBeaconRelatedRegisters8814A(PADAPTER padapter);
-+
-+void ReadRFType8814A(PADAPTER padapter);
-+void InitDefaultValue8814A(PADAPTER padapter);
-+
-+u8 SetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval);
-+void GetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval);
-+u8 SetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+u8 GetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
-+void rtl8814_set_hal_ops(struct hal_ops *pHalFunc);
-+void init_hal_spec_8814a(_adapter *adapter);
-+
-+void rtl8814_start_thread(PADAPTER padapter);
-+void rtl8814_stop_thread(PADAPTER padapter);
-+
-+
-+#ifdef CONFIG_PCI_HCI
-+	BOOLEAN	InterruptRecognized8814AE(PADAPTER Adapter);
-+	void	UpdateInterruptMask8814AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
-+	void	InitMAC_TRXBD_8814AE(PADAPTER Adapter);
-+	void rtl8814ae_reset_desc_ring(_adapter *padapter);
-+	u16	get_txbd_rw_reg(u16 ff_hwaddr);
-+#endif
-+
-+#ifdef CONFIG_BT_COEXIST
-+	void rtl8814a_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
-+#endif
-+
-+#endif /* __RTL8188E_HAL_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8814a_led.h b/drivers/staging/rtl8723cs/include/rtl8814a_led.h
-new file mode 100644
-index 000000000000..cc457921efa1
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8814a_led.h
-@@ -0,0 +1,36 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8814A_LED_H__
-+#define __RTL8814A_LED_H__
-+
-+#ifdef CONFIG_RTW_SW_LED
-+/* ********************************************************************************
-+ * Interface to manipulate LED objects.
-+ * ******************************************************************************** */
-+#ifdef CONFIG_USB_HCI
-+	void rtl8814au_InitSwLeds(PADAPTER padapter);
-+	void rtl8814au_DeInitSwLeds(PADAPTER padapter);
-+#endif /* CONFIG_USB_HCI */
-+#ifdef CONFIG_PCI_HCI
-+	void rtl8814ae_InitSwLeds(PADAPTER padapter);
-+	void rtl8814ae_DeInitSwLeds(PADAPTER padapter);
-+#endif /* CONFIG_PCI_HCI */
-+#ifdef CONFIG_SDIO_HCI
-+	void rtl8814s_InitSwLeds(PADAPTER padapter);
-+	void rtl8814s_DeInitSwLeds(PADAPTER padapter);
-+#endif /* CONFIG_SDIO_HCI */
-+
-+#endif /* __RTL8814A_LED_H__ */
-+#endif /*CONFIG_RTW_SW_LED*/
-diff --git a/drivers/staging/rtl8723cs/include/rtl8814a_recv.h b/drivers/staging/rtl8723cs/include/rtl8814a_recv.h
-new file mode 100644
-index 000000000000..68da6333178c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8814a_recv.h
-@@ -0,0 +1,182 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8814A_RECV_H__
-+#define __RTL8814A_RECV_H__
-+
-+#if defined(CONFIG_USB_HCI)
-+
-+	#ifndef MAX_RECVBUF_SZ
-+		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
-+			#ifdef CONFIG_PLATFORM_MSTAR
-+				#define MAX_RECVBUF_SZ (8192) /* 8K */
-+			#else
-+				#define MAX_RECVBUF_SZ (32768) /* 32k */
-+			#endif
-+			/* #define MAX_RECVBUF_SZ (24576) */ /* 24k */
-+			/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
-+			/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
-+			/* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */
-+			/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
-+		#else
-+			#define MAX_RECVBUF_SZ (4000) /* about 4K */
-+		#endif
-+	#endif /* !MAX_RECVBUF_SZ */
-+
-+#elif defined(CONFIG_PCI_HCI)
-+	/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
-+	/*	#define MAX_RECVBUF_SZ (9100) */
-+	/* #else */
-+	#define MAX_RECVBUF_SZ (4000) /* about 4K
-+	* #endif */
-+
-+
-+#elif defined(CONFIG_SDIO_HCI)
-+	#if 0
-+		/* temp solution */
-+		#ifdef CONFIG_SDIO_RX_COPY
-+			#define MAX_RECVBUF_SZ (10240)
-+		#else /*  !CONFIG_SDIO_RX_COPY */
-+			#define MAX_RECVBUF_SZ	MAX_RX_DMA_BUFFER_SIZE_8821
-+		#endif /*  !CONFIG_SDIO_RX_COPY */
-+	#endif
-+#endif
-+
-+
-+/* RX buffer descriptor */
-+/* DWORD 0 */
-+#define SET_RX_BUFFER_DESC_DATA_LENGTH_8814A(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
-+#define SET_RX_BUFFER_DESC_LS_8814A(__pRxStatusDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 14, 1, __Value)
-+#define SET_RX_BUFFER_DESC_FS_8814A(__pRxStatusDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
-+#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8814A(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 16, __Value)
-+
-+#define GET_RX_BUFFER_DESC_OWN_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
-+#define GET_RX_BUFFER_DESC_LS_8814A(__pRxStatusDesc)							LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
-+#define GET_RX_BUFFER_DESC_FS_8814A(__pRxStatusDesc)							LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
-+#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
-+
-+/* DWORD 1 */
-+#define SET_RX_BUFFER_PHYSICAL_LOW_8814A(__pRxStatusDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
-+#define GET_RX_BUFFER_PHYSICAL_LOW_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 32)
-+
-+/* DWORD 2 */
-+#define SET_RX_BUFFER_PHYSICAL_HIGH_8814A(__pRxStatusDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
-+
-+/* DWORD 3*/ /* RESERVED */
-+
-+
-+#if 0
-+	/* =============
-+	* RX Info
-+	* ============== */
-+#endif
-+/* DWORD 0 */
-+#define SET_RX_STATUS_DESC_PKT_LEN_8814A(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
-+#define SET_RX_STATUS_DESC_EOR_8814A(__pRxStatusDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
-+#define SET_RX_STATUS_DESC_OWN_8814AE(__pRxStatusDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
-+
-+#define GET_RX_STATUS_DESC_PKT_LEN_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
-+#define GET_RX_STATUS_DESC_CRC32_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
-+#define GET_RX_STATUS_DESC_ICV_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
-+#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
-+#define GET_RX_STATUS_DESC_SECURITY_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
-+#define GET_RX_STATUS_DESC_QOS_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
-+#define GET_RX_STATUS_DESC_SHIFT_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
-+#define GET_RX_STATUS_DESC_PHY_STATUS_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
-+#define GET_RX_STATUS_DESC_SWDEC_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
-+#define GET_RX_STATUS_DESC_LAST_SEG_8814AE(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
-+#define GET_RX_STATUS_DESC_EOR_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
-+
-+/* DWORD 1 */
-+#define GET_RX_STATUS_DESC_MACID_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 7)
-+#define GET_RX_STATUS_DESC_EXT_SECTYPE_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 7, 1)/* 20130415 KaiYuan add for 8814 */
-+#define GET_RX_STATUS_DESC_TID_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 8, 4)
-+#define GET_RX_STATUS_DESC_MACID_VLD_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 12, 1)
-+#define GET_RX_STATUS_DESC_AMSDU_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 13, 1)
-+#define GET_RX_STATUS_DESC_RXID_MATCH_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 14, 1)
-+#define GET_RX_STATUS_DESC_PAGGR_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 15, 1)
-+#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHKERR_8814A(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 20, 1)
-+#define GET_RX_STATUS_DESC_TCPOFFLOAD_IPVER_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 21, 1)
-+#define GET_RX_STATUS_DESC_TCPOFFLOAD_IS_TCPUDP_8814A(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 22, 1)
-+#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHK_VLD_8814A(__pRxStatusDesc)		LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 23, 1)
-+#define GET_RX_STATUS_DESC_PAM_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 24, 1)
-+#define GET_RX_STATUS_DESC_PWR_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 1)
-+#define GET_RX_STATUS_DESC_MORE_DATA_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 26, 1)
-+#define GET_RX_STATUS_DESC_MORE_FRAG_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 27, 1)
-+#define GET_RX_STATUS_DESC_TYPE_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 2)
-+#define GET_RX_STATUS_DESC_FIRST_SEG_8814AE(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
-+#define GET_RX_STATUS_DESC_EOR_8814AE(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
-+#define GET_RX_STATUS_DESC_MC_8814A(__pRxStatusDesc)							LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 1)
-+#define GET_RX_STATUS_DESC_BC_8814A(__pRxStatusDesc)							LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 31, 1)
-+
-+/* DWORD 2 */
-+#define GET_RX_STATUS_DESC_SEQ_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
-+#define GET_RX_STATUS_DESC_FRAG_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
-+#ifdef CONFIG_USB_RX_AGGREGATION
-+	#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 8)
-+#else
-+	#define GET_RX_STATUS_DESC_RX_IS_QOS_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
-+#endif
-+#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
-+#define GET_RX_STATUS_DESC_HWRSVD_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 24, 4)
-+#define GET_RX_STATUS_C2H_8814A(__pRxStatusDesc)								LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
-+#define GET_RX_STATUS_DESC_FCS_OK_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
-+
-+/* DWORD 3 */
-+#define GET_RX_STATUS_DESC_RX_RATE_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
-+#define GET_RX_STATUS_DESC_BSSID_FIT_H_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 7, 3)/* 20130415 KaiYuan add for 8814 */
-+#define GET_RX_STATUS_DESC_HTC_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
-+#define GET_RX_STATUS_DESC_EOSP_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
-+#define GET_RX_STATUS_DESC_BSSID_FIT_L_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
-+#define GET_RX_STATUS_DESC_DMA_AGG_NUM_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)/* 20130415 KaiYuan Check if it exist anymore */
-+#define GET_RX_STATUS_DESC_PATTERN_MATCH_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 29, 1)
-+#define GET_RX_STATUS_DESC_UNICAST_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 30, 1)
-+#define GET_RX_STATUS_DESC_MAGIC_WAKE_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 31, 1)
-+
-+/* DWORD 4 */
-+#define GET_RX_STATUS_DESC_PATTERN_IDX_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 0, 8)
-+#define GET_RX_STATUS_DESC_RX_EOF_8814A(__pRxStatusDesc)					LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 8, 1)
-+#define GET_RX_STATUS_DESC_RX_SCRAMBLER_8814A(__pRxStatusDesc)				LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 9, 7)
-+#define GET_RX_STATUS_DESC_RX_PRE_NDP_VLD_8814A(__pRxStatusDesc)			LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 16, 1)
-+#define GET_RX_STATUS_DESC_A1_FIT_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 24, 5)
-+
-+
-+/* DWORD 5 */
-+#define GET_RX_STATUS_DESC_TSFL_8814A(__pRxStatusDesc)						LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
-+
-+
-+/* Rx smooth factor */
-+#define Rx_Smooth_Factor (20)
-+
-+#ifdef CONFIG_USB_HCI
-+	s32 rtl8814au_init_recv_priv(PADAPTER padapter);
-+	void rtl8814au_free_recv_priv(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8814ae_init_recv_priv(PADAPTER padapter);
-+	void rtl8814ae_free_recv_priv(PADAPTER padapter);
-+#endif
-+
-+#if 0
-+	/* temp solution */
-+	#ifdef CONFIG_SDIO_HCI
-+		s32 InitRecvPriv8821AS(PADAPTER padapter);
-+		void FreeRecvPriv8821AS(PADAPTER padapter);
-+	#endif /*  CONFIG_SDIO_HCI */
-+#endif
-+
-+void rtl8814_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
-+
-+#endif /* __RTL8814A_RECV_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8814a_rf.h b/drivers/staging/rtl8723cs/include/rtl8814a_rf.h
-new file mode 100644
-index 000000000000..9bb099c925a5
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8814a_rf.h
-@@ -0,0 +1,28 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8814A_RF_H__
-+#define __RTL8814A_RF_H__
-+
-+void
-+PHY_RF6052SetBandwidth8814A(
-+		PADAPTER				Adapter,
-+		enum channel_width		Bandwidth);
-+
-+
-+int
-+PHY_RF6052_Config_8814A(
-+		PADAPTER	Adapter);
-+
-+#endif/* __RTL8188E_RF_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8814a_spec.h b/drivers/staging/rtl8723cs/include/rtl8814a_spec.h
-new file mode 100644
-index 000000000000..a27ab8872c0c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8814a_spec.h
-@@ -0,0 +1,653 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8814A_SPEC_H__
-+#define __RTL8814A_SPEC_H__
-+
-+#include <drv_conf.h>
-+
-+
-+/* ************************************************************
-+ *
-+ * ************************************************************ */
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0000h ~ 0x00FFh	System Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_SYS_ISO_CTRL_8814A			0x0000	/* 2 Byte */
-+#define REG_SYS_FUNC_EN_8814A			0x0002	/* 2 Byte */
-+#define REG_SYS_PW_CTRL_8814A			0x0004	/* 4 Byte        */
-+#define REG_SYS_CLKR_8814A				0x0008	/* 2 Byte */
-+#define REG_SYS_EEPROM_CTRL_8814A		0x000A	/* 2 Byte        */
-+#define REG_EE_VPD_8814A				0x000C	/* 2 Byte */
-+#define REG_SYS_SWR_CTRL1_8814A			0x0010	/* 1 Byte */
-+#define REG_SPS0_CTRL_8814A				0x0011	/* 7 Byte */
-+#define REG_SYS_SWR_CTRL3_8814A			0x0018	/* 4 Byte */
-+#define REG_RSV_CTRL_8814A				0x001C	/* 3 Byte */
-+#define REG_RF_CTRL0_8814A				0x001F	/* 1 Byte */
-+#define REG_RF_CTRL1_8814A				0x0020	/* 1 Byte */
-+#define REG_RF_CTRL2_8814A				0x0021	/* 1 Byte */
-+#define REG_LPLDO_CTRL_8814A			0x0023	/* 1 Byte */
-+#define REG_AFE_CTRL1_8814A				0x0024	/* 4 Byte        */
-+#define REG_AFE_CTRL2_8814A				0x0028	/* 4 Byte        */
-+#define REG_AFE_CTRL3_8814A				0x002c	/* 4 Byte  */
-+#define REG_EFUSE_CTRL_8814A			0x0030
-+#define REG_LDO_EFUSE_CTRL_8814A		0x0034
-+#define REG_PWR_DATA_8814A				0x0038
-+#define REG_CAL_TIMER_8814A				0x003C
-+#define REG_ACLK_MON_8814A				0x003E
-+#define REG_GPIO_MUXCFG_8814A			0x0040
-+#define REG_GPIO_IO_SEL_8814A			0x0042
-+#define REG_MAC_PINMUX_CFG_8814A		0x0043
-+#define REG_GPIO_PIN_CTRL_8814A			0x0044
-+#define REG_GPIO_INTM_8814A				0x0048
-+#define REG_LEDCFG0_8814A				0x004C
-+#define REG_LEDCFG1_8814A				0x004D
-+#define REG_LEDCFG2_8814A				0x004E
-+#define REG_LEDCFG3_8814A				0x004F
-+#define REG_FSIMR_8814A					0x0050
-+#define REG_FSISR_8814A					0x0054
-+#define REG_HSIMR_8814A					0x0058
-+#define REG_HSISR_8814A					0x005c
-+#define REG_GPIO_EXT_CTRL_8814A			0x0060
-+#define REG_GPIO_STATUS_8814A			0x006C
-+#define REG_SDIO_CTRL_8814A				0x0070
-+#define REG_HCI_OPT_CTRL_8814A			0x0074
-+#define REG_RF_CTRL3_8814A				0x0076	/* 1 Byte */
-+#define REG_AFE_CTRL4_8814A				0x0078
-+#define REG_8051FW_CTRL_8814A			0x0080
-+#define REG_HIMR0_8814A					0x00B0
-+#define REG_HISR0_8814A					0x00B4
-+#define REG_HIMR1_8814A					0x00B8
-+#define REG_HISR1_8814A					0x00BC
-+#define REG_SYS_CFG1_8814A				0x00F0
-+#define REG_SYS_CFG2_8814A				0x00FC
-+#define REG_SYS_CFG3_8814A				0x1000
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_CR_8814A						0x0100
-+#define REG_PBP_8814A					0x0104
-+#define REG_PKT_BUFF_ACCESS_CTRL_8814A	0x0106
-+#define REG_TRXDMA_CTRL_8814A			0x010C
-+#define REG_TRXFF_BNDY_8814A			0x0114
-+#define REG_TRXFF_STATUS_8814A			0x0118
-+#define REG_RXFF_PTR_8814A				0x011C
-+#define REG_CPWM_8814A					0x012F
-+#define REG_FWIMR_8814A					0x0130
-+#define REG_FWISR_8814A					0x0134
-+#define REG_FTIMR_8814A					0x0138
-+#define REG_PKTBUF_DBG_CTRL_8814A		0x0140
-+#define REG_RXPKTBUF_CTRL_8814A		0x0142
-+#define REG_PKTBUF_DBG_DATA_L_8814A	0x0144
-+#define REG_PKTBUF_DBG_DATA_H_8814A	0x0148
-+
-+#define REG_WOWLAN_WAKE_REASON			REG_MCUTST_WOWLAN
-+
-+#define REG_TC0_CTRL_8814A				0x0150
-+#define REG_TC1_CTRL_8814A				0x0154
-+#define REG_TC2_CTRL_8814A				0x0158
-+#define REG_TC3_CTRL_8814A				0x015C
-+#define REG_TC4_CTRL_8814A				0x0160
-+#define REG_TCUNIT_BASE_8814A			0x0164
-+#define REG_RSVD3_8814A					0x0168
-+#define REG_C2HEVT_MSG_NORMAL_8814A	0x01A0
-+#define REG_C2HEVT_CLEAR_8814A			0x01AF
-+#define REG_MCUTST_1_8814A				0x01C0
-+#define REG_MCUTST_WOWLAN_8814A		0x01C7
-+#define REG_FMETHR_8814A				0x01C8
-+#define REG_HMETFR_8814A				0x01CC
-+#define REG_HMEBOX_0_8814A				0x01D0
-+#define REG_HMEBOX_1_8814A				0x01D4
-+#define REG_HMEBOX_2_8814A				0x01D8
-+#define REG_HMEBOX_3_8814A				0x01DC
-+#define REG_LLT_INIT_8814A				0x01E0
-+#define REG_LLT_ADDR_8814A				0x01E4 /* 20130415 KaiYuan add for 8814 */
-+#define REG_HMEBOX_EXT0_8814A			0x01F0
-+#define REG_HMEBOX_EXT1_8814A			0x01F4
-+#define REG_HMEBOX_EXT2_8814A			0x01F8
-+#define REG_HMEBOX_EXT3_8814A			0x01FC
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_FIFOPAGE_CTRL_1_8814A			0x0200
-+#define REG_FIFOPAGE_CTRL_2_8814A		0x0204
-+#define REG_AUTO_LLT_8814A					0x0208
-+#define REG_TXDMA_OFFSET_CHK_8814A	0x020C
-+#define REG_TXDMA_STATUS_8814A			0x0210
-+#define REG_RQPN_NPQ_8814A				0x0214
-+#define REG_TQPNT1_8814A					0x0218
-+#define REG_TQPNT2_8814A					0x021C
-+#define REG_TQPNT3_8814A					0x0220
-+#define REG_TQPNT4_8814A					0x0224
-+#define REG_RQPN_CTRL_1_8814A				0x0228
-+#define REG_RQPN_CTRL_2_8814A				0x022C
-+#define REG_FIFOPAGE_INFO_1_8814A			0x0230
-+#define REG_FIFOPAGE_INFO_2_8814A			0x0234
-+#define REG_FIFOPAGE_INFO_3_8814A			0x0238
-+#define REG_FIFOPAGE_INFO_4_8814A			0x023C
-+#define REG_FIFOPAGE_INFO_5_8814A			0x0240
-+
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_RXDMA_AGG_PG_TH_8814A		0x0280
-+#define REG_RXPKT_NUM_8814A				0x0284 /* The number of packets in RXPKTBUF. */
-+#define REG_RXDMA_CONTROL_8814A			0x0286 /* ?????? Control the RX DMA. */
-+#define REG_RXDMA_STATUS_8814A			0x0288
-+#define REG_RXDMA_MODE_8814A				0x0290 /* ?????? */
-+#define REG_EARLY_MODE_CONTROL_8814A	0x02BC /* ?????? */
-+#define REG_RSVD5_8814A					0x02F0 /* ?????? */
-+
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0300h ~ 0x03FFh	PCIe
-+ *
-+ * ----------------------------------------------------- */
-+#define	REG_PCIE_CTRL_REG_8814A			0x0300
-+#define	REG_INT_MIG_8814A				0x0304	/* Interrupt Migration */
-+#define	REG_BCNQ_TXBD_DESA_8814A		0x0308	/* TX Beacon Descriptor Address */
-+#define	REG_MGQ_TXBD_DESA_8814A			0x0310	/* TX Manage Queue Descriptor Address */
-+#define	REG_VOQ_TXBD_DESA_8814A			0x0318	/* TX VO Queue Descriptor Address */
-+#define	REG_VIQ_TXBD_DESA_8814A			0x0320	/* TX VI Queue Descriptor Address */
-+#define	REG_BEQ_TXBD_DESA_8814A			0x0328	/* TX BE Queue Descriptor Address */
-+#define	REG_BKQ_TXBD_DESA_8814A			0x0330	/* TX BK Queue Descriptor Address */
-+#define	REG_RXQ_RXBD_DESA_8814A			0x0338	/* RX Queue	Descriptor Address */
-+#define REG_HI0Q_TXBD_DESA_8814A		0x0340
-+#define REG_HI1Q_TXBD_DESA_8814A		0x0348
-+#define REG_HI2Q_TXBD_DESA_8814A		0x0350
-+#define REG_HI3Q_TXBD_DESA_8814A		0x0358
-+#define REG_HI4Q_TXBD_DESA_8814A		0x0360
-+#define REG_HI5Q_TXBD_DESA_8814A		0x0368
-+#define REG_HI6Q_TXBD_DESA_8814A		0x0370
-+#define REG_HI7Q_TXBD_DESA_8814A		0x0378
-+#define	REG_MGQ_TXBD_NUM_8814A			0x0380
-+#define	REG_RX_RXBD_NUM_8814A			0x0382
-+#define	REG_VOQ_TXBD_NUM_8814A			0x0384
-+#define	REG_VIQ_TXBD_NUM_8814A			0x0386
-+#define	REG_BEQ_TXBD_NUM_8814A			0x0388
-+#define	REG_BKQ_TXBD_NUM_8814A			0x038A
-+#define	REG_HI0Q_TXBD_NUM_8814A			0x038C
-+#define	REG_HI1Q_TXBD_NUM_8814A			0x038E
-+#define	REG_HI2Q_TXBD_NUM_8814A			0x0390
-+#define	REG_HI3Q_TXBD_NUM_8814A			0x0392
-+#define	REG_HI4Q_TXBD_NUM_8814A			0x0394
-+#define	REG_HI5Q_TXBD_NUM_8814A			0x0396
-+#define	REG_HI6Q_TXBD_NUM_8814A			0x0398
-+#define	REG_HI7Q_TXBD_NUM_8814A			0x039A
-+#define	REG_TSFTIMER_HCI_8814A			0x039C
-+
-+/* Read Write Point */
-+#define	REG_VOQ_TXBD_IDX_8814A			0x03A0
-+#define	REG_VIQ_TXBD_IDX_8814A			0x03A4
-+#define	REG_BEQ_TXBD_IDX_8814A			0x03A8
-+#define	REG_BKQ_TXBD_IDX_8814A			0x03AC
-+#define	REG_MGQ_TXBD_IDX_8814A			0x03B0
-+#define	REG_RXQ_TXBD_IDX_8814A			0x03B4
-+#define	REG_HI0Q_TXBD_IDX_8814A			0x03B8
-+#define	REG_HI1Q_TXBD_IDX_8814A			0x03BC
-+#define	REG_HI2Q_TXBD_IDX_8814A			0x03C0
-+#define	REG_HI3Q_TXBD_IDX_8814A			0x03C4
-+#define	REG_HI4Q_TXBD_IDX_8814A			0x03C8
-+#define	REG_HI5Q_TXBD_IDX_8814A			0x03CC
-+#define	REG_HI6Q_TXBD_IDX_8814A			0x03D0
-+#define	REG_HI7Q_TXBD_IDX_8814A			0x03D4
-+#define REG_DBG_SEL_V1_8814A				0x03D8
-+#define REG_PCIE_HRPWM1_V1_8814A			0x03D9
-+#define REG_PCIE_HCPWM1_V1_8814A			0x03DA
-+#define REG_PCIE_CTRL2_8814A				0x03DB
-+#define REG_PCIE_HRPWM2_V1_8814A			0x03DC
-+#define REG_PCIE_HCPWM2_V1_8814A			0x03DE
-+#define REG_PCIE_H2C_MSG_V1_8814A		0x03E0
-+#define REG_PCIE_C2H_MSG_V1_8814A		0x03E4
-+#define REG_DBI_WDATA_V1_8814A			0x03E8
-+#define REG_DBI_RDATA_V1_8814A			0x03EC
-+#define REG_DBI_FLAG_V1_8814A				0x03F0
-+#define REG_MDIO_V1_8814A					0x03F4
-+#define REG_PCIE_MIX_CFG_8814A			0x03F8
-+#define REG_DBG_8814A						0x03FC
-+/* -----------------------------------------------------
-+ *
-+ *	0x0400h ~ 0x047Fh	Protocol Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_VOQ_INFORMATION_8814A		0x0400
-+#define REG_VIQ_INFORMATION_8814A		0x0404
-+#define REG_BEQ_INFORMATION_8814A		0x0408
-+#define REG_BKQ_INFORMATION_8814A		0x040C
-+#define REG_MGQ_INFORMATION_8814A		0x0410
-+#define REG_HGQ_INFORMATION_8814A		0x0414
-+#define REG_BCNQ_INFORMATION_8814A	0x0418
-+#define REG_TXPKT_EMPTY_8814A			0x041A
-+#define REG_CPU_MGQ_INFORMATION_8814A	0x041C
-+#define REG_FWHW_TXQ_CTRL_8814A		0x0420
-+#define REG_HWSEQ_CTRL_8814A			0x0423
-+#define REG_TXPKTBUF_BCNQ_BDNY_8814A	0x0424
-+/* #define REG_MGQ_BDNY_8814A				0x0425 */
-+#define REG_LIFETIME_EN_8814A				0x0426
-+/* #define REG_FW_FREE_TAIL_8814A			0x0427 */
-+#define REG_SPEC_SIFS_8814A				0x0428
-+#define REG_RETRY_LIMIT_8814A				0x042A
-+#define REG_TXBF_CTRL_8814A				0x042C
-+#define REG_DARFRC_8814A				0x0430
-+#define REG_RARFRC_8814A				0x0438
-+#define REG_RRSR_8814A					0x0440
-+#define REG_ARFR0_8814A					0x0444
-+#define REG_ARFR1_8814A					0x044C
-+#define REG_CCK_CHECK_8814A				0x0454
-+#define REG_AMPDU_MAX_TIME_8814A			0x0455
-+#define REG_TXPKTBUF_BCNQ1_BDNY_8814A	0x0456
-+#define REG_AMPDU_MAX_LENGTH_8814A	0x0458
-+#define REG_ACQ_STOP_8814A				0x045C
-+#define REG_NDPA_RATE_8814A				0x045D
-+#define REG_TX_HANG_CTRL_8814A			0x045E
-+#define REG_NDPA_OPT_CTRL_8814A		0x045F
-+#define REG_FAST_EDCA_CTRL_8814A		0x0460
-+#define REG_RD_RESP_PKT_TH_8814A		0x0463
-+#define REG_CMDQ_INFO_8814A				0x0464
-+#define REG_Q4_INFO_8814A					0x0468
-+#define REG_Q5_INFO_8814A					0x046C
-+#define REG_Q6_INFO_8814A					0x0470
-+#define REG_Q7_INFO_8814A					0x0474
-+#define REG_WMAC_LBK_BUF_HD_8814A		0x0478
-+#define REG_MGQ_PGBNDY_8814A				0x047A
-+#define REG_INIRTS_RATE_SEL_8814A			0x0480
-+#define REG_BASIC_CFEND_RATE_8814A		0x0481
-+#define REG_STBC_CFEND_RATE_8814A		0x0482
-+#define REG_DATA_SC_8814A					0x0483
-+#define REG_MACID_SLEEP3_8814A			0x0484
-+#define REG_MACID_SLEEP1_8814A			0x0488
-+#ifdef CONFIG_WOWLAN
-+	#define REG_TXPKTBUF_IV_LOW				0x0484
-+	#define REG_TXPKTBUF_IV_HIGH			0x0488
-+#endif /* CONFIG_WOWLAN */
-+#define REG_ARFR2_8814A					0x048C
-+#define REG_ARFR3_8814A					0x0494
-+#define REG_ARFR4_8814A					0x049C
-+#define REG_ARFR5_8814A					0x04A4
-+#define REG_TXRPT_START_OFFSET_8814A		0x04AC
-+#define REG_TRYING_CNT_TH_8814A			0x04B0
-+#define REG_POWER_STAGE1_8814A		0x04B4
-+#define REG_POWER_STAGE2_8814A		0x04B8
-+#define REG_SW_AMPDU_BURST_MODE_CTRL_8814A	0x04BC
-+#define REG_PKT_LIFE_TIME_8814A			0x04C0
-+#define REG_PKT_BE_BK_LIFE_TIME_8814A		0x04C2 /* ?????? */
-+#define REG_STBC_SETTING_8814A			0x04C4
-+#define REG_STBC_8814A						0x04C5
-+#define REG_QUEUE_CTRL_8814A				0x04C6
-+#define REG_SINGLE_AMPDU_CTRL_8814A		0x04C7
-+#define REG_PROT_MODE_CTRL_8814A		0x04C8
-+#define REG_MAX_AGGR_NUM_8814A		0x04CA
-+#define REG_RTS_MAX_AGGR_NUM_8814A	0x04CB
-+#define REG_BAR_MODE_CTRL_8814A		0x04CC
-+#define REG_RA_TRY_RATE_AGG_LMT_8814A	0x04CF
-+#define REG_MACID_SLEEP2_8814A			0x04D0
-+#define REG_MACID_SLEEP0_8814A			0x04D4
-+#define REG_HW_SEQ0_8814A				0x04D8
-+#define REG_HW_SEQ1_8814A				0x04DA
-+#define REG_HW_SEQ2_8814A				0x04DC
-+#define REG_HW_SEQ3_8814A				0x04DE
-+#define REG_NULL_PKT_STATUS_8814A			0x04E0
-+#define REG_PTCL_ERR_STATUS_8814A			0x04E2
-+#define REG_DROP_PKT_NUM_8814A			0x04EC
-+#define REG_PTCL_TX_RPT_8814A				0x04F0
-+#define REG_Dummy_8814A					0x04FC
-+
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0500h ~ 0x05FFh	EDCA Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_EDCA_VO_PARAM_8814A			0x0500
-+#define REG_EDCA_VI_PARAM_8814A			0x0504
-+#define REG_EDCA_BE_PARAM_8814A			0x0508
-+#define REG_EDCA_BK_PARAM_8814A			0x050C
-+#define REG_BCNTCFG_8814A					0x0510
-+#define REG_PIFS_8814A						0x0512
-+#define REG_RDG_PIFS_8814A					0x0513
-+#define REG_SIFS_CTX_8814A					0x0514
-+#define REG_SIFS_TRX_8814A					0x0516
-+#define REG_AGGR_BREAK_TIME_8814A			0x051A
-+#define REG_SLOT_8814A						0x051B
-+#define REG_TX_PTCL_CTRL_8814A				0x0520
-+#define REG_TXPAUSE_8814A					0x0522
-+#define REG_DIS_TXREQ_CLR_8814A			0x0523
-+#define REG_RD_CTRL_8814A					0x0524
-+/*
-+ * Format for offset 540h-542h:
-+ *	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
-+ *	[7:4]:   Reserved.
-+ *	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
-+ *	[23:20]: Reserved
-+ * Description:
-+ *	              |
-+ * |<--Setup--|--Hold------------>|
-+ *	--------------|----------------------
-+ * |
-+ * TBTT
-+ * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
-+ * Described by Designer Tim and Bruce, 2011-01-14.
-+ *   */
-+#define REG_TBTT_PROHIBIT_8814A			0x0540
-+#define REG_RD_NAV_NXT_8814A				0x0544
-+#define REG_NAV_PROT_LEN_8814A			0x0546
-+#define REG_BCN_CTRL_8814A					0x0550
-+#define REG_BCN_CTRL_1_8814A				0x0551
-+#define REG_MBID_NUM_8814A				0x0552
-+#define REG_DUAL_TSF_RST_8814A				0x0553
-+#define REG_MBSSID_BCN_SPACE_8814A		0x0554
-+#define REG_DRVERLYINT_8814A				0x0558
-+#define REG_BCNDMATIM_8814A				0x0559
-+#define REG_ATIMWND_8814A					0x055A
-+#define REG_USTIME_TSF_8814A				0x055C
-+#define REG_BCN_MAX_ERR_8814A				0x055D
-+#define REG_RXTSF_OFFSET_CCK_8814A		0x055E
-+#define REG_RXTSF_OFFSET_OFDM_8814A		0x055F
-+#define REG_TSFTR_8814A						0x0560
-+#define REG_CTWND_8814A					0x0572
-+#define REG_SECONDARY_CCA_CTRL_8814A		0x0577 /* ?????? */
-+#define REG_PSTIMER_8814A					0x0580
-+#define REG_TIMER0_8814A					0x0584
-+#define REG_TIMER1_8814A					0x0588
-+#define REG_BCN_PREDL_ITV_8814A			0x058F	/* Pre download beacon interval */
-+#define REG_ACMHWCTRL_8814A				0x05C0
-+#define REG_P2P_RST_8814A				0x05F0
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0x0600h ~ 0x07FFh	WMAC Configuration
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_MAC_CR_8814A					0x0600
-+#define REG_TCR_8814A						0x0604
-+#define REG_RCR_8814A						0x0608
-+#define REG_RX_PKT_LIMIT_8814A				0x060C
-+#define REG_RX_DLK_TIME_8814A				0x060D
-+#define REG_RX_DRVINFO_SZ_8814A			0x060F
-+
-+#define REG_MACID_8814A					0x0610
-+#define REG_BSSID_8814A						0x0618
-+#define REG_MAR_8814A						0x0620
-+#define REG_MBIDCAMCFG_8814A				0x0628
-+
-+#define REG_USTIME_EDCA_8814A				0x0638
-+#define REG_MAC_SPEC_SIFS_8814A			0x063A
-+#define REG_RESP_SIFP_CCK_8814A			0x063C
-+#define REG_RESP_SIFS_OFDM_8814A			0x063E
-+#define REG_ACKTO_8814A					0x0640
-+#define REG_CTS2TO_8814A					0x0641
-+#define REG_EIFS_8814A						0x0642
-+
-+#define	REG_NAV_UPPER_8814A				0x0652	/* unit of 128 */
-+#define REG_TRXPTCL_CTL_8814A				0x0668
-+
-+/* Security */
-+#define REG_CAMCMD_8814A					0x0670
-+#define REG_CAMWRITE_8814A				0x0674
-+#define REG_CAMREAD_8814A					0x0678
-+#define REG_CAMDBG_8814A					0x067C
-+#define REG_SECCFG_8814A					0x0680
-+
-+/* Power */
-+#define REG_WOW_CTRL_8814A				0x0690
-+#define REG_PS_RX_INFO_8814A				0x0692
-+#define REG_UAPSD_TID_8814A				0x0693
-+#define REG_WKFMCAM_NUM_8814A			0x0698
-+#define REG_RXFLTMAP0_8814A				0x06A0
-+#define REG_RXFLTMAP1_8814A				0x06A2
-+#define REG_RXFLTMAP2_8814A				0x06A4
-+#define REG_BCN_PSR_RPT_8814A				0x06A8
-+#define REG_BT_COEX_TABLE_8814A			0x06C0
-+#define REG_TX_DATA_RSP_RATE_8814A		0x06DE
-+#define REG_ASSOCIATED_BFMER0_INFO_8814A	0x06E4
-+#define REG_ASSOCIATED_BFMER1_INFO_8814A	0x06EC
-+#define REG_CSI_RPT_PARAM_BW20_8814A		0x06F4
-+#define REG_CSI_RPT_PARAM_BW40_8814A		0x06F8
-+#define REG_CSI_RPT_PARAM_BW80_8814A		0x06FC
-+
-+/* Hardware Port 2 */
-+#define REG_MACID1_8814A					0x0700
-+#define REG_BSSID1_8814A					0x0708
-+/* Hardware Port 3 */
-+#define REG_MACID2_8814A					0x1620
-+#define REG_BSSID2_8814A					0x1628
-+/* Hardware Port 4 */
-+#define REG_MACID3_8814A					0x1630
-+#define REG_BSSID3_8814A					0x1638
-+/* Hardware Port 5 */
-+#define REG_MACID4_8814A					0x1640
-+#define REG_BSSID4_8814A					0x1648
-+
-+#define REG_ASSOCIATED_BFMEE_SEL_8814A	0x0714
-+#define REG_SND_PTCL_CTRL_8814A			0x0718
-+#define REG_IQ_DUMP_8814A					0x07C0
-+
-+#define REG_CPU_DMEM_CON_8814A			0x1080
-+
-+/**** page 19 ****/
-+/* TX BeamForming */
-+#define	REG_BB_TXBF_ANT_SET_BF1				0x19ac
-+#define	REG_BB_TXBF_ANT_SET_BF0				0x19b4
-+
-+/*	0x1200h ~ 0x12FFh	DDMA CTRL
-+ *
-+ * ----------------------------------------------------- */
-+#define REG_DDMA_CH0SA                   0x1200
-+#define REG_DDMA_CH0DA                   0x1204
-+#define REG_DDMA_CH0CTRL                0x1208
-+#define REG_DDMA_CH1SA                   0x1210
-+#define REG_DDMA_CH1DA	0x1214
-+#define REG_DDMA_CH1CTRL                0x1218
-+#define REG_DDMA_CH2SA                   0x1220
-+#define REG_DDMA_CH2DA                   0x1224
-+#define REG_DDMA_CH2CTRL                0x1228
-+#define REG_DDMA_CH3SA                   0x1230
-+#define REG_DDMA_CH3DA                   0x1234
-+#define REG_DDMA_CH3CTRL                0x1238
-+#define REG_DDMA_CH4SA                   0x1240
-+#define REG_DDMA_CH4DA                   0x1244
-+#define REG_DDMA_CH4CTRL                0x1248
-+#define REG_DDMA_CH5SA                   0x1250
-+#define REG_DDMA_CH5DA                   0x1254
-+#define REG_DDMA_CH5CTRL                0x1258
-+#define REG_DDMA_INT_MSK                0x12E0
-+#define REG_DDMA_CHSTATUS              0x12E8
-+#define REG_DDMA_CHKSUM                 0x12F0
-+#define REG_DDMA_MONITER                0x12FC
-+
-+#define REG_Q0_Q1_INFO_8814A		0x1400
-+#define REG_Q2_Q3_INFO_8814A		0x1404
-+#define REG_Q4_Q5_INFO_8814A		0x1408
-+#define REG_Q6_Q7_INFO_8814A		0x140C
-+#define REG_MGQ_HIQ_INFO_8814A	0x1410
-+#define REG_CMDQ_BCNQ_INFO_8814A	0x1414
-+
-+#define REG_MACID_DROP0_8814A 0x1450
-+#define REG_MACID_DROP1_8814A 0x1454
-+#define REG_MACID_DROP2_8814A 0x1458
-+#define REG_MACID_DROP3_8814A 0x145C
-+
-+#define DDMA_LEN_MASK		0x0001FFFF
-+#define FW_CHKSUM_DUMMY_SZ		8
-+#define DDMA_CH_CHKSUM_CNT		BIT(24)
-+#define DDMA_RST_CHKSUM_STS		BIT(25)
-+#define DDMA_MODE_BLOCK_CPU		BIT(26)
-+#define DDMA_CHKSUM_FAIL			BIT(27)
-+#define DDMA_DA_W_DISABLE			BIT(28)
-+#define DDMA_CHKSUM_EN			BIT(29)
-+#define DDMA_CH_OWN	BIT(31)
-+
-+
-+/* 3081 FWDL */
-+#define FWDL_EN                 BIT0
-+#define IMEM_BOOT_DL_RDY        BIT1
-+#define IMEM_BOOT_CHKSUM_FAIL   BIT2
-+#define IMEM_DL_RDY             BIT3
-+#define IMEM_CHKSUM_OK        BIT4
-+#define DMEM_DL_RDY             BIT5
-+#define DMEM_CHKSUM_OK        BIT6
-+#define EMEM_DL_RDY             BIT7
-+#define EMEM_CHKSUM_FAIL        BIT8
-+#define EMEM_TXBUF_DL_RDY       BIT9
-+#define EMEM_TXBUF_CHKSUM_FAIL  BIT10
-+#define CPU_CLK_SWITCH_BUSY     BIT11
-+#define CPU_CLK_SEL             (BIT12 | BIT13)
-+#define FWDL_OK                 BIT14
-+#define FW_INIT_RDY             BIT15
-+#define R_EN_BOOT_FLASH         BIT20
-+
-+#define OCPBASE_IMEM_3081        0x00000000
-+#define OCPBASE_DMEM_3081        0x00200000
-+#define OCPBASE_RPTBUF_3081      0x18660000
-+#define OCPBASE_RXBUF2_3081      0x18680000
-+#define OCPBASE_RXBUF_3081       0x18700000
-+#define OCPBASE_TXBUF_3081       0x18780000
-+
-+
-+#define REG_FAST_EDCA_VOVI_SETTING_8814A 0x1448
-+#define REG_FAST_EDCA_BEBK_SETTING_8814A 0x144C
-+
-+
-+/* -----------------------------------------------------
-+ *   */
-+
-+
-+/* -----------------------------------------------------
-+ *
-+ *	Redifine 8192C register definition for compatibility
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* TODO: use these definition when using REG_xxx naming rule.
-+ * NOTE: DO NOT Remove these definition. Use later. */
-+#define	EFUSE_CTRL_8814A					REG_EFUSE_CTRL_8814A		/* E-Fuse Control. */
-+#define	EFUSE_TEST_8814A					REG_LDO_EFUSE_CTRL_8814A		/* E-Fuse Test. */
-+#define	MSR_8814A							(REG_CR_8814A + 2)		/* Media Status register */
-+#define	ISR_8814A							REG_HISR0_8814A
-+#define	TSFR_8814A							REG_TSFTR_8814A			/* Timing Sync Function Timer Register. */
-+
-+#define PBP_8814A							REG_PBP_8814A
-+
-+/* Redifine MACID register, to compatible prior ICs. */
-+#define	IDR0_8814A							REG_MACID_8814A			/* MAC ID Register, Offset 0x0050-0x0053 */
-+#define	IDR4_8814A							(REG_MACID_8814A + 4)	/* MAC ID Register, Offset 0x0054-0x0055 */
-+
-+
-+/*
-+ * 9. Security Control Registers	(Offset: )
-+ *   */
-+#define	RWCAM_8814A						REG_CAMCMD_8814A		/*  8190 Data Sheet is called CAMcmd */
-+#define	WCAMI_8814A						REG_CAMWRITE_8814A		/* Software write CAM input content */
-+#define	RCAMO_8814A						REG_CAMREAD_8814A		/* Software read/write CAM config */
-+#define	CAMDBG_8814A						REG_CAMDBG_8814A
-+#define	SECR_8814A							REG_SECCFG_8814A		/* Security Configuration Register */
-+
-+
-+/* ----------------------------------------------------------------------------
-+ * 8195 IMR/ISR bits						(offset 0xB0,  8bits)
-+ * ---------------------------------------------------------------------------- */
-+#define	IMR_DISABLED_8814A					0
-+/* IMR DW0(0x00B0-00B3) Bit 0-31 */
-+#define	IMR_TIMER2_8814A					BIT31		/* Timeout interrupt 2 */
-+#define	IMR_TIMER1_8814A					BIT30		/* Timeout interrupt 1	 */
-+#define	IMR_PSTIMEOUT_8814A				BIT29		/* Power Save Time Out Interrupt */
-+#define	IMR_GTINT4_8814A					BIT28		/* When GTIMER4 expires, this bit is set to 1	 */
-+#define	IMR_GTINT3_8814A					BIT27		/* When GTIMER3 expires, this bit is set to 1	 */
-+#define	IMR_TXBCN0ERR_8814A				BIT26		/* Transmit Beacon0 Error			 */
-+#define	IMR_TXBCN0OK_8814A					BIT25		/* Transmit Beacon0 OK			 */
-+#define	IMR_TSF_BIT32_TOGGLE_8814A		BIT24		/* TSF Timer BIT32 toggle indication interrupt			 */
-+#define	IMR_BCNDMAINT0_8814A				BIT20		/* Beacon DMA Interrupt 0			 */
-+#define	IMR_BCNDERR0_8814A					BIT16		/* Beacon Queue DMA OK0			 */
-+#define	IMR_HSISR_IND_ON_INT_8814A		BIT15		/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
-+#define	IMR_BCNDMAINT_E_8814A				BIT14		/* Beacon DMA Interrupt Extension for Win7			 */
-+#define	IMR_ATIMEND_8814A					BIT12		/* CTWidnow End or ATIM Window End */
-+#define	IMR_C2HCMD_8814A					BIT10		/* CPU to Host Command INT Status, Write 1 clear	 */
-+#define	IMR_CPWM2_8814A					BIT9			/* CPU power Mode exchange INT Status, Write 1 clear	 */
-+#define	IMR_CPWM_8814A						BIT8			/* CPU power Mode exchange INT Status, Write 1 clear	 */
-+#define	IMR_HIGHDOK_8814A					BIT7			/* High Queue DMA OK	 */
-+#define	IMR_MGNTDOK_8814A					BIT6			/* Management Queue DMA OK	 */
-+#define	IMR_BKDOK_8814A					BIT5			/* AC_BK DMA OK		 */
-+#define	IMR_BEDOK_8814A					BIT4			/* AC_BE DMA OK	 */
-+#define	IMR_VIDOK_8814A					BIT3			/* AC_VI DMA OK		 */
-+#define	IMR_VODOK_8814A					BIT2			/* AC_VO DMA OK	 */
-+#define	IMR_RDU_8814A						BIT1			/* Rx Descriptor Unavailable	 */
-+#define	IMR_ROK_8814A						BIT0			/* Receive DMA OK */
-+
-+/* IMR DW1(0x00B4-00B7) Bit 0-31 */
-+#define	IMR_MCUERR_8814A						BIT28		/* Beacon DMA Interrupt 7 */
-+#define	IMR_BCNDMAINT7_8814A				BIT27		/* Beacon DMA Interrupt 7 */
-+#define	IMR_BCNDMAINT6_8814A				BIT26		/* Beacon DMA Interrupt 6 */
-+#define	IMR_BCNDMAINT5_8814A				BIT25		/* Beacon DMA Interrupt 5 */
-+#define	IMR_BCNDMAINT4_8814A				BIT24		/* Beacon DMA Interrupt 4 */
-+#define	IMR_BCNDMAINT3_8814A				BIT23		/* Beacon DMA Interrupt 3 */
-+#define	IMR_BCNDMAINT2_8814A				BIT22		/* Beacon DMA Interrupt 2 */
-+#define	IMR_BCNDMAINT1_8814A				BIT21		/* Beacon DMA Interrupt 1 */
-+#define	IMR_BCNDOK7_8814A					BIT20		/* Beacon Queue DMA OK Interrup 7 */
-+#define	IMR_BCNDOK6_8814A					BIT19		/* Beacon Queue DMA OK Interrup 6 */
-+#define	IMR_BCNDOK5_8814A					BIT18		/* Beacon Queue DMA OK Interrup 5 */
-+#define	IMR_BCNDOK4_8814A					BIT17		/* Beacon Queue DMA OK Interrup 4 */
-+#define	IMR_BCNDOK3_8814A					BIT16		/* Beacon Queue DMA OK Interrup 3 */
-+#define	IMR_BCNDOK2_8814A					BIT15		/* Beacon Queue DMA OK Interrup 2 */
-+#define	IMR_BCNDOK1_8814A					BIT14		/* Beacon Queue DMA OK Interrup 1 */
-+#define	IMR_ATIMEND_E_8814A				BIT13		/* ATIM Window End Extension for Win7 */
-+#define	IMR_TXERR_8814A					BIT11		/* Tx Error Flag Interrupt Status, write 1 clear. */
-+#define	IMR_RXERR_8814A					BIT10		/* Rx Error Flag INT Status, Write 1 clear */
-+#define	IMR_TXFOVW_8814A					BIT9			/* Transmit FIFO Overflow */
-+#define	IMR_RXFOVW_8814A					BIT8			/* Receive FIFO Overflow */
-+
-+
-+#ifdef CONFIG_PCI_HCI
-+	#define IMR_TX_MASK			(IMR_VODOK_8814A | IMR_VIDOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A | IMR_MGNTDOK_8814A | IMR_HIGHDOK_8814A)
-+
-+	#define RT_BCN_INT_MASKS	(IMR_BCNDMAINT0_8814A | IMR_TXBCN0OK_8814A | IMR_TXBCN0ERR_8814A | IMR_BCNDERR0_8814A)
-+
-+	#define RT_AC_INT_MASKS	(IMR_VIDOK_8814A | IMR_VODOK_8814A | IMR_BEDOK_8814A | IMR_BKDOK_8814A)
-+#endif
-+
-+
-+/*===================================================================
-+=====================================================================
-+Here the register defines are for 92C. When the define is as same with 92C,
-+we will use the 92C's define for the consistency
-+So the following defines for 92C is not entire!!!!!!
-+=====================================================================
-+=====================================================================*/
-+
-+
-+/* -----------------------------------------------------
-+ *
-+ *	0xFE00h ~ 0xFE55h	USB Configuration
-+ *
-+ * ----------------------------------------------------- */
-+
-+/* 2 Special Option */
-+#define USB_AGG_EN_8814A			BIT(7)
-+#define REG_USB_HRPWM_U3			0xF052
-+
-+#define LAST_ENTRY_OF_TX_PKT_BUFFER_8814A       (2048-1)	/* 20130415 KaiYuan add for 8814 */
-+
-+#endif /* __RTL8814A_SPEC_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8814a_sreset.h b/drivers/staging/rtl8723cs/include/rtl8814a_sreset.h
-new file mode 100644
-index 000000000000..d65cb98a530e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8814a_sreset.h
-@@ -0,0 +1,24 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL88814A_SRESET_H_
-+#define _RTL8814A_SRESET_H_
-+
-+#include <rtw_sreset.h>
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	extern void rtl8814_sreset_xmit_status_check(_adapter *padapter);
-+	extern void rtl8814_sreset_linked_status_check(_adapter *padapter);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8814a_xmit.h b/drivers/staging/rtl8723cs/include/rtl8814a_xmit.h
-new file mode 100644
-index 000000000000..8901fdeab52a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8814a_xmit.h
-@@ -0,0 +1,315 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8814A_XMIT_H__
-+#define __RTL8814A_XMIT_H__
-+
-+typedef struct txdescriptor_8814 {
-+	/* Offset 0 */
-+	u32 pktlen:16;
-+	u32 offset:8;
-+	u32 bmc:1;
-+	u32 htc:1;
-+	u32 ls:1;
-+} TXDESC_8814, *PTXDESC_8814;
-+
-+
-+#define OFFSET_SZ	0
-+#define OFFSET_SHT	16
-+
-+
-+
-+#ifdef CONFIG_SDIO_HCI
-+	#define SET_TX_DESC_SDIO_TXSEQ_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
-+#endif /* CONFIG_SDIO_HCI */
-+
-+/* -----------------------------------------------------------------
-+ *	RTL8814A TX BUFFER DESC
-+ * -----------------------------------------------------------------
-+ *
-+- Each TXBD has 4 segment.
-+ -- For 32 bit, each segment is 8 bytes.
-+ -- For 64 bit, each segment is 16 bytes.
-+*/
-+#if 0
-+	#if 1 /* 32 bit */
-+		#define SET_TX_EXTBUFF_DESC_LEN_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*8), 0, 16, __Value)
-+		#define SET_TX_EXTBUFF_DESC_ADDR_LOW_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*8)+4, 0, 32, __Value)
-+	#else /* 64 bit */
-+		#define SET_TX_EXTBUFF_DESC_LEN_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16), 0, 16, __Value)
-+		#define SET_TX_EXTBUFF_DESC_ADDR_LOW_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16)+4, 0, 32, __Value)
-+	#endif
-+	#define SET_TX_EXTBUFF_DESC_ADDR_HIGH_8814A(__pTxDesc, __Value, __Set) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Set*16)+8, 0, 32, __Value)
-+#endif
-+/*c2h-DWORD 2*/
-+#define GET_RX_STATUS_DESC_RPT_SEL_8814A(__pRxDesc)			LE_BITS_TO_4BYTE(__pRxDesc+8, 28, 1)
-+
-+/* *********************************************************
-+ * for Txfilldescroptor8814Ae, fill the desc content. */
-+#if 1 /* 32 bit */
-+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8), 0, 16, __Valeu)
-+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8), 31, 1, __Valeu)
-+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*8)+4, 0, 32, __Valeu)
-+#else /* 64 bit */
-+	#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
-+	#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
-+	#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
-+#endif
-+#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
-+
-+/* ********************************************************* */
-+
-+/* TX buffer
-+ * *************
-+ * Dword 0 */
-+#define SET_TX_BUFF_DESC_LEN_0_8814A(__pTxDesc, __Valeu)			SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Valeu)
-+#define SET_TX_BUFF_DESC_PSB_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
-+#define SET_TX_BUFF_DESC_OWN_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
-+#define GET_TX_BUFF_DESC_OWN_8814A(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
-+
-+/* Dword 1 */
-+#define SET_TX_BUFF_DESC_ADDR_LOW_0_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
-+#define GET_TX_BUFF_DESC_ADDR_LOW_0_8814A(__pTxDesc)			LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
-+/* Dword 2 */
-+#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value)
-+#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8814A(__pTxDesc)			LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
-+/* Dword 3 */ /* RESERVED 0 */
-+
-+#if 0 /* 64 bit */
-+	/* Dword 4 */
-+	#define SET_TX_BUFF_DESC_LEN_1_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 16, __Value)
-+	#define SET_TX_BUFF_DESC_AMSDU_1_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 31, 1, __Value)
-+	/* Dword 5 */
-+	#define SET_TX_BUFF_DESC_ADDR_LOW_1_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 32, __Value)
-+	/* Dword 6 */
-+	#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 32, __Value)
-+	/* Dword 7 */ /* RESERVED 0 */
-+	/* Dword 8 */
-+	#define SET_TX_BUFF_DESC_LEN_2_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 16, __Value)
-+	#define SET_TX_BUFF_DESC_AMSDU_2_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 31, 1, __Value)
-+	/* Dword 9 */
-+	#define SET_TX_BUFF_DESC_ADDR_LOW_2_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 32, __Value)
-+	/* Dword 10 */
-+	#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
-+	/* Dword 11 */ /* RESERVED 0 */
-+	/* Dword 12 */
-+	#define SET_TX_BUFF_DESC_LEN_3_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 16, __Value)
-+	#define SET_TX_BUFF_DESC_AMSDU_3_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 31, 1, __Value)
-+	/* Dword 13 */
-+	#define SET_TX_BUFF_DESC_ADDR_LOW_3_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+52, 0, 32, __Value)
-+	/* Dword 14 */
-+	#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+56, 0, 32, __Value)
-+	/* Dword 15 */ /* RESERVED 0 */
-+#endif
-+
-+/* *****Desc content
-+ * TX Info
-+ * *************
-+ * Dword 0 */
-+#define SET_TX_DESC_PKT_SIZE_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
-+#define GET_TX_DESC_PKT_SIZE_8814A(__pTxDesc)									LE_BITS_TO_4BYTE(__pTxDesc, 0, 16)
-+#define SET_TX_DESC_OFFSET_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
-+#define GET_TX_DESC_OFFSET_8814A(__pTxDesc)									LE_BITS_TO_4BYTE(__pTxDesc, 16, 8)
-+#define SET_TX_DESC_BMC_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
-+#define SET_TX_DESC_HTC_8814A(__pTxDesc, __Value)								SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
-+#define SET_TX_DESC_LAST_SEG_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
-+#define SET_TX_DESC_LINIP_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
-+#define SET_TX_DESC_AMSDU_PAD_EN_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
-+#define SET_TX_DESC_NO_ACM_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
-+#define SET_TX_DESC_GF_8814A(__pTxDesc, __Value)								SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
-+#define SET_TX_DESC_DISQSELSEQ_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
-+
-+/* Dword 1 */
-+#define SET_TX_DESC_MACID_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
-+#define SET_TX_DESC_QUEUE_SEL_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
-+#define SET_TX_DESC_RDG_NAV_EXT_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
-+#define SET_TX_DESC_LSIG_TXOP_EN_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
-+#define SET_TX_DESC_PIFS_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
-+#define SET_TX_DESC_RATE_ID_8814A(__pTxDesc, __Value)							SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
-+#define SET_TX_DESC_EN_DESC_ID_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
-+#define SET_TX_DESC_SEC_TYPE_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
-+#define SET_TX_DESC_PKT_OFFSET_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
-+#define SET_TX_DESC_MORE_DATA_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
-+#define SET_TX_DESC_TXOP_PS_CAP_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 30, 1, __Value)
-+#define SET_TX_DESC_TXOP_PS_MODE_8814A(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 31, 1, __Value)
-+
-+
-+/* Dword 2 */
-+#define SET_TX_DESC_PAID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
-+#define SET_TX_DESC_CCA_RTS_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
-+#define SET_TX_DESC_AGG_ENABLE_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
-+#define SET_TX_DESC_RDG_ENABLE_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
-+#define SET_TX_DESC_NULL_0_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
-+#define SET_TX_DESC_NULL_1_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
-+#define SET_TX_DESC_BK_8814A(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
-+#define SET_TX_DESC_MORE_FRAG_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
-+#define GET_TX_DESC_MORE_FRAG_8814A(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc+8, 17, 1)
-+#define SET_TX_DESC_RAW_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
-+#define SET_TX_DESC_SPE_RPT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
-+#define SET_TX_DESC_AMPDU_DENSITY_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
-+#define SET_TX_DESC_BT_NULL_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
-+#define SET_TX_DESC_GID_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
-+#define SET_TX_DESC_HW_AES_IV_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 31, 1, __Value)
-+
-+
-+/* Dword 3 */
-+#define SET_TX_DESC_WHEADER_LEN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 5, __Value)
-+#define SET_TX_DESC_EARLY_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
-+#define SET_TX_DESC_HW_SSN_SEL_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
-+#define SET_TX_DESC_USE_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
-+#define SET_TX_DESC_DISABLE_RTS_FB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
-+#define SET_TX_DESC_DISABLE_FB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
-+#define SET_TX_DESC_CTS2SELF_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
-+#define SET_TX_DESC_RTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
-+#define SET_TX_DESC_HW_RTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
-+#define SET_TX_DESC_CHECK_EN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)
-+#define SET_TX_DESC_NAV_USE_HDR_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
-+#define SET_TX_DESC_USE_MAX_LEN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
-+#define SET_TX_DESC_MAX_AGG_NUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
-+#define SET_TX_DESC_NDPA_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
-+#define SET_TX_DESC_AMPDU_MAX_TIME_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
-+
-+/* Dword 4 */
-+#define SET_TX_DESC_TX_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
-+#define SET_TX_DESC_TRY_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
-+#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
-+#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
-+#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
-+#define SET_TX_DESC_DATA_RETRY_LIMIT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
-+#define SET_TX_DESC_RTS_RATE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
-+#define SET_TX_DESC_PCTS_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
-+#define SET_TX_DESC_PCTS_MASK_IDX_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
-+
-+
-+/* Dword 5 */
-+#define SET_TX_DESC_DATA_SC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
-+#define SET_TX_DESC_DATA_SHORT_8814A(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
-+#define SET_TX_DESC_DATA_BW_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
-+#define SET_TX_DESC_DATA_LDPC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
-+#define SET_TX_DESC_DATA_STBC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
-+#define SET_TX_DESC_CTROL_STBC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
-+#define SET_TX_DESC_RTS_SHORT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
-+#define SET_TX_DESC_RTS_SC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
-+#define SET_TX_DESC_SIGNALING_TA_PKT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 17, 1, __Value)
-+#define SET_TX_DESC_PORT_ID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 21, 3, __Value)/* 20130415 KaiYuan add for 8814 */
-+#define SET_TX_DESC_TX_ANT_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value)
-+#define SET_TX_DESC_TX_POWER_OFFSET_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
-+
-+/* Dword 6 */
-+#define SET_TX_DESC_SW_DEFINE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
-+#define SET_TX_DESC_MBSSID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
-+#define SET_TX_DESC_ANTSEL_A_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
-+#define SET_TX_DESC_ANTSEL_B_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
-+#define SET_TX_DESC_ANT_MAPA_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 2, __Value)
-+#define SET_TX_DESC_ANT_MAPB_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 24, 2, __Value)
-+#define SET_TX_DESC_ANT_MAPC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 26, 2, __Value)
-+#define SET_TX_DESC_ANT_MAPD_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 28, 2, __Value)
-+
-+
-+/* Dword 7 */
-+#ifdef CONFIG_PCI_HCI
-+	#define SET_TX_DESC_TX_BUFFER_SIZE_8814A(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+#endif
-+#if defined(CONFIG_SDIO_HCI)|| defined(CONFIG_USB_HCI)
-+	#define SET_TX_DESC_TX_DESC_CHECKSUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
-+#endif
-+#define SET_TX_DESC_NTX_MAP_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 20, 4, __Value)
-+#define SET_TX_DESC_USB_TXAGG_NUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
-+
-+
-+/* Dword 8 */
-+#define SET_TX_DESC_RTS_RC_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
-+#define SET_TX_DESC_BAR_RTY_TH_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
-+#define SET_TX_DESC_DATA_RC_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
-+#define SET_TX_DESC_EN_HWEXSEQ_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 14, 1, __Value)
-+#define SET_TX_DESC_HWSEQ_EN_8814A(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
-+#if defined(CONFIG_PCI_HCI)|| defined(CONFIG_USB_HCI)
-+	#define SET_TX_DESC_NEXT_HEAD_PAGE_L_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
-+#endif
-+#ifdef CONFIG_SDIO_HCI
-+	#define SET_TX_DESC_SDIO_SEQ_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) 			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) /* 20130415 KaiYuan add for 8814AS */
-+#endif
-+#define SET_TX_DESC_TAIL_PAGE_L_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
-+
-+/* Dword 9 */
-+#define SET_TX_DESC_PADDING_LENGTH_8814A(__pTxDesc, __Value)						SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
-+#define SET_TX_DESC_TXBF_PATH_8814A(__pTxDesc, __Value)								SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 11, 1, __Value)
-+#define SET_TX_DESC_SEQ_8814A(__pTxDesc, __Value)										SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
-+#define SET_TX_DESC_NEXT_HEAD_PAGE_H_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 4, __Value)
-+#define SET_TX_DESC_TAIL_PAGE_H_8814A(__pTxDesc, __Value)(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 28, 4, __Value)
-+
-+
-+
-+#define SET_EARLYMODE_PKTNUM_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
-+#define SET_EARLYMODE_LEN0_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
-+#define SET_EARLYMODE_LEN1_1_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
-+#define SET_EARLYMODE_LEN1_2_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
-+#define SET_EARLYMODE_LEN2_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,  __Value)
-+#define SET_EARLYMODE_LEN3_8814A(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
-+
-+
-+void rtl8814a_cal_txdesc_chksum(u8 *ptxdesc);
-+void rtl8814a_fill_fake_txdesc(PADAPTER	padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8	IsBTQosNull, u8 bDataFrame);
-+void rtl8814a_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void rtl8814a_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void rtl8814a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
-+
-+#ifdef CONFIG_USB_HCI
-+	s32 rtl8814au_init_xmit_priv(PADAPTER padapter);
-+	void rtl8814au_free_xmit_priv(PADAPTER padapter);
-+	s32 rtl8814au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8814au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8814au_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	 rtl8814au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8814au_xmit_buf_handler(PADAPTER padapter);
-+	void rtl8814au_xmit_tasklet(void *priv);
-+	s32 rtl8814au_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+#endif /* CONFIG_USB_HCI */
-+
-+#ifdef CONFIG_PCI_HCI
-+	s32 rtl8814ae_init_xmit_priv(PADAPTER padapter);
-+	void rtl8814ae_free_xmit_priv(PADAPTER padapter);
-+	struct xmit_buf *rtl8814ae_dequeue_xmitbuf(struct rtw_tx_ring *ring);
-+	void rtl8814ae_xmitframe_resume(_adapter *padapter);
-+	s32 rtl8814ae_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+	s32 rtl8814ae_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	s32 rtl8814ae_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+	s32	rtl8814ae_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+	void rtl8814ae_xmit_tasklet(void *priv);
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+	s32 rtl8814ae_xmit_buf_handler(_adapter *padapter);
-+#endif
-+#endif
-+
-+void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, u8 *ptxdesc);
-+u8
-+SCMapping_8814(
-+		PADAPTER		Adapter,
-+		struct pkt_attrib	*pattrib
-+);
-+
-+u8
-+BWMapping_8814(
-+		PADAPTER		Adapter,
-+		struct pkt_attrib	*pattrib
-+);
-+
-+
-+#endif /* __RTL8814_XMIT_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8814b_hal.h b/drivers/staging/rtl8723cs/include/rtl8814b_hal.h
-new file mode 100644
-index 000000000000..301d1a054166
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8814b_hal.h
-@@ -0,0 +1,239 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8814B_HAL_H_
-+#define _RTL8814B_HAL_H_
-+
-+#include <osdep_service.h>		/* BIT(x) */
-+#include <drv_types.h>			/* PADAPTER */
-+#include "../hal/halmac/halmac_api.h"	/* MAC REG definition */
-+
-+
-+#ifdef CONFIG_SUPPORT_TRX_SHARED
-+#define MAX_RECVBUF_SZ		46080	/* 45KB, TX: (256-64)KB */
-+#else /* !CONFIG_SUPPORT_TRX_SHARED */
-+#define MAX_RECVBUF_SZ		24576	/* 24KB, TX: 256KB */
-+#endif /* !CONFIG_SUPPORT_TRX_SHARED */
-+
-+#if 0
-+/*
-+ * MAC Register definition
-+ */
-+#define REG_AFE_XTAL_CTRL	REG_AFE_CTRL1_8814B	/* hal_com.c & phydm */
-+#define REG_AFE_PLL_CTRL	REG_AFE_CTRL2_8814B	/* hal_com.c & phydm */
-+#define REG_MAC_PHY_CTRL	REG_AFE_CTRL3_8814B	/* phydm only */
-+#endif
-+#define REG_LEDCFG0		REG_LED_CFG_8814B	/* rtw_mp.c */
-+#if 0
-+#define MSR			(REG_CR_8814B + 2)	/* rtw_mp.c & hal_com.c */
-+#define MSR1			REG_CR_EXT_8814B	/* rtw_mp.c & hal_com.c */
-+#endif
-+#define REG_C2HEVT_MSG_NORMAL	0x1A0			/* hal_com.c */
-+#if 0
-+#define REG_C2HEVT_CLEAR	0x1AF			/* hal_com.c */
-+
-+#define REG_GPIO_PIN_CTRL_2		REG_GPIO_EXT_CTRL_8814B		/* hal_com.c */
-+#endif
-+#define REG_WKFMCAM_NUM		REG_WKFMCAM_CMD_8814B	/* hal_com.c: WOWLAN */
-+#define REG_WOWLAN_WAKE_REASON	0x01C7 /* hal_com.c: WOWLAN */
-+#define REG_RXPKTBUF_CTRL	(REG_PKTBUF_DBG_CTRL_8814B + 2)	/* hal_com.c: WOWLAN */
-+#define REG_RXPKT_NUM		REG_RXDMA_CTRL_8814B	/* hal_com.c: WOWLAN */
-+
-+/* RXERR_RPT, for rtw_mp.c */
-+#define RXERR_TYPE_OFDM_PPDU		0
-+#define RXERR_TYPE_OFDM_FALSE_ALARM	2
-+#define RXERR_TYPE_OFDM_MPDU_OK		0
-+#define RXERR_TYPE_OFDM_MPDU_FAIL	1
-+#define RXERR_TYPE_CCK_PPDU		3
-+#define RXERR_TYPE_CCK_FALSE_ALARM	5
-+#define RXERR_TYPE_CCK_MPDU_OK		3
-+#define RXERR_TYPE_CCK_MPDU_FAIL	4
-+#define RXERR_TYPE_HT_PPDU		8
-+#define RXERR_TYPE_HT_FALSE_ALARM	9
-+#define RXERR_TYPE_HT_MPDU_TOTAL	6
-+#define RXERR_TYPE_HT_MPDU_OK		6
-+#define RXERR_TYPE_HT_MPDU_FAIL		7
-+#define RXERR_TYPE_RX_FULL_DROP		10
-+
-+#define RXERR_COUNTER_MASK		BIT_MASK_RPT_COUNTER_8814B
-+#define RXERR_RPT_RST			BIT_RXERR_RPT_RST_8814B
-+#define _RXERR_RPT_SEL(type)		(BIT_RXERR_RPT_SEL_V1_3_0_8814B(type) \
-+					| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8814B : 0))
-+
-+/* hal_com.c:rtw_lps_state_chk() */
-+#define BIT_PWRBIT_OW_EN		BIT_WMAC_TCRPWRMGT_HWDATA_EN_8814B
-+
-+/*
-+ * BB Register definition
-+ */
-+#define rPMAC_Reset			0x100	/* hal_mp.c */
-+
-+#define	rFPGA0_RFMOD			0x800
-+#define rFPGA0_TxInfo			0x804
-+#define rOFDMCCKEN_Jaguar		0x808	/* hal_mp.c */
-+#define rFPGA0_TxGainStage		0x80C	/* phydm only */
-+#define rFPGA0_XA_HSSIParameter1	0x820	/* hal_mp.c */
-+#define rFPGA0_XA_HSSIParameter2	0x824	/* hal_mp.c */
-+#define rFPGA0_XB_HSSIParameter1	0x828	/* hal_mp.c */
-+#define rFPGA0_XB_HSSIParameter2	0x82C	/* hal_mp.c */
-+#define rTxAGC_B_Rate18_06		0x830
-+#define rTxAGC_B_Rate54_24		0x834
-+#define rTxAGC_B_CCK1_55_Mcs32		0x838
-+#define rCCAonSec_Jaguar		0x838	/* hal_mp.c */
-+#define rTxAGC_B_Mcs03_Mcs00		0x83C
-+#define rTxAGC_B_Mcs07_Mcs04		0x848
-+#define rTxAGC_B_Mcs11_Mcs08		0x84C
-+#define rFPGA0_XA_RFInterfaceOE		0x860
-+#define rFPGA0_XB_RFInterfaceOE		0x864
-+#define rTxAGC_B_Mcs15_Mcs12		0x868
-+#define rTxAGC_B_CCK11_A_CCK2_11	0x86C
-+#define rFPGA0_XAB_RFInterfaceSW	0x870
-+#define rFPGA0_XAB_RFParameter		0x878
-+#define rFPGA0_AnalogParameter4		0x88C	/* hal_mp.c & phydm */
-+#define rFPGA0_XB_LSSIReadBack		0x8A4	/* phydm */
-+#define rHSSIRead_Jaguar		0x8B0	/* RF read addr (rtl8814b_phy.c) */
-+
-+#define	rC_TxScale_Jaguar2		0x181C  /* Pah_C TX scaling factor (hal_mp.c) */
-+#define	rC_IGI_Jaguar2			0x1850	/* Initial Gain for path-C (hal_mp.c) */
-+
-+#define rFPGA1_TxInfo			0x90C	/* hal_mp.c */
-+#define rSingleTone_ContTx_Jaguar	0x914	/* hal_mp.c */
-+/* TX BeamForming */
-+#define REG_BB_TX_PATH_SEL_1_8814B	0x93C	/* rtl8814b_phy.c */
-+#define REG_BB_TX_PATH_SEL_2_8814B	0x940	/* rtl8814b_phy.c */
-+
-+/* TX BeamForming */
-+#define REG_BB_TXBF_ANT_SET_BF1_8814B	0x19AC	/* rtl8814b_phy.c */
-+#define REG_BB_TXBF_ANT_SET_BF0_8814B	0x19B4	/* rtl8814b_phy.c */
-+
-+#define rCCK0_System			0xA00
-+#define rCCK0_AFESetting		0xA04
-+
-+#define rCCK0_DSPParameter2		0xA1C
-+#define rCCK0_TxFilter1			0xA20
-+#define rCCK0_TxFilter2			0xA24
-+#define rCCK0_DebugPort			0xA28
-+#define rCCK0_FalseAlarmReport		0xA2C
-+
-+#define	rD_TxScale_Jaguar2		0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */
-+#define	rD_IGI_Jaguar2			0x1A50	/* Initial Gain for path-D (hal_mp.c) */
-+
-+#define rOFDM0_TRxPathEnable		0xC04
-+#define rOFDM0_TRMuxPar			0xC08
-+#define rA_TxScale_Jaguar		0xC1C	/* Pah_A TX scaling factor (hal_mp.c) */
-+#define rOFDM0_RxDetector1		0xC30	/* rtw_mp.c */
-+#define rOFDM0_ECCAThreshold		0xC4C	/* phydm only */
-+#define rOFDM0_XAAGCCore1		0xC50	/* phydm only */
-+#define rA_IGI_Jaguar			0xC50	/* Initial Gain for path-A (hal_mp.c) */
-+#define rOFDM0_XBAGCCore1		0xC58	/* phydm only */
-+#define rOFDM0_XATxIQImbalance		0xC80	/* phydm only */
-+#define rA_LSSIWrite_Jaguar		0xC90	/* RF write addr, LSSI Parameter (rtl8814b_phy.c) */
-+
-+#define rOFDM1_LSTF			0xD00
-+#define rOFDM1_TRxPathEnable		0xD04	/* hal_mp.c */
-+#define rA_PIRead_Jaguar		0xD04	/* RF readback with PI (rtl8814b_phy.c) */
-+#define rA_SIRead_Jaguar		0xD08	/* RF readback with SI (rtl8814b_phy.c) */
-+#define rB_PIRead_Jaguar		0xD44	/* RF readback with PI (rtl8814b_phy.c) */
-+#define rB_SIRead_Jaguar		0xD48	/* RF readback with SI (rtl8814b_phy.c) */
-+
-+#define rTxAGC_A_Rate18_06		0xE00
-+#define rTxAGC_A_Rate54_24		0xE04
-+#define rTxAGC_A_CCK1_Mcs32		0xE08
-+#define rTxAGC_A_Mcs03_Mcs00		0xE10
-+#define rTxAGC_A_Mcs07_Mcs04		0xE14
-+#define rTxAGC_A_Mcs11_Mcs08		0xE18
-+#define rTxAGC_A_Mcs15_Mcs12		0xE1C
-+#define rB_TxScale_Jaguar		0xE1C	/* Path_B TX scaling factor (hal_mp.c) */
-+#define rB_IGI_Jaguar			0xE50	/* Initial Gain for path-B (hal_mp.c) */
-+#define rB_LSSIWrite_Jaguar		0xE90	/* RF write addr, LSSI Parameter (rtl8814b_phy.c) */
-+/* RFE */
-+#define rA_RFE_Pinmux_Jaguar	0xCB0	/* hal_mp.c */
-+#define	rB_RFE_Pinmux_Jaguar	0xEB0	/* Path_B RFE control pinmux */
-+#define	rA_RFE_Inv_Jaguar		0xCB4	/* Path_A RFE cotrol */  
-+#define	rB_RFE_Inv_Jaguar		0xEB4	/* Path_B RFE control */
-+#define	rA_RFE_Jaguar			0xCB8 	/* Path_A RFE cotrol */  
-+#define	rB_RFE_Jaguar			0xEB8	/* Path_B RFE control */
-+#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
-+#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
-+#define	r_ANTSEL_SW_Jaguar		0x900	/* ANTSEL SW Control */
-+#define	bMask_RFEInv_Jaguar	0x3FF00000
-+#define	bMask_AntselPathFollow_Jaguar 0x00030000
-+
-+#define		rC_RFE_Pinmux_Jaguar	0x18B4	/* Path_C RFE cotrol pinmux*/
-+#define		rD_RFE_Pinmux_Jaguar	0x1AB4	/* Path_D RFE cotrol pinmux*/
-+#define		rA_RFE_Sel_Jaguar2		0x1990
-+
-+/* Page1(0x100) */
-+#define bBBResetB			0x100
-+
-+/* Page8(0x800) */
-+#define bCCKEn				0x1000000
-+#define bOFDMEn				0x2000000
-+/* Reg 0x80C rFPGA0_TxGainStage */
-+#define bXBTxAGC			0xF00
-+#define bXCTxAGC			0xF000
-+#define bXDTxAGC			0xF0000
-+
-+/* PageA(0xA00) */
-+#define bCCKBBMode			0x3
-+
-+#define bCCKScramble			0x8
-+#define bCCKTxRate			0x3000
-+
-+/* General */
-+#define bMaskByte0		0xFF		/* mp, rtw_odm.c & phydm */
-+#define bMaskByte1		0xFF00		/* hal_mp.c & phydm */
-+#define bMaskByte2		0xFF0000	/* hal_mp.c & phydm */
-+#define bMaskByte3		0xFF000000	/* hal_mp.c & phydm */
-+#define bMaskHWord		0xFFFF0000	/* hal_com.c, rtw_mp.c */
-+#define bMaskLWord		0x0000FFFF	/* mp, hal_com.c & phydm */
-+#define bMaskDWord		0xFFFFFFFF	/* mp, hal, rtw_odm.c & phydm */
-+
-+#define bEnable			0x1		/* hal_mp.c, rtw_mp.c */
-+#define bDisable		0x0		/* rtw_mp.c */
-+
-+#define MAX_STALL_TIME		50		/* unit: us, hal_com_phycfg.c */
-+
-+#define Rx_Smooth_Factor	20		/* phydm only */
-+
-+/*
-+ * RF Register definition
-+ */
-+#define RF_AC			0x00
-+#define RF_AC_Jaguar		0x00	/* hal_mp.c */
-+#define RF_CHNLBW		0x18	/* rtl8814b_phy.c */
-+#define RF_ModeTableAddr	0x30	/* rtl8814b_phy.c */
-+#define RF_ModeTableData0	0x31	/* rtl8814b_phy.c */
-+#define RF_ModeTableData1	0x32	/* rtl8814b_phy.c */
-+#define RF_0x52			0x52
-+#define RF_WeLut_Jaguar		0xEF	/* rtl8814b_phy.c */
-+
-+/* General Functions */
-+void rtl8814b_init_hal_spec(PADAPTER);				/* hal/hal_com.c */
-+
-+#ifdef CONFIG_MP_INCLUDED
-+/* MP Functions */
-+#include <rtw_mp.h>		/* struct mp_priv */
-+void rtl8814b_prepare_mp_txdesc(PADAPTER, struct mp_priv *);	/* rtw_mp.c */
-+void rtl8814b_mp_config_rfpath(PADAPTER);			/* hal_mp.c */
-+#endif
-+void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
-+
-+#ifdef CONFIG_USB_HCI
-+#include <rtl8814bu_hal.h>
-+#elif defined(CONFIG_PCI_HCI)
-+#include <rtl8814be_hal.h>
-+#endif
-+
-+#endif /* _RTL8814B_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8814be_hal.h b/drivers/staging/rtl8723cs/include/rtl8814be_hal.h
-new file mode 100644
-index 000000000000..3e124cae69de
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8814be_hal.h
-@@ -0,0 +1,30 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8814BE_HAL_H_
-+#define _RTL8814BE_HAL_H_
-+
-+#include <drv_types.h>		/* PADAPTER */
-+
-+#define RT_BCN_INT_MASKS	(BIT_BCNDMAINT0_MSK_8814B |	\
-+				 BIT_TXBCN0OK_MSK_8814B |	\
-+				 BIT_TXBCN0ERR_MSK_8814B |	\
-+				 BIT_BCNDERR0_MSK_8814B)
-+
-+/* rtl8814be_ops.c */
-+void UpdateInterruptMask8814BE(PADAPTER, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
-+u16 get_txbd_rw_reg(u16 q_idx);
-+
-+
-+#endif /* _RTL8814BE_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8814bu_hal.h b/drivers/staging/rtl8723cs/include/rtl8814bu_hal.h
-new file mode 100644
-index 000000000000..aa5cef998014
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8814bu_hal.h
-@@ -0,0 +1,61 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8814BU_HAL_H_
-+#define _RTL8814BU_HAL_H_
-+
-+#ifdef CONFIG_USB_HCI
-+	#include <drv_types.h>		/* PADAPTER */
-+
-+	#ifdef CONFIG_USB_HCI
-+		#ifdef USB_PACKET_OFFSET_SZ
-+			#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)
-+		#else
-+			#define PACKET_OFFSET_SZ (8)
-+		#endif
-+		#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
-+	#endif
-+
-+	/* undefine MAX_RECVBUF_SZ from rtl8822c_hal.h  */
-+	#ifdef MAX_RECVBUF_SZ
-+		#undef MAX_RECVBUF_SZ
-+	#endif
-+
-+	/* recv_buffer must be large than usb agg size */
-+	#ifndef MAX_RECVBUF_SZ
-+		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
-+			#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
-+				#define MAX_RECVBUF_SZ (15360) /* 15k */
-+				#elif defined(CONFIG_PLATFORM_HISILICON)
-+				/* use 16k to workaround for HISILICON platform */
-+				#define MAX_RECVBUF_SZ (16384)
-+			#else
-+				#define MAX_RECVBUF_SZ (32768)
-+			#endif
-+		#else
-+			#define MAX_RECVBUF_SZ (4000)
-+		#endif
-+	#endif /* !MAX_RECVBUF_SZ */
-+
-+	/* rtl8814bu_ops.c */
-+	void rtl8814bu_set_hal_ops(PADAPTER padapter);
-+	void rtl8814bu_set_hw_type(struct dvobj_priv *pdvobj);
-+
-+	/* rtl8814bu_io.c */
-+	void rtl8814bu_set_intf_ops(struct _io_ops *pops);
-+
-+#endif /* CONFIG_USB_HCI */
-+
-+
-+#endif /* _RTL8814BU_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8821a_spec.h b/drivers/staging/rtl8723cs/include/rtl8821a_spec.h
-new file mode 100644
-index 000000000000..1379ffc3cf9d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8821a_spec.h
-@@ -0,0 +1,90 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8821A_SPEC_H__
-+#define __RTL8821A_SPEC_H__
-+
-+#include <drv_conf.h>
-+/* This file should based on "hal_com_reg.h" */
-+#include <hal_com_reg.h>
-+/* Because 8812a and 8821a is the same serial,
-+ * most of 8821a register definitions are the same as 8812a. */
-+#include <rtl8812a_spec.h>
-+
-+
-+/* ************************************************************
-+ * 8821A Regsiter offset definition
-+ * ************************************************************ */
-+
-+/* ************************************************************
-+ * MAC register
-+ * ************************************************************ */
-+
-+/* -----------------------------------------------------
-+ *	0x0000h ~ 0x00FFh	System Configuration
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *	0x0100h ~ 0x01FFh	MACTOP General Configuration
-+ * ----------------------------------------------------- */
-+#define REG_WOWLAN_WAKE_REASON          REG_MCUTST_WOWLAN
-+
-+/* -----------------------------------------------------
-+ *	0x0200h ~ 0x027Fh	TXDMA Configuration
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *	0x0280h ~ 0x02FFh	RXDMA Configuration
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *	0x0300h ~ 0x03FFh	PCIe
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *	0x0400h ~ 0x047Fh	Protocol Configuration
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *	0x0500h ~ 0x05FFh	EDCA Configuration
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ *	0x0600h ~ 0x07FFh	WMAC Configuration
-+ * ----------------------------------------------------- */
-+
-+
-+/* ************************************************************
-+ * SDIO Bus Specification
-+ * ************************************************************ */
-+
-+/* -----------------------------------------------------
-+ * SDIO CMD Address Mapping
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ * I/O bus domain (Host)
-+ * ----------------------------------------------------- */
-+
-+/* -----------------------------------------------------
-+ * SDIO register
-+ * ----------------------------------------------------- */
-+#define SDIO_REG_FREE_TXPG2		0x024
-+#define SDIO_REG_HCPWM1_8821A	0x025
-+
-+/* ************************************************************
-+ * Regsiter Bit and Content definition
-+ * ************************************************************ */
-+
-+#endif /* __RTL8821A_SPEC_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8821a_xmit.h b/drivers/staging/rtl8723cs/include/rtl8821a_xmit.h
-new file mode 100644
-index 000000000000..28323b79cd79
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8821a_xmit.h
-@@ -0,0 +1,176 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8821A_XMIT_H__
-+#define __RTL8821A_XMIT_H__
-+
-+#include <drv_types.h>
-+
-+typedef struct txdescriptor_8821a {
-+	/* Offset 0 */
-+	u32 pktlen:16;
-+	u32 offset:8;
-+	u32 bmc:1;
-+	u32 htc:1;
-+	u32 rsvd0026:1;
-+	u32 rsvd0027:1;
-+	u32 linip:1;
-+	u32 noacm:1;
-+	u32 gf:1;
-+	u32 rsvd0031:1;
-+
-+	/* Offset 4 */
-+	u32 macid:7;
-+	u32 rsvd0407:1;
-+	u32 qsel:5;
-+	u32 rdg_nav_ext:1;
-+	u32 lsig_txop_en:1;
-+	u32 pifs:1;
-+	u32 rate_id:5;
-+	u32 en_desc_id:1;
-+	u32 sectype:2;
-+	u32 pkt_offset:5; /* unit: 8 bytes */
-+	u32 moredata:1;
-+	u32 txop_ps_cap:1;
-+	u32 txop_ps_mode:1;
-+
-+	/* Offset 8 */
-+	u32 p_aid:9;
-+	u32 rsvd0809:1;
-+	u32 cca_rts:2;
-+	u32 agg_en:1;
-+	u32 rdg_en:1;
-+	u32 null_0:1;
-+	u32 null_1:1;
-+	u32 bk:1;
-+	u32 morefrag:1;
-+	u32 raw:1;
-+	u32 spe_rpt:1;
-+	u32 ampdu_density:3;
-+	u32 bt_null:1;
-+	u32 g_id:6;
-+	u32 rsvd0830:2;
-+
-+	/* Offset 12 */
-+	u32 wheader_len:4;
-+	u32 chk_en:1;
-+	u32 early_rate:1;
-+	u32 hw_ssn_sel:2;
-+	u32 userate:1;
-+	u32 disrtsfb:1;
-+	u32 disdatafb:1;
-+	u32 cts2self:1;
-+	u32 rtsen:1;
-+	u32 hw_rts_en:1;
-+	u32 port_id:1;
-+	u32 navusehdr:1;
-+	u32 use_max_len:1;
-+	u32 max_agg_num:5;
-+	u32 ndpa:2;
-+	u32 ampdu_max_time:8;
-+
-+	/* Offset 16 */
-+	u32 datarate:7;
-+	u32 try_rate:1;
-+	u32 data_ratefb_lmt:5;
-+	u32 rts_ratefb_lmt:4;
-+	u32 rty_lmt_en:1;
-+	u32 data_rt_lmt:6;
-+	u32 rtsrate:5;
-+	u32 pcts_en:1;
-+	u32 pcts_mask_idx:2;
-+
-+	/* Offset 20 */
-+	u32 data_sc:4;
-+	u32 data_short:1;
-+	u32 data_bw:2;
-+	u32 data_ldpc:1;
-+	u32 data_stbc:2;
-+	u32 vcs_stbc:2;
-+	u32 rts_short:1;
-+	u32 rts_sc:4;
-+	u32 rsvd2016:7;
-+	u32 tx_ant:4;
-+	u32 txpwr_offset:3;
-+	u32 rsvd2031:1;
-+
-+	/* Offset 24 */
-+	u32 sw_define:12;
-+	u32 mbssid:4;
-+	u32 antsel_A:3;
-+	u32 antsel_B:3;
-+	u32 antsel_C:3;
-+	u32 antsel_D:3;
-+	u32 rsvd2428:4;
-+
-+	/* Offset 28 */
-+	u32 checksum:16;
-+	u32 rsvd2816:8;
-+	u32 usb_txagg_num:8;
-+
-+	/* Offset 32 */
-+	u32 rts_rc:6;
-+	u32 bar_rty_th:2;
-+	u32 data_rc:6;
-+	u32 rsvd3214:1;
-+	u32 en_hwseq:1;
-+	u32 nextneadpage:8;
-+	u32 tailpage:8;
-+
-+	/* Offset 36 */
-+	u32 padding_len:11;
-+	u32 txbf_path:1;
-+	u32 seq:12;
-+	u32 final_data_rate:8;
-+} TXDESC_8821A, *PTXDESC_8821A;
-+
-+#ifdef CONFIG_SDIO_HCI
-+s32 InitXmitPriv8821AS(PADAPTER padapter);
-+void FreeXmitPriv8821AS(PADAPTER padapter);
-+s32 XmitBufHandler8821AS(PADAPTER padapter);
-+s32 MgntXmit8821AS(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+#ifdef CONFIG_RTW_MGMT_QUEUE 
-+s32 rtl8821as_hal_mgmt_xmit_enqueue(PADAPTER adapter, struct xmit_frame *pxmitframe);
-+#endif
-+s32	HalXmitNoLock8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+s32 HalXmit8821AS(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+#ifndef CONFIG_SDIO_TX_TASKLET
-+thread_return XmitThread8821AS(thread_context context);
-+#endif /* !CONFIG_SDIO_TX_TASKLET */
-+#endif /* CONFIG_SDIO_HCI */
-+
-+#if 0
-+#ifdef CONFIG_USB_HCI
-+s32 rtl8821au_init_xmit_priv(PADAPTER padapter);
-+void rtl8821au_free_xmit_priv(PADAPTER padapter);
-+s32 rtl8821au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+s32 rtl8821au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+s32 rtl8821au_hal_xmitframe_enqueue(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+s32 rtl8821au_xmit_buf_handler(PADAPTER padapter);
-+void rtl8821au_xmit_tasklet(void *priv);
-+s32 rtl8821au_xmitframe_complete(PADAPTER padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+#endif /* CONFIG_USB_HCI */
-+
-+#ifdef CONFIG_PCI_HCI
-+s32 rtl8821e_init_xmit_priv(PADAPTER padapter);
-+void rtl8821e_free_xmit_priv(PADAPTER padapter);
-+struct xmit_buf *rtl8821e_dequeue_xmitbuf(struct rtw_tx_ring *ring);
-+void rtl8821e_xmitframe_resume(PADAPTER padapter);
-+s32 rtl8821e_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
-+s32 rtl8821e_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
-+void rtl8821e_xmit_tasklet(void *priv);
-+#endif /* CONFIG_PCI_HCI */
-+#endif
-+
-+#endif /* __RTL8821_XMIT_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8821c_dm.h b/drivers/staging/rtl8723cs/include/rtl8821c_dm.h
-new file mode 100644
-index 000000000000..b1e4fe608b2a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8821c_dm.h
-@@ -0,0 +1,23 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8812C_DM_H__
-+#define __RTL8812C_DM_H__
-+
-+void rtl8821c_phy_init_dm_priv(PADAPTER);
-+void rtl8821c_phy_deinit_dm_priv(PADAPTER);
-+void rtl8821c_phy_init_haldm(PADAPTER);
-+void rtl8821c_phy_haldm_watchdog(PADAPTER);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtl8821c_hal.h b/drivers/staging/rtl8723cs/include/rtl8821c_hal.h
-new file mode 100644
-index 000000000000..41d222ef34d9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8821c_hal.h
-@@ -0,0 +1,84 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8821C_HAL_H_
-+#define _RTL8821C_HAL_H_
-+
-+#include <osdep_service.h>		/* BIT(x) */
-+#include "../hal/halmac/halmac_api.h"	/* MAC REG definition */
-+#include "hal_data.h"
-+#include "rtl8821c_spec.h"
-+#include "../hal/rtl8821c/hal8821c_fw.h"
-+
-+#ifdef CONFIG_USB_HCI
-+#include <rtl8821cu_hal.h>
-+#endif
-+#ifdef CONFIG_SDIO_HCI
-+#include <rtl8821cs_hal.h>
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+#include <rtl8821ce_hal.h>
-+#endif
-+
-+#ifdef CONFIG_SUPPORT_TRX_SHARED
-+#define FIFO_BLOCK_SIZE		32768 /*@Block size = 32K*/
-+#define RX_FIFO_EXPANDING	(1 * FIFO_BLOCK_SIZE)
-+#else
-+#define RX_FIFO_EXPANDING	0
-+#endif
-+
-+
-+#if defined(CONFIG_USB_HCI)
-+
-+	#ifndef MAX_RECVBUF_SZ
-+		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
-+			/* 8821C - RX FIFO :16K ,for RX agg DMA mode = 16K, Rx agg USB mode could large than 16k*/
-+			/* #define MAX_RECVBUF_SZ		(16384 + RX_FIFO_EXPANDING)*/
-+			/* For Max throughput issue , need to use USB AGG mode to replace DMA AGG mode*/
-+			#define MAX_RECVBUF_SZ (32768)
-+
-+			/*#define MAX_RECVBUF_SZ_8821C (24576)*/ /* 24k*/
-+			/*#define MAX_RECVBUF_SZ_8821C (20480)*/ /*20K*/
-+			/*#define MAX_RECVBUF_SZ_8821C (10240) */ /*10K*/
-+			/*#define MAX_RECVBUF_SZ_8821C (15360)*/ /*15k < 16k*/
-+			/*#define MAX_RECVBUF_SZ_8821C (8192+1024)*/ /* 8K+1k*/
-+		#else
-+			#define MAX_RECVBUF_SZ (4096 + RX_FIFO_EXPANDING) /* about 4K */
-+		#endif
-+	#endif/* !MAX_RECVBUF_SZ*/
-+
-+#elif defined(CONFIG_PCI_HCI)
-+	/*#ifndef CONFIG_MINIMAL_MEMORY_USAGE
-+	#define MAX_RECVBUF_SZ (9100)
-+	#else*/
-+	#define MAX_RECVBUF_SZ (4096 + RX_FIFO_EXPANDING) /* about 4K */
-+	/*#endif*/
-+
-+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	#define MAX_RECVBUF_SZ	(16384 + RX_FIFO_EXPANDING)
-+#endif
-+
-+void init_hal_spec_rtl8821c(PADAPTER);
-+/* MP Functions */
-+#ifdef CONFIG_MP_INCLUDED
-+void rtl8821c_prepare_mp_txdesc(PADAPTER, struct mp_priv *);	/* rtw_mp.c */
-+void rtl8821c_mp_config_rfpath(PADAPTER);			/* hal_mp.c */
-+#endif
-+void rtl8821c_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
-+
-+#ifdef CONFIG_PCI_HCI
-+u16 get_txbd_rw_reg(u16 q_idx);
-+#endif
-+
-+#endif /* _RTL8821C_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8821c_spec.h b/drivers/staging/rtl8723cs/include/rtl8821c_spec.h
-new file mode 100644
-index 000000000000..949f349b66e9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8821c_spec.h
-@@ -0,0 +1,202 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTL8821C_SPEC_H__
-+#define __RTL8821C_SPEC_H__
-+
-+#define EFUSE_MAP_SIZE		HALMAC_EFUSE_SIZE_8821C
-+
-+/*
-+ * MAC Register definition
-+ */
-+#define REG_AFE_XTAL_CTRL			REG_AFE_CTRL1_8821C	/* hal_com.c & phydm */
-+#define REG_AFE_PLL_CTRL			REG_AFE_CTRL2_8821C	/* hal_com.c & phydm */
-+#define REG_MAC_PHY_CTRL			REG_AFE_CTRL3_8821C	/* phydm only */
-+#define REG_LEDCFG0					REG_LED_CFG_8821C	/* rtw_mp.c */
-+#define MSR							(REG_CR_8821C + 2)	/* rtw_mp.c */
-+#define MSR1						REG_CR_EXT_8821C	/* rtw_mp.c & hal_com.c */
-+#define REG_C2HEVT_MSG_NORMAL		0x1A0			/* hal_com.c */
-+#define REG_C2HEVT_CLEAR			0x1AF			/* hal_com.c */
-+#define REG_BCN_CTRL_1				REG_BCN_CTRL_CLINT0_8821C/* hal_com.c */
-+
-+#define REG_WOWLAN_WAKE_REASON	0x01C7
-+#define REG_GPIO_PIN_CTRL_2			REG_GPIO_EXT_CTRL_8821C
-+
-+/* RXERR_RPT, for rtw_mp.c */
-+#define RXERR_TYPE_OFDM_PPDU		0
-+#define RXERR_TYPE_OFDM_FALSE_ALARM	2
-+#define RXERR_TYPE_OFDM_MPDU_OK		0
-+#define RXERR_TYPE_OFDM_MPDU_FAIL	1
-+#define RXERR_TYPE_CCK_PPDU		3
-+#define RXERR_TYPE_CCK_FALSE_ALARM	5
-+#define RXERR_TYPE_CCK_MPDU_OK		3
-+#define RXERR_TYPE_CCK_MPDU_FAIL	4
-+#define RXERR_TYPE_HT_PPDU		8
-+#define RXERR_TYPE_HT_FALSE_ALARM	9
-+#define RXERR_TYPE_HT_MPDU_TOTAL	6
-+#define RXERR_TYPE_HT_MPDU_OK		6
-+#define RXERR_TYPE_HT_MPDU_FAIL		7
-+#define RXERR_TYPE_RX_FULL_DROP		10
-+
-+#define RXERR_COUNTER_MASK		BIT_MASK_RPT_COUNTER_8821C
-+#define RXERR_RPT_RST			BIT_RXERR_RPT_RST_8821C
-+#define _RXERR_RPT_SEL(type)		(BIT_RXERR_RPT_SEL_V1_3_0_8821C(type) \
-+		| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8821C : 0))
-+
-+/*
-+ * BB Register definition
-+ */
-+#define rPMAC_Reset				0x100	/* hal_mp.c */
-+
-+#define rFPGA0_RFMOD				0x800
-+#define rFPGA0_TxInfo				0x804
-+#define rOFDMCCKEN_Jaguar		0x808	/* hal_mp.c */
-+#define rFPGA0_TxGainStage		0x80C	/* phydm only */
-+#define rFPGA0_XA_HSSIParameter1	0x820	/* hal_mp.c */
-+#define rFPGA0_XA_HSSIParameter2	0x824	/* hal_mp.c */
-+#define rFPGA0_XB_HSSIParameter1	0x828	/* hal_mp.c */
-+#define rFPGA0_XB_HSSIParameter2	0x82C	/* hal_mp.c */
-+#define rTxAGC_B_Rate18_06		0x830
-+#define rTxAGC_B_Rate54_24		0x834
-+#define rTxAGC_B_CCK1_55_Mcs32	0x838
-+#define rCCAonSec_Jaguar			0x838	/* hal_mp.c */
-+#define rTxAGC_B_Mcs03_Mcs00		0x83C
-+#define rTxAGC_B_Mcs07_Mcs04		0x848
-+#define rTxAGC_B_Mcs11_Mcs08		0x84C
-+#define rFPGA0_XA_RFInterfaceOE		0x860
-+#define rFPGA0_XB_RFInterfaceOE		0x864
-+#define rTxAGC_B_Mcs15_Mcs12		0x868
-+#define rTxAGC_B_CCK11_A_CCK2_11	0x86C
-+#define rFPGA0_XAB_RFInterfaceSW		0x870
-+#define rFPGA0_XAB_RFParameter		0x878
-+#define rFPGA0_AnalogParameter4		0x88C	/* hal_mp.c & phydm */
-+#define rFPGA0_XB_LSSIReadBack		0x8A4	/* phydm */
-+#define rHSSIRead_Jaguar				0x8B0	/* RF read addr (rtl8821c_phy.c) */
-+
-+#define	rC_TxScale_Jaguar2			0x181C  /* Pah_C TX scaling factor (hal_mp.c) */
-+#define	rC_IGI_Jaguar2				0x1850	/* Initial Gain for path-C (hal_mp.c) */
-+
-+#define rFPGA1_TxInfo					0x90C	/* hal_mp.c */
-+#define rSingleTone_ContTx_Jaguar		0x914	/* hal_mp.c */
-+
-+#define rCCK0_System					0xA00
-+#define rCCK0_AFESetting				0xA04
-+
-+#define rCCK0_DSPParameter2			0xA1C
-+#define rCCK0_TxFilter1				0xA20
-+#define rCCK0_TxFilter2				0xA24
-+#define rCCK0_DebugPort				0xA28
-+#define rCCK0_FalseAlarmReport		0xA2C
-+
-+#define	rD_TxScale_Jaguar2			0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */
-+#define	rD_IGI_Jaguar2				0x1A50	/* Initial Gain for path-D (hal_mp.c) */
-+
-+#define rOFDM0_TRxPathEnable			0xC04
-+#define rOFDM0_TRMuxPar				0xC08
-+#define rA_TxScale_Jaguar				0xC1C	/* Pah_A TX scaling factor (hal_mp.c) */
-+#define rOFDM0_RxDetector1			0xC30	/* rtw_mp.c */
-+#define rOFDM0_ECCAThreshold			0xC4C	/* phydm only */
-+#define rOFDM0_XAAGCCore1			0xC50	/* phydm only */
-+#define rA_IGI_Jaguar					0xC50	/* Initial Gain for path-A (hal_mp.c) */
-+#define rOFDM0_XBAGCCore1			0xC58	/* phydm only */
-+#define rOFDM0_XATxIQImbalance		0xC80	/* phydm only */
-+#define rA_LSSIWrite_Jaguar			0xC90	/* RF write addr, LSSI Parameter (rtl8821c_phy.c) */
-+/* RFE */
-+#define rA_RFE_Pinmux_Jaguar	0xCB0	/* hal_mp.c */
-+#define	rB_RFE_Pinmux_Jaguar	0xEB0	/* Path_B RFE control pinmux */
-+#define	rA_RFE_Inv_Jaguar		0xCB4	/* Path_A RFE cotrol */  
-+#define	rB_RFE_Inv_Jaguar		0xEB4	/* Path_B RFE control */
-+#define	rA_RFE_Jaguar			0xCB8 	/* Path_A RFE cotrol */  
-+#define	rB_RFE_Jaguar			0xEB8	/* Path_B RFE control */
-+#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
-+#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
-+#define	r_ANTSEL_SW_Jaguar		0x900	/* ANTSEL SW Control */
-+#define	bMask_RFEInv_Jaguar	0x3FF00000
-+#define	bMask_AntselPathFollow_Jaguar 0x00030000   
-+
-+#define rOFDM1_LSTF					0xD00
-+#define rOFDM1_TRxPathEnable			0xD04	/* hal_mp.c */
-+#define rA_PIRead_Jaguar				0xD04	/* RF readback with PI (rtl8821c_phy.c) */
-+#define rA_SIRead_Jaguar				0xD08	/* RF readback with SI (rtl8821c_phy.c) */
-+#define rB_PIRead_Jaguar				0xD44	/* RF readback with PI (rtl8821c_phy.c) */
-+#define rB_SIRead_Jaguar				0xD48	/* RF readback with SI (rtl8821c_phy.c) */
-+
-+#define rTxAGC_A_Rate18_06			0xE00
-+#define rTxAGC_A_Rate54_24			0xE04
-+#define rTxAGC_A_CCK1_Mcs32			0xE08
-+#define rTxAGC_A_Mcs03_Mcs00		0xE10
-+#define rTxAGC_A_Mcs07_Mcs04		0xE14
-+#define rTxAGC_A_Mcs11_Mcs08		0xE18
-+#define rTxAGC_A_Mcs15_Mcs12		0xE1C
-+#define rB_TxScale_Jaguar				0xE1C	/* Path_B TX scaling factor (hal_mp.c) */
-+#define rB_IGI_Jaguar					0xE50	/* Initial Gain for path-B (hal_mp.c) */
-+#define rB_LSSIWrite_Jaguar			0xE90	/* RF write addr, LSSI Parameter (rtl8821c_phy.c) */
-+
-+/* Page1(0x100) */
-+#define bBBResetB					0x100
-+
-+/* Page8(0x800) */
-+#define bCCKEn						0x1000000
-+#define bOFDMEn						0x2000000
-+/* Reg 0x80C rFPGA0_TxGainStage */
-+#define bXBTxAGC						0xF00
-+#define bXCTxAGC						0xF000
-+#define bXDTxAGC						0xF0000
-+
-+/* PageA(0xA00) */
-+#define bCCKBBMode					0x3
-+
-+#define bCCKScramble					0x8
-+#define bCCKTxRate					0x3000
-+
-+/* General */
-+#define bMaskByte0		0xFF		/* mp, rtw_odm.c & phydm */
-+#define bMaskByte1		0xFF00		/* hal_mp.c & phydm */
-+#define bMaskByte2		0xFF0000	/* hal_mp.c & phydm */
-+#define bMaskByte3		0xFF000000	/* hal_mp.c & phydm */
-+#define bMaskHWord		0xFFFF0000	/* hal_com.c, rtw_mp.c */
-+#define bMaskLWord		0x0000FFFF	/* mp, hal_com.c & phydm */
-+#define bMaskDWord		0xFFFFFFFF	/* mp, hal, rtw_odm.c & phydm */
-+
-+#define bEnable			0x1		/* hal_mp.c, rtw_mp.c */
-+#define bDisable			0x0		/* rtw_mp.c */
-+
-+#define MAX_STALL_TIME		50		/* unit: us, hal_com_phycfg.c */
-+
-+#define Rx_Smooth_Factor		20		/* phydm only */
-+
-+/*
-+ * RF Register definition
-+ */
-+#define RF_AC			0x00
-+#define RF_AC_Jaguar		0x00	/* hal_mp.c */
-+#define RF_CHNLBW		0x18	/* rtl8821c_phy.c */
-+#define RF_0x52			0x52
-+
-+struct hw_port_reg {
-+	u32 net_type;	/*reg_offset*/
-+	u8 net_type_shift;
-+	u32 macaddr;		/*reg_offset*/
-+	u32 bssid;		/*reg_offset*/
-+	u32 bcn_ctl;			/*reg_offset*/
-+	u32 tsf_rst;			/*reg_offset*/
-+	u8 tsf_rst_bit;
-+	u32 bcn_space;		/*reg_offset*/
-+	u8 bcn_space_shift;
-+	u16 bcn_space_mask;
-+	u32	ps_aid;			/*reg_offset*/
-+	u32	ta;				/*reg_offset*/
-+};
-+
-+#endif /* __RTL8192E_SPEC_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8821ce_hal.h b/drivers/staging/rtl8723cs/include/rtl8821ce_hal.h
-new file mode 100644
-index 000000000000..426002a30c9a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8821ce_hal.h
-@@ -0,0 +1,23 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8821CE_HAL_H_
-+#define _RTL8821CE_HAL_H_
-+
-+#include <drv_types.h>		/* PADAPTER */
-+
-+/* rtl8821ce_ops.c */
-+void rtl8821ce_set_hal_ops(PADAPTER);
-+
-+#endif /* _RTL8821CE_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8821cs_hal.h b/drivers/staging/rtl8723cs/include/rtl8821cs_hal.h
-new file mode 100644
-index 000000000000..ceecc15f966d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8821cs_hal.h
-@@ -0,0 +1,23 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8821CS_HAL_H_
-+#define _RTL8821CS_HAL_H_
-+
-+#include <drv_types.h>		/* PADAPTER */
-+
-+/* rtl8821cs_ops.c */
-+u8 rtl8821cs_set_hal_ops(PADAPTER);
-+
-+#endif /* _RTL8821CS_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8821cu_hal.h b/drivers/staging/rtl8723cs/include/rtl8821cu_hal.h
-new file mode 100644
-index 000000000000..aec437224c73
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8821cu_hal.h
-@@ -0,0 +1,24 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8821CU_HAL_H_
-+#define _RTL8821CU_HAL_H_
-+
-+#include <drv_types.h>		/* PADAPTER */
-+
-+/* rtl8821cu_ops.c */
-+u8 rtl8821cu_set_hal_ops(PADAPTER);
-+void rtl8821cu_set_hw_type(struct dvobj_priv *pdvobj);
-+
-+#endif /* _RTL8821CU_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8822b_hal.h b/drivers/staging/rtl8723cs/include/rtl8822b_hal.h
-new file mode 100644
-index 000000000000..68ad9704172c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8822b_hal.h
-@@ -0,0 +1,234 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8822B_HAL_H_
-+#define _RTL8822B_HAL_H_
-+
-+#include <osdep_service.h>		/* BIT(x) */
-+#include <drv_types.h>			/* PADAPTER */
-+#include "../hal/halmac/halmac_api.h"	/* MAC REG definition */
-+
-+
-+#ifdef CONFIG_SUPPORT_TRX_SHARED
-+#define MAX_RECVBUF_SZ		46080	/* 45KB, TX: (256-64)KB */
-+#else /* !CONFIG_SUPPORT_TRX_SHARED */
-+#ifdef CONFIG_PCI_HCI
-+#define MAX_RECVBUF_SZ		12288	/* 12KB */
-+#else
-+#define MAX_RECVBUF_SZ		24576	/* 24KB, TX: 256KB */
-+#endif /* !CONFIG_PCI_HCI */
-+#endif /* !CONFIG_SUPPORT_TRX_SHARED */
-+
-+/*
-+ * MAC Register definition
-+ */
-+#define REG_AFE_XTAL_CTRL	REG_AFE_CTRL1_8822B	/* hal_com.c & phydm */
-+#define REG_AFE_PLL_CTRL	REG_AFE_CTRL2_8822B	/* hal_com.c & phydm */
-+#define REG_MAC_PHY_CTRL	REG_AFE_CTRL3_8822B	/* phydm only */
-+#define REG_LEDCFG0		REG_LED_CFG_8822B	/* rtw_mp.c */
-+#define MSR			(REG_CR_8822B + 2)	/* rtw_mp.c & hal_com.c */
-+#define MSR1			REG_CR_EXT_8822B	/* rtw_mp.c & hal_com.c */
-+#define REG_C2HEVT_MSG_NORMAL	0x1A0			/* hal_com.c */
-+#define REG_C2HEVT_CLEAR	0x1AF			/* hal_com.c */
-+#define REG_BCN_CTRL_1		REG_BCN_CTRL_CLINT0_8822B	/* hal_com.c */
-+
-+#define REG_WOWLAN_WAKE_REASON	0x01C7 /* hal_com.c */
-+#define REG_GPIO_PIN_CTRL_2		REG_GPIO_EXT_CTRL_8822B		/* hal_com.c */
-+
-+/* RXERR_RPT, for rtw_mp.c */
-+#define RXERR_TYPE_OFDM_PPDU		0
-+#define RXERR_TYPE_OFDM_FALSE_ALARM	2
-+#define RXERR_TYPE_OFDM_MPDU_OK		0
-+#define RXERR_TYPE_OFDM_MPDU_FAIL	1
-+#define RXERR_TYPE_CCK_PPDU		3
-+#define RXERR_TYPE_CCK_FALSE_ALARM	5
-+#define RXERR_TYPE_CCK_MPDU_OK		3
-+#define RXERR_TYPE_CCK_MPDU_FAIL	4
-+#define RXERR_TYPE_HT_PPDU		8
-+#define RXERR_TYPE_HT_FALSE_ALARM	9
-+#define RXERR_TYPE_HT_MPDU_TOTAL	6
-+#define RXERR_TYPE_HT_MPDU_OK		6
-+#define RXERR_TYPE_HT_MPDU_FAIL		7
-+#define RXERR_TYPE_RX_FULL_DROP		10
-+
-+#define RXERR_COUNTER_MASK		BIT_MASK_RPT_COUNTER_8822B
-+#define RXERR_RPT_RST			BIT_RXERR_RPT_RST_8822B
-+#define _RXERR_RPT_SEL(type)		(BIT_RXERR_RPT_SEL_V1_3_0_8822B(type) \
-+					| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8822B : 0))
-+
-+/*
-+ * BB Register definition
-+ */
-+#define rPMAC_Reset			0x100	/* hal_mp.c */
-+
-+#define	rFPGA0_RFMOD			0x800
-+#define rFPGA0_TxInfo			0x804
-+#define rOFDMCCKEN_Jaguar		0x808	/* hal_mp.c */
-+#define rFPGA0_TxGainStage		0x80C	/* phydm only */
-+#define rFPGA0_XA_HSSIParameter1	0x820	/* hal_mp.c */
-+#define rFPGA0_XA_HSSIParameter2	0x824	/* hal_mp.c */
-+#define rFPGA0_XB_HSSIParameter1	0x828	/* hal_mp.c */
-+#define rFPGA0_XB_HSSIParameter2	0x82C	/* hal_mp.c */
-+#define rTxAGC_B_Rate18_06		0x830
-+#define rTxAGC_B_Rate54_24		0x834
-+#define rTxAGC_B_CCK1_55_Mcs32		0x838
-+#define rCCAonSec_Jaguar		0x838	/* hal_mp.c */
-+#define rTxAGC_B_Mcs03_Mcs00		0x83C
-+#define rTxAGC_B_Mcs07_Mcs04		0x848
-+#define rTxAGC_B_Mcs11_Mcs08		0x84C
-+#define rFPGA0_XA_RFInterfaceOE		0x860
-+#define rFPGA0_XB_RFInterfaceOE		0x864
-+#define rTxAGC_B_Mcs15_Mcs12		0x868
-+#define rTxAGC_B_CCK11_A_CCK2_11	0x86C
-+#define rFPGA0_XAB_RFInterfaceSW	0x870
-+#define rFPGA0_XAB_RFParameter		0x878
-+#define rFPGA0_AnalogParameter4		0x88C	/* hal_mp.c & phydm */
-+#define rFPGA0_XB_LSSIReadBack		0x8A4	/* phydm */
-+#define rHSSIRead_Jaguar		0x8B0	/* RF read addr (rtl8822b_phy.c) */
-+
-+#define	rC_TxScale_Jaguar2		0x181C  /* Pah_C TX scaling factor (hal_mp.c) */
-+#define	rC_IGI_Jaguar2			0x1850	/* Initial Gain for path-C (hal_mp.c) */
-+
-+#define rFPGA1_TxInfo			0x90C	/* hal_mp.c */
-+#define rSingleTone_ContTx_Jaguar	0x914	/* hal_mp.c */
-+/* TX BeamForming */
-+#define REG_BB_TX_PATH_SEL_1_8822B	0x93C	/* rtl8822b_phy.c */
-+#define REG_BB_TX_PATH_SEL_2_8822B	0x940	/* rtl8822b_phy.c */
-+
-+/* TX BeamForming */
-+#define REG_BB_TXBF_ANT_SET_BF1_8822B	0x19AC	/* rtl8822b_phy.c */
-+#define REG_BB_TXBF_ANT_SET_BF0_8822B	0x19B4	/* rtl8822b_phy.c */
-+
-+#define rCCK0_System			0xA00
-+#define rCCK0_AFESetting		0xA04
-+
-+#define rCCK0_DSPParameter2		0xA1C
-+#define rCCK0_TxFilter1			0xA20
-+#define rCCK0_TxFilter2			0xA24
-+#define rCCK0_DebugPort			0xA28
-+#define rCCK0_FalseAlarmReport		0xA2C
-+
-+#define	rD_TxScale_Jaguar2		0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */
-+#define	rD_IGI_Jaguar2			0x1A50	/* Initial Gain for path-D (hal_mp.c) */
-+
-+#define rOFDM0_TRxPathEnable		0xC04
-+#define rOFDM0_TRMuxPar			0xC08
-+#define rA_TxScale_Jaguar		0xC1C	/* Pah_A TX scaling factor (hal_mp.c) */
-+#define rOFDM0_RxDetector1		0xC30	/* rtw_mp.c */
-+#define rOFDM0_ECCAThreshold		0xC4C	/* phydm only */
-+#define rOFDM0_XAAGCCore1		0xC50	/* phydm only */
-+#define rA_IGI_Jaguar			0xC50	/* Initial Gain for path-A (hal_mp.c) */
-+#define rOFDM0_XBAGCCore1		0xC58	/* phydm only */
-+#define rOFDM0_XATxIQImbalance		0xC80	/* phydm only */
-+#define rA_LSSIWrite_Jaguar		0xC90	/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
-+
-+#define rOFDM1_LSTF			0xD00
-+#define rOFDM1_TRxPathEnable		0xD04	/* hal_mp.c */
-+#define rA_PIRead_Jaguar		0xD04	/* RF readback with PI (rtl8822b_phy.c) */
-+#define rA_SIRead_Jaguar		0xD08	/* RF readback with SI (rtl8822b_phy.c) */
-+#define rB_PIRead_Jaguar		0xD44	/* RF readback with PI (rtl8822b_phy.c) */
-+#define rB_SIRead_Jaguar		0xD48	/* RF readback with SI (rtl8822b_phy.c) */
-+
-+#define rTxAGC_A_Rate18_06		0xE00
-+#define rTxAGC_A_Rate54_24		0xE04
-+#define rTxAGC_A_CCK1_Mcs32		0xE08
-+#define rTxAGC_A_Mcs03_Mcs00		0xE10
-+#define rTxAGC_A_Mcs07_Mcs04		0xE14
-+#define rTxAGC_A_Mcs11_Mcs08		0xE18
-+#define rTxAGC_A_Mcs15_Mcs12		0xE1C
-+#define rB_TxScale_Jaguar		0xE1C	/* Path_B TX scaling factor (hal_mp.c) */
-+#define rB_IGI_Jaguar			0xE50	/* Initial Gain for path-B (hal_mp.c) */
-+#define rB_LSSIWrite_Jaguar		0xE90	/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
-+/* RFE */
-+#define rA_RFE_Pinmux_Jaguar	0xCB0	/* hal_mp.c */
-+#define	rB_RFE_Pinmux_Jaguar	0xEB0	/* Path_B RFE control pinmux */
-+#define	rA_RFE_Inv_Jaguar		0xCB4	/* Path_A RFE cotrol */  
-+#define	rB_RFE_Inv_Jaguar		0xEB4	/* Path_B RFE control */
-+#define	rA_RFE_Jaguar			0xCB8 	/* Path_A RFE cotrol */  
-+#define	rB_RFE_Jaguar			0xEB8	/* Path_B RFE control */
-+#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
-+#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
-+#define	r_ANTSEL_SW_Jaguar		0x900	/* ANTSEL SW Control */
-+#define	bMask_RFEInv_Jaguar	0x3FF00000
-+#define	bMask_AntselPathFollow_Jaguar 0x00030000
-+
-+#define		rC_RFE_Pinmux_Jaguar	0x18B4	/* Path_C RFE cotrol pinmux*/
-+#define		rD_RFE_Pinmux_Jaguar	0x1AB4	/* Path_D RFE cotrol pinmux*/
-+#define		rA_RFE_Sel_Jaguar2		0x1990
-+
-+/* Page1(0x100) */
-+#define bBBResetB			0x100
-+
-+/* Page8(0x800) */
-+#define bCCKEn				0x1000000
-+#define bOFDMEn				0x2000000
-+/* Reg 0x80C rFPGA0_TxGainStage */
-+#define bXBTxAGC			0xF00
-+#define bXCTxAGC			0xF000
-+#define bXDTxAGC			0xF0000
-+
-+/* PageA(0xA00) */
-+#define bCCKBBMode			0x3
-+
-+#define bCCKScramble			0x8
-+#define bCCKTxRate			0x3000
-+
-+/* General */
-+#define bMaskByte0		0xFF		/* mp, rtw_odm.c & phydm */
-+#define bMaskByte1		0xFF00		/* hal_mp.c & phydm */
-+#define bMaskByte2		0xFF0000	/* hal_mp.c & phydm */
-+#define bMaskByte3		0xFF000000	/* hal_mp.c & phydm */
-+#define bMaskHWord		0xFFFF0000	/* hal_com.c, rtw_mp.c */
-+#define bMaskLWord		0x0000FFFF	/* mp, hal_com.c & phydm */
-+#define bMaskDWord		0xFFFFFFFF	/* mp, hal, rtw_odm.c & phydm */
-+
-+#define bEnable			0x1		/* hal_mp.c, rtw_mp.c */
-+#define bDisable		0x0		/* rtw_mp.c */
-+
-+#define MAX_STALL_TIME		50		/* unit: us, hal_com_phycfg.c */
-+
-+#define Rx_Smooth_Factor	20		/* phydm only */
-+
-+/*
-+ * RF Register definition
-+ */
-+#define RF_AC			0x00
-+#define RF_AC_Jaguar		0x00	/* hal_mp.c */
-+#define RF_CHNLBW		0x18	/* rtl8822b_phy.c */
-+#define RF_ModeTableAddr	0x30	/* rtl8822b_phy.c */
-+#define RF_ModeTableData0	0x31	/* rtl8822b_phy.c */
-+#define RF_ModeTableData1	0x32	/* rtl8822b_phy.c */
-+#define RF_0x52			0x52
-+#define RF_WeLut_Jaguar		0xEF	/* rtl8822b_phy.c */
-+
-+/* General Functions */
-+void rtl8822b_init_hal_spec(PADAPTER);				/* hal/hal_com.c */
-+
-+#ifdef CONFIG_MP_INCLUDED
-+/* MP Functions */
-+#include <rtw_mp.h>		/* struct mp_priv */
-+void rtl8822b_prepare_mp_txdesc(PADAPTER, struct mp_priv *);	/* rtw_mp.c */
-+void rtl8822b_mp_config_rfpath(PADAPTER);			/* hal_mp.c */
-+#endif
-+void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
-+
-+#ifdef CONFIG_USB_HCI
-+#include <rtl8822bu_hal.h>
-+#elif defined(CONFIG_SDIO_HCI)
-+#include <rtl8822bs_hal.h>
-+#elif defined(CONFIG_PCI_HCI)
-+#include <rtl8822be_hal.h>
-+#endif
-+
-+#endif /* _RTL8822B_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8822be_hal.h b/drivers/staging/rtl8723cs/include/rtl8822be_hal.h
-new file mode 100644
-index 000000000000..a81445fa166f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8822be_hal.h
-@@ -0,0 +1,27 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8822BE_HAL_H_
-+#define _RTL8822BE_HAL_H_
-+
-+#include <drv_types.h>		/* PADAPTER */
-+
-+#define RT_BCN_INT_MASKS	(BIT20 | BIT25 | BIT26 | BIT16)
-+
-+/* rtl8822be_ops.c */
-+void UpdateInterruptMask8822BE(PADAPTER, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
-+u16 get_txbd_rw_reg(u16 q_idx);
-+
-+
-+#endif /* _RTL8822BE_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8822bs_hal.h b/drivers/staging/rtl8723cs/include/rtl8822bs_hal.h
-new file mode 100644
-index 000000000000..ffaddee09832
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8822bs_hal.h
-@@ -0,0 +1,31 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8822BS_HAL_H_
-+#define _RTL8822BS_HAL_H_
-+
-+#include <drv_types.h>		/* PADAPTER */
-+
-+/* rtl8822bs_ops.c */
-+void rtl8822bs_set_hal_ops(PADAPTER);
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+void rtl8822bs_disable_interrupt_but_cpwm2(PADAPTER adapter);
-+#endif
-+
-+/* rtl8822bs_xmit.c */
-+s32 rtl8822bs_dequeue_writeport(PADAPTER);
-+#define _dequeue_writeport(a)	rtl8822bs_dequeue_writeport(a)
-+
-+#endif /* _RTL8822BS_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8822bu_hal.h b/drivers/staging/rtl8723cs/include/rtl8822bu_hal.h
-new file mode 100644
-index 000000000000..a35773f12bee
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8822bu_hal.h
-@@ -0,0 +1,61 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8822BU_HAL_H_
-+#define _RTL8822BU_HAL_H_
-+
-+#ifdef CONFIG_USB_HCI
-+	#include <drv_types.h>		/* PADAPTER */
-+
-+	#ifdef CONFIG_USB_HCI
-+		#ifdef USB_PACKET_OFFSET_SZ
-+			#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)
-+		#else
-+			#define PACKET_OFFSET_SZ (8)
-+		#endif
-+		#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
-+	#endif
-+
-+	/* undefine MAX_RECVBUF_SZ from rtl8822b_hal.h  */
-+	#ifdef MAX_RECVBUF_SZ
-+		#undef MAX_RECVBUF_SZ
-+	#endif
-+
-+	/* recv_buffer must be large than usb agg size */
-+	#ifndef MAX_RECVBUF_SZ
-+		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
-+			#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
-+				#define MAX_RECVBUF_SZ (15360) /* 15k */
-+				#elif defined(CONFIG_PLATFORM_HISILICON)
-+				/* use 16k to workaround for HISILICON platform */
-+				#define MAX_RECVBUF_SZ (16384)
-+			#else
-+				#define MAX_RECVBUF_SZ (32768)
-+			#endif
-+		#else
-+			#define MAX_RECVBUF_SZ (4000)
-+		#endif
-+	#endif /* !MAX_RECVBUF_SZ */
-+
-+	/* rtl8822bu_ops.c */
-+	void rtl8822bu_set_hal_ops(PADAPTER padapter);
-+	void rtl8822bu_set_hw_type(struct dvobj_priv *pdvobj);
-+
-+	/* rtl8822bu_io.c */
-+	void rtl8822bu_set_intf_ops(struct _io_ops *pops);
-+
-+#endif /* CONFIG_USB_HCI */
-+
-+
-+#endif /* _RTL8822BU_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8822c_hal.h b/drivers/staging/rtl8723cs/include/rtl8822c_hal.h
-new file mode 100644
-index 000000000000..0230d934f9ea
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8822c_hal.h
-@@ -0,0 +1,246 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8822C_HAL_H_
-+#define _RTL8822C_HAL_H_
-+
-+#include <osdep_service.h>		/* BIT(x) */
-+#include <drv_types.h>			/* PADAPTER */
-+#include "../hal/halmac/halmac_api.h"	/* MAC REG definition */
-+
-+#ifdef CONFIG_SUPPORT_TRX_SHARED
-+#define DEF_RECVBUF_SZ		24576	/* RX 24K */
-+#if (DFT_TRX_SHARE_MODE == 1)
-+#define RX_FIFO_EXPANDING 40960	/* RX= 24K+40K=64K , TX=256K-40K=216K */
-+#elif (DFT_TRX_SHARE_MODE == 2)
-+#define RX_FIFO_EXPANDING 65536	/* RX= 24K+40K+24=88K , TX=256K-40K-24K=192K */
-+#elif (DFT_TRX_SHARE_MODE ==3)
-+#define RX_FIFO_EXPANDING 106496	/* RX= 24K+40K+24+40K=128K , TX=256K-40K-24K-40K=152K */
-+#elif (DFT_TRX_SHARE_MODE ==4)
-+#define RX_FIFO_EXPANDING 131072	/* RX= 24K+40K+24+40K+24K=128K , TX=256K-40K-24K-40K-24K=128K */
-+#else
-+#define RX_FIFO_EXPANDING 0
-+#endif
-+#define MAX_RECVBUF_SZ	(DEF_RECVBUF_SZ + RX_FIFO_EXPANDING)	
-+#else /* !CONFIG_SUPPORT_TRX_SHARED */
-+#ifdef CONFIG_PCI_HCI
-+#define MAX_RECVBUF_SZ		12288	/* 12KB */
-+#else
-+#define MAX_RECVBUF_SZ		24576	/* 24KB, TX: 256KB */
-+#endif /* !CONFIG_PCI_HCI */
-+#endif /* !CONFIG_SUPPORT_TRX_SHARED */
-+
-+/*
-+ * MAC Register definition
-+ */
-+#define REG_AFE_XTAL_CTRL	REG_AFE_CTRL1_8822C	/* hal_com.c & phydm */
-+#define REG_LEDCFG0		REG_LED_CFG_8822C	/* rtw_mp.c */
-+#define MSR			(REG_CR_8822C + 2)	/* rtw_mp.c & hal_com.c */
-+#define MSR1			REG_CR_EXT_8822C	/* rtw_mp.c & hal_com.c */
-+#define REG_C2HEVT_MSG_NORMAL	0x1A0			/* hal_com.c */
-+#define REG_C2HEVT_CLEAR	0x1AF			/* hal_com.c */
-+#define REG_BCN_CTRL_1		REG_BCN_CTRL_CLINT0_8822C	/* hal_com.c */
-+
-+#define REG_WOWLAN_WAKE_REASON	0x01C7 /* hal_com.c */
-+#define REG_GPIO_PIN_CTRL_2		REG_GPIO_EXT_CTRL_8822C		/* hal_com.c */
-+
-+/* RXERR_RPT, for rtw_mp.c */
-+#define RXERR_TYPE_OFDM_PPDU		0
-+#define RXERR_TYPE_OFDM_FALSE_ALARM	2
-+#define RXERR_TYPE_OFDM_MPDU_OK		0
-+#define RXERR_TYPE_OFDM_MPDU_FAIL	1
-+#define RXERR_TYPE_CCK_PPDU		3
-+#define RXERR_TYPE_CCK_FALSE_ALARM	5
-+#define RXERR_TYPE_CCK_MPDU_OK		3
-+#define RXERR_TYPE_CCK_MPDU_FAIL	4
-+#define RXERR_TYPE_HT_PPDU		8
-+#define RXERR_TYPE_HT_FALSE_ALARM	9
-+#define RXERR_TYPE_HT_MPDU_TOTAL	6
-+#define RXERR_TYPE_HT_MPDU_OK		6
-+#define RXERR_TYPE_HT_MPDU_FAIL		7
-+#define RXERR_TYPE_RX_FULL_DROP		10
-+
-+#define RXERR_COUNTER_MASK		BIT_MASK_RPT_COUNTER_8822C
-+#define RXERR_RPT_RST			BIT_RXERR_RPT_RST_8822C
-+#define _RXERR_RPT_SEL(type)		(BIT_RXERR_RPT_SEL_V1_3_0_8822C(type) \
-+					| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8822C : 0))
-+
-+/*
-+ * BB Register definition
-+ */
-+#define rPMAC_Reset			0x100	/* hal_mp.c */
-+
-+#define	rFPGA0_RFMOD			0x800
-+#define rFPGA0_TxInfo			0x804
-+#define rOFDMCCKEN_Jaguar		0x808	/* hal_mp.c */
-+#define rFPGA0_TxGainStage		0x80C	/* phydm only */
-+#define rFPGA0_XA_HSSIParameter1	0x820	/* hal_mp.c */
-+#define rFPGA0_XA_HSSIParameter2	0x824	/* hal_mp.c */
-+#define rFPGA0_XB_HSSIParameter1	0x828	/* hal_mp.c */
-+#define rFPGA0_XB_HSSIParameter2	0x82C	/* hal_mp.c */
-+#define rTxAGC_B_Rate18_06		0x830
-+#define rTxAGC_B_Rate54_24		0x834
-+#define rTxAGC_B_CCK1_55_Mcs32		0x838
-+#define rCCAonSec_Jaguar		0x838	/* hal_mp.c */
-+#define rTxAGC_B_Mcs03_Mcs00		0x83C
-+#define rTxAGC_B_Mcs07_Mcs04		0x848
-+#define rTxAGC_B_Mcs11_Mcs08		0x84C
-+#define rFPGA0_XA_RFInterfaceOE		0x860
-+#define rFPGA0_XB_RFInterfaceOE		0x864
-+#define rTxAGC_B_Mcs15_Mcs12		0x868
-+#define rTxAGC_B_CCK11_A_CCK2_11	0x86C
-+#define rFPGA0_XAB_RFInterfaceSW	0x870
-+#define rFPGA0_XAB_RFParameter		0x878
-+#define rFPGA0_AnalogParameter4		0x88C	/* hal_mp.c & phydm */
-+#define rFPGA0_XB_LSSIReadBack		0x8A4	/* phydm */
-+#define rHSSIRead_Jaguar		0x8B0	/* RF read addr (rtl8822c_phy.c) */
-+
-+#define	rC_TxScale_Jaguar2		0x181C  /* Pah_C TX scaling factor (hal_mp.c) */
-+#define	rC_IGI_Jaguar2			0x1850	/* Initial Gain for path-C (hal_mp.c) */
-+
-+#define rFPGA1_TxInfo			0x90C	/* hal_mp.c */
-+#define rSingleTone_ContTx_Jaguar	0x914	/* hal_mp.c */
-+/* TX BeamForming */
-+#define REG_BB_TX_PATH_SEL_1_8822C	0x93C	/* rtl8822c_phy.c */
-+#define REG_BB_TX_PATH_SEL_2_8822C	0x940	/* rtl8822c_phy.c */
-+
-+/* TX BeamForming */
-+#define REG_BB_TXBF_ANT_SET_BF1_8822C	0x19AC	/* rtl8822c_phy.c */
-+#define REG_BB_TXBF_ANT_SET_BF0_8822C	0x19B4	/* rtl8822c_phy.c */
-+
-+#define rCCK0_System			0xA00
-+#define rCCK0_AFESetting		0xA04
-+
-+#define rCCK0_DSPParameter2		0xA1C
-+#define rCCK0_TxFilter1			0xA20
-+#define rCCK0_TxFilter2			0xA24
-+#define rCCK0_DebugPort			0xA28
-+#define rCCK0_FalseAlarmReport		0xA2C
-+
-+#define	rD_TxScale_Jaguar2		0x1A1C  /* Path_D TX scaling factor (hal_mp.c) */
-+#define	rD_IGI_Jaguar2			0x1A50	/* Initial Gain for path-D (hal_mp.c) */
-+
-+#define rOFDM0_TRxPathEnable		0xC04
-+#define rOFDM0_TRMuxPar			0xC08
-+#define rA_TxScale_Jaguar		0xC1C	/* Pah_A TX scaling factor (hal_mp.c) */
-+#define rOFDM0_RxDetector1		0xC30	/* rtw_mp.c */
-+#define rOFDM0_ECCAThreshold		0xC4C	/* phydm only */
-+#define rOFDM0_XAAGCCore1		0xC50	/* phydm only */
-+#define rA_IGI_Jaguar			0xC50	/* Initial Gain for path-A (hal_mp.c) */
-+#define rOFDM0_XBAGCCore1		0xC58	/* phydm only */
-+#define rOFDM0_XATxIQImbalance		0xC80	/* phydm only */
-+#define rA_LSSIWrite_Jaguar		0xC90	/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
-+
-+#define rOFDM1_LSTF			0xD00
-+#define rOFDM1_TRxPathEnable		0xD04	/* hal_mp.c */
-+#define rA_PIRead_Jaguar		0xD04	/* RF readback with PI (rtl8822c_phy.c) */
-+#define rA_SIRead_Jaguar		0xD08	/* RF readback with SI (rtl8822c_phy.c) */
-+#define rB_PIRead_Jaguar		0xD44	/* RF readback with PI (rtl8822c_phy.c) */
-+#define rB_SIRead_Jaguar		0xD48	/* RF readback with SI (rtl8822c_phy.c) */
-+
-+#define rTxAGC_A_Rate18_06		0xE00
-+#define rTxAGC_A_Rate54_24		0xE04
-+#define rTxAGC_A_CCK1_Mcs32		0xE08
-+#define rTxAGC_A_Mcs03_Mcs00		0xE10
-+#define rTxAGC_A_Mcs07_Mcs04		0xE14
-+#define rTxAGC_A_Mcs11_Mcs08		0xE18
-+#define rTxAGC_A_Mcs15_Mcs12		0xE1C
-+#define rB_TxScale_Jaguar		0xE1C	/* Path_B TX scaling factor (hal_mp.c) */
-+#define rB_IGI_Jaguar			0xE50	/* Initial Gain for path-B (hal_mp.c) */
-+#define rB_LSSIWrite_Jaguar		0xE90	/* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
-+/* RFE */
-+#define rA_RFE_Pinmux_Jaguar	0xCB0	/* hal_mp.c */
-+#define	rB_RFE_Pinmux_Jaguar	0xEB0	/* Path_B RFE control pinmux */
-+#define	rA_RFE_Inv_Jaguar		0xCB4	/* Path_A RFE cotrol */  
-+#define	rB_RFE_Inv_Jaguar		0xEB4	/* Path_B RFE control */
-+#define	rA_RFE_Jaguar			0xCB8 	/* Path_A RFE cotrol */  
-+#define	rB_RFE_Jaguar			0xEB8	/* Path_B RFE control */
-+#define	rA_RFE_Inverse_Jaguar	0xCBC	/* Path_A RFE control inverse */
-+#define	rB_RFE_Inverse_Jaguar	0xEBC	/* Path_B RFE control inverse */
-+#define	r_ANTSEL_SW_Jaguar		0x900	/* ANTSEL SW Control */
-+#define	bMask_RFEInv_Jaguar	0x3FF00000
-+#define	bMask_AntselPathFollow_Jaguar 0x00030000
-+
-+#define		rC_RFE_Pinmux_Jaguar	0x18B4	/* Path_C RFE cotrol pinmux*/
-+#define		rD_RFE_Pinmux_Jaguar	0x1AB4	/* Path_D RFE cotrol pinmux*/
-+#define		rA_RFE_Sel_Jaguar2		0x1990
-+
-+/* Page1(0x100) */
-+#define bBBResetB			0x100
-+
-+/* Page8(0x800) */
-+#define bCCKEn				0x1000000
-+#define bOFDMEn				0x2000000
-+/* Reg 0x80C rFPGA0_TxGainStage */
-+#define bXBTxAGC			0xF00
-+#define bXCTxAGC			0xF000
-+#define bXDTxAGC			0xF0000
-+
-+/* PageA(0xA00) */
-+#define bCCKBBMode			0x3
-+
-+#define bCCKScramble			0x8
-+#define bCCKTxRate			0x3000
-+
-+/* General */
-+#define bMaskByte0		0xFF		/* mp, rtw_odm.c & phydm */
-+#define bMaskByte1		0xFF00		/* hal_mp.c & phydm */
-+#define bMaskByte2		0xFF0000	/* hal_mp.c & phydm */
-+#define bMaskByte3		0xFF000000	/* hal_mp.c & phydm */
-+#define bMaskHWord		0xFFFF0000	/* hal_com.c, rtw_mp.c */
-+#define bMaskLWord		0x0000FFFF	/* mp, hal_com.c & phydm */
-+#define bMaskDWord		0xFFFFFFFF	/* mp, hal, rtw_odm.c & phydm */
-+
-+#define bEnable			0x1		/* hal_mp.c, rtw_mp.c */
-+#define bDisable		0x0		/* rtw_mp.c */
-+
-+#define MAX_STALL_TIME		50		/* unit: us, hal_com_phycfg.c */
-+
-+#define Rx_Smooth_Factor	20		/* phydm only */
-+
-+/*
-+ * RF Register definition
-+ */
-+#define RF_AC			0x00
-+#define RF_AC_Jaguar		0x00	/* hal_mp.c */
-+#define RF_CHNLBW		0x18	/* rtl8822c_phy.c */
-+#define RF_ModeTableAddr	0x30	/* rtl8822c_phy.c */
-+#define RF_ModeTableData0	0x31	/* rtl8822c_phy.c */
-+#define RF_ModeTableData1	0x32	/* rtl8822c_phy.c */
-+#define RF_0x52			0x52
-+#define RF_WeLut_Jaguar		0xEF	/* rtl8822c_phy.c */
-+
-+/* rtw_lps_state_chk()@hal_com.c */
-+#define BIT_PWRBIT_OW_EN	BIT_WMAC_TCRPWRMGT_HWDATA_EN_8822C 
-+
-+/* General Functions */
-+void rtl8822c_init_hal_spec(PADAPTER);				/* hal/hal_com.c */
-+
-+#ifdef CONFIG_MP_INCLUDED
-+/* MP Functions */
-+#include <rtw_mp.h>		/* struct mp_priv */
-+void rtl8822c_prepare_mp_txdesc(PADAPTER, struct mp_priv *);	/* rtw_mp.c */
-+void rtl8822c_mp_config_rfpath(PADAPTER);			/* hal_mp.c */
-+#endif
-+void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
-+
-+#ifdef CONFIG_USB_HCI
-+#include <rtl8822cu_hal.h>
-+#elif defined(CONFIG_SDIO_HCI)
-+#include <rtl8822cs_hal.h>
-+#elif defined(CONFIG_PCI_HCI)
-+#include <rtl8822ce_hal.h>
-+#endif
-+
-+#endif /* _RTL8822C_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8822ce_hal.h b/drivers/staging/rtl8723cs/include/rtl8822ce_hal.h
-new file mode 100644
-index 000000000000..f56566e05fd3
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8822ce_hal.h
-@@ -0,0 +1,27 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8822CE_HAL_H_
-+#define _RTL8822CE_HAL_H_
-+
-+#include <drv_types.h>		/* PADAPTER */
-+
-+#define RT_BCN_INT_MASKS	(BIT20 | BIT25 | BIT26 | BIT16)
-+
-+/* rtl8822ce_ops.c */
-+void UpdateInterruptMask8822CE(PADAPTER, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
-+u16 get_txbd_rw_reg(u16 q_idx);
-+
-+
-+#endif /* _RTL8822CE_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8822cs_hal.h b/drivers/staging/rtl8723cs/include/rtl8822cs_hal.h
-new file mode 100644
-index 000000000000..3e54b2a65e77
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8822cs_hal.h
-@@ -0,0 +1,31 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8822CS_HAL_H_
-+#define _RTL8822CS_HAL_H_
-+
-+#include <drv_types.h>		/* PADAPTER */
-+
-+/* rtl8822cs_ops.c */
-+void rtl8822cs_set_hal_ops(PADAPTER);
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+void rtl8822cs_disable_interrupt_but_cpwm2(PADAPTER adapter);
-+#endif
-+
-+/* rtl8822cs_xmit.c */
-+s32 rtl8822cs_dequeue_writeport(PADAPTER);
-+#define _dequeue_writeport(a)	rtl8822cs_dequeue_writeport(a)
-+
-+#endif /* _RTL8822CS_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtl8822cu_hal.h b/drivers/staging/rtl8723cs/include/rtl8822cu_hal.h
-new file mode 100644
-index 000000000000..ba2e36e56762
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtl8822cu_hal.h
-@@ -0,0 +1,61 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL8822CU_HAL_H_
-+#define _RTL8822CU_HAL_H_
-+
-+#ifdef CONFIG_USB_HCI
-+	#include <drv_types.h>		/* PADAPTER */
-+
-+	#ifdef CONFIG_USB_HCI
-+		#ifdef USB_PACKET_OFFSET_SZ
-+			#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)
-+		#else
-+			#define PACKET_OFFSET_SZ (8)
-+		#endif
-+		#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
-+	#endif
-+
-+	/* undefine MAX_RECVBUF_SZ from rtl8822c_hal.h  */
-+	#ifdef MAX_RECVBUF_SZ
-+		#undef MAX_RECVBUF_SZ
-+	#endif
-+
-+	/* recv_buffer must be large than usb agg size */
-+	#ifndef MAX_RECVBUF_SZ
-+		#ifndef CONFIG_MINIMAL_MEMORY_USAGE
-+			#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
-+				#define MAX_RECVBUF_SZ (15360) /* 15k */
-+				#elif defined(CONFIG_PLATFORM_HISILICON)
-+				/* use 16k to workaround for HISILICON platform */
-+				#define MAX_RECVBUF_SZ (16384)
-+			#else
-+				#define MAX_RECVBUF_SZ (32768)
-+			#endif
-+		#else
-+			#define MAX_RECVBUF_SZ (4000)
-+		#endif
-+	#endif /* !MAX_RECVBUF_SZ */
-+
-+	/* rtl8822cu_ops.c */
-+	void rtl8822cu_set_hal_ops(PADAPTER padapter);
-+	void rtl8822cu_set_hw_type(struct dvobj_priv *pdvobj);
-+
-+	/* rtl8822cu_io.c */
-+	void rtl8822cu_set_intf_ops(struct _io_ops *pops);
-+
-+#endif /* CONFIG_USB_HCI */
-+
-+
-+#endif /* _RTL8822CU_HAL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_android.h b/drivers/staging/rtl8723cs/include/rtw_android.h
-new file mode 100644
-index 000000000000..9bb8e32f5ec5
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_android.h
-@@ -0,0 +1,117 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __RTW_ANDROID_H__
-+#define __RTW_ANDROID_H__
-+
-+enum ANDROID_WIFI_CMD {
-+	ANDROID_WIFI_CMD_START,
-+	ANDROID_WIFI_CMD_STOP,
-+	ANDROID_WIFI_CMD_SCAN_ACTIVE,
-+	ANDROID_WIFI_CMD_SCAN_PASSIVE,
-+	ANDROID_WIFI_CMD_RSSI,
-+	ANDROID_WIFI_CMD_LINKSPEED,
-+	ANDROID_WIFI_CMD_RXFILTER_START,
-+	ANDROID_WIFI_CMD_RXFILTER_STOP,
-+	ANDROID_WIFI_CMD_RXFILTER_ADD,
-+	ANDROID_WIFI_CMD_RXFILTER_REMOVE,
-+	ANDROID_WIFI_CMD_BTCOEXSCAN_START,
-+	ANDROID_WIFI_CMD_BTCOEXSCAN_STOP,
-+	ANDROID_WIFI_CMD_BTCOEXMODE,
-+	ANDROID_WIFI_CMD_SETSUSPENDMODE,
-+	ANDROID_WIFI_CMD_SETSUSPENDOPT,
-+	ANDROID_WIFI_CMD_P2P_DEV_ADDR,
-+	ANDROID_WIFI_CMD_SETFWPATH,
-+	ANDROID_WIFI_CMD_SETBAND,
-+	ANDROID_WIFI_CMD_GETBAND,
-+	ANDROID_WIFI_CMD_COUNTRY,
-+	ANDROID_WIFI_CMD_P2P_SET_NOA,
-+	ANDROID_WIFI_CMD_P2P_GET_NOA,
-+	ANDROID_WIFI_CMD_P2P_SET_PS,
-+	ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE,
-+
-+	ANDROID_WIFI_CMD_MIRACAST,
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+	ANDROID_WIFI_CMD_PNOSSIDCLR_SET,
-+	ANDROID_WIFI_CMD_PNOSETUP_SET,
-+	ANDROID_WIFI_CMD_PNOENABLE_SET,
-+	ANDROID_WIFI_CMD_PNODEBUG_SET,
-+#endif
-+
-+	ANDROID_WIFI_CMD_MACADDR,
-+
-+	ANDROID_WIFI_CMD_BLOCK_SCAN,
-+	ANDROID_WIFI_CMD_BLOCK,
-+
-+	ANDROID_WIFI_CMD_WFD_ENABLE,
-+	ANDROID_WIFI_CMD_WFD_DISABLE,
-+
-+	ANDROID_WIFI_CMD_WFD_SET_TCPPORT,
-+	ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT,
-+	ANDROID_WIFI_CMD_WFD_SET_DEVTYPE,
-+	ANDROID_WIFI_CMD_CHANGE_DTIM,
-+	ANDROID_WIFI_CMD_HOSTAPD_SET_MACADDR_ACL,
-+	ANDROID_WIFI_CMD_HOSTAPD_ACL_ADD_STA,
-+	ANDROID_WIFI_CMD_HOSTAPD_ACL_REMOVE_STA,
-+#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
-+	ANDROID_WIFI_CMD_GTK_REKEY_OFFLOAD,
-+#endif /* CONFIG_GTK_OL */
-+	ANDROID_WIFI_CMD_P2P_DISABLE,
-+	ANDROID_WIFI_CMD_SET_AEK,
-+	ANDROID_WIFI_CMD_EXT_AUTH_STATUS,
-+	ANDROID_WIFI_CMD_DRIVERVERSION,
-+	ANDROID_WIFI_CMD_MAX
-+};
-+
-+int rtw_android_cmdstr_to_num(char *cmdstr);
-+int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd);
-+
-+#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+int rtw_android_pno_enable(struct net_device *net, int pno_enable);
-+int rtw_android_cfg80211_pno_setup(struct net_device *net,
-+		   struct cfg80211_ssid *ssid, int n_ssids, int interval);
-+#endif
-+
-+#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)
-+int rtw_android_wifictrl_func_add(void);
-+void rtw_android_wifictrl_func_del(void);
-+void *wl_android_prealloc(int section, unsigned long size);
-+
-+int wifi_get_irq_number(unsigned long *irq_flags_ptr);
-+int wifi_set_power(int on, unsigned long msec);
-+int wifi_get_mac_addr(unsigned char *buf);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
-+void *wifi_get_country_code(char *ccode, u32 flags);
-+#else /* Linux kernel < 3.18 */
-+void *wifi_get_country_code(char *ccode);
-+#endif /* Linux kernel < 3.18 */
-+#else
-+static inline int rtw_android_wifictrl_func_add(void)
-+{
-+	return 0;
-+}
-+static inline void rtw_android_wifictrl_func_del(void) {}
-+#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+int wifi_configure_gpio(void);
-+#endif /* CONFIG_PLATFORM_INTEL_BYT */
-+void wifi_free_gpio(unsigned int gpio);
-+#endif /* CONFIG_GPIO_WAKEUP */
-+
-+
-+#endif /* __RTW_ANDROID_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_ap.h b/drivers/staging/rtl8723cs/include/rtw_ap.h
-new file mode 100644
-index 000000000000..5ccb5516fb83
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_ap.h
-@@ -0,0 +1,143 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_AP_H_
-+#define __RTW_AP_H_
-+
-+
-+#ifdef CONFIG_AP_MODE
-+
-+/* external function */
-+extern void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta);
-+extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta);
-+
-+
-+void init_mlme_ap_info(_adapter *padapter);
-+void free_mlme_ap_info(_adapter *padapter);
-+u8 rtw_set_tim_ie(u8 dtim_cnt, u8 dtim_period
-+	, const u8 *tim_bmp, u8 tim_bmp_len, u8 *tim_ie);
-+/* void update_BCNTIM(_adapter *padapter); */
-+void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len);
-+void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index);
-+void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, u8 flags, const char *tag);
-+#define update_beacon(adapter, ie_id, oui, tx, flags) _update_beacon((adapter), (ie_id), (oui), (tx), (flags), __func__)
-+/*update_beacon - (flags) can set to normal enqueue (0) and RTW_CMDF_WAIT_ACK enqueue. 
-+ (flags) = RTW_CMDF_DIRECTLY  is not currently implemented, it will do normal enqueue.*/
-+
-+void rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta);
-+
-+void expire_timeout_chk(_adapter *padapter);
-+void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta);
-+void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter);
-+void start_bss_network(_adapter *padapter, struct createbss_parm *parm);
-+int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf,  int len);
-+void rtw_ap_restore_network(_adapter *padapter);
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+void rtw_macaddr_acl_init(_adapter *adapter, u8 period);
-+void rtw_macaddr_acl_deinit(_adapter *adapter, u8 period);
-+void rtw_macaddr_acl_clear(_adapter *adapter, u8 period);
-+void rtw_set_macaddr_acl(_adapter *adapter, u8 period, int mode);
-+int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr);
-+int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr);
-+#endif /* CONFIG_RTW_MACADDR_ACL */
-+
-+u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk);
-+u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta);
-+int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid);
-+int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx);
-+
-+#ifdef CONFIG_NATIVEAP_MLME
-+void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type);
-+void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta);
-+u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta);
-+void sta_info_update(_adapter *padapter, struct sta_info *psta);
-+void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta);
-+u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue);
-+int rtw_sta_flush(_adapter *padapter, bool enqueue);
-+int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset);
-+void start_ap_mode(_adapter *padapter);
-+void stop_ap_mode(_adapter *padapter);
-+#endif
-+
-+void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset);
-+u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp
-+	, s16 req_ch, s8 req_bw, s8 req_offset, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow, bool *set_u_ch);
-+
-+#ifdef CONFIG_AUTO_AP_MODE
-+void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos);
-+extern void rtw_start_auto_ap(_adapter *adapter);
-+#endif /* CONFIG_AUTO_AP_MODE */
-+
-+void rtw_ap_parse_sta_capability(_adapter *adapter, struct sta_info *sta, u8 *cap);
-+u16 rtw_ap_parse_sta_supported_rates(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len);
-+u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems);
-+void rtw_ap_parse_sta_wmm_ie(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len);
-+void rtw_ap_parse_sta_ht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems);
-+void rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems);
-+void rtw_ap_parse_sta_multi_ap_ie(_adapter *adapter, struct sta_info *sta, u8 *ies, int ies_len);
-+
-+/* b2u flags */
-+#define RTW_AP_B2U_ALL		BIT0
-+#define RTW_AP_B2U_GA_UCAST	BIT1 /* WDS group addressed unicast frame, forward only */
-+#define RTW_AP_B2U_BCAST	BIT2
-+#define RTW_AP_B2U_IP_MCAST	BIT3
-+
-+#define rtw_ap_src_b2u_policy_chk(flags, da) ( \
-+	(flags & RTW_AP_B2U_ALL) \
-+	|| ((flags & RTW_AP_B2U_BCAST) && is_broadcast_mac_addr(da)) \
-+	|| ((flags & RTW_AP_B2U_IP_MCAST) && (IP_MCAST_MAC(da) || ICMPV6_MCAST_MAC(da))) \
-+	)
-+
-+#define rtw_ap_fwd_b2u_policy_chk(flags, da, gaucst) ( \
-+	(flags & RTW_AP_B2U_ALL) \
-+	|| ((flags & RTW_AP_B2U_GA_UCAST) && gaucst) \
-+	|| ((flags & RTW_AP_B2U_BCAST) && is_broadcast_mac_addr(da)) \
-+	|| ((flags & RTW_AP_B2U_IP_MCAST) && (IP_MCAST_MAC(da) || ICMPV6_MCAST_MAC(da))) \
-+	)
-+
-+void dump_ap_b2u_flags(void *sel, _adapter *adapter);
-+
-+int rtw_ap_addr_resolve(_adapter *adapter, u16 os_qid, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list);
-+int rtw_ap_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta);
-+int rtw_ap_rx_msdu_act_check(union recv_frame *rframe
-+	, const u8 *da, const u8 *sa
-+	, u8 *msdu, enum rtw_rx_llc_hdl llc_hdl
-+	, struct xmit_frame **fwd_frame, _list *b2u_list);
-+
-+void update_bmc_sta(_adapter *padapter);
-+
-+#ifdef CONFIG_BMC_TX_RATE_SELECT
-+void rtw_update_bmc_sta_tx_rate(_adapter *adapter);
-+#endif
-+
-+void rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field);
-+void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len);
-+#ifdef CONFIG_80211N_HT
-+int rtw_ht_operation_update(_adapter *padapter);
-+#endif /* CONFIG_80211N_HT */
-+u8 rtw_ap_sta_states_check(_adapter *adapter);
-+
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+#define rtw_ap_get_nums(adapter)	(adapter_to_dvobj(adapter)->nr_ap_if)
-+bool rtw_ap_nums_check(_adapter *adapter);
-+#endif
-+
-+#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+void tx_beacon_handlder(struct dvobj_priv *pdvobj);
-+void tx_beacon_timer_handlder(void *ctx);
-+#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
-+
-+#endif /* end of CONFIG_AP_MODE */
-+#endif /*__RTW_AP_H_*/
-diff --git a/drivers/staging/rtl8723cs/include/rtw_beamforming.h b/drivers/staging/rtl8723cs/include/rtw_beamforming.h
-new file mode 100644
-index 000000000000..4c7f006e8254
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_beamforming.h
-@@ -0,0 +1,297 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_BEAMFORMING_H_
-+#define __RTW_BEAMFORMING_H_
-+
-+#ifdef CONFIG_BEAMFORMING
-+
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+#define MAX_NUM_BEAMFORMEE_SU	2
-+#define MAX_NUM_BEAMFORMER_SU	2
-+#define MAX_NUM_BEAMFORMEE_MU	6
-+#define MAX_NUM_BEAMFORMER_MU	1
-+
-+#define MAX_BEAMFORMEE_ENTRY_NUM	(MAX_NUM_BEAMFORMEE_SU + MAX_NUM_BEAMFORMEE_MU)
-+#define MAX_BEAMFORMER_ENTRY_NUM	(MAX_NUM_BEAMFORMER_SU + MAX_NUM_BEAMFORMER_MU)
-+
-+/* <Note> Need to be defined by IC */
-+#define SU_SOUNDING_TIMEOUT	5	/* unit: ms */
-+#define MU_SOUNDING_TIMEOUT	8	/* unit: ms */
-+
-+#define GET_BEAMFORM_INFO(adapter)	(&GET_HAL_DATA(adapter)->beamforming_info)
-+#define GetInitSoundCnt(_SoundPeriod, _MinSoundPeriod)	((_SoundPeriod)/(_MinSoundPeriod))
-+
-+enum BEAMFORMING_CTRL_TYPE {
-+	BEAMFORMING_CTRL_ENTER = 0,
-+	BEAMFORMING_CTRL_LEAVE = 1,
-+	BEAMFORMING_CTRL_START_PERIOD = 2,
-+	BEAMFORMING_CTRL_END_PERIOD = 3,
-+	BEAMFORMING_CTRL_SOUNDING_FAIL = 4,
-+	BEAMFORMING_CTRL_SOUNDING_CLK = 5,
-+	BEAMFORMING_CTRL_SET_GID_TABLE = 6,
-+	BEAMFORMING_CTRL_SET_CSI_REPORT = 7,
-+};
-+
-+enum _BEAMFORMING_STATE {
-+	BEAMFORMING_STATE_IDLE,
-+	BEAMFORMING_STATE_START,
-+	BEAMFORMING_STATE_END,
-+};
-+
-+/*
-+ * typedef BEAMFORMING_CAP for phydm
-+ */
-+typedef enum beamforming_cap {
-+	BEAMFORMING_CAP_NONE = 0x0,
-+	BEAMFORMER_CAP_HT_EXPLICIT = 0x1,
-+	BEAMFORMEE_CAP_HT_EXPLICIT = 0x2,
-+	BEAMFORMER_CAP_VHT_SU = 0x4,			/* Self has er Cap, because Reg er  & peer ee */
-+	BEAMFORMEE_CAP_VHT_SU = 0x8, 			/* Self has ee Cap, because Reg ee & peer er */
-+	BEAMFORMER_CAP_VHT_MU = 0x10,			/* Self has er Cap, because Reg er & peer ee */
-+	BEAMFORMEE_CAP_VHT_MU = 0x20,			/* Self has ee Cap, because Reg ee & peer er */
-+	BEAMFORMER_CAP = 0x40,
-+	BEAMFORMEE_CAP = 0x80,
-+} BEAMFORMING_CAP;
-+
-+enum _BEAMFORM_ENTRY_HW_STATE {
-+	BEAMFORM_ENTRY_HW_STATE_NONE,
-+	BEAMFORM_ENTRY_HW_STATE_ADD_INIT,
-+	BEAMFORM_ENTRY_HW_STATE_ADDING,
-+	BEAMFORM_ENTRY_HW_STATE_ADDED,
-+	BEAMFORM_ENTRY_HW_STATE_DELETE_INIT,
-+	BEAMFORM_ENTRY_HW_STATE_DELETING,
-+	BEAMFORM_ENTRY_HW_STATE_MAX
-+};
-+
-+/* The sounding state is recorded by BFer. */
-+enum _SOUNDING_STATE {
-+	SOUNDING_STATE_NONE		= 0,
-+	SOUNDING_STATE_INIT		= 1,
-+	SOUNDING_STATE_SU_START		= 2,
-+	SOUNDING_STATE_SU_SOUNDDOWN	= 3,
-+	SOUNDING_STATE_MU_START		= 4,
-+	SOUNDING_STATE_MU_SOUNDDOWN	= 5,
-+	SOUNDING_STATE_SOUNDING_TIMEOUT	= 6,
-+	SOUNDING_STATE_MAX
-+};
-+
-+struct beamformee_entry {
-+	u8 used;	/* _TRUE/_FALSE */
-+	u8 txbf;
-+	u8 sounding;
-+	/* Used to construct AID field of NDPA packet */
-+	u16 aid;
-+	/* Used to Set Reg42C in IBSS mode */
-+	u16 mac_id;
-+	/* Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC */
-+	u16 p_aid;
-+	u8 g_id;
-+	/* Used to fill Reg6E4 to fill Mac address of CSI report frame */
-+	u8 mac_addr[ETH_ALEN];
-+	/* Sounding BandWidth */
-+	enum channel_width sound_bw;
-+	u16 sound_period;
-+
-+	enum beamforming_cap cap;
-+	enum _BEAMFORM_ENTRY_HW_STATE state;
-+
-+	/* The BFee need to be sounded when count to zero */
-+	u8 SoundCnt;
-+	u8 bCandidateSoundingPeer;
-+	u8 bSoundingTimeout;
-+	u8 bDeleteSounding;
-+	/* Get the result through throughput and Tx rate from BB API */
-+	u8 bApplySounding;
-+
-+	/* information for sounding judgement */
-+	systime tx_timestamp;
-+	u64 tx_bytes;
-+
-+	u16 LogStatusFailCnt:5;	/* 0~21 */
-+	u16 DefaultCSICnt:5; /* 0~21 */
-+	u8 CSIMatrix[327];
-+	u16 CSIMatrixLen;
-+
-+	u8 NumofSoundingDim;
-+
-+	u8 comp_steering_num_of_bfer;
-+
-+
-+	/* SU-MIMO */
-+	u8 su_reg_index;
-+
-+	/* MU-MIMO */
-+	u8 mu_reg_index;
-+	u8 gid_valid[8];
-+	u8 user_position[16];
-+
-+	/* For 8822B C-cut workaround */
-+	/* If the flag set to _TRUE, do not sound this STA */
-+	u8 bSuspendSUCap;
-+};
-+
-+struct beamformer_entry {
-+	u8 used;
-+	/* p_aid of BFer entry is probably not used */
-+	/* Used to fill Reg42C & Reg714 to compare with p_aid of Tx DESC */
-+	u16 p_aid;
-+	u8 g_id;
-+	u8 mac_addr[ETH_ALEN];
-+
-+	enum beamforming_cap cap;
-+	enum _BEAMFORM_ENTRY_HW_STATE state;
-+
-+	u8 NumofSoundingDim;
-+
-+	/* SU-MIMO */
-+	u8 su_reg_index;
-+
-+	/* MU-MIMO */
-+	u8 gid_valid[8];
-+	u8 user_position[16];
-+	u16 aid;
-+};
-+
-+struct sounding_info {
-+	u8 su_sounding_list[MAX_NUM_BEAMFORMEE_SU];
-+	u8 mu_sounding_list[MAX_NUM_BEAMFORMEE_MU];
-+
-+	enum _SOUNDING_STATE state;
-+	/*
-+	 * su_bfee_curidx is index for beamforming_info.bfee_entry[]
-+	 * range: 0~MAX_BEAMFORMEE_ENTRY_NUM
-+	 */
-+	u8 su_bfee_curidx;
-+	u8 candidate_mu_bfee_cnt;
-+
-+	/* For sounding schedule maintenance */
-+	u16 min_sounding_period;
-+	/* Get from sounding list */
-+	/* Ex: SU STA1, SU STA2, MU STA(1~n) => the value will be 2+1=3 */
-+	u8 sound_remain_cnt_per_period;
-+};
-+
-+struct _RT_CSI_INFO{
-+	u8 Nc;
-+	u8 Nr;
-+	u8 Ng;
-+	u8 CodeBook;
-+	u8 ChnlWidth;
-+	u8 bVHT;
-+};
-+
-+struct beamforming_info {
-+	enum beamforming_cap beamforming_cap;
-+	enum _BEAMFORMING_STATE beamforming_state;
-+	struct beamformee_entry bfee_entry[MAX_BEAMFORMEE_ENTRY_NUM];
-+	struct beamformer_entry bfer_entry[MAX_BEAMFORMER_ENTRY_NUM];
-+	u8 sounding_sequence;
-+	u8 beamformee_su_cnt;
-+	u8 beamformer_su_cnt;
-+	u32 beamformee_su_reg_maping;
-+	u32 beamformer_su_reg_maping;
-+	/* For MU-MINO */
-+	u8 beamformee_mu_cnt;
-+	u8 beamformer_mu_cnt;
-+	u32 beamformee_mu_reg_maping;
-+	u8 first_mu_bfee_index;
-+	u8 mu_bfer_curidx;
-+	u8 cur_csi_rpt_rate;
-+
-+	struct sounding_info sounding_info;
-+	/* schedule regular timer for sounding */
-+	_timer sounding_timer;
-+	/* moniter if soudning too long */
-+	_timer sounding_timeout_timer;
-+
-+	/* For HW configuration */
-+	u8 SetHalBFEnterOnDemandCnt;
-+	u8 SetHalBFLeaveOnDemandCnt;
-+	u8 SetHalSoundownOnDemandCnt;
-+	u8 bSetBFHwConfigInProgess;
-+
-+	/*
-+	 * Target CSI report info.
-+	 * Keep the first SU CSI report info for 8822B HW bug workaround.
-+	 */
-+	u8 bEnableSUTxBFWorkAround;
-+	struct _RT_CSI_INFO TargetCSIInfo;
-+	/* Only peform sounding to the first SU BFee */
-+	struct beamformee_entry *TargetSUBFee;
-+
-+	/* For debug */
-+	s8 sounding_running;
-+};
-+
-+enum beamforming_cap rtw_bf_bfee_get_entry_cap_by_macid(void *mlmepriv, u8 mac_id);
-+struct beamformer_entry *rtw_bf_bfer_get_entry_by_addr(PADAPTER, u8 *ra);
-+struct beamformee_entry *rtw_bf_bfee_get_entry_by_addr(PADAPTER, u8 *ra);
-+void rtw_bf_get_ndpa_packet(PADAPTER, union recv_frame *);
-+u32 rtw_bf_get_report_packet(PADAPTER, union recv_frame *);
-+u8 rtw_bf_send_vht_gid_mgnt_packet(PADAPTER, u8 *ra, u8 *gid, u8 *position);
-+void rtw_bf_get_vht_gid_mgnt_packet(PADAPTER, union recv_frame *);
-+void rtw_bf_init(PADAPTER);
-+void rtw_bf_cmd_hdl(PADAPTER, u8 type, u8 *pbuf);
-+u8 rtw_bf_cmd(PADAPTER, s32 type, u8 *pbuf, s32 size, u8 enqueue);
-+void rtw_bf_update_attrib(PADAPTER, struct pkt_attrib *, struct sta_info *);
-+void rtw_bf_c2h_handler(PADAPTER, u8 id, u8 *buf, u8 buf_len);
-+void rtw_bf_update_traffic(PADAPTER);
-+
-+/* Compatible with old function name, only for using outside rtw_beamforming.c */
-+#define beamforming_get_entry_beam_cap_by_mac_id	rtw_bf_bfee_get_entry_cap_by_macid
-+#define rtw_beamforming_get_ndpa_frame			rtw_bf_get_ndpa_packet
-+#define rtw_beamforming_get_report_frame			rtw_bf_get_report_packet
-+#define rtw_beamforming_get_vht_gid_mgnt_frame		rtw_bf_get_vht_gid_mgnt_packet
-+#define beamforming_wk_hdl				rtw_bf_cmd_hdl
-+#define beamforming_wk_cmd				rtw_bf_cmd
-+#define update_attrib_txbf_info				rtw_bf_update_attrib
-+
-+#define HT_BF_CAP(adapter) ((adapter)->mlmepriv.htpriv.beamform_cap)
-+#define VHT_BF_CAP(adapter) ((adapter)->mlmepriv.vhtpriv.beamform_cap)
-+
-+#define IS_HT_BEAMFORMEE(adapter) \
-+		(HT_BF_CAP(adapter) & \
-+		(BEAMFORMING_HT_BEAMFORMEE_ENABLE))
-+
-+#define IS_VHT_BEAMFORMEE(adapter) \
-+		(VHT_BF_CAP(adapter) & \
-+		(BEAMFORMING_VHT_BEAMFORMEE_ENABLE | \
-+		 BEAMFORMING_VHT_MU_MIMO_STA_ENABLE))
-+
-+#define IS_BEAMFORMEE(adapter) (IS_HT_BEAMFORMEE(adapter) | \
-+				IS_VHT_BEAMFORMEE(adapter))
-+
-+#else /* !RTW_BEAMFORMING_VERSION_2 */
-+/*PHYDM_BF - (BEAMFORMING_SUPPORT == 1)*/
-+enum BEAMFORMING_CTRL_TYPE {
-+	BEAMFORMING_CTRL_ENTER = 0,
-+	BEAMFORMING_CTRL_LEAVE = 1,
-+	BEAMFORMING_CTRL_START_PERIOD = 2,
-+	BEAMFORMING_CTRL_END_PERIOD = 3,
-+	BEAMFORMING_CTRL_SOUNDING_FAIL = 4,
-+	BEAMFORMING_CTRL_SOUNDING_CLK = 5,
-+};
-+u32	rtw_beamforming_get_report_frame(PADAPTER	 Adapter, union recv_frame *precv_frame);
-+void	rtw_beamforming_get_ndpa_frame(PADAPTER	 Adapter, union recv_frame *precv_frame);
-+
-+void	beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf);
-+u8	beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue);
-+void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta);
-+
-+#endif /* !RTW_BEAMFORMING_VERSION_2 */
-+
-+#endif /*#ifdef CONFIG_BEAMFORMING */
-+
-+#endif /*__RTW_BEAMFORMING_H_*/
-diff --git a/drivers/staging/rtl8723cs/include/rtw_br_ext.h b/drivers/staging/rtl8723cs/include/rtw_br_ext.h
-new file mode 100644
-index 000000000000..54ba75ea1df5
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_br_ext.h
-@@ -0,0 +1,69 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTW_BR_EXT_H_
-+#define _RTW_BR_EXT_H_
-+
-+#if 1	/* rtw_wifi_driver */
-+#define CL_IPV6_PASS	1
-+#define MACADDRLEN		6
-+#define _DEBUG_ERR		RTW_INFO
-+#define _DEBUG_INFO		/* RTW_INFO */
-+#define DEBUG_WARN		RTW_INFO
-+#define DEBUG_INFO		/* RTW_INFO */
-+#define DEBUG_ERR		RTW_INFO
-+/* #define GET_MY_HWADDR		((GET_MIB(priv))->dot11OperationEntry.hwaddr) */
-+#define GET_MY_HWADDR(padapter)		(adapter_mac_addr(padapter))
-+#endif /* rtw_wifi_driver */
-+
-+#define NAT25_HASH_BITS		4
-+#define NAT25_HASH_SIZE		(1 << NAT25_HASH_BITS)
-+#define NAT25_AGEING_TIME	300
-+
-+#ifdef CL_IPV6_PASS
-+	#define MAX_NETWORK_ADDR_LEN	17
-+#else
-+	#define MAX_NETWORK_ADDR_LEN	11
-+#endif
-+
-+struct nat25_network_db_entry {
-+	struct nat25_network_db_entry	*next_hash;
-+	struct nat25_network_db_entry	**pprev_hash;
-+	atomic_t						use_count;
-+	unsigned char					macAddr[6];
-+	unsigned long					ageing_timer;
-+	unsigned char				networkAddr[MAX_NETWORK_ADDR_LEN];
-+};
-+
-+enum NAT25_METHOD {
-+	NAT25_MIN,
-+	NAT25_CHECK,
-+	NAT25_INSERT,
-+	NAT25_LOOKUP,
-+	NAT25_PARSE,
-+	NAT25_MAX
-+};
-+
-+struct br_ext_info {
-+	unsigned int	nat25_disable;
-+	unsigned int	macclone_enable;
-+	unsigned int	dhcp_bcst_disable;
-+	int		addPPPoETag;		/* 1: Add PPPoE relay-SID, 0: disable */
-+	unsigned char	nat25_dmzMac[MACADDRLEN];
-+	unsigned int	nat25sc_disable;
-+};
-+
-+void nat25_db_cleanup(_adapter *priv);
-+
-+#endif /* _RTW_BR_EXT_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_bt_mp.h b/drivers/staging/rtl8723cs/include/rtw_bt_mp.h
-new file mode 100644
-index 000000000000..93af3c8f068f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_bt_mp.h
-@@ -0,0 +1,288 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __RTW_BT_MP_H
-+#define __RTW_BT_MP_H
-+
-+
-+#if (MP_DRIVER == 1)
-+
-+#pragma pack(1)
-+
-+/* definition for BT_UP_OP_BT_READY */
-+#define	MP_BT_NOT_READY						0
-+#define	MP_BT_READY							1
-+
-+/* definition for BT_UP_OP_BT_SET_MODE */
-+typedef enum _MP_BT_MODE {
-+	MP_BT_MODE_RF_TXRX_TEST_MODE							= 0,
-+	MP_BT_MODE_BT20_DUT_TEST_MODE							= 1,
-+	MP_BT_MODE_BT40_DIRECT_TEST_MODE						= 2,
-+	MP_BT_MODE_CONNECT_TEST_MODE							= 3,
-+	MP_BT_MODE_MAX
-+} MP_BT_MODE, *PMP_BT_MODE;
-+
-+
-+/* definition for BT_UP_OP_BT_SET_TX_RX_PARAMETER */
-+typedef struct _BT_TXRX_PARAMETERS {
-+	u8		txrxChannel;
-+	u32		txrxTxPktCnt;
-+	u8		txrxTxPktInterval;
-+	u8		txrxPayloadType;
-+	u8		txrxPktType;
-+	u16		txrxPayloadLen;
-+	u32		txrxPktHeader;
-+	u8		txrxWhitenCoeff;
-+	u8		txrxBdaddr[6];
-+	u8		txrxTxGainIndex;
-+} BT_TXRX_PARAMETERS, *PBT_TXRX_PARAMETERS;
-+
-+/* txrxPktType */
-+typedef enum _MP_BT_PKT_TYPE {
-+	MP_BT_PKT_DH1							= 0,
-+	MP_BT_PKT_DH3							= 1,
-+	MP_BT_PKT_DH5							= 2,
-+	MP_BT_PKT_2DH1							= 3,
-+	MP_BT_PKT_2DH3							= 4,
-+	MP_BT_PKT_2DH5							= 5,
-+	MP_BT_PKT_3DH1							= 6,
-+	MP_BT_PKT_3DH3							= 7,
-+	MP_BT_PKT_3DH5							= 8,
-+	MP_BT_PKT_LE							= 9,
-+	MP_BT_PKT_MAX
-+} MP_BT_PKT_TYPE, *PMP_BT_PKT_TYPE;
-+/* txrxPayloadType */
-+typedef enum _MP_BT_PAYLOAD_TYPE {
-+	MP_BT_PAYLOAD_01010101					= 0,
-+	MP_BT_PAYLOAD_ALL_1						= 1,
-+	MP_BT_PAYLOAD_ALL_0						= 2,
-+	MP_BT_PAYLOAD_11110000					= 3,
-+	MP_BT_PAYLOAD_PRBS9						= 4,
-+	MP_BT_PAYLOAD_MAX						= 8,
-+} MP_BT_PAYLOAD_TYPE, *PMP_BT_PAYLOAD_TYPE;
-+
-+
-+/* definition for BT_UP_OP_BT_TEST_CTRL */
-+typedef enum _MP_BT_TEST_CTRL {
-+	MP_BT_TEST_STOP_ALL_TESTS						= 0,
-+	MP_BT_TEST_START_RX_TEST						= 1,
-+	MP_BT_TEST_START_PACKET_TX_TEST					= 2,
-+	MP_BT_TEST_START_CONTINUOUS_TX_TEST			= 3,
-+	MP_BT_TEST_START_INQUIRY_SCAN_TEST				= 4,
-+	MP_BT_TEST_START_PAGE_SCAN_TEST					= 5,
-+	MP_BT_TEST_START_INQUIRY_PAGE_SCAN_TEST			= 6,
-+	MP_BT_TEST_START_LEGACY_CONNECT_TEST			= 7,
-+	MP_BT_TEST_START_LE_CONNECT_TEST_INITIATOR		= 8,
-+	MP_BT_TEST_START_LE_CONNECT_TEST_ADVERTISER	= 9,
-+	MP_BT_TEST_MAX
-+} MP_BT_TEST_CTRL, *PMP_BT_TEST_CTRL;
-+
-+
-+typedef enum _RTL_EXT_C2H_EVT {
-+	EXT_C2H_WIFI_FW_ACTIVE_RSP = 0,
-+	EXT_C2H_TRIG_BY_BT_FW = 1,
-+	MAX_EXT_C2HEVENT
-+} RTL_EXT_C2H_EVT;
-+
-+/* OP codes definition between the user layer and driver */
-+typedef enum _BT_CTRL_OPCODE_UPPER {
-+	BT_UP_OP_BT_READY										= 0x00,
-+	BT_UP_OP_BT_SET_MODE									= 0x01,
-+	BT_UP_OP_BT_SET_TX_RX_PARAMETER						= 0x02,
-+	BT_UP_OP_BT_SET_GENERAL								= 0x03,
-+	BT_UP_OP_BT_GET_GENERAL								= 0x04,
-+	BT_UP_OP_BT_TEST_CTRL									= 0x05,
-+	BT_UP_OP_TEST_BT										= 0x06,
-+	BT_UP_OP_MAX
-+} BT_CTRL_OPCODE_UPPER, *PBT_CTRL_OPCODE_UPPER;
-+
-+
-+typedef enum _BT_SET_GENERAL {
-+	BT_GSET_REG											= 0x00,
-+	BT_GSET_RESET											= 0x01,
-+	BT_GSET_TARGET_BD_ADDR									= 0x02,
-+	BT_GSET_TX_PWR_FINETUNE								= 0x03,
-+	BT_SET_TRACKING_INTERVAL								= 0x04,
-+	BT_SET_THERMAL_METER									= 0x05,
-+	BT_ENABLE_CFO_TRACKING									= 0x06,
-+	BT_GSET_UPDATE_BT_PATCH								= 0x07,
-+	BT_GSET_MAX
-+} BT_SET_GENERAL, *PBT_SET_GENERAL;
-+
-+typedef enum _BT_GET_GENERAL {
-+	BT_GGET_REG											= 0x00,
-+	BT_GGET_STATUS											= 0x01,
-+	BT_GGET_REPORT											= 0x02,
-+	BT_GGET_AFH_MAP										= 0x03,
-+	BT_GGET_AFH_STATUS										= 0x04,
-+	BT_GGET_MAX
-+} BT_GET_GENERAL, *PBT_GET_GENERAL;
-+
-+/* definition for BT_UP_OP_BT_SET_GENERAL */
-+typedef enum _BT_REG_TYPE {
-+	BT_REG_RF								= 0,
-+	BT_REG_MODEM							= 1,
-+	BT_REG_BLUEWIZE						= 2,
-+	BT_REG_VENDOR							= 3,
-+	BT_REG_LE								= 4,
-+	BT_REG_MAX
-+} BT_REG_TYPE, *PBT_REG_TYPE;
-+
-+/* definition for BT_LO_OP_GET_AFH_MAP */
-+typedef enum _BT_AFH_MAP_TYPE {
-+	BT_AFH_MAP_RESULT						= 0,
-+	BT_AFH_MAP_WIFI_PSD_ONLY				= 1,
-+	BT_AFH_MAP_WIFI_CH_BW_ONLY				= 2,
-+	BT_AFH_MAP_BT_PSD_ONLY					= 3,
-+	BT_AFH_MAP_HOST_CLASSIFICATION_ONLY	= 4,
-+	BT_AFH_MAP_MAX
-+} BT_AFH_MAP_TYPE, *PBT_AFH_MAP_TYPE;
-+
-+/* definition for BT_UP_OP_BT_GET_GENERAL */
-+typedef enum _BT_REPORT_TYPE {
-+	BT_REPORT_RX_PACKET_CNT				= 0,
-+	BT_REPORT_RX_ERROR_BITS				= 1,
-+	BT_REPORT_RSSI							= 2,
-+	BT_REPORT_CFO_HDR_QUALITY				= 3,
-+	BT_REPORT_CONNECT_TARGET_BD_ADDR		= 4,
-+	BT_REPORT_MAX
-+} BT_REPORT_TYPE, *PBT_REPORT_TYPE;
-+
-+void
-+MPTBT_Test(
-+		PADAPTER	Adapter,
-+		u8		opCode,
-+		u8		byte1,
-+		u8		byte2,
-+		u8		byte3
-+);
-+
-+uint
-+MPTBT_SendOidBT(
-+		PADAPTER		pAdapter,
-+		void				*InformationBuffer,
-+		u32				InformationBufferLength,
-+		u32 				*BytesRead,
-+		u32 				*BytesNeeded
-+);
-+
-+void
-+MPTBT_FwC2hBtMpCtrl(
-+	PADAPTER	Adapter,
-+	u8 			*tmpBuf,
-+	u8			length
-+);
-+
-+void MPh2c_timeout_handle(void *FunctionContext);
-+
-+void mptbt_BtControlProcess(
-+	PADAPTER	Adapter,
-+	void			*pInBuf
-+);
-+
-+#define	BT_H2C_MAX_RETRY								1
-+#define	BT_MAX_C2H_LEN								20
-+
-+typedef struct _BT_REQ_CMD {
-+	u8       opCodeVer;
-+	u8       OpCode;
-+	u16      paraLength;
-+	u8       pParamStart[100];
-+} BT_REQ_CMD, *PBT_REQ_CMD;
-+
-+typedef struct _BT_RSP_CMD {
-+	u16      status;
-+	u16      paraLength;
-+	u8       pParamStart[100];
-+} BT_RSP_CMD, *PBT_RSP_CMD;
-+
-+
-+typedef struct _BT_H2C {
-+	u8	opCodeVer:4;
-+	u8	reqNum:4;
-+	u8	opCode;
-+	u8	buf[100];
-+} BT_H2C, *PBT_H2C;
-+
-+
-+
-+typedef struct _BT_EXT_C2H {
-+	u8	extendId;
-+	u8	statusCode:4;
-+	u8	retLen:4;
-+	u8	opCodeVer:4;
-+	u8	reqNum:4;
-+	u8	buf[100];
-+} BT_EXT_C2H, *PBT_EXT_C2H;
-+
-+
-+typedef enum _BT_OPCODE_STATUS {
-+	BT_OP_STATUS_SUCCESS									= 0x00, /* Success */
-+	BT_OP_STATUS_VERSION_MISMATCH							= 0x01,
-+	BT_OP_STATUS_UNKNOWN_OPCODE								= 0x02,
-+	BT_OP_STATUS_ERROR_PARAMETER							= 0x03,
-+	BT_OP_STATUS_MAX
-+} BT_OPCODE_STATUS, *PBT_OPCODE_STATUS;
-+
-+
-+
-+/* OP codes definition between driver and bt fw */
-+typedef enum _BT_CTRL_OPCODE_LOWER {
-+	BT_LO_OP_GET_BT_VERSION									= 0x00,
-+	BT_LO_OP_RESET												= 0x01,
-+	BT_LO_OP_TEST_CTRL											= 0x02,
-+	BT_LO_OP_SET_BT_MODE										= 0x03,
-+	BT_LO_OP_SET_CHNL_TX_GAIN									= 0x04,
-+	BT_LO_OP_SET_PKT_TYPE_LEN									= 0x05,
-+	BT_LO_OP_SET_PKT_CNT_L_PL_TYPE								= 0x06,
-+	BT_LO_OP_SET_PKT_CNT_H_PKT_INTV							= 0x07,
-+	BT_LO_OP_SET_PKT_HEADER									= 0x08,
-+	BT_LO_OP_SET_WHITENCOEFF									= 0x09,
-+	BT_LO_OP_SET_BD_ADDR_L										= 0x0a,
-+	BT_LO_OP_SET_BD_ADDR_H										= 0x0b,
-+	BT_LO_OP_WRITE_REG_ADDR									= 0x0c,
-+	BT_LO_OP_WRITE_REG_VALUE									= 0x0d,
-+	BT_LO_OP_GET_BT_STATUS										= 0x0e,
-+	BT_LO_OP_GET_BD_ADDR_L										= 0x0f,
-+	BT_LO_OP_GET_BD_ADDR_H										= 0x10,
-+	BT_LO_OP_READ_REG											= 0x11,
-+	BT_LO_OP_SET_TARGET_BD_ADDR_L								= 0x12,
-+	BT_LO_OP_SET_TARGET_BD_ADDR_H								= 0x13,
-+	BT_LO_OP_SET_TX_POWER_CALIBRATION							= 0x14,
-+	BT_LO_OP_GET_RX_PKT_CNT_L									= 0x15,
-+	BT_LO_OP_GET_RX_PKT_CNT_H									= 0x16,
-+	BT_LO_OP_GET_RX_ERROR_BITS_L								= 0x17,
-+	BT_LO_OP_GET_RX_ERROR_BITS_H								= 0x18,
-+	BT_LO_OP_GET_RSSI											= 0x19,
-+	BT_LO_OP_GET_CFO_HDR_QUALITY_L								= 0x1a,
-+	BT_LO_OP_GET_CFO_HDR_QUALITY_H								= 0x1b,
-+	BT_LO_OP_GET_TARGET_BD_ADDR_L								= 0x1c,
-+	BT_LO_OP_GET_TARGET_BD_ADDR_H								= 0x1d,
-+	BT_LO_OP_GET_AFH_MAP_L										= 0x1e,
-+	BT_LO_OP_GET_AFH_MAP_M										= 0x1f,
-+	BT_LO_OP_GET_AFH_MAP_H										= 0x20,
-+	BT_LO_OP_GET_AFH_STATUS									= 0x21,
-+	BT_LO_OP_SET_TRACKING_INTERVAL								= 0x22,
-+	BT_LO_OP_SET_THERMAL_METER									= 0x23,
-+	BT_LO_OP_ENABLE_CFO_TRACKING								= 0x24,
-+	BT_LO_OP_MAX
-+} BT_CTRL_OPCODE_LOWER, *PBT_CTRL_OPCODE_LOWER;
-+
-+
-+
-+
-+#endif  /* #if(MP_DRIVER == 1) */
-+
-+#endif /*  #ifndef __INC_MPT_BT_H */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_btcoex.h b/drivers/staging/rtl8723cs/include/rtw_btcoex.h
-new file mode 100644
-index 000000000000..3361dbef8d94
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_btcoex.h
-@@ -0,0 +1,468 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifdef CONFIG_BT_COEXIST
-+
-+#ifndef __RTW_BTCOEX_H__
-+#define __RTW_BTCOEX_H__
-+
-+#include <drv_types.h>
-+
-+/* For H2C: H2C_BT_MP_OPER. Return status definition to the user layer */
-+typedef enum _BT_CTRL_STATUS {
-+	BT_STATUS_SUCCESS								= 0x00, /* Success */
-+	BT_STATUS_BT_OP_SUCCESS							= 0x01, /* bt fw op execution success */
-+	BT_STATUS_H2C_SUCCESS							= 0x02, /* H2c success */
-+	BT_STATUS_H2C_FAIL								= 0x03, /* H2c fail */
-+	BT_STATUS_H2C_LENGTH_EXCEEDED					= 0x04, /* H2c command length exceeded */
-+	BT_STATUS_H2C_TIMTOUT							= 0x05, /* H2c timeout */
-+	BT_STATUS_H2C_BT_NO_RSP							= 0x06, /* H2c sent, bt no rsp */
-+	BT_STATUS_C2H_SUCCESS							= 0x07, /* C2h success */
-+	BT_STATUS_C2H_REQNUM_MISMATCH					= 0x08, /* bt fw wrong rsp */
-+	BT_STATUS_OPCODE_U_VERSION_MISMATCH				= 0x08, /* Upper layer OP code version mismatch. */
-+	BT_STATUS_OPCODE_L_VERSION_MISMATCH				= 0x0a, /* Lower layer OP code version mismatch. */
-+	BT_STATUS_UNKNOWN_OPCODE_U						= 0x0b, /* Unknown Upper layer OP code */
-+	BT_STATUS_UNKNOWN_OPCODE_L						= 0x0c, /* Unknown Lower layer OP code */
-+	BT_STATUS_PARAMETER_FORMAT_ERROR_U				= 0x0d, /* Wrong parameters sent by upper layer. */
-+	BT_STATUS_PARAMETER_FORMAT_ERROR_L				= 0x0e, /* bt fw parameter format is not consistency */
-+	BT_STATUS_PARAMETER_OUT_OF_RANGE_U				= 0x0f, /* uppery layer parameter value is out of range */
-+	BT_STATUS_PARAMETER_OUT_OF_RANGE_L				= 0x10, /* bt fw parameter value is out of range */
-+	BT_STATUS_UNKNOWN_STATUS_L						= 0x11, /* bt returned an defined status code */
-+	BT_STATUS_UNKNOWN_STATUS_H						= 0x12, /* driver need to do error handle or not handle-well. */
-+	BT_STATUS_WRONG_LEVEL							= 0x13, /* should be under passive level */
-+	BT_STATUS_NOT_IMPLEMENT						= 0x14, /* op code not implemented yet */
-+	BT_STATUS_BT_STACK_OP_SUCCESS					= 0x15, /* bt stack op execution success */
-+	BT_STATUS_BT_STACK_NOT_SUPPORT					= 0x16, /* stack version not support this. */
-+	BT_STATUS_BT_STACK_SEND_HCI_EVENT_FAIL			= 0x17, /* send hci event fail */
-+	BT_STATUS_BT_STACK_NOT_BIND						= 0x18, /* stack not bind wifi driver */
-+	BT_STATUS_BT_STACK_NO_RSP						= 0x19, /* stack doesn't have any rsp. */
-+	BT_STATUS_MAX
-+} BT_CTRL_STATUS, *PBT_CTRL_STATUS;
-+
-+typedef enum _BTCOEX_SUSPEND_STATE {
-+	BTCOEX_SUSPEND_STATE_RESUME					= 0x0,
-+	BTCOEX_SUSPEND_STATE_SUSPEND				= 0x1,
-+	BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT		= 0x2,
-+	BTCOEX_SUSPEND_STATE_MAX
-+} BTCOEX_SUSPEND_STATE, *PBTCOEX_SUSPEND_STATE;
-+
-+typedef enum _BTCOEX_POLICY_CONTROL {
-+	BTCOEX_POLICY_CONTROL_AUTO,
-+	BTCOEX_POLICY_CONTROL_FORCE_FREERUN,
-+	BTCOEX_POLICY_CONTROL_FORCE_TDMA
-+} BTCOEX_POLICY_CONTROL, *PBTCOEX_POLICY_CONTROL;
-+
-+#define SET_BT_MP_OPER_RET(OpCode, StatusCode)						((OpCode << 8) | StatusCode)
-+#define GET_OP_CODE_FROM_BT_MP_OPER_RET(RetCode)					((RetCode & 0xF0) >> 8)
-+#define GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode)				(RetCode & 0x0F)
-+#define CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode, StatusCode)	(GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode) == StatusCode)
-+
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+
-+#define NETLINK_USER 31
-+#define CONNECT_PORT 30000
-+#define CONNECT_PORT_BT 30001
-+#define KERNEL_SOCKET_OK 0x01
-+#define NETLINK_SOCKET_OK 0x02
-+
-+#define OTHER 0
-+#define RX_ATTEND_ACK 1
-+#define RX_LEAVE_ACK 2
-+#define RX_BT_LEAVE 3
-+#define RX_INVITE_REQ 4
-+#define RX_ATTEND_REQ 5
-+#define RX_INVITE_RSP 6
-+
-+#define invite_req "INVITE_REQ"
-+#define invite_rsp "INVITE_RSP"
-+#define attend_req "ATTEND_REQ"
-+#define attend_ack "ATTEND_ACK"
-+#define wifi_leave "WIFI_LEAVE"
-+#define leave_ack "LEAVE_ACK"
-+#define bt_leave "BT_LEAVE"
-+
-+#define BT_INFO_NOTIFY_CMD 0x0106
-+#define BT_INFO_LEN 8
-+
-+typedef struct _HCI_LINK_INFO {
-+	u16					ConnectHandle;
-+	u8					IncomingTrafficMode;
-+	u8					OutgoingTrafficMode;
-+	u8					BTProfile;
-+	u8					BTCoreSpec;
-+	s8					BT_RSSI;
-+	u8					TrafficProfile;
-+	u8					linkRole;
-+} HCI_LINK_INFO, *PHCI_LINK_INFO;
-+
-+#define	MAX_BT_ACL_LINK_NUM				8
-+
-+typedef struct _HCI_EXT_CONFIG {
-+	HCI_LINK_INFO				aclLink[MAX_BT_ACL_LINK_NUM];
-+	u8					btOperationCode;
-+	u16					CurrentConnectHandle;
-+	u8					CurrentIncomingTrafficMode;
-+	u8					CurrentOutgoingTrafficMode;
-+
-+	u8					NumberOfACL;
-+	u8					NumberOfSCO;
-+	u8					CurrentBTStatus;
-+	u16					HCIExtensionVer;
-+
-+	BOOLEAN					bEnableWifiScanNotify;
-+} HCI_EXT_CONFIG, *PHCI_EXT_CONFIG;
-+
-+typedef struct _HCI_PHY_LINK_BSS_INFO {
-+	u16						bdCap;			/* capability information */
-+
-+	/* Qos related. Added by Annie, 2005-11-01. */
-+	/* BSS_QOS						BssQos;		 */
-+
-+} HCI_PHY_LINK_BSS_INFO, *PHCI_PHY_LINK_BSS_INFO;
-+
-+typedef enum _BT_CONNECT_TYPE {
-+	BT_CONNECT_AUTH_REQ								= 0x00,
-+	BT_CONNECT_AUTH_RSP								= 0x01,
-+	BT_CONNECT_ASOC_REQ								= 0x02,
-+	BT_CONNECT_ASOC_RSP								= 0x03,
-+	BT_DISCONNECT										= 0x04
-+} BT_CONNECT_TYPE, *PBT_CONNECT_TYPE;
-+
-+
-+typedef struct _PACKET_IRP_HCIEVENT_DATA {
-+	u8		EventCode;
-+	u8		Length; /* total cmd length = extension event length+1(extension event code length) */
-+	u8		Data[1]; /* byte1 is extension event code */
-+} rtw_HCI_event;
-+
-+
-+struct btinfo_8761ATV {
-+	u8 cid;
-+	u8 len;
-+
-+	u8 bConnection:1;
-+	u8 bSCOeSCO:1;
-+	u8 bInQPage:1;
-+	u8 bACLBusy:1;
-+	u8 bSCOBusy:1;
-+	u8 bHID:1;
-+	u8 bA2DP:1;
-+	u8 bFTP:1;
-+
-+	u8 retry_cnt:4;
-+	u8 rsvd_34:1;
-+	u8 bPage:1;
-+	u8 TRxMask:1;
-+	u8 Sniff_attempt:1;
-+
-+	u8 rssi;
-+
-+	u8 A2dp_rate:1;
-+	u8 ReInit:1;
-+	u8 MaxPower:1;
-+	u8 bEnIgnoreWlanAct:1;
-+	u8 TxPowerLow:1;
-+	u8 TxPowerHigh:1;
-+	u8 eSCO_SCO:1;
-+	u8 Master_Slave:1;
-+
-+	u8 ACL_TRx_TP_low;
-+	u8 ACL_TRx_TP_high;
-+};
-+
-+#define HCIOPCODE(_OCF, _OGF)     ((_OGF)<<10|(_OCF))
-+#define HCIOPCODELOW(_OCF, _OGF)	(u8)(HCIOPCODE(_OCF, _OGF) & 0x00ff)
-+#define HCIOPCODEHIGHT(_OCF, _OGF) (u8)(HCIOPCODE(_OCF, _OGF)>>8)
-+#define HCI_OGF(opCode)  (unsigned char)((0xFC00 & (opCode)) >> 10)
-+#define HCI_OCF(opCode)  (0x3FF & (opCode))
-+
-+
-+typedef enum _HCI_STATUS {
-+	HCI_STATUS_SUCCESS										= 0x00, /* Success */
-+	HCI_STATUS_UNKNOW_HCI_CMD								= 0x01, /* Unknown HCI Command */
-+	HCI_STATUS_UNKNOW_CONNECT_ID							= 0X02, /* Unknown Connection Identifier */
-+	HCI_STATUS_HW_FAIL										= 0X03, /* Hardware Failure */
-+	HCI_STATUS_PAGE_TIMEOUT									= 0X04, /* Page Timeout */
-+	HCI_STATUS_AUTH_FAIL										= 0X05, /* Authentication Failure */
-+	HCI_STATUS_PIN_OR_KEY_MISSING							= 0X06, /* PIN or Key Missing */
-+	HCI_STATUS_MEM_CAP_EXCEED								= 0X07, /* Memory Capacity Exceeded */
-+	HCI_STATUS_CONNECT_TIMEOUT								= 0X08, /* Connection Timeout */
-+	HCI_STATUS_CONNECT_LIMIT									= 0X09, /* Connection Limit Exceeded */
-+	HCI_STATUS_SYN_CONNECT_LIMIT								= 0X0a, /* Synchronous Connection Limit To A Device Exceeded */
-+	HCI_STATUS_ACL_CONNECT_EXISTS							= 0X0b, /* ACL Connection Already Exists */
-+	HCI_STATUS_CMD_DISALLOW									= 0X0c, /* Command Disallowed */
-+	HCI_STATUS_CONNECT_RJT_LIMIT_RESOURCE					= 0X0d, /* Connection Rejected due to Limited Resources */
-+	HCI_STATUS_CONNECT_RJT_SEC_REASON						= 0X0e, /* Connection Rejected Due To Security Reasons */
-+	HCI_STATUS_CONNECT_RJT_UNACCEPT_BD_ADDR				= 0X0f, /* Connection Rejected due to Unacceptable BD_ADDR */
-+	HCI_STATUS_CONNECT_ACCEPT_TIMEOUT						= 0X10, /* Connection Accept Timeout Exceeded */
-+	HCI_STATUS_UNSUPPORT_FEATURE_PARA_VALUE				= 0X11, /* Unsupported Feature or Parameter Value */
-+	HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE					= 0X12, /* Invalid HCI Command Parameters */
-+	HCI_STATUS_REMOTE_USER_TERMINATE_CONNECT				= 0X13, /* Remote User Terminated Connection */
-+	HCI_STATUS_REMOTE_DEV_TERMINATE_LOW_RESOURCE			= 0X14, /* Remote Device Terminated Connection due to Low Resources */
-+	HCI_STATUS_REMOTE_DEV_TERMINATE_CONNECT_POWER_OFF	= 0X15, /* Remote Device Terminated Connection due to Power Off */
-+	HCI_STATUS_CONNECT_TERMINATE_LOCAL_HOST				= 0X16, /* Connection Terminated By Local Host */
-+	HCI_STATUS_REPEATE_ATTEMPT								= 0X17, /* Repeated Attempts */
-+	HCI_STATUS_PAIR_NOT_ALLOW								= 0X18, /* Pairing Not Allowed */
-+	HCI_STATUS_UNKNOW_LMP_PDU								= 0X19, /* Unknown LMP PDU */
-+	HCI_STATUS_UNSUPPORT_REMOTE_LMP_FEATURE				= 0X1a, /* Unsupported Remote Feature / Unsupported LMP Feature */
-+	HCI_STATUS_SOC_OFFSET_REJECT								= 0X1b, /* SCO Offset Rejected */
-+	HCI_STATUS_SOC_INTERVAL_REJECT							= 0X1c, /* SCO Interval Rejected */
-+	HCI_STATUS_SOC_AIR_MODE_REJECT							= 0X1d, /* SCO Air Mode Rejected */
-+	HCI_STATUS_INVALID_LMP_PARA								= 0X1e, /* Invalid LMP Parameters */
-+	HCI_STATUS_UNSPECIFIC_ERROR								= 0X1f, /* Unspecified Error */
-+	HCI_STATUS_UNSUPPORT_LMP_PARA_VALUE					= 0X20, /* Unsupported LMP Parameter Value */
-+	HCI_STATUS_ROLE_CHANGE_NOT_ALLOW						= 0X21, /* Role Change Not Allowed */
-+	HCI_STATUS_LMP_RESPONSE_TIMEOUT							= 0X22, /* LMP Response Timeout */
-+	HCI_STATUS_LMP_ERROR_TRANSACTION_COLLISION				= 0X23, /* LMP Error Transaction Collision */
-+	HCI_STATUS_LMP_PDU_NOT_ALLOW							= 0X24, /* LMP PDU Not Allowed */
-+	HCI_STATUS_ENCRYPTION_MODE_NOT_ALLOW					= 0X25, /* Encryption Mode Not Acceptable */
-+	HCI_STATUS_LINK_KEY_CAN_NOT_CHANGE						= 0X26, /* Link Key Can Not be Changed */
-+	HCI_STATUS_REQUEST_QOS_NOT_SUPPORT						= 0X27, /* Requested QoS Not Supported */
-+	HCI_STATUS_INSTANT_PASSED								= 0X28, /* Instant Passed */
-+	HCI_STATUS_PAIRING_UNIT_KEY_NOT_SUPPORT					= 0X29, /* Pairing With Unit Key Not Supported */
-+	HCI_STATUS_DIFFERENT_TRANSACTION_COLLISION				= 0X2a, /* Different Transaction Collision */
-+	HCI_STATUS_RESERVE_1										= 0X2b, /* Reserved */
-+	HCI_STATUS_QOS_UNACCEPT_PARA							= 0X2c, /* QoS Unacceptable Parameter */
-+	HCI_STATUS_QOS_REJECT										= 0X2d, /* QoS Rejected */
-+	HCI_STATUS_CHNL_CLASSIFICATION_NOT_SUPPORT				= 0X2e, /* Channel Classification Not Supported */
-+	HCI_STATUS_INSUFFICIENT_SECURITY							= 0X2f, /* Insufficient Security */
-+	HCI_STATUS_PARA_OUT_OF_RANGE							= 0x30, /* Parameter Out Of Mandatory Range */
-+	HCI_STATUS_RESERVE_2										= 0X31, /* Reserved */
-+	HCI_STATUS_ROLE_SWITCH_PENDING							= 0X32, /* Role Switch Pending */
-+	HCI_STATUS_RESERVE_3										= 0X33, /* Reserved */
-+	HCI_STATUS_RESERVE_SOLT_VIOLATION						= 0X34, /* Reserved Slot Violation */
-+	HCI_STATUS_ROLE_SWITCH_FAIL								= 0X35, /* Role Switch Failed */
-+	HCI_STATUS_EXTEND_INQUIRY_RSP_TOO_LARGE				= 0X36, /* Extended Inquiry Response Too Large */
-+	HCI_STATUS_SEC_SIMPLE_PAIRING_NOT_SUPPORT				= 0X37, /* Secure Simple Pairing Not Supported By Host. */
-+	HCI_STATUS_HOST_BUSY_PAIRING								= 0X38, /* Host Busy - Pairing */
-+	HCI_STATUS_CONNECT_REJ_NOT_SUIT_CHNL_FOUND			= 0X39, /* Connection Rejected due to No Suitable Channel Found */
-+	HCI_STATUS_CONTROLLER_BUSY								= 0X3a /* CONTROLLER BUSY */
-+} RTW_HCI_STATUS;
-+
-+#define HCI_EVENT_COMMAND_COMPLETE					0x0e
-+
-+#define OGF_EXTENSION									0X3f
-+typedef enum HCI_EXTENSION_COMMANDS {
-+	HCI_SET_ACL_LINK_DATA_FLOW_MODE				= 0x0010,
-+	HCI_SET_ACL_LINK_STATUS							= 0x0020,
-+	HCI_SET_SCO_LINK_STATUS							= 0x0030,
-+	HCI_SET_RSSI_VALUE								= 0x0040,
-+	HCI_SET_CURRENT_BLUETOOTH_STATUS				= 0x0041,
-+
-+	/* The following is for RTK8723 */
-+	HCI_EXTENSION_VERSION_NOTIFY					= 0x0100,
-+	HCI_LINK_STATUS_NOTIFY							= 0x0101,
-+	HCI_BT_OPERATION_NOTIFY							= 0x0102,
-+	HCI_ENABLE_WIFI_SCAN_NOTIFY						= 0x0103,
-+	HCI_QUERY_RF_STATUS								= 0x0104,
-+	HCI_BT_ABNORMAL_NOTIFY							= 0x0105,
-+	HCI_BT_INFO_NOTIFY								= 0x0106,
-+	HCI_BT_COEX_NOTIFY								= 0x0107,
-+	HCI_BT_PATCH_VERSION_NOTIFY						= 0x0108,
-+	HCI_BT_AFH_MAP_NOTIFY							= 0x0109,
-+	HCI_BT_REGISTER_VALUE_NOTIFY					= 0x010a,
-+
-+	/* The following is for IVT */
-+	HCI_WIFI_CURRENT_CHANNEL						= 0x0300,
-+	HCI_WIFI_CURRENT_BANDWIDTH						= 0x0301,
-+	HCI_WIFI_CONNECTION_STATUS						= 0x0302
-+} RTW_HCI_EXT_CMD;
-+
-+#define HCI_EVENT_EXTENSION_RTK						0xfe
-+typedef enum HCI_EXTENSION_EVENT_RTK {
-+	HCI_EVENT_EXT_WIFI_SCAN_NOTIFY								= 0x01,
-+	HCI_EVENT_EXT_WIFI_RF_STATUS_NOTIFY						= 0x02,
-+	HCI_EVENT_EXT_BT_INFO_CONTROL								= 0x03,
-+	HCI_EVENT_EXT_BT_COEX_CONTROL								= 0x04
-+} RTW_HCI_EXT_EVENT;
-+
-+typedef enum _BT_TRAFFIC_MODE {
-+	BT_MOTOR_EXT_BE		= 0x00, /* Best Effort. Default. for HCRP, PAN, SDP, RFCOMM-based profiles like FTP,OPP, SPP, DUN, etc. */
-+	BT_MOTOR_EXT_GUL		= 0x01, /* Guaranteed Latency. This type of traffic is used e.g. for HID and AVRCP. */
-+	BT_MOTOR_EXT_GUB		= 0X02, /* Guaranteed Bandwidth. */
-+	BT_MOTOR_EXT_GULB	= 0X03  /* Guaranteed Latency and Bandwidth. for A2DP and VDP. */
-+} BT_TRAFFIC_MODE;
-+
-+typedef enum _BT_TRAFFIC_MODE_PROFILE {
-+	BT_PROFILE_NONE,
-+	BT_PROFILE_A2DP,
-+	BT_PROFILE_PAN	,
-+	BT_PROFILE_HID,
-+	BT_PROFILE_SCO
-+} BT_TRAFFIC_MODE_PROFILE;
-+
-+typedef enum _HCI_EXT_BT_OPERATION {
-+	HCI_BT_OP_NONE				= 0x0,
-+	HCI_BT_OP_INQUIRY_START		= 0x1,
-+	HCI_BT_OP_INQUIRY_FINISH		= 0x2,
-+	HCI_BT_OP_PAGING_START		= 0x3,
-+	HCI_BT_OP_PAGING_SUCCESS		= 0x4,
-+	HCI_BT_OP_PAGING_UNSUCCESS	= 0x5,
-+	HCI_BT_OP_PAIRING_START		= 0x6,
-+	HCI_BT_OP_PAIRING_FINISH		= 0x7,
-+	HCI_BT_OP_BT_DEV_ENABLE		= 0x8,
-+	HCI_BT_OP_BT_DEV_DISABLE		= 0x9,
-+	HCI_BT_OP_MAX
-+} HCI_EXT_BT_OPERATION, *PHCI_EXT_BT_OPERATION;
-+
-+typedef struct _BT_MGNT {
-+	BOOLEAN				bBTConnectInProgress;
-+	BOOLEAN				bLogLinkInProgress;
-+	BOOLEAN				bPhyLinkInProgress;
-+	BOOLEAN				bPhyLinkInProgressStartLL;
-+	u8				BtCurrentPhyLinkhandle;
-+	u16				BtCurrentLogLinkhandle;
-+	u8				CurrentConnectEntryNum;
-+	u8				DisconnectEntryNum;
-+	u8				CurrentBTConnectionCnt;
-+	BT_CONNECT_TYPE		BTCurrentConnectType;
-+	BT_CONNECT_TYPE		BTReceiveConnectPkt;
-+	u8				BTAuthCount;
-+	u8				BTAsocCount;
-+	BOOLEAN				bStartSendSupervisionPkt;
-+	BOOLEAN				BtOperationOn;
-+	BOOLEAN				BTNeedAMPStatusChg;
-+	BOOLEAN				JoinerNeedSendAuth;
-+	HCI_PHY_LINK_BSS_INFO	bssDesc;
-+	HCI_EXT_CONFIG		ExtConfig;
-+	BOOLEAN				bNeedNotifyAMPNoCap;
-+	BOOLEAN				bCreateSpportQos;
-+	BOOLEAN				bSupportProfile;
-+	u8				BTChannel;
-+	BOOLEAN				CheckChnlIsSuit;
-+	BOOLEAN				bBtScan;
-+	BOOLEAN				btLogoTest;
-+	BOOLEAN				bRfStatusNotified;
-+	BOOLEAN				bBtRsvedPageDownload;
-+} BT_MGNT, *PBT_MGNT;
-+
-+struct bt_coex_info {
-+	/* For Kernel Socket */
-+	struct socket *udpsock;
-+	struct sockaddr_in wifi_sockaddr; /*wifi socket*/
-+	struct sockaddr_in bt_sockaddr;/* BT socket */
-+	struct sock *sk_store;/*back up socket for UDP RX int*/
-+
-+	/* store which socket is OK */
-+	u8 sock_open;
-+
-+	u8 BT_attend;
-+	u8 is_exist; /* socket exist */
-+	BT_MGNT BtMgnt;
-+	struct workqueue_struct *btcoex_wq;
-+	struct delayed_work recvmsg_work;
-+};
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+
-+#define	PACKET_NORMAL			0
-+#define	PACKET_DHCP				1
-+#define	PACKET_ARP				2
-+#define	PACKET_EAPOL			3
-+
-+void rtw_btcoex_Initialize(PADAPTER);
-+void rtw_btcoex_PowerOnSetting(PADAPTER padapter);
-+void rtw_btcoex_AntInfoSetting(PADAPTER padapter);
-+void rtw_btcoex_PowerOffSetting(PADAPTER padapter);
-+void rtw_btcoex_PreLoadFirmware(PADAPTER padapter);
-+void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly);
-+void rtw_btcoex_IpsNotify(PADAPTER, u8 type);
-+void rtw_btcoex_LpsNotify(PADAPTER, u8 type);
-+void rtw_btcoex_ScanNotify(PADAPTER, u8 type);
-+void rtw_btcoex_MediaStatusNotify(PADAPTER, u8 mediaStatus);
-+void rtw_btcoex_SpecialPacketNotify(PADAPTER, u8 pktType);
-+void rtw_btcoex_IQKNotify(PADAPTER padapter, u8 state);
-+void rtw_btcoex_WLRFKNotify(PADAPTER padapter, u8 path, u8 type, u8 state);
-+void rtw_btcoex_BtInfoNotify(PADAPTER, u8 length, u8 *tmpBuf);
-+void rtw_btcoex_BtMpRptNotify(PADAPTER, u8 length, u8 *tmpBuf);
-+void rtw_btcoex_SuspendNotify(PADAPTER, u8 state);
-+void rtw_btcoex_HaltNotify(PADAPTER);
-+void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type);
-+void rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length);
-+void rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id);
-+void rtw_btcoex_SwitchBtTRxMask(PADAPTER);
-+void rtw_btcoex_Switch(PADAPTER, u8 enable);
-+u8 rtw_btcoex_IsBtDisabled(PADAPTER);
-+void rtw_btcoex_Handler(PADAPTER);
-+s32 rtw_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter);
-+s32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER);
-+u32 rtw_btcoex_GetAMPDUSize(PADAPTER);
-+void rtw_btcoex_SetManualControl(PADAPTER, u8 bmanual);
-+void rtw_btcoex_set_policy_control(PADAPTER, u8 btc_policy);
-+u8 rtw_btcoex_1Ant(PADAPTER);
-+u8 rtw_btcoex_IsBtControlLps(PADAPTER);
-+u8 rtw_btcoex_IsLpsOn(PADAPTER);
-+u8 rtw_btcoex_RpwmVal(PADAPTER);
-+u8 rtw_btcoex_LpsVal(PADAPTER);
-+u32 rtw_btcoex_GetRaMask(PADAPTER);
-+u8 rtw_btcoex_query_reduced_wl_pwr_lvl(PADAPTER padapter);
-+void rtw_btcoex_set_reduced_wl_pwr_lvl(PADAPTER padapter, u8 val);
-+void rtw_btcoex_do_reduce_wl_pwr_lvl(PADAPTER padapter);
-+void rtw_btcoex_RecordPwrMode(PADAPTER, u8 *pCmdBuf, u8 cmdLen);
-+void rtw_btcoex_DisplayBtCoexInfo(PADAPTER, u8 *pbuf, u32 bufsize);
-+void rtw_btcoex_SetDBG(PADAPTER, u32 *pDbgModule);
-+u32 rtw_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize);
-+u8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER);
-+u8 rtw_btcoex_IsBtLinkExist(PADAPTER);
-+void rtw_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON);
-+
-+#ifdef CONFIG_RF4CE_COEXIST
-+void rtw_btcoex_SetRf4ceLinkState(PADAPTER padapter, u8 state);
-+u8 rtw_btcoex_GetRf4ceLinkState(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+void rtw_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer);
-+void rtw_btcoex_SetHciVersion(PADAPTER  padapter, u16 hciVersion);
-+void rtw_btcoex_StackUpdateProfileInfo(void);
-+void rtw_btcoex_init_socket(_adapter *padapter);
-+void rtw_btcoex_close_socket(_adapter *padapter);
-+void rtw_btcoex_dump_tx_msg(u8 *tx_msg, u8 len, u8 *msg_name);
-+u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool force);
-+u8 rtw_btcoex_create_kernel_socket(_adapter *padapter);
-+void rtw_btcoex_close_kernel_socket(_adapter *padapter);
-+void rtw_btcoex_recvmsgbysocket(void *data);
-+u16 rtw_btcoex_parse_recv_data(u8 *msg, u8 msg_size);
-+u8 rtw_btcoex_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length);
-+void rtw_btcoex_parse_hci_cmd(_adapter *padapter, u8 *cmd, u16 len);
-+void rtw_btcoex_SendEventExtBtCoexControl(PADAPTER Adapter, u8 bNeedDbgRsp, u8 dataLen, void *pData);
-+void rtw_btcoex_SendEventExtBtInfoControl(PADAPTER Adapter, u8 dataLen, void *pData);
-+void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType);
-+#define BT_SendEventExtBtCoexControl(Adapter, bNeedDbgRsp, dataLen, pData) rtw_btcoex_SendEventExtBtCoexControl(Adapter, bNeedDbgRsp, dataLen, pData)
-+#define BT_SendEventExtBtInfoControl(Adapter, dataLen, pData) rtw_btcoex_SendEventExtBtInfoControl(Adapter, dataLen, pData)
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+u16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data);
-+u16 rtw_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val);
-+u8 rtw_btcoex_get_reduce_wl_txpwr(PADAPTER padapter);
-+u8 rtw_btcoex_get_bt_coexist(PADAPTER padapter);
-+u8 rtw_btcoex_get_chip_type(PADAPTER padapter);
-+u8 rtw_btcoex_get_pg_ant_num(PADAPTER padapter);
-+u8 rtw_btcoex_get_pg_single_ant_path(PADAPTER padapter);
-+u8 rtw_btcoex_get_pg_rfe_type(PADAPTER padapter);
-+u8 rtw_btcoex_is_tfbga_package_type(PADAPTER padapter);
-+u8 rtw_btcoex_get_ant_div_cfg(PADAPTER padapter);
-+u16 rtw_btcoex_btset_testmode(PADAPTER padapter, u8 type);
-+
-+/* ==================================================
-+ * Below Functions are called by BT-Coex
-+ * ================================================== */
-+void rtw_btcoex_rx_ampdu_apply(PADAPTER padapter);
-+void rtw_btcoex_LPS_Enter(PADAPTER padapter);
-+u8 rtw_btcoex_LPS_Leave(PADAPTER padapter);
-+
-+#endif /* __RTW_BTCOEX_H__ */
-+#endif /* CONFIG_BT_COEXIST */
-+
-+void rtw_btcoex_set_ant_info(PADAPTER padapter);
-+void rtw_btcoex_connect_notify(PADAPTER, u8 join_type);
-+
-diff --git a/drivers/staging/rtl8723cs/include/rtw_btcoex_wifionly.h b/drivers/staging/rtl8723cs/include/rtw_btcoex_wifionly.h
-new file mode 100644
-index 000000000000..93087ebe09a4
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_btcoex_wifionly.h
-@@ -0,0 +1,24 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_BTCOEX_WIFIONLY_H__
-+#define __RTW_BTCOEX_WIFIONLY_H__
-+
-+void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter);
-+void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter);
-+void rtw_btcoex_wifionly_connect_notify(PADAPTER padapter);
-+void rtw_btcoex_wifionly_hw_config(PADAPTER padapter);
-+void rtw_btcoex_wifionly_initialize(PADAPTER padapter);
-+void rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter);
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtw_byteorder.h b/drivers/staging/rtl8723cs/include/rtw_byteorder.h
-new file mode 100644
-index 000000000000..8e6bb7a6df01
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_byteorder.h
-@@ -0,0 +1,33 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTL871X_BYTEORDER_H_
-+#define _RTL871X_BYTEORDER_H_
-+
-+
-+#if defined(CONFIG_LITTLE_ENDIAN) && defined (CONFIG_BIG_ENDIAN)
-+	#error "Shall be CONFIG_LITTLE_ENDIAN or CONFIG_BIG_ENDIAN, but not both!\n"
-+#endif
-+
-+#if defined(CONFIG_LITTLE_ENDIAN)
-+	#ifndef CONFIG_PLATFORM_MSTAR389
-+		#include <byteorder/little_endian.h>
-+	#endif
-+#elif defined (CONFIG_BIG_ENDIAN)
-+	#include <byteorder/big_endian.h>
-+#else
-+	#  error "Must be LITTLE/BIG Endian Host"
-+#endif
-+
-+#endif /* _RTL871X_BYTEORDER_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_cmd.h b/drivers/staging/rtl8723cs/include/rtw_cmd.h
-new file mode 100644
-index 000000000000..a64245c904ea
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_cmd.h
-@@ -0,0 +1,790 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_CMD_H_
-+#define __RTW_CMD_H_
-+
-+
-+#define C2H_MEM_SZ (16*1024)
-+
-+#define FREE_CMDOBJ_SZ	128
-+
-+#define MAX_CMDSZ	1536
-+#define MAX_RSPSZ	512
-+#define MAX_EVTSZ	1024
-+
-+#define CMDBUFF_ALIGN_SZ 512
-+
-+struct cmd_obj {
-+	_adapter *padapter;
-+	u16	cmdcode;
-+	u8	res;
-+	u8	*parmbuf;
-+	u32	cmdsz;
-+	u8	*rsp;
-+	u32	rspsz;
-+	struct submit_ctx *sctx;
-+	u8 no_io;
-+	/* _sema 	cmd_sem; */
-+	_list	list;
-+};
-+
-+/* cmd flags */
-+enum {
-+	RTW_CMDF_DIRECTLY = BIT0,
-+	RTW_CMDF_WAIT_ACK = BIT1,
-+};
-+
-+struct cmd_priv {
-+	_sema	cmd_queue_sema;
-+	/* _sema	cmd_done_sema; */
-+	_sema	start_cmdthread_sema;
-+
-+	_queue	cmd_queue;
-+	u8	cmd_seq;
-+	u8	*cmd_buf;	/* shall be non-paged, and 4 bytes aligned */
-+	u8	*cmd_allocated_buf;
-+	u8	*rsp_buf;	/* shall be non-paged, and 4 bytes aligned		 */
-+	u8	*rsp_allocated_buf;
-+	u32	cmd_issued_cnt;
-+	u32	cmd_done_cnt;
-+	u32	rsp_cnt;
-+	ATOMIC_T cmdthd_running;
-+	/* u8 cmdthd_running; */
-+
-+	_adapter *padapter;
-+	_mutex sctx_mutex;
-+};
-+
-+#ifdef CONFIG_EVENT_THREAD_MODE
-+struct evt_obj {
-+	u16	evtcode;
-+	u8	res;
-+	u8	*parmbuf;
-+	u32	evtsz;
-+	_list	list;
-+};
-+#endif
-+
-+struct	evt_priv {
-+#ifdef CONFIG_EVENT_THREAD_MODE
-+	_sema	evt_notify;
-+
-+	_queue	evt_queue;
-+#endif
-+
-+#ifdef CONFIG_FW_C2H_REG
-+	#define CONFIG_C2H_WK
-+#endif
-+
-+#ifdef CONFIG_C2H_WK
-+	_workitem c2h_wk;
-+	bool c2h_wk_alive;
-+	struct rtw_cbuf *c2h_queue;
-+	#define C2H_QUEUE_MAX_LEN 10
-+#endif
-+
-+#ifdef CONFIG_H2CLBK
-+	_sema	lbkevt_done;
-+	u8	lbkevt_limit;
-+	u8	lbkevt_num;
-+	u8	*cmdevt_parm;
-+#endif
-+	ATOMIC_T event_seq;
-+	u8	*evt_buf;	/* shall be non-paged, and 4 bytes aligned		 */
-+	u8	*evt_allocated_buf;
-+	u32	evt_done_cnt;
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	u8	*c2h_mem;
-+	u8	*allocated_c2h_mem;
-+#endif
-+
-+};
-+
-+#define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \
-+	do {\
-+		_rtw_init_listhead(&pcmd->list);\
-+		pcmd->cmdcode = code;\
-+		pcmd->parmbuf = (u8 *)(pparm);\
-+		pcmd->cmdsz = sizeof (*pparm);\
-+		pcmd->rsp = NULL;\
-+		pcmd->rspsz = 0;\
-+	} while (0)
-+
-+#define init_h2fwcmd_w_parm_no_parm_rsp(pcmd, code) \
-+	do {\
-+		_rtw_init_listhead(&pcmd->list);\
-+		pcmd->cmdcode = code;\
-+		pcmd->parmbuf = NULL;\
-+		pcmd->cmdsz = 0;\
-+		pcmd->rsp = NULL;\
-+		pcmd->rspsz = 0;\
-+	} while (0)
-+
-+struct P2P_PS_Offload_t {
-+	u8 Offload_En:1;
-+	u8 role:1; /* 1: Owner, 0: Client */
-+	u8 CTWindow_En:1;
-+	u8 NoA0_En:1;
-+	u8 NoA1_En:1;
-+	u8 AllStaSleep:1; /* Only valid in Owner */
-+	u8 discovery:1;
-+	u8 rsvd:1;
-+#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
-+	u8 p2p_macid:7;
-+	u8 disable_close_rf:1; /*1: not close RF but just pause p2p_macid when NoA duration*/
-+#endif /* CONFIG_P2P_PS_NOA_USE_MACID_SLEEP */
-+};
-+
-+struct P2P_PS_CTWPeriod_t {
-+	u8 CTWPeriod;	/* TU */
-+};
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+
-+struct P2P_WoWlan_Offload_t {
-+	u8 Disconnect_Wkup_Drv:1;
-+	u8 role:2;
-+	u8 Wps_Config[2];
-+};
-+
-+#endif /* CONFIG_P2P_WOWLAN */
-+
-+extern u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj);
-+extern struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv);
-+extern void rtw_free_cmd_obj(struct cmd_obj *pcmd);
-+
-+#ifdef CONFIG_EVENT_THREAD_MODE
-+extern u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj);
-+extern struct evt_obj *rtw_dequeue_evt(_queue *queue);
-+extern void rtw_free_evt_obj(struct evt_obj *pcmd);
-+#endif
-+
-+void rtw_stop_cmd_thread(_adapter *adapter);
-+thread_return rtw_cmd_thread(thread_context context);
-+
-+extern u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv);
-+extern void rtw_free_cmd_priv(struct cmd_priv *pcmdpriv);
-+
-+extern u32 rtw_init_evt_priv(struct evt_priv *pevtpriv);
-+extern void rtw_free_evt_priv(struct evt_priv *pevtpriv);
-+extern void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv);
-+extern void rtw_evt_notify_isr(struct evt_priv *pevtpriv);
-+#ifdef CONFIG_P2P
-+u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType);
-+#endif /* CONFIG_P2P */
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+struct rtw_roch_parm {
-+	u64 cookie;
-+	struct wireless_dev *wdev;
-+	struct ieee80211_channel ch;
-+	enum nl80211_channel_type ch_type;
-+	unsigned int duration;
-+};
-+
-+u8 rtw_roch_cmd(_adapter *adapter
-+	, u64 cookie, struct wireless_dev *wdev
-+	, struct ieee80211_channel *ch, enum nl80211_channel_type ch_type
-+	, unsigned int duration
-+	, u8 flags
-+);
-+
-+u8 rtw_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags);
-+
-+u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags);
-+struct mgnt_tx_parm {
-+	u8 tx_ch;
-+	u8 no_cck;
-+	const u8 *buf;
-+	size_t len;
-+	int wait_ack;
-+};
-+#endif
-+
-+enum rtw_drvextra_cmd_id {
-+	NONE_WK_CID,
-+	STA_MSTATUS_RPT_WK_CID,
-+	DYNAMIC_CHK_WK_CID,
-+	DM_CTRL_WK_CID,
-+	PBC_POLLING_WK_CID,
-+	POWER_SAVING_CTRL_WK_CID,/* IPS,AUTOSuspend */
-+	LPS_CTRL_WK_CID,
-+	ANT_SELECT_WK_CID,
-+	P2P_PS_WK_CID,
-+	P2P_PROTO_WK_CID,
-+	CHECK_HIQ_WK_CID,/* for softap mode, check hi queue if empty */
-+	C2H_WK_CID,
-+	RTP_TIMER_CFG_WK_CID,
-+	RESET_SECURITYPRIV, /* add for CONFIG_IEEE80211W, none 11w also can use */
-+	FREE_ASSOC_RESOURCES, /* add for CONFIG_IEEE80211W, none 11w also can use */
-+	DM_IN_LPS_WK_CID,
-+	DM_RA_MSK_WK_CID, /* add for STA update RAMask when bandwith change. */
-+	BEAMFORMING_WK_CID,
-+	LPS_CHANGE_DTIM_CID,
-+	BTINFO_WK_CID,
-+	BTC_REDUCE_WL_TXPWR_CID,
-+	DFS_RADAR_DETECT_WK_CID,
-+	DFS_RADAR_DETECT_EN_DEC_WK_CID,
-+	SESSION_TRACKER_WK_CID,
-+	EN_HW_UPDATE_TSF_WK_CID,
-+	PERIOD_TSF_UPDATE_END_WK_CID,
-+	TEST_H2C_CID,
-+	MP_CMD_WK_CID,
-+	CUSTOMER_STR_WK_CID,
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	RSON_SCAN_WK_CID,
-+#endif
-+	ROCH_WK_CID,
-+	MGNT_TX_WK_CID,
-+	REQ_PER_CMD_WK_CID,
-+	SSMPS_WK_CID,
-+#ifdef CONFIG_CTRL_TXSS_BY_TP
-+	TXSS_WK_CID,
-+#endif
-+	AC_PARM_CMD_WK_CID,
-+#ifdef CONFIG_AP_MODE
-+	STOP_AP_WK_CID,
-+#endif
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	TBTX_CONTROL_TX_WK_CID,
-+#endif
-+	MAX_WK_CID
-+};
-+
-+enum LPS_CTRL_TYPE {
-+	LPS_CTRL_SCAN = 0,
-+	LPS_CTRL_JOINBSS = 1,
-+	LPS_CTRL_CONNECT = 2,
-+	LPS_CTRL_DISCONNECT = 3,
-+	LPS_CTRL_SPECIAL_PACKET = 4,
-+	LPS_CTRL_LEAVE = 5,
-+	LPS_CTRL_TRAFFIC_BUSY = 6,
-+	LPS_CTRL_TX_TRAFFIC_LEAVE = 7,
-+	LPS_CTRL_RX_TRAFFIC_LEAVE = 8,
-+	LPS_CTRL_ENTER = 9,
-+	LPS_CTRL_LEAVE_CFG80211_PWRMGMT = 10,
-+	LPS_CTRL_LEAVE_SET_OPTION = 11,
-+};
-+
-+enum STAKEY_TYPE {
-+	GROUP_KEY		= 0,
-+	UNICAST_KEY		= 1,
-+	TDLS_KEY		= 2,
-+};
-+
-+enum RFINTFS {
-+	SWSI,
-+	HWSI,
-+	HWPI,
-+};
-+
-+
-+/*
-+Caller Mode: Infra, Ad-Hoc
-+
-+Notes: To join the specified bss
-+
-+Command Event Mode
-+
-+*/
-+struct joinbss_parm {
-+	WLAN_BSSID_EX network;
-+};
-+
-+/*
-+Caller Mode: Infra, Ad-HoC(C)
-+
-+Notes: To disconnect the current associated BSS
-+
-+Command Mode
-+
-+*/
-+struct disconnect_parm {
-+	u32 deauth_timeout_ms;
-+};
-+
-+/*
-+Caller Mode: AP, Ad-HoC(M)
-+
-+Notes: To create a BSS
-+
-+Command Mode
-+*/
-+struct createbss_parm {
-+	bool adhoc;
-+
-+	/* used by AP/Mesh mode now */
-+	u8 ifbmp;
-+	u8 excl_ifbmp;
-+	s16 req_ch;
-+	s8 req_bw;
-+	s8 req_offset;
-+};
-+
-+
-+struct	setopmode_parm {
-+	u8	mode;
-+	u8	rsvd[3];
-+};
-+
-+/*
-+Caller Mode: AP, Ad-HoC, Infra
-+
-+Notes: To ask RTL8711 performing site-survey
-+
-+Command-Event Mode
-+
-+*/
-+
-+#define RTW_SSID_SCAN_AMOUNT 9 /* for WEXT_CSCAN_AMOUNT 9 */
-+#define RTW_CHANNEL_SCAN_AMOUNT (14+37)
-+struct sitesurvey_parm {
-+	sint scan_mode;	/* active: 1, passive: 0 */
-+	/* sint bsslimit;	// 1 ~ 48 */
-+	u8 ssid_num;
-+	u8 ch_num;
-+	NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT];
-+	struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT];
-+
-+	u32 token; 	/* 80211k use it to identify caller */
-+	u16 duration;	/* 0: use default, otherwise: channel scan time */
-+	u8 igi;		/* 0: use defalut */
-+	u8 bw;		/* 0: use default */
-+
-+	bool acs; /* aim to trigger channel selection when scan done */
-+};
-+
-+/*
-+Caller Mode: Any
-+
-+Notes: To set the auth type of RTL8711. open/shared/802.1x
-+
-+Command Mode
-+
-+*/
-+struct setauth_parm {
-+	u8 mode;  /* 0: legacy open, 1: legacy shared 2: 802.1x */
-+	u8 _1x;   /* 0: PSK, 1: TLS */
-+	u8 rsvd[2];
-+};
-+
-+/*
-+Caller Mode: Infra
-+
-+a. algorithm: wep40, wep104, tkip & aes
-+b. keytype: grp key/unicast key
-+c. key contents
-+
-+when shared key ==> keyid is the camid
-+when 802.1x ==> keyid [0:1] ==> grp key
-+when 802.1x ==> keyid > 2 ==> unicast key
-+
-+*/
-+struct setkey_parm {
-+	u8	algorithm;	/* encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 */
-+	u8	keyid;
-+	u8	set_tx;		/* 1: main tx key for wep. 0: other key. */
-+	u8	key[32];	/* this could be 40 or 104 */
-+};
-+
-+/*
-+When in AP or Ad-Hoc mode, this is used to
-+allocate an sw/hw entry for a newly associated sta.
-+
-+Command
-+
-+when shared key ==> algorithm/keyid
-+
-+*/
-+struct set_stakey_parm {
-+	u8 addr[ETH_ALEN];
-+	u8 algorithm;
-+	u8 keyid;
-+	u8 key[32];
-+	u8 gk;
-+};
-+
-+struct set_stakey_rsp {
-+	u8	addr[ETH_ALEN];
-+	u8	keyid;
-+	u8	rsvd;
-+};
-+
-+struct Tx_Beacon_param {
-+	WLAN_BSSID_EX network;
-+};
-+
-+/*
-+	Notes: This command is used for H2C/C2H loopback testing
-+
-+	mac[0] == 0
-+	==> CMD mode, return H2C_SUCCESS.
-+	The following condition must be ture under CMD mode
-+		mac[1] == mac[4], mac[2] == mac[3], mac[0]=mac[5]= 0;
-+		s0 == 0x1234, s1 == 0xabcd, w0 == 0x78563412, w1 == 0x5aa5def7;
-+		s2 == (b1 << 8 | b0);
-+
-+	mac[0] == 1
-+	==> CMD_RSP mode, return H2C_SUCCESS_RSP
-+
-+	The rsp layout shall be:
-+	rsp:			parm:
-+		mac[0]  =   mac[5];
-+		mac[1]  =   mac[4];
-+		mac[2]  =   mac[3];
-+		mac[3]  =   mac[2];
-+		mac[4]  =   mac[1];
-+		mac[5]  =   mac[0];
-+		s0		=   s1;
-+		s1		=   swap16(s0);
-+		w0		=	swap32(w1);
-+		b0		=	b1
-+		s2		=	s0 + s1
-+		b1		=	b0
-+		w1		=	w0
-+
-+	mac[0] ==	2
-+	==> CMD_EVENT mode, return	H2C_SUCCESS
-+	The event layout shall be:
-+	event:			parm:
-+		mac[0]  =   mac[5];
-+		mac[1]  =   mac[4];
-+		mac[2]  =   event's sequence number, starting from 1 to parm's marc[3]
-+		mac[3]  =   mac[2];
-+		mac[4]  =   mac[1];
-+		mac[5]  =   mac[0];
-+		s0		=   swap16(s0) - event.mac[2];
-+		s1		=   s1 + event.mac[2];
-+		w0		=	swap32(w0);
-+		b0		=	b1
-+		s2		=	s0 + event.mac[2]
-+		b1		=	b0
-+		w1		=	swap32(w1) - event.mac[2];
-+
-+		parm->mac[3] is the total event counts that host requested.
-+
-+
-+	event will be the same with the cmd's param.
-+
-+*/
-+
-+#ifdef CONFIG_H2CLBK
-+
-+struct seth2clbk_parm {
-+	u8 mac[6];
-+	u16	s0;
-+	u16	s1;
-+	u32	w0;
-+	u8	b0;
-+	u16  s2;
-+	u8	b1;
-+	u32	w1;
-+};
-+
-+struct geth2clbk_parm {
-+	u32 rsv;
-+};
-+
-+struct geth2clbk_rsp {
-+	u8	mac[6];
-+	u16	s0;
-+	u16	s1;
-+	u32	w0;
-+	u8	b0;
-+	u16	s2;
-+	u8	b1;
-+	u32	w1;
-+};
-+
-+#endif	/* CONFIG_H2CLBK */
-+
-+/* CMD param Formart for driver extra cmd handler */
-+struct drvextra_cmd_parm {
-+	int ec_id; /* extra cmd id */
-+	int type; /* Can use this field as the type id or command size */
-+	int size; /* buffer size */
-+	unsigned char *pbuf;
-+};
-+
-+/*------------------- Below are used for RF/BB tunning ---------------------*/
-+struct addBaReq_parm {
-+	unsigned int tid;
-+	u8	addr[ETH_ALEN];
-+};
-+
-+struct addBaRsp_parm {
-+	unsigned int tid;
-+	unsigned int start_seq;
-+	u8 addr[ETH_ALEN];
-+	u8 status;
-+	u8 size;
-+};
-+
-+struct set_ch_parm {
-+	u8 ch;
-+	u8 bw;
-+	u8 ch_offset;
-+};
-+
-+struct SetChannelPlan_param {
-+	enum regd_src_t regd_src;
-+	const struct country_chplan *country_ent;
-+	u8 channel_plan;
-+};
-+
-+struct get_channel_plan_param {
-+	struct get_chplan_resp **resp;
-+};
-+
-+struct LedBlink_param {
-+	void *pLed;
-+};
-+
-+struct TDLSoption_param {
-+	u8 addr[ETH_ALEN];
-+	u8 option;
-+};
-+
-+struct RunInThread_param {
-+	void (*func)(void *);
-+	void *context;
-+};
-+
-+
-+#define GEN_CMD_CODE(cmd)	cmd ## _CMD_
-+
-+
-+/*
-+
-+Result:
-+0x00: success
-+0x01: sucess, and check Response.
-+0x02: cmd ignored due to duplicated sequcne number
-+0x03: cmd dropped due to invalid cmd code
-+0x04: reserved.
-+
-+*/
-+
-+#define H2C_RSP_OFFSET			512
-+
-+#define H2C_SUCCESS			0x00
-+#define H2C_SUCCESS_RSP			0x01
-+#define H2C_DUPLICATED			0x02
-+#define H2C_DROPPED			0x03
-+#define H2C_PARAMETERS_ERROR		0x04
-+#define H2C_REJECTED			0x05
-+#define H2C_CMD_OVERFLOW		0x06
-+#define H2C_RESERVED			0x07
-+#define H2C_ENQ_HEAD			0x08
-+#define H2C_ENQ_HEAD_FAIL		0x09
-+#define H2C_CMD_FAIL			0x0A
-+
-+void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm);
-+u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm);
-+#ifdef CONFIG_AP_MODE
-+u8 rtw_create_ibss_cmd(_adapter *adapter, int flags);
-+u8 rtw_startbss_cmd(_adapter *adapter, int flags);
-+#endif
-+
-+#define REQ_CH_NONE		-1
-+#define REQ_CH_INT_INFO	-2
-+#define REQ_BW_NONE		-1
-+#define REQ_BW_ORI		-2
-+#define REQ_OFFSET_NONE	-1
-+
-+struct sta_info;
-+extern u8 rtw_setstakey_cmd(_adapter  *padapter, struct sta_info *sta, u8 key_type, bool enqueue);
-+extern u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue);
-+
-+extern u8 rtw_joinbss_cmd(_adapter  *padapter, struct wlan_network *pnetwork);
-+u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags);
-+#ifdef CONFIG_AP_MODE
-+u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags
-+	, u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset);
-+u8 rtw_stop_ap_cmd(_adapter *adapter, u8 flags);
-+#endif
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+u8 rtw_tx_control_cmd(_adapter *adapter);
-+#endif
-+extern u8 rtw_setopmode_cmd(_adapter  *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags);
-+
-+extern u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr);
-+extern u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq);
-+/* add for CONFIG_IEEE80211W, none 11w also can use */
-+extern u8 rtw_reset_securitypriv_cmd(_adapter *padapter);
-+extern u8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int flags);
-+extern u8 rtw_dynamic_chk_wk_cmd(_adapter *adapter);
-+
-+u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 flags);
-+u8 rtw_lps_ctrl_leave_set_level_cmd(_adapter *adapter, u8 lps_level, u8 flags);
-+#ifdef CONFIG_LPS_1T1R
-+u8 rtw_lps_ctrl_leave_set_1t1r_cmd(_adapter *adapter, u8 lps_1t1r, u8 flags);
-+#endif
-+u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter);
-+u8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim);
-+
-+#if (RATE_ADAPTIVE_SUPPORT == 1)
-+u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime);
-+#endif
-+
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+extern  u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue);
-+#endif
-+
-+u8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta);
-+
-+extern u8 rtw_ps_cmd(_adapter *padapter);
-+
-+#if CONFIG_DFS
-+void rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj);
-+#endif
-+
-+#ifdef CONFIG_AP_MODE
-+u8 rtw_chk_hi_queue_cmd(_adapter *padapter);
-+#ifdef CONFIG_DFS_MASTER
-+u8 rtw_dfs_rd_cmd(_adapter *adapter, bool enqueue);
-+void rtw_dfs_rd_timer_hdl(void *ctx);
-+void rtw_dfs_rd_en_decision(_adapter *adapter, u8 mlme_act, u8 excl_ifbmp);
-+u8 rtw_dfs_rd_en_decision_cmd(_adapter *adapter);
-+#endif /* CONFIG_DFS_MASTER */
-+#endif /* CONFIG_AP_MODE */
-+
-+#ifdef CONFIG_BT_COEXIST
-+u8 rtw_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length);
-+u8 rtw_btc_reduce_wl_txpwr_cmd(_adapter *adapter, u32 val);
-+#endif
-+
-+u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len);
-+
-+u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter);
-+u8 rtw_periodic_tsf_update_end_cmd(_adapter *adapter);
-+
-+u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags);
-+u8 rtw_iqk_cmd(_adapter *padapter, u8 flags);
-+
-+u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig);
-+u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig);
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+u8 rtw_sync_os_regd_cmd(_adapter *adapter, int flags, const char *country_code, u8 dfs_region);
-+#endif
-+u8 rtw_get_chplan_cmd(_adapter *adapter, int flags, struct get_chplan_resp **resp);
-+
-+extern u8 rtw_led_blink_cmd(_adapter *padapter, void *pLed);
-+extern u8 rtw_set_csa_cmd(_adapter *adapter);
-+extern u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option);
-+
-+u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags);
-+
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+u8 rtw_customer_str_req_cmd(_adapter *adapter);
-+u8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr);
-+#endif
-+
-+#ifdef CONFIG_FW_C2H_REG
-+u8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt);
-+#endif
-+#ifdef CONFIG_FW_C2H_PKT
-+u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length);
-+#endif
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+#define RSON_SCAN_PROCESS		10
-+#define RSON_SCAN_DISABLE		11
-+u8 rtw_rson_scan_wk_cmd(_adapter *adapter, int op);
-+#endif
-+
-+u8 rtw_run_in_thread_cmd(_adapter *adapter, void (*func)(void *), void *context);
-+u8 rtw_run_in_thread_cmd_wait(_adapter *adapter, void (*func)(void *), void *context, s32 timeout_ms);
-+
-+struct ssmps_cmd_parm {
-+	struct sta_info *sta;
-+	u8 smps;
-+};
-+u8 rtw_ssmps_wk_cmd(_adapter *adapter, struct sta_info *sta, u8 smps, u8 enqueue);
-+
-+u8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta);
-+u8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);
-+u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);
-+
-+u8 set_txq_params_cmd(_adapter *adapter, u32 ac_parm, u8 ac_type);
-+
-+#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW)
-+u8 rtw_req_per_cmd(_adapter * adapter);
-+#endif
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+u8 rtw_tbtx_chk_cmd(_adapter *adapter);
-+u8 rtw_tbtx_token_dispatch_cmd(_adapter *adapter);
-+#endif
-+#ifdef CONFIG_CTRL_TXSS_BY_TP
-+struct txss_cmd_parm {
-+	struct sta_info *sta;
-+	bool tx_1ss;
-+};
-+
-+void rtw_ctrl_txss_update_mimo_type(_adapter *adapter, struct sta_info *sta);
-+u8 rtw_ctrl_txss(_adapter *adapter, struct sta_info *sta, bool tx_1ss);
-+void rtw_ctrl_tx_ss_by_tp(_adapter *adapter, u8 from_timer);
-+
-+#ifdef DBG_CTRL_TXSS
-+void dbg_ctrl_txss(_adapter *adapter, bool tx_1ss);
-+#endif
-+#endif
-+
-+u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf);
-+
-+extern void rtw_survey_cmd_callback(_adapter  *padapter, struct cmd_obj *pcmd);
-+extern void rtw_disassoc_cmd_callback(_adapter  *padapter, struct cmd_obj *pcmd);
-+extern void rtw_joinbss_cmd_callback(_adapter  *padapter, struct cmd_obj *pcmd);
-+void rtw_create_ibss_post_hdl(_adapter *padapter, int status);
-+extern void rtw_readtssi_cmdrsp_callback(_adapter	*padapter,  struct cmd_obj *pcmd);
-+
-+extern void rtw_setstaKey_cmdrsp_callback(_adapter  *padapter,  struct cmd_obj *pcmd);
-+extern void rtw_getrttbl_cmdrsp_callback(_adapter  *padapter,  struct cmd_obj *pcmd);
-+
-+enum rtw_cmd_id {
-+	CMD_JOINBSS, /*0*/
-+	CMD_DISCONNECT, /*1*/
-+	CMD_CREATE_BSS,/*2*/
-+	CMD_SET_OPMODE, /*3*/
-+	CMD_SITE_SURVEY, /*4*/
-+	CMD_SET_AUTH, /*5*/
-+	CMD_SET_KEY, /*6*/
-+	CMD_SET_STAKEY, /*7*/
-+	CMD_ADD_BAREQ, /*8*/
-+	CMD_SET_CHANNEL, /*9*/
-+	CMD_TX_BEACON, /*10*/
-+	CMD_SET_MLME_EVT, /*11*/
-+	CMD_SET_DRV_EXTRA, /*12*/
-+	CMD_SET_CHANPLAN, /*13*/
-+	CMD_LEDBLINK, /*14*/
-+	CMD_SET_CHANSWITCH, /*15*/
-+	CMD_TDLS, /*16*/
-+	CMD_CHK_BMCSLEEPQ,  /*17*/
-+	CMD_RUN_INTHREAD, /*18*/
-+	CMD_ADD_BARSP, /*19*/
-+	CMD_RM_POST_EVENT, /*20*/
-+	CMD_SET_MESH_PLINK_STATE, /* 21 */
-+	CMD_DO_IQK, /* 22 */
-+	CMD_GET_CHANPLAN, /*23*/
-+	CMD_ID_MAX
-+};
-+
-+#define CMD_FMT "cmd=%d,%d,%d"
-+#define CMD_ARG(cmd) \
-+	(cmd)->cmdcode, \
-+	(cmd)->cmdcode == CMD_SET_DRV_EXTRA ? ((struct drvextra_cmd_parm *)(cmd)->parmbuf)->ec_id : ((cmd)->cmdcode == CMD_SET_MLME_EVT ? ((struct rtw_evt_header *)(cmd)->parmbuf)->id : 0), \
-+	(cmd)->cmdcode == CMD_SET_DRV_EXTRA ? ((struct drvextra_cmd_parm *)(cmd)->parmbuf)->type : 0
-+
-+#endif /* _CMD_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_debug.h b/drivers/staging/rtl8723cs/include/rtw_debug.h
-new file mode 100644
-index 000000000000..1ce9af3c9594
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_debug.h
-@@ -0,0 +1,727 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_DEBUG_H__
-+#define __RTW_DEBUG_H__
-+
-+/* driver log level*/
-+enum {
-+	_DRV_NONE_ = 0,
-+	_DRV_ALWAYS_ = 1,
-+	_DRV_ERR_ = 2,
-+	_DRV_WARNING_ = 3,
-+	_DRV_INFO_ = 4,
-+	_DRV_DEBUG_ = 5,
-+	_DRV_MAX_ = 6
-+};
-+
-+#define DRIVER_PREFIX "RTW: "
-+
-+#ifdef PLATFORM_OS_CE
-+extern void rtl871x_cedbg(const char *fmt, ...);
-+#endif
-+
-+#ifdef PLATFORM_WINDOWS
-+	#define RTW_PRINT do {} while (0)
-+	#define RTW_ERR do {} while (0)
-+	#define RTW_WARN do {} while (0)
-+	#define RTW_INFO do {} while (0)
-+	#define RTW_DBG do {} while (0)
-+	#define RTW_PRINT_SEL do {} while (0)
-+	#define _RTW_PRINT do {} while (0)
-+	#define _RTW_ERR do {} while (0)
-+	#define _RTW_WARN do {} while (0)
-+	#define _RTW_INFO do {} while (0)
-+	#define _RTW_DBG do {} while (0)
-+	#define _RTW_PRINT_SEL do {} while (0)
-+#else
-+	#define RTW_PRINT(x, ...) do {} while (0)
-+	#define RTW_ERR(x, ...) do {} while (0)
-+	#define RTW_WARN(x,...) do {} while (0)
-+	#define RTW_INFO(x,...) do {} while (0)
-+	#define RTW_DBG(x,...) do {} while (0)
-+	#define RTW_PRINT_SEL(x,...) do {} while (0)
-+	#define _RTW_PRINT(x, ...) do {} while (0)
-+	#define _RTW_ERR(x, ...) do {} while (0)
-+	#define _RTW_WARN(x,...) do {} while (0)
-+	#define _RTW_INFO(x,...) do {} while (0)
-+	#define _RTW_DBG(x,...) do {} while (0)
-+	#define _RTW_PRINT_SEL(x,...) do {} while (0)
-+#endif
-+
-+#define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0)
-+#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0)
-+#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0)
-+
-+#define RTW_DBG_EXPR(EXPR) do {} while (0)
-+
-+#define RTW_DBGDUMP 0 /* 'stream' for _dbgdump */
-+
-+
-+
-+#undef _dbgdump
-+#undef _seqdump
-+
-+#if defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_XP)
-+	#define _dbgdump DbgPrint
-+	#define KERN_CONT
-+	#define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg)
-+#elif defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_CE)
-+	#define _dbgdump rtl871x_cedbg
-+	#define KERN_CONT
-+	#define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg)
-+#elif defined PLATFORM_LINUX
-+	#define _dbgdump printk
-+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
-+	#define KERN_CONT
-+	#endif
-+	#define _seqdump seq_printf
-+#elif defined PLATFORM_FREEBSD
-+	#define _dbgdump printf
-+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
-+	#define KERN_CONT
-+	#endif
-+	#define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg)
-+#endif
-+
-+void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring,
-+								bool _idx_show, const u8 *_hexdata, int _hexdatalen);
-+
-+#ifdef CONFIG_RTW_DEBUG
-+
-+#ifndef _OS_INTFS_C_
-+extern uint rtw_drv_log_level;
-+#endif
-+
-+#if defined(_dbgdump)
-+
-+#ifdef PLATFORM_LINUX
-+#ifdef DBG_THREAD_PID
-+#define T_PID_FMT	"(%5u) "
-+#define T_PID_ARG	current->pid
-+#else /* !DBG_THREAD_PID */
-+#define T_PID_FMT	"%s"
-+#define T_PID_ARG	""
-+#endif /* !DBG_THREAD_PID */
-+
-+#ifdef DBG_CPU_INFO
-+#define CPU_INFO_FMT	"[%u] "
-+#define CPU_INFO_ARG	get_cpu()
-+#else /* !DBG_CPU_INFO */
-+#define CPU_INFO_FMT	"%s"
-+#define CPU_INFO_ARG	""
-+#endif /* !DBG_CPU_INFO */
-+
-+/* Extra information in prefix */
-+#define EX_INFO_FMT	T_PID_FMT CPU_INFO_FMT
-+#define EX_INFO_ARG	T_PID_ARG, CPU_INFO_ARG
-+#else /* !PLATFORM_LINUX */
-+#define EX_INFO_FMT	"%s"
-+#define EX_INFO_ARG	""
-+#endif /* !PLATFORM_LINUX */
-+
-+#define DBG_PREFIX	EX_INFO_FMT DRIVER_PREFIX
-+#define DBG_PREFIX_ARG	EX_INFO_ARG
-+
-+/* with driver-defined prefix */
-+#undef RTW_PRINT
-+#define RTW_PRINT(fmt, arg...)     \
-+	do {\
-+		if (_DRV_ALWAYS_ <= rtw_drv_log_level) {\
-+			_dbgdump(DBG_PREFIX fmt, DBG_PREFIX_ARG, ##arg);\
-+		} \
-+	} while (0)
-+
-+#undef RTW_ERR
-+#define RTW_ERR(fmt, arg...)     \
-+	do {\
-+		if (_DRV_ERR_ <= rtw_drv_log_level) {\
-+			_dbgdump(DBG_PREFIX "ERROR " fmt, \
-+				 DBG_PREFIX_ARG, ##arg);\
-+		} \
-+	} while (0)
-+
-+
-+#undef RTW_WARN
-+#define RTW_WARN(fmt, arg...)     \
-+	do {\
-+		if (_DRV_WARNING_ <= rtw_drv_log_level) {\
-+			_dbgdump(DBG_PREFIX "WARN " fmt, \
-+				 DBG_PREFIX_ARG, ##arg);\
-+		} \
-+	} while (0)
-+
-+#undef RTW_INFO
-+#define RTW_INFO(fmt, arg...)     \
-+	do {\
-+		if (_DRV_INFO_ <= rtw_drv_log_level) {\
-+			_dbgdump(DBG_PREFIX fmt, DBG_PREFIX_ARG, ##arg);\
-+		} \
-+	} while (0)
-+
-+
-+#undef RTW_DBG
-+#define RTW_DBG(fmt, arg...)     \
-+	do {\
-+		if (_DRV_DEBUG_ <= rtw_drv_log_level) {\
-+			_dbgdump(DBG_PREFIX fmt, DBG_PREFIX_ARG, ##arg);\
-+		} \
-+	} while (0)
-+
-+#undef RTW_INFO_DUMP
-+#define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen)	\
-+	RTW_BUF_DUMP_SEL(_DRV_INFO_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen)
-+
-+#undef RTW_DBG_DUMP
-+#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen)	\
-+	RTW_BUF_DUMP_SEL(_DRV_DEBUG_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen)
-+
-+
-+#undef RTW_PRINT_DUMP
-+#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen)	\
-+	RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen)
-+
-+/* without driver-defined prefix */
-+#undef _RTW_PRINT
-+#define _RTW_PRINT(fmt, arg...)     \
-+	do {\
-+		if (_DRV_ALWAYS_ <= rtw_drv_log_level) {\
-+			_dbgdump(KERN_CONT fmt, ##arg);\
-+		} \
-+	} while (0)
-+
-+#undef _RTW_ERR
-+#define _RTW_ERR(fmt, arg...)     \
-+	do {\
-+		if (_DRV_ERR_ <= rtw_drv_log_level) {\
-+			_dbgdump(KERN_CONT fmt, ##arg);\
-+		} \
-+	} while (0)
-+
-+
-+#undef _RTW_WARN
-+#define _RTW_WARN(fmt, arg...)     \
-+	do {\
-+		if (_DRV_WARNING_ <= rtw_drv_log_level) {\
-+			_dbgdump(KERN_CONT fmt, ##arg);\
-+		} \
-+	} while (0)
-+
-+#undef _RTW_INFO
-+#define _RTW_INFO(fmt, arg...)     \
-+	do {\
-+		if (_DRV_INFO_ <= rtw_drv_log_level) {\
-+			_dbgdump(KERN_CONT fmt, ##arg);\
-+		} \
-+	} while (0)
-+
-+#undef _RTW_DBG
-+#define _RTW_DBG(fmt, arg...)     \
-+	do {\
-+		if (_DRV_DEBUG_ <= rtw_drv_log_level) {\
-+			_dbgdump(KERN_CONT fmt, ##arg);\
-+		} \
-+	} while (0)
-+
-+
-+/* other debug APIs */
-+#undef RTW_DBG_EXPR
-+#define RTW_DBG_EXPR(EXPR) do { if (_DRV_DEBUG_ <= rtw_drv_log_level) EXPR; } while (0)
-+
-+#endif /* defined(_dbgdump) */
-+#endif /* CONFIG_RTW_DEBUG */
-+
-+
-+#if defined(_seqdump)
-+/* dump message to selected 'stream' with driver-defined prefix */
-+#undef RTW_PRINT_SEL
-+#define RTW_PRINT_SEL(sel, fmt, arg...) \
-+	do {\
-+		if (sel == RTW_DBGDUMP)\
-+			RTW_PRINT(fmt, ##arg); \
-+		else {\
-+			_seqdump(sel, fmt, ##arg) /*rtw_warn_on(1)*/; \
-+		} \
-+	} while (0)
-+
-+/* dump message to selected 'stream' */
-+#undef _RTW_PRINT_SEL
-+#define _RTW_PRINT_SEL(sel, fmt, arg...) \
-+	do {\
-+		if (sel == RTW_DBGDUMP)\
-+			_RTW_PRINT(fmt, ##arg); \
-+		else {\
-+			_seqdump(sel, fmt, ##arg) /*rtw_warn_on(1)*/; \
-+		} \
-+	} while (0)
-+
-+/* dump message to selected 'stream' */
-+#undef RTW_DUMP_SEL
-+#define RTW_DUMP_SEL(sel, _HexData, _HexDataLen) \
-+	RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, sel, NULL, _FALSE, _HexData, _HexDataLen)
-+
-+#define RTW_MAP_DUMP_SEL(sel, _TitleString, _HexData, _HexDataLen) \
-+	RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, sel, _TitleString, _TRUE, _HexData, _HexDataLen)
-+#endif /* defined(_seqdump) */
-+
-+
-+#ifdef CONFIG_DBG_COUNTER
-+	#define DBG_COUNTER(counter) counter++
-+#else
-+	#define DBG_COUNTER(counter)
-+#endif
-+
-+void dump_drv_version(void *sel);
-+void dump_log_level(void *sel);
-+
-+#ifdef CONFIG_SDIO_HCI
-+void sd_f0_reg_dump(void *sel, _adapter *adapter);
-+void sdio_local_reg_dump(void *sel, _adapter *adapter);
-+#endif /* CONFIG_SDIO_HCI */
-+
-+void mac_reg_dump(void *sel, _adapter *adapter);
-+void bb_reg_dump(void *sel, _adapter *adapter);
-+void bb_reg_dump_ex(void *sel, _adapter *adapter);
-+void rf_reg_dump(void *sel, _adapter *adapter);
-+
-+void rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos);
-+
-+struct sta_info;
-+void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta);
-+
-+struct dvobj_priv;
-+void dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj);
-+void dump_adapters_status(void *sel, struct dvobj_priv *dvobj);
-+
-+struct sec_cam_ent;
-+#if defined(CONFIG_RTW_DEBUG) || defined(CONFIG_PROC_DEBUG)
-+void dump_sec_cam_ent(void *sel, struct sec_cam_ent *ent, int id);
-+void dump_sec_cam_ent_title(void *sel, u8 has_id);
-+#endif
-+void dump_sec_cam(void *sel, _adapter *adapter);
-+void dump_sec_cam_cache(void *sel, _adapter *adapter);
-+
-+bool rtw_fwdl_test_trigger_chksum_fail(void);
-+bool rtw_fwdl_test_trigger_wintint_rdy_fail(void);
-+bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void);
-+u32 rtw_get_wait_hiq_empty_ms(void);
-+void rtw_sta_linking_test_set_start(void);
-+bool rtw_sta_linking_test_wait_done(void);
-+bool rtw_sta_linking_test_force_fail(void);
-+#ifdef CONFIG_AP_MODE
-+u16 rtw_ap_linking_test_force_auth_fail(void);
-+u16 rtw_ap_linking_test_force_asoc_fail(void);
-+#endif
-+
-+#ifdef CONFIG_PROC_DEBUG
-+ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_read_reg(struct seq_file *m, void *v);
-+ssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+void dump_drv_cfg(void *sel);
-+int proc_get_fwstate(struct seq_file *m, void *v);
-+int proc_get_sec_info(struct seq_file *m, void *v);
-+int proc_get_mlmext_state(struct seq_file *m, void *v);
-+#ifdef CONFIG_LAYER2_ROAMING
-+int proc_get_roam_flags(struct seq_file *m, void *v);
-+ssize_t proc_set_roam_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_roam_param(struct seq_file *m, void *v);
-+ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+ssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif /* CONFIG_LAYER2_ROAMING */
-+int proc_get_qos_option(struct seq_file *m, void *v);
-+int proc_get_ht_option(struct seq_file *m, void *v);
-+int proc_get_rf_info(struct seq_file *m, void *v);
-+int proc_get_scan_param(struct seq_file *m, void *v);
-+ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_scan_abort(struct seq_file *m, void *v);
-+#ifdef CONFIG_RTW_REPEATER_SON
-+int proc_get_rson_data(struct seq_file *m, void *v);
-+ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif
-+int proc_get_survey_info(struct seq_file *m, void *v);
-+ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_ap_info(struct seq_file *m, void *v);
-+#ifdef ROKU_PRIVATE
-+int proc_get_infra_ap(struct seq_file *m, void *v);
-+#endif /* ROKU_PRIVATE */
-+ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_trx_info(struct seq_file *m, void *v);
-+ssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_tx_power_offset(struct seq_file *m, void *v);
-+int proc_get_rate_ctl(struct seq_file *m, void *v);
-+int proc_get_wifi_spec(struct seq_file *m, void *v);
-+ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_bw_ctl(struct seq_file *m, void *v);
-+ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#ifdef DBG_RX_COUNTER_DUMP
-+int proc_get_rx_cnt_dump(struct seq_file *m, void *v);
-+ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif
-+
-+#ifdef CONFIG_AP_MODE
-+int proc_get_bmc_tx_rate(struct seq_file *m, void *v);
-+ssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif /*CONFIG_AP_MODE*/
-+
-+int proc_get_ps_dbg_info(struct seq_file *m, void *v);
-+ssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#ifdef CONFIG_AP_MODE
-+ssize_t proc_set_ap_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif
-+
-+int proc_get_rx_stat(struct seq_file *m, void *v);
-+int proc_get_tx_stat(struct seq_file *m, void *v);
-+#ifdef CONFIG_AP_MODE
-+int proc_get_all_sta_info(struct seq_file *m, void *v);
-+#endif /* CONFIG_AP_MODE */
-+
-+#ifdef DBG_MEMORY_LEAK
-+int proc_get_malloc_cnt(struct seq_file *m, void *v);
-+#endif /* DBG_MEMORY_LEAK */
-+
-+#ifdef CONFIG_FIND_BEST_CHANNEL
-+int proc_get_best_channel(struct seq_file *m, void *v);
-+ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif /* CONFIG_FIND_BEST_CHANNEL */
-+
-+int proc_get_trx_info_debug(struct seq_file *m, void *v);
-+
-+#ifdef CONFIG_HUAWEI_PROC
-+int proc_get_huawei_trx_info(struct seq_file *m, void *v);
-+#endif
-+
-+int proc_get_rx_signal(struct seq_file *m, void *v);
-+ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_hw_status(struct seq_file *m, void *v);
-+ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_mac_rptbuf(struct seq_file *m, void *v);
-+
-+#ifdef CONFIG_80211N_HT
-+int proc_get_ht_enable(struct seq_file *m, void *v);
-+ssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+int proc_get_bw_mode(struct seq_file *m, void *v);
-+ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+int proc_get_ampdu_enable(struct seq_file *m, void *v);
-+ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter);
-+int proc_get_rx_ampdu(struct seq_file *m, void *v);
-+ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+void rtw_dump_dft_phy_cap(void *sel, _adapter *adapter);
-+void rtw_get_dft_phy_cap(void *sel, _adapter *adapter);
-+void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter);
-+
-+int proc_get_rx_stbc(struct seq_file *m, void *v);
-+ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_stbc_cap(struct seq_file *m, void *v);
-+ssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_ldpc_cap(struct seq_file *m, void *v);
-+ssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#ifdef CONFIG_BEAMFORMING
-+int proc_get_txbf_cap(struct seq_file *m, void *v);
-+ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif
-+#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+int proc_get_tx_aval_th(struct seq_file *m, void *v);
-+ssize_t proc_set_tx_aval_th(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif /*CONFIG_SDIO_TX_ENABLE_AVAL_INT*/
-+int proc_get_rx_ampdu_factor(struct seq_file *m, void *v);
-+ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+int proc_get_tx_max_agg_num(struct seq_file *m, void *v);
-+ssize_t proc_set_tx_max_agg_num(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+int proc_get_rx_ampdu_density(struct seq_file *m, void *v);
-+ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+int proc_get_tx_ampdu_density(struct seq_file *m, void *v);
-+ssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+int proc_get_tx_quick_addba_req(struct seq_file *m, void *v);
-+ssize_t proc_set_tx_quick_addba_req(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#ifdef CONFIG_TX_AMSDU
-+int proc_get_tx_amsdu(struct seq_file *m, void *v);
-+ssize_t proc_set_tx_amsdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_tx_amsdu_rate(struct seq_file *m, void *v);
-+ssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif
-+#endif /* CONFIG_80211N_HT */
-+
-+#ifdef CONFIG_80211AC_VHT
-+int proc_get_vht_24g_enable(struct seq_file *m, void *v);
-+ssize_t proc_set_vht_24g_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif
-+
-+ssize_t proc_set_dyn_rrsr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_dyn_rrsr(struct seq_file *m, void *v);
-+
-+int proc_get_en_fwps(struct seq_file *m, void *v);
-+ssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+#if 0
-+int proc_get_two_path_rssi(struct seq_file *m, void *v);
-+int proc_get_rssi_disp(struct seq_file *m, void *v);
-+ssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif
-+
-+#ifdef CONFIG_BT_COEXIST
-+int proc_get_btcoex_dbg(struct seq_file *m, void *v);
-+ssize_t proc_set_btcoex_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_btcoex_info(struct seq_file *m, void *v);
-+#ifdef CONFIG_RF4CE_COEXIST
-+int proc_get_rf4ce_state(struct seq_file *m, void *v);
-+ssize_t proc_set_rf4ce_state(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif
-+#endif /* CONFIG_BT_COEXIST */
-+
-+#if defined(DBG_CONFIG_ERROR_DETECT)
-+int proc_get_sreset(struct seq_file *m, void *v);
-+ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif /* DBG_CONFIG_ERROR_DETECT */
-+
-+int proc_get_odm_adaptivity(struct seq_file *m, void *v);
-+ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+#ifdef CONFIG_DBG_COUNTER
-+int proc_get_rx_logs(struct seq_file *m, void *v);
-+int proc_get_tx_logs(struct seq_file *m, void *v);
-+int proc_get_int_logs(struct seq_file *m, void *v);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+int proc_get_rx_ring(struct seq_file *m, void *v);
-+int proc_get_tx_ring(struct seq_file *m, void *v);
-+int proc_get_pci_aspm(struct seq_file *m, void *v);
-+int proc_get_pci_conf_space(struct seq_file *m, void *v);
-+ssize_t proc_set_pci_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+int proc_get_pci_bridge_conf_space(struct seq_file *m, void *v);
-+ssize_t proc_set_pci_bridge_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+
-+#ifdef DBG_TXBD_DESC_DUMP
-+int proc_get_tx_ring_ext(struct seq_file *m, void *v);
-+ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif
-+#endif
-+
-+#ifdef CONFIG_WOWLAN
-+int proc_get_wow_enable(struct seq_file *m, void *v);
-+ssize_t proc_set_wow_enable(struct file *file, const char __user *buffer,
-+		size_t count, loff_t *pos, void *data);
-+int proc_get_pattern_info(struct seq_file *m, void *v);
-+ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer,
-+		size_t count, loff_t *pos, void *data);
-+int proc_get_wakeup_event(struct seq_file *m, void *v);
-+ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer,
-+		size_t count, loff_t *pos, void *data);
-+int proc_get_wakeup_reason(struct seq_file *m, void *v);
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+int proc_dump_wow_keep_alive_info(struct seq_file *m, void *v);
-+#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+#endif
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+int proc_get_war_offload_enable(struct seq_file *m, void *v);
-+ssize_t proc_set_war_offload_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_war_offload_ipv4_addr(struct seq_file *m, void *v);
-+ssize_t proc_set_war_offload_ipv4_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_war_offload_ipv6_addr(struct seq_file *m, void *v);
-+ssize_t proc_set_war_offload_ipv6_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_war_offload_mdns_domain_name(struct seq_file *m, void *v);
-+ssize_t proc_set_war_offload_mdns_domain_name(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_war_offload_mdns_machine_name(struct seq_file *m, void *v);
-+ssize_t proc_set_war_offload_mdns_machine_name(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_war_offload_mdns_txt_rsp(struct seq_file *m, void *v);
-+ssize_t proc_set_war_offload_mdns_txt_rsp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_war_offload_mdns_service_info(struct seq_file *m, void *v);
-+ssize_t proc_set_war_offload_mdns_service_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif /* CONFIG_WAR_OFFLOAD */
-+
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+int proc_get_wowlan_gpio_info(struct seq_file *m, void *v);
-+ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer,
-+		size_t count, loff_t *pos, void *data);
-+#endif /*CONFIG_GPIO_WAKEUP*/
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+int proc_get_p2p_wowlan_info(struct seq_file *m, void *v);
-+#endif /* CONFIG_P2P_WOWLAN */
-+
-+int proc_get_new_bcn_max(struct seq_file *m, void *v);
-+ssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+#ifdef CONFIG_POWER_SAVING
-+int proc_get_ps_info(struct seq_file *m, void *v);
-+ssize_t proc_set_ps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#ifdef CONFIG_WMMPS_STA	
-+int proc_get_wmmps_info(struct seq_file *m, void *v);
-+ssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif /* CONFIG_WMMPS_STA */
-+#endif /* CONFIG_POWER_SAVING */
-+
-+#ifdef CONFIG_TDLS
-+int proc_get_tdls_enable(struct seq_file *m, void *v);
-+ssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_tdls_info(struct seq_file *m, void *v);
-+#endif
-+
-+int proc_get_monitor(struct seq_file *m, void *v);
-+ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+#ifdef RTW_SIMPLE_CONFIG
-+int proc_get_simple_config(struct seq_file *m, void *v);
-+ssize_t proc_set_simple_config(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif
-+
-+#ifdef DBG_XMIT_BLOCK
-+int proc_get_xmit_block(struct seq_file *m, void *v);
-+ssize_t proc_set_xmit_block(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif
-+
-+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
-+int proc_get_rtkm_info(struct seq_file *m, void *v);
-+#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
-+
-+#ifdef CONFIG_IEEE80211W
-+ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_tx_sa_query(struct seq_file *m, void *v);
-+ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_tx_deauth(struct seq_file *m, void *v);
-+ssize_t proc_set_tx_auth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_tx_auth(struct seq_file *m, void *v);
-+#endif /* CONFIG_IEEE80211W */
-+
-+#endif /* CONFIG_PROC_DEBUG */
-+
-+int proc_get_efuse_map(struct seq_file *m, void *v);
-+ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
-+int proc_get_pathb_phase(struct seq_file *m, void *v);
-+ssize_t proc_set_pathb_phase(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif
-+
-+#ifdef CONFIG_MCC_MODE
-+int proc_get_mcc_info(struct seq_file *m, void *v);
-+ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+ssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+ssize_t proc_set_mcc_phydm_offload_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif
-+ssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+ssize_t proc_set_mcc_ap_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+ssize_t proc_set_mcc_ap_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+ssize_t proc_set_mcc_ap_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+ssize_t proc_set_mcc_sta_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+ssize_t proc_set_mcc_sta_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+ssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_mcc_policy_table(struct seq_file *m, void *v);
-+#endif /* CONFIG_MCC_MODE */
-+
-+int proc_get_ack_timeout(struct seq_file *m, void *v);
-+ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+int proc_get_fw_offload(struct seq_file *m, void *v);
-+ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+ssize_t proc_set_fw_tbtt_rpt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_fw_tbtt_rpt(struct seq_file *m, void *v);
-+#endif
-+
-+#ifdef CONFIG_DBG_RF_CAL
-+int proc_get_iqk_info(struct seq_file *m, void *v);
-+ssize_t proc_set_iqk(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_lck_info(struct seq_file *m, void *v);
-+ssize_t proc_set_lck(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+#endif /*CONFIG_DBG_RF_CAL*/
-+
-+#ifdef CONFIG_CTRL_TXSS_BY_TP
-+ssize_t proc_set_txss_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_txss_tp(struct seq_file *m, void *v);
-+#ifdef DBG_CTRL_TXSS
-+ssize_t proc_set_txss_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_txss_ctrl(struct seq_file *m, void *v);
-+#endif
-+#endif
-+
-+#ifdef CONFIG_LPS_CHK_BY_TP
-+ssize_t proc_set_lps_chk_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_lps_chk_tp(struct seq_file *m, void *v);
-+#endif
-+
-+#ifdef CONFIG_SUPPORT_STATIC_SMPS
-+ssize_t proc_set_smps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+int proc_get_smps(struct seq_file *m, void *v);
-+#endif
-+
-+int proc_get_defs_param(struct seq_file *m, void *v);
-+ssize_t proc_set_defs_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+
-+#define _drv_always_		1
-+#define _drv_emerg_			2
-+#define _drv_alert_			3
-+#define _drv_crit_			4
-+#define _drv_err_			5
-+#define _drv_warning_		6
-+#define _drv_notice_		7
-+#define _drv_info_			8
-+#define _drv_dump_			9
-+#define _drv_debug_			10
-+
-+#define _module_rtl871x_xmit_c_		BIT(0)
-+#define _module_xmit_osdep_c_		BIT(1)
-+#define _module_rtl871x_recv_c_		BIT(2)
-+#define _module_recv_osdep_c_		BIT(3)
-+#define _module_rtl871x_mlme_c_		BIT(4)
-+#define _module_mlme_osdep_c_		BIT(5)
-+#define _module_rtl871x_sta_mgt_c_		BIT(6)
-+#define _module_rtl871x_cmd_c_			BIT(7)
-+#define _module_cmd_osdep_c_		BIT(8)
-+#define _module_rtl871x_io_c_				BIT(9)
-+#define _module_io_osdep_c_		BIT(10)
-+#define _module_os_intfs_c_			BIT(11)
-+#define _module_rtl871x_security_c_		BIT(12)
-+#define _module_rtl871x_eeprom_c_			BIT(13)
-+#define _module_hal_init_c_		BIT(14)
-+#define _module_hci_hal_init_c_		BIT(15)
-+#define _module_rtl871x_ioctl_c_		BIT(16)
-+#define _module_rtl871x_ioctl_set_c_		BIT(17)
-+#define _module_rtl871x_ioctl_query_c_	BIT(18)
-+#define _module_rtl871x_pwrctrl_c_			BIT(19)
-+#define _module_hci_intfs_c_			BIT(20)
-+#define _module_hci_ops_c_			BIT(21)
-+#define _module_osdep_service_c_			BIT(22)
-+#define _module_mp_			BIT(23)
-+#define _module_hci_ops_os_c_			BIT(24)
-+#define _module_rtl871x_ioctl_os_c		BIT(25)
-+#define _module_rtl8712_cmd_c_		BIT(26)
-+/* #define _module_efuse_			BIT(27) */
-+#define	_module_rtl8192c_xmit_c_ BIT(28)
-+#define _module_hal_xmit_c_	BIT(28)
-+#define _module_efuse_			BIT(29)
-+#define _module_rtl8712_recv_c_		BIT(30)
-+#define _module_rtl8712_led_c_		BIT(31)
-+
-+#endif /* __RTW_DEBUG_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_eeprom.h b/drivers/staging/rtl8723cs/include/rtw_eeprom.h
-new file mode 100644
-index 000000000000..62304d577f38
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_eeprom.h
-@@ -0,0 +1,116 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_EEPROM_H__
-+#define __RTW_EEPROM_H__
-+
-+
-+#define	RTL8712_EEPROM_ID			0x8712
-+/* #define	EEPROM_MAX_SIZE			256 */
-+
-+#define	HWSET_MAX_SIZE_128		128
-+#define	HWSET_MAX_SIZE_256		256
-+#define	HWSET_MAX_SIZE_512		512
-+#define HWSET_MAX_SIZE_1024		1024
-+
-+#define	EEPROM_MAX_SIZE			HWSET_MAX_SIZE_1024
-+
-+#define	CLOCK_RATE					50			/* 100us		 */
-+
-+/* - EEPROM opcodes */
-+#define EEPROM_READ_OPCODE		06
-+#define EEPROM_WRITE_OPCODE		05
-+#define EEPROM_ERASE_OPCODE		07
-+#define EEPROM_EWEN_OPCODE		19      /* Erase/write enable */
-+#define EEPROM_EWDS_OPCODE		16      /* Erase/write disable */
-+
-+/* Country codes */
-+#define USA							0x555320
-+#define EUROPE						0x1 /* temp, should be provided later	 */
-+#define JAPAN						0x2 /* temp, should be provided later */
-+
-+/*
-+ * Customer ID, note that:
-+ * This variable is initiailzed through EEPROM or registry,
-+ * however, its definition may be different with that in EEPROM for
-+ * EEPROM size consideration. So, we have to perform proper translation between them.
-+ * Besides, CustomerID of registry has precedence of that of EEPROM.
-+ * defined below. 060703, by rcnjko.
-+ *   */
-+typedef enum _RT_CUSTOMER_ID {
-+	RT_CID_DEFAULT = 0,
-+	RT_CID_8187_ALPHA0 = 1,
-+	RT_CID_8187_SERCOMM_PS = 2,
-+	RT_CID_8187_HW_LED = 3,
-+	RT_CID_8187_NETGEAR = 4,
-+	RT_CID_WHQL = 5,
-+	RT_CID_819x_CAMEO  = 6,
-+	RT_CID_819x_RUNTOP = 7,
-+	RT_CID_819x_Senao = 8,
-+	RT_CID_TOSHIBA = 9,	/* Merge by Jacken, 2008/01/31. */
-+	RT_CID_819x_Netcore = 10,
-+	RT_CID_Nettronix = 11,
-+	RT_CID_DLINK = 12,
-+	RT_CID_PRONET = 13,
-+	RT_CID_COREGA = 14,
-+	RT_CID_CHINA_MOBILE = 15,
-+	RT_CID_819x_ALPHA = 16,
-+	RT_CID_819x_Sitecom = 17,
-+	RT_CID_CCX = 18, /* It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. */
-+	RT_CID_819X_LENOVO = 19,
-+	RT_CID_819x_QMI = 20,
-+	RT_CID_819x_Edimax_Belkin = 21,
-+	RT_CID_819x_Sercomm_Belkin = 22,
-+	RT_CID_819x_CAMEO1 = 23,
-+	RT_CID_819x_MSI = 24,
-+	RT_CID_819X_ACER = 25,
-+	RT_CID_819x_AzWave_ASUS = 26,
-+	RT_CID_819x_AzWave = 27, /* For AzWave in PCIe, The ID is AzWave use and not only Asus */
-+	RT_CID_819x_HP = 28,
-+	RT_CID_819x_WNC_COREGA = 29,
-+	RT_CID_819x_Arcadyan_Belkin = 30,
-+	RT_CID_819x_SAMSUNG = 31,
-+	RT_CID_819x_CLEVO = 32,
-+	RT_CID_819x_DELL = 33,
-+	RT_CID_819x_PRONETS = 34,
-+	RT_CID_819x_Edimax_ASUS = 35,
-+	RT_CID_NETGEAR = 36,
-+	RT_CID_PLANEX = 37,
-+	RT_CID_CC_C = 38,
-+	RT_CID_819x_Xavi = 39,
-+	RT_CID_LENOVO_CHINA = 40,
-+	RT_CID_INTEL_CHINA = 41,
-+	RT_CID_TPLINK_HPWR = 42,
-+	RT_CID_819x_Sercomm_Netgear = 43,
-+	RT_CID_819x_ALPHA_Dlink = 44,/* add by ylb 20121012 for customer led for alpha */
-+	RT_CID_WNC_NEC = 45,/* add by page for NEC */
-+	RT_CID_DNI_BUFFALO = 46,/* add by page for NEC */
-+} RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
-+
-+extern void eeprom_write16(_adapter *padapter, u16 reg, u16 data);
-+extern u16 eeprom_read16(_adapter *padapter, u16 reg);
-+extern void read_eeprom_content(_adapter *padapter);
-+extern void eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz);
-+
-+extern void read_eeprom_content_by_attrib(_adapter	*padapter);
-+
-+#ifdef PLATFORM_LINUX
-+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
-+extern int isAdaptorInfoFileValid(void);
-+extern int storeAdaptorInfoFile(char *path, u8 *efuse_data);
-+extern int retriveAdaptorInfoFile(char *path, u8 *efuse_data);
-+#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */
-+#endif /* PLATFORM_LINUX */
-+
-+#endif /* __RTL871X_EEPROM_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_efuse.h b/drivers/staging/rtl8723cs/include/rtw_efuse.h
-new file mode 100644
-index 000000000000..9a07d27a4a3b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_efuse.h
-@@ -0,0 +1,285 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_EFUSE_H__
-+#define __RTW_EFUSE_H__
-+
-+
-+#define	EFUSE_ERROE_HANDLE		1
-+
-+#define	PG_STATE_HEADER		0x01
-+#define	PG_STATE_WORD_0		0x02
-+#define	PG_STATE_WORD_1		0x04
-+#define	PG_STATE_WORD_2		0x08
-+#define	PG_STATE_WORD_3		0x10
-+#define	PG_STATE_DATA			0x20
-+
-+#define	PG_SWBYTE_H			0x01
-+#define	PG_SWBYTE_L			0x02
-+
-+#define	PGPKT_DATA_SIZE		8
-+
-+#define	EFUSE_WIFI				0
-+#define	EFUSE_BT				1
-+
-+enum _EFUSE_DEF_TYPE {
-+	TYPE_EFUSE_MAX_SECTION				= 0,
-+	TYPE_EFUSE_REAL_CONTENT_LEN			= 1,
-+	TYPE_AVAILABLE_EFUSE_BYTES_BANK		= 2,
-+	TYPE_AVAILABLE_EFUSE_BYTES_TOTAL	= 3,
-+	TYPE_EFUSE_MAP_LEN					= 4,
-+	TYPE_EFUSE_PROTECT_BYTES_BANK		= 5,
-+	TYPE_EFUSE_CONTENT_LEN_BANK			= 6,
-+};
-+
-+#define		EFUSE_MAX_MAP_LEN		1024
-+
-+#define		EFUSE_MAX_HW_SIZE		1024
-+#define		EFUSE_MAX_SECTION_BASE	16
-+#define		EFUSE_MAX_SECTION_NUM	128
-+#define		EFUSE_MAX_BANK_SIZE		512
-+
-+/*RTL8822B 8821C BT EFUSE Define 1 BANK 128 size logical map 1024*/
-+#ifdef RTW_HALMAC
-+#define BANK_NUM		1
-+#if defined(CONFIG_RTL8723F)
-+#define EFUSE_BT_REAL_BANK_CONTENT_LEN		512
-+#else
-+#define EFUSE_BT_REAL_BANK_CONTENT_LEN		128
-+#endif
-+
-+#define EFUSE_BT_REAL_CONTENT_LEN		(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
-+#define EFUSE_BT_MAP_LEN				1024	/* 1k bytes */
-+#define EFUSE_BT_MAX_SECTION			(EFUSE_BT_MAP_LEN / 8)
-+
-+#if defined(CONFIG_RTL8822C)
-+#define EFUSE_PROTECT_BYTES_BANK		54
-+#elif defined(CONFIG_RTL8723F)
-+#define EFUSE_PROTECT_BYTES_BANK		40
-+#else
-+#define EFUSE_PROTECT_BYTES_BANK		16
-+#endif
-+#define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK)
-+#endif /* #ifdef RTW_HALMAC */
-+
-+#define EXT_HEADER(header) ((header & 0x1F) == 0x0F)
-+#define ALL_WORDS_DISABLED(wde)	((wde & 0x0F) == 0x0F)
-+#define GET_HDR_OFFSET_2_0(header) ((header & 0xE0) >> 5)
-+
-+#define		EFUSE_REPEAT_THRESHOLD_			3
-+
-+#define IS_MASKED_MP(ic, txt, offset) (EFUSE_IsAddressMasked_MP_##ic##txt(offset))
-+#define IS_MASKED_TC(ic, txt, offset) (EFUSE_IsAddressMasked_TC_##ic##txt(offset))
-+#define GET_MASK_ARRAY_LEN_MP(ic, txt) (EFUSE_GetArrayLen_MP_##ic##txt())
-+#define GET_MASK_ARRAY_LEN_TC(ic, txt) (EFUSE_GetArrayLen_TC_##ic##txt())
-+#define GET_MASK_ARRAY_MP(ic, txt, offset) (EFUSE_GetMaskArray_MP_##ic##txt(offset))
-+#define GET_MASK_ARRAY_TC(ic, txt, offset) (EFUSE_GetMaskArray_TC_##ic##txt(offset))
-+
-+
-+#define IS_MASKED(ic, txt, offset) (IS_MASKED_MP(ic, txt, offset))
-+#define GET_MASK_ARRAY_LEN(ic, txt) (GET_MASK_ARRAY_LEN_MP(ic, txt))
-+#define GET_MASK_ARRAY(ic, txt, out) do { GET_MASK_ARRAY_MP(ic, txt, out); } while (0)
-+
-+#ifdef CONFIG_BT_EFUSE_MASK
-+#define IS_BT_MASKED_MP(ic, txt, offset) (EFUSE_IsBTAddressMasked_MP_##ic##txt(offset))
-+#define GET_BT_MASK_ARRAY_LEN_MP(ic, txt) (EFUSE_GetBTArrayLen_MP_##ic##txt())
-+#define GET_BT_MASK_ARRAY_LEN_TC(ic, txt) (EFUSE_GetBTArrayLen_TC_##ic##txt())
-+#define GET_BT_MASK_ARRAY_MP(ic, txt, offset) (EFUSE_GetBTMaskArray_MP_##ic##txt(offset))
-+
-+#define IS_BT_MASKED(ic, txt, offset) (IS_BT_MASKED_MP(ic,txt, offset))
-+#define GET_BT_MASK_ARRAY(ic, txt, out) do { GET_BT_MASK_ARRAY_MP(ic,txt, out); } while(0)
-+#define GET_BT_MASK_ARRAY_LEN(ic, txt) (GET_BT_MASK_ARRAY_LEN_MP(ic,txt))
-+#endif
-+
-+/* *********************************************
-+ *	The following is for BT Efuse definition
-+ * ********************************************* */
-+#define		EFUSE_BT_MAX_MAP_LEN		1024
-+#define		EFUSE_MAX_BANK			4
-+#define		EFUSE_MAX_BT_BANK		(EFUSE_MAX_BANK-1)
-+/* *********************************************
-+ *--------------------------Define Parameters-------------------------------*/
-+#define		EFUSE_MAX_WORD_UNIT			4
-+
-+/*------------------------------Define structure----------------------------*/
-+typedef struct PG_PKT_STRUCT_A {
-+	u8 offset;
-+	u8 word_en;
-+	u8 data[8];
-+	u8 word_cnts;
-+} PGPKT_STRUCT, *PPGPKT_STRUCT;
-+
-+typedef enum {
-+	ERR_SUCCESS = 0,
-+	ERR_DRIVER_FAILURE,
-+	ERR_IO_FAILURE,
-+	ERR_WI_TIMEOUT,
-+	ERR_WI_BUSY,
-+	ERR_BAD_FORMAT,
-+	ERR_INVALID_DATA,
-+	ERR_NOT_ENOUGH_SPACE,
-+	ERR_WRITE_PROTECT,
-+	ERR_READ_BACK_FAIL,
-+	ERR_OUT_OF_RANGE
-+} ERROR_CODE;
-+
-+/*------------------------------Define structure----------------------------*/
-+typedef struct _EFUSE_HAL {
-+	u8	fakeEfuseBank;
-+	u32	fakeEfuseUsedBytes;
-+	u8	fakeEfuseContent[EFUSE_MAX_HW_SIZE];
-+	u8	fakeEfuseInitMap[EFUSE_MAX_MAP_LEN];
-+	u8	fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN];
-+	u32	EfuseUsedBytes;
-+	u8	EfuseUsedPercentage;
-+
-+	u16	BTEfuseUsedBytes;
-+	u8	BTEfuseUsedPercentage;
-+	u8	BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
-+	u8	BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN];
-+	u8	BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN];
-+
-+	u16	fakeBTEfuseUsedBytes;
-+	u8	fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
-+	u8	fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN];
-+	u8	fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN];
-+
-+	/* EFUSE Configuration, initialized in HAL_CmnInitPGData(). */
-+	const u16  MaxSecNum_WiFi;
-+	const u16  MaxSecNum_BT;
-+	const u16  WordUnit;
-+	const u16  PhysicalLen_WiFi;
-+	const u16  PhysicalLen_BT;
-+	const u16  LogicalLen_WiFi;
-+	const u16  LogicalLen_BT;
-+	const u16  BankSize;
-+	const u16  TotalBankNum;
-+	const u16  BankNum_WiFi;
-+	const u16  BankNum_BT;
-+	const u16  OOBProtectBytes;
-+	const u16  ProtectBytes;
-+	const u16  BankAvailBytes;
-+	const u16  TotalAvailBytes_WiFi;
-+	const u16  TotalAvailBytes_BT;
-+	const u16  HeaderRetry;
-+	const u16  DataRetry;
-+
-+	ERROR_CODE	  Status;
-+
-+} EFUSE_HAL, *PEFUSE_HAL;
-+
-+extern u8 maskfileBuffer[64];
-+extern u8 btmaskfileBuffer[64];
-+
-+/*------------------------Export global variable----------------------------*/
-+extern u8 fakeEfuseBank;
-+extern u32 fakeEfuseUsedBytes;
-+extern u8 fakeEfuseContent[];
-+extern u8 fakeEfuseInitMap[];
-+extern u8 fakeEfuseModifiedMap[];
-+
-+extern u32 BTEfuseUsedBytes;
-+extern u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
-+extern u8 BTEfuseInitMap[];
-+extern u8 BTEfuseModifiedMap[];
-+
-+extern u32 fakeBTEfuseUsedBytes;
-+extern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
-+extern u8 fakeBTEfuseInitMap[];
-+extern u8 fakeBTEfuseModifiedMap[];
-+/*------------------------Export global variable----------------------------*/
-+#define		MAX_SEGMENT_SIZE			200
-+#define		MAX_SEGMENT_NUM			200
-+#define		MAX_BUF_SIZE				(MAX_SEGMENT_SIZE*MAX_SEGMENT_NUM)
-+#define		TMP_BUF_SIZE				100
-+#define		rtprintf					dcmd_Store_Return_Buf
-+
-+u8	efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size);
-+u16	efuse_bt_GetMaxSize(PADAPTER padapter);
-+u16 efuse_GetavailableSize(PADAPTER adapter);
-+
-+u8	efuse_GetCurrentSize(PADAPTER padapter, u16 *size);
-+u16	efuse_GetMaxSize(PADAPTER padapter);
-+u8	rtw_efuse_access(PADAPTER padapter, u8 bRead, u16 start_addr, u16 cnts, u8 *data);
-+u8	rtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data);
-+
-+u8	rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
-+u8	rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
-+u8	rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
-+u8	rtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
-+u8	rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data);
-+#ifdef CONFIG_RTL8822C
-+void	rtw_pre_bt_efuse(PADAPTER padapter);
-+#endif
-+u16	Efuse_GetCurrentSize(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest);
-+u8	Efuse_CalculateWordCnts(u8 word_en);
-+void	ReadEFuseByte(PADAPTER Adapter, u16 _offset, u8 *pbuf, BOOLEAN bPseudoTest) ;
-+void	EFUSE_GetEfuseDefinition(PADAPTER pAdapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);
-+u8	efuse_OneByteRead(PADAPTER pAdapter, u16 addr, u8 *data, BOOLEAN	 bPseudoTest);
-+#define efuse_onebyte_read(adapter, addr, data, pseudo_test) efuse_OneByteRead((adapter), (addr), (data), (pseudo_test))
-+
-+u8	efuse_OneByteWrite(PADAPTER pAdapter, u16 addr, u8 data, BOOLEAN	 bPseudoTest);
-+
-+void	BTEfuse_PowerSwitch(PADAPTER pAdapter, u8	bWrite, u8	 PwrState);
-+void	Efuse_PowerSwitch(PADAPTER pAdapter, u8	bWrite, u8	 PwrState);
-+int	Efuse_PgPacketRead(PADAPTER pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
-+int	Efuse_PgPacketWrite(PADAPTER pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
-+void	efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata);
-+u8	Efuse_WordEnableDataWrite(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
-+void	EFUSE_ShadowMapUpdate(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest);
-+void	EFUSE_ShadowRead(PADAPTER pAdapter, u8 Type, u16 Offset, u32 *Value);
-+#define efuse_logical_map_read(adapter, type, offset, value) EFUSE_ShadowRead((adapter), (type), (offset), (value))
-+
-+BOOLEAN rtw_file_efuse_IsMasked(PADAPTER pAdapter, u16 Offset, u8 *maskbuf);
-+BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset);
-+
-+void	hal_ReadEFuse_BT_logic_map(
-+	PADAPTER	padapter,
-+	u16			_offset,
-+	u16			_size_byte,
-+	u8			*pbuf
-+);
-+u8	EfusePgPacketWrite_BT(
-+	PADAPTER	pAdapter,
-+	u8			offset,
-+	u8			word_en,
-+	u8			*pData,
-+	u8			bPseudoTest);
-+
-+u16 rtw_get_bt_efuse_mask_arraylen(PADAPTER pAdapter);
-+void rtw_bt_efuse_mask_array(PADAPTER pAdapter, u8 *pArray);
-+u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter);
-+void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray);
-+void rtw_efuse_analyze(PADAPTER	padapter, u8 Type, u8 Fake);
-+
-+#define MAC_HIDDEN_MAX_BW_NUM 8
-+extern const u8 _mac_hidden_max_bw_to_hal_bw_cap[];
-+#define mac_hidden_max_bw_to_hal_bw_cap(max_bw) (((max_bw) >= MAC_HIDDEN_MAX_BW_NUM) ? 0 : _mac_hidden_max_bw_to_hal_bw_cap[(max_bw)])
-+
-+#define MAC_HIDDEN_PROTOCOL_NUM 4
-+extern const u8 _mac_hidden_proto_to_hal_proto_cap[];
-+#define mac_hidden_proto_to_hal_proto_cap(proto) (((proto) >= MAC_HIDDEN_PROTOCOL_NUM) ? 0 : _mac_hidden_proto_to_hal_proto_cap[(proto)])
-+
-+u8 mac_hidden_wl_func_to_hal_wl_func(u8 func);
-+
-+#ifdef PLATFORM_LINUX
-+u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepath, u8 *buf, u32 len);
-+u8 rtw_efuse_file_store(PADAPTER padapter, u8 *filepath, u8 *buf, u32 len);
-+#ifdef CONFIG_EFUSE_CONFIG_FILE
-+u32 rtw_read_efuse_from_file(const char *path, u8 *buf, int map_size);
-+u32 rtw_read_macaddr_from_file(const char *path, u8 *buf);
-+#endif /* CONFIG_EFUSE_CONFIG_FILE */
-+#endif /* PLATFORM_LINUX */
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtw_event.h b/drivers/staging/rtl8723cs/include/rtw_event.h
-new file mode 100644
-index 000000000000..13e3f5287116
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_event.h
-@@ -0,0 +1,95 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTW_EVENT_H_
-+#define _RTW_EVENT_H_
-+
-+#ifdef CONFIG_H2CLBK
-+	#include <h2clbk.h>
-+#endif
-+
-+/*
-+Used to report a bss has been scanned
-+
-+*/
-+struct survey_event	{
-+	WLAN_BSSID_EX bss;
-+};
-+
-+/*
-+Used to report that the requested site survey has been done.
-+
-+bss_cnt indicates the number of bss that has been reported.
-+
-+
-+*/
-+struct surveydone_event {
-+	unsigned int	bss_cnt;
-+	u8 activate_ch_cnt;
-+	bool acs; /* aim to trigger channel selection */
-+};
-+
-+/*
-+Used to report the link result of joinning the given bss
-+
-+
-+join_res:
-+-1: authentication fail
-+-2: association fail
-+> 0: TID
-+
-+*/
-+struct joinbss_event {
-+	struct	wlan_network	network;
-+};
-+
-+/*
-+Used to report a given STA has joinned the created BSS.
-+It is used in AP/Ad-HoC(M) mode.
-+
-+
-+*/
-+struct stassoc_event {
-+	unsigned char macaddr[6];
-+};
-+
-+struct stadel_event {
-+	unsigned char macaddr[6];
-+	unsigned char rsvd[2]; /* for reason */
-+	unsigned char locally_generated;
-+	int mac_id;
-+};
-+
-+struct wmm_event {
-+	unsigned char wmm;
-+};
-+
-+#ifdef CONFIG_H2CLBK
-+struct c2hlbk_event {
-+	unsigned char mac[6];
-+	unsigned short	s0;
-+	unsigned short	s1;
-+	unsigned int	w0;
-+	unsigned char	b0;
-+	unsigned short  s2;
-+	unsigned char	b1;
-+	unsigned int	w1;
-+};
-+#endif/* CONFIG_H2CLBK */
-+
-+struct rtw_event {
-+	u32 parmsize;
-+	void (*event_callback)(_adapter *dev, u8 *pbuf);
-+};
-+#endif /* _WLANEVENT_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_ft.h b/drivers/staging/rtl8723cs/include/rtw_ft.h
-new file mode 100644
-index 000000000000..025f19e6729b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_ft.h
-@@ -0,0 +1,183 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __RTW_FT_H_
-+#define __RTW_FT_H_
-+
-+enum rtw_ieee80211_ft_actioncode {
-+	RTW_WLAN_ACTION_FT_RESV,
-+	RTW_WLAN_ACTION_FT_REQ,
-+	RTW_WLAN_ACTION_FT_RSP,
-+	RTW_WLAN_ACTION_FT_CONF,
-+	RTW_WLAN_ACTION_FT_ACK,
-+	RTW_WLAN_ACTION_FT_MAX,
-+};
-+
-+enum _rtw_ft_sta_status {
-+	RTW_FT_UNASSOCIATED_STA = 0,
-+	RTW_FT_AUTHENTICATING_STA,
-+	RTW_FT_AUTHENTICATED_STA,
-+	RTW_FT_ASSOCIATING_STA,
-+	RTW_FT_ASSOCIATED_STA,
-+	RTW_FT_REQUESTING_STA,
-+	RTW_FT_REQUESTED_STA,
-+	RTW_FT_CONFIRMED_STA,
-+	RTW_FT_UNSPECIFIED_STA
-+};
-+
-+#define RTW_FT_ACTION_REQ_LMT	4
-+
-+#define RTW_FT_MAX_IE_SZ	256
-+
-+#define rtw_ft_chk_status(a, s) \
-+	((a)->mlmepriv.ft_roam.ft_status == (s))
-+
-+#define rtw_ft_roam_status(a, s)	\
-+	((rtw_to_roam(a) > 0) && rtw_ft_chk_status(a, s))
-+
-+#define rtw_ft_authed_sta(a)	\
-+	((rtw_ft_chk_status(a, RTW_FT_AUTHENTICATED_STA)) ||	\
-+	(rtw_ft_chk_status(a, RTW_FT_ASSOCIATING_STA)) ||	\
-+	(rtw_ft_chk_status(a, RTW_FT_ASSOCIATED_STA)))
-+
-+#define rtw_ft_set_status(a, s) \
-+	do { \
-+		((a)->mlmepriv.ft_roam.ft_status = (s)); \
-+	} while (0)
-+
-+#define rtw_ft_lock_set_status(a, s, irq) \
-+	do { \
-+		_enter_critical_bh(&(a)->mlmepriv.lock, ((_irqL *)(irq)));	\
-+		((a)->mlmepriv.ft_roam.ft_status = (s));	\
-+		_exit_critical_bh(&(a)->mlmepriv.lock, ((_irqL *)(irq)));	\
-+	} while (0)
-+
-+#define rtw_ft_reset_status(a) \
-+	do { \
-+		((a)->mlmepriv.ft_roam.ft_status = RTW_FT_UNASSOCIATED_STA); \
-+	} while (0)
-+
-+enum rtw_ft_capability {
-+	RTW_FT_EN = BIT0,
-+	RTW_FT_OTD_EN = BIT1,
-+	RTW_FT_PEER_EN = BIT2,
-+	RTW_FT_PEER_OTD_EN = BIT3,
-+	RTW_FT_BTM_ROAM = BIT4,
-+	RTW_FT_TEST_RSSI_ROAM = BIT7,
-+};
-+
-+#define rtw_ft_chk_flags(a, f) \
-+	((a)->mlmepriv.ft_roam.ft_flags & (f))
-+
-+#define rtw_ft_set_flags(a, f) \
-+	do { \
-+		((a)->mlmepriv.ft_roam.ft_flags |= (f)); \
-+	} while (0)
-+
-+#define rtw_ft_clr_flags(a, f) \
-+	do { \
-+		((a)->mlmepriv.ft_roam.ft_flags &= ~(f)); \
-+	} while (0)
-+
-+#define rtw_ft_roam(a)	\
-+	((rtw_to_roam(a) > 0) && rtw_ft_chk_flags(a, RTW_FT_PEER_EN))
-+	
-+#define rtw_ft_valid_akm(a, t)	\
-+	((rtw_ft_chk_flags(a, RTW_FT_EN)) && \
-+	(((t) == 3) || ((t) == 4)))
-+
-+#define rtw_ft_roam_expired(a, r)	\
-+	((rtw_chk_roam_flags(a, RTW_ROAM_ON_EXPIRED)) \
-+	&& (r == WLAN_REASON_ACTIVE_ROAM))
-+
-+#define rtw_ft_otd_roam_en(a)	\
-+	((rtw_ft_chk_flags(a, RTW_FT_OTD_EN))	\
-+	&& ((a)->mlmepriv.ft_roam.ft_roam_on_expired == _FALSE)	\
-+	&& ((a)->mlmepriv.ft_roam.ft_cap & 0x01))
-+	
-+#define rtw_ft_otd_roam(a) \
-+	rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN)
-+
-+#define rtw_ft_valid_otd_candidate(a, p)	\
-+	((rtw_ft_chk_flags(a, RTW_FT_OTD_EN)) 	\
-+	&& ((rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN)	\
-+	&& ((*((p)+4) & 0x01) == 0))	\
-+	|| ((rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN) == 0)	\
-+	&& (*((p)+4) & 0x01))))
-+
-+struct ft_roam_info {
-+	u16	mdid;
-+	u8	ft_cap;	
-+	/*b0: FT over DS, b1: Resource Req Protocol Cap, b2~b7: Reserved*/
-+	u8	updated_ft_ies[RTW_FT_MAX_IE_SZ];
-+	u16	updated_ft_ies_len;
-+	u8	ft_action[RTW_FT_MAX_IE_SZ];
-+	u16	ft_action_len;
-+	struct cfg80211_ft_event_params ft_event;
-+	u8	ft_roam_on_expired;
-+	u8	ft_flags;
-+	u32 ft_status;
-+	u32 ft_req_retry_cnt;
-+	bool ft_updated_bcn;	
-+};
-+
-+void rtw_ft_info_init(struct ft_roam_info *pft);
-+
-+int rtw_ft_proc_flags_get(struct seq_file *m, void *v);
-+
-+ssize_t rtw_ft_proc_flags_set(struct file *file, const char __user *buffer,
-+	size_t count, loff_t *pos, void *data);
-+
-+u8 rtw_ft_chk_roaming_candidate(
-+	_adapter *padapter, struct wlan_network *competitor);
-+
-+void rtw_ft_update_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork);
-+
-+void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf);
-+
-+void rtw_ft_validate_akm_type(_adapter  *padapter,
-+	struct wlan_network *pnetwork);
-+
-+void rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame);
-+
-+void rtw_ft_start_clnt_join(_adapter *padapter);
-+
-+u8 rtw_ft_update_rsnie(
-+	_adapter *padapter, u8 bwrite, 
-+	struct pkt_attrib *pattrib, u8 **pframe);
-+
-+void rtw_ft_build_auth_req_ies(_adapter *padapter, 
-+	struct pkt_attrib *pattrib, u8 **pframe);
-+
-+void rtw_ft_build_assoc_req_ies(_adapter *padapter, 
-+	u8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe);
-+
-+u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len);
-+
-+void rtw_ft_start_roam(_adapter *padapter, u8 *pTargetAddr);
-+
-+void rtw_ft_issue_action_req(_adapter *padapter, u8 *pTargetAddr);
-+
-+void rtw_ft_report_evt(_adapter *padapter);
-+
-+void rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr);
-+
-+void rtw_ft_link_timer_hdl(void *ctx);
-+
-+void rtw_ft_roam_timer_hdl(void *ctx);
-+
-+void rtw_ft_roam_status_reset(_adapter *padapter);
-+
-+#endif /* __RTW_FT_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_ht.h b/drivers/staging/rtl8723cs/include/rtw_ht.h
-new file mode 100644
-index 000000000000..8237bbe76603
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_ht.h
-@@ -0,0 +1,217 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTW_HT_H_
-+#define _RTW_HT_H_
-+
-+#define HT_CAP_IE_LEN 26
-+#define HT_OP_IE_LEN 22
-+
-+struct ht_priv {
-+	u8	ht_option;
-+	u8	ampdu_enable;/* for enable Tx A-MPDU */
-+	u8	tx_amsdu_enable;/* for enable Tx A-MSDU */
-+	u8	bss_coexist;/* for 20/40 Bss coexist */
-+
-+	/* u8	baddbareq_issued[16]; */
-+	u32	tx_amsdu_maxlen; /* 1: 8k, 0:4k ; default:8k, for tx */
-+	u32	rx_ampdu_maxlen; /* for rx reordering ctrl win_sz, updated when join_callback. */
-+
-+	u8	rx_ampdu_min_spacing;
-+
-+	u8	ch_offset;/* PRIME_CHNL_OFFSET */
-+	u8	sgi_20m;
-+	u8	sgi_40m;
-+
-+	/* for processing Tx A-MPDU */
-+	u8	agg_enable_bitmap;
-+	/* u8	ADDBA_retry_count; */
-+	u8	candidate_tid_bitmap;
-+
-+	u8	ldpc_cap;
-+	u8	stbc_cap;
-+	u8	beamform_cap;
-+	u8	smps_cap; /*spatial multiplexing power save mode. 0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/
-+
-+	u8 op_present:1; /* ht_op is present */
-+
-+	struct rtw_ieee80211_ht_cap ht_cap;
-+	u8 ht_op[HT_OP_IE_LEN];
-+
-+};
-+
-+#ifdef ROKU_PRIVATE
-+struct ht_priv_infra_ap {
-+
-+	/*Infra mode, only store AP's info , not intersection of STA and AP*/
-+	u8	channel_width_infra_ap;
-+	u8	sgi_20m_infra_ap;
-+	u8	sgi_40m_infra_ap;
-+	u8	ldpc_cap_infra_ap;
-+	u8	stbc_cap_infra_ap;
-+	u8	MCS_set_infra_ap[16];
-+	u8	Rx_ss_infra_ap;
-+	u16	rx_highest_data_rate_infra_ap;
-+};
-+#endif /* ROKU_PRIVATE */
-+
-+typedef enum AGGRE_SIZE {
-+	HT_AGG_SIZE_8K = 0,
-+	HT_AGG_SIZE_16K = 1,
-+	HT_AGG_SIZE_32K = 2,
-+	HT_AGG_SIZE_64K = 3,
-+	VHT_AGG_SIZE_128K = 4,
-+	VHT_AGG_SIZE_256K = 5,
-+	VHT_AGG_SIZE_512K = 6,
-+	VHT_AGG_SIZE_1024K = 7,
-+} AGGRE_SIZE_E, *PAGGRE_SIZE_E;
-+
-+#define	LDPC_HT_ENABLE_RX			BIT0
-+#define	LDPC_HT_ENABLE_TX			BIT1
-+#define	LDPC_HT_TEST_TX_ENABLE		BIT2
-+#define	LDPC_HT_CAP_TX				BIT3
-+
-+#define	STBC_HT_ENABLE_RX			BIT0
-+#define	STBC_HT_ENABLE_TX			BIT1
-+#define	STBC_HT_TEST_TX_ENABLE		BIT2
-+#define	STBC_HT_CAP_TX				BIT3
-+
-+/* ------------------------------------------------------------
-+ * The HT Control field
-+ * ------------------------------------------------------------ */
-+#define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+2, 6, 2, _val)
-+#define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+3, 0, 1, _val)
-+#define GET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+3, 0, 1)
-+
-+/* 20/40 BSS Coexist */
-+#define SET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 1, _val)
-+#define GET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 1)
-+
-+/* HT Capabilities Info field */
-+#define HT_CAP_ELE_CAP_INFO(_pEleStart)					((u8 *)(_pEleStart))
-+#define GET_HT_CAP_ELE_LDPC_CAP(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 1)
-+#define GET_HT_CAP_ELE_CHL_WIDTH(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 1, 1)
-+#define GET_HT_CAP_ELE_SM_PS(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 2, 2)
-+#define GET_HT_CAP_ELE_GREENFIELD(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 4, 1)
-+#define GET_HT_CAP_ELE_SHORT_GI20M(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 5, 1)
-+#define GET_HT_CAP_ELE_SHORT_GI40M(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 6, 1)
-+#define GET_HT_CAP_ELE_TX_STBC(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 7, 1)
-+#define GET_HT_CAP_ELE_RX_STBC(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 0, 2)
-+#define GET_HT_CAP_ELE_DELAYED_BA(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 2, 1)
-+#define GET_HT_CAP_ELE_MAX_AMSDU_LENGTH(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 3, 1)
-+#define GET_HT_CAP_ELE_DSSS_CCK_40M(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 4, 1)
-+#define GET_HT_CAP_ELE_FORTY_INTOLERANT(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 6, 1)
-+#define GET_HT_CAP_ELE_LSIG_TXOP_PROTECT(_pEleStart)	LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 7, 1)
-+
-+#define SET_HT_CAP_ELE_LDPC_CAP(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 1, _val)
-+#define SET_HT_CAP_ELE_CHL_WIDTH(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 1, 1, _val)
-+#define SET_HT_CAP_ELE_SM_PS(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 2, 2, _val)
-+#define SET_HT_CAP_ELE_GREENFIELD(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 4, 1, _val)
-+#define SET_HT_CAP_ELE_SHORT_GI20M(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 5, 1, _val)
-+#define SET_HT_CAP_ELE_SHORT_GI40M(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 6, 1, _val)
-+#define SET_HT_CAP_ELE_TX_STBC(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 7, 1, _val)
-+#define SET_HT_CAP_ELE_RX_STBC(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2, _val)
-+#define SET_HT_CAP_ELE_DELAYED_BA(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1, _val)
-+#define SET_HT_CAP_ELE_MAX_AMSDU_LENGTH(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1, _val)
-+#define SET_HT_CAP_ELE_DSSS_CCK_40M(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 4, 1, _val)
-+#define SET_HT_CAP_ELE_FORTY_INTOLERANT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 6, 1, _val)
-+#define SET_HT_CAP_ELE_LSIG_TXOP_PROTECT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 7, 1, _val)
-+
-+/* A-MPDU Parameters field */
-+#define HT_CAP_ELE_AMPDU_PARA(_pEleStart)				(((u8 *)(_pEleStart))+2)
-+#define GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(_pEleStart)	LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+2, 0, 2)
-+#define GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+2, 2, 3)
-+
-+#define HT_AMPDU_PARA_FMT "%02x " \
-+	"MAX AMPDU len:%u bytes, MIN MPDU Start Spacing:%u"
-+
-+#define HT_AMPDU_PARA_ARG(x) \
-+	*((u8 *)(x)) \
-+	, (1 << (13+GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(((u8 *)x)-2)))-1 \
-+	, GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(((u8 *)x)-2)
-+
-+#define SET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2, _val)
-+#define SET_HT_CAP_ELE_MIN_MPDU_S_SPACE(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 3, _val)
-+
-+/* Supported MCS Set field */
-+#define HT_CAP_ELE_SUP_MCS_SET(_pEleStart)				(((u8 *)(_pEleStart))+3)
-+#define HT_CAP_ELE_RX_MCS_MAP(_pEleStart)				HT_CAP_ELE_SUP_MCS_SET(_pEleStart)
-+#define GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(_pEleStart)	LE_BITS_TO_2BYTE(((u8 *)(_pEleStart))+13, 0, 10)
-+#define GET_HT_CAP_ELE_TX_MCS_DEF(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 0, 1)
-+#define GET_HT_CAP_ELE_TRX_MCS_NEQ(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 1, 1)
-+#define GET_HT_CAP_ELE_TX_MAX_SS(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 2, 2)
-+#define GET_HT_CAP_ELE_TX_UEQM(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 4, 1)
-+
-+#define HT_RX_MCS_BMP_FMT "%02x %02x %02x %02x %02x%02x%02x%02x%02x%02x"
-+#define HT_RX_MCS_BMP_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \
-+	((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9]
-+
-+#define HT_SUP_MCS_SET_FMT HT_RX_MCS_BMP_FMT \
-+	/* "\n%02x%02x%02x%02x%02x%02x" */\
-+	" %uMbps %s%s%s"
-+#define HT_SUP_MCS_SET_ARG(x) HT_RX_MCS_BMP_ARG(x) \
-+	/*,((u8 *)(x))[10], ((u8 *)(x))[11], ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15] */\
-+	, GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(((u8 *)x)-3) \
-+	, GET_HT_CAP_ELE_TX_MCS_DEF(((u8 *)x)-3) ? "TX_MCS_DEF " : "" \
-+	, GET_HT_CAP_ELE_TRX_MCS_NEQ(((u8 *)x)-3) ? "TRX_MCS_NEQ " : "" \
-+	, GET_HT_CAP_ELE_TX_UEQM(((u8 *)x)-3) ? "TX_UEQM " : ""
-+
-+/* TXBF Capabilities */
-+#define SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(_pEleStart, _val)				SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 3, 1, ((u8)_val))
-+#define SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(_pEleStart, _val)				SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 4, 1, ((u8)_val))
-+#define SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 10, 1, ((u8)_val))
-+#define SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 15, 2, ((u8)_val))
-+#define SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 23, 2, ((u8)_val))
-+#define SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 27, 2, ((u8)_val))
-+
-+
-+#define GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart)			LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 10, 1)
-+#define GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart)			LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 15, 2)
-+#define GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart)		LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 23, 2)
-+#define GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(_pEleStart)		LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 27, 2)
-+
-+/* HT Operation element */
-+
-+#define GET_HT_OP_ELE_PRI_CHL(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 8)
-+#define SET_HT_OP_ELE_PRI_CHL(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 8, _val)
-+
-+/* HT Operation Info field */
-+#define HT_OP_ELE_OP_INFO(_pEleStart)						(((u8 *)(_pEleStart)) + 1)
-+#define GET_HT_OP_ELE_2ND_CHL_OFFSET(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2)
-+#define GET_HT_OP_ELE_STA_CHL_WIDTH(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1)
-+#define GET_HT_OP_ELE_RIFS_MODE(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1)
-+#define GET_HT_OP_ELE_HT_PROTECT(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2)
-+#define GET_HT_OP_ELE_NON_GREEN_PRESENT(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 1)
-+#define GET_HT_OP_ELE_OBSS_NON_HT_PRESENT(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 4, 1)
-+#define GET_HT_OP_ELE_DUAL_BEACON(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 4, 6, 1)
-+#define GET_HT_OP_ELE_DUAL_CTS(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 4, 7, 1)
-+#define GET_HT_OP_ELE_STBC_BEACON(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 0, 1)
-+#define GET_HT_OP_ELE_LSIG_TXOP_PROTECT(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 1, 1)
-+#define GET_HT_OP_ELE_PCO_ACTIVE(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 2, 1)
-+#define GET_HT_OP_ELE_PCO_PHASE(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 3, 1)
-+
-+#define SET_HT_OP_ELE_2ND_CHL_OFFSET(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2, _val)
-+#define SET_HT_OP_ELE_STA_CHL_WIDTH(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1, _val)
-+#define SET_HT_OP_ELE_RIFS_MODE(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1, _val)
-+#define SET_HT_OP_ELE_HT_PROTECT(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2, _val)
-+#define SET_HT_OP_ELE_NON_GREEN_PRESENT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 1, _val)
-+#define SET_HT_OP_ELE_OBSS_NON_HT_PRESENT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 4, 1, _val)
-+#define SET_HT_OP_ELE_DUAL_BEACON(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 4, 6, 1, _val)
-+#define SET_HT_OP_ELE_DUAL_CTS(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 4, 7, 1, _val)
-+#define SET_HT_OP_ELE_STBC_BEACON(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 0, 1, _val)
-+#define SET_HT_OP_ELE_LSIG_TXOP_PROTECT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 1, 1, _val)
-+#define SET_HT_OP_ELE_PCO_ACTIVE(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 2, 1, _val)
-+#define SET_HT_OP_ELE_PCO_PHASE(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 3, 1, _val)
-+
-+#endif /* _RTL871X_HT_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_io.h b/drivers/staging/rtl8723cs/include/rtw_io.h
-new file mode 100644
-index 000000000000..50291e1b88c7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_io.h
-@@ -0,0 +1,526 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef _RTW_IO_H_
-+#define _RTW_IO_H_
-+
-+#define NUM_IOREQ		8
-+
-+#ifdef PLATFORM_LINUX
-+	#define MAX_PROT_SZ	(64-16)
-+#endif
-+
-+#define _IOREADY			0
-+#define _IO_WAIT_COMPLETE   1
-+#define _IO_WAIT_RSP        2
-+
-+/* IO COMMAND TYPE */
-+#define _IOSZ_MASK_		(0x7F)
-+#define _IO_WRITE_		BIT(7)
-+#define _IO_FIXED_		BIT(8)
-+#define _IO_BURST_		BIT(9)
-+#define _IO_BYTE_		BIT(10)
-+#define _IO_HW_			BIT(11)
-+#define _IO_WORD_		BIT(12)
-+#define _IO_SYNC_		BIT(13)
-+#define _IO_CMDMASK_	(0x1F80)
-+
-+
-+/*
-+	For prompt mode accessing, caller shall free io_req
-+	Otherwise, io_handler will free io_req
-+*/
-+
-+
-+
-+/* IO STATUS TYPE */
-+#define _IO_ERR_		BIT(2)
-+#define _IO_SUCCESS_	BIT(1)
-+#define _IO_DONE_		BIT(0)
-+
-+
-+#define IO_RD32			(_IO_SYNC_ | _IO_WORD_)
-+#define IO_RD16			(_IO_SYNC_ | _IO_HW_)
-+#define IO_RD8			(_IO_SYNC_ | _IO_BYTE_)
-+
-+#define IO_RD32_ASYNC	(_IO_WORD_)
-+#define IO_RD16_ASYNC	(_IO_HW_)
-+#define IO_RD8_ASYNC	(_IO_BYTE_)
-+
-+#define IO_WR32			(_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_)
-+#define IO_WR16			(_IO_WRITE_ | _IO_SYNC_ | _IO_HW_)
-+#define IO_WR8			(_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_)
-+
-+#define IO_WR32_ASYNC	(_IO_WRITE_ | _IO_WORD_)
-+#define IO_WR16_ASYNC	(_IO_WRITE_ | _IO_HW_)
-+#define IO_WR8_ASYNC	(_IO_WRITE_ | _IO_BYTE_)
-+
-+/*
-+
-+	Only Sync. burst accessing is provided.
-+
-+*/
-+
-+#define IO_WR_BURST(x)		(_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_))
-+#define IO_RD_BURST(x)		(_IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_))
-+
-+
-+
-+/* below is for the intf_option bit defition... */
-+
-+#define _INTF_ASYNC_	BIT(0)	/* support async io */
-+
-+struct intf_priv;
-+struct intf_hdl;
-+struct io_queue;
-+
-+struct _io_ops {
-+	u8(*_read8)(struct intf_hdl *pintfhdl, u32 addr);
-+	u16(*_read16)(struct intf_hdl *pintfhdl, u32 addr);
-+	u32(*_read32)(struct intf_hdl *pintfhdl, u32 addr);
-+
-+	int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
-+	int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
-+	int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
-+	int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
-+
-+	int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
-+	int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
-+	int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
-+
-+	void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
-+	void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
-+
-+	void (*_sync_irp_protocol_rw)(struct io_queue *pio_q);
-+
-+	u32(*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
-+
-+	u32(*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
-+	u32(*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
-+
-+	u32(*_write_scsi)(struct intf_hdl *pintfhdl, u32 cnt, u8 *pmem);
-+
-+	void (*_read_port_cancel)(struct intf_hdl *pintfhdl);
-+	void (*_write_port_cancel)(struct intf_hdl *pintfhdl);
-+
-+#ifdef CONFIG_SDIO_HCI
-+	u8(*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr);
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+	u8(*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr);
-+	u16(*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr);
-+	u32(*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr);
-+	int (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
-+	int (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
-+	int (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
-+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
-+#endif
-+
-+};
-+
-+struct io_req {
-+	_list	list;
-+	u32	addr;
-+	volatile u32	val;
-+	u32	command;
-+	u32	status;
-+	u8	*pbuf;
-+	_sema	sema;
-+	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt);
-+	u8 *cnxt;
-+};
-+
-+struct	intf_hdl {
-+	_adapter *padapter;
-+	struct dvobj_priv *pintf_dev;/*	pointer to &(padapter->dvobjpriv); */
-+	struct _io_ops	io_ops;
-+};
-+
-+struct reg_protocol_rd {
-+
-+#ifdef CONFIG_LITTLE_ENDIAN
-+
-+	/* DW1 */
-+	u32		NumOfTrans:4;
-+	u32		Reserved1:4;
-+	u32		Reserved2:24;
-+	/* DW2 */
-+	u32		ByteCount:7;
-+	u32		WriteEnable:1;		/* 0:read, 1:write */
-+	u32		FixOrContinuous:1;	/* 0:continuous, 1: Fix */
-+	u32		BurstMode:1;
-+	u32		Byte1Access:1;
-+	u32		Byte2Access:1;
-+	u32		Byte4Access:1;
-+	u32		Reserved3:3;
-+	u32		Reserved4:16;
-+	/* DW3 */
-+	u32		BusAddress;
-+	/* DW4 */
-+	/* u32		Value; */
-+#else
-+
-+
-+	/* DW1 */
-+	u32 Reserved1:4;
-+	u32 NumOfTrans:4;
-+
-+	u32 Reserved2:24;
-+
-+	/* DW2 */
-+	u32 WriteEnable:1;
-+	u32 ByteCount:7;
-+
-+
-+	u32 Reserved3:3;
-+	u32 Byte4Access:1;
-+
-+	u32 Byte2Access:1;
-+	u32 Byte1Access:1;
-+	u32 BurstMode:1;
-+	u32 FixOrContinuous:1;
-+
-+	u32 Reserved4:16;
-+
-+	/* DW3 */
-+	u32		BusAddress;
-+
-+	/* DW4 */
-+	/* u32		Value; */
-+
-+#endif
-+
-+};
-+
-+
-+struct reg_protocol_wt {
-+
-+
-+#ifdef CONFIG_LITTLE_ENDIAN
-+
-+	/* DW1 */
-+	u32		NumOfTrans:4;
-+	u32		Reserved1:4;
-+	u32		Reserved2:24;
-+	/* DW2 */
-+	u32		ByteCount:7;
-+	u32		WriteEnable:1;		/* 0:read, 1:write */
-+	u32		FixOrContinuous:1;	/* 0:continuous, 1: Fix */
-+	u32		BurstMode:1;
-+	u32		Byte1Access:1;
-+	u32		Byte2Access:1;
-+	u32		Byte4Access:1;
-+	u32		Reserved3:3;
-+	u32		Reserved4:16;
-+	/* DW3 */
-+	u32		BusAddress;
-+	/* DW4 */
-+	u32		Value;
-+
-+#else
-+	/* DW1 */
-+	u32 Reserved1:4;
-+	u32 NumOfTrans:4;
-+
-+	u32 Reserved2:24;
-+
-+	/* DW2 */
-+	u32 WriteEnable:1;
-+	u32 ByteCount:7;
-+
-+	u32 Reserved3:3;
-+	u32 Byte4Access:1;
-+
-+	u32 Byte2Access:1;
-+	u32 Byte1Access:1;
-+	u32 BurstMode:1;
-+	u32 FixOrContinuous:1;
-+
-+	u32 Reserved4:16;
-+
-+	/* DW3 */
-+	u32		BusAddress;
-+
-+	/* DW4 */
-+	u32		Value;
-+
-+#endif
-+
-+};
-+#ifdef CONFIG_PCI_HCI
-+#define MAX_CONTINUAL_IO_ERR 4
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+#define MAX_CONTINUAL_IO_ERR 4
-+#endif
-+
-+#ifdef CONFIG_SDIO_HCI
-+#define SD_IO_TRY_CNT (8)
-+#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT
-+#endif
-+
-+#ifdef CONFIG_GSPI_HCI
-+#define SD_IO_TRY_CNT (8)
-+#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT
-+#endif
-+
-+
-+int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj);
-+void rtw_reset_continual_io_error(struct dvobj_priv *dvobj);
-+
-+/*
-+Below is the data structure used by _io_handler
-+
-+*/
-+
-+struct io_queue {
-+	_lock	lock;
-+	_list	free_ioreqs;
-+	_list		pending;		/* The io_req list that will be served in the single protocol read/write.	 */
-+	_list		processing;
-+	u8	*free_ioreqs_buf; /* 4-byte aligned */
-+	u8	*pallocated_free_ioreqs_buf;
-+	struct	intf_hdl	intf;
-+};
-+
-+struct io_priv {
-+
-+	_adapter *padapter;
-+
-+	struct intf_hdl intf;
-+
-+};
-+
-+extern uint ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);
-+extern void sync_ioreq_enqueue(struct io_req *preq, struct io_queue *ioqueue);
-+extern uint sync_ioreq_flush(_adapter *adapter, struct io_queue *ioqueue);
-+
-+
-+extern uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue);
-+extern struct io_req *alloc_ioreq(struct io_queue *pio_q);
-+
-+extern uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl);
-+extern void unregister_intf_hdl(struct intf_hdl *pintfhdl);
-+
-+extern void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
-+extern void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
-+
-+extern u8 _rtw_read8(_adapter *adapter, u32 addr);
-+extern u16 _rtw_read16(_adapter *adapter, u32 addr);
-+extern u32 _rtw_read32(_adapter *adapter, u32 addr);
-+extern void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
-+extern void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
-+extern void _rtw_read_port_cancel(_adapter *adapter);
-+
-+
-+extern int _rtw_write8(_adapter *adapter, u32 addr, u8 val);
-+extern int _rtw_write16(_adapter *adapter, u32 addr, u16 val);
-+extern int _rtw_write32(_adapter *adapter, u32 addr, u32 val);
-+extern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata);
-+
-+#ifdef CONFIG_SDIO_HCI
-+u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr);
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+u8 _rtw_sd_iread8(_adapter *adapter, u32 addr);
-+u16 _rtw_sd_iread16(_adapter *adapter, u32 addr);
-+u32 _rtw_sd_iread32(_adapter *adapter, u32 addr);
-+int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val);
-+int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val);
-+int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val);
-+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
-+#endif /* CONFIG_SDIO_HCI */
-+
-+extern int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val);
-+extern int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val);
-+extern int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val);
-+
-+extern void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
-+extern u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
-+u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms);
-+extern void _rtw_write_port_cancel(_adapter *adapter);
-+
-+#ifdef DBG_IO
-+u32 match_read_sniff(_adapter *adapter, u32 addr, u16 len, u32 val);
-+u32 match_write_sniff(_adapter *adapter, u32 addr, u16 len, u32 val);
-+bool match_rf_read_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask);
-+bool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask);
-+
-+void dbg_rtw_reg_read_monitor(_adapter *adapter, u32 addr, u32 len, u32 val, const char *caller, const int line);
-+void dbg_rtw_reg_write_monitor(_adapter *adapter, u32 addr, u32 len, u32 val, const char *caller, const int line);
-+
-+extern u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line);
-+extern u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line);
-+extern u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line);
-+
-+extern int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
-+extern int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
-+extern int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
-+extern int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line);
-+
-+#ifdef CONFIG_SDIO_HCI
-+u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line);
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line);
-+u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line);
-+u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line);
-+int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
-+int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
-+int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
-+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
-+#endif /* CONFIG_SDIO_HCI */
-+
-+#define rtw_read8(adapter, addr) dbg_rtw_read8((adapter), (addr), __FUNCTION__, __LINE__)
-+#define rtw_read16(adapter, addr) dbg_rtw_read16((adapter), (addr), __FUNCTION__, __LINE__)
-+#define rtw_read32(adapter, addr) dbg_rtw_read32((adapter), (addr), __FUNCTION__, __LINE__)
-+#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
-+#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
-+#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
-+
-+#define  rtw_write8(adapter, addr, val) dbg_rtw_write8((adapter), (addr), (val), __FUNCTION__, __LINE__)
-+#define  rtw_write16(adapter, addr, val) dbg_rtw_write16((adapter), (addr), (val), __FUNCTION__, __LINE__)
-+#define  rtw_write32(adapter, addr, val) dbg_rtw_write32((adapter), (addr), (val), __FUNCTION__, __LINE__)
-+#define  rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN((adapter), (addr), (length), (data), __FUNCTION__, __LINE__)
-+
-+#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
-+#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
-+#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))
-+
-+#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), addr, cnt, mem)
-+#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem)
-+#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
-+#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter)
-+
-+#ifdef CONFIG_SDIO_HCI
-+#define rtw_sd_f0_read8(adapter, addr) dbg_rtw_sd_f0_read8((adapter), (addr), __func__, __LINE__)
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+#define rtw_sd_iread8(adapter, addr) dbg_rtw_sd_iread8((adapter), (addr), __func__, __LINE__)
-+#define rtw_sd_iread16(adapter, addr) dbg_rtw_sd_iread16((adapter), (addr), __func__, __LINE__)
-+#define rtw_sd_iread32(adapter, addr) dbg_rtw_sd_iread32((adapter), (addr), __func__, __LINE__)
-+#define rtw_sd_iwrite8(adapter, addr, val) dbg_rtw_sd_iwrite8((adapter), (addr), (val), __func__, __LINE__)
-+#define rtw_sd_iwrite16(adapter, addr, val) dbg_rtw_sd_iwrite16((adapter), (addr), (val), __func__, __LINE__)
-+#define rtw_sd_iwrite32(adapter, addr, val) dbg_rtw_sd_iwrite32((adapter), (addr), (val), __func__, __LINE__)
-+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
-+#endif /* CONFIG_SDIO_HCI */
-+
-+#else /* DBG_IO */
-+#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr))
-+#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr))
-+#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr))
-+#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem))
-+#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem))
-+#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter))
-+
-+#define  rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val))
-+#define  rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val))
-+#define  rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val))
-+#define  rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data))
-+
-+#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val))
-+#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val))
-+#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val))
-+
-+#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem))
-+#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem))
-+#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms))
-+#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter))
-+
-+#ifdef CONFIG_SDIO_HCI
-+#define rtw_sd_f0_read8(adapter, addr) _rtw_sd_f0_read8((adapter), (addr))
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+#define rtw_sd_iread8(adapter, addr) _rtw_sd_iread8((adapter), (addr))
-+#define rtw_sd_iread16(adapter, addr) _rtw_sd_iread16((adapter), (addr))
-+#define rtw_sd_iread32(adapter, addr) _rtw_sd_iread32((adapter), (addr))
-+#define rtw_sd_iwrite8(adapter, addr, val) _rtw_sd_iwrite8((adapter), (addr), (val))
-+#define rtw_sd_iwrite16(adapter, addr, val) _rtw_sd_iwrite16((adapter), (addr), (val))
-+#define rtw_sd_iwrite32(adapter, addr, val) _rtw_sd_iwrite32((adapter), (addr), (val))
-+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
-+#endif /* CONFIG_SDIO_HCI */
-+
-+#endif /* DBG_IO */
-+
-+extern void rtw_write_scsi(_adapter *adapter, u32 cnt, u8 *pmem);
-+
-+/* ioreq */
-+extern void ioreq_read8(_adapter *adapter, u32 addr, u8 *pval);
-+extern void ioreq_read16(_adapter *adapter, u32 addr, u16 *pval);
-+extern void ioreq_read32(_adapter *adapter, u32 addr, u32 *pval);
-+extern void ioreq_write8(_adapter *adapter, u32 addr, u8 val);
-+extern void ioreq_write16(_adapter *adapter, u32 addr, u16 val);
-+extern void ioreq_write32(_adapter *adapter, u32 addr, u32 val);
-+
-+
-+extern uint async_read8(_adapter *adapter, u32 addr, u8 *pbuff,
-+	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
-+extern uint async_read16(_adapter *adapter, u32 addr,  u8 *pbuff,
-+	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
-+extern uint async_read32(_adapter *adapter, u32 addr,  u8 *pbuff,
-+	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
-+
-+extern void async_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
-+extern void async_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
-+
-+extern void async_write8(_adapter *adapter, u32 addr, u8 val,
-+	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
-+extern void async_write16(_adapter *adapter, u32 addr, u16 val,
-+	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
-+extern void async_write32(_adapter *adapter, u32 addr, u32 val,
-+	void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt);
-+
-+extern void async_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
-+extern void async_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
-+
-+
-+int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter, struct _io_ops *pops));
-+
-+
-+extern uint alloc_io_queue(_adapter *adapter);
-+extern void free_io_queue(_adapter *adapter);
-+extern void async_bus_io(struct io_queue *pio_q);
-+extern void bus_sync_io(struct io_queue *pio_q);
-+extern u32 _ioreq2rwmem(struct io_queue *pio_q);
-+
-+/*
-+#define RTL_R8(reg)		rtw_read8(padapter, reg)
-+#define RTL_R16(reg)            rtw_read16(padapter, reg)
-+#define RTL_R32(reg)            rtw_read32(padapter, reg)
-+#define RTL_W8(reg, val8)       rtw_write8(padapter, reg, val8)
-+#define RTL_W16(reg, val16)     rtw_write16(padapter, reg, val16)
-+#define RTL_W32(reg, val32)     rtw_write32(padapter, reg, val32)
-+*/
-+
-+/*
-+#define RTL_W8_ASYNC(reg, val8) rtw_write32_async(padapter, reg, val8)
-+#define RTL_W16_ASYNC(reg, val16) rtw_write32_async(padapter, reg, val16)
-+#define RTL_W32_ASYNC(reg, val32) rtw_write32_async(padapter, reg, val32)
-+
-+#define RTL_WRITE_BB(reg, val32)	phy_SetUsbBBReg(padapter, reg, val32)
-+#define RTL_READ_BB(reg)	phy_QueryUsbBBReg(padapter, reg)
-+*/
-+
-+#define PlatformEFIOWrite1Byte(_a, _b, _c)		\
-+	rtw_write8(_a, _b, _c)
-+#define PlatformEFIOWrite2Byte(_a, _b, _c)		\
-+	rtw_write16(_a, _b, _c)
-+#define PlatformEFIOWrite4Byte(_a, _b, _c)		\
-+	rtw_write32(_a, _b, _c)
-+
-+#define PlatformEFIORead1Byte(_a, _b)		\
-+	rtw_read8(_a, _b)
-+#define PlatformEFIORead2Byte(_a, _b)		\
-+	rtw_read16(_a, _b)
-+#define PlatformEFIORead4Byte(_a, _b)		\
-+	rtw_read32(_a, _b)
-+
-+#endif /* _RTL8711_IO_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_ioctl.h b/drivers/staging/rtl8723cs/include/rtw_ioctl.h
-new file mode 100644
-index 000000000000..1143d97104d8
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_ioctl.h
-@@ -0,0 +1,47 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTW_IOCTL_H_
-+#define _RTW_IOCTL_H_
-+
-+enum oid_type {
-+	QUERY_OID,
-+	SET_OID
-+};
-+
-+struct oid_par_priv {
-+	void		*adapter_context;
-+	NDIS_OID	oid;
-+	void		*information_buf;
-+	u32		information_buf_len;
-+	u32		*bytes_rw;
-+	u32		*bytes_needed;
-+	enum oid_type	type_of_oid;
-+	u32		dbg;
-+};
-+
-+#if defined(PLATFORM_LINUX) && defined(CONFIG_WIRELESS_EXT)
-+extern struct iw_handler_def  rtw_handlers_def;
-+#endif
-+
-+extern void rtw_request_wps_pbc_event(_adapter *padapter);
-+
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+extern int rtw_vendor_ie_get_raw_data(struct net_device *, u32, char *, u32);
-+extern int rtw_vendor_ie_get_data(struct net_device*, int , char*);
-+extern int rtw_vendor_ie_get(struct net_device *, struct iw_request_info *, union iwreq_data *, char *);
-+extern int rtw_vendor_ie_set(struct net_device*, struct iw_request_info*, union iwreq_data*, char*);
-+#endif
-+
-+#endif /*  #ifndef __INC_CEINFO_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_ioctl_query.h b/drivers/staging/rtl8723cs/include/rtw_ioctl_query.h
-new file mode 100644
-index 000000000000..7badcddfbbd4
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_ioctl_query.h
-@@ -0,0 +1,19 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTW_IOCTL_QUERY_H_
-+#define _RTW_IOCTL_QUERY_H_
-+
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtw_ioctl_set.h b/drivers/staging/rtl8723cs/include/rtw_ioctl_set.h
-new file mode 100644
-index 000000000000..82b4c182d882
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_ioctl_set.h
-@@ -0,0 +1,40 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_IOCTL_SET_H_
-+#define __RTW_IOCTL_SET_H_
-+
-+u8 rtw_set_802_11_authentication_mode(_adapter *pdapter, NDIS_802_11_AUTHENTICATION_MODE authmode);
-+u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid);
-+u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep);
-+u8 rtw_set_802_11_disassociate(_adapter *padapter);
-+u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm);
-+#ifdef CONFIG_RTW_ACS
-+u8 rtw_set_acs_sitesurvey(_adapter *adapter);
-+#endif
-+u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags);
-+u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid);
-+u8 rtw_set_802_11_connect(_adapter *padapter,
-+			  u8 *bssid, NDIS_802_11_SSID *ssid, u16 ch);
-+
-+u8 rtw_validate_bssid(u8 *bssid);
-+u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid);
-+
-+u16 rtw_get_cur_max_rate(_adapter *adapter);
-+int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode);
-+int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan);
-+int rtw_set_country(_adapter *adapter, const char *country_code);
-+int rtw_set_band(_adapter *adapter, u8 band);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtw_iol.h b/drivers/staging/rtl8723cs/include/rtw_iol.h
-new file mode 100644
-index 000000000000..fa35a59c75c7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_iol.h
-@@ -0,0 +1,131 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_IOL_H_
-+#define __RTW_IOL_H_
-+
-+
-+struct xmit_frame	*rtw_IOL_accquire_xmit_frame(ADAPTER *adapter);
-+int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len);
-+int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary);
-+int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
-+bool rtw_IOL_applied(ADAPTER *adapter);
-+int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us);
-+int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms);
-+int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame);
-+
-+
-+#ifdef CONFIG_IOL_NEW_GENERATION
-+#define IOREG_CMD_END_LEN	4
-+
-+struct ioreg_cfg {
-+	u8	length;
-+	u8	cmd_id;
-+	u16	address;
-+	u32	data;
-+	u32  mask;
-+};
-+enum ioreg_cmd {
-+	IOREG_CMD_LLT			= 0x01,
-+	IOREG_CMD_REFUSE		= 0x02,
-+	IOREG_CMD_EFUSE_PATH = 0x03,
-+	IOREG_CMD_WB_REG		= 0x04,
-+	IOREG_CMD_WW_REG	= 0x05,
-+	IOREG_CMD_WD_REG	= 0x06,
-+	IOREG_CMD_W_RF		= 0x07,
-+	IOREG_CMD_DELAY_US	= 0x10,
-+	IOREG_CMD_DELAY_MS	= 0x11,
-+	IOREG_CMD_END		= 0xFF,
-+};
-+void read_efuse_from_txpktbuf(ADAPTER *adapter, int bcnhead, u8 *content, u16 *size);
-+
-+int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask);
-+int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask);
-+int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask);
-+int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask);
-+#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), (mask))
-+#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), (mask))
-+#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), (mask))
-+#define rtw_IOL_append_WRF_cmd(xmit_frame, rf_path, addr, value, mask) _rtw_IOL_append_WRF_cmd((xmit_frame), (rf_path), (addr), (value), (mask))
-+
-+u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame);
-+void  rtw_IOL_cmd_buf_dump(ADAPTER *Adapter, int buf_len, u8 *pbuf);
-+
-+#ifdef CONFIG_IOL_IOREG_CFG_DBG
-+struct cmd_cmp {
-+	u16 addr;
-+	u32 value;
-+};
-+#endif
-+
-+#else /* CONFIG_IOL_NEW_GENERATION */
-+
-+typedef struct _io_offload_cmd {
-+	u8 rsvd0;
-+	u8 cmd;
-+	u16 address;
-+	u32 value;
-+} IO_OFFLOAD_CMD, IOL_CMD;
-+
-+#define IOL_CMD_LLT			0x00
-+/* #define IOL_CMD_R_EFUSE	0x01 */
-+#define IOL_CMD_WB_REG		0x02
-+#define IOL_CMD_WW_REG	0x03
-+#define IOL_CMD_WD_REG		0x04
-+/* #define IOL_CMD_W_RF		0x05 */
-+#define IOL_CMD_DELAY_US	0x80
-+#define IOL_CMD_DELAY_MS	0x81
-+/* #define IOL_CMD_DELAY_S	0x82 */
-+#define IOL_CMD_END			0x83
-+
-+/*****************************************************
-+CMD					Address			Value
-+(B1)					(B2/B3:H/L addr)	(B4:B7 : MSB:LSB)
-+******************************************************
-+IOL_CMD_LLT			-				B7: PGBNDY
-+IOL_CMD_R_EFUSE	-				-
-+IOL_CMD_WB_REG		0x0~0xFFFF		B7
-+IOL_CMD_WW_REG	0x0~0xFFFF		B6~B7
-+IOL_CMD_WD_REG	0x0~0xFFFF		B4~B7
-+IOL_CMD_W_RF		RF Reg			B5~B7
-+IOL_CMD_DELAY_US	-				B6~B7
-+IOL_CMD_DELAY_MS	-				B6~B7
-+IOL_CMD_DELAY_S	-				B6~B7
-+IOL_CMD_END		-				-
-+******************************************************/
-+int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value);
-+int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value);
-+int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value);
-+
-+
-+int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms);
-+int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms);
-+
-+#ifdef DBG_IO
-+int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line);
-+int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line);
-+int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line);
-+#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
-+#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
-+#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__)
-+#else
-+#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value))
-+#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value))
-+#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value))
-+#endif /* DBG_IO */
-+#endif /* CONFIG_IOL_NEW_GENERATION */
-+
-+
-+
-+#endif /* __RTW_IOL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_mbo.h b/drivers/staging/rtl8723cs/include/rtw_mbo.h
-new file mode 100644
-index 000000000000..9524cb6c6e11
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_mbo.h
-@@ -0,0 +1,114 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __RTW_MBO_H_
-+#define __RTW_MBO_H_
-+
-+#define rtw_mbo_wifi_logo_test(a)	((a->registrypriv.wifi_spec) == 1)
-+
-+#define rtw_mbo_set_ext_cap_internw(_pEleStart, _val) \
-+	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+3, 7, 1, _val)
-+
-+#define rtw_mbo_wnm_notification_req(c, a) \
-+	(((c) == RTW_WLAN_CATEGORY_WNM) &&	\
-+	(((a) == RTW_WLAN_ACTION_WNM_NOTIF_REQ)))
-+
-+/* IEEE Std 802.11-2016 Table 9-46 - Status codes */
-+#define RTW_ASSOC_DENIED_NO_MORE_STAS	17
-+#define RTW_ASSOC_REFUSED_TEMPORARILY	30
-+
-+/* MBO-OCE Information Element */
-+#define RTW_MBO_EID		WLAN_EID_VENDOR_SPECIFIC
-+#define RTW_MBO_OUI		0x506F9A
-+#define RTW_MBO_OUI_TYPE	0x16
-+
-+/* Non-preferred Channel Report */
-+#define RTW_MBO_ATTR_NPREF_CH_RPT_ID	0x2
-+/* Cellular Data Capabilities */
-+#define RTW_MBO_ATTR_CELL_DATA_CAP_ID	0x3
-+/* Association Disallowed */
-+#define RTW_MBO_ATTR_ASSOC_DISABLED_ID	0x4
-+/* Transition Reason Code */
-+#define RTW_MBO_ATTR_TRANS_RES_ID		0x6
-+/* Transition Rejection Reason Code */
-+#define RTW_MBO_ATTR_TRANS_REJ_ID		0x7
-+/* Association Retry Delay */
-+#define RTW_MBO_ATTR_TASSOC_RETRY_ID	0x8
-+
-+#define RTW_MBO_MAX_CH_LIST_NUM MAX_CHANNEL_NUM
-+
-+#define RTW_MBO_MAX_CH_RPT_NUM 32
-+
-+struct npref_ch {
-+	u8 op_class;
-+	u8 chs[RTW_MBO_MAX_CH_LIST_NUM];
-+	size_t nm_of_ch;
-+	u8 preference;
-+	u8 reason;
-+};
-+
-+struct npref_ch_rtp {
-+	struct npref_ch ch_rpt[RTW_MBO_MAX_CH_RPT_NUM];
-+	size_t nm_of_rpt;
-+};
-+
-+void rtw_mbo_build_cell_data_cap_attr(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib);
-+
-+void rtw_mbo_update_ie_data(
-+	_adapter *padapter, u8 *pie, u32 ie_len);
-+	
-+void rtw_mbo_build_supp_op_class_elem(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib);
-+
-+void rtw_mbo_build_npref_ch_rpt_attr(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib);
-+
-+void rtw_mbo_build_trans_reject_reason_attr(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib, u8 *pres);
-+
-+u8 rtw_mbo_disallowed_network(struct wlan_network *pnetwork);
-+
-+void rtw_mbo_build_exented_cap(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib);
-+
-+ssize_t rtw_mbo_proc_non_pref_chans_set(
-+	struct file *pfile, const char __user *buffer, 
-+	size_t count, loff_t *pos, void *pdata);
-+
-+int rtw_mbo_proc_non_pref_chans_get(
-+	struct seq_file *m, void *v);
-+
-+ssize_t rtw_mbo_proc_cell_data_set(
-+	struct file *pfile, const char __user *buffer,
-+	size_t count, loff_t *pos, void *pdata);
-+
-+int rtw_mbo_proc_cell_data_get(
-+	struct seq_file *m, void *v);
-+
-+void rtw_mbo_wnm_notification_parsing(
-+	_adapter *padapter, const u8 *pdata, size_t data_len);
-+
-+void rtw_mbo_build_wnm_notification(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib);
-+
-+void rtw_mbo_build_probe_req_ies(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib);
-+
-+void rtw_mbo_build_assoc_req_ies(
-+	_adapter *padapter, u8 **pframe, struct pkt_attrib *pattrib);
-+
-+#endif /* __RTW_MBO_H_ */
-+
-diff --git a/drivers/staging/rtl8723cs/include/rtw_mcc.h b/drivers/staging/rtl8723cs/include/rtw_mcc.h
-new file mode 100644
-index 000000000000..5d2198b03063
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_mcc.h
-@@ -0,0 +1,315 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifdef CONFIG_MCC_MODE
-+
-+#ifndef _RTW_MCC_H_
-+#define _RTW_MCC_H_
-+
-+#include <drv_types.h> /* PADAPTER */
-+
-+#define MCC_STATUS_PROCESS_MCC_START_SETTING BIT0
-+#define MCC_STATUS_PROCESS_MCC_STOP_SETTING BIT1
-+#define MCC_STATUS_NEED_MCC BIT2
-+#define MCC_STATUS_DOING_MCC BIT3
-+
-+
-+#define MCC_SWCH_FW_EARLY_TIME 10 /* ms */
-+#define MCC_EXPIRE_TIME 50 /* ms */
-+#define MCC_TOLERANCE_TIME 2 /* 2*2 = 4s */
-+#define MCC_UPDATE_PARAMETER_THRESHOLD 5 /* ms */
-+
-+#define MCC_ROLE_STA_GC_MGMT_QUEUE_MACID 0
-+#define MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID 1
-+
-+/* Lower for stop, Higher for start */
-+#define MCC_SETCMD_STATUS_STOP_DISCONNECT 0x0
-+#define MCC_SETCMD_STATUS_STOP_SCAN_START 0x1
-+#define MCC_SETCMD_STATUS_START_CONNECT 0x80
-+#define MCC_SETCMD_STATUS_START_SCAN_DONE 0x81
-+
-+/*
-+* depenad platform or customer requirement(TP unit:Mbps),
-+* must be provided by PM or sales or product document
-+* too large value means not to limit tx bytes (current for ap mode)
-+* NOTE: following values ref from test results
-+*/
-+#define MCC_AP_BW20_TARGET_TX_TP (300)
-+#define MCC_AP_BW40_TARGET_TX_TP (300)
-+#define MCC_AP_BW80_TARGET_TX_TP (300)
-+#define MCC_STA_BW20_TARGET_TX_TP (35)
-+#define MCC_STA_BW40_TARGET_TX_TP (70)
-+#define MCC_STA_BW80_TARGET_TX_TP (140)
-+#define MCC_SINGLE_TX_CRITERIA 5 /* Mbps */
-+
-+#define MAX_MCC_NUM 2
-+#ifdef CONFIG_RTL8822C
-+#define DBG_MCC_REG_NUM 3
-+#else
-+#define DBG_MCC_REG_NUM 4
-+#endif
-+#define DBG_MCC_RF_REG_NUM 1
-+
-+#define MCC_STOP(adapter) (adapter->mcc_adapterpriv.mcc_tx_stop)
-+#define MCC_EN(adapter) (adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc)
-+#define adapter_to_mccobjpriv(adapter) (&(adapter_to_dvobj(adapter)->mcc_objpriv))
-+#define SET_MCC_EN_FLAG(adapter, flag)\
-+	do { \
-+		adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc = (flag); \
-+	} while (0)
-+#define SET_MCC_DURATION(adapter, val)\
-+	do { \
-+		adapter_to_dvobj(adapter)->mcc_objpriv.duration = (val); \
-+	} while (0)
-+#define SET_MCC_RUNTIME_DURATION(adapter, flag)\
-+	do { \
-+		adapter_to_dvobj(adapter)->mcc_objpriv.enable_runtime_duration = (flag); \
-+	} while (0)
-+
-+#define SET_MCC_PHYDM_OFFLOAD(adapter, flag)\
-+	do { \
-+		adapter_to_dvobj(adapter)->mcc_objpriv.mcc_phydm_offload = (flag); \
-+	} while (0)
-+
-+#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+enum mcc_cfg_phydm_ops {
-+	MCC_CFG_PHYDM_OFFLOAD = 0,
-+	MCC_CFG_PHYDM_RF_CH,
-+	MCC_CFG_PHYDM_ADD_CLIENT,
-+	MCC_CFG_PHYDM_REMOVE_CLIENT,
-+	MCC_CFG_PHYDM_START,
-+	MCC_CFG_PHYDM_STOP,
-+	MCC_CFG_PHYDM_DUMP,
-+	MCC_CFG_PHYDM_MAX,
-+};
-+#endif
-+
-+enum rtw_mcc_cmd_id {
-+	MCC_CMD_WK_CID = 0,
-+	MCC_SET_DURATION_WK_CID,
-+	MCC_GET_DBG_REG_WK_CID,
-+	#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+	MCC_SET_PHYDM_OFFLOAD_WK_CID,
-+	#endif
-+};
-+
-+/* Represent Channel Tx Null setting */
-+enum mcc_channel_tx_null {
-+	MCC_ENABLE_TX_NULL = 0,
-+	MCC_DISABLE_TX_NULL = 1,
-+};
-+
-+/* Represent C2H Report setting */
-+enum mcc_c2h_report {
-+	MCC_C2H_REPORT_DISABLE = 0,
-+	MCC_C2H_REPORT_FAIL_STATUS = 1,
-+	MCC_C2H_REPORT_ALL_STATUS = 2,
-+};
-+
-+/* Represent Channel Scan */
-+enum mcc_channel_scan {
-+	MCC_CHIDX = 0,
-+	MCC_SCANCH_RSVD_LOC = 1,
-+};
-+
-+/* Represent FW status report of channel switch */
-+enum mcc_status_rpt {
-+	MCC_RPT_SUCCESS = 0,
-+	MCC_RPT_TXNULL_FAIL = 1,
-+	MCC_RPT_STOPMCC = 2,
-+	MCC_RPT_READY = 3,
-+	MCC_RPT_SWICH_CHANNEL_NOTIFY = 7,
-+	MCC_RPT_UPDATE_NOA_START_TIME = 8,
-+	MCC_RPT_TSF = 9,
-+	MCC_RPT_MAX,
-+};
-+
-+enum mcc_role {
-+	MCC_ROLE_STA = 0,
-+	MCC_ROLE_AP = 1,
-+	MCC_ROLE_GC = 2,
-+	MCC_ROLE_GO = 3,
-+	MCC_ROLE_MAX,
-+};
-+
-+struct mcc_iqk_backup {
-+	u16 TX_X;
-+	u16 TX_Y;
-+	u16 RX_X;
-+	u16 RX_Y;
-+};
-+
-+enum mcc_duration_setting {
-+	MCC_DURATION_MAPPING = 0,
-+	MCC_DURATION_DIRECET = 1,
-+};
-+
-+enum mcc_sched_mode {
-+	MCC_FAIR_SCHEDULE = 0,
-+	MCC_FAVOR_STA = 1,
-+	MCC_FAVOR_P2P = 2,
-+};
-+
-+/*  mcc data for adapter */
-+struct mcc_adapter_priv {
-+	u8 order;		/* FW document, softap/AP must be 0 */
-+	enum mcc_role role;			/* MCC role(AP,STA,GO,GC) */
-+	u8 mcc_duration; /* channel stay period, UNIT:1TU */
-+
-+	/* flow control */
-+	u8 mcc_tx_stop;				/* check if tp stop or not */
-+	u8 mcc_tp_limit;				/* check if tp limit or not */
-+	u32 mcc_target_tx_bytes_to_port;		/* customer require  */
-+	u32 mcc_tx_bytes_to_port;	/* already tx to tx fifo (write port) */
-+
-+	/* data from kernel to check if enqueue data or netif stop queue */
-+	u32 mcc_tp;
-+	u64 mcc_tx_bytes_from_kernel;
-+	u64 mcc_last_tx_bytes_from_kernel;
-+
-+	/* Backup IQK value for MCC */
-+	struct mcc_iqk_backup mcc_iqk_arr[MAX_RF_PATH];
-+
-+	/* mgmt queue macid to avoid RA issue */
-+	u8 mgmt_queue_macid;
-+
-+	/* set macid bitmap to let fw know which macid should be tx pause */
-+	/* all interface share total 16 macid */
-+	u16 mcc_macid_bitmap;
-+
-+	/* use for NoA start time (unit: mircoseconds) */
-+	u32 noa_start_time;
-+
-+	u8 p2p_go_noa_ie[MAX_P2P_IE_LEN];
-+	u32 p2p_go_noa_ie_len;
-+	u64 tsf;
-+#ifdef CONFIG_TDLS
-+	u8 backup_tdls_en;
-+#endif /* CONFIG_TDLS */
-+
-+	u8 null_early;
-+	u8 null_rty_num;
-+};
-+
-+struct mcc_obj_priv {
-+	u8 en_mcc; /* enable MCC or not */
-+	u8 duration; /* store duration(%) from registry, for primary adapter */
-+	u8 interval;
-+	u8 start_time;
-+	u8 mcc_c2h_status;
-+	u8 cur_mcc_success_cnt; /* used for check mcc switch channel success */
-+	u8 prev_mcc_success_cnt; /* used for check mcc switch channel success */
-+	u8 mcc_tolerance_time; /* used for detect mcc switch channel success */
-+	u8 mcc_loc_rsvd_paga[MAX_MCC_NUM];  /* mcc rsvd page */
-+	u8 mcc_status; /* mcc status stop or start .... */
-+	u8 policy_index;
-+	u8 mcc_stop_threshold;
-+	u8 current_order;
-+	u8 last_tsfdiff;
-+	systime mcc_launch_time; /* mcc launch time, used for starting detect mcc switch channel success */
-+	_mutex mcc_mutex;
-+	_lock mcc_lock;
-+	PADAPTER iface[MAX_MCC_NUM]; /* by order, use for mcc parameter cmd */
-+	struct submit_ctx mcc_sctx;
-+	struct submit_ctx mcc_tsf_req_sctx;
-+	_mutex mcc_tsf_req_mutex;
-+	u8 mcc_tsf_req_sctx_order; /* record current order for mcc_tsf_req_sctx */
-+#ifdef CONFIG_MCC_MODE_V2
-+	u8 mcc_iqk_value_rsvd_page[3];
-+#endif /* CONFIG_MCC_MODE_V2 */
-+	u8 mcc_pwr_idx_rsvd_page[MAX_MCC_NUM];
-+	u8 enable_runtime_duration;
-+	/* for LG */
-+	u8 mchan_sched_mode;
-+
-+	_mutex mcc_dbg_reg_mutex;
-+	u32 dbg_reg[DBG_MCC_REG_NUM];
-+	u32 dbg_reg_val[DBG_MCC_REG_NUM];
-+	u32 dbg_rf_reg[DBG_MCC_RF_REG_NUM];
-+	u32 dbg_rf_reg_val[DBG_MCC_RF_REG_NUM][MAX_RF_PATH];
-+	u8 mcc_phydm_offload;
-+};
-+
-+/* backup IQK val */
-+void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter);
-+
-+/* check mcc status */
-+u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status);
-+
-+/* set mcc status */
-+void rtw_hal_set_mcc_status(PADAPTER padapter, u8 mcc_status);
-+
-+/* clear mcc status */
-+void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status);
-+
-+/* dl mcc rsvd page */
-+u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index
-+	, u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num);
-+
-+/* handle C2H */
-+void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf);
-+
-+/* switch channel successfully or not */
-+void rtw_hal_mcc_sw_status_check(PADAPTER padapter);
-+
-+/* change some scan flags under site survey */
-+u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset);
-+
-+/* record data kernel TX to driver to check MCC concurrent TX  */
-+void rtw_hal_mcc_calc_tx_bytes_from_kernel(PADAPTER padapter, u32 len);
-+
-+/* record data to port to let driver do flow ctrl  */
-+void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len);
-+
-+/* check stop write port or not  */
-+u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter);
-+
-+u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter);
-+
-+u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter);
-+
-+u8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_grouped);
-+
-+u8 rtw_hal_set_mcc_setting_disconnect(PADAPTER padapter);
-+
-+u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter);
-+
-+u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset, u8 chbw_allow);
-+
-+void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj);
-+
-+void update_mcc_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
-+
-+u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg);
-+
-+void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode);
-+
-+u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len);
-+
-+void rtw_hal_dump_mcc_policy_table(void *sel);
-+
-+void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add);
-+
-+void rtw_hal_mcc_process_noa(PADAPTER padapter);
-+
-+void rtw_hal_mcc_parameter_init(PADAPTER padapter);
-+
-+u8 rtw_mcc_cmd_hdl(PADAPTER adapter, u8 type, const u8 *val);
-+
-+u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val);
-+#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+u8 rtw_set_mcc_phydm_offload_enable_cmd(PADAPTER adapter, u8 enable, u8 enqueue);
-+#endif /* CONFIG_MCC_PHYDM_OFFLOAD */
-+#endif /* _RTW_MCC_H_ */
-+#endif /* CONFIG_MCC_MODE */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_mem.h b/drivers/staging/rtl8723cs/include/rtw_mem.h
-new file mode 100644
-index 000000000000..9e33ed519ed6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_mem.h
-@@ -0,0 +1,29 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_MEM_H__
-+#define __RTW_MEM_H__
-+
-+#include <drv_conf.h>
-+#include <basic_types.h>
-+#include <osdep_service.h>
-+
-+u16 rtw_rtkm_get_buff_size(void);
-+u8 rtw_rtkm_get_nr_recv_skb(void);
-+struct u8 *rtw_alloc_revcbuf_premem(void);
-+struct sk_buff *rtw_alloc_skb_premem(u16 in_size);
-+int rtw_free_skb_premem(struct sk_buff *pskb);
-+
-+
-+#endif /* __RTW_MEM_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_mi.h b/drivers/staging/rtl8723cs/include/rtw_mi.h
-new file mode 100644
-index 000000000000..0eb8b53b8882
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_mi.h
-@@ -0,0 +1,305 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_MI_H_
-+#define __RTW_MI_H_
-+
-+void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw);
-+u8 rtw_mi_stayin_union_ch_chk(_adapter *adapter);
-+u8 rtw_mi_stayin_union_band_chk(_adapter *adapter);
-+
-+int rtw_mi_get_ch_setting_union_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, u8 *ch, u8 *bw, u8 *offset);
-+int rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset);
-+int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset);
-+
-+struct mi_state {
-+	u8 sta_num;			/* WIFI_STATION_STATE */
-+	u8 ld_sta_num;		/* WIFI_STATION_STATE && WIFI_ASOC_STATE */
-+	u8 lg_sta_num;		/* WIFI_STATION_STATE && WIFI_UNDER_LINKING */
-+#ifdef CONFIG_TDLS
-+	u8 ld_tdls_num;		/* adapter.tdlsinfo.link_established */
-+#endif
-+#ifdef CONFIG_AP_MODE
-+	u8 ap_num;			/* WIFI_AP_STATE && WIFI_ASOC_STATE */
-+	u8 starting_ap_num;	/*WIFI_FW_AP_STATE*/
-+	u8 ld_ap_num;		/* WIFI_AP_STATE && WIFI_ASOC_STATE && asoc_sta_count > 2 */
-+#endif
-+	u8 adhoc_num;		/* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && WIFI_ASOC_STATE */
-+	u8 ld_adhoc_num;	/* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && WIFI_ASOC_STATE && asoc_sta_count > 2 */
-+#ifdef CONFIG_RTW_MESH
-+	u8 mesh_num;		/* WIFI_MESH_STATE &&  WIFI_ASOC_STATE */
-+	u8 ld_mesh_num;		/* WIFI_MESH_STATE &&  WIFI_ASOC_STATE && asoc_sta_count > 2 */
-+#endif
-+	u8 scan_num;		/* WIFI_UNDER_SURVEY */
-+	u8 scan_enter_num;	/* WIFI_UNDER_SURVEY && !SCAN_DISABLE && !SCAN_BACK_OP */
-+	u8 uwps_num;		/* WIFI_UNDER_WPS */
-+#ifdef CONFIG_IOCTL_CFG80211
-+	u8 roch_num;
-+	u8 mgmt_tx_num;
-+#endif
-+#ifdef CONFIG_P2P
-+	u8 p2p_device_num;
-+	u8 p2p_gc;
-+	u8 p2p_go;
-+#endif
-+};
-+
-+#define MSTATE_STA_NUM(_mstate)			((_mstate)->sta_num)
-+#define MSTATE_STA_LD_NUM(_mstate)		((_mstate)->ld_sta_num)
-+#define MSTATE_STA_LG_NUM(_mstate)		((_mstate)->lg_sta_num)
-+
-+#ifdef CONFIG_TDLS
-+#define MSTATE_TDLS_LD_NUM(_mstate)		((_mstate)->ld_tdls_num)
-+#else
-+#define MSTATE_TDLS_LD_NUM(_mstate)		0
-+#endif
-+
-+#ifdef CONFIG_AP_MODE
-+#define MSTATE_AP_NUM(_mstate)			((_mstate)->ap_num)
-+#define MSTATE_AP_STARTING_NUM(_mstate)	((_mstate)->starting_ap_num)
-+#define MSTATE_AP_LD_NUM(_mstate)		((_mstate)->ld_ap_num)
-+#else
-+#define MSTATE_AP_NUM(_mstate)			0
-+#define MSTATE_AP_STARTING_NUM(_mstate) 0
-+#define MSTATE_AP_LD_NUM(_mstate)		0
-+#endif
-+
-+#define MSTATE_ADHOC_NUM(_mstate)		((_mstate)->adhoc_num)
-+#define MSTATE_ADHOC_LD_NUM(_mstate)	((_mstate)->ld_adhoc_num)
-+
-+#ifdef CONFIG_RTW_MESH
-+#define MSTATE_MESH_NUM(_mstate)		((_mstate)->mesh_num)
-+#define MSTATE_MESH_LD_NUM(_mstate)		((_mstate)->ld_mesh_num)
-+#else
-+#define MSTATE_MESH_NUM(_mstate)		0
-+#define MSTATE_MESH_LD_NUM(_mstate)		0
-+#endif
-+
-+#define MSTATE_SCAN_NUM(_mstate)		((_mstate)->scan_num)
-+#define MSTATE_SCAN_ENTER_NUM(_mstate)	((_mstate)->scan_enter_num)
-+#define MSTATE_WPS_NUM(_mstate)			((_mstate)->uwps_num)
-+
-+#if defined(CONFIG_IOCTL_CFG80211)
-+#define MSTATE_ROCH_NUM(_mstate)		((_mstate)->roch_num)
-+#else
-+#define MSTATE_ROCH_NUM(_mstate)		0
-+#endif
-+
-+#ifdef CONFIG_P2P
-+#define MSTATE_P2P_DV_NUM(_mstate)		((_mstate)->p2p_device_num)
-+#define MSTATE_P2P_GC_NUM(_mstate)		((_mstate)->p2p_gc)
-+#define MSTATE_P2P_GO_NUM(_mstate)		((_mstate)->p2p_go)
-+#else
-+#define MSTATE_P2P_DV_NUM(_mstate)		0
-+#define MSTATE_P2P_GC_NUM(_mstate)		0
-+#define MSTATE_P2P_GO_NUM(_mstate)		0
-+#endif
-+
-+#if defined(CONFIG_IOCTL_CFG80211)
-+#define MSTATE_MGMT_TX_NUM(_mstate)		((_mstate)->mgmt_tx_num)
-+#else
-+#define MSTATE_MGMT_TX_NUM(_mstate)		0
-+#endif
-+
-+#define rtw_mi_get_union_chan(adapter)		((adapter_to_dvobj(adapter)->union_ch) ? (adapter_to_dvobj(adapter)->union_ch) : (adapter_to_dvobj(adapter)->union_ch_bak))
-+#define rtw_mi_get_union_bw(adapter)		((adapter_to_dvobj(adapter)->union_ch) ? (adapter_to_dvobj(adapter)->union_bw) : (adapter_to_dvobj(adapter)->union_bw_bak))
-+#define rtw_mi_get_union_offset(adapter)	((adapter_to_dvobj(adapter)->union_ch) ? (adapter_to_dvobj(adapter)->union_offset) : (adapter_to_dvobj(adapter)->union_offset_bak))
-+
-+#define rtw_mi_get_assoced_sta_num(adapter)	DEV_STA_LD_NUM(adapter_to_dvobj(adapter))
-+#define rtw_mi_get_ap_num(adapter)			DEV_AP_NUM(adapter_to_dvobj(adapter))
-+#define rtw_mi_get_mesh_num(adapter)		DEV_MESH_NUM(adapter_to_dvobj(adapter))
-+u8 rtw_mi_get_assoc_if_num(_adapter *adapter);
-+
-+/* For now, not return union_ch/bw/offset */
-+void rtw_mi_status_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, struct mi_state *mstate);
-+void rtw_mi_status(_adapter *adapter, struct mi_state *mstate);
-+void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate);
-+void rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate);
-+
-+/* For now, not handle union_ch/bw/offset */
-+void rtw_mi_status_merge(struct mi_state *d, struct mi_state *a);
-+
-+void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state);
-+
-+u8 rtw_mi_netif_stop_queue(_adapter *padapter);
-+u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter);
-+
-+u8 rtw_mi_netif_wake_queue(_adapter *padapter);
-+u8 rtw_mi_buddy_netif_wake_queue(_adapter *padapter);
-+
-+u8 rtw_mi_netif_carrier_on(_adapter *padapter);
-+u8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter);
-+u8 rtw_mi_netif_carrier_off(_adapter *padapter);
-+u8 rtw_mi_buddy_netif_carrier_off(_adapter *padapter);
-+
-+u8 rtw_mi_netif_caroff_qstop(_adapter *padapter);
-+u8 rtw_mi_buddy_netif_caroff_qstop(_adapter *padapter);
-+u8 rtw_mi_netif_caron_qstart(_adapter *padapter);
-+u8 rtw_mi_buddy_netif_caron_qstart(_adapter *padapter);
-+
-+void rtw_mi_scan_abort(_adapter *adapter, bool bwait);
-+void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait);
-+u32 rtw_mi_start_drv_threads(_adapter *adapter);
-+u32 rtw_mi_buddy_start_drv_threads(_adapter *adapter);
-+void rtw_mi_stop_drv_threads(_adapter *adapter);
-+void rtw_mi_buddy_stop_drv_threads(_adapter *adapter);
-+void rtw_mi_cancel_all_timer(_adapter *adapter);
-+void rtw_mi_buddy_cancel_all_timer(_adapter *adapter);
-+void rtw_mi_reset_drv_sw(_adapter *adapter);
-+void rtw_mi_buddy_reset_drv_sw(_adapter *adapter);
-+
-+extern void rtw_intf_start(_adapter *adapter);
-+extern void rtw_intf_stop(_adapter *adapter);
-+void rtw_mi_intf_start(_adapter *adapter);
-+void rtw_mi_buddy_intf_start(_adapter *adapter);
-+void rtw_mi_intf_stop(_adapter *adapter);
-+void rtw_mi_buddy_intf_stop(_adapter *adapter);
-+
-+#ifdef CONFIG_NEW_NETDEV_HDL
-+u8 rtw_mi_hal_iface_init(_adapter *padapter);
-+#endif
-+void rtw_mi_suspend_free_assoc_resource(_adapter *adapter);
-+void rtw_mi_buddy_suspend_free_assoc_resource(_adapter *adapter);
-+
-+#ifdef CONFIG_SET_SCAN_DENY_TIMER
-+void rtw_mi_set_scan_deny(_adapter *adapter, u32 ms);
-+void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms);
-+#else
-+#define rtw_mi_set_scan_deny(adapter, ms) do {} while (0)
-+#define rtw_mi_buddy_set_scan_deny(adapter, ms) do {} while (0)
-+#endif
-+
-+u8 rtw_mi_is_scan_deny(_adapter *adapter);
-+u8 rtw_mi_buddy_is_scan_deny(_adapter *adapter);
-+
-+void rtw_mi_beacon_update(_adapter *padapter);
-+void rtw_mi_buddy_beacon_update(_adapter *padapter);
-+
-+#ifndef CONFIG_MI_WITH_MBSSID_CAM
-+void rtw_mi_hal_dump_macaddr(void *sel, _adapter *padapter);
-+void rtw_mi_buddy_hal_dump_macaddr(void *sel, _adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+void rtw_mi_xmit_tasklet_schedule(_adapter *padapter);
-+void rtw_mi_buddy_xmit_tasklet_schedule(_adapter *padapter);
-+#endif
-+
-+u8 rtw_mi_busy_traffic_check(_adapter *padapter);
-+u8 rtw_mi_buddy_busy_traffic_check(_adapter *padapter);
-+
-+u8 rtw_mi_check_mlmeinfo_state(_adapter *padapter, u32 state);
-+u8 rtw_mi_buddy_check_mlmeinfo_state(_adapter *padapter, u32 state);
-+
-+u8 rtw_mi_check_fwstate(_adapter *padapter, sint state);
-+u8 rtw_mi_buddy_check_fwstate(_adapter *padapter, sint state);
-+enum {
-+	MI_LINKED,
-+	MI_ASSOC,
-+	MI_UNDER_WPS,
-+	MI_AP_MODE,
-+	MI_AP_ASSOC,
-+	MI_ADHOC,
-+	MI_ADHOC_ASSOC,
-+	MI_MESH,
-+	MI_MESH_ASSOC,
-+	MI_STA_NOLINK, /* this is misleading, but not used now */
-+	MI_STA_LINKED,
-+	MI_STA_LINKING,
-+};
-+u8 rtw_mi_check_status(_adapter *adapter, u8 type);
-+
-+void dump_dvobj_mi_status(void *sel, const char *fun_name, _adapter *adapter);
-+#ifdef DBG_IFACE_STATUS
-+#define DBG_IFACE_STATUS_DUMP(adapter)	dump_dvobj_mi_status(RTW_DBGDUMP, __func__, adapter)
-+#endif
-+void dump_mi_status(void *sel, struct dvobj_priv *dvobj);
-+
-+u8 rtw_mi_traffic_statistics(_adapter *padapter);
-+u8 rtw_mi_check_miracast_enabled(_adapter *padapter);
-+
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+u8 rtw_mi_check_pending_xmitbuf(_adapter *padapter);
-+u8 rtw_mi_buddy_check_pending_xmitbuf(_adapter *padapter);
-+#endif
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+#ifdef CONFIG_RTL8822B
-+	#include <rtl8822b_hal.h>
-+#elif defined(CONFIG_RTL8822C)
-+	#include <rtl8822c_hal.h>
-+#elif defined(CONFIG_RTL8723F)
-+	#include <rtl8723f_hal.h>
-+#else
-+	extern s32 _dequeue_writeport(PADAPTER padapter);
-+#endif
-+u8 rtw_mi_dequeue_writeport(_adapter *padapter);
-+u8 rtw_mi_buddy_dequeue_writeport(_adapter *padapter);
-+#endif
-+
-+void rtw_mi_adapter_reset(_adapter *padapter);
-+void rtw_mi_buddy_adapter_reset(_adapter *padapter);
-+
-+u8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter);
-+u8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter);
-+
-+extern void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter);
-+u8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter);
-+u8 rtw_mi_buddy_dynamic_chk_wk_hdl(_adapter *padapter);
-+
-+u8 rtw_mi_os_xmit_schedule(_adapter *padapter);
-+u8 rtw_mi_buddy_os_xmit_schedule(_adapter *padapter);
-+
-+u8 rtw_mi_report_survey_event(_adapter *padapter, union recv_frame *precv_frame);
-+u8 rtw_mi_buddy_report_survey_event(_adapter *padapter, union recv_frame *precv_frame);
-+
-+extern void sreset_start_adapter(_adapter *padapter);
-+extern void sreset_stop_adapter(_adapter *padapter);
-+u8 rtw_mi_sreset_adapter_hdl(_adapter *padapter, u8 bstart);
-+u8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart);
-+
-+#ifdef CONFIG_AP_MODE
-+#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE)
-+void rtw_mi_ap_info_restore(_adapter *adapter);
-+#endif
-+u8 rtw_mi_tx_beacon_hdl(_adapter *padapter);
-+u8 rtw_mi_buddy_tx_beacon_hdl(_adapter *padapter);
-+
-+u8 rtw_mi_set_tx_beacon_cmd(_adapter *padapter);
-+u8 rtw_mi_buddy_set_tx_beacon_cmd(_adapter *padapter);
-+#endif /* CONFIG_AP_MODE */
-+
-+#ifdef CONFIG_P2P
-+u8 rtw_mi_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state);
-+u8 rtw_mi_buddy_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state);
-+u8 rtw_mi_stay_in_p2p_mode(_adapter *padapter);
-+u8 rtw_mi_buddy_stay_in_p2p_mode(_adapter *padapter);
-+#endif
-+
-+_adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id);
-+_adapter *rtw_get_iface_by_macddr(_adapter *padapter, const u8 *mac_addr);
-+_adapter *rtw_get_iface_by_hwport(_adapter *padapter, u8 hw_port);
-+
-+void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe, u8 *pphy_status);
-+
-+#ifdef CONFIG_PCI_HCI
-+/*API be create temporary for MI, caller is interrupt-handler, PCIE's interrupt handler cannot apply to multi-AP*/
-+_adapter *rtw_mi_get_ap_adapter(_adapter *padapter);
-+#endif
-+
-+u8 rtw_mi_get_ld_sta_ifbmp(_adapter *adapter);
-+u8 rtw_mi_get_ap_mesh_ifbmp(_adapter *adapter);
-+void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b);
-+
-+#endif /*__RTW_MI_H_*/
-diff --git a/drivers/staging/rtl8723cs/include/rtw_mlme.h b/drivers/staging/rtl8723cs/include/rtw_mlme.h
-new file mode 100644
-index 000000000000..e3095a562d6a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_mlme.h
-@@ -0,0 +1,1238 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_MLME_H_
-+#define __RTW_MLME_H_
-+
-+
-+#define	MAX_BSS_CNT	128
-+/* #define   MAX_JOIN_TIMEOUT	2000 */
-+/* #define   MAX_JOIN_TIMEOUT	2500 */
-+#define   MAX_JOIN_TIMEOUT	6500
-+
-+/*	Commented by Albert 20101105
-+ *	Increase the scanning timeout because of increasing the SURVEY_TO value. */
-+#define	SCANQUEUE_LIFETIME 20000 /* 20sec, unit:msec */
-+
-+#define MAX_UNASSOC_STA_CNT 128
-+#define UNASSOC_STA_LIFETIME_MS 60000
-+
-+/*pmlmepriv->fw_state*/
-+#define WIFI_NULL_STATE				0x00000000
-+#define WIFI_ASOC_STATE				0x00000001 /* Linked */
-+#define WIFI_REASOC_STATE			0x00000002
-+#define WIFI_SLEEP_STATE			0x00000004
-+#define WIFI_STATION_STATE			0x00000008
-+#define WIFI_AP_STATE				0x00000010
-+#define WIFI_ADHOC_STATE			0x00000020
-+#define WIFI_ADHOC_MASTER_STATE		0x00000040
-+#define WIFI_UNDER_LINKING			0x00000080
-+#define WIFI_UNDER_WPS				0x00000100
-+#define WIFI_MESH_STATE				0x00000200
-+#define WIFI_STA_ALIVE_CHK_STATE		0x00000400
-+#define WIFI_UNDER_SURVEY			0x00000800 /* under site surveying */
-+/*#define WIFI_UNDEFINED_STATE			0x00001000*/
-+/*#define WIFI_UNDEFINED_STATE			0x00002000*/
-+/*#define WIFI_UNDEFINED_STATE			0x00004000*/
-+/*#define WIFI_UNDEFINED_STATE			0x00008000*/
-+#define WIFI_MP_STATE				0x00010000
-+/*#define WIFI_UNDEFINED_STATE			0x00020000*/
-+/*#define WIFI_UNDEFINED_STATE			0x00040000*/
-+/*#define WIFI_UNDEFINED_STATE			0x00080000*/
-+/*#define WIFI_UNDEFINED_STATE			0x00100000*/
-+/*#define WIFI_UNDEFINED_STATE			0x00200000*/ 
-+/*#define WIFI_UNDEFINED_STATE			0x00400000*/
-+#define WIFI_OP_CH_SWITCHING			0x00800000
-+#define WIFI_UNDER_KEY_HANDSHAKE		0x01000000
-+/*#define WIFI_UNDEFINED_STATE			0x02000000*/
-+/*#define WIFI_UNDEFINED_STATE			0x04000000*/
-+/*#define WIFI_UNDEFINED_STATE			0x08000000*/
-+/*#define WIFI_UNDEFINED_STATE			0x10000000*/
-+/*#define WIFI_UNDEFINED_STATE			0x20000000*/
-+#define WIFI_CSA_UPDATE_BEACON			0x40000000
-+#define WIFI_MONITOR_STATE			0x80000000
-+
-+
-+#define MIRACAST_DISABLED	0
-+#define MIRACAST_SOURCE		BIT0
-+#define MIRACAST_SINK		BIT1
-+
-+#define MIRACAST_MODE_REVERSE(mode) \
-+	((((mode) & MIRACAST_SOURCE) ? MIRACAST_SINK : 0) | (((mode) & MIRACAST_SINK) ? MIRACAST_SOURCE : 0))
-+
-+bool is_miracast_enabled(_adapter *adapter);
-+bool rtw_chk_miracast_mode(_adapter *adapter, u8 mode);
-+const char *get_miracast_mode_str(int mode);
-+void rtw_wfd_st_switch(struct sta_info *sta, bool on);
-+
-+#define MLME_STATE(adapter) get_fwstate(&((adapter)->mlmepriv))
-+#define CHK_MLME_STATE(adapter, state) check_fwstate(&((adapter)->mlmepriv), (state))
-+
-+#define MLME_IS_NULL(adapter) CHK_MLME_STATE(adapter, WIFI_NULL_STATE)
-+#define MLME_IS_STA(adapter) CHK_MLME_STATE(adapter, WIFI_STATION_STATE)
-+#define MLME_IS_AP(adapter) CHK_MLME_STATE(adapter, WIFI_AP_STATE)
-+#define MLME_IS_ADHOC(adapter) CHK_MLME_STATE(adapter, WIFI_ADHOC_STATE)
-+#define MLME_IS_ADHOC_MASTER(adapter) CHK_MLME_STATE(adapter, WIFI_ADHOC_MASTER_STATE)
-+#define MLME_IS_MESH(adapter) CHK_MLME_STATE(adapter, WIFI_MESH_STATE)
-+#define MLME_IS_MONITOR(adapter) CHK_MLME_STATE(adapter, WIFI_MONITOR_STATE)
-+#define MLME_IS_MP(adapter) CHK_MLME_STATE(adapter, WIFI_MP_STATE)
-+#ifdef CONFIG_P2P
-+	#define MLME_IS_PD(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_DEVICE)
-+	#define MLME_IS_GC(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_CLIENT)
-+	#define MLME_IS_GO(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_GO)
-+#else /* !CONFIG_P2P */
-+	#define MLME_IS_PD(adapter) 0
-+	#define MLME_IS_GC(adapter) 0
-+	#define MLME_IS_GO(adapter) 0
-+#endif /* !CONFIG_P2P */
-+
-+#define MLME_IS_MSRC(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SOURCE)
-+#define MLME_IS_MSINK(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SINK)
-+
-+#define MLME_IS_SCAN(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_SURVEY)
-+#define MLME_IS_LINKING(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_LINKING)
-+#define MLME_IS_ASOC(adapter) CHK_MLME_STATE(adapter, WIFI_ASOC_STATE)
-+#define MLME_IS_OPCH_SW(adapter) CHK_MLME_STATE(adapter, WIFI_OP_CH_SWITCHING)
-+#define MLME_IS_WPS(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_WPS)
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+#define MLME_IS_ROCH(adapter) (rtw_cfg80211_get_is_roch(adapter) == _TRUE)
-+#else
-+#define MLME_IS_ROCH(adapter) 0
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+#define MLME_IS_MGMT_TX(adapter) rtw_cfg80211_get_is_mgmt_tx(adapter)
-+#else
-+#define MLME_IS_MGMT_TX(adapter) 0
-+#endif
-+
-+#define MLME_STATE_FMT "%s%s%s%s%s%s%s%s%s%s%s%s"
-+#define MLME_STATE_ARG(adapter) \
-+	MLME_IS_STA((adapter)) ? (MLME_IS_GC((adapter)) ? " GC" : " STA") : \
-+	MLME_IS_AP((adapter)) ? (MLME_IS_GO((adapter)) ? " GO" : " AP") : \
-+	MLME_IS_ADHOC((adapter)) ? " ADHOC" : \
-+	MLME_IS_ADHOC_MASTER((adapter)) ? " ADHOC_M" : \
-+	MLME_IS_MESH((adapter)) ? " MESH" : \
-+	MLME_IS_MONITOR((adapter)) ? " MONITOR" : \
-+	MLME_IS_MP((adapter)) ? " MP" : "", \
-+	MLME_IS_PD((adapter)) ? " PD" : "", \
-+	MLME_IS_MSRC((adapter)) ? " MSRC" : "", \
-+	MLME_IS_MSINK((adapter)) ? " MSINK" : "", \
-+	MLME_IS_SCAN((adapter)) ? " SCAN" : "", \
-+	MLME_IS_LINKING((adapter)) ? " LINKING" : "", \
-+	MLME_IS_ASOC((adapter)) ? " ASOC" : "", \
-+	MLME_IS_OPCH_SW((adapter)) ? " OPCH_SW" : "", \
-+	MLME_IS_WPS((adapter)) ? " WPS" : "", \
-+	MLME_IS_ROCH((adapter)) ? " ROCH" : "", \
-+	MLME_IS_MGMT_TX((adapter)) ? " MGMT_TX" : "", \
-+	(MLME_STATE((adapter)) & WIFI_SLEEP_STATE) ? " SLEEP" : ""
-+
-+enum {
-+	MLME_ACTION_UNKNOWN,
-+	MLME_ACTION_NONE,
-+	MLME_SCAN_ENABLE, /* WIFI_UNDER_SURVEY */
-+	MLME_SCAN_ENTER, /* WIFI_UNDER_SURVEY && !SCAN_DISABLE && !SCAN_BACK_OP */
-+	MLME_SCAN_DONE, /*  WIFI_UNDER_SURVEY && (SCAN_DISABLE || SCAN_BACK_OP) */
-+	MLME_SCAN_DISABLE, /* WIFI_UNDER_SURVEY is going to be cleared */
-+	MLME_STA_CONNECTING,
-+	MLME_STA_CONNECTED,
-+	MLME_STA_DISCONNECTED,
-+	MLME_TDLS_LINKED,
-+	MLME_TDLS_NOLINK,
-+	MLME_AP_STARTED,
-+	MLME_AP_STOPPED,
-+	MLME_ADHOC_STARTED,
-+	MLME_ADHOC_STOPPED,
-+	MLME_MESH_STARTED,
-+	MLME_MESH_STOPPED,
-+	MLME_OPCH_SWITCH,
-+};
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+enum MODE_WOW_KEEP_ALIVE_PATTERN {
-+	wow_keep_alive_pattern_disable = 0,
-+	wow_keep_alive_pattern_tx,
-+	wow_keep_alive_pattern_trx,
-+	wow_keep_alive_pattern_trx_with_ack
-+};
-+#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+enum dot11AuthAlgrthmNum {
-+	dot11AuthAlgrthm_Open = 0,
-+	dot11AuthAlgrthm_Shared,
-+	dot11AuthAlgrthm_8021X,
-+	dot11AuthAlgrthm_Auto,
-+	dot11AuthAlgrthm_WAPI,
-+	dot11AuthAlgrthm_MaxNum
-+};
-+
-+/**
-+ * enum mlme_auth_type - AuthenticationType
-+ *
-+ * @MLME_AUTHTYPE_OPEN_SYSTEM: Open System authentication
-+ * @MLME_AUTHTYPE_SHARED_KEY: Shared Key authentication (WEP only)
-+ * @MLME_AUTHTYPE_FT: Fast BSS Transition (IEEE 802.11r)
-+ * @MLME_AUTHTYPE_NETWORK_EAP: Network EAP (some Cisco APs and mainly LEAP)
-+ * @MLME_AUTHTYPE_SAE: Simultaneous authentication of equals
-+ * @MLME_AUTHTYPE_FILS_SK: Fast Initial Link Setup shared key
-+ * @MLME_AUTHTYPE_FILS_SK_PFS: Fast Initial Link Setup shared key with PFS
-+ * @MLME_AUTHTYPE_FILS_PK: Fast Initial Link Setup public key
-+ * @__MLME_AUTHTYPE_NUM: internal
-+ * @MLME_AUTHTYPE_MAX: maximum valid auth algorithm
-+ * @MLME_AUTHTYPE_AUTOMATIC: determine automatically (if necessary by trying
-+ *      multiple times); this is invalid in netlink -- leave out the attribute
-+ *      for this on CONNECT commands.
-+ */
-+enum mlme_auth_type {
-+	MLME_AUTHTYPE_OPEN_SYSTEM,
-+	MLME_AUTHTYPE_SHARED_KEY,
-+	MLME_AUTHTYPE_FT,
-+	MLME_AUTHTYPE_NETWORK_EAP,
-+	MLME_AUTHTYPE_SAE,
-+	MLME_AUTHTYPE_FILS_SK,
-+	MLME_AUTHTYPE_FILS_SK_PFS,
-+	MLME_AUTHTYPE_FILS_PK,
-+
-+	/* keep last */
-+	__MLME_AUTHTYPE_NUM,
-+	MLME_AUTHTYPE_MAX = __MLME_AUTHTYPE_NUM - 1,
-+	MLME_AUTHTYPE_AUTOMATIC
-+};
-+
-+/* Scan type including active and passive scan. */
-+typedef enum _RT_SCAN_TYPE {
-+	SCAN_PASSIVE,
-+	SCAN_ACTIVE,
-+	SCAN_MIX,
-+} RT_SCAN_TYPE, *PRT_SCAN_TYPE;
-+
-+#define WIFI_FREQUENCY_BAND_AUTO 0
-+#define WIFI_FREQUENCY_BAND_5GHZ 1
-+#define WIFI_FREQUENCY_BAND_2GHZ 2
-+
-+#define rtw_band_valid(band) ((band) <= WIFI_FREQUENCY_BAND_2GHZ)
-+
-+enum DriverInterface {
-+	DRIVER_WEXT =  1,
-+	DRIVER_CFG80211 = 2
-+};
-+
-+enum SCAN_RESULT_TYPE {
-+	SCAN_RESULT_P2P_ONLY = 0,		/*	Will return all the P2P devices. */
-+	SCAN_RESULT_ALL = 1,			/*	Will return all the scanned device, include AP. */
-+	SCAN_RESULT_WFD_TYPE = 2		/*	Will just return the correct WFD device. */
-+									/*	If this device is Miracast sink device, it will just return all the Miracast source devices. */
-+};
-+
-+/*
-+
-+there are several "locks" in mlme_priv,
-+since mlme_priv is a shared resource between many threads,
-+like ISR/Call-Back functions, the OID handlers, and even timer functions.
-+
-+
-+Each _queue has its own locks, already.
-+Other items are protected by mlme_priv.lock.
-+
-+To avoid possible dead lock, any thread trying to modifiying mlme_priv
-+SHALL not lock up more than one locks at a time!
-+
-+*/
-+
-+
-+#define traffic_threshold	10
-+#define	traffic_scan_period	500
-+
-+typedef struct _RT_LINK_DETECT_T {
-+	u32				NumTxOkInPeriod;
-+	u32				NumRxOkInPeriod;
-+	u32				NumRxUnicastOkInPeriod;
-+	BOOLEAN			bBusyTraffic;
-+	BOOLEAN			bTxBusyTraffic;
-+	BOOLEAN			bRxBusyTraffic;
-+	BOOLEAN			bHigherBusyTraffic; /* For interrupt migration purpose. */
-+	BOOLEAN			bHigherBusyRxTraffic; /* We may disable Tx interrupt according as Rx traffic. */
-+	BOOLEAN			bHigherBusyTxTraffic; /* We may disable Tx interrupt according as Tx traffic. */
-+	/* u8 TrafficBusyState; */
-+	u8 TrafficTransitionCount;
-+	u32 LowPowerTransitionCount;
-+} RT_LINK_DETECT_T, *PRT_LINK_DETECT_T;
-+
-+struct profile_info {
-+	u8	ssidlen;
-+	u8	ssid[WLAN_SSID_MAXLEN];
-+	u8	peermac[ETH_ALEN];
-+};
-+
-+struct tx_invite_req_info {
-+	u8					token;
-+	u8					benable;
-+	u8					go_ssid[WLAN_SSID_MAXLEN];
-+	u8					ssidlen;
-+	u8					go_bssid[ETH_ALEN];
-+	u8					peer_macaddr[ETH_ALEN];
-+	u8					operating_ch;	/*	This information will be set by using the p2p_set op_ch=x */
-+	u8					peer_ch;		/*	The listen channel for peer P2P device */
-+
-+};
-+
-+struct tx_invite_resp_info {
-+	u8					token;	/*	Used to record the dialog token of p2p invitation request frame. */
-+};
-+
-+#ifdef CONFIG_WFD
-+
-+struct wifi_display_info {
-+	u16							wfd_enable;			/*	Eanble/Disable the WFD function. */
-+	u16							init_rtsp_ctrlport;	/* init value of rtsp_ctrlport when WFD enable */
-+	u16							rtsp_ctrlport;		/* TCP port number at which the this WFD device listens for RTSP messages, 0 when WFD disable */
-+	u16							tdls_rtsp_ctrlport;	/* rtsp_ctrlport used by tdls, will sync when rtsp_ctrlport is changed by user */
-+	u16							peer_rtsp_ctrlport;	/*	TCP port number at which the peer WFD device listens for RTSP messages */
-+													/*	This filed should be filled when receiving the gropu negotiation request */
-+
-+	u8							peer_session_avail;	/*	WFD session is available or not for the peer wfd device. */
-+													/*	This variable will be set when sending the provisioning discovery request to peer WFD device. */
-+													/*	And this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command. */
-+	u8							ip_address[4];
-+	u8							peer_ip_address[4];
-+	u8							wfd_pc;				/*	WFD preferred connection */
-+													/*	0 -> Prefer to use the P2P for WFD connection on peer side. */
-+													/*	1 -> Prefer to use the TDLS for WFD connection on peer side. */
-+
-+	u8							wfd_device_type;	/*	WFD Device Type */
-+													/*	0 -> WFD Source Device */
-+													/*	1 -> WFD Primary Sink Device */
-+	enum	SCAN_RESULT_TYPE	scan_result_type;	/*	Used when P2P is enable. This parameter will impact the scan result. */
-+	u8 op_wfd_mode;
-+	u8 stack_wfd_mode;
-+};
-+#endif /* CONFIG_WFD */
-+
-+struct tx_provdisc_req_info {
-+	u16					wps_config_method_request;	/*	Used when sending the provisioning request frame */
-+	u16					peer_channel_num[2];		/*	The channel number which the receiver stands. */
-+	NDIS_802_11_SSID	ssid;
-+	u8					peerDevAddr[ETH_ALEN];		/*	Peer device address */
-+	u8					peerIFAddr[ETH_ALEN];		/*	Peer interface address */
-+	u8					benable;					/*	This provision discovery request frame is trigger to send or not */
-+};
-+
-+struct rx_provdisc_req_info {	/* When peer device issue prov_disc_req first, we should store the following informations */
-+	u8					peerDevAddr[ETH_ALEN];		/*	Peer device address */
-+	u8					strconfig_method_desc_of_prov_disc_req[4];	/*	description for the config method located in the provisioning discovery request frame.	 */
-+																	/*	The UI must know this information to know which config method the remote p2p device is requiring. */
-+};
-+
-+struct tx_nego_req_info {
-+	u16					peer_channel_num[2];		/*	The channel number which the receiver stands. */
-+	u8					peerDevAddr[ETH_ALEN];		/*	Peer device address */
-+	u8					benable;					/*	This negoitation request frame is trigger to send or not */
-+	u8					peer_ch;					/*	The listen channel for peer P2P device */
-+};
-+
-+struct group_id_info {
-+	u8					go_device_addr[ETH_ALEN];	/*	The GO's device address of this P2P group */
-+	u8					ssid[WLAN_SSID_MAXLEN];		/*	The SSID of this P2P group */
-+};
-+
-+struct scan_limit_info {
-+	u8					scan_op_ch_only;			/*	When this flag is set, the driver should just scan the operation channel */
-+#ifndef CONFIG_P2P_OP_CHK_SOCIAL_CH
-+	u8					operation_ch[2];				/*	Store the operation channel of invitation request frame */
-+#else
-+	u8					operation_ch[5];				/*	Store additional channel 1,6,11  for Android 4.2 IOT & Nexus 4 */
-+#endif /* CONFIG_P2P_OP_CHK_SOCIAL_CH */
-+};
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+
-+enum P2P_WOWLAN_RECV_FRAME_TYPE {
-+	P2P_WOWLAN_RECV_NEGO_REQ = 0,
-+	P2P_WOWLAN_RECV_INVITE_REQ = 1,
-+	P2P_WOWLAN_RECV_PROVISION_REQ = 2,
-+};
-+
-+struct p2p_wowlan_info {
-+
-+	u8						is_trigger;
-+	enum P2P_WOWLAN_RECV_FRAME_TYPE	wowlan_recv_frame_type;
-+	u8						wowlan_peer_addr[ETH_ALEN];
-+	u16						wowlan_peer_wpsconfig;
-+	u8						wowlan_peer_is_persistent;
-+	u8						wowlan_peer_invitation_type;
-+};
-+
-+#endif /* CONFIG_P2P_WOWLAN */
-+
-+struct wifidirect_info {
-+	_adapter				*padapter;
-+	_timer					find_phase_timer;
-+	_timer					restore_p2p_state_timer;
-+
-+	/*	Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer. */
-+	_timer					pre_tx_scan_timer;
-+	_timer					reset_ch_sitesurvey;
-+	_timer					reset_ch_sitesurvey2;	/*	Just for resetting the scan limit function by using p2p nego */
-+
-+	struct tx_provdisc_req_info	tx_prov_disc_info;
-+	struct rx_provdisc_req_info rx_prov_disc_info;
-+	struct tx_invite_req_info	invitereq_info;
-+	struct profile_info			profileinfo[P2P_MAX_PERSISTENT_GROUP_NUM];	/*	Store the profile information of persistent group */
-+	struct tx_invite_resp_info	inviteresp_info;
-+	struct tx_nego_req_info	nego_req_info;
-+	struct group_id_info		groupid_info;	/*	Store the group id information when doing the group negotiation handshake. */
-+	struct scan_limit_info		rx_invitereq_info;	/*	Used for get the limit scan channel from the Invitation procedure */
-+	struct scan_limit_info		p2p_info;		/*	Used for get the limit scan channel from the P2P negotiation handshake */
-+#ifdef CONFIG_WFD
-+	struct wifi_display_info		*wfd_info;
-+#endif
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+	struct p2p_wowlan_info		p2p_wow_info;
-+#endif /* CONFIG_P2P_WOWLAN */
-+
-+	enum P2P_ROLE			role;
-+	enum P2P_STATE			pre_p2p_state;
-+	enum P2P_STATE			p2p_state;
-+	u8						device_addr[ETH_ALEN];	/*	The device address should be the mac address of this device. */
-+	u8						interface_addr[ETH_ALEN];
-+	u8						social_chan[4];
-+	u8						listen_channel;
-+	u8						operating_channel;
-+	u8						listen_dwell;		/*	This value should be between 1 and 3 */
-+	u8						support_rate[8];
-+	u8						p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN];
-+	u8						intent;		/*	should only include the intent value. */
-+	u8						p2p_peer_interface_addr[ETH_ALEN];
-+	u8						p2p_peer_device_addr[ETH_ALEN];
-+	u8						peer_intent;	/*	Included the intent value and tie breaker value. */
-+	u8						device_name[WPS_MAX_DEVICE_NAME_LEN];	/*	Device name for displaying on searching device screen */
-+	u16						device_name_len;
-+	u8						profileindex;	/*	Used to point to the index of profileinfo array */
-+	u8						peer_operating_ch;
-+	u8						find_phase_state_exchange_cnt;
-+	u16						device_password_id_for_nego;	/*	The device password ID for group negotation */
-+	u8						negotiation_dialog_token;
-+	u8						nego_ssid[WLAN_SSID_MAXLEN];	/*	SSID information for group negotitation */
-+	u8						nego_ssidlen;
-+	u8						p2p_group_ssid[WLAN_SSID_MAXLEN];
-+	u8						p2p_group_ssid_len;
-+	u8						persistent_supported;		/*	Flag to know the persistent function should be supported or not. */
-+														/*	In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. */
-+														/*	0: disable */
-+														/*	1: enable */
-+	u8						session_available;			/*	Flag to set the WFD session available to enable or disable "by Sigma" */
-+														/*	In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. */
-+														/*	0: disable */
-+														/*	1: enable */
-+
-+	u8						wfd_tdls_enable;			/*	Flag to enable or disable the TDLS by WFD Sigma */
-+														/*	0: disable */
-+														/*	1: enable */
-+	u8						wfd_tdls_weaksec;			/*	Flag to enable or disable the weak security function for TDLS by WFD Sigma */
-+														/*	0: disable */
-+														/*	In this case, the driver can't issue the tdsl setup request frame. */
-+														/*	1: enable */
-+														/*	In this case, the driver can issue the tdls setup request frame */
-+														/*	even the current security is weak security. */
-+
-+	enum	P2P_WPSINFO		ui_got_wps_info;			/*	This field will store the WPS value (PIN value or PBC) that UI had got from the user. */
-+	u16						supported_wps_cm;			/*	This field describes the WPS config method which this driver supported. */
-+														/*	The value should be the combination of config method defined in page104 of WPS v2.0 spec.	 */
-+	u8						external_uuid;				/* UUID flag */
-+	u8						uuid[16];					/* UUID */
-+	uint						channel_list_attr_len;	/*	This field will contain the length of body of P2P Channel List attribute of group negotitation response frame. */
-+	u8						channel_list_attr[100];		/*	This field will contain the body of P2P Channel List attribute of group negotitation response frame. */
-+														/*	We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. */
-+	u8						driver_interface;			/*	Indicate DRIVER_WEXT or DRIVER_CFG80211 */
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	u16						ext_listen_interval;	/*	The interval to be available with legacy AP (ms) */
-+	u16						ext_listen_period;	/*	The time period to be available for P2P listen state (ms) */
-+#endif
-+#ifdef CONFIG_P2P_PS
-+	enum P2P_PS_MODE		p2p_ps_mode; /* indicate p2p ps mode */
-+	enum P2P_PS_STATE		p2p_ps_state; /* indicate p2p ps state */
-+	u8						noa_index; /* Identifies and instance of Notice of Absence timing. */
-+	u8						ctwindow; /* Client traffic window. A period of time in TU after TBTT. */
-+	u8						opp_ps; /* opportunistic power save. */
-+	u8						noa_num; /* number of NoA descriptor in P2P IE. */
-+	u8						noa_count[P2P_MAX_NOA_NUM]; /* Count for owner, Type of client. */
-+	u32						noa_duration[P2P_MAX_NOA_NUM]; /* Max duration for owner, preferred or min acceptable duration for client. */
-+	u32						noa_interval[P2P_MAX_NOA_NUM]; /* Length of interval for owner, preferred or max acceptable interval of client. */
-+	u32						noa_start_time[P2P_MAX_NOA_NUM]; /* schedule expressed in terms of the lower 4 bytes of the TSF timer. */
-+#endif /* CONFIG_P2P_PS */
-+};
-+
-+struct tdls_ss_record {	/* signal strength record */
-+	u8		macaddr[ETH_ALEN];
-+	u8		RxPWDBAll;
-+	u8		is_tdls_sta;	/* _TRUE: direct link sta, _FALSE: else */
-+};
-+
-+struct tdls_temp_mgmt {
-+	u8	initiator;	/* 0: None, 1: we initiate, 2: peer initiate */
-+	u8	peer_addr[ETH_ALEN];
-+};
-+
-+#ifdef CONFIG_TDLS_CH_SW
-+struct tdls_ch_switch {
-+	u32	ch_sw_state;
-+	ATOMIC_T	chsw_on;
-+	u8	addr[ETH_ALEN];
-+	u8	off_ch_num;
-+	u8	ch_offset;
-+	u8	bcn_early_reg_bkp;
-+	u32	cur_time;
-+	u8	delay_switch_back;
-+	u8	dump_stack;
-+	struct submit_ctx	chsw_sctx;
-+};
-+#endif
-+
-+struct tdls_info {
-+	u8					ap_prohibited;
-+	u8					ch_switch_prohibited;
-+	u8					link_established;
-+	u8					sta_cnt;
-+	u8					sta_maximum;	/* 1:tdls sta is equal (NUM_STA-1), reach max direct link number; 0: else; */
-+	struct tdls_ss_record	ss_record;
-+#ifdef CONFIG_TDLS_CH_SW
-+	struct tdls_ch_switch	chsw_info;
-+#endif
-+
-+	u8					ch_sensing;
-+	u8					cur_channel;
-+	u8					collect_pkt_num[MAX_CHANNEL_NUM];
-+	_lock				cmd_lock;
-+	_lock				hdl_lock;
-+	u8					watchdog_count;
-+	u8					dev_discovered;		/* WFD_TDLS: for sigma test */
-+
-+	/* Let wpa_supplicant to setup*/
-+	u8					driver_setup;
-+#ifdef CONFIG_WFD
-+	struct wifi_display_info		*wfd_info;
-+#endif
-+
-+	struct submit_ctx	*tdls_sctx;
-+};
-+
-+struct tdls_txmgmt {
-+	u8 peer[ETH_ALEN];
-+	u8 action_code;
-+	u8 dialog_token;
-+	u16 status_code;
-+	u8 *buf;
-+	size_t len;
-+};
-+
-+/* used for mlme_priv.roam_flags */
-+enum {
-+	RTW_ROAM_ON_EXPIRED = BIT0,
-+	RTW_ROAM_ON_RESUME = BIT1,
-+	RTW_ROAM_ACTIVE = BIT2,
-+};
-+
-+#define UNASOC_STA_SRC_RX_BMC		0
-+#define UNASOC_STA_SRC_RX_NMY_UC	1
-+#define UNASOC_STA_SRC_NUM			2
-+
-+#define UNASOC_STA_MODE_DISABLED	0
-+#define UNASOC_STA_MODE_INTERESTED	1
-+#define UNASOC_STA_MODE_ALL			2
-+#define UNASOC_STA_MODE_NUM			3
-+
-+#define UNASOC_STA_DEL_CHK_SKIP		0
-+#define UNASOC_STA_DEL_CHK_ALIVE	1
-+#define UNASOC_STA_DEL_CHK_DELETED	2
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+struct unassoc_sta_info {
-+	_list list;
-+	u8 addr[ETH_ALEN];
-+	u8 interested;
-+	s8 recv_signal_power;
-+	systime time;
-+};
-+#endif
-+
-+struct mlme_priv {
-+
-+	_lock	lock;
-+	sint	fw_state;	/* shall we protect this variable? maybe not necessarily... */
-+	u8	to_join; /* flag */
-+	u16 join_status;
-+#ifdef CONFIG_LAYER2_ROAMING
-+	u8 to_roam; /* roaming trying times */
-+	struct wlan_network *roam_network; /* the target of active roam */
-+	u8 roam_flags;
-+	u8 roam_rssi_diff_th; /* rssi difference threshold for active scan candidate selection */
-+	u32 roam_scan_int; 		/* scan interval for active roam (Unit:2 second)*/
-+	u32 roam_scanr_exp_ms; /* scan result expire time in ms  for roam */
-+	u8 roam_tgt_addr[ETH_ALEN]; /* request to roam to speicific target without other consideration */
-+	u8 roam_rssi_threshold;
-+	systime last_roaming;
-+	bool need_to_roam;
-+#endif
-+
-+	u32 defs_lmt_sta;
-+	u32 defs_lmt_time;
-+
-+	u8	*nic_hdl;
-+	u32	max_bss_cnt;		/*	The size of scan queue	*/
-+	_list		*pscanned;
-+	_queue	free_bss_pool;
-+	_queue	scanned_queue;
-+	u8		*free_bss_buf;
-+	u32	num_of_scanned;
-+
-+	NDIS_802_11_SSID	assoc_ssid;
-+	u8	assoc_bssid[6];
-+	u16	assoc_ch;		/* 0 reserved for no specific channel */
-+
-+	struct wlan_network	cur_network;
-+	struct wlan_network *cur_network_scanned;
-+
-+	/* bcn check info */
-+	struct beacon_keys cur_beacon_keys; /* save current beacon keys */
-+#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
-+	struct beacon_keys new_beacon_keys; /* save new beacon keys */
-+	u8 new_beacon_cnts; /* if new_beacon_cnts >= threshold, ap beacon is changed */
-+#endif
-+
-+#ifdef CONFIG_ARP_KEEP_ALIVE
-+	/* for arp offload keep alive */
-+	u8 bGetGateway;
-+	u8	GetGatewayTryCnt;
-+	u8	gw_mac_addr[ETH_ALEN];
-+	u8	gw_ip[4];
-+#endif
-+
-+	/* uint wireless_mode; no used, remove it */
-+
-+	u32	auto_scan_int_ms;
-+
-+	_timer assoc_timer;
-+
-+	uint assoc_by_bssid;
-+	uint assoc_by_rssi;
-+
-+	_timer scan_to_timer; /* driver itself handles scan_timeout status. */
-+	systime scan_start_time; /* used to evaluate the time spent in scanning */
-+
-+#ifdef CONFIG_SET_SCAN_DENY_TIMER
-+	_timer set_scan_deny_timer;
-+	ATOMIC_T set_scan_deny; /* 0: allowed, 1: deny */
-+#endif
-+	u8 wpa_phase;/*wpa_phase after wps finished*/
-+
-+	struct qos_priv qospriv;
-+
-+#ifdef CONFIG_80211N_HT
-+
-+	/* Number of non-HT AP/stations */
-+	int num_sta_no_ht;
-+
-+	/* Number of HT AP/stations 20 MHz */
-+	/* int num_sta_ht_20mhz; */
-+
-+
-+	int num_FortyMHzIntolerant;
-+
-+	struct ht_priv	htpriv;
-+
-+#endif
-+
-+#ifdef CONFIG_80211AC_VHT
-+	struct vht_priv	vhtpriv;
-+#ifdef ROKU_PRIVATE
-+	/*infra mode, used to store AP's info*/
-+	struct vht_priv_infra_ap vhtpriv_infra_ap;
-+#endif /* ROKU_PRIVATE */
-+#endif
-+
-+#ifdef ROKU_PRIVATE
-+	struct ht_priv_infra_ap htpriv_infra_ap;
-+#endif /* ROKU_PRIVATE */
-+
-+#ifdef CONFIG_RTW_80211R
-+	struct ft_roam_info ft_roam;
-+#endif
-+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
-+	struct roam_nb_info nb_info;
-+	u8 ch_cnt;
-+#endif
-+
-+	RT_LINK_DETECT_T	LinkDetectInfo;
-+
-+	u8	acm_mask; /* for wmm acm mask */
-+	RT_SCAN_TYPE	scan_mode; /* active: 1, passive: 0 */
-+
-+	u8 *wps_probe_req_ie;
-+	u32 wps_probe_req_ie_len;
-+
-+	u8 ext_capab_ie_data[8];/*currently for ap mode only*/
-+	u8 ext_capab_ie_len;
-+
-+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
-+	/* Number of associated Non-ERP stations (i.e., stations using 802.11b
-+	 * in 802.11g BSS) */
-+	int num_sta_non_erp;
-+
-+	/* Number of associated stations that do not support Short Slot Time */
-+	int num_sta_no_short_slot_time;
-+
-+	/* Number of associated stations that do not support Short Preamble */
-+	int num_sta_no_short_preamble;
-+
-+	ATOMIC_T olbc; /* Overlapping Legacy BSS Condition (Legacy b/g)*/
-+
-+	/* Number of HT associated stations that do not support greenfield */
-+	int num_sta_ht_no_gf;
-+
-+	/* Number of associated non-HT stations */
-+	/* int num_sta_no_ht; */
-+
-+	/* Number of HT associated stations 20 MHz */
-+	int num_sta_ht_20mhz;
-+
-+	/* number of associated stations 40MHz intolerant */
-+	int num_sta_40mhz_intolerant;
-+
-+	/* Overlapping BSS information */
-+	ATOMIC_T olbc_ht;
-+
-+#ifdef CONFIG_80211N_HT
-+	int ht_20mhz_width_req;
-+	int ht_intolerant_ch_reported;
-+	u16 ht_op_mode;
-+	u8 sw_to_20mhz; /*switch to 20Mhz BW*/
-+#endif /* CONFIG_80211N_HT */
-+
-+#ifdef CONFIG_RTW_80211R
-+	u8 *auth_rsp;
-+	u32 auth_rsp_len;
-+#endif
-+#endif /* CONFIG_AP_MODE and CONFIG_NATIVEAP_MLME */
-+
-+	u8 *assoc_req;
-+	u32 assoc_req_len;
-+	u8 *assoc_rsp;
-+	u32 assoc_rsp_len;
-+
-+#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
-+	/* u8 *wps_probe_req_ie; */
-+	/* u32 wps_probe_req_ie_len; */
-+
-+	u8 *wps_beacon_ie;
-+	u32 wps_beacon_ie_len;
-+
-+	u8 *wps_probe_resp_ie;
-+	u32 wps_probe_resp_ie_len;
-+
-+	u8 *wps_assoc_resp_ie;
-+	u32 wps_assoc_resp_ie_len;
-+
-+	u8 *p2p_beacon_ie;
-+	u32 p2p_beacon_ie_len;
-+
-+	u8 *p2p_probe_req_ie;
-+	u32 p2p_probe_req_ie_len;
-+
-+	u8 *p2p_probe_resp_ie;
-+	u32 p2p_probe_resp_ie_len;
-+
-+	u8 *p2p_go_probe_resp_ie;		/* for GO */
-+	u32 p2p_go_probe_resp_ie_len;	/* for GO */
-+
-+	u8 *p2p_assoc_req_ie;
-+	u32 p2p_assoc_req_ie_len;
-+
-+	u8 *p2p_assoc_resp_ie;
-+	u32 p2p_assoc_resp_ie_len;
-+
-+	_lock	bcn_update_lock;
-+	u8		update_bcn;
-+
-+	u8 ori_ch;
-+	u8 ori_bw;
-+	u8 ori_offset;
-+	#ifdef CONFIG_80211AC_VHT
-+	u8 ori_vht_en;
-+	#endif
-+
-+	u8 ap_isolate;
-+#endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */
-+
-+#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
-+	u8 *wfd_beacon_ie;
-+	u32 wfd_beacon_ie_len;
-+
-+	u8 *wfd_probe_req_ie;
-+	u32 wfd_probe_req_ie_len;
-+
-+	u8 *wfd_probe_resp_ie;
-+	u32 wfd_probe_resp_ie_len;
-+
-+	u8 *wfd_go_probe_resp_ie;		/* for GO */
-+	u32 wfd_go_probe_resp_ie_len;	/* for GO */
-+
-+	u8 *wfd_assoc_req_ie;
-+	u32 wfd_assoc_req_ie_len;
-+
-+	u8 *wfd_assoc_resp_ie;
-+	u32 wfd_assoc_resp_ie_len;
-+#endif
-+
-+#ifdef CONFIG_RTW_MBO
-+	u8 *pcell_data_cap_ie;
-+	u32 cell_data_cap_len;
-+#endif
-+
-+#ifdef RTK_DMP_PLATFORM
-+	/* DMP kobject_hotplug function  signal need in passive level */
-+	_workitem	Linkup_workitem;
-+	_workitem	Linkdown_workitem;
-+#endif
-+
-+#ifdef RTW_BUSY_DENY_SCAN
-+	systime lastscantime;
-+#endif
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	u8	scanning_via_buddy_intf;
-+#endif
-+
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+	u32 vendor_ie_mask[WLAN_MAX_VENDOR_IE_NUM];
-+	u8 vendor_ie[WLAN_MAX_VENDOR_IE_NUM][WLAN_MAX_VENDOR_IE_LEN];
-+	u32 vendor_ielen[WLAN_MAX_VENDOR_IE_NUM];
-+#endif
-+#ifdef CONFIG_RTW_MULTI_AP
-+	u8 unassoc_sta_mode_of_stype[UNASOC_STA_SRC_NUM];
-+	_queue unassoc_sta_queue;
-+	_queue free_unassoc_sta_queue;
-+	u8 *free_unassoc_sta_buf;
-+	u32 interested_unassoc_sta_cnt;
-+	u32 max_unassoc_sta_cnt;
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+	struct unassoc_sta_info cmap_unassoc_sta[CMAP_UNASSOC_METRICS_STA_MAX];
-+	u8 cmap_unassoc_sta_cnt;
-+	_timer cmap_unassoc_sta_timer;
-+#endif
-+#endif
-+};
-+
-+#define mlme_set_scan_to_timer(mlme, ms) \
-+	do { \
-+		/* RTW_INFO("%s set_scan_to_timer(%p, %d)\n", __FUNCTION__, (mlme), (ms)); */ \
-+		_set_timer(&(mlme)->scan_to_timer, (ms)); \
-+	} while (0)
-+
-+#define rtw_mlme_set_auto_scan_int(adapter, ms) \
-+	do { \
-+		adapter->mlmepriv.auto_scan_int_ms = ms; \
-+	} while (0)
-+
-+#define RTW_AUTO_SCAN_REASON_UNSPECIFIED		0
-+#define RTW_AUTO_SCAN_REASON_2040_BSS			BIT0
-+#define RTW_AUTO_SCAN_REASON_ACS				BIT1
-+#define RTW_AUTO_SCAN_REASON_ROAM				BIT2
-+#define RTW_AUTO_SCAN_REASON_MESH_OFFCH_CAND	BIT3
-+
-+void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason);
-+
-+#ifdef CONFIG_AP_MODE
-+
-+struct hostapd_priv {
-+	_adapter *padapter;
-+
-+#ifdef CONFIG_HOSTAPD_MLME
-+	struct net_device *pmgnt_netdev;
-+	struct usb_anchor anchored;
-+#endif
-+
-+};
-+
-+extern int hostapd_mode_init(_adapter *padapter);
-+extern void hostapd_mode_unload(_adapter *padapter);
-+#endif
-+
-+
-+extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status);
-+extern void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf);
-+extern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf);
-+extern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf);
-+extern void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf);
-+extern void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf);
-+void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id);
-+void rtw_sta_mstatus_report(_adapter *adapter);
-+extern void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf);
-+#ifdef CONFIG_IEEE80211W
-+void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf);
-+#endif /* CONFIG_IEEE80211W */
-+thread_return event_thread(thread_context context);
-+
-+extern void rtw_free_network_queue(_adapter *adapter, u8 isfreeall);
-+extern int rtw_init_mlme_priv(_adapter *adapter);/* (struct mlme_priv *pmlmepriv); */
-+
-+extern void rtw_free_mlme_priv(struct mlme_priv *pmlmepriv);
-+
-+
-+extern sint rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv);
-+extern sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint keyid, u8 set_tx, bool enqueue);
-+extern sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv);
-+
-+__inline static u8 *get_bssid(struct mlme_priv *pmlmepriv)
-+{
-+	/* if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid */
-+	/* if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address */
-+	return pmlmepriv->cur_network.network.MacAddress;
-+}
-+
-+__inline static sint check_fwstate(struct mlme_priv *pmlmepriv, sint state)
-+{
-+	if ((state == WIFI_NULL_STATE) &&
-+		(pmlmepriv->fw_state == WIFI_NULL_STATE))
-+		return _TRUE;
-+
-+	if (pmlmepriv->fw_state & state)
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+__inline static sint get_fwstate(struct mlme_priv *pmlmepriv)
-+{
-+	return pmlmepriv->fw_state;
-+}
-+
-+/*
-+ * No Limit on the calling context,
-+ * therefore set it to be the critical section...
-+ *
-+ * ### NOTE:#### (!!!!)
-+ * MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock
-+ */
-+extern void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state);
-+
-+static inline void set_fwstate(struct mlme_priv *pmlmepriv, sint state)
-+{
-+	pmlmepriv->fw_state |= state;
-+	rtw_mi_update_iface_status(pmlmepriv, state);
-+}
-+static inline void init_fwstate(struct mlme_priv *pmlmepriv, sint state)
-+{
-+	pmlmepriv->fw_state = state;
-+	rtw_mi_update_iface_status(pmlmepriv, state);
-+}
-+
-+static inline void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state)
-+{
-+	pmlmepriv->fw_state &= ~state;
-+	rtw_mi_update_iface_status(pmlmepriv, state);
-+}
-+
-+/*
-+ * No Limit on the calling context,
-+ * therefore set it to be the critical section...
-+ */
-+static inline void clr_fwstate(struct mlme_priv *pmlmepriv, sint state)
-+{
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+	_clr_fwstate_(pmlmepriv, state);
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+}
-+
-+static inline void up_scanned_network(struct mlme_priv *pmlmepriv)
-+{
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+	pmlmepriv->num_of_scanned++;
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+}
-+u8 rtw_is_adapter_up(_adapter *padapter);
-+
-+__inline static void down_scanned_network(struct mlme_priv *pmlmepriv)
-+{
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+	pmlmepriv->num_of_scanned--;
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+}
-+
-+__inline static void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint val)
-+{
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+	pmlmepriv->num_of_scanned = val;
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+}
-+
-+extern u16 rtw_get_capability(WLAN_BSSID_EX *bss);
-+extern bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target);
-+extern void rtw_disconnect_hdl_under_linked(_adapter *adapter, struct sta_info *psta, u8 free_assoc);
-+extern void rtw_generate_random_ibss(u8 *pibss);
-+struct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr);
-+struct wlan_network *rtw_find_network(_queue *scanned_queue, const u8 *addr);
-+extern struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue);
-+struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network);
-+struct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network);
-+
-+extern void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue);
-+extern void rtw_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated);
-+extern void rtw_indicate_connect(_adapter *adapter);
-+void rtw_indicate_scan_done(_adapter *padapter, bool aborted);
-+
-+void rtw_drv_scan_by_self(_adapter *padapter, u8 reason);
-+void rtw_scan_wait_completed(_adapter *adapter);
-+u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms);
-+void rtw_scan_abort_no_wait(_adapter *adapter);
-+void rtw_scan_abort(_adapter *adapter);
-+u32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms);
-+
-+int rtw_cached_pmkid(_adapter *Adapter, u8 *bssid);
-+int rtw_rsn_sync_pmkid(_adapter *adapter, u8 *ie, uint ie_len, int i_ent);
-+
-+extern int rtw_restruct_sec_ie(_adapter *adapter, u8 *out_ie);
-+#ifdef CONFIG_WMMPS_STA
-+void rtw_uapsd_use_default_setting(_adapter *padapter);
-+bool rtw_is_wmmps_mode(_adapter *padapter);
-+#endif /* CONFIG_WMMPS_STA */
-+extern int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len);
-+extern void rtw_init_registrypriv_dev_network(_adapter *adapter);
-+
-+extern void rtw_update_registrypriv_dev_network(_adapter *adapter);
-+
-+extern void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter);
-+
-+extern void rtw_join_timeout_handler(void *ctx);
-+extern void rtw_scan_timeout_handler(void *ctx);
-+
-+extern void rtw_dynamic_check_timer_handlder(void *ctx);
-+extern void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter);
-+
-+enum {
-+	SS_DENY_MP_MODE,
-+	SS_DENY_RSON_SCANING,
-+	SS_DENY_BLOCK_SCAN,
-+	SS_DENY_BY_DRV,
-+	SS_DENY_SELF_AP_UNDER_WPS,
-+	SS_DENY_SELF_AP_UNDER_LINKING,
-+	SS_DENY_SELF_AP_UNDER_SURVEY,
-+	/*SS_DENY_SELF_STA_UNDER_WPS,*/
-+	SS_DENY_SELF_STA_UNDER_LINKING,
-+	SS_DENY_SELF_STA_UNDER_SURVEY,
-+	SS_DENY_BUDDY_UNDER_LINK_WPS,
-+	SS_DENY_BUDDY_UNDER_SURVEY,
-+	SS_DENY_BUSY_TRAFFIC,
-+	SS_ALLOW,
-+#ifdef DBG_LA_MODE
-+	SS_DENY_LA_MODE,
-+#endif
-+	SS_DENY_ADAPTIVITY,
-+};
-+
-+u8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval);
-+#define rtw_sitesurvey_condition_check(adapter, check_sc_interval) _rtw_sitesurvey_condition_check(__func__, adapter, check_sc_interval)
-+
-+#ifdef CONFIG_SET_SCAN_DENY_TIMER
-+bool rtw_is_scan_deny(_adapter *adapter);
-+void rtw_clear_scan_deny(_adapter *adapter);
-+void rtw_set_scan_deny_timer_hdl(void *ctx);
-+void rtw_set_scan_deny(_adapter *adapter, u32 ms);
-+#else
-+#define rtw_is_scan_deny(adapter) _FALSE
-+#define rtw_clear_scan_deny(adapter) do {} while (0)
-+#define rtw_set_scan_deny(adapter, ms) do {} while (0)
-+#endif
-+
-+void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv);
-+
-+#define MLME_BEACON_IE			0
-+#define MLME_PROBE_REQ_IE		1
-+#define MLME_PROBE_RESP_IE		2
-+#define MLME_GO_PROBE_RESP_IE	3
-+#define MLME_ASSOC_REQ_IE		4
-+#define MLME_ASSOC_RESP_IE		5
-+
-+#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
-+int rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_len);
-+#endif
-+
-+
-+/* extern struct wlan_network* _rtw_dequeue_network(_queue *queue); */
-+
-+extern struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv);
-+
-+
-+extern void _rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 isfreeall);
-+extern void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork);
-+
-+extern void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall);
-+
-+extern sint rtw_if_up(_adapter *padapter);
-+
-+sint rtw_linked_check(_adapter *padapter);
-+
-+u8 *rtw_get_capability_from_ie(u8 *ie);
-+u8 *rtw_get_timestampe_from_ie(u8 *ie);
-+u8 *rtw_get_beacon_interval_from_ie(u8 *ie);
-+
-+
-+void rtw_joinbss_reset(_adapter *padapter);
-+
-+#ifdef CONFIG_80211N_HT
-+void	rtw_ht_use_default_setting(_adapter *padapter);
-+void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len);
-+unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel);
-+void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel);
-+void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe, u8 issue_when_busy);
-+void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len);
-+#endif
-+
-+int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork);
-+int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature);
-+
-+#ifdef CONFIG_LAYER2_ROAMING
-+#define rtw_roam_flags(adapter) ((adapter)->mlmepriv.roam_flags)
-+#define rtw_chk_roam_flags(adapter, flags) ((adapter)->mlmepriv.roam_flags & flags)
-+#define rtw_clr_roam_flags(adapter, flags) \
-+	do { \
-+		((adapter)->mlmepriv.roam_flags &= ~flags); \
-+	} while (0)
-+
-+#define rtw_set_roam_flags(adapter, flags) \
-+	do { \
-+		((adapter)->mlmepriv.roam_flags |= flags); \
-+	} while (0)
-+
-+#define rtw_assign_roam_flags(adapter, flags) \
-+	do { \
-+		((adapter)->mlmepriv.roam_flags = flags); \
-+	} while (0)
-+
-+void _rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network);
-+void rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network);
-+void rtw_set_to_roam(_adapter *adapter, u8 to_roam);
-+u8 rtw_dec_to_roam(_adapter *adapter);
-+u8 rtw_to_roam(_adapter *adapter);
-+int rtw_select_roaming_candidate(struct mlme_priv *pmlmepriv);
-+#else
-+#define rtw_roam_flags(adapter) 0
-+#define rtw_chk_roam_flags(adapter, flags) 0
-+#define rtw_clr_roam_flags(adapter, flags) do {} while (0)
-+#define rtw_set_roam_flags(adapter, flags) do {} while (0)
-+#define rtw_assign_roam_flags(adapter, flags) do {} while (0)
-+#define _rtw_roaming(adapter, tgt_network) do {} while (0)
-+#define rtw_roaming(adapter, tgt_network) do {} while (0)
-+#define rtw_set_to_roam(adapter, to_roam) do {} while (0)
-+#define rtw_dec_to_roam(adapter) 0
-+#define rtw_to_roam(adapter) 0
-+#define rtw_select_roaming_candidate(mlme) _FAIL
-+#endif /* CONFIG_LAYER2_ROAMING */
-+
-+bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset);
-+
-+struct sta_media_status_rpt_cmd_parm {
-+	struct sta_info *sta;
-+	bool connected;
-+};
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+void rtw_unassoc_sta_set_mode(_adapter *adapter, u8 stype, u8 mode);
-+bool rtw_unassoc_sta_src_chk(_adapter *adapter, u8 stype);
-+void dump_unassoc_sta(void *sel, _adapter *adapter);
-+void rtw_del_unassoc_sta_queue(_adapter *adapter);
-+void rtw_del_unassoc_sta(_adapter *adapter, u8 *addr);
-+void rtw_rx_add_unassoc_sta(_adapter *adapter, u8 stype, u8 *addr, s8 recv_signal_power);
-+void rtw_add_interested_unassoc_sta(_adapter *adapter, u8 *addr);
-+void rtw_undo_interested_unassoc_sta(_adapter *adapter, u8 *addr);
-+void rtw_undo_all_interested_unassoc_sta(_adapter *adapter);
-+u8 rtw_search_unassoc_sta(_adapter *adapter, u8 *addr, struct unassoc_sta_info *ret_sta);
-+#endif
-+
-+void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected);
-+u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected);
-+void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm);
-+void rtw_sta_traffic_info(void *sel, _adapter *adapter);
-+
-+#define GET_ARP_HTYPE(_arp)	BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 0, 0, 16)
-+#define GET_ARP_PTYPE(_arp)	BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 2, 0, 16)
-+#define GET_ARP_HLEN(_arp)	BE_BITS_TO_1BYTE(((u8 *)(_arp)) + 4, 0, 8)
-+#define GET_ARP_PLEN(_arp)	BE_BITS_TO_1BYTE(((u8 *)(_arp)) + 5, 0, 8)
-+#define GET_ARP_OPER(_arp)	BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 6, 0, 16)
-+
-+#define SET_ARP_HTYPE(_arp, _val)	SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 0, 0, 16, _val)
-+#define SET_ARP_PTYPE(_arp, _val)	SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 2, 0, 16, _val)
-+#define SET_ARP_HLEN(_arp, _val)	SET_BITS_TO_BE_1BYTE(((u8 *)(_arp)) + 4, 0, 8, _val)
-+#define SET_ARP_PLEN(_arp, _val)	SET_BITS_TO_BE_1BYTE(((u8 *)(_arp)) + 5, 0, 8, _val)
-+#define SET_ARP_OPER(_arp, _val)	SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 6, 0, 16, _val)
-+
-+#define ARP_SHA(_arp, _hlen, _plen)	(((u8 *)(_arp)) + 8)
-+#define ARP_SPA(_arp, _hlen, _plen)	(((u8 *)(_arp)) + 8 + (_hlen))
-+#define ARP_THA(_arp, _hlen, _plen)	(((u8 *)(_arp)) + 8 + (_hlen) + (_plen))
-+#define ARP_TPA(_arp, _hlen, _plen)	(((u8 *)(_arp)) + 8 + 2 * (_hlen) + (_plen))
-+
-+#define ARP_SENDER_MAC_ADDR(_arp)	ARP_SHA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
-+#define ARP_SENDER_IP_ADDR(_arp)	ARP_SPA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
-+#define ARP_TARGET_MAC_ADDR(_arp)	ARP_THA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
-+#define ARP_TARGET_IP_ADDR(_arp)	ARP_TPA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN)
-+
-+#define GET_ARP_SENDER_MAC_ADDR(_arp, _val)	_rtw_memcpy(_val, ARP_SENDER_MAC_ADDR(_arp), ETH_ALEN)
-+#define GET_ARP_SENDER_IP_ADDR(_arp, _val)	_rtw_memcpy(_val, ARP_SENDER_IP_ADDR(_arp), RTW_IP_ADDR_LEN)
-+#define GET_ARP_TARGET_MAC_ADDR(_arp, _val)	_rtw_memcpy(_val, ARP_TARGET_MAC_ADDR(_arp), ETH_ALEN)
-+#define GET_ARP_TARGET_IP_ADDR(_arp, _val)	_rtw_memcpy(_val, ARP_TARGET_IP_ADDR(_arp), RTW_IP_ADDR_LEN)
-+
-+#define SET_ARP_SENDER_MAC_ADDR(_arp, _val)	_rtw_memcpy(ARP_SENDER_MAC_ADDR(_arp), _val, ETH_ALEN)
-+#define SET_ARP_SENDER_IP_ADDR(_arp, _val)	_rtw_memcpy(ARP_SENDER_IP_ADDR(_arp), _val, RTW_IP_ADDR_LEN)
-+#define SET_ARP_TARGET_MAC_ADDR(_arp, _val)	_rtw_memcpy(ARP_TARGET_MAC_ADDR(_arp), _val, ETH_ALEN)
-+#define SET_ARP_TARGET_IP_ADDR(_arp, _val)	_rtw_memcpy(ARP_TARGET_IP_ADDR(_arp), _val, RTW_IP_ADDR_LEN)
-+
-+void dump_arp_pkt(void *sel, u8 *da, u8 *sa, u8 *arp, bool tx);
-+
-+#define IPV4_SRC(_iphdr)			(((u8 *)(_iphdr)) + 12)
-+#define IPV4_DST(_iphdr)			(((u8 *)(_iphdr)) + 16)
-+#define GET_IPV4_IHL(_iphdr)		BE_BITS_TO_1BYTE(((u8 *)(_iphdr)) + 0, 0, 4)
-+#define GET_IPV4_PROTOCOL(_iphdr)	BE_BITS_TO_1BYTE(((u8 *)(_iphdr)) + 9, 0, 8)
-+#define GET_IPV4_SRC(_iphdr)		BE_BITS_TO_4BYTE(((u8 *)(_iphdr)) + 12, 0, 32)
-+#define GET_IPV4_DST(_iphdr)		BE_BITS_TO_4BYTE(((u8 *)(_iphdr)) + 16, 0, 32)
-+
-+#define GET_UDP_SRC(_udphdr)			BE_BITS_TO_2BYTE(((u8 *)(_udphdr)) + 0, 0, 16)
-+#define GET_UDP_DST(_udphdr)			BE_BITS_TO_2BYTE(((u8 *)(_udphdr)) + 2, 0, 16)
-+#define GET_UDP_SIG1(_udphdr)			BE_BITS_TO_1BYTE(((u8 *)(_udphdr)) + 8, 0, 8)
-+#define GET_UDP_SIG2(_udphdr)			BE_BITS_TO_1BYTE(((u8 *)(_udphdr)) + 23, 0, 8)
-+
-+#define TCP_SRC(_tcphdr)				(((u8 *)(_tcphdr)) + 0)
-+#define TCP_DST(_tcphdr)				(((u8 *)(_tcphdr)) + 2)
-+#define GET_TCP_SRC(_tcphdr)			BE_BITS_TO_2BYTE(((u8 *)(_tcphdr)) + 0, 0, 16)
-+#define GET_TCP_DST(_tcphdr)			BE_BITS_TO_2BYTE(((u8 *)(_tcphdr)) + 2, 0, 16)
-+#define GET_TCP_SEQ(_tcphdr)			BE_BITS_TO_4BYTE(((u8 *)(_tcphdr)) + 4, 0, 32)
-+#define GET_TCP_ACK_SEQ(_tcphdr)		BE_BITS_TO_4BYTE(((u8 *)(_tcphdr)) + 8, 0, 32)
-+#define GET_TCP_DOFF(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 12, 4, 4)
-+#define GET_TCP_FIN(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 0, 1)
-+#define GET_TCP_SYN(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 1, 1)
-+#define GET_TCP_RST(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 2, 1)
-+#define GET_TCP_PSH(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 3, 1)
-+#define GET_TCP_ACK(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 4, 1)
-+#define GET_TCP_URG(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 5, 1)
-+#define GET_TCP_ECE(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 6, 1)
-+#define GET_TCP_CWR(_tcphdr)			BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 7, 1)
-+
-+#endif /* __RTL871X_MLME_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_mlme_ext.h b/drivers/staging/rtl8723cs/include/rtw_mlme_ext.h
-new file mode 100644
-index 000000000000..af05277c64c7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_mlme_ext.h
-@@ -0,0 +1,1239 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_MLME_EXT_H_
-+#define __RTW_MLME_EXT_H_
-+
-+
-+/*	Commented by Albert 20101105
-+ *	Increase the SURVEY_TO value from 100 to 150  ( 100ms to 150ms )
-+ *	The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request.
-+ *	So, this driver tried to extend the dwell time for each scanning channel.
-+ *	This will increase the chance to receive the probe response from SoftAP. */
-+#define SURVEY_TO		(100)
-+
-+#define REAUTH_TO		(300) /* (50) */
-+#define REASSOC_TO		(300) /* (50) */
-+/* #define DISCONNECT_TO	(3000) */
-+#define ADDBA_TO			(2000)
-+
-+#define LINKED_TO (1) /* unit:2 sec, 1x2 = 2 sec */
-+
-+#define REAUTH_LIMIT	(4)
-+#define REASSOC_LIMIT	(4)
-+#define READDBA_LIMIT	(2)
-+
-+#ifdef CONFIG_GSPI_HCI
-+	#define ROAMING_LIMIT	5
-+#else
-+	#define ROAMING_LIMIT	8
-+#endif
-+
-+/*net_type, pmlmeinfo->state*/
-+#define _HW_STATE_NOLINK_	0x00
-+#define _HW_STATE_ADHOC_	0x01
-+#define _HW_STATE_STATION_	0x02
-+#define _HW_STATE_AP_		0x03
-+#define _HW_STATE_MONITOR_	0x04
-+
-+#define	WIFI_FW_NULL_STATE		_HW_STATE_NOLINK_
-+#define	WIFI_FW_STATION_STATE		_HW_STATE_STATION_
-+#define	WIFI_FW_AP_STATE		_HW_STATE_AP_
-+#define	WIFI_FW_ADHOC_STATE		_HW_STATE_ADHOC_
-+
-+#define	WIFI_FW_PRE_LINK		0x00000800
-+#define	WIFI_FW_AUTH_NULL		0x00000100
-+#define	WIFI_FW_AUTH_STATE		0x00000200
-+#define	WIFI_FW_AUTH_SUCCESS		0x00000400
-+
-+#define	WIFI_FW_ASSOC_STATE		0x00002000
-+#define	WIFI_FW_ASSOC_SUCCESS		0x00004000
-+
-+#define	WIFI_FW_LINKING_STATE		(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE | WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)
-+
-+
-+#define		_1M_RATE_	0
-+#define		_2M_RATE_	1
-+#define		_5M_RATE_	2
-+#define		_11M_RATE_	3
-+#define		_6M_RATE_	4
-+#define		_9M_RATE_	5
-+#define		_12M_RATE_	6
-+#define		_18M_RATE_	7
-+#define		_24M_RATE_	8
-+#define		_36M_RATE_	9
-+#define		_48M_RATE_	10
-+#define		_54M_RATE_	11
-+
-+/********************************************************
-+MCS rate definitions
-+*********************************************************/
-+#define MCS_RATE_1R	(0x000000ff)
-+#define MCS_RATE_2R	(0x0000ffff)
-+#define MCS_RATE_3R	(0x00ffffff)
-+#define MCS_RATE_4R	(0xffffffff)
-+#define MCS_RATE_2R_13TO15_OFF	(0x00001fff)
-+
-+
-+extern unsigned char RTW_WPA_OUI[];
-+extern unsigned char WMM_OUI[];
-+extern unsigned char WPS_OUI[];
-+extern unsigned char WFD_OUI[];
-+extern unsigned char P2P_OUI[];
-+extern unsigned char MULTI_AP_OUI[];
-+
-+extern unsigned char WMM_INFO_OUI[];
-+extern unsigned char WMM_PARA_OUI[];
-+
-+typedef struct _RT_CHANNEL_PLAN {
-+	unsigned char	Channel[MAX_CHANNEL_NUM];
-+	unsigned char	Len;
-+} RT_CHANNEL_PLAN, *PRT_CHANNEL_PLAN;
-+
-+typedef enum _HT_IOT_PEER {
-+	HT_IOT_PEER_UNKNOWN			= 0,
-+	HT_IOT_PEER_REALTEK			= 1,
-+	HT_IOT_PEER_REALTEK_92SE		= 2,
-+	HT_IOT_PEER_BROADCOM		= 3,
-+	HT_IOT_PEER_RALINK			= 4,
-+	HT_IOT_PEER_ATHEROS			= 5,
-+	HT_IOT_PEER_CISCO				= 6,
-+	HT_IOT_PEER_MERU				= 7,
-+	HT_IOT_PEER_MARVELL			= 8,
-+	HT_IOT_PEER_REALTEK_SOFTAP 	= 9,/* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */
-+	HT_IOT_PEER_SELF_SOFTAP 		= 10, /* Self is SoftAP */
-+	HT_IOT_PEER_AIRGO				= 11,
-+	HT_IOT_PEER_INTEL				= 12,
-+	HT_IOT_PEER_RTK_APCLIENT		= 13,
-+	HT_IOT_PEER_REALTEK_81XX		= 14,
-+	HT_IOT_PEER_REALTEK_WOW		= 15,
-+	HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16,
-+	HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17,
-+	HT_IOT_PEER_MAX				= 18
-+} HT_IOT_PEER_E, *PHTIOT_PEER_E;
-+
-+
-+typedef enum _RT_HT_INF0_CAP {
-+	RT_HT_CAP_USE_TURBO_AGGR = 0x01,
-+	RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
-+	RT_HT_CAP_USE_AMPDU = 0x04,
-+	RT_HT_CAP_USE_WOW = 0x8,
-+	RT_HT_CAP_USE_SOFTAP = 0x10,
-+	RT_HT_CAP_USE_92SE = 0x20,
-+	RT_HT_CAP_USE_88C_92C = 0x40,
-+	RT_HT_CAP_USE_AP_CLIENT_MODE = 0x80,	/* AP team request to reserve this bit, by Emily */
-+} RT_HT_INF0_CAPBILITY, *PRT_HT_INF0_CAPBILITY;
-+
-+typedef enum _RT_HT_INF1_CAP {
-+	RT_HT_CAP_USE_VIDEO_CLIENT = 0x01,
-+	RT_HT_CAP_USE_JAGUAR_BCUT = 0x02,
-+	RT_HT_CAP_USE_JAGUAR_CCUT = 0x04,
-+} RT_HT_INF1_CAPBILITY, *PRT_HT_INF1_CAPBILITY;
-+
-+struct mlme_handler {
-+	unsigned int   num;
-+	char *str;
-+	unsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame);
-+};
-+
-+struct action_handler {
-+	unsigned int   num;
-+	char *str;
-+	unsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame);
-+};
-+
-+enum SCAN_STATE {
-+	SCAN_DISABLE = 0,
-+	SCAN_START = 1,
-+	SCAN_PS_ANNC_WAIT = 2,
-+	SCAN_ENTER = 3,
-+	SCAN_PROCESS = 4,
-+
-+	/* backop */
-+	SCAN_BACKING_OP = 5,
-+	SCAN_BACK_OP = 6,
-+	SCAN_LEAVING_OP = 7,
-+	SCAN_LEAVE_OP = 8,
-+
-+	/* SW antenna diversity (before linked) */
-+	SCAN_SW_ANTDIV_BL = 9,
-+
-+	/* legacy p2p */
-+	SCAN_TO_P2P_LISTEN = 10,
-+	SCAN_P2P_LISTEN = 11,
-+
-+	SCAN_COMPLETE = 12,
-+	SCAN_STATE_MAX,
-+};
-+
-+const char *scan_state_str(u8 state);
-+
-+enum ss_backop_flag {
-+	SS_BACKOP_EN = BIT0, /* backop when linked */
-+	SS_BACKOP_EN_NL = BIT1, /* backop even when no linked */
-+
-+	SS_BACKOP_PS_ANNC = BIT4,
-+	SS_BACKOP_TX_RESUME = BIT5,
-+};
-+
-+struct ss_res {
-+	u8 state;
-+	u8 next_state; /* will set to state on next cmd hdl */
-+	int	bss_cnt;
-+	u8 activate_ch_cnt;
-+	int	channel_idx;
-+	u8 force_ssid_scan;
-+	int	scan_mode;
-+	u16 scan_ch_ms;
-+	u32 scan_timeout_ms;
-+	u8 rx_ampdu_accept;
-+	u8 rx_ampdu_size;
-+	u8 igi_scan;
-+	u8 igi_before_scan; /* used for restoring IGI value without enable DIG & FA_CNT */
-+#ifdef CONFIG_SCAN_BACKOP
-+	u8 backop_flags_sta; /* policy for station mode*/
-+	#ifdef CONFIG_AP_MODE
-+	u8 backop_flags_ap; /* policy for ap mode */
-+	#endif
-+	#ifdef CONFIG_RTW_MESH
-+	u8 backop_flags_mesh; /* policy for mesh mode */
-+	#endif
-+	u8 backop_flags; /* per backop runtime decision */
-+	u8 scan_cnt;
-+	u8 scan_cnt_max;
-+	systime backop_time; /* the start time of backop */
-+	u16 backop_ms;
-+#endif
-+#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
-+	u8 is_sw_antdiv_bl_scan;
-+#endif
-+	u8 ssid_num;
-+	u8 ch_num;
-+	NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT];
-+	struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT];
-+
-+	u32 token; 	/* 0: use to identify caller */
-+	u16 duration;	/* 0: use default */
-+	u8 igi;		/* 0: use defalut */
-+	u8 bw;		/* 0: use default */
-+
-+	bool acs; /* aim to trigger channel selection when scan done */
-+};
-+
-+#ifdef CONFIG_TDLS
-+enum TDLS_option {
-+	TDLS_ESTABLISHED = 1,
-+	TDLS_ISSUE_PTI,
-+	TDLS_CH_SW_RESP,
-+	TDLS_CH_SW_PREPARE,
-+	TDLS_CH_SW_START,
-+	TDLS_CH_SW_TO_OFF_CHNL,
-+	TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED,
-+	TDLS_CH_SW_TO_BASE_CHNL,
-+	TDLS_CH_SW_END_TO_BASE_CHNL,
-+	TDLS_CH_SW_END,
-+	TDLS_RS_RCR,
-+	TDLS_TEARDOWN_STA,
-+	TDLS_TEARDOWN_STA_NO_WAIT,
-+	TDLS_TEARDOWN_STA_LOCALLY,
-+	TDLS_TEARDOWN_STA_LOCALLY_POST,
-+	maxTDLS,
-+};
-+
-+#endif /* CONFIG_TDLS */
-+
-+/*
-+ * Usage:
-+ * When one iface acted as AP mode and the other iface is STA mode and scanning,
-+ * it should switch back to AP's operating channel periodically.
-+ * Parameters info:
-+ * When the driver scanned RTW_SCAN_NUM_OF_CH channels, it would switch back to AP's operating channel for
-+ * RTW_BACK_OP_CH_MS milliseconds.
-+ * Example:
-+ * For chip supports 2.4G + 5GHz and AP mode is operating in channel 1,
-+ * RTW_SCAN_NUM_OF_CH is 8, RTW_BACK_OP_CH_MS is 300
-+ * When it's STA mode gets set_scan command,
-+ * it would
-+ * 1. Doing the scan on channel 1.2.3.4.5.6.7.8
-+ * 2. Back to channel 1 for 300 milliseconds
-+ * 3. Go through doing site survey on channel 9.10.11.36.40.44.48.52
-+ * 4. Back to channel 1 for 300 milliseconds
-+ * 5. ... and so on, till survey done.
-+ */
-+#if defined(CONFIG_ATMEL_RC_PATCH)
-+	#define RTW_SCAN_NUM_OF_CH 2
-+	#define RTW_BACK_OP_CH_MS 200
-+#elseif defined(CONFIG_CUSTOMER_EZVIZ_CHIME2)
-+	#define RTW_SCAN_NUM_OF_CH 1
-+	#define RTW_BACK_OP_CH_MS 200
-+#else
-+	#define RTW_SCAN_NUM_OF_CH 3
-+	#define RTW_BACK_OP_CH_MS 400
-+#endif
-+
-+#define RTW_IP_ADDR_LEN 4
-+#define RTW_IPv6_ADDR_LEN 16
-+
-+struct mlme_ext_info {
-+	u32	state;
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+	u8	hw_media_state;
-+#endif
-+	u32	reauth_count;
-+	u32	reassoc_count;
-+	u32	link_count;
-+	u32	auth_seq;
-+	u32	auth_algo;	/* 802.11 auth, could be open, shared, auto */
-+	u16 auth_status;
-+	u32	authModeToggle;
-+	u32	enc_algo;/* encrypt algorithm; */
-+	u32	key_index;	/* this is only valid for legendary wep, 0~3 for key id. */
-+	u32	iv;
-+	u8	chg_txt[128];
-+	u16	aid;
-+	u16	bcn_interval;
-+	u16	capability;
-+	u8	assoc_AP_vendor;
-+	u8	slotTime;
-+	u8	preamble_mode;
-+	u8	WMM_enable;
-+	u8	ERP_enable;
-+	u8	ERP_IE;
-+	u8	HT_enable;
-+	u8	HT_caps_enable;
-+	u8	HT_info_enable;
-+	u8	HT_protection;
-+	u8	turboMode_cts2self;
-+	u8	turboMode_rtsen;
-+	u8	SM_PS;
-+	u8	agg_enable_bitmap;
-+	u8	ADDBA_retry_count;
-+	u8	candidate_tid_bitmap;
-+	u8	dialogToken;
-+	/* Accept ADDBA Request */
-+	BOOLEAN bAcceptAddbaReq;
-+	u8	bwmode_updated;
-+	u8	hidden_ssid_mode;
-+	u8	VHT_enable;
-+
-+	u8 ip_addr[RTW_IP_ADDR_LEN];
-+	u8 ip6_addr[RTW_IPv6_ADDR_LEN];
-+
-+	struct ADDBA_request		ADDBA_req;
-+	struct WMM_para_element	WMM_param;
-+	struct HT_caps_element	HT_caps;
-+	struct HT_info_element		HT_info;
-+	WLAN_BSSID_EX			network;/* join network or bss_network, if in ap mode, it is the same to cur_network.network */
-+#ifdef ROKU_PRIVATE
-+	/*infra mode, store supported rates from AssocRsp*/
-+	NDIS_802_11_RATES_EX	SupportedRates_infra_ap;
-+	u8 ht_vht_received;/*ht_vht_received used to show debug msg BIT(0):HT BIT(1):VHT */
-+#endif /* ROKU_PRIVATE */
-+};
-+
-+enum {
-+	RTW_CHF_NO_IR = BIT0,
-+	RTW_CHF_DFS = BIT1,
-+	RTW_CHF_LONG_CAC = BIT2,
-+	RTW_CHF_NON_OCP = BIT3,
-+	RTW_CHF_NO_HT40U = BIT4,
-+	RTW_CHF_NO_HT40L = BIT5,
-+	RTW_CHF_NO_80MHZ = BIT6,
-+	RTW_CHF_NO_160MHZ = BIT7,
-+};
-+
-+/* The channel information about this channel including joining, scanning, and power constraints. */
-+typedef struct _RT_CHANNEL_INFO {
-+	u8				ChannelNum;		/* The channel number. */
-+
-+	/*
-+	* Bitmap and its usage:
-+	* RTW_CHF_NO_IR, RTW_CHF_DFS: is used to check for status
-+	* RTW_CHF_NO_HT40U, RTW_CHF_NO_HT40L, RTW_CHF_NO_80MHZ, RTW_CHF_NO_160MHZ: extra bandwidth limitation (ex: from regulatory)
-+	* RTW_CHF_NON_OCP: is only used to record if event is reported, status check is still done using non_ocp_end_time
-+	*/
-+	u8 flags;
-+	/* u16				ScanPeriod;		 */ /* Listen time in millisecond in this channel. */
-+	/* s32				MaxTxPwrDbm;	 */ /* Max allowed tx power. */
-+	/* u32				ExInfo;			 */ /* Extended Information for this channel. */
-+#ifdef CONFIG_FIND_BEST_CHANNEL
-+	u32				rx_count;
-+#endif
-+#if CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS
-+	#ifdef CONFIG_DFS_MASTER
-+	systime non_ocp_end_time;
-+	#endif
-+#endif
-+	u8 hidden_bss_cnt; /* per scan count */
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	void *os_chan;
-+#endif
-+} RT_CHANNEL_INFO, *PRT_CHANNEL_INFO;
-+
-+#define CAC_TIME_MS (60*1000)
-+#define CAC_TIME_CE_MS (10*60*1000)
-+#define NON_OCP_TIME_MS (30*60*1000)
-+
-+#if CONFIG_TXPWR_LIMIT
-+void rtw_txpwr_init_regd(struct rf_ctl_t *rfctl);
-+#endif
-+int rtw_rfctl_init(_adapter *adapter);
-+void rtw_rfctl_deinit(_adapter *adapter);
-+void rtw_rfctl_chplan_init(_adapter *adapter);
-+void rtw_rfctl_update_op_mode(struct rf_ctl_t *rfctl, u8 ifbmp_mod, u8 if_op);
-+
-+u8 rtw_rfctl_get_dfs_domain(struct rf_ctl_t *rfctl);
-+u8 rtw_rfctl_dfs_domain_unknown(struct rf_ctl_t *rfctl);
-+
-+#ifdef CONFIG_DFS_MASTER
-+struct rf_ctl_t;
-+#define CH_IS_NON_OCP(rt_ch_info) (rtw_time_after((rt_ch_info)->non_ocp_end_time, rtw_get_current_time()))
-+bool rtw_is_cac_reset_needed(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);
-+bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);
-+bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl);
-+bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl);
-+bool rtw_chset_is_chbw_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset);
-+bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch);
-+bool rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset);
-+bool rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms);
-+void rtw_chset_chk_non_ocp_finish(struct rf_ctl_t *rfctl);
-+u32 rtw_get_ch_waiting_ms(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms);
-+void rtw_reset_cac(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset);
-+u32 rtw_force_stop_cac(struct rf_ctl_t *rfctl, u32 timeout_ms);
-+#else
-+#define CH_IS_NON_OCP(rt_ch_info) 0
-+#define rtw_chset_is_chbw_non_ocp(ch_set, ch, bw, offset) _FALSE
-+#define rtw_chset_is_ch_non_ocp(ch_set, ch) _FALSE
-+#define rtw_rfctl_is_tx_blocked_by_ch_waiting(rfctl) _FALSE
-+#endif
-+
-+bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw
-+	, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset
-+	, u8 e_flags, u8 d_flags, u8 cur_ch, bool by_int_info, u8 mesh_only);
-+
-+struct get_chplan_resp {
-+	enum regd_src_t regd_src;
-+	bool has_country;
-+	struct country_chplan country_ent;
-+	u8 channel_plan;
-+#if CONFIG_TXPWR_LIMIT
-+	const char *regd_name;
-+#endif
-+#ifdef CONFIG_DFS_MASTER
-+	u8 dfs_domain;
-+#endif
-+	u8 chset_num;
-+	RT_CHANNEL_INFO chset[0];
-+};
-+
-+#ifdef CONFIG_PROC_DEBUG
-+void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set, u8 chset_num);
-+void dump_cur_chset(void *sel, struct rf_ctl_t *rfctl);
-+#endif
-+
-+int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch);
-+u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset
-+	, bool allow_primary_passive, bool allow_passive);
-+void rtw_chset_sync_chbw(RT_CHANNEL_INFO *ch_set, u8 *req_ch, u8 *req_bw, u8 *req_offset
-+	, u8 *g_ch, u8 *g_bw, u8 *g_offset, bool allow_primary_passive, bool allow_passive);
-+
-+bool rtw_mlme_band_check(_adapter *adapter, const u32 ch);
-+
-+
-+enum {
-+	BAND_24G = BIT0,
-+	BAND_5G = BIT1,
-+};
-+void RTW_SET_SCAN_BAND_SKIP(_adapter *padapter, int skip_band);
-+void RTW_CLR_SCAN_BAND_SKIP(_adapter *padapter, int skip_band);
-+int RTW_GET_SCAN_BAND_SKIP(_adapter *padapter);
-+
-+bool rtw_mlme_ignore_chan(_adapter *adapter, const u32 ch);
-+
-+/* P2P_MAX_REG_CLASSES - Maximum number of regulatory classes */
-+#define P2P_MAX_REG_CLASSES 10
-+
-+/* P2P_MAX_REG_CLASS_CHANNELS - Maximum number of channels per regulatory class */
-+#define P2P_MAX_REG_CLASS_CHANNELS 20
-+
-+/* struct p2p_channels - List of supported channels */
-+struct p2p_channels {
-+	/* struct p2p_reg_class - Supported regulatory class */
-+	struct p2p_reg_class {
-+		/* reg_class - Regulatory class (IEEE 802.11-2007, Annex J) */
-+		u8 reg_class;
-+
-+		/* channel - Supported channels */
-+		u8 channel[P2P_MAX_REG_CLASS_CHANNELS];
-+
-+		/* channels - Number of channel entries in use */
-+		size_t channels;
-+	} reg_class[P2P_MAX_REG_CLASSES];
-+
-+	/* reg_classes - Number of reg_class entries in use */
-+	size_t reg_classes;
-+};
-+
-+struct p2p_oper_class_map {
-+	enum hw_mode {IEEE80211G, IEEE80211A} mode;
-+	u8 op_class;
-+	u8 min_chan;
-+	u8 max_chan;
-+	u8 inc;
-+	enum { BW20, BW40PLUS, BW40MINUS } bw;
-+};
-+
-+struct mlme_ext_priv {
-+	_adapter	*padapter;
-+	u8	mlmeext_init;
-+	ATOMIC_T		event_seq;
-+	u16	mgnt_seq;
-+#ifdef CONFIG_IEEE80211W
-+	u16	sa_query_seq;
-+#endif
-+	/* struct fw_priv 	fwpriv; */
-+
-+	unsigned char	cur_channel;
-+	unsigned char	cur_bwmode;
-+	unsigned char	cur_ch_offset;/* PRIME_CHNL_OFFSET */
-+	unsigned char	cur_wireless_mode;	/* NETWORK_TYPE */
-+
-+	unsigned char	basicrate[NumRates];
-+	unsigned char	datarate[NumRates];
-+#ifdef CONFIG_80211N_HT
-+	unsigned char default_supported_mcs_set[16];
-+#endif
-+
-+	struct ss_res		sitesurvey_res;
-+	struct mlme_ext_info	mlmext_info;/* for sta/adhoc mode, including current scanning/connecting/connected related info.
-+                                                      * for ap mode, network includes ap's cap_info */
-+	_timer		survey_timer;
-+	_timer		link_timer;
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	_timer		rson_scan_timer;
-+#endif
-+#ifdef CONFIG_RTW_80211R
-+	_timer		ft_link_timer;
-+	_timer		ft_roam_timer;
-+#endif
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	_timer		tbtx_xmit_timer;
-+	_timer		tbtx_token_dispatch_timer;
-+#endif
-+
-+	systime last_scan_time;
-+	u8	scan_abort;
-+	u8 join_abort;
-+	u8	tx_rate; /* TXRATE when USERATE is set. */
-+
-+	u32	retry; /* retry for issue probereq */
-+
-+	u64 TSFValue;
-+	u32 bcn_cnt;
-+	u32 last_bcn_cnt;
-+	u8 cur_bcn_cnt;/*2s*/
-+	u8 dtim;/*DTIM Period*/
-+#ifdef DBG_RX_BCN
-+	u8 tim[4];
-+#endif
-+#ifdef CONFIG_BCN_RECV_TIME
-+	u16 bcn_rx_time;
-+#endif
-+#ifdef CONFIG_AP_MODE
-+	unsigned char bstart_bss;
-+#endif
-+
-+#ifdef CONFIG_80211D
-+	u8 update_channel_plan_by_ap_done;
-+#endif
-+	/* recv_decache check for Action_public frame */
-+	u8 action_public_dialog_token;
-+	u16	 action_public_rxseq;
-+
-+	/* #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
-+	u8 active_keep_alive_check;
-+	/* #endif */
-+#ifdef DBG_FIXED_CHAN
-+	u8 fixed_chan;
-+#endif
-+
-+	u8 tsf_update_required:1;
-+	u8 en_hw_update_tsf:1; /* set hw sync bcn tsf register or not */
-+	systime tsf_update_pause_stime;
-+	u8 tsf_update_pause_factor; /* num of bcn intervals to stay TSF update pause status */
-+	u8 tsf_update_restore_factor; /* num of bcn interval to stay TSF update restore status */
-+#ifdef CONFIG_SUPPORT_STATIC_SMPS
-+	u8 ssmps_en;
-+	u16 ssmps_tx_tp_th;/*Mbps*/
-+	u16 ssmps_rx_tp_th;/*Mbps*/
-+	#ifdef DBG_STATIC_SMPS
-+	u8 ssmps_test;
-+	u8 ssmps_test_en;
-+	#endif
-+#endif
-+#ifdef CONFIG_CTRL_TXSS_BY_TP
-+	u8 txss_ctrl_en;
-+	u16 txss_tp_th;/*Mbps*/
-+	u8 txss_tp_chk_cnt;/*unit 2s*/
-+	bool txss_1ss;
-+	u8 txss_momi_type_bk;
-+#endif
-+#ifdef CONFIG_DFS
-+	_timer csa_timer;
-+#endif /* CONFIG_DFS */
-+};
-+
-+struct support_rate_handler {
-+	u8 rate;
-+	bool basic;
-+	bool existence;
-+};
-+
-+static inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state)
-+{
-+	if ((plmeext->mlmext_info.state & 0x03) == state)
-+		return _TRUE;
-+
-+	return _FALSE;
-+}
-+
-+void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state);
-+
-+#define mlmeext_msr(mlmeext) ((mlmeext)->mlmext_info.state & 0x03)
-+#define mlmeext_scan_state(mlmeext) ((mlmeext)->sitesurvey_res.state)
-+#define mlmeext_scan_state_str(mlmeext) scan_state_str((mlmeext)->sitesurvey_res.state)
-+#define mlmeext_chk_scan_state(mlmeext, _state) ((mlmeext)->sitesurvey_res.state == (_state))
-+#define mlmeext_set_scan_state(mlmeext, _state) \
-+	do { \
-+		((mlmeext)->sitesurvey_res.state = (_state)); \
-+		((mlmeext)->sitesurvey_res.next_state = (_state)); \
-+		rtw_mi_update_iface_status(&((container_of(mlmeext, _adapter, mlmeextpriv)->mlmepriv)), 0); \
-+		/* RTW_INFO("set_scan_state:%s\n", scan_state_str(_state)); */ \
-+		sitesurvey_set_offch_state(container_of(mlmeext, _adapter, mlmeextpriv), _state); \
-+	} while (0)
-+
-+#define mlmeext_scan_next_state(mlmeext) ((mlmeext)->sitesurvey_res.next_state)
-+#define mlmeext_set_scan_next_state(mlmeext, _state) \
-+	do { \
-+		((mlmeext)->sitesurvey_res.next_state = (_state)); \
-+		/* RTW_INFO("set_scan_next_state:%s\n", scan_state_str(_state)); */ \
-+	} while (0)
-+
-+#ifdef CONFIG_SCAN_BACKOP
-+#define mlmeext_scan_backop_flags(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags)
-+#define mlmeext_chk_scan_backop_flags(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags & (flags))
-+#define mlmeext_assign_scan_backop_flags(mlmeext, flags) \
-+	do { \
-+		((mlmeext)->sitesurvey_res.backop_flags = (flags)); \
-+		RTW_INFO("assign_scan_backop_flags:0x%02x\n", (mlmeext)->sitesurvey_res.backop_flags); \
-+	} while (0)
-+
-+#define mlmeext_scan_backop_flags_sta(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_sta)
-+#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_sta & (flags))
-+#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) \
-+	do { \
-+		((mlmeext)->sitesurvey_res.backop_flags_sta = (flags)); \
-+	} while (0)
-+#else
-+#define mlmeext_scan_backop_flags(mlmeext) (0)
-+#define mlmeext_chk_scan_backop_flags(mlmeext, flags) (0)
-+#define mlmeext_assign_scan_backop_flags(mlmeext, flags) do {} while (0)
-+
-+#define mlmeext_scan_backop_flags_sta(mlmeext) (0)
-+#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) (0)
-+#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) do {} while (0)
-+#endif /* CONFIG_SCAN_BACKOP */
-+
-+#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE)
-+#define mlmeext_scan_backop_flags_ap(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_ap)
-+#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_ap & (flags))
-+#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) \
-+	do { \
-+		((mlmeext)->sitesurvey_res.backop_flags_ap = (flags)); \
-+	} while (0)
-+#else
-+#define mlmeext_scan_backop_flags_ap(mlmeext) (0)
-+#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) (0)
-+#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) do {} while (0)
-+#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE) */
-+
-+#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH)
-+#define mlmeext_scan_backop_flags_mesh(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_mesh)
-+#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_mesh & (flags))
-+#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) \
-+	do { \
-+		((mlmeext)->sitesurvey_res.backop_flags_mesh = (flags)); \
-+	} while (0)
-+#else
-+#define mlmeext_scan_backop_flags_mesh(mlmeext) (0)
-+#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) (0)
-+#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) do {} while (0)
-+#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH) */
-+
-+u32 rtw_scan_timeout_decision(_adapter *padapter);
-+
-+void init_mlme_default_rate_set(_adapter *padapter);
-+int init_mlme_ext_priv(_adapter *padapter);
-+int init_hw_mlme_ext(_adapter *padapter);
-+void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext);
-+extern struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv);
-+struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv);
-+
-+/* void fill_fwpriv(_adapter * padapter, struct fw_priv *pfwpriv); */
-+u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen);
-+void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len);
-+void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask);
-+void UpdateBrateTbl(_adapter *padapter, u8 *mBratesOS);
-+void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen);
-+void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch);
-+
-+void Set_MSR(_adapter *padapter, u8 type);
-+
-+
-+void rtw_set_external_auth_status(_adapter *padapter, const void *data, int len);
-+
-+u8 rtw_get_oper_ch(_adapter *adapter);
-+void rtw_set_oper_ch(_adapter *adapter, u8 ch);
-+u8 rtw_get_oper_bw(_adapter *adapter);
-+void rtw_set_oper_bw(_adapter *adapter, u8 bw);
-+u8 rtw_get_oper_choffset(_adapter *adapter);
-+void rtw_set_oper_choffset(_adapter *adapter, u8 offset);
-+systime rtw_get_on_oper_ch_time(_adapter *adapter);
-+systime rtw_get_on_cur_ch_time(_adapter *adapter);
-+
-+void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode);
-+
-+void csa_timer_hdl(void *FunctionContext);
-+
-+unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval);
-+
-+void _clear_cam_entry(_adapter *padapter, u8 entry);
-+void write_cam_from_cache(_adapter *adapter, u8 id);
-+void rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b);
-+void rtw_clean_dk_section(_adapter *adapter);
-+void rtw_clean_hw_dk_cam(_adapter *adapter);
-+
-+/* modify both HW and cache */
-+void write_cam(_adapter *padapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
-+void clear_cam_entry(_adapter *padapter, u8 id);
-+
-+/* modify cache only */
-+void write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
-+void clear_cam_cache(_adapter *adapter, u8 id);
-+
-+void invalidate_cam_all(_adapter *padapter);
-+
-+void flush_all_cam_entry(_adapter *padapter);
-+
-+BOOLEAN IsLegal5GChannel(PADAPTER Adapter, u8 channel);
-+
-+void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType);
-+u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid);
-+void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, _adapter *padapter, bool update_ie);
-+
-+u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork);
-+u16 get_beacon_interval(WLAN_BSSID_EX *bss);
-+
-+int is_client_associated_to_ap(_adapter *padapter);
-+int is_client_associated_to_ibss(_adapter *padapter);
-+int is_IBSS_empty(_adapter *padapter);
-+
-+unsigned char check_assoc_AP(u8 *pframe, uint len);
-+void get_assoc_AP_Vendor(char *vendor, u8 assoc_AP_vendor);
-+#ifdef CONFIG_RTS_FULL_BW
-+void rtw_parse_sta_vendor_ie_8812(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len);
-+#endif/*CONFIG_RTS_FULL_BW*/
-+#ifdef CONFIG_80211AC_VHT
-+void get_vht_bf_cap(u8 *pframe, uint len, struct vht_bf_cap *bf_cap);
-+#endif
-+
-+int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs	pIE);
-+#ifdef CONFIG_WFD
-+void rtw_process_wfd_ie(_adapter *adapter, u8 *ie, u8 ie_len, const char *tag);
-+void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag);
-+#endif
-+void WMMOnAssocRsp(_adapter *padapter);
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+u8 rtw_is_tbtx_capabilty(u8 *p, u8 len);
-+#endif
-+
-+void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
-+#ifdef ROKU_PRIVATE
-+void HT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
-+#endif
-+void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
-+void HTOnAssocRsp(_adapter *padapter);
-+
-+#ifdef ROKU_PRIVATE
-+void Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
-+void Extended_Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
-+#endif
-+
-+void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
-+void VCS_update(_adapter *padapter, struct sta_info *psta);
-+void	update_ldpc_stbc_cap(struct sta_info *psta);
-+
-+#ifdef CONFIG_CHECK_SPECIFIC_IE_CONTENT
-+bool rtw_validate_value(u16 EID, u8 *p, u16 len);
-+#endif /* CONFIG_CHECK_SPECIFIC_IE_CONTENT */
-+
-+bool is_hidden_ssid(char *ssid, int len);
-+bool hidden_ssid_ap(WLAN_BSSID_EX *snetwork);
-+void rtw_absorb_ssid_ifneed(_adapter *padapter, WLAN_BSSID_EX *bssid, u8 *pframe);
-+
-+int rtw_get_bcn_keys(_adapter *adapter, u8 *whdr, u32 flen, struct beacon_keys *bcn_keys);
-+int rtw_get_bcn_keys_from_bss(WLAN_BSSID_EX *bss, struct beacon_keys *bcn_keys);
-+int rtw_update_bcn_keys_of_network(struct wlan_network *network);
-+
-+int validate_beacon_len(u8 *pframe, uint len);
-+void rtw_dump_bcn_keys(void *sel, struct beacon_keys *recv_beacon);
-+void rtw_bcn_key_err_fix(struct beacon_keys *cur, struct beacon_keys *recv);
-+bool rtw_bcn_key_compare(struct beacon_keys *cur, struct beacon_keys *recv);
-+int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len);
-+void update_beacon_info(_adapter *padapter, u8 *pframe, uint len, struct sta_info *psta);
-+#if CONFIG_DFS
-+void process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len);
-+#endif
-+void update_capinfo(PADAPTER Adapter, u16 updateCap);
-+void update_wireless_mode(_adapter *padapter);
-+void update_tx_basic_rate(_adapter *padapter, u8 modulation);
-+void update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode);
-+int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num);
-+
-+/* for sta/adhoc mode */
-+void update_sta_info(_adapter *padapter, struct sta_info *psta);
-+unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz);
-+unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz);
-+void Update_RA_Entry(_adapter *padapter, struct sta_info *psta);
-+void set_sta_rate(_adapter *padapter, struct sta_info *psta);
-+
-+unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated);
-+
-+unsigned char get_highest_rate_idx(u64 mask);
-+unsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit);
-+#define get_lowest_rate_idx(mask) get_lowest_rate_idx_ex(mask, 0)
-+
-+int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode);
-+unsigned int is_ap_in_tkip(_adapter *padapter);
-+unsigned int is_ap_in_wep(_adapter *padapter);
-+unsigned int should_forbid_n_rate(_adapter *padapter);
-+
-+enum eap_type parsing_eapol_packet(_adapter *padapter, u8 *key_payload, struct sta_info *psta, u8 trx_type);
-+
-+bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap);
-+void _rtw_camctl_set_flags(_adapter *adapter, u32 flags);
-+void rtw_camctl_set_flags(_adapter *adapter, u32 flags);
-+void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags);
-+void rtw_camctl_clr_flags(_adapter *adapter, u32 flags);
-+bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags);
-+
-+struct sec_cam_bmp;
-+void dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num);
-+void rtw_sec_cam_map_set(struct sec_cam_bmp *map, u8 id);
-+void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map);
-+
-+bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id);
-+bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id);
-+s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk);
-+s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool ext_sec, bool *used);
-+void rtw_camid_free(_adapter *adapter, u8 cam_id);
-+u8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id);
-+
-+struct macid_bmp;
-+struct macid_ctl_t;
-+bool _rtw_macid_ctl_chk_cap(_adapter *adapter, u8 cap);
-+void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num);
-+bool rtw_macid_is_set(struct macid_bmp *map, u8 id);
-+void rtw_macid_map_clr(struct macid_bmp *map, u8 id);
-+bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id);
-+bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id);
-+u8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id);
-+bool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id);
-+bool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter);
-+s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id);
-+void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta);
-+void rtw_release_macid(_adapter *padapter, struct sta_info *psta);
-+u8 rtw_search_max_mac_id(_adapter *padapter);
-+u8 rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr);
-+void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw);
-+void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en);
-+void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp);
-+void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp);
-+#ifdef CONFIG_PROTSEL_MACSLEEP
-+void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 reg_ctrl, u16 reg_info);
-+void rtw_macid_ctl_init_drop_reg(struct macid_ctl_t *macid_ctl, u16 reg_ctrl, u16 reg_info);
-+#else
-+void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3);
-+void rtw_macid_ctl_init_drop_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3);
-+#endif
-+void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl);
-+void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl);
-+u8 rtw_iface_bcmc_id_get(_adapter *padapter);
-+void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id);
-+#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE)
-+void rtw_iface_bcmc_sec_cam_map_restore(_adapter *adapter);
-+#endif
-+bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id);
-+void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id);
-+void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id);
-+bool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len);
-+bool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len);
-+
-+#ifdef CONFIG_AP_MODE
-+bool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id);
-+void rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id);
-+void rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id);
-+bool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map);
-+bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map);
-+#endif /* CONFIG_AP_MODE */
-+
-+u32 report_join_res(_adapter *padapter, int aid_res, u16 status);
-+void report_survey_event(_adapter *padapter, union recv_frame *precv_frame);
-+void report_surveydone_event(_adapter *padapter, bool acs);
-+u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated);
-+void report_add_sta_event(_adapter *padapter, unsigned char *MacAddr);
-+bool rtw_port_switch_chk(_adapter *adapter);
-+void report_wmm_edca_update(_adapter *padapter);
-+
-+void beacon_timing_control(_adapter *padapter);
-+u8 chk_bmc_sleepq_cmd(_adapter *padapter);
-+extern u8 set_tx_beacon_cmd(_adapter *padapter, u8 flags);
-+unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame);
-+void update_mgnt_tx_rate(_adapter *padapter, u8 rate);
-+void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+void update_mgntframe_subtype(_adapter *padapter, struct xmit_frame *pmgntframe);
-+#endif
-+void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
-+void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe);
-+void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe);
-+s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms);
-+s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe);
-+s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms);
-+
-+#ifdef CONFIG_P2P
-+int get_reg_classes_full_count(struct p2p_channels *channel_list);
-+void issue_probersp_p2p(_adapter *padapter, unsigned char *da);
-+void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr);
-+void issue_p2p_GO_request(_adapter *padapter, u8 *raddr);
-+void issue_probereq_p2p(_adapter *padapter, u8 *da);
-+int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms);
-+void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 success);
-+void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr);
-+#endif /* CONFIG_P2P */
-+void issue_beacon(_adapter *padapter, int timeout_ms);
-+void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq);
-+void _issue_assocreq(_adapter *padapter, u8 is_assoc);
-+void issue_assocreq(_adapter *padapter);
-+void issue_reassocreq(_adapter *padapter);
-+void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type);
-+void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status);
-+void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da);
-+s32 issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int try_cnt, int wait_ms);
-+int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms);
-+int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms);
-+int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason);
-+int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, int wait_ms);
-+void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset);
-+void issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid);
-+void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size);
-+u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms);
-+void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator);
-+int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator, int try_cnt, int wait_ms);
-+void issue_action_BSSCoexistPacket(_adapter *padapter);
-+
-+#ifdef CONFIG_IEEE80211W
-+void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type);
-+int issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reason, u8 key_type);
-+#endif /* CONFIG_IEEE80211W */
-+int issue_action_SM_PS(_adapter *padapter ,  unsigned char *raddr , u8 NewMimoPsMode);
-+int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms);
-+
-+unsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid, u8 force);
-+unsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid, u8 force);
-+
-+unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr);
-+#ifdef CONFIG_AP_MODE
-+unsigned int send_beacon(_adapter *padapter);
-+#endif
-+void start_clnt_assoc(_adapter *padapter);
-+void start_clnt_auth(_adapter *padapter);
-+void start_clnt_join(_adapter *padapter);
-+void start_create_ibss(_adapter *padapter);
-+
-+unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame);
-+
-+unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame);
-+#ifdef CONFIG_RTW_WNM
-+unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe);
-+#endif
-+
-+#define RX_AMPDU_ACCEPT_INVALID 0xFF
-+#define RX_AMPDU_SIZE_INVALID 0xFF
-+
-+enum rx_ampdu_reason {
-+	RX_AMPDU_DRV_FIXED = 1,
-+	RX_AMPDU_BTCOEX = 2, /* not used, because BTCOEX has its own variable management */
-+	RX_AMPDU_DRV_SCAN = 3,
-+};
-+u8 rtw_rx_ampdu_size(_adapter *adapter);
-+bool rtw_rx_ampdu_is_accept(_adapter *adapter);
-+bool rtw_rx_ampdu_set_size(_adapter *adapter, u8 size, u8 reason);
-+bool rtw_rx_ampdu_set_accept(_adapter *adapter, u8 accept, u8 reason);
-+u8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 accept, u8 size);
-+u8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta);
-+u8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 size);
-+u16 rtw_rx_ampdu_apply(_adapter *adapter);
-+
-+unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame);
-+#ifdef CONFIG_IEEE80211W
-+unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame);
-+#endif /* CONFIG_IEEE80211W */
-+unsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame);
-+unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame);
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+unsigned int OnAction_tbtx_token(_adapter *padapter, union recv_frame *precv_frame);
-+#endif
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+void rtw_issue_action_token_req(_adapter *padapter, struct sta_info *pstat);
-+void rtw_issue_action_token_rel(_adapter *padapter);
-+#endif
-+
-+void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res);
-+void mlmeext_sta_del_event_callback(_adapter *padapter);
-+void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta);
-+
-+int rtw_get_rx_chk_limit(_adapter *adapter);
-+void rtw_set_rx_chk_limit(_adapter *adapter, int limit);
-+void linked_status_chk(_adapter *padapter, u8 from_timer);
-+
-+#define rtw_get_bcn_cnt(adapter)	(adapter->mlmeextpriv.cur_bcn_cnt)
-+#define rtw_get_bcn_dtim_period(adapter)	(adapter->mlmeextpriv.dtim)
-+void rtw_collect_bcn_info(_adapter *adapter);
-+
-+void _linked_info_dump(_adapter *padapter);
-+
-+void survey_timer_hdl(void *ctx);
-+#ifdef CONFIG_RTW_REPEATER_SON
-+void rson_timer_hdl(void *ctx);
-+#endif
-+void link_timer_hdl(void *ctx);
-+void addba_timer_hdl(void *ctx);
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+void rtw_tbtx_xmit_timer_hdl(void *ctx);
-+void rtw_tbtx_token_dispatch_timer_hdl(void *ctx);
-+#endif
-+#ifdef CONFIG_IEEE80211W
-+void sa_query_timer_hdl(void *ctx);
-+#endif /* CONFIG_IEEE80211W */
-+#if 0
-+void reauth_timer_hdl(_adapter *padapter);
-+void reassoc_timer_hdl(_adapter *padapter);
-+#endif
-+
-+#define set_survey_timer(mlmeext, ms) \
-+	do { \
-+		/*RTW_INFO("%s set_survey_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \
-+		_set_timer(&(mlmeext)->survey_timer, (ms)); \
-+	} while (0)
-+
-+#define set_link_timer(mlmeext, ms) \
-+	do { \
-+		/*RTW_INFO("%s set_link_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \
-+		_set_timer(&(mlmeext)->link_timer, (ms)); \
-+	} while (0)
-+
-+bool rtw_is_cck_rate(u8 rate);
-+bool rtw_is_ofdm_rate(u8 rate);
-+bool rtw_is_basic_rate_cck(u8 rate);
-+bool rtw_is_basic_rate_ofdm(u8 rate);
-+bool rtw_is_basic_rate_mix(u8 rate);
-+
-+extern int cckrates_included(unsigned char *rate, int ratelen);
-+extern int cckratesonly_included(unsigned char *rate, int ratelen);
-+
-+extern void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr);
-+
-+extern void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len);
-+extern void correct_TSF(_adapter *padapter, u8 mlme_state);
-+#ifdef CONFIG_BCN_RECV_TIME
-+void rtw_rx_bcn_time_update(_adapter *adapter, uint bcn_len, u8 data_rate);
-+#endif
-+extern u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer);
-+
-+void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame);
-+void rtw_join_done_chk_ch(_adapter *padapter, int join_res);
-+
-+int rtw_chk_start_clnt_join(_adapter *padapter, u8 *ch, u8 *bw, u8 *offset);
-+
-+#ifdef RTW_BUSY_DENY_SCAN
-+#ifndef BUSY_TRAFFIC_SCAN_DENY_PERIOD
-+#ifdef CONFIG_RTW_ANDROID
-+#ifdef CONFIG_PLATFORM_ARM_SUN8I
-+	#define BUSY_TRAFFIC_SCAN_DENY_PERIOD	8000
-+#else
-+	#define BUSY_TRAFFIC_SCAN_DENY_PERIOD	12000
-+#endif
-+#else /* !CONFIG_ANDROID */
-+#define BUSY_TRAFFIC_SCAN_DENY_PERIOD	16000
-+#endif /* !CONFIG_ANDROID */
-+#endif /* !BUSY_TRAFFIC_SCAN_DENY_PERIOD */
-+#endif /* RTW_BUSY_DENY_SCAN */
-+
-+void rtw_leave_opch(_adapter *adapter);
-+void rtw_back_opch(_adapter *adapter);
-+
-+u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf);
-+u8 disconnect_hdl(_adapter *padapter, u8 *pbuf);
-+u8 createbss_hdl(_adapter *padapter, u8 *pbuf);
-+#ifdef CONFIG_AP_MODE
-+u8 stop_ap_hdl(_adapter *adapter);
-+#endif
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+u8 tx_control_hdl(_adapter *adapter);
-+#endif
-+u8 setopmode_hdl(_adapter *padapter, u8 *pbuf);
-+u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf);
-+u8 setauth_hdl(_adapter *padapter, u8 *pbuf);
-+u8 setkey_hdl(_adapter *padapter, u8 *pbuf);
-+u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf);
-+u8 set_assocsta_hdl(_adapter *padapter, u8 *pbuf);
-+u8 del_assocsta_hdl(_adapter *padapter, u8 *pbuf);
-+u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf);
-+u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf);
-+
-+void rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta);
-+
-+u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf);
-+u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf);
-+u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf);
-+u8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf);
-+u8 rtw_iqk_hdl(_adapter *padapter, unsigned char *pbuf);
-+u8 rtw_set_chplan_hdl(_adapter *padapter, unsigned char *pbuf);
-+u8 rtw_get_chplan_hdl(_adapter *padapter, unsigned char *pbuf);
-+u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf);
-+u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf);	/* Kurt: Handling DFS channel switch announcement ie. */
-+u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf);
-+u8 run_in_thread_hdl(_adapter *padapter, u8 *pbuf);
-+
-+int rtw_sae_preprocess(_adapter *adapter, const u8 *buf, u32 len, u8 tx);
-+
-+u32 rtw_desc_rate_to_bitrate(u8 bw, u8 rate_idx, u8 sgi);
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+u8 rtw_get_ch_utilization(_adapter *adapter);
-+void rtw_ch_util_rpt(_adapter *adapter);
-+#endif
-+
-+#define GEN_MLME_EXT_HANDLER(cmd, callback_func)	{.cmd_hdl = cmd, .callback = callback_func},
-+
-+struct rtw_cmd {
-+	u8(*cmd_hdl)(_adapter *padapter, u8 *pbuf);
-+	void (*callback)(_adapter  *padapter, struct cmd_obj *cmd);
-+};
-+
-+#ifdef _RTW_CMD_C_
-+#ifdef CONFIG_RTW_MESH
-+extern u8 rtw_mesh_set_plink_state_cmd_hdl(_adapter *adapter, u8 *parmbuf);
-+#else
-+u8 rtw_mesh_set_plink_state_cmd_hdl(_adapter *adapter, u8 *parmbuf) { return H2C_CMD_FAIL; };
-+#endif
-+
-+struct rtw_cmd wlancmds[] = {
-+	GEN_MLME_EXT_HANDLER(join_cmd_hdl, rtw_joinbss_cmd_callback) /*CMD_JOINBSS*/
-+	GEN_MLME_EXT_HANDLER(disconnect_hdl, rtw_disassoc_cmd_callback) /*CMD_DISCONNECT*/
-+	GEN_MLME_EXT_HANDLER(createbss_hdl, NULL) /*CMD_CREATE_BSS*/
-+	GEN_MLME_EXT_HANDLER(setopmode_hdl, NULL) /*CMD_SET_OPMODE*/
-+	GEN_MLME_EXT_HANDLER(sitesurvey_cmd_hdl, rtw_survey_cmd_callback) /*CMD_SITE_SURVEY*/
-+	GEN_MLME_EXT_HANDLER(setauth_hdl, NULL) /*CMD_SET_AUTH*/
-+	GEN_MLME_EXT_HANDLER(setkey_hdl, NULL) /*CMD_SET_KEY*/
-+	GEN_MLME_EXT_HANDLER(set_stakey_hdl, rtw_setstaKey_cmdrsp_callback) /*CMD_SET_STAKEY*/
-+	GEN_MLME_EXT_HANDLER(add_ba_hdl, NULL) /*CMD_ADD_BAREQ*/
-+	GEN_MLME_EXT_HANDLER(rtw_set_chbw_hdl, NULL) /*CMD_SET_CHANNEL*/
-+	GEN_MLME_EXT_HANDLER(tx_beacon_hdl, NULL) /*CMD_TX_BEACON*/
-+	GEN_MLME_EXT_HANDLER(mlme_evt_hdl, NULL) /*CMD_SET_MLME_EVT*/
-+	GEN_MLME_EXT_HANDLER(rtw_drvextra_cmd_hdl, NULL) /*CMD_SET_DRV_EXTRA*/
-+	GEN_MLME_EXT_HANDLER(rtw_set_chplan_hdl, NULL) /*CMD_SET_CHANPLAN*/
-+	GEN_MLME_EXT_HANDLER(led_blink_hdl, NULL) /*CMD_LEDBLINK*/
-+	GEN_MLME_EXT_HANDLER(set_csa_hdl, NULL) /*CMD_SET_CHANSWITCH*/
-+	GEN_MLME_EXT_HANDLER(tdls_hdl, NULL) /*CMD_TDLS*/
-+	GEN_MLME_EXT_HANDLER(chk_bmc_sleepq_hdl, NULL) /*CMD_CHK_BMCSLEEPQ*/
-+	GEN_MLME_EXT_HANDLER(run_in_thread_hdl, NULL) /*CMD_RUN_INTHREAD*/
-+	GEN_MLME_EXT_HANDLER(add_ba_rsp_hdl, NULL) /*CMD_ADD_BARSP*/
-+	GEN_MLME_EXT_HANDLER(rm_post_event_hdl, NULL) /*CMD_RM_POST_EVENT*/
-+	GEN_MLME_EXT_HANDLER(rtw_mesh_set_plink_state_cmd_hdl, NULL) /*CMD_SET_MESH_PLINK_STATE*/
-+	GEN_MLME_EXT_HANDLER(rtw_iqk_hdl, NULL) /*CMD_DO_IQK*/
-+	GEN_MLME_EXT_HANDLER(rtw_get_chplan_hdl, NULL) /* CMD_GET_CHANPLAN */
-+};
-+#endif
-+
-+struct rtw_evt_header {
-+	u8 id;
-+	u8 seq;
-+	u16 len;
-+};
-+
-+enum rtw_event_id {
-+	EVT_SURVEY, /*0*/
-+	EVT_SURVEY_DONE, /*1*/
-+	EVT_JOINBSS, /*2*/
-+	EVT_ADD_STA, /*3*/
-+	EVT_DEL_STA, /*4*/
-+	EVT_WMM_UPDATE, /*5*/
-+#ifdef CONFIG_IEEE80211W
-+	EVT_TIMEOUT_STA, /*6*/
-+#endif /* CONFIG_IEEE80211W */
-+#ifdef CONFIG_RTW_80211R
-+	EVT_FT_REASSOC, /*7*/
-+#endif
-+	EVT_ID_MAX
-+};
-+#ifdef _RTW_MLME_EXT_C_
-+static struct rtw_event wlanevents[] = {
-+	{sizeof(struct survey_event), &rtw_survey_event_callback}, /*EVT_SURVEY*/
-+	{sizeof(struct surveydone_event), &rtw_surveydone_event_callback}, /*EVT_SURVEY_DONE*/
-+	{sizeof(struct joinbss_event), &rtw_joinbss_event_callback}, /*EVT_JOINBSS*/
-+	{sizeof(struct stassoc_event), &rtw_stassoc_event_callback}, /*EVT_ADD_STA*/
-+	{sizeof(struct stadel_event), &rtw_stadel_event_callback}, /*EVT_DEL_STA*/
-+	{sizeof(struct wmm_event), &rtw_wmm_event_callback}, /*EVT_WMM_UPDATE*/
-+	#ifdef CONFIG_IEEE80211W
-+	{sizeof(struct stadel_event), &rtw_sta_timeout_event_callback}, /*EVT_TIMEOUT_STA*/
-+	#endif /* CONFIG_IEEE80211W */
-+	#ifdef CONFIG_RTW_80211R
-+	{sizeof(struct stassoc_event), &rtw_ft_reassoc_event_callback}, /*EVT_FT_REASSOC*/
-+	#endif
-+};
-+#endif/* _RTW_MLME_EXT_C_ */
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtw_mp.h b/drivers/staging/rtl8723cs/include/rtw_mp.h
-new file mode 100644
-index 000000000000..c2a6ca4c16e7
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_mp.h
-@@ -0,0 +1,943 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTW_MP_H_
-+#define _RTW_MP_H_
-+
-+#define RTWPRIV_VER_INFO	1
-+
-+#define MAX_MP_XMITBUF_SZ	2048
-+#define NR_MP_XMITFRAME		8
-+#define MP_READ_REG_MAX_OFFSET 0x4FFF
-+
-+struct mp_xmit_frame {
-+	_list	list;
-+
-+	struct pkt_attrib attrib;
-+
-+	_pkt *pkt;
-+
-+	int frame_tag;
-+
-+	_adapter *padapter;
-+
-+#ifdef CONFIG_USB_HCI
-+
-+	/* insert urb, irp, and irpcnt info below... */
-+	/* max frag_cnt = 8 */
-+	u8 *mem_addr;
-+	u32 sz[8];
-+	u8 bpending[8];
-+	sint ac_tag[8];
-+	sint last[8];
-+	uint irpcnt;
-+	uint fragcnt;
-+#endif /* CONFIG_USB_HCI */
-+
-+	uint mem[(MAX_MP_XMITBUF_SZ >> 2)];
-+};
-+
-+struct mp_wiparam {
-+	u32 bcompleted;
-+	u32 act_type;
-+	u32 io_offset;
-+	u32 io_value;
-+};
-+
-+typedef void(*wi_act_func)(void *padapter);
-+
-+struct mp_tx {
-+	u8 stop;
-+	u32 count, sended;
-+	u8 payload;
-+	struct pkt_attrib attrib;
-+	/* struct tx_desc desc; */
-+	/* u8 resvdtx[7]; */
-+	u8 desc[TXDESC_SIZE];
-+	u8 *pallocated_buf;
-+	u8 *buf;
-+	u32 buf_size, write_size;
-+	_thread_hdl_ PktTxThread;
-+};
-+
-+#define MP_MAX_LINES		1000
-+#define MP_MAX_LINES_BYTES	256
-+
-+
-+typedef struct _RT_PMAC_PKT_INFO {
-+	u8			MCS;
-+	u8			Nss;
-+	u8			Nsts;
-+	u32			N_sym;
-+	u8			SIGA2B3;
-+} RT_PMAC_PKT_INFO, *PRT_PMAC_PKT_INFO;
-+
-+typedef struct _RT_PMAC_TX_INFO {
-+	u8			bEnPMacTx:1;		/* 0: Disable PMac 1: Enable PMac */
-+	u8			Mode:3;				/* 0: Packet TX 3:Continuous TX */
-+	u8			Ntx:4;				/* 0-7 */
-+	u8			TX_RATE;			/* MPT_RATE_E */
-+	u8			TX_RATE_HEX;
-+	u8			TX_SC;
-+	u8			bSGI:1;
-+	u8			bSPreamble:1;
-+	u8			bSTBC:1;
-+	u8			bLDPC:1;
-+	u8			NDP_sound:1;
-+	u8			BandWidth:3;		/* 0: 20 1:40 2:80Mhz */
-+	u8			m_STBC;			/* bSTBC + 1 */
-+	u16			PacketPeriod;
-+	u32		PacketCount;
-+	u32		PacketLength;
-+	u8			PacketPattern;
-+	u16			SFD;
-+	u8			SignalField;
-+	u8			ServiceField;
-+	u16			LENGTH;
-+	u8			CRC16[2];
-+	u8			LSIG[3];
-+	u8			HT_SIG[6];
-+	u8			VHT_SIG_A[6];
-+	u8			VHT_SIG_B[4];
-+	u8			VHT_SIG_B_CRC;
-+	u8			VHT_Delimiter[4];
-+	u8			MacAddress[6];
-+} RT_PMAC_TX_INFO, *PRT_PMAC_TX_INFO;
-+
-+
-+typedef void (*MPT_WORK_ITEM_HANDLER)(void *Adapter);
-+typedef struct _MPT_CONTEXT {
-+	/* Indicate if we have started Mass Production Test. */
-+	BOOLEAN			bMassProdTest;
-+
-+	/* Indicate if the driver is unloading or unloaded. */
-+	BOOLEAN			bMptDrvUnload;
-+
-+	_sema			MPh2c_Sema;
-+	_timer			MPh2c_timeout_timer;
-+	/* Event used to sync H2c for BT control */
-+
-+	BOOLEAN		MptH2cRspEvent;
-+	BOOLEAN		MptBtC2hEvent;
-+	BOOLEAN		bMPh2c_timeout;
-+
-+	/* 8190 PCI does not support NDIS_WORK_ITEM. */
-+	/* Work Item for Mass Production Test. */
-+	/* NDIS_WORK_ITEM	MptWorkItem;
-+	*	RT_WORK_ITEM		MptWorkItem; */
-+	/* Event used to sync the case unloading driver and MptWorkItem is still in progress.
-+	*	NDIS_EVENT		MptWorkItemEvent; */
-+	/* To protect the following variables.
-+	*	NDIS_SPIN_LOCK		MptWorkItemSpinLock; */
-+	/* Indicate a MptWorkItem is scheduled and not yet finished. */
-+	BOOLEAN			bMptWorkItemInProgress;
-+	/* An instance which implements function and context of MptWorkItem. */
-+	MPT_WORK_ITEM_HANDLER	CurrMptAct;
-+
-+	/* 1=Start, 0=Stop from UI. */
-+	u32			MptTestStart;
-+	/* _TEST_MODE, defined in MPT_Req2.h */
-+	u32			MptTestItem;
-+	/* Variable needed in each implementation of CurrMptAct. */
-+	u32			MptActType;	/* Type of action performed in CurrMptAct. */
-+	/* The Offset of IO operation is depend of MptActType. */
-+	u32			MptIoOffset;
-+	/* The Value of IO operation is depend of MptActType. */
-+	u32			MptIoValue;
-+	/* The RfPath of IO operation is depend of MptActType. */
-+
-+	u32			mpt_rf_path;
-+
-+
-+	WIRELESS_MODE		MptWirelessModeToSw;	/* Wireless mode to switch. */
-+	u8			MptChannelToSw;	/* Channel to switch. */
-+	u8			MptInitGainToSet;	/* Initial gain to set. */
-+	/* u32			bMptAntennaA;		 */ /* TRUE if we want to use antenna A. */
-+	u32			MptBandWidth;		/* bandwidth to switch. */
-+
-+	u32			mpt_rate_index;/* rate index. */
-+
-+	/* Register value kept for Single Carrier Tx test. */
-+	u8			btMpCckTxPower;
-+	/* Register value kept for Single Carrier Tx test. */
-+	u8			btMpOfdmTxPower;
-+	/* For MP Tx Power index */
-+	u8			TxPwrLevel[4];	/* rf-A, rf-B*/
-+	u32			RegTxPwrLimit;
-+	/* Content of RCR Regsiter for Mass Production Test. */
-+	u32			MptRCR;
-+	/* TRUE if we only receive packets with specific pattern. */
-+	BOOLEAN			bMptFilterPattern;
-+	/* Rx OK count, statistics used in Mass Production Test. */
-+	u32			MptRxOkCnt;
-+	/* Rx CRC32 error count, statistics used in Mass Production Test. */
-+	u32			MptRxCrcErrCnt;
-+
-+	BOOLEAN			bCckContTx;	/* TRUE if we are in CCK Continuous Tx test. */
-+	BOOLEAN			bOfdmContTx;	/* TRUE if we are in OFDM Continuous Tx test. */
-+		/* TRUE if we have start Continuous Tx test. */
-+	BOOLEAN			is_start_cont_tx;
-+
-+	/* TRUE if we are in Single Carrier Tx test. */
-+	BOOLEAN			bSingleCarrier;
-+	/* TRUE if we are in Carrier Suppression Tx Test. */
-+
-+	BOOLEAN			is_carrier_suppression;
-+
-+	/* TRUE if we are in Single Tone Tx test. */
-+
-+	BOOLEAN			is_single_tone;
-+
-+
-+	/* ACK counter asked by K.Y.. */
-+	BOOLEAN			bMptEnableAckCounter;
-+	u32			MptAckCounter;
-+
-+	/* SD3 Willis For 8192S to save 1T/2T RF table for ACUT	Only fro ACUT delete later ~~~! */
-+	/* s8		BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; */
-+	/* s8			BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; */
-+	/* s32			RfReadLine[2]; */
-+
-+	u8		APK_bound[2];	/* for APK	path A/path B */
-+	BOOLEAN		bMptIndexEven;
-+
-+	u8		backup0xc50;
-+	u8		backup0xc58;
-+	u8		backup0xc30;
-+	u8		backup0x52_RF_A;
-+	u8		backup0x52_RF_B;
-+
-+	u32			backup0x58_RF_A;
-+	u32			backup0x58_RF_B;
-+
-+	u8			h2cReqNum;
-+	u8			c2hBuf[32];
-+
-+	u8          btInBuf[100];
-+	u32			mptOutLen;
-+	u8          mptOutBuf[100];
-+	RT_PMAC_TX_INFO	PMacTxInfo;
-+	RT_PMAC_PKT_INFO	PMacPktInfo;
-+	u8 HWTxmode;
-+
-+	BOOLEAN			bldpc;
-+	BOOLEAN			bstbc;
-+} MPT_CONTEXT, *PMPT_CONTEXT;
-+/* #endif */
-+
-+
-+/* #define RTPRIV_IOCTL_MP					( SIOCIWFIRSTPRIV + 0x17) */
-+enum {
-+	WRITE_REG = 1,
-+	READ_REG,
-+	WRITE_RF,
-+	READ_RF,
-+	MP_START,
-+	MP_STOP,
-+	MP_RATE,
-+	MP_CHANNEL,
-+	MP_CHL_OFFSET,
-+	MP_BANDWIDTH,
-+	MP_TXPOWER,
-+	MP_ANT_TX,
-+	MP_ANT_RX,
-+	MP_CTX,
-+	MP_QUERY,
-+	MP_ARX,
-+	MP_PSD,
-+	MP_PWRTRK,
-+	MP_THER,
-+	MP_IOCTL,
-+	EFUSE_GET,
-+	EFUSE_SET,
-+	MP_RESET_STATS,
-+	MP_DUMP,
-+	MP_PHYPARA,
-+	MP_SetRFPathSwh,
-+	MP_QueryDrvStats,
-+	CTA_TEST,
-+	MP_DISABLE_BT_COEXIST,
-+	MP_PwrCtlDM,
-+	MP_GETVER,
-+	MP_MON,
-+	EFUSE_BT_MASK,
-+	EFUSE_MASK,
-+	EFUSE_FILE,
-+	EFUSE_FILE_STORE,
-+	MP_TX,
-+	MP_RX,
-+	MP_IQK,
-+	MP_LCK,
-+	MP_HW_TX_MODE,
-+	MP_GET_TXPOWER_INX,
-+	MP_CUSTOMER_STR,
-+	MP_PWRLMT,
-+	MP_PWRBYRATE,
-+	BT_EFUSE_FILE,
-+	MP_SetBT,
-+	MP_SWRFPath,
-+	MP_LINK,
-+	MP_DPK_TRK,
-+	MP_DPK,
-+	MP_GET_TSSIDE,
-+	MP_SET_TSSIDE,
-+	MP_NULL,
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+	VENDOR_IE_SET ,
-+	VENDOR_IE_GET ,
-+#endif
-+#ifdef CONFIG_WOWLAN
-+	MP_WOW_ENABLE,
-+	MP_WOW_SET_PATTERN,
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+	MP_WOW_SET_KEEP_ALIVE_PATTERN,
-+#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+
-+#endif
-+#ifdef CONFIG_AP_WOWLAN
-+	MP_AP_WOW_ENABLE,
-+#endif
-+	MP_SD_IREAD,
-+	MP_SD_IWRITE,
-+};
-+
-+struct mp_priv {
-+	_adapter *papdater;
-+
-+	/* Testing Flag */
-+	u32 mode;/* 0 for normal type packet, 1 for loopback packet (16bytes TXCMD) */
-+
-+	u32 prev_fw_state;
-+
-+	/* OID cmd handler */
-+	struct mp_wiparam workparam;
-+	/*	u8 act_in_progress; */
-+
-+	/* Tx Section */
-+	u8 TID;
-+	u32 tx_pktcount;
-+	u32 pktInterval;
-+	u32 pktLength;
-+	struct mp_tx tx;
-+
-+	/* Rx Section */
-+	u32 rx_bssidpktcount;
-+	u32 rx_pktcount;
-+	u32 rx_pktcount_filter_out;
-+	u32 rx_crcerrpktcount;
-+	u32 rx_pktloss;
-+	BOOLEAN  rx_bindicatePkt;
-+	struct recv_stat rxstat;
-+	BOOLEAN brx_filter_beacon;
-+
-+	/* RF/BB relative */
-+	u8 channel;
-+	u8 bandwidth;
-+	u8 prime_channel_offset;
-+	u8 txpoweridx;
-+	u8 rateidx;
-+	u32 preamble;
-+	/*	u8 modem; */
-+	u32 CrystalCap;
-+	/*	u32 curr_crystalcap; */
-+
-+	u16 antenna_tx;
-+	u16 antenna_rx;
-+	/*	u8 curr_rfpath; */
-+
-+	u8 check_mp_pkt;
-+
-+	u8 bSetTxPower;
-+	/*	uint ForcedDataRate; */
-+	u8 mp_dm;
-+	u8 mac_filter[ETH_ALEN];
-+	u8 bmac_filter;
-+
-+	/* RF PATH Setting for WLG WLA BTG BT */
-+	u8 rf_path_cfg;
-+
-+	struct wlan_network mp_network;
-+	NDIS_802_11_MAC_ADDRESS network_macaddr;
-+
-+	u8 *pallocated_mp_xmitframe_buf;
-+	u8 *pmp_xmtframe_buf;
-+	_queue free_mp_xmitqueue;
-+	u32 free_mp_xmitframe_cnt;
-+	BOOLEAN bSetRxBssid;
-+	BOOLEAN bTxBufCkFail;
-+	BOOLEAN bRTWSmbCfg;
-+	BOOLEAN bloopback;
-+	BOOLEAN bloadefusemap;
-+	BOOLEAN bloadBTefusemap;
-+	BOOLEAN bprocess_mp_mode;
-+
-+	MPT_CONTEXT	mpt_ctx;
-+
-+	u8		*TXradomBuffer;
-+	u8		CureFuseBTCoex;
-+    u8		mplink_buf[2048];
-+    u32		mplink_rx_len;
-+	BOOLEAN mplink_brx;
-+	BOOLEAN mplink_btx;
-+
-+	bool tssitrk_on;
-+	bool efuse_update_file;
-+	char efuse_file_path[128];
-+};
-+
-+typedef struct _IOCMD_STRUCT_ {
-+	u8	cmdclass;
-+	u16	value;
-+	u8	index;
-+} IOCMD_STRUCT;
-+
-+struct rf_reg_param {
-+	u32 path;
-+	u32 offset;
-+	u32 value;
-+};
-+
-+struct bb_reg_param {
-+	u32 offset;
-+	u32 value;
-+};
-+
-+typedef struct _MP_FIRMWARE {
-+	FIRMWARE_SOURCE eFWSource;
-+#ifdef CONFIG_EMBEDDED_FWIMG
-+	u8		*szFwBuffer;
-+#else
-+	u8			szFwBuffer[0x8000];
-+#endif
-+	u32		ulFwLength;
-+} RT_MP_FIRMWARE, *PRT_MP_FIRMWARE;
-+
-+
-+
-+
-+/* *********************************************************************** */
-+
-+#define LOWER	_TRUE
-+#define RAISE	_FALSE
-+
-+/* Hardware Registers */
-+#if 0
-+#if 0
-+#define IOCMD_CTRL_REG			0x102502C0
-+#define IOCMD_DATA_REG			0x102502C4
-+#else
-+#define IOCMD_CTRL_REG			0x10250370
-+#define IOCMD_DATA_REG			0x10250374
-+#endif
-+
-+#define IOCMD_GET_THERMAL_METER		0xFD000028
-+
-+#define IOCMD_CLASS_BB_RF		0xF0
-+#define IOCMD_BB_READ_IDX		0x00
-+#define IOCMD_BB_WRITE_IDX		0x01
-+#define IOCMD_RF_READ_IDX		0x02
-+#define IOCMD_RF_WRIT_IDX		0x03
-+#endif
-+#define BB_REG_BASE_ADDR		0x800
-+
-+/* MP variables */
-+#if 0
-+#define _2MAC_MODE_	0
-+#define _LOOPBOOK_MODE_	1
-+#endif
-+typedef enum _MP_MODE_ {
-+	MP_OFF,
-+	MP_ON,
-+	MP_ERR,
-+	MP_CONTINUOUS_TX,
-+	MP_SINGLE_CARRIER_TX,
-+	MP_CARRIER_SUPPRISSION_TX,
-+	MP_SINGLE_TONE_TX,
-+	MP_PACKET_TX,
-+	MP_PACKET_RX
-+} MP_MODE;
-+
-+typedef enum _TEST_MODE {
-+	TEST_NONE                 ,
-+	PACKETS_TX                ,
-+	PACKETS_RX                ,
-+	CONTINUOUS_TX             ,
-+	OFDM_Single_Tone_TX       ,
-+	CCK_Carrier_Suppression_TX
-+} TEST_MODE;
-+
-+
-+typedef enum _MPT_BANDWIDTH {
-+	MPT_BW_20MHZ = 0,
-+	MPT_BW_40MHZ_DUPLICATE = 1,
-+	MPT_BW_40MHZ_ABOVE = 2,
-+	MPT_BW_40MHZ_BELOW = 3,
-+	MPT_BW_40MHZ = 4,
-+	MPT_BW_80MHZ = 5,
-+	MPT_BW_80MHZ_20_ABOVE = 6,
-+	MPT_BW_80MHZ_20_BELOW = 7,
-+	MPT_BW_80MHZ_20_BOTTOM = 8,
-+	MPT_BW_80MHZ_20_TOP = 9,
-+	MPT_BW_80MHZ_40_ABOVE = 10,
-+	MPT_BW_80MHZ_40_BELOW = 11,
-+} MPT_BANDWIDTHE, *PMPT_BANDWIDTH;
-+
-+#define MAX_RF_PATH_NUMS	RF_PATH_MAX
-+
-+
-+extern u8 mpdatarate[NumRates];
-+
-+/* MP set force data rate base on the definition. */
-+typedef enum _MPT_RATE_INDEX {
-+	/* CCK rate. */
-+	MPT_RATE_1M = 1 ,	/* 0 */
-+	MPT_RATE_2M,
-+	MPT_RATE_55M,
-+	MPT_RATE_11M,	/* 3 */
-+
-+	/* OFDM rate. */
-+	MPT_RATE_6M,	/* 4 */
-+	MPT_RATE_9M,
-+	MPT_RATE_12M,
-+	MPT_RATE_18M,
-+	MPT_RATE_24M,
-+	MPT_RATE_36M,
-+	MPT_RATE_48M,
-+	MPT_RATE_54M,	/* 11 */
-+
-+	/* HT rate. */
-+	MPT_RATE_MCS0,	/* 12 */
-+	MPT_RATE_MCS1,
-+	MPT_RATE_MCS2,
-+	MPT_RATE_MCS3,
-+	MPT_RATE_MCS4,
-+	MPT_RATE_MCS5,
-+	MPT_RATE_MCS6,
-+	MPT_RATE_MCS7,	/* 19 */
-+	MPT_RATE_MCS8,
-+	MPT_RATE_MCS9,
-+	MPT_RATE_MCS10,
-+	MPT_RATE_MCS11,
-+	MPT_RATE_MCS12,
-+	MPT_RATE_MCS13,
-+	MPT_RATE_MCS14,
-+	MPT_RATE_MCS15,	/* 27 */
-+	MPT_RATE_MCS16,
-+	MPT_RATE_MCS17, /*  #29 */
-+	MPT_RATE_MCS18,
-+	MPT_RATE_MCS19,
-+	MPT_RATE_MCS20,
-+	MPT_RATE_MCS21,
-+	MPT_RATE_MCS22, /*  #34 */
-+	MPT_RATE_MCS23,
-+	MPT_RATE_MCS24,
-+	MPT_RATE_MCS25,
-+	MPT_RATE_MCS26,
-+	MPT_RATE_MCS27, /*  #39 */
-+	MPT_RATE_MCS28, /*  #40 */
-+	MPT_RATE_MCS29, /*  #41 */
-+	MPT_RATE_MCS30, /*  #42 */
-+	MPT_RATE_MCS31, /*  #43 */
-+	/* VHT rate. Total: 20*/
-+	MPT_RATE_VHT1SS_MCS0 = 100,/*  #44*/
-+	MPT_RATE_VHT1SS_MCS1, /*  # */
-+	MPT_RATE_VHT1SS_MCS2,
-+	MPT_RATE_VHT1SS_MCS3,
-+	MPT_RATE_VHT1SS_MCS4,
-+	MPT_RATE_VHT1SS_MCS5,
-+	MPT_RATE_VHT1SS_MCS6, /*  # */
-+	MPT_RATE_VHT1SS_MCS7,
-+	MPT_RATE_VHT1SS_MCS8,
-+	MPT_RATE_VHT1SS_MCS9, /* #53 */
-+	MPT_RATE_VHT2SS_MCS0, /* #54 */
-+	MPT_RATE_VHT2SS_MCS1,
-+	MPT_RATE_VHT2SS_MCS2,
-+	MPT_RATE_VHT2SS_MCS3,
-+	MPT_RATE_VHT2SS_MCS4,
-+	MPT_RATE_VHT2SS_MCS5,
-+	MPT_RATE_VHT2SS_MCS6,
-+	MPT_RATE_VHT2SS_MCS7,
-+	MPT_RATE_VHT2SS_MCS8,
-+	MPT_RATE_VHT2SS_MCS9, /* #63 */
-+	MPT_RATE_VHT3SS_MCS0,
-+	MPT_RATE_VHT3SS_MCS1,
-+	MPT_RATE_VHT3SS_MCS2,
-+	MPT_RATE_VHT3SS_MCS3,
-+	MPT_RATE_VHT3SS_MCS4,
-+	MPT_RATE_VHT3SS_MCS5,
-+	MPT_RATE_VHT3SS_MCS6, /*  #126 */
-+	MPT_RATE_VHT3SS_MCS7,
-+	MPT_RATE_VHT3SS_MCS8,
-+	MPT_RATE_VHT3SS_MCS9,
-+	MPT_RATE_VHT4SS_MCS0,
-+	MPT_RATE_VHT4SS_MCS1, /*  #131 */
-+	MPT_RATE_VHT4SS_MCS2,
-+	MPT_RATE_VHT4SS_MCS3,
-+	MPT_RATE_VHT4SS_MCS4,
-+	MPT_RATE_VHT4SS_MCS5,
-+	MPT_RATE_VHT4SS_MCS6, /*  #136 */
-+	MPT_RATE_VHT4SS_MCS7,
-+	MPT_RATE_VHT4SS_MCS8,
-+	MPT_RATE_VHT4SS_MCS9,
-+	MPT_RATE_LAST
-+} MPT_RATE_E, *PMPT_RATE_E;
-+
-+#define MAX_TX_PWR_INDEX_N_MODE 64	/* 0x3F */
-+
-+#define MPT_IS_CCK_RATE(_value)		(MPT_RATE_1M <= _value && _value <= MPT_RATE_11M)
-+#define MPT_IS_OFDM_RATE(_value)	(MPT_RATE_6M <= _value && _value <= MPT_RATE_54M)
-+#define MPT_IS_HT_RATE(_value)		(MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS31)
-+#define MPT_IS_HT_1S_RATE(_value)	(MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS7)
-+#define MPT_IS_HT_2S_RATE(_value)	(MPT_RATE_MCS8 <= _value && _value <= MPT_RATE_MCS15)
-+#define MPT_IS_HT_3S_RATE(_value)	(MPT_RATE_MCS16 <= _value && _value <= MPT_RATE_MCS23)
-+#define MPT_IS_HT_4S_RATE(_value)	(MPT_RATE_MCS24 <= _value && _value <= MPT_RATE_MCS31)
-+
-+#define MPT_IS_VHT_RATE(_value)		(MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9)
-+#define MPT_IS_VHT_1S_RATE(_value)	(MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT1SS_MCS9)
-+#define MPT_IS_VHT_2S_RATE(_value)	(MPT_RATE_VHT2SS_MCS0 <= _value && _value <= MPT_RATE_VHT2SS_MCS9)
-+#define MPT_IS_VHT_3S_RATE(_value)	(MPT_RATE_VHT3SS_MCS0 <= _value && _value <= MPT_RATE_VHT3SS_MCS9)
-+#define MPT_IS_VHT_4S_RATE(_value)	(MPT_RATE_VHT4SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9)
-+
-+#define MPT_IS_2SS_RATE(_rate) ((MPT_RATE_MCS8 <= _rate && _rate <= MPT_RATE_MCS15) || \
-+	(MPT_RATE_VHT2SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT2SS_MCS9))
-+#define MPT_IS_3SS_RATE(_rate) ((MPT_RATE_MCS16 <= _rate && _rate <= MPT_RATE_MCS23) || \
-+	(MPT_RATE_VHT3SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT3SS_MCS9))
-+#define MPT_IS_4SS_RATE(_rate) ((MPT_RATE_MCS24 <= _rate && _rate <= MPT_RATE_MCS31) || \
-+	(MPT_RATE_VHT4SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT4SS_MCS9))
-+
-+typedef enum _POWER_MODE_ {
-+	POWER_LOW = 0,
-+	POWER_NORMAL
-+} POWER_MODE;
-+
-+/* The following enumeration is used to define the value of Reg0xD00[30:28] or JaguarReg0x914[18:16]. */
-+typedef enum _OFDM_TX_MODE {
-+	OFDM_ALL_OFF		= 0,
-+	OFDM_ContinuousTx	= 1,
-+	OFDM_SingleCarrier	= 2,
-+	OFDM_SingleTone	= 4,
-+} OFDM_TX_MODE;
-+
-+
-+#define RX_PKT_BROADCAST	1
-+#define RX_PKT_DEST_ADDR	2
-+#define RX_PKT_PHY_MATCH	3
-+
-+typedef enum _ENCRY_CTRL_STATE_ {
-+	HW_CONTROL,		/* hw encryption& decryption */
-+	SW_CONTROL,		/* sw encryption& decryption */
-+	HW_ENCRY_SW_DECRY,	/* hw encryption & sw decryption */
-+	SW_ENCRY_HW_DECRY	/* sw encryption & hw decryption */
-+} ENCRY_CTRL_STATE;
-+
-+typedef enum	_MPT_TXPWR_DEF {
-+	MPT_CCK,
-+	MPT_OFDM, /* L and HT OFDM */
-+	MPT_OFDM_AND_HT,
-+	MPT_HT,
-+	MPT_VHT
-+} MPT_TXPWR_DEF;
-+
-+
-+#define IS_MPT_HT_RATE(_rate)			(_rate >= MPT_RATE_MCS0 && _rate <= MPT_RATE_MCS31)
-+#define IS_MPT_VHT_RATE(_rate)			(_rate >= MPT_RATE_VHT1SS_MCS0 && _rate <= MPT_RATE_VHT4SS_MCS9)
-+#define IS_MPT_CCK_RATE(_rate)			(_rate >= MPT_RATE_1M && _rate <= MPT_RATE_11M)
-+#define IS_MPT_OFDM_RATE(_rate)			(_rate >= MPT_RATE_6M && _rate <= MPT_RATE_54M)
-+
-+typedef enum _mp_tx_pkt_payload{
-+	MP_TX_Payload_00 = 0,
-+	MP_TX_Payload_a5,
-+	MP_TX_Payload_5a,
-+	MP_TX_Payload_ff,
-+	MP_TX_Payload_prbs9,
-+	MP_TX_Payload_default_random
-+} mp_tx_pkt_payload;
-+
-+/*************************************************************************/
-+#if 0
-+extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv);
-+extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe);
-+#endif
-+
-+extern s32 init_mp_priv(PADAPTER padapter);
-+extern void free_mp_priv(struct mp_priv *pmp_priv);
-+extern s32 MPT_InitializeAdapter(PADAPTER padapter, u8 Channel);
-+extern void MPT_DeInitAdapter(PADAPTER padapter);
-+extern s32 mp_start_test(PADAPTER padapter);
-+extern void mp_stop_test(PADAPTER padapter);
-+
-+extern u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask);
-+extern void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val);
-+
-+extern u32 read_macreg(_adapter *padapter, u32 addr, u32 sz);
-+extern void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz);
-+extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask);
-+extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val);
-+extern u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr);
-+extern void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val);
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain);
-+#endif
-+void	SetChannel(PADAPTER pAdapter);
-+void	SetBandwidth(PADAPTER pAdapter);
-+int	SetTxPower(PADAPTER pAdapter);
-+void	SetAntenna(PADAPTER pAdapter);
-+void	SetDataRate(PADAPTER pAdapter);
-+void	SetAntenna(PADAPTER pAdapter);
-+s32	SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
-+void	GetThermalMeter(PADAPTER pAdapter, u8 rfpath ,u8 *value);
-+void	SetContinuousTx(PADAPTER pAdapter, u8 bStart);
-+void	SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart);
-+void	SetSingleToneTx(PADAPTER pAdapter, u8 bStart);
-+void	SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
-+void	PhySetTxPowerLevel(PADAPTER pAdapter);
-+void	fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc);
-+void	SetPacketTx(PADAPTER padapter);
-+void	SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB);
-+void	ResetPhyRxPktCount(PADAPTER pAdapter);
-+u32	GetPhyRxPktReceived(PADAPTER pAdapter);
-+u32	GetPhyRxPktCRC32Error(PADAPTER pAdapter);
-+s32	SetPowerTracking(PADAPTER padapter, u8 enable);
-+void	GetPowerTracking(PADAPTER padapter, u8 *enable);
-+u32	mp_query_psd(PADAPTER pAdapter, u8 *data);
-+void	rtw_mp_trigger_iqk(PADAPTER padapter);
-+void	rtw_mp_trigger_lck(PADAPTER padapter);
-+void	rtw_mp_trigger_dpk(PADAPTER padapter);
-+u8 rtw_mp_mode_check(PADAPTER padapter);
-+bool rtw_is_mp_tssitrk_on(_adapter *adapter);
-+
-+void hal_mpt_SwitchRfSetting(PADAPTER pAdapter);
-+s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable);
-+void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable);
-+void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14);
-+void hal_mpt_SetChannel(PADAPTER pAdapter);
-+void hal_mpt_SetBandwidth(PADAPTER pAdapter);
-+void hal_mpt_SetTxPower(PADAPTER pAdapter);
-+void hal_mpt_SetDataRate(PADAPTER pAdapter);
-+void hal_mpt_SetAntenna(PADAPTER pAdapter);
-+s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther);
-+void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter);
-+u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path);
-+void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value);
-+void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart);
-+void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart);
-+void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart);
-+void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart);
-+u8 mpt_ProSetPMacTx(PADAPTER	Adapter);
-+void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain);
-+void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate);
-+u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter);
-+u32 mpt_ProQueryCalTxPower(PADAPTER	pAdapter, u8 RfPath);
-+void MPT_PwrCtlDM(PADAPTER padapter, u32 trk_type);
-+u8 mpt_to_mgnt_rate(u32	MptRateIdx);
-+u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr);
-+u32 mp_join(PADAPTER padapter, u8 mode);
-+u32 hal_mpt_query_phytxok(PADAPTER	pAdapter);
-+u32 mpt_get_tx_power_finalabs_val(PADAPTER	padapter, u8 rf_path);
-+void mpt_trigger_tssi_tracking(PADAPTER pAdapter, u8 rf_path);
-+
-+
-+void
-+PMAC_Get_Pkt_Param(
-+	PRT_PMAC_TX_INFO	pPMacTxInfo,
-+	PRT_PMAC_PKT_INFO	pPMacPktInfo
-+);
-+void
-+CCK_generator(
-+	PRT_PMAC_TX_INFO	pPMacTxInfo,
-+	PRT_PMAC_PKT_INFO	pPMacPktInfo
-+);
-+void
-+PMAC_Nsym_generator(
-+	PRT_PMAC_TX_INFO	pPMacTxInfo,
-+	PRT_PMAC_PKT_INFO	pPMacPktInfo
-+);
-+void
-+L_SIG_generator(
-+	u32	N_SYM,		/* Max: 750*/
-+	PRT_PMAC_TX_INFO	pPMacTxInfo,
-+	PRT_PMAC_PKT_INFO	pPMacPktInfo
-+);
-+
-+void HT_SIG_generator(
-+	PRT_PMAC_TX_INFO	pPMacTxInfo,
-+	PRT_PMAC_PKT_INFO	pPMacPktInfo);
-+
-+void VHT_SIG_A_generator(
-+	PRT_PMAC_TX_INFO	pPMacTxInfo,
-+	PRT_PMAC_PKT_INFO	pPMacPktInfo);
-+
-+void VHT_SIG_B_generator(
-+	PRT_PMAC_TX_INFO	pPMacTxInfo);
-+
-+void VHT_Delimiter_generator(
-+	PRT_PMAC_TX_INFO	pPMacTxInfo);
-+
-+
-+int rtw_mp_write_reg(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_read_reg(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_write_rf(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_read_rf(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_start(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_stop(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_rate(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_channel(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_ch_offset(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_bandwidth(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_txpower_index(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_txpower(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_txpower(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_ant_tx(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_ant_rx(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_set_ctx_destAddr(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_ctx(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_disable_bt_coexist(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_mp_disable_bt_coexist(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_mp_arx(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_trx_query(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_pwrtrk(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_psd(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_thermal(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_reset_stats(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_dump(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_phypara(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_SetRFPath(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_switch_rf_path(struct net_device *dev,
-+			struct iw_request_info *info,
-+			struct iw_point *wrqu, char *extra);
-+int rtw_mp_link(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_QueryDrv(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_mp_PwrCtlDM(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_getver(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_mp_mon(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_mp_pwrlmt(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_mp_pwrbyrate(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_mp_dpk_track(struct net_device *dev,
-+			struct iw_request_info *info,
-+			union iwreq_data *wrqu, char *extra);
-+int rtw_mp_dpk(struct net_device *dev,
-+			struct iw_request_info *info,
-+			union iwreq_data *wrqu, char *extra);
-+int rtw_efuse_mask_file(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_bt_efuse_mask_file(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_efuse_file_map(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_efuse_file_map_store(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_bt_efuse_file_map(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_mp_SetBT(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra);
-+int rtw_mp_tx(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_mp_rx(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+int rtw_mp_hwtx(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra);
-+u8 HwRateToMPTRate(u8 rate);
-+int rtw_mp_iqk(struct net_device *dev,
-+		 struct iw_request_info *info,
-+		 struct iw_point *wrqu, char *extra);
-+int rtw_mp_lck(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_get_tsside(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+int rtw_mp_set_tsside(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra);
-+#endif /* _RTW_MP_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_mp_phy_regdef.h b/drivers/staging/rtl8723cs/include/rtw_mp_phy_regdef.h
-new file mode 100644
-index 000000000000..be627800e522
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_mp_phy_regdef.h
-@@ -0,0 +1,1094 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*****************************************************************************
-+ *
-+ * Module:	__RTW_MP_PHY_REGDEF_H_
-+ *
-+ *
-+ * Note:	1. Define PMAC/BB register map
-+ *			2. Define RF register map
-+ *			3. PMAC/BB register bit mask.
-+ *			4. RF reg bit mask.
-+ *			5. Other BB/RF relative definition.
-+ *
-+ *
-+ * Export:	Constants, macro, functions(API), global variables(None).
-+ *
-+ * Abbrev:
-+ *
-+ * History:
-+ *	Data			Who		Remark
-+ *	08/07/2007	MHC		1. Porting from 9x series PHYCFG.h.
-+ *						2. Reorganize code architecture.
-+ *	09/25/2008	MH		1. Add RL6052 register definition
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_MP_PHY_REGDEF_H_
-+#define __RTW_MP_PHY_REGDEF_H_
-+
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+/* ************************************************************
-+ * 8192S Regsiter offset definition
-+ * ************************************************************ */
-+
-+/*
-+ * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
-+ * 3. RF register 0x00-2E
-+ * 4. Bit Mask for BB/RF register
-+ * 5. Other defintion for BB/RF R/W
-+ *   */
-+
-+
-+/*
-+ * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
-+ * 1. Page1(0x100)
-+ *   */
-+#define		rPMAC_Reset					0x100
-+#define		rPMAC_TxStart					0x104
-+#define		rPMAC_TxLegacySIG				0x108
-+#define		rPMAC_TxHTSIG1				0x10c
-+#define		rPMAC_TxHTSIG2				0x110
-+#define		rPMAC_PHYDebug				0x114
-+#define		rPMAC_TxPacketNum				0x118
-+#define		rPMAC_TxIdle					0x11c
-+#define		rPMAC_TxMACHeader0			0x120
-+#define		rPMAC_TxMACHeader1			0x124
-+#define		rPMAC_TxMACHeader2			0x128
-+#define		rPMAC_TxMACHeader3			0x12c
-+#define		rPMAC_TxMACHeader4			0x130
-+#define		rPMAC_TxMACHeader5			0x134
-+#define		rPMAC_TxDataType				0x138
-+#define		rPMAC_TxRandomSeed			0x13c
-+#define		rPMAC_CCKPLCPPreamble			0x140
-+#define		rPMAC_CCKPLCPHeader			0x144
-+#define		rPMAC_CCKCRC16				0x148
-+#define		rPMAC_OFDMRxCRC32OK			0x170
-+#define		rPMAC_OFDMRxCRC32Er			0x174
-+#define		rPMAC_OFDMRxParityEr			0x178
-+#define		rPMAC_OFDMRxCRC8Er			0x17c
-+#define		rPMAC_CCKCRxRC16Er			0x180
-+#define		rPMAC_CCKCRxRC32Er			0x184
-+#define		rPMAC_CCKCRxRC32OK			0x188
-+#define		rPMAC_TxStatus					0x18c
-+
-+/*
-+ * 2. Page2(0x200)
-+ *
-+ * The following two definition are only used for USB interface.
-+ * #define		RF_BB_CMD_ADDR				0x02c0 */	/* RF/BB read/write command address.
-+ * #define		RF_BB_CMD_DATA				0x02c4 */	/* RF/BB read/write command data. */
-+
-+/*
-+ * 3. Page8(0x800)
-+ *   */
-+#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC */ /* RF BW Setting?? */
-+
-+#define		rFPGA0_TxInfo				0x804	/* Status report?? */
-+#define		rFPGA0_PSDFunction			0x808
-+
-+#define		rFPGA0_TxGainStage			0x80c	/* Set TX PWR init gain? */
-+
-+#define		rFPGA0_RFTiming1			0x810	/* Useless now */
-+#define		rFPGA0_RFTiming2			0x814
-+/* #define rFPGA0_XC_RFTiming		0x818 */
-+/* #define rFPGA0_XD_RFTiming		0x81c */
-+
-+#define		rFPGA0_XA_HSSIParameter1		0x820	/* RF 3 wire register */
-+#define		rFPGA0_XA_HSSIParameter2		0x824
-+#define		rFPGA0_XB_HSSIParameter1		0x828
-+#define		rFPGA0_XB_HSSIParameter2		0x82c
-+#define		rFPGA0_XC_HSSIParameter1		0x830
-+#define		rFPGA0_XC_HSSIParameter2		0x834
-+#define		rFPGA0_XD_HSSIParameter1		0x838
-+#define		rFPGA0_XD_HSSIParameter2		0x83c
-+#define		rFPGA0_XA_LSSIParameter		0x840
-+#define		rFPGA0_XB_LSSIParameter		0x844
-+#define		rFPGA0_XC_LSSIParameter		0x848
-+#define		rFPGA0_XD_LSSIParameter		0x84c
-+
-+#define		rFPGA0_RFWakeUpParameter		0x850	/* Useless now */
-+#define		rFPGA0_RFSleepUpParameter		0x854
-+
-+#define		rFPGA0_XAB_SwitchControl		0x858	/* RF Channel switch */
-+#define		rFPGA0_XCD_SwitchControl		0x85c
-+
-+#define		rFPGA0_XA_RFInterfaceOE		0x860	/* RF Channel switch */
-+#define		rFPGA0_XB_RFInterfaceOE		0x864
-+#define		rFPGA0_XC_RFInterfaceOE		0x868
-+#define		rFPGA0_XD_RFInterfaceOE		0x86c
-+
-+#define		rFPGA0_XAB_RFInterfaceSW		0x870	/* RF Interface Software Control */
-+#define		rFPGA0_XCD_RFInterfaceSW		0x874
-+
-+#define		rFPGA0_XAB_RFParameter		0x878	/* RF Parameter */
-+#define		rFPGA0_XCD_RFParameter		0x87c
-+
-+#define		rFPGA0_AnalogParameter1		0x880	/* Crystal cap setting RF-R/W protection for parameter4?? */
-+#define		rFPGA0_AnalogParameter2		0x884
-+#define		rFPGA0_AnalogParameter3		0x888	/* Useless now */
-+#define		rFPGA0_AnalogParameter4		0x88c
-+
-+#define		rFPGA0_XA_LSSIReadBack		0x8a0	/* Tranceiver LSSI Readback */
-+#define		rFPGA0_XB_LSSIReadBack		0x8a4
-+#define		rFPGA0_XC_LSSIReadBack		0x8a8
-+#define		rFPGA0_XD_LSSIReadBack		0x8ac
-+
-+#define		rFPGA0_PSDReport				0x8b4	/* Useless now */
-+#define		rFPGA0_XAB_RFInterfaceRB		0x8e0	/* Useless now */ /* RF Interface Readback Value */
-+#define		rFPGA0_XCD_RFInterfaceRB		0x8e4	/* Useless now */
-+
-+/*
-+ * 4. Page9(0x900)
-+ *   */
-+#define		rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC */ /* RF BW Setting?? */
-+
-+#define		rFPGA1_TxBlock				0x904	/* Useless now */
-+#define		rFPGA1_DebugSelect			0x908	/* Useless now */
-+#define		rFPGA1_TxInfo				0x90c	/* Useless now */ /* Status report?? */
-+#define	rS0S1_PathSwitch			0x948
-+
-+/*
-+ * 5. PageA(0xA00)
-+ *
-+ * Set Control channel to upper or lower. These settings are required only for 40MHz */
-+#define		rCCK0_System				0xa00
-+
-+#define		rCCK0_AFESetting			0xa04	/* Disable init gain now */ /* Select RX path by RSSI */
-+#define		rCCK0_CCA					0xa08	/* Disable init gain now */ /* Init gain */
-+
-+#define		rCCK0_RxAGC1				0xa0c	/* AGC default value, saturation level  */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
-+#define		rCCK0_RxAGC2				0xa10	/* AGC & DAGC */
-+
-+#define		rCCK0_RxHP					0xa14
-+
-+#define		rCCK0_DSPParameter1		0xa18	/* Timing recovery & Channel estimation threshold */
-+#define		rCCK0_DSPParameter2		0xa1c	/* SQ threshold */
-+
-+#define		rCCK0_TxFilter1				0xa20
-+#define		rCCK0_TxFilter2				0xa24
-+#define		rCCK0_DebugPort			0xa28	/* debug port and Tx filter3 */
-+#define		rCCK0_FalseAlarmReport		0xa2c	/* 0xa2d	useless now 0xa30-a4f channel report */
-+#define		rCCK0_TRSSIReport		0xa50
-+#define		rCCK0_RxReport            		0xa54  /* 0xa57 */
-+#define		rCCK0_FACounterLower      	0xa5c  /* 0xa5b */
-+#define		rCCK0_FACounterUpper      	0xa58  /* 0xa5c */
-+
-+/*
-+ * 6. PageC(0xC00)
-+ *   */
-+#define		rOFDM0_LSTF				0xc00
-+
-+#define		rOFDM0_TRxPathEnable		0xc04
-+#define		rOFDM0_TRMuxPar			0xc08
-+#define		rOFDM0_TRSWIsolation		0xc0c
-+
-+#define		rOFDM0_XARxAFE			0xc10  /* RxIQ DC offset, Rx digital filter, DC notch filter */
-+#define		rOFDM0_XARxIQImbalance    	0xc14  /* RxIQ imblance matrix */
-+#define		rOFDM0_XBRxAFE		0xc18
-+#define		rOFDM0_XBRxIQImbalance	0xc1c
-+#define		rOFDM0_XCRxAFE		0xc20
-+#define		rOFDM0_XCRxIQImbalance	0xc24
-+#define		rOFDM0_XDRxAFE		0xc28
-+#define		rOFDM0_XDRxIQImbalance	0xc2c
-+
-+#define		rOFDM0_RxDetector1			0xc30  /* PD, BW & SBD	 */ /* DM tune init gain */
-+#define		rOFDM0_RxDetector2			0xc34  /* SBD & Fame Sync. */
-+#define		rOFDM0_RxDetector3			0xc38  /* Frame Sync. */
-+#define		rOFDM0_RxDetector4			0xc3c  /* PD, SBD, Frame Sync & Short-GI */
-+
-+#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
-+#define		rOFDM0_CFOandDAGC		0xc44  /* CFO & DAGC */
-+#define		rOFDM0_CCADropThreshold	0xc48 /* CCA Drop threshold */
-+#define		rOFDM0_ECCAThreshold		0xc4c /* energy CCA */
-+
-+#define		rOFDM0_XAAGCCore1			0xc50	/* DIG  */
-+#define		rOFDM0_XAAGCCore2			0xc54
-+#define		rOFDM0_XBAGCCore1			0xc58
-+#define		rOFDM0_XBAGCCore2			0xc5c
-+#define		rOFDM0_XCAGCCore1			0xc60
-+#define		rOFDM0_XCAGCCore2			0xc64
-+#define		rOFDM0_XDAGCCore1			0xc68
-+#define		rOFDM0_XDAGCCore2			0xc6c
-+
-+#define		rOFDM0_AGCParameter1			0xc70
-+#define		rOFDM0_AGCParameter2			0xc74
-+#define		rOFDM0_AGCRSSITable			0xc78
-+#define		rOFDM0_HTSTFAGC				0xc7c
-+
-+#define		rOFDM0_XATxIQImbalance		0xc80	/* TX PWR TRACK and DIG */
-+#define		rOFDM0_XATxAFE				0xc84
-+#define		rOFDM0_XBTxIQImbalance		0xc88
-+#define		rOFDM0_XBTxAFE				0xc8c
-+#define		rOFDM0_XCTxIQImbalance		0xc90
-+#define		rOFDM0_XCTxAFE			0xc94
-+#define		rOFDM0_XDTxIQImbalance		0xc98
-+#define		rOFDM0_XDTxAFE				0xc9c
-+#define		rOFDM0_RxIQExtAnta			0xca0
-+
-+#define		rOFDM0_RxHPParameter			0xce0
-+#define		rOFDM0_TxPseudoNoiseWgt		0xce4
-+#define		rOFDM0_FrameSync				0xcf0
-+#define		rOFDM0_DFSReport				0xcf4
-+#define		rOFDM0_TxCoeff1				0xca4
-+#define		rOFDM0_TxCoeff2				0xca8
-+#define		rOFDM0_TxCoeff3				0xcac
-+#define		rOFDM0_TxCoeff4				0xcb0
-+#define		rOFDM0_TxCoeff5				0xcb4
-+#define		rOFDM0_TxCoeff6				0xcb8
-+
-+
-+/*
-+ * 7. PageD(0xD00)
-+ *   */
-+#define		rOFDM1_LSTF					0xd00
-+#define		rOFDM1_TRxPathEnable			0xd04
-+
-+#define		rOFDM1_CFO						0xd08	/* No setting now */
-+#define		rOFDM1_CSI1					0xd10
-+#define		rOFDM1_SBD						0xd14
-+#define		rOFDM1_CSI2					0xd18
-+#define		rOFDM1_CFOTracking			0xd2c
-+#define		rOFDM1_TRxMesaure1			0xd34
-+#define		rOFDM1_IntfDet					0xd3c
-+#define		rOFDM1_PseudoNoiseStateAB		0xd50
-+#define		rOFDM1_PseudoNoiseStateCD		0xd54
-+#define		rOFDM1_RxPseudoNoiseWgt		0xd58
-+
-+#define		rOFDM_PHYCounter1				0xda0  /* cca, parity fail */
-+#define		rOFDM_PHYCounter2				0xda4  /* rate illegal, crc8 fail */
-+#define		rOFDM_PHYCounter3				0xda8  /* MCS not support */
-+
-+#define		rOFDM_ShortCFOAB				0xdac	/* No setting now */
-+#define		rOFDM_ShortCFOCD				0xdb0
-+#define		rOFDM_LongCFOAB				0xdb4
-+#define		rOFDM_LongCFOCD				0xdb8
-+#define		rOFDM_TailCFOAB				0xdbc
-+#define		rOFDM_TailCFOCD				0xdc0
-+#define		rOFDM_PWMeasure1		0xdc4
-+#define		rOFDM_PWMeasure2		0xdc8
-+#define		rOFDM_BWReport				0xdcc
-+#define		rOFDM_AGCReport				0xdd0
-+#define		rOFDM_RxSNR					0xdd4
-+#define		rOFDM_RxEVMCSI				0xdd8
-+#define		rOFDM_SIGReport				0xddc
-+
-+
-+/*
-+ * 8. PageE(0xE00)
-+ *   */
-+#define		rTxAGC_Rate18_06				0xe00
-+#define		rTxAGC_Rate54_24				0xe04
-+#define		rTxAGC_CCK_Mcs32				0xe08
-+#define		rTxAGC_Mcs03_Mcs00			0xe10
-+#define		rTxAGC_Mcs07_Mcs04			0xe14
-+#define		rTxAGC_Mcs11_Mcs08			0xe18
-+#define		rTxAGC_Mcs15_Mcs12			0xe1c
-+
-+/* Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] */
-+#define		rRx_Wait_CCCA					0xe70
-+#define		rAnapar_Ctrl_BB					0xee0
-+
-+/*
-+ * 7. RF Register 0x00-0x2E (RF 8256)
-+ * RF-0222D 0x00-3F
-+ *
-+ * Zebra1 */
-+#define RTL92SE_FPGA_VERIFY 0
-+#define		rZebra1_HSSIEnable				0x0	/* Useless now */
-+#define		rZebra1_TRxEnable1				0x1
-+#define		rZebra1_TRxEnable2				0x2
-+#define		rZebra1_AGC					0x4
-+#define		rZebra1_ChargePump			0x5
-+/* #if (RTL92SE_FPGA_VERIFY == 1) */
-+#define		rZebra1_Channel				0x7	/* RF channel switch
-+ * #else */
-+
-+/* #endif */
-+#define		rZebra1_TxGain					0x8	/* Useless now */
-+#define		rZebra1_TxLPF					0x9
-+#define		rZebra1_RxLPF					0xb
-+#define		rZebra1_RxHPFCorner			0xc
-+
-+/* Zebra4 */
-+#define		rGlobalCtrl						0	/* Useless now */
-+#define		rRTL8256_TxLPF					19
-+#define		rRTL8256_RxLPF					11
-+
-+/* RTL8258 */
-+#define		rRTL8258_TxLPF					0x11	/* Useless now */
-+#define		rRTL8258_RxLPF					0x13
-+#define		rRTL8258_RSSILPF				0xa
-+
-+/*
-+ * RL6052 Register definition
-+ *   */
-+#define		RF_AC						0x00	/*  */
-+
-+#define		RF_IQADJ_G1				0x01	/*  */
-+#define		RF_IQADJ_G2				0x02	/*  */
-+#define		RF_POW_TRSW				0x05	/*  */
-+
-+#define		RF_GAIN_RX					0x06	/*  */
-+#define		RF_GAIN_TX					0x07	/*  */
-+
-+#define		RF_TXM_IDAC				0x08	/*  */
-+#define		RF_BS_IQGEN				0x0F	/*  */
-+
-+#define		RF_MODE1					0x10	/*  */
-+#define		RF_MODE2					0x11	/*  */
-+
-+#define		RF_RX_AGC_HP				0x12	/*  */
-+#define		RF_TX_AGC					0x13	/*  */
-+#define		RF_BIAS						0x14	/*  */
-+#define		RF_IPA						0x15	/*  */
-+#define		RF_TXBIAS					0x16
-+#define		RF_POW_ABILITY			0x17	/*  */
-+#define		RF_MODE_AG				0x18	/*  */
-+#define		rRfChannel					0x18	/* RF channel and BW switch */
-+#define		RF_CHNLBW					0x18	/* RF channel and BW switch */
-+#define		RF_TOP						0x19	/*  */
-+
-+#define		RF_RX_G1					0x1A	/*  */
-+#define		RF_RX_G2					0x1B	/*  */
-+
-+#define		RF_RX_BB2					0x1C	/*  */
-+#define		RF_RX_BB1					0x1D	/*  */
-+
-+#define		RF_RCK1					0x1E	/*  */
-+#define		RF_RCK2					0x1F	/*  */
-+
-+#define		RF_TX_G1					0x20	/*  */
-+#define		RF_TX_G2					0x21	/*  */
-+#define		RF_TX_G3					0x22	/*  */
-+
-+#define		RF_TX_BB1					0x23	/*  */
-+
-+#define		RF_T_METER					0x24	/*  */
-+
-+#define		RF_SYN_G1					0x25	/* RF TX Power control */
-+#define		RF_SYN_G2					0x26	/* RF TX Power control */
-+#define		RF_SYN_G3					0x27	/* RF TX Power control */
-+#define		RF_SYN_G4					0x28	/* RF TX Power control */
-+#define		RF_SYN_G5					0x29	/* RF TX Power control */
-+#define		RF_SYN_G6					0x2A	/* RF TX Power control */
-+#define		RF_SYN_G7					0x2B	/* RF TX Power control */
-+#define		RF_SYN_G8					0x2C	/* RF TX Power control */
-+
-+#define		RF_RCK_OS					0x30	/* RF TX PA control */
-+
-+#define		RF_TXPA_G1					0x31	/* RF TX PA control */
-+#define		RF_TXPA_G2					0x32	/* RF TX PA control */
-+#define		RF_TXPA_G3					0x33	/* RF TX PA control */
-+
-+/*
-+ * Bit Mask
-+ *
-+ * 1. Page1(0x100) */
-+#define		bBBResetB						0x100	/* Useless now? */
-+#define		bGlobalResetB					0x200
-+#define		bOFDMTxStart					0x4
-+#define		bCCKTxStart						0x8
-+#define		bCRC32Debug					0x100
-+#define		bPMACLoopback					0x10
-+#define		bTxLSIG							0xffffff
-+#define		bOFDMTxRate					0xf
-+#define		bOFDMTxReserved				0x10
-+#define		bOFDMTxLength					0x1ffe0
-+#define		bOFDMTxParity					0x20000
-+#define		bTxHTSIG1						0xffffff
-+#define		bTxHTMCSRate					0x7f
-+#define		bTxHTBW						0x80
-+#define		bTxHTLength					0xffff00
-+#define		bTxHTSIG2						0xffffff
-+#define		bTxHTSmoothing					0x1
-+#define		bTxHTSounding					0x2
-+#define		bTxHTReserved					0x4
-+#define		bTxHTAggreation				0x8
-+#define		bTxHTSTBC						0x30
-+#define		bTxHTAdvanceCoding			0x40
-+#define		bTxHTShortGI					0x80
-+#define		bTxHTNumberHT_LTF			0x300
-+#define		bTxHTCRC8						0x3fc00
-+#define		bCounterReset					0x10000
-+#define		bNumOfOFDMTx					0xffff
-+#define		bNumOfCCKTx					0xffff0000
-+#define		bTxIdleInterval					0xffff
-+#define		bOFDMService					0xffff0000
-+#define		bTxMACHeader					0xffffffff
-+#define		bTxDataInit						0xff
-+#define		bTxHTMode						0x100
-+#define		bTxDataType					0x30000
-+#define		bTxRandomSeed					0xffffffff
-+#define		bCCKTxPreamble					0x1
-+#define		bCCKTxSFD						0xffff0000
-+#define		bCCKTxSIG						0xff
-+#define		bCCKTxService					0xff00
-+#define		bCCKLengthExt					0x8000
-+#define		bCCKTxLength					0xffff0000
-+#define		bCCKTxCRC16					0xffff
-+#define		bCCKTxStatus					0x1
-+#define		bOFDMTxStatus					0x2
-+
-+#define		IS_BB_REG_OFFSET_92S(_Offset)		((_Offset >= 0x800) && (_Offset <= 0xfff))
-+
-+/* 2. Page8(0x800) */
-+#define		bRFMOD							0x1	/* Reg 0x800 rFPGA0_RFMOD */
-+#define		bJapanMode						0x2
-+#define		bCCKTxSC						0x30
-+#define		bCCKEn							0x1000000
-+#define		bOFDMEn						0x2000000
-+
-+#define		bOFDMRxADCPhase           		0x10000	/* Useless now */
-+#define		bOFDMTxDACPhase		0x40000
-+#define		bXATxAGC			0x3f
-+
-+#define		bXBTxAGC                  			0xf00	/* Reg 80c rFPGA0_TxGainStage */
-+#define		bXCTxAGC			0xf000
-+#define		bXDTxAGC			0xf0000
-+
-+#define		bPAStart                  			0xf0000000	/* Useless now */
-+#define		bTRStart			0x00f00000
-+#define		bRFStart			0x0000f000
-+#define		bBBStart			0x000000f0
-+#define		bBBCCKStart		0x0000000f
-+#define		bPAEnd                    			0xf          /* Reg0x814 */
-+#define		bTREnd			0x0f000000
-+#define		bRFEnd			0x000f0000
-+#define		bCCAMask                  			0x000000f0   /* T2R */
-+#define		bR2RCCAMask		0x00000f00
-+#define		bHSSI_R2TDelay		0xf8000000
-+#define		bHSSI_T2RDelay		0xf80000
-+#define		bContTxHSSI               		0x400     /* chane gain at continue Tx */
-+#define		bIGFromCCK		0x200
-+#define		bAGCAddress		0x3f
-+#define		bRxHPTx			0x7000
-+#define		bRxHPT2R			0x38000
-+#define		bRxHPCCKIni		0xc0000
-+#define		bAGCTxCode		0xc00000
-+#define		bAGCRxCode		0x300000
-+
-+#define		b3WireDataLength          		0x800	/* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
-+#define		b3WireAddressLength		0x400
-+
-+#define		b3WireRFPowerDown         		0x1	/* Useless now
-+ * #define bHWSISelect		0x8 */
-+#define		b5GPAPEPolarity		0x40000000
-+#define		b2GPAPEPolarity		0x80000000
-+#define		bRFSW_TxDefaultAnt		0x3
-+#define		bRFSW_TxOptionAnt		0x30
-+#define		bRFSW_RxDefaultAnt		0x300
-+#define		bRFSW_RxOptionAnt		0x3000
-+#define		bRFSI_3WireData		0x1
-+#define		bRFSI_3WireClock		0x2
-+#define		bRFSI_3WireLoad		0x4
-+#define		bRFSI_3WireRW		0x8
-+#define		bRFSI_3Wire			0xf
-+
-+#define		bRFSI_RFENV               		0x10	/* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
-+
-+#define		bRFSI_TRSW                		0x20	/* Useless now */
-+#define		bRFSI_TRSWB		0x40
-+#define		bRFSI_ANTSW		0x100
-+#define		bRFSI_ANTSWB		0x200
-+#define		bRFSI_PAPE			0x400
-+#define		bRFSI_PAPE5G		0x800
-+#define		bBandSelect			0x1
-+#define		bHTSIG2_GI			0x80
-+#define		bHTSIG2_Smoothing		0x01
-+#define		bHTSIG2_Sounding		0x02
-+#define		bHTSIG2_Aggreaton		0x08
-+#define		bHTSIG2_STBC		0x30
-+#define		bHTSIG2_AdvCoding		0x40
-+#define		bHTSIG2_NumOfHTLTF	0x300
-+#define		bHTSIG2_CRC8		0x3fc
-+#define		bHTSIG1_MCS		0x7f
-+#define		bHTSIG1_BandWidth		0x80
-+#define		bHTSIG1_HTLength		0xffff
-+#define		bLSIG_Rate			0xf
-+#define		bLSIG_Reserved		0x10
-+#define		bLSIG_Length		0x1fffe
-+#define		bLSIG_Parity			0x20
-+#define		bCCKRxPhase		0x4
-+#if (RTL92SE_FPGA_VERIFY == 1)
-+	#define		bLSSIReadAddress          		0x3f000000   /* LSSI "Read" Address	 */ /* Reg 0x824 rFPGA0_XA_HSSIParameter2 */
-+#else
-+	#define		bLSSIReadAddress          		0x7f800000   /* T65 RF */
-+#endif
-+#define		bLSSIReadEdge             		0x80000000   /* LSSI "Read" edge signal */
-+#if (RTL92SE_FPGA_VERIFY == 1)
-+	#define		bLSSIReadBackData         		0xfff		/* Reg 0x8a0 rFPGA0_XA_LSSIReadBack */
-+#else
-+	#define		bLSSIReadBackData         		0xfffff		/* T65 RF */
-+#endif
-+#define		bLSSIReadOKFlag           		0x1000	/* Useless now */
-+#define		bCCKSampleRate            		0x8       /* 0: 44MHz, 1:88MHz      		 */
-+#define		bRegulator0Standby		0x1
-+#define		bRegulatorPLLStandby		0x2
-+#define		bRegulator1Standby		0x4
-+#define		bPLLPowerUp		0x8
-+#define		bDPLLPowerUp		0x10
-+#define		bDA10PowerUp		0x20
-+#define		bAD7PowerUp		0x200
-+#define		bDA6PowerUp		0x2000
-+#define		bXtalPowerUp		0x4000
-+#define		b40MDClkPowerUP		0x8000
-+#define		bDA6DebugMode		0x20000
-+#define		bDA6Swing			0x380000
-+
-+#define		bADClkPhase               		0x4000000	/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
-+
-+#define		b80MClkDelay              		0x18000000	/* Useless */
-+#define		bAFEWatchDogEnable		0x20000000
-+
-+#define		bXtalCap01                			0xc0000000	/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
-+#define		bXtalCap23			0x3
-+#define		bXtalCap92x					0x0f000000
-+#define		bXtalCap			0x0f000000
-+
-+#define		bIntDifClkEnable          		0x400	/* Useless */
-+#define		bExtSigClkEnable		0x800
-+#define		bBandgapMbiasPowerUp	0x10000
-+#define		bAD11SHGain		0xc0000
-+#define		bAD11InputRange		0x700000
-+#define		bAD11OPCurrent		0x3800000
-+#define		bIPathLoopback		0x4000000
-+#define		bQPathLoopback		0x8000000
-+#define		bAFELoopback		0x10000000
-+#define		bDA10Swing		0x7e0
-+#define		bDA10Reverse		0x800
-+#define		bDAClkSource		0x1000
-+#define		bAD7InputRange		0x6000
-+#define		bAD7Gain			0x38000
-+#define		bAD7OutputCMMode		0x40000
-+#define		bAD7InputCMMode		0x380000
-+#define		bAD7Current			0xc00000
-+#define		bRegulatorAdjust		0x7000000
-+#define		bAD11PowerUpAtTx		0x1
-+#define		bDA10PSAtTx		0x10
-+#define		bAD11PowerUpAtRx		0x100
-+#define		bDA10PSAtRx		0x1000
-+#define		bCCKRxAGCFormat		0x200
-+#define		bPSDFFTSamplepPoint		0xc000
-+#define		bPSDAverageNum		0x3000
-+#define		bIQPathControl		0xc00
-+#define		bPSDFreq			0x3ff
-+#define		bPSDAntennaPath		0x30
-+#define		bPSDIQSwitch		0x40
-+#define		bPSDRxTrigger		0x400000
-+#define		bPSDTxTrigger		0x80000000
-+#define		bPSDSineToneScale		0x7f000000
-+#define		bPSDReport			0xffff
-+
-+/* 3. Page9(0x900) */
-+#define		bOFDMTxSC                 		0x30000000	/* Useless */
-+#define		bCCKTxOn			0x1
-+#define		bOFDMTxOn		0x2
-+#define		bDebugPage                		0xfff  /* reset debug page and also HWord, LWord */
-+#define		bDebugItem                		0xff   /* reset debug page and LWord */
-+#define		bAntL			0x10
-+#define		bAntNonHT				0x100
-+#define		bAntHT1			0x1000
-+#define		bAntHT2			0x10000
-+#define		bAntHT1S1			0x100000
-+#define		bAntNonHTS1		0x1000000
-+
-+/* 4. PageA(0xA00) */
-+#define		bCCKBBMode                		0x3	/* Useless */
-+#define		bCCKTxPowerSaving		0x80
-+#define		bCCKRxPowerSaving		0x40
-+
-+#define		bCCKSideBand              		0x10	/* Reg 0xa00 rCCK0_System 20/40 switch */
-+
-+#define		bCCKScramble              		0x8	/* Useless */
-+#define		bCCKAntDiversity			0x8000
-+#define		bCCKCarrierRecovery		0x4000
-+#define		bCCKTxRate			0x3000
-+#define		bCCKDCCancel		0x0800
-+#define		bCCKISICancel		0x0400
-+#define		bCCKMatchFilter		0x0200
-+#define		bCCKEqualizer		0x0100
-+#define		bCCKPreambleDetect		0x800000
-+#define		bCCKFastFalseCCA		0x400000
-+#define		bCCKChEstStart		0x300000
-+#define		bCCKCCACount		0x080000
-+#define		bCCKcs_lim			0x070000
-+#define		bCCKBistMode		0x80000000
-+#define		bCCKCCAMask		0x40000000
-+#define		bCCKTxDACPhase		0x4
-+#define		bCCKRxADCPhase         	   	0x20000000   /* r_rx_clk */
-+#define		bCCKr_cp_mode0		0x0100
-+#define		bCCKTxDCOffset		0xf0
-+#define		bCCKRxDCOffset		0xf
-+#define		bCCKCCAMode		0xc000
-+#define		bCCKFalseCS_lim		0x3f00
-+#define		bCCKCS_ratio		0xc00000
-+#define		bCCKCorgBit_sel		0x300000
-+#define		bCCKPD_lim			0x0f0000
-+#define		bCCKNewCCA		0x80000000
-+#define		bCCKRxHPofIG		0x8000
-+#define		bCCKRxIG			0x7f00
-+#define		bCCKLNAPolarity		0x800000
-+#define		bCCKRx1stGain		0x7f0000
-+#define		bCCKRFExtend              		0x20000000 /* CCK Rx Iinital gain polarity */
-+#define		bCCKRxAGCSatLevel		0x1f000000
-+#define		bCCKRxAGCSatCount		0xe0
-+#define		bCCKRxRFSettle            		0x1f       /* AGCsamp_dly */
-+#define		bCCKFixedRxAGC		0x8000
-+/* #define bCCKRxAGCFormat		0x4000 */   /* remove to HSSI register 0x824 */
-+#define		bCCKAntennaPolarity		0x2000
-+#define		bCCKTxFilterType		0x0c00
-+#define		bCCKRxAGCReportType		0x0300
-+#define		bCCKRxDAGCEn		0x80000000
-+#define		bCCKRxDAGCPeriod		0x20000000
-+#define		bCCKRxDAGCSatLevel		0x1f000000
-+#define		bCCKTimingRecovery		0x800000
-+#define		bCCKTxC0			0x3f0000
-+#define		bCCKTxC1			0x3f000000
-+#define		bCCKTxC2			0x3f
-+#define		bCCKTxC3			0x3f00
-+#define		bCCKTxC4			0x3f0000
-+#define		bCCKTxC5			0x3f000000
-+#define		bCCKTxC6			0x3f
-+#define		bCCKTxC7			0x3f00
-+#define		bCCKDebugPort		0xff0000
-+#define		bCCKDACDebug		0x0f000000
-+#define		bCCKFalseAlarmEnable		0x8000
-+#define		bCCKFalseAlarmRead		0x4000
-+#define		bCCKTRSSI			0x7f
-+#define		bCCKRxAGCReport		0xfe
-+#define		bCCKRxReport_AntSel		0x80000000
-+#define		bCCKRxReport_MFOff		0x40000000
-+#define		bCCKRxRxReport_SQLoss	0x20000000
-+#define		bCCKRxReport_Pktloss		0x10000000
-+#define		bCCKRxReport_Lockedbit	0x08000000
-+#define		bCCKRxReport_RateError	0x04000000
-+#define		bCCKRxReport_RxRate		0x03000000
-+#define		bCCKRxFACounterLower	0xff
-+#define		bCCKRxFACounterUpper	0xff000000
-+#define		bCCKRxHPAGCStart		0xe000
-+#define		bCCKRxHPAGCFinal		0x1c00
-+#define		bCCKRxFalseAlarmEnable	0x8000
-+#define		bCCKFACounterFreeze		0x4000
-+#define		bCCKTxPathSel		0x10000000
-+#define		bCCKDefaultRxPath		0xc000000
-+#define		bCCKOptionRxPath		0x3000000
-+
-+/* 5. PageC(0xC00) */
-+#define		bNumOfSTF                			0x3	/* Useless */
-+#define		bShift_L			0xc0
-+#define		bGI_TH			0xc
-+#define		bRxPathA			0x1
-+#define		bRxPathB			0x2
-+#define		bRxPathC			0x4
-+#define		bRxPathD			0x8
-+#define		bTxPathA			0x1
-+#define		bTxPathB			0x2
-+#define		bTxPathC			0x4
-+#define		bTxPathD			0x8
-+#define		bTRSSIFreq			0x200
-+#define		bADCBackoff			0x3000
-+#define		bDFIRBackoff			0xc000
-+#define		bTRSSILatchPhase		0x10000
-+#define		bRxIDCOffset			0xff
-+#define		bRxQDCOffset			0xff00
-+#define		bRxDFIRMode		0x1800000
-+#define		bRxDCNFType		0xe000000
-+#define		bRXIQImb_A			0x3ff
-+#define		bRXIQImb_B			0xfc00
-+#define		bRXIQImb_C			0x3f0000
-+#define		bRXIQImb_D			0xffc00000
-+#define		bDC_dc_Notch		0x60000
-+#define		bRxNBINotch			0x1f000000
-+#define		bPD_TH			0xf
-+#define		bPD_TH_Opt2		0xc000
-+#define		bPWED_TH			0x700
-+#define		bIfMF_Win_L			0x800
-+#define		bPD_Option			0x1000
-+#define		bMF_Win_L			0xe000
-+#define		bBW_Search_L		0x30000
-+#define		bwin_enh_L			0xc0000
-+#define		bBW_TH			0x700000
-+#define		bED_TH2			0x3800000
-+#define		bBW_option			0x4000000
-+#define		bRatio_TH			0x18000000
-+#define		bWindow_L			0xe0000000
-+#define		bSBD_Option			0x1
-+#define		bFrame_TH			0x1c
-+#define		bFS_Option			0x60
-+#define		bDC_Slope_check		0x80
-+#define		bFGuard_Counter_DC_L		0xe00
-+#define		bFrame_Weight_Short		0x7000
-+#define		bSub_Tune			0xe00000
-+#define		bFrame_DC_Length		0xe000000
-+#define		bSBD_start_offset		0x30000000
-+#define		bFrame_TH_2		0x7
-+#define		bFrame_GI2_TH		0x38
-+#define		bGI2_Sync_en		0x40
-+#define		bSarch_Short_Early		0x300
-+#define		bSarch_Short_Late		0xc00
-+#define		bSarch_GI2_Late		0x70000
-+#define		bCFOAntSum		0x1
-+#define		bCFOAcc			0x2
-+#define		bCFOStartOffset		0xc
-+#define		bCFOLookBack		0x70
-+#define		bCFOSumWeight		0x80
-+#define		bDAGCEnable			0x10000
-+#define		bTXIQImb_A			0x3ff
-+#define		bTXIQImb_B			0xfc00
-+#define		bTXIQImb_C			0x3f0000
-+#define		bTXIQImb_D			0xffc00000
-+#define		bTxIDCOffset			0xff
-+#define		bTxQDCOffset			0xff00
-+#define		bTxDFIRMode		0x10000
-+#define		bTxPesudoNoiseOn		0x4000000
-+#define		bTxPesudoNoise_A		0xff
-+#define		bTxPesudoNoise_B		0xff00
-+#define		bTxPesudoNoise_C		0xff0000
-+#define		bTxPesudoNoise_D		0xff000000
-+#define		bCCADropOption		0x20000
-+#define		bCCADropThres		0xfff00000
-+#define		bEDCCA_H			0xf
-+#define		bEDCCA_L			0xf0
-+#define		bLambda_ED               0x300
-+#define		bRxInitialGain           0x7f
-+#define		bRxAntDivEn              0x80
-+#define		bRxAGCAddressForLNA      0x7f00
-+#define		bRxHighPowerFlow         0x8000
-+#define		bRxAGCFreezeThres        0xc0000
-+#define		bRxFreezeStep_AGC1       0x300000
-+#define		bRxFreezeStep_AGC2       0xc00000
-+#define		bRxFreezeStep_AGC3       0x3000000
-+#define		bRxFreezeStep_AGC0       0xc000000
-+#define		bRxRssi_Cmp_En           0x10000000
-+#define		bRxQuickAGCEn            0x20000000
-+#define		bRxAGCFreezeThresMode    0x40000000
-+#define		bRxOverFlowCheckType     0x80000000
-+#define		bRxAGCShift              0x7f
-+#define		bTRSW_Tri_Only           0x80
-+#define		bPowerThres              0x300
-+#define		bRxAGCEn                 0x1
-+#define		bRxAGCTogetherEn         0x2
-+#define		bRxAGCMin                0x4
-+#define		bRxHP_Ini                0x7
-+#define		bRxHP_TRLNA              0x70
-+#define		bRxHP_RSSI               0x700
-+#define		bRxHP_BBP1               0x7000
-+#define		bRxHP_BBP2               0x70000
-+#define		bRxHP_BBP3               0x700000
-+#define		bRSSI_H                  0x7f0000     /* the threshold for high power */
-+#define		bRSSI_Gen                0x7f000000   /* the threshold for ant diversity */
-+#define		bRxSettle_TRSW           0x7
-+#define		bRxSettle_LNA            0x38
-+#define		bRxSettle_RSSI           0x1c0
-+#define		bRxSettle_BBP            0xe00
-+#define		bRxSettle_RxHP           0x7000
-+#define		bRxSettle_AntSW_RSSI     0x38000
-+#define		bRxSettle_AntSW          0xc0000
-+#define		bRxProcessTime_DAGC      0x300000
-+#define		bRxSettle_HSSI           0x400000
-+#define		bRxProcessTime_BBPPW     0x800000
-+#define		bRxAntennaPowerShift     0x3000000
-+#define		bRSSITableSelect         0xc000000
-+#define		bRxHP_Final              0x7000000
-+#define		bRxHTSettle_BBP          0x7
-+#define		bRxHTSettle_HSSI         0x8
-+#define		bRxHTSettle_RxHP         0x70
-+#define		bRxHTSettle_BBPPW        0x80
-+#define		bRxHTSettle_Idle         0x300
-+#define		bRxHTSettle_Reserved     0x1c00
-+#define		bRxHTRxHPEn              0x8000
-+#define		bRxHTAGCFreezeThres      0x30000
-+#define		bRxHTAGCTogetherEn       0x40000
-+#define		bRxHTAGCMin              0x80000
-+#define		bRxHTAGCEn               0x100000
-+#define		bRxHTDAGCEn              0x200000
-+#define		bRxHTRxHP_BBP            0x1c00000
-+#define		bRxHTRxHP_Final          0xe0000000
-+#define		bRxPWRatioTH             0x3
-+#define		bRxPWRatioEn             0x4
-+#define		bRxMFHold                0x3800
-+#define		bRxPD_Delay_TH1          0x38
-+#define		bRxPD_Delay_TH2          0x1c0
-+#define		bRxPD_DC_COUNT_MAX       0x600
-+/* #define bRxMF_Hold               0x3800 */
-+#define		bRxPD_Delay_TH           0x8000
-+#define		bRxProcess_Delay         0xf0000
-+#define		bRxSearchrange_GI2_Early 0x700000
-+#define		bRxFrame_Guard_Counter_L 0x3800000
-+#define		bRxSGI_Guard_L           0xc000000
-+#define		bRxSGI_Search_L          0x30000000
-+#define		bRxSGI_TH                0xc0000000
-+#define		bDFSCnt0                 0xff
-+#define		bDFSCnt1                 0xff00
-+#define		bDFSFlag                 0xf0000
-+#define		bMFWeightSum             0x300000
-+#define		bMinIdxTH                0x7f000000
-+#define		bDAFormat                0x40000
-+#define		bTxChEmuEnable           0x01000000
-+#define		bTRSWIsolation_A         0x7f
-+#define		bTRSWIsolation_B         0x7f00
-+#define		bTRSWIsolation_C         0x7f0000
-+#define		bTRSWIsolation_D         0x7f000000
-+#define		bExtLNAGain              0x7c00
-+
-+/* 6. PageE(0xE00) */
-+#define		bSTBCEn                  0x4	/* Useless */
-+#define		bAntennaMapping          0x10
-+#define		bNss                     0x20
-+#define		bCFOAntSumD              0x200
-+#define		bPHYCounterReset         0x8000000
-+#define		bCFOReportGet            0x4000000
-+#define		bOFDMContinueTx          0x10000000
-+#define		bOFDMSingleCarrier       0x20000000
-+#define		bOFDMSingleTone          0x40000000
-+/* #define bRxPath1                 0x01 */
-+/* #define bRxPath2                 0x02 */
-+/* #define bRxPath3                 0x04 */
-+/* #define bRxPath4                 0x08 */
-+/* #define bTxPath1                 0x10 */
-+/* #define bTxPath2                 0x20 */
-+#define		bHTDetect                0x100
-+#define		bCFOEn                   0x10000
-+#define		bCFOValue                0xfff00000
-+#define		bSigTone_Re              0x3f
-+#define		bSigTone_Im              0x7f00
-+#define		bCounter_CCA             0xffff
-+#define		bCounter_ParityFail      0xffff0000
-+#define		bCounter_RateIllegal     0xffff
-+#define		bCounter_CRC8Fail        0xffff0000
-+#define		bCounter_MCSNoSupport    0xffff
-+#define		bCounter_FastSync        0xffff
-+#define		bShortCFO                0xfff
-+#define		bShortCFOTLength         12   /* total */
-+#define		bShortCFOFLength         11   /* fraction */
-+#define		bLongCFO                 0x7ff
-+#define		bLongCFOTLength          11
-+#define		bLongCFOFLength          11
-+#define		bTailCFO                 0x1fff
-+#define		bTailCFOTLength          13
-+#define		bTailCFOFLength          12
-+#define		bmax_en_pwdB             0xffff
-+#define		bCC_power_dB             0xffff0000
-+#define		bnoise_pwdB              0xffff
-+#define		bPowerMeasTLength        10
-+#define		bPowerMeasFLength        3
-+#define		bRx_HT_BW                0x1
-+#define		bRxSC                    0x6
-+#define		bRx_HT                   0x8
-+#define		bNB_intf_det_on          0x1
-+#define		bIntf_win_len_cfg        0x30
-+#define		bNB_Intf_TH_cfg          0x1c0
-+#define		bRFGain                  0x3f
-+#define		bTableSel                0x40
-+#define		bTRSW                    0x80
-+#define		bRxSNR_A                 0xff
-+#define		bRxSNR_B                 0xff00
-+#define		bRxSNR_C                 0xff0000
-+#define		bRxSNR_D                 0xff000000
-+#define		bSNREVMTLength           8
-+#define		bSNREVMFLength           1
-+#define		bCSI1st                  0xff
-+#define		bCSI2nd                  0xff00
-+#define		bRxEVM1st                0xff0000
-+#define		bRxEVM2nd                0xff000000
-+#define		bSIGEVM                  0xff
-+#define		bPWDB                    0xff00
-+#define		bSGIEN                   0x10000
-+
-+#define		bSFactorQAM1             0xf	/* Useless */
-+#define		bSFactorQAM2             0xf0
-+#define		bSFactorQAM3             0xf00
-+#define		bSFactorQAM4             0xf000
-+#define		bSFactorQAM5             0xf0000
-+#define		bSFactorQAM6             0xf0000
-+#define		bSFactorQAM7             0xf00000
-+#define		bSFactorQAM8             0xf000000
-+#define		bSFactorQAM9             0xf0000000
-+#define		bCSIScheme               0x100000
-+
-+#define		bNoiseLvlTopSet          0x3	/* Useless */
-+#define		bChSmooth                0x4
-+#define		bChSmoothCfg1            0x38
-+#define		bChSmoothCfg2            0x1c0
-+#define		bChSmoothCfg3            0xe00
-+#define		bChSmoothCfg4            0x7000
-+#define		bMRCMode                 0x800000
-+#define		bTHEVMCfg                0x7000000
-+
-+#define		bLoopFitType             0x1	/* Useless */
-+#define		bUpdCFO                  0x40
-+#define		bUpdCFOOffData           0x80
-+#define		bAdvUpdCFO               0x100
-+#define		bAdvTimeCtrl             0x800
-+#define		bUpdClko                 0x1000
-+#define		bFC                      0x6000
-+#define		bTrackingMode            0x8000
-+#define		bPhCmpEnable             0x10000
-+#define		bUpdClkoLTF              0x20000
-+#define		bComChCFO                0x40000
-+#define		bCSIEstiMode             0x80000
-+#define		bAdvUpdEqz               0x100000
-+#define		bUChCfg                  0x7000000
-+#define		bUpdEqz                  0x8000000
-+
-+#define		bTxAGCRate18_06			0x7f7f7f7f	/* Useless */
-+#define		bTxAGCRate54_24			0x7f7f7f7f
-+#define		bTxAGCRateMCS32			0x7f
-+#define		bTxAGCRateCCK			0x7f00
-+#define		bTxAGCRateMCS3_MCS0		0x7f7f7f7f
-+#define		bTxAGCRateMCS7_MCS4		0x7f7f7f7f
-+#define		bTxAGCRateMCS11_MCS8	0x7f7f7f7f
-+#define		bTxAGCRateMCS15_MCS12	0x7f7f7f7f
-+
-+/* Rx Pseduo noise */
-+#define		bRxPesudoNoiseOn         0x20000000	/* Useless */
-+#define		bRxPesudoNoise_A         0xff
-+#define		bRxPesudoNoise_B         0xff00
-+#define		bRxPesudoNoise_C         0xff0000
-+#define		bRxPesudoNoise_D         0xff000000
-+#define		bPesudoNoiseState_A      0xffff
-+#define		bPesudoNoiseState_B      0xffff0000
-+#define		bPesudoNoiseState_C      0xffff
-+#define		bPesudoNoiseState_D      0xffff0000
-+
-+/* 7. RF Register
-+ * Zebra1 */
-+#define		bZebra1_HSSIEnable        0x8		/* Useless */
-+#define		bZebra1_TRxControl        0xc00
-+#define		bZebra1_TRxGainSetting    0x07f
-+#define		bZebra1_RxCorner          0xc00
-+#define		bZebra1_TxChargePump      0x38
-+#define		bZebra1_RxChargePump      0x7
-+#define		bZebra1_ChannelNum        0xf80
-+#define		bZebra1_TxLPFBW           0x400
-+#define		bZebra1_RxLPFBW           0x600
-+
-+/* Zebra4 */
-+#define		bRTL8256RegModeCtrl1      0x100	/* Useless */
-+#define		bRTL8256RegModeCtrl0      0x40
-+#define		bRTL8256_TxLPFBW          0x18
-+#define		bRTL8256_RxLPFBW          0x600
-+
-+/* RTL8258 */
-+#define		bRTL8258_TxLPFBW          0xc	/* Useless */
-+#define		bRTL8258_RxLPFBW          0xc00
-+#define		bRTL8258_RSSILPFBW        0xc0
-+
-+
-+/*
-+ * Other Definition
-+ *   */
-+
-+/* byte endable for sb_write */
-+#define		bByte0                    0x1	/* Useless */
-+#define		bByte1                    0x2
-+#define		bByte2                    0x4
-+#define		bByte3                    0x8
-+#define		bWord0                    0x3
-+#define		bWord1                    0xc
-+#define		bDWord                    0xf
-+
-+/* for PutRegsetting & GetRegSetting BitMask */
-+#define		bMaskByte0		0xff	/* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
-+#define		bMaskByte1		0xff00
-+#define		bMaskByte2		0xff0000
-+#define		bMaskByte3		0xff000000
-+#define		bMaskHWord	0xffff0000
-+#define		bMaskLWord		0x0000ffff
-+#define		bMaskDWord	0xffffffff
-+#define		bMaskH4Bits		0xf0000000
-+#define		bMaskH3Bytes	0xffffff00
-+#define		bMaskOFDM_D	0xffc00000
-+#define		bMaskCCK		0x3f3f3f3f
-+#define		bMask12Bits		0xfff
-+
-+/* for PutRFRegsetting & GetRFRegSetting BitMask */
-+#if (RTL92SE_FPGA_VERIFY == 1)
-+/* #define		bMask12Bits               0xfff */	/* RF Reg mask bits */
-+/* #define		bMask20Bits               0xfff */	/* RF Reg mask bits T65 RF */
-+#define		bRFRegOffsetMask	0xfff
-+#else
-+/* #define		bMask12Bits               0xfffff */	/* RF Reg mask bits */
-+/* #define		bMask20Bits               0xfffff */	/* RF Reg mask bits T65 RF */
-+#define		bRFRegOffsetMask	0xfffff
-+#endif
-+#define		bEnable                   0x1	/* Useless */
-+#define		bDisable                  0x0
-+
-+#define		LeftAntenna               0x0	/* Useless */
-+#define		RightAntenna              0x1
-+
-+#define		tCheckTxStatus            500   /* 500ms */ /* Useless */
-+#define		tUpdateRxCounter          100   /* 100ms */
-+
-+#define		rateCCK     0	/* Useless */
-+#define		rateOFDM    1
-+#define		rateHT      2
-+
-+/* define Register-End */
-+#define		bPMAC_End                 0x1ff	/* Useless */
-+#define		bFPGAPHY0_End             0x8ff
-+#define		bFPGAPHY1_End             0x9ff
-+#define		bCCKPHY0_End              0xaff
-+#define		bOFDMPHY0_End             0xcff
-+#define		bOFDMPHY1_End             0xdff
-+
-+/* define max debug item in each debug page
-+ * #define bMaxItem_FPGA_PHY0        0x9
-+ * #define bMaxItem_FPGA_PHY1        0x3
-+ * #define bMaxItem_PHY_11B          0x16
-+ * #define bMaxItem_OFDM_PHY0        0x29
-+ * #define bMaxItem_OFDM_PHY1        0x0 */
-+
-+#define		bPMACControl	0x0		/* Useless */
-+#define		bWMACControl	0x1
-+#define		bWNICControl	0x2
-+
-+#if 0
-+#define		ANTENNA_A	0x1	/* Useless */
-+#define		ANTENNA_B	0x2
-+#define		ANTENNA_AB	0x3	/* ANTENNA_A | ANTENNA_B */
-+
-+#define		ANTENNA_C	0x4
-+#define		ANTENNA_D	0x8
-+#endif
-+
-+#define RCR_AAP			BIT(0)				/* accept all physical address */
-+#define RCR_APM			BIT(1)				/* accept physical match */
-+#define RCR_AM			BIT(2)				/* accept multicast */
-+#define RCR_AB			BIT(3)				/* accept broadcast */
-+#define RCR_ACRC32		BIT(5)				/* accept error packet */
-+#define RCR_9356SEL		BIT(6)
-+#define RCR_AICV		BIT(9)				/* Accept ICV error packet */
-+#define RCR_RXFTH0		(BIT(13) | BIT(14) | BIT(15))	/* Rx FIFO threshold */
-+#define RCR_ADF			BIT(18)				/* Accept Data(frame type) frame */
-+#define RCR_ACF			BIT(19)				/* Accept control frame */
-+#define RCR_AMF			BIT(20)				/* Accept management frame */
-+#define RCR_ADD3		BIT(21)
-+#define RCR_APWRMGT		BIT(22)				/* Accept power management packet */
-+#define RCR_CBSSID		BIT(23)				/* Accept BSSID match packet */
-+#define RCR_ENMARP		BIT(28)				/* enable mac auto reset phy */
-+#define RCR_EnCS1		BIT(29)				/* enable carrier sense method 1 */
-+#define RCR_EnCS2		BIT(30)				/* enable carrier sense method 2 */
-+#define RCR_OnlyErlPkt		BIT(31)				/* Rx Early mode is performed for packet size greater than 1536 */
-+
-+/*--------------------------Define Parameters-------------------------------*/
-+
-+
-+#endif /* __INC_HAL8192SPHYREG_H */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_odm.h b/drivers/staging/rtl8723cs/include/rtw_odm.h
-new file mode 100644
-index 000000000000..515b9583be39
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_odm.h
-@@ -0,0 +1,103 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_ODM_H__
-+#define __RTW_ODM_H__
-+
-+#include <drv_types.h>
-+#include "../hal/phydm/phydm_types.h"
-+/*
-+* This file provides utilities/wrappers for rtw driver to use ODM
-+*/
-+typedef enum _HAL_PHYDM_OPS {
-+	HAL_PHYDM_DIS_ALL_FUNC,
-+	HAL_PHYDM_FUNC_SET,
-+	HAL_PHYDM_FUNC_CLR,
-+	HAL_PHYDM_ABILITY_BK,
-+	HAL_PHYDM_ABILITY_RESTORE,
-+	HAL_PHYDM_ABILITY_SET,
-+	HAL_PHYDM_ABILITY_GET,
-+} HAL_PHYDM_OPS;
-+
-+
-+#define DYNAMIC_FUNC_DISABLE		(0x0)
-+	u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability);
-+
-+#define rtw_phydm_func_disable_all(adapter)	\
-+		rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0)
-+
-+#ifdef CONFIG_RTW_ACS
-+#define rtw_phydm_func_for_offchannel(adapter) \
-+		do { \
-+			rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \
-+			if (rtw_odm_adaptivity_needed(adapter)) \
-+				rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \
-+			if (IS_ACS_ENABLE(adapter))\
-+				rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ENV_MONITOR); \
-+		} while (0)
-+#else
-+#define rtw_phydm_func_for_offchannel(adapter) \
-+		do { \
-+			rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \
-+			if (rtw_odm_adaptivity_needed(adapter)) \
-+				rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \
-+		} while (0)
-+#endif
-+
-+#define rtw_phydm_func_clr(adapter, ability)	\
-+		rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_CLR, ability)
-+
-+#define rtw_phydm_ability_backup(adapter)	\
-+		rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_BK, 0)
-+
-+#define rtw_phydm_ability_restore(adapter)	\
-+		rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_RESTORE, 0)
-+
-+
-+static inline u32 rtw_phydm_ability_get(_adapter *adapter)
-+{
-+	return rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_GET, 0);
-+}
-+
-+
-+void rtw_odm_init_ic_type(_adapter *adapter);
-+
-+void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter);
-+
-+bool rtw_odm_adaptivity_needed(_adapter *adapter);
-+void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter);
-+void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff);
-+void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter);
-+void rtw_odm_acquirespinlock(_adapter *adapter,	enum rt_spinlock_type type);
-+void rtw_odm_releasespinlock(_adapter *adapter,	enum rt_spinlock_type type);
-+
-+struct dm_struct;
-+s16 rtw_odm_get_tx_power_mbm(struct dm_struct *dm, u8 rfpath, u8 rate, u8 bw, u8 cch);
-+
-+#ifdef CONFIG_DFS_MASTER
-+void rtw_odm_radar_detect_reset(_adapter *adapter);
-+void rtw_odm_radar_detect_disable(_adapter *adapter);
-+void rtw_odm_radar_detect_enable(_adapter *adapter);
-+BOOLEAN rtw_odm_radar_detect(_adapter *adapter);
-+void rtw_odm_update_dfs_region(struct dvobj_priv *dvobj);
-+u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj);
-+#endif /* CONFIG_DFS_MASTER */
-+
-+void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys);
-+
-+#if defined(CONFIG_RTL8822C) && defined(CONFIG_LPS_PG)
-+void odm_lps_pg_debug_8822c(void *dm_void);
-+#endif
-+
-+#endif /* __RTW_ODM_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_p2p.h b/drivers/staging/rtl8723cs/include/rtw_p2p.h
-new file mode 100644
-index 000000000000..8d929ad61c43
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_p2p.h
-@@ -0,0 +1,167 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_P2P_H_
-+#define __RTW_P2P_H_
-+
-+
-+u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
-+u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
-+u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 *pssid, u8 ussidlen, u8 *pdev_raddr);
-+u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code);
-+u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
-+#ifdef CONFIG_WFD
-+int rtw_init_wifi_display_info(_adapter *padapter);
-+void rtw_wfd_enable(_adapter *adapter, bool on);
-+void rtw_wfd_set_ctrl_port(_adapter *adapter, u16 port);
-+void rtw_tdls_wfd_enable(_adapter *adapter, bool on);
-+
-+u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
-+u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled);
-+u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
-+u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
-+u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
-+u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
-+u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
-+u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
-+u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
-+u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
-+u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
-+u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf);
-+
-+u32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf);
-+u32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf);
-+u32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf);
-+u32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf);
-+u32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf);
-+#endif /*CONFIG_WFD */
-+
-+void rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe);
-+
-+u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
-+u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta);
-+u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
-+u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
-+u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo,  u8 *pframe, uint len);
-+u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo,  u8 *pframe);
-+u8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
-+u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
-+u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
-+u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len);
-+int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength);
-+
-+s32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf);
-+
-+#ifdef CONFIG_P2P_PS
-+void	process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength);
-+void	p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state);
-+u8	p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue);
-+#endif /* CONFIG_P2P_PS */
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx);
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+void reset_global_wifidirect_info(_adapter *padapter);
-+void rtw_init_wifidirect_timers(_adapter *padapter);
-+void rtw_init_wifidirect_addrs(_adapter *padapter, u8 *dev_addr, u8 *iface_addr);
-+void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role);
-+int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role);
-+
-+static inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
-+{
-+	if (wdinfo->p2p_state != state) {
-+		/* wdinfo->pre_p2p_state = wdinfo->p2p_state; */
-+		wdinfo->p2p_state = state;
-+	}
-+}
-+static inline void _rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
-+{
-+	if (wdinfo->pre_p2p_state != state)
-+		wdinfo->pre_p2p_state = state;
-+}
-+#if 0
-+static inline void _rtw_p2p_restore_state(struct wifidirect_info *wdinfo)
-+{
-+	if (wdinfo->pre_p2p_state != -1) {
-+		wdinfo->p2p_state = wdinfo->pre_p2p_state;
-+		wdinfo->pre_p2p_state = -1;
-+	}
-+}
-+#endif
-+void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role);
-+
-+static inline int _rtw_p2p_state(struct wifidirect_info *wdinfo)
-+{
-+	return wdinfo->p2p_state;
-+}
-+static inline int _rtw_p2p_pre_state(struct wifidirect_info *wdinfo)
-+{
-+	return wdinfo->pre_p2p_state;
-+}
-+static inline int _rtw_p2p_role(struct wifidirect_info *wdinfo)
-+{
-+	return wdinfo->role;
-+}
-+static inline bool _rtw_p2p_chk_state(struct wifidirect_info *wdinfo, enum P2P_STATE state)
-+{
-+	return wdinfo->p2p_state == state;
-+}
-+static inline bool _rtw_p2p_chk_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role)
-+{
-+	return wdinfo->role == role;
-+}
-+
-+#ifdef CONFIG_DBG_P2P
-+void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line);
-+void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line);
-+/* void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line); */
-+void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line);
-+#define rtw_p2p_set_state(wdinfo, state) dbg_rtw_p2p_set_state(wdinfo, state, __FUNCTION__, __LINE__)
-+#define rtw_p2p_set_pre_state(wdinfo, state) dbg_rtw_p2p_set_pre_state(wdinfo, state, __FUNCTION__, __LINE__)
-+#define rtw_p2p_set_role(wdinfo, role) dbg_rtw_p2p_set_role(wdinfo, role, __FUNCTION__, __LINE__)
-+/* #define rtw_p2p_restore_state(wdinfo) dbg_rtw_p2p_restore_state(wdinfo, __FUNCTION__, __LINE__) */
-+#else /* CONFIG_DBG_P2P */
-+#define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state)
-+#define rtw_p2p_set_pre_state(wdinfo, state) _rtw_p2p_set_pre_state(wdinfo, state)
-+#define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role)
-+/* #define rtw_p2p_restore_state(wdinfo) _rtw_p2p_restore_state(wdinfo) */
-+#endif /* CONFIG_DBG_P2P */
-+
-+#define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo)
-+#define rtw_p2p_pre_state(wdinfo) _rtw_p2p_pre_state(wdinfo)
-+#define rtw_p2p_role(wdinfo) _rtw_p2p_role(wdinfo)
-+#define rtw_p2p_chk_state(wdinfo, state) _rtw_p2p_chk_state(wdinfo, state)
-+#define rtw_p2p_chk_role(wdinfo, role) _rtw_p2p_chk_role(wdinfo, role)
-+
-+#define rtw_p2p_findphase_ex_set(wdinfo, value) \
-+	(wdinfo)->find_phase_state_exchange_cnt = (value)
-+
-+#ifdef CONFIG_P2P
-+/* is this find phase exchange for social channel scan? */
-+#define rtw_p2p_findphase_ex_is_social(wdinfo)   \
-+	(wdinfo)->find_phase_state_exchange_cnt >= P2P_FINDPHASE_EX_SOCIAL_FIRST
-+
-+/* should we need find phase exchange anymore? */
-+#define rtw_p2p_findphase_ex_is_needed(wdinfo) \
-+	((wdinfo)->find_phase_state_exchange_cnt < P2P_FINDPHASE_EX_MAX && \
-+	 (wdinfo)->find_phase_state_exchange_cnt != P2P_FINDPHASE_EX_NONE && \
-+	 !(wdinfo)->rx_invitereq_info.scan_op_ch_only && \
-+	 !(wdinfo)->p2p_info.scan_op_ch_only)
-+#else
-+#define rtw_p2p_findphase_ex_is_social(wdinfo) 0
-+#define rtw_p2p_findphase_ex_is_needed(wdinfo) 0
-+#endif /* CONFIG_P2P */
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtw_pwrctrl.h b/drivers/staging/rtl8723cs/include/rtw_pwrctrl.h
-new file mode 100644
-index 000000000000..38bad0a51d33
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_pwrctrl.h
-@@ -0,0 +1,772 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_PWRCTRL_H_
-+#define __RTW_PWRCTRL_H_
-+
-+
-+#define FW_PWR0	0
-+#define FW_PWR1	1
-+#define FW_PWR2	2
-+#define FW_PWR3	3
-+
-+
-+#define HW_PWR0	7
-+#define HW_PWR1	6
-+#define HW_PWR2	2
-+#define HW_PWR3	0
-+#define HW_PWR4	8
-+
-+#define FW_PWRMSK	0x7
-+
-+
-+#define XMIT_ALIVE	BIT(0)
-+#define RECV_ALIVE	BIT(1)
-+#define CMD_ALIVE	BIT(2)
-+#define EVT_ALIVE	BIT(3)
-+#ifdef CONFIG_BT_COEXIST
-+#define BTCOEX_ALIVE	BIT(4)
-+#endif /* CONFIG_BT_COEXIST */
-+#define LPS_ALIVE	BIT(5)
-+
-+#ifdef CONFIG_WOWLAN
-+	#ifdef CONFIG_PLATFORM_ANDROID_INTEL_X86
-+		/* TCP/ICMP/UDP multicast with specific IP addr */
-+		#define DEFAULT_PATTERN_NUM 4
-+	#else
-+		/* TCP/ICMP */
-+		#define DEFAULT_PATTERN_NUM 3
-+	#endif
-+
-+#ifdef CONFIG_WOW_PATTERN_HW_CAM	/* Frame Mask Cam number for pattern match */
-+#define MAX_WKFM_CAM_NUM	12
-+#else
-+#define MAX_WKFM_CAM_NUM	16
-+#endif
-+
-+#define MAX_WKFM_SIZE	16 /* (16 bytes for WKFM bit mask, 16*8 = 128 bits) */
-+#define MAX_WKFM_PATTERN_SIZE	128
-+#define MAX_IN_PATTERN_SIZE		512
-+
-+/*
-+ * MAX_WKFM_PATTERN_STR_LEN : the max. length of wow pattern string
-+ *	e.g. echo 00:01:02:...:7f > /proc/net/rtl88x2bu/wlan0/wow_pattern_info
-+ *	- each byte of pattern is represented as 2-bytes ascii : MAX_WKFM_PATTERN_SIZE * 2
-+ *	- the number of common ':' in pattern string : MAX_WKFM_PATTERN_SIZE - 1
-+ *	- 1 byte '\n'(0x0a) is generated at the end when we use echo command
-+ *	so total max. length is (MAX_WKFM_PATTERN_SIZE * 3)
-+ */
-+#define MAX_WKFM_PATTERN_STR_LEN (MAX_WKFM_PATTERN_SIZE * 3)
-+
-+#define WKFMCAM_ADDR_NUM 6
-+#define WKFMCAM_SIZE 24 /* each entry need 6*4 bytes */
-+enum pattern_type {
-+	PATTERN_BROADCAST = 0,
-+	PATTERN_MULTICAST,
-+	PATTERN_UNICAST,
-+	PATTERN_VALID,
-+	PATTERN_INVALID,
-+};
-+
-+typedef struct rtl_priv_pattern {
-+	int len;
-+	char content[MAX_WKFM_PATTERN_SIZE];
-+	char mask[MAX_WKFM_SIZE];
-+} rtl_priv_pattern_t;
-+
-+#endif /* CONFIG_WOWLAN */
-+
-+enum Power_Mgnt {
-+	PS_MODE_ACTIVE	= 0	,
-+	PS_MODE_MIN			,
-+	PS_MODE_MAX			,
-+	PS_MODE_DTIM			,	/* PS_MODE_SELF_DEFINED */
-+	PS_MODE_VOIP			,
-+	PS_MODE_UAPSD_WMM	,
-+	PS_MODE_UAPSD			,
-+	PS_MODE_IBSS			,
-+	PS_MODE_WWLAN		,
-+	PM_Radio_Off			,
-+	PM_Card_Disable		,
-+	PS_MODE_NUM,
-+};
-+
-+enum lps_level {
-+	LPS_NORMAL = 0,
-+	LPS_LCLK,
-+	LPS_PG,
-+	LPS_LEVEL_MAX,
-+};
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+#define MAX_PNO_LIST_COUNT 16
-+#define MAX_SCAN_LIST_COUNT 14	/* 2.4G only */
-+#define MAX_HIDDEN_AP 8		/* 8 hidden AP */
-+#endif
-+
-+/*
-+	BIT[2:0] = HW state
-+	BIT[3] = Protocol PS state,   0: register active state , 1: register sleep state
-+	BIT[4] = sub-state
-+*/
-+
-+#define PS_DPS				BIT(0)
-+#define PS_LCLK				(PS_DPS)
-+#define PS_RF_OFF			BIT(1)
-+#define PS_ALL_ON			BIT(2)
-+#define PS_ST_ACTIVE		BIT(3)
-+
-+#define PS_ISR_ENABLE		BIT(4)
-+#define PS_IMR_ENABLE		BIT(5)
-+#define PS_ACK				BIT(6)
-+#define PS_TOGGLE			BIT(7)
-+
-+#define PS_STATE_MASK		(0x0F)
-+#define PS_STATE_HW_MASK	(0x07)
-+#define PS_SEQ_MASK			(0xc0)
-+
-+#define PS_STATE(x)		(PS_STATE_MASK & (x))
-+#define PS_STATE_HW(x)	(PS_STATE_HW_MASK & (x))
-+#define PS_SEQ(x)		(PS_SEQ_MASK & (x))
-+
-+#define PS_STATE_S0		(PS_DPS)
-+#define PS_STATE_S1		(PS_LCLK)
-+#define PS_STATE_S2		(PS_RF_OFF)
-+#define PS_STATE_S3		(PS_ALL_ON)
-+#define PS_STATE_S4		((PS_ST_ACTIVE) | (PS_ALL_ON))
-+
-+
-+#define PS_IS_RF_ON(x)	((x) & (PS_ALL_ON))
-+#define PS_IS_ACTIVE(x)	((x) & (PS_ST_ACTIVE))
-+#define CLR_PS_STATE(x)	((x) = ((x) & (0xF0)))
-+
-+
-+struct reportpwrstate_parm {
-+	unsigned char mode;
-+	unsigned char state; /* the CPWM value */
-+	unsigned short rsvd;
-+};
-+
-+
-+typedef _sema _pwrlock;
-+
-+
-+__inline static void _init_pwrlock(_pwrlock *plock)
-+{
-+	_rtw_init_sema(plock, 1);
-+}
-+
-+__inline static void _free_pwrlock(_pwrlock *plock)
-+{
-+	_rtw_free_sema(plock);
-+}
-+
-+
-+__inline static void _enter_pwrlock(_pwrlock *plock)
-+{
-+	_rtw_down_sema(plock);
-+}
-+
-+
-+__inline static void _exit_pwrlock(_pwrlock *plock)
-+{
-+	_rtw_up_sema(plock);
-+}
-+
-+#define LPS_DELAY_MS	1000 /* 1 sec */
-+
-+#define EXE_PWR_NONE	0x01
-+#define EXE_PWR_IPS		0x02
-+#define EXE_PWR_LPS		0x04
-+
-+/* RF state. */
-+typedef enum _rt_rf_power_state {
-+	rf_on,		/* RF is on after RFSleep or RFOff */
-+	rf_sleep,	/* 802.11 Power Save mode */
-+	rf_off,		/* HW/SW Radio OFF or Inactive Power Save */
-+	/* =====Add the new RF state above this line===== */
-+	rf_max
-+} rt_rf_power_state;
-+
-+/* ASPM OSC Control bit, added by Roger, 2013.03.29. */
-+#define	RT_PCI_ASPM_OSC_IGNORE		0	 /* PCI ASPM ignore OSC control in default */
-+#define	RT_PCI_ASPM_OSC_ENABLE		BIT0 /* PCI ASPM controlled by OS according to ACPI Spec 5.0 */
-+#define	RT_PCI_ASPM_OSC_DISABLE		BIT1 /* PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM */
-+
-+
-+enum _PS_BBRegBackup_ {
-+	PSBBREG_RF0 = 0,
-+	PSBBREG_RF1,
-+	PSBBREG_RF2,
-+	PSBBREG_AFE0,
-+	PSBBREG_TOTALCNT
-+};
-+
-+enum { /* for ips_mode */
-+	IPS_NONE = 0,
-+	IPS_NORMAL,
-+	IPS_LEVEL_2,
-+	IPS_NUM
-+};
-+
-+/* Design for pwrctrl_priv.ips_deny, 32 bits for 32 reasons at most */
-+typedef enum _PS_DENY_REASON {
-+	PS_DENY_DRV_INITIAL = 0,
-+	PS_DENY_SCAN,
-+	PS_DENY_JOIN,
-+	PS_DENY_DISCONNECT,
-+	PS_DENY_SUSPEND,
-+	PS_DENY_IOCTL,
-+	PS_DENY_MGNT_TX,
-+	PS_DENY_MONITOR_MODE,
-+	PS_DENY_BEAMFORMING,		/* Beamforming */
-+	PS_DENY_DRV_REMOVE = 30,
-+	PS_DENY_OTHERS = 31
-+} PS_DENY_REASON;
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+/* only support mDNS V4/V6 rsp now */
-+enum {
-+	WAR_ARP_RSP_EN = 0x0000001,
-+	WAR_ICMPV6_NS_RSP_EN = 0x00000002,
-+	WAR_ICMPV4_ECHO_RSP_EN = 0x00000004,
-+	WAR_ICMPV6_ECHO_RSP_EN = 0x00000008,
-+	WAR_NETBIOS_RSP_EN = 0x00000010,
-+	WAR_LLMNR_V4_RSP_EN = 0x00000020,
-+	WAR_LLMNR_V6_RSP_EN = 0x00000040,
-+	WAR_SNMP_V4_RSP_EN = 0x00000080,
-+	WAR_SNMP_V6_RSP_EN = 0x00000100,
-+	WAR_SNMP_V4_WAKEUP_EN = 0x00000200,
-+	WAR_SNMP_V6_WAKEUP_EN = 0x00000400,
-+	WAR_SSDP_V4_WAKEUP_EN = 0x00000800,
-+	WAR_SSDP_V6_WAKEUP_EN = 0x00001000,
-+	WAR_WSD_V4_WAKEUP_EN = 0x00002000,
-+	WAR_WSD_V6_WAKEUP_EN = 0x00004000,
-+	WAR_SLP_V4_WAKEUP_EN = 0x00008000,
-+	WAR_SLP_V6_WAKEUP_EN = 0x00010000,
-+	WAR_MDNS_V4_RSP_EN = 0x00020000,
-+	WAR_MDNS_V6_RSP_EN = 0x00040000,
-+	WAR_DESIGNATED_MAC_EN = 0x00080000,
-+	WAR_LLTD_WAKEUP_EN = 0x00100000,
-+	WAR_ARP_WAKEUP_EN = 0x00200000,
-+	WAR_MAGIC_WAKEUP_EN = 0x00400000,
-+	WAR_MDNS_V4_WAKEUP_EN = 0x000800000,
-+	WAR_MDNS_V6_WAKEUP_EN = 0x001000000
-+};
-+
-+#endif /* CONFIG_WAR_OFFLOAD */
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+typedef struct pno_nlo_info {
-+	u32 fast_scan_period;				/* Fast scan period */
-+	u8	ssid_num;				/* number of entry */
-+	u8	hidden_ssid_num;
-+	u32	slow_scan_period;			/* slow scan period */
-+	u32	fast_scan_iterations;			/* Fast scan iterations */
-+	u8	ssid_length[MAX_PNO_LIST_COUNT];	/* SSID Length Array */
-+	u8	ssid_cipher_info[MAX_PNO_LIST_COUNT];	/* Cipher information for security */
-+	u8	ssid_channel_info[MAX_PNO_LIST_COUNT];	/* channel information */
-+	u8	loc_probe_req[MAX_HIDDEN_AP];		/* loc_probeReq */
-+} pno_nlo_info_t;
-+
-+typedef struct pno_ssid {
-+	u32		SSID_len;
-+	u8		SSID[32];
-+} pno_ssid_t;
-+
-+typedef struct pno_ssid_list {
-+	pno_ssid_t	node[MAX_PNO_LIST_COUNT];
-+} pno_ssid_list_t;
-+
-+typedef struct pno_scan_channel_info {
-+	u8	channel;
-+	u8	tx_power;
-+	u8	timeout;
-+	u8	active;				/* set 1 means active scan, or pasivite scan. */
-+} pno_scan_channel_info_t;
-+
-+typedef struct pno_scan_info {
-+	u8	enableRFE;			/* Enable RFE */
-+	u8	period_scan_time;		/* exclusive with fast_scan_period and slow_scan_period */
-+	u8	periodScan;			/* exclusive with fast_scan_period and slow_scan_period */
-+	u8	orig_80_offset;			/* original channel 80 offset */
-+	u8	orig_40_offset;			/* original channel 40 offset */
-+	u8	orig_bw;			/* original bandwidth */
-+	u8	orig_ch;			/* original channel */
-+	u8	channel_num;			/* number of channel */
-+	u64	rfe_type;			/* rfe_type && 0x00000000000000ff */
-+	pno_scan_channel_info_t ssid_channel_info[MAX_SCAN_LIST_COUNT];
-+} pno_scan_info_t;
-+#endif /* CONFIG_PNO_SUPPORT */
-+
-+#ifdef CONFIG_LPS_POFF
-+/* Driver context for LPS 32K Close IO Power */
-+typedef struct lps_poff_info {
-+	bool	bEn;
-+	u8	*pStaticFile;
-+	u8	*pDynamicFile;
-+	u32	ConfFileOffset;
-+	u32	tx_bndy_static;
-+	u32	tx_bndy_dynamic;
-+	u16	ConfLenForPTK;
-+	u16	ConfLenForGTK;
-+	ATOMIC_T bEnterPOFF;
-+	ATOMIC_T bTxBoundInProgress;
-+	ATOMIC_T bSetPOFFParm;
-+} lps_poff_info_t;
-+#endif /*CONFIG_LPS_POFF*/
-+
-+struct aoac_report {
-+	u8 iv[8];
-+	u8 replay_counter_eapol_key[8];
-+	u8 group_key[32];
-+	u8 key_index;
-+	u8 security_type;
-+	u8 wow_pattern_idx;
-+	u8 version_info;
-+	u8 rekey_ok:1;
-+	u8 dummy:7;
-+	u8 reserved[3];
-+	u8 rxptk_iv[8];
-+	u8 rxgtk_iv[4][8];
-+};
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+
-+struct war_ipv4_fmt {
-+	u32 ip_addr[4];
-+	u32 ip_subnet[4];
-+	u32 ip_gateway[4];
-+};
-+
-+struct war_ipv6_fmt {
-+	u8 ipv6_addr[8][16];
-+};
-+
-+#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
-+/* limitation of mDNS parameter : length and number */
-+#define MAX_MDNS_SERVICE_NAME_LEN 15 
-+#define MAX_MDNS_TRANS_LEN 4 /* _tcp or _udp */
-+#define MAX_MDNS_DOMAIN_LEN 5 /* local only for mdns */
-+#define MAX_MDNS_MACHINE_NAME_LEN (63+1) /* +1 for the length byte used by the DNS format */
-+#define MAX_MDNS_TARGET_LEN 63
-+#define MAX_MDNS_DOMAIN_NAME_LEN 63
-+#define MAX_MDNS_TXT_LEN 1536
-+#define MAX_MDNS_TXT_SINGLE_LEN 255
-+
-+
-+#define MAX_MDNS_SERVICE_NUM 10
-+#define MAX_MDNS_TXT_NUM 8
-+#define MAX_MDNS_MACHINE_NAME_NUM 3
-+
-+/* for monitor rsvd page using */
-+#define MAX_MDNS_PARA_SIZE 1700 // 14*128 = 1792
-+#define MAX_MDNS_TXT_TOTAL_SIZE 10*MAX_MDNS_TXT_LEN
-+#define MAX_MDNS_RSP_PKT_SIZE 760   //  6*128 = 768
-+
-+#define RTW_MDNS_SRV_INFO(sname, sname_len, tname, tname_len, dname, dname_len, port0, port1, ttlv, tar, tar_len, idx) \
-+	{ .service=sname, .service_len=sname_len, .transport=tname, .transport_len=tname_len, \
-+	  .domain=dname , .domain_len=dname_len , .port[0]=port0, .port[1]=port1, .ttl=ttlv, \
-+	  .target=tar, .target_len=tar_len, .txt_rsp_idx=idx }
-+
-+
-+struct war_mdns_service_info {
-+	u8  service[MAX_MDNS_SERVICE_NAME_LEN+1];
-+	u8  service_len;
-+	u8  transport[MAX_MDNS_TRANS_LEN+1];
-+	u8  transport_len;
-+	u8  domain[MAX_MDNS_DOMAIN_LEN+1];
-+	u8  domain_len;
-+	u8  port[2];
-+	u32 ttl;
-+	u8  target[MAX_MDNS_TARGET_LEN+1];
-+	u8  target_len;
-+	s8  txt_rsp_idx;
-+};
-+
-+struct war_mdns_machine_name {
-+	u8  name[MAX_MDNS_MACHINE_NAME_LEN];
-+	u8  name_len;
-+};
-+
-+struct war_mdns_txt_rsp {
-+	u8  txt[MAX_MDNS_TXT_LEN];
-+	u16  txt_len;
-+};
-+#endif
-+#endif /* CONFIG_WAR_OFFLOAD */
-+
-+
-+struct rsvd_page_cache_t;
-+
-+struct pwrctrl_priv {
-+	_pwrlock	lock;
-+	_pwrlock	check_32k_lock;
-+	volatile u8 rpwm; /* requested power state for fw */
-+	volatile u8 cpwm; /* fw current power state. updated when 1. read from HCPWM 2. driver lowers power level */
-+	volatile u8 tog; /* toggling */
-+	volatile u8 cpwm_tog; /* toggling */
-+	u8 rpwm_retry;
-+
-+	u8	pwr_mode;
-+	u8	smart_ps;
-+	u8	bcn_ant_mode;
-+	u8	dtim;
-+#ifdef CONFIG_LPS_CHK_BY_TP
-+	u8	lps_chk_by_tp;
-+	u16	lps_tx_tp_th;/*Mbps*/
-+	u16	lps_rx_tp_th;/*Mbps*/
-+	u16	lps_bi_tp_th;/*Mbps*//*TRX TP*/
-+	int	lps_chk_cnt_th;
-+	int	lps_chk_cnt;
-+	u32	lps_tx_pkts;
-+	u32	lps_rx_pkts;
-+
-+#endif
-+
-+#ifdef CONFIG_WMMPS_STA
-+	u8 wmm_smart_ps;
-+#endif /* CONFIG_WMMPS_STA */	
-+
-+	u32	alives;
-+	_workitem cpwm_event;
-+	_workitem dma_event; /*for handle un-synchronized tx dma*/
-+#ifdef CONFIG_LPS_RPWM_TIMER
-+	u8 brpwmtimeout;
-+	_workitem rpwmtimeoutwi;
-+	_timer pwr_rpwm_timer;
-+#endif /* CONFIG_LPS_RPWM_TIMER */
-+	u8	bpower_saving; /* for LPS/IPS */
-+
-+	u8	b_hw_radio_off;
-+	u8	reg_rfoff;
-+	u8	reg_pdnmode; /* powerdown mode */
-+	u32	rfoff_reason;
-+
-+	uint	ips_enter_cnts;
-+	uint	ips_leave_cnts;
-+	uint	lps_enter_cnts;
-+	uint	lps_leave_cnts;
-+
-+	u8	ips_mode;
-+	u8	ips_org_mode;
-+	u8	ips_mode_req; /* used to accept the mode setting request, will update to ipsmode later */
-+	uint bips_processing;
-+	systime ips_deny_time; /* will deny IPS when system time is smaller than this */
-+	u8 pre_ips_type;/* 0: default flow, 1: carddisbale flow */
-+
-+	/* ps_deny: if 0, power save is free to go; otherwise deny all kinds of power save. */
-+	/* Use PS_DENY_REASON to decide reason. */
-+	/* Don't access this variable directly without control function, */
-+	/* and this variable should be protected by lock. */
-+	u32 ps_deny;
-+
-+	u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */
-+
-+	u8 fw_psmode_iface_id;
-+	u8	bLeisurePs;
-+	u8	LpsIdleCount;
-+	u8	power_mgnt;
-+	u8	org_power_mgnt;
-+	u8	bFwCurrentInPSMode;
-+	systime	lps_deny_time; /* will deny LPS when system time is smaller than this */
-+	s32		pnp_current_pwr_state;
-+	u8		pnp_bstop_trx;
-+	u8		bInSuspend;
-+#ifdef CONFIG_BT_COEXIST
-+	u8		bAutoResume;
-+	u8		autopm_cnt;
-+#endif
-+	u8		bSupportRemoteWakeup;
-+	u8		wowlan_wake_reason;
-+	u8		wowlan_last_wake_reason;
-+	u8		wowlan_ap_mode;
-+	u8		wowlan_mode;
-+	u8		wowlan_p2p_mode;
-+	u8		wowlan_pno_enable;
-+	u8		wowlan_in_resume;
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+	u8		is_high_active;
-+	u8		wowlan_gpio_index;
-+	u8		wowlan_gpio_output_state;
-+#endif /* CONFIG_GPIO_WAKEUP */
-+	u8		hst2dev_high_active;
-+#ifdef CONFIG_WOWLAN
-+	bool		default_patterns_en;
-+#ifdef CONFIG_IPV6
-+	u8		wowlan_ns_offload_en;
-+#endif /*CONFIG_IPV6*/
-+	u8		wowlan_txpause_status;
-+	u8		wowlan_pattern_idx;
-+	u64		wowlan_fw_iv;
-+	struct rtl_priv_pattern	patterns[MAX_WKFM_CAM_NUM];
-+#ifdef CONFIG_PNO_SUPPORT
-+	u8		pno_inited;
-+	pno_nlo_info_t	*pnlo_info;
-+	pno_scan_info_t	*pscan_info;
-+	pno_ssid_list_t	*pno_ssid_list;
-+#endif /* CONFIG_PNO_SUPPORT */
-+#ifdef CONFIG_WOW_PATTERN_HW_CAM
-+	_mutex	wowlan_pattern_cam_mutex;
-+#endif
-+	u8		wowlan_aoac_rpt_loc;
-+	struct aoac_report wowlan_aoac_rpt;
-+	u8		wowlan_power_mgmt;
-+	u8		wowlan_lps_level;
-+	#ifdef CONFIG_LPS_1T1R
-+	u8		wowlan_lps_1t1r;
-+	#endif
-+
-+	#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+	/*data 0,rsv page location*/
-+	u8		wowlan_keep_alive_mode;
-+	u8		keep_alive_pattern_loc;
-+	/*data 1 ,cam id, rx udp packet*/
-+	u8		wowlan_keep_alive_ack_index;
-+	/*data 2 ,cam id, pattern match packet*/
-+	u8		wowlan_wake_pattern_index;
-+	/*data3,unit: TBTT*/
-+	u16		wowlan_keep_alive_period;
-+	/*data4,unit: TBTT*/
-+	u8		wowlan_keep_alive_retry_interval;
-+	/*data5*/
-+	u8		wowlan_keep_alive_retry_counter;
-+	/*from echo*/
-+	u8		keep_alive_pattern[WLAN_MAX_KEEP_ALIVE_IE_LEN];
-+	u32		keep_alive_pattern_len;
-+	#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+	u8		wowlan_war_offload_mode;
-+	u32 	wowlan_war_offload_ctrl;
-+	struct war_ipv4_fmt wowlan_war_offload_ipv4;
-+	struct war_ipv6_fmt wowlan_war_offload_ipv6;
-+	u8		wowlan_war_offload_mac[6];
-+#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
-+	struct war_mdns_machine_name wowlan_war_offload_mdns_mnane[MAX_MDNS_MACHINE_NAME_NUM];
-+	struct war_mdns_service_info wowlan_war_offload_mdns_service[MAX_MDNS_SERVICE_NUM];
-+	struct war_mdns_txt_rsp 	 wowlan_war_offload_mdns_txt_rsp[MAX_MDNS_TXT_NUM];
-+	u8	   wowlan_war_offload_mdns_mnane_num;
-+	u8	   wowlan_war_offload_mdns_service_info_num;
-+	u8	   wowlan_war_offload_mdns_txt_rsp_num;
-+	u8	   wowlan_war_offload_mdns_domain_name[MAX_MDNS_DOMAIN_NAME_LEN+1];
-+	u8	   wowlan_war_offload_mdns_domain_name_len;
-+	u32    wowlan_war_offload_mdns_para_cur_size;
-+	u32    wowlan_war_offload_mdns_rsp_cur_size;
-+#endif /* CONFIG_OFFLOAD_MDNS_V4 || CONFIG_OFFLOAD_MDNS_V6 */    
-+#endif /* CONFIG_WAR_OFFLOAD */	
-+#endif /* CONFIG_WOWLAN */
-+	_timer	pwr_state_check_timer;
-+	int		pwr_state_check_interval;
-+	u8		pwr_state_check_cnts;
-+
-+
-+	rt_rf_power_state	rf_pwrstate;/* cur power state, only for IPS */
-+	/* rt_rf_power_state	current_rfpwrstate; */
-+	rt_rf_power_state	change_rfpwrstate;
-+
-+	u8		bHWPowerdown; /* power down mode selection. 0:radio off, 1:power down */
-+	u8		bHWPwrPindetect; /* come from registrypriv.hwpwrp_detect. enable power down function. 0:disable, 1:enable */
-+	u8		bkeepfwalive;
-+	u8		brfoffbyhw;
-+	unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
-+
-+#ifdef CONFIG_RESUME_IN_WORKQUEUE
-+	struct workqueue_struct *rtw_workqueue;
-+	_workitem resume_work;
-+#endif
-+
-+#ifdef CONFIG_HAS_EARLYSUSPEND
-+	struct early_suspend early_suspend;
-+	u8 do_late_resume;
-+#endif /* CONFIG_HAS_EARLYSUSPEND */
-+
-+#ifdef CONFIG_ANDROID_POWER
-+	android_early_suspend_t early_suspend;
-+	u8 do_late_resume;
-+#endif
-+
-+#ifdef CONFIG_LPS_POFF
-+	lps_poff_info_t	*plps_poff_info;
-+#endif
-+	u8 lps_level_bk;
-+	u8 lps_level; /*LPS_NORMAL,LPA_CG,LPS_PG*/
-+#ifdef CONFIG_LPS_1T1R
-+	u8 lps_1t1r_bk;
-+	u8 lps_1t1r;
-+#endif
-+#ifdef CONFIG_LPS_PG
-+	struct rsvd_page_cache_t lpspg_info;
-+#ifdef CONFIG_RTL8822C
-+	struct rsvd_page_cache_t lpspg_dpk_info;
-+	struct rsvd_page_cache_t lpspg_iqk_info;
-+#endif
-+#endif
-+	u8 current_lps_hw_port_id;
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
-+	systime radio_on_start_time;
-+	systime pwr_saving_start_time;
-+	u32 pwr_saving_time;
-+	u32 on_time;
-+	u32 tx_time;
-+	u32 rx_time;
-+#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
-+
-+#ifdef CONFIG_LPS_ACK
-+	struct submit_ctx lps_ack_sctx;
-+	s8 lps_ack_status;
-+	_mutex lps_ack_mutex;
-+#endif /* CONFIG_LPS_ACK */
-+};
-+
-+#define rtw_get_ips_mode_req(pwrctl) \
-+	(pwrctl)->ips_mode_req
-+
-+#define rtw_ips_mode_req(pwrctl, ips_mode) \
-+	(pwrctl)->ips_mode_req = (ips_mode)
-+
-+#define RTW_PWR_STATE_CHK_INTERVAL 2000
-+
-+#define _rtw_set_pwr_state_check_timer(pwrctl, ms) \
-+	do { \
-+		/*RTW_INFO("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctl), (ms));*/ \
-+		_set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \
-+	} while (0)
-+
-+#define rtw_set_pwr_state_check_timer(pwrctl) \
-+	_rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval)
-+
-+extern void rtw_init_pwrctrl_priv(_adapter *adapter);
-+extern void rtw_free_pwrctrl_priv(_adapter *adapter);
-+
-+#ifdef CONFIG_LPS_LCLK
-+s32 rtw_register_task_alive(PADAPTER, u32 task);
-+void rtw_unregister_task_alive(PADAPTER, u32 task);
-+extern s32 rtw_register_tx_alive(PADAPTER padapter);
-+extern void rtw_unregister_tx_alive(PADAPTER padapter);
-+extern s32 rtw_register_rx_alive(PADAPTER padapter);
-+extern void rtw_unregister_rx_alive(PADAPTER padapter);
-+extern s32 rtw_register_cmd_alive(PADAPTER padapter);
-+extern void rtw_unregister_cmd_alive(PADAPTER padapter);
-+extern s32 rtw_register_evt_alive(PADAPTER padapter);
-+extern void rtw_unregister_evt_alive(PADAPTER padapter);
-+extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate);
-+extern void LPS_Leave_check(PADAPTER padapter);
-+#endif
-+
-+extern void LeaveAllPowerSaveMode(PADAPTER Adapter);
-+extern void LeaveAllPowerSaveModeDirect(PADAPTER Adapter);
-+#ifdef CONFIG_IPS
-+void _ips_enter(_adapter *padapter);
-+void ips_enter(_adapter *padapter);
-+int _ips_leave(_adapter *padapter);
-+int ips_leave(_adapter *padapter);
-+#endif
-+
-+void rtw_ps_processor(_adapter *padapter);
-+
-+#ifdef SUPPORT_HW_RFOFF_DETECTED
-+rt_rf_power_state RfOnOffDetect(PADAPTER pAdapter);
-+#endif
-+
-+
-+#ifdef DBG_CHECK_FW_PS_STATE
-+int rtw_fw_ps_state(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_LPS
-+extern const char * const LPS_CTRL_PHYDM;
-+void LPS_Enter(PADAPTER padapter, const char *msg);
-+void LPS_Leave(PADAPTER padapter, const char *msg);
-+void rtw_exec_lps(_adapter *padapter, u8 ps_mode);
-+void rtw_lps_rfon_ctrl(_adapter *padapter, u8 rfon_ctrl);
-+#ifdef CONFIG_CHECK_LEAVE_LPS
-+#ifdef CONFIG_LPS_CHK_BY_TP
-+void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta);
-+#endif
-+void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets);
-+#endif /*CONFIG_CHECK_LEAVE_LPS*/
-+void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg);
-+void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable);
-+u8 rtw_set_rpwm(_adapter *padapter, u8 val8);
-+#ifdef CONFIG_WOWLAN
-+void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en);
-+#endif /* CONFIG_WOWLAN */
-+#endif /* CONFIG_LPS */
-+
-+#ifdef CONFIG_RESUME_IN_WORKQUEUE
-+void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv);
-+#endif /* CONFIG_RESUME_IN_WORKQUEUE */
-+
-+#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
-+bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv);
-+bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv);
-+void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable);
-+void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv);
-+void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv);
-+#else
-+#define rtw_is_earlysuspend_registered(pwrpriv) _FALSE
-+#define rtw_is_do_late_resume(pwrpriv) _FALSE
-+#define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0)
-+#define rtw_register_early_suspend(pwrpriv) do {} while (0)
-+#define rtw_unregister_early_suspend(pwrpriv) do {} while (0)
-+#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
-+
-+u8 rtw_interface_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
-+void rtw_set_ips_deny(_adapter *padapter, u32 ms);
-+int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller);
-+#define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__)
-+#define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__)
-+int rtw_pm_set_ips(_adapter *padapter, u8 mode);
-+int rtw_pm_set_lps(_adapter *padapter, u8 mode);
-+int rtw_pm_set_lps_level(_adapter *padapter, u8 level);
-+#ifdef CONFIG_LPS_1T1R
-+int rtw_pm_set_lps_1t1r(_adapter *padapter, u8 en);
-+#endif
-+void rtw_set_lps_deny(_adapter *adapter, u32 ms);
-+#ifdef CONFIG_WOWLAN
-+int rtw_pm_set_wow_lps(_adapter *padapter, u8 mode);
-+int rtw_pm_set_wow_lps_level(_adapter *padapter, u8 level);
-+#ifdef CONFIG_LPS_1T1R
-+int rtw_pm_set_wow_lps_1t1r(_adapter *padapter, u8 en);
-+#endif
-+#endif /* CONFIG_WOWLAN */
-+
-+void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason);
-+void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason);
-+u32 rtw_ps_deny_get(PADAPTER padapter);
-+
-+#if defined(CONFIG_WOWLAN)
-+void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip);
-+void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr);
-+bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern,
-+				int *pattern_len, char *bit_mask);
-+void rtw_wow_pattern_sw_reset(_adapter *adapter);
-+u8 rtw_set_default_pattern(_adapter *adapter);
-+void rtw_wow_pattern_sw_dump(_adapter *adapter);
-+#ifdef CONFIG_WAR_OFFLOAD
-+#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
-+void rtw_wow_war_mdns_dump_buf(struct seq_file *m, u8 *title, u8 *buf, u32 len);
-+void rtw_wow_war_mdns_dump_txt(struct seq_file *m, u8 *title, u8 *buf, u32 len);
-+bool rtw_wow_war_mdns_parser_pattern(u8 *input, char *target, u32 *target_len, u32 max_len);
-+void rtw_wow_war_mdns_parms_reset(_adapter *adapter, u8 is_set_default);
-+#endif /* defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) */
-+#endif /* CONFIG_WAR_OFFLOAD */
-+
-+#endif /* CONFIG_WOWLAN */
-+void rtw_ssmps_enter(_adapter *adapter, struct sta_info *sta);
-+void rtw_ssmps_leave(_adapter *adapter, struct sta_info *sta);
-+#endif /* __RTL871X_PWRCTRL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_qos.h b/drivers/staging/rtl8723cs/include/rtw_qos.h
-new file mode 100644
-index 000000000000..8e1d013e128f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_qos.h
-@@ -0,0 +1,66 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+#ifndef _RTW_QOS_H_
-+#define _RTW_QOS_H_
-+
-+#define DRV_CFG_UAPSD_VO 	BIT0
-+#define DRV_CFG_UAPSD_VI 	BIT1
-+#define DRV_CFG_UAPSD_BK 	BIT2
-+#define DRV_CFG_UAPSD_BE 	BIT3
-+
-+#define WMM_IE_UAPSD_VO 	BIT0
-+#define WMM_IE_UAPSD_VI 	BIT1
-+#define WMM_IE_UAPSD_BK 	BIT2
-+#define WMM_IE_UAPSD_BE 	BIT3
-+
-+#define WMM_TID0 	BIT0
-+#define WMM_TID1 	BIT1
-+#define WMM_TID2 	BIT2
-+#define WMM_TID3 	BIT3
-+#define WMM_TID4 	BIT4
-+#define WMM_TID5 	BIT5
-+#define WMM_TID6 	BIT6
-+#define WMM_TID7 	BIT7
-+
-+#define AP_SUPPORTED_UAPSD BIT7
-+/* TC = Traffic Category,  TID0~7 represents TC */
-+#define BIT_MASK_TID_TC 0xff
-+/* TS = Traffic Stream,  TID8~15 represents TS */
-+#define BIT_MASK_TID_TS 0xff00
-+#define ALL_TID_TC_SUPPORTED_UAPSD 0xff
-+
-+struct	qos_priv	{
-+
-+	unsigned int	  qos_option;	/* bit mask option: u-apsd, s-apsd, ts, block ack...		 */
-+
-+#ifdef CONFIG_WMMPS_STA
-+	/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */
-+	u8 uapsd_max_sp_len;
-+	/* declare uapsd_tid as a bitmap for the uapsd setting of TID 0~15 */
-+	u16 uapsd_tid;
-+	/* declare uapsd_tid_delivery_enabled as a bitmap for the delivery-enabled setting of TID 0~7 */
-+	u8 uapsd_tid_delivery_enabled;
-+	/* declare uapsd_tid_trigger_enabled as a bitmap for the trigger-enabled setting of TID 0~7 */
-+	u8 uapsd_tid_trigger_enabled;
-+	/* declare uapsd_ap_supported to record whether the connected ap  supports uapsd or not */
-+	u8 uapsd_ap_supported;
-+#endif /* CONFIG_WMMPS_STA */	
-+
-+};
-+
-+
-+#endif /* _RTL871X_QOS_H_ */
-\ No newline at end of file
-diff --git a/drivers/staging/rtl8723cs/include/rtw_recv.h b/drivers/staging/rtl8723cs/include/rtw_recv.h
-new file mode 100644
-index 000000000000..a2574f755434
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_recv.h
-@@ -0,0 +1,868 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTW_RECV_H_
-+#define _RTW_RECV_H_
-+
-+#define RTW_RX_MSDU_ACT_NONE		0
-+#define RTW_RX_MSDU_ACT_INDICATE	BIT0
-+#define RTW_RX_MSDU_ACT_FORWARD		BIT1
-+
-+#ifdef CONFIG_SINGLE_RECV_BUF
-+	#define NR_RECVBUFF (1)
-+#else
-+	#if defined(CONFIG_GSPI_HCI)
-+		#define NR_RECVBUFF (32)
-+	#elif defined(CONFIG_SDIO_HCI)
-+		#define NR_RECVBUFF (64)
-+	#else
-+		#define NR_RECVBUFF (64)
-+	#endif
-+#endif /* CONFIG_SINGLE_RECV_BUF */
-+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
-+	#define NR_PREALLOC_RECV_SKB (rtw_rtkm_get_nr_recv_skb()>>1)
-+#else /*!CONFIG_PREALLOC_RX_SKB_BUFFER */
-+	#define NR_PREALLOC_RECV_SKB 8
-+#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
-+
-+#ifdef CONFIG_RTW_NAPI
-+	#define RTL_NAPI_WEIGHT (32)
-+#endif
-+
-+
-+#if defined(CONFIG_RTL8821C) && defined(CONFIG_SDIO_HCI) && defined(CONFIG_RECV_THREAD_MODE)
-+	#ifdef NR_RECVBUFF
-+	#undef NR_RECVBUFF
-+	#define NR_RECVBUFF (32)
-+	#endif
-+#endif
-+
-+#define NR_RECVFRAME 256
-+
-+#define RXFRAME_ALIGN	8
-+#define RXFRAME_ALIGN_SZ	(1<<RXFRAME_ALIGN)
-+
-+#define DRVINFO_SZ	4 /* unit is 8bytes */
-+
-+#define MAX_RXFRAME_CNT	512
-+#define MAX_RX_NUMBLKS		(32)
-+#define RECVFRAME_HDR_ALIGN 128
-+#define MAX_CONTINUAL_NORXPACKET_COUNT 4    /*  In MAX_CONTINUAL_NORXPACKET_COUNT*2 sec  , no rx traffict would issue DELBA*/
-+
-+#define PHY_RSSI_SLID_WIN_MAX				100
-+#define PHY_LINKQUALITY_SLID_WIN_MAX		20
-+
-+
-+#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr)
-+
-+#define RX_MPDU_QUEUE				0
-+#define RX_CMD_QUEUE				1
-+#define RX_MAX_QUEUE				2
-+
-+#define MAX_SUBFRAME_COUNT	64
-+/* Bridge-Tunnel header (for EtherTypes ETH_P_AARP and ETH_P_IPX) */
-+extern u8 rtw_bridge_tunnel_header[];
-+extern u8 rtw_rfc1042_header[];
-+
-+enum addba_rsp_ack_state {
-+	RTW_RECV_ACK_OR_TIMEOUT,
-+};
-+
-+/* for Rx reordering buffer control */
-+struct recv_reorder_ctrl {
-+	_adapter	*padapter;
-+	u8 tid;
-+	u8 enable;
-+	u16 indicate_seq;/* =wstart_b, init_value=0xffff */
-+	u16 wend_b;
-+	u8 wsize_b;
-+	u8 ampdu_size;
-+	_queue pending_recvframe_queue;
-+	_timer reordering_ctrl_timer;
-+	u8 bReorderWaiting;
-+	unsigned long rec_abba_rsp_ack;
-+};
-+
-+struct	stainfo_rxcache	{
-+	u16	tid_rxseq[16];
-+	u8 iv[16][8];
-+	u8 last_tid;
-+#if 0
-+	unsigned short	tid0_rxseq;
-+	unsigned short	tid1_rxseq;
-+	unsigned short	tid2_rxseq;
-+	unsigned short	tid3_rxseq;
-+	unsigned short	tid4_rxseq;
-+	unsigned short	tid5_rxseq;
-+	unsigned short	tid6_rxseq;
-+	unsigned short	tid7_rxseq;
-+	unsigned short	tid8_rxseq;
-+	unsigned short	tid9_rxseq;
-+	unsigned short	tid10_rxseq;
-+	unsigned short	tid11_rxseq;
-+	unsigned short	tid12_rxseq;
-+	unsigned short	tid13_rxseq;
-+	unsigned short	tid14_rxseq;
-+	unsigned short	tid15_rxseq;
-+#endif
-+};
-+
-+
-+struct smooth_rssi_data {
-+	u32	elements[100];	/* array to store values */
-+	u32	index;			/* index to current array to store */
-+	u32	total_num;		/* num of valid elements */
-+	u32	total_val;		/* sum of valid elements */
-+};
-+
-+struct signal_stat {
-+	u8	update_req;		/* used to indicate */
-+	u8	avg_val;		/* avg of valid elements */
-+	u32	total_num;		/* num of valid elements */
-+	u32	total_val;		/* sum of valid elements	 */
-+};
-+
-+struct rx_raw_rssi {
-+	u8 data_rate;
-+	u8 pwdball;
-+	s8 pwr_all;
-+
-+	u8 mimo_signal_strength[4];/* in 0~100 index */
-+	u8 mimo_signal_quality[4];
-+
-+	s8 ofdm_pwr[4];
-+	u8 ofdm_snr[4];
-+};
-+
-+
-+#include "cmn_info/rtw_sta_info.h"
-+
-+struct rx_pkt_attrib	{
-+	u16	pkt_len;
-+	u8	physt;
-+	u8	drvinfo_sz;
-+	u8	shift_sz;
-+	u8	hdrlen; /* the WLAN Header Len */
-+	u8	to_fr_ds;
-+	u8	amsdu;
-+	u8	qos;
-+	u8	priority;
-+	u8	pw_save;
-+	u8	mdata;
-+	u16	seq_num;
-+	u8	frag_num;
-+	u8	mfrag;
-+	u8	order;
-+	u8	privacy; /* in frame_ctrl field */
-+	u8	bdecrypted;
-+	u8	encrypt; /* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */
-+	u8	iv_len;
-+	u8	icv_len;
-+	u8	crc_err;
-+	u8	icv_err;
-+
-+	u8	dst[ETH_ALEN];
-+	u8	src[ETH_ALEN];
-+	u8	ta[ETH_ALEN];
-+	u8	ra[ETH_ALEN];
-+	u8	bssid[ETH_ALEN];
-+#ifdef CONFIG_RTW_MESH
-+	u8	msa[ETH_ALEN]; /* mesh sa */
-+	u8	mda[ETH_ALEN]; /* mesh da */
-+	u8 mesh_ctrl_present;
-+	u8	mesh_ctrl_len; /* length of mesh control field */
-+#endif
-+
-+	u8	ack_policy;
-+
-+	u8	key_index;
-+
-+	u8	data_rate;
-+	u8 ch; /* RX channel */
-+	u8	bw;
-+	u8	stbc;
-+	u8	ldpc;
-+	u8	sgi;
-+	u8	pkt_rpt_type;
-+	u32	MacIDValidEntry[2];	/* 64 bits present 64 entry. */
-+	u8	ampdu;
-+	u8	ppdu_cnt;
-+	u8	ampdu_eof;
-+	u32 	free_cnt;		/* free run counter */
-+	struct phydm_phyinfo_struct phy_info;
-+#ifdef CONFIG_WIFI_MONITOR
-+	u8 moif[16];
-+#endif
-+
-+#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
-+	/* checksum offload realted varaiables */
-+	u8 csum_valid;		/* Checksum valid, 0: not check, 1: checked */
-+	u8 csum_err;		/* Checksum Error occurs */
-+#endif /* CONFIG_TCP_CSUM_OFFLOAD_RX */
-+};
-+
-+#ifdef CONFIG_RTW_MESH
-+#define RATTRIB_GET_MCTRL_LEN(rattrib) ((rattrib)->mesh_ctrl_len)
-+#else
-+#define RATTRIB_GET_MCTRL_LEN(rattrib) 0
-+#endif
-+
-+/* These definition is used for Rx packet reordering. */
-+#define SN_LESS(a, b)		(((a-b) & 0x800) != 0)
-+#define SN_EQUAL(a, b)	(a == b)
-+/* #define REORDER_WIN_SIZE	128 */
-+/* #define REORDER_ENTRY_NUM	128 */
-+#define REORDER_WAIT_TIME	(50) /* (ms) */
-+
-+#if defined(CONFIG_PLATFORM_RTK390X) && defined(CONFIG_USB_HCI)
-+	#define RECVBUFF_ALIGN_SZ 32
-+#else
-+	#define RECVBUFF_ALIGN_SZ 8
-+#endif
-+
-+#ifdef CONFIG_TRX_BD_ARCH
-+	#define RX_WIFI_INFO_SIZE	24
-+#elif (defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)) && defined(CONFIG_PCI_HCI)
-+	#define RXBD_SIZE	sizeof(struct recv_stat)
-+#endif
-+
-+#define RXDESC_SIZE	24
-+#define RXDESC_OFFSET RXDESC_SIZE
-+
-+#ifdef CONFIG_TRX_BD_ARCH
-+struct rx_buf_desc {
-+	/* RX has exactly one segment */
-+#ifdef CONFIG_64BIT_DMA
-+	unsigned int dword[4];
-+#else
-+	unsigned int dword[2];
-+#endif
-+};
-+
-+struct recv_stat {
-+	unsigned int rxdw[8];
-+};
-+#else
-+struct recv_stat {
-+	unsigned int rxdw0;
-+
-+	unsigned int rxdw1;
-+
-+#if !((defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI))  /* exclude 8192ee, 8814ae, 8822be, 8821ce */
-+	unsigned int rxdw2;
-+
-+	unsigned int rxdw3;
-+#endif
-+
-+#ifndef BUF_DESC_ARCH
-+	unsigned int rxdw4;
-+
-+	unsigned int rxdw5;
-+
-+#ifdef CONFIG_PCI_HCI
-+	unsigned int rxdw6;
-+
-+	unsigned int rxdw7;
-+#endif
-+#endif /* if BUF_DESC_ARCH is defined, rx_buf_desc occupy 4 double words */
-+};
-+#endif
-+
-+#define EOR BIT(30)
-+
-+#ifdef CONFIG_PCI_HCI
-+#define PCI_MAX_RX_QUEUE		1/* MSDU packet queue, Rx Command Queue */
-+#define PCI_MAX_RX_COUNT		128
-+#ifdef CONFIG_TRX_BD_ARCH
-+#define RX_BD_NUM				PCI_MAX_RX_COUNT	/* alias */
-+#endif
-+
-+struct rtw_rx_ring {
-+#ifdef CONFIG_TRX_BD_ARCH
-+	struct rx_buf_desc	*buf_desc;
-+#else
-+	struct recv_stat	*desc;
-+#endif
-+	dma_addr_t		dma;
-+	unsigned int		idx;
-+	struct sk_buff	*rx_buf[PCI_MAX_RX_COUNT];
-+};
-+#endif
-+
-+
-+
-+/*
-+accesser of recv_priv: rtw_recv_entry(dispatch / passive level); recv_thread(passive) ; returnpkt(dispatch)
-+; halt(passive) ;
-+
-+using enter_critical section to protect
-+*/
-+
-+#ifndef DBG_RX_BH_TRACKING
-+#define DBG_RX_BH_TRACKING 0
-+#endif
-+
-+struct recv_priv {
-+	_lock	lock;
-+
-+#ifdef CONFIG_RECV_THREAD_MODE
-+	_sema	recv_sema;
-+
-+#endif
-+
-+	/* _queue	blk_strms[MAX_RX_NUMBLKS];    */ /* keeping the block ack frame until return ack */
-+	_queue	free_recv_queue;
-+	_queue	recv_pending_queue;
-+	_queue	uc_swdec_pending_queue;
-+
-+
-+	u8 *pallocated_frame_buf;
-+	u8 *precv_frame_buf;
-+
-+	uint free_recvframe_cnt;
-+
-+	#if DBG_RX_BH_TRACKING
-+	u32 rx_bh_stage;
-+	u32 rx_bh_buf_dq_cnt;
-+	void *rx_bh_lbuf;
-+	void *rx_bh_cbuf;
-+	void *rx_bh_cbuf_data;
-+	u32 rx_bh_cbuf_dlen;
-+	u32 rx_bh_cbuf_pos;
-+	void *rx_bh_cframe;
-+	#endif
-+
-+	_adapter	*adapter;
-+
-+	u32 is_any_non_be_pkts;
-+
-+	u64	rx_bytes;
-+	u64	rx_pkts;
-+	u64	rx_drop;
-+
-+	u64 dbg_rx_drop_count;
-+	u64 dbg_rx_ampdu_drop_count;
-+	u64 dbg_rx_ampdu_forced_indicate_count;
-+	u64 dbg_rx_ampdu_loss_count;
-+	u64 dbg_rx_dup_mgt_frame_drop_count;
-+	u64 dbg_rx_ampdu_window_shift_cnt;
-+	u64 dbg_rx_conflic_mac_addr_cnt;
-+
-+	uint  rx_icv_err;
-+	uint  rx_largepacket_crcerr;
-+	uint  rx_smallpacket_crcerr;
-+	uint  rx_middlepacket_crcerr;
-+
-+#ifdef CONFIG_USB_HCI
-+	/* u8 *pallocated_urb_buf; */
-+	_sema allrxreturnevt;
-+	uint	ff_hwaddr;
-+	ATOMIC_T	rx_pending_cnt;
-+
-+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
-+#ifdef PLATFORM_LINUX
-+	PURB	int_in_urb;
-+#endif
-+
-+	u8	*int_in_buf;
-+#endif /* CONFIG_USB_INTERRUPT_IN_PIPE */
-+
-+#endif
-+#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
-+	_tasklet irq_prepare_beacon_tasklet;
-+	_tasklet recv_tasklet;
-+
-+	struct sk_buff_head free_recv_skb_queue;
-+	struct sk_buff_head rx_skb_queue;
-+#ifdef CONFIG_RTW_NAPI
-+		struct sk_buff_head rx_napi_skb_queue;
-+#endif 
-+#ifdef CONFIG_RX_INDICATE_QUEUE
-+	_tasklet rx_indicate_tasklet;
-+	struct ifqueue rx_indicate_queue;
-+#endif /* CONFIG_RX_INDICATE_QUEUE */
-+
-+#endif /* defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) */
-+
-+	u8 *pallocated_recv_buf;
-+	u8 *precv_buf;    /* 4 alignment */
-+	_queue	free_recv_buf_queue;
-+	u32	free_recv_buf_queue_cnt;
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) || defined(CONFIG_USB_HCI)
-+	_queue	recv_buf_pending_queue;
-+#endif
-+
-+#if defined(CONFIG_SDIO_HCI)
-+#ifdef CONFIG_SDIO_RECVBUF_PWAIT
-+	struct rtw_pwait_ctx recvbuf_pwait;
-+#endif
-+#ifdef CONFIG_SDIO_RECVBUF_AGGREGATION
-+	bool recvbuf_agg;
-+#endif
-+#endif /* CONFIG_SDIO_HCI */
-+
-+#ifdef CONFIG_PCI_HCI
-+	/* Rx */
-+	struct rtw_rx_ring	rx_ring[PCI_MAX_RX_QUEUE];
-+	int rxringcount;	/* size should be PCI_MAX_RX_QUEUE */
-+	u32	rxbuffersize;
-+#endif
-+
-+	/* For display the phy informatiom */
-+	u8 is_signal_dbg;	/* for debug */
-+	u8 signal_strength_dbg;	/* for debug */
-+
-+	u8 signal_strength;
-+	u8 signal_qual;
-+	s8 rssi;	/* translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength); */
-+	struct rx_raw_rssi raw_rssi_info;
-+	/* s8 rxpwdb;	 */
-+	/* int RxSNRdB[2]; */
-+	/* s8 RxRssi[2]; */
-+	/* int FalseAlmCnt_all; */
-+
-+
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+	_timer signal_stat_timer;
-+	u32 signal_stat_sampling_interval;
-+	/* u32 signal_stat_converging_constant; */
-+	struct signal_stat signal_qual_data;
-+	struct signal_stat signal_strength_data;
-+#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+	struct smooth_rssi_data signal_qual_data;
-+	struct smooth_rssi_data signal_strength_data;
-+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+	u16 sink_udpport, pre_rtp_rxseq, cur_rtp_rxseq;
-+
-+	BOOLEAN store_law_data_flag;
-+};
-+
-+#ifdef CONFIG_SDIO_RECVBUF_AGGREGATION
-+#define recv_buf_agg(recvpriv) recvpriv->recvbuf_agg
-+#ifndef CONFIG_SDIO_RECVBUF_AGGREGATION_EN
-+#define CONFIG_SDIO_RECVBUF_AGGREGATION_EN 1
-+#endif
-+#else
-+#define recv_buf_agg(recvpriv) 0
-+#endif
-+
-+#define RX_BH_STG_UNKNOWN		0
-+#define RX_BH_STG_HDL_ENTER		1
-+#define RX_BH_STG_HDL_EXIT		2
-+#define RX_BH_STG_NEW_BUF		3
-+#define RX_BH_STG_NEW_FRAME		4
-+#define RX_BH_STG_NORMAL_RX		5
-+#define RX_BH_STG_NORMAL_RX_END	6
-+#define RX_BH_STG_C2H			7
-+#define RX_BH_STG_C2H_END		8
-+
-+#if DBG_RX_BH_TRACKING
-+void rx_bh_tk_set_stage(struct recv_priv *recv, u32 s);
-+void rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen);
-+void rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos);
-+void rx_bh_tk_set_frame(struct recv_priv *recv, void *frame);
-+void dump_rx_bh_tk(void *sel, struct recv_priv *recv);
-+#else
-+#define rx_bh_tk_set_stage(recv, s) do {} while (0)
-+#define rx_bh_tk_set_buf(recv, buf, data, dlen) do {} while (0)
-+#define rx_bh_tk_set_buf_pos(recv, pos) do {} while (0)
-+#define rx_bh_tk_set_frame(recv, frame) do {} while (0)
-+#define dump_rx_bh_tk(sel, recv) do {} while (0)
-+#endif
-+
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+#define rtw_set_signal_stat_timer(recvpriv) _set_timer(&(recvpriv)->signal_stat_timer, (recvpriv)->signal_stat_sampling_interval)
-+#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
-+
-+struct sta_recv_priv {
-+
-+	_lock	lock;
-+	sint	option;
-+
-+	/* _queue	blk_strms[MAX_RX_NUMBLKS]; */
-+	_queue defrag_q;	 /* keeping the fragment frame until defrag */
-+
-+	struct	stainfo_rxcache rxcache;
-+	u16	bmc_tid_rxseq[16];
-+	u16	nonqos_rxseq;
-+	u16	nonqos_bmc_rxseq;
-+
-+	/* uint	sta_rx_bytes; */
-+	/* uint	sta_rx_pkts; */
-+	/* uint	sta_rx_fail; */
-+
-+};
-+
-+
-+#define RBUF_TYPE_PREALLOC	0
-+#define RBUF_TYPE_TMP		1
-+#define RBUF_TYPE_PWAIT_ADJ	2
-+
-+struct recv_buf {
-+	_list list;
-+
-+#ifdef PLATFORM_WINDOWS
-+	_lock recvbuf_lock;
-+#endif
-+
-+#ifdef CONFIG_SDIO_RECVBUF_PWAIT_RUNTIME_ADJUST
-+	u8 type;
-+#endif
-+
-+	u32	ref_cnt;
-+
-+	PADAPTER adapter;
-+
-+	u8	*pbuf;
-+	u8	*pallocated_buf;
-+
-+	u32	len;
-+	u8	*phead;
-+	u8	*pdata;
-+	u8	*ptail;
-+	u8	*pend;
-+
-+#ifdef CONFIG_USB_HCI
-+	PURB	purb;
-+	dma_addr_t dma_transfer_addr;	/* (in) dma addr for transfer_buffer */
-+	u32 alloc_sz;
-+
-+	u8  irp_pending;
-+	int  transfer_len;
-+#endif
-+
-+#if defined(PLATFORM_LINUX)
-+	_pkt *pskb;
-+#elif defined(PLATFORM_FREEBSD) /* skb solution */
-+	struct sk_buff *pskb;
-+#endif
-+};
-+
-+#ifdef CONFIG_SDIO_RECVBUF_PWAIT_RUNTIME_ADJUST
-+#define RBUF_IS_PREALLOC(rbuf) ((rbuf)->type == RBUF_TYPE_PREALLOC)
-+#else
-+#define RBUF_IS_PREALLOC(rbuf) 1
-+#endif
-+
-+/*
-+	head  ----->
-+
-+		data  ----->
-+
-+			payload
-+
-+		tail  ----->
-+
-+
-+	end   ----->
-+
-+	len = (unsigned int )(tail - data);
-+
-+*/
-+struct recv_frame_hdr {
-+	_list	list;
-+	_pkt *pkt;
-+
-+	_adapter  *adapter;
-+
-+	u8 fragcnt;
-+
-+	int frame_tag;
-+
-+	struct rx_pkt_attrib attrib;
-+
-+	uint  len;
-+	u8 *rx_head;
-+	u8 *rx_data;
-+	u8 *rx_tail;
-+	u8 *rx_end;
-+
-+	void *precvbuf;
-+
-+
-+	/*  */
-+	struct sta_info *psta;
-+
-+	/* for A-MPDU Rx reordering buffer control */
-+	struct recv_reorder_ctrl *preorder_ctrl;
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	u8 UserPriority;
-+	u8 WapiTempPN[16];
-+	u8 WapiSrcAddr[6];
-+	u8 bWapiCheckPNInDecrypt;
-+	u8 bIsWaiPacket;
-+#endif
-+
-+};
-+
-+
-+union recv_frame {
-+
-+	union {
-+		_list list;
-+		struct recv_frame_hdr hdr;
-+		uint mem[RECVFRAME_HDR_ALIGN >> 2];
-+	} u;
-+
-+	/* uint mem[MAX_RXSZ>>2]; */
-+
-+};
-+
-+enum rtw_rx_llc_hdl {
-+	RTW_RX_LLC_KEEP		= 0,
-+	RTW_RX_LLC_REMOVE	= 1,
-+	RTW_RX_LLC_VLAN		= 2,
-+};
-+
-+bool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset);
-+
-+typedef enum _RX_PACKET_TYPE {
-+	NORMAL_RX,/* Normal rx packet */
-+	TX_REPORT1,/* CCX */
-+	TX_REPORT2,/* TX RPT */
-+	HIS_REPORT,/* USB HISR RPT */
-+	C2H_PACKET
-+} RX_PACKET_TYPE, *PRX_PACKET_TYPE;
-+
-+extern union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue);   /* get a free recv_frame from pfree_recv_queue */
-+extern union recv_frame *rtw_alloc_recvframe(_queue *pfree_recv_queue);   /* get a free recv_frame from pfree_recv_queue */
-+extern void rtw_init_recvframe(union recv_frame *precvframe , struct recv_priv *precvpriv);
-+extern int	 rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue);
-+
-+#define rtw_dequeue_recvframe(queue) rtw_alloc_recvframe(queue)
-+extern int _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue);
-+extern int rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue);
-+
-+extern void rtw_free_recvframe_queue(_queue *pframequeue,  _queue *pfree_recv_queue);
-+u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter);
-+
-+sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue);
-+sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue);
-+struct recv_buf *rtw_dequeue_recvbuf(_queue *queue);
-+
-+void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta);
-+void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta);
-+
-+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
-+void rtw_reordering_ctrl_timeout_handler(void *pcontext);
-+#endif
-+
-+void rx_query_phy_status(union recv_frame *rframe, u8 *phy_stat);
-+int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index);
-+void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index);
-+
-+#ifdef CONFIG_RECV_THREAD_MODE
-+thread_return rtw_recv_thread(thread_context context);
-+#endif
-+
-+__inline static u8 *get_rxmem(union recv_frame *precvframe)
-+{
-+	/* always return rx_head... */
-+	if (precvframe == NULL)
-+		return NULL;
-+
-+	return precvframe->u.hdr.rx_head;
-+}
-+
-+__inline static u8 *get_rx_status(union recv_frame *precvframe)
-+{
-+
-+	return get_rxmem(precvframe);
-+
-+}
-+
-+__inline static u8 *get_recvframe_data(union recv_frame *precvframe)
-+{
-+
-+	/* alwasy return rx_data */
-+	if (precvframe == NULL)
-+		return NULL;
-+
-+	return precvframe->u.hdr.rx_data;
-+
-+}
-+
-+__inline static u8 *recvframe_push(union recv_frame *precvframe, sint sz)
-+{
-+	/* append data before rx_data */
-+
-+	/* add data to the start of recv_frame
-+	*
-+	*      This function extends the used data area of the recv_frame at the buffer
-+	*      start. rx_data must be still larger than rx_head, after pushing.
-+	*/
-+
-+	if (precvframe == NULL)
-+		return NULL;
-+
-+
-+	precvframe->u.hdr.rx_data -= sz ;
-+	if (precvframe->u.hdr.rx_data < precvframe->u.hdr.rx_head) {
-+		precvframe->u.hdr.rx_data += sz ;
-+		return NULL;
-+	}
-+
-+	precvframe->u.hdr.len += sz;
-+
-+	return precvframe->u.hdr.rx_data;
-+
-+}
-+
-+
-+__inline static u8 *recvframe_pull(union recv_frame *precvframe, sint sz)
-+{
-+	/* rx_data += sz; move rx_data sz bytes  hereafter */
-+
-+	/* used for extract sz bytes from rx_data, update rx_data and return the updated rx_data to the caller */
-+
-+
-+	if (precvframe == NULL)
-+		return NULL;
-+
-+
-+	precvframe->u.hdr.rx_data += sz;
-+
-+	if (precvframe->u.hdr.rx_data > precvframe->u.hdr.rx_tail) {
-+		precvframe->u.hdr.rx_data -= sz;
-+		return NULL;
-+	}
-+
-+	precvframe->u.hdr.len -= sz;
-+
-+	return precvframe->u.hdr.rx_data;
-+
-+}
-+
-+__inline static u8 *recvframe_put(union recv_frame *precvframe, sint sz)
-+{
-+	/* rx_tai += sz; move rx_tail sz bytes  hereafter */
-+
-+	/* used for append sz bytes from ptr to rx_tail, update rx_tail and return the updated rx_tail to the caller */
-+	/* after putting, rx_tail must be still larger than rx_end. */
-+	unsigned char *prev_rx_tail;
-+
-+	/* RTW_INFO("recvframe_put: len=%d\n", sz); */
-+
-+	if (precvframe == NULL)
-+		return NULL;
-+
-+	prev_rx_tail = precvframe->u.hdr.rx_tail;
-+
-+	precvframe->u.hdr.rx_tail += sz;
-+
-+	if (precvframe->u.hdr.rx_tail > precvframe->u.hdr.rx_end) {
-+		precvframe->u.hdr.rx_tail -= sz;
-+		return NULL;
-+	}
-+
-+	precvframe->u.hdr.len += sz;
-+
-+	return precvframe->u.hdr.rx_tail;
-+
-+}
-+
-+
-+
-+__inline static u8 *recvframe_pull_tail(union recv_frame *precvframe, sint sz)
-+{
-+	/* rmv data from rx_tail (by yitsen) */
-+
-+	/* used for extract sz bytes from rx_end, update rx_end and return the updated rx_end to the caller */
-+	/* after pulling, rx_end must be still larger than rx_data. */
-+
-+	if (precvframe == NULL)
-+		return NULL;
-+
-+	precvframe->u.hdr.rx_tail -= sz;
-+
-+	if (precvframe->u.hdr.rx_tail < precvframe->u.hdr.rx_data) {
-+		precvframe->u.hdr.rx_tail += sz;
-+		return NULL;
-+	}
-+
-+	precvframe->u.hdr.len -= sz;
-+
-+	return precvframe->u.hdr.rx_tail;
-+
-+}
-+
-+__inline static union recv_frame *rxmem_to_recvframe(u8 *rxmem)
-+{
-+	/* due to the design of 2048 bytes alignment of recv_frame, we can reference the union recv_frame */
-+	/* from any given member of recv_frame. */
-+	/* rxmem indicates the any member/address in recv_frame */
-+
-+	return (union recv_frame *)(((SIZE_PTR)rxmem >> RXFRAME_ALIGN) << RXFRAME_ALIGN);
-+
-+}
-+
-+__inline static union recv_frame *pkt_to_recvframe(_pkt *pkt)
-+{
-+
-+	u8 *buf_star;
-+	union recv_frame *precv_frame;
-+	precv_frame = rxmem_to_recvframe((unsigned char *)buf_star);
-+
-+	return precv_frame;
-+}
-+
-+__inline static u8 *pkt_to_recvmem(_pkt *pkt)
-+{
-+	/* return the rx_head */
-+
-+	union recv_frame *precv_frame = pkt_to_recvframe(pkt);
-+
-+	return	precv_frame->u.hdr.rx_head;
-+
-+}
-+
-+__inline static u8 *pkt_to_recvdata(_pkt *pkt)
-+{
-+	/* return the rx_data */
-+
-+	union recv_frame *precv_frame = pkt_to_recvframe(pkt);
-+
-+	return	precv_frame->u.hdr.rx_data;
-+
-+}
-+
-+
-+__inline static sint get_recvframe_len(union recv_frame *precvframe)
-+{
-+	return precvframe->u.hdr.len;
-+}
-+
-+
-+__inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex)
-+{
-+	s32	SignalPower; /* in dBm. */
-+
-+	/* Translate to dBm (x=y-100) */
-+	SignalPower = SignalStrengthIndex - 100;
-+	return SignalPower;
-+}
-+
-+struct sta_info;
-+
-+extern void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv);
-+
-+extern void  mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame);
-+
-+u8 adapter_allow_bmc_data_rx(_adapter *adapter);
-+s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status);
-+void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtw_rf.h b/drivers/staging/rtl8723cs/include/rtw_rf.h
-new file mode 100644
-index 000000000000..3a24929a59c8
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_rf.h
-@@ -0,0 +1,326 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef	__RTW_RF_H_
-+#define __RTW_RF_H_
-+
-+#define NumRates	(13)
-+#define	B_MODE_RATE_NUM	(4)
-+#define	G_MODE_RATE_NUM	(8)
-+#define	G_MODE_BASIC_RATE_NUM	(3)
-+/* slot time for 11g */
-+#define SHORT_SLOT_TIME					9
-+#define NON_SHORT_SLOT_TIME				20
-+
-+#define CENTER_CH_2G_40M_NUM	9
-+#define CENTER_CH_2G_NUM		14
-+#define CENTER_CH_5G_20M_NUM	28	/* 20M center channels */
-+#define CENTER_CH_5G_40M_NUM	14	/* 40M center channels */
-+#define CENTER_CH_5G_80M_NUM	7	/* 80M center channels */
-+#define CENTER_CH_5G_160M_NUM	3	/* 160M center channels */
-+#define CENTER_CH_5G_ALL_NUM	(CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM + CENTER_CH_5G_80M_NUM)
-+
-+#define	MAX_CHANNEL_NUM_2G	CENTER_CH_2G_NUM
-+#define	MAX_CHANNEL_NUM_5G	CENTER_CH_5G_20M_NUM
-+#define	MAX_CHANNEL_NUM		(MAX_CHANNEL_NUM_2G + MAX_CHANNEL_NUM_5G)
-+#define MAX_CHANNEL_NUM_OF_BAND rtw_max(MAX_CHANNEL_NUM_2G, MAX_CHANNEL_NUM_5G)
-+
-+extern u8 center_ch_2g[CENTER_CH_2G_NUM];
-+extern u8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM];
-+
-+u8 center_chs_2g_num(u8 bw);
-+u8 center_chs_2g(u8 bw, u8 id);
-+
-+extern u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM];
-+extern u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM];
-+extern u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM];
-+extern u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM];
-+extern u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM];
-+
-+u8 center_chs_5g_num(u8 bw);
-+u8 center_chs_5g(u8 bw, u8 id);
-+
-+u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset);
-+u8 rtw_get_scch_by_cch_opch(u8 cch, u8 bw, u8 opch);
-+
-+u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num);
-+
-+u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset);
-+u8 rtw_get_center_ch(u8 ch, u8 bw, u8 offset);
-+
-+u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group);
-+
-+typedef enum _CAPABILITY {
-+	cESS			= 0x0001,
-+	cIBSS			= 0x0002,
-+	cPollable		= 0x0004,
-+	cPollReq			= 0x0008,
-+	cPrivacy		= 0x0010,
-+	cShortPreamble	= 0x0020,
-+	cPBCC			= 0x0040,
-+	cChannelAgility	= 0x0080,
-+	cSpectrumMgnt	= 0x0100,
-+	cQos			= 0x0200,	/* For HCCA, use with CF-Pollable and CF-PollReq */
-+	cShortSlotTime	= 0x0400,
-+	cAPSD			= 0x0800,
-+	cRM				= 0x1000,	/* RRM (Radio Request Measurement) */
-+	cDSSS_OFDM	= 0x2000,
-+	cDelayedBA		= 0x4000,
-+	cImmediateBA	= 0x8000,
-+} CAPABILITY, *PCAPABILITY;
-+
-+enum	_REG_PREAMBLE_MODE {
-+	PREAMBLE_LONG	= 1,
-+	PREAMBLE_AUTO	= 2,
-+	PREAMBLE_SHORT	= 3,
-+};
-+
-+#define rf_path_char(path) (((path) >= RF_PATH_MAX) ? 'X' : 'A' + (path))
-+
-+/* Bandwidth Offset */
-+#define HAL_PRIME_CHNL_OFFSET_DONT_CARE	0
-+#define HAL_PRIME_CHNL_OFFSET_LOWER	1
-+#define HAL_PRIME_CHNL_OFFSET_UPPER	2
-+
-+typedef enum _BAND_TYPE {
-+	BAND_ON_2_4G = 0,
-+	BAND_ON_5G = 1,
-+	BAND_MAX,
-+} BAND_TYPE, *PBAND_TYPE;
-+
-+#ifdef CONFIG_NARROWBAND_SUPPORTING
-+enum nb_config {
-+	RTW_NB_CONFIG_NONE		= 0,
-+	RTW_NB_CONFIG_WIDTH_5	= 5,
-+	RTW_NB_CONFIG_WIDTH_10	= 6,
-+};
-+#endif
-+
-+extern const char *const _band_str[];
-+#define band_str(band) (((band) >= BAND_MAX) ? _band_str[BAND_MAX] : _band_str[(band)])
-+
-+extern const u8 _band_to_band_cap[];
-+#define band_to_band_cap(band) (((band) >= BAND_MAX) ? _band_to_band_cap[BAND_MAX] : _band_to_band_cap[(band)])
-+
-+
-+extern const char *const _ch_width_str[];
-+#define ch_width_str(bw) (((bw) < CHANNEL_WIDTH_MAX) ? _ch_width_str[(bw)] : "CHANNEL_WIDTH_MAX")
-+
-+extern const u8 _ch_width_to_bw_cap[];
-+#define ch_width_to_bw_cap(bw) (((bw) < CHANNEL_WIDTH_MAX) ? _ch_width_to_bw_cap[(bw)] : 0)
-+
-+enum opc_bw {
-+	OPC_BW20		= 0,
-+	OPC_BW40PLUS	= 1,
-+	OPC_BW40MINUS	= 2,
-+	OPC_BW80		= 3,
-+	OPC_BW160		= 4,
-+	OPC_BW80P80		= 5,
-+	OPC_BW_NUM,
-+};
-+
-+extern const char *const _opc_bw_str[OPC_BW_NUM];
-+#define opc_bw_str(bw) (((bw) < OPC_BW_NUM) ? _opc_bw_str[(bw)] : "N/A")
-+
-+extern const u8 _opc_bw_to_ch_width[OPC_BW_NUM];
-+#define opc_bw_to_ch_width(bw) (((bw) < OPC_BW_NUM) ? _opc_bw_to_ch_width[(bw)] : CHANNEL_WIDTH_MAX)
-+
-+/* global op class APIs */
-+bool is_valid_global_op_class_id(u8 gid);
-+s16 get_sub_op_class(u8 gid, u8 ch);
-+void dump_global_op_class(void *sel);
-+u8 rtw_get_op_class_by_chbw(u8 ch, u8 bw, u8 offset);
-+u8 rtw_get_bw_offset_by_op_class_ch(u8 gid, u8 ch, u8 *bw, u8 *offset);
-+
-+struct op_ch_t {
-+	u8 ch;
-+	u8 static_non_op:1; /* not in channel list */
-+	u8 no_ir:1;
-+	s16 max_txpwr; /* mBm */
-+};
-+
-+struct op_class_pref_t {
-+	u8 class_id;
-+	BAND_TYPE band;
-+	enum opc_bw bw;
-+	u8 ch_num; /* number of chs */
-+	u8 op_ch_num; /* channel number which is not static non operable */
-+	u8 ir_ch_num; /* channel number which can init radiation */
-+	struct op_ch_t chs[MAX_CHANNEL_NUM_OF_BAND]; /* zero(ch) terminated array */
-+};
-+
-+int op_class_pref_init(_adapter *adapter);
-+void op_class_pref_deinit(_adapter *adapter);
-+
-+#define REG_BEACON_HINT		0
-+#define REG_TXPWR_CHANGE	1
-+#define REG_CHANGE			2
-+
-+void op_class_pref_apply_regulatory(_adapter *adapter, u8 reason);
-+
-+struct rf_ctl_t;
-+void dump_cap_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool detail);
-+void dump_reg_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool detail);
-+void dump_cur_spt_op_class_ch(void *sel, struct rf_ctl_t *rfctl, bool detail);
-+
-+/*
-+ * Represent Extention Channel Offset in HT Capabilities
-+ * This is available only in 40Mhz mode.
-+ *   */
-+typedef enum _EXTCHNL_OFFSET {
-+	EXTCHNL_OFFSET_NO_EXT = 0,
-+	EXTCHNL_OFFSET_UPPER = 1,
-+	EXTCHNL_OFFSET_NO_DEF = 2,
-+	EXTCHNL_OFFSET_LOWER = 3,
-+} EXTCHNL_OFFSET, *PEXTCHNL_OFFSET;
-+
-+typedef enum _VHT_DATA_SC {
-+	VHT_DATA_SC_DONOT_CARE = 0,
-+	VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
-+	VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
-+	VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
-+	VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
-+	VHT_DATA_SC_20_RECV1 = 5,
-+	VHT_DATA_SC_20_RECV2 = 6,
-+	VHT_DATA_SC_20_RECV3 = 7,
-+	VHT_DATA_SC_20_RECV4 = 8,
-+	VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
-+	VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
-+} VHT_DATA_SC, *PVHT_DATA_SC_E;
-+
-+typedef enum _PROTECTION_MODE {
-+	PROTECTION_MODE_AUTO = 0,
-+	PROTECTION_MODE_FORCE_ENABLE = 1,
-+	PROTECTION_MODE_FORCE_DISABLE = 2,
-+} PROTECTION_MODE, *PPROTECTION_MODE;
-+
-+#define RF_TYPE_VALID(rf_type) (rf_type < RF_TYPE_MAX)
-+
-+extern const u8 _rf_type_to_rf_tx_cnt[];
-+#define rf_type_to_rf_tx_cnt(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rf_tx_cnt[rf_type] : 0)
-+
-+extern const u8 _rf_type_to_rf_rx_cnt[];
-+#define rf_type_to_rf_rx_cnt(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rf_rx_cnt[rf_type] : 0)
-+
-+extern const char *const _rf_type_to_rfpath_str[];
-+#define rf_type_to_rfpath_str(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rfpath_str[rf_type] : "UNKNOWN")
-+
-+void rf_type_to_default_trx_bmp(enum rf_type rf, enum bb_path *tx, enum bb_path *rx);
-+
-+enum rf_type trx_num_to_rf_type(u8 tx_num, u8 rx_num);
-+enum rf_type trx_bmp_to_rf_type(u8 tx_bmp, u8 rx_bmp);
-+bool rf_type_is_a_in_b(enum rf_type a, enum rf_type b);
-+u8 rtw_restrict_trx_path_bmp_by_trx_num_lmt(u8 trx_path_bmp, u8 tx_num_lmt, u8 rx_num_lmt, u8 *tx_num, u8 *rx_num);
-+u8 rtw_restrict_trx_path_bmp_by_rftype(u8 trx_path_bmp, enum rf_type type, u8 *tx_num, u8 *rx_num);
-+void tx_path_nss_set_default(enum bb_path txpath_nss[], u8 txpath_num_nss[], u8 txpath);
-+void tx_path_nss_set_full_tx(enum bb_path txpath_nss[], u8 txpath_num_nss[], u8 txpath);
-+
-+int rtw_ch2freq(int chan);
-+int rtw_freq2ch(int freq);
-+bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo);
-+
-+struct rf_ctl_t;
-+
-+typedef enum _REGULATION_TXPWR_LMT {
-+	TXPWR_LMT_NONE = 0, /* no limit */
-+	TXPWR_LMT_FCC = 1,
-+	TXPWR_LMT_MKK = 2,
-+	TXPWR_LMT_ETSI = 3,
-+	TXPWR_LMT_IC = 4,
-+	TXPWR_LMT_KCC = 5,
-+	TXPWR_LMT_NCC = 6,
-+	TXPWR_LMT_ACMA = 7,
-+	TXPWR_LMT_CHILE = 8,
-+	TXPWR_LMT_UKRAINE = 9,
-+	TXPWR_LMT_MEXICO = 10,
-+	TXPWR_LMT_CN = 11,
-+	TXPWR_LMT_WW, /* smallest of all available limit, keep last */
-+} REGULATION_TXPWR_LMT;
-+
-+extern const char *const _regd_str[];
-+#define regd_str(regd) (((regd) > TXPWR_LMT_WW) ? _regd_str[TXPWR_LMT_WW] : _regd_str[(regd)])
-+
-+void txpwr_idx_get_dbm_str(s8 idx, u8 txgi_max, u8 txgi_pdbm, SIZE_T cwidth, char dbm_str[], u8 dbm_str_len);
-+
-+#define MBM_PDBM 100
-+#define UNSPECIFIED_MBM 32767 /* maximum of s16 */
-+
-+void txpwr_mbm_get_dbm_str(s16 mbm, SIZE_T cwidth, char dbm_str[], u8 dbm_str_len);
-+s16 mb_of_ntx(u8 ntx);
-+
-+#if CONFIG_TXPWR_LIMIT
-+struct regd_exc_ent {
-+	_list list;
-+	char country[2];
-+	u8 domain;
-+	char regd_name[0];
-+};
-+
-+void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl);
-+void rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen);
-+void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name);
-+struct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain);
-+struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain);
-+void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl);
-+
-+void dump_txpwr_lmt(void *sel, _adapter *adapter);
-+void rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen
-+	, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt);
-+void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name
-+	, u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt);
-+struct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name);
-+struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name);
-+void rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl);
-+#endif /* CONFIG_TXPWR_LIMIT */
-+
-+#define BB_GAIN_2G 0
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+#define BB_GAIN_5GLB1 1
-+#define BB_GAIN_5GLB2 2
-+#define BB_GAIN_5GMB1 3
-+#define BB_GAIN_5GMB2 4
-+#define BB_GAIN_5GHB 5
-+#endif
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+#define BB_GAIN_NUM 6
-+#else
-+#define BB_GAIN_NUM 1
-+#endif
-+
-+int rtw_ch_to_bb_gain_sel(int ch);
-+void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset);
-+void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch);
-+
-+/* only check channel ranges */
-+#define rtw_is_2g_ch(ch) (ch >= 1 && ch <= 14)
-+#define rtw_is_5g_ch(ch) ((ch) >= 36 && (ch) <= 177)
-+#define rtw_is_same_band(a, b) \
-+	((rtw_is_2g_ch(a) && rtw_is_2g_ch(b)) \
-+	|| (rtw_is_5g_ch(a) && rtw_is_5g_ch(b)))
-+
-+#define rtw_is_5g_band1(ch) ((ch) >= 36 && (ch) <= 48)
-+#define rtw_is_5g_band2(ch) ((ch) >= 52 && (ch) <= 64)
-+#define rtw_is_5g_band3(ch) ((ch) >= 100 && (ch) <= 144)
-+#define rtw_is_5g_band4(ch) ((ch) >= 149 && (ch) <= 177)
-+#define rtw_is_same_5g_band(a, b) \
-+	((rtw_is_5g_band1(a) && rtw_is_5g_band1(b)) \
-+	|| (rtw_is_5g_band2(a) && rtw_is_5g_band2(b)) \
-+	|| (rtw_is_5g_band3(a) && rtw_is_5g_band3(b)) \
-+	|| (rtw_is_5g_band4(a) && rtw_is_5g_band4(b)))
-+
-+bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region);
-+bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region);
-+
-+#endif /* _RTL8711_RF_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_rm.h b/drivers/staging/rtl8723cs/include/rtw_rm.h
-new file mode 100644
-index 000000000000..8aa2b9d167e6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_rm.h
-@@ -0,0 +1,105 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __RTW_RM_H_
-+#define __RTW_RM_H_
-+
-+u8 rm_post_event_hdl(_adapter *padapter, u8 *pbuf);
-+
-+#define RM_TIMER_NUM 		32
-+#define RM_ALL_MEAS		BIT(1)
-+#define RM_ID_FOR_ALL(aid)	((aid<<16)|RM_ALL_MEAS)
-+
-+#define RM_CAP_ARG(x) ((u8 *)(x))[4], ((u8 *)(x))[3], ((u8 *)(x))[2], ((u8 *)(x))[1], ((u8 *)(x))[0]
-+#define RM_CAP_FMT "%02x %02x%02x %02x%02x"
-+
-+/* remember to modify rm_event_name() when adding new event */
-+enum RM_EV_ID {
-+	RM_EV_state_in,
-+	RM_EV_busy_timer_expire,
-+	RM_EV_delay_timer_expire,
-+	RM_EV_meas_timer_expire,
-+	RM_EV_retry_timer_expire,
-+	RM_EV_repeat_delay_expire,
-+	RM_EV_request_timer_expire,
-+	RM_EV_wait_report,
-+	RM_EV_start_meas,
-+	RM_EV_survey_done,
-+	RM_EV_recv_rep,
-+	RM_EV_cancel,
-+	RM_EV_state_out,
-+	RM_EV_max
-+};
-+
-+struct rm_event {
-+	u32 rmid;
-+	enum RM_EV_ID evid;
-+	_list list;
-+};
-+
-+#ifdef CONFIG_RTW_80211K
-+
-+struct rm_clock {
-+	struct rm_obj *prm;
-+	ATOMIC_T counter;
-+	enum RM_EV_ID evid;
-+};
-+
-+struct rm_priv {
-+	u8 enable;
-+	_queue ev_queue;
-+	_queue rm_queue;
-+	_timer rm_timer;
-+
-+	struct rm_clock clock[RM_TIMER_NUM];
-+	u8 rm_en_cap_def[5];
-+	u8 rm_en_cap_assoc[5];
-+
-+	u8 meas_token;
-+	/* rm debug */
-+	void *prm_sel;
-+};
-+
-+#define	MAX_CH_NUM_IN_OP_CLASS	11
-+typedef struct _RT_OPERATING_CLASS {
-+	int	global_op_class;
-+	int	Len;
-+	u8	Channel[MAX_CH_NUM_IN_OP_CLASS];
-+} RT_OPERATING_CLASS, *PRT_OPERATING_CLASS;
-+
-+int rtw_init_rm(_adapter *padapter);
-+int rtw_free_rm_priv(_adapter *padapter);
-+
-+unsigned int rm_on_action(_adapter *padapter, union recv_frame *precv_frame);
-+void RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
-+void rtw_ap_parse_sta_rm_en_cap(_adapter *padapter,
-+	struct sta_info *psta, struct rtw_ieee802_11_elems *elems);
-+
-+int rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid);
-+void rm_handler(_adapter *padapter, struct rm_event *pev);
-+
-+u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta);
-+
-+/* from ioctl */
-+int rm_send_bcn_reqs(_adapter *padapter, u8 *sta_addr, u8 op_class, u8 ch,
-+	u16 measure_duration, u8 measure_mode, u8 *bssid, u8 *ssid,
-+	u8 reporting_detail,
-+	u8 n_ap_ch_rpt, struct _RT_OPERATING_CLASS *rpt,
-+	u8 n_elem_id, u8 *elem_id_list);
-+void indicate_beacon_report(u8 *sta_addr,
-+	u8 n_measure_rpt, u32 elem_len, u8 *elem);
-+
-+#endif /*CONFIG_RTW_80211K */
-+#endif /* __RTW_RM_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_rm_fsm.h b/drivers/staging/rtl8723cs/include/rtw_rm_fsm.h
-new file mode 100644
-index 000000000000..bbbb3d918bed
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_rm_fsm.h
-@@ -0,0 +1,397 @@
-+
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __RTW_RM_FSM_H_
-+#define __RTW_RM_FSM_H_
-+
-+#ifdef CONFIG_RTW_80211K
-+
-+#define RM_SUPPORT_IWPRIV_DBG	1
-+#define RM_MORE_DBG_MSG		0
-+
-+#define DBG_BCN_REQ_DETAIL	0
-+#define DBG_BCN_REQ_WILDCARD	0
-+#define DBG_BCN_REQ_SSID	0
-+#define DBG_BCN_REQ_SSID_NAME	"RealKungFu"
-+
-+#define RM_REQ_TIMEOUT		10000	/* 10 seconds */
-+#define RM_MEAS_TIMEOUT		10000	/* 10 seconds */
-+#define RM_REPT_SCAN_INTVL	5000	/*  5 seconds */
-+#define RM_REPT_POLL_INTVL	2000	/*  2 seconds */
-+#define RM_COND_INTVL		2000	/*  2 seconds */
-+#define RM_SCAN_DENY_TIMES	10
-+#define RM_BUSY_TRAFFIC_TIMES	10
-+#define RM_WAIT_BUSY_TIMEOUT	1000	/*  1 seconds */
-+
-+#define MEAS_REQ_MOD_PARALLEL	BIT(0)
-+#define MEAS_REQ_MOD_ENABLE	BIT(1)
-+#define MEAS_REQ_MOD_REQUEST	BIT(2)
-+#define MEAS_REQ_MOD_REPORT	BIT(3)
-+#define MEAS_REQ_MOD_DUR_MAND	BIT(4)
-+
-+#define MEAS_REP_MOD_LATE	BIT(0)
-+#define MEAS_REP_MOD_INCAP	BIT(1)
-+#define MEAS_REP_MOD_REFUSE	BIT(2)
-+
-+#define RM_MASTER		BIT(0)	/* STA who issue meas_req */
-+#define RM_SLAVE		0	/* STA who do measurement */
-+
-+#define CLOCK_UNIT		10	/* ms */
-+#define RTW_MAX_NB_RPT_IE_NUM	16
-+
-+#define RM_GET_AID(rmid)	((rmid&0xffff0000)>>16)
-+#define RM_IS_ID_FOR_ALL(rmid)	(rmid&RM_ALL_MEAS)
-+
-+/* IEEE 802.11-2012 Table 8-59 Measurement Type definitions
-+*  for measurement request
-+*  modify rm_meas_type_req_name() when adding new type
-+*/
-+enum meas_type_of_req {
-+	basic_req,	/* spectrum measurement */
-+	cca_req,
-+	rpi_histo_req,
-+	ch_load_req,
-+	noise_histo_req,
-+	bcn_req,
-+	frame_req,
-+	sta_statis_req,
-+	lci_req,
-+	meas_type_req_max,
-+};
-+
-+/* IEEE 802.11-2012 Table 8-81 Measurement Type definitions
-+*  for measurement report
-+*  modify rm_type_rep_name() when adding new type
-+*/
-+enum meas_type_of_rep {
-+	basic_rep,	/* spectrum measurement */
-+	cca_rep,
-+	rpi_histo_rep,
-+	ch_load_rep,	/* radio measurement */
-+	noise_histo_rep,
-+	bcn_rep,
-+	frame_rep,
-+	sta_statis_rep,	/* Radio measurement and WNM */
-+	lci_rep,
-+	meas_type_rep_max
-+};
-+
-+/*
-+* Beacon request
-+*/
-+/* IEEE 802.11-2012 Table 8-64 Measurement mode for Beacon Request element */
-+enum bcn_req_meas_mode {
-+	bcn_req_passive,
-+	bcn_req_active,
-+	bcn_req_bcn_table
-+};
-+
-+/* IEEE 802.11-2012 Table 8-65 optional subelement IDs for Beacon Request */
-+enum bcn_req_opt_sub_id{
-+	bcn_req_ssid = 0,		/* len 0-32 */
-+	bcn_req_rep_info = 1,		/* len 2 */
-+	bcn_req_rep_detail = 2,		/* len 1 */
-+	bcn_req_req = 10,		/* len 0-237 */
-+	bcn_req_ap_ch_rep = 51		/* len 1-237 */
-+};
-+
-+/* IEEE 802.11-2012 Table 8-66 Reporting condition of Beacon Report */
-+enum bcn_rep_cound_id{
-+	bcn_rep_cond_immediately,	/* default */
-+	bcn_req_cond_rcpi_greater,
-+	bcn_req_cond_rcpi_less,
-+	bcn_req_cond_rsni_greater,
-+	bcn_req_cond_rsni_less,
-+	bcn_req_cond_max
-+};
-+
-+struct opt_rep_info {
-+	u8 cond;
-+	u8 threshold;
-+};
-+
-+#define BCN_REQ_OPT_MAX_NUM		16
-+#define BCN_REQ_REQ_OPT_MAX_NUM		16
-+#define BCN_REQ_OPT_AP_CH_RPT_MAX_NUM	12
-+struct bcn_req_opt {
-+	/* all req cmd id */
-+	u8 opt_id[BCN_REQ_OPT_MAX_NUM];
-+	u8 opt_id_num;
-+	u8 req_id_num;
-+	u8 req_id[BCN_REQ_REQ_OPT_MAX_NUM];
-+	u8 rep_detail;
-+	NDIS_802_11_SSID ssid;
-+
-+	/* bcn report condition */
-+	struct opt_rep_info rep_cond;
-+
-+	u8 ap_ch_rpt_num;
-+	struct _RT_OPERATING_CLASS *ap_ch_rpt[BCN_REQ_OPT_AP_CH_RPT_MAX_NUM];
-+
-+	/* 0:default(Report to be issued after each measurement) */
-+	u8 *req_start;	/*id : 10 request;start  */
-+	u8 req_len;	/*id : 10 request;length */
-+};
-+
-+/*
-+* channel load
-+*/
-+/* IEEE 802.11-2012 Table 8-60 optional subelement IDs for channel load request */
-+enum ch_load_opt_sub_id{
-+	ch_load_rsvd,
-+	ch_load_rep_info
-+};
-+
-+/* IEEE 802.11-2012 Table 8-61 Reporting condition for channel load Report */
-+enum ch_load_cound_id{
-+	ch_load_cond_immediately,	/* default */
-+	ch_load_cond_anpi_equal_greater,
-+	ch_load_cond_anpi_equal_less,
-+	ch_load_cond_max
-+};
-+
-+/*
-+* Noise histogram
-+*/
-+/* IEEE 802.11-2012 Table 8-62 optional subelement IDs for noise histogram */
-+enum noise_histo_opt_sub_id{
-+	noise_histo_rsvd,
-+	noise_histo_rep_info
-+};
-+
-+/* IEEE 802.11-2012 Table 8-63 Reporting condition for noise historgarm Report */
-+enum noise_histo_cound_id{
-+	noise_histo_cond_immediately,	/* default */
-+	noise_histo_cond_anpi_equal_greater,
-+	noise_histo_cond_anpi_equal_less,
-+	noise_histo_cond_max
-+};
-+
-+struct meas_req_opt {
-+	/* report condition */
-+	struct opt_rep_info rep_cond;
-+};
-+
-+/*
-+* State machine
-+*/
-+
-+enum RM_STATE {
-+	RM_ST_IDLE,
-+	RM_ST_DO_MEAS,
-+	RM_ST_WAIT_MEAS,
-+	RM_ST_SEND_REPORT,
-+	RM_ST_RECV_REPORT,
-+	RM_ST_END,
-+	RM_ST_MAX
-+};
-+
-+struct rm_meas_req {
-+	u8 category;
-+	u8 action_code;		/* T8-206  */
-+	u8 diag_token;
-+	u16 rpt;
-+
-+	u8 e_id;
-+	u8 len;
-+	u8 m_token;
-+	u8 m_mode;		/* req:F8-105, rep:F8-141 */
-+	u8 m_type;		/* T8-59 */
-+	u8 op_class;
-+	u8 ch_num;
-+	u16 rand_intvl;		/* units of TU */
-+	u16 meas_dur;		/* units of TU */
-+
-+	u8 bssid[6];		/* for bcn_req */
-+
-+	u8 *pssid;
-+	u8 *opt_s_elem_start;
-+	int opt_s_elem_len;
-+
-+	s8 tx_pwr_used;		/* for link measurement */
-+	s8 tx_pwr_max;		/* for link measurement */
-+
-+	union {
-+		struct bcn_req_opt bcn;
-+		struct meas_req_opt clm;
-+		struct meas_req_opt nhm;
-+	}opt;
-+
-+	struct rtw_ieee80211_channel ch_set[RTW_CHANNEL_SCAN_AMOUNT];
-+	u8 ch_set_ch_amount;
-+	s8 rx_pwr;		/* in dBm */
-+	u8 rx_bw;
-+	u8 rx_rate;
-+	u8 rx_rsni;
-+};
-+
-+struct rm_meas_rep {
-+	u8 category;
-+	u8 action_code;		/* T8-206  */
-+	u8 diag_token;
-+
-+	u8 e_id;		/* T8-54, 38 request; 39 report */
-+	u8 len;
-+	u8 m_token;
-+	u8 m_mode;		/* req:F8-105, rep:F8-141 */
-+	u8 m_type;		/* T8-59 */
-+	u8 op_class;
-+	u8 ch_num;
-+
-+	u8 ch_load;
-+	u8 anpi;
-+	u8 ipi[11];
-+
-+	u16 rpt;
-+	u8 bssid[6];		/* for bcn_req */
-+};
-+
-+#define MAX_BUF_NUM	128
-+struct data_buf {
-+	u8 *pbuf;
-+	u16 len;
-+};
-+
-+struct rm_obj {
-+
-+	/* aid << 16 
-+		|diag_token << 8
-+		|B(1) 1/0:All_AID/UNIC
-+		|B(0) 1/0:RM_MASTER/RM_SLAVE */
-+	u32 rmid;
-+
-+	enum RM_STATE state;
-+	struct rm_meas_req q;
-+	struct rm_meas_rep p;
-+	struct sta_info *psta;
-+	struct rm_clock *pclock;
-+
-+	/* meas report */
-+	u64 meas_start_time;
-+	u64 meas_end_time;
-+	int wait_busy;
-+	u8 poll_mode;
-+	u8 free_run_counter_valid; /* valid:_SUCCESS/invalid:_FAIL */
-+
-+	struct data_buf buf[MAX_BUF_NUM];
-+	bool from_ioctl;
-+
-+	_list list;
-+};
-+
-+/*
-+* Measurement
-+*/
-+struct opt_subelement {
-+	u8 id;
-+	u8 length;
-+	u8 *data;
-+};
-+
-+/* 802.11-2012 Table 8-206 Radio Measurment Action field */
-+enum rm_action_code {
-+	RM_ACT_RADIO_MEAS_REQ,
-+	RM_ACT_RADIO_MEAS_REP,
-+	RM_ACT_LINK_MEAS_REQ,
-+	RM_ACT_LINK_MEAS_REP,
-+	RM_ACT_NB_REP_REQ,	/* 4 */
-+	RM_ACT_NB_REP_RESP,
-+	RM_ACT_RESV,
-+	RM_ACT_MAX
-+};
-+
-+/* 802.11-2012 Table 8-119 RM Enabled Capabilities definition */
-+enum rm_cap_en {
-+	RM_LINK_MEAS_CAP_EN,
-+	RM_NB_REP_CAP_EN,		/* neighbor report */
-+	RM_PARAL_MEAS_CAP_EN,		/* parallel report */
-+	RM_REPEAT_MEAS_CAP_EN,
-+	RM_BCN_PASSIVE_MEAS_CAP_EN,
-+	RM_BCN_ACTIVE_MEAS_CAP_EN,
-+	RM_BCN_TABLE_MEAS_CAP_EN,
-+	RM_BCN_MEAS_REP_COND_CAP_EN,	/* conditions */
-+
-+	RM_FRAME_MEAS_CAP_EN,
-+	RM_CH_LOAD_CAP_EN,
-+	RM_NOISE_HISTO_CAP_EN,		/* noise historgram */
-+	RM_STATIS_MEAS_CAP_EN,		/* statistics */
-+	RM_LCI_MEAS_CAP_EN,		/* 12 */
-+	RM_LCI_AMIMUTH_CAP_EN,
-+	RM_TRANS_STREAM_CAT_MEAS_CAP_EN,
-+	RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN,
-+
-+	RM_AP_CH_REP_CAP_EN,
-+	RM_RM_MIB_CAP_EN,
-+	RM_OP_CH_MAX_MEAS_DUR0,		/* 18-20 */
-+	RM_OP_CH_MAX_MEAS_DUR1,
-+	RM_OP_CH_MAX_MEAS_DUR2,
-+	RM_NONOP_CH_MAX_MEAS_DUR0,	/* 21-23 */
-+	RM_NONOP_CH_MAX_MEAS_DUR1,
-+	RM_NONOP_CH_MAX_MEAS_DUR2,
-+
-+	RM_MEAS_PILOT_CAP0,		/* 24-26 */
-+	RM_MEAS_PILOT_CAP1,
-+	RM_MEAS_PILOT_CAP2,
-+	RM_MEAS_PILOT_TRANS_INFO_CAP_EN,
-+	RM_NB_REP_TSF_OFFSET_CAP_EN,
-+	RM_RCPI_MEAS_CAP_EN,		/* 29 */
-+	RM_RSNI_MEAS_CAP_EN,
-+	RM_BSS_AVG_ACCESS_DELAY_CAP_EN,
-+
-+	RM_AVALB_ADMIS_CAPACITY_CAP_EN,
-+	RM_ANT_CAP_EN,
-+	RM_RSVD,			/* 34-39 */
-+	RM_MAX
-+};
-+
-+char *rm_state_name(enum RM_STATE state);
-+char *rm_event_name(enum RM_EV_ID evid);
-+char *rm_type_req_name(u8 meas_type);
-+int _rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid);
-+int rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *obj, bool to_head);
-+
-+void rm_free_rmobj(struct rm_obj *prm);
-+struct rm_obj *rm_alloc_rmobj(_adapter *padapter);
-+struct rm_obj *rm_get_rmobj(_adapter *padapter, u32 rmid);
-+struct sta_info *rm_get_psta(_adapter *padapter, u32 rmid);
-+
-+int retrieve_radio_meas_result(struct rm_obj *prm);
-+int rm_radio_meas_report_cond(struct rm_obj *prm);
-+int rm_recv_radio_mens_req(_adapter *padapter,
-+	union recv_frame *precv_frame,struct sta_info *psta);
-+int rm_recv_radio_mens_rep(_adapter *padapter,
-+	union recv_frame *precv_frame, struct sta_info *psta);
-+int rm_recv_link_mens_req(_adapter *padapter,
-+	union recv_frame *precv_frame,struct sta_info *psta);
-+int rm_recv_link_mens_rep(_adapter *padapter,
-+	union recv_frame *precv_frame, struct sta_info *psta);
-+int rm_radio_mens_nb_rep(_adapter *padapter,
-+	union recv_frame *precv_frame, struct sta_info *psta);
-+int issue_null_reply(struct rm_obj *prm);
-+int issue_beacon_rep(struct rm_obj *prm);
-+int issue_nb_req(struct rm_obj *prm);
-+int issue_radio_meas_req(struct rm_obj *prm);
-+int issue_radio_meas_rep(struct rm_obj *prm);
-+int issue_link_meas_req(struct rm_obj *prm);
-+int issue_link_meas_rep(struct rm_obj *prm);
-+
-+void rm_set_rep_mode(struct rm_obj *prm, u8 mode);
-+
-+int ready_for_scan(struct rm_obj *prm);
-+int rm_sitesurvey(struct rm_obj *prm);
-+
-+#endif /*CONFIG_RTW_80211K*/
-+#endif /*__RTW_RM_FSM_H_*/
-diff --git a/drivers/staging/rtl8723cs/include/rtw_rm_util.h b/drivers/staging/rtl8723cs/include/rtw_rm_util.h
-new file mode 100644
-index 000000000000..932cfb9658b9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_rm_util.h
-@@ -0,0 +1,47 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef _RTW_RM_UTIL_H_
-+#define _RTW_RM_UTIL_H_
-+/*
-+ * define the following channels as the max channels in each channel plan.
-+ * 2G, total 14 chnls
-+ * {1,2,3,4,5,6,7,8,9,10,11,12,13,14}
-+ * 5G, total 25 chnls
-+ * {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,144,149,153,157,161,165}
-+ */
-+#ifndef MAX
-+#define MAX(x, y) (((x) > (y)) ? (x) : (y))
-+#endif
-+
-+u8 rm_get_oper_class_via_ch(u8 ch);
-+u8 rm_get_ch_set( struct rtw_ieee80211_channel *pch_set, u8 op_class, u8 ch_num);
-+u8 rm_get_ch_set_from_bcn_req_opt(
-+	struct rtw_ieee80211_channel *pch_set, struct bcn_req_opt *opt);
-+u8 rm_get_bcn_rsni(struct rm_obj *prm, struct wlan_network *pnetwork);
-+u8 rm_get_bcn_rcpi(struct rm_obj *prm, struct wlan_network *pnetwork);
-+u8 rm_get_frame_rsni(struct rm_obj *prm, union recv_frame *pframe);
-+u8 translate_percentage_to_rcpi(u32 SignalStrengthIndex);
-+u8 translate_dbm_to_rcpi(s8 SignalPower);
-+u8 rm_gen_dialog_token(_adapter *padapter);
-+u8 rm_gen_meas_token(_adapter *padapter);
-+u32 rm_gen_rmid(_adapter *padapter, struct rm_obj *prm, u8 role);
-+int is_wildcard_bssid(u8 *bssid);
-+
-+int rm_get_path_a_max_tx_power(_adapter *adapter, s8 *path_a);
-+int rm_get_tx_power(PADAPTER adapter, enum rf_path path, enum MGN_RATE rate, s8 *pwr);
-+int rm_get_rx_sensitivity(PADAPTER adapter, enum channel_width bw, enum MGN_RATE rate, s8 *pwr);
-+
-+#endif /* _RTW_RM_UTIL_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_roch.h b/drivers/staging/rtl8723cs/include/rtw_roch.h
-new file mode 100644
-index 000000000000..d3de7e299b59
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_roch.h
-@@ -0,0 +1,61 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2020 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_ROCH_H__
-+#define __RTW_ROCH_H__
-+
-+#include <drv_types.h>
-+
-+struct rtw_roch_parm;
-+
-+#if (defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)) || defined(CONFIG_IOCTL_CFG80211)
-+struct roch_info {
-+#ifdef CONFIG_CONCURRENT_MODE
-+	_timer	ap_roch_ch_switch_timer;	/* Used to switch the channel between legacy AP and listen state. */
-+#ifdef CONFIG_IOCTL_CFG80211
-+	u32	min_home_dur;		/* min duration for traffic, home_time */
-+	u32	max_away_dur;		/* max acceptable away duration, home_away_time */
-+#endif
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	_timer remain_on_ch_timer;
-+	u8 restore_channel;
-+	struct ieee80211_channel remain_on_ch_channel;
-+	enum nl80211_channel_type remain_on_ch_type;
-+	ATOMIC_T ro_ch_cookie_gen;
-+	u64 remain_on_ch_cookie;
-+	bool is_ro_ch;
-+	struct wireless_dev *ro_ch_wdev;
-+	systime last_ro_ch_time;		/* this will be updated at the beginning and end of ro_ch */
-+#endif
-+};
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+u8 rtw_roch_stay_in_cur_chan(_adapter *padapter);
-+#endif
-+
-+#if (defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)) || defined(CONFIG_IOCTL_CFG80211)
-+s32 rtw_roch_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf);
-+u8 rtw_roch_wk_cmd(_adapter *padapter, int intCmdType, struct rtw_roch_parm *roch_parm, u8 flags);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+void rtw_concurrent_handler(_adapter *padapter);
-+#endif
-+
-+void rtw_init_roch_info(_adapter *padapter);
-+#endif /* (defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)) || defined(CONFIG_IOCTL_CFG80211) */
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtw_rson.h b/drivers/staging/rtl8723cs/include/rtw_rson.h
-new file mode 100644
-index 000000000000..6996738b071a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_rson.h
-@@ -0,0 +1,61 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program; if not, write to the Free Software Foundation, Inc.,
-+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
-+ *
-+ *
-+ ******************************************************************************/
-+#ifndef __RTW_RSON_H_
-+#define __RTW_RSON_H_
-+
-+
-+#define RTW_RSON_VER						1
-+
-+#define RTW_RSON_SCORE_NOTSUP			0x0
-+#define RTW_RSON_SCORE_NOTCNNT			0x1
-+#define RTW_RSON_SCORE_MAX				0xFF
-+#define RTW_RSON_HC_NOTREADY			0xFF
-+#define RTW_RSON_HC_ROOT				0x0
-+#define RTW_RSON_ALLOWCONNECT			0x1
-+#define RTW_RSON_DENYCONNECT			0x0
-+
-+
-+
-+/*	for rtw self-origanization spec 1	*/
-+struct rtw_rson_struct {
-+	u8 ver;
-+	u32 id;
-+	u8 hopcnt;
-+	u8 connectible;
-+	u8 loading;
-+	u8 res[16];
-+} __attribute__((__packed__));
-+
-+void init_rtw_rson_data(struct dvobj_priv *dvobj);
-+void rtw_rson_get_property_str(_adapter *padapter, char *rson_data_str);
-+int rtw_rson_set_property(_adapter *padapter, char *field, char *value);
-+int rtw_rson_choose(struct wlan_network **candidate, struct wlan_network *competitor);
-+int rtw_get_rson_struct(WLAN_BSSID_EX *bssid, struct  rtw_rson_struct *rson_data);
-+u8 rtw_cal_rson_score(struct rtw_rson_struct *cand_rson_data, NDIS_802_11_RSSI  Rssi);
-+void rtw_rson_handle_ie(WLAN_BSSID_EX *bssid, u8 ie_offset);
-+u32 rtw_rson_append_ie(_adapter *padapter, unsigned char *pframe, u32 *len);
-+void rtw_rson_do_disconnect(_adapter *padapter);
-+void rtw_rson_join_done(_adapter *padapter);
-+int rtw_rson_isupdate_roamcan(struct mlme_priv *mlme, struct wlan_network **candidate, struct wlan_network *competitor);
-+void rtw_rson_show_survey_info(struct seq_file *m, _list *plist, _list *phead);
-+u8 rtw_rson_ap_check_sta(_adapter *padapter, u8 *pframe, uint pkt_len, unsigned short ie_offset);
-+u8 rtw_rson_scan_wk_cmd(_adapter *padapter, int op);
-+void rtw_rson_scan_cmd_hdl(_adapter *padapter, int op);
-+#endif /* __RTW_RSON_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_sdio.h b/drivers/staging/rtl8723cs/include/rtw_sdio.h
-new file mode 100644
-index 000000000000..7490b5481328
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_sdio.h
-@@ -0,0 +1,26 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2015 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTW_SDIO_H_
-+#define _RTW_SDIO_H_
-+
-+#include <drv_types.h>		/* struct dvobj_priv and etc. */
-+
-+u8 rtw_sdio_read_cmd52(struct dvobj_priv *, u32 addr, void *buf, size_t len);
-+u8 rtw_sdio_read_cmd53(struct dvobj_priv *, u32 addr, void *buf, size_t len);
-+u8 rtw_sdio_write_cmd52(struct dvobj_priv *, u32 addr, void *buf, size_t len);
-+u8 rtw_sdio_write_cmd53(struct dvobj_priv *, u32 addr, void *buf, size_t len);
-+u8 rtw_sdio_f0_read(struct dvobj_priv *, u32 addr, void *buf, size_t len);
-+
-+#endif /* _RTW_SDIO_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_security.h b/drivers/staging/rtl8723cs/include/rtw_security.h
-new file mode 100644
-index 000000000000..9cceed6973b3
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_security.h
-@@ -0,0 +1,421 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_SECURITY_H_
-+#define __RTW_SECURITY_H_
-+
-+enum security_type {
-+	/* TYPE */
-+	_NO_PRIVACY_	= 0x00,
-+	_WEP40_		= 0x01,
-+	_TKIP_		= 0x02,
-+	_TKIP_WTMIC_	= 0x03,
-+	_AES_		= 0x04,
-+	_WEP104_	= 0x05,
-+	_SMS4_		= 0x06,
-+	_GCMP_		= 0x07,
-+	_SEC_TYPE_MAX_,
-+
-+	/* EXT_SECTYPE=1 */
-+	_SEC_TYPE_256_	= 0x10,
-+	_CCMP_256_	= (_AES_ | _SEC_TYPE_256_),
-+	_GCMP_256_	= (_GCMP_ | _SEC_TYPE_256_),
-+
-+#ifdef CONFIG_IEEE80211W
-+	/* EXT_SECTYPE=0, MGNT=1, GK=0/1, KEYID=00/01 */
-+	_SEC_TYPE_BIT_	= 0x20,
-+	_BIP_CMAC_128_	= (_SEC_TYPE_BIT_),
-+	_BIP_GMAC_128_	= (_SEC_TYPE_BIT_ + 1),
-+	_BIP_GMAC_256_	= (_SEC_TYPE_BIT_ + 2),
-+	/* EXT_SECTYPE=1, MGNT=1, GK=1, KEYID=00/01 */
-+	_BIP_CMAC_256_	= (_SEC_TYPE_BIT_ + 3),
-+	_BIP_MAX_,
-+#endif
-+};
-+
-+/* 802.11W use wrong key */
-+#define IEEE80211W_RIGHT_KEY	0x0
-+#define IEEE80211W_WRONG_KEY	0x1
-+#define IEEE80211W_NO_KEY		0x2
-+
-+#define CCMPH_2_PN(ch)	((ch) & 0x000000000000ffff) \
-+			| (((ch) & 0xffffffff00000000) >> 16)
-+
-+#define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_))
-+
-+const char *security_type_str(u8 value);
-+#ifdef CONFIG_IEEE80211W
-+u32 security_type_bip_to_gmcs(enum security_type type);
-+#endif
-+
-+#define _WPA_IE_ID_	0xdd
-+#define _WPA2_IE_ID_	0x30
-+
-+#define RTW_KEK_LEN 16
-+#define RTW_KCK_LEN 16
-+#define RTW_TKIP_MIC_LEN 8
-+#define RTW_REPLAY_CTR_LEN 8
-+
-+#define INVALID_SEC_MAC_CAM_ID	0xFF
-+
-+typedef enum {
-+	ENCRYP_PROTOCOL_OPENSYS,   /* open system */
-+	ENCRYP_PROTOCOL_WEP,       /* WEP */
-+	ENCRYP_PROTOCOL_WPA,       /* WPA */
-+	ENCRYP_PROTOCOL_WPA2,      /* WPA2 */
-+	ENCRYP_PROTOCOL_WAPI,      /* WAPI: Not support in this version */
-+	ENCRYP_PROTOCOL_MAX
-+} ENCRYP_PROTOCOL_E;
-+
-+
-+#ifndef Ndis802_11AuthModeWPA2
-+#define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1)
-+#endif
-+
-+#ifndef Ndis802_11AuthModeWPA2PSK
-+#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2)
-+#endif
-+
-+union pn48	{
-+
-+	u64	val;
-+
-+#ifdef CONFIG_LITTLE_ENDIAN
-+
-+struct {
-+	u8 TSC0;
-+	u8 TSC1;
-+	u8 TSC2;
-+	u8 TSC3;
-+	u8 TSC4;
-+	u8 TSC5;
-+	u8 TSC6;
-+	u8 TSC7;
-+} _byte_;
-+
-+#elif defined(CONFIG_BIG_ENDIAN)
-+
-+struct {
-+	u8 TSC7;
-+	u8 TSC6;
-+	u8 TSC5;
-+	u8 TSC4;
-+	u8 TSC3;
-+	u8 TSC2;
-+	u8 TSC1;
-+	u8 TSC0;
-+} _byte_;
-+
-+#endif
-+
-+};
-+
-+union Keytype {
-+	u8 skey[32];
-+};
-+
-+typedef struct _RT_PMKID_LIST {
-+	u8						bUsed;
-+	u8						Bssid[6];
-+	u8						PMKID[16];
-+	u8						SsidBuf[33];
-+	u8						*ssid_octet;
-+	u16						ssid_length;
-+} RT_PMKID_LIST, *PRT_PMKID_LIST;
-+
-+
-+struct security_priv {
-+	u32	  dot11AuthAlgrthm;		/* 802.11 auth, could be open, shared, 8021x and authswitch */
-+	u32	  dot11PrivacyAlgrthm;	/* This specify the privacy for shared auth. algorithm. */
-+
-+	/* WEP */
-+	u32	  dot11PrivacyKeyIndex;	/* this is only valid for legendary wep, 0~3 for key id. (tx key index) */
-+	union Keytype dot11DefKey[6];			/* this is only valid for def. key	 */
-+	u32	dot11DefKeylen[6];
-+	u8	dot11Def_camid[6];
-+	u8 	key_mask; /* use to restore wep key after hal_init */
-+
-+	u32 dot118021XGrpPrivacy;	/* This specify the privacy algthm. used for Grp key */
-+	u32	dot118021XGrpKeyid;		/* key id used for Grp Key ( tx key index) */
-+	union Keytype	dot118021XGrpKey[6];	/* 802.1x Group Key, for inx0 and inx1	 */
-+	union Keytype	dot118021XGrptxmickey[6];
-+	union Keytype	dot118021XGrprxmickey[6];
-+	union pn48		dot11Grptxpn;			/* PN48 used for Grp Key xmit. */
-+	union pn48		dot11Grprxpn;			/* PN48 used for Grp Key recv. */
-+	u8				iv_seq[4][8];
-+#ifdef CONFIG_IEEE80211W
-+	enum security_type dot11wCipher;
-+	u32	dot11wBIPKeyid;						/* key id used for BIP Key ( tx key index) */
-+	union Keytype	dot11wBIPKey[6];		/* BIP Key, for index4 and index5 */
-+	union pn48		dot11wBIPtxpn;			/* PN48 used for BIP xmit. */
-+	union pn48		dot11wBIPrxpn;			/* PN48 used for BIP recv. */
-+#endif /* CONFIG_IEEE80211W */
-+#ifdef CONFIG_AP_MODE
-+	/* extend security capabilities for AP_MODE */
-+	unsigned int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */
-+	unsigned int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */
-+	unsigned int wpa_group_cipher;
-+	unsigned int wpa2_group_cipher;
-+	unsigned int wpa_pairwise_cipher;
-+	unsigned int wpa2_pairwise_cipher;
-+	unsigned int akmp; /* An authentication and key management protocol */
-+#endif
-+	u8 mfp_opt;
-+	u8	dot118021x_bmc_cam_id;
-+	/*IEEE802.11-2012 Std. Table 8-101 AKM Suite Selectors*/
-+	u32	rsn_akm_suite_type;
-+
-+	u8 wps_ie[MAX_WPS_IE_LEN];/* added in assoc req */
-+	int wps_ie_len;
-+
-+	u8 owe_ie[MAX_OWE_IE_LEN];/* added in assoc req */
-+	int owe_ie_len;
-+
-+	u8	binstallGrpkey;
-+#ifdef CONFIG_GTK_OL
-+	u8	binstallKCK_KEK;
-+#endif /* CONFIG_GTK_OL */
-+#ifdef CONFIG_IEEE80211W
-+	u8	binstallBIPkey;
-+#endif /* CONFIG_IEEE80211W */
-+	u8	busetkipkey;
-+	u8	bcheck_grpkey;
-+	u8	bgrpkey_handshake;
-+
-+	u8	auth_alg;
-+	u8	auth_type;
-+	u8	extauth_status;
-+	/* u8	packet_cnt; */ /* unused, removed */
-+
-+	s32	sw_encrypt;/* from registry_priv */
-+	s32	sw_decrypt;/* from registry_priv */
-+
-+	s32 	hw_decrypted;/* if the rx packets is hw_decrypted==_FALSE, it means the hw has not been ready. */
-+
-+
-+	/* keeps the auth_type & enc_status from upper layer ioctl(wpa_supplicant or wzc) */
-+	u32 ndisauthtype;	/* NDIS_802_11_AUTHENTICATION_MODE */
-+	u32 ndisencryptstatus;	/* NDIS_802_11_ENCRYPTION_STATUS */
-+
-+	NDIS_802_11_WEP ndiswep;
-+
-+	u8 assoc_info[600];
-+	u8 szofcapability[256]; /* for wpa2 usage */
-+	u8 oidassociation[512]; /* for wpa/wpa2 usage */
-+	u8 authenticator_ie[256];  /* store ap security information element */
-+	u8 supplicant_ie[256];  /* store sta security information element */
-+
-+
-+	/* for tkip countermeasure */
-+	systime last_mic_err_time;
-+	u8	btkip_countermeasure;
-+	u8	btkip_wait_report;
-+	systime btkip_countermeasure_time;
-+
-+	/* --------------------------------------------------------------------------- */
-+	/* For WPA2 Pre-Authentication. */
-+	/* --------------------------------------------------------------------------- */
-+	/* u8				RegEnablePreAuth;				 */ /* Default value: Pre-Authentication enabled or not, from registry "EnablePreAuth". Added by Annie, 2005-11-01. */
-+	/* u8				EnablePreAuthentication;			 */ /* Current Value: Pre-Authentication enabled or not. */
-+	RT_PMKID_LIST		PMKIDList[NUM_PMKID_CACHE];	/* Renamed from PreAuthKey[NUM_PRE_AUTH_KEY]. Annie, 2006-10-13. */
-+	u8				PMKIDIndex;
-+	/* u32				PMKIDCount;						 */ /* Added by Annie, 2006-10-13. */
-+	/* u8				szCapability[256];				 */ /* For WPA2-PSK using zero-config, by Annie, 2005-09-20. */
-+
-+	u8 bWepDefaultKeyIdxSet;
-+
-+#define DBG_SW_SEC_CNT
-+#ifdef DBG_SW_SEC_CNT
-+	u64 wep_sw_enc_cnt_bc;
-+	u64 wep_sw_enc_cnt_mc;
-+	u64 wep_sw_enc_cnt_uc;
-+	u64 wep_sw_dec_cnt_bc;
-+	u64 wep_sw_dec_cnt_mc;
-+	u64 wep_sw_dec_cnt_uc;
-+
-+	u64 tkip_sw_enc_cnt_bc;
-+	u64 tkip_sw_enc_cnt_mc;
-+	u64 tkip_sw_enc_cnt_uc;
-+	u64 tkip_sw_dec_cnt_bc;
-+	u64 tkip_sw_dec_cnt_mc;
-+	u64 tkip_sw_dec_cnt_uc;
-+
-+	u64 aes_sw_enc_cnt_bc;
-+	u64 aes_sw_enc_cnt_mc;
-+	u64 aes_sw_enc_cnt_uc;
-+	u64 aes_sw_dec_cnt_bc;
-+	u64 aes_sw_dec_cnt_mc;
-+	u64 aes_sw_dec_cnt_uc;
-+
-+	u64 gcmp_sw_enc_cnt_bc;
-+	u64 gcmp_sw_enc_cnt_mc;
-+	u64 gcmp_sw_enc_cnt_uc;
-+	u64 gcmp_sw_dec_cnt_bc;
-+	u64 gcmp_sw_dec_cnt_mc;
-+	u64 gcmp_sw_dec_cnt_uc;
-+#endif /* DBG_SW_SEC_CNT */
-+};
-+
-+#ifdef CONFIG_IEEE80211W
-+#define SEC_IS_BIP_KEY_INSTALLED(sec) ((sec)->binstallBIPkey)
-+#else
-+#define SEC_IS_BIP_KEY_INSTALLED(sec) _FALSE
-+#endif
-+
-+#define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst)\
-+	do {\
-+		switch (psecuritypriv->dot11AuthAlgrthm) {\
-+		case dot11AuthAlgrthm_Open:\
-+		case dot11AuthAlgrthm_Shared:\
-+		case dot11AuthAlgrthm_Auto:\
-+			encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\
-+			break;\
-+		case dot11AuthAlgrthm_8021X:\
-+			if (bmcst)\
-+				encry_algo = (u8)psecuritypriv->dot118021XGrpPrivacy;\
-+			else\
-+				encry_algo = (u8) psta->dot118021XPrivacy;\
-+			break;\
-+		case dot11AuthAlgrthm_WAPI:\
-+			encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\
-+			break;\
-+		} \
-+	} while (0)
-+
-+#define _AES_IV_LEN_ 8
-+
-+#define SET_ICE_IV_LEN(iv_len, icv_len, encrypt)\
-+	do {\
-+		switch (encrypt) {\
-+		case _WEP40_:\
-+		case _WEP104_:\
-+			iv_len = 4;\
-+			icv_len = 4;\
-+			break;\
-+		case _TKIP_:\
-+			iv_len = 8;\
-+			icv_len = 4;\
-+			break;\
-+		case _AES_:\
-+			iv_len = 8;\
-+			icv_len = 8;\
-+			break;\
-+		case _GCMP_:\
-+		case _GCMP_256_:\
-+			iv_len = 8;\
-+			icv_len = 16;\
-+			break;\
-+		case _CCMP_256_:\
-+			iv_len = 8;\
-+			icv_len = 16;\
-+			break;\
-+		case _SMS4_:\
-+			iv_len = 18;\
-+			icv_len = 16;\
-+			break;\
-+		default:\
-+			iv_len = 0;\
-+			icv_len = 0;\
-+			break;\
-+		} \
-+	} while (0)
-+
-+
-+#define GET_TKIP_PN(iv, dot11txpn)\
-+	do {\
-+		dot11txpn._byte_.TSC0 = iv[2];\
-+		dot11txpn._byte_.TSC1 = iv[0];\
-+		dot11txpn._byte_.TSC2 = iv[4];\
-+		dot11txpn._byte_.TSC3 = iv[5];\
-+		dot11txpn._byte_.TSC4 = iv[6];\
-+		dot11txpn._byte_.TSC5 = iv[7];\
-+	} while (0)
-+
-+
-+#define ROL32(A, n)	(((A) << (n)) | (((A)>>(32-(n)))  & ((1UL << (n)) - 1)))
-+#define ROR32(A, n)	ROL32((A), 32-(n))
-+
-+struct mic_data {
-+	u32  K0, K1;         /* Key */
-+	u32  L, R;           /* Current state */
-+	u32  M;              /* Message accumulator (single word) */
-+	u32     nBytesInM;      /*  # bytes in M */
-+};
-+
-+void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key);
-+void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b);
-+void rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nBytes);
-+void rtw_secgetmic(struct mic_data *pmicdata, u8 *dst);
-+
-+void rtw_seccalctkipmic(
-+	u8 *key,
-+	u8 *header,
-+	u8 *data,
-+	u32 data_len,
-+	u8 *Miccode,
-+	u8   priority);
-+
-+u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe);
-+u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe);
-+void rtw_wep_encrypt(_adapter *padapter, u8  *pxmitframe);
-+
-+u32 rtw_aes_decrypt(_adapter *padapter, u8  *precvframe);
-+u32 rtw_tkip_decrypt(_adapter *padapter, u8  *precvframe);
-+void rtw_wep_decrypt(_adapter *padapter, u8  *precvframe);
-+
-+u32 rtw_gcmp_encrypt(_adapter *padapter, u8 *pxmitframe);
-+u32 rtw_gcmp_decrypt(_adapter *padapter, u8 *precvframe);
-+
-+#ifdef CONFIG_RTW_MESH_AEK
-+int rtw_aes_siv_encrypt(const u8 *key, size_t key_len,
-+	const u8 *pw, size_t pwlen, size_t num_elem,
-+	const u8 *addr[], const size_t *len, u8 *out);
-+int rtw_aes_siv_decrypt(const u8 *key, size_t key_len,
-+	const u8 *iv_crypt, size_t iv_c_len, size_t num_elem,
-+	const u8 *addr[], const size_t *len, u8 *out);
-+#endif /* CONFIG_RTW_MESH_AEK */
-+
-+#ifdef CONFIG_IEEE80211W
-+u8 rtw_calculate_bip_mic(enum security_type gmcs, u8 *whdr_pos, s32 len,
-+	const u8 *key, const u8 *data, size_t data_len, u8 *mic);
-+u32 rtw_bip_verify(enum security_type gmcs, u16 pkt_len,
-+	u8 *whdr_pos, sint flen, const u8 *key, u16 keyid, u64 *ipn);
-+#endif
-+#ifdef CONFIG_TDLS
-+void wpa_tdls_generate_tpk(_adapter *padapter, void *sta);
-+int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq,
-+			u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie,
-+			u8 *mic);
-+int wpa_tdls_teardown_ftie_mic(u8 *kck, u8 *lnkid, u16 reason,
-+			u8 dialog_token, u8 trans_seq, u8 *ftie, u8 *mic);
-+int tdls_verify_mic(u8 *kck, u8 trans_seq,
-+			u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie);
-+#endif /* CONFIG_TDLS */
-+
-+void rtw_sec_restore_wep_key(_adapter *adapter);
-+u8 rtw_handle_tkip_countermeasure(_adapter *adapter, const char *caller);
-+
-+#ifdef CONFIG_WOWLAN
-+u16 rtw_calc_crc(u8  *pdata, int length);
-+#endif /*CONFIG_WOWLAN*/
-+
-+#define rtw_sec_chk_auth_alg(a, s) \
-+	((a)->securitypriv.auth_alg == (s))
-+
-+#define rtw_sec_chk_auth_type(a, s) \
-+	((a)->securitypriv.auth_type == (s))
-+
-+#endif /* __RTL871X_SECURITY_H_ */
-+
-+u32 rtw_calc_crc32(u8 *data, size_t len);
-diff --git a/drivers/staging/rtl8723cs/include/rtw_sreset.h b/drivers/staging/rtl8723cs/include/rtw_sreset.h
-new file mode 100644
-index 000000000000..1fd999a9d76e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_sreset.h
-@@ -0,0 +1,66 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTW_SRESET_H_
-+#define _RTW_SRESET_H_
-+
-+/* #include <drv_types.h> */
-+
-+enum {
-+	SRESET_TGP_NULL = 0,
-+	SRESET_TGP_XMIT_STATUS = 1,
-+	SRESET_TGP_LINK_STATUS = 2,
-+	SRESET_TGP_INFO = 99,
-+};
-+
-+struct sreset_priv {
-+	_mutex	silentreset_mutex;
-+	u8	silent_reset_inprogress;
-+	u8	Wifi_Error_Status;
-+	systime last_tx_time;
-+	systime last_tx_complete_time;
-+
-+	s32 dbg_trigger_point;
-+	u64 self_dect_tx_cnt;
-+	u64 self_dect_rx_cnt;
-+	u64 self_dect_fw_cnt;
-+	u64 tx_dma_status_cnt;
-+	u64 rx_dma_status_cnt;
-+	u8 rx_cnt;
-+	u8 self_dect_fw;
-+	u8 self_dect_case;
-+	u16 last_mac_rxff_ptr;
-+	u8 dbg_sreset_ctrl;
-+};
-+
-+
-+
-+#define	WIFI_STATUS_SUCCESS		0
-+#define	USB_VEN_REQ_CMD_FAIL	BIT0
-+#define	USB_READ_PORT_FAIL		BIT1
-+#define	USB_WRITE_PORT_FAIL		BIT2
-+#define	WIFI_MAC_TXDMA_ERROR	BIT3
-+#define   WIFI_TX_HANG				BIT4
-+#define	WIFI_RX_HANG				BIT5
-+#define	WIFI_IF_NOT_EXIST			BIT6
-+
-+void sreset_init_value(_adapter *padapter);
-+void sreset_reset_value(_adapter *padapter);
-+u8 sreset_get_wifi_status(_adapter *padapter);
-+void sreset_set_wifi_error_status(_adapter *padapter, u32 status);
-+void sreset_set_trigger_point(_adapter *padapter, s32 tgp);
-+bool sreset_inprogress(_adapter *padapter);
-+void sreset_reset(_adapter *padapter);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtw_swcrypto.h b/drivers/staging/rtl8723cs/include/rtw_swcrypto.h
-new file mode 100644
-index 000000000000..b00878ea8142
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_swcrypto.h
-@@ -0,0 +1,49 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __RTW_SWCRYPTO_H_
-+#define __RTW_SWCRYPTO_H_
-+
-+#define NEW_CRYPTO 1
-+
-+int _rtw_ccmp_encrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen);
-+int _rtw_ccmp_decrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen);
-+
-+int _rtw_gcmp_encrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen);
-+int _rtw_gcmp_decrypt(u8 *key, u32 key_len, uint hdrlen, u8 *frame, uint plen);
-+
-+#ifdef CONFIG_RTW_MESH_AEK
-+int _aes_siv_encrypt(const u8 *key, size_t key_len,
-+	const u8 *pw, size_t pwlen,
-+	size_t num_elem, const u8 *addr[], const size_t *len, u8 *out);
-+int _aes_siv_decrypt(const u8 *key, size_t key_len,
-+	const u8 *iv_crypt, size_t iv_c_len,
-+	size_t num_elem, const u8 *addr[], const size_t *len, u8 *out);
-+#endif
-+
-+#if defined(CONFIG_IEEE80211W) | defined(CONFIG_TDLS)
-+u8 _bip_ccmp_protect(const u8 *key, size_t key_len,
-+	const u8 *data, size_t data_len, u8 *mic);
-+u8 _bip_gcmp_protect(u8 *whdr_pos, size_t len,
-+	const u8 *key, size_t key_len,
-+	const u8 *data, size_t data_len, u8 *mic);
-+#endif /* CONFIG_IEEE80211W */
-+
-+#ifdef CONFIG_TDLS
-+void _tdls_generate_tpk(void *sta, const u8 *own_addr, const u8 *bssid);
-+#endif /* CONFIG_TDLS */
-+
-+#endif /* __RTW_SWCRYPTO_H_ */
-+
-diff --git a/drivers/staging/rtl8723cs/include/rtw_tdls.h b/drivers/staging/rtl8723cs/include/rtw_tdls.h
-new file mode 100644
-index 000000000000..5c23e4ea4c2f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_tdls.h
-@@ -0,0 +1,185 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_TDLS_H_
-+#define __RTW_TDLS_H_
-+
-+
-+#ifdef CONFIG_TDLS
-+/* TDLS STA state */
-+
-+
-+/* TDLS Diect Link Establishment */
-+#define	TDLS_STATE_NONE				0x00000000		/* Default state */
-+#define	TDLS_INITIATOR_STATE		BIT(28)			/* 0x10000000 */
-+#define	TDLS_RESPONDER_STATE		BIT(29)			/* 0x20000000 */
-+#define	TDLS_LINKED_STATE			BIT(30)			/* 0x40000000 */
-+/* TDLS PU Buffer STA */
-+#define	TDLS_WAIT_PTR_STATE			BIT(24)			/* 0x01000000 */	/* Waiting peer's TDLS_PEER_TRAFFIC_RESPONSE frame */
-+/* TDLS Check ALive */
-+#define	TDLS_ALIVE_STATE			BIT(20)			/* 0x00100000 */	/* Check if peer sta is alived. */
-+/* TDLS Channel Switch */
-+#define	TDLS_CH_SWITCH_PREPARE_STATE	BIT(15)			/* 0x00008000 */
-+#define	TDLS_CH_SWITCH_ON_STATE			BIT(16)			/* 0x00010000 */
-+#define	TDLS_PEER_AT_OFF_STATE			BIT(17)			/* 0x00020000 */	/* Could send pkt on target ch */
-+#define	TDLS_CH_SW_INITIATOR_STATE		BIT(18)			/* 0x00040000 */	/* Avoid duplicated or unconditional ch. switch rsp. */
-+#define	TDLS_WAIT_CH_RSP_STATE			BIT(19)			/* 0x00080000 */	/* Wait Ch. response as we are TDLS channel switch initiator */
-+
-+
-+#define	TDLS_TPK_RESEND_COUNT			86400	/*Unit: seconds */
-+#define	TDLS_CH_SWITCH_TIME				15
-+#define	TDLS_CH_SWITCH_TIMEOUT			30
-+#define	TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT	10
-+#define	TDLS_SIGNAL_THRESH			0x20
-+#define	TDLS_WATCHDOG_PERIOD		10	/* Periodically sending tdls discovery request in TDLS_WATCHDOG_PERIOD * 2 sec */
-+#define	TDLS_HANDSHAKE_TIME			3000
-+#define	TDLS_PTI_TIME				7000
-+
-+#define TDLS_CH_SW_STAY_ON_BASE_CHNL_TIMEOUT	20		/* ms */
-+#define TDLS_CH_SW_MONITOR_TIMEOUT				2000	/*ms */
-+
-+#define TDLS_MIC_LEN 16
-+#define WPA_NONCE_LEN 32
-+#define TDLS_TIMEOUT_LEN 4
-+
-+enum TDLS_CH_SW_CHNL {
-+	TDLS_CH_SW_BASE_CHNL = 0,
-+	TDLS_CH_SW_OFF_CHNL
-+};
-+
-+#define TDLS_MIC_CTRL_LEN 2
-+#define TDLS_FTIE_DATA_LEN (TDLS_MIC_CTRL_LEN + TDLS_MIC_LEN + \
-+							WPA_NONCE_LEN + WPA_NONCE_LEN)
-+struct wpa_tdls_ftie {
-+	u8 ie_type; /* FTIE */
-+	u8 ie_len;
-+	union {
-+		struct {
-+			u8 mic_ctrl[TDLS_MIC_CTRL_LEN];
-+			u8 mic[TDLS_MIC_LEN];
-+			u8 Anonce[WPA_NONCE_LEN]; /* Responder Nonce in TDLS */
-+			u8 Snonce[WPA_NONCE_LEN]; /* Initiator Nonce in TDLS */
-+		};
-+		struct {
-+			u8 data[TDLS_FTIE_DATA_LEN];
-+		};
-+	};
-+	/* followed by optional elements */
-+} ;
-+
-+struct wpa_tdls_lnkid {
-+	u8 ie_type; /* Link Identifier IE */
-+	u8 ie_len;
-+	u8 bssid[ETH_ALEN];
-+	u8 init_sta[ETH_ALEN];
-+	u8 resp_sta[ETH_ALEN];
-+} ;
-+
-+static u8 TDLS_RSNIE[20] = {	0x01, 0x00,	/* Version shall be set to 1 */
-+				0x00, 0x0f, 0xac, 0x07,	/* Group sipher suite */
-+				0x01, 0x00,	/* Pairwise cipher suite count */
-+	0x00, 0x0f, 0xac, 0x04,	/* Pairwise cipher suite list; CCMP only */
-+				0x01, 0x00,	/* AKM suite count */
-+				0x00, 0x0f, 0xac, 0x07,	/* TPK Handshake */
-+				0x0c, 0x02,
-+				/* PMKID shall not be present */
-+			   };
-+
-+static u8 TDLS_WMMIE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00};	/* Qos info all set zero */
-+
-+static u8 TDLS_WMM_PARAM_IE[] = {0x00, 0x00, 0x03, 0xa4, 0x00, 0x00, 0x27, 0xa4, 0x00, 0x00, 0x42, 0x43, 0x5e, 0x00, 0x62, 0x32, 0x2f, 0x00};
-+
-+static u8 TDLS_EXT_CAPIE[] = {0x00, 0x00, 0x00, 0x50, 0x20, 0x00, 0x00, 0x00};	/* bit(28), bit(30), bit(37) */
-+
-+/* SRC: Supported Regulatory Classes */
-+static u8 TDLS_SRC[] = { 0x01, 0x01, 0x02, 0x03, 0x04, 0x0c, 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1d, 0x1e, 0x20, 0x21 };
-+
-+int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len);
-+int check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len);
-+
-+void rtw_set_tdls_enable(_adapter *padapter, u8 enable);
-+u8 rtw_is_tdls_enabled(_adapter *padapter);
-+u8 rtw_is_tdls_sta_existed(_adapter *padapter);
-+u8 rtw_tdls_is_setup_allowed(_adapter *padapter);
-+#ifdef CONFIG_TDLS_CH_SW
-+u8 rtw_tdls_is_chsw_allowed(_adapter *padapter);
-+#endif
-+
-+void rtw_tdls_set_link_established(_adapter *adapter, bool en);
-+void rtw_reset_tdls_info(_adapter *padapter);
-+int rtw_init_tdls_info(_adapter *padapter);
-+void rtw_free_tdls_info(struct tdls_info *ptdlsinfo);
-+void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd);
-+void rtw_enable_tdls_func(_adapter *padapter);
-+void rtw_disable_tdls_func(_adapter *padapter, u8 enqueue_cmd);
-+int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms);
-+void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta);
-+void	rtw_cancel_tdls_timer(struct sta_info *psta);
-+void rtw_tdls_teardown_pre_hdl(_adapter *padapter, struct sta_info *psta);
-+void rtw_tdls_teardown_post_hdl(_adapter *padapter, struct sta_info *psta, u8 enqueue_cmd);
-+
-+#ifdef CONFIG_TDLS_CH_SW
-+void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable);
-+void rtw_tdls_ch_sw_back_to_base_chnl(_adapter *padapter);
-+s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_type, u8 channel, u8 channel_offset, u16 bwmode, u16 ch_switch_time);
-+void rtw_tdls_chsw_oper_done(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_WFD
-+int issue_tunneled_probe_req(_adapter *padapter);
-+int issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame);
-+#endif /* CONFIG_WFD */
-+int issue_tdls_dis_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt);
-+int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack);
-+int issue_tdls_setup_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt);
-+int issue_tdls_setup_cfm(_adapter *padapter, struct tdls_txmgmt *ptxmgmt);
-+int issue_tdls_dis_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 privacy);
-+int issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack);
-+int issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *psta, struct tdls_txmgmt *ptxmgmt);
-+int issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *psta);
-+#ifdef CONFIG_TDLS_CH_SW
-+int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta);
-+int issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack);
-+#endif
-+sint On_TDLS_Dis_Rsp(_adapter *adapter, union recv_frame *precv_frame);
-+sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
-+int On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
-+int On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
-+int On_TDLS_Dis_Req(_adapter *adapter, union recv_frame *precv_frame);
-+int On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
-+int On_TDLS_Peer_Traffic_Indication(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
-+int On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
-+#ifdef CONFIG_TDLS_CH_SW
-+sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
-+sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta);
-+void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
-+void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
-+#endif
-+void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
-+void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
-+void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
-+void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
-+void rtw_build_tdls_dis_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt);
-+void rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, u8 privacy);
-+void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
-+void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta);
-+void rtw_build_tunneled_probe_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe);
-+void rtw_build_tunneled_probe_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe);
-+
-+int rtw_tdls_is_driver_setup(_adapter *padapter);
-+void rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta);
-+const char *rtw_tdls_action_txt(enum TDLS_ACTION_FIELD action);
-+#endif /* CONFIG_TDLS */
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtw_version.h b/drivers/staging/rtl8723cs/include/rtw_version.h
-new file mode 100644
-index 000000000000..667edeae05d1
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_version.h
-@@ -0,0 +1,3 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+#define DRIVERVERSION	"v5.12.2-7-g2de5ec386.20201013_beta"
-+#define BTCOEXVERSION	"COEX20180330-1e00"
-diff --git a/drivers/staging/rtl8723cs/include/rtw_vht.h b/drivers/staging/rtl8723cs/include/rtw_vht.h
-new file mode 100644
-index 000000000000..f08ac4f19d6e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_vht.h
-@@ -0,0 +1,184 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTW_VHT_H_
-+#define _RTW_VHT_H_
-+
-+#define VHT_CAP_IE_LEN 12
-+#define VHT_OP_IE_LEN 5
-+
-+#define	LDPC_VHT_ENABLE_RX			BIT0
-+#define	LDPC_VHT_ENABLE_TX			BIT1
-+#define	LDPC_VHT_TEST_TX_ENABLE		BIT2
-+#define	LDPC_VHT_CAP_TX				BIT3
-+
-+#define	STBC_VHT_ENABLE_RX			BIT0
-+#define	STBC_VHT_ENABLE_TX			BIT1
-+#define	STBC_VHT_TEST_TX_ENABLE		BIT2
-+#define	STBC_VHT_CAP_TX				BIT3
-+
-+/* VHT capability info */
-+#define SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val)
-+#define SET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 2, _val)
-+#define SET_VHT_CAPABILITY_ELE_RX_LDPC(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 1, _val)
-+#define SET_VHT_CAPABILITY_ELE_SHORT_GI80M(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(_pEleStart, 5, 1, _val)
-+#define SET_VHT_CAPABILITY_ELE_SHORT_GI160M(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(_pEleStart, 6, 1, _val)
-+#define SET_VHT_CAPABILITY_ELE_TX_STBC(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val)
-+#define SET_VHT_CAPABILITY_ELE_RX_STBC(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 0, 3, _val)
-+#define SET_VHT_CAPABILITY_ELE_SU_BFER(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 3, 1, _val)
-+#define SET_VHT_CAPABILITY_ELE_SU_BFEE(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 4, 1, _val)
-+#define SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 5, 3, _val)
-+#define SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 0, 3, _val)
-+
-+#define SET_VHT_CAPABILITY_ELE_MU_BFER(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 3, 1, _val)
-+#define SET_VHT_CAPABILITY_ELE_MU_BFEE(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 4, 1, _val)
-+#define SET_VHT_CAPABILITY_ELE_TXOP_PS(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 5, 1, _val)
-+#define SET_VHT_CAPABILITY_ELE_HTC_VHT(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 1, _val)
-+#define SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(_pEleStart, _val)		SET_BITS_TO_LE_2BYTE((_pEleStart)+2, 7, 3, _val) /* B23~B25 */
-+#define SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE((_pEleStart)+3, 2, 2, _val)
-+#define SET_VHT_CAPABILITY_ELE_MCS_RX_MAP(_pEleStart, _val)				SET_BITS_TO_LE_2BYTE((_pEleStart)+4, 0, 16, _val)   /* B0~B15 indicate Rx MCS MAP, we write 0 to indicate MCS0~7. by page */
-+#define SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(_pEleStart, _val)				SET_BITS_TO_LE_2BYTE((_pEleStart)+6, 0, 13, _val)
-+#define SET_VHT_CAPABILITY_ELE_MCS_TX_MAP(_pEleStart, _val)				SET_BITS_TO_LE_2BYTE((_pEleStart)+8, 0, 16, _val)   /* B0~B15 indicate Tx MCS MAP, we write 0 to indicate MCS0~7. by page */
-+#define SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(_pEleStart, _val)				SET_BITS_TO_LE_2BYTE((_pEleStart)+10, 0, 13, _val)
-+
-+
-+#define GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart)			LE_BITS_TO_1BYTE(_pEleStart, 0, 2)
-+#define GET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 2, 2)
-+#define GET_VHT_CAPABILITY_ELE_RX_LDPC(_pEleStart)			LE_BITS_TO_1BYTE(_pEleStart, 4, 1)
-+#define GET_VHT_CAPABILITY_ELE_SHORT_GI80M(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 5, 1)
-+#define GET_VHT_CAPABILITY_ELE_SHORT_GI160M(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 6, 1)
-+#define GET_VHT_CAPABILITY_ELE_TX_STBC(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 7, 1)
-+#define GET_VHT_CAPABILITY_ELE_RX_STBC(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+1, 0, 3)
-+#define GET_VHT_CAPABILITY_ELE_SU_BFER(_pEleStart)					LE_BITS_TO_1BYTE((_pEleStart)+1, 3, 1)
-+#define GET_VHT_CAPABILITY_ELE_SU_BFEE(_pEleStart)					LE_BITS_TO_1BYTE((_pEleStart)+1, 4, 1)
-+/*phydm-beamforming*/
-+#define GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(_pEleStart)	LE_BITS_TO_2BYTE((_pEleStart)+1, 5, 3)
-+#define GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(_pEleStart)	LE_BITS_TO_2BYTE((_pEleStart)+2, 0, 3)
-+#define GET_VHT_CAPABILITY_ELE_MU_BFER(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+2, 3, 1)
-+#define GET_VHT_CAPABILITY_ELE_MU_BFEE(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+2, 4, 1)
-+#define GET_VHT_CAPABILITY_ELE_TXOP_PS(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+2, 5, 1)
-+#define GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(_pEleStart)	LE_BITS_TO_2BYTE((_pEleStart)+2, 7, 3)
-+#define GET_VHT_CAPABILITY_ELE_RX_MCS(_pEleStart)					       ((_pEleStart)+4)
-+#define GET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(_pEleStart)			LE_BITS_TO_2BYTE((_pEleStart)+6, 0, 13)
-+#define GET_VHT_CAPABILITY_ELE_TX_MCS(_pEleStart)					       ((_pEleStart)+8)
-+#define GET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(_pEleStart)			LE_BITS_TO_2BYTE((_pEleStart)+10, 0, 13)
-+
-+
-+/* VHT Operation Information Element */
-+#define SET_VHT_OPERATION_ELE_CHL_WIDTH(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 8, _val)
-+#define SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart+1, 0, 8, _val)
-+#define SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart+2, 0, 8, _val)
-+#define SET_VHT_OPERATION_ELE_BASIC_MCS_SET(_pEleStart, _val)			SET_BITS_TO_LE_2BYTE((_pEleStart)+3, 0, 16, _val)
-+
-+#define GET_VHT_OPERATION_ELE_CHL_WIDTH(_pEleStart)		LE_BITS_TO_1BYTE(_pEleStart, 0, 8)
-+#define GET_VHT_OPERATION_ELE_CENTER_FREQ1(_pEleStart)	LE_BITS_TO_1BYTE((_pEleStart)+1, 0, 8)
-+#define GET_VHT_OPERATION_ELE_CENTER_FREQ2(_pEleStart)     LE_BITS_TO_1BYTE((_pEleStart)+2, 0, 8)
-+
-+/* VHT Operating Mode */
-+#define SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val)
-+#define SET_VHT_OPERATING_MODE_FIELD_RX_NSS(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 3, _val)
-+#define SET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val)
-+#define GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(_pEleStart)			LE_BITS_TO_1BYTE(_pEleStart, 0, 2)
-+#define GET_VHT_OPERATING_MODE_FIELD_RX_NSS(_pEleStart)				LE_BITS_TO_1BYTE(_pEleStart, 4, 3)
-+#define GET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(_pEleStart)		LE_BITS_TO_1BYTE(_pEleStart, 7, 1)
-+
-+#define SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE((_pEleStart)+7, 6, 1, _val)
-+#define GET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart)				LE_BITS_TO_1BYTE((_pEleStart)+7, 6, 1)
-+
-+#define VHT_MAX_MPDU_LEN_MAX 3
-+extern const u16 _vht_max_mpdu_len[];
-+#define vht_max_mpdu_len(val) (((val) >= VHT_MAX_MPDU_LEN_MAX) ? _vht_max_mpdu_len[VHT_MAX_MPDU_LEN_MAX] : _vht_max_mpdu_len[(val)])
-+
-+#define VHT_SUP_CH_WIDTH_SET_MAX 3
-+extern const u8 _vht_sup_ch_width_set_to_bw_cap[];
-+#define vht_sup_ch_width_set_to_bw_cap(set) (((set) >= VHT_SUP_CH_WIDTH_SET_MAX) ? _vht_sup_ch_width_set_to_bw_cap[VHT_SUP_CH_WIDTH_SET_MAX] : _vht_sup_ch_width_set_to_bw_cap[(set)])
-+#define VHT_MAX_AMPDU_LEN(f) ((1 << (13 + f)) - 1)
-+
-+#ifdef CONFIG_RTW_DEBUG
-+extern const char *const _vht_sup_ch_width_set_str[];
-+#define vht_sup_ch_width_set_str(set) (((set) >= VHT_SUP_CH_WIDTH_SET_MAX) ? _vht_sup_ch_width_set_str[VHT_SUP_CH_WIDTH_SET_MAX] : _vht_sup_ch_width_set_str[(set)])
-+
-+void dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len);
-+
-+#define VHT_OP_CH_WIDTH_MAX 4
-+extern const char *const _vht_op_ch_width_str[];
-+#define vht_op_ch_width_str(ch_width) (((ch_width) >= VHT_OP_CH_WIDTH_MAX) ? _vht_op_ch_width_str[VHT_OP_CH_WIDTH_MAX] : _vht_op_ch_width_str[(ch_width)])
-+
-+void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len);
-+#endif
-+
-+struct vht_bf_cap {
-+	u8 is_mu_bfer;
-+	u8 su_sound_dim;
-+};
-+
-+struct vht_priv {
-+	u8	vht_option;
-+
-+	u8	ldpc_cap;
-+	u8	stbc_cap;
-+	u16	beamform_cap;
-+	struct	vht_bf_cap ap_bf_cap;
-+
-+	u8	sgi_80m;/* short GI */
-+	u8	ampdu_len;
-+
-+	u8	vht_highest_rate;
-+	u8	vht_mcs_map[2];
-+
-+	u8 op_present:1; /* vht_op is present */
-+	u8 notify_present:1; /* vht_op_mode_notify is present */
-+
-+	u8 vht_cap[32];
-+	u8 vht_op[VHT_OP_IE_LEN];
-+	u8 vht_op_mode_notify;
-+};
-+
-+#ifdef ROKU_PRIVATE
-+struct vht_priv_infra_ap {
-+
-+	/* Infra mode, only store for AP's info, not intersection of STA and AP*/
-+	u8	ldpc_cap_infra_ap;
-+	u8	stbc_cap_infra_ap;
-+	u16	beamform_cap_infra_ap;
-+	u8	vht_mcs_map_infra_ap[2];
-+	u8	vht_mcs_map_tx_infra_ap[2];
-+	u8	channel_width_infra_ap;
-+	u8	number_of_streams_infra_ap;
-+};
-+#endif /* ROKU_PRIVATE */
-+
-+u8	rtw_get_vht_highest_rate(u8 *pvht_mcs_map);
-+u16	rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate);
-+u64	rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss);
-+void	rtw_vht_use_default_setting(_adapter *padapter);
-+u32	rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel);
-+u32	rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw);
-+u32	rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf);
-+void	update_sta_vht_info_apmode(_adapter *padapter, void *psta);
-+void	update_hw_vht_param(_adapter *padapter);
-+void	VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
-+#ifdef ROKU_PRIVATE
-+void	VHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
-+#endif /* ROKU_PRIVATE */
-+void	VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
-+void	rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, void *sta);
-+u32	rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len);
-+void	VHTOnAssocRsp(_adapter *padapter);
-+u8	rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map);
-+void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map);
-+void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pcur_network);
-+void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pcur_network);
-+void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len);
-+#endif /* _RTW_VHT_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/rtw_wapi.h b/drivers/staging/rtl8723cs/include/rtw_wapi.h
-new file mode 100644
-index 000000000000..512bb7f300a2
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_wapi.h
-@@ -0,0 +1,230 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __INC_WAPI_H
-+#define __INC_WAPI_H
-+
-+
-+#define CONFIG_WAPI_SW_SMS4
-+#define WAPI_DEBUG
-+
-+#define SMS4_MIC_LEN                16
-+#define WAPI_EXT_LEN                18
-+#define MAX_WAPI_IE_LEN		    256
-+#define sMacHdrLng				24		/* octets in data header, no WEP */
-+
-+#ifdef WAPI_DEBUG
-+
-+/* WAPI trace debug */
-+extern u32 wapi_debug_component;
-+
-+static inline void dump_buf(u8 *buf, u32 len)
-+{
-+	u32 i;
-+	printk("-----------------Len %d----------------\n", len);
-+	for (i = 0; i < len; i++)
-+		printk("%2.2x-", *(buf + i));
-+	printk("\n");
-+}
-+
-+#define WAPI_TRACE(component, x, args...) \
-+	do { if (wapi_debug_component & (component)) \
-+			printk(KERN_DEBUG "WAPI" ":" x "" , \
-+			       ##args);\
-+	} while (0);
-+
-+#define WAPI_DATA(component, x, buf, len) \
-+	do { if (wapi_debug_component & (component)) { \
-+			printk("%s:\n", x);\
-+			dump_buf((buf), (len)); } \
-+	} while (0);
-+
-+#define RT_ASSERT_RET(_Exp)								\
-+	if (!(_Exp)) {									\
-+		printk("RTWLAN: ");					\
-+		printk("Assertion failed! %s,%s, line=%d\n", \
-+		       #_Exp, __FUNCTION__, __LINE__);          \
-+		return;						\
-+	}
-+#define RT_ASSERT_RET_VALUE(_Exp, Ret)								\
-+	if (!(_Exp)) {									\
-+		printk("RTWLAN: ");					\
-+		printk("Assertion failed! %s,%s, line=%d\n", \
-+		       #_Exp, __FUNCTION__, __LINE__);          \
-+		return Ret;						\
-+	}
-+
-+#else
-+#define RT_ASSERT_RET(_Exp) do {} while (0)
-+#define RT_ASSERT_RET_VALUE(_Exp, Ret) do {} while (0)
-+#define WAPI_TRACE(component, x, args...) do {} while (0)
-+#define WAPI_DATA(component, x, buf, len) do {} while (0)
-+#endif
-+
-+
-+enum WAPI_DEBUG {
-+	WAPI_INIT				= 1,
-+	WAPI_API				= 1 << 1,
-+	WAPI_TX				= 1 << 2,
-+	WAPI_RX				= 1 << 3,
-+	WAPI_MLME				= 1 << 4,
-+	WAPI_IOCTL				= 1 << 5,
-+	WAPI_ERR			= 1 << 31
-+};
-+
-+#define			WAPI_MAX_BKID_NUM				4
-+#define			WAPI_MAX_STAINFO_NUM			4
-+#define			WAPI_CAM_ENTRY_NUM			14	/* 28/2 = 14 */
-+
-+typedef struct  _RT_WAPI_BKID {
-+	struct list_head	list;
-+	u8				bkid[16];
-+} RT_WAPI_BKID, *PRT_WAPI_BKID;
-+
-+typedef struct  _RT_WAPI_KEY {
-+	u8			dataKey[16];
-+	u8			micKey[16];
-+	u8			keyId;
-+	bool			bSet;
-+	bool             bTxEnable;
-+} RT_WAPI_KEY, *PRT_WAPI_KEY;
-+
-+typedef enum _RT_WAPI_PACKET_TYPE {
-+	WAPI_NONE = 0,
-+	WAPI_PREAUTHENTICATE = 1,
-+	WAPI_STAKEY_REQUEST = 2,
-+	WAPI_AUTHENTICATE_ACTIVE = 3,
-+	WAPI_ACCESS_AUTHENTICATE_REQUEST = 4,
-+	WAPI_ACCESS_AUTHENTICATE_RESPONSE = 5,
-+	WAPI_CERTIFICATE_AUTHENTICATE_REQUEST = 6,
-+	WAPI_CERTIFICATE_AUTHENTICATE_RESPONSE = 7,
-+	WAPI_USK_REQUEST = 8,
-+	WAPI_USK_RESPONSE = 9,
-+	WAPI_USK_CONFIRM = 10,
-+	WAPI_MSK_NOTIFICATION = 11,
-+	WAPI_MSK_RESPONSE = 12
-+} RT_WAPI_PACKET_TYPE;
-+
-+typedef struct	_RT_WAPI_STA_INFO {
-+	struct list_head		list;
-+	u8					PeerMacAddr[6];
-+	RT_WAPI_KEY		      wapiUsk;
-+	RT_WAPI_KEY		      wapiUskUpdate;
-+	RT_WAPI_KEY		      wapiMsk;
-+	RT_WAPI_KEY		      wapiMskUpdate;
-+	u8					lastRxUnicastPN[16];
-+	u8					lastTxUnicastPN[16];
-+	u8					lastRxMulticastPN[16];
-+	u8					lastRxUnicastPNBEQueue[16];
-+	u8					lastRxUnicastPNBKQueue[16];
-+	u8					lastRxUnicastPNVIQueue[16];
-+	u8					lastRxUnicastPNVOQueue[16];
-+	bool					bSetkeyOk;
-+	bool					bAuthenticateInProgress;
-+	bool					bAuthenticatorInUpdata;
-+} RT_WAPI_STA_INFO, *PRT_WAPI_STA_INFO;
-+
-+/* Added for HW wapi en/decryption */
-+typedef struct _RT_WAPI_CAM_ENTRY {
-+	/* RT_LIST_ENTRY		list; */
-+	u8			IsUsed;
-+	u8			entry_idx;/* for cam entry */
-+	u8			keyidx;	/* 0 or 1,new or old key */
-+	u8			PeerMacAddr[6];
-+	u8			type;	/* should be 110,wapi */
-+} RT_WAPI_CAM_ENTRY, *PRT_WAPI_CAM_ENTRY;
-+
-+typedef struct _RT_WAPI_T {
-+	/* BKID */
-+	RT_WAPI_BKID		wapiBKID[WAPI_MAX_BKID_NUM];
-+	struct list_head		wapiBKIDIdleList;
-+	struct list_head		wapiBKIDStoreList;
-+	/* Key for Tx Multicast/Broadcast */
-+	RT_WAPI_KEY		      wapiTxMsk;
-+
-+	/* sec related */
-+	u8				lastTxMulticastPN[16];
-+	/* STA list */
-+	RT_WAPI_STA_INFO	wapiSta[WAPI_MAX_STAINFO_NUM];
-+	struct list_head		wapiSTAIdleList;
-+	struct list_head		wapiSTAUsedList;
-+	/*  */
-+	bool				bWapiEnable;
-+
-+	/* store WAPI IE */
-+	u8				wapiIE[256];
-+	u8				wapiIELength;
-+	bool				bWapiPSK;
-+	/* last sequece number for wai packet */
-+	u16				wapiSeqnumAndFragNum;
-+	int extra_prefix_len;
-+	int extra_postfix_len;
-+
-+	RT_WAPI_CAM_ENTRY	wapiCamEntry[WAPI_CAM_ENTRY_NUM];
-+} RT_WAPI_T, *PRT_WAPI_T;
-+
-+typedef struct _WLAN_HEADER_WAPI_EXTENSION {
-+	u8      KeyIdx;
-+	u8      Reserved;
-+	u8      PN[16];
-+} WLAN_HEADER_WAPI_EXTENSION, *PWLAN_HEADER_WAPI_EXTENSION;
-+
-+u32 WapiComparePN(u8 *PN1, u8 *PN2);
-+
-+
-+void rtw_wapi_init(_adapter *padapter);
-+
-+void rtw_wapi_free(_adapter *padapter);
-+
-+void rtw_wapi_disable_tx(_adapter *padapter);
-+
-+u8 rtw_wapi_is_wai_packet(_adapter *padapter, u8 *pkt_data);
-+
-+void rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame);
-+
-+u8 rtw_wapi_check_for_drop(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_ops);
-+
-+void rtw_build_probe_resp_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib);
-+
-+void rtw_build_beacon_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib);
-+
-+void rtw_build_assoc_req_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib);
-+
-+void rtw_wapi_on_assoc_ok(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE);
-+
-+void rtw_wapi_return_one_sta_info(_adapter *padapter, u8 *MacAddr);
-+
-+void rtw_wapi_return_all_sta_info(_adapter *padapter);
-+
-+void rtw_wapi_clear_cam_entry(_adapter *padapter, u8 *pMacAddr);
-+
-+void rtw_wapi_clear_all_cam_entry(_adapter *padapter);
-+
-+void rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey, u8 bUseDefaultKey);
-+
-+int rtw_wapi_create_event_send(_adapter *padapter, u8 EventId, u8 *MacAddr, u8 *Buff, u16 BufLen);
-+
-+u32	rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe);
-+
-+u32	rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe);
-+
-+void rtw_wapi_get_iv(_adapter *padapter, u8 *pRA, u8 *IV);
-+
-+u8 WapiIncreasePN(u8 *PN, u8 AddCount);
-+
-+bool rtw_wapi_drop_for_key_absent(_adapter *padapter, u8 *pRA);
-+
-+void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/rtw_wnm.h b/drivers/staging/rtl8723cs/include/rtw_wnm.h
-new file mode 100644
-index 000000000000..8d6bcb56a0c6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_wnm.h
-@@ -0,0 +1,209 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __RTW_WNM_H_
-+#define __RTW_WNM_H_
-+
-+#define RTW_RRM_NB_RPT_EN		BIT(1)
-+#define RTW_MAX_NB_RPT_NUM	8
-+
-+#define RTW_WNM_FEATURE_BTM_REQ_EN		BIT(0)
-+
-+#define rtw_roam_busy_scan(a, nb)	\
-+	(((a)->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE) && \
-+	(((a)->mlmepriv.ch_cnt) < ((nb)->nb_rpt_ch_list_num)))
-+
-+#define rtw_wnm_btm_preference_cap(a) \
-+	((a)->mlmepriv.nb_info.preference_en == _TRUE)
-+
-+#define rtw_wnm_btm_roam_triggered(a) \
-+	(((a)->mlmepriv.nb_info.preference_en == _TRUE) \
-+	&& (rtw_ft_chk_flags((a), RTW_FT_BTM_ROAM))	\
-+	)
-+
-+#define rtw_wnm_btm_diff_bss(a) \
-+	((rtw_wnm_btm_preference_cap(a)) && \
-+	(is_zero_mac_addr((a)->mlmepriv.nb_info.roam_target_addr) == _FALSE) && \
-+	(_rtw_memcmp((a)->mlmepriv.nb_info.roam_target_addr,\
-+		(a)->mlmepriv.cur_network.network.MacAddress, ETH_ALEN) == _FALSE))
-+
-+#define rtw_wnm_btm_roam_candidate(a, c) \
-+	((rtw_wnm_btm_preference_cap(a)) && \
-+	(is_zero_mac_addr((a)->mlmepriv.nb_info.roam_target_addr) == _FALSE) && \
-+	(_rtw_memcmp((a)->mlmepriv.nb_info.roam_target_addr,\
-+		(c)->network.MacAddress, ETH_ALEN)))
-+
-+#define rtw_wnm_set_ext_cap_btm(_pEleStart, _val) \
-+	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+2, 3, 1, _val)
-+
-+#define wnm_btm_bss_term_inc(p) (*((u8 *)((p)+3)) & BSS_TERMINATION_INCLUDED)
-+
-+#define wnm_btm_ess_disassoc_im(p) (*((u8 *)((p)+3)) & ESS_DISASSOC_IMMINENT)
-+
-+#define wnm_btm_dialog_token(p) (*((u8 *)((p)+2)))
-+
-+#define wnm_btm_req_mode(p) (*((u8 *)((p)+3)))
-+
-+#define wnm_btm_disassoc_timer(p) (*((u16 *)((p)+4)))
-+
-+#define wnm_btm_valid_interval(p) (*((u8 *)((p)+6)))
-+
-+#define wnm_btm_term_duration_offset(p) ((p)+7)
-+
-+#define wnm_btm_rsp_status(p) (*((u8 *)((p)+3)))
-+
-+#define wnm_btm_rsp_term_delay(p) (*((u8 *)((p)+4)))
-+
-+#define RTW_WLAN_ACTION_WNM_NB_RPT_ELEM	0x34
-+
-+enum rtw_ieee80211_wnm_actioncode {
-+	RTW_WLAN_ACTION_WNM_BTM_QUERY = 6,
-+	RTW_WLAN_ACTION_WNM_BTM_REQ = 7,
-+	RTW_WLAN_ACTION_WNM_BTM_RSP = 8,
-+	RTW_WLAN_ACTION_WNM_NOTIF_REQ = 26,
-+	RTW_WLAN_ACTION_WNM_NOTIF_RSP = 27,	
-+};
-+
-+/*IEEE Std 80211k Figure 7-95b Neighbor Report element format*/
-+struct nb_rpt_hdr {
-+	u8 id; /*0x34: Neighbor Report Element ID*/
-+	u8 len;
-+	u8 bssid[ETH_ALEN];
-+	u32 bss_info;
-+	u8 reg_class;
-+	u8 ch_num;
-+	u8 phy_type;	
-+};
-+
-+/*IEEE Std 80211v, Figure 7-9 BSS Termination Duration subelement field format */
-+struct btm_term_duration {
-+	u8 id;
-+	u8 len;
-+	u64 tsf;		/* value of the TSF counter when BSS termination will occur in the future */
-+	u16 duration;		/* number of minutes for which the BSS is not present*/
-+};
-+
-+/*IEEE Std 80211v, Figure 7-10 BSS Transition Management Request frame body format */
-+struct btm_req_hdr {
-+	u8 dialog_token;
-+	u8 req_mode;
-+	/* number of TBTTs until the AP sends a Disassociation frame to this STA */
-+	u16 disassoc_timer;
-+	/* number of TBTTs until the BSS transition candidate list is no longer valid */
-+	u8 validity_interval;
-+	struct btm_term_duration term_duration;
-+};
-+
-+struct btm_rsp_hdr {
-+	u8 dialog_token;
-+	u8 status;
-+	/* the number of minutes that
-+		the responding STA requests the BSS to delay termination */
-+	u8 termination_delay;
-+	u8 bssid[ETH_ALEN];
-+	u8 *pcandidates;
-+	u32 candidates_num;
-+};
-+
-+struct btm_rpt_cache {
-+	u8 dialog_token;
-+	u8 req_mode;
-+	u16 disassoc_timer;
-+	u8 validity_interval;
-+	struct btm_term_duration term_duration;
-+
-+	/* from BTM req */
-+	u32 validity_time;
-+	u32 disassoc_time;
-+
-+	systime req_stime;
-+};
-+
-+/*IEEE Std 80211v,  Table 7-43b Optional Subelement IDs for Neighbor Report*/
-+/* BSS Transition Candidate Preference */
-+#define WNM_BTM_CAND_PREF_SUBEID 0x03
-+
-+/* BSS Termination Duration */
-+#define WNM_BTM_TERM_DUR_SUBEID		0x04
-+
-+struct wnm_btm_cant {
-+	struct nb_rpt_hdr nb_rpt;
-+	u8 preference;	/* BSS Transition Candidate Preference */
-+};
-+
-+enum rtw_btm_req_mod {
-+	PREFERRED_CANDIDATE_LIST_INCLUDED = BIT0,
-+	ABRIDGED = BIT1,
-+	DISASSOC_IMMINENT = BIT2,
-+	BSS_TERMINATION_INCLUDED = BIT3,
-+	ESS_DISASSOC_IMMINENT = BIT4,
-+};
-+
-+struct roam_nb_info {
-+	struct nb_rpt_hdr nb_rpt[RTW_MAX_NB_RPT_NUM];
-+	struct rtw_ieee80211_channel nb_rpt_ch_list[RTW_MAX_NB_RPT_NUM];
-+	struct btm_rpt_cache btm_cache;
-+	bool	nb_rpt_valid;
-+	u8	nb_rpt_ch_list_num;
-+	u8 preference_en;
-+	u8 roam_target_addr[ETH_ALEN];
-+	u32	last_nb_rpt_entries;
-+	u8 nb_rpt_is_same;
-+	s8 disassoc_waiting;
-+	_timer roam_scan_timer;
-+	_timer disassoc_chk_timer;	
-+
-+	u32 features;
-+};
-+
-+u8 rtw_wnm_btm_reassoc_req(_adapter *padapter);
-+
-+void rtw_wnm_roam_scan_hdl(void *ctx);
-+
-+void rtw_wnm_disassoc_chk_hdl(void *ctx);
-+
-+u8 rtw_wnm_try_btm_roam_imnt(_adapter *padapter);
-+
-+void rtw_wnm_process_btm_req(_adapter *padapter,  u8* pframe, u32 frame_len);
-+
-+void rtw_wnm_reset_btm_candidate(struct roam_nb_info *pnb);
-+
-+void rtw_wnm_reset_btm_state(_adapter *padapter);
-+
-+u32 rtw_wnm_btm_rsp_candidates_sz_get(
-+	_adapter *padapter, u8* pframe, u32 frame_len);
-+
-+void rtw_wnm_process_btm_rsp(_adapter *padapter,
-+	u8* pframe, u32 frame_len, struct btm_rsp_hdr *prsp);
-+
-+void rtw_wnm_issue_btm_req(_adapter *padapter,
-+	u8 *pmac, struct btm_req_hdr *phdr, u8 *purl, u32 url_len,
-+	u8 *pcandidates, u8 candidate_cnt);
-+
-+void rtw_wnm_reset_btm_cache(_adapter *padapter);
-+
-+void rtw_wnm_issue_action(_adapter *padapter, u8 action, u8 reason, u8 dialog);
-+
-+void rtw_wnm_update_reassoc_req_ie(_adapter *padapter);
-+
-+void rtw_roam_nb_info_init(_adapter *padapter);
-+
-+u8 rtw_roam_nb_scan_list_set(_adapter *padapter,
-+	struct sitesurvey_parm *pparm);
-+
-+u32 rtw_wnm_btm_candidates_survey(_adapter *padapter, 
-+	u8* pframe, u32 elem_len, u8 is_preference);
-+#endif /* __RTW_WNM_H_ */
-+
-diff --git a/drivers/staging/rtl8723cs/include/rtw_xmit.h b/drivers/staging/rtl8723cs/include/rtw_xmit.h
-new file mode 100644
-index 000000000000..b8b0243071fc
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/rtw_xmit.h
-@@ -0,0 +1,1071 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _RTW_XMIT_H_
-+#define _RTW_XMIT_H_
-+
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	#ifdef CONFIG_TX_AGGREGATION
-+		#ifdef CONFIG_RTL8822C
-+			#ifdef CONFIG_SDIO_TX_FORMAT_DUMMY_AUTO
-+				#define MAX_XMITBUF_SZ	(51200)
-+			#else
-+				#define MAX_XMITBUF_SZ	(32764)
-+			#endif
-+		#else
-+			#define MAX_XMITBUF_SZ	(20480)	/* 20k */
-+		#endif
-+		/* #define SDIO_TX_AGG_MAX	5 */
-+	#else
-+		#define MAX_XMITBUF_SZ (1664)
-+		#define SDIO_TX_AGG_MAX	1
-+	#endif
-+
-+	#if defined CONFIG_SDIO_HCI
-+		#define NR_XMITBUFF	(16)
-+		#define SDIO_TX_DIV_NUM (2)
-+	#endif
-+	#if defined(CONFIG_GSPI_HCI)
-+		#define NR_XMITBUFF	(128)
-+	#endif
-+
-+#elif defined (CONFIG_USB_HCI)
-+
-+	#ifdef CONFIG_USB_TX_AGGREGATION
-+		#if defined(CONFIG_PLATFORM_ARM_SUNxI) || defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) || defined(CONFIG_PLATFORM_ARM_SUN8I) || defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
-+			#define MAX_XMITBUF_SZ (12288)  /* 12k 1536*8 */
-+		#elif defined (CONFIG_PLATFORM_MSTAR)
-+			#define MAX_XMITBUF_SZ	7680	/* 7.5k */
-+		#else
-+			#define MAX_XMITBUF_SZ	(20480)	/* 20k */
-+		#endif
-+	#else
-+		#define MAX_XMITBUF_SZ	(2048)
-+	#endif
-+
-+	#ifdef CONFIG_SINGLE_XMIT_BUF
-+		#define NR_XMITBUFF	(1)
-+	#else
-+		#define NR_XMITBUFF	(4)
-+	#endif /* CONFIG_SINGLE_XMIT_BUF */
-+#elif defined (CONFIG_PCI_HCI)
-+#ifdef CONFIG_TX_AMSDU
-+	#define MAX_XMITBUF_SZ	(3500)
-+#else
-+	#define MAX_XMITBUF_SZ	(1664)
-+#endif
-+#ifdef CONFIG_PCI_TX_POLLING
-+	#define NR_XMITBUFF	(256)
-+#else
-+	#define NR_XMITBUFF	(128)
-+#endif
-+#endif
-+
-+
-+#ifdef CONFIG_PCI_HCI
-+	#define XMITBUF_ALIGN_SZ 4
-+#else
-+	#ifdef USB_XMITBUF_ALIGN_SZ
-+		#define XMITBUF_ALIGN_SZ (USB_XMITBUF_ALIGN_SZ)
-+	#else
-+		#define XMITBUF_ALIGN_SZ 512
-+	#endif
-+#endif
-+
-+
-+/* xmit extension buff defination */
-+#define MAX_XMIT_EXTBUF_SZ	(1536)
-+
-+#ifdef CONFIG_SINGLE_XMIT_BUF
-+	#define NR_XMIT_EXTBUFF	(1)
-+#else
-+	#define NR_XMIT_EXTBUFF	(32)
-+#endif
-+
-+#ifdef CONFIG_RTL8812A
-+	#define MAX_CMDBUF_SZ	(512 * 18)
-+#elif defined(CONFIG_RTL8723D) && defined(CONFIG_LPS_POFF)
-+	#define MAX_CMDBUF_SZ	(128*70) /*(8960)*/
-+#elif defined(CONFIG_RTL8822C) && defined(CONFIG_WAR_OFFLOAD)
-+	#define MAX_CMDBUF_SZ	(128*128) /*(16k) */
-+#else
-+	#define MAX_CMDBUF_SZ	(5120)	/* (4096) */
-+#endif
-+
-+#define MAX_BEACON_LEN	512
-+
-+#define MAX_NUMBLKS		(1)
-+
-+#define XMIT_VO_QUEUE (0)
-+#define XMIT_VI_QUEUE (1)
-+#define XMIT_BE_QUEUE (2)
-+#define XMIT_BK_QUEUE (3)
-+
-+#define VO_QUEUE_INX		0
-+#define VI_QUEUE_INX		1
-+#define BE_QUEUE_INX		2
-+#define BK_QUEUE_INX		3
-+#define BCN_QUEUE_INX		4
-+#define MGT_QUEUE_INX		5
-+#define TXCMD_QUEUE_INX		6
-+#define HIGH_QUEUE_INX		7
-+/* keep high queue to be the last one, so we can extend HIQ to port 1, 2, ... */
-+
-+#ifndef CONFIG_PORT_BASED_HIQ
-+#define HW_QUEUE_ENTRY	8
-+#else
-+#define HI_QUEUE_INX(n)	(HIGH_QUEUE_INX + (n))
-+#define HW_QUEUE_ENTRY	(8 + CONFIG_IFACE_NUMBER - 1)
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	#ifdef CONFIG_TRX_BD_ARCH
-+		#define TX_BD_NUM			(128+1)	/* +1 result from ring buffer */
-+	#else
-+		#define TXDESC_NUM			128
-+	#endif
-+#endif
-+
-+#define WEP_IV(pattrib_iv, dot11txpn, keyidx)\
-+	do {\
-+		dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val + 1);\
-+		pattrib_iv[0] = dot11txpn._byte_.TSC0;\
-+		pattrib_iv[1] = dot11txpn._byte_.TSC1;\
-+		pattrib_iv[2] = dot11txpn._byte_.TSC2;\
-+		pattrib_iv[3] = ((keyidx & 0x3)<<6);\
-+	} while (0)
-+
-+
-+#define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\
-+	do {\
-+		dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\
-+		pattrib_iv[0] = dot11txpn._byte_.TSC1;\
-+		pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\
-+		pattrib_iv[2] = dot11txpn._byte_.TSC0;\
-+		pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\
-+		pattrib_iv[4] = dot11txpn._byte_.TSC2;\
-+		pattrib_iv[5] = dot11txpn._byte_.TSC3;\
-+		pattrib_iv[6] = dot11txpn._byte_.TSC4;\
-+		pattrib_iv[7] = dot11txpn._byte_.TSC5;\
-+	} while (0)
-+
-+#define AES_IV(pattrib_iv, dot11txpn, keyidx)\
-+	do {\
-+		dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\
-+		pattrib_iv[0] = dot11txpn._byte_.TSC0;\
-+		pattrib_iv[1] = dot11txpn._byte_.TSC1;\
-+		pattrib_iv[2] = 0;\
-+		pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\
-+		pattrib_iv[4] = dot11txpn._byte_.TSC2;\
-+		pattrib_iv[5] = dot11txpn._byte_.TSC3;\
-+		pattrib_iv[6] = dot11txpn._byte_.TSC4;\
-+		pattrib_iv[7] = dot11txpn._byte_.TSC5;\
-+	} while (0)
-+
-+#define GCMP_IV(a, b, c) AES_IV(a, b, c)
-+
-+/* Check if AMPDU Tx is supported or not. If it is supported,
-+* it need to check "amsdu in ampdu" is supported or not.
-+* (ampdu_en, amsdu_ampdu_en) =
-+* (0, x) : AMPDU is not enable, but AMSDU is valid to send.
-+* (1, 0) : AMPDU is enable, AMSDU in AMPDU is not enable. So, AMSDU is not valid to send.
-+* (1, 1) : AMPDU and AMSDU in AMPDU are enable. So, AMSDU is valid to send.
-+*/
-+#define IS_AMSDU_AMPDU_NOT_VALID(pattrib)\
-+	 ((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE))
-+
-+#define IS_AMSDU_AMPDU_VALID(pattrib)\
-+	 !((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE))
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+#define HWXMIT_ENTRY 5
-+#else
-+#define HWXMIT_ENTRY 4
-+#endif
-+
-+/* For Buffer Descriptor ring architecture */
-+#if defined(BUF_DESC_ARCH) || defined(CONFIG_TRX_BD_ARCH)
-+	#if defined(CONFIG_RTL8192E)
-+		#define TX_BUFFER_SEG_NUM	1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */
-+	#elif defined(CONFIG_RTL8814A)
-+		#define TX_BUFFER_SEG_NUM	1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */
-+	#else
-+		#define TX_BUFFER_SEG_NUM	1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */
-+	#endif
-+#endif
-+
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) ||\
-+	defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8192E) ||\
-+	defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8703B) ||\
-+	defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) ||\
-+	defined(CONFIG_RTL8710B) || defined(CONFIG_RTL8192F) ||\
-+	defined(CONFIG_RTL8723F)
-+	#define TXDESC_SIZE 40
-+#elif defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)
-+	#define TXDESC_SIZE 48		/* HALMAC_TX_DESC_SIZE_8822B */
-+#elif defined(CONFIG_RTL8821C)
-+	#define TXDESC_SIZE 48		/* HALMAC_TX_DESC_SIZE_8821C */
-+#elif defined(CONFIG_RTL8814B)
-+	#define TXDESC_SIZE (16 + 32)
-+#else
-+	#define TXDESC_SIZE 32 /* old IC (ex: 8188E) */
-+#endif
-+
-+#ifdef CONFIG_TX_EARLY_MODE
-+	#define EARLY_MODE_INFO_SIZE	8
-+#endif
-+
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	#define TXDESC_OFFSET TXDESC_SIZE
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+	#ifdef USB_PACKET_OFFSET_SZ
-+		#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)
-+	#else
-+		#define PACKET_OFFSET_SZ (8)
-+	#endif
-+	#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	#if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_TRX_BD_ARCH)
-+		/* this section is defined for buffer descriptor ring architecture */
-+		#define TX_WIFI_INFO_SIZE (TXDESC_SIZE) /* it may add 802.11 hdr or others... */
-+		/* tx desc and payload are in the same buf */
-+		#define TXDESC_OFFSET (TX_WIFI_INFO_SIZE)
-+	#else
-+		/* tx desc and payload are NOT in the same buf */
-+		#define TXDESC_OFFSET (0)
-+		/* 8188ee/8723be/8812ae/8821ae has extra PCI DMA info in tx desc */
-+		#define TX_DESC_NEXT_DESC_OFFSET	(TXDESC_SIZE + 8)
-+	#endif
-+#endif /* CONFIG_PCI_HCI */
-+
-+enum TXDESC_SC {
-+	SC_DONT_CARE = 0x00,
-+	SC_UPPER = 0x01,
-+	SC_LOWER = 0x02,
-+	SC_DUPLICATE = 0x03
-+};
-+
-+#ifdef CONFIG_PCI_HCI
-+	#ifndef CONFIG_TRX_BD_ARCH	/* CONFIG_TRX_BD_ARCH doesn't need this */
-+		#define TXDESC_64_BYTES
-+	#endif
-+#elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8723B) \
-+	|| defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) \
-+	|| defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8723F)
-+	#define TXDESC_40_BYTES
-+#endif
-+
-+#ifdef CONFIG_TRX_BD_ARCH
-+struct tx_buf_desc {
-+#ifdef CONFIG_64BIT_DMA
-+#define TX_BUFFER_SEG_SIZE	4	/* in unit of DWORD */
-+#else
-+#define TX_BUFFER_SEG_SIZE	2	/* in unit of DWORD */
-+#endif
-+	unsigned int dword[TX_BUFFER_SEG_SIZE * (2 << TX_BUFFER_SEG_NUM)];
-+} __packed;
-+#elif (defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI) /* 8192ee or 8814ae */
-+/* 8192EE_TODO */
-+struct tx_desc {
-+	unsigned int txdw0;
-+	unsigned int txdw1;
-+	unsigned int txdw2;
-+	unsigned int txdw3;
-+	unsigned int txdw4;
-+	unsigned int txdw5;
-+	unsigned int txdw6;
-+	unsigned int txdw7;
-+};
-+#else
-+struct tx_desc {
-+	unsigned int txdw0;
-+	unsigned int txdw1;
-+	unsigned int txdw2;
-+	unsigned int txdw3;
-+	unsigned int txdw4;
-+	unsigned int txdw5;
-+	unsigned int txdw6;
-+	unsigned int txdw7;
-+
-+#if defined(TXDESC_40_BYTES) || defined(TXDESC_64_BYTES)
-+	unsigned int txdw8;
-+	unsigned int txdw9;
-+#endif /* TXDESC_40_BYTES */
-+
-+#ifdef TXDESC_64_BYTES
-+	unsigned int txdw10;
-+	unsigned int txdw11;
-+
-+	/* 2008/05/15 MH Because PCIE HW memory R/W 4K limit. And now,  our descriptor */
-+	/* size is 40 bytes. If you use more than 102 descriptor( 103*40>4096), HW will execute */
-+	/* memoryR/W CRC error. And then all DMA fetch will fail. We must decrease descriptor */
-+	/* number or enlarge descriptor size as 64 bytes. */
-+	unsigned int txdw12;
-+	unsigned int txdw13;
-+	unsigned int txdw14;
-+	unsigned int txdw15;
-+#endif
-+};
-+#endif
-+
-+#ifndef CONFIG_TRX_BD_ARCH
-+union txdesc {
-+	struct tx_desc txdesc;
-+	unsigned int value[TXDESC_SIZE >> 2];
-+};
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+#define PCI_MAX_TX_QUEUE_COUNT	HW_QUEUE_ENTRY
-+
-+struct rtw_tx_ring {
-+	unsigned char	qid;
-+#ifdef CONFIG_TRX_BD_ARCH
-+	struct tx_buf_desc	*buf_desc;
-+#else
-+	struct tx_desc	*desc;
-+#endif
-+	dma_addr_t	dma;
-+	unsigned int	idx;
-+	unsigned int	entries;
-+	_queue		queue;
-+	u32		qlen;
-+#ifdef CONFIG_TRX_BD_ARCH
-+	u16		hw_rp_cache;
-+#endif
-+};
-+
-+#ifdef DBG_TXBD_DESC_DUMP
-+
-+#define TX_BAK_FRMAE_CNT	10
-+#define TX_BAK_DESC_LEN	48	/* byte */
-+#define TX_BAK_DATA_LEN		30	/* byte */
-+
-+struct rtw_tx_desc_backup {
-+	int tx_bak_rp;
-+	int tx_bak_wp;
-+	u8 tx_bak_desc[TX_BAK_DESC_LEN];
-+	u8 tx_bak_data_hdr[TX_BAK_DATA_LEN];
-+	u8 tx_desc_size;
-+};
-+#endif
-+#endif
-+
-+struct	hw_xmit	{
-+	/* _lock xmit_lock; */
-+	/* _list	pending; */
-+	_queue *sta_queue;
-+	/* struct hw_txqueue *phwtxqueue; */
-+	/* sint	txcmdcnt; */
-+	int	accnt;
-+};
-+
-+struct pkt_attrib {
-+	u8	type;
-+	u8	subtype;
-+	u8	bswenc;
-+	u8	dhcp_pkt;
-+	u16	ether_type;
-+	u16	seqnum;
-+	u8	hw_ssn_sel;	/* for HW_SEQ0,1,2,3 */
-+	u16	pkt_hdrlen;	/* the original 802.3 pkt header len */
-+	u16	hdrlen;		/* the WLAN Header Len */
-+	u32	pktlen;		/* the original 802.3 pkt raw_data len (not include ether_hdr data) */
-+	u32	last_txcmdsz;
-+	u8	nr_frags;
-+	u8	encrypt;	/* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */
-+	u8	bmc_camid;
-+	u8	iv_len;
-+	u8	icv_len;
-+	u8	iv[18];
-+	u8	icv[16];
-+	u8	priority;
-+	u8	ack_policy;
-+	u8	mac_id;
-+	u8	vcs_mode;	/* virtual carrier sense method */
-+	u8	dst[ETH_ALEN];
-+	u8	src[ETH_ALEN];
-+	u8	ta[ETH_ALEN];
-+	u8	ra[ETH_ALEN];
-+#ifdef CONFIG_RTW_WDS
-+	u8	wds;
-+#endif
-+#ifdef CONFIG_RTW_MESH
-+	u8	mda[ETH_ALEN];	/* mesh da */
-+	u8	msa[ETH_ALEN];	/* mesh sa */
-+	u8	meshctrl_len;	/* Length of Mesh Control field */
-+	u8	mesh_frame_mode;
-+	#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+	u8 mb2u;
-+	#endif
-+	u8 mfwd_ttl;
-+	u32 mseq;
-+#endif
-+#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
-+	u8	hw_csum;
-+#endif
-+	u8	key_idx;
-+	u8	qos_en;
-+	u8	ht_en;
-+	u8	raid;/* rate adpative id */
-+	u8	bwmode;
-+	u8	ch_offset;/* PRIME_CHNL_OFFSET */
-+	u8	sgi;/* short GI */
-+	u8	ampdu_en;/* tx ampdu enable */
-+	u8	ampdu_spacing; /* ampdu_min_spacing for peer sta's rx */
-+	u8	amsdu;
-+	u8	amsdu_ampdu_en;/* tx amsdu in ampdu enable */
-+	u8	mdata;/* more data bit */
-+	u8	pctrl;/* per packet txdesc control enable */
-+	u8	triggered;/* for ap mode handling Power Saving sta */
-+	u8	qsel;
-+	u8	order;/* order bit */
-+	u8	eosp;
-+	u8	rate;
-+	u8	intel_proxim;
-+	u8	retry_ctrl;
-+	u8   mbssid;
-+	u8	ldpc;
-+	u8	stbc;
-+#ifdef CONFIG_WMMPS_STA
-+	u8	trigger_frame;
-+#endif /* CONFIG_WMMPS_STA */
-+	
-+	struct sta_info *psta;
-+
-+	u8 rtsen;
-+	u8 cts2self;
-+	union Keytype	dot11tkiptxmickey;
-+	/* union Keytype	dot11tkiprxmickey; */
-+	union Keytype	dot118021x_UncstKey;
-+
-+#ifdef CONFIG_TDLS
-+	u8 direct_link;
-+	struct sta_info *ptdls_sta;
-+#endif /* CONFIG_TDLS */
-+	u8 key_type;
-+
-+	u8 icmp_pkt;
-+	u8 hipriority_pkt; /* high priority packet */
-+
-+#ifdef CONFIG_BEAMFORMING
-+	u16 txbf_p_aid;/*beamforming Partial_AID*/
-+	u16 txbf_g_id;/*beamforming Group ID*/
-+
-+	/*
-+	 * 2'b00: Unicast NDPA
-+	 * 2'b01: Broadcast NDPA
-+	 * 2'b10: Beamforming Report Poll
-+	 * 2'b11: Final Beamforming Report Poll
-+	 */
-+	u8 bf_pkt_type;
-+#endif
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	u8 ps_dontq; /* 1: this frame can't be queued at PS state */
-+#endif
-+};
-+
-+#ifdef CONFIG_RTW_WDS
-+#define XATTRIB_GET_WDS(xattrib) ((xattrib)->wds)
-+#else
-+#define XATTRIB_GET_WDS(xattrib) 0
-+#endif
-+
-+#ifdef CONFIG_RTW_MESH
-+#define XATTRIB_GET_MCTRL_LEN(xattrib) ((xattrib)->meshctrl_len)
-+#else
-+#define XATTRIB_GET_MCTRL_LEN(xattrib) 0
-+#endif
-+
-+#ifdef CONFIG_TX_AMSDU
-+enum {
-+	RTW_AMSDU_TIMER_UNSET = 0,
-+	RTW_AMSDU_TIMER_SETTING,
-+	RTW_AMSDU_TIMER_TIMEOUT,
-+};
-+#endif
-+
-+#define WLANHDR_OFFSET	64
-+
-+#define NULL_FRAMETAG		(0x0)
-+#define DATA_FRAMETAG		0x01
-+#define L2_FRAMETAG		0x02
-+#define MGNT_FRAMETAG		0x03
-+#define AMSDU_FRAMETAG	0x04
-+
-+#define EII_FRAMETAG		0x05
-+#define IEEE8023_FRAMETAG  0x06
-+
-+#define MP_FRAMETAG		0x07
-+
-+#define TXAGG_FRAMETAG	0x08
-+
-+enum {
-+	XMITBUF_DATA = 0,
-+	XMITBUF_MGNT = 1,
-+	XMITBUF_CMD = 2,
-+};
-+
-+bool rtw_xmit_ac_blocked(_adapter *adapter);
-+
-+struct  submit_ctx {
-+	systime submit_time; /* */
-+	u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */
-+	int status; /* status for operation */
-+#ifdef PLATFORM_LINUX
-+	struct completion done;
-+#endif
-+};
-+
-+enum {
-+	RTW_SCTX_SUBMITTED = -1,
-+	RTW_SCTX_DONE_SUCCESS = 0,
-+	RTW_SCTX_DONE_UNKNOWN,
-+	RTW_SCTX_DONE_TIMEOUT,
-+	RTW_SCTX_DONE_BUF_ALLOC,
-+	RTW_SCTX_DONE_BUF_FREE,
-+	RTW_SCTX_DONE_WRITE_PORT_ERR,
-+	RTW_SCTX_DONE_TX_DESC_NA,
-+	RTW_SCTX_DONE_TX_DENY,
-+	RTW_SCTX_DONE_CCX_PKT_FAIL,
-+	RTW_SCTX_DONE_DRV_STOP,
-+	RTW_SCTX_DONE_DEV_REMOVE,
-+	RTW_SCTX_DONE_CMD_ERROR,
-+	RTW_SCTX_DONE_CMD_DROP,
-+	RTX_SCTX_CSTR_WAIT_RPT2,
-+};
-+
-+
-+void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms);
-+int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg);
-+void rtw_sctx_done_err(struct submit_ctx **sctx, int status);
-+void rtw_sctx_done(struct submit_ctx **sctx);
-+
-+struct xmit_buf {
-+	_list	list;
-+
-+	_adapter *padapter;
-+
-+	u8 *pallocated_buf;
-+
-+	u8 *pbuf;
-+
-+	void *priv_data;
-+
-+	u16 buf_tag; /* 0: Normal xmitbuf, 1: extension xmitbuf, 2:cmd xmitbuf */
-+	u16 flags;
-+	u32 alloc_sz;
-+
-+	u32  len;
-+
-+	struct submit_ctx *sctx;
-+
-+#ifdef CONFIG_USB_HCI
-+
-+	/* u32 sz[8]; */
-+	u32	ff_hwaddr;
-+#ifdef RTW_HALMAC
-+	u8 bulkout_id; /* for halmac */
-+#endif /* RTW_HALMAC */
-+
-+	PURB	pxmit_urb[8];
-+	dma_addr_t dma_transfer_addr;	/* (in) dma addr for transfer_buffer */
-+
-+	u8 bpending[8];
-+
-+	sint last[8];
-+
-+#endif
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	u8 *phead;
-+	u8 *pdata;
-+	u8 *ptail;
-+	u8 *pend;
-+	u32 ff_hwaddr;
-+	u8	pg_num;
-+	u8	agg_num;
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+#ifdef CONFIG_TRX_BD_ARCH
-+	/*struct tx_buf_desc *buf_desc;*/
-+#else
-+	struct tx_desc *desc;
-+#endif
-+#endif
-+
-+#if defined(DBG_XMIT_BUF) || defined(DBG_XMIT_BUF_EXT)
-+	u8 no;
-+#endif
-+
-+};
-+
-+
-+struct xmit_frame {
-+	_list	list;
-+
-+	struct pkt_attrib attrib;
-+
-+	u16 os_qid;
-+	_pkt *pkt;
-+
-+	int	frame_tag;
-+
-+	_adapter *padapter;
-+
-+	u8	*buf_addr;
-+
-+	struct xmit_buf *pxmitbuf;
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	u8	pg_num;
-+	u8	agg_num;
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+#ifdef CONFIG_USB_TX_AGGREGATION
-+	u8	agg_num;
-+#endif
-+	s8	pkt_offset;
-+#endif
-+
-+#ifdef CONFIG_XMIT_ACK
-+	u8 ack_report;
-+#endif
-+
-+	u8 *alloc_addr; /* the actual address this xmitframe allocated */
-+	u8 ext_tag; /* 0:data, 1:mgmt */
-+
-+};
-+
-+struct tx_servq {
-+	_list	tx_pending;
-+	_queue	sta_pending;
-+	int qcnt;
-+};
-+
-+
-+struct sta_xmit_priv {
-+	_lock	lock;
-+	sint	option;
-+	sint	apsd_setting;	/* When bit mask is on, the associated edca queue supports APSD. */
-+
-+
-+	/* struct tx_servq blk_q[MAX_NUMBLKS]; */
-+	struct tx_servq	be_q;			/* priority == 0,3 */
-+	struct tx_servq	bk_q;			/* priority == 1,2 */
-+	struct tx_servq	vi_q;			/* priority == 4,5 */
-+	struct tx_servq	vo_q;			/* priority == 6,7 */
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	struct tx_servq	mgmt_q;
-+#endif
-+
-+	_list	legacy_dz;
-+	_list  apsd;
-+
-+	u16 txseq_tid[16];
-+
-+	/* uint	sta_tx_bytes; */
-+	/* u64	sta_tx_pkts; */
-+	/* uint	sta_tx_fail; */
-+
-+
-+};
-+
-+
-+struct	hw_txqueue	{
-+	volatile sint	head;
-+	volatile sint	tail;
-+	volatile sint 	free_sz;	/* in units of 64 bytes */
-+	volatile sint      free_cmdsz;
-+	volatile sint	 txsz[8];
-+	uint	ff_hwaddr;
-+	uint	cmd_hwaddr;
-+	sint	ac_tag;
-+};
-+
-+struct agg_pkt_info {
-+	u16 offset;
-+	u16 pkt_len;
-+};
-+
-+enum cmdbuf_type {
-+	CMDBUF_BEACON = 0x00,
-+	CMDBUF_RSVD,
-+	CMDBUF_MAX
-+};
-+
-+u8 rtw_get_hwseq_no(_adapter *padapter);
-+
-+struct	xmit_priv	{
-+
-+	_lock	lock;
-+
-+	_sema	xmit_sema;
-+
-+	/* _queue	blk_strms[MAX_NUMBLKS]; */
-+	_queue	be_pending;
-+	_queue	bk_pending;
-+	_queue	vi_pending;
-+	_queue	vo_pending;
-+	_queue	mgmt_pending;
-+
-+	/* _queue	legacy_dz_queue; */
-+	/* _queue	apsd_queue; */
-+
-+	u8 *pallocated_frame_buf;
-+	u8 *pxmit_frame_buf;
-+	uint free_xmitframe_cnt;
-+	_queue	free_xmit_queue;
-+
-+	/* uint mapping_addr; */
-+	/* uint pkt_sz; */
-+
-+	u8 *xframe_ext_alloc_addr;
-+	u8 *xframe_ext;
-+	uint free_xframe_ext_cnt;
-+	_queue free_xframe_ext_queue;
-+
-+	/* struct	hw_txqueue	be_txqueue; */
-+	/* struct	hw_txqueue	bk_txqueue; */
-+	/* struct	hw_txqueue	vi_txqueue; */
-+	/* struct	hw_txqueue	vo_txqueue; */
-+	/* struct	hw_txqueue	bmc_txqueue; */
-+
-+	uint	frag_len;
-+
-+	_adapter	*adapter;
-+
-+	u8   vcs_setting;
-+	u8	vcs;
-+	u8	vcs_type;
-+	/* u16  rts_thresh; */
-+
-+	u64	tx_bytes;
-+	u64	tx_pkts;
-+	u64	tx_drop;
-+	u64	last_tx_pkts;
-+
-+	struct hw_xmit *hwxmits;
-+	u8	hwxmit_entry;
-+
-+	u8	wmm_para_seq[4];/* sequence for wmm ac parameter strength from large to small. it's value is 0->vo, 1->vi, 2->be, 3->bk. */
-+
-+#ifdef CONFIG_USB_HCI
-+	_sema	tx_retevt;/* all tx return event; */
-+	u8		txirp_cnt;
-+
-+	_tasklet xmit_tasklet;
-+
-+	/* per AC pending irp */
-+	int beq_cnt;
-+	int bkq_cnt;
-+	int viq_cnt;
-+	int voq_cnt;
-+
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	/* Tx */
-+	struct rtw_tx_ring	tx_ring[PCI_MAX_TX_QUEUE_COUNT];
-+	int	txringcount[PCI_MAX_TX_QUEUE_COUNT];
-+	u8 	beaconDMAing;		/* flag of indicating beacon is transmiting to HW by DMA */
-+	_tasklet xmit_tasklet;
-+#endif
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+#ifdef CONFIG_SDIO_TX_TASKLET
-+	_tasklet xmit_tasklet;
-+#else
-+	_thread_hdl_	SdioXmitThread;
-+	_sema		SdioXmitSema;
-+	#ifdef SDIO_FREE_XMIT_BUF_SEMA
-+	_sema		sdio_free_xmitbuf_sema;
-+	#endif
-+#endif /* CONFIG_SDIO_TX_TASKLET */
-+#endif /* CONFIG_SDIO_HCI */
-+
-+	_queue free_xmitbuf_queue;
-+	_queue pending_xmitbuf_queue;
-+	u8 *pallocated_xmitbuf;
-+	u8 *pxmitbuf;
-+	uint free_xmitbuf_cnt;
-+
-+	_queue free_xmit_extbuf_queue;
-+	u8 *pallocated_xmit_extbuf;
-+	u8 *pxmit_extbuf;
-+	uint free_xmit_extbuf_cnt;
-+
-+	struct xmit_buf	pcmd_xmitbuf[CMDBUF_MAX];
-+	u8   hw_ssn_seq_no;/* mapping to REG_HW_SEQ 0,1,2,3 */
-+	u16	nqos_ssn;
-+#ifdef CONFIG_TX_EARLY_MODE
-+
-+#ifdef CONFIG_SDIO_HCI
-+#define MAX_AGG_PKT_NUM 20
-+#else
-+#define MAX_AGG_PKT_NUM 256 /* Max tx ampdu coounts		 */
-+#endif
-+
-+	struct agg_pkt_info agg_pkt[MAX_AGG_PKT_NUM];
-+#endif
-+
-+#ifdef CONFIG_XMIT_ACK
-+	int	ack_tx;
-+	_mutex ack_tx_mutex;
-+	struct submit_ctx ack_tx_ops;
-+	u8 seq_no;
-+#ifdef CONFIG_REMOVE_DUP_TX_STATE
-+	u8 retry_count;
-+#endif
-+#endif
-+
-+#ifdef CONFIG_TX_AMSDU
-+	_timer amsdu_vo_timer;
-+	u8 amsdu_vo_timeout;
-+
-+	_timer amsdu_vi_timer;
-+	u8 amsdu_vi_timeout;
-+
-+	_timer amsdu_be_timer;
-+	u8 amsdu_be_timeout;
-+
-+	_timer amsdu_bk_timer;
-+	u8 amsdu_bk_timeout;
-+
-+	u32 amsdu_debug_set_timer;
-+	u32 amsdu_debug_timeout;
-+	u32 amsdu_debug_coalesce_one;
-+	u32 amsdu_debug_coalesce_two;
-+
-+#endif
-+#ifdef DBG_TXBD_DESC_DUMP
-+	BOOLEAN	 dump_txbd_desc;
-+#endif
-+#ifdef CONFIG_PCI_TX_POLLING
-+	_timer tx_poll_timer;
-+#endif
-+	_lock lock_sctx;
-+
-+};
-+
-+extern struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv,
-+		enum cmdbuf_type buf_type);
-+#define rtw_alloc_cmdxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_RSVD)
-+#if defined(CONFIG_RTL8192E) && defined(CONFIG_PCI_HCI)
-+extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192ee(struct xmit_priv *pxmitpriv,
-+		enum cmdbuf_type buf_type);
-+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192ee(p, CMDBUF_BEACON)
-+#elif defined(CONFIG_RTL8822B) && defined(CONFIG_PCI_HCI)
-+extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8822be(struct xmit_priv *pxmitpriv,
-+		enum cmdbuf_type buf_type);
-+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8822be(p, CMDBUF_BEACON)
-+#elif defined(CONFIG_RTL8822C) && defined(CONFIG_PCI_HCI)
-+extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8822ce(struct xmit_priv *pxmitpriv,
-+		enum cmdbuf_type buf_type);
-+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8822ce(p, CMDBUF_BEACON)
-+#elif defined(CONFIG_RTL8821C) && defined(CONFIG_PCI_HCI)
-+extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8821ce(struct xmit_priv *pxmitpriv,
-+		enum cmdbuf_type buf_type);
-+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8821ce(p, CMDBUF_BEACON)
-+#elif defined(CONFIG_RTL8192F) && defined(CONFIG_PCI_HCI)
-+extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192fe(struct xmit_priv *pxmitpriv,
-+		enum cmdbuf_type buf_type);
-+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192fe(p, CMDBUF_BEACON)
-+#elif defined(CONFIG_RTL8812A) && defined(CONFIG_PCI_HCI)
-+extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8812ae(struct xmit_priv *pxmitpriv,
-+		enum cmdbuf_type buf_type);
-+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8812ae(p, CMDBUF_BEACON)
-+#elif defined(CONFIG_RTL8723D) && defined(CONFIG_PCI_HCI)
-+extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8723de(struct xmit_priv *pxmitpriv,
-+		enum cmdbuf_type buf_type);
-+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8723de(p, CMDBUF_BEACON)
-+#elif defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI)
-+extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8723be(struct xmit_priv *pxmitpriv,
-+		enum cmdbuf_type buf_type);
-+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8723be(p, CMDBUF_BEACON)
-+#elif defined(CONFIG_RTL8814A) && defined(CONFIG_PCI_HCI)
-+extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8814ae(struct xmit_priv *pxmitpriv,
-+		enum cmdbuf_type buf_type);
-+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8814ae(p, CMDBUF_BEACON)
-+#elif defined(CONFIG_RTL8814B) && defined(CONFIG_PCI_HCI)
-+extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8814be(struct xmit_priv *pxmitpriv,
-+		enum cmdbuf_type buf_type);
-+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8814be(p, CMDBUF_BEACON)
-+#else
-+#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_BEACON)
-+#endif
-+
-+extern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv);
-+extern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+
-+extern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv);
-+extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+
-+void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz);
-+extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len);
-+
-+extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib);
-+extern s32 rtw_put_snap(u8 *data, u16 h_proto);
-+
-+extern struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv, u16 os_qid);
-+struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv);
-+struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv);
-+extern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe);
-+extern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue);
-+struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac);
-+extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+void rtw_free_mgmt_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *mgmt_queue);
-+u8 rtw_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
-+struct xmit_frame *rtw_dequeue_mgmt_xframe(struct xmit_priv *pxmitpriv);
-+#endif /* CONFIG_RTW_MGMT_QUEUE */
-+
-+extern struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry);
-+
-+extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe);
-+extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib);
-+#define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib)
-+extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe);
-+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
-+extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe);
-+#endif
-+#ifdef CONFIG_TDLS
-+extern struct tdls_txmgmt *ptxmgmt;
-+s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt);
-+s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
-+#endif
-+s32 _rtw_init_hw_txqueue(struct hw_txqueue *phw_txqueue, u8 ac_tag);
-+void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv);
-+
-+
-+s32 rtw_txframes_pending(_adapter *padapter);
-+s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib);
-+void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry);
-+
-+
-+s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter);
-+void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv);
-+
-+
-+void rtw_alloc_hwxmits(_adapter *padapter);
-+void rtw_free_hwxmits(_adapter *padapter);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
-+s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev);
-+#endif
-+void rtw_xmit_dequeue_callback(_workitem *work);
-+void rtw_xmit_queue_set(struct sta_info *sta);
-+void rtw_xmit_queue_clear(struct sta_info *sta);
-+s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt);
-+s32 rtw_xmit(_adapter *padapter, _pkt **pkt, u16 os_qid);
-+bool xmitframe_hiq_filter(struct xmit_frame *xmitframe);
-+#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS)
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+u8 mgmt_xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe);
-+#endif
-+sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe);
-+void stop_sta_xmit(_adapter *padapter, struct sta_info *psta);
-+void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta);
-+void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta);
-+#endif
-+
-+u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta);
-+
-+void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj);
-+u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw);
-+u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw);
-+s16 rtw_adapter_get_oper_txpwr_max_mbm(_adapter *adapter, bool eirp);
-+s16 rtw_rfctl_get_oper_txpwr_max_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u8 ifbmp_mod, u8 if_op, bool eirp);
-+s16 rtw_get_oper_txpwr_max_mbm(struct dvobj_priv *dvobj, bool erip);
-+s16 rtw_rfctl_get_reg_max_txpwr_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool eirp);
-+
-+u8 query_ra_short_GI(struct sta_info *psta, u8 bw);
-+
-+u8	qos_acm(u8 acm_mask, u8 priority);
-+
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+void	enqueue_pending_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+void enqueue_pending_xmitbuf_to_head(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
-+struct xmit_buf	*dequeue_pending_xmitbuf(struct xmit_priv *pxmitpriv);
-+struct xmit_buf	*select_and_dequeue_pending_xmitbuf(_adapter *padapter);
-+sint	check_pending_xmitbuf(struct xmit_priv *pxmitpriv);
-+thread_return	rtw_xmit_thread(thread_context context);
-+#endif
-+
-+#ifdef CONFIG_TX_AMSDU
-+extern void rtw_amsdu_vo_timeout_handler(void *FunctionContext);
-+extern void rtw_amsdu_vi_timeout_handler(void *FunctionContext);
-+extern void rtw_amsdu_be_timeout_handler(void *FunctionContext);
-+extern void rtw_amsdu_bk_timeout_handler(void *FunctionContext);
-+
-+extern u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority);
-+extern void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status);
-+extern void rtw_amsdu_set_timer(_adapter *padapter, u8 priority);
-+extern void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority);
-+
-+extern s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue);	
-+extern s32 check_amsdu(struct xmit_frame *pxmitframe);
-+extern s32 check_amsdu_tx_support(_adapter *padapter);
-+extern struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame);
-+#endif
-+
-+#ifdef DBG_TXBD_DESC_DUMP
-+void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq);
-+void rtw_tx_desc_backup_reset(void);
-+u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak);
-+#endif
-+
-+#ifdef CONFIG_PCI_TX_POLLING
-+void rtw_tx_poll_init(_adapter *padapter);
-+void rtw_tx_poll_timeout_handler(void *FunctionContext);
-+void rtw_tx_poll_timer_set(_adapter *padapter, u32 delay);
-+void rtw_tx_poll_timer_cancel(_adapter *padapter);
-+#endif
-+
-+u32	rtw_get_ff_hwaddr(struct xmit_frame	*pxmitframe);
-+
-+#ifdef CONFIG_XMIT_ACK
-+int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms);
-+void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status);
-+#endif /* CONFIG_XMIT_ACK */
-+
-+enum XMIT_BLOCK_REASON {
-+	XMIT_BLOCK_NONE = 0,
-+	XMIT_BLOCK_REDLMEM = BIT0, /*LPS-PG*/
-+	XMIT_BLOCK_SUSPEND = BIT1, /*WOW*/
-+	XMIT_BLOCK_MAX = 0xFF,
-+};
-+void rtw_init_xmit_block(_adapter *padapter);
-+void rtw_deinit_xmit_block(_adapter *padapter);
-+
-+#ifdef DBG_XMIT_BLOCK
-+void dump_xmit_block(void *sel, _adapter *padapter);
-+#endif
-+void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason);
-+void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason);
-+bool rtw_is_xmit_blocked(_adapter *padapter);
-+
-+/* include after declaring struct xmit_buf, in order to avoid warning */
-+#include <xmit_osdep.h>
-+
-+#endif /* _RTL871X_XMIT_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/sdio_hal.h b/drivers/staging/rtl8723cs/include/sdio_hal.h
-new file mode 100644
-index 000000000000..6e49835a4154
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/sdio_hal.h
-@@ -0,0 +1,57 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __SDIO_HAL_H__
-+#define __SDIO_HAL_H__
-+
-+void sd_int_dpc(PADAPTER padapter);
-+u8 rtw_set_hal_ops(_adapter *padapter);
-+
-+#ifdef CONFIG_RTL8188E
-+void rtl8188es_set_hal_ops(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8723B
-+void rtl8723bs_set_hal_ops(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8821A
-+void rtl8821as_set_hal_ops(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+void rtl8192es_set_hal_ops(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+void rtl8703bs_set_hal_ops(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+void rtl8723ds_set_hal_ops(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8188F
-+void rtl8188fs_set_hal_ops(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8188GTV
-+void rtl8188gtvs_set_hal_ops(PADAPTER padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8192F
-+void rtl8192fs_set_hal_ops(PADAPTER padapter);
-+#endif
-+
-+#endif /* __SDIO_HAL_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/sdio_ops.h b/drivers/staging/rtl8723cs/include/sdio_ops.h
-new file mode 100644
-index 000000000000..74ddeca291b5
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/sdio_ops.h
-@@ -0,0 +1,207 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __SDIO_OPS_H__
-+#define __SDIO_OPS_H__
-+
-+
-+/* Follow mac team suggestion, default I/O fail return value is 0xFF */
-+#define SDIO_ERR_VAL8	0xFF
-+#define SDIO_ERR_VAL16	0xFFFF
-+#define SDIO_ERR_VAL32	0xFFFFFFFF
-+
-+#ifdef PLATFORM_LINUX
-+#include <sdio_ops_linux.h>
-+#endif
-+
-+extern void sdio_set_intf_ops(_adapter *padapter, struct _io_ops *pops);
-+void dump_sdio_card_info(void *sel, struct dvobj_priv *dvobj);
-+
-+u32 sdio_init(struct dvobj_priv *dvobj);
-+void sdio_deinit(struct dvobj_priv *dvobj);
-+int sdio_alloc_irq(struct dvobj_priv *dvobj);
-+void sdio_free_irq(struct dvobj_priv *dvobj);
-+u8 sdio_get_num_of_func(struct dvobj_priv *dvobj);
-+
-+#if 0
-+extern void sdio_func1cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem);
-+extern void sdio_func1cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem);
-+#endif
-+extern u8 SdioLocalCmd52Read1Byte(PADAPTER padapter, u32 addr);
-+extern void SdioLocalCmd52Write1Byte(PADAPTER padapter, u32 addr, u8 v);
-+extern s32 _sdio_local_read(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);
-+extern s32 sdio_local_read(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);
-+extern s32 _sdio_local_write(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);
-+extern s32 sdio_local_write(PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf);
-+
-+u32 _sdio_read32(PADAPTER padapter, u32 addr);
-+s32 _sdio_write32(PADAPTER padapter, u32 addr, u32 val);
-+
-+extern void sd_int_hdl(PADAPTER padapter);
-+extern u8 CheckIPSStatus(PADAPTER padapter);
-+
-+#ifdef CONFIG_RTL8188E
-+extern void InitInterrupt8188ESdio(PADAPTER padapter);
-+extern void EnableInterrupt8188ESdio(PADAPTER padapter);
-+extern void DisableInterrupt8188ESdio(PADAPTER padapter);
-+extern void UpdateInterruptMask8188ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
-+extern u8 HalQueryTxBufferStatus8189ESdio(PADAPTER padapter);
-+extern u8 HalQueryTxOQTBufferStatus8189ESdio(PADAPTER padapter);
-+extern void ClearInterrupt8188ESdio(PADAPTER padapter);
-+#endif /* CONFIG_RTL8188E */
-+
-+#ifdef CONFIG_RTL8821A
-+extern void InitInterrupt8821AS(PADAPTER padapter);
-+extern void EnableInterrupt8821AS(PADAPTER padapter);
-+extern void DisableInterrupt8821AS(PADAPTER padapter);
-+extern u8 HalQueryTxBufferStatus8821AS(PADAPTER padapter);
-+extern u8 HalQueryTxOQTBufferStatus8821ASdio(PADAPTER padapter);
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+void ClearInterrupt8821AS(PADAPTER padapter);
-+#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */
-+#endif /* CONFIG_RTL8821A */
-+
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+#if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) \
-+    || defined(CONFIG_RTL8723F)
-+u8 rtw_hal_enable_cpwm2(_adapter *adapter);
-+#endif
-+extern u8 RecvOnePkt(PADAPTER padapter);
-+#endif /* CONFIG_WOWLAN */
-+#ifdef CONFIG_RTL8723B
-+extern void InitInterrupt8723BSdio(PADAPTER padapter);
-+extern void InitSysInterrupt8723BSdio(PADAPTER padapter);
-+extern void EnableInterrupt8723BSdio(PADAPTER padapter);
-+extern void DisableInterrupt8723BSdio(PADAPTER padapter);
-+extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter);
-+extern u8 HalQueryTxOQTBufferStatus8723BSdio(PADAPTER padapter);
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+extern void DisableInterruptButCpwm28723BSdio(PADAPTER padapter);
-+extern void ClearInterrupt8723BSdio(PADAPTER padapter);
-+#endif /* CONFIG_WOWLAN */
-+#endif
-+
-+
-+#ifdef CONFIG_RTL8192E
-+extern void InitInterrupt8192ESdio(PADAPTER padapter);
-+extern void EnableInterrupt8192ESdio(PADAPTER padapter);
-+extern void DisableInterrupt8192ESdio(PADAPTER padapter);
-+extern void UpdateInterruptMask8192ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
-+extern u8 HalQueryTxBufferStatus8192ESdio(PADAPTER padapter);
-+extern u8 HalQueryTxOQTBufferStatus8192ESdio(PADAPTER padapter);
-+extern void ClearInterrupt8192ESdio(PADAPTER padapter);
-+#endif /* CONFIG_RTL8192E */
-+
-+#ifdef CONFIG_RTL8703B
-+extern void InitInterrupt8703BSdio(PADAPTER padapter);
-+extern void InitSysInterrupt8703BSdio(PADAPTER padapter);
-+extern void EnableInterrupt8703BSdio(PADAPTER padapter);
-+extern void DisableInterrupt8703BSdio(PADAPTER padapter);
-+extern u8 HalQueryTxBufferStatus8703BSdio(PADAPTER padapter);
-+extern u8 HalQueryTxOQTBufferStatus8703BSdio(PADAPTER padapter);
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+extern void DisableInterruptButCpwm28703BSdio(PADAPTER padapter);
-+extern void ClearInterrupt8703BSdio(PADAPTER padapter);
-+#endif /* CONFIG_WOWLAN */
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+extern void InitInterrupt8723DSdio(PADAPTER padapter);
-+extern void InitSysInterrupt8723DSdio(PADAPTER padapter);
-+extern void EnableInterrupt8723DSdio(PADAPTER padapter);
-+extern void DisableInterrupt8723DSdio(PADAPTER padapter);
-+extern u8 HalQueryTxBufferStatus8723DSdio(PADAPTER padapter);
-+extern u8 HalQueryTxOQTBufferStatus8723DSdio(PADAPTER padapter);
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+extern void DisableInterruptButCpwm28723dSdio(PADAPTER padapter);
-+extern void ClearInterrupt8723DSdio(PADAPTER padapter);
-+#endif /* CONFIG_WOWLAN */
-+#endif
-+
-+#ifdef CONFIG_RTL8192F
-+extern void InitInterrupt8192FSdio(PADAPTER padapter);
-+extern void InitSysInterrupt8192FSdio(PADAPTER padapter);
-+extern void EnableInterrupt8192FSdio(PADAPTER padapter);
-+extern void DisableInterrupt8192FSdio(PADAPTER padapter);
-+extern void UpdateInterruptMask8192FSdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
-+extern u8 HalQueryTxBufferStatus8192FSdio(PADAPTER padapter);
-+extern u8 HalQueryTxOQTBufferStatus8192FSdio(PADAPTER padapter);
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+extern void DisableInterruptButCpwm2192fSdio(PADAPTER padapter);
-+extern void ClearInterrupt8192FSdio(PADAPTER padapter);
-+#endif /* CONFIG_WOWLAN */
-+#endif
-+
-+#ifdef CONFIG_RTL8188F
-+extern void InitInterrupt8188FSdio(PADAPTER padapter);
-+extern void InitSysInterrupt8188FSdio(PADAPTER padapter);
-+extern void EnableInterrupt8188FSdio(PADAPTER padapter);
-+extern void DisableInterrupt8188FSdio(PADAPTER padapter);
-+extern u8 HalQueryTxBufferStatus8188FSdio(PADAPTER padapter);
-+extern u8 HalQueryTxOQTBufferStatus8188FSdio(PADAPTER padapter);
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+extern void DisableInterruptButCpwm28188FSdio(PADAPTER padapter);
-+extern void ClearInterrupt8188FSdio(PADAPTER padapter);
-+#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */
-+#endif
-+
-+#ifdef CONFIG_RTL8188GTV
-+extern void InitInterrupt8188GTVSdio(PADAPTER padapter);
-+extern void InitSysInterrupt8188GTVSdio(PADAPTER padapter);
-+extern void EnableInterrupt8188GTVSdio(PADAPTER padapter);
-+extern void DisableInterrupt8188GTVSdio(PADAPTER padapter);
-+extern u8 HalQueryTxBufferStatus8188GTVSdio(PADAPTER padapter);
-+extern u8 HalQueryTxOQTBufferStatus8188GTVSdio(PADAPTER padapter);
-+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-+extern void DisableInterruptButCpwm28188GTVSdio(PADAPTER padapter);
-+extern void ClearInterrupt8188GTVSdio(PADAPTER padapter);
-+#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */
-+#endif
-+
-+/**
-+ * rtw_sdio_get_block_size() - Get block size of SDIO transfer
-+ * @d		struct dvobj_priv*
-+ *
-+ * The unit of return value is byte.
-+ */
-+static inline u32 rtw_sdio_get_block_size(struct dvobj_priv *d)
-+{
-+	return d->intf_data.block_transfer_len;
-+}
-+
-+/**
-+ * rtw_sdio_cmd53_align_size() - Align size to one CMD53 could complete
-+ * @d		struct dvobj_priv*
-+ * @len		length to align
-+ *
-+ * Adjust len to align block size, and the new size could be transfered by one
-+ * CMD53.
-+ * If len < block size, it would keep original value, otherwise the value
-+ * would be rounded up by block size.
-+ *
-+ * Return adjusted length.
-+ */
-+static inline size_t rtw_sdio_cmd53_align_size(struct dvobj_priv *d, size_t len)
-+{
-+	u32 blk_sz;
-+
-+
-+	blk_sz = rtw_sdio_get_block_size(d);
-+	if (len <= blk_sz)
-+		return len;
-+
-+	return _RND(len, blk_sz);
-+}
-+
-+#endif /* !__SDIO_OPS_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/sdio_ops_ce.h b/drivers/staging/rtl8723cs/include/sdio_ops_ce.h
-new file mode 100644
-index 000000000000..d542cb7ea206
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/sdio_ops_ce.h
-@@ -0,0 +1,49 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _SDIO_OPS_WINCE_H_
-+#define _SDIO_OPS_WINCE_H_
-+
-+#include <drv_conf.h>
-+#include <osdep_service.h>
-+#include <drv_types.h>
-+#include <osdep_intf.h>
-+
-+
-+#ifdef PLATFORM_OS_CE
-+
-+
-+extern u8 sdbus_cmd52r_ce(struct intf_priv *pintfpriv, u32 addr);
-+
-+
-+extern void sdbus_cmd52w_ce(struct intf_priv *pintfpriv, u32 addr, u8 val8);
-+
-+
-+uint sdbus_read_blocks_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
-+
-+extern uint sdbus_read_bytes_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
-+
-+
-+extern uint sdbus_write_blocks_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf, u8 async);
-+
-+extern uint sdbus_write_bytes_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
-+extern u8 sdbus_func1cmd52r_ce(struct intf_priv *pintfpriv, u32 addr);
-+extern void sdbus_func1cmd52w_ce(struct intf_priv *pintfpriv, u32 addr, u8 val8);
-+extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);
-+extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);
-+extern void sdio_read_int(_adapter *padapter, u32 addr, u8 sz, void *pdata);
-+
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/sdio_ops_linux.h b/drivers/staging/rtl8723cs/include/sdio_ops_linux.h
-new file mode 100644
-index 000000000000..4bbd8fe7ff68
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/sdio_ops_linux.h
-@@ -0,0 +1,58 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __SDIO_OPS_LINUX_H__
-+#define __SDIO_OPS_LINUX_H__
-+
-+#ifndef RTW_HALMAC
-+u8 sd_f0_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
-+void sd_f0_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err);
-+
-+s32 _sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);
-+s32 _sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);
-+s32 sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);
-+s32 sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata);
-+
-+u8 _sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
-+u8 sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
-+u16 sd_read16(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
-+u32 _sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
-+u32 sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err);
-+void sd_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err);
-+void sd_write16(struct intf_hdl *pintfhdl, u32 addr, u16 v, s32 *err);
-+void _sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err);
-+void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err);
-+#endif /* RTW_HALMAC */
-+
-+bool rtw_is_sdio30(_adapter *adapter);
-+
-+/* The unit of return value is Hz */
-+static inline u32 rtw_sdio_get_clock(struct dvobj_priv *d)
-+{
-+	return d->intf_data.clock;
-+}
-+
-+s32 _sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);
-+s32 sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);
-+s32 _sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);
-+s32 sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata);
-+
-+void rtw_sdio_set_irq_thd(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl);
-+int __must_check rtw_sdio_raw_read(struct dvobj_priv *d, unsigned int addr,
-+				void *buf, size_t len, bool fixed);
-+int __must_check rtw_sdio_raw_write(struct dvobj_priv *d, unsigned int addr,
-+				void *buf, size_t len, bool fixed);
-+
-+#endif /* __SDIO_OPS_LINUX_H__ */
-+
-diff --git a/drivers/staging/rtl8723cs/include/sdio_ops_xp.h b/drivers/staging/rtl8723cs/include/sdio_ops_xp.h
-new file mode 100644
-index 000000000000..d3d8764d3878
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/sdio_ops_xp.h
-@@ -0,0 +1,49 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _SDIO_OPS_XP_H_
-+#define _SDIO_OPS_XP_H_
-+
-+#include <drv_conf.h>
-+#include <osdep_service.h>
-+#include <drv_types.h>
-+#include <osdep_intf.h>
-+
-+
-+#ifdef PLATFORM_OS_XP
-+
-+
-+extern u8 sdbus_cmd52r_xp(struct intf_priv *pintfpriv, u32 addr);
-+
-+
-+extern void sdbus_cmd52w_xp(struct intf_priv *pintfpriv, u32 addr, u8 val8);
-+
-+
-+uint sdbus_read_blocks_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
-+
-+extern uint sdbus_read_bytes_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
-+
-+
-+extern uint sdbus_write_blocks_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf, u8 async);
-+
-+extern uint sdbus_write_bytes_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf);
-+extern u8 sdbus_func1cmd52r_xp(struct intf_priv *pintfpriv, u32 addr);
-+extern void sdbus_func1cmd52w_xp(struct intf_priv *pintfpriv, u32 addr, u8 val8);
-+extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);
-+extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata);
-+extern void sdio_read_int(_adapter *padapter, u32 addr, u8 sz, void *pdata);
-+
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/sdio_osintf.h b/drivers/staging/rtl8723cs/include/sdio_osintf.h
-new file mode 100644
-index 000000000000..a94e656793af
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/sdio_osintf.h
-@@ -0,0 +1,19 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __SDIO_OSINTF_H__
-+#define __SDIO_OSINTF_H__
-+
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/sta_info.h b/drivers/staging/rtl8723cs/include/sta_info.h
-new file mode 100644
-index 000000000000..9b5fab36c690
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/sta_info.h
-@@ -0,0 +1,782 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __STA_INFO_H_
-+#define __STA_INFO_H_
-+
-+#include <cmn_info/rtw_sta_info.h>
-+
-+#define IBSS_START_MAC_ID	2
-+#define NUM_STA MACID_NUM_SW_LIMIT
-+
-+#ifndef CONFIG_RTW_MACADDR_ACL
-+	#ifdef CONFIG_AP_MODE
-+	#define CONFIG_RTW_MACADDR_ACL 1
-+	#else
-+	#define CONFIG_RTW_MACADDR_ACL 0
-+	#endif
-+#endif
-+
-+#ifndef CONFIG_RTW_PRE_LINK_STA
-+	#define CONFIG_RTW_PRE_LINK_STA 0
-+#endif
-+
-+#define NUM_ACL 16
-+
-+#define RTW_ACL_PERIOD_DEV 0
-+#define RTW_ACL_PERIOD_BSS 1
-+#define RTW_ACL_PERIOD_NUM 2
-+
-+#define RTW_ACL_MODE_DISABLED				0
-+#define RTW_ACL_MODE_ACCEPT_UNLESS_LISTED	1
-+#define RTW_ACL_MODE_DENY_UNLESS_LISTED		2
-+#define RTW_ACL_MODE_MAX					3
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+extern const char *const _acl_period_str[RTW_ACL_PERIOD_NUM];
-+#define acl_period_str(mode) (((mode) >= RTW_ACL_PERIOD_NUM) ? "INVALID" : _acl_period_str[(mode)])
-+extern const char *const _acl_mode_str[RTW_ACL_MODE_MAX];
-+#define acl_mode_str(mode) (((mode) >= RTW_ACL_MODE_MAX) ? "INVALID" : _acl_mode_str[(mode)])
-+#endif
-+
-+#ifndef RTW_PRE_LINK_STA_NUM
-+	#define RTW_PRE_LINK_STA_NUM 8
-+#endif
-+
-+struct pre_link_sta_node_t {
-+	u8 valid;
-+	u8 addr[ETH_ALEN];
-+};
-+
-+struct pre_link_sta_ctl_t {
-+	_lock lock;
-+	u8 num;
-+	struct pre_link_sta_node_t node[RTW_PRE_LINK_STA_NUM];
-+};
-+
-+#ifdef CONFIG_TDLS
-+#define MAX_ALLOWED_TDLS_STA_NUM	4
-+#endif
-+
-+enum sta_info_update_type {
-+	STA_INFO_UPDATE_NONE = 0,
-+	STA_INFO_UPDATE_BW = BIT(0),
-+	STA_INFO_UPDATE_RATE = BIT(1),
-+	STA_INFO_UPDATE_PROTECTION_MODE = BIT(2),
-+	STA_INFO_UPDATE_CAP = BIT(3),
-+	STA_INFO_UPDATE_HT_CAP = BIT(4),
-+	STA_INFO_UPDATE_VHT_CAP = BIT(5),
-+	STA_INFO_UPDATE_ALL = STA_INFO_UPDATE_BW
-+			      | STA_INFO_UPDATE_RATE
-+			      | STA_INFO_UPDATE_PROTECTION_MODE
-+			      | STA_INFO_UPDATE_CAP
-+			      | STA_INFO_UPDATE_HT_CAP
-+			      | STA_INFO_UPDATE_VHT_CAP,
-+	STA_INFO_UPDATE_MAX
-+};
-+
-+struct rtw_wlan_acl_node {
-+	_list		        list;
-+	u8       addr[ETH_ALEN];
-+	u8       valid;
-+};
-+
-+struct wlan_acl_pool {
-+	int mode;
-+	int num;
-+	struct rtw_wlan_acl_node aclnode[NUM_ACL];
-+	_queue	acl_node_q;
-+};
-+
-+struct	stainfo_stats	{
-+	systime last_rx_time;
-+
-+	u64 rx_mgnt_pkts;
-+	u64 rx_beacon_pkts;
-+	u64 rx_probereq_pkts;
-+	u64 rx_probersp_pkts; /* unicast to self */
-+	u64 rx_probersp_bm_pkts;
-+	u64 rx_probersp_uo_pkts; /* unicast to others */
-+	u64 rx_ctrl_pkts;
-+	u64 rx_data_pkts;
-+	u64 rx_data_bc_pkts;
-+	u64 rx_data_mc_pkts;
-+	u64 rx_data_qos_pkts[TID_NUM]; /* unicast only */
-+
-+	u64	last_rx_mgnt_pkts;
-+	u64 last_rx_beacon_pkts;
-+	u64 last_rx_probereq_pkts;
-+	u64 last_rx_probersp_pkts; /* unicast to self */
-+	u64 last_rx_probersp_bm_pkts;
-+	u64 last_rx_probersp_uo_pkts; /* unicast to others */
-+	u64	last_rx_ctrl_pkts;
-+	u64	last_rx_data_pkts;
-+	u64 last_rx_data_bc_pkts;
-+	u64 last_rx_data_mc_pkts;
-+	u64 last_rx_data_qos_pkts[TID_NUM]; /* unicast only */
-+
-+#ifdef CONFIG_TDLS
-+	u64 rx_tdls_disc_rsp_pkts;
-+	u64 last_rx_tdls_disc_rsp_pkts;
-+#endif
-+
-+	u64	rx_bytes;
-+	u64	rx_bc_bytes;
-+	u64	rx_mc_bytes;
-+	u64	last_rx_bytes;
-+	u64 last_rx_bc_bytes;
-+	u64 last_rx_mc_bytes;
-+	u64	rx_drops; /* TBD */
-+	u32 rx_tp_kbits;
-+	u32 smooth_rx_tp_kbits;
-+
-+	u64	tx_pkts;
-+	u64	last_tx_pkts;
-+
-+	u64	tx_bytes;
-+	u64	last_tx_bytes;
-+	u64 tx_drops; /* TBD */
-+	u32 tx_tp_kbits;
-+	u32 smooth_tx_tp_kbits;
-+
-+#ifdef CONFIG_LPS_CHK_BY_TP
-+	u64 acc_tx_bytes;
-+	u64 acc_rx_bytes;
-+#endif
-+
-+	/* unicast only */
-+	u64 last_rx_data_uc_pkts; /* For Read & Clear requirement in proc_get_rx_stat() */
-+	u32 duplicate_cnt;	/* Read & Clear, in proc_get_rx_stat() */
-+	u32 rxratecnt[128];	/* Read & Clear, in proc_get_rx_stat() */
-+	u32 tx_ok_cnt;		/* Read & Clear, in proc_get_tx_stat() */
-+	u32 tx_fail_cnt;	/* Read & Clear, in proc_get_tx_stat() */
-+	u32 tx_retry_cnt;	/* Read & Clear, in proc_get_tx_stat() */
-+#ifdef CONFIG_RTW_MESH
-+	u32 rx_hwmp_pkts;
-+	u32 last_rx_hwmp_pkts;
-+#endif
-+};
-+
-+#ifndef DBG_SESSION_TRACKER
-+#define DBG_SESSION_TRACKER 0
-+#endif
-+
-+/* session tracker status */
-+#define ST_STATUS_NONE		0
-+#define ST_STATUS_CHECK		BIT0
-+#define ST_STATUS_ESTABLISH	BIT1
-+#define ST_STATUS_EXPIRE	BIT2
-+
-+#define ST_EXPIRE_MS (10 * 1000)
-+
-+struct session_tracker {
-+	_list list; /* session_tracker_queue */
-+	u32 local_naddr;
-+	u16 local_port;
-+	u32 remote_naddr;
-+	u16 remote_port;
-+	systime set_time;
-+	u8 status;
-+};
-+
-+/* session tracker cmd */
-+#define ST_CMD_ADD 0
-+#define ST_CMD_DEL 1
-+#define ST_CMD_CHK 2
-+
-+struct st_cmd_parm {
-+	u8 cmd;
-+	struct sta_info *sta;
-+	u32 local_naddr; /* TODO: IPV6 */
-+	u16 local_port;
-+	u32 remote_naddr; /* TODO: IPV6 */
-+	u16 remote_port;
-+};
-+
-+typedef bool (*st_match_rule)(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);
-+
-+struct st_register {
-+	u8 s_proto;
-+	st_match_rule rule;
-+};
-+
-+#define SESSION_TRACKER_REG_ID_WFD 0
-+#define SESSION_TRACKER_REG_ID_NUM 1
-+
-+struct st_ctl_t {
-+	struct st_register reg[SESSION_TRACKER_REG_ID_NUM];
-+	_queue tracker_q;
-+};
-+
-+void rtw_st_ctl_init(struct st_ctl_t *st_ctl);
-+void rtw_st_ctl_deinit(struct st_ctl_t *st_ctl);
-+void rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_register *reg);
-+void rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id);
-+bool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto);
-+bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port);
-+void rtw_st_ctl_rx(struct sta_info *sta, u8 *ehdr_pos);
-+void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl);
-+
-+#ifdef CONFIG_TDLS
-+struct TDLS_PeerKey {
-+	u8 kck[16]; /* TPK-KCK */
-+	u8 tk[16]; /* TPK-TK; only CCMP will be used */
-+} ;
-+#endif /* CONFIG_TDLS */
-+
-+#ifdef DBG_RX_DFRAME_RAW_DATA
-+struct sta_recv_dframe_info {
-+
-+	u8 sta_data_rate;
-+	u8 sta_sgi;
-+	u8 sta_bw_mode;
-+	s8 sta_mimo_signal_strength[4];
-+	s8 sta_RxPwr[4];
-+	u8 sta_ofdm_snr[4];
-+};
-+#endif
-+
-+#ifdef CONFIG_RTW_MESH
-+struct mesh_plink_ent;
-+struct rtw_ewma_err_rate {
-+	unsigned long internal;
-+};
-+
-+/* Mesh airtime link metrics parameters */
-+struct rtw_atlm_param {
-+	struct rtw_ewma_err_rate err_rate; /* Now is PACKET error rate */
-+	u16 data_rate; /* The unit is 100Kbps */
-+	u16 total_pkt;
-+	u16 overhead; /* Channel access overhead */
-+};
-+#endif
-+
-+struct sta_info {
-+
-+	_lock	lock;
-+	_list	list; /* free_sta_queue */
-+	_list	hash_list; /* sta_hash */
-+	/* _list asoc_list; */ /* 20061114 */
-+	/* _list sleep_list; */ /* sleep_q */
-+	/* _list wakeup_list; */ /* wakeup_q */
-+	_adapter *padapter;
-+	struct cmn_sta_info cmn;
-+
-+	struct sta_xmit_priv sta_xmitpriv;
-+	struct sta_recv_priv sta_recvpriv;
-+
-+#ifdef DBG_RX_DFRAME_RAW_DATA
-+	struct sta_recv_dframe_info  sta_dframe_info;
-+	struct sta_recv_dframe_info  sta_dframe_info_bmc;
-+#endif
-+	_queue sleep_q;
-+	unsigned int sleepq_len;
-+#ifdef CONFIG_RTW_MGMT_QUEUE
-+	_queue mgmt_sleep_q;
-+	unsigned int mgmt_sleepq_len;
-+#endif
-+
-+	uint state;
-+	uint qos_option;
-+	u16 hwseq;
-+
-+#ifdef CONFIG_RTW_80211K
-+	u8 rm_en_cap[5];
-+	u8 rm_diag_token;
-+#endif /* CONFIG_RTW_80211K */
-+
-+	systime	resp_nonenc_eapol_key_starttime;
-+	uint	ieee8021x_blocked;	/* 0: allowed, 1:blocked */
-+	uint	dot118021XPrivacy; /* aes, tkip... */
-+	union Keytype	dot11tkiptxmickey;
-+	union Keytype	dot11tkiprxmickey;
-+	union Keytype	dot118021x_UncstKey;
-+	union pn48		dot11txpn;			/* PN48 used for Unicast xmit */
-+	union pn48		dot11rxpn;			/* PN48 used for Unicast recv. */
-+#ifdef CONFIG_RTW_MESH
-+	/* peer's GTK, RX only */
-+	u8 group_privacy;
-+	u8 gtk_bmp;
-+	union Keytype gtk;
-+	union pn48 gtk_pn;
-+	#ifdef CONFIG_IEEE80211W
-+	/* peer's IGTK, RX only */
-+	enum security_type dot11wCipher;
-+	u8 igtk_bmp;
-+	u8 igtk_id;
-+	union Keytype igtk;
-+	union pn48 igtk_pn;
-+	#endif /* CONFIG_IEEE80211W */
-+#endif /* CONFIG_RTW_MESH */
-+#ifdef CONFIG_GTK_OL
-+	u8 kek[RTW_KEK_LEN];
-+	u8 kck[RTW_KCK_LEN];
-+	u8 replay_ctr[RTW_REPLAY_CTR_LEN];
-+#endif /* CONFIG_GTK_OL */
-+#ifdef CONFIG_IEEE80211W
-+	_timer dot11w_expire_timer;
-+#endif /* CONFIG_IEEE80211W */
-+
-+	u8	bssrateset[16];
-+	u32	bssratelen;
-+
-+	u8	cts2self;
-+	u8	rtsen;
-+
-+	u8	init_rate;
-+	u8	wireless_mode;	/* NETWORK_TYPE */
-+
-+	struct stainfo_stats sta_stats;
-+
-+#ifdef CONFIG_TDLS
-+	u32	tdls_sta_state;
-+	u8	SNonce[32];
-+	u8	ANonce[32];
-+	u32	TDLS_PeerKey_Lifetime;
-+	u32	TPK_count;
-+	_timer	TPK_timer;
-+	struct TDLS_PeerKey	tpk;
-+#ifdef CONFIG_TDLS_CH_SW
-+	u16	ch_switch_time;
-+	u16	ch_switch_timeout;
-+	/* u8	option; */
-+	_timer	ch_sw_timer;
-+	_timer	delay_timer;
-+	_timer	stay_on_base_chnl_timer;
-+	_timer	ch_sw_monitor_timer;
-+#endif
-+	_timer handshake_timer;
-+	u8 alive_count;
-+	_timer	pti_timer;
-+	u8	TDLS_RSNIE[20];	/* Save peer's RSNIE, used for sending TDLS_SETUP_RSP */
-+#endif /* CONFIG_TDLS */
-+
-+	/* for A-MPDU TX, ADDBA timeout check	 */
-+	_timer addba_retry_timer;
-+
-+	/* for A-MPDU Rx reordering buffer control */
-+	struct recv_reorder_ctrl recvreorder_ctrl[TID_NUM];
-+	ATOMIC_T continual_no_rx_packet[TID_NUM];
-+	/* for A-MPDU Tx */
-+	/* unsigned char		ampdu_txen_bitmap; */
-+	u16	BA_starting_seqctrl[16];
-+
-+
-+#ifdef CONFIG_80211N_HT
-+	struct ht_priv	htpriv;
-+#endif
-+
-+#ifdef CONFIG_80211AC_VHT
-+	struct vht_priv	vhtpriv;
-+#endif
-+
-+	/* Notes:	 */
-+	/* STA_Mode: */
-+	/* curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO	 */
-+	/* scan_q: AP CAP/INFO */
-+
-+	/* AP_Mode: */
-+	/* curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO */
-+	/* sta_info: (AP & STA) CAP/INFO */
-+
-+	unsigned int expire_to;
-+
-+	int flags;
-+
-+	u8 bpairwise_key_installed;
-+
-+#ifdef CONFIG_AP_MODE
-+
-+	_list asoc_list;
-+	_list auth_list;
-+
-+	unsigned int auth_seq;
-+	unsigned int authalg;
-+	unsigned char chg_txt[128];
-+
-+	u16 capability;
-+
-+	int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */
-+	int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */
-+	int wpa_group_cipher;
-+	int wpa2_group_cipher;
-+	int wpa_pairwise_cipher;
-+	int wpa2_pairwise_cipher;
-+
-+	u32 akm_suite_type;
-+
-+#ifdef CONFIG_RTW_80211R
-+	u8 ft_pairwise_key_installed;
-+#endif
-+
-+#ifdef CONFIG_NATIVEAP_MLME
-+	u8 wpa_ie[32];
-+
-+	u8 nonerp_set;
-+	u8 no_short_slot_time_set;
-+	u8 no_short_preamble_set;
-+	u8 no_ht_gf_set;
-+	u8 no_ht_set;
-+	u8 ht_20mhz_set;
-+	u8 ht_40mhz_intolerant;
-+#endif /* CONFIG_NATIVEAP_MLME */
-+
-+#ifdef CONFIG_ATMEL_RC_PATCH
-+	u8 flag_atmel_rc;
-+#endif
-+
-+	u8 qos_info;
-+
-+	u8 max_sp_len;
-+	u8 uapsd_bk;/* BIT(0): Delivery enabled, BIT(1): Trigger enabled */
-+	u8 uapsd_be;
-+	u8 uapsd_vi;
-+	u8 uapsd_vo;
-+
-+	u8 has_legacy_ac;
-+	unsigned int sleepq_ac_len;
-+
-+#ifdef CONFIG_P2P
-+	/* p2p priv data */
-+	u8 is_p2p_device;
-+	u8 p2p_status_code;
-+
-+	/* p2p client info */
-+	u8 dev_addr[ETH_ALEN];
-+	/* u8 iface_addr[ETH_ALEN]; */ /* = hwaddr[ETH_ALEN] */
-+	u8 dev_cap;
-+	u16 config_methods;
-+	u8 primary_dev_type[8];
-+	u8 num_of_secdev_type;
-+	u8 secdev_types_list[32];/* 32/8 == 4; */
-+	u16 dev_name_len;
-+	u8 dev_name[32];
-+#endif /* CONFIG_P2P */
-+
-+#ifdef CONFIG_WFD
-+	u8 op_wfd_mode;
-+#endif
-+
-+#if !defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && defined(CONFIG_80211N_HT)
-+	u8 under_exist_checking;
-+#endif
-+
-+	u8 keep_alive_trycnt;
-+
-+#ifdef CONFIG_AUTO_AP_MODE
-+	u8 isrc; /* this device is rc */
-+	u16 pid; /* pairing id */
-+#endif
-+
-+#endif /* CONFIG_AP_MODE	 */
-+
-+#ifdef CONFIG_RTW_MESH
-+	struct mesh_plink_ent *plink;
-+
-+	u8 local_mps;
-+	u8 peer_mps;
-+	u8 nonpeer_mps;
-+
-+	struct rtw_atlm_param metrics;
-+	/* The reference for nexthop_lookup */
-+	BOOLEAN alive;
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	u8 *pauth_frame;
-+	u32 auth_len;
-+	u8 *passoc_req;
-+	u32 assoc_req_len;
-+#endif
-+
-+	u8		IOTPeer;			/* Enum value.	HT_IOT_PEER_E */
-+#ifdef CONFIG_LPS_PG
-+	u8		lps_pg_rssi_lv;
-+#endif
-+
-+	/* To store the sequence number of received management frame */
-+	u16 RxMgmtFrameSeqNum;
-+
-+	struct st_ctl_t st_ctl;
-+	u8 max_agg_num_minimal_record; /*keep minimal tx desc max_agg_num setting*/
-+	u8 curr_rx_rate;
-+	u8 curr_rx_rate_bmc;
-+#ifdef CONFIG_RTS_FULL_BW
-+	bool vendor_8812;
-+#endif
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	u8 tbtx_enable;			/* Does this sta_info support & enable TBTX function? */
-+//	u8 tbtx_timeslot;		/* This sta_info belong to which time slot.	*/
-+#endif
-+
-+	/*
-+	 * Vaiables for queuing TX pkt a short period of time
-+	 * to wait something ready.
-+	 */
-+	u8 tx_q_enable;
-+	struct __queue tx_queue;
-+	_workitem tx_q_work;
-+};
-+
-+#ifdef CONFIG_RTW_MESH
-+#define STA_SET_MESH_PLINK(sta, link) (sta)->plink = link
-+#else
-+#define STA_SET_MESH_PLINK(sta, link) do {} while (0)
-+#endif
-+
-+#define sta_tx_pkts(sta) \
-+	(sta->sta_stats.tx_pkts)
-+
-+#define sta_last_tx_pkts(sta) \
-+	(sta->sta_stats.last_tx_pkts)
-+
-+#define sta_rx_pkts(sta) \
-+	(sta->sta_stats.rx_mgnt_pkts \
-+	 + sta->sta_stats.rx_ctrl_pkts \
-+	 + sta->sta_stats.rx_data_pkts)
-+
-+#define sta_last_rx_pkts(sta) \
-+	(sta->sta_stats.last_rx_mgnt_pkts \
-+	 + sta->sta_stats.last_rx_ctrl_pkts \
-+	 + sta->sta_stats.last_rx_data_pkts)
-+
-+#define sta_rx_data_pkts(sta) (sta->sta_stats.rx_data_pkts)
-+#define sta_last_rx_data_pkts(sta) (sta->sta_stats.last_rx_data_pkts)
-+
-+#define sta_rx_data_uc_pkts(sta) (sta->sta_stats.rx_data_pkts - sta->sta_stats.rx_data_bc_pkts - sta->sta_stats.rx_data_mc_pkts)
-+#define sta_last_rx_data_uc_pkts(sta) (sta->sta_stats.last_rx_data_pkts - sta->sta_stats.last_rx_data_bc_pkts - sta->sta_stats.last_rx_data_mc_pkts)
-+
-+#define sta_rx_data_qos_pkts(sta, i) \
-+	(sta->sta_stats.rx_data_qos_pkts[i])
-+
-+#define sta_last_rx_data_qos_pkts(sta, i) \
-+	(sta->sta_stats.last_rx_data_qos_pkts[i])
-+
-+#define sta_rx_mgnt_pkts(sta) \
-+	(sta->sta_stats.rx_mgnt_pkts)
-+
-+#define sta_last_rx_mgnt_pkts(sta) \
-+	(sta->sta_stats.last_rx_mgnt_pkts)
-+
-+#define sta_rx_beacon_pkts(sta) \
-+	(sta->sta_stats.rx_beacon_pkts)
-+
-+#define sta_last_rx_beacon_pkts(sta) \
-+	(sta->sta_stats.last_rx_beacon_pkts)
-+
-+#define sta_rx_probereq_pkts(sta) \
-+	(sta->sta_stats.rx_probereq_pkts)
-+
-+#define sta_last_rx_probereq_pkts(sta) \
-+	(sta->sta_stats.last_rx_probereq_pkts)
-+
-+#define sta_rx_probersp_pkts(sta) \
-+	(sta->sta_stats.rx_probersp_pkts)
-+
-+#define sta_last_rx_probersp_pkts(sta) \
-+	(sta->sta_stats.last_rx_probersp_pkts)
-+
-+#define sta_rx_probersp_bm_pkts(sta) \
-+	(sta->sta_stats.rx_probersp_bm_pkts)
-+
-+#define sta_last_rx_probersp_bm_pkts(sta) \
-+	(sta->sta_stats.last_rx_probersp_bm_pkts)
-+
-+#define sta_rx_probersp_uo_pkts(sta) \
-+	(sta->sta_stats.rx_probersp_uo_pkts)
-+
-+#define sta_last_rx_probersp_uo_pkts(sta) \
-+	(sta->sta_stats.last_rx_probersp_uo_pkts)
-+
-+#ifdef CONFIG_RTW_MESH
-+#define update_last_rx_hwmp_pkts(sta) \
-+	do { \
-+		sta->sta_stats.last_rx_hwmp_pkts = sta->sta_stats.rx_hwmp_pkts; \
-+	} while(0)
-+#else
-+#define update_last_rx_hwmp_pkts(sta) do {} while(0)
-+#endif
-+
-+#define sta_update_last_rx_pkts(sta) \
-+	do { \
-+		int __i; \
-+		\
-+		sta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \
-+		sta->sta_stats.last_rx_beacon_pkts = sta->sta_stats.rx_beacon_pkts; \
-+		sta->sta_stats.last_rx_probereq_pkts = sta->sta_stats.rx_probereq_pkts; \
-+		sta->sta_stats.last_rx_probersp_pkts = sta->sta_stats.rx_probersp_pkts; \
-+		sta->sta_stats.last_rx_probersp_bm_pkts = sta->sta_stats.rx_probersp_bm_pkts; \
-+		sta->sta_stats.last_rx_probersp_uo_pkts = sta->sta_stats.rx_probersp_uo_pkts; \
-+		sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \
-+		update_last_rx_hwmp_pkts(sta); \
-+		\
-+		sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \
-+		sta->sta_stats.last_rx_data_bc_pkts = sta->sta_stats.rx_data_bc_pkts; \
-+		sta->sta_stats.last_rx_data_mc_pkts = sta->sta_stats.rx_data_mc_pkts; \
-+		for (__i = 0; __i < TID_NUM; __i++) \
-+			sta->sta_stats.last_rx_data_qos_pkts[__i] = sta->sta_stats.rx_data_qos_pkts[__i]; \
-+	} while (0)
-+
-+#define STA_RX_PKTS_ARG(sta) \
-+	sta->sta_stats.rx_mgnt_pkts \
-+	, sta->sta_stats.rx_ctrl_pkts \
-+	, sta->sta_stats.rx_data_pkts
-+
-+#define STA_LAST_RX_PKTS_ARG(sta) \
-+	sta->sta_stats.last_rx_mgnt_pkts \
-+	, sta->sta_stats.last_rx_ctrl_pkts \
-+	, sta->sta_stats.last_rx_data_pkts
-+
-+#define STA_RX_PKTS_DIFF_ARG(sta) \
-+	sta->sta_stats.rx_mgnt_pkts - sta->sta_stats.last_rx_mgnt_pkts \
-+	, sta->sta_stats.rx_ctrl_pkts - sta->sta_stats.last_rx_ctrl_pkts \
-+	, sta->sta_stats.rx_data_pkts - sta->sta_stats.last_rx_data_pkts
-+
-+#define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)"
-+
-+#define sta_rx_uc_bytes(sta) (sta->sta_stats.rx_bytes - sta->sta_stats.rx_bc_bytes - sta->sta_stats.rx_mc_bytes)
-+#define sta_last_rx_uc_bytes(sta) (sta->sta_stats.last_rx_bytes - sta->sta_stats.last_rx_bc_bytes - sta->sta_stats.last_rx_mc_bytes)
-+
-+#ifdef CONFIG_WFD
-+#define STA_OP_WFD_MODE(sta) (sta)->op_wfd_mode
-+#define STA_SET_OP_WFD_MODE(sta, mode) (sta)->op_wfd_mode = (mode)
-+#else
-+#define STA_OP_WFD_MODE(sta) 0
-+#define STA_SET_OP_WFD_MODE(sta, mode) do {} while (0)
-+#endif
-+
-+#define AID_BMP_LEN(max_aid) ((max_aid + 1) / 8 + (((max_aid + 1) % 8) ? 1 : 0))
-+
-+struct	sta_priv {
-+
-+	u8 *pallocated_stainfo_buf;
-+	u8 *pstainfo_buf;
-+	_queue	free_sta_queue;
-+
-+	_lock sta_hash_lock;
-+	_list   sta_hash[NUM_STA];
-+	int asoc_sta_count;
-+	_queue sleep_q;
-+	_queue wakeup_q;
-+
-+	_adapter *padapter;
-+
-+	u32 adhoc_expire_to;
-+
-+	int rx_chk_limit;
-+
-+#ifdef CONFIG_AP_MODE
-+	_list asoc_list;
-+	_list auth_list;
-+	_lock asoc_list_lock;
-+	_lock auth_list_lock;
-+	u8 asoc_list_cnt;
-+	u8 auth_list_cnt;
-+
-+	unsigned int auth_to;  /* sec, time to expire in authenticating. */
-+	unsigned int assoc_to; /* sec, time to expire before associating. */
-+	unsigned int expire_to; /* sec , time to expire after associated. */
-+
-+	/*
-+	* pointers to STA info; based on allocated AID or NULL if AID free
-+	* AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1
-+	*/
-+	struct sta_info **sta_aid;
-+	u16 max_aid;
-+	u16 started_aid; /* started AID for allocation search */
-+	bool rr_aid; /* round robin AID allocation, will modify started_aid */
-+	u8 aid_bmp_len; /* in byte */
-+	u8 *sta_dz_bitmap;
-+	u8 *tim_bitmap;
-+
-+	u16 max_num_sta;
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+	struct wlan_acl_pool acl_list[RTW_ACL_PERIOD_NUM];
-+#endif
-+
-+	#if CONFIG_RTW_PRE_LINK_STA
-+	struct pre_link_sta_ctl_t pre_link_sta_ctl;
-+	#endif
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	u8 tbtx_asoc_list_cnt;
-+	struct sta_info *token_holder[NR_MAXSTA_INSLOT];
-+	struct sta_info *last_token_holder;
-+	ATOMIC_T nr_token_keeper;
-+#endif
-+#endif /* CONFIG_AP_MODE */
-+
-+#ifdef CONFIG_ATMEL_RC_PATCH
-+	u8 atmel_rc_pattern[6];
-+#endif
-+	u8 c2h_sta_mac[ETH_ALEN];
-+	u8 c2h_adapter_id;
-+	struct submit_ctx *gotc2h;
-+};
-+
-+
-+__inline static u32 wifi_mac_hash(const u8 *mac)
-+{
-+	u32 x;
-+
-+	x = mac[0];
-+	x = (x << 2) ^ mac[1];
-+	x = (x << 2) ^ mac[2];
-+	x = (x << 2) ^ mac[3];
-+	x = (x << 2) ^ mac[4];
-+	x = (x << 2) ^ mac[5];
-+
-+	x ^= x >> 8;
-+	x  = x & (NUM_STA - 1);
-+
-+	return x;
-+}
-+
-+
-+extern u32	_rtw_init_sta_priv(struct sta_priv *pstapriv);
-+extern u32	_rtw_free_sta_priv(struct sta_priv *pstapriv);
-+
-+#define stainfo_offset_valid(offset) (offset < NUM_STA && offset >= 0)
-+int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta);
-+struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset);
-+
-+extern struct sta_info *rtw_alloc_stainfo(struct	sta_priv *pstapriv, const u8 *hwaddr);
-+extern u32	rtw_free_stainfo(_adapter *padapter , struct sta_info *psta);
-+extern void rtw_free_all_stainfo(_adapter *padapter);
-+extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr);
-+extern u32 rtw_init_bcmc_stainfo(_adapter *padapter);
-+extern struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter);
-+
-+#ifdef CONFIG_AP_MODE
-+u16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta);
-+void dump_aid_status(void *sel, _adapter *adapter);
-+#endif
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+extern u8 rtw_access_ctrl(_adapter *adapter, const u8 *mac_addr);
-+void dump_macaddr_acl(void *sel, _adapter *adapter);
-+#endif
-+
-+bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr);
-+#if CONFIG_RTW_PRE_LINK_STA
-+struct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr);
-+void rtw_pre_link_sta_del(struct sta_priv *stapriv, u8 *hwaddr);
-+void rtw_pre_link_sta_ctl_reset(struct sta_priv *stapriv);
-+void rtw_pre_link_sta_ctl_init(struct sta_priv *stapriv);
-+void rtw_pre_link_sta_ctl_deinit(struct sta_priv *stapriv);
-+void dump_pre_link_sta_ctl(void *sel, struct sta_priv *stapriv);
-+#endif /* CONFIG_RTW_PRE_LINK_STA */
-+
-+#endif /* _STA_INFO_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/usb_hal.h b/drivers/staging/rtl8723cs/include/usb_hal.h
-new file mode 100644
-index 000000000000..2d7776f0695d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/usb_hal.h
-@@ -0,0 +1,71 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __USB_HAL_H__
-+#define __USB_HAL_H__
-+
-+int usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz);
-+void usb_free_recv_priv(_adapter *padapter, u16 ini_in_buf_sz);
-+#ifdef CONFIG_FW_C2H_REG
-+void usb_c2h_hisr_hdl(_adapter *adapter, u8 *buf);
-+#endif
-+
-+u8 rtw_set_hal_ops(_adapter *padapter);
-+
-+#ifdef CONFIG_RTL8188E
-+void rtl8188eu_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+void rtl8812au_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8192E
-+void rtl8192eu_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+
-+#ifdef CONFIG_RTL8723B
-+void rtl8723bu_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+void rtl8814au_set_hal_ops(_adapter *padapter);
-+#endif /* CONFIG_RTL8814A */
-+
-+#ifdef CONFIG_RTL8188F
-+void rtl8188fu_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8188GTV
-+void rtl8188gtvu_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+void rtl8703bu_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+void rtl8723du_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8710B
-+void rtl8710bu_set_hal_ops(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RTL8192F
-+void rtl8192fu_set_hal_ops(_adapter *padapter);
-+#endif /* CONFIG_RTL8192F */
-+
-+#endif /* __USB_HAL_H__ */
-diff --git a/drivers/staging/rtl8723cs/include/usb_ops.h b/drivers/staging/rtl8723cs/include/usb_ops.h
-new file mode 100644
-index 000000000000..6d5435d65741
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/usb_ops.h
-@@ -0,0 +1,153 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __USB_OPS_H_
-+#define __USB_OPS_H_
-+
-+
-+#define REALTEK_USB_VENQT_READ		0xC0
-+#define REALTEK_USB_VENQT_WRITE	0x40
-+#define REALTEK_USB_VENQT_CMD_REQ	0x05
-+#define REALTEK_USB_VENQT_CMD_IDX	0x00
-+#define REALTEK_USB_IN_INT_EP_IDX	1
-+
-+enum {
-+	VENDOR_WRITE = 0x00,
-+	VENDOR_READ = 0x01,
-+};
-+#define ALIGNMENT_UNIT				16
-+#define MAX_VENDOR_REQ_CMD_SIZE	254		/* 8188cu SIE Support */
-+#define MAX_USB_IO_CTL_SIZE		(MAX_VENDOR_REQ_CMD_SIZE + ALIGNMENT_UNIT)
-+
-+#ifdef PLATFORM_LINUX
-+#include <usb_ops_linux.h>
-+#endif /* PLATFORM_LINUX */
-+
-+#ifdef CONFIG_RTL8188E
-+void rtl8188eu_set_hw_type(struct dvobj_priv *pdvobj);
-+#ifdef CONFIG_SUPPORT_USB_INT
-+void interrupt_handler_8188eu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
-+#endif
-+#endif
-+
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
-+void rtl8812au_set_hw_type(struct dvobj_priv *pdvobj);
-+#ifdef CONFIG_SUPPORT_USB_INT
-+void interrupt_handler_8812au(_adapter *padapter, u16 pkt_len, u8 *pbuf);
-+#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8814A
-+void rtl8814au_set_hw_type(struct dvobj_priv *pdvobj);
-+#ifdef CONFIG_SUPPORT_USB_INT
-+void interrupt_handler_8814au(_adapter *padapter, u16 pkt_len, u8 *pbuf);
-+#endif
-+#endif /* CONFIG_RTL8814 */
-+
-+#ifdef CONFIG_RTL8192E
-+void rtl8192eu_set_hw_type(struct dvobj_priv *pdvobj);
-+#ifdef CONFIG_SUPPORT_USB_INT
-+void interrupt_handler_8192eu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
-+#endif
-+
-+#endif
-+
-+#ifdef CONFIG_RTL8188F
-+void rtl8188fu_set_hw_type(struct dvobj_priv *pdvobj);
-+#ifdef CONFIG_SUPPORT_USB_INT
-+void interrupt_handler_8188fu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
-+#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8188GTV
-+void rtl8188gtvu_set_hw_type(struct dvobj_priv *pdvobj);
-+#ifdef CONFIG_SUPPORT_USB_INT
-+void interrupt_handler_8188gtvu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
-+#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8723B
-+void rtl8723bu_set_hw_type(struct dvobj_priv *pdvobj);
-+#ifdef CONFIG_SUPPORT_USB_INT
-+void interrupt_handler_8723bu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
-+#endif
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+void rtl8703bu_set_hw_type(struct dvobj_priv *pdvobj);
-+#ifdef CONFIG_SUPPORT_USB_INT
-+void interrupt_handler_8703bu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
-+#endif /* CONFIG_SUPPORT_USB_INT */
-+#endif /* CONFIG_RTL8703B */
-+
-+void usb_set_intf_ops(_adapter *padapter, struct _io_ops *pops);
-+
-+#ifdef CONFIG_RTL8723D
-+void rtl8723du_set_hw_type(struct dvobj_priv *pdvobj);
-+void rtl8723du_set_intf_ops(struct _io_ops *pops);
-+void rtl8723du_recv_tasklet(void *priv);
-+void rtl8723du_xmit_tasklet(void *priv);
-+#ifdef CONFIG_SUPPORT_USB_INT
-+void interrupt_handler_8723du(_adapter *padapter, u16 pkt_len, u8 *pbuf);
-+#endif /* CONFIG_SUPPORT_USB_INT */
-+#endif /* CONFIG_RTL8723D */
-+
-+#ifdef CONFIG_RTL8710B
-+void rtl8710bu_set_hw_type(struct dvobj_priv *pdvobj);
-+void rtl8710bu_set_intf_ops(struct _io_ops *pops);
-+void rtl8710bu_recv_tasklet(void *priv);
-+void rtl8710bu_xmit_tasklet(void *priv);
-+#ifdef CONFIG_SUPPORT_USB_INT
-+void interrupt_handler_8710bu(_adapter *padapter, u16 pkt_len, u8 *pbuf);
-+#endif /* CONFIG_SUPPORT_USB_INT */
-+#endif /* CONFIG_RTL8710B */
-+
-+#ifdef CONFIG_RTL8192F
-+void rtl8192fu_set_hw_type(struct dvobj_priv *pdvobj);
-+void rtl8192fu_xmit_tasklet(void *priv);
-+#ifdef CONFIG_SUPPORT_USB_INT
-+void rtl8192fu_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf);
-+#endif /* CONFIG_SUPPORT_USB_INT */
-+#endif /* CONFIG_RTL8192F */
-+
-+enum RTW_USB_SPEED {
-+	RTW_USB_SPEED_UNKNOWN	= 0,
-+	RTW_USB_SPEED_1_1	= 1,
-+	RTW_USB_SPEED_2		= 2,
-+	RTW_USB_SPEED_3		= 3,
-+};
-+
-+#define IS_FULL_SPEED_USB(Adapter)	(adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_1_1)
-+#define IS_HIGH_SPEED_USB(Adapter)	(adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_2)
-+#define IS_SUPER_SPEED_USB(Adapter)	(adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_3)
-+
-+#define USB_SUPER_SPEED_BULK_SIZE	1024	/* usb 3.0 */
-+#define USB_HIGH_SPEED_BULK_SIZE	512		/* usb 2.0 */
-+#define USB_FULL_SPEED_BULK_SIZE	64		/* usb 1.1 */
-+
-+static inline u8 rtw_usb_bulk_size_boundary(_adapter *padapter, int buf_len)
-+{
-+	u8 rst = _TRUE;
-+
-+	if (IS_SUPER_SPEED_USB(padapter))
-+		rst = (0 == (buf_len) % USB_SUPER_SPEED_BULK_SIZE) ? _TRUE : _FALSE;
-+	else if (IS_HIGH_SPEED_USB(padapter))
-+		rst = (0 == (buf_len) % USB_HIGH_SPEED_BULK_SIZE) ? _TRUE : _FALSE;
-+	else
-+		rst = (0 == (buf_len) % USB_FULL_SPEED_BULK_SIZE) ? _TRUE : _FALSE;
-+	return rst;
-+}
-+
-+
-+#endif /* __USB_OPS_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/usb_ops_linux.h b/drivers/staging/rtl8723cs/include/usb_ops_linux.h
-new file mode 100644
-index 000000000000..bf59ca0fa51a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/usb_ops_linux.h
-@@ -0,0 +1,98 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __USB_OPS_LINUX_H__
-+#define __USB_OPS_LINUX_H__
-+
-+#define VENDOR_CMD_MAX_DATA_LEN	254
-+#define FW_START_ADDRESS	0x1000
-+
-+#define RTW_USB_CONTROL_MSG_TIMEOUT_TEST	10/* ms */
-+#define RTW_USB_CONTROL_MSG_TIMEOUT	500/* ms */
-+
-+#define RECV_BULK_IN_ADDR		0x80/* assign by drv, not real address */
-+#define RECV_INT_IN_ADDR		0x81/* assign by drv, not real address */
-+
-+#define INTERRUPT_MSG_FORMAT_LEN 60
-+
-+#if defined(CONFIG_VENDOR_REQ_RETRY) && defined(CONFIG_USB_VENDOR_REQ_MUTEX)
-+	/* vendor req retry should be in the situation when each vendor req is atomically submitted from others */
-+	#define MAX_USBCTRL_VENDORREQ_TIMES	10
-+#else
-+	#define MAX_USBCTRL_VENDORREQ_TIMES	1
-+#endif
-+
-+#define RTW_USB_BULKOUT_TIMEOUT	5000/* ms */
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18))
-+#define _usbctrl_vendorreq_async_callback(urb, regs)	_usbctrl_vendorreq_async_callback(urb)
-+#define usb_bulkout_zero_complete(purb, regs)	usb_bulkout_zero_complete(purb)
-+#define usb_write_mem_complete(purb, regs)	usb_write_mem_complete(purb)
-+#define usb_write_port_complete(purb, regs)	usb_write_port_complete(purb)
-+#define usb_read_port_complete(purb, regs)	usb_read_port_complete(purb)
-+#define usb_read_interrupt_complete(purb, regs)	usb_read_interrupt_complete(purb)
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 12))
-+#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size, timeout_ms) \
-+	usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), (timeout_ms))
-+#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \
-+	usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), (timeout_ms))
-+#else
-+#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size, timeout_ms) \
-+	usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), \
-+		((timeout_ms) == 0) || ((timeout_ms) * HZ / 1000 > 0) ? ((timeout_ms) * HZ / 1000) : 1)
-+#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \
-+	usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), \
-+		((timeout_ms) == 0) || ((timeout_ms) * HZ / 1000 > 0) ? ((timeout_ms) * HZ / 1000) : 1)
-+#endif
-+
-+
-+#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
-+int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val);
-+int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val);
-+int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val);
-+#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */
-+
-+unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr);
-+
-+void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem);
-+void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem);
-+
-+void usb_read_port_cancel(struct intf_hdl *pintfhdl);
-+
-+u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem);
-+void usb_write_port_cancel(struct intf_hdl *pintfhdl);
-+
-+int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype);
-+#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
-+int _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request,
-+		u16 value, u16 index, void *pdata, u16 len, u8 requesttype);
-+#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */
-+
-+u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr);
-+u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr);
-+u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr);
-+int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val);
-+int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val);
-+int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val);
-+int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
-+u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem);
-+void usb_recv_tasklet(void *priv);
-+
-+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
-+void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs);
-+u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr);
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/usb_osintf.h b/drivers/staging/rtl8723cs/include/usb_osintf.h
-new file mode 100644
-index 000000000000..48495b492fcc
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/usb_osintf.h
-@@ -0,0 +1,26 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __USB_OSINTF_H
-+#define __USB_OSINTF_H
-+
-+#include <usb_vendor_req.h>
-+
-+#define USBD_HALTED(Status) ((u32)(Status) >> 30 == 3)
-+
-+
-+u8 usbvendorrequest(struct dvobj_priv *pdvobjpriv, RT_USB_BREQUEST brequest, RT_USB_WVALUE wvalue, u8 windex, void *data, u8 datalen, u8 isdirectionin);
-+
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/usb_vendor_req.h b/drivers/staging/rtl8723cs/include/usb_vendor_req.h
-new file mode 100644
-index 000000000000..3e25878639ae
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/usb_vendor_req.h
-@@ -0,0 +1,56 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _USB_VENDOR_REQUEST_H_
-+#define _USB_VENDOR_REQUEST_H_
-+
-+/* 4	Set/Get Register related wIndex/Data */
-+#define	RT_USB_RESET_MASK_OFF		0
-+#define	RT_USB_RESET_MASK_ON		1
-+#define	RT_USB_SLEEP_MASK_OFF		0
-+#define	RT_USB_SLEEP_MASK_ON		1
-+#define	RT_USB_LDO_ON				1
-+#define	RT_USB_LDO_OFF				0
-+
-+/* 4	Set/Get SYSCLK related	wValue or Data */
-+#define	RT_USB_SYSCLK_32KHZ		0
-+#define	RT_USB_SYSCLK_40MHZ		1
-+#define	RT_USB_SYSCLK_60MHZ		2
-+
-+
-+typedef enum _RT_USB_BREQUEST {
-+	RT_USB_SET_REGISTER		= 1,
-+	RT_USB_SET_SYSCLK		= 2,
-+	RT_USB_GET_SYSCLK		= 3,
-+	RT_USB_GET_REGISTER		= 4
-+} RT_USB_BREQUEST;
-+
-+
-+typedef enum _RT_USB_WVALUE {
-+	RT_USB_RESET_MASK	=	1,
-+	RT_USB_SLEEP_MASK	=	2,
-+	RT_USB_USB_HRCPWM	=	3,
-+	RT_USB_LDO			=	4,
-+	RT_USB_BOOT_TYPE	=	5
-+} RT_USB_WVALUE;
-+
-+
-+#if 0
-+BOOLEAN usbvendorrequest(PCE_USB_DEVICE	CEdevice, RT_USB_BREQUEST bRequest, RT_USB_WVALUE wValue, u8 wIndex, void *Data, u8 DataLength, BOOLEAN isDirectionIn);
-+BOOLEAN CEusbGetStatusRequest(PCE_USB_DEVICE CEdevice, u16 Op, u16 Index, void *Data);
-+BOOLEAN CEusbFeatureRequest(PCE_USB_DEVICE CEdevice, u16 Op, u16 FeatureSelector, u16 Index);
-+BOOLEAN CEusbGetDescriptorRequest(PCE_USB_DEVICE CEdevice, short urbLength, u8 DescriptorType, u8 Index, u16 LanguageId, void *TransferBuffer, u32 TransferBufferLength);
-+#endif
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/include/wifi.h b/drivers/staging/rtl8723cs/include/wifi.h
-new file mode 100644
-index 000000000000..d07b349ac5bc
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/wifi.h
-@@ -0,0 +1,1369 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef _WIFI_H_
-+#define _WIFI_H_
-+
-+
-+#ifndef BIT
-+#define BIT(x)	(1 << (x))
-+#endif
-+#ifndef BIT_ULL
-+#define BIT_ULL(x)	(1ULL << (x))
-+#endif
-+
-+
-+#define WLAN_ETHHDR_LEN		14
-+#define WLAN_ETHADDR_LEN	6
-+#define WLAN_IEEE_OUI_LEN	3
-+#define WLAN_ADDR_LEN		6
-+#define WLAN_CRC_LEN		4
-+#define WLAN_BSSID_LEN		6
-+#define WLAN_BSS_TS_LEN		8
-+#define WLAN_HDR_A3_LEN		24
-+#define WLAN_HDR_A4_LEN		30
-+#define WLAN_HDR_A3_QOS_LEN	26
-+#define WLAN_HDR_A4_QOS_LEN	32
-+#define WLAN_SSID_MAXLEN	32
-+#define WLAN_DATA_MAXLEN	2312
-+
-+#define WLAN_A3_PN_OFFSET	24
-+#define WLAN_A4_PN_OFFSET	30
-+
-+#define WLAN_MIN_ETHFRM_LEN	60
-+#define WLAN_MAX_ETHFRM_LEN	1514
-+#define WLAN_ETHHDR_LEN		14
-+#define WLAN_WMM_LEN		24
-+#define VENDOR_NAME_LEN		20
-+
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+#define WLAN_MAX_VENDOR_IE_LEN 255
-+#define WLAN_MAX_VENDOR_IE_NUM 5
-+#define WIFI_BEACON_VENDOR_IE_BIT BIT(0)
-+#define WIFI_PROBEREQ_VENDOR_IE_BIT BIT(1)
-+#define WIFI_PROBERESP_VENDOR_IE_BIT BIT(2)
-+#define WIFI_ASSOCREQ_VENDOR_IE_BIT BIT(3)
-+#define WIFI_ASSOCRESP_VENDOR_IE_BIT BIT(4)
-+#ifdef CONFIG_P2P
-+#define WIFI_P2P_PROBEREQ_VENDOR_IE_BIT BIT(5)
-+#define WIFI_P2P_PROBERESP_VENDOR_IE_BIT BIT(6)
-+#define WLAN_MAX_VENDOR_IE_MASK_MAX 7
-+#else
-+#define WLAN_MAX_VENDOR_IE_MASK_MAX 5
-+#endif
-+#endif
-+
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+#define WLAN_MAX_KEEP_ALIVE_IE_LEN 256
-+#endif/*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+
-+#define P80211CAPTURE_VERSION	0x80211001
-+
-+/* This value is tested by WiFi 11n Test Plan 5.2.3.
-+ * This test verifies the WLAN NIC can update the NAV through sending the CTS with large duration. */
-+#define	WiFiNavUpperUs				30000	/* 30 ms */
-+
-+#ifdef GREEN_HILL
-+#pragma pack(1)
-+#endif
-+
-+enum WIFI_FRAME_TYPE {
-+	WIFI_MGT_TYPE  =	(0),
-+	WIFI_CTRL_TYPE =	(BIT(2)),
-+	WIFI_DATA_TYPE =	(BIT(3)),
-+	WIFI_QOS_DATA_TYPE	= (BIT(7) | BIT(3)),	/* !< QoS Data	 */
-+};
-+
-+enum WIFI_FRAME_SUBTYPE {
-+
-+	/* below is for mgt frame */
-+	WIFI_ASSOCREQ       = (0 | WIFI_MGT_TYPE),
-+	WIFI_ASSOCRSP       = (BIT(4) | WIFI_MGT_TYPE),
-+	WIFI_REASSOCREQ     = (BIT(5) | WIFI_MGT_TYPE),
-+	WIFI_REASSOCRSP     = (BIT(5) | BIT(4) | WIFI_MGT_TYPE),
-+	WIFI_PROBEREQ       = (BIT(6) | WIFI_MGT_TYPE),
-+	WIFI_PROBERSP       = (BIT(6) | BIT(4) | WIFI_MGT_TYPE),
-+	WIFI_BEACON         = (BIT(7) | WIFI_MGT_TYPE),
-+	WIFI_ATIM           = (BIT(7) | BIT(4) | WIFI_MGT_TYPE),
-+	WIFI_DISASSOC       = (BIT(7) | BIT(5) | WIFI_MGT_TYPE),
-+	WIFI_AUTH           = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE),
-+	WIFI_DEAUTH         = (BIT(7) | BIT(6) | WIFI_MGT_TYPE),
-+	WIFI_ACTION         = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE),
-+	WIFI_ACTION_NOACK = (BIT(7) | BIT(6) | BIT(5) | WIFI_MGT_TYPE),
-+
-+	/* below is for control frame */
-+	WIFI_BF_REPORT_POLL = (BIT(6) | WIFI_CTRL_TYPE),
-+	WIFI_NDPA         = (BIT(6) | BIT(4) | WIFI_CTRL_TYPE),
-+	WIFI_BAR            = (BIT(7) | WIFI_CTRL_TYPE),
-+	WIFI_PSPOLL         = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE),
-+	WIFI_RTS            = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE),
-+	WIFI_CTS            = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE),
-+	WIFI_ACK            = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE),
-+	WIFI_CFEND          = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE),
-+	WIFI_CFEND_CFACK    = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE),
-+
-+	/* below is for data frame */
-+	WIFI_DATA           = (0 | WIFI_DATA_TYPE),
-+	WIFI_DATA_CFACK     = (BIT(4) | WIFI_DATA_TYPE),
-+	WIFI_DATA_CFPOLL    = (BIT(5) | WIFI_DATA_TYPE),
-+	WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE),
-+	WIFI_DATA_NULL      = (BIT(6) | WIFI_DATA_TYPE),
-+	WIFI_CF_ACK         = (BIT(6) | BIT(4) | WIFI_DATA_TYPE),
-+	WIFI_CF_POLL        = (BIT(6) | BIT(5) | WIFI_DATA_TYPE),
-+	WIFI_CF_ACKPOLL     = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE),
-+	WIFI_QOS_DATA_NULL	= (BIT(6) | WIFI_QOS_DATA_TYPE),
-+};
-+
-+enum WIFI_REASON_CODE	{
-+	_RSON_RESERVED_					= 0,
-+	_RSON_UNSPECIFIED_				= 1,
-+	_RSON_AUTH_NO_LONGER_VALID_		= 2,
-+	_RSON_DEAUTH_STA_LEAVING_		= 3,
-+	_RSON_INACTIVITY_				= 4,
-+	_RSON_UNABLE_HANDLE_			= 5,
-+	_RSON_CLS2_						= 6,
-+	_RSON_CLS3_						= 7,
-+	_RSON_DISAOC_STA_LEAVING_		= 8,
-+	_RSON_ASOC_NOT_AUTH_			= 9,
-+
-+	/* WPA reason */
-+	_RSON_INVALID_IE_				= 13,
-+	_RSON_MIC_FAILURE_				= 14,
-+	_RSON_4WAY_HNDSHK_TIMEOUT_		= 15,
-+	_RSON_GROUP_KEY_UPDATE_TIMEOUT_	= 16,
-+	_RSON_DIFF_IE_					= 17,
-+	_RSON_MLTCST_CIPHER_NOT_VALID_	= 18,
-+	_RSON_UNICST_CIPHER_NOT_VALID_	= 19,
-+	_RSON_AKMP_NOT_VALID_			= 20,
-+	_RSON_UNSUPPORT_RSNE_VER_		= 21,
-+	_RSON_INVALID_RSNE_CAP_			= 22,
-+	_RSON_IEEE_802DOT1X_AUTH_FAIL_	= 23,
-+
-+	/* belowing are Realtek definition */
-+	_RSON_PMK_NOT_AVAILABLE_		= 24,
-+	_RSON_TDLS_TEAR_TOOFAR_			= 25,
-+	_RSON_TDLS_TEAR_UN_RSN_			= 26,
-+};
-+
-+/* Reason codes (IEEE 802.11-2007, 7.3.1.7, Table 7-22) */
-+#if 0
-+#define WLAN_REASON_UNSPECIFIED 1
-+#define WLAN_REASON_PREV_AUTH_NOT_VALID 2
-+#define WLAN_REASON_DEAUTH_LEAVING 3
-+#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4
-+#define WLAN_REASON_DISASSOC_AP_BUSY 5
-+#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6
-+#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7
-+#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8
-+#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9
-+#endif
-+/* IEEE 802.11h */
-+#define WLAN_REASON_PWR_CAPABILITY_NOT_VALID 10
-+#define WLAN_REASON_SUPPORTED_CHANNEL_NOT_VALID 11
-+#if 0
-+/* IEEE 802.11i */
-+#define WLAN_REASON_INVALID_IE 13
-+#define WLAN_REASON_MICHAEL_MIC_FAILURE 14
-+#define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT 15
-+#define WLAN_REASON_GROUP_KEY_UPDATE_TIMEOUT 16
-+#define WLAN_REASON_IE_IN_4WAY_DIFFERS 17
-+#define WLAN_REASON_GROUP_CIPHER_NOT_VALID 18
-+#define WLAN_REASON_PAIRWISE_CIPHER_NOT_VALID 19
-+#define WLAN_REASON_AKMP_NOT_VALID 20
-+#define WLAN_REASON_UNSUPPORTED_RSN_IE_VERSION 21
-+#define WLAN_REASON_INVALID_RSN_IE_CAPAB 22
-+#define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23
-+#define WLAN_REASON_CIPHER_SUITE_REJECTED 24
-+#endif
-+
-+enum WIFI_STATUS_CODE {
-+	_STATS_SUCCESSFUL_			= 0,
-+	_STATS_FAILURE_				= 1,
-+	_STATS_SEC_DISABLED_			= 5,
-+	_STATS_NOT_IN_SAME_BSS_		= 7,
-+	_STATS_CAP_FAIL_			= 10,
-+	_STATS_NO_ASOC_				= 11,
-+	_STATS_OTHER_				= 12,
-+	_STATS_NO_SUPP_ALG_			= 13,
-+	_STATS_OUT_OF_AUTH_SEQ_		= 14,
-+	_STATS_CHALLENGE_FAIL_		= 15,
-+	_STATS_AUTH_TIMEOUT_		= 16,
-+	_STATS_UNABLE_HANDLE_STA_	= 17,
-+	_STATS_RATE_FAIL_			= 18,
-+	_STATS_REFUSED_TEMPORARILY_ = 30,
-+	_STATS_DECLINE_REQ_			= 37,
-+	_STATS_INVALID_PARAMETERS_	= 38,
-+	_STATS_INVALID_RSNIE_			= 72,
-+};
-+
-+/* Status codes (IEEE 802.11-2007, 7.3.1.9, Table 7-23) */
-+#if 0
-+#define WLAN_STATUS_SUCCESS 0
-+#define WLAN_STATUS_UNSPECIFIED_FAILURE 1
-+#define WLAN_STATUS_CAPS_UNSUPPORTED 10
-+#define WLAN_STATUS_REASSOC_NO_ASSOC 11
-+#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12
-+#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13
-+#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14
-+#define WLAN_STATUS_CHALLENGE_FAIL 15
-+#define WLAN_STATUS_AUTH_TIMEOUT 16
-+#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17
-+#define WLAN_STATUS_ASSOC_DENIED_RATES 18
-+#endif
-+/* entended */
-+/* IEEE 802.11b */
-+#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19
-+#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20
-+#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21
-+/* IEEE 802.11h */
-+#define WLAN_STATUS_SPEC_MGMT_REQUIRED 22
-+#define WLAN_STATUS_PWR_CAPABILITY_NOT_VALID 23
-+#define WLAN_STATUS_SUPPORTED_CHANNEL_NOT_VALID 24
-+/* IEEE 802.11g */
-+#define WLAN_STATUS_ASSOC_DENIED_NO_SHORT_SLOT_TIME 25
-+#define WLAN_STATUS_ASSOC_DENIED_NO_ER_PBCC 26
-+#define WLAN_STATUS_ASSOC_DENIED_NO_DSSS_OFDM 27
-+/* IEEE 802.11w */
-+#define WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY 30
-+#define WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION 31
-+/* IEEE 802.11i */
-+#define WLAN_STATUS_INVALID_IE 40
-+#define WLAN_STATUS_GROUP_CIPHER_NOT_VALID 41
-+#define WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID 42
-+#define WLAN_STATUS_AKMP_NOT_VALID 43
-+#define WLAN_STATUS_UNSUPPORTED_RSN_IE_VERSION 44
-+#define WLAN_STATUS_INVALID_RSN_IE_CAPAB 45
-+#define WLAN_STATUS_CIPHER_REJECTED_PER_POLICY 46
-+#define WLAN_STATUS_TS_NOT_CREATED 47
-+#define WLAN_STATUS_DIRECT_LINK_NOT_ALLOWED 48
-+#define WLAN_STATUS_DEST_STA_NOT_PRESENT 49
-+#define WLAN_STATUS_DEST_STA_NOT_QOS_STA 50
-+#define WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE 51
-+/* IEEE 802.11r */
-+#define WLAN_STATUS_INVALID_FT_ACTION_FRAME_COUNT 52
-+#define WLAN_STATUS_INVALID_PMKID 53
-+#define WLAN_STATUS_INVALID_MDIE 54
-+#define WLAN_STATUS_INVALID_FTIE 55
-+
-+
-+enum WIFI_REG_DOMAIN {
-+	DOMAIN_FCC		= 1,
-+	DOMAIN_IC		= 2,
-+	DOMAIN_ETSI		= 3,
-+	DOMAIN_SPAIN	= 4,
-+	DOMAIN_FRANCE	= 5,
-+	DOMAIN_MKK		= 6,
-+	DOMAIN_ISRAEL	= 7,
-+	DOMAIN_MKK1		= 8,
-+	DOMAIN_MKK2		= 9,
-+	DOMAIN_MKK3		= 10,
-+	DOMAIN_MAX
-+};
-+
-+#define _TO_DS_		BIT(8)
-+#define _FROM_DS_	BIT(9)
-+#define _MORE_FRAG_	BIT(10)
-+#define _RETRY_		BIT(11)
-+#define _PWRMGT_	BIT(12)
-+#define _MORE_DATA_	BIT(13)
-+#define _PRIVACY_	BIT(14)
-+#define _ORDER_			BIT(15)
-+
-+#define SetToDs(pbuf)	\
-+	do	{	\
-+		*(unsigned short *)(pbuf) |= cpu_to_le16(_TO_DS_); \
-+	} while (0)
-+
-+#define GetToDs(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_TO_DS_)) != 0)
-+
-+#define ClearToDs(pbuf)	\
-+	do	{	\
-+		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_TO_DS_)); \
-+	} while (0)
-+
-+#define SetFrDs(pbuf)	\
-+	do	{	\
-+		*(unsigned short *)(pbuf) |= cpu_to_le16(_FROM_DS_); \
-+	} while (0)
-+
-+#define GetFrDs(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_FROM_DS_)) != 0)
-+
-+#define ClearFrDs(pbuf)	\
-+	do	{	\
-+		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_FROM_DS_)); \
-+	} while (0)
-+
-+#define get_tofr_ds(pframe)	((GetFrDs(pframe) << 1) | GetToDs(pframe))
-+
-+
-+#define SetMFrag(pbuf)	\
-+	do	{	\
-+		*(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_FRAG_); \
-+	} while (0)
-+
-+#define GetMFrag(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_FRAG_)) != 0)
-+
-+#define ClearMFrag(pbuf)	\
-+	do	{	\
-+		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_FRAG_)); \
-+	} while (0)
-+
-+#define SetRetry(pbuf)	\
-+	do	{	\
-+		*(unsigned short *)(pbuf) |= cpu_to_le16(_RETRY_); \
-+	} while (0)
-+
-+#define GetRetry(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_RETRY_)) != 0)
-+
-+#define ClearRetry(pbuf)	\
-+	do	{	\
-+		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_RETRY_)); \
-+	} while (0)
-+
-+#define SetPwrMgt(pbuf)	\
-+	do	{	\
-+		*(unsigned short *)(pbuf) |= cpu_to_le16(_PWRMGT_); \
-+	} while (0)
-+
-+#define GetPwrMgt(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_PWRMGT_)) != 0)
-+
-+#define ClearPwrMgt(pbuf)	\
-+	do	{	\
-+		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_PWRMGT_)); \
-+	} while (0)
-+
-+#define SetMData(pbuf)	\
-+	do	{	\
-+		*(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_DATA_); \
-+	} while (0)
-+
-+#define GetMData(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_DATA_)) != 0)
-+
-+#define ClearMData(pbuf)	\
-+	do	{	\
-+		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_DATA_)); \
-+	} while (0)
-+
-+#define SetPrivacy(pbuf)	\
-+	do	{	\
-+		*(unsigned short *)(pbuf) |= cpu_to_le16(_PRIVACY_); \
-+	} while (0)
-+
-+#define GetPrivacy(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_PRIVACY_)) != 0)
-+
-+#define ClearPrivacy(pbuf)	\
-+	do	{	\
-+		*(unsigned short *)(pbuf) &= (~cpu_to_le16(_PRIVACY_)); \
-+	} while (0)
-+
-+
-+#define GetOrder(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0)
-+
-+#define GetFrameType(pbuf)	(le16_to_cpu(*(unsigned short *)(pbuf)) & (BIT(3) | BIT(2)))
-+
-+#define SetFrameType(pbuf, type)	\
-+	do {	\
-+		*(unsigned short *)(pbuf) &= __constant_cpu_to_le16(~(BIT(3) | BIT(2))); \
-+		*(unsigned short *)(pbuf) |= __constant_cpu_to_le16(type); \
-+	} while (0)
-+
-+#define get_frame_sub_type(pbuf)	(cpu_to_le16(*(unsigned short *)(pbuf)) & (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2)))
-+
-+
-+#define set_frame_sub_type(pbuf, type) \
-+	do {    \
-+		*(unsigned short *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))); \
-+		*(unsigned short *)(pbuf) |= cpu_to_le16(type); \
-+	} while (0)
-+
-+
-+#define GetSequence(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) >> 4)
-+
-+#define GetFragNum(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & 0x0f)
-+
-+#define GetTupleCache(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)))
-+
-+#define SetFragNum(pbuf, num) \
-+	do {    \
-+		*(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \
-+			((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu(~(0x000f))) | \
-+				cpu_to_le16(0x0f & (num));     \
-+	} while (0)
-+
-+#define SetSeqNum(pbuf, num) \
-+	do {    \
-+		*(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \
-+			((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu((unsigned short)~0xfff0)) | \
-+			le16_to_cpu((unsigned short)(0xfff0 & (num << 4))); \
-+	} while (0)
-+
-+#define set_duration(pbuf, dur) \
-+	do {    \
-+		*(unsigned short *)((SIZE_PTR)(pbuf) + 2) = cpu_to_le16(0xffff & (dur)); \
-+	} while (0)
-+
-+
-+/* QoS control field */
-+#define SetPriority(qc, tid)	SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 0, 4, tid)
-+#define SetEOSP(qc, eosp)		SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 4, 1, eosp)
-+#define SetAckpolicy(qc, ack)	SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 5, 2, ack)
-+#define SetAMsdu(qc, amsdu)		SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 7, 1, amsdu)
-+
-+#define GetPriority(qc)		LE_BITS_TO_2BYTE(((u8 *)(qc)), 0, 4)
-+#define GetEOSP(qc)			LE_BITS_TO_2BYTE(((u8 *)(qc)), 4, 1)
-+#define GetAckpolicy(qc)	LE_BITS_TO_2BYTE(((u8 *)(qc)), 5, 2)
-+#define GetAMsdu(qc)		LE_BITS_TO_2BYTE(((u8 *)(qc)), 7, 1)
-+
-+/* QoS control field (MSTA only) */
-+#define set_mctrl_present(qc, p)	SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 8, 1, p)
-+#define set_mps_lv(qc, lv)			SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 9, 1, lv)
-+#define set_rspi(qc, rspi)			SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 10, 1, rspi)
-+
-+#define get_mctrl_present(qc)	LE_BITS_TO_2BYTE(((u8 *)(qc)), 8, 1)
-+#define get_mps_lv(qc)			LE_BITS_TO_2BYTE(((u8 *)(qc)), 9, 1)
-+#define get_rspi(qc)			LE_BITS_TO_2BYTE(((u8 *)(qc)), 10, 1)
-+
-+
-+#define GetAid(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 2)) & 0x3fff)
-+
-+#define GetTid(pbuf)	(cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + (((GetToDs(pbuf)<<1) | GetFrDs(pbuf)) == 3 ? 30 : 24))) & 0x000f)
-+
-+#define GetAddr1Ptr(pbuf)	((unsigned char *)((SIZE_PTR)(pbuf) + 4))
-+
-+#define get_addr2_ptr(pbuf)	((unsigned char *)((SIZE_PTR)(pbuf) + 10))
-+
-+#define GetAddr3Ptr(pbuf)	((unsigned char *)((SIZE_PTR)(pbuf) + 16))
-+
-+#define GetAddr4Ptr(pbuf)	((unsigned char *)((SIZE_PTR)(pbuf) + 24))
-+
-+
-+#define MacAddr_isBcst(addr) \
-+	(\
-+	 ((addr[0] == 0xff) && (addr[1] == 0xff) && \
-+	  (addr[2] == 0xff) && (addr[3] == 0xff) && \
-+	  (addr[4] == 0xff) && (addr[5] == 0xff)) ? _TRUE : _FALSE \
-+	)
-+
-+__inline static int IS_MCAST(const u8 *da)
-+{
-+	if ((*da) & 0x01)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+__inline static unsigned char *get_ra(unsigned char *pframe)
-+{
-+	unsigned char	*ra;
-+	ra = GetAddr1Ptr(pframe);
-+	return ra;
-+}
-+__inline static unsigned char *get_ta(unsigned char *pframe)
-+{
-+	unsigned char	*ta;
-+	ta = get_addr2_ptr(pframe);
-+	return ta;
-+}
-+
-+/* can't apply to mesh mode */
-+__inline static unsigned char *get_da(unsigned char *pframe)
-+{
-+	unsigned char	*da;
-+	unsigned int	to_fr_ds	= (GetFrDs(pframe) << 1) | GetToDs(pframe);
-+
-+	switch (to_fr_ds) {
-+	case 0x00:	/* ToDs=0, FromDs=0 */
-+		da = GetAddr1Ptr(pframe);
-+		break;
-+	case 0x01:	/* ToDs=1, FromDs=0 */
-+		da = GetAddr3Ptr(pframe);
-+		break;
-+	case 0x02:	/* ToDs=0, FromDs=1 */
-+		da = GetAddr1Ptr(pframe);
-+		break;
-+	default:	/* ToDs=1, FromDs=1 */
-+		da = GetAddr3Ptr(pframe);
-+		break;
-+	}
-+
-+	return da;
-+}
-+
-+/* can't apply to mesh mode */
-+__inline static unsigned char *get_sa(unsigned char *pframe)
-+{
-+	unsigned char	*sa;
-+	unsigned int	to_fr_ds	= (GetFrDs(pframe) << 1) | GetToDs(pframe);
-+
-+	switch (to_fr_ds) {
-+	case 0x00:	/* ToDs=0, FromDs=0 */
-+		sa = get_addr2_ptr(pframe);
-+		break;
-+	case 0x01:	/* ToDs=1, FromDs=0 */
-+		sa = get_addr2_ptr(pframe);
-+		break;
-+	case 0x02:	/* ToDs=0, FromDs=1 */
-+		sa = GetAddr3Ptr(pframe);
-+		break;
-+	default:	/* ToDs=1, FromDs=1 */
-+		sa = GetAddr4Ptr(pframe);
-+		break;
-+	}
-+
-+	return sa;
-+}
-+
-+/* can't apply to mesh mode */
-+__inline static unsigned char *get_hdr_bssid(unsigned char *pframe)
-+{
-+	unsigned char	*bssid= NULL;
-+	unsigned int	to_fr_ds	= (GetFrDs(pframe) << 1) | GetToDs(pframe);
-+
-+	switch (to_fr_ds) {
-+	case 0x00:	/* ToDs=0, FromDs=0 */
-+		bssid = GetAddr3Ptr(pframe);
-+		break;
-+	case 0x01:	/* ToDs=1, FromDs=0 */
-+		bssid = GetAddr1Ptr(pframe);
-+		break;
-+	case 0x02:	/* ToDs=0, FromDs=1 */
-+		bssid = get_addr2_ptr(pframe);
-+		break;
-+	case 0x03:	/* ToDs=1, FromDs=1 */
-+		bssid = GetAddr1Ptr(pframe);
-+		break;
-+	}
-+
-+	return bssid;
-+}
-+
-+
-+__inline static int IsFrameTypeCtrl(unsigned char *pframe)
-+{
-+	if (WIFI_CTRL_TYPE == GetFrameType(pframe))
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+static inline int IsFrameTypeMgnt(unsigned char *pframe)
-+{
-+	if (GetFrameType(pframe) == WIFI_MGT_TYPE)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+static inline int IsFrameTypeData(unsigned char *pframe)
-+{
-+	if (GetFrameType(pframe) == WIFI_DATA_TYPE)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+
-+/*-----------------------------------------------------------------------------
-+			Below is for the security related definition
-+------------------------------------------------------------------------------*/
-+#define _RESERVED_FRAME_TYPE_	0
-+#define _SKB_FRAME_TYPE_		2
-+#define _PRE_ALLOCMEM_			1
-+#define _PRE_ALLOCHDR_			3
-+#define _PRE_ALLOCLLCHDR_		4
-+#define _PRE_ALLOCICVHDR_		5
-+#define _PRE_ALLOCMICHDR_		6
-+
-+#define _SIFSTIME_				((priv->pmib->dot11BssType.net_work_type&WIRELESS_11A) ? 16 : 10)
-+#define _ACKCTSLNG_				14	/* 14 bytes long, including crclng */
-+#define _CRCLNG_				4
-+
-+#define _ASOCREQ_IE_OFFSET_		4	/* excluding wlan_hdr */
-+#define	_ASOCRSP_IE_OFFSET_		6
-+#define _REASOCREQ_IE_OFFSET_	10
-+#define _REASOCRSP_IE_OFFSET_	6
-+#define _PROBEREQ_IE_OFFSET_	0
-+#define	_PROBERSP_IE_OFFSET_	12
-+#define _AUTH_IE_OFFSET_		6
-+#define _DEAUTH_IE_OFFSET_		0
-+#define _BEACON_IE_OFFSET_		12
-+#define _PUBLIC_ACTION_IE_OFFSET_	8
-+
-+#define _FIXED_IE_LENGTH_			_BEACON_IE_OFFSET_
-+
-+#define _SSID_IE_				0
-+#define _SUPPORTEDRATES_IE_	1
-+#define _DSSET_IE_				3
-+#define _TIM_IE_					5
-+#define _IBSS_PARA_IE_			6
-+#define _COUNTRY_IE_			7
-+#define _CHLGETXT_IE_			16
-+#define _SUPPORTED_CH_IE_		36
-+#define _CH_SWTICH_ANNOUNCE_	37	/* Secondary Channel Offset */
-+#define	_MEAS_REQ_IE_		38
-+#define	_MEAS_RSP_IE_		39
-+#define _RSN_IE_2_				48
-+#define _SSN_IE_1_					221
-+#define _ERPINFO_IE_			42
-+#define _EXT_SUPPORTEDRATES_IE_	50
-+
-+#define _HT_CAPABILITY_IE_			45
-+#define _MDIE_					54
-+#define _FTIE_					55
-+#define _TIMEOUT_ITVL_IE_			56
-+#define _SRC_IE_				59
-+#define _HT_EXTRA_INFO_IE_			61
-+#define _HT_ADD_INFO_IE_			61 /* _HT_EXTRA_INFO_IE_ */
-+#define _WAPI_IE_				68
-+#define _EID_RRM_EN_CAP_IE_			70
-+
-+
-+/* #define EID_BSSCoexistence			72 */ /* 20/40 BSS Coexistence
-+ * #define EID_BSSIntolerantChlReport	73 */
-+#define _RIC_Descriptor_IE_			75
-+#ifdef CONFIG_IEEE80211W
-+#define _MME_IE_					76 /* 802.11w Management MIC element */
-+#endif /* CONFIG_IEEE80211W */
-+#define _LINK_ID_IE_					101
-+#define _CH_SWITCH_TIMING_		104
-+#define _PTI_BUFFER_STATUS_		106
-+#define _EXT_CAP_IE_				127
-+#define _VENDOR_SPECIFIC_IE_		221
-+
-+#define	_RESERVED47_				47
-+
-+typedef	enum _ELEMENT_ID {
-+	EID_SsId					= 0, /* service set identifier (0:32) */
-+	EID_SupRates				= 1, /* supported rates (1:8) */
-+	EID_FHParms				= 2, /* FH parameter set (5) */
-+	EID_DSParms				= 3, /* DS parameter set (1) */
-+	EID_CFParms				= 4, /* CF parameter set (6) */
-+	EID_Tim						= 5, /* Traffic Information Map (4:254) */
-+	EID_IbssParms				= 6, /* IBSS parameter set (2) */
-+	EID_Country					= 7, /* */
-+
-+	/* Form 7.3.2: Information elements in 802.11E/D13.0, page 46. */
-+	EID_QBSSLoad				= 11,
-+	EID_EDCAParms				= 12,
-+	EID_TSpec					= 13,
-+	EID_TClass					= 14,
-+	EID_Schedule				= 15,
-+	/*  */
-+
-+	EID_Ctext					= 16, /* challenge text*/
-+	EID_POWER_CONSTRAINT		= 32, /* Power Constraint*/
-+
-+	/* vivi for WIFITest, 802.11h AP, 20100427 */
-+	/* 2010/12/26 MH The definition we can declare always!! */
-+	EID_PowerCap				= 33,
-+	EID_TPC				= 35,
-+	EID_SupportedChannels		= 36,
-+	EID_ChlSwitchAnnounce		= 37,
-+
-+	EID_MeasureRequest			= 38, /* Measurement Request */
-+	EID_MeasureReport			= 39, /* Measurement Report */
-+
-+	EID_ERPInfo				= 42,
-+
-+	/* Form 7.3.2: Information elements in 802.11E/D13.0, page 46. */
-+	EID_TSDelay				= 43,
-+	EID_TCLASProc				= 44,
-+	EID_HTCapability			= 45,
-+	EID_QoSCap					= 46,
-+	/*  */
-+
-+	EID_WPA2					= 48,
-+	EID_ExtSupRates			= 50,
-+
-+	EID_FTIE					= 55, /* Defined in 802.11r */
-+	EID_Timeout				= 56, /* Defined in 802.11r */
-+
-+	EID_SupRegulatory			= 59, /* Supported Requlatory Classes 802.11y */
-+	EID_HTInfo					= 61,
-+	EID_SecondaryChnlOffset		= 62,
-+
-+	EID_BSSCoexistence			= 72, /* 20/40 BSS Coexistence */
-+	EID_BSSIntolerantChlReport	= 73,
-+	EID_OBSS					= 74, /* Overlapping BSS Scan Parameters */
-+
-+	EID_LinkIdentifier			= 101, /* Defined in 802.11z */
-+	EID_WakeupSchedule		= 102, /* Defined in 802.11z */
-+	EID_ChnlSwitchTimeing		= 104, /* Defined in 802.11z */
-+	EID_PTIControl				= 105, /* Defined in 802.11z */
-+	EID_PUBufferStatus			= 106, /* Defined in 802.11z */
-+
-+	EID_EXTCapability			= 127, /* Extended Capabilities */
-+	/* From S19:Aironet IE and S21:AP IP address IE in CCX v1.13, p16 and p18. */
-+	EID_Aironet					= 133, /* 0x85: Aironet Element for Cisco CCX */
-+	EID_CiscoIP					= 149, /* 0x95: IP Address IE for Cisco CCX */
-+
-+	EID_CellPwr					= 150, /* 0x96: Cell Power Limit IE. Ref. 0x96. */
-+
-+	EID_CCKM					= 156,
-+
-+	EID_Vendor					= 221, /* 0xDD: Vendor Specific */
-+
-+	EID_WAPI					= 68,
-+	EID_VHTCapability 			= 191, /* Based on 802.11ac D2.0 */
-+	EID_VHTOperation 			= 192, /* Based on 802.11ac D2.0 */
-+	EID_AID						= 197, /* Based on 802.11ac D4.0 */
-+	EID_OpModeNotification		= 199, /* Based on 802.11ac D3.0 */
-+} ELEMENT_ID, *PELEMENT_ID;
-+
-+/* ---------------------------------------------------------------------------
-+					Below is the fixed elements...
-+-----------------------------------------------------------------------------*/
-+#define _AUTH_ALGM_NUM_			2
-+#define _AUTH_SEQ_NUM_			2
-+#define _BEACON_ITERVAL_		2
-+#define _CAPABILITY_			2
-+#define _CURRENT_APADDR_		6
-+#define _LISTEN_INTERVAL_		2
-+#define _RSON_CODE_				2
-+#define _ASOC_ID_				2
-+#define _STATUS_CODE_			2
-+#define _TIMESTAMP_				8
-+
-+#define AUTH_ODD_TO				0
-+#define AUTH_EVEN_TO			1
-+
-+#define WLAN_ETHCONV_ENCAP		1
-+#define WLAN_ETHCONV_RFC1042	2
-+#define WLAN_ETHCONV_8021h	3
-+
-+#define cap_ESS 		BIT(0)
-+#define cap_IBSS		BIT(1)
-+#define cap_CFPollable		BIT(2)
-+#define cap_CFRequest		BIT(3)
-+#define cap_Privacy		BIT(4)
-+#define cap_ShortPremble	BIT(5)
-+#define cap_PBCC		BIT(6)
-+#define cap_ChAgility		BIT(7)
-+#define cap_SpecMgmt		BIT(8)
-+#define cap_QoS 		BIT(9)
-+#define cap_ShortSlot		BIT(10)
-+#define cap_APSD		BIT(11)
-+#define cap_RM			BIT(12)
-+#define cap_DSSSOFDM		BIT(13)
-+#define cap_DelayedBACK 	BIT(14)
-+#define cap_ImmediateBACK	BIT(15)
-+
-+/*-----------------------------------------------------------------------------
-+				Below is the definition for 802.11i / 802.1x
-+------------------------------------------------------------------------------*/
-+#define _IEEE8021X_MGT_			1		/* WPA */
-+#define _IEEE8021X_PSK_			2		/* WPA with pre-shared key */
-+
-+#if 0
-+#define _NO_PRIVACY_			0
-+#define _WEP_40_PRIVACY_		1
-+#define _TKIP_PRIVACY_			2
-+#define _WRAP_PRIVACY_			3
-+#define _CCMP_PRIVACY_			4
-+#define _WEP_104_PRIVACY_		5
-+#define _WEP_WPA_MIXED_PRIVACY_ 6	/*  WEP + WPA */
-+#endif
-+
-+#define _MME_IE_LENGTH_  26
-+
-+/*-----------------------------------------------------------------------------
-+				Below is the definition for WMM
-+------------------------------------------------------------------------------*/
-+#define _WMM_IE_Length_				7  /* for WMM STA */
-+
-+
-+/*-----------------------------------------------------------------------------
-+				Below is the definition for 802.11n
-+------------------------------------------------------------------------------*/
-+
-+/* #ifdef CONFIG_80211N_HT */
-+
-+#define set_order_bit(pbuf)	\
-+		do	{	\
-+			*(unsigned short *)(pbuf) |= cpu_to_le16(_ORDER_); \
-+		} while (0)
-+
-+
-+
-+#define GetOrderBit(pbuf)	(((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0)
-+
-+#define ACT_CAT_VENDOR				0x7F/* 127 */
-+
-+/**
-+ * struct rtw_ieee80211_bar - HT Block Ack Request
-+ *
-+ * This structure refers to "HT BlockAckReq" as
-+ * described in 802.11n draft section 7.2.1.7.1
-+ */
-+#if defined(PLATFORM_LINUX)
-+struct rtw_ieee80211_bar {
-+	unsigned short frame_control;
-+	unsigned short duration;
-+	unsigned char ra[6];
-+	unsigned char ta[6];
-+	unsigned short control;
-+	unsigned short start_seq_num;
-+} __attribute__((packed));
-+#endif
-+
-+/* 802.11 BAR control masks */
-+#define IEEE80211_BAR_CTRL_ACK_POLICY_NORMAL     0x0000
-+#define IEEE80211_BAR_CTRL_CBMTID_COMPRESSED_BA  0x0004
-+
-+
-+#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD)
-+
-+
-+
-+/**
-+* struct rtw_ieee80211_ht_cap - HT capabilities
-+*
-+* This structure refers to "HT capabilities element" as
-+* described in 802.11n draft section 7.3.2.52
-+*/
-+
-+struct rtw_ieee80211_ht_cap {
-+	unsigned short	cap_info;
-+	unsigned char	ampdu_params_info;
-+	unsigned char	supp_mcs_set[16];
-+	unsigned short	extended_ht_cap_info;
-+	unsigned int		tx_BF_cap_info;
-+	unsigned char	       antenna_selection_info;
-+} __attribute__((packed));
-+
-+/**
-+ * struct rtw_ieee80211_ht_cap - HT additional information
-+ *
-+ * This structure refers to "HT information element" as
-+ * described in 802.11n draft section 7.3.2.53
-+ */
-+#ifndef CONFIG_IEEE80211_HT_ADDT_INFO
-+struct ieee80211_ht_addt_info {
-+	unsigned char	control_chan;
-+	unsigned char		ht_param;
-+	unsigned short	operation_mode;
-+	unsigned short	stbc_param;
-+	unsigned char		basic_set[16];
-+} __attribute__((packed));
-+#endif
-+
-+struct HT_caps_element {
-+	union {
-+		struct {
-+			unsigned short	HT_caps_info;
-+			unsigned char	AMPDU_para;
-+			unsigned char	MCS_rate[16];
-+			unsigned short	HT_ext_caps;
-+			unsigned int	Beamforming_caps;
-+			unsigned char	ASEL_caps;
-+		} HT_cap_element;
-+		unsigned char HT_cap[26];
-+	} u;
-+} __attribute__((packed));
-+
-+struct HT_info_element {
-+	unsigned char	primary_channel;
-+	unsigned char	infos[5];
-+	unsigned char	MCS_rate[16];
-+}  __attribute__((packed));
-+
-+struct AC_param {
-+	unsigned char		ACI_AIFSN;
-+	unsigned char		CW;
-+	unsigned short	TXOP_limit;
-+}  __attribute__((packed));
-+
-+struct WMM_para_element {
-+	unsigned char		QoS_info;
-+	unsigned char		reserved;
-+	struct AC_param	ac_param[4];
-+}  __attribute__((packed));
-+
-+struct ADDBA_request {
-+	unsigned char		dialog_token;
-+	unsigned short	BA_para_set;
-+	unsigned short	BA_timeout_value;
-+	unsigned short	BA_starting_seqctrl;
-+}  __attribute__((packed));
-+
-+
-+
-+#endif
-+
-+
-+typedef enum _HT_CAP_AMPDU_FACTOR {
-+	MAX_AMPDU_FACTOR_8K		= 0,
-+	MAX_AMPDU_FACTOR_16K	= 1,
-+	MAX_AMPDU_FACTOR_32K	= 2,
-+	MAX_AMPDU_FACTOR_64K	= 3,
-+} HT_CAP_AMPDU_FACTOR;
-+
-+typedef enum _VHT_CAP_AMPDU_FACTOR {
-+	MAX_AMPDU_FACTOR_128K = 4,
-+	MAX_AMPDU_FACTOR_256K = 5,
-+	MAX_AMPDU_FACTOR_512K = 6,
-+	MAX_AMPDU_FACTOR_1M = 7,
-+} VHT_CAP_AMPDU_FACTOR;
-+
-+
-+typedef enum _HT_CAP_AMPDU_DENSITY {
-+	AMPDU_DENSITY_VALUE_0 = 0 , /* For no restriction */
-+	AMPDU_DENSITY_VALUE_1 = 1 , /* For 1/4 us */
-+	AMPDU_DENSITY_VALUE_2 = 2 , /* For 1/2 us */
-+	AMPDU_DENSITY_VALUE_3 = 3 , /* For 1 us */
-+	AMPDU_DENSITY_VALUE_4 = 4 , /* For 2 us */
-+	AMPDU_DENSITY_VALUE_5 = 5 , /* For 4 us */
-+	AMPDU_DENSITY_VALUE_6 = 6 , /* For 8 us */
-+	AMPDU_DENSITY_VALUE_7 = 7 , /* For 16 us */
-+} HT_CAP_AMPDU_DENSITY;
-+
-+/* 802.11n HT capabilities masks */
-+#define IEEE80211_HT_CAP_LDPC_CODING		0x0001
-+#define IEEE80211_HT_CAP_SUP_WIDTH		0x0002
-+#define IEEE80211_HT_CAP_SM_PS			0x000C
-+#define IEEE80211_HT_CAP_GRN_FLD		0x0010
-+#define IEEE80211_HT_CAP_SGI_20			0x0020
-+#define IEEE80211_HT_CAP_SGI_40			0x0040
-+#define IEEE80211_HT_CAP_TX_STBC			0x0080
-+#define IEEE80211_HT_CAP_RX_STBC_1R		0x0100
-+#define IEEE80211_HT_CAP_RX_STBC_2R		0x0200
-+#define IEEE80211_HT_CAP_RX_STBC_3R		0x0300
-+#define IEEE80211_HT_CAP_DELAY_BA		0x0400
-+#define IEEE80211_HT_CAP_MAX_AMSDU		0x0800
-+#define IEEE80211_HT_CAP_DSSSCCK40		0x1000
-+#define RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT	((u16) BIT(14))
-+/* 802.11n HT capability AMPDU settings */
-+#define IEEE80211_HT_CAP_AMPDU_FACTOR		0x03
-+#define IEEE80211_HT_CAP_AMPDU_DENSITY		0x1C
-+/* 802.11n HT capability MSC set */
-+#define IEEE80211_SUPP_MCS_SET_UEQM		4
-+#define IEEE80211_HT_CAP_MAX_STREAMS		4
-+#define IEEE80211_SUPP_MCS_SET_LEN		10
-+/* maximum streams the spec allows */
-+#define IEEE80211_HT_CAP_MCS_TX_DEFINED		0x01
-+#define IEEE80211_HT_CAP_MCS_TX_RX_DIFF		0x02
-+#define IEEE80211_HT_CAP_MCS_TX_STREAMS		0x0C
-+#define IEEE80211_HT_CAP_MCS_TX_UEQM		0x10
-+/* 802.11n HT capability TXBF capability */
-+#define IEEE80211_HT_CAP_TXBF_RX_NDP		0x00000008
-+#define IEEE80211_HT_CAP_TXBF_TX_NDP		0x00000010
-+#define IEEE80211_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP	0x00000400
-+
-+/* 802.11n HT IE masks */
-+#define IEEE80211_HT_IE_CHA_SEC_OFFSET		0x03
-+#define IEEE80211_HT_IE_CHA_SEC_NONE		0x00
-+#define IEEE80211_HT_IE_CHA_SEC_ABOVE		0x01
-+#define IEEE80211_HT_IE_CHA_SEC_BELOW		0x03
-+#define IEEE80211_HT_IE_CHA_WIDTH		0x04
-+#define IEEE80211_HT_IE_HT_PROTECTION		0x0003
-+#define IEEE80211_HT_IE_NON_GF_STA_PRSNT	0x0004
-+#define IEEE80211_HT_IE_NON_HT_STA_PRSNT	0x0010
-+
-+/* block-ack parameters */
-+#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002
-+#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C
-+#define RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFC0
-+#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000
-+#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800
-+
-+/*
-+ * A-PMDU buffer sizes
-+ * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2)
-+ */
-+#define IEEE80211_MIN_AMPDU_BUF 0x8
-+#define IEEE80211_MAX_AMPDU_BUF_HT 0x40
-+
-+
-+/* Spatial Multiplexing Power Save Modes */
-+#define WLAN_HT_CAP_SM_PS_STATIC		0
-+#define WLAN_HT_CAP_SM_PS_DYNAMIC	1
-+#define WLAN_HT_CAP_SM_PS_INVALID	2
-+#define WLAN_HT_CAP_SM_PS_DISABLED	3
-+
-+
-+#define OP_MODE_PURE                    0
-+#define OP_MODE_MAY_BE_LEGACY_STAS      1
-+#define OP_MODE_20MHZ_HT_STA_ASSOCED    2
-+#define OP_MODE_MIXED                   3
-+
-+#define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK	((u8) BIT(0) | BIT(1))
-+#define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE		((u8) BIT(0))
-+#define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW		((u8) BIT(0) | BIT(1))
-+#define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH		((u8) BIT(2))
-+#define HT_INFO_HT_PARAM_RIFS_MODE			((u8) BIT(3))
-+#define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY		((u8) BIT(4))
-+#define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY	((u8) BIT(5))
-+
-+#define HT_INFO_OPERATION_MODE_OP_MODE_MASK	\
-+	((u16) (0x0001 | 0x0002))
-+#define HT_INFO_OPERATION_MODE_OP_MODE_OFFSET		0
-+#define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT	((u8) BIT(2))
-+#define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT	((u8) BIT(3))
-+#define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT	((u8) BIT(4))
-+
-+#define HT_INFO_STBC_PARAM_DUAL_BEACON			((u16) BIT(6))
-+#define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT		((u16) BIT(7))
-+#define HT_INFO_STBC_PARAM_SECONDARY_BCN		((u16) BIT(8))
-+#define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED	((u16) BIT(9))
-+#define HT_INFO_STBC_PARAM_PCO_ACTIVE			((u16) BIT(10))
-+#define HT_INFO_STBC_PARAM_PCO_PHASE			((u16) BIT(11))
-+
-+
-+
-+/* #endif */
-+
-+/*	===============WPS Section=============== */
-+/*	For WPSv1.0 */
-+#define WPSOUI							0x0050f204
-+/*	WPS attribute ID */
-+#define WPS_ATTR_VER1					0x104A
-+#define WPS_ATTR_SIMPLE_CONF_STATE	0x1044
-+#define WPS_ATTR_RESP_TYPE			0x103B
-+#define WPS_ATTR_UUID_E				0x1047
-+#define WPS_ATTR_MANUFACTURER		0x1021
-+#define WPS_ATTR_MODEL_NAME			0x1023
-+#define WPS_ATTR_MODEL_NUMBER		0x1024
-+#define WPS_ATTR_SERIAL_NUMBER		0x1042
-+#define WPS_ATTR_PRIMARY_DEV_TYPE	0x1054
-+#define WPS_ATTR_SEC_DEV_TYPE_LIST	0x1055
-+#define WPS_ATTR_DEVICE_NAME			0x1011
-+#define WPS_ATTR_CONF_METHOD			0x1008
-+#define WPS_ATTR_RF_BANDS				0x103C
-+#define WPS_ATTR_DEVICE_PWID			0x1012
-+#define WPS_ATTR_REQUEST_TYPE			0x103A
-+#define WPS_ATTR_ASSOCIATION_STATE	0x1002
-+#define WPS_ATTR_CONFIG_ERROR			0x1009
-+#define WPS_ATTR_VENDOR_EXT			0x1049
-+#define WPS_ATTR_SELECTED_REGISTRAR	0x1041
-+
-+/*	Value of WPS attribute "WPS_ATTR_DEVICE_NAME */
-+#define WPS_MAX_DEVICE_NAME_LEN		32
-+
-+/*	Value of WPS Request Type Attribute */
-+#define WPS_REQ_TYPE_ENROLLEE_INFO_ONLY			0x00
-+#define WPS_REQ_TYPE_ENROLLEE_OPEN_8021X		0x01
-+#define WPS_REQ_TYPE_REGISTRAR					0x02
-+#define WPS_REQ_TYPE_WLAN_MANAGER_REGISTRAR	0x03
-+
-+/*	Value of WPS Response Type Attribute */
-+#define WPS_RESPONSE_TYPE_INFO_ONLY	0x00
-+#define WPS_RESPONSE_TYPE_8021X		0x01
-+#define WPS_RESPONSE_TYPE_REGISTRAR	0x02
-+#define WPS_RESPONSE_TYPE_AP			0x03
-+
-+/*	Value of WPS WiFi Simple Configuration State Attribute */
-+#define WPS_WSC_STATE_NOT_CONFIG	0x01
-+#define WPS_WSC_STATE_CONFIG			0x02
-+
-+/*	Value of WPS Version Attribute */
-+#define WPS_VERSION_1					0x10
-+
-+/*	Value of WPS Configuration Method Attribute */
-+#define WPS_CONFIG_METHOD_FLASH		0x0001
-+#define WPS_CONFIG_METHOD_ETHERNET	0x0002
-+#define WPS_CONFIG_METHOD_LABEL		0x0004
-+#define WPS_CONFIG_METHOD_DISPLAY	0x0008
-+#define WPS_CONFIG_METHOD_E_NFC		0x0010
-+#define WPS_CONFIG_METHOD_I_NFC		0x0020
-+#define WPS_CONFIG_METHOD_NFC		0x0040
-+#define WPS_CONFIG_METHOD_PBC		0x0080
-+#define WPS_CONFIG_METHOD_KEYPAD	0x0100
-+#define WPS_CONFIG_METHOD_VPBC		0x0280
-+#define WPS_CONFIG_METHOD_PPBC		0x0480
-+#define WPS_CONFIG_METHOD_VDISPLAY	0x2008
-+#define WPS_CONFIG_METHOD_PDISPLAY	0x4008
-+
-+/*	Value of Category ID of WPS Primary Device Type Attribute */
-+#define WPS_PDT_CID_DISPLAYS			0x0007
-+#define WPS_PDT_CID_MULIT_MEDIA		0x0008
-+#define WPS_PDT_CID_RTK_WIDI			WPS_PDT_CID_MULIT_MEDIA
-+
-+/*	Value of Sub Category ID of WPS Primary Device Type Attribute */
-+#define WPS_PDT_SCID_MEDIA_SERVER	0x0005
-+#define WPS_PDT_SCID_RTK_DMP			WPS_PDT_SCID_MEDIA_SERVER
-+
-+/*	Value of Device Password ID */
-+#define WPS_DPID_PIN					0x0000
-+#define WPS_DPID_USER_SPEC			0x0001
-+#define WPS_DPID_MACHINE_SPEC			0x0002
-+#define WPS_DPID_REKEY					0x0003
-+#define WPS_DPID_PBC					0x0004
-+#define WPS_DPID_REGISTRAR_SPEC		0x0005
-+
-+/*	Value of WPS RF Bands Attribute */
-+#define WPS_RF_BANDS_2_4_GHZ		0x01
-+#define WPS_RF_BANDS_5_GHZ		0x02
-+
-+/*	Value of WPS Association State Attribute */
-+#define WPS_ASSOC_STATE_NOT_ASSOCIATED			0x00
-+#define WPS_ASSOC_STATE_CONNECTION_SUCCESS		0x01
-+#define WPS_ASSOC_STATE_CONFIGURATION_FAILURE	0x02
-+#define WPS_ASSOC_STATE_ASSOCIATION_FAILURE		0x03
-+#define WPS_ASSOC_STATE_IP_FAILURE				0x04
-+
-+/*	=====================P2P Section===================== */
-+/*	For P2P */
-+#define	P2POUI							0x506F9A09
-+
-+/*	P2P Attribute ID */
-+#define	P2P_ATTR_STATUS					0x00
-+#define	P2P_ATTR_MINOR_REASON_CODE		0x01
-+#define	P2P_ATTR_CAPABILITY				0x02
-+#define	P2P_ATTR_DEVICE_ID				0x03
-+#define	P2P_ATTR_GO_INTENT				0x04
-+#define	P2P_ATTR_CONF_TIMEOUT			0x05
-+#define	P2P_ATTR_LISTEN_CH				0x06
-+#define	P2P_ATTR_GROUP_BSSID				0x07
-+#define	P2P_ATTR_EX_LISTEN_TIMING		0x08
-+#define	P2P_ATTR_INTENDED_IF_ADDR		0x09
-+#define	P2P_ATTR_MANAGEABILITY			0x0A
-+#define	P2P_ATTR_CH_LIST					0x0B
-+#define	P2P_ATTR_NOA						0x0C
-+#define	P2P_ATTR_DEVICE_INFO				0x0D
-+#define	P2P_ATTR_GROUP_INFO				0x0E
-+#define	P2P_ATTR_GROUP_ID					0x0F
-+#define	P2P_ATTR_INTERFACE				0x10
-+#define	P2P_ATTR_OPERATING_CH			0x11
-+#define	P2P_ATTR_INVITATION_FLAGS		0x12
-+
-+/*	Value of Status Attribute */
-+#define	P2P_STATUS_SUCCESS						0x00
-+#define	P2P_STATUS_FAIL_INFO_UNAVAILABLE		0x01
-+#define	P2P_STATUS_FAIL_INCOMPATIBLE_PARAM		0x02
-+#define	P2P_STATUS_FAIL_LIMIT_REACHED			0x03
-+#define	P2P_STATUS_FAIL_INVALID_PARAM			0x04
-+#define	P2P_STATUS_FAIL_REQUEST_UNABLE			0x05
-+#define	P2P_STATUS_FAIL_PREVOUS_PROTO_ERR		0x06
-+#define	P2P_STATUS_FAIL_NO_COMMON_CH			0x07
-+#define	P2P_STATUS_FAIL_UNKNOWN_P2PGROUP		0x08
-+#define	P2P_STATUS_FAIL_BOTH_GOINTENT_15		0x09
-+#define	P2P_STATUS_FAIL_INCOMPATIBLE_PROVSION	0x0A
-+#define	P2P_STATUS_FAIL_USER_REJECT				0x0B
-+
-+/*	Value of Inviation Flags Attribute */
-+#define	P2P_INVITATION_FLAGS_PERSISTENT			BIT(0)
-+
-+#define	DMP_P2P_DEVCAP_SUPPORT	(P2P_DEVCAP_SERVICE_DISCOVERY | \
-+				 P2P_DEVCAP_CLIENT_DISCOVERABILITY | \
-+				 P2P_DEVCAP_CONCURRENT_OPERATION | \
-+				 P2P_DEVCAP_INVITATION_PROC)
-+
-+#define	DMP_P2P_GRPCAP_SUPPORT	(P2P_GRPCAP_INTRABSS)
-+
-+/*	Value of Device Capability Bitmap */
-+#define	P2P_DEVCAP_SERVICE_DISCOVERY		BIT(0)
-+#define	P2P_DEVCAP_CLIENT_DISCOVERABILITY	BIT(1)
-+#define	P2P_DEVCAP_CONCURRENT_OPERATION	BIT(2)
-+#define	P2P_DEVCAP_INFRA_MANAGED			BIT(3)
-+#define	P2P_DEVCAP_DEVICE_LIMIT				BIT(4)
-+#define	P2P_DEVCAP_INVITATION_PROC			BIT(5)
-+
-+/*	Value of Group Capability Bitmap */
-+#define	P2P_GRPCAP_GO							BIT(0)
-+#define	P2P_GRPCAP_PERSISTENT_GROUP			BIT(1)
-+#define	P2P_GRPCAP_GROUP_LIMIT				BIT(2)
-+#define	P2P_GRPCAP_INTRABSS					BIT(3)
-+#define	P2P_GRPCAP_CROSS_CONN				BIT(4)
-+#define	P2P_GRPCAP_PERSISTENT_RECONN		BIT(5)
-+#define	P2P_GRPCAP_GROUP_FORMATION			BIT(6)
-+
-+/*	P2P Public Action Frame ( Management Frame ) */
-+#define	P2P_PUB_ACTION_ACTION				0x09
-+
-+/*	P2P Public Action Frame Type */
-+#define	P2P_GO_NEGO_REQ						0
-+#define	P2P_GO_NEGO_RESP						1
-+#define	P2P_GO_NEGO_CONF						2
-+#define	P2P_INVIT_REQ							3
-+#define	P2P_INVIT_RESP							4
-+#define	P2P_DEVDISC_REQ						5
-+#define	P2P_DEVDISC_RESP						6
-+#define	P2P_PROVISION_DISC_REQ				7
-+#define	P2P_PROVISION_DISC_RESP				8
-+
-+/*	P2P Action Frame Type */
-+#define	P2P_NOTICE_OF_ABSENCE	0
-+#define	P2P_PRESENCE_REQUEST		1
-+#define	P2P_PRESENCE_RESPONSE	2
-+#define	P2P_GO_DISC_REQUEST		3
-+
-+
-+#define	P2P_MAX_PERSISTENT_GROUP_NUM		10
-+
-+#define	P2P_PROVISIONING_SCAN_CNT			3
-+
-+#define	P2P_WILDCARD_SSID_LEN				7
-+
-+#define	P2P_FINDPHASE_EX_NONE				0	/* default value, used when: (1)p2p disabed or (2)p2p enabled but only do 1 scan phase */
-+#define	P2P_FINDPHASE_EX_FULL				1	/* used when p2p enabled and want to do 1 scan phase and P2P_FINDPHASE_EX_MAX-1 find phase */
-+#define	P2P_FINDPHASE_EX_SOCIAL_FIRST		(P2P_FINDPHASE_EX_FULL+1)
-+#define	P2P_FINDPHASE_EX_MAX					4
-+#define	P2P_FINDPHASE_EX_SOCIAL_LAST		P2P_FINDPHASE_EX_MAX
-+
-+#define	P2P_PROVISION_TIMEOUT				5000	/*	5 seconds timeout for sending the provision discovery request */
-+#define	P2P_CONCURRENT_PROVISION_TIMEOUT	3000	/*	3 seconds timeout for sending the provision discovery request under concurrent mode */
-+#define	P2P_GO_NEGO_TIMEOUT					5000	/*	5 seconds timeout for receiving the group negotation response */
-+#define	P2P_CONCURRENT_GO_NEGO_TIMEOUT		3000	/*	3 seconds timeout for sending the negotiation request under concurrent mode */
-+#define	P2P_TX_PRESCAN_TIMEOUT				100		/*	100ms */
-+#define	P2P_INVITE_TIMEOUT					5000	/*	5 seconds timeout for sending the invitation request */
-+#define	P2P_CONCURRENT_INVITE_TIMEOUT		3000	/*	3 seconds timeout for sending the invitation request under concurrent mode */
-+#define	P2P_RESET_SCAN_CH						25000	/*	25 seconds timeout to reset the scan channel (based on channel plan) */
-+#define	P2P_MAX_INTENT						15
-+
-+#define	P2P_MAX_NOA_NUM						2
-+
-+/*	WPS Configuration Method */
-+#define	WPS_CM_NONE							0x0000
-+#define	WPS_CM_LABEL							0x0004
-+#define	WPS_CM_DISPLYA						0x0008
-+#define	WPS_CM_EXTERNAL_NFC_TOKEN			0x0010
-+#define	WPS_CM_INTEGRATED_NFC_TOKEN		0x0020
-+#define	WPS_CM_NFC_INTERFACE					0x0040
-+#define	WPS_CM_PUSH_BUTTON					0x0080
-+#define	WPS_CM_KEYPAD						0x0100
-+#define	WPS_CM_SW_PUHS_BUTTON				0x0280
-+#define	WPS_CM_HW_PUHS_BUTTON				0x0480
-+#define	WPS_CM_SW_DISPLAY_PIN				0x2008
-+#define	WPS_CM_LCD_DISPLAY_PIN				0x4008
-+
-+enum P2P_ROLE {
-+	P2P_ROLE_DISABLE = 0,
-+	P2P_ROLE_DEVICE = 1,
-+	P2P_ROLE_CLIENT = 2,
-+	P2P_ROLE_GO = 3
-+};
-+
-+enum P2P_STATE {
-+	P2P_STATE_NONE = 0,							/*	P2P disable */
-+	P2P_STATE_IDLE = 1,								/*	P2P had enabled and do nothing ,  buddy adapters is linked */
-+	P2P_STATE_LISTEN = 2,							/*	In pure listen state */
-+	P2P_STATE_SCAN = 3,							/*	In scan phase */
-+	P2P_STATE_FIND_PHASE_LISTEN = 4,				/*	In the listen state of find phase */
-+	P2P_STATE_FIND_PHASE_SEARCH = 5,				/*	In the search state of find phase */
-+	P2P_STATE_TX_PROVISION_DIS_REQ = 6,			/*	In P2P provisioning discovery */
-+	P2P_STATE_RX_PROVISION_DIS_RSP = 7,
-+	P2P_STATE_RX_PROVISION_DIS_REQ = 8,
-+	P2P_STATE_GONEGO_ING = 9,						/*	Doing the group owner negoitation handshake */
-+	P2P_STATE_GONEGO_OK = 10,						/*	finish the group negoitation handshake with success */
-+	P2P_STATE_GONEGO_FAIL = 11,					/*	finish the group negoitation handshake with failure */
-+	P2P_STATE_RECV_INVITE_REQ_MATCH = 12,		/*	receiving the P2P Inviation request and match with the profile. */
-+	P2P_STATE_PROVISIONING_ING = 13,				/*	Doing the P2P WPS */
-+	P2P_STATE_PROVISIONING_DONE = 14,			/*	Finish the P2P WPS */
-+	P2P_STATE_TX_INVITE_REQ = 15,					/*	Transmit the P2P Invitation request */
-+	P2P_STATE_RX_INVITE_RESP_OK = 16,				/*	Receiving the P2P Invitation response */
-+	P2P_STATE_RECV_INVITE_REQ_DISMATCH = 17,	/*	receiving the P2P Inviation request and dismatch with the profile. */
-+	P2P_STATE_RECV_INVITE_REQ_GO = 18,			/*	receiving the P2P Inviation request and this wifi is GO. */
-+	P2P_STATE_RECV_INVITE_REQ_JOIN = 19,			/*	receiving the P2P Inviation request to join an existing P2P Group. */
-+	P2P_STATE_RX_INVITE_RESP_FAIL = 20,			/*	recveing the P2P Inviation response with failure */
-+	P2P_STATE_RX_INFOR_NOREADY = 21,			/* receiving p2p negoitation response with information is not available */
-+	P2P_STATE_TX_INFOR_NOREADY = 22,			/* sending p2p negoitation response with information is not available */
-+};
-+
-+enum P2P_WPSINFO {
-+	P2P_NO_WPSINFO						= 0,
-+	P2P_GOT_WPSINFO_PEER_DISPLAY_PIN	= 1,
-+	P2P_GOT_WPSINFO_SELF_DISPLAY_PIN	= 2,
-+	P2P_GOT_WPSINFO_PBC					= 3,
-+};
-+
-+#define	P2P_PRIVATE_IOCTL_SET_LEN		64
-+
-+enum P2P_PROTO_WK_ID {
-+	P2P_FIND_PHASE_WK = 0,
-+	P2P_RESTORE_STATE_WK = 1,
-+	P2P_PRE_TX_PROVDISC_PROCESS_WK = 2,
-+	P2P_PRE_TX_NEGOREQ_PROCESS_WK = 3,
-+	P2P_PRE_TX_INVITEREQ_PROCESS_WK = 4,
-+};
-+
-+#ifdef CONFIG_P2P_PS
-+enum P2P_PS_STATE {
-+	P2P_PS_DISABLE = 0,
-+	P2P_PS_ENABLE = 1,
-+	P2P_PS_SCAN = 2,
-+	P2P_PS_SCAN_DONE = 3,
-+	P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
-+};
-+
-+enum P2P_PS_MODE {
-+	P2P_PS_NONE = 0,
-+	P2P_PS_CTWINDOW = 1,
-+	P2P_PS_NOA	 = 2,
-+	P2P_PS_MIX = 3, /* CTWindow and NoA */
-+};
-+#endif /* CONFIG_P2P_PS */
-+
-+/*	=====================WFD Section=====================
-+ *	For Wi-Fi Display */
-+#define	WFD_ATTR_DEVICE_INFO			0x00
-+#define	WFD_ATTR_ASSOC_BSSID			0x01
-+#define	WFD_ATTR_COUPLED_SINK_INFO	0x06
-+#define	WFD_ATTR_LOCAL_IP_ADDR		0x08
-+#define	WFD_ATTR_SESSION_INFO		0x09
-+#define	WFD_ATTR_ALTER_MAC			0x0a
-+
-+/*	For WFD Device Information Attribute */
-+#define	WFD_DEVINFO_SOURCE					0x0000
-+#define	WFD_DEVINFO_PSINK					0x0001
-+#define	WFD_DEVINFO_SSINK					0x0002
-+#define	WFD_DEVINFO_DUAL					0x0003
-+
-+#define	WFD_DEVINFO_SESSION_AVAIL			0x0010
-+#define	WFD_DEVINFO_WSD						0x0040
-+#define	WFD_DEVINFO_PC_TDLS					0x0080
-+#define	WFD_DEVINFO_HDCP_SUPPORT			0x0100
-+
-+#define IP_MCAST_MAC(mac)		((mac[0] == 0x01) && (mac[1] == 0x00) && (mac[2] == 0x5e))
-+#define ICMPV6_MCAST_MAC(mac)	((mac[0] == 0x33) && (mac[1] == 0x33) && (mac[2] != 0xff))
-+
-+enum RTW_ROCH_WK_ID{
-+	ROCH_RO_CH_WK,
-+	ROCH_CANCEL_RO_CH_WK,
-+	ROCH_AP_ROCH_CH_SWITCH_PROCESS_WK,
-+};
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+/* Regulatroy Domain */
-+struct regd_pair_mapping {
-+	u16 reg_dmnenum;
-+	u16 reg_5ghz_ctl;
-+	u16 reg_2ghz_ctl;
-+};
-+
-+struct rtw_regulatory {
-+	char alpha2[2];
-+	u16 country_code;
-+	u16 max_power_level;
-+	u32 tp_scale;
-+	u16 current_rd;
-+	u16 current_rd_ext;
-+	int16_t power_limit;
-+	struct regd_pair_mapping *regpair;
-+};
-+#endif
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+#ifndef IW_AUTH_WAPI_VERSION_1
-+#define IW_AUTH_WAPI_VERSION_1		0x00000008
-+#endif
-+#ifndef IW_AUTH_KEY_MGMT_WAPI_PSK
-+#define IW_AUTH_KEY_MGMT_WAPI_PSK	0x04
-+#endif
-+#ifndef IW_AUTH_WAPI_ENABLED
-+#define IW_AUTH_WAPI_ENABLED		0x20
-+#endif
-+#ifndef IW_ENCODE_ALG_SM4
-+#define IW_ENCODE_ALG_SM4			0x20
-+#endif
-+#endif
-+
-+#endif /* _WIFI_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/wlan_bssdef.h b/drivers/staging/rtl8723cs/include/wlan_bssdef.h
-new file mode 100644
-index 000000000000..c8f3229b9a30
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/wlan_bssdef.h
-@@ -0,0 +1,327 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __WLAN_BSSDEF_H__
-+#define __WLAN_BSSDEF_H__
-+
-+
-+#define MAX_IE_SZ	768
-+
-+
-+#ifdef PLATFORM_LINUX
-+
-+#define NDIS_802_11_LENGTH_SSID         32
-+#define NDIS_802_11_LENGTH_RATES        8
-+#define NDIS_802_11_LENGTH_RATES_EX     16
-+
-+typedef unsigned char   NDIS_802_11_MAC_ADDRESS[ETH_ALEN];
-+typedef long    		NDIS_802_11_RSSI;           /* in dBm */
-+typedef unsigned char   NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES];        /* Set of 8 data rates */
-+typedef unsigned char   NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX];  /* Set of 16 data rates */
-+
-+typedef struct _NDIS_802_11_SSID {
-+	u32  SsidLength;
-+	u8  Ssid[32];
-+} NDIS_802_11_SSID, *PNDIS_802_11_SSID;
-+
-+/*
-+	FW will only save the channel number in DSConfig.
-+	ODI Handler will convert the channel number to freq. number.
-+*/
-+typedef struct _NDIS_802_11_CONFIGURATION {
-+	u32           Length;             /* Length of structure */
-+	u32           BeaconPeriod;       /* units are Kusec */
-+	u32           ATIMWindow;         /* units are Kusec */
-+	u32           DSConfig;           /* channel number */
-+} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION;
-+
-+typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE {
-+	Ndis802_11IBSS,
-+	Ndis802_11Infrastructure,
-+	Ndis802_11AutoUnknown,
-+	Ndis802_11InfrastructureMax,     /* Not a real value, defined as upper bound */
-+	Ndis802_11APMode,
-+	Ndis802_11Monitor,
-+	Ndis802_11_mesh,
-+} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
-+
-+typedef struct _NDIS_802_11_FIXED_IEs {
-+	u8  Timestamp[8];
-+	u16  BeaconInterval;
-+	u16  Capabilities;
-+} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs;
-+
-+typedef struct _NDIS_802_11_VARIABLE_IEs {
-+	u8  ElementID;
-+	u8  Length;
-+	u8  data[1];
-+} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs;
-+
-+typedef enum _NDIS_802_11_AUTHENTICATION_MODE {
-+	Ndis802_11AuthModeOpen,
-+	Ndis802_11AuthModeShared,
-+	Ndis802_11AuthModeAutoSwitch,
-+	Ndis802_11AuthModeWPA,
-+	Ndis802_11AuthModeWPAPSK,
-+	Ndis802_11AuthModeWPANone,
-+	Ndis802_11AuthModeWAPI,
-+	Ndis802_11AuthModeMax               /* Not a real mode, defined as upper bound */
-+} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;
-+
-+typedef enum _NDIS_802_11_WEP_STATUS {
-+	Ndis802_11WEPEnabled,
-+	Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
-+	Ndis802_11WEPDisabled,
-+	Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled,
-+	Ndis802_11WEPKeyAbsent,
-+	Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,
-+	Ndis802_11WEPNotSupported,
-+	Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,
-+	Ndis802_11Encryption2Enabled,
-+	Ndis802_11Encryption2KeyAbsent,
-+	Ndis802_11Encryption3Enabled,
-+	Ndis802_11Encryption3KeyAbsent,
-+	Ndis802_11_EncrypteionWAPI
-+} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,
-+NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;
-+
-+typedef struct _NDIS_802_11_WEP {
-+	u32     Length;        /* Length of this structure */
-+	u32     KeyIndex;      /* 0 is the per-client key, 1-N are the global keys */
-+	u32     KeyLength;     /* length of key in bytes */
-+	u8     KeyMaterial[16];/* variable length depending on above field */
-+} NDIS_802_11_WEP, *PNDIS_802_11_WEP;
-+
-+#endif /* end of #ifdef PLATFORM_LINUX */
-+
-+#ifdef PLATFORM_FREEBSD
-+
-+#define NDIS_802_11_LENGTH_SSID         32
-+#define NDIS_802_11_LENGTH_RATES        8
-+#define NDIS_802_11_LENGTH_RATES_EX     16
-+
-+typedef unsigned char   NDIS_802_11_MAC_ADDRESS[ETH_ALEN];
-+typedef long    		NDIS_802_11_RSSI;           /* in dBm */
-+typedef unsigned char   NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES];        /* Set of 8 data rates */
-+typedef unsigned char   NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX];  /* Set of 16 data rates */
-+
-+
-+typedef struct _NDIS_802_11_SSID {
-+	u32  SsidLength;
-+	u8  Ssid[32];
-+} NDIS_802_11_SSID, *PNDIS_802_11_SSID;
-+
-+/*
-+	FW will only save the channel number in DSConfig.
-+	ODI Handler will convert the channel number to freq. number.
-+*/
-+typedef struct _NDIS_802_11_CONFIGURATION {
-+	u32           Length;             /* Length of structure */
-+	u32           BeaconPeriod;       /* units are Kusec */
-+	u32           ATIMWindow;         /* units are Kusec */
-+	u32           DSConfig;           /* channel number */
-+} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION;
-+
-+typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE {
-+	Ndis802_11IBSS,
-+	Ndis802_11Infrastructure,
-+	Ndis802_11AutoUnknown,
-+	Ndis802_11InfrastructureMax,     /* Not a real value, defined as upper bound */
-+	Ndis802_11APMode
-+} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
-+
-+typedef struct _NDIS_802_11_FIXED_IEs {
-+	u8  Timestamp[8];
-+	u16  BeaconInterval;
-+	u16  Capabilities;
-+} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs;
-+
-+typedef struct _NDIS_802_11_VARIABLE_IEs {
-+	u8  ElementID;
-+	u8  Length;
-+	u8  data[1];
-+} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs;
-+
-+typedef enum _NDIS_802_11_AUTHENTICATION_MODE {
-+	Ndis802_11AuthModeOpen,
-+	Ndis802_11AuthModeShared,
-+	Ndis802_11AuthModeAutoSwitch,
-+	Ndis802_11AuthModeWPA,
-+	Ndis802_11AuthModeWPAPSK,
-+	Ndis802_11AuthModeWPANone,
-+	Ndis802_11AuthModeMax               /* Not a real mode, defined as upper bound */
-+} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;
-+
-+typedef enum _NDIS_802_11_WEP_STATUS {
-+	Ndis802_11WEPEnabled,
-+	Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
-+	Ndis802_11WEPDisabled,
-+	Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled,
-+	Ndis802_11WEPKeyAbsent,
-+	Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,
-+	Ndis802_11WEPNotSupported,
-+	Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,
-+	Ndis802_11Encryption2Enabled,
-+	Ndis802_11Encryption2KeyAbsent,
-+	Ndis802_11Encryption3Enabled,
-+	Ndis802_11Encryption3KeyAbsent
-+} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,
-+NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;
-+
-+
-+typedef struct _NDIS_802_11_WEP {
-+	u32     Length;        /* Length of this structure */
-+	u32     KeyIndex;      /* 0 is the per-client key, 1-N are the global keys */
-+	u32     KeyLength;     /* length of key in bytes */
-+	u8     KeyMaterial[16];/* variable length depending on above field */
-+} NDIS_802_11_WEP, *PNDIS_802_11_WEP;
-+
-+#endif /* PLATFORM_FREEBSD */
-+
-+#ifndef Ndis802_11APMode
-+#define Ndis802_11APMode (Ndis802_11InfrastructureMax+1)
-+#endif
-+
-+typedef struct _WLAN_PHY_INFO {
-+	u8	SignalStrength;/* (in percentage) */
-+	u8	SignalQuality;/* (in percentage) */
-+	u8	Optimum_antenna;  /* for Antenna diversity */
-+	u8	is_cck_rate;	/* 1:cck_rate */
-+	s8	rx_snr[4];
-+#ifdef CONFIG_RTW_80211K
-+	u32	free_cnt; 	/* freerun counter */
-+	u8	rm_en_cap[5];
-+#endif
-+} WLAN_PHY_INFO, *PWLAN_PHY_INFO;
-+
-+typedef struct _WLAN_BCN_INFO {
-+	/* these infor get from rtw_get_encrypt_info when
-+	 *	 * translate scan to UI */
-+	u8 encryp_protocol;/* ENCRYP_PROTOCOL_E: OPEN/WEP/WPA/WPA2/WAPI */
-+	int group_cipher; /* WPA/WPA2 group cipher */
-+	int pairwise_cipher;/* //WPA/WPA2/WEP pairwise cipher */
-+	int is_8021x;
-+
-+	/* bwmode 20/40 and ch_offset UP/LOW */
-+	unsigned short	ht_cap_info;
-+	unsigned char	ht_info_infos_0;
-+} WLAN_BCN_INFO, *PWLAN_BCN_INFO;
-+
-+enum bss_type {
-+	BSS_TYPE_UNDEF,
-+	BSS_TYPE_PROB_REQ = 1,
-+	BSS_TYPE_BCN = 2,
-+	BSS_TYPE_PROB_RSP = 3,
-+};
-+
-+/* temporally add #pragma pack for structure alignment issue of
-+*   WLAN_BSSID_EX and get_WLAN_BSSID_EX_sz()
-+*/
-+typedef struct _WLAN_BSSID_EX {
-+	u32  Length;
-+	NDIS_802_11_MAC_ADDRESS  MacAddress;
-+	u8  Reserved[2];/* [0]: IS beacon frame , bss_type*/
-+	NDIS_802_11_SSID  Ssid;
-+	NDIS_802_11_SSID  mesh_id;
-+	u32  Privacy;
-+	NDIS_802_11_RSSI  Rssi;/* (in dBM,raw data ,get from PHY) */
-+	NDIS_802_11_CONFIGURATION  Configuration;
-+	NDIS_802_11_NETWORK_INFRASTRUCTURE  InfrastructureMode;
-+	NDIS_802_11_RATES_EX  SupportedRates;
-+	WLAN_PHY_INFO	PhyInfo;
-+	u32  IELength;
-+	u8  IEs[MAX_IE_SZ];	/* (timestamp, beacon interval, and capability information) */
-+}
-+__attribute__((packed)) WLAN_BSSID_EX, *PWLAN_BSSID_EX;
-+
-+#define BSS_EX_IES(bss_ex) ((bss_ex)->IEs)
-+#define BSS_EX_IES_LEN(bss_ex) ((bss_ex)->IELength)
-+#define BSS_EX_FIXED_IE_OFFSET(bss_ex) ((bss_ex)->Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12)
-+#define BSS_EX_TLV_IES(bss_ex) (BSS_EX_IES((bss_ex)) + BSS_EX_FIXED_IE_OFFSET((bss_ex)))
-+#define BSS_EX_TLV_IES_LEN(bss_ex) (BSS_EX_IES_LEN((bss_ex)) - BSS_EX_FIXED_IE_OFFSET((bss_ex)))
-+
-+__inline  static uint get_WLAN_BSSID_EX_sz(WLAN_BSSID_EX *bss)
-+{
-+	return sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + bss->IELength;
-+}
-+
-+struct beacon_keys {
-+	u8 ssid[IW_ESSID_MAX_SIZE];
-+	u32 ssid_len;
-+	u8 ch;
-+	u8 bw;
-+	u8 offset;
-+	u8 proto_cap; /* PROTO_CAP_XXX */
-+	u8 rate_set[12];
-+	u8 rate_num;
-+	int encryp_protocol;
-+	int pairwise_cipher;
-+	int group_cipher;
-+	u32 akm;
-+};
-+
-+struct	wlan_network {
-+	_list	list;
-+	int	network_type;	/* refer to ieee80211.h for WIRELESS_11A/B/G */
-+	int	fixed;			/* set to fixed when not to be removed as site-surveying */
-+	systime last_scanned; /* timestamp for the network */
-+	systime last_non_hidden_ssid_ap;
-+#ifdef CONFIG_RTW_MESH
-+#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+	systime acnode_stime;
-+	systime acnode_notify_etime;
-+#endif
-+#endif
-+	int	aid;			/* will only be valid when a BSS is joinned. */
-+	int	join_res;
-+	struct beacon_keys bcn_keys;
-+	bool bcn_keys_valid;
-+	WLAN_BSSID_EX	network; /* must be the last item */
-+};
-+
-+enum VRTL_CARRIER_SENSE {
-+	DISABLE_VCS,
-+	ENABLE_VCS,
-+	AUTO_VCS
-+};
-+
-+enum VCS_TYPE {
-+	NONE_VCS,
-+	RTS_CTS,
-+	CTS_TO_SELF
-+};
-+
-+
-+
-+
-+#define PWR_CAM 0
-+#define PWR_MINPS 1
-+#define PWR_MAXPS 2
-+#define PWR_UAPSD 3
-+#define PWR_VOIP 4
-+
-+
-+enum UAPSD_MAX_SP {
-+	NO_LIMIT,
-+	TWO_MSDU,
-+	FOUR_MSDU,
-+	SIX_MSDU
-+};
-+
-+
-+/* john */
-+#define NUM_PRE_AUTH_KEY 16
-+#define NUM_PMKID_CACHE NUM_PRE_AUTH_KEY
-+
-+#endif /* #ifndef WLAN_BSSDEF_H_ */
-diff --git a/drivers/staging/rtl8723cs/include/xmit_osdep.h b/drivers/staging/rtl8723cs/include/xmit_osdep.h
-new file mode 100644
-index 000000000000..9bf9c93d5af3
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/include/xmit_osdep.h
-@@ -0,0 +1,96 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __XMIT_OSDEP_H_
-+#define __XMIT_OSDEP_H_
-+
-+
-+struct pkt_file {
-+	_pkt *pkt;
-+	SIZE_T pkt_len;	 /* the remainder length of the open_file */
-+	_buffer *cur_buffer;
-+	u8 *buf_start;
-+	u8 *cur_addr;
-+	SIZE_T buf_len;
-+};
-+
-+#ifdef PLATFORM_WINDOWS
-+
-+#ifdef PLATFORM_OS_XP
-+#ifdef CONFIG_USB_HCI
-+#include <usb.h>
-+#include <usbdlib.h>
-+#include <usbioctl.h>
-+#endif
-+#endif
-+
-+#ifdef CONFIG_GSPI_HCI
-+	#define NR_XMITFRAME     64
-+#else
-+	#define NR_XMITFRAME     128
-+#endif
-+
-+#define ETH_ALEN	6
-+
-+extern NDIS_STATUS rtw_xmit_entry(
-+	_nic_hdl		cnxt,
-+	NDIS_PACKET		*pkt,
-+	u32				flags
-+);
-+
-+#endif /* PLATFORM_WINDOWS */
-+
-+#ifdef PLATFORM_FREEBSD
-+#define NR_XMITFRAME	256
-+extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);
-+extern void rtw_xmit_entry_wrap(struct ifnet *pifp);
-+#endif /* PLATFORM_FREEBSD */
-+
-+#ifdef PLATFORM_LINUX
-+
-+#define NR_XMITFRAME	256
-+
-+struct xmit_priv;
-+struct pkt_attrib;
-+struct sta_xmit_priv;
-+struct xmit_frame;
-+struct xmit_buf;
-+
-+extern int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);
-+extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);
-+
-+#endif /* PLATFORM_LINUX */
-+
-+void rtw_os_xmit_schedule(_adapter *padapter);
-+
-+int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag);
-+void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 free_sz, u8 flag);
-+
-+extern void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib);
-+
-+extern uint rtw_remainder_len(struct pkt_file *pfile);
-+extern void _rtw_open_pktfile(_pkt *pkt, struct pkt_file *pfile);
-+extern uint _rtw_pktfile_read(struct pkt_file *pfile, u8 *rmem, uint rlen);
-+extern sint rtw_endofpktfile(struct pkt_file *pfile);
-+
-+extern void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt);
-+extern void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe);
-+
-+void rtw_os_check_wakup_queue(_adapter *adapter, u16 os_qid);
-+bool rtw_os_check_stop_queue(_adapter *adapter, u16 os_qid);
-+void rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed);
-+
-+void dump_os_queue(void *sel, _adapter *padapter);
-+
-+#endif /* __XMIT_OSDEP_H_ */
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/custom_gpio_linux.c b/drivers/staging/rtl8723cs/os_dep/linux/custom_gpio_linux.c
-new file mode 100644
-index 000000000000..23401b7d6b7c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/custom_gpio_linux.c
-@@ -0,0 +1,340 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include "drv_types.h"
-+
-+#ifdef CONFIG_PLATFORM_SPRD
-+
-+/* gspi func & GPIO define */
-+#include <mach/gpio.h>/* 0915 */
-+#include <mach/board.h>
-+
-+#if !(defined ANDROID_2X)
-+
-+#ifdef CONFIG_RTL8188E
-+#include <mach/regulator.h>
-+#include <linux/regulator/consumer.h>
-+#endif /* CONFIG_RTL8188E */
-+
-+#ifndef GPIO_WIFI_POWER
-+#define GPIO_WIFI_POWER -1
-+#endif /* !GPIO_WIFI_POWER */
-+
-+#ifndef GPIO_WIFI_RESET
-+#define GPIO_WIFI_RESET -1
-+#endif /* !GPIO_WIFI_RESET */
-+
-+#ifndef GPIO_WIFI_PWDN
-+#define GPIO_WIFI_PWDN -1
-+#endif /* !GPIO_WIFI_RESET */
-+#ifdef CONFIG_GSPI_HCI
-+extern unsigned int oob_irq;
-+#endif /* CONFIG_GSPI_HCI */
-+
-+#ifdef CONFIG_SDIO_HCI
-+extern int rtw_mp_mode;
-+#else /* !CONFIG_SDIO_HCI */
-+#endif /* !CONFIG_SDIO_HCI */
-+
-+int rtw_wifi_gpio_init(void)
-+{
-+#ifdef CONFIG_GSPI_HCI
-+	if (GPIO_WIFI_IRQ > 0) {
-+		gpio_request(GPIO_WIFI_IRQ, "oob_irq");
-+		gpio_direction_input(GPIO_WIFI_IRQ);
-+
-+		oob_irq = gpio_to_irq(GPIO_WIFI_IRQ);
-+
-+		RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq);
-+	}
-+#endif
-+	if (GPIO_WIFI_RESET > 0)
-+		gpio_request(GPIO_WIFI_RESET , "wifi_rst");
-+	if (GPIO_WIFI_POWER > 0)
-+		gpio_request(GPIO_WIFI_POWER, "wifi_power");
-+
-+#ifdef CONFIG_SDIO_HCI
-+#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1)
-+	if (rtw_mp_mode == 1) {
-+		RTW_INFO("%s GPIO_BT_RESET pin special for mp_test\n", __func__);
-+		if (GPIO_BT_RESET > 0)
-+			gpio_request(GPIO_BT_RESET , "bt_rst");
-+	}
-+#endif
-+#endif
-+	return 0;
-+}
-+
-+int rtw_wifi_gpio_deinit(void)
-+{
-+#ifdef CONFIG_GSPI_HCI
-+	if (GPIO_WIFI_IRQ > 0)
-+		gpio_free(GPIO_WIFI_IRQ);
-+#endif
-+	if (GPIO_WIFI_RESET > 0)
-+		gpio_free(GPIO_WIFI_RESET);
-+	if (GPIO_WIFI_POWER > 0)
-+		gpio_free(GPIO_WIFI_POWER);
-+
-+#ifdef CONFIG_SDIO_HCI
-+#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1)
-+	if (rtw_mp_mode == 1) {
-+		RTW_INFO("%s GPIO_BT_RESET pin special for mp_test\n", __func__);
-+		if (GPIO_BT_RESET > 0)
-+			gpio_free(GPIO_BT_RESET);
-+	}
-+#endif
-+#endif
-+	return 0;
-+}
-+
-+/* Customer function to control hw specific wlan gpios */
-+void rtw_wifi_gpio_wlan_ctrl(int onoff)
-+{
-+	switch (onoff) {
-+	case WLAN_PWDN_OFF:
-+		RTW_INFO("%s: call customer specific GPIO(%d) to set wifi power down pin to 0\n",
-+			 __FUNCTION__, GPIO_WIFI_RESET);
-+
-+#ifndef CONFIG_DONT_BUS_SCAN
-+		if (GPIO_WIFI_RESET > 0)
-+			gpio_direction_output(GPIO_WIFI_RESET , 0);
-+#endif
-+		break;
-+
-+	case WLAN_PWDN_ON:
-+		RTW_INFO("%s: callc customer specific GPIO(%d) to set wifi power down pin to 1\n",
-+			 __FUNCTION__, GPIO_WIFI_RESET);
-+
-+		if (GPIO_WIFI_RESET > 0)
-+			gpio_direction_output(GPIO_WIFI_RESET , 1);
-+		break;
-+
-+	case WLAN_POWER_OFF:
-+		break;
-+
-+	case WLAN_POWER_ON:
-+		break;
-+#ifdef CONFIG_SDIO_HCI
-+#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1)
-+	case WLAN_BT_PWDN_OFF:
-+		if (rtw_mp_mode == 1) {
-+			RTW_INFO("%s: call customer specific GPIO to set wifi power down pin to 0\n",
-+				 __FUNCTION__);
-+			if (GPIO_BT_RESET > 0)
-+				gpio_direction_output(GPIO_BT_RESET , 0);
-+		}
-+		break;
-+
-+	case WLAN_BT_PWDN_ON:
-+		if (rtw_mp_mode == 1) {
-+			RTW_INFO("%s: callc customer specific GPIO to set wifi power down pin to 1 %x\n",
-+				 __FUNCTION__, GPIO_BT_RESET);
-+
-+			if (GPIO_BT_RESET > 0)
-+				gpio_direction_output(GPIO_BT_RESET , 1);
-+		}
-+		break;
-+#endif
-+#endif
-+	}
-+}
-+
-+#else /* ANDROID_2X */
-+
-+#include <mach/ldo.h>
-+
-+#ifdef CONFIG_RTL8188E
-+extern int sprd_3rdparty_gpio_wifi_power;
-+#endif
-+extern int sprd_3rdparty_gpio_wifi_pwd;
-+#if  defined(CONFIG_RTL8723B)
-+extern int sprd_3rdparty_gpio_bt_reset;
-+#endif
-+
-+int rtw_wifi_gpio_init(void)
-+{
-+#if defined(CONFIG_RTL8723B)
-+	if (sprd_3rdparty_gpio_bt_reset > 0)
-+		gpio_direction_output(sprd_3rdparty_gpio_bt_reset, 1);
-+#endif
-+
-+	return 0;
-+}
-+
-+int rtw_wifi_gpio_deinit(void)
-+{
-+	return 0;
-+}
-+
-+/* Customer function to control hw specific wlan gpios */
-+void rtw_wifi_gpio_wlan_ctrl(int onoff)
-+{
-+	switch (onoff) {
-+	case WLAN_PWDN_OFF:
-+		RTW_INFO("%s: call customer specific GPIO to set wifi power down pin to 0\n",
-+			 __FUNCTION__);
-+		if (sprd_3rdparty_gpio_wifi_pwd > 0)
-+			gpio_set_value(sprd_3rdparty_gpio_wifi_pwd, 0);
-+
-+		if (sprd_3rdparty_gpio_wifi_pwd == 60) {
-+			RTW_INFO("%s: turn off VSIM2 2.8V\n", __func__);
-+			LDO_TurnOffLDO(LDO_LDO_SIM2);
-+		}
-+		break;
-+
-+	case WLAN_PWDN_ON:
-+		RTW_INFO("%s: callc customer specific GPIO to set wifi power down pin to 1\n",
-+			 __FUNCTION__);
-+		if (sprd_3rdparty_gpio_wifi_pwd == 60) {
-+			RTW_INFO("%s: turn on VSIM2 2.8V\n", __func__);
-+			LDO_SetVoltLevel(LDO_LDO_SIM2, LDO_VOLT_LEVEL0);
-+			LDO_TurnOnLDO(LDO_LDO_SIM2);
-+		}
-+		if (sprd_3rdparty_gpio_wifi_pwd > 0)
-+			gpio_set_value(sprd_3rdparty_gpio_wifi_pwd, 1);
-+		break;
-+
-+	case WLAN_POWER_OFF:
-+#ifdef CONFIG_RTL8188E
-+#ifdef CONFIG_WIF1_LDO
-+		RTW_INFO("%s: turn off VDD-WIFI0 1.2V\n", __FUNCTION__);
-+		LDO_TurnOffLDO(LDO_LDO_WIF1);
-+#endif /* CONFIG_WIF1_LDO */
-+
-+		RTW_INFO("%s: turn off VDD-WIFI0 3.3V\n", __FUNCTION__);
-+		LDO_TurnOffLDO(LDO_LDO_WIF0);
-+
-+		RTW_INFO("%s: call customer specific GPIO(%d) to turn off wifi power\n",
-+			 __FUNCTION__, sprd_3rdparty_gpio_wifi_power);
-+		if (sprd_3rdparty_gpio_wifi_power != 65535)
-+			gpio_set_value(sprd_3rdparty_gpio_wifi_power, 0);
-+#endif
-+		break;
-+
-+	case WLAN_POWER_ON:
-+#ifdef CONFIG_RTL8188E
-+		RTW_INFO("%s: call customer specific GPIO(%d) to turn on wifi power\n",
-+			 __FUNCTION__, sprd_3rdparty_gpio_wifi_power);
-+		if (sprd_3rdparty_gpio_wifi_power != 65535)
-+			gpio_set_value(sprd_3rdparty_gpio_wifi_power, 1);
-+
-+		RTW_INFO("%s: turn on VDD-WIFI0 3.3V\n", __FUNCTION__);
-+		LDO_TurnOnLDO(LDO_LDO_WIF0);
-+		LDO_SetVoltLevel(LDO_LDO_WIF0, LDO_VOLT_LEVEL1);
-+
-+#ifdef CONFIG_WIF1_LDO
-+		RTW_INFO("%s: turn on VDD-WIFI1 1.2V\n", __func__);
-+		LDO_TurnOnLDO(LDO_LDO_WIF1);
-+		LDO_SetVoltLevel(LDO_LDO_WIF1, LDO_VOLT_LEVEL3);
-+#endif /* CONFIG_WIF1_LDO */
-+#endif
-+		break;
-+
-+	case WLAN_BT_PWDN_OFF:
-+		RTW_INFO("%s: call customer specific GPIO to set bt power down pin to 0\n",
-+			 __FUNCTION__);
-+#if defined(CONFIG_RTL8723B)
-+		if (sprd_3rdparty_gpio_bt_reset > 0)
-+			gpio_set_value(sprd_3rdparty_gpio_bt_reset, 0);
-+#endif
-+		break;
-+
-+	case WLAN_BT_PWDN_ON:
-+		RTW_INFO("%s: callc customer specific GPIO to set bt power down pin to 1\n",
-+			 __FUNCTION__);
-+#if defined(CONFIG_RTL8723B)
-+		if (sprd_3rdparty_gpio_bt_reset > 0)
-+			gpio_set_value(sprd_3rdparty_gpio_bt_reset, 1);
-+#endif
-+		break;
-+	}
-+}
-+#endif /* ANDROID_2X */
-+
-+#elif defined(CONFIG_PLATFORM_ARM_RK3066)
-+#include <mach/iomux.h>
-+
-+#define GPIO_WIFI_IRQ		RK30_PIN2_PC2
-+extern unsigned int oob_irq;
-+int rtw_wifi_gpio_init(void)
-+{
-+#ifdef CONFIG_GSPI_HCI
-+	if (GPIO_WIFI_IRQ > 0) {
-+		rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME, GPIO2C_GPIO2C2);/* jacky_test */
-+		gpio_request(GPIO_WIFI_IRQ, "oob_irq");
-+		gpio_direction_input(GPIO_WIFI_IRQ);
-+
-+		oob_irq = gpio_to_irq(GPIO_WIFI_IRQ);
-+
-+		RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq);
-+	}
-+#endif
-+	return 0;
-+}
-+
-+
-+int rtw_wifi_gpio_deinit(void)
-+{
-+#ifdef CONFIG_GSPI_HCI
-+	if (GPIO_WIFI_IRQ > 0)
-+		gpio_free(GPIO_WIFI_IRQ);
-+#endif
-+	return 0;
-+}
-+
-+void rtw_wifi_gpio_wlan_ctrl(int onoff)
-+{
-+}
-+
-+#ifdef CONFIG_GPIO_API
-+/* this is a demo for extending GPIO pin[7] as interrupt mode */
-+struct net_device *rtl_net;
-+extern int rtw_register_gpio_interrupt(struct net_device *netdev, int gpio_num, void(*callback)(u8 level));
-+extern int rtw_disable_gpio_interrupt(struct net_device *netdev, int gpio_num);
-+void gpio_int(u8 is_high)
-+{
-+	RTW_INFO("%s level=%d\n", __func__, is_high);
-+}
-+int register_net_gpio_init(void)
-+{
-+	rtl_net = dev_get_by_name(&init_net, "wlan0");
-+	if (!rtl_net) {
-+		RTW_PRINT("rtl_net init fail!\n");
-+		return -1;
-+	}
-+	return rtw_register_gpio_interrupt(rtl_net, 7, gpio_int);
-+}
-+int unregister_net_gpio_init(void)
-+{
-+	rtl_net = dev_get_by_name(&init_net, "wlan0");
-+	if (!rtl_net) {
-+		RTW_PRINT("rtl_net init fail!\n");
-+		return -1;
-+	}
-+	return rtw_disable_gpio_interrupt(rtl_net, 7);
-+}
-+#endif
-+
-+#else
-+
-+int rtw_wifi_gpio_init(void)
-+{
-+	return 0;
-+}
-+
-+void rtw_wifi_gpio_wlan_ctrl(int onoff)
-+{
-+}
-+#endif /* CONFIG_PLATFORM_SPRD */
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/ioctl_cfg80211.c b/drivers/staging/rtl8723cs/os_dep/linux/ioctl_cfg80211.c
-new file mode 100644
-index 000000000000..ca999734af96
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/ioctl_cfg80211.c
-@@ -0,0 +1,10852 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define  _IOCTL_CFG80211_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+
-+#ifndef DBG_RTW_CFG80211_STA_PARAM
-+#define DBG_RTW_CFG80211_STA_PARAM 0
-+#endif
-+
-+#ifndef DBG_RTW_CFG80211_MESH_CONF
-+#define DBG_RTW_CFG80211_MESH_CONF 0
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
-+#define STATION_INFO_INACTIVE_TIME	BIT(NL80211_STA_INFO_INACTIVE_TIME)
-+#define STATION_INFO_LLID			BIT(NL80211_STA_INFO_LLID)
-+#define STATION_INFO_PLID			BIT(NL80211_STA_INFO_PLID)
-+#define STATION_INFO_PLINK_STATE	BIT(NL80211_STA_INFO_PLINK_STATE)
-+#define STATION_INFO_SIGNAL			BIT(NL80211_STA_INFO_SIGNAL)
-+#define STATION_INFO_TX_BITRATE		BIT(NL80211_STA_INFO_TX_BITRATE)
-+#define STATION_INFO_RX_PACKETS		BIT(NL80211_STA_INFO_RX_PACKETS)
-+#define STATION_INFO_TX_PACKETS		BIT(NL80211_STA_INFO_TX_PACKETS)
-+#define STATION_INFO_TX_FAILED		BIT(NL80211_STA_INFO_TX_FAILED)
-+#define STATION_INFO_LOCAL_PM		BIT(NL80211_STA_INFO_LOCAL_PM)
-+#define STATION_INFO_PEER_PM		BIT(NL80211_STA_INFO_PEER_PM)
-+#define STATION_INFO_NONPEER_PM		BIT(NL80211_STA_INFO_NONPEER_PM)
-+#define STATION_INFO_ASSOC_REQ_IES	0
-+#endif /* Linux kernel >= 4.0.0 */
-+
-+#define RTW_MAX_MGMT_TX_CNT (8)
-+#define RTW_MAX_MGMT_TX_MS_GAS (500)
-+
-+#define RTW_SCAN_IE_LEN_MAX      2304
-+#define RTW_MAX_REMAIN_ON_CHANNEL_DURATION 5000 /* ms */
-+#define RTW_MAX_NUM_PMKIDS 4
-+
-+#define RTW_CH_MAX_2G_CHANNEL               14      /* Max channel in 2G band */
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+
-+#ifndef WLAN_CIPHER_SUITE_SMS4
-+#define WLAN_CIPHER_SUITE_SMS4          0x00147201
-+#endif
-+
-+#ifndef WLAN_AKM_SUITE_WAPI_PSK
-+#define WLAN_AKM_SUITE_WAPI_PSK         0x000FAC04
-+#endif
-+
-+#ifndef WLAN_AKM_SUITE_WAPI_CERT
-+#define WLAN_AKM_SUITE_WAPI_CERT        0x000FAC12
-+#endif
-+
-+#ifndef NL80211_WAPI_VERSION_1
-+#define NL80211_WAPI_VERSION_1          (1 << 2)
-+#endif
-+
-+#endif /* CONFIG_WAPI_SUPPORT */
-+
-+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(4, 11, 12))
-+#ifdef CONFIG_RTW_80211R
-+#define WLAN_AKM_SUITE_FT_8021X		0x000FAC03
-+#define WLAN_AKM_SUITE_FT_PSK			0x000FAC04
-+#endif
-+#endif
-+
-+#define WIFI_CIPHER_SUITE_GCMP		0x000FAC08
-+#define WIFI_CIPHER_SUITE_GCMP_256	0x000FAC09
-+#define WIFI_CIPHER_SUITE_CCMP_256	0x000FAC0A
-+#define WIFI_CIPHER_SUITE_BIP_GMAC_128	0x000FAC0B
-+#define WIFI_CIPHER_SUITE_BIP_GMAC_256	0x000FAC0C
-+#define WIFI_CIPHER_SUITE_BIP_CMAC_256	0x000FAC0D
-+
-+/*
-+ * If customer need, defining this flag will make driver 
-+ * always return -EBUSY at the condition of scan deny.
-+ */
-+/* #define CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY */
-+
-+static const u32 rtw_cipher_suites[] = {
-+	WLAN_CIPHER_SUITE_WEP40,
-+	WLAN_CIPHER_SUITE_WEP104,
-+	WLAN_CIPHER_SUITE_TKIP,
-+	WLAN_CIPHER_SUITE_CCMP,
-+#ifdef CONFIG_WAPI_SUPPORT
-+	WLAN_CIPHER_SUITE_SMS4,
-+#endif /* CONFIG_WAPI_SUPPORT */
-+#ifdef CONFIG_IEEE80211W
-+	WLAN_CIPHER_SUITE_AES_CMAC,
-+	WIFI_CIPHER_SUITE_GCMP,
-+	WIFI_CIPHER_SUITE_GCMP_256,
-+	WIFI_CIPHER_SUITE_CCMP_256,
-+	WIFI_CIPHER_SUITE_BIP_GMAC_128,
-+	WIFI_CIPHER_SUITE_BIP_GMAC_256,
-+	WIFI_CIPHER_SUITE_BIP_CMAC_256,
-+#endif /* CONFIG_IEEE80211W */
-+};
-+
-+#define RATETAB_ENT(_rate, _rateid, _flags) \
-+	{								\
-+		.bitrate	= (_rate),				\
-+		.hw_value	= (_rateid),				\
-+		.flags		= (_flags),				\
-+	}
-+
-+#define CHAN2G(_channel, _freq, _flags) {			\
-+		.band			= NL80211_BAND_2GHZ,		\
-+		.center_freq		= (_freq),			\
-+		.hw_value		= (_channel),			\
-+		.flags			= (_flags),			\
-+		.max_antenna_gain	= 0,				\
-+		.max_power		= 0,				\
-+	}
-+
-+#define CHAN5G(_channel, _flags) {				\
-+		.band			= NL80211_BAND_5GHZ,		\
-+		.center_freq		= 5000 + (5 * (_channel)),	\
-+		.hw_value		= (_channel),			\
-+		.flags			= (_flags),			\
-+		.max_antenna_gain	= 0,				\
-+		.max_power		= 0,				\
-+	}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+/* if wowlan is not supported, kernel generate a disconnect at each suspend
-+ * cf: /net/wireless/sysfs.c, so register a stub wowlan.
-+ * Moreover wowlan has to be enabled via a the nl80211_set_wowlan callback.
-+ * (from user space, e.g. iw phy0 wowlan enable)
-+ */
-+static const struct wiphy_wowlan_support wowlan_stub = {
-+	.flags = WIPHY_WOWLAN_ANY,
-+	.n_patterns = 0,
-+	.pattern_max_len = 0,
-+	.pattern_min_len = 0,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
-+	.max_pkt_offset = 0,
-+#endif
-+};
-+#endif
-+
-+static struct ieee80211_rate rtw_rates[] = {
-+	RATETAB_ENT(10,  0x1,   0),
-+	RATETAB_ENT(20,  0x2,   0),
-+	RATETAB_ENT(55,  0x4,   0),
-+	RATETAB_ENT(110, 0x8,   0),
-+	RATETAB_ENT(60,  0x10,  0),
-+	RATETAB_ENT(90,  0x20,  0),
-+	RATETAB_ENT(120, 0x40,  0),
-+	RATETAB_ENT(180, 0x80,  0),
-+	RATETAB_ENT(240, 0x100, 0),
-+	RATETAB_ENT(360, 0x200, 0),
-+	RATETAB_ENT(480, 0x400, 0),
-+	RATETAB_ENT(540, 0x800, 0),
-+};
-+
-+#define rtw_a_rates		(rtw_rates + 4)
-+#define RTW_A_RATES_NUM	8
-+#define rtw_g_rates		(rtw_rates + 0)
-+#define RTW_G_RATES_NUM	12
-+
-+/* from center_ch_2g */
-+static struct ieee80211_channel rtw_2ghz_channels[MAX_CHANNEL_NUM_2G] = {
-+	CHAN2G(1, 2412, 0),
-+	CHAN2G(2, 2417, 0),
-+	CHAN2G(3, 2422, 0),
-+	CHAN2G(4, 2427, 0),
-+	CHAN2G(5, 2432, 0),
-+	CHAN2G(6, 2437, 0),
-+	CHAN2G(7, 2442, 0),
-+	CHAN2G(8, 2447, 0),
-+	CHAN2G(9, 2452, 0),
-+	CHAN2G(10, 2457, 0),
-+	CHAN2G(11, 2462, 0),
-+	CHAN2G(12, 2467, 0),
-+	CHAN2G(13, 2472, 0),
-+	CHAN2G(14, 2484, 0),
-+};
-+
-+/* from center_ch_5g_20m */
-+static struct ieee80211_channel rtw_5ghz_a_channels[MAX_CHANNEL_NUM_5G] = {
-+	CHAN5G(36, 0),	CHAN5G(40, 0),	CHAN5G(44, 0),	CHAN5G(48, 0),
-+
-+	CHAN5G(52, 0),	CHAN5G(56, 0),	CHAN5G(60, 0),	CHAN5G(64, 0),
-+
-+	CHAN5G(100, 0),	CHAN5G(104, 0),	CHAN5G(108, 0),	CHAN5G(112, 0),
-+	CHAN5G(116, 0),	CHAN5G(120, 0),	CHAN5G(124, 0),	CHAN5G(128, 0),
-+	CHAN5G(132, 0),	CHAN5G(136, 0),	CHAN5G(140, 0),	CHAN5G(144, 0),
-+
-+	CHAN5G(149, 0),	CHAN5G(153, 0),	CHAN5G(157, 0),	CHAN5G(161, 0),
-+	CHAN5G(165, 0),	CHAN5G(169, 0),	CHAN5G(173, 0),	CHAN5G(177, 0),
-+};
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+static u8 rtw_chbw_to_cfg80211_chan_def(struct wiphy *wiphy, struct cfg80211_chan_def *chdef, u8 ch, u8 bw, u8 offset, u8 ht)
-+{
-+	int freq, cfreq;
-+	struct ieee80211_channel *chan;
-+	u8 ret = _FAIL;
-+
-+	_rtw_memset(chdef, 0, sizeof(*chdef));
-+
-+	freq = rtw_ch2freq(ch);
-+	if (!freq)
-+		goto exit;
-+
-+	cfreq = rtw_get_center_ch(ch, bw, offset);
-+	if (!cfreq)
-+		goto exit;
-+	cfreq = rtw_ch2freq(cfreq);
-+	if (!cfreq)
-+		goto exit;
-+
-+	chan = ieee80211_get_channel(wiphy, freq);
-+	if (!chan)
-+		goto exit;
-+
-+	if (bw == CHANNEL_WIDTH_20) 
-+		chdef->width = ht ? NL80211_CHAN_WIDTH_20 : NL80211_CHAN_WIDTH_20_NOHT;
-+	else if (bw == CHANNEL_WIDTH_40)
-+		chdef->width = NL80211_CHAN_WIDTH_40;
-+	else if (bw == CHANNEL_WIDTH_80)
-+		chdef->width = NL80211_CHAN_WIDTH_80;
-+	else if (bw == CHANNEL_WIDTH_160)
-+		chdef->width = NL80211_CHAN_WIDTH_160;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+	else if (bw == CHANNEL_WIDTH_5)
-+		chdef->width = NL80211_CHAN_WIDTH_5;
-+	else if (bw == CHANNEL_WIDTH_10)
-+		chdef->width = NL80211_CHAN_WIDTH_10;
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) */
-+	else {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	chdef->chan = chan;
-+	chdef->center_freq1 = cfreq;
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+#ifdef CONFIG_RTW_MESH
-+static const char *nl80211_chan_width_str(enum nl80211_chan_width cwidth)
-+{
-+	switch (cwidth) {
-+	case NL80211_CHAN_WIDTH_20_NOHT:
-+		return "20_NOHT";
-+	case NL80211_CHAN_WIDTH_20:
-+		return "20";
-+	case NL80211_CHAN_WIDTH_40:
-+		return "40";
-+	case NL80211_CHAN_WIDTH_80:
-+		return "80";
-+	case NL80211_CHAN_WIDTH_80P80:
-+		return "80+80";
-+	case NL80211_CHAN_WIDTH_160:
-+		return "160";
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+	case NL80211_CHAN_WIDTH_5:
-+		return "5";
-+	case NL80211_CHAN_WIDTH_10:
-+		return "10";
-+#endif
-+	default:
-+		return "INVALID";
-+	};
-+}
-+
-+static void rtw_get_chbw_from_cfg80211_chan_def(struct cfg80211_chan_def *chdef, u8 *ht, u8 *ch, u8 *bw, u8 *offset)
-+{
-+	int pri_freq;
-+	struct ieee80211_channel *chan = chdef->chan;
-+
-+	pri_freq = rtw_ch2freq(chan->hw_value);
-+	if (!pri_freq) {
-+		RTW_INFO("invalid channel:%d\n", chan->hw_value);
-+		rtw_warn_on(1);
-+		*ch = 0;
-+		return;
-+	}		
-+
-+	switch (chdef->width) {
-+	case NL80211_CHAN_WIDTH_20_NOHT:
-+		*ht = 0;
-+		*bw = CHANNEL_WIDTH_20;
-+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		*ch = chan->hw_value;
-+		break;
-+	case NL80211_CHAN_WIDTH_20:
-+		*ht = 1;
-+		*bw = CHANNEL_WIDTH_20;
-+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		*ch = chan->hw_value;
-+		break;
-+	case NL80211_CHAN_WIDTH_40:
-+		*ht = 1;
-+		*bw = CHANNEL_WIDTH_40;
-+		*offset = pri_freq > chdef->center_freq1 ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER;
-+		if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset))
-+			*ch = chan->hw_value;
-+		break;
-+	case NL80211_CHAN_WIDTH_80:
-+		*ht = 1;
-+		*bw = CHANNEL_WIDTH_80;
-+		if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset))
-+			*ch = chan->hw_value;
-+		break;
-+	case NL80211_CHAN_WIDTH_160:
-+		*ht = 1;
-+		*bw = CHANNEL_WIDTH_160;
-+		if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset))
-+			*ch = chan->hw_value;
-+		break;
-+	case NL80211_CHAN_WIDTH_80P80:
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+	case NL80211_CHAN_WIDTH_5:
-+	case NL80211_CHAN_WIDTH_10:
-+	#endif
-+	default:
-+		*ht = 0;
-+		*bw = CHANNEL_WIDTH_20;
-+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		RTW_INFO("unsupported cwidth:%s\n", nl80211_chan_width_str(chdef->width));
-+		rtw_warn_on(1);
-+	};
-+}
-+#endif /* CONFIG_RTW_MESH */
-+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+static const char *nl80211_channel_type_str(enum nl80211_channel_type ctype)
-+{
-+	switch (ctype) {
-+	case NL80211_CHAN_NO_HT:
-+		return "NO_HT";
-+	case NL80211_CHAN_HT20:
-+		return "HT20";
-+	case NL80211_CHAN_HT40MINUS:
-+		return "HT40-";
-+	case NL80211_CHAN_HT40PLUS:
-+		return "HT40+";
-+	default:
-+		return "INVALID";
-+	};
-+}
-+
-+static enum nl80211_channel_type rtw_chbw_to_nl80211_channel_type(u8 ch, u8 bw, u8 offset, u8 ht)
-+{
-+	rtw_warn_on(!ht && (bw >= CHANNEL_WIDTH_40 || offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE));
-+
-+	if (!ht)
-+		return NL80211_CHAN_NO_HT;
-+	if (bw >= CHANNEL_WIDTH_40) {
-+		if (offset == HAL_PRIME_CHNL_OFFSET_UPPER)
-+			return NL80211_CHAN_HT40MINUS;
-+		else if (offset == HAL_PRIME_CHNL_OFFSET_LOWER)
-+			return NL80211_CHAN_HT40PLUS;
-+		else
-+			rtw_warn_on(1);
-+	}
-+	return NL80211_CHAN_HT20;
-+}
-+
-+static void rtw_get_chbw_from_nl80211_channel_type(struct ieee80211_channel *chan, enum nl80211_channel_type ctype, u8 *ht, u8 *ch, u8 *bw, u8 *offset)
-+{
-+	int pri_freq;
-+
-+	pri_freq = rtw_ch2freq(chan->hw_value);
-+	if (!pri_freq) {
-+		RTW_INFO("invalid channel:%d\n", chan->hw_value);
-+		rtw_warn_on(1);
-+		*ch = 0;
-+		return;
-+	}
-+	*ch = chan->hw_value;
-+
-+	switch (ctype) {
-+	case NL80211_CHAN_NO_HT:
-+		*ht = 0;
-+		*bw = CHANNEL_WIDTH_20;
-+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		break;
-+	case NL80211_CHAN_HT20:
-+		*ht = 1;
-+		*bw = CHANNEL_WIDTH_20;
-+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		break;
-+	case NL80211_CHAN_HT40MINUS:
-+		*ht = 1;
-+		*bw = CHANNEL_WIDTH_40;
-+		*offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+		break;
-+	case NL80211_CHAN_HT40PLUS:
-+		*ht = 1;
-+		*bw = CHANNEL_WIDTH_40;
-+		*offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+		break;
-+	default:
-+		*ht = 0;
-+		*bw = CHANNEL_WIDTH_20;
-+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		RTW_INFO("unsupported ctype:%s\n", nl80211_channel_type_str(ctype));
-+		rtw_warn_on(1);
-+	};
-+}
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) */
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
-+bool rtw_cfg80211_allow_ch_switch_notify(_adapter *adapter)
-+{
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0))
-+	if ((!MLME_IS_AP(adapter))
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))
-+		&& (!MLME_IS_ADHOC(adapter))
-+		&& (!MLME_IS_ADHOC_MASTER(adapter))
-+		&& (!MLME_IS_MESH(adapter))
-+#elif defined(CONFIG_RTW_MESH)
-+		&& (!MLME_IS_MESH(adapter))
-+#endif
-+		)
-+		return 0;
-+#endif
-+	return 1;
-+}
-+
-+u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset,
-+	u8 ht, bool started)
-+{
-+	struct wiphy *wiphy = adapter_to_wiphy(adapter);
-+	u8 ret = _SUCCESS;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	struct cfg80211_chan_def chdef;
-+
-+	ret = rtw_chbw_to_cfg80211_chan_def(wiphy, &chdef, ch, bw, offset, ht);
-+	if (ret != _SUCCESS)
-+		goto exit;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
-+	if (started) {
-+		cfg80211_ch_switch_started_notify(adapter->pnetdev, &chdef, 0, false);
-+		goto exit;
-+	}
-+#endif
-+
-+	if (!rtw_cfg80211_allow_ch_switch_notify(adapter))
-+		goto exit;
-+
-+	cfg80211_ch_switch_notify(adapter->pnetdev, &chdef);
-+
-+#else
-+	int freq = rtw_ch2freq(ch);
-+	enum nl80211_channel_type ctype;
-+
-+	if (!rtw_cfg80211_allow_ch_switch_notify(adapter))
-+		goto exit;
-+
-+	if (!freq) {
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	ctype = rtw_chbw_to_nl80211_channel_type(ch, bw, offset, ht);
-+	cfg80211_ch_switch_notify(adapter->pnetdev, freq, ctype);
-+#endif
-+
-+exit:
-+	return ret;
-+}
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */
-+
-+void rtw_2g_channels_init(struct ieee80211_channel *channels)
-+{
-+	_rtw_memcpy((void *)channels, (void *)rtw_2ghz_channels, sizeof(rtw_2ghz_channels));
-+}
-+
-+void rtw_5g_channels_init(struct ieee80211_channel *channels)
-+{
-+	_rtw_memcpy((void *)channels, (void *)rtw_5ghz_a_channels, sizeof(rtw_5ghz_a_channels));
-+}
-+
-+void rtw_2g_rates_init(struct ieee80211_rate *rates)
-+{
-+	_rtw_memcpy(rates, rtw_g_rates,
-+		sizeof(struct ieee80211_rate) * RTW_G_RATES_NUM
-+	);
-+}
-+
-+void rtw_5g_rates_init(struct ieee80211_rate *rates)
-+{
-+	_rtw_memcpy(rates, rtw_a_rates,
-+		sizeof(struct ieee80211_rate) * RTW_A_RATES_NUM
-+	);
-+}
-+
-+struct ieee80211_supported_band *rtw_spt_band_alloc(BAND_TYPE band)
-+{
-+	struct ieee80211_supported_band *spt_band = NULL;
-+	int n_channels, n_bitrates;
-+
-+	if (band == BAND_ON_2_4G) {
-+		n_channels = MAX_CHANNEL_NUM_2G;
-+		n_bitrates = RTW_G_RATES_NUM;
-+	} else if (band == BAND_ON_5G) {
-+		n_channels = MAX_CHANNEL_NUM_5G;
-+		n_bitrates = RTW_A_RATES_NUM;
-+	} else
-+		goto exit;
-+
-+	spt_band = (struct ieee80211_supported_band *)rtw_zmalloc(
-+		sizeof(struct ieee80211_supported_band)
-+		+ sizeof(struct ieee80211_channel) * n_channels
-+		+ sizeof(struct ieee80211_rate) * n_bitrates
-+	);
-+	if (!spt_band)
-+		goto exit;
-+
-+	spt_band->channels = (struct ieee80211_channel *)(((u8 *)spt_band) + sizeof(struct ieee80211_supported_band));
-+	spt_band->bitrates = (struct ieee80211_rate *)(((u8 *)spt_band->channels) + sizeof(struct ieee80211_channel) * n_channels);
-+	spt_band->band = rtw_band_to_nl80211_band(band);
-+	spt_band->n_channels = n_channels;
-+	spt_band->n_bitrates = n_bitrates;
-+
-+exit:
-+	return spt_band;
-+}
-+
-+void rtw_spt_band_free(struct ieee80211_supported_band *spt_band)
-+{
-+	u32 size = 0;
-+
-+	if (!spt_band)
-+		return;
-+
-+	if (spt_band->band == NL80211_BAND_2GHZ) {
-+		size = sizeof(struct ieee80211_supported_band)
-+			+ sizeof(struct ieee80211_channel) * MAX_CHANNEL_NUM_2G
-+			+ sizeof(struct ieee80211_rate) * RTW_G_RATES_NUM;
-+	} else if (spt_band->band == NL80211_BAND_5GHZ) {
-+		size = sizeof(struct ieee80211_supported_band)
-+			+ sizeof(struct ieee80211_channel) * MAX_CHANNEL_NUM_5G
-+			+ sizeof(struct ieee80211_rate) * RTW_A_RATES_NUM;
-+	} else {
-+
-+	}
-+	rtw_mfree((u8 *)spt_band, size);
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+static const struct ieee80211_txrx_stypes
-+	rtw_cfg80211_default_mgmt_stypes[NUM_NL80211_IFTYPES] = {
-+	[NL80211_IFTYPE_ADHOC] = {
-+		.tx = 0xffff,
-+		.rx = BIT(IEEE80211_STYPE_ACTION >> 4)
-+	},
-+	[NL80211_IFTYPE_STATION] = {
-+		.tx = 0xffff,
-+		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
-+		BIT(IEEE80211_STYPE_AUTH >> 4) |
-+		BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
-+	},
-+	[NL80211_IFTYPE_AP] = {
-+		.tx = 0xffff,
-+		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
-+		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
-+		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
-+		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
-+		BIT(IEEE80211_STYPE_AUTH >> 4) |
-+		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
-+		BIT(IEEE80211_STYPE_ACTION >> 4)
-+	},
-+	[NL80211_IFTYPE_AP_VLAN] = {
-+		/* copy AP */
-+		.tx = 0xffff,
-+		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
-+		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
-+		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
-+		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
-+		BIT(IEEE80211_STYPE_AUTH >> 4) |
-+		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
-+		BIT(IEEE80211_STYPE_ACTION >> 4)
-+	},
-+	[NL80211_IFTYPE_P2P_CLIENT] = {
-+		.tx = 0xffff,
-+		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
-+		BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
-+	},
-+	[NL80211_IFTYPE_P2P_GO] = {
-+		.tx = 0xffff,
-+		.rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
-+		BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
-+		BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
-+		BIT(IEEE80211_STYPE_DISASSOC >> 4) |
-+		BIT(IEEE80211_STYPE_AUTH >> 4) |
-+		BIT(IEEE80211_STYPE_DEAUTH >> 4) |
-+		BIT(IEEE80211_STYPE_ACTION >> 4)
-+	},
-+#if defined(RTW_DEDICATED_P2P_DEVICE)
-+	[NL80211_IFTYPE_P2P_DEVICE] = {
-+		.tx = 0xffff,
-+		.rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
-+			BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
-+	},
-+#endif
-+#if defined(CONFIG_RTW_MESH)
-+	[NL80211_IFTYPE_MESH_POINT] = {
-+		.tx = 0xffff,
-+		.rx = BIT(IEEE80211_STYPE_ACTION >> 4)
-+			| BIT(IEEE80211_STYPE_AUTH >> 4)
-+	},
-+#endif
-+
-+};
-+#endif
-+
-+NDIS_802_11_NETWORK_INFRASTRUCTURE nl80211_iftype_to_rtw_network_type(enum nl80211_iftype type)
-+{
-+	switch (type) {
-+	case NL80211_IFTYPE_ADHOC:
-+		return Ndis802_11IBSS;
-+
-+	#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
-+	case NL80211_IFTYPE_P2P_CLIENT:
-+	#endif
-+	case NL80211_IFTYPE_STATION:
-+		return Ndis802_11Infrastructure;
-+
-+#ifdef CONFIG_AP_MODE
-+	#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
-+	case NL80211_IFTYPE_P2P_GO:
-+	#endif
-+	case NL80211_IFTYPE_AP:
-+		return Ndis802_11APMode;
-+#endif
-+
-+#ifdef CONFIG_RTW_MESH
-+	case NL80211_IFTYPE_MESH_POINT:
-+		return Ndis802_11_mesh;
-+#endif
-+
-+#ifdef CONFIG_WIFI_MONITOR
-+	case NL80211_IFTYPE_MONITOR:
-+		return Ndis802_11Monitor;
-+#endif /* CONFIG_WIFI_MONITOR */
-+
-+	default:
-+		return Ndis802_11InfrastructureMax;
-+	}
-+}
-+
-+u32 nl80211_iftype_to_rtw_mlme_state(enum nl80211_iftype type)
-+{
-+	switch (type) {
-+	case NL80211_IFTYPE_ADHOC:
-+		return WIFI_ADHOC_STATE;
-+
-+	#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
-+	case NL80211_IFTYPE_P2P_CLIENT:
-+	#endif
-+	case NL80211_IFTYPE_STATION:
-+		return WIFI_STATION_STATE;
-+
-+#ifdef CONFIG_AP_MODE
-+	#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
-+	case NL80211_IFTYPE_P2P_GO:
-+	#endif
-+	case NL80211_IFTYPE_AP:
-+		return WIFI_AP_STATE;
-+#endif
-+
-+#ifdef CONFIG_RTW_MESH
-+	case NL80211_IFTYPE_MESH_POINT:
-+		return WIFI_MESH_STATE;
-+#endif
-+
-+	case NL80211_IFTYPE_MONITOR:
-+		return WIFI_MONITOR_STATE;
-+
-+	default:
-+		return WIFI_NULL_STATE;
-+	}
-+}
-+
-+static int rtw_cfg80211_sync_iftype(_adapter *adapter)
-+{
-+	struct wireless_dev *rtw_wdev = adapter->rtw_wdev;
-+
-+	if (!(nl80211_iftype_to_rtw_mlme_state(rtw_wdev->iftype) & MLME_STATE(adapter))) {
-+		/* iftype and mlme state is not syc */
-+		NDIS_802_11_NETWORK_INFRASTRUCTURE network_type;
-+
-+		network_type = nl80211_iftype_to_rtw_network_type(rtw_wdev->iftype);
-+		if (network_type != Ndis802_11InfrastructureMax) {
-+			if (rtw_pwr_wakeup(adapter) == _FAIL) {
-+				RTW_WARN(FUNC_ADPT_FMT" call rtw_pwr_wakeup fail\n", FUNC_ADPT_ARG(adapter));
-+				return _FAIL;
-+			}
-+
-+			rtw_set_802_11_infrastructure_mode(adapter, network_type, 0);
-+			rtw_setopmode_cmd(adapter, network_type, RTW_CMDF_WAIT_ACK);
-+		} else {
-+			rtw_warn_on(1);
-+			RTW_WARN(FUNC_ADPT_FMT" iftype:%u is not support\n", FUNC_ADPT_ARG(adapter), rtw_wdev->iftype);
-+			return _FAIL;
-+		}
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+static u64 rtw_get_systime_us(void)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0))
-+	return ktime_to_us(ktime_get_boottime());
-+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
-+	struct timespec ts;
-+	get_monotonic_boottime(&ts);
-+	return ((u64)ts.tv_sec * 1000000) + ts.tv_nsec / 1000;
-+#else
-+	struct timeval tv;
-+	do_gettimeofday(&tv);
-+	return ((u64)tv.tv_sec * 1000000) + tv.tv_usec;
-+#endif
-+}
-+
-+/* Try to remove non target BSS's SR to reduce PBC overlap rate */
-+static int rtw_cfg80211_clear_wps_sr_of_non_target_bss(_adapter *padapter, struct wlan_network *pnetwork, struct cfg80211_ssid *req_ssid)
-+{
-+	int ret = 0;
-+	u8 *psr = NULL, sr = 0;
-+	NDIS_802_11_SSID *pssid = &pnetwork->network.Ssid;
-+	u32 wpsielen = 0;
-+	u8 *wpsie = NULL;
-+
-+	if (pssid->SsidLength == req_ssid->ssid_len
-+		&& _rtw_memcmp(pssid->Ssid, req_ssid->ssid, req_ssid->ssid_len) == _TRUE)
-+		goto exit;
-+
-+	wpsie = rtw_get_wps_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_
-+		, pnetwork->network.IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen);
-+	if (wpsie && wpsielen > 0)
-+		psr = rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_SELECTED_REGISTRAR, &sr, NULL);
-+
-+	if (psr && sr) {
-+		if (0)
-+			RTW_INFO("clear sr of non target bss:%s("MAC_FMT")\n"
-+				, pssid->Ssid, MAC_ARG(pnetwork->network.MacAddress));
-+		*psr = 0; /* clear sr */
-+		ret = 1;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+#define MAX_BSSINFO_LEN 1000
-+struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork)
-+{
-+	struct ieee80211_channel *notify_channel;
-+	struct cfg80211_bss *bss = NULL;
-+	/* struct ieee80211_supported_band *band;       */
-+	u16 channel;
-+	u32 freq;
-+	u64 notify_timestamp;
-+	u16 notify_capability;
-+	u16 notify_interval;
-+	u8 *notify_ie;
-+	size_t notify_ielen;
-+	s32 notify_signal;
-+	/* u8 buf[MAX_BSSINFO_LEN]; */
-+
-+	u8 *pbuf;
-+	size_t buf_size = MAX_BSSINFO_LEN;
-+	size_t len, bssinf_len = 0;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	unsigned short *fctrl;
-+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+
-+	struct wireless_dev *wdev = padapter->rtw_wdev;
-+	struct wiphy *wiphy = wdev->wiphy;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	pbuf = rtw_zmalloc(buf_size);
-+	if (pbuf == NULL) {
-+		RTW_INFO("%s pbuf allocate failed  !!\n", __FUNCTION__);
-+		return bss;
-+	}
-+
-+	/* RTW_INFO("%s\n", __func__); */
-+
-+	bssinf_len = pnetwork->network.IELength + sizeof(struct rtw_ieee80211_hdr_3addr);
-+	if (bssinf_len > buf_size) {
-+		RTW_INFO("%s IE Length too long > %zu byte\n", __FUNCTION__, buf_size);
-+		goto exit;
-+	}
-+
-+#ifndef CONFIG_WAPI_SUPPORT
-+	{
-+		u16 wapi_len = 0;
-+
-+		if (rtw_get_wapi_ie(pnetwork->network.IEs, pnetwork->network.IELength, NULL, &wapi_len) > 0) {
-+			if (wapi_len > 0) {
-+				RTW_INFO("%s, no support wapi!\n", __FUNCTION__);
-+				goto exit;
-+			}
-+		}
-+	}
-+#endif /* !CONFIG_WAPI_SUPPORT */
-+
-+	channel = pnetwork->network.Configuration.DSConfig;
-+	freq = rtw_ch2freq(channel);
-+	notify_channel = ieee80211_get_channel(wiphy, freq);
-+
-+	if (0)
-+		notify_timestamp = le64_to_cpu(*(u64 *)rtw_get_timestampe_from_ie(pnetwork->network.IEs));
-+	else
-+		notify_timestamp = rtw_get_systime_us();
-+
-+	notify_interval = le16_to_cpu(*(u16 *)rtw_get_beacon_interval_from_ie(pnetwork->network.IEs));
-+	notify_capability = le16_to_cpu(*(u16 *)rtw_get_capability_from_ie(pnetwork->network.IEs));
-+
-+	notify_ie = pnetwork->network.IEs + _FIXED_IE_LENGTH_;
-+	notify_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_;
-+
-+	/* We've set wiphy's signal_type as CFG80211_SIGNAL_TYPE_MBM: signal strength in mBm (100*dBm) */
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE &&
-+		is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) {
-+		notify_signal = 100 * translate_percentage_to_dbm(padapter->recvpriv.signal_strength); /* dbm */
-+	} else {
-+		notify_signal = 100 * translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength); /* dbm */
-+	}
-+
-+#if 0
-+	RTW_INFO("bssid: "MAC_FMT"\n", MAC_ARG(pnetwork->network.MacAddress));
-+	RTW_INFO("Channel: %d(%d)\n", channel, freq);
-+	RTW_INFO("Capability: %X\n", notify_capability);
-+	RTW_INFO("Beacon interval: %d\n", notify_interval);
-+	RTW_INFO("Signal: %d\n", notify_signal);
-+	RTW_INFO("notify_timestamp: %llu\n", notify_timestamp);
-+#endif
-+
-+	/* pbuf = buf; */
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pbuf;
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
-+	/* pmlmeext->mgnt_seq++; */
-+
-+	if (pnetwork->network.Reserved[0] == BSS_TYPE_BCN) { /* WIFI_BEACON */
-+		_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
-+		set_frame_sub_type(pbuf, WIFI_BEACON);
-+	} else {
-+		_rtw_memcpy(pwlanhdr->addr1, adapter_mac_addr(padapter), ETH_ALEN);
-+		set_frame_sub_type(pbuf, WIFI_PROBERSP);
-+	}
-+
-+	_rtw_memcpy(pwlanhdr->addr2, pnetwork->network.MacAddress, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, pnetwork->network.MacAddress, ETH_ALEN);
-+
-+
-+	/* pbuf += sizeof(struct rtw_ieee80211_hdr_3addr); */
-+	len = sizeof(struct rtw_ieee80211_hdr_3addr);
-+	_rtw_memcpy((pbuf + len), pnetwork->network.IEs, pnetwork->network.IELength);
-+	*((u64 *)(pbuf + len)) = cpu_to_le64(notify_timestamp);
-+
-+	len += pnetwork->network.IELength;
-+
-+	#if defined(CONFIG_P2P) && 0
-+	if(rtw_get_p2p_ie(pnetwork->network.IEs+12, pnetwork->network.IELength-12, NULL, NULL))
-+		RTW_INFO("%s, got p2p_ie\n", __func__);
-+	#endif
-+
-+#if 1
-+	bss = cfg80211_inform_bss_frame(wiphy, notify_channel, (struct ieee80211_mgmt *)pbuf,
-+					len, notify_signal, GFP_ATOMIC);
-+#else
-+
-+	bss = cfg80211_inform_bss(wiphy, notify_channel, (const u8 *)pnetwork->network.MacAddress,
-+		notify_timestamp, notify_capability, notify_interval, notify_ie,
-+		notify_ielen, notify_signal, GFP_ATOMIC/*GFP_KERNEL*/);
-+#endif
-+
-+	if (unlikely(!bss)) {
-+		RTW_INFO(FUNC_ADPT_FMT" bss NULL\n", FUNC_ADPT_ARG(padapter));
-+		goto exit;
-+	}
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 38))
-+#ifndef COMPAT_KERNEL_RELEASE
-+	/* patch for cfg80211, update beacon ies to information_elements */
-+	if (pnetwork->network.Reserved[0] == BSS_TYPE_BCN) { /* WIFI_BEACON */
-+
-+		if (bss->len_information_elements != bss->len_beacon_ies) {
-+			bss->information_elements = bss->beacon_ies;
-+			bss->len_information_elements =  bss->len_beacon_ies;
-+		}
-+	}
-+#endif /* COMPAT_KERNEL_RELEASE */
-+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 38) */
-+
-+#if 0
-+	{
-+		if (bss->information_elements == bss->proberesp_ies) {
-+			if (bss->len_information_elements !=  bss->len_proberesp_ies)
-+				RTW_INFO("error!, len_information_elements != bss->len_proberesp_ies\n");
-+		} else if (bss->len_information_elements <  bss->len_beacon_ies) {
-+			bss->information_elements = bss->beacon_ies;
-+			bss->len_information_elements =  bss->len_beacon_ies;
-+		}
-+	}
-+#endif
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
-+	cfg80211_put_bss(wiphy, bss);
-+#else
-+	cfg80211_put_bss(bss);
-+#endif
-+
-+exit:
-+	if (pbuf)
-+		rtw_mfree(pbuf, buf_size);
-+	return bss;
-+
-+}
-+
-+/*
-+	Check the given bss is valid by kernel API cfg80211_get_bss()
-+	@padapter : the given adapter
-+
-+	return _TRUE if bss is valid,  _FALSE for not found.
-+*/
-+int rtw_cfg80211_check_bss(_adapter *padapter)
-+{
-+	WLAN_BSSID_EX  *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network);
-+	struct cfg80211_bss *bss = NULL;
-+	struct ieee80211_channel *notify_channel = NULL;
-+	u32 freq;
-+
-+	if (!(pnetwork) || !(padapter->rtw_wdev))
-+		return _FALSE;
-+
-+	freq = rtw_ch2freq(pnetwork->Configuration.DSConfig);
-+	notify_channel = ieee80211_get_channel(padapter->rtw_wdev->wiphy, freq);
-+	bss = cfg80211_get_bss(padapter->rtw_wdev->wiphy, notify_channel,
-+			pnetwork->MacAddress, pnetwork->Ssid.Ssid,
-+			pnetwork->Ssid.SsidLength,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
-+			pnetwork->InfrastructureMode == Ndis802_11Infrastructure?IEEE80211_BSS_TYPE_ESS:IEEE80211_BSS_TYPE_IBSS,
-+			IEEE80211_PRIVACY(pnetwork->Privacy));
-+#else
-+			pnetwork->InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS, pnetwork->InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS);
-+#endif
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
-+	cfg80211_put_bss(padapter->rtw_wdev->wiphy, bss);
-+#else
-+	cfg80211_put_bss(bss);
-+#endif
-+
-+	return bss != NULL;
-+}
-+
-+void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct wlan_network  *cur_network = &(pmlmepriv->cur_network);
-+	struct wireless_dev *pwdev = padapter->rtw_wdev;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
-+	struct wiphy *wiphy = pwdev->wiphy;
-+	int freq = 2412;
-+	struct ieee80211_channel *notify_channel;
-+#endif
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+
-+	if (pwdev->iftype != NL80211_IFTYPE_ADHOC)
-+		return;
-+
-+	if (!rtw_cfg80211_check_bss(padapter)) {
-+		WLAN_BSSID_EX  *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network);
-+		struct wlan_network *scanned = pmlmepriv->cur_network_scanned;
-+
-+		if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) {
-+
-+			_rtw_memcpy(&cur_network->network, pnetwork, sizeof(WLAN_BSSID_EX));
-+			if (cur_network) {
-+				if (!rtw_cfg80211_inform_bss(padapter, cur_network))
-+					RTW_INFO(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter));
-+				else
-+					RTW_INFO(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter));
-+			} else {
-+				RTW_INFO("cur_network is not exist!!!\n");
-+				return ;
-+			}
-+		} else {
-+			if (scanned == NULL)
-+				rtw_warn_on(1);
-+
-+			if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE
-+				&& _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE
-+			) {
-+				if (!rtw_cfg80211_inform_bss(padapter, scanned))
-+					RTW_INFO(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter));
-+				else {
-+					/* RTW_INFO(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter)); */
-+				}
-+			} else {
-+				RTW_INFO("scanned & pnetwork compare fail\n");
-+				rtw_warn_on(1);
-+			}
-+		}
-+
-+		if (!rtw_cfg80211_check_bss(padapter))
-+			RTW_PRINT(FUNC_ADPT_FMT" BSS not found !!\n", FUNC_ADPT_ARG(padapter));
-+	}
-+	/* notify cfg80211 that device joined an IBSS */
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
-+	freq = rtw_ch2freq(cur_network->network.Configuration.DSConfig);
-+	if (1)
-+		RTW_INFO("chan: %d, freq: %d\n", cur_network->network.Configuration.DSConfig, freq);
-+	notify_channel = ieee80211_get_channel(wiphy, freq);
-+	cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, notify_channel, GFP_ATOMIC);
-+#else
-+	cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, GFP_ATOMIC);
-+#endif
-+}
-+
-+void rtw_cfg80211_indicate_connect(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct wlan_network  *cur_network = &(pmlmepriv->cur_network);
-+	struct wireless_dev *pwdev = padapter->rtw_wdev;
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+	_irqL irqL;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+#endif
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)
-+	struct cfg80211_roam_info roam_info ={};
-+#endif
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+	if (pwdev->iftype != NL80211_IFTYPE_STATION
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+		&& pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT
-+		#endif
-+	)
-+		return;
-+
-+	if (!MLME_IS_STA(padapter))
-+		return;
-+
-+#ifdef CONFIG_P2P
-+	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
-+		#if !RTW_P2P_GROUP_INTERFACE
-+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
-+			rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
-+			rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT);
-+			rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
-+			RTW_INFO("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo));
-+		}
-+		#endif
-+	}
-+#endif /* CONFIG_P2P */
-+
-+	if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE) {
-+		WLAN_BSSID_EX  *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network);
-+		struct wlan_network *scanned = pmlmepriv->cur_network_scanned;
-+
-+		/* RTW_INFO(FUNC_ADPT_FMT" BSS not found\n", FUNC_ADPT_ARG(padapter)); */
-+
-+		if (scanned == NULL) {
-+			rtw_warn_on(1);
-+			goto check_bss;
-+		}
-+
-+		if (_rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE
-+			&& _rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE
-+		) {
-+			if (!rtw_cfg80211_inform_bss(padapter, scanned))
-+				RTW_INFO(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter));
-+			else {
-+				/* RTW_INFO(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter)); */
-+			}
-+		} else {
-+			RTW_INFO("scanned: %s("MAC_FMT"), cur: %s("MAC_FMT")\n",
-+				scanned->network.Ssid.Ssid, MAC_ARG(scanned->network.MacAddress),
-+				pnetwork->Ssid.Ssid, MAC_ARG(pnetwork->MacAddress)
-+			);
-+			rtw_warn_on(1);
-+		}
-+	}
-+
-+check_bss:
-+	if (!rtw_cfg80211_check_bss(padapter))
-+		RTW_PRINT(FUNC_ADPT_FMT" BSS not found !!\n", FUNC_ADPT_ARG(padapter));
-+
-+	_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
-+
-+	if (rtw_to_roam(padapter) > 0) {
-+		#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE)
-+		struct wiphy *wiphy = pwdev->wiphy;
-+		struct ieee80211_channel *notify_channel;
-+		u32 freq;
-+		u16 channel = cur_network->network.Configuration.DSConfig;
-+
-+		freq = rtw_ch2freq(channel);
-+		notify_channel = ieee80211_get_channel(wiphy, freq);
-+		#endif
-+
-+		#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)
-+		roam_info.bssid = cur_network->network.MacAddress;
-+		roam_info.req_ie = pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2;
-+		roam_info.req_ie_len = pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2;
-+		roam_info.resp_ie = pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6;
-+		roam_info.resp_ie_len = pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6;
-+
-+		cfg80211_roamed(padapter->pnetdev, &roam_info, GFP_ATOMIC);
-+		#else
-+		cfg80211_roamed(padapter->pnetdev
-+			#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE)
-+			, notify_channel
-+			#endif
-+			, cur_network->network.MacAddress
-+			, pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2
-+			, pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2
-+			, pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6
-+			, pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6
-+			, GFP_ATOMIC);
-+		#endif /*LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)*/
-+
-+		RTW_INFO(FUNC_ADPT_FMT" call cfg80211_roamed\n", FUNC_ADPT_ARG(padapter));
-+
-+#ifdef CONFIG_RTW_80211R
-+		if (rtw_ft_roam(padapter))
-+			rtw_ft_set_status(padapter, RTW_FT_ASSOCIATED_STA);
-+#endif
-+	} else {
-+		#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE)
-+		RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state);
-+		#endif
-+
-+		if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE)
-+			rtw_cfg80211_connect_result(pwdev, cur_network->network.MacAddress
-+				, pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2
-+				, pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2
-+				, pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6
-+				, pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6
-+				, WLAN_STATUS_SUCCESS, GFP_ATOMIC);
-+		#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE)
-+		RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state);
-+		#endif
-+	}
-+
-+	rtw_wdev_free_connect_req(pwdev_priv);
-+
-+	_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
-+}
-+
-+void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated)
-+{
-+	struct wireless_dev *pwdev = padapter->rtw_wdev;
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+	_irqL irqL;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+#endif
-+
-+	RTW_INFO(FUNC_ADPT_FMT" ,reason = %d\n", FUNC_ADPT_ARG(padapter), reason);
-+
-+	/*always replace privated definitions with wifi reserved value 0*/
-+	if (WLAN_REASON_IS_PRIVATE(reason))
-+		reason = 0;
-+
-+	if (pwdev->iftype != NL80211_IFTYPE_STATION
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+		&& pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT
-+		#endif
-+	)
-+		return;
-+
-+	if (!MLME_IS_STA(padapter))
-+		return;
-+
-+#ifdef CONFIG_P2P
-+	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
-+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
-+			rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
-+
-+			#if RTW_P2P_GROUP_INTERFACE
-+			#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+			if (pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT)
-+			#endif
-+			#endif
-+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
-+
-+			RTW_INFO("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo));
-+		}
-+	}
-+#endif /* CONFIG_P2P */
-+
-+	_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
-+
-+	if (padapter->ndev_unregistering || !rtw_wdev_not_indic_disco(pwdev_priv)) {
-+		#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE)
-+		RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state);
-+
-+		if (pwdev->sme_state == CFG80211_SME_CONNECTING) {
-+			RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result, reason:%d\n", FUNC_ADPT_ARG(padapter), reason);
-+			rtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0,
-+				reason?reason:WLAN_STATUS_UNSPECIFIED_FAILURE,
-+				GFP_ATOMIC);
-+		} else if (pwdev->sme_state == CFG80211_SME_CONNECTED) {
-+			RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected, reason:%d\n", FUNC_ADPT_ARG(padapter), reason);
-+			rtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC);
-+		}
-+
-+		RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state);
-+		#else
-+		if (pwdev_priv->connect_req) {
-+			RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result, reason:%d\n", FUNC_ADPT_ARG(padapter), reason);
-+			rtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0,
-+				reason?reason:WLAN_STATUS_UNSPECIFIED_FAILURE,
-+				GFP_ATOMIC);
-+		} else {
-+			RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected, reason:%d\n", FUNC_ADPT_ARG(padapter), reason);
-+			rtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC);
-+		}
-+		#endif
-+	}
-+
-+	rtw_wdev_free_connect_req(pwdev_priv);
-+
-+	_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
-+}
-+
-+
-+#ifdef CONFIG_AP_MODE
-+static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_param *param)
-+{
-+	int ret = 0;
-+	u32 wep_key_idx, wep_key_len;
-+	struct sta_info *psta = NULL, *pbcmc_sta = NULL;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	param->u.crypt.err = 0;
-+	param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
-+
-+	if (is_broadcast_mac_addr(param->sta_addr)) {
-+		if (param->u.crypt.idx >= WEP_KEYS
-+			#ifdef CONFIG_IEEE80211W
-+			&& param->u.crypt.idx > BIP_MAX_KEYID
-+			#endif
-+		) {
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+	} else {
-+		psta = rtw_get_stainfo(pstapriv, param->sta_addr);
-+		if (!psta) {
-+			ret = -EINVAL;
-+			RTW_INFO(FUNC_ADPT_FMT", sta "MAC_FMT" not found\n"
-+				, FUNC_ADPT_ARG(padapter), MAC_ARG(param->sta_addr));
-+			goto exit;
-+		}
-+	}
-+
-+	if (strcmp(param->u.crypt.alg, "none") == 0 && (psta == NULL)) {
-+		/* todo:clear default encryption keys */
-+
-+		RTW_INFO("clear default encryption keys, keyid=%d\n", param->u.crypt.idx);
-+
-+		goto exit;
-+	}
-+
-+
-+	if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta == NULL)) {
-+		RTW_INFO("r871x_set_encryption, crypt.alg = WEP\n");
-+
-+		wep_key_idx = param->u.crypt.idx;
-+		wep_key_len = param->u.crypt.key_len;
-+
-+		RTW_INFO("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len);
-+
-+		if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+
-+		if (wep_key_len > 0)
-+			wep_key_len = wep_key_len <= 5 ? 5 : 13;
-+
-+		if (psecuritypriv->bWepDefaultKeyIdxSet == 0) {
-+			/* wep default key has not been set, so use this key index as default key. */
-+
-+			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
-+			psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+			psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
-+			psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
-+
-+			if (wep_key_len == 13) {
-+				psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
-+				psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
-+			}
-+
-+			psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
-+		}
-+
-+		_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len);
-+
-+		psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len;
-+
-+		rtw_ap_set_wep_key(padapter, param->u.crypt.key, wep_key_len, wep_key_idx, 1);
-+
-+		goto exit;
-+
-+	}
-+
-+	if (!psta) { /* group key */
-+		if (param->u.crypt.set_tx == 0) { /* group key, TX only */
-+			if (strcmp(param->u.crypt.alg, "WEP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set WEP TX GTK idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+				psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
-+				if (param->u.crypt.key_len == 13)
-+					psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
-+
-+			} else if (strcmp(param->u.crypt.alg, "TKIP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set TKIP TX GTK idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+				psecuritypriv->dot118021XGrpPrivacy = _TKIP_;
-+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+				/* set mic key */
-+				_rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
-+				_rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
-+				psecuritypriv->busetkipkey = _TRUE;
-+
-+			} else if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set CCMP TX GTK idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+				psecuritypriv->dot118021XGrpPrivacy = _AES_;
-+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+
-+			} else if (strcmp(param->u.crypt.alg, "GCMP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set GCMP TX GTK idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+				psecuritypriv->dot118021XGrpPrivacy = _GCMP_;
-+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,
-+					param->u.crypt.key,
-+					(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+
-+			} else if (strcmp(param->u.crypt.alg, "GCMP_256") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set GCMP_256 TX GTK idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+				psecuritypriv->dot118021XGrpPrivacy = _GCMP_256_;
-+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,
-+					param->u.crypt.key,
-+					(param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
-+
-+			} else if (strcmp(param->u.crypt.alg, "CCMP_256") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set CCMP_256 TX GTK idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+				psecuritypriv->dot118021XGrpPrivacy = _CCMP_256_;
-+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,
-+					param->u.crypt.key,
-+					(param->u.crypt.key_len > 32 ? 32: param->u.crypt.key_len));
-+
-+			#ifdef CONFIG_IEEE80211W
-+			} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
-+				psecuritypriv->dot11wCipher = _BIP_CMAC_128_;
-+				RTW_INFO(FUNC_ADPT_FMT" set TX CMAC-128 IGTK idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+				_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+				padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx;
-+				psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+				padapter->securitypriv.binstallBIPkey = _TRUE;
-+				goto exit;
-+			} else if (strcmp(param->u.crypt.alg, "BIP_GMAC_128") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set TX GMAC-128 IGTK idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+				psecuritypriv->dot11wCipher = _BIP_GMAC_128_;
-+				_rtw_memcpy(psecuritypriv->dot11wBIPKey[param->u.crypt.idx].skey,
-+					param->u.crypt.key, param->u.crypt.key_len);
-+				psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
-+				psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+				psecuritypriv->binstallBIPkey = _TRUE;
-+				goto exit;
-+			} else if (strcmp(param->u.crypt.alg, "BIP_GMAC_256") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set TX GMAC-256 IGTK idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+				psecuritypriv->dot11wCipher = _BIP_GMAC_256_;
-+				_rtw_memcpy(psecuritypriv->dot11wBIPKey[param->u.crypt.idx].skey,
-+					param->u.crypt.key, param->u.crypt.key_len);
-+				padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx;
-+				psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+				padapter->securitypriv.binstallBIPkey = _TRUE;
-+				goto exit;
-+			} else if (strcmp(param->u.crypt.alg, "BIP_CMAC_256") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set TX CMAC-256 IGTK idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+				psecuritypriv->dot11wCipher = _BIP_CMAC_256_;
-+				_rtw_memcpy(psecuritypriv->dot11wBIPKey[param->u.crypt.idx].skey,
-+					param->u.crypt.key, param->u.crypt.key_len);
-+				psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
-+				psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+				psecuritypriv->binstallBIPkey = _TRUE;
-+				goto exit;
-+			#endif /* CONFIG_IEEE80211W */
-+
-+			} else if (strcmp(param->u.crypt.alg, "none") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" clear group key, idx:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx);
-+				psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
-+			} else {
-+				RTW_WARN(FUNC_ADPT_FMT" set group key, not support\n"
-+					, FUNC_ADPT_ARG(padapter));
-+				goto exit;
-+			}
-+
-+			psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx;
-+			pbcmc_sta = rtw_get_bcmc_stainfo(padapter);
-+			if (pbcmc_sta) {
-+				pbcmc_sta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+				pbcmc_sta->ieee8021x_blocked = _FALSE;
-+				pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy			 */
-+			}
-+			psecuritypriv->binstallGrpkey = _TRUE;
-+			psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */
-+
-+			rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx);
-+		}
-+
-+		goto exit;
-+
-+	}
-+
-+	if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) { /* psk/802_1x */
-+		if (param->u.crypt.set_tx == 1) {
-+			/* pairwise key */
-+			if (param->u.crypt.key_len == 32)
-+				_rtw_memcpy(psta->dot118021x_UncstKey.skey,
-+						param->u.crypt.key,
-+						(param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
-+			else
-+				_rtw_memcpy(psta->dot118021x_UncstKey.skey,
-+						param->u.crypt.key,
-+						(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+
-+			if (strcmp(param->u.crypt.alg, "WEP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set WEP PTK of "MAC_FMT" idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx, param->u.crypt.key_len);
-+				psta->dot118021XPrivacy = _WEP40_;
-+				if (param->u.crypt.key_len == 13)
-+					psta->dot118021XPrivacy = _WEP104_;
-+
-+			} else if (strcmp(param->u.crypt.alg, "TKIP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set TKIP PTK of "MAC_FMT" idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx, param->u.crypt.key_len);
-+				psta->dot118021XPrivacy = _TKIP_;
-+				/* set mic key */
-+				_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
-+				_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
-+				psecuritypriv->busetkipkey = _TRUE;
-+
-+			} else if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set CCMP PTK of "MAC_FMT" idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx, param->u.crypt.key_len);
-+				psta->dot118021XPrivacy = _AES_;
-+
-+			} else if (strcmp(param->u.crypt.alg, "GCMP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set GCMP PTK of "MAC_FMT" idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx, param->u.crypt.key_len);
-+				psta->dot118021XPrivacy = _GCMP_;
-+
-+			} else if (strcmp(param->u.crypt.alg, "GCMP_256") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set GCMP_256 PTK of "MAC_FMT" idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx, param->u.crypt.key_len);
-+				psta->dot118021XPrivacy = _GCMP_256_;
-+
-+			} else if (strcmp(param->u.crypt.alg, "CCMP_256") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set CCMP_256 PTK of "MAC_FMT" idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx, param->u.crypt.key_len);
-+				psta->dot118021XPrivacy = _CCMP_256_;
-+
-+			} else if (strcmp(param->u.crypt.alg, "none") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" clear pairwise key of "MAC_FMT" idx:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx);
-+				psta->dot118021XPrivacy = _NO_PRIVACY_;
-+			} else {
-+				RTW_WARN(FUNC_ADPT_FMT" set pairwise key of "MAC_FMT", not support\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
-+				goto exit;
-+			}
-+
-+			psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+			psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+			psta->ieee8021x_blocked = _FALSE;
-+
-+			if (psta->dot118021XPrivacy != _NO_PRIVACY_) {
-+				psta->bpairwise_key_installed = _TRUE;
-+
-+				/* WPA2 key-handshake has completed */
-+				if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK)
-+					psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE);
-+			}
-+
-+			rtw_ap_set_pairwise_key(padapter, psta);
-+		} else {
-+			/* peer's group key, RX only */
-+			#ifdef CONFIG_RTW_MESH
-+			if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set CCMP GTK of "MAC_FMT", idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx, param->u.crypt.key_len);
-+				psta->group_privacy = _AES_;
-+				_rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+				psta->gtk_bmp |= BIT(param->u.crypt.idx);
-+				psta->gtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
-+
-+			} else if (strcmp(param->u.crypt.alg, "GCMP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set GCMP GTK of "MAC_FMT", idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx, param->u.crypt.key_len);
-+				psta->group_privacy = _GCMP_;
-+				_rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+				psta->gtk_bmp |= BIT(param->u.crypt.idx);
-+				psta->gtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
-+
-+			} else if (strcmp(param->u.crypt.alg, "CCMP_256") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set CCMP_256 GTK of "MAC_FMT", idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx, param->u.crypt.key_len);
-+				psta->group_privacy = _CCMP_256_;
-+				_rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
-+				psta->gtk_bmp |= BIT(param->u.crypt.idx);
-+				psta->gtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
-+
-+			} else if (strcmp(param->u.crypt.alg, "GCMP_256") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set GCMP_256 GTK of "MAC_FMT", idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx, param->u.crypt.key_len);
-+				psta->group_privacy = _GCMP_256_;
-+				_rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
-+				psta->gtk_bmp |= BIT(param->u.crypt.idx);
-+				psta->gtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
-+
-+			#ifdef CONFIG_IEEE80211W
-+			} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set CMAC-128 IGTK of "MAC_FMT", idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx, param->u.crypt.key_len);
-+				psta->dot11wCipher = _BIP_CMAC_128_;
-+				_rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+				psta->igtk_bmp |= BIT(param->u.crypt.idx);
-+				psta->igtk_id = param->u.crypt.idx;
-+				psta->igtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
-+				goto exit;
-+
-+			} else if (strcmp(param->u.crypt.alg, "BIP_GMAC_128") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set GMAC-128 IGTK of "MAC_FMT", idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx, param->u.crypt.key_len);
-+				psta->dot11wCipher = _BIP_GMAC_128_;
-+				_rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+				psta->igtk_bmp |= BIT(param->u.crypt.idx);
-+				psta->igtk_id = param->u.crypt.idx;
-+				psta->igtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
-+				goto exit;
-+
-+			} else if (strcmp(param->u.crypt.alg, "BIP_CMAC_256") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set CMAC-256 IGTK of "MAC_FMT", idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx, param->u.crypt.key_len);
-+				psta->dot11wCipher = _BIP_CMAC_256_;
-+				_rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
-+				psta->igtk_bmp |= BIT(param->u.crypt.idx);
-+				psta->igtk_id = param->u.crypt.idx;
-+				psta->igtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
-+				goto exit;
-+
-+			} else if (strcmp(param->u.crypt.alg, "BIP_GMAC_256") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set GMAC-256 IGTK of "MAC_FMT", idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx, param->u.crypt.key_len);
-+				psta->dot11wCipher = _BIP_GMAC_256_;
-+				_rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
-+				psta->igtk_bmp |= BIT(param->u.crypt.idx);
-+				psta->igtk_id = param->u.crypt.idx;
-+				psta->igtk_pn.val = RTW_GET_LE64(param->u.crypt.seq);
-+				goto exit;
-+			#endif /* CONFIG_IEEE80211W */
-+
-+			} else if (strcmp(param->u.crypt.alg, "none") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" clear group key of "MAC_FMT", idx:%u\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+					, param->u.crypt.idx);
-+				psta->group_privacy = _NO_PRIVACY_;
-+				psta->gtk_bmp &= ~BIT(param->u.crypt.idx);
-+			} else
-+			#endif /* CONFIG_RTW_MESH */
-+			{
-+				RTW_WARN(FUNC_ADPT_FMT" set group key of "MAC_FMT", not support\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
-+				goto exit;
-+			}
-+
-+			#ifdef CONFIG_RTW_MESH
-+			rtw_ap_set_sta_key(padapter, psta->cmn.mac_addr, psta->group_privacy
-+				, param->u.crypt.key, param->u.crypt.idx, 1);
-+			#endif
-+		}
-+
-+	}
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param *param)
-+{
-+	int ret = 0;
-+	u32 wep_key_idx, wep_key_len;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
-+#endif /* CONFIG_P2P */
-+
-+	RTW_INFO("%s\n", __func__);
-+
-+	param->u.crypt.err = 0;
-+	param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
-+
-+	if (is_broadcast_mac_addr(param->sta_addr)) {
-+		if (param->u.crypt.idx >= WEP_KEYS
-+			#ifdef CONFIG_IEEE80211W
-+			&& param->u.crypt.idx > BIP_MAX_KEYID
-+			#endif
-+		) {
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+	} else {
-+#ifdef CONFIG_WAPI_SUPPORT
-+		if (strcmp(param->u.crypt.alg, "SMS4"))
-+#endif
-+		{
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+	}
-+
-+	if (strcmp(param->u.crypt.alg, "WEP") == 0) {
-+		RTW_INFO("wpa_set_encryption, crypt.alg = WEP\n");
-+
-+		wep_key_idx = param->u.crypt.idx;
-+		wep_key_len = param->u.crypt.key_len;
-+
-+		if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+
-+		if (psecuritypriv->bWepDefaultKeyIdxSet == 0) {
-+			/* wep default key has not been set, so use this key index as default key. */
-+
-+			wep_key_len = wep_key_len <= 5 ? 5 : 13;
-+
-+			psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+			psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
-+			psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
-+
-+			if (wep_key_len == 13) {
-+				psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
-+				psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
-+			}
-+
-+			psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
-+		}
-+
-+		_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len);
-+
-+		psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len;
-+
-+		rtw_set_key(padapter, psecuritypriv, wep_key_idx, 0, _TRUE);
-+
-+		goto exit;
-+	}
-+
-+	if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802_1x */
-+		struct sta_info *psta, *pbcmc_sta;
-+		struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+		/* RTW_INFO("%s, : dot11AuthAlgrthm == dot11AuthAlgrthm_8021X\n", __func__); */
-+
-+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) { /* sta mode */
-+#ifdef CONFIG_RTW_80211R
-+			if (rtw_ft_roam(padapter))
-+				psta = rtw_get_stainfo(pstapriv, pmlmepriv->assoc_bssid);
-+			else
-+#endif
-+				psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
-+			if (psta == NULL) {
-+				/* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */
-+				RTW_INFO("%s, : Obtain Sta_info fail\n", __func__);
-+			} else {
-+				/* Jeff: don't disable ieee8021x_blocked while clearing key */
-+				if (strcmp(param->u.crypt.alg, "none") != 0)
-+					psta->ieee8021x_blocked = _FALSE;
-+
-+				if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||
-+				    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))
-+					psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
-+
-+				if (param->u.crypt.set_tx == 1) { /* pairwise key */
-+					RTW_INFO(FUNC_ADPT_FMT" set %s PTK idx:%u, len:%u\n"
-+						, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);
-+
-+					if (strcmp(param->u.crypt.alg, "GCMP_256") == 0
-+						|| strcmp(param->u.crypt.alg, "CCMP_256") == 0) {
-+						_rtw_memcpy(psta->dot118021x_UncstKey.skey,
-+							param->u.crypt.key,
-+							((param->u.crypt.key_len > 32) ?
-+								32 : param->u.crypt.key_len));
-+					} else
-+						_rtw_memcpy(psta->dot118021x_UncstKey.skey,
-+							param->u.crypt.key,
-+							(param->u.crypt.key_len > 16 ?
-+								16 : param->u.crypt.key_len));
-+
-+					if (strcmp(param->u.crypt.alg, "TKIP") == 0) { /* set mic key */
-+						_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
-+						_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
-+						padapter->securitypriv.busetkipkey = _FALSE;
-+					}
-+					psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+					psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+					psta->bpairwise_key_installed = _TRUE;
-+					#ifdef CONFIG_RTW_80211R
-+					psta->ft_pairwise_key_installed = _TRUE;
-+					#endif
-+					rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE);
-+
-+				} else { /* group key */
-+					if (strcmp(param->u.crypt.alg, "TKIP") == 0
-+						|| strcmp(param->u.crypt.alg, "CCMP") == 0
-+						|| strcmp(param->u.crypt.alg, "GCMP") == 0) {
-+						RTW_INFO(FUNC_ADPT_FMT" set %s GTK idx:%u, len:%u\n"
-+							, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);
-+						_rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey,
-+							param->u.crypt.key,
-+							(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+						_rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
-+						_rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
-+						padapter->securitypriv.binstallGrpkey = _TRUE;
-+						if (param->u.crypt.idx < 4) 
-+							_rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], param->u.crypt.seq, 8);							
-+						padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx;
-+						rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE);
-+					} else if (strcmp(param->u.crypt.alg, "GCMP_256") == 0
-+						|| strcmp(param->u.crypt.alg, "CCMP_256") == 0) {
-+						RTW_INFO(FUNC_ADPT_FMT" set %s GTK idx:%u, len:%u\n"
-+							, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);
-+						_rtw_memcpy(
-+							padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey,
-+							param->u.crypt.key,
-+							(param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
-+						padapter->securitypriv.binstallGrpkey = _TRUE;
-+						padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx;
-+						rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE);
-+					#ifdef CONFIG_IEEE80211W
-+					} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
-+						psecuritypriv->dot11wCipher = _BIP_CMAC_128_;
-+						RTW_INFO(FUNC_ADPT_FMT" set CMAC-128 IGTK idx:%u, len:%u\n"
-+							, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+						_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey,
-+							param->u.crypt.key,
-+							(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+						psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
-+						psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+						psecuritypriv->binstallBIPkey = _TRUE;
-+					} else if (strcmp(param->u.crypt.alg, "BIP_GMAC_128") == 0) {
-+						psecuritypriv->dot11wCipher = _BIP_GMAC_128_;
-+						RTW_INFO(FUNC_ADPT_FMT" set GMAC-128 IGTK idx:%u, len:%u\n"
-+							, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+						_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey,
-+							param->u.crypt.key,
-+							(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+						psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
-+						psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+						psecuritypriv->binstallBIPkey = _TRUE;
-+					} else if (strcmp(param->u.crypt.alg, "BIP_GMAC_256") == 0) {
-+						psecuritypriv->dot11wCipher = _BIP_GMAC_256_;
-+						RTW_INFO(FUNC_ADPT_FMT" set GMAC-256 IGTK idx:%u, len:%u\n"
-+							, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+						_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey,
-+							param->u.crypt.key,
-+							(param->u.crypt.key_len > 32 ? 32 : param->u.crypt.key_len));
-+						psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
-+						psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+						psecuritypriv->binstallBIPkey = _TRUE;
-+					} else if (strcmp(param->u.crypt.alg, "BIP_CMAC_256") == 0) {
-+						psecuritypriv->dot11wCipher = _BIP_CMAC_256_;
-+						RTW_INFO(FUNC_ADPT_FMT" set CMAC-256 IGTK idx:%u, len:%u\n"
-+							, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+						_rtw_memcpy(psecuritypriv->dot11wBIPKey[param->u.crypt.idx].skey,
-+							param->u.crypt.key, param->u.crypt.key_len);
-+						psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
-+						psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+						psecuritypriv->binstallBIPkey = _TRUE;
-+					#endif /* CONFIG_IEEE80211W */
-+
-+					}
-+
-+#ifdef CONFIG_P2P
-+					if (pwdinfo->driver_interface == DRIVER_CFG80211) {
-+						if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
-+							rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE);
-+					}
-+#endif /* CONFIG_P2P */
-+
-+					/* WPA/WPA2 key-handshake has completed */
-+					clr_fwstate(pmlmepriv, WIFI_UNDER_KEY_HANDSHAKE);
-+
-+				}
-+			}
-+
-+			pbcmc_sta = rtw_get_bcmc_stainfo(padapter);
-+			if (pbcmc_sta == NULL) {
-+				/* DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null\n")); */
-+			} else {
-+				/* Jeff: don't disable ieee8021x_blocked while clearing key */
-+				if (strcmp(param->u.crypt.alg, "none") != 0)
-+					pbcmc_sta->ieee8021x_blocked = _FALSE;
-+
-+				if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||
-+				    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))
-+					pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
-+			}
-+		} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { /* adhoc mode */
-+		}
-+	}
-+
-+	#ifdef CONFIG_WAPI_SUPPORT
-+	if (strcmp(param->u.crypt.alg, "SMS4") == 0)
-+		rtw_wapi_set_set_encryption(padapter, param);
-+	#endif
-+
-+exit:
-+
-+	RTW_INFO("%s, ret=%d\n", __func__, ret);
-+
-+
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev
-+	, u8 key_index
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+	, bool pairwise
-+#endif
-+	, const u8 *mac_addr, struct key_params *params)
-+{
-+	char *alg_name;
-+	u32 param_len;
-+	struct ieee_param *param = NULL;
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct wireless_dev *rtw_wdev = padapter->rtw_wdev;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+#ifdef CONFIG_TDLS
-+	struct sta_info *ptdls_sta;
-+#endif /* CONFIG_TDLS */
-+
-+	if (mac_addr)
-+		RTW_INFO(FUNC_NDEV_FMT" adding key for %pM\n", FUNC_NDEV_ARG(ndev), mac_addr);
-+	RTW_INFO(FUNC_NDEV_FMT" cipher=0x%x\n", FUNC_NDEV_ARG(ndev), params->cipher);
-+	RTW_INFO(FUNC_NDEV_FMT" key_len=%d, key_index=%d\n", FUNC_NDEV_ARG(ndev), params->key_len, key_index);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+	RTW_INFO(FUNC_NDEV_FMT" pairwise=%d\n", FUNC_NDEV_ARG(ndev), pairwise);
-+#endif
-+
-+	if (rtw_cfg80211_sync_iftype(padapter) != _SUCCESS) {
-+		ret = -ENOTSUPP;
-+		goto addkey_end;
-+	}
-+
-+	param_len = sizeof(struct ieee_param) + params->key_len;
-+	param = rtw_malloc(param_len);
-+	if (param == NULL)
-+		return -1;
-+
-+	_rtw_memset(param, 0, param_len);
-+
-+	param->cmd = IEEE_CMD_SET_ENCRYPTION;
-+	_rtw_memset(param->sta_addr, 0xff, ETH_ALEN);
-+
-+	switch (params->cipher) {
-+	case IW_AUTH_CIPHER_NONE:
-+		/* todo: remove key */
-+		/* remove = 1;	 */
-+		alg_name = "none";
-+		break;
-+	case WLAN_CIPHER_SUITE_WEP40:
-+	case WLAN_CIPHER_SUITE_WEP104:
-+		alg_name = "WEP";
-+		break;
-+	case WLAN_CIPHER_SUITE_TKIP:
-+		alg_name = "TKIP";
-+		break;
-+	case WLAN_CIPHER_SUITE_CCMP:
-+		alg_name = "CCMP";
-+		break;
-+	case WIFI_CIPHER_SUITE_GCMP:
-+		alg_name = "GCMP";
-+		break;
-+	case WIFI_CIPHER_SUITE_GCMP_256:
-+		alg_name = "GCMP_256";
-+		break;
-+	case WIFI_CIPHER_SUITE_CCMP_256:
-+		alg_name = "CCMP_256";
-+		break;
-+#ifdef CONFIG_IEEE80211W
-+	case WLAN_CIPHER_SUITE_AES_CMAC:
-+		alg_name = "BIP";
-+		break;
-+	case WIFI_CIPHER_SUITE_BIP_GMAC_128:
-+		alg_name = "BIP_GMAC_128";
-+		break;
-+	case WIFI_CIPHER_SUITE_BIP_GMAC_256:
-+		alg_name = "BIP_GMAC_256";
-+		break;
-+	case WIFI_CIPHER_SUITE_BIP_CMAC_256:
-+		alg_name = "BIP_CMAC_256";
-+		break;
-+#endif /* CONFIG_IEEE80211W */
-+#ifdef CONFIG_WAPI_SUPPORT
-+	case WLAN_CIPHER_SUITE_SMS4:
-+		alg_name = "SMS4";
-+		if (pairwise == NL80211_KEYTYPE_PAIRWISE) {
-+			if (key_index != 0 && key_index != 1) {
-+				ret = -ENOTSUPP;
-+				goto addkey_end;
-+			}
-+			_rtw_memcpy((void *)param->sta_addr, (void *)mac_addr, ETH_ALEN);
-+		} else
-+			RTW_INFO("mac_addr is null\n");
-+		RTW_INFO("rtw_wx_set_enc_ext: SMS4 case\n");
-+		break;
-+#endif
-+
-+	default:
-+		ret = -ENOTSUPP;
-+		goto addkey_end;
-+	}
-+
-+	strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN);
-+
-+
-+	if (!mac_addr || is_broadcast_ether_addr(mac_addr)
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+		|| !pairwise
-+		#endif
-+	) {
-+		param->u.crypt.set_tx = 0; /* for wpa/wpa2 group key */
-+	} else {
-+		param->u.crypt.set_tx = 1; /* for wpa/wpa2 pairwise key */
-+	}
-+
-+	param->u.crypt.idx = key_index;
-+
-+	if (params->seq_len && params->seq) {
-+		_rtw_memcpy(param->u.crypt.seq, (u8 *)params->seq, params->seq_len);
-+		RTW_INFO(FUNC_NDEV_FMT" seq_len:%u, seq:0x%llx\n", FUNC_NDEV_ARG(ndev)
-+			, params->seq_len, RTW_GET_LE64(param->u.crypt.seq));
-+	}
-+
-+	if (params->key_len && params->key) {
-+		param->u.crypt.key_len = params->key_len;
-+		_rtw_memcpy(param->u.crypt.key, (u8 *)params->key, params->key_len);
-+	}
-+
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
-+#ifdef CONFIG_TDLS
-+		if (rtw_tdls_is_driver_setup(padapter) == _FALSE && mac_addr) {
-+			ptdls_sta = rtw_get_stainfo(&padapter->stapriv, (void *)mac_addr);
-+			if (ptdls_sta != NULL && ptdls_sta->tdls_sta_state) {
-+				_rtw_memcpy(ptdls_sta->tpk.tk, params->key, params->key_len);
-+				rtw_tdls_set_key(padapter, ptdls_sta);
-+				goto addkey_end;
-+			}
-+		}
-+#endif /* CONFIG_TDLS */
-+		ret = rtw_cfg80211_set_encryption(ndev, param);
-+	} else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
-+#ifdef CONFIG_AP_MODE
-+		if (mac_addr)
-+			_rtw_memcpy(param->sta_addr, (void *)mac_addr, ETH_ALEN);
-+
-+		ret = rtw_cfg80211_ap_set_encryption(ndev, param);
-+#endif
-+	} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE
-+		|| check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE
-+	) {
-+		/* RTW_INFO("@@@@@@@@@@ fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype); */
-+		ret = rtw_cfg80211_set_encryption(ndev, param);
-+	} else
-+		RTW_INFO("error! fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype);
-+
-+
-+addkey_end:
-+	if (param)
-+		rtw_mfree(param, param_len);
-+
-+	return ret;
-+
-+}
-+
-+static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev
-+	, u8 keyid
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+	, bool pairwise
-+#endif
-+	, const u8 *mac_addr, void *cookie
-+	, void (*callback)(void *cookie, struct key_params *))
-+{
-+#define GET_KEY_PARAM_FMT_S " keyid=%d"
-+#define GET_KEY_PARAM_ARG_S , keyid
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+	#define GET_KEY_PARAM_FMT_2_6_37 ", pairwise=%d"
-+	#define GET_KEY_PARAM_ARG_2_6_37 , pairwise
-+#else
-+	#define GET_KEY_PARAM_FMT_2_6_37 ""
-+	#define GET_KEY_PARAM_ARG_2_6_37
-+#endif
-+#define GET_KEY_PARAM_FMT_E ", addr=%pM"
-+#define GET_KEY_PARAM_ARG_E , mac_addr
-+
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct security_priv *sec = &adapter->securitypriv;
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct sta_info *sta = NULL;
-+	u32 cipher = _NO_PRIVACY_;
-+	union Keytype *key = NULL;
-+	u8 key_len = 0;
-+	u64 *pn = NULL;
-+	u8 pn_len = 0;
-+	u8 pn_val[8] = {0};
-+
-+	struct key_params params;
-+	int ret = -ENOENT;
-+
-+	if (keyid >= WEP_KEYS
-+		#ifdef CONFIG_IEEE80211W
-+		&& keyid > BIP_MAX_KEYID
-+		#endif
-+	)
-+		goto exit;
-+
-+	if (!mac_addr || is_broadcast_ether_addr(mac_addr)
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+		|| (MLME_IS_STA(adapter) && !pairwise)
-+		#endif
-+	) {	
-+		/* WEP key, TX GTK/IGTK, RX GTK/IGTK(for STA mode) */
-+		if (is_wep_enc(sec->dot118021XGrpPrivacy)) {
-+			if (keyid >= WEP_KEYS)
-+				goto exit;
-+			if (!(sec->key_mask & BIT(keyid)))
-+				goto exit;
-+			cipher = sec->dot118021XGrpPrivacy;
-+			key = &sec->dot11DefKey[keyid];
-+		} else {
-+			if (keyid < WEP_KEYS) {
-+				if (sec->binstallGrpkey != _TRUE)
-+					goto exit;
-+				cipher = sec->dot118021XGrpPrivacy;
-+				key = &sec->dot118021XGrpKey[keyid];
-+				sta = rtw_get_bcmc_stainfo(adapter);
-+				if (sta)
-+					pn = &sta->dot11txpn.val;
-+			#ifdef CONFIG_IEEE80211W
-+			} else if (keyid <= BIP_MAX_KEYID) {
-+				if (SEC_IS_BIP_KEY_INSTALLED(sec) != _TRUE)
-+					goto exit;
-+				cipher = sec->dot11wCipher;
-+				key = &sec->dot11wBIPKey[keyid];
-+				pn = &sec->dot11wBIPtxpn.val;
-+			#endif
-+			}
-+		}
-+	} else {
-+		/* Pairwise key, RX GTK/IGTK for specific peer */
-+		sta = rtw_get_stainfo(stapriv, mac_addr);
-+		if (!sta)
-+			goto exit;
-+
-+		if (keyid < WEP_KEYS && pairwise) {
-+			if (sta->bpairwise_key_installed != _TRUE)
-+				goto exit;
-+			cipher = sta->dot118021XPrivacy;
-+			key = &sta->dot118021x_UncstKey;
-+		#ifdef CONFIG_RTW_MESH
-+		} else if (keyid < WEP_KEYS && !pairwise) {
-+			if (!(sta->gtk_bmp & BIT(keyid)))
-+				goto exit;
-+			cipher = sta->group_privacy;
-+			key = &sta->gtk;
-+		#ifdef CONFIG_IEEE80211W
-+		} else if (keyid <= BIP_MAX_KEYID && !pairwise) {
-+			if (!(sta->igtk_bmp & BIT(keyid)))
-+				goto exit;
-+			cipher = sta->dot11wCipher;
-+			key = &sta->igtk;
-+			pn = &sta->igtk_pn.val;
-+		#endif
-+		#endif /* CONFIG_RTW_MESH */
-+		}
-+	}
-+
-+	if (!key)
-+		goto exit;
-+
-+	if (cipher == _WEP40_) {
-+		cipher = WLAN_CIPHER_SUITE_WEP40;
-+		key_len = sec->dot11DefKeylen[keyid];
-+	} else if (cipher == _WEP104_) {
-+		cipher = WLAN_CIPHER_SUITE_WEP104;
-+		key_len = sec->dot11DefKeylen[keyid];
-+	} else if (cipher == _TKIP_ || cipher == _TKIP_WTMIC_) {
-+		cipher = WLAN_CIPHER_SUITE_TKIP;
-+		key_len = 16;
-+	} else if (cipher == _AES_) {
-+		cipher = WLAN_CIPHER_SUITE_CCMP;
-+		key_len = 16;
-+#ifdef CONFIG_WAPI_SUPPORT
-+	} else if (cipher == _SMS4_) {
-+		cipher = WLAN_CIPHER_SUITE_SMS4;
-+		key_len = 16;
-+#endif
-+	} else if (cipher == _GCMP_) {
-+		cipher = WIFI_CIPHER_SUITE_GCMP;
-+		key_len = 16;
-+	} else if (cipher == _CCMP_256_) {
-+		cipher = WIFI_CIPHER_SUITE_CCMP_256;
-+		key_len = 32;
-+	} else if (cipher == _GCMP_256_) {
-+		cipher = WIFI_CIPHER_SUITE_GCMP_256;
-+		key_len = 32;
-+	#ifdef CONFIG_IEEE80211W
-+	} else if (cipher == _BIP_CMAC_128_) {
-+		cipher = WLAN_CIPHER_SUITE_AES_CMAC;
-+		key_len = 16;
-+	} else if (cipher == _BIP_GMAC_128_) {
-+		cipher = WIFI_CIPHER_SUITE_BIP_GMAC_128;
-+		key_len = 16;
-+	} else if (cipher == _BIP_GMAC_256_) {
-+		cipher = WIFI_CIPHER_SUITE_BIP_GMAC_256;
-+		key_len = 32;
-+	} else if (cipher == _BIP_CMAC_256_) {
-+		cipher = WIFI_CIPHER_SUITE_BIP_CMAC_256;
-+		key_len = 32;
-+	#endif
-+	} else {
-+		RTW_WARN(FUNC_NDEV_FMT" unknown cipher:%u\n", FUNC_NDEV_ARG(ndev), cipher);
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (pn) {
-+		*((u64 *)pn_val) = cpu_to_le64(*pn);
-+		pn_len = 6;
-+	}
-+
-+	ret = 0;
-+	
-+exit:
-+	RTW_INFO(FUNC_NDEV_FMT
-+		GET_KEY_PARAM_FMT_S
-+		GET_KEY_PARAM_FMT_2_6_37
-+		GET_KEY_PARAM_FMT_E
-+		" ret %d\n", FUNC_NDEV_ARG(ndev)
-+		GET_KEY_PARAM_ARG_S
-+		GET_KEY_PARAM_ARG_2_6_37
-+		GET_KEY_PARAM_ARG_E
-+		, ret);
-+	if (pn)
-+		RTW_INFO(FUNC_NDEV_FMT " seq:0x%llx\n", FUNC_NDEV_ARG(ndev), *pn);
-+
-+	if (ret == 0) {
-+		_rtw_memset(&params, 0, sizeof(params));
-+
-+		params.cipher = cipher;
-+		params.key = key->skey;
-+		params.key_len = key_len;
-+		if (pn) {
-+			params.seq = pn_val;
-+			params.seq_len = pn_len;
-+		}
-+
-+		callback(cookie, &params);
-+	}
-+
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+				u8 key_index, bool pairwise, const u8 *mac_addr)
-+#else	/* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */
-+				u8 key_index, const u8 *mac_addr)
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+
-+	RTW_INFO(FUNC_NDEV_FMT" key_index=%d, addr=%pM\n", FUNC_NDEV_ARG(ndev), key_index, mac_addr);
-+
-+	if (key_index == psecuritypriv->dot11PrivacyKeyIndex) {
-+		/* clear the flag of wep default key set. */
-+		psecuritypriv->bWepDefaultKeyIdxSet = 0;
-+	}
-+
-+	return 0;
-+}
-+
-+static int cfg80211_rtw_set_default_key(struct wiphy *wiphy,
-+	struct net_device *ndev, u8 key_index
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
-+	, bool unicast, bool multicast
-+	#endif
-+)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+
-+#define SET_DEF_KEY_PARAM_FMT " key_index=%d"
-+#define SET_DEF_KEY_PARAM_ARG , key_index
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
-+	#define SET_DEF_KEY_PARAM_FMT_2_6_38 ", unicast=%d, multicast=%d"
-+	#define SET_DEF_KEY_PARAM_ARG_2_6_38 , unicast, multicast
-+#else
-+	#define SET_DEF_KEY_PARAM_FMT_2_6_38 ""
-+	#define SET_DEF_KEY_PARAM_ARG_2_6_38
-+#endif
-+
-+	RTW_INFO(FUNC_NDEV_FMT
-+		SET_DEF_KEY_PARAM_FMT
-+		SET_DEF_KEY_PARAM_FMT_2_6_38
-+		"\n", FUNC_NDEV_ARG(ndev)
-+		SET_DEF_KEY_PARAM_ARG
-+		SET_DEF_KEY_PARAM_ARG_2_6_38
-+	);
-+
-+	if ((key_index < WEP_KEYS) && ((psecuritypriv->dot11PrivacyAlgrthm == _WEP40_) || (psecuritypriv->dot11PrivacyAlgrthm == _WEP104_))) { /* set wep default key */
-+		psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+
-+		psecuritypriv->dot11PrivacyKeyIndex = key_index;
-+
-+		psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
-+		psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
-+		if (psecuritypriv->dot11DefKeylen[key_index] == 13) {
-+			psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
-+			psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
-+		}
-+
-+		psecuritypriv->bWepDefaultKeyIdxSet = 1; /* set the flag to represent that wep default key has been set */
-+	}
-+
-+	return 0;
-+
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30))
-+int cfg80211_rtw_set_default_mgmt_key(struct wiphy *wiphy,
-+	struct net_device *ndev, u8 key_index)
-+{
-+#define SET_DEF_KEY_PARAM_FMT " key_index=%d"
-+#define SET_DEF_KEY_PARAM_ARG , key_index
-+
-+	RTW_INFO(FUNC_NDEV_FMT
-+		SET_DEF_KEY_PARAM_FMT
-+		"\n", FUNC_NDEV_ARG(ndev)
-+		SET_DEF_KEY_PARAM_ARG
-+	);
-+
-+	return 0;
-+}
-+#endif
-+
-+#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
-+static int cfg80211_rtw_set_rekey_data(struct wiphy *wiphy,
-+	struct net_device *ndev,
-+	struct cfg80211_gtk_rekey_data *data)
-+{
-+	/*int i;*/
-+	struct sta_info *psta;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct mlme_priv   *pmlmepriv = &padapter->mlmepriv;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
-+
-+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
-+	if (psta == NULL) {
-+		RTW_INFO("%s, : Obtain Sta_info fail\n", __func__);
-+		return -1;
-+	}
-+
-+	_rtw_memcpy(psta->kek, data->kek, NL80211_KEK_LEN);
-+	/*printk("\ncfg80211_rtw_set_rekey_data KEK:");
-+	for(i=0;i<NL80211_KEK_LEN; i++)
-+		printk(" %02x ", psta->kek[i]);*/
-+	_rtw_memcpy(psta->kck, data->kck, NL80211_KCK_LEN);
-+	/*printk("\ncfg80211_rtw_set_rekey_data KCK:");
-+	for(i=0;i<NL80211_KCK_LEN; i++)
-+		printk(" %02x ", psta->kck[i]);*/
-+	_rtw_memcpy(psta->replay_ctr, data->replay_ctr, NL80211_REPLAY_CTR_LEN);
-+	psecuritypriv->binstallKCK_KEK = _TRUE;
-+	/*printk("\nREPLAY_CTR: ");
-+	for(i=0;i<RTW_REPLAY_CTR_LEN; i++)
-+		printk(" %02x ", psta->replay_ctr[i]);*/
-+
-+	return 0;
-+}
-+#endif /*CONFIG_GTK_OL*/
-+
-+#ifdef CONFIG_RTW_MESH
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
-+static enum nl80211_mesh_power_mode rtw_mesh_ps_to_nl80211_mesh_power_mode(u8 ps)
-+{
-+	if (ps == RTW_MESH_PS_UNKNOWN)
-+		return NL80211_MESH_POWER_UNKNOWN;
-+	if (ps == RTW_MESH_PS_ACTIVE)
-+		return NL80211_MESH_POWER_ACTIVE;
-+	if (ps == RTW_MESH_PS_LSLEEP)
-+		return NL80211_MESH_POWER_LIGHT_SLEEP;
-+	if (ps == RTW_MESH_PS_DSLEEP)
-+		return NL80211_MESH_POWER_DEEP_SLEEP;
-+
-+	rtw_warn_on(1);
-+	return NL80211_MESH_POWER_UNKNOWN;
-+}
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+enum nl80211_plink_state rtw_plink_state_to_nl80211_plink_state(u8 plink_state)
-+{
-+	if (plink_state == RTW_MESH_PLINK_UNKNOWN)
-+		return NUM_NL80211_PLINK_STATES;
-+	if (plink_state == RTW_MESH_PLINK_LISTEN)
-+		return NL80211_PLINK_LISTEN;
-+	if (plink_state == RTW_MESH_PLINK_OPN_SNT)
-+		return NL80211_PLINK_OPN_SNT;
-+	if (plink_state == RTW_MESH_PLINK_OPN_RCVD)
-+		return NL80211_PLINK_OPN_RCVD;
-+	if (plink_state == RTW_MESH_PLINK_CNF_RCVD)
-+		return NL80211_PLINK_CNF_RCVD;
-+	if (plink_state == RTW_MESH_PLINK_ESTAB)
-+		return NL80211_PLINK_ESTAB;
-+	if (plink_state == RTW_MESH_PLINK_HOLDING)
-+		return NL80211_PLINK_HOLDING;
-+	if (plink_state == RTW_MESH_PLINK_BLOCKED)
-+		return NL80211_PLINK_BLOCKED;
-+
-+	rtw_warn_on(1);
-+	return NUM_NL80211_PLINK_STATES;
-+}
-+
-+u8 nl80211_plink_state_to_rtw_plink_state(enum nl80211_plink_state plink_state)
-+{
-+	if (plink_state == NL80211_PLINK_LISTEN)
-+		return RTW_MESH_PLINK_LISTEN;
-+	if (plink_state == NL80211_PLINK_OPN_SNT)
-+		return RTW_MESH_PLINK_OPN_SNT;
-+	if (plink_state == NL80211_PLINK_OPN_RCVD)
-+		return RTW_MESH_PLINK_OPN_RCVD;
-+	if (plink_state == NL80211_PLINK_CNF_RCVD)
-+		return RTW_MESH_PLINK_CNF_RCVD;
-+	if (plink_state == NL80211_PLINK_ESTAB)
-+		return RTW_MESH_PLINK_ESTAB;
-+	if (plink_state == NL80211_PLINK_HOLDING)
-+		return RTW_MESH_PLINK_HOLDING;
-+	if (plink_state == NL80211_PLINK_BLOCKED)
-+		return RTW_MESH_PLINK_BLOCKED;
-+
-+	rtw_warn_on(1);
-+	return RTW_MESH_PLINK_UNKNOWN;
-+}
-+#endif
-+
-+static void rtw_cfg80211_fill_mesh_only_sta_info(struct mesh_plink_ent *plink, struct sta_info *sta, struct station_info *sinfo)
-+{
-+	sinfo->filled |= STATION_INFO_LLID;
-+	sinfo->llid = plink->llid;
-+	sinfo->filled |= STATION_INFO_PLID;
-+	sinfo->plid = plink->plid;
-+	sinfo->filled |= STATION_INFO_PLINK_STATE;
-+	sinfo->plink_state = rtw_plink_state_to_nl80211_plink_state(plink->plink_state);
-+	if (!sta && plink->scanned) {
-+		sinfo->filled |= STATION_INFO_SIGNAL;
-+		sinfo->signal = translate_percentage_to_dbm(plink->scanned->network.PhyInfo.SignalStrength);
-+		sinfo->filled |= STATION_INFO_INACTIVE_TIME;
-+		if (plink->plink_state == RTW_MESH_PLINK_UNKNOWN)
-+			sinfo->inactive_time = 0 - 1;
-+		else
-+			sinfo->inactive_time = rtw_get_passing_time_ms(plink->scanned->last_scanned);
-+	}
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
-+	if (sta) {
-+		sinfo->filled |= STATION_INFO_LOCAL_PM;
-+		sinfo->local_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->local_mps);
-+		sinfo->filled |= STATION_INFO_PEER_PM;
-+		sinfo->peer_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->peer_mps);
-+		sinfo->filled |= STATION_INFO_NONPEER_PM;
-+		sinfo->nonpeer_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->nonpeer_mps);
-+	}
-+#endif
-+}
-+#endif /* CONFIG_RTW_MESH */
-+
-+static int cfg80211_rtw_get_station(struct wiphy *wiphy,
-+	struct net_device *ndev,
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
-+	u8 *mac,
-+#else
-+	const u8 *mac,
-+#endif
-+	struct station_info *sinfo)
-+{
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct sta_info *psta = NULL;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+#ifdef CONFIG_RTW_MESH
-+	struct mesh_plink_ent *plink = NULL;
-+#endif
-+
-+	sinfo->filled = 0;
-+
-+	if (!mac) {
-+		RTW_INFO(FUNC_NDEV_FMT" mac==%p\n", FUNC_NDEV_ARG(ndev), mac);
-+		ret = -ENOENT;
-+		goto exit;
-+	}
-+
-+	psta = rtw_get_stainfo(pstapriv, mac);
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(padapter)) {
-+		if (psta)
-+			plink = psta->plink;
-+		if (!plink)
-+			plink = rtw_mesh_plink_get(padapter, mac);
-+	}
-+#endif /* CONFIG_RTW_MESH */
-+
-+	if ((!MLME_IS_MESH(padapter) && !psta)
-+		#ifdef CONFIG_RTW_MESH
-+		|| (MLME_IS_MESH(padapter) && !plink)
-+		#endif
-+	) {
-+		RTW_INFO(FUNC_NDEV_FMT" no sta info for mac="MAC_FMT"\n"
-+			, FUNC_NDEV_ARG(ndev), MAC_ARG(mac));
-+		ret = -ENOENT;
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_DEBUG_CFG80211
-+	RTW_INFO(FUNC_NDEV_FMT" mac="MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(mac));
-+#endif
-+
-+	/* for infra./P2PClient mode */
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
-+		&& check_fwstate(pmlmepriv, WIFI_ASOC_STATE)
-+	) {
-+		struct wlan_network  *cur_network = &(pmlmepriv->cur_network);
-+
-+		if (_rtw_memcmp((u8 *)mac, cur_network->network.MacAddress, ETH_ALEN) == _FALSE) {
-+			RTW_INFO("%s, mismatch bssid="MAC_FMT"\n", __func__, MAC_ARG(cur_network->network.MacAddress));
-+			ret = -ENOENT;
-+			goto exit;
-+		}
-+
-+		sinfo->filled |= STATION_INFO_SIGNAL;
-+		sinfo->signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);
-+
-+		sinfo->filled |= STATION_INFO_TX_BITRATE;
-+		sinfo->txrate.legacy = rtw_get_cur_max_rate(padapter);
-+	}
-+
-+	if (psta) {
-+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE
-+			|| check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE
-+		) {
-+			sinfo->filled |= STATION_INFO_SIGNAL;
-+			sinfo->signal = translate_percentage_to_dbm(psta->cmn.rssi_stat.rssi);
-+		}
-+		sinfo->filled |= STATION_INFO_INACTIVE_TIME;
-+		sinfo->inactive_time = rtw_get_passing_time_ms(psta->sta_stats.last_rx_time);
-+		sinfo->filled |= STATION_INFO_RX_PACKETS;
-+		sinfo->rx_packets = sta_rx_data_pkts(psta);
-+		sinfo->filled |= STATION_INFO_TX_PACKETS;
-+		sinfo->tx_packets = psta->sta_stats.tx_pkts;
-+		sinfo->filled |= STATION_INFO_TX_FAILED;
-+		sinfo->tx_failed = psta->sta_stats.tx_fail_cnt;
-+	}
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(padapter))
-+		rtw_cfg80211_fill_mesh_only_sta_info(plink, psta, sinfo);
-+#endif
-+
-+exit:
-+	return ret;
-+}
-+
-+extern int netdev_open(struct net_device *pnetdev);
-+
-+#if 0
-+enum nl80211_iftype {
-+	NL80211_IFTYPE_UNSPECIFIED,
-+	NL80211_IFTYPE_ADHOC, /* 1 */
-+	NL80211_IFTYPE_STATION, /* 2 */
-+	NL80211_IFTYPE_AP, /* 3 */
-+	NL80211_IFTYPE_AP_VLAN,
-+	NL80211_IFTYPE_WDS,
-+	NL80211_IFTYPE_MONITOR, /* 6 */
-+	NL80211_IFTYPE_MESH_POINT,
-+	NL80211_IFTYPE_P2P_CLIENT, /* 8 */
-+	NL80211_IFTYPE_P2P_GO, /* 9 */
-+	/* keep last */
-+	NUM_NL80211_IFTYPES,
-+	NL80211_IFTYPE_MAX = NUM_NL80211_IFTYPES - 1
-+};
-+#endif
-+static int cfg80211_rtw_change_iface(struct wiphy *wiphy,
-+				     struct net_device *ndev,
-+				     enum nl80211_iftype type,
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
-+				     u32 *flags,
-+#endif
-+				     struct vif_params *params)
-+{
-+	enum nl80211_iftype old_type;
-+	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct wireless_dev *rtw_wdev = padapter->rtw_wdev;
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+#endif
-+#ifdef CONFIG_MONITOR_MODE_XMIT
-+	struct mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+#endif
-+	int ret = 0;
-+	u8 change = _FALSE;
-+
-+	RTW_INFO(FUNC_NDEV_FMT" type=%d, hw_port:%d\n", FUNC_NDEV_ARG(ndev), type, padapter->hw_port);
-+
-+	if (adapter_to_dvobj(padapter)->processing_dev_remove == _TRUE) {
-+		ret = -EPERM;
-+		goto exit;
-+	}
-+
-+
-+	RTW_INFO(FUNC_NDEV_FMT" call netdev_open\n", FUNC_NDEV_ARG(ndev));
-+	if (netdev_open(ndev) != 0) {
-+		RTW_INFO(FUNC_NDEV_FMT" call netdev_open fail\n", FUNC_NDEV_ARG(ndev));
-+		ret = -EPERM;
-+		goto exit;
-+	}
-+
-+
-+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
-+		RTW_INFO(FUNC_NDEV_FMT" call rtw_pwr_wakeup fail\n", FUNC_NDEV_ARG(ndev));
-+		ret = -EPERM;
-+		goto exit;
-+	}
-+
-+	old_type = rtw_wdev->iftype;
-+	RTW_INFO(FUNC_NDEV_FMT" old_iftype=%d, new_iftype=%d\n",
-+		FUNC_NDEV_ARG(ndev), old_type, type);
-+
-+	if (old_type != type) {
-+		change = _TRUE;
-+		pmlmeext->action_public_rxseq = 0xffff;
-+		pmlmeext->action_public_dialog_token = 0xff;
-+	}
-+
-+	/* initial default type */
-+	ndev->type = ARPHRD_ETHER;
-+
-+	/*
-+	 * Disable Power Save in moniter mode,
-+	 * and enable it after leaving moniter mode.
-+	 */
-+	if (type == NL80211_IFTYPE_MONITOR) {
-+		rtw_ps_deny(padapter, PS_DENY_MONITOR_MODE);
-+		LeaveAllPowerSaveMode(padapter);
-+	} else if (old_type == NL80211_IFTYPE_MONITOR) {
-+		/* driver in moniter mode in last time */
-+		rtw_ps_deny_cancel(padapter, PS_DENY_MONITOR_MODE);
-+	}
-+
-+	switch (type) {
-+	case NL80211_IFTYPE_ADHOC:
-+		networkType = Ndis802_11IBSS;
-+		break;
-+
-+	case NL80211_IFTYPE_STATION:
-+		networkType = Ndis802_11Infrastructure;
-+		#ifdef CONFIG_P2P
-+		if (change && pwdinfo->driver_interface == DRIVER_CFG80211) {
-+			#if !RTW_P2P_GROUP_INTERFACE
-+			if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)
-+				|| rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)
-+			) {
-+				/* it means remove GC/GO and change mode from GC/GO to station(P2P DEVICE) */
-+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
-+			}
-+			#endif
-+		}
-+		#endif /* CONFIG_P2P */
-+		break;
-+
-+	case NL80211_IFTYPE_AP:
-+		networkType = Ndis802_11APMode;
-+		#ifdef CONFIG_P2P
-+		if (change && pwdinfo->driver_interface == DRIVER_CFG80211) {
-+			#if !RTW_P2P_GROUP_INTERFACE
-+			if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
-+				/* it means P2P Group created, we will be GO and change mode from  P2P DEVICE to AP(GO) */
-+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
-+			}
-+			#endif
-+		}
-+		#endif /* CONFIG_P2P */
-+		break;
-+
-+#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
-+	case NL80211_IFTYPE_P2P_CLIENT:
-+		networkType = Ndis802_11Infrastructure;
-+		if (change && pwdinfo->driver_interface == DRIVER_CFG80211) {
-+			if (!rtw_p2p_enable(padapter, P2P_ROLE_CLIENT)) {
-+				ret = -EOPNOTSUPP;
-+				goto exit;
-+			}
-+		}
-+		break;
-+
-+	case NL80211_IFTYPE_P2P_GO:
-+		networkType = Ndis802_11APMode;
-+		if (change && pwdinfo->driver_interface == DRIVER_CFG80211) {
-+			if (!rtw_p2p_enable(padapter, P2P_ROLE_GO)) {
-+				ret = -EOPNOTSUPP;
-+				goto exit;
-+			}
-+		}
-+		break;
-+#endif /* defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) */
-+
-+#ifdef CONFIG_RTW_MESH
-+	case NL80211_IFTYPE_MESH_POINT:
-+		networkType = Ndis802_11_mesh;
-+		break;
-+#endif
-+
-+#ifdef CONFIG_WIFI_MONITOR
-+	case NL80211_IFTYPE_MONITOR:
-+		networkType = Ndis802_11Monitor;
-+
-+#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
-+		ndev->type = ARPHRD_IEEE80211; /* IEEE 802.11 : 801 */
-+#else
-+		ndev->type = ARPHRD_IEEE80211_RADIOTAP; /* IEEE 802.11 + radiotap header : 803 */
-+#endif
-+		break;
-+#endif /* CONFIG_WIFI_MONITOR */
-+	default:
-+		ret = -EOPNOTSUPP;
-+		goto exit;
-+	}
-+
-+	rtw_wdev->iftype = type;
-+
-+	if (rtw_set_802_11_infrastructure_mode(padapter, networkType, 0) == _FALSE) {
-+		rtw_wdev->iftype = old_type;
-+		ret = -EPERM;
-+		goto exit;
-+	}
-+
-+	rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK);
-+#ifdef CONFIG_MONITOR_MODE_XMIT
-+	if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE)
-+		rtw_indicate_connect(padapter);
-+#endif
-+
-+	#if defined(CONFIG_RTW_WDS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))
-+	if (params->use_4addr != -1) {
-+		RTW_INFO(FUNC_NDEV_FMT" use_4addr=%d\n"
-+			, FUNC_NDEV_ARG(ndev), params->use_4addr);
-+		adapter_set_use_wds(padapter, params->use_4addr);
-+	}
-+	#endif
-+
-+exit:
-+
-+	RTW_INFO(FUNC_NDEV_FMT" ret:%d\n", FUNC_NDEV_ARG(ndev), ret);
-+	return ret;
-+}
-+
-+void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted)
-+{
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
-+	_irqL	irqL;
-+
-+#if (KERNEL_VERSION(4, 8, 0) <= LINUX_VERSION_CODE)
-+	struct cfg80211_scan_info info;
-+
-+	memset(&info, 0, sizeof(info));
-+	info.aborted = aborted;
-+#endif
-+
-+	_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
-+	if (pwdev_priv->scan_request != NULL) {
-+		#ifdef CONFIG_DEBUG_CFG80211
-+		RTW_INFO("%s with scan req\n", __FUNCTION__);
-+		#endif
-+
-+		/* avoid WARN_ON(request != wiphy_to_dev(request->wiphy)->scan_req); */
-+		if (pwdev_priv->scan_request->wiphy != pwdev_priv->rtw_wdev->wiphy)
-+			RTW_INFO("error wiphy compare\n");
-+		else
-+#if (KERNEL_VERSION(4, 8, 0) <= LINUX_VERSION_CODE)
-+			cfg80211_scan_done(pwdev_priv->scan_request, &info);
-+#else
-+			cfg80211_scan_done(pwdev_priv->scan_request, aborted);
-+#endif
-+
-+		pwdev_priv->scan_request = NULL;
-+	} else {
-+		#ifdef CONFIG_DEBUG_CFG80211
-+		RTW_INFO("%s without scan req\n", __FUNCTION__);
-+		#endif
-+	}
-+	_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
-+}
-+
-+u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms)
-+{
-+	struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);
-+	u8 empty = _FALSE;
-+	systime start;
-+	u32 pass_ms;
-+
-+	start = rtw_get_current_time();
-+
-+	while (rtw_get_passing_time_ms(start) <= timeout_ms) {
-+
-+		if (RTW_CANNOT_RUN(adapter))
-+			break;
-+
-+		if (!wdev_priv->scan_request) {
-+			empty = _TRUE;
-+			break;
-+		}
-+
-+		rtw_msleep_os(10);
-+	}
-+
-+	pass_ms = rtw_get_passing_time_ms(start);
-+
-+	if (empty == _FALSE && pass_ms > timeout_ms)
-+		RTW_PRINT(FUNC_ADPT_FMT" pass_ms:%u, timeout\n"
-+			, FUNC_ADPT_ARG(adapter), pass_ms);
-+
-+	return pass_ms;
-+}
-+
-+void rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork)
-+{
-+	struct wireless_dev *pwdev = padapter->rtw_wdev;
-+	struct wiphy *wiphy = pwdev->wiphy;
-+	struct cfg80211_bss *bss = NULL;
-+	WLAN_BSSID_EX select_network = pnetwork->network;
-+
-+	bss = cfg80211_get_bss(wiphy, NULL/*notify_channel*/,
-+		select_network.MacAddress, select_network.Ssid.Ssid,
-+		select_network.Ssid.SsidLength,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)
-+		select_network.InfrastructureMode == Ndis802_11Infrastructure?IEEE80211_BSS_TYPE_ESS:IEEE80211_BSS_TYPE_IBSS,
-+		IEEE80211_PRIVACY(select_network.Privacy));
-+#else
-+		select_network.InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS,
-+		select_network.InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS);
-+#endif
-+
-+	if (bss) {
-+		cfg80211_unlink_bss(wiphy, bss);
-+		RTW_INFO("%s(): cfg80211_unlink %s!!\n", __func__, select_network.Ssid.Ssid);
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
-+		cfg80211_put_bss(padapter->rtw_wdev->wiphy, bss);
-+#else
-+		cfg80211_put_bss(bss);
-+#endif
-+	}
-+	return;
-+}
-+
-+/* if target wps scan ongoing, target_ssid is filled */
-+int rtw_cfg80211_is_target_wps_scan(struct cfg80211_scan_request *scan_req, struct cfg80211_ssid *target_ssid)
-+{
-+	int ret = 0;
-+
-+	if (scan_req->n_ssids != 1
-+		|| scan_req->ssids[0].ssid_len == 0
-+		|| scan_req->n_channels != 1
-+	)
-+		goto exit;
-+
-+	/* under target WPS scan */
-+	_rtw_memcpy(target_ssid, scan_req->ssids, sizeof(struct cfg80211_ssid));
-+	ret = 1;
-+
-+exit:
-+	return ret;
-+}
-+
-+static void _rtw_cfg80211_surveydone_event_callback(_adapter *padapter, struct cfg80211_scan_request *scan_req)
-+{
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	RT_CHANNEL_INFO *chset = rfctl->channel_set;
-+	_irqL	irqL;
-+	_list					*plist, *phead;
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	_queue				*queue	= &(pmlmepriv->scanned_queue);
-+	struct	wlan_network	*pnetwork = NULL;
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+	struct cfg80211_ssid target_ssid;
-+	u8 target_wps_scan = 0;
-+	u8 ch;
-+
-+#ifdef CONFIG_DEBUG_CFG80211
-+	RTW_INFO("%s\n", __func__);
-+#endif
-+
-+	if (scan_req)
-+		target_wps_scan = rtw_cfg80211_is_target_wps_scan(scan_req, &target_ssid);
-+	else {
-+		_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
-+		if (pwdev_priv->scan_request != NULL)
-+			target_wps_scan = rtw_cfg80211_is_target_wps_scan(pwdev_priv->scan_request, &target_ssid);
-+		_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
-+	}
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+		ch = pnetwork->network.Configuration.DSConfig;
-+
-+		/* report network only if the current channel set contains the channel to which this network belongs */
-+		if (rtw_chset_search_ch(chset, ch) >= 0
-+			&& rtw_mlme_band_check(padapter, ch) == _TRUE
-+			&& _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))
-+			&& (!IS_DFS_SLAVE_WITH_RD(rfctl)
-+				|| rtw_rfctl_dfs_domain_unknown(rfctl)
-+				|| !rtw_chset_is_ch_non_ocp(chset, ch))
-+		) {
-+			if (target_wps_scan)
-+				rtw_cfg80211_clear_wps_sr_of_non_target_bss(padapter, pnetwork, &target_ssid);
-+			rtw_cfg80211_inform_bss(padapter, pnetwork);
-+		}
-+#if 0
-+		/* check ralink testbed RSN IE length */
-+		{
-+			if (_rtw_memcmp(pnetwork->network.Ssid.Ssid, "Ralink_11n_AP", 13)) {
-+				uint ie_len = 0;
-+				u8 *p = NULL;
-+				p = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_));
-+				RTW_INFO("ie_len=%d\n", ie_len);
-+			}
-+		}
-+#endif
-+		plist = get_next(plist);
-+
-+	}
-+
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+}
-+
-+inline void rtw_cfg80211_surveydone_event_callback(_adapter *padapter)
-+{
-+	_rtw_cfg80211_surveydone_event_callback(padapter, NULL);
-+}
-+
-+static int rtw_cfg80211_set_probe_req_wpsp2pie(_adapter *padapter, char *buf, int len)
-+{
-+	int ret = 0;
-+	uint wps_ielen = 0;
-+	u8 *wps_ie;
-+	u32	p2p_ielen = 0;
-+	u8 *p2p_ie;
-+	u32	wfd_ielen = 0;
-+	u8 *wfd_ie;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+#ifdef CONFIG_DEBUG_CFG80211
-+	RTW_INFO("%s, ielen=%d\n", __func__, len);
-+#endif
-+
-+	if (len > 0) {
-+		wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen);
-+		if (wps_ie) {
-+			#ifdef CONFIG_DEBUG_CFG80211
-+			RTW_INFO("probe_req_wps_ielen=%d\n", wps_ielen);
-+			#endif
-+
-+			if (pmlmepriv->wps_probe_req_ie) {
-+				u32 free_len = pmlmepriv->wps_probe_req_ie_len;
-+				pmlmepriv->wps_probe_req_ie_len = 0;
-+				rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);
-+				pmlmepriv->wps_probe_req_ie = NULL;
-+			}
-+
-+			pmlmepriv->wps_probe_req_ie = rtw_malloc(wps_ielen);
-+			if (pmlmepriv->wps_probe_req_ie == NULL) {
-+				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
-+				return -EINVAL;
-+
-+			}
-+			_rtw_memcpy(pmlmepriv->wps_probe_req_ie, wps_ie, wps_ielen);
-+			pmlmepriv->wps_probe_req_ie_len = wps_ielen;
-+		}
-+
-+		/* buf += wps_ielen; */
-+		/* len -= wps_ielen; */
-+
-+		#ifdef CONFIG_P2P
-+		p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen);
-+		if (p2p_ie) {
-+			struct wifidirect_info *wdinfo = &padapter->wdinfo;
-+			u32 attr_contentlen = 0;
-+			u8 listen_ch_attr[5];
-+
-+			#ifdef CONFIG_DEBUG_CFG80211
-+			RTW_INFO("probe_req_p2p_ielen=%d\n", p2p_ielen);
-+			#endif
-+
-+			if (pmlmepriv->p2p_probe_req_ie) {
-+				u32 free_len = pmlmepriv->p2p_probe_req_ie_len;
-+				pmlmepriv->p2p_probe_req_ie_len = 0;
-+				rtw_mfree(pmlmepriv->p2p_probe_req_ie, free_len);
-+				pmlmepriv->p2p_probe_req_ie = NULL;
-+			}
-+
-+			pmlmepriv->p2p_probe_req_ie = rtw_malloc(p2p_ielen);
-+			if (pmlmepriv->p2p_probe_req_ie == NULL) {
-+				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
-+				return -EINVAL;
-+
-+			}
-+			_rtw_memcpy(pmlmepriv->p2p_probe_req_ie, p2p_ie, p2p_ielen);
-+			pmlmepriv->p2p_probe_req_ie_len = p2p_ielen;
-+
-+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8 *)listen_ch_attr, (uint *) &attr_contentlen)
-+				&& attr_contentlen == 5) {
-+				if (wdinfo->listen_channel !=  listen_ch_attr[4]) {
-+					RTW_INFO(FUNC_ADPT_FMT" listen channel - country:%c%c%c, class:%u, ch:%u\n",
-+						FUNC_ADPT_ARG(padapter), listen_ch_attr[0], listen_ch_attr[1], listen_ch_attr[2],
-+						listen_ch_attr[3], listen_ch_attr[4]);
-+					wdinfo->listen_channel = listen_ch_attr[4];
-+				}
-+			}
-+		}
-+		#endif /* CONFIG_P2P */
-+
-+		#ifdef CONFIG_WFD
-+		wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen);
-+		if (wfd_ie) {
-+			#ifdef CONFIG_DEBUG_CFG80211
-+			RTW_INFO("probe_req_wfd_ielen=%d\n", wfd_ielen);
-+			#endif
-+
-+			if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_PROBE_REQ_IE, wfd_ie, wfd_ielen) != _SUCCESS)
-+				return -EINVAL;
-+		}
-+		#endif /* CONFIG_WFD */
-+
-+		#ifdef CONFIG_RTW_MBO
-+		rtw_mbo_update_ie_data(padapter, buf, len);
-+		#endif
-+	}
-+
-+	return ret;
-+
-+}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+u8 rtw_cfg80211_scan_via_buddy(_adapter *padapter, struct cfg80211_scan_request *request)
-+{
-+	int i;
-+	u8 ret = _FALSE;
-+	_adapter *iface = NULL;
-+	_irqL	irqL;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		struct mlme_priv *buddy_mlmepriv;
-+		struct rtw_wdev_priv *buddy_wdev_priv;
-+
-+		iface = dvobj->padapters[i];
-+		if (iface == NULL)
-+			continue;
-+
-+		if (iface == padapter)
-+			continue;
-+
-+		if (rtw_is_adapter_up(iface) == _FALSE)
-+			continue;
-+
-+		buddy_mlmepriv = &iface->mlmepriv;
-+		if (!check_fwstate(buddy_mlmepriv, WIFI_UNDER_SURVEY))
-+			continue;
-+
-+		buddy_wdev_priv = adapter_wdev_data(iface);
-+		_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
-+		_enter_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL);
-+		if (buddy_wdev_priv->scan_request) {
-+			pmlmepriv->scanning_via_buddy_intf = _TRUE;
-+			_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+			set_fwstate(pmlmepriv, WIFI_UNDER_SURVEY);
-+			_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+			pwdev_priv->scan_request = request;
-+			ret = _TRUE;
-+		}
-+		_exit_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL);
-+		_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
-+
-+		if (ret == _TRUE)
-+			goto exit;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+void rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_aborted)
-+{
-+	int i;
-+	_adapter *iface = NULL;
-+	_irqL	irqL;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	struct mlme_priv *mlmepriv;
-+	struct rtw_wdev_priv *wdev_priv;
-+	bool indicate_buddy_scan;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if ((iface) && rtw_is_adapter_up(iface)) {
-+
-+			if (iface == padapter)
-+				continue;
-+
-+			mlmepriv = &(iface->mlmepriv);
-+			wdev_priv = adapter_wdev_data(iface);
-+
-+			indicate_buddy_scan = _FALSE;
-+			_enter_critical_bh(&wdev_priv->scan_req_lock, &irqL);
-+			if (mlmepriv->scanning_via_buddy_intf == _TRUE) {
-+				mlmepriv->scanning_via_buddy_intf = _FALSE;
-+				clr_fwstate(mlmepriv, WIFI_UNDER_SURVEY);
-+				if (wdev_priv->scan_request)
-+					indicate_buddy_scan = _TRUE;
-+			}
-+			_exit_critical_bh(&wdev_priv->scan_req_lock, &irqL);
-+
-+			if (indicate_buddy_scan == _TRUE) {
-+				rtw_cfg80211_surveydone_event_callback(iface);
-+				rtw_indicate_scan_done(iface, bscan_aborted);
-+			}
-+
-+		}
-+	}
-+}
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+static int cfg80211_rtw_scan(struct wiphy *wiphy
-+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
-+	, struct net_device *ndev
-+	#endif
-+	, struct cfg80211_scan_request *request)
-+{
-+	int i;
-+	u8 _status = _FALSE;
-+	int ret = 0;
-+	struct sitesurvey_parm parm;
-+	_irqL	irqL;
-+	u8 survey_times = 3;
-+	u8 survey_times_for_one_ch = 6;
-+	struct cfg80211_ssid *ssids = request->ssids;
-+	int social_channel = 0, j = 0;
-+	bool need_indicate_scan_done = _FALSE;
-+	bool ps_denied = _FALSE;
-+	u8 ssc_chk;
-+	_adapter *padapter;
-+	struct wireless_dev *wdev;
-+	struct rtw_wdev_priv *pwdev_priv;
-+	struct mlme_priv *pmlmepriv = NULL;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo;
-+#endif /* CONFIG_P2P */
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	wdev = request->wdev;
-+	#if defined(RTW_DEDICATED_P2P_DEVICE)
-+	if (wdev == wiphy_to_pd_wdev(wiphy))
-+		padapter = wiphy_to_adapter(wiphy);
-+	else
-+	#endif
-+	if (wdev_to_ndev(wdev))
-+		padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
-+	else {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+#else
-+	if (ndev == NULL) {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+	padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	wdev = ndev_to_wdev(ndev);
-+#endif
-+
-+	pwdev_priv = adapter_wdev_data(padapter);
-+	pmlmepriv = &padapter->mlmepriv;
-+#ifdef CONFIG_P2P
-+	pwdinfo = &(padapter->wdinfo);
-+#endif /* CONFIG_P2P */
-+
-+	RTW_INFO(FUNC_ADPT_FMT"%s\n", FUNC_ADPT_ARG(padapter)
-+		, wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : "");
-+
-+#if 1
-+	ssc_chk = rtw_sitesurvey_condition_check(padapter, _TRUE);
-+
-+	if (ssc_chk == SS_DENY_MP_MODE)
-+		goto bypass_p2p_chk;
-+#ifdef DBG_LA_MODE
-+	if (ssc_chk == SS_DENY_LA_MODE)
-+		goto bypass_p2p_chk;
-+#endif
-+#ifdef CONFIG_P2P
-+	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
-+		if (request->n_ssids && ssids
-+			&& _rtw_memcmp(ssids[0].ssid, "DIRECT-", 7)
-+			&& rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL)
-+		) {
-+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
-+				if (!rtw_p2p_enable(padapter, P2P_ROLE_DEVICE)) {
-+					ret = -EOPNOTSUPP;
-+					goto exit;
-+				}
-+			} else {
-+				rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
-+				#ifdef CONFIG_DEBUG_CFG80211
-+				RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
-+				#endif
-+			}
-+			rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
-+
-+			if (request->n_channels == 3 &&
-+				request->channels[0]->hw_value == 1 &&
-+				request->channels[1]->hw_value == 6 &&
-+				request->channels[2]->hw_value == 11
-+			)
-+				social_channel = 1;
-+		}
-+	}
-+#endif /*CONFIG_P2P*/
-+
-+	if (request->ie && request->ie_len > 0)
-+		rtw_cfg80211_set_probe_req_wpsp2pie(padapter, (u8 *)request->ie, request->ie_len);
-+
-+bypass_p2p_chk:
-+
-+	switch (ssc_chk) {
-+		case SS_ALLOW :
-+			break;
-+
-+		case SS_DENY_MP_MODE:
-+			ret = -EPERM;
-+			goto exit;
-+		#ifdef DBG_LA_MODE
-+		case SS_DENY_LA_MODE:
-+			ret = -EPERM;
-+			goto exit;
-+		#endif
-+		#ifdef CONFIG_RTW_REPEATER_SON
-+		case SS_DENY_RSON_SCANING :
-+		#endif
-+		case SS_DENY_BLOCK_SCAN :
-+		case SS_DENY_SELF_AP_UNDER_WPS :
-+		case SS_DENY_SELF_AP_UNDER_LINKING :
-+		case SS_DENY_SELF_AP_UNDER_SURVEY :
-+		case SS_DENY_SELF_STA_UNDER_SURVEY :
-+		#ifdef CONFIG_CONCURRENT_MODE
-+		case SS_DENY_BUDDY_UNDER_LINK_WPS :
-+		#endif
-+		case SS_DENY_BUSY_TRAFFIC :
-+		case SS_DENY_ADAPTIVITY:
-+			need_indicate_scan_done = _TRUE;
-+			goto check_need_indicate_scan_done;
-+
-+		case SS_DENY_BY_DRV :
-+			#ifdef CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY
-+			ret = -EBUSY;
-+			goto exit;
-+			#else
-+			need_indicate_scan_done = _TRUE;
-+			goto check_need_indicate_scan_done;
-+			#endif
-+			break;
-+
-+		case SS_DENY_SELF_STA_UNDER_LINKING :
-+			ret = -EBUSY;
-+			goto check_need_indicate_scan_done;
-+
-+		#ifdef CONFIG_CONCURRENT_MODE
-+		case SS_DENY_BUDDY_UNDER_SURVEY :
-+			{
-+				bool scan_via_buddy = rtw_cfg80211_scan_via_buddy(padapter, request);
-+
-+				if (scan_via_buddy == _FALSE)
-+					need_indicate_scan_done = _TRUE;
-+
-+				goto check_need_indicate_scan_done;
-+			}
-+		#endif
-+
-+		default :
-+			RTW_ERR("site survey check code (%d) unknown\n", ssc_chk);
-+			need_indicate_scan_done = _TRUE;
-+			goto check_need_indicate_scan_done;
-+	}
-+
-+	rtw_ps_deny(padapter, PS_DENY_SCAN);
-+	ps_denied = _TRUE;
-+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
-+		need_indicate_scan_done = _TRUE;
-+		goto check_need_indicate_scan_done;
-+	}
-+
-+#else
-+
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	if (rtw_mp_mode_check(padapter)) {
-+		RTW_INFO("MP mode block Scan request\n");
-+		ret = -EPERM;
-+		goto exit;
-+	}
-+#endif
-+
-+#ifdef CONFIG_P2P
-+	if (pwdinfo->driver_interface == DRIVER_CFG80211) {
-+		if (request->n_ssids && ssids
-+			&& _rtw_memcmp(ssids[0].ssid, "DIRECT-", 7)
-+			&& rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL)
-+		) {
-+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
-+				rtw_p2p_enable(padapter, P2P_ROLE_DEVICE);
-+			else {
-+				rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
-+				#ifdef CONFIG_DEBUG_CFG80211
-+				RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
-+				#endif
-+			}
-+			rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
-+
-+			if (request->n_channels == 3 &&
-+				request->channels[0]->hw_value == 1 &&
-+				request->channels[1]->hw_value == 6 &&
-+				request->channels[2]->hw_value == 11
-+			)
-+				social_channel = 1;
-+		}
-+	}
-+#endif /*CONFIG_P2P*/
-+
-+	if (request->ie && request->ie_len > 0)
-+		rtw_cfg80211_set_probe_req_wpsp2pie(padapter, (u8 *)request->ie, request->ie_len);
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) {
-+		RTW_INFO(FUNC_ADPT_FMT" blocking scan for under rson scanning process\n", FUNC_ADPT_ARG(padapter));
-+		need_indicate_scan_done = _TRUE;
-+		goto check_need_indicate_scan_done;
-+	}
-+#endif
-+
-+	if (adapter_wdev_data(padapter)->block_scan == _TRUE) {
-+		RTW_INFO(FUNC_ADPT_FMT" wdev_priv.block_scan is set\n", FUNC_ADPT_ARG(padapter));
-+		need_indicate_scan_done = _TRUE;
-+		goto check_need_indicate_scan_done;
-+	}
-+
-+	rtw_ps_deny(padapter, PS_DENY_SCAN);
-+	ps_denied = _TRUE;
-+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
-+		need_indicate_scan_done = _TRUE;
-+		goto check_need_indicate_scan_done;
-+	}
-+
-+	if (rtw_is_scan_deny(padapter)) {
-+		RTW_INFO(FUNC_ADPT_FMT	": scan deny\n", FUNC_ADPT_ARG(padapter));
-+#ifdef CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY
-+		ret = -EBUSY;
-+		goto exit;
-+#else
-+		need_indicate_scan_done = _TRUE;
-+		goto check_need_indicate_scan_done;
-+#endif
-+	}
-+
-+	/* check fw state*/
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
-+
-+#ifdef CONFIG_DEBUG_CFG80211
-+		RTW_INFO(FUNC_ADPT_FMT" under WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter));
-+#endif
-+
-+		if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS | WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING) == _TRUE) {
-+			RTW_INFO("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state);
-+
-+			if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS))
-+				RTW_INFO("AP mode process WPS\n");
-+
-+			need_indicate_scan_done = _TRUE;
-+			goto check_need_indicate_scan_done;
-+		}
-+	}
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE) {
-+		RTW_INFO("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state);
-+		need_indicate_scan_done = _TRUE;
-+		goto check_need_indicate_scan_done;
-+	} else if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) {
-+		RTW_INFO("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state);
-+		ret = -EBUSY;
-+		goto check_need_indicate_scan_done;
-+	}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)) {
-+		RTW_INFO("%s exit due to buddy_intf's mlme state under linking or wps\n", __func__);
-+		need_indicate_scan_done = _TRUE;
-+		goto check_need_indicate_scan_done;
-+
-+	} else if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_SURVEY)) {
-+		bool scan_via_buddy = rtw_cfg80211_scan_via_buddy(padapter, request);
-+
-+		if (scan_via_buddy == _FALSE)
-+			need_indicate_scan_done = _TRUE;
-+
-+		goto check_need_indicate_scan_done;
-+	}
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+#ifdef RTW_BUSY_DENY_SCAN
-+	/*
-+	 * busy traffic check
-+	 * Rules:
-+	 * 1. If (scan interval <= BUSY_TRAFFIC_SCAN_DENY_PERIOD) always allow
-+	 *    scan, otherwise goto rule 2.
-+	 * 2. Deny scan if any interface is busy, otherwise allow scan.
-+	 */
-+	if (pmlmepriv->lastscantime
-+	    && (rtw_get_passing_time_ms(pmlmepriv->lastscantime) >
-+		registry_par->scan_interval_thr)
-+	    && rtw_mi_busy_traffic_check(padapter)) {
-+		RTW_WARN(FUNC_ADPT_FMT ": scan abort!! BusyTraffic\n",
-+			 FUNC_ADPT_ARG(padapter));
-+ 		need_indicate_scan_done = _TRUE;
-+		goto check_need_indicate_scan_done;
-+	}
-+#endif /* RTW_BUSY_DENY_SCAN */
-+#endif
-+
-+#ifdef CONFIG_P2P
-+	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {
-+		rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
-+
-+		if (social_channel == 0)
-+			rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE);
-+		else
-+			rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_SOCIAL_LAST);
-+	}
-+#endif /* CONFIG_P2P */
-+
-+	rtw_init_sitesurvey_parm(padapter, &parm);
-+
-+	/* parsing request ssids, n_ssids */
-+	for (i = 0; i < request->n_ssids && ssids && i < RTW_SSID_SCAN_AMOUNT; i++) {
-+		#ifdef CONFIG_DEBUG_CFG80211
-+		RTW_INFO("ssid=%s, len=%d\n", ssids[i].ssid, ssids[i].ssid_len);
-+		#endif
-+		_rtw_memcpy(&parm.ssid[i].Ssid, ssids[i].ssid, ssids[i].ssid_len);
-+		parm.ssid[i].SsidLength = ssids[i].ssid_len;
-+	}
-+	parm.ssid_num = i;
-+
-+	/* no ssid entry, set the scan type as passvie */
-+	if (request->n_ssids == 0)
-+		parm.scan_mode = SCAN_PASSIVE;
-+
-+	/* parsing channels, n_channels */
-+	for (i = 0; i < request->n_channels && i < RTW_CHANNEL_SCAN_AMOUNT; i++) {
-+		#ifdef CONFIG_DEBUG_CFG80211
-+		RTW_INFO(FUNC_ADPT_FMT CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(request->channels[i]));
-+		#endif
-+		parm.ch[i].hw_value = request->channels[i]->hw_value;
-+		parm.ch[i].flags = request->channels[i]->flags;
-+	}
-+	parm.ch_num = i;
-+
-+	if (request->n_channels == 1) {
-+		for (i = 1; i < survey_times_for_one_ch; i++)
-+			_rtw_memcpy(&parm.ch[i], &parm.ch[0], sizeof(struct rtw_ieee80211_channel));
-+		parm.ch_num = survey_times_for_one_ch;
-+	} else if (request->n_channels <= 4) {
-+		for (j = request->n_channels - 1; j >= 0; j--)
-+			for (i = 0; i < survey_times; i++)
-+				_rtw_memcpy(&parm.ch[j * survey_times + i], &parm.ch[j], sizeof(struct rtw_ieee80211_channel));
-+		parm.ch_num = survey_times * request->n_channels;
-+	}
-+
-+	_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+	_status = rtw_sitesurvey_cmd(padapter, &parm);
-+	if (_status == _SUCCESS)
-+		pwdev_priv->scan_request = request;
-+	else
-+		ret = -1;
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+	_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
-+
-+check_need_indicate_scan_done:
-+	if (_TRUE == need_indicate_scan_done) {
-+#if (KERNEL_VERSION(4, 8, 0) <= LINUX_VERSION_CODE)
-+		struct cfg80211_scan_info info;
-+
-+		memset(&info, 0, sizeof(info));
-+		info.aborted = 0;
-+#endif
-+		/* the process time of scan results must be over at least 1ms in the newly Android */
-+		rtw_msleep_os(1); 
-+
-+		_rtw_cfg80211_surveydone_event_callback(padapter, request);
-+#if (KERNEL_VERSION(4, 8, 0) <= LINUX_VERSION_CODE)
-+		cfg80211_scan_done(request, &info);
-+#else
-+		cfg80211_scan_done(request, 0);
-+#endif
-+	}
-+
-+	if (ps_denied == _TRUE)
-+		rtw_ps_deny_cancel(padapter, PS_DENY_SCAN);
-+
-+exit:
-+#ifdef RTW_BUSY_DENY_SCAN
-+	if (pmlmepriv)
-+		pmlmepriv->lastscantime = rtw_get_current_time();
-+#endif
-+
-+	return ret;
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 5, 0)) && \
-+    defined(CONFIG_RTW_ABORT_SCAN)
-+static void cfg80211_rtw_abort_scan(struct wiphy *wiphy,
-+				    struct wireless_dev *wdev)
-+{
-+	_adapter *padapter = wiphy_to_adapter(wiphy);
-+
-+	RTW_INFO("=>"FUNC_ADPT_FMT" - Abort Scan\n", FUNC_ADPT_ARG(padapter));
-+	if (wdev->iftype != NL80211_IFTYPE_STATION) {
-+		RTW_ERR("abort scan ignored, iftype(%d)\n", wdev->iftype);
-+		return;
-+	}
-+	rtw_scan_abort(padapter);
-+}
-+#endif
-+
-+static int cfg80211_rtw_set_wiphy_params(struct wiphy *wiphy, u32 changed)
-+{
-+#if 0
-+	struct iwm_priv *iwm = wiphy_to_iwm(wiphy);
-+
-+	if (changed & WIPHY_PARAM_RTS_THRESHOLD &&
-+	    (iwm->conf.rts_threshold != wiphy->rts_threshold)) {
-+		int ret;
-+
-+		iwm->conf.rts_threshold = wiphy->rts_threshold;
-+
-+		ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX,
-+				CFG_RTS_THRESHOLD,
-+				iwm->conf.rts_threshold);
-+		if (ret < 0)
-+			return ret;
-+	}
-+
-+	if (changed & WIPHY_PARAM_FRAG_THRESHOLD &&
-+	    (iwm->conf.frag_threshold != wiphy->frag_threshold)) {
-+		int ret;
-+
-+		iwm->conf.frag_threshold = wiphy->frag_threshold;
-+
-+		ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_FA_CFG_FIX,
-+				CFG_FRAG_THRESHOLD,
-+				iwm->conf.frag_threshold);
-+		if (ret < 0)
-+			return ret;
-+	}
-+#endif
-+	RTW_INFO("%s\n", __func__);
-+	return 0;
-+}
-+
-+
-+
-+static int rtw_cfg80211_set_wpa_version(struct security_priv *psecuritypriv, u32 wpa_version)
-+{
-+	RTW_INFO("%s, wpa_version=%d\n", __func__, wpa_version);
-+
-+	if (!wpa_version) {
-+		psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
-+		return 0;
-+	}
-+
-+
-+	if (wpa_version & (NL80211_WPA_VERSION_1 | NL80211_WPA_VERSION_2))
-+		psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK;
-+
-+#if 0
-+	if (wpa_version & NL80211_WPA_VERSION_2)
-+		psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK;
-+#endif
-+
-+	#ifdef CONFIG_WAPI_SUPPORT
-+	if (wpa_version & NL80211_WAPI_VERSION_1)
-+		psecuritypriv->ndisauthtype = Ndis802_11AuthModeWAPI;
-+	#endif
-+
-+	return 0;
-+
-+}
-+
-+static int rtw_cfg80211_set_auth_type(struct security_priv *psecuritypriv,
-+		enum nl80211_auth_type sme_auth_type)
-+{
-+	RTW_INFO("%s, nl80211_auth_type=%d\n", __func__, sme_auth_type);
-+
-+	if (NL80211_AUTHTYPE_MAX <= (int)MLME_AUTHTYPE_SAE) {
-+		if (MLME_AUTHTYPE_SAE == psecuritypriv->auth_type) {
-+			/* This case pre handle in
-+			 * rtw_check_connect_sae_compat()
-+			 */
-+			psecuritypriv->auth_alg = WLAN_AUTH_SAE;
-+			return 0;
-+		}
-+	} else if (sme_auth_type == (int)MLME_AUTHTYPE_SAE) {
-+		psecuritypriv->auth_type = MLME_AUTHTYPE_SAE;
-+		psecuritypriv->auth_alg = WLAN_AUTH_SAE;
-+		return 0;
-+	}
-+
-+	psecuritypriv->auth_type = sme_auth_type;
-+
-+	switch (sme_auth_type) {
-+	case NL80211_AUTHTYPE_AUTOMATIC:
-+
-+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
-+
-+		break;
-+	case NL80211_AUTHTYPE_OPEN_SYSTEM:
-+
-+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
-+
-+		if (psecuritypriv->ndisauthtype > Ndis802_11AuthModeWPA)
-+			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+		if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWAPI)
-+			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
-+#endif
-+
-+		break;
-+	case NL80211_AUTHTYPE_SHARED_KEY:
-+
-+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Shared;
-+
-+		psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+
-+
-+		break;
-+	default:
-+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
-+		/* return -ENOTSUPP; */
-+	}
-+
-+	return 0;
-+
-+}
-+
-+static int rtw_cfg80211_set_cipher(struct security_priv *psecuritypriv, u32 cipher, bool ucast)
-+{
-+	u32 ndisencryptstatus = Ndis802_11EncryptionDisabled;
-+
-+	u32 *profile_cipher = ucast ? &psecuritypriv->dot11PrivacyAlgrthm :
-+		&psecuritypriv->dot118021XGrpPrivacy;
-+
-+	RTW_INFO("%s, ucast=%d, cipher=0x%x\n", __func__, ucast, cipher);
-+
-+
-+	if (!cipher) {
-+		*profile_cipher = _NO_PRIVACY_;
-+		psecuritypriv->ndisencryptstatus = ndisencryptstatus;
-+		return 0;
-+	}
-+
-+	switch (cipher) {
-+	case IW_AUTH_CIPHER_NONE:
-+		*profile_cipher = _NO_PRIVACY_;
-+		ndisencryptstatus = Ndis802_11EncryptionDisabled;
-+#ifdef CONFIG_WAPI_SUPPORT
-+		if (psecuritypriv->dot11PrivacyAlgrthm == _SMS4_)
-+			*profile_cipher = _SMS4_;
-+#endif
-+		break;
-+	case WLAN_CIPHER_SUITE_WEP40:
-+		*profile_cipher = _WEP40_;
-+		ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+		break;
-+	case WLAN_CIPHER_SUITE_WEP104:
-+		*profile_cipher = _WEP104_;
-+		ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+		break;
-+	case WLAN_CIPHER_SUITE_TKIP:
-+		*profile_cipher = _TKIP_;
-+		ndisencryptstatus = Ndis802_11Encryption2Enabled;
-+		break;
-+	case WLAN_CIPHER_SUITE_CCMP:
-+		*profile_cipher = _AES_;
-+		ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+		break;
-+	case WIFI_CIPHER_SUITE_GCMP:
-+		*profile_cipher = _GCMP_;
-+		ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+		break;
-+	case WIFI_CIPHER_SUITE_GCMP_256:
-+		*profile_cipher = _GCMP_256_;
-+		ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+		break;
-+	case WIFI_CIPHER_SUITE_CCMP_256:
-+		*profile_cipher = _CCMP_256_;
-+		ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+		break;
-+#ifdef CONFIG_WAPI_SUPPORT
-+	case WLAN_CIPHER_SUITE_SMS4:
-+		*profile_cipher = _SMS4_;
-+		ndisencryptstatus = Ndis802_11_EncrypteionWAPI;
-+		break;
-+#endif
-+	default:
-+		RTW_INFO("Unsupported cipher: 0x%x\n", cipher);
-+		return -ENOTSUPP;
-+	}
-+
-+	if (ucast) {
-+		psecuritypriv->ndisencryptstatus = ndisencryptstatus;
-+
-+		/* if(psecuritypriv->dot11PrivacyAlgrthm >= _AES_) */
-+		/*	psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK; */
-+	}
-+
-+	return 0;
-+}
-+
-+static int rtw_cfg80211_set_key_mgt(struct security_priv *psecuritypriv, u32 key_mgt)
-+{
-+	RTW_INFO("%s, key_mgt=0x%x\n", __func__, key_mgt);
-+
-+	if (key_mgt == WLAN_AKM_SUITE_8021X) {
-+		/* *auth_type = UMAC_AUTH_TYPE_8021X; */
-+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
-+		psecuritypriv->rsn_akm_suite_type = 1;
-+	} else if (key_mgt == WLAN_AKM_SUITE_PSK) {
-+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
-+		psecuritypriv->rsn_akm_suite_type = 2;
-+	}
-+#ifdef CONFIG_WAPI_SUPPORT
-+	else if (key_mgt == WLAN_AKM_SUITE_WAPI_PSK)
-+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
-+	else if (key_mgt == WLAN_AKM_SUITE_WAPI_CERT)
-+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
-+#endif
-+#ifdef CONFIG_RTW_80211R
-+	else if (key_mgt == WLAN_AKM_SUITE_FT_8021X) {
-+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
-+		psecuritypriv->rsn_akm_suite_type = 3;
-+	} else if (key_mgt == WLAN_AKM_SUITE_FT_PSK) {
-+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
-+		psecuritypriv->rsn_akm_suite_type = 4;
-+	}
-+#endif
-+	else if (key_mgt == WLAN_AKM_SUITE_SAE) { 
-+		psecuritypriv->rsn_akm_suite_type = 8; 
-+	} else {
-+		RTW_INFO("Invalid key mgt: 0x%x\n", key_mgt);
-+		/* return -EINVAL; */
-+	}
-+
-+	return 0;
-+}
-+
-+static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen)
-+{
-+	u8 *buf = NULL, *pos = NULL;
-+	int group_cipher = 0, pairwise_cipher = 0;
-+	u8 mfp_opt = MFP_NO;
-+	int ret = 0;
-+	int wpa_ielen = 0;
-+	int wpa2_ielen = 0;
-+	u8 *pwpa, *pwpa2;
-+	u8 null_addr[] = {0, 0, 0, 0, 0, 0};
-+
-+	if (pie == NULL || !ielen) {
-+		/* Treat this as normal case, but need to clear WIFI_UNDER_WPS */
-+		_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
-+		goto exit;
-+	}
-+
-+	if (ielen > MAX_WPA_IE_LEN + MAX_WPS_IE_LEN + MAX_P2P_IE_LEN) {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	buf = rtw_zmalloc(ielen);
-+	if (buf == NULL) {
-+		ret =  -ENOMEM;
-+		goto exit;
-+	}
-+
-+	_rtw_memcpy(buf, pie , ielen);
-+
-+	RTW_INFO("set wpa_ie(length:%zu):\n", ielen);
-+	RTW_INFO_DUMP(NULL, buf, ielen);
-+
-+	pos = buf;
-+	if (ielen < RSN_HEADER_LEN) {
-+		ret  = -1;
-+		goto exit;
-+	}
-+
-+	pwpa = rtw_get_wpa_ie(buf, &wpa_ielen, ielen);
-+	if (pwpa && wpa_ielen > 0) {
-+		if (rtw_parse_wpa_ie(pwpa, wpa_ielen + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
-+			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
-+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK;
-+			_rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa[0], wpa_ielen + 2);
-+
-+			RTW_INFO("got wpa_ie, wpa_ielen:%u\n", wpa_ielen);
-+		}
-+	}
-+
-+	pwpa2 = rtw_get_wpa2_ie(buf, &wpa2_ielen, ielen);
-+	if (pwpa2 && wpa2_ielen > 0) {
-+		if (rtw_parse_wpa2_ie(pwpa2, wpa2_ielen + 2, &group_cipher, &pairwise_cipher, NULL, NULL, &mfp_opt) == _SUCCESS) {
-+			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
-+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK;
-+			_rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa2[0], wpa2_ielen + 2);
-+
-+			RTW_INFO("got wpa2_ie, wpa2_ielen:%u\n", wpa2_ielen);
-+		}
-+	}
-+
-+	if (group_cipher == 0)
-+		group_cipher = WPA_CIPHER_NONE;
-+	if (pairwise_cipher == 0)
-+		pairwise_cipher = WPA_CIPHER_NONE;
-+
-+	switch (group_cipher) {
-+	case WPA_CIPHER_NONE:
-+		padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
-+		break;
-+	case WPA_CIPHER_WEP40:
-+		padapter->securitypriv.dot118021XGrpPrivacy = _WEP40_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+		break;
-+	case WPA_CIPHER_TKIP:
-+		padapter->securitypriv.dot118021XGrpPrivacy = _TKIP_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
-+		break;
-+	case WPA_CIPHER_CCMP:
-+		padapter->securitypriv.dot118021XGrpPrivacy = _AES_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+		break;
-+	case WPA_CIPHER_GCMP:
-+		padapter->securitypriv.dot118021XGrpPrivacy = _GCMP_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+		break;
-+	case WPA_CIPHER_GCMP_256:
-+		padapter->securitypriv.dot118021XGrpPrivacy = _GCMP_256_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+		break;
-+	case WPA_CIPHER_CCMP_256:
-+		padapter->securitypriv.dot118021XGrpPrivacy = _CCMP_256_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+		break;
-+	case WPA_CIPHER_WEP104:
-+		padapter->securitypriv.dot118021XGrpPrivacy = _WEP104_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+		break;
-+	}
-+
-+	switch (pairwise_cipher) {
-+	case WPA_CIPHER_NONE:
-+		padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
-+		break;
-+	case WPA_CIPHER_WEP40:
-+		padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+		break;
-+	case WPA_CIPHER_TKIP:
-+		padapter->securitypriv.dot11PrivacyAlgrthm = _TKIP_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
-+		break;
-+	case WPA_CIPHER_CCMP:
-+		padapter->securitypriv.dot11PrivacyAlgrthm = _AES_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+		break;
-+	case WPA_CIPHER_GCMP:
-+		padapter->securitypriv.dot11PrivacyAlgrthm = _GCMP_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+		break;
-+	case WPA_CIPHER_GCMP_256:
-+		padapter->securitypriv.dot11PrivacyAlgrthm = _GCMP_256_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+		break;
-+	case WPA_CIPHER_CCMP_256:
-+		padapter->securitypriv.dot11PrivacyAlgrthm = _CCMP_256_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+		break;
-+	case WPA_CIPHER_WEP104:
-+		padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+		break;
-+	}
-+
-+	if (mfp_opt == MFP_INVALID) {
-+		RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter));
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+	padapter->securitypriv.mfp_opt = mfp_opt;
-+
-+	{/* handle wps_ie */
-+		uint wps_ielen;
-+		u8 *wps_ie;
-+
-+		wps_ie = rtw_get_wps_ie(buf, ielen, NULL, &wps_ielen);
-+		if (wps_ie && wps_ielen > 0) {
-+			RTW_INFO("got wps_ie, wps_ielen:%u\n", wps_ielen);
-+			padapter->securitypriv.wps_ie_len = wps_ielen < MAX_WPS_IE_LEN ? wps_ielen : MAX_WPS_IE_LEN;
-+			_rtw_memcpy(padapter->securitypriv.wps_ie, wps_ie, padapter->securitypriv.wps_ie_len);
-+			set_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS);
-+		} else
-+			_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
-+	}
-+
-+	{/* handle owe_ie */
-+		uint owe_ielen;
-+		u8 *owe_ie;
-+
-+		owe_ie = rtw_get_owe_ie(buf, ielen, NULL, &owe_ielen);
-+		if (owe_ie && owe_ielen > 0) {
-+			RTW_INFO("got owe_ie, owe_ielen:%u\n", owe_ielen);
-+			padapter->securitypriv.owe_ie_len = owe_ielen < MAX_OWE_IE_LEN ? owe_ielen : MAX_OWE_IE_LEN;
-+			_rtw_memcpy(padapter->securitypriv.owe_ie, owe_ie, padapter->securitypriv.owe_ie_len);
-+		}
-+	}
-+
-+	#ifdef CONFIG_P2P
-+	{/* check p2p_ie for assoc req; */
-+		uint p2p_ielen = 0;
-+		u8 *p2p_ie;
-+		struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+		p2p_ie = rtw_get_p2p_ie(buf, ielen, NULL, &p2p_ielen);
-+		if (p2p_ie) {
-+			#ifdef CONFIG_DEBUG_CFG80211
-+			RTW_INFO("%s p2p_assoc_req_ielen=%d\n", __FUNCTION__, p2p_ielen);
-+			#endif
-+
-+			if (pmlmepriv->p2p_assoc_req_ie) {
-+				u32 free_len = pmlmepriv->p2p_assoc_req_ie_len;
-+				pmlmepriv->p2p_assoc_req_ie_len = 0;
-+				rtw_mfree(pmlmepriv->p2p_assoc_req_ie, free_len);
-+				pmlmepriv->p2p_assoc_req_ie = NULL;
-+			}
-+
-+			pmlmepriv->p2p_assoc_req_ie = rtw_malloc(p2p_ielen);
-+			if (pmlmepriv->p2p_assoc_req_ie == NULL) {
-+				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
-+				goto exit;
-+			}
-+			_rtw_memcpy(pmlmepriv->p2p_assoc_req_ie, p2p_ie, p2p_ielen);
-+			pmlmepriv->p2p_assoc_req_ie_len = p2p_ielen;
-+		}
-+	}
-+	#endif /* CONFIG_P2P */
-+
-+	#ifdef CONFIG_WFD
-+	{
-+		uint wfd_ielen = 0;
-+		u8 *wfd_ie;
-+		struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+		wfd_ie = rtw_get_wfd_ie(buf, ielen, NULL, &wfd_ielen);
-+		if (wfd_ie) {
-+			#ifdef CONFIG_DEBUG_CFG80211
-+			RTW_INFO("%s wfd_assoc_req_ielen=%d\n", __FUNCTION__, wfd_ielen);
-+			#endif
-+
-+			if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_ASSOC_REQ_IE, wfd_ie, wfd_ielen) != _SUCCESS)
-+				goto exit;
-+		}
-+	}
-+	#endif /* CONFIG_WFD */
-+
-+	#ifdef CONFIG_RTW_MULTI_AP
-+	padapter->multi_ap = rtw_get_multi_ap_ie_ext(buf, ielen) & MULTI_AP_BACKHAUL_STA;
-+	if (padapter->multi_ap)
-+		adapter_set_use_wds(padapter, 1);
-+	#endif
-+
-+	/* TKIP and AES disallow multicast packets until installing group key */
-+	if (padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_
-+		|| padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_
-+		|| padapter->securitypriv.dot11PrivacyAlgrthm == _AES_
-+		|| padapter->securitypriv.dot11PrivacyAlgrthm == _GCMP_
-+		|| padapter->securitypriv.dot11PrivacyAlgrthm == _GCMP_256_
-+		|| padapter->securitypriv.dot11PrivacyAlgrthm == _CCMP_256_)
-+		/* WPS open need to enable multicast */
-+		/* || check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr);
-+
-+
-+exit:
-+	if (buf)
-+		rtw_mfree(buf, ielen);
-+	if (ret)
-+		_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
-+
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev,
-+				  struct cfg80211_ibss_params *params)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	NDIS_802_11_SSID ndis_ssid;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	struct cfg80211_chan_def *pch_def;
-+#endif
-+	struct ieee80211_channel *pch;
-+	int ret = 0;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	pch_def = (struct cfg80211_chan_def *)(&params->chandef);
-+	pch = (struct ieee80211_channel *) pch_def->chan;
-+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
-+	pch = (struct ieee80211_channel *)(params->channel);
-+#endif
-+
-+	if (!params->ssid || !params->ssid_len) {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	if (params->ssid_len > IW_ESSID_MAX_SIZE) {
-+		ret = -E2BIG;
-+		goto exit;
-+	}
-+
-+	rtw_ps_deny(padapter, PS_DENY_JOIN);
-+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
-+		ret = -EPERM;
-+		goto cancel_ps_deny;
-+	}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING)) {
-+		RTW_INFO("%s, but buddy_intf is under linking\n", __FUNCTION__);
-+		ret = -EINVAL;
-+		goto cancel_ps_deny;
-+	}
-+	rtw_mi_buddy_scan_abort(padapter, _TRUE); /* OR rtw_mi_scan_abort(padapter, _TRUE);*/
-+#endif /*CONFIG_CONCURRENT_MODE*/
-+
-+
-+	_rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));
-+	ndis_ssid.SsidLength = params->ssid_len;
-+	_rtw_memcpy(ndis_ssid.Ssid, (u8 *)params->ssid, params->ssid_len);
-+
-+	/* RTW_INFO("ssid=%s, len=%zu\n", ndis_ssid.Ssid, params->ssid_len); */
-+
-+	psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;
-+	psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
-+	psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
-+	psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
-+	psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
-+
-+	ret = rtw_cfg80211_set_auth_type(psecuritypriv, NL80211_AUTHTYPE_OPEN_SYSTEM);
-+	rtw_set_802_11_authentication_mode(padapter, psecuritypriv->ndisauthtype);
-+
-+	RTW_INFO("%s: center_freq = %d\n", __func__, pch->center_freq);
-+	pmlmeext->cur_channel = rtw_freq2ch(pch->center_freq);
-+
-+	if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) {
-+		ret = -1;
-+		goto cancel_ps_deny;
-+	}
-+
-+cancel_ps_deny:
-+	rtw_ps_deny_cancel(padapter, PS_DENY_JOIN);
-+exit:
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct wireless_dev *rtw_wdev = padapter->rtw_wdev;
-+	enum nl80211_iftype old_type;
-+	int ret = 0;
-+
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
-+
-+#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
-+	rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 1);
-+#endif
-+
-+	old_type = rtw_wdev->iftype;
-+
-+	rtw_set_to_roam(padapter, 0);
-+
-+	if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) {
-+		rtw_scan_abort(padapter);
-+		LeaveAllPowerSaveMode(padapter);
-+
-+		rtw_wdev->iftype = NL80211_IFTYPE_STATION;
-+
-+		if (rtw_set_802_11_infrastructure_mode(padapter, Ndis802_11Infrastructure, 0) == _FALSE) {
-+			rtw_wdev->iftype = old_type;
-+			ret = -EPERM;
-+			goto leave_ibss;
-+		}
-+		rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK);
-+	}
-+
-+leave_ibss:
-+#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
-+	rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 0);
-+#endif
-+
-+	return 0;
-+}
-+
-+bool rtw_cfg80211_is_connect_requested(_adapter *adapter)
-+{
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
-+	_irqL irqL;
-+	bool requested;
-+
-+	_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
-+	requested = pwdev_priv->connect_req ? 1 : 0;
-+	_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
-+
-+	return requested;
-+}
-+
-+static int _rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+
-+
-+	/* if(check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) */
-+	{
-+		rtw_scan_abort(padapter);
-+		rtw_join_abort_timeout(padapter, 300);
-+		LeaveAllPowerSaveMode(padapter);
-+		rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK);
-+#ifdef CONFIG_RTW_REPEATER_SON
-+		rtw_rson_do_disconnect(padapter);
-+#endif
-+		RTW_INFO("%s...call rtw_indicate_disconnect\n", __func__);
-+
-+		rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK);
-+
-+		/* indicate locally_generated = 0 when suspend */
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0))
-+		rtw_indicate_disconnect(padapter, 0, wiphy->dev.power.is_prepared ? _FALSE : _TRUE);
-+		#else
-+		/*
-+		* for kernel < 4.2, DISCONNECT event is hardcoded with
-+		* NL80211_ATTR_DISCONNECTED_BY_AP=1 in NL80211 layer
-+		* no need to judge if under suspend
-+		*/
-+		rtw_indicate_disconnect(padapter, 0, _TRUE);
-+		#endif
-+
-+		rtw_pwr_wakeup(padapter);
-+	}
-+	return 0;
-+}
-+
-+#if (KERNEL_VERSION(4, 17, 0) > LINUX_VERSION_CODE) \
-+    && !defined(CONFIG_KERNEL_PATCH_EXTERNAL_AUTH)
-+static bool rtw_check_connect_sae_compat(struct cfg80211_connect_params *sme)
-+{
-+	struct rtw_ieee802_11_elems elems;
-+	struct rsne_info info;
-+	u8 AKM_SUITE_SAE[] = { 0x00, 0x0f, 0xac, 8 };
-+	int i;
-+
-+	if (sme->auth_type != (int)MLME_AUTHTYPE_SHARED_KEY)
-+		return false;
-+
-+	if (rtw_ieee802_11_parse_elems((u8 *)sme->ie, sme->ie_len, &elems, 0)
-+	    == ParseFailed)
-+		return false;
-+
-+	if (!elems.rsn_ie)
-+		return false;
-+
-+	if (rtw_rsne_info_parse(elems.rsn_ie - 2, elems.rsn_ie_len + 2, &info) == _FAIL)
-+		return false;
-+
-+	for (i = 0; i < info.akm_cnt; i++)
-+		if (memcmp(info.akm_list + i * RSN_SELECTOR_LEN,
-+			   AKM_SUITE_SAE, RSN_SELECTOR_LEN) == 0)
-+			return true;
-+
-+	return false;
-+}
-+#else
-+#define rtw_check_connect_sae_compat(sme)	false
-+#endif
-+
-+static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev,
-+				struct cfg80211_connect_params *sme)
-+{
-+	int ret = 0;
-+	NDIS_802_11_AUTHENTICATION_MODE authmode;
-+	NDIS_802_11_SSID ndis_ssid;
-+	/* u8 matched_by_bssid=_FALSE; */
-+	/* u8 matched_by_ssid=_FALSE; */
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	_irqL irqL;
-+
-+#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT)
-+	rtw_wdev_set_not_indic_disco(pwdev_priv, 1);
-+#endif
-+
-+	RTW_INFO("=>"FUNC_NDEV_FMT" - Start to Connection\n", FUNC_NDEV_ARG(ndev));
-+	RTW_INFO("privacy=%d, key=%p, key_len=%d, key_idx=%d, auth_type=%d\n",
-+		sme->privacy, sme->key, sme->key_len, sme->key_idx, sme->auth_type);
-+
-+	if (rtw_check_connect_sae_compat(sme)) {
-+		sme->auth_type = (int)MLME_AUTHTYPE_SAE;
-+		psecuritypriv->auth_type = MLME_AUTHTYPE_SAE;
-+		psecuritypriv->auth_alg = WLAN_AUTH_SAE;
-+		RTW_INFO("%s set sme->auth_type for SAE compat\n", __FUNCTION__);
-+	}
-+
-+	if (pwdev_priv->block == _TRUE) {
-+		ret = -EBUSY;
-+		RTW_INFO("%s wdev_priv.block is set\n", __FUNCTION__);
-+		goto exit;
-+	}
-+
-+       if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_LINKING) == _TRUE) {
-+
-+		_rtw_disconnect(wiphy, ndev);
-+		RTW_INFO("%s disconnect before connecting! fw_state=0x%x\n",
-+			__FUNCTION__, pmlmepriv->fw_state);
-+	}
-+
-+#ifdef CONFIG_PLATFORM_MSTAR_SCAN_BEFORE_CONNECT
-+	printk("MStar Android!\n");
-+	if (pwdev_priv->bandroid_scan == _FALSE) {
-+#ifdef CONFIG_P2P
-+		struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
-+#endif /* CONFIG_P2P */
-+		{
-+			ret = -EBUSY;
-+			printk("Android hasn't attached yet!\n");
-+			goto exit;
-+		}
-+	}
-+#endif
-+
-+	if (!sme->ssid || !sme->ssid_len) {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	if (sme->ssid_len > IW_ESSID_MAX_SIZE) {
-+		ret = -E2BIG;
-+		goto exit;
-+	}
-+
-+	rtw_ps_deny(padapter, PS_DENY_JOIN);
-+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
-+		ret = -EPERM;
-+		goto cancel_ps_deny;
-+	}
-+
-+	rtw_mi_scan_abort(padapter, _TRUE);
-+
-+	rtw_join_abort_timeout(padapter, 300);
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_LINKING)) {
-+		ret = -EINVAL;
-+		goto cancel_ps_deny;
-+	}
-+#endif
-+
-+	_rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));
-+	ndis_ssid.SsidLength = sme->ssid_len;
-+	_rtw_memcpy(ndis_ssid.Ssid, (u8 *)sme->ssid, sme->ssid_len);
-+
-+	RTW_INFO("ssid=%s, len=%zu\n", ndis_ssid.Ssid, sme->ssid_len);
-+
-+
-+	if (sme->bssid)
-+		RTW_INFO("bssid="MAC_FMT"\n", MAC_ARG(sme->bssid));
-+
-+
-+	psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;
-+	psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
-+	psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
-+	psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
-+	psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
-+	psecuritypriv->auth_alg = WLAN_AUTH_OPEN;
-+	psecuritypriv->extauth_status = WLAN_STATUS_UNSPECIFIED_FAILURE;
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	padapter->wapiInfo.bWapiEnable = false;
-+#endif
-+
-+	ret = rtw_cfg80211_set_wpa_version(psecuritypriv, sme->crypto.wpa_versions);
-+	if (ret < 0)
-+		goto cancel_ps_deny;
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	if (sme->crypto.wpa_versions & NL80211_WAPI_VERSION_1) {
-+		padapter->wapiInfo.bWapiEnable = true;
-+		padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN;
-+		padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN;
-+	}
-+#endif
-+
-+	ret = rtw_cfg80211_set_auth_type(psecuritypriv, sme->auth_type);
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_WAPI)
-+		padapter->mlmeextpriv.mlmext_info.auth_algo = psecuritypriv->dot11AuthAlgrthm;
-+#endif
-+
-+
-+	if (ret < 0)
-+		goto cancel_ps_deny;
-+
-+	RTW_INFO("%s, ie_len=%zu\n", __func__, sme->ie_len);
-+
-+	ret = rtw_cfg80211_set_wpa_ie(padapter, (u8 *)sme->ie, sme->ie_len);
-+	if (ret < 0)
-+		goto cancel_ps_deny;
-+
-+	if (sme->crypto.n_ciphers_pairwise) {
-+		ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.ciphers_pairwise[0], _TRUE);
-+		if (ret < 0)
-+			goto cancel_ps_deny;
-+	}
-+
-+	/* For WEP Shared auth */
-+	if (sme->key_len > 0 && sme->key) {
-+		u32 wep_key_idx, wep_key_len, wep_total_len;
-+		NDIS_802_11_WEP	*pwep = NULL;
-+		RTW_INFO("%s(): Shared/Auto WEP\n", __FUNCTION__);
-+
-+		wep_key_idx = sme->key_idx;
-+		wep_key_len = sme->key_len;
-+
-+		if (sme->key_idx > WEP_KEYS) {
-+			ret = -EINVAL;
-+			goto cancel_ps_deny;
-+		}
-+
-+		if (wep_key_len > 0) {
-+			wep_key_len = wep_key_len <= 5 ? 5 : 13;
-+			wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);
-+			pwep = (NDIS_802_11_WEP *) rtw_malloc(wep_total_len);
-+			if (pwep == NULL) {
-+				RTW_INFO(" wpa_set_encryption: pwep allocate fail !!!\n");
-+				ret = -ENOMEM;
-+				goto cancel_ps_deny;
-+			}
-+
-+			_rtw_memset(pwep, 0, wep_total_len);
-+
-+			pwep->KeyLength = wep_key_len;
-+			pwep->Length = wep_total_len;
-+
-+			if (wep_key_len == 13) {
-+				padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;
-+				padapter->securitypriv.dot118021XGrpPrivacy = _WEP104_;
-+			}
-+		} else {
-+			ret = -EINVAL;
-+			goto cancel_ps_deny;
-+		}
-+
-+		pwep->KeyIndex = wep_key_idx;
-+		pwep->KeyIndex |= 0x80000000;
-+
-+		_rtw_memcpy(pwep->KeyMaterial, (void *)sme->key, pwep->KeyLength);
-+
-+		if (rtw_set_802_11_add_wep(padapter, pwep) == (u8)_FAIL)
-+			ret = -EOPNOTSUPP ;
-+
-+		if (pwep)
-+			rtw_mfree((u8 *)pwep, wep_total_len);
-+
-+		if (ret < 0)
-+			goto cancel_ps_deny;
-+	}
-+
-+	ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.cipher_group, _FALSE);
-+	if (ret < 0)
-+		return ret;
-+
-+	if (sme->crypto.n_akm_suites) {
-+		ret = rtw_cfg80211_set_key_mgt(psecuritypriv, sme->crypto.akm_suites[0]);
-+		if (ret < 0)
-+			goto cancel_ps_deny;
-+	}
-+#ifdef CONFIG_8011R
-+	else {
-+		/*It could be a connection without RSN IEs*/
-+		psecuritypriv->rsn_akm_suite_type = 0;
-+	}
-+#endif
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	if (sme->crypto.akm_suites[0] == WLAN_AKM_SUITE_WAPI_PSK)
-+		padapter->wapiInfo.bWapiPSK = true;
-+	else if (sme->crypto.akm_suites[0] == WLAN_AKM_SUITE_WAPI_CERT)
-+		padapter->wapiInfo.bWapiPSK = false;
-+#endif
-+
-+	authmode = psecuritypriv->ndisauthtype;
-+	rtw_set_802_11_authentication_mode(padapter, authmode);
-+
-+	/* rtw_set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */
-+
-+#ifdef CONFIG_RTW_MBO
-+	rtw_mbo_update_ie_data(padapter, (u8 *)sme->ie, sme->ie_len);
-+#endif
-+
-+	if (rtw_set_802_11_connect(padapter, (u8 *)sme->bssid, &ndis_ssid, \
-+			sme->channel ? sme->channel->hw_value : 0) == _FALSE) {
-+		ret = -1;
-+		goto cancel_ps_deny;
-+	}
-+
-+
-+	_enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
-+
-+	if (pwdev_priv->connect_req) {
-+		rtw_wdev_free_connect_req(pwdev_priv);
-+		RTW_INFO(FUNC_NDEV_FMT" free existing connect_req\n", FUNC_NDEV_ARG(ndev));
-+	}
-+
-+	pwdev_priv->connect_req = (struct cfg80211_connect_params *)rtw_malloc(sizeof(*pwdev_priv->connect_req));
-+	if (pwdev_priv->connect_req)
-+		_rtw_memcpy(pwdev_priv->connect_req, sme, sizeof(*pwdev_priv->connect_req));
-+	else
-+		RTW_WARN(FUNC_NDEV_FMT" alloc connect_req fail\n", FUNC_NDEV_ARG(ndev));
-+
-+	_exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL);
-+
-+	RTW_INFO("set ssid:dot11AuthAlgrthm=%d, dot11PrivacyAlgrthm=%d, dot118021XGrpPrivacy=%d\n", psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm,
-+		psecuritypriv->dot118021XGrpPrivacy);
-+
-+cancel_ps_deny:
-+	rtw_ps_deny_cancel(padapter, PS_DENY_JOIN);
-+
-+exit:
-+	RTW_INFO("<=%s, ret %d\n", __FUNCTION__, ret);
-+
-+#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT)
-+	rtw_wdev_set_not_indic_disco(pwdev_priv, 0);
-+#endif
-+
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev,
-+				   u16 reason_code)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+
-+	RTW_INFO(FUNC_NDEV_FMT" - Start to Disconnect\n", FUNC_NDEV_ARG(ndev));
-+
-+#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+	if (!wiphy->dev.power.is_prepared)
-+	#endif
-+		rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 1);
-+#endif
-+
-+	rtw_set_to_roam(padapter, 0);
-+
-+	/* if(check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) */
-+	{
-+		_rtw_disconnect(wiphy, ndev);
-+	}
-+
-+#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
-+	rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 0);
-+#endif
-+
-+	RTW_INFO(FUNC_NDEV_FMT" return 0\n", FUNC_NDEV_ARG(ndev));
-+	return 0;
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
-+#ifdef CONFIG_RTW_DEBUG
-+static const char *nl80211_tx_power_setting_str(int type)
-+{
-+	switch (type) {
-+	case NL80211_TX_POWER_AUTOMATIC:
-+		return "AUTO";
-+	case NL80211_TX_POWER_LIMITED:
-+		return "LIMIT";
-+	case NL80211_TX_POWER_FIXED:
-+		return "FIX";
-+	default:
-+		return "UNKNOWN";
-+	};
-+}
-+#endif	/*	CONFIG_RTW_DEBUG	*/
-+
-+static int cfg80211_rtw_set_txpower(struct wiphy *wiphy,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	struct wireless_dev *wdev,
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) || defined(COMPAT_KERNEL_RELEASE)
-+	enum nl80211_tx_power_setting type, int mbm)
-+#else
-+	enum tx_power_setting type, int dbm)
-+#endif
-+{
-+#if !((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) || defined(COMPAT_KERNEL_RELEASE))
-+	int mbm = dbm * 100;
-+#endif
-+	struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy);
-+	_adapter *adapter = wiphy_to_adapter(wiphy);
-+	int ret = -EOPNOTSUPP;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	if (wdev) {
-+		RTW_WARN(FUNC_WIPHY_FMT" wdev specific control is not supported\n", FUNC_WIPHY_ARG(wiphy));
-+		goto exit;
-+	}
-+#endif
-+
-+	RTW_INFO(FUNC_WIPHY_FMT" type:%s(%u) mbm:%d\n", FUNC_WIPHY_ARG(wiphy)
-+		, nl80211_tx_power_setting_str(type), type, mbm);
-+
-+	switch (type) {
-+	case NL80211_TX_POWER_AUTOMATIC:
-+		wiphy_data->txpwr_total_lmt_mbm = UNSPECIFIED_MBM;
-+		wiphy_data->txpwr_total_target_mbm = UNSPECIFIED_MBM;
-+		ret = 0;
-+		break;
-+	case NL80211_TX_POWER_LIMITED:
-+		if (!phy_is_txpwr_user_mbm_valid(adapter, mbm)) {
-+			RTW_WARN(FUNC_WIPHY_FMT" mbm:%d not support\n", FUNC_WIPHY_ARG(wiphy), mbm);
-+			goto exit;
-+		}
-+		wiphy_data->txpwr_total_lmt_mbm = mbm;
-+		wiphy_data->txpwr_total_target_mbm = UNSPECIFIED_MBM;
-+		ret = 0;
-+		break;
-+	case NL80211_TX_POWER_FIXED:
-+		if (!phy_is_txpwr_user_mbm_valid(adapter, mbm)) {
-+			RTW_WARN(FUNC_WIPHY_FMT" mbm:%d not support\n", FUNC_WIPHY_ARG(wiphy), mbm);
-+			goto exit;
-+		}
-+		wiphy_data->txpwr_total_lmt_mbm = UNSPECIFIED_MBM;
-+		wiphy_data->txpwr_total_target_mbm = mbm;
-+		ret = 0;
-+		break;
-+	default:
-+		RTW_WARN(FUNC_WIPHY_FMT" unknown type:%d\n", FUNC_WIPHY_ARG(wiphy), type);
-+	}
-+
-+	if (ret == 0)
-+		rtw_run_in_thread_cmd_wait(adapter, ((void *)(rtw_hal_update_txpwr_level)), adapter, 2000);
-+
-+exit:
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_get_txpower(struct wiphy *wiphy,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	struct wireless_dev *wdev,
-+#endif
-+	int *dbm)
-+{
-+	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
-+	s16 mbm;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	if (wdev && wdev_to_ndev(wdev)) {
-+		_adapter *adapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
-+		mbm = rtw_adapter_get_oper_txpwr_max_mbm(adapter, 1);
-+		RTW_INFO(FUNC_ADPT_FMT" total max: %d mbm\n", FUNC_ADPT_ARG(adapter), mbm);
-+	} else
-+#endif
-+	{
-+		mbm = rtw_get_oper_txpwr_max_mbm(dvobj, 1);
-+		RTW_INFO(FUNC_WIPHY_FMT" total max: %d mbm\n", FUNC_WIPHY_ARG(wiphy), mbm);
-+	}
-+
-+	*dbm = mbm / MBM_PDBM;
-+
-+	return 0;
-+}
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)) */
-+
-+inline bool rtw_cfg80211_pwr_mgmt(_adapter *adapter)
-+{
-+	struct rtw_wdev_priv *rtw_wdev_priv = adapter_wdev_data(adapter);
-+	struct wireless_dev *wdev = rtw_wdev_priv->rtw_wdev;
-+
-+	return wdev->ps;
-+}
-+
-+static int cfg80211_rtw_set_power_mgmt(struct wiphy *wiphy,
-+				       struct net_device *ndev,
-+				       bool enabled, int timeout)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+
-+	RTW_INFO(FUNC_NDEV_FMT" enabled:%u, timeout:%d\n", FUNC_NDEV_ARG(ndev),
-+		enabled, timeout);
-+
-+#ifdef CONFIG_LPS
-+	if (!enabled)
-+		rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE_CFG80211_PWRMGMT, 0);
-+#endif
-+
-+	return 0;
-+}
-+
-+static void _rtw_set_pmksa(struct net_device *ndev,
-+	u8 *bssid, u8 *pmkid)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	u8 index, blInserted = _FALSE;
-+
-+	/* overwrite PMKID */
-+	for (index = 0 ; index < NUM_PMKID_CACHE; index++) {
-+		if (_rtw_memcmp(psecuritypriv->PMKIDList[index].Bssid, bssid, ETH_ALEN) == _TRUE) {
-+			/* BSSID is matched, the same AP => rewrite with new PMKID. */
-+			RTW_INFO("BSSID("MAC_FMT") exists in the PMKList.\n", MAC_ARG(bssid));
-+
-+			_rtw_memcpy(psecuritypriv->PMKIDList[index].PMKID, pmkid, WLAN_PMKID_LEN);
-+			psecuritypriv->PMKIDList[index].bUsed = _TRUE;
-+			psecuritypriv->PMKIDIndex = index + 1;
-+			blInserted = _TRUE;
-+			break;
-+		}
-+	}
-+
-+	if (!blInserted) {
-+		/* Find a new entry */
-+		RTW_INFO("Use the new entry index = %d for this PMKID.\n",
-+			psecuritypriv->PMKIDIndex);
-+
-+		_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, bssid, ETH_ALEN);
-+		_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pmkid, WLAN_PMKID_LEN);
-+
-+		psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].bUsed = _TRUE;
-+		psecuritypriv->PMKIDIndex++ ;
-+		if (psecuritypriv->PMKIDIndex == 16)
-+			psecuritypriv->PMKIDIndex = 0;
-+	}
-+}
-+
-+static int cfg80211_rtw_set_pmksa(struct wiphy *wiphy,
-+				  struct net_device *ndev,
-+				  struct cfg80211_pmksa *pmksa)
-+{
-+	u8	index, blInserted = _FALSE;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct mlme_priv *mlme = &padapter->mlmepriv;
-+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
-+	u8	strZeroMacAddress[ETH_ALEN] = { 0x00 };
-+	bool sae_auth = rtw_sec_chk_auth_type(padapter, MLME_AUTHTYPE_SAE);
-+
-+	RTW_INFO(FUNC_NDEV_FMT" "MAC_FMT" "KEY_FMT"\n", FUNC_NDEV_ARG(ndev)
-+		, MAC_ARG(pmksa->bssid), KEY_ARG(pmksa->pmkid));
-+
-+	if (_rtw_memcmp((u8 *)pmksa->bssid, strZeroMacAddress, ETH_ALEN) == _TRUE)
-+		return -EINVAL;
-+
-+	_rtw_set_pmksa(ndev, (u8 *)pmksa->bssid, (u8 *)pmksa->pmkid);
-+
-+	if (sae_auth &&
-+		(psecuritypriv->extauth_status == WLAN_STATUS_SUCCESS)) {
-+		RTW_PRINT("SAE: auth success, start assoc\n");
-+		start_clnt_assoc(padapter);
-+	}
-+
-+	return 0;
-+}
-+
-+static int cfg80211_rtw_del_pmksa(struct wiphy *wiphy,
-+				  struct net_device *ndev,
-+				  struct cfg80211_pmksa *pmksa)
-+{
-+	u8	index, bMatched = _FALSE;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
-+
-+	RTW_INFO(FUNC_NDEV_FMT" "MAC_FMT" "KEY_FMT"\n", FUNC_NDEV_ARG(ndev)
-+		, MAC_ARG(pmksa->bssid), KEY_ARG(pmksa->pmkid));
-+
-+	for (index = 0 ; index < NUM_PMKID_CACHE; index++) {
-+		if (_rtw_memcmp(psecuritypriv->PMKIDList[index].Bssid, (u8 *)pmksa->bssid, ETH_ALEN) == _TRUE) {
-+			/* BSSID is matched, the same AP => Remove this PMKID information and reset it. */
-+			_rtw_memset(psecuritypriv->PMKIDList[index].Bssid, 0x00, ETH_ALEN);
-+			_rtw_memset(psecuritypriv->PMKIDList[index].PMKID, 0x00, WLAN_PMKID_LEN);
-+			psecuritypriv->PMKIDList[index].bUsed = _FALSE;
-+			bMatched = _TRUE;
-+			RTW_INFO(FUNC_NDEV_FMT" clear id:%hhu\n", FUNC_NDEV_ARG(ndev), index);
-+			break;
-+		}
-+	}
-+
-+	if (_FALSE == bMatched) {
-+		RTW_INFO(FUNC_NDEV_FMT" do not have matched BSSID\n"
-+			, FUNC_NDEV_ARG(ndev));
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int cfg80211_rtw_flush_pmksa(struct wiphy *wiphy,
-+				    struct net_device *ndev)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
-+
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
-+
-+	_rtw_memset(&psecuritypriv->PMKIDList[0], 0x00, sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
-+	psecuritypriv->PMKIDIndex = 0;
-+
-+	return 0;
-+}
-+
-+static int rtw_cfg80211_monitor_if_open(struct net_device *ndev)
-+{
-+	int ret = 0;
-+
-+	RTW_INFO("%s\n", __func__);
-+
-+	return ret;
-+}
-+
-+static int rtw_cfg80211_monitor_if_close(struct net_device *ndev)
-+{
-+	int ret = 0;
-+
-+	RTW_INFO("%s\n", __func__);
-+
-+	return ret;
-+}
-+
-+static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_device *ndev)
-+{
-+	int ret = 0;
-+	int rtap_len;
-+	int qos_len = 0;
-+	int dot11_hdr_len = 24;
-+	int snap_len = 6;
-+	unsigned char *pdata;
-+	u16 frame_ctl;
-+	unsigned char src_mac_addr[ETH_ALEN];
-+	unsigned char dst_mac_addr[ETH_ALEN];
-+	struct rtw_ieee80211_hdr *dot11_hdr;
-+	struct ieee80211_radiotap_header *rtap_hdr;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+#ifdef CONFIG_DFS_MASTER
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+#endif
-+
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
-+
-+	rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize);
-+
-+	if (IS_CH_WAITING(rfctl)) {
-+		#ifdef CONFIG_DFS_MASTER
-+		if (rtw_rfctl_overlap_radar_detect_ch(rfctl))
-+			goto fail;
-+		#endif
-+	}
-+
-+	if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header)))
-+		goto fail;
-+
-+	rtap_hdr = (struct ieee80211_radiotap_header *)skb->data;
-+	if (unlikely(rtap_hdr->it_version))
-+		goto fail;
-+
-+	rtap_len = ieee80211_get_radiotap_len(skb->data);
-+	if (unlikely(skb->len < rtap_len))
-+		goto fail;
-+
-+	if (rtap_len != 14) {
-+		RTW_INFO("radiotap len (should be 14): %d\n", rtap_len);
-+		goto fail;
-+	}
-+
-+	/* Skip the ratio tap header */
-+	skb_pull(skb, rtap_len);
-+
-+	dot11_hdr = (struct rtw_ieee80211_hdr *)skb->data;
-+	frame_ctl = le16_to_cpu(dot11_hdr->frame_ctl);
-+	/* Check if the QoS bit is set */
-+	if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) {
-+		/* Check if this ia a Wireless Distribution System (WDS) frame
-+		 * which has 4 MAC addresses
-+		 */
-+		if (dot11_hdr->frame_ctl & 0x0080)
-+			qos_len = 2;
-+		if ((dot11_hdr->frame_ctl & 0x0300) == 0x0300)
-+			dot11_hdr_len += 6;
-+
-+		memcpy(dst_mac_addr, dot11_hdr->addr1, sizeof(dst_mac_addr));
-+		memcpy(src_mac_addr, dot11_hdr->addr2, sizeof(src_mac_addr));
-+
-+		/* Skip the 802.11 header, QoS (if any) and SNAP, but leave spaces for
-+		 * for two MAC addresses
-+		 */
-+		skb_pull(skb, dot11_hdr_len + qos_len + snap_len - sizeof(src_mac_addr) * 2);
-+		pdata = (unsigned char *)skb->data;
-+		memcpy(pdata, dst_mac_addr, sizeof(dst_mac_addr));
-+		memcpy(pdata + sizeof(dst_mac_addr), src_mac_addr, sizeof(src_mac_addr));
-+
-+		RTW_INFO("should be eapol packet\n");
-+
-+		/* Use the real net device to transmit the packet */
-+		ret = _rtw_xmit_entry(skb, padapter->pnetdev);
-+
-+		return ret;
-+
-+	} else if ((frame_ctl & (RTW_IEEE80211_FCTL_FTYPE | RTW_IEEE80211_FCTL_STYPE))
-+		== (RTW_IEEE80211_FTYPE_MGMT | RTW_IEEE80211_STYPE_ACTION)
-+	) {
-+		/* only for action frames */
-+		struct xmit_frame		*pmgntframe;
-+		struct pkt_attrib	*pattrib;
-+		unsigned char	*pframe;
-+		/* u8 category, action, OUI_Subtype, dialogToken=0; */
-+		/* unsigned char	*frame_body; */
-+		struct rtw_ieee80211_hdr *pwlanhdr;
-+		struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
-+		struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+		u8 *buf = skb->data;
-+		u32 len = skb->len;
-+		u8 category, action;
-+		int type = -1;
-+
-+		if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) {
-+			RTW_INFO(FUNC_NDEV_FMT" frame_control:0x%x\n", FUNC_NDEV_ARG(ndev),
-+				le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl));
-+			goto fail;
-+		}
-+
-+		RTW_INFO("RTW_Tx:da="MAC_FMT" via "FUNC_NDEV_FMT"\n",
-+			MAC_ARG(GetAddr1Ptr(buf)), FUNC_NDEV_ARG(ndev));
-+		#ifdef CONFIG_P2P
-+		type = rtw_p2p_check_frames(padapter, buf, len, _TRUE);
-+		if (type >= 0)
-+			goto dump;
-+		#endif
-+		if (category == RTW_WLAN_CATEGORY_PUBLIC)
-+			RTW_INFO("RTW_Tx:%s\n", action_public_str(action));
-+		else
-+			RTW_INFO("RTW_Tx:category(%u), action(%u)\n", category, action);
-+#ifdef CONFIG_P2P
-+dump:
-+#endif
-+		/* starting alloc mgmt frame to dump it */
-+		pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+		if (pmgntframe == NULL)
-+			goto fail;
-+
-+		/* update attribute */
-+		pattrib = &pmgntframe->attrib;
-+		update_mgntframe_attrib(padapter, pattrib);
-+		pattrib->retry_ctrl = _FALSE;
-+
-+		_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+		pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+
-+		_rtw_memcpy(pframe, (void *)buf, len);
-+		pattrib->pktlen = len;
-+
-+#ifdef CONFIG_P2P
-+		if (type >= 0)
-+			rtw_xframe_chk_wfd_ie(pmgntframe);
-+#endif /* CONFIG_P2P */
-+
-+		pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+		/* update seq number */
-+		pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
-+		pattrib->seqnum = pmlmeext->mgnt_seq;
-+		pmlmeext->mgnt_seq++;
-+
-+		pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+		dump_mgntframe(padapter, pmgntframe);
-+
-+	} else
-+		RTW_INFO("frame_ctl=0x%x\n", frame_ctl & (RTW_IEEE80211_FCTL_FTYPE | RTW_IEEE80211_FCTL_STYPE));
-+
-+
-+fail:
-+
-+	rtw_skb_free(skb);
-+
-+	return 0;
-+
-+}
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))
-+static void rtw_cfg80211_monitor_if_set_multicast_list(struct net_device *ndev)
-+{
-+	RTW_INFO("%s\n", __func__);
-+}
-+#endif
-+static int rtw_cfg80211_monitor_if_set_mac_address(struct net_device *ndev, void *addr)
-+{
-+	int ret = 0;
-+
-+	RTW_INFO("%s\n", __func__);
-+
-+	return ret;
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+static const struct net_device_ops rtw_cfg80211_monitor_if_ops = {
-+	.ndo_open = rtw_cfg80211_monitor_if_open,
-+	.ndo_stop = rtw_cfg80211_monitor_if_close,
-+	.ndo_start_xmit = rtw_cfg80211_monitor_if_xmit_entry,
-+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))
-+	.ndo_set_multicast_list = rtw_cfg80211_monitor_if_set_multicast_list,
-+	#endif
-+	.ndo_set_mac_address = rtw_cfg80211_monitor_if_set_mac_address,
-+};
-+#endif
-+
-+static int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct net_device **ndev)
-+{
-+	int ret = 0;
-+	struct net_device *mon_ndev = NULL;
-+	struct wireless_dev *mon_wdev = NULL;
-+	struct rtw_netdev_priv_indicator *pnpi;
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+
-+	if (!name) {
-+		RTW_INFO(FUNC_ADPT_FMT" without specific name\n", FUNC_ADPT_ARG(padapter));
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
-+	if (pwdev_priv->pmon_ndev) {
-+		RTW_INFO(FUNC_ADPT_FMT" monitor interface exist: "NDEV_FMT"\n",
-+			FUNC_ADPT_ARG(padapter), NDEV_ARG(pwdev_priv->pmon_ndev));
-+		ret = -EBUSY;
-+		goto out;
-+	}
-+
-+	mon_ndev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));
-+	if (!mon_ndev) {
-+		RTW_INFO(FUNC_ADPT_FMT" allocate ndev fail\n", FUNC_ADPT_ARG(padapter));
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	mon_ndev->type = ARPHRD_IEEE80211_RADIOTAP;
-+	strncpy(mon_ndev->name, name, IFNAMSIZ);
-+	mon_ndev->name[IFNAMSIZ - 1] = 0;
-+#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 11, 8))
-+	mon_ndev->priv_destructor = rtw_ndev_destructor;
-+#else
-+	mon_ndev->destructor = rtw_ndev_destructor;
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+	mon_ndev->netdev_ops = &rtw_cfg80211_monitor_if_ops;
-+#else
-+	mon_ndev->open = rtw_cfg80211_monitor_if_open;
-+	mon_ndev->stop = rtw_cfg80211_monitor_if_close;
-+	mon_ndev->hard_start_xmit = rtw_cfg80211_monitor_if_xmit_entry;
-+	mon_ndev->set_mac_address = rtw_cfg80211_monitor_if_set_mac_address;
-+#endif
-+
-+	pnpi = netdev_priv(mon_ndev);
-+	pnpi->priv = padapter;
-+	pnpi->sizeof_priv = sizeof(_adapter);
-+
-+	/*  wdev */
-+	mon_wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev));
-+	if (!mon_wdev) {
-+		RTW_INFO(FUNC_ADPT_FMT" allocate mon_wdev fail\n", FUNC_ADPT_ARG(padapter));
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	mon_wdev->wiphy = padapter->rtw_wdev->wiphy;
-+	mon_wdev->netdev = mon_ndev;
-+	mon_wdev->iftype = NL80211_IFTYPE_MONITOR;
-+	mon_ndev->ieee80211_ptr = mon_wdev;
-+
-+	ret = register_netdevice(mon_ndev);
-+	if (ret)
-+		goto out;
-+
-+	*ndev = pwdev_priv->pmon_ndev = mon_ndev;
-+	_rtw_memcpy(pwdev_priv->ifname_mon, name, IFNAMSIZ + 1);
-+
-+out:
-+	if (ret && mon_wdev) {
-+		rtw_mfree((u8 *)mon_wdev, sizeof(struct wireless_dev));
-+		mon_wdev = NULL;
-+	}
-+
-+	if (ret && mon_ndev) {
-+		free_netdev(mon_ndev);
-+		*ndev = mon_ndev = NULL;
-+	}
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len)
-+{
-+#if !defined(RTW_USE_CFG80211_STA_EVENT) && !defined(COMPAT_KERNEL_RELEASE)
-+	s32 freq;
-+	int channel;
-+	struct wireless_dev *pwdev = padapter->rtw_wdev;
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+#endif
-+	struct net_device *ndev = padapter->pnetdev;
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+
-+#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE)
-+	{
-+		struct station_info sinfo;
-+		u8 ie_offset;
-+		if (get_frame_sub_type(pmgmt_frame) == WIFI_ASSOCREQ)
-+			ie_offset = _ASOCREQ_IE_OFFSET_;
-+		else /* WIFI_REASSOCREQ */
-+			ie_offset = _REASOCREQ_IE_OFFSET_;
-+
-+		memset(&sinfo, 0, sizeof(sinfo));
-+		sinfo.filled = STATION_INFO_ASSOC_REQ_IES;
-+		sinfo.assoc_req_ies = pmgmt_frame + WLAN_HDR_A3_LEN + ie_offset;
-+		sinfo.assoc_req_ies_len = frame_len - WLAN_HDR_A3_LEN - ie_offset;
-+		cfg80211_new_sta(ndev, get_addr2_ptr(pmgmt_frame), &sinfo, GFP_ATOMIC);
-+	}
-+#else /* defined(RTW_USE_CFG80211_STA_EVENT) */
-+	channel = pmlmeext->cur_channel;
-+	freq = rtw_ch2freq(channel);
-+
-+	#ifdef COMPAT_KERNEL_RELEASE
-+	rtw_cfg80211_rx_mgmt(pwdev, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC);
-+	#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
-+	rtw_cfg80211_rx_mgmt(pwdev, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC);
-+	#else /* COMPAT_KERNEL_RELEASE */
-+	{
-+		/* to avoid WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION)  when calling cfg80211_send_rx_assoc() */
-+		#ifndef CONFIG_PLATFORM_MSTAR
-+		pwdev->iftype = NL80211_IFTYPE_STATION;
-+		#endif /* CONFIG_PLATFORM_MSTAR */
-+		RTW_INFO("iftype=%d before call cfg80211_send_rx_assoc()\n", pwdev->iftype);
-+		rtw_cfg80211_send_rx_assoc(padapter, NULL, pmgmt_frame, frame_len);
-+		RTW_INFO("iftype=%d after call cfg80211_send_rx_assoc()\n", pwdev->iftype);
-+		pwdev->iftype = NL80211_IFTYPE_AP;
-+		/* cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); */
-+	}
-+	#endif /* COMPAT_KERNEL_RELEASE */
-+#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */
-+
-+}
-+
-+void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason)
-+{
-+#if !defined(RTW_USE_CFG80211_STA_EVENT) && !defined(COMPAT_KERNEL_RELEASE)
-+	s32 freq;
-+	int channel;
-+	u8 *pmgmt_frame;
-+	uint frame_len;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	unsigned short *fctrl;
-+	u8 mgmt_buf[128] = {0};
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct wireless_dev *wdev = padapter->rtw_wdev;
-+#endif
-+	struct net_device *ndev = padapter->pnetdev;
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+
-+#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE)
-+	cfg80211_del_sta(ndev, da, GFP_ATOMIC);
-+#else /* defined(RTW_USE_CFG80211_STA_EVENT) */
-+	channel = pmlmeext->cur_channel;
-+	freq = rtw_ch2freq(channel);
-+
-+	pmgmt_frame = mgmt_buf;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pmgmt_frame;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, da, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pmgmt_frame, WIFI_DEAUTH);
-+
-+	pmgmt_frame += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	frame_len = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	reason = cpu_to_le16(reason);
-+	pmgmt_frame = rtw_set_fixed_ie(pmgmt_frame, _RSON_CODE_ , (unsigned char *)&reason, &frame_len);
-+
-+	#ifdef COMPAT_KERNEL_RELEASE
-+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC);
-+	#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
-+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC);
-+	#else /* COMPAT_KERNEL_RELEASE */
-+	cfg80211_send_disassoc(padapter->pnetdev, mgmt_buf, frame_len);
-+	/* cfg80211_rx_action(padapter->pnetdev, freq, mgmt_buf, frame_len, GFP_ATOMIC); */
-+	#endif /* COMPAT_KERNEL_RELEASE */
-+#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */
-+}
-+
-+static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, const u8 *tail, size_t tail_len)
-+{
-+	int ret = 0;
-+	u8 *pbuf = NULL;
-+	uint len, wps_ielen = 0;
-+	uint p2p_ielen = 0;
-+	u8 got_p2p_ie = _FALSE;
-+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
-+	/* struct sta_priv *pstapriv = &padapter->stapriv; */
-+
-+
-+	RTW_INFO("%s beacon_head_len=%zu, beacon_tail_len=%zu\n", __FUNCTION__, head_len, tail_len);
-+
-+
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
-+		return -EINVAL;
-+
-+	if (head_len < 24)
-+		return -EINVAL;
-+
-+	#ifdef CONFIG_FW_HANDLE_TXBCN
-+	if (!rtw_ap_nums_check(adapter)) {
-+		RTW_ERR(FUNC_ADPT_FMT"failed, con't support over %d BCN\n", FUNC_ADPT_ARG(adapter), CONFIG_LIMITED_AP_NUM);
-+		return -EINVAL;
-+	}
-+	#endif /*CONFIG_FW_HANDLE_TXBCN*/
-+
-+	pbuf = rtw_zmalloc(head_len + tail_len);
-+	if (!pbuf) {
-+		ret = -ENOMEM;
-+		goto exit;
-+	}
-+
-+
-+	/* _rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2); */
-+
-+	/* if((pstapriv->max_num_sta>NUM_STA) || (pstapriv->max_num_sta<=0)) */
-+	/*	pstapriv->max_num_sta = NUM_STA; */
-+
-+
-+	_rtw_memcpy(pbuf, (void *)head + 24, head_len - 24); /* 24=beacon header len. */
-+	_rtw_memcpy(pbuf + head_len - 24, (void *)tail, tail_len);
-+
-+	len = head_len + tail_len - 24;
-+
-+	/* check wps ie if inclued */
-+	if (rtw_get_wps_ie(pbuf + _FIXED_IE_LENGTH_, len - _FIXED_IE_LENGTH_, NULL, &wps_ielen))
-+		RTW_INFO("add bcn, wps_ielen=%d\n", wps_ielen);
-+
-+#ifdef CONFIG_P2P
-+	if (adapter->wdinfo.driver_interface == DRIVER_CFG80211) {
-+		/* check p2p if enable */
-+		if (rtw_get_p2p_ie(pbuf + _FIXED_IE_LENGTH_, len - _FIXED_IE_LENGTH_, NULL, &p2p_ielen)) {
-+			struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
-+
-+			RTW_INFO("got p2p_ie, len=%d\n", p2p_ielen);
-+
-+			got_p2p_ie = _TRUE;
-+
-+			if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
-+
-+				if (rtw_p2p_enable(adapter, P2P_ROLE_GO)) {
-+					RTW_INFO("Enable P2P function for the first time\n");
-+					adapter->stapriv.expire_to = 3; /* 3x2 = 6 sec in p2p mode */
-+				} else {
-+					ret = -EOPNOTSUPP;
-+					goto exit;
-+				}
-+			} else {
-+				RTW_INFO("enter GO Mode, p2p_ielen=%d\n", p2p_ielen);
-+
-+				rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO);
-+				rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK);
-+				pwdinfo->intent = 15;
-+			}
-+		}
-+	}
-+#endif /* CONFIG_P2P */
-+
-+	/* pbss_network->IEs will not include p2p_ie, wfd ie */
-+	rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, P2P_OUI, 4);
-+	rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, WFD_OUI, 4);
-+
-+	if (rtw_check_beacon_data(adapter, pbuf,  len) == _SUCCESS) {
-+#ifdef CONFIG_P2P
-+		/* check p2p if enable */
-+		if (got_p2p_ie == _TRUE) {
-+			struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
-+			struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
-+			pwdinfo->operating_channel = pmlmeext->cur_channel;
-+		}
-+#endif /* CONFIG_P2P */
-+		ret = 0;
-+	} else
-+		ret = -EINVAL;
-+
-+exit:
-+	if (pbuf)
-+		rtw_mfree(pbuf, head_len + tail_len);
-+
-+	return ret;
-+}
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE)
-+static int cfg80211_rtw_add_beacon(struct wiphy *wiphy, struct net_device *ndev,
-+		struct beacon_parameters *info)
-+{
-+	int ret = 0;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
-+
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
-+
-+	if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) {
-+		ret = -ENOTSUPP;
-+		goto exit;
-+	}
-+	rtw_mi_scan_abort(adapter, _TRUE);
-+	rtw_mi_buddy_set_scan_deny(adapter, 300);
-+	ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len);
-+
-+exit:
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_set_beacon(struct wiphy *wiphy, struct net_device *ndev,
-+		struct beacon_parameters *info)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
-+
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
-+
-+	pmlmeext->bstart_bss = _TRUE;
-+
-+	cfg80211_rtw_add_beacon(wiphy, ndev, info);
-+
-+	return 0;
-+}
-+
-+static int	cfg80211_rtw_del_beacon(struct wiphy *wiphy, struct net_device *ndev)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
-+
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
-+
-+	rtw_stop_ap_cmd(adapter, RTW_CMDF_WAIT_ACK);
-+	return 0;
-+}
-+#else
-+static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev,
-+		struct cfg80211_ap_settings *settings)
-+{
-+	int ret = 0;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
-+
-+	RTW_INFO(FUNC_NDEV_FMT" hidden_ssid:%d, auth_type:%d\n", FUNC_NDEV_ARG(ndev),
-+		settings->hidden_ssid, settings->auth_type);
-+
-+	if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) {
-+		ret = -ENOTSUPP;
-+		goto exit;
-+	}
-+
-+	/* Kernel < v5.x, the auth_type set as NL80211_AUTHTYPE_AUTOMATIC. if
-+	 * the AKM SAE in the RSN IE, we have to update the auth_type for SAE in
-+	 * rtw_check_beacon_data().
-+	 *
-+	 * we only update auth_type when rtw_check_beacon_data()
-+	 */
-+	/* rtw_cfg80211_set_auth_type(&adapter->securitypriv, settings->auth_type); */
-+
-+	rtw_mi_scan_abort(adapter, _TRUE);
-+	rtw_mi_buddy_set_scan_deny(adapter, 300);
-+
-+	adapter->mlmeextpriv.mlmext_info.hidden_ssid_mode = settings->hidden_ssid;
-+	ret = rtw_add_beacon(adapter, settings->beacon.head, settings->beacon.head_len,
-+		settings->beacon.tail, settings->beacon.tail_len);
-+
-+	if (settings->ssid && settings->ssid_len) {
-+		WLAN_BSSID_EX *pbss_network = &adapter->mlmepriv.cur_network.network;
-+		WLAN_BSSID_EX *pbss_network_ext = &adapter->mlmeextpriv.mlmext_info.network;
-+
-+		if (0)
-+			RTW_INFO(FUNC_ADPT_FMT" ssid:(%s,%zu), from ie:(%s,%d)\n", FUNC_ADPT_ARG(adapter),
-+				settings->ssid, settings->ssid_len,
-+				pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength);
-+
-+		_rtw_memcpy(pbss_network->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len);
-+		pbss_network->Ssid.SsidLength = settings->ssid_len;
-+		_rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len);
-+		pbss_network_ext->Ssid.SsidLength = settings->ssid_len;
-+
-+		if (0)
-+			RTW_INFO(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter),
-+				pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,
-+				pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_change_beacon(struct wiphy *wiphy, struct net_device *ndev,
-+		struct cfg80211_beacon_data *info)
-+{
-+	int ret = 0;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
-+
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
-+
-+	ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len);
-+
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
-+
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
-+
-+	rtw_stop_ap_cmd(adapter, RTW_CMDF_WAIT_ACK);
-+	return 0;
-+}
-+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) */
-+
-+#if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
-+static int cfg80211_rtw_set_mac_acl(struct wiphy *wiphy, struct net_device *ndev,
-+		const struct cfg80211_acl_data *params)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
-+	u8 acl_mode = RTW_ACL_MODE_DISABLED;
-+	int ret = -1;
-+	int i;
-+
-+	if (!params) {
-+		RTW_WARN(FUNC_ADPT_FMT" params NULL\n", FUNC_ADPT_ARG(adapter));
-+		rtw_macaddr_acl_clear(adapter, RTW_ACL_PERIOD_BSS);
-+		goto exit;
-+	}
-+
-+	RTW_INFO(FUNC_ADPT_FMT" acl_policy:%d, entry_num:%d\n"
-+		, FUNC_ADPT_ARG(adapter), params->acl_policy, params->n_acl_entries);
-+
-+	if (params->acl_policy == NL80211_ACL_POLICY_ACCEPT_UNLESS_LISTED)
-+		acl_mode = RTW_ACL_MODE_ACCEPT_UNLESS_LISTED;
-+	else if (params->acl_policy == NL80211_ACL_POLICY_DENY_UNLESS_LISTED)
-+		acl_mode = RTW_ACL_MODE_DENY_UNLESS_LISTED;
-+
-+	rtw_macaddr_acl_clear(adapter, RTW_ACL_PERIOD_BSS);
-+
-+	rtw_set_macaddr_acl(adapter, RTW_ACL_PERIOD_BSS, acl_mode);
-+
-+	for (i = 0; i < params->n_acl_entries; i++)
-+		rtw_acl_add_sta(adapter, RTW_ACL_PERIOD_BSS, params->mac_addrs[i].addr);
-+
-+	ret = 0;
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) */
-+
-+const char *_nl80211_sta_flags_str[] = {
-+	"INVALID",
-+	"AUTHORIZED",
-+	"SHORT_PREAMBLE",
-+	"WME",
-+	"MFP",
-+	"AUTHENTICATED",
-+	"TDLS_PEER",
-+	"ASSOCIATED",
-+};
-+
-+#define nl80211_sta_flags_str(_f) ((_f <= NL80211_STA_FLAG_MAX) ? _nl80211_sta_flags_str[_f] : _nl80211_sta_flags_str[0])
-+
-+const char *_nl80211_plink_state_str[] = {
-+	"LISTEN",
-+	"OPN_SNT",
-+	"OPN_RCVD",
-+	"CNF_RCVD",
-+	"ESTAB",
-+	"HOLDING",
-+	"BLOCKED",
-+	"UNKNOWN",
-+};
-+
-+#define nl80211_plink_state_str(_s) ((_s < NUM_NL80211_PLINK_STATES) ? _nl80211_plink_state_str[_s] : _nl80211_plink_state_str[NUM_NL80211_PLINK_STATES])
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
-+#define NL80211_PLINK_ACTION_NO_ACTION PLINK_ACTION_INVALID
-+#define NL80211_PLINK_ACTION_OPEN PLINK_ACTION_OPEN
-+#define NL80211_PLINK_ACTION_BLOCK PLINK_ACTION_BLOCK
-+#define NUM_NL80211_PLINK_ACTIONS 3
-+#endif
-+
-+const char *_nl80211_plink_actions_str[] = {
-+	"NO_ACTION",
-+	"OPEN",
-+	"BLOCK",
-+	"UNKNOWN",
-+};
-+
-+#define nl80211_plink_actions_str(_a) ((_a < NUM_NL80211_PLINK_ACTIONS) ? _nl80211_plink_actions_str[_a] : _nl80211_plink_actions_str[NUM_NL80211_PLINK_ACTIONS])
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
-+const char *_nl80211_mesh_power_mode_str[] = {
-+	"UNKNOWN",
-+	"ACTIVE",
-+	"LIGHT_SLEEP",
-+	"DEEP_SLEEP",
-+};
-+
-+#define nl80211_mesh_power_mode_str(_p) ((_p <= NL80211_MESH_POWER_MAX) ? _nl80211_mesh_power_mode_str[_p] : _nl80211_mesh_power_mode_str[0])
-+#endif
-+
-+void dump_station_parameters(void *sel, struct wiphy *wiphy, const struct station_parameters *params)
-+{
-+#if DBG_RTW_CFG80211_STA_PARAM
-+	if (params->supported_rates_len) {
-+		#define SUPP_RATES_BUF_LEN (3 * RTW_G_RATES_NUM + 1)
-+		int i;
-+		char supp_rates_buf[SUPP_RATES_BUF_LEN] = {0};
-+		u8 cnt = 0;
-+
-+		rtw_warn_on(params->supported_rates_len > RTW_G_RATES_NUM);
-+
-+		for (i = 0; i < params->supported_rates_len; i++) {
-+			if (i >= RTW_G_RATES_NUM)
-+				break;
-+			cnt += snprintf(supp_rates_buf + cnt, SUPP_RATES_BUF_LEN - cnt -1
-+				, "%02X ", params->supported_rates[i]);
-+			if (cnt >= SUPP_RATES_BUF_LEN - 1)
-+				break;
-+		}
-+
-+		RTW_PRINT_SEL(sel, "supported_rates:%s\n", supp_rates_buf);
-+	}
-+
-+	if (params->vlan)
-+		RTW_PRINT_SEL(sel, "vlan:"NDEV_FMT"\n", NDEV_ARG(params->vlan));
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
-+	if (params->sta_flags_mask) {
-+		#define STA_FLAGS_BUF_LEN 128
-+		int i = 0;
-+		char sta_flags_buf[STA_FLAGS_BUF_LEN] = {0};
-+		u8 cnt = 0;
-+
-+		for (i = 1; i <= NL80211_STA_FLAG_MAX; i++) {
-+			if (params->sta_flags_mask & BIT(i)) {
-+				cnt += snprintf(sta_flags_buf + cnt, STA_FLAGS_BUF_LEN - cnt -1, "%s=%u "
-+					, nl80211_sta_flags_str(i), (params->sta_flags_set & BIT(i)) ? 1 : 0);
-+				if (cnt >= STA_FLAGS_BUF_LEN - 1)
-+					break;
-+			}
-+		}
-+
-+		RTW_PRINT_SEL(sel, "sta_flags:%s\n", sta_flags_buf);
-+	}
-+#else
-+	u32 station_flags;
-+	#error "TBD\n"
-+#endif
-+
-+	if (params->listen_interval != -1)
-+		RTW_PRINT_SEL(sel, "listen_interval:%d\n", params->listen_interval);
-+
-+	if (params->aid)
-+		RTW_PRINT_SEL(sel, "aid:%u\n", params->aid);
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
-+	if (params->peer_aid)
-+		RTW_PRINT_SEL(sel, "peer_aid:%u\n", params->peer_aid);
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26))
-+	if (params->plink_action != NL80211_PLINK_ACTION_NO_ACTION)
-+		RTW_PRINT_SEL(sel, "plink_action:%s\n", nl80211_plink_actions_str(params->plink_action));
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
-+	if (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE)
-+	#endif
-+		RTW_PRINT_SEL(sel, "plink_state:%s\n"
-+			, nl80211_plink_state_str(params->plink_state));
-+#endif
-+
-+#if 0 /* TODO */
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28))
-+	const struct ieee80211_ht_cap *ht_capa;
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	const struct ieee80211_vht_cap *vht_capa;
-+#endif
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
-+	if (params->sta_modify_mask & STATION_PARAM_APPLY_UAPSD)
-+		RTW_PRINT_SEL(sel, "uapsd_queues:0x%02x\n", params->uapsd_queues);
-+	if (params->max_sp)
-+		RTW_PRINT_SEL(sel, "max_sp:%u\n", params->max_sp);
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
-+	if (params->local_pm != NL80211_MESH_POWER_UNKNOWN) {
-+		RTW_PRINT_SEL(sel, "local_pm:%s\n"
-+			, nl80211_mesh_power_mode_str(params->local_pm));
-+	}
-+
-+	if (params->sta_modify_mask & STATION_PARAM_APPLY_CAPABILITY)
-+		RTW_PRINT_SEL(sel, "capability:0x%04x\n", params->capability);
-+
-+#if 0 /* TODO */
-+	const u8 *ext_capab;
-+	u8 ext_capab_len;
-+#endif
-+#endif
-+
-+#if 0 /* TODO */
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0))
-+	const u8 *supported_channels;
-+	u8 supported_channels_len;
-+	const u8 *supported_oper_classes;
-+	u8 supported_oper_classes_len;
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
-+	u8 opmode_notif;
-+	bool opmode_notif_used;
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
-+	int support_p2p_ps;
-+#endif
-+#endif
-+#endif /* DBG_RTW_CFG80211_STA_PARAM */
-+}
-+
-+static int	cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev,
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
-+	u8 *mac,
-+#else
-+	const u8 *mac,
-+#endif
-+	struct station_parameters *params)
-+{
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+#if defined(CONFIG_TDLS) || defined(CONFIG_RTW_MESH)
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+#endif
-+#ifdef CONFIG_TDLS
-+	struct sta_info *psta;
-+#endif /* CONFIG_TDLS */
-+
-+	RTW_INFO(FUNC_NDEV_FMT" mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(mac));
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+	if (rtw_access_ctrl(padapter, mac) == _FALSE) {
-+		RTW_INFO(FUNC_NDEV_FMT" deny by macaddr ACL\n", FUNC_NDEV_ARG(ndev));
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+#endif
-+
-+	dump_station_parameters(RTW_DBGDUMP, wiphy, params);
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(padapter)) {
-+		struct rtw_mesh_cfg *mcfg = &padapter->mesh_cfg;
-+		struct rtw_mesh_info *minfo = &padapter->mesh_info;
-+		struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
-+		struct mesh_plink_ent *plink = NULL;
-+		struct wlan_network *scanned = NULL;
-+		bool acnode = 0;
-+		u8 add_new_sta = 0, probe_req = 0;
-+		_irqL irqL;
-+
-+		if (params->plink_state != NL80211_PLINK_LISTEN) {
-+			RTW_WARN(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(ndev), nl80211_plink_state_str(params->plink_state));
-+			rtw_warn_on(1);
-+		}
-+		if (!params->aid || params->aid > pstapriv->max_aid) {
-+			RTW_WARN(FUNC_NDEV_FMT" invalid aid:%u\n", FUNC_NDEV_ARG(ndev), params->aid);
-+			rtw_warn_on(1);
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+
-+		_enter_critical_bh(&(plink_ctl->lock), &irqL);
-+
-+		plink = _rtw_mesh_plink_get(padapter, mac);
-+		if (plink)
-+			goto release_plink_ctl;
-+
-+		#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+		if (rtw_mesh_peer_blacklist_search(padapter, mac)) {
-+			RTW_INFO(FUNC_NDEV_FMT" deny by peer blacklist\n"
-+				, FUNC_NDEV_ARG(ndev));
-+			ret = -EINVAL;
-+			goto release_plink_ctl;
-+		}
-+		#endif
-+
-+		scanned = rtw_find_network(&padapter->mlmepriv.scanned_queue, mac);
-+		if (!scanned
-+			|| rtw_get_passing_time_ms(scanned->last_scanned) >= mcfg->peer_sel_policy.scanr_exp_ms
-+		) {
-+			if (!scanned)
-+				RTW_INFO(FUNC_NDEV_FMT" corresponding network not found\n", FUNC_NDEV_ARG(ndev));
-+			else
-+				RTW_INFO(FUNC_NDEV_FMT" corresponding network too old\n", FUNC_NDEV_ARG(ndev));
-+
-+			if (adapter_to_rfctl(padapter)->offch_state == OFFCHS_NONE)
-+				probe_req = 1;
-+
-+			ret = -EINVAL;
-+			goto release_plink_ctl;
-+		}
-+
-+		#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+		if (plink_ctl->acnode_rsvd)
-+			acnode = rtw_mesh_scanned_is_acnode_confirmed(padapter, scanned);
-+		#endif
-+
-+		/* wpa_supplicant's auto peer will initiate peering when candidate peer is reported without max_peer_links consideration */
-+		if (plink_ctl->num >= mcfg->max_peer_links + acnode ? 1 : 0) {
-+			RTW_INFO(FUNC_NDEV_FMT" exceed max_peer_links:%u%s\n"
-+				, FUNC_NDEV_ARG(ndev), mcfg->max_peer_links, acnode ? " acn" : "");
-+			ret = -EINVAL;
-+			goto release_plink_ctl;
-+		}
-+
-+		if (!rtw_bss_is_candidate_mesh_peer(padapter, &scanned->network, 1, 1)) {
-+			RTW_WARN(FUNC_NDEV_FMT" corresponding network is not candidate with same ch\n"
-+				, FUNC_NDEV_ARG(ndev));
-+			ret = -EINVAL;
-+			goto release_plink_ctl;
-+		}
-+
-+		#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+		if (!rtw_mesh_cto_mgate_network_filter(padapter, scanned)) {
-+			RTW_INFO(FUNC_NDEV_FMT" peer filtered out by cto_mgate check\n"
-+				, FUNC_NDEV_ARG(ndev));
-+			ret = -EINVAL;
-+			goto release_plink_ctl;
-+		}
-+		#endif
-+
-+		if (_rtw_mesh_plink_add(padapter, mac) == _SUCCESS) {
-+			/* hook corresponding network in scan queue */
-+			plink = _rtw_mesh_plink_get(padapter, mac);
-+			plink->aid = params->aid;
-+			plink->scanned = scanned;
-+
-+			#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+			if (acnode) {
-+				RTW_INFO(FUNC_ADPT_FMT" acnode "MAC_FMT"\n"
-+				, FUNC_ADPT_ARG(padapter), MAC_ARG(scanned->network.MacAddress));
-+			}
-+			#endif
-+
-+			add_new_sta = 1;
-+		} else {
-+			RTW_WARN(FUNC_NDEV_FMT" rtw_mesh_plink_add not success\n"
-+				, FUNC_NDEV_ARG(ndev));
-+			ret = -EINVAL;
-+		}
-+release_plink_ctl:
-+		_exit_critical_bh(&(plink_ctl->lock), &irqL);
-+
-+		if (probe_req)
-+			issue_probereq(padapter, &padapter->mlmepriv.cur_network.network.mesh_id, mac);
-+
-+		if (add_new_sta) {
-+			struct station_info sinfo;
-+
-+			#ifdef CONFIG_DFS_MASTER
-+			if (IS_UNDER_CAC(adapter_to_rfctl(padapter)))
-+				rtw_force_stop_cac(adapter_to_rfctl(padapter), 300);
-+			#endif
-+
-+			/* indicate new sta */
-+			_rtw_memset(&sinfo, 0, sizeof(sinfo));
-+			cfg80211_new_sta(ndev, mac, &sinfo, GFP_ATOMIC);
-+		}
-+		goto exit;
-+	}
-+#endif /* CONFIG_RTW_MESH */
-+
-+#ifdef CONFIG_TDLS
-+	psta = rtw_get_stainfo(pstapriv, (u8 *)mac);
-+	if (psta == NULL) {
-+		psta = rtw_alloc_stainfo(pstapriv, (u8 *)mac);
-+		if (psta == NULL) {
-+			RTW_INFO("[%s] Alloc station for "MAC_FMT" fail\n", __FUNCTION__, MAC_ARG(mac));
-+			ret = -EOPNOTSUPP;
-+			goto exit;
-+		}
-+	}
-+#endif /* CONFIG_TDLS */
-+
-+exit:
-+	return ret;
-+}
-+
-+static int	cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev,
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
-+	u8 *mac
-+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0))
-+	const u8 *mac
-+#else
-+	struct station_del_parameters *params
-+#endif
-+)
-+{
-+	int ret = 0;
-+	_irqL irqL;
-+	_list	*phead, *plist;
-+	u8 updated = _FALSE;
-+	const u8 *target_mac;
-+	struct sta_info *psta = NULL;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0))
-+	target_mac = mac;
-+#else
-+	target_mac = params->mac;
-+#endif
-+
-+	RTW_INFO("+"FUNC_NDEV_FMT" mac=%pM\n", FUNC_NDEV_ARG(ndev), target_mac);
-+
-+	if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE | WIFI_MESH_STATE)) != _TRUE) {
-+		RTW_INFO("%s, fw_state != FW_LINKED|WIFI_AP_STATE|WIFI_MESH_STATE\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+
-+	if (!target_mac) {
-+		RTW_INFO("flush all sta, and cam_entry\n");
-+
-+		flush_all_cam_entry(padapter);	/* clear CAM */
-+
-+#ifdef CONFIG_AP_MODE
-+		ret = rtw_sta_flush(padapter, _TRUE);
-+#endif
-+		return ret;
-+	}
-+
-+
-+	RTW_INFO("free sta macaddr =" MAC_FMT "\n", MAC_ARG(target_mac));
-+
-+	if (target_mac[0] == 0xff && target_mac[1] == 0xff &&
-+	    target_mac[2] == 0xff && target_mac[3] == 0xff &&
-+	    target_mac[4] == 0xff && target_mac[5] == 0xff)
-+		return -EINVAL;
-+
-+
-+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+	phead = &pstapriv->asoc_list;
-+	plist = get_next(phead);
-+
-+	/* check asoc_queue */
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+		psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+
-+		plist = get_next(plist);
-+
-+		if (_rtw_memcmp((u8 *)target_mac, psta->cmn.mac_addr, ETH_ALEN)) {
-+			if (psta->dot8021xalg == 1 && psta->bpairwise_key_installed == _FALSE) {
-+				RTW_INFO("%s, sta's dot8021xalg = 1 and key_installed = _FALSE\n", __func__);
-+
-+				#ifdef CONFIG_AP_MODE
-+				if (MLME_IS_AP(padapter)) {
-+					rtw_list_delete(&psta->asoc_list);
-+					pstapriv->asoc_list_cnt--;
-+					#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+					if (psta->tbtx_enable)
-+						pstapriv->tbtx_asoc_list_cnt--;
-+					#endif
-+					STA_SET_MESH_PLINK(psta, NULL);
-+
-+					ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_IEEE_802_1X_AUTH_FAILED, _TRUE);
-+					psta = NULL;
-+					break;
-+				}
-+				#endif
-+			} else {
-+				RTW_INFO("free psta=%p, aid=%d\n", psta, psta->cmn.aid);
-+
-+				rtw_list_delete(&psta->asoc_list);
-+				pstapriv->asoc_list_cnt--;
-+				#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+				if (psta->tbtx_enable)
-+					pstapriv->tbtx_asoc_list_cnt--;
-+				#endif
-+				STA_SET_MESH_PLINK(psta, NULL);
-+
-+				/* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */
-+				if (MLME_IS_AP(padapter))
-+					updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE);
-+				else
-+					updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE);
-+				/* _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); */
-+
-+				psta = NULL;
-+
-+				break;
-+			}
-+
-+		}
-+
-+	}
-+
-+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+	associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(padapter))
-+		rtw_mesh_plink_del(padapter, target_mac);
-+#endif
-+
-+	RTW_INFO("-"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
-+
-+	return ret;
-+
-+}
-+
-+static int	cfg80211_rtw_change_station(struct wiphy *wiphy, struct net_device *ndev,
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
-+	u8 *mac,
-+#else
-+	const u8 *mac,
-+#endif
-+	struct station_parameters *params)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
-+	int ret = 0;
-+
-+	RTW_INFO(FUNC_ADPT_FMT" mac:"MAC_FMT"\n", FUNC_ADPT_ARG(adapter), MAC_ARG(mac));
-+
-+	dump_station_parameters(RTW_DBGDUMP, wiphy, params);
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(adapter)) {
-+		enum cfg80211_station_type sta_type = CFG80211_STA_MESH_PEER_USER;
-+		u8 plink_state = nl80211_plink_state_to_rtw_plink_state(params->plink_state);
-+
-+		ret = cfg80211_check_station_change(wiphy, params, sta_type);
-+		if (ret) {
-+			RTW_INFO("cfg80211_check_station_change return %d\n", ret);
-+			goto exit;
-+		}
-+
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
-+		if (!(params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE))
-+			goto exit;
-+		#endif
-+
-+		if (rtw_mesh_set_plink_state_cmd(adapter, mac, plink_state) != _SUCCESS)
-+			ret = -ENOENT;
-+	}
-+
-+exit:
-+#endif /* CONFIG_RTW_MESH */
-+
-+	if (ret)
-+		RTW_INFO(FUNC_ADPT_FMT" mac:"MAC_FMT" ret:%d\n", FUNC_ADPT_ARG(adapter), MAC_ARG(mac), ret);
-+	return ret;
-+}
-+
-+struct sta_info *rtw_sta_info_get_by_idx(struct sta_priv *pstapriv, const int idx, u8 *asoc_list_num)
-+{
-+	_list	*phead, *plist;
-+	struct sta_info *psta = NULL;
-+	int i = 0;
-+
-+	phead = &pstapriv->asoc_list;
-+	plist = get_next(phead);
-+
-+	/* check asoc_queue */
-+	while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+		if (idx == i)
-+			psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
-+		plist = get_next(plist);
-+		i++;
-+	}
-+
-+	if (asoc_list_num)
-+		*asoc_list_num = i;
-+
-+	return psta;
-+}
-+
-+static int	cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *ndev,
-+		int idx, u8 *mac, struct station_info *sinfo)
-+{
-+#define DBG_DUMP_STATION 0
-+
-+	int ret = 0;
-+	_irqL irqL;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info *psta = NULL;
-+#ifdef CONFIG_RTW_MESH
-+	struct mesh_plink_ent *plink = NULL;
-+#endif
-+	u8 asoc_list_num;
-+
-+	if (DBG_DUMP_STATION)
-+		RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
-+
-+	_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+	psta = rtw_sta_info_get_by_idx(pstapriv, idx, &asoc_list_num);
-+	_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(padapter)) {
-+		if (psta)
-+			plink = psta->plink;
-+		if (!plink)
-+			plink = rtw_mesh_plink_get_no_estab_by_idx(padapter, idx - asoc_list_num);
-+	}
-+#endif /* CONFIG_RTW_MESH */
-+
-+	if ((!MLME_IS_MESH(padapter) && !psta)
-+		#ifdef CONFIG_RTW_MESH
-+		|| (MLME_IS_MESH(padapter) && !plink)
-+		#endif
-+	) {
-+		if (DBG_DUMP_STATION)
-+			RTW_INFO(FUNC_NDEV_FMT" end with idx:%d\n", FUNC_NDEV_ARG(ndev), idx);
-+		ret = -ENOENT;
-+		goto exit;
-+	}
-+
-+	if (psta)
-+		_rtw_memcpy(mac, psta->cmn.mac_addr, ETH_ALEN);
-+	#ifdef CONFIG_RTW_MESH
-+	else
-+		_rtw_memcpy(mac, plink->addr, ETH_ALEN);
-+	#endif
-+	
-+	sinfo->filled = 0;
-+
-+	if (psta) {
-+		sinfo->filled |= STATION_INFO_SIGNAL;
-+		sinfo->signal = translate_percentage_to_dbm(psta->cmn.rssi_stat.rssi);
-+		sinfo->filled |= STATION_INFO_INACTIVE_TIME;
-+		sinfo->inactive_time = rtw_get_passing_time_ms(psta->sta_stats.last_rx_time);
-+	}
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(padapter))
-+		rtw_cfg80211_fill_mesh_only_sta_info(plink, psta, sinfo);
-+#endif
-+
-+exit:
-+	return ret;
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28))
-+static int	cfg80211_rtw_change_bss(struct wiphy *wiphy, struct net_device *ndev,
-+		struct bss_parameters *params)
-+{
-+	_adapter *adapter = rtw_netdev_priv(ndev);
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
-+
-+if (0) {
-+	if (params->use_cts_prot != -1)
-+		RTW_INFO("use_cts_prot=%d\n", params->use_cts_prot);
-+	if (params->use_short_preamble != -1)
-+		RTW_INFO("use_short_preamble=%d\n", params->use_short_preamble);
-+	if (params->use_short_slot_time != -1)
-+		RTW_INFO("use_short_slot_time=%d\n", params->use_short_slot_time);
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+	if (params->basic_rates && params->basic_rates_len) {
-+		RTW_INFO("basic_rates_len=%d\n", params->basic_rates_len);
-+		RTW_INFO_DUMP("basic_rates=", params->basic_rates, params->basic_rates_len);
-+	}
-+#endif
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	if (params->ap_isolate != -1) {
-+		RTW_INFO("ap_isolate=%d\n", params->ap_isolate);
-+		adapter->mlmepriv.ap_isolate = params->ap_isolate ? 1 : 0;
-+	}
-+#endif
-+
-+if (0) {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
-+	if (params->ht_opmode != -1)
-+		RTW_INFO("ht_opmode=0x%04x\n", params->ht_opmode);
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	if (params->p2p_ctwindow != -1)
-+		RTW_INFO("p2p_ctwindow=%d\n", params->p2p_ctwindow);
-+	if (params->p2p_opp_ps != -1)
-+		RTW_INFO("p2p_opp_ps=%d\n", params->p2p_opp_ps);
-+#endif
-+}
-+	return 0;
-+}
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)) */
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+static int	cfg80211_rtw_set_txq_params(struct wiphy *wiphy
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
-+	, struct net_device *ndev
-+#endif
-+	, struct ieee80211_txq_params *params)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
-+	_adapter *padapter = rtw_netdev_priv(ndev);
-+#else
-+	_adapter *padapter = wiphy_to_adapter(wiphy);
-+#endif
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	u8	ac, AIFS, ECWMin, ECWMax, aSifsTime;
-+	u16	TXOP;
-+	u8	shift_count = 0;
-+	u32	acParm;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
-+	ac = params->ac;
-+#else
-+	ac = params->queue;
-+#endif
-+
-+	switch (ac) {
-+	case NL80211_TXQ_Q_VO:
-+		ac = XMIT_VO_QUEUE;
-+		break;
-+
-+	case NL80211_TXQ_Q_VI:
-+		ac = XMIT_VI_QUEUE;
-+		break;
-+
-+	case NL80211_TXQ_Q_BE:
-+		ac = XMIT_BE_QUEUE;
-+		break;
-+
-+	case NL80211_TXQ_Q_BK:
-+		ac = XMIT_BK_QUEUE;
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+#if 0
-+	RTW_INFO("ac=%d\n", ac);
-+	RTW_INFO("txop=%u\n", params->txop);
-+	RTW_INFO("cwmin=%u\n", params->cwmin);
-+	RTW_INFO("cwmax=%u\n", params->cwmax);
-+	RTW_INFO("aifs=%u\n", params->aifs);
-+#endif
-+
-+	if (is_supported_5g(pmlmeext->cur_wireless_mode) ||
-+	    (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
-+		aSifsTime = 16;
-+	else
-+		aSifsTime = 10;
-+
-+	AIFS = params->aifs * pmlmeinfo->slotTime + aSifsTime;
-+
-+	while ((params->cwmin + 1) >> shift_count != 1) {
-+		shift_count++;
-+		if (shift_count == 15)
-+			break;
-+	}
-+
-+	ECWMin = shift_count;
-+
-+	shift_count = 0;
-+	while ((params->cwmax + 1) >> shift_count != 1) {
-+		shift_count++;
-+		if (shift_count == 15)
-+			break;
-+	}
-+
-+	ECWMax = shift_count;
-+
-+	TXOP = le16_to_cpu(params->txop);
-+
-+	acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16);
-+
-+	set_txq_params_cmd(padapter, acParm, ac);
-+
-+	return 0;
-+}
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) */
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
-+static int	cfg80211_rtw_set_channel(struct wiphy *wiphy
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	, struct net_device *ndev
-+	#endif
-+	, struct ieee80211_channel *chan, enum nl80211_channel_type channel_type)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+#else
-+	_adapter *padapter = wiphy_to_adapter(wiphy);
-+#endif
-+	int chan_target = (u8) ieee80211_frequency_to_channel(chan->center_freq);
-+	int chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	int chan_width = CHANNEL_WIDTH_20;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
-+#endif
-+
-+	switch (channel_type) {
-+	case NL80211_CHAN_NO_HT:
-+	case NL80211_CHAN_HT20:
-+		chan_width = CHANNEL_WIDTH_20;
-+		chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		break;
-+	case NL80211_CHAN_HT40MINUS:
-+		chan_width = CHANNEL_WIDTH_40;
-+		chan_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+		break;
-+	case NL80211_CHAN_HT40PLUS:
-+		chan_width = CHANNEL_WIDTH_40;
-+		chan_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+		break;
-+	default:
-+		chan_width = CHANNEL_WIDTH_20;
-+		chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		break;
-+	}
-+
-+	RTW_INFO(FUNC_ADPT_FMT" ch:%d bw:%d, offset:%d\n"
-+		, FUNC_ADPT_ARG(padapter), chan_target, chan_width, chan_offset);
-+
-+	rtw_set_chbw_cmd(padapter, chan_target, chan_width, chan_offset, RTW_CMDF_WAIT_ACK);
-+
-+	return 0;
-+}
-+#endif /*#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))*/
-+
-+/*
-+static int	cfg80211_rtw_auth(struct wiphy *wiphy, struct net_device *ndev,
-+		struct cfg80211_auth_request *req)
-+{
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
-+
-+	return 0;
-+}
-+
-+static int	cfg80211_rtw_assoc(struct wiphy *wiphy, struct net_device *ndev,
-+		struct cfg80211_assoc_request *req)
-+{
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
-+
-+	return 0;
-+}
-+*/
-+
-+static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, int len)
-+{
-+	int ret = 0;
-+	uint wps_ielen = 0;
-+	u8 *wps_ie;
-+	u32	p2p_ielen = 0;
-+	u8 wps_oui[8] = {0x0, 0x50, 0xf2, 0x04};
-+	u8 *p2p_ie;
-+	u32	wfd_ielen = 0;
-+	u8 *wfd_ie;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+
-+	RTW_INFO(FUNC_NDEV_FMT" ielen=%d\n", FUNC_NDEV_ARG(ndev), len);
-+
-+	if (len > 0) {
-+		wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen);
-+		if (wps_ie) {
-+			#ifdef CONFIG_DEBUG_CFG80211
-+			RTW_INFO("bcn_wps_ielen=%d\n", wps_ielen);
-+			#endif
-+
-+			if (pmlmepriv->wps_beacon_ie) {
-+				u32 free_len = pmlmepriv->wps_beacon_ie_len;
-+				pmlmepriv->wps_beacon_ie_len = 0;
-+				rtw_mfree(pmlmepriv->wps_beacon_ie, free_len);
-+				pmlmepriv->wps_beacon_ie = NULL;
-+			}
-+
-+			pmlmepriv->wps_beacon_ie = rtw_malloc(wps_ielen);
-+			if (pmlmepriv->wps_beacon_ie == NULL) {
-+				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
-+				return -EINVAL;
-+
-+			}
-+
-+			_rtw_memcpy(pmlmepriv->wps_beacon_ie, wps_ie, wps_ielen);
-+			pmlmepriv->wps_beacon_ie_len = wps_ielen;
-+
-+			update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE, RTW_CMDF_WAIT_ACK);
-+
-+		}
-+
-+		/* buf += wps_ielen; */
-+		/* len -= wps_ielen; */
-+
-+		#ifdef CONFIG_P2P
-+		p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen);
-+		if (p2p_ie) {
-+			#ifdef CONFIG_DEBUG_CFG80211
-+			RTW_INFO("bcn_p2p_ielen=%d\n", p2p_ielen);
-+			#endif
-+
-+			if (pmlmepriv->p2p_beacon_ie) {
-+				u32 free_len = pmlmepriv->p2p_beacon_ie_len;
-+				pmlmepriv->p2p_beacon_ie_len = 0;
-+				rtw_mfree(pmlmepriv->p2p_beacon_ie, free_len);
-+				pmlmepriv->p2p_beacon_ie = NULL;
-+			}
-+
-+			pmlmepriv->p2p_beacon_ie = rtw_malloc(p2p_ielen);
-+			if (pmlmepriv->p2p_beacon_ie == NULL) {
-+				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
-+				return -EINVAL;
-+
-+			}
-+
-+			_rtw_memcpy(pmlmepriv->p2p_beacon_ie, p2p_ie, p2p_ielen);
-+			pmlmepriv->p2p_beacon_ie_len = p2p_ielen;
-+
-+		}
-+		#endif /* CONFIG_P2P */
-+
-+
-+		#ifdef CONFIG_WFD
-+		wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen);
-+		if (wfd_ie) {
-+			#ifdef CONFIG_DEBUG_CFG80211
-+			RTW_INFO("bcn_wfd_ielen=%d\n", wfd_ielen);
-+			#endif
-+
-+			if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_BEACON_IE, wfd_ie, wfd_ielen) != _SUCCESS)
-+				return -EINVAL;
-+		}
-+		#endif /* CONFIG_WFD */
-+
-+		pmlmeext->bstart_bss = _TRUE;
-+
-+	}
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *buf, int len)
-+{
-+	int ret = 0;
-+	uint wps_ielen = 0;
-+	u8 *wps_ie;
-+	u32	p2p_ielen = 0;
-+	u8 *p2p_ie;
-+	u32	wfd_ielen = 0;
-+	u8 *wfd_ie;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+#ifdef CONFIG_DEBUG_CFG80211
-+	RTW_INFO("%s, ielen=%d\n", __func__, len);
-+#endif
-+
-+	if (len > 0) {
-+		wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen);
-+		if (wps_ie) {
-+			uint	attr_contentlen = 0;
-+			u16	uconfig_method, *puconfig_method = NULL;
-+
-+			#ifdef CONFIG_DEBUG_CFG80211
-+			RTW_INFO("probe_resp_wps_ielen=%d\n", wps_ielen);
-+			#endif
-+
-+			if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
-+				u8 sr = 0;
-+				rtw_get_wps_attr_content(wps_ie,  wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);
-+
-+				if (sr != 0)
-+					RTW_INFO("%s, got sr\n", __func__);
-+				else {
-+					RTW_INFO("GO mode process WPS under site-survey,  sr no set\n");
-+					return ret;
-+				}
-+			}
-+
-+			if (pmlmepriv->wps_probe_resp_ie) {
-+				u32 free_len = pmlmepriv->wps_probe_resp_ie_len;
-+				pmlmepriv->wps_probe_resp_ie_len = 0;
-+				rtw_mfree(pmlmepriv->wps_probe_resp_ie, free_len);
-+				pmlmepriv->wps_probe_resp_ie = NULL;
-+			}
-+
-+			pmlmepriv->wps_probe_resp_ie = rtw_malloc(wps_ielen);
-+			if (pmlmepriv->wps_probe_resp_ie == NULL) {
-+				RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
-+				return -EINVAL;
-+
-+			}
-+
-+			/* add PUSH_BUTTON config_method by driver self in wpsie of probe_resp at GO Mode */
-+			puconfig_method = (u16 *)rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_CONF_METHOD , NULL, &attr_contentlen);
-+			if (puconfig_method != NULL) {
-+				/* struct registry_priv *pregistrypriv = &padapter->registrypriv; */
-+				struct wireless_dev *wdev = padapter->rtw_wdev;
-+
-+				#ifdef CONFIG_DEBUG_CFG80211
-+				/* printk("config_method in wpsie of probe_resp = 0x%x\n", be16_to_cpu(*puconfig_method)); */
-+				#endif
-+
-+				#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+				/* for WIFI-DIRECT LOGO 4.2.2, AUTO GO can't set PUSH_BUTTON flags */
-+				if (wdev->iftype == NL80211_IFTYPE_P2P_GO) {
-+					uconfig_method = WPS_CM_PUSH_BUTTON;
-+					uconfig_method = cpu_to_be16(uconfig_method);
-+
-+					*puconfig_method &= ~uconfig_method;
-+				}
-+				#endif
-+			}
-+
-+			_rtw_memcpy(pmlmepriv->wps_probe_resp_ie, wps_ie, wps_ielen);
-+			pmlmepriv->wps_probe_resp_ie_len = wps_ielen;
-+
-+		}
-+
-+		/* buf += wps_ielen; */
-+		/* len -= wps_ielen; */
-+
-+		#ifdef CONFIG_P2P
-+		p2p_ie = rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen);
-+		if (p2p_ie) {
-+			u8 is_GO = _FALSE;
-+			u32 attr_contentlen = 0;
-+			u16 cap_attr = 0;
-+
-+			#ifdef CONFIG_DEBUG_CFG80211
-+			RTW_INFO("probe_resp_p2p_ielen=%d\n", p2p_ielen);
-+			#endif
-+
-+			/* Check P2P Capability ATTR */
-+			if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *) &attr_contentlen)) {
-+				u8 grp_cap = 0;
-+				/* RTW_INFO( "[%s] Got P2P Capability Attr!!\n", __FUNCTION__ ); */
-+				cap_attr = le16_to_cpu(cap_attr);
-+				grp_cap = (u8)((cap_attr >> 8) & 0xff);
-+
-+				is_GO = (grp_cap & BIT(0)) ? _TRUE : _FALSE;
-+
-+				if (is_GO)
-+					RTW_INFO("Got P2P Capability Attr, grp_cap=0x%x, is_GO\n", grp_cap);
-+			}
-+
-+
-+			if (is_GO == _FALSE) {
-+				if (pmlmepriv->p2p_probe_resp_ie) {
-+					u32 free_len = pmlmepriv->p2p_probe_resp_ie_len;
-+					pmlmepriv->p2p_probe_resp_ie_len = 0;
-+					rtw_mfree(pmlmepriv->p2p_probe_resp_ie, free_len);
-+					pmlmepriv->p2p_probe_resp_ie = NULL;
-+				}
-+
-+				pmlmepriv->p2p_probe_resp_ie = rtw_malloc(p2p_ielen);
-+				if (pmlmepriv->p2p_probe_resp_ie == NULL) {
-+					RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
-+					return -EINVAL;
-+
-+				}
-+				_rtw_memcpy(pmlmepriv->p2p_probe_resp_ie, p2p_ie, p2p_ielen);
-+				pmlmepriv->p2p_probe_resp_ie_len = p2p_ielen;
-+			} else {
-+				if (pmlmepriv->p2p_go_probe_resp_ie) {
-+					u32 free_len = pmlmepriv->p2p_go_probe_resp_ie_len;
-+					pmlmepriv->p2p_go_probe_resp_ie_len = 0;
-+					rtw_mfree(pmlmepriv->p2p_go_probe_resp_ie, free_len);
-+					pmlmepriv->p2p_go_probe_resp_ie = NULL;
-+				}
-+
-+				pmlmepriv->p2p_go_probe_resp_ie = rtw_malloc(p2p_ielen);
-+				if (pmlmepriv->p2p_go_probe_resp_ie == NULL) {
-+					RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
-+					return -EINVAL;
-+
-+				}
-+				_rtw_memcpy(pmlmepriv->p2p_go_probe_resp_ie, p2p_ie, p2p_ielen);
-+				pmlmepriv->p2p_go_probe_resp_ie_len = p2p_ielen;
-+			}
-+
-+		}
-+		#endif /* CONFIG_P2P */
-+
-+
-+		#ifdef CONFIG_WFD
-+		wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen);
-+		#ifdef CONFIG_DEBUG_CFG80211
-+		RTW_INFO("probe_resp_wfd_ielen=%d\n", wfd_ielen);
-+		#endif
-+
-+		if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_PROBE_RESP_IE, wfd_ie, wfd_ielen) != _SUCCESS)
-+			return -EINVAL;
-+		#endif /* CONFIG_WFD */
-+
-+	}
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_cfg80211_set_assoc_resp_wpsp2pie(struct net_device *net, char *buf, int len)
-+{
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	u8 *ie;
-+	u32 ie_len;
-+
-+	RTW_INFO("%s, ielen=%d\n", __func__, len);
-+
-+	if (len <= 0)
-+		goto exit;
-+
-+	ie = rtw_get_wps_ie(buf, len, NULL, &ie_len);
-+	if (ie && ie_len) {
-+		if (pmlmepriv->wps_assoc_resp_ie) {
-+			u32 free_len = pmlmepriv->wps_assoc_resp_ie_len;
-+
-+			pmlmepriv->wps_assoc_resp_ie_len = 0;
-+			rtw_mfree(pmlmepriv->wps_assoc_resp_ie, free_len);
-+			pmlmepriv->wps_assoc_resp_ie = NULL;
-+		}
-+
-+		pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len);
-+		if (pmlmepriv->wps_assoc_resp_ie == NULL) {
-+			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
-+			return -EINVAL;
-+		}
-+		_rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, ie, ie_len);
-+		pmlmepriv->wps_assoc_resp_ie_len = ie_len;
-+	}
-+#ifdef CONFIG_P2P
-+	ie = rtw_get_p2p_ie(buf, len, NULL, &ie_len);
-+	if (ie && ie_len) {
-+		if (pmlmepriv->p2p_assoc_resp_ie) {
-+			u32 free_len = pmlmepriv->p2p_assoc_resp_ie_len;
-+
-+			pmlmepriv->p2p_assoc_resp_ie_len = 0;
-+			rtw_mfree(pmlmepriv->p2p_assoc_resp_ie, free_len);
-+			pmlmepriv->p2p_assoc_resp_ie = NULL;
-+		}
-+
-+		pmlmepriv->p2p_assoc_resp_ie = rtw_malloc(ie_len);
-+		if (pmlmepriv->p2p_assoc_resp_ie == NULL) {
-+			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
-+			return -EINVAL;
-+		}
-+		_rtw_memcpy(pmlmepriv->p2p_assoc_resp_ie, ie, ie_len);
-+		pmlmepriv->p2p_assoc_resp_ie_len = ie_len;
-+	}
-+#endif
-+#ifdef CONFIG_WFD
-+	ie = rtw_get_wfd_ie(buf, len, NULL, &ie_len);
-+	if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_ASSOC_RESP_IE, ie, ie_len) != _SUCCESS)
-+		return -EINVAL;
-+#endif
-+
-+exit:
-+	return ret;
-+}
-+
-+int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len,
-+	int type)
-+{
-+	int ret = 0;
-+	uint wps_ielen = 0;
-+	u32	p2p_ielen = 0;
-+
-+#ifdef CONFIG_DEBUG_CFG80211
-+	RTW_INFO("%s, ielen=%d\n", __func__, len);
-+#endif
-+
-+	if ((rtw_get_wps_ie(buf, len, NULL, &wps_ielen) && (wps_ielen > 0))
-+		#ifdef CONFIG_P2P
-+		|| (rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen) && (p2p_ielen > 0))
-+		#endif
-+	) {
-+		if (net != NULL) {
-+			switch (type) {
-+			case 0x1: /* BEACON */
-+				ret = rtw_cfg80211_set_beacon_wpsp2pie(net, buf, len);
-+				break;
-+			case 0x2: /* PROBE_RESP */
-+				ret = rtw_cfg80211_set_probe_resp_wpsp2pie(net, buf, len);
-+				#ifdef CONFIG_P2P
-+				if (ret == 0)
-+					adapter_wdev_data((_adapter *)rtw_netdev_priv(net))->probe_resp_ie_update_time = rtw_get_current_time();
-+				#endif
-+				break;
-+			case 0x4: /* ASSOC_RESP */
-+				ret = rtw_cfg80211_set_assoc_resp_wpsp2pie(net, buf, len);
-+				break;
-+			}
-+		}
-+	}
-+
-+	return ret;
-+
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+static struct wireless_dev *
-+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
-+static struct net_device *
-+#else
-+static int
-+#endif
-+	cfg80211_rtw_add_virtual_intf(
-+		struct wiphy *wiphy,
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
-+		const char *name,
-+		#else
-+		char *name,
-+		#endif
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
-+		unsigned char name_assign_type,
-+		#endif
-+		enum nl80211_iftype type,
-+		#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
-+		u32 *flags,
-+		#endif
-+		struct vif_params *params)
-+{
-+	int ret = 0;
-+	struct wireless_dev *wdev = NULL;
-+	struct net_device *ndev = NULL;
-+	_adapter *padapter;
-+	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
-+
-+	rtw_set_rtnl_lock_holder(dvobj, current);
-+
-+	RTW_INFO(FUNC_WIPHY_FMT" name:%s, type:%d\n", FUNC_WIPHY_ARG(wiphy), name, type);
-+
-+	switch (type) {
-+	case NL80211_IFTYPE_MONITOR:
-+		padapter = wiphy_to_adapter(wiphy); /* TODO: get ap iface ? */
-+		ret = rtw_cfg80211_add_monitor_if(padapter, (char *)name, &ndev);
-+		if (ret == 0)
-+			wdev = ndev->ieee80211_ptr;
-+		break;
-+
-+#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
-+	case NL80211_IFTYPE_P2P_CLIENT:
-+	case NL80211_IFTYPE_P2P_GO:
-+#endif
-+	case NL80211_IFTYPE_STATION:
-+	case NL80211_IFTYPE_AP:
-+#ifdef CONFIG_RTW_MESH
-+	case NL80211_IFTYPE_MESH_POINT:
-+#endif
-+		padapter = dvobj_get_unregisterd_adapter(dvobj);
-+		if (!padapter) {
-+			RTW_WARN("adapter pool empty!\n");
-+			ret = -ENODEV;
-+			break;
-+		}
-+
-+		#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P)
-+		#if defined(CONFIG_P2P) && ((KERNEL_VERSION(2, 6, 37) <= LINUX_VERSION_CODE) || defined(COMPAT_KERNEL_RELEASE))
-+		if ((type == NL80211_IFTYPE_P2P_CLIENT || type == NL80211_IFTYPE_P2P_GO) && (padapter->iface_id != padapter->registrypriv.sel_p2p_iface)) {
-+			RTW_ERR("%s, iface_id:%d is not P2P interface!\n", __func__, padapter->iface_id);
-+			ret = -EOPNOTSUPP;
-+			break;
-+		}
-+		#endif
-+		#endif
-+
-+		if (rtw_os_ndev_init(padapter, name) != _SUCCESS) {
-+			RTW_WARN("ndev init fail!\n");
-+			ret = -ENODEV;
-+			break;
-+		}
-+		#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
-+		if (type == NL80211_IFTYPE_P2P_CLIENT || type == NL80211_IFTYPE_P2P_GO)
-+			rtw_p2p_enable(padapter, P2P_ROLE_DEVICE);
-+		#endif
-+		ndev = padapter->pnetdev;
-+		wdev = ndev->ieee80211_ptr;
-+		break;
-+
-+#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE)
-+	case NL80211_IFTYPE_P2P_DEVICE:
-+		ret = rtw_pd_iface_alloc(wiphy, name, &wdev);
-+		break;
-+#endif
-+
-+	case NL80211_IFTYPE_ADHOC:
-+	case NL80211_IFTYPE_AP_VLAN:
-+	case NL80211_IFTYPE_WDS:
-+	default:
-+		ret = -ENODEV;
-+		RTW_INFO("Unsupported interface type\n");
-+		break;
-+	}
-+
-+	if (ndev)
-+		RTW_INFO(FUNC_WIPHY_FMT" ndev:%p, ret:%d\n", FUNC_WIPHY_ARG(wiphy), ndev, ret);
-+	else
-+		RTW_INFO(FUNC_WIPHY_FMT" wdev:%p, ret:%d\n", FUNC_WIPHY_ARG(wiphy), wdev, ret);
-+
-+	rtw_set_rtnl_lock_holder(dvobj, NULL);
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	return wdev ? wdev : ERR_PTR(ret);
-+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
-+	return ndev ? ndev : ERR_PTR(ret);
-+#else
-+	return ret;
-+#endif
-+}
-+
-+static int cfg80211_rtw_del_virtual_intf(struct wiphy *wiphy,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	struct wireless_dev *wdev
-+#else
-+	struct net_device *ndev
-+#endif
-+)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	struct net_device *ndev = wdev_to_ndev(wdev);
-+#endif
-+	int ret = 0;
-+	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
-+	_adapter *adapter;
-+	struct rtw_wdev_priv *pwdev_priv;
-+
-+	rtw_set_rtnl_lock_holder(dvobj, current);
-+
-+	if (ndev) {
-+		adapter = (_adapter *)rtw_netdev_priv(ndev);
-+		pwdev_priv = adapter_wdev_data(adapter);
-+
-+		if (ndev == pwdev_priv->pmon_ndev) {
-+			unregister_netdevice(ndev);
-+			pwdev_priv->pmon_ndev = NULL;
-+			pwdev_priv->ifname_mon[0] = '\0';
-+			RTW_INFO(FUNC_NDEV_FMT" remove monitor ndev\n", FUNC_NDEV_ARG(ndev));
-+		} else {
-+			RTW_INFO(FUNC_NDEV_FMT" unregister ndev\n", FUNC_NDEV_ARG(ndev));
-+			rtw_os_ndev_unregister(adapter);
-+		}
-+	} else
-+#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE)
-+	if (wdev->iftype == NL80211_IFTYPE_P2P_DEVICE) {
-+		if (wdev == wiphy_to_pd_wdev(wiphy))
-+			rtw_pd_iface_free(wiphy);
-+		else {
-+			RTW_ERR(FUNC_WIPHY_FMT" unknown P2P Device wdev:%p\n", FUNC_WIPHY_ARG(wiphy), wdev);
-+			rtw_warn_on(1);
-+		}
-+	} else
-+#endif
-+	{
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+exit:
-+	rtw_set_rtnl_lock_holder(dvobj, NULL);
-+	return ret;
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+static int cfg80211_rtw_get_channel(struct wiphy *wiphy,
-+	struct wireless_dev *wdev,
-+	struct cfg80211_chan_def *chandef)
-+{
-+	_adapter *padapter = wiphy_to_adapter(wiphy);
-+	struct mlme_ext_priv *mlmeext = &(padapter->mlmeextpriv);
-+	u8 ht_option = 0;
-+	u8 report = 0;
-+	int retval = 1;
-+
-+	if (MLME_IS_ASOC(padapter)) {
-+#ifdef CONFIG_80211N_HT
-+		ht_option = padapter->mlmepriv.htpriv.ht_option;
-+#endif /* CONFIG_80211N_HT */
-+		report = 1;
-+	} else if (MLME_IS_MONITOR(padapter)) {
-+		/* monitor mode always set to HT
-+		   we don't support sniffer No HT */
-+		ht_option = 1;
-+		report = 1;
-+	}
-+
-+	if (report) {
-+		rtw_chbw_to_cfg80211_chan_def(wiphy, chandef,
-+			mlmeext->cur_channel, mlmeext->cur_bwmode,
-+			mlmeext->cur_ch_offset, ht_option);
-+		retval = 0;
-+	}
-+
-+	return retval;
-+}
-+
-+static void rtw_get_chbwoff_from_cfg80211_chan_def(
-+	struct cfg80211_chan_def *chandef,
-+	u8 *ht, u8 *ch, u8 *bw, u8 *offset)
-+{
-+	struct ieee80211_channel *chan = chandef->chan;
-+
-+	*ch = chan->hw_value;
-+	*ht = 1;
-+
-+	switch (chandef->width) {
-+	case NL80211_CHAN_WIDTH_20_NOHT:
-+		*ht = 0;
-+		fallthrough;
-+	case NL80211_CHAN_WIDTH_20:
-+		*bw = CHANNEL_WIDTH_20;
-+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		break;
-+	case NL80211_CHAN_WIDTH_40:
-+		*bw = CHANNEL_WIDTH_40;
-+		*offset = (chandef->center_freq1 > chan->center_freq) ?
-+			HAL_PRIME_CHNL_OFFSET_LOWER : HAL_PRIME_CHNL_OFFSET_UPPER;
-+		break;
-+	case NL80211_CHAN_WIDTH_80:
-+		*bw = CHANNEL_WIDTH_80;
-+		*offset = (chandef->center_freq1 > chan->center_freq) ?
-+			HAL_PRIME_CHNL_OFFSET_LOWER : HAL_PRIME_CHNL_OFFSET_UPPER;
-+		break;
-+	case NL80211_CHAN_WIDTH_160:
-+		*bw = CHANNEL_WIDTH_160;
-+		*offset = (chandef->center_freq1 > chan->center_freq) ?
-+			HAL_PRIME_CHNL_OFFSET_LOWER : HAL_PRIME_CHNL_OFFSET_UPPER;
-+		break;
-+	case NL80211_CHAN_WIDTH_80P80:
-+		*bw = CHANNEL_WIDTH_80_80;
-+		*offset = (chandef->center_freq1 > chan->center_freq) ?
-+			HAL_PRIME_CHNL_OFFSET_LOWER : HAL_PRIME_CHNL_OFFSET_UPPER;
-+		break;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+	case NL80211_CHAN_WIDTH_5:
-+		*bw = CHANNEL_WIDTH_5;
-+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		break;
-+	case NL80211_CHAN_WIDTH_10:
-+		*bw = CHANNEL_WIDTH_10;
-+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		break;
-+#endif
-+	default:
-+		*ht = 0;
-+		*bw = CHANNEL_WIDTH_20;
-+		*offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		RTW_INFO("unsupported cwidth:%u\n", chandef->width);
-+		rtw_warn_on(1);
-+	};
-+}
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) */
-+
-+static int cfg80211_rtw_set_monitor_channel(struct wiphy *wiphy
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	, struct cfg80211_chan_def *chandef
-+#else
-+	, struct ieee80211_channel *chan
-+	, enum nl80211_channel_type channel_type
-+#endif
-+	)
-+{
-+	_adapter *padapter = wiphy_to_adapter(wiphy);
-+	u8 target_channal, target_offset, target_width, ht_option;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+#ifdef CONFIG_DEBUG_CFG80211
-+	RTW_INFO("center_freq %u Mhz ch %u width %u freq1 %u freq2 %u\n"
-+		, chandef->chan->center_freq
-+		, chandef->chan->hw_value
-+		, chandef->width
-+		, chandef->center_freq1
-+		, chandef->center_freq2);
-+#endif /* CONFIG_DEBUG_CFG80211 */
-+
-+	rtw_get_chbwoff_from_cfg80211_chan_def(chandef,
-+		&ht_option, &target_channal, &target_width, &target_offset);
-+#else
-+#ifdef CONFIG_DEBUG_CFG80211
-+	RTW_INFO("center_freq %u Mhz ch %u channel_type %u\n"
-+		, chan->center_freq
-+		, chan->hw_value
-+		, channel_type);
-+#endif /* CONFIG_DEBUG_CFG80211 */
-+
-+	rtw_get_chbw_from_nl80211_channel_type(chan, channel_type,
-+		&ht_option, &target_channal, &target_width, &target_offset);
-+#endif
-+	RTW_INFO(FUNC_ADPT_FMT" ch:%d bw:%d, offset:%d\n",
-+		FUNC_ADPT_ARG(padapter), target_channal,
-+		target_width, target_offset);
-+
-+	rtw_set_chbw_cmd(padapter, target_channal, target_width,
-+		target_offset, RTW_CMDF_WAIT_ACK);
-+
-+	return 0;
-+}
-+
-+void rtw_cfg80211_external_auth_request(_adapter *padapter, union recv_frame *rframe)
-+{
-+	struct rtw_external_auth_params params;
-+	struct wireless_dev *wdev = padapter->rtw_wdev;
-+	struct net_device *netdev = wdev_to_ndev(wdev);
-+	struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
-+
-+	u8 frame[256] = { 0 };
-+	uint frame_len = 24;
-+	s32 freq = 0;
-+
-+	/* rframe, in this case is null point */
-+
-+	freq = rtw_ch2freq(pmlmeext->cur_channel);
-+
-+#if (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE) \
-+    || defined(CONFIG_KERNEL_PATCH_EXTERNAL_AUTH)
-+	params.action = EXTERNAL_AUTH_START;
-+	_rtw_memcpy(params.bssid, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
-+	params.ssid.ssid_len = pmlmeinfo->network.Ssid.SsidLength;
-+	_rtw_memcpy(params.ssid.ssid, pmlmeinfo->network.Ssid.Ssid,
-+		pmlmeinfo->network.Ssid.SsidLength);
-+	params.key_mgmt_suite = 0x8ac0f00;
-+
-+	cfg80211_external_auth_request(netdev,
-+		(struct cfg80211_external_auth_params *)&params, GFP_ATOMIC);
-+#elif (KERNEL_VERSION(2, 6, 37) <= LINUX_VERSION_CODE)
-+	set_frame_sub_type(frame, WIFI_AUTH);
-+
-+	_rtw_memcpy(frame + 4, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
-+	_rtw_memcpy(frame + 10, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(frame + 16, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
-+	RTW_PUT_LE32((frame + 18), 0x8ac0f00);
-+
-+	if (pmlmeinfo->network.Ssid.SsidLength) {
-+		*(frame + 23) = pmlmeinfo->network.Ssid.SsidLength;
-+		_rtw_memcpy(frame + 24, pmlmeinfo->network.Ssid.Ssid,
-+			pmlmeinfo->network.Ssid.SsidLength);
-+		frame_len = 24 + pmlmeinfo->network.Ssid.SsidLength;
-+	}
-+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
-+#endif
-+}
-+
-+void rtw_cfg80211_rx_probe_request(_adapter *adapter, union recv_frame *rframe)
-+{
-+	struct wireless_dev *wdev = adapter->rtw_wdev;
-+	u8 *frame = get_recvframe_data(rframe);
-+	uint frame_len = rframe->u.hdr.len;
-+	s32 freq;
-+	u8 ch, sch = rtw_get_oper_ch(adapter);
-+
-+	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
-+	freq = rtw_ch2freq(ch);
-+
-+#ifdef CONFIG_DEBUG_CFG80211
-+	RTW_INFO("RTW_Rx: probe request, ch=%d(%d), ta="MAC_FMT"\n"
-+		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)
-+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
-+#else
-+	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
-+#endif
-+}
-+
-+void rtw_cfg80211_rx_action_p2p(_adapter *adapter, union recv_frame *rframe)
-+{
-+	struct wireless_dev *wdev = adapter->rtw_wdev;
-+	u8 *frame = get_recvframe_data(rframe);
-+	uint frame_len = rframe->u.hdr.len;
-+	s32 freq;
-+	u8 ch, sch = rtw_get_oper_ch(adapter);
-+	u8 category, action;
-+	int type;
-+
-+	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
-+	freq = rtw_ch2freq(ch);
-+
-+	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n"
-+		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
-+#ifdef CONFIG_P2P
-+	type = rtw_p2p_check_frames(adapter, frame, frame_len, _FALSE);
-+	if (type >= 0)
-+		goto indicate;
-+#endif
-+	rtw_action_frame_parse(frame, frame_len, &category, &action);
-+	RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action);
-+#ifdef CONFIG_P2P
-+indicate:
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
-+#else
-+	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
-+#endif
-+}
-+
-+void rtw_cfg80211_rx_p2p_action_public(_adapter *adapter, union recv_frame *rframe)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct wireless_dev *wdev = adapter->rtw_wdev;
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
-+	u8 *frame = get_recvframe_data(rframe);
-+	uint frame_len = rframe->u.hdr.len;
-+	s32 freq;
-+	u8 ch, sch = rtw_get_oper_ch(adapter);
-+	u8 category, action;
-+	int type;
-+
-+	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
-+	freq = rtw_ch2freq(ch);
-+
-+	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n"
-+		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
-+	#ifdef CONFIG_P2P
-+	type = rtw_p2p_check_frames(adapter, frame, frame_len, _FALSE);
-+	if (type >= 0) {
-+		switch (type) {
-+		case P2P_GO_NEGO_CONF:
-+			if (0) {
-+				RTW_INFO(FUNC_ADPT_FMT" Nego confirm. state=%u, status=%u, iaddr="MAC_FMT"\n"
-+					, FUNC_ADPT_ARG(adapter), pwdev_priv->nego_info.state, pwdev_priv->nego_info.status
-+					, MAC_ARG(pwdev_priv->nego_info.iface_addr));
-+			}
-+			if (pwdev_priv->nego_info.state == 2
-+				&& pwdev_priv->nego_info.status == 0
-+				&& rtw_check_invalid_mac_address(pwdev_priv->nego_info.iface_addr, _FALSE) == _FALSE
-+			) {
-+				_adapter *intended_iface = dvobj_get_adapter_by_addr(dvobj, pwdev_priv->nego_info.iface_addr);
-+
-+				if (intended_iface) {
-+					RTW_INFO(FUNC_ADPT_FMT" Nego confirm. Allow only "ADPT_FMT" to scan for 2000 ms\n"
-+						, FUNC_ADPT_ARG(adapter), ADPT_ARG(intended_iface));
-+					/* allow only intended_iface to do scan for 2000 ms */
-+					rtw_mi_set_scan_deny(adapter, 2000);
-+					rtw_clear_scan_deny(intended_iface);
-+				}
-+			}
-+			break;
-+		case P2P_PROVISION_DISC_RESP:
-+		case P2P_INVIT_RESP:
-+			rtw_clear_scan_deny(adapter);
-+			#if !RTW_P2P_GROUP_INTERFACE
-+			rtw_mi_buddy_set_scan_deny(adapter, 2000);
-+			#endif
-+			break;
-+		}
-+		goto indicate;
-+	}
-+	#endif
-+	rtw_action_frame_parse(frame, frame_len, &category, &action);
-+	RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action);
-+#ifdef CONFIG_P2P
-+indicate:
-+#endif
-+	#if defined(RTW_DEDICATED_P2P_DEVICE)
-+	if (rtw_cfg80211_redirect_pd_wdev(dvobj_to_wiphy(dvobj), get_ra(frame), &wdev))
-+		if (0)
-+			RTW_INFO("redirect to pd_wdev:%p\n", wdev);
-+	#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
-+#else
-+	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
-+#endif
-+}
-+
-+void rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const char *msg)
-+{
-+	struct wireless_dev *wdev = adapter->rtw_wdev;
-+	u8 *frame = get_recvframe_data(rframe);
-+	uint frame_len = rframe->u.hdr.len;
-+	s32 freq;
-+	u8 ch, sch = rtw_get_oper_ch(adapter);
-+	u8 category, action;
-+	int type = -1;
-+
-+	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
-+	freq = rtw_ch2freq(ch);
-+
-+	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n"
-+		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
-+
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(adapter)) {
-+		type = rtw_mesh_check_frames_rx(adapter, frame, frame_len);
-+		if (type >= 0)
-+			goto indicate;
-+	}
-+#endif
-+	rtw_action_frame_parse(frame, frame_len, &category, &action);
-+	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
-+		if (action == ACT_PUBLIC_GAS_INITIAL_REQ) {
-+			rtw_mi_set_scan_deny(adapter, 200);
-+			rtw_mi_scan_abort(adapter, _FALSE); /*rtw_scan_abort_no_wait*/
-+		}
-+	}
-+#ifdef CONFIG_RTW_MESH
-+indicate:
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
-+#else
-+	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
-+#endif
-+
-+	if (type == -1) {
-+		if (msg)
-+			RTW_INFO("RTW_Rx:%s\n", msg);
-+		else
-+			RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action);
-+	}
-+}
-+
-+#ifdef CONFIG_RTW_80211K
-+void rtw_cfg80211_rx_rrm_action(_adapter *adapter, union recv_frame *rframe)
-+{
-+	struct wireless_dev *wdev = adapter->rtw_wdev;
-+	u8 *frame = get_recvframe_data(rframe);
-+	uint frame_len = rframe->u.hdr.len;
-+	s32 freq;
-+	u8 ch, sch = rtw_get_oper_ch(adapter);
-+
-+	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
-+	freq = rtw_ch2freq(ch);
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
-+#else
-+	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
-+#endif
-+	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n"
-+		, ch, sch, MAC_ARG(get_addr2_ptr(frame)));
-+}
-+#endif /* CONFIG_RTW_80211K */
-+
-+void rtw_cfg80211_rx_mframe(_adapter *adapter, union recv_frame *rframe, const char *msg)
-+{
-+	struct wireless_dev *wdev = adapter->rtw_wdev;
-+	u8 *frame = get_recvframe_data(rframe);
-+	uint frame_len = rframe->u.hdr.len;
-+	s32 freq;
-+	u8 ch, sch = rtw_get_oper_ch(adapter);
-+
-+	ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch;
-+	freq = rtw_ch2freq(ch);
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+	rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC);
-+#else
-+	cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC);
-+#endif
-+
-+	RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n", ch, sch, MAC_ARG(get_addr2_ptr(frame)));
-+	if (!rtw_sae_preprocess(adapter, frame, frame_len, _FALSE)) {
-+		if (msg)
-+			RTW_INFO("RTW_Rx:%s\n", msg);
-+		else
-+			RTW_INFO("RTW_Rx:frame_control:0x%02x\n", le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)rframe)->frame_ctl));
-+	}
-+}
-+
-+#ifdef CONFIG_P2P
-+void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len)
-+{
-+	u16	wps_devicepassword_id = 0x0000;
-+	uint	wps_devicepassword_id_len = 0;
-+	u8			wpsie[255] = { 0x00 }, p2p_ie[255] = { 0x00 };
-+	uint			p2p_ielen = 0;
-+	uint			wpsielen = 0;
-+	u32	devinfo_contentlen = 0;
-+	u8	devinfo_content[64] = { 0x00 };
-+	u16	capability = 0;
-+	uint capability_len = 0;
-+
-+	unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
-+	u8			action = P2P_PUB_ACTION_ACTION;
-+	u8			dialogToken = 1;
-+	u32			p2poui = cpu_to_be32(P2POUI);
-+	u8			oui_subtype = P2P_PROVISION_DISC_REQ;
-+	u32			p2pielen = 0;
-+#ifdef CONFIG_WFD
-+	u32					wfdielen = 0;
-+#endif
-+
-+	struct xmit_frame			*pmgntframe;
-+	struct pkt_attrib			*pattrib;
-+	unsigned char					*pframe;
-+	struct rtw_ieee80211_hdr	*pwlanhdr;
-+	unsigned short				*fctrl;
-+	struct xmit_priv			*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+	u8 *frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr));
-+	size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+
-+	RTW_INFO("[%s] In\n", __FUNCTION__);
-+
-+	/* prepare for building provision_request frame	 */
-+	_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr1Ptr(buf), ETH_ALEN);
-+	_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, GetAddr1Ptr(buf), ETH_ALEN);
-+
-+	pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;
-+
-+	rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen);
-+	rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len);
-+	wps_devicepassword_id = be16_to_cpu(wps_devicepassword_id);
-+
-+	switch (wps_devicepassword_id) {
-+	case WPS_DPID_PIN:
-+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL;
-+		break;
-+	case WPS_DPID_USER_SPEC:
-+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA;
-+		break;
-+	case WPS_DPID_MACHINE_SPEC:
-+		break;
-+	case WPS_DPID_REKEY:
-+		break;
-+	case WPS_DPID_PBC:
-+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;
-+		break;
-+	case WPS_DPID_REGISTRAR_SPEC:
-+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+
-+	if (rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, p2p_ie, &p2p_ielen)) {
-+
-+		rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, devinfo_content, &devinfo_contentlen);
-+		rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&capability, &capability_len);
-+
-+	}
-+
-+
-+	/* start to build provision_request frame	 */
-+	_rtw_memset(wpsie, 0, sizeof(wpsie));
-+	_rtw_memset(p2p_ie, 0, sizeof(p2p_ie));
-+	p2p_ielen = 0;
-+
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL)
-+		return;
-+
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	fctrl = &(pwlanhdr->frame_ctl);
-+	*(fctrl) = 0;
-+
-+	_rtw_memcpy(pwlanhdr->addr1, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pwlanhdr->addr3, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN);
-+
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+	set_frame_sub_type(pframe, WIFI_ACTION);
-+
-+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
-+	pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
-+
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen));
-+	pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen));
-+
-+
-+	/* build_prov_disc_request_p2p_ie	 */
-+	/*	P2P OUI */
-+	p2pielen = 0;
-+	p2p_ie[p2pielen++] = 0x50;
-+	p2p_ie[p2pielen++] = 0x6F;
-+	p2p_ie[p2pielen++] = 0x9A;
-+	p2p_ie[p2pielen++] = 0x09;	/*	WFA P2P v1.0 */
-+
-+	/*	Commented by Albert 20110301 */
-+	/*	According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes */
-+	/*	1. P2P Capability */
-+	/*	2. Device Info */
-+	/*	3. Group ID ( When joining an operating P2P Group ) */
-+
-+	/*	P2P Capability ATTR */
-+	/*	Type:	 */
-+	p2p_ie[p2pielen++] = P2P_ATTR_CAPABILITY;
-+
-+	/*	Length: */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */
-+	RTW_PUT_LE16(p2p_ie + p2pielen, 0x0002);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	/*	Device Capability Bitmap, 1 byte */
-+	/*	Group Capability Bitmap, 1 byte */
-+	_rtw_memcpy(p2p_ie + p2pielen, &capability, 2);
-+	p2pielen += 2;
-+
-+
-+	/*	Device Info ATTR */
-+	/*	Type: */
-+	p2p_ie[p2pielen++] = P2P_ATTR_DEVICE_INFO;
-+
-+	/*	Length: */
-+	/*	21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes)  */
-+	/*	+ NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */
-+	/* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */
-+	RTW_PUT_LE16(p2p_ie + p2pielen, devinfo_contentlen);
-+	p2pielen += 2;
-+
-+	/*	Value: */
-+	_rtw_memcpy(p2p_ie + p2pielen, devinfo_content, devinfo_contentlen);
-+	p2pielen += devinfo_contentlen;
-+
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2p_ie, &p2p_ielen);
-+	/* p2pielen = build_prov_disc_request_p2p_ie( pwdinfo, pframe, NULL, 0, pwdinfo->tx_prov_disc_info.peerDevAddr); */
-+	/* pframe += p2pielen; */
-+	pattrib->pktlen += p2p_ielen;
-+
-+	wpsielen = 0;
-+	/*	WPS OUI */
-+	*(u32 *)(wpsie) = cpu_to_be32(WPSOUI);
-+	wpsielen += 4;
-+
-+	/*	WPS version */
-+	/*	Type: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1);
-+	wpsielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001);
-+	wpsielen += 2;
-+
-+	/*	Value: */
-+	wpsie[wpsielen++] = WPS_VERSION_1;	/*	Version 1.0 */
-+
-+	/*	Config Method */
-+	/*	Type: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD);
-+	wpsielen += 2;
-+
-+	/*	Length: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002);
-+	wpsielen += 2;
-+
-+	/*	Value: */
-+	*(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->tx_prov_disc_info.wps_config_method_request);
-+	wpsielen += 2;
-+
-+	pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen);
-+
-+
-+#ifdef CONFIG_WFD
-+	wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe);
-+	pframe += wfdielen;
-+	pattrib->pktlen += wfdielen;
-+#endif
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	/* dump_mgntframe(padapter, pmgntframe); */
-+	if (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS)
-+		RTW_INFO("%s, ack to\n", __func__);
-+
-+	#if 0
-+	if(wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) {
-+		RTW_INFO("waiting for p2p peer key-in PIN CODE\n");
-+		rtw_msleep_os(15000); /* 15 sec for key in PIN CODE, workaround for GS2 before issuing Nego Req. */
-+	}
-+	#endif
-+
-+}
-+
-+#ifdef CONFIG_RTW_80211R
-+static s32 cfg80211_rtw_update_ft_ies(struct wiphy *wiphy,
-+	struct net_device *ndev,
-+	struct cfg80211_update_ft_ies_params *ftie)
-+{
-+	_adapter *padapter = NULL;
-+	struct mlme_priv *pmlmepriv = NULL;
-+	struct ft_roam_info *pft_roam = NULL;
-+	_irqL irqL;
-+	u8 *p;
-+	u8 *pie = NULL;
-+	u32 ie_len = 0;
-+
-+	if (ndev == NULL)
-+		return  -EINVAL;
-+
-+	padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	pmlmepriv = &(padapter->mlmepriv);
-+	pft_roam = &(pmlmepriv->ft_roam);
-+
-+	p = (u8 *)ftie->ie;
-+	if (ftie->ie_len <= sizeof(pft_roam->updated_ft_ies)) {
-+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+		_rtw_memcpy(pft_roam->updated_ft_ies, ftie->ie, ftie->ie_len);
-+		pft_roam->updated_ft_ies_len = ftie->ie_len;
-+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+	} else {
-+		RTW_ERR("FTIEs parsing fail!\n");
-+		return -EINVAL;
-+	}
-+
-+	if (rtw_ft_roam_status(padapter, RTW_FT_AUTHENTICATED_STA)) {
-+		RTW_PRINT("auth success, start reassoc\n");
-+		rtw_ft_lock_set_status(padapter, RTW_FT_ASSOCIATING_STA, &irqL);
-+		start_clnt_assoc(padapter);
-+	}
-+
-+	return 0;
-+}
-+#endif
-+#endif /* CONFIG_P2P */
-+
-+inline void rtw_cfg80211_set_is_roch(_adapter *adapter, bool val)
-+{
-+	adapter->rochinfo.is_ro_ch = val;
-+	rtw_mi_update_iface_status(&(adapter->mlmepriv), 0);
-+}
-+
-+inline bool rtw_cfg80211_get_is_roch(_adapter *adapter)
-+{
-+	return adapter->rochinfo.is_ro_ch;
-+}
-+
-+inline bool rtw_cfg80211_is_ro_ch_once(_adapter *adapter)
-+{
-+	return adapter->rochinfo.last_ro_ch_time ? 1 : 0;
-+}
-+
-+inline void rtw_cfg80211_set_last_ro_ch_time(_adapter *adapter)
-+{
-+	adapter->rochinfo.last_ro_ch_time = rtw_get_current_time();
-+
-+	if (!adapter->rochinfo.last_ro_ch_time)
-+		adapter->rochinfo.last_ro_ch_time++;
-+}
-+
-+inline s32 rtw_cfg80211_get_last_ro_ch_passing_ms(_adapter *adapter)
-+{
-+	return rtw_get_passing_time_ms(adapter->rochinfo.last_ro_ch_time);
-+}
-+
-+static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	struct wireless_dev *wdev,
-+#else
-+	struct net_device *ndev,
-+#endif
-+	struct ieee80211_channel *channel,
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
-+	enum nl80211_channel_type channel_type,
-+#endif
-+	unsigned int duration, u64 *cookie)
-+{
-+	s32 err = 0;
-+	u8 remain_ch = (u8) ieee80211_frequency_to_channel(channel->center_freq);
-+	_adapter *padapter = NULL;
-+	struct rtw_wdev_priv *pwdev_priv;
-+	struct roch_info *prochinfo;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo;
-+#ifdef CONFIG_CONCURRENT_MODE
-+	u8 is_p2p_find = _FALSE;
-+#endif
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	#if defined(RTW_DEDICATED_P2P_DEVICE)
-+	if (wdev == wiphy_to_pd_wdev(wiphy))
-+		padapter = wiphy_to_adapter(wiphy);
-+	else
-+	#endif
-+	if (wdev_to_ndev(wdev))
-+		padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
-+	else {
-+		err = -EINVAL;
-+		goto exit;
-+	}
-+#else
-+	struct wireless_dev *wdev;
-+
-+	if (ndev == NULL) {
-+		err = -EINVAL;
-+		goto exit;
-+	}
-+	padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	wdev = ndev_to_wdev(ndev);
-+#endif
-+
-+	pwdev_priv = adapter_wdev_data(padapter);
-+	prochinfo = &padapter->rochinfo;
-+#ifdef CONFIG_P2P
-+	pwdinfo = &padapter->wdinfo;
-+#ifdef CONFIG_CONCURRENT_MODE
-+	is_p2p_find = (duration < (pwdinfo->ext_listen_interval)) ? _TRUE : _FALSE;
-+#endif
-+#endif
-+
-+	*cookie = ATOMIC_INC_RETURN(&prochinfo->ro_ch_cookie_gen);
-+
-+	RTW_INFO(FUNC_ADPT_FMT"%s ch:%u duration:%d, cookie:0x%llx\n"
-+		, FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : ""
-+		, remain_ch, duration, *cookie);
-+
-+	if (rtw_chset_search_ch(adapter_to_chset(padapter), remain_ch) < 0) {
-+		RTW_WARN(FUNC_ADPT_FMT" invalid ch:%u\n", FUNC_ADPT_ARG(padapter), remain_ch);
-+		err = -EFAULT;
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	if (rtw_mp_mode_check(padapter)) {
-+		RTW_INFO("MP mode block remain_on_channel request\n");
-+		err = -EFAULT;
-+		goto exit;
-+	}
-+#endif
-+
-+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
-+		err = -EFAULT;
-+		goto exit;
-+	}
-+
-+	rtw_scan_abort(padapter);
-+#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P)
-+	/*don't scan_abort during p2p_listen.*/
-+	if (is_p2p_find)
-+		rtw_mi_buddy_scan_abort(padapter, _TRUE);
-+#endif /* defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P) */
-+
-+	if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) {
-+		_cancel_timer_ex(&padapter->rochinfo.remain_on_ch_timer);
-+		rtw_cancel_roch_cmd(padapter, 0, NULL, RTW_CMDF_WAIT_ACK);
-+	}
-+
-+#ifdef CONFIG_P2P
-+	/* if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) */
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
-+		#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P)
-+		&& ((padapter->iface_id == padapter->registrypriv.sel_p2p_iface))
-+		#endif
-+	) {
-+		rtw_p2p_enable(padapter, P2P_ROLE_DEVICE);
-+		padapter->wdinfo.listen_channel = remain_ch;
-+		RTW_INFO(FUNC_ADPT_FMT" init listen_channel %u\n"
-+			, FUNC_ADPT_ARG(padapter), padapter->wdinfo.listen_channel);
-+	} else if (rtw_p2p_chk_state(pwdinfo , P2P_STATE_LISTEN)
-+		&& (time_after_eq(rtw_get_current_time(), pwdev_priv->probe_resp_ie_update_time)
-+			&& rtw_get_passing_time_ms(pwdev_priv->probe_resp_ie_update_time) < 50)
-+	) {
-+		if (padapter->wdinfo.listen_channel != remain_ch) {
-+			padapter->wdinfo.listen_channel = remain_ch;
-+			RTW_INFO(FUNC_ADPT_FMT" update listen_channel %u\n"
-+				, FUNC_ADPT_ARG(padapter), padapter->wdinfo.listen_channel);
-+		}
-+	} else {
-+		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
-+#ifdef CONFIG_DEBUG_CFG80211
-+		RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
-+#endif
-+	}
-+
-+	rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
-+#endif /* CONFIG_P2P */
-+
-+	#ifdef RTW_ROCH_DURATION_ENLARGE
-+	if (duration < 400)
-+		duration = duration * 3; /* extend from exper */
-+	#endif
-+
-+#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P)
-+	if (rtw_mi_check_status(padapter, MI_LINKED)) {
-+		if (is_p2p_find) /* p2p_find , duration<1000 */
-+			duration = duration + pwdinfo->ext_listen_interval;
-+	}
-+#endif /* defined (RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P) */
-+
-+	rtw_cfg80211_set_is_roch(padapter, _TRUE);
-+	prochinfo->ro_ch_wdev = wdev;
-+	prochinfo->remain_on_ch_cookie = *cookie;
-+	rtw_cfg80211_set_last_ro_ch_time(padapter);
-+	_rtw_memcpy(&prochinfo->remain_on_ch_channel, channel, sizeof(struct ieee80211_channel));
-+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
-+	prochinfo->remain_on_ch_type = channel_type;
-+	#endif
-+	prochinfo->restore_channel = rtw_get_oper_ch(padapter);
-+
-+	rtw_roch_cmd(padapter, *cookie, wdev, channel, prochinfo->remain_on_ch_type,
-+		duration, RTW_CMDF_WAIT_ACK);
-+
-+	rtw_cfg80211_ready_on_channel(wdev, *cookie, channel, channel_type, duration, GFP_KERNEL);
-+exit:
-+	return err;
-+}
-+
-+static s32 cfg80211_rtw_cancel_remain_on_channel(struct wiphy *wiphy,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	struct wireless_dev *wdev,
-+#else
-+	struct net_device *ndev,
-+#endif
-+	u64 cookie)
-+{
-+	s32 err = 0;
-+	_adapter *padapter;
-+	struct rtw_wdev_priv *pwdev_priv;
-+	struct roch_info *prochinfo;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo;
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	#if defined(RTW_DEDICATED_P2P_DEVICE)
-+	if (wdev == wiphy_to_pd_wdev(wiphy))
-+		padapter = wiphy_to_adapter(wiphy);
-+	else
-+	#endif
-+	if (wdev_to_ndev(wdev))
-+		padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
-+	else {
-+		err = -EINVAL;
-+		goto exit;
-+	}
-+#else
-+	struct wireless_dev *wdev;
-+
-+	if (ndev == NULL) {
-+		err = -EINVAL;
-+		goto exit;
-+	}
-+	padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	wdev = ndev_to_wdev(ndev);
-+#endif
-+
-+	pwdev_priv = adapter_wdev_data(padapter);
-+	prochinfo = &padapter->rochinfo;
-+#ifdef CONFIG_P2P
-+	pwdinfo = &padapter->wdinfo;
-+#endif
-+
-+	RTW_INFO(FUNC_ADPT_FMT"%s cookie:0x%llx\n"
-+		, FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : ""
-+		, cookie);
-+
-+	if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) {
-+		_cancel_timer_ex(&padapter->rochinfo.remain_on_ch_timer);
-+		rtw_cancel_roch_cmd(padapter, cookie, wdev, RTW_CMDF_WAIT_ACK);
-+	}
-+
-+exit:
-+	return err;
-+}
-+
-+#ifdef CONFIG_P2P
-+inline int rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter)
-+{
-+#if RTW_P2P_GROUP_INTERFACE
-+	if (is_primary_adapter(adapter))
-+		return 0;
-+#endif
-+	return 1;
-+}
-+
-+inline int rtw_cfg80211_is_p2p_scan(_adapter *adapter)
-+{
-+#if RTW_P2P_GROUP_INTERFACE
-+	if (rtw_cfg80211_iface_has_p2p_group_cap(adapter))
-+#endif
-+	{
-+		struct wifidirect_info *wdinfo = &adapter->wdinfo;
-+
-+		return rtw_p2p_chk_state(wdinfo, P2P_STATE_SCAN)
-+			|| rtw_p2p_chk_state(wdinfo, P2P_STATE_FIND_PHASE_SEARCH);
-+	}
-+
-+#if RTW_P2P_GROUP_INTERFACE
-+	#if defined(RTW_DEDICATED_P2P_DEVICE)
-+	if (wiphy_to_pd_wdev(adapter_to_wiphy(adapter))) /* pd_wdev exist */
-+		return rtw_cfg80211_is_scan_by_pd_wdev(adapter);
-+	#endif
-+	{
-+		/*
-+		* For 2 RTW_P2P_GROUP_INTERFACE cases:
-+		* 1. RTW_DEDICATED_P2P_DEVICE defined but upper layer don't use pd_wdev or
-+		* 2. RTW_DEDICATED_P2P_DEVICE not defined
-+		*/
-+		struct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter);
-+		_irqL irqL;
-+		int is_p2p_scan = 0;
-+
-+		_enter_critical_bh(&wdev_data->scan_req_lock, &irqL);
-+		if (wdev_data->scan_request
-+			&& wdev_data->scan_request->n_ssids
-+			&& wdev_data->scan_request->ssids
-+			&& wdev_data->scan_request->ie
-+		) {
-+			if (_rtw_memcmp(wdev_data->scan_request->ssids[0].ssid, "DIRECT-", 7)
-+				&& rtw_get_p2p_ie((u8 *)wdev_data->scan_request->ie, wdev_data->scan_request->ie_len, NULL, NULL))
-+				is_p2p_scan = 1;
-+		}
-+		_exit_critical_bh(&wdev_data->scan_req_lock, &irqL);
-+
-+		return is_p2p_scan;
-+	}
-+#endif
-+}
-+
-+#if defined(RTW_DEDICATED_P2P_DEVICE)
-+int rtw_pd_iface_alloc(struct wiphy *wiphy, const char *name, struct wireless_dev **pd_wdev)
-+{
-+	struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy);
-+	struct wireless_dev *wdev = NULL;
-+	struct rtw_netdev_priv_indicator *npi;
-+	_adapter *primary_adpt = wiphy_to_adapter(wiphy);
-+	int ret = 0;
-+
-+	if (wiphy_data->pd_wdev) {
-+		RTW_WARN(FUNC_WIPHY_FMT" pd_wdev already exists\n", FUNC_WIPHY_ARG(wiphy));
-+		ret = -EBUSY;
-+		goto exit;
-+	}
-+
-+	wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev));
-+	if (!wdev) {
-+		RTW_WARN(FUNC_WIPHY_FMT" allocate wdev fail\n", FUNC_WIPHY_ARG(wiphy));
-+		ret = -ENOMEM;
-+		goto exit;
-+	}
-+
-+	wdev->wiphy = wiphy;
-+	wdev->iftype = NL80211_IFTYPE_P2P_DEVICE;
-+	_rtw_memcpy(wdev->address, adapter_mac_addr(primary_adpt), ETH_ALEN);
-+
-+	wiphy_data->pd_wdev = wdev;
-+	*pd_wdev = wdev;
-+
-+	RTW_INFO(FUNC_WIPHY_FMT" pd_wdev:%p, addr="MAC_FMT" added\n"
-+		, FUNC_WIPHY_ARG(wiphy), wdev, MAC_ARG(wdev_address(wdev)));
-+
-+exit:
-+	if (ret && wdev) {
-+		rtw_mfree((u8 *)wdev, sizeof(struct wireless_dev));
-+		wdev = NULL;
-+	}
-+
-+	return ret;
-+}
-+
-+void rtw_pd_iface_free(struct wiphy *wiphy)
-+{
-+	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
-+	struct rtw_wiphy_data *wiphy_data = rtw_wiphy_priv(wiphy);
-+	u8 rtnl_lock_needed;
-+
-+	if (!wiphy_data->pd_wdev)
-+		goto exit;
-+
-+	RTW_INFO(FUNC_WIPHY_FMT" pd_wdev:%p, addr="MAC_FMT"\n"
-+		, FUNC_WIPHY_ARG(wiphy), wiphy_data->pd_wdev
-+		, MAC_ARG(wdev_address(wiphy_data->pd_wdev)));
-+
-+	rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);
-+	if (rtnl_lock_needed)
-+		rtnl_lock();
-+	cfg80211_unregister_wdev(wiphy_data->pd_wdev);
-+	if (rtnl_lock_needed)
-+		rtnl_unlock();
-+
-+	rtw_mfree((u8 *)wiphy_data->pd_wdev, sizeof(struct wireless_dev));
-+	wiphy_data->pd_wdev = NULL;
-+
-+exit:
-+	return;
-+}
-+
-+static int cfg80211_rtw_start_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev)
-+{
-+	_adapter *adapter = wiphy_to_adapter(wiphy);
-+
-+	RTW_INFO(FUNC_WIPHY_FMT" wdev=%p\n", FUNC_WIPHY_ARG(wiphy), wdev);
-+
-+	rtw_p2p_enable(adapter, P2P_ROLE_DEVICE);
-+	return 0;
-+}
-+
-+static void cfg80211_rtw_stop_p2p_device(struct wiphy *wiphy, struct wireless_dev *wdev)
-+{
-+	_adapter *adapter = wiphy_to_adapter(wiphy);
-+
-+	RTW_INFO(FUNC_WIPHY_FMT" wdev=%p\n", FUNC_WIPHY_ARG(wiphy), wdev);
-+
-+	if (rtw_cfg80211_is_p2p_scan(adapter))
-+		rtw_scan_abort(adapter);
-+
-+	rtw_p2p_enable(adapter, P2P_ROLE_DISABLE);
-+}
-+
-+inline int rtw_cfg80211_redirect_pd_wdev(struct wiphy *wiphy, u8 *ra, struct wireless_dev **wdev)
-+{
-+	struct wireless_dev *pd_wdev = wiphy_to_pd_wdev(wiphy);
-+
-+	if (pd_wdev && pd_wdev != *wdev
-+		&& _rtw_memcmp(wdev_address(pd_wdev), ra, ETH_ALEN) == _TRUE
-+	) {
-+		*wdev = pd_wdev;
-+		return 1;
-+	}
-+	return 0;
-+}
-+
-+inline int rtw_cfg80211_is_scan_by_pd_wdev(_adapter *adapter)
-+{
-+	struct wiphy *wiphy = adapter_to_wiphy(adapter);
-+	struct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter);
-+	struct wireless_dev *wdev = NULL;
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&wdev_data->scan_req_lock, &irqL);
-+	if (wdev_data->scan_request)
-+		wdev = wdev_data->scan_request->wdev;
-+	_exit_critical_bh(&wdev_data->scan_req_lock, &irqL);
-+
-+	if (wdev && wdev == wiphy_to_pd_wdev(wiphy))
-+		return 1;
-+
-+	return 0;
-+}
-+#endif /* RTW_DEDICATED_P2P_DEVICE */
-+#endif /* CONFIG_P2P */
-+
-+inline void rtw_cfg80211_set_is_mgmt_tx(_adapter *adapter, u8 val)
-+{
-+	struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);
-+
-+	wdev_priv->is_mgmt_tx = val;
-+	rtw_mi_update_iface_status(&(adapter->mlmepriv), 0);
-+}
-+
-+inline u8 rtw_cfg80211_get_is_mgmt_tx(_adapter *adapter)
-+{
-+	struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);
-+
-+	return wdev_priv->is_mgmt_tx;
-+}
-+
-+static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack)
-+{
-+	struct xmit_frame	*pmgntframe;
-+	struct pkt_attrib	*pattrib;
-+	unsigned char	*pframe;
-+	int ret = _FAIL;
-+	bool ack = _TRUE;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+#endif
-+	struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	u8 u_ch = rtw_mi_get_union_chan(padapter);
-+	u8 leave_op = 0;
-+	struct roch_info *prochinfo = &padapter->rochinfo;
-+#if defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)
-+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
-+#endif
-+
-+	rtw_cfg80211_set_is_mgmt_tx(padapter, 1);
-+
-+#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_ScanNotify(padapter, _TRUE);
-+#endif
-+
-+#ifdef CONFIG_P2P
-+	if (rtw_cfg80211_get_is_roch(padapter) == _TRUE) {
-+		#ifdef CONFIG_CONCURRENT_MODE
-+		if (!check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) {
-+			RTW_INFO("%s, extend ro ch time\n", __func__);
-+			_set_timer(&padapter->rochinfo.remain_on_ch_timer, pwdinfo->ext_listen_period);
-+		}
-+		#endif /* CONFIG_CONCURRENT_MODE */
-+	}
-+#endif /* CONFIG_P2P */
-+
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(padapter)) {
-+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
-+			/* don't set channel, issue frame directly */
-+			goto issue_mgmt_frame;
-+	}
-+#endif /* CONFIG_MCC_MODE */
-+
-+	if (rtw_mi_check_status(padapter, MI_LINKED)
-+		&& tx_ch != u_ch
-+	) {
-+		rtw_leave_opch(padapter);
-+		leave_op = 1;
-+	}
-+
-+	if (tx_ch != rtw_get_oper_ch(padapter))
-+		set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+#ifdef CONFIG_MCC_MODE
-+issue_mgmt_frame:
-+#endif
-+	/* starting alloc mgmt frame to dump it */
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL) {
-+		/* ret = -ENOMEM; */
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+	/* update attribute */
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+
-+	if (no_cck && IS_CCK_RATE(pattrib->rate)) {
-+		/* force OFDM 6M rate*/
-+		pattrib->rate = MGN_6M;
-+		pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);
-+	}
-+
-+	pattrib->retry_ctrl = _FALSE;
-+
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+
-+	_rtw_memcpy(pframe, (void *)buf, len);
-+	pattrib->pktlen = len;
-+
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+	/* update seq number */
-+	pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
-+	pattrib->seqnum = pmlmeext->mgnt_seq;
-+	pmlmeext->mgnt_seq++;
-+
-+#ifdef CONFIG_P2P
-+	rtw_xframe_chk_wfd_ie(pmgntframe);
-+#endif /* CONFIG_P2P */
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+
-+	if (wait_ack) {
-+		if (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS) {
-+			ack = _FALSE;
-+			ret = _FAIL;
-+
-+#ifdef CONFIG_DEBUG_CFG80211
-+			RTW_INFO("%s, ack == _FAIL\n", __func__);
-+#endif
-+		} else {
-+
-+#ifdef CONFIG_XMIT_ACK
-+			if (!MLME_IS_MESH(padapter)) /* TODO: remove this sleep for all mode */
-+				rtw_msleep_os(50);
-+#endif
-+#ifdef CONFIG_DEBUG_CFG80211
-+			RTW_INFO("%s, ack=%d, ok!\n", __func__, ack);
-+#endif
-+			ret = _SUCCESS;
-+		}
-+	} else {
-+		dump_mgntframe(padapter, pmgntframe);
-+		ret = _SUCCESS;
-+	}
-+
-+exit:
-+	if (rtw_cfg80211_get_is_roch(padapter)
-+		&& !rtw_roch_stay_in_cur_chan(padapter)
-+		&& prochinfo->remain_on_ch_channel.hw_value != u_ch
-+	) {
-+		/* roch is ongoing, switch back to rch */
-+		if (prochinfo->remain_on_ch_channel.hw_value != tx_ch)
-+			set_channel_bwmode(padapter, prochinfo->remain_on_ch_channel.hw_value
-+				, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+	} else if (leave_op) {
-+		if (rtw_mi_check_status(padapter, MI_LINKED)) {
-+			u8 u_bw = rtw_mi_get_union_bw(padapter);
-+			u8 u_offset = rtw_mi_get_union_offset(padapter);
-+
-+			set_channel_bwmode(padapter, u_ch, u_offset, u_bw);
-+		}
-+		rtw_back_opch(padapter);
-+	}
-+
-+	rtw_cfg80211_set_is_mgmt_tx(padapter, 0);
-+
-+#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_ScanNotify(padapter, _FALSE);
-+#endif
-+
-+#ifdef CONFIG_DEBUG_CFG80211
-+	RTW_INFO("%s, ret=%d\n", __func__, ret);
-+#endif
-+
-+	return ret;
-+
-+}
-+
-+u8 rtw_mgnt_tx_handler(_adapter *adapter, u8 *buf)
-+{
-+	u8 rst = H2C_CMD_FAIL;
-+	struct mgnt_tx_parm *mgnt_parm = (struct mgnt_tx_parm *)buf;
-+
-+	if (_cfg80211_rtw_mgmt_tx(adapter, mgnt_parm->tx_ch, mgnt_parm->no_cck,
-+		mgnt_parm->buf, mgnt_parm->len, mgnt_parm->wait_ack) == _SUCCESS)
-+		rst = H2C_SUCCESS;
-+
-+	return rst;
-+}
-+
-+static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	struct wireless_dev *wdev,
-+#else
-+	struct net_device *ndev,
-+#endif
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) || defined(COMPAT_KERNEL_RELEASE)
-+	struct ieee80211_channel *chan,
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
-+	bool offchan,
-+	#endif
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
-+	enum nl80211_channel_type channel_type,
-+	#endif
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
-+	bool channel_type_valid,
-+	#endif
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
-+	unsigned int wait,
-+	#endif
-+	const u8 *buf, size_t len,
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
-+	bool no_cck,
-+	#endif
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
-+	bool dont_wait_for_ack,
-+	#endif
-+#else
-+	struct cfg80211_mgmt_tx_params *params,
-+#endif
-+	u64 *cookie)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(COMPAT_KERNEL_RELEASE)
-+	struct ieee80211_channel *chan = params->chan;
-+	const u8 *buf = params->buf;
-+	size_t len = params->len;
-+	bool no_cck = params->no_cck;
-+#endif
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0))
-+	bool no_cck = 0;
-+#endif
-+	int ret = 0;
-+	u8 tx_ret;
-+	int wait_ack = 1;
-+	const u8 *dump_buf = buf;
-+	size_t dump_len = len;
-+	u32 dump_limit = RTW_MAX_MGMT_TX_CNT;
-+	u32 dump_cnt = 0;
-+	u32 sleep_ms = 0;
-+	u32 retry_guarantee_ms = 0;
-+	bool ack = _TRUE;
-+	u8 tx_ch;
-+	u8 category, action;
-+	u8 frame_styp;
-+#ifdef CONFIG_P2P
-+	u8 is_p2p = 0;
-+#endif
-+	int type = (-1);
-+	systime start = rtw_get_current_time();
-+	_adapter *padapter;
-+	struct dvobj_priv *dvobj;
-+	struct rtw_wdev_priv *pwdev_priv;
-+	struct rf_ctl_t *rfctl;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	#if defined(RTW_DEDICATED_P2P_DEVICE)
-+	if (wdev == wiphy_to_pd_wdev(wiphy))
-+		padapter = wiphy_to_adapter(wiphy);
-+	else
-+	#endif
-+	if (wdev_to_ndev(wdev))
-+		padapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
-+	else {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+#else
-+	struct wireless_dev *wdev;
-+
-+	if (ndev == NULL) {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+	padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	wdev = ndev_to_wdev(ndev);
-+#endif
-+
-+	if (chan == NULL) {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	rfctl = adapter_to_rfctl(padapter);
-+	tx_ch = (u8)ieee80211_frequency_to_channel(chan->center_freq);
-+	if (IS_CH_WAITING(rfctl)) {
-+		#ifdef CONFIG_DFS_MASTER
-+		if (_rtw_rfctl_overlap_radar_detect_ch(rfctl, tx_ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE)) {
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+		#endif
-+	}
-+
-+	dvobj = adapter_to_dvobj(padapter);
-+	pwdev_priv = adapter_wdev_data(padapter);
-+
-+	/* cookie generation */
-+	*cookie = pwdev_priv->mgmt_tx_cookie++;
-+
-+#ifdef CONFIG_DEBUG_CFG80211
-+	RTW_INFO(FUNC_ADPT_FMT"%s len=%zu, ch=%d"
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
-+		", ch_type=%d"
-+		#endif
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
-+		", channel_type_valid=%d"
-+		#endif
-+		"\n", FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : ""
-+		, len, tx_ch
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
-+		, channel_type
-+		#endif
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
-+		, channel_type_valid
-+		#endif
-+	);
-+#endif /* CONFIG_DEBUG_CFG80211 */
-+
-+	/* indicate ack before issue frame to avoid racing with rsp frame */
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+	rtw_cfg80211_mgmt_tx_status(wdev, *cookie, buf, len, ack, GFP_KERNEL);
-+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 36))
-+	cfg80211_action_tx_status(ndev, *cookie, buf, len, ack, GFP_KERNEL);
-+#endif
-+
-+	frame_styp = le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl) & IEEE80211_FCTL_STYPE;
-+	if (IEEE80211_STYPE_PROBE_RESP == frame_styp) {
-+#ifdef CONFIG_DEBUG_CFG80211
-+		RTW_INFO("RTW_Tx: probe_resp tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf)));
-+#endif /* CONFIG_DEBUG_CFG80211 */
-+		wait_ack = 0;
-+		goto dump;
-+	}
-+	else if (frame_styp == RTW_IEEE80211_STYPE_AUTH) {
-+		int retval = 0;
-+
-+		RTW_INFO("RTW_Tx:tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf)));
-+
-+		retval = rtw_sae_preprocess(padapter, buf, len, _TRUE);
-+		if (retval == 2)
-+			goto exit;
-+		if (retval == 0)
-+			RTW_INFO("RTW_Tx:AUTH\n");
-+		dump_limit = 1;
-+		goto dump;
-+	}
-+
-+	if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) {
-+		RTW_INFO(FUNC_ADPT_FMT" frame_control:0x%02x\n", FUNC_ADPT_ARG(padapter),
-+			le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl));
-+		goto exit;
-+	}
-+
-+	RTW_INFO("RTW_Tx:tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf)));
-+#ifdef CONFIG_P2P
-+	type = rtw_p2p_check_frames(padapter, buf, len, _TRUE);
-+	if (type >= 0) {
-+		is_p2p = 1;
-+		no_cck = 1; /* force no CCK for P2P frames */
-+		goto dump;
-+	}
-+#endif
-+#ifdef CONFIG_RTW_MESH
-+	if (MLME_IS_MESH(padapter)) {
-+		type = rtw_mesh_check_frames_tx(padapter, &dump_buf, &dump_len);
-+		if (type >= 0) {
-+			dump_limit = 1;
-+			goto dump;
-+		}
-+	}
-+#endif
-+	if (category == RTW_WLAN_CATEGORY_PUBLIC) {
-+		RTW_INFO("RTW_Tx:%s\n", action_public_str(action));
-+		switch (action) {
-+		case ACT_PUBLIC_GAS_INITIAL_REQ:
-+		case ACT_PUBLIC_GAS_INITIAL_RSP:
-+			sleep_ms = 50;
-+			retry_guarantee_ms = RTW_MAX_MGMT_TX_MS_GAS;
-+			break;
-+		}
-+	}
-+#ifdef CONFIG_RTW_80211K
-+	else if (category == RTW_WLAN_CATEGORY_RADIO_MEAS)
-+		RTW_INFO("RTW_Tx: RRM Action\n");
-+#endif
-+	else
-+		RTW_INFO("RTW_Tx:category(%u), action(%u)\n", category, action);
-+
-+dump:
-+
-+	rtw_ps_deny(padapter, PS_DENY_MGNT_TX);
-+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
-+		ret = -EFAULT;
-+		goto cancel_ps_deny;
-+	}
-+
-+	while (1) {
-+		dump_cnt++;
-+
-+		rtw_mi_set_scan_deny(padapter, 1000);
-+		rtw_mi_scan_abort(padapter, _TRUE);
-+		tx_ret = rtw_mgnt_tx_cmd(padapter, tx_ch, no_cck, dump_buf, dump_len, wait_ack, RTW_CMDF_WAIT_ACK);
-+		if (tx_ret == _SUCCESS
-+			|| (dump_cnt >= dump_limit && rtw_get_passing_time_ms(start) >= retry_guarantee_ms))
-+			break;
-+
-+		if (sleep_ms > 0)
-+			rtw_msleep_os(sleep_ms);
-+	}
-+
-+	if (tx_ret != _SUCCESS || dump_cnt > 1) {
-+		RTW_INFO(FUNC_ADPT_FMT" %s (%d/%d) in %d ms\n", FUNC_ADPT_ARG(padapter),
-+			tx_ret == _SUCCESS ? "OK" : "FAIL", dump_cnt, dump_limit, rtw_get_passing_time_ms(start));
-+	}
-+
-+#ifdef CONFIG_P2P
-+	if (is_p2p) {
-+		switch (type) {
-+		case P2P_GO_NEGO_CONF:
-+			if (0) {
-+				RTW_INFO(FUNC_ADPT_FMT" Nego confirm. state=%u, status=%u, iaddr="MAC_FMT"\n"
-+					, FUNC_ADPT_ARG(padapter), pwdev_priv->nego_info.state, pwdev_priv->nego_info.status
-+					, MAC_ARG(pwdev_priv->nego_info.iface_addr));
-+			}
-+			if (pwdev_priv->nego_info.state == 2
-+				&& pwdev_priv->nego_info.status == 0
-+				&& rtw_check_invalid_mac_address(pwdev_priv->nego_info.iface_addr, _FALSE) == _FALSE
-+			) {
-+				_adapter *intended_iface = dvobj_get_adapter_by_addr(dvobj, pwdev_priv->nego_info.iface_addr);
-+
-+				if (intended_iface) {
-+					RTW_INFO(FUNC_ADPT_FMT" Nego confirm. Allow only "ADPT_FMT" to scan for 2000 ms\n"
-+						, FUNC_ADPT_ARG(padapter), ADPT_ARG(intended_iface));
-+					/* allow only intended_iface to do scan for 2000 ms */
-+					rtw_mi_set_scan_deny(padapter, 2000);
-+					rtw_clear_scan_deny(intended_iface);
-+				}
-+			}
-+			break;
-+		case P2P_INVIT_RESP:
-+			if (pwdev_priv->invit_info.flags & BIT(0)
-+				&& pwdev_priv->invit_info.status == 0
-+			) {
-+				rtw_clear_scan_deny(padapter);
-+				RTW_INFO(FUNC_ADPT_FMT" agree with invitation of persistent group\n",
-+					FUNC_ADPT_ARG(padapter));
-+				#if !RTW_P2P_GROUP_INTERFACE
-+				rtw_mi_buddy_set_scan_deny(padapter, 5000);
-+				#endif
-+				rtw_pwr_wakeup_ex(padapter, 5000);
-+			}
-+			break;
-+		}
-+	}
-+#endif /* CONFIG_P2P */
-+
-+cancel_ps_deny:
-+	rtw_ps_deny_cancel(padapter, PS_DENY_MGNT_TX);
-+
-+	if (dump_buf != buf)
-+		rtw_mfree((u8 *)dump_buf, dump_len);
-+exit:
-+	return ret;
-+}
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))
-+static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	struct wireless_dev *wdev,
-+#else
-+	struct net_device *ndev,
-+#endif
-+	u16 frame_type, bool reg)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	struct net_device *ndev = wdev_to_ndev(wdev);
-+#endif
-+	_adapter *adapter;
-+	struct rtw_wdev_priv *pwdev_priv;
-+
-+	if (ndev == NULL)
-+		goto exit;
-+
-+	adapter = (_adapter *)rtw_netdev_priv(ndev);
-+	pwdev_priv = adapter_wdev_data(adapter);
-+
-+#ifdef CONFIG_DEBUG_CFG80211
-+	RTW_INFO(FUNC_ADPT_FMT" frame_type:%x, reg:%d\n", FUNC_ADPT_ARG(adapter),
-+		frame_type, reg);
-+#endif
-+
-+	switch (frame_type) {
-+	case IEEE80211_STYPE_AUTH: /* 0x00B0 */
-+		if (reg > 0)
-+			SET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_AUTH);
-+		else
-+			CLR_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_AUTH);
-+		break;
-+#ifdef not_yet
-+	case IEEE80211_STYPE_PROBE_REQ: /* 0x0040 */
-+		if (reg > 0)
-+			SET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_PROBE_REQ);
-+		else
-+			CLR_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_PROBE_REQ);
-+		break;
-+	case IEEE80211_STYPE_ACTION: /* 0x00D0 */
-+		if (reg > 0)
-+			SET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_ACTION);
-+		else
-+			CLR_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_ACTION);
-+		break;
-+#endif
-+	default:
-+		break;
-+	}
-+
-+exit:
-+	return;
-+}
-+#else
-+static void cfg80211_rtw_update_mgmt_frame_register(
-+	struct wiphy *wiphy,
-+	struct wireless_dev *wdev,
-+	struct mgmt_frame_regs *upd)
-+{
-+	struct net_device *ndev;
-+	_adapter *padapter;
-+	struct rtw_wdev_priv *pwdev_priv;
-+	u32 rtw_stypes_mask = 0;
-+	u32 rtw_mstypes_mask = 0;
-+
-+	ndev = wdev_to_ndev(wdev);
-+
-+	if (ndev == NULL)
-+		goto exit;
-+
-+	padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	pwdev_priv = adapter_wdev_data(padapter);
-+
-+	rtw_stypes_mask = BIT(IEEE80211_STYPE_AUTH >> 4);
-+
-+#ifdef CONFIG_DEBUG_CFG80211
-+	RTW_INFO(FUNC_ADPT_FMT " global_stypes:0x%08x interface_stypes:0x%08x\n",
-+		FUNC_ADPT_ARG(padapter), upd->global_stypes, upd->interface_stypes);
-+	RTW_INFO(FUNC_ADPT_FMT " global_mcast_stypes:0x%08x interface_mcast_stypes:0x%08x\n",
-+		FUNC_ADPT_ARG(padapter), upd->global_mcast_stypes, upd->interface_mcast_stypes);
-+	RTW_INFO(FUNC_ADPT_FMT " old_regs:0x%08x new_regs:0x%08x\n",
-+		FUNC_ADPT_ARG(padapter), pwdev_priv->mgmt_regs,
-+		(upd->interface_stypes & rtw_stypes_mask));
-+#endif
-+	if (pwdev_priv->mgmt_regs !=
-+			(upd->interface_stypes & rtw_stypes_mask)) {
-+		pwdev_priv->mgmt_regs = (upd->interface_stypes & rtw_stypes_mask);
-+	}
-+
-+exit:
-+	return;
-+}
-+#endif
-+
-+#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
-+static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy,
-+	struct net_device *ndev,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
-+	const u8 *peer,
-+#else
-+	u8 *peer,
-+#endif
-+	u8 action_code,
-+	u8 dialog_token,
-+	u16 status_code,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0))
-+	u32 peer_capability,
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0))
-+	bool initiator,
-+#endif
-+	const u8 *buf,
-+	size_t len)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &pmlmeext->mlmext_info;
-+	int ret = 0;
-+	struct tdls_txmgmt txmgmt;
-+
-+	if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {
-+		RTW_INFO("Discard tdls action:%d, since hal doesn't support tdls\n", action_code);
-+		goto discard;
-+	}
-+
-+	if (rtw_is_tdls_enabled(padapter) == _FALSE) {
-+		RTW_INFO("TDLS is not enabled\n");
-+		goto discard;
-+	}
-+
-+	if (rtw_tdls_is_driver_setup(padapter)) {
-+		RTW_INFO("Discard tdls action:%d, let driver to set up direct link\n", action_code);
-+		goto discard;
-+	}
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	_rtw_memcpy(txmgmt.peer, peer, ETH_ALEN);
-+	txmgmt.action_code = action_code;
-+	txmgmt.dialog_token = dialog_token;
-+	txmgmt.status_code = status_code;
-+	txmgmt.len = len;
-+	txmgmt.buf = (u8 *)rtw_malloc(txmgmt.len);
-+	if (txmgmt.buf == NULL) {
-+		ret = -ENOMEM;
-+		goto bad;
-+	}
-+	_rtw_memcpy(txmgmt.buf, (void *)buf, txmgmt.len);
-+
-+	/* Debug purpose */
-+#if 1
-+	RTW_INFO("%s %d\n", __FUNCTION__, __LINE__);
-+	RTW_INFO("peer:"MAC_FMT", action code:%d, dialog:%d, status code:%d\n",
-+		MAC_ARG(txmgmt.peer), txmgmt.action_code,
-+		txmgmt.dialog_token, txmgmt.status_code);
-+	if (txmgmt.len > 0) {
-+		int i = 0;
-+		for (; i < len; i++)
-+			printk("%02x ", *(txmgmt.buf + i));
-+		RTW_INFO("len:%d\n", (u32)txmgmt.len);
-+	}
-+#endif
-+
-+	switch (txmgmt.action_code) {
-+	case TDLS_SETUP_REQUEST:
-+		issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
-+		break;
-+	case TDLS_SETUP_RESPONSE:
-+		issue_tdls_setup_rsp(padapter, &txmgmt);
-+		break;
-+	case TDLS_SETUP_CONFIRM:
-+		issue_tdls_setup_cfm(padapter, &txmgmt);
-+		break;
-+	case TDLS_TEARDOWN:
-+		issue_tdls_teardown(padapter, &txmgmt, _TRUE);
-+		break;
-+	case TDLS_DISCOVERY_REQUEST:
-+		issue_tdls_dis_req(padapter, &txmgmt);
-+		break;
-+	case TDLS_DISCOVERY_RESPONSE:
-+		issue_tdls_dis_rsp(padapter, &txmgmt, pmlmeinfo->enc_algo ? _TRUE : _FALSE);
-+		break;
-+	}
-+
-+bad:
-+	if (txmgmt.buf)
-+		rtw_mfree(txmgmt.buf, txmgmt.len);
-+
-+discard:
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_tdls_oper(struct wiphy *wiphy,
-+	struct net_device *ndev,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
-+	const u8 *peer,
-+#else
-+	u8 *peer,
-+#endif
-+	enum nl80211_tdls_operation oper)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	struct tdls_txmgmt	txmgmt;
-+	struct sta_info *ptdls_sta = NULL;
-+
-+	RTW_INFO(FUNC_NDEV_FMT", nl80211_tdls_operation:%d\n", FUNC_NDEV_ARG(ndev), oper);
-+
-+	if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {
-+		RTW_INFO("Discard tdls oper:%d, since hal doesn't support tdls\n", oper);
-+		return 0;
-+	}
-+
-+	if (rtw_is_tdls_enabled(padapter) == _FALSE) {
-+		RTW_INFO("TDLS is not enabled\n");
-+		return 0;
-+	}
-+
-+#ifdef CONFIG_LPS
-+	rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 0);
-+#endif /* CONFIG_LPS */
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	if (peer)
-+		_rtw_memcpy(txmgmt.peer, peer, ETH_ALEN);
-+
-+	if (rtw_tdls_is_driver_setup(padapter)) {
-+		/* these two cases are done by driver itself */
-+		if (oper == NL80211_TDLS_ENABLE_LINK || oper == NL80211_TDLS_DISABLE_LINK)
-+			return 0;
-+	}
-+
-+	switch (oper) {
-+	case NL80211_TDLS_DISCOVERY_REQ:
-+		issue_tdls_dis_req(padapter, &txmgmt);
-+		break;
-+	case NL80211_TDLS_SETUP:
-+#ifdef CONFIG_WFD
-+		if (_AES_ != padapter->securitypriv.dot11PrivacyAlgrthm) {
-+			if (padapter->wdinfo.wfd_tdls_weaksec == _TRUE)
-+				issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
-+			else
-+				RTW_INFO("[%s] Current link is not AES, SKIP sending the tdls setup request!!\n", __FUNCTION__);
-+		} else
-+#endif /* CONFIG_WFD */
-+		{
-+			issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
-+		}
-+		break;
-+	case NL80211_TDLS_TEARDOWN:
-+		ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), txmgmt.peer);
-+		if (ptdls_sta != NULL) {
-+			txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;
-+			issue_tdls_teardown(padapter, &txmgmt, _TRUE);
-+		} else
-+			RTW_INFO("TDLS peer not found\n");
-+		break;
-+	case NL80211_TDLS_ENABLE_LINK:
-+		RTW_INFO(FUNC_NDEV_FMT", NL80211_TDLS_ENABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer));
-+		ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer);
-+		if (ptdls_sta != NULL) {
-+			rtw_tdls_set_link_established(padapter, _TRUE);
-+			ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;
-+			ptdls_sta->state |= WIFI_ASOC_STATE;
-+			rtw_tdls_cmd(padapter, txmgmt.peer, TDLS_ESTABLISHED);
-+		}
-+		break;
-+	case NL80211_TDLS_DISABLE_LINK:
-+		RTW_INFO(FUNC_NDEV_FMT", NL80211_TDLS_DISABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer));
-+		ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer);
-+		if (ptdls_sta != NULL) {
-+			rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
-+			rtw_tdls_cmd(padapter, (u8 *)peer, TDLS_TEARDOWN_STA_LOCALLY_POST);
-+		}
-+		break;
-+	}
-+	return 0;
-+}
-+#endif /* CONFIG_TDLS */
-+
-+#if defined(CONFIG_RTW_MESH) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
-+
-+#if DBG_RTW_CFG80211_MESH_CONF
-+#define LEGACY_RATES_STR_LEN (RTW_G_RATES_NUM * 5 + 1)
-+int get_legacy_rates_str(struct wiphy *wiphy, enum nl80211_band band, u32 mask, char *buf)
-+{
-+	int i;
-+	int cnt = 0;
-+
-+	for (i = 0; i < wiphy->bands[band]->n_bitrates; i++) {
-+		if (mask & BIT(i)) {
-+			cnt += snprintf(buf + cnt, LEGACY_RATES_STR_LEN - cnt -1, "%d.%d "
-+				, wiphy->bands[band]->bitrates[i].bitrate / 10
-+				, wiphy->bands[band]->bitrates[i].bitrate % 10);
-+			if (cnt >= LEGACY_RATES_STR_LEN - 1)
-+				break;
-+		}
-+	}
-+
-+	return cnt;
-+}
-+
-+void dump_mesh_setup(void *sel, struct wiphy *wiphy, const struct mesh_setup *setup)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	struct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef);
-+#endif
-+	struct ieee80211_channel *chan;
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	chan = (struct ieee80211_channel *)chdef->chan;
-+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	chan = (struct ieee80211_channel *)setup->channel;
-+#endif
-+
-+	RTW_PRINT_SEL(sel, "mesh_id:\"%s\", len:%u\n", setup->mesh_id, setup->mesh_id_len);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
-+	RTW_PRINT_SEL(sel, "sync_method:%u\n", setup->sync_method);
-+#endif
-+	RTW_PRINT_SEL(sel, "path_sel_proto:%u, path_metric:%u\n", setup->path_sel_proto, setup->path_metric);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+	RTW_PRINT_SEL(sel, "auth_id:%u\n", setup->auth_id);
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+	if (setup->ie && setup->ie_len) {
-+		RTW_PRINT_SEL(sel, "ie:%p, len:%u\n", setup->ie, setup->ie_len);
-+		dump_ies(RTW_DBGDUMP, setup->ie, setup->ie_len);
-+	}
-+#else
-+	if (setup->vendor_ie && setup->vendor_ie_len) {
-+		RTW_PRINT_SEL(sel, "ie:%p, len:%u\n", setup->vendor_ie, setup->vendor_ie_len);
-+		dump_ies(RTW_DBGDUMP, setup->vendor_ie, setup->vendor_ie_len);
-+	}
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+	RTW_PRINT_SEL(sel, "is_authenticated:%d, is_secure:%d\n", setup->is_authenticated, setup->is_secure);
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
-+	RTW_PRINT_SEL(sel, "user_mpm:%d\n", setup->user_mpm);
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
-+	RTW_PRINT_SEL(sel, "dtim_period:%u, beacon_interval:%u\n", setup->dtim_period, setup->beacon_interval);
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	RTW_PRINT_SEL(sel, "center_freq:%u, ch:%u, width:%s, cfreq1:%u, cfreq2:%u\n"
-+		, chan->center_freq, chan->hw_value, nl80211_chan_width_str(chdef->width), chdef->center_freq1, chdef->center_freq2);
-+#else
-+	RTW_PRINT_SEL(sel, "center_freq:%u, ch:%u, channel_type:%s\n"
-+		, chan->center_freq, chan->hw_value, nl80211_channel_type_str(setup->channel_type));
-+#endif
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
-+	if (setup->mcast_rate[chan->band]) {
-+		RTW_PRINT_SEL(sel, "mcast_rate:%d.%d\n"
-+			, wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate / 10
-+			, wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate % 10
-+		);
-+	}
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+	if (setup->basic_rates) {
-+		char buf[LEGACY_RATES_STR_LEN] = {0};
-+
-+		get_legacy_rates_str(wiphy, chan->band, setup->basic_rates, buf);
-+		RTW_PRINT_SEL(sel, "basic_rates:%s\n", buf);
-+	}
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0))
-+	if (setup->beacon_rate.control[chan->band].legacy) {
-+		char buf[LEGACY_RATES_STR_LEN] = {0};
-+
-+		get_legacy_rates_str(wiphy, chan->band, setup->beacon_rate.control[chan->band].legacy, buf);
-+		RTW_PRINT_SEL(sel, "beacon_rate.legacy:%s\n", buf);
-+	}
-+	if (*((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[0]))
-+		|| *((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[4]))
-+		|| *((u16 *)&(setup->beacon_rate.control[chan->band].ht_mcs[8]))
-+	) {
-+		RTW_PRINT_SEL(sel, "beacon_rate.ht_mcs:"HT_RX_MCS_BMP_FMT"\n"
-+			, HT_RX_MCS_BMP_ARG(setup->beacon_rate.control[chan->band].ht_mcs));
-+	}
-+
-+	if (setup->beacon_rate.control[chan->band].vht_mcs[0]
-+		|| setup->beacon_rate.control[chan->band].vht_mcs[1]
-+		|| setup->beacon_rate.control[chan->band].vht_mcs[2]
-+		|| setup->beacon_rate.control[chan->band].vht_mcs[3]
-+	) {
-+		int i;
-+
-+		for (i = 0; i < 4; i++) {/* parsing up to 4SS */
-+			u16 mcs_mask = setup->beacon_rate.control[chan->band].vht_mcs[i];
-+
-+			RTW_PRINT_SEL(sel, "beacon_rate.vht_mcs[%d]:%s\n", i
-+				, mcs_mask == 0x00FF ? "0~7" : mcs_mask == 0x01FF ? "0~8" : mcs_mask == 0x03FF ? "0~9" : "invalid");
-+		}
-+	}
-+
-+	if (setup->beacon_rate.control[chan->band].gi) {
-+		RTW_PRINT_SEL(sel, "beacon_rate.gi:%s\n"
-+			, setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_SGI ? "SGI" :
-+				setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_LGI ? "LGI" : "invalid"
-+		);
-+	}
-+#endif
-+}
-+
-+void dump_mesh_config(void *sel, const struct mesh_config *conf)
-+{
-+	RTW_PRINT_SEL(sel, "dot11MeshRetryTimeout:%u\n", conf->dot11MeshRetryTimeout);
-+	RTW_PRINT_SEL(sel, "dot11MeshConfirmTimeout:%u\n", conf->dot11MeshConfirmTimeout);
-+	RTW_PRINT_SEL(sel, "dot11MeshHoldingTimeout:%u\n", conf->dot11MeshHoldingTimeout);
-+	RTW_PRINT_SEL(sel, "dot11MeshMaxPeerLinks:%u\n", conf->dot11MeshMaxPeerLinks);
-+	RTW_PRINT_SEL(sel, "dot11MeshMaxRetries:%u\n", conf->dot11MeshMaxRetries);
-+	RTW_PRINT_SEL(sel, "dot11MeshTTL:%u\n", conf->dot11MeshTTL);
-+	RTW_PRINT_SEL(sel, "element_ttl:%u\n", conf->element_ttl);
-+	RTW_PRINT_SEL(sel, "auto_open_plinks:%d\n", conf->auto_open_plinks);
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
-+	RTW_PRINT_SEL(sel, "dot11MeshNbrOffsetMaxNeighbor:%u\n", conf->dot11MeshNbrOffsetMaxNeighbor);
-+#endif
-+
-+	RTW_PRINT_SEL(sel, "dot11MeshHWMPmaxPREQretries:%u\n", conf->dot11MeshHWMPmaxPREQretries);
-+	RTW_PRINT_SEL(sel, "path_refresh_time:%u\n", conf->path_refresh_time);
-+	RTW_PRINT_SEL(sel, "min_discovery_timeout:%u\n", conf->min_discovery_timeout);
-+	RTW_PRINT_SEL(sel, "dot11MeshHWMPactivePathTimeout:%u\n", conf->dot11MeshHWMPactivePathTimeout);
-+	RTW_PRINT_SEL(sel, "dot11MeshHWMPpreqMinInterval:%u\n", conf->dot11MeshHWMPpreqMinInterval);	
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
-+	RTW_PRINT_SEL(sel, "dot11MeshHWMPperrMinInterval:%u\n", conf->dot11MeshHWMPperrMinInterval);
-+#endif
-+	RTW_PRINT_SEL(sel, "dot11MeshHWMPnetDiameterTraversalTime:%u\n", conf->dot11MeshHWMPnetDiameterTraversalTime);
-+	RTW_PRINT_SEL(sel, "dot11MeshHWMPRootMode:%u\n", conf->dot11MeshHWMPRootMode);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
-+	RTW_PRINT_SEL(sel, "dot11MeshHWMPRannInterval:%u\n", conf->dot11MeshHWMPRannInterval);
-+	RTW_PRINT_SEL(sel, "dot11MeshGateAnnouncementProtocol:%d\n", conf->dot11MeshGateAnnouncementProtocol);
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
-+	RTW_PRINT_SEL(sel, "dot11MeshForwarding:%d\n", conf->dot11MeshForwarding);
-+	RTW_PRINT_SEL(sel, "rssi_threshold:%d\n", conf->rssi_threshold);
-+#endif
-+	
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
-+	RTW_PRINT_SEL(sel, "ht_opmode:0x%04x\n", conf->ht_opmode);
-+#endif
-+	
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	RTW_PRINT_SEL(sel, "dot11MeshHWMPactivePathToRootTimeout:%u\n", conf->dot11MeshHWMPactivePathToRootTimeout);
-+	RTW_PRINT_SEL(sel, "dot11MeshHWMProotInterval:%u\n", conf->dot11MeshHWMProotInterval);
-+	RTW_PRINT_SEL(sel, "dot11MeshHWMPconfirmationInterval:%u\n", conf->dot11MeshHWMPconfirmationInterval);
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
-+	RTW_PRINT_SEL(sel, "power_mode:%s\n", nl80211_mesh_power_mode_str(conf->power_mode));
-+	RTW_PRINT_SEL(sel, "dot11MeshAwakeWindowDuration:%u\n", conf->dot11MeshAwakeWindowDuration);
-+#endif
-+	
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+	RTW_PRINT_SEL(sel, "plink_timeout:%u\n", conf->plink_timeout);
-+#endif
-+}
-+#endif /* DBG_RTW_CFG80211_MESH_CONF */
-+
-+static void rtw_cfg80211_mesh_info_set_profile(struct rtw_mesh_info *minfo, const struct mesh_setup *setup)
-+{
-+	_rtw_memcpy(minfo->mesh_id, setup->mesh_id, setup->mesh_id_len);
-+	minfo->mesh_id_len = setup->mesh_id_len;
-+	minfo->mesh_pp_id = setup->path_sel_proto;
-+	minfo->mesh_pm_id = setup->path_metric;
-+	minfo->mesh_cc_id = 0;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
-+	minfo->mesh_sp_id = setup->sync_method;
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+	minfo->mesh_auth_id = setup->auth_id;
-+#else
-+	if (setup->is_authenticated) {
-+		u8 *rsn_ie;
-+		sint rsn_ie_len;
-+		struct rsne_info info;
-+		u8 *akm;
-+		u8 AKM_SUITE_SAE[4] = {0x00, 0x0F, 0xAC, 0x08};
-+
-+		rsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len);
-+		if (!rsn_ie || !rsn_ie_len) {
-+			rtw_warn_on(1);
-+			return;
-+		}
-+
-+		if (rtw_rsne_info_parse(rsn_ie, rsn_ie_len + 2, &info) != _SUCCESS) {
-+			rtw_warn_on(1);
-+			return;
-+		}
-+
-+		if (!info.akm_list || !info.akm_cnt) {
-+			rtw_warn_on(1);
-+			return;
-+		}
-+
-+		akm = info.akm_list;
-+		while (akm < info.akm_list + info.akm_cnt * 4) {
-+			if (_rtw_memcmp(akm, AKM_SUITE_SAE, 4) == _TRUE) {
-+				minfo->mesh_auth_id = 0x01;
-+				break;
-+			}
-+		}
-+
-+		if (!minfo->mesh_auth_id) {
-+			rtw_warn_on(1);
-+			return;
-+		}
-+	}
-+#endif
-+}
-+
-+static inline bool chk_mesh_attr(enum nl80211_meshconf_params parm, u32 mask)
-+{
-+	return (mask >> (parm - 1)) & 0x1;
-+}
-+
-+static void rtw_cfg80211_mesh_cfg_set(_adapter *adapter, const struct mesh_config *conf, u32 mask)
-+{
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+
-+#if 0 /* driver MPM */
-+	if (chk_mesh_attr(NL80211_MESHCONF_RETRY_TIMEOUT, mask));
-+	if (chk_mesh_attr(NL80211_MESHCONF_CONFIRM_TIMEOUT, mask));
-+	if (chk_mesh_attr(NL80211_MESHCONF_HOLDING_TIMEOUT, mask));
-+	if (chk_mesh_attr(NL80211_MESHCONF_MAX_PEER_LINKS, mask));
-+	if (chk_mesh_attr(NL80211_MESHCONF_MAX_RETRIES, mask));
-+#endif
-+
-+	if (chk_mesh_attr(NL80211_MESHCONF_TTL, mask))
-+		mcfg->dot11MeshTTL = conf->dot11MeshTTL;
-+	if (chk_mesh_attr(NL80211_MESHCONF_ELEMENT_TTL, mask))
-+		mcfg->element_ttl = conf->element_ttl;
-+
-+#if 0 /* driver MPM */
-+	if (chk_mesh_attr(NL80211_MESHCONF_AUTO_OPEN_PLINKS, mask));
-+#endif
-+
-+#if 0 /* TBD: synchronization */
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
-+	if (chk_mesh_attr(NL80211_MESHCONF_SYNC_OFFSET_MAX_NEIGHBOR, mask));
-+#endif
-+#endif
-+
-+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES, mask))
-+		mcfg->dot11MeshHWMPmaxPREQretries = conf->dot11MeshHWMPmaxPREQretries;
-+	if (chk_mesh_attr(NL80211_MESHCONF_PATH_REFRESH_TIME, mask))
-+		mcfg->path_refresh_time = conf->path_refresh_time;
-+	if (chk_mesh_attr(NL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT, mask))
-+		mcfg->min_discovery_timeout = conf->min_discovery_timeout;
-+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT, mask))
-+		mcfg->dot11MeshHWMPactivePathTimeout = conf->dot11MeshHWMPactivePathTimeout;
-+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL, mask))
-+		mcfg->dot11MeshHWMPpreqMinInterval = conf->dot11MeshHWMPpreqMinInterval;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
-+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PERR_MIN_INTERVAL, mask))
-+		mcfg->dot11MeshHWMPperrMinInterval = conf->dot11MeshHWMPperrMinInterval;
-+#endif
-+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME, mask))
-+		mcfg->dot11MeshHWMPnetDiameterTraversalTime = conf->dot11MeshHWMPnetDiameterTraversalTime;
-+
-+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOTMODE, mask))
-+		mcfg->dot11MeshHWMPRootMode = conf->dot11MeshHWMPRootMode;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
-+	if (chk_mesh_attr(NL80211_MESHCONF_GATE_ANNOUNCEMENTS, mask))
-+		mcfg->dot11MeshGateAnnouncementProtocol = conf->dot11MeshGateAnnouncementProtocol;
-+	/* our current gate annc implementation rides on root annc with gate annc bit in PREQ flags */
-+	if (mcfg->dot11MeshGateAnnouncementProtocol
-+		&& mcfg->dot11MeshHWMPRootMode <= RTW_IEEE80211_ROOTMODE_ROOT
-+	) {
-+		mcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_PROACTIVE_RANN;
-+		RTW_INFO(ADPT_FMT" enable PROACTIVE_RANN becaue gate annc is needed\n", ADPT_ARG(adapter));
-+	}
-+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_RANN_INTERVAL, mask))
-+		mcfg->dot11MeshHWMPRannInterval = conf->dot11MeshHWMPRannInterval;
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
-+	if (chk_mesh_attr(NL80211_MESHCONF_FORWARDING, mask))
-+		mcfg->dot11MeshForwarding = conf->dot11MeshForwarding;
-+
-+	if (chk_mesh_attr(NL80211_MESHCONF_RSSI_THRESHOLD, mask))
-+		mcfg->rssi_threshold = conf->rssi_threshold;
-+#endif
-+
-+#if 0 /* controlled by driver */
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
-+	if (chk_mesh_attr(NL80211_MESHCONF_HT_OPMODE, mask));
-+#endif
-+#endif
-+	
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT, mask))
-+		mcfg->dot11MeshHWMPactivePathToRootTimeout = conf->dot11MeshHWMPactivePathToRootTimeout;
-+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOT_INTERVAL, mask))
-+		mcfg->dot11MeshHWMProotInterval = conf->dot11MeshHWMProotInterval;
-+	if (chk_mesh_attr(NL80211_MESHCONF_HWMP_CONFIRMATION_INTERVAL, mask))
-+		mcfg->dot11MeshHWMPconfirmationInterval = conf->dot11MeshHWMPconfirmationInterval;	
-+#endif
-+
-+#if 0 /* TBD */
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
-+	if (chk_mesh_attr(NL80211_MESHCONF_POWER_MODE, mask));
-+	if (chk_mesh_attr(NL80211_MESHCONF_AWAKE_WINDOW, mask));
-+#endif
-+#endif
-+
-+#if 0 /* driver MPM */
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+	if (chk_mesh_attr(NL80211_MESHCONF_PLINK_TIMEOUT, mask));
-+#endif
-+#endif
-+}
-+
-+u8 *rtw_cfg80211_construct_mesh_beacon_ies(struct wiphy *wiphy, _adapter *adapter
-+	, const struct mesh_config *conf, const struct mesh_setup *setup
-+	, uint *ies_len)
-+{
-+	struct rtw_mesh_info *minfo = &adapter->mesh_info;
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	struct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef);
-+#endif
-+	struct ieee80211_channel *chan;
-+	u8 ch, bw, offset;
-+#endif
-+	uint len;
-+	u8 n_bitrates;
-+	u8 ht = 0;
-+	u8 vht = 0;
-+	u8 *rsn_ie = NULL;
-+	sint rsn_ie_len = 0;
-+	u8 *ies = NULL, *c;
-+	u8 supported_rates[RTW_G_RATES_NUM] = {0};
-+	int i;
-+
-+	*ies_len = 0;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	chan = (struct ieee80211_channel *)chdef->chan;
-+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	chan = (struct ieee80211_channel *)setup->channel;
-+#endif
-+
-+	n_bitrates = wiphy->bands[chan->band]->n_bitrates;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	rtw_get_chbw_from_cfg80211_chan_def(chdef, &ht, &ch, &bw, &offset);
-+#else
-+	rtw_get_chbw_from_nl80211_channel_type(chan, setup->channel_type, &ht, &ch, &bw, &offset);
-+#endif
-+	if (!ch)
-+		goto exit;
-+	
-+#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	vht = ht && ch > 14 && bw >= CHANNEL_WIDTH_80; /* VHT40/VHT20? */
-+#endif
-+
-+	RTW_INFO(FUNC_ADPT_FMT" => ch:%u,%u,%u, ht:%u, vht:%u\n"
-+		, FUNC_ADPT_ARG(adapter), ch, bw, offset, ht, vht);
-+#endif
-+
-+	rsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len);
-+	if (rsn_ie && !rsn_ie_len) {
-+		rtw_warn_on(1);
-+		rsn_ie = NULL;
-+	}
-+
-+	len = _BEACON_IE_OFFSET_
-+		+ 2 /* 0-length SSID */
-+		+ (n_bitrates >= 8 ? 8 : n_bitrates) + 2 /* Supported Rates */
-+		+ 3 /* DS parameter set */
-+		+ 6 /* TIM  */
-+		+ (n_bitrates > 8 ? n_bitrates - 8 + 2 : 0) /* Extended Supported Rates */
-+		+ (rsn_ie ? rsn_ie_len + 2 : 0) /* RSN */
-+		#if defined(CONFIG_80211N_HT)
-+		+ (ht ? HT_CAP_IE_LEN + 2 + HT_OP_IE_LEN + 2 : 0) /* HT */
-+		#endif
-+		#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+		+ (vht ? VHT_CAP_IE_LEN + 2 + VHT_OP_IE_LEN + 2 : 0) /* VHT */
-+		#endif
-+		+ minfo->mesh_id_len + 2 /* Mesh ID */
-+		+ 9 /* Mesh configuration */
-+		;
-+
-+	ies = rtw_zmalloc(len);
-+	if (!ies)
-+		goto exit;
-+
-+	/* timestamp */
-+	c = ies + 8;
-+
-+	/* beacon interval */
-+	RTW_PUT_LE16(c , setup->beacon_interval);
-+	c += 2;
-+
-+	/* capability */
-+	if (rsn_ie)
-+		*((u16 *)c) |= cpu_to_le16(cap_Privacy);
-+	c += 2;
-+
-+	/* SSID */
-+	c = rtw_set_ie(c, WLAN_EID_SSID, 0, NULL, NULL);
-+
-+	/* Supported Rates */
-+	for (i = 0; i < n_bitrates; i++) {
-+		supported_rates[i] = wiphy->bands[chan->band]->bitrates[i].bitrate / 5;
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+		if (setup->basic_rates & BIT(i))
-+		#else
-+		if (rtw_is_basic_rate_mix(supported_rates[i]))
-+		#endif
-+			supported_rates[i] |= IEEE80211_BASIC_RATE_MASK;
-+	}
-+	c = rtw_set_ie(c, WLAN_EID_SUPP_RATES, (n_bitrates >= 8 ? 8 : n_bitrates), supported_rates, NULL);
-+
-+	/* DS parameter set */
-+	c = rtw_set_ie(c, WLAN_EID_DS_PARAMS, 1, &ch, NULL);
-+
-+	/* TIM */
-+	*c = WLAN_EID_TIM;
-+	*(c + 1) = 4;
-+	c += 6;
-+	//c = rtw_set_ie(c, _TIM_IE_, 4, NULL, NULL);
-+
-+	/* Extended Supported Rates */
-+	if (n_bitrates > 8)
-+		c = rtw_set_ie(c, WLAN_EID_EXT_SUPP_RATES, n_bitrates - 8, supported_rates + 8, NULL);
-+
-+	/* RSN */
-+	if (rsn_ie)
-+		c = rtw_set_ie(c, WLAN_EID_RSN, rsn_ie_len, rsn_ie + 2, NULL);
-+
-+#if defined(CONFIG_80211N_HT)
-+	if (ht) {
-+		struct ieee80211_sta_ht_cap *sta_ht_cap = &wiphy->bands[chan->band]->ht_cap;
-+		u8 ht_cap[HT_CAP_IE_LEN];
-+		u8 ht_op[HT_OP_IE_LEN];
-+
-+		_rtw_memset(ht_cap, 0, HT_CAP_IE_LEN);
-+		_rtw_memset(ht_op, 0, HT_OP_IE_LEN);
-+
-+		/* WLAN_EID_HT_CAP */
-+		RTW_PUT_LE16(HT_CAP_ELE_CAP_INFO(ht_cap), sta_ht_cap->cap);
-+		SET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(ht_cap, sta_ht_cap->ampdu_factor);
-+		SET_HT_CAP_ELE_MIN_MPDU_S_SPACE(ht_cap, sta_ht_cap->ampdu_density);
-+		_rtw_memcpy(HT_CAP_ELE_SUP_MCS_SET(ht_cap), &sta_ht_cap->mcs, 16);
-+		c = rtw_set_ie(c, WLAN_EID_HT_CAP, HT_CAP_IE_LEN, ht_cap, NULL);
-+
-+		/* WLAN_EID_HT_OPERATION */
-+		SET_HT_OP_ELE_PRI_CHL(ht_op, ch);
-+		switch (offset) {
-+		case HAL_PRIME_CHNL_OFFSET_LOWER:
-+			SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCA);
-+			break;
-+		case HAL_PRIME_CHNL_OFFSET_UPPER:
-+			SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCB);
-+			break;
-+		case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
-+		default:
-+			SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCN);
-+			break;
-+		}
-+		if (bw >= CHANNEL_WIDTH_40)
-+			SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 1);
-+		else
-+			SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 0);
-+		c = rtw_set_ie(c, WLAN_EID_HT_OPERATION, HT_OP_IE_LEN, ht_op, NULL);
-+	}
-+#endif /* defined(CONFIG_80211N_HT) */
-+
-+#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	if (vht) {
-+		struct ieee80211_sta_vht_cap *sta_vht_cap = &wiphy->bands[chan->band]->vht_cap;
-+		u8 vht_cap[VHT_CAP_IE_LEN];
-+		u8 vht_op[VHT_OP_IE_LEN];
-+		u8 cch = rtw_get_center_ch(ch, bw, offset);
-+
-+		_rtw_memset(vht_op, 0, VHT_OP_IE_LEN);
-+
-+		/* WLAN_EID_VHT_CAPABILITY */
-+		_rtw_memcpy(vht_cap, &sta_vht_cap->cap, 4);
-+		_rtw_memcpy(vht_cap + 4, &sta_vht_cap->vht_mcs, 8);
-+		c = rtw_set_ie(c, WLAN_EID_VHT_CAPABILITY, VHT_CAP_IE_LEN, vht_cap, NULL);
-+
-+		/* WLAN_EID_VHT_OPERATION */
-+		if (bw < CHANNEL_WIDTH_80) {
-+			SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 0);
-+			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, 0);
-+			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0);
-+		} else if (bw == CHANNEL_WIDTH_80) {
-+			SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 1);
-+			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, cch);
-+			SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0);
-+		} else {
-+			RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(adapter), bw);
-+			rtw_warn_on(1);
-+			rtw_mfree(ies, len);
-+			goto exit;
-+		}
-+
-+		/* Hard code 1 stream, MCS0-7 is a min Basic VHT MCS rates */
-+		vht_op[3] = 0xfc;
-+		vht_op[4] = 0xff;
-+		c = rtw_set_ie(c, WLAN_EID_VHT_OPERATION, VHT_OP_IE_LEN, vht_op, NULL);
-+	}
-+#endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */
-+
-+	/* Mesh ID */
-+	c = rtw_set_ie_mesh_id(c, NULL, minfo->mesh_id, minfo->mesh_id_len);
-+
-+	/* Mesh configuration */
-+	c = rtw_set_ie_mesh_config(c, NULL
-+		, minfo->mesh_pp_id
-+		, minfo->mesh_pm_id
-+		, minfo->mesh_cc_id
-+		, minfo->mesh_sp_id
-+		, minfo->mesh_auth_id
-+		, 0, 0, 0
-+		, 1
-+		, 0, 0
-+		, mcfg->dot11MeshForwarding
-+		, 0, 0, 0
-+	);
-+
-+#if DBG_RTW_CFG80211_MESH_CONF
-+	RTW_INFO(FUNC_ADPT_FMT" ies_len:%u\n", FUNC_ADPT_ARG(adapter), len);
-+	dump_ies(RTW_DBGDUMP, ies + _BEACON_IE_OFFSET_, len - _BEACON_IE_OFFSET_);
-+#endif
-+
-+exit:
-+	if (ies)
-+		*ies_len = len;
-+	return ies;
-+}
-+
-+static int cfg80211_rtw_get_mesh_config(struct wiphy *wiphy, struct net_device *dev
-+	, struct mesh_config *conf)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rtw_mesh_cfg *mesh_cfg = &adapter->mesh_cfg;
-+	int ret = 0;
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
-+
-+	/* driver MPM */
-+	conf->dot11MeshRetryTimeout = 0;
-+	conf->dot11MeshConfirmTimeout = 0;
-+	conf->dot11MeshHoldingTimeout = 0;
-+	conf->dot11MeshMaxPeerLinks = mesh_cfg->max_peer_links;
-+	conf->dot11MeshMaxRetries = 0;
-+
-+	conf->dot11MeshTTL = mesh_cfg->dot11MeshTTL;
-+	conf->element_ttl = mesh_cfg->element_ttl;
-+
-+	/* driver MPM */
-+	conf->auto_open_plinks = 0;
-+
-+	/* TBD: synchronization */
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
-+	conf->dot11MeshNbrOffsetMaxNeighbor = 0;
-+#endif
-+
-+	conf->dot11MeshHWMPmaxPREQretries = mesh_cfg->dot11MeshHWMPmaxPREQretries;
-+	conf->path_refresh_time = mesh_cfg->path_refresh_time;
-+	conf->min_discovery_timeout = mesh_cfg->min_discovery_timeout;
-+	conf->dot11MeshHWMPactivePathTimeout = mesh_cfg->dot11MeshHWMPactivePathTimeout;
-+	conf->dot11MeshHWMPpreqMinInterval = mesh_cfg->dot11MeshHWMPpreqMinInterval;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
-+	conf->dot11MeshHWMPperrMinInterval = mesh_cfg->dot11MeshHWMPperrMinInterval;
-+#endif
-+	conf->dot11MeshHWMPnetDiameterTraversalTime = mesh_cfg->dot11MeshHWMPnetDiameterTraversalTime;
-+	conf->dot11MeshHWMPRootMode = mesh_cfg->dot11MeshHWMPRootMode;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
-+	conf->dot11MeshHWMPRannInterval = mesh_cfg->dot11MeshHWMPRannInterval;
-+#endif
-+	conf->dot11MeshGateAnnouncementProtocol = mesh_cfg->dot11MeshGateAnnouncementProtocol;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
-+	conf->dot11MeshForwarding = mesh_cfg->dot11MeshForwarding;
-+	conf->rssi_threshold = mesh_cfg->rssi_threshold;
-+#endif
-+
-+	/* TBD */
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
-+	conf->ht_opmode = 0xffff;
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	conf->dot11MeshHWMPactivePathToRootTimeout = mesh_cfg->dot11MeshHWMPactivePathToRootTimeout;
-+	conf->dot11MeshHWMProotInterval = mesh_cfg->dot11MeshHWMProotInterval;
-+	conf->dot11MeshHWMPconfirmationInterval = mesh_cfg->dot11MeshHWMPconfirmationInterval;
-+#endif
-+
-+	/* TBD: power save */
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
-+	conf->power_mode = NL80211_MESH_POWER_ACTIVE;
-+	conf->dot11MeshAwakeWindowDuration = 0;
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+	conf->plink_timeout = mesh_cfg->plink_timeout;
-+#endif
-+
-+	return ret;
-+}
-+
-+static void rtw_mbss_info_change_notify(_adapter *adapter, bool minfo_changed, bool need_work)
-+{
-+	if (need_work)
-+		rtw_mesh_work(&adapter->mesh_work);
-+}
-+
-+static int cfg80211_rtw_update_mesh_config(struct wiphy *wiphy, struct net_device *dev
-+	, u32 mask, const struct mesh_config *nconf)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	int ret = 0;
-+	bool minfo_changed = _FALSE, need_work = _FALSE;
-+
-+	RTW_INFO(FUNC_ADPT_FMT" mask:0x%08x\n", FUNC_ADPT_ARG(adapter), mask);
-+
-+	rtw_cfg80211_mesh_cfg_set(adapter, nconf, mask);
-+	update_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE, 0);
-+#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
-+	if (rtw_mesh_cto_mgate_required(adapter))
-+		rtw_netif_carrier_off(adapter->pnetdev);
-+	else
-+		rtw_netif_carrier_on(adapter->pnetdev);
-+#endif
-+	need_work = rtw_ieee80211_mesh_root_setup(adapter);
-+
-+	rtw_mbss_info_change_notify(adapter, minfo_changed, need_work);
-+
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_join_mesh(struct wiphy *wiphy, struct net_device *dev,
-+	const struct mesh_config *conf, const struct mesh_setup *setup)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 *ies = NULL;
-+	uint ies_len;
-+	int ret = 0;
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
-+
-+#if DBG_RTW_CFG80211_MESH_CONF
-+	RTW_INFO(FUNC_ADPT_FMT" mesh_setup:\n", FUNC_ADPT_ARG(adapter));
-+	dump_mesh_setup(RTW_DBGDUMP, wiphy, setup);
-+	RTW_INFO(FUNC_ADPT_FMT" mesh_config:\n", FUNC_ADPT_ARG(adapter));
-+	dump_mesh_config(RTW_DBGDUMP, conf);
-+#endif
-+
-+	if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) {
-+		ret = -ENOTSUPP;
-+		goto exit;
-+	}
-+
-+	/* initialization */
-+	rtw_mesh_init_mesh_info(adapter);
-+
-+	/* apply cfg80211 settings*/
-+	rtw_cfg80211_mesh_info_set_profile(&adapter->mesh_info, setup);
-+	rtw_cfg80211_mesh_cfg_set(adapter, conf, 0xFFFFFFFF);
-+
-+	/* apply cfg80211 settings (join only) */
-+	rtw_mesh_cfg_init_max_peer_links(adapter, conf->dot11MeshMaxPeerLinks);
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+	rtw_mesh_cfg_init_plink_timeout(adapter, conf->plink_timeout);
-+	#endif
-+
-+	rtw_ieee80211_mesh_root_setup(adapter);
-+
-+	ies = rtw_cfg80211_construct_mesh_beacon_ies(wiphy, adapter, conf, setup, &ies_len);
-+	if (!ies) {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	/* start mbss */
-+	if (rtw_check_beacon_data(adapter, ies,  ies_len) != _SUCCESS) {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+	
-+	rtw_mesh_work(&adapter->mesh_work);
-+
-+exit:
-+	if (ies)
-+		rtw_mfree(ies, ies_len);
-+	if (ret)
-+		rtw_mesh_deinit_mesh_info(adapter);
-+
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_leave_mesh(struct wiphy *wiphy, struct net_device *dev)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	int ret = 0;
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
-+
-+	rtw_mesh_deinit_mesh_info(adapter);
-+
-+	rtw_stop_ap_cmd(adapter, RTW_CMDF_WAIT_ACK);
-+
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_add_mpath(struct wiphy *wiphy, struct net_device *dev
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
-+	, const u8 *dst, const u8 *next_hop
-+	#else
-+	, u8 *dst, u8 *next_hop
-+	#endif
-+)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct sta_info *sta;
-+	struct rtw_mesh_path *mpath;
-+	int ret = 0;
-+
-+	rtw_rcu_read_lock();
-+
-+	sta = rtw_get_stainfo(stapriv, next_hop);
-+	if (!sta) {
-+		ret = -ENOENT;
-+		goto exit;
-+	}
-+
-+	mpath = rtw_mesh_path_add(adapter, dst);
-+	if (!mpath) {
-+		ret = -ENOENT;
-+		goto exit;
-+	}
-+
-+	rtw_mesh_path_fix_nexthop(mpath, sta);
-+
-+exit:
-+	rtw_rcu_read_unlock();
-+
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_del_mpath(struct wiphy *wiphy, struct net_device *dev
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
-+	, const u8 *dst
-+	#else
-+	, u8 *dst
-+	#endif
-+)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	int ret = 0;
-+
-+	if (dst) {
-+		if (rtw_mesh_path_del(adapter, dst)) {
-+			ret = -ENOENT;
-+			goto exit;
-+		}
-+	} else {
-+		rtw_mesh_path_flush_by_iface(adapter);
-+	}	
-+
-+exit:
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_change_mpath(struct wiphy *wiphy, struct net_device *dev
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
-+	, const u8 *dst, const u8 *next_hop
-+	#else
-+	, u8 *dst, u8 *next_hop
-+	#endif
-+)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+	struct sta_info *sta;
-+	struct rtw_mesh_path *mpath;
-+	int ret = 0;
-+
-+	rtw_rcu_read_lock();
-+
-+	sta = rtw_get_stainfo(stapriv, next_hop);
-+	if (!sta) {
-+		ret = -ENOENT;
-+		goto exit;
-+	}
-+
-+	mpath = rtw_mesh_path_lookup(adapter, dst);
-+	if (!mpath) {
-+		ret = -ENOENT;
-+		goto exit;
-+	}
-+
-+	rtw_mesh_path_fix_nexthop(mpath, sta);
-+
-+exit:
-+	rtw_rcu_read_unlock();
-+
-+	return ret;
-+}
-+
-+static void rtw_cfg80211_mpath_set_pinfo(struct rtw_mesh_path *mpath, u8 *next_hop, struct mpath_info *pinfo)
-+{
-+	struct sta_info *next_hop_sta = rtw_rcu_dereference(mpath->next_hop);
-+
-+	if (next_hop_sta)
-+		_rtw_memcpy(next_hop, next_hop_sta->cmn.mac_addr, ETH_ALEN);
-+	else
-+		_rtw_memset(next_hop, 0, ETH_ALEN);
-+
-+	_rtw_memset(pinfo, 0, sizeof(*pinfo));
-+
-+	pinfo->generation = mpath->adapter->mesh_info.mesh_paths_generation;
-+
-+	pinfo->filled = 0
-+		| MPATH_INFO_FRAME_QLEN
-+		| MPATH_INFO_SN
-+		| MPATH_INFO_METRIC
-+		| MPATH_INFO_EXPTIME
-+		| MPATH_INFO_DISCOVERY_TIMEOUT
-+		| MPATH_INFO_DISCOVERY_RETRIES
-+		| MPATH_INFO_FLAGS
-+		;
-+
-+	pinfo->frame_qlen = mpath->frame_queue_len;
-+	pinfo->sn = mpath->sn;
-+	pinfo->metric = mpath->metric;
-+	if (rtw_time_after(mpath->exp_time, rtw_get_current_time()))
-+		pinfo->exptime = rtw_get_remaining_time_ms(mpath->exp_time);
-+	pinfo->discovery_timeout = rtw_systime_to_ms(mpath->discovery_timeout);
-+	pinfo->discovery_retries = mpath->discovery_retries;
-+	if (mpath->flags & RTW_MESH_PATH_ACTIVE)
-+		pinfo->flags |= NL80211_MPATH_FLAG_ACTIVE;
-+	if (mpath->flags & RTW_MESH_PATH_RESOLVING)
-+		pinfo->flags |= NL80211_MPATH_FLAG_RESOLVING;
-+	if (mpath->flags & RTW_MESH_PATH_SN_VALID)
-+		pinfo->flags |= NL80211_MPATH_FLAG_SN_VALID;
-+	if (mpath->flags & RTW_MESH_PATH_FIXED)
-+		pinfo->flags |= NL80211_MPATH_FLAG_FIXED;
-+	if (mpath->flags & RTW_MESH_PATH_RESOLVED)
-+		pinfo->flags |= NL80211_MPATH_FLAG_RESOLVED;
-+}
-+
-+static int cfg80211_rtw_get_mpath(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *next_hop, struct mpath_info *pinfo)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rtw_mesh_path *mpath;
-+	int ret = 0;
-+
-+	rtw_rcu_read_lock();
-+
-+	mpath = rtw_mesh_path_lookup(adapter, dst);
-+	if (!mpath) {
-+		ret = -ENOENT;
-+		goto exit;
-+	}
-+
-+	rtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo);
-+
-+exit:
-+	rtw_rcu_read_unlock();
-+
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_dump_mpath(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *next_hop, struct mpath_info *pinfo)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rtw_mesh_path *mpath;
-+	int ret = 0;
-+
-+	rtw_rcu_read_lock();
-+
-+	mpath = rtw_mesh_path_lookup_by_idx(adapter, idx);
-+	if (!mpath) {
-+		ret = -ENOENT;
-+		goto exit;
-+	}
-+
-+	_rtw_memcpy(dst, mpath->dst, ETH_ALEN);
-+	rtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo);
-+
-+exit:
-+	rtw_rcu_read_unlock();
-+
-+	return ret;
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
-+static void rtw_cfg80211_mpp_set_pinfo(struct rtw_mesh_path *mpath, u8 *mpp, struct mpath_info *pinfo)
-+{
-+	_rtw_memcpy(mpp, mpath->mpp, ETH_ALEN);
-+
-+	_rtw_memset(pinfo, 0, sizeof(*pinfo));
-+	pinfo->generation = mpath->adapter->mesh_info.mpp_paths_generation;
-+}
-+
-+static int cfg80211_rtw_get_mpp(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *mpp, struct mpath_info *pinfo)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rtw_mesh_path *mpath;
-+	int ret = 0;
-+
-+	rtw_rcu_read_lock();
-+
-+	mpath = rtw_mpp_path_lookup(adapter, dst);
-+	if (!mpath) {
-+		ret = -ENOENT;
-+		goto exit;
-+	}
-+
-+	rtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo);
-+
-+exit:
-+	rtw_rcu_read_unlock();
-+
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_dump_mpp(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *mpp, struct mpath_info *pinfo)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rtw_mesh_path *mpath;
-+	int ret = 0;
-+
-+	rtw_rcu_read_lock();
-+
-+	mpath = rtw_mpp_path_lookup_by_idx(adapter, idx);
-+	if (!mpath) {
-+		ret = -ENOENT;
-+		goto exit;
-+	}
-+
-+	_rtw_memcpy(dst, mpath->dst, ETH_ALEN);
-+	rtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo);
-+
-+exit:
-+	rtw_rcu_read_unlock();
-+
-+	return ret;
-+}
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) */
-+
-+#endif /* defined(CONFIG_RTW_MESH) */
-+
-+#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy,
-+		struct net_device *dev,
-+		struct cfg80211_sched_scan_request *request)
-+{
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct cfg80211_ssid *ssids;
-+	int n_ssids = 0;
-+	int interval = 0;
-+	int i = 0;
-+	u8 ret;
-+
-+	if (padapter->bup == _FALSE) {
-+		RTW_INFO("%s: net device is down.\n", __func__);
-+		return -EIO;
-+	}
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE ||
-+		check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE  ||
-+		check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) {
-+		RTW_INFO("%s: device is busy.\n", __func__);
-+		rtw_scan_abort(padapter);
-+	}
-+
-+	if (request == NULL) {
-+		RTW_INFO("%s: invalid cfg80211_requests parameters.\n", __func__);
-+		return -EINVAL;
-+	}
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)
-+	interval = request->scan_plans->interval;
-+#else
-+	interval = request->interval;
-+#endif
-+	n_ssids = request->n_match_sets;
-+	ssids = (struct cfg80211_ssid *)rtw_zmalloc(n_ssids * sizeof(struct cfg80211_ssid));
-+	if(ssids == NULL) {
-+		RTW_ERR("Fail to allocate ssids for PNO\n");
-+		return -ENOMEM;
-+	}
-+	for (i=0;i<request->n_match_sets;i++) {
-+			ssids[i].ssid_len = request->match_sets[i].ssid.ssid_len;
-+			memcpy(ssids[i].ssid, request->match_sets[i].ssid.ssid,
-+					request->match_sets[i].ssid.ssid_len);
-+	}
-+#else
-+	interval = request->interval;
-+	n_ssids = request->n_ssids;
-+	ssids = request->ssids;
-+#endif
-+ret = rtw_android_cfg80211_pno_setup(dev, ssids,
-+			n_ssids, interval);
-+	if (ret < 0) {
-+		RTW_INFO("%s ret: %d\n", __func__, ret);
-+		goto exit;
-+	}
-+
-+	ret = rtw_android_pno_enable(dev, _TRUE);
-+	if (ret < 0) {
-+		RTW_INFO("%s ret: %d\n", __func__, ret);
-+		goto exit;
-+	}
-+exit:
-+	return ret;
-+}
-+
-+static int cfg80211_rtw_sched_scan_stop(struct wiphy *wiphy,
-+		struct net_device *dev)
-+{
-+	return rtw_android_pno_enable(dev, _FALSE);
-+}
-+
-+int	cfg80211_rtw_suspend(struct wiphy *wiphy, struct cfg80211_wowlan *wow) {
-+	RTW_DBG("==> %s\n",__func__);
-+	RTW_DBG("<== %s\n",__func__);
-+	return 0;
-+}
-+
-+int	cfg80211_rtw_resume(struct wiphy *wiphy) {
-+
-+	_adapter *padapter;
-+	struct pwrctrl_priv *pwrpriv;
-+	struct mlme_priv *pmlmepriv;
-+	padapter = wiphy_to_adapter(wiphy);
-+	pwrpriv = adapter_to_pwrctl(padapter);
-+	pmlmepriv = &padapter->mlmepriv;
-+	struct sitesurvey_parm parm;
-+	int i, len;
-+
-+
-+	RTW_DBG("==> %s\n",__func__);
-+	if (pwrpriv->wowlan_last_wake_reason == RX_PNO) {
-+
-+		struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+		_irqL irqL;
-+		int PNOWakeupScanWaitCnt = 0;
-+
-+		rtw_cfg80211_disconnected(padapter->rtw_wdev, 0, NULL, 0, 1, GFP_ATOMIC);
-+
-+		rtw_init_sitesurvey_parm(padapter, &parm);
-+		for (i=0;i<pwrpriv->pnlo_info->ssid_num && i < RTW_SSID_SCAN_AMOUNT; i++) {
-+			len = pwrpriv->pno_ssid_list->node[i].SSID_len;
-+			_rtw_memcpy(&parm.ssid[i].Ssid, pwrpriv->pno_ssid_list->node[i].SSID, len);
-+			parm.ssid[i].SsidLength = len;
-+		}
-+		parm.ssid_num = pwrpriv->pnlo_info->ssid_num;
-+
-+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+		//This modification fix PNO wakeup reconnect issue with hidden SSID AP.
-+		//rtw_sitesurvey_cmd(padapter, NULL);
-+		rtw_sitesurvey_cmd(padapter, &parm);
-+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+		
-+		for (PNOWakeupScanWaitCnt = 0; PNOWakeupScanWaitCnt < 10; PNOWakeupScanWaitCnt++) {
-+			if(check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _FALSE)
-+				break;
-+			rtw_msleep_os(1000);
-+		}
-+		
-+		_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+		cfg80211_sched_scan_results(padapter->rtw_wdev->wiphy);
-+		_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+	}
-+	RTW_DBG("<== %s\n",__func__);
-+	return 0;
-+	
-+}
-+#endif /* CONFIG_PNO_SUPPORT */
-+
-+#ifdef CONFIG_80211N_HT
-+static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter
-+	, struct ieee80211_sta_ht_cap *ht_cap, BAND_TYPE band, u8 rf_type)
-+{
-+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct ht_priv		*phtpriv = &pmlmepriv->htpriv;
-+	u8 stbc_rx_enable = _FALSE;
-+
-+	rtw_ht_use_default_setting(padapter);
-+
-+	/* RX LDPC */
-+	if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX))
-+		ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
-+
-+	/* TX STBC */
-+	if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX))
-+		ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC;
-+
-+	/* RX STBC */
-+	if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) {
-+		/*rtw_rx_stbc 0: disable, bit(0):enable 2.4g, bit(1):enable 5g*/
-+		if (band == BAND_ON_2_4G)
-+			stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(0)) ? _TRUE : _FALSE;
-+		if (band == BAND_ON_5G)
-+			stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(1)) ? _TRUE : _FALSE;
-+
-+		if (stbc_rx_enable) {
-+			switch (rf_type) {
-+			case RF_1T1R:
-+				ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/*RX STBC One spatial stream*/
-+				break;
-+
-+			case RF_2T2R:
-+			case RF_1T2R:
-+				ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */
-+				break;
-+			case RF_3T3R:
-+			case RF_3T4R:
-+			case RF_4T4R:
-+				ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */
-+				break;
-+			default:
-+				RTW_INFO("[warning] rf_type %d is not expected\n", rf_type);
-+				break;
-+			}
-+		}
-+	}
-+}
-+
-+static void rtw_cfg80211_init_ht_capab(_adapter *padapter
-+	, struct ieee80211_sta_ht_cap *ht_cap, BAND_TYPE band, u8 rf_type)
-+{
-+	struct registry_priv *regsty = &padapter->registrypriv;
-+	u8 rx_nss = 0;
-+
-+	if (!regsty->ht_enable || !is_supported_ht(regsty->wireless_mode))
-+		return;
-+
-+	ht_cap->ht_supported = 1;
-+
-+	ht_cap->cap = IEEE80211_HT_CAP_MAX_AMSDU;
-+
-+	if (TEST_FLAG(regsty->short_gi, BIT0))
-+		ht_cap->cap |= IEEE80211_HT_CAP_SGI_20;
-+	if (hal_is_bw_support(padapter, CHANNEL_WIDTH_40)
-+		&& ((band == BAND_ON_2_4G && REGSTY_IS_BW_2G_SUPPORT(regsty, CHANNEL_WIDTH_40))
-+			|| (band == BAND_ON_5G && REGSTY_IS_BW_5G_SUPPORT(regsty, CHANNEL_WIDTH_40)))
-+	) {
-+		ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
-+		if (band == BAND_ON_2_4G)
-+			ht_cap->cap |= IEEE80211_HT_CAP_DSSSCCK40;
-+		if (TEST_FLAG(regsty->short_gi, BIT1))
-+			ht_cap->cap |= IEEE80211_HT_CAP_SGI_40;
-+	}
-+
-+	rtw_cfg80211_init_ht_capab_ex(padapter, ht_cap, band, rf_type);
-+
-+	/*
-+	 *Maximum length of AMPDU that the STA can receive.
-+	 *Length = 2 ^ (13 + max_ampdu_length_exp) - 1 (octets)
-+	 */
-+	ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
-+
-+	/*Minimum MPDU start spacing , */
-+	ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
-+
-+	ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
-+
-+	rx_nss = GET_HAL_RX_NSS(padapter);
-+	switch (rx_nss) {
-+	case 1:
-+		ht_cap->mcs.rx_mask[0] = 0xFF;
-+		break;
-+	case 2:
-+		ht_cap->mcs.rx_mask[0] = 0xFF;
-+		ht_cap->mcs.rx_mask[1] = 0xFF;
-+		break;
-+	case 3:
-+		ht_cap->mcs.rx_mask[0] = 0xFF;
-+		ht_cap->mcs.rx_mask[1] = 0xFF;
-+		ht_cap->mcs.rx_mask[2] = 0xFF;
-+		break;
-+	case 4:
-+		ht_cap->mcs.rx_mask[0] = 0xFF;
-+		ht_cap->mcs.rx_mask[1] = 0xFF;
-+		ht_cap->mcs.rx_mask[2] = 0xFF;
-+		ht_cap->mcs.rx_mask[3] = 0xFF;
-+		break;
-+	default:
-+		rtw_warn_on(1);
-+		RTW_INFO("%s, error rf_type=%d, rx_nss=%d\n", __func__, rf_type, rx_nss);
-+	};
-+
-+	ht_cap->mcs.rx_highest = cpu_to_le16(
-+		rtw_ht_mcs_rate(hal_is_bw_support(padapter, CHANNEL_WIDTH_40)
-+			, hal_is_bw_support(padapter, CHANNEL_WIDTH_40) ? ht_cap->cap & IEEE80211_HT_CAP_SGI_40 : ht_cap->cap & IEEE80211_HT_CAP_SGI_20
-+			, ht_cap->mcs.rx_mask) / 10);
-+}
-+#endif /* CONFIG_80211N_HT */
-+
-+#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+static void rtw_cfg80211_init_vht_capab(_adapter *padapter
-+	, struct ieee80211_sta_vht_cap *sta_vht_cap, BAND_TYPE band, u8 rf_type)
-+{
-+	struct registry_priv *regsty = &padapter->registrypriv;
-+	u8 vht_cap_ie[2 + 12] = {0};
-+
-+	if (!REGSTY_IS_11AC_ENABLE(regsty) || !is_supported_vht(regsty->wireless_mode))
-+		return;
-+
-+	rtw_vht_use_default_setting(padapter);
-+	rtw_build_vht_cap_ie(padapter, vht_cap_ie);
-+
-+	sta_vht_cap->vht_supported = 1;
-+
-+	_rtw_memcpy(&sta_vht_cap->cap, vht_cap_ie + 2, 4);
-+	_rtw_memcpy(&sta_vht_cap->vht_mcs, vht_cap_ie + 2 + 4, 8);
-+}
-+#endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */
-+
-+void rtw_cfg80211_init_wdev_data(_adapter *padapter)
-+{
-+#ifdef CONFIG_CONCURRENT_MODE
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+
-+	ATOMIC_SET(&pwdev_priv->switch_ch_to, 1);
-+#endif
-+}
-+
-+static int rtw_cfg80211_init_wiphy_band(_adapter *padapter, struct wiphy *wiphy)
-+{
-+	u8 rf_type;
-+	struct ieee80211_supported_band *band;
-+	int ret = _FAIL;
-+
-+	rf_type = GET_HAL_RFPATH(padapter);
-+	RTW_INFO("%s:rf_type=%d\n", __func__, rf_type);
-+
-+	if (IsSupported24G(padapter->registrypriv.wireless_mode)) {
-+		band = wiphy->bands[NL80211_BAND_2GHZ] = rtw_spt_band_alloc(BAND_ON_2_4G);
-+		if (!band)
-+			goto exit;
-+		rtw_2g_channels_init(band->channels);
-+		rtw_2g_rates_init(band->bitrates);
-+		#if defined(CONFIG_80211N_HT)
-+		rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_2_4G, rf_type);
-+		#endif
-+	}
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	if (is_supported_5g(padapter->registrypriv.wireless_mode)) {
-+		band = wiphy->bands[NL80211_BAND_5GHZ] = rtw_spt_band_alloc(BAND_ON_5G);
-+		if (!band) {
-+			if (wiphy->bands[NL80211_BAND_2GHZ]) {
-+				rtw_spt_band_free(wiphy->bands[NL80211_BAND_2GHZ]);
-+				wiphy->bands[NL80211_BAND_2GHZ] = NULL;
-+			}
-+			goto exit;
-+		}
-+		rtw_5g_channels_init(band->channels);
-+		rtw_5g_rates_init(band->bitrates);
-+		#if defined(CONFIG_80211N_HT)
-+		rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_5G, rf_type);
-+		#endif
-+		#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+		rtw_cfg80211_init_vht_capab(padapter, &band->vht_cap, BAND_ON_5G, rf_type);
-+		#endif
-+	}
-+#endif
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+#if !defined(CONFIG_REGD_SRC_FROM_OS) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
-+void rtw_cfg80211_update_wiphy_max_txpower(_adapter *adapter, struct wiphy *wiphy)
-+{
-+	struct ieee80211_supported_band *band;
-+	struct ieee80211_channel *channel;
-+	s16 max_txpwr;
-+	int i;
-+
-+	if (IsSupported24G(adapter->registrypriv.wireless_mode)) {
-+		band = wiphy->bands[NL80211_BAND_2GHZ];
-+		if (band) {
-+			max_txpwr = phy_get_txpwr_by_rate_total_max_mbm(adapter, BAND_ON_2_4G, 1, 1);
-+			if (max_txpwr != UNSPECIFIED_MBM) {
-+				for (i = 0; i < band->n_channels; i++) {
-+					channel = &band->channels[i];
-+					channel->max_power = max_txpwr / MBM_PDBM;
-+				}
-+			}
-+		}
-+	}
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	if (is_supported_5g(adapter->registrypriv.wireless_mode)) {
-+		band = wiphy->bands[NL80211_BAND_5GHZ];
-+		if (band) {
-+			max_txpwr = phy_get_txpwr_by_rate_total_max_mbm(adapter, BAND_ON_5G, 1, 1);
-+			if (max_txpwr != UNSPECIFIED_MBM) {
-+				for (i = 0; i < band->n_channels; i++) {
-+					channel = &band->channels[i];
-+					channel->max_power = max_txpwr / MBM_PDBM;
-+				}
-+			}
-+		}
-+	}
-+#endif
-+}
-+#endif /* defined(CONFIG_REGD_SRC_FROM_OS) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) */
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) && defined(RTW_SINGLE_WIPHY) && (CONFIG_IFACE_NUMBER >= 2)
-+struct ieee80211_iface_limit rtw_limits[] = {
-+	{
-+		.max = CONFIG_IFACE_NUMBER,
-+		.types = BIT(NL80211_IFTYPE_STATION)
-+			#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
-+			| BIT(NL80211_IFTYPE_P2P_CLIENT)
-+			#endif
-+	},
-+	#ifdef CONFIG_AP_MODE
-+	{
-+		.max = rtw_min(CONFIG_IFACE_NUMBER, CONFIG_LIMITED_AP_NUM),
-+		.types = BIT(NL80211_IFTYPE_AP)
-+			#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
-+			| BIT(NL80211_IFTYPE_P2P_GO)
-+			#endif
-+	},
-+	#endif
-+	#if defined(RTW_DEDICATED_P2P_DEVICE)
-+	{
-+		.max = 1,
-+		.types = BIT(NL80211_IFTYPE_P2P_DEVICE)
-+	},
-+	#endif
-+	#if defined(CONFIG_RTW_MESH)
-+	{
-+		.max = 1,
-+		.types = BIT(NL80211_IFTYPE_MESH_POINT)
-+	},
-+	#endif
-+};
-+
-+struct ieee80211_iface_combination rtw_combinations[] = {
-+	{
-+		.limits = rtw_limits,
-+		.n_limits = ARRAY_SIZE(rtw_limits),
-+		#if defined(RTW_DEDICATED_P2P_DEVICE)
-+		.max_interfaces = CONFIG_IFACE_NUMBER + 1,
-+		#else
-+		.max_interfaces = CONFIG_IFACE_NUMBER,
-+		#endif
-+		.num_different_channels = 1,
-+	},
-+};
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) */
-+
-+static int rtw_cfg80211_init_wiphy(_adapter *adapter, struct wiphy *wiphy)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
-+	int ret = _FAIL;
-+
-+	/* copy mac_addr to wiphy */
-+	_rtw_memcpy(wiphy->perm_addr, adapter_mac_addr(adapter), ETH_ALEN);
-+
-+	wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
-+
-+	wiphy->max_scan_ssids = RTW_SSID_SCAN_AMOUNT;
-+	wiphy->max_scan_ie_len = RTW_SCAN_IE_LEN_MAX;
-+	wiphy->max_num_pmkids = RTW_MAX_NUM_PMKIDS;
-+
-+#if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
-+	wiphy->max_acl_mac_addrs = NUM_ACL;
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE)
-+	wiphy->max_remain_on_channel_duration = RTW_MAX_REMAIN_ON_CHANNEL_DURATION;
-+#endif
-+
-+	wiphy->interface_modes =	BIT(NL80211_IFTYPE_STATION)
-+								#ifdef CONFIG_AP_MODE
-+								| BIT(NL80211_IFTYPE_ADHOC) /* todo : AD-HOC task group will refine it */
-+								| BIT(NL80211_IFTYPE_AP)
-+								#endif
-+								#ifdef CONFIG_WIFI_MONITOR
-+								| BIT(NL80211_IFTYPE_MONITOR)
-+								#endif
-+#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE))
-+								| BIT(NL80211_IFTYPE_P2P_CLIENT)
-+								| BIT(NL80211_IFTYPE_P2P_GO)
-+								#if defined(RTW_DEDICATED_P2P_DEVICE)
-+								| BIT(NL80211_IFTYPE_P2P_DEVICE)
-+								#endif
-+#endif
-+#ifdef CONFIG_RTW_MESH
-+								| BIT(NL80211_IFTYPE_MESH_POINT) /* 2.6.26 */
-+#endif
-+								;
-+
-+#if !defined(RTW_SINGLE_WIPHY) && defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_P2P)
-+	if (adapter->iface_id != adapter->registrypriv.sel_p2p_iface) {
-+		wiphy->interface_modes &= ~(BIT(NL80211_IFTYPE_P2P_GO) | BIT(NL80211_IFTYPE_P2P_CLIENT));
-+		RTW_INFO("%s iface_id:%d- don't set p2p capability\n", __func__, adapter->iface_id);
-+	}
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+	wiphy->mgmt_stypes = rtw_cfg80211_default_mgmt_stypes;
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+	#ifdef CONFIG_WIFI_MONITOR
-+	wiphy->software_iftypes |= BIT(NL80211_IFTYPE_MONITOR);
-+	#endif
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) && defined(RTW_SINGLE_WIPHY) && (CONFIG_IFACE_NUMBER >= 2)
-+	wiphy->iface_combinations = rtw_combinations;
-+	wiphy->n_iface_combinations = ARRAY_SIZE(rtw_combinations);
-+#endif
-+
-+	wiphy->cipher_suites = rtw_cipher_suites;
-+
-+	/* Todo refine */
-+	if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_EXTRA_SEC))
-+		wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites);
-+	else {
-+#ifdef CONFIG_IEEE80211W
-+		/* remove hardware not support cipher */
-+		wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites) - 6;
-+#else
-+		wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites);
-+#endif
-+	}
-+
-+	if (rtw_cfg80211_init_wiphy_band(adapter, wiphy) != _SUCCESS) {
-+		RTW_ERR("rtw_cfg80211_init_wiphy_band fail\n");
-+		goto exit;
-+	}
-+	#if !defined(CONFIG_REGD_SRC_FROM_OS) || (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
-+	rtw_cfg80211_update_wiphy_max_txpower(adapter, wiphy);
-+	#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38) && LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0))
-+	wiphy->flags |= WIPHY_FLAG_SUPPORTS_SEPARATE_DEFAULT_KEYS;
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
-+	wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
-+	wiphy->flags |= WIPHY_FLAG_HAVE_AP_SME;
-+	/* remove WIPHY_FLAG_OFFCHAN_TX, because we not support this feature */
-+	/* wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX | WIPHY_FLAG_HAVE_AP_SME; */
-+#endif
-+
-+#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) && \
-+			   LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0))
-+	wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN;
-+#ifdef CONFIG_PNO_SUPPORT
-+	wiphy->max_sched_scan_ssids = MAX_PNO_LIST_COUNT;
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)
-+	wiphy->max_match_sets = MAX_PNO_LIST_COUNT;
-+#endif
-+#endif
-+#endif
-+
-+#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0))
-+	wiphy->wowlan = wowlan_stub;
-+#else
-+	wiphy->wowlan = &wowlan_stub;
-+#endif
-+#endif
-+
-+#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
-+	wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
-+#ifndef CONFIG_TDLS_DRIVER_SETUP
-+	wiphy->flags |= WIPHY_FLAG_TDLS_EXTERNAL_SETUP;	/* Driver handles key exchange */
-+	wiphy->flags |= NL80211_ATTR_HT_CAPABILITY;
-+#endif /* CONFIG_TDLS_DRIVER_SETUP */
-+#endif /* CONFIG_TDLS */
-+
-+#ifdef CONFIG_LPS
-+		wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT;
-+#else
-+		wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
-+	/* wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM; */
-+#endif
-+
-+#ifdef CONFIG_RTW_WDS
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))
-+	wiphy->flags |= WIPHY_FLAG_4ADDR_AP;
-+	wiphy->flags |= WIPHY_FLAG_4ADDR_STATION;
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTW_MESH
-+	wiphy->flags |= 0
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
-+		| WIPHY_FLAG_IBSS_RSN
-+		#endif
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+		| WIPHY_FLAG_MESH_AUTH
-+		#endif
-+		;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
-+	wiphy->features |= 0
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
-+		| NL80211_FEATURE_USERSPACE_MPM
-+		#endif
-+		;
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) */
-+#endif /* CONFIG_RTW_MESH */
-+
-+#if defined(CONFIG_RTW_80211K) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 6, 0))
-+	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_RRM);
-+#endif
-+
-+#if (KERNEL_VERSION(3, 8, 0) <= LINUX_VERSION_CODE)
-+	wiphy->features |= NL80211_FEATURE_SAE;
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+#ifdef CONFIG_WIFI_MONITOR
-+	/* Currently only for Monitor debugging */
-+	wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
-+#endif
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) */
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+#ifdef CONFIG_RFKILL_POLL
-+void rtw_cfg80211_init_rfkill(struct wiphy *wiphy)
-+{
-+	wiphy_rfkill_set_hw_state(wiphy, 0);
-+	wiphy_rfkill_start_polling(wiphy);
-+}
-+
-+void rtw_cfg80211_deinit_rfkill(struct wiphy *wiphy)
-+{
-+	wiphy_rfkill_stop_polling(wiphy);
-+}
-+
-+static void cfg80211_rtw_rfkill_poll(struct wiphy *wiphy)
-+{
-+	_adapter *padapter = NULL;
-+	bool blocked = _FALSE;
-+	u8 valid = 0;
-+
-+	padapter = wiphy_to_adapter(wiphy);
-+
-+	if (adapter_to_dvobj(padapter)->processing_dev_remove == _TRUE) {
-+		/*RTW_INFO("cfg80211_rtw_rfkill_poll: device is removed!\n");*/
-+		return;
-+	}
-+
-+	blocked = rtw_hal_rfkill_poll(padapter, &valid);
-+	/*RTW_INFO("cfg80211_rtw_rfkill_poll: valid=%d, blocked=%d\n",
-+			valid, blocked);*/
-+
-+	if (valid)
-+		wiphy_rfkill_set_hw_state(wiphy, blocked);
-+}
-+#endif
-+
-+#if defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
-+#define SURVEY_INFO_TIME			SURVEY_INFO_CHANNEL_TIME
-+#define SURVEY_INFO_TIME_BUSY		SURVEY_INFO_CHANNEL_TIME_BUSY
-+#define SURVEY_INFO_TIME_EXT_BUSY	SURVEY_INFO_CHANNEL_TIME_EXT_BUSY
-+#define SURVEY_INFO_TIME_RX			SURVEY_INFO_CHANNEL_TIME_RX
-+#define SURVEY_INFO_TIME_TX			SURVEY_INFO_CHANNEL_TIME_TX
-+#endif
-+
-+#ifdef CONFIG_RTW_ACS
-+static void rtw_cfg80211_set_survey_info_with_clm(PADAPTER padapter, int idx, struct survey_info *pinfo)
-+{
-+	s8 noise = -50;			/*channel noise in dBm. This and all following fields are optional */
-+	u64 time = SURVEY_TO;	/*amount of time in ms the radio was turn on (on the channel)*/
-+	u64 time_busy = 0;		/*amount of time the primary channel was sensed busy*/
-+	u8 chan = (u8)idx;
-+
-+	if ((idx < 0) || (pinfo == NULL))
-+		return;
-+
-+	pinfo->filled  = SURVEY_INFO_NOISE_DBM
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
-+		| SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY
-+		#endif
-+		;
-+
-+	time_busy = rtw_acs_get_clm_ratio_by_ch_idx(padapter, chan);
-+	noise = rtw_acs_get_nhm_noise_pwr_by_ch_idx(padapter, chan);
-+	/* RTW_INFO("%s: ch-idx:%d time=%llu(ms), time_busy=%llu(ms), noise=%d(dbm)\n", __func__, idx, time, time_busy, noise); */
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
-+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
-+	pinfo->channel_time = time;
-+	pinfo->channel_time_busy = time_busy;
-+	#else
-+	pinfo->time = time;
-+	pinfo->time_busy = time_busy;
-+	#endif
-+#endif
-+	pinfo->noise = noise;
-+}
-+#endif /* CONFIG_RTW_ACS */
-+
-+static int rtw_hostapd_acs_dump_survey(struct wiphy *wiphy, struct net_device *netdev, int idx, struct survey_info *info)
-+{
-+	PADAPTER padapter = (_adapter *)rtw_netdev_priv(netdev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	RT_CHANNEL_INFO *pch_set = rfctl->channel_set;
-+	u8 max_chan_nums = rfctl->max_chan_nums;
-+	u32 freq = 0;
-+	u8 ret = 0;
-+	u16 channel = 0;
-+
-+	if (!netdev || !info) {
-+		RTW_INFO("%s: invial parameters.\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	_rtw_memset(info, 0, sizeof(struct survey_info));
-+	if (padapter->bup == _FALSE) {
-+		RTW_INFO("%s: net device is down.\n", __func__);
-+		return -EIO;
-+	}
-+
-+	if (idx >= max_chan_nums)
-+		return -ENOENT;
-+
-+	channel = pch_set[idx].ChannelNum;
-+	freq = rtw_ch2freq(channel);
-+	info->channel = ieee80211_get_channel(wiphy, freq);
-+	/* RTW_INFO("%s: channel %d, freq %d\n", __func__, channel, freq); */
-+
-+	if (!info->channel)
-+		return -EINVAL;
-+
-+	if (info->channel->flags == IEEE80211_CHAN_DISABLED)
-+		return ret;
-+
-+#ifdef CONFIG_RTW_ACS
-+	rtw_cfg80211_set_survey_info_with_clm(padapter, idx, info);
-+#else
-+	RTW_ERR("%s: unknown acs operation!\n", __func__);
-+#endif
-+
-+	return ret;
-+}
-+#endif /* defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) */
-+
-+#if (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE) \
-+    || defined(CONFIG_KERNEL_PATCH_EXTERNAL_AUTH)
-+int cfg80211_rtw_external_auth(struct wiphy *wiphy, struct net_device *dev,
-+	struct cfg80211_external_auth_params *params)
-+{
-+	PADAPTER padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(dev));
-+
-+	rtw_cfg80211_external_auth_status(wiphy, dev,
-+		(struct rtw_external_auth_params *)params);
-+
-+	return 0;
-+}
-+#endif
-+
-+void rtw_cfg80211_external_auth_status(struct wiphy *wiphy, struct net_device *dev,
-+	struct rtw_external_auth_params *params)
-+{
-+	PADAPTER padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct sta_info	*psta = NULL;
-+	u8 *buf = NULL;
-+	u32 len = 0;
-+	_irqL irqL;
-+
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(dev));
-+
-+	RTW_INFO("SAE: action: %u, status: %u\n", params->action, params->status);
-+	if (params->status == WLAN_STATUS_SUCCESS) {
-+		RTW_INFO("bssid: "MAC_FMT"\n", MAC_ARG(params->bssid));
-+		RTW_INFO("SSID: [%s]\n",
-+			((params->ssid.ssid_len == 0) ? "" : (char *)params->ssid.ssid));
-+		RTW_INFO("suite: 0x%08x\n", params->key_mgmt_suite);
-+	}
-+
-+	psta = rtw_get_stainfo(pstapriv, params->bssid);
-+	if (psta && (params->status == WLAN_STATUS_SUCCESS)) {
-+#ifdef CONFIG_AP_MODE
-+		/* AP mode */
-+		RTW_INFO("station match\n");
-+
-+		psta->state &= ~WIFI_FW_AUTH_NULL;
-+		psta->state |= WIFI_FW_AUTH_SUCCESS;
-+		psta->expire_to = padapter->stapriv.assoc_to;
-+
-+		/* ToDo: Kernel v5.1 pmkid is pointer */
-+		/* RTW_INFO_DUMP("PMKID:", params->pmkid, PMKID_LEN); */
-+		_rtw_set_pmksa(dev, params->bssid, params->pmkid);
-+
-+		_enter_critical_bh(&psta->lock, &irqL);
-+		if ((psta->auth_len != 0) && (psta->pauth_frame != NULL)) {
-+			buf =  rtw_zmalloc(psta->auth_len);
-+			if (buf) {
-+				_rtw_memcpy(buf, psta->pauth_frame, psta->auth_len);
-+				len = psta->auth_len;
-+			}
-+
-+			rtw_mfree(psta->pauth_frame, psta->auth_len);
-+			psta->pauth_frame = NULL;
-+			psta->auth_len = 0;
-+		}
-+		_exit_critical_bh(&psta->lock, &irqL);
-+
-+		if (buf) {
-+			struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
-+			/* send the SAE auth Confirm */
-+
-+			rtw_ps_deny(padapter, PS_DENY_MGNT_TX);
-+			if (_SUCCESS == rtw_pwr_wakeup(padapter)) {
-+				rtw_mi_set_scan_deny(padapter, 1000);
-+				rtw_mi_scan_abort(padapter, _TRUE);
-+
-+				RTW_INFO("SAE: Tx auth Confirm\n");
-+				rtw_mgnt_tx_cmd(padapter, pmlmeext->cur_channel, 1, buf, len, 0, RTW_CMDF_DIRECTLY);
-+
-+			}
-+			rtw_ps_deny_cancel(padapter, PS_DENY_MGNT_TX);
-+
-+			rtw_mfree(buf, len);
-+			buf = NULL;
-+			len = 0;
-+		}
-+#endif
-+	} else {
-+		/* STA mode */
-+		psecuritypriv->extauth_status = params->status;
-+	}
-+}
-+
-+static struct cfg80211_ops rtw_cfg80211_ops = {
-+	.change_virtual_intf = cfg80211_rtw_change_iface,
-+	.add_key = cfg80211_rtw_add_key,
-+	.get_key = cfg80211_rtw_get_key,
-+	.del_key = cfg80211_rtw_del_key,
-+	.set_default_key = cfg80211_rtw_set_default_key,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30))
-+	.set_default_mgmt_key = cfg80211_rtw_set_default_mgmt_key,
-+#endif
-+#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
-+	.set_rekey_data = cfg80211_rtw_set_rekey_data,
-+#endif /*CONFIG_GTK_OL*/
-+	.get_station = cfg80211_rtw_get_station,
-+	.scan = cfg80211_rtw_scan,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 5, 0)) && \
-+    defined(CONFIG_RTW_ABORT_SCAN)
-+	.abort_scan = cfg80211_rtw_abort_scan,
-+#endif
-+	.set_wiphy_params = cfg80211_rtw_set_wiphy_params,
-+	.connect = cfg80211_rtw_connect,
-+	.disconnect = cfg80211_rtw_disconnect,
-+	.join_ibss = cfg80211_rtw_join_ibss,
-+	.leave_ibss = cfg80211_rtw_leave_ibss,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
-+	.set_tx_power = cfg80211_rtw_set_txpower,
-+	.get_tx_power = cfg80211_rtw_get_txpower,
-+#endif
-+	.set_power_mgmt = cfg80211_rtw_set_power_mgmt,
-+	.set_pmksa = cfg80211_rtw_set_pmksa,
-+	.del_pmksa = cfg80211_rtw_del_pmksa,
-+	.flush_pmksa = cfg80211_rtw_flush_pmksa,
-+
-+	.add_virtual_intf = cfg80211_rtw_add_virtual_intf,
-+	.del_virtual_intf = cfg80211_rtw_del_virtual_intf,
-+
-+#ifdef CONFIG_AP_MODE
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE)
-+	.add_beacon = cfg80211_rtw_add_beacon,
-+	.set_beacon = cfg80211_rtw_set_beacon,
-+	.del_beacon = cfg80211_rtw_del_beacon,
-+#else
-+	.start_ap = cfg80211_rtw_start_ap,
-+	.change_beacon = cfg80211_rtw_change_beacon,
-+	.stop_ap = cfg80211_rtw_stop_ap,
-+#endif
-+
-+#if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
-+	.set_mac_acl = cfg80211_rtw_set_mac_acl,
-+#endif
-+
-+	.add_station = cfg80211_rtw_add_station,
-+	.del_station = cfg80211_rtw_del_station,
-+	.change_station = cfg80211_rtw_change_station,
-+	.dump_station = cfg80211_rtw_dump_station,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28))
-+	.change_bss = cfg80211_rtw_change_bss,
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+	.set_txq_params = cfg80211_rtw_set_txq_params,
-+#endif
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
-+	.set_channel = cfg80211_rtw_set_channel,
-+#endif
-+	/* .auth = cfg80211_rtw_auth, */
-+	/* .assoc = cfg80211_rtw_assoc,	 */
-+#endif /* CONFIG_AP_MODE */
-+
-+#if defined(CONFIG_RTW_MESH) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
-+	.get_mesh_config = cfg80211_rtw_get_mesh_config,
-+	.update_mesh_config = cfg80211_rtw_update_mesh_config,
-+	.join_mesh = cfg80211_rtw_join_mesh,
-+	.leave_mesh = cfg80211_rtw_leave_mesh,
-+	.add_mpath = cfg80211_rtw_add_mpath,
-+	.del_mpath = cfg80211_rtw_del_mpath,
-+	.change_mpath = cfg80211_rtw_change_mpath,
-+	.get_mpath = cfg80211_rtw_get_mpath,
-+	.dump_mpath = cfg80211_rtw_dump_mpath,
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
-+	.get_mpp = cfg80211_rtw_get_mpp,
-+	.dump_mpp = cfg80211_rtw_dump_mpp,
-+	#endif
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	.set_monitor_channel = cfg80211_rtw_set_monitor_channel,
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	.get_channel = cfg80211_rtw_get_channel,
-+#endif
-+
-+	.remain_on_channel = cfg80211_rtw_remain_on_channel,
-+	.cancel_remain_on_channel = cfg80211_rtw_cancel_remain_on_channel,
-+
-+#if defined(CONFIG_P2P) && defined(RTW_DEDICATED_P2P_DEVICE)
-+	.start_p2p_device = cfg80211_rtw_start_p2p_device,
-+	.stop_p2p_device = cfg80211_rtw_stop_p2p_device,
-+#endif
-+
-+#ifdef CONFIG_RTW_80211R
-+	.update_ft_ies = cfg80211_rtw_update_ft_ies,
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
-+	.mgmt_tx = cfg80211_rtw_mgmt_tx,
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))
-+	.mgmt_frame_register = cfg80211_rtw_mgmt_frame_register,
-+#else
-+	.update_mgmt_frame_registrations = cfg80211_rtw_update_mgmt_frame_register,
-+#endif
-+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
-+	.action = cfg80211_rtw_mgmt_tx,
-+#endif
-+
-+#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
-+	.tdls_mgmt = cfg80211_rtw_tdls_mgmt,
-+	.tdls_oper = cfg80211_rtw_tdls_oper,
-+#endif /* CONFIG_TDLS */
-+
-+#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+	.sched_scan_start = cfg80211_rtw_sched_scan_start,
-+	.sched_scan_stop = cfg80211_rtw_sched_scan_stop,
-+	.suspend = cfg80211_rtw_suspend,
-+	.resume = cfg80211_rtw_resume,
-+#endif /* CONFIG_PNO_SUPPORT */
-+#ifdef CONFIG_RFKILL_POLL
-+	.rfkill_poll = cfg80211_rtw_rfkill_poll,
-+#endif
-+#if defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))
-+	.dump_survey = rtw_hostapd_acs_dump_survey,
-+#endif
-+#if (KERNEL_VERSION(4, 17, 0) <= LINUX_VERSION_CODE) \
-+    || defined(CONFIG_KERNEL_PATCH_EXTERNAL_AUTH)
-+	.external_auth = cfg80211_rtw_external_auth,
-+#endif
-+};
-+
-+struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev)
-+{
-+	struct wiphy *wiphy;
-+	struct rtw_wiphy_data *wiphy_data;
-+
-+	/* wiphy */
-+	wiphy = wiphy_new(&rtw_cfg80211_ops, sizeof(struct rtw_wiphy_data));
-+	if (!wiphy) {
-+		RTW_ERR("Couldn't allocate wiphy device\n");
-+		goto exit;
-+	}
-+	set_wiphy_dev(wiphy, dev);
-+
-+	/* wiphy_data */
-+	wiphy_data = rtw_wiphy_priv(wiphy);
-+	wiphy_data->dvobj = adapter_to_dvobj(padapter);
-+#ifndef RTW_SINGLE_WIPHY
-+	wiphy_data->adapter = padapter;
-+#endif
-+	wiphy_data->txpwr_total_lmt_mbm = UNSPECIFIED_MBM;
-+	wiphy_data->txpwr_total_target_mbm = UNSPECIFIED_MBM;
-+
-+	if (rtw_cfg80211_init_wiphy(padapter, wiphy) != _SUCCESS) {
-+		rtw_wiphy_free(wiphy);
-+		wiphy = NULL;
-+		goto exit;
-+	}
-+
-+	RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy));
-+
-+exit:
-+	return wiphy;
-+}
-+
-+void rtw_wiphy_free(struct wiphy *wiphy)
-+{
-+	if (!wiphy)
-+		return;
-+
-+	RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy));
-+
-+	if (wiphy->bands[NL80211_BAND_2GHZ]) {
-+		rtw_spt_band_free(wiphy->bands[NL80211_BAND_2GHZ]);
-+		wiphy->bands[NL80211_BAND_2GHZ] = NULL;
-+	}
-+	if (wiphy->bands[NL80211_BAND_5GHZ]) {
-+		rtw_spt_band_free(wiphy->bands[NL80211_BAND_5GHZ]);
-+		wiphy->bands[NL80211_BAND_5GHZ] = NULL;
-+	}
-+
-+	wiphy_free(wiphy);
-+}
-+
-+int rtw_wiphy_register(struct wiphy *wiphy)
-+{
-+	RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy));
-+
-+#if ( (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) \
-+     || defined(RTW_VENDOR_EXT_SUPPORT) )
-+	rtw_cfgvendor_attach(wiphy);
-+#endif
-+
-+	rtw_regd_init(wiphy);
-+
-+	return wiphy_register(wiphy);
-+}
-+
-+void rtw_wiphy_unregister(struct wiphy *wiphy)
-+{
-+	RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy));
-+
-+#if ( (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) \
-+     || defined(RTW_VENDOR_EXT_SUPPORT) )
-+	rtw_cfgvendor_detach(wiphy);
-+#endif
-+
-+	#if defined(RTW_DEDICATED_P2P_DEVICE)
-+	rtw_pd_iface_free(wiphy);
-+	#endif
-+
-+	return wiphy_unregister(wiphy);
-+}
-+
-+int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy)
-+{
-+	int ret = 0;
-+	struct net_device *pnetdev = padapter->pnetdev;
-+	struct wireless_dev *wdev;
-+	struct rtw_wdev_priv *pwdev_priv;
-+
-+	RTW_INFO("%s(padapter=%p)\n", __func__, padapter);
-+
-+	/*  wdev */
-+	wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev));
-+	if (!wdev) {
-+		RTW_INFO("Couldn't allocate wireless device\n");
-+		ret = -ENOMEM;
-+		goto exit;
-+	}
-+	wdev->wiphy = wiphy;
-+	wdev->netdev = pnetdev;
-+	wdev->iftype = NL80211_IFTYPE_STATION;
-+	padapter->rtw_wdev = wdev;
-+	pnetdev->ieee80211_ptr = wdev;
-+
-+	/* init pwdev_priv */
-+	pwdev_priv = adapter_wdev_data(padapter);
-+	pwdev_priv->rtw_wdev = wdev;
-+	pwdev_priv->pmon_ndev = NULL;
-+	pwdev_priv->ifname_mon[0] = '\0';
-+	pwdev_priv->padapter = padapter;
-+	pwdev_priv->scan_request = NULL;
-+	_rtw_spinlock_init(&pwdev_priv->scan_req_lock);
-+	pwdev_priv->connect_req = NULL;
-+	_rtw_spinlock_init(&pwdev_priv->connect_req_lock);
-+
-+	pwdev_priv->p2p_enabled = _FALSE;
-+	pwdev_priv->probe_resp_ie_update_time = rtw_get_current_time();
-+	pwdev_priv->provdisc_req_issued = _FALSE;
-+	rtw_wdev_invit_info_init(&pwdev_priv->invit_info);
-+	rtw_wdev_nego_info_init(&pwdev_priv->nego_info);
-+
-+	pwdev_priv->bandroid_scan = _FALSE;
-+
-+	_rtw_mutex_init(&pwdev_priv->roch_mutex);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	ATOMIC_SET(&pwdev_priv->switch_ch_to, 1);
-+#endif
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
-+        pwdev_priv->rssi_monitor_enable = 0;
-+        pwdev_priv->rssi_monitor_max = 0;
-+        pwdev_priv->rssi_monitor_min = 0;
-+#endif
-+
-+
-+exit:
-+	return ret;
-+}
-+
-+void rtw_wdev_free(struct wireless_dev *wdev)
-+{
-+	if (!wdev)
-+		return;
-+
-+	RTW_INFO("%s(wdev=%p)\n", __func__, wdev);
-+
-+	if (wdev_to_ndev(wdev)) {
-+		_adapter *adapter = (_adapter *)rtw_netdev_priv(wdev_to_ndev(wdev));
-+		struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter);
-+		_irqL irqL;
-+
-+		_rtw_spinlock_free(&wdev_priv->scan_req_lock);
-+
-+		_enter_critical_bh(&wdev_priv->connect_req_lock, &irqL);
-+		rtw_wdev_free_connect_req(wdev_priv);
-+		_exit_critical_bh(&wdev_priv->connect_req_lock, &irqL);
-+		_rtw_spinlock_free(&wdev_priv->connect_req_lock);
-+
-+		_rtw_mutex_free(&wdev_priv->roch_mutex);
-+	}
-+
-+	rtw_mfree((u8 *)wdev, sizeof(struct wireless_dev));
-+}
-+
-+void rtw_wdev_unregister(struct wireless_dev *wdev)
-+{
-+	struct net_device *ndev;
-+	_adapter *adapter;
-+	struct rtw_wdev_priv *pwdev_priv;
-+
-+	if (!wdev)
-+		return;
-+
-+	RTW_INFO("%s(wdev=%p)\n", __func__, wdev);
-+
-+	ndev = wdev_to_ndev(wdev);
-+	if (!ndev)
-+		return;
-+
-+	adapter = (_adapter *)rtw_netdev_priv(ndev);
-+	pwdev_priv = adapter_wdev_data(adapter);
-+
-+	rtw_cfg80211_indicate_scan_done(adapter, _TRUE);
-+
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) || defined(COMPAT_KERNEL_RELEASE)
-+	if (wdev->current_bss) {
-+		RTW_INFO(FUNC_ADPT_FMT" clear current_bss by cfg80211_disconnected\n", FUNC_ADPT_ARG(adapter));
-+		rtw_cfg80211_indicate_disconnect(adapter, 0, 1);
-+	}
-+	#endif
-+
-+	if (pwdev_priv->pmon_ndev) {
-+		RTW_INFO("%s, unregister monitor interface\n", __func__);
-+		unregister_netdev(pwdev_priv->pmon_ndev);
-+	}
-+}
-+
-+int rtw_cfg80211_ndev_res_alloc(_adapter *adapter)
-+{
-+	int ret = _FAIL;
-+
-+#if !defined(RTW_SINGLE_WIPHY)
-+	struct wiphy *wiphy;
-+	struct device *dev = dvobj_to_dev(adapter_to_dvobj(adapter));
-+
-+	wiphy = rtw_wiphy_alloc(adapter, dev);
-+	if (wiphy == NULL)
-+		goto exit;
-+
-+	adapter->wiphy = wiphy;
-+#endif
-+
-+	if (rtw_wdev_alloc(adapter, adapter_to_wiphy(adapter)) == 0)
-+		ret = _SUCCESS;
-+
-+#if !defined(RTW_SINGLE_WIPHY)
-+	if (ret != _SUCCESS) {
-+		rtw_wiphy_free(wiphy);
-+		adapter->wiphy = NULL;
-+	}
-+
-+exit:
-+#endif
-+
-+	return ret;
-+}
-+
-+void rtw_cfg80211_ndev_res_free(_adapter *adapter)
-+{
-+	rtw_wdev_free(adapter->rtw_wdev);
-+	adapter->rtw_wdev = NULL;
-+#if !defined(RTW_SINGLE_WIPHY)
-+	rtw_wiphy_free(adapter_to_wiphy(adapter));
-+	adapter->wiphy = NULL;
-+#endif
-+}
-+
-+
-+int rtw_cfg80211_ndev_res_register(_adapter *adapter)
-+{
-+#if !defined(RTW_SINGLE_WIPHY)
-+	int ret = _FAIL;
-+
-+	if (rtw_wiphy_register(adapter_to_wiphy(adapter)) < 0) {
-+		RTW_INFO("%s rtw_wiphy_register fail for if%d\n", __func__, (adapter->iface_id + 1));
-+		goto exit;
-+	}
-+
-+	#ifdef CONFIG_RFKILL_POLL
-+	rtw_cfg80211_init_rfkill(adapter_to_wiphy(adapter));
-+	#endif
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+#else
-+	return _SUCCESS;
-+#endif
-+}
-+
-+void rtw_cfg80211_ndev_res_unregister(_adapter *adapter)
-+{
-+	rtw_wdev_unregister(adapter->rtw_wdev);
-+}
-+
-+int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj)
-+{
-+	int ret = _FAIL;
-+
-+#if defined(RTW_SINGLE_WIPHY)
-+	struct wiphy *wiphy;
-+	struct device *dev = dvobj_to_dev(dvobj);
-+
-+	wiphy = rtw_wiphy_alloc(dvobj_get_primary_adapter(dvobj), dev);
-+	if (wiphy == NULL)
-+		return ret;
-+
-+	dvobj->wiphy = wiphy;
-+#endif
-+
-+	ret = _SUCCESS;
-+	return ret;
-+}
-+
-+void rtw_cfg80211_dev_res_free(struct dvobj_priv *dvobj)
-+{
-+#if defined(RTW_SINGLE_WIPHY)
-+	rtw_wiphy_free(dvobj_to_wiphy(dvobj));
-+	dvobj->wiphy = NULL;
-+#endif
-+}
-+
-+int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj)
-+{
-+	int ret = _FAIL;
-+
-+#if defined(RTW_SINGLE_WIPHY)
-+	if (rtw_wiphy_register(dvobj_to_wiphy(dvobj)) != 0)
-+		return ret;
-+
-+#ifdef CONFIG_RFKILL_POLL
-+	rtw_cfg80211_init_rfkill(dvobj_to_wiphy(dvobj));
-+#endif
-+#endif
-+
-+	ret = _SUCCESS;
-+
-+	return ret;
-+}
-+
-+void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj)
-+{
-+#if defined(RTW_SINGLE_WIPHY)
-+#ifdef CONFIG_RFKILL_POLL
-+	rtw_cfg80211_deinit_rfkill(dvobj_to_wiphy(dvobj));
-+#endif
-+	rtw_wiphy_unregister(dvobj_to_wiphy(dvobj));
-+#endif
-+}
-+
-+s16 rtw_cfg80211_dev_get_total_txpwr_lmt_mbm(struct dvobj_priv *dvobj)
-+{
-+	struct rtw_wiphy_data *wiphy_data;
-+	s16 mbm = UNSPECIFIED_MBM;
-+
-+	/* TODO: input radio index to choose corresponding wiphy(s) */
-+
-+#if defined(RTW_SINGLE_WIPHY)
-+	wiphy_data = rtw_wiphy_priv(dvobj_to_wiphy(dvobj));
-+	mbm = wiphy_data->txpwr_total_lmt_mbm;
-+#else
-+	struct wiphy *wiphy;
-+	int i;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		if (!dvobj->padapters[i])
-+			continue;
-+		wiphy = dvobj->padapters[i]->wiphy;
-+		if (!wiphy)
-+			continue;
-+		wiphy_data = rtw_wiphy_priv(wiphy);
-+		if (wiphy_data->txpwr_total_lmt_mbm == UNSPECIFIED_MBM)
-+			continue;
-+		if (mbm > wiphy_data->txpwr_total_lmt_mbm)
-+			mbm = wiphy_data->txpwr_total_lmt_mbm;
-+	}
-+#endif
-+
-+	return mbm;
-+}
-+
-+s16 rtw_cfg80211_dev_get_total_txpwr_target_mbm(struct dvobj_priv *dvobj)
-+{
-+	struct rtw_wiphy_data *wiphy_data;
-+	s16 mbm = UNSPECIFIED_MBM;
-+
-+	/* TODO: input radio index to choose corresponding wiphy(s) */
-+
-+#if defined(RTW_SINGLE_WIPHY)
-+	wiphy_data = rtw_wiphy_priv(dvobj_to_wiphy(dvobj));
-+	mbm = wiphy_data->txpwr_total_target_mbm;
-+#else
-+	struct wiphy *wiphy;
-+	int i;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		if (!dvobj->padapters[i])
-+			continue;
-+		wiphy = dvobj->padapters[i]->wiphy;
-+		if (!wiphy)
-+			continue;
-+		wiphy_data = rtw_wiphy_priv(wiphy);
-+		if (wiphy_data->txpwr_total_target_mbm == UNSPECIFIED_MBM)
-+			continue;
-+		if (mbm > wiphy_data->txpwr_total_target_mbm)
-+			mbm = wiphy_data->txpwr_total_target_mbm;
-+	}
-+#endif
-+
-+	return mbm;
-+}
-+#endif /* CONFIG_IOCTL_CFG80211 */
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/ioctl_cfg80211.h b/drivers/staging/rtl8723cs/os_dep/linux/ioctl_cfg80211.h
-new file mode 100644
-index 000000000000..22018caa33fe
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/ioctl_cfg80211.h
-@@ -0,0 +1,454 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __IOCTL_CFG80211_H__
-+#define __IOCTL_CFG80211_H__
-+
-+#define RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT		BIT0
-+#define RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT	BIT1
-+
-+#ifndef RTW_CFG80211_BLOCK_STA_DISCON_EVENT
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0))
-+#define RTW_CFG80211_BLOCK_STA_DISCON_EVENT (RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT)
-+#else
-+#define RTW_CFG80211_BLOCK_STA_DISCON_EVENT (RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT | RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT)
-+#endif
-+#endif
-+
-+#if defined(RTW_USE_CFG80211_STA_EVENT)
-+	#undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
-+#endif
-+
-+#ifndef RTW_P2P_GROUP_INTERFACE
-+	#define RTW_P2P_GROUP_INTERFACE 0
-+#endif
-+
-+/*
-+* (RTW_P2P_GROUP_INTERFACE, RTW_DEDICATED_P2P_DEVICE)
-+* (0, 0): wlan0 + p2p0(PD+PG)
-+* (1, 0): wlan0(with PD) + dynamic PGs
-+* (1, 1): wlan0 (with dynamic PD wdev) + dynamic PGs
-+*/
-+
-+#if RTW_P2P_GROUP_INTERFACE
-+	#ifndef CONFIG_RTW_DYNAMIC_NDEV
-+		#define CONFIG_RTW_DYNAMIC_NDEV
-+	#endif
-+	#ifndef RTW_SINGLE_WIPHY
-+		#define RTW_SINGLE_WIPHY
-+	#endif
-+	#ifndef CONFIG_RADIO_WORK
-+		#define CONFIG_RADIO_WORK
-+	#endif
-+	#ifndef RTW_DEDICATED_P2P_DEVICE
-+		#define RTW_DEDICATED_P2P_DEVICE
-+	#endif
-+#endif
-+
-+#ifndef CONFIG_RADIO_WORK
-+#define RTW_ROCH_DURATION_ENLARGE
-+#define RTW_ROCH_BACK_OP
-+#endif
-+
-+#if !defined(CONFIG_P2P) && RTW_P2P_GROUP_INTERFACE
-+	#error "RTW_P2P_GROUP_INTERFACE can't be enabled when CONFIG_P2P is disabled\n"
-+#endif
-+
-+#if !RTW_P2P_GROUP_INTERFACE && defined(RTW_DEDICATED_P2P_DEVICE)
-+	#error "RTW_DEDICATED_P2P_DEVICE can't be enabled when RTW_P2P_GROUP_INTERFACE is disabled\n"
-+#endif
-+
-+#if defined(RTW_DEDICATED_P2P_DEVICE) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0))
-+	#error "RTW_DEDICATED_P2P_DEVICE can't be enabled when kernel < 3.7.0\n"
-+#endif
-+
-+#ifdef CONFIG_RTW_MESH
-+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
-+		#error "CONFIG_RTW_MESH can't be enabled when kernel < 3.10.0\n"
-+	#endif
-+#endif
-+
-+struct rtw_wdev_invit_info {
-+	u8 state; /* 0: req, 1:rep */
-+	u8 peer_mac[ETH_ALEN];
-+	u8 group_bssid[ETH_ALEN];
-+	u8 active;
-+	u8 token;
-+	u8 flags;
-+	u8 status;
-+	u8 req_op_ch;
-+	u8 rsp_op_ch;
-+};
-+
-+#define rtw_wdev_invit_info_init(invit_info) \
-+	do { \
-+		(invit_info)->state = 0xff; \
-+		_rtw_memset((invit_info)->peer_mac, 0, ETH_ALEN); \
-+		_rtw_memset((invit_info)->group_bssid, 0, ETH_ALEN); \
-+		(invit_info)->active = 0xff; \
-+		(invit_info)->token = 0; \
-+		(invit_info)->flags = 0x00; \
-+		(invit_info)->status = 0xff; \
-+		(invit_info)->req_op_ch = 0; \
-+		(invit_info)->rsp_op_ch = 0; \
-+	} while (0)
-+
-+struct rtw_wdev_nego_info {
-+	u8 state; /* 0: req, 1:rep, 2:conf */
-+	u8 iface_addr[ETH_ALEN];
-+	u8 peer_mac[ETH_ALEN];
-+	u8 peer_iface_addr[ETH_ALEN];
-+	u8 active;
-+	u8 token;
-+	u8 status;
-+	u8 req_intent;
-+	u8 req_op_ch;
-+	u8 req_listen_ch;
-+	u8 rsp_intent;
-+	u8 rsp_op_ch;
-+	u8 conf_op_ch;
-+};
-+
-+#define rtw_wdev_nego_info_init(nego_info) \
-+	do { \
-+		(nego_info)->state = 0xff; \
-+		_rtw_memset((nego_info)->iface_addr, 0, ETH_ALEN); \
-+		_rtw_memset((nego_info)->peer_mac, 0, ETH_ALEN); \
-+		_rtw_memset((nego_info)->peer_iface_addr, 0, ETH_ALEN); \
-+		(nego_info)->active = 0xff; \
-+		(nego_info)->token = 0; \
-+		(nego_info)->status = 0xff; \
-+		(nego_info)->req_intent = 0xff; \
-+		(nego_info)->req_op_ch = 0; \
-+		(nego_info)->req_listen_ch = 0; \
-+		(nego_info)->rsp_intent = 0xff; \
-+		(nego_info)->rsp_op_ch = 0; \
-+		(nego_info)->conf_op_ch = 0; \
-+	} while (0)
-+
-+struct rtw_wdev_priv {
-+	struct wireless_dev *rtw_wdev;
-+
-+	_adapter *padapter;
-+
-+	#if RTW_CFG80211_BLOCK_STA_DISCON_EVENT
-+	u8 not_indic_disco;
-+	#endif
-+
-+	struct cfg80211_scan_request *scan_request;
-+	_lock scan_req_lock;
-+
-+	struct cfg80211_connect_params *connect_req;
-+	_lock connect_req_lock;
-+
-+	struct net_device *pmon_ndev;/* for monitor interface */
-+	char ifname_mon[IFNAMSIZ + 1]; /* interface name for monitor interface */
-+
-+	u8 p2p_enabled;
-+	systime probe_resp_ie_update_time;
-+
-+	u8 provdisc_req_issued;
-+
-+	struct rtw_wdev_invit_info invit_info;
-+	struct rtw_wdev_nego_info nego_info;
-+
-+	u8 bandroid_scan;
-+	bool block;
-+	bool block_scan;
-+
-+	/**
-+	 * mgmt_regs: bitmap of management frame subtypes registered for the
-+	 * 	given interface
-+	 * mcast_mgmt_regs: mcast RX is needed on this interface for these
-+	 * 	subtypes
-+	 */
-+	u32 mgmt_regs;
-+	/* u32 mcast_mgmt_regs; */
-+
-+	u8 is_mgmt_tx;
-+	u16 mgmt_tx_cookie;
-+
-+	_mutex roch_mutex;
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	ATOMIC_T switch_ch_to;
-+#endif
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+	u8 pno_mac_addr[ETH_ALEN];
-+	u16 pno_scan_seq_num;
-+#endif
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
-+        s8 rssi_monitor_max;
-+        s8 rssi_monitor_min;
-+        u8 rssi_monitor_enable;
-+#endif
-+
-+};
-+
-+enum external_auth_action {
-+	EXTERNAL_AUTH_START,
-+	EXTERNAL_AUTH_ABORT,
-+};
-+
-+struct rtw_external_auth_params {
-+	enum external_auth_action action;
-+	u8 bssid[ETH_ALEN]__aligned(2);
-+	struct cfg80211_ssid ssid;
-+	unsigned int key_mgmt_suite;
-+	u16 status;
-+	u8 pmkid[PMKID_LEN];
-+};
-+
-+bool rtw_cfg80211_is_connect_requested(_adapter *adapter);
-+
-+#if RTW_CFG80211_BLOCK_STA_DISCON_EVENT
-+#define rtw_wdev_not_indic_disco(rtw_wdev_data) ((rtw_wdev_data)->not_indic_disco)
-+#define rtw_wdev_set_not_indic_disco(rtw_wdev_data, val) do { (rtw_wdev_data)->not_indic_disco = (val); } while (0)
-+#else
-+#define rtw_wdev_not_indic_disco(rtw_wdev_data) 0
-+#define rtw_wdev_set_not_indic_disco(rtw_wdev_data, val) do {} while (0)
-+#endif
-+
-+#define rtw_wdev_free_connect_req(rtw_wdev_data) \
-+	do { \
-+		if ((rtw_wdev_data)->connect_req) { \
-+			rtw_mfree((u8 *)(rtw_wdev_data)->connect_req, sizeof(*(rtw_wdev_data)->connect_req)); \
-+			(rtw_wdev_data)->connect_req = NULL; \
-+		} \
-+	} while (0)
-+
-+#define wdev_to_ndev(w) ((w)->netdev)
-+#define wdev_to_wiphy(w) ((w)->wiphy)
-+#define ndev_to_wdev(n) ((n)->ieee80211_ptr)
-+
-+struct rtw_wiphy_data {
-+	struct dvobj_priv *dvobj;
-+
-+#ifndef RTW_SINGLE_WIPHY
-+	_adapter *adapter;
-+#endif
-+
-+#if defined(RTW_DEDICATED_P2P_DEVICE)
-+	struct wireless_dev *pd_wdev; /* P2P device wdev */
-+#endif
-+
-+	s16 txpwr_total_lmt_mbm;	/* EIRP */
-+	s16 txpwr_total_target_mbm;	/* EIRP */
-+};
-+
-+#define rtw_wiphy_priv(wiphy) ((struct rtw_wiphy_data *)wiphy_priv(wiphy))
-+#define wiphy_to_dvobj(wiphy) (((struct rtw_wiphy_data *)wiphy_priv(wiphy))->dvobj)
-+#ifdef RTW_SINGLE_WIPHY
-+#define wiphy_to_adapter(wiphy) (dvobj_get_primary_adapter(wiphy_to_dvobj(wiphy)))
-+#else
-+#define wiphy_to_adapter(wiphy) (((struct rtw_wiphy_data *)wiphy_priv(wiphy))->adapter)
-+#endif
-+
-+#if defined(RTW_DEDICATED_P2P_DEVICE)
-+#define wiphy_to_pd_wdev(wiphy) (rtw_wiphy_priv(wiphy)->pd_wdev)
-+#else
-+#define wiphy_to_pd_wdev(wiphy) NULL
-+#endif
-+
-+#define WIPHY_FMT "%s"
-+#define WIPHY_ARG(wiphy) wiphy_name(wiphy)
-+#define FUNC_WIPHY_FMT "%s("WIPHY_FMT")"
-+#define FUNC_WIPHY_ARG(wiphy) __func__, WIPHY_ARG(wiphy)
-+
-+#define SET_CFG80211_MGMT_REGS(w, t) (w |= BIT(t >> 4))
-+#define CLR_CFG80211_MGMT_REGS(w, t) (w &= (~BIT(t >> 4)))
-+#define GET_CFG80211_MGMT_REGS(w, t) ((w & BIT(t >> 4)) > 0)
-+
-+#define SET_CFG80211_REPORT_MGMT(w, t) (SET_CFG80211_MGMT_REGS(w->mgmt_regs, t))
-+#define CLR_CFG80211_REPORT_MGMT(w, t) (CLR_CFG80211_MGMT_REGS(w->mgmt_regs, t))
-+#define GET_CFG80211_REPORT_MGMT(w, t) (GET_CFG80211_MGMT_REGS(w->mgmt_regs, t))
-+
-+struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev);
-+void rtw_wiphy_free(struct wiphy *wiphy);
-+int rtw_wiphy_register(struct wiphy *wiphy);
-+void rtw_wiphy_unregister(struct wiphy *wiphy);
-+
-+int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy);
-+void rtw_wdev_free(struct wireless_dev *wdev);
-+void rtw_wdev_unregister(struct wireless_dev *wdev);
-+
-+int rtw_cfg80211_ndev_res_alloc(_adapter *adapter);
-+void rtw_cfg80211_ndev_res_free(_adapter *adapter);
-+int rtw_cfg80211_ndev_res_register(_adapter *adapter);
-+void rtw_cfg80211_ndev_res_unregister(_adapter *adapter);
-+
-+int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj);
-+void rtw_cfg80211_dev_res_free(struct dvobj_priv *dvobj);
-+int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj);
-+void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj);
-+s16 rtw_cfg80211_dev_get_total_txpwr_lmt_mbm(struct dvobj_priv *dvobj);
-+s16 rtw_cfg80211_dev_get_total_txpwr_target_mbm(struct dvobj_priv *dvobj);
-+
-+void rtw_cfg80211_init_wdev_data(_adapter *padapter);
-+
-+void rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork);
-+void rtw_cfg80211_surveydone_event_callback(_adapter *padapter);
-+struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork);
-+int rtw_cfg80211_check_bss(_adapter *padapter);
-+void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter);
-+void rtw_cfg80211_indicate_connect(_adapter *padapter);
-+void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated);
-+void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted);
-+u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+u8 rtw_cfg80211_scan_via_buddy(_adapter *padapter, struct cfg80211_scan_request *request);
-+void rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_aborted);
-+#endif
-+
-+#ifdef CONFIG_AP_MODE
-+void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len);
-+void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason);
-+int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type);
-+#endif /* CONFIG_AP_MODE */
-+
-+void rtw_cfg80211_set_is_roch(_adapter *adapter, bool val);
-+bool rtw_cfg80211_get_is_roch(_adapter *adapter);
-+bool rtw_cfg80211_is_ro_ch_once(_adapter *adapter);
-+void rtw_cfg80211_set_last_ro_ch_time(_adapter *adapter);
-+s32 rtw_cfg80211_get_last_ro_ch_passing_ms(_adapter *adapter);
-+
-+#ifdef CONFIG_P2P
-+int rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter);
-+int rtw_cfg80211_is_p2p_scan(_adapter *adapter);
-+#if defined(RTW_DEDICATED_P2P_DEVICE)
-+int rtw_cfg80211_redirect_pd_wdev(struct wiphy *wiphy, u8 *ra, struct wireless_dev **wdev);
-+int rtw_cfg80211_is_scan_by_pd_wdev(_adapter *adapter);
-+int rtw_pd_iface_alloc(struct wiphy *wiphy, const char *name, struct wireless_dev **pd_wdev);
-+void rtw_pd_iface_free(struct wiphy *wiphy);
-+#endif
-+#endif /* CONFIG_P2P */
-+
-+void rtw_cfg80211_set_is_mgmt_tx(_adapter *adapter, u8 val);
-+u8 rtw_cfg80211_get_is_mgmt_tx(_adapter *adapter);
-+u8 rtw_mgnt_tx_handler(_adapter *adapter, u8 *buf);
-+
-+void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len);
-+
-+void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, union recv_frame *rframe);
-+void rtw_cfg80211_rx_action_p2p(_adapter *padapter, union recv_frame *rframe);
-+void rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const char *msg);
-+void rtw_cfg80211_rx_mframe(_adapter *adapter, union recv_frame *rframe, const char *msg);
-+void rtw_cfg80211_rx_probe_request(_adapter *padapter, union recv_frame *rframe);
-+
-+void rtw_cfg80211_external_auth_request(_adapter *padapter, union recv_frame *rframe);
-+void rtw_cfg80211_external_auth_status(struct wiphy *wiphy, struct net_device *dev,
-+	struct rtw_external_auth_params *params);
-+
-+bool rtw_cfg80211_pwr_mgmt(_adapter *adapter);
-+#ifdef CONFIG_RTW_80211K
-+void rtw_cfg80211_rx_rrm_action(_adapter *adapter, union recv_frame *rframe);
-+#endif
-+
-+#ifdef CONFIG_RFKILL_POLL
-+void rtw_cfg80211_init_rfkill(struct wiphy *wiphy);
-+void rtw_cfg80211_deinit_rfkill(struct wiphy *wiphy);
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))  && !defined(COMPAT_KERNEL_RELEASE)
-+#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev_to_ndev(wdev), freq, buf, len, gfp)
-+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
-+#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev_to_ndev(wdev), freq, sig_dbm, buf, len, gfp)
-+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 12, 0))
-+#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp)
-+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3 , 18 , 0))
-+#define rtw_cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , 0 , gfp)
-+#else
-+#define rtw_cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt(wdev , freq , sig_dbm , buf , len , 0)
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))  && !defined(COMPAT_KERNEL_RELEASE)
-+#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, buf, len)
-+#else
-+#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, bss, buf, len)
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
-+#define rtw_cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status(wdev_to_ndev(wdev), cookie, buf, len, ack, gfp)
-+#else
-+#define rtw_cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status(wdev, cookie, buf, len, ack, gfp)
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0))
-+#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)  cfg80211_ready_on_channel(wdev_to_ndev(wdev), cookie, chan, channel_type, duration, gfp)
-+#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev_to_ndev(wdev), cookie, chan, chan_type, gfp)
-+#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0))
-+#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)  cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)
-+#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp)
-+#else
-+#define rtw_cfg80211_ready_on_channel(wdev, cookie, chan, channel_type, duration, gfp)  cfg80211_ready_on_channel(wdev, cookie, chan, duration, gfp)
-+#define rtw_cfg80211_remain_on_channel_expired(wdev, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired(wdev, cookie, chan, gfp)
-+#endif
-+
-+#define rtw_cfg80211_connect_result(wdev, bssid, req_ie, req_ie_len, resp_ie, resp_ie_len, status, gfp) cfg80211_connect_result(wdev_to_ndev(wdev), bssid, req_ie, req_ie_len, resp_ie, resp_ie_len, status, gfp)
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0))
-+#define rtw_cfg80211_disconnected(wdev, reason, ie, ie_len, locally_generated, gfp) cfg80211_disconnected(wdev_to_ndev(wdev), reason, ie, ie_len, gfp)
-+#else
-+#define rtw_cfg80211_disconnected(wdev, reason, ie, ie_len, locally_generated, gfp) cfg80211_disconnected(wdev_to_ndev(wdev), reason, ie, ie_len, locally_generated, gfp)
-+#endif
-+
-+#ifdef CONFIG_RTW_80211R
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
-+#define rtw_cfg80211_ft_event(adapter, parm)  cfg80211_ft_event((adapter)->pnetdev, parm)
-+#else
-+	#error "Cannot support FT for KERNEL_VERSION < 3.10\n"
-+#endif
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))
-+#define rtw_cfg80211_notify_new_peer_candidate(wdev, addr, ie, ie_len, sig_dbm, gfp) cfg80211_notify_new_peer_candidate(wdev_to_ndev(wdev), addr, ie, ie_len, sig_dbm, gfp)
-+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
-+#define rtw_cfg80211_notify_new_peer_candidate(wdev, addr, ie, ie_len, sig_dbm, gfp) cfg80211_notify_new_peer_candidate(wdev_to_ndev(wdev), addr, ie, ie_len, gfp)
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
-+u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, u8 ht, bool started);
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 31))
-+#define IEEE80211_CHAN_NO_HT40PLUS IEEE80211_CHAN_NO_FAT_ABOVE
-+#define IEEE80211_CHAN_NO_HT40MINUS IEEE80211_CHAN_NO_FAT_BELOW
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0))
-+#define NL80211_BAND_2GHZ IEEE80211_BAND_2GHZ
-+#define NL80211_BAND_5GHZ IEEE80211_BAND_5GHZ
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+#define NL80211_BAND_60GHZ IEEE80211_BAND_60GHZ
-+#endif
-+#define NUM_NL80211_BANDS IEEE80211_NUM_BANDS
-+#endif
-+
-+#define rtw_band_to_nl80211_band(band) \
-+	(band == BAND_ON_2_4G) ? NL80211_BAND_2GHZ : \
-+	(band == BAND_ON_5G) ? NL80211_BAND_5GHZ : NUM_NL80211_BANDS
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36))
-+#define NL80211_TX_POWER_AUTOMATIC	TX_POWER_AUTOMATIC
-+#define NL80211_TX_POWER_LIMITED	TX_POWER_LIMITED
-+#define NL80211_TX_POWER_FIXED		TX_POWER_FIXED
-+#endif
-+
-+#include "wifi_regd.h"
-+#include "rtw_cfgvendor.h"
-+
-+#endif /* __IOCTL_CFG80211_H__ */
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/ioctl_linux.c b/drivers/staging/rtl8723cs/os_dep/linux/ioctl_linux.c
-new file mode 100644
-index 000000000000..afce78422aa8
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/ioctl_linux.c
-@@ -0,0 +1,13049 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _IOCTL_LINUX_C_
-+
-+#include <drv_types.h>
-+#include <rtw_mp.h>
-+#include "../../hal/phydm/phydm_precomp.h"
-+#ifdef RTW_HALMAC
-+#include "../../hal/hal_halmac.h"
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27))
-+#define  iwe_stream_add_event(a, b, c, d, e)  iwe_stream_add_event(b, c, d, e)
-+#define  iwe_stream_add_point(a, b, c, d, e)  iwe_stream_add_point(b, c, d, e)
-+#endif
-+
-+#ifdef CONFIG_80211N_HT
-+extern int rtw_ht_enable;
-+#endif
-+
-+
-+
-+#define RTL_IOCTL_WPA_SUPPLICANT	(SIOCIWFIRSTPRIV+30)
-+
-+#define SCAN_ITEM_SIZE 768
-+#define MAX_CUSTOM_LEN 64
-+#define RATE_COUNT 4
-+#define MAX_SCAN_BUFFER_LEN 65535
-+
-+#ifdef CONFIG_GLOBAL_UI_PID
-+extern int ui_pid[3];
-+#endif
-+
-+/* combo scan */
-+#define WEXT_CSCAN_AMOUNT 9
-+#define WEXT_CSCAN_BUF_LEN		360
-+#define WEXT_CSCAN_HEADER		"CSCAN S\x01\x00\x00S\x00"
-+#define WEXT_CSCAN_HEADER_SIZE		12
-+#define WEXT_CSCAN_SSID_SECTION		'S'
-+#define WEXT_CSCAN_CHANNEL_SECTION	'C'
-+#define WEXT_CSCAN_NPROBE_SECTION	'N'
-+#define WEXT_CSCAN_ACTV_DWELL_SECTION	'A'
-+#define WEXT_CSCAN_PASV_DWELL_SECTION	'P'
-+#define WEXT_CSCAN_HOME_DWELL_SECTION	'H'
-+#define WEXT_CSCAN_TYPE_SECTION		'T'
-+
-+
-+extern u8 key_2char2num(u8 hch, u8 lch);
-+extern u8 str_2char2num(u8 hch, u8 lch);
-+extern void macstr2num(u8 *dst, u8 *src);
-+extern u8 convert_ip_addr(u8 hch, u8 mch, u8 lch);
-+
-+u32 rtw_rates[] = {1000000, 2000000, 5500000, 11000000,
-+	6000000, 9000000, 12000000, 18000000, 24000000, 36000000, 48000000, 54000000};
-+
-+#ifdef CONFIG_RTW_ANDROID
-+static void indicate_wx_custom_event(_adapter *padapter, char *msg)
-+{
-+	u8 *buff;
-+	union iwreq_data wrqu;
-+
-+	if (strlen(msg) > IW_CUSTOM_MAX) {
-+		RTW_INFO("%s strlen(msg):%zu > IW_CUSTOM_MAX:%u\n", __FUNCTION__ , strlen(msg), IW_CUSTOM_MAX);
-+		return;
-+	}
-+
-+	buff = rtw_zmalloc(IW_CUSTOM_MAX + 1);
-+	if (!buff)
-+		return;
-+
-+	_rtw_memcpy(buff, msg, strlen(msg));
-+
-+	_rtw_memset(&wrqu, 0, sizeof(wrqu));
-+	wrqu.data.length = strlen(msg);
-+
-+	RTW_INFO("%s %s\n", __FUNCTION__, buff);
-+#ifndef CONFIG_IOCTL_CFG80211
-+	wireless_send_event(padapter->pnetdev, IWEVCUSTOM, &wrqu, buff);
-+#endif
-+
-+	rtw_mfree(buff, IW_CUSTOM_MAX + 1);
-+
-+}
-+#endif
-+
-+#if 0
-+static void request_wps_pbc_event(_adapter *padapter)
-+{
-+	u8 *buff, *p;
-+	union iwreq_data wrqu;
-+
-+
-+	buff = rtw_malloc(IW_CUSTOM_MAX);
-+	if (!buff)
-+		return;
-+
-+	_rtw_memset(buff, 0, IW_CUSTOM_MAX);
-+
-+	p = buff;
-+
-+	p += sprintf(p, "WPS_PBC_START.request=TRUE");
-+
-+	_rtw_memset(&wrqu, 0, sizeof(wrqu));
-+
-+	wrqu.data.length = p - buff;
-+
-+	wrqu.data.length = (wrqu.data.length < IW_CUSTOM_MAX) ? wrqu.data.length : IW_CUSTOM_MAX;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+#ifndef CONFIG_IOCTL_CFG80211
-+	wireless_send_event(padapter->pnetdev, IWEVCUSTOM, &wrqu, buff);
-+#endif
-+
-+	if (buff)
-+		rtw_mfree(buff, IW_CUSTOM_MAX);
-+
-+}
-+#endif
-+
-+#ifdef CONFIG_SUPPORT_HW_WPS_PBC
-+void rtw_request_wps_pbc_event(_adapter *padapter)
-+{
-+#ifdef RTK_DMP_PLATFORM
-+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))
-+	kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_NET_PBC);
-+#else
-+	kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_NET_PBC);
-+#endif
-+#else
-+
-+	if (padapter->pid[0] == 0) {
-+		/*	0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver. */
-+		return;
-+	}
-+
-+	rtw_signal_process(padapter->pid[0], SIGUSR1);
-+
-+#endif
-+
-+	rtw_led_control(padapter, LED_CTL_START_WPS_BOTTON);
-+}
-+#endif/* #ifdef CONFIG_SUPPORT_HW_WPS_PBC */
-+
-+void indicate_wx_scan_complete_event(_adapter *padapter)
-+{
-+	union iwreq_data wrqu;
-+
-+	_rtw_memset(&wrqu, 0, sizeof(union iwreq_data));
-+
-+	/* RTW_INFO("+rtw_indicate_wx_scan_complete_event\n"); */
-+#ifndef CONFIG_IOCTL_CFG80211
-+	wireless_send_event(padapter->pnetdev, SIOCGIWSCAN, &wrqu, NULL);
-+#endif
-+}
-+
-+
-+void rtw_indicate_wx_assoc_event(_adapter *padapter)
-+{
-+	union iwreq_data wrqu;
-+	struct	mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	WLAN_BSSID_EX		*pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
-+
-+	_rtw_memset(&wrqu, 0, sizeof(union iwreq_data));
-+
-+	wrqu.ap_addr.sa_family = ARPHRD_ETHER;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)
-+		_rtw_memcpy(wrqu.ap_addr.sa_data, pnetwork->MacAddress, ETH_ALEN);
-+	else
-+		_rtw_memcpy(wrqu.ap_addr.sa_data, pmlmepriv->cur_network.network.MacAddress, ETH_ALEN);
-+
-+	RTW_PRINT("assoc success\n");
-+#ifndef CONFIG_IOCTL_CFG80211
-+	wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL);
-+#endif
-+}
-+
-+void rtw_indicate_wx_disassoc_event(_adapter *padapter)
-+{
-+	union iwreq_data wrqu;
-+
-+	_rtw_memset(&wrqu, 0, sizeof(union iwreq_data));
-+
-+	wrqu.ap_addr.sa_family = ARPHRD_ETHER;
-+	_rtw_memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN);
-+
-+#ifndef CONFIG_IOCTL_CFG80211
-+	RTW_PRINT("indicate disassoc\n");
-+	wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL);
-+#endif
-+}
-+
-+/*
-+uint	rtw_is_cckrates_included(u8 *rate)
-+{
-+		u32	i = 0;
-+
-+		while(rate[i]!=0)
-+		{
-+			if  (  (((rate[i]) & 0x7f) == 2)	|| (((rate[i]) & 0x7f) == 4) ||
-+			(((rate[i]) & 0x7f) == 11)  || (((rate[i]) & 0x7f) == 22) )
-+			return _TRUE;
-+			i++;
-+		}
-+
-+		return _FALSE;
-+}
-+
-+uint	rtw_is_cckratesonly_included(u8 *rate)
-+{
-+	u32 i = 0;
-+
-+	while(rate[i]!=0)
-+	{
-+			if  (  (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) &&
-+				(((rate[i]) & 0x7f) != 11)  && (((rate[i]) & 0x7f) != 22) )
-+			return _FALSE;
-+			i++;
-+	}
-+
-+	return _TRUE;
-+}
-+*/
-+
-+#ifdef CONFIG_IOCTL_WEXT
-+static int search_p2p_wfd_ie(_adapter *padapter,
-+		struct iw_request_info *info, struct wlan_network *pnetwork,
-+		char *start, char *stop)
-+{
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
-+#ifdef CONFIG_WFD
-+	if (SCAN_RESULT_ALL == pwdinfo->wfd_info->scan_result_type) {
-+
-+	} else if ((SCAN_RESULT_P2P_ONLY == pwdinfo->wfd_info->scan_result_type) ||
-+		(SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type))
-+#endif /* CONFIG_WFD */
-+	{
-+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
-+			u32	blnGotP2PIE = _FALSE;
-+
-+			/*	User is doing the P2P device discovery */
-+			/*	The prefix of SSID should be "DIRECT-" and the IE should contains the P2P IE. */
-+			/*	If not, the driver should ignore this AP and go to the next AP. */
-+
-+			/*	Verifying the SSID */
-+			if (_rtw_memcmp(pnetwork->network.Ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN)) {
-+				u32	p2pielen = 0;
-+
-+				/*	Verifying the P2P IE */
-+				if (rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen))
-+					blnGotP2PIE = _TRUE;
-+			}
-+
-+			if (blnGotP2PIE == _FALSE)
-+				return _FALSE;
-+
-+		}
-+	}
-+
-+#ifdef CONFIG_WFD
-+	if (SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type) {
-+		u32	blnGotWFD = _FALSE;
-+		u8 *wfd_ie;
-+		uint wfd_ielen = 0;
-+
-+		wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);
-+		if (wfd_ie) {
-+			u8 *wfd_devinfo;
-+			uint wfd_devlen;
-+
-+			wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);
-+			if (wfd_devinfo) {
-+				if (pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_PSINK) {
-+					/*	the first two bits will indicate the WFD device type */
-+					if ((wfd_devinfo[1] & 0x03) == WFD_DEVINFO_SOURCE) {
-+						/*	If this device is Miracast PSink device, the scan reuslt should just provide the Miracast source. */
-+						blnGotWFD = _TRUE;
-+					}
-+				} else if (pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_SOURCE) {
-+					/*	the first two bits will indicate the WFD device type */
-+					if ((wfd_devinfo[1] & 0x03) == WFD_DEVINFO_PSINK) {
-+						/*	If this device is Miracast source device, the scan reuslt should just provide the Miracast PSink. */
-+						/*	Todo: How about the SSink?! */
-+						blnGotWFD = _TRUE;
-+					}
-+				}
-+			}
-+		}
-+
-+		if (blnGotWFD == _FALSE)
-+			return _FALSE;
-+	}
-+#endif /* CONFIG_WFD */
-+
-+#endif /* CONFIG_P2P */
-+	return _TRUE;
-+}
-+static inline char *iwe_stream_mac_addr_proess(_adapter *padapter,
-+		struct iw_request_info *info, struct wlan_network *pnetwork,
-+		char *start, char *stop, struct iw_event *iwe)
-+{
-+	/*  AP MAC address */
-+	iwe->cmd = SIOCGIWAP;
-+	iwe->u.ap_addr.sa_family = ARPHRD_ETHER;
-+
-+	_rtw_memcpy(iwe->u.ap_addr.sa_data, pnetwork->network.MacAddress, ETH_ALEN);
-+	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_ADDR_LEN);
-+	return start;
-+}
-+static inline char *iwe_stream_essid_proess(_adapter *padapter,
-+		struct iw_request_info *info, struct wlan_network *pnetwork,
-+		char *start, char *stop, struct iw_event *iwe)
-+{
-+
-+	/* Add the ESSID */
-+	iwe->cmd = SIOCGIWESSID;
-+	iwe->u.data.flags = 1;
-+	iwe->u.data.length = min((u16)pnetwork->network.Ssid.SsidLength, (u16)32);
-+	start = iwe_stream_add_point(info, start, stop, iwe, pnetwork->network.Ssid.Ssid);
-+	return start;
-+}
-+
-+static inline char *iwe_stream_chan_process(_adapter *padapter,
-+		struct iw_request_info *info, struct wlan_network *pnetwork,
-+		char *start, char *stop, struct iw_event *iwe)
-+{
-+	if (pnetwork->network.Configuration.DSConfig < 1 /*|| pnetwork->network.Configuration.DSConfig>14*/)
-+		pnetwork->network.Configuration.DSConfig = 1;
-+
-+	/* Add frequency/channel */
-+	iwe->cmd = SIOCGIWFREQ;
-+	iwe->u.freq.m = rtw_ch2freq(pnetwork->network.Configuration.DSConfig) * 100000;
-+	iwe->u.freq.e = 1;
-+	iwe->u.freq.i = pnetwork->network.Configuration.DSConfig;
-+	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_FREQ_LEN);
-+	return start;
-+}
-+static inline char *iwe_stream_mode_process(_adapter *padapter,
-+		struct iw_request_info *info, struct wlan_network *pnetwork,
-+		char *start, char *stop, struct iw_event *iwe, u16 cap)
-+{
-+	/* Add mode */
-+	if (cap & (WLAN_CAPABILITY_IBSS | WLAN_CAPABILITY_BSS)) {
-+		iwe->cmd = SIOCGIWMODE;
-+		if (cap & WLAN_CAPABILITY_BSS)
-+			iwe->u.mode = IW_MODE_MASTER;
-+		else
-+			iwe->u.mode = IW_MODE_ADHOC;
-+
-+		start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_UINT_LEN);
-+	}
-+	return start;
-+}
-+static inline char *iwe_stream_encryption_process(_adapter *padapter,
-+		struct iw_request_info *info, struct wlan_network *pnetwork,
-+		char *start, char *stop, struct iw_event *iwe, u16 cap)
-+{
-+
-+	/* Add encryption capability */
-+	iwe->cmd = SIOCGIWENCODE;
-+	if (cap & WLAN_CAPABILITY_PRIVACY)
-+		iwe->u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
-+	else
-+		iwe->u.data.flags = IW_ENCODE_DISABLED;
-+	iwe->u.data.length = 0;
-+	start = iwe_stream_add_point(info, start, stop, iwe, pnetwork->network.Ssid.Ssid);
-+	return start;
-+
-+}
-+
-+static inline char *iwe_stream_protocol_process(_adapter *padapter,
-+		struct iw_request_info *info, struct wlan_network *pnetwork,
-+		char *start, char *stop, struct iw_event *iwe)
-+{
-+	u16 ht_cap = _FALSE, vht_cap = _FALSE;
-+	u32 ht_ielen = 0, vht_ielen = 0;
-+	char *p;
-+	u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); /* Probe Request	 */
-+
-+#ifdef CONFIG_80211N_HT
-+	/* parsing HT_CAP_IE	 */
-+	if(padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) {
-+		p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset);
-+		if (p && ht_ielen > 0)
-+			ht_cap = _TRUE;
-+	}
-+#endif
-+
-+#ifdef CONFIG_80211AC_VHT
-+	/* parsing VHT_CAP_IE */
-+	if(padapter->registrypriv.wireless_mode & WIRELESS_11AC) {
-+		p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset);
-+		if (p && vht_ielen > 0)
-+			vht_cap = _TRUE;
-+	}
-+#endif
-+	/* Add the protocol name */
-+	iwe->cmd = SIOCGIWNAME;
-+	if ((rtw_is_cckratesonly_included((u8 *)&pnetwork->network.SupportedRates)) == _TRUE) {
-+		if (ht_cap == _TRUE)
-+			snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bn");
-+		else
-+			snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11b");
-+	} else if ((rtw_is_cckrates_included((u8 *)&pnetwork->network.SupportedRates)) == _TRUE) {
-+		if (ht_cap == _TRUE)
-+			snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bgn");
-+		else
-+			snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bg");
-+	} else {
-+		if (pnetwork->network.Configuration.DSConfig > 14) {
-+			#ifdef CONFIG_80211AC_VHT
-+			if (vht_cap == _TRUE)
-+				snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11AC");
-+			else
-+			#endif
-+			{
-+				if (ht_cap == _TRUE)
-+					snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11an");
-+				else
-+					snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11a");
-+			}
-+		} else {
-+			if (ht_cap == _TRUE)
-+				snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11gn");
-+			else
-+				snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11g");
-+		}
-+	}
-+	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_CHAR_LEN);
-+	return start;
-+}
-+
-+static inline char *iwe_stream_rate_process(_adapter *padapter,
-+		struct iw_request_info *info, struct wlan_network *pnetwork,
-+		char *start, char *stop, struct iw_event *iwe)
-+{
-+	u32 ht_ielen = 0, vht_ielen = 0;
-+	char *p;
-+	u16 max_rate = 0, rate, ht_cap = _FALSE, vht_cap = _FALSE;
-+	u32 i = 0;
-+	u8 bw_40MHz = 0, short_GI = 0, bw_160MHz = 0, vht_highest_rate = 0;
-+	u16 mcs_rate = 0, vht_data_rate = 0;
-+	char custom[MAX_CUSTOM_LEN] = {0};
-+	u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); /* Probe Request	 */
-+
-+	/* parsing HT_CAP_IE	 */
-+	if(is_supported_ht(padapter->registrypriv.wireless_mode)) {
-+		p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset);
-+		if (p && ht_ielen > 0) {
-+			struct rtw_ieee80211_ht_cap *pht_capie;
-+			ht_cap = _TRUE;
-+			pht_capie = (struct rtw_ieee80211_ht_cap *)(p + 2);
-+			_rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2);
-+			bw_40MHz = (pht_capie->cap_info & IEEE80211_HT_CAP_SUP_WIDTH) ? 1 : 0;
-+			short_GI = (pht_capie->cap_info & (IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40)) ? 1 : 0;
-+		}
-+	}
-+#ifdef CONFIG_80211AC_VHT
-+	/* parsing VHT_CAP_IE */
-+	if(padapter->registrypriv.wireless_mode & WIRELESS_11AC){
-+		p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset);
-+		if (p && vht_ielen > 0) {
-+			u8	mcs_map[2];
-+
-+			vht_cap = _TRUE;
-+			bw_160MHz = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p + 2);
-+			if (bw_160MHz)
-+				short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI160M(p + 2);
-+			else
-+				short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI80M(p + 2);
-+
-+			_rtw_memcpy(mcs_map, GET_VHT_CAPABILITY_ELE_TX_MCS(p + 2), 2);
-+
-+			vht_highest_rate = rtw_get_vht_highest_rate(mcs_map);
-+			vht_data_rate = rtw_vht_mcs_to_data_rate(CHANNEL_WIDTH_80, short_GI, vht_highest_rate);
-+		}
-+	}
-+#endif
-+
-+	/*Add basic and extended rates */
-+	p = custom;
-+	p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), " Rates (Mb/s): ");
-+	while (pnetwork->network.SupportedRates[i] != 0) {
-+		rate = pnetwork->network.SupportedRates[i] & 0x7F;
-+		if (rate > max_rate)
-+			max_rate = rate;
-+		p += snprintf(p, MAX_CUSTOM_LEN - (p - custom),
-+			      "%d%s ", rate >> 1, (rate & 1) ? ".5" : "");
-+		i++;
-+	}
-+#ifdef CONFIG_80211AC_VHT
-+	if (vht_cap == _TRUE)
-+		max_rate = vht_data_rate;
-+	else
-+#endif
-+		if (ht_cap == _TRUE) {
-+			if (mcs_rate & 0x8000) /* MCS15 */
-+				max_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130);
-+
-+			else if (mcs_rate & 0x0080) /* MCS7 */
-+				max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65);
-+			else { /* default MCS7 */
-+				/* RTW_INFO("wx_get_scan, mcs_rate_bitmap=0x%x\n", mcs_rate); */
-+				max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65);
-+			}
-+
-+			max_rate = max_rate * 2; /* Mbps/2;		 */
-+		}
-+
-+	iwe->cmd = SIOCGIWRATE;
-+	iwe->u.bitrate.fixed = iwe->u.bitrate.disabled = 0;
-+	iwe->u.bitrate.value = max_rate * 500000;
-+	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_PARAM_LEN);
-+	return start ;
-+}
-+
-+static inline char *iwe_stream_wpa_wpa2_process(_adapter *padapter,
-+		struct iw_request_info *info, struct wlan_network *pnetwork,
-+		char *start, char *stop, struct iw_event *iwe)
-+{
-+	int buf_size = MAX_WPA_IE_LEN * 2;
-+	/* u8 pbuf[buf_size]={0};	 */
-+	u8 *pbuf = rtw_zmalloc(buf_size);
-+
-+	u8 wpa_ie[255] = {0}, rsn_ie[255] = {0};
-+	u16 i, wpa_len = 0, rsn_len = 0;
-+	u8 *p;
-+	sint out_len = 0;
-+
-+
-+	if (pbuf) {
-+		p = pbuf;
-+
-+		/* parsing WPA/WPA2 IE */
-+		if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ) { /* Probe Request */
-+			out_len = rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, rsn_ie, &rsn_len, wpa_ie, &wpa_len);
-+
-+			if (wpa_len > 0) {
-+
-+				_rtw_memset(pbuf, 0, buf_size);
-+				p += sprintf(p, "wpa_ie=");
-+				for (i = 0; i < wpa_len; i++)
-+					p += sprintf(p, "%02x", wpa_ie[i]);
-+
-+				if (wpa_len > 100) {
-+					printk("-----------------Len %d----------------\n", wpa_len);
-+					for (i = 0; i < wpa_len; i++)
-+						printk("%02x ", wpa_ie[i]);
-+					printk("\n");
-+					printk("-----------------Len %d----------------\n", wpa_len);
-+				}
-+
-+				_rtw_memset(iwe, 0, sizeof(*iwe));
-+				iwe->cmd = IWEVCUSTOM;
-+				iwe->u.data.length = strlen(pbuf);
-+				start = iwe_stream_add_point(info, start, stop, iwe, pbuf);
-+
-+				_rtw_memset(iwe, 0, sizeof(*iwe));
-+				iwe->cmd = IWEVGENIE;
-+				iwe->u.data.length = wpa_len;
-+				start = iwe_stream_add_point(info, start, stop, iwe, wpa_ie);
-+			}
-+			if (rsn_len > 0) {
-+
-+				_rtw_memset(pbuf, 0, buf_size);
-+				p += sprintf(p, "rsn_ie=");
-+				for (i = 0; i < rsn_len; i++)
-+					p += sprintf(p, "%02x", rsn_ie[i]);
-+				_rtw_memset(iwe, 0, sizeof(*iwe));
-+				iwe->cmd = IWEVCUSTOM;
-+				iwe->u.data.length = strlen(pbuf);
-+				start = iwe_stream_add_point(info, start, stop, iwe, pbuf);
-+
-+				_rtw_memset(iwe, 0, sizeof(*iwe));
-+				iwe->cmd = IWEVGENIE;
-+				iwe->u.data.length = rsn_len;
-+				start = iwe_stream_add_point(info, start, stop, iwe, rsn_ie);
-+			}
-+		}
-+
-+		rtw_mfree(pbuf, buf_size);
-+	}
-+	return start;
-+}
-+
-+static inline char *iwe_stream_wps_process(_adapter *padapter,
-+		struct iw_request_info *info, struct wlan_network *pnetwork,
-+		char *start, char *stop, struct iw_event *iwe)
-+{
-+	/* parsing WPS IE */
-+	uint cnt = 0, total_ielen;
-+	u8 *wpsie_ptr = NULL;
-+	uint wps_ielen = 0;
-+	u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12);
-+
-+	u8 *ie_ptr = pnetwork->network.IEs + ie_offset;
-+	total_ielen = pnetwork->network.IELength - ie_offset;
-+
-+	if (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ) { /* Probe Request */
-+		ie_ptr = pnetwork->network.IEs;
-+		total_ielen = pnetwork->network.IELength;
-+	} else { /* Beacon or Probe Respones */
-+		ie_ptr = pnetwork->network.IEs + _FIXED_IE_LENGTH_;
-+		total_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_;
-+	}
-+	while (cnt < total_ielen) {
-+		if (rtw_is_wps_ie(&ie_ptr[cnt], &wps_ielen) && (wps_ielen > 2)) {
-+			wpsie_ptr = &ie_ptr[cnt];
-+			iwe->cmd = IWEVGENIE;
-+			iwe->u.data.length = (u16)wps_ielen;
-+			start = iwe_stream_add_point(info, start, stop, iwe, wpsie_ptr);
-+		}
-+		cnt += ie_ptr[cnt + 1] + 2; /* goto next */
-+	}
-+	return start;
-+}
-+
-+static inline char *iwe_stream_wapi_process(_adapter *padapter,
-+		struct iw_request_info *info, struct wlan_network *pnetwork,
-+		char *start, char *stop, struct iw_event *iwe)
-+{
-+#ifdef CONFIG_WAPI_SUPPORT
-+	char *p;
-+
-+	if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ) { /* Probe Request */
-+		sint out_len_wapi = 0;
-+		/* here use static for stack size */
-+		static u8 buf_wapi[MAX_WAPI_IE_LEN * 2] = {0};
-+		static u8 wapi_ie[MAX_WAPI_IE_LEN] = {0};
-+		u16 wapi_len = 0;
-+		u16  i;
-+
-+		out_len_wapi = rtw_get_wapi_ie(pnetwork->network.IEs , pnetwork->network.IELength, wapi_ie, &wapi_len);
-+
-+		RTW_INFO("rtw_wx_get_scan: %s ", pnetwork->network.Ssid.Ssid);
-+		RTW_INFO("rtw_wx_get_scan: ssid = %d ", wapi_len);
-+
-+
-+		if (wapi_len > 0) {
-+			p = buf_wapi;
-+			/* _rtw_memset(buf_wapi, 0, MAX_WAPI_IE_LEN*2); */
-+			p += sprintf(p, "wapi_ie=");
-+			for (i = 0; i < wapi_len; i++)
-+				p += sprintf(p, "%02x", wapi_ie[i]);
-+
-+			_rtw_memset(iwe, 0, sizeof(*iwe));
-+			iwe->cmd = IWEVCUSTOM;
-+			iwe->u.data.length = strlen(buf_wapi);
-+			start = iwe_stream_add_point(info, start, stop, iwe, buf_wapi);
-+
-+			_rtw_memset(iwe, 0, sizeof(*iwe));
-+			iwe->cmd = IWEVGENIE;
-+			iwe->u.data.length = wapi_len;
-+			start = iwe_stream_add_point(info, start, stop, iwe, wapi_ie);
-+		}
-+	}
-+#endif/* #ifdef CONFIG_WAPI_SUPPORT */
-+	return start;
-+}
-+
-+static inline char   *iwe_stream_rssi_process(_adapter *padapter,
-+		struct iw_request_info *info, struct wlan_network *pnetwork,
-+		char *start, char *stop, struct iw_event *iwe)
-+{
-+	u8 ss, sq;
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+	s16 noise = 0;
-+#endif
-+
-+	/* Add quality statistics */
-+	iwe->cmd = IWEVQUAL;
-+	iwe->u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+			      | IW_QUAL_NOISE_UPDATED
-+#else
-+			      | IW_QUAL_NOISE_INVALID
-+#endif
-+#ifdef CONFIG_SIGNAL_DISPLAY_DBM
-+			      | IW_QUAL_DBM
-+#endif
-+			      ;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE &&
-+	    is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) {
-+		ss = padapter->recvpriv.signal_strength;
-+		sq = padapter->recvpriv.signal_qual;
-+	} else {
-+		ss = pnetwork->network.PhyInfo.SignalStrength;
-+		sq = pnetwork->network.PhyInfo.SignalQuality;
-+	}
-+
-+
-+#ifdef CONFIG_SIGNAL_DISPLAY_DBM
-+	iwe->u.qual.level = (u8) translate_percentage_to_dbm(ss); /* dbm */
-+#else
-+	iwe->u.qual.level = (u8)ss; /* % */
-+#endif
-+
-+	iwe->u.qual.qual = (u8)sq;   /* signal quality */
-+
-+#ifdef CONFIG_PLATFORM_ROCKCHIPS
-+	iwe->u.qual.noise = -100; /* noise level suggest by zhf@rockchips */
-+#else
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+	if (IS_NM_ENABLE(padapter)) {
-+		noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig);
-+		#ifndef CONFIG_SIGNAL_DISPLAY_DBM
-+		noise = translate_dbm_to_percentage(noise);/*percentage*/
-+		#endif
-+		iwe->u.qual.noise = noise;
-+	}
-+#else
-+	iwe->u.qual.noise = 0; /* noise level */
-+#endif
-+#endif /* CONFIG_PLATFORM_ROCKCHIPS */
-+
-+	/* RTW_INFO("iqual=%d, ilevel=%d, inoise=%d, iupdated=%d\n", iwe.u.qual.qual, iwe.u.qual.level , iwe.u.qual.noise, iwe.u.qual.updated); */
-+
-+	start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_QUAL_LEN);
-+	return start;
-+}
-+
-+static inline char   *iwe_stream_net_rsv_process(_adapter *padapter,
-+		struct iw_request_info *info, struct wlan_network *pnetwork,
-+		char *start, char *stop, struct iw_event *iwe)
-+{
-+	u8 buf[32] = {0};
-+	u8 *p, *pos;
-+	p = buf;
-+	pos = pnetwork->network.Reserved;
-+
-+	p += sprintf(p, "fm=%02X%02X", pos[1], pos[0]);
-+	_rtw_memset(iwe, 0, sizeof(*iwe));
-+	iwe->cmd = IWEVCUSTOM;
-+	iwe->u.data.length = strlen(buf);
-+	start = iwe_stream_add_point(info, start, stop, iwe, buf);
-+	return start;
-+}
-+
-+static char *translate_scan(_adapter *padapter,
-+		struct iw_request_info *info, struct wlan_network *pnetwork,
-+		char *start, char *stop)
-+{
-+	struct iw_event iwe;
-+	u16 cap = 0;
-+	_rtw_memset(&iwe, 0, sizeof(iwe));
-+
-+	if (_FALSE == search_p2p_wfd_ie(padapter, info, pnetwork, start, stop))
-+		return start;
-+
-+	start = iwe_stream_mac_addr_proess(padapter, info, pnetwork, start, stop, &iwe);
-+	start = iwe_stream_essid_proess(padapter, info, pnetwork, start, stop, &iwe);
-+	start = iwe_stream_protocol_process(padapter, info, pnetwork, start, stop, &iwe);
-+	if (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ) /* Probe Request */
-+		cap = 0;
-+	else {
-+		_rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2);
-+		cap = le16_to_cpu(cap);
-+	}
-+
-+	start = iwe_stream_mode_process(padapter, info, pnetwork, start, stop, &iwe, cap);
-+	start = iwe_stream_chan_process(padapter, info, pnetwork, start, stop, &iwe);
-+	start = iwe_stream_encryption_process(padapter, info, pnetwork, start, stop, &iwe, cap);
-+	start = iwe_stream_rate_process(padapter, info, pnetwork, start, stop, &iwe);
-+	start = iwe_stream_wpa_wpa2_process(padapter, info, pnetwork, start, stop, &iwe);
-+	start = iwe_stream_wps_process(padapter, info, pnetwork, start, stop, &iwe);
-+	start = iwe_stream_wapi_process(padapter, info, pnetwork, start, stop, &iwe);
-+	start = iwe_stream_rssi_process(padapter, info, pnetwork, start, stop, &iwe);
-+	start = iwe_stream_net_rsv_process(padapter, info, pnetwork, start, stop, &iwe);
-+
-+	return start;
-+}
-+
-+static int wpa_set_auth_algs(struct net_device *dev, u32 value)
-+{
-+	_adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
-+	int ret = 0;
-+
-+	if ((value & AUTH_ALG_SHARED_KEY) && (value & AUTH_ALG_OPEN_SYSTEM)) {
-+		RTW_INFO("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY and  AUTH_ALG_OPEN_SYSTEM [value:0x%x]\n", value);
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+		padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;
-+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
-+	} else if (value & AUTH_ALG_SHARED_KEY) {
-+		RTW_INFO("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY  [value:0x%x]\n", value);
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+
-+#ifdef CONFIG_PLATFORM_MT53XX
-+		padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;
-+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
-+#else
-+		padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeShared;
-+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Shared;
-+#endif
-+	} else if (value & AUTH_ALG_OPEN_SYSTEM) {
-+		RTW_INFO("wpa_set_auth_algs, AUTH_ALG_OPEN_SYSTEM\n");
-+		/* padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; */
-+		if (padapter->securitypriv.ndisauthtype < Ndis802_11AuthModeWPAPSK) {
-+#ifdef CONFIG_PLATFORM_MT53XX
-+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch;
-+			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
-+#else
-+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
-+			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
-+#endif
-+		}
-+
-+	} else if (value & AUTH_ALG_LEAP)
-+		RTW_INFO("wpa_set_auth_algs, AUTH_ALG_LEAP\n");
-+	else {
-+		RTW_INFO("wpa_set_auth_algs, error!\n");
-+		ret = -EINVAL;
-+	}
-+
-+	return ret;
-+
-+}
-+
-+static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len)
-+{
-+	int ret = 0;
-+	u32 wep_key_idx, wep_key_len;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
-+#endif /* CONFIG_P2P */
-+
-+
-+	param->u.crypt.err = 0;
-+	param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
-+
-+	if (param_len < (u32)((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) {
-+		ret =  -EINVAL;
-+		goto exit;
-+	}
-+
-+	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
-+	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
-+	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) {
-+
-+		if (param->u.crypt.idx >= WEP_KEYS
-+#ifdef CONFIG_IEEE80211W
-+		    && param->u.crypt.idx > BIP_MAX_KEYID
-+#endif /* CONFIG_IEEE80211W */
-+		   ) {
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+	} else {
-+#ifdef CONFIG_WAPI_SUPPORT
-+		if (strcmp(param->u.crypt.alg, "SMS4"))
-+#endif
-+		{
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+	}
-+
-+	if (strcmp(param->u.crypt.alg, "WEP") == 0) {
-+		RTW_INFO("wpa_set_encryption, crypt.alg = WEP\n");
-+
-+		wep_key_idx = param->u.crypt.idx;
-+		wep_key_len = param->u.crypt.key_len;
-+
-+		if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+
-+		if (psecuritypriv->bWepDefaultKeyIdxSet == 0) {
-+			/* wep default key has not been set, so use this key index as default key.*/
-+
-+			wep_key_len = wep_key_len <= 5 ? 5 : 13;
-+
-+			psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+			psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
-+			psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
-+
-+			if (wep_key_len == 13) {
-+				psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
-+				psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
-+			}
-+
-+			psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
-+		}
-+
-+		_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len);
-+
-+		psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len;
-+
-+		psecuritypriv->key_mask |= BIT(wep_key_idx);
-+
-+		padapter->mlmeextpriv.mlmext_info.key_index = wep_key_idx;
-+		goto exit;
-+	}
-+
-+	if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802_1x */
-+		struct sta_info *psta, *pbcmc_sta;
-+		struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) { /* sta mode */
-+			psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
-+			if (psta == NULL) {
-+				/* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */
-+			} else {
-+				/* Jeff: don't disable ieee8021x_blocked while clearing key */
-+				if (strcmp(param->u.crypt.alg, "none") != 0)
-+					psta->ieee8021x_blocked = _FALSE;
-+
-+				if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||
-+				    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))
-+					psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
-+
-+				if (param->u.crypt.set_tx == 1) { /* pairwise key */
-+					RTW_INFO(FUNC_ADPT_FMT" set %s PTK idx:%u, len:%u\n"
-+						, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);
-+					_rtw_memcpy(psta->dot118021x_UncstKey.skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+					if (strcmp(param->u.crypt.alg, "TKIP") == 0) { /* set mic key */
-+						_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
-+						_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
-+						padapter->securitypriv.busetkipkey = _FALSE;
-+					}
-+					psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+					psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+					psta->bpairwise_key_installed = _TRUE;
-+					rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE);
-+
-+				} else { /* group key */
-+					if (strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) {
-+						RTW_INFO(FUNC_ADPT_FMT" set %s GTK idx:%u, len:%u\n"
-+							, FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len);
-+						_rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key,
-+							(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+						/* only TKIP group key need to install this */
-+						if (param->u.crypt.key_len > 16) {
-+							_rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
-+							_rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
-+						}
-+						padapter->securitypriv.binstallGrpkey = _TRUE;
-+						if (param->u.crypt.idx < 4)
-+							_rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], param->u.crypt.seq, 8);
-+						padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx;
-+						rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE);
-+
-+					#ifdef CONFIG_IEEE80211W
-+					} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
-+						RTW_INFO(FUNC_ADPT_FMT" set IGTK idx:%u, len:%u\n"
-+							, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+						_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey,  param->u.crypt.key,
-+							(param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+						psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
-+						psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+						psecuritypriv->binstallBIPkey = _TRUE;
-+					#endif /* CONFIG_IEEE80211W */
-+
-+					}
-+
-+#ifdef CONFIG_P2P
-+					if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING))
-+						rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE);
-+#endif /* CONFIG_P2P */
-+
-+					/* WPA/WPA2 key-handshake has completed */
-+					clr_fwstate(pmlmepriv, WIFI_UNDER_KEY_HANDSHAKE);
-+				}
-+			}
-+
-+			pbcmc_sta = rtw_get_bcmc_stainfo(padapter);
-+			if (pbcmc_sta == NULL) {
-+				/* DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null\n")); */
-+			} else {
-+				/* Jeff: don't disable ieee8021x_blocked while clearing key */
-+				if (strcmp(param->u.crypt.alg, "none") != 0)
-+					pbcmc_sta->ieee8021x_blocked = _FALSE;
-+
-+				if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) ||
-+				    (padapter->securitypriv.ndisencryptstatus ==  Ndis802_11Encryption3Enabled))
-+					pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
-+			}
-+		} else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { /* adhoc mode */
-+		}
-+	}
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	if (strcmp(param->u.crypt.alg, "SMS4") == 0)
-+		rtw_wapi_set_set_encryption(padapter, param);
-+#endif
-+
-+exit:
-+
-+
-+	return ret;
-+}
-+
-+static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen)
-+{
-+	u8 *buf = NULL, *pos = NULL;
-+	int group_cipher = 0, pairwise_cipher = 0;
-+	u8 mfp_opt = MFP_NO;
-+	int ret = 0;
-+	u8 null_addr[] = {0, 0, 0, 0, 0, 0};
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &padapter->wdinfo;
-+#endif /* CONFIG_P2P */
-+
-+	if ((ielen > MAX_WPA_IE_LEN) || (pie == NULL)) {
-+		_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
-+		if (pie == NULL)
-+			return ret;
-+		else
-+			return -EINVAL;
-+	}
-+
-+	if (ielen) {
-+		buf = rtw_zmalloc(ielen);
-+		if (buf == NULL) {
-+			ret =  -ENOMEM;
-+			goto exit;
-+		}
-+
-+		_rtw_memcpy(buf, pie , ielen);
-+
-+		/* dump */
-+		{
-+			int i;
-+			RTW_INFO("\n wpa_ie(length:%d):\n", ielen);
-+			for (i = 0; i < ielen; i = i + 8)
-+				RTW_INFO("0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x\n", buf[i], buf[i + 1], buf[i + 2], buf[i + 3], buf[i + 4], buf[i + 5], buf[i + 6], buf[i + 7]);
-+		}
-+
-+		pos = buf;
-+		if (ielen < RSN_HEADER_LEN) {
-+			ret  = -1;
-+			goto exit;
-+		}
-+
-+		if (rtw_parse_wpa_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
-+			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
-+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK;
-+			_rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen);
-+		}
-+
-+		if (rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL, NULL, &mfp_opt) == _SUCCESS) {
-+			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
-+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK;
-+			_rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen);
-+		}
-+
-+		if (group_cipher == 0)
-+			group_cipher = WPA_CIPHER_NONE;
-+		if (pairwise_cipher == 0)
-+			pairwise_cipher = WPA_CIPHER_NONE;
-+
-+		switch (group_cipher) {
-+		case WPA_CIPHER_NONE:
-+			padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
-+			padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
-+			break;
-+		case WPA_CIPHER_WEP40:
-+			padapter->securitypriv.dot118021XGrpPrivacy = _WEP40_;
-+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+			break;
-+		case WPA_CIPHER_TKIP:
-+			padapter->securitypriv.dot118021XGrpPrivacy = _TKIP_;
-+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
-+			break;
-+		case WPA_CIPHER_CCMP:
-+			padapter->securitypriv.dot118021XGrpPrivacy = _AES_;
-+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+			break;
-+		case WPA_CIPHER_WEP104:
-+			padapter->securitypriv.dot118021XGrpPrivacy = _WEP104_;
-+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+			break;
-+		}
-+
-+		switch (pairwise_cipher) {
-+		case WPA_CIPHER_NONE:
-+			padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
-+			padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
-+			break;
-+		case WPA_CIPHER_WEP40:
-+			padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;
-+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+			break;
-+		case WPA_CIPHER_TKIP:
-+			padapter->securitypriv.dot11PrivacyAlgrthm = _TKIP_;
-+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
-+			break;
-+		case WPA_CIPHER_CCMP:
-+			padapter->securitypriv.dot11PrivacyAlgrthm = _AES_;
-+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+			break;
-+		case WPA_CIPHER_WEP104:
-+			padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;
-+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+			break;
-+		}
-+
-+		if (mfp_opt == MFP_INVALID) {
-+			RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter));
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+		padapter->securitypriv.mfp_opt = mfp_opt;
-+
-+		_clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS);
-+		{/* set wps_ie	 */
-+			u16 cnt = 0;
-+			u8 eid, wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};
-+
-+			while (cnt < ielen) {
-+				eid = buf[cnt];
-+
-+				if ((eid == _VENDOR_SPECIFIC_IE_) && (_rtw_memcmp(&buf[cnt + 2], wps_oui, 4) == _TRUE)) {
-+					RTW_INFO("SET WPS_IE\n");
-+
-+					padapter->securitypriv.wps_ie_len = ((buf[cnt + 1] + 2) < MAX_WPS_IE_LEN) ? (buf[cnt + 1] + 2) : MAX_WPS_IE_LEN;
-+
-+					_rtw_memcpy(padapter->securitypriv.wps_ie, &buf[cnt], padapter->securitypriv.wps_ie_len);
-+
-+					set_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS);
-+
-+#ifdef CONFIG_P2P
-+					if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK))
-+						rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_ING);
-+#endif /* CONFIG_P2P */
-+					cnt += buf[cnt + 1] + 2;
-+
-+					break;
-+				} else {
-+					cnt += buf[cnt + 1] + 2; /* goto next	 */
-+				}
-+			}
-+		}
-+
-+		#ifdef CONFIG_RTW_MULTI_AP
-+		padapter->multi_ap = rtw_get_multi_ap_ie_ext(buf, ielen) & MULTI_AP_BACKHAUL_STA;
-+		if (padapter->multi_ap)
-+			adapter_set_use_wds(padapter, 1);
-+		#endif
-+	}
-+
-+	/* TKIP and AES disallow multicast packets until installing group key */
-+	if (padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_
-+	    || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_
-+	    || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)
-+		/* WPS open need to enable multicast
-+		 * || check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) */
-+		rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr);
-+
-+
-+exit:
-+
-+	if (buf)
-+		rtw_mfree(buf, ielen);
-+
-+	return ret;
-+}
-+
-+static int rtw_wx_get_name(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u32 ht_ielen = 0;
-+	char *p;
-+	u8 ht_cap = _FALSE, vht_cap = _FALSE;
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	WLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;
-+	NDIS_802_11_RATES_EX *prates = NULL;
-+
-+
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE) {
-+		/* parsing HT_CAP_IE */
-+		if( is_supported_ht(padapter->registrypriv.wireless_mode)&&(padapter->registrypriv.ht_enable)) {
-+			p = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength - 12);
-+			if (p && ht_ielen > 0 )
-+				ht_cap = _TRUE;
-+		}
-+#ifdef CONFIG_80211AC_VHT
-+		if ((padapter->registrypriv.wireless_mode & WIRELESS_11AC) &&
-+			(pmlmepriv->vhtpriv.vht_option == _TRUE))
-+			vht_cap = _TRUE;
-+#endif
-+
-+		prates = &pcur_bss->SupportedRates;
-+		if (rtw_is_cckratesonly_included((u8 *)prates) == _TRUE) {
-+			if (ht_cap == _TRUE)
-+				snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bn");
-+			else
-+				snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11b");
-+		} else if ((rtw_is_cckrates_included((u8 *)prates)) == _TRUE) {
-+			if (ht_cap == _TRUE)
-+				snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bgn");
-+			else {
-+				if(padapter->registrypriv.wireless_mode & WIRELESS_11G)
-+					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bg");
-+				else
-+					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11b");
-+			}
-+		} else {
-+			if (pcur_bss->Configuration.DSConfig > 14) {
-+#ifdef CONFIG_80211AC_VHT
-+				if (vht_cap == _TRUE)
-+					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11AC");
-+				else
-+#endif
-+				{
-+					if (ht_cap == _TRUE)
-+						snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11an");
-+					else
-+						snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11a");
-+				}
-+			} else {
-+				if (ht_cap == _TRUE)
-+					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11gn");
-+				else
-+					snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g");
-+			}
-+		}
-+	} else {
-+		/* prates = &padapter->registrypriv.dev_network.SupportedRates; */
-+		/* snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g"); */
-+		snprintf(wrqu->name, IFNAMSIZ, "unassociated");
-+	}
-+
-+
-+	return 0;
-+}
-+
-+static int rtw_wx_set_freq(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	int exp = 1, freq = 0, div = 0;
-+
-+	rtw_ps_deny(padapter, PS_DENY_IOCTL);
-+	if (rtw_pwr_wakeup(padapter) == _FALSE)
-+		goto exit;
-+	if (wrqu->freq.m <= 1000) {
-+		if (wrqu->freq.flags == IW_FREQ_AUTO) {
-+			if (rtw_chset_search_ch(adapter_to_chset(padapter), wrqu->freq.m) > 0) {
-+				padapter->mlmeextpriv.cur_channel = wrqu->freq.m;
-+				RTW_INFO("%s: channel is auto, set to channel %d\n", __func__, wrqu->freq.m);
-+			} else {
-+				padapter->mlmeextpriv.cur_channel = 1;
-+				RTW_INFO("%s: channel is auto, Channel Plan don't match just set to channel 1\n", __func__);
-+			}
-+		} else {
-+			padapter->mlmeextpriv.cur_channel = wrqu->freq.m;
-+			RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel);
-+		}
-+	} else {
-+		while (wrqu->freq.e) {
-+			exp *= 10;
-+			wrqu->freq.e--;
-+		}
-+
-+		freq = wrqu->freq.m;
-+
-+		while (!(freq % 10)) {
-+			freq /= 10;
-+			exp *= 10;
-+		}
-+
-+		/* freq unit is MHz here */
-+		div = 1000000 / exp;
-+
-+		if (div)
-+			freq /= div;
-+		else {
-+			div = exp / 1000000;
-+			freq *= div;
-+		}
-+
-+		/* If freq is invalid, rtw_freq2ch() will return channel 1 */
-+		padapter->mlmeextpriv.cur_channel = rtw_freq2ch(freq);
-+		RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel);
-+	}
-+	set_channel_bwmode(padapter, padapter->mlmeextpriv.cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+exit:
-+	rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
-+
-+	return 0;
-+}
-+
-+static int rtw_wx_get_freq(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	WLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE && check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE) {
-+
-+		wrqu->freq.m = rtw_ch2freq(pcur_bss->Configuration.DSConfig) * 100000;
-+		wrqu->freq.e = 1;
-+		wrqu->freq.i = pcur_bss->Configuration.DSConfig;
-+
-+	} else {
-+		wrqu->freq.m = rtw_ch2freq(padapter->mlmeextpriv.cur_channel) * 100000;
-+		wrqu->freq.e = 1;
-+		wrqu->freq.i = padapter->mlmeextpriv.cur_channel;
-+	}
-+
-+	return 0;
-+}
-+
-+static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a,
-+			   union iwreq_data *wrqu, char *b)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType ;
-+	int ret = 0;
-+
-+
-+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
-+		ret = -EPERM;
-+		goto exit;
-+	}
-+
-+	if (!rtw_is_hw_init_completed(padapter)) {
-+		ret = -EPERM;
-+		goto exit;
-+	}
-+
-+	/* initial default type */
-+	dev->type = ARPHRD_ETHER;
-+
-+	if (wrqu->mode != IW_MODE_MONITOR) {
-+		rtw_ps_deny_cancel(padapter, PS_DENY_MONITOR_MODE);
-+	}
-+
-+	switch (wrqu->mode) {
-+#ifdef CONFIG_WIFI_MONITOR
-+	case IW_MODE_MONITOR:
-+		networkType = Ndis802_11Monitor;
-+
-+		rtw_ps_deny(padapter, PS_DENY_MONITOR_MODE);
-+		LeaveAllPowerSaveMode(padapter);
-+
-+#if 0
-+		dev->type = ARPHRD_IEEE80211; /* IEEE 802.11 : 801 */
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
-+		dev->type = ARPHRD_IEEE80211_RADIOTAP; /* IEEE 802.11 + radiotap header : 803 */
-+		RTW_INFO("set_mode = IW_MODE_MONITOR\n");
-+#else
-+		RTW_INFO("kernel version < 2.6.24 not support IW_MODE_MONITOR\n");
-+#endif
-+		break;
-+#endif /* CONFIG_WIFI_MONITOR */
-+	case IW_MODE_AUTO:
-+		networkType = Ndis802_11AutoUnknown;
-+		RTW_INFO("set_mode = IW_MODE_AUTO\n");
-+		break;
-+	case IW_MODE_ADHOC:
-+		networkType = Ndis802_11IBSS;
-+		RTW_INFO("set_mode = IW_MODE_ADHOC\n");
-+		break;
-+	case IW_MODE_MASTER:
-+		networkType = Ndis802_11APMode;
-+		RTW_INFO("set_mode = IW_MODE_MASTER\n");
-+		break;
-+	case IW_MODE_INFRA:
-+		networkType = Ndis802_11Infrastructure;
-+		RTW_INFO("set_mode = IW_MODE_INFRA\n");
-+		break;
-+
-+	default:
-+		ret = -EINVAL;;
-+		goto exit;
-+	}
-+
-+	if (rtw_set_802_11_infrastructure_mode(padapter, networkType, 0) == _FALSE) {
-+
-+		ret = -EPERM;
-+		goto exit;
-+
-+	}
-+
-+	rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE)
-+		rtw_indicate_connect(padapter);
-+
-+exit:
-+
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_wx_get_mode(struct net_device *dev, struct iw_request_info *a,
-+			   union iwreq_data *wrqu, char *b)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+
-+
-+
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
-+		wrqu->mode = IW_MODE_INFRA;
-+	else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
-+		 (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
-+
-+		wrqu->mode = IW_MODE_ADHOC;
-+	else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
-+		wrqu->mode = IW_MODE_MASTER;
-+	else if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE)
-+		wrqu->mode = IW_MODE_MONITOR;
-+	else
-+		wrqu->mode = IW_MODE_AUTO;
-+
-+
-+	return 0;
-+
-+}
-+
-+
-+static int rtw_wx_set_pmkid(struct net_device *dev,
-+			    struct iw_request_info *a,
-+			    union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8          j, blInserted = _FALSE;
-+	int         intReturn = _FALSE;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct iw_pmksa  *pPMK = (struct iw_pmksa *) extra;
-+	u8     strZeroMacAddress[ETH_ALEN] = { 0x00 };
-+	u8     strIssueBssid[ETH_ALEN] = { 0x00 };
-+
-+#if 0
-+	struct iw_pmksa {
-+		__u32   cmd;
-+		struct sockaddr bssid;
-+		__u8    pmkid[IW_PMKID_LEN];   /* IW_PMKID_LEN=16 */
-+	}
-+	There are the BSSID information in the bssid.sa_data array.
-+	If cmd is IW_PMKSA_FLUSH, it means the wpa_suppplicant wants to clear all the PMKID information.
-+	If cmd is IW_PMKSA_ADD, it means the wpa_supplicant wants to add a PMKID / BSSID to driver.
-+	If cmd is IW_PMKSA_REMOVE, it means the wpa_supplicant wants to remove a PMKID / BSSID from driver.
-+#endif
-+
-+	_rtw_memcpy(strIssueBssid, pPMK->bssid.sa_data, ETH_ALEN);
-+	if (pPMK->cmd == IW_PMKSA_ADD) {
-+		RTW_INFO("[rtw_wx_set_pmkid] IW_PMKSA_ADD!\n");
-+		if (_rtw_memcmp(strIssueBssid, strZeroMacAddress, ETH_ALEN) == _TRUE)
-+			return intReturn ;
-+		else
-+			intReturn = _TRUE;
-+		blInserted = _FALSE;
-+
-+		/* overwrite PMKID */
-+		for (j = 0 ; j < NUM_PMKID_CACHE; j++) {
-+			if (_rtw_memcmp(psecuritypriv->PMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) == _TRUE) {
-+				/* BSSID is matched, the same AP => rewrite with new PMKID. */
-+
-+				RTW_INFO("[rtw_wx_set_pmkid] BSSID exists in the PMKList.\n");
-+
-+				_rtw_memcpy(psecuritypriv->PMKIDList[j].PMKID, pPMK->pmkid, IW_PMKID_LEN);
-+				psecuritypriv->PMKIDList[j].bUsed = _TRUE;
-+				psecuritypriv->PMKIDIndex = j + 1;
-+				blInserted = _TRUE;
-+				break;
-+			}
-+		}
-+
-+		if (!blInserted) {
-+			/* Find a new entry */
-+			RTW_INFO("[rtw_wx_set_pmkid] Use the new entry index = %d for this PMKID.\n",
-+				 psecuritypriv->PMKIDIndex);
-+
-+			_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, strIssueBssid, ETH_ALEN);
-+			_rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pPMK->pmkid, IW_PMKID_LEN);
-+
-+			psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].bUsed = _TRUE;
-+			psecuritypriv->PMKIDIndex++ ;
-+			if (psecuritypriv->PMKIDIndex == 16)
-+				psecuritypriv->PMKIDIndex = 0;
-+		}
-+	} else if (pPMK->cmd == IW_PMKSA_REMOVE) {
-+		RTW_INFO("[rtw_wx_set_pmkid] IW_PMKSA_REMOVE!\n");
-+		intReturn = _TRUE;
-+		for (j = 0 ; j < NUM_PMKID_CACHE; j++) {
-+			if (_rtw_memcmp(psecuritypriv->PMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) == _TRUE) {
-+				/* BSSID is matched, the same AP => Remove this PMKID information and reset it. */
-+				_rtw_memset(psecuritypriv->PMKIDList[j].Bssid, 0x00, ETH_ALEN);
-+				psecuritypriv->PMKIDList[j].bUsed = _FALSE;
-+				break;
-+			}
-+		}
-+	} else if (pPMK->cmd == IW_PMKSA_FLUSH) {
-+		RTW_INFO("[rtw_wx_set_pmkid] IW_PMKSA_FLUSH!\n");
-+		_rtw_memset(&psecuritypriv->PMKIDList[0], 0x00, sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
-+		psecuritypriv->PMKIDIndex = 0;
-+		intReturn = _TRUE;
-+	}
-+	return intReturn ;
-+}
-+
-+static int rtw_wx_get_sens(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+#ifdef CONFIG_PLATFORM_ROCKCHIPS
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	/*
-+	*  20110311 Commented by Jeff
-+	*  For rockchip platform's wpa_driver_wext_get_rssi
-+	*/
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+		/* wrqu->sens.value=-padapter->recvpriv.signal_strength; */
-+		wrqu->sens.value = -padapter->recvpriv.rssi;
-+		/* RTW_INFO("%s: %d\n", __FUNCTION__, wrqu->sens.value); */
-+		wrqu->sens.fixed = 0; /* no auto select */
-+	} else
-+#endif
-+	{
-+		wrqu->sens.value = 0;
-+		wrqu->sens.fixed = 0;	/* no auto select */
-+		wrqu->sens.disabled = 1;
-+	}
-+	return 0;
-+}
-+
-+static int rtw_wx_get_range(struct net_device *dev,
-+			    struct iw_request_info *info,
-+			    union iwreq_data *wrqu, char *extra)
-+{
-+	struct iw_range *range = (struct iw_range *)extra;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	u16 val;
-+	int i;
-+
-+
-+
-+	wrqu->data.length = sizeof(*range);
-+	_rtw_memset(range, 0, sizeof(*range));
-+
-+	/* Let's try to keep this struct in the same order as in
-+	 * linux/include/wireless.h
-+	 */
-+
-+	/* TODO: See what values we can set, and remove the ones we can't
-+	 * set, or fill them with some default data.
-+	 */
-+
-+	/* ~5 Mb/s real (802.11b) */
-+	range->throughput = 5 * 1000 * 1000;
-+
-+	/* TODO: Not used in 802.11b?
-+	*	range->min_nwid;	 Minimal NWID we are able to set  */
-+	/* TODO: Not used in 802.11b?
-+	*	range->max_nwid;	 Maximal NWID we are able to set  */
-+
-+	/* Old Frequency (backward compat - moved lower ) */
-+	/*	range->old_num_channels;
-+	 *	range->old_num_frequency;
-+	 * 	range->old_freq[6];  Filler to keep "version" at the same offset  */
-+
-+	/* signal level threshold range */
-+
-+	/* Quality of link & SNR stuff */
-+	/* Quality range (link, level, noise)
-+	 * If the quality is absolute, it will be in the range [0 ; max_qual],
-+	 * if the quality is dBm, it will be in the range [max_qual ; 0].
-+	 * Don't forget that we use 8 bit arithmetics...
-+	 *
-+	 * If percentage range is 0~100
-+	 * Signal strength dbm range logical is -100 ~ 0
-+	 * but usually value is -90 ~ -20
-+	 */
-+	range->max_qual.qual = 100;
-+#ifdef CONFIG_SIGNAL_DISPLAY_DBM
-+	range->max_qual.level = (u8)-100;
-+	range->max_qual.noise = (u8)-100;
-+	range->max_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */
-+	range->max_qual.updated |= IW_QUAL_DBM;
-+#else /* !CONFIG_SIGNAL_DISPLAY_DBM */
-+	/* percent values between 0 and 100. */
-+	range->max_qual.level = 100;
-+	range->max_qual.noise = 100;
-+	range->max_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */
-+#endif /* !CONFIG_SIGNAL_DISPLAY_DBM */
-+
-+	/* This should contain the average/typical values of the quality
-+	 * indicator. This should be the threshold between a "good" and
-+	 * a "bad" link (example : monitor going from green to orange).
-+	 * Currently, user space apps like quality monitors don't have any
-+	 * way to calibrate the measurement. With this, they can split
-+	 * the range between 0 and max_qual in different quality level
-+	 * (using a geometric subdivision centered on the average).
-+	 * I expect that people doing the user space apps will feedback
-+	 * us on which value we need to put in each driver... */
-+	range->avg_qual.qual = 92; /* > 8% missed beacons is 'bad' */
-+#ifdef CONFIG_SIGNAL_DISPLAY_DBM
-+	/* TODO: Find real 'good' to 'bad' threshold value for RSSI */
-+	range->avg_qual.level = (u8)-70;
-+	range->avg_qual.noise = 0;
-+	range->avg_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */
-+	range->avg_qual.updated |= IW_QUAL_DBM;
-+#else /* !CONFIG_SIGNAL_DISPLAY_DBM */
-+	/* TODO: Find real 'good' to 'bad' threshol value for RSSI */
-+	range->avg_qual.level = 30;
-+	range->avg_qual.noise = 100;
-+	range->avg_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */
-+#endif /* !CONFIG_SIGNAL_DISPLAY_DBM */
-+
-+	range->num_bitrates = RATE_COUNT;
-+
-+	for (i = 0; i < RATE_COUNT && i < IW_MAX_BITRATES; i++)
-+		range->bitrate[i] = rtw_rates[i];
-+
-+	range->min_frag = MIN_FRAG_THRESHOLD;
-+	range->max_frag = MAX_FRAG_THRESHOLD;
-+
-+	range->pm_capa = 0;
-+
-+	range->we_version_compiled = WIRELESS_EXT;
-+	range->we_version_source = 16;
-+
-+	/*	range->retry_capa;	 What retry options are supported
-+	 *	range->retry_flags;	 How to decode max/min retry limit
-+	 *	range->r_time_flags;	 How to decode max/min retry life
-+	 *	range->min_retry;	 Minimal number of retries
-+	 *	range->max_retry;	 Maximal number of retries
-+	 *	range->min_r_time;	 Minimal retry lifetime
-+	 *	range->max_r_time;	 Maximal retry lifetime  */
-+
-+	for (i = 0, val = 0; i < rfctl->max_chan_nums; i++) {
-+
-+		/* Include only legal frequencies for some countries */
-+		if (rfctl->channel_set[i].ChannelNum != 0) {
-+			range->freq[val].i = rfctl->channel_set[i].ChannelNum;
-+			range->freq[val].m = rtw_ch2freq(rfctl->channel_set[i].ChannelNum) * 100000;
-+			range->freq[val].e = 1;
-+			val++;
-+		}
-+
-+		if (val == IW_MAX_FREQUENCIES)
-+			break;
-+	}
-+
-+	range->num_channels = val;
-+	range->num_frequency = val;
-+
-+	/* Commented by Albert 2009/10/13
-+	 * The following code will proivde the security capability to network manager.
-+	 * If the driver doesn't provide this capability to network manager,
-+	 * the WPA/WPA2 routers can't be choosen in the network manager. */
-+
-+	/*
-+	#define IW_SCAN_CAPA_NONE		0x00
-+	#define IW_SCAN_CAPA_ESSID		0x01
-+	#define IW_SCAN_CAPA_BSSID		0x02
-+	#define IW_SCAN_CAPA_CHANNEL	0x04
-+	#define IW_SCAN_CAPA_MODE		0x08
-+	#define IW_SCAN_CAPA_RATE		0x10
-+	#define IW_SCAN_CAPA_TYPE		0x20
-+	#define IW_SCAN_CAPA_TIME		0x40
-+	*/
-+
-+#if WIRELESS_EXT > 17
-+	range->enc_capa = IW_ENC_CAPA_WPA | IW_ENC_CAPA_WPA2 |
-+			  IW_ENC_CAPA_CIPHER_TKIP | IW_ENC_CAPA_CIPHER_CCMP;
-+#endif
-+
-+#ifdef IW_SCAN_CAPA_ESSID /* WIRELESS_EXT > 21 */
-+	range->scan_capa = IW_SCAN_CAPA_ESSID | IW_SCAN_CAPA_TYPE | IW_SCAN_CAPA_BSSID |
-+		   IW_SCAN_CAPA_CHANNEL | IW_SCAN_CAPA_MODE | IW_SCAN_CAPA_RATE;
-+#endif
-+
-+
-+
-+	return 0;
-+
-+}
-+
-+/* set bssid flow
-+ * s1. rtw_set_802_11_infrastructure_mode()
-+ * s2. rtw_set_802_11_authentication_mode()
-+ * s3. set_802_11_encryption_mode()
-+ * s4. rtw_set_802_11_bssid() */
-+static int rtw_wx_set_wap(struct net_device *dev,
-+			  struct iw_request_info *info,
-+			  union iwreq_data *awrq,
-+			  char *extra)
-+{
-+	_irqL	irqL;
-+	uint ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct sockaddr *temp = (struct sockaddr *)awrq;
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	_list	*phead;
-+	u8 *dst_bssid, *src_bssid;
-+	_queue	*queue	= &(pmlmepriv->scanned_queue);
-+	struct	wlan_network	*pnetwork = NULL;
-+	NDIS_802_11_AUTHENTICATION_MODE	authmode;
-+
-+	/*
-+	#ifdef CONFIG_CONCURRENT_MODE
-+		if(padapter->adapter_type > PRIMARY_IFACE)
-+		{
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+	#endif
-+	*/
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING) == _TRUE) {
-+		RTW_INFO("set bssid, but buddy_intf is under scanning or linking\n");
-+
-+		ret = -EINVAL;
-+
-+		goto exit;
-+	}
-+#endif
-+
-+	rtw_ps_deny(padapter, PS_DENY_JOIN);
-+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
-+		ret = -1;
-+		goto cancel_ps_deny;
-+	}
-+
-+	if (!padapter->bup) {
-+		ret = -1;
-+		goto cancel_ps_deny;
-+	}
-+
-+
-+	if (temp->sa_family != ARPHRD_ETHER) {
-+		ret = -EINVAL;
-+		goto cancel_ps_deny;
-+	}
-+
-+	authmode = padapter->securitypriv.ndisauthtype;
-+	_enter_critical_bh(&queue->lock, &irqL);
-+	phead = get_list_head(queue);
-+	pmlmepriv->pscanned = get_next(phead);
-+
-+	while (1) {
-+
-+		if ((rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) == _TRUE) {
-+#if 0
-+			ret = -EINVAL;
-+			goto cancel_ps_deny;
-+
-+			if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
-+				rtw_set_802_11_bssid(padapter, temp->sa_data);
-+				goto cancel_ps_deny;
-+			} else {
-+				ret = -EINVAL;
-+				goto cancel_ps_deny;
-+			}
-+#endif
-+
-+			break;
-+		}
-+
-+		pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
-+
-+		pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
-+
-+		dst_bssid = pnetwork->network.MacAddress;
-+
-+		src_bssid = temp->sa_data;
-+
-+		if ((_rtw_memcmp(dst_bssid, src_bssid, ETH_ALEN)) == _TRUE) {
-+			if (!rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode, 0)) {
-+				ret = -1;
-+				_exit_critical_bh(&queue->lock, &irqL);
-+				goto cancel_ps_deny;
-+			}
-+
-+			break;
-+		}
-+
-+	}
-+	_exit_critical_bh(&queue->lock, &irqL);
-+
-+	rtw_set_802_11_authentication_mode(padapter, authmode);
-+	/* set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */
-+	if (rtw_set_802_11_bssid(padapter, temp->sa_data) == _FALSE) {
-+		ret = -1;
-+		goto cancel_ps_deny;
-+	}
-+
-+cancel_ps_deny:
-+	rtw_ps_deny_cancel(padapter, PS_DENY_JOIN);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+exit:
-+#endif
-+	return ret;
-+}
-+
-+static int rtw_wx_get_wap(struct net_device *dev,
-+			  struct iw_request_info *info,
-+			  union iwreq_data *wrqu, char *extra)
-+{
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	WLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;
-+
-+	wrqu->ap_addr.sa_family = ARPHRD_ETHER;
-+
-+	_rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN);
-+
-+
-+
-+	if (((check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) == _TRUE) ||
-+	    ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) ||
-+	    ((check_fwstate(pmlmepriv, WIFI_AP_STATE)) == _TRUE))
-+
-+		_rtw_memcpy(wrqu->ap_addr.sa_data, pcur_bss->MacAddress, ETH_ALEN);
-+	else
-+		_rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN);
-+
-+
-+	return 0;
-+
-+}
-+
-+static int rtw_wx_set_mlme(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+#if 0
-+	/* SIOCSIWMLME data */
-+	struct	iw_mlme {
-+		__u16		cmd; /* IW_MLME_* */
-+		__u16		reason_code;
-+		struct sockaddr	addr;
-+	};
-+#endif
-+
-+	int ret = 0;
-+	u16 reason;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct iw_mlme *mlme = (struct iw_mlme *) extra;
-+
-+
-+	if (mlme == NULL)
-+		return -1;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	reason = cpu_to_le16(mlme->reason_code);
-+
-+
-+	RTW_INFO("%s, cmd=%d, reason=%d\n", __FUNCTION__, mlme->cmd, reason);
-+
-+
-+	switch (mlme->cmd) {
-+	case IW_MLME_DEAUTH:
-+		if (!rtw_set_802_11_disassociate(padapter))
-+			ret = -1;
-+		break;
-+
-+	case IW_MLME_DISASSOC:
-+		if (!rtw_set_802_11_disassociate(padapter))
-+			ret = -1;
-+
-+		break;
-+
-+	default:
-+		return -EOPNOTSUPP;
-+	}
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	rtw_rson_do_disconnect(padapter);
-+#endif
-+	return ret;
-+}
-+
-+static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+	u8 _status = _FALSE;
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	/*struct mlme_priv *pmlmepriv = &padapter->mlmepriv;*/
-+	struct sitesurvey_parm parm;
-+	u8 ssc_chk;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+#endif /* CONFIG_P2P */
-+
-+#ifdef DBG_IOCTL
-+	RTW_INFO("DBG_IOCTL %s:%d\n", __FUNCTION__, __LINE__);
-+#endif
-+
-+#if 1
-+	ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE);
-+
-+	#ifdef CONFIG_DOSCAN_IN_BUSYTRAFFIC
-+	if ((ssc_chk != SS_ALLOW) && (ssc_chk != SS_DENY_BUSY_TRAFFIC))
-+	#else
-+	/* When Busy Traffic, driver do not site survey. So driver return success. */
-+	/* wpa_supplicant will not issue SIOCSIWSCAN cmd again after scan timeout. */
-+	/* modify by thomas 2011-02-22. */
-+	if (ssc_chk != SS_ALLOW)
-+	#endif
-+	{
-+		if (ssc_chk == SS_DENY_MP_MODE)
-+			ret = -EPERM;
-+		#ifdef DBG_LA_MODE
-+		else if (ssc_chk == SS_DENY_LA_MODE)
-+			ret = -EPERM;
-+		#endif
-+		else
-+			indicate_wx_scan_complete_event(padapter);
-+
-+		goto exit;
-+	} else
-+		RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+
-+	rtw_ps_deny(padapter, PS_DENY_SCAN);
-+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
-+		ret = -1;
-+		goto cancel_ps_deny;
-+	}
-+	if (!rtw_is_adapter_up(padapter)) {
-+		ret = -1;
-+		goto cancel_ps_deny;
-+	}
-+#else
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	if (rtw_mp_mode_check(padapter)) {
-+		RTW_INFO("MP mode block Scan request\n");
-+		ret = -EPERM;
-+		goto exit;
-+	}
-+#endif
-+	if (rtw_is_scan_deny(padapter)) {
-+		indicate_wx_scan_complete_event(padapter);
-+		goto exit;
-+	}
-+
-+	rtw_ps_deny(padapter, PS_DENY_SCAN);
-+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
-+		ret = -1;
-+		goto cancel_ps_deny;
-+	}
-+
-+	if (!rtw_is_adapter_up(padapter)) {
-+		ret = -1;
-+		goto cancel_ps_deny;
-+	}
-+
-+#ifndef CONFIG_DOSCAN_IN_BUSYTRAFFIC
-+	/* When Busy Traffic, driver do not site survey. So driver return success. */
-+	/* wpa_supplicant will not issue SIOCSIWSCAN cmd again after scan timeout. */
-+	/* modify by thomas 2011-02-22. */
-+	if (rtw_mi_busy_traffic_check(padapter)) {
-+		indicate_wx_scan_complete_event(padapter);
-+		goto cancel_ps_deny;
-+	}
-+#endif
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) {
-+		RTW_INFO(FUNC_ADPT_FMT" blocking scan for under rson scanning process\n", FUNC_ADPT_ARG(padapter));
-+		indicate_wx_scan_complete_event(padapter);
-+		goto cancel_ps_deny;
-+	}
-+#endif
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
-+		RTW_INFO("AP mode process WPS\n");
-+		indicate_wx_scan_complete_event(padapter);
-+		goto cancel_ps_deny;
-+	}
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING) == _TRUE) {
-+		indicate_wx_scan_complete_event(padapter);
-+		goto cancel_ps_deny;
-+	}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_buddy_check_fwstate(padapter,
-+		       WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING | WIFI_UNDER_WPS)) {
-+
-+		indicate_wx_scan_complete_event(padapter);
-+		goto cancel_ps_deny;
-+	}
-+#endif
-+#endif
-+
-+#ifdef CONFIG_P2P
-+	if (pwdinfo->p2p_state != P2P_STATE_NONE) {
-+		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
-+		rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
-+		rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_FULL);
-+		rtw_free_network_queue(padapter, _TRUE);
-+	}
-+#endif /* CONFIG_P2P */
-+
-+#if WIRELESS_EXT >= 17
-+	if (wrqu->data.length == sizeof(struct iw_scan_req)) {
-+		struct iw_scan_req *req = (struct iw_scan_req *)extra;
-+
-+		if (wrqu->data.flags & IW_SCAN_THIS_ESSID) {
-+			int len = min((int)req->essid_len, IW_ESSID_MAX_SIZE);
-+
-+			rtw_init_sitesurvey_parm(padapter, &parm);
-+			_rtw_memcpy(&parm.ssid[0].Ssid, &req->essid, len);
-+			parm.ssid[0].SsidLength = len;
-+			parm.ssid_num = 1;
-+
-+			RTW_INFO("IW_SCAN_THIS_ESSID, ssid=%s, len=%d\n", req->essid, req->essid_len);
-+
-+			_status = rtw_set_802_11_bssid_list_scan(padapter, &parm);
-+
-+		} else if (req->scan_type == IW_SCAN_TYPE_PASSIVE)
-+			RTW_INFO("rtw_wx_set_scan, req->scan_type == IW_SCAN_TYPE_PASSIVE\n");
-+
-+	} else
-+#endif
-+
-+		if (wrqu->data.length >= WEXT_CSCAN_HEADER_SIZE
-+		    && _rtw_memcmp(extra, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE
-+		   ) {
-+			int len = wrqu->data.length - WEXT_CSCAN_HEADER_SIZE;
-+			char *pos = extra + WEXT_CSCAN_HEADER_SIZE;
-+			char section;
-+			char sec_len;
-+			int ssid_index = 0;
-+
-+			/* RTW_INFO("%s COMBO_SCAN header is recognized\n", __FUNCTION__); */
-+			rtw_init_sitesurvey_parm(padapter, &parm);
-+
-+			while (len >= 1) {
-+				section = *(pos++);
-+				len -= 1;
-+
-+				switch (section) {
-+				case WEXT_CSCAN_SSID_SECTION:
-+					/* RTW_INFO("WEXT_CSCAN_SSID_SECTION\n"); */
-+					if (len < 1) {
-+						len = 0;
-+						break;
-+					}
-+
-+					sec_len = *(pos++);
-+					len -= 1;
-+
-+					if (sec_len > 0 && sec_len <= len) {
-+
-+						parm.ssid[ssid_index].SsidLength = sec_len;
-+						_rtw_memcpy(&parm.ssid[ssid_index].Ssid, pos, sec_len);
-+
-+						/* RTW_INFO("%s COMBO_SCAN with specific parm.ssid:%s, %d\n", __FUNCTION__ */
-+						/*	, parm.ssid[ssid_index].Ssid, parm.ssid[ssid_index].SsidLength); */
-+						ssid_index++;
-+					}
-+
-+					pos += sec_len;
-+					len -= sec_len;
-+					break;
-+
-+
-+				case WEXT_CSCAN_CHANNEL_SECTION:
-+					/* RTW_INFO("WEXT_CSCAN_CHANNEL_SECTION\n"); */
-+					pos += 1;
-+					len -= 1;
-+					break;
-+				case WEXT_CSCAN_ACTV_DWELL_SECTION:
-+					/* RTW_INFO("WEXT_CSCAN_ACTV_DWELL_SECTION\n"); */
-+					pos += 2;
-+					len -= 2;
-+					break;
-+				case WEXT_CSCAN_PASV_DWELL_SECTION:
-+					/* RTW_INFO("WEXT_CSCAN_PASV_DWELL_SECTION\n"); */
-+					pos += 2;
-+					len -= 2;
-+					break;
-+				case WEXT_CSCAN_HOME_DWELL_SECTION:
-+					/* RTW_INFO("WEXT_CSCAN_HOME_DWELL_SECTION\n"); */
-+					pos += 2;
-+					len -= 2;
-+					break;
-+				case WEXT_CSCAN_TYPE_SECTION:
-+					/* RTW_INFO("WEXT_CSCAN_TYPE_SECTION\n"); */
-+					pos += 1;
-+					len -= 1;
-+					break;
-+#if 0
-+				case WEXT_CSCAN_NPROBE_SECTION:
-+					RTW_INFO("WEXT_CSCAN_NPROBE_SECTION\n");
-+					break;
-+#endif
-+
-+				default:
-+					/* RTW_INFO("Unknown CSCAN section %c\n", section); */
-+					len = 0; /* stop parsing */
-+				}
-+				/* RTW_INFO("len:%d\n", len); */
-+
-+			}
-+			parm.ssid_num = ssid_index;
-+
-+			/* jeff: it has still some scan paramater to parse, we only do this now... */
-+			_status = rtw_set_802_11_bssid_list_scan(padapter, &parm);
-+
-+		} else
-+
-+			_status = rtw_set_802_11_bssid_list_scan(padapter, NULL);
-+
-+	if (_status == _FALSE)
-+		ret = -1;
-+
-+cancel_ps_deny:
-+	rtw_ps_deny_cancel(padapter, PS_DENY_SCAN);
-+
-+exit:
-+#ifdef DBG_IOCTL
-+	RTW_INFO("DBG_IOCTL %s:%d return %d\n", __FUNCTION__, __LINE__, ret);
-+#endif
-+
-+	return ret;
-+}
-+
-+static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+	_irqL	irqL;
-+	_list					*plist, *phead;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	RT_CHANNEL_INFO *chset = rfctl->channel_set;
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	_queue				*queue	= &(pmlmepriv->scanned_queue);
-+	struct	wlan_network	*pnetwork = NULL;
-+	char *ev = extra;
-+	char *stop = ev + wrqu->data.length;
-+	u32 ret = 0;
-+	u32 wait_for_surveydone;
-+	sint wait_status;
-+	u8 ch;
-+
-+#ifdef CONFIG_P2P
-+	struct	wifidirect_info	*pwdinfo = &padapter->wdinfo;
-+#endif /* CONFIG_P2P */
-+
-+
-+#ifdef DBG_IOCTL
-+	RTW_INFO("DBG_IOCTL %s:%d\n", __FUNCTION__, __LINE__);
-+#endif
-+
-+	if (adapter_to_pwrctl(padapter)->brfoffbyhw && rtw_is_drv_stopped(padapter)) {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_P2P
-+	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
-+		wait_for_surveydone = 200;
-+	else {
-+		/*	P2P is disabled */
-+		wait_for_surveydone = 100;
-+	}
-+#else
-+	{
-+		wait_for_surveydone = 100;
-+	}
-+#endif /* CONFIG_P2P */
-+
-+#if 1 /* Wireless Extension use EAGAIN to try */
-+	wait_status = WIFI_UNDER_SURVEY
-+#ifndef CONFIG_RTW_ANDROID
-+		      | WIFI_UNDER_LINKING
-+#endif
-+		      ;
-+
-+	while (check_fwstate(pmlmepriv, wait_status) == _TRUE)
-+		return -EAGAIN;
-+#else
-+	wait_status = WIFI_UNDER_SURVEY
-+#ifndef CONFIG_RTW_ANDROID
-+		      | WIFI_UNDER_LINKING
-+#endif
-+		      ;
-+
-+	while (check_fwstate(pmlmepriv, wait_status) == _TRUE) {
-+		rtw_msleep_os(30);
-+		cnt++;
-+		if (cnt > wait_for_surveydone)
-+			break;
-+	}
-+#endif
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		if ((stop - ev) < SCAN_ITEM_SIZE) {
-+			if(wrqu->data.length == MAX_SCAN_BUFFER_LEN){ /*max buffer len defined by iwlist*/
-+				ret = 0;
-+				RTW_INFO("%s: Scan results incomplete\n", __FUNCTION__);
-+				break;
-+			}
-+			ret = -E2BIG;
-+			break;
-+		}
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+		ch = pnetwork->network.Configuration.DSConfig;
-+
-+		/* report network only if the current channel set contains the channel to which this network belongs */
-+		if (rtw_chset_search_ch(chset, ch) >= 0
-+			&& rtw_mlme_band_check(padapter, ch) == _TRUE
-+			&& _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))
-+			&& (!IS_DFS_SLAVE_WITH_RD(rfctl)
-+				|| rtw_rfctl_dfs_domain_unknown(rfctl)
-+				|| !rtw_chset_is_ch_non_ocp(chset, ch))
-+		)
-+			ev = translate_scan(padapter, a, pnetwork, ev, stop);
-+
-+		plist = get_next(plist);
-+
-+	}
-+
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	wrqu->data.length = ev - extra;
-+	wrqu->data.flags = 0;
-+
-+exit:
-+
-+
-+#ifdef DBG_IOCTL
-+	RTW_INFO("DBG_IOCTL %s:%d return %d\n", __FUNCTION__, __LINE__, ret);
-+#endif
-+
-+	return ret ;
-+
-+}
-+
-+/* set ssid flow
-+ * s1. rtw_set_802_11_infrastructure_mode()
-+ * s2. set_802_11_authenticaion_mode()
-+ * s3. set_802_11_encryption_mode()
-+ * s4. rtw_set_802_11_ssid() */
-+static int rtw_wx_set_essid(struct net_device *dev,
-+			    struct iw_request_info *a,
-+			    union iwreq_data *wrqu, char *extra)
-+{
-+	_irqL irqL;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	_queue *queue = &pmlmepriv->scanned_queue;
-+	_list *phead;
-+	struct wlan_network *pnetwork = NULL;
-+	NDIS_802_11_AUTHENTICATION_MODE authmode;
-+	NDIS_802_11_SSID ndis_ssid;
-+	u8 *dst_ssid, *src_ssid;
-+
-+	uint ret = 0, len;
-+
-+
-+#ifdef DBG_IOCTL
-+	RTW_INFO("DBG_IOCTL %s:%d\n", __FUNCTION__, __LINE__);
-+#endif
-+#ifdef CONFIG_WEXT_DONT_JOIN_BYSSID
-+	RTW_INFO("%s: CONFIG_WEXT_DONT_JOIN_BYSSID be defined!! only allow bssid joining\n", __func__);
-+	return -EPERM;
-+#endif
-+
-+#if WIRELESS_EXT <= 20
-+	if ((wrqu->essid.length - 1) > IW_ESSID_MAX_SIZE) {
-+#else
-+	if (wrqu->essid.length > IW_ESSID_MAX_SIZE) {
-+#endif
-+		ret = -E2BIG;
-+		goto exit;
-+	}
-+
-+
-+
-+	rtw_ps_deny(padapter, PS_DENY_JOIN);
-+	if (_FAIL == rtw_pwr_wakeup(padapter)) {
-+		ret = -1;
-+		goto cancel_ps_deny;
-+	}
-+
-+	if (!padapter->bup) {
-+		ret = -1;
-+		goto cancel_ps_deny;
-+	}
-+
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
-+		ret = -1;
-+		goto cancel_ps_deny;
-+	}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (rtw_mi_buddy_check_fwstate(padapter, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING)) {
-+		RTW_INFO("set ssid, but buddy_intf is under scanning or linking\n");
-+		ret = -EINVAL;
-+		goto cancel_ps_deny;
-+	}
-+#endif
-+	authmode = padapter->securitypriv.ndisauthtype;
-+	RTW_INFO("=>%s\n", __FUNCTION__);
-+	if (wrqu->essid.flags && wrqu->essid.length) {
-+		/* Commented by Albert 20100519 */
-+		/* We got the codes in "set_info" function of iwconfig source code. */
-+		/*	========================================= */
-+		/*	wrq.u.essid.length = strlen(essid) + 1; */
-+		/*	if(we_kernel_version > 20) */
-+		/*		wrq.u.essid.length--; */
-+		/*	========================================= */
-+		/*	That means, if the WIRELESS_EXT less than or equal to 20, the correct ssid len should subtract 1. */
-+#if WIRELESS_EXT <= 20
-+		len = ((wrqu->essid.length - 1) < IW_ESSID_MAX_SIZE) ? (wrqu->essid.length - 1) : IW_ESSID_MAX_SIZE;
-+#else
-+		len = (wrqu->essid.length < IW_ESSID_MAX_SIZE) ? wrqu->essid.length : IW_ESSID_MAX_SIZE;
-+#endif
-+
-+		if (wrqu->essid.length != 33)
-+			RTW_INFO("ssid=%s, len=%d\n", extra, wrqu->essid.length);
-+
-+		_rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));
-+		ndis_ssid.SsidLength = len;
-+		_rtw_memcpy(ndis_ssid.Ssid, extra, len);
-+		src_ssid = ndis_ssid.Ssid;
-+
-+		_enter_critical_bh(&queue->lock, &irqL);
-+		phead = get_list_head(queue);
-+		pmlmepriv->pscanned = get_next(phead);
-+
-+		while (1) {
-+			if (rtw_end_of_queue_search(phead, pmlmepriv->pscanned) == _TRUE) {
-+#if 0
-+				if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
-+					rtw_set_802_11_ssid(padapter, &ndis_ssid);
-+
-+					goto cancel_ps_deny;
-+				} else {
-+					ret = -EINVAL;
-+					goto cancel_ps_deny;
-+				}
-+#endif
-+
-+				break;
-+			}
-+
-+			pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
-+
-+			pmlmepriv->pscanned = get_next(pmlmepriv->pscanned);
-+
-+			dst_ssid = pnetwork->network.Ssid.Ssid;
-+
-+
-+			if ((_rtw_memcmp(dst_ssid, src_ssid, ndis_ssid.SsidLength) == _TRUE) &&
-+			    (pnetwork->network.Ssid.SsidLength == ndis_ssid.SsidLength)) {
-+
-+				if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) {
-+					if (pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode)
-+						continue;
-+				}
-+
-+				if (rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode, 0) == _FALSE) {
-+					ret = -1;
-+					_exit_critical_bh(&queue->lock, &irqL);
-+					goto cancel_ps_deny;
-+				}
-+
-+				break;
-+			}
-+		}
-+		_exit_critical_bh(&queue->lock, &irqL);
-+		rtw_set_802_11_authentication_mode(padapter, authmode);
-+		/* set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */
-+		if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) {
-+			ret = -1;
-+			goto cancel_ps_deny;
-+		}
-+	}
-+
-+cancel_ps_deny:
-+	rtw_ps_deny_cancel(padapter, PS_DENY_JOIN);
-+
-+exit:
-+	RTW_INFO("<=%s, ret %d\n", __FUNCTION__, ret);
-+
-+#ifdef DBG_IOCTL
-+	RTW_INFO("DBG_IOCTL %s:%d return %d\n", __FUNCTION__, __LINE__, ret);
-+#endif
-+
-+
-+	return ret;
-+}
-+
-+static int rtw_wx_get_essid(struct net_device *dev,
-+			    struct iw_request_info *a,
-+			    union iwreq_data *wrqu, char *extra)
-+{
-+	u32 len, ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	WLAN_BSSID_EX  *pcur_bss = &pmlmepriv->cur_network.network;
-+
-+
-+
-+	if ((check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) ||
-+	    (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
-+		len = pcur_bss->Ssid.SsidLength;
-+
-+		wrqu->essid.length = len;
-+
-+		_rtw_memcpy(extra, pcur_bss->Ssid.Ssid, len);
-+
-+		wrqu->essid.flags = 1;
-+	} else {
-+		ret = -1;
-+		goto exit;
-+	}
-+
-+exit:
-+
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_wx_set_rate(struct net_device *dev,
-+			   struct iw_request_info *a,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+#if 0
-+	int i;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8	datarates[NumRates];
-+	u32	target_rate = wrqu->bitrate.value;
-+	u32	fixed = wrqu->bitrate.fixed;
-+	u32	ratevalue = 0;
-+	u8 mpdatarate[NumRates] = {11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0xff};
-+
-+
-+
-+	if (target_rate == -1) {
-+		ratevalue = 11;
-+		goto set_rate;
-+	}
-+	target_rate = target_rate / 100000;
-+
-+	switch (target_rate) {
-+	case 10:
-+		ratevalue = 0;
-+		break;
-+	case 20:
-+		ratevalue = 1;
-+		break;
-+	case 55:
-+		ratevalue = 2;
-+		break;
-+	case 60:
-+		ratevalue = 3;
-+		break;
-+	case 90:
-+		ratevalue = 4;
-+		break;
-+	case 110:
-+		ratevalue = 5;
-+		break;
-+	case 120:
-+		ratevalue = 6;
-+		break;
-+	case 180:
-+		ratevalue = 7;
-+		break;
-+	case 240:
-+		ratevalue = 8;
-+		break;
-+	case 360:
-+		ratevalue = 9;
-+		break;
-+	case 480:
-+		ratevalue = 10;
-+		break;
-+	case 540:
-+		ratevalue = 11;
-+		break;
-+	default:
-+		ratevalue = 11;
-+		break;
-+	}
-+
-+set_rate:
-+
-+	for (i = 0; i < NumRates; i++) {
-+		if (ratevalue == mpdatarate[i]) {
-+			datarates[i] = mpdatarate[i];
-+			if (fixed == 0)
-+				break;
-+		} else
-+			datarates[i] = 0xff;
-+
-+	}
-+
-+	if (rtw_setdatarate_cmd(padapter, datarates) != _SUCCESS) {
-+		ret = -1;
-+	}
-+
-+#endif
-+	return ret;
-+}
-+
-+static int rtw_wx_get_rate(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+	u16 max_rate = 0;
-+
-+	max_rate = rtw_get_cur_max_rate((_adapter *)rtw_netdev_priv(dev));
-+
-+	if (max_rate == 0)
-+		return -EPERM;
-+
-+	wrqu->bitrate.fixed = 0;	/* no auto select */
-+	wrqu->bitrate.value = max_rate * 100000;
-+
-+	return 0;
-+}
-+
-+static int rtw_wx_set_rts(struct net_device *dev,
-+			  struct iw_request_info *info,
-+			  union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+
-+	if (wrqu->rts.disabled)
-+		padapter->registrypriv.rts_thresh = 2347;
-+	else {
-+		if (wrqu->rts.value < 0 ||
-+		    wrqu->rts.value > 2347)
-+			return -EINVAL;
-+
-+		padapter->registrypriv.rts_thresh = wrqu->rts.value;
-+	}
-+
-+	RTW_INFO("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh);
-+
-+
-+	return 0;
-+
-+}
-+
-+static int rtw_wx_get_rts(struct net_device *dev,
-+			  struct iw_request_info *info,
-+			  union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+
-+	RTW_INFO("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh);
-+
-+	wrqu->rts.value = padapter->registrypriv.rts_thresh;
-+	wrqu->rts.fixed = 0;	/* no auto select */
-+	/* wrqu->rts.disabled = (wrqu->rts.value == DEFAULT_RTS_THRESHOLD); */
-+
-+
-+	return 0;
-+}
-+
-+static int rtw_wx_set_frag(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+
-+	if (wrqu->frag.disabled)
-+		padapter->xmitpriv.frag_len = MAX_FRAG_THRESHOLD;
-+	else {
-+		if (wrqu->frag.value < MIN_FRAG_THRESHOLD ||
-+		    wrqu->frag.value > MAX_FRAG_THRESHOLD)
-+			return -EINVAL;
-+
-+		padapter->xmitpriv.frag_len = wrqu->frag.value & ~0x1;
-+	}
-+
-+	RTW_INFO("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len);
-+
-+
-+	return 0;
-+
-+}
-+
-+static int rtw_wx_get_frag(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+
-+	RTW_INFO("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len);
-+
-+	wrqu->frag.value = padapter->xmitpriv.frag_len;
-+	wrqu->frag.fixed = 0;	/* no auto select */
-+	/* wrqu->frag.disabled = (wrqu->frag.value == DEFAULT_FRAG_THRESHOLD); */
-+
-+
-+	return 0;
-+}
-+
-+static int rtw_wx_get_retry(struct net_device *dev,
-+			    struct iw_request_info *info,
-+			    union iwreq_data *wrqu, char *extra)
-+{
-+	/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */
-+
-+
-+	wrqu->retry.value = 7;
-+	wrqu->retry.fixed = 0;	/* no auto select */
-+	wrqu->retry.disabled = 1;
-+
-+	return 0;
-+
-+}
-+
-+#if 0
-+	#define IW_ENCODE_INDEX		0x00FF	/* Token index (if needed) */
-+	#define IW_ENCODE_FLAGS		0xFF00	/* Flags defined below */
-+	#define IW_ENCODE_MODE		0xF000	/* Modes defined below */
-+	#define IW_ENCODE_DISABLED	0x8000	/* Encoding disabled */
-+	#define IW_ENCODE_ENABLED	0x0000	/* Encoding enabled */
-+	#define IW_ENCODE_RESTRICTED	0x4000	/* Refuse non-encoded packets */
-+	#define IW_ENCODE_OPEN		0x2000	/* Accept non-encoded packets */
-+	#define IW_ENCODE_NOKEY		0x0800  /* Key is write only, so not present */
-+	#define IW_ENCODE_TEMP		0x0400  /* Temporary key */
-+	/*
-+	iwconfig wlan0 key on->flags = 0x6001->maybe it means auto
-+	iwconfig wlan0 key off->flags = 0x8800
-+	iwconfig wlan0 key open->flags = 0x2800
-+	iwconfig wlan0 key open 1234567890->flags = 0x2000
-+	iwconfig wlan0 key restricted->flags = 0x4800
-+	iwconfig wlan0 key open [3] 1234567890->flags = 0x2003
-+	iwconfig wlan0 key restricted [2] 1234567890->flags = 0x4002
-+	iwconfig wlan0 key open [3] -> flags = 0x2803
-+	iwconfig wlan0 key restricted [2] -> flags = 0x4802
-+	*/
-+#endif
-+
-+static int rtw_wx_set_enc(struct net_device *dev,
-+			  struct iw_request_info *info,
-+			  union iwreq_data *wrqu, char *keybuf)
-+{
-+	u32 key, ret = 0;
-+	u32 keyindex_provided;
-+	NDIS_802_11_WEP	 wep;
-+	NDIS_802_11_AUTHENTICATION_MODE authmode;
-+
-+	struct iw_point *erq = &(wrqu->encoding);
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	RTW_INFO("+rtw_wx_set_enc, flags=0x%x\n", erq->flags);
-+
-+	_rtw_memset(&wep, 0, sizeof(NDIS_802_11_WEP));
-+
-+	key = erq->flags & IW_ENCODE_INDEX;
-+
-+
-+	if (erq->flags & IW_ENCODE_DISABLED) {
-+		RTW_INFO("EncryptionDisabled\n");
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
-+		padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
-+		padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
-+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
-+		authmode = Ndis802_11AuthModeOpen;
-+		padapter->securitypriv.ndisauthtype = authmode;
-+
-+		goto exit;
-+	}
-+
-+	if (key) {
-+		if (key > WEP_KEYS)
-+			return -EINVAL;
-+		key--;
-+		keyindex_provided = 1;
-+	} else {
-+		keyindex_provided = 0;
-+		key = padapter->securitypriv.dot11PrivacyKeyIndex;
-+		RTW_INFO("rtw_wx_set_enc, key=%d\n", key);
-+	}
-+
-+	/* set authentication mode	 */
-+	if (erq->flags & IW_ENCODE_OPEN) {
-+		RTW_INFO("rtw_wx_set_enc():IW_ENCODE_OPEN\n");
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;/* Ndis802_11EncryptionDisabled; */
-+
-+#ifdef CONFIG_PLATFORM_MT53XX
-+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
-+#else
-+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
-+#endif
-+
-+		padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
-+		padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
-+		authmode = Ndis802_11AuthModeOpen;
-+		padapter->securitypriv.ndisauthtype = authmode;
-+	} else if (erq->flags & IW_ENCODE_RESTRICTED) {
-+		RTW_INFO("rtw_wx_set_enc():IW_ENCODE_RESTRICTED\n");
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+
-+#ifdef CONFIG_PLATFORM_MT53XX
-+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
-+#else
-+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Shared;
-+#endif
-+
-+		padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;
-+		padapter->securitypriv.dot118021XGrpPrivacy = _WEP40_;
-+		authmode = Ndis802_11AuthModeShared;
-+		padapter->securitypriv.ndisauthtype = authmode;
-+	} else {
-+		RTW_INFO("rtw_wx_set_enc():erq->flags=0x%x\n", erq->flags);
-+
-+		padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;/* Ndis802_11EncryptionDisabled; */
-+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
-+		padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
-+		padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
-+		authmode = Ndis802_11AuthModeOpen;
-+		padapter->securitypriv.ndisauthtype = authmode;
-+	}
-+
-+	wep.KeyIndex = key;
-+	if (erq->length > 0) {
-+		wep.KeyLength = erq->length <= 5 ? 5 : 13;
-+
-+		wep.Length = wep.KeyLength + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);
-+	} else {
-+		wep.KeyLength = 0 ;
-+
-+		if (keyindex_provided == 1) { /* set key_id only, no given KeyMaterial(erq->length==0). */
-+			padapter->securitypriv.dot11PrivacyKeyIndex = key;
-+
-+			RTW_INFO("(keyindex_provided == 1), keyid=%d, key_len=%d\n", key, padapter->securitypriv.dot11DefKeylen[key]);
-+
-+			switch (padapter->securitypriv.dot11DefKeylen[key]) {
-+			case 5:
-+				padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;
-+				break;
-+			case 13:
-+				padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;
-+				break;
-+			default:
-+				padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
-+				break;
-+			}
-+
-+			goto exit;
-+
-+		}
-+
-+	}
-+
-+	wep.KeyIndex |= 0x80000000;
-+
-+	_rtw_memcpy(wep.KeyMaterial, keybuf, wep.KeyLength);
-+
-+	if (rtw_set_802_11_add_wep(padapter, &wep) == _FALSE) {
-+		if (rf_on == pwrpriv->rf_pwrstate)
-+			ret = -EOPNOTSUPP;
-+		goto exit;
-+	}
-+
-+exit:
-+
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_wx_get_enc(struct net_device *dev,
-+			  struct iw_request_info *info,
-+			  union iwreq_data *wrqu, char *keybuf)
-+{
-+	uint key, ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct iw_point *erq = &(wrqu->encoding);
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) != _TRUE) {
-+		if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE) {
-+			erq->length = 0;
-+			erq->flags |= IW_ENCODE_DISABLED;
-+			return 0;
-+		}
-+	}
-+
-+
-+	key = erq->flags & IW_ENCODE_INDEX;
-+
-+	if (key) {
-+		if (key > WEP_KEYS)
-+			return -EINVAL;
-+		key--;
-+	} else
-+		key = padapter->securitypriv.dot11PrivacyKeyIndex;
-+
-+	erq->flags = key + 1;
-+
-+	/* if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen) */
-+	/* { */
-+	/* erq->flags |= IW_ENCODE_OPEN; */
-+	/* }	  */
-+
-+	switch (padapter->securitypriv.ndisencryptstatus) {
-+	case Ndis802_11EncryptionNotSupported:
-+	case Ndis802_11EncryptionDisabled:
-+
-+		erq->length = 0;
-+		erq->flags |= IW_ENCODE_DISABLED;
-+
-+		break;
-+
-+	case Ndis802_11Encryption1Enabled:
-+
-+		erq->length = padapter->securitypriv.dot11DefKeylen[key];
-+
-+		if (erq->length) {
-+			_rtw_memcpy(keybuf, padapter->securitypriv.dot11DefKey[key].skey, padapter->securitypriv.dot11DefKeylen[key]);
-+
-+			erq->flags |= IW_ENCODE_ENABLED;
-+
-+			if (padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen)
-+				erq->flags |= IW_ENCODE_OPEN;
-+			else if (padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeShared)
-+				erq->flags |= IW_ENCODE_RESTRICTED;
-+		} else {
-+			erq->length = 0;
-+			erq->flags |= IW_ENCODE_DISABLED;
-+		}
-+
-+		break;
-+
-+	case Ndis802_11Encryption2Enabled:
-+	case Ndis802_11Encryption3Enabled:
-+
-+		erq->length = 16;
-+		erq->flags |= (IW_ENCODE_ENABLED | IW_ENCODE_OPEN | IW_ENCODE_NOKEY);
-+
-+		break;
-+
-+	default:
-+		erq->length = 0;
-+		erq->flags |= IW_ENCODE_DISABLED;
-+
-+		break;
-+
-+	}
-+
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_wx_get_power(struct net_device *dev,
-+			    struct iw_request_info *info,
-+			    union iwreq_data *wrqu, char *extra)
-+{
-+	/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */
-+
-+	wrqu->power.value = 0;
-+	wrqu->power.fixed = 0;	/* no auto select */
-+	wrqu->power.disabled = 1;
-+
-+	return 0;
-+
-+}
-+
-+static int rtw_wx_set_gen_ie(struct net_device *dev,
-+			     struct iw_request_info *info,
-+			     union iwreq_data *wrqu, char *extra)
-+{
-+	int ret;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	ret = rtw_set_wpa_ie(padapter, extra, wrqu->data.length);
-+
-+	return ret;
-+}
-+
-+static int rtw_wx_set_auth(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct iw_param *param = (struct iw_param *)&(wrqu->param);
-+#ifdef CONFIG_WAPI_SUPPORT
-+#ifndef CONFIG_IOCTL_CFG80211
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	u32 value = param->value;
-+#endif
-+#endif
-+	int ret = 0;
-+
-+	switch (param->flags & IW_AUTH_INDEX) {
-+
-+	case IW_AUTH_WPA_VERSION:
-+#ifdef CONFIG_WAPI_SUPPORT
-+#ifndef CONFIG_IOCTL_CFG80211
-+		padapter->wapiInfo.bWapiEnable = false;
-+		if (value == IW_AUTH_WAPI_VERSION_1) {
-+			padapter->wapiInfo.bWapiEnable = true;
-+			psecuritypriv->dot11PrivacyAlgrthm = _SMS4_;
-+			psecuritypriv->dot118021XGrpPrivacy = _SMS4_;
-+			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI;
-+			pmlmeinfo->auth_algo = psecuritypriv->dot11AuthAlgrthm;
-+			padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN;
-+			padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN;
-+		}
-+#endif
-+#endif
-+		break;
-+	case IW_AUTH_CIPHER_PAIRWISE:
-+
-+		break;
-+	case IW_AUTH_CIPHER_GROUP:
-+
-+		break;
-+	case IW_AUTH_KEY_MGMT:
-+#ifdef CONFIG_WAPI_SUPPORT
-+#ifndef CONFIG_IOCTL_CFG80211
-+		RTW_INFO("rtw_wx_set_auth: IW_AUTH_KEY_MGMT case\n");
-+		if (value == IW_AUTH_KEY_MGMT_WAPI_PSK)
-+			padapter->wapiInfo.bWapiPSK = true;
-+		else
-+			padapter->wapiInfo.bWapiPSK = false;
-+		RTW_INFO("rtw_wx_set_auth: IW_AUTH_KEY_MGMT bwapipsk %d\n", padapter->wapiInfo.bWapiPSK);
-+#endif
-+#endif
-+		/*
-+		 *  ??? does not use these parameters
-+		 */
-+		break;
-+
-+	case IW_AUTH_TKIP_COUNTERMEASURES: {
-+		if (param->value) {
-+			/* wpa_supplicant is enabling the tkip countermeasure. */
-+			padapter->securitypriv.btkip_countermeasure = _TRUE;
-+		} else {
-+			/* wpa_supplicant is disabling the tkip countermeasure. */
-+			padapter->securitypriv.btkip_countermeasure = _FALSE;
-+		}
-+		break;
-+	}
-+	case IW_AUTH_DROP_UNENCRYPTED: {
-+		/* HACK:
-+		 *
-+		 * wpa_supplicant calls set_wpa_enabled when the driver
-+		 * is loaded and unloaded, regardless of if WPA is being
-+		 * used.  No other calls are made which can be used to
-+		 * determine if encryption will be used or not prior to
-+		 * association being expected.  If encryption is not being
-+		 * used, drop_unencrypted is set to false, else true -- we
-+		 * can use this to determine if the CAP_PRIVACY_ON bit should
-+		 * be set.
-+		 */
-+
-+		if (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption1Enabled) {
-+			break;/* it means init value, or using wep, ndisencryptstatus = Ndis802_11Encryption1Enabled, */
-+			/* then it needn't reset it; */
-+		}
-+
-+		if (param->value) {
-+			padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled;
-+			padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
-+			padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_;
-+			padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
-+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
-+		}
-+
-+		break;
-+	}
-+
-+	case IW_AUTH_80211_AUTH_ALG:
-+
-+#if defined(CONFIG_RTW_ANDROID) || 1
-+		/*
-+		 *  It's the starting point of a link layer connection using wpa_supplicant
-+		*/
-+		if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) {
-+			LeaveAllPowerSaveMode(padapter);
-+			rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK);
-+			RTW_INFO("%s...call rtw_indicate_disconnect\n ", __FUNCTION__);
-+			rtw_indicate_disconnect(padapter, 0, _FALSE);
-+			rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK);
-+		}
-+#endif
-+
-+
-+		ret = wpa_set_auth_algs(dev, (u32)param->value);
-+
-+		break;
-+
-+	case IW_AUTH_WPA_ENABLED:
-+
-+		/* if(param->value) */
-+		/* padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; */ /* 802.1x */
-+		/* else */
-+		/* padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; */ /* open system */
-+
-+		/* _disassociate(priv); */
-+
-+		break;
-+
-+	case IW_AUTH_RX_UNENCRYPTED_EAPOL:
-+		/* ieee->ieee802_1x = param->value; */
-+		break;
-+
-+	case IW_AUTH_PRIVACY_INVOKED:
-+		/* ieee->privacy_invoked = param->value; */
-+		break;
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+#ifndef CONFIG_IOCTL_CFG80211
-+	case IW_AUTH_WAPI_ENABLED:
-+		break;
-+#endif
-+#endif
-+
-+	default:
-+		return -EOPNOTSUPP;
-+
-+	}
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_wx_set_enc_ext(struct net_device *dev,
-+			      struct iw_request_info *info,
-+			      union iwreq_data *wrqu, char *extra)
-+{
-+	char *alg_name;
-+	u32 param_len;
-+	struct ieee_param *param = NULL;
-+	struct iw_point *pencoding = &wrqu->encoding;
-+	struct iw_encode_ext *pext = (struct iw_encode_ext *)extra;
-+	int ret = 0;
-+
-+	param_len = sizeof(struct ieee_param) + pext->key_len;
-+	param = (struct ieee_param *)rtw_malloc(param_len);
-+	if (param == NULL)
-+		return -1;
-+
-+	_rtw_memset(param, 0, param_len);
-+
-+	param->cmd = IEEE_CMD_SET_ENCRYPTION;
-+	_rtw_memset(param->sta_addr, 0xff, ETH_ALEN);
-+
-+
-+	switch (pext->alg) {
-+	case IW_ENCODE_ALG_NONE:
-+		/* todo: remove key */
-+		/* remove = 1;	 */
-+		alg_name = "none";
-+		break;
-+	case IW_ENCODE_ALG_WEP:
-+		alg_name = "WEP";
-+		break;
-+	case IW_ENCODE_ALG_TKIP:
-+		alg_name = "TKIP";
-+		break;
-+	case IW_ENCODE_ALG_CCMP:
-+		alg_name = "CCMP";
-+		break;
-+#ifdef CONFIG_IEEE80211W
-+	case IW_ENCODE_ALG_AES_CMAC:
-+		alg_name = "BIP";
-+		break;
-+#endif /* CONFIG_IEEE80211W */
-+#ifdef CONFIG_WAPI_SUPPORT
-+#ifndef CONFIG_IOCTL_CFG80211
-+	case IW_ENCODE_ALG_SM4:
-+		alg_name = "SMS4";
-+		_rtw_memcpy(param->sta_addr, pext->addr.sa_data, ETH_ALEN);
-+		RTW_INFO("rtw_wx_set_enc_ext: SMS4 case\n");
-+		break;
-+#endif
-+#endif
-+	default:
-+		ret = -1;
-+		goto exit;
-+	}
-+
-+	strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN);
-+
-+	if (pext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY)
-+		param->u.crypt.set_tx = 1;
-+
-+	/* cliW: WEP does not have group key
-+	 * just not checking GROUP key setting
-+	 */
-+	if ((pext->alg != IW_ENCODE_ALG_WEP) &&
-+	    ((pext->ext_flags & IW_ENCODE_EXT_GROUP_KEY)
-+#ifdef CONFIG_IEEE80211W
-+	     || (pext->ext_flags & IW_ENCODE_ALG_AES_CMAC)
-+#endif /* CONFIG_IEEE80211W */
-+	    ))
-+		param->u.crypt.set_tx = 0;
-+
-+	param->u.crypt.idx = (pencoding->flags & 0x00FF) - 1 ;
-+
-+	if (pext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) {
-+#ifdef CONFIG_WAPI_SUPPORT
-+#ifndef CONFIG_IOCTL_CFG80211
-+		if (pext->alg == IW_ENCODE_ALG_SM4)
-+			_rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 16);
-+		else
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+#endif /* CONFIG_WAPI_SUPPORT */
-+			_rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 8);
-+	}
-+
-+	if (pext->key_len) {
-+		param->u.crypt.key_len = pext->key_len;
-+		/* _rtw_memcpy(param + 1, pext + 1, pext->key_len); */
-+		_rtw_memcpy(param->u.crypt.key, pext + 1, pext->key_len);
-+	}
-+
-+	if (pencoding->flags & IW_ENCODE_DISABLED) {
-+		/* todo: remove key */
-+		/* remove = 1; */
-+	}
-+
-+	ret =  wpa_set_encryption(dev, param, param_len);
-+
-+exit:
-+	if (param)
-+		rtw_mfree((u8 *)param, param_len);
-+
-+	return ret;
-+}
-+
-+
-+static int rtw_wx_get_nick(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+	/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */
-+	/* struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); */
-+	/* struct security_priv *psecuritypriv = &padapter->securitypriv; */
-+
-+	if (extra) {
-+		wrqu->data.length = 14;
-+		wrqu->data.flags = 1;
-+		_rtw_memcpy(extra, "<WIFI@REALTEK>", 14);
-+	}
-+
-+	/* rtw_signal_process(pid, SIGUSR1); */ /* for test */
-+
-+	/* dump debug info here	 */
-+#if 0
-+	u32 dot11AuthAlgrthm;		/*  802.11 auth, could be open, shared, and 8021x */
-+	u32 dot11PrivacyAlgrthm;	/*  This specify the privacy for shared auth. algorithm. */
-+	u32 dot118021XGrpPrivacy;	/*  This specify the privacy algthm. used for Grp key */
-+	u32 ndisauthtype;
-+	u32 ndisencryptstatus;
-+#endif
-+
-+	/* RTW_INFO("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n",  */
-+	/*		psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, */
-+	/*		psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); */
-+
-+	/* RTW_INFO("enc_alg=0x%x\n", psecuritypriv->dot11PrivacyAlgrthm); */
-+	/* RTW_INFO("auth_type=0x%x\n", psecuritypriv->ndisauthtype); */
-+	/* RTW_INFO("enc_type=0x%x\n", psecuritypriv->ndisencryptstatus); */
-+
-+#if 0
-+	RTW_INFO("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210));
-+	RTW_INFO("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608));
-+	RTW_INFO("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280));
-+	RTW_INFO("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284));
-+	RTW_INFO("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288));
-+
-+	RTW_INFO("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664));
-+
-+
-+	RTW_INFO("\n");
-+
-+	RTW_INFO("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430));
-+	RTW_INFO("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438));
-+
-+	RTW_INFO("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440));
-+
-+	RTW_INFO("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458));
-+
-+	RTW_INFO("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484));
-+	RTW_INFO("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488));
-+
-+	RTW_INFO("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444));
-+	RTW_INFO("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448));
-+	RTW_INFO("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c));
-+	RTW_INFO("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450));
-+#endif
-+
-+	return 0;
-+
-+}
-+#endif
-+
-+static int rtw_wx_read32(struct net_device *dev,
-+			 struct iw_request_info *info,
-+			 union iwreq_data *wrqu, char *extra)
-+{
-+	PADAPTER padapter;
-+	struct iw_point *p;
-+	u16 len;
-+	u32 addr;
-+	u32 data32;
-+	u32 bytes;
-+	u8 *ptmp;
-+	int ret;
-+
-+
-+	ret = 0;
-+	padapter = (PADAPTER)rtw_netdev_priv(dev);
-+	p = &wrqu->data;
-+	len = p->length;
-+	if (0 == len)
-+		return -EINVAL;
-+
-+	ptmp = (u8 *)rtw_malloc(len);
-+	if (NULL == ptmp)
-+		return -ENOMEM;
-+
-+	if (copy_from_user(ptmp, p->pointer, len)) {
-+		ret = -EFAULT;
-+		goto exit;
-+	}
-+
-+	bytes = 0;
-+	addr = 0;
-+	sscanf(ptmp, "%d,%x", &bytes, &addr);
-+
-+	switch (bytes) {
-+	case 1:
-+		data32 = rtw_read8(padapter, addr);
-+		sprintf(extra, "0x%02X", data32);
-+		break;
-+	case 2:
-+		data32 = rtw_read16(padapter, addr);
-+		sprintf(extra, "0x%04X", data32);
-+		break;
-+	case 4:
-+		data32 = rtw_read32(padapter, addr);
-+		sprintf(extra, "0x%08X", data32);
-+		break;
-+
-+	#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_SDIO_INDIRECT_ACCESS) && defined(DBG_SDIO_INDIRECT_ACCESS)
-+	case 11:
-+		data32 = rtw_sd_iread8(padapter, addr);
-+		sprintf(extra, "0x%02X", data32);
-+		break;
-+	case 12:
-+		data32 = rtw_sd_iread16(padapter, addr);
-+		sprintf(extra, "0x%04X", data32);
-+		break;
-+	case 14:
-+		data32 = rtw_sd_iread32(padapter, addr);
-+		sprintf(extra, "0x%08X", data32);
-+		break;
-+	#endif
-+	default:
-+		RTW_INFO("%s: usage> read [bytes],[address(hex)]\n", __func__);
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+	RTW_INFO("%s: addr=0x%08X data=%s\n", __func__, addr, extra);
-+
-+exit:
-+	rtw_mfree(ptmp, len);
-+
-+	return 0;
-+}
-+
-+static int rtw_wx_write32(struct net_device *dev,
-+			  struct iw_request_info *info,
-+			  union iwreq_data *wrqu, char *extra)
-+{
-+	PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev);
-+
-+	u32 addr;
-+	u32 data32;
-+	u32 bytes;
-+
-+
-+	bytes = 0;
-+	addr = 0;
-+	data32 = 0;
-+	sscanf(extra, "%d,%x,%x", &bytes, &addr, &data32);
-+
-+	switch (bytes) {
-+	case 1:
-+		rtw_write8(padapter, addr, (u8)data32);
-+		RTW_INFO("%s: addr=0x%08X data=0x%02X\n", __func__, addr, (u8)data32);
-+		break;
-+	case 2:
-+		rtw_write16(padapter, addr, (u16)data32);
-+		RTW_INFO("%s: addr=0x%08X data=0x%04X\n", __func__, addr, (u16)data32);
-+		break;
-+	case 4:
-+		rtw_write32(padapter, addr, data32);
-+		RTW_INFO("%s: addr=0x%08X data=0x%08X\n", __func__, addr, data32);
-+		break;
-+	default:
-+		RTW_INFO("%s: usage> write [bytes],[address(hex)],[data(hex)]\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int rtw_wx_read_rf(struct net_device *dev,
-+			  struct iw_request_info *info,
-+			  union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u32 path, addr, data32;
-+
-+
-+	path = *(u32 *)extra;
-+	addr = *((u32 *)extra + 1);
-+	data32 = rtw_hal_read_rfreg(padapter, path, addr, 0xFFFFF);
-+	/*	RTW_INFO("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); */
-+	/*
-+	 * IMPORTANT!!
-+	 * Only when wireless private ioctl is at odd order,
-+	 * "extra" would be copied to user space.
-+	 */
-+	sprintf(extra, "0x%05x", data32);
-+
-+	return 0;
-+}
-+
-+static int rtw_wx_write_rf(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u32 path, addr, data32;
-+
-+
-+	path = *(u32 *)extra;
-+	addr = *((u32 *)extra + 1);
-+	data32 = *((u32 *)extra + 2);
-+	/*	RTW_INFO("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); */
-+	rtw_hal_write_rfreg(padapter, path, addr, 0xFFFFF, data32);
-+
-+	return 0;
-+}
-+
-+static int rtw_wx_priv_null(struct net_device *dev, struct iw_request_info *a,
-+			    union iwreq_data *wrqu, char *b)
-+{
-+	return -1;
-+}
-+
-+#ifdef CONFIG_RTW_80211K
-+extern void rm_dbg_cmd(_adapter *padapter, char *s);
-+static int rtw_wx_priv_rrm(struct net_device *dev, struct iw_request_info *a,
-+			    union iwreq_data *wrqu, char *b)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u32 path, addr, data32;
-+
-+
-+	rm_dbg_cmd(padapter, b);
-+	wrqu->data.length = strlen(b);
-+
-+	return 0;
-+}
-+#endif
-+
-+#ifdef CONFIG_IOCTL_WEXT
-+static int dummy(struct net_device *dev, struct iw_request_info *a,
-+		 union iwreq_data *wrqu, char *b)
-+{
-+	/* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);	 */
-+	/* struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); */
-+
-+	/* RTW_INFO("cmd_code=%x, fwstate=0x%x\n", a->cmd, get_fwstate(pmlmepriv)); */
-+
-+	return -1;
-+
-+}
-+#endif
-+
-+static int rtw_wx_set_channel_plan(struct net_device *dev,
-+				   struct iw_request_info *info,
-+				   union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 channel_plan_req = (u8)(*((int *)wrqu));
-+
-+	if (_SUCCESS != rtw_set_channel_plan(padapter, channel_plan_req))
-+		return -EPERM;
-+
-+	return 0;
-+}
-+
-+static int rtw_wx_set_mtk_wps_probe_ie(struct net_device *dev,
-+				       struct iw_request_info *a,
-+				       union iwreq_data *wrqu, char *b)
-+{
-+#ifdef CONFIG_PLATFORM_MT53XX
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+#endif
-+	return 0;
-+}
-+
-+static int rtw_wx_get_sensitivity(struct net_device *dev,
-+				  struct iw_request_info *info,
-+				  union iwreq_data *wrqu, char *buf)
-+{
-+#ifdef CONFIG_PLATFORM_MT53XX
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	/*	Modified by Albert 20110914 */
-+	/*	This is in dbm format for MTK platform. */
-+	wrqu->qual.level = padapter->recvpriv.rssi;
-+	RTW_INFO(" level = %u\n",  wrqu->qual.level);
-+#endif
-+	return 0;
-+}
-+
-+static int rtw_wx_set_mtk_wps_ie(struct net_device *dev,
-+				 struct iw_request_info *info,
-+				 union iwreq_data *wrqu, char *extra)
-+{
-+#ifdef CONFIG_PLATFORM_MT53XX
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	return rtw_set_wpa_ie(padapter, wrqu->data.pointer, wrqu->data.length);
-+#else
-+	return 0;
-+#endif
-+}
-+
-+#ifdef MP_IOCTL_HDL
-+static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len)
-+{
-+	pRW_Reg	RegRWStruct;
-+	struct rf_reg_param *prfreg;
-+	u8 path;
-+	u8 offset;
-+	u32 value;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	switch (id) {
-+	case GEN_MP_IOCTL_SUBCODE(MP_START):
-+		RTW_INFO("871x_driver is only for normal mode, can't enter mp mode\n");
-+		break;
-+	case GEN_MP_IOCTL_SUBCODE(READ_REG):
-+		RegRWStruct = (pRW_Reg)pdata;
-+		switch (RegRWStruct->width) {
-+		case 1:
-+			RegRWStruct->value = rtw_read8(padapter, RegRWStruct->offset);
-+			break;
-+		case 2:
-+			RegRWStruct->value = rtw_read16(padapter, RegRWStruct->offset);
-+			break;
-+		case 4:
-+			RegRWStruct->value = rtw_read32(padapter, RegRWStruct->offset);
-+			break;
-+		default:
-+			break;
-+		}
-+
-+		break;
-+	case GEN_MP_IOCTL_SUBCODE(WRITE_REG):
-+		RegRWStruct = (pRW_Reg)pdata;
-+		switch (RegRWStruct->width) {
-+		case 1:
-+			rtw_write8(padapter, RegRWStruct->offset, (u8)RegRWStruct->value);
-+			break;
-+		case 2:
-+			rtw_write16(padapter, RegRWStruct->offset, (u16)RegRWStruct->value);
-+			break;
-+		case 4:
-+			rtw_write32(padapter, RegRWStruct->offset, (u32)RegRWStruct->value);
-+			break;
-+		default:
-+			break;
-+		}
-+
-+		break;
-+	case GEN_MP_IOCTL_SUBCODE(READ_RF_REG):
-+
-+		prfreg = (struct rf_reg_param *)pdata;
-+
-+		path = (u8)prfreg->path;
-+		offset = (u8)prfreg->offset;
-+
-+		value = rtw_hal_read_rfreg(padapter, path, offset, 0xffffffff);
-+
-+		prfreg->value = value;
-+
-+		break;
-+	case GEN_MP_IOCTL_SUBCODE(WRITE_RF_REG):
-+
-+		prfreg = (struct rf_reg_param *)pdata;
-+
-+		path = (u8)prfreg->path;
-+		offset = (u8)prfreg->offset;
-+		value = prfreg->value;
-+
-+		rtw_hal_write_rfreg(padapter, path, offset, 0xffffffff, value);
-+
-+		break;
-+	case GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO):
-+		RTW_INFO("==> trigger gpio 0\n");
-+		rtw_hal_set_hwreg(padapter, HW_VAR_TRIGGER_GPIO_0, 0);
-+		break;
-+#ifdef CONFIG_BT_COEXIST
-+	case GEN_MP_IOCTL_SUBCODE(SET_DM_BT):
-+		RTW_INFO("==> set dm_bt_coexist:%x\n", *(u8 *)pdata);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_BT_SET_COEXIST, pdata);
-+		break;
-+	case GEN_MP_IOCTL_SUBCODE(DEL_BA):
-+		RTW_INFO("==> delete ba:%x\n", *(u8 *)pdata);
-+		rtw_hal_set_hwreg(padapter, HW_VAR_BT_ISSUE_DELBA, pdata);
-+		break;
-+#endif
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	case GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS):
-+		*pdata = rtw_hal_sreset_get_wifi_status(padapter);
-+		break;
-+#endif
-+
-+	default:
-+		break;
-+	}
-+
-+}
-+static int rtw_mp_ioctl_hdl(struct net_device *dev, struct iw_request_info *info,
-+			    union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+	u32 BytesRead, BytesWritten, BytesNeeded;
-+	struct oid_par_priv	oid_par;
-+	struct mp_ioctl_handler	*phandler;
-+	struct mp_ioctl_param	*poidparam;
-+	uint status = 0;
-+	u16 len;
-+	u8 *pparmbuf = NULL, bset;
-+	PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev);
-+	struct iw_point *p = &wrqu->data;
-+
-+	/* RTW_INFO("+rtw_mp_ioctl_hdl\n"); */
-+
-+	/* mutex_lock(&ioctl_mutex); */
-+
-+	if ((!p->length) || (!p->pointer)) {
-+		ret = -EINVAL;
-+		goto _rtw_mp_ioctl_hdl_exit;
-+	}
-+
-+	pparmbuf = NULL;
-+	bset = (u8)(p->flags & 0xFFFF);
-+	len = p->length;
-+	pparmbuf = (u8 *)rtw_malloc(len);
-+	if (pparmbuf == NULL) {
-+		ret = -ENOMEM;
-+		goto _rtw_mp_ioctl_hdl_exit;
-+	}
-+
-+	if (copy_from_user(pparmbuf, p->pointer, len)) {
-+		ret = -EFAULT;
-+		goto _rtw_mp_ioctl_hdl_exit;
-+	}
-+
-+	poidparam = (struct mp_ioctl_param *)pparmbuf;
-+
-+	if (poidparam->subcode >= MAX_MP_IOCTL_SUBCODE) {
-+		ret = -EINVAL;
-+		goto _rtw_mp_ioctl_hdl_exit;
-+	}
-+
-+	/* RTW_INFO("%s: %d\n", __func__, poidparam->subcode); */
-+#ifdef CONFIG_MP_INCLUDED
-+	if (padapter->registrypriv.mp_mode == 1) {
-+		phandler = mp_ioctl_hdl + poidparam->subcode;
-+
-+		if ((phandler->paramsize != 0) && (poidparam->len < phandler->paramsize)) {
-+			ret = -EINVAL;
-+			goto _rtw_mp_ioctl_hdl_exit;
-+		}
-+
-+		if (phandler->handler) {
-+			oid_par.adapter_context = padapter;
-+			oid_par.oid = phandler->oid;
-+			oid_par.information_buf = poidparam->data;
-+			oid_par.information_buf_len = poidparam->len;
-+			oid_par.dbg = 0;
-+
-+			BytesWritten = 0;
-+			BytesNeeded = 0;
-+
-+			if (bset) {
-+				oid_par.bytes_rw = &BytesRead;
-+				oid_par.bytes_needed = &BytesNeeded;
-+				oid_par.type_of_oid = SET_OID;
-+			} else {
-+				oid_par.bytes_rw = &BytesWritten;
-+				oid_par.bytes_needed = &BytesNeeded;
-+				oid_par.type_of_oid = QUERY_OID;
-+			}
-+
-+			status = phandler->handler(&oid_par);
-+
-+			/* todo:check status, BytesNeeded, etc. */
-+		} else {
-+			RTW_INFO("rtw_mp_ioctl_hdl(): err!, subcode=%d, oid=%d, handler=%p\n",
-+				poidparam->subcode, phandler->oid, phandler->handler);
-+			ret = -EFAULT;
-+			goto _rtw_mp_ioctl_hdl_exit;
-+		}
-+	} else
-+#endif
-+	{
-+		rtw_dbg_mode_hdl(padapter, poidparam->subcode, poidparam->data, poidparam->len);
-+	}
-+
-+	if (bset == 0x00) {/* query info */
-+		if (copy_to_user(p->pointer, pparmbuf, len))
-+			ret = -EFAULT;
-+	}
-+
-+	if (status) {
-+		ret = -EFAULT;
-+		goto _rtw_mp_ioctl_hdl_exit;
-+	}
-+
-+_rtw_mp_ioctl_hdl_exit:
-+
-+	if (pparmbuf)
-+		rtw_mfree(pparmbuf, len);
-+
-+	/* mutex_unlock(&ioctl_mutex); */
-+
-+	return ret;
-+}
-+#endif /*MP_IOCTL_HDL*/
-+static int rtw_get_ap_info(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+	u32 cnt = 0, wpa_ielen;
-+	_irqL	irqL;
-+	_list	*plist, *phead;
-+	unsigned char *pbuf;
-+	u8 bssid[ETH_ALEN];
-+	char data[32];
-+	struct wlan_network *pnetwork = NULL;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	_queue *queue = &(pmlmepriv->scanned_queue);
-+	struct iw_point *pdata = &wrqu->data;
-+
-+	RTW_INFO("+rtw_get_aplist_info\n");
-+
-+	if (rtw_is_drv_stopped(padapter) || (pdata == NULL)) {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	while ((check_fwstate(pmlmepriv, (WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING))) == _TRUE) {
-+		rtw_msleep_os(30);
-+		cnt++;
-+		if (cnt > 100)
-+			break;
-+	}
-+
-+
-+	/* pdata->length = 0; */ /* ?	 */
-+	pdata->flags = 0;
-+	if (pdata->length >= 32) {
-+		if (copy_from_user(data, pdata->pointer, 32)) {
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+	} else {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+
-+		if (hwaddr_aton_i(data, bssid)) {
-+			RTW_INFO("Invalid BSSID '%s'.\n", (u8 *)data);
-+			_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+			return -EINVAL;
-+		}
-+
-+
-+		if (_rtw_memcmp(bssid, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE) { /* BSSID match, then check if supporting wpa/wpa2 */
-+			RTW_INFO("BSSID:" MAC_FMT "\n", MAC_ARG(bssid));
-+
-+			pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12);
-+			if (pbuf && (wpa_ielen > 0)) {
-+				pdata->flags = 1;
-+				break;
-+			}
-+
-+			pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12);
-+			if (pbuf && (wpa_ielen > 0)) {
-+				pdata->flags = 2;
-+				break;
-+			}
-+
-+		}
-+
-+		plist = get_next(plist);
-+
-+	}
-+
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	if (pdata->length >= 34) {
-+		if (copy_to_user((u8 *)pdata->pointer + 32, (u8 *)&pdata->flags, 1)) {
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+	}
-+
-+exit:
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_set_pid(struct net_device *dev,
-+		       struct iw_request_info *info,
-+		       union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = rtw_netdev_priv(dev);
-+	int *pdata = (int *)wrqu;
-+	int selector;
-+
-+	if (rtw_is_drv_stopped(padapter) || (pdata == NULL)) {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	selector = *pdata;
-+	if (selector < 3 && selector >= 0) {
-+		padapter->pid[selector] = *(pdata + 1);
-+#ifdef CONFIG_GLOBAL_UI_PID
-+		ui_pid[selector] = *(pdata + 1);
-+#endif
-+		RTW_INFO("%s set pid[%d]=%d\n", __FUNCTION__, selector , padapter->pid[selector]);
-+	} else
-+		RTW_INFO("%s selector %d error\n", __FUNCTION__, selector);
-+
-+exit:
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_wps_start(struct net_device *dev,
-+			 struct iw_request_info *info,
-+			 union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct iw_point *pdata = &wrqu->data;
-+	u32   u32wps_start = 0;
-+	unsigned int uintRet = 0;
-+
-+	if (RTW_CANNOT_RUN(padapter) || (NULL == pdata)) {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	uintRet = copy_from_user((void *) &u32wps_start, pdata->pointer, 4);
-+	if (u32wps_start == 0)
-+		u32wps_start = *extra;
-+
-+	RTW_INFO("[%s] wps_start = %d\n", __FUNCTION__, u32wps_start);
-+
-+	if (u32wps_start == 1)   /* WPS Start */
-+		rtw_led_control(padapter, LED_CTL_START_WPS);
-+	else if (u32wps_start == 2)   /* WPS Stop because of wps success */
-+		rtw_led_control(padapter, LED_CTL_STOP_WPS);
-+	else if (u32wps_start == 3)   /* WPS Stop because of wps fail */
-+		rtw_led_control(padapter, LED_CTL_STOP_WPS_FAIL);
-+
-+exit:
-+
-+	return ret;
-+
-+}
-+
-+#ifdef CONFIG_P2P
-+static int rtw_wext_p2p_enable(struct net_device *dev,
-+			       struct iw_request_info *info,
-+			       union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	enum P2P_ROLE init_role = P2P_ROLE_DISABLE;
-+#ifdef CONFIG_CONCURRENT_MODE
-+	struct roch_info *prochinfo = &padapter->rochinfo;
-+#endif
-+
-+	if (*extra == '0')
-+		init_role = P2P_ROLE_DISABLE;
-+	else if (*extra == '1')
-+		init_role = P2P_ROLE_DEVICE;
-+	else if (*extra == '2')
-+		init_role = P2P_ROLE_CLIENT;
-+	else if (*extra == '3')
-+		init_role = P2P_ROLE_GO;
-+
-+	if (_FAIL == rtw_p2p_enable(padapter, init_role)) {
-+		ret = -EFAULT;
-+		goto exit;
-+	}
-+
-+	/* set channel/bandwidth */
-+	if (init_role != P2P_ROLE_DISABLE) {
-+		u8 channel, ch_offset;
-+		u16 bwmode;
-+
-+		if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)) {
-+			/*	Stay at the listen state and wait for discovery. */
-+			channel = pwdinfo->listen_channel;
-+			pwdinfo->operating_channel = pwdinfo->listen_channel;
-+			ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+			bwmode = CHANNEL_WIDTH_20;
-+		}
-+#ifdef CONFIG_CONCURRENT_MODE
-+		else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {
-+
-+			_set_timer(&prochinfo->ap_roch_ch_switch_timer, pwdinfo->ext_listen_interval);
-+
-+			channel = rtw_mi_get_union_chan(padapter);
-+			ch_offset = rtw_mi_get_union_offset(padapter);
-+			bwmode = rtw_mi_get_union_bw(padapter);
-+
-+			pwdinfo->operating_channel = channel;
-+		}
-+#endif
-+		else {
-+			pwdinfo->operating_channel = pmlmeext->cur_channel;
-+
-+			channel = pwdinfo->operating_channel;
-+			ch_offset = pmlmeext->cur_ch_offset;
-+			bwmode = pmlmeext->cur_bwmode;
-+		}
-+
-+		set_channel_bwmode(padapter, channel, ch_offset, bwmode);
-+	}
-+
-+exit:
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_set_go_nego_ssid(struct net_device *dev,
-+				    struct iw_request_info *info,
-+				    union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+
-+	RTW_INFO("[%s] ssid = %s, len = %zu\n", __FUNCTION__, extra, strlen(extra));
-+	_rtw_memcpy(pwdinfo->nego_ssid, extra, strlen(extra));
-+	pwdinfo->nego_ssidlen = strlen(extra);
-+
-+	return ret;
-+
-+}
-+
-+
-+static int rtw_p2p_set_intent(struct net_device *dev,
-+			      struct iw_request_info *info,
-+			      union iwreq_data *wrqu, char *extra)
-+{
-+	int							ret = 0;
-+	_adapter						*padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info			*pwdinfo = &(padapter->wdinfo);
-+	u8							intent = pwdinfo->intent;
-+
-+	extra[wrqu->data.length] = 0x00;
-+
-+	intent = rtw_atoi(extra);
-+
-+	if (intent <= 15)
-+		pwdinfo->intent = intent;
-+	else
-+		ret = -1;
-+
-+	RTW_INFO("[%s] intent = %d\n", __FUNCTION__, intent);
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_set_listen_ch(struct net_device *dev,
-+				 struct iw_request_info *info,
-+				 union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+	u8	listen_ch = pwdinfo->listen_channel;	/*	Listen channel number */
-+
-+	extra[wrqu->data.length] = 0x00;
-+	listen_ch = rtw_atoi(extra);
-+
-+	if ((listen_ch == 1) || (listen_ch == 6) || (listen_ch == 11)) {
-+		pwdinfo->listen_channel = listen_ch;
-+		set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+	} else
-+		ret = -1;
-+
-+	RTW_INFO("[%s] listen_ch = %d\n", __FUNCTION__, pwdinfo->listen_channel);
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_set_op_ch(struct net_device *dev,
-+			     struct iw_request_info *info,
-+			     union iwreq_data *wrqu, char *extra)
-+{
-+	/*	Commented by Albert 20110524
-+	 *	This function is used to set the operating channel if the driver will become the group owner */
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+	u8	op_ch = pwdinfo->operating_channel;	/*	Operating channel number */
-+
-+	extra[wrqu->data.length] = 0x00;
-+
-+	op_ch = (u8) rtw_atoi(extra);
-+	if (op_ch > 0)
-+		pwdinfo->operating_channel = op_ch;
-+	else
-+		ret = -1;
-+
-+	RTW_INFO("[%s] op_ch = %d\n", __FUNCTION__, pwdinfo->operating_channel);
-+
-+	return ret;
-+
-+}
-+
-+
-+static int rtw_p2p_profilefound(struct net_device *dev,
-+				struct iw_request_info *info,
-+				union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+
-+	/*	Comment by Albert 2010/10/13 */
-+	/*	Input data format: */
-+	/*	Ex:  0 */
-+	/*	Ex:  1XX:XX:XX:XX:XX:XXYYSSID */
-+	/*	0 => Reflush the profile record list. */
-+	/*	1 => Add the profile list */
-+	/*	XX:XX:XX:XX:XX:XX => peer's MAC Address ( ex: 00:E0:4C:00:00:01 ) */
-+	/*	YY => SSID Length */
-+	/*	SSID => SSID for persistence group */
-+
-+	RTW_INFO("[%s] In value = %s, len = %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
-+
-+
-+	/*	The upper application should pass the SSID to driver by using this rtw_p2p_profilefound function. */
-+	if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
-+		if (extra[0] == '0') {
-+			/*	Remove all the profile information of wifidirect_info structure. */
-+			_rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM);
-+			pwdinfo->profileindex = 0;
-+		} else {
-+			if (pwdinfo->profileindex >= P2P_MAX_PERSISTENT_GROUP_NUM)
-+				ret = -1;
-+			else {
-+				int jj, kk;
-+
-+				/*	Add this profile information into pwdinfo->profileinfo */
-+				/*	Ex:  1XX:XX:XX:XX:XX:XXYYSSID */
-+				for (jj = 0, kk = 1; jj < ETH_ALEN; jj++, kk += 3)
-+					pwdinfo->profileinfo[pwdinfo->profileindex].peermac[jj] = key_2char2num(extra[kk], extra[kk + 1]);
-+
-+				/* pwdinfo->profileinfo[pwdinfo->profileindex].ssidlen = ( extra[18] - '0' ) * 10 + ( extra[19] - '0' ); */
-+				/* _rtw_memcpy( pwdinfo->profileinfo[pwdinfo->profileindex].ssid, &extra[20], pwdinfo->profileinfo[pwdinfo->profileindex].ssidlen ); */
-+				pwdinfo->profileindex++;
-+			}
-+		}
-+	}
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_setDN(struct net_device *dev,
-+			 struct iw_request_info *info,
-+			 union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+
-+
-+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
-+	_rtw_memset(pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN);
-+	_rtw_memcpy(pwdinfo->device_name, extra, wrqu->data.length - 1);
-+	pwdinfo->device_name_len = wrqu->data.length - 1;
-+
-+	return ret;
-+
-+}
-+
-+
-+static int rtw_p2p_get_status(struct net_device *dev,
-+			      struct iw_request_info *info,
-+			      union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+	if (padapter->bShowGetP2PState) {
-+		RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
-+			pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],
-+			pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
-+	}
-+
-+	/*	Commented by Albert 2010/10/12 */
-+	/*	Because of the output size limitation, I had removed the "Role" information. */
-+	/*	About the "Role" information, we will use the new private IOCTL to get the "Role" information. */
-+	sprintf(extra, "\n\nStatus=%.2d\n", rtw_p2p_state(pwdinfo));
-+	wrqu->data.length = strlen(extra);
-+
-+	return ret;
-+
-+}
-+
-+/*	Commented by Albert 20110520
-+ *	This function will return the config method description
-+ *	This config method description will show us which config method the remote P2P device is intented to use
-+ *	by sending the provisioning discovery request frame. */
-+
-+static int rtw_p2p_get_req_cm(struct net_device *dev,
-+			      struct iw_request_info *info,
-+			      union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+	sprintf(extra, "\n\nCM=%s\n", pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req);
-+	wrqu->data.length = strlen(extra);
-+	return ret;
-+
-+}
-+
-+
-+static int rtw_p2p_get_role(struct net_device *dev,
-+			    struct iw_request_info *info,
-+			    union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+	RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
-+		pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],
-+		pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
-+
-+	sprintf(extra, "\n\nRole=%.2d\n", rtw_p2p_role(pwdinfo));
-+	wrqu->data.length = strlen(extra);
-+	return ret;
-+
-+}
-+
-+
-+static int rtw_p2p_get_peer_ifaddr(struct net_device *dev,
-+				   struct iw_request_info *info,
-+				   union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+
-+	RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
-+		pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],
-+		pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
-+
-+	sprintf(extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X",
-+		pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2],
-+		pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]);
-+	wrqu->data.length = strlen(extra);
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_get_peer_devaddr(struct net_device *dev,
-+				    struct iw_request_info *info,
-+				    union iwreq_data *wrqu, char *extra)
-+
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+	RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
-+		pwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1],
-+		pwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3],
-+		pwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]);
-+	sprintf(extra, "\n%.2X%.2X%.2X%.2X%.2X%.2X",
-+		pwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1],
-+		pwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3],
-+		pwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]);
-+	wrqu->data.length = strlen(extra);
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_get_peer_devaddr_by_invitation(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra)
-+
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+	RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo),
-+		pwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1],
-+		pwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3],
-+		pwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]);
-+	sprintf(extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X",
-+		pwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1],
-+		pwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3],
-+		pwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]);
-+	wrqu->data.length = strlen(extra);
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_get_groupid(struct net_device *dev,
-+			       struct iw_request_info *info,
-+			       union iwreq_data *wrqu, char *extra)
-+
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+	sprintf(extra, "\n%.2X:%.2X:%.2X:%.2X:%.2X:%.2X %s",
-+		pwdinfo->groupid_info.go_device_addr[0], pwdinfo->groupid_info.go_device_addr[1],
-+		pwdinfo->groupid_info.go_device_addr[2], pwdinfo->groupid_info.go_device_addr[3],
-+		pwdinfo->groupid_info.go_device_addr[4], pwdinfo->groupid_info.go_device_addr[5],
-+		pwdinfo->groupid_info.ssid);
-+	wrqu->data.length = strlen(extra);
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_get_op_ch(struct net_device *dev,
-+			     struct iw_request_info *info,
-+			     union iwreq_data *wrqu, char *extra)
-+
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+
-+	RTW_INFO("[%s] Op_ch = %02x\n", __FUNCTION__, pwdinfo->operating_channel);
-+
-+	sprintf(extra, "\n\nOp_ch=%.2d\n", pwdinfo->operating_channel);
-+	wrqu->data.length = strlen(extra);
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_get_wps_configmethod(struct net_device *dev,
-+					struct iw_request_info *info,
-+			union iwreq_data *wrqu, char *extra, char *subcmd)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 peerMAC[ETH_ALEN] = { 0x00 };
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	_irqL irqL;
-+	_list *plist, *phead;
-+	_queue *queue = &(pmlmepriv->scanned_queue);
-+	struct wlan_network *pnetwork = NULL;
-+	u8 blnMatch = 0;
-+	u16	attr_content = 0;
-+	uint attr_contentlen = 0;
-+	u8	attr_content_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
-+
-+	/*	Commented by Albert 20110727 */
-+	/*	The input data is the MAC address which the application wants to know its WPS config method. */
-+	/*	After knowing its WPS config method, the application can decide the config method for provisioning discovery. */
-+	/*	Format: iwpriv wlanx p2p_get_wpsCM 00:E0:4C:00:00:05 */
-+
-+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
-+
-+	macstr2num(peerMAC, subcmd);
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
-+			u8 *wpsie;
-+			uint	wpsie_len = 0;
-+
-+			/*	The mac address is matched. */
-+
-+			wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]);
-+			if (wpsie) {
-+				rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_CONF_METHOD, (u8 *)&attr_content, &attr_contentlen);
-+				if (attr_contentlen) {
-+					attr_content = be16_to_cpu(attr_content);
-+					sprintf(attr_content_str, "\n\nM=%.4d", attr_content);
-+					blnMatch = 1;
-+				}
-+			}
-+
-+			break;
-+		}
-+
-+		plist = get_next(plist);
-+
-+	}
-+
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	if (!blnMatch)
-+		sprintf(attr_content_str, "\n\nM=0000");
-+
-+	wrqu->data.length = strlen(attr_content_str);
-+	_rtw_memcpy(extra, attr_content_str, wrqu->data.length);
-+
-+	return ret;
-+
-+}
-+
-+#ifdef CONFIG_WFD
-+static int rtw_p2p_get_peer_wfd_port(struct net_device *dev,
-+				     struct iw_request_info *info,
-+				     union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+	RTW_INFO("[%s] p2p_state = %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo));
-+
-+	sprintf(extra, "\n\nPort=%d\n", pwdinfo->wfd_info->peer_rtsp_ctrlport);
-+	RTW_INFO("[%s] remote port = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport);
-+
-+	wrqu->data.length = strlen(extra);
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_get_peer_wfd_preferred_connection(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+	sprintf(extra, "\n\nwfd_pc=%d\n", pwdinfo->wfd_info->wfd_pc);
-+	RTW_INFO("[%s] wfd_pc = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_pc);
-+
-+	wrqu->data.length = strlen(extra);
-+	pwdinfo->wfd_info->wfd_pc = _FALSE;	/*	Reset the WFD preferred connection to P2P */
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_get_peer_wfd_session_available(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+	sprintf(extra, "\n\nwfd_sa=%d\n", pwdinfo->wfd_info->peer_session_avail);
-+	RTW_INFO("[%s] wfd_sa = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_session_avail);
-+
-+	wrqu->data.length = strlen(extra);
-+	pwdinfo->wfd_info->peer_session_avail = _TRUE;	/*	Reset the WFD session available */
-+	return ret;
-+
-+}
-+#endif /* CONFIG_WFD */
-+
-+static int rtw_p2p_get_go_device_address(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra, char *subcmd)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 peerMAC[ETH_ALEN] = { 0x00 };
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	_irqL irqL;
-+	_list *plist, *phead;
-+	_queue *queue	= &(pmlmepriv->scanned_queue);
-+	struct wlan_network *pnetwork = NULL;
-+	u8 blnMatch = 0;
-+	u8 *p2pie;
-+	uint p2pielen = 0, attr_contentlen = 0;
-+	u8 attr_content[100] = { 0x00 };
-+	u8 go_devadd_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
-+
-+	/*	Commented by Albert 20121209 */
-+	/*	The input data is the GO's interface address which the application wants to know its device address. */
-+	/*	Format: iwpriv wlanx p2p_get2 go_devadd=00:E0:4C:00:00:05 */
-+
-+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
-+
-+	macstr2num(peerMAC, subcmd);
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
-+			/*	Commented by Albert 2011/05/18 */
-+			/*	Match the device address located in the P2P IE */
-+			/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
-+
-+			p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
-+			if (p2pie) {
-+				while (p2pie) {
-+					/*	The P2P Device ID attribute is included in the Beacon frame. */
-+					/*	The P2P Device Info attribute is included in the probe response frame. */
-+
-+					_rtw_memset(attr_content, 0x00, 100);
-+					if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {
-+						/*	Handle the P2P Device ID attribute of Beacon first */
-+						blnMatch = 1;
-+						break;
-+
-+					} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {
-+						/*	Handle the P2P Device Info attribute of probe response */
-+						blnMatch = 1;
-+						break;
-+					}
-+
-+					/* Get the next P2P IE */
-+					p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen);
-+				}
-+			}
-+		}
-+
-+		plist = get_next(plist);
-+
-+	}
-+
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	if (!blnMatch)
-+		sprintf(go_devadd_str, "\n\ndev_add=NULL");
-+	else {
-+		sprintf(go_devadd_str, "\n\ndev_add=%.2X:%.2X:%.2X:%.2X:%.2X:%.2X",
-+			attr_content[0], attr_content[1], attr_content[2], attr_content[3], attr_content[4], attr_content[5]);
-+	}
-+
-+	wrqu->data.length = strlen(go_devadd_str);
-+	_rtw_memcpy(extra, go_devadd_str, wrqu->data.length);
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_get_device_type(struct net_device *dev,
-+				   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra, char *subcmd)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 peerMAC[ETH_ALEN] = { 0x00 };
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	_irqL irqL;
-+	_list *plist, *phead;
-+	_queue *queue = &(pmlmepriv->scanned_queue);
-+	struct wlan_network *pnetwork = NULL;
-+	u8 blnMatch = 0;
-+	u8 dev_type[8] = { 0x00 };
-+	uint dev_type_len = 0;
-+	u8 dev_type_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };    /* +9 is for the str "dev_type=", we have to clear it at wrqu->data.pointer */
-+
-+	/*	Commented by Albert 20121209 */
-+	/*	The input data is the MAC address which the application wants to know its device type. */
-+	/*	Such user interface could know the device type. */
-+	/*	Format: iwpriv wlanx p2p_get2 dev_type=00:E0:4C:00:00:05 */
-+
-+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
-+
-+	macstr2num(peerMAC, subcmd);
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
-+			u8 *wpsie;
-+			uint	wpsie_len = 0;
-+
-+			/*	The mac address is matched. */
-+
-+			wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]);
-+			if (wpsie) {
-+				rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_PRIMARY_DEV_TYPE, dev_type, &dev_type_len);
-+				if (dev_type_len) {
-+					u16	type = 0;
-+
-+					_rtw_memcpy(&type, dev_type, 2);
-+					type = be16_to_cpu(type);
-+					sprintf(dev_type_str, "\n\nN=%.2d", type);
-+					blnMatch = 1;
-+				}
-+			}
-+			break;
-+		}
-+
-+		plist = get_next(plist);
-+
-+	}
-+
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	if (!blnMatch)
-+		sprintf(dev_type_str, "\n\nN=00");
-+
-+	wrqu->data.length = strlen(dev_type_str);
-+	_rtw_memcpy(extra, dev_type_str, wrqu->data.length);
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_get_device_name(struct net_device *dev,
-+				   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra, char *subcmd)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 peerMAC[ETH_ALEN] = { 0x00 };
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	_irqL irqL;
-+	_list *plist, *phead;
-+	_queue *queue = &(pmlmepriv->scanned_queue);
-+	struct wlan_network *pnetwork = NULL;
-+	u8 blnMatch = 0;
-+	u8 dev_name[WPS_MAX_DEVICE_NAME_LEN] = { 0x00 };
-+	uint dev_len = 0;
-+	u8 dev_name_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
-+
-+	/*	Commented by Albert 20121225 */
-+	/*	The input data is the MAC address which the application wants to know its device name. */
-+	/*	Such user interface could show peer device's device name instead of ssid. */
-+	/*	Format: iwpriv wlanx p2p_get2 devN=00:E0:4C:00:00:05 */
-+
-+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
-+
-+	macstr2num(peerMAC, subcmd);
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
-+			u8 *wpsie;
-+			uint	wpsie_len = 0;
-+
-+			/*	The mac address is matched. */
-+
-+			wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]);
-+			if (wpsie) {
-+				rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_DEVICE_NAME, dev_name, &dev_len);
-+				if (dev_len) {
-+					sprintf(dev_name_str, "\n\nN=%s", dev_name);
-+					blnMatch = 1;
-+				}
-+			}
-+			break;
-+		}
-+
-+		plist = get_next(plist);
-+
-+	}
-+
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	if (!blnMatch)
-+		sprintf(dev_name_str, "\n\nN=0000");
-+
-+	wrqu->data.length = strlen(dev_name_str);
-+	_rtw_memcpy(extra, dev_name_str, wrqu->data.length);
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_get_invitation_procedure(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra, char *subcmd)
-+{
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 peerMAC[ETH_ALEN] = { 0x00 };
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	_irqL irqL;
-+	_list *plist, *phead;
-+	_queue *queue	= &(pmlmepriv->scanned_queue);
-+	struct wlan_network *pnetwork = NULL;
-+	u8 blnMatch = 0;
-+	u8 *p2pie;
-+	uint p2pielen = 0, attr_contentlen = 0;
-+	u8 attr_content[2] = { 0x00 };
-+	u8 inv_proc_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 };
-+
-+	/*	Commented by Ouden 20121226 */
-+	/*	The application wants to know P2P initation procedure is support or not. */
-+	/*	Format: iwpriv wlanx p2p_get2 InvProc=00:E0:4C:00:00:05 */
-+
-+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd);
-+
-+	macstr2num(peerMAC, subcmd);
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
-+			/*	Commented by Albert 20121226 */
-+			/*	Match the device address located in the P2P IE */
-+			/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
-+
-+			p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
-+			if (p2pie) {
-+				while (p2pie) {
-+					/* _rtw_memset( attr_content, 0x00, 2); */
-+					if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_CAPABILITY, attr_content, &attr_contentlen)) {
-+						/*	Handle the P2P capability attribute */
-+						blnMatch = 1;
-+						break;
-+
-+					}
-+
-+					/* Get the next P2P IE */
-+					p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen);
-+				}
-+			}
-+		}
-+
-+		plist = get_next(plist);
-+
-+	}
-+
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	if (!blnMatch)
-+		sprintf(inv_proc_str, "\nIP=-1");
-+	else {
-+		if ((attr_content[0] & 0x20) == 0x20)
-+			sprintf(inv_proc_str, "\nIP=1");
-+		else
-+			sprintf(inv_proc_str, "\nIP=0");
-+	}
-+
-+	wrqu->data.length = strlen(inv_proc_str);
-+	_rtw_memcpy(extra, inv_proc_str, wrqu->data.length);
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_connect(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	u8					peerMAC[ETH_ALEN] = { 0x00 };
-+	int					jj, kk;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	_irqL				irqL;
-+	_list					*plist, *phead;
-+	_queue				*queue	= &(pmlmepriv->scanned_queue);
-+	struct	wlan_network	*pnetwork = NULL;
-+	uint					uintPeerChannel = 0;
-+#ifdef CONFIG_CONCURRENT_MODE
-+	struct roch_info		*prochinfo = &padapter->rochinfo;
-+#endif
-+
-+	/*	Commented by Albert 20110304 */
-+	/*	The input data contains two informations. */
-+	/*	1. First information is the MAC address which wants to formate with */
-+	/*	2. Second information is the WPS PINCode or "pbc" string for push button method */
-+	/*	Format: 00:E0:4C:00:00:05 */
-+	/*	Format: 00:E0:4C:00:00:05 */
-+
-+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
-+
-+	if (pwdinfo->p2p_state == P2P_STATE_NONE) {
-+		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
-+		return ret;
-+	}
-+
-+	if (pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO)
-+		return -1;
-+
-+	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
-+		peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]);
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+		if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) {
-+			if (pnetwork->network.Configuration.DSConfig != 0)
-+				uintPeerChannel = pnetwork->network.Configuration.DSConfig;
-+			else if (pwdinfo->nego_req_info.peer_ch != 0)
-+				uintPeerChannel = pnetwork->network.Configuration.DSConfig = pwdinfo->nego_req_info.peer_ch;
-+			else {
-+				/* Unexpected case */
-+				uintPeerChannel = 0;
-+				RTW_INFO("%s  uintPeerChannel = 0\n", __func__);
-+			}
-+			break;
-+		}
-+
-+		plist = get_next(plist);
-+
-+	}
-+
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	if (uintPeerChannel) {
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED))
-+			_cancel_timer_ex(&prochinfo->ap_roch_ch_switch_timer);
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+		_rtw_memset(&pwdinfo->nego_req_info, 0x00, sizeof(struct tx_nego_req_info));
-+		_rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info));
-+
-+		pwdinfo->nego_req_info.peer_channel_num[0] = uintPeerChannel;
-+		_rtw_memcpy(pwdinfo->nego_req_info.peerDevAddr, pnetwork->network.MacAddress, ETH_ALEN);
-+		pwdinfo->nego_req_info.benable = _TRUE;
-+
-+		_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
-+		if (rtw_p2p_state(pwdinfo) != P2P_STATE_GONEGO_OK) {
-+			/*	Restore to the listen state if the current p2p state is not nego OK */
-+			rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN);
-+		}
-+
-+		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
-+		rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED)) {
-+			u8 union_ch = rtw_mi_get_union_chan(padapter);
-+			u8 union_bw = rtw_mi_get_union_bw(padapter);
-+			u8 union_offset = rtw_mi_get_union_offset(padapter);
-+
-+			set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
-+			rtw_leave_opch(padapter);
-+		}
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+		RTW_INFO("[%s] Start PreTx Procedure!\n", __FUNCTION__);
-+		_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED))
-+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_GO_NEGO_TIMEOUT);
-+		else
-+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT);
-+#else
-+		_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT);
-+#endif /* CONFIG_CONCURRENT_MODE		 */
-+
-+	} else {
-+		RTW_INFO("[%s] Not Found in Scanning Queue~\n", __FUNCTION__);
-+		ret = -1;
-+	}
-+
-+	return ret;
-+}
-+
-+static int rtw_p2p_invite_req(struct net_device *dev,
-+			      struct iw_request_info *info,
-+			      union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter					*padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info		*pwdinfo = &(padapter->wdinfo);
-+	int						jj, kk;
-+	struct mlme_priv			*pmlmepriv = &padapter->mlmepriv;
-+	_list						*plist, *phead;
-+	_queue					*queue	= &(pmlmepriv->scanned_queue);
-+	struct	wlan_network		*pnetwork = NULL;
-+	uint						uintPeerChannel = 0;
-+	u8						attr_content[50] = { 0x00 };
-+	u8						*p2pie;
-+	uint						p2pielen = 0, attr_contentlen = 0;
-+	_irqL					irqL;
-+	struct tx_invite_req_info	*pinvite_req_info = &pwdinfo->invitereq_info;
-+#ifdef CONFIG_CONCURRENT_MODE
-+	struct roch_info			*prochinfo = &padapter->rochinfo;
-+#endif
-+
-+	/*	Commented by Albert 20120321 */
-+	/*	The input data contains two informations. */
-+	/*	1. First information is the P2P device address which you want to send to.	 */
-+	/*	2. Second information is the group id which combines with GO's mac address, space and GO's ssid. */
-+	/*	Command line sample: iwpriv wlan0 p2p_set invite="00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy" */
-+	/*	Format: 00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy */
-+
-+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
-+
-+	if (wrqu->data.length <=  37) {
-+		RTW_INFO("[%s] Wrong format!\n", __FUNCTION__);
-+		return ret;
-+	}
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
-+		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
-+		return ret;
-+	} else {
-+		/*	Reset the content of struct tx_invite_req_info */
-+		pinvite_req_info->benable = _FALSE;
-+		_rtw_memset(pinvite_req_info->go_bssid, 0x00, ETH_ALEN);
-+		_rtw_memset(pinvite_req_info->go_ssid, 0x00, WLAN_SSID_MAXLEN);
-+		pinvite_req_info->ssidlen = 0x00;
-+		pinvite_req_info->operating_ch = pwdinfo->operating_channel;
-+		_rtw_memset(pinvite_req_info->peer_macaddr, 0x00, ETH_ALEN);
-+		pinvite_req_info->token = 3;
-+	}
-+
-+	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
-+		pinvite_req_info->peer_macaddr[jj] = key_2char2num(extra[kk], extra[kk + 1]);
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+
-+		/*	Commented by Albert 2011/05/18 */
-+		/*	Match the device address located in the P2P IE */
-+		/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
-+
-+		p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
-+		if (p2pie) {
-+			/*	The P2P Device ID attribute is included in the Beacon frame. */
-+			/*	The P2P Device Info attribute is included in the probe response frame. */
-+
-+			if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {
-+				/*	Handle the P2P Device ID attribute of Beacon first */
-+				if (_rtw_memcmp(attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN)) {
-+					uintPeerChannel = pnetwork->network.Configuration.DSConfig;
-+					break;
-+				}
-+			} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {
-+				/*	Handle the P2P Device Info attribute of probe response */
-+				if (_rtw_memcmp(attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN)) {
-+					uintPeerChannel = pnetwork->network.Configuration.DSConfig;
-+					break;
-+				}
-+			}
-+
-+		}
-+
-+		plist = get_next(plist);
-+
-+	}
-+
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+#ifdef CONFIG_WFD
-+	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST) && uintPeerChannel) {
-+		struct wifi_display_info *pwfd_info = pwdinfo->wfd_info;
-+		u8 *wfd_ie;
-+		uint wfd_ielen = 0;
-+
-+		wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);
-+		if (wfd_ie) {
-+			u8 *wfd_devinfo;
-+			uint wfd_devlen;
-+
-+			RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__);
-+			wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);
-+			if (wfd_devinfo) {
-+				u16	wfd_devinfo_field = 0;
-+
-+				/*	Commented by Albert 20120319 */
-+				/*	The first two bytes are the WFD device information field of WFD device information subelement. */
-+				/*	In big endian format. */
-+				wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);
-+				if (wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL)
-+					pwfd_info->peer_session_avail = _TRUE;
-+				else
-+					pwfd_info->peer_session_avail = _FALSE;
-+			}
-+		}
-+
-+		if (_FALSE == pwfd_info->peer_session_avail) {
-+			RTW_INFO("[%s] WFD Session not avaiable!\n", __FUNCTION__);
-+			goto exit;
-+		}
-+	}
-+#endif /* CONFIG_WFD */
-+
-+	if (uintPeerChannel) {
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED))
-+			_cancel_timer_ex(&prochinfo->ap_roch_ch_switch_timer);
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+		/*	Store the GO's bssid */
-+		for (jj = 0, kk = 18; jj < ETH_ALEN; jj++, kk += 3)
-+			pinvite_req_info->go_bssid[jj] = key_2char2num(extra[kk], extra[kk + 1]);
-+
-+		/*	Store the GO's ssid */
-+		pinvite_req_info->ssidlen = wrqu->data.length - 36;
-+		_rtw_memcpy(pinvite_req_info->go_ssid, &extra[36], (u32) pinvite_req_info->ssidlen);
-+		pinvite_req_info->benable = _TRUE;
-+		pinvite_req_info->peer_ch = uintPeerChannel;
-+
-+		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
-+		rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INVITE_REQ);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED)) {
-+			u8 union_ch = rtw_mi_get_union_chan(padapter);
-+			u8 union_bw = rtw_mi_get_union_bw(padapter);
-+			u8 union_offset = rtw_mi_get_union_offset(padapter);
-+
-+			set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
-+			rtw_leave_opch(padapter);
-+
-+		} else
-+			set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+#else
-+		set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+#endif/*CONFIG_CONCURRENT_MODE*/
-+
-+		_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED))
-+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_INVITE_TIMEOUT);
-+		else
-+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT);
-+#else
-+		_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT);
-+#endif /* CONFIG_CONCURRENT_MODE		 */
-+
-+
-+	} else
-+		RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__);
-+exit:
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_set_persistent(struct net_device *dev,
-+				  struct iw_request_info *info,
-+				  union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter					*padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info		*pwdinfo = &(padapter->wdinfo);
-+
-+	/*	Commented by Albert 20120328 */
-+	/*	The input data is 0 or 1 */
-+	/*	0: disable persistent group functionality */
-+	/*	1: enable persistent group founctionality */
-+
-+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
-+		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
-+		return ret;
-+	} else {
-+		if (extra[0] == '0')	/*	Disable the persistent group function. */
-+			pwdinfo->persistent_supported = _FALSE;
-+		else if (extra[0] == '1')	/*	Enable the persistent group function. */
-+			pwdinfo->persistent_supported = _TRUE;
-+		else
-+			pwdinfo->persistent_supported = _FALSE;
-+	}
-+	printk("[%s] persistent_supported = %d\n", __FUNCTION__, pwdinfo->persistent_supported);
-+
-+	return ret;
-+
-+}
-+
-+static int uuid_str2bin(const char *str, u8 *bin)
-+{
-+	const char *pos;
-+	u8 *opos;
-+
-+	pos = str;
-+	opos = bin;
-+
-+	if (hexstr2bin(pos, opos, 4))
-+		return -1;
-+	pos += 8;
-+	opos += 4;
-+
-+	if (*pos++ != '-' || hexstr2bin(pos, opos, 2))
-+		return -1;
-+	pos += 4;
-+	opos += 2;
-+
-+	if (*pos++ != '-' || hexstr2bin(pos, opos, 2))
-+		return -1;
-+	pos += 4;
-+	opos += 2;
-+
-+	if (*pos++ != '-' || hexstr2bin(pos, opos, 2))
-+		return -1;
-+	pos += 4;
-+	opos += 2;
-+
-+	if (*pos++ != '-' || hexstr2bin(pos, opos, 6))
-+		return -1;
-+
-+	return 0;
-+}
-+
-+static int rtw_p2p_set_wps_uuid(struct net_device *dev,
-+				struct iw_request_info *info,
-+				union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info			*pwdinfo = &(padapter->wdinfo);
-+
-+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
-+
-+	if ((36 == strlen(extra)) && (uuid_str2bin(extra, pwdinfo->uuid) == 0))
-+		pwdinfo->external_uuid = 1;
-+	else {
-+		pwdinfo->external_uuid = 0;
-+		ret = -EINVAL;
-+	}
-+
-+	return ret;
-+
-+}
-+#ifdef CONFIG_WFD
-+static int rtw_p2p_set_pc(struct net_device *dev,
-+			  struct iw_request_info *info,
-+			  union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	u8					peerMAC[ETH_ALEN] = { 0x00 };
-+	int					jj, kk;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	_list					*plist, *phead;
-+	_queue				*queue	= &(pmlmepriv->scanned_queue);
-+	struct	wlan_network	*pnetwork = NULL;
-+	u8					attr_content[50] = { 0x00 };
-+	u8 *p2pie;
-+	uint					p2pielen = 0, attr_contentlen = 0;
-+	_irqL				irqL;
-+	uint					uintPeerChannel = 0;
-+
-+	struct wifi_display_info	*pwfd_info = pwdinfo->wfd_info;
-+
-+	/*	Commented by Albert 20120512 */
-+	/*	1. Input information is the MAC address which wants to know the Preferred Connection bit (PC bit) */
-+	/*	Format: 00:E0:4C:00:00:05 */
-+
-+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
-+
-+	if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
-+		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
-+		return ret;
-+	}
-+
-+	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
-+		peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]);
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+
-+		/*	Commented by Albert 2011/05/18 */
-+		/*	Match the device address located in the P2P IE */
-+		/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
-+
-+		p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
-+		if (p2pie) {
-+			/*	The P2P Device ID attribute is included in the Beacon frame. */
-+			/*	The P2P Device Info attribute is included in the probe response frame. */
-+			printk("[%s] Got P2P IE\n", __FUNCTION__);
-+			if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {
-+				/*	Handle the P2P Device ID attribute of Beacon first */
-+				printk("[%s] P2P_ATTR_DEVICE_ID\n", __FUNCTION__);
-+				if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {
-+					uintPeerChannel = pnetwork->network.Configuration.DSConfig;
-+					break;
-+				}
-+			} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {
-+				/*	Handle the P2P Device Info attribute of probe response */
-+				printk("[%s] P2P_ATTR_DEVICE_INFO\n", __FUNCTION__);
-+				if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {
-+					uintPeerChannel = pnetwork->network.Configuration.DSConfig;
-+					break;
-+				}
-+			}
-+
-+		}
-+
-+		plist = get_next(plist);
-+
-+	}
-+
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+	printk("[%s] channel = %d\n", __FUNCTION__, uintPeerChannel);
-+
-+	if (uintPeerChannel) {
-+		u8 *wfd_ie;
-+		uint wfd_ielen = 0;
-+
-+		wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);
-+		if (wfd_ie) {
-+			u8 *wfd_devinfo;
-+			uint wfd_devlen;
-+
-+			RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__);
-+			wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);
-+			if (wfd_devinfo) {
-+				u16	wfd_devinfo_field = 0;
-+
-+				/*	Commented by Albert 20120319 */
-+				/*	The first two bytes are the WFD device information field of WFD device information subelement. */
-+				/*	In big endian format. */
-+				wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);
-+				if (wfd_devinfo_field & WFD_DEVINFO_PC_TDLS)
-+					pwfd_info->wfd_pc = _TRUE;
-+				else
-+					pwfd_info->wfd_pc = _FALSE;
-+			}
-+		}
-+	} else
-+		RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__);
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_set_wfd_device_type(struct net_device *dev,
-+				       struct iw_request_info *info,
-+				       union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter					*padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info		*pwdinfo = &(padapter->wdinfo);
-+	struct wifi_display_info		*pwfd_info = pwdinfo->wfd_info;
-+
-+	/*	Commented by Albert 20120328 */
-+	/*	The input data is 0 or 1 */
-+	/*	0: specify to Miracast source device */
-+	/*	1 or others: specify to Miracast sink device (display device) */
-+
-+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
-+
-+	if (extra[0] == '0')	/*	Set to Miracast source device. */
-+		pwfd_info->wfd_device_type = WFD_DEVINFO_SOURCE;
-+	else					/*	Set to Miracast sink device. */
-+		pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK;
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_set_wfd_enable(struct net_device *dev,
-+				  struct iw_request_info *info,
-+				  union iwreq_data *wrqu, char *extra)
-+{
-+	/*	Commented by Kurt 20121206
-+	 *	This function is used to set wfd enabled */
-+
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+
-+	if (*extra == '0')
-+		rtw_wfd_enable(padapter, 0);
-+	else if (*extra == '1')
-+		rtw_wfd_enable(padapter, 1);
-+
-+	RTW_INFO("[%s] wfd_enable = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_enable);
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_set_driver_iface(struct net_device *dev,
-+				    struct iw_request_info *info,
-+				    union iwreq_data *wrqu, char *extra)
-+{
-+	/*	Commented by Kurt 20121206
-+	 *	This function is used to set driver iface is WEXT or CFG80211 */
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+
-+	if (*extra == '1') {
-+		pwdinfo->driver_interface = DRIVER_WEXT;
-+		RTW_INFO("[%s] driver_interface = WEXT\n", __FUNCTION__);
-+	} else if (*extra == '2') {
-+		pwdinfo->driver_interface = DRIVER_CFG80211;
-+		RTW_INFO("[%s] driver_interface = CFG80211\n", __FUNCTION__);
-+	}
-+
-+	return ret;
-+
-+}
-+
-+/*	To set the WFD session available to enable or disable */
-+static int rtw_p2p_set_sa(struct net_device *dev,
-+			  struct iw_request_info *info,
-+			  union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter					*padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info		*pwdinfo = &(padapter->wdinfo);
-+
-+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
-+
-+	if (0) {
-+		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
-+		return ret;
-+	} else {
-+		if (extra[0] == '0')	/*	Disable the session available. */
-+			pwdinfo->session_available = _FALSE;
-+		else if (extra[0] == '1')	/*	Enable the session available. */
-+			pwdinfo->session_available = _TRUE;
-+		else
-+			pwdinfo->session_available = _FALSE;
-+	}
-+	printk("[%s] session available = %d\n", __FUNCTION__, pwdinfo->session_available);
-+
-+	return ret;
-+
-+}
-+#endif /* CONFIG_WFD */
-+
-+static int rtw_p2p_prov_disc(struct net_device *dev,
-+			     struct iw_request_info *info,
-+			     union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+	u8					peerMAC[ETH_ALEN] = { 0x00 };
-+	int					jj, kk;
-+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;
-+	_list					*plist, *phead;
-+	_queue				*queue	= &(pmlmepriv->scanned_queue);
-+	struct	wlan_network	*pnetwork = NULL;
-+	uint					uintPeerChannel = 0;
-+	u8					attr_content[100] = { 0x00 };
-+	u8 *p2pie;
-+	uint					p2pielen = 0, attr_contentlen = 0;
-+	_irqL				irqL;
-+#ifdef CONFIG_CONCURRENT_MODE
-+	struct roch_info 		*prochinfo = &padapter->rochinfo;
-+#endif
-+
-+	/*	Commented by Albert 20110301 */
-+	/*	The input data contains two informations. */
-+	/*	1. First information is the MAC address which wants to issue the provisioning discovery request frame. */
-+	/*	2. Second information is the WPS configuration method which wants to discovery */
-+	/*	Format: 00:E0:4C:00:00:05_display */
-+	/*	Format: 00:E0:4C:00:00:05_keypad */
-+	/*	Format: 00:E0:4C:00:00:05_pbc */
-+	/*	Format: 00:E0:4C:00:00:05_label */
-+
-+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
-+
-+	if (pwdinfo->p2p_state == P2P_STATE_NONE) {
-+		RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__);
-+		return ret;
-+	} else {
-+		/*	Reset the content of struct tx_provdisc_req_info excluded the wps_config_method_request. */
-+		_rtw_memset(pwdinfo->tx_prov_disc_info.peerDevAddr, 0x00, ETH_ALEN);
-+		_rtw_memset(pwdinfo->tx_prov_disc_info.peerIFAddr, 0x00, ETH_ALEN);
-+		_rtw_memset(&pwdinfo->tx_prov_disc_info.ssid, 0x00, sizeof(NDIS_802_11_SSID));
-+		pwdinfo->tx_prov_disc_info.peer_channel_num[0] = 0;
-+		pwdinfo->tx_prov_disc_info.peer_channel_num[1] = 0;
-+		pwdinfo->tx_prov_disc_info.benable = _FALSE;
-+	}
-+
-+	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
-+		peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]);
-+
-+	if (_rtw_memcmp(&extra[18], "display", 7))
-+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA;
-+	else if (_rtw_memcmp(&extra[18], "keypad", 7))
-+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD;
-+	else if (_rtw_memcmp(&extra[18], "pbc", 3))
-+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON;
-+	else if (_rtw_memcmp(&extra[18], "label", 5))
-+		pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL;
-+	else {
-+		RTW_INFO("[%s] Unknown WPS config methodn", __FUNCTION__);
-+		return ret ;
-+	}
-+
-+	_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	phead = get_list_head(queue);
-+	plist = get_next(phead);
-+
-+	while (1) {
-+		if (rtw_end_of_queue_search(phead, plist) == _TRUE)
-+			break;
-+
-+		if (uintPeerChannel != 0)
-+			break;
-+
-+		pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
-+
-+		/*	Commented by Albert 2011/05/18 */
-+		/*	Match the device address located in the P2P IE */
-+		/*	This is for the case that the P2P device address is not the same as the P2P interface address. */
-+
-+		p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen);
-+		if (p2pie) {
-+			while (p2pie) {
-+				/*	The P2P Device ID attribute is included in the Beacon frame. */
-+				/*	The P2P Device Info attribute is included in the probe response frame. */
-+
-+				if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) {
-+					/*	Handle the P2P Device ID attribute of Beacon first */
-+					if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {
-+						uintPeerChannel = pnetwork->network.Configuration.DSConfig;
-+						break;
-+					}
-+				} else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) {
-+					/*	Handle the P2P Device Info attribute of probe response */
-+					if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) {
-+						uintPeerChannel = pnetwork->network.Configuration.DSConfig;
-+						break;
-+					}
-+				}
-+
-+				/* Get the next P2P IE */
-+				p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen);
-+			}
-+
-+		}
-+
-+		plist = get_next(plist);
-+
-+	}
-+
-+	_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-+
-+	if (uintPeerChannel) {
-+#ifdef CONFIG_WFD
-+		if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
-+			struct wifi_display_info *pwfd_info = pwdinfo->wfd_info;
-+			u8 *wfd_ie;
-+			uint wfd_ielen = 0;
-+
-+			wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen);
-+			if (wfd_ie) {
-+				u8 *wfd_devinfo;
-+				uint wfd_devlen;
-+
-+				RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__);
-+				wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen);
-+				if (wfd_devinfo) {
-+					u16	wfd_devinfo_field = 0;
-+
-+					/*	Commented by Albert 20120319 */
-+					/*	The first two bytes are the WFD device information field of WFD device information subelement. */
-+					/*	In big endian format. */
-+					wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo);
-+					if (wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL)
-+						pwfd_info->peer_session_avail = _TRUE;
-+					else
-+						pwfd_info->peer_session_avail = _FALSE;
-+				}
-+			}
-+
-+			if (_FALSE == pwfd_info->peer_session_avail) {
-+				RTW_INFO("[%s] WFD Session not avaiable!\n", __FUNCTION__);
-+				goto exit;
-+			}
-+		}
-+#endif /* CONFIG_WFD */
-+
-+		RTW_INFO("[%s] peer channel: %d!\n", __FUNCTION__, uintPeerChannel);
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED))
-+			_cancel_timer_ex(&prochinfo->ap_roch_ch_switch_timer);
-+#endif /* CONFIG_CONCURRENT_MODE */
-+		_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, pnetwork->network.MacAddress, ETH_ALEN);
-+		_rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, peerMAC, ETH_ALEN);
-+		pwdinfo->tx_prov_disc_info.peer_channel_num[0] = (u16) uintPeerChannel;
-+		pwdinfo->tx_prov_disc_info.benable = _TRUE;
-+		rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo));
-+		rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ);
-+
-+		if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT))
-+			_rtw_memcpy(&pwdinfo->tx_prov_disc_info.ssid, &pnetwork->network.Ssid, sizeof(NDIS_802_11_SSID));
-+		else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
-+			_rtw_memcpy(pwdinfo->tx_prov_disc_info.ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN);
-+			pwdinfo->tx_prov_disc_info.ssid.SsidLength = P2P_WILDCARD_SSID_LEN;
-+		}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED)) {
-+			u8 union_ch = rtw_mi_get_union_chan(padapter);
-+			u8 union_bw = rtw_mi_get_union_bw(padapter);
-+			u8 union_offset = rtw_mi_get_union_offset(padapter);
-+
-+			set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
-+			rtw_leave_opch(padapter);
-+
-+		} else
-+			set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+#else
-+		set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-+#endif
-+
-+		_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+		if (rtw_mi_check_status(padapter, MI_LINKED))
-+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_PROVISION_TIMEOUT);
-+		else
-+			_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);
-+#else
-+		_set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT);
-+#endif /* CONFIG_CONCURRENT_MODE		 */
-+
-+	} else {
-+		RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__);
-+	}
-+exit:
-+
-+	return ret;
-+
-+}
-+
-+/*	Added by Albert 20110328
-+ *	This function is used to inform the driver the user had specified the pin code value or pbc
-+ *	to application. */
-+
-+static int rtw_p2p_got_wpsinfo(struct net_device *dev,
-+			       struct iw_request_info *info,
-+			       union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+	_adapter				*padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wifidirect_info	*pwdinfo = &(padapter->wdinfo);
-+
-+
-+	RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra);
-+	/*	Added by Albert 20110328 */
-+	/*	if the input data is P2P_NO_WPSINFO -> reset the wpsinfo */
-+	/*	if the input data is P2P_GOT_WPSINFO_PEER_DISPLAY_PIN -> the utility just input the PIN code got from the peer P2P device. */
-+	/*	if the input data is P2P_GOT_WPSINFO_SELF_DISPLAY_PIN -> the utility just got the PIN code from itself. */
-+	/*	if the input data is P2P_GOT_WPSINFO_PBC -> the utility just determine to use the PBC */
-+
-+	if (*extra == '0')
-+		pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;
-+	else if (*extra == '1')
-+		pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PEER_DISPLAY_PIN;
-+	else if (*extra == '2')
-+		pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_SELF_DISPLAY_PIN;
-+	else if (*extra == '3')
-+		pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PBC;
-+	else
-+		pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO;
-+
-+	return ret;
-+
-+}
-+
-+#endif /* CONFIG_P2P */
-+
-+static int rtw_p2p_set(struct net_device *dev,
-+		       struct iw_request_info *info,
-+		       union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+#ifdef CONFIG_P2P
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra);
-+
-+	if (_rtw_memcmp(extra, "enable=", 7))
-+		rtw_wext_p2p_enable(dev, info, wrqu, &extra[7]);
-+	else if (_rtw_memcmp(extra, "setDN=", 6)) {
-+		wrqu->data.length -= 6;
-+		rtw_p2p_setDN(dev, info, wrqu, &extra[6]);
-+	} else if (_rtw_memcmp(extra, "profilefound=", 13)) {
-+		wrqu->data.length -= 13;
-+		rtw_p2p_profilefound(dev, info, wrqu, &extra[13]);
-+	} else if (_rtw_memcmp(extra, "prov_disc=", 10)) {
-+		wrqu->data.length -= 10;
-+		rtw_p2p_prov_disc(dev, info, wrqu, &extra[10]);
-+	} else if (_rtw_memcmp(extra, "nego=", 5)) {
-+		wrqu->data.length -= 5;
-+		rtw_p2p_connect(dev, info, wrqu, &extra[5]);
-+	} else if (_rtw_memcmp(extra, "intent=", 7)) {
-+		/*	Commented by Albert 2011/03/23 */
-+		/*	The wrqu->data.length will include the null character */
-+		/*	So, we will decrease 7 + 1 */
-+		wrqu->data.length -= 8;
-+		rtw_p2p_set_intent(dev, info, wrqu, &extra[7]);
-+	} else if (_rtw_memcmp(extra, "ssid=", 5)) {
-+		wrqu->data.length -= 5;
-+		rtw_p2p_set_go_nego_ssid(dev, info, wrqu, &extra[5]);
-+	} else if (_rtw_memcmp(extra, "got_wpsinfo=", 12)) {
-+		wrqu->data.length -= 12;
-+		rtw_p2p_got_wpsinfo(dev, info, wrqu, &extra[12]);
-+	} else if (_rtw_memcmp(extra, "listen_ch=", 10)) {
-+		/*	Commented by Albert 2011/05/24 */
-+		/*	The wrqu->data.length will include the null character */
-+		/*	So, we will decrease (10 + 1)	 */
-+		wrqu->data.length -= 11;
-+		rtw_p2p_set_listen_ch(dev, info, wrqu, &extra[10]);
-+	} else if (_rtw_memcmp(extra, "op_ch=", 6)) {
-+		/*	Commented by Albert 2011/05/24 */
-+		/*	The wrqu->data.length will include the null character */
-+		/*	So, we will decrease (6 + 1)	 */
-+		wrqu->data.length -= 7;
-+		rtw_p2p_set_op_ch(dev, info, wrqu, &extra[6]);
-+	} else if (_rtw_memcmp(extra, "invite=", 7)) {
-+		wrqu->data.length -= 8;
-+		rtw_p2p_invite_req(dev, info, wrqu, &extra[7]);
-+	} else if (_rtw_memcmp(extra, "persistent=", 11)) {
-+		wrqu->data.length -= 11;
-+		rtw_p2p_set_persistent(dev, info, wrqu, &extra[11]);
-+	} else if (_rtw_memcmp(extra, "uuid=", 5)) {
-+		wrqu->data.length -= 5;
-+		ret = rtw_p2p_set_wps_uuid(dev, info, wrqu, &extra[5]);
-+	}
-+
-+#ifdef CONFIG_WFD
-+	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
-+		if (_rtw_memcmp(extra, "sa=", 3)) {
-+			/* sa: WFD Session Available information */
-+			wrqu->data.length -= 3;
-+			rtw_p2p_set_sa(dev, info, wrqu, &extra[3]);
-+		} else if (_rtw_memcmp(extra, "pc=", 3)) {
-+			/* pc: WFD Preferred Connection */
-+			wrqu->data.length -= 3;
-+			rtw_p2p_set_pc(dev, info, wrqu, &extra[3]);
-+		} else if (_rtw_memcmp(extra, "wfd_type=", 9)) {
-+			wrqu->data.length -= 9;
-+			rtw_p2p_set_wfd_device_type(dev, info, wrqu, &extra[9]);
-+		} else if (_rtw_memcmp(extra, "wfd_enable=", 11)) {
-+			wrqu->data.length -= 11;
-+			rtw_p2p_set_wfd_enable(dev, info, wrqu, &extra[11]);
-+		} else if (_rtw_memcmp(extra, "driver_iface=", 13)) {
-+			wrqu->data.length -= 13;
-+			rtw_p2p_set_driver_iface(dev, info, wrqu, &extra[13]);
-+		}
-+	}
-+#endif /* CONFIG_WFD */
-+
-+#endif /* CONFIG_P2P */
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_get(struct net_device *dev,
-+		       struct iw_request_info *info,
-+		       union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+#ifdef CONFIG_P2P
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (padapter->bShowGetP2PState)
-+		RTW_INFO("[%s] extra = %s\n", __FUNCTION__, (char *) wrqu->data.pointer);
-+
-+	if (_rtw_memcmp(wrqu->data.pointer, "status", 6))
-+		rtw_p2p_get_status(dev, info, wrqu, extra);
-+	else if (_rtw_memcmp(wrqu->data.pointer, "role", 4))
-+		rtw_p2p_get_role(dev, info, wrqu, extra);
-+	else if (_rtw_memcmp(wrqu->data.pointer, "peer_ifa", 8))
-+		rtw_p2p_get_peer_ifaddr(dev, info, wrqu, extra);
-+	else if (_rtw_memcmp(wrqu->data.pointer, "req_cm", 6))
-+		rtw_p2p_get_req_cm(dev, info, wrqu, extra);
-+	else if (_rtw_memcmp(wrqu->data.pointer, "peer_deva", 9)) {
-+		/*	Get the P2P device address when receiving the provision discovery request frame. */
-+		rtw_p2p_get_peer_devaddr(dev, info, wrqu, extra);
-+	} else if (_rtw_memcmp(wrqu->data.pointer, "group_id", 8))
-+		rtw_p2p_get_groupid(dev, info, wrqu, extra);
-+	else if (_rtw_memcmp(wrqu->data.pointer, "inv_peer_deva", 13)) {
-+		/*	Get the P2P device address when receiving the P2P Invitation request frame. */
-+		rtw_p2p_get_peer_devaddr_by_invitation(dev, info, wrqu, extra);
-+	} else if (_rtw_memcmp(wrqu->data.pointer, "op_ch", 5))
-+		rtw_p2p_get_op_ch(dev, info, wrqu, extra);
-+
-+#ifdef CONFIG_WFD
-+	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
-+		if (_rtw_memcmp(wrqu->data.pointer, "peer_port", 9))
-+			rtw_p2p_get_peer_wfd_port(dev, info, wrqu, extra);
-+		else if (_rtw_memcmp(wrqu->data.pointer, "wfd_sa", 6))
-+			rtw_p2p_get_peer_wfd_session_available(dev, info, wrqu, extra);
-+		else if (_rtw_memcmp(wrqu->data.pointer, "wfd_pc", 6))
-+			rtw_p2p_get_peer_wfd_preferred_connection(dev, info, wrqu, extra);
-+	}
-+#endif /* CONFIG_WFD */
-+
-+#endif /* CONFIG_P2P */
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_p2p_get2(struct net_device *dev,
-+			struct iw_request_info *info,
-+			union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+
-+#ifdef CONFIG_P2P
-+
-+	int length = wrqu->data.length;
-+	char *buffer = (u8 *)rtw_malloc(length);
-+
-+	if (buffer == NULL) {
-+		ret = -ENOMEM;
-+		goto bad;
-+	}
-+
-+	if (copy_from_user(buffer, wrqu->data.pointer, wrqu->data.length)) {
-+		ret = -EFAULT;
-+		goto bad;
-+	}
-+
-+	RTW_INFO("[%s] buffer = %s\n", __FUNCTION__, buffer);
-+
-+	if (_rtw_memcmp(buffer, "wpsCM=", 6))
-+		ret = rtw_p2p_get_wps_configmethod(dev, info, wrqu, extra, &buffer[6]);
-+	else if (_rtw_memcmp(buffer, "devN=", 5))
-+		ret = rtw_p2p_get_device_name(dev, info, wrqu, extra, &buffer[5]);
-+	else if (_rtw_memcmp(buffer, "dev_type=", 9))
-+		ret = rtw_p2p_get_device_type(dev, info, wrqu, extra, &buffer[9]);
-+	else if (_rtw_memcmp(buffer, "go_devadd=", 10))
-+		ret = rtw_p2p_get_go_device_address(dev, info, wrqu, extra, &buffer[10]);
-+	else if (_rtw_memcmp(buffer, "InvProc=", 8))
-+		ret = rtw_p2p_get_invitation_procedure(dev, info, wrqu, extra, &buffer[8]);
-+	else {
-+		snprintf(extra, sizeof("Command not found."), "Command not found.");
-+		wrqu->data.length = strlen(extra);
-+	}
-+
-+bad:
-+	if (buffer)
-+		rtw_mfree(buffer, length);
-+
-+#endif /* CONFIG_P2P */
-+
-+	return ret;
-+
-+}
-+
-+#ifdef CONFIG_MP_INCLUDED
-+static int rtw_cta_test_start(struct net_device *dev,
-+			      struct iw_request_info *info,
-+			      union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+	_adapter	*padapter = (_adapter *)rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
-+
-+	RTW_INFO("%s %s\n", __func__, extra);
-+	if (!strcmp(extra, "1"))
-+		hal_data->in_cta_test = 1;
-+	else
-+		hal_data->in_cta_test = 0;
-+
-+	rtw_hal_rcr_set_chk_bssid(padapter, MLME_ACTION_NONE);
-+
-+	return ret;
-+}
-+#endif
-+
-+#ifdef CONFIG_IOL
-+#include <rtw_iol.h>
-+#endif
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+#include "../../hal/hal_dm_acs.h"
-+#endif
-+#ifdef DBG_CMD_QUEUE
-+u8 dump_cmd_id = 0;
-+#endif
-+
-+static int rtw_dbg_port(struct net_device *dev,
-+			struct iw_request_info *info,
-+			union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+#ifdef CONFIG_RTW_DEBUG
-+	_irqL irqL;
-+	u8 major_cmd, minor_cmd;
-+	u16 arg;
-+	u32 extra_arg, *pdata, val32;
-+	struct sta_info *psta;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+	struct wlan_network *cur_network = &(pmlmepriv->cur_network);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+
-+	pdata = (u32 *)&wrqu->data;
-+
-+	val32 = *pdata;
-+	arg = (u16)(val32 & 0x0000ffff);
-+	major_cmd = (u8)(val32 >> 24);
-+	minor_cmd = (u8)((val32 >> 16) & 0x00ff);
-+
-+	extra_arg = *(pdata + 1);
-+
-+	switch (major_cmd) {
-+	case 0x70: /* read_reg */
-+		switch (minor_cmd) {
-+		case 1:
-+			RTW_INFO("rtw_read8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg));
-+			break;
-+		case 2:
-+			RTW_INFO("rtw_read16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg));
-+			break;
-+		case 4:
-+			RTW_INFO("rtw_read32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg));
-+			break;
-+		}
-+		break;
-+	case 0x71: /* write_reg */
-+		switch (minor_cmd) {
-+		case 1:
-+			rtw_write8(padapter, arg, extra_arg);
-+			RTW_INFO("rtw_write8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg));
-+			break;
-+		case 2:
-+			rtw_write16(padapter, arg, extra_arg);
-+			RTW_INFO("rtw_write16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg));
-+			break;
-+		case 4:
-+			rtw_write32(padapter, arg, extra_arg);
-+			RTW_INFO("rtw_write32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg));
-+			break;
-+		}
-+		break;
-+	case 0x72: /* read_bb */
-+		RTW_INFO("read_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff));
-+		break;
-+	case 0x73: /* write_bb */
-+		rtw_hal_write_bbreg(padapter, arg, 0xffffffff, extra_arg);
-+		RTW_INFO("write_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff));
-+		break;
-+	case 0x74: /* read_rf */
-+		RTW_INFO("read RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n", minor_cmd, arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff));
-+		break;
-+	case 0x75: /* write_rf */
-+		rtw_hal_write_rfreg(padapter, minor_cmd, arg, 0xffffffff, extra_arg);
-+		RTW_INFO("write RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n", minor_cmd, arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff));
-+		break;
-+
-+	case 0x76:
-+		switch (minor_cmd) {
-+		case 0x00: /* normal mode, */
-+			padapter->recvpriv.is_signal_dbg = 0;
-+			break;
-+		case 0x01: /* dbg mode */
-+			padapter->recvpriv.is_signal_dbg = 1;
-+			extra_arg = extra_arg > 100 ? 100 : extra_arg;
-+			padapter->recvpriv.signal_strength_dbg = extra_arg;
-+			break;
-+		}
-+		break;
-+	case 0x78: /* IOL test */
-+		switch (minor_cmd) {
-+		#ifdef CONFIG_IOL
-+		case 0x04: { /* LLT table initialization test */
-+			u8 page_boundary = 0xf9;
-+			{
-+				struct xmit_frame	*xmit_frame;
-+
-+				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
-+				if (xmit_frame == NULL) {
-+					ret = -ENOMEM;
-+					break;
-+				}
-+
-+				rtw_IOL_append_LLT_cmd(xmit_frame, page_boundary);
-+
-+
-+				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 500, 0))
-+					ret = -EPERM;
-+			}
-+		}
-+			break;
-+		case 0x05: { /* blink LED test */
-+			u16 reg = 0x4c;
-+			u32 blink_num = 50;
-+			u32 blink_delay_ms = 200;
-+			int i;
-+
-+			{
-+				struct xmit_frame	*xmit_frame;
-+
-+				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
-+				if (xmit_frame == NULL) {
-+					ret = -ENOMEM;
-+					break;
-+				}
-+
-+				for (i = 0; i < blink_num; i++) {
-+					#ifdef CONFIG_IOL_NEW_GENERATION
-+					rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x00, 0xff);
-+					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);
-+					rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x08, 0xff);
-+					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);
-+					#else
-+					rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x00);
-+					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);
-+					rtw_IOL_append_WB_cmd(xmit_frame, reg, 0x08);
-+					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, blink_delay_ms);
-+					#endif
-+				}
-+				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, (blink_delay_ms * blink_num * 2) + 200, 0))
-+					ret = -EPERM;
-+			}
-+		}
-+			break;
-+
-+		case 0x06: { /* continuous wirte byte test */
-+			u16 reg = arg;
-+			u16 start_value = 0;
-+			u32 write_num = extra_arg;
-+			int i;
-+			u8 final;
-+
-+			{
-+				struct xmit_frame	*xmit_frame;
-+
-+				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
-+				if (xmit_frame == NULL) {
-+					ret = -ENOMEM;
-+					break;
-+				}
-+
-+				for (i = 0; i < write_num; i++) {
-+					#ifdef CONFIG_IOL_NEW_GENERATION
-+					rtw_IOL_append_WB_cmd(xmit_frame, reg, i + start_value, 0xFF);
-+					#else
-+					rtw_IOL_append_WB_cmd(xmit_frame, reg, i + start_value);
-+					#endif
-+				}
-+				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0))
-+					ret = -EPERM;
-+			}
-+
-+			final = rtw_read8(padapter, reg);
-+			if (start_value + write_num - 1 == final)
-+				RTW_INFO("continuous IOL_CMD_WB_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final);
-+			else
-+				RTW_INFO("continuous IOL_CMD_WB_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final);
-+		}
-+			break;
-+
-+		case 0x07: { /* continuous wirte word test */
-+			u16 reg = arg;
-+			u16 start_value = 200;
-+			u32 write_num = extra_arg;
-+
-+			int i;
-+			u16 final;
-+
-+			{
-+				struct xmit_frame	*xmit_frame;
-+
-+				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
-+				if (xmit_frame == NULL) {
-+					ret = -ENOMEM;
-+					break;
-+				}
-+
-+				for (i = 0; i < write_num; i++) {
-+					#ifdef CONFIG_IOL_NEW_GENERATION
-+					rtw_IOL_append_WW_cmd(xmit_frame, reg, i + start_value, 0xFFFF);
-+					#else
-+					rtw_IOL_append_WW_cmd(xmit_frame, reg, i + start_value);
-+					#endif
-+				}
-+				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0))
-+					ret = -EPERM;
-+			}
-+
-+			final = rtw_read16(padapter, reg);
-+			if (start_value + write_num - 1 == final)
-+				RTW_INFO("continuous IOL_CMD_WW_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final);
-+			else
-+				RTW_INFO("continuous IOL_CMD_WW_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final);
-+		}
-+			break;
-+
-+		case 0x08: { /* continuous wirte dword test */
-+			u16 reg = arg;
-+			u32 start_value = 0x110000c7;
-+			u32 write_num = extra_arg;
-+
-+			int i;
-+			u32 final;
-+
-+			{
-+				struct xmit_frame	*xmit_frame;
-+
-+				xmit_frame = rtw_IOL_accquire_xmit_frame(padapter);
-+				if (xmit_frame == NULL) {
-+					ret = -ENOMEM;
-+					break;
-+				}
-+
-+				for (i = 0; i < write_num; i++) {
-+					#ifdef CONFIG_IOL_NEW_GENERATION
-+					rtw_IOL_append_WD_cmd(xmit_frame, reg, i + start_value, 0xFFFFFFFF);
-+					#else
-+					rtw_IOL_append_WD_cmd(xmit_frame, reg, i + start_value);
-+					#endif
-+				}
-+				if (_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 5000, 0))
-+					ret = -EPERM;
-+
-+			}
-+
-+			final = rtw_read32(padapter, reg);
-+			if (start_value + write_num - 1 == final)
-+				RTW_INFO("continuous IOL_CMD_WD_REG to 0x%x %u times Success, start:%u, final:%u\n", reg, write_num, start_value, final);
-+			else
-+				RTW_INFO("continuous IOL_CMD_WD_REG to 0x%x %u times Fail, start:%u, final:%u\n", reg, write_num, start_value, final);
-+		}
-+			break;
-+		#endif /* CONFIG_IOL */
-+		}
-+		break;
-+	case 0x79: {
-+		/*
-+		* dbg 0x79000000 [value], set RESP_TXAGC to + value, value:0~15
-+		* dbg 0x79010000 [value], set RESP_TXAGC to - value, value:0~15
-+		*/
-+		u8 value =  extra_arg & 0x0f;
-+		u8 sign = minor_cmd;
-+		u16 write_value = 0;
-+
-+		RTW_INFO("%s set RESP_TXAGC to %s %u\n", __func__, sign ? "minus" : "plus", value);
-+
-+		if (sign)
-+			value = value | 0x10;
-+
-+		write_value = value | (value << 5);
-+		rtw_write16(padapter, 0x6d9, write_value);
-+	}
-+		break;
-+	case 0x7a:
-+		receive_disconnect(padapter, pmlmeinfo->network.MacAddress
-+				   , WLAN_REASON_EXPIRATION_CHK, _FALSE);
-+		break;
-+	case 0x7F:
-+		switch (minor_cmd) {
-+		case 0x0:
-+			RTW_INFO("fwstate=0x%x\n", get_fwstate(pmlmepriv));
-+			break;
-+		case 0x01:
-+			RTW_INFO("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n",
-+				psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm,
-+				psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus);
-+			break;
-+		case 0x03:
-+			RTW_INFO("qos_option=%d\n", pmlmepriv->qospriv.qos_option);
-+#ifdef CONFIG_80211N_HT
-+			RTW_INFO("ht_option=%d\n", pmlmepriv->htpriv.ht_option);
-+#endif /* CONFIG_80211N_HT */
-+			break;
-+		case 0x04:
-+			RTW_INFO("cur_ch=%d\n", pmlmeext->cur_channel);
-+			RTW_INFO("cur_bw=%d\n", pmlmeext->cur_bwmode);
-+			RTW_INFO("cur_ch_off=%d\n", pmlmeext->cur_ch_offset);
-+
-+			RTW_INFO("oper_ch=%d\n", rtw_get_oper_ch(padapter));
-+			RTW_INFO("oper_bw=%d\n", rtw_get_oper_bw(padapter));
-+			RTW_INFO("oper_ch_offet=%d\n", rtw_get_oper_choffset(padapter));
-+
-+			break;
-+		case 0x05:
-+			psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
-+			if (psta) {
-+				RTW_INFO("SSID=%s\n", cur_network->network.Ssid.Ssid);
-+				RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
-+				RTW_INFO("cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
-+				RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self);
-+				RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n",
-+					psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);
-+#ifdef CONFIG_80211N_HT
-+				RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
-+				RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n"
-+					, psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);
-+				RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
-+				RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
-+#endif /* CONFIG_80211N_HT */
-+
-+				sta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta);
-+			} else
-+				RTW_INFO("can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress));
-+			break;
-+		case 0x06: {
-+				u64 tsf = 0;
-+
-+				tsf = rtw_hal_get_tsftr_by_port(padapter, extra_arg);
-+				RTW_INFO(" PORT-%d TSF :%21lld\n", extra_arg, tsf);
-+		}
-+			break;
-+		case 0x07:
-+			RTW_INFO("bSurpriseRemoved=%s, bDriverStopped=%s\n"
-+				, rtw_is_surprise_removed(padapter) ? "True" : "False"
-+				, rtw_is_drv_stopped(padapter) ? "True" : "False");
-+			break;
-+		case 0x08: {
-+			struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+			struct recv_priv  *precvpriv = &padapter->recvpriv;
-+
-+			RTW_INFO("free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d"
-+				", free_xmit_extbuf_cnt=%d, free_xframe_ext_cnt=%d"
-+				 ", free_recvframe_cnt=%d\n",
-+				pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt,
-+				pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt,
-+				 precvpriv->free_recvframe_cnt);
-+#ifdef CONFIG_USB_HCI
-+			RTW_INFO("rx_urb_pending_cn=%d\n", ATOMIC_READ(&(precvpriv->rx_pending_cnt)));
-+#endif
-+		}
-+			break;
-+		case 0x09: {
-+			int i;
-+			_list	*plist, *phead;
-+
-+#ifdef CONFIG_AP_MODE
-+			RTW_INFO_DUMP("sta_dz_bitmap:", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
-+			RTW_INFO_DUMP("tim_bitmap:", pstapriv->tim_bitmap, pstapriv->aid_bmp_len);
-+#endif
-+			_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+			for (i = 0; i < NUM_STA; i++) {
-+				phead = &(pstapriv->sta_hash[i]);
-+				plist = get_next(phead);
-+
-+				while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+					psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+
-+					plist = get_next(plist);
-+
-+					if (extra_arg == psta->cmn.aid) {
-+						RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
-+						RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self);
-+						RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n",
-+							psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);
-+#ifdef CONFIG_80211N_HT
-+						RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
-+						RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n",
-+							psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m,
-+							psta->htpriv.sgi_40m);
-+						RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
-+						RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
-+#endif /* CONFIG_80211N_HT */
-+
-+#ifdef CONFIG_AP_MODE
-+						RTW_INFO("capability=0x%x\n", psta->capability);
-+						RTW_INFO("flags=0x%x\n", psta->flags);
-+						RTW_INFO("wpa_psk=0x%x\n", psta->wpa_psk);
-+						RTW_INFO("wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher);
-+						RTW_INFO("wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher);
-+						RTW_INFO("qos_info=0x%x\n", psta->qos_info);
-+#endif
-+						RTW_INFO("dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy);
-+
-+						sta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta);
-+					}
-+
-+				}
-+			}
-+
-+			_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+		}
-+			break;
-+
-+		case 0x0b: { /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */
-+			/* u8 driver_vcs_en; */ /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */
-+			/* u8 driver_vcs_type; */ /* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */
-+
-+			if (arg == 0) {
-+				RTW_INFO("disable driver ctrl vcs\n");
-+				padapter->driver_vcs_en = 0;
-+			} else if (arg == 1) {
-+				RTW_INFO("enable driver ctrl vcs = %d\n", extra_arg);
-+				padapter->driver_vcs_en = 1;
-+
-+				if (extra_arg > 2)
-+					padapter->driver_vcs_type = 1;
-+				else
-+					padapter->driver_vcs_type = extra_arg;
-+			}
-+		}
-+			break;
-+		case 0x0c: { /* dump rx/tx packet */
-+			if (arg == 0) {
-+				RTW_INFO("dump rx packet (%d)\n", extra_arg);
-+				/* pHalData->bDumpRxPkt =extra_arg;						 */
-+				rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_RXPKT, &(extra_arg));
-+			} else if (arg == 1) {
-+				RTW_INFO("dump tx packet (%d)\n", extra_arg);
-+				rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(extra_arg));
-+			}
-+		}
-+			break;
-+		case 0x0e: {
-+			if (arg == 0) {
-+				RTW_INFO("disable driver ctrl rx_ampdu_factor\n");
-+				padapter->driver_rx_ampdu_factor = 0xFF;
-+			} else if (arg == 1) {
-+
-+				RTW_INFO("enable driver ctrl rx_ampdu_factor = %d\n", extra_arg);
-+
-+				if (extra_arg > 0x03)
-+					padapter->driver_rx_ampdu_factor = 0xFF;
-+				else
-+					padapter->driver_rx_ampdu_factor = extra_arg;
-+			}
-+		}
-+			break;
-+		#ifdef DBG_CONFIG_ERROR_DETECT
-+		case 0x0f: {
-+			if (extra_arg == 0) {
-+				RTW_INFO("###### silent reset test.......#####\n");
-+				rtw_hal_sreset_reset(padapter);
-+			} else {
-+				HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+				struct sreset_priv *psrtpriv = &pHalData->srestpriv;
-+				psrtpriv->dbg_trigger_point = extra_arg;
-+			}
-+
-+		}
-+			break;
-+		case 0x15: {
-+			struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+			RTW_INFO("==>silent resete cnts:%d\n", pwrpriv->ips_enter_cnts);
-+		}
-+			break;
-+
-+		#endif
-+
-+		case 0x10: /* driver version display */
-+			dump_drv_version(RTW_DBGDUMP);
-+			break;
-+		case 0x11: { /* dump linked status */
-+			int pre_mode;
-+			pre_mode = padapter->bLinkInfoDump;
-+			/* linked_info_dump(padapter,extra_arg); */
-+			if (extra_arg == 1 || (extra_arg == 0 && pre_mode == 1)) /* not consider pwr_saving 0: */
-+				padapter->bLinkInfoDump = extra_arg;
-+
-+			else if ((extra_arg == 2) || (extra_arg == 0 && pre_mode == 2)) { /* consider power_saving */
-+				/* RTW_INFO("linked_info_dump =%s\n", (padapter->bLinkInfoDump)?"enable":"disable") */
-+				linked_info_dump(padapter, extra_arg);
-+			}
-+
-+
-+
-+		}
-+			break;
-+#ifdef CONFIG_80211N_HT
-+		case 0x12: { /* set rx_stbc */
-+			struct registry_priv	*pregpriv = &padapter->registrypriv;
-+			/* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, 0x3: enable both 2.4g and 5g */
-+			/* default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */
-+			if (pregpriv && (extra_arg == 0 || extra_arg == 1 || extra_arg == 2 || extra_arg == 3)) {
-+				pregpriv->rx_stbc = extra_arg;
-+				RTW_INFO("set rx_stbc=%d\n", pregpriv->rx_stbc);
-+			} else
-+				RTW_INFO("get rx_stbc=%d\n", pregpriv->rx_stbc);
-+
-+		}
-+			break;
-+		case 0x13: { /* set ampdu_enable */
-+			struct registry_priv	*pregpriv = &padapter->registrypriv;
-+			/* 0: disable, 0x1:enable */
-+			if (pregpriv && extra_arg < 2) {
-+				pregpriv->ampdu_enable = extra_arg;
-+				RTW_INFO("set ampdu_enable=%d\n", pregpriv->ampdu_enable);
-+			} else
-+				RTW_INFO("get ampdu_enable=%d\n", pregpriv->ampdu_enable);
-+
-+		}
-+			break;
-+#endif
-+		case 0x14: { /* get wifi_spec */
-+			struct registry_priv	*pregpriv = &padapter->registrypriv;
-+			RTW_INFO("get wifi_spec=%d\n", pregpriv->wifi_spec);
-+
-+		}
-+			break;
-+
-+#ifdef DBG_FIXED_CHAN
-+		case 0x17: {
-+			struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+			printk("===>  Fixed channel to %d\n", extra_arg);
-+			pmlmeext->fixed_chan = extra_arg;
-+
-+		}
-+			break;
-+#endif
-+#ifdef CONFIG_80211N_HT
-+		case 0x19: {
-+			struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+			/* extra_arg : */
-+			/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, */
-+			/* BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */
-+			if (arg == 0) {
-+				RTW_INFO("driver disable LDPC\n");
-+				pregistrypriv->ldpc_cap = 0x00;
-+			} else if (arg == 1) {
-+				RTW_INFO("driver set LDPC cap = 0x%x\n", extra_arg);
-+				pregistrypriv->ldpc_cap = (u8)(extra_arg & 0x33);
-+			}
-+		}
-+			break;
-+		case 0x1a: {
-+			struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+			/* extra_arg : */
-+			/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, */
-+			/* BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */
-+			if (arg == 0) {
-+				RTW_INFO("driver disable STBC\n");
-+				pregistrypriv->stbc_cap = 0x00;
-+			} else if (arg == 1) {
-+				RTW_INFO("driver set STBC cap = 0x%x\n", extra_arg);
-+				pregistrypriv->stbc_cap = (u8)(extra_arg & 0x33);
-+			}
-+		}
-+			break;
-+#endif /* CONFIG_80211N_HT */
-+		case 0x1b: {
-+			struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+
-+			if (arg == 0) {
-+				RTW_INFO("disable driver ctrl max_rx_rate, reset to default_rate_set\n");
-+				init_mlme_default_rate_set(padapter);
-+#ifdef CONFIG_80211N_HT
-+				pregistrypriv->ht_enable = (u8)rtw_ht_enable;
-+#endif /* CONFIG_80211N_HT */
-+			} else if (arg == 1) {
-+
-+				int i;
-+				u8 max_rx_rate;
-+
-+				RTW_INFO("enable driver ctrl max_rx_rate = 0x%x\n", extra_arg);
-+
-+				max_rx_rate = (u8)extra_arg;
-+
-+				if (max_rx_rate < 0xc) { /* max_rx_rate < MSC0->B or G -> disable HT */
-+#ifdef CONFIG_80211N_HT
-+					pregistrypriv->ht_enable = 0;
-+#endif /* CONFIG_80211N_HT */
-+					for (i = 0; i < NumRates; i++) {
-+						if (pmlmeext->datarate[i] > max_rx_rate)
-+							pmlmeext->datarate[i] = 0xff;
-+					}
-+
-+				}
-+#ifdef CONFIG_80211N_HT
-+				else if (max_rx_rate < 0x1c) { /* mcs0~mcs15 */
-+					u32 mcs_bitmap = 0x0;
-+
-+					for (i = 0; i < ((max_rx_rate + 1) - 0xc); i++)
-+						mcs_bitmap |= BIT(i);
-+
-+					set_mcs_rate_by_mask(pmlmeext->default_supported_mcs_set, mcs_bitmap);
-+				}
-+#endif /* CONFIG_80211N_HT							 */
-+			}
-+		}
-+			break;
-+		case 0x1c: { /* enable/disable driver control AMPDU Density for peer sta's rx */
-+			if (arg == 0) {
-+				RTW_INFO("disable driver ctrl ampdu density\n");
-+				padapter->driver_ampdu_spacing = 0xFF;
-+			} else if (arg == 1) {
-+
-+				RTW_INFO("enable driver ctrl ampdu density = %d\n", extra_arg);
-+
-+				if (extra_arg > 0x07)
-+					padapter->driver_ampdu_spacing = 0xFF;
-+				else
-+					padapter->driver_ampdu_spacing = extra_arg;
-+			}
-+		}
-+			break;
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+		case 0x1e: {
-+			RTW_INFO("===========================================\n");
-+			rtw_noise_measure_curchan(padapter);
-+			RTW_INFO("===========================================\n");
-+		}
-+			break;
-+#endif
-+
-+
-+#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_SDIO_INDIRECT_ACCESS) && defined(DBG_SDIO_INDIRECT_ACCESS)
-+		case 0x1f:
-+			{
-+				int i, j = 0, test_cnts = 0;
-+				static u8 test_code = 0x5A;
-+				static u32 data_misatch_cnt = 0, d_acc_err_cnt = 0;
-+
-+				u32 d_data, i_data;
-+				u32 imr;
-+
-+				test_cnts = extra_arg;
-+				for (i = 0; i < test_cnts; i++) {
-+					if (RTW_CANNOT_IO(padapter))
-+						break;
-+
-+					rtw_write8(padapter, 0x07, test_code);
-+
-+					d_data = rtw_read32(padapter, 0x04);
-+					imr =  rtw_read32(padapter, 0x10250014);
-+					rtw_write32(padapter, 0x10250014, 0);
-+					rtw_msleep_os(50);
-+
-+					i_data = rtw_sd_iread32(padapter, 0x04);
-+
-+					rtw_write32(padapter, 0x10250014, imr);
-+
-+					if (d_data != i_data) {
-+						data_misatch_cnt++;
-+						RTW_ERR("d_data :0x%08x, i_data : 0x%08x\n", d_data, i_data);
-+					}
-+
-+					if (test_code != (i_data >> 24)) {
-+						d_acc_err_cnt++;
-+						rtw_write8(padapter, 0x07, 0xAA);
-+						RTW_ERR("test_code :0x%02x, i_data : 0x%08x\n", test_code, i_data);
-+					}
-+					if ((j++) == 100) {
-+						rtw_msleep_os(2000);
-+						RTW_INFO(" Indirect access testing..........%d/%d\n", i, test_cnts);
-+						j = 0;
-+					}
-+
-+					test_code = ~test_code;
-+					rtw_msleep_os(50);
-+				}
-+				RTW_INFO("========Indirect access test=========\n");
-+				RTW_INFO(" test_cnts = %d\n", test_cnts);
-+				RTW_INFO(" direct & indirect read32 data missatch cnts = %d\n", data_misatch_cnt);
-+				RTW_INFO(" indirect rdata is not equal to wdata cnts = %d\n", d_acc_err_cnt);
-+				RTW_INFO("========Indirect access test=========\n\n");
-+				data_misatch_cnt = d_acc_err_cnt = 0;
-+
-+			}
-+			break;
-+#endif
-+		case 0x20:
-+			{
-+				if (arg == 0xAA) {
-+					u8 page_offset, page_num;
-+
-+					page_offset = (u8)(extra_arg >> 16);
-+					page_num = (u8)(extra_arg & 0xFF);
-+					rtw_dump_rsvd_page(RTW_DBGDUMP, padapter, page_offset, page_num);
-+				}
-+#ifdef CONFIG_SUPPORT_FIFO_DUMP
-+				else {
-+					u8 fifo_sel;
-+					u32 addr, size;
-+
-+					fifo_sel = (u8)(arg & 0x0F);
-+					addr = (extra_arg >> 16) & 0xFFFF;
-+					size = extra_arg & 0xFFFF;
-+					rtw_dump_fifo(RTW_DBGDUMP, padapter, fifo_sel, addr, size);
-+				}
-+#endif
-+			}
-+			break;
-+
-+		case 0x23: {
-+			RTW_INFO("turn %s the bNotifyChannelChange Variable\n", (extra_arg == 1) ? "on" : "off");
-+			padapter->bNotifyChannelChange = extra_arg;
-+			break;
-+		}
-+		case 0x24: {
-+#ifdef CONFIG_P2P
-+			RTW_INFO("turn %s the bShowGetP2PState Variable\n", (extra_arg == 1) ? "on" : "off");
-+			padapter->bShowGetP2PState = extra_arg;
-+#endif /* CONFIG_P2P */
-+			break;
-+		}
-+#ifdef CONFIG_GPIO_API
-+		case 0x25: { /* Get GPIO register */
-+			/*
-+			* dbg 0x7f250000 [gpio_num], Get gpio value, gpio_num:0~7
-+			*/
-+
-+			u8 value;
-+			RTW_INFO("Read GPIO Value  extra_arg = %d\n", extra_arg);
-+			value = rtw_hal_get_gpio(padapter, extra_arg);
-+			RTW_INFO("Read GPIO Value = %d\n", value);
-+			break;
-+		}
-+		case 0x26: { /* Set GPIO direction */
-+
-+			/* dbg 0x7f26000x [y], Set gpio direction,
-+			* x: gpio_num,4~7  y: indicate direction, 0~1
-+			*/
-+
-+			int value;
-+			RTW_INFO("Set GPIO Direction! arg = %d ,extra_arg=%d\n", arg , extra_arg);
-+			value = rtw_hal_config_gpio(padapter, arg, extra_arg);
-+			RTW_INFO("Set GPIO Direction %s\n", (value == -1) ? "Fail!!!" : "Success");
-+			break;
-+		}
-+		case 0x27: { /* Set GPIO output direction value */
-+			/*
-+			* dbg 0x7f27000x [y], Set gpio output direction value,
-+			* x: gpio_num,4~7  y: indicate direction, 0~1
-+			*/
-+
-+			int value;
-+			RTW_INFO("Set GPIO Value! arg = %d ,extra_arg=%d\n", arg , extra_arg);
-+			value = rtw_hal_set_gpio_output_value(padapter, arg, extra_arg);
-+			RTW_INFO("Set GPIO Value %s\n", (value == -1) ? "Fail!!!" : "Success");
-+			break;
-+		}
-+#endif
-+#ifdef DBG_CMD_QUEUE
-+		case 0x28: {
-+			dump_cmd_id = extra_arg;
-+			RTW_INFO("dump_cmd_id:%d\n", dump_cmd_id);
-+		}
-+			break;
-+#endif /* DBG_CMD_QUEUE */
-+		case 0xaa: {
-+			if ((extra_arg & 0x7F) > 0x3F)
-+				extra_arg = 0xFF;
-+			RTW_INFO("chang data rate to :0x%02x\n", extra_arg);
-+			padapter->fix_rate = extra_arg;
-+		}
-+			break;
-+		case 0xdd: { /* registers dump , 0 for mac reg,1 for bb reg, 2 for rf reg */
-+			if (extra_arg == 0)
-+				mac_reg_dump(RTW_DBGDUMP, padapter);
-+			else if (extra_arg == 1)
-+				bb_reg_dump(RTW_DBGDUMP, padapter);
-+			else if (extra_arg == 2)
-+				rf_reg_dump(RTW_DBGDUMP, padapter);
-+			else if (extra_arg == 11)
-+				bb_reg_dump_ex(RTW_DBGDUMP, padapter);
-+		}
-+			break;
-+
-+		case 0xee: {
-+			RTW_INFO(" === please control /proc  to trun on/off PHYDM func ===\n");
-+		}
-+			break;
-+
-+		case 0xfd:
-+			rtw_write8(padapter, 0xc50, arg);
-+			RTW_INFO("wr(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50));
-+			rtw_write8(padapter, 0xc58, arg);
-+			RTW_INFO("wr(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58));
-+			break;
-+		case 0xfe:
-+			RTW_INFO("rd(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50));
-+			RTW_INFO("rd(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58));
-+			break;
-+		case 0xff: {
-+			RTW_INFO("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210));
-+			RTW_INFO("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608));
-+			RTW_INFO("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280));
-+			RTW_INFO("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284));
-+			RTW_INFO("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288));
-+
-+			RTW_INFO("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664));
-+
-+
-+			RTW_INFO("\n");
-+
-+			RTW_INFO("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430));
-+			RTW_INFO("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438));
-+
-+			RTW_INFO("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440));
-+
-+			RTW_INFO("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458));
-+
-+			RTW_INFO("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484));
-+			RTW_INFO("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488));
-+
-+			RTW_INFO("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444));
-+			RTW_INFO("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448));
-+			RTW_INFO("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c));
-+			RTW_INFO("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450));
-+		}
-+			break;
-+		}
-+		break;
-+	default:
-+		RTW_INFO("error dbg cmd!\n");
-+		break;
-+	}
-+
-+#endif
-+	return ret;
-+
-+}
-+
-+#ifdef CONFIG_IOCTL_WEXT
-+static int wpa_set_param(struct net_device *dev, u8 name, u32 value)
-+{
-+	uint ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	switch (name) {
-+	case IEEE_PARAM_WPA_ENABLED:
-+
-+		padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; /* 802.1x */
-+
-+		/* ret = ieee80211_wpa_enable(ieee, value); */
-+
-+		switch ((value) & 0xff) {
-+		case 1: /* WPA */
-+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK; /* WPA_PSK */
-+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled;
-+			break;
-+		case 2: /* WPA2 */
-+			padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; /* WPA2_PSK */
-+			padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled;
-+			break;
-+		}
-+
-+
-+		break;
-+
-+	case IEEE_PARAM_TKIP_COUNTERMEASURES:
-+		/* ieee->tkip_countermeasures=value; */
-+		break;
-+
-+	case IEEE_PARAM_DROP_UNENCRYPTED: {
-+		/* HACK:
-+		 *
-+		 * wpa_supplicant calls set_wpa_enabled when the driver
-+		 * is loaded and unloaded, regardless of if WPA is being
-+		 * used.  No other calls are made which can be used to
-+		 * determine if encryption will be used or not prior to
-+		 * association being expected.  If encryption is not being
-+		 * used, drop_unencrypted is set to false, else true -- we
-+		 * can use this to determine if the CAP_PRIVACY_ON bit should
-+		 * be set.
-+		 */
-+
-+#if 0
-+		struct ieee80211_security sec = {
-+			.flags = SEC_ENABLED,
-+			.enabled = value,
-+		};
-+		ieee->drop_unencrypted = value;
-+		/* We only change SEC_LEVEL for open mode. Others
-+		 * are set by ipw_wpa_set_encryption.
-+		 */
-+		if (!value) {
-+			sec.flags |= SEC_LEVEL;
-+			sec.level = SEC_LEVEL_0;
-+		} else {
-+			sec.flags |= SEC_LEVEL;
-+			sec.level = SEC_LEVEL_1;
-+		}
-+		if (ieee->set_security)
-+			ieee->set_security(ieee->dev, &sec);
-+#endif
-+		break;
-+
-+	}
-+	case IEEE_PARAM_PRIVACY_INVOKED:
-+
-+		/* ieee->privacy_invoked=value; */
-+
-+		break;
-+
-+	case IEEE_PARAM_AUTH_ALGS:
-+
-+		ret = wpa_set_auth_algs(dev, value);
-+
-+		break;
-+
-+	case IEEE_PARAM_IEEE_802_1X:
-+
-+		/* ieee->ieee802_1x=value;		 */
-+
-+		break;
-+
-+	case IEEE_PARAM_WPAX_SELECT:
-+
-+		/* added for WPA2 mixed mode */
-+		/*RTW_WARN("------------------------>wpax value = %x\n", value);*/
-+		/*
-+		spin_lock_irqsave(&ieee->wpax_suitlist_lock,flags);
-+		ieee->wpax_type_set = 1;
-+		ieee->wpax_type_notify = value;
-+		spin_unlock_irqrestore(&ieee->wpax_suitlist_lock,flags);
-+		*/
-+
-+		break;
-+
-+	default:
-+
-+
-+
-+		ret = -EOPNOTSUPP;
-+
-+
-+		break;
-+
-+	}
-+
-+	return ret;
-+
-+}
-+
-+static int wpa_mlme(struct net_device *dev, u32 command, u32 reason)
-+{
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	switch (command) {
-+	case IEEE_MLME_STA_DEAUTH:
-+
-+		if (!rtw_set_802_11_disassociate(padapter))
-+			ret = -1;
-+
-+		break;
-+
-+	case IEEE_MLME_STA_DISASSOC:
-+
-+		if (!rtw_set_802_11_disassociate(padapter))
-+			ret = -1;
-+
-+		break;
-+
-+	default:
-+		ret = -EOPNOTSUPP;
-+		break;
-+	}
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	rtw_rson_do_disconnect(padapter);
-+#endif
-+	return ret;
-+
-+}
-+
-+static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p)
-+{
-+	struct ieee_param *param;
-+	uint ret = 0;
-+
-+	/* down(&ieee->wx_sem);	 */
-+
-+	if (p->length < sizeof(struct ieee_param) || !p->pointer) {
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
-+	param = (struct ieee_param *)rtw_malloc(p->length);
-+	if (param == NULL) {
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	if (copy_from_user(param, p->pointer, p->length)) {
-+		rtw_mfree((u8 *)param, p->length);
-+		ret = -EFAULT;
-+		goto out;
-+	}
-+
-+	switch (param->cmd) {
-+
-+	case IEEE_CMD_SET_WPA_PARAM:
-+		ret = wpa_set_param(dev, param->u.wpa_param.name, param->u.wpa_param.value);
-+		break;
-+
-+	case IEEE_CMD_SET_WPA_IE:
-+		/* ret = wpa_set_wpa_ie(dev, param, p->length); */
-+		ret =  rtw_set_wpa_ie((_adapter *)rtw_netdev_priv(dev), (char *)param->u.wpa_ie.data, (u16)param->u.wpa_ie.len);
-+		break;
-+
-+	case IEEE_CMD_SET_ENCRYPTION:
-+		ret = wpa_set_encryption(dev, param, p->length);
-+		break;
-+
-+	case IEEE_CMD_MLME:
-+		ret = wpa_mlme(dev, param->u.mlme.command, param->u.mlme.reason_code);
-+		break;
-+
-+	default:
-+		RTW_INFO("Unknown WPA supplicant request: %d\n", param->cmd);
-+		ret = -EOPNOTSUPP;
-+		break;
-+
-+	}
-+
-+	if (ret == 0 && copy_to_user(p->pointer, param, p->length))
-+		ret = -EFAULT;
-+
-+	rtw_mfree((u8 *)param, p->length);
-+
-+out:
-+
-+	/* up(&ieee->wx_sem); */
-+
-+	return ret;
-+
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len)
-+{
-+	int ret = 0;
-+	u32 wep_key_idx, wep_key_len, wep_total_len;
-+	NDIS_802_11_WEP	*pwep = NULL;
-+	struct sta_info *psta = NULL, *pbcmc_sta = NULL;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	param->u.crypt.err = 0;
-+	param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0';
-+
-+	/* sizeof(struct ieee_param) = 64 bytes; */
-+	/* if (param_len !=  (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) */
-+	if (param_len !=  sizeof(struct ieee_param) + param->u.crypt.key_len) {
-+		ret =  -EINVAL;
-+		goto exit;
-+	}
-+
-+	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
-+	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
-+	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) {
-+		if (param->u.crypt.idx >= WEP_KEYS
-+#ifdef CONFIG_IEEE80211W
-+		    && param->u.crypt.idx > BIP_MAX_KEYID
-+#endif /* CONFIG_IEEE80211W */
-+		   ) {
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+	} else {
-+		psta = rtw_get_stainfo(pstapriv, param->sta_addr);
-+		if (!psta) {
-+			/* ret = -EINVAL; */
-+			RTW_INFO("rtw_set_encryption(), sta has already been removed or never been added\n");
-+			goto exit;
-+		}
-+	}
-+
-+	if (strcmp(param->u.crypt.alg, "none") == 0 && (psta == NULL)) {
-+		/* todo:clear default encryption keys */
-+
-+		psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open;
-+		psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;
-+		psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
-+		psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
-+
-+		RTW_INFO("clear default encryption keys, keyid=%d\n", param->u.crypt.idx);
-+
-+		goto exit;
-+	}
-+
-+
-+	if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta == NULL)) {
-+		RTW_INFO("r871x_set_encryption, crypt.alg = WEP\n");
-+
-+		wep_key_idx = param->u.crypt.idx;
-+		wep_key_len = param->u.crypt.key_len;
-+
-+		RTW_INFO("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len);
-+
-+		if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) {
-+			ret = -EINVAL;
-+			goto exit;
-+		}
-+
-+
-+		if (wep_key_len > 0) {
-+			wep_key_len = wep_key_len <= 5 ? 5 : 13;
-+			wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);
-+			pwep = (NDIS_802_11_WEP *)rtw_malloc(wep_total_len);
-+			if (pwep == NULL) {
-+				RTW_INFO(" r871x_set_encryption: pwep allocate fail !!!\n");
-+				goto exit;
-+			}
-+
-+			_rtw_memset(pwep, 0, wep_total_len);
-+
-+			pwep->KeyLength = wep_key_len;
-+			pwep->Length = wep_total_len;
-+
-+		}
-+
-+		pwep->KeyIndex = wep_key_idx;
-+
-+		_rtw_memcpy(pwep->KeyMaterial,  param->u.crypt.key, pwep->KeyLength);
-+
-+		if (param->u.crypt.set_tx) {
-+			RTW_INFO("wep, set_tx=1\n");
-+
-+			psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto;
-+			psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled;
-+			psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
-+			psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
-+
-+			if (pwep->KeyLength == 13) {
-+				psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
-+				psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
-+			}
-+
-+
-+			psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx;
-+
-+			_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength);
-+
-+			psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength;
-+
-+			rtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 1);
-+		} else {
-+			RTW_INFO("wep, set_tx=0\n");
-+
-+			/* don't update "psecuritypriv->dot11PrivacyAlgrthm" and  */
-+			/* "psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to cam */
-+
-+			_rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength);
-+
-+			psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength;
-+
-+			rtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 0);
-+		}
-+
-+		goto exit;
-+
-+	}
-+
-+
-+	if (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) /*  */ { /* group key */
-+		if (param->u.crypt.set_tx == 1) {
-+			if (strcmp(param->u.crypt.alg, "WEP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set WEP TX GTK idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+				psecuritypriv->dot118021XGrpPrivacy = _WEP40_;
-+				if (param->u.crypt.key_len == 13)
-+					psecuritypriv->dot118021XGrpPrivacy = _WEP104_;
-+
-+			} else if (strcmp(param->u.crypt.alg, "TKIP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set TKIP TX GTK idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+				psecuritypriv->dot118021XGrpPrivacy = _TKIP_;
-+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+				/* set mic key */
-+				_rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
-+				_rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
-+				psecuritypriv->busetkipkey = _TRUE;
-+
-+			} else if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set CCMP TX GTK idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+				psecuritypriv->dot118021XGrpPrivacy = _AES_;
-+				_rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+
-+			#ifdef CONFIG_IEEE80211W
-+			} else if (strcmp(param->u.crypt.alg, "BIP") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" set TX IGTK idx:%u, len:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len);
-+				_rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+				psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx;
-+				psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+				psecuritypriv->binstallBIPkey = _TRUE;
-+				goto exit;
-+			#endif /* CONFIG_IEEE80211W */
-+
-+			} else if (strcmp(param->u.crypt.alg, "none") == 0) {
-+				RTW_INFO(FUNC_ADPT_FMT" clear group key, idx:%u\n"
-+					, FUNC_ADPT_ARG(padapter), param->u.crypt.idx);
-+				psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
-+			} else {
-+				RTW_WARN(FUNC_ADPT_FMT" set group key, not support\n"
-+					, FUNC_ADPT_ARG(padapter));
-+				goto exit;
-+			}
-+
-+			psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx;
-+			pbcmc_sta = rtw_get_bcmc_stainfo(padapter);
-+			if (pbcmc_sta) {
-+				pbcmc_sta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+				pbcmc_sta->ieee8021x_blocked = _FALSE;
-+				pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy			 */
-+			}
-+			psecuritypriv->binstallGrpkey = _TRUE;
-+			psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */
-+
-+			rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx);
-+		}
-+
-+		goto exit;
-+
-+	}
-+
-+	if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) { /* psk/802_1x */
-+		if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
-+			if (param->u.crypt.set_tx == 1) {
-+				_rtw_memcpy(psta->dot118021x_UncstKey.skey,  param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len));
-+
-+				if (strcmp(param->u.crypt.alg, "WEP") == 0) {
-+					RTW_INFO(FUNC_ADPT_FMT" set WEP PTK of "MAC_FMT" idx:%u, len:%u\n"
-+						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+						, param->u.crypt.idx, param->u.crypt.key_len);
-+					psta->dot118021XPrivacy = _WEP40_;
-+					if (param->u.crypt.key_len == 13)
-+						psta->dot118021XPrivacy = _WEP104_;
-+
-+				} else if (strcmp(param->u.crypt.alg, "TKIP") == 0) {
-+					RTW_INFO(FUNC_ADPT_FMT" set TKIP PTK of "MAC_FMT" idx:%u, len:%u\n"
-+						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+						, param->u.crypt.idx, param->u.crypt.key_len);
-+					psta->dot118021XPrivacy = _TKIP_;
-+					/* set mic key */
-+					_rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8);
-+					_rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8);
-+					psecuritypriv->busetkipkey = _TRUE;
-+
-+				} else if (strcmp(param->u.crypt.alg, "CCMP") == 0) {
-+					RTW_INFO(FUNC_ADPT_FMT" set CCMP PTK of "MAC_FMT" idx:%u, len:%u\n"
-+						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+						, param->u.crypt.idx, param->u.crypt.key_len);
-+					psta->dot118021XPrivacy = _AES_;
-+
-+				} else if (strcmp(param->u.crypt.alg, "none") == 0) {
-+					RTW_INFO(FUNC_ADPT_FMT" clear pairwise key of "MAC_FMT" idx:%u\n"
-+						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)
-+						, param->u.crypt.idx);
-+					psta->dot118021XPrivacy = _NO_PRIVACY_;
-+
-+				} else {
-+					RTW_WARN(FUNC_ADPT_FMT" set pairwise key of "MAC_FMT", not support\n"
-+						, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
-+					goto exit;
-+				}
-+
-+				psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+				psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq);
-+				psta->ieee8021x_blocked = _FALSE;
-+
-+				if (psta->dot118021XPrivacy != _NO_PRIVACY_) {
-+					psta->bpairwise_key_installed = _TRUE;
-+
-+					/* WPA2 key-handshake has completed */
-+					if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK)
-+						psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE);
-+				}
-+
-+				rtw_ap_set_pairwise_key(padapter, psta);
-+			} else {
-+				RTW_WARN(FUNC_ADPT_FMT" set group key of "MAC_FMT", not support\n"
-+					, FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
-+				goto exit;
-+			}
-+
-+		}
-+
-+	}
-+
-+exit:
-+
-+	if (pwep)
-+		rtw_mfree((u8 *)pwep, wep_total_len);
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int len)
-+{
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	unsigned char *pbuf = param->u.bcn_ie.buf;
-+
-+
-+	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
-+		return -EINVAL;
-+
-+	_rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2);
-+
-+	if ((pstapriv->max_num_sta > NUM_STA) || (pstapriv->max_num_sta <= 0))
-+		pstapriv->max_num_sta = NUM_STA;
-+
-+
-+	if (rtw_check_beacon_data(padapter, pbuf, (len - 12 - 2)) == _SUCCESS) /* 12 = param header, 2:no packed */
-+		ret = 0;
-+	else
-+		ret = -EINVAL;
-+
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_hostapd_sta_flush(struct net_device *dev)
-+{
-+	/* _irqL irqL; */
-+	/* _list	*phead, *plist; */
-+	int ret = 0;
-+	/* struct sta_info *psta = NULL; */
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	/* struct sta_priv *pstapriv = &padapter->stapriv; */
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	flush_all_cam_entry(padapter);	/* clear CAM */
-+#ifdef CONFIG_AP_MODE
-+	ret = rtw_sta_flush(padapter, _TRUE);
-+#endif
-+	return ret;
-+
-+}
-+
-+static int rtw_add_sta(struct net_device *dev, struct ieee_param *param)
-+{
-+	int ret = 0;
-+	struct sta_info *psta = NULL;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+	RTW_INFO("rtw_add_sta(aid=%d)=" MAC_FMT "\n", param->u.add_sta.aid, MAC_ARG(param->sta_addr));
-+
-+	if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE)
-+		return -EINVAL;
-+
-+	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
-+	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
-+	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
-+		return -EINVAL;
-+
-+#if 0
-+	psta = rtw_get_stainfo(pstapriv, param->sta_addr);
-+	if (psta) {
-+		RTW_INFO("rtw_add_sta(), free has been added psta=%p\n", psta);
-+		/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);		 */
-+		rtw_free_stainfo(padapter,  psta);
-+		/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
-+
-+		psta = NULL;
-+	}
-+#endif
-+	/* psta = rtw_alloc_stainfo(pstapriv, param->sta_addr); */
-+	psta = rtw_get_stainfo(pstapriv, param->sta_addr);
-+	if (psta) {
-+		int flags = param->u.add_sta.flags;
-+
-+		/* RTW_INFO("rtw_add_sta(), init sta's variables, psta=%p\n", psta); */
-+
-+		psta->cmn.aid = param->u.add_sta.aid;/* aid=1~2007 */
-+
-+		_rtw_memcpy(psta->bssrateset, param->u.add_sta.tx_supp_rates, 16);
-+
-+
-+		/* check wmm cap. */
-+		if (WLAN_STA_WME & flags)
-+			psta->qos_option = 1;
-+		else
-+			psta->qos_option = 0;
-+
-+		if (pmlmepriv->qospriv.qos_option == 0)
-+			psta->qos_option = 0;
-+
-+
-+#ifdef CONFIG_80211N_HT
-+		/* chec 802.11n ht cap. */
-+		if (padapter->registrypriv.ht_enable &&
-+			is_supported_ht(padapter->registrypriv.wireless_mode) &&
-+			(WLAN_STA_HT & flags)) {
-+			psta->htpriv.ht_option = _TRUE;
-+			psta->qos_option = 1;
-+			_rtw_memcpy((void *)&psta->htpriv.ht_cap, (void *)&param->u.add_sta.ht_cap, sizeof(struct rtw_ieee80211_ht_cap));
-+		} else
-+			psta->htpriv.ht_option = _FALSE;
-+
-+		if (pmlmepriv->htpriv.ht_option == _FALSE)
-+			psta->htpriv.ht_option = _FALSE;
-+
-+#endif
-+
-+
-+		update_sta_info_apmode(padapter, psta);
-+
-+
-+	} else
-+		ret = -ENOMEM;
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_del_sta(struct net_device *dev, struct ieee_param *param)
-+{
-+	_irqL irqL;
-+	int ret = 0;
-+	struct sta_info *psta = NULL;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+	RTW_INFO("rtw_del_sta=" MAC_FMT "\n", MAC_ARG(param->sta_addr));
-+
-+	if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE)
-+		return -EINVAL;
-+
-+	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
-+	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
-+	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
-+		return -EINVAL;
-+
-+	psta = rtw_get_stainfo(pstapriv, param->sta_addr);
-+	if (psta) {
-+		u8 updated = _FALSE;
-+
-+		/* RTW_INFO("free psta=%p, aid=%d\n", psta, psta->cmn.aid); */
-+
-+		_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+		if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
-+			rtw_list_delete(&psta->asoc_list);
-+			pstapriv->asoc_list_cnt--;
-+			#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+			if (psta->tbtx_enable)
-+				pstapriv->tbtx_asoc_list_cnt--;
-+			#endif
-+			updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE);
-+
-+		}
-+		_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-+
-+		associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
-+
-+		psta = NULL;
-+
-+	} else {
-+		RTW_INFO("rtw_del_sta(), sta has already been removed or never been added\n");
-+
-+		/* ret = -1; */
-+	}
-+
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *param, int len)
-+{
-+	int ret = 0;
-+	struct sta_info *psta = NULL;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct ieee_param_ex *param_ex = (struct ieee_param_ex *)param;
-+	struct sta_data *psta_data = (struct sta_data *)param_ex->data;
-+
-+	RTW_INFO("rtw_ioctl_get_sta_info, sta_addr: " MAC_FMT "\n", MAC_ARG(param_ex->sta_addr));
-+
-+	if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE)
-+		return -EINVAL;
-+
-+	if (param_ex->sta_addr[0] == 0xff && param_ex->sta_addr[1] == 0xff &&
-+	    param_ex->sta_addr[2] == 0xff && param_ex->sta_addr[3] == 0xff &&
-+	    param_ex->sta_addr[4] == 0xff && param_ex->sta_addr[5] == 0xff)
-+		return -EINVAL;
-+
-+	psta = rtw_get_stainfo(pstapriv, param_ex->sta_addr);
-+	if (psta) {
-+#if 0
-+		struct {
-+			u16 aid;
-+			u16 capability;
-+			int flags;
-+			u32 sta_set;
-+			u8 tx_supp_rates[16];
-+			u32 tx_supp_rates_len;
-+			struct rtw_ieee80211_ht_cap ht_cap;
-+			u64	rx_pkts;
-+			u64	rx_bytes;
-+			u64	rx_drops;
-+			u64	tx_pkts;
-+			u64	tx_bytes;
-+			u64	tx_drops;
-+		} get_sta;
-+#endif
-+		psta_data->aid = (u16)psta->cmn.aid;
-+		psta_data->capability = psta->capability;
-+		psta_data->flags = psta->flags;
-+
-+		/*
-+				nonerp_set : BIT(0)
-+				no_short_slot_time_set : BIT(1)
-+				no_short_preamble_set : BIT(2)
-+				no_ht_gf_set : BIT(3)
-+				no_ht_set : BIT(4)
-+				ht_20mhz_set : BIT(5)
-+		*/
-+
-+		psta_data->sta_set = ((psta->nonerp_set) |
-+				      (psta->no_short_slot_time_set << 1) |
-+				      (psta->no_short_preamble_set << 2) |
-+				      (psta->no_ht_gf_set << 3) |
-+				      (psta->no_ht_set << 4) |
-+				      (psta->ht_20mhz_set << 5));
-+
-+		psta_data->tx_supp_rates_len =  psta->bssratelen;
-+		_rtw_memcpy(psta_data->tx_supp_rates, psta->bssrateset, psta->bssratelen);
-+#ifdef CONFIG_80211N_HT
-+		if(padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode))
-+			_rtw_memcpy(&psta_data->ht_cap, &psta->htpriv.ht_cap, sizeof(struct rtw_ieee80211_ht_cap));
-+#endif /* CONFIG_80211N_HT */
-+		psta_data->rx_pkts = psta->sta_stats.rx_data_pkts;
-+		psta_data->rx_bytes = psta->sta_stats.rx_bytes;
-+		psta_data->rx_drops = psta->sta_stats.rx_drops;
-+
-+		psta_data->tx_pkts = psta->sta_stats.tx_pkts;
-+		psta_data->tx_bytes = psta->sta_stats.tx_bytes;
-+		psta_data->tx_drops = psta->sta_stats.tx_drops;
-+
-+
-+	} else
-+		ret = -1;
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param)
-+{
-+	int ret = 0;
-+	struct sta_info *psta = NULL;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+	RTW_INFO("rtw_get_sta_wpaie, sta_addr: " MAC_FMT "\n", MAC_ARG(param->sta_addr));
-+
-+	if (check_fwstate(pmlmepriv, (WIFI_ASOC_STATE | WIFI_AP_STATE)) != _TRUE)
-+		return -EINVAL;
-+
-+	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
-+	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
-+	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
-+		return -EINVAL;
-+
-+	psta = rtw_get_stainfo(pstapriv, param->sta_addr);
-+	if (psta) {
-+		if ((psta->wpa_ie[0] == WLAN_EID_RSN) || (psta->wpa_ie[0] == WLAN_EID_GENERIC)) {
-+			int wpa_ie_len;
-+			int copy_len;
-+
-+			wpa_ie_len = psta->wpa_ie[1];
-+
-+			copy_len = ((wpa_ie_len + 2) > sizeof(psta->wpa_ie)) ? (sizeof(psta->wpa_ie)) : (wpa_ie_len + 2);
-+
-+			param->u.wpa_ie.len = copy_len;
-+
-+			_rtw_memcpy(param->u.wpa_ie.reserved, psta->wpa_ie, copy_len);
-+		} else {
-+			/* ret = -1; */
-+			RTW_INFO("sta's wpa_ie is NONE\n");
-+		}
-+	} else
-+		ret = -1;
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, int len)
-+{
-+	int ret = 0;
-+	unsigned char wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
-+	int ie_len;
-+
-+	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
-+		return -EINVAL;
-+
-+	ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */
-+
-+
-+	if (pmlmepriv->wps_beacon_ie) {
-+		rtw_mfree(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len);
-+		pmlmepriv->wps_beacon_ie = NULL;
-+	}
-+
-+	if (ie_len > 0) {
-+		pmlmepriv->wps_beacon_ie = rtw_malloc(ie_len);
-+		pmlmepriv->wps_beacon_ie_len = ie_len;
-+		if (pmlmepriv->wps_beacon_ie == NULL) {
-+			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
-+			return -EINVAL;
-+		}
-+
-+		_rtw_memcpy(pmlmepriv->wps_beacon_ie, param->u.bcn_ie.buf, ie_len);
-+
-+		update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE, 0);
-+
-+		pmlmeext->bstart_bss = _TRUE;
-+
-+	}
-+
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *param, int len)
-+{
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	int ie_len;
-+
-+	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
-+		return -EINVAL;
-+
-+	ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */
-+
-+
-+	if (pmlmepriv->wps_probe_resp_ie) {
-+		rtw_mfree(pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len);
-+		pmlmepriv->wps_probe_resp_ie = NULL;
-+	}
-+
-+	if (ie_len > 0) {
-+		pmlmepriv->wps_probe_resp_ie = rtw_malloc(ie_len);
-+		pmlmepriv->wps_probe_resp_ie_len = ie_len;
-+		if (pmlmepriv->wps_probe_resp_ie == NULL) {
-+			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
-+			return -EINVAL;
-+		}
-+		_rtw_memcpy(pmlmepriv->wps_probe_resp_ie, param->u.bcn_ie.buf, ie_len);
-+	}
-+
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *param, int len)
-+{
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	int ie_len;
-+
-+	RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
-+		return -EINVAL;
-+
-+	ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */
-+
-+
-+	if (pmlmepriv->wps_assoc_resp_ie) {
-+		rtw_mfree(pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len);
-+		pmlmepriv->wps_assoc_resp_ie = NULL;
-+	}
-+
-+	if (ie_len > 0) {
-+		pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len);
-+		pmlmepriv->wps_assoc_resp_ie_len = ie_len;
-+		if (pmlmepriv->wps_assoc_resp_ie == NULL) {
-+			RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
-+			return -EINVAL;
-+		}
-+
-+		_rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, param->u.bcn_ie.buf, ie_len);
-+	}
-+
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, int len)
-+{
-+	int ret = 0;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *mlmepriv = &(adapter->mlmepriv);
-+	struct mlme_ext_priv	*mlmeext = &(adapter->mlmeextpriv);
-+	struct mlme_ext_info	*mlmeinfo = &(mlmeext->mlmext_info);
-+	int ie_len;
-+	u8 *ssid_ie;
-+	char ssid[NDIS_802_11_LENGTH_SSID + 1];
-+	sint ssid_len = 0;
-+	u8 ignore_broadcast_ssid;
-+
-+	if (check_fwstate(mlmepriv, WIFI_AP_STATE) != _TRUE)
-+		return -EPERM;
-+
-+	if (param->u.bcn_ie.reserved[0] != 0xea)
-+		return -EINVAL;
-+
-+	mlmeinfo->hidden_ssid_mode = ignore_broadcast_ssid = param->u.bcn_ie.reserved[1];
-+
-+	ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */
-+	ssid_ie = rtw_get_ie(param->u.bcn_ie.buf,  WLAN_EID_SSID, &ssid_len, ie_len);
-+
-+	if (ssid_ie && ssid_len > 0 && ssid_len <= NDIS_802_11_LENGTH_SSID) {
-+		WLAN_BSSID_EX *pbss_network = &mlmepriv->cur_network.network;
-+		WLAN_BSSID_EX *pbss_network_ext = &mlmeinfo->network;
-+
-+		_rtw_memcpy(ssid, ssid_ie + 2, ssid_len);
-+		ssid[ssid_len] = 0x0;
-+
-+		if (0)
-+			RTW_INFO(FUNC_ADPT_FMT" ssid:(%s,%d), from ie:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter),
-+				ssid, ssid_len,
-+				pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,
-+				pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);
-+
-+		_rtw_memcpy(pbss_network->Ssid.Ssid, (void *)ssid, ssid_len);
-+		pbss_network->Ssid.SsidLength = ssid_len;
-+		_rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)ssid, ssid_len);
-+		pbss_network_ext->Ssid.SsidLength = ssid_len;
-+
-+		if (0)
-+			RTW_INFO(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter),
-+				pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength,
-+				pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength);
-+	}
-+
-+	RTW_INFO(FUNC_ADPT_FMT" ignore_broadcast_ssid:%d, %s,%d\n", FUNC_ADPT_ARG(adapter),
-+		ignore_broadcast_ssid, ssid, ssid_len);
-+
-+	return ret;
-+}
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *param, int len)
-+{
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
-+		return -EINVAL;
-+
-+	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
-+	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
-+	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
-+		return -EINVAL;
-+
-+	ret = rtw_acl_remove_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr);
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *param, int len)
-+{
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
-+		return -EINVAL;
-+
-+	if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff &&
-+	    param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff &&
-+	    param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff)
-+		return -EINVAL;
-+
-+	ret = rtw_acl_add_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr);
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param *param, int len)
-+{
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
-+		return -EINVAL;
-+
-+	rtw_set_macaddr_acl(padapter, RTW_ACL_PERIOD_BSS, param->u.mlme.command);
-+
-+	return ret;
-+}
-+#endif /* CONFIG_RTW_MACADDR_ACL */
-+
-+static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p)
-+{
-+	struct ieee_param *param;
-+	int ret = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	/* RTW_INFO("%s\n", __FUNCTION__); */
-+
-+	/*
-+	* this function is expect to call in master mode, which allows no power saving
-+	* so, we just check hw_init_completed
-+	*/
-+
-+	if (!rtw_is_hw_init_completed(padapter)) {
-+		ret = -EPERM;
-+		goto out;
-+	}
-+
-+
-+	/* if (p->length < sizeof(struct ieee_param) || !p->pointer){ */
-+	if (!p->pointer) {
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
-+	param = (struct ieee_param *)rtw_malloc(p->length);
-+	if (param == NULL) {
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	if (copy_from_user(param, p->pointer, p->length)) {
-+		rtw_mfree((u8 *)param, p->length);
-+		ret = -EFAULT;
-+		goto out;
-+	}
-+
-+	/* RTW_INFO("%s, cmd=%d\n", __FUNCTION__, param->cmd); */
-+
-+	switch (param->cmd) {
-+	case RTL871X_HOSTAPD_FLUSH:
-+
-+		ret = rtw_hostapd_sta_flush(dev);
-+
-+		break;
-+
-+	case RTL871X_HOSTAPD_ADD_STA:
-+
-+		ret = rtw_add_sta(dev, param);
-+
-+		break;
-+
-+	case RTL871X_HOSTAPD_REMOVE_STA:
-+
-+		ret = rtw_del_sta(dev, param);
-+
-+		break;
-+
-+	case RTL871X_HOSTAPD_SET_BEACON:
-+
-+		ret = rtw_set_beacon(dev, param, p->length);
-+
-+		break;
-+
-+	case RTL871X_SET_ENCRYPTION:
-+
-+		ret = rtw_set_encryption(dev, param, p->length);
-+
-+		break;
-+
-+	case RTL871X_HOSTAPD_GET_WPAIE_STA:
-+
-+		ret = rtw_get_sta_wpaie(dev, param);
-+
-+		break;
-+
-+	case RTL871X_HOSTAPD_SET_WPS_BEACON:
-+
-+		ret = rtw_set_wps_beacon(dev, param, p->length);
-+
-+		break;
-+
-+	case RTL871X_HOSTAPD_SET_WPS_PROBE_RESP:
-+
-+		ret = rtw_set_wps_probe_resp(dev, param, p->length);
-+
-+		break;
-+
-+	case RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP:
-+
-+		ret = rtw_set_wps_assoc_resp(dev, param, p->length);
-+
-+		break;
-+
-+	case RTL871X_HOSTAPD_SET_HIDDEN_SSID:
-+
-+		ret = rtw_set_hidden_ssid(dev, param, p->length);
-+
-+		break;
-+
-+	case RTL871X_HOSTAPD_GET_INFO_STA:
-+
-+		ret = rtw_ioctl_get_sta_data(dev, param, p->length);
-+
-+		break;
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+	case RTL871X_HOSTAPD_SET_MACADDR_ACL:
-+		ret = rtw_ioctl_set_macaddr_acl(dev, param, p->length);
-+		break;
-+	case RTL871X_HOSTAPD_ACL_ADD_STA:
-+		ret = rtw_ioctl_acl_add_sta(dev, param, p->length);
-+		break;
-+	case RTL871X_HOSTAPD_ACL_REMOVE_STA:
-+		ret = rtw_ioctl_acl_remove_sta(dev, param, p->length);
-+		break;
-+#endif /* CONFIG_RTW_MACADDR_ACL */
-+
-+	default:
-+		RTW_INFO("Unknown hostapd request: %d\n", param->cmd);
-+		ret = -EOPNOTSUPP;
-+		break;
-+
-+	}
-+
-+	if (ret == 0 && copy_to_user(p->pointer, param, p->length))
-+		ret = -EFAULT;
-+
-+
-+	rtw_mfree((u8 *)param, p->length);
-+
-+out:
-+
-+	return ret;
-+
-+}
-+#endif	/*	CONFIG_AP_MODE	*/
-+
-+static int rtw_wx_set_priv(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *awrq,
-+			   char *extra)
-+{
-+
-+#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
-+	char *ext_dbg;
-+#endif
-+
-+	int ret = 0;
-+	int len = 0;
-+	char *ext;
-+#ifdef CONFIG_RTW_ANDROID
-+	int i;
-+#endif
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct iw_point *dwrq = (struct iw_point *)awrq;
-+
-+	if (dwrq->length == 0)
-+		return -EFAULT;
-+
-+	len = dwrq->length;
-+	ext = rtw_vmalloc(len);
-+	if (!ext)
-+		return -ENOMEM;
-+
-+	if (copy_from_user(ext, dwrq->pointer, len)) {
-+		rtw_vmfree(ext, len);
-+		return -EFAULT;
-+	}
-+
-+
-+
-+#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
-+	ext_dbg = rtw_vmalloc(len);
-+	if (!ext_dbg) {
-+		rtw_vmfree(ext, len);
-+		return -ENOMEM;
-+	}
-+
-+	_rtw_memcpy(ext_dbg, ext, len);
-+#endif
-+
-+	/* added for wps2.0 @20110524 */
-+	if (dwrq->flags == 0x8766 && len > 8) {
-+		u32 cp_sz;
-+		struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+		u8 *probereq_wpsie = ext;
-+		int probereq_wpsie_len = len;
-+		u8 wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};
-+
-+		if ((_VENDOR_SPECIFIC_IE_ == probereq_wpsie[0]) &&
-+		    (_rtw_memcmp(&probereq_wpsie[2], wps_oui, 4) == _TRUE)) {
-+			cp_sz = probereq_wpsie_len > MAX_WPS_IE_LEN ? MAX_WPS_IE_LEN : probereq_wpsie_len;
-+
-+			if (pmlmepriv->wps_probe_req_ie) {
-+				u32 free_len = pmlmepriv->wps_probe_req_ie_len;
-+				pmlmepriv->wps_probe_req_ie_len = 0;
-+				rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len);
-+				pmlmepriv->wps_probe_req_ie = NULL;
-+			}
-+
-+			pmlmepriv->wps_probe_req_ie = rtw_malloc(cp_sz);
-+			if (pmlmepriv->wps_probe_req_ie == NULL) {
-+				printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__);
-+				ret =  -EINVAL;
-+				goto FREE_EXT;
-+
-+			}
-+
-+			_rtw_memcpy(pmlmepriv->wps_probe_req_ie, probereq_wpsie, cp_sz);
-+			pmlmepriv->wps_probe_req_ie_len = cp_sz;
-+
-+		}
-+
-+		goto FREE_EXT;
-+
-+	}
-+
-+	if (len >= WEXT_CSCAN_HEADER_SIZE
-+		&& _rtw_memcmp(ext, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE
-+	) {
-+		ret = rtw_wx_set_scan(dev, info, awrq, ext);
-+		goto FREE_EXT;
-+	}
-+
-+#ifdef CONFIG_RTW_ANDROID
-+	/* RTW_INFO("rtw_wx_set_priv: %s req=%s\n", dev->name, ext); */
-+
-+	i = rtw_android_cmdstr_to_num(ext);
-+
-+	switch (i) {
-+	case ANDROID_WIFI_CMD_START:
-+		indicate_wx_custom_event(padapter, "START");
-+		break;
-+	case ANDROID_WIFI_CMD_STOP:
-+		indicate_wx_custom_event(padapter, "STOP");
-+		break;
-+	case ANDROID_WIFI_CMD_RSSI: {
-+		struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+		struct	wlan_network	*pcur_network = &pmlmepriv->cur_network;
-+
-+		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE)
-+			sprintf(ext, "%s rssi %d", pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi);
-+		else
-+			sprintf(ext, "OK");
-+	}
-+		break;
-+	case ANDROID_WIFI_CMD_LINKSPEED: {
-+		u16 mbps = rtw_get_cur_max_rate(padapter) / 10;
-+		sprintf(ext, "LINKSPEED %d", mbps);
-+	}
-+		break;
-+	case ANDROID_WIFI_CMD_MACADDR:
-+		sprintf(ext, "MACADDR = " MAC_FMT, MAC_ARG(dev->dev_addr));
-+		break;
-+	case ANDROID_WIFI_CMD_SCAN_ACTIVE: {
-+		/* rtw_set_scan_mode(padapter, SCAN_ACTIVE); */
-+		sprintf(ext, "OK");
-+	}
-+		break;
-+	case ANDROID_WIFI_CMD_SCAN_PASSIVE: {
-+		/* rtw_set_scan_mode(padapter, SCAN_PASSIVE); */
-+		sprintf(ext, "OK");
-+	}
-+		break;
-+
-+	case ANDROID_WIFI_CMD_COUNTRY: {
-+		char country_code[10];
-+		sscanf(ext, "%*s %s", country_code);
-+		rtw_set_country(padapter, country_code);
-+		sprintf(ext, "OK");
-+	}
-+		break;
-+	default:
-+		#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
-+		RTW_INFO("%s: %s unknowned req=%s\n", __FUNCTION__,
-+			dev->name, ext_dbg);
-+		#endif
-+
-+		sprintf(ext, "OK");
-+
-+	}
-+
-+	if (copy_to_user(dwrq->pointer, ext, min(dwrq->length, (u16)(strlen(ext) + 1))))
-+		ret = -EFAULT;
-+
-+#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
-+	RTW_INFO("%s: %s req=%s rep=%s dwrq->length=%d, strlen(ext)+1=%d\n", __FUNCTION__,
-+		dev->name, ext_dbg , ext, dwrq->length, (u16)(strlen(ext) + 1));
-+#endif
-+#endif /* end of CONFIG_ANDROID */
-+
-+
-+FREE_EXT:
-+
-+	rtw_vmfree(ext, len);
-+	#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV
-+	rtw_vmfree(ext_dbg, len);
-+	#endif
-+
-+	/* RTW_INFO("rtw_wx_set_priv: (SIOCSIWPRIV) %s ret=%d\n",  */
-+	/*		dev->name, ret); */
-+
-+	return ret;
-+
-+}
-+#endif	/*CONFIG_IOCTL_WEXT*/
-+
-+#ifdef CONFIG_WOWLAN
-+static int rtw_wowlan_ctrl(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wowlan_ioctl_param poidparam;
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	int ret = 0;
-+	systime start_time = rtw_get_current_time();
-+	poidparam.subcode = 0;
-+
-+	RTW_INFO("+rtw_wowlan_ctrl: %s\n", extra);
-+
-+	if (!check_fwstate(pmlmepriv, WIFI_ASOC_STATE) &&
-+		check_fwstate(pmlmepriv, WIFI_STATION_STATE) &&
-+		!WOWLAN_IS_STA_MIX_MODE(padapter)) {
-+#ifdef CONFIG_PNO_SUPPORT
-+		pwrctrlpriv->wowlan_pno_enable = _TRUE;
-+#else
-+		RTW_INFO("[%s] WARNING: Please Connect With AP First!!\n", __func__);
-+		goto _rtw_wowlan_ctrl_exit_free;
-+#endif /* CONFIG_PNO_SUPPORT */
-+	}
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY))
-+		rtw_scan_abort(padapter);
-+
-+	if (_rtw_memcmp(extra, "enable", 6))
-+
-+
-+		rtw_suspend_common(padapter);
-+
-+	else if (_rtw_memcmp(extra, "disable", 7)) {
-+#ifdef CONFIG_USB_HCI
-+		RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
-+		RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
-+#endif
-+		rtw_resume_common(padapter);
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+		pwrctrlpriv->wowlan_pno_enable = _FALSE;
-+#endif /* CONFIG_PNO_SUPPORT */
-+
-+	} else {
-+		RTW_INFO("[%s] Invalid Parameter.\n", __func__);
-+		goto _rtw_wowlan_ctrl_exit_free;
-+	}
-+	/* mutex_lock(&ioctl_mutex); */
-+_rtw_wowlan_ctrl_exit_free:
-+	RTW_INFO("-rtw_wowlan_ctrl( subcode = %d)\n", poidparam.subcode);
-+	RTW_PRINT("%s in %d ms\n", __func__,
-+		  rtw_get_passing_time_ms(start_time));
-+	return ret;
-+}
-+
-+/*
-+ * IP filter This pattern if for a frame containing a ip packet:
-+ * AA:AA:AA:AA:AA:AA:BB:BB:BB:BB:BB:BB:CC:CC:DD:-:-:-:-:-:-:-:-:EE:-:-:FF:FF:FF:FF:GG:GG:GG:GG:HH:HH:II:II
-+ *
-+ * A: Ethernet destination address
-+ * B: Ethernet source address
-+ * C: Ethernet protocol type
-+ * D: IP header VER+Hlen, use: 0x45 (4 is for ver 4, 5 is for len 20)
-+ * E: IP protocol
-+ * F: IP source address ( 192.168.0.4: C0:A8:00:2C )
-+ * G: IP destination address ( 192.168.0.4: C0:A8:00:2C )
-+ * H: Source port (1024: 04:00)
-+ * I: Destination port (1024: 04:00)
-+ */
-+
-+static int rtw_wowlan_set_pattern(struct net_device *dev,
-+				  struct iw_request_info *info,
-+				  union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct wowlan_ioctl_param poidparam;
-+	int ret = 0;
-+	u8 input[MAX_IN_PATTERN_SIZE];
-+	u8 index = 0;
-+
-+	poidparam.subcode = 0;
-+
-+	if (!check_fwstate(pmlmepriv, WIFI_ASOC_STATE) &&
-+	    check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
-+		ret = -EFAULT;
-+		RTW_INFO("Please Connect With AP First!!\n");
-+		goto _rtw_wowlan_set_pattern_exit;
-+	}
-+
-+	if ((wrqu->data.length <= 0) || (wrqu->data.length > MAX_IN_PATTERN_SIZE)) {
-+		ret = -EFAULT;
-+		RTW_INFO("ERROR: parameter length error, len=%d\n", wrqu->data.length);
-+		goto _rtw_wowlan_set_pattern_exit;
-+	} else {
-+		/* set pattern */
-+		if (copy_from_user(input,
-+				   wrqu->data.pointer, wrqu->data.length))
-+			return -EFAULT;
-+		/* leave PS first */
-+		rtw_ps_deny(padapter, PS_DENY_IOCTL);
-+		LeaveAllPowerSaveModeDirect(padapter);
-+		if ((strncmp(input, "pattern=", 8) == 0) ||(strncmp(input, "ack_pattern=", 12) == 0)) {
-+			if (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_CAM_NUM) {
-+				RTW_INFO("WARNING: priv-pattern is full(idx: %d)\n",
-+					 pwrpriv->wowlan_pattern_idx);
-+				RTW_INFO("WARNING: please clean priv-pattern first\n");
-+				ret = -EINVAL;
-+				goto _rtw_wowlan_set_pattern_exit;
-+			} else {
-+				index = pwrpriv->wowlan_pattern_idx;
-+				ret = rtw_wowlan_parser_pattern_cmd(input,
-+					    pwrpriv->patterns[index].content,
-+					    &pwrpriv->patterns[index].len,
-+					    pwrpriv->patterns[index].mask);
-+
-+				if (ret == _TRUE) {
-+					#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+					if(strncmp(input, "ack_pattern=", 12) == 0)
-+						pwrpriv->wowlan_keep_alive_ack_index = index;
-+					else
-+						pwrpriv->wowlan_wake_pattern_index = index;
-+					RTW_INFO("pwrpriv->wowlan_keep_alive_ack_index =%d\n",pwrpriv->wowlan_keep_alive_ack_index);
-+					RTW_INFO("pwrpriv->wowlan_wake_pattern_index =%d\n",pwrpriv->wowlan_wake_pattern_index);
-+					#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+					pwrpriv->wowlan_pattern_idx++;
-+				}
-+			}
-+		} else if (strncmp(input, "clean", 5) == 0) {
-+			poidparam.subcode = WOWLAN_PATTERN_CLEAN;
-+			#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+			pwrpriv->wowlan_wake_pattern_index = 0xFF;
-+			pwrpriv->wowlan_keep_alive_ack_index = 0xFF;
-+			#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+
-+			rtw_hal_set_hwreg(padapter,
-+					  HW_VAR_WOWLAN, (u8 *)&poidparam);
-+		} else if (strncmp(input, "show", 4) == 0) {
-+			rtw_wow_pattern_cam_dump(padapter);
-+			rtw_wow_pattern_sw_dump(padapter);
-+		} else {
-+			RTW_INFO("ERROR: incorrect parameter!\n");
-+			ret = -EINVAL;
-+		}
-+		rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
-+	}
-+_rtw_wowlan_set_pattern_exit:
-+	return ret;
-+}
-+
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+static int rtw_wowlan_set_keep_alive_pattern(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+
-+	int ret = 0,totoal_len=0,i=0,len=0;
-+	char *cp = NULL;
-+	u32	mode = 0xFF;  /*para1*/
-+	u16 period = 15*10; /* para2;units:100ms,default 15s*/
-+	char tx_pattern[512];	   /*para3*/
-+	u32   retry_intervel = 2*10; /* para4;units:100ms,default 2s*/
-+	u32	retry_limit_count = 5; /*para5*/
-+
-+	ret = sscanf(extra, "%d %hu %s %d %d", &mode , &period, tx_pattern, &retry_intervel, &retry_limit_count);
-+	pwrpriv->wowlan_keep_alive_mode = mode;
-+
-+	RTW_INFO("[%s] ret =%d \n", __func__ ,ret);
-+	totoal_len = strlen(tx_pattern);
-+	RTW_INFO("[%s] totoal_len=%d \n", __func__ ,totoal_len);
-+
-+	 if (mode && (ret < 3))
-+                return  -EINVAL;
-+
-+	 if (((mode ==2) ||(mode ==3)) && ((retry_intervel*retry_limit_count) > period)) {
-+		RTW_INFO("[%s]  retry_intervel*retry_limit_count need smaller than period\n", __func__ );
-+		return  -EINVAL;
-+	 }
-+
-+	switch(mode){
-+		case wow_keep_alive_pattern_disable:
-+			/*disable this feature*/
-+			pwrpriv->keep_alive_pattern_loc = 0;
-+			pwrpriv->keep_alive_pattern_len = 0;
-+			pwrpriv->wowlan_keep_alive_period = 0;
-+			pwrpriv->wowlan_keep_alive_ack_index = 0xFF;
-+			pwrpriv->wowlan_wake_pattern_index = 0xFF;
-+			pwrpriv->wowlan_keep_alive_retry_interval = 0;
-+			pwrpriv->wowlan_keep_alive_retry_counter = 0;
-+			_rtw_memset(pwrpriv->keep_alive_pattern,0,WLAN_MAX_KEEP_ALIVE_IE_LEN);
-+			RTW_INFO("[%s] clear pattern \n", __func__ );
-+			ret = _SUCCESS;
-+			break;
-+		case wow_keep_alive_pattern_tx:
-+			/*only tx udp packet*/
-+			pwrpriv->wowlan_keep_alive_period = period;
-+			pwrpriv->wowlan_keep_alive_retry_interval = 0;
-+			pwrpriv->wowlan_keep_alive_retry_counter = 0;
-+			RTW_INFO("[%s] wow_keep_alive_pattern_tx \n", __func__ );
-+			break;
-+		case wow_keep_alive_pattern_trx:
-+			/*trx+no need wakeup*/
-+			pwrpriv->wowlan_keep_alive_period = period;
-+			pwrpriv->wowlan_keep_alive_retry_interval = retry_intervel;
-+			pwrpriv->wowlan_keep_alive_retry_counter = retry_limit_count;
-+			RTW_INFO("[%s] wow_keep_alive_pattern_trx \n", __func__ );
-+			break;
-+		case wow_keep_alive_pattern_trx_with_ack:
-+			/*trx+need wakeup*/
-+			pwrpriv->wowlan_keep_alive_period = period;
-+			pwrpriv->wowlan_keep_alive_retry_interval = retry_intervel;
-+			pwrpriv->wowlan_keep_alive_retry_counter = retry_limit_count;
-+			RTW_INFO("[%s] wow_keep_alive_pattern_trx_with_ack \n", __func__ );
-+			break;
-+		default:
-+			RTW_INFO("[%s] please setting valid mode \n", __func__ );
-+			ret = -EINVAL;
-+			break;
-+
-+	}
-+
-+	if((mode == 0) || (mode > 4))
-+		return ret;
-+
-+	totoal_len = strlen(tx_pattern);
-+	RTW_INFO("[%s] totoal_len=%d \n", __func__ ,totoal_len);
-+	if (totoal_len > WLAN_MAX_KEEP_ALIVE_IE_LEN*2) {
-+		RTW_INFO("[%s] Fail , not support ie length extend %d\n", __func__ , WLAN_MAX_KEEP_ALIVE_IE_LEN);
-+		return -EFAULT;
-+	}
-+	RTW_INFO("[%s] period = %hu ,ie = %s , len = %d\n", __func__ , period , tx_pattern  , totoal_len);
-+
-+
-+	if (totoal_len > 0) {
-+		RTW_INFO("[%s] pwrpriv->keep_alive_pattern==========> \n", __func__ );
-+		for (i = 0  ; i <totoal_len ; i += 2) {
-+			pwrpriv->keep_alive_pattern[len] = key_2char2num(tx_pattern[i], tx_pattern[i + 1]);
-+			RTW_INFO("[0x%x] ",pwrpriv->keep_alive_pattern[len]);
-+			len++;
-+		}
-+		RTW_INFO(" \n" );
-+		pwrpriv->keep_alive_pattern_len = len;
-+	}
-+
-+	return ret;
-+}
-+#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+
-+#endif /* CONFIG_WOWLAN */
-+
-+#ifdef CONFIG_AP_WOWLAN
-+static int rtw_ap_wowlan_ctrl(struct net_device *dev,
-+			      struct iw_request_info *info,
-+			      union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct wowlan_ioctl_param poidparam;
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct sta_info	*psta = NULL;
-+	int ret = 0;
-+	systime start_time = rtw_get_current_time();
-+	poidparam.subcode = 0;
-+
-+	RTW_INFO("+rtw_ap_wowlan_ctrl: %s\n", extra);
-+
-+	if (!check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
-+		RTW_INFO("[%s] It is not AP mode!!\n", __func__);
-+		goto _rtw_ap_wowlan_ctrl_exit_free;
-+	}
-+
-+	if (_rtw_memcmp(extra, "enable", 6)) {
-+
-+		pwrctrlpriv->wowlan_ap_mode = _TRUE;
-+
-+		rtw_suspend_common(padapter);
-+	} else if (_rtw_memcmp(extra, "disable", 7)) {
-+#ifdef CONFIG_USB_HCI
-+		RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
-+		RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
-+#endif
-+		rtw_resume_common(padapter);
-+	} else {
-+		RTW_INFO("[%s] Invalid Parameter.\n", __func__);
-+		goto _rtw_ap_wowlan_ctrl_exit_free;
-+	}
-+	/* mutex_lock(&ioctl_mutex); */
-+_rtw_ap_wowlan_ctrl_exit_free:
-+	RTW_INFO("-rtw_ap_wowlan_ctrl( subcode = %d)\n", poidparam.subcode);
-+	RTW_PRINT("%s in %d ms\n", __func__,
-+		  rtw_get_passing_time_ms(start_time));
-+_rtw_ap_wowlan_ctrl_exit:
-+	return ret;
-+}
-+#endif /* CONFIG_AP_WOWLAN */
-+
-+static int rtw_pm_set(struct net_device *dev,
-+		      struct iw_request_info *info,
-+		      union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+	unsigned	mode = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra);
-+
-+	if (_rtw_memcmp(extra, "lps=", 4)) {
-+		sscanf(extra + 4, "%u", &mode);
-+		ret = rtw_pm_set_lps(padapter, mode);
-+	} else if (_rtw_memcmp(extra, "ips=", 4)) {
-+		sscanf(extra + 4, "%u", &mode);
-+		ret = rtw_pm_set_ips(padapter, mode);
-+	} else if (_rtw_memcmp(extra, "lps_level=", 10)) {
-+		if (sscanf(extra + 10, "%u", &mode) > 0)
-+			ret = rtw_pm_set_lps_level(padapter, mode);
-+#ifdef CONFIG_LPS_1T1R
-+	} else if (_rtw_memcmp(extra, "lps_1t1r=", 9)) {
-+		if (sscanf(extra + 9, "%u", &mode) > 0)
-+			ret = rtw_pm_set_lps_1t1r(padapter, mode);
-+#endif
-+	}
-+#ifdef CONFIG_WOWLAN
-+	else if (_rtw_memcmp(extra, "wow_lps=", 8)) {
-+		sscanf(extra + 8, "%u", &mode);
-+		ret = rtw_pm_set_wow_lps(padapter, mode);
-+	} else if (_rtw_memcmp(extra, "wow_lps_level=", 14)) {
-+		if (sscanf(extra + 14, "%u", &mode) > 0)
-+			ret = rtw_pm_set_wow_lps_level(padapter, mode);
-+	#ifdef CONFIG_LPS_1T1R
-+	} else if (_rtw_memcmp(extra, "wow_lps_1t1r=", 13)) {
-+		if (sscanf(extra + 13, "%u", &mode) > 0)
-+			ret = rtw_pm_set_wow_lps_1t1r(padapter, mode);
-+	#endif
-+	}
-+#endif /* CONFIG_WOWLAN */
-+	else
-+		ret = -EINVAL;
-+
-+	return ret;
-+}
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+
-+int rtw_vendor_ie_get_raw_data(struct net_device *dev, u32 vendor_ie_num,
-+							   char *extra, u32 length)
-+{
-+	int j;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	u32 vendor_ie_mask = 0;
-+	char *pstring;
-+
-+	if (vendor_ie_num >= WLAN_MAX_VENDOR_IE_NUM) {
-+		RTW_INFO("[%s] only support %d vendor ie\n", __func__ ,
-+				 WLAN_MAX_VENDOR_IE_NUM);
-+		return -EFAULT;
-+	}
-+
-+	if (pmlmepriv->vendor_ielen[vendor_ie_num] == 0) {
-+		RTW_INFO("[%s]  Fail, vendor_ie_num: %d is not set\n", __func__,
-+				 vendor_ie_num);
-+		return -EFAULT;
-+	}
-+
-+	if (length < 2 * pmlmepriv->vendor_ielen[vendor_ie_num] + 5) {
-+		RTW_INFO("[%s]  Fail, buffer size is too small\n", __func__);
-+		return -EFAULT;
-+	}
-+
-+	vendor_ie_mask = pmlmepriv->vendor_ie_mask[vendor_ie_num];
-+	_rtw_memset(extra, 0, length);
-+
-+	pstring = extra;
-+	pstring += sprintf(pstring, "%d,%x,", vendor_ie_num, vendor_ie_mask);
-+
-+	for (j = 0; j < pmlmepriv->vendor_ielen[vendor_ie_num]; j++)
-+		pstring += sprintf(pstring, "%02x", pmlmepriv->vendor_ie[vendor_ie_num][j]);
-+
-+	length = pstring - extra;
-+	return length;
-+}
-+
-+int rtw_vendor_ie_get_data(struct net_device *dev, int vendor_ie_num, char *extra)
-+{
-+	int j;
-+	char *pstring;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	u32 vendor_ie_mask = 0;
-+	__u16 length = 0;
-+
-+	vendor_ie_mask = pmlmepriv->vendor_ie_mask[vendor_ie_num];
-+	pstring = extra;
-+	pstring += sprintf(pstring , "\nVendor IE num %d , Mask:%x " , vendor_ie_num , vendor_ie_mask);
-+
-+	if (vendor_ie_mask & WIFI_BEACON_VENDOR_IE_BIT)
-+		pstring += sprintf(pstring , "[Beacon]");
-+	if (vendor_ie_mask & WIFI_PROBEREQ_VENDOR_IE_BIT)
-+		pstring += sprintf(pstring , "[Probe Req]");
-+	if (vendor_ie_mask & WIFI_PROBERESP_VENDOR_IE_BIT)
-+		pstring += sprintf(pstring , "[Probe Resp]");
-+	if (vendor_ie_mask & WIFI_ASSOCREQ_VENDOR_IE_BIT)
-+		pstring += sprintf(pstring , "[Assoc Req]");
-+	if (vendor_ie_mask & WIFI_ASSOCRESP_VENDOR_IE_BIT)
-+		pstring += sprintf(pstring , "[Assoc Resp]");
-+#ifdef CONFIG_P2P
-+	if (vendor_ie_mask & WIFI_P2P_PROBEREQ_VENDOR_IE_BIT)
-+		pstring += sprintf(pstring , "[P2P_Probe Req]");
-+	if (vendor_ie_mask & WIFI_P2P_PROBERESP_VENDOR_IE_BIT)
-+		pstring += sprintf(pstring , "[P2P_Probe Resp]");
-+#endif
-+
-+	pstring += sprintf(pstring , "\nVendor IE:\n");
-+	for (j = 0 ; j < pmlmepriv->vendor_ielen[vendor_ie_num]  ; j++)
-+		pstring += sprintf(pstring , "%02x" , pmlmepriv->vendor_ie[vendor_ie_num][j]);
-+
-+	length = pstring - extra;
-+	return length;
-+
-+}
-+
-+int rtw_vendor_ie_get(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0, vendor_ie_num = 0, cmdlen;
-+	struct iw_point *p;
-+	u8 *ptmp;
-+
-+	p = &wrqu->data;
-+	cmdlen = p->length;
-+	if (0 == cmdlen)
-+		return -EINVAL;
-+
-+	ptmp = (u8 *)rtw_malloc(cmdlen);
-+	if (NULL == ptmp)
-+		return -ENOMEM;
-+
-+	if (copy_from_user(ptmp, p->pointer, cmdlen)) {
-+		ret = -EFAULT;
-+		goto exit;
-+	}
-+	ret = sscanf(ptmp , "%d", &vendor_ie_num);
-+	if (vendor_ie_num > WLAN_MAX_VENDOR_IE_NUM - 1) {
-+		ret = -EFAULT;
-+		goto exit;
-+	}
-+
-+	wrqu->data.length = rtw_vendor_ie_get_data(dev, vendor_ie_num, extra);
-+
-+exit:
-+	rtw_mfree(ptmp, cmdlen);
-+
-+	return 0;
-+}
-+
-+int rtw_vendor_ie_set(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0, i , len = 0 , totoal_ie_len = 0 , total_ie_len_byte = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
-+	u32 vendor_ie_mask = 0;
-+	u32 vendor_ie_num = 0;
-+	u32 vendor_ie_mask_max = BIT(WLAN_MAX_VENDOR_IE_MASK_MAX) - 1;
-+	u32 id, elen;
-+
-+	ret = sscanf(extra, "%d,%x,%*s", &vendor_ie_num , &vendor_ie_mask);
-+	if (strrchr(extra , ','))
-+		extra = strrchr(extra , ',') + 1;
-+	else
-+		return -EINVAL;
-+	totoal_ie_len = strlen(extra);
-+	RTW_INFO("[%s] vendor_ie_num = %d , vendor_ie_mask = 0x%x , vendor_ie = %s , len = %d\n", __func__ , vendor_ie_num , vendor_ie_mask , extra  , totoal_ie_len);
-+
-+	if (vendor_ie_num  > WLAN_MAX_VENDOR_IE_NUM - 1) {
-+		RTW_INFO("[%s] Fail, only support %d vendor ie\n", __func__ , WLAN_MAX_VENDOR_IE_NUM);
-+		return -EFAULT;
-+	}
-+
-+	if (totoal_ie_len > WLAN_MAX_VENDOR_IE_LEN) {
-+		RTW_INFO("[%s] Fail , not support ie length extend %d\n", __func__ , WLAN_MAX_VENDOR_IE_LEN);
-+		return -EFAULT;
-+	}
-+
-+	if (vendor_ie_mask > vendor_ie_mask_max) {
-+		RTW_INFO("[%s] Fail, not support vendor_ie_mask more than 0x%x\n", __func__ , vendor_ie_mask_max);
-+		return -EFAULT;
-+	}
-+
-+	if (vendor_ie_mask == 0) {
-+		RTW_INFO("[%s] Clear vendor_ie_num %d group\n", __func__ , vendor_ie_num);
-+		goto _clear_path;
-+	}
-+
-+	if (totoal_ie_len % 2 != 0) {
-+		RTW_INFO("[%s]  Fail , IE length = %zu is odd\n" , __func__ , strlen(extra));
-+		return -EFAULT;
-+	}
-+
-+	if (totoal_ie_len > 0) {
-+		for (i = 0  ; i < strlen(extra) ; i += 2) {
-+			pmlmepriv->vendor_ie[vendor_ie_num][len] = key_2char2num(extra[i] , extra[i + 1]);
-+			if (len == 0) {
-+				id = pmlmepriv->vendor_ie[vendor_ie_num][len];
-+				if (id != WLAN_EID_VENDOR_SPECIFIC) {
-+					RTW_INFO("[%s] Fail , VENDOR SPECIFIC IE ID \"%x\" was not correct\n", __func__ , id);
-+					goto _clear_path;
-+				}
-+			} else if (len == 1) {
-+				total_ie_len_byte = (totoal_ie_len / 2) - 2;
-+				elen = pmlmepriv->vendor_ie[vendor_ie_num][len];
-+				if (elen != total_ie_len_byte) {
-+					RTW_INFO("[%s] Fail , Input IE length = \"%d\"(hex:%x) bytes , not match input total IE context length \"%d\" bytes\n", __func__ , elen , elen ,
-+						 total_ie_len_byte);
-+					goto _clear_path;
-+				}
-+			}
-+			len++;
-+		}
-+		pmlmepriv->vendor_ielen[vendor_ie_num] = len;
-+	} else
-+		pmlmepriv->vendor_ielen[vendor_ie_num] = 0;
-+
-+
-+
-+	if (vendor_ie_mask & WIFI_BEACON_VENDOR_IE_BIT)
-+		RTW_INFO("[%s] Beacon append vendor ie\n", __func__);
-+	if (vendor_ie_mask & WIFI_PROBEREQ_VENDOR_IE_BIT)
-+		RTW_INFO("[%s] Probe Req append vendor ie\n", __func__);
-+	if (vendor_ie_mask & WIFI_PROBERESP_VENDOR_IE_BIT)
-+		RTW_INFO("[%s] Probe Resp append vendor ie\n", __func__);
-+	if (vendor_ie_mask & WIFI_ASSOCREQ_VENDOR_IE_BIT)
-+		RTW_INFO("[%s] Assoc Req append vendor ie\n", __func__);
-+	if (vendor_ie_mask & WIFI_ASSOCRESP_VENDOR_IE_BIT)
-+		RTW_INFO("[%s] Assoc Resp append vendor ie\n", __func__);
-+#ifdef CONFIG_P2P
-+	if (vendor_ie_mask & WIFI_P2P_PROBEREQ_VENDOR_IE_BIT)
-+		RTW_INFO("[%s] P2P Probe Req append vendor ie\n", __func__);
-+	if (vendor_ie_mask & WIFI_P2P_PROBERESP_VENDOR_IE_BIT)
-+		RTW_INFO("[%s] P2P Probe Resp append vendor ie\n", __func__);
-+#endif
-+
-+	pmlmepriv->vendor_ie_mask[vendor_ie_num] = vendor_ie_mask;
-+
-+	return ret;
-+
-+_clear_path:
-+	_rtw_memset(pmlmepriv->vendor_ie[vendor_ie_num] , 0 , sizeof(u32) * WLAN_MAX_VENDOR_IE_LEN);
-+	pmlmepriv->vendor_ielen[vendor_ie_num] = 0;
-+	pmlmepriv->vendor_ie_mask[vendor_ie_num] = 0;
-+	return -EFAULT;
-+}
-+#endif
-+
-+static int rtw_mp_efuse_get(struct net_device *dev,
-+			    struct iw_request_info *info,
-+			    union iwreq_data *wdata, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	PEFUSE_HAL pEfuseHal;
-+	struct iw_point *wrqu;
-+
-+	u8 ips_mode = IPS_NUM; /* init invalid value */
-+	u8 lps_mode = PS_MODE_NUM; /* init invalid value */
-+	struct pwrctrl_priv *pwrctrlpriv ;
-+	u8 *data = NULL;
-+	u8 *rawdata = NULL;
-+	char *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00};
-+	u16 i = 0, j = 0, mapLen = 0, addr = 0, cnts = 0;
-+	u16 max_available_len = 0, raw_cursize = 0, raw_maxsize = 0;
-+	u16 mask_len;
-+	u8 mask_buf[64] = "";
-+	int err;
-+	char *pextra = NULL;
-+#ifdef CONFIG_IOL
-+	u8 org_fw_iol = padapter->registrypriv.fw_iol;/* 0:Disable, 1:enable, 2:by usb speed */
-+#endif
-+
-+	wrqu = (struct iw_point *)wdata;
-+	pwrctrlpriv = adapter_to_pwrctl(padapter);
-+	pEfuseHal = &pHalData->EfuseHal;
-+
-+	err = 0;
-+	data = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN);
-+	if (data == NULL) {
-+		err = -ENOMEM;
-+		goto exit;
-+	}
-+	rawdata = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN);
-+	if (rawdata == NULL) {
-+		err = -ENOMEM;
-+		goto exit;
-+	}
-+
-+	if (copy_from_user(extra, wrqu->pointer, wrqu->length)) {
-+		err = -EFAULT;
-+		goto exit;
-+	}
-+
-+	*(extra + wrqu->length) = '\0';
-+
-+#ifdef CONFIG_LPS
-+	lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */
-+	rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
-+#endif
-+
-+#ifdef CONFIG_IPS
-+	ips_mode = pwrctrlpriv->ips_mode;/* keep org value */
-+	rtw_pm_set_ips(padapter, IPS_NONE);
-+#endif
-+
-+	pch = extra;
-+	RTW_INFO("%s: in=%s\n", __FUNCTION__, extra);
-+
-+	i = 0;
-+	/* mac 16 "00e04c871200" rmap,00,2 */
-+	while ((token = strsep(&pch, ",")) != NULL) {
-+		if (i > 2)
-+			break;
-+		tmp[i] = token;
-+		i++;
-+	}
-+#ifdef CONFIG_IOL
-+	padapter->registrypriv.fw_iol = 0;/* 0:Disable, 1:enable, 2:by usb speed */
-+#endif
-+
-+	if (strcmp(tmp[0], "status") == 0) {
-+		sprintf(extra, "Load File efuse=%s,Load File MAC=%s"
-+			, pHalData->efuse_file_status == EFUSE_FILE_FAILED ? "FAIL" : "OK"
-+			, pHalData->macaddr_file_status == MACADDR_FILE_FAILED ? "FAIL" : "OK"
-+		       );
-+		goto exit;
-+	} else if (strcmp(tmp[0], "drvmap") == 0) {
-+		static u8 drvmaporder = 0;
-+		u8 *efuse;
-+		u32 shift, cnt;
-+		u32 blksz = 0x200; /* The size of one time show, default 512 */
-+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE);
-+
-+		efuse = pHalData->efuse_eeprom_data;
-+
-+		shift = blksz * drvmaporder;
-+		efuse += shift;
-+		cnt = mapLen - shift;
-+
-+		if (cnt > blksz) {
-+			cnt = blksz;
-+			drvmaporder++;
-+		} else
-+			drvmaporder = 0;
-+
-+		sprintf(extra, "\n");
-+		for (i = 0; i < cnt; i += 16) {
-+			pextra = extra + strlen(extra);
-+			pextra += sprintf(pextra, "0x%02x\t", shift + i);
-+			for (j = 0; j < 8; j++)
-+				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
-+			pextra += sprintf(pextra, "\t");
-+			for (; j < 16; j++)
-+				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
-+			pextra += sprintf(pextra, "\n");
-+		}
-+		if ((shift + cnt) < mapLen)
-+			pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen);
-+
-+	} else if (strcmp(tmp[0], "realmap") == 0) {
-+		static u8 order = 0;
-+		u8 *efuse;
-+		u32 shift, cnt;
-+		u32 blksz = 0x200; /* The size of one time show, default 512 */
-+
-+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE);
-+		efuse = pEfuseHal->fakeEfuseInitMap;
-+		if (rtw_efuse_mask_map_read(padapter, 0, mapLen, efuse) == _FAIL) {
-+			RTW_INFO("%s: read realmap Fail!!\n", __FUNCTION__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+#if 0
-+		RTW_INFO("OFFSET\tVALUE(hex)\n");
-+		for (i = 0; i < mapLen; i += 16) {
-+			RTW_INFO("0x%02x\t", i);
-+			for (j = 0; j < 8; j++)
-+				RTW_INFO("%02X ", efuse[i + j]);
-+			RTW_INFO("\t");
-+			for (; j < 16; j++)
-+				RTW_INFO("%02X ", efuse[i + j]);
-+			RTW_INFO("\n");
-+		}
-+		RTW_INFO("\n");
-+#endif
-+
-+		shift = blksz * order;
-+		efuse += shift;
-+		cnt = mapLen - shift;
-+		if (cnt > blksz) {
-+			cnt = blksz;
-+			order++;
-+		} else
-+			order = 0;
-+
-+		sprintf(extra, "\n");
-+		for (i = 0; i < cnt; i += 16) {
-+			pextra = extra + strlen(extra);
-+			pextra += sprintf(pextra, "0x%02x\t", shift + i);
-+			for (j = 0; j < 8; j++)
-+				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
-+			pextra += sprintf(pextra, "\t");
-+			for (; j < 16; j++)
-+				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
-+			pextra += sprintf(pextra, "\n");
-+		}
-+		if ((shift + cnt) < mapLen)
-+			pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen);
-+	} else if (strcmp(tmp[0], "rmap") == 0) {
-+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
-+			RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__);
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		/* rmap addr cnts */
-+		addr = simple_strtoul(tmp[1], &ptmp, 16);
-+		RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr);
-+
-+		cnts = simple_strtoul(tmp[2], &ptmp, 10);
-+		if (cnts == 0) {
-+			RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__);
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
-+
-+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&max_available_len, _FALSE);
-+		if ((addr + cnts) > max_available_len) {
-+			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) {
-+			RTW_INFO("%s: rtw_efuse_mask_map_read error!\n", __func__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		/*		RTW_INFO("%s: data={", __FUNCTION__); */
-+		*extra = 0;
-+		pextra = extra;
-+		for (i = 0; i < cnts; i++) {
-+			/*			RTW_INFO("0x%02x ", data[i]); */
-+			pextra += sprintf(pextra, "0x%02X ", data[i]);
-+		}
-+		/*		RTW_INFO("}\n"); */
-+	} else if (strcmp(tmp[0], "realraw") == 0) {
-+		static u8 raw_order = 0;
-+		u32 shift, cnt;
-+		u32 blksz = 0x200; /* The size of one time show, default 512 */
-+
-+		addr = 0;
-+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN , (void *)&mapLen, _FALSE);
-+		RTW_INFO("Real content len = %d\n",mapLen );
-+
-+		if (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) {
-+			RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		_rtw_memset(extra, '\0', strlen(extra));
-+
-+		shift = blksz * raw_order;
-+		rawdata += shift;
-+		cnt = mapLen - shift;
-+		if (cnt > blksz) {
-+			cnt = blksz;
-+			raw_order++;
-+		} else
-+			raw_order = 0;
-+
-+		sprintf(extra, "\n");
-+		for (i = 0; i < cnt; i += 16) {
-+			pextra = extra + strlen(extra);
-+			pextra += sprintf(pextra, "0x%02x\t", shift + i);
-+			for (j = 0; j < 8; j++)
-+				pextra += sprintf(pextra, "%02X ", rawdata[i + j]);
-+			pextra += sprintf(pextra, "\t");
-+			for (; j < 16; j++)
-+				pextra += sprintf(pextra, "%02X ", rawdata[i + j]);
-+			pextra += sprintf(pextra, "\n");
-+		}
-+		if ((shift + cnt) < mapLen)
-+			pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen);
-+
-+	} else if (strcmp(tmp[0], "btrealraw") == 0) {
-+		static u8 bt_raw_order = 0;
-+		u32 shift, cnt;
-+		u32 blksz = 0x200; /* The size of one time show, default 512 */
-+
-+		addr = 0;
-+		EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_REAL_CONTENT_LEN, (void *)&mapLen, _FALSE);
-+		RTW_INFO("Real content len = %d\n", mapLen);
-+#ifdef RTW_HALMAC
-+		if (rtw_efuse_bt_access(padapter, _FALSE, 0, mapLen, rawdata) == _FAIL) {
-+			RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+#else
-+		rtw_write8(padapter, 0x35, 0x1);
-+
-+		if (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) {
-+			RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+#endif
-+		_rtw_memset(extra, '\0', strlen(extra));
-+
-+		shift = blksz * bt_raw_order;
-+		rawdata += shift;
-+		cnt = mapLen - shift;
-+		if (cnt > blksz) {
-+			cnt = blksz;
-+			bt_raw_order++;
-+		} else
-+			bt_raw_order = 0;
-+
-+		sprintf(extra, "\n");
-+		for (i = 0; i < cnt; i += 16) {
-+			pextra = extra + strlen(extra);
-+			pextra += sprintf(pextra, "0x%02x\t", shift + i);
-+			for (j = 0; j < 8; j++)
-+				pextra += sprintf(pextra, "%02X ", rawdata[i + j]);
-+			pextra += sprintf(pextra, "\t");
-+			for (; j < 16; j++)
-+				pextra += sprintf(pextra, "%02X ", rawdata[i + j]);
-+			pextra += sprintf(pextra, "\n");
-+		}
-+		if ((shift + cnt) < mapLen)
-+			pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen);
-+
-+	} else if (strcmp(tmp[0], "mac") == 0) {
-+		if (hal_efuse_macaddr_offset(padapter) == -1) {
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		addr = hal_efuse_macaddr_offset(padapter);
-+		cnts = 6;
-+
-+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);
-+		if ((addr + cnts) > max_available_len) {
-+			RTW_INFO("%s: addr(0x%02x)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) {
-+			RTW_INFO("%s: rtw_efuse_mask_map_read error!\n", __func__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		/*		RTW_INFO("%s: MAC address={", __FUNCTION__); */
-+		*extra = 0;
-+		pextra = extra;
-+		for (i = 0; i < cnts; i++) {
-+			/*			RTW_INFO("%02X", data[i]); */
-+			pextra += sprintf(pextra, "%02X", data[i]);
-+			if (i != (cnts - 1)) {
-+				/*				RTW_INFO(":"); */
-+				pextra += sprintf(pextra, ":");
-+			}
-+		}
-+		/*		RTW_INFO("}\n"); */
-+	} else if (strcmp(tmp[0], "vidpid") == 0) {
-+#ifdef CONFIG_RTL8188E
-+#ifdef CONFIG_USB_HCI
-+		addr = EEPROM_VID_88EU;
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+		addr = EEPROM_VID_88EE;
-+#endif
-+#endif /* CONFIG_RTL8188E */
-+
-+#ifdef CONFIG_RTL8192E
-+#ifdef CONFIG_USB_HCI
-+		addr = EEPROM_VID_8192EU;
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+		addr = EEPROM_VID_8192EE;
-+#endif
-+#endif /* CONFIG_RTL8192E */
-+#ifdef CONFIG_RTL8723B
-+		addr = EEPROM_VID_8723BU;
-+#endif /* CONFIG_RTL8192E */
-+
-+#ifdef CONFIG_RTL8188F
-+		addr = EEPROM_VID_8188FU;
-+#endif /* CONFIG_RTL8188F */
-+
-+#ifdef CONFIG_RTL8188GTV
-+		addr = EEPROM_VID_8188GTVU;
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+#ifdef CONFIG_USB_HCI
-+		addr = EEPROM_VID_8703BU;
-+#endif
-+#endif /* CONFIG_RTL8703B */
-+
-+#ifdef CONFIG_RTL8723D
-+#ifdef CONFIG_USB_HCI
-+		addr = EEPROM_VID_8723DU;
-+#endif /* CONFIG_USB_HCI */
-+#endif /* CONFIG_RTL8723D */
-+
-+		cnts = 4;
-+
-+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);
-+		if ((addr + cnts) > max_available_len) {
-+			RTW_INFO("%s: addr(0x%02x)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+		if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) {
-+			RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		/*		RTW_INFO("%s: {VID,PID}={", __FUNCTION__); */
-+		*extra = 0;
-+		pextra = extra;
-+		for (i = 0; i < cnts; i++) {
-+			/*			RTW_INFO("0x%02x", data[i]); */
-+			pextra += sprintf(pextra, "0x%02X", data[i]);
-+			if (i != (cnts - 1)) {
-+				/*				RTW_INFO(","); */
-+				pextra += sprintf(pextra, ",");
-+			}
-+		}
-+		/*		RTW_INFO("}\n"); */
-+	} else if (strcmp(tmp[0], "ableraw") == 0) {
-+#ifdef RTW_HALMAC
-+		raw_maxsize = efuse_GetavailableSize(padapter);
-+#else
-+		efuse_GetCurrentSize(padapter, &raw_cursize);
-+		raw_maxsize = efuse_GetMaxSize(padapter);
-+#endif
-+		sprintf(extra, "[available raw size]= %d bytes\n", raw_maxsize - raw_cursize);
-+	} else if (strcmp(tmp[0], "btableraw") == 0) {
-+		efuse_bt_GetCurrentSize(padapter, &raw_cursize);
-+		raw_maxsize = efuse_bt_GetMaxSize(padapter);
-+		sprintf(extra, "[available raw size]= %d bytes\n", raw_maxsize - raw_cursize);
-+	} else if (strcmp(tmp[0], "btfmap") == 0) {
-+
-+		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
-+
-+		mapLen = EFUSE_BT_MAX_MAP_LEN;
-+		if (rtw_BT_efuse_map_read(padapter, 0, mapLen, pEfuseHal->BTEfuseInitMap) == _FAIL) {
-+			RTW_INFO("%s: rtw_BT_efuse_map_read Fail!!\n", __FUNCTION__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		/*		RTW_INFO("OFFSET\tVALUE(hex)\n"); */
-+		sprintf(extra, "\n");
-+		for (i = 0; i < 512; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */
-+			/*			RTW_INFO("0x%03x\t", i); */
-+			pextra = extra + strlen(extra);
-+			pextra += sprintf(pextra, "0x%03x\t", i);
-+			for (j = 0; j < 8; j++) {
-+				/*				RTW_INFO("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); */
-+				pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]);
-+			}
-+			/*			RTW_INFO("\t"); */
-+			pextra += sprintf(pextra, "\t");
-+			for (; j < 16; j++) {
-+				/*				RTW_INFO("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); */
-+				pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]);
-+			}
-+			/*			RTW_INFO("\n"); */
-+			pextra += sprintf(pextra, "\n");
-+		}
-+		/*		RTW_INFO("\n"); */
-+	} else if (strcmp(tmp[0], "btbmap") == 0) {
-+		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
-+
-+		mapLen = EFUSE_BT_MAX_MAP_LEN;
-+		if (rtw_BT_efuse_map_read(padapter, 0, mapLen, pEfuseHal->BTEfuseInitMap) == _FAIL) {
-+			RTW_INFO("%s: rtw_BT_efuse_map_read Fail!!\n", __FUNCTION__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		/*		RTW_INFO("OFFSET\tVALUE(hex)\n"); */
-+		sprintf(extra, "\n");
-+		for (i = 512; i < 1024 ; i += 16) {
-+			/*			RTW_INFO("0x%03x\t", i); */
-+			pextra = extra + strlen(extra);
-+			pextra += sprintf(pextra, "0x%03x\t", i);
-+			for (j = 0; j < 8; j++) {
-+				/*				RTW_INFO("%02X ", data[i+j]); */
-+				pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]);
-+			}
-+			/*			RTW_INFO("\t"); */
-+			pextra += sprintf(pextra, "\t");
-+			for (; j < 16; j++) {
-+				/*				RTW_INFO("%02X ", data[i+j]); */
-+				pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]);
-+			}
-+			/*			RTW_INFO("\n"); */
-+			pextra += sprintf(pextra, "\n");
-+		}
-+		/*		RTW_INFO("\n"); */
-+	} else if (strcmp(tmp[0], "btrmap") == 0) {
-+		u8 BTStatus;
-+
-+		rtw_write8(padapter, 0xa3, 0x05); /* For 8723AB ,8821S ? */
-+		BTStatus = rtw_read8(padapter, 0xa0);
-+
-+		RTW_INFO("%s: Check 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus);
-+		if (BTStatus != 0x04) {
-+			sprintf(extra, "BT Status not Active ,can't to read BT eFuse\n");
-+			goto exit;
-+		}
-+
-+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
-+
-+		/* rmap addr cnts */
-+		addr = simple_strtoul(tmp[1], &ptmp, 16);
-+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
-+
-+		cnts = simple_strtoul(tmp[2], &ptmp, 10);
-+		if (cnts == 0) {
-+			RTW_INFO("%s: btrmap Fail!! cnts error!\n", __FUNCTION__);
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
-+#ifndef RTW_HALMAC
-+		EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);
-+		if ((addr + cnts) > max_available_len) {
-+			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+#endif
-+		if (rtw_BT_efuse_map_read(padapter, addr, cnts, data) == _FAIL) {
-+			RTW_INFO("%s: rtw_BT_efuse_map_read error!!\n", __FUNCTION__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		*extra = 0;
-+		pextra = extra;
-+		/*		RTW_INFO("%s: bt efuse data={", __FUNCTION__); */
-+		for (i = 0; i < cnts; i++) {
-+			/*			RTW_INFO("0x%02x ", data[i]); */
-+			pextra += sprintf(pextra, " 0x%02X ", data[i]);
-+		}
-+		/*		RTW_INFO("}\n"); */
-+		RTW_INFO(FUNC_ADPT_FMT ": BT MAC=[%s]\n", FUNC_ADPT_ARG(padapter), extra);
-+	} else if (strcmp(tmp[0], "btffake") == 0) {
-+		/*		RTW_INFO("OFFSET\tVALUE(hex)\n"); */
-+		sprintf(extra, "\n");
-+		for (i = 0; i < 512; i += 16) {
-+			/*			RTW_INFO("0x%03x\t", i); */
-+			pextra = extra + strlen(extra);
-+			pextra += sprintf(pextra, "0x%03x\t", i);
-+			for (j = 0; j < 8; j++) {
-+				/*				RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */
-+				pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);
-+			}
-+			/*			RTW_INFO("\t"); */
-+			pextra += sprintf(pextra, "\t");
-+			for (; j < 16; j++) {
-+				/*				RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */
-+				pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);
-+			}
-+			/*			RTW_INFO("\n"); */
-+			pextra += sprintf(pextra, "\n");
-+		}
-+		/*		RTW_INFO("\n"); */
-+	} else if (strcmp(tmp[0], "btbfake") == 0) {
-+		/*		RTW_INFO("OFFSET\tVALUE(hex)\n"); */
-+		sprintf(extra, "\n");
-+		for (i = 512; i < 1024; i += 16) {
-+			/*			RTW_INFO("0x%03x\t", i); */
-+			pextra = extra + strlen(extra);
-+			pextra += sprintf(pextra, "0x%03x\t", i);
-+			for (j = 0; j < 8; j++) {
-+				/*				RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */
-+				pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);
-+			}
-+			/*			RTW_INFO("\t"); */
-+			pextra += sprintf(pextra, "\t");
-+			for (; j < 16; j++) {
-+				/*				RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */
-+				pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]);
-+			}
-+			/*			RTW_INFO("\n"); */
-+			pextra += sprintf(pextra, "\n");
-+		}
-+		/*		RTW_INFO("\n"); */
-+	} else if (strcmp(tmp[0], "wlrfkmap") == 0) {
-+		static u8 fk_order = 0;
-+		u8 *efuse;
-+		u32 shift, cnt;
-+		u32 blksz = 0x200; /* The size of one time show, default 512 */
-+
-+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE);
-+		efuse = pEfuseHal->fakeEfuseModifiedMap;
-+
-+		shift = blksz * fk_order;
-+		efuse += shift;
-+		cnt = mapLen - shift;
-+		if (cnt > blksz) {
-+			cnt = blksz;
-+			fk_order++;
-+		} else
-+			fk_order = 0;
-+
-+		sprintf(extra, "\n");
-+		for (i = 0; i < cnt; i += 16) {
-+			pextra = extra + strlen(extra);
-+			pextra += sprintf(pextra, "0x%02x\t", shift + i);
-+			for (j = 0; j < 8; j++)
-+				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
-+			pextra += sprintf(pextra, "\t");
-+			for (; j < 16; j++)
-+				pextra += sprintf(pextra, "%02X ", efuse[i + j]);
-+			pextra += sprintf(pextra, "\n");
-+		}
-+		if ((shift + cnt) < mapLen)
-+			pextra += sprintf(pextra, "\t...more\n");
-+
-+	} else if (strcmp(tmp[0], "wlrfkrmap") == 0) {
-+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
-+			RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__);
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		/* rmap addr cnts */
-+		addr = simple_strtoul(tmp[1], &ptmp, 16);
-+		RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr);
-+
-+		cnts = simple_strtoul(tmp[2], &ptmp, 10);
-+		if (cnts == 0) {
-+			RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__);
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
-+
-+		/*		RTW_INFO("%s: data={", __FUNCTION__); */
-+		*extra = 0;
-+		pextra = extra;
-+		for (i = 0; i < cnts; i++) {
-+			RTW_INFO("wlrfkrmap = 0x%02x\n", pEfuseHal->fakeEfuseModifiedMap[addr + i]);
-+			pextra += sprintf(pextra, "0x%02X ", pEfuseHal->fakeEfuseModifiedMap[addr+i]);
-+		}
-+	} else if (strcmp(tmp[0], "btrfkrmap") == 0) {
-+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
-+			RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__);
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		/* rmap addr cnts */
-+		addr = simple_strtoul(tmp[1], &ptmp, 16);
-+		RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr);
-+
-+		cnts = simple_strtoul(tmp[2], &ptmp, 10);
-+		if (cnts == 0) {
-+			RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__);
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
-+
-+		/*		RTW_INFO("%s: data={", __FUNCTION__); */
-+		*extra = 0;
-+		pextra = extra;
-+		for (i = 0; i < cnts; i++) {
-+			RTW_INFO("wlrfkrmap = 0x%02x\n", pEfuseHal->fakeBTEfuseModifiedMap[addr + i]);
-+			pextra += sprintf(pextra, "0x%02X ", pEfuseHal->fakeBTEfuseModifiedMap[addr+i]);
-+		}
-+	} else if (strcmp(tmp[0], "mask") == 0) {
-+		*extra = 0;
-+		mask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(padapter);
-+		rtw_efuse_mask_array(padapter, mask_buf);
-+
-+		if (padapter->registrypriv.bFileMaskEfuse == _TRUE)
-+			_rtw_memcpy(mask_buf, maskfileBuffer, mask_len);
-+
-+		sprintf(extra, "\n");
-+		pextra = extra + strlen(extra);
-+		for (i = 0; i < mask_len; i++)
-+			pextra += sprintf(pextra, "0x%02X\n", mask_buf[i]);
-+
-+	} else if (strcmp(tmp[0], "btmask") == 0) {
-+		*extra = 0;
-+		mask_len = sizeof(u8) * rtw_get_bt_efuse_mask_arraylen(padapter);
-+		rtw_bt_efuse_mask_array(padapter, mask_buf);
-+
-+		if (padapter->registrypriv.bBTFileMaskEfuse == _TRUE)
-+			_rtw_memcpy(mask_buf, btmaskfileBuffer, mask_len);
-+
-+		sprintf(extra, "\n");
-+		pextra = extra + strlen(extra);
-+		for (i = 0; i < mask_len; i++)
-+			pextra += sprintf(pextra, "0x%02X\n", mask_buf[i]);
-+
-+	} else
-+		sprintf(extra, "Command not found!");
-+
-+exit:
-+	if (data)
-+		rtw_mfree(data, EFUSE_BT_MAX_MAP_LEN);
-+	if (rawdata)
-+		rtw_mfree(rawdata, EFUSE_BT_MAX_MAP_LEN);
-+	if (!err)
-+		wrqu->length = strlen(extra);
-+
-+	if (padapter->registrypriv.mp_mode == 0) {
-+#ifdef CONFIG_IPS
-+		rtw_pm_set_ips(padapter, ips_mode);
-+#endif /* CONFIG_IPS */
-+
-+#ifdef CONFIG_LPS
-+		rtw_pm_set_lps(padapter, lps_mode);
-+#endif /* CONFIG_LPS */
-+	}
-+
-+#ifdef CONFIG_IOL
-+	padapter->registrypriv.fw_iol = org_fw_iol;/* 0:Disable, 1:enable, 2:by usb speed */
-+#endif
-+	return err;
-+}
-+
-+
-+#ifdef CONFIG_MP_INCLUDED
-+static int rtw_mp_efuse_set(struct net_device *dev,
-+			    struct iw_request_info *info,
-+			    union iwreq_data *wdata, char *extra)
-+{
-+	struct iw_point *wrqu;
-+	PADAPTER padapter;
-+	struct pwrctrl_priv *pwrctrlpriv ;
-+	PHAL_DATA_TYPE pHalData;
-+	PEFUSE_HAL pEfuseHal;
-+	struct hal_ops *pHalFunc;
-+	struct mp_priv *pmp_priv;
-+
-+	u8 ips_mode = IPS_NUM; /* init invalid value */
-+	u8 lps_mode = PS_MODE_NUM; /* init invalid value */
-+	u32 i = 0, j = 0, jj, kk;
-+	u8 *setdata = NULL;
-+	u8 *ShadowMapBT = NULL;
-+	u8 *ShadowMapWiFi = NULL;
-+	u8 *setrawdata = NULL;
-+	char *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00};
-+	u16 addr = 0xFF, cnts = 0, BTStatus = 0 , max_available_len = 0;
-+	u16 wifimaplen;
-+	int err;
-+	boolean bcmpchk = _TRUE;
-+
-+
-+	wrqu = (struct iw_point *)wdata;
-+	padapter = rtw_netdev_priv(dev);
-+	pwrctrlpriv = adapter_to_pwrctl(padapter);
-+	pHalData = GET_HAL_DATA(padapter);
-+	pEfuseHal = &pHalData->EfuseHal;
-+	pHalFunc = &padapter->hal_func;
-+	pmp_priv = &padapter->mppriv;
-+
-+	err = 0;
-+
-+	if (copy_from_user(extra, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+#ifdef CONFIG_RTL8822C
-+	rtw_pre_bt_efuse(padapter);
-+#endif
-+	*(extra + wrqu->length) = '\0';
-+
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&wifimaplen, _FALSE);
-+
-+	setdata = rtw_zmalloc(1024);
-+	if (setdata == NULL) {
-+		err = -ENOMEM;
-+		goto exit;
-+	}
-+	ShadowMapBT = rtw_malloc(EFUSE_BT_MAX_MAP_LEN);
-+	if (ShadowMapBT == NULL) {
-+		err = -ENOMEM;
-+		goto exit;
-+	}
-+	ShadowMapWiFi = rtw_malloc(wifimaplen);
-+	if (ShadowMapWiFi == NULL) {
-+		err = -ENOMEM;
-+		goto exit;
-+	}
-+	setrawdata = rtw_malloc(EFUSE_MAX_SIZE);
-+	if (setrawdata == NULL) {
-+		err = -ENOMEM;
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_LPS
-+	lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */
-+	rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
-+#endif
-+
-+#ifdef CONFIG_IPS
-+	ips_mode = pwrctrlpriv->ips_mode;/* keep org value */
-+	rtw_pm_set_ips(padapter, IPS_NONE);
-+#endif
-+
-+	pch = extra;
-+	RTW_INFO("%s: in=%s\n", __FUNCTION__, extra);
-+
-+	i = 0;
-+	while ((token = strsep(&pch, ",")) != NULL) {
-+		if (i > 2)
-+			break;
-+		tmp[i] = token;
-+		i++;
-+	}
-+
-+	/* tmp[0],[1],[2] */
-+	/* wmap,addr,00e04c871200 */
-+	if (strcmp(tmp[0], "wmap") == 0) {
-+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+#ifndef RTW_HALMAC
-+		/* unknown bug workaround, need to fix later */
-+		addr = 0x1ff;
-+		rtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff));
-+		rtw_msleep_os(10);
-+		rtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03));
-+		rtw_msleep_os(10);
-+		rtw_write8(padapter, EFUSE_CTRL + 3, 0x72);
-+		rtw_msleep_os(10);
-+		rtw_read8(padapter, EFUSE_CTRL);
-+#endif /* RTW_HALMAC */
-+
-+		addr = simple_strtoul(tmp[1], &ptmp, 16);
-+		addr &= 0xFFF;
-+
-+		cnts = strlen(tmp[2]);
-+		if (cnts % 2) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		cnts /= 2;
-+		if (cnts == 0) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
-+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
-+		RTW_INFO("%s: map data=%s\n", __FUNCTION__, tmp[2]);
-+
-+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
-+			setdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
-+
-+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);
-+
-+		if ((addr + cnts) > max_available_len) {
-+			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {
-+			RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+		*extra = 0;
-+		RTW_INFO("%s: after rtw_efuse_map_write to _rtw_memcmp\n", __func__);
-+		if (rtw_efuse_mask_map_read(padapter, addr, cnts, ShadowMapWiFi) == _SUCCESS) {
-+			if (_rtw_memcmp((void *)ShadowMapWiFi , (void *)setdata, cnts)) {
-+				RTW_INFO("%s: WiFi write map afterf compare success\n", __FUNCTION__);
-+				sprintf(extra, "WiFi write map compare OK\n");
-+				err = 0;
-+				goto exit;
-+			} else {
-+				sprintf(extra, "WiFi write map compare FAIL\n");
-+				RTW_INFO("%s: WiFi write map compare Fail\n", __FUNCTION__);
-+				err = 0;
-+				goto exit;
-+			}
-+		}
-+	} else if (strcmp(tmp[0], "wraw") == 0) {
-+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		addr = simple_strtoul(tmp[1], &ptmp, 16);
-+		addr &= 0xFFF;
-+
-+		cnts = strlen(tmp[2]);
-+		if (cnts % 2) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		cnts /= 2;
-+		if (cnts == 0) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
-+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
-+		RTW_INFO("%s: raw data=%s\n", __FUNCTION__, tmp[2]);
-+
-+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
-+			setrawdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
-+
-+		if (rtw_efuse_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) {
-+			RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+	} else if (strcmp(tmp[0], "btwraw") == 0) {
-+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		addr = simple_strtoul(tmp[1], &ptmp, 16);
-+		addr &= 0xFFF;
-+
-+		cnts = strlen(tmp[2]);
-+		if (cnts % 2) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		cnts /= 2;
-+		if (cnts == 0) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
-+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
-+		RTW_INFO("%s: raw data=%s\n", __FUNCTION__, tmp[2]);
-+
-+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
-+			setrawdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
-+#ifdef RTW_HALMAC
-+		if (rtw_efuse_bt_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) {
-+			RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+#else
-+		rtw_write8(padapter, 0x35, 1); /* switch bank 1 (BT)*/
-+		if (rtw_efuse_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) {
-+			RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__);
-+			rtw_write8(padapter, 0x35, 0); /* switch bank 0 (WiFi)*/
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+		rtw_write8(padapter, 0x35, 0); /* switch bank 0 (WiFi)*/
-+#endif
-+	} else if (strcmp(tmp[0], "mac") == 0) {
-+		if (tmp[1] == NULL) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		/* mac,00e04c871200 */
-+
-+		if (hal_efuse_macaddr_offset(padapter) == -1) {
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		addr = hal_efuse_macaddr_offset(padapter);
-+		cnts = strlen(tmp[1]);
-+		if (cnts % 2) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		cnts /= 2;
-+		if (cnts == 0) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		if (cnts > 6) {
-+			RTW_INFO("%s: error data for mac addr=\"%s\"\n", __FUNCTION__, tmp[1]);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
-+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
-+		RTW_INFO("%s: MAC address=%s\n", __FUNCTION__, tmp[1]);
-+
-+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
-+			setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
-+
-+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);
-+
-+		if ((addr + cnts) > max_available_len) {
-+			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {
-+			RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+	} else if (strcmp(tmp[0], "vidpid") == 0) {
-+		if (tmp[1] == NULL) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		/* pidvid,da0b7881		 */
-+#ifdef CONFIG_RTL8188E
-+#ifdef CONFIG_USB_HCI
-+		addr = EEPROM_VID_88EU;
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+		addr = EEPROM_VID_88EE;
-+#endif
-+#endif /* CONFIG_RTL8188E */
-+
-+#ifdef CONFIG_RTL8192E
-+#ifdef CONFIG_USB_HCI
-+		addr = EEPROM_VID_8192EU;
-+#endif
-+#ifdef CONFIG_PCI_HCI
-+		addr = EEPROM_VID_8192EE;
-+#endif
-+#endif /* CONFIG_RTL8188E */
-+
-+#ifdef CONFIG_RTL8723B
-+		addr = EEPROM_VID_8723BU;
-+#endif
-+
-+#ifdef CONFIG_RTL8188F
-+		addr = EEPROM_VID_8188FU;
-+#endif
-+
-+#ifdef CONFIG_RTL8188GTV
-+		addr = EEPROM_VID_8188GTVU;
-+#endif
-+
-+#ifdef CONFIG_RTL8703B
-+#ifdef CONFIG_USB_HCI
-+		addr = EEPROM_VID_8703BU;
-+#endif /* CONFIG_USB_HCI */
-+#endif /* CONFIG_RTL8703B */
-+
-+#ifdef CONFIG_RTL8723D
-+#ifdef CONFIG_USB_HCI
-+		addr = EEPROM_VID_8723DU;
-+#endif /* CONFIG_USB_HCI */
-+#endif /* CONFIG_RTL8723D */
-+
-+		cnts = strlen(tmp[1]);
-+		if (cnts % 2) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		cnts /= 2;
-+		if (cnts == 0) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
-+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
-+		RTW_INFO("%s: VID/PID=%s\n", __FUNCTION__, tmp[1]);
-+
-+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
-+			setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
-+
-+		EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);
-+		if ((addr + cnts) > max_available_len) {
-+			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {
-+			RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+	} else if (strcmp(tmp[0], "wldumpfake") == 0) {
-+		if (wifimaplen > EFUSE_MAX_MAP_LEN)
-+			cnts = EFUSE_MAX_MAP_LEN;
-+		else
-+			cnts = wifimaplen;
-+		if (rtw_efuse_mask_map_read(padapter, 0, cnts, pEfuseHal->fakeEfuseModifiedMap) == _SUCCESS)
-+			RTW_INFO("%s: WiFi hw efuse dump to Fake map success\n", __func__);
-+		else {
-+			RTW_INFO("%s: WiFi hw efuse dump to Fake map Fail\n", __func__);
-+			err = -EFAULT;
-+		}
-+	} else if (strcmp(tmp[0], "btwmap") == 0) {
-+		rtw_write8(padapter, 0xa3, 0x05); /* For 8723AB ,8821S ? */
-+		BTStatus = rtw_read8(padapter, 0xa0);
-+		RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus);
-+		if (BTStatus != 0x04) {
-+			sprintf(extra, "BT Status not Active ,can't do Write\n");
-+			goto exit;
-+		}
-+
-+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+#ifndef RTW_HALMAC
-+		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
-+		addr = 0x1ff;
-+		rtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff));
-+		rtw_msleep_os(10);
-+		rtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03));
-+		rtw_msleep_os(10);
-+		rtw_write8(padapter, EFUSE_CTRL + 3, 0x72);
-+		rtw_msleep_os(10);
-+		rtw_read8(padapter, EFUSE_CTRL);
-+		BTEfuse_PowerSwitch(padapter, 1, _FALSE);
-+#endif /* RTW_HALMAC */
-+
-+		addr = simple_strtoul(tmp[1], &ptmp, 16);
-+		addr &= 0xFFF;
-+
-+		cnts = strlen(tmp[2]);
-+		if (cnts % 2) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		cnts /= 2;
-+		if (cnts == 0) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
-+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
-+		RTW_INFO("%s: BT data=%s\n", __FUNCTION__, tmp[2]);
-+
-+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
-+			setdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
-+#ifndef RTW_HALMAC
-+		EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (void *)&max_available_len, _FALSE);
-+		if ((addr + cnts) > max_available_len) {
-+			RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+#endif
-+		if (rtw_BT_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) {
-+			RTW_INFO("%s: rtw_BT_efuse_map_write error!!\n", __FUNCTION__);
-+			sprintf(extra, "BT write FAIL !!!\n");
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+		*extra = 0;
-+		RTW_INFO("%s: after rtw_BT_efuse_map_write to _rtw_memcmp\n", __FUNCTION__);
-+		if ((rtw_BT_efuse_map_read(padapter, addr, cnts, ShadowMapBT) == _SUCCESS)) {
-+			if (_rtw_memcmp((void *)ShadowMapBT , (void *)setdata, cnts)) {
-+				RTW_INFO("%s: BT write map compare OK BTStatus=0x%x\n", __FUNCTION__, BTStatus);
-+				sprintf(extra, "BT write map compare OK");
-+				err = 0;
-+				goto exit;
-+			} else {
-+				sprintf(extra, "BT write map compare FAIL");
-+				RTW_INFO("%s: BT write map compare FAIL BTStatus=0x%x\n", __FUNCTION__, BTStatus);
-+				err = 0;
-+				goto exit;
-+			}
-+		}
-+	} else if (strcmp(tmp[0], "btwfake") == 0) {
-+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		if (pmp_priv->bprocess_mp_mode != _TRUE) {
-+			RTW_INFO("%s: btwfake not to be exec, please first to mp_start\n", __FUNCTION__);
-+			sprintf(extra, "Error, btwfake cant to be exec, please first to mp_start !!!!\n");
-+			err = 0;
-+			goto exit;
-+		}
-+		addr = simple_strtoul(tmp[1], &ptmp, 16);
-+		addr &= 0xFFF;
-+
-+		cnts = strlen(tmp[2]);
-+		if (cnts % 2) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		cnts /= 2;
-+		if (cnts == 0) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
-+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
-+		RTW_INFO("%s: BT tmp data=%s\n", __FUNCTION__, tmp[2]);
-+
-+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
-+			pEfuseHal->fakeBTEfuseModifiedMap[addr + jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
-+	} else if (strcmp(tmp[0], "btdumpfake") == 0) {
-+		if (rtw_BT_efuse_map_read(padapter, 0, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _SUCCESS)
-+			RTW_INFO("%s: BT read all map success\n", __FUNCTION__);
-+		else {
-+			RTW_INFO("%s: BT read all map Fail!\n", __FUNCTION__);
-+			err = -EFAULT;
-+		}
-+	} else if (strcmp(tmp[0], "btfk2map") == 0) {
-+#ifdef CONFIG_BT_EFUSE_MASK
-+		if (padapter->registrypriv.bBTFileMaskEfuse != _TRUE && pmp_priv->bloadBTefusemap == _TRUE) {
-+			RTW_INFO("%s: File BT eFuse mask file not to be loaded\n", __FUNCTION__);
-+			sprintf(extra, "Not load BT eFuse mask file yet, Please advance to use [ efuse_bt_mask ], now remove the Adapter.!!!!\n");
-+			rtw_set_surprise_removed(padapter);
-+			err = 0;
-+			goto exit;
-+		}
-+#endif
-+		rtw_write8(padapter, 0xa3, 0x05);
-+		BTStatus = rtw_read8(padapter, 0xa0);
-+		RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus);
-+		if (BTStatus != 0x04) {
-+			sprintf(extra, "BT Status not Active Write FAIL\n");
-+			goto exit;
-+		}
-+		if (pmp_priv->bprocess_mp_mode != _TRUE) {
-+			RTW_INFO("%s: btfk2map not to be exec, please first to mp_start\n", __FUNCTION__);
-+			sprintf(extra, "Error, btfk2map cant to be exec, please first to mp_start !!!!\n");
-+			err = 0;
-+			goto exit;
-+		}
-+#ifndef RTW_HALMAC
-+		BTEfuse_PowerSwitch(padapter, 1, _TRUE);
-+		addr = 0x1ff;
-+		rtw_write8(padapter, EFUSE_CTRL + 1, (addr & 0xff));
-+		rtw_msleep_os(10);
-+		rtw_write8(padapter, EFUSE_CTRL + 2, ((addr >> 8) & 0x03));
-+		rtw_msleep_os(10);
-+		rtw_write8(padapter, EFUSE_CTRL + 3, 0x72);
-+		rtw_msleep_os(10);
-+		rtw_read8(padapter, EFUSE_CTRL);
-+		BTEfuse_PowerSwitch(padapter, 1, _FALSE);
-+#endif /* RTW_HALMAC */
-+
-+		if (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL) {
-+			RTW_INFO("%s: rtw_BT_efuse_map_write error!\n", __FUNCTION__);
-+			sprintf(extra, "BT write FAIL !!!\n");
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		RTW_INFO("pEfuseHal->fakeBTEfuseModifiedMap OFFSET\tVALUE(hex)\n");
-+		for (i = 0; i < EFUSE_BT_MAX_MAP_LEN; i += 16) {
-+			printk("0x%02x\t", i);
-+			for (j = 0; j < 8; j++)
-+				printk("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i + j]);
-+			printk("\t");
-+
-+			for (; j < 16; j++)
-+				printk("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i + j]);
-+			printk("\n");
-+		}
-+		printk("\n");
-+#if 1
-+		err = -EFAULT;
-+		RTW_INFO("%s: rtw_BT_efuse_map_read _rtw_memcmp\n", __FUNCTION__);
-+		if ((rtw_BT_efuse_map_read(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseInitMap) == _SUCCESS)) {
-+			if (_rtw_memcmp((void *)pEfuseHal->fakeBTEfuseModifiedMap, (void *)pEfuseHal->fakeBTEfuseInitMap, EFUSE_BT_MAX_MAP_LEN)) {
-+				sprintf(extra, "BT write map compare OK");
-+				RTW_INFO("%s: BT write map afterf compare success BTStatus=0x%x\n", __FUNCTION__, BTStatus);
-+				err = 0;
-+				goto exit;
-+			} else {
-+				sprintf(extra, "BT write map compare FAIL");
-+				if (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL)
-+					RTW_INFO("%s: rtw_BT_efuse_map_write compare error,retry = %d!\n", __FUNCTION__, i);
-+
-+				if (rtw_BT_efuse_map_read(padapter, EFUSE_BT, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseInitMap) == _SUCCESS) {
-+					RTW_INFO("pEfuseHal->fakeBTEfuseInitMap OFFSET\tVALUE(hex)\n");
-+
-+					for (i = 0; i < EFUSE_BT_MAX_MAP_LEN; i += 16) {
-+						printk("0x%02x\t", i);
-+						for (j = 0; j < 8; j++)
-+							printk("%02X ", pEfuseHal->fakeBTEfuseInitMap[i + j]);
-+						printk("\t");
-+						for (; j < 16; j++)
-+							printk("%02X ", pEfuseHal->fakeBTEfuseInitMap[i + j]);
-+						printk("\n");
-+					}
-+					printk("\n");
-+				}
-+				RTW_INFO("%s: BT write map afterf compare not match to write efuse try write Map again , BTStatus=0x%x\n", __FUNCTION__, BTStatus);
-+				goto exit;
-+			}
-+		}
-+#endif
-+
-+	} else if (strcmp(tmp[0], "wlfk2map") == 0) {
-+		*extra = 0;
-+
-+		if (padapter->registrypriv.bFileMaskEfuse != _TRUE && pmp_priv->bloadefusemap == _TRUE) {
-+			RTW_INFO("%s: File eFuse mask file not to be loaded\n", __FUNCTION__);
-+			sprintf(extra, "Not load eFuse mask file yet, Please use the efuse_mask CMD, now remove the interface !!!!\n");
-+			rtw_set_surprise_removed(padapter);
-+			err = 0;
-+			goto exit;
-+		}
-+
-+		if (pmp_priv->bprocess_mp_mode != _TRUE) {
-+			RTW_INFO("%s: wlfk2map not to be exec, please first to mp_start\n", __FUNCTION__);
-+			sprintf(extra, "Error, wlfk2map cant to be exec, please first to mp_start !!!!\n");
-+			err = 0;
-+			goto exit;
-+		}
-+		if (wifimaplen > EFUSE_MAX_MAP_LEN)
-+			cnts = EFUSE_MAX_MAP_LEN;
-+		else
-+			cnts = wifimaplen;
-+		if (rtw_efuse_map_write(padapter, 0x00, cnts, pEfuseHal->fakeEfuseModifiedMap) == _FAIL) {
-+			RTW_INFO("%s: rtw_efuse_map_write fakeEfuseModifiedMap error!\n", __FUNCTION__);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		if (rtw_efuse_mask_map_read(padapter, 0x00, wifimaplen, ShadowMapWiFi) == _SUCCESS) {
-+			addr = 0x00;
-+			err = _TRUE;
-+
-+			for (i = 0; i < cnts; i++) {
-+				if (padapter->registrypriv.boffefusemask == 0) {
-+					if (padapter->registrypriv.bFileMaskEfuse == _TRUE) {
-+						if (rtw_file_efuse_IsMasked(padapter, addr + i, maskfileBuffer) == _TRUE)	/*use file efuse mask. */
-+							bcmpchk = _FALSE;
-+					} else {
-+						if (efuse_IsMasked(padapter, addr + i) == _TRUE)
-+							bcmpchk = _FALSE;
-+					}
-+				}
-+
-+				if (bcmpchk == _TRUE) {
-+					RTW_INFO("compare readMapWiFi[0x%02x] = %x, ModifiedMap = %x\n", addr + i, ShadowMapWiFi[ addr + i], pEfuseHal->fakeEfuseModifiedMap[addr + i]);
-+					if (_rtw_memcmp((void *) &ShadowMapWiFi[addr + i], (void *)&pEfuseHal->fakeEfuseModifiedMap[addr + i], 1) == _FALSE){
-+						err = _FALSE;
-+						break;
-+					}
-+				}
-+				bcmpchk = _TRUE;
-+			}
-+		}
-+
-+		if (err) {
-+			RTW_INFO("%s: WiFi write map afterf compare OK\n", __FUNCTION__);
-+			sprintf(extra, "WiFi write map compare OK\n");
-+			err = 0;
-+			goto exit;
-+		} else {
-+			sprintf(extra, "WiFi write map compare FAIL\n");
-+			RTW_INFO("%s: WiFi write map compare Fail\n", __FUNCTION__);
-+			err = 0;
-+			goto exit;
-+		}
-+	} else if (strcmp(tmp[0], "wlwfake") == 0) {
-+		if ((tmp[1] == NULL) || (tmp[2] == NULL)) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		if (pmp_priv->bprocess_mp_mode != _TRUE) {
-+			RTW_INFO("%s: wlwfake not to be exec, please first to mp_start\n", __FUNCTION__);
-+			sprintf(extra, "Error, wlwfake cant to be exec, please first to mp_start !!!!\n");
-+			err = 0;
-+			goto exit;
-+		}
-+		addr = simple_strtoul(tmp[1], &ptmp, 16);
-+		addr &= 0xFFF;
-+
-+		cnts = strlen(tmp[2]);
-+		if (cnts % 2) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		cnts /= 2;
-+		if (cnts == 0) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
-+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
-+		RTW_INFO("%s: map tmp data=%s\n", __FUNCTION__, tmp[2]);
-+
-+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
-+			pEfuseHal->fakeEfuseModifiedMap[addr + jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]);
-+		_rtw_memset(extra, '\0', strlen(extra));
-+		sprintf(extra, "wlwfake OK\n");
-+
-+	}
-+	else if (strcmp(tmp[0], "wfakemac") == 0) {
-+		if (tmp[1] == NULL) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		if (pmp_priv->bprocess_mp_mode != _TRUE) {
-+			RTW_INFO("%s: wfakemac not to be exec, please first to mp_start\n", __FUNCTION__);
-+			sprintf(extra, "Error, wfakemac cant to be exec, please first to mp_start !!!!\n");
-+			err = 0;
-+			goto exit;
-+		}
-+		/* wfakemac,00e04c871200 */
-+		if (hal_efuse_macaddr_offset(padapter) == -1) {
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		addr = hal_efuse_macaddr_offset(padapter);
-+		cnts = strlen(tmp[1]);
-+		if (cnts % 2) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		cnts /= 2;
-+		if (cnts == 0) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		if (cnts > 6) {
-+			RTW_INFO("%s: error data for mac addr=\"%s\"\n", __FUNCTION__, tmp[1]);
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+
-+		RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr);
-+		RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts);
-+		RTW_INFO("%s: MAC address=%s\n", __FUNCTION__, tmp[1]);
-+
-+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2)
-+			if ((addr + jj) < EFUSE_MAX_MAP_LEN)
-+				pEfuseHal->fakeEfuseModifiedMap[addr + jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
-+
-+		_rtw_memset(extra, '\0', strlen(extra));
-+		sprintf(extra, "write mac addr to fake map OK\n");
-+	} else if(strcmp(tmp[0], "update") == 0) {
-+		RTW_INFO("To Use new eFuse map ver3\n");
-+		if (tmp[1] != 0x00) {
-+			pmp_priv->efuse_update_file = _TRUE;
-+			strcpy(pmp_priv->efuse_file_path , tmp[1]);
-+			RTW_INFO("Got file path %s\n", pmp_priv->efuse_file_path);
-+		}
-+		/*step read efuse/eeprom data and get mac_addr*/
-+		if (padapter->hal_func.read_adapter_info(padapter)) {
-+			_rtw_memset(extra, '\0', strlen(extra));
-+			sprintf(extra, "eFuse Update OK\n");
-+			RTW_INFO("eFuse Update OK\n");
-+		} else {
-+			_rtw_memset(extra, '\0', strlen(extra));
-+			sprintf(extra, "eFuse Update FAIL\n");
-+			RTW_INFO("eFuse Update FAIL\n");
-+		}
-+		pmp_priv->efuse_update_file = _FALSE;
-+		RTW_INFO("To Use new eFuse map done ver3\n");
-+	} else if (strcmp(tmp[0], "analyze") == 0) {
-+
-+		rtw_efuse_analyze(padapter, EFUSE_WIFI, 0);
-+		_rtw_memset(extra, '\0', strlen(extra));
-+		sprintf(extra, "eFuse Analyze OK,please to check kernel log\n");
-+	}
-+exit:
-+	if (setdata)
-+		rtw_mfree(setdata, 1024);
-+	if (ShadowMapBT)
-+		rtw_mfree(ShadowMapBT, EFUSE_BT_MAX_MAP_LEN);
-+	if (ShadowMapWiFi)
-+		rtw_mfree(ShadowMapWiFi, wifimaplen);
-+	if (setrawdata)
-+		rtw_mfree(setrawdata, EFUSE_MAX_SIZE);
-+
-+	wrqu->length = strlen(extra);
-+
-+	if (padapter->registrypriv.mp_mode == 0) {
-+#ifdef CONFIG_IPS
-+		rtw_pm_set_ips(padapter, ips_mode);
-+#endif /* CONFIG_IPS */
-+
-+#ifdef CONFIG_LPS
-+		rtw_pm_set_lps(padapter, lps_mode);
-+#endif /* CONFIG_LPS */
-+	}
-+
-+	return err;
-+}
-+
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+static int rtw_mp_customer_str(
-+	struct net_device *dev,
-+	struct iw_request_info *info,
-+	union iwreq_data *wrqu, char *extra)
-+{
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	u32 len;
-+	u8 *pbuf = NULL, *pch;
-+	char *ptmp;
-+	u8 param[RTW_CUSTOMER_STR_LEN];
-+	u8 count = 0;
-+	u8 tmp;
-+	u8 i;
-+	u32 pos;
-+	u8 ret;
-+	u8 read = 0;
-+
-+	if (adapter->registrypriv.mp_mode != 1
-+		|| !adapter->registrypriv.mp_customer_str)
-+		return -EFAULT;
-+
-+	len = wrqu->data.length + 1;
-+
-+	pbuf = (u8 *)rtw_zmalloc(len);
-+	if (pbuf == NULL) {
-+		RTW_WARN("%s: no memory!\n", __func__);
-+		return -ENOMEM;
-+	}
-+
-+	if (copy_from_user(pbuf, wrqu->data.pointer, wrqu->data.length)) {
-+		rtw_mfree(pbuf, len);
-+		RTW_WARN("%s: copy from user fail!\n", __func__);
-+		return -EFAULT;
-+	}
-+	RTW_INFO("%s: string=\"%s\"\n", __func__, pbuf);
-+
-+	ptmp = (char *)pbuf;
-+	pch = strsep(&ptmp, ",");
-+	if ((pch == NULL) || (strlen(pch) == 0)) {
-+		rtw_mfree(pbuf, len);
-+		RTW_INFO("%s: parameter error(no cmd)!\n", __func__);
-+		return -EFAULT;
-+	}
-+
-+	_rtw_memset(param, 0xFF, RTW_CUSTOMER_STR_LEN);
-+
-+	if (strcmp(pch, "read") == 0) {
-+		read = 1;
-+		ret = rtw_hal_customer_str_read(adapter, param);
-+
-+	} else if (strcmp(pch, "write") == 0) {
-+		do {
-+			pch = strsep(&ptmp, ":");
-+			if ((pch == NULL) || (strlen(pch) == 0))
-+				break;
-+			if (strlen(pch) != 2
-+				|| IsHexDigit(*pch) == _FALSE
-+				|| IsHexDigit(*(pch + 1)) == _FALSE
-+				|| sscanf(pch, "%hhx", &tmp) != 1
-+			) {
-+				RTW_WARN("%s: invalid 8-bit hex!\n", __func__);
-+				rtw_mfree(pbuf, len);
-+				return -EFAULT;
-+			}
-+
-+			param[count++] = tmp;
-+
-+		} while (count < RTW_CUSTOMER_STR_LEN);
-+
-+		if (count == 0) {
-+			rtw_mfree(pbuf, len);
-+			RTW_WARN("%s: no input!\n", __func__);
-+			return -EFAULT;
-+		}
-+		ret = rtw_hal_customer_str_write(adapter, param);
-+	} else {
-+		rtw_mfree(pbuf, len);
-+		RTW_INFO("%s: parameter error(unknown cmd)!\n", __func__);
-+		return -EFAULT;
-+	}
-+
-+	pos = sprintf(extra, "%s: ", read ? "read" : "write");
-+	if (read == 0 || ret == _SUCCESS) {
-+		for (i = 0; i < RTW_CUSTOMER_STR_LEN; i++)
-+			pos += sprintf(extra + pos, "%02x:", param[i]);
-+		extra[pos] = 0;
-+		pos--;
-+	}
-+	pos += sprintf(extra + pos, " %s", ret == _SUCCESS ? "OK" : "FAIL");
-+
-+	wrqu->data.length = strlen(extra) + 1;
-+
-+	rtw_mfree(pbuf, len);
-+	return 0;
-+}
-+#endif /* CONFIG_RTW_CUSTOMER_STR */
-+
-+static int rtw_priv_mp_set(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wdata, char *extra)
-+{
-+
-+	struct iw_point *wrqu = (struct iw_point *)wdata;
-+	u32 subcmd = wrqu->flags;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	int status = 0;
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (!is_primary_adapter(padapter)) {
-+		RTW_INFO("MP mode only primary Adapter support\n");
-+		return -EIO;
-+	}
-+#endif
-+
-+	RTW_INFO("%s mutx in %d\n", __func__, subcmd);
-+	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL);
-+	switch (subcmd) {
-+	case CTA_TEST:
-+		RTW_INFO("set CTA_TEST\n");
-+		status = rtw_cta_test_start(dev, info, wdata, extra);
-+		break;
-+	case MP_DISABLE_BT_COEXIST:
-+		RTW_INFO("set case MP_DISABLE_BT_COEXIST\n");
-+		status = rtw_mp_disable_bt_coexist(dev, info, wdata, extra);
-+		break;
-+	case MP_IQK:
-+		RTW_INFO("set MP_IQK\n");
-+		status = rtw_mp_iqk(dev, info, wrqu, extra);
-+		break;
-+	case MP_LCK:
-+		RTW_INFO("set MP_LCK\n");
-+		status = rtw_mp_lck(dev, info, wrqu, extra);
-+	break;
-+
-+	default:
-+		status = -EIO;
-+	}
-+	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL);
-+	RTW_INFO("%s mutx done %d\n", __func__, subcmd);
-+
-+	return status;
-+}
-+
-+static int rtw_priv_mp_get(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wdata, char *extra)
-+{
-+
-+	struct iw_point *wrqu = (struct iw_point *)wdata;
-+	u32 subcmd = wrqu->flags;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	int status = 0;
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (!is_primary_adapter(padapter)) {
-+		RTW_INFO("MP mode only primary Adapter support\n");
-+		return -EIO;
-+	}
-+#endif
-+
-+	RTW_INFO("%s mutx in %d\n", __func__, subcmd);
-+	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL);
-+
-+	switch (subcmd) {
-+	case MP_START:
-+		RTW_INFO("set case mp_start\n");
-+		status = rtw_mp_start(dev, info, wrqu, extra);
-+		break;
-+	case MP_STOP:
-+		RTW_INFO("set case mp_stop\n");
-+		status = rtw_mp_stop(dev, info, wrqu, extra);
-+		break;
-+	case MP_BANDWIDTH:
-+		RTW_INFO("set case mp_bandwidth\n");
-+		status = rtw_mp_bandwidth(dev, info, wrqu, extra);
-+		break;
-+	case MP_RESET_STATS:
-+		RTW_INFO("set case MP_RESET_STATS\n");
-+		status = rtw_mp_reset_stats(dev, info, wrqu, extra);
-+		break;
-+	case MP_SetRFPathSwh:
-+		RTW_INFO("set MP_SetRFPathSwitch\n");
-+		status = rtw_mp_SetRFPath(dev, info, wrqu, extra);
-+		break;
-+	case WRITE_REG:
-+		status = rtw_mp_write_reg(dev, info, wrqu, extra);
-+		break;
-+	case WRITE_RF:
-+		status = rtw_mp_write_rf(dev, info, wrqu, extra);
-+		break;
-+	case MP_PHYPARA:
-+		RTW_INFO("mp_get  MP_PHYPARA\n");
-+		status = rtw_mp_phypara(dev, info, wrqu, extra);
-+		break;
-+	case MP_CHANNEL:
-+		RTW_INFO("set case mp_channel\n");
-+		status = rtw_mp_channel(dev , info, wrqu, extra);
-+		break;
-+	case  MP_CHL_OFFSET:
-+		RTW_INFO("set case mp_ch_offset\n");
-+		status = rtw_mp_ch_offset(dev , info, wrqu, extra);
-+		break;
-+	case READ_REG:
-+		RTW_INFO("mp_get  READ_REG\n");
-+		status = rtw_mp_read_reg(dev, info, wrqu, extra);
-+		break;
-+	case READ_RF:
-+		RTW_INFO("mp_get  READ_RF\n");
-+		status = rtw_mp_read_rf(dev, info, wrqu, extra);
-+		break;
-+	case MP_RATE:
-+		RTW_INFO("set case mp_rate\n");
-+		status = rtw_mp_rate(dev, info, wrqu, extra);
-+		break;
-+	case MP_TXPOWER:
-+		RTW_INFO("set case MP_TXPOWER\n");
-+		status = rtw_mp_txpower(dev, info, wrqu, extra);
-+		break;
-+	case MP_ANT_TX:
-+		RTW_INFO("set case MP_ANT_TX\n");
-+		status = rtw_mp_ant_tx(dev, info, wrqu, extra);
-+		break;
-+	case MP_ANT_RX:
-+		RTW_INFO("set case MP_ANT_RX\n");
-+		status = rtw_mp_ant_rx(dev, info, wrqu, extra);
-+		break;
-+	case MP_QUERY:
-+		status = rtw_mp_trx_query(dev, info, wrqu, extra);
-+		break;
-+	case MP_CTX:
-+		RTW_INFO("set case MP_CTX\n");
-+		status = rtw_mp_ctx(dev, info, wrqu, extra);
-+		break;
-+	case MP_ARX:
-+		RTW_INFO("set case MP_ARX\n");
-+		status = rtw_mp_arx(dev, info, wrqu, extra);
-+		break;
-+	case MP_DUMP:
-+		RTW_INFO("set case MP_DUMP\n");
-+		status = rtw_mp_dump(dev, info, wrqu, extra);
-+		break;
-+	case MP_PSD:
-+		RTW_INFO("set case MP_PSD\n");
-+		status = rtw_mp_psd(dev, info, wrqu, extra);
-+		break;
-+	case MP_THER:
-+		RTW_INFO("set case MP_THER\n");
-+		status = rtw_mp_thermal(dev, info, wrqu, extra);
-+		break;
-+	case MP_PwrCtlDM:
-+		RTW_INFO("set MP_PwrCtlDM\n");
-+		status = rtw_mp_PwrCtlDM(dev, info, wrqu, extra);
-+		break;
-+	case MP_QueryDrvStats:
-+		RTW_INFO("mp_get MP_QueryDrvStats\n");
-+		status = rtw_mp_QueryDrv(dev, info, wdata, extra);
-+		break;
-+	case MP_PWRTRK:
-+		RTW_INFO("set case MP_PWRTRK\n");
-+		status = rtw_mp_pwrtrk(dev, info, wrqu, extra);
-+		break;
-+	case MP_SET_TSSIDE:
-+		RTW_INFO("set case MP_TSSI_DE\n");
-+		status = rtw_mp_set_tsside(dev, info, wrqu, extra);
-+		break;
-+#ifdef CONFIG_MP_INCLUDED
-+	case EFUSE_SET:
-+		RTW_INFO("set case efuse set\n");
-+		status = rtw_mp_efuse_set(dev, info, wdata, extra);
-+		break;
-+#endif
-+	case EFUSE_GET:
-+		RTW_INFO("efuse get EFUSE_GET\n");
-+		status = rtw_mp_efuse_get(dev, info, wdata, extra);
-+		break;
-+	case MP_GET_TXPOWER_INX:
-+		RTW_INFO("mp_get MP_GET_TXPOWER_INX\n");
-+		status = rtw_mp_txpower_index(dev, info, wrqu, extra);
-+		break;
-+	case MP_GETVER:
-+		RTW_INFO("mp_get MP_GETVER\n");
-+		status = rtw_mp_getver(dev, info, wdata, extra);
-+		break;
-+	case MP_MON:
-+		RTW_INFO("mp_get MP_MON\n");
-+		status = rtw_mp_mon(dev, info, wdata, extra);
-+		break;
-+	case EFUSE_BT_MASK:
-+		RTW_INFO("mp_get EFUSE_BT_MASK\n");
-+		status = rtw_bt_efuse_mask_file(dev, info, wdata, extra);
-+		break;
-+	case EFUSE_MASK:
-+		RTW_INFO("mp_get EFUSE_MASK\n");
-+		status = rtw_efuse_mask_file(dev, info, wdata, extra);
-+		break;
-+	case EFUSE_FILE:
-+		RTW_INFO("mp_get EFUSE_FILE\n");
-+		status = rtw_efuse_file_map(dev, info, wdata, extra);
-+		break;
-+	case EFUSE_FILE_STORE:
-+		RTW_INFO("mp_get EFUSE_FILE_STORE\n");
-+		status = rtw_efuse_file_map_store(dev, info, wdata, extra);
-+		break;
-+	case MP_TX:
-+		RTW_INFO("mp_get MP_TX\n");
-+		status = rtw_mp_tx(dev, info, wdata, extra);
-+		break;
-+	case MP_RX:
-+		RTW_INFO("mp_get MP_RX\n");
-+		status = rtw_mp_rx(dev, info, wdata, extra);
-+		break;
-+	case MP_HW_TX_MODE:
-+		RTW_INFO("mp_get MP_HW_TX_MODE\n");
-+		status = rtw_mp_hwtx(dev, info, wdata, extra);
-+		break;
-+	case MP_GET_TSSIDE:
-+		RTW_INFO("mp_get TSSI_DE\n");
-+		status = rtw_mp_get_tsside(dev, info, wrqu, extra);
-+		break;
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+	case MP_CUSTOMER_STR:
-+		RTW_INFO("customer str\n");
-+		status = rtw_mp_customer_str(dev, info, wdata, extra);
-+		break;
-+#endif
-+	case MP_PWRLMT:
-+		RTW_INFO("mp_get MP_SETPWRLMT\n");
-+		status = rtw_mp_pwrlmt(dev, info, wdata, extra);
-+		break;
-+	case MP_PWRBYRATE:
-+		RTW_INFO("mp_get MP_SETPWRBYRATE\n");
-+		status = rtw_mp_pwrbyrate(dev, info, wdata, extra);
-+		break;
-+	case  BT_EFUSE_FILE:
-+		RTW_INFO("mp_get BT EFUSE_FILE\n");
-+		status = rtw_bt_efuse_file_map(dev, info, wdata, extra);
-+		break;
-+	case MP_SWRFPath:
-+		RTW_INFO("mp_get MP_SWRFPath\n");
-+		status = rtw_mp_switch_rf_path(dev, info, wrqu, extra);
-+		break;
-+	case MP_LINK:
-+		RTW_INFO("mp_get MP_LINK\n");
-+		status = rtw_mp_link(dev, info, wrqu, extra);
-+		break;
-+	case MP_DPK_TRK:
-+		RTW_INFO("mp_get MP_DPK_TRK\n");
-+		status = rtw_mp_dpk_track(dev, info, wdata, extra);
-+		break;
-+	case MP_DPK:
-+		RTW_INFO("set MP_DPK\n");
-+		status = rtw_mp_dpk(dev, info, wdata, extra);
-+		break;
-+	default:
-+		status = -EIO;
-+	}
-+
-+	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->ioctrl_mutex), NULL);
-+	RTW_INFO("%s mutx done_%d\n", __func__, subcmd);
-+
-+	return status;
-+}
-+#endif /*#if defined(CONFIG_MP_INCLUDED)*/
-+
-+
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+#define DBG_MP_SDIO_INDIRECT_ACCESS 1
-+static int rtw_mp_sd_iread(struct net_device *dev
-+			   , struct iw_request_info *info
-+			   , struct iw_point *wrqu
-+			   , char *extra)
-+{
-+	char input[16];
-+	u8 width;
-+	unsigned long addr;
-+	u32 ret = 0;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+
-+	if (wrqu->length > 16) {
-+		RTW_INFO(FUNC_ADPT_FMT" wrqu->length:%d\n", FUNC_ADPT_ARG(padapter), wrqu->length);
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length)) {
-+		RTW_INFO(FUNC_ADPT_FMT" copy_from_user fail\n", FUNC_ADPT_ARG(padapter));
-+		ret = -EFAULT;
-+		goto exit;
-+	}
-+
-+	_rtw_memset(extra, 0, wrqu->length);
-+
-+	if (sscanf(input, "%hhu,%lx", &width, &addr) != 2) {
-+		RTW_INFO(FUNC_ADPT_FMT" sscanf fail\n", FUNC_ADPT_ARG(padapter));
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	if (addr > 0x3FFF) {
-+		RTW_INFO(FUNC_ADPT_FMT" addr:0x%lx\n", FUNC_ADPT_ARG(padapter), addr);
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	if (DBG_MP_SDIO_INDIRECT_ACCESS)
-+		RTW_INFO(FUNC_ADPT_FMT" width:%u, addr:0x%lx\n", FUNC_ADPT_ARG(padapter), width, addr);
-+
-+	switch (width) {
-+	case 1:
-+		sprintf(extra, "0x%02x", rtw_sd_iread8(padapter, addr));
-+		wrqu->length = strlen(extra);
-+		break;
-+	case 2:
-+		sprintf(extra, "0x%04x", rtw_sd_iread16(padapter, addr));
-+		wrqu->length = strlen(extra);
-+		break;
-+	case 4:
-+		sprintf(extra, "0x%08x", rtw_sd_iread32(padapter, addr));
-+		wrqu->length = strlen(extra);
-+		break;
-+	default:
-+		wrqu->length = 0;
-+		ret = -EINVAL;
-+		break;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+static int rtw_mp_sd_iwrite(struct net_device *dev
-+			    , struct iw_request_info *info
-+			    , struct iw_point *wrqu
-+			    , char *extra)
-+{
-+	char width;
-+	unsigned long addr, data;
-+	int ret = 0;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	char input[32];
-+
-+	if (wrqu->length > 32) {
-+		RTW_INFO(FUNC_ADPT_FMT" wrqu->length:%d\n", FUNC_ADPT_ARG(padapter), wrqu->length);
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length)) {
-+		RTW_INFO(FUNC_ADPT_FMT" copy_from_user fail\n", FUNC_ADPT_ARG(padapter));
-+		ret = -EFAULT;
-+		goto exit;
-+	}
-+
-+	_rtw_memset(extra, 0, wrqu->length);
-+
-+	if (sscanf(input, "%hhu,%lx,%lx", &width, &addr, &data) != 3) {
-+		RTW_INFO(FUNC_ADPT_FMT" sscanf fail\n", FUNC_ADPT_ARG(padapter));
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	if (addr > 0x3FFF) {
-+		RTW_INFO(FUNC_ADPT_FMT" addr:0x%lx\n", FUNC_ADPT_ARG(padapter), addr);
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	if (DBG_MP_SDIO_INDIRECT_ACCESS)
-+		RTW_INFO(FUNC_ADPT_FMT" width:%u, addr:0x%lx, data:0x%lx\n", FUNC_ADPT_ARG(padapter), width, addr, data);
-+
-+	switch (width) {
-+	case 1:
-+		if (data > 0xFF) {
-+			ret = -EINVAL;
-+			break;
-+		}
-+		rtw_sd_iwrite8(padapter, addr, data);
-+		break;
-+	case 2:
-+		if (data > 0xFFFF) {
-+			ret = -EINVAL;
-+			break;
-+		}
-+		rtw_sd_iwrite16(padapter, addr, data);
-+		break;
-+	case 4:
-+		rtw_sd_iwrite32(padapter, addr, data);
-+		break;
-+	default:
-+		wrqu->length = 0;
-+		ret = -EINVAL;
-+		break;
-+	}
-+
-+exit:
-+	return ret;
-+}
-+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
-+
-+static int rtw_priv_set(struct net_device *dev,
-+			struct iw_request_info *info,
-+			union iwreq_data *wdata, char *extra)
-+{
-+	struct iw_point *wrqu = (struct iw_point *)wdata;
-+	u32 subcmd = wrqu->flags;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+
-+	if (padapter == NULL)
-+		return -ENETDOWN;
-+
-+	if (padapter->bup == _FALSE) {
-+		RTW_INFO(" %s fail =>(padapter->bup == _FALSE )\n", __FUNCTION__);
-+		return -ENETDOWN;
-+	}
-+
-+	if (RTW_CANNOT_RUN(padapter)) {
-+		RTW_INFO("%s fail =>(bSurpriseRemoved == _TRUE) || ( bDriverStopped == _TRUE)\n", __func__);
-+		return -ENETDOWN;
-+	}
-+
-+	if (extra == NULL) {
-+		wrqu->length = 0;
-+		return -EIO;
-+	}
-+
-+	if (subcmd < MP_NULL) {
-+#ifdef CONFIG_MP_INCLUDED
-+		rtw_priv_mp_set(dev, info, wdata, extra);
-+#endif
-+		return 0;
-+	}
-+
-+	switch (subcmd) {
-+#ifdef CONFIG_WOWLAN
-+	case MP_WOW_ENABLE:
-+		RTW_INFO("set case MP_WOW_ENABLE: %s\n", extra);
-+
-+		rtw_wowlan_ctrl(dev, info, wdata, extra);
-+		break;
-+	case MP_WOW_SET_PATTERN:
-+		RTW_INFO("set case MP_WOW_SET_PATTERN: %s\n", extra);
-+		rtw_wowlan_set_pattern(dev, info, wdata, extra);
-+		break;
-+	#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+	case MP_WOW_SET_KEEP_ALIVE_PATTERN:
-+		RTW_INFO("set case MP_WOW_SET_KEEP_ALIVE_PATTERN: %s\n", extra);
-+		rtw_wowlan_set_keep_alive_pattern(dev, info, wdata, extra);
-+		break;
-+	#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+
-+#endif
-+#ifdef CONFIG_AP_WOWLAN
-+	case MP_AP_WOW_ENABLE:
-+		RTW_INFO("set case MP_AP_WOW_ENABLE: %s\n", extra);
-+		rtw_ap_wowlan_ctrl(dev, info, wdata, extra);
-+		break;
-+#endif
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+	case VENDOR_IE_SET:
-+		RTW_INFO("set case VENDOR_IE_SET\n");
-+		rtw_vendor_ie_set(dev , info , wdata , extra);
-+		break;
-+#endif
-+	default:
-+		return -EIO;
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static int rtw_priv_get(struct net_device *dev,
-+			struct iw_request_info *info,
-+			union iwreq_data *wdata, char *extra)
-+{
-+	struct iw_point *wrqu = (struct iw_point *)wdata;
-+	u32 subcmd = wrqu->flags;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct dm_struct	*p_dm = &pHalData->odmpriv;
-+	struct dm_rf_calibration_struct	*p_rf_calibrate_info = &(p_dm->rf_calibrate_info);
-+	struct dm_iqk_info	*p_iqk_info = &p_dm->IQK_info;
-+	u32 i = 100;
-+
-+
-+	if (padapter->bup == _FALSE) {
-+		RTW_INFO(" %s fail =>(padapter->bup == _FALSE )\n", __FUNCTION__);
-+		return -ENETDOWN;
-+	}
-+
-+	if (RTW_CANNOT_RUN(padapter)) {
-+		RTW_INFO("%s fail =>(padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)\n", __func__);
-+		return -ENETDOWN;
-+	}
-+
-+	if (extra == NULL) {
-+		wrqu->length = 0;
-+		return -EIO;
-+	}
-+
-+	if (subcmd < MP_NULL) {
-+#ifdef CONFIG_MP_INCLUDED
-+		while (i > 1) {
-+			if (p_rf_calibrate_info->is_iqk_in_progress) {
-+				rtw_msleep_os(10);
-+			} else {
-+				p_iqk_info->rfk_forbidden = _TRUE;
-+				break;
-+			}
-+			i--;
-+		}
-+		if (subcmd == MP_CHANNEL || subcmd == MP_BANDWIDTH || subcmd == MP_START || subcmd == MP_DPK)
-+			p_iqk_info->rfk_forbidden = _FALSE;
-+		rtw_priv_mp_get(dev, info, wdata, extra);
-+		rtw_msleep_os(10); /* delay 5ms for sending pkt before exit adb shell operation */
-+		p_iqk_info->rfk_forbidden = _FALSE;
-+#endif
-+	} else {
-+			switch (subcmd) {
-+#if defined(CONFIG_RTL8723B)
-+			case MP_SetBT:
-+				RTW_INFO("set MP_SetBT\n");
-+				rtw_mp_SetBT(dev, info, wdata, extra);
-+				break;
-+#endif
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+			case MP_SD_IREAD:
-+				rtw_mp_sd_iread(dev, info, wrqu, extra);
-+				break;
-+			case MP_SD_IWRITE:
-+				rtw_mp_sd_iwrite(dev, info, wrqu, extra);
-+				break;
-+#endif
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+			case VENDOR_IE_GET:
-+				RTW_INFO("get case VENDOR_IE_GET\n");
-+				rtw_vendor_ie_get(dev , info , wdata , extra);
-+				break;
-+#endif
-+			default:
-+				return -EIO;
-+			}
-+		}
-+
-+	return 0;
-+}
-+
-+
-+#ifdef CONFIG_TDLS
-+static int rtw_wx_tdls_wfd_enable(struct net_device *dev,
-+				  struct iw_request_info *info,
-+				  union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_WFD
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
-+
-+	if (extra[0] == '0')
-+		rtw_tdls_wfd_enable(padapter, 0);
-+	else
-+		rtw_tdls_wfd_enable(padapter, 1);
-+
-+#endif /* CONFIG_WFD */
-+
-+	return ret;
-+}
-+
-+static int rtw_tdls_weaksec(struct net_device *dev,
-+			    struct iw_request_info *info,
-+			    union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+
-+	u8 i, j;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
-+
-+	if (extra[0] == '0')
-+		padapter->wdinfo.wfd_tdls_weaksec = 0;
-+	else
-+		padapter->wdinfo.wfd_tdls_weaksec = 1;
-+
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+
-+static int rtw_tdls_enable(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
-+
-+	if (extra[0] == '0')
-+		rtw_disable_tdls_func(padapter, _TRUE);
-+	else if (extra[0] == '1')
-+		rtw_enable_tdls_func(padapter);
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+static int rtw_tdls_setup(struct net_device *dev,
-+			  struct iw_request_info *info,
-+			  union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+#ifdef CONFIG_TDLS
-+	u8 i, j;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct tdls_txmgmt txmgmt;
-+#ifdef CONFIG_WFD
-+	struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-+#endif /* CONFIG_WFD */
-+
-+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
-+
-+	if (wrqu->data.length - 1 != 17) {
-+		RTW_INFO("[%s] length:%d != 17\n", __FUNCTION__, (wrqu->data.length - 1));
-+		return ret;
-+	}
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
-+		txmgmt.peer[i] = key_2char2num(*(extra + j), *(extra + j + 1));
-+
-+#ifdef CONFIG_WFD
-+	if (_AES_ != padapter->securitypriv.dot11PrivacyAlgrthm) {
-+		/* Weak Security situation with AP. */
-+		if (0 == pwdinfo->wfd_tdls_weaksec)	{
-+			/* Can't send the tdls setup request out!! */
-+			RTW_INFO("[%s] Current link is not AES, "
-+				"SKIP sending the tdls setup request!!\n", __FUNCTION__);
-+		} else
-+			issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
-+	} else
-+#endif /* CONFIG_WFD */
-+	{
-+		issue_tdls_setup_req(padapter, &txmgmt, _TRUE);
-+	}
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+static int rtw_tdls_teardown(struct net_device *dev,
-+			     struct iw_request_info *info,
-+			     union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+
-+	u8 i, j;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct sta_info *ptdls_sta = NULL;
-+	struct tdls_txmgmt txmgmt;
-+
-+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
-+
-+	if (wrqu->data.length - 1 != 17 && wrqu->data.length - 1 != 19) {
-+		RTW_INFO("[%s] length:%d != 17 or 19\n",
-+			 __FUNCTION__, (wrqu->data.length - 1));
-+		return ret;
-+	}
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	for (i = 0, j = 0; i < ETH_ALEN; i++, j += 3)
-+		txmgmt.peer[i] = key_2char2num(*(extra + j), *(extra + j + 1));
-+
-+	ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), txmgmt.peer);
-+
-+	if (ptdls_sta != NULL) {
-+		txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;
-+		if (wrqu->data.length - 1 == 19)
-+			issue_tdls_teardown(padapter, &txmgmt, _FALSE);
-+		else
-+			issue_tdls_teardown(padapter, &txmgmt, _TRUE);
-+	} else
-+		RTW_INFO("TDLS peer not found\n");
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+static int rtw_tdls_discovery(struct net_device *dev,
-+			      struct iw_request_info *info,
-+			      union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct tdls_txmgmt	txmgmt;
-+	int i = 0, j = 0;
-+
-+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+	for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
-+		txmgmt.peer[i] = key_2char2num(*(extra + j), *(extra + j + 1));
-+
-+	issue_tdls_dis_req(padapter, &txmgmt);
-+
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+static int rtw_tdls_ch_switch(struct net_device *dev,
-+			      struct iw_request_info *info,
-+			      union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_TDLS_CH_SW
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
-+	u8 i, j;
-+	struct sta_info *ptdls_sta = NULL;
-+	u8 take_care_iqk;
-+
-+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
-+
-+	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
-+		RTW_INFO("TDLS channel switch is not allowed\n");
-+		return ret;
-+	}
-+
-+	for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
-+		pchsw_info->addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));
-+
-+	ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pchsw_info->addr);
-+	if (ptdls_sta == NULL)
-+		return ret;
-+
-+	pchsw_info->ch_sw_state |= TDLS_CH_SW_INITIATOR_STATE;
-+
-+	if (ptdls_sta != NULL) {
-+		if (pchsw_info->off_ch_num == 0)
-+			pchsw_info->off_ch_num = 11;
-+	} else
-+		RTW_INFO("TDLS peer not found\n");
-+
-+	rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
-+
-+	rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
-+	if (take_care_iqk == _TRUE) {
-+#ifdef CONFIG_TDLS_CH_SW_V2
-+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE);
-+#else
-+		u8 central_chnl;
-+		u8 bw_mode;
-+
-+		bw_mode = (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20;
-+		central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset);
-+		if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) >= 0)
-+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);
-+		else
-+			rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE);
-+#endif
-+	} else
-+		rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);
-+
-+	/* issue_tdls_ch_switch_req(padapter, ptdls_sta); */
-+	/* RTW_INFO("issue tdls ch switch req\n"); */
-+
-+#endif /* CONFIG_TDLS_CH_SW */
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+static int rtw_tdls_ch_switch_off(struct net_device *dev,
-+				  struct iw_request_info *info,
-+				  union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_TDLS_CH_SW
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
-+	u8 i, j, mac_addr[ETH_ALEN];
-+	struct sta_info *ptdls_sta = NULL;
-+	struct tdls_txmgmt txmgmt;
-+
-+	_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
-+
-+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
-+
-+	if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) {
-+		RTW_INFO("TDLS channel switch is not allowed\n");
-+		return ret;
-+	}
-+
-+	if (wrqu->data.length >= 17) {
-+		for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
-+			mac_addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));
-+		ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);
-+	}
-+
-+	if (ptdls_sta == NULL)
-+		return ret;
-+
-+	rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL);
-+
-+	pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE |
-+				     TDLS_CH_SWITCH_ON_STATE |
-+				     TDLS_PEER_AT_OFF_STATE);
-+	_rtw_memset(pchsw_info->addr, 0x00, ETH_ALEN);
-+
-+	ptdls_sta->ch_switch_time = 0;
-+	ptdls_sta->ch_switch_timeout = 0;
-+	_cancel_timer_ex(&ptdls_sta->ch_sw_timer);
-+	_cancel_timer_ex(&ptdls_sta->delay_timer);
-+	_cancel_timer_ex(&ptdls_sta->stay_on_base_chnl_timer);
-+	_cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer);
-+
-+	rtw_pm_set_lps(padapter, PS_MODE_MAX);
-+#endif /* CONFIG_TDLS_CH_SW */
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+static int rtw_tdls_dump_ch(struct net_device *dev,
-+			    struct iw_request_info *info,
-+			    union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_TDLS_CH_SW
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+
-+	RTW_INFO("[%s] dump_stack:%s\n", __FUNCTION__, extra);
-+
-+	extra[wrqu->data.length] = 0x00;
-+	ptdlsinfo->chsw_info.dump_stack = rtw_atoi(extra);
-+
-+	return ret;
-+
-+#endif
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+static int rtw_tdls_off_ch_num(struct net_device *dev,
-+			       struct iw_request_info *info,
-+			       union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_TDLS_CH_SW
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+
-+	RTW_INFO("[%s] off_ch_num:%s\n", __FUNCTION__, extra);
-+
-+	extra[wrqu->data.length] = 0x00;
-+	ptdlsinfo->chsw_info.off_ch_num = rtw_atoi(extra);
-+
-+	return ret;
-+
-+#endif
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+static int rtw_tdls_ch_offset(struct net_device *dev,
-+			      struct iw_request_info *info,
-+			      union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_TDLS_CH_SW
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+
-+	RTW_INFO("[%s] ch_offset:%s\n", __FUNCTION__, extra);
-+
-+	extra[wrqu->data.length] = 0x00;
-+	switch (rtw_atoi(extra)) {
-+	case SCA:
-+		ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
-+		break;
-+
-+	case SCB:
-+		ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
-+		break;
-+
-+	default:
-+		ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+		break;
-+	}
-+
-+	return ret;
-+
-+#endif
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+static int rtw_tdls_pson(struct net_device *dev,
-+			 struct iw_request_info *info,
-+			 union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 i, j, mac_addr[ETH_ALEN];
-+	struct sta_info *ptdls_sta = NULL;
-+
-+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
-+
-+	for (i = 0, j = 0; i < ETH_ALEN; i++, j += 3)
-+		mac_addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));
-+
-+	ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);
-+
-+	issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 3, 500);
-+
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+static int rtw_tdls_psoff(struct net_device *dev,
-+			  struct iw_request_info *info,
-+			  union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 i, j, mac_addr[ETH_ALEN];
-+	struct sta_info *ptdls_sta = NULL;
-+
-+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
-+
-+	for (i = 0, j = 0; i < ETH_ALEN; i++, j += 3)
-+		mac_addr[i] = key_2char2num(*(extra + j), *(extra + j + 1));
-+
-+	ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr);
-+
-+	if (ptdls_sta)
-+		issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 3, 500);
-+
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+static int rtw_tdls_setip(struct net_device *dev,
-+			  struct iw_request_info *info,
-+			  union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_WFD
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;
-+	u8 i = 0, j = 0, k = 0, tag = 0;
-+
-+	RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1);
-+
-+	while (i < 4) {
-+		for (j = 0; j < 4; j++) {
-+			if (*(extra + j + tag) == '.' || *(extra + j + tag) == '\0') {
-+				if (j == 1)
-+					pwfd_info->ip_address[i] = convert_ip_addr('0', '0', *(extra + (j - 1) + tag));
-+				if (j == 2)
-+					pwfd_info->ip_address[i] = convert_ip_addr('0', *(extra + (j - 2) + tag), *(extra + (j - 1) + tag));
-+				if (j == 3)
-+					pwfd_info->ip_address[i] = convert_ip_addr(*(extra + (j - 3) + tag), *(extra + (j - 2) + tag), *(extra + (j - 1) + tag));
-+
-+				tag += j + 1;
-+				break;
-+			}
-+		}
-+		i++;
-+	}
-+
-+	RTW_INFO("[%s] Set IP = %u.%u.%u.%u\n", __FUNCTION__,
-+		 ptdlsinfo->wfd_info->ip_address[0],
-+		 ptdlsinfo->wfd_info->ip_address[1],
-+		 ptdlsinfo->wfd_info->ip_address[2],
-+		 ptdlsinfo->wfd_info->ip_address[3]);
-+
-+#endif /* CONFIG_WFD */
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+static int rtw_tdls_getip(struct net_device *dev,
-+			  struct iw_request_info *info,
-+			  union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_WFD
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;
-+
-+	RTW_INFO("[%s]\n", __FUNCTION__);
-+
-+	sprintf(extra, "\n\n%u.%u.%u.%u\n",
-+		pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1],
-+		pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]);
-+
-+	RTW_INFO("[%s] IP=%u.%u.%u.%u\n", __FUNCTION__,
-+		 pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1],
-+		 pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]);
-+
-+	wrqu->data.length = strlen(extra);
-+
-+#endif /* CONFIG_WFD */
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+static int rtw_tdls_getport(struct net_device *dev,
-+			    struct iw_request_info *info,
-+			    union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_WFD
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+	struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info;
-+
-+	RTW_INFO("[%s]\n", __FUNCTION__);
-+
-+	sprintf(extra, "\n\n%d\n", pwfd_info->peer_rtsp_ctrlport);
-+	RTW_INFO("[%s] remote port = %d\n",
-+		 __FUNCTION__, pwfd_info->peer_rtsp_ctrlport);
-+
-+	wrqu->data.length = strlen(extra);
-+
-+#endif /* CONFIG_WFD */
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+
-+}
-+
-+/* WFDTDLS, for sigma test */
-+static int rtw_tdls_dis_result(struct net_device *dev,
-+			       struct iw_request_info *info,
-+			       union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+#ifdef CONFIG_WFD
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+
-+	RTW_INFO("[%s]\n", __FUNCTION__);
-+
-+	if (ptdlsinfo->dev_discovered == _TRUE) {
-+		sprintf(extra, "\n\nDis=1\n");
-+		ptdlsinfo->dev_discovered = _FALSE;
-+	}
-+
-+	wrqu->data.length = strlen(extra);
-+
-+#endif /* CONFIG_WFD */
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+
-+}
-+
-+/* WFDTDLS, for sigma test */
-+static int rtw_wfd_tdls_status(struct net_device *dev,
-+			       struct iw_request_info *info,
-+			       union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
-+
-+	RTW_INFO("[%s]\n", __FUNCTION__);
-+
-+	sprintf(extra, "\nlink_established:%d\n"
-+		"sta_cnt:%d\n"
-+		"sta_maximum:%d\n"
-+		"cur_channel:%d\n"
-+		"tdls_enable:%d"
-+#ifdef CONFIG_TDLS_CH_SW
-+		"ch_sw_state:%08x\n"
-+		"chsw_on:%d\n"
-+		"off_ch_num:%d\n"
-+		"cur_time:%d\n"
-+		"ch_offset:%d\n"
-+		"delay_swtich_back:%d"
-+#endif
-+		,
-+		ptdlsinfo->link_established, ptdlsinfo->sta_cnt,
-+		ptdlsinfo->sta_maximum, ptdlsinfo->cur_channel,
-+		rtw_is_tdls_enabled(padapter)
-+#ifdef CONFIG_TDLS_CH_SW
-+		,
-+		ptdlsinfo->chsw_info.ch_sw_state,
-+		ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on),
-+		ptdlsinfo->chsw_info.off_ch_num,
-+		ptdlsinfo->chsw_info.cur_time,
-+		ptdlsinfo->chsw_info.ch_offset,
-+		ptdlsinfo->chsw_info.delay_switch_back
-+#endif
-+	       );
-+
-+	wrqu->data.length = strlen(extra);
-+
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+
-+}
-+
-+static int rtw_tdls_getsta(struct net_device *dev,
-+			   struct iw_request_info *info,
-+			   union iwreq_data *wrqu, char *extra)
-+{
-+
-+	int ret = 0;
-+#ifdef CONFIG_TDLS
-+	u8 i, j;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 addr[ETH_ALEN] = {0};
-+	char charmac[17];
-+	struct sta_info *ptdls_sta = NULL;
-+
-+	RTW_INFO("[%s] %s %d\n", __FUNCTION__,
-+		 (char *)wrqu->data.pointer, wrqu->data.length - 1);
-+
-+	if (copy_from_user(charmac, wrqu->data.pointer + 9, 17)) {
-+		ret = -EFAULT;
-+		goto exit;
-+	}
-+
-+	RTW_INFO("[%s] %d, charmac:%s\n", __FUNCTION__, __LINE__, charmac);
-+	for (i = 0, j = 0 ; i < ETH_ALEN; i++, j += 3)
-+		addr[i] = key_2char2num(*(charmac + j), *(charmac + j + 1));
-+
-+	RTW_INFO("[%s] %d, charmac:%s, addr:"MAC_FMT"\n",
-+		 __FUNCTION__, __LINE__, charmac, MAC_ARG(addr));
-+	ptdls_sta = rtw_get_stainfo(&padapter->stapriv, addr);
-+	if (ptdls_sta) {
-+		sprintf(extra, "\n\ntdls_sta_state=0x%08x\n", ptdls_sta->tdls_sta_state);
-+		RTW_INFO("\n\ntdls_sta_state=%d\n", ptdls_sta->tdls_sta_state);
-+	} else {
-+		sprintf(extra, "\n\nNot found this sta\n");
-+		RTW_INFO("\n\nNot found this sta\n");
-+	}
-+	wrqu->data.length = strlen(extra);
-+
-+exit:
-+#endif /* CONFIG_TDLS */
-+	return ret;
-+
-+}
-+
-+static int rtw_tdls_get_best_ch(struct net_device *dev,
-+				struct iw_request_info *info,
-+				union iwreq_data *wrqu, char *extra)
-+{
-+#ifdef CONFIG_FIND_BEST_CHANNEL
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0;
-+
-+	for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {
-+		if (rfctl->channel_set[i].ChannelNum == 1)
-+			index_24G = i;
-+		if (rfctl->channel_set[i].ChannelNum == 36)
-+			index_5G = i;
-+	}
-+
-+	for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {
-+		/* 2.4G */
-+		if (rfctl->channel_set[i].ChannelNum == 6 || rfctl->channel_set[i].ChannelNum == 11) {
-+			if (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) {
-+				index_24G = i;
-+				best_channel_24G = rfctl->channel_set[i].ChannelNum;
-+			}
-+		}
-+
-+		/* 5G */
-+		if (rfctl->channel_set[i].ChannelNum >= 36
-+		    && rfctl->channel_set[i].ChannelNum < 140) {
-+			/* Find primary channel */
-+			if (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0)
-+			    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {
-+				index_5G = i;
-+				best_channel_5G = rfctl->channel_set[i].ChannelNum;
-+			}
-+		}
-+
-+		if (rfctl->channel_set[i].ChannelNum >= 149
-+		    && rfctl->channel_set[i].ChannelNum < 165) {
-+			/* Find primary channel */
-+			if (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0)
-+			    && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {
-+				index_5G = i;
-+				best_channel_5G = rfctl->channel_set[i].ChannelNum;
-+			}
-+		}
-+#if 1 /* debug */
-+		RTW_INFO("The rx cnt of channel %3d = %d\n",
-+			 rfctl->channel_set[i].ChannelNum,
-+			 rfctl->channel_set[i].rx_count);
-+#endif
-+	}
-+
-+	sprintf(extra, "\nbest_channel_24G = %d\n", best_channel_24G);
-+	RTW_INFO("best_channel_24G = %d\n", best_channel_24G);
-+
-+	if (index_5G != 0) {
-+		sprintf(extra, "best_channel_5G = %d\n", best_channel_5G);
-+		RTW_INFO("best_channel_5G = %d\n", best_channel_5G);
-+	}
-+
-+	wrqu->data.length = strlen(extra);
-+
-+#endif
-+
-+	return 0;
-+
-+}
-+#endif /*#ifdef CONFIG_TDLS*/
-+static int rtw_tdls(struct net_device *dev,
-+		    struct iw_request_info *info,
-+		    union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra);
-+
-+	if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) {
-+		RTW_INFO("Discard tdls oper since hal doesn't support tdls\n");
-+		return 0;
-+	}
-+
-+	if (rtw_is_tdls_enabled(padapter) == _FALSE) {
-+		RTW_INFO("TDLS is not enabled\n");
-+		return 0;
-+	}
-+
-+	/* WFD Sigma will use the tdls enable command to let the driver know we want to test the tdls now! */
-+
-+	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
-+		if (_rtw_memcmp(extra, "wfdenable=", 10)) {
-+			wrqu->data.length -= 10;
-+			rtw_wx_tdls_wfd_enable(dev, info, wrqu, &extra[10]);
-+			return ret;
-+		}
-+	}
-+
-+	if (_rtw_memcmp(extra, "weaksec=", 8)) {
-+		wrqu->data.length -= 8;
-+		rtw_tdls_weaksec(dev, info, wrqu, &extra[8]);
-+		return ret;
-+	} else if (_rtw_memcmp(extra, "tdlsenable=", 11)) {
-+		wrqu->data.length -= 11;
-+		rtw_tdls_enable(dev, info, wrqu, &extra[11]);
-+		return ret;
-+	}
-+
-+	if (_rtw_memcmp(extra, "setup=", 6)) {
-+		wrqu->data.length -= 6;
-+		rtw_tdls_setup(dev, info, wrqu, &extra[6]);
-+	} else if (_rtw_memcmp(extra, "tear=", 5)) {
-+		wrqu->data.length -= 5;
-+		rtw_tdls_teardown(dev, info, wrqu, &extra[5]);
-+	} else if (_rtw_memcmp(extra, "dis=", 4)) {
-+		wrqu->data.length -= 4;
-+		rtw_tdls_discovery(dev, info, wrqu, &extra[4]);
-+	} else if (_rtw_memcmp(extra, "swoff=", 6)) {
-+		wrqu->data.length -= 6;
-+		rtw_tdls_ch_switch_off(dev, info, wrqu, &extra[6]);
-+	} else if (_rtw_memcmp(extra, "sw=", 3)) {
-+		wrqu->data.length -= 3;
-+		rtw_tdls_ch_switch(dev, info, wrqu, &extra[3]);
-+	} else if (_rtw_memcmp(extra, "dumpstack=", 10)) {
-+		wrqu->data.length -= 10;
-+		rtw_tdls_dump_ch(dev, info, wrqu, &extra[10]);
-+	} else if (_rtw_memcmp(extra, "offchnum=", 9)) {
-+		wrqu->data.length -= 9;
-+		rtw_tdls_off_ch_num(dev, info, wrqu, &extra[9]);
-+	} else if (_rtw_memcmp(extra, "choffset=", 9)) {
-+		wrqu->data.length -= 9;
-+		rtw_tdls_ch_offset(dev, info, wrqu, &extra[9]);
-+	} else if (_rtw_memcmp(extra, "pson=", 5)) {
-+		wrqu->data.length -= 5;
-+		rtw_tdls_pson(dev, info, wrqu, &extra[5]);
-+	} else if (_rtw_memcmp(extra, "psoff=", 6)) {
-+		wrqu->data.length -= 6;
-+		rtw_tdls_psoff(dev, info, wrqu, &extra[6]);
-+	}
-+
-+#ifdef CONFIG_WFD
-+	if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
-+		if (_rtw_memcmp(extra, "setip=", 6)) {
-+			wrqu->data.length -= 6;
-+			rtw_tdls_setip(dev, info, wrqu, &extra[6]);
-+		} else if (_rtw_memcmp(extra, "tprobe=", 6))
-+			issue_tunneled_probe_req((_adapter *)rtw_netdev_priv(dev));
-+	}
-+#endif /* CONFIG_WFD */
-+
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+
-+static int rtw_tdls_get(struct net_device *dev,
-+			struct iw_request_info *info,
-+			union iwreq_data *wrqu, char *extra)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_TDLS
-+
-+	RTW_INFO("[%s] extra = %s\n", __FUNCTION__, (char *) wrqu->data.pointer);
-+
-+	if (_rtw_memcmp(wrqu->data.pointer, "ip", 2))
-+		rtw_tdls_getip(dev, info, wrqu, extra);
-+	else if (_rtw_memcmp(wrqu->data.pointer, "port", 4))
-+		rtw_tdls_getport(dev, info, wrqu, extra);
-+	/* WFDTDLS, for sigma test */
-+	else if (_rtw_memcmp(wrqu->data.pointer, "dis", 3))
-+		rtw_tdls_dis_result(dev, info, wrqu, extra);
-+	else if (_rtw_memcmp(wrqu->data.pointer, "status", 6))
-+		rtw_wfd_tdls_status(dev, info, wrqu, extra);
-+	else if (_rtw_memcmp(wrqu->data.pointer, "tdls_sta=", 9))
-+		rtw_tdls_getsta(dev, info, wrqu, extra);
-+	else if (_rtw_memcmp(wrqu->data.pointer, "best_ch", 7))
-+		rtw_tdls_get_best_ch(dev, info, wrqu, extra);
-+#endif /* CONFIG_TDLS */
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
-+
-+#if defined(CONFIG_RTL8188E)
-+#include <rtl8188e_hal.h>
-+extern void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc);
-+#define cal_txdesc_chksum(padapter, desc) rtl8188e_cal_txdesc_chksum(desc)
-+#ifdef CONFIG_SDIO_HCI || defined(CONFIG_GSPI_HCI)
-+extern void rtl8188es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf);
-+#define fill_default_txdesc rtl8188es_fill_default_txdesc
-+#endif /* CONFIG_SDIO_HCI */
-+#endif /* CONFIG_RTL8188E */
-+#if defined(CONFIG_RTL8723B)
-+extern void rtl8723b_cal_txdesc_chksum(struct tx_desc *ptxdesc);
-+#define cal_txdesc_chksum(padapter, desc) rtl8723b_cal_txdesc_chksum(desc)
-+extern void rtl8723b_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf);
-+#define fill_default_txdesc rtl8723b_fill_default_txdesc
-+#endif /* CONFIG_RTL8723B */
-+
-+#if defined(CONFIG_RTL8703B)
-+/* extern void rtl8703b_cal_txdesc_chksum(struct tx_desc *ptxdesc); */
-+#define cal_txdesc_chksum(padapter, desc) rtl8703b_cal_txdesc_chksum(desc)
-+/* extern void rtl8703b_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */
-+#define fill_default_txdesc rtl8703b_fill_default_txdesc
-+#endif /* CONFIG_RTL8703B */
-+
-+#if defined(CONFIG_RTL8723D)
-+/* extern void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc); */
-+#define cal_txdesc_chksum(padapter, desc) rtl8723d_cal_txdesc_chksum(desc)
-+/* extern void rtl8723d_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */
-+#define fill_default_txdesc rtl8723d_fill_default_txdesc
-+#endif /* CONFIG_RTL8723D */
-+
-+#if defined(CONFIG_RTL8710B)
-+#define cal_txdesc_chksum(padapter, desc) rtl8710b_cal_txdesc_chksum(desc)
-+#define fill_default_txdesc rtl8710b_fill_default_txdesc
-+#endif /* CONFIG_RTL8710B */
-+
-+#if defined(CONFIG_RTL8192E)
-+extern void rtl8192e_cal_txdesc_chksum(struct tx_desc *ptxdesc);
-+#define cal_txdesc_chksum(padapter, desc) rtl8192e_cal_txdesc_chksum(desc)
-+#ifdef CONFIG_SDIO_HCI || defined(CONFIG_GSPI_HCI)
-+extern void rtl8192es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf);
-+#define fill_default_txdesc rtl8192es_fill_default_txdesc
-+#endif /* CONFIG_SDIO_HCI */
-+#endif /* CONFIG_RTL8192E */
-+
-+#if defined(CONFIG_RTL8192F)
-+/* extern void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc); */
-+#define cal_txdesc_chksum(padapter, desc) rtl8192f_cal_txdesc_chksum(desc)
-+/* extern void rtl8192f_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */
-+#define fill_default_txdesc rtl8192f_fill_default_txdesc
-+#endif /* CONFIG_RTL8192F */
-+
-+#ifdef CONFIG_RTL8723F
-+#include <../../hal/rtl8723f/rtl8723f.h>
-+
-+#define REG_LOOPBACK_ENABLE 0x0103
-+#define LOOKBACK_ENABLE_VALUE 0x0b
-+#define cal_txdesc_chksum(padapter, desc) rtl8723f_cal_txdesc_chksum(padapter, desc)
-+#define dump_txdesc_data(padapter, desc) rtl8723f_dbg_dump_tx_desc(padapter, DATA_FRAMETAG, desc);
-+#define get_rx_desc(rx_desc, rxbuf) rtl8723f_rxdesc2attribute(rx_desc, rxbuf)
-+#define hal_init rtl8723f_hal_init
-+#endif /* CONFIG_RTL8723F */
-+
-+void dbg_dump_pkt(char *s, u8 *buf, u8 len)
-+{
-+	u8 i, j = 1;
-+
-+	RTW_INFO("%s size = %u\n", s, len);
-+
-+	for (i = 0; (i + 4) < len; i += 4) {
-+		if (j % 4 == 1)
-+			RTW_PRINT("idx:%u:", i);
-+		_RTW_PRINT(" 0x%02x 0x%02x 0x%02x 0x%02x", buf[i], buf[i+1], buf[i+2], buf[i+3]);
-+		if ((j++) % 4 == 0)
-+			_RTW_PRINT("\n");
-+	}
-+
-+	for (; i < len ; i++) {
-+		_RTW_PRINT(" 0x%02x", buf[i]);
-+	}
-+	_RTW_PRINT("\n ================================\n");
-+}
-+
-+static s32 initLoopback(PADAPTER padapter)
-+{
-+	PLOOPBACKDATA ploopback;
-+
-+	if (padapter->ploopback == NULL) {
-+		ploopback = (PLOOPBACKDATA)rtw_zmalloc(sizeof(LOOPBACKDATA));
-+		if (ploopback == NULL)
-+			return -ENOMEM;
-+
-+		_rtw_init_sema(&ploopback->sema, 0);
-+		ploopback->bstop = _TRUE;
-+		ploopback->cnt = 0;
-+		ploopback->size = 300;
-+		_rtw_memset(ploopback->msg, 0, sizeof(ploopback->msg));
-+
-+		padapter->ploopback = ploopback;
-+	}
-+
-+	return 0;
-+}
-+
-+static void freeLoopback(PADAPTER padapter)
-+{
-+	PLOOPBACKDATA ploopback;
-+
-+	ploopback = padapter->ploopback;
-+	if (ploopback) {
-+		rtw_mfree((u8 *)ploopback, sizeof(LOOPBACKDATA));
-+		padapter->ploopback = NULL;
-+	}
-+}
-+
-+static s32 initpseudoadhoc(PADAPTER padapter)
-+{
-+	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType;
-+	s32 err;
-+
-+	networkType = Ndis802_11IBSS;
-+	err = rtw_set_802_11_infrastructure_mode(padapter, networkType, 0);
-+	if (err == _FALSE)
-+		return _FAIL;
-+
-+	err = rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK);
-+	if (err == _FAIL)
-+		return _FAIL;
-+
-+	return _SUCCESS;
-+}
-+
-+static s32 createpseudoadhoc(PADAPTER padapter)
-+{
-+	NDIS_802_11_AUTHENTICATION_MODE authmode;
-+	struct mlme_priv *pmlmepriv;
-+	NDIS_802_11_SSID *passoc_ssid;
-+	WLAN_BSSID_EX *pdev_network;
-+	u8 *pibss;
-+	u8 ssid[] = "pseduo_ad-hoc";
-+	s32 err;
-+	_irqL irqL;
-+
-+	pmlmepriv = &padapter->mlmepriv;
-+
-+	authmode = Ndis802_11AuthModeOpen;
-+	err = rtw_set_802_11_authentication_mode(padapter, authmode);
-+	if (err == _FALSE)
-+		return _FAIL;
-+
-+	passoc_ssid = &pmlmepriv->assoc_ssid;
-+	_rtw_memset(passoc_ssid, 0, sizeof(NDIS_802_11_SSID));
-+	passoc_ssid->SsidLength = sizeof(ssid) - 1;
-+	_rtw_memcpy(passoc_ssid->Ssid, ssid, passoc_ssid->SsidLength);
-+
-+	pdev_network = &padapter->registrypriv.dev_network;
-+	pibss = padapter->registrypriv.dev_network.MacAddress;
-+	_rtw_memcpy(&pdev_network->Ssid, passoc_ssid, sizeof(NDIS_802_11_SSID));
-+
-+	rtw_update_registrypriv_dev_network(padapter);
-+	rtw_generate_random_ibss(pibss);
-+
-+	_enter_critical_bh(&pmlmepriv->lock, &irqL);
-+	/*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/
-+	init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
-+
-+	_exit_critical_bh(&pmlmepriv->lock, &irqL);
-+
-+#if 0
-+	err = rtw_create_ibss_cmd(padapter, 0);
-+	if (err == _FAIL)
-+		return _FAIL;
-+#else
-+	{
-+		struct wlan_network *pcur_network;
-+		struct sta_info *psta;
-+
-+		/* 3  create a new psta */
-+		pcur_network = &pmlmepriv->cur_network;
-+
-+		/* clear psta in the cur_network, if any */
-+		psta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress);
-+		if (psta)
-+			rtw_free_stainfo(padapter, psta);
-+
-+		psta = rtw_alloc_stainfo(&padapter->stapriv, pibss);
-+		if (psta == NULL)
-+			return _FAIL;
-+
-+		/* 3  join psudo AdHoc */
-+		pcur_network->join_res = 1;
-+		pcur_network->aid = psta->cmn.aid = 1;
-+		_rtw_memcpy(&pcur_network->network, pdev_network, get_WLAN_BSSID_EX_sz(pdev_network));
-+
-+		/* set msr to WIFI_FW_ADHOC_STATE */
-+		padapter->hw_port = HW_PORT0;
-+		Set_MSR(padapter, WIFI_FW_ADHOC_STATE);
-+
-+	}
-+#endif
-+
-+	return _SUCCESS;
-+}
-+
-+static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size)
-+{
-+	struct xmit_priv *pxmitpriv;
-+	struct xmit_frame *pframe;
-+	struct xmit_buf *pxmitbuf;
-+	struct pkt_attrib *pattrib;
-+	struct tx_desc *desc;
-+	u8 *pkt_start, *pkt_end, *ptr;
-+	struct rtw_ieee80211_hdr *hdr;
-+	s32 bmcast;
-+	_irqL irqL;
-+
-+
-+	if ((TXDESC_SIZE + WLANHDR_OFFSET + size) > MAX_XMITBUF_SZ)
-+		return NULL;
-+
-+	pxmitpriv = &padapter->xmitpriv;
-+	pframe = NULL;
-+
-+	/* 2 1. allocate xmit frame */
-+	pframe = rtw_alloc_xmitframe(pxmitpriv, 0);
-+	if (pframe == NULL)
-+		return NULL;
-+	pframe->padapter = padapter;
-+
-+	/* 2 2. allocate xmit buffer */
-+	_enter_critical_bh(&pxmitpriv->lock, &irqL);
-+	pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
-+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
-+	if (pxmitbuf == NULL) {
-+		rtw_free_xmitframe(pxmitpriv, pframe);
-+		return NULL;
-+	}
-+
-+	pframe->pxmitbuf = pxmitbuf;
-+	pframe->buf_addr = pxmitbuf->pbuf;
-+	pxmitbuf->priv_data = pframe;
-+
-+	/* 2 3. update_attrib() */
-+	pattrib = &pframe->attrib;
-+
-+	/* init xmitframe attribute */
-+	_rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));
-+
-+	pattrib->ether_type = 0x8723;
-+	_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
-+	_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
-+	_rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
-+	_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
-+
-+	/*	pattrib->dhcp_pkt = 0;
-+	 *	pattrib->pktlen = 0; */
-+	pattrib->ack_policy = 0;
-+	/*	pattrib->pkt_hdrlen = ETH_HLEN; */
-+	pattrib->hdrlen = WLAN_HDR_A3_LEN;
-+	pattrib->subtype = WIFI_DATA;
-+	pattrib->priority = 0;
-+	pattrib->qsel = pattrib->priority;
-+	/*	do_queue_select(padapter, pattrib); */
-+	pattrib->nr_frags = 1;
-+	pattrib->encrypt = 0;
-+	pattrib->bswenc = _FALSE;
-+	pattrib->qos_en = _FALSE;
-+
-+	bmcast = IS_MCAST(pattrib->ra);
-+	if (bmcast)
-+		pattrib->psta = rtw_get_bcmc_stainfo(padapter);
-+	else
-+		pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
-+
-+	pattrib->mac_id = pattrib->psta->cmn.mac_id;
-+	pattrib->pktlen = size;
-+	pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
-+
-+	/* 2 4. fill TX descriptor */
-+	desc = (struct tx_desc *)pframe->buf_addr;
-+	_rtw_memset(desc, 0, TXDESC_SIZE);
-+
-+	fill_default_txdesc(pframe, (u8 *)desc);
-+
-+#if 0
-+	/* Hw set sequence number */
-+	((PTXDESC)desc)->hwseq_en = 0; /* HWSEQ_EN, 0:disable, 1:enable
-+ * ((PTXDESC)desc)->hwseq_sel = 0;  */ /* HWSEQ_SEL */
-+
-+	((PTXDESC)desc)->disdatafb = 1;
-+
-+	/* convert to little endian */
-+	desc->txdw0 = cpu_to_le32(desc->txdw0);
-+	desc->txdw1 = cpu_to_le32(desc->txdw1);
-+	desc->txdw2 = cpu_to_le32(desc->txdw2);
-+	desc->txdw3 = cpu_to_le32(desc->txdw3);
-+	desc->txdw4 = cpu_to_le32(desc->txdw4);
-+	desc->txdw5 = cpu_to_le32(desc->txdw5);
-+	desc->txdw6 = cpu_to_le32(desc->txdw6);
-+	desc->txdw7 = cpu_to_le32(desc->txdw7);
-+#ifdef CONFIG_PCI_HCI
-+	desc->txdw8 = cpu_to_le32(desc->txdw8);
-+	desc->txdw9 = cpu_to_le32(desc->txdw9);
-+	desc->txdw10 = cpu_to_le32(desc->txdw10);
-+	desc->txdw11 = cpu_to_le32(desc->txdw11);
-+	desc->txdw12 = cpu_to_le32(desc->txdw12);
-+	desc->txdw13 = cpu_to_le32(desc->txdw13);
-+	desc->txdw14 = cpu_to_le32(desc->txdw14);
-+	desc->txdw15 = cpu_to_le32(desc->txdw15);
-+#endif
-+#endif
-+
-+	cal_txdesc_chksum(padapter, (u8*)desc);
-+	/* dump_txdesc_data(padapter, (u8*)desc); */
-+
-+	/* 2 5. coalesce */
-+	pkt_start = pframe->buf_addr + TXDESC_SIZE;
-+	pkt_end = pkt_start + pattrib->last_txcmdsz;
-+
-+	/* 3 5.1. make wlan header, make_wlanhdr() */
-+	hdr = (struct rtw_ieee80211_hdr *)pkt_start;
-+	set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype);
-+	_rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */
-+	_rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */
-+	_rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */
-+
-+	/* 3 5.2. make payload */
-+	ptr = pkt_start + pattrib->hdrlen;
-+	get_random_bytes(ptr, pkt_end - ptr);
-+
-+	pxmitbuf->len = TXDESC_SIZE + pattrib->last_txcmdsz;
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	pxmitbuf->ptail += pxmitbuf->len;
-+#endif
-+
-+	dbg_dump_pkt("TX packet", pxmitbuf->pbuf, pxmitbuf->len);
-+
-+	return pframe;
-+}
-+
-+static void freeloopbackpkt(PADAPTER padapter, struct xmit_frame *pframe)
-+{
-+	struct xmit_priv *pxmitpriv;
-+	struct xmit_buf *pxmitbuf;
-+
-+	pxmitpriv = &padapter->xmitpriv;
-+	pxmitbuf = pframe->pxmitbuf;
-+
-+	rtw_free_xmitframe(pxmitpriv, pframe);
-+	rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
-+}
-+
-+static void printdata(u8 *pbuf, u32 len)
-+{
-+	u32 i, val;
-+
-+	for (i = 0; (i + 4) <= len; i += 4) {
-+		printk("%08X", *(u32 *)(pbuf + i));
-+		if ((i + 4) & 0x1F)
-+			printk(" ");
-+		else
-+			printk("\n");
-+	}
-+
-+	if (i < len) {
-+#ifdef CONFIG_BIG_ENDIAN
-+		for (; i < len, i++)
-+			printk("%02X", pbuf + i);
-+#else /* CONFIG_LITTLE_ENDIAN */
-+#if 0
-+		val = 0;
-+		_rtw_memcpy(&val, pbuf + i, len - i);
-+		printk("%8X", val);
-+#else
-+		u8 str[9];
-+		u8 n;
-+		val = 0;
-+		n = len - i;
-+		_rtw_memcpy(&val, pbuf + i, n);
-+		sprintf(str, "%08X", val);
-+		n = (4 - n) * 2;
-+		printk("%8s", str + n);
-+#endif
-+#endif /* CONFIG_LITTLE_ENDIAN */
-+	}
-+	printk("\n");
-+}
-+
-+static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz)
-+{
-+	struct rx_pkt_attrib rx_desc;
-+#if 0
-+	struct recv_stat *prxstat;
-+	struct recv_stat report;
-+	PRXREPORT prxreport;
-+#endif
-+	u32 rxpktsize;
-+	u8 drvinfosize;
-+	u8 shiftsize;
-+	u8 ret = _FALSE;
-+	u8 skip_len = 4; /* Don't compare the frame control and duration field */
-+	get_rx_desc(&rx_desc, rxbuf);
-+	rxpktsize = rx_desc.pkt_len;
-+	drvinfosize = rx_desc.drvinfo_sz;
-+	shiftsize = rx_desc.shift_sz;
-+
-+#if 0
-+	prxstat = (struct recv_stat *)rxbuf;
-+	report.rxdw0 = le32_to_cpu(prxstat->rxdw0);
-+	report.rxdw1 = le32_to_cpu(prxstat->rxdw1);
-+	report.rxdw2 = le32_to_cpu(prxstat->rxdw2);
-+	report.rxdw3 = le32_to_cpu(prxstat->rxdw3);
-+	report.rxdw4 = le32_to_cpu(prxstat->rxdw4);
-+	report.rxdw5 = le32_to_cpu(prxstat->rxdw5);
-+
-+	prxreport = (PRXREPORT)&report;
-+	drvinfosize = prxreport->drvinfosize << 3;
-+	rxpktsize = prxreport->pktlen;
-+#endif
-+
-+	if (rtw_hal_rcr_check(padapter, RCR_APPFCS))
-+		rxpktsize -= IEEE80211_FCS_LEN;
-+
-+	if ((txsz - TXDESC_SIZE) != rxpktsize) {
-+		RTW_INFO("%s: ERROR! size not match tx/rx=%d/%d !\n",
-+			 __func__, txsz - TXDESC_SIZE, rxpktsize);
-+		ret = _FALSE;
-+	} else {
-+		ret = _rtw_memcmp(txbuf + TXDESC_SIZE + skip_len, \
-+				  rxbuf + RXDESC_SIZE + skip_len + drvinfosize, \
-+				  txsz - TXDESC_SIZE - skip_len);
-+		if (ret == _FALSE)
-+			RTW_INFO("%s: ERROR! pkt content mismatch!\n", __func__);
-+	}
-+
-+	if (ret == _FALSE) {
-+		RTW_INFO("\n%s: TX PKT total=%d, desc=%d, content=%d\n",
-+			 __func__, txsz, TXDESC_SIZE, txsz - TXDESC_SIZE);
-+		dbg_dump_pkt("TX DESC", txbuf, TXDESC_SIZE);
-+		dbg_dump_pkt("TX content", txbuf + TXDESC_SIZE, txsz - TXDESC_SIZE);
-+
-+		RTW_INFO("\n%s: RX PKT read=%d offset=%d(%d,%d) content=%d\n",
-+			__func__, rxsz, RXDESC_SIZE + drvinfosize, RXDESC_SIZE, drvinfosize, rxpktsize);
-+		if (rxpktsize != 0) {
-+			dbg_dump_pkt("RX DESC", rxbuf, RXDESC_SIZE);
-+			dbg_dump_pkt("RX drvinfo", rxbuf + RXDESC_SIZE, drvinfosize);
-+			dbg_dump_pkt("RX packet content", rxbuf + RXDESC_SIZE + drvinfosize, rxpktsize);
-+		} else {
-+			RTW_INFO("%s: RX data size=%d\n", __func__, rxsz);
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+thread_return lbk_thread(thread_context context)
-+{
-+	s32 err;
-+	PADAPTER padapter;
-+	PLOOPBACKDATA ploopback;
-+	struct xmit_frame *pxmitframe;
-+	u32 cnt, ok, fail, headerlen;
-+	u32 pktsize;
-+	u32 ff_hwaddr;
-+
-+	padapter = (PADAPTER)context;
-+	ploopback = padapter->ploopback;
-+	if (ploopback == NULL)
-+		return -1;
-+	cnt = 0;
-+	ok = 0;
-+	fail = 0;
-+
-+	thread_enter("RTW_LBK_THREAD");
-+	/* daemonize("%s", "RTW_LBK_THREAD"); */
-+	allow_signal(SIGTERM);
-+
-+	do {
-+		if (ploopback->size == 0) {
-+			get_random_bytes(&pktsize, 4);
-+			pktsize = (pktsize % 1535) + 1; /* 1~1535 */
-+		} else
-+			pktsize = ploopback->size;
-+
-+		pxmitframe = createloopbackpkt(padapter, pktsize);
-+		if (pxmitframe == NULL) {
-+			sprintf(ploopback->msg, "loopback FAIL! 3. create Packet FAIL!");
-+			break;
-+		}
-+
-+		ploopback->txsize = TXDESC_SIZE + pxmitframe->attrib.last_txcmdsz;
-+		_rtw_memcpy(ploopback->txbuf, pxmitframe->buf_addr, ploopback->txsize);
-+		ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
-+		cnt++;
-+		RTW_INFO("%s: wirte port cnt=%d size=%d\n", __func__, cnt, ploopback->txsize);
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+		pxmitframe->pxmitbuf->pdata = ploopback->txbuf;
-+#endif
-+		rtw_write_port(padapter, ff_hwaddr, ploopback->txsize, (u8 *)pxmitframe->pxmitbuf);
-+
-+		/* wait for rx pkt */
-+		RTW_INFO("%s: wait for rx packet\n", __func__);
-+		_rtw_down_sema(&ploopback->sema);
-+
-+		err = pktcmp(padapter, ploopback->txbuf, ploopback->txsize, ploopback->rxbuf, ploopback->rxsize);
-+		if (err == _TRUE)
-+			ok++;
-+		else
-+			fail++;
-+
-+		ploopback->txsize = 0;
-+		_rtw_memset(ploopback->txbuf, 0, 0x8000);
-+		ploopback->rxsize = 0;
-+		_rtw_memset(ploopback->rxbuf, 0, 0x8000);
-+
-+		freeloopbackpkt(padapter, pxmitframe);
-+		pxmitframe = NULL;
-+
-+		flush_signals_thread();
-+
-+		if ((ploopback->bstop == _TRUE) ||
-+		    ((ploopback->cnt != 0) && (ploopback->cnt == cnt))) {
-+			u32 ok_rate, fail_rate, all;
-+			all = cnt;
-+			ok_rate = (ok * 100) / all;
-+			fail_rate = (fail * 100) / all;
-+			sprintf(ploopback->msg, \
-+				"loopback result: ok=%d%%(%d/%d),error=%d%%(%d/%d)", \
-+				ok_rate, ok, all, fail_rate, fail, all);
-+			break;
-+		}
-+	} while (1);
-+
-+	ploopback->bstop = _TRUE;
-+
-+	thread_exit(NULL);
-+	return 0;
-+}
-+
-+static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8 *pmsg)
-+{
-+	PLOOPBACKDATA ploopback;
-+	u32 len;
-+	s32 err;
-+
-+	ploopback = padapter->ploopback;
-+
-+	if (ploopback) {
-+		if (ploopback->bstop == _FALSE) {
-+			ploopback->bstop = _TRUE;
-+			_rtw_up_sema(&ploopback->sema);
-+		}
-+		len = 0;
-+		do {
-+			len = strlen(ploopback->msg);
-+			if (len)
-+				break;
-+			rtw_msleep_os(1);
-+		} while (1);
-+		RTW_INFO("Free loopback, end the test.\n");
-+		_rtw_memcpy(pmsg, ploopback->msg, len + 1);
-+		freeLoopback(padapter);
-+
-+		return;
-+	}
-+
-+	/* disable dynamic algorithm	 */
-+#ifndef CONFIG_NO_PHYDM
-+	rtw_phydm_ability_backup(padapter);
-+	rtw_phydm_func_disable_all(padapter);
-+#endif
-+
-+	/* create pseudo ad-hoc connection */
-+	err = initpseudoadhoc(padapter);
-+	if (err == _FAIL) {
-+		sprintf(pmsg, "loopback FAIL! 1.1 init ad-hoc FAIL!");
-+		return;
-+	}
-+
-+	err = createpseudoadhoc(padapter);
-+	if (err == _FAIL) {
-+		sprintf(pmsg, "loopback FAIL! 1.2 create ad-hoc master FAIL!");
-+		return;
-+	}
-+
-+	err = initLoopback(padapter);
-+	if (err) {
-+		sprintf(pmsg, "loopback FAIL! 2. init FAIL! error code=%d", err);
-+		return;
-+	}
-+
-+	ploopback = padapter->ploopback;
-+
-+	ploopback->bstop = _FALSE;
-+	ploopback->cnt = cnt;
-+	ploopback->size = size;
-+	ploopback->lbkthread = kthread_run(lbk_thread, padapter, "RTW_LBK_THREAD");
-+	if (IS_ERR(ploopback->lbkthread)) {
-+		freeLoopback(padapter);
-+		ploopback->lbkthread = NULL;
-+		sprintf(pmsg, "loopback start FAIL! cnt=%d", cnt);
-+		return;
-+	}
-+
-+	sprintf(pmsg, "loopback start! cnt=%d", cnt);
-+}
-+#endif /* CONFIG_MAC_LOOPBACK_DRIVER */
-+
-+static int rtw_test(
-+	struct net_device *dev,
-+	struct iw_request_info *info,
-+	union iwreq_data *wrqu, char *extra)
-+{
-+	u32 len;
-+	u8 *pbuf, *pch;
-+	char *ptmp;
-+	u8 *delim = ",";
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+
-+
-+	RTW_INFO("+%s\n", __func__);
-+	len = wrqu->data.length;
-+
-+	pbuf = (u8 *)rtw_zmalloc(len + 1);
-+	if (pbuf == NULL) {
-+		RTW_INFO("%s: no memory!\n", __func__);
-+		return -ENOMEM;
-+	}
-+
-+	if (copy_from_user(pbuf, wrqu->data.pointer, len)) {
-+		rtw_mfree(pbuf, len + 1);
-+		RTW_INFO("%s: copy from user fail!\n", __func__);
-+		return -EFAULT;
-+	}
-+
-+	pbuf[len] = '\0';
-+
-+	RTW_INFO("%s: string=\"%s\"\n", __func__, pbuf);
-+
-+	ptmp = (char *)pbuf;
-+	pch = strsep(&ptmp, delim);
-+	if ((pch == NULL) || (strlen(pch) == 0)) {
-+		rtw_mfree(pbuf, len);
-+		RTW_INFO("%s: parameter error(level 1)!\n", __func__);
-+		return -EFAULT;
-+	}
-+
-+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
-+	if (strcmp(pch, "init") == 0) {
-+		u8 status;
-+
-+		rtw_clr_drv_stopped(padapter); /* should clear drv_stopped, otherwise driver can't trx */
-+
-+		status = hal_init(padapter);
-+		RTW_INFO("HAL_INIT %s\n", status ? "SUCCESS" : "FAIL");
-+
-+		rtw_write8(padapter, REG_LOOPBACK_ENABLE, LOOKBACK_ENABLE_VALUE);
-+		RTW_INFO("Write 0x%03x to 0x%02x, enable loopback\n",
-+			REG_LOOPBACK_ENABLE, LOOKBACK_ENABLE_VALUE);
-+
-+	} else if (strcmp(pch, "loopback") == 0) {
-+		s32 cnt = 0;
-+		u32 size = 64;
-+
-+		pch = strsep(&ptmp, delim);
-+		if ((pch == NULL) || (strlen(pch) == 0)) {
-+			rtw_mfree(pbuf, len);
-+			RTW_INFO("%s: parameter error(level 2)!\n", __func__);
-+			return -EFAULT;
-+		}
-+
-+		sscanf(pch, "%d", &cnt);
-+		RTW_INFO("%s: loopback cnt=%d\n", __func__, cnt);
-+
-+		pch = strsep(&ptmp, delim);
-+		if ((pch == NULL) || (strlen(pch) == 0)) {
-+			rtw_mfree(pbuf, len);
-+			RTW_INFO("%s: parameter error(level 2)!\n", __func__);
-+			return -EFAULT;
-+		}
-+
-+		sscanf(pch, "%d", &size);
-+		RTW_INFO("%s: loopback size=%d\n", __func__, size);
-+
-+		loopbackTest(padapter, cnt, size, extra);
-+		wrqu->data.length = strlen(extra) + 1;
-+
-+		goto free_buf;
-+	}
-+#endif
-+
-+
-+#ifdef CONFIG_BT_COEXIST
-+	if (strcmp(pch, "bton") == 0) {
-+		rtw_btcoex_SetManualControl(padapter, _FALSE);
-+		goto free_buf;
-+	} else if (strcmp(pch, "btoff") == 0) {
-+		rtw_btcoex_SetManualControl(padapter, _TRUE);
-+		goto free_buf;
-+	} else if (strcmp(pch, "coex_auto") == 0) {
-+		rtw_btcoex_set_policy_control(padapter, BTCOEX_POLICY_CONTROL_AUTO);
-+		goto free_buf;
-+	} else if (strcmp(pch, "coex_force_freerun") == 0) {
-+		rtw_btcoex_set_policy_control(padapter, BTCOEX_POLICY_CONTROL_FORCE_FREERUN);
-+		goto free_buf;
-+	} else if (strcmp(pch, "coex_force_tdma") == 0) {
-+		rtw_btcoex_set_policy_control(padapter, BTCOEX_POLICY_CONTROL_FORCE_TDMA);
-+		goto free_buf;
-+	}
-+#endif
-+
-+	if (strcmp(pch, "h2c") == 0) {
-+		u8 param[8];
-+		u8 count = 0;
-+		u32 tmp;
-+		u8 i;
-+		u32 pos;
-+		u8 ret;
-+
-+		do {
-+			pch = strsep(&ptmp, delim);
-+			if ((pch == NULL) || (strlen(pch) == 0))
-+				break;
-+
-+			sscanf(pch, "%x", &tmp);
-+			param[count++] = (u8)tmp;
-+		} while (count < 8);
-+
-+		if (count == 0) {
-+			rtw_mfree(pbuf, len);
-+			RTW_INFO("%s: parameter error(level 2)!\n", __func__);
-+			return -EFAULT;
-+		}
-+
-+		ret = rtw_test_h2c_cmd(padapter, param, count);
-+
-+		pos = sprintf(extra, "H2C ID=0x%02x content=", param[0]);
-+		for (i = 1; i < count; i++)
-+			pos += sprintf(extra + pos, "%02x,", param[i]);
-+		extra[pos] = 0;
-+		pos--;
-+		pos += sprintf(extra + pos, " %s", ret == _FAIL ? "FAIL" : "OK");
-+
-+		wrqu->data.length = strlen(extra) + 1;
-+
-+		goto free_buf;
-+	}
-+
-+	if (strcmp(pch, "dump_mac_reg") == 0) {
-+		mac_reg_dump(RTW_DBGDUMP, padapter);
-+		goto free_buf;
-+	}
-+
-+free_buf:
-+	rtw_mfree(pbuf, len);
-+	return 0;
-+}
-+
-+static iw_handler rtw_handlers[] = {
-+#ifdef CONFIG_IOCTL_WEXT
-+	NULL,					/* SIOCSIWCOMMIT */
-+	rtw_wx_get_name,		/* SIOCGIWNAME */
-+	dummy,					/* SIOCSIWNWID */
-+	dummy,					/* SIOCGIWNWID */
-+	rtw_wx_set_freq,		/* SIOCSIWFREQ */
-+	rtw_wx_get_freq,		/* SIOCGIWFREQ */
-+	rtw_wx_set_mode,		/* SIOCSIWMODE */
-+	rtw_wx_get_mode,		/* SIOCGIWMODE */
-+	dummy,					/* SIOCSIWSENS */
-+	rtw_wx_get_sens,		/* SIOCGIWSENS */
-+	NULL,					/* SIOCSIWRANGE */
-+	rtw_wx_get_range,		/* SIOCGIWRANGE */
-+	rtw_wx_set_priv,		/* SIOCSIWPRIV */
-+	NULL,					/* SIOCGIWPRIV */
-+	NULL,					/* SIOCSIWSTATS */
-+	NULL,					/* SIOCGIWSTATS */
-+	dummy,					/* SIOCSIWSPY */
-+	dummy,					/* SIOCGIWSPY */
-+	NULL,					/* SIOCGIWTHRSPY */
-+	NULL,					/* SIOCWIWTHRSPY */
-+	rtw_wx_set_wap,		/* SIOCSIWAP */
-+	rtw_wx_get_wap,		/* SIOCGIWAP */
-+	rtw_wx_set_mlme,		/* request MLME operation; uses struct iw_mlme */
-+	dummy,					/* SIOCGIWAPLIST -- depricated */
-+	rtw_wx_set_scan,		/* SIOCSIWSCAN */
-+	rtw_wx_get_scan,		/* SIOCGIWSCAN */
-+	rtw_wx_set_essid,		/* SIOCSIWESSID */
-+	rtw_wx_get_essid,		/* SIOCGIWESSID */
-+	dummy,					/* SIOCSIWNICKN */
-+	rtw_wx_get_nick,		/* SIOCGIWNICKN */
-+	NULL,					/* -- hole -- */
-+	NULL,					/* -- hole -- */
-+	rtw_wx_set_rate,		/* SIOCSIWRATE */
-+	rtw_wx_get_rate,		/* SIOCGIWRATE */
-+	rtw_wx_set_rts,			/* SIOCSIWRTS */
-+	rtw_wx_get_rts,			/* SIOCGIWRTS */
-+	rtw_wx_set_frag,		/* SIOCSIWFRAG */
-+	rtw_wx_get_frag,		/* SIOCGIWFRAG */
-+	dummy,					/* SIOCSIWTXPOW */
-+	dummy,					/* SIOCGIWTXPOW */
-+	dummy,					/* SIOCSIWRETRY */
-+	rtw_wx_get_retry,		/* SIOCGIWRETRY */
-+	rtw_wx_set_enc,			/* SIOCSIWENCODE */
-+	rtw_wx_get_enc,			/* SIOCGIWENCODE */
-+	dummy,					/* SIOCSIWPOWER */
-+	rtw_wx_get_power,		/* SIOCGIWPOWER */
-+	NULL,					/*---hole---*/
-+	NULL,					/*---hole---*/
-+	rtw_wx_set_gen_ie,		/* SIOCSIWGENIE */
-+	NULL,					/* SIOCGWGENIE */
-+	rtw_wx_set_auth,		/* SIOCSIWAUTH */
-+	NULL,					/* SIOCGIWAUTH */
-+	rtw_wx_set_enc_ext,		/* SIOCSIWENCODEEXT */
-+	NULL,					/* SIOCGIWENCODEEXT */
-+	rtw_wx_set_pmkid,		/* SIOCSIWPMKSA */
-+	NULL,					/*---hole---*/
-+#endif
-+};
-+
-+
-+static const struct iw_priv_args rtw_private_args[] = {
-+	{
-+		SIOCIWFIRSTPRIV + 0x0,
-+		IW_PRIV_TYPE_CHAR | 0x7FF, 0, "write"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0x1,
-+		IW_PRIV_TYPE_CHAR | 0x7FF,
-+		IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "read"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0x2, 0, 0, "driver_ext"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0x3, 0, 0, "mp_ioctl"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0x4,
-+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "apinfo"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0x5,
-+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "setpid"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0x6,
-+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_start"
-+	},
-+	/* for PLATFORM_MT53XX	 */
-+	{
-+		SIOCIWFIRSTPRIV + 0x7,
-+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "get_sensitivity"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0x8,
-+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_prob_req_ie"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0x9,
-+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_assoc_req_ie"
-+	},
-+
-+	/* for RTK_DMP_PLATFORM	 */
-+	{
-+		SIOCIWFIRSTPRIV + 0xA,
-+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "channel_plan"
-+	},
-+
-+	{
-+		SIOCIWFIRSTPRIV + 0xB,
-+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "dbg"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0xC,
-+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3, 0, "rfw"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0xD,
-+		IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "rfr"
-+	},
-+#if 0
-+	{
-+		SIOCIWFIRSTPRIV + 0xE, 0, 0, "wowlan_ctrl"
-+	},
-+#endif
-+	{
-+		SIOCIWFIRSTPRIV + 0x10,
-+		IW_PRIV_TYPE_CHAR | 1024, 0, "p2p_set"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0x11,
-+		IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "p2p_get"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0x12, 0, 0, "NULL"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0x13,
-+		IW_PRIV_TYPE_CHAR | 64, IW_PRIV_TYPE_CHAR | 64 , "p2p_get2"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0x14,
-+		IW_PRIV_TYPE_CHAR  | 64, 0, "tdls"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0x15,
-+		IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | 1024 , "tdls_get"
-+	},
-+	{
-+		SIOCIWFIRSTPRIV + 0x16,
-+		IW_PRIV_TYPE_CHAR | 64, 0, "pm_set"
-+	},
-+#ifdef CONFIG_RTW_80211K
-+	{
-+		SIOCIWFIRSTPRIV + 0x17,
-+		IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | 1024 , "rrm"
-+	},
-+#else
-+	{SIOCIWFIRSTPRIV + 0x17, IW_PRIV_TYPE_CHAR | 1024 , 0 , "NULL"},
-+#endif
-+
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+	{SIOCIWFIRSTPRIV + 0x18, IW_PRIV_TYPE_CHAR | 1024 , 0 , "cmap_intfs"},
-+#else
-+	{SIOCIWFIRSTPRIV + 0x18, 0, 0, "NULL"},
-+#endif
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	{SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0,  "NULL"},
-+	{SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "NULL"},
-+#else
-+	{SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0,  "NULL"},
-+	{SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get"},
-+#endif
-+	{
-+		SIOCIWFIRSTPRIV + 0x1D,
-+		IW_PRIV_TYPE_CHAR | 40, IW_PRIV_TYPE_CHAR | 0x7FF, "test"
-+	},
-+
-+	{ SIOCIWFIRSTPRIV + 0x0E, IW_PRIV_TYPE_CHAR | 1024, 0 , ""},  /* set  */
-+	{ SIOCIWFIRSTPRIV + 0x0F, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , ""},/* get
-+ * --- sub-ioctls definitions --- */
-+
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+	{ VENDOR_IE_SET, IW_PRIV_TYPE_CHAR | 1024 , 0 , "vendor_ie_set" },
-+	{ VENDOR_IE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "vendor_ie_get" },
-+#endif
-+#if defined(CONFIG_RTL8723B)
-+	{ MP_SetBT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setbt" },
-+	{ MP_DISABLE_BT_COEXIST, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_disa_btcoex"},
-+#endif
-+#ifdef CONFIG_WOWLAN
-+	{ MP_WOW_ENABLE , IW_PRIV_TYPE_CHAR | 1024, 0, "wow_mode" },
-+	{ MP_WOW_SET_PATTERN , IW_PRIV_TYPE_CHAR | 1024, 0, "wow_set_pattern" },
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+	{ MP_WOW_SET_KEEP_ALIVE_PATTERN ,IW_PRIV_TYPE_CHAR | 1024 , 0 , "wow_keep_alive"},
-+#endif /* defined (CONFIG_KEEP_ALIVE_PATTERN)*/
-+#endif
-+
-+#ifdef CONFIG_AP_WOWLAN
-+	{ MP_AP_WOW_ENABLE , IW_PRIV_TYPE_CHAR | 1024, 0, "ap_wow_mode" }, /* set  */
-+#endif
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+	{ MP_SD_IREAD, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "sd_iread" },
-+	{ MP_SD_IWRITE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "sd_iwrite" },
-+#endif
-+};
-+
-+
-+static const struct iw_priv_args rtw_mp_private_args[] = {
-+	/* --- sub-ioctls definitions --- */
-+#ifdef CONFIG_MP_INCLUDED
-+	{ MP_START , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_start" },
-+	{ MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" },
-+	{ MP_STOP , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_stop" },
-+	{ MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" },
-+	{ MP_CHL_OFFSET , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ch_offset" },
-+	{ MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_bandwidth"},
-+	{ MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" },
-+	{ MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_reset_stats"},
-+	{ MP_QUERY , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "mp_query"},
-+	{ READ_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_reg" },
-+	{ MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" },
-+	{ READ_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_rf" },
-+	{ MP_PSD , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_psd"},
-+	{ MP_DUMP, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dump" },
-+	{ MP_TXPOWER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_txpower"},
-+	{ MP_ANT_TX , IW_PRIV_TYPE_CHAR | 1024,  IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_tx"},
-+	{ MP_ANT_RX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_rx"},
-+	{ WRITE_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_reg" },
-+	{ WRITE_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_rf" },
-+	{ MP_CTX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ctx"},
-+	{ MP_ARX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_arx"},
-+	{ MP_THER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ther"},
-+	{ EFUSE_SET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_set" },
-+	{ EFUSE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get" },
-+	{ MP_PWRTRK , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrtrk"},
-+	{ MP_QueryDrvStats, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_drvquery" },
-+	{ MP_IOCTL, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_ioctl"},
-+	{ MP_SetRFPathSwh, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setrfpath" },
-+	{ MP_PwrCtlDM, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrctldm" },
-+	{ MP_GET_TXPOWER_INX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_get_txpower" },
-+	{ MP_GETVER, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_priv_ver" },
-+	{ MP_MON, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_mon" },
-+	{ EFUSE_BT_MASK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_bt_mask" },
-+	{ EFUSE_MASK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_mask" },
-+	{ EFUSE_FILE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_file" },
-+	{ EFUSE_FILE_STORE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_store" },
-+	{ MP_TX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_tx" },
-+	{ MP_RX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rx" },
-+	{ MP_HW_TX_MODE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_hxtx" },
-+	{ MP_PWRLMT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrlmt" },
-+	{ MP_PWRBYRATE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrbyrate" },
-+	{ CTA_TEST, IW_PRIV_TYPE_CHAR | 1024, 0, "cta_test"},
-+	{ MP_IQK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_iqk"},
-+	{ MP_LCK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_lck"},
-+	{ BT_EFUSE_FILE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "bt_efuse_file" },
-+	{ MP_SWRFPath, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_swrfpath" },
-+	{ MP_LINK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_link" },
-+	{ MP_DPK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dpk"},
-+	{ MP_DPK_TRK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dpk_trk" },
-+	{ MP_GET_TSSIDE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_get_tsside" },
-+	{ MP_SET_TSSIDE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_set_tsside" },
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+	{ MP_CUSTOMER_STR, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "customer_str" },
-+#endif
-+
-+#endif /* CONFIG_MP_INCLUDED */
-+};
-+
-+static iw_handler rtw_private_handler[] = {
-+	rtw_wx_write32,					/* 0x00 */
-+	rtw_wx_read32,					/* 0x01 */
-+	NULL,					/* 0x02 */
-+#ifdef MP_IOCTL_HDL
-+	rtw_mp_ioctl_hdl,				/* 0x03 */
-+#else
-+	rtw_wx_priv_null,
-+#endif
-+	/* for MM DTV platform */
-+	rtw_get_ap_info,					/* 0x04 */
-+
-+	rtw_set_pid,						/* 0x05 */
-+	rtw_wps_start,					/* 0x06 */
-+
-+	/* for PLATFORM_MT53XX */
-+	rtw_wx_get_sensitivity,			/* 0x07 */
-+	rtw_wx_set_mtk_wps_probe_ie,	/* 0x08 */
-+	rtw_wx_set_mtk_wps_ie,			/* 0x09 */
-+
-+	/* for RTK_DMP_PLATFORM
-+	 * Set Channel depend on the country code */
-+	rtw_wx_set_channel_plan,		/* 0x0A */
-+
-+	rtw_dbg_port,					/* 0x0B */
-+	rtw_wx_write_rf,					/* 0x0C */
-+	rtw_wx_read_rf,					/* 0x0D */
-+
-+	rtw_priv_set,					/*0x0E*/
-+	rtw_priv_get,					/*0x0F*/
-+
-+	rtw_p2p_set,					/* 0x10 */
-+	rtw_p2p_get,					/* 0x11 */
-+	NULL,							/* 0x12 */
-+	rtw_p2p_get2,					/* 0x13 */
-+
-+	rtw_tdls,						/* 0x14 */
-+	rtw_tdls_get,					/* 0x15 */
-+
-+	rtw_pm_set,						/* 0x16 */
-+#ifdef CONFIG_RTW_80211K
-+	rtw_wx_priv_rrm,				/* 0x17 */
-+#else
-+	rtw_wx_priv_null,				/* 0x17 */
-+#endif
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+	cmap_intfs_ioctl,				/* 0x18 */
-+#else
-+	NULL,							/* 0x18 */
-+#endif
-+	rtw_wx_priv_null,				/* 0x19 */
-+#ifdef CONFIG_MP_INCLUDED
-+	rtw_wx_priv_null,				/* 0x1A */
-+	rtw_wx_priv_null,				/* 0x1B */
-+#else
-+	rtw_wx_priv_null,				/* 0x1A */
-+	rtw_mp_efuse_get,				/* 0x1B */
-+#endif
-+	NULL,							/* 0x1C is reserved for hostapd */
-+	rtw_test,						/* 0x1D */
-+};
-+
-+#ifdef CONFIG_WIRELESS_EXT
-+#if WIRELESS_EXT >= 17
-+static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct iw_statistics *piwstats = &padapter->iwstats;
-+	int tmp_level = 0;
-+	int tmp_qual = 0;
-+	int tmp_noise = 0;
-+
-+	if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) != _TRUE) {
-+		piwstats->qual.qual = 0;
-+		piwstats->qual.level = 0;
-+		piwstats->qual.noise = 0;
-+		/* RTW_INFO("No link  level:%d, qual:%d, noise:%d\n", tmp_level, tmp_qual, tmp_noise); */
-+	} else {
-+#ifdef CONFIG_SIGNAL_DISPLAY_DBM
-+		tmp_level = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);
-+#else
-+		tmp_level = padapter->recvpriv.signal_strength;
-+#endif
-+
-+		tmp_qual = padapter->recvpriv.signal_qual;
-+		#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+		if (IS_NM_ENABLE(padapter)) {
-+			tmp_noise = rtw_noise_measure_curchan(padapter);
-+			#ifndef CONFIG_SIGNAL_DISPLAY_DBM
-+			tmp_noise = translate_dbm_to_percentage(tmp_noise);/*percentage*/
-+			#endif
-+		}
-+		#endif
-+		/* RTW_INFO("level:%d, qual:%d, noise:%d, rssi (%d)\n", tmp_level, tmp_qual, tmp_noise,padapter->recvpriv.rssi); */
-+
-+		piwstats->qual.level = tmp_level;
-+		piwstats->qual.qual = tmp_qual;
-+		piwstats->qual.noise = tmp_noise;
-+	}
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 14))
-+	piwstats->qual.updated = IW_QUAL_ALL_UPDATED ;/* |IW_QUAL_DBM; */
-+#else
-+#ifdef RTK_DMP_PLATFORM
-+	/* IW_QUAL_DBM= 0x8, if driver use this flag, wireless extension will show value of dbm. */
-+	/* remove this flag for show percentage 0~100 */
-+	piwstats->qual.updated = 0x07;
-+#else
-+	piwstats->qual.updated = 0x0f;
-+#endif
-+#endif
-+
-+#ifdef CONFIG_SIGNAL_DISPLAY_DBM
-+	piwstats->qual.updated = piwstats->qual.updated | IW_QUAL_DBM;
-+#endif
-+
-+	return &padapter->iwstats;
-+}
-+#endif
-+
-+struct iw_handler_def rtw_handlers_def = {
-+	.standard = rtw_handlers,
-+	.num_standard = sizeof(rtw_handlers) / sizeof(iw_handler),
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33)) || defined(CONFIG_WEXT_PRIV)
-+	.private = rtw_private_handler,
-+	.private_args = (struct iw_priv_args *)rtw_private_args,
-+	.num_private = sizeof(rtw_private_handler) / sizeof(iw_handler),
-+	.num_private_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args),
-+#endif
-+#if WIRELESS_EXT >= 17
-+	.get_wireless_stats = rtw_get_wireless_stats,
-+#endif
-+};
-+#endif
-+
-+/* copy from net/wireless/wext.c start
-+ * ----------------------------------------------------------------
-+ *
-+ * Calculate size of private arguments
-+ */
-+static const char iw_priv_type_size[] = {
-+	0,                              /* IW_PRIV_TYPE_NONE */
-+	1,                              /* IW_PRIV_TYPE_BYTE */
-+	1,                              /* IW_PRIV_TYPE_CHAR */
-+	0,                              /* Not defined */
-+	sizeof(__u32),                  /* IW_PRIV_TYPE_INT */
-+	sizeof(struct iw_freq),         /* IW_PRIV_TYPE_FLOAT */
-+	sizeof(struct sockaddr),        /* IW_PRIV_TYPE_ADDR */
-+	0,                              /* Not defined */
-+};
-+
-+static int get_priv_size(__u16 args)
-+{
-+	int num = args & IW_PRIV_SIZE_MASK;
-+	int type = (args & IW_PRIV_TYPE_MASK) >> 12;
-+
-+	return num * iw_priv_type_size[type];
-+}
-+/* copy from net/wireless/wext.c end */
-+
-+
-+static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq_data)
-+{
-+	int err = 0;
-+	u8 *input = NULL;
-+	u32 input_len = 0;
-+	const char delim[] = " ";
-+	u8 *output = NULL;
-+	u32 output_len = 0;
-+	u32 count = 0;
-+	u8 *buffer = NULL;
-+	u32 buffer_len = 0;
-+	char *ptr = NULL;
-+	u8 cmdname[17] = {0}; /* IFNAMSIZ+1 */
-+	u32 cmdlen;
-+	s32 len;
-+	u8 *extra = NULL;
-+	u32 extra_size = 0;
-+
-+	s32 k;
-+	const iw_handler *priv;		/* Private ioctl */
-+	const struct iw_priv_args *priv_args;	/* Private ioctl description */
-+	const struct iw_priv_args *mp_priv_args;	/*MP Private ioctl description */
-+	const struct iw_priv_args *sel_priv_args;	/*Selected Private ioctl description */
-+	u32 num_priv;				/* Number of ioctl */
-+	u32 num_priv_args;			/* Number of descriptions */
-+	u32 num_mp_priv_args;			/*Number of MP descriptions */
-+	u32 num_sel_priv_args;			/*Number of Selected descriptions */
-+	iw_handler handler;
-+	int temp;
-+	int subcmd = 0;				/* sub-ioctl index */
-+	int offset = 0;				/* Space for sub-ioctl index */
-+
-+	union iwreq_data wdata;
-+
-+	_rtw_memcpy(&wdata, wrq_data, sizeof(wdata));
-+
-+	input_len = wdata.data.length;
-+	if (!input_len)
-+		return -EINVAL;
-+	input = rtw_zmalloc(input_len);
-+
-+	if (input == NULL) {
-+		err = -EOPNOTSUPP;
-+		goto exit;
-+	}
-+
-+	if (copy_from_user(input, wdata.data.pointer, input_len)) {
-+		err = -EFAULT;
-+		goto exit;
-+	}
-+	input[input_len - 1] = '\0';
-+	ptr = input;
-+	len = input_len;
-+
-+	sscanf(ptr, "%16s", cmdname);
-+	cmdlen = strlen(cmdname);
-+	RTW_DBG("%s: cmd=%s\n", __func__, cmdname);
-+
-+	/* skip command string */
-+	if (cmdlen > 0)
-+		cmdlen += 1; /* skip one space */
-+	ptr += cmdlen;
-+	len -= cmdlen;
-+	RTW_DBG("%s: parameters=%s\n", __func__, ptr);
-+
-+	priv = rtw_private_handler;
-+	priv_args = rtw_private_args;
-+	mp_priv_args = rtw_mp_private_args;
-+	num_priv = sizeof(rtw_private_handler) / sizeof(iw_handler);
-+	num_priv_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args);
-+	num_mp_priv_args = sizeof(rtw_mp_private_args) / sizeof(struct iw_priv_args);
-+
-+	if (num_priv_args == 0) {
-+		err = -EOPNOTSUPP;
-+		goto exit;
-+	}
-+
-+	/* Search the correct ioctl */
-+	k = -1;
-+	sel_priv_args = priv_args;
-+	num_sel_priv_args = num_priv_args;
-+	while
-+	((++k < num_sel_priv_args) && strcmp(sel_priv_args[k].name, cmdname))
-+		;
-+
-+	/* If not found... */
-+	if (k == num_sel_priv_args) {
-+		k = -1;
-+		sel_priv_args = mp_priv_args;
-+		num_sel_priv_args = num_mp_priv_args;
-+		while
-+		((++k < num_sel_priv_args) && strcmp(sel_priv_args[k].name, cmdname))
-+			;
-+
-+		if (k == num_sel_priv_args) {
-+			err = -EOPNOTSUPP;
-+			goto exit;
-+		}
-+	}
-+
-+	/* Watch out for sub-ioctls ! */
-+	if (sel_priv_args[k].cmd < SIOCDEVPRIVATE) {
-+		int j = -1;
-+
-+		/* Find the matching *real* ioctl */
-+		while ((++j < num_priv_args) && ((priv_args[j].name[0] != '\0') ||
-+			 (priv_args[j].set_args != sel_priv_args[k].set_args) ||
-+			 (priv_args[j].get_args != sel_priv_args[k].get_args)))
-+			;
-+
-+		/* If not found... */
-+		if (j == num_priv_args) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		/* Save sub-ioctl number */
-+		subcmd = sel_priv_args[k].cmd;
-+		/* Reserve one int (simplify alignment issues) */
-+		offset = sizeof(__u32);
-+		/* Use real ioctl definition from now on */
-+		k = j;
-+	}
-+
-+	buffer = rtw_zmalloc(4096);
-+	if (NULL == buffer) {
-+		err = -ENOMEM;
-+		goto exit;
-+	}
-+
-+	if (k >= num_priv_args) {
-+		err = -EINVAL;
-+		goto exit;
-+	}
-+
-+	/* If we have to set some data */
-+	if ((priv_args[k].set_args & IW_PRIV_TYPE_MASK) &&
-+	    (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) {
-+		u8 *str;
-+
-+		switch (priv_args[k].set_args & IW_PRIV_TYPE_MASK) {
-+		case IW_PRIV_TYPE_BYTE:
-+			/* Fetch args */
-+			count = 0;
-+			do {
-+				str = strsep(&ptr, delim);
-+				if (NULL == str)
-+					break;
-+				sscanf(str, "%i", &temp);
-+				buffer[count++] = (u8)temp;
-+			} while (1);
-+			buffer_len = count;
-+
-+			/* Number of args to fetch */
-+			wdata.data.length = count;
-+			if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK))
-+				wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK;
-+
-+			break;
-+
-+		case IW_PRIV_TYPE_INT:
-+			/* Fetch args */
-+			count = 0;
-+			do {
-+				str = strsep(&ptr, delim);
-+				if (NULL == str)
-+					break;
-+				sscanf(str, "%i", &temp);
-+				((s32 *)buffer)[count++] = (s32)temp;
-+			} while (1);
-+			buffer_len = count * sizeof(s32);
-+
-+			/* Number of args to fetch */
-+			wdata.data.length = count;
-+			if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK))
-+				wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK;
-+
-+			break;
-+
-+		case IW_PRIV_TYPE_CHAR:
-+			if (len > 0) {
-+				/* Size of the string to fetch */
-+				wdata.data.length = len;
-+				if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK))
-+					wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK;
-+
-+				/* Fetch string */
-+				_rtw_memcpy(buffer, ptr, wdata.data.length);
-+			} else {
-+				wdata.data.length = 1;
-+				buffer[0] = '\0';
-+			}
-+			buffer_len = wdata.data.length;
-+			break;
-+
-+		default:
-+			RTW_INFO("%s: Not yet implemented...\n", __func__);
-+			err = -1;
-+			goto exit;
-+		}
-+
-+		if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) &&
-+		    (wdata.data.length != (priv_args[k].set_args & IW_PRIV_SIZE_MASK))) {
-+			RTW_INFO("%s: The command %s needs exactly %d argument(s)...\n",
-+				__func__, cmdname, priv_args[k].set_args & IW_PRIV_SIZE_MASK);
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+	}   /* if args to set */
-+	else
-+		wdata.data.length = 0L;
-+
-+	/* Those two tests are important. They define how the driver
-+	* will have to handle the data */
-+	if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) &&
-+	    ((get_priv_size(priv_args[k].set_args) + offset) <= IFNAMSIZ)) {
-+		/* First case : all SET args fit within wrq */
-+		if (offset)
-+			wdata.mode = subcmd;
-+		_rtw_memcpy(wdata.name + offset, buffer, IFNAMSIZ - offset);
-+	} else {
-+		if ((priv_args[k].set_args == 0) &&
-+		    (priv_args[k].get_args & IW_PRIV_SIZE_FIXED) &&
-+		    (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) {
-+			/* Second case : no SET args, GET args fit within wrq */
-+			if (offset)
-+				wdata.mode = subcmd;
-+		} else {
-+			/* Third case : args won't fit in wrq, or variable number of args */
-+			if (copy_to_user(wdata.data.pointer, buffer, buffer_len)) {
-+				err = -EFAULT;
-+				goto exit;
-+			}
-+			wdata.data.flags = subcmd;
-+		}
-+	}
-+
-+	rtw_mfree(input, input_len);
-+	input = NULL;
-+
-+	extra_size = 0;
-+	if (IW_IS_SET(priv_args[k].cmd)) {
-+		/* Size of set arguments */
-+		extra_size = get_priv_size(priv_args[k].set_args);
-+
-+		/* Does it fits in iwr ? */
-+		if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) &&
-+		    ((extra_size + offset) <= IFNAMSIZ))
-+			extra_size = 0;
-+	} else {
-+		/* Size of get arguments */
-+		extra_size = get_priv_size(priv_args[k].get_args);
-+
-+		/* Does it fits in iwr ? */
-+		if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) &&
-+		    (extra_size <= IFNAMSIZ))
-+			extra_size = 0;
-+	}
-+
-+	if (extra_size == 0) {
-+		extra = (u8 *)&wdata;
-+		rtw_mfree(buffer, 4096);
-+		buffer = NULL;
-+	} else
-+		extra = buffer;
-+
-+	handler = priv[priv_args[k].cmd - SIOCIWFIRSTPRIV];
-+	err = handler(dev, NULL, &wdata, extra);
-+
-+	/* If we have to get some data */
-+	if ((priv_args[k].get_args & IW_PRIV_TYPE_MASK) &&
-+	    (priv_args[k].get_args & IW_PRIV_SIZE_MASK)) {
-+		int j;
-+		int n = 0;	/* number of args */
-+		u8 str[20] = {0};
-+
-+		/* Check where is the returned data */
-+		if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) &&
-+		    (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ))
-+			n = priv_args[k].get_args & IW_PRIV_SIZE_MASK;
-+		else
-+			n = wdata.data.length;
-+
-+		output = rtw_zmalloc(4096);
-+		if (NULL == output) {
-+			err =  -ENOMEM;
-+			goto exit;
-+		}
-+
-+		switch (priv_args[k].get_args & IW_PRIV_TYPE_MASK) {
-+		case IW_PRIV_TYPE_BYTE:
-+			/* Display args */
-+			for (j = 0; j < n; j++) {
-+				sprintf(str, "%d  ", extra[j]);
-+				len = strlen(str);
-+				output_len = strlen(output);
-+				if ((output_len + len + 1) > 4096) {
-+					err = -E2BIG;
-+					goto exit;
-+				}
-+				_rtw_memcpy(output + output_len, str, len);
-+			}
-+			break;
-+
-+		case IW_PRIV_TYPE_INT:
-+			/* Display args */
-+			for (j = 0; j < n; j++) {
-+				sprintf(str, "%d  ", ((__s32 *)extra)[j]);
-+				len = strlen(str);
-+				output_len = strlen(output);
-+				if ((output_len + len + 1) > 4096) {
-+					err = -E2BIG;
-+					goto exit;
-+				}
-+				_rtw_memcpy(output + output_len, str, len);
-+			}
-+			break;
-+
-+		case IW_PRIV_TYPE_CHAR:
-+			/* Display args */
-+			_rtw_memcpy(output, extra, n);
-+			break;
-+
-+		default:
-+			RTW_INFO("%s: Not yet implemented...\n", __func__);
-+			err = -1;
-+			goto exit;
-+		}
-+
-+		output_len = strlen(output) + 1;
-+		wrq_data->data.length = output_len;
-+		if (copy_to_user(wrq_data->data.pointer, output, output_len)) {
-+			err = -EFAULT;
-+			goto exit;
-+		}
-+	}   /* if args to set */
-+	else
-+		wrq_data->data.length = 0;
-+
-+exit:
-+	if (input)
-+		rtw_mfree(input, input_len);
-+	if (buffer)
-+		rtw_mfree(buffer, 4096);
-+	if (output)
-+		rtw_mfree(output, 4096);
-+
-+	return err;
-+}
-+
-+#ifdef CONFIG_COMPAT
-+static int rtw_ioctl_compat_wext_private(struct net_device *dev, struct ifreq *rq)
-+{
-+	struct compat_iw_point iwp_compat;
-+	union iwreq_data wrq_data;
-+	int err = 0;
-+	RTW_DBG("%s:...\n", __func__);
-+	if (copy_from_user(&iwp_compat, rq->ifr_ifru.ifru_data, sizeof(struct compat_iw_point)))
-+		return -EFAULT;
-+
-+	wrq_data.data.pointer = compat_ptr(iwp_compat.pointer);
-+	wrq_data.data.length = iwp_compat.length;
-+	wrq_data.data.flags = iwp_compat.flags;
-+
-+	err = _rtw_ioctl_wext_private(dev, &wrq_data);
-+
-+	iwp_compat.pointer = ptr_to_compat(wrq_data.data.pointer);
-+	iwp_compat.length = wrq_data.data.length;
-+	iwp_compat.flags = wrq_data.data.flags;
-+	if (copy_to_user(rq->ifr_ifru.ifru_data, &iwp_compat, sizeof(struct compat_iw_point)))
-+		return -EFAULT;
-+
-+	return err;
-+}
-+#endif /* CONFIG_COMPAT */
-+
-+static int rtw_ioctl_standard_wext_private(struct net_device *dev, struct ifreq *rq)
-+{
-+	struct iw_point *iwp;
-+	union iwreq_data wrq_data;
-+	int err = 0;
-+	iwp = &wrq_data.data;
-+	RTW_DBG("%s:...\n", __func__);
-+	if (copy_from_user(iwp, rq->ifr_ifru.ifru_data, sizeof(struct iw_point)))
-+		return -EFAULT;
-+
-+	err = _rtw_ioctl_wext_private(dev, &wrq_data);
-+
-+	if (copy_to_user(rq->ifr_ifru.ifru_data, iwp, sizeof(struct iw_point)))
-+		return -EFAULT;
-+
-+	return err;
-+}
-+
-+static int rtw_ioctl_wext_private(struct net_device *dev, struct ifreq *rq)
-+{
-+#ifdef CONFIG_COMPAT
-+#if (KERNEL_VERSION(4, 6, 0) > LINUX_VERSION_CODE)
-+	if (is_compat_task())
-+#else
-+	if (in_compat_syscall())
-+#endif
-+		return rtw_ioctl_compat_wext_private(dev, rq);
-+	else
-+#endif /* CONFIG_COMPAT */
-+		return rtw_ioctl_standard_wext_private(dev, rq);
-+}
-+
-+int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
-+{
-+	struct iwreq *wrq = (struct iwreq *)rq;
-+	int ret = 0;
-+
-+	switch (cmd) {
-+#ifdef CONFIG_IOCTL_WEXT
-+	case RTL_IOCTL_WPA_SUPPLICANT:
-+		ret = wpa_supplicant_ioctl(dev, &wrq->u.data);
-+		break;
-+#ifdef CONFIG_AP_MODE
-+	case RTL_IOCTL_HOSTAPD:
-+		ret = rtw_hostapd_ioctl(dev, &wrq->u.data);
-+		break;
-+#ifdef CONFIG_WIRELESS_EXT
-+	case SIOCSIWMODE:
-+		ret = rtw_wx_set_mode(dev, NULL, &wrq->u, NULL);
-+		break;
-+#endif
-+#endif /* CONFIG_AP_MODE */
-+#endif /* CONFIG_IOCTL_WEXT */
-+	case SIOCDEVPRIVATE:
-+		ret = rtw_ioctl_wext_private(dev, rq);
-+		break;
-+	case (SIOCDEVPRIVATE+1):
-+		ret = rtw_android_priv_cmd(dev, rq, cmd);
-+		break;
-+	default:
-+		ret = -EOPNOTSUPP;
-+		break;
-+	}
-+
-+	return ret;
-+}
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/ioctl_mp.c b/drivers/staging/rtl8723cs/os_dep/linux/ioctl_mp.c
-new file mode 100644
-index 000000000000..185cc9478015
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/ioctl_mp.c
-@@ -0,0 +1,3531 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#if defined(CONFIG_MP_INCLUDED)
-+
-+#include <drv_types.h>
-+#include <rtw_mp.h>
-+#include "../../hal/phydm/phydm_precomp.h"
-+#include <linux/ctype.h>
-+
-+
-+#if defined(CONFIG_RTL8723B)
-+	#include <rtw_bt_mp.h>
-+#endif
-+
-+#define RTW_IWD_MAX_LEN	128
-+inline u8 rtw_do_mp_iwdata_len_chk(const char *caller, u32 len)
-+{
-+	u8 is_illegal = _FALSE;
-+	if (len >= RTW_IWD_MAX_LEN) {
-+		RTW_ERR("%s : iw data len(%u) > RTW_IWD_MAX_LEN(%u)",
-+			caller, len, RTW_IWD_MAX_LEN);
-+		is_illegal = _TRUE;
-+	}
-+	return is_illegal;
-+}
-+
-+/*
-+ * Input Format: %s,%d,%d
-+ *	%s is width, could be
-+ *		"b" for 1 byte
-+ *		"w" for WORD (2 bytes)
-+ *		"dw" for DWORD (4 bytes)
-+ *	1st %d is address(offset)
-+ *	2st %d is data to write
-+ */
-+int rtw_mp_write_reg(struct net_device *dev,
-+		     struct iw_request_info *info,
-+		     struct iw_point *wrqu, char *extra)
-+{
-+	char *pch, *pnext;
-+	char *width_str;
-+	char width;
-+	u32 addr, data;
-+	int ret;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	char input[RTW_IWD_MAX_LEN];
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1)))
-+		return -EFAULT;
-+
-+	_rtw_memset(input, 0, sizeof(input));
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	input[wrqu->length] = '\0';
-+
-+	_rtw_memset(extra, 0, wrqu->length);
-+
-+	pch = input;
-+
-+	pnext = strpbrk(pch, " ,.-");
-+	if (pnext == NULL)
-+		return -EINVAL;
-+	*pnext = 0;
-+	width_str = pch;
-+
-+	pch = pnext + 1;
-+	pnext = strpbrk(pch, " ,.-");
-+	if (pnext == NULL)
-+		return -EINVAL;
-+	*pnext = 0;
-+	/*addr = simple_strtoul(pch, &ptmp, 16);
-+	_rtw_memset(buf, '\0', sizeof(buf));
-+	_rtw_memcpy(buf, pch, pnext-pch);
-+	ret = kstrtoul(buf, 16, &addr);*/
-+	ret = sscanf(pch, "%x", &addr);
-+
-+	pch = pnext + 1;
-+	pnext = strpbrk(pch, " ,.-");
-+	if ((pch - input) >= wrqu->length)
-+		return -EINVAL;
-+	/*data = simple_strtoul(pch, &ptmp, 16);*/
-+	ret = sscanf(pch, "%x", &data);
-+	RTW_INFO("data=%x,addr=%x\n", (u32)data, (u32)addr);
-+	ret = 0;
-+	width = width_str[0];
-+	switch (width) {
-+	case 'b':
-+		/* 1 byte*/
-+		if (data > 0xFF) {
-+			ret = -EINVAL;
-+			break;
-+		}
-+		rtw_write8(padapter, addr, data);
-+		break;
-+	case 'w':
-+		/* 2 bytes*/
-+		if (data > 0xFFFF) {
-+			ret = -EINVAL;
-+			break;
-+		}
-+		rtw_write16(padapter, addr, data);
-+		break;
-+	case 'd':
-+		/* 4 bytes*/
-+		rtw_write32(padapter, addr, data);
-+		break;
-+	default:
-+		ret = -EINVAL;
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+
-+/*
-+ * Input Format: %s,%d
-+ *	%s is width, could be
-+ *		"b" for 1 byte
-+ *		"w" for WORD (2 bytes)
-+ *		"dw" for DWORD (4 bytes)
-+ *	%d is address(offset)
-+ *
-+ * Return:
-+ *	%d for data readed
-+ */
-+int rtw_mp_read_reg(struct net_device *dev,
-+		    struct iw_request_info *info,
-+		    struct iw_point *wrqu, char *extra)
-+{
-+	char input[RTW_IWD_MAX_LEN];
-+	char *pch, *pnext;
-+	char *width_str;
-+	char width;
-+	char data[20], tmp[20];
-+	u32 addr = 0, strtout = 0;
-+	u32 i = 0, j = 0, ret = 0, data32 = 0;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	char *pextra = extra;
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1)))
-+		return -EFAULT;
-+
-+	if (wrqu->length > 128)
-+		return -EFAULT;
-+
-+	_rtw_memset(input, 0, sizeof(input));
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	input[wrqu->length] = '\0';
-+	_rtw_memset(extra, 0, wrqu->length);
-+	_rtw_memset(data, '\0', sizeof(data));
-+	_rtw_memset(tmp, '\0', sizeof(tmp));
-+	pch = input;
-+	pnext = strpbrk(pch, " ,.-");
-+	if (pnext == NULL)
-+		return -EINVAL;
-+	*pnext = 0;
-+	width_str = pch;
-+
-+	pch = pnext + 1;
-+
-+	ret = sscanf(pch, "%x", &addr);
-+	if (addr > MP_READ_REG_MAX_OFFSET)
-+		return -EINVAL;
-+
-+	ret = 0;
-+	width = width_str[0];
-+
-+	switch (width) {
-+	case 'b':
-+		data32 = rtw_read8(padapter, addr);
-+		RTW_INFO("%x\n", data32);
-+		sprintf(extra, "%d", data32);
-+		wrqu->length = strlen(extra);
-+		break;
-+	case 'w':
-+		/* 2 bytes*/
-+		sprintf(data, "%04x\n", rtw_read16(padapter, addr));
-+
-+		for (i = 0 ; i <= strlen(data) ; i++) {
-+			if (i % 2 == 0) {
-+				tmp[j] = ' ';
-+				j++;
-+			}
-+			if (data[i] != '\0')
-+				tmp[j] = data[i];
-+
-+			j++;
-+		}
-+		pch = tmp;
-+		RTW_INFO("pch=%s", pch);
-+
-+		while (*pch != '\0') {
-+			pnext = strpbrk(pch, " ");
-+			if (!pnext || ((pnext - tmp) > 4))
-+				break;
-+
-+			pnext++;
-+			if (*pnext != '\0') {
-+				/*strtout = simple_strtoul(pnext , &ptmp, 16);*/
-+				ret = sscanf(pnext, "%x", &strtout);
-+				pextra += sprintf(pextra, " %d", strtout);
-+			} else
-+				break;
-+			pch = pnext;
-+		}
-+		wrqu->length = strlen(extra);
-+		break;
-+	case 'd':
-+		/* 4 bytes */
-+		sprintf(data, "%08x", rtw_read32(padapter, addr));
-+		/*add read data format blank*/
-+		for (i = 0 ; i <= strlen(data) ; i++) {
-+			if (i % 2 == 0) {
-+				tmp[j] = ' ';
-+				j++;
-+			}
-+			if (data[i] != '\0')
-+				tmp[j] = data[i];
-+
-+			j++;
-+		}
-+		pch = tmp;
-+		RTW_INFO("pch=%s", pch);
-+
-+		while (*pch != '\0') {
-+			pnext = strpbrk(pch, " ");
-+			if (!pnext)
-+				break;
-+
-+			pnext++;
-+			if (*pnext != '\0') {
-+				ret = sscanf(pnext, "%x", &strtout);
-+				pextra += sprintf(pextra, " %d", strtout);
-+			} else
-+				break;
-+			pch = pnext;
-+		}
-+		wrqu->length = strlen(extra);
-+		break;
-+
-+	default:
-+		wrqu->length = 0;
-+		ret = -EINVAL;
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+
-+/*
-+ * Input Format: %d,%x,%x
-+ *	%d is RF path, should be smaller than MAX_RF_PATH_NUMS
-+ *	1st %x is address(offset)
-+ *	2st %x is data to write
-+ */
-+int rtw_mp_write_rf(struct net_device *dev,
-+		    struct iw_request_info *info,
-+		    struct iw_point *wrqu, char *extra)
-+{
-+	u32 path, addr, data;
-+	int ret;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+	char input[RTW_IWD_MAX_LEN];
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length))
-+		return -EFAULT;
-+
-+	_rtw_memset(input, 0, wrqu->length);
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+
-+	ret = sscanf(input, "%d,%x,%x", &path, &addr, &data);
-+	if (ret < 3)
-+		return -EINVAL;
-+
-+	if (path >= hal_spec->rf_reg_path_num)
-+		return -EINVAL;
-+	if (addr > 0xFF)
-+		return -EINVAL;
-+	if (data > 0xFFFFF)
-+		return -EINVAL;
-+
-+	_rtw_memset(extra, 0, wrqu->length);
-+
-+	write_rfreg(padapter, path, addr, data);
-+
-+	sprintf(extra, "write_rf completed\n");
-+	wrqu->length = strlen(extra);
-+
-+	return 0;
-+}
-+
-+
-+/*
-+ * Input Format: %d,%x
-+ *	%d is RF path, should be smaller than MAX_RF_PATH_NUMS
-+ *	%x is address(offset)
-+ *
-+ * Return:
-+ *	%d for data readed
-+ */
-+int rtw_mp_read_rf(struct net_device *dev,
-+		   struct iw_request_info *info,
-+		   struct iw_point *wrqu, char *extra)
-+{
-+	char input[RTW_IWD_MAX_LEN];
-+	char *pch, *pnext;
-+	char data[20], tmp[20];
-+	u32 path, addr, strtou;
-+	u32 ret, i = 0 , j = 0;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+	char *pextra = extra;
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length))
-+		return -EFAULT;
-+
-+	if (wrqu->length > 128)
-+		return -EFAULT;
-+	_rtw_memset(input, 0, wrqu->length);
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	ret = sscanf(input, "%d,%x", &path, &addr);
-+	if (ret < 2)
-+		return -EINVAL;
-+
-+	if (path >= hal_spec->rf_reg_path_num)
-+		return -EINVAL;
-+
-+	if (addr > MP_READ_REG_MAX_OFFSET)
-+		return -EINVAL;
-+
-+	_rtw_memset(extra, 0, wrqu->length);
-+
-+	sprintf(data, "%08x", read_rfreg(padapter, path, addr));
-+	/*add read data format blank*/
-+	for (i = 0 ; i <= strlen(data) ; i++) {
-+		if (i % 2 == 0) {
-+			tmp[j] = ' ';
-+			j++;
-+		}
-+		tmp[j] = data[i];
-+		j++;
-+	}
-+	pch = tmp;
-+	RTW_INFO("pch=%s", pch);
-+
-+	while (*pch != '\0') {
-+		pnext = strpbrk(pch, " ");
-+		if (!pnext)
-+			break;
-+		pnext++;
-+		if (*pnext != '\0') {
-+			/*strtou =simple_strtoul(pnext , &ptmp, 16);*/
-+			ret = sscanf(pnext, "%x", &strtou);
-+			pextra += sprintf(pextra, " %d", strtou);
-+		} else
-+			break;
-+		pch = pnext;
-+	}
-+	wrqu->length = strlen(extra);
-+
-+	return 0;
-+}
-+
-+
-+int rtw_mp_start(struct net_device *dev,
-+		 struct iw_request_info *info,
-+		 struct iw_point *wrqu, char *extra)
-+{
-+	int ret = 0;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	struct mp_priv *pmppriv = &padapter->mppriv;
-+
-+	rtw_pm_set_ips(padapter, IPS_NONE);
-+	LeaveAllPowerSaveMode(padapter);
-+
-+	pmppriv->bprocess_mp_mode = _TRUE;
-+
-+	if (rtw_mi_check_fwstate(padapter, WIFI_UNDER_SURVEY)) {
-+		rtw_mi_buddy_set_scan_deny(padapter, 5000);
-+		rtw_mi_scan_abort(padapter, _TRUE);
-+	}
-+
-+	rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
-+
-+	if (rtw_mp_cmd(padapter, MP_START, RTW_CMDF_WAIT_ACK) != _SUCCESS)
-+		ret = -EPERM;
-+
-+	_rtw_memset(extra, 0, wrqu->length);
-+	sprintf(extra, "mp_start %s\n", ret == 0 ? "ok" : "fail");
-+	wrqu->length = strlen(extra);
-+
-+	return ret;
-+}
-+
-+
-+
-+int rtw_mp_stop(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra)
-+{
-+	int ret = 0;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	struct mp_priv *pmppriv = &padapter->mppriv;
-+
-+	if (pmppriv->mode != MP_ON)
-+		return -EPERM;
-+
-+	if (rtw_mp_cmd(padapter, MP_STOP, RTW_CMDF_WAIT_ACK) != _SUCCESS)
-+		ret = -EPERM;
-+
-+	pmppriv->bprocess_mp_mode = _FALSE;
-+	_rtw_memset(extra, 0, wrqu->length);
-+	sprintf(extra, "mp_stop %s\n", ret == 0 ? "ok" : "fail");
-+	wrqu->length = strlen(extra);
-+
-+	return ret;
-+}
-+
-+
-+int rtw_mp_rate(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra)
-+{
-+	u32 rate = MPT_RATE_1M;
-+	u8 err = 0;
-+	u8 input[RTW_IWD_MAX_LEN];
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	PMPT_CONTEXT		pMptCtx = &(padapter->mppriv.mpt_ctx);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+	struct	mp_priv	*pmppriv = &padapter->mppriv;
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1)))
-+		return -EFAULT;
-+
-+	_rtw_memset(input, 0, sizeof(input));
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	input[wrqu->length] = '\0';
-+	rate = rtw_mpRateParseFunc(padapter, input);
-+	pmppriv->rateidx = rate;
-+
-+	if (rate == 0 && strcmp(input, "1M") != 0) {
-+		rate = rtw_atoi(input);
-+		if (rate <= MGN_VHT4SS_MCS9)
-+			pmppriv->rateidx = MRateToHwRate(rate);
-+		/*if (rate <= 0x7f)
-+			rate = wifirate2_ratetbl_inx((u8)rate);
-+		else if (rate < 0xC8)
-+			rate = (rate - 0x79 + MPT_RATE_MCS0);
-+		HT  rate 0x80(MCS0)  ~ 0x8F(MCS15) ~ 0x9F(MCS31) 128~159
-+		VHT1SS~2SS rate 0xA0 (VHT1SS_MCS0 44) ~ 0xB3 (VHT2SS_MCS9 #63) 160~179
-+		VHT rate 0xB4 (VHT3SS_MCS0 64) ~ 0xC7 (VHT2SS_MCS9 #83) 180~199
-+		else
-+		VHT rate 0x90(VHT1SS_MCS0) ~ 0x99(VHT1SS_MCS9) 144~153
-+		rate =(rate - MPT_RATE_VHT1SS_MCS0);
-+		*/
-+	}
-+
-+	_rtw_memset(extra, 0, wrqu->length);
-+
-+	if (pmppriv->rateidx > DESC_RATEVHTSS4MCS9) {
-+		sprintf(extra, "Set %s Error" , input);
-+		return -EINVAL;
-+	}
-+
-+	if (hal_spec->tx_nss_num < 2 && MPT_IS_2SS_RATE(HwRateToMPTRate(pmppriv->rateidx)))
-+		err = 1;
-+	if (hal_spec->tx_nss_num < 3 && MPT_IS_3SS_RATE(HwRateToMPTRate(pmppriv->rateidx)))
-+		err = 1;
-+	if (hal_spec->tx_nss_num < 4 && MPT_IS_4SS_RATE(HwRateToMPTRate(pmppriv->rateidx)))
-+		err = 1;
-+	if (!is_supported_vht(padapter->registrypriv.wireless_mode) && MPT_IS_VHT_RATE(HwRateToMPTRate(pmppriv->rateidx)))
-+		err = 1;
-+	if (!is_supported_ht(padapter->registrypriv.wireless_mode) && MPT_IS_HT_RATE(HwRateToMPTRate(pmppriv->rateidx)))
-+		err = 1;
-+
-+	if (err == 1) {
-+		sprintf(extra, "Set data rate to %s Error" , input);
-+		pmppriv->rateidx = 0;
-+	} else {
-+		sprintf(extra, "Set data rate to %s index %d" , input, pmppriv->rateidx);
-+		RTW_INFO("%s: %s rate index=%d\n", __func__, input, pmppriv->rateidx);
-+		pMptCtx->mpt_rate_index = HwRateToMPTRate(pmppriv->rateidx);
-+		SetDataRate(padapter);
-+	}
-+	wrqu->length = strlen(extra);
-+	return err;
-+}
-+
-+int rtw_mp_channel(struct net_device *dev,
-+		   struct iw_request_info *info,
-+		   struct iw_point *wrqu, char *extra)
-+{
-+
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
-+	u8 input[RTW_IWD_MAX_LEN];
-+	u8	channel = 1;
-+	struct	mp_priv	*pmppriv = &padapter->mppriv;
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1)))
-+		return -EFAULT;
-+
-+	_rtw_memset(input, 0, sizeof(input));
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	input[wrqu->length] = '\0';
-+	channel = rtw_atoi(input);
-+	/*RTW_INFO("%s: channel=%d\n", __func__, channel);*/
-+	_rtw_memset(extra, 0, wrqu->length);
-+	sprintf(extra, "Change channel %d to channel %d", padapter->mppriv.channel , channel);
-+	padapter->mppriv.channel = channel;
-+	rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
-+	rtw_adjust_chbw(padapter, channel, &pmppriv->bandwidth, &pmppriv->prime_channel_offset);
-+	SetChannel(padapter);
-+	pHalData->current_channel = channel;
-+
-+	wrqu->length = strlen(extra);
-+	return 0;
-+}
-+
-+
-+int rtw_mp_ch_offset(struct net_device *dev,
-+		   struct iw_request_info *info,
-+		   struct iw_point *wrqu, char *extra)
-+{
-+
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	u8 input[RTW_IWD_MAX_LEN];
-+	u32	ch_offset = 0;
-+	char *pch;
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1)))
-+		return -EFAULT;
-+
-+	_rtw_memset(input, 0, sizeof(input));
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	input[wrqu->length] = '\0';
-+	ch_offset = rtw_atoi(input);
-+	/*RTW_INFO("%s: channel=%d\n", __func__, channel);*/
-+	_rtw_memset(extra, 0, wrqu->length);
-+	pch = extra;
-+	pch += sprintf(pch, "Change prime channel offset %d to %d", padapter->mppriv.prime_channel_offset , ch_offset);
-+	padapter->mppriv.prime_channel_offset = ch_offset;
-+	SetChannel(padapter);
-+
-+	wrqu->length = strlen(extra);
-+	return 0;
-+}
-+
-+
-+int rtw_mp_bandwidth(struct net_device *dev,
-+		     struct iw_request_info *info,
-+		     struct iw_point *wrqu, char *extra)
-+{
-+	u8 bandwidth = 0, sg = 0;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
-+	struct	mp_priv	*pmppriv = &padapter->mppriv;
-+	u8 input[RTW_IWD_MAX_LEN];
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length))
-+		return -EFAULT;
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	if (sscanf(input, "40M=%hhd,shortGI=%hhd", &bandwidth, &sg) > 0)
-+		RTW_INFO("%s: bw=%hhd sg=%hhd\n", __func__, bandwidth , sg);
-+
-+	rtw_adjust_chbw(padapter, pmppriv->channel, &bandwidth, &pmppriv->prime_channel_offset);
-+
-+	padapter->mppriv.bandwidth = (u8)bandwidth;
-+	padapter->mppriv.preamble = sg;
-+	_rtw_memset(extra, 0, wrqu->length);
-+	sprintf(extra, "Change BW %d to BW %d\n", pHalData->current_channel_bw , bandwidth);
-+	rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
-+	SetBandwidth(padapter);
-+	pHalData->current_channel_bw = bandwidth;
-+
-+	wrqu->length = strlen(extra);
-+
-+	return 0;
-+}
-+
-+
-+int rtw_mp_txpower_index(struct net_device *dev,
-+			 struct iw_request_info *info,
-+			 struct iw_point *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+ 	HAL_DATA_TYPE	*phal_data	= GET_HAL_DATA(padapter);
-+	char input[RTW_IWD_MAX_LEN];
-+	u32 rfpath = 0 ;
-+	u32 txpower_inx = 0, tarpowerdbm = 0;
-+	char *pextra = extra;
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1)))
-+		return -EFAULT;
-+
-+	if (wrqu->length > 128)
-+		return -EFAULT;
-+
-+	_rtw_memset(input, 0, sizeof(input));
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	input[wrqu->length] = '\0';
-+	_rtw_memset(extra, 0, strlen(extra));
-+
-+	if (wrqu->length == 2) {
-+		if (input[0] != '\0' ) {
-+			rfpath = rtw_atoi(input);
-+			txpower_inx = mpt_ProQueryCalTxPower(padapter, rfpath);
-+		}
-+		pextra += sprintf(pextra, " %d\n", txpower_inx);
-+		tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, rfpath);
-+		if (tarpowerdbm > 0)
-+			pextra += sprintf(pextra, "\t\t dBm:%d", tarpowerdbm);
-+	} else {
-+		if (phal_data->ant_path == 1)
-+			rfpath = 1;
-+		else
-+			rfpath = 0;
-+
-+		txpower_inx = mpt_ProQueryCalTxPower(padapter, rfpath);
-+		pextra += sprintf(pextra, "patha=%d", txpower_inx);
-+		if (phal_data->rf_type > RF_1T2R) {
-+			txpower_inx = mpt_ProQueryCalTxPower(padapter, 1);
-+			pextra += sprintf(pextra, ",pathb=%d", txpower_inx);
-+		}
-+		if (phal_data->rf_type > RF_2T4R) {
-+			txpower_inx = mpt_ProQueryCalTxPower(padapter, 2);
-+			pextra += sprintf(pextra, ",pathc=%d", txpower_inx);
-+		}
-+		if (phal_data->rf_type > RF_3T4R) {
-+			txpower_inx = mpt_ProQueryCalTxPower(padapter, 3);
-+			pextra += sprintf(pextra, ",pathd=%d", txpower_inx);
-+		}
-+
-+		tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, rfpath);
-+		pextra += sprintf(pextra, "\n\t\t\tpatha dBm=%d", tarpowerdbm);
-+		if (phal_data->rf_type > RF_1T2R) {
-+			tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, 1);
-+			pextra += sprintf(pextra, ",pathb dBm=%d", tarpowerdbm);
-+		}
-+		if (phal_data->rf_type > RF_2T4R) {
-+			tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, 2);
-+			pextra += sprintf(pextra, ",pathc dBm=%d", tarpowerdbm);
-+		}
-+		if (phal_data->rf_type > RF_3T4R) {
-+			tarpowerdbm = mpt_get_tx_power_finalabs_val(padapter, 3);
-+			pextra += sprintf(pextra, ",pathd dBm=%d", tarpowerdbm);
-+		}
-+	}
-+	wrqu->length = strlen(extra);
-+
-+	return 0;
-+}
-+
-+
-+int rtw_mp_txpower(struct net_device *dev,
-+		   struct iw_request_info *info,
-+		   struct iw_point *wrqu, char *extra)
-+{
-+	u32 idx_a = 0, idx_b = 0, idx_c = 0, idx_d = 0;
-+	int MsetPower = 1;
-+	u8 input[RTW_IWD_MAX_LEN];
-+	u8 res = 0;
-+
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	PMPT_CONTEXT		pMptCtx = &(padapter->mppriv.mpt_ctx);
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length))
-+		return -EFAULT;
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	MsetPower = strncmp(input, "off", 3);
-+	if (MsetPower == 0) {
-+		padapter->mppriv.bSetTxPower = 0;
-+		sprintf(extra, "MP Set power off");
-+	} else {
-+			res = sscanf(input, "patha=%d,pathb=%d,pathc=%d,pathd=%d", &idx_a, &idx_b, &idx_c, &idx_d);
-+			if (res < 1) {
-+				if(isdigit(input[0])){
-+					idx_a = rtw_atoi(input);
-+					RTW_INFO("direct set RF Path A Power =%d\n", idx_a);
-+				} else
-+					RTW_INFO("Invalid format on %s !, Get patha=%d,pathb=%d,pathc=%d,pathd=%d\n", input , idx_a , idx_b , idx_c , idx_d);
-+			}
-+		if (res > 0 || idx_a !=0)
-+			sprintf(extra, "Set power level path_A:%d path_B:%d path_C:%d path_D:%d", idx_a , idx_b , idx_c , idx_d);
-+		else
-+			sprintf(extra, "Invalid format on string :%s ", input);
-+
-+		padapter->mppriv.txpoweridx = (u8)idx_a;
-+
-+		pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)idx_a;
-+		pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)idx_b;
-+		pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)idx_c;
-+		pMptCtx->TxPwrLevel[RF_PATH_D]  = (u8)idx_d;
-+		padapter->mppriv.bSetTxPower = 1;
-+
-+		SetTxPower(padapter);
-+	}
-+
-+	wrqu->length = strlen(extra);
-+	return 0;
-+}
-+
-+
-+int rtw_mp_ant_tx(struct net_device *dev,
-+		  struct iw_request_info *info,
-+		  struct iw_point *wrqu, char *extra)
-+{
-+	u8 i;
-+	u8 input[RTW_IWD_MAX_LEN];
-+	u16 antenna = 0;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1)))
-+		return -EFAULT;
-+
-+	_rtw_memset(input, 0, sizeof(input));
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	input[wrqu->length] = '\0';
-+	sprintf(extra, "switch Tx antenna to %s", input);
-+
-+	for (i = 0; i < strlen(input); i++) {
-+		switch (input[i]) {
-+		case 'a':
-+			antenna |= ANTENNA_A;
-+			break;
-+		case 'b':
-+			antenna |= ANTENNA_B;
-+			break;
-+		case 'c':
-+			antenna |= ANTENNA_C;
-+			break;
-+		case 'd':
-+			antenna |= ANTENNA_D;
-+			break;
-+		}
-+	}
-+	/*antenna |= BIT(extra[i]-'a');*/
-+	RTW_INFO("%s: antenna=0x%x\n", __func__, antenna);
-+	padapter->mppriv.antenna_tx = antenna;
-+
-+	/*RTW_INFO("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_tx);*/
-+	pHalData->antenna_tx_path = antenna;
-+	if (IS_HARDWARE_TYPE_8822C(padapter) && padapter->mppriv.antenna_tx == ANTENNA_B) {
-+		if (padapter->mppriv.antenna_rx == ANTENNA_A || padapter->mppriv.antenna_rx == ANTENNA_B) {
-+			padapter->mppriv.antenna_rx = ANTENNA_AB;
-+			pHalData->AntennaRxPath = ANTENNA_AB;
-+			RTW_INFO("%s:8822C Tx-B Rx Ant to AB\n", __func__);
-+		}
-+	}
-+	SetAntenna(padapter);
-+
-+	wrqu->length = strlen(extra);
-+	return 0;
-+}
-+
-+
-+int rtw_mp_ant_rx(struct net_device *dev,
-+		  struct iw_request_info *info,
-+		  struct iw_point *wrqu, char *extra)
-+{
-+	u8 i;
-+	u16 antenna = 0;
-+	u8 input[RTW_IWD_MAX_LEN];
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1)))
-+		return -EFAULT;
-+
-+	_rtw_memset(input, 0, sizeof(input));
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	input[wrqu->length] = '\0';
-+	/*RTW_INFO("%s: input=%s\n", __func__, input);*/
-+	_rtw_memset(extra, 0, wrqu->length);
-+
-+	sprintf(extra, "switch Rx antenna to %s", input);
-+
-+	for (i = 0; i < strlen(input); i++) {
-+		switch (input[i]) {
-+		case 'a':
-+			antenna |= ANTENNA_A;
-+			break;
-+		case 'b':
-+			antenna |= ANTENNA_B;
-+			break;
-+		case 'c':
-+			antenna |= ANTENNA_C;
-+			break;
-+		case 'd':
-+			antenna |= ANTENNA_D;
-+			break;
-+		}
-+	}
-+
-+	RTW_INFO("%s: antenna=0x%x\n", __func__, antenna);
-+
-+	padapter->mppriv.antenna_rx = antenna;
-+	pHalData->AntennaRxPath = antenna;
-+	/*RTW_INFO("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_rx);*/
-+	SetAntenna(padapter);
-+	wrqu->length = strlen(extra);
-+
-+	return 0;
-+}
-+
-+
-+int rtw_set_ctx_destAddr(struct net_device *dev,
-+			 struct iw_request_info *info,
-+			 struct iw_point *wrqu, char *extra)
-+{
-+	int jj, kk = 0;
-+
-+	struct pkt_attrib *pattrib;
-+	struct mp_priv *pmp_priv;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+
-+	pmp_priv = &padapter->mppriv;
-+	pattrib = &pmp_priv->tx.attrib;
-+
-+	if (strlen(extra) < 5)
-+		return _FAIL;
-+
-+	RTW_INFO("%s: in=%s\n", __func__, extra);
-+	for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3)
-+		pattrib->dst[jj] = key_2char2num(extra[kk], extra[kk + 1]);
-+
-+	RTW_INFO("pattrib->dst:%x %x %x %x %x %x\n", pattrib->dst[0], pattrib->dst[1], pattrib->dst[2], pattrib->dst[3], pattrib->dst[4], pattrib->dst[5]);
-+	return 0;
-+}
-+
-+
-+
-+int rtw_mp_ctx(struct net_device *dev,
-+	       struct iw_request_info *info,
-+	       struct iw_point *wrqu, char *extra)
-+{
-+	u32 pkTx = 1;
-+	int countPkTx = 1, cotuTx = 1, CarrSprTx = 1, scTx = 1, sgleTx = 1, stop = 1, payload = 1;
-+	u32 bStartTest = 1;
-+	u32 count = 0, pktinterval = 0, pktlen = 0;
-+	u8 status;
-+	struct mp_priv *pmp_priv;
-+	struct pkt_attrib *pattrib;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	pmp_priv = &padapter->mppriv;
-+	pattrib = &pmp_priv->tx.attrib;
-+
-+	if (padapter->registrypriv.mp_mode != 1 ) {
-+		sprintf(extra, "Error: can't tx ,not in MP mode. \n");
-+		wrqu->length = strlen(extra);
-+		return 0;
-+	}
-+
-+	if (copy_from_user(extra, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	*(extra + wrqu->length) = '\0';
-+	RTW_INFO("%s: in=%s\n", __func__, extra);
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (!is_primary_adapter(padapter)) {
-+		sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n");
-+		wrqu->length = strlen(extra);
-+		return 0;
-+	}
-+#endif
-+	countPkTx = strncmp(extra, "count=", 5); /* strncmp TRUE is 0*/
-+	cotuTx = strncmp(extra, "background", 20);
-+	CarrSprTx = strncmp(extra, "background,cs", 20);
-+	scTx = strncmp(extra, "background,sc", 20);
-+	sgleTx = strncmp(extra, "background,stone", 20);
-+	pkTx = strncmp(extra, "background,pkt", 20);
-+	stop = strncmp(extra, "stop", 4);
-+	payload = strncmp(extra, "payload=", 8);
-+
-+	if (sscanf(extra, "count=%d,pkt", &count) > 0)
-+		RTW_INFO("count= %d\n", count);
-+	if (sscanf(extra, "pktinterval=%d", &pktinterval) > 0)
-+		RTW_INFO("pktinterval= %d\n", pktinterval);
-+	if (sscanf(extra, "pktlen=%d", &pktlen) > 0)
-+		RTW_INFO("pktlen= %d\n", pktlen);
-+
-+	if (payload == 0) {
-+			payload = MP_TX_Payload_default_random;
-+			if (strncmp(extra, "payload=prbs9", 14) == 0) {
-+				payload = MP_TX_Payload_prbs9;
-+				sprintf(extra, "config payload PRBS9\n");
-+			} else {
-+				if (sscanf(extra, "payload=%x", &payload) > 0){
-+					RTW_INFO("payload= %x\n", payload);
-+					sprintf(extra, "config payload setting = %x\n"
-+									"1. input payload=[]:\n		"
-+									"[0]: 00, [1]: A5, [2]: 5A, [3]: FF, [4]: PRBS-9, [5]: Random\n"
-+									"2. specified a hex payload: payload=0xee\n", payload);
-+				 }
-+			}
-+			pmp_priv->tx.payload = payload;
-+			wrqu->length = strlen(extra);
-+			return 0;
-+	}
-+
-+	if (_rtw_memcmp(extra, "destmac=", 8)) {
-+		wrqu->length -= 8;
-+		rtw_set_ctx_destAddr(dev, info, wrqu, &extra[8]);
-+		sprintf(extra, "Set dest mac OK !\n");
-+		return 0;
-+	}
-+	/*RTW_INFO("%s: count=%d countPkTx=%d cotuTx=%d CarrSprTx=%d scTx=%d sgleTx=%d pkTx=%d stop=%d\n", __func__, count, countPkTx, cotuTx, CarrSprTx, pkTx, sgleTx, scTx, stop);*/
-+	_rtw_memset(extra, '\0', strlen(extra));
-+
-+	if (pktinterval != 0) {
-+		sprintf(extra, "Pkt Interval = %d", pktinterval);
-+		padapter->mppriv.pktInterval = pktinterval;
-+		wrqu->length = strlen(extra);
-+		return 0;
-+
-+	} else if (pktlen != 0) {
-+		sprintf(extra, "Pkt len = %d", pktlen);
-+		pattrib->pktlen = pktlen;
-+		wrqu->length = strlen(extra);
-+		return 0;
-+
-+	} else if (stop == 0) {
-+		struct xmit_priv	*pxmitpriv = &(padapter->xmitpriv);
-+		_queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;
-+		_queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue;
-+
-+		u32 i = 0;
-+		bStartTest = 0; /* To set Stop*/
-+		pmp_priv->tx.stop = 1;
-+		sprintf(extra, "Stop continuous Tx");
-+		odm_write_dig(&pHalData->odmpriv, 0x20);
-+		do {
-+			if (pxmitpriv->free_xmitframe_cnt == NR_XMITFRAME && pxmitpriv->free_xmitbuf_cnt == NR_XMITBUFF)
-+				break;
-+			else {
-+				i++;
-+				RTW_INFO("%s:wait queue_empty %d!!\n", __func__, i);
-+				rtw_msleep_os(10);
-+			}
-+		} while (i < 1000);
-+	} else {
-+		bStartTest = 1;
-+		odm_write_dig(&pHalData->odmpriv, 0x3f);
-+		if (IS_HARDWARE_TYPE_8822C(padapter) && pmp_priv->antenna_tx == ANTENNA_B) {
-+			if (pmp_priv->antenna_rx == ANTENNA_A || pmp_priv->antenna_rx == ANTENNA_B) {
-+				pmp_priv->antenna_rx = ANTENNA_AB;
-+				pHalData->AntennaRxPath = ANTENNA_AB;
-+				RTW_INFO("%s:8822C Tx-B Rx Ant to AB\n", __func__);
-+				SetAntenna(padapter);
-+			}
-+		}
-+		if (pmp_priv->mode != MP_ON) {
-+			if (pmp_priv->tx.stop != 1) {
-+				RTW_INFO("%s:Error MP_MODE %d != ON\n", __func__, pmp_priv->mode);
-+				return	-EFAULT;
-+			}
-+		}
-+	}
-+
-+	pmp_priv->tx.count = count;
-+
-+	if (pkTx == 0 || countPkTx == 0)
-+		pmp_priv->mode = MP_PACKET_TX;
-+	if (sgleTx == 0)
-+		pmp_priv->mode = MP_SINGLE_TONE_TX;
-+	if (cotuTx == 0)
-+		pmp_priv->mode = MP_CONTINUOUS_TX;
-+	if (CarrSprTx == 0)
-+		pmp_priv->mode = MP_CARRIER_SUPPRISSION_TX;
-+	if (scTx == 0)
-+		pmp_priv->mode = MP_SINGLE_CARRIER_TX;
-+
-+	status = rtw_mp_pretx_proc(padapter, bStartTest, extra);
-+
-+	if (stop == 0)
-+		pmp_priv->mode = MP_ON;
-+
-+	wrqu->length = strlen(extra);
-+	return status;
-+}
-+
-+
-+
-+int rtw_mp_disable_bt_coexist(struct net_device *dev,
-+			      struct iw_request_info *info,
-+			      union iwreq_data *wrqu, char *extra)
-+{
-+#ifdef CONFIG_BT_COEXIST
-+	PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev);
-+
-+#endif
-+	u8 input[RTW_IWD_MAX_LEN];
-+	u32 bt_coexist;
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->data.length + 1)))
-+		return -EFAULT;
-+
-+	_rtw_memset(input, 0, sizeof(input));
-+
-+	if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+
-+	input[wrqu->data.length] = '\0';
-+
-+	bt_coexist = rtw_atoi(input);
-+
-+	if (bt_coexist == 0) {
-+		RTW_INFO("Set OID_RT_SET_DISABLE_BT_COEXIST: disable BT_COEXIST\n");
-+#ifdef CONFIG_BT_COEXIST
-+		rtw_btcoex_HaltNotify(padapter);
-+		rtw_btcoex_SetManualControl(padapter, _TRUE);
-+		/* Force to switch Antenna to WiFi*/
-+		rtw_write16(padapter, 0x870, 0x300);
-+		rtw_write16(padapter, 0x860, 0x110);
-+#endif
-+		/* CONFIG_BT_COEXIST */
-+	} else {
-+#ifdef CONFIG_BT_COEXIST
-+		rtw_btcoex_SetManualControl(padapter, _FALSE);
-+#endif
-+	}
-+
-+	return 0;
-+}
-+
-+
-+int rtw_mp_arx(struct net_device *dev,
-+	       struct iw_request_info *info,
-+	       struct iw_point *wrqu, char *extra)
-+{
-+	int bStartRx = 0, bStopRx = 0, bQueryPhy = 0, bQueryMac = 0, bSetBssid = 0, bSetRxframe = 0;
-+	int bmac_filter = 0, bmon = 0, bSmpCfg = 0;
-+	u8 input[RTW_IWD_MAX_LEN];
-+	char *pch, *token, *tmp[2] = {0x00, 0x00};
-+	u32 i = 0, jj = 0, kk = 0, cnts = 0, ret;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	struct mp_priv *pmppriv = &padapter->mppriv;
-+	struct dbg_rx_counter rx_counter;
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length))
-+		return -EFAULT;
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	RTW_INFO("%s: %s\n", __func__, input);
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (!is_primary_adapter(padapter)) {
-+		sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n");
-+		wrqu->length = strlen(extra);
-+		return 0;
-+	}
-+#endif
-+	bStartRx = (strncmp(input, "start", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
-+	bStopRx = (strncmp(input, "stop", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
-+	bQueryPhy = (strncmp(input, "phy", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
-+	bQueryMac = (strncmp(input, "mac", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
-+	bSetBssid = (strncmp(input, "setbssid=", 8) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
-+	bSetRxframe = (strncmp(input, "frametype", 9) == 0) ? 1 : 0;
-+	/*bfilter_init = (strncmp(input, "filter_init",11)==0)?1:0;*/
-+	bmac_filter = (strncmp(input, "accept_mac", 10) == 0) ? 1 : 0;
-+	bmon = (strncmp(input, "mon=", 4) == 0) ? 1 : 0;
-+	bSmpCfg = (strncmp(input , "smpcfg=" , 7) == 0) ? 1 : 0;
-+	pmppriv->bloopback = (strncmp(input, "loopbk", 6) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
-+
-+	if (bSetBssid == 1) {
-+		pch = input;
-+		while ((token = strsep(&pch, "=")) != NULL) {
-+			if (i > 1)
-+				break;
-+			tmp[i] = token;
-+			i++;
-+		}
-+		if ((tmp[0] != NULL) && (tmp[1] != NULL)) {
-+			cnts = strlen(tmp[1]) / 2;
-+			if (cnts < 1)
-+				return -EFAULT;
-+			RTW_INFO("%s: cnts=%d\n", __func__, cnts);
-+			RTW_INFO("%s: data=%s\n", __func__, tmp[1]);
-+			for (jj = 0, kk = 0; jj < cnts ; jj++, kk += 2) {
-+				pmppriv->network_macaddr[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
-+				RTW_INFO("network_macaddr[%d]=%x\n", jj, pmppriv->network_macaddr[jj]);
-+			}
-+		} else
-+			return -EFAULT;
-+
-+		pmppriv->bSetRxBssid = _TRUE;
-+	}
-+	if (bSetRxframe) {
-+		if (strncmp(input, "frametype beacon", 16) == 0)
-+			pmppriv->brx_filter_beacon = _TRUE;
-+		else
-+			pmppriv->brx_filter_beacon = _FALSE;
-+	}
-+
-+	if (bmac_filter) {
-+		pmppriv->bmac_filter = bmac_filter;
-+		pch = input;
-+		while ((token = strsep(&pch, "=")) != NULL) {
-+			if (i > 1)
-+				break;
-+			tmp[i] = token;
-+			i++;
-+		}
-+		if ((tmp[0] != NULL) && (tmp[1] != NULL)) {
-+			cnts = strlen(tmp[1]) / 2;
-+			if (cnts < 1)
-+				return -EFAULT;
-+			RTW_INFO("%s: cnts=%d\n", __func__, cnts);
-+			RTW_INFO("%s: data=%s\n", __func__, tmp[1]);
-+			for (jj = 0, kk = 0; jj < cnts ; jj++, kk += 2) {
-+				pmppriv->mac_filter[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
-+				RTW_INFO("%s mac_filter[%d]=%x\n", __func__, jj, pmppriv->mac_filter[jj]);
-+			}
-+		} else
-+			return -EFAULT;
-+
-+	}
-+
-+	if (bStartRx) {
-+		sprintf(extra, "start");
-+		SetPacketRx(padapter, bStartRx, _FALSE);
-+	} else if (bStopRx) {
-+		SetPacketRx(padapter, bStartRx, _FALSE);
-+		pmppriv->bmac_filter = _FALSE;
-+		pmppriv->bSetRxBssid = _FALSE;
-+		sprintf(extra, "Received packet OK:%d CRC error:%d ,Filter out:%d", padapter->mppriv.rx_pktcount, padapter->mppriv.rx_crcerrpktcount, padapter->mppriv.rx_pktcount_filter_out);
-+	} else if (bQueryPhy) {
-+		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
-+		rtw_dump_phy_rx_counters(padapter, &rx_counter);
-+
-+		RTW_INFO("%s: OFDM_FA =%d\n", __func__, rx_counter.rx_ofdm_fa);
-+		RTW_INFO("%s: CCK_FA =%d\n", __func__, rx_counter.rx_cck_fa);
-+		sprintf(extra, "Phy Received packet OK:%d CRC error:%d FA Counter: %d", rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_cck_fa + rx_counter.rx_ofdm_fa);
-+
-+
-+	} else if (bQueryMac) {
-+		_rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter));
-+		rtw_dump_mac_rx_counters(padapter, &rx_counter);
-+		sprintf(extra, "Mac Received packet OK: %d , CRC error: %d , Drop Packets: %d\n",
-+			rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_pkt_drop);
-+
-+	}
-+
-+	if (bmon == 1) {
-+		ret = sscanf(input, "mon=%d", &bmon);
-+
-+		if (bmon == 1) {
-+			pmppriv->rx_bindicatePkt = _TRUE;
-+			sprintf(extra, "Indicating Receive Packet to network start\n");
-+		} else {
-+			pmppriv->rx_bindicatePkt = _FALSE;
-+			sprintf(extra, "Indicating Receive Packet to network Stop\n");
-+		}
-+	}
-+	if (bSmpCfg == 1) {
-+		ret = sscanf(input, "smpcfg=%d", &bSmpCfg);
-+
-+		if (bSmpCfg == 1) {
-+			pmppriv->bRTWSmbCfg = _TRUE;
-+			sprintf(extra , "Indicate By Simple Config Format\n");
-+			SetPacketRx(padapter, _TRUE, _TRUE);
-+		} else {
-+			pmppriv->bRTWSmbCfg = _FALSE;
-+			sprintf(extra , "Indicate By Normal Format\n");
-+			SetPacketRx(padapter, _TRUE, _FALSE);
-+		}
-+	}
-+
-+	if (pmppriv->bloopback == _TRUE) {
-+		sprintf(extra , "Enter MAC LoopBack mode\n");
-+#if defined(CONFIG_RTL8814B)
-+		/* 1. No adhoc, 2. Enable short cut */
-+		rtw_write32(padapter, 0x100, 0x0B000EFF);
-+#else
-+		rtw_write32(padapter, 0x100, 0x0B0106FF);
-+#endif
-+		RTW_INFO("0x100 :0x%x", rtw_read32(padapter, 0x100));
-+		rtw_write16(padapter, 0x608, 0x30c);
-+		RTW_INFO("0x608 :0x%x", rtw_read32(padapter, 0x608));
-+	}
-+
-+	wrqu->length = strlen(extra) + 1;
-+
-+	return 0;
-+}
-+
-+
-+int rtw_mp_trx_query(struct net_device *dev,
-+		     struct iw_request_info *info,
-+		     struct iw_point *wrqu, char *extra)
-+{
-+	u32 txok, txfail, rxok, rxfail, rxfilterout;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	PMPT_CONTEXT	pMptCtx		=	&(padapter->mppriv.mpt_ctx);
-+	RT_PMAC_TX_INFO	PMacTxInfo	=	pMptCtx->PMacTxInfo;
-+
-+	if (PMacTxInfo.bEnPMacTx == TRUE)
-+		txok = hal_mpt_query_phytxok(padapter);
-+	else
-+		txok = padapter->mppriv.tx.sended;
-+
-+	txfail = 0;
-+	rxok = padapter->mppriv.rx_pktcount;
-+	rxfail = padapter->mppriv.rx_crcerrpktcount;
-+	rxfilterout = padapter->mppriv.rx_pktcount_filter_out;
-+
-+	_rtw_memset(extra, '\0', 128);
-+
-+	sprintf(extra, "Tx OK:%d, Tx Fail:%d, Rx OK:%d, CRC error:%d ,Rx Filter out:%d\n", txok, txfail, rxok, rxfail, rxfilterout);
-+
-+	wrqu->length = strlen(extra) + 1;
-+
-+	return 0;
-+}
-+
-+
-+int rtw_mp_pwrtrk(struct net_device *dev,
-+		  struct iw_request_info *info,
-+		  struct iw_point *wrqu, char *extra)
-+{
-+	u8 enable;
-+	u32 thermal;
-+	s32 ret;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	u8 input[RTW_IWD_MAX_LEN];
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length))
-+		return -EFAULT;
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	_rtw_memset(extra, 0, wrqu->length);
-+
-+	enable = 1;
-+	if (wrqu->length > 1) {
-+		/* not empty string*/
-+		if (strncmp(input, "stop", 4) == 0) {
-+			enable = 0;
-+			sprintf(extra, "mp tx power tracking stop");
-+		} else if (sscanf(input, "ther=%d", &thermal) == 1) {
-+			ret = SetThermalMeter(padapter, (u8)thermal);
-+			if (ret == _FAIL)
-+				return -EPERM;
-+			sprintf(extra, "mp tx power tracking start,target value=%d ok", thermal);
-+		} else
-+			return -EINVAL;
-+	}
-+
-+	ret = SetPowerTracking(padapter, enable);
-+	if (ret == _FAIL)
-+		return -EPERM;
-+
-+	wrqu->length = strlen(extra);
-+
-+	return 0;
-+}
-+
-+
-+
-+int rtw_mp_psd(struct net_device *dev,
-+	       struct iw_request_info *info,
-+	       struct iw_point *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	u8 input[RTW_IWD_MAX_LEN];
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, (wrqu->length + 1)))
-+		return -EFAULT;
-+
-+	_rtw_memset(input, 0, sizeof(input));
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	input[wrqu->length] = '\0';
-+	strcpy(extra, input);
-+
-+	wrqu->length = mp_query_psd(padapter, extra);
-+
-+	return 0;
-+}
-+
-+
-+int rtw_mp_thermal(struct net_device *dev,
-+		   struct iw_request_info *info,
-+		   struct iw_point *wrqu, char *extra)
-+{
-+	u8 val[4] = {0};
-+	u8 ret = 0;
-+	u16 ther_path_addr[4] = {0};
-+	u16 cnt = 1;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+	int rfpath = RF_PATH_A;
-+
-+#ifdef CONFIG_RTL8188E
-+	ther_path_addr[0] = EEPROM_THERMAL_METER_88E;
-+#endif
-+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
-+	ther_path_addr[0] = EEPROM_THERMAL_METER_8812;
-+#endif
-+#ifdef CONFIG_RTL8192E
-+	ther_path_addr[0] = EEPROM_THERMAL_METER_8192E;
-+#endif
-+#ifdef CONFIG_RTL8192F
-+	ther_path_addr[0] = EEPROM_THERMAL_METER_8192F;
-+#endif
-+#ifdef CONFIG_RTL8723B
-+	ther_path_addr[0] = EEPROM_THERMAL_METER_8723B;
-+#endif
-+#ifdef CONFIG_RTL8703B
-+	ther_path_addr[0] = EEPROM_THERMAL_METER_8703B;
-+#endif
-+#ifdef CONFIG_RTL8723D
-+	ther_path_addr[0] = EEPROM_THERMAL_METER_8723D;
-+#endif
-+#ifdef CONFIG_RTL8188F
-+	ther_path_addr[0] = EEPROM_THERMAL_METER_8188F;
-+#endif
-+#ifdef CONFIG_RTL8188GTV
-+	ther_path_addr[0] = EEPROM_THERMAL_METER_8188GTV;
-+#endif
-+#ifdef CONFIG_RTL8822B
-+	ther_path_addr[0] = EEPROM_THERMAL_METER_8822B;
-+#endif
-+#ifdef CONFIG_RTL8821C
-+	ther_path_addr[0] = EEPROM_THERMAL_METER_8821C;
-+#endif
-+#ifdef CONFIG_RTL8710B
-+	ther_path_addr[0] = EEPROM_THERMAL_METER_8710B;
-+#endif
-+#ifdef CONFIG_RTL8822C
-+	ther_path_addr[0]  = EEPROM_THERMAL_METER_A_8822C;
-+	ther_path_addr[1]  = EEPROM_THERMAL_METER_B_8822C;
-+#endif
-+#ifdef CONFIG_RTL8814B
-+	ther_path_addr[0] = EEPROM_THERMAL_METER_A_8814B;
-+	ther_path_addr[1] = EEPROM_THERMAL_METER_B_8814B;
-+	ther_path_addr[2] = EEPROM_THERMAL_METER_C_8814B;
-+	ther_path_addr[3] = EEPROM_THERMAL_METER_D_8814B;
-+#endif
-+#ifdef CONFIG_RTL8723F
-+	ther_path_addr[0] = EEPROM_THERMAL_METER_8723F;
-+#endif
-+
-+	if (copy_from_user(extra, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	if ((strncmp(extra, "write", 6) == 0)) {
-+		int i;
-+		u16 raw_cursize = 0, raw_maxsize = 0;
-+#ifdef RTW_HALMAC
-+		raw_maxsize = efuse_GetavailableSize(padapter);
-+#else
-+		efuse_GetCurrentSize(padapter, &raw_cursize);
-+		raw_maxsize = efuse_GetMaxSize(padapter);
-+#endif
-+		RTW_INFO("[eFuse available raw size]= %d bytes\n", raw_maxsize - raw_cursize);
-+		if (2 > raw_maxsize - raw_cursize) {
-+			RTW_INFO("no available efuse!\n");
-+			return -EFAULT;
-+		}
-+
-+		for (i = 0; i < hal_spec->rf_reg_path_num; i++) {
-+				GetThermalMeter(padapter, i , &val[i]);
-+				if (ther_path_addr[i] != 0 && val[i] != 0) {
-+					if (rtw_efuse_map_write(padapter, ther_path_addr[i], cnt, &val[i]) == _FAIL) {
-+						RTW_INFO("Error efuse write thermal addr 0x%x ,val = 0x%x\n", ther_path_addr[i], val[i]);
-+						return -EFAULT;
-+					}
-+				} else {
-+						RTW_INFO("Error efuse write thermal Null addr,val \n");
-+						return -EFAULT;
-+				}
-+		}
-+		_rtw_memset(extra, 0, wrqu->length);
-+		sprintf(extra, " efuse write ok :%d", val[0]);
-+	} else {
-+		ret = sscanf(extra, "%d", &rfpath);
-+		if (ret < 1) {
-+			rfpath = RF_PATH_A;
-+			RTW_INFO("default thermal of path(%d)\n", rfpath);
-+		}
-+		if (rfpath >= hal_spec->rf_reg_path_num)
-+			return -EINVAL;
-+
-+		RTW_INFO("read thermal of path(%d)\n", rfpath);
-+		GetThermalMeter(padapter, rfpath, &val[0]);
-+
-+		_rtw_memset(extra, 0, wrqu->length);
-+		sprintf(extra, "%d", val[0]);
-+	}
-+	wrqu->length = strlen(extra);
-+
-+	return 0;
-+}
-+
-+
-+
-+int rtw_mp_reset_stats(struct net_device *dev,
-+		       struct iw_request_info *info,
-+		       struct iw_point *wrqu, char *extra)
-+{
-+	struct mp_priv *pmp_priv;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+
-+	pmp_priv = &padapter->mppriv;
-+
-+	pmp_priv->tx.sended = 0;
-+	pmp_priv->tx_pktcount = 0;
-+	pmp_priv->rx_pktcount = 0;
-+	pmp_priv->rx_pktcount_filter_out = 0;
-+	pmp_priv->rx_crcerrpktcount = 0;
-+
-+	rtw_reset_phy_rx_counters(padapter);
-+	rtw_reset_mac_rx_counters(padapter);
-+
-+	_rtw_memset(extra, 0, wrqu->length);
-+	sprintf(extra, "mp_reset_stats ok\n");
-+	wrqu->length = strlen(extra);
-+
-+	return 0;
-+}
-+
-+
-+int rtw_mp_dump(struct net_device *dev,
-+		struct iw_request_info *info,
-+		struct iw_point *wrqu, char *extra)
-+{
-+	struct mp_priv *pmp_priv;
-+	u8 input[RTW_IWD_MAX_LEN];
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+
-+	pmp_priv = &padapter->mppriv;
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length))
-+		return -EFAULT;
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	if (strncmp(input, "all", 4) == 0) {
-+		mac_reg_dump(RTW_DBGDUMP, padapter);
-+		bb_reg_dump(RTW_DBGDUMP, padapter);
-+		rf_reg_dump(RTW_DBGDUMP, padapter);
-+	}
-+	return 0;
-+}
-+
-+
-+int rtw_mp_phypara(struct net_device *dev,
-+		   struct iw_request_info *info,
-+		   struct iw_point *wrqu, char *extra)
-+{
-+
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
-+	char input[RTW_IWD_MAX_LEN];
-+	u32		invalxcap = 0, ret = 0, bwrite_xcap = 0, hwxtaladdr = 0;
-+	u16		pgval;
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length))
-+		return -EFAULT;
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	RTW_INFO("%s:priv in=%s\n", __func__, input);
-+	bwrite_xcap = (strncmp(input, "write_xcap=", 11) == 0) ? 1 : 0;
-+
-+	if (bwrite_xcap == 1) {
-+		ret = sscanf(input, "write_xcap=%d", &invalxcap);
-+		invalxcap = invalxcap & 0x7f; /* xtal bit 0 ~6 */
-+		RTW_INFO("get crystal_cap %d\n", invalxcap);
-+
-+		if (IS_HARDWARE_TYPE_8822C(padapter) && ret == 1) {
-+			hwxtaladdr = 0x110;
-+			pgval = invalxcap | 0x80; /* reserved default bit7 on */
-+			pgval = pgval | pgval << 8; /* xtal xi/xo efuse 0x110 0x111 */
-+
-+			RTW_INFO("Get crystal_cap 0x%x\n", pgval);
-+			if (rtw_efuse_map_write(padapter, hwxtaladdr, 2, (u8*)&pgval) == _FAIL) {
-+					RTW_INFO("%s: rtw_efuse_map_write xcap error!!\n", __func__);
-+					sprintf(extra, "write xcap pgdata fail");
-+					ret = -EFAULT;
-+			} else
-+					sprintf(extra, "write xcap pgdata ok");
-+
-+		}
-+	} else {
-+		ret = sscanf(input, "xcap=%d", &invalxcap);
-+
-+		if (ret == 1) {
-+			pHalData->crystal_cap = (u8)invalxcap;
-+			RTW_INFO("%s:crystal_cap=%d\n", __func__, pHalData->crystal_cap);
-+
-+			if (rtw_phydm_set_crystal_cap(padapter, pHalData->crystal_cap) == _FALSE) {
-+				RTW_ERR("set crystal_cap failed\n");
-+				rtw_warn_on(1);
-+			}
-+			sprintf(extra, "Set xcap=%d", invalxcap);
-+		}
-+	}
-+
-+	wrqu->length = strlen(extra) + 1;
-+	return ret;
-+}
-+
-+
-+int rtw_mp_SetRFPath(struct net_device *dev,
-+		     struct iw_request_info *info,
-+		     struct iw_point *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	char input[RTW_IWD_MAX_LEN];
-+	int		bMain = 1, bTurnoff = 1;
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	u8 ret = _TRUE;
-+#endif
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length))
-+		return -EFAULT;
-+
-+	RTW_INFO("%s:iwpriv in=%s\n", __func__, input);
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	bMain = strncmp(input, "1", 2); /* strncmp TRUE is 0*/
-+	bTurnoff = strncmp(input, "0", 3); /* strncmp TRUE is 0*/
-+
-+	_rtw_memset(extra, 0, wrqu->length);
-+#ifdef CONFIG_ANTENNA_DIVERSITY
-+	if (bMain == 0)
-+		ret = rtw_mp_set_antdiv(padapter, _TRUE);
-+	else
-+		ret = rtw_mp_set_antdiv(padapter, _FALSE);
-+	if (ret == _FALSE)
-+		RTW_INFO("%s:ANTENNA_DIVERSITY FAIL\n", __func__);
-+#endif
-+
-+	if (bMain == 0) {
-+		MP_PHY_SetRFPathSwitch(padapter, _TRUE);
-+		RTW_INFO("%s:PHY_SetRFPathSwitch=TRUE\n", __func__);
-+		sprintf(extra, "mp_setrfpath Main\n");
-+
-+	} else if (bTurnoff == 0) {
-+		MP_PHY_SetRFPathSwitch(padapter, _FALSE);
-+		RTW_INFO("%s:PHY_SetRFPathSwitch=FALSE\n", __func__);
-+		sprintf(extra, "mp_setrfpath Aux\n");
-+	} else {
-+		bMain = MP_PHY_QueryRFPathSwitch(padapter);
-+		RTW_INFO("%s:Query RF Path = %s\n", __func__, (bMain ? "Main":"Aux"));
-+		sprintf(extra, "RF Path %s\n" , (bMain ? "1":"0"));
-+	}
-+
-+	wrqu->length = strlen(extra);
-+
-+	return 0;
-+}
-+
-+
-+int rtw_mp_switch_rf_path(struct net_device *dev,
-+			struct iw_request_info *info,
-+			struct iw_point *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	struct mp_priv *pmp_priv;
-+	char input[RTW_IWD_MAX_LEN];
-+	char *pch;
-+	int		bwlg = 1, bwla = 1, btg = 1, bbt=1;
-+	u8 ret = 0;
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length))
-+		return -EFAULT;
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	pmp_priv = &padapter->mppriv;
-+
-+	RTW_INFO("%s: in=%s\n", __func__, input);
-+
-+	_rtw_memset(extra, '\0', wrqu->length);
-+	pch = extra;
-+#ifdef CONFIG_RTL8821C /* only support for 8821c wlg/wla/btg/bt RF switch path */
-+	if ((strncmp(input, "WLG", 3) == 0) || (strncmp(input, "1", 1) == 0)) {
-+		pmp_priv->rf_path_cfg = SWITCH_TO_WLG;
-+		pch += sprintf(pch, "switch rf path WLG\n");
-+
-+	} else if ((strncmp(input, "WLA", 3) == 0) || (strncmp(input, "2", 1) == 0)) {
-+		pmp_priv->rf_path_cfg = SWITCH_TO_WLA;
-+		pch += sprintf(pch, "switch rf path WLA\n");
-+
-+	} else if ((strncmp(input, "BTG", 3) == 0) || (strncmp(input, "0", 1) == 0)) {
-+		pmp_priv->rf_path_cfg = SWITCH_TO_BTG;
-+		pch += sprintf(pch, "switch rf path BTG\n");
-+
-+	} else if ((strncmp(input, "BT", 3) == 0) || (strncmp(input, "3", 1) == 0)) {
-+		pmp_priv->rf_path_cfg = SWITCH_TO_BT;
-+		pch += sprintf(pch, "switch rf path BT\n");
-+	} else {
-+		pmp_priv->rf_path_cfg = SWITCH_TO_WLG;
-+		pch += sprintf(pch, "Error input, default set WLG\n");
-+		return -EFAULT;
-+	}
-+
-+	mp_phy_switch_rf_path_set(padapter, &pmp_priv->rf_path_cfg);
-+#endif
-+	wrqu->length = strlen(extra);
-+
-+	return ret;
-+
-+}
-+int rtw_mp_QueryDrv(struct net_device *dev,
-+		    struct iw_request_info *info,
-+		    union iwreq_data *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	char input[RTW_IWD_MAX_LEN];
-+	int	qAutoLoad = 1;
-+
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->data.length))
-+		return -EFAULT;
-+
-+	if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+	RTW_INFO("%s:iwpriv in=%s\n", __func__, input);
-+
-+	qAutoLoad = strncmp(input, "autoload", 8); /* strncmp TRUE is 0*/
-+
-+	if (qAutoLoad == 0) {
-+		RTW_INFO("%s:qAutoLoad\n", __func__);
-+
-+		if (pHalData->bautoload_fail_flag)
-+			sprintf(extra, "fail");
-+		else
-+			sprintf(extra, "ok");
-+	}
-+	wrqu->data.length = strlen(extra) + 1;
-+	return 0;
-+}
-+
-+
-+int rtw_mp_PwrCtlDM(struct net_device *dev,
-+		    struct iw_request_info *info,
-+		    struct iw_point *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	u8 input[RTW_IWD_MAX_LEN];
-+	u8		pwrtrk_state = 0;
-+	u8		pwtk_type[5][25] = {"Thermal tracking off","Thermal tracking on",
-+					"TSSI tracking off","TSSI tracking on","TSSI calibration"};
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length))
-+		return -EFAULT;
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	input[wrqu->length - 1] = '\0';
-+	RTW_INFO("%s: in=%s\n", __func__, input);
-+
-+	if (wrqu->length == 2) {
-+		if(input[0] >= '0' && input[0] <= '4') {
-+			pwrtrk_state = rtw_atoi(input);
-+			MPT_PwrCtlDM(padapter, pwrtrk_state);
-+			sprintf(extra, "PwrCtlDM start %s\n" , pwtk_type[pwrtrk_state]);
-+		} else {
-+			sprintf(extra, "Error unknown number ! Please check your input number\n"
-+				" 0 : Thermal tracking off\n 1 : Thermal tracking on\n 2 : TSSI tracking off\n"
-+				" 3 : TSSI tracking on\n 4 : TSSI calibration\n");
-+		}
-+		wrqu->length = strlen(extra);
-+
-+		return 0;
-+	}
-+	if (strncmp(input, "start", 5) == 0 || strncmp(input, "thertrk on", 10) == 0) {/* strncmp TRUE is 0*/
-+		pwrtrk_state = 1;
-+		sprintf(extra, "PwrCtlDM start %s\n" , pwtk_type[pwrtrk_state]);
-+	} else if (strncmp(input, "thertrk off", 11) == 0 || strncmp(input, "stop", 5) == 0) {
-+		pwrtrk_state = 0;
-+		sprintf(extra, "PwrCtlDM stop %s\n" , pwtk_type[pwrtrk_state]);
-+	} else if (strncmp(input, "tssitrk off", 11) == 0){
-+		pwrtrk_state = 2;
-+		sprintf(extra, "PwrCtlDM stop %s\n" , pwtk_type[pwrtrk_state]);
-+	} else if (strncmp(input, "tssitrk on", 10) == 0){
-+		pwrtrk_state = 3;
-+		sprintf(extra, "PwrCtlDM start %s\n" , pwtk_type[pwrtrk_state]);
-+	} else if (strncmp(input, "tssik", 5) == 0){
-+		pwrtrk_state = 4;
-+		sprintf(extra, "PwrCtlDM start %s\n" , pwtk_type[pwrtrk_state]);
-+	} else {
-+		sprintf(extra, "Error input !!!\n"
-+			" thertrk off : Thermal tracking off\n thertrk on : Thermal tracking on\n"
-+			" tssitrk off : TSSI tracking off\n tssitrk on : TSSI tracking on\n tssik : TSSI calibration\n\n"
-+			" 0 : Thermal tracking off\n 1 : Thermal tracking on\n 2 : TSSI tracking off\n"
-+			" 3 : TSSI tracking on\n 4 : TSSI calibration\n");
-+		wrqu->length = strlen(extra);
-+		return 0;
-+	}
-+
-+	MPT_PwrCtlDM(padapter, pwrtrk_state);
-+	wrqu->length = strlen(extra);
-+
-+	return 0;
-+}
-+
-+int rtw_mp_iqk(struct net_device *dev,
-+		 struct iw_request_info *info,
-+		 struct iw_point *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+
-+	rtw_mp_trigger_iqk(padapter);
-+
-+	return 0;
-+}
-+
-+int rtw_mp_lck(struct net_device *dev,
-+		 struct iw_request_info *info,
-+		 struct iw_point *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+
-+	rtw_mp_trigger_lck(padapter);
-+
-+	return 0;
-+}
-+
-+int rtw_mp_dpk(struct net_device *dev,
-+			struct iw_request_info *info,
-+			union iwreq_data *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+	char *pch;
-+
-+	u8 ips_mode = IPS_NUM; /* init invalid value */
-+	u8 lps_mode = PS_MODE_NUM; /* init invalid value */
-+
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+
-+	*(extra + wrqu->data.length) = '\0';
-+	pch = extra;
-+
-+	if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) {
-+			pDM_Odm->dpk_info.is_dpk_enable = 0;
-+			halrf_dpk_enable_disable(pDM_Odm);
-+			pch += sprintf(pch, "set dpk off\n");
-+
-+	} else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) {
-+			pDM_Odm->dpk_info.is_dpk_enable = 1;
-+			halrf_dpk_enable_disable(pDM_Odm);
-+			pch += sprintf(pch, "set dpk on\n");
-+	} else	{
-+#ifdef CONFIG_LPS
-+			lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */
-+			rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
-+#endif
-+#ifdef CONFIG_IPS
-+			ips_mode = pwrctrlpriv->ips_mode;/* keep org value */
-+			rtw_pm_set_ips(padapter, IPS_NONE);
-+#endif
-+			rtw_mp_trigger_dpk(padapter);
-+	if (padapter->registrypriv.mp_mode == 0) {
-+#ifdef CONFIG_IPS
-+			rtw_pm_set_ips(padapter, ips_mode);
-+#endif /* CONFIG_IPS */
-+
-+#ifdef CONFIG_LPS
-+			rtw_pm_set_lps(padapter, lps_mode);
-+#endif /* CONFIG_LPS */
-+	}
-+			pch += sprintf(pch, "set dpk trigger\n");
-+	}
-+
-+	wrqu->data.length = strlen(extra);
-+
-+	return 0;
-+}
-+
-+int rtw_mp_get_tsside(struct net_device *dev,
-+			 struct iw_request_info *info,
-+			 struct iw_point *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+ 	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
-+	char input[RTW_IWD_MAX_LEN];
-+	u8 rfpath;
-+	u32 tssi_de;
-+
-+	u8 legal_param_num = 1;
-+	int param_num;
-+	char pout_str_buf[7];
-+	u8 signed_flag = 0;
-+	int integer_num;
-+	u32 decimal_num;
-+	s32 pout;
-+	char *pextra;
-+	int i;
-+
-+	#ifdef CONFIG_RTL8723F
-+	/*
-+	* rtwpriv wlan0 mp_get_tsside rf_path pout
-+	* rf_path : 0 ~ 1
-+	* pout : -15.000 ~ 25.000
-+	* ex : rtwpriv wlan0 mp_get_tsside 0 -12.123
-+	*/
-+	legal_param_num = 2;
-+	#endif
-+	if (wrqu->length > 128)
-+		return -EFAULT;
-+
-+	_rtw_memset(input, 0, sizeof(input));
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	param_num = sscanf(input, "%hhu %7s", &rfpath, pout_str_buf);
-+
-+	/* Check parameter format*/
-+	if(param_num != legal_param_num)
-+		goto invalid_param_format;
-+
-+	if(rfpath <0 || 3 < rfpath)
-+		goto invalid_param_format;
-+
-+#ifdef CONFIG_RTL8723F
-+	/* Convert pout from floating-point to integer
-+	 * For Floating-Point Precision, pout*1000
-+	 */
-+	if(pout_str_buf[0] == '-')
-+		signed_flag = 1;
-+	i = sscanf(pout_str_buf, "%d.%3u", &integer_num, &decimal_num);
-+	pout = integer_num * 1000;
-+	if(i == 2) {
-+		/* Convert decimal number
-+		 * ex : 0.1 => 100, -0.1 => 100
-+		 */
-+		decimal_num = (decimal_num < 10) ? decimal_num * 100 : decimal_num;
-+		decimal_num = (decimal_num < 100) ? decimal_num * 10 : decimal_num;
-+		pout += ((pout < 0 || signed_flag == 1) ? -decimal_num : decimal_num);
-+	}
-+	if(pout < -15000 || 25000 < pout)
-+		goto invalid_param_format;
-+#endif
-+
-+#ifdef CONFIG_RTL8723F
-+	/* For Floating-Point Precision, pout */
-+	tssi_de = halrf_get_online_tssi_de(pDM_Odm, rfpath, pout);
-+#else
-+	tssi_de = halrf_tssi_get_de(pDM_Odm, rfpath);
-+#endif
-+
-+	if (rfpath == 0)
-+		sprintf(extra, "patha=%d", tssi_de);
-+	else if (rfpath == 1)
-+		sprintf(extra, "pathb=%d", tssi_de);
-+	else if (rfpath == 2)
-+		sprintf(extra, "pathc=%d", tssi_de);
-+	else if (rfpath == 3)
-+		sprintf(extra, "pathd=%d", tssi_de);
-+
-+	wrqu->length = strlen(extra);
-+	return 0;
-+
-+invalid_param_format:
-+	sprintf(extra, "Invalid command format, please indicate RF path 0/1/2/3");
-+#ifdef CONFIG_RTL8723F
-+	pextra = extra + strlen(extra);
-+	sprintf(pextra, " and pout value : -15.000 ~ 25.000\n");
-+#endif
-+	wrqu->length = strlen(extra);
-+
-+	return 0;
-+}
-+
-+int rtw_mp_set_tsside(struct net_device *dev,
-+		   struct iw_request_info *info,
-+		   struct iw_point *wrqu, char *extra)
-+{
-+	u32 tsside_a = 0, tsside_b = 0, tsside_c = 0, tsside_d = 0;
-+	char input[RTW_IWD_MAX_LEN];
-+
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length))
-+		return -EFAULT;
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	if (sscanf(input, "patha=%d", &tsside_a) == 1) {
-+		sprintf(extra, "Set TSSI DE path_A: %d", tsside_a);
-+		halrf_tssi_set_de_for_tx_verify(pDM_Odm, tsside_a, RF_PATH_A);
-+		mpt_trigger_tssi_tracking(padapter, RF_PATH_A);
-+
-+	} else if (sscanf(input, "pathb=%d", &tsside_b) == 1) {
-+		sprintf(extra, "Set TSSI DE path_B: %d", tsside_b);
-+		halrf_tssi_set_de_for_tx_verify(pDM_Odm, tsside_b, RF_PATH_B);
-+		mpt_trigger_tssi_tracking(padapter, RF_PATH_B);
-+
-+	} else if (sscanf(input, "pathc=%d", &tsside_c) == 1) {
-+		sprintf(extra, "Set TSSI DE path_C: %d", tsside_c);
-+		halrf_tssi_set_de_for_tx_verify(pDM_Odm, tsside_c, RF_PATH_C);
-+		mpt_trigger_tssi_tracking(padapter, RF_PATH_C);
-+
-+	} else if (sscanf(input, "pathd=%d", &tsside_d) == 1) {
-+		sprintf(extra, "Set TSSI DE path_D: %d", tsside_d);
-+		halrf_tssi_set_de_for_tx_verify(pDM_Odm, tsside_d, RF_PATH_D);
-+		mpt_trigger_tssi_tracking(padapter, RF_PATH_D);
-+
-+	} else
-+		sprintf(extra, "Invalid command format, please input TSSI DE value within patha/b/c/d=xyz");
-+
-+	wrqu->length = strlen(extra);
-+
-+	return 0;
-+}
-+
-+int rtw_mp_getver(struct net_device *dev,
-+		  struct iw_request_info *info,
-+		  union iwreq_data *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	struct mp_priv *pmp_priv;
-+
-+	pmp_priv = &padapter->mppriv;
-+
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+
-+	sprintf(extra, "rtwpriv=%d\n", RTWPRIV_VER_INFO);
-+	wrqu->data.length = strlen(extra);
-+	return 0;
-+}
-+
-+
-+int rtw_mp_mon(struct net_device *dev,
-+	       struct iw_request_info *info,
-+	       union iwreq_data *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct hal_ops *pHalFunc = &padapter->hal_func;
-+	NDIS_802_11_NETWORK_INFRASTRUCTURE networkType;
-+	int bstart = 1, bstop = 1;
-+
-+	networkType = Ndis802_11Infrastructure;
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+
-+	*(extra + wrqu->data.length) = '\0';
-+	rtw_pm_set_ips(padapter, IPS_NONE);
-+	LeaveAllPowerSaveMode(padapter);
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	if (init_mp_priv(padapter) == _FAIL)
-+		RTW_INFO("%s: initialize MP private data Fail!\n", __func__);
-+	padapter->mppriv.channel = 6;
-+
-+	bstart = strncmp(extra, "start", 5); /* strncmp TRUE is 0*/
-+	bstop = strncmp(extra, "stop", 4); /* strncmp TRUE is 0*/
-+	if (bstart == 0) {
-+		mp_join(padapter, WIFI_FW_ADHOC_STATE);
-+		SetPacketRx(padapter, _TRUE, _FALSE);
-+		SetChannel(padapter);
-+		pmp_priv->rx_bindicatePkt = _TRUE;
-+		pmp_priv->bRTWSmbCfg = _TRUE;
-+		sprintf(extra, "monitor mode start\n");
-+	} else if (bstop == 0) {
-+		SetPacketRx(padapter, _FALSE, _FALSE);
-+		pmp_priv->rx_bindicatePkt = _FALSE;
-+		pmp_priv->bRTWSmbCfg = _FALSE;
-+		padapter->registrypriv.mp_mode = 1;
-+		pHalFunc->hal_deinit(padapter);
-+		padapter->registrypriv.mp_mode = 0;
-+		pHalFunc->hal_init(padapter);
-+		/*rtw_disassoc_cmd(padapter, 0, 0);*/
-+		if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+			rtw_disassoc_cmd(padapter, 500, 0);
-+			rtw_indicate_disconnect(padapter, 0, _FALSE);
-+			/*rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);*/
-+		}
-+		rtw_pm_set_ips(padapter, IPS_NORMAL);
-+		sprintf(extra, "monitor mode Stop\n");
-+	}
-+#endif
-+	wrqu->data.length = strlen(extra);
-+	return 0;
-+}
-+
-+int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra)
-+{
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	char *pextra = extra;
-+
-+	switch (pmp_priv->mode) {
-+
-+	case MP_PACKET_TX:
-+		if (bStartTest == 0) {
-+			pmp_priv->tx.stop = 1;
-+			pmp_priv->mode = MP_ON;
-+			#ifdef CONFIG_RTL8822B
-+			rtw_write8(padapter, 0x838, 0x61);
-+			#endif
-+			sprintf(extra, "Stop continuous Tx");
-+		} else if (pmp_priv->tx.stop == 1) {
-+			pextra = extra + strlen(extra);
-+			pextra += sprintf(pextra, "\nStart continuous DA=ffffffffffff len=1500 count=%u\n", pmp_priv->tx.count);
-+			pmp_priv->tx.stop = 0;
-+			#ifdef CONFIG_RTL8822B
-+			rtw_write8(padapter, 0x838, 0x6d);
-+			#endif
-+			SetPacketTx(padapter);
-+		} else
-+			return -EFAULT;
-+		return 0;
-+	case MP_SINGLE_TONE_TX:
-+		if (bStartTest != 0)
-+			strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.");
-+		SetSingleToneTx(padapter, (u8)bStartTest);
-+		break;
-+	case MP_CONTINUOUS_TX:
-+		if (bStartTest != 0)
-+			strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.");
-+		SetContinuousTx(padapter, (u8)bStartTest);
-+		break;
-+	case MP_CARRIER_SUPPRISSION_TX:
-+		if (bStartTest != 0) {
-+			if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_11M)
-+				strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.");
-+			else
-+				strcat(extra, "\nSpecify carrier suppression but not CCK rate");
-+		}
-+		SetCarrierSuppressionTx(padapter, (u8)bStartTest);
-+		break;
-+	case MP_SINGLE_CARRIER_TX:
-+		if (bStartTest != 0)
-+			strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.");
-+		SetSingleCarrierTx(padapter, (u8)bStartTest);
-+		break;
-+
-+	default:
-+		sprintf(extra, "Error! Continuous-Tx is not on-going.");
-+		return -EFAULT;
-+	}
-+
-+	if (bStartTest == 1 && pmp_priv->mode != MP_ON) {
-+		struct mp_priv *pmp_priv = &padapter->mppriv;
-+
-+		if (pmp_priv->tx.stop == 0) {
-+			pmp_priv->tx.stop = 1;
-+			rtw_msleep_os(5);
-+		}
-+#ifdef CONFIG_80211N_HT
-+		if(padapter->registrypriv.ht_enable &&
-+			is_supported_ht(padapter->registrypriv.wireless_mode))
-+			pmp_priv->tx.attrib.ht_en = 1;
-+#endif
-+		pmp_priv->tx.stop = 0;
-+		pmp_priv->tx.count = 1;
-+		SetPacketTx(padapter);
-+	} else
-+		pmp_priv->mode = MP_ON;
-+
-+#if defined(CONFIG_RTL8812A)
-+	if (IS_HARDWARE_TYPE_8812AU(padapter)) {
-+		/* <20130425, Kordan> Turn off OFDM Rx to prevent from CCA causing Tx hang.*/
-+		if (pmp_priv->mode == MP_PACKET_TX)
-+			phy_set_bb_reg(padapter, rCCAonSec_Jaguar, BIT3, 1);
-+		else
-+			phy_set_bb_reg(padapter, rCCAonSec_Jaguar, BIT3, 0);
-+	}
-+#endif
-+
-+	return 0;
-+}
-+
-+
-+int rtw_mp_tx(struct net_device *dev,
-+	      struct iw_request_info *info,
-+	      union iwreq_data *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	PMPT_CONTEXT		pMptCtx = &(padapter->mppriv.mpt_ctx);
-+	char *pextra = extra;
-+	u32 bandwidth = 0, sg = 0, channel = 6, txpower = 40, rate = 108, ant = 0, txmode = 1, count = 0;
-+	u8 bStartTest = 1, status = 0;
-+#ifdef CONFIG_MP_VHT_HW_TX_MODE
-+	u8 Idx = 0, tmpU1B;
-+#endif
-+	u16 antenna = 0;
-+
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+	RTW_INFO("extra = %s\n", extra);
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (!is_primary_adapter(padapter)) {
-+		sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n");
-+		wrqu->data.length = strlen(extra);
-+		return 0;
-+	}
-+#endif
-+
-+	if (strncmp(extra, "stop", 3) == 0) {
-+		bStartTest = 0; /* To set Stop*/
-+		pmp_priv->tx.stop = 1;
-+		sprintf(extra, "Stop continuous Tx");
-+		status = rtw_mp_pretx_proc(padapter, bStartTest, extra);
-+		wrqu->data.length = strlen(extra);
-+		return status;
-+	} else if (strncmp(extra, "count", 5) == 0) {
-+		if (sscanf(extra, "count=%d", &count) < 1)
-+			RTW_INFO("Got Count=%d]\n", count);
-+		pmp_priv->tx.count = count;
-+		return 0;
-+	} else if (strncmp(extra, "setting", 7) == 0) {
-+		_rtw_memset(extra, 0, wrqu->data.length);
-+		pextra += sprintf(pextra, "Current Setting :\n Channel:%d", pmp_priv->channel);
-+		pextra += sprintf(pextra, "\n Bandwidth:%d", pmp_priv->bandwidth);
-+		pextra += sprintf(pextra, "\n Rate index:%d", pmp_priv->rateidx);
-+		pextra += sprintf(pextra, "\n TxPower index:%d", pmp_priv->txpoweridx);
-+		pextra += sprintf(pextra, "\n Antenna TxPath:%d", pmp_priv->antenna_tx);
-+		pextra += sprintf(pextra, "\n Antenna RxPath:%d", pmp_priv->antenna_rx);
-+		pextra += sprintf(pextra, "\n MP Mode:%d", pmp_priv->mode);
-+		wrqu->data.length = strlen(extra);
-+		return 0;
-+#ifdef CONFIG_MP_VHT_HW_TX_MODE
-+	} else if (strncmp(extra, "pmact", 5) == 0) {
-+		if (strncmp(extra, "pmact=", 6) == 0) {
-+			_rtw_memset(&pMptCtx->PMacTxInfo, 0, sizeof(pMptCtx->PMacTxInfo));
-+			if (strncmp(extra, "pmact=start", 11) == 0) {
-+				pMptCtx->PMacTxInfo.bEnPMacTx = _TRUE;
-+				sprintf(extra, "Set PMac Tx Mode start\n");
-+			} else {
-+				pMptCtx->PMacTxInfo.bEnPMacTx = _FALSE;
-+				sprintf(extra, "Set PMac Tx Mode Stop\n");
-+			}
-+			if (pMptCtx->bldpc == TRUE)
-+				pMptCtx->PMacTxInfo.bLDPC = _TRUE;
-+
-+			if (pMptCtx->bstbc == TRUE)
-+				pMptCtx->PMacTxInfo.bSTBC = _TRUE;
-+
-+			pMptCtx->PMacTxInfo.bSPreamble = pmp_priv->preamble;
-+			pMptCtx->PMacTxInfo.bSGI = pmp_priv->preamble;
-+			pMptCtx->PMacTxInfo.BandWidth = pmp_priv->bandwidth;
-+			pMptCtx->PMacTxInfo.TX_RATE = HwRateToMPTRate(pmp_priv->rateidx);
-+
-+			pMptCtx->PMacTxInfo.Mode = pMptCtx->HWTxmode;
-+
-+			pMptCtx->PMacTxInfo.NDP_sound = FALSE;/*(Adapter.PacketType == NDP_PKT)?TRUE:FALSE;*/
-+
-+			if (padapter->mppriv.pktInterval == 0)
-+				pMptCtx->PMacTxInfo.PacketPeriod = 100;
-+			else
-+				pMptCtx->PMacTxInfo.PacketPeriod = padapter->mppriv.pktInterval;
-+
-+			if (padapter->mppriv.pktLength < 1000)
-+				pMptCtx->PMacTxInfo.PacketLength = 1000;
-+			else
-+				pMptCtx->PMacTxInfo.PacketLength = padapter->mppriv.pktLength;
-+
-+			pMptCtx->PMacTxInfo.PacketPattern  = rtw_random32() % 0xFF;
-+
-+			if (padapter->mppriv.tx_pktcount != 0)
-+				pMptCtx->PMacTxInfo.PacketCount = padapter->mppriv.tx_pktcount;
-+
-+			pMptCtx->PMacTxInfo.Ntx = 0;
-+			for (Idx = 16; Idx < 20; Idx++) {
-+				tmpU1B = (padapter->mppriv.antenna_tx >> Idx) & 1;
-+				if (tmpU1B)
-+					pMptCtx->PMacTxInfo.Ntx++;
-+			}
-+
-+			_rtw_memset(pMptCtx->PMacTxInfo.MacAddress, 0xFF, ETH_ALEN);
-+
-+			PMAC_Get_Pkt_Param(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
-+
-+			if (MPT_IS_CCK_RATE(pMptCtx->PMacTxInfo.TX_RATE))
-+
-+				CCK_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
-+			else {
-+				PMAC_Nsym_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
-+				/* 24 BIT*/
-+				L_SIG_generator(pMptCtx->PMacPktInfo.N_sym, &pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
-+			}
-+			/*	48BIT*/
-+			if (MPT_IS_HT_RATE(pMptCtx->PMacTxInfo.TX_RATE))
-+				HT_SIG_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
-+			else if (MPT_IS_VHT_RATE(pMptCtx->PMacTxInfo.TX_RATE)) {
-+				/*	48BIT*/
-+				VHT_SIG_A_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo);
-+
-+				/*	26/27/29 BIT  & CRC 8 BIT*/
-+				VHT_SIG_B_generator(&pMptCtx->PMacTxInfo);
-+
-+				/* 32 BIT*/
-+				VHT_Delimiter_generator(&pMptCtx->PMacTxInfo);
-+			}
-+
-+			mpt_ProSetPMacTx(padapter);
-+
-+		} else if (strncmp(extra, "pmact,mode=", 11) == 0) {
-+			int txmode = 0;
-+
-+			if (sscanf(extra, "pmact,mode=%d", &txmode) > 0) {
-+				if (txmode == 1) {
-+					pMptCtx->HWTxmode = CONTINUOUS_TX;
-+					sprintf(extra, "\t Config HW Tx mode = CONTINUOUS_TX\n");
-+				} else if (txmode == 2) {
-+					pMptCtx->HWTxmode = OFDM_Single_Tone_TX;
-+					sprintf(extra, "\t Config HW Tx mode = OFDM_Single_Tone_TX\n");
-+				} else {
-+					pMptCtx->HWTxmode = PACKETS_TX;
-+					sprintf(extra, "\t Config HW Tx mode = PACKETS_TX\n");
-+				}
-+			} else {
-+				pMptCtx->HWTxmode = PACKETS_TX;
-+				sprintf(extra, "\t Config HW Tx mode=\n 0 = PACKETS_TX\n 1 = CONTINUOUS_TX\n 2 = OFDM_Single_Tone_TX");
-+			}
-+		} else if (strncmp(extra, "pmact,", 6) == 0) {
-+			int PacketPeriod = 0, PacketLength = 0, PacketCout = 0;
-+			int bldpc = 0, bstbc = 0;
-+
-+			if (sscanf(extra, "pmact,period=%d", &PacketPeriod) > 0) {
-+				padapter->mppriv.pktInterval = PacketPeriod;
-+				RTW_INFO("PacketPeriod=%d\n", padapter->mppriv.pktInterval);
-+				sprintf(extra, "PacketPeriod [1~255]= %d\n", padapter->mppriv.pktInterval);
-+
-+			} else if (sscanf(extra, "pmact,length=%d", &PacketLength) > 0) {
-+				padapter->mppriv.pktLength = PacketLength;
-+				RTW_INFO("PacketPeriod=%d\n", padapter->mppriv.pktLength);
-+				sprintf(extra, "PacketLength[~65535]=%d\n", padapter->mppriv.pktLength);
-+
-+			} else if (sscanf(extra, "pmact,count=%d", &PacketCout) > 0) {
-+				padapter->mppriv.tx_pktcount = PacketCout;
-+				RTW_INFO("Packet Cout =%d\n", padapter->mppriv.tx_pktcount);
-+				sprintf(extra, "Packet Cout =%d\n", padapter->mppriv.tx_pktcount);
-+
-+			} else if (sscanf(extra, "pmact,ldpc=%d", &bldpc) > 0) {
-+				pMptCtx->bldpc = bldpc;
-+				RTW_INFO("Set LDPC =%d\n", pMptCtx->bldpc);
-+				sprintf(extra, "Set LDPC =%d\n", pMptCtx->bldpc);
-+
-+			} else if (sscanf(extra, "pmact,stbc=%d", &bstbc) > 0) {
-+				pMptCtx->bstbc = bstbc;
-+				RTW_INFO("Set STBC =%d\n", pMptCtx->bstbc);
-+				sprintf(extra, "Set STBC =%d\n", pMptCtx->bstbc);
-+			} else
-+				sprintf(extra, "\n period={1~255}\n length={1000~65535}\n count={0~}\n ldpc={0/1}\n stbc={0/1}");
-+
-+		}
-+
-+		wrqu->data.length = strlen(extra);
-+		return 0;
-+#endif
-+	} else {
-+
-+		if (sscanf(extra, "ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d", &channel, &bandwidth, &rate, &txpower, &ant, &txmode) < 6) {
-+			RTW_INFO("Invalid format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\n", channel, bandwidth, rate, txpower, ant, txmode);
-+			_rtw_memset(extra, 0, wrqu->data.length);
-+			pextra += sprintf(pextra, "\n Please input correct format as bleow:\n");
-+			pextra += sprintf(pextra, "\t ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d\n", channel, bandwidth, rate, txpower, ant, txmode);
-+			pextra += sprintf(pextra, "\n [ ch : BGN = <1~14> , A or AC = <36~165> ]");
-+			pextra += sprintf(pextra, "\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]");
-+			pextra += sprintf(pextra, "\n [ rate :	CCK: 1 2 5.5 11M X 2 = < 2 4 11 22 >]");
-+			pextra += sprintf(pextra, "\n [		OFDM: 6 9 12 18 24 36 48 54M X 2 = < 12 18 24 36 48 72 96 108>");
-+			pextra += sprintf(pextra, "\n [		HT 1S2SS MCS0 ~ MCS15 : < [MCS0]=128 ~ [MCS7]=135 ~ [MCS15]=143 >");
-+			pextra += sprintf(pextra, "\n [		HT 3SS MCS16 ~ MCS32 : < [MCS16]=144 ~ [MCS23]=151 ~ [MCS32]=159 >");
-+			pextra += sprintf(pextra, "\n [		VHT 1SS MCS0 ~ MCS9 : < [MCS0]=160 ~ [MCS9]=169 >");
-+			pextra += sprintf(pextra, "\n [ txpower : 1~63 power index");
-+			pextra += sprintf(pextra, "\n [ ant : <A = 1, B = 2, C = 4, D = 8> ,2T ex: AB=3 BC=6 CD=12");
-+			pextra += sprintf(pextra, "\n [ txmode : < 0 = CONTINUOUS_TX, 1 = PACKET_TX, 2 = SINGLE_TONE_TX, 3 = CARRIER_SUPPRISSION_TX, 4 = SINGLE_CARRIER_TX>\n");
-+			wrqu->data.length = strlen(extra);
-+			return status;
-+
-+		} else {
-+			char *pextra = extra;
-+			RTW_INFO("Got format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\n", channel, bandwidth, rate, txpower, ant, txmode);
-+			_rtw_memset(extra, 0, wrqu->data.length);
-+			sprintf(extra, "Change Current channel %d to channel %d", padapter->mppriv.channel , channel);
-+			padapter->mppriv.channel = channel;
-+			SetChannel(padapter);
-+			pHalData->current_channel = channel;
-+
-+			if (bandwidth == 1)
-+				bandwidth = CHANNEL_WIDTH_40;
-+			else if (bandwidth == 2)
-+				bandwidth = CHANNEL_WIDTH_80;
-+			pextra = extra + strlen(pextra);
-+			pextra += sprintf(pextra, "\nChange Current Bandwidth %d to Bandwidth %d", padapter->mppriv.bandwidth, bandwidth);
-+			padapter->mppriv.bandwidth = (u8)bandwidth;
-+			padapter->mppriv.preamble = sg;
-+			SetBandwidth(padapter);
-+			pHalData->current_channel_bw = bandwidth;
-+
-+			pextra += sprintf(pextra, "\nSet power level :%d", txpower);
-+			padapter->mppriv.txpoweridx = (u8)txpower;
-+			pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)txpower;
-+			pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)txpower;
-+			pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)txpower;
-+			pMptCtx->TxPwrLevel[RF_PATH_D]  = (u8)txpower;
-+			SetTxPower(padapter);
-+
-+			RTW_INFO("%s: bw=%d sg=%d\n", __func__, bandwidth, sg);
-+
-+			if (rate <= 0x7f)
-+				rate = wifirate2_ratetbl_inx((u8)rate);
-+			else if (rate < 0xC8)
-+				rate = (rate - 0x80 + MPT_RATE_MCS0);
-+			/*HT  rate 0x80(MCS0)  ~ 0x8F(MCS15) ~ 0x9F(MCS31) 128~159
-+			VHT1SS~2SS rate 0xA0 (VHT1SS_MCS0 44) ~ 0xB3 (VHT2SS_MCS9 #63) 160~179
-+			VHT rate 0xB4 (VHT3SS_MCS0 64) ~ 0xC7 (VHT2SS_MCS9 #83) 180~199
-+			else
-+			VHT rate 0x90(VHT1SS_MCS0) ~ 0x99(VHT1SS_MCS9) 144~153
-+			rate =(rate - MPT_RATE_VHT1SS_MCS0);
-+			*/
-+			RTW_INFO("%s: rate index=%d\n", __func__, rate);
-+			if (rate >= MPT_RATE_LAST)
-+				return -EINVAL;
-+			pextra += sprintf(pextra, "\nSet data rate to %d index %d", padapter->mppriv.rateidx, rate);
-+
-+			padapter->mppriv.rateidx = rate;
-+			pMptCtx->mpt_rate_index = rate;
-+			SetDataRate(padapter);
-+
-+			pextra += sprintf(pextra, "\nSet Antenna Path :%d", ant);
-+			switch (ant) {
-+			case 1:
-+				antenna = ANTENNA_A;
-+				break;
-+			case 2:
-+				antenna = ANTENNA_B;
-+				break;
-+			case 4:
-+				antenna = ANTENNA_C;
-+				break;
-+			case 8:
-+				antenna = ANTENNA_D;
-+				break;
-+			case 3:
-+				antenna = ANTENNA_AB;
-+				break;
-+			case 5:
-+				antenna = ANTENNA_AC;
-+				break;
-+			case 9:
-+				antenna = ANTENNA_AD;
-+				break;
-+			case 6:
-+				antenna = ANTENNA_BC;
-+				break;
-+			case 10:
-+				antenna = ANTENNA_BD;
-+				break;
-+			case 12:
-+				antenna = ANTENNA_CD;
-+				break;
-+			case 7:
-+				antenna = ANTENNA_ABC;
-+				break;
-+			case 14:
-+				antenna = ANTENNA_BCD;
-+				break;
-+			case 11:
-+				antenna = ANTENNA_ABD;
-+				break;
-+			case 15:
-+				antenna = ANTENNA_ABCD;
-+				break;
-+			}
-+			RTW_INFO("%s: antenna=0x%x\n", __func__, antenna);
-+			padapter->mppriv.antenna_tx = antenna;
-+			padapter->mppriv.antenna_rx = antenna;
-+			pHalData->antenna_tx_path = antenna;
-+			SetAntenna(padapter);
-+
-+			if (txmode == 0)
-+				pmp_priv->mode = MP_CONTINUOUS_TX;
-+			else if (txmode == 1) {
-+				pmp_priv->mode = MP_PACKET_TX;
-+				pmp_priv->tx.count = count;
-+			} else if (txmode == 2)
-+				pmp_priv->mode = MP_SINGLE_TONE_TX;
-+			else if (txmode == 3)
-+				pmp_priv->mode = MP_CARRIER_SUPPRISSION_TX;
-+			else if (txmode == 4)
-+				pmp_priv->mode = MP_SINGLE_CARRIER_TX;
-+
-+			status = rtw_mp_pretx_proc(padapter, bStartTest, extra);
-+		}
-+
-+	}
-+
-+	wrqu->data.length = strlen(extra);
-+	return status;
-+}
-+
-+
-+int rtw_mp_rx(struct net_device *dev,
-+	      struct iw_request_info *info,
-+	      union iwreq_data *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	char *pextra = extra;
-+	u32 bandwidth = 0, sg = 0, channel = 6, ant = 0;
-+	u16 antenna = 0;
-+	u8 bStartRx = 0;
-+
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (!is_primary_adapter(padapter)) {
-+		sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n");
-+		wrqu->data.length = strlen(extra);
-+		return 0;
-+	}
-+#endif
-+
-+	if (strncmp(extra, "stop", 4) == 0) {
-+		_rtw_memset(extra, 0, wrqu->data.length);
-+		SetPacketRx(padapter, bStartRx, _FALSE);
-+		pmp_priv->bmac_filter = _FALSE;
-+		sprintf(extra, "Received packet OK:%d CRC error:%d ,Filter out:%d", padapter->mppriv.rx_pktcount, padapter->mppriv.rx_crcerrpktcount, padapter->mppriv.rx_pktcount_filter_out);
-+		wrqu->data.length = strlen(extra);
-+		return 0;
-+
-+	} else if (sscanf(extra, "ch=%d,bw=%d,ant=%d", &channel, &bandwidth, &ant) < 3) {
-+		RTW_INFO("Invalid format [ch=%d,bw=%d,ant=%d]\n", channel, bandwidth, ant);
-+		_rtw_memset(extra, 0, wrqu->data.length);
-+		pextra += sprintf(pextra, "\n Please input correct format as bleow:\n");
-+		pextra += sprintf(pextra, "\t ch=%d,bw=%d,ant=%d\n", channel, bandwidth, ant);
-+		pextra += sprintf(pextra, "\n [ ch : BGN = <1~14> , A or AC = <36~165> ]");
-+		pextra += sprintf(pextra, "\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]");
-+		pextra += sprintf(pextra, "\n [ ant : <A = 1, B = 2, C = 4, D = 8> ,2T ex: AB=3 BC=6 CD=12");
-+		wrqu->data.length = strlen(extra);
-+		return 0;
-+
-+	} else {
-+		char *pextra = extra;
-+		bStartRx = 1;
-+		RTW_INFO("Got format [ch=%d,bw=%d,ant=%d]\n", channel, bandwidth, ant);
-+		_rtw_memset(extra, 0, wrqu->data.length);
-+		sprintf(extra, "Change Current channel %d to channel %d", padapter->mppriv.channel , channel);
-+		padapter->mppriv.channel = channel;
-+		SetChannel(padapter);
-+		pHalData->current_channel = channel;
-+
-+		if (bandwidth == 1)
-+			bandwidth = CHANNEL_WIDTH_40;
-+		else if (bandwidth == 2)
-+			bandwidth = CHANNEL_WIDTH_80;
-+		pextra = extra + strlen(extra);
-+		pextra += sprintf(pextra, "\nChange Current Bandwidth %d to Bandwidth %d", padapter->mppriv.bandwidth, bandwidth);
-+		padapter->mppriv.bandwidth = (u8)bandwidth;
-+		padapter->mppriv.preamble = sg;
-+		SetBandwidth(padapter);
-+		pHalData->current_channel_bw = bandwidth;
-+
-+		pextra += sprintf(pextra, "\nSet Antenna Path :%d", ant);
-+		switch (ant) {
-+		case 1:
-+			antenna = ANTENNA_A;
-+			break;
-+		case 2:
-+			antenna = ANTENNA_B;
-+			break;
-+		case 4:
-+			antenna = ANTENNA_C;
-+			break;
-+		case 8:
-+			antenna = ANTENNA_D;
-+			break;
-+		case 3:
-+			antenna = ANTENNA_AB;
-+			break;
-+		case 5:
-+			antenna = ANTENNA_AC;
-+			break;
-+		case 9:
-+			antenna = ANTENNA_AD;
-+			break;
-+		case 6:
-+			antenna = ANTENNA_BC;
-+			break;
-+		case 10:
-+			antenna = ANTENNA_BD;
-+			break;
-+		case 12:
-+			antenna = ANTENNA_CD;
-+			break;
-+		case 7:
-+			antenna = ANTENNA_ABC;
-+			break;
-+		case 14:
-+			antenna = ANTENNA_BCD;
-+			break;
-+		case 11:
-+			antenna = ANTENNA_ABD;
-+			break;
-+		case 15:
-+			antenna = ANTENNA_ABCD;
-+			break;
-+		}
-+		RTW_INFO("%s: antenna=0x%x\n", __func__, antenna);
-+		padapter->mppriv.antenna_tx = antenna;
-+		padapter->mppriv.antenna_rx = antenna;
-+		pHalData->antenna_tx_path = antenna;
-+		SetAntenna(padapter);
-+
-+		strcat(extra, "\nstart Rx");
-+		SetPacketRx(padapter, bStartRx, _FALSE);
-+	}
-+	wrqu->data.length = strlen(extra);
-+	return 0;
-+}
-+
-+
-+int rtw_mp_hwtx(struct net_device *dev,
-+		struct iw_request_info *info,
-+		union iwreq_data *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+	PMPT_CONTEXT		pMptCtx = &(padapter->mppriv.mpt_ctx);
-+	char *pch;
-+
-+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) \
-+	|| defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8723F)
-+/* todo: 8723F */
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+	*(extra + wrqu->data.length) = '\0';
-+
-+	_rtw_memset(&pMptCtx->PMacTxInfo, 0, sizeof(RT_PMAC_TX_INFO));
-+	_rtw_memcpy((void *)&pMptCtx->PMacTxInfo, (void *)extra, sizeof(RT_PMAC_TX_INFO));
-+	_rtw_memset(extra, 0, wrqu->data.length);
-+	pch = extra;
-+
-+	if (pMptCtx->PMacTxInfo.bEnPMacTx == 1 && pmp_priv->mode != MP_ON) {
-+		pch += sprintf(pch, "MP Tx Running, Please Set PMac Tx Mode Stop\n");
-+		RTW_INFO("Error !!! MP Tx Running, Please Set PMac Tx Mode Stop\n");
-+	} else {
-+		RTW_INFO("To set MAC Tx mode\n");
-+		if (mpt_ProSetPMacTx(padapter))
-+			pch += sprintf(pch, "Set PMac Tx Mode OK\n");
-+		else
-+			pch += sprintf(pch, "Set PMac Tx Mode Error\n");
-+	}
-+	wrqu->data.length = strlen(extra);
-+#endif
-+	return 0;
-+
-+}
-+
-+int rtw_mp_pwrlmt(struct net_device *dev,
-+			struct iw_request_info *info,
-+			union iwreq_data *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	struct registry_priv  *registry_par = &padapter->registrypriv;
-+	char *pch;
-+
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+
-+	*(extra + wrqu->data.length) = '\0';
-+	pch = extra;
-+
-+#if CONFIG_TXPWR_LIMIT
-+	if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) {
-+		padapter->registrypriv.RegEnableTxPowerLimit = 0;
-+		pch += sprintf(pch, "Turn off Power Limit\n");
-+
-+	} else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) {
-+		padapter->registrypriv.RegEnableTxPowerLimit = 1;
-+		pch += sprintf(pch, "Turn on Power Limit\n");
-+
-+	} else
-+#endif
-+		pch += sprintf(pch, "Get Power Limit Status:%s\n", (registry_par->RegEnableTxPowerLimit == 1) ? "ON" : "OFF");
-+
-+
-+	wrqu->data.length = strlen(extra);
-+	return 0;
-+}
-+
-+int rtw_mp_pwrbyrate(struct net_device *dev,
-+			struct iw_request_info *info,
-+			union iwreq_data *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+
-+	*(extra + wrqu->data.length) = '\0';
-+	if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) {
-+		padapter->registrypriv.RegEnableTxPowerByRate = 0;
-+		sprintf(extra, "Turn off Tx Power by Rate\n");
-+
-+	} else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) {
-+		padapter->registrypriv.RegEnableTxPowerByRate = 1;
-+		sprintf(extra, "Turn On Tx Power by Rate\n");
-+
-+	} else {
-+		sprintf(extra, "Get Power by Rate Status:%s\n", (padapter->registrypriv.RegEnableTxPowerByRate == 1) ? "ON" : "OFF");
-+	}
-+
-+	wrqu->data.length = strlen(extra);
-+	return 0;
-+}
-+
-+
-+int rtw_mp_dpk_track(struct net_device *dev,
-+			struct iw_request_info *info,
-+			union iwreq_data *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct dm_struct		*pDM_Odm = &pHalData->odmpriv;
-+	char *pch;
-+
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+
-+	*(extra + wrqu->data.length) = '\0';
-+	pch = extra;
-+
-+	if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) {
-+		halrf_set_dpk_track(pDM_Odm, FALSE);
-+		pch += sprintf(pch, "set dpk track off\n");
-+
-+	} else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) {
-+		halrf_set_dpk_track(pDM_Odm, TRUE);
-+		pch += sprintf(pch, "set dpk track on\n");
-+	}
-+
-+	wrqu->data.length = strlen(extra);
-+	return 0;
-+}
-+
-+
-+int rtw_bt_efuse_mask_file(struct net_device *dev,
-+			struct iw_request_info *info,
-+			union iwreq_data *wrqu, char *extra)
-+{
-+	char *rtw_efuse_mask_file_path;
-+	u8	*pch;
-+	char	*ptmp, tmp;
-+	u8 Status;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+
-+	_rtw_memset(btmaskfileBuffer, 0x00, sizeof(btmaskfileBuffer));
-+
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+
-+	*(extra + wrqu->data.length) = '\0';
-+	ptmp = extra;
-+
-+	if (strncmp(extra, "data,", 5) == 0) {
-+		u8	count = 0;
-+		u8	i = 0;
-+
-+		pch = strsep(&ptmp, ",");
-+
-+		if ((pch == NULL) || (strlen(pch) == 0)) {
-+			RTW_INFO("%s: parameter error(no cmd)!\n", __func__);
-+			return -EFAULT;
-+		}
-+
-+		do {
-+			pch = strsep(&ptmp, ":");
-+			if ((pch == NULL) || (strlen(pch) == 0))
-+				break;
-+			if (strlen(pch) != 2
-+				|| IsHexDigit(*pch) == _FALSE
-+				|| IsHexDigit(*(pch + 1)) == _FALSE
-+				|| sscanf(pch, "%hhx", &tmp) != 1
-+			) {
-+				RTW_INFO("%s: invalid 8-bit hex! input format: data,01:23:45:67:89:ab:cd:ef...\n", __func__);
-+				return -EFAULT;
-+			}
-+			btmaskfileBuffer[count++] = tmp;
-+
-+		 } while (count < 64);
-+
-+		_rtw_memset(extra, '\0' , strlen(extra));
-+
-+		for (i = 0; i < count; i++)
-+			ptmp += sprintf(ptmp, "%02x:", btmaskfileBuffer[i]);
-+
-+		padapter->registrypriv.bBTFileMaskEfuse = _TRUE;
-+
-+		ptmp += sprintf(ptmp, "\nLoad BT Efuse Mask data %d hex ok\n", count);
-+		wrqu->data.length = strlen(extra);
-+		return 0;
-+	}
-+	rtw_efuse_mask_file_path = extra;
-+
-+	if (rtw_is_file_readable(rtw_efuse_mask_file_path) == _TRUE) {
-+		RTW_INFO("%s do rtw_is_file_readable = %s! ,sizeof BT maskfileBuffer %zu\n", __func__, rtw_efuse_mask_file_path, sizeof(btmaskfileBuffer));
-+		Status = rtw_efuse_file_read(padapter, rtw_efuse_mask_file_path, btmaskfileBuffer, sizeof(btmaskfileBuffer));
-+		_rtw_memset(extra, '\0' , strlen(extra));
-+		if (Status == _TRUE) {
-+			padapter->registrypriv.bBTFileMaskEfuse = _TRUE;
-+			ptmp += sprintf(ptmp, "BT efuse mask file read OK\n");
-+		} else {
-+			padapter->registrypriv.bBTFileMaskEfuse = _FALSE;
-+			ptmp += sprintf(ptmp, "read BT efuse mask file FAIL\n");
-+			RTW_INFO("%s rtw_efuse_file_read BT mask fail!\n", __func__);
-+		}
-+	} else {
-+		padapter->registrypriv.bBTFileMaskEfuse = _FALSE;
-+		ptmp += sprintf(ptmp, "BT efuse mask file readable FAIL\n");
-+		RTW_INFO("%s rtw_is_file_readable BT Mask file fail!\n", __func__);
-+	}
-+	wrqu->data.length = strlen(extra);
-+	return 0;
-+}
-+
-+
-+int rtw_efuse_mask_file(struct net_device *dev,
-+			struct iw_request_info *info,
-+			union iwreq_data *wrqu, char *extra)
-+{
-+	char *rtw_efuse_mask_file_path;
-+	u8 Status;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+
-+	_rtw_memset(maskfileBuffer, 0x00, sizeof(maskfileBuffer));
-+
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+
-+	*(extra + wrqu->data.length) = '\0';
-+	if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) {
-+		padapter->registrypriv.boffefusemask = 1;
-+		sprintf(extra, "Turn off Efuse Mask\n");
-+		wrqu->data.length = strlen(extra);
-+		return 0;
-+	}
-+	if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) {
-+		padapter->registrypriv.boffefusemask = 0;
-+		sprintf(extra, "Turn on Efuse Mask\n");
-+		wrqu->data.length = strlen(extra);
-+		return 0;
-+	}
-+	if (strncmp(extra, "data,", 5) == 0) {
-+		u8	*pch;
-+		char	*ptmp, tmp;
-+		u8	count = 0;
-+		u8	i = 0;
-+
-+		ptmp = extra;
-+		pch = strsep(&ptmp, ",");
-+
-+		if ((pch == NULL) || (strlen(pch) == 0)) {
-+			RTW_INFO("%s: parameter error(no cmd)!\n", __func__);
-+			return -EFAULT;
-+		}
-+
-+		do {
-+			pch = strsep(&ptmp, ":");
-+			if ((pch == NULL) || (strlen(pch) == 0))
-+				break;
-+			if (strlen(pch) != 2
-+				|| IsHexDigit(*pch) == _FALSE
-+				|| IsHexDigit(*(pch + 1)) == _FALSE
-+				|| sscanf(pch, "%hhx", &tmp) != 1
-+			) {
-+				RTW_INFO("%s: invalid 8-bit hex! input format: data,01:23:45:67:89:ab:cd:ef...\n", __func__);
-+				return -EFAULT;
-+			}
-+			maskfileBuffer[count++] = tmp;
-+
-+		} while (count < 64);
-+
-+		_rtw_memset(extra, '\0' , strlen(extra));
-+
-+		for (i = 0; i < count; i++)
-+			ptmp += sprintf(ptmp, "%02x:", maskfileBuffer[i]);
-+
-+		padapter->registrypriv.bFileMaskEfuse = _TRUE;
-+
-+		sprintf(ptmp, "\nLoad Efuse Mask data %d hex ok\n", count);
-+		wrqu->data.length = strlen(extra);
-+		return 0;
-+	}
-+	rtw_efuse_mask_file_path = extra;
-+
-+	if (rtw_is_file_readable(rtw_efuse_mask_file_path) == _TRUE) {
-+		RTW_INFO("%s do rtw_efuse_mask_file_read = %s! ,sizeof maskfileBuffer %zu\n", __func__, rtw_efuse_mask_file_path, sizeof(maskfileBuffer));
-+		Status = rtw_efuse_file_read(padapter, rtw_efuse_mask_file_path, maskfileBuffer, sizeof(maskfileBuffer));
-+		if (Status == _TRUE) {
-+			padapter->registrypriv.bFileMaskEfuse = _TRUE;
-+			sprintf(extra, "efuse mask file read OK\n");
-+		} else {
-+			padapter->registrypriv.bFileMaskEfuse = _FALSE;
-+			sprintf(extra, "read efuse mask file FAIL\n");
-+			RTW_INFO("%s rtw_efuse_file_read mask fail!\n", __func__);
-+		}
-+	} else {
-+		padapter->registrypriv.bFileMaskEfuse = _FALSE;
-+		sprintf(extra, "efuse mask file readable FAIL\n");
-+		RTW_INFO("%s rtw_is_file_readable fail!\n", __func__);
-+	}
-+	wrqu->data.length = strlen(extra);
-+	return 0;
-+}
-+
-+
-+int rtw_efuse_file_map(struct net_device *dev,
-+		       struct iw_request_info *info,
-+		       union iwreq_data *wrqu, char *extra)
-+{
-+	char *rtw_efuse_file_map_path;
-+	u8 Status;
-+	PEFUSE_HAL pEfuseHal;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+
-+	pEfuseHal = &pHalData->EfuseHal;
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+
-+	rtw_efuse_file_map_path = extra;
-+
-+	_rtw_memset(pEfuseHal->fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
-+
-+	if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) {
-+		RTW_INFO("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path);
-+		Status = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeEfuseModifiedMap, sizeof(pEfuseHal->fakeEfuseModifiedMap));
-+		if (Status == _TRUE) {
-+			pmp_priv->bloadefusemap = _TRUE;
-+			sprintf(extra, "efuse file file_read OK\n");
-+		} else {
-+			pmp_priv->bloadefusemap = _FALSE;
-+			sprintf(extra, "efuse file file_read FAIL\n");
-+		}
-+	} else {
-+		sprintf(extra, "efuse file readable FAIL\n");
-+		RTW_INFO("%s rtw_is_file_readable fail!\n", __func__);
-+	}
-+	wrqu->data.length = strlen(extra);
-+	return 0;
-+}
-+
-+
-+int rtw_efuse_file_map_store(struct net_device *dev,
-+				struct iw_request_info *info,
-+				union iwreq_data *wrqu, char *extra)
-+{
-+	char *rtw_efuse_file_map_path;
-+	u8 Status;
-+	u16 mapLen;
-+	PEFUSE_HAL pEfuseHal;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+
-+	pEfuseHal = &pHalData->EfuseHal;
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+
-+	rtw_efuse_file_map_path = extra;
-+	RTW_INFO("%s rtw_is_file_readable! %s\n", __func__, rtw_efuse_file_map_path);
-+
-+	EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE);
-+
-+	if (mapLen != 0) {
-+		RTW_INFO("%s, efuse store path = %s! mapLen = %d\n", __func__, rtw_efuse_file_map_path, mapLen);
-+		Status = rtw_efuse_file_store(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeEfuseModifiedMap, mapLen);
-+		if (Status) {
-+			sprintf(extra, "efuse file restore OK\n");
-+		} else {
-+			sprintf(extra, "efuse file restore FAIL\n");
-+		}
-+	} else {
-+		sprintf(extra, "efuse file readable FAIL\n");
-+		RTW_INFO("%s rtw_is_file_readable fail! map Len %d\n", __func__, mapLen);
-+	}
-+
-+	wrqu->data.length = strlen(extra);
-+	return 0;
-+}
-+
-+int rtw_bt_efuse_file_map(struct net_device *dev,
-+				struct iw_request_info *info,
-+				union iwreq_data *wrqu, char *extra)
-+{
-+	char *rtw_efuse_file_map_path;
-+	u8 Status;
-+	PEFUSE_HAL pEfuseHal;
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+	struct mp_priv *pmp_priv = &padapter->mppriv;
-+
-+	pEfuseHal = &pHalData->EfuseHal;
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+
-+	rtw_efuse_file_map_path = extra;
-+
-+	_rtw_memset(pEfuseHal->fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
-+
-+	if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) {
-+		RTW_INFO("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path);
-+		Status = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeBTEfuseModifiedMap, sizeof(pEfuseHal->fakeBTEfuseModifiedMap));
-+		if (Status == _TRUE) {
-+			pmp_priv->bloadBTefusemap = _TRUE;
-+			sprintf(extra, "BT efuse file file_read OK\n");
-+		} else {
-+			pmp_priv->bloadBTefusemap = _FALSE;
-+			sprintf(extra, "BT efuse file file_read FAIL\n");
-+		}
-+	} else {
-+		sprintf(extra, "BT efuse file readable FAIL\n");
-+		RTW_INFO("%s rtw_is_file_readable fail!\n", __func__);
-+	}
-+	wrqu->data.length = strlen(extra);
-+	return 0;
-+}
-+
-+
-+static inline void dump_buf(u8 *buf, u32 len)
-+{
-+	u32 i;
-+
-+	RTW_INFO("-----------------Len %d----------------\n", len);
-+	for (i = 0; i < len; i++)
-+		RTW_INFO("%2.2x-", *(buf + i));
-+	RTW_INFO("\n");
-+}
-+
-+int rtw_mp_link(struct net_device *dev,
-+			struct iw_request_info *info,
-+			struct iw_point *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	struct mp_priv *pmp_priv;
-+	char input[RTW_IWD_MAX_LEN];
-+	int		bgetrxdata = 0, btxdata = 0, bsetbt = 0;
-+	u8 err = 0;
-+	u32 i = 0, datalen = 0,jj, kk, waittime = 0;
-+	u16 val = 0x00, ret = 0;
-+	char *pextra = NULL;
-+	u8 *setdata = NULL;
-+	char *pch, *ptmp, *token, *tmp[4] = {0x00, 0x00, 0x00};
-+
-+	pmp_priv = &padapter->mppriv;
-+
-+	if (rtw_do_mp_iwdata_len_chk(__func__, wrqu->length))
-+		return -EFAULT;
-+
-+	if (copy_from_user(input, wrqu->pointer, wrqu->length))
-+		return -EFAULT;
-+
-+	_rtw_memset(extra, 0, wrqu->length);
-+
-+	RTW_INFO("%s: in=%s\n", __func__, input);
-+
-+	bgetrxdata =  (strncmp(input, "rxdata", 6) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
-+	btxdata =  (strncmp(input, "txdata", 6) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
-+	bsetbt =  (strncmp(input, "setbt", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/
-+
-+	if (bgetrxdata) {
-+		RTW_INFO("%s: in= 1 \n", __func__);
-+		if (pmp_priv->mplink_brx == _TRUE) {
-+			pch = extra;
-+				while (waittime < 100 && pmp_priv->mplink_brx == _FALSE) {
-+						if (pmp_priv->mplink_brx == _FALSE)
-+							rtw_msleep_os(10);
-+						else
-+							break;
-+						waittime++;
-+				}
-+				if (pmp_priv->mplink_brx == _TRUE) {
-+					pch += sprintf(pch, "\n");
-+
-+					for (i = 0; i < pmp_priv->mplink_rx_len; i ++) {
-+						pch += sprintf(pch, "%02x:", pmp_priv->mplink_buf[i]);
-+					}
-+					_rtw_memset(pmp_priv->mplink_buf, '\0' , sizeof(pmp_priv->mplink_buf));
-+					pmp_priv->mplink_brx = _FALSE;
-+				}
-+		}
-+	} else if (btxdata) {
-+		struct pkt_attrib *pattrib;
-+
-+		pch = input;
-+		setdata = rtw_zmalloc(1024);
-+		if (setdata == NULL) {
-+			err = -ENOMEM;
-+			goto exit;
-+		}
-+
-+		i = 0;
-+		while ((token = strsep(&pch, ",")) != NULL) {
-+			if (i > 2)
-+				break;
-+			tmp[i] = token;
-+			i++;
-+		}
-+
-+		/* tmp[0],[1],[2] */
-+		/* txdata,00e04c871200........... */
-+		if (strcmp(tmp[0], "txdata") == 0) {
-+			if (tmp[1] == NULL) {
-+				err = -EINVAL;
-+				goto exit;
-+			}
-+		}
-+
-+		datalen = strlen(tmp[1]);
-+		if (datalen % 2) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+		datalen /= 2;
-+		if (datalen == 0) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		RTW_INFO("%s: data len=%d\n", __FUNCTION__, datalen);
-+		RTW_INFO("%s: tx data=%s\n", __FUNCTION__, tmp[1]);
-+
-+		for (jj = 0, kk = 0; jj < datalen; jj++, kk += 2)
-+			setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
-+
-+		dump_buf(setdata, datalen);
-+		_rtw_memset(pmp_priv->mplink_buf, '\0' , sizeof(pmp_priv->mplink_buf));
-+		_rtw_memcpy(pmp_priv->mplink_buf, setdata, datalen);
-+
-+		pattrib = &pmp_priv->tx.attrib;
-+		pattrib->pktlen = datalen;
-+		pmp_priv->tx.count = 1;
-+		pmp_priv->tx.stop = 0;
-+		pmp_priv->mplink_btx = _TRUE;
-+		SetPacketTx(padapter);
-+		pmp_priv->mode = MP_PACKET_TX;
-+
-+	} else if (bsetbt) {
-+
-+#ifdef CONFIG_BT_COEXIST
-+		pch = input;
-+		i = 0;
-+
-+		while ((token = strsep(&pch, ",")) != NULL) {
-+			if (i > 3)
-+				break;
-+			tmp[i] = token;
-+			i++;
-+		}
-+
-+		if (tmp[1] == NULL) {
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+
-+		if (strcmp(tmp[1], "scbd") == 0) {
-+			u16 org_val = 0x8002, pre_val, read_score_board_val;
-+			u8 state;
-+
-+			pre_val = (rtw_read16(padapter,(0xaa))) & 0x7fff;
-+
-+			if (tmp[2] != NULL) {
-+				state = simple_strtoul(tmp[2], &ptmp, 10);
-+
-+				if (state)
-+						org_val = org_val | BIT6;
-+				else
-+						org_val = org_val & (~BIT6);
-+
-+				if (org_val != pre_val) {
-+					pre_val = org_val;
-+					rtw_write16(padapter, 0xaa, org_val);
-+					RTW_INFO("%s,setbt scbd write org_val = 0x%x , pre_val = 0x%x\n", __func__, org_val, pre_val);
-+				} else {
-+					RTW_INFO("%s,setbt scbd org_val = 0x%x ,pre_val = 0x%x\n", __func__, org_val, pre_val);
-+				}
-+			} else {
-+					read_score_board_val = (rtw_read16(padapter,(0xaa))) & 0x7fff;
-+					RTW_INFO("%s,read_score_board_val = 0x%x\n", __func__, read_score_board_val);
-+			}
-+			goto exit;
-+
-+		} else if (strcmp(tmp[1], "testmode") == 0) {
-+
-+			if (tmp[2] == NULL) {
-+				err = -EINVAL;
-+				goto exit;
-+			}
-+
-+			val = simple_strtoul(tmp[2], &ptmp, 16);
-+			RTW_INFO("get tmp, type  %s, val =0x%x!\n", tmp[1], val);
-+
-+			if (tmp[2] != NULL) {
-+				_rtw_memset(extra, 0, wrqu->length);
-+				pch = extra;
-+				ret = rtw_btcoex_btset_testmode(padapter, val);
-+				if (!CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS)) {
-+					RTW_INFO("%s: BT_OP fail = 0x%x!\n", __FUNCTION__, val);
-+					pch += sprintf(pch, "BT_OP fail  0x%x!\n", val);
-+				} else
-+					pch += sprintf(pch, "Set BT_OP 0x%x done!\n", val);
-+			}
-+
-+		}
-+#endif /* CONFIG_BT_COEXIST */
-+	}
-+
-+exit:
-+	if (setdata)
-+		rtw_mfree(setdata, 1024);
-+
-+	wrqu->length = strlen(extra);
-+	return err;
-+
-+}
-+
-+#if defined(CONFIG_RTL8723B)
-+int rtw_mp_SetBT(struct net_device *dev,
-+		 struct iw_request_info *info,
-+		 union iwreq_data *wrqu, char *extra)
-+{
-+	PADAPTER padapter = rtw_netdev_priv(dev);
-+	struct hal_ops *pHalFunc = &padapter->hal_func;
-+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
-+
-+	BT_REQ_CMD	BtReq;
-+	PMPT_CONTEXT	pMptCtx = &(padapter->mppriv.mpt_ctx);
-+	PBT_RSP_CMD	pBtRsp = (PBT_RSP_CMD)&pMptCtx->mptOutBuf[0];
-+	char	input[128];
-+	char *pch, *ptmp, *token, *tmp[2] = {0x00, 0x00};
-+	u8 setdata[100];
-+	u8 resetbt = 0x00;
-+	u8 tempval, BTStatus;
-+	u8 H2cSetbtmac[6];
-+	u8 u1H2CBtMpOperParm[4] = {0x01};
-+	int testmode = 1, ready = 1, trxparam = 1, setgen = 1, getgen = 1, testctrl = 1, testbt = 1, readtherm = 1, setbtmac = 1;
-+	u32 i = 0, ii = 0, jj = 0, kk = 0, cnts = 0, status = 0;
-+	PRT_MP_FIRMWARE pBTFirmware = NULL;
-+
-+	if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length))
-+		return -EFAULT;
-+
-+	*(extra + wrqu->data.length) = '\0';
-+	pch = extra;
-+
-+	if (strlen(extra) < 1)
-+		return -EFAULT;
-+
-+	RTW_INFO("%s:iwpriv in=%s\n", __func__, extra);
-+	ready = strncmp(extra, "ready", 5);
-+	testmode = strncmp(extra, "testmode", 8); /* strncmp TRUE is 0*/
-+	trxparam = strncmp(extra, "trxparam", 8);
-+	setgen = strncmp(extra, "setgen", 6);
-+	getgen = strncmp(extra, "getgen", 6);
-+	testctrl = strncmp(extra, "testctrl", 8);
-+	testbt = strncmp(extra, "testbt", 6);
-+	readtherm = strncmp(extra, "readtherm", 9);
-+	setbtmac = strncmp(extra, "setbtmac", 8);
-+
-+	if (strncmp(extra, "dlbt", 4) == 0) {
-+		pHalData->LastHMEBoxNum = 0;
-+		pHalData->bBTFWReady = _FALSE;
-+		rtw_write8(padapter, 0xa3, 0x05);
-+		BTStatus = rtw_read8(padapter, 0xa0);
-+		RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __func__, BTStatus);
-+		if (BTStatus != 0x04) {
-+			pch += sprintf(pch, "BT Status not Active DLFW FAIL\n");
-+			goto exit;
-+		}
-+
-+		tempval = rtw_read8(padapter, 0x6B);
-+		tempval |= BIT7;
-+		rtw_write8(padapter, 0x6B, tempval);
-+
-+		/* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay*/
-+		/* So don't write 0x6A[14]=1 and 0x6A[15]=0 together!*/
-+		rtw_usleep_os(100);
-+		/* disable BT power cut*/
-+		/* 0x6A[14] = 0*/
-+		tempval = rtw_read8(padapter, 0x6B);
-+		tempval &= ~BIT6;
-+		rtw_write8(padapter, 0x6B, tempval);
-+		rtw_usleep_os(100);
-+		MPT_PwrCtlDM(padapter, 0);
-+		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004));
-+		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF));
-+		rtw_msleep_os(600);
-+		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010));
-+		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB));
-+		rtw_msleep_os(1200);
-+		pBTFirmware = (PRT_MP_FIRMWARE)rtw_zmalloc(sizeof(RT_MP_FIRMWARE));
-+		if (pBTFirmware == NULL)
-+			goto exit;
-+		pHalData->bBTFWReady = _FALSE;
-+		FirmwareDownloadBT(padapter, pBTFirmware);
-+		if (pBTFirmware)
-+			rtw_mfree((u8 *)pBTFirmware, sizeof(RT_MP_FIRMWARE));
-+
-+		RTW_INFO("Wait for FirmwareDownloadBT fw boot!\n");
-+		rtw_msleep_os(2000);
-+		_rtw_memset(extra, '\0', wrqu->data.length);
-+		BtReq.opCodeVer = 1;
-+		BtReq.OpCode = 0;
-+		BtReq.paraLength = 0;
-+		mptbt_BtControlProcess(padapter, &BtReq);
-+		rtw_msleep_os(100);
-+
-+		RTW_INFO("FirmwareDownloadBT ready = 0x%x 0x%x", pMptCtx->mptOutBuf[4], pMptCtx->mptOutBuf[5]);
-+		if ((pMptCtx->mptOutBuf[4] == 0x00) && (pMptCtx->mptOutBuf[5] == 0x00)) {
-+
-+			if (padapter->mppriv.bTxBufCkFail == _TRUE)
-+				pch += sprintf(pch, "check TxBuf Fail.\n");
-+			else
-+				pch += sprintf(pch, "download FW Fail.\n");
-+		} else {
-+			pch += sprintf(pch, "download FW OK.\n");
-+			goto exit;
-+		}
-+		goto exit;
-+	}
-+	if (strncmp(extra, "dlfw", 4) == 0) {
-+		pHalData->LastHMEBoxNum = 0;
-+		pHalData->bBTFWReady = _FALSE;
-+		rtw_write8(padapter, 0xa3, 0x05);
-+		BTStatus = rtw_read8(padapter, 0xa0);
-+		RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __func__, BTStatus);
-+		if (BTStatus != 0x04) {
-+			pch += sprintf(pch, "BT Status not Active DLFW FAIL\n");
-+			goto exit;
-+		}
-+
-+		tempval = rtw_read8(padapter, 0x6B);
-+		tempval |= BIT7;
-+		rtw_write8(padapter, 0x6B, tempval);
-+
-+		/* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay*/
-+		/* So don't write 0x6A[14]=1 and 0x6A[15]=0 together!*/
-+		rtw_usleep_os(100);
-+		/* disable BT power cut*/
-+		/* 0x6A[14] = 0*/
-+		tempval = rtw_read8(padapter, 0x6B);
-+		tempval &= ~BIT6;
-+		rtw_write8(padapter, 0x6B, tempval);
-+		rtw_usleep_os(100);
-+
-+		MPT_PwrCtlDM(padapter, 0);
-+		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004));
-+		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF));
-+		rtw_msleep_os(600);
-+		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010));
-+		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB));
-+		rtw_msleep_os(1200);
-+
-+#if defined(CONFIG_PLATFORM_SPRD) && (MP_DRIVER == 1)
-+		/* Pull up BT reset pin.*/
-+		RTW_INFO("%s: pull up BT reset pin when bt start mp test\n", __func__);
-+		rtw_wifi_gpio_wlan_ctrl(WLAN_BT_PWDN_ON);
-+#endif
-+		RTW_INFO(" FirmwareDownload!\n");
-+
-+#if defined(CONFIG_RTL8723B)
-+		status = rtl8723b_FirmwareDownload(padapter, _FALSE);
-+#endif
-+		RTW_INFO("Wait for FirmwareDownloadBT fw boot!\n");
-+		rtw_msleep_os(1000);
-+#ifdef CONFIG_BT_COEXIST
-+		rtw_btcoex_HaltNotify(padapter);
-+		RTW_INFO("SetBT btcoex HaltNotify !\n");
-+		/*hal_btcoex1ant_SetAntPath(padapter);*/
-+		rtw_btcoex_SetManualControl(padapter, _TRUE);
-+#endif
-+		_rtw_memset(extra, '\0', wrqu->data.length);
-+		BtReq.opCodeVer = 1;
-+		BtReq.OpCode = 0;
-+		BtReq.paraLength = 0;
-+		mptbt_BtControlProcess(padapter, &BtReq);
-+		rtw_msleep_os(200);
-+
-+		RTW_INFO("FirmwareDownloadBT ready = 0x%x 0x%x", pMptCtx->mptOutBuf[4], pMptCtx->mptOutBuf[5]);
-+		if ((pMptCtx->mptOutBuf[4] == 0x00) && (pMptCtx->mptOutBuf[5] == 0x00)) {
-+			if (padapter->mppriv.bTxBufCkFail == _TRUE)
-+				pch += sprintf(pch, "check TxBuf Fail.\n");
-+			else
-+				pch += sprintf(pch, "download FW Fail.\n");
-+		} else {
-+#ifdef CONFIG_BT_COEXIST
-+			rtw_btcoex_SwitchBtTRxMask(padapter);
-+#endif
-+			rtw_msleep_os(200);
-+			pch += sprintf(pch, "download FW OK.\n");
-+			goto exit;
-+		}
-+		goto exit;
-+	}
-+
-+	if (strncmp(extra, "down", 4) == 0) {
-+		RTW_INFO("SetBT down for to hal_init !\n");
-+#ifdef CONFIG_BT_COEXIST
-+		rtw_btcoex_SetManualControl(padapter, _FALSE);
-+		rtw_btcoex_Initialize(padapter);
-+#endif
-+		pHalFunc->read_adapter_info(padapter);
-+		pHalFunc->hal_deinit(padapter);
-+		pHalFunc->hal_init(padapter);
-+		rtw_pm_set_ips(padapter, IPS_NONE);
-+		LeaveAllPowerSaveMode(padapter);
-+		MPT_PwrCtlDM(padapter, 0);
-+		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004));
-+		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF));
-+		rtw_msleep_os(600);
-+		/*rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a)& 0xFFFFFFFE));*/
-+		rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010));
-+		rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB));
-+		rtw_msleep_os(1200);
-+		goto exit;
-+	}
-+	if (strncmp(extra, "disable", 7) == 0) {
-+		RTW_INFO("SetBT disable !\n");
-+		rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a) & 0xFFFFFFFB));
-+		rtw_msleep_os(500);
-+		goto exit;
-+	}
-+	if (strncmp(extra, "enable", 6) == 0) {
-+		RTW_INFO("SetBT enable !\n");
-+		rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a) | 0x00000004));
-+		rtw_msleep_os(500);
-+		goto exit;
-+	}
-+	if (strncmp(extra, "h2c", 3) == 0) {
-+		RTW_INFO("SetBT h2c !\n");
-+		pHalData->bBTFWReady = _TRUE;
-+		rtw_hal_fill_h2c_cmd(padapter, 0x63, 1, u1H2CBtMpOperParm);
-+		goto exit;
-+	}
-+	if (strncmp(extra, "2ant", 4) == 0) {
-+		RTW_INFO("Set BT 2ant use!\n");
-+		phy_set_mac_reg(padapter, 0x67, BIT5, 0x1);
-+		rtw_write32(padapter, 0x948, 0000);
-+
-+		goto exit;
-+	}
-+
-+	if (ready != 0 && testmode != 0 && trxparam != 0 && setgen != 0 && getgen != 0 && testctrl != 0 && testbt != 0 && readtherm != 0 && setbtmac != 0)
-+		return -EFAULT;
-+
-+	if (testbt == 0) {
-+		BtReq.opCodeVer = 1;
-+		BtReq.OpCode = 6;
-+		BtReq.paraLength = cnts / 2;
-+		goto todo;
-+	}
-+	if (ready == 0) {
-+		BtReq.opCodeVer = 1;
-+		BtReq.OpCode = 0;
-+		BtReq.paraLength = 0;
-+		goto todo;
-+	}
-+
-+	i = 0;
-+	while ((token = strsep(&pch, ",")) != NULL) {
-+		if (i > 1)
-+			break;
-+		tmp[i] = token;
-+		i++;
-+	}
-+
-+	if ((tmp[0] != NULL) && (tmp[1] != NULL)) {
-+		cnts = strlen(tmp[1]);
-+		if (cnts < 1)
-+			return -EFAULT;
-+
-+		RTW_INFO("%s: cnts=%d\n", __func__, cnts);
-+		RTW_INFO("%s: data=%s\n", __func__, tmp[1]);
-+
-+		for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) {
-+			BtReq.pParamStart[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]);
-+			/*			RTW_INFO("BtReq.pParamStart[%d]=0x%02x\n", jj, BtReq.pParamStart[jj]);*/
-+		}
-+	} else
-+		return -EFAULT;
-+
-+	if (testmode == 0) {
-+		BtReq.opCodeVer = 1;
-+		BtReq.OpCode = 1;
-+		BtReq.paraLength = 1;
-+	}
-+	if (trxparam == 0) {
-+		BtReq.opCodeVer = 1;
-+		BtReq.OpCode = 2;
-+		BtReq.paraLength = cnts / 2;
-+	}
-+	if (setgen == 0) {
-+		RTW_INFO("%s: BT_SET_GENERAL\n", __func__);
-+		BtReq.opCodeVer = 1;
-+		BtReq.OpCode = 3;/*BT_SET_GENERAL	3*/
-+		BtReq.paraLength = cnts / 2;
-+	}
-+	if (getgen == 0) {
-+		RTW_INFO("%s: BT_GET_GENERAL\n", __func__);
-+		BtReq.opCodeVer = 1;
-+		BtReq.OpCode = 4;/*BT_GET_GENERAL	4*/
-+		BtReq.paraLength = cnts / 2;
-+	}
-+	if (readtherm == 0) {
-+		RTW_INFO("%s: BT_GET_GENERAL\n", __func__);
-+		BtReq.opCodeVer = 1;
-+		BtReq.OpCode = 4;/*BT_GET_GENERAL	4*/
-+		BtReq.paraLength = cnts / 2;
-+	}
-+
-+	if (testctrl == 0) {
-+		RTW_INFO("%s: BT_TEST_CTRL\n", __func__);
-+		BtReq.opCodeVer = 1;
-+		BtReq.OpCode = 5;/*BT_TEST_CTRL	5*/
-+		BtReq.paraLength = cnts / 2;
-+	}
-+
-+	RTW_INFO("%s: Req opCodeVer=%d OpCode=%d paraLength=%d\n",
-+		 __func__, BtReq.opCodeVer, BtReq.OpCode, BtReq.paraLength);
-+
-+	if (BtReq.paraLength < 1)
-+		goto todo;
-+	for (i = 0; i < BtReq.paraLength; i++) {
-+		RTW_INFO("%s: BtReq.pParamStart[%d] = 0x%02x\n",
-+			 __func__, i, BtReq.pParamStart[i]);
-+	}
-+
-+todo:
-+	_rtw_memset(extra, '\0', wrqu->data.length);
-+
-+	if (pHalData->bBTFWReady == _FALSE) {
-+		pch += sprintf(pch, "BTFWReady = FALSE.\n");
-+		goto exit;
-+	}
-+
-+	mptbt_BtControlProcess(padapter, &BtReq);
-+
-+	if (readtherm == 0) {
-+		pch += sprintf(pch, "BT thermal=");
-+		for (i = 4; i < pMptCtx->mptOutLen; i++) {
-+			if ((pMptCtx->mptOutBuf[i] == 0x00) && (pMptCtx->mptOutBuf[i + 1] == 0x00))
-+				goto exit;
-+
-+			pch += sprintf(pch, " %d ", (pMptCtx->mptOutBuf[i] & 0x1f));
-+		}
-+	} else {
-+		for (i = 4; i < pMptCtx->mptOutLen; i++)
-+			pch += sprintf(pch, " 0x%x ", pMptCtx->mptOutBuf[i]);
-+	}
-+
-+exit:
-+	wrqu->data.length = strlen(extra) + 1;
-+	RTW_INFO("-%s: output len=%d data=%s\n", __func__, wrqu->data.length, extra);
-+
-+	return status;
-+}
-+
-+#endif /*#ifdef CONFIG_RTL8723B*/
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/mlme_linux.c b/drivers/staging/rtl8723cs/os_dep/linux/mlme_linux.c
-new file mode 100644
-index 000000000000..6fd24e8e2f3b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/mlme_linux.c
-@@ -0,0 +1,444 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+#define _MLME_OSDEP_C_
-+
-+#include <drv_types.h>
-+
-+
-+#ifdef RTK_DMP_PLATFORM
-+void Linkup_workitem_callback(struct work_struct *work)
-+{
-+	struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkup_workitem);
-+	_adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv);
-+
-+
-+
-+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))
-+	kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKUP);
-+#else
-+	kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKUP);
-+#endif
-+
-+}
-+
-+void Linkdown_workitem_callback(struct work_struct *work)
-+{
-+	struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkdown_workitem);
-+	_adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv);
-+
-+
-+
-+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))
-+	kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKDOWN);
-+#else
-+	kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKDOWN);
-+#endif
-+
-+}
-+#endif
-+
-+extern void rtw_indicate_wx_assoc_event(_adapter *padapter);
-+extern void rtw_indicate_wx_disassoc_event(_adapter *padapter);
-+
-+void rtw_os_indicate_connect(_adapter *adapter)
-+{
-+	struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
-+	    (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
-+		rtw_cfg80211_ibss_indicate_connect(adapter);
-+	else
-+		rtw_cfg80211_indicate_connect(adapter);
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+	rtw_indicate_wx_assoc_event(adapter);
-+
-+#ifdef CONFIG_RTW_MESH
-+#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
-+	if (!rtw_mesh_cto_mgate_required(adapter))
-+#endif
-+#endif
-+		rtw_netif_carrier_on(adapter->pnetdev);
-+
-+	if (adapter->pid[2] != 0)
-+		rtw_signal_process(adapter->pid[2], SIGALRM);
-+
-+#ifdef RTK_DMP_PLATFORM
-+	_set_workitem(&adapter->mlmepriv.Linkup_workitem);
-+#endif
-+
-+
-+}
-+
-+extern void indicate_wx_scan_complete_event(_adapter *padapter);
-+void rtw_os_indicate_scan_done(_adapter *padapter, bool aborted)
-+{
-+#ifdef CONFIG_IOCTL_CFG80211
-+	rtw_cfg80211_indicate_scan_done(padapter, aborted);
-+#endif
-+	indicate_wx_scan_complete_event(padapter);
-+}
-+
-+static RT_PMKID_LIST   backupPMKIDList[NUM_PMKID_CACHE];
-+void rtw_reset_securitypriv(_adapter *adapter)
-+{
-+	u8	backupPMKIDIndex = 0;
-+	u8	backupTKIPCountermeasure = 0x00;
-+	u32	backupTKIPcountermeasure_time = 0;
-+	/* add for CONFIG_IEEE80211W, none 11w also can use */
-+	_irqL irqL;
-+
-+	_enter_critical_bh(&adapter->security_key_mutex, &irqL);
-+
-+	if (adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802.1x */
-+		u8 backup_sw_encrypt, backup_sw_decrypt;
-+
-+		backup_sw_encrypt = adapter->securitypriv.sw_encrypt;
-+		backup_sw_decrypt = adapter->securitypriv.sw_decrypt;
-+
-+		/* Added by Albert 2009/02/18 */
-+		/* We have to backup the PMK information for WiFi PMK Caching test item. */
-+		/*  */
-+		/* Backup the btkip_countermeasure information. */
-+		/* When the countermeasure is trigger, the driver have to disconnect with AP for 60 seconds. */
-+
-+		_rtw_memset(&backupPMKIDList[0], 0x00, sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
-+
-+		_rtw_memcpy(&backupPMKIDList[0], &adapter->securitypriv.PMKIDList[0], sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
-+		backupPMKIDIndex = adapter->securitypriv.PMKIDIndex;
-+		backupTKIPCountermeasure = adapter->securitypriv.btkip_countermeasure;
-+		backupTKIPcountermeasure_time = adapter->securitypriv.btkip_countermeasure_time;
-+		_rtw_memset((unsigned char *)&adapter->securitypriv, 0, sizeof(struct security_priv));
-+
-+		/* Added by Albert 2009/02/18 */
-+		/* Restore the PMK information to securitypriv structure for the following connection. */
-+		_rtw_memcpy(&adapter->securitypriv.PMKIDList[0], &backupPMKIDList[0], sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE);
-+		adapter->securitypriv.PMKIDIndex = backupPMKIDIndex;
-+		adapter->securitypriv.btkip_countermeasure = backupTKIPCountermeasure;
-+		adapter->securitypriv.btkip_countermeasure_time = backupTKIPcountermeasure_time;
-+
-+		adapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen;
-+		adapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled;
-+
-+		adapter->securitypriv.extauth_status = WLAN_STATUS_UNSPECIFIED_FAILURE;
-+
-+		adapter->securitypriv.sw_encrypt = backup_sw_encrypt;
-+		adapter->securitypriv.sw_decrypt = backup_sw_decrypt;
-+
-+	} else { /* reset values in securitypriv */
-+		/* if(adapter->mlmepriv.fw_state & WIFI_STATION_STATE) */
-+		/* { */
-+		struct security_priv *psec_priv = &adapter->securitypriv;
-+
-+		psec_priv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
-+		psec_priv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
-+		psec_priv->dot11PrivacyKeyIndex = 0;
-+
-+		psec_priv->dot118021XGrpPrivacy = _NO_PRIVACY_;
-+		psec_priv->dot118021XGrpKeyid = 1;
-+
-+		psec_priv->ndisauthtype = Ndis802_11AuthModeOpen;
-+		psec_priv->ndisencryptstatus = Ndis802_11WEPDisabled;
-+		/* } */
-+
-+		psec_priv->extauth_status = WLAN_STATUS_UNSPECIFIED_FAILURE;
-+	}
-+	/* add for CONFIG_IEEE80211W, none 11w also can use */
-+	_exit_critical_bh(&adapter->security_key_mutex, &irqL);
-+
-+	RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(adapter));
-+}
-+
-+void rtw_os_indicate_disconnect(_adapter *adapter,  u16 reason, u8 locally_generated)
-+{
-+	/* RT_PMKID_LIST   backupPMKIDList[NUM_PMKID_CACHE]; */
-+
-+
-+	rtw_netif_carrier_off(adapter->pnetdev); /* Do it first for tx broadcast pkt after disconnection issue! */
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	rtw_cfg80211_indicate_disconnect(adapter,  reason, locally_generated);
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+	rtw_indicate_wx_disassoc_event(adapter);
-+
-+#ifdef RTK_DMP_PLATFORM
-+	_set_workitem(&adapter->mlmepriv.Linkdown_workitem);
-+#endif
-+	/* modify for CONFIG_IEEE80211W, none 11w also can use the same command */
-+	rtw_reset_securitypriv_cmd(adapter);
-+
-+
-+}
-+
-+void rtw_report_sec_ie(_adapter *adapter, u8 authmode, u8 *sec_ie)
-+{
-+	uint	len;
-+	u8	*buff, *p, i;
-+	union iwreq_data wrqu;
-+
-+
-+
-+	buff = NULL;
-+	if (authmode == _WPA_IE_ID_) {
-+
-+		buff = rtw_zmalloc(IW_CUSTOM_MAX);
-+		if (NULL == buff) {
-+			RTW_INFO(FUNC_ADPT_FMT ": alloc memory FAIL!!\n",
-+				 FUNC_ADPT_ARG(adapter));
-+			return;
-+		}
-+		p = buff;
-+
-+		p += sprintf(p, "ASSOCINFO(ReqIEs=");
-+
-+		len = sec_ie[1] + 2;
-+		len = (len < IW_CUSTOM_MAX) ? len : IW_CUSTOM_MAX;
-+
-+		for (i = 0; i < len; i++)
-+			p += sprintf(p, "%02x", sec_ie[i]);
-+
-+		p += sprintf(p, ")");
-+
-+		_rtw_memset(&wrqu, 0, sizeof(wrqu));
-+
-+		wrqu.data.length = p - buff;
-+
-+		wrqu.data.length = (wrqu.data.length < IW_CUSTOM_MAX) ? wrqu.data.length : IW_CUSTOM_MAX;
-+
-+#ifndef CONFIG_IOCTL_CFG80211
-+		wireless_send_event(adapter->pnetdev, IWEVCUSTOM, &wrqu, buff);
-+#endif
-+
-+		rtw_mfree(buff, IW_CUSTOM_MAX);
-+	}
-+
-+
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+
-+void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta)
-+{
-+	union iwreq_data wrqu;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+	if (psta == NULL)
-+		return;
-+
-+	if (psta->cmn.aid > pstapriv->max_aid)
-+		return;
-+
-+	if (pstapriv->sta_aid[psta->cmn.aid - 1] != psta)
-+		return;
-+
-+
-+	wrqu.addr.sa_family = ARPHRD_ETHER;
-+
-+	_rtw_memcpy(wrqu.addr.sa_data, psta->cmn.mac_addr, ETH_ALEN);
-+
-+	RTW_INFO("+rtw_indicate_sta_assoc_event\n");
-+
-+#ifndef CONFIG_IOCTL_CFG80211
-+	wireless_send_event(padapter->pnetdev, IWEVREGISTERED, &wrqu, NULL);
-+#endif
-+
-+}
-+
-+void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta)
-+{
-+	union iwreq_data wrqu;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+
-+	if (psta == NULL)
-+		return;
-+
-+	if (psta->cmn.aid > pstapriv->max_aid)
-+		return;
-+
-+	if (pstapriv->sta_aid[psta->cmn.aid - 1] != psta)
-+		return;
-+
-+
-+	wrqu.addr.sa_family = ARPHRD_ETHER;
-+
-+	_rtw_memcpy(wrqu.addr.sa_data, psta->cmn.mac_addr, ETH_ALEN);
-+
-+	RTW_INFO("+rtw_indicate_sta_disassoc_event\n");
-+
-+#ifndef CONFIG_IOCTL_CFG80211
-+	wireless_send_event(padapter->pnetdev, IWEVEXPIRED, &wrqu, NULL);
-+#endif
-+
-+}
-+
-+
-+#ifdef CONFIG_HOSTAPD_MLME
-+
-+static int mgnt_xmit_entry(struct sk_buff *skb, struct net_device *pnetdev)
-+{
-+	struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);
-+	_adapter *padapter = (_adapter *)phostapdpriv->padapter;
-+
-+	/* RTW_INFO("%s\n", __FUNCTION__); */
-+
-+	return rtw_hal_hostap_mgnt_xmit_entry(padapter, skb);
-+}
-+
-+static int mgnt_netdev_open(struct net_device *pnetdev)
-+{
-+	struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);
-+
-+	RTW_INFO("mgnt_netdev_open: MAC Address:" MAC_FMT "\n", MAC_ARG(pnetdev->dev_addr));
-+
-+
-+	init_usb_anchor(&phostapdpriv->anchored);
-+
-+	rtw_netif_wake_queue(pnetdev);
-+
-+	rtw_netif_carrier_on(pnetdev);
-+
-+	/* rtw_write16(phostapdpriv->padapter, 0x0116, 0x0100); */ /* only excluding beacon */
-+
-+	return 0;
-+}
-+static int mgnt_netdev_close(struct net_device *pnetdev)
-+{
-+	struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev);
-+
-+	RTW_INFO("%s\n", __FUNCTION__);
-+
-+	usb_kill_anchored_urbs(&phostapdpriv->anchored);
-+
-+	rtw_netif_carrier_off(pnetdev);
-+
-+	rtw_netif_stop_queue(pnetdev);
-+
-+	/* rtw_write16(phostapdpriv->padapter, 0x0116, 0x3f3f); */
-+
-+	return 0;
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+static const struct net_device_ops rtl871x_mgnt_netdev_ops = {
-+	.ndo_open = mgnt_netdev_open,
-+	.ndo_stop = mgnt_netdev_close,
-+	.ndo_start_xmit = mgnt_xmit_entry,
-+	#if 0
-+	.ndo_set_mac_address = r871x_net_set_mac_address,
-+	.ndo_get_stats = r871x_net_get_stats,
-+	.ndo_do_ioctl = r871x_mp_ioctl,
-+	#endif
-+};
-+#endif
-+
-+int hostapd_mode_init(_adapter *padapter)
-+{
-+	unsigned char mac[ETH_ALEN];
-+	struct hostapd_priv *phostapdpriv;
-+	struct net_device *pnetdev;
-+
-+	pnetdev = rtw_alloc_etherdev(sizeof(struct hostapd_priv));
-+	if (!pnetdev)
-+		return -ENOMEM;
-+
-+	/* SET_MODULE_OWNER(pnetdev); */
-+	ether_setup(pnetdev);
-+
-+	/* pnetdev->type = ARPHRD_IEEE80211; */
-+
-+	phostapdpriv = rtw_netdev_priv(pnetdev);
-+	phostapdpriv->pmgnt_netdev = pnetdev;
-+	phostapdpriv->padapter = padapter;
-+	padapter->phostapdpriv = phostapdpriv;
-+
-+	/* pnetdev->init = NULL; */
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+
-+	RTW_INFO("register rtl871x_mgnt_netdev_ops to netdev_ops\n");
-+
-+	pnetdev->netdev_ops = &rtl871x_mgnt_netdev_ops;
-+
-+#else
-+
-+	pnetdev->open = mgnt_netdev_open;
-+
-+	pnetdev->stop = mgnt_netdev_close;
-+
-+	pnetdev->hard_start_xmit = mgnt_xmit_entry;
-+
-+	/* pnetdev->set_mac_address = r871x_net_set_mac_address; */
-+
-+	/* pnetdev->get_stats = r871x_net_get_stats; */
-+
-+	/* pnetdev->do_ioctl = r871x_mp_ioctl; */
-+
-+#endif
-+
-+	pnetdev->watchdog_timeo = HZ; /* 1 second timeout */
-+
-+	/* pnetdev->wireless_handlers = NULL; */
-+
-+
-+
-+
-+	if (dev_alloc_name(pnetdev, "mgnt.wlan%d") < 0)
-+		RTW_INFO("hostapd_mode_init(): dev_alloc_name, fail!\n");
-+
-+
-+	/* SET_NETDEV_DEV(pnetdev, pintfpriv->udev); */
-+
-+
-+	mac[0] = 0x00;
-+	mac[1] = 0xe0;
-+	mac[2] = 0x4c;
-+	mac[3] = 0x87;
-+	mac[4] = 0x11;
-+	mac[5] = 0x12;
-+
-+	_rtw_memcpy(pnetdev->dev_addr, mac, ETH_ALEN);
-+
-+
-+	rtw_netif_carrier_off(pnetdev);
-+
-+
-+	/* Tell the network stack we exist */
-+	if (register_netdev(pnetdev) != 0) {
-+		RTW_INFO("hostapd_mode_init(): register_netdev fail!\n");
-+
-+		if (pnetdev)
-+			rtw_free_netdev(pnetdev);
-+	}
-+
-+	return 0;
-+
-+}
-+
-+void hostapd_mode_unload(_adapter *padapter)
-+{
-+	struct hostapd_priv *phostapdpriv = padapter->phostapdpriv;
-+	struct net_device *pnetdev = phostapdpriv->pmgnt_netdev;
-+
-+	unregister_netdev(pnetdev);
-+	rtw_free_netdev(pnetdev);
-+
-+}
-+
-+#endif
-+#endif
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/nlrtw.c b/drivers/staging/rtl8723cs/os_dep/linux/nlrtw.c
-new file mode 100644
-index 000000000000..14d164b7ac95
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/nlrtw.c
-@@ -0,0 +1,583 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2020 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RTW_NLRTW_C_
-+
-+#include <drv_types.h>
-+#include "nlrtw.h"
-+
-+#ifdef CONFIG_RTW_NLRTW
-+
-+#include <net/netlink.h>
-+#include <net/genetlink.h>
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
-+#include <uapi/linux/netlink.h>
-+#endif
-+
-+
-+enum nlrtw_cmds {
-+	NLRTW_CMD_UNSPEC,
-+
-+	NLRTW_CMD_CHANNEL_UTILIZATION,
-+	NLRTW_CMD_REG_CHANGE,
-+	NLRTW_CMD_REG_BEACON_HINT,
-+	NLRTW_CMD_RADAR_EVENT,
-+	NLRTW_CMD_RADIO_OPMODE,
-+
-+	__NLRTW_CMD_AFTER_LAST,
-+	NLRTW_CMD_MAX = __NLRTW_CMD_AFTER_LAST - 1
-+};
-+
-+enum nlrtw_attrs {
-+	NLRTW_ATTR_UNSPEC,
-+
-+	NLRTW_ATTR_WIPHY_NAME,
-+	NLRTW_ATTR_CHANNEL_UTILIZATIONS,
-+	NLRTW_ATTR_CHANNEL_UTILIZATION_THRESHOLD,
-+	NLRTW_ATTR_CHANNEL_CENTER,
-+	NLRTW_ATTR_CHANNEL_WIDTH,
-+	NLRTW_ATTR_RADAR_EVENT,
-+	NLRTW_ATTR_OP_CLASS,
-+	NLRTW_ATTR_OP_CHANNEL,
-+	NLRTW_ATTR_OP_TXPWR_MAX,
-+	NLRTW_ATTR_IF_OPMODES,
-+
-+	__NLRTW_ATTR_AFTER_LAST,
-+	NUM_NLRTW_ATTR = __NLRTW_ATTR_AFTER_LAST,
-+	NLRTW_ATTR_MAX = __NLRTW_ATTR_AFTER_LAST - 1
-+};
-+
-+enum nlrtw_ch_util_attrs {
-+	__NLRTW_ATTR_CHANNEL_UTILIZATION_INVALID,
-+
-+	NLRTW_ATTR_CHANNEL_UTILIZATION_VALUE,
-+	NLRTW_ATTR_CHANNEL_UTILIZATION_BSSID,
-+
-+	__NLRTW_ATTR_CHANNEL_UTILIZATION_AFTER_LAST,
-+	NUM_NLRTW_ATTR_CHANNEL_UTILIZATION = __NLRTW_ATTR_CHANNEL_UTILIZATION_AFTER_LAST,
-+	NLRTW_ATTR_CHANNEL_UTILIZATION_MAX = __NLRTW_ATTR_CHANNEL_UTILIZATION_AFTER_LAST - 1
-+};
-+
-+enum nlrtw_radar_event {
-+	NLRTW_RADAR_DETECTED,
-+	NLRTW_RADAR_CAC_FINISHED,
-+	NLRTW_RADAR_CAC_ABORTED,
-+	NLRTW_RADAR_NOP_FINISHED,
-+	NLRTW_RADAR_NOP_STARTED, /* NON_OCP started not by local radar detection */
-+};
-+
-+enum nlrtw_if_opmode_attrs {
-+	NLRTW_IF_OPMODE_UNSPEC,
-+
-+	NLRTW_IF_OPMODE_MACADDR,
-+	NLRTW_IF_OPMODE_OP_CLASS,
-+	NLRTW_IF_OPMODE_OP_CHANNEL,
-+
-+	__NLRTW_IF_OPMODE_ATTR_AFTER_LAST,
-+	NUM_NLRTW_IF_OPMODE_ATTR = __NLRTW_IF_OPMODE_ATTR_AFTER_LAST,
-+	NLRTW_IF_OPMODE_ATTR_MAX = __NLRTW_IF_OPMODE_ATTR_AFTER_LAST - 1
-+};
-+
-+static int nlrtw_ch_util_set(struct sk_buff *skb, struct genl_info *info)
-+{
-+	unsigned int msg;
-+
-+	if (!info->attrs[NLRTW_ATTR_CHANNEL_UTILIZATION_THRESHOLD])
-+		return -EINVAL;
-+	msg = nla_get_u8(info->attrs[NLRTW_ATTR_CHANNEL_UTILIZATION_THRESHOLD]);
-+
-+	return 0;
-+}
-+
-+static struct nla_policy nlrtw_genl_policy[NUM_NLRTW_ATTR] = {
-+	[NLRTW_ATTR_CHANNEL_UTILIZATION_THRESHOLD] = { .type = NLA_U8 },
-+};
-+
-+static struct genl_ops nlrtw_genl_ops[] = {
-+	{
-+		.cmd = NLRTW_CMD_CHANNEL_UTILIZATION,
-+		.flags = 0,
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)
-+		.policy = nlrtw_genl_policy,
-+#endif
-+		.doit = nlrtw_ch_util_set,
-+		.dumpit = NULL,
-+	},
-+};
-+
-+enum nlrtw_multicast_groups {
-+	NLRTW_MCGRP_DEFAULT,
-+};
-+static struct genl_multicast_group nlrtw_genl_mcgrp[] = {
-+	[NLRTW_MCGRP_DEFAULT] = { .name = "nlrtw_default" },
-+};
-+
-+/* family definition */
-+static struct genl_family nlrtw_genl_family = {
-+	.hdrsize = 0,
-+	.name = "nlrtw_"DRV_NAME,
-+	.version = 1,
-+	.maxattr = NLRTW_ATTR_MAX,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0)
-+	.policy = nlrtw_genl_policy,
-+#endif
-+	.netnsok = true,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 12)
-+	.module = THIS_MODULE,
-+#endif
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)
-+	.ops = nlrtw_genl_ops,
-+	.n_ops = ARRAY_SIZE(nlrtw_genl_ops),
-+	.mcgrps = nlrtw_genl_mcgrp,
-+	.n_mcgrps = ARRAY_SIZE(nlrtw_genl_mcgrp),
-+#endif
-+};
-+
-+static inline int nlrtw_multicast(const struct genl_family *family,
-+				  struct sk_buff *skb, u32 portid,
-+				  unsigned int group, gfp_t flags)
-+{
-+	int ret;
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)
-+	ret = genlmsg_multicast(&nlrtw_genl_family, skb, portid, group, flags);
-+#else
-+	ret = genlmsg_multicast(skb, portid, nlrtw_genl_mcgrp[group].id, flags);
-+#endif
-+	return ret;
-+}
-+
-+int rtw_nlrtw_ch_util_rpt(_adapter *adapter, u8 n_rpts, u8 *val, u8 **mac_addr)
-+{
-+	struct sk_buff *skb = NULL;
-+	void *msg_header = NULL;
-+	struct nlattr *nl_ch_util, *nl_ch_utils;
-+	struct wiphy *wiphy;
-+	u8 i;
-+	int ret;
-+
-+	wiphy = adapter_to_wiphy(adapter);
-+	if (!wiphy)
-+		return -EINVAL;
-+
-+	/* allocate memory */
-+	skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
-+	if (!skb) {
-+		nlmsg_free(skb);
-+		return -ENOMEM;
-+	}
-+
-+	/* create the message headers */
-+	msg_header = genlmsg_put(skb, 0, 0, &nlrtw_genl_family, 0,
-+				 NLRTW_CMD_CHANNEL_UTILIZATION);
-+	if (!msg_header) {
-+		ret = -ENOMEM;
-+		goto err_out;
-+	}
-+
-+	/* add attributes */
-+	ret = nla_put_string(skb, NLRTW_ATTR_WIPHY_NAME, wiphy_name(wiphy));
-+
-+	nl_ch_utils = nla_nest_start(skb, NLRTW_ATTR_CHANNEL_UTILIZATIONS);
-+	if (!nl_ch_utils) {
-+		ret = -EMSGSIZE;
-+		goto err_out;
-+	}
-+
-+	for (i = 0; i < n_rpts; i++) {
-+		nl_ch_util = nla_nest_start(skb, i);
-+		if (!nl_ch_util) {
-+			ret = -EMSGSIZE;
-+			goto err_out;
-+		}
-+
-+		ret = nla_put(skb, NLRTW_ATTR_CHANNEL_UTILIZATION_BSSID, ETH_ALEN, *(mac_addr + i));
-+		if (ret != 0)
-+			goto err_out;
-+
-+		ret = nla_put_u8(skb, NLRTW_ATTR_CHANNEL_UTILIZATION_VALUE, *(val + i));
-+		if (ret != 0)
-+			goto err_out;
-+
-+		nla_nest_end(skb, nl_ch_util);
-+	}
-+
-+	nla_nest_end(skb, nl_ch_utils);
-+
-+	/* finalize the message */
-+	genlmsg_end(skb, msg_header);
-+
-+	ret = nlrtw_multicast(&nlrtw_genl_family, skb, 0, NLRTW_MCGRP_DEFAULT, GFP_KERNEL);
-+	if (ret == -ESRCH) {
-+		RTW_INFO("[%s] return ESRCH(No such process)."
-+			 " Maybe no process waits for this msg\n", __func__);
-+		return ret;
-+	} else if (ret != 0) {
-+		RTW_INFO("[%s] ret = %d\n", __func__, ret);
-+		return ret;
-+	}
-+
-+	return 0;
-+err_out:
-+	nlmsg_free(skb);
-+	return ret;
-+}
-+
-+int rtw_nlrtw_reg_change_event(_adapter *adapter)
-+{
-+	struct sk_buff *skb = NULL;
-+	void *msg_header = NULL;
-+	struct wiphy *wiphy;
-+	u8 i;
-+	int ret;
-+
-+	wiphy = adapter_to_wiphy(adapter);
-+	if (!wiphy) {
-+		ret = -EINVAL;
-+		goto err_out;
-+	}
-+
-+	/* allocate memory */
-+	skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
-+	if (!skb) {
-+		ret = -ENOMEM;
-+		goto err_out;
-+	}
-+
-+	/* create the message headers */
-+	msg_header = genlmsg_put(skb, 0, 0, &nlrtw_genl_family, 0, NLRTW_CMD_REG_CHANGE);
-+	if (!msg_header) {
-+		ret = -ENOMEM;
-+		goto err_out;
-+	}
-+
-+	/* add attributes */
-+	ret = nla_put_string(skb, NLRTW_ATTR_WIPHY_NAME, wiphy_name(wiphy));
-+	if (ret)
-+		goto err_out;
-+
-+	/* finalize the message */
-+	genlmsg_end(skb, msg_header);
-+
-+	ret = nlrtw_multicast(&nlrtw_genl_family, skb, 0, NLRTW_MCGRP_DEFAULT, GFP_KERNEL);
-+	if (ret == -ESRCH) {
-+		RTW_DBG(FUNC_WIPHY_FMT" return -ESRCH(No such process)."
-+			 " Maybe no process waits for this msg\n", FUNC_WIPHY_ARG(wiphy));
-+		return ret;
-+	} else if (ret != 0) {
-+		RTW_WARN(FUNC_WIPHY_FMT" return %d\n", FUNC_WIPHY_ARG(wiphy), ret);
-+		return ret;
-+	}
-+
-+	return 0;
-+
-+err_out:
-+	if (skb)
-+		nlmsg_free(skb);
-+	return ret;
-+}
-+
-+int rtw_nlrtw_reg_beacon_hint_event(_adapter *adapter)
-+{
-+	struct sk_buff *skb = NULL;
-+	void *msg_header = NULL;
-+	struct wiphy *wiphy;
-+	u8 i;
-+	int ret;
-+
-+	wiphy = adapter_to_wiphy(adapter);
-+	if (!wiphy) {
-+		ret = -EINVAL;
-+		goto err_out;
-+	}
-+
-+	/* allocate memory */
-+	skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
-+	if (!skb) {
-+		ret = -ENOMEM;
-+		goto err_out;
-+	}
-+
-+	/* create the message headers */
-+	msg_header = genlmsg_put(skb, 0, 0, &nlrtw_genl_family, 0, NLRTW_CMD_REG_BEACON_HINT);
-+	if (!msg_header) {
-+		ret = -ENOMEM;
-+		goto err_out;
-+	}
-+
-+	/* add attributes */
-+	ret = nla_put_string(skb, NLRTW_ATTR_WIPHY_NAME, wiphy_name(wiphy));
-+	if (ret)
-+		goto err_out;
-+
-+	/* finalize the message */
-+	genlmsg_end(skb, msg_header);
-+
-+	ret = nlrtw_multicast(&nlrtw_genl_family, skb, 0, NLRTW_MCGRP_DEFAULT, GFP_KERNEL);
-+	if (ret == -ESRCH) {
-+		RTW_DBG(FUNC_WIPHY_FMT" return -ESRCH(No such process)."
-+			 " Maybe no process waits for this msg\n", FUNC_WIPHY_ARG(wiphy));
-+		return ret;
-+	} else if (ret != 0) {
-+		RTW_WARN(FUNC_WIPHY_FMT" return %d\n", FUNC_WIPHY_ARG(wiphy), ret);
-+		return ret;
-+	}
-+
-+	return 0;
-+
-+err_out:
-+	if (skb)
-+		nlmsg_free(skb);
-+	return ret;
-+}
-+
-+#ifdef CONFIG_DFS_MASTER
-+static int _rtw_nlrtw_radar_event(_adapter *adapter, enum nlrtw_radar_event evt_type, u8 cch, u8 bw)
-+{
-+	struct sk_buff *skb = NULL;
-+	void *msg_header = NULL;
-+	struct wiphy *wiphy;
-+	u8 i;
-+	int ret;
-+
-+	wiphy = adapter_to_wiphy(adapter);
-+	if (!wiphy) {
-+		ret = -EINVAL;
-+		goto err_out;
-+	}
-+
-+	/* allocate memory */
-+	skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
-+	if (!skb) {
-+		ret = -ENOMEM;
-+		goto err_out;
-+	}
-+
-+	/* create the message headers */
-+	msg_header = genlmsg_put(skb, 0, 0, &nlrtw_genl_family, 0, NLRTW_CMD_RADAR_EVENT);
-+	if (!msg_header) {
-+		ret = -ENOMEM;
-+		goto err_out;
-+	}
-+
-+	/* add attributes */
-+	ret = nla_put_string(skb, NLRTW_ATTR_WIPHY_NAME, wiphy_name(wiphy));
-+	if (ret)
-+		goto err_out;
-+
-+	ret = nla_put_u8(skb, NLRTW_ATTR_RADAR_EVENT, (uint8_t)evt_type);
-+	if (ret != 0)
-+		goto err_out;
-+
-+	ret = nla_put_u8(skb, NLRTW_ATTR_CHANNEL_CENTER, cch);
-+	if (ret != 0)
-+		goto err_out;
-+
-+	ret = nla_put_u8(skb, NLRTW_ATTR_CHANNEL_WIDTH, bw);
-+	if (ret != 0)
-+		goto err_out;
-+
-+	/* finalize the message */
-+	genlmsg_end(skb, msg_header);
-+
-+	ret = nlrtw_multicast(&nlrtw_genl_family, skb, 0, NLRTW_MCGRP_DEFAULT, GFP_KERNEL);
-+	if (ret == -ESRCH) {
-+		RTW_DBG(FUNC_WIPHY_FMT" return -ESRCH(No such process)."
-+			 " Maybe no process waits for this msg\n", FUNC_WIPHY_ARG(wiphy));
-+		return ret;
-+	} else if (ret != 0) {
-+		RTW_WARN(FUNC_WIPHY_FMT" return %d\n", FUNC_WIPHY_ARG(wiphy), ret);
-+		return ret;
-+	}
-+
-+	return 0;
-+
-+err_out:
-+	if (skb)
-+		nlmsg_free(skb);
-+	return ret;
-+}
-+
-+int rtw_nlrtw_radar_detect_event(_adapter *adapter, u8 cch, u8 bw)
-+{
-+	return _rtw_nlrtw_radar_event(adapter, NLRTW_RADAR_DETECTED, cch, bw);
-+}
-+
-+int rtw_nlrtw_cac_finish_event(_adapter *adapter, u8 cch, u8 bw)
-+{
-+	return _rtw_nlrtw_radar_event(adapter, NLRTW_RADAR_CAC_FINISHED, cch, bw);
-+}
-+
-+int rtw_nlrtw_cac_abort_event(_adapter *adapter, u8 cch, u8 bw)
-+{
-+	return _rtw_nlrtw_radar_event(adapter, NLRTW_RADAR_CAC_ABORTED, cch, bw);
-+}
-+
-+int rtw_nlrtw_nop_finish_event(_adapter *adapter, u8 cch, u8 bw)
-+{
-+	return _rtw_nlrtw_radar_event(adapter, NLRTW_RADAR_NOP_FINISHED, cch, bw);
-+}
-+
-+int rtw_nlrtw_nop_start_event(_adapter *adapter, u8 cch, u8 bw)
-+{
-+	return _rtw_nlrtw_radar_event(adapter, NLRTW_RADAR_NOP_STARTED, cch, bw);
-+}
-+#endif /* CONFIG_DFS_MASTER */
-+
-+int rtw_nlrtw_radio_opmode_notify(struct rf_ctl_t *rfctl)
-+{
-+	struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl);
-+	_adapter *iface;
-+	struct sk_buff *skb = NULL;
-+	void *msg_header = NULL;
-+	struct nlattr *nl_if_opmodes, *nl_if_opmode;
-+	struct wiphy *wiphy;
-+	u16 op_txpwr_max_u16;
-+	u8 i;
-+	int ret;
-+
-+	wiphy = dvobj_to_wiphy(dvobj);
-+	if (!wiphy) {
-+		ret = -EINVAL;
-+		goto err_out;
-+	}
-+
-+	/* allocate memory */
-+	skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
-+	if (!skb) {
-+		ret = -ENOMEM;
-+		goto err_out;
-+	}
-+
-+	/* create the message headers */
-+	msg_header = genlmsg_put(skb, 0, 0, &nlrtw_genl_family, 0, NLRTW_CMD_RADIO_OPMODE);
-+	if (!msg_header) {
-+		ret = -ENOBUFS;
-+		goto err_out;
-+	}
-+
-+	/* add attributes */
-+	ret = nla_put_string(skb, NLRTW_ATTR_WIPHY_NAME, wiphy_name(wiphy));
-+	if (ret)
-+		goto err_out;
-+
-+	ret = nla_put_u8(skb, NLRTW_ATTR_OP_CLASS, rfctl->op_class);
-+	if (ret != 0)
-+		goto err_out;
-+
-+	ret = nla_put_u8(skb, NLRTW_ATTR_OP_CHANNEL, rfctl->op_ch);
-+	if (ret != 0)
-+		goto err_out;
-+
-+	*((s16 *)&op_txpwr_max_u16) = rfctl->op_txpwr_max;
-+	ret = nla_put_u16(skb, NLRTW_ATTR_OP_TXPWR_MAX, op_txpwr_max_u16);
-+	if (ret != 0)
-+		goto err_out;
-+
-+	if (0)
-+		RTW_INFO("radio: %u,%u %d\n", rfctl->op_class, rfctl->op_ch, rfctl->op_txpwr_max);
-+
-+	nl_if_opmodes = nla_nest_start(skb, NLRTW_ATTR_IF_OPMODES);
-+	if (!nl_if_opmodes) {
-+		ret = -ENOBUFS;
-+		goto err_out;
-+	}
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		if (!dvobj->padapters[i])
-+			continue;
-+		iface = dvobj->padapters[i];
-+
-+		if (!rfctl->if_op_class[i] || !rfctl->if_op_ch[i])
-+			continue;
-+
-+		if (0)
-+			RTW_INFO(ADPT_FMT": %u,%u\n", ADPT_ARG(iface), rfctl->if_op_class[i], rfctl->if_op_ch[i]);
-+
-+		nl_if_opmode = nla_nest_start(skb, i + 1);
-+		if (!nl_if_opmode) {
-+			ret = -ENOBUFS;
-+			goto err_out;
-+		}
-+
-+		ret = nla_put(skb, NLRTW_IF_OPMODE_MACADDR, ETH_ALEN, adapter_mac_addr(iface));
-+		if (ret != 0)
-+			goto err_out;
-+
-+		ret = nla_put_u8(skb, NLRTW_IF_OPMODE_OP_CLASS, rfctl->if_op_class[i]);
-+		if (ret != 0)
-+			goto err_out;
-+
-+		ret = nla_put_u8(skb, NLRTW_IF_OPMODE_OP_CHANNEL, rfctl->if_op_ch[i]);
-+		if (ret != 0)
-+			goto err_out;
-+
-+		nla_nest_end(skb, nl_if_opmode);
-+	}
-+
-+	nla_nest_end(skb, nl_if_opmodes);
-+
-+	/* finalize the message */
-+	genlmsg_end(skb, msg_header);
-+
-+	ret = nlrtw_multicast(&nlrtw_genl_family, skb, 0, NLRTW_MCGRP_DEFAULT, GFP_KERNEL);
-+	if (ret == -ESRCH) {
-+		RTW_DBG(FUNC_WIPHY_FMT" return -ESRCH(No such process)."
-+			 " Maybe no process waits for this msg\n", FUNC_WIPHY_ARG(wiphy));
-+		return ret;
-+	} else if (ret != 0) {
-+		RTW_WARN(FUNC_WIPHY_FMT" return %d\n", FUNC_WIPHY_ARG(wiphy), ret);
-+		return ret;
-+	}
-+
-+	return 0;
-+
-+err_out:
-+	if (skb)
-+		nlmsg_free(skb);
-+	return ret;
-+}
-+
-+int rtw_nlrtw_init(void)
-+{
-+	int err;
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)
-+	err = genl_register_family(&nlrtw_genl_family);
-+	if (err)
-+		return err;
-+#else
-+	err = genl_register_family_with_ops(&nlrtw_genl_family, nlrtw_genl_ops, ARRAY_SIZE(nlrtw_genl_ops));
-+	if (err)
-+		return err;
-+
-+	err = genl_register_mc_group(&nlrtw_genl_family, &nlrtw_genl_mcgrp[0]);
-+	if (err) {
-+		genl_unregister_family(&nlrtw_genl_family);
-+		return err;
-+	}
-+#endif
-+	RTW_INFO("[%s] %s\n", __func__, nlrtw_genl_family.name);
-+	return 0;
-+}
-+
-+int rtw_nlrtw_deinit(void)
-+{
-+	int err;
-+
-+	err = genl_unregister_family(&nlrtw_genl_family);
-+	RTW_INFO("[%s] err = %d\n", __func__, err);
-+
-+	return err;
-+}
-+#endif /* CONFIG_RTW_NLRTW */
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/nlrtw.h b/drivers/staging/rtl8723cs/os_dep/linux/nlrtw.h
-new file mode 100644
-index 000000000000..374002a8a057
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/nlrtw.h
-@@ -0,0 +1,48 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2020 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_NLRTW_H_
-+#define __RTW_NLRTW_H_
-+
-+#ifdef CONFIG_RTW_NLRTW
-+int rtw_nlrtw_init(void);
-+int rtw_nlrtw_deinit(void);
-+int rtw_nlrtw_ch_util_rpt(_adapter *adapter, u8 n_rpts, u8 *val, u8 **mac_addr);
-+int rtw_nlrtw_reg_change_event(_adapter *adapter);
-+int rtw_nlrtw_reg_beacon_hint_event(_adapter *adapter);
-+int rtw_nlrtw_radio_opmode_notify(struct rf_ctl_t *rfctl);
-+#else
-+static inline int rtw_nlrtw_init(void) {return _FAIL;}
-+static inline int rtw_nlrtw_deinit(void) {return _FAIL;}
-+static inline int rtw_nlrtw_ch_util_rpt(_adapter *adapter, u8 n_rpts, u8 *val, u8 **mac_addr) {return _FAIL;}
-+static inline int rtw_nlrtw_reg_change_event(_adapter *adapter) {return _FAIL;}
-+static inline int rtw_nlrtw_reg_beacon_hint_event(_adapter *adapter) {return _FAIL;}
-+static inline int rtw_nlrtw_radio_opmode_notify(struct rf_ctl_t *rfctl) {return _FAIL;}
-+#endif /* CONFIG_RTW_NLRTW */
-+
-+#if defined(CONFIG_RTW_NLRTW) && defined(CONFIG_DFS_MASTER)
-+int rtw_nlrtw_radar_detect_event(_adapter *adapter, u8 cch, u8 bw);
-+int rtw_nlrtw_cac_finish_event(_adapter *adapter, u8 cch, u8 bw);
-+int rtw_nlrtw_cac_abort_event(_adapter *adapter, u8 cch, u8 bw);
-+int rtw_nlrtw_nop_finish_event(_adapter *adapter, u8 cch, u8 bw);
-+int rtw_nlrtw_nop_start_event(_adapter *adapter, u8 cch, u8 bw);
-+#else
-+static inline int rtw_nlrtw_radar_detect_event(_adapter *adapter, u8 cch, u8 bw) {return _FAIL;}
-+static inline int rtw_nlrtw_cac_finish_event(_adapter *adapter, u8 cch, u8 bw) {return _FAIL;}
-+static inline int rtw_nlrtw_cac_abort_event(_adapter *adapter, u8 cch, u8 bw) {return _FAIL;}
-+static inline int rtw_nlrtw_nop_finish_event(_adapter *adapter, u8 cch, u8 bw) {return _FAIL;}
-+static inline int rtw_nlrtw_nop_start_event(_adapter *adapter, u8 cch, u8 bw) {return _FAIL;}
-+#endif /* defined(CONFIG_RTW_NLRTW) && defined(CONFIG_DFS_MASTER) */
-+
-+#endif /* __RTW_NLRTW_H_ */
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/os_intfs.c b/drivers/staging/rtl8723cs/os_dep/linux/os_intfs.c
-new file mode 100644
-index 000000000000..c982c2d0447b
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/os_intfs.c
-@@ -0,0 +1,5744 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _OS_INTFS_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("Realtek Wireless Lan Driver");
-+MODULE_AUTHOR("Realtek Semiconductor Corp.");
-+MODULE_VERSION(DRIVERVERSION);
-+
-+/* module param defaults */
-+int rtw_chip_version = 0x00;
-+int rtw_rfintfs = HWPI;
-+int rtw_lbkmode = 0;/* RTL8712_AIR_TRX; */
-+#ifdef DBG_LA_MODE
-+int rtw_la_mode_en=0;
-+module_param(rtw_la_mode_en, int, 0644);
-+#endif
-+int rtw_network_mode = Ndis802_11IBSS;/* Ndis802_11Infrastructure; */ /* infra, ad-hoc, auto */
-+/* NDIS_802_11_SSID	ssid; */
-+int rtw_channel = 1;/* ad-hoc support requirement */
-+int rtw_wireless_mode = WIRELESS_MODE_MAX;
-+module_param(rtw_wireless_mode, int, 0644);
-+int rtw_vrtl_carrier_sense = AUTO_VCS;
-+int rtw_vcs_type = RTS_CTS;
-+int rtw_rts_thresh = 2347;
-+int rtw_frag_thresh = 2346;
-+int rtw_preamble = PREAMBLE_LONG;/* long, short, auto */
-+int rtw_scan_mode = 1;/* active, passive */
-+/* int smart_ps = 1; */
-+#ifdef CONFIG_POWER_SAVING
-+	/* IPS configuration */
-+	int rtw_ips_mode = RTW_IPS_MODE;
-+
-+	/* LPS configuration */
-+/* RTW_LPS_MODE=0:disable, 1:LPS , 2:LPS with clock gating, 3: power gating */
-+#if (RTW_LPS_MODE > 0)
-+	int rtw_power_mgnt = PS_MODE_MAX;
-+
-+	#ifdef CONFIG_USB_HCI
-+		int rtw_lps_level = LPS_NORMAL; /*USB default LPS level*/
-+	#else /*SDIO,PCIE*/
-+		int rtw_lps_level = (RTW_LPS_MODE - 1);
-+	#endif/*CONFIG_USB_HCI*/
-+#else
-+	int rtw_power_mgnt = PS_MODE_ACTIVE;
-+	int rtw_lps_level = LPS_NORMAL;
-+#endif
-+
-+	int rtw_lps_chk_by_tp = 1;
-+
-+	/* WOW LPS configuration */
-+#ifdef CONFIG_WOWLAN
-+/* RTW_WOW_LPS_MODE=0:disable, 1:LPS , 2:LPS with clock gating, 3: power gating */
-+#if (RTW_WOW_LPS_MODE > 0)
-+	int rtw_wow_power_mgnt = PS_MODE_MAX;
-+	int rtw_wow_lps_level = (RTW_WOW_LPS_MODE - 1);
-+#else
-+	int rtw_wow_power_mgnt = PS_MODE_ACTIVE;
-+	int rtw_wow_lps_level = LPS_NORMAL;
-+#endif	
-+#endif /* CONFIG_WOWLAN */
-+
-+#else /* !CONFIG_POWER_SAVING */
-+	int rtw_ips_mode = IPS_NONE;
-+	int rtw_power_mgnt = PS_MODE_ACTIVE;
-+	int rtw_lps_level = LPS_NORMAL;
-+	int rtw_lps_chk_by_tp = 0;
-+#ifdef CONFIG_WOWLAN
-+	int rtw_wow_power_mgnt = PS_MODE_ACTIVE;
-+	int rtw_wow_lps_level = LPS_NORMAL;
-+#endif /* CONFIG_WOWLAN */
-+#endif /* CONFIG_POWER_SAVING */
-+
-+#ifdef CONFIG_NARROWBAND_SUPPORTING
-+int rtw_nb_config = CONFIG_NB_VALUE;
-+module_param(rtw_nb_config, int, 0644);
-+MODULE_PARM_DESC(rtw_nb_config, "5M/10M/Normal bandwidth configuration");
-+#endif
-+
-+module_param(rtw_ips_mode, int, 0644);
-+MODULE_PARM_DESC(rtw_ips_mode, "The default IPS mode");
-+
-+module_param(rtw_lps_level, int, 0644);
-+MODULE_PARM_DESC(rtw_lps_level, "The default LPS level");
-+
-+#ifdef CONFIG_LPS_1T1R
-+int rtw_lps_1t1r = RTW_LPS_1T1R;
-+module_param(rtw_lps_1t1r, int, 0644);
-+MODULE_PARM_DESC(rtw_lps_1t1r, "The default LPS 1T1R setting");
-+#endif
-+
-+module_param(rtw_lps_chk_by_tp, int, 0644);
-+
-+#ifdef CONFIG_WOWLAN
-+module_param(rtw_wow_power_mgnt, int, 0644);
-+MODULE_PARM_DESC(rtw_wow_power_mgnt, "The default WOW LPS mode");
-+module_param(rtw_wow_lps_level, int, 0644);
-+MODULE_PARM_DESC(rtw_wow_lps_level, "The default WOW LPS level");
-+#ifdef CONFIG_LPS_1T1R
-+int rtw_wow_lps_1t1r = RTW_WOW_LPS_1T1R;
-+module_param(rtw_wow_lps_1t1r, int, 0644);
-+MODULE_PARM_DESC(rtw_wow_lps_1t1r, "The default WOW LPS 1T1R setting");
-+#endif
-+#endif /* CONFIG_WOWLAN */
-+
-+/* LPS: 
-+ * rtw_smart_ps = 0 => TX: pwr bit = 1, RX: PS_Poll
-+ * rtw_smart_ps = 1 => TX: pwr bit = 0, RX: PS_Poll
-+ * rtw_smart_ps = 2 => TX: pwr bit = 0, RX: NullData with pwr bit = 0
-+*/
-+int rtw_smart_ps = 2;
-+
-+int rtw_max_bss_cnt = 0;
-+module_param(rtw_max_bss_cnt, int, 0644);
-+#ifdef CONFIG_WMMPS_STA	
-+/* WMMPS: 
-+ * rtw_smart_ps = 0 => Only for fw test
-+ * rtw_smart_ps = 1 => Refer to Beacon's TIM Bitmap
-+ * rtw_smart_ps = 2 => Don't refer to Beacon's TIM Bitmap
-+*/
-+int rtw_wmm_smart_ps = 2;
-+#endif /* CONFIG_WMMPS_STA */
-+
-+int rtw_check_fw_ps = 1;
-+
-+#ifdef CONFIG_TX_EARLY_MODE
-+int rtw_early_mode = 1;
-+#endif
-+
-+int rtw_usb_rxagg_mode = 2;/* RX_AGG_DMA=1, RX_AGG_USB=2 */
-+module_param(rtw_usb_rxagg_mode, int, 0644);
-+
-+int rtw_dynamic_agg_enable = 1;
-+module_param(rtw_dynamic_agg_enable, int, 0644);
-+
-+/* set log level when inserting driver module, default log level is _DRV_INFO_ = 4,
-+* please refer to "How_to_set_driver_debug_log_level.doc" to set the available level.
-+*/
-+#ifdef CONFIG_RTW_DEBUG
-+#ifdef RTW_LOG_LEVEL
-+	uint rtw_drv_log_level = (uint)RTW_LOG_LEVEL; /* from Makefile */
-+#else
-+	uint rtw_drv_log_level = _DRV_INFO_;
-+#endif
-+module_param(rtw_drv_log_level, uint, 0644);
-+MODULE_PARM_DESC(rtw_drv_log_level, "set log level when insert driver module, default log level is _DRV_INFO_ = 4");
-+#endif
-+int rtw_radio_enable = 1;
-+int rtw_long_retry_lmt = 7;
-+int rtw_short_retry_lmt = 7;
-+int rtw_busy_thresh = 40;
-+/* int qos_enable = 0; */ /* * */
-+int rtw_ack_policy = NORMAL_ACK;
-+
-+int rtw_mp_mode = 0;
-+
-+#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
-+uint rtw_mp_customer_str = 0;
-+module_param(rtw_mp_customer_str, uint, 0644);
-+MODULE_PARM_DESC(rtw_mp_customer_str, "Whether or not to enable customer str support on MP mode");
-+#endif
-+
-+int rtw_software_encrypt = 0;
-+int rtw_software_decrypt = 0;
-+
-+int rtw_acm_method = 0;/* 0:By SW 1:By HW. */
-+
-+int rtw_wmm_enable = 1;/* default is set to enable the wmm. */
-+
-+#ifdef CONFIG_WMMPS_STA
-+/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */
-+/* 0: NO_LIMIT, 1: TWO_MSDU, 2: FOUR_MSDU, 3: SIX_MSDU */
-+int rtw_uapsd_max_sp = NO_LIMIT;
-+/* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */
-+int rtw_uapsd_ac_enable = 0x0;
-+#endif /* CONFIG_WMMPS_STA */
-+
-+#if defined(CONFIG_RTL8814A)
-+	int rtw_pwrtrim_enable = 2; /* disable kfree , rename to power trim disable */
-+#elif defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)
-+	/*PHYDM API, must enable by default*/
-+	int rtw_pwrtrim_enable = 1;
-+#else
-+	int rtw_pwrtrim_enable = 0; /* Default Enalbe  power trim by efuse config */
-+#endif
-+
-+#if CONFIG_TX_AC_LIFETIME
-+uint rtw_tx_aclt_flags = CONFIG_TX_ACLT_FLAGS;
-+module_param(rtw_tx_aclt_flags, uint, 0644);
-+MODULE_PARM_DESC(rtw_tx_aclt_flags, "device TX AC queue packet lifetime control flags");
-+
-+static uint rtw_tx_aclt_conf_default[3] = CONFIG_TX_ACLT_CONF_DEFAULT;
-+static uint rtw_tx_aclt_conf_default_num = 0;
-+module_param_array(rtw_tx_aclt_conf_default, uint, &rtw_tx_aclt_conf_default_num, 0644);
-+MODULE_PARM_DESC(rtw_tx_aclt_conf_default, "device TX AC queue lifetime config for default status");
-+
-+#ifdef CONFIG_AP_MODE
-+#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+static uint rtw_tx_aclt_conf_ap_m2u[3] = CONFIG_TX_ACLT_CONF_AP_M2U;
-+static uint rtw_tx_aclt_conf_ap_m2u_num = 0;
-+module_param_array(rtw_tx_aclt_conf_ap_m2u, uint, &rtw_tx_aclt_conf_ap_m2u_num, 0644);
-+MODULE_PARM_DESC(rtw_tx_aclt_conf_ap_m2u, "device TX AC queue lifetime config for AP mode M2U status");
-+#endif
-+#endif /* CONFIG_AP_MODE */
-+
-+#ifdef CONFIG_RTW_MESH
-+static uint rtw_tx_aclt_conf_mesh[3] = CONFIG_TX_ACLT_CONF_MESH;
-+static uint rtw_tx_aclt_conf_mesh_num = 0;
-+module_param_array(rtw_tx_aclt_conf_mesh, uint, &rtw_tx_aclt_conf_mesh_num, 0644);
-+MODULE_PARM_DESC(rtw_tx_aclt_conf_mesh, "device TX AC queue lifetime config for MESH status");
-+#endif
-+#endif /* CONFIG_TX_AC_LIFETIME */
-+
-+uint rtw_tx_bw_mode = 0x21;
-+module_param(rtw_tx_bw_mode, uint, 0644);
-+MODULE_PARM_DESC(rtw_tx_bw_mode, "The max tx bw for 2.4G and 5G. format is the same as rtw_bw_mode");
-+
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+uint rtw_tbtt_rpt = 0;	/*ROOT AP - BIT0, VAP1 - BIT1, VAP2 - BIT2, VAP3 - VAP3, FW report TBTT INT by C2H*/
-+module_param(rtw_tbtt_rpt, uint, 0644);
-+#endif
-+
-+#ifdef CONFIG_80211N_HT
-+int rtw_ht_enable = 1;
-+/* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz, 4: 80+80MHz
-+* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7
-+* 0x21 means enable 2.4G 40MHz & 5G 80MHz */
-+#ifdef CONFIG_RTW_CUSTOMIZE_BWMODE
-+int rtw_bw_mode = CONFIG_RTW_CUSTOMIZE_BWMODE;
-+#else
-+int rtw_bw_mode = 0x21;
-+#endif
-+int rtw_ampdu_enable = 1;/* for enable tx_ampdu , */ /* 0: disable, 0x1:enable */
-+int rtw_rx_stbc = 1;/* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */
-+#if (defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8814B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI)
-+int rtw_rx_ampdu_amsdu = 2;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */
-+#elif ((defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_SDIO_HCI))
-+int rtw_rx_ampdu_amsdu = 1;
-+#else
-+int rtw_rx_ampdu_amsdu;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */
-+#endif
-+/*
-+* 2: Follow the AMSDU filed in ADDBA Resp. (Deault)
-+* 0: Force the AMSDU filed in ADDBA Resp. to be disabled.
-+* 1: Force the AMSDU filed in ADDBA Resp. to be enabled.
-+*/
-+int rtw_tx_ampdu_amsdu = 2;
-+
-+int rtw_quick_addba_req = 0;
-+
-+static uint rtw_rx_ampdu_sz_limit_1ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS;
-+static uint rtw_rx_ampdu_sz_limit_1ss_num = 0;
-+module_param_array(rtw_rx_ampdu_sz_limit_1ss, uint, &rtw_rx_ampdu_sz_limit_1ss_num, 0644);
-+MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_1ss, "RX AMPDU size limit for 1SS link of each BW, 0xFF: no limitation");
-+
-+static uint rtw_rx_ampdu_sz_limit_2ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS;
-+static uint rtw_rx_ampdu_sz_limit_2ss_num = 0;
-+module_param_array(rtw_rx_ampdu_sz_limit_2ss, uint, &rtw_rx_ampdu_sz_limit_2ss_num, 0644);
-+MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_2ss, "RX AMPDU size limit for 2SS link of each BW, 0xFF: no limitation");
-+
-+static uint rtw_rx_ampdu_sz_limit_3ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS;
-+static uint rtw_rx_ampdu_sz_limit_3ss_num = 0;
-+module_param_array(rtw_rx_ampdu_sz_limit_3ss, uint, &rtw_rx_ampdu_sz_limit_3ss_num, 0644);
-+MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_3ss, "RX AMPDU size limit for 3SS link of each BW, 0xFF: no limitation");
-+
-+static uint rtw_rx_ampdu_sz_limit_4ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS;
-+static uint rtw_rx_ampdu_sz_limit_4ss_num = 0;
-+module_param_array(rtw_rx_ampdu_sz_limit_4ss, uint, &rtw_rx_ampdu_sz_limit_4ss_num, 0644);
-+MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_4ss, "RX AMPDU size limit for 4SS link of each BW, 0xFF: no limitation");
-+
-+/* Short GI support Bit Map
-+* BIT0 - 20MHz, 0: non-support, 1: support
-+* BIT1 - 40MHz, 0: non-support, 1: support
-+* BIT2 - 80MHz, 0: non-support, 1: support
-+* BIT3 - 160MHz, 0: non-support, 1: support */
-+int rtw_short_gi = 0xf;
-+/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */
-+int rtw_ldpc_cap = 0x33;
-+/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */
-+#ifdef CONFIG_RTL8192F
-+int rtw_stbc_cap = 0x30;
-+#else
-+int rtw_stbc_cap = 0x13;
-+#endif
-+module_param(rtw_stbc_cap, int, 0644);
-+/*
-+* BIT0: Enable VHT SU Beamformer
-+* BIT1: Enable VHT SU Beamformee
-+* BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer
-+* BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee
-+* BIT4: Enable HT Beamformer
-+* BIT5: Enable HT Beamformee
-+*/
-+int rtw_beamform_cap = BIT(1) | BIT(3);
-+int rtw_bfer_rf_number = 0; /*BeamformerCapRfNum Rf path number, 0 for auto, others for manual*/
-+int rtw_bfee_rf_number = 0; /*BeamformeeCapRfNum  Rf path number, 0 for auto, others for manual*/
-+
-+#endif /* CONFIG_80211N_HT */
-+
-+#ifdef CONFIG_80211AC_VHT
-+int rtw_vht_enable = 1; /* 0:disable, 1:enable, 2:force auto enable */
-+module_param(rtw_vht_enable, int, 0644);
-+
-+int rtw_vht_24g_enable = 1; /* 0:disable, 1:enable */
-+module_param(rtw_vht_24g_enable, int, 0644);
-+
-+int rtw_ampdu_factor = 7;
-+
-+uint rtw_vht_rx_mcs_map = 0xaaaa;
-+module_param(rtw_vht_rx_mcs_map, uint, 0644);
-+MODULE_PARM_DESC(rtw_vht_rx_mcs_map, "VHT RX MCS map");
-+#endif /* CONFIG_80211AC_VHT */
-+
-+
-+/* 0: not check in watch dog, 1: check in watch dog  */
-+int rtw_check_hw_status = 0;
-+
-+int rtw_low_power = 0;
-+int rtw_wifi_spec = 0;
-+
-+
-+int rtw_trx_path_bmp = 0x00;
-+module_param(rtw_trx_path_bmp, int, 0644); /* [7:4]TX path bmp, [0:3]RX path bmp, 0: not specified */
-+
-+#ifdef CONFIG_SPECIAL_RF_PATH /* configure Nss/xTxR IC to 1ss/1T1R */
-+int rtw_tx_path_lmt = 1;
-+int rtw_rx_path_lmt = 1;
-+int rtw_tx_nss = 1;
-+int rtw_rx_nss = 1;
-+#elif defined(CONFIG_CUSTOMER01_SMART_ANTENNA)
-+int rtw_tx_path_lmt = 2;
-+int rtw_rx_path_lmt = 2;
-+int rtw_tx_nss = 1;
-+int rtw_rx_nss = 1;
-+#else
-+int rtw_tx_path_lmt = 0;
-+int rtw_rx_path_lmt = 0;
-+int rtw_tx_nss = 0;
-+int rtw_rx_nss = 0;
-+#endif
-+module_param(rtw_tx_path_lmt, int, 0644); /* limit of TX path number, 0: not specified */
-+module_param(rtw_rx_path_lmt, int, 0644); /* limit of RX path number, 0: not specified */
-+module_param(rtw_tx_nss, int, 0644);
-+module_param(rtw_rx_nss, int, 0644);
-+
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+static uint rtw_regd_src = CONFIG_RTW_REGD_SRC;
-+module_param(rtw_regd_src, uint, 0644);
-+MODULE_PARM_DESC(rtw_regd_src, "The default regd source selection, 0:Realtek defined, 1: OS");
-+#endif
-+
-+char rtw_country_unspecified[] = {0xFF, 0xFF, 0x00};
-+char *rtw_country_code = rtw_country_unspecified;
-+module_param(rtw_country_code, charp, 0644);
-+MODULE_PARM_DESC(rtw_country_code, "The default country code (in alpha2)");
-+
-+int rtw_channel_plan = CONFIG_RTW_CHPLAN;
-+module_param(rtw_channel_plan, int, 0644);
-+MODULE_PARM_DESC(rtw_channel_plan, "The default chplan ID when rtw_alpha2 is not specified or valid");
-+
-+static uint rtw_excl_chs[MAX_CHANNEL_NUM] = CONFIG_RTW_EXCL_CHS;
-+static int rtw_excl_chs_num = 0;
-+module_param_array(rtw_excl_chs, uint, &rtw_excl_chs_num, 0644);
-+MODULE_PARM_DESC(rtw_excl_chs, "exclusive channel array");
-+
-+/*if concurrent softap + p2p(GO) is needed, this param lets p2p response full channel list.
-+But Softap must be SHUT DOWN once P2P decide to set up connection and become a GO.*/
-+#ifdef CONFIG_FULL_CH_IN_P2P_HANDSHAKE
-+	int rtw_full_ch_in_p2p_handshake = 1; /* reply full channel list*/
-+#else
-+	int rtw_full_ch_in_p2p_handshake = 0; /* reply only softap channel*/
-+#endif
-+
-+#ifdef CONFIG_BT_COEXIST
-+int rtw_btcoex_enable = 2;
-+module_param(rtw_btcoex_enable, int, 0644);
-+MODULE_PARM_DESC(rtw_btcoex_enable, "BT co-existence on/off, 0:off, 1:on, 2:by efuse");
-+
-+int rtw_ant_num = 0;
-+module_param(rtw_ant_num, int, 0644);
-+MODULE_PARM_DESC(rtw_ant_num, "Antenna number setting, 0:by efuse");
-+
-+int rtw_bt_iso = 2;/* 0:Low, 1:High, 2:From Efuse */
-+int rtw_bt_sco = 3;/* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy, 5.OtherBusy */
-+int rtw_bt_ampdu = 1 ; /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
-+#endif /* CONFIG_BT_COEXIST */
-+
-+int rtw_AcceptAddbaReq = _TRUE;/* 0:Reject AP's Add BA req, 1:Accept AP's Add BA req. */
-+
-+int rtw_antdiv_cfg = 2; /* 0:OFF , 1:ON, 2:decide by Efuse config */
-+int rtw_antdiv_type = 0
-+	; /* 0:decide by efuse  1: for 88EE, 1Tx and 1RxCG are diversity.(2 Ant with SPDT), 2:  for 88EE, 1Tx and 2Rx are diversity.( 2 Ant, Tx and RxCG are both on aux port, RxCS is on main port ), 3: for 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */
-+
-+int rtw_drv_ant_band_switch = 1; /* 0:OFF , 1:ON, Driver control antenna band switch*/
-+
-+int rtw_single_ant_path; /*0:main ant , 1:aux ant , Fixed single antenna path, default main ant*/
-+
-+/* 0: doesn't switch, 1: switch from usb2.0 to usb 3.0 2: switch from usb3.0 to usb 2.0 */
-+int rtw_switch_usb_mode = 0;
-+
-+#ifdef CONFIG_USB_AUTOSUSPEND
-+int rtw_enusbss = 1;/* 0:disable,1:enable */
-+#else
-+int rtw_enusbss = 0;/* 0:disable,1:enable */
-+#endif
-+
-+int rtw_hwpdn_mode = 2; /* 0:disable,1:enable,2: by EFUSE config */
-+
-+#ifdef CONFIG_HW_PWRP_DETECTION
-+int rtw_hwpwrp_detect = 1;
-+#else
-+int rtw_hwpwrp_detect = 0; /* HW power  ping detect 0:disable , 1:enable */
-+#endif
-+
-+#ifdef CONFIG_USB_HCI
-+int rtw_hw_wps_pbc = 1;
-+#else
-+int rtw_hw_wps_pbc = 0;
-+#endif
-+
-+#ifdef CONFIG_80211D
-+int rtw_80211d = 0;
-+#endif
-+
-+#ifdef CONFIG_PCI_ASPM
-+/* CLK_REQ:BIT0 L0s:BIT1 ASPM_L1:BIT2 L1Off:BIT3*/
-+int	rtw_pci_aspm_enable = 0x5;
-+#else
-+int	rtw_pci_aspm_enable;
-+#endif
-+
-+/*
-+ * BIT [15:12] mask of ps mode
-+ * BIT [11:8] val of ps mode
-+ * BIT [7:4] mask of perf mode
-+ * BIT [3:0] val of perf mode
-+ *
-+ * L0s:BIT[+0] L1:BIT[+1]
-+ *
-+ * 0x0030: change value only if perf mode
-+ * 0x3300: change value only if ps mode
-+ * 0x3330: change value in both perf and ps mode
-+ */
-+#ifdef CONFIG_PCI_DYNAMIC_ASPM
-+#ifdef CONFIG_PCI_ASPM
-+int rtw_pci_dynamic_aspm_linkctrl = 0x3330;
-+#else
-+int rtw_pci_dynamic_aspm_linkctrl = 0x0030;
-+#endif
-+#else
-+int rtw_pci_dynamic_aspm_linkctrl = 0x0000;
-+#endif
-+module_param(rtw_pci_dynamic_aspm_linkctrl, int, 0644);
-+
-+#ifdef CONFIG_QOS_OPTIMIZATION
-+int rtw_qos_opt_enable = 1; /* 0: disable,1:enable */
-+#else
-+int rtw_qos_opt_enable = 0; /* 0: disable,1:enable */
-+#endif
-+module_param(rtw_qos_opt_enable, int, 0644);
-+
-+#ifdef CONFIG_RTW_ACS
-+int rtw_acs_auto_scan = 0; /*0:disable, 1:enable*/
-+module_param(rtw_acs_auto_scan, int, 0644);
-+
-+int rtw_acs = 1;
-+module_param(rtw_acs, int, 0644);
-+#endif
-+
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+int rtw_nm = 1;/*noise monitor*/
-+module_param(rtw_nm, int, 0644);
-+#endif
-+
-+char *ifname = "wlan%d";
-+module_param(ifname, charp, 0644);
-+MODULE_PARM_DESC(ifname, "The default name to allocate for first interface");
-+
-+#ifdef CONFIG_PLATFORM_ANDROID
-+	char *if2name = "p2p%d";
-+#else /* CONFIG_PLATFORM_ANDROID */
-+	char *if2name = "wlan%d";
-+#endif /* CONFIG_PLATFORM_ANDROID */
-+module_param(if2name, charp, 0644);
-+MODULE_PARM_DESC(if2name, "The default name to allocate for second interface");
-+
-+char *rtw_initmac = 0;  /* temp mac address if users want to use instead of the mac address in Efuse */
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+
-+	#if (CONFIG_IFACE_NUMBER > 2)
-+		int rtw_virtual_iface_num = CONFIG_IFACE_NUMBER - 1;
-+		module_param(rtw_virtual_iface_num, int, 0644);
-+	#else
-+		int rtw_virtual_iface_num = 1;
-+	#endif
-+
-+#ifdef CONFIG_P2P
-+
-+	#ifdef CONFIG_SEL_P2P_IFACE
-+	int rtw_sel_p2p_iface = CONFIG_SEL_P2P_IFACE;
-+	#else
-+	int rtw_sel_p2p_iface = IFACE_ID1;
-+	#endif
-+
-+	module_param(rtw_sel_p2p_iface, int, 0644);
-+
-+#endif
-+
-+#endif
-+
-+#ifdef CONFIG_AP_MODE
-+u8 rtw_bmc_tx_rate = MGN_UNKNOWN;
-+
-+#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+int rtw_ap_src_b2u_flags = CONFIG_RTW_AP_SRC_B2U_FLAGS;
-+module_param(rtw_ap_src_b2u_flags, int, 0644);
-+
-+int rtw_ap_fwd_b2u_flags = CONFIG_RTW_AP_FWD_B2U_FLAGS;
-+module_param(rtw_ap_fwd_b2u_flags, int, 0644);
-+#endif /* CONFIG_RTW_AP_DATA_BMC_TO_UC */
-+#endif /* CONFIG_AP_MODE */
-+
-+#ifdef CONFIG_RTW_MESH
-+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+int rtw_msrc_b2u_flags = CONFIG_RTW_MSRC_B2U_FLAGS;
-+module_param(rtw_msrc_b2u_flags, int, 0644);
-+
-+int rtw_mfwd_b2u_flags = CONFIG_RTW_MFWD_B2U_FLAGS;
-+module_param(rtw_mfwd_b2u_flags, int, 0644);
-+#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */
-+#endif /* CONFIG_RTW_MESH */
-+
-+#ifdef RTW_WOW_STA_MIX
-+int rtw_wowlan_sta_mix_mode = 1;
-+#else
-+int rtw_wowlan_sta_mix_mode = 0;
-+#endif
-+module_param(rtw_wowlan_sta_mix_mode, int, 0644);
-+module_param(rtw_pwrtrim_enable, int, 0644);
-+module_param(rtw_initmac, charp, 0644);
-+module_param(rtw_chip_version, int, 0644);
-+module_param(rtw_rfintfs, int, 0644);
-+module_param(rtw_lbkmode, int, 0644);
-+module_param(rtw_network_mode, int, 0644);
-+module_param(rtw_channel, int, 0644);
-+module_param(rtw_mp_mode, int, 0644);
-+module_param(rtw_wmm_enable, int, 0644);
-+#ifdef CONFIG_WMMPS_STA
-+module_param(rtw_uapsd_max_sp, int, 0644);
-+module_param(rtw_uapsd_ac_enable, int, 0644);
-+module_param(rtw_wmm_smart_ps, int, 0644);
-+#endif /* CONFIG_WMMPS_STA */
-+module_param(rtw_vrtl_carrier_sense, int, 0644);
-+module_param(rtw_vcs_type, int, 0644);
-+module_param(rtw_busy_thresh, int, 0644);
-+
-+#ifdef CONFIG_80211N_HT
-+module_param(rtw_ht_enable, int, 0644);
-+module_param(rtw_bw_mode, int, 0644);
-+module_param(rtw_ampdu_enable, int, 0644);
-+module_param(rtw_rx_stbc, int, 0644);
-+module_param(rtw_rx_ampdu_amsdu, int, 0644);
-+module_param(rtw_tx_ampdu_amsdu, int, 0644);
-+module_param(rtw_quick_addba_req, int, 0644);
-+#endif /* CONFIG_80211N_HT */
-+
-+#ifdef CONFIG_BEAMFORMING
-+module_param(rtw_beamform_cap, int, 0644);
-+#endif
-+
-+module_param(rtw_power_mgnt, int, 0644);
-+module_param(rtw_smart_ps, int, 0644);
-+module_param(rtw_low_power, int, 0644);
-+module_param(rtw_wifi_spec, int, 0644);
-+
-+module_param(rtw_full_ch_in_p2p_handshake, int, 0644);
-+module_param(rtw_antdiv_cfg, int, 0644);
-+module_param(rtw_antdiv_type, int, 0644);
-+
-+module_param(rtw_drv_ant_band_switch, int, 0644);
-+module_param(rtw_single_ant_path, int, 0644);
-+
-+module_param(rtw_switch_usb_mode, int, 0644);
-+
-+module_param(rtw_enusbss, int, 0644);
-+module_param(rtw_hwpdn_mode, int, 0644);
-+module_param(rtw_hwpwrp_detect, int, 0644);
-+
-+module_param(rtw_hw_wps_pbc, int, 0644);
-+module_param(rtw_check_hw_status, int, 0644);
-+
-+#ifdef CONFIG_PCI_HCI
-+module_param(rtw_pci_aspm_enable, int, 0644);
-+#endif
-+
-+#ifdef CONFIG_TX_EARLY_MODE
-+module_param(rtw_early_mode, int, 0644);
-+#endif
-+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
-+char *rtw_adaptor_info_caching_file_path = "/data/misc/wifi/rtw_cache";
-+module_param(rtw_adaptor_info_caching_file_path, charp, 0644);
-+MODULE_PARM_DESC(rtw_adaptor_info_caching_file_path, "The path of adapter info cache file");
-+#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */
-+
-+#ifdef CONFIG_LAYER2_ROAMING
-+uint rtw_max_roaming_times = 2;
-+module_param(rtw_max_roaming_times, uint, 0644);
-+MODULE_PARM_DESC(rtw_max_roaming_times, "The max roaming times to try");
-+#endif /* CONFIG_LAYER2_ROAMING */
-+
-+#ifdef CONFIG_IOL
-+int rtw_fw_iol = 1;
-+module_param(rtw_fw_iol, int, 0644);
-+MODULE_PARM_DESC(rtw_fw_iol, "FW IOL. 0:Disable, 1:enable, 2:by usb speed");
-+#endif /* CONFIG_IOL */
-+
-+#ifdef CONFIG_FILE_FWIMG
-+char *rtw_fw_file_path = "/system/etc/firmware/rtlwifi/FW_NIC.BIN";
-+module_param(rtw_fw_file_path, charp, 0644);
-+MODULE_PARM_DESC(rtw_fw_file_path, "The path of fw image");
-+
-+char *rtw_fw_wow_file_path = "/system/etc/firmware/rtlwifi/FW_WoWLAN.BIN";
-+module_param(rtw_fw_wow_file_path, charp, 0644);
-+MODULE_PARM_DESC(rtw_fw_wow_file_path, "The path of fw for Wake on Wireless image");
-+
-+#ifdef CONFIG_MP_INCLUDED
-+char *rtw_fw_mp_bt_file_path = "";
-+module_param(rtw_fw_mp_bt_file_path, charp, 0644);
-+MODULE_PARM_DESC(rtw_fw_mp_bt_file_path, "The path of fw for MP-BT image");
-+#endif /* CONFIG_MP_INCLUDED */
-+#endif /* CONFIG_FILE_FWIMG */
-+
-+#ifdef CONFIG_80211D
-+module_param(rtw_80211d, int, 0644);
-+MODULE_PARM_DESC(rtw_80211d, "Enable 802.11d mechanism");
-+#endif
-+
-+#ifdef CONFIG_ADVANCE_OTA
-+/*	BIT(0): OTA continuous rotated test within low RSSI,1R CCA in path B
-+	BIT(1) & BIT(2): OTA continuous rotated test with low high RSSI */
-+/* Experimental environment: shielding room with half of absorber and 2~3 rotation per minute */
-+int rtw_advnace_ota;
-+module_param(rtw_advnace_ota, int, 0644);
-+#endif
-+
-+uint rtw_notch_filter = RTW_NOTCH_FILTER;
-+module_param(rtw_notch_filter, uint, 0644);
-+MODULE_PARM_DESC(rtw_notch_filter, "0:Disable, 1:Enable, 2:Enable only for P2P");
-+
-+uint rtw_hiq_filter = CONFIG_RTW_HIQ_FILTER;
-+module_param(rtw_hiq_filter, uint, 0644);
-+MODULE_PARM_DESC(rtw_hiq_filter, "0:allow all, 1:allow special, 2:deny all");
-+
-+uint rtw_adaptivity_en = CONFIG_RTW_ADAPTIVITY_EN;
-+module_param(rtw_adaptivity_en, uint, 0644);
-+MODULE_PARM_DESC(rtw_adaptivity_en, "0:disable, 1:enable");
-+
-+uint rtw_adaptivity_mode = CONFIG_RTW_ADAPTIVITY_MODE;
-+module_param(rtw_adaptivity_mode, uint, 0644);
-+MODULE_PARM_DESC(rtw_adaptivity_mode, "0:normal, 1:carrier sense");
-+
-+int rtw_adaptivity_th_l2h_ini = CONFIG_RTW_ADAPTIVITY_TH_L2H_INI;
-+module_param(rtw_adaptivity_th_l2h_ini, int, 0644);
-+MODULE_PARM_DESC(rtw_adaptivity_th_l2h_ini, "th_l2h_ini for Adaptivity");
-+
-+int rtw_adaptivity_th_edcca_hl_diff = CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF;
-+module_param(rtw_adaptivity_th_edcca_hl_diff, int, 0644);
-+MODULE_PARM_DESC(rtw_adaptivity_th_edcca_hl_diff, "th_edcca_hl_diff for Adaptivity");
-+
-+#ifdef CONFIG_DFS_MASTER
-+uint rtw_dfs_region_domain = CONFIG_RTW_DFS_REGION_DOMAIN;
-+module_param(rtw_dfs_region_domain, uint, 0644);
-+MODULE_PARM_DESC(rtw_dfs_region_domain, "0:NONE, 1:FCC, 2:MKK, 3:ETSI");
-+#endif
-+
-+uint rtw_amplifier_type_2g = CONFIG_RTW_AMPLIFIER_TYPE_2G;
-+module_param(rtw_amplifier_type_2g, uint, 0644);
-+MODULE_PARM_DESC(rtw_amplifier_type_2g, "BIT3:2G ext-PA, BIT4:2G ext-LNA");
-+
-+uint rtw_amplifier_type_5g = CONFIG_RTW_AMPLIFIER_TYPE_5G;
-+module_param(rtw_amplifier_type_5g, uint, 0644);
-+MODULE_PARM_DESC(rtw_amplifier_type_5g, "BIT6:5G ext-PA, BIT7:5G ext-LNA");
-+
-+uint rtw_RFE_type = CONFIG_RTW_RFE_TYPE;
-+module_param(rtw_RFE_type, uint, 0644);
-+MODULE_PARM_DESC(rtw_RFE_type, "default init value:64");
-+
-+uint rtw_powertracking_type = 64;
-+module_param(rtw_powertracking_type, uint, 0644);
-+MODULE_PARM_DESC(rtw_powertracking_type, "default init value:64");
-+
-+uint rtw_GLNA_type = CONFIG_RTW_GLNA_TYPE;
-+module_param(rtw_GLNA_type, uint, 0644);
-+MODULE_PARM_DESC(rtw_GLNA_type, "default init value:0");
-+
-+uint rtw_TxBBSwing_2G = 0xFF;
-+module_param(rtw_TxBBSwing_2G, uint, 0644);
-+MODULE_PARM_DESC(rtw_TxBBSwing_2G, "default init value:0xFF");
-+
-+uint rtw_TxBBSwing_5G = 0xFF;
-+module_param(rtw_TxBBSwing_5G, uint, 0644);
-+MODULE_PARM_DESC(rtw_TxBBSwing_5G, "default init value:0xFF");
-+
-+uint rtw_OffEfuseMask = 0;
-+module_param(rtw_OffEfuseMask, uint, 0644);
-+MODULE_PARM_DESC(rtw_OffEfuseMask, "default open Efuse Mask value:0");
-+
-+uint rtw_FileMaskEfuse = 0;
-+module_param(rtw_FileMaskEfuse, uint, 0644);
-+MODULE_PARM_DESC(rtw_FileMaskEfuse, "default drv Mask Efuse value:0");
-+
-+uint rtw_rxgain_offset_2g = 0;
-+module_param(rtw_rxgain_offset_2g, uint, 0644);
-+MODULE_PARM_DESC(rtw_rxgain_offset_2g, "default RF Gain 2G Offset value:0");
-+
-+uint rtw_rxgain_offset_5gl = 0;
-+module_param(rtw_rxgain_offset_5gl, uint, 0644);
-+MODULE_PARM_DESC(rtw_rxgain_offset_5gl, "default RF Gain 5GL Offset value:0");
-+
-+uint rtw_rxgain_offset_5gm = 0;
-+module_param(rtw_rxgain_offset_5gm, uint, 0644);
-+MODULE_PARM_DESC(rtw_rxgain_offset_5gm, "default RF Gain 5GM Offset value:0");
-+
-+uint rtw_rxgain_offset_5gh = 0;
-+module_param(rtw_rxgain_offset_5gh, uint, 0644);
-+MODULE_PARM_DESC(rtw_rxgain_offset_5gm, "default RF Gain 5GL Offset value:0");
-+
-+uint rtw_pll_ref_clk_sel = CONFIG_RTW_PLL_REF_CLK_SEL;
-+module_param(rtw_pll_ref_clk_sel, uint, 0644);
-+MODULE_PARM_DESC(rtw_pll_ref_clk_sel, "force pll_ref_clk_sel, 0xF:use autoload value");
-+
-+int rtw_tx_pwr_by_rate = CONFIG_TXPWR_BY_RATE_EN;
-+module_param(rtw_tx_pwr_by_rate, int, 0644);
-+MODULE_PARM_DESC(rtw_tx_pwr_by_rate, "0:Disable, 1:Enable, 2: Depend on efuse");
-+
-+#if CONFIG_TXPWR_LIMIT
-+int rtw_tx_pwr_lmt_enable = CONFIG_TXPWR_LIMIT_EN;
-+module_param(rtw_tx_pwr_lmt_enable, int, 0644);
-+MODULE_PARM_DESC(rtw_tx_pwr_lmt_enable, "0:Disable, 1:Enable, 2: Depend on efuse");
-+#endif
-+
-+static int rtw_target_tx_pwr_2g_a[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_A;
-+static int rtw_target_tx_pwr_2g_a_num = 0;
-+module_param_array(rtw_target_tx_pwr_2g_a, int, &rtw_target_tx_pwr_2g_a_num, 0644);
-+MODULE_PARM_DESC(rtw_target_tx_pwr_2g_a, "2.4G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined");
-+
-+static int rtw_target_tx_pwr_2g_b[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_B;
-+static int rtw_target_tx_pwr_2g_b_num = 0;
-+module_param_array(rtw_target_tx_pwr_2g_b, int, &rtw_target_tx_pwr_2g_b_num, 0644);
-+MODULE_PARM_DESC(rtw_target_tx_pwr_2g_b, "2.4G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined");
-+
-+static int rtw_target_tx_pwr_2g_c[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_C;
-+static int rtw_target_tx_pwr_2g_c_num = 0;
-+module_param_array(rtw_target_tx_pwr_2g_c, int, &rtw_target_tx_pwr_2g_c_num, 0644);
-+MODULE_PARM_DESC(rtw_target_tx_pwr_2g_c, "2.4G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined");
-+
-+static int rtw_target_tx_pwr_2g_d[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_D;
-+static int rtw_target_tx_pwr_2g_d_num = 0;
-+module_param_array(rtw_target_tx_pwr_2g_d, int, &rtw_target_tx_pwr_2g_d_num, 0644);
-+MODULE_PARM_DESC(rtw_target_tx_pwr_2g_d, "2.4G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined");
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+static int rtw_target_tx_pwr_5g_a[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_A;
-+static int rtw_target_tx_pwr_5g_a_num = 0;
-+module_param_array(rtw_target_tx_pwr_5g_a, int, &rtw_target_tx_pwr_5g_a_num, 0644);
-+MODULE_PARM_DESC(rtw_target_tx_pwr_5g_a, "5G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined");
-+
-+static int rtw_target_tx_pwr_5g_b[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_B;
-+static int rtw_target_tx_pwr_5g_b_num = 0;
-+module_param_array(rtw_target_tx_pwr_5g_b, int, &rtw_target_tx_pwr_5g_b_num, 0644);
-+MODULE_PARM_DESC(rtw_target_tx_pwr_5g_b, "5G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined");
-+
-+static int rtw_target_tx_pwr_5g_c[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_C;
-+static int rtw_target_tx_pwr_5g_c_num = 0;
-+module_param_array(rtw_target_tx_pwr_5g_c, int, &rtw_target_tx_pwr_5g_c_num, 0644);
-+MODULE_PARM_DESC(rtw_target_tx_pwr_5g_c, "5G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined");
-+
-+static int rtw_target_tx_pwr_5g_d[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_D;
-+static int rtw_target_tx_pwr_5g_d_num = 0;
-+module_param_array(rtw_target_tx_pwr_5g_d, int, &rtw_target_tx_pwr_5g_d_num, 0644);
-+MODULE_PARM_DESC(rtw_target_tx_pwr_5g_d, "5G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined");
-+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-+
-+int rtw_antenna_gain = CONFIG_RTW_ANTENNA_GAIN;
-+module_param(rtw_antenna_gain, int, 0644);
-+MODULE_PARM_DESC(rtw_antenna_gain, "Antenna gain in mBi. 0x7FFF: unspecifed");
-+
-+#ifdef CONFIG_RTW_TX_NPATH_EN
-+/*0:disable ,1: 2path*/
-+int rtw_tx_npath_enable = 1;
-+module_param(rtw_tx_npath_enable, int, 0644);
-+MODULE_PARM_DESC(rtw_tx_npath_enable, "0:Disable, 1:TX-2PATH");
-+#endif
-+
-+#ifdef CONFIG_RTW_PATH_DIV
-+/*0:disable ,1: path diversity*/
-+int rtw_path_div_enable = 1;
-+module_param(rtw_path_div_enable, int, 0644);
-+MODULE_PARM_DESC(rtw_path_div_enable, "0:Disable, 1:Enable path diversity");
-+#endif
-+
-+
-+int rtw_tsf_update_pause_factor = CONFIG_TSF_UPDATE_PAUSE_FACTOR;
-+module_param(rtw_tsf_update_pause_factor, int, 0644);
-+MODULE_PARM_DESC(rtw_tsf_update_pause_factor, "num of bcn intervals to stay TSF update pause status");
-+
-+int rtw_tsf_update_restore_factor = CONFIG_TSF_UPDATE_RESTORE_FACTOR;
-+module_param(rtw_tsf_update_restore_factor, int, 0644);
-+MODULE_PARM_DESC(rtw_tsf_update_restore_factor, "num of bcn intervals to stay TSF update restore status");
-+
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+char *rtw_phy_file_path = REALTEK_CONFIG_PATH;
-+module_param(rtw_phy_file_path, charp, 0644);
-+MODULE_PARM_DESC(rtw_phy_file_path, "The path of phy parameter");
-+/* PHY FILE Bit Map
-+* BIT0 - MAC,				0: non-support, 1: support
-+* BIT1 - BB,					0: non-support, 1: support
-+* BIT2 - BB_PG,				0: non-support, 1: support
-+* BIT3 - BB_MP,				0: non-support, 1: support
-+* BIT4 - RF,					0: non-support, 1: support
-+* BIT5 - RF_TXPWR_TRACK,	0: non-support, 1: support
-+* BIT6 - RF_TXPWR_LMT,		0: non-support, 1: support */
-+int rtw_load_phy_file = (BIT2 | BIT6);
-+module_param(rtw_load_phy_file, int, 0644);
-+MODULE_PARM_DESC(rtw_load_phy_file, "PHY File Bit Map");
-+int rtw_decrypt_phy_file = 0;
-+module_param(rtw_decrypt_phy_file, int, 0644);
-+MODULE_PARM_DESC(rtw_decrypt_phy_file, "Enable Decrypt PHY File");
-+#endif
-+
-+uint rtw_recvbuf_nr = NR_RECVBUFF;
-+module_param(rtw_recvbuf_nr, int, 0644);
-+MODULE_PARM_DESC(rtw_recvbuf_nr, "Preallocated number of struct recv_buf");
-+
-+#ifdef CONFIG_SUPPORT_TRX_SHARED
-+#ifdef DFT_TRX_SHARE_MODE
-+int rtw_trx_share_mode = DFT_TRX_SHARE_MODE;
-+#else
-+int rtw_trx_share_mode = 0;
-+#endif
-+module_param(rtw_trx_share_mode, int, 0644);
-+MODULE_PARM_DESC(rtw_trx_share_mode, "TRx FIFO Shared");
-+#endif
-+
-+#ifdef CONFIG_DYNAMIC_SOML
-+uint rtw_dynamic_soml_en = 1;
-+module_param(rtw_dynamic_soml_en, int, 0644);
-+MODULE_PARM_DESC(rtw_dynamic_soml_en, "0: disable, 1: enable with default param, 2: enable with specified param.");
-+
-+uint rtw_dynamic_soml_train_num = 0;
-+module_param(rtw_dynamic_soml_train_num, int, 0644);
-+MODULE_PARM_DESC(rtw_dynamic_soml_train_num, "SOML training number");
-+
-+uint rtw_dynamic_soml_interval = 0;
-+module_param(rtw_dynamic_soml_interval, int, 0644);
-+MODULE_PARM_DESC(rtw_dynamic_soml_interval, "SOML training interval");
-+
-+uint rtw_dynamic_soml_period = 0;
-+module_param(rtw_dynamic_soml_period, int, 0644);
-+MODULE_PARM_DESC(rtw_dynamic_soml_period, "SOML training period");
-+
-+uint rtw_dynamic_soml_delay = 0;
-+module_param(rtw_dynamic_soml_delay, int, 0644);
-+MODULE_PARM_DESC(rtw_dynamic_soml_delay, "SOML training delay");
-+#endif
-+
-+uint rtw_phydm_ability = 0xffffffff;
-+module_param(rtw_phydm_ability, uint, 0644);
-+
-+uint rtw_halrf_ability = 0xffffffff;
-+module_param(rtw_halrf_ability, uint, 0644);
-+
-+#ifdef CONFIG_RTW_MESH
-+uint rtw_peer_alive_based_preq = 1;
-+module_param(rtw_peer_alive_based_preq, uint, 0644);
-+MODULE_PARM_DESC(rtw_peer_alive_based_preq,
-+	"On demand PREQ will reference peer alive status. 0: Off, 1: On");
-+#endif
-+
-+int _netdev_open(struct net_device *pnetdev);
-+int netdev_open(struct net_device *pnetdev);
-+static int netdev_close(struct net_device *pnetdev);
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+extern int rtw_sdio_set_power(int on);
-+#endif /* CONFIG_PLATFORM_INTEL_BYT */
-+
-+#ifdef CONFIG_MCC_MODE
-+/* enable MCC mode or not */
-+int rtw_en_mcc = 1;
-+/* can referece following value before insmod driver */
-+int rtw_mcc_ap_bw20_target_tx_tp = MCC_AP_BW20_TARGET_TX_TP;
-+int rtw_mcc_ap_bw40_target_tx_tp = MCC_AP_BW40_TARGET_TX_TP;
-+int rtw_mcc_ap_bw80_target_tx_tp = MCC_AP_BW80_TARGET_TX_TP;
-+int rtw_mcc_sta_bw20_target_tx_tp = MCC_STA_BW20_TARGET_TX_TP;
-+int rtw_mcc_sta_bw40_target_tx_tp = MCC_STA_BW40_TARGET_TX_TP;
-+int rtw_mcc_sta_bw80_target_tx_tp = MCC_STA_BW80_TARGET_TX_TP;
-+int rtw_mcc_single_tx_cri = MCC_SINGLE_TX_CRITERIA;
-+int rtw_mcc_policy_table_idx = 0;
-+int rtw_mcc_duration = 0;
-+int rtw_mcc_enable_runtime_duration = 1;
-+#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+int rtw_mcc_phydm_offload = 1;
-+#else
-+int rtw_mcc_phydm_offload = 0;
-+#endif
-+module_param(rtw_en_mcc, int, 0644);
-+module_param(rtw_mcc_single_tx_cri, int, 0644);
-+module_param(rtw_mcc_ap_bw20_target_tx_tp, int, 0644);
-+module_param(rtw_mcc_ap_bw40_target_tx_tp, int, 0644);
-+module_param(rtw_mcc_ap_bw80_target_tx_tp, int, 0644);
-+module_param(rtw_mcc_sta_bw20_target_tx_tp, int, 0644);
-+module_param(rtw_mcc_sta_bw40_target_tx_tp, int, 0644);
-+module_param(rtw_mcc_sta_bw80_target_tx_tp, int, 0644);
-+module_param(rtw_mcc_policy_table_idx, int, 0644);
-+module_param(rtw_mcc_duration, int, 0644);
-+module_param(rtw_mcc_phydm_offload, int, 0644);
-+#endif /*CONFIG_MCC_MODE */
-+
-+#ifdef CONFIG_RTW_NAPI
-+/*following setting should define NAPI in Makefile
-+enable napi only = 1, disable napi = 0*/
-+int rtw_en_napi = 1;
-+module_param(rtw_en_napi, int, 0644);
-+#ifdef CONFIG_RTW_NAPI_DYNAMIC
-+int rtw_napi_threshold = 100; /* unit: Mbps */
-+module_param(rtw_napi_threshold, int, 0644);
-+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
-+#ifdef CONFIG_RTW_GRO
-+/*following setting should define GRO in Makefile
-+enable gro = 1, disable gro = 0*/
-+int rtw_en_gro = 1;
-+module_param(rtw_en_gro, int, 0644);
-+#endif /* CONFIG_RTW_GRO */
-+#endif /* CONFIG_RTW_NAPI */
-+
-+#ifdef RTW_IQK_FW_OFFLOAD
-+int rtw_iqk_fw_offload = 1;
-+#else
-+int rtw_iqk_fw_offload;
-+#endif /* RTW_IQK_FW_OFFLOAD */
-+module_param(rtw_iqk_fw_offload, int, 0644);
-+
-+#ifdef RTW_CHANNEL_SWITCH_OFFLOAD
-+int rtw_ch_switch_offload = 0;
-+#else
-+int rtw_ch_switch_offload;
-+#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
-+module_param(rtw_ch_switch_offload, int, 0644);
-+
-+#ifdef CONFIG_TDLS
-+int rtw_en_tdls = 1;
-+module_param(rtw_en_tdls, int, 0644);
-+#endif
-+
-+#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
-+int rtw_fw_param_init = 1;
-+module_param(rtw_fw_param_init, int, 0644);
-+#endif
-+
-+#ifdef CONFIG_TDMADIG
-+int rtw_tdmadig_en = 1;
-+/*
-+1:MODE_PERFORMANCE
-+2:MODE_COVERAGE
-+*/
-+int rtw_tdmadig_mode = 1;
-+int rtw_dynamic_tdmadig = 0;
-+module_param(rtw_tdmadig_en, int, 0644);
-+module_param(rtw_tdmadig_mode, int, 0644);
-+module_param(rtw_dynamic_tdmadig, int, 0644);
-+#endif/*CONFIG_TDMADIG*/
-+
-+/*dynamic RRSR default enable*/
-+int rtw_en_dyn_rrsr = 1;
-+int rtw_rrsr_value = 0xFFFFFFFF;
-+module_param(rtw_en_dyn_rrsr, int, 0644);
-+module_param(rtw_rrsr_value, int, 0644);
-+
-+#ifdef CONFIG_WOWLAN
-+/*
-+ * 0: disable, 1: enable
-+ */
-+uint rtw_wow_enable = 1;
-+module_param(rtw_wow_enable, uint, 0644);
-+/*
-+ * bit[0]: magic packet wake up
-+ * bit[1]: unucast packet(HW/FW unuicast)
-+ * bit[2]: deauth wake up
-+ */
-+uint rtw_wakeup_event = RTW_WAKEUP_EVENT;
-+module_param(rtw_wakeup_event, uint, 0644);
-+/*
-+ * 0: common WOWLAN
-+ * bit[0]: disable BB RF
-+ * bit[1]: For wireless remote controller with or without connection
-+ */
-+uint rtw_suspend_type = RTW_SUSPEND_TYPE;
-+module_param(rtw_suspend_type, uint, 0644);
-+#endif
-+
-+#ifdef RTW_BUSY_DENY_SCAN
-+uint rtw_scan_interval_thr = BUSY_TRAFFIC_SCAN_DENY_PERIOD;
-+module_param(rtw_scan_interval_thr, uint, 0644);
-+MODULE_PARM_DESC(rtw_scan_interval_thr, "Threshold used to judge if scan " \
-+		 "request comes from scan UI, unit is ms.");
-+#endif /* RTW_BUSY_DENY_SCAN */
-+
-+#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY
-+uint rtw_8822c_xcap_overwrite = 1;
-+module_param(rtw_8822c_xcap_overwrite, uint, 0644);
-+#endif
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+static int rtw_unassoc_sta_mode_of_stype[UNASOC_STA_SRC_NUM] = CONFIG_RTW_UNASOC_STA_MODE_OF_STYPE;
-+static int rtw_unassoc_sta_mode_of_stype_num = 0;
-+module_param_array(rtw_unassoc_sta_mode_of_stype, int, &rtw_unassoc_sta_mode_of_stype_num, 0644);
-+
-+uint rtw_max_unassoc_sta_cnt = 0;
-+module_param(rtw_max_unassoc_sta_cnt, uint, 0644);
-+#endif
-+
-+#if CONFIG_TX_AC_LIFETIME
-+static void rtw_regsty_load_tx_ac_lifetime(struct registry_priv *regsty)
-+{
-+	int i, j;
-+	struct tx_aclt_conf_t *conf;
-+	uint *parm;
-+
-+	regsty->tx_aclt_flags = (u8)rtw_tx_aclt_flags;
-+
-+	for (i = 0; i < TX_ACLT_CONF_NUM; i++) {
-+		conf = &regsty->tx_aclt_confs[i];
-+		if (i == TX_ACLT_CONF_DEFAULT)
-+			parm = rtw_tx_aclt_conf_default;
-+		#ifdef CONFIG_AP_MODE
-+		#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+		else if (i == TX_ACLT_CONF_AP_M2U)
-+			parm = rtw_tx_aclt_conf_ap_m2u;
-+		#endif
-+		#endif /* CONFIG_AP_MODE */
-+		#ifdef CONFIG_RTW_MESH
-+		else if (i == TX_ACLT_CONF_MESH)
-+			parm = rtw_tx_aclt_conf_mesh;
-+		#endif
-+		else
-+			parm = NULL;
-+
-+		if (parm) {
-+			conf->en = parm[0] & 0xF;
-+			conf->vo_vi = parm[1];
-+			conf->be_bk = parm[2];
-+		}	
-+	}
-+}
-+#endif
-+
-+void rtw_regsty_load_target_tx_power(struct registry_priv *regsty)
-+{
-+	int path, rs;
-+	int *target_tx_pwr;
-+
-+	for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
-+		if (path == RF_PATH_A)
-+			target_tx_pwr = rtw_target_tx_pwr_2g_a;
-+		else if (path == RF_PATH_B)
-+			target_tx_pwr = rtw_target_tx_pwr_2g_b;
-+		else if (path == RF_PATH_C)
-+			target_tx_pwr = rtw_target_tx_pwr_2g_c;
-+		else if (path == RF_PATH_D)
-+			target_tx_pwr = rtw_target_tx_pwr_2g_d;
-+
-+		for (rs = CCK; rs < RATE_SECTION_NUM; rs++)
-+			regsty->target_tx_pwr_2g[path][rs] = target_tx_pwr[rs];
-+	}
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
-+		if (path == RF_PATH_A)
-+			target_tx_pwr = rtw_target_tx_pwr_5g_a;
-+		else if (path == RF_PATH_B)
-+			target_tx_pwr = rtw_target_tx_pwr_5g_b;
-+		else if (path == RF_PATH_C)
-+			target_tx_pwr = rtw_target_tx_pwr_5g_c;
-+		else if (path == RF_PATH_D)
-+			target_tx_pwr = rtw_target_tx_pwr_5g_d;
-+
-+		for (rs = OFDM; rs < RATE_SECTION_NUM; rs++)
-+			regsty->target_tx_pwr_5g[path][rs - 1] = target_tx_pwr[rs - 1];
-+	}
-+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-+}
-+
-+inline void rtw_regsty_load_excl_chs(struct registry_priv *regsty)
-+{
-+	int i;
-+	int ch_num = 0;
-+
-+	for (i = 0; i < MAX_CHANNEL_NUM; i++)
-+		if (((u8)rtw_excl_chs[i]) != 0)
-+			regsty->excl_chs[ch_num++] = (u8)rtw_excl_chs[i];
-+
-+	if (ch_num < MAX_CHANNEL_NUM)
-+		regsty->excl_chs[ch_num] = 0;
-+}
-+
-+#ifdef CONFIG_80211N_HT
-+inline void rtw_regsty_init_rx_ampdu_sz_limit(struct registry_priv *regsty)
-+{
-+	int i, j;
-+	uint *sz_limit;
-+
-+	for (i = 0; i < 4; i++) {
-+		if (i == 0)
-+			sz_limit = rtw_rx_ampdu_sz_limit_1ss;
-+		else if (i == 1)
-+			sz_limit = rtw_rx_ampdu_sz_limit_2ss;
-+		else if (i == 2)
-+			sz_limit = rtw_rx_ampdu_sz_limit_3ss;
-+		else if (i == 3)
-+			sz_limit = rtw_rx_ampdu_sz_limit_4ss;
-+
-+		for (j = 0; j < 4; j++)
-+			regsty->rx_ampdu_sz_limit_by_nss_bw[i][j] = sz_limit[j];
-+	}
-+}
-+#endif /* CONFIG_80211N_HT */
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+inline void rtw_regsty_init_unassoc_sta_param(struct registry_priv *regsty)
-+{
-+	int i;
-+
-+	for (i = 0; i < UNASOC_STA_SRC_NUM; i++)
-+		regsty->unassoc_sta_mode_of_stype[i] = rtw_unassoc_sta_mode_of_stype[i];
-+
-+	regsty->max_unassoc_sta_cnt = (u16) rtw_max_unassoc_sta_cnt;
-+}
-+#endif
-+
-+uint loadparam(_adapter *padapter)
-+{
-+	uint status = _SUCCESS;
-+	struct registry_priv  *registry_par = &padapter->registrypriv;
-+
-+
-+#ifdef CONFIG_RTW_DEBUG
-+	if (rtw_drv_log_level >= _DRV_MAX_)
-+		rtw_drv_log_level = _DRV_DEBUG_;
-+#endif
-+
-+	registry_par->chip_version = (u8)rtw_chip_version;
-+	registry_par->rfintfs = (u8)rtw_rfintfs;
-+	registry_par->lbkmode = (u8)rtw_lbkmode;
-+	/* registry_par->hci = (u8)hci; */
-+	registry_par->network_mode  = (u8)rtw_network_mode;
-+
-+	_rtw_memcpy(registry_par->ssid.Ssid, "ANY", 3);
-+	registry_par->ssid.SsidLength = 3;
-+
-+	registry_par->channel = (u8)rtw_channel;
-+#ifdef CONFIG_NARROWBAND_SUPPORTING
-+	if (rtw_nb_config != RTW_NB_CONFIG_NONE)
-+		rtw_wireless_mode &= ~WIRELESS_11B;
-+#endif
-+	registry_par->wireless_mode = (u8)rtw_wireless_mode;
-+
-+	if (IsSupported24G(registry_par->wireless_mode) && (!is_supported_5g(registry_par->wireless_mode))
-+	    && (registry_par->channel > 14))
-+		registry_par->channel = 1;
-+	else if (is_supported_5g(registry_par->wireless_mode) && (!IsSupported24G(registry_par->wireless_mode))
-+		 && (registry_par->channel <= 14))
-+		registry_par->channel = 36;
-+
-+	registry_par->vrtl_carrier_sense = (u8)rtw_vrtl_carrier_sense ;
-+	registry_par->vcs_type = (u8)rtw_vcs_type;
-+	registry_par->rts_thresh = (u16)rtw_rts_thresh;
-+	registry_par->frag_thresh = (u16)rtw_frag_thresh;
-+	registry_par->preamble = (u8)rtw_preamble;
-+	registry_par->scan_mode = (u8)rtw_scan_mode;
-+	registry_par->smart_ps = (u8)rtw_smart_ps;
-+	registry_par->check_fw_ps = (u8)rtw_check_fw_ps;
-+	#ifdef CONFIG_TDMADIG
-+		registry_par->tdmadig_en = (u8)rtw_tdmadig_en;
-+		registry_par->tdmadig_mode = (u8)rtw_tdmadig_mode;
-+		registry_par->tdmadig_dynamic = (u8) rtw_dynamic_tdmadig;
-+		registry_par->power_mgnt = PS_MODE_ACTIVE;
-+		registry_par->ips_mode = IPS_NONE;
-+	#else
-+		registry_par->power_mgnt = (u8)rtw_power_mgnt;
-+		registry_par->ips_mode = (u8)rtw_ips_mode;
-+	#endif/*CONFIG_TDMADIG*/
-+	registry_par->lps_level = (u8)rtw_lps_level;
-+	registry_par->en_dyn_rrsr = (u8)rtw_en_dyn_rrsr;
-+	registry_par->set_rrsr_value = (u32)rtw_rrsr_value;
-+#ifdef CONFIG_LPS_1T1R
-+	registry_par->lps_1t1r = (u8)(rtw_lps_1t1r ? 1 : 0);
-+#endif
-+	registry_par->lps_chk_by_tp = (u8)rtw_lps_chk_by_tp;
-+#ifdef CONFIG_WOWLAN
-+	registry_par->wow_power_mgnt = (u8)rtw_wow_power_mgnt;
-+	registry_par->wow_lps_level = (u8)rtw_wow_lps_level;
-+	#ifdef CONFIG_LPS_1T1R
-+	registry_par->wow_lps_1t1r = (u8)(rtw_wow_lps_1t1r ? 1 : 0);
-+	#endif
-+#endif /* CONFIG_WOWLAN */
-+	registry_par->radio_enable = (u8)rtw_radio_enable;
-+	registry_par->long_retry_lmt = (u8)rtw_long_retry_lmt;
-+	registry_par->short_retry_lmt = (u8)rtw_short_retry_lmt;
-+	registry_par->busy_thresh = (u16)rtw_busy_thresh;
-+	registry_par->max_bss_cnt = (u16)rtw_max_bss_cnt;
-+	/* registry_par->qos_enable = (u8)rtw_qos_enable; */
-+	registry_par->ack_policy = (u8)rtw_ack_policy;
-+	registry_par->mp_mode = (u8)rtw_mp_mode;
-+#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
-+	registry_par->mp_customer_str = (u8)rtw_mp_customer_str;
-+#endif
-+	registry_par->software_encrypt = (u8)rtw_software_encrypt;
-+	registry_par->software_decrypt = (u8)rtw_software_decrypt;
-+
-+	registry_par->acm_method = (u8)rtw_acm_method;
-+	registry_par->usb_rxagg_mode = (u8)rtw_usb_rxagg_mode;
-+	registry_par->dynamic_agg_enable = (u8)rtw_dynamic_agg_enable;
-+
-+	/* WMM */
-+	registry_par->wmm_enable = (u8)rtw_wmm_enable;
-+
-+#ifdef CONFIG_WMMPS_STA
-+	/* UAPSD */
-+	registry_par->uapsd_max_sp_len= (u8)rtw_uapsd_max_sp;
-+	registry_par->uapsd_ac_enable = (u8)rtw_uapsd_ac_enable;
-+	registry_par->wmm_smart_ps = (u8)rtw_wmm_smart_ps;
-+#endif /* CONFIG_WMMPS_STA */
-+
-+	registry_par->RegPwrTrimEnable = (u8)rtw_pwrtrim_enable;
-+
-+#if CONFIG_TX_AC_LIFETIME
-+	rtw_regsty_load_tx_ac_lifetime(registry_par);
-+#endif
-+
-+	registry_par->tx_bw_mode = (u8)rtw_tx_bw_mode;
-+
-+#ifdef CONFIG_80211N_HT
-+	registry_par->ht_enable = (u8)rtw_ht_enable;
-+	if (registry_par->ht_enable && is_supported_ht(registry_par->wireless_mode)) {
-+#ifdef CONFIG_NARROWBAND_SUPPORTING
-+	if (rtw_nb_config != RTW_NB_CONFIG_NONE)
-+		rtw_bw_mode = 0;
-+#endif
-+		registry_par->bw_mode = (u8)rtw_bw_mode;
-+		registry_par->ampdu_enable = (u8)rtw_ampdu_enable;
-+		registry_par->rx_stbc = (u8)rtw_rx_stbc;
-+		registry_par->rx_ampdu_amsdu = (u8)rtw_rx_ampdu_amsdu;
-+		registry_par->tx_ampdu_amsdu = (u8)rtw_tx_ampdu_amsdu;
-+		registry_par->tx_quick_addba_req = (u8)rtw_quick_addba_req;
-+		registry_par->short_gi = (u8)rtw_short_gi;
-+		registry_par->ldpc_cap = (u8)rtw_ldpc_cap;
-+#if defined(CONFIG_CUSTOMER01_SMART_ANTENNA)
-+		rtw_stbc_cap = 0x0;
-+#endif
-+#ifdef CONFIG_RTW_TX_NPATH_EN
-+		registry_par->tx_npath = (u8)rtw_tx_npath_enable;
-+#endif
-+#ifdef CONFIG_RTW_PATH_DIV
-+		registry_par->path_div = (u8)rtw_path_div_enable;
-+#endif
-+		registry_par->stbc_cap = (u8)rtw_stbc_cap;
-+		registry_par->beamform_cap = (u8)rtw_beamform_cap;
-+		registry_par->beamformer_rf_num = (u8)rtw_bfer_rf_number;
-+		registry_par->beamformee_rf_num = (u8)rtw_bfee_rf_number;
-+		rtw_regsty_init_rx_ampdu_sz_limit(registry_par);
-+	}
-+#endif
-+#ifdef DBG_LA_MODE
-+	registry_par->la_mode_en = (u8)rtw_la_mode_en;
-+#endif
-+#ifdef CONFIG_NARROWBAND_SUPPORTING
-+	registry_par->rtw_nb_config = (u8)rtw_nb_config;
-+#endif
-+
-+#ifdef CONFIG_80211AC_VHT
-+	registry_par->vht_enable = (u8)rtw_vht_enable;
-+	registry_par->vht_24g_enable = (u8)rtw_vht_24g_enable;
-+	registry_par->ampdu_factor = (u8)rtw_ampdu_factor;
-+	registry_par->vht_rx_mcs_map[0] = (u8)(rtw_vht_rx_mcs_map & 0xFF);
-+	registry_par->vht_rx_mcs_map[1] = (u8)((rtw_vht_rx_mcs_map & 0xFF00) >> 8);
-+#endif
-+
-+#ifdef CONFIG_TX_EARLY_MODE
-+	registry_par->early_mode = (u8)rtw_early_mode;
-+#endif
-+	registry_par->trx_path_bmp = (u8)rtw_trx_path_bmp;
-+	registry_par->tx_path_lmt = (u8)rtw_tx_path_lmt;
-+	registry_par->rx_path_lmt = (u8)rtw_rx_path_lmt;
-+	registry_par->tx_nss = (u8)rtw_tx_nss;
-+	registry_par->rx_nss = (u8)rtw_rx_nss;
-+	registry_par->low_power = (u8)rtw_low_power;
-+
-+	registry_par->check_hw_status = (u8)rtw_check_hw_status;
-+
-+	registry_par->wifi_spec = (u8)rtw_wifi_spec;
-+
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+	if (regd_src_is_valid(rtw_regd_src))
-+		registry_par->regd_src = (u8)rtw_regd_src;
-+	else {
-+		RTW_WARN("%s invalid rtw_regd_src(%u), use REGD_SRC_RTK_PRIV instead\n", __func__, rtw_regd_src);
-+		registry_par->regd_src = REGD_SRC_RTK_PRIV;
-+	}
-+#endif
-+
-+	if (strlen(rtw_country_code) != 2
-+		|| is_alpha(rtw_country_code[0]) == _FALSE
-+		|| is_alpha(rtw_country_code[1]) == _FALSE
-+	) {
-+		if (rtw_country_code != rtw_country_unspecified)
-+			RTW_ERR("%s discard rtw_country_code not in alpha2\n", __func__);
-+		_rtw_memset(registry_par->alpha2, 0xFF, 2);
-+	} else
-+		_rtw_memcpy(registry_par->alpha2, rtw_country_code, 2);
-+
-+	registry_par->channel_plan = (u8)rtw_channel_plan;
-+	rtw_regsty_load_excl_chs(registry_par);
-+
-+	registry_par->full_ch_in_p2p_handshake = (u8)rtw_full_ch_in_p2p_handshake;
-+#ifdef CONFIG_BT_COEXIST
-+	registry_par->btcoex = (u8)rtw_btcoex_enable;
-+	registry_par->bt_iso = (u8)rtw_bt_iso;
-+	registry_par->bt_sco = (u8)rtw_bt_sco;
-+	registry_par->bt_ampdu = (u8)rtw_bt_ampdu;
-+	registry_par->ant_num = (u8)rtw_ant_num;
-+	registry_par->single_ant_path = (u8) rtw_single_ant_path;
-+#endif
-+
-+	registry_par->bAcceptAddbaReq = (u8)rtw_AcceptAddbaReq;
-+
-+	registry_par->antdiv_cfg = (u8)rtw_antdiv_cfg;
-+	registry_par->antdiv_type = (u8)rtw_antdiv_type;
-+
-+	registry_par->drv_ant_band_switch = (u8) rtw_drv_ant_band_switch;
-+
-+	registry_par->switch_usb_mode = (u8)rtw_switch_usb_mode;
-+#ifdef SUPPORT_HW_RFOFF_DETECTED
-+	registry_par->hwpdn_mode = (u8)rtw_hwpdn_mode;/* 0:disable,1:enable,2:by EFUSE config */
-+	registry_par->hwpwrp_detect = (u8)rtw_hwpwrp_detect;/* 0:disable,1:enable */
-+#endif
-+
-+	registry_par->hw_wps_pbc = (u8)rtw_hw_wps_pbc;
-+
-+#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
-+	snprintf(registry_par->adaptor_info_caching_file_path, PATH_LENGTH_MAX, "%s", rtw_adaptor_info_caching_file_path);
-+	registry_par->adaptor_info_caching_file_path[PATH_LENGTH_MAX - 1] = 0;
-+#endif
-+
-+#ifdef CONFIG_LAYER2_ROAMING
-+	registry_par->max_roaming_times = (u8)rtw_max_roaming_times;
-+#endif
-+
-+#ifdef CONFIG_IOL
-+	registry_par->fw_iol = rtw_fw_iol;
-+#endif
-+
-+#ifdef CONFIG_80211D
-+	registry_par->enable80211d = (u8)rtw_80211d;
-+#endif
-+
-+	snprintf(registry_par->ifname, 16, "%s", ifname);
-+	snprintf(registry_par->if2name, 16, "%s", if2name);
-+
-+	registry_par->notch_filter = (u8)rtw_notch_filter;
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	registry_par->virtual_iface_num = (u8)rtw_virtual_iface_num;
-+#ifdef CONFIG_P2P
-+	registry_par->sel_p2p_iface = (u8)rtw_sel_p2p_iface;
-+	RTW_INFO("%s, Select P2P interface: iface_id:%d\n", __func__, registry_par->sel_p2p_iface);
-+#endif
-+#endif
-+	registry_par->pll_ref_clk_sel = (u8)rtw_pll_ref_clk_sel;
-+
-+#if CONFIG_TXPWR_LIMIT
-+	registry_par->RegEnableTxPowerLimit = (u8)rtw_tx_pwr_lmt_enable;
-+#endif
-+	registry_par->RegEnableTxPowerByRate = (u8)rtw_tx_pwr_by_rate;
-+
-+	rtw_regsty_load_target_tx_power(registry_par);
-+
-+	registry_par->antenna_gain = (s16)rtw_antenna_gain;
-+
-+	registry_par->tsf_update_pause_factor = (u8)rtw_tsf_update_pause_factor;
-+	registry_par->tsf_update_restore_factor = (u8)rtw_tsf_update_restore_factor;
-+
-+	registry_par->TxBBSwing_2G = (s8)rtw_TxBBSwing_2G;
-+	registry_par->TxBBSwing_5G = (s8)rtw_TxBBSwing_5G;
-+	registry_par->bEn_RFE = 1;
-+	registry_par->RFE_Type = (u8)rtw_RFE_type;
-+	registry_par->PowerTracking_Type = (u8)rtw_powertracking_type;
-+	registry_par->AmplifierType_2G = (u8)rtw_amplifier_type_2g;
-+	registry_par->AmplifierType_5G = (u8)rtw_amplifier_type_5g;
-+	registry_par->GLNA_Type = (u8)rtw_GLNA_type;
-+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+	registry_par->load_phy_file = (u8)rtw_load_phy_file;
-+	registry_par->RegDecryptCustomFile = (u8)rtw_decrypt_phy_file;
-+#endif
-+	registry_par->qos_opt_enable = (u8)rtw_qos_opt_enable;
-+
-+	registry_par->hiq_filter = (u8)rtw_hiq_filter;
-+
-+	registry_par->adaptivity_en = (u8)rtw_adaptivity_en;
-+	registry_par->adaptivity_mode = (u8)rtw_adaptivity_mode;
-+	registry_par->adaptivity_th_l2h_ini = (s8)rtw_adaptivity_th_l2h_ini;
-+	registry_par->adaptivity_th_edcca_hl_diff = (s8)rtw_adaptivity_th_edcca_hl_diff;
-+
-+#ifdef CONFIG_DYNAMIC_SOML
-+	registry_par->dyn_soml_en = (u8)rtw_dynamic_soml_en;
-+	registry_par->dyn_soml_train_num = (u8)rtw_dynamic_soml_train_num;
-+	registry_par->dyn_soml_interval = (u8)rtw_dynamic_soml_interval;
-+	registry_par->dyn_soml_period = (u8)rtw_dynamic_soml_period;
-+	registry_par->dyn_soml_delay = (u8)rtw_dynamic_soml_delay;
-+#endif
-+
-+	registry_par->boffefusemask = (u8)rtw_OffEfuseMask;
-+	registry_par->bFileMaskEfuse = (u8)rtw_FileMaskEfuse;
-+	registry_par->bBTFileMaskEfuse = (u8)rtw_FileMaskEfuse;
-+
-+#ifdef CONFIG_RTW_ACS
-+	registry_par->acs_mode = (u8)rtw_acs;
-+	registry_par->acs_auto_scan = (u8)rtw_acs_auto_scan;
-+#endif
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+	registry_par->nm_mode = (u8)rtw_nm;
-+#endif
-+	registry_par->reg_rxgain_offset_2g = (u32) rtw_rxgain_offset_2g;
-+	registry_par->reg_rxgain_offset_5gl = (u32) rtw_rxgain_offset_5gl;
-+	registry_par->reg_rxgain_offset_5gm = (u32) rtw_rxgain_offset_5gm;
-+	registry_par->reg_rxgain_offset_5gh = (u32) rtw_rxgain_offset_5gh;
-+
-+#ifdef CONFIG_DFS_MASTER
-+	registry_par->dfs_region_domain = (u8)rtw_dfs_region_domain;
-+	#ifdef CONFIG_REGD_SRC_FROM_OS
-+	if (rtw_regd_src == REGD_SRC_OS && registry_par->dfs_region_domain != RTW_DFS_REGD_NONE) {
-+		RTW_WARN("%s force disable radar detection capability when regd_src is OS\n", __func__);
-+		registry_par->dfs_region_domain = RTW_DFS_REGD_NONE;
-+	}
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_MCC_MODE
-+	registry_par->en_mcc = (u8)rtw_en_mcc;
-+	registry_par->rtw_mcc_ap_bw20_target_tx_tp = (u32)rtw_mcc_ap_bw20_target_tx_tp;
-+	registry_par->rtw_mcc_ap_bw40_target_tx_tp = (u32)rtw_mcc_ap_bw40_target_tx_tp;
-+	registry_par->rtw_mcc_ap_bw80_target_tx_tp = (u32)rtw_mcc_ap_bw80_target_tx_tp;
-+	registry_par->rtw_mcc_sta_bw20_target_tx_tp = (u32)rtw_mcc_sta_bw20_target_tx_tp;
-+	registry_par->rtw_mcc_sta_bw40_target_tx_tp = (u32)rtw_mcc_sta_bw40_target_tx_tp;
-+	registry_par->rtw_mcc_sta_bw80_target_tx_tp = (u32)rtw_mcc_sta_bw80_target_tx_tp;
-+	registry_par->rtw_mcc_single_tx_cri = (u32)rtw_mcc_single_tx_cri;
-+	registry_par->rtw_mcc_policy_table_idx = rtw_mcc_policy_table_idx;
-+	registry_par->rtw_mcc_duration = (u8)rtw_mcc_duration;
-+	registry_par->rtw_mcc_enable_runtime_duration = rtw_mcc_enable_runtime_duration;
-+	registry_par->rtw_mcc_phydm_offload = rtw_mcc_phydm_offload;
-+#endif /*CONFIG_MCC_MODE */
-+
-+#ifdef CONFIG_WOWLAN
-+	registry_par->wowlan_enable = rtw_wow_enable;
-+	registry_par->wakeup_event = rtw_wakeup_event;
-+	registry_par->suspend_type = rtw_suspend_type;
-+#endif
-+
-+#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_PREALLOC_RX_SKB_BUFFER)
-+	if (rtw_recvbuf_nr != NR_RECVBUFF) {
-+		RTW_WARN("CONFIG_PREALLOC_RX_SKB_BUFFER && CONFIG_SDIO_HCI, force recvbuf_nr to NR_RECVBUFF(%d)\n", NR_RECVBUFF);
-+		rtw_recvbuf_nr = NR_RECVBUFF;
-+	}
-+#endif
-+	registry_par->recvbuf_nr = rtw_recvbuf_nr;
-+
-+#ifdef CONFIG_SUPPORT_TRX_SHARED
-+	registry_par->trx_share_mode = rtw_trx_share_mode;
-+#endif
-+	registry_par->wowlan_sta_mix_mode = rtw_wowlan_sta_mix_mode;
-+
-+#ifdef CONFIG_PCI_HCI
-+	registry_par->pci_aspm_config = rtw_pci_aspm_enable;
-+	registry_par->pci_dynamic_aspm_linkctrl = rtw_pci_dynamic_aspm_linkctrl;
-+#endif
-+
-+#ifdef CONFIG_RTW_NAPI
-+	registry_par->en_napi = (u8)rtw_en_napi;
-+#ifdef CONFIG_RTW_NAPI_DYNAMIC
-+	registry_par->napi_threshold = (u32)rtw_napi_threshold;
-+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
-+#ifdef CONFIG_RTW_GRO
-+	registry_par->en_gro = (u8)rtw_en_gro;
-+	if (!registry_par->en_napi && registry_par->en_gro) {
-+		registry_par->en_gro = 0;
-+		RTW_WARN("Disable GRO because NAPI is not enabled\n");
-+	}
-+#endif /* CONFIG_RTW_GRO */
-+#endif /* CONFIG_RTW_NAPI */
-+
-+	registry_par->iqk_fw_offload = (u8)rtw_iqk_fw_offload;
-+	registry_par->ch_switch_offload = (u8)rtw_ch_switch_offload;
-+
-+#ifdef CONFIG_TDLS
-+	registry_par->en_tdls = rtw_en_tdls;
-+#endif
-+
-+#ifdef CONFIG_ADVANCE_OTA
-+	registry_par->adv_ota = rtw_advnace_ota;
-+#endif
-+#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
-+	registry_par->fw_param_init = rtw_fw_param_init;
-+#endif
-+#ifdef CONFIG_AP_MODE
-+	registry_par->bmc_tx_rate = rtw_bmc_tx_rate;
-+	#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+	registry_par->ap_src_b2u_flags = rtw_ap_src_b2u_flags;
-+	registry_par->ap_fwd_b2u_flags = rtw_ap_fwd_b2u_flags;
-+	#endif
-+#endif /* CONFIG_AP_MODE */
-+
-+#ifdef CONFIG_RTW_MESH
-+	#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+	registry_par->msrc_b2u_flags = rtw_msrc_b2u_flags;
-+	registry_par->mfwd_b2u_flags = rtw_mfwd_b2u_flags;
-+	#endif
-+#endif /* CONFIG_RTW_MESH */
-+
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+	registry_par->fw_tbtt_rpt = rtw_tbtt_rpt;
-+#endif
-+	registry_par->phydm_ability = rtw_phydm_ability;
-+	registry_par->halrf_ability = rtw_halrf_ability;
-+#ifdef CONFIG_RTW_MESH
-+	registry_par->peer_alive_based_preq = rtw_peer_alive_based_preq;
-+#endif
-+
-+#ifdef RTW_BUSY_DENY_SCAN
-+	registry_par->scan_interval_thr = rtw_scan_interval_thr;
-+#endif
-+
-+#ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY
-+	registry_par->rtw_8822c_xcap_overwrite = (u8)rtw_8822c_xcap_overwrite;
-+#endif
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+	rtw_regsty_init_unassoc_sta_param(registry_par);
-+#endif
-+
-+	return status;
-+}
-+
-+/**
-+ * rtw_net_set_mac_address
-+ * This callback function is used for the Media Access Control address
-+ * of each net_device needs to be changed.
-+ *
-+ * Arguments:
-+ * @pnetdev: net_device pointer.
-+ * @addr: new MAC address.
-+ *
-+ * Return:
-+ * ret = 0: Permit to change net_device's MAC address.
-+ * ret = -1 (Default): Operation not permitted.
-+ *
-+ * Auther: Arvin Liu
-+ * Date: 2015/05/29
-+ */
-+static int rtw_net_set_mac_address(struct net_device *pnetdev, void *addr)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct sockaddr *sa = (struct sockaddr *)addr;
-+	int ret = -1;
-+
-+	/* only the net_device is in down state to permit modifying mac addr */
-+	if ((pnetdev->flags & IFF_UP) == _TRUE) {
-+		RTW_INFO(FUNC_ADPT_FMT": The net_device's is not in down state\n"
-+			 , FUNC_ADPT_ARG(padapter));
-+
-+		return ret;
-+	}
-+
-+	/* if the net_device is linked, it's not permit to modify mac addr */
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) ||
-+	    check_fwstate(pmlmepriv, WIFI_ASOC_STATE) ||
-+	    check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) {
-+		RTW_INFO(FUNC_ADPT_FMT": The net_device's is not idle currently\n"
-+			 , FUNC_ADPT_ARG(padapter));
-+
-+		return ret;
-+	}
-+
-+	/* check whether the input mac address is valid to permit modifying mac addr */
-+	if (rtw_check_invalid_mac_address(sa->sa_data, _FALSE) == _TRUE) {
-+		RTW_INFO(FUNC_ADPT_FMT": Invalid Mac Addr for "MAC_FMT"\n"
-+			 , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data));
-+
-+		return ret;
-+	}
-+
-+	_rtw_memcpy(adapter_mac_addr(padapter), sa->sa_data, ETH_ALEN); /* set mac addr to adapter */
-+	_rtw_memcpy(pnetdev->dev_addr, sa->sa_data, ETH_ALEN); /* set mac addr to net_device */
-+
-+#if 0
-+	if (rtw_is_hw_init_completed(padapter)) {
-+		rtw_ps_deny(padapter, PS_DENY_IOCTL);
-+		LeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */
-+
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+		rtw_hal_change_macaddr_mbid(padapter, sa->sa_data);
-+#else
-+		rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, sa->sa_data); /* set mac addr to mac register */
-+#endif
-+
-+		rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
-+	}
-+#else
-+	rtw_ps_deny(padapter, PS_DENY_IOCTL);
-+	LeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+	rtw_hal_change_macaddr_mbid(padapter, sa->sa_data);
-+#else
-+	rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, sa->sa_data); /* set mac addr to mac register */
-+#endif
-+	rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
-+#endif
-+
-+	RTW_INFO(FUNC_ADPT_FMT": Set Mac Addr to "MAC_FMT" Successfully\n"
-+		 , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data));
-+
-+	ret = 0;
-+
-+	return ret;
-+}
-+
-+static struct net_device_stats *rtw_net_get_stats(struct net_device *pnetdev)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
-+	struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
-+	struct recv_priv *precvpriv = &(padapter->recvpriv);
-+
-+	padapter->stats.tx_packets = pxmitpriv->tx_pkts;/* pxmitpriv->tx_pkts++; */
-+	padapter->stats.rx_packets = precvpriv->rx_pkts;/* precvpriv->rx_pkts++; */
-+	padapter->stats.tx_dropped = pxmitpriv->tx_drop;
-+	padapter->stats.rx_dropped = precvpriv->rx_drop;
-+	padapter->stats.tx_bytes = pxmitpriv->tx_bytes;
-+	padapter->stats.rx_bytes = precvpriv->rx_bytes;
-+
-+	return &padapter->stats;
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+/*
-+ * AC to queue mapping
-+ *
-+ * AC_VO -> queue 0
-+ * AC_VI -> queue 1
-+ * AC_BE -> queue 2
-+ * AC_BK -> queue 3
-+ */
-+static const u16 rtw_1d_to_queue[8] = { 2, 3, 3, 2, 1, 1, 0, 0 };
-+
-+/* Given a data frame determine the 802.1p/1d tag to use. */
-+unsigned int rtw_classify8021d(struct sk_buff *skb)
-+{
-+	unsigned int dscp;
-+
-+	/* skb->priority values from 256->263 are magic values to
-+	 * directly indicate a specific 802.1d priority.  This is used
-+	 * to allow 802.1d priority to be passed directly in from VLAN
-+	 * tags, etc.
-+	 */
-+	if (skb->priority >= 256 && skb->priority <= 263)
-+		return skb->priority - 256;
-+
-+	switch (skb->protocol) {
-+	case htons(ETH_P_IP):
-+		dscp = ip_hdr(skb)->tos & 0xfc;
-+		break;
-+	default:
-+		return 0;
-+	}
-+
-+	return dscp >> 5;
-+}
-+
-+
-+static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)
-+	#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)
-+	, struct net_device *sb_dev
-+	#else
-+	, void *accel_priv
-+	#endif
-+	#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)))
-+	, select_queue_fallback_t fallback
-+	#endif
-+#endif
-+)
-+{
-+	_adapter	*padapter = rtw_netdev_priv(dev);
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+	skb->priority = rtw_classify8021d(skb);
-+
-+	if (pmlmepriv->acm_mask != 0)
-+		skb->priority = qos_acm(pmlmepriv->acm_mask, skb->priority);
-+
-+	return rtw_1d_to_queue[skb->priority];
-+}
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) */
-+
-+u16 rtw_os_recv_select_queue(u8 *msdu, enum rtw_rx_llc_hdl llc_hdl)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	u32 priority = 0;
-+
-+	if (llc_hdl == RTW_RX_LLC_REMOVE) {
-+		u16 eth_type = RTW_GET_BE16(msdu + SNAP_SIZE);
-+
-+		if (eth_type == ETH_P_IP) {
-+			struct iphdr *iphdr = (struct iphdr *)(msdu + SNAP_SIZE + 2);
-+			unsigned int dscp = iphdr->tos & 0xfc;
-+
-+			priority = dscp >> 5;
-+		}
-+	}
-+
-+	return rtw_1d_to_queue[priority];
-+#else
-+	return 0;
-+#endif
-+}
-+
-+static u8 is_rtw_ndev(struct net_device *ndev)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+	return ndev->netdev_ops
-+		&& ndev->netdev_ops->ndo_do_ioctl
-+		&& ndev->netdev_ops->ndo_do_ioctl == rtw_ioctl;
-+#else
-+	return ndev->do_ioctl
-+		&& ndev->do_ioctl == rtw_ioctl;
-+#endif
-+}
-+
-+static int rtw_ndev_notifier_call(struct notifier_block *nb, unsigned long state, void *ptr)
-+{
-+	struct net_device *ndev;
-+
-+	if (ptr == NULL)
-+		return NOTIFY_DONE;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0))
-+	ndev = netdev_notifier_info_to_dev(ptr);
-+#else
-+	ndev = ptr;
-+#endif
-+
-+	if (ndev == NULL)
-+		return NOTIFY_DONE;
-+
-+	if (!is_rtw_ndev(ndev))
-+		return NOTIFY_DONE;
-+
-+	RTW_INFO(FUNC_NDEV_FMT" state:%lu\n", FUNC_NDEV_ARG(ndev), state);
-+
-+	switch (state) {
-+	case NETDEV_CHANGENAME:
-+		rtw_adapter_proc_replace(ndev);
-+		break;
-+	#ifdef CONFIG_NEW_NETDEV_HDL
-+	case NETDEV_PRE_UP :
-+		{
-+			_adapter *adapter = rtw_netdev_priv(ndev);
-+
-+			rtw_pwr_wakeup(adapter);
-+		}
-+		break;
-+	#endif
-+	}
-+
-+	return NOTIFY_DONE;
-+}
-+
-+static struct notifier_block rtw_ndev_notifier = {
-+	.notifier_call = rtw_ndev_notifier_call,
-+};
-+
-+int rtw_ndev_notifier_register(void)
-+{
-+	return register_netdevice_notifier(&rtw_ndev_notifier);
-+}
-+
-+void rtw_ndev_notifier_unregister(void)
-+{
-+	unregister_netdevice_notifier(&rtw_ndev_notifier);
-+}
-+
-+int rtw_ndev_init(struct net_device *dev)
-+{
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+
-+	RTW_PRINT(FUNC_ADPT_FMT" if%d mac_addr="MAC_FMT"\n"
-+		, FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1), MAC_ARG(dev->dev_addr));
-+	strncpy(adapter->old_ifname, dev->name, IFNAMSIZ);
-+	adapter->old_ifname[IFNAMSIZ - 1] = '\0';
-+	rtw_adapter_proc_init(dev);
-+
-+	return 0;
-+}
-+
-+void rtw_ndev_uninit(struct net_device *dev)
-+{
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+
-+	RTW_PRINT(FUNC_ADPT_FMT" if%d\n"
-+		  , FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1));
-+	rtw_adapter_proc_deinit(dev);
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+static const struct net_device_ops rtw_netdev_ops = {
-+	.ndo_init = rtw_ndev_init,
-+	.ndo_uninit = rtw_ndev_uninit,
-+	.ndo_open = netdev_open,
-+	.ndo_stop = netdev_close,
-+	.ndo_start_xmit = rtw_xmit_entry,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	.ndo_select_queue	= rtw_select_queue,
-+#endif
-+	.ndo_set_mac_address = rtw_net_set_mac_address,
-+	.ndo_get_stats = rtw_net_get_stats,
-+	.ndo_do_ioctl = rtw_ioctl,
-+};
-+#endif
-+
-+int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname)
-+{
-+#ifdef CONFIG_EASY_REPLACEMENT
-+	_adapter *padapter = rtw_netdev_priv(pnetdev);
-+	struct net_device	*TargetNetdev = NULL;
-+	_adapter			*TargetAdapter = NULL;
-+
-+	if (padapter->bDongle == 1) {
-+		TargetNetdev = rtw_get_same_net_ndev_by_name(pnetdev, "wlan0");
-+		if (TargetNetdev) {
-+			RTW_INFO("Force onboard module driver disappear !!!\n");
-+			TargetAdapter = rtw_netdev_priv(TargetNetdev);
-+			TargetAdapter->DriverState = DRIVER_DISAPPEAR;
-+
-+			padapter->pid[0] = TargetAdapter->pid[0];
-+			padapter->pid[1] = TargetAdapter->pid[1];
-+			padapter->pid[2] = TargetAdapter->pid[2];
-+
-+			dev_put(TargetNetdev);
-+			unregister_netdev(TargetNetdev);
-+
-+			padapter->DriverState = DRIVER_REPLACE_DONGLE;
-+		}
-+	}
-+#endif /* CONFIG_EASY_REPLACEMENT */
-+
-+	if (dev_alloc_name(pnetdev, ifname) < 0)
-+		RTW_ERR("dev_alloc_name, fail!\n");
-+
-+	rtw_netif_carrier_off(pnetdev);
-+	/* rtw_netif_stop_queue(pnetdev); */
-+
-+	return 0;
-+}
-+
-+void rtw_hook_if_ops(struct net_device *ndev)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+	ndev->netdev_ops = &rtw_netdev_ops;
-+#else
-+	ndev->init = rtw_ndev_init;
-+	ndev->uninit = rtw_ndev_uninit;
-+	ndev->open = netdev_open;
-+	ndev->stop = netdev_close;
-+	ndev->hard_start_xmit = rtw_xmit_entry;
-+	ndev->set_mac_address = rtw_net_set_mac_address;
-+	ndev->get_stats = rtw_net_get_stats;
-+	ndev->do_ioctl = rtw_ioctl;
-+#endif
-+}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+static void rtw_hook_vir_if_ops(struct net_device *ndev);
-+#endif
-+struct net_device *rtw_init_netdev(_adapter *old_padapter)
-+{
-+	_adapter *padapter;
-+	struct net_device *pnetdev;
-+
-+	if (old_padapter != NULL) {
-+		rtw_os_ndev_free(old_padapter);
-+		pnetdev = rtw_alloc_etherdev_with_old_priv(sizeof(_adapter), (void *)old_padapter);
-+	} else
-+		pnetdev = rtw_alloc_etherdev(sizeof(_adapter));
-+
-+	if (!pnetdev)
-+		return NULL;
-+
-+	padapter = rtw_netdev_priv(pnetdev);
-+	padapter->pnetdev = pnetdev;
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)
-+	SET_MODULE_OWNER(pnetdev);
-+#endif
-+
-+	rtw_hook_if_ops(pnetdev);
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (!is_primary_adapter(padapter))
-+		rtw_hook_vir_if_ops(pnetdev);
-+#endif /* CONFIG_CONCURRENT_MODE */
-+
-+
-+#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
-+        pnetdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)
-+        pnetdev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
-+#endif
-+#endif
-+
-+#ifdef CONFIG_RTW_NETIF_SG
-+        pnetdev->features |= NETIF_F_SG;
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)
-+        pnetdev->hw_features |= NETIF_F_SG;
-+#endif
-+#endif
-+
-+	if ((pnetdev->features & NETIF_F_SG) && (pnetdev->features & NETIF_F_IP_CSUM)) {
-+		pnetdev->features |= (NETIF_F_TSO | NETIF_F_GSO);
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)
-+		pnetdev->hw_features |= (NETIF_F_TSO | NETIF_F_GSO);
-+#endif
-+	}
-+	/* pnetdev->tx_timeout = NULL; */
-+	pnetdev->watchdog_timeo = HZ * 3; /* 3 second timeout */
-+
-+#ifdef CONFIG_WIRELESS_EXT
-+	pnetdev->wireless_handlers = (struct iw_handler_def *)&rtw_handlers_def;
-+#endif
-+
-+#ifdef WIRELESS_SPY
-+	/* priv->wireless_data.spy_data = &priv->spy_data; */
-+	/* pnetdev->wireless_data = &priv->wireless_data; */
-+#endif
-+
-+	return pnetdev;
-+}
-+
-+int rtw_os_ndev_alloc(_adapter *adapter)
-+{
-+	int ret = _FAIL;
-+	struct net_device *ndev = NULL;
-+
-+	ndev = rtw_init_netdev(adapter);
-+	if (ndev == NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)
-+	SET_NETDEV_DEV(ndev, dvobj_to_dev(adapter_to_dvobj(adapter)));
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	if (adapter_to_dvobj(adapter)->bdma64)
-+		ndev->features |= NETIF_F_HIGHDMA;
-+	ndev->irq = adapter_to_dvobj(adapter)->irq;
-+#endif
-+
-+#if defined(CONFIG_IOCTL_CFG80211)
-+	if (rtw_cfg80211_ndev_res_alloc(adapter) != _SUCCESS) {
-+		rtw_warn_on(1);
-+	} else
-+#endif
-+	ret = _SUCCESS;
-+
-+	if (ret != _SUCCESS && ndev)
-+		rtw_free_netdev(ndev);
-+exit:
-+	return ret;
-+}
-+
-+void rtw_os_ndev_free(_adapter *adapter)
-+{
-+#if defined(CONFIG_IOCTL_CFG80211)
-+	rtw_cfg80211_ndev_res_free(adapter);
-+#endif
-+
-+	if (adapter->pnetdev) {
-+		rtw_free_netdev(adapter->pnetdev);
-+		adapter->pnetdev = NULL;
-+	}
-+}
-+
-+/* For ethtool +++ */
-+#ifdef CONFIG_IOCTL_CFG80211
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 8))
-+static void rtw_ethtool_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
-+{
-+	struct wireless_dev *wdev = NULL;
-+	_adapter *padapter = NULL;
-+	HAL_DATA_TYPE *hal_data = NULL;
-+
-+	wdev = dev->ieee80211_ptr;
-+	if (wdev) {
-+		strlcpy(info->driver, wiphy_dev(wdev->wiphy)->driver->name,
-+			sizeof(info->driver));
-+	} else {
-+		strlcpy(info->driver, "N/A", sizeof(info->driver));
-+	}
-+
-+	strlcpy(info->version, DRIVERVERSION, sizeof(info->version));
-+
-+	padapter = (_adapter *)rtw_netdev_priv(dev);
-+	if (padapter) {
-+		hal_data = GET_HAL_DATA(padapter);
-+	}
-+
-+	if (hal_data) {
-+		scnprintf(info->fw_version, sizeof(info->fw_version), "%d.%d",
-+			  hal_data->firmware_version, hal_data->firmware_sub_version);
-+	} else {
-+		strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
-+	}
-+
-+	strlcpy(info->bus_info, dev_name(wiphy_dev(wdev->wiphy)),
-+		sizeof(info->bus_info));
-+}
-+
-+static const char rtw_ethtool_gstrings_sta_stats[][ETH_GSTRING_LEN] = {
-+	"rx_packets", "rx_bytes", "rx_dropped",
-+	"tx_packets", "tx_bytes", "tx_dropped",
-+};
-+
-+#define RTW_ETHTOOL_STATS_LEN	ARRAY_SIZE(rtw_ethtool_gstrings_sta_stats)
-+
-+static int rtw_ethtool_get_sset_count(struct net_device *dev, int sset)
-+{
-+	int rv = 0;
-+
-+	if (sset == ETH_SS_STATS)
-+		rv += RTW_ETHTOOL_STATS_LEN;
-+
-+	if (rv == 0)
-+		return -EOPNOTSUPP;
-+
-+	return rv;
-+}
-+
-+static void rtw_ethtool_get_strings(struct net_device *dev, u32 sset, u8 *data)
-+{
-+	int sz_sta_stats = 0;
-+
-+	if (sset == ETH_SS_STATS) {
-+		sz_sta_stats = sizeof(rtw_ethtool_gstrings_sta_stats);
-+		memcpy(data, rtw_ethtool_gstrings_sta_stats, sz_sta_stats);
-+	}
-+}
-+
-+static void rtw_ethtool_get_stats(struct net_device *dev,
-+				  struct ethtool_stats *stats,
-+				  u64 *data)
-+{
-+	int i = 0;
-+	_adapter *padapter = NULL;
-+	struct xmit_priv *pxmitpriv = NULL;
-+	struct recv_priv *precvpriv = NULL;
-+
-+	memset(data, 0, sizeof(u64) * RTW_ETHTOOL_STATS_LEN);
-+	
-+	padapter = (_adapter *)rtw_netdev_priv(dev);
-+	if (padapter) {
-+		pxmitpriv = &(padapter->xmitpriv);
-+		precvpriv = &(padapter->recvpriv);
-+
-+		data[i++] = precvpriv->rx_pkts;
-+		data[i++] = precvpriv->rx_bytes;
-+		data[i++] = precvpriv->rx_drop;
-+
-+		data[i++] = pxmitpriv->tx_pkts;
-+		data[i++] = pxmitpriv->tx_bytes;
-+		data[i++] = pxmitpriv->tx_drop;
-+	} else {
-+		data[i++] = 0;
-+		data[i++] = 0;
-+		data[i++] = 0;
-+
-+		data[i++] = 0;
-+		data[i++] = 0;
-+		data[i++] = 0;
-+	}
-+}
-+
-+static const struct ethtool_ops rtw_ethtool_ops = {
-+	.get_drvinfo = rtw_ethtool_get_drvinfo,
-+	.get_link = ethtool_op_get_link,
-+	.get_strings = rtw_ethtool_get_strings,
-+	.get_ethtool_stats = rtw_ethtool_get_stats,
-+	.get_sset_count = rtw_ethtool_get_sset_count,
-+};
-+#endif // LINUX_VERSION_CODE >= 3.7.8 
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+/* For ethtool --- */
-+
-+int rtw_os_ndev_register(_adapter *adapter, const char *name)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	int ret = _SUCCESS;
-+	struct net_device *ndev = adapter->pnetdev;
-+	u8 rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);
-+
-+#ifdef CONFIG_RTW_NAPI
-+	netif_napi_add(ndev, &adapter->napi, rtw_recv_napi_poll, RTL_NAPI_WEIGHT);
-+#endif /* CONFIG_RTW_NAPI */
-+
-+#if defined(CONFIG_IOCTL_CFG80211)
-+	if (rtw_cfg80211_ndev_res_register(adapter) != _SUCCESS) {
-+		rtw_warn_on(1);
-+		ret = _FAIL;
-+		goto exit;
-+	}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 8))
-+	netdev_set_default_ethtool_ops(ndev, &rtw_ethtool_ops);
-+#endif /* LINUX_VERSION_CODE >= 3.7.8 */
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) && defined(CONFIG_PCI_HCI)
-+	ndev->gro_flush_timeout = 100000;
-+#endif
-+	/* alloc netdev name */
-+	rtw_init_netdev_name(ndev, name);
-+
-+	_rtw_memcpy(ndev->dev_addr, adapter_mac_addr(adapter), ETH_ALEN);
-+
-+	/* Tell the network stack we exist */
-+
-+	if (rtnl_lock_needed)
-+		ret = (register_netdev(ndev) == 0) ? _SUCCESS : _FAIL;
-+	else
-+		ret = (register_netdevice(ndev) == 0) ? _SUCCESS : _FAIL;
-+
-+	if (ret == _SUCCESS)
-+		adapter->registered = 1;
-+	else
-+		RTW_INFO(FUNC_NDEV_FMT" if%d Failed!\n", FUNC_NDEV_ARG(ndev), (adapter->iface_id + 1));
-+
-+#if defined(CONFIG_IOCTL_CFG80211)
-+	if (ret != _SUCCESS) {
-+		rtw_cfg80211_ndev_res_unregister(adapter);
-+		#if !defined(RTW_SINGLE_WIPHY)
-+		rtw_wiphy_unregister(adapter_to_wiphy(adapter));
-+		#endif
-+	}
-+#endif
-+
-+#if defined(CONFIG_IOCTL_CFG80211)
-+exit:
-+#endif
-+#ifdef CONFIG_RTW_NAPI
-+	if (ret != _SUCCESS)
-+		netif_napi_del(&adapter->napi);
-+#endif /* CONFIG_RTW_NAPI */
-+
-+	return ret;
-+}
-+
-+void rtw_os_ndev_unregister(_adapter *adapter)
-+{
-+	struct net_device *netdev = NULL;
-+
-+	if (adapter == NULL || adapter->registered == 0)
-+		return;
-+
-+	adapter->ndev_unregistering = 1;
-+
-+	netdev = adapter->pnetdev;
-+
-+#if defined(CONFIG_IOCTL_CFG80211)
-+	rtw_cfg80211_ndev_res_unregister(adapter);
-+#endif
-+
-+	if ((adapter->DriverState != DRIVER_DISAPPEAR) && netdev) {
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+		u8 rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj);
-+
-+		if (rtnl_lock_needed)
-+			unregister_netdev(netdev);
-+		else
-+			unregister_netdevice(netdev);
-+	}
-+
-+#if defined(CONFIG_IOCTL_CFG80211) && !defined(RTW_SINGLE_WIPHY)
-+#ifdef CONFIG_RFKILL_POLL
-+	rtw_cfg80211_deinit_rfkill(adapter_to_wiphy(adapter));
-+#endif
-+	rtw_wiphy_unregister(adapter_to_wiphy(adapter));
-+#endif
-+
-+#ifdef CONFIG_RTW_NAPI
-+	if (adapter->napi_state == NAPI_ENABLE) {
-+		napi_disable(&adapter->napi);
-+		adapter->napi_state = NAPI_DISABLE;
-+	}
-+	netif_napi_del(&adapter->napi);
-+#endif /* CONFIG_RTW_NAPI */
-+
-+	adapter->registered = 0;
-+	adapter->ndev_unregistering = 0;
-+}
-+
-+/**
-+ * rtw_os_ndev_init - Allocate and register OS layer net device and relating structures for @adapter
-+ * @adapter: the adapter on which this function applies
-+ * @name: the requesting net device name
-+ *
-+ * Returns:
-+ * _SUCCESS or _FAIL
-+ */
-+int rtw_os_ndev_init(_adapter *adapter, const char *name)
-+{
-+	int ret = _FAIL;
-+
-+	if (rtw_os_ndev_alloc(adapter) != _SUCCESS)
-+		goto exit;
-+
-+	if (rtw_os_ndev_register(adapter, name) != _SUCCESS)
-+		goto os_ndev_free;
-+
-+	ret = _SUCCESS;
-+
-+os_ndev_free:
-+	if (ret != _SUCCESS)
-+		rtw_os_ndev_free(adapter);
-+exit:
-+	return ret;
-+}
-+
-+/**
-+ * rtw_os_ndev_deinit - Unregister and free OS layer net device and relating structures for @adapter
-+ * @adapter: the adapter on which this function applies
-+ */
-+void rtw_os_ndev_deinit(_adapter *adapter)
-+{
-+	rtw_os_ndev_unregister(adapter);
-+	rtw_os_ndev_free(adapter);
-+}
-+
-+int rtw_os_ndevs_alloc(struct dvobj_priv *dvobj)
-+{
-+	int i, status = _SUCCESS;
-+	_adapter *adapter;
-+
-+#if defined(CONFIG_IOCTL_CFG80211)
-+	if (rtw_cfg80211_dev_res_alloc(dvobj) != _SUCCESS) {
-+		rtw_warn_on(1);
-+		return _FAIL;
-+	}
-+#endif
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+
-+		if (i >= CONFIG_IFACE_NUMBER) {
-+			RTW_ERR("%s %d >= CONFIG_IFACE_NUMBER(%d)\n", __func__, i, CONFIG_IFACE_NUMBER);
-+			rtw_warn_on(1);
-+			continue;
-+		}
-+
-+		adapter = dvobj->padapters[i];
-+		if (adapter && !adapter->pnetdev) {
-+
-+			#ifdef CONFIG_RTW_DYNAMIC_NDEV
-+			if (!is_primary_adapter(adapter))
-+				continue;
-+			#endif
-+
-+			status = rtw_os_ndev_alloc(adapter);
-+			if (status != _SUCCESS) {
-+				rtw_warn_on(1);
-+				break;
-+			}
-+		}
-+	}
-+
-+	if (status != _SUCCESS) {
-+		for (; i >= 0; i--) {
-+			adapter = dvobj->padapters[i];
-+			if (adapter && adapter->pnetdev)
-+				rtw_os_ndev_free(adapter);
-+		}
-+	}
-+
-+#if defined(CONFIG_IOCTL_CFG80211)
-+	if (status != _SUCCESS)
-+		rtw_cfg80211_dev_res_free(dvobj);
-+#endif
-+
-+	return status;
-+}
-+
-+void rtw_os_ndevs_free(struct dvobj_priv *dvobj)
-+{
-+	int i;
-+	_adapter *adapter = NULL;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+
-+		if (i >= CONFIG_IFACE_NUMBER) {
-+			RTW_ERR("%s %d >= CONFIG_IFACE_NUMBER(%d)\n", __func__, i, CONFIG_IFACE_NUMBER);
-+			rtw_warn_on(1);
-+			continue;
-+		}
-+
-+		adapter = dvobj->padapters[i];
-+
-+		if (adapter == NULL)
-+			continue;
-+
-+		rtw_os_ndev_free(adapter);
-+	}
-+
-+#if defined(CONFIG_IOCTL_CFG80211)
-+	rtw_cfg80211_dev_res_free(dvobj);
-+#endif
-+}
-+
-+u32 rtw_start_drv_threads(_adapter *padapter)
-+{
-+	u32 _status = _SUCCESS;
-+
-+	RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(padapter));
-+
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+#if defined(CONFIG_SDIO_HCI)
-+	if (is_primary_adapter(padapter))
-+#endif
-+	{
-+		if (padapter->xmitThread == NULL) {
-+			RTW_INFO(FUNC_ADPT_FMT " start RTW_XMIT_THREAD\n", FUNC_ADPT_ARG(padapter));
-+			padapter->xmitThread = kthread_run(rtw_xmit_thread, padapter, "RTW_XMIT_THREAD");
-+			if (IS_ERR(padapter->xmitThread)) {
-+				padapter->xmitThread = NULL;
-+				_status = _FAIL;
-+			}
-+		}
-+	}
-+#endif /* #ifdef CONFIG_XMIT_THREAD_MODE */
-+
-+#ifdef CONFIG_RECV_THREAD_MODE
-+	if (is_primary_adapter(padapter)) {
-+		if (padapter->recvThread == NULL) {
-+			RTW_INFO(FUNC_ADPT_FMT " start RTW_RECV_THREAD\n", FUNC_ADPT_ARG(padapter));
-+			padapter->recvThread = kthread_run(rtw_recv_thread, padapter, "RTW_RECV_THREAD");
-+			if (IS_ERR(padapter->recvThread)) {
-+				padapter->recvThread = NULL;
-+				_status = _FAIL;
-+			}
-+		}
-+	}
-+#endif
-+
-+	if (is_primary_adapter(padapter)) {
-+		if (padapter->cmdThread == NULL) {
-+			RTW_INFO(FUNC_ADPT_FMT " start RTW_CMD_THREAD\n", FUNC_ADPT_ARG(padapter));
-+			padapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, "RTW_CMD_THREAD");
-+			if (IS_ERR(padapter->cmdThread)) {
-+				padapter->cmdThread = NULL;
-+				_status = _FAIL;
-+			}
-+			else
-+				_rtw_down_sema(&padapter->cmdpriv.start_cmdthread_sema); /* wait for cmd_thread to run */
-+		}
-+	}
-+
-+
-+#ifdef CONFIG_EVENT_THREAD_MODE
-+	if (padapter->evtThread == NULL) {
-+		RTW_INFO(FUNC_ADPT_FMT " start RTW_EVENT_THREAD\n", FUNC_ADPT_ARG(padapter));
-+		padapter->evtThread = kthread_run(event_thread, padapter, "RTW_EVENT_THREAD");
-+		if (IS_ERR(padapter->evtThread)) {
-+			padapter->evtThread = NULL;
-+			_status = _FAIL;
-+		}
-+	}
-+#endif
-+
-+	rtw_hal_start_thread(padapter);
-+	return _status;
-+
-+}
-+
-+void rtw_stop_drv_threads(_adapter *padapter)
-+{
-+	RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(padapter));
-+	if (is_primary_adapter(padapter))
-+		rtw_stop_cmd_thread(padapter);
-+
-+#ifdef CONFIG_EVENT_THREAD_MODE
-+	if (padapter->evtThread) {
-+		_rtw_up_sema(&padapter->evtpriv.evt_notify);
-+		rtw_thread_stop(padapter->evtThread);
-+		padapter->evtThread = NULL;
-+	}
-+#endif
-+
-+#ifdef CONFIG_XMIT_THREAD_MODE
-+	/* Below is to termindate tx_thread... */
-+#if defined(CONFIG_SDIO_HCI)
-+	/* Only wake-up primary adapter */
-+	if (is_primary_adapter(padapter))
-+#endif  /*SDIO_HCI */
-+	{
-+		if (padapter->xmitThread) {
-+			_rtw_up_sema(&padapter->xmitpriv.xmit_sema);
-+			rtw_thread_stop(padapter->xmitThread);
-+			padapter->xmitThread = NULL;
-+		}
-+	}
-+#endif
-+
-+#ifdef CONFIG_RECV_THREAD_MODE
-+	if (is_primary_adapter(padapter) && padapter->recvThread) {
-+		/* Below is to termindate rx_thread... */
-+		_rtw_up_sema(&padapter->recvpriv.recv_sema);
-+		rtw_thread_stop(padapter->recvThread);
-+		padapter->recvThread = NULL;
-+	}
-+#endif
-+
-+	rtw_hal_stop_thread(padapter);
-+}
-+
-+u8 rtw_init_default_value(_adapter *padapter)
-+{
-+	u8 ret  = _SUCCESS;
-+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
-+	struct security_priv *psecuritypriv = &padapter->securitypriv;
-+
-+	/* xmit_priv */
-+	pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense;
-+	pxmitpriv->vcs = pregistrypriv->vcs_type;
-+	pxmitpriv->vcs_type = pregistrypriv->vcs_type;
-+	/* pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; */
-+	pxmitpriv->frag_len = pregistrypriv->frag_thresh;
-+
-+	/* security_priv */
-+	/* rtw_get_encrypt_decrypt_from_registrypriv(padapter); */
-+	psecuritypriv->binstallGrpkey = _FAIL;
-+#ifdef CONFIG_GTK_OL
-+	psecuritypriv->binstallKCK_KEK = _FAIL;
-+#endif /* CONFIG_GTK_OL */
-+	psecuritypriv->sw_encrypt = pregistrypriv->software_encrypt;
-+	psecuritypriv->sw_decrypt = pregistrypriv->software_decrypt;
-+
-+	psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
-+	psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
-+
-+	psecuritypriv->dot11PrivacyKeyIndex = 0;
-+
-+	psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
-+	psecuritypriv->dot118021XGrpKeyid = 1;
-+
-+	psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
-+	psecuritypriv->ndisencryptstatus = Ndis802_11WEPDisabled;
-+	psecuritypriv->dot118021x_bmc_cam_id = INVALID_SEC_MAC_CAM_ID;
-+
-+
-+	/* pwrctrl_priv */
-+
-+
-+	/* registry_priv */
-+	rtw_init_registrypriv_dev_network(padapter);
-+	rtw_update_registrypriv_dev_network(padapter);
-+
-+
-+	/* hal_priv */
-+	rtw_hal_def_value_init(padapter);
-+
-+#ifdef CONFIG_MCC_MODE
-+	/* MCC parameter */
-+	rtw_hal_mcc_parameter_init(padapter);
-+#endif /* CONFIG_MCC_MODE */
-+
-+	/* misc. */
-+	RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
-+	RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
-+	padapter->bLinkInfoDump = 0;
-+	padapter->bNotifyChannelChange = _FALSE;
-+#ifdef CONFIG_P2P
-+	padapter->bShowGetP2PState = 1;
-+#endif
-+
-+	/* for debug purpose */
-+	padapter->fix_rate = 0xFF;
-+	padapter->data_fb = 0;
-+	padapter->fix_bw = 0xFF;
-+	padapter->power_offset = 0;
-+	padapter->rsvd_page_offset = 0;
-+	padapter->rsvd_page_num = 0;
-+#ifdef CONFIG_AP_MODE
-+	padapter->bmc_tx_rate = pregistrypriv->bmc_tx_rate;
-+	#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+	padapter->b2u_flags_ap_src = pregistrypriv->ap_src_b2u_flags;
-+	padapter->b2u_flags_ap_fwd = pregistrypriv->ap_fwd_b2u_flags;
-+	#endif
-+#endif
-+	padapter->driver_tx_bw_mode = pregistrypriv->tx_bw_mode;
-+
-+	padapter->driver_ampdu_spacing = 0xFF;
-+	padapter->driver_rx_ampdu_factor =  0xFF;
-+	padapter->driver_rx_ampdu_spacing = 0xFF;
-+	padapter->fix_rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID;
-+	padapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID;
-+#ifdef CONFIG_TX_AMSDU
-+	padapter->tx_amsdu = 2;
-+	padapter->tx_amsdu_rate = 400;
-+#endif
-+	padapter->driver_tx_max_agg_num = 0xFF;
-+#ifdef DBG_RX_COUNTER_DUMP
-+	padapter->dump_rx_cnt_mode = 0;
-+	padapter->drv_rx_cnt_ok = 0;
-+	padapter->drv_rx_cnt_crcerror = 0;
-+	padapter->drv_rx_cnt_drop = 0;
-+#endif
-+#ifdef CONFIG_RTW_NAPI
-+	padapter->napi_state = NAPI_DISABLE;
-+#endif
-+
-+#ifdef CONFIG_RTW_ACS
-+	if (pregistrypriv->acs_mode)
-+		rtw_acs_start(padapter);
-+	else
-+		rtw_acs_stop(padapter);
-+#endif
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+	if (pregistrypriv->nm_mode)
-+		rtw_nm_enable(padapter);
-+	else
-+		rtw_nm_disable(padapter);
-+#endif
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
-+	ATOMIC_SET(&padapter->tbtx_tx_pause, _FALSE);
-+	ATOMIC_SET(&padapter->tbtx_remove_tx_pause, _FALSE);
-+	padapter->tbtx_capability = _TRUE;
-+#endif
-+
-+	return ret;
-+}
-+#ifdef CONFIG_CLIENT_PORT_CFG
-+extern void rtw_clt_port_init(struct clt_port_t  *cltp);
-+extern void rtw_clt_port_deinit(struct clt_port_t  *cltp);
-+#endif
-+
-+struct dvobj_priv *devobj_init(void)
-+{
-+	struct dvobj_priv *pdvobj = NULL;
-+
-+	pdvobj = (struct dvobj_priv *)rtw_zmalloc(sizeof(*pdvobj));
-+	if (pdvobj == NULL)
-+		return NULL;
-+
-+	_rtw_mutex_init(&pdvobj->hw_init_mutex);
-+	_rtw_mutex_init(&pdvobj->h2c_fwcmd_mutex);
-+	_rtw_mutex_init(&pdvobj->setch_mutex);
-+	_rtw_mutex_init(&pdvobj->setbw_mutex);
-+	_rtw_mutex_init(&pdvobj->rf_read_reg_mutex);
-+	_rtw_mutex_init(&pdvobj->ioctrl_mutex);
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+	_rtw_mutex_init(&pdvobj->sd_indirect_access_mutex);
-+#endif
-+#ifdef CONFIG_SYSON_INDIRECT_ACCESS
-+	_rtw_mutex_init(&pdvobj->syson_indirect_access_mutex);
-+#endif
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+	_rtw_mutex_init(&pdvobj->customer_str_mutex);
-+	_rtw_memset(pdvobj->customer_str, 0xFF, RTW_CUSTOMER_STR_LEN);
-+#endif
-+#ifdef CONFIG_PROTSEL_PORT
-+	_rtw_mutex_init(&pdvobj->protsel_port.mutex);
-+#endif
-+#ifdef CONFIG_PROTSEL_ATIMDTIM
-+	_rtw_mutex_init(&pdvobj->protsel_atimdtim.mutex);
-+#endif
-+#ifdef CONFIG_PROTSEL_MACSLEEP
-+	_rtw_mutex_init(&pdvobj->protsel_macsleep.mutex);
-+#endif
-+
-+	pdvobj->processing_dev_remove = _FALSE;
-+
-+	ATOMIC_SET(&pdvobj->disable_func, 0);
-+
-+	rtw_macid_ctl_init(&pdvobj->macid_ctl);
-+#ifdef CONFIG_CLIENT_PORT_CFG
-+	rtw_clt_port_init(&pdvobj->clt_port);
-+#endif
-+	_rtw_spinlock_init(&pdvobj->cam_ctl.lock);
-+	_rtw_mutex_init(&pdvobj->cam_ctl.sec_cam_access_mutex);
-+#if defined(CONFIG_PLATFORM_RTK129X) && defined(CONFIG_PCI_HCI)
-+	_rtw_spinlock_init(&pdvobj->io_reg_lock);
-+#endif
-+#ifdef CONFIG_MBSSID_CAM
-+	rtw_mbid_cam_init(pdvobj);
-+#endif
-+
-+#ifdef CONFIG_AP_MODE
-+	#ifdef CONFIG_SUPPORT_MULTI_BCN
-+	pdvobj->nr_ap_if = 0;
-+	pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL; /* default value is equal to the default beacon_interval (100ms) */
-+	_rtw_init_queue(&pdvobj->ap_if_q);
-+	pdvobj->vap_map = 0;
-+	#endif /*CONFIG_SUPPORT_MULTI_BCN*/
-+	#ifdef CONFIG_SWTIMER_BASED_TXBCN
-+	rtw_init_timer(&(pdvobj->txbcn_timer), NULL, tx_beacon_timer_handlder, pdvobj);
-+	#endif
-+#endif
-+
-+	rtw_init_timer(&(pdvobj->dynamic_chk_timer), NULL, rtw_dynamic_check_timer_handlder, pdvobj);
-+	rtw_init_timer(&(pdvobj->periodic_tsf_update_end_timer), NULL, rtw_hal_periodic_tsf_update_end_timer_hdl, pdvobj);
-+
-+#ifdef CONFIG_MCC_MODE
-+	_rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_mutex));
-+	_rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_tsf_req_mutex));
-+	_rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_dbg_reg_mutex));
-+	_rtw_spinlock_init(&pdvobj->mcc_objpriv.mcc_lock);
-+#endif /* CONFIG_MCC_MODE */
-+
-+#ifdef CONFIG_RTW_NAPI_DYNAMIC
-+	pdvobj->en_napi_dynamic = 0;
-+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
-+
-+
-+#ifdef CONFIG_RTW_TPT_MODE
-+	pdvobj->tpt_mode = 0;
-+	pdvobj->edca_be_ul = 0x5ea42b;
-+	pdvobj->edca_be_dl = 0x00a42b;
-+#endif 
-+	pdvobj->scan_deny = _FALSE;
-+
-+	return pdvobj;
-+
-+}
-+
-+void devobj_deinit(struct dvobj_priv *pdvobj)
-+{
-+	if (!pdvobj)
-+		return;
-+
-+	/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
-+#if defined(CONFIG_IOCTL_CFG80211)
-+	rtw_cfg80211_dev_res_free(pdvobj);
-+#endif
-+
-+#ifdef CONFIG_MCC_MODE
-+	_rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_mutex));
-+	_rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_tsf_req_mutex));
-+	_rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_dbg_reg_mutex));
-+	_rtw_spinlock_free(&pdvobj->mcc_objpriv.mcc_lock);
-+#endif /* CONFIG_MCC_MODE */
-+
-+	_rtw_mutex_free(&pdvobj->hw_init_mutex);
-+	_rtw_mutex_free(&pdvobj->h2c_fwcmd_mutex);
-+
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+	_rtw_mutex_free(&pdvobj->customer_str_mutex);
-+#endif
-+#ifdef CONFIG_PROTSEL_PORT
-+	_rtw_mutex_free(&pdvobj->protsel_port.mutex);
-+#endif
-+#ifdef CONFIG_PROTSEL_ATIMDTIM
-+	_rtw_mutex_free(&pdvobj->protsel_atimdtim.mutex);
-+#endif
-+#ifdef CONFIG_PROTSEL_MACSLEEP
-+	_rtw_mutex_free(&pdvobj->protsel_macsleep.mutex);
-+#endif
-+
-+	_rtw_mutex_free(&pdvobj->setch_mutex);
-+	_rtw_mutex_free(&pdvobj->setbw_mutex);
-+	_rtw_mutex_free(&pdvobj->rf_read_reg_mutex);
-+	_rtw_mutex_free(&pdvobj->ioctrl_mutex);
-+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
-+	_rtw_mutex_free(&pdvobj->sd_indirect_access_mutex);
-+#endif
-+#ifdef CONFIG_SYSON_INDIRECT_ACCESS
-+	_rtw_mutex_free(&pdvobj->syson_indirect_access_mutex);
-+#endif
-+
-+	rtw_macid_ctl_deinit(&pdvobj->macid_ctl);
-+#ifdef CONFIG_CLIENT_PORT_CFG
-+	rtw_clt_port_deinit(&pdvobj->clt_port);
-+#endif
-+
-+	_rtw_spinlock_free(&pdvobj->cam_ctl.lock);
-+	_rtw_mutex_free(&pdvobj->cam_ctl.sec_cam_access_mutex);
-+
-+#if defined(CONFIG_PLATFORM_RTK129X) && defined(CONFIG_PCI_HCI)
-+	_rtw_spinlock_free(&pdvobj->io_reg_lock);
-+#endif
-+#ifdef CONFIG_MBSSID_CAM
-+	rtw_mbid_cam_deinit(pdvobj);
-+#endif
-+#ifdef CONFIG_SUPPORT_MULTI_BCN
-+	_rtw_spinlock_free(&(pdvobj->ap_if_q.lock));
-+#endif
-+	rtw_mfree((u8 *)pdvobj, sizeof(*pdvobj));
-+}
-+
-+inline u8 rtw_rtnl_lock_needed(struct dvobj_priv *dvobj)
-+{
-+	if (dvobj->rtnl_lock_holder && dvobj->rtnl_lock_holder == current)
-+		return 0;
-+	return 1;
-+}
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
-+static inline int rtnl_is_locked(void)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 17))
-+	if (unlikely(rtnl_trylock())) {
-+		rtnl_unlock();
-+#else
-+	if (unlikely(down_trylock(&rtnl_sem) == 0)) {
-+		up(&rtnl_sem);
-+#endif
-+		return 0;
-+	}
-+	return 1;
-+}
-+#endif
-+
-+inline void rtw_set_rtnl_lock_holder(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl)
-+{
-+	rtw_warn_on(!rtnl_is_locked());
-+
-+	if (!thd_hdl || rtnl_is_locked())
-+		dvobj->rtnl_lock_holder = thd_hdl;
-+
-+	if (dvobj->rtnl_lock_holder && 0)
-+		RTW_INFO("rtnl_lock_holder: %s:%d\n", current->comm, current->pid);
-+}
-+
-+u8 rtw_reset_drv_sw(_adapter *padapter)
-+{
-+	u8	ret8 = _SUCCESS;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+
-+	/* hal_priv */
-+	rtw_hal_def_value_init(padapter);
-+
-+	RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
-+	RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
-+
-+	padapter->bLinkInfoDump = 0;
-+
-+	padapter->xmitpriv.tx_pkts = 0;
-+	padapter->recvpriv.rx_pkts = 0;
-+
-+	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
-+
-+	/* pmlmepriv->LinkDetectInfo.TrafficBusyState = _FALSE; */
-+	pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;
-+	pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;
-+
-+	_clr_fwstate_(pmlmepriv, WIFI_UNDER_SURVEY | WIFI_UNDER_LINKING);
-+
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	if (is_primary_adapter(padapter))
-+		rtw_hal_sreset_reset_value(padapter);
-+#endif
-+	pwrctrlpriv->pwr_state_check_cnts = 0;
-+
-+	/* mlmeextpriv */
-+	mlmeext_set_scan_state(&padapter->mlmeextpriv, SCAN_DISABLE);
-+
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+	rtw_set_signal_stat_timer(&padapter->recvpriv);
-+#endif
-+
-+	return ret8;
-+}
-+
-+
-+u8 rtw_init_drv_sw(_adapter *padapter)
-+{
-+	u8	ret8 = _SUCCESS;
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+#endif
-+
-+	#if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN)
-+	_rtw_init_listhead(&padapter->list);
-+	#ifdef CONFIG_FW_HANDLE_TXBCN
-+	padapter->vap_id = CONFIG_LIMITED_AP_NUM;
-+	if (is_primary_adapter(padapter))
-+		adapter_to_dvobj(padapter)->vap_tbtt_rpt_map = adapter_to_regsty(padapter)->fw_tbtt_rpt;
-+	#endif
-+	#endif
-+
-+	#ifdef CONFIG_CLIENT_PORT_CFG
-+	padapter->client_id = MAX_CLIENT_PORT_NUM;
-+	padapter->client_port = CLT_PORT_INVALID;
-+	#endif
-+
-+	if (is_primary_adapter(padapter)) {
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+		struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+
-+		dvobj->macid_ctl.num = rtw_min(hal_spec->macid_num, MACID_NUM_SW_LIMIT);
-+		dvobj->macid_ctl.macid_cap = hal_spec->macid_cap;
-+		dvobj->macid_ctl.macid_txrpt = hal_spec->macid_txrpt;
-+		dvobj->macid_ctl.macid_txrpt_pgsz = hal_spec->macid_txrpt_pgsz;
-+		dvobj->cam_ctl.sec_cap = hal_spec->sec_cap;
-+		dvobj->cam_ctl.num = rtw_min(hal_spec->sec_cam_ent_num, SEC_CAM_ENT_NUM_SW_LIMIT);
-+		
-+		dvobj->wow_ctl.wow_cap = hal_spec->wow_cap;
-+
-+		#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+		dvobj->tx_aval_int_thr_mode = 2; /*setting by max tx length*/
-+		dvobj->tx_aval_int_thr_value = 0;
-+		#endif /*CONFIG_SDIO_TX_ENABLE_AVAL_INT*/
-+		
-+		#if CONFIG_TX_AC_LIFETIME
-+		{
-+			struct registry_priv *regsty = adapter_to_regsty(padapter);
-+			int i;
-+
-+			dvobj->tx_aclt_flags = regsty->tx_aclt_flags;
-+			for (i = 0; i < TX_ACLT_CONF_NUM; i++) {
-+				dvobj->tx_aclt_confs[i].en = regsty->tx_aclt_confs[i].en;
-+				dvobj->tx_aclt_confs[i].vo_vi
-+					= regsty->tx_aclt_confs[i].vo_vi / (hal_spec->tx_aclt_unit_factor * 32);
-+				if (dvobj->tx_aclt_confs[i].vo_vi > 0xFFFF)
-+					dvobj->tx_aclt_confs[i].vo_vi = 0xFFFF;
-+				dvobj->tx_aclt_confs[i].be_bk
-+					= regsty->tx_aclt_confs[i].be_bk / (hal_spec->tx_aclt_unit_factor * 32);
-+				if (dvobj->tx_aclt_confs[i].be_bk > 0xFFFF)
-+					dvobj->tx_aclt_confs[i].be_bk = 0xFFFF;
-+			}
-+
-+			dvobj->tx_aclt_force_val.en = 0xFF;
-+		}
-+		#endif
-+	}
-+
-+	ret8 = rtw_init_default_value(padapter);
-+
-+	if ((rtw_init_cmd_priv(&padapter->cmdpriv)) == _FAIL) {
-+		ret8 = _FAIL;
-+		goto exit;
-+	}
-+
-+	padapter->cmdpriv.padapter = padapter;
-+
-+	if ((rtw_init_evt_priv(&padapter->evtpriv)) == _FAIL) {
-+		ret8 = _FAIL;
-+		goto exit;
-+	}
-+
-+	if (is_primary_adapter(padapter)) {
-+		if (rtw_hal_rfpath_init(padapter) == _FAIL) {
-+			ret8 = _FAIL;
-+			goto exit;
-+		}
-+		if (rtw_hal_trxnss_init(padapter) == _FAIL) {
-+			ret8 = _FAIL;
-+			goto exit;
-+		}
-+		if (rtw_hal_runtime_trx_path_decision(padapter) == _FAIL) {
-+			ret8 = _FAIL;
-+			goto exit;
-+		}
-+		if (rtw_rfctl_init(padapter) == _FAIL) {
-+			ret8 = _FAIL;
-+			goto exit;
-+		}
-+	}
-+
-+	if (rtw_init_mlme_priv(padapter) == _FAIL) {
-+		ret8 = _FAIL;
-+		goto exit;
-+	}
-+
-+#if (defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)) || defined(CONFIG_IOCTL_CFG80211)
-+	rtw_init_roch_info(padapter);
-+#endif
-+
-+#ifdef CONFIG_P2P
-+	rtw_init_wifidirect_timers(padapter);
-+	init_wifidirect_info(padapter, P2P_ROLE_DISABLE);
-+	reset_global_wifidirect_info(padapter);
-+#ifdef CONFIG_WFD
-+	if (rtw_init_wifi_display_info(padapter) == _FAIL)
-+		RTW_ERR("Can't init init_wifi_display_info\n");
-+#endif
-+#endif /* CONFIG_P2P */
-+
-+	if (init_mlme_ext_priv(padapter) == _FAIL) {
-+		ret8 = _FAIL;
-+		goto exit;
-+	}
-+
-+#ifdef CONFIG_TDLS
-+	if (rtw_init_tdls_info(padapter) == _FAIL) {
-+		RTW_INFO("Can't rtw_init_tdls_info\n");
-+		ret8 = _FAIL;
-+		goto exit;
-+	}
-+#endif /* CONFIG_TDLS */
-+
-+#ifdef CONFIG_RTW_MESH
-+	rtw_mesh_cfg_init(padapter);
-+#endif
-+
-+	if (_rtw_init_xmit_priv(&padapter->xmitpriv, padapter) == _FAIL) {
-+		RTW_INFO("Can't _rtw_init_xmit_priv\n");
-+		ret8 = _FAIL;
-+		goto exit;
-+	}
-+
-+	if (_rtw_init_recv_priv(&padapter->recvpriv, padapter) == _FAIL) {
-+		RTW_INFO("Can't _rtw_init_recv_priv\n");
-+		ret8 = _FAIL;
-+		goto exit;
-+	}
-+	/* add for CONFIG_IEEE80211W, none 11w also can use */
-+	_rtw_spinlock_init(&padapter->security_key_mutex);
-+
-+	/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
-+	/* _rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof (struct security_priv)); */
-+
-+	if (_rtw_init_sta_priv(&padapter->stapriv) == _FAIL) {
-+		RTW_INFO("Can't _rtw_init_sta_priv\n");
-+		ret8 = _FAIL;
-+		goto exit;
-+	}
-+
-+	padapter->setband = WIFI_FREQUENCY_BAND_AUTO;
-+	padapter->fix_rate = 0xFF;
-+	padapter->power_offset = 0;
-+	padapter->rsvd_page_offset = 0;
-+	padapter->rsvd_page_num = 0;
-+
-+	padapter->data_fb = 0;
-+	padapter->fix_rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID;
-+	padapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID;
-+#ifdef DBG_RX_COUNTER_DUMP
-+	padapter->dump_rx_cnt_mode = 0;
-+	padapter->drv_rx_cnt_ok = 0;
-+	padapter->drv_rx_cnt_crcerror = 0;
-+	padapter->drv_rx_cnt_drop = 0;
-+#endif
-+	rtw_init_bcmc_stainfo(padapter);
-+
-+	rtw_init_pwrctrl_priv(padapter);
-+
-+	/* _rtw_memset((u8 *)&padapter->qospriv, 0, sizeof (struct qos_priv)); */ /* move to mlme_priv */
-+
-+#ifdef CONFIG_MP_INCLUDED
-+	if (init_mp_priv(padapter) == _FAIL)
-+		RTW_INFO("%s: initialize MP private data Fail!\n", __func__);
-+#endif
-+
-+	rtw_hal_dm_init(padapter);
-+
-+	if (is_primary_adapter(padapter))
-+		rtw_rfctl_chplan_init(padapter);
-+
-+#ifdef CONFIG_RTW_SW_LED
-+	rtw_hal_sw_led_init(padapter);
-+#endif
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	rtw_hal_sreset_init(padapter);
-+#endif
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	padapter->WapiSupport = true; /* set true temp, will revise according to Efuse or Registry value later. */
-+	rtw_wapi_init(padapter);
-+#endif
-+
-+#ifdef CONFIG_BR_EXT
-+	_rtw_spinlock_init(&padapter->br_ext_lock);
-+#endif /* CONFIG_BR_EXT */
-+
-+#ifdef CONFIG_BEAMFORMING
-+#ifdef RTW_BEAMFORMING_VERSION_2
-+	rtw_bf_init(padapter);
-+#endif /* RTW_BEAMFORMING_VERSION_2 */
-+#endif /* CONFIG_BEAMFORMING */
-+
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	init_rtw_rson_data(adapter_to_dvobj(padapter));
-+#endif
-+
-+#ifdef CONFIG_RTW_80211K
-+	rtw_init_rm(padapter);
-+#endif
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+	memset(pwdev_priv->pno_mac_addr, 0xFF, ETH_ALEN);
-+#endif
-+
-+exit:
-+
-+
-+
-+	return ret8;
-+
-+}
-+
-+#ifdef CONFIG_WOWLAN
-+void rtw_cancel_dynamic_chk_timer(_adapter *padapter)
-+{
-+	_cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer);
-+}
-+#endif
-+
-+void rtw_cancel_all_timer(_adapter *padapter)
-+{
-+
-+	_cancel_timer_ex(&padapter->mlmepriv.assoc_timer);
-+
-+	_cancel_timer_ex(&padapter->mlmepriv.scan_to_timer);
-+
-+#ifdef CONFIG_DFS_MASTER
-+	_cancel_timer_ex(&adapter_to_rfctl(padapter)->radar_detect_timer);
-+#endif
-+
-+	_cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer);
-+	_cancel_timer_ex(&adapter_to_dvobj(padapter)->periodic_tsf_update_end_timer);
-+#ifdef CONFIG_RTW_SW_LED
-+	/* cancel sw led timer */
-+	rtw_hal_sw_led_deinit(padapter);
-+#endif
-+	_cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_state_check_timer));
-+
-+#ifdef CONFIG_TX_AMSDU
-+	_cancel_timer_ex(&padapter->xmitpriv.amsdu_bk_timer);
-+	_cancel_timer_ex(&padapter->xmitpriv.amsdu_be_timer);
-+	_cancel_timer_ex(&padapter->xmitpriv.amsdu_vo_timer);
-+	_cancel_timer_ex(&padapter->xmitpriv.amsdu_vi_timer);
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	_cancel_timer_ex(&padapter->rochinfo.remain_on_ch_timer);
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+#ifdef CONFIG_SET_SCAN_DENY_TIMER
-+	_cancel_timer_ex(&padapter->mlmepriv.set_scan_deny_timer);
-+	rtw_clear_scan_deny(padapter);
-+#endif
-+
-+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-+	_cancel_timer_ex(&padapter->recvpriv.signal_stat_timer);
-+#endif
-+
-+#ifdef CONFIG_LPS_RPWM_TIMER
-+	_cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_rpwm_timer));
-+#endif /* CONFIG_LPS_RPWM_TIMER */
-+
-+#ifdef CONFIG_RTW_TOKEN_BASED_XMIT	
-+	_cancel_timer_ex(&padapter->mlmeextpriv.tbtx_xmit_timer);
-+	_cancel_timer_ex(&padapter->mlmeextpriv.tbtx_token_dispatch_timer);
-+#endif
-+
-+	/* cancel dm timer */
-+	rtw_hal_dm_deinit(padapter);
-+
-+#ifdef CONFIG_PLATFORM_FS_MX61
-+	msleep(50);
-+#endif
-+}
-+
-+u8 rtw_free_drv_sw(_adapter *padapter)
-+{
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	rtw_wapi_free(padapter);
-+#endif
-+
-+	/* we can call rtw_p2p_enable here, but: */
-+	/* 1. rtw_p2p_enable may have IO operation */
-+	/* 2. rtw_p2p_enable is bundled with wext interface */
-+	#ifdef CONFIG_P2P
-+	{
-+		struct wifidirect_info *pwdinfo = &padapter->wdinfo;
-+		#ifdef CONFIG_CONCURRENT_MODE
-+		struct roch_info *prochinfo = &padapter->rochinfo;
-+		#endif
-+		if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
-+			_cancel_timer_ex(&pwdinfo->find_phase_timer);
-+			_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
-+			_cancel_timer_ex(&pwdinfo->pre_tx_scan_timer);
-+			#ifdef CONFIG_CONCURRENT_MODE
-+			_cancel_timer_ex(&prochinfo->ap_roch_ch_switch_timer);
-+			#endif /* CONFIG_CONCURRENT_MODE */
-+			rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE);
-+		}
-+	}
-+	#endif
-+	/* add for CONFIG_IEEE80211W, none 11w also can use */
-+	_rtw_spinlock_free(&padapter->security_key_mutex);
-+
-+#ifdef CONFIG_BR_EXT
-+	_rtw_spinlock_free(&padapter->br_ext_lock);
-+#endif /* CONFIG_BR_EXT */
-+
-+	free_mlme_ext_priv(&padapter->mlmeextpriv);
-+
-+#ifdef CONFIG_TDLS
-+	/* rtw_free_tdls_info(&padapter->tdlsinfo); */
-+#endif /* CONFIG_TDLS */
-+
-+#ifdef CONFIG_RTW_80211K
-+	rtw_free_rm_priv(padapter);
-+#endif
-+
-+	rtw_free_cmd_priv(&padapter->cmdpriv);
-+
-+	rtw_free_evt_priv(&padapter->evtpriv);
-+
-+	rtw_free_mlme_priv(&padapter->mlmepriv);
-+
-+	if (is_primary_adapter(padapter))
-+		rtw_rfctl_deinit(padapter);
-+
-+	/* free_io_queue(padapter); */
-+
-+	_rtw_free_xmit_priv(&padapter->xmitpriv);
-+
-+	_rtw_free_sta_priv(&padapter->stapriv); /* will free bcmc_stainfo here */
-+
-+	_rtw_free_recv_priv(&padapter->recvpriv);
-+
-+	rtw_free_pwrctrl_priv(padapter);
-+
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+	if (padapter->cmap_bss_status_evt) {
-+		cmap_intfs_mfree(padapter->cmap_bss_status_evt, padapter->cmap_bss_status_evt_len);
-+		padapter->cmap_bss_status_evt = NULL;
-+	}
-+#endif
-+
-+	/* rtw_mfree((void *)padapter, sizeof (padapter)); */
-+
-+	rtw_hal_free_data(padapter);
-+
-+	return _SUCCESS;
-+
-+}
-+void rtw_intf_start(_adapter *adapter)
-+{
-+	if (adapter->intf_start)
-+		adapter->intf_start(adapter);
-+	GET_HAL_DATA(adapter)->intf_start = 1;
-+}
-+void rtw_intf_stop(_adapter *adapter)
-+{
-+	if (adapter->intf_stop)
-+		adapter->intf_stop(adapter);
-+	GET_HAL_DATA(adapter)->intf_start = 0;
-+}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+#ifndef CONFIG_NEW_NETDEV_HDL
-+int _netdev_vir_if_open(struct net_device *pnetdev)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
-+	_adapter *primary_padapter = GET_PRIMARY_ADAPTER(padapter);
-+
-+	RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
-+
-+	if (!primary_padapter)
-+		goto _netdev_virtual_iface_open_error;
-+
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+	if (padapter->bup == _FALSE) {
-+		u8 mac[ETH_ALEN];
-+
-+		/* get mac address from primary_padapter */
-+		if (primary_padapter->bup == _FALSE)
-+			rtw_macaddr_cfg(adapter_mac_addr(primary_padapter), get_hal_mac_addr(primary_padapter));
-+
-+		_rtw_memcpy(mac, adapter_mac_addr(primary_padapter), ETH_ALEN);
-+
-+		/*
-+		* If the BIT1 is 0, the address is universally administered.
-+		* If it is 1, the address is locally administered
-+		*/
-+		mac[0] |= BIT(1);
-+
-+		_rtw_memcpy(adapter_mac_addr(padapter), mac, ETH_ALEN);
-+
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+		rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));
-+#endif
-+		rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
-+		_rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN);
-+	}
-+#endif /*CONFIG_PLATFORM_INTEL_BYT*/
-+
-+	if (primary_padapter->bup == _FALSE || !rtw_is_hw_init_completed(primary_padapter))
-+		_netdev_open(primary_padapter->pnetdev);
-+
-+	if (padapter->bup == _FALSE && primary_padapter->bup == _TRUE &&
-+	    rtw_is_hw_init_completed(primary_padapter)) {
-+#if 0 /*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/
-+		rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */
-+#endif
-+
-+	}
-+
-+	if (padapter->bup == _FALSE) {
-+		if (rtw_start_drv_threads(padapter) == _FAIL)
-+			goto _netdev_virtual_iface_open_error;
-+	}
-+
-+#ifdef CONFIG_RTW_NAPI
-+	if (padapter->napi_state == NAPI_DISABLE) {
-+		napi_enable(&padapter->napi);
-+		padapter->napi_state = NAPI_ENABLE;
-+	}
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	rtw_cfg80211_init_wdev_data(padapter);
-+#endif
-+
-+	padapter->bup = _TRUE;
-+
-+	padapter->net_closed = _FALSE;
-+
-+	rtw_netif_wake_queue(pnetdev);
-+
-+	RTW_INFO(FUNC_NDEV_FMT" (bup=%d) exit\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
-+
-+	return 0;
-+
-+_netdev_virtual_iface_open_error:
-+
-+	padapter->bup = _FALSE;
-+
-+#ifdef CONFIG_RTW_NAPI
-+	if(padapter->napi_state == NAPI_ENABLE) {
-+		napi_disable(&padapter->napi);
-+		padapter->napi_state = NAPI_DISABLE;
-+	}
-+#endif
-+
-+	rtw_netif_carrier_off(pnetdev);
-+	rtw_netif_stop_queue(pnetdev);
-+
-+	return -1;
-+
-+}
-+
-+int netdev_vir_if_open(struct net_device *pnetdev)
-+{
-+	int ret;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
-+
-+	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
-+	ret = _netdev_vir_if_open(pnetdev);
-+	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
-+
-+#ifdef CONFIG_AUTO_AP_MODE
-+	/* if(padapter->iface_id == 2) */
-+	/*	rtw_start_auto_ap(padapter); */
-+#endif
-+
-+	return ret;
-+}
-+
-+static int netdev_vir_if_close(struct net_device *pnetdev)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+
-+	RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
-+	padapter->net_closed = _TRUE;
-+	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
-+
-+	if (pnetdev)
-+		rtw_netif_stop_queue(pnetdev);
-+
-+#ifdef CONFIG_P2P
-+	if (!rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_DISABLE))
-+		rtw_p2p_enable(padapter, P2P_ROLE_DISABLE);
-+#endif
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	rtw_scan_abort(padapter);
-+	rtw_cfg80211_wait_scan_req_empty(padapter, 200);
-+	adapter_wdev_data(padapter)->bandroid_scan = _FALSE;
-+#endif
-+
-+	return 0;
-+}
-+#endif /*#ifndef CONFIG_NEW_NETDEV_HDL*/
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+static const struct net_device_ops rtw_netdev_vir_if_ops = {
-+	.ndo_init = rtw_ndev_init,
-+	.ndo_uninit = rtw_ndev_uninit,
-+	#ifdef CONFIG_NEW_NETDEV_HDL
-+	.ndo_open = netdev_open,
-+	.ndo_stop = netdev_close,
-+	#else
-+	.ndo_open = netdev_vir_if_open,
-+	.ndo_stop = netdev_vir_if_close,
-+	#endif
-+	.ndo_start_xmit = rtw_xmit_entry,
-+	.ndo_set_mac_address = rtw_net_set_mac_address,
-+	.ndo_get_stats = rtw_net_get_stats,
-+	.ndo_do_ioctl = rtw_ioctl,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	.ndo_select_queue	= rtw_select_queue,
-+#endif
-+};
-+#endif
-+
-+static void rtw_hook_vir_if_ops(struct net_device *ndev)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+	ndev->netdev_ops = &rtw_netdev_vir_if_ops;
-+#else
-+	ndev->init = rtw_ndev_init;
-+	ndev->uninit = rtw_ndev_uninit;
-+	#ifdef CONFIG_NEW_NETDEV_HDL
-+	ndev->open = netdev_open;
-+	ndev->stop = netdev_close;
-+	#else
-+	ndev->open = netdev_vir_if_open;
-+	ndev->stop = netdev_vir_if_close;
-+	#endif
-+
-+	ndev->set_mac_address = rtw_net_set_mac_address;
-+#endif
-+}
-+_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter,
-+	void (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops))
-+{
-+	int res = _FAIL;
-+	_adapter *padapter = NULL;
-+	struct dvobj_priv *pdvobjpriv;
-+	u8 mac[ETH_ALEN];
-+#ifdef CONFIG_MI_UNIQUE_MACADDR_BIT
-+	u32 mi_unique_macaddr_bit = 0;
-+	u8 i;
-+#endif
-+
-+	/****** init adapter ******/
-+	padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter));
-+	if (padapter == NULL)
-+		goto exit;
-+
-+	if (loadparam(padapter) != _SUCCESS)
-+		goto free_adapter;
-+
-+	_rtw_memcpy(padapter, primary_padapter, sizeof(_adapter));
-+
-+	/*  */
-+	padapter->bup = _FALSE;
-+	padapter->net_closed = _TRUE;
-+	padapter->dir_dev = NULL;
-+	padapter->dir_odm = NULL;
-+
-+	/*set adapter_type/iface type*/
-+	padapter->isprimary = _FALSE;
-+	padapter->adapter_type = VIRTUAL_ADAPTER;
-+
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+	padapter->hw_port = HW_PORT0;
-+#elif defined(CONFIG_PORT_BASED_TXBCN)
-+	padapter->hw_port = adapter_to_dvobj(padapter)->iface_nums;
-+#else
-+	padapter->hw_port = HW_PORT1;
-+#endif
-+
-+
-+	/****** hook vir if into dvobj ******/
-+	pdvobjpriv = adapter_to_dvobj(padapter);
-+	padapter->iface_id = pdvobjpriv->iface_nums;
-+	pdvobjpriv->padapters[pdvobjpriv->iface_nums++] = padapter;
-+
-+	padapter->intf_start = primary_padapter->intf_start;
-+	padapter->intf_stop = primary_padapter->intf_stop;
-+
-+	/* step init_io_priv */
-+	if ((rtw_init_io_priv(padapter, set_intf_ops)) == _FAIL) {
-+		goto free_adapter;
-+	}
-+
-+	/*init drv data*/
-+	if (rtw_init_drv_sw(padapter) != _SUCCESS)
-+		goto free_drv_sw;
-+
-+
-+	/*get mac address from primary_padapter*/
-+	_rtw_memcpy(mac, adapter_mac_addr(primary_padapter), ETH_ALEN);
-+
-+#ifdef CONFIG_MI_UNIQUE_MACADDR_BIT
-+	mi_unique_macaddr_bit = BIT(CONFIG_MI_UNIQUE_MACADDR_BIT) >> 24;
-+	/* Find out CONFIG_MI_UNIQUE_MACADDR_BIT in which nic specific byte */
-+	for(i=3;i<6;i++) {
-+		if((mi_unique_macaddr_bit >> 8) == 0)
-+			break;
-+
-+		mi_unique_macaddr_bit >>= 8;
-+	}
-+
-+	if((mac[i] & (u8)mi_unique_macaddr_bit)== 0) {
-+		RTW_INFO("%s() "MAC_FMT" : BIT%u is zero\n", __func__, MAC_ARG(mac), CONFIG_MI_UNIQUE_MACADDR_BIT);
-+		/* IFACE_ID1/IFACE_ID3 : set locally administered bit */
-+		if(padapter->iface_id & BIT(0))
-+			mac[0] |= BIT(1);
-+		/* IFACE_ID2/IFACE_ID3 : set bit(CONFIG_MI_UNIQUE_MACADDR_BIT) */
-+		if(padapter->iface_id >> 1)
-+			mac[i] |= (u8)mi_unique_macaddr_bit;
-+	} else
-+#endif
-+	{
-+	/*
-+	* If the BIT1 is 0, the address is universally administered.
-+	* If it is 1, the address is locally administered
-+	*/
-+	mac[0] |= BIT(1);
-+	if (padapter->iface_id > IFACE_ID1)
-+		mac[0] ^= ((padapter->iface_id)<<2);
-+	}
-+
-+	_rtw_memcpy(adapter_mac_addr(padapter), mac, ETH_ALEN);
-+	/* update mac-address to mbsid-cam cache*/
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+	rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));
-+#endif
-+	RTW_INFO("%s if%d mac_addr : "MAC_FMT"\n", __func__, padapter->iface_id + 1, MAC_ARG(adapter_mac_addr(padapter)));
-+#ifdef CONFIG_P2P
-+	rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
-+#endif
-+
-+	rtw_led_set_ctl_en_mask_virtual(padapter);
-+	rtw_led_set_iface_en(padapter, 1);
-+
-+	res = _SUCCESS;
-+
-+free_drv_sw:
-+	if (res != _SUCCESS && padapter)
-+		rtw_free_drv_sw(padapter);
-+free_adapter:
-+	if (res != _SUCCESS && padapter) {
-+		rtw_vmfree((u8 *)padapter, sizeof(*padapter));
-+		padapter = NULL;
-+	}
-+exit:
-+	return padapter;
-+}
-+
-+void rtw_drv_stop_vir_if(_adapter *padapter)
-+{
-+	struct net_device *pnetdev = NULL;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+	if (padapter == NULL)
-+		return;
-+	RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(padapter));
-+
-+	pnetdev = padapter->pnetdev;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
-+		rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY);
-+
-+#ifdef CONFIG_AP_MODE
-+	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
-+		free_mlme_ap_info(padapter);
-+		#ifdef CONFIG_HOSTAPD_MLME
-+		hostapd_mode_unload(padapter);
-+		#endif
-+	}
-+#endif
-+
-+	if (padapter->bup == _TRUE) {
-+		#ifdef CONFIG_XMIT_ACK
-+		if (padapter->xmitpriv.ack_tx)
-+			rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP);
-+		#endif
-+
-+		rtw_intf_stop(padapter);
-+	#ifndef CONFIG_NEW_NETDEV_HDL
-+		rtw_stop_drv_threads(padapter);
-+	#endif
-+		padapter->bup = _FALSE;
-+	}
-+	#ifdef CONFIG_NEW_NETDEV_HDL
-+	rtw_stop_drv_threads(padapter);
-+	#endif
-+	/* cancel timer after thread stop */
-+	rtw_cancel_all_timer(padapter);
-+}
-+
-+void rtw_drv_free_vir_if(_adapter *padapter)
-+{
-+	if (padapter == NULL)
-+		return;
-+
-+	RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+	rtw_free_drv_sw(padapter);
-+
-+	/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
-+	rtw_os_ndev_free(padapter);
-+
-+	rtw_vmfree((u8 *)padapter, sizeof(_adapter));
-+}
-+
-+
-+void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj)
-+{
-+	int i;
-+
-+	for (i = VIF_START_ID; i < dvobj->iface_nums; i++)
-+		rtw_drv_stop_vir_if(dvobj->padapters[i]);
-+}
-+
-+void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj)
-+{
-+	int i;
-+
-+	for (i = VIF_START_ID; i < dvobj->iface_nums; i++)
-+		rtw_drv_free_vir_if(dvobj->padapters[i]);
-+}
-+
-+
-+#endif /*end of CONFIG_CONCURRENT_MODE*/
-+
-+/* IPv4, IPv6 IP addr notifier */
-+static int rtw_inetaddr_notifier_call(struct notifier_block *nb,
-+				      unsigned long action, void *data)
-+{
-+	struct in_ifaddr *ifa = (struct in_ifaddr *)data;
-+	struct net_device *ndev;
-+	struct mlme_ext_priv *pmlmeext = NULL;
-+	struct mlme_ext_info *pmlmeinfo = NULL;
-+	_adapter *adapter = NULL;
-+
-+	if (!ifa || !ifa->ifa_dev || !ifa->ifa_dev->dev)
-+		return NOTIFY_DONE;
-+
-+	ndev = ifa->ifa_dev->dev;
-+
-+	if (!is_rtw_ndev(ndev))
-+		return NOTIFY_DONE;
-+
-+	adapter = (_adapter *)rtw_netdev_priv(ifa->ifa_dev->dev);
-+
-+	if (adapter == NULL)
-+		return NOTIFY_DONE;
-+
-+	pmlmeext = &adapter->mlmeextpriv;
-+	pmlmeinfo = &pmlmeext->mlmext_info;
-+
-+	switch (action) {
-+	case NETDEV_UP:
-+		_rtw_memcpy(pmlmeinfo->ip_addr, &ifa->ifa_address,
-+					RTW_IP_ADDR_LEN);
-+		RTW_DBG("%s[%s]: up IP: %pI4\n", __func__,
-+					ifa->ifa_label, pmlmeinfo->ip_addr);
-+	break;
-+	case NETDEV_DOWN:
-+		_rtw_memset(pmlmeinfo->ip_addr, 0, RTW_IP_ADDR_LEN);
-+		RTW_DBG("%s[%s]: down IP: %pI4\n", __func__,
-+					ifa->ifa_label, pmlmeinfo->ip_addr);
-+	break;
-+	default:
-+		RTW_DBG("%s: default action\n", __func__);
-+	break;
-+	}
-+	return NOTIFY_DONE;
-+}
-+
-+#ifdef CONFIG_IPV6
-+static int rtw_inet6addr_notifier_call(struct notifier_block *nb,
-+				       unsigned long action, void *data)
-+{
-+	struct inet6_ifaddr *inet6_ifa = data;
-+	struct net_device *ndev;
-+	struct pwrctrl_priv *pwrctl = NULL;
-+	struct mlme_ext_priv *pmlmeext = NULL;
-+	struct mlme_ext_info *pmlmeinfo = NULL;
-+	_adapter *adapter = NULL;
-+
-+	if (!inet6_ifa || !inet6_ifa->idev || !inet6_ifa->idev->dev)
-+		return NOTIFY_DONE;
-+
-+	ndev = inet6_ifa->idev->dev;
-+
-+	if (!is_rtw_ndev(ndev))
-+		return NOTIFY_DONE;
-+
-+	adapter = (_adapter *)rtw_netdev_priv(inet6_ifa->idev->dev);
-+
-+	if (adapter == NULL)
-+		return NOTIFY_DONE;
-+
-+	pmlmeext =  &adapter->mlmeextpriv;
-+	pmlmeinfo = &pmlmeext->mlmext_info;
-+	pwrctl = adapter_to_pwrctl(adapter);
-+
-+	pmlmeext = &adapter->mlmeextpriv;
-+	pmlmeinfo = &pmlmeext->mlmext_info;
-+
-+	switch (action) {
-+	case NETDEV_UP:
-+#ifdef CONFIG_WOWLAN
-+		pwrctl->wowlan_ns_offload_en = _TRUE;
-+#endif
-+		_rtw_memcpy(pmlmeinfo->ip6_addr, &inet6_ifa->addr,
-+					RTW_IPv6_ADDR_LEN);
-+		RTW_DBG("%s: up IPv6 addrs: %pI6\n", __func__,
-+					pmlmeinfo->ip6_addr);
-+			break;
-+	case NETDEV_DOWN:
-+#ifdef CONFIG_WOWLAN
-+		pwrctl->wowlan_ns_offload_en = _FALSE;
-+#endif
-+		_rtw_memset(pmlmeinfo->ip6_addr, 0, RTW_IPv6_ADDR_LEN);
-+		RTW_DBG("%s: down IPv6 addrs: %pI6\n", __func__,
-+					pmlmeinfo->ip6_addr);
-+		break;
-+	default:
-+		RTW_DBG("%s: default action\n", __func__);
-+		break;
-+	}
-+	return NOTIFY_DONE;
-+}
-+#endif
-+
-+static struct notifier_block rtw_inetaddr_notifier = {
-+	.notifier_call = rtw_inetaddr_notifier_call
-+};
-+
-+#ifdef CONFIG_IPV6
-+static struct notifier_block rtw_inet6addr_notifier = {
-+	.notifier_call = rtw_inet6addr_notifier_call
-+};
-+#endif
-+
-+void rtw_inetaddr_notifier_register(void)
-+{
-+	RTW_INFO("%s\n", __func__);
-+	register_inetaddr_notifier(&rtw_inetaddr_notifier);
-+#ifdef CONFIG_IPV6
-+	register_inet6addr_notifier(&rtw_inet6addr_notifier);
-+#endif
-+}
-+
-+void rtw_inetaddr_notifier_unregister(void)
-+{
-+	RTW_INFO("%s\n", __func__);
-+	unregister_inetaddr_notifier(&rtw_inetaddr_notifier);
-+#ifdef CONFIG_IPV6
-+	unregister_inet6addr_notifier(&rtw_inet6addr_notifier);
-+#endif
-+}
-+
-+int rtw_os_ndevs_register(struct dvobj_priv *dvobj)
-+{
-+	int i, status = _SUCCESS;
-+	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
-+	_adapter *adapter;
-+
-+#if defined(CONFIG_IOCTL_CFG80211)
-+	if (rtw_cfg80211_dev_res_register(dvobj) != _SUCCESS) {
-+		rtw_warn_on(1);
-+		return _FAIL;
-+	}
-+#endif
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+
-+		if (i >= CONFIG_IFACE_NUMBER) {
-+			RTW_ERR("%s %d >= CONFIG_IFACE_NUMBER(%d)\n", __func__, i, CONFIG_IFACE_NUMBER);
-+			rtw_warn_on(1);
-+			continue;
-+		}
-+
-+		adapter = dvobj->padapters[i];
-+		if (adapter) {
-+			char *name;
-+
-+			#ifdef CONFIG_RTW_DYNAMIC_NDEV
-+			if (!is_primary_adapter(adapter))
-+				continue;
-+			#endif
-+
-+			if (adapter->iface_id == IFACE_ID0)
-+				name = regsty->ifname;
-+			else if (adapter->iface_id == IFACE_ID1)
-+				name = regsty->if2name;
-+			else
-+				name = "wlan%d";
-+
-+			status = rtw_os_ndev_register(adapter, name);
-+
-+			if (status != _SUCCESS) {
-+				rtw_warn_on(1);
-+				break;
-+			}
-+		}
-+	}
-+
-+	if (status != _SUCCESS) {
-+		for (; i >= 0; i--) {
-+			adapter = dvobj->padapters[i];
-+			if (adapter)
-+				rtw_os_ndev_unregister(adapter);
-+		}
-+	}
-+
-+#if defined(CONFIG_IOCTL_CFG80211)
-+	if (status != _SUCCESS)
-+		rtw_cfg80211_dev_res_unregister(dvobj);
-+#endif
-+	return status;
-+}
-+
-+void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj)
-+{
-+	int i;
-+	_adapter *adapter = NULL;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		adapter = dvobj->padapters[i];
-+
-+		if (adapter == NULL)
-+			continue;
-+
-+		rtw_os_ndev_unregister(adapter);
-+	}
-+
-+#if defined(CONFIG_IOCTL_CFG80211)
-+	rtw_cfg80211_dev_res_unregister(dvobj);
-+#endif
-+}
-+
-+/**
-+ * rtw_os_ndevs_init - Allocate and register OS layer net devices and relating structures for @dvobj
-+ * @dvobj: the dvobj on which this function applies
-+ *
-+ * Returns:
-+ * _SUCCESS or _FAIL
-+ */
-+int rtw_os_ndevs_init(struct dvobj_priv *dvobj)
-+{
-+	int ret = _FAIL;
-+
-+	if (rtw_os_ndevs_alloc(dvobj) != _SUCCESS)
-+		goto exit;
-+
-+	if (rtw_os_ndevs_register(dvobj) != _SUCCESS)
-+		goto os_ndevs_free;
-+
-+	ret = _SUCCESS;
-+
-+os_ndevs_free:
-+	if (ret != _SUCCESS)
-+		rtw_os_ndevs_free(dvobj);
-+exit:
-+	return ret;
-+}
-+
-+/**
-+ * rtw_os_ndevs_deinit - Unregister and free OS layer net devices and relating structures for @dvobj
-+ * @dvobj: the dvobj on which this function applies
-+ */
-+void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj)
-+{
-+	rtw_os_ndevs_unregister(dvobj);
-+	rtw_os_ndevs_free(dvobj);
-+}
-+
-+#ifdef CONFIG_BR_EXT
-+void netdev_br_init(struct net_device *netdev)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
-+
-+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
-+	rcu_read_lock();
-+#endif
-+
-+	/* if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) */
-+	{
-+		/* struct net_bridge	*br = netdev->br_port->br; */ /* ->dev->dev_addr; */
-+		#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
-+		if (netdev->br_port)
-+		#else
-+		if (rcu_dereference(adapter->pnetdev->rx_handler_data))
-+		#endif
-+		{
-+			struct net_device *br_netdev;
-+
-+			br_netdev = rtw_get_bridge_ndev_by_name(CONFIG_BR_EXT_BRNAME);
-+			if (br_netdev) {
-+				memcpy(adapter->br_mac, br_netdev->dev_addr, ETH_ALEN);
-+				dev_put(br_netdev);
-+				RTW_INFO(FUNC_NDEV_FMT" bind bridge dev "NDEV_FMT"("MAC_FMT")\n"
-+					, FUNC_NDEV_ARG(netdev), NDEV_ARG(br_netdev), MAC_ARG(br_netdev->dev_addr));
-+			} else {
-+				RTW_INFO(FUNC_NDEV_FMT" can't get bridge dev by name \"%s\"\n"
-+					, FUNC_NDEV_ARG(netdev), CONFIG_BR_EXT_BRNAME);
-+			}
-+		}
-+
-+		adapter->ethBrExtInfo.addPPPoETag = 1;
-+	}
-+
-+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35))
-+	rcu_read_unlock();
-+#endif
-+}
-+#endif /* CONFIG_BR_EXT */
-+
-+#ifdef CONFIG_NEW_NETDEV_HDL
-+int _netdev_open(struct net_device *pnetdev)
-+{
-+	uint status;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+
-+	RTW_INFO(FUNC_NDEV_FMT" start\n", FUNC_NDEV_ARG(pnetdev));
-+
-+	if (!rtw_is_hw_init_completed(padapter)) { // ips 
-+		rtw_clr_surprise_removed(padapter);
-+		rtw_clr_drv_stopped(padapter);
-+		RTW_ENABLE_FUNC(padapter, DF_RX_BIT);
-+		RTW_ENABLE_FUNC(padapter, DF_TX_BIT);
-+		status = rtw_hal_init(padapter);
-+		if (status == _FAIL)
-+			goto netdev_open_error;
-+		rtw_led_control(padapter, LED_CTL_NO_LINK);
-+		#ifndef RTW_HALMAC
-+		status = rtw_mi_start_drv_threads(padapter);
-+		if (status == _FAIL) {
-+			RTW_ERR(FUNC_NDEV_FMT "Initialize driver thread failed!\n", FUNC_NDEV_ARG(pnetdev));
-+			goto netdev_open_error;
-+		}
-+
-+		rtw_intf_start(GET_PRIMARY_ADAPTER(padapter));
-+		#endif /* !RTW_HALMAC */
-+
-+		{
-+	#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+			_adapter *prim_adpt = GET_PRIMARY_ADAPTER(padapter);
-+		
-+			if (prim_adpt && (_TRUE == prim_adpt->EEPROMBluetoothCoexist)) {
-+				rtw_btcoex_init_socket(prim_adpt);
-+				prim_adpt->coex_info.BtMgnt.ExtConfig.HCIExtensionVer = 0x04;
-+				rtw_btcoex_SetHciVersion(prim_adpt, 0x04);
-+			}
-+	#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+
-+			_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
-+
-+	#ifndef CONFIG_IPS_CHECK_IN_WD
-+			rtw_set_pwr_state_check_timer(pwrctrlpriv);
-+	#endif /*CONFIG_IPS_CHECK_IN_WD*/
-+		}
-+
-+	}
-+
-+	/*if (padapter->bup == _FALSE) */
-+	{
-+		rtw_hal_iface_init(padapter);
-+
-+		#ifdef CONFIG_RTW_NAPI
-+		if(padapter->napi_state == NAPI_DISABLE) {
-+			napi_enable(&padapter->napi);
-+			padapter->napi_state = NAPI_ENABLE;
-+		}
-+		#endif
-+
-+		#ifdef CONFIG_IOCTL_CFG80211
-+		rtw_cfg80211_init_wdev_data(padapter);
-+		#endif
-+		/* rtw_netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */
-+		rtw_netif_wake_queue(pnetdev);
-+
-+		#ifdef CONFIG_BR_EXT
-+		if (is_primary_adapter(padapter))
-+			netdev_br_init(pnetdev);
-+		#endif /* CONFIG_BR_EXT */
-+
-+
-+		padapter->bup = _TRUE;
-+		padapter->net_closed = _FALSE;
-+		padapter->netif_up = _TRUE;
-+		pwrctrlpriv->bips_processing = _FALSE;
-+	}
-+
-+	RTW_INFO(FUNC_NDEV_FMT" Success (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
-+	return 0;
-+
-+netdev_open_error:
-+	padapter->bup = _FALSE;
-+
-+	#ifdef CONFIG_RTW_NAPI
-+	if(padapter->napi_state == NAPI_ENABLE) {
-+		napi_disable(&padapter->napi);
-+		padapter->napi_state = NAPI_DISABLE;
-+	}
-+	#endif
-+
-+	rtw_netif_carrier_off(pnetdev);
-+	rtw_netif_stop_queue(pnetdev);
-+
-+	RTW_ERR(FUNC_NDEV_FMT" Failed!! (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
-+
-+	return -1;
-+
-+}
-+
-+#else
-+int _netdev_open(struct net_device *pnetdev)
-+{
-+	uint status;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+
-+
-+	RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
-+
-+	padapter->netif_up = _TRUE;
-+
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+	rtw_sdio_set_power(1);
-+#endif /* CONFIG_PLATFORM_INTEL_BYT */
-+
-+	if (padapter->bup == _FALSE) {
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+		rtw_macaddr_cfg(adapter_mac_addr(padapter),  get_hal_mac_addr(padapter));
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+		rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));
-+#endif
-+		rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
-+		_rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN);
-+#endif /* CONFIG_PLATFORM_INTEL_BYT */
-+
-+		rtw_clr_surprise_removed(padapter);
-+		rtw_clr_drv_stopped(padapter);
-+
-+		status = rtw_hal_init(padapter);
-+		if (status == _FAIL) {
-+			goto netdev_open_error;
-+		}
-+#if 0/*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/
-+		rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */
-+#endif
-+
-+		RTW_INFO("MAC Address = "MAC_FMT"\n", MAC_ARG(pnetdev->dev_addr));
-+
-+#ifndef RTW_HALMAC
-+		status = rtw_start_drv_threads(padapter);
-+		if (status == _FAIL) {
-+			RTW_INFO("Initialize driver software resource Failed!\n");
-+			goto netdev_open_error;
-+		}
-+#endif /* !RTW_HALMAC */
-+
-+#ifdef CONFIG_RTW_NAPI
-+		if(padapter->napi_state == NAPI_DISABLE) {
-+			napi_enable(&padapter->napi);
-+			padapter->napi_state = NAPI_ENABLE;
-+		}
-+#endif
-+
-+#ifndef RTW_HALMAC
-+		rtw_intf_start(padapter);
-+#endif /* !RTW_HALMAC */
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+		rtw_cfg80211_init_wdev_data(padapter);
-+#endif
-+
-+		rtw_led_control(padapter, LED_CTL_NO_LINK);
-+
-+		padapter->bup = _TRUE;
-+		pwrctrlpriv->bips_processing = _FALSE;
-+
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+#ifdef CONFIG_BT_COEXIST
-+		rtw_btcoex_IpsNotify(padapter, IPS_NONE);
-+#endif /* CONFIG_BT_COEXIST */
-+#endif /* CONFIG_PLATFORM_INTEL_BYT		 */
-+	}
-+	padapter->net_closed = _FALSE;
-+
-+	_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
-+
-+#ifndef CONFIG_IPS_CHECK_IN_WD
-+	rtw_set_pwr_state_check_timer(pwrctrlpriv);
-+#endif
-+
-+	/* rtw_netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */
-+	rtw_netif_wake_queue(pnetdev);
-+
-+#ifdef CONFIG_BR_EXT
-+	netdev_br_init(pnetdev);
-+#endif /* CONFIG_BR_EXT */
-+
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+	if (is_primary_adapter(padapter) && (_TRUE == pHalData->EEPROMBluetoothCoexist)) {
-+		rtw_btcoex_init_socket(padapter);
-+		padapter->coex_info.BtMgnt.ExtConfig.HCIExtensionVer = 0x04;
-+		rtw_btcoex_SetHciVersion(padapter, 0x04);
-+	} else
-+		RTW_INFO("CONFIG_BT_COEXIST: VIRTUAL_ADAPTER\n");
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	{
-+		_adapter *sec_adapter = adapter_to_dvobj(padapter)->padapters[IFACE_ID1];
-+
-+		#ifndef CONFIG_RTW_DYNAMIC_NDEV
-+		if (sec_adapter && (sec_adapter->bup == _FALSE))
-+			_netdev_vir_if_open(sec_adapter->pnetdev);
-+		#endif
-+	}
-+#endif
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
-+	pwrctrlpriv->radio_on_start_time = rtw_get_current_time();
-+	pwrctrlpriv->pwr_saving_start_time = rtw_get_current_time();
-+	pwrctrlpriv->pwr_saving_time = 0;
-+	pwrctrlpriv->on_time = 0;
-+	pwrctrlpriv->tx_time = 0;
-+	pwrctrlpriv->rx_time = 0;
-+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
-+
-+	RTW_INFO("-871x_drv - drv_open, bup=%d\n", padapter->bup);
-+
-+	return 0;
-+
-+netdev_open_error:
-+
-+	padapter->bup = _FALSE;
-+
-+#ifdef CONFIG_RTW_NAPI
-+	if(padapter->napi_state == NAPI_ENABLE) {
-+		napi_disable(&padapter->napi);
-+		padapter->napi_state = NAPI_DISABLE;
-+	}
-+#endif
-+
-+	rtw_netif_carrier_off(pnetdev);
-+	rtw_netif_stop_queue(pnetdev);
-+
-+	RTW_INFO("-871x_drv - drv_open fail, bup=%d\n", padapter->bup);
-+
-+	return -1;
-+
-+}
-+#endif
-+int netdev_open(struct net_device *pnetdev)
-+{
-+	int ret = _FALSE;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+
-+	if (pwrctrlpriv->bInSuspend == _TRUE) {
-+		RTW_INFO(" [WARN] "ADPT_FMT" %s  failed, bInSuspend=%d\n", ADPT_ARG(padapter), __func__, pwrctrlpriv->bInSuspend);
-+		return 0;
-+	}
-+
-+	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
-+#ifdef CONFIG_NEW_NETDEV_HDL
-+	ret = _netdev_open(pnetdev);
-+#else
-+	if (is_primary_adapter(padapter))
-+		ret = _netdev_open(pnetdev);
-+#ifdef CONFIG_CONCURRENT_MODE
-+	else
-+		ret = _netdev_vir_if_open(pnetdev);
-+#endif
-+#endif
-+	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
-+
-+
-+#ifdef CONFIG_AUTO_AP_MODE
-+	if (padapter->iface_id == IFACE_ID2)
-+		rtw_start_auto_ap(padapter);
-+#endif
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_IPS
-+int  ips_netdrv_open(_adapter *padapter)
-+{
-+	int status = _SUCCESS;
-+	/* struct pwrctrl_priv	*pwrpriv = adapter_to_pwrctl(padapter); */
-+
-+	padapter->net_closed = _FALSE;
-+
-+	RTW_INFO("===> %s.........\n", __FUNCTION__);
-+
-+
-+	rtw_clr_drv_stopped(padapter);
-+	/* padapter->bup = _TRUE; */
-+#ifdef CONFIG_NEW_NETDEV_HDL
-+	if (!rtw_is_hw_init_completed(padapter)) {
-+		status = rtw_hal_init(padapter);
-+		if (status == _FAIL) {
-+			goto netdev_open_error;
-+		}
-+		rtw_mi_hal_iface_init(padapter);
-+	}
-+#else
-+	status = rtw_hal_init(padapter);
-+	if (status == _FAIL) {
-+		goto netdev_open_error;
-+	}
-+#endif
-+#if 0
-+	rtw_mi_set_mac_addr(padapter);
-+#endif
-+#ifndef RTW_HALMAC
-+	rtw_intf_start(padapter);
-+#endif /* !RTW_HALMAC */
-+
-+#ifndef CONFIG_IPS_CHECK_IN_WD
-+	rtw_set_pwr_state_check_timer(adapter_to_pwrctl(padapter));
-+#endif
-+	_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
-+
-+	return _SUCCESS;
-+
-+netdev_open_error:
-+	/* padapter->bup = _FALSE; */
-+	RTW_INFO("-ips_netdrv_open - drv_open failure, bup=%d\n", padapter->bup);
-+
-+	return _FAIL;
-+}
-+
-+int rtw_ips_pwr_up(_adapter *padapter)
-+{
-+	int result;
-+#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
-+#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
-+#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */
-+	systime start_time = rtw_get_current_time();
-+	RTW_INFO("===>  rtw_ips_pwr_up..............\n");
-+
-+#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	if (psrtpriv->silent_reset_inprogress == _TRUE)
-+#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
-+#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */
-+		rtw_reset_drv_sw(padapter);
-+
-+	result = ips_netdrv_open(padapter);
-+
-+	rtw_led_control(padapter, LED_CTL_NO_LINK);
-+
-+	RTW_INFO("<===  rtw_ips_pwr_up.............. in %dms\n", rtw_get_passing_time_ms(start_time));
-+	return result;
-+
-+}
-+
-+void rtw_ips_pwr_down(_adapter *padapter)
-+{
-+	systime start_time = rtw_get_current_time();
-+	RTW_INFO("===> rtw_ips_pwr_down...................\n");
-+
-+	padapter->net_closed = _TRUE;
-+
-+	rtw_ips_dev_unload(padapter);
-+	RTW_INFO("<=== rtw_ips_pwr_down..................... in %dms\n", rtw_get_passing_time_ms(start_time));
-+}
-+#endif
-+void rtw_ips_dev_unload(_adapter *padapter)
-+{
-+#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;
-+#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
-+#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */
-+	RTW_INFO("====> %s...\n", __FUNCTION__);
-+
-+
-+#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS)
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+	if (psrtpriv->silent_reset_inprogress == _TRUE)
-+#endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
-+#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */
-+	{
-+		rtw_hal_set_hwreg(padapter, HW_VAR_FIFO_CLEARN_UP, 0);
-+		rtw_intf_stop(padapter);
-+	}
-+
-+	if (!rtw_is_surprise_removed(padapter))
-+		rtw_hal_deinit(padapter);
-+
-+}
-+#ifdef CONFIG_NEW_NETDEV_HDL
-+int _pm_netdev_open(_adapter *padapter)
-+{
-+	uint status;
-+	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
-+	struct net_device *pnetdev = padapter->pnetdev;
-+
-+	RTW_INFO(FUNC_NDEV_FMT" start\n", FUNC_NDEV_ARG(pnetdev));
-+
-+	if (!rtw_is_hw_init_completed(padapter)) { // ips 
-+		rtw_clr_surprise_removed(padapter);
-+		rtw_clr_drv_stopped(padapter);
-+		status = rtw_hal_init(padapter);
-+		if (status == _FAIL)
-+			goto netdev_open_error;
-+		rtw_led_control(padapter, LED_CTL_NO_LINK);
-+		#ifndef RTW_HALMAC
-+		status = rtw_mi_start_drv_threads(padapter);
-+		if (status == _FAIL) {
-+			RTW_ERR(FUNC_NDEV_FMT "Initialize driver thread failed!\n", FUNC_NDEV_ARG(pnetdev));
-+			goto netdev_open_error;
-+		}
-+
-+		rtw_intf_start(GET_PRIMARY_ADAPTER(padapter));
-+		#endif /* !RTW_HALMAC */
-+
-+		{
-+			_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
-+
-+	#ifndef CONFIG_IPS_CHECK_IN_WD
-+			rtw_set_pwr_state_check_timer(pwrctrlpriv);
-+	#endif /*CONFIG_IPS_CHECK_IN_WD*/
-+		}
-+
-+	}
-+
-+	/*if (padapter->bup == _FALSE) */
-+	{
-+		rtw_hal_iface_init(padapter);
-+
-+		padapter->bup = _TRUE;
-+		padapter->net_closed = _FALSE;
-+		padapter->netif_up = _TRUE;
-+		pwrctrlpriv->bips_processing = _FALSE;
-+	}
-+
-+	RTW_INFO(FUNC_NDEV_FMT" Success (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
-+	return 0;
-+
-+netdev_open_error:
-+	padapter->bup = _FALSE;
-+
-+	rtw_netif_carrier_off(pnetdev);
-+	rtw_netif_stop_queue(pnetdev);
-+
-+	RTW_ERR(FUNC_NDEV_FMT" Failed!! (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
-+
-+	return -1;
-+
-+}
-+int _mi_pm_netdev_open(struct net_device *pnetdev)
-+{
-+	int i;
-+	int status = 0;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
-+	_adapter *iface;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface->netif_up) {
-+			status = _pm_netdev_open(iface);
-+			if (status == -1) {
-+				RTW_ERR("%s failled\n", __func__);
-+				break;
-+			}
-+		}
-+	}
-+
-+	return status;
-+}
-+#endif /*CONFIG_NEW_NETDEV_HDL*/
-+int pm_netdev_open(struct net_device *pnetdev, u8 bnormal)
-+{
-+	int status = 0;
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
-+
-+	if (_TRUE == bnormal) {
-+		_enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
-+		#ifdef CONFIG_NEW_NETDEV_HDL
-+		status = _mi_pm_netdev_open(pnetdev);
-+		#else
-+		status = _netdev_open(pnetdev);
-+		#endif
-+		_exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL);
-+	}
-+#ifdef CONFIG_IPS
-+	else
-+		status = (_SUCCESS == ips_netdrv_open(padapter)) ? (0) : (-1);
-+#endif
-+
-+	return status;
-+}
-+#ifdef CONFIG_CLIENT_PORT_CFG
-+extern void rtw_hw_client_port_release(_adapter *adapter);
-+#endif
-+static int netdev_close(struct net_device *pnetdev)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+
-+	RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup);
-+#ifndef CONFIG_PLATFORM_INTEL_BYT
-+	padapter->net_closed = _TRUE;
-+	padapter->netif_up = _FALSE;
-+	pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
-+
-+#ifdef CONFIG_CLIENT_PORT_CFG
-+	if (MLME_IS_STA(padapter))
-+		rtw_hw_client_port_release(padapter);
-+#endif
-+	/*	if (!rtw_is_hw_init_completed(padapter)) {
-+			RTW_INFO("(1)871x_drv - drv_close, bup=%d, hw_init_completed=%s\n", padapter->bup, rtw_is_hw_init_completed(padapter)?"_TRUE":"_FALSE");
-+
-+			rtw_set_drv_stopped(padapter);
-+
-+			rtw_dev_unload(padapter);
-+		}
-+		else*/
-+	if (pwrctl->rf_pwrstate == rf_on) {
-+		RTW_INFO("(2)871x_drv - drv_close, bup=%d, hw_init_completed=%s\n", padapter->bup, rtw_is_hw_init_completed(padapter) ? "_TRUE" : "_FALSE");
-+
-+		/* s1. */
-+		if (pnetdev)
-+			rtw_netif_stop_queue(pnetdev);
-+
-+#ifndef CONFIG_RTW_ANDROID
-+		/* s2. */
-+		LeaveAllPowerSaveMode(padapter);
-+		rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK);
-+		/* s2-2.  indicate disconnect to os */
-+		rtw_indicate_disconnect(padapter, 0, _FALSE);
-+		/* s2-3. */
-+		rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK);
-+		/* s2-4. */
-+		rtw_free_network_queue(padapter, _TRUE);
-+#endif
-+	}
-+
-+#ifdef CONFIG_BR_EXT
-+	/* if (OPMODE & (WIFI_STATION_STATE | WIFI_ADHOC_STATE)) */
-+	{
-+		/* void nat25_db_cleanup(_adapter *priv); */
-+		nat25_db_cleanup(padapter);
-+	}
-+#endif /* CONFIG_BR_EXT */
-+
-+#ifdef CONFIG_P2P
-+	if (!rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_DISABLE))
-+		rtw_p2p_enable(padapter, P2P_ROLE_DISABLE);
-+#endif /* CONFIG_P2P */
-+
-+	rtw_scan_abort(padapter); /* stop scanning process before wifi is going to down */
-+#ifdef CONFIG_IOCTL_CFG80211
-+	rtw_cfg80211_wait_scan_req_empty(padapter, 200);
-+	adapter_wdev_data(padapter)->bandroid_scan = _FALSE;
-+	/* padapter->rtw_wdev->iftype = NL80211_IFTYPE_MONITOR; */ /* set this at the end */
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+#ifdef CONFIG_WAPI_SUPPORT
-+	rtw_wapi_disable_tx(padapter);
-+#endif
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+	if (is_primary_adapter(padapter) && (_TRUE == pHalData->EEPROMBluetoothCoexist))
-+		rtw_btcoex_close_socket(padapter);
-+	else
-+		RTW_INFO("CONFIG_BT_COEXIST: VIRTUAL_ADAPTER\n");
-+#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
-+#else /* !CONFIG_PLATFORM_INTEL_BYT */
-+
-+	if (pwrctl->bInSuspend == _TRUE) {
-+		RTW_INFO("+871x_drv - drv_close, bInSuspend=%d\n", pwrctl->bInSuspend);
-+		return 0;
-+	}
-+
-+	rtw_scan_abort(padapter); /* stop scanning process before wifi is going to down */
-+#ifdef CONFIG_IOCTL_CFG80211
-+	rtw_cfg80211_wait_scan_req_empty(padapter, 200);
-+#endif
-+
-+	RTW_INFO("netdev_close, bips_processing=%d\n", pwrctl->bips_processing);
-+	while (pwrctl->bips_processing == _TRUE) /* waiting for ips_processing done before call rtw_dev_unload() */
-+		rtw_msleep_os(1);
-+
-+	rtw_dev_unload(padapter);
-+	rtw_sdio_set_power(0);
-+
-+#endif /* !CONFIG_PLATFORM_INTEL_BYT */
-+
-+	RTW_INFO("-871x_drv - drv_close, bup=%d\n", padapter->bup);
-+
-+	return 0;
-+
-+}
-+
-+int pm_netdev_close(struct net_device *pnetdev, u8 bnormal)
-+{
-+	int status = 0;
-+
-+	status = netdev_close(pnetdev);
-+
-+	return status;
-+}
-+
-+void rtw_ndev_destructor(struct net_device *ndev)
-+{
-+	RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev));
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (ndev->ieee80211_ptr)
-+		rtw_mfree((u8 *)ndev->ieee80211_ptr, sizeof(struct wireless_dev));
-+#endif
-+	free_netdev(ndev);
-+}
-+
-+#ifdef CONFIG_ARP_KEEP_ALIVE
-+struct route_info {
-+	struct in_addr dst_addr;
-+	struct in_addr src_addr;
-+	struct in_addr gateway;
-+	unsigned int dev_index;
-+};
-+
-+static void parse_routes(struct nlmsghdr *nl_hdr, struct route_info *rt_info)
-+{
-+	struct rtmsg *rt_msg;
-+	struct rtattr *rt_attr;
-+	int rt_len;
-+
-+	rt_msg = (struct rtmsg *) NLMSG_DATA(nl_hdr);
-+	if ((rt_msg->rtm_family != AF_INET) || (rt_msg->rtm_table != RT_TABLE_MAIN))
-+		return;
-+
-+	rt_attr = (struct rtattr *) RTM_RTA(rt_msg);
-+	rt_len = RTM_PAYLOAD(nl_hdr);
-+
-+	for (; RTA_OK(rt_attr, rt_len); rt_attr = RTA_NEXT(rt_attr, rt_len)) {
-+		switch (rt_attr->rta_type) {
-+		case RTA_OIF:
-+			rt_info->dev_index = *(int *) RTA_DATA(rt_attr);
-+			break;
-+		case RTA_GATEWAY:
-+			rt_info->gateway.s_addr = *(u_int *) RTA_DATA(rt_attr);
-+			break;
-+		case RTA_PREFSRC:
-+			rt_info->src_addr.s_addr = *(u_int *) RTA_DATA(rt_attr);
-+			break;
-+		case RTA_DST:
-+			rt_info->dst_addr.s_addr = *(u_int *) RTA_DATA(rt_attr);
-+			break;
-+		}
-+	}
-+}
-+
-+static int route_dump(u32 *gw_addr , int *gw_index)
-+{
-+	int err = 0;
-+	struct socket *sock;
-+	struct {
-+		struct nlmsghdr nlh;
-+		struct rtgenmsg g;
-+	} req;
-+	struct msghdr msg;
-+	struct iovec iov;
-+	struct sockaddr_nl nladdr;
-+	mm_segment_t oldfs;
-+	char *pg;
-+	int size = 0;
-+
-+	err = sock_create(AF_NETLINK, SOCK_DGRAM, NETLINK_ROUTE, &sock);
-+	if (err) {
-+		printk(": Could not create a datagram socket, error = %d\n", -ENXIO);
-+		return err;
-+	}
-+
-+	memset(&nladdr, 0, sizeof(nladdr));
-+	nladdr.nl_family = AF_NETLINK;
-+
-+	req.nlh.nlmsg_len = sizeof(req);
-+	req.nlh.nlmsg_type = RTM_GETROUTE;
-+	req.nlh.nlmsg_flags = NLM_F_ROOT | NLM_F_MATCH | NLM_F_REQUEST;
-+	req.nlh.nlmsg_pid = 0;
-+	req.g.rtgen_family = AF_INET;
-+
-+	iov.iov_base = &req;
-+	iov.iov_len = sizeof(req);
-+
-+	msg.msg_name = &nladdr;
-+	msg.msg_namelen = sizeof(nladdr);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
-+	/* referece:sock_xmit in kernel code
-+	 * WRITE for sock_sendmsg, READ for sock_recvmsg
-+	 * third parameter for msg_iovlen
-+	 * last parameter for iov_len
-+	 */
-+	iov_iter_init(&msg.msg_iter, WRITE, &iov, 1, sizeof(req));
-+#else
-+	msg.msg_iov = &iov;
-+	msg.msg_iovlen = 1;
-+#endif
-+	msg.msg_control = NULL;
-+	msg.msg_controllen = 0;
-+	msg.msg_flags = MSG_DONTWAIT;
-+
-+	oldfs = get_fs();
-+	set_fs(KERNEL_DS);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
-+	err = sock_sendmsg(sock, &msg);
-+#else
-+	err = sock_sendmsg(sock, &msg, sizeof(req));
-+#endif
-+	set_fs(oldfs);
-+
-+	if (err < 0)
-+		goto out_sock;
-+
-+	pg = (char *) __get_free_page(GFP_KERNEL);
-+	if (pg == NULL) {
-+		err = -ENOMEM;
-+		goto out_sock;
-+	}
-+
-+#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
-+restart:
-+#endif
-+
-+	for (;;) {
-+		struct nlmsghdr *h;
-+
-+		iov.iov_base = pg;
-+		iov.iov_len = PAGE_SIZE;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
-+		iov_iter_init(&msg.msg_iter, READ, &iov, 1, PAGE_SIZE);
-+#endif
-+
-+		oldfs = get_fs();
-+		set_fs(KERNEL_DS);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
-+		err = sock_recvmsg(sock, &msg, MSG_DONTWAIT);
-+#else
-+		err = sock_recvmsg(sock, &msg, PAGE_SIZE, MSG_DONTWAIT);
-+#endif
-+		set_fs(oldfs);
-+
-+		if (err < 0)
-+			goto out_sock_pg;
-+
-+		if (msg.msg_flags & MSG_TRUNC) {
-+			err = -ENOBUFS;
-+			goto out_sock_pg;
-+		}
-+
-+		h = (struct nlmsghdr *) pg;
-+
-+		while (NLMSG_OK(h, err)) {
-+			struct route_info rt_info;
-+			if (h->nlmsg_type == NLMSG_DONE) {
-+				err = 0;
-+				goto done;
-+			}
-+
-+			if (h->nlmsg_type == NLMSG_ERROR) {
-+				struct nlmsgerr *errm = (struct nlmsgerr *) NLMSG_DATA(h);
-+				err = errm->error;
-+				printk("NLMSG error: %d\n", errm->error);
-+				goto done;
-+			}
-+
-+			if (h->nlmsg_type == RTM_GETROUTE)
-+				printk("RTM_GETROUTE: NLMSG: %d\n", h->nlmsg_type);
-+			if (h->nlmsg_type != RTM_NEWROUTE) {
-+				printk("NLMSG: %d\n", h->nlmsg_type);
-+				err = -EINVAL;
-+				goto done;
-+			}
-+
-+			memset(&rt_info, 0, sizeof(struct route_info));
-+			parse_routes(h, &rt_info);
-+			if (!rt_info.dst_addr.s_addr && rt_info.gateway.s_addr && rt_info.dev_index) {
-+				*gw_addr = rt_info.gateway.s_addr;
-+				*gw_index = rt_info.dev_index;
-+
-+			}
-+			h = NLMSG_NEXT(h, err);
-+		}
-+
-+		if (err) {
-+			printk("!!!Remnant of size %d %d %d\n", err, h->nlmsg_len, h->nlmsg_type);
-+			err = -EINVAL;
-+			break;
-+		}
-+	}
-+
-+done:
-+#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
-+	if (!err && req.g.rtgen_family == AF_INET) {
-+		req.g.rtgen_family = AF_INET6;
-+
-+		iov.iov_base = &req;
-+		iov.iov_len = sizeof(req);
-+
-+		msg.msg_name = &nladdr;
-+		msg.msg_namelen = sizeof(nladdr);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
-+		iov_iter_init(&msg.msg_iter, WRITE, &iov, 1, sizeof(req));
-+#else
-+		msg.msg_iov = &iov;
-+		msg.msg_iovlen = 1;
-+#endif
-+		msg.msg_control = NULL;
-+		msg.msg_controllen = 0;
-+		msg.msg_flags = MSG_DONTWAIT;
-+
-+		oldfs = get_fs();
-+		set_fs(KERNEL_DS);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
-+		err = sock_sendmsg(sock, &msg);
-+#else
-+		err = sock_sendmsg(sock, &msg, sizeof(req));
-+#endif
-+		set_fs(oldfs);
-+
-+		if (err > 0)
-+			goto restart;
-+	}
-+#endif
-+
-+out_sock_pg:
-+	free_page((unsigned long) pg);
-+
-+out_sock:
-+	sock_release(sock);
-+	return err;
-+}
-+
-+static int arp_query(unsigned char *haddr, u32 paddr,
-+		     struct net_device *dev)
-+{
-+	struct neighbour *neighbor_entry;
-+	int	ret = 0;
-+
-+	neighbor_entry = neigh_lookup(&arp_tbl, &paddr, dev);
-+
-+	if (neighbor_entry != NULL) {
-+		neighbor_entry->used = jiffies;
-+		if (neighbor_entry->nud_state & NUD_VALID) {
-+			_rtw_memcpy(haddr, neighbor_entry->ha, dev->addr_len);
-+			ret = 1;
-+		}
-+		neigh_release(neighbor_entry);
-+	}
-+	return ret;
-+}
-+
-+static int get_defaultgw(u32 *ip_addr , char mac[])
-+{
-+	int gw_index = 0; /* oif device index */
-+	struct net_device *gw_dev = NULL; /* oif device */
-+
-+	route_dump(ip_addr, &gw_index);
-+
-+	if (!(*ip_addr) || !gw_index) {
-+		/* RTW_INFO("No default GW\n"); */
-+		return -1;
-+	}
-+
-+	gw_dev = dev_get_by_index(&init_net, gw_index);
-+
-+	if (gw_dev == NULL) {
-+		/* RTW_INFO("get Oif Device Fail\n"); */
-+		return -1;
-+	}
-+
-+	if (!arp_query(mac, *ip_addr, gw_dev)) {
-+		/* RTW_INFO( "arp query failed\n"); */
-+		dev_put(gw_dev);
-+		return -1;
-+
-+	}
-+	dev_put(gw_dev);
-+
-+	return 0;
-+}
-+
-+int	rtw_gw_addr_query(_adapter *padapter)
-+{
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
-+	u32 gw_addr = 0; /* default gw address */
-+	unsigned char gw_mac[32] = {0}; /* default gw mac */
-+	int i;
-+	int res;
-+
-+	res = get_defaultgw(&gw_addr, gw_mac);
-+	if (!res) {
-+		pmlmepriv->gw_ip[0] = gw_addr & 0xff;
-+		pmlmepriv->gw_ip[1] = (gw_addr & 0xff00) >> 8;
-+		pmlmepriv->gw_ip[2] = (gw_addr & 0xff0000) >> 16;
-+		pmlmepriv->gw_ip[3] = (gw_addr & 0xff000000) >> 24;
-+		_rtw_memcpy(pmlmepriv->gw_mac_addr, gw_mac, ETH_ALEN);
-+		RTW_INFO("%s Gateway Mac:\t" MAC_FMT "\n", __FUNCTION__, MAC_ARG(pmlmepriv->gw_mac_addr));
-+		RTW_INFO("%s Gateway IP:\t" IP_FMT "\n", __FUNCTION__, IP_ARG(pmlmepriv->gw_ip));
-+	} else
-+		RTW_INFO("Get Gateway IP/MAC fail!\n");
-+
-+	return res;
-+}
-+#endif
-+
-+void rtw_dev_unload(PADAPTER padapter)
-+{
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
-+	struct dvobj_priv *pobjpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &pobjpriv->drv_dbg;
-+	struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-+
-+	if (padapter->bup == _TRUE) {
-+		RTW_INFO("==> "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+
-+#ifdef CONFIG_WOWLAN
-+#ifdef CONFIG_GPIO_WAKEUP
-+		/*default wake up pin change to BT*/
-+		RTW_INFO("%s:default wake up pin change to BT\n", __FUNCTION__);
-+		rtw_hal_switch_gpio_wl_ctrl(padapter, pwrctl->wowlan_gpio_index, _FALSE);
-+#endif /* CONFIG_GPIO_WAKEUP */
-+#endif /* CONFIG_WOWLAN */
-+
-+		rtw_set_drv_stopped(padapter);
-+#ifdef CONFIG_XMIT_ACK
-+		if (padapter->xmitpriv.ack_tx)
-+			rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP);
-+#endif
-+
-+		rtw_intf_stop(padapter);
-+		
-+		rtw_stop_drv_threads(padapter);
-+
-+		if (ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _TRUE) {
-+			RTW_ERR("cmd_thread not stop !!\n");
-+			rtw_warn_on(1);
-+		}
-+		
-+		/* check the status of IPS */
-+		if (rtw_hal_check_ips_status(padapter) == _TRUE || pwrctl->rf_pwrstate == rf_off) { /* check HW status and SW state */
-+			RTW_PRINT("%s: driver in IPS-FWLPS\n", __func__);
-+			pdbgpriv->dbg_dev_unload_inIPS_cnt++;
-+		} else
-+			RTW_PRINT("%s: driver not in IPS\n", __func__);
-+
-+		if (!rtw_is_surprise_removed(padapter)) {
-+#ifdef CONFIG_BT_COEXIST
-+			rtw_btcoex_IpsNotify(padapter, pwrctl->ips_mode_req);
-+#endif
-+#ifdef CONFIG_WOWLAN
-+			if (pwrctl->bSupportRemoteWakeup == _TRUE &&
-+			    pwrctl->wowlan_mode == _TRUE)
-+				RTW_PRINT("%s bSupportRemoteWakeup==_TRUE  do not run rtw_hal_deinit()\n", __FUNCTION__);
-+			else
-+#endif
-+			{
-+				/* amy modify 20120221 for power seq is different between driver open and ips */
-+				rtw_hal_deinit(padapter);
-+			}
-+			rtw_set_surprise_removed(padapter);
-+		}
-+
-+		padapter->bup = _FALSE;
-+
-+		RTW_INFO("<== "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
-+	} else {
-+		RTW_INFO("%s: bup==_FALSE\n", __FUNCTION__);
-+	}
-+	rtw_cancel_all_timer(padapter);
-+}
-+
-+int rtw_suspend_free_assoc_resource(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+#ifdef CONFIG_P2P
-+	struct wifidirect_info	*pwdinfo = &padapter->wdinfo;
-+#endif /* CONFIG_P2P */
-+
-+	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
-+
-+	if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) {
-+		if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
-+			&& check_fwstate(pmlmepriv, WIFI_ASOC_STATE)
-+			#ifdef CONFIG_P2P
-+			&& (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
-+				#if defined(CONFIG_IOCTL_CFG80211) && RTW_P2P_GROUP_INTERFACE
-+				|| rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)
-+				#endif
-+				)
-+			#endif /* CONFIG_P2P */
-+		) {
-+			RTW_INFO("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n", __FUNCTION__,
-+				pmlmepriv->cur_network.network.Ssid.Ssid,
-+				MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
-+				pmlmepriv->cur_network.network.Ssid.SsidLength,
-+				pmlmepriv->assoc_ssid.SsidLength);
-+			rtw_set_to_roam(padapter, 1);
-+		}
-+	}
-+
-+	if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
-+		rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY);
-+		/* s2-2.  indicate disconnect to os */
-+		rtw_indicate_disconnect(padapter, 0, _FALSE);
-+	}
-+#ifdef CONFIG_AP_MODE
-+	else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter))
-+		rtw_sta_flush(padapter, _TRUE);
-+#endif
-+
-+	/* s2-3. */
-+	rtw_free_assoc_resources(padapter, _TRUE);
-+
-+	/* s2-4. */
-+	rtw_free_network_queue(padapter, _TRUE);
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY)) {
-+		RTW_PRINT("%s: fw_under_survey\n", __func__);
-+		rtw_indicate_scan_done(padapter, 1);
-+		clr_fwstate(pmlmepriv, WIFI_UNDER_SURVEY);
-+	}
-+
-+	if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) {
-+		RTW_PRINT("%s: fw_under_linking\n", __FUNCTION__);
-+		rtw_indicate_disconnect(padapter, 0, _FALSE);
-+	}
-+
-+	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
-+	return _SUCCESS;
-+}
-+
-+#ifdef CONFIG_WOWLAN
-+int rtw_suspend_wow(_adapter *padapter)
-+{
-+	u8 ch, bw, offset;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct wowlan_ioctl_param poidparam;
-+	int ret = _SUCCESS;
-+	u8 en = _TRUE, i;
-+	struct registry_priv *registry_par = &padapter->registrypriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+	_adapter *iface = NULL;
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
-+
-+	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
-+
-+
-+	RTW_INFO("wowlan_mode: %d\n", pwrpriv->wowlan_mode);
-+	RTW_INFO("wowlan_pno_enable: %d\n", pwrpriv->wowlan_pno_enable);
-+#ifdef CONFIG_P2P_WOWLAN
-+	RTW_INFO("wowlan_p2p_enable: %d\n", pwrpriv->wowlan_p2p_enable);
-+#endif
-+
-+	if (pwrpriv->wowlan_mode == _TRUE) {
-+		rtw_mi_netif_stop_queue(padapter);
-+		#ifdef CONFIG_CONCURRENT_MODE
-+		rtw_mi_buddy_netif_carrier_off(padapter);
-+		#endif
-+
-+		/* 0. Power off LED */
-+		rtw_led_control(padapter, LED_CTL_POWER_OFF);
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+		/* 2.only for SDIO disable interrupt */
-+		rtw_intf_stop(padapter);
-+
-+		/* 2.1 clean interrupt */
-+		rtw_hal_clear_interrupt(padapter);
-+#endif /* CONFIG_SDIO_HCI */
-+		
-+		/* enable ac lifetime during scan to avoid txfifo not empty. */
-+		dvobj->lifetime_en = rtw_read8(padapter, 0x426);
-+		dvobj->pkt_lifetime = rtw_read32(padapter, 0x4c0);
-+		rtw_write8(padapter, 0x426, rtw_read8(padapter, 0x426) | 0x0f);
-+		if(hal_spec->tx_aclt_unit_factor == 1) {
-+			rtw_write16(padapter, 0x4c0, 0x1000);	// unit: 32us. 131ms 
-+			rtw_write16(padapter, 0x4c0 + 2 , 0x1000);	// unit: 32us. 131ms
-+		} else {
-+			rtw_write16(padapter, 0x4c0, 0x0200);	// unit: 256us. 131ms 
-+			rtw_write16(padapter, 0x4c0 + 2 , 0x0200);	// unit: 256us. 131ms
-+		}
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			if ((iface) && rtw_is_adapter_up(iface)) {
-+				rtw_write_port_cancel(iface);
-+				RTW_INFO(ADPT_FMT " write port cancel\n", ADPT_ARG(iface));
-+			}
-+		}
-+		RTW_INFO("lifetime_en=%x, pkt_lifetime=%x\n", rtw_read8(padapter, 0x426), rtw_read32(padapter, 0x4c0));
-+		rtw_msleep_os(200);
-+		
-+		/* 1. stop thread */
-+		rtw_set_drv_stopped(padapter);	/*for stop thread*/
-+		rtw_mi_stop_drv_threads(padapter);
-+
-+		rtw_clr_drv_stopped(padapter);	/*for 32k command*/
-+
-+		/* #ifdef CONFIG_LPS */
-+		/* rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN"); */
-+		/* #endif */
-+
-+		#ifdef CONFIG_SDIO_HCI
-+		/* 2.2 free irq */
-+		#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
-+		sdio_free_irq(adapter_to_dvobj(padapter));
-+		#endif
-+		#endif/*CONFIG_SDIO_HCI*/
-+
-+#ifdef CONFIG_RUNTIME_PORT_SWITCH
-+		if (rtw_port_switch_chk(padapter)) {
-+			RTW_INFO(" ### PORT SWITCH ###\n");
-+			rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
-+		}
-+#endif
-+		if(registry_par->suspend_type == FW_IPS_WRC)
-+			rtw_hal_set_hwreg(padapter, HW_VAR_VENDOR_WOW_MODE, &en);
-+#ifdef CONFIG_LPS
-+		rtw_wow_lps_level_decide(padapter, _TRUE);
-+#endif
-+		poidparam.subcode = WOWLAN_ENABLE;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);
-+		if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) {
-+			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
-+			    && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
-+				RTW_INFO("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n", __FUNCTION__,
-+					pmlmepriv->cur_network.network.Ssid.Ssid,
-+					MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
-+					pmlmepriv->cur_network.network.Ssid.SsidLength,
-+					 pmlmepriv->assoc_ssid.SsidLength);
-+
-+				rtw_set_to_roam(padapter, 0);
-+			}
-+		}
-+
-+		RTW_PRINT("%s: wowmode suspending\n", __func__);
-+
-+		if (check_fwstate(pmlmepriv, WIFI_UNDER_SURVEY) == _TRUE) {
-+			RTW_PRINT("%s: fw_under_survey\n", __func__);
-+			rtw_indicate_scan_done(padapter, 1);
-+			clr_fwstate(pmlmepriv, WIFI_UNDER_SURVEY);
-+		}
-+
-+		if (rtw_mi_check_status(padapter, MI_LINKED)) {
-+			ch =  rtw_mi_get_union_chan(padapter);
-+			bw = rtw_mi_get_union_bw(padapter);
-+			offset = rtw_mi_get_union_offset(padapter);
-+			RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n",
-+				 FUNC_ADPT_ARG(padapter), ch, bw, offset);
-+			set_channel_bwmode(padapter, ch, offset, bw);
-+		}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+		rtw_mi_buddy_suspend_free_assoc_resource(padapter);
-+#endif
-+
-+#ifdef CONFIG_BT_COEXIST
-+		rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT);
-+#endif
-+
-+		if (pwrpriv->wowlan_pno_enable) {
-+			RTW_PRINT("%s: pno: %d\n", __func__,
-+				  pwrpriv->wowlan_pno_enable);
-+#ifdef CONFIG_FWLPS_IN_IPS
-+			rtw_set_fw_in_ips_mode(padapter, _TRUE);
-+#endif
-+		}
-+#ifdef CONFIG_LPS
-+		else {
-+			if(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) {
-+				rtw_set_ps_mode(padapter, pwrpriv->wowlan_power_mgmt, 0, 0, "WOWLAN");
-+			}
-+		}
-+#endif /* #ifdef CONFIG_LPS */
-+
-+	} else
-+		RTW_PRINT("%s: ### ERROR ### wowlan_mode=%d\n", __FUNCTION__, pwrpriv->wowlan_mode);
-+	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
-+	return ret;
-+}
-+#endif /* #ifdef CONFIG_WOWLAN */
-+
-+#ifdef CONFIG_AP_WOWLAN
-+int rtw_suspend_ap_wow(_adapter *padapter)
-+{
-+	u8 ch, bw, offset;
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct wowlan_ioctl_param poidparam;
-+	int ret = _SUCCESS;
-+
-+	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
-+
-+	pwrpriv->wowlan_ap_mode = _TRUE;
-+
-+	RTW_INFO("wowlan_ap_mode: %d\n", pwrpriv->wowlan_ap_mode);
-+
-+	rtw_mi_netif_stop_queue(padapter);
-+
-+	/* 0. Power off LED */
-+	rtw_led_control(padapter, LED_CTL_POWER_OFF);
-+#ifdef CONFIG_SDIO_HCI
-+	/* 2.only for SDIO disable interrupt*/
-+	rtw_intf_stop(padapter);
-+
-+	/* 2.1 clean interrupt */
-+	rtw_hal_clear_interrupt(padapter);
-+#endif /* CONFIG_SDIO_HCI */
-+
-+	/* 1. stop thread */
-+	rtw_set_drv_stopped(padapter);	/*for stop thread*/
-+	rtw_mi_stop_drv_threads(padapter);
-+	rtw_clr_drv_stopped(padapter);	/*for 32k command*/
-+
-+	#ifdef CONFIG_SDIO_HCI
-+	/* 2.2 free irq */
-+	#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
-+	sdio_free_irq(adapter_to_dvobj(padapter));
-+	#endif
-+	#endif/*CONFIG_SDIO_HCI*/
-+
-+#ifdef CONFIG_RUNTIME_PORT_SWITCH
-+	if (rtw_port_switch_chk(padapter)) {
-+		RTW_INFO(" ### PORT SWITCH ###\n");
-+		rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL);
-+	}
-+#endif
-+
-+	rtw_wow_lps_level_decide(padapter, _TRUE);
-+	poidparam.subcode = WOWLAN_AP_ENABLE;
-+	rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);
-+
-+	RTW_PRINT("%s: wowmode suspending\n", __func__);
-+
-+	if (rtw_mi_check_status(padapter, MI_LINKED)) {
-+		ch =  rtw_mi_get_union_chan(padapter);
-+		bw = rtw_mi_get_union_bw(padapter);
-+		offset = rtw_mi_get_union_offset(padapter);
-+		RTW_INFO("back to linked/linking union - ch:%u, bw:%u, offset:%u\n", ch, bw, offset);
-+		set_channel_bwmode(padapter, ch, offset, bw);
-+	}
-+
-+	/*FOR ONE AP - TODO :Multi-AP*/
-+	{
-+		int i;
-+		_adapter *iface;
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			if ((iface) && rtw_is_adapter_up(iface)) {
-+				if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE) == _FALSE)
-+					rtw_suspend_free_assoc_resource(iface);
-+			}
-+		}
-+
-+	}
-+
-+#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT);
-+#endif
-+
-+#ifdef CONFIG_LPS
-+	if(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) {
-+		rtw_set_ps_mode(padapter, pwrpriv->wowlan_power_mgmt, 0, 0, "AP-WOWLAN");
-+	}
-+#endif
-+
-+	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
-+	return ret;
-+}
-+#endif /* CONFIG_AP_WOWLAN */
-+
-+
-+int rtw_suspend_normal(_adapter *padapter)
-+{
-+	int ret = _SUCCESS;
-+
-+	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
-+
-+#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND);
-+#endif
-+	rtw_mi_netif_caroff_qstop(padapter);
-+
-+	rtw_mi_suspend_free_assoc_resource(padapter);
-+
-+	rtw_led_control(padapter, LED_CTL_POWER_OFF);
-+
-+	if ((rtw_hal_check_ips_status(padapter) == _TRUE)
-+	    || (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off))
-+		RTW_PRINT("%s: ### ERROR #### driver in IPS ####ERROR###!!!\n", __FUNCTION__);
-+
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	rtw_set_drv_stopped(padapter);	/*for stop thread*/
-+	rtw_stop_cmd_thread(padapter);
-+	rtw_drv_stop_vir_ifaces(adapter_to_dvobj(padapter));
-+#endif
-+	rtw_dev_unload(padapter);
-+
-+	#ifdef CONFIG_SDIO_HCI
-+	sdio_deinit(adapter_to_dvobj(padapter));
-+
-+	#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
-+	sdio_free_irq(adapter_to_dvobj(padapter));
-+	#endif
-+	#endif /*CONFIG_SDIO_HCI*/
-+
-+	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
-+	return ret;
-+}
-+
-+int rtw_suspend_common(_adapter *padapter)
-+{
-+	struct dvobj_priv *dvobj = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
-+#ifdef CONFIG_WOWLAN
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct registry_priv *registry_par = &padapter->registrypriv;
-+#endif
-+
-+	int ret = 0;
-+	systime start_time = rtw_get_current_time();
-+
-+	RTW_PRINT(" suspend start\n");
-+	RTW_INFO("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid);
-+
-+	pdbgpriv->dbg_suspend_cnt++;
-+
-+	pwrpriv->bInSuspend = _TRUE;
-+
-+	while (pwrpriv->bips_processing == _TRUE)
-+		rtw_msleep_os(1);
-+
-+#ifdef CONFIG_IOL_READ_EFUSE_MAP
-+	if (!padapter->bup) {
-+		u8 bMacPwrCtrlOn = _FALSE;
-+		rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
-+		if (bMacPwrCtrlOn)
-+			rtw_hal_power_off(padapter);
-+	}
-+#endif
-+
-+	if ((!padapter->bup) || RTW_CANNOT_RUN(padapter)) {
-+		RTW_INFO("%s bup=%d bDriverStopped=%s bSurpriseRemoved = %s\n", __func__
-+			 , padapter->bup
-+			 , rtw_is_drv_stopped(padapter) ? "True" : "False"
-+			, rtw_is_surprise_removed(padapter) ? "True" : "False");
-+		pdbgpriv->dbg_suspend_error_cnt++;
-+		goto exit;
-+	}
-+	rtw_mi_scan_abort(padapter, _TRUE);
-+	rtw_ps_deny(padapter, PS_DENY_SUSPEND);
-+
-+	rtw_mi_cancel_all_timer(padapter);
-+	LeaveAllPowerSaveModeDirect(padapter);
-+
-+	rtw_ps_deny_cancel(padapter, PS_DENY_SUSPEND);
-+
-+	if (rtw_mi_check_status(padapter, MI_AP_MODE) == _FALSE) {
-+#ifdef CONFIG_WOWLAN
-+		if (WOWLAN_IS_STA_MIX_MODE(padapter))
-+			pwrpriv->wowlan_mode = _TRUE;
-+		else if ( registry_par->wowlan_enable && check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
-+			pwrpriv->wowlan_mode = _TRUE;
-+		else if (pwrpriv->wowlan_pno_enable == _TRUE)
-+			pwrpriv->wowlan_mode |= pwrpriv->wowlan_pno_enable;
-+
-+#ifdef CONFIG_P2P_WOWLAN
-+		if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE) || P2P_ROLE_DISABLE != padapter->wdinfo.role)
-+			pwrpriv->wowlan_p2p_mode = _TRUE;
-+		if (_TRUE == pwrpriv->wowlan_p2p_mode)
-+			pwrpriv->wowlan_mode |= pwrpriv->wowlan_p2p_mode;
-+#endif /* CONFIG_P2P_WOWLAN */
-+
-+		if (pwrpriv->wowlan_mode == _TRUE)
-+			rtw_suspend_wow(padapter);
-+		else
-+#endif /* CONFIG_WOWLAN */
-+			rtw_suspend_normal(padapter);
-+	} else if (rtw_mi_check_status(padapter, MI_AP_MODE)) {
-+#ifdef CONFIG_AP_WOWLAN
-+		rtw_suspend_ap_wow(padapter);
-+#else
-+		rtw_suspend_normal(padapter);
-+#endif /*CONFIG_AP_WOWLAN*/
-+	}
-+
-+
-+	RTW_PRINT("rtw suspend success in %d ms\n",
-+		  rtw_get_passing_time_ms(start_time));
-+
-+exit:
-+	RTW_INFO("<===  %s return %d.............. in %dms\n", __FUNCTION__
-+		 , ret, rtw_get_passing_time_ms(start_time));
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_WOWLAN
-+int rtw_resume_process_wow(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+	struct wowlan_ioctl_param poidparam;
-+	struct sta_info	*psta = NULL;
-+	struct registry_priv  *registry_par = &padapter->registrypriv;
-+	int ret = _SUCCESS;
-+	u8 en = _FALSE;
-+
-+	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
-+
-+	if (padapter) {
-+		pwrpriv = adapter_to_pwrctl(padapter);
-+	} else {
-+		pdbgpriv->dbg_resume_error_cnt++;
-+		ret = -1;
-+		goto exit;
-+	}
-+
-+	if (RTW_CANNOT_RUN(padapter)) {
-+		RTW_INFO("%s pdapter %p bDriverStopped %s bSurpriseRemoved %s\n"
-+			 , __func__, padapter
-+			 , rtw_is_drv_stopped(padapter) ? "True" : "False"
-+			, rtw_is_surprise_removed(padapter) ? "True" : "False");
-+		goto exit;
-+	}
-+
-+	pwrpriv->wowlan_in_resume = _TRUE;
-+#ifdef CONFIG_PNO_SUPPORT
-+#ifdef CONFIG_FWLPS_IN_IPS
-+	if (pwrpriv->wowlan_pno_enable)
-+		rtw_set_fw_in_ips_mode(padapter, _FALSE);
-+#endif /* CONFIG_FWLPS_IN_IPS */
-+#endif/* CONFIG_PNO_SUPPORT */
-+
-+	if (pwrpriv->wowlan_mode == _TRUE) {
-+#ifdef CONFIG_LPS
-+		if(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) {
-+			rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN");
-+			rtw_wow_lps_level_decide(padapter, _FALSE);
-+		}
-+#endif /* CONFIG_LPS */
-+
-+		rtw_write8(padapter, 0x426, psdpriv->lifetime_en);
-+		rtw_write32(padapter, 0x4c0, psdpriv->pkt_lifetime);
-+
-+		pwrpriv->bFwCurrentInPSMode = _FALSE;
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI)
-+		rtw_mi_intf_stop(padapter);
-+		rtw_hal_clear_interrupt(padapter);
-+#endif
-+
-+		#ifdef CONFIG_SDIO_HCI
-+		#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
-+		if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) {
-+			ret = -1;
-+			goto exit;
-+		}
-+		#endif
-+		#endif/*CONFIG_SDIO_HCI*/
-+
-+		/* Disable WOW, set H2C command */
-+		poidparam.subcode = WOWLAN_DISABLE;
-+		rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+		rtw_mi_buddy_reset_drv_sw(padapter);
-+#endif
-+
-+		psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
-+		if (psta)
-+			set_sta_rate(padapter, psta);
-+
-+
-+		rtw_clr_drv_stopped(padapter);
-+		RTW_INFO("%s: wowmode resuming, DriverStopped:%s\n", __func__, rtw_is_drv_stopped(padapter) ? "True" : "False");
-+		
-+		if(registry_par->suspend_type == FW_IPS_WRC)
-+			rtw_hal_set_hwreg(padapter, HW_VAR_VENDOR_WOW_MODE, &en);
-+		
-+		rtw_mi_start_drv_threads(padapter);
-+
-+		rtw_mi_intf_start(padapter);
-+		
-+		if(registry_par->suspend_type == FW_IPS_DISABLE_BBRF && !check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
-+			if (!rtw_is_surprise_removed(padapter)) {
-+				rtw_hal_deinit(padapter);
-+				rtw_hal_init(padapter);
-+			}
-+			RTW_INFO("FW_IPS_DISABLE_BBRF hal deinit, hal init \n");
-+		}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+		rtw_mi_buddy_netif_carrier_on(padapter);
-+#endif
-+
-+		/* start netif queue */
-+		rtw_mi_netif_wake_queue(padapter);
-+
-+	} else
-+
-+		RTW_PRINT("%s: ### ERROR ### wowlan_mode=%d\n", __FUNCTION__, pwrpriv->wowlan_mode);
-+
-+	if (padapter->pid[1] != 0) {
-+		RTW_INFO("pid[1]:%d\n", padapter->pid[1]);
-+		rtw_signal_process(padapter->pid[1], SIGUSR2);
-+	}
-+
-+	if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) {
-+		if (pwrpriv->wowlan_wake_reason == FW_DECISION_DISCONNECT ||
-+		    pwrpriv->wowlan_wake_reason == RX_DISASSOC||
-+		    pwrpriv->wowlan_wake_reason == RX_DEAUTH) {
-+
-+			RTW_INFO("%s: disconnect reason: %02x\n", __func__,
-+				 pwrpriv->wowlan_wake_reason);
-+			rtw_indicate_disconnect(padapter, 0, _FALSE);
-+
-+			rtw_sta_media_status_rpt(padapter,
-+					 rtw_get_stainfo(&padapter->stapriv,
-+					 get_bssid(&padapter->mlmepriv)), 0);
-+
-+			rtw_free_assoc_resources(padapter, _TRUE);
-+			pmlmeinfo->state = WIFI_FW_NULL_STATE;
-+
-+		} else {
-+			RTW_INFO("%s: do roaming\n", __func__);
-+			rtw_roaming(padapter, NULL);
-+		}
-+	}
-+
-+	if (pwrpriv->wowlan_mode == _TRUE) {
-+		pwrpriv->bips_processing = _FALSE;
-+		_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
-+#ifndef CONFIG_IPS_CHECK_IN_WD
-+		rtw_set_pwr_state_check_timer(pwrpriv);
-+#endif
-+	} else
-+		RTW_PRINT("do not reset timer\n");
-+
-+	pwrpriv->wowlan_mode = _FALSE;
-+
-+	/* Power On LED */
-+#ifdef CONFIG_RTW_SW_LED
-+
-+	if (pwrpriv->wowlan_wake_reason == RX_DISASSOC||
-+	    pwrpriv->wowlan_wake_reason == RX_DEAUTH||
-+	    pwrpriv->wowlan_wake_reason == FW_DECISION_DISCONNECT)
-+		rtw_led_control(padapter, LED_CTL_NO_LINK);
-+	else
-+		rtw_led_control(padapter, LED_CTL_LINK);
-+#endif
-+	/* clean driver side wake up reason. */
-+	pwrpriv->wowlan_last_wake_reason = pwrpriv->wowlan_wake_reason;
-+	pwrpriv->wowlan_wake_reason = 0;
-+
-+#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME);
-+#endif /* CONFIG_BT_COEXIST */
-+
-+exit:
-+	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
-+	return ret;
-+}
-+#endif /* #ifdef CONFIG_WOWLAN */
-+
-+#ifdef CONFIG_AP_WOWLAN
-+int rtw_resume_process_ap_wow(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+	struct wowlan_ioctl_param poidparam;
-+	struct sta_info	*psta = NULL;
-+	int ret = _SUCCESS;
-+	u8 ch, bw, offset;
-+
-+	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
-+
-+	if (padapter) {
-+		pwrpriv = adapter_to_pwrctl(padapter);
-+	} else {
-+		pdbgpriv->dbg_resume_error_cnt++;
-+		ret = -1;
-+		goto exit;
-+	}
-+
-+
-+#ifdef CONFIG_LPS
-+	if(pwrpriv->wowlan_power_mgmt != PS_MODE_ACTIVE) {
-+		rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "AP-WOWLAN");
-+		rtw_wow_lps_level_decide(padapter, _FALSE);
-+	}
-+#endif /* CONFIG_LPS */
-+
-+	pwrpriv->bFwCurrentInPSMode = _FALSE;
-+
-+	rtw_hal_disable_interrupt(padapter);
-+
-+	rtw_hal_clear_interrupt(padapter);
-+
-+	#ifdef CONFIG_SDIO_HCI
-+	#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
-+	if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) {
-+		ret = -1;
-+		goto exit;
-+	}
-+	#endif
-+	#endif/*CONFIG_SDIO_HCI*/
-+	/* Disable WOW, set H2C command */
-+	poidparam.subcode = WOWLAN_AP_DISABLE;
-+	rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam);
-+	pwrpriv->wowlan_ap_mode = _FALSE;
-+
-+	rtw_clr_drv_stopped(padapter);
-+	RTW_INFO("%s: wowmode resuming, DriverStopped:%s\n", __func__, rtw_is_drv_stopped(padapter) ? "True" : "False");
-+
-+	rtw_mi_start_drv_threads(padapter);
-+
-+	if (rtw_mi_check_status(padapter, MI_LINKED)) {
-+		ch =  rtw_mi_get_union_chan(padapter);
-+		bw = rtw_mi_get_union_bw(padapter);
-+		offset = rtw_mi_get_union_offset(padapter);
-+		RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", FUNC_ADPT_ARG(padapter), ch, bw, offset);
-+		set_channel_bwmode(padapter, ch, offset, bw);
-+	}
-+
-+	/*FOR ONE AP - TODO :Multi-AP*/
-+	{
-+		int i;
-+		_adapter *iface;
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			if ((iface) && rtw_is_adapter_up(iface)) {
-+				if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE | WIFI_ASOC_STATE))
-+					rtw_reset_drv_sw(iface);
-+			}
-+		}
-+
-+	}
-+	rtw_mi_intf_start(padapter);
-+
-+	/* start netif queue */
-+	rtw_mi_netif_wake_queue(padapter);
-+
-+	if (padapter->pid[1] != 0) {
-+		RTW_INFO("pid[1]:%d\n", padapter->pid[1]);
-+		rtw_signal_process(padapter->pid[1], SIGUSR2);
-+	}
-+
-+#ifdef CONFIG_RESUME_IN_WORKQUEUE
-+	/* rtw_unlock_suspend(); */
-+#endif /* CONFIG_RESUME_IN_WORKQUEUE */
-+
-+	pwrpriv->bips_processing = _FALSE;
-+	_set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
-+#ifndef CONFIG_IPS_CHECK_IN_WD
-+	rtw_set_pwr_state_check_timer(pwrpriv);
-+#endif
-+	/* clean driver side wake up reason. */
-+	pwrpriv->wowlan_wake_reason = 0;
-+
-+#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME);
-+#endif /* CONFIG_BT_COEXIST */
-+
-+	/* Power On LED */
-+#ifdef CONFIG_RTW_SW_LED
-+
-+	rtw_led_control(padapter, LED_CTL_LINK);
-+#endif
-+exit:
-+	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
-+	return ret;
-+}
-+#endif /* #ifdef CONFIG_APWOWLAN */
-+
-+void rtw_mi_resume_process_normal(_adapter *padapter)
-+{
-+	int i;
-+	_adapter *iface;
-+	struct mlme_priv *pmlmepriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if ((iface) && rtw_is_adapter_up(iface)) {
-+			pmlmepriv = &iface->mlmepriv;
-+
-+			if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
-+				RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv));
-+
-+				if (rtw_chk_roam_flags(iface, RTW_ROAM_ON_RESUME))
-+					rtw_roaming(iface, NULL);
-+
-+			}
-+#ifdef CONFIG_AP_MODE
-+			else if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {
-+				RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(iface), MLME_IS_AP(iface) ? "AP" : "MESH");
-+				rtw_ap_restore_network(iface);
-+			}
-+#endif
-+			else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE))
-+				RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv));
-+			else
-+				RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv));
-+		}
-+	}
-+}
-+
-+int rtw_resume_process_normal(_adapter *padapter)
-+{
-+	struct net_device *pnetdev;
-+	struct pwrctrl_priv *pwrpriv;
-+	struct dvobj_priv *psdpriv;
-+	struct debug_priv *pdbgpriv;
-+
-+	int ret = _SUCCESS;
-+
-+	if (!padapter) {
-+		ret = -1;
-+		goto exit;
-+	}
-+
-+	pnetdev = padapter->pnetdev;
-+	pwrpriv = adapter_to_pwrctl(padapter);
-+	psdpriv = padapter->dvobj;
-+	pdbgpriv = &psdpriv->drv_dbg;
-+
-+	RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter));
-+
-+	#ifdef CONFIG_SDIO_HCI
-+	/* interface init */
-+	if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) {
-+		ret = -1;
-+		goto exit;
-+	}
-+	#endif/*CONFIG_SDIO_HCI*/
-+
-+	rtw_clr_surprise_removed(padapter);
-+	rtw_hal_disable_interrupt(padapter);
-+
-+	#ifdef CONFIG_SDIO_HCI
-+	#if !(CONFIG_RTW_SDIO_KEEP_IRQ)
-+	if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) {
-+		ret = -1;
-+		goto exit;
-+	}
-+	#endif
-+	#endif/*CONFIG_SDIO_HCI*/
-+
-+	rtw_mi_reset_drv_sw(padapter);
-+
-+	pwrpriv->bkeepfwalive = _FALSE;
-+
-+	RTW_INFO("bkeepfwalive(%x)\n", pwrpriv->bkeepfwalive);
-+	if (pm_netdev_open(pnetdev, _TRUE) != 0) {
-+		ret = -1;
-+		pdbgpriv->dbg_resume_error_cnt++;
-+		goto exit;
-+	}
-+
-+	rtw_mi_netif_caron_qstart(padapter);
-+
-+	if (padapter->pid[1] != 0) {
-+		RTW_INFO("pid[1]:%d\n", padapter->pid[1]);
-+		rtw_signal_process(padapter->pid[1], SIGUSR2);
-+	}
-+
-+#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME);
-+#endif /* CONFIG_BT_COEXIST */
-+
-+	rtw_mi_resume_process_normal(padapter);
-+
-+#ifdef CONFIG_RESUME_IN_WORKQUEUE
-+	/* rtw_unlock_suspend(); */
-+#endif /* CONFIG_RESUME_IN_WORKQUEUE */
-+	RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter));
-+
-+exit:
-+	return ret;
-+}
-+
-+int rtw_resume_common(_adapter *padapter)
-+{
-+	int ret = 0;
-+	systime start_time = rtw_get_current_time();
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+
-+	if (pwrpriv == NULL)
-+		return 0;
-+
-+	if (pwrpriv->bInSuspend == _FALSE)
-+		return 0;
-+
-+	RTW_PRINT("resume start\n");
-+	RTW_INFO("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid);
-+
-+	if (rtw_mi_check_status(padapter, MI_AP_MODE) == _FALSE) {
-+#ifdef CONFIG_WOWLAN
-+		if (pwrpriv->wowlan_mode == _TRUE)
-+			rtw_resume_process_wow(padapter);
-+		else
-+#endif
-+			rtw_resume_process_normal(padapter);
-+
-+	} else if (rtw_mi_check_status(padapter, MI_AP_MODE)) {
-+#ifdef CONFIG_AP_WOWLAN
-+		rtw_resume_process_ap_wow(padapter);
-+#else
-+		rtw_resume_process_normal(padapter);
-+#endif /* CONFIG_AP_WOWLAN */
-+	}
-+
-+	pwrpriv->bInSuspend = _FALSE;
-+	pwrpriv->wowlan_in_resume = _FALSE;
-+
-+	RTW_PRINT("%s:%d in %d ms\n", __FUNCTION__ , ret,
-+		  rtw_get_passing_time_ms(start_time));
-+
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_GPIO_API
-+u8 rtw_get_gpio(struct net_device *netdev, u8 gpio_num)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
-+	return rtw_hal_get_gpio(adapter, gpio_num);
-+}
-+EXPORT_SYMBOL(rtw_get_gpio);
-+
-+int  rtw_set_gpio_output_value(struct net_device *netdev, u8 gpio_num, bool isHigh)
-+{
-+	u8 direction = 0;
-+	u8 res = -1;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
-+	return rtw_hal_set_gpio_output_value(adapter, gpio_num, isHigh);
-+}
-+EXPORT_SYMBOL(rtw_set_gpio_output_value);
-+
-+int rtw_config_gpio(struct net_device *netdev, u8 gpio_num, bool isOutput)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
-+	return rtw_hal_config_gpio(adapter, gpio_num, isOutput);
-+}
-+EXPORT_SYMBOL(rtw_config_gpio);
-+int rtw_register_gpio_interrupt(struct net_device *netdev, int gpio_num, void(*callback)(u8 level))
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
-+	return rtw_hal_register_gpio_interrupt(adapter, gpio_num, callback);
-+}
-+EXPORT_SYMBOL(rtw_register_gpio_interrupt);
-+
-+int rtw_disable_gpio_interrupt(struct net_device *netdev, int gpio_num)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(netdev);
-+	return rtw_hal_disable_gpio_interrupt(adapter, gpio_num);
-+}
-+EXPORT_SYMBOL(rtw_disable_gpio_interrupt);
-+
-+#endif /* #ifdef CONFIG_GPIO_API */
-+
-+#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
-+
-+int rtw_vendor_ie_get_api(struct net_device *dev, int ie_num, char *extra,
-+		u16 extra_len)
-+{
-+	int ret = 0;
-+
-+	ret = rtw_vendor_ie_get_raw_data(dev, ie_num, extra, extra_len);
-+	return ret;
-+}
-+EXPORT_SYMBOL(rtw_vendor_ie_get_api);
-+
-+int rtw_vendor_ie_set_api(struct net_device *dev, char *extra)
-+{
-+	return rtw_vendor_ie_set(dev, NULL, NULL, extra);
-+}
-+EXPORT_SYMBOL(rtw_vendor_ie_set_api);
-+
-+#endif
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/recv_linux.c b/drivers/staging/rtl8723cs/os_dep/linux/recv_linux.c
-new file mode 100644
-index 000000000000..d1a908a07437
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/recv_linux.c
-@@ -0,0 +1,734 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _RECV_OSDEP_C_
-+
-+#include <drv_types.h>
-+
-+int rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pcloneframe, _pkt *pskb)
-+{
-+	int res = _SUCCESS;
-+	_pkt	*pkt_copy = NULL;
-+
-+	if (pskb == NULL) {
-+		RTW_INFO("%s [WARN] skb == NULL, drop frag frame\n", __func__);
-+		return _FAIL;
-+	}
-+#if 1
-+	pkt_copy = rtw_skb_copy(pskb);
-+
-+	if (pkt_copy == NULL) {
-+		RTW_INFO("%s [WARN] rtw_skb_copy fail , drop frag frame\n", __func__);
-+		return _FAIL;
-+	}
-+#else
-+	pkt_copy = rtw_skb_clone(pskb);
-+
-+	if (pkt_copy == NULL) {
-+		RTW_INFO("%s [WARN] rtw_skb_clone fail , drop frag frame\n", __func__);
-+		return _FAIL;
-+	}
-+#endif
-+	pkt_copy->dev = padapter->pnetdev;
-+
-+	pcloneframe->u.hdr.pkt = pkt_copy;
-+	pcloneframe->u.hdr.rx_head = pkt_copy->head;
-+	pcloneframe->u.hdr.rx_data = pkt_copy->data;
-+	pcloneframe->u.hdr.rx_end = skb_end_pointer(pkt_copy);
-+	pcloneframe->u.hdr.rx_tail = skb_tail_pointer(pkt_copy);
-+	pcloneframe->u.hdr.len = pkt_copy->len;
-+
-+	return res;
-+}
-+
-+int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb)
-+{
-+	int res = _SUCCESS;
-+	u8	shift_sz = 0;
-+	u32	skb_len, alloc_sz;
-+	_pkt	*pkt_copy = NULL;
-+	struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
-+
-+
-+	if (pdata == NULL) {
-+		precvframe->u.hdr.pkt = NULL;
-+		res = _FAIL;
-+		return res;
-+	}
-+
-+
-+	/*	Modified by Albert 20101213 */
-+	/*	For 8 bytes IP header alignment. */
-+	shift_sz = pattrib->qos ? 6 : 0; /*	Qos data, wireless lan header length is 26 */
-+
-+	skb_len = pattrib->pkt_len;
-+
-+	/* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */
-+	/* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */
-+	if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) {
-+		/* alloc_sz = 1664;	 */ /* 1664 is 128 alignment. */
-+		alloc_sz = (skb_len <= 1650) ? 1664 : (skb_len + 14);
-+	} else {
-+		alloc_sz = skb_len;
-+		/*	6 is for IP header 8 bytes alignment in QoS packet case. */
-+		/*	8 is for skb->data 4 bytes alignment. */
-+		alloc_sz += 14;
-+	}
-+
-+	pkt_copy = rtw_skb_alloc(alloc_sz);
-+
-+	if (pkt_copy) {
-+		pkt_copy->dev = padapter->pnetdev;
-+		pkt_copy->len = skb_len;
-+		precvframe->u.hdr.pkt = pkt_copy;
-+		precvframe->u.hdr.rx_head = pkt_copy->head;
-+		precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz;
-+		skb_reserve(pkt_copy, 8 - ((SIZE_PTR)(pkt_copy->data) & 7));  /* force pkt_copy->data at 8-byte alignment address */
-+		skb_reserve(pkt_copy, shift_sz);/* force ip_hdr at 8-byte alignment address according to shift_sz. */
-+		_rtw_memcpy(pkt_copy->data, pdata, skb_len);
-+		precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;
-+	} else {
-+#if 0
-+		{
-+			rtw_free_recvframe(precvframe_if2, &precvpriv->free_recv_queue);
-+			rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
-+
-+			/* The case of can't allocate skb is serious and may never be recovered,
-+			 once bDriverStopped is enable, this task should be stopped.*/
-+			if (!rtw_is_drv_stopped(secondary_padapter))
-+#ifdef PLATFORM_LINUX
-+				tasklet_schedule(&precvpriv->recv_tasklet);
-+#endif
-+			return ret;
-+		}
-+
-+#endif
-+
-+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
-+		RTW_INFO("%s:can not allocate memory for skb copy\n", __func__);
-+
-+		precvframe->u.hdr.pkt = NULL;
-+
-+		/* rtw_free_recvframe(precvframe, pfree_recv_queue); */
-+		/*exit_rtw_os_recv_resource_alloc;*/
-+
-+		res = _FAIL;
-+#else
-+		if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) {
-+			RTW_INFO("%s: alloc_skb fail , drop frag frame\n", __FUNCTION__);
-+			/* rtw_free_recvframe(precvframe, pfree_recv_queue); */
-+			res = _FAIL;
-+			goto exit_rtw_os_recv_resource_alloc;
-+		}
-+
-+		if (pskb == NULL) {
-+			res = _FAIL;
-+			goto exit_rtw_os_recv_resource_alloc;
-+		}
-+
-+		precvframe->u.hdr.pkt = rtw_skb_clone(pskb);
-+		if (precvframe->u.hdr.pkt) {
-+			precvframe->u.hdr.pkt->dev = padapter->pnetdev;
-+			precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pdata;
-+			precvframe->u.hdr.rx_end =  pdata + alloc_sz;
-+		} else {
-+			RTW_INFO("%s: rtw_skb_clone fail\n", __FUNCTION__);
-+			/* rtw_free_recvframe(precvframe, pfree_recv_queue); */
-+			/*exit_rtw_os_recv_resource_alloc;*/
-+			res = _FAIL;
-+		}
-+#endif
-+	}
-+
-+exit_rtw_os_recv_resource_alloc:
-+
-+	return res;
-+
-+}
-+
-+void rtw_os_free_recvframe(union recv_frame *precvframe)
-+{
-+	if (precvframe->u.hdr.pkt) {
-+		rtw_os_pkt_free(precvframe->u.hdr.pkt);
-+		precvframe->u.hdr.pkt = NULL;
-+	}
-+}
-+
-+/* init os related resource in struct recv_priv */
-+int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter)
-+{
-+	int	res = _SUCCESS;
-+
-+
-+#ifdef CONFIG_RTW_NAPI
-+	skb_queue_head_init(&precvpriv->rx_napi_skb_queue);
-+#endif /* CONFIG_RTW_NAPI */
-+
-+	return res;
-+}
-+
-+/* alloc os related resource in union recv_frame */
-+int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe)
-+{
-+	int	res = _SUCCESS;
-+
-+	precvframe->u.hdr.pkt = NULL;
-+
-+	return res;
-+}
-+
-+/* free os related resource in union recv_frame */
-+void rtw_os_recv_resource_free(struct recv_priv *precvpriv)
-+{
-+	sint i;
-+	union recv_frame *precvframe;
-+	precvframe = (union recv_frame *) precvpriv->precv_frame_buf;
-+
-+
-+#ifdef CONFIG_RTW_NAPI
-+	if (skb_queue_len(&precvpriv->rx_napi_skb_queue))
-+		RTW_WARN("rx_napi_skb_queue not empty\n");
-+	rtw_skb_queue_purge(&precvpriv->rx_napi_skb_queue);
-+#endif /* CONFIG_RTW_NAPI */
-+
-+	for (i = 0; i < NR_RECVFRAME; i++) {
-+		rtw_os_free_recvframe(precvframe);
-+		precvframe++;
-+	}
-+}
-+
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+#if !defined(CONFIG_RTL8822B) && !defined(CONFIG_RTL8822C)
-+#ifdef CONFIG_SDIO_RX_COPY
-+static int sdio_init_recvbuf_with_skb(struct recv_priv *recvpriv, struct recv_buf *rbuf, u32 size)
-+{
-+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
-+	if (RBUF_IS_PREALLOC(rbuf)) {
-+		rbuf->pskb = rtw_alloc_skb_premem(size);
-+		if (!rbuf->pskb) {
-+			RTW_WARN("%s: Fail to get pre-alloc skb! size=%d\n", __func__, size);
-+			return _FAIL;
-+		}
-+		skb_set_tail_pointer(rbuf->pskb, 0); /* TODO: do this in RTKM */
-+	} else
-+#else
-+	{
-+		SIZE_PTR tmpaddr = 0;
-+		SIZE_PTR alignment = 0;
-+
-+		rbuf->pskb = rtw_skb_alloc(size + RECVBUFF_ALIGN_SZ);
-+		if (!rbuf->pskb)
-+			return _FAIL;
-+
-+		tmpaddr = (SIZE_PTR)rbuf->pskb->data;
-+		alignment = tmpaddr & (RECVBUFF_ALIGN_SZ - 1);
-+		skb_reserve(rbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
-+	}
-+#endif
-+
-+	rbuf->pskb->dev = recvpriv->adapter->pnetdev;
-+
-+	/* init recvbuf */
-+	rbuf->phead = rbuf->pskb->head;
-+	rbuf->pdata = rbuf->pskb->data;
-+	rbuf->ptail = skb_tail_pointer(rbuf->pskb);
-+	rbuf->pend = skb_end_pointer(rbuf->pskb);
-+	rbuf->len = 0;
-+
-+	return _SUCCESS;
-+}
-+#endif /* CONFIG_SDIO_RX_COPY */
-+#endif /* !defined(CONFIG_RTL8822B) && !defined(CONFIG_RTL8822C) */
-+#endif /* defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) */
-+
-+/* alloc os related resource in struct recv_buf */
-+int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf, u32 size)
-+{
-+	int res = _SUCCESS;
-+
-+#ifdef CONFIG_USB_HCI
-+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct usb_device	*pusbd = pdvobjpriv->pusbdev;
-+#endif
-+
-+	precvbuf->irp_pending = _FALSE;
-+	precvbuf->purb = usb_alloc_urb(0, GFP_KERNEL);
-+	if (precvbuf->purb == NULL)
-+		res = _FAIL;
-+
-+	precvbuf->pskb = NULL;
-+
-+	precvbuf->pallocated_buf  = precvbuf->pbuf = NULL;
-+
-+	precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pend = NULL;
-+
-+	precvbuf->transfer_len = 0;
-+
-+	precvbuf->len = 0;
-+
-+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
-+	precvbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)size, &precvbuf->dma_transfer_addr);
-+	precvbuf->pbuf = precvbuf->pallocated_buf;
-+	if (precvbuf->pallocated_buf == NULL)
-+		return _FAIL;
-+#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
-+
-+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	#if !defined(CONFIG_RTL8822B) && !defined(CONFIG_RTL8822C)
-+	#ifdef CONFIG_SDIO_RX_COPY
-+	res = sdio_init_recvbuf_with_skb(&padapter->recvpriv, precvbuf, size);
-+	#endif
-+	#endif
-+
-+#endif /* CONFIG_XXX_HCI */
-+
-+	return res;
-+}
-+
-+/* free os related resource in struct recv_buf */
-+int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf)
-+{
-+	int ret = _SUCCESS;
-+
-+#ifdef CONFIG_USB_HCI
-+
-+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
-+
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
-+	struct usb_device	*pusbd = pdvobjpriv->pusbdev;
-+
-+	rtw_usb_buffer_free(pusbd, (size_t)precvbuf->alloc_sz, precvbuf->pallocated_buf, precvbuf->dma_transfer_addr);
-+	precvbuf->pallocated_buf =  NULL;
-+	precvbuf->dma_transfer_addr = 0;
-+
-+#endif /* CONFIG_USE_USB_BUFFER_ALLOC_RX */
-+
-+	if (precvbuf->purb) {
-+		/* usb_kill_urb(precvbuf->purb); */
-+		usb_free_urb(precvbuf->purb);
-+	}
-+
-+#endif /* CONFIG_USB_HCI */
-+
-+
-+	if (precvbuf->pskb) {
-+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
-+		if (rtw_free_skb_premem(precvbuf->pskb) != 0)
-+#endif
-+			rtw_skb_free(precvbuf->pskb);
-+	}
-+	return ret;
-+
-+}
-+
-+_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa
-+	, u8 *msdu ,u16 msdu_len, enum rtw_rx_llc_hdl llc_hdl)
-+{
-+	u8	*data_ptr;
-+	_pkt *sub_skb;
-+	struct rx_pkt_attrib *pattrib;
-+
-+	pattrib = &prframe->u.hdr.attrib;
-+
-+#ifdef CONFIG_SKB_COPY
-+	sub_skb = rtw_skb_alloc(msdu_len + 14);
-+	if (sub_skb) {
-+		skb_reserve(sub_skb, 14);
-+		data_ptr = (u8 *)skb_put(sub_skb, msdu_len);
-+		_rtw_memcpy(data_ptr, msdu, msdu_len);
-+	} else
-+#endif /* CONFIG_SKB_COPY */
-+	{
-+		sub_skb = rtw_skb_clone(prframe->u.hdr.pkt);
-+		if (sub_skb) {
-+			sub_skb->data = msdu;
-+			sub_skb->len = msdu_len;
-+			skb_set_tail_pointer(sub_skb, msdu_len);
-+		} else {
-+			RTW_INFO("%s(): rtw_skb_clone() Fail!!!\n", __FUNCTION__);
-+			return NULL;
-+		}
-+	}
-+
-+	if (llc_hdl) {
-+		/* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */
-+		skb_pull(sub_skb, SNAP_SIZE);
-+		_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), sa, ETH_ALEN);
-+		_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), da, ETH_ALEN);
-+	} else {
-+		/* Leave Ethernet header part of hdr and full payload */
-+		u16 len;
-+
-+		len = htons(sub_skb->len);
-+		_rtw_memcpy(skb_push(sub_skb, 2), &len, 2);
-+		_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), sa, ETH_ALEN);
-+		_rtw_memcpy(skb_push(sub_skb, ETH_ALEN), da, ETH_ALEN);
-+	}
-+
-+	return sub_skb;
-+}
-+
-+#ifdef CONFIG_RTW_NAPI
-+static int napi_recv(_adapter *padapter, int budget)
-+{
-+	_pkt *pskb;
-+	struct recv_priv *precvpriv = &padapter->recvpriv;
-+	int work_done = 0;
-+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
-+	u8 rx_ok;
-+
-+
-+	while ((work_done < budget) &&
-+	       (!skb_queue_empty(&precvpriv->rx_napi_skb_queue))) {
-+		pskb = skb_dequeue(&precvpriv->rx_napi_skb_queue);
-+		if (!pskb)
-+			break;
-+
-+		rx_ok = _FALSE;
-+
-+#ifdef CONFIG_RTW_GRO
-+		/*	 
-+			cloned SKB use dataref to avoid kernel release it.
-+			But dataref changed in napi_gro_receive.
-+			So, we should prevent cloned SKB go into napi_gro_receive.
-+		*/
-+		if (pregistrypriv->en_gro && !skb_cloned(pskb)) {
-+			rtw_napi_gro_receive(&padapter->napi, pskb);
-+			rx_ok = _TRUE;
-+			goto next;
-+		}
-+#endif /* CONFIG_RTW_GRO */
-+
-+		if (rtw_netif_receive_skb(padapter->pnetdev, pskb) == NET_RX_SUCCESS)
-+			rx_ok = _TRUE;
-+
-+next:
-+		if (rx_ok == _TRUE) {
-+			work_done++;
-+			DBG_COUNTER(padapter->rx_logs.os_netif_ok);
-+		} else {
-+			DBG_COUNTER(padapter->rx_logs.os_netif_err);
-+		}
-+	}
-+
-+	return work_done;
-+}
-+
-+int rtw_recv_napi_poll(struct napi_struct *napi, int budget)
-+{
-+	_adapter *padapter = container_of(napi, _adapter, napi);
-+	int work_done = 0;
-+	struct recv_priv *precvpriv = &padapter->recvpriv;
-+
-+
-+	work_done = napi_recv(padapter, budget);
-+	if (work_done < budget) {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) && defined(CONFIG_PCI_HCI)
-+		napi_complete_done(napi, work_done);
-+#else
-+		napi_complete(napi);
-+#endif
-+		if (!skb_queue_empty(&precvpriv->rx_napi_skb_queue))
-+			napi_schedule(napi);
-+	}
-+
-+	return work_done;
-+}
-+
-+#ifdef CONFIG_RTW_NAPI_DYNAMIC
-+void dynamic_napi_th_chk (_adapter *adapter)
-+{
-+
-+	if (adapter->registrypriv.en_napi) {
-+		struct dvobj_priv *dvobj;
-+		struct registry_priv *registry;
-+	
-+		dvobj = adapter_to_dvobj(adapter);
-+		registry = &adapter->registrypriv;
-+		if (dvobj->traffic_stat.cur_rx_tp > registry->napi_threshold)
-+			dvobj->en_napi_dynamic = 1;
-+		else
-+			dvobj->en_napi_dynamic = 0;
-+	}
-+
-+}
-+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
-+#endif /* CONFIG_RTW_NAPI */
-+
-+void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe)
-+{
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+	struct recv_priv *precvpriv = &(padapter->recvpriv);
-+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
-+#ifdef CONFIG_BR_EXT
-+	void *br_port = NULL;
-+#endif
-+	int ret;
-+
-+	/* Indicat the packets to upper layer */
-+	if (pkt) {
-+		struct ethhdr *ehdr = (struct ethhdr *)pkt->data;
-+
-+		DBG_COUNTER(padapter->rx_logs.os_indicate);
-+
-+#ifdef CONFIG_BR_EXT
-+		if (!adapter_use_wds(padapter) && check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) {
-+			/* Insert NAT2.5 RX here! */
-+			#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
-+			br_port = padapter->pnetdev->br_port;
-+			#else
-+			rcu_read_lock();
-+			br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
-+			rcu_read_unlock();
-+			#endif
-+
-+			if (br_port) {
-+				int nat25_handle_frame(_adapter *priv, struct sk_buff *skb);
-+
-+				if (nat25_handle_frame(padapter, pkt) == -1) {
-+					/* priv->ext_stats.rx_data_drops++; */
-+					/* DEBUG_ERR("RX DROP: nat25_handle_frame fail!\n"); */
-+					/* return FAIL; */
-+
-+					#if 1
-+					/* bypass this frame to upper layer!! */
-+					#else
-+					rtw_skb_free(sub_skb);
-+					continue;
-+					#endif
-+				}
-+			}
-+		}
-+#endif /* CONFIG_BR_EXT */
-+
-+		/* After eth_type_trans process , pkt->data pointer will move from ethrnet header to ip header */
-+		pkt->protocol = eth_type_trans(pkt, padapter->pnetdev);
-+		pkt->dev = padapter->pnetdev;
-+		pkt->ip_summed = CHECKSUM_NONE; /* CONFIG_TCP_CSUM_OFFLOAD_RX */
-+#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
-+		if ((rframe->u.hdr.attrib.csum_valid == 1)
-+		    && (rframe->u.hdr.attrib.csum_err == 0))
-+			pkt->ip_summed = CHECKSUM_UNNECESSARY;
-+#endif /* CONFIG_TCP_CSUM_OFFLOAD_RX */
-+
-+#ifdef CONFIG_RTW_NAPI
-+#ifdef CONFIG_RTW_NAPI_DYNAMIC
-+		if (!skb_queue_empty(&precvpriv->rx_napi_skb_queue)
-+			&& !adapter_to_dvobj(padapter)->en_napi_dynamic			
-+			)
-+			napi_recv(padapter, RTL_NAPI_WEIGHT);
-+#endif
-+
-+		if (pregistrypriv->en_napi
-+			#ifdef CONFIG_RTW_NAPI_DYNAMIC
-+			&& adapter_to_dvobj(padapter)->en_napi_dynamic
-+			#endif
-+		) {
-+			skb_queue_tail(&precvpriv->rx_napi_skb_queue, pkt);
-+			#ifndef CONFIG_RTW_NAPI_V2
-+			napi_schedule(&padapter->napi);
-+			#endif
-+			return;
-+		}
-+#endif /* CONFIG_RTW_NAPI */
-+
-+		ret = rtw_netif_rx(padapter->pnetdev, pkt);
-+		if (ret == NET_RX_SUCCESS)
-+			DBG_COUNTER(padapter->rx_logs.os_netif_ok);
-+		else
-+			DBG_COUNTER(padapter->rx_logs.os_netif_err);
-+	}
-+}
-+
-+void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup)
-+{
-+#ifdef CONFIG_IOCTL_CFG80211
-+	enum nl80211_key_type key_type = 0;
-+#endif
-+	union iwreq_data wrqu;
-+	struct iw_michaelmicfailure    ev;
-+	struct security_priv	*psecuritypriv = &padapter->securitypriv;
-+	systime cur_time = 0;
-+
-+	if (psecuritypriv->last_mic_err_time == 0)
-+		psecuritypriv->last_mic_err_time = rtw_get_current_time();
-+	else {
-+		cur_time = rtw_get_current_time();
-+
-+		if (cur_time - psecuritypriv->last_mic_err_time < 60 * HZ) {
-+			psecuritypriv->btkip_countermeasure = _TRUE;
-+			psecuritypriv->last_mic_err_time = 0;
-+			psecuritypriv->btkip_countermeasure_time = cur_time;
-+		} else
-+			psecuritypriv->last_mic_err_time = rtw_get_current_time();
-+	}
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	if (bgroup)
-+		key_type |= NL80211_KEYTYPE_GROUP;
-+	else
-+		key_type |= NL80211_KEYTYPE_PAIRWISE;
-+
-+	cfg80211_michael_mic_failure(padapter->pnetdev, sta->cmn.mac_addr, key_type, -1, NULL, GFP_ATOMIC);
-+#endif
-+
-+	_rtw_memset(&ev, 0x00, sizeof(ev));
-+	if (bgroup)
-+		ev.flags |= IW_MICFAILURE_GROUP;
-+	else
-+		ev.flags |= IW_MICFAILURE_PAIRWISE;
-+
-+	ev.src_addr.sa_family = ARPHRD_ETHER;
-+	_rtw_memcpy(ev.src_addr.sa_data, sta->cmn.mac_addr, ETH_ALEN);
-+
-+	_rtw_memset(&wrqu, 0x00, sizeof(wrqu));
-+	wrqu.data.length = sizeof(ev);
-+
-+#ifndef CONFIG_IOCTL_CFG80211
-+	wireless_send_event(padapter->pnetdev, IWEVMICHAELMICFAILURE, &wrqu, (char *) &ev);
-+#endif
-+}
-+
-+#ifdef CONFIG_HOSTAPD_MLME
-+void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	_pkt *skb;
-+	struct hostapd_priv *phostapdpriv  = padapter->phostapdpriv;
-+	struct net_device *pmgnt_netdev = phostapdpriv->pmgnt_netdev;
-+
-+
-+	skb = precv_frame->u.hdr.pkt;
-+
-+	if (skb == NULL)
-+		return;
-+
-+	skb->data = precv_frame->u.hdr.rx_data;
-+	skb->tail = precv_frame->u.hdr.rx_tail;
-+	skb->len = precv_frame->u.hdr.len;
-+
-+	/* pskb_copy = rtw_skb_copy(skb);
-+	*	if(skb == NULL) goto _exit; */
-+
-+	skb->dev = pmgnt_netdev;
-+	skb->ip_summed = CHECKSUM_NONE;
-+	skb->pkt_type = PACKET_OTHERHOST;
-+	/* skb->protocol = __constant_htons(0x0019); ETH_P_80211_RAW */
-+	skb->protocol = __constant_htons(0x0003); /*ETH_P_80211_RAW*/
-+
-+	/* RTW_INFO("(1)data=0x%x, head=0x%x, tail=0x%x, mac_header=0x%x, len=%d\n", skb->data, skb->head, skb->tail, skb->mac_header, skb->len); */
-+
-+	/* skb->mac.raw = skb->data; */
-+	skb_reset_mac_header(skb);
-+
-+	/* skb_pull(skb, 24); */
-+	_rtw_memset(skb->cb, 0, sizeof(skb->cb));
-+
-+	rtw_netif_rx(pmgnt_netdev, skb);
-+
-+	precv_frame->u.hdr.pkt = NULL; /* set pointer to NULL before rtw_free_recvframe() if call rtw_netif_rx() */
-+}
-+#endif /* CONFIG_HOSTAPD_MLME */
-+
-+#ifdef CONFIG_WIFI_MONITOR
-+/* 
-+   precv_frame: impossible to be NULL
-+   precv_frame: free by caller
-+ */
-+int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	int ret = _FAIL;
-+	_pkt *skb;
-+
-+	skb = precv_frame->u.hdr.pkt;
-+	if (skb == NULL) {
-+		RTW_INFO("%s :skb==NULL something wrong!!!!\n", __func__);
-+		goto _recv_drop;
-+	}
-+
-+	skb->data = precv_frame->u.hdr.rx_data;
-+	skb_set_tail_pointer(skb, precv_frame->u.hdr.len);
-+	skb->len = precv_frame->u.hdr.len;
-+	skb->ip_summed = CHECKSUM_NONE;
-+	skb->pkt_type = PACKET_OTHERHOST;
-+	skb->protocol = htons(0x0019); /* ETH_P_80211_RAW */
-+
-+	/* send to kernel */
-+	rtw_netif_rx(padapter->pnetdev, skb);
-+
-+	/* pointers to NULL before rtw_free_recvframe() */
-+	precv_frame->u.hdr.pkt = NULL;
-+
-+	ret = _SUCCESS;
-+
-+_recv_drop:
-+	return ret;
-+}
-+#endif /* CONFIG_WIFI_MONITOR */
-+
-+inline void rtw_rframe_set_os_pkt(union recv_frame *rframe)
-+{
-+	_pkt *skb = rframe->u.hdr.pkt;
-+
-+	skb->data = rframe->u.hdr.rx_data;
-+	skb_set_tail_pointer(skb, rframe->u.hdr.len);
-+	skb->len = rframe->u.hdr.len;
-+}
-+
-+int rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame)
-+{
-+	struct recv_priv *precvpriv;
-+	_queue	*pfree_recv_queue;
-+
-+	precvpriv = &(padapter->recvpriv);
-+	pfree_recv_queue = &(precvpriv->free_recv_queue);
-+
-+	if (precv_frame->u.hdr.pkt == NULL)
-+		goto _recv_indicatepkt_drop;
-+
-+	rtw_os_recv_indicate_pkt(padapter, precv_frame->u.hdr.pkt, precv_frame);
-+
-+	precv_frame->u.hdr.pkt = NULL;
-+	rtw_free_recvframe(precv_frame, pfree_recv_queue);
-+	return _SUCCESS;
-+
-+_recv_indicatepkt_drop:
-+	rtw_free_recvframe(precv_frame, pfree_recv_queue);
-+	DBG_COUNTER(padapter->rx_logs.os_indicate_err);
-+	return _FAIL;
-+}
-+
-+void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf)
-+{
-+#ifdef CONFIG_USB_HCI
-+	struct recv_priv *precvpriv = &padapter->recvpriv;
-+
-+	precvbuf->ref_cnt--;
-+
-+	/* free skb in recv_buf */
-+	rtw_skb_free(precvbuf->pskb);
-+
-+	precvbuf->pskb = NULL;
-+
-+	if (precvbuf->irp_pending == _FALSE)
-+		rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
-+
-+
-+#endif
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	precvbuf->pskb = NULL;
-+#endif
-+
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/rhashtable.c b/drivers/staging/rtl8723cs/os_dep/linux/rhashtable.c
-new file mode 100644
-index 000000000000..0163a4b07ec1
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/rhashtable.c
-@@ -0,0 +1,844 @@
-+/*
-+ * Resizable, Scalable, Concurrent Hash Table
-+ *
-+ * Copyright (c) 2015 Herbert Xu <herbert@gondor.apana.org.au>
-+ * Copyright (c) 2014-2015 Thomas Graf <tgraf@suug.ch>
-+ * Copyright (c) 2008-2014 Patrick McHardy <kaber@trash.net>
-+ *
-+ * Code partially derived from nft_hash
-+ * Rewritten with rehash code from br_multicast plus single list
-+ * pointer as suggested by Josh Triplett
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/atomic.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/log2.h>
-+#include <linux/sched.h>
-+#include <linux/slab.h>
-+#include <linux/vmalloc.h>
-+#include <linux/mm.h>
-+#include <linux/jhash.h>
-+#include <linux/random.h>
-+#include <linux/err.h>
-+#include <linux/export.h>
-+
-+#define HASH_DEFAULT_SIZE	64UL
-+#define HASH_MIN_SIZE		4U
-+#define BUCKET_LOCKS_PER_CPU   128UL
-+
-+static u32 head_hashfn(struct rhashtable *ht,
-+		       const struct bucket_table *tbl,
-+		       const struct rhash_head *he)
-+{
-+	return rht_head_hashfn(ht, tbl, he, ht->p);
-+}
-+
-+#ifdef CONFIG_PROVE_LOCKING
-+#define ASSERT_RHT_MUTEX(HT) BUG_ON(!lockdep_rht_mutex_is_held(HT))
-+
-+int lockdep_rht_mutex_is_held(struct rhashtable *ht)
-+{
-+	return (debug_locks) ? lockdep_is_held(&ht->mutex) : 1;
-+}
-+
-+int lockdep_rht_bucket_is_held(const struct bucket_table *tbl, u32 hash)
-+{
-+	spinlock_t *lock = rht_bucket_lock(tbl, hash);
-+
-+	return (debug_locks) ? lockdep_is_held(lock) : 1;
-+}
-+#else
-+#define ASSERT_RHT_MUTEX(HT)
-+#endif
-+
-+
-+static int alloc_bucket_locks(struct rhashtable *ht, struct bucket_table *tbl,
-+			      gfp_t gfp)
-+{
-+	unsigned int i, size;
-+#if defined(CONFIG_PROVE_LOCKING)
-+	unsigned int nr_pcpus = 2;
-+#else
-+	unsigned int nr_pcpus = num_possible_cpus();
-+#endif
-+
-+	nr_pcpus = min_t(unsigned int, nr_pcpus, 32UL);
-+	size = roundup_pow_of_two(nr_pcpus * ht->p.locks_mul);
-+
-+	/* Never allocate more than 0.5 locks per bucket */
-+	size = min_t(unsigned int, size, tbl->size >> 1);
-+
-+	if (sizeof(spinlock_t) != 0) {
-+#ifdef CONFIG_NUMA
-+		if (size * sizeof(spinlock_t) > PAGE_SIZE &&
-+		    gfp == GFP_KERNEL)
-+			tbl->locks = vmalloc(size * sizeof(spinlock_t));
-+		else
-+#endif
-+		tbl->locks = kmalloc_array(size, sizeof(spinlock_t),
-+					   gfp);
-+		if (!tbl->locks)
-+			return -ENOMEM;
-+		for (i = 0; i < size; i++)
-+			spin_lock_init(&tbl->locks[i]);
-+	}
-+	tbl->locks_mask = size - 1;
-+
-+	return 0;
-+}
-+
-+static void bucket_table_free(const struct bucket_table *tbl)
-+{
-+	if (tbl)
-+		kvfree(tbl->locks);
-+
-+	kvfree(tbl);
-+}
-+
-+static void bucket_table_free_rcu(struct rcu_head *head)
-+{
-+	bucket_table_free(container_of(head, struct bucket_table, rcu));
-+}
-+
-+static struct bucket_table *bucket_table_alloc(struct rhashtable *ht,
-+					       size_t nbuckets,
-+					       gfp_t gfp)
-+{
-+	struct bucket_table *tbl = NULL;
-+	size_t size;
-+	int i;
-+
-+	size = sizeof(*tbl) + nbuckets * sizeof(tbl->buckets[0]);
-+	if (size <= (PAGE_SIZE << PAGE_ALLOC_COSTLY_ORDER) ||
-+	    gfp != GFP_KERNEL)
-+		tbl = kzalloc(size, gfp | __GFP_NOWARN | __GFP_NORETRY);
-+	if (tbl == NULL && gfp == GFP_KERNEL)
-+		tbl = vzalloc(size);
-+	if (tbl == NULL)
-+		return NULL;
-+
-+	tbl->size = nbuckets;
-+
-+	if (alloc_bucket_locks(ht, tbl, gfp) < 0) {
-+		bucket_table_free(tbl);
-+		return NULL;
-+	}
-+
-+	INIT_LIST_HEAD(&tbl->walkers);
-+
-+	get_random_bytes(&tbl->hash_rnd, sizeof(tbl->hash_rnd));
-+
-+	for (i = 0; i < nbuckets; i++)
-+		INIT_RHT_NULLS_HEAD(tbl->buckets[i], ht, i);
-+
-+	return tbl;
-+}
-+
-+static struct bucket_table *rhashtable_last_table(struct rhashtable *ht,
-+						  struct bucket_table *tbl)
-+{
-+	struct bucket_table *new_tbl;
-+
-+	do {
-+		new_tbl = tbl;
-+		tbl = rht_dereference_rcu(tbl->future_tbl, ht);
-+	} while (tbl);
-+
-+	return new_tbl;
-+}
-+
-+static int rhashtable_rehash_one(struct rhashtable *ht, unsigned int old_hash)
-+{
-+	struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht);
-+	struct bucket_table *new_tbl = rhashtable_last_table(ht,
-+		rht_dereference_rcu(old_tbl->future_tbl, ht));
-+	struct rhash_head __rcu **pprev = &old_tbl->buckets[old_hash];
-+	int err = -ENOENT;
-+	struct rhash_head *head, *next, *entry;
-+	spinlock_t *new_bucket_lock;
-+	unsigned int new_hash;
-+
-+	rht_for_each(entry, old_tbl, old_hash) {
-+		err = 0;
-+		next = rht_dereference_bucket(entry->next, old_tbl, old_hash);
-+
-+		if (rht_is_a_nulls(next))
-+			break;
-+
-+		pprev = &entry->next;
-+	}
-+
-+	if (err)
-+		goto out;
-+
-+	new_hash = head_hashfn(ht, new_tbl, entry);
-+
-+	new_bucket_lock = rht_bucket_lock(new_tbl, new_hash);
-+
-+	spin_lock_nested(new_bucket_lock, SINGLE_DEPTH_NESTING);
-+	head = rht_dereference_bucket(new_tbl->buckets[new_hash],
-+				      new_tbl, new_hash);
-+
-+	RCU_INIT_POINTER(entry->next, head);
-+
-+	rcu_assign_pointer(new_tbl->buckets[new_hash], entry);
-+	spin_unlock(new_bucket_lock);
-+
-+	rcu_assign_pointer(*pprev, next);
-+
-+out:
-+	return err;
-+}
-+
-+static void rhashtable_rehash_chain(struct rhashtable *ht,
-+				    unsigned int old_hash)
-+{
-+	struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht);
-+	spinlock_t *old_bucket_lock;
-+
-+	old_bucket_lock = rht_bucket_lock(old_tbl, old_hash);
-+
-+	spin_lock_bh(old_bucket_lock);
-+	while (!rhashtable_rehash_one(ht, old_hash))
-+		;
-+	old_tbl->rehash++;
-+	spin_unlock_bh(old_bucket_lock);
-+}
-+
-+static int rhashtable_rehash_attach(struct rhashtable *ht,
-+				    struct bucket_table *old_tbl,
-+				    struct bucket_table *new_tbl)
-+{
-+	/* Protect future_tbl using the first bucket lock. */
-+	spin_lock_bh(old_tbl->locks);
-+
-+	/* Did somebody beat us to it? */
-+	if (rcu_access_pointer(old_tbl->future_tbl)) {
-+		spin_unlock_bh(old_tbl->locks);
-+		return -EEXIST;
-+	}
-+
-+	/* Make insertions go into the new, empty table right away. Deletions
-+	 * and lookups will be attempted in both tables until we synchronize.
-+	 */
-+	rcu_assign_pointer(old_tbl->future_tbl, new_tbl);
-+
-+	/* Ensure the new table is visible to readers. */
-+	smp_wmb();
-+
-+	spin_unlock_bh(old_tbl->locks);
-+
-+	return 0;
-+}
-+
-+static int rhashtable_rehash_table(struct rhashtable *ht)
-+{
-+	struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht);
-+	struct bucket_table *new_tbl;
-+	struct rhashtable_walker *walker;
-+	unsigned int old_hash;
-+
-+	new_tbl = rht_dereference(old_tbl->future_tbl, ht);
-+	if (!new_tbl)
-+		return 0;
-+
-+	for (old_hash = 0; old_hash < old_tbl->size; old_hash++)
-+		rhashtable_rehash_chain(ht, old_hash);
-+
-+	/* Publish the new table pointer. */
-+	rcu_assign_pointer(ht->tbl, new_tbl);
-+
-+	spin_lock(&ht->lock);
-+	list_for_each_entry(walker, &old_tbl->walkers, list)
-+		walker->tbl = NULL;
-+	spin_unlock(&ht->lock);
-+
-+	/* Wait for readers. All new readers will see the new
-+	 * table, and thus no references to the old table will
-+	 * remain.
-+	 */
-+	call_rcu(&old_tbl->rcu, bucket_table_free_rcu);
-+
-+	return rht_dereference(new_tbl->future_tbl, ht) ? -EAGAIN : 0;
-+}
-+
-+/**
-+ * rhashtable_expand - Expand hash table while allowing concurrent lookups
-+ * @ht:		the hash table to expand
-+ *
-+ * A secondary bucket array is allocated and the hash entries are migrated.
-+ *
-+ * This function may only be called in a context where it is safe to call
-+ * synchronize_rcu(), e.g. not within a rcu_read_lock() section.
-+ *
-+ * The caller must ensure that no concurrent resizing occurs by holding
-+ * ht->mutex.
-+ *
-+ * It is valid to have concurrent insertions and deletions protected by per
-+ * bucket locks or concurrent RCU protected lookups and traversals.
-+ */
-+static int rhashtable_expand(struct rhashtable *ht)
-+{
-+	struct bucket_table *new_tbl, *old_tbl = rht_dereference(ht->tbl, ht);
-+	int err;
-+
-+	ASSERT_RHT_MUTEX(ht);
-+
-+	old_tbl = rhashtable_last_table(ht, old_tbl);
-+
-+	new_tbl = bucket_table_alloc(ht, old_tbl->size * 2, GFP_KERNEL);
-+	if (new_tbl == NULL)
-+		return -ENOMEM;
-+
-+	err = rhashtable_rehash_attach(ht, old_tbl, new_tbl);
-+	if (err)
-+		bucket_table_free(new_tbl);
-+
-+	return err;
-+}
-+
-+/**
-+ * rhashtable_shrink - Shrink hash table while allowing concurrent lookups
-+ * @ht:		the hash table to shrink
-+ *
-+ * This function shrinks the hash table to fit, i.e., the smallest
-+ * size would not cause it to expand right away automatically.
-+ *
-+ * The caller must ensure that no concurrent resizing occurs by holding
-+ * ht->mutex.
-+ *
-+ * The caller must ensure that no concurrent table mutations take place.
-+ * It is however valid to have concurrent lookups if they are RCU protected.
-+ *
-+ * It is valid to have concurrent insertions and deletions protected by per
-+ * bucket locks or concurrent RCU protected lookups and traversals.
-+ */
-+static int rhashtable_shrink(struct rhashtable *ht)
-+{
-+	struct bucket_table *new_tbl, *old_tbl = rht_dereference(ht->tbl, ht);
-+	unsigned int size;
-+	int err;
-+
-+	ASSERT_RHT_MUTEX(ht);
-+
-+	size = roundup_pow_of_two(atomic_read(&ht->nelems) * 3 / 2);
-+	if (size < ht->p.min_size)
-+		size = ht->p.min_size;
-+
-+	if (old_tbl->size <= size)
-+		return 0;
-+
-+	if (rht_dereference(old_tbl->future_tbl, ht))
-+		return -EEXIST;
-+
-+	new_tbl = bucket_table_alloc(ht, size, GFP_KERNEL);
-+	if (new_tbl == NULL)
-+		return -ENOMEM;
-+
-+	err = rhashtable_rehash_attach(ht, old_tbl, new_tbl);
-+	if (err)
-+		bucket_table_free(new_tbl);
-+
-+	return err;
-+}
-+
-+static void rht_deferred_worker(struct work_struct *work)
-+{
-+	struct rhashtable *ht;
-+	struct bucket_table *tbl;
-+	int err = 0;
-+
-+	ht = container_of(work, struct rhashtable, run_work);
-+	mutex_lock(&ht->mutex);
-+
-+	tbl = rht_dereference(ht->tbl, ht);
-+	tbl = rhashtable_last_table(ht, tbl);
-+
-+	if (rht_grow_above_75(ht, tbl))
-+		rhashtable_expand(ht);
-+	else if (ht->p.automatic_shrinking && rht_shrink_below_30(ht, tbl))
-+		rhashtable_shrink(ht);
-+
-+	err = rhashtable_rehash_table(ht);
-+
-+	mutex_unlock(&ht->mutex);
-+
-+	if (err)
-+		schedule_work(&ht->run_work);
-+}
-+
-+static bool rhashtable_check_elasticity(struct rhashtable *ht,
-+					struct bucket_table *tbl,
-+					unsigned int hash)
-+{
-+	unsigned int elasticity = ht->elasticity;
-+	struct rhash_head *head;
-+
-+	rht_for_each(head, tbl, hash)
-+		if (!--elasticity)
-+			return true;
-+
-+	return false;
-+}
-+
-+int rhashtable_insert_rehash(struct rhashtable *ht,
-+			     struct bucket_table *tbl)
-+{
-+	struct bucket_table *old_tbl;
-+	struct bucket_table *new_tbl;
-+	unsigned int size;
-+	int err;
-+
-+	old_tbl = rht_dereference_rcu(ht->tbl, ht);
-+
-+	size = tbl->size;
-+
-+	err = -EBUSY;
-+
-+	if (rht_grow_above_75(ht, tbl))
-+		size *= 2;
-+	/* Do not schedule more than one rehash */
-+	else if (old_tbl != tbl)
-+		goto fail;
-+
-+	err = -ENOMEM;
-+
-+	new_tbl = bucket_table_alloc(ht, size, GFP_ATOMIC);
-+	if (new_tbl == NULL)
-+		goto fail;
-+
-+	err = rhashtable_rehash_attach(ht, tbl, new_tbl);
-+	if (err) {
-+		bucket_table_free(new_tbl);
-+		if (err == -EEXIST)
-+			err = 0;
-+	} else
-+		schedule_work(&ht->run_work);
-+
-+	return err;
-+
-+fail:
-+	/* Do not fail the insert if someone else did a rehash. */
-+	if (likely(rcu_dereference_raw(tbl->future_tbl)))
-+		return 0;
-+
-+	/* Schedule async rehash to retry allocation in process context. */
-+	if (err == -ENOMEM)
-+		schedule_work(&ht->run_work);
-+
-+	return err;
-+}
-+
-+struct bucket_table *rhashtable_insert_slow(struct rhashtable *ht,
-+					    const void *key,
-+					    struct rhash_head *obj,
-+					    struct bucket_table *tbl)
-+{
-+	struct rhash_head *head;
-+	unsigned int hash;
-+	int err;
-+
-+	tbl = rhashtable_last_table(ht, tbl);
-+	hash = head_hashfn(ht, tbl, obj);
-+	spin_lock_nested(rht_bucket_lock(tbl, hash), SINGLE_DEPTH_NESTING);
-+
-+	err = -EEXIST;
-+	if (key && rhashtable_lookup_fast(ht, key, ht->p))
-+		goto exit;
-+
-+	err = -E2BIG;
-+	if (unlikely(rht_grow_above_max(ht, tbl)))
-+		goto exit;
-+
-+	err = -EAGAIN;
-+	if (rhashtable_check_elasticity(ht, tbl, hash) ||
-+	    rht_grow_above_100(ht, tbl))
-+		goto exit;
-+
-+	err = 0;
-+
-+	head = rht_dereference_bucket(tbl->buckets[hash], tbl, hash);
-+
-+	RCU_INIT_POINTER(obj->next, head);
-+
-+	rcu_assign_pointer(tbl->buckets[hash], obj);
-+
-+	atomic_inc(&ht->nelems);
-+
-+exit:
-+	spin_unlock(rht_bucket_lock(tbl, hash));
-+
-+	if (err == 0)
-+		return NULL;
-+	else if (err == -EAGAIN)
-+		return tbl;
-+	else
-+		return ERR_PTR(err);
-+}
-+
-+/**
-+ * rhashtable_walk_init - Initialise an iterator
-+ * @ht:		Table to walk over
-+ * @iter:	Hash table Iterator
-+ *
-+ * This function prepares a hash table walk.
-+ *
-+ * Note that if you restart a walk after rhashtable_walk_stop you
-+ * may see the same object twice.  Also, you may miss objects if
-+ * there are removals in between rhashtable_walk_stop and the next
-+ * call to rhashtable_walk_start.
-+ *
-+ * For a completely stable walk you should construct your own data
-+ * structure outside the hash table.
-+ *
-+ * This function may sleep so you must not call it from interrupt
-+ * context or with spin locks held.
-+ *
-+ * You must call rhashtable_walk_exit if this function returns
-+ * successfully.
-+ */
-+int rhashtable_walk_init(struct rhashtable *ht, struct rhashtable_iter *iter)
-+{
-+	iter->ht = ht;
-+	iter->p = NULL;
-+	iter->slot = 0;
-+	iter->skip = 0;
-+
-+	iter->walker = kmalloc(sizeof(*iter->walker), GFP_KERNEL);
-+	if (!iter->walker)
-+		return -ENOMEM;
-+
-+	spin_lock(&ht->lock);
-+	iter->walker->tbl =
-+		rcu_dereference_protected(ht->tbl, lockdep_is_held(&ht->lock));
-+	list_add(&iter->walker->list, &iter->walker->tbl->walkers);
-+	spin_unlock(&ht->lock);
-+
-+	return 0;
-+}
-+
-+/**
-+ * rhashtable_walk_exit - Free an iterator
-+ * @iter:	Hash table Iterator
-+ *
-+ * This function frees resources allocated by rhashtable_walk_init.
-+ */
-+void rhashtable_walk_exit(struct rhashtable_iter *iter)
-+{
-+	spin_lock(&iter->ht->lock);
-+	if (iter->walker->tbl)
-+		list_del(&iter->walker->list);
-+	spin_unlock(&iter->ht->lock);
-+	kfree(iter->walker);
-+}
-+
-+/**
-+ * rhashtable_walk_start - Start a hash table walk
-+ * @iter:	Hash table iterator
-+ *
-+ * Start a hash table walk.  Note that we take the RCU lock in all
-+ * cases including when we return an error.  So you must always call
-+ * rhashtable_walk_stop to clean up.
-+ *
-+ * Returns zero if successful.
-+ *
-+ * Returns -EAGAIN if resize event occured.  Note that the iterator
-+ * will rewind back to the beginning and you may use it immediately
-+ * by calling rhashtable_walk_next.
-+ */
-+int rhashtable_walk_start(struct rhashtable_iter *iter)
-+	__acquires(RCU)
-+{
-+	struct rhashtable *ht = iter->ht;
-+
-+	rcu_read_lock();
-+
-+	spin_lock(&ht->lock);
-+	if (iter->walker->tbl)
-+		list_del(&iter->walker->list);
-+	spin_unlock(&ht->lock);
-+
-+	if (!iter->walker->tbl) {
-+		iter->walker->tbl = rht_dereference_rcu(ht->tbl, ht);
-+		return -EAGAIN;
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * rhashtable_walk_next - Return the next object and advance the iterator
-+ * @iter:	Hash table iterator
-+ *
-+ * Note that you must call rhashtable_walk_stop when you are finished
-+ * with the walk.
-+ *
-+ * Returns the next object or NULL when the end of the table is reached.
-+ *
-+ * Returns -EAGAIN if resize event occured.  Note that the iterator
-+ * will rewind back to the beginning and you may continue to use it.
-+ */
-+void *rhashtable_walk_next(struct rhashtable_iter *iter)
-+{
-+	struct bucket_table *tbl = iter->walker->tbl;
-+	struct rhashtable *ht = iter->ht;
-+	struct rhash_head *p = iter->p;
-+
-+	if (p) {
-+		p = rht_dereference_bucket_rcu(p->next, tbl, iter->slot);
-+		goto next;
-+	}
-+
-+	for (; iter->slot < tbl->size; iter->slot++) {
-+		int skip = iter->skip;
-+
-+		rht_for_each_rcu(p, tbl, iter->slot) {
-+			if (!skip)
-+				break;
-+			skip--;
-+		}
-+
-+next:
-+		if (!rht_is_a_nulls(p)) {
-+			iter->skip++;
-+			iter->p = p;
-+			return rht_obj(ht, p);
-+		}
-+
-+		iter->skip = 0;
-+	}
-+
-+	iter->p = NULL;
-+
-+	/* Ensure we see any new tables. */
-+	smp_rmb();
-+
-+	iter->walker->tbl = rht_dereference_rcu(tbl->future_tbl, ht);
-+	if (iter->walker->tbl) {
-+		iter->slot = 0;
-+		iter->skip = 0;
-+		return ERR_PTR(-EAGAIN);
-+	}
-+
-+	return NULL;
-+}
-+
-+/**
-+ * rhashtable_walk_stop - Finish a hash table walk
-+ * @iter:	Hash table iterator
-+ *
-+ * Finish a hash table walk.
-+ */
-+void rhashtable_walk_stop(struct rhashtable_iter *iter)
-+	__releases(RCU)
-+{
-+	struct rhashtable *ht;
-+	struct bucket_table *tbl = iter->walker->tbl;
-+
-+	if (!tbl)
-+		goto out;
-+
-+	ht = iter->ht;
-+
-+	spin_lock(&ht->lock);
-+	if (tbl->rehash < tbl->size)
-+		list_add(&iter->walker->list, &tbl->walkers);
-+	else
-+		iter->walker->tbl = NULL;
-+	spin_unlock(&ht->lock);
-+
-+	iter->p = NULL;
-+
-+out:
-+	rcu_read_unlock();
-+}
-+
-+static size_t rounded_hashtable_size(const struct rhashtable_params *params)
-+{
-+	return max(roundup_pow_of_two(params->nelem_hint * 4 / 3),
-+		   (unsigned long)params->min_size);
-+}
-+
-+static u32 rhashtable_jhash2(const void *key, u32 length, u32 seed)
-+{
-+	return jhash2(key, length, seed);
-+}
-+
-+/**
-+ * rhashtable_init - initialize a new hash table
-+ * @ht:		hash table to be initialized
-+ * @params:	configuration parameters
-+ *
-+ * Initializes a new hash table based on the provided configuration
-+ * parameters. A table can be configured either with a variable or
-+ * fixed length key:
-+ *
-+ * Configuration Example 1: Fixed length keys
-+ * struct test_obj {
-+ *	int			key;
-+ *	void *			my_member;
-+ *	struct rhash_head	node;
-+ * };
-+ *
-+ * struct rhashtable_params params = {
-+ *	.head_offset = offsetof(struct test_obj, node),
-+ *	.key_offset = offsetof(struct test_obj, key),
-+ *	.key_len = sizeof(int),
-+ *	.hashfn = jhash,
-+ *	.nulls_base = (1U << RHT_BASE_SHIFT),
-+ * };
-+ *
-+ * Configuration Example 2: Variable length keys
-+ * struct test_obj {
-+ *	[...]
-+ *	struct rhash_head	node;
-+ * };
-+ *
-+ * u32 my_hash_fn(const void *data, u32 len, u32 seed)
-+ * {
-+ *	struct test_obj *obj = data;
-+ *
-+ *	return [... hash ...];
-+ * }
-+ *
-+ * struct rhashtable_params params = {
-+ *	.head_offset = offsetof(struct test_obj, node),
-+ *	.hashfn = jhash,
-+ *	.obj_hashfn = my_hash_fn,
-+ * };
-+ */
-+int rhashtable_init(struct rhashtable *ht,
-+		    const struct rhashtable_params *params)
-+{
-+	struct bucket_table *tbl;
-+	size_t size;
-+
-+	size = HASH_DEFAULT_SIZE;
-+
-+	if ((!params->key_len && !params->obj_hashfn) ||
-+	    (params->obj_hashfn && !params->obj_cmpfn))
-+		return -EINVAL;
-+
-+	if (params->nulls_base && params->nulls_base < (1U << RHT_BASE_SHIFT))
-+		return -EINVAL;
-+
-+	memset(ht, 0, sizeof(*ht));
-+	mutex_init(&ht->mutex);
-+	spin_lock_init(&ht->lock);
-+	memcpy(&ht->p, params, sizeof(*params));
-+
-+	if (params->min_size)
-+		ht->p.min_size = roundup_pow_of_two(params->min_size);
-+
-+	if (params->max_size)
-+		ht->p.max_size = rounddown_pow_of_two(params->max_size);
-+
-+	if (params->insecure_max_entries)
-+		ht->p.insecure_max_entries =
-+			rounddown_pow_of_two(params->insecure_max_entries);
-+	else
-+		ht->p.insecure_max_entries = ht->p.max_size * 2;
-+
-+	ht->p.min_size = max(ht->p.min_size, HASH_MIN_SIZE);
-+
-+	if (params->nelem_hint)
-+		size = rounded_hashtable_size(&ht->p);
-+
-+	/* The maximum (not average) chain length grows with the
-+	 * size of the hash table, at a rate of (log N)/(log log N).
-+	 * The value of 16 is selected so that even if the hash
-+	 * table grew to 2^32 you would not expect the maximum
-+	 * chain length to exceed it unless we are under attack
-+	 * (or extremely unlucky).
-+	 *
-+	 * As this limit is only to detect attacks, we don't need
-+	 * to set it to a lower value as you'd need the chain
-+	 * length to vastly exceed 16 to have any real effect
-+	 * on the system.
-+	 */
-+	if (!params->insecure_elasticity)
-+		ht->elasticity = 16;
-+
-+	if (params->locks_mul)
-+		ht->p.locks_mul = roundup_pow_of_two(params->locks_mul);
-+	else
-+		ht->p.locks_mul = BUCKET_LOCKS_PER_CPU;
-+
-+	ht->key_len = ht->p.key_len;
-+	if (!params->hashfn) {
-+		ht->p.hashfn = jhash;
-+
-+		if (!(ht->key_len & (sizeof(u32) - 1))) {
-+			ht->key_len /= sizeof(u32);
-+			ht->p.hashfn = rhashtable_jhash2;
-+		}
-+	}
-+
-+	tbl = bucket_table_alloc(ht, size, GFP_KERNEL);
-+	if (tbl == NULL)
-+		return -ENOMEM;
-+
-+	atomic_set(&ht->nelems, 0);
-+
-+	RCU_INIT_POINTER(ht->tbl, tbl);
-+
-+	INIT_WORK(&ht->run_work, rht_deferred_worker);
-+
-+	return 0;
-+}
-+
-+/**
-+ * rhashtable_free_and_destroy - free elements and destroy hash table
-+ * @ht:		the hash table to destroy
-+ * @free_fn:	callback to release resources of element
-+ * @arg:	pointer passed to free_fn
-+ *
-+ * Stops an eventual async resize. If defined, invokes free_fn for each
-+ * element to releasal resources. Please note that RCU protected
-+ * readers may still be accessing the elements. Releasing of resources
-+ * must occur in a compatible manner. Then frees the bucket array.
-+ *
-+ * This function will eventually sleep to wait for an async resize
-+ * to complete. The caller is responsible that no further write operations
-+ * occurs in parallel.
-+ */
-+void rhashtable_free_and_destroy(struct rhashtable *ht,
-+				 void (*free_fn)(void *ptr, void *arg),
-+				 void *arg)
-+{
-+	const struct bucket_table *tbl;
-+	unsigned int i;
-+
-+	cancel_work_sync(&ht->run_work);
-+
-+	mutex_lock(&ht->mutex);
-+	tbl = rht_dereference(ht->tbl, ht);
-+	if (free_fn) {
-+		for (i = 0; i < tbl->size; i++) {
-+			struct rhash_head *pos, *next;
-+
-+			for (pos = rht_dereference(tbl->buckets[i], ht),
-+			     next = !rht_is_a_nulls(pos) ?
-+					rht_dereference(pos->next, ht) : NULL;
-+			     !rht_is_a_nulls(pos);
-+			     pos = next,
-+			     next = !rht_is_a_nulls(pos) ?
-+					rht_dereference(pos->next, ht) : NULL)
-+				free_fn(rht_obj(ht, pos), arg);
-+		}
-+	}
-+
-+	bucket_table_free(tbl);
-+	mutex_unlock(&ht->mutex);
-+}
-+
-+void rhashtable_destroy(struct rhashtable *ht)
-+{
-+	return rhashtable_free_and_destroy(ht, NULL, NULL);
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/rhashtable.h b/drivers/staging/rtl8723cs/os_dep/linux/rhashtable.h
-new file mode 100644
-index 000000000000..b47107ff619f
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/rhashtable.h
-@@ -0,0 +1,827 @@
-+/*
-+ * Resizable, Scalable, Concurrent Hash Table
-+ *
-+ * Copyright (c) 2015 Herbert Xu <herbert@gondor.apana.org.au>
-+ * Copyright (c) 2014-2015 Thomas Graf <tgraf@suug.ch>
-+ * Copyright (c) 2008-2014 Patrick McHardy <kaber@trash.net>
-+ *
-+ * Code partially derived from nft_hash
-+ * Rewritten with rehash code from br_multicast plus single list
-+ * pointer as suggested by Josh Triplett
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#ifndef _LINUX_RHASHTABLE_H
-+#define _LINUX_RHASHTABLE_H
-+
-+#include <linux/atomic.h>
-+#include <linux/compiler.h>
-+#include <linux/err.h>
-+#include <linux/errno.h>
-+#include <linux/jhash.h>
-+#include <linux/list_nulls.h>
-+#include <linux/workqueue.h>
-+#include <linux/mutex.h>
-+#include <linux/rcupdate.h>
-+
-+/*
-+ * The end of the chain is marked with a special nulls marks which has
-+ * the following format:
-+ *
-+ * +-------+-----------------------------------------------------+-+
-+ * | Base  |                      Hash                           |1|
-+ * +-------+-----------------------------------------------------+-+
-+ *
-+ * Base (4 bits) : Reserved to distinguish between multiple tables.
-+ *                 Specified via &struct rhashtable_params.nulls_base.
-+ * Hash (27 bits): Full hash (unmasked) of first element added to bucket
-+ * 1 (1 bit)     : Nulls marker (always set)
-+ *
-+ * The remaining bits of the next pointer remain unused for now.
-+ */
-+#define RHT_BASE_BITS		4
-+#define RHT_HASH_BITS		27
-+#define RHT_BASE_SHIFT		RHT_HASH_BITS
-+
-+/* Base bits plus 1 bit for nulls marker */
-+#define RHT_HASH_RESERVED_SPACE	(RHT_BASE_BITS + 1)
-+
-+struct rhash_head {
-+	struct rhash_head __rcu		*next;
-+};
-+
-+/**
-+ * struct bucket_table - Table of hash buckets
-+ * @size: Number of hash buckets
-+ * @rehash: Current bucket being rehashed
-+ * @hash_rnd: Random seed to fold into hash
-+ * @locks_mask: Mask to apply before accessing locks[]
-+ * @locks: Array of spinlocks protecting individual buckets
-+ * @walkers: List of active walkers
-+ * @rcu: RCU structure for freeing the table
-+ * @future_tbl: Table under construction during rehashing
-+ * @buckets: size * hash buckets
-+ */
-+struct bucket_table {
-+	unsigned int		size;
-+	unsigned int		rehash;
-+	u32			hash_rnd;
-+	unsigned int		locks_mask;
-+	spinlock_t		*locks;
-+	struct list_head	walkers;
-+	struct rcu_head		rcu;
-+
-+	struct bucket_table __rcu *future_tbl;
-+
-+	struct rhash_head __rcu	*buckets[] ____cacheline_aligned_in_smp;
-+};
-+
-+/**
-+ * struct rhashtable_compare_arg - Key for the function rhashtable_compare
-+ * @ht: Hash table
-+ * @key: Key to compare against
-+ */
-+struct rhashtable_compare_arg {
-+	struct rhashtable *ht;
-+	const void *key;
-+};
-+
-+typedef u32 (*rht_hashfn_t)(const void *data, u32 len, u32 seed);
-+typedef u32 (*rht_obj_hashfn_t)(const void *data, u32 len, u32 seed);
-+typedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *arg,
-+			       const void *obj);
-+
-+struct rhashtable;
-+
-+/**
-+ * struct rhashtable_params - Hash table construction parameters
-+ * @nelem_hint: Hint on number of elements, should be 75% of desired size
-+ * @key_len: Length of key
-+ * @key_offset: Offset of key in struct to be hashed
-+ * @head_offset: Offset of rhash_head in struct to be hashed
-+ * @insecure_max_entries: Maximum number of entries (may be exceeded)
-+ * @max_size: Maximum size while expanding
-+ * @min_size: Minimum size while shrinking
-+ * @nulls_base: Base value to generate nulls marker
-+ * @insecure_elasticity: Set to true to disable chain length checks
-+ * @automatic_shrinking: Enable automatic shrinking of tables
-+ * @locks_mul: Number of bucket locks to allocate per cpu (default: 128)
-+ * @hashfn: Hash function (default: jhash2 if !(key_len % 4), or jhash)
-+ * @obj_hashfn: Function to hash object
-+ * @obj_cmpfn: Function to compare key with object
-+ */
-+struct rhashtable_params {
-+	size_t			nelem_hint;
-+	size_t			key_len;
-+	size_t			key_offset;
-+	size_t			head_offset;
-+	unsigned int		insecure_max_entries;
-+	unsigned int		max_size;
-+	unsigned int		min_size;
-+	u32			nulls_base;
-+	bool			insecure_elasticity;
-+	bool			automatic_shrinking;
-+	size_t			locks_mul;
-+	rht_hashfn_t		hashfn;
-+	rht_obj_hashfn_t	obj_hashfn;
-+	rht_obj_cmpfn_t		obj_cmpfn;
-+};
-+
-+/**
-+ * struct rhashtable - Hash table handle
-+ * @tbl: Bucket table
-+ * @nelems: Number of elements in table
-+ * @key_len: Key length for hashfn
-+ * @elasticity: Maximum chain length before rehash
-+ * @p: Configuration parameters
-+ * @run_work: Deferred worker to expand/shrink asynchronously
-+ * @mutex: Mutex to protect current/future table swapping
-+ * @lock: Spin lock to protect walker list
-+ */
-+struct rhashtable {
-+	struct bucket_table __rcu	*tbl;
-+	atomic_t			nelems;
-+	unsigned int			key_len;
-+	unsigned int			elasticity;
-+	struct rhashtable_params	p;
-+	struct work_struct		run_work;
-+	struct mutex                    mutex;
-+	spinlock_t			lock;
-+};
-+
-+/**
-+ * struct rhashtable_walker - Hash table walker
-+ * @list: List entry on list of walkers
-+ * @tbl: The table that we were walking over
-+ */
-+struct rhashtable_walker {
-+	struct list_head list;
-+	struct bucket_table *tbl;
-+};
-+
-+/**
-+ * struct rhashtable_iter - Hash table iterator, fits into netlink cb
-+ * @ht: Table to iterate through
-+ * @p: Current pointer
-+ * @walker: Associated rhashtable walker
-+ * @slot: Current slot
-+ * @skip: Number of entries to skip in slot
-+ */
-+struct rhashtable_iter {
-+	struct rhashtable *ht;
-+	struct rhash_head *p;
-+	struct rhashtable_walker *walker;
-+	unsigned int slot;
-+	unsigned int skip;
-+};
-+
-+static inline unsigned long rht_marker(const struct rhashtable *ht, u32 hash)
-+{
-+	return NULLS_MARKER(ht->p.nulls_base + hash);
-+}
-+
-+#define INIT_RHT_NULLS_HEAD(ptr, ht, hash) \
-+	((ptr) = (typeof(ptr)) rht_marker(ht, hash))
-+
-+static inline bool rht_is_a_nulls(const struct rhash_head *ptr)
-+{
-+	return ((unsigned long) ptr & 1);
-+}
-+
-+static inline unsigned long rht_get_nulls_value(const struct rhash_head *ptr)
-+{
-+	return ((unsigned long) ptr) >> 1;
-+}
-+
-+static inline void *rht_obj(const struct rhashtable *ht,
-+			    const struct rhash_head *he)
-+{
-+	return (char *)he - ht->p.head_offset;
-+}
-+
-+static inline unsigned int rht_bucket_index(const struct bucket_table *tbl,
-+					    unsigned int hash)
-+{
-+	return (hash >> RHT_HASH_RESERVED_SPACE) & (tbl->size - 1);
-+}
-+
-+static inline unsigned int rht_key_hashfn(
-+	struct rhashtable *ht, const struct bucket_table *tbl,
-+	const void *key, const struct rhashtable_params params)
-+{
-+	unsigned int hash;
-+
-+	/* params must be equal to ht->p if it isn't constant. */
-+	if (!__builtin_constant_p(params.key_len))
-+		hash = ht->p.hashfn(key, ht->key_len, tbl->hash_rnd);
-+	else if (params.key_len) {
-+		unsigned int key_len = params.key_len;
-+
-+		if (params.hashfn)
-+			hash = params.hashfn(key, key_len, tbl->hash_rnd);
-+		else if (key_len & (sizeof(u32) - 1))
-+			hash = jhash(key, key_len, tbl->hash_rnd);
-+		else
-+			hash = jhash2(key, key_len / sizeof(u32),
-+				      tbl->hash_rnd);
-+	} else {
-+		unsigned int key_len = ht->p.key_len;
-+
-+		if (params.hashfn)
-+			hash = params.hashfn(key, key_len, tbl->hash_rnd);
-+		else
-+			hash = jhash(key, key_len, tbl->hash_rnd);
-+	}
-+
-+	return rht_bucket_index(tbl, hash);
-+}
-+
-+static inline unsigned int rht_head_hashfn(
-+	struct rhashtable *ht, const struct bucket_table *tbl,
-+	const struct rhash_head *he, const struct rhashtable_params params)
-+{
-+	const char *ptr = rht_obj(ht, he);
-+
-+	return likely(params.obj_hashfn) ?
-+	       rht_bucket_index(tbl, params.obj_hashfn(ptr, params.key_len ?:
-+							    ht->p.key_len,
-+						       tbl->hash_rnd)) :
-+	       rht_key_hashfn(ht, tbl, ptr + params.key_offset, params);
-+}
-+
-+/**
-+ * rht_grow_above_75 - returns true if nelems > 0.75 * table-size
-+ * @ht:		hash table
-+ * @tbl:	current table
-+ */
-+static inline bool rht_grow_above_75(const struct rhashtable *ht,
-+				     const struct bucket_table *tbl)
-+{
-+	/* Expand table when exceeding 75% load */
-+	return atomic_read(&ht->nelems) > (tbl->size / 4 * 3) &&
-+	       (!ht->p.max_size || tbl->size < ht->p.max_size);
-+}
-+
-+/**
-+ * rht_shrink_below_30 - returns true if nelems < 0.3 * table-size
-+ * @ht:		hash table
-+ * @tbl:	current table
-+ */
-+static inline bool rht_shrink_below_30(const struct rhashtable *ht,
-+				       const struct bucket_table *tbl)
-+{
-+	/* Shrink table beneath 30% load */
-+	return atomic_read(&ht->nelems) < (tbl->size * 3 / 10) &&
-+	       tbl->size > ht->p.min_size;
-+}
-+
-+/**
-+ * rht_grow_above_100 - returns true if nelems > table-size
-+ * @ht:		hash table
-+ * @tbl:	current table
-+ */
-+static inline bool rht_grow_above_100(const struct rhashtable *ht,
-+				      const struct bucket_table *tbl)
-+{
-+	return atomic_read(&ht->nelems) > tbl->size &&
-+		(!ht->p.max_size || tbl->size < ht->p.max_size);
-+}
-+
-+/**
-+ * rht_grow_above_max - returns true if table is above maximum
-+ * @ht:		hash table
-+ * @tbl:	current table
-+ */
-+static inline bool rht_grow_above_max(const struct rhashtable *ht,
-+				      const struct bucket_table *tbl)
-+{
-+	return ht->p.insecure_max_entries &&
-+	       atomic_read(&ht->nelems) >= ht->p.insecure_max_entries;
-+}
-+
-+/* The bucket lock is selected based on the hash and protects mutations
-+ * on a group of hash buckets.
-+ *
-+ * A maximum of tbl->size/2 bucket locks is allocated. This ensures that
-+ * a single lock always covers both buckets which may both contains
-+ * entries which link to the same bucket of the old table during resizing.
-+ * This allows to simplify the locking as locking the bucket in both
-+ * tables during resize always guarantee protection.
-+ *
-+ * IMPORTANT: When holding the bucket lock of both the old and new table
-+ * during expansions and shrinking, the old bucket lock must always be
-+ * acquired first.
-+ */
-+static inline spinlock_t *rht_bucket_lock(const struct bucket_table *tbl,
-+					  unsigned int hash)
-+{
-+	return &tbl->locks[hash & tbl->locks_mask];
-+}
-+
-+#ifdef CONFIG_PROVE_LOCKING
-+int lockdep_rht_mutex_is_held(struct rhashtable *ht);
-+int lockdep_rht_bucket_is_held(const struct bucket_table *tbl, u32 hash);
-+#else
-+static inline int lockdep_rht_mutex_is_held(struct rhashtable *ht)
-+{
-+	return 1;
-+}
-+
-+static inline int lockdep_rht_bucket_is_held(const struct bucket_table *tbl,
-+					     u32 hash)
-+{
-+	return 1;
-+}
-+#endif /* CONFIG_PROVE_LOCKING */
-+
-+int rhashtable_init(struct rhashtable *ht,
-+		    const struct rhashtable_params *params);
-+
-+struct bucket_table *rhashtable_insert_slow(struct rhashtable *ht,
-+					    const void *key,
-+					    struct rhash_head *obj,
-+					    struct bucket_table *old_tbl);
-+int rhashtable_insert_rehash(struct rhashtable *ht, struct bucket_table *tbl);
-+
-+int rhashtable_walk_init(struct rhashtable *ht, struct rhashtable_iter *iter);
-+void rhashtable_walk_exit(struct rhashtable_iter *iter);
-+int rhashtable_walk_start(struct rhashtable_iter *iter) __acquires(RCU);
-+void *rhashtable_walk_next(struct rhashtable_iter *iter);
-+void rhashtable_walk_stop(struct rhashtable_iter *iter) __releases(RCU);
-+
-+void rhashtable_free_and_destroy(struct rhashtable *ht,
-+				 void (*free_fn)(void *ptr, void *arg),
-+				 void *arg);
-+void rhashtable_destroy(struct rhashtable *ht);
-+
-+#define rht_dereference(p, ht) \
-+	rcu_dereference_protected(p, lockdep_rht_mutex_is_held(ht))
-+
-+#define rht_dereference_rcu(p, ht) \
-+	rcu_dereference_check(p, lockdep_rht_mutex_is_held(ht))
-+
-+#define rht_dereference_bucket(p, tbl, hash) \
-+	rcu_dereference_protected(p, lockdep_rht_bucket_is_held(tbl, hash))
-+
-+#define rht_dereference_bucket_rcu(p, tbl, hash) \
-+	rcu_dereference_check(p, lockdep_rht_bucket_is_held(tbl, hash))
-+
-+#define rht_entry(tpos, pos, member) \
-+	({ tpos = container_of(pos, typeof(*tpos), member); 1; })
-+
-+/**
-+ * rht_for_each_continue - continue iterating over hash chain
-+ * @pos:	the &struct rhash_head to use as a loop cursor.
-+ * @head:	the previous &struct rhash_head to continue from
-+ * @tbl:	the &struct bucket_table
-+ * @hash:	the hash value / bucket index
-+ */
-+#define rht_for_each_continue(pos, head, tbl, hash) \
-+	for (pos = rht_dereference_bucket(head, tbl, hash); \
-+	     !rht_is_a_nulls(pos); \
-+	     pos = rht_dereference_bucket((pos)->next, tbl, hash))
-+
-+/**
-+ * rht_for_each - iterate over hash chain
-+ * @pos:	the &struct rhash_head to use as a loop cursor.
-+ * @tbl:	the &struct bucket_table
-+ * @hash:	the hash value / bucket index
-+ */
-+#define rht_for_each(pos, tbl, hash) \
-+	rht_for_each_continue(pos, (tbl)->buckets[hash], tbl, hash)
-+
-+/**
-+ * rht_for_each_entry_continue - continue iterating over hash chain
-+ * @tpos:	the type * to use as a loop cursor.
-+ * @pos:	the &struct rhash_head to use as a loop cursor.
-+ * @head:	the previous &struct rhash_head to continue from
-+ * @tbl:	the &struct bucket_table
-+ * @hash:	the hash value / bucket index
-+ * @member:	name of the &struct rhash_head within the hashable struct.
-+ */
-+#define rht_for_each_entry_continue(tpos, pos, head, tbl, hash, member)	\
-+	for (pos = rht_dereference_bucket(head, tbl, hash);		\
-+	     (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member);	\
-+	     pos = rht_dereference_bucket((pos)->next, tbl, hash))
-+
-+/**
-+ * rht_for_each_entry - iterate over hash chain of given type
-+ * @tpos:	the type * to use as a loop cursor.
-+ * @pos:	the &struct rhash_head to use as a loop cursor.
-+ * @tbl:	the &struct bucket_table
-+ * @hash:	the hash value / bucket index
-+ * @member:	name of the &struct rhash_head within the hashable struct.
-+ */
-+#define rht_for_each_entry(tpos, pos, tbl, hash, member)		\
-+	rht_for_each_entry_continue(tpos, pos, (tbl)->buckets[hash],	\
-+				    tbl, hash, member)
-+
-+/**
-+ * rht_for_each_entry_safe - safely iterate over hash chain of given type
-+ * @tpos:	the type * to use as a loop cursor.
-+ * @pos:	the &struct rhash_head to use as a loop cursor.
-+ * @next:	the &struct rhash_head to use as next in loop cursor.
-+ * @tbl:	the &struct bucket_table
-+ * @hash:	the hash value / bucket index
-+ * @member:	name of the &struct rhash_head within the hashable struct.
-+ *
-+ * This hash chain list-traversal primitive allows for the looped code to
-+ * remove the loop cursor from the list.
-+ */
-+#define rht_for_each_entry_safe(tpos, pos, next, tbl, hash, member)	    \
-+	for (pos = rht_dereference_bucket((tbl)->buckets[hash], tbl, hash), \
-+	     next = !rht_is_a_nulls(pos) ?				    \
-+		       rht_dereference_bucket(pos->next, tbl, hash) : NULL; \
-+	     (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member);	    \
-+	     pos = next,						    \
-+	     next = !rht_is_a_nulls(pos) ?				    \
-+		       rht_dereference_bucket(pos->next, tbl, hash) : NULL)
-+
-+/**
-+ * rht_for_each_rcu_continue - continue iterating over rcu hash chain
-+ * @pos:	the &struct rhash_head to use as a loop cursor.
-+ * @head:	the previous &struct rhash_head to continue from
-+ * @tbl:	the &struct bucket_table
-+ * @hash:	the hash value / bucket index
-+ *
-+ * This hash chain list-traversal primitive may safely run concurrently with
-+ * the _rcu mutation primitives such as rhashtable_insert() as long as the
-+ * traversal is guarded by rcu_read_lock().
-+ */
-+#define rht_for_each_rcu_continue(pos, head, tbl, hash)			\
-+	for (({barrier(); }),						\
-+	     pos = rht_dereference_bucket_rcu(head, tbl, hash);		\
-+	     !rht_is_a_nulls(pos);					\
-+	     pos = rcu_dereference_raw(pos->next))
-+
-+/**
-+ * rht_for_each_rcu - iterate over rcu hash chain
-+ * @pos:	the &struct rhash_head to use as a loop cursor.
-+ * @tbl:	the &struct bucket_table
-+ * @hash:	the hash value / bucket index
-+ *
-+ * This hash chain list-traversal primitive may safely run concurrently with
-+ * the _rcu mutation primitives such as rhashtable_insert() as long as the
-+ * traversal is guarded by rcu_read_lock().
-+ */
-+#define rht_for_each_rcu(pos, tbl, hash)				\
-+	rht_for_each_rcu_continue(pos, (tbl)->buckets[hash], tbl, hash)
-+
-+/**
-+ * rht_for_each_entry_rcu_continue - continue iterating over rcu hash chain
-+ * @tpos:	the type * to use as a loop cursor.
-+ * @pos:	the &struct rhash_head to use as a loop cursor.
-+ * @head:	the previous &struct rhash_head to continue from
-+ * @tbl:	the &struct bucket_table
-+ * @hash:	the hash value / bucket index
-+ * @member:	name of the &struct rhash_head within the hashable struct.
-+ *
-+ * This hash chain list-traversal primitive may safely run concurrently with
-+ * the _rcu mutation primitives such as rhashtable_insert() as long as the
-+ * traversal is guarded by rcu_read_lock().
-+ */
-+#define rht_for_each_entry_rcu_continue(tpos, pos, head, tbl, hash, member) \
-+	for (({barrier(); }),						    \
-+	     pos = rht_dereference_bucket_rcu(head, tbl, hash);		    \
-+	     (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member);	    \
-+	     pos = rht_dereference_bucket_rcu(pos->next, tbl, hash))
-+
-+/**
-+ * rht_for_each_entry_rcu - iterate over rcu hash chain of given type
-+ * @tpos:	the type * to use as a loop cursor.
-+ * @pos:	the &struct rhash_head to use as a loop cursor.
-+ * @tbl:	the &struct bucket_table
-+ * @hash:	the hash value / bucket index
-+ * @member:	name of the &struct rhash_head within the hashable struct.
-+ *
-+ * This hash chain list-traversal primitive may safely run concurrently with
-+ * the _rcu mutation primitives such as rhashtable_insert() as long as the
-+ * traversal is guarded by rcu_read_lock().
-+ */
-+#define rht_for_each_entry_rcu(tpos, pos, tbl, hash, member)		\
-+	rht_for_each_entry_rcu_continue(tpos, pos, (tbl)->buckets[hash],\
-+					tbl, hash, member)
-+
-+static inline int rhashtable_compare(struct rhashtable_compare_arg *arg,
-+				     const void *obj)
-+{
-+	struct rhashtable *ht = arg->ht;
-+	const char *ptr = obj;
-+
-+	return memcmp(ptr + ht->p.key_offset, arg->key, ht->p.key_len);
-+}
-+
-+/**
-+ * rhashtable_lookup_fast - search hash table, inlined version
-+ * @ht:		hash table
-+ * @key:	the pointer to the key
-+ * @params:	hash table parameters
-+ *
-+ * Computes the hash value for the key and traverses the bucket chain looking
-+ * for a entry with an identical key. The first matching entry is returned.
-+ *
-+ * Returns the first entry on which the compare function returned true.
-+ */
-+static inline void *rhashtable_lookup_fast(
-+	struct rhashtable *ht, const void *key,
-+	const struct rhashtable_params params)
-+{
-+	struct rhashtable_compare_arg arg = {
-+		.ht = ht,
-+		.key = key,
-+	};
-+	const struct bucket_table *tbl;
-+	struct rhash_head *he;
-+	unsigned int hash;
-+
-+	rcu_read_lock();
-+
-+	tbl = rht_dereference_rcu(ht->tbl, ht);
-+restart:
-+	hash = rht_key_hashfn(ht, tbl, key, params);
-+	rht_for_each_rcu(he, tbl, hash) {
-+		if (params.obj_cmpfn ?
-+		    params.obj_cmpfn(&arg, rht_obj(ht, he)) :
-+		    rhashtable_compare(&arg, rht_obj(ht, he)))
-+			continue;
-+		rcu_read_unlock();
-+		return rht_obj(ht, he);
-+	}
-+
-+	/* Ensure we see any new tables. */
-+	smp_rmb();
-+
-+	tbl = rht_dereference_rcu(tbl->future_tbl, ht);
-+	if (unlikely(tbl))
-+		goto restart;
-+	rcu_read_unlock();
-+
-+	return NULL;
-+}
-+
-+/* Internal function, please use rhashtable_insert_fast() instead */
-+static inline int __rhashtable_insert_fast(
-+	struct rhashtable *ht, const void *key, struct rhash_head *obj,
-+	const struct rhashtable_params params)
-+{
-+	struct rhashtable_compare_arg arg = {
-+		.ht = ht,
-+		.key = key,
-+	};
-+	struct bucket_table *tbl, *new_tbl;
-+	struct rhash_head *head;
-+	spinlock_t *lock;
-+	unsigned int elasticity;
-+	unsigned int hash;
-+	int err;
-+
-+restart:
-+	rcu_read_lock();
-+
-+	tbl = rht_dereference_rcu(ht->tbl, ht);
-+
-+	/* All insertions must grab the oldest table containing
-+	 * the hashed bucket that is yet to be rehashed.
-+	 */
-+	for (;;) {
-+		hash = rht_head_hashfn(ht, tbl, obj, params);
-+		lock = rht_bucket_lock(tbl, hash);
-+		spin_lock_bh(lock);
-+
-+		if (tbl->rehash <= hash)
-+			break;
-+
-+		spin_unlock_bh(lock);
-+		tbl = rht_dereference_rcu(tbl->future_tbl, ht);
-+	}
-+
-+	new_tbl = rht_dereference_rcu(tbl->future_tbl, ht);
-+	if (unlikely(new_tbl)) {
-+		tbl = rhashtable_insert_slow(ht, key, obj, new_tbl);
-+		if (!IS_ERR_OR_NULL(tbl))
-+			goto slow_path;
-+
-+		err = PTR_ERR(tbl);
-+		goto out;
-+	}
-+
-+	err = -E2BIG;
-+	if (unlikely(rht_grow_above_max(ht, tbl)))
-+		goto out;
-+
-+	if (unlikely(rht_grow_above_100(ht, tbl))) {
-+slow_path:
-+		spin_unlock_bh(lock);
-+		err = rhashtable_insert_rehash(ht, tbl);
-+		rcu_read_unlock();
-+		if (err)
-+			return err;
-+
-+		goto restart;
-+	}
-+
-+	err = -EEXIST;
-+	elasticity = ht->elasticity;
-+	rht_for_each(head, tbl, hash) {
-+		if (key &&
-+		    unlikely(!(params.obj_cmpfn ?
-+			       params.obj_cmpfn(&arg, rht_obj(ht, head)) :
-+			       rhashtable_compare(&arg, rht_obj(ht, head)))))
-+			goto out;
-+		if (!--elasticity)
-+			goto slow_path;
-+	}
-+
-+	err = 0;
-+
-+	head = rht_dereference_bucket(tbl->buckets[hash], tbl, hash);
-+
-+	RCU_INIT_POINTER(obj->next, head);
-+
-+	rcu_assign_pointer(tbl->buckets[hash], obj);
-+
-+	atomic_inc(&ht->nelems);
-+	if (rht_grow_above_75(ht, tbl))
-+		schedule_work(&ht->run_work);
-+
-+out:
-+	spin_unlock_bh(lock);
-+	rcu_read_unlock();
-+
-+	return err;
-+}
-+
-+/**
-+ * rhashtable_insert_fast - insert object into hash table
-+ * @ht:		hash table
-+ * @obj:	pointer to hash head inside object
-+ * @params:	hash table parameters
-+ *
-+ * Will take a per bucket spinlock to protect against mutual mutations
-+ * on the same bucket. Multiple insertions may occur in parallel unless
-+ * they map to the same bucket lock.
-+ *
-+ * It is safe to call this function from atomic context.
-+ *
-+ * Will trigger an automatic deferred table resizing if the size grows
-+ * beyond the watermark indicated by grow_decision() which can be passed
-+ * to rhashtable_init().
-+ */
-+static inline int rhashtable_insert_fast(
-+	struct rhashtable *ht, struct rhash_head *obj,
-+	const struct rhashtable_params params)
-+{
-+	return __rhashtable_insert_fast(ht, NULL, obj, params);
-+}
-+
-+/**
-+ * rhashtable_lookup_insert_fast - lookup and insert object into hash table
-+ * @ht:		hash table
-+ * @obj:	pointer to hash head inside object
-+ * @params:	hash table parameters
-+ *
-+ * Locks down the bucket chain in both the old and new table if a resize
-+ * is in progress to ensure that writers can't remove from the old table
-+ * and can't insert to the new table during the atomic operation of search
-+ * and insertion. Searches for duplicates in both the old and new table if
-+ * a resize is in progress.
-+ *
-+ * This lookup function may only be used for fixed key hash table (key_len
-+ * parameter set). It will BUG() if used inappropriately.
-+ *
-+ * It is safe to call this function from atomic context.
-+ *
-+ * Will trigger an automatic deferred table resizing if the size grows
-+ * beyond the watermark indicated by grow_decision() which can be passed
-+ * to rhashtable_init().
-+ */
-+static inline int rhashtable_lookup_insert_fast(
-+	struct rhashtable *ht, struct rhash_head *obj,
-+	const struct rhashtable_params params)
-+{
-+	const char *key = rht_obj(ht, obj);
-+
-+	BUG_ON(ht->p.obj_hashfn);
-+
-+	return __rhashtable_insert_fast(ht, key + ht->p.key_offset, obj,
-+					params);
-+}
-+
-+/**
-+ * rhashtable_lookup_insert_key - search and insert object to hash table
-+ *				  with explicit key
-+ * @ht:		hash table
-+ * @key:	key
-+ * @obj:	pointer to hash head inside object
-+ * @params:	hash table parameters
-+ *
-+ * Locks down the bucket chain in both the old and new table if a resize
-+ * is in progress to ensure that writers can't remove from the old table
-+ * and can't insert to the new table during the atomic operation of search
-+ * and insertion. Searches for duplicates in both the old and new table if
-+ * a resize is in progress.
-+ *
-+ * Lookups may occur in parallel with hashtable mutations and resizing.
-+ *
-+ * Will trigger an automatic deferred table resizing if the size grows
-+ * beyond the watermark indicated by grow_decision() which can be passed
-+ * to rhashtable_init().
-+ *
-+ * Returns zero on success.
-+ */
-+static inline int rhashtable_lookup_insert_key(
-+	struct rhashtable *ht, const void *key, struct rhash_head *obj,
-+	const struct rhashtable_params params)
-+{
-+	BUG_ON(!ht->p.obj_hashfn || !key);
-+
-+	return __rhashtable_insert_fast(ht, key, obj, params);
-+}
-+
-+/* Internal function, please use rhashtable_remove_fast() instead */
-+static inline int __rhashtable_remove_fast(
-+	struct rhashtable *ht, struct bucket_table *tbl,
-+	struct rhash_head *obj, const struct rhashtable_params params)
-+{
-+	struct rhash_head __rcu **pprev;
-+	struct rhash_head *he;
-+	spinlock_t * lock;
-+	unsigned int hash;
-+	int err = -ENOENT;
-+
-+	hash = rht_head_hashfn(ht, tbl, obj, params);
-+	lock = rht_bucket_lock(tbl, hash);
-+
-+	spin_lock_bh(lock);
-+
-+	pprev = &tbl->buckets[hash];
-+	rht_for_each(he, tbl, hash) {
-+		if (he != obj) {
-+			pprev = &he->next;
-+			continue;
-+		}
-+
-+		rcu_assign_pointer(*pprev, obj->next);
-+		err = 0;
-+		break;
-+	}
-+
-+	spin_unlock_bh(lock);
-+
-+	return err;
-+}
-+
-+/**
-+ * rhashtable_remove_fast - remove object from hash table
-+ * @ht:		hash table
-+ * @obj:	pointer to hash head inside object
-+ * @params:	hash table parameters
-+ *
-+ * Since the hash chain is single linked, the removal operation needs to
-+ * walk the bucket chain upon removal. The removal operation is thus
-+ * considerable slow if the hash table is not correctly sized.
-+ *
-+ * Will automatically shrink the table via rhashtable_expand() if the
-+ * shrink_decision function specified at rhashtable_init() returns true.
-+ *
-+ * Returns zero on success, -ENOENT if the entry could not be found.
-+ */
-+static inline int rhashtable_remove_fast(
-+	struct rhashtable *ht, struct rhash_head *obj,
-+	const struct rhashtable_params params)
-+{
-+	struct bucket_table *tbl;
-+	int err;
-+
-+	rcu_read_lock();
-+
-+	tbl = rht_dereference_rcu(ht->tbl, ht);
-+
-+	/* Because we have already taken (and released) the bucket
-+	 * lock in old_tbl, if we find that future_tbl is not yet
-+	 * visible then that guarantees the entry to still be in
-+	 * the old tbl if it exists.
-+	 */
-+	while ((err = __rhashtable_remove_fast(ht, tbl, obj, params)) &&
-+	       (tbl = rht_dereference_rcu(tbl->future_tbl, ht)))
-+		;
-+
-+	if (err)
-+		goto out;
-+
-+	atomic_dec(&ht->nelems);
-+	if (unlikely(ht->p.automatic_shrinking &&
-+		     rht_shrink_below_30(ht, tbl)))
-+		schedule_work(&ht->run_work);
-+
-+out:
-+	rcu_read_unlock();
-+
-+	return err;
-+}
-+
-+#endif /* _LINUX_RHASHTABLE_H */
-+
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/rtw_android.c b/drivers/staging/rtl8723cs/os_dep/linux/rtw_android.c
-new file mode 100644
-index 000000000000..10f8f232d696
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/rtw_android.c
-@@ -0,0 +1,1346 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+#include <linux/gpio.h>
-+#endif
-+
-+#include <drv_types.h>
-+
-+#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)
-+#include <linux/platform_device.h>
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	#include <linux/wlan_plat.h>
-+#else
-+	#include <linux/wifi_tiwlan.h>
-+#endif
-+#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
-+#define strnicmp	strncasecmp
-+#endif /* Linux kernel >= 4.0.0 */
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#endif
-+
-+#include "rtw_version.h"
-+
-+extern void macstr2num(u8 *dst, u8 *src);
-+
-+const char *android_wifi_cmd_str[ANDROID_WIFI_CMD_MAX] = {
-+	"START",
-+	"STOP",
-+	"SCAN-ACTIVE",
-+	"SCAN-PASSIVE",
-+	"RSSI",
-+	"LINKSPEED",
-+	"RXFILTER-START",
-+	"RXFILTER-STOP",
-+	"RXFILTER-ADD",
-+	"RXFILTER-REMOVE",
-+	"BTCOEXSCAN-START",
-+	"BTCOEXSCAN-STOP",
-+	"BTCOEXMODE",
-+	"SETSUSPENDMODE",
-+	"SETSUSPENDOPT",
-+	"P2P_DEV_ADDR",
-+	"SETFWPATH",
-+	"SETBAND",
-+	"GETBAND",
-+	"COUNTRY",
-+	"P2P_SET_NOA",
-+	"P2P_GET_NOA",
-+	"P2P_SET_PS",
-+	"SET_AP_WPS_P2P_IE",
-+
-+	"MIRACAST",
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+	"PNOSSIDCLR",
-+	"PNOSETUP",
-+	"PNOFORCE",
-+	"PNODEBUG",
-+#endif
-+
-+	"MACADDR",
-+
-+	"BLOCK_SCAN",
-+	"BLOCK",
-+	"WFD-ENABLE",
-+	"WFD-DISABLE",
-+	"WFD-SET-TCPPORT",
-+	"WFD-SET-MAXTPUT",
-+	"WFD-SET-DEVTYPE",
-+	"SET_DTIM",
-+	"HOSTAPD_SET_MACADDR_ACL",
-+	"HOSTAPD_ACL_ADD_STA",
-+	"HOSTAPD_ACL_REMOVE_STA",
-+#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
-+	"GTK_REKEY_OFFLOAD",
-+#endif /* CONFIG_GTK_OL */
-+/*	Private command for	P2P disable*/
-+	"P2P_DISABLE",
-+	"SET_AEK",
-+	"EXT_AUTH_STATUS",
-+	"DRIVER_VERSION"
-+};
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+#define PNO_TLV_PREFIX			'S'
-+#define PNO_TLV_VERSION			'1'
-+#define PNO_TLV_SUBVERSION		'2'
-+#define PNO_TLV_RESERVED		'0'
-+#define PNO_TLV_TYPE_SSID_IE	'S'
-+#define PNO_TLV_TYPE_TIME		'T'
-+#define PNO_TLV_FREQ_REPEAT		'R'
-+#define PNO_TLV_FREQ_EXPO_MAX	'M'
-+
-+typedef struct cmd_tlv {
-+	char prefix;
-+	char version;
-+	char subver;
-+	char reserved;
-+} cmd_tlv_t;
-+
-+#ifdef CONFIG_PNO_SET_DEBUG
-+char pno_in_example[] = {
-+	'P', 'N', 'O', 'S', 'E', 'T', 'U', 'P', ' ',
-+	'S', '1', '2', '0',
-+	'S',	/* 1 */
-+	0x05,
-+	'd', 'l', 'i', 'n', 'k',
-+	'S',	/* 2 */
-+	0x06,
-+	'B', 'U', 'F', 'B', 'U', 'F',
-+	'S',	/* 3 */
-+	0x20,
-+	'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '!', '@', '#', '$', '%', '^',
-+	'S',	/* 4 */
-+	0x0a,
-+	'!', '@', '#', '$', '%', '^', '&', '*', '(', ')',
-+	'T',
-+	'0', '5',
-+	'R',
-+	'2',
-+	'M',
-+	'2',
-+	0x00
-+};
-+#endif /* CONFIG_PNO_SET_DEBUG */
-+#endif /* PNO_SUPPORT */
-+
-+typedef struct android_wifi_priv_cmd {
-+	char *buf;
-+	int used_len;
-+	int total_len;
-+} android_wifi_priv_cmd;
-+
-+#ifdef CONFIG_COMPAT
-+typedef struct compat_android_wifi_priv_cmd {
-+	compat_uptr_t buf;
-+	int used_len;
-+	int total_len;
-+} compat_android_wifi_priv_cmd;
-+#endif /* CONFIG_COMPAT */
-+
-+/**
-+ * Local (static) functions and variables
-+ */
-+
-+/* Initialize g_wifi_on to 1 so dhd_bus_start will be called for the first
-+ * time (only) in dhd_open, subsequential wifi on will be handled by
-+ * wl_android_wifi_on
-+ */
-+static int g_wifi_on = _TRUE;
-+
-+unsigned int oob_irq = 0;
-+unsigned int oob_gpio = 0;
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+/*
-+ * rtw_android_pno_setup
-+ * Description:
-+ * This is used for private command.
-+ *
-+ * Parameter:
-+ * net: net_device
-+ * command: parameters from private command
-+ * total_len: the length of the command.
-+ *
-+ * */
-+static int rtw_android_pno_setup(struct net_device *net, char *command, int total_len)
-+{
-+	pno_ssid_t pno_ssids_local[MAX_PNO_LIST_COUNT];
-+	int res = -1;
-+	int nssid = 0;
-+	cmd_tlv_t *cmd_tlv_temp;
-+	char *str_ptr;
-+	int tlv_size_left;
-+	int pno_time = 0;
-+	int pno_repeat = 0;
-+	int pno_freq_expo_max = 0;
-+	int cmdlen = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_PNOSETUP_SET]) + 1;
-+
-+#ifdef CONFIG_PNO_SET_DEBUG
-+	int i;
-+	char *p;
-+	p = pno_in_example;
-+
-+	total_len = sizeof(pno_in_example);
-+	str_ptr = p + cmdlen;
-+#else
-+	str_ptr = command + cmdlen;
-+#endif
-+
-+	if (total_len < (cmdlen + sizeof(cmd_tlv_t))) {
-+		RTW_INFO("%s argument=%d less min size\n", __func__, total_len);
-+		goto exit_proc;
-+	}
-+
-+	tlv_size_left = total_len - cmdlen;
-+
-+	cmd_tlv_temp = (cmd_tlv_t *)str_ptr;
-+	memset(pno_ssids_local, 0, sizeof(pno_ssids_local));
-+
-+	if ((cmd_tlv_temp->prefix == PNO_TLV_PREFIX) &&
-+	    (cmd_tlv_temp->version == PNO_TLV_VERSION) &&
-+	    (cmd_tlv_temp->subver == PNO_TLV_SUBVERSION)) {
-+
-+		str_ptr += sizeof(cmd_tlv_t);
-+		tlv_size_left -= sizeof(cmd_tlv_t);
-+
-+		nssid = rtw_parse_ssid_list_tlv(&str_ptr, pno_ssids_local,
-+			     MAX_PNO_LIST_COUNT, &tlv_size_left);
-+		if (nssid <= 0) {
-+			RTW_INFO("SSID is not presented or corrupted ret=%d\n", nssid);
-+			goto exit_proc;
-+		} else {
-+			if ((str_ptr[0] != PNO_TLV_TYPE_TIME) || (tlv_size_left <= 1)) {
-+				RTW_INFO("%s scan duration corrupted field size %d\n",
-+					 __func__, tlv_size_left);
-+				goto exit_proc;
-+			}
-+			str_ptr++;
-+			pno_time = simple_strtoul(str_ptr, &str_ptr, 16);
-+			RTW_INFO("%s: pno_time=%d\n", __func__, pno_time);
-+
-+			if (str_ptr[0] != 0) {
-+				if ((str_ptr[0] != PNO_TLV_FREQ_REPEAT)) {
-+					RTW_INFO("%s pno repeat : corrupted field\n",
-+						 __func__);
-+					goto exit_proc;
-+				}
-+				str_ptr++;
-+				pno_repeat = simple_strtoul(str_ptr, &str_ptr, 16);
-+				RTW_INFO("%s :got pno_repeat=%d\n", __FUNCTION__, pno_repeat);
-+				if (str_ptr[0] != PNO_TLV_FREQ_EXPO_MAX) {
-+					RTW_INFO("%s FREQ_EXPO_MAX corrupted field size\n",
-+						 __func__);
-+					goto exit_proc;
-+				}
-+				str_ptr++;
-+				pno_freq_expo_max = simple_strtoul(str_ptr, &str_ptr, 16);
-+				RTW_INFO("%s: pno_freq_expo_max=%d\n",
-+					 __func__, pno_freq_expo_max);
-+			}
-+		}
-+	} else {
-+		RTW_INFO("%s get wrong TLV command\n", __FUNCTION__);
-+		goto exit_proc;
-+	}
-+
-+	res = rtw_dev_pno_set(net, pno_ssids_local, nssid, pno_time, pno_repeat, pno_freq_expo_max);
-+
-+#ifdef CONFIG_PNO_SET_DEBUG
-+	rtw_dev_pno_debug(net);
-+#endif
-+
-+exit_proc:
-+	return res;
-+}
-+
-+/*
-+ * rtw_android_cfg80211_pno_setup
-+ * Description:
-+ * This is used for cfg80211 sched_scan.
-+ *
-+ * Parameter:
-+ * net: net_device
-+ * request: cfg80211_request
-+ * */
-+
-+int rtw_android_cfg80211_pno_setup(struct net_device *net,
-+		   struct cfg80211_ssid *ssids, int n_ssids, int interval)
-+{
-+	int res = -1;
-+	int nssid = 0;
-+	int pno_time = 0;
-+	int pno_repeat = 0;
-+	int pno_freq_expo_max = 0;
-+	int index = 0;
-+	pno_ssid_t pno_ssids_local[MAX_PNO_LIST_COUNT];
-+
-+	if (n_ssids > MAX_PNO_LIST_COUNT || n_ssids < 0) {
-+		RTW_INFO("%s: nssids(%d) is invalid.\n", __func__, n_ssids);
-+		return -EINVAL;
-+	}
-+
-+	memset(pno_ssids_local, 0, sizeof(pno_ssids_local));
-+
-+	nssid = n_ssids;
-+
-+	for (index = 0 ; index < nssid ; index++) {
-+		pno_ssids_local[index].SSID_len = ssids[index].ssid_len;
-+		memcpy(pno_ssids_local[index].SSID, ssids[index].ssid,
-+		       ssids[index].ssid_len);
-+	}
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)
-+	if(ssids)
-+		rtw_mfree((u8 *)ssids, (n_ssids * sizeof(struct cfg80211_ssid)));
-+#endif
-+	pno_time = (interval / 1000);
-+
-+	RTW_INFO("%s: nssids: %d, pno_time=%d\n", __func__, nssid, pno_time);
-+
-+	res = rtw_dev_pno_set(net, pno_ssids_local, nssid, pno_time,
-+			      pno_repeat, pno_freq_expo_max);
-+
-+#ifdef CONFIG_PNO_SET_DEBUG
-+	rtw_dev_pno_debug(net);
-+#endif
-+exit_proc:
-+	return res;
-+}
-+
-+int rtw_android_pno_enable(struct net_device *net, int pno_enable)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
-+	struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
-+
-+	if (pwrctl) {
-+		pwrctl->wowlan_pno_enable = pno_enable;
-+		RTW_INFO("%s: wowlan_pno_enable: %d\n", __func__, pwrctl->wowlan_pno_enable);
-+		if (pwrctl->wowlan_pno_enable == 0) {
-+			if (pwrctl->pnlo_info != NULL) {
-+				rtw_mfree((u8 *)pwrctl->pnlo_info, sizeof(pno_nlo_info_t));
-+				pwrctl->pnlo_info = NULL;
-+			}
-+			if (pwrctl->pno_ssid_list != NULL) {
-+				rtw_mfree((u8 *)pwrctl->pno_ssid_list, sizeof(pno_ssid_list_t));
-+				pwrctl->pno_ssid_list = NULL;
-+			}
-+			if (pwrctl->pscan_info != NULL) {
-+				rtw_mfree((u8 *)pwrctl->pscan_info, sizeof(pno_scan_info_t));
-+				pwrctl->pscan_info = NULL;
-+			}
-+		}
-+		return 0;
-+	} else
-+		return -1;
-+}
-+#endif /* CONFIG_PNO_SUPPORT */
-+
-+int rtw_android_cmdstr_to_num(char *cmdstr)
-+{
-+	int cmd_num;
-+	for (cmd_num = 0 ; cmd_num < ANDROID_WIFI_CMD_MAX; cmd_num++)
-+		if (0 == strnicmp(cmdstr , android_wifi_cmd_str[cmd_num], strlen(android_wifi_cmd_str[cmd_num])))
-+			break;
-+
-+	return cmd_num;
-+}
-+
-+int rtw_android_get_rssi(struct net_device *net, char *command, int total_len)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct	wlan_network	*pcur_network = &pmlmepriv->cur_network;
-+	int bytes_written = 0;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) {
-+		bytes_written += snprintf(&command[bytes_written], total_len, "%s rssi %d",
-+			pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi);
-+	}
-+
-+	return bytes_written;
-+}
-+
-+int rtw_android_get_link_speed(struct net_device *net, char *command, int total_len)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
-+	int bytes_written = 0;
-+	u16 link_speed = 0;
-+
-+	link_speed = rtw_get_cur_max_rate(padapter) / 10;
-+	bytes_written = snprintf(command, total_len, "LinkSpeed %d", link_speed);
-+
-+	return bytes_written;
-+}
-+
-+int rtw_android_get_macaddr(struct net_device *net, char *command, int total_len)
-+{
-+	int bytes_written = 0;
-+
-+	bytes_written = snprintf(command, total_len, "Macaddr = "MAC_FMT, MAC_ARG(net->dev_addr));
-+	return bytes_written;
-+}
-+
-+int rtw_android_set_country(struct net_device *net, char *command, int total_len)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
-+	char *country_code = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_COUNTRY]) + 1;
-+	int ret = _FAIL;
-+
-+	ret = rtw_set_country(adapter, country_code);
-+
-+	return (ret == _SUCCESS) ? 0 : -1;
-+}
-+
-+int rtw_android_get_p2p_dev_addr(struct net_device *net, char *command, int total_len)
-+{
-+	int bytes_written = 0;
-+
-+	/* We use the same address as our HW MAC address */
-+	_rtw_memcpy(command, net->dev_addr, ETH_ALEN);
-+
-+	bytes_written = ETH_ALEN;
-+	return bytes_written;
-+}
-+
-+int rtw_android_set_block_scan(struct net_device *net, char *command, int total_len)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
-+	char *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK_SCAN]) + 1;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	adapter_wdev_data(adapter)->block_scan = (*block_value == '0') ? _FALSE : _TRUE;
-+#endif
-+
-+	return 0;
-+}
-+
-+int rtw_android_set_block(struct net_device *net, char *command, int total_len)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
-+	char *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK]) + 1;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	adapter_wdev_data(adapter)->block = (*block_value == '0') ? _FALSE : _TRUE;
-+#endif
-+
-+	return 0;
-+}
-+
-+int rtw_android_setband(struct net_device *net, char *command, int total_len)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
-+	char *arg = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SETBAND]) + 1;
-+	u32 band = WIFI_FREQUENCY_BAND_AUTO;
-+	int ret = _FAIL;
-+
-+	if (sscanf(arg, "%u", &band) >= 1)
-+		ret = rtw_set_band(adapter, band);
-+
-+	return (ret == _SUCCESS) ? 0 : -1;
-+}
-+
-+int rtw_android_getband(struct net_device *net, char *command, int total_len)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
-+	int bytes_written = 0;
-+
-+	bytes_written = snprintf(command, total_len, "%u", adapter->setband);
-+
-+	return bytes_written;
-+}
-+
-+#ifdef CONFIG_WFD
-+int rtw_android_set_miracast_mode(struct net_device *net, char *command, int total_len)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(net);
-+	struct wifi_display_info *wfd_info = &adapter->wfd_info;
-+	char *arg = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_MIRACAST]) + 1;
-+	u8 mode;
-+	int num;
-+	int ret = _FAIL;
-+
-+	num = sscanf(arg, "%hhu", &mode);
-+
-+	if (num < 1)
-+		goto exit;
-+
-+	switch (mode) {
-+	case 1: /* soruce */
-+		mode = MIRACAST_SOURCE;
-+		break;
-+	case 2: /* sink */
-+		mode = MIRACAST_SINK;
-+		break;
-+	case 0: /* disabled */
-+	default:
-+		mode = MIRACAST_DISABLED;
-+		break;
-+	}
-+	wfd_info->stack_wfd_mode = mode;
-+	RTW_INFO("stack miracast mode: %s\n", get_miracast_mode_str(wfd_info->stack_wfd_mode));
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return (ret == _SUCCESS) ? 0 : -1;
-+}
-+#endif /* CONFIG_WFD */
-+
-+int get_int_from_command(char *pcmd)
-+{
-+	int i = 0;
-+
-+	for (i = 0; i < strlen(pcmd); i++) {
-+		if (pcmd[i] == '=') {
-+			/*	Skip the '=' and space characters. */
-+			i += 2;
-+			break;
-+		}
-+	}
-+	return rtw_atoi(pcmd + i) ;
-+}
-+
-+#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
-+int rtw_gtk_offload(struct net_device *net, u8 *cmd_ptr)
-+{
-+	int i;
-+	/* u8 *cmd_ptr = priv_cmd.buf; */
-+	struct sta_info *psta;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(net);
-+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	struct security_priv *psecuritypriv = &(padapter->securitypriv);
-+	psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
-+
-+
-+	if (psta == NULL)
-+		RTW_INFO("%s, : Obtain Sta_info fail\n", __func__);
-+	else {
-+		/* string command length of "GTK_REKEY_OFFLOAD" */
-+		cmd_ptr += 18;
-+
-+		_rtw_memcpy(psta->kek, cmd_ptr, RTW_KEK_LEN);
-+		cmd_ptr += RTW_KEK_LEN;
-+		/*
-+		printk("supplicant KEK: ");
-+		for(i=0;i<RTW_KEK_LEN; i++)
-+			printk(" %02x ", psta->kek[i]);
-+		printk("\n supplicant KCK: ");
-+		*/
-+		_rtw_memcpy(psta->kck, cmd_ptr, RTW_KCK_LEN);
-+		cmd_ptr += RTW_KCK_LEN;
-+		/*
-+		for(i=0;i<RTW_KEK_LEN; i++)
-+			printk(" %02x ", psta->kck[i]);
-+		*/
-+		_rtw_memcpy(psta->replay_ctr, cmd_ptr, RTW_REPLAY_CTR_LEN);
-+		psecuritypriv->binstallKCK_KEK = _TRUE;
-+
-+		/* printk("\nREPLAY_CTR: "); */
-+		/* for(i=0;i<RTW_REPLAY_CTR_LEN; i++) */
-+		/* printk(" %02x ", psta->replay_ctr[i]); */
-+	}
-+
-+	return _SUCCESS;
-+}
-+#endif /* CONFIG_GTK_OL */
-+
-+#ifdef CONFIG_RTW_MESH_AEK
-+static int rtw_android_set_aek(struct net_device *ndev, char *command, int total_len)
-+{
-+#define SET_AEK_DATA_LEN (ETH_ALEN + 32)
-+
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(ndev);
-+	u8 *addr;
-+	u8 *aek;
-+	int err = 0;
-+
-+	if (total_len - strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AEK]) - 1 != SET_AEK_DATA_LEN) {
-+		err = -EINVAL;
-+		goto exit;
-+	}
-+
-+	addr = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AEK]) + 1;
-+	aek = addr + ETH_ALEN;
-+
-+	RTW_PRINT(FUNC_NDEV_FMT" addr="MAC_FMT"\n"
-+		, FUNC_NDEV_ARG(ndev), MAC_ARG(addr));
-+	if (0)
-+		RTW_PRINT(FUNC_NDEV_FMT" aek="KEY_FMT KEY_FMT"\n"
-+			, FUNC_NDEV_ARG(ndev), KEY_ARG(aek), KEY_ARG(aek + 16));
-+
-+	if (rtw_mesh_plink_set_aek(adapter, addr, aek) != _SUCCESS)
-+		err = -ENOENT;
-+
-+exit:
-+	return err;
-+}
-+#endif /* CONFIG_RTW_MESH_AEK */
-+
-+int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd)
-+{
-+	#define PRIVATE_COMMAND_MAX_LEN        8192
-+	int ret = 0;
-+	char *command = NULL;
-+	int cmd_num;
-+	int bytes_written = 0;
-+#ifdef CONFIG_PNO_SUPPORT
-+	uint cmdlen = 0;
-+	uint pno_enable = 0;
-+#endif
-+	android_wifi_priv_cmd priv_cmd;
-+	_adapter	*padapter = (_adapter *) rtw_netdev_priv(net);
-+#ifdef CONFIG_WFD
-+	struct wifi_display_info		*pwfd_info;
-+#endif
-+
-+	rtw_lock_suspend();
-+
-+	if (!ifr->ifr_data) {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+	if (padapter->registrypriv.mp_mode == 1) {
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+#ifdef CONFIG_COMPAT
-+#if (KERNEL_VERSION(4, 6, 0) > LINUX_VERSION_CODE)
-+	if (is_compat_task()) {
-+#else
-+	if (in_compat_syscall()) {
-+#endif
-+		/* User space is 32-bit, use compat ioctl */
-+		compat_android_wifi_priv_cmd compat_priv_cmd;
-+
-+		if (copy_from_user(&compat_priv_cmd, ifr->ifr_data, sizeof(compat_android_wifi_priv_cmd))) {
-+			ret = -EFAULT;
-+			goto exit;
-+		}
-+		priv_cmd.buf = compat_ptr(compat_priv_cmd.buf);
-+		priv_cmd.used_len = compat_priv_cmd.used_len;
-+		priv_cmd.total_len = compat_priv_cmd.total_len;
-+	} else
-+#endif /* CONFIG_COMPAT */
-+		if (copy_from_user(&priv_cmd, ifr->ifr_data, sizeof(android_wifi_priv_cmd))) {
-+			ret = -EFAULT;
-+			goto exit;
-+		}
-+	if (padapter->registrypriv.mp_mode == 1) {
-+		ret = -EFAULT;
-+		goto exit;
-+	}
-+	/*RTW_INFO("%s priv_cmd.buf=%p priv_cmd.total_len=%d  priv_cmd.used_len=%d\n",__func__,priv_cmd.buf,priv_cmd.total_len,priv_cmd.used_len);*/
-+	if (priv_cmd.total_len > PRIVATE_COMMAND_MAX_LEN || priv_cmd.total_len < 0) {
-+		RTW_WARN("%s: invalid private command (%d)\n", __FUNCTION__,
-+			priv_cmd.total_len);
-+		ret = -EFAULT;
-+		goto exit;
-+	}
-+	
-+	command = rtw_zmalloc(priv_cmd.total_len+1);
-+	if (!command) {
-+		RTW_INFO("%s: failed to allocate memory\n", __FUNCTION__);
-+		ret = -ENOMEM;
-+		goto exit;
-+	}
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0))
-+	if (!access_ok(priv_cmd.buf, priv_cmd.total_len)) {
-+	#else
-+	if (!access_ok(VERIFY_READ, priv_cmd.buf, priv_cmd.total_len)) {
-+	#endif
-+		RTW_INFO("%s: failed to access memory\n", __FUNCTION__);
-+		ret = -EFAULT;
-+		goto exit;
-+	}
-+	if (copy_from_user(command, (void *)priv_cmd.buf, priv_cmd.total_len)) {
-+		ret = -EFAULT;
-+		goto exit;
-+	}
-+	command[priv_cmd.total_len] = '\0';
-+	RTW_INFO("%s: Android private cmd \"%s\" on %s\n"
-+		 , __FUNCTION__, command, ifr->ifr_name);
-+
-+	cmd_num = rtw_android_cmdstr_to_num(command);
-+
-+	switch (cmd_num) {
-+	case ANDROID_WIFI_CMD_START:
-+		/* bytes_written = wl_android_wifi_on(net); */
-+		goto response;
-+	case ANDROID_WIFI_CMD_SETFWPATH:
-+		goto response;
-+	}
-+
-+	if (!g_wifi_on) {
-+		RTW_INFO("%s: Ignore private cmd \"%s\" - iface %s is down\n"
-+			 , __FUNCTION__, command, ifr->ifr_name);
-+		ret = 0;
-+		goto exit;
-+	}
-+
-+	if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) {
-+		switch (cmd_num) {
-+		case ANDROID_WIFI_CMD_WFD_ENABLE:
-+		case ANDROID_WIFI_CMD_WFD_DISABLE:
-+		case ANDROID_WIFI_CMD_WFD_SET_TCPPORT:
-+		case ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT:
-+		case ANDROID_WIFI_CMD_WFD_SET_DEVTYPE:
-+			goto response;
-+		}
-+	}
-+
-+	switch (cmd_num) {
-+
-+	case ANDROID_WIFI_CMD_STOP:
-+		/* bytes_written = wl_android_wifi_off(net); */
-+		break;
-+
-+	case ANDROID_WIFI_CMD_SCAN_ACTIVE:
-+		/* rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_ACTIVE); */
-+#ifdef CONFIG_PLATFORM_MSTAR
-+#ifdef CONFIG_IOCTL_CFG80211
-+		adapter_wdev_data((_adapter *)rtw_netdev_priv(net))->bandroid_scan = _TRUE;
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+#endif /* CONFIG_PLATFORM_MSTAR */
-+		break;
-+	case ANDROID_WIFI_CMD_SCAN_PASSIVE:
-+		/* rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_PASSIVE); */
-+		break;
-+
-+	case ANDROID_WIFI_CMD_RSSI:
-+		bytes_written = rtw_android_get_rssi(net, command, priv_cmd.total_len);
-+		break;
-+	case ANDROID_WIFI_CMD_LINKSPEED:
-+		bytes_written = rtw_android_get_link_speed(net, command, priv_cmd.total_len);
-+		break;
-+
-+	case ANDROID_WIFI_CMD_MACADDR:
-+		bytes_written = rtw_android_get_macaddr(net, command, priv_cmd.total_len);
-+		break;
-+
-+	case ANDROID_WIFI_CMD_BLOCK_SCAN:
-+		bytes_written = rtw_android_set_block_scan(net, command, priv_cmd.total_len);
-+		break;
-+
-+	case ANDROID_WIFI_CMD_BLOCK:
-+		bytes_written = rtw_android_set_block(net, command, priv_cmd.total_len);
-+		break;
-+
-+	case ANDROID_WIFI_CMD_RXFILTER_START:
-+		/* bytes_written = net_os_set_packet_filter(net, 1); */
-+		break;
-+	case ANDROID_WIFI_CMD_RXFILTER_STOP:
-+		/* bytes_written = net_os_set_packet_filter(net, 0); */
-+		break;
-+	case ANDROID_WIFI_CMD_RXFILTER_ADD:
-+		/* int filter_num = *(command + strlen(CMD_RXFILTER_ADD) + 1) - '0'; */
-+		/* bytes_written = net_os_rxfilter_add_remove(net, TRUE, filter_num); */
-+		break;
-+	case ANDROID_WIFI_CMD_RXFILTER_REMOVE:
-+		/* int filter_num = *(command + strlen(CMD_RXFILTER_REMOVE) + 1) - '0'; */
-+		/* bytes_written = net_os_rxfilter_add_remove(net, FALSE, filter_num); */
-+		break;
-+
-+	case ANDROID_WIFI_CMD_BTCOEXSCAN_START:
-+		/* TBD: BTCOEXSCAN-START */
-+		break;
-+	case ANDROID_WIFI_CMD_BTCOEXSCAN_STOP:
-+		/* TBD: BTCOEXSCAN-STOP */
-+		break;
-+	case ANDROID_WIFI_CMD_BTCOEXMODE:
-+#if 0
-+		uint mode = *(command + strlen(CMD_BTCOEXMODE) + 1) - '0';
-+		if (mode == 1)
-+			net_os_set_packet_filter(net, 0); /* DHCP starts */
-+		else
-+			net_os_set_packet_filter(net, 1); /* DHCP ends */
-+#ifdef WL_CFG80211
-+		bytes_written = wl_cfg80211_set_btcoex_dhcp(net, command);
-+#endif
-+#endif
-+		break;
-+
-+	case ANDROID_WIFI_CMD_SETSUSPENDMODE:
-+		break;
-+
-+	case ANDROID_WIFI_CMD_SETSUSPENDOPT:
-+		/* bytes_written = wl_android_set_suspendopt(net, command, priv_cmd.total_len); */
-+		break;
-+
-+	case ANDROID_WIFI_CMD_SETBAND:
-+		bytes_written = rtw_android_setband(net, command, priv_cmd.total_len);
-+		break;
-+
-+	case ANDROID_WIFI_CMD_GETBAND:
-+		bytes_written = rtw_android_getband(net, command, priv_cmd.total_len);
-+		break;
-+
-+	case ANDROID_WIFI_CMD_COUNTRY:
-+		bytes_written = rtw_android_set_country(net, command, priv_cmd.total_len);
-+		break;
-+
-+#ifdef CONFIG_PNO_SUPPORT
-+	case ANDROID_WIFI_CMD_PNOSSIDCLR_SET:
-+		/* bytes_written = dhd_dev_pno_reset(net); */
-+		break;
-+	case ANDROID_WIFI_CMD_PNOSETUP_SET:
-+		bytes_written = rtw_android_pno_setup(net, command, priv_cmd.total_len);
-+		break;
-+	case ANDROID_WIFI_CMD_PNOENABLE_SET:
-+		cmdlen = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_PNOENABLE_SET]);
-+		pno_enable = *(command + cmdlen + 1) - '0';
-+		bytes_written = rtw_android_pno_enable(net, pno_enable);
-+		break;
-+#endif
-+
-+	case ANDROID_WIFI_CMD_P2P_DEV_ADDR:
-+		bytes_written = rtw_android_get_p2p_dev_addr(net, command, priv_cmd.total_len);
-+		break;
-+	case ANDROID_WIFI_CMD_P2P_SET_NOA:
-+		/* int skip = strlen(CMD_P2P_SET_NOA) + 1; */
-+		/* bytes_written = wl_cfg80211_set_p2p_noa(net, command + skip, priv_cmd.total_len - skip); */
-+		break;
-+	case ANDROID_WIFI_CMD_P2P_GET_NOA:
-+		/* bytes_written = wl_cfg80211_get_p2p_noa(net, command, priv_cmd.total_len); */
-+		break;
-+	case ANDROID_WIFI_CMD_P2P_SET_PS:
-+		/* int skip = strlen(CMD_P2P_SET_PS) + 1; */
-+		/* bytes_written = wl_cfg80211_set_p2p_ps(net, command + skip, priv_cmd.total_len - skip); */
-+		break;
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+	#ifdef CONFIG_AP_MODE
-+	case ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE: {
-+		int skip = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE]) + 3;
-+		bytes_written = rtw_cfg80211_set_mgnt_wpsp2pie(net, command + skip, priv_cmd.total_len - skip, *(command + skip - 2) - '0');
-+		break;
-+	}
-+	#endif
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+#ifdef CONFIG_WFD
-+
-+	case ANDROID_WIFI_CMD_MIRACAST:
-+		bytes_written = rtw_android_set_miracast_mode(net, command, priv_cmd.total_len);
-+		break;
-+
-+	case ANDROID_WIFI_CMD_WFD_ENABLE: {
-+		/*	Commented by Albert 2012/07/24 */
-+		/*	We can enable the WFD function by using the following command: */
-+		/*	wpa_cli driver wfd-enable */
-+
-+		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
-+			rtw_wfd_enable(padapter, 1);
-+		break;
-+	}
-+
-+	case ANDROID_WIFI_CMD_WFD_DISABLE: {
-+		/*	Commented by Albert 2012/07/24 */
-+		/*	We can disable the WFD function by using the following command: */
-+		/*	wpa_cli driver wfd-disable */
-+
-+		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
-+			rtw_wfd_enable(padapter, 0);
-+		break;
-+	}
-+	case ANDROID_WIFI_CMD_WFD_SET_TCPPORT: {
-+		/*	Commented by Albert 2012/07/24 */
-+		/*	We can set the tcp port number by using the following command: */
-+		/*	wpa_cli driver wfd-set-tcpport = 554 */
-+
-+		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
-+			rtw_wfd_set_ctrl_port(padapter, (u16)get_int_from_command(command));
-+		break;
-+	}
-+	case ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT: {
-+		break;
-+	}
-+	case ANDROID_WIFI_CMD_WFD_SET_DEVTYPE: {
-+		/*	Commented by Albert 2012/08/28 */
-+		/*	Specify the WFD device type ( WFD source/primary sink ) */
-+
-+		pwfd_info = &padapter->wfd_info;
-+		if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) {
-+			pwfd_info->wfd_device_type = (u8) get_int_from_command(command);
-+			pwfd_info->wfd_device_type &= WFD_DEVINFO_DUAL;
-+		}
-+		break;
-+	}
-+#endif
-+	case ANDROID_WIFI_CMD_CHANGE_DTIM: {
-+#ifdef CONFIG_LPS
-+		u8 dtim;
-+		u8 *ptr = (u8 *) command;
-+
-+		ptr += 9;/* string command length of  "SET_DTIM"; */
-+
-+		dtim = rtw_atoi(ptr);
-+
-+		RTW_INFO("DTIM=%d\n", dtim);
-+
-+		rtw_lps_change_dtim_cmd(padapter, dtim);
-+#endif
-+	}
-+	break;
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+	case ANDROID_WIFI_CMD_HOSTAPD_SET_MACADDR_ACL: {
-+		rtw_set_macaddr_acl(padapter, RTW_ACL_PERIOD_BSS, get_int_from_command(command));
-+		break;
-+	}
-+	case ANDROID_WIFI_CMD_HOSTAPD_ACL_ADD_STA: {
-+		u8 addr[ETH_ALEN] = {0x00};
-+		macstr2num(addr, command + strlen("HOSTAPD_ACL_ADD_STA") + 3);	/* 3 is space bar + "=" + space bar these 3 chars */
-+		rtw_acl_add_sta(padapter, RTW_ACL_PERIOD_BSS, addr);
-+		break;
-+	}
-+	case ANDROID_WIFI_CMD_HOSTAPD_ACL_REMOVE_STA: {
-+		u8 addr[ETH_ALEN] = {0x00};
-+		macstr2num(addr, command + strlen("HOSTAPD_ACL_REMOVE_STA") + 3);	/* 3 is space bar + "=" + space bar these 3 chars */
-+		rtw_acl_remove_sta(padapter, RTW_ACL_PERIOD_BSS, addr);
-+		break;
-+	}
-+#endif /* CONFIG_RTW_MACADDR_ACL */
-+#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0))
-+	case ANDROID_WIFI_CMD_GTK_REKEY_OFFLOAD:
-+		rtw_gtk_offload(net, (u8 *)command);
-+		break;
-+#endif /* CONFIG_GTK_OL		 */
-+	case ANDROID_WIFI_CMD_P2P_DISABLE: {
-+#ifdef CONFIG_P2P
-+		rtw_p2p_enable(padapter, P2P_ROLE_DISABLE);
-+#endif /* CONFIG_P2P */
-+		break;
-+	}
-+
-+#ifdef CONFIG_RTW_MESH_AEK
-+	case ANDROID_WIFI_CMD_SET_AEK:
-+		bytes_written = rtw_android_set_aek(net, command, priv_cmd.total_len);
-+		break;
-+#endif
-+	
-+	case ANDROID_WIFI_CMD_EXT_AUTH_STATUS: {
-+		rtw_set_external_auth_status(padapter,
-+			command + strlen("EXT_AUTH_STATUS "),
-+			priv_cmd.total_len - strlen("EXT_AUTH_STATUS "));
-+		break;
-+	}
-+	case ANDROID_WIFI_CMD_DRIVERVERSION: {
-+		bytes_written = strlen(DRIVERVERSION);
-+		snprintf(command, bytes_written + 1, DRIVERVERSION);
-+		break;
-+	}
-+	default:
-+		RTW_INFO("Unknown PRIVATE command %s - ignored\n", command);
-+		snprintf(command, 3, "OK");
-+		bytes_written = strlen("OK");
-+	}
-+
-+response:
-+	if (bytes_written >= 0) {
-+		if ((bytes_written == 0) && (priv_cmd.total_len > 0))
-+			command[0] = '\0';
-+		if (bytes_written >= priv_cmd.total_len) {
-+			RTW_INFO("%s: bytes_written = %d\n", __FUNCTION__, bytes_written);
-+			bytes_written = priv_cmd.total_len;
-+		} else
-+			bytes_written++;
-+		priv_cmd.used_len = bytes_written;
-+		if (copy_to_user((void *)priv_cmd.buf, command, bytes_written)) {
-+			RTW_INFO("%s: failed to copy data to user buffer\n", __FUNCTION__);
-+			ret = -EFAULT;
-+		}
-+	} else
-+		ret = bytes_written;
-+
-+exit:
-+	rtw_unlock_suspend();
-+	if (command)
-+		rtw_mfree(command, priv_cmd.total_len + 1);
-+
-+	return ret;
-+}
-+
-+
-+/**
-+ * Functions for Android WiFi card detection
-+ */
-+#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC)
-+
-+static int g_wifidev_registered = 0;
-+static struct semaphore wifi_control_sem;
-+static struct wifi_platform_data *wifi_control_data = NULL;
-+static struct resource *wifi_irqres = NULL;
-+
-+static int wifi_add_dev(void);
-+static void wifi_del_dev(void);
-+
-+int rtw_android_wifictrl_func_add(void)
-+{
-+	int ret = 0;
-+	sema_init(&wifi_control_sem, 0);
-+
-+	ret = wifi_add_dev();
-+	if (ret) {
-+		RTW_INFO("%s: platform_driver_register failed\n", __FUNCTION__);
-+		return ret;
-+	}
-+	g_wifidev_registered = 1;
-+
-+	/* Waiting callback after platform_driver_register is done or exit with error */
-+	if (down_timeout(&wifi_control_sem,  msecs_to_jiffies(1000)) != 0) {
-+		ret = -EINVAL;
-+		RTW_INFO("%s: platform_driver_register timeout\n", __FUNCTION__);
-+	}
-+
-+	return ret;
-+}
-+
-+void rtw_android_wifictrl_func_del(void)
-+{
-+	if (g_wifidev_registered) {
-+		wifi_del_dev();
-+		g_wifidev_registered = 0;
-+	}
-+}
-+
-+void *wl_android_prealloc(int section, unsigned long size)
-+{
-+	void *alloc_ptr = NULL;
-+	if (wifi_control_data && wifi_control_data->mem_prealloc) {
-+		alloc_ptr = wifi_control_data->mem_prealloc(section, size);
-+		if (alloc_ptr) {
-+			RTW_INFO("success alloc section %d\n", section);
-+			if (size != 0L)
-+				memset(alloc_ptr, 0, size);
-+			return alloc_ptr;
-+		}
-+	}
-+
-+	RTW_INFO("can't alloc section %d\n", section);
-+	return NULL;
-+}
-+
-+int wifi_get_irq_number(unsigned long *irq_flags_ptr)
-+{
-+	if (wifi_irqres) {
-+		*irq_flags_ptr = wifi_irqres->flags & IRQF_TRIGGER_MASK;
-+		return (int)wifi_irqres->start;
-+	}
-+#ifdef CUSTOM_OOB_GPIO_NUM
-+	return CUSTOM_OOB_GPIO_NUM;
-+#else
-+	return -1;
-+#endif
-+}
-+
-+int wifi_set_power(int on, unsigned long msec)
-+{
-+	RTW_INFO("%s = %d\n", __FUNCTION__, on);
-+	if (wifi_control_data && wifi_control_data->set_power)
-+		wifi_control_data->set_power(on);
-+	if (msec)
-+		msleep(msec);
-+	return 0;
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+int wifi_get_mac_addr(unsigned char *buf)
-+{
-+	RTW_INFO("%s\n", __FUNCTION__);
-+	if (!buf)
-+		return -EINVAL;
-+	if (wifi_control_data && wifi_control_data->get_mac_addr)
-+		return wifi_control_data->get_mac_addr(buf);
-+	return -EOPNOTSUPP;
-+}
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) */
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) || defined(COMPAT_KERNEL_RELEASE)
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
-+void *wifi_get_country_code(char *ccode, u32 flags)
-+#else /* Linux kernel < 3.18 */
-+void *wifi_get_country_code(char *ccode)
-+#endif /* Linux kernel < 3.18 */
-+{
-+	RTW_INFO("%s\n", __FUNCTION__);
-+	if (!ccode)
-+		return NULL;
-+	if (wifi_control_data && wifi_control_data->get_country_code)
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
-+		return wifi_control_data->get_country_code(ccode, flags);
-+#else /* Linux kernel < 3.18 */
-+		return wifi_control_data->get_country_code(ccode);
-+#endif /* Linux kernel < 3.18 */
-+	return NULL;
-+}
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) */
-+
-+static int wifi_set_carddetect(int on)
-+{
-+	RTW_INFO("%s = %d\n", __FUNCTION__, on);
-+	if (wifi_control_data && wifi_control_data->set_carddetect)
-+		wifi_control_data->set_carddetect(on);
-+	return 0;
-+}
-+
-+static int wifi_probe(struct platform_device *pdev)
-+{
-+	struct wifi_platform_data *wifi_ctrl =
-+		(struct wifi_platform_data *)(pdev->dev.platform_data);
-+	int wifi_wake_gpio = 0;
-+
-+	RTW_INFO("## %s\n", __FUNCTION__);
-+	wifi_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "bcmdhd_wlan_irq");
-+
-+	if (wifi_irqres == NULL)
-+		wifi_irqres = platform_get_resource_byname(pdev,
-+				IORESOURCE_IRQ, "bcm4329_wlan_irq");
-+	else
-+		wifi_wake_gpio = wifi_irqres->start;
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+	RTW_INFO("%s: gpio:%d wifi_wake_gpio:%d\n", __func__,
-+	       (int)wifi_irqres->start, wifi_wake_gpio);
-+
-+	if (wifi_wake_gpio > 0) {
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+		wifi_configure_gpio();
-+#else /* CONFIG_PLATFORM_INTEL_BYT */
-+		gpio_request(wifi_wake_gpio, "oob_irq");
-+		gpio_direction_input(wifi_wake_gpio);
-+		oob_irq = gpio_to_irq(wifi_wake_gpio);
-+#endif /* CONFIG_PLATFORM_INTEL_BYT */
-+		RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq);
-+	} else if (wifi_irqres) {
-+		oob_irq = wifi_irqres->start;
-+		RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq);
-+	}
-+#endif
-+	wifi_control_data = wifi_ctrl;
-+
-+	wifi_set_power(1, 0);	/* Power On */
-+	wifi_set_carddetect(1);	/* CardDetect (0->1) */
-+
-+	up(&wifi_control_sem);
-+	return 0;
-+}
-+
-+#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
-+extern PADAPTER g_test_adapter;
-+
-+static void shutdown_card(void)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(g_test_adapter);
-+	u32 addr;
-+	u8 tmp8, cnt = 0;
-+
-+	if (NULL == g_test_adapter) {
-+		RTW_INFO("%s: padapter==NULL\n", __FUNCTION__);
-+		return;
-+	}
-+
-+#ifdef CONFIG_FWLPS_IN_IPS
-+	LeaveAllPowerSaveMode(g_test_adapter);
-+#endif /* CONFIG_FWLPS_IN_IPS */
-+
-+#ifdef CONFIG_WOWLAN
-+#ifdef CONFIG_GPIO_WAKEUP
-+	/*default wake up pin change to BT*/
-+	RTW_INFO("%s:default wake up pin change to BT\n", __FUNCTION__);
-+	rtw_hal_switch_gpio_wl_ctrl(g_test_adapter, pwrpriv->wowlan_gpio_index, _FALSE);
-+#endif /* CONFIG_GPIO_WAKEUP */
-+#endif /* CONFIG_WOWLAN */
-+
-+	/* Leave SDIO HCI Suspend */
-+	addr = 0x10250086;
-+	rtw_write8(g_test_adapter, addr, 0);
-+	do {
-+		tmp8 = rtw_read8(g_test_adapter, addr);
-+		cnt++;
-+		RTW_INFO(FUNC_ADPT_FMT ": polling SDIO_HSUS_CTRL(0x%x)=0x%x, cnt=%d\n",
-+			 FUNC_ADPT_ARG(g_test_adapter), addr, tmp8, cnt);
-+
-+		if (tmp8 & BIT(1))
-+			break;
-+
-+		if (cnt >= 100) {
-+			RTW_INFO(FUNC_ADPT_FMT ": polling 0x%x[1]==1 FAIL!!\n",
-+				 FUNC_ADPT_ARG(g_test_adapter), addr);
-+			break;
-+		}
-+
-+		rtw_mdelay_os(10);
-+	} while (1);
-+
-+	/* unlock register I/O */
-+	rtw_write8(g_test_adapter, 0x1C, 0);
-+
-+	/* enable power down function */
-+	/* 0x04[4] = 1 */
-+	/* 0x05[7] = 1 */
-+	addr = 0x04;
-+	tmp8 = rtw_read8(g_test_adapter, addr);
-+	tmp8 |= BIT(4);
-+	rtw_write8(g_test_adapter, addr, tmp8);
-+	RTW_INFO(FUNC_ADPT_FMT ": read after write 0x%x=0x%x\n",
-+		FUNC_ADPT_ARG(g_test_adapter), addr, rtw_read8(g_test_adapter, addr));
-+
-+	addr = 0x05;
-+	tmp8 = rtw_read8(g_test_adapter, addr);
-+	tmp8 |= BIT(7);
-+	rtw_write8(g_test_adapter, addr, tmp8);
-+	RTW_INFO(FUNC_ADPT_FMT ": read after write 0x%x=0x%x\n",
-+		FUNC_ADPT_ARG(g_test_adapter), addr, rtw_read8(g_test_adapter, addr));
-+
-+	/* lock register page0 0x0~0xB read/write */
-+	rtw_write8(g_test_adapter, 0x1C, 0x0E);
-+
-+	rtw_set_surprise_removed(g_test_adapter);
-+	RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=%s\n",
-+		FUNC_ADPT_ARG(g_test_adapter), rtw_is_surprise_removed(g_test_adapter) ? "True" : "False");
-+}
-+#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
-+
-+static int wifi_remove(struct platform_device *pdev)
-+{
-+	struct wifi_platform_data *wifi_ctrl =
-+		(struct wifi_platform_data *)(pdev->dev.platform_data);
-+
-+	RTW_INFO("## %s\n", __FUNCTION__);
-+	wifi_control_data = wifi_ctrl;
-+
-+	wifi_set_power(0, 0);	/* Power Off */
-+	wifi_set_carddetect(0);	/* CardDetect (1->0) */
-+
-+	up(&wifi_control_sem);
-+	return 0;
-+}
-+
-+#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
-+static void wifi_shutdown(struct platform_device *pdev)
-+{
-+	struct wifi_platform_data *wifi_ctrl =
-+		(struct wifi_platform_data *)(pdev->dev.platform_data);
-+
-+
-+	RTW_INFO("## %s\n", __FUNCTION__);
-+
-+	wifi_control_data = wifi_ctrl;
-+
-+	shutdown_card();
-+	wifi_set_power(0, 0);	/* Power Off */
-+	wifi_set_carddetect(0);	/* CardDetect (1->0) */
-+}
-+#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
-+
-+static int wifi_suspend(struct platform_device *pdev, pm_message_t state)
-+{
-+	RTW_INFO("##> %s\n", __FUNCTION__);
-+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY)
-+	bcmsdh_oob_intr_set(0);
-+#endif
-+	return 0;
-+}
-+
-+static int wifi_resume(struct platform_device *pdev)
-+{
-+	RTW_INFO("##> %s\n", __FUNCTION__);
-+#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY)
-+	if (dhd_os_check_if_up(bcmsdh_get_drvdata()))
-+		bcmsdh_oob_intr_set(1);
-+#endif
-+	return 0;
-+}
-+
-+/* temporarily use these two */
-+static struct platform_driver wifi_device = {
-+	.probe          = wifi_probe,
-+	.remove         = wifi_remove,
-+	.suspend        = wifi_suspend,
-+	.resume         = wifi_resume,
-+#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
-+	.shutdown       = wifi_shutdown,
-+#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
-+	.driver         = {
-+		.name   = "bcmdhd_wlan",
-+	}
-+};
-+
-+static struct platform_driver wifi_device_legacy = {
-+	.probe          = wifi_probe,
-+	.remove         = wifi_remove,
-+	.suspend        = wifi_suspend,
-+	.resume         = wifi_resume,
-+	.driver         = {
-+		.name   = "bcm4329_wlan",
-+	}
-+};
-+
-+static int wifi_add_dev(void)
-+{
-+	RTW_INFO("## Calling platform_driver_register\n");
-+	platform_driver_register(&wifi_device);
-+	platform_driver_register(&wifi_device_legacy);
-+	return 0;
-+}
-+
-+static void wifi_del_dev(void)
-+{
-+	RTW_INFO("## Unregister platform_driver_register\n");
-+	platform_driver_unregister(&wifi_device);
-+	platform_driver_unregister(&wifi_device_legacy);
-+}
-+#endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+int wifi_configure_gpio(void)
-+{
-+	if (gpio_request(oob_gpio, "oob_irq")) {
-+		RTW_INFO("## %s Cannot request GPIO\n", __FUNCTION__);
-+		return -1;
-+	}
-+	gpio_export(oob_gpio, 0);
-+	if (gpio_direction_input(oob_gpio)) {
-+		RTW_INFO("## %s Cannot set GPIO direction input\n", __FUNCTION__);
-+		return -1;
-+	}
-+	oob_irq = gpio_to_irq(oob_gpio);
-+	if (oob_irq < 0) {
-+		RTW_INFO("## %s Cannot convert GPIO to IRQ\n", __FUNCTION__);
-+		return -1;
-+	}
-+
-+	RTW_INFO("## %s OOB_IRQ=%d\n", __FUNCTION__, oob_irq);
-+
-+	return 0;
-+}
-+#endif /* CONFIG_PLATFORM_INTEL_BYT */
-+void wifi_free_gpio(unsigned int gpio)
-+{
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+	if (gpio)
-+		gpio_free(gpio);
-+#endif /* CONFIG_PLATFORM_INTEL_BYT */
-+}
-+#endif /* CONFIG_GPIO_WAKEUP */
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/rtw_cfgvendor.c b/drivers/staging/rtl8723cs/os_dep/linux/rtw_cfgvendor.c
-new file mode 100644
-index 000000000000..6daa9e2d6dd1
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/rtw_cfgvendor.c
-@@ -0,0 +1,2170 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT)
-+
-+/*
-+#include <linux/kernel.h>
-+#include <linux/if_arp.h>
-+#include <asm/uaccess.h>
-+
-+#include <linux/kernel.h>
-+#include <linux/kthread.h>
-+#include <linux/netdevice.h>
-+#include <linux/sched.h>
-+#include <linux/etherdevice.h>
-+#include <linux/wireless.h>
-+#include <linux/ieee80211.h>
-+#include <linux/wait.h>
-+#include <net/cfg80211.h>
-+*/
-+
-+#include <net/rtnetlink.h>
-+
-+#ifndef MIN
-+#define MIN(x,y) (((x) < (y)) ? (x) : (y))
-+#endif
-+
-+#ifdef DBG_MEM_ALLOC
-+extern bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size);
-+struct sk_buff *dbg_rtw_cfg80211_vendor_event_alloc(struct wiphy *wiphy, struct wireless_dev *wdev, int len, int event_id, gfp_t gfp
-+		, const enum mstat_f flags, const char *func, const int line)
-+{
-+	struct sk_buff *skb;
-+	unsigned int truesize = 0;
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))
-+	skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp);
-+#else
-+	skb = cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp);
-+#endif
-+
-+	if (skb)
-+		truesize = skb->truesize;
-+
-+	if (!skb || truesize < len || match_mstat_sniff_rules(flags, truesize))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, len, skb, truesize);
-+
-+	rtw_mstat_update(
-+		flags
-+		, skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
-+		, truesize
-+	);
-+
-+	return skb;
-+}
-+
-+void dbg_rtw_cfg80211_vendor_event(struct sk_buff *skb, gfp_t gfp
-+		   , const enum mstat_f flags, const char *func, const int line)
-+{
-+	unsigned int truesize = skb->truesize;
-+
-+	if (match_mstat_sniff_rules(flags, truesize))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
-+
-+	cfg80211_vendor_event(skb, gfp);
-+
-+	rtw_mstat_update(
-+		flags
-+		, MSTAT_FREE
-+		, truesize
-+	);
-+}
-+
-+struct sk_buff *dbg_rtw_cfg80211_vendor_cmd_alloc_reply_skb(struct wiphy *wiphy, int len
-+		, const enum mstat_f flags, const char *func, const int line)
-+{
-+	struct sk_buff *skb;
-+	unsigned int truesize = 0;
-+
-+	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);
-+
-+	if (skb)
-+		truesize = skb->truesize;
-+
-+	if (!skb || truesize < len || match_mstat_sniff_rules(flags, truesize))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, len, skb, truesize);
-+
-+	rtw_mstat_update(
-+		flags
-+		, skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
-+		, truesize
-+	);
-+
-+	return skb;
-+}
-+
-+int dbg_rtw_cfg80211_vendor_cmd_reply(struct sk_buff *skb
-+	      , const enum mstat_f flags, const char *func, const int line)
-+{
-+	unsigned int truesize = skb->truesize;
-+	int ret;
-+
-+	if (match_mstat_sniff_rules(flags, truesize))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
-+
-+	ret = cfg80211_vendor_cmd_reply(skb);
-+
-+	rtw_mstat_update(
-+		flags
-+		, MSTAT_FREE
-+		, truesize
-+	);
-+
-+	return ret;
-+}
-+
-+#define rtw_cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp) \
-+	dbg_rtw_cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+
-+#define rtw_cfg80211_vendor_event(skb, gfp) \
-+	dbg_rtw_cfg80211_vendor_event(skb, gfp, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+
-+#define rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \
-+	dbg_rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+
-+#define rtw_cfg80211_vendor_cmd_reply(skb) \
-+	dbg_rtw_cfg80211_vendor_cmd_reply(skb, MSTAT_FUNC_CFG_VENDOR | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
-+#else
-+
-+struct sk_buff *rtw_cfg80211_vendor_event_alloc(
-+	struct wiphy *wiphy, struct wireless_dev *wdev, int len, int event_id, gfp_t gfp)
-+{
-+	struct sk_buff *skb;
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))
-+	skb = cfg80211_vendor_event_alloc(wiphy, len, event_id, gfp);
-+#else
-+	skb = cfg80211_vendor_event_alloc(wiphy, wdev, len, event_id, gfp);
-+#endif
-+	return skb;
-+}
-+
-+#define rtw_cfg80211_vendor_event(skb, gfp) \
-+	cfg80211_vendor_event(skb, gfp)
-+
-+#define rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len) \
-+	cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len)
-+
-+#define rtw_cfg80211_vendor_cmd_reply(skb) \
-+	cfg80211_vendor_cmd_reply(skb)
-+#endif /* DBG_MEM_ALLOC */
-+
-+/*
-+ * This API is to be used for asynchronous vendor events. This
-+ * shouldn't be used in response to a vendor command from its
-+ * do_it handler context (instead rtw_cfgvendor_send_cmd_reply should
-+ * be used).
-+ */
-+int rtw_cfgvendor_send_async_event(struct wiphy *wiphy,
-+	   struct net_device *dev, int event_id, const void  *data, int len)
-+{
-+	gfp_t kflags;
-+	struct sk_buff *skb;
-+
-+	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
-+
-+	/* Alloc the SKB for vendor_event */
-+	skb = rtw_cfg80211_vendor_event_alloc(wiphy, ndev_to_wdev(dev), len, event_id, kflags);
-+	if (!skb) {
-+		RTW_ERR(FUNC_NDEV_FMT" skb alloc failed", FUNC_NDEV_ARG(dev));
-+		return -ENOMEM;
-+	}
-+
-+	/* Push the data to the skb */
-+	nla_put_nohdr(skb, len, data);
-+
-+	rtw_cfg80211_vendor_event(skb, kflags);
-+
-+	return 0;
-+}
-+
-+static int rtw_cfgvendor_send_cmd_reply(struct wiphy *wiphy,
-+			struct net_device *dev, const void  *data, int len)
-+{
-+	struct sk_buff *skb;
-+
-+	/* Alloc the SKB for vendor_event */
-+	skb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, len);
-+	if (unlikely(!skb)) {
-+		RTW_ERR(FUNC_NDEV_FMT" skb alloc failed", FUNC_NDEV_ARG(dev));
-+		return -ENOMEM;
-+	}
-+
-+	/* Push the data to the skb */
-+	nla_put_nohdr(skb, len, data);
-+
-+	return rtw_cfg80211_vendor_cmd_reply(skb);
-+}
-+
-+/* Feature enums */
-+#define WIFI_FEATURE_INFRA              0x0001      // Basic infrastructure mode
-+#define WIFI_FEATURE_INFRA_5G           0x0002      // Support for 5 GHz Band
-+#define WIFI_FEATURE_HOTSPOT            0x0004      // Support for GAS/ANQP
-+#define WIFI_FEATURE_P2P                0x0008      // Wifi-Direct
-+#define WIFI_FEATURE_SOFT_AP            0x0010      // Soft AP
-+#define WIFI_FEATURE_GSCAN              0x0020      // Google-Scan APIs
-+#define WIFI_FEATURE_NAN                0x0040      // Neighbor Awareness Networking
-+#define WIFI_FEATURE_D2D_RTT            0x0080      // Device-to-device RTT
-+#define WIFI_FEATURE_D2AP_RTT           0x0100      // Device-to-AP RTT
-+#define WIFI_FEATURE_BATCH_SCAN         0x0200      // Batched Scan (legacy)
-+#define WIFI_FEATURE_PNO                0x0400      // Preferred network offload
-+#define WIFI_FEATURE_ADDITIONAL_STA     0x0800      // Support for two STAs
-+#define WIFI_FEATURE_TDLS               0x1000      // Tunnel directed link setup
-+#define WIFI_FEATURE_TDLS_OFFCHANNEL    0x2000      // Support for TDLS off channel
-+#define WIFI_FEATURE_EPR                0x4000      // Enhanced power reporting
-+#define WIFI_FEATURE_AP_STA             0x8000      // Support for AP STA Concurrency
-+#define WIFI_FEATURE_LINK_LAYER_STATS   0x10000     // Link layer stats collection
-+#define WIFI_FEATURE_LOGGER             0x20000     // WiFi Logger
-+#define WIFI_FEATURE_HAL_EPNO           0x40000     // WiFi PNO enhanced
-+#define WIFI_FEATURE_RSSI_MONITOR       0x80000     // RSSI Monitor
-+#define WIFI_FEATURE_MKEEP_ALIVE        0x100000    // WiFi mkeep_alive
-+#define WIFI_FEATURE_CONFIG_NDO         0x200000    // ND offload configure
-+#define WIFI_FEATURE_TX_TRANSMIT_POWER  0x400000    // Capture Tx transmit power levels
-+#define WIFI_FEATURE_CONTROL_ROAMING    0x800000    // Enable/Disable firmware roaming
-+#define WIFI_FEATURE_IE_WHITELIST       0x1000000   // Support Probe IE white listing
-+#define WIFI_FEATURE_SCAN_RAND          0x2000000   // Support MAC & Probe Sequence Number randomization
-+#define WIFI_FEATURE_SET_TX_POWER_LIMIT 0x4000000   // Support Tx Power Limit setting
-+#define WIFI_FEATURE_USE_BODY_HEAD_SAR  0x8000000   // Support Using Body/Head Proximity for SAR
-+#define WIFI_FEATURE_SET_LATENCY_MODE   0x40000000  // Support Latency mode setting
-+#define WIFI_FEATURE_P2P_RAND_MAC       0x80000000  // Support Support P2P MAC randomization
-+// Add more features here
-+
-+#define MAX_FEATURE_SET_CONCURRRENT_GROUPS  3
-+
-+#include <hal_data.h>
-+int rtw_dev_get_feature_set(struct net_device *dev)
-+{
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
-+	int feature_set = 0;
-+
-+	feature_set |= WIFI_FEATURE_INFRA;
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	if (is_supported_5g(adapter_to_regsty(adapter)->wireless_mode))
-+		feature_set |= WIFI_FEATURE_INFRA_5G;
-+#endif
-+
-+	feature_set |= WIFI_FEATURE_P2P;
-+	feature_set |= WIFI_FEATURE_SOFT_AP;
-+
-+	feature_set |= WIFI_FEATURE_ADDITIONAL_STA;
-+#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
-+	feature_set |= WIFI_FEATURE_LINK_LAYER_STATS;
-+#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
-+        feature_set |= WIFI_FEATURE_RSSI_MONITOR;
-+#endif
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
-+	feature_set |= WIFI_FEATURE_LOGGER;
-+#endif
-+
-+#ifdef CONFIG_RTW_WIFI_HAL
-+	feature_set |= WIFI_FEATURE_CONFIG_NDO;
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+	feature_set |= WIFI_FEATURE_SCAN_RAND;
-+#endif
-+#endif
-+
-+	return feature_set;
-+}
-+
-+int *rtw_dev_get_feature_set_matrix(struct net_device *dev, int *num)
-+{
-+	int feature_set_full, mem_needed;
-+	int *ret;
-+
-+	*num = 0;
-+	mem_needed = sizeof(int) * MAX_FEATURE_SET_CONCURRRENT_GROUPS;
-+	ret = (int *)rtw_malloc(mem_needed);
-+
-+	if (!ret) {
-+		RTW_ERR(FUNC_NDEV_FMT" failed to allocate %d bytes\n"
-+			, FUNC_NDEV_ARG(dev), mem_needed);
-+		return ret;
-+	}
-+
-+	feature_set_full = rtw_dev_get_feature_set(dev);
-+
-+	ret[0] = (feature_set_full & WIFI_FEATURE_INFRA) |
-+		 (feature_set_full & WIFI_FEATURE_INFRA_5G) |
-+		 (feature_set_full & WIFI_FEATURE_NAN) |
-+		 (feature_set_full & WIFI_FEATURE_D2D_RTT) |
-+		 (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
-+		 (feature_set_full & WIFI_FEATURE_PNO) |
-+		 (feature_set_full & WIFI_FEATURE_BATCH_SCAN) |
-+		 (feature_set_full & WIFI_FEATURE_GSCAN) |
-+		 (feature_set_full & WIFI_FEATURE_HOTSPOT) |
-+		 (feature_set_full & WIFI_FEATURE_ADDITIONAL_STA) |
-+		 (feature_set_full & WIFI_FEATURE_EPR);
-+
-+	ret[1] = (feature_set_full & WIFI_FEATURE_INFRA) |
-+		 (feature_set_full & WIFI_FEATURE_INFRA_5G) |
-+		 /* Not yet verified NAN with P2P */
-+		 /* (feature_set_full & WIFI_FEATURE_NAN) | */
-+		 (feature_set_full & WIFI_FEATURE_P2P) |
-+		 (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
-+		 (feature_set_full & WIFI_FEATURE_D2D_RTT) |
-+		 (feature_set_full & WIFI_FEATURE_EPR);
-+
-+	ret[2] = (feature_set_full & WIFI_FEATURE_INFRA) |
-+		 (feature_set_full & WIFI_FEATURE_INFRA_5G) |
-+		 (feature_set_full & WIFI_FEATURE_NAN) |
-+		 (feature_set_full & WIFI_FEATURE_D2D_RTT) |
-+		 (feature_set_full & WIFI_FEATURE_D2AP_RTT) |
-+		 (feature_set_full & WIFI_FEATURE_TDLS) |
-+		 (feature_set_full & WIFI_FEATURE_TDLS_OFFCHANNEL) |
-+		 (feature_set_full & WIFI_FEATURE_EPR);
-+	*num = MAX_FEATURE_SET_CONCURRRENT_GROUPS;
-+
-+	return ret;
-+}
-+
-+static int rtw_cfgvendor_get_feature_set(struct wiphy *wiphy,
-+		struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0;
-+	int reply;
-+
-+	reply = rtw_dev_get_feature_set(wdev_to_ndev(wdev));
-+
-+	err =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &reply, sizeof(int));
-+
-+	if (unlikely(err))
-+		RTW_ERR(FUNC_NDEV_FMT" Vendor Command reply failed ret:%d\n"
-+			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);
-+
-+	return err;
-+}
-+
-+static int rtw_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy,
-+		struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0;
-+	struct sk_buff *skb;
-+	int *reply;
-+	int num, mem_needed, i;
-+
-+	reply = rtw_dev_get_feature_set_matrix(wdev_to_ndev(wdev), &num);
-+
-+	if (!reply) {
-+		RTW_ERR(FUNC_NDEV_FMT" Could not get feature list matrix\n"
-+			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)));
-+		err = -EINVAL;
-+		return err;
-+	}
-+
-+	mem_needed = VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * num) +
-+		     ATTRIBUTE_U32_LEN;
-+
-+	/* Alloc the SKB for vendor_event */
-+	skb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
-+	if (unlikely(!skb)) {
-+		RTW_ERR(FUNC_NDEV_FMT" skb alloc failed", FUNC_NDEV_ARG(wdev_to_ndev(wdev)));
-+		err = -ENOMEM;
-+		goto exit;
-+	}
-+
-+	nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, num);
-+	for (i = 0; i < num; i++)
-+		nla_put_u32(skb, ANDR_WIFI_ATTRIBUTE_FEATURE_SET, reply[i]);
-+
-+	err =  rtw_cfg80211_vendor_cmd_reply(skb);
-+
-+	if (unlikely(err))
-+		RTW_ERR(FUNC_NDEV_FMT" Vendor Command reply failed ret:%d\n"
-+			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);
-+exit:
-+	rtw_mfree((u8 *)reply, sizeof(int) * num);
-+	return err;
-+}
-+
-+#if defined(GSCAN_SUPPORT) && 0
-+int rtw_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
-+	struct net_device *dev, void  *data, int len, rtw_vendor_event_t event)
-+{
-+	u16 kflags;
-+	const void *ptr;
-+	struct sk_buff *skb;
-+	int malloc_len, total, iter_cnt_to_send, cnt;
-+	gscan_results_cache_t *cache = (gscan_results_cache_t *)data;
-+
-+	total = len / sizeof(wifi_gscan_result_t);
-+	while (total > 0) {
-+		malloc_len = (total * sizeof(wifi_gscan_result_t)) + VENDOR_DATA_OVERHEAD;
-+		if (malloc_len > NLMSG_DEFAULT_SIZE)
-+			malloc_len = NLMSG_DEFAULT_SIZE;
-+		iter_cnt_to_send =
-+			(malloc_len - VENDOR_DATA_OVERHEAD) / sizeof(wifi_gscan_result_t);
-+		total = total - iter_cnt_to_send;
-+
-+		kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
-+
-+		/* Alloc the SKB for vendor_event */
-+		skb = rtw_cfg80211_vendor_event_alloc(wiphy, ndev_to_wdev(dev), malloc_len, event, kflags);
-+		if (!skb) {
-+			WL_ERR(("skb alloc failed"));
-+			return -ENOMEM;
-+		}
-+
-+		while (cache && iter_cnt_to_send) {
-+			ptr = (const void *) &cache->results[cache->tot_consumed];
-+
-+			if (iter_cnt_to_send < (cache->tot_count - cache->tot_consumed))
-+				cnt = iter_cnt_to_send;
-+			else
-+				cnt = (cache->tot_count - cache->tot_consumed);
-+
-+			iter_cnt_to_send -= cnt;
-+			cache->tot_consumed += cnt;
-+			/* Push the data to the skb */
-+			nla_append(skb, cnt * sizeof(wifi_gscan_result_t), ptr);
-+			if (cache->tot_consumed == cache->tot_count)
-+				cache = cache->next;
-+
-+		}
-+
-+		rtw_cfg80211_vendor_event(skb, kflags);
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static int rtw_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy,
-+		struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0;
-+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
-+	dhd_pno_gscan_capabilities_t *reply = NULL;
-+	uint32 reply_len = 0;
-+
-+
-+	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
-+			      DHD_PNO_GET_CAPABILITIES, NULL, &reply_len);
-+	if (!reply) {
-+		WL_ERR(("Could not get capabilities\n"));
-+		err = -EINVAL;
-+		return err;
-+	}
-+
-+	err =  rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
-+					    reply, reply_len);
-+
-+	if (unlikely(err))
-+		WL_ERR(("Vendor Command reply failed ret:%d\n", err));
-+
-+	kfree(reply);
-+	return err;
-+}
-+
-+static int rtw_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy,
-+		struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0, type, band;
-+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
-+	uint16 *reply = NULL;
-+	uint32 reply_len = 0, num_channels, mem_needed;
-+	struct sk_buff *skb;
-+
-+	type = nla_type(data);
-+
-+	if (type == GSCAN_ATTRIBUTE_BAND)
-+		band = nla_get_u32(data);
-+	else
-+		return -1;
-+
-+	reply = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
-+			      DHD_PNO_GET_CHANNEL_LIST, &band, &reply_len);
-+
-+	if (!reply) {
-+		WL_ERR(("Could not get channel list\n"));
-+		err = -EINVAL;
-+		return err;
-+	}
-+	num_channels =  reply_len / sizeof(uint32);
-+	mem_needed = reply_len + VENDOR_REPLY_OVERHEAD + (ATTRIBUTE_U32_LEN * 2);
-+
-+	/* Alloc the SKB for vendor_event */
-+	skb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
-+	if (unlikely(!skb)) {
-+		WL_ERR(("skb alloc failed"));
-+		err = -ENOMEM;
-+		goto exit;
-+	}
-+
-+	nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_CHANNELS, num_channels);
-+	nla_put(skb, GSCAN_ATTRIBUTE_CHANNEL_LIST, reply_len, reply);
-+
-+	err =  rtw_cfg80211_vendor_cmd_reply(skb);
-+
-+	if (unlikely(err))
-+		WL_ERR(("Vendor Command reply failed ret:%d\n", err));
-+exit:
-+	kfree(reply);
-+	return err;
-+}
-+
-+static int rtw_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy,
-+		struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0;
-+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
-+	gscan_results_cache_t *results, *iter;
-+	uint32 reply_len, complete = 0, num_results_iter;
-+	int32 mem_needed;
-+	wifi_gscan_result_t *ptr;
-+	uint16 num_scan_ids, num_results;
-+	struct sk_buff *skb;
-+	struct nlattr *scan_hdr;
-+
-+	dhd_dev_wait_batch_results_complete(bcmcfg_to_prmry_ndev(cfg));
-+	dhd_dev_pno_lock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
-+	results = dhd_dev_pno_get_gscan(bcmcfg_to_prmry_ndev(cfg),
-+				DHD_PNO_GET_BATCH_RESULTS, NULL, &reply_len);
-+
-+	if (!results) {
-+		WL_ERR(("No results to send %d\n", err));
-+		err =  rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
-+						    results, 0);
-+
-+		if (unlikely(err))
-+			WL_ERR(("Vendor Command reply failed ret:%d\n", err));
-+		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
-+		return err;
-+	}
-+	num_scan_ids = reply_len & 0xFFFF;
-+	num_results = (reply_len & 0xFFFF0000) >> 16;
-+	mem_needed = (num_results * sizeof(wifi_gscan_result_t)) +
-+		     (num_scan_ids * GSCAN_BATCH_RESULT_HDR_LEN) +
-+		     VENDOR_REPLY_OVERHEAD + SCAN_RESULTS_COMPLETE_FLAG_LEN;
-+
-+	if (mem_needed > (int32)NLMSG_DEFAULT_SIZE) {
-+		mem_needed = (int32)NLMSG_DEFAULT_SIZE;
-+		complete = 0;
-+	} else
-+		complete = 1;
-+
-+	WL_TRACE(("complete %d mem_needed %d max_mem %d\n", complete, mem_needed,
-+		  (int)NLMSG_DEFAULT_SIZE));
-+	/* Alloc the SKB for vendor_event */
-+	skb = rtw_cfg80211_vendor_cmd_alloc_reply_skb(wiphy, mem_needed);
-+	if (unlikely(!skb)) {
-+		WL_ERR(("skb alloc failed"));
-+		dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
-+		return -ENOMEM;
-+	}
-+	iter = results;
-+
-+	nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE, complete);
-+
-+	mem_needed = mem_needed - (SCAN_RESULTS_COMPLETE_FLAG_LEN + VENDOR_REPLY_OVERHEAD);
-+
-+	while (iter && ((mem_needed - GSCAN_BATCH_RESULT_HDR_LEN)  > 0)) {
-+		scan_hdr = nla_nest_start(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS);
-+		nla_put_u32(skb, GSCAN_ATTRIBUTE_SCAN_ID, iter->scan_id);
-+		nla_put_u8(skb, GSCAN_ATTRIBUTE_SCAN_FLAGS, iter->flag);
-+		num_results_iter =
-+			(mem_needed - GSCAN_BATCH_RESULT_HDR_LEN) / sizeof(wifi_gscan_result_t);
-+
-+		if ((iter->tot_count - iter->tot_consumed) < num_results_iter)
-+			num_results_iter = iter->tot_count - iter->tot_consumed;
-+
-+		nla_put_u32(skb, GSCAN_ATTRIBUTE_NUM_OF_RESULTS, num_results_iter);
-+		if (num_results_iter) {
-+			ptr = &iter->results[iter->tot_consumed];
-+			iter->tot_consumed += num_results_iter;
-+			nla_put(skb, GSCAN_ATTRIBUTE_SCAN_RESULTS,
-+				num_results_iter * sizeof(wifi_gscan_result_t), ptr);
-+		}
-+		nla_nest_end(skb, scan_hdr);
-+		mem_needed -= GSCAN_BATCH_RESULT_HDR_LEN +
-+			      (num_results_iter * sizeof(wifi_gscan_result_t));
-+		iter = iter->next;
-+	}
-+
-+	dhd_dev_gscan_batch_cache_cleanup(bcmcfg_to_prmry_ndev(cfg));
-+	dhd_dev_pno_unlock_access_batch_results(bcmcfg_to_prmry_ndev(cfg));
-+
-+	return rtw_cfg80211_vendor_cmd_reply(skb);
-+}
-+
-+static int rtw_cfgvendor_initiate_gscan(struct wiphy *wiphy,
-+		       struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0;
-+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
-+	int type, tmp = len;
-+	int run = 0xFF;
-+	int flush = 0;
-+	const struct nlattr *iter;
-+
-+	nla_for_each_attr(iter, data, len, tmp) {
-+		type = nla_type(iter);
-+		if (type == GSCAN_ATTRIBUTE_ENABLE_FEATURE)
-+			run = nla_get_u32(iter);
-+		else if (type == GSCAN_ATTRIBUTE_FLUSH_FEATURE)
-+			flush = nla_get_u32(iter);
-+	}
-+
-+	if (run != 0xFF) {
-+		err = dhd_dev_pno_run_gscan(bcmcfg_to_prmry_ndev(cfg), run, flush);
-+
-+		if (unlikely(err))
-+			WL_ERR(("Could not run gscan:%d\n", err));
-+		return err;
-+	} else
-+		return -1;
-+
-+
-+}
-+
-+static int rtw_cfgvendor_enable_full_scan_result(struct wiphy *wiphy,
-+		struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0;
-+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
-+	int type;
-+	bool real_time = FALSE;
-+
-+	type = nla_type(data);
-+
-+	if (type == GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS) {
-+		real_time = nla_get_u32(data);
-+
-+		err = dhd_dev_pno_enable_full_scan_result(bcmcfg_to_prmry_ndev(cfg), real_time);
-+
-+		if (unlikely(err))
-+			WL_ERR(("Could not run gscan:%d\n", err));
-+
-+	} else
-+		err = -1;
-+
-+	return err;
-+}
-+
-+static int rtw_cfgvendor_set_scan_cfg(struct wiphy *wiphy,
-+		     struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0;
-+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
-+	gscan_scan_params_t *scan_param;
-+	int j = 0;
-+	int type, tmp, tmp1, tmp2, k = 0;
-+	const struct nlattr *iter, *iter1, *iter2;
-+	struct dhd_pno_gscan_channel_bucket  *ch_bucket;
-+
-+	scan_param = kzalloc(sizeof(gscan_scan_params_t), GFP_KERNEL);
-+	if (!scan_param) {
-+		WL_ERR(("Could not set GSCAN scan cfg, mem alloc failure\n"));
-+		err = -EINVAL;
-+		return err;
-+
-+	}
-+
-+	scan_param->scan_fr = PNO_SCAN_MIN_FW_SEC;
-+	nla_for_each_attr(iter, data, len, tmp) {
-+		type = nla_type(iter);
-+
-+		if (j >= GSCAN_MAX_CH_BUCKETS)
-+			break;
-+
-+		switch (type) {
-+		case GSCAN_ATTRIBUTE_BASE_PERIOD:
-+			scan_param->scan_fr = nla_get_u32(iter) / 1000;
-+			break;
-+		case GSCAN_ATTRIBUTE_NUM_BUCKETS:
-+			scan_param->nchannel_buckets = nla_get_u32(iter);
-+			break;
-+		case GSCAN_ATTRIBUTE_CH_BUCKET_1:
-+		case GSCAN_ATTRIBUTE_CH_BUCKET_2:
-+		case GSCAN_ATTRIBUTE_CH_BUCKET_3:
-+		case GSCAN_ATTRIBUTE_CH_BUCKET_4:
-+		case GSCAN_ATTRIBUTE_CH_BUCKET_5:
-+		case GSCAN_ATTRIBUTE_CH_BUCKET_6:
-+		case GSCAN_ATTRIBUTE_CH_BUCKET_7:
-+			nla_for_each_nested(iter1, iter, tmp1) {
-+				type = nla_type(iter1);
-+				ch_bucket =
-+					scan_param->channel_bucket;
-+
-+				switch (type) {
-+				case GSCAN_ATTRIBUTE_BUCKET_ID:
-+					break;
-+				case GSCAN_ATTRIBUTE_BUCKET_PERIOD:
-+					ch_bucket[j].bucket_freq_multiple =
-+						nla_get_u32(iter1) / 1000;
-+					break;
-+				case GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS:
-+					ch_bucket[j].num_channels =
-+						nla_get_u32(iter1);
-+					break;
-+				case GSCAN_ATTRIBUTE_BUCKET_CHANNELS:
-+					nla_for_each_nested(iter2, iter1, tmp2) {
-+						if (k >= PFN_SWC_RSSI_WINDOW_MAX)
-+							break;
-+						ch_bucket[j].chan_list[k] =
-+							nla_get_u32(iter2);
-+						k++;
-+					}
-+					k = 0;
-+					break;
-+				case GSCAN_ATTRIBUTE_BUCKETS_BAND:
-+					ch_bucket[j].band = (uint16)
-+							    nla_get_u32(iter1);
-+					break;
-+				case GSCAN_ATTRIBUTE_REPORT_EVENTS:
-+					ch_bucket[j].report_flag = (uint8)
-+							   nla_get_u32(iter1);
-+					break;
-+				}
-+			}
-+			j++;
-+			break;
-+		}
-+	}
-+
-+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
-+				      DHD_PNO_SCAN_CFG_ID, scan_param, 0) < 0) {
-+		WL_ERR(("Could not set GSCAN scan cfg\n"));
-+		err = -EINVAL;
-+	}
-+
-+	kfree(scan_param);
-+	return err;
-+
-+}
-+
-+static int rtw_cfgvendor_hotlist_cfg(struct wiphy *wiphy,
-+		    struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0;
-+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
-+	gscan_hotlist_scan_params_t *hotlist_params;
-+	int tmp, tmp1, tmp2, type, j = 0, dummy;
-+	const struct nlattr *outer, *inner, *iter;
-+	uint8 flush = 0;
-+	struct bssid_t *pbssid;
-+
-+	hotlist_params = (gscan_hotlist_scan_params_t *)kzalloc(len, GFP_KERNEL);
-+	if (!hotlist_params) {
-+		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes\n", len));
-+		return -1;
-+	}
-+
-+	hotlist_params->lost_ap_window = GSCAN_LOST_AP_WINDOW_DEFAULT;
-+
-+	nla_for_each_attr(iter, data, len, tmp2) {
-+		type = nla_type(iter);
-+		switch (type) {
-+		case GSCAN_ATTRIBUTE_HOTLIST_BSSIDS:
-+			pbssid = hotlist_params->bssid;
-+			nla_for_each_nested(outer, iter, tmp) {
-+				nla_for_each_nested(inner, outer, tmp1) {
-+					type = nla_type(inner);
-+
-+					switch (type) {
-+					case GSCAN_ATTRIBUTE_BSSID:
-+						memcpy(&(pbssid[j].macaddr),
-+						       nla_data(inner), ETHER_ADDR_LEN);
-+						break;
-+					case GSCAN_ATTRIBUTE_RSSI_LOW:
-+						pbssid[j].rssi_reporting_threshold =
-+							(int8) nla_get_u8(inner);
-+						break;
-+					case GSCAN_ATTRIBUTE_RSSI_HIGH:
-+						dummy = (int8) nla_get_u8(inner);
-+						break;
-+					}
-+				}
-+				j++;
-+			}
-+			hotlist_params->nbssid = j;
-+			break;
-+		case GSCAN_ATTRIBUTE_HOTLIST_FLUSH:
-+			flush = nla_get_u8(iter);
-+			break;
-+		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
-+			hotlist_params->lost_ap_window = nla_get_u32(iter);
-+			break;
-+		}
-+
-+	}
-+
-+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
-+		DHD_PNO_GEOFENCE_SCAN_CFG_ID, hotlist_params, flush) < 0) {
-+		WL_ERR(("Could not set GSCAN HOTLIST cfg\n"));
-+		err = -EINVAL;
-+		goto exit;
-+	}
-+exit:
-+	kfree(hotlist_params);
-+	return err;
-+}
-+static int rtw_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy,
-+		struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0, tmp, type;
-+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
-+	gscan_batch_params_t batch_param;
-+	const struct nlattr *iter;
-+
-+	batch_param.mscan = batch_param.bestn = 0;
-+	batch_param.buffer_threshold = GSCAN_BATCH_NO_THR_SET;
-+
-+	nla_for_each_attr(iter, data, len, tmp) {
-+		type = nla_type(iter);
-+
-+		switch (type) {
-+		case GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN:
-+			batch_param.bestn = nla_get_u32(iter);
-+			break;
-+		case GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE:
-+			batch_param.mscan = nla_get_u32(iter);
-+			break;
-+		case GSCAN_ATTRIBUTE_REPORT_THRESHOLD:
-+			batch_param.buffer_threshold = nla_get_u32(iter);
-+			break;
-+		}
-+	}
-+
-+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
-+			      DHD_PNO_BATCH_SCAN_CFG_ID, &batch_param, 0) < 0) {
-+		WL_ERR(("Could not set batch cfg\n"));
-+		err = -EINVAL;
-+		return err;
-+	}
-+
-+	return err;
-+}
-+
-+static int rtw_cfgvendor_significant_change_cfg(struct wiphy *wiphy,
-+		struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0;
-+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
-+	gscan_swc_params_t *significant_params;
-+	int tmp, tmp1, tmp2, type, j = 0;
-+	const struct nlattr *outer, *inner, *iter;
-+	uint8 flush = 0;
-+	wl_pfn_significant_bssid_t *pbssid;
-+
-+	significant_params = (gscan_swc_params_t *) kzalloc(len, GFP_KERNEL);
-+	if (!significant_params) {
-+		WL_ERR(("Cannot Malloc mem to parse config commands size - %d bytes\n", len));
-+		return -1;
-+	}
-+
-+
-+	nla_for_each_attr(iter, data, len, tmp2) {
-+		type = nla_type(iter);
-+
-+		switch (type) {
-+		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH:
-+			flush = nla_get_u8(iter);
-+			break;
-+		case GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE:
-+			significant_params->rssi_window = nla_get_u16(iter);
-+			break;
-+		case GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE:
-+			significant_params->lost_ap_window = nla_get_u16(iter);
-+			break;
-+		case GSCAN_ATTRIBUTE_MIN_BREACHING:
-+			significant_params->swc_threshold = nla_get_u16(iter);
-+			break;
-+		case GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS:
-+			pbssid = significant_params->bssid_elem_list;
-+			nla_for_each_nested(outer, iter, tmp) {
-+				nla_for_each_nested(inner, outer, tmp1) {
-+					switch (nla_type(inner)) {
-+					case GSCAN_ATTRIBUTE_BSSID:
-+						memcpy(&(pbssid[j].macaddr),
-+						       nla_data(inner),
-+						       ETHER_ADDR_LEN);
-+						break;
-+					case GSCAN_ATTRIBUTE_RSSI_HIGH:
-+						pbssid[j].rssi_high_threshold =
-+							(int8) nla_get_u8(inner);
-+						break;
-+					case GSCAN_ATTRIBUTE_RSSI_LOW:
-+						pbssid[j].rssi_low_threshold =
-+							(int8) nla_get_u8(inner);
-+						break;
-+					}
-+				}
-+				j++;
-+			}
-+			break;
-+		}
-+	}
-+	significant_params->nbssid = j;
-+
-+	if (dhd_dev_pno_set_cfg_gscan(bcmcfg_to_prmry_ndev(cfg),
-+		DHD_PNO_SIGNIFICANT_SCAN_CFG_ID, significant_params, flush) < 0) {
-+		WL_ERR(("Could not set GSCAN significant cfg\n"));
-+		err = -EINVAL;
-+		goto exit;
-+	}
-+exit:
-+	kfree(significant_params);
-+	return err;
-+}
-+#endif /* GSCAN_SUPPORT */
-+
-+#if defined(RTT_SUPPORT) && 0
-+void rtw_cfgvendor_rtt_evt(void *ctx, void *rtt_data)
-+{
-+	struct wireless_dev *wdev = (struct wireless_dev *)ctx;
-+	struct wiphy *wiphy;
-+	struct sk_buff *skb;
-+	uint32 tot_len = NLMSG_DEFAULT_SIZE, entry_len = 0;
-+	gfp_t kflags;
-+	rtt_report_t *rtt_report = NULL;
-+	rtt_result_t *rtt_result = NULL;
-+	struct list_head *rtt_list;
-+	wiphy = wdev->wiphy;
-+
-+	WL_DBG(("In\n"));
-+	/* Push the data to the skb */
-+	if (!rtt_data) {
-+		WL_ERR(("rtt_data is NULL\n"));
-+		goto exit;
-+	}
-+	rtt_list = (struct list_head *)rtt_data;
-+	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
-+	/* Alloc the SKB for vendor_event */
-+	skb = rtw_cfg80211_vendor_event_alloc(wiphy, wdev, tot_len, GOOGLE_RTT_COMPLETE_EVENT, kflags);
-+	if (!skb) {
-+		WL_ERR(("skb alloc failed"));
-+		goto exit;
-+	}
-+	/* fill in the rtt results on each entry */
-+	list_for_each_entry(rtt_result, rtt_list, list) {
-+		entry_len = 0;
-+		if (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) {
-+			entry_len = sizeof(rtt_report_t);
-+			rtt_report = kzalloc(entry_len, kflags);
-+			if (!rtt_report) {
-+				WL_ERR(("rtt_report alloc failed"));
-+				goto exit;
-+			}
-+			rtt_report->addr = rtt_result->peer_mac;
-+			rtt_report->num_measurement = 1; /* ONE SHOT */
-+			rtt_report->status = rtt_result->err_code;
-+			rtt_report->type = (rtt_result->TOF_type == TOF_TYPE_ONE_WAY) ? RTT_ONE_WAY : RTT_TWO_WAY;
-+			rtt_report->peer = rtt_result->target_info->peer;
-+			rtt_report->channel = rtt_result->target_info->channel;
-+			rtt_report->rssi = rtt_result->avg_rssi;
-+			/* tx_rate */
-+			rtt_report->tx_rate = rtt_result->tx_rate;
-+			/* RTT */
-+			rtt_report->rtt = rtt_result->meanrtt;
-+			rtt_report->rtt_sd = rtt_result->sdrtt;
-+			/* convert to centi meter */
-+			if (rtt_result->distance != 0xffffffff)
-+				rtt_report->distance = (rtt_result->distance >> 2) * 25;
-+			else /* invalid distance */
-+				rtt_report->distance = -1;
-+
-+			rtt_report->ts = rtt_result->ts;
-+			nla_append(skb, entry_len, rtt_report);
-+			kfree(rtt_report);
-+		}
-+	}
-+	rtw_cfg80211_vendor_event(skb, kflags);
-+exit:
-+	return;
-+}
-+
-+static int rtw_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev *wdev,
-+				       const void *data, int len)
-+{
-+	int err = 0, rem, rem1, rem2, type;
-+	rtt_config_params_t rtt_param;
-+	rtt_target_info_t *rtt_target = NULL;
-+	const struct nlattr *iter, *iter1, *iter2;
-+	int8 eabuf[ETHER_ADDR_STR_LEN];
-+	int8 chanbuf[CHANSPEC_STR_LEN];
-+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
-+
-+	WL_DBG(("In\n"));
-+	err = dhd_dev_rtt_register_noti_callback(wdev->netdev, wdev, wl_cfgvendor_rtt_evt);
-+	if (err < 0) {
-+		WL_ERR(("failed to register rtt_noti_callback\n"));
-+		goto exit;
-+	}
-+	memset(&rtt_param, 0, sizeof(rtt_param));
-+	nla_for_each_attr(iter, data, len, rem) {
-+		type = nla_type(iter);
-+		switch (type) {
-+		case RTT_ATTRIBUTE_TARGET_CNT:
-+			rtt_param.rtt_target_cnt = nla_get_u8(iter);
-+			if (rtt_param.rtt_target_cnt > RTT_MAX_TARGET_CNT) {
-+				WL_ERR(("exceed max target count : %d\n",
-+					rtt_param.rtt_target_cnt));
-+				err = BCME_RANGE;
-+			}
-+			break;
-+		case RTT_ATTRIBUTE_TARGET_INFO:
-+			rtt_target = rtt_param.target_info;
-+			nla_for_each_nested(iter1, iter, rem1) {
-+				nla_for_each_nested(iter2, iter1, rem2) {
-+					type = nla_type(iter2);
-+					switch (type) {
-+					case RTT_ATTRIBUTE_TARGET_MAC:
-+						memcpy(&rtt_target->addr, nla_data(iter2), ETHER_ADDR_LEN);
-+						break;
-+					case RTT_ATTRIBUTE_TARGET_TYPE:
-+						rtt_target->type = nla_get_u8(iter2);
-+						break;
-+					case RTT_ATTRIBUTE_TARGET_PEER:
-+						rtt_target->peer = nla_get_u8(iter2);
-+						break;
-+					case RTT_ATTRIBUTE_TARGET_CHAN:
-+						memcpy(&rtt_target->channel, nla_data(iter2),
-+						       sizeof(rtt_target->channel));
-+						break;
-+					case RTT_ATTRIBUTE_TARGET_MODE:
-+						rtt_target->continuous = nla_get_u8(iter2);
-+						break;
-+					case RTT_ATTRIBUTE_TARGET_INTERVAL:
-+						rtt_target->interval = nla_get_u32(iter2);
-+						break;
-+					case RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT:
-+						rtt_target->measure_cnt = nla_get_u32(iter2);
-+						break;
-+					case RTT_ATTRIBUTE_TARGET_NUM_PKT:
-+						rtt_target->ftm_cnt = nla_get_u32(iter2);
-+						break;
-+					case RTT_ATTRIBUTE_TARGET_NUM_RETRY:
-+						rtt_target->retry_cnt = nla_get_u32(iter2);
-+					}
-+				}
-+				/* convert to chanspec value */
-+				rtt_target->chanspec = dhd_rtt_convert_to_chspec(rtt_target->channel);
-+				if (rtt_target->chanspec == 0) {
-+					WL_ERR(("Channel is not valid\n"));
-+					goto exit;
-+				}
-+				WL_INFORM(("Target addr %s, Channel : %s for RTT\n",
-+					bcm_ether_ntoa((const struct ether_addr *)&rtt_target->addr, eabuf),
-+					wf_chspec_ntoa(rtt_target->chanspec, chanbuf)));
-+				rtt_target++;
-+			}
-+			break;
-+		}
-+	}
-+	WL_DBG(("leave :target_cnt : %d\n", rtt_param.rtt_target_cnt));
-+	if (dhd_dev_rtt_set_cfg(bcmcfg_to_prmry_ndev(cfg), &rtt_param) < 0) {
-+		WL_ERR(("Could not set RTT configuration\n"));
-+		err = -EINVAL;
-+	}
-+exit:
-+	return err;
-+}
-+
-+static int rtw_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_dev *wdev,
-+		const void *data, int len)
-+{
-+	int err = 0, rem, type, target_cnt = 0;
-+	const struct nlattr *iter;
-+	struct ether_addr *mac_list = NULL, *mac_addr = NULL;
-+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
-+
-+	nla_for_each_attr(iter, data, len, rem) {
-+		type = nla_type(iter);
-+		switch (type) {
-+		case RTT_ATTRIBUTE_TARGET_CNT:
-+			target_cnt = nla_get_u8(iter);
-+			mac_list = (struct ether_addr *)kzalloc(target_cnt * ETHER_ADDR_LEN , GFP_KERNEL);
-+			if (mac_list == NULL) {
-+				WL_ERR(("failed to allocate mem for mac list\n"));
-+				goto exit;
-+			}
-+			mac_addr = &mac_list[0];
-+			break;
-+		case RTT_ATTRIBUTE_TARGET_MAC:
-+			if (mac_addr)
-+				memcpy(mac_addr++, nla_data(iter), ETHER_ADDR_LEN);
-+			else {
-+				WL_ERR(("mac_list is NULL\n"));
-+				goto exit;
-+			}
-+			break;
-+		}
-+		if (dhd_dev_rtt_cancel_cfg(bcmcfg_to_prmry_ndev(cfg), mac_list, target_cnt) < 0) {
-+			WL_ERR(("Could not cancel RTT configuration\n"));
-+			err = -EINVAL;
-+			goto exit;
-+		}
-+	}
-+exit:
-+	if (mac_list)
-+		kfree(mac_list);
-+	return err;
-+}
-+static int rtw_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_dev *wdev,
-+		const void *data, int len)
-+{
-+	int err = 0;
-+	struct bcm_cfg80211 *cfg = wiphy_priv(wiphy);
-+	rtt_capabilities_t capability;
-+
-+	err = dhd_dev_rtt_capability(bcmcfg_to_prmry_ndev(cfg), &capability);
-+	if (unlikely(err)) {
-+		WL_ERR(("Vendor Command reply failed ret:%d\n", err));
-+		goto exit;
-+	}
-+	err =  rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg),
-+					    &capability, sizeof(capability));
-+
-+	if (unlikely(err))
-+		WL_ERR(("Vendor Command reply failed ret:%d\n", err));
-+exit:
-+	return err;
-+}
-+
-+#endif /* RTT_SUPPORT */
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
-+enum {
-+    LSTATS_SUBCMD_GET_INFO = ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START,
-+	LSTATS_SUBCMD_SET_INFO,
-+	LSTATS_SUBCMD_CLEAR_INFO,
-+};
-+static void LinkLayerStats(_adapter *padapter)
-+{
-+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
-+	struct recv_priv		*precvpriv = &(padapter->recvpriv);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
-+	u32 ps_time, trx_total_time;
-+	u64 tx_bytes, rx_bytes, trx_total_bytes = 0;
-+	u64 tmp = 0;
-+	
-+	RTW_DBG("%s adapter type : %u\n", __func__, padapter->adapter_type);
-+
-+	tx_bytes = 0;
-+	rx_bytes = 0;
-+	ps_time = 0;
-+	trx_total_time = 0;
-+
-+	if ( padapter->netif_up == _TRUE ) {
-+
-+		pwrpriv->on_time = rtw_get_passing_time_ms(pwrpriv->radio_on_start_time);
-+
-+		if (rtw_mi_check_fwstate(padapter, WIFI_ASOC_STATE)) {
-+			if ( pwrpriv->bpower_saving == _TRUE ) {
-+				pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);
-+				pwrpriv->pwr_saving_start_time = rtw_get_current_time();
-+			}
-+		} else {		
-+#ifdef CONFIG_IPS
-+			if ( pwrpriv->bpower_saving == _TRUE ) {
-+				pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);
-+				pwrpriv->pwr_saving_start_time = rtw_get_current_time();
-+			}
-+#else
-+			pwrpriv->pwr_saving_time = pwrpriv->on_time;
-+#endif
-+		}
-+
-+		ps_time = pwrpriv->pwr_saving_time;
-+
-+		/* Deviation caused by caculation start time */
-+		if ( ps_time > pwrpriv->on_time )
-+			ps_time = pwrpriv->on_time;
-+
-+		tx_bytes = pdvobjpriv->traffic_stat.last_tx_bytes;
-+		rx_bytes = pdvobjpriv->traffic_stat.last_rx_bytes;		
-+		trx_total_bytes = tx_bytes + rx_bytes;
-+
-+		trx_total_time = pwrpriv->on_time - ps_time;
-+
-+		if ( trx_total_bytes == 0) {
-+			pwrpriv->tx_time = 0;
-+			pwrpriv->rx_time = 0;
-+		} else {
-+
-+			/* tx_time = (trx_total_time * tx_total_bytes) / trx_total_bytes; */
-+			/* rx_time = (trx_total_time * rx_total_bytes) / trx_total_bytes; */
-+
-+			tmp = (tx_bytes * trx_total_time);
-+			tmp = rtw_division64(tmp, trx_total_bytes);
-+			pwrpriv->tx_time = tmp;
-+
-+			tmp = (rx_bytes * trx_total_time);
-+			tmp = rtw_division64(tmp, trx_total_bytes);
-+			pwrpriv->rx_time = tmp;		
-+
-+		}
-+	
-+	}
-+	else {
-+			pwrpriv->on_time = 0;
-+			pwrpriv->tx_time = 0;
-+			pwrpriv->rx_time = 0;	
-+	}
-+
-+#ifdef CONFIG_RTW_WIFI_HAL_DEBUG
-+	RTW_INFO("- tx_bytes : %llu rx_bytes : %llu total bytes : %llu\n", tx_bytes, rx_bytes, trx_total_bytes);
-+	RTW_INFO("- netif_up = %s, on_time : %u ms\n", padapter->netif_up ? "1":"0", pwrpriv->on_time);
-+	RTW_INFO("- pwr_saving_time : %u (%u) ms\n", pwrpriv->pwr_saving_time, ps_time);
-+	RTW_INFO("- trx_total_time : %u ms\n", trx_total_time);		
-+	RTW_INFO("- tx_time : %u ms\n", pwrpriv->tx_time);
-+	RTW_INFO("- rx_time : %u ms\n", pwrpriv->rx_time);	
-+#endif /* CONFIG_RTW_WIFI_HAL_DEBUG */
-+
-+}
-+
-+#define DUMMY_TIME_STATICS 99
-+static int rtw_cfgvendor_lstats_get_info(struct wiphy *wiphy,	
-+	struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0;
-+	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	wifi_radio_stat_internal *radio;
-+	wifi_iface_stat *iface;
-+	char *output;
-+
-+	output = rtw_malloc(sizeof(wifi_radio_stat_internal) + sizeof(wifi_iface_stat));
-+	if (output == NULL) {
-+		RTW_DBG("Allocate lstats info buffer fail!\n");
-+	}
-+
-+	radio = (wifi_radio_stat_internal *)output;
-+
-+	radio->num_channels = 0;
-+	radio->radio = 1;
-+
-+	/* to get on_time, tx_time, rx_time */
-+	LinkLayerStats(padapter); 
-+	
-+	radio->on_time = pwrpriv->on_time;
-+	radio->tx_time = pwrpriv->tx_time;
-+	radio->rx_time = pwrpriv->rx_time;
-+	radio->on_time_scan = 0;
-+	radio->on_time_nbd = 0;
-+	radio->on_time_gscan = 0;
-+	radio->on_time_pno_scan = 0;
-+	radio->on_time_hs20 = 0;
-+	#ifdef CONFIG_RTW_WIFI_HAL_DEBUG
-+	RTW_INFO("==== %s ====\n", __func__);
-+	RTW_INFO("radio->radio : %d\n", (radio->radio));
-+	RTW_INFO("pwrpriv->on_time : %u ms\n", (pwrpriv->on_time));
-+	RTW_INFO("pwrpriv->tx_time :  %u ms\n", (pwrpriv->tx_time));
-+	RTW_INFO("pwrpriv->rx_time :  %u ms\n", (pwrpriv->rx_time));
-+	RTW_INFO("radio->on_time :  %u ms\n", (radio->on_time));
-+	RTW_INFO("radio->tx_time :  %u ms\n", (radio->tx_time));
-+	RTW_INFO("radio->rx_time :  %u ms\n", (radio->rx_time));
-+	#endif /* CONFIG_RTW_WIFI_HAL_DEBUG */
-+	
-+	RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
-+	err =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), 
-+		output, sizeof(wifi_iface_stat) + sizeof(wifi_radio_stat_internal));
-+	if (unlikely(err))
-+		RTW_ERR(FUNC_NDEV_FMT"Vendor Command reply failed ret:%d \n"
-+			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);
-+	rtw_mfree(output, sizeof(wifi_iface_stat) + sizeof(wifi_radio_stat_internal));
-+	return err;
-+}
-+static int rtw_cfgvendor_lstats_set_info(struct wiphy *wiphy,	
-+	struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0;
-+	RTW_INFO("%s\n", __func__);
-+	return err;
-+}
-+static int rtw_cfgvendor_lstats_clear_info(struct wiphy *wiphy,	
-+	struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0;
-+	RTW_INFO("%s\n", __func__);
-+	return err;
-+}
-+#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
-+#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
-+static int rtw_cfgvendor_set_rssi_monitor(struct wiphy *wiphy,
-+	struct wireless_dev *wdev, const void  *data, int len)
-+{
-+        _adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
-+        struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+
-+        struct recv_priv *precvpriv = &padapter->recvpriv;
-+	int err = 0, rem, type;
-+        const struct nlattr *iter;
-+
-+        RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
-+
-+	nla_for_each_attr(iter, data, len, rem) {
-+		type = nla_type(iter);
-+
-+		switch (type) {
-+        		case RSSI_MONITOR_ATTRIBUTE_MAX_RSSI:
-+                                pwdev_priv->rssi_monitor_max = (s8)nla_get_u32(iter);;
-+	        		break;
-+		        case RSSI_MONITOR_ATTRIBUTE_MIN_RSSI:
-+                                pwdev_priv->rssi_monitor_min = (s8)nla_get_u32(iter);
-+			        break;
-+        		case RSSI_MONITOR_ATTRIBUTE_START:
-+                                pwdev_priv->rssi_monitor_enable = (u8)nla_get_u32(iter);
-+	        		break;
-+		}
-+	}
-+
-+	return err;
-+}
-+
-+void rtw_cfgvendor_rssi_monitor_evt(_adapter *padapter) {
-+	struct wireless_dev *wdev =  padapter->rtw_wdev;
-+	struct wiphy *wiphy= wdev->wiphy;
-+        struct recv_priv *precvpriv = &padapter->recvpriv;
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	struct	wlan_network	*pcur_network = &pmlmepriv->cur_network;
-+        struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-+	struct sk_buff *skb;
-+	u32 tot_len = NLMSG_DEFAULT_SIZE;
-+	gfp_t kflags;
-+        rssi_monitor_evt data ;
-+        s8 rssi = precvpriv->rssi;
-+
-+        if (pwdev_priv->rssi_monitor_enable == 0 || check_fwstate(pmlmepriv, WIFI_ASOC_STATE) != _TRUE)
-+                return;
-+
-+        if (rssi < pwdev_priv->rssi_monitor_max || rssi > pwdev_priv->rssi_monitor_min)
-+                return;
-+
-+	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
-+
-+	/* Alloc the SKB for vendor_event */
-+	skb = rtw_cfg80211_vendor_event_alloc(wiphy, wdev, tot_len, GOOGLE_RSSI_MONITOR_EVENT, kflags);
-+	if (!skb) {
-+		goto exit;
-+	}
-+
-+        _rtw_memset(&data, 0, sizeof(data));
-+
-+        data.version = RSSI_MONITOR_EVT_VERSION;
-+        data.cur_rssi = rssi;
-+        _rtw_memcpy(data.BSSID, pcur_network->network.MacAddress, sizeof(mac_addr));
-+
-+        nla_append(skb, sizeof(data), &data);
-+
-+	rtw_cfg80211_vendor_event(skb, kflags);
-+exit:
-+	return;
-+}
-+#endif /* CONFIG_RTW_CFGVENDOR_RSSIMONITR */
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
-+static int rtw_cfgvendor_logger_start_logging(struct wiphy *wiphy,
-+	struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int ret = 0, rem, type;
-+	char ring_name[32] = {0};
-+	int log_level = 0, flags = 0, time_intval = 0, threshold = 0;
-+	const struct nlattr *iter;
-+
-+	nla_for_each_attr(iter, data, len, rem) {
-+		type = nla_type(iter);
-+		switch (type) {
-+			case LOGGER_ATTRIBUTE_RING_NAME:
-+				strncpy(ring_name, nla_data(iter),
-+					MIN(sizeof(ring_name) -1, nla_len(iter)));
-+				break;
-+			case LOGGER_ATTRIBUTE_LOG_LEVEL:
-+				log_level = nla_get_u32(iter);
-+				break;
-+			case LOGGER_ATTRIBUTE_RING_FLAGS:
-+				flags = nla_get_u32(iter);
-+				break;
-+			case LOGGER_ATTRIBUTE_LOG_TIME_INTVAL:
-+				time_intval = nla_get_u32(iter);
-+				break;
-+			case LOGGER_ATTRIBUTE_LOG_MIN_DATA_SIZE:
-+				threshold = nla_get_u32(iter);
-+				break;
-+			default:
-+				RTW_ERR("Unknown type: %d\n", type);
-+				ret = WIFI_ERROR_INVALID_ARGS;
-+				goto exit;
-+		}
-+	}
-+
-+exit:
-+	return ret;
-+}
-+static int rtw_cfgvendor_logger_get_feature(struct wiphy *wiphy,
-+	struct wireless_dev *wdev, const void *data, int len)
-+{
-+	int err = 0;
-+	u32 supported_features = 0;
-+
-+	err =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &supported_features, sizeof(supported_features));
-+
-+	if (unlikely(err))
-+		RTW_ERR(FUNC_NDEV_FMT" Vendor Command reply failed ret:%d\n"
-+			, FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err);
-+
-+	return err;
-+}
-+static int rtw_cfgvendor_logger_get_version(struct wiphy *wiphy,
-+	struct wireless_dev *wdev, const void *data, int len)
-+{
-+	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
-+	HAL_DATA_TYPE *hal = GET_HAL_DATA(padapter);
-+	int ret = 0, rem, type;
-+	int buf_len = 1024;
-+	char *buf_ptr;
-+	const struct nlattr *iter;
-+	gfp_t kflags;
-+
-+	kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL;
-+	buf_ptr = kzalloc(buf_len, kflags);
-+	if (!buf_ptr) {
-+		RTW_ERR("failed to allocate the buffer for version n");
-+		ret = -ENOMEM;
-+		goto exit;
-+	}
-+	nla_for_each_attr(iter, data, len, rem) {
-+		type = nla_type(iter);
-+		switch (type) {
-+			case LOGGER_ATTRIBUTE_GET_DRIVER:
-+				memcpy(buf_ptr, DRIVERVERSION, strlen(DRIVERVERSION)+1);
-+				break;
-+			case LOGGER_ATTRIBUTE_GET_FW:
-+				sprintf(buf_ptr, "v%d.%d", hal->firmware_version, hal->firmware_sub_version);
-+				break;
-+			default:
-+				RTW_ERR("Unknown type: %d\n", type);
-+				ret = -EINVAL;
-+				goto exit;
-+		}
-+	}
-+	if (ret < 0) {
-+		RTW_ERR("failed to get the version %d\n", ret);
-+		goto exit;
-+	}
-+
-+
-+	ret =  rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), buf_ptr, strlen(buf_ptr));
-+exit:
-+	kfree(buf_ptr);
-+	return ret;
-+}
-+
-+static int rtw_cfgvendor_logger_get_ring_status(struct wiphy *wiphy,
-+	struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int ret = 0;
-+	int ring_id;
-+	char ring_buf_name[] = "RTW_RING_BUFFER";
-+
-+	struct sk_buff *skb;
-+	wifi_ring_buffer_status ring_status;
-+
-+
-+	_rtw_memcpy(ring_status.name, ring_buf_name, strlen(ring_buf_name)+1);
-+	ring_status.ring_id = 1;
-+	/* Alloc the SKB for vendor_event */
-+	skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy,
-+		sizeof(wifi_ring_buffer_status));
-+	if (!skb) {
-+		RTW_ERR("skb allocation is failed\n");
-+		ret = FAIL;
-+		goto exit;
-+	}
-+
-+	nla_put_u32(skb, LOGGER_ATTRIBUTE_RING_NUM, 1);
-+	nla_put(skb, LOGGER_ATTRIBUTE_RING_STATUS, sizeof(wifi_ring_buffer_status),
-+				&ring_status);
-+	ret = cfg80211_vendor_cmd_reply(skb);
-+
-+	if (ret) {
-+		RTW_ERR("Vendor Command reply failed ret:%d \n", ret);
-+	}
-+exit:
-+	return ret;
-+}
-+
-+static int rtw_cfgvendor_logger_get_ring_data(struct wiphy *wiphy,
-+	struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int ret = 0, rem, type;
-+	char ring_name[32] = {0};
-+	const struct nlattr *iter;
-+
-+	nla_for_each_attr(iter, data, len, rem) {
-+		type = nla_type(iter);
-+		switch (type) {
-+			case LOGGER_ATTRIBUTE_RING_NAME:
-+				strncpy(ring_name, nla_data(iter),
-+					MIN(sizeof(ring_name) -1, nla_len(iter)));
-+				RTW_INFO(" %s LOGGER_ATTRIBUTE_RING_NAME : %s\n", __func__, ring_name);
-+				break;
-+			default:
-+				RTW_ERR("Unknown type: %d\n", type);
-+				return ret;
-+		}
-+	}
-+
-+
-+	return ret;
-+}
-+
-+static int rtw_cfgvendor_logger_get_firmware_memory_dump(struct wiphy *wiphy,
-+	struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int ret = WIFI_ERROR_NOT_SUPPORTED;
-+
-+	return ret;
-+}
-+
-+static int rtw_cfgvendor_logger_start_pkt_fate_monitoring(struct wiphy *wiphy,
-+	struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int ret = WIFI_SUCCESS;
-+
-+	return ret;
-+}
-+
-+static int rtw_cfgvendor_logger_get_tx_pkt_fates(struct wiphy *wiphy,
-+	struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int ret = WIFI_SUCCESS;
-+
-+	return ret;
-+}
-+
-+static int rtw_cfgvendor_logger_get_rx_pkt_fates(struct wiphy *wiphy,
-+	struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int ret = WIFI_SUCCESS;
-+
-+	return ret;
-+}
-+
-+#endif /* CONFIG_RTW_CFGVENDOR_WIFI_LOGGER */
-+#ifdef CONFIG_RTW_WIFI_HAL
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+
-+#ifndef ETHER_ISMULTI
-+#define ETHER_ISMULTI(ea) (((const u8 *)(ea))[0] & 1)
-+#endif
-+
-+
-+static u8 null_addr[ETH_ALEN] = {0};
-+static void rtw_hal_random_gen_mac_addr(u8 *mac_addr)
-+{
-+	do {
-+		get_random_bytes(&mac_addr[3], ETH_ALEN-3);
-+		if (memcmp(mac_addr, null_addr, ETH_ALEN) != 0)
-+			break;
-+	} while(1);
-+}
-+
-+void rtw_hal_pno_random_gen_mac_addr(PADAPTER adapter)
-+{
-+	u8 mac_addr[ETH_ALEN];
-+	struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
-+
-+	memcpy(mac_addr, pwdev_priv->pno_mac_addr, ETH_ALEN);
-+	if (mac_addr[0] == 0xFF) return;
-+	rtw_hal_random_gen_mac_addr(mac_addr);
-+	memcpy(pwdev_priv->pno_mac_addr, mac_addr, ETH_ALEN);
-+#ifdef CONFIG_RTW_DEBUG
-+	print_hex_dump(KERN_DEBUG, "pno_mac_addr: ",
-+		       DUMP_PREFIX_OFFSET, 16, 1, pwdev_priv->pno_mac_addr,
-+		       ETH_ALEN, 1);
-+#endif
-+}
-+
-+void rtw_hal_set_hw_mac_addr(PADAPTER adapter, u8 *mac_addr)
-+{
-+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
-+	LeaveAllPowerSaveModeDirect(adapter);
-+
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+	rtw_hal_change_macaddr_mbid(adapter, mac_addr);
-+#else
-+	rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, mac_addr);
-+#endif
-+#ifdef CONFIG_RTW_DEBUG
-+	rtw_hal_dump_macaddr(RTW_DBGDUMP, adapter);
-+#endif
-+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
-+}
-+
-+static int rtw_cfgvendor_set_rand_mac_oui(struct wiphy *wiphy,
-+		struct wireless_dev *wdev, const void  *data, int len)
-+{
-+	int err = 0;
-+	PADAPTER adapter;
-+	void *devaddr;
-+	struct net_device *netdev;
-+	int type, mac_len;
-+	u8 pno_random_mac_oui[3];
-+	u8 mac_addr[ETH_ALEN] = {0};
-+	struct pwrctrl_priv *pwrctl;
-+	struct rtw_wdev_priv *pwdev_priv;
-+
-+	type = nla_type(data);
-+	mac_len = nla_len(data);
-+	if (mac_len != 3) {
-+		RTW_ERR("%s oui len error %d != 3\n", __func__, mac_len);
-+		return -1;
-+	}
-+
-+	if (type == ANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI) {
-+		memcpy(pno_random_mac_oui, nla_data(data), 3);
-+		print_hex_dump(KERN_DEBUG, "pno_random_mac_oui: ",
-+			       DUMP_PREFIX_OFFSET, 16, 1, pno_random_mac_oui,
-+			       3, 1);
-+
-+		if (ETHER_ISMULTI(pno_random_mac_oui)) {
-+			pr_err("%s: oui is multicast address\n", __func__);
-+			return -1;
-+		}
-+
-+		adapter = wiphy_to_adapter(wiphy);
-+		if (adapter == NULL) {
-+			pr_err("%s: wiphy_to_adapter == NULL\n", __func__);
-+			return -1;
-+		}
-+
-+		pwdev_priv = adapter_wdev_data(adapter);
-+
-+		memcpy(mac_addr, pno_random_mac_oui, 3);
-+		rtw_hal_random_gen_mac_addr(mac_addr);
-+		memcpy(pwdev_priv->pno_mac_addr, mac_addr, ETH_ALEN);
-+#ifdef CONFIG_RTW_DEBUG
-+		print_hex_dump(KERN_DEBUG, "pno_mac_addr: ",
-+			       DUMP_PREFIX_OFFSET, 16, 1, pwdev_priv->pno_mac_addr,
-+			       ETH_ALEN, 1);
-+#endif
-+	} else {
-+		RTW_ERR("%s oui type error %x != 0x2\n", __func__, type);
-+		err = -1;
-+	}
-+
-+
-+	return err;
-+}
-+
-+#endif
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_WIFI_OFFLOAD
-+static int rtw_cfgvendor_start_mkeep_alive(struct wiphy *wiphy, struct wireless_dev *wdev,
-+	const void *data, int len)
-+{
-+	int ret = WIFI_SUCCESS;
-+
-+	RTW_INFO("%s : TODO\n", __func__);
-+
-+	return ret;
-+}
-+
-+static int rtw_cfgvendor_stop_mkeep_alive(struct wiphy *wiphy, struct wireless_dev *wdev,
-+	const void *data, int len)
-+{
-+	int ret = WIFI_SUCCESS;
-+
-+	RTW_INFO("%s : TODO\n", __func__);
-+
-+	return ret;
-+}
-+#endif
-+
-+static int rtw_cfgvendor_set_nodfs_flag(struct wiphy *wiphy,
-+	struct wireless_dev *wdev, const void *data, int len)
-+{
-+	int err = 0;	
-+	int type;
-+	u32 nodfs = 0;
-+	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
-+
-+	RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
-+
-+	type = nla_type(data);
-+	if (type == ANDR_WIFI_ATTRIBUTE_NODFS_SET) {
-+		nodfs = nla_get_u32(data);
-+		adapter_to_dvobj(padapter)->nodfs = nodfs;
-+	} else {
-+		err = -EINVAL;
-+	}
-+
-+	RTW_INFO("%s nodfs=%d, err=%d\n", __func__, nodfs, err);
-+	
-+	return err;
-+}
-+
-+static int rtw_cfgvendor_set_country(struct wiphy *wiphy,
-+	struct wireless_dev *wdev, const void  *data, int len)
-+{
-+#define CNTRY_BUF_SZ	4	/* Country string is 3 bytes + NUL */
-+	int err = 0, rem, type;
-+	char country_code[CNTRY_BUF_SZ] = {0};
-+	const struct nlattr *iter;
-+	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
-+
-+	RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
-+
-+	nla_for_each_attr(iter, data, len, rem) {
-+		type = nla_type(iter);
-+		switch (type) {
-+			case ANDR_WIFI_ATTRIBUTE_COUNTRY:
-+				_rtw_memcpy(country_code, nla_data(iter),
-+					MIN(nla_len(iter), CNTRY_BUF_SZ));
-+				break;
-+			default:
-+				RTW_ERR("Unknown type: %d\n", type);
-+				return -EINVAL;
-+		}
-+	}
-+
-+	RTW_INFO("%s country_code:\"%c%c\" \n", __func__, country_code[0], country_code[1]);
-+
-+	rtw_set_country(padapter, country_code);
-+
-+	return err;
-+}
-+
-+static int rtw_cfgvendor_set_nd_offload(struct wiphy *wiphy,
-+	struct wireless_dev *wdev, const void *data, int len)
-+{
-+	int err = 0;	
-+	int type;
-+	u8 nd_en = 0;
-+	_adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy));
-+
-+	RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data);
-+
-+	type = nla_type(data);
-+	if (type == ANDR_WIFI_ATTRIBUTE_ND_OFFLOAD_VALUE) {
-+		nd_en = nla_get_u8(data);
-+		/* ND has been enabled when wow is enabled */
-+	} else {
-+		err = -EINVAL;
-+	}
-+
-+	RTW_INFO("%s nd_en=%d, err=%d\n", __func__, nd_en, err);
-+	
-+	return err;
-+}
-+#endif /* CONFIG_RTW_WIFI_HAL */
-+
-+static const struct wiphy_vendor_command rtw_vendor_cmds[] = {
-+#if defined(GSCAN_SUPPORT) && 0
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = GSCAN_SUBCMD_GET_CAPABILITIES
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+		.doit = rtw_cfgvendor_gscan_get_capabilities
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = GSCAN_SUBCMD_SET_CONFIG
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+		.doit = rtw_cfgvendor_set_scan_cfg
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+		.doit = rtw_cfgvendor_set_batch_scan_cfg
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = GSCAN_SUBCMD_ENABLE_GSCAN
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+		.doit = rtw_cfgvendor_initiate_gscan
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+		.doit = rtw_cfgvendor_enable_full_scan_result
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = GSCAN_SUBCMD_SET_HOTLIST
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+		.doit = rtw_cfgvendor_hotlist_cfg
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+		.doit = rtw_cfgvendor_significant_change_cfg
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+		.doit = rtw_cfgvendor_gscan_get_batch_results
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+		.doit = rtw_cfgvendor_gscan_get_channel_list
-+	},
-+#endif /* GSCAN_SUPPORT */
-+#if defined(RTT_SUPPORT) && 0
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = RTT_SUBCMD_SET_CONFIG
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+		.doit = rtw_cfgvendor_rtt_set_config
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = RTT_SUBCMD_CANCEL_CONFIG
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+		.doit = rtw_cfgvendor_rtt_cancel_config
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = RTT_SUBCMD_GETCAPABILITY
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+		.doit = rtw_cfgvendor_rtt_get_capability
-+	},
-+#endif /* RTT_SUPPORT */
-+#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = LSTATS_SUBCMD_GET_INFO
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_lstats_get_info
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = LSTATS_SUBCMD_SET_INFO
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_lstats_set_info
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = LSTATS_SUBCMD_CLEAR_INFO
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_lstats_clear_info
-+	},
-+#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
-+#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
-+        {
-+                {
-+                        .vendor_id = OUI_GOOGLE,
-+                        .subcmd = WIFI_SUBCMD_SET_RSSI_MONITOR
-+                },
-+                .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+                .doit = rtw_cfgvendor_set_rssi_monitor
-+        },
-+#endif /* CONFIG_RTW_CFGVENDOR_RSSIMONITOR */
-+#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = LOGGER_START_LOGGING
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_logger_start_logging
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = LOGGER_GET_FEATURE
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_logger_get_feature
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = LOGGER_GET_VER
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_logger_get_version
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = LOGGER_GET_RING_STATUS
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_logger_get_ring_status
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = LOGGER_GET_RING_DATA
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_logger_get_ring_data
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = LOGGER_TRIGGER_MEM_DUMP
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_logger_get_firmware_memory_dump
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = LOGGER_START_PKT_FATE_MONITORING
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_logger_start_pkt_fate_monitoring
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = LOGGER_GET_TX_PKT_FATES
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_logger_get_tx_pkt_fates
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = LOGGER_GET_RX_PKT_FATES
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_logger_get_rx_pkt_fates
-+	},	
-+#endif /* CONFIG_RTW_CFGVENDOR_WIFI_LOGGER */
-+#ifdef CONFIG_RTW_WIFI_HAL
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = WIFI_SUBCMD_SET_PNO_RANDOM_MAC_OUI
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_set_rand_mac_oui
-+	},
-+#endif
-+#ifdef CONFIG_RTW_CFGVENDOR_WIFI_OFFLOAD
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = WIFI_OFFLOAD_SUBCMD_START_MKEEP_ALIVE
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_start_mkeep_alive
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = WIFI_OFFLOAD_SUBCMD_STOP_MKEEP_ALIVE
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_stop_mkeep_alive
-+	},
-+#endif
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = WIFI_SUBCMD_NODFS_SET
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_set_nodfs_flag
-+
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = WIFI_SUBCMD_SET_COUNTRY_CODE
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_set_country
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = WIFI_SUBCMD_CONFIG_ND_OFFLOAD
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_set_nd_offload
-+	},
-+#endif /* CONFIG_RTW_WIFI_HAL */
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = WIFI_SUBCMD_GET_FEATURE_SET
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_get_feature_set
-+	},
-+	{
-+		{
-+			.vendor_id = OUI_GOOGLE,
-+			.subcmd = WIFI_SUBCMD_GET_FEATURE_SET_MATRIX
-+		},
-+		.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0))
-+		.policy = VENDOR_CMD_RAW_DATA,
-+#endif
-+		.doit = rtw_cfgvendor_get_feature_set_matrix
-+	}
-+};
-+
-+static const struct  nl80211_vendor_cmd_info rtw_vendor_events[] = {
-+#if defined(GSCAN_SUPPORT) && 0
-+	{ OUI_GOOGLE, GSCAN_EVENT_SIGNIFICANT_CHANGE_RESULTS },
-+	{ OUI_GOOGLE, GSCAN_EVENT_HOTLIST_RESULTS_FOUND },
-+	{ OUI_GOOGLE, GSCAN_EVENT_SCAN_RESULTS_AVAILABLE },
-+	{ OUI_GOOGLE, GSCAN_EVENT_FULL_SCAN_RESULTS },
-+#endif /* GSCAN_SUPPORT */
-+#if defined(RTT_SUPPORT) && 0
-+	{ OUI_GOOGLE, RTT_EVENT_COMPLETE },
-+#endif /* RTT_SUPPORT */
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
-+	{ OUI_GOOGLE, GOOGLE_RSSI_MONITOR_EVENT },
-+#endif /* RTW_CFGVENDOR_RSSIMONITR */
-+
-+#if defined(GSCAN_SUPPORT) && 0
-+	{ OUI_GOOGLE, GSCAN_EVENT_COMPLETE_SCAN },
-+	{ OUI_GOOGLE, GSCAN_EVENT_HOTLIST_RESULTS_LOST }
-+#endif /* GSCAN_SUPPORT */
-+};
-+
-+int rtw_cfgvendor_attach(struct wiphy *wiphy)
-+{
-+
-+	RTW_INFO("Register RTW cfg80211 vendor cmd(0x%x) interface\n", NL80211_CMD_VENDOR);
-+
-+	wiphy->vendor_commands	= rtw_vendor_cmds;
-+	wiphy->n_vendor_commands = ARRAY_SIZE(rtw_vendor_cmds);
-+	wiphy->vendor_events	= rtw_vendor_events;
-+	wiphy->n_vendor_events	= ARRAY_SIZE(rtw_vendor_events);
-+
-+	return 0;
-+}
-+
-+int rtw_cfgvendor_detach(struct wiphy *wiphy)
-+{
-+	RTW_INFO("Vendor: Unregister RTW cfg80211 vendor interface\n");
-+
-+	wiphy->vendor_commands  = NULL;
-+	wiphy->vendor_events    = NULL;
-+	wiphy->n_vendor_commands = 0;
-+	wiphy->n_vendor_events  = 0;
-+
-+	return 0;
-+}
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */
-+
-+#endif /* CONFIG_IOCTL_CFG80211 */
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/rtw_cfgvendor.h b/drivers/staging/rtl8723cs/os_dep/linux/rtw_cfgvendor.h
-new file mode 100644
-index 000000000000..0e59b2b9454e
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/rtw_cfgvendor.h
-@@ -0,0 +1,636 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef _RTW_CFGVENDOR_H_
-+#define _RTW_CFGVENDOR_H_
-+
-+#define OUI_GOOGLE  0x001A11
-+#define ATTRIBUTE_U32_LEN                  (NLA_HDRLEN  + 4)
-+#define VENDOR_ID_OVERHEAD                 ATTRIBUTE_U32_LEN
-+#define VENDOR_SUBCMD_OVERHEAD             ATTRIBUTE_U32_LEN
-+#define VENDOR_DATA_OVERHEAD               (NLA_HDRLEN)
-+
-+#define SCAN_RESULTS_COMPLETE_FLAG_LEN       ATTRIBUTE_U32_LEN
-+#define SCAN_INDEX_HDR_LEN                   (NLA_HDRLEN)
-+#define SCAN_ID_HDR_LEN                      ATTRIBUTE_U32_LEN
-+#define SCAN_FLAGS_HDR_LEN                   ATTRIBUTE_U32_LEN
-+#define GSCAN_NUM_RESULTS_HDR_LEN            ATTRIBUTE_U32_LEN
-+#define GSCAN_RESULTS_HDR_LEN                (NLA_HDRLEN)
-+#define GSCAN_BATCH_RESULT_HDR_LEN  (SCAN_INDEX_HDR_LEN + SCAN_ID_HDR_LEN + \
-+				     SCAN_FLAGS_HDR_LEN + \
-+				     GSCAN_NUM_RESULTS_HDR_LEN + \
-+				     GSCAN_RESULTS_HDR_LEN)
-+
-+#define VENDOR_REPLY_OVERHEAD       (VENDOR_ID_OVERHEAD + \
-+				     VENDOR_SUBCMD_OVERHEAD + \
-+				     VENDOR_DATA_OVERHEAD)
-+typedef enum {
-+    /* don't use 0 as a valid subcommand */
-+    VENDOR_NL80211_SUBCMD_UNSPECIFIED,
-+
-+    /* define all vendor startup commands between 0x0 and 0x0FFF */
-+    VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001,
-+    VENDOR_NL80211_SUBCMD_RANGE_END   = 0x0FFF,
-+
-+    /* define all GScan related commands between 0x1000 and 0x10FF */
-+    ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000,
-+    ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END   = 0x10FF,
-+
-+    /* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */
-+    ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100,
-+    ANDROID_NL80211_SUBCMD_NBD_RANGE_END   = 0x11FF,
-+
-+    /* define all RTT related commands between 0x1100 and 0x11FF */
-+    ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100,
-+    ANDROID_NL80211_SUBCMD_RTT_RANGE_END   = 0x11FF,
-+
-+    ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200,
-+    ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END   = 0x12FF,
-+
-+    /* define all Logger related commands between 0x1400 and 0x14FF */
-+    ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START = 0x1400,
-+    ANDROID_NL80211_SUBCMD_DEBUG_RANGE_END   = 0x14FF,
-+
-+    /* define all wifi offload related commands between 0x1600 and 0x16FF */
-+    ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START = 0x1600,
-+    ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_END   = 0x16FF,
-+
-+    /* define all NAN related commands between 0x1700 and 0x17FF */
-+    ANDROID_NL80211_SUBCMD_NAN_RANGE_START = 0x1700,
-+    ANDROID_NL80211_SUBCMD_NAN_RANGE_END   = 0x17FF,
-+
-+    /* define all Android Packet Filter related commands between 0x1800 and 0x18FF */
-+    ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START = 0x1800,
-+    ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_END   = 0x18FF,
-+
-+    /* This is reserved for future usage */
-+
-+} ANDROID_VENDOR_SUB_COMMAND;
-+
-+enum rtw_vendor_subcmd {
-+    GSCAN_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START,
-+
-+    GSCAN_SUBCMD_SET_CONFIG,                            /* 0x1001 */
-+
-+    GSCAN_SUBCMD_SET_SCAN_CONFIG,                       /* 0x1002 */
-+    GSCAN_SUBCMD_ENABLE_GSCAN,                          /* 0x1003 */
-+    GSCAN_SUBCMD_GET_SCAN_RESULTS,                      /* 0x1004 */
-+    GSCAN_SUBCMD_SCAN_RESULTS,                          /* 0x1005 */
-+
-+    GSCAN_SUBCMD_SET_HOTLIST,                           /* 0x1006 */
-+
-+    GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG,         /* 0x1007 */
-+    GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS,              /* 0x1008 */
-+    GSCAN_SUBCMD_GET_CHANNEL_LIST,                       /* 0x1009 */
-+
-+    WIFI_SUBCMD_GET_FEATURE_SET,                         /* 0x100A */
-+    WIFI_SUBCMD_GET_FEATURE_SET_MATRIX,                  /* 0x100B */
-+    WIFI_SUBCMD_SET_PNO_RANDOM_MAC_OUI,                  /* 0x100C */
-+    WIFI_SUBCMD_NODFS_SET,                               /* 0x100D */
-+    WIFI_SUBCMD_SET_COUNTRY_CODE,                             /* 0x100E */
-+    /* Add more sub commands here */
-+    GSCAN_SUBCMD_SET_EPNO_SSID,                          /* 0x100F */
-+
-+    WIFI_SUBCMD_SET_SSID_WHITE_LIST,                    /* 0x1010 */
-+    WIFI_SUBCMD_SET_ROAM_PARAMS,                        /* 0x1011 */
-+    WIFI_SUBCMD_ENABLE_LAZY_ROAM,                       /* 0x1012 */
-+    WIFI_SUBCMD_SET_BSSID_PREF,                         /* 0x1013 */
-+    WIFI_SUBCMD_SET_BSSID_BLACKLIST,                     /* 0x1014 */
-+
-+    GSCAN_SUBCMD_ANQPO_CONFIG,                          /* 0x1015 */
-+    WIFI_SUBCMD_SET_RSSI_MONITOR,                       /* 0x1016 */
-+    WIFI_SUBCMD_CONFIG_ND_OFFLOAD,                      /* 0x1017 */
-+    /* Add more sub commands here */
-+
-+    GSCAN_SUBCMD_MAX,
-+
-+	RTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START,
-+	RTT_SUBCMD_CANCEL_CONFIG,
-+	RTT_SUBCMD_GETCAPABILITY,
-+
-+    APF_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START,
-+    APF_SUBCMD_SET_FILTER,
-+    
-+    LOGGER_START_LOGGING = ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START,
-+    LOGGER_TRIGGER_MEM_DUMP,
-+    LOGGER_GET_MEM_DUMP,
-+    LOGGER_GET_VER,
-+    LOGGER_GET_RING_STATUS,
-+    LOGGER_GET_RING_DATA,
-+    LOGGER_GET_FEATURE,
-+    LOGGER_RESET_LOGGING,
-+    LOGGER_TRIGGER_DRIVER_MEM_DUMP,
-+    LOGGER_GET_DRIVER_MEM_DUMP,
-+    LOGGER_START_PKT_FATE_MONITORING,
-+    LOGGER_GET_TX_PKT_FATES,
-+    LOGGER_GET_RX_PKT_FATES,
-+
-+	WIFI_OFFLOAD_SUBCMD_START_MKEEP_ALIVE = ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START,
-+	WIFI_OFFLOAD_SUBCMD_STOP_MKEEP_ALIVE,
-+
-+	VENDOR_SUBCMD_MAX
-+};
-+
-+enum gscan_attributes {
-+	GSCAN_ATTRIBUTE_NUM_BUCKETS = 10,
-+	GSCAN_ATTRIBUTE_BASE_PERIOD,
-+	GSCAN_ATTRIBUTE_BUCKETS_BAND,
-+	GSCAN_ATTRIBUTE_BUCKET_ID,
-+	GSCAN_ATTRIBUTE_BUCKET_PERIOD,
-+	GSCAN_ATTRIBUTE_BUCKET_NUM_CHANNELS,
-+	GSCAN_ATTRIBUTE_BUCKET_CHANNELS,
-+	GSCAN_ATTRIBUTE_NUM_AP_PER_SCAN,
-+	GSCAN_ATTRIBUTE_REPORT_THRESHOLD,
-+	GSCAN_ATTRIBUTE_NUM_SCANS_TO_CACHE,
-+	GSCAN_ATTRIBUTE_BAND = GSCAN_ATTRIBUTE_BUCKETS_BAND,
-+
-+	GSCAN_ATTRIBUTE_ENABLE_FEATURE = 20,
-+	GSCAN_ATTRIBUTE_SCAN_RESULTS_COMPLETE,
-+	GSCAN_ATTRIBUTE_FLUSH_FEATURE,
-+	GSCAN_ATTRIBUTE_ENABLE_FULL_SCAN_RESULTS,
-+	GSCAN_ATTRIBUTE_REPORT_EVENTS,
-+	/* remaining reserved for additional attributes */
-+	GSCAN_ATTRIBUTE_NUM_OF_RESULTS = 30,
-+	GSCAN_ATTRIBUTE_FLUSH_RESULTS,
-+	GSCAN_ATTRIBUTE_SCAN_RESULTS,                       /* flat array of wifi_scan_result */
-+	GSCAN_ATTRIBUTE_SCAN_ID,                            /* indicates scan number */
-+	GSCAN_ATTRIBUTE_SCAN_FLAGS,                         /* indicates if scan was aborted */
-+	GSCAN_ATTRIBUTE_AP_FLAGS,                           /* flags on significant change event */
-+	GSCAN_ATTRIBUTE_NUM_CHANNELS,
-+	GSCAN_ATTRIBUTE_CHANNEL_LIST,
-+
-+	/* remaining reserved for additional attributes */
-+
-+	GSCAN_ATTRIBUTE_SSID = 40,
-+	GSCAN_ATTRIBUTE_BSSID,
-+	GSCAN_ATTRIBUTE_CHANNEL,
-+	GSCAN_ATTRIBUTE_RSSI,
-+	GSCAN_ATTRIBUTE_TIMESTAMP,
-+	GSCAN_ATTRIBUTE_RTT,
-+	GSCAN_ATTRIBUTE_RTTSD,
-+
-+	/* remaining reserved for additional attributes */
-+
-+	GSCAN_ATTRIBUTE_HOTLIST_BSSIDS = 50,
-+	GSCAN_ATTRIBUTE_RSSI_LOW,
-+	GSCAN_ATTRIBUTE_RSSI_HIGH,
-+	GSCAN_ATTRIBUTE_HOSTLIST_BSSID_ELEM,
-+	GSCAN_ATTRIBUTE_HOTLIST_FLUSH,
-+
-+	/* remaining reserved for additional attributes */
-+	GSCAN_ATTRIBUTE_RSSI_SAMPLE_SIZE = 60,
-+	GSCAN_ATTRIBUTE_LOST_AP_SAMPLE_SIZE,
-+	GSCAN_ATTRIBUTE_MIN_BREACHING,
-+	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_BSSIDS,
-+	GSCAN_ATTRIBUTE_SIGNIFICANT_CHANGE_FLUSH,
-+	GSCAN_ATTRIBUTE_MAX
-+};
-+
-+enum gscan_bucket_attributes {
-+	GSCAN_ATTRIBUTE_CH_BUCKET_1,
-+	GSCAN_ATTRIBUTE_CH_BUCKET_2,
-+	GSCAN_ATTRIBUTE_CH_BUCKET_3,
-+	GSCAN_ATTRIBUTE_CH_BUCKET_4,
-+	GSCAN_ATTRIBUTE_CH_BUCKET_5,
-+	GSCAN_ATTRIBUTE_CH_BUCKET_6,
-+	GSCAN_ATTRIBUTE_CH_BUCKET_7
-+};
-+
-+enum gscan_ch_attributes {
-+	GSCAN_ATTRIBUTE_CH_ID_1,
-+	GSCAN_ATTRIBUTE_CH_ID_2,
-+	GSCAN_ATTRIBUTE_CH_ID_3,
-+	GSCAN_ATTRIBUTE_CH_ID_4,
-+	GSCAN_ATTRIBUTE_CH_ID_5,
-+	GSCAN_ATTRIBUTE_CH_ID_6,
-+	GSCAN_ATTRIBUTE_CH_ID_7
-+};
-+
-+enum wifi_rssi_monitor_attr {
-+        RSSI_MONITOR_ATTRIBUTE_MAX_RSSI,
-+        RSSI_MONITOR_ATTRIBUTE_MIN_RSSI,
-+        RSSI_MONITOR_ATTRIBUTE_START,
-+};
-+
-+
-+enum rtt_attributes {
-+	RTT_ATTRIBUTE_TARGET_CNT,
-+	RTT_ATTRIBUTE_TARGET_INFO,
-+	RTT_ATTRIBUTE_TARGET_MAC,
-+	RTT_ATTRIBUTE_TARGET_TYPE,
-+	RTT_ATTRIBUTE_TARGET_PEER,
-+	RTT_ATTRIBUTE_TARGET_CHAN,
-+	RTT_ATTRIBUTE_TARGET_MODE,
-+	RTT_ATTRIBUTE_TARGET_INTERVAL,
-+	RTT_ATTRIBUTE_TARGET_NUM_MEASUREMENT,
-+	RTT_ATTRIBUTE_TARGET_NUM_PKT,
-+	RTT_ATTRIBUTE_TARGET_NUM_RETRY
-+};
-+
-+enum logger_attributes {
-+	LOGGER_ATTRIBUTE_GET_DRIVER,
-+	LOGGER_ATTRIBUTE_GET_FW,
-+	LOGGER_ATTRIBUTE_RING_ID,
-+	LOGGER_ATTRIBUTE_RING_NAME,
-+	LOGGER_ATTRIBUTE_RING_FLAGS,
-+	LOGGER_ATTRIBUTE_LOG_LEVEL,
-+	LOGGER_ATTRIBUTE_LOG_TIME_INTVAL,
-+	LOGGER_ATTRIBUTE_LOG_MIN_DATA_SIZE,
-+	LOGGER_ATTRIBUTE_FW_DUMP_LEN,
-+	LOGGER_ATTRIBUTE_FW_DUMP_DATA,
-+	LOGGERG_ATTRIBUTE_RING_DATA,
-+	LOGGER_ATTRIBUTE_RING_STATUS,
-+	LOGGER_ATTRIBUTE_RING_NUM
-+};
-+typedef enum rtw_vendor_event {
-+    RTK_RESERVED1,
-+    RTK_RESERVED2,
-+    GSCAN_EVENT_SIGNIFICANT_CHANGE_RESULTS ,
-+    GSCAN_EVENT_HOTLIST_RESULTS_FOUND,
-+    GSCAN_EVENT_SCAN_RESULTS_AVAILABLE,
-+    GSCAN_EVENT_FULL_SCAN_RESULTS,
-+    RTT_EVENT_COMPLETE,
-+    GSCAN_EVENT_COMPLETE_SCAN,
-+    GSCAN_EVENT_HOTLIST_RESULTS_LOST,
-+    GSCAN_EVENT_EPNO_EVENT,
-+    GOOGLE_DEBUG_RING_EVENT,
-+    GOOGLE_DEBUG_MEM_DUMP_EVENT,
-+    GSCAN_EVENT_ANQPO_HOTSPOT_MATCH,
-+    GOOGLE_RSSI_MONITOR_EVENT
-+} rtw_vendor_event_t;
-+
-+enum andr_wifi_feature_set_attr {
-+	ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET,
-+	ANDR_WIFI_ATTRIBUTE_FEATURE_SET,
-+	ANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI,
-+	ANDR_WIFI_ATTRIBUTE_NODFS_SET,
-+	ANDR_WIFI_ATTRIBUTE_COUNTRY,
-+	ANDR_WIFI_ATTRIBUTE_ND_OFFLOAD_VALUE
-+	// Add more attribute here
-+};
-+
-+typedef enum rtw_vendor_gscan_attribute {
-+	ATTR_START_GSCAN,
-+	ATTR_STOP_GSCAN,
-+	ATTR_SET_SCAN_BATCH_CFG_ID, /* set batch scan params */
-+	ATTR_SET_SCAN_GEOFENCE_CFG_ID, /* set list of bssids to track */
-+	ATTR_SET_SCAN_SIGNIFICANT_CFG_ID, /* set list of bssids, rssi threshold etc.. */
-+	ATTR_SET_SCAN_CFG_ID, /* set common scan config params here */
-+	ATTR_GET_GSCAN_CAPABILITIES_ID,
-+	/* Add more sub commands here */
-+	ATTR_GSCAN_MAX
-+} rtw_vendor_gscan_attribute_t;
-+
-+typedef enum gscan_batch_attribute {
-+	ATTR_GSCAN_BATCH_BESTN,
-+	ATTR_GSCAN_BATCH_MSCAN,
-+	ATTR_GSCAN_BATCH_BUFFER_THRESHOLD
-+} gscan_batch_attribute_t;
-+
-+typedef enum gscan_geofence_attribute {
-+	ATTR_GSCAN_NUM_HOTLIST_BSSID,
-+	ATTR_GSCAN_HOTLIST_BSSID
-+} gscan_geofence_attribute_t;
-+
-+typedef enum gscan_complete_event {
-+	WIFI_SCAN_BUFFER_FULL,
-+	WIFI_SCAN_COMPLETE
-+} gscan_complete_event_t;
-+/* wifi_hal.h */
-+/* WiFi Common definitions */
-+typedef unsigned char byte;
-+typedef int wifi_request_id;
-+typedef int wifi_channel;                       // indicates channel frequency in MHz
-+typedef int wifi_rssi;
-+typedef byte mac_addr[6];
-+typedef byte oui[3];
-+typedef int64_t wifi_timestamp;                 // In microseconds (us)
-+typedef int64_t wifi_timespan;                  // In picoseconds  (ps)
-+
-+struct wifi_info;
-+struct wifi_interface_info;
-+typedef struct wifi_info *wifi_handle;
-+typedef struct wifi_interface_info *wifi_interface_handle;
-+
-+/* channel operating width */
-+typedef enum {
-+    WIFI_CHAN_WIDTH_20    = 0,
-+    WIFI_CHAN_WIDTH_40    = 1,
-+    WIFI_CHAN_WIDTH_80    = 2,
-+    WIFI_CHAN_WIDTH_160   = 3,
-+    WIFI_CHAN_WIDTH_80P80 = 4,
-+    WIFI_CHAN_WIDTH_5     = 5,
-+    WIFI_CHAN_WIDTH_10    = 6,
-+    WIFI_CHAN_WIDTH_INVALID = -1
-+} wifi_channel_width;
-+
-+typedef int wifi_radio;
-+
-+typedef struct {
-+    wifi_channel_width width;
-+    int center_frequency0;
-+    int center_frequency1;
-+    int primary_frequency;
-+} wifi_channel_spec;
-+
-+typedef enum {
-+    WIFI_SUCCESS = 0,
-+    WIFI_ERROR_NONE = 0,
-+    WIFI_ERROR_UNKNOWN = -1,
-+    WIFI_ERROR_UNINITIALIZED = -2,
-+    WIFI_ERROR_NOT_SUPPORTED = -3,
-+    WIFI_ERROR_NOT_AVAILABLE = -4,              // Not available right now, but try later
-+    WIFI_ERROR_INVALID_ARGS = -5,
-+    WIFI_ERROR_INVALID_REQUEST_ID = -6,
-+    WIFI_ERROR_TIMED_OUT = -7,
-+    WIFI_ERROR_TOO_MANY_REQUESTS = -8,          // Too many instances of this request
-+    WIFI_ERROR_OUT_OF_MEMORY = -9,
-+    WIFI_ERROR_BUSY = -10,
-+} wifi_error;
-+
-+typedef int wifi_ring_buffer_id;
-+/* ring buffer params */
-+/**
-+ * written_bytes and read_bytes implement a producer consumer API
-+ *     hence written_bytes >= read_bytes
-+ * a modulo arithmetic of the buffer size has to be applied to those counters:
-+ * actual offset into ring buffer = written_bytes % ring_buffer_byte_size
-+ *
-+ */
-+typedef struct {
-+    u8 name[32];
-+    u32 flags;
-+    wifi_ring_buffer_id ring_id; // unique integer representing the ring
-+    u32 ring_buffer_byte_size;   // total memory size allocated for the buffer
-+    u32 verbose_level;           // verbose level for ring buffer
-+    u32 written_bytes;           // number of bytes that was written to the buffer by driver,
-+                                 // monotonously increasing integer
-+    u32 read_bytes;              // number of bytes that was read from the buffer by user land,
-+                                 // monotonously increasing integer
-+    u32 written_records;         // number of records that was written to the buffer by driver,
-+                                 // monotonously increasing integer
-+} wifi_ring_buffer_status;
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
-+#define STATS_MAJOR_VERSION      1
-+#define STATS_MINOR_VERSION      0
-+#define STATS_MICRO_VERSION      0
-+
-+typedef enum {
-+    WIFI_DISCONNECTED = 0,
-+    WIFI_AUTHENTICATING = 1,
-+    WIFI_ASSOCIATING = 2,
-+    WIFI_ASSOCIATED = 3,
-+    WIFI_EAPOL_STARTED = 4,   // if done by firmware/driver
-+    WIFI_EAPOL_COMPLETED = 5, // if done by firmware/driver
-+} wifi_connection_state;
-+
-+typedef enum {
-+    WIFI_ROAMING_IDLE = 0,
-+    WIFI_ROAMING_ACTIVE = 1,
-+} wifi_roam_state;
-+
-+typedef enum {
-+    WIFI_INTERFACE_STA = 0,
-+    WIFI_INTERFACE_SOFTAP = 1,
-+    WIFI_INTERFACE_IBSS = 2,
-+    WIFI_INTERFACE_P2P_CLIENT = 3,
-+    WIFI_INTERFACE_P2P_GO = 4,
-+    WIFI_INTERFACE_NAN = 5,
-+    WIFI_INTERFACE_MESH = 6,
-+    WIFI_INTERFACE_UNKNOWN = -1
-+ } wifi_interface_mode;
-+
-+#define WIFI_CAPABILITY_QOS          0x00000001     // set for QOS association
-+#define WIFI_CAPABILITY_PROTECTED    0x00000002     // set for protected association (802.11 beacon frame control protected bit set)
-+#define WIFI_CAPABILITY_INTERWORKING 0x00000004     // set if 802.11 Extended Capabilities element interworking bit is set
-+#define WIFI_CAPABILITY_HS20         0x00000008     // set for HS20 association
-+#define WIFI_CAPABILITY_SSID_UTF8    0x00000010     // set is 802.11 Extended Capabilities element UTF-8 SSID bit is set
-+#define WIFI_CAPABILITY_COUNTRY      0x00000020     // set is 802.11 Country Element is present
-+
-+typedef struct {
-+   wifi_interface_mode mode;     // interface mode
-+   u8 mac_addr[6];               // interface mac address (self)
-+   wifi_connection_state state;  // connection state (valid for STA, CLI only)
-+   wifi_roam_state roaming;      // roaming state
-+   u32 capabilities;             // WIFI_CAPABILITY_XXX (self)
-+   u8 ssid[33];                  // null terminated SSID
-+   u8 bssid[6];                  // bssid
-+   u8 ap_country_str[3];         // country string advertised by AP
-+   u8 country_str[3];            // country string for this association
-+} wifi_interface_link_layer_info;
-+
-+/* channel information */
-+typedef struct {
-+   wifi_channel_width width;   // channel width (20, 40, 80, 80+80, 160)
-+   wifi_channel center_freq;   // primary 20 MHz channel
-+   wifi_channel center_freq0;  // center frequency (MHz) first segment
-+   wifi_channel center_freq1;  // center frequency (MHz) second segment
-+} wifi_channel_info;
-+
-+/* wifi rate */
-+typedef struct {
-+   u32 preamble   :3;   // 0: OFDM, 1:CCK, 2:HT 3:VHT 4..7 reserved
-+   u32 nss        :2;   // 0:1x1, 1:2x2, 3:3x3, 4:4x4
-+   u32 bw         :3;   // 0:20MHz, 1:40Mhz, 2:80Mhz, 3:160Mhz
-+   u32 rateMcsIdx :8;   // OFDM/CCK rate code would be as per ieee std in the units of 0.5mbps
-+                        // HT/VHT it would be mcs index
-+   u32 reserved  :16;   // reserved
-+   u32 bitrate;         // units of 100 Kbps
-+} wifi_rate;
-+
-+/* channel statistics */
-+typedef struct {
-+   wifi_channel_info channel;  // channel
-+   u32 on_time;                // msecs the radio is awake (32 bits number accruing over time)
-+   u32 cca_busy_time;          // msecs the CCA register is busy (32 bits number accruing over time)
-+} wifi_channel_stat;
-+
-+// Max number of tx power levels. The actual number vary per device and is specified by |num_tx_levels|
-+#define RADIO_STAT_MAX_TX_LEVELS 256
-+
-+/* Internal radio statistics structure in the driver */
-+typedef struct {
-+   wifi_radio radio;                      // wifi radio (if multiple radio supported)
-+   u32 on_time;                           // msecs the radio is awake (32 bits number accruing over time)
-+   u32 tx_time;                           // msecs the radio is transmitting (32 bits number accruing over time)
-+   u32 rx_time;                           // msecs the radio is in active receive (32 bits number accruing over time)
-+   u32 on_time_scan;                      // msecs the radio is awake due to all scan (32 bits number accruing over time)
-+   u32 on_time_nbd;                       // msecs the radio is awake due to NAN (32 bits number accruing over time)
-+   u32 on_time_gscan;                     // msecs the radio is awake due to G?scan (32 bits number accruing over time)
-+   u32 on_time_roam_scan;                 // msecs the radio is awake due to roam?scan (32 bits number accruing over time)
-+   u32 on_time_pno_scan;                  // msecs the radio is awake due to PNO scan (32 bits number accruing over time)
-+   u32 on_time_hs20;                      // msecs the radio is awake due to HS2.0 scans and GAS exchange (32 bits number accruing over time)
-+   u32 num_channels;                      // number of channels
-+   wifi_channel_stat channels[];          // channel statistics
-+} wifi_radio_stat_internal;
-+
-+/**
-+ * Packet statistics reporting by firmware is performed on MPDU basi (i.e. counters increase by 1 for each MPDU)
-+ * As well, "data packet" in associated comments, shall be interpreted as 802.11 data packet,
-+ * that is, 802.11 frame control subtype == 2 and excluding management and control frames.
-+ *
-+ * As an example, in the case of transmission of an MSDU fragmented in 16 MPDUs which are transmitted
-+ * OTA in a 16 units long a-mpdu, for which a block ack is received with 5 bits set:
-+ *          tx_mpdu : shall increase by 5
-+ *          retries : shall increase by 16
-+ *          tx_ampdu : shall increase by 1
-+ * data packet counters shall not increase regardless of the number of BAR potentially sent by device for this a-mpdu
-+ * data packet counters shall not increase regardless of the number of BA received by device for this a-mpdu
-+ *
-+ * For each subsequent retransmission of the 11 remaining non ACK'ed mpdus
-+ * (regardless of the fact that they are transmitted in a-mpdu or not)
-+ *          retries : shall increase by 1
-+ *
-+ * If no subsequent BA or ACK are received from AP, until packet lifetime expires for those 11 packet that were not ACK'ed
-+ *          mpdu_lost : shall increase by 11
-+ */
-+
-+/* per rate statistics */
-+typedef struct {
-+   wifi_rate rate;     // rate information
-+   u32 tx_mpdu;        // number of successfully transmitted data pkts (ACK rcvd)
-+   u32 rx_mpdu;        // number of received data pkts
-+   u32 mpdu_lost;      // number of data packet losses (no ACK)
-+   u32 retries;        // total number of data pkt retries
-+   u32 retries_short;  // number of short data pkt retries
-+   u32 retries_long;   // number of long data pkt retries
-+} wifi_rate_stat;
-+
-+/* access categories */
-+typedef enum {
-+   WIFI_AC_VO  = 0,
-+   WIFI_AC_VI  = 1,
-+   WIFI_AC_BE  = 2,
-+   WIFI_AC_BK  = 3,
-+   WIFI_AC_MAX = 4,
-+} wifi_traffic_ac;
-+
-+/* wifi peer type */
-+typedef enum
-+{
-+   WIFI_PEER_STA,
-+   WIFI_PEER_AP,
-+   WIFI_PEER_P2P_GO,
-+   WIFI_PEER_P2P_CLIENT,
-+   WIFI_PEER_NAN,
-+   WIFI_PEER_TDLS,
-+   WIFI_PEER_INVALID,
-+} wifi_peer_type;
-+
-+/* per peer statistics */
-+typedef struct {
-+   wifi_peer_type type;           // peer type (AP, TDLS, GO etc.)
-+   u8 peer_mac_address[6];        // mac address
-+   u32 capabilities;              // peer WIFI_CAPABILITY_XXX
-+   u32 num_rate;                  // number of rates
-+   wifi_rate_stat rate_stats[];   // per rate statistics, number of entries  = num_rate
-+} wifi_peer_info;
-+
-+/* Per access category statistics */
-+typedef struct {
-+   wifi_traffic_ac ac;             // access category (VI, VO, BE, BK)
-+   u32 tx_mpdu;                    // number of successfully transmitted unicast data pkts (ACK rcvd)
-+   u32 rx_mpdu;                    // number of received unicast data packets
-+   u32 tx_mcast;                   // number of succesfully transmitted multicast data packets
-+                                   // STA case: implies ACK received from AP for the unicast packet in which mcast pkt was sent
-+   u32 rx_mcast;                   // number of received multicast data packets
-+   u32 rx_ampdu;                   // number of received unicast a-mpdus; support of this counter is optional
-+   u32 tx_ampdu;                   // number of transmitted unicast a-mpdus; support of this counter is optional
-+   u32 mpdu_lost;                  // number of data pkt losses (no ACK)
-+   u32 retries;                    // total number of data pkt retries
-+   u32 retries_short;              // number of short data pkt retries
-+   u32 retries_long;               // number of long data pkt retries
-+   u32 contention_time_min;        // data pkt min contention time (usecs)
-+   u32 contention_time_max;        // data pkt max contention time (usecs)
-+   u32 contention_time_avg;        // data pkt avg contention time (usecs)
-+   u32 contention_num_samples;     // num of data pkts used for contention statistics
-+} wifi_wmm_ac_stat;
-+
-+/* interface statistics */
-+typedef struct {
-+   wifi_interface_handle iface;          // wifi interface
-+   wifi_interface_link_layer_info info;  // current state of the interface
-+   u32 beacon_rx;                        // access point beacon received count from connected AP
-+   u64 average_tsf_offset;               // average beacon offset encountered (beacon_TSF - TBTT)
-+                                         // The average_tsf_offset field is used so as to calculate the
-+                                         // typical beacon contention time on the channel as well may be
-+                                         // used to debug beacon synchronization and related power consumption issue
-+   u32 leaky_ap_detected;                // indicate that this AP typically leaks packets beyond the driver guard time.
-+   u32 leaky_ap_avg_num_frames_leaked;  // average number of frame leaked by AP after frame with PM bit set was ACK'ed by AP
-+   u32 leaky_ap_guard_time;              // guard time currently in force (when implementing IEEE power management based on
-+                                         // frame control PM bit), How long driver waits before shutting down the radio and
-+                                         // after receiving an ACK for a data frame with PM bit set)
-+   u32 mgmt_rx;                          // access point mgmt frames received count from connected AP (including Beacon)
-+   u32 mgmt_action_rx;                   // action frames received count
-+   u32 mgmt_action_tx;                   // action frames transmit count
-+   wifi_rssi rssi_mgmt;                  // access Point Beacon and Management frames RSSI (averaged)
-+   wifi_rssi rssi_data;                  // access Point Data Frames RSSI (averaged) from connected AP
-+   wifi_rssi rssi_ack;                   // access Point ACK RSSI (averaged) from connected AP
-+   wifi_wmm_ac_stat ac[WIFI_AC_MAX];     // per ac data packet statistics
-+   u32 num_peers;                        // number of peers
-+   wifi_peer_info peer_info[];           // per peer statistics
-+} wifi_iface_stat;
-+
-+/* configuration params */
-+typedef struct {
-+   u32 mpdu_size_threshold;             // threshold to classify the pkts as short or long
-+                                        // packet size < mpdu_size_threshold => short
-+   u32 aggressive_statistics_gathering; // set for field debug mode. Driver should collect all statistics regardless of performance impact.
-+} wifi_link_layer_params;
-+
-+#define RSSI_MONITOR_EVT_VERSION   1
-+typedef struct {
-+    u8 version;
-+    s8 cur_rssi;
-+    mac_addr BSSID;
-+} rssi_monitor_evt;
-+
-+
-+/* wifi statistics bitmap  */
-+#define WIFI_STATS_RADIO              0x00000001      // all radio statistics
-+#define WIFI_STATS_RADIO_CCA          0x00000002      // cca_busy_time (within radio statistics)
-+#define WIFI_STATS_RADIO_CHANNELS     0x00000004      // all channel statistics (within radio statistics)
-+#define WIFI_STATS_RADIO_SCAN         0x00000008      // all scan statistics (within radio statistics)
-+#define WIFI_STATS_IFACE              0x00000010      // all interface statistics
-+#define WIFI_STATS_IFACE_TXRATE       0x00000020      // all tx rate statistics (within interface statistics)
-+#define WIFI_STATS_IFACE_AC           0x00000040      // all ac statistics (within interface statistics)
-+#define WIFI_STATS_IFACE_CONTENTION   0x00000080      // all contention (min, max, avg) statistics (within ac statisctics)
-+
-+#endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
-+
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT)
-+extern int rtw_cfgvendor_attach(struct wiphy *wiphy);
-+extern int rtw_cfgvendor_detach(struct wiphy *wiphy);
-+extern int rtw_cfgvendor_send_async_event(struct wiphy *wiphy,
-+	struct net_device *dev, int event_id, const void  *data, int len);
-+#if defined(GSCAN_SUPPORT) && 0
-+extern int rtw_cfgvendor_send_hotlist_event(struct wiphy *wiphy,
-+	struct net_device *dev, void  *data, int len, rtw_vendor_event_t event);
-+#endif
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
-+void rtw_cfgvendor_rssi_monitor_evt(_adapter *padapter);
-+#endif
-+
-+#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
-+void rtw_hal_pno_random_gen_mac_addr(PADAPTER adapter);
-+void rtw_hal_set_hw_mac_addr(PADAPTER adapter, u8 *mac_addr);
-+#endif
-+
-+
-+#endif /* _RTW_CFGVENDOR_H_ */
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/rtw_proc.c b/drivers/staging/rtl8723cs/os_dep/linux/rtw_proc.c
-new file mode 100644
-index 000000000000..bfe65dbbc4f9
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/rtw_proc.c
-@@ -0,0 +1,6233 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <linux/ctype.h>	/* tolower() */
-+#include <drv_types.h>
-+#include <hal_data.h>
-+#include "rtw_proc.h"
-+#include <rtw_btcoex.h>
-+
-+#ifdef CONFIG_PROC_DEBUG
-+
-+static struct proc_dir_entry *rtw_proc = NULL;
-+
-+inline struct proc_dir_entry *get_rtw_drv_proc(void)
-+{
-+	return rtw_proc;
-+}
-+
-+#define RTW_PROC_NAME DRV_NAME
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
-+#define file_inode(file) ((file)->f_dentry->d_inode)
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
-+#define PDE_DATA(inode) PDE((inode))->data
-+#define proc_get_parent_data(inode) PDE((inode))->parent->data
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
-+#define get_proc_net proc_net
-+#else
-+#define get_proc_net init_net.proc_net
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0))
-+int single_open_size(struct file *file, int (*show)(struct seq_file *, void *),
-+		void *data, size_t size)
-+{
-+	char *buf = kmalloc(size, GFP_KERNEL);
-+	int ret;
-+	if (!buf)
-+		return -ENOMEM;
-+	ret = single_open(file, show, data);
-+	if (ret) {
-+		kfree(buf);
-+		return ret;
-+	}
-+	((struct seq_file *)file->private_data)->buf = buf;
-+	((struct seq_file *)file->private_data)->size = size;
-+	return 0;
-+}
-+#endif
-+
-+inline struct proc_dir_entry *rtw_proc_create_dir(const char *name, struct proc_dir_entry *parent, void *data)
-+{
-+	struct proc_dir_entry *entry;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0))
-+	entry = proc_mkdir_data(name, S_IRUGO | S_IXUGO, parent, data);
-+#else
-+	/* entry = proc_mkdir_mode(name, S_IRUGO|S_IXUGO, parent); */
-+	entry = proc_mkdir(name, parent);
-+	if (entry)
-+		entry->data = data;
-+#endif
-+
-+	return entry;
-+}
-+
-+inline struct proc_dir_entry *rtw_proc_create_entry(const char *name, struct proc_dir_entry *parent,
-+	const struct rtw_proc_ops *fops, void * data)
-+{
-+	struct proc_dir_entry *entry;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26))
-+	entry = proc_create_data(name,  S_IFREG | S_IRUGO | S_IWUGO, parent, fops, data);
-+#else
-+	entry = create_proc_entry(name, S_IFREG | S_IRUGO | S_IWUGO, parent);
-+	if (entry) {
-+		entry->data = data;
-+		entry->proc_fops = fops;
-+	}
-+#endif
-+
-+	return entry;
-+}
-+
-+static int proc_get_dummy(struct seq_file *m, void *v)
-+{
-+	return 0;
-+}
-+
-+static int proc_get_drv_version(struct seq_file *m, void *v)
-+{
-+	dump_drv_version(m);
-+	return 0;
-+}
-+
-+static int proc_get_log_level(struct seq_file *m, void *v)
-+{
-+	dump_log_level(m);
-+	return 0;
-+}
-+
-+static int proc_get_drv_cfg(struct seq_file *m, void *v)
-+{
-+	dump_drv_cfg(m);
-+	return 0;
-+}
-+
-+static ssize_t proc_set_log_level(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	char tmp[32];
-+	int log_level;
-+
-+	if (count < 1)
-+		return -EINVAL;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+#ifdef CONFIG_RTW_DEBUG
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d ", &log_level);
-+
-+		if (num == 1 &&
-+		    log_level >= _DRV_NONE_ && log_level <= _DRV_MAX_) {
-+			rtw_drv_log_level = log_level;
-+			printk("rtw_drv_log_level:%d\n", rtw_drv_log_level);
-+		}
-+	} else
-+		return -EFAULT;
-+#else
-+	printk("CONFIG_RTW_DEBUG is disabled\n");
-+#endif
-+
-+	return count;
-+}
-+
-+#ifdef DBG_MEM_ALLOC
-+static int proc_get_mstat(struct seq_file *m, void *v)
-+{
-+	rtw_mstat_dump(m);
-+	return 0;
-+}
-+#endif /* DBG_MEM_ALLOC */
-+
-+static int proc_get_country_chplan_map(struct seq_file *m, void *v)
-+{
-+	dump_country_chplan_map(m);
-+	return 0;
-+}
-+
-+static int proc_get_chplan_id_list(struct seq_file *m, void *v)
-+{
-+	dump_chplan_id_list(m);
-+	return 0;
-+}
-+
-+#ifdef CONFIG_RTW_DEBUG
-+static int proc_get_chplan_test(struct seq_file *m, void *v)
-+{
-+	dump_chplan_test(m);
-+	return 0;
-+}
-+#endif
-+
-+static int proc_get_chplan_ver(struct seq_file *m, void *v)
-+{
-+	dump_chplan_ver(m);
-+	return 0;
-+}
-+
-+static int proc_get_global_op_class(struct seq_file *m, void *v)
-+{
-+	dump_global_op_class(m);
-+	return 0;
-+}
-+
-+#ifdef CONFIG_RTW_DEBUG
-+static int proc_get_hw_rate_map_test(struct seq_file *m, void *v)
-+{
-+	dump_hw_rate_map_test(m);
-+	return 0;
-+}
-+#endif
-+
-+#ifdef RTW_HALMAC
-+extern void rtw_halmac_get_version(char *str, u32 len);
-+
-+static int proc_get_halmac_info(struct seq_file *m, void *v)
-+{
-+	char ver[30] = {0};
-+
-+
-+	rtw_halmac_get_version(ver, 30);
-+	RTW_PRINT_SEL(m, "version: %s\n", ver);
-+
-+	return 0;
-+}
-+#endif
-+
-+/*
-+* rtw_drv_proc:
-+* init/deinit when register/unregister driver
-+*/
-+const struct rtw_proc_hdl drv_proc_hdls[] = {
-+	RTW_PROC_HDL_SSEQ("ver_info", proc_get_drv_version, NULL),
-+	RTW_PROC_HDL_SSEQ("log_level", proc_get_log_level, proc_set_log_level),
-+	RTW_PROC_HDL_SSEQ("drv_cfg", proc_get_drv_cfg, NULL),
-+#ifdef DBG_MEM_ALLOC
-+	RTW_PROC_HDL_SSEQ("mstat", proc_get_mstat, NULL),
-+#endif /* DBG_MEM_ALLOC */
-+	RTW_PROC_HDL_SSEQ("country_chplan_map", proc_get_country_chplan_map, NULL),
-+	RTW_PROC_HDL_SSEQ("chplan_id_list", proc_get_chplan_id_list, NULL),
-+#ifdef CONFIG_RTW_DEBUG
-+	RTW_PROC_HDL_SSEQ("chplan_test", proc_get_chplan_test, NULL),
-+#endif
-+	RTW_PROC_HDL_SSEQ("chplan_ver", proc_get_chplan_ver, NULL),
-+	RTW_PROC_HDL_SSEQ("global_op_class", proc_get_global_op_class, NULL),
-+#ifdef CONFIG_RTW_DEBUG
-+	RTW_PROC_HDL_SSEQ("hw_rate_map_test", proc_get_hw_rate_map_test, NULL),
-+#endif
-+#ifdef RTW_HALMAC
-+	RTW_PROC_HDL_SSEQ("halmac_info", proc_get_halmac_info, NULL),
-+#endif /* RTW_HALMAC */
-+};
-+
-+const int drv_proc_hdls_num = sizeof(drv_proc_hdls) / sizeof(struct rtw_proc_hdl);
-+
-+static int rtw_drv_proc_open(struct inode *inode, struct file *file)
-+{
-+	/* struct net_device *dev = proc_get_parent_data(inode); */
-+	ssize_t index = (ssize_t)PDE_DATA(inode);
-+	const struct rtw_proc_hdl *hdl = drv_proc_hdls + index;
-+	void *private = NULL;
-+
-+	if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
-+		int res = seq_open(file, hdl->u.seq_op);
-+
-+		if (res == 0)
-+			((struct seq_file *)file->private_data)->private = private;
-+
-+		return res;
-+	} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
-+		int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
-+
-+		return single_open(file, show, private);
-+	} else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) {
-+		int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy;
-+
-+		return single_open_size(file, show, private, hdl->u.sz.size);
-+	} else {
-+		return -EROFS;
-+	}
-+}
-+
-+static ssize_t rtw_drv_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
-+{
-+	ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
-+	const struct rtw_proc_hdl *hdl = drv_proc_hdls + index;
-+	ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
-+
-+	if (write)
-+		return write(file, buffer, count, pos, NULL);
-+
-+	return -EROFS;
-+}
-+
-+static const struct rtw_proc_ops rtw_drv_proc_seq_fops = {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
-+	.proc_open = rtw_drv_proc_open,
-+	.proc_read = seq_read,
-+	.proc_lseek = seq_lseek,
-+	.proc_release = seq_release,
-+	.proc_write = rtw_drv_proc_write,
-+#else
-+	.owner = THIS_MODULE,
-+	.open = rtw_drv_proc_open,
-+	.read = seq_read,
-+	.llseek = seq_lseek,
-+	.release = seq_release,
-+	.write = rtw_drv_proc_write,
-+#endif
-+};
-+
-+static const struct rtw_proc_ops rtw_drv_proc_sseq_fops = {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
-+	.proc_open = rtw_drv_proc_open,
-+	.proc_read = seq_read,
-+	.proc_lseek = seq_lseek,
-+	.proc_release = single_release,
-+	.proc_write = rtw_drv_proc_write,
-+#else
-+	.owner = THIS_MODULE,
-+	.open = rtw_drv_proc_open,
-+	.read = seq_read,
-+	.llseek = seq_lseek,
-+	.release = single_release,
-+	.write = rtw_drv_proc_write,
-+#endif
-+};
-+
-+int rtw_drv_proc_init(void)
-+{
-+	int ret = _FAIL;
-+	ssize_t i;
-+	struct proc_dir_entry *entry = NULL;
-+
-+	if (rtw_proc != NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	rtw_proc = rtw_proc_create_dir(RTW_PROC_NAME, get_proc_net, NULL);
-+
-+	if (rtw_proc == NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	for (i = 0; i < drv_proc_hdls_num; i++) {
-+		if (drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
-+			entry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_seq_fops, (void *)i);
-+		else if (drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ ||
-+			 drv_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SZSEQ)
-+			entry = rtw_proc_create_entry(drv_proc_hdls[i].name, rtw_proc, &rtw_drv_proc_sseq_fops, (void *)i);
-+		else
-+			entry = NULL;
-+
-+		if (!entry) {
-+			rtw_warn_on(1);
-+			goto exit;
-+		}
-+	}
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+void rtw_drv_proc_deinit(void)
-+{
-+	int i;
-+
-+	if (rtw_proc == NULL)
-+		return;
-+
-+	for (i = 0; i < drv_proc_hdls_num; i++)
-+		remove_proc_entry(drv_proc_hdls[i].name, rtw_proc);
-+
-+	remove_proc_entry(RTW_PROC_NAME, get_proc_net);
-+	rtw_proc = NULL;
-+}
-+
-+#ifndef RTW_SEQ_FILE_TEST
-+#define RTW_SEQ_FILE_TEST 0
-+#endif
-+
-+#if RTW_SEQ_FILE_TEST
-+#define RTW_SEQ_FILE_TEST_SHOW_LIMIT 300
-+static void *proc_start_seq_file_test(struct seq_file *m, loff_t *pos)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
-+	if (*pos >= RTW_SEQ_FILE_TEST_SHOW_LIMIT) {
-+		RTW_PRINT(FUNC_ADPT_FMT" pos:%llu, out of range return\n", FUNC_ADPT_ARG(adapter), *pos);
-+		return NULL;
-+	}
-+
-+	RTW_PRINT(FUNC_ADPT_FMT" return pos:%lld\n", FUNC_ADPT_ARG(adapter), *pos);
-+	return pos;
-+}
-+void proc_stop_seq_file_test(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
-+}
-+
-+void *proc_next_seq_file_test(struct seq_file *m, void *v, loff_t *pos)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	(*pos)++;
-+	if (*pos >= RTW_SEQ_FILE_TEST_SHOW_LIMIT) {
-+		RTW_PRINT(FUNC_ADPT_FMT" pos:%lld, out of range return\n", FUNC_ADPT_ARG(adapter), *pos);
-+		return NULL;
-+	}
-+
-+	RTW_PRINT(FUNC_ADPT_FMT" return pos:%lld\n", FUNC_ADPT_ARG(adapter), *pos);
-+	return pos;
-+}
-+
-+static int proc_get_seq_file_test(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	u32 pos = *((loff_t *)(v));
-+	RTW_PRINT(FUNC_ADPT_FMT" pos:%d\n", FUNC_ADPT_ARG(adapter), pos);
-+	RTW_PRINT_SEL(m, FUNC_ADPT_FMT" pos:%d\n", FUNC_ADPT_ARG(adapter), pos);
-+	return 0;
-+}
-+
-+struct seq_operations seq_file_test = {
-+	.start = proc_start_seq_file_test,
-+	.stop  = proc_stop_seq_file_test,
-+	.next  = proc_next_seq_file_test,
-+	.show  = proc_get_seq_file_test,
-+};
-+#endif /* RTW_SEQ_FILE_TEST */
-+
-+#ifdef CONFIG_SDIO_HCI
-+static int proc_get_sd_f0_reg_dump(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	sd_f0_reg_dump(m, adapter);
-+
-+	return 0;
-+}
-+
-+static int proc_get_sdio_local_reg_dump(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	sdio_local_reg_dump(m, adapter);
-+
-+	return 0;
-+}
-+static int proc_get_sdio_card_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_sdio_card_info(m, adapter_to_dvobj(adapter));
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_SDIO_RECVBUF_AGGREGATION
-+int proc_get_sdio_recvbuf_aggregation(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = GET_PRIMARY_ADAPTER((_adapter *)rtw_netdev_priv(dev));
-+	struct recv_priv *recvpriv = &adapter->recvpriv;
-+
-+	RTW_PRINT_SEL(m, "%d\n", recvpriv->recvbuf_agg);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_sdio_recvbuf_aggregation(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = GET_PRIMARY_ADAPTER((_adapter *)rtw_netdev_priv(dev));
-+	struct recv_priv *recvpriv = &adapter->recvpriv;
-+
-+	char tmp[32];
-+	u8 enable;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu", &enable);
-+
-+		if (num >= 1)
-+			recvpriv->recvbuf_agg = enable ? 1 : 0;
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_SDIO_RECVBUF_AGGREGATION */
-+
-+#ifdef CONFIG_SDIO_RECVBUF_PWAIT
-+int proc_get_sdio_recvbuf_pwait(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = GET_PRIMARY_ADAPTER((_adapter *)rtw_netdev_priv(dev));
-+	struct recv_priv *recvpriv = &adapter->recvpriv;
-+
-+	dump_recvbuf_pwait_conf(m, recvpriv);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_sdio_recvbuf_pwait(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+#ifdef CONFIG_SDIO_RECVBUF_PWAIT_RUNTIME_ADJUST
-+	struct net_device *dev = data;
-+	_adapter *adapter = GET_PRIMARY_ADAPTER((_adapter *)rtw_netdev_priv(dev));
-+	struct recv_priv *recvpriv = &adapter->recvpriv;
-+
-+	char tmp[64];
-+	char type[64];
-+	s32 time;
-+	s32 cnt_lmt;
-+
-+	if (count < 3)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%s %d %d", type, &time, &cnt_lmt);
-+		int i;
-+
-+		if (num < 3)
-+			return -EINVAL;
-+
-+		for (i = 0; i < RTW_PWAIT_TYPE_NUM; i++)
-+			if (strncmp(_rtw_pwait_type_str[i], type, strlen(_rtw_pwait_type_str[i])) == 0)
-+				break;
-+
-+		if (i < RTW_PWAIT_TYPE_NUM && recvbuf_pwait_config_req(recvpriv, i, time, cnt_lmt) != _SUCCESS)
-+			return -EINVAL;
-+	}
-+	return count;
-+#else
-+	return -EFAULT;
-+#endif /* CONFIG_SDIO_RECVBUF_PWAIT_RUNTIME_ADJUST */
-+}
-+#endif /* CONFIG_SDIO_RECVBUF_PWAIT */
-+
-+#ifdef DBG_SDIO
-+static int proc_get_sdio_dbg(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev;
-+	struct _ADAPTER *a;
-+	struct dvobj_priv *d;
-+	struct sdio_data *sdio;
-+
-+
-+	dev = m->private;
-+	a = (struct _ADAPTER *)rtw_netdev_priv(dev);
-+	d = adapter_to_dvobj(a);
-+	sdio = &d->intf_data;
-+
-+	dump_sdio_card_info(m, d);
-+
-+	RTW_PRINT_SEL(m, "CMD52 error cnt: %d\n", sdio->cmd52_err_cnt);
-+	RTW_PRINT_SEL(m, "CMD53 error cnt: %d\n", sdio->cmd53_err_cnt);
-+
-+#if (DBG_SDIO >= 3)
-+	RTW_PRINT_SEL(m, "dbg: %s\n", sdio->dbg_enable?"enable":"disable");
-+	RTW_PRINT_SEL(m, "err_stop: %s\n", sdio->err_stop?"enable":"disable");
-+	RTW_PRINT_SEL(m, "err_test: %s\n", sdio->err_test?"enable":"disable");
-+	RTW_PRINT_SEL(m, "err_test_triggered: %s\n",
-+		      sdio->err_test_triggered?"yes":"no");
-+#endif /* DBG_SDIO >= 3 */
-+
-+#if (DBG_SDIO >= 2)
-+	RTW_PRINT_SEL(m, "I/O error dump mark: %d\n", sdio->reg_dump_mark);
-+	if (sdio->reg_dump_mark) {
-+		if (sdio->dbg_msg)
-+			RTW_PRINT_SEL(m, "debug messages: %s\n", sdio->dbg_msg);
-+		if (sdio->reg_mac)
-+			RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, "MAC register:",
-+					 _TRUE, sdio->reg_mac, 0x800);
-+		if (sdio->reg_mac_ext)
-+			RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, "MAC EXT register:",
-+					 _TRUE, sdio->reg_mac_ext, 0x800);
-+		if (sdio->reg_local)
-+			RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, "SDIO Local register:",
-+					 _TRUE, sdio->reg_local, 0x100);
-+		if (sdio->reg_cia)
-+			RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, m, "SDIO CIA register:",
-+					 _TRUE, sdio->reg_cia, 0x200);
-+	}
-+#endif /* DBG_SDIO >= 2 */
-+
-+	return 0;
-+}
-+
-+#if (DBG_SDIO >= 2)
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
-+#define strnicmp	strncasecmp
-+#endif /* Linux kernel >= 4.0.0 */
-+void rtw_sdio_dbg_reg_free(struct dvobj_priv *d);
-+#endif /* DBG_SDIO >= 2 */
-+
-+ssize_t proc_set_sdio_dbg(struct file *file, const char __user *buffer,
-+			  size_t count, loff_t *pos, void *data)
-+{
-+#if (DBG_SDIO >= 2)
-+	struct net_device *dev = data;
-+	struct dvobj_priv *d;
-+	struct _ADAPTER *a;
-+	struct sdio_data *sdio;
-+	char tmp[32], cmd[32] = {0};
-+	int num;
-+
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	a = (struct _ADAPTER *)rtw_netdev_priv(dev);
-+	d = adapter_to_dvobj(a);
-+	sdio = &d->intf_data;
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		num = sscanf(tmp, "%s", cmd);
-+
-+		if (num >= 1) {
-+			if (strnicmp(cmd, "reg_reset", 10) == 0) {
-+				sdio->reg_dump_mark = 0;
-+				goto exit;
-+			}
-+			if (strnicmp(cmd, "reg_free", 9) == 0) {
-+				rtw_sdio_dbg_reg_free(d);
-+				sdio->reg_dump_mark = 0;
-+				goto exit;
-+			}
-+#if (DBG_SDIO >= 3)
-+			if (strnicmp(cmd, "dbg_enable", 11) == 0) {
-+				sdio->dbg_enable = 1;
-+				goto exit;
-+			}
-+			if (strnicmp(cmd, "dbg_disable", 12) == 0) {
-+				sdio->dbg_enable = 0;
-+				goto exit;
-+			}
-+			if (strnicmp(cmd, "err_stop", 9) == 0) {
-+				sdio->err_stop = 1;
-+				goto exit;
-+			}
-+			if (strnicmp(cmd, "err_stop_disable", 16) == 0) {
-+				sdio->err_stop = 0;
-+				goto exit;
-+			}
-+			if (strnicmp(cmd, "err_test", 9) == 0) {
-+				sdio->err_test_triggered = 0;
-+				sdio->err_test = 1;
-+				goto exit;
-+			}
-+#endif /* DBG_SDIO >= 3 */
-+		}
-+
-+		return -EINVAL;
-+	}
-+
-+exit:
-+#endif /* DBG_SDIO >= 2 */
-+	return count;
-+}
-+#endif /* DBG_SDIO */
-+#endif /* CONFIG_SDIO_HCI */
-+
-+static int proc_get_fw_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	rtw_dump_fw_info(m, adapter);
-+	return 0;
-+}
-+static int proc_get_mac_reg_dump(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	mac_reg_dump(m, adapter);
-+
-+	return 0;
-+}
-+
-+static int proc_get_bb_reg_dump(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	bb_reg_dump(m, adapter);
-+
-+	return 0;
-+}
-+
-+static int proc_get_bb_reg_dump_ex(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	bb_reg_dump_ex(m, adapter);
-+
-+	return 0;
-+}
-+
-+static int proc_get_rf_reg_dump(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	rf_reg_dump(m, adapter);
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_RTW_LED
-+int proc_get_led_config(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_led_config(m, adapter);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_led_config(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	char tmp[32];
-+	u8 strategy;
-+	u8 iface_en_mask;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu %hhx", &strategy, &iface_en_mask);
-+
-+		if (num >= 1)
-+			rtw_led_set_strategy(adapter, strategy);
-+		if (num >= 2)
-+			rtw_led_set_iface_en_mask(adapter, iface_en_mask);
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_RTW_LED */
-+
-+#ifdef CONFIG_AP_MODE
-+int proc_get_aid_status(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_aid_status(m, adapter);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_aid_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct sta_priv *stapriv = &adapter->stapriv;
-+
-+	char tmp[32];
-+	u8 rr;
-+	u16 started_aid;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu %hu", &rr, &started_aid);
-+
-+		if (num >= 1)
-+			stapriv->rr_aid = rr ? 1 : 0;
-+		if (num >= 2) {
-+			started_aid = started_aid % (stapriv->max_aid + 1);
-+			stapriv->started_aid = started_aid ? started_aid : 1;
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+int proc_get_ap_isolate(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m, "%d\n", adapter->mlmepriv.ap_isolate);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_ap_isolate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int ap_isolate;
-+		int num = sscanf(tmp, "%d", &ap_isolate);
-+
-+		if (num >= 1)
-+			adapter->mlmepriv.ap_isolate = ap_isolate ? 1 : 0;
-+	}
-+
-+	return count;
-+}
-+
-+#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+static int proc_get_ap_b2u_flags(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_AP(adapter))
-+		dump_ap_b2u_flags(m, adapter);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_ap_b2u_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		u8 src, fwd;
-+		int num = sscanf(tmp, "%hhx %hhx", &src, &fwd);
-+
-+		if (num >= 1)
-+			adapter->b2u_flags_ap_src = src;
-+		if (num >= 2)
-+			adapter->b2u_flags_ap_fwd = fwd;
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_RTW_AP_DATA_BMC_TO_UC */
-+#endif /* CONFIG_AP_MODE */
-+
-+static int proc_get_dump_tx_rate_bmp(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_tx_rate_bmp(m, adapter_to_dvobj(adapter));
-+
-+	return 0;
-+}
-+
-+static int proc_get_dump_adapters_status(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_adapters_status(m, adapter_to_dvobj(adapter));
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+static int proc_get_customer_str(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	u8 cstr[RTW_CUSTOMER_STR_LEN];
-+
-+	rtw_ps_deny(adapter, PS_DENY_IOCTL);
-+	if (rtw_pwr_wakeup(adapter) == _FAIL)
-+		goto exit;
-+
-+	if (rtw_hal_customer_str_read(adapter, cstr) != _SUCCESS)
-+		goto exit;
-+
-+	RTW_PRINT_SEL(m, RTW_CUSTOMER_STR_FMT"\n", RTW_CUSTOMER_STR_ARG(cstr));
-+
-+exit:
-+	rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
-+	return 0;
-+}
-+#endif /* CONFIG_RTW_CUSTOMER_STR */
-+
-+#ifdef CONFIG_SCAN_BACKOP
-+static int proc_get_backop_flags_sta(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+
-+	RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_sta(mlmeext));
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_backop_flags_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+
-+	char tmp[32];
-+	u8 flags;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhx", &flags);
-+
-+		if (num == 1)
-+			mlmeext_assign_scan_backop_flags_sta(mlmeext, flags);
-+	}
-+
-+	return count;
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+static int proc_get_backop_flags_ap(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+
-+	RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_ap(mlmeext));
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+
-+	char tmp[32];
-+	u8 flags;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhx", &flags);
-+
-+		if (num == 1)
-+			mlmeext_assign_scan_backop_flags_ap(mlmeext, flags);
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_AP_MODE */
-+
-+#ifdef CONFIG_RTW_MESH
-+static int proc_get_backop_flags_mesh(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+
-+	RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_mesh(mlmeext));
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_backop_flags_mesh(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+
-+	char tmp[32];
-+	u8 flags;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhx", &flags);
-+
-+		if (num == 1)
-+			mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags);
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_RTW_MESH */
-+
-+#endif /* CONFIG_SCAN_BACKOP */
-+
-+#if defined(CONFIG_LPS_PG) && defined(CONFIG_RTL8822C)
-+static int proc_get_lps_pg_debug(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	struct dm_struct *dm = adapter_to_phydm(adapter);
-+
-+	rtw_run_in_thread_cmd(adapter, ((void *)(odm_lps_pg_debug_8822c)), dm);
-+
-+	return 0;
-+}
-+#endif
-+
-+/* gpio setting */
-+#ifdef CONFIG_GPIO_API
-+static ssize_t proc_set_config_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32] = {0};
-+	int num = 0, gpio_pin = 0, gpio_mode = 0; /* gpio_mode:0 input  1:output; */
-+
-+	if (count < 2)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		num	= sscanf(tmp, "%d %d", &gpio_pin, &gpio_mode);
-+		RTW_INFO("num=%d gpio_pin=%d mode=%d\n", num, gpio_pin, gpio_mode);
-+		padapter->pre_gpio_pin = gpio_pin;
-+
-+		if (gpio_mode == 0 || gpio_mode == 1)
-+			rtw_hal_config_gpio(padapter, gpio_pin, gpio_mode);
-+	}
-+	return count;
-+
-+}
-+static ssize_t proc_set_gpio_output_value(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32] = {0};
-+	int num = 0, gpio_pin = 0, pin_mode = 0; /* pin_mode: 1 high         0:low */
-+
-+	if (count < 2)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		num	= sscanf(tmp, "%d %d", &gpio_pin, &pin_mode);
-+		RTW_INFO("num=%d gpio_pin=%d pin_high=%d\n", num, gpio_pin, pin_mode);
-+		padapter->pre_gpio_pin = gpio_pin;
-+
-+		if (pin_mode == 0 || pin_mode == 1)
-+			rtw_hal_set_gpio_output_value(padapter, gpio_pin, pin_mode);
-+	}
-+	return count;
-+}
-+static int proc_get_gpio(struct seq_file *m, void *v)
-+{
-+	u8 gpioreturnvalue = 0;
-+	struct net_device *dev = m->private;
-+
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	if (!padapter)
-+		return -EFAULT;
-+	gpioreturnvalue = rtw_hal_get_gpio(padapter, padapter->pre_gpio_pin);
-+	RTW_PRINT_SEL(m, "get_gpio %d:%d\n", padapter->pre_gpio_pin, gpioreturnvalue);
-+
-+	return 0;
-+
-+}
-+static ssize_t proc_set_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32] = {0};
-+	int num = 0, gpio_pin = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		num	= sscanf(tmp, "%d", &gpio_pin);
-+		RTW_INFO("num=%d gpio_pin=%d\n", num, gpio_pin);
-+		padapter->pre_gpio_pin = gpio_pin;
-+
-+	}
-+	return count;
-+}
-+#endif
-+
-+static ssize_t proc_set_rx_info_msg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct recv_priv *precvpriv = &(padapter->recvpriv);
-+	char tmp[32] = {0};
-+	int phy_info_flag = 0;
-+
-+	if (!padapter)
-+		return -EFAULT;
-+
-+	if (count < 1) {
-+		RTW_INFO("argument size is less than 1\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%d", &phy_info_flag);
-+
-+		if (num == 1)
-+			precvpriv->store_law_data_flag = (BOOLEAN) phy_info_flag;
-+
-+		/*RTW_INFO("precvpriv->store_law_data_flag = %d\n",( BOOLEAN )(precvpriv->store_law_data_flag));*/
-+	}
-+	return count;
-+}
-+static int proc_get_rx_info_msg(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	rtw_hal_set_odm_var(padapter, HAL_ODM_RX_Dframe_INFO, m, _FALSE);
-+	return 0;
-+}
-+static int proc_get_tx_info_msg(struct seq_file *m, void *v)
-+{
-+	_irqL irqL;
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct sta_info *psta;
-+	u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+	u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct sta_priv *pstapriv = &padapter->stapriv;
-+	int i;
-+	_list	*plist, *phead;
-+	u8 current_rate_id = 0, current_sgi = 0;
-+
-+	char *BW, *status;
-+
-+	_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+	if (MLME_IS_STA(padapter))
-+		status = "station mode";
-+	else if (MLME_IS_AP(padapter))
-+		status = "AP mode";
-+	else if (MLME_IS_MESH(padapter))
-+		status = "mesh mode";
-+	else
-+		status = " ";
-+	_RTW_PRINT_SEL(m, "status=%s\n", status);
-+	for (i = 0; i < NUM_STA; i++) {
-+		phead = &(pstapriv->sta_hash[i]);
-+		plist = get_next(phead);
-+
-+		while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
-+
-+			psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
-+
-+			plist = get_next(plist);
-+
-+			if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)  !=  _TRUE)
-+				&& (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE)
-+				&& (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN) != _TRUE)) {
-+
-+				switch (psta->cmn.bw_mode) {
-+
-+				case CHANNEL_WIDTH_20:
-+					BW = "20M";
-+					break;
-+
-+				case CHANNEL_WIDTH_40:
-+					BW = "40M";
-+					break;
-+
-+				case CHANNEL_WIDTH_80:
-+					BW = "80M";
-+					break;
-+
-+				case CHANNEL_WIDTH_160:
-+					BW = "160M";
-+					break;
-+
-+				default:
-+					BW = "";
-+					break;
-+				}
-+				current_rate_id = rtw_get_current_tx_rate(adapter, psta);
-+				current_sgi = rtw_get_current_tx_sgi(adapter, psta);
-+
-+				RTW_PRINT_SEL(m, "==============================\n");
-+				_RTW_PRINT_SEL(m, "macaddr=" MAC_FMT"\n", MAC_ARG(psta->cmn.mac_addr));
-+				_RTW_PRINT_SEL(m, "Tx_Data_Rate=%s\n", HDATA_RATE(current_rate_id));
-+				_RTW_PRINT_SEL(m, "BW=%s,sgi=%u\n", BW, current_sgi);
-+
-+			}
-+		}
-+	}
-+
-+	_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
-+
-+	return 0;
-+
-+}
-+
-+
-+static int proc_get_linked_info_dump(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	if (padapter)
-+		RTW_PRINT_SEL(m, "linked_info_dump :%s\n", (padapter->bLinkInfoDump) ? "enable" : "disable");
-+
-+	return 0;
-+}
-+
-+
-+static ssize_t proc_set_linked_info_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	char tmp[32] = {0};
-+	int mode = 0, pre_mode = 0;
-+	int num = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	pre_mode = padapter->bLinkInfoDump;
-+	RTW_INFO("pre_mode=%d\n", pre_mode);
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		num	= sscanf(tmp, "%d ", &mode);
-+		RTW_INFO("num=%d mode=%d\n", num, mode);
-+
-+		if (num != 1) {
-+			RTW_INFO("argument number is wrong\n");
-+			return -EFAULT;
-+		}
-+
-+		if (mode == 1 || (mode == 0 && pre_mode == 1)) /* not consider pwr_saving 0: */
-+			padapter->bLinkInfoDump = mode;
-+
-+		else if ((mode == 2) || (mode == 0 && pre_mode == 2)) { /* consider power_saving */
-+			/* RTW_INFO("linked_info_dump =%s\n", (padapter->bLinkInfoDump)?"enable":"disable") */
-+			linked_info_dump(padapter, mode);
-+		}
-+	}
-+	return count;
-+}
-+
-+
-+static int proc_get_sta_tp_dump(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (padapter)
-+		RTW_PRINT_SEL(m, "sta_tp_dump :%s\n", (padapter->bsta_tp_dump) ? "enable" : "disable");
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_sta_tp_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	char tmp[32] = {0};
-+	int mode = 0;
-+	int num = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		num	= sscanf(tmp, "%d ", &mode);
-+
-+		if (num != 1) {
-+			RTW_INFO("argument number is wrong\n");
-+			return -EFAULT;
-+		}
-+		if (padapter)
-+			padapter->bsta_tp_dump = mode;
-+	}
-+	return count;
-+}
-+
-+static int proc_get_sta_tp_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (padapter)
-+		rtw_sta_traffic_info(m, padapter);
-+
-+	return 0;
-+}
-+
-+static int proc_get_turboedca_ctrl(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
-+
-+	if (hal_data) {
-+
-+		u32 edca_param;
-+
-+		if (hal_data->dis_turboedca == 0)
-+			RTW_PRINT_SEL(m, "Turbo-EDCA : %s\n", "Enable");
-+		else
-+			RTW_PRINT_SEL(m, "Turbo-EDCA : %s, mode=%d, edca_param_mode=0x%x\n", "Disable", hal_data->dis_turboedca, hal_data->edca_param_mode);
-+
-+
-+		rtw_hal_get_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
-+
-+		_RTW_PRINT_SEL(m, "PARAM_BE:0x%x\n", edca_param);
-+
-+	}
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_turboedca_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
-+	char tmp[32] = {0};
-+	int mode = 0, num = 0;
-+	u32 param_mode = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp))
-+		return -EFAULT;
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		num = sscanf(tmp, "%d %x", &mode, &param_mode);
-+
-+		if (num < 1 || num > 2) {
-+			RTW_INFO("argument number is wrong\n");
-+			return -EFAULT;
-+		}
-+
-+		/*  0: enable turboedca,
-+			1: disable turboedca,
-+			2: disable turboedca and setting EDCA parameter based on the input parameter
-+			> 2 : currently reset to 0 */
-+
-+		if (mode > 2)
-+			mode = 0;
-+
-+		hal_data->dis_turboedca = mode;
-+
-+		hal_data->edca_param_mode = 0; /* init. value */
-+
-+		RTW_INFO("dis_turboedca mode = 0x%x\n", hal_data->dis_turboedca);
-+
-+		if (num == 2) {
-+
-+			hal_data->edca_param_mode = param_mode;
-+
-+			RTW_INFO("param_mode = 0x%x\n", param_mode);
-+		}
-+
-+	}
-+
-+	return count;
-+
-+}
-+
-+static int proc_get_mac_qinfo(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	rtw_hal_get_hwreg(adapter, HW_VAR_DUMP_MAC_QUEUE_INFO, (u8 *)m);
-+
-+	return 0;
-+}
-+
-+int proc_get_wifi_spec(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv	*pregpriv = &padapter->registrypriv;
-+
-+	RTW_PRINT_SEL(m, "wifi_spec=%d\n", pregpriv->wifi_spec);
-+	return 0;
-+}
-+
-+static int proc_get_chan_plan(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_cur_chset(m, adapter_to_rfctl(adapter));
-+	return 0;
-+}
-+
-+static ssize_t proc_set_chan_plan(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 chan_plan = RTW_CHPLAN_UNSPECIFIED;
-+
-+	if (!padapter)
-+		return -EFAULT;
-+
-+	if (count < 1) {
-+		RTW_INFO("argument size is less than 1\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%hhx", &chan_plan);
-+		if (num !=  1)
-+			return count;
-+	}
-+
-+	rtw_set_channel_plan(padapter, chan_plan);
-+
-+	return count;
-+}
-+
-+static int proc_get_country_code(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	if (rfctl->country_ent)
-+		dump_country_chplan(m, rfctl->country_ent);
-+	else
-+		RTW_PRINT_SEL(m, "unspecified\n");
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_country_code(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	char alpha2[2];
-+	int num;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (!buffer || copy_from_user(tmp, buffer, count))
-+		goto exit;
-+
-+	num = sscanf(tmp, "%c%c", &alpha2[0], &alpha2[1]);
-+	if (num !=	2)
-+		return count;
-+
-+	rtw_set_country(padapter, alpha2);
-+
-+exit:
-+	return count;
-+}
-+
-+static int cap_spt_op_class_ch_detail = 0;
-+
-+static int proc_get_cap_spt_op_class_ch(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_cap_spt_op_class_ch(m , adapter_to_rfctl(adapter), cap_spt_op_class_ch_detail);
-+	return 0;
-+}
-+
-+static ssize_t proc_set_cap_spt_op_class_ch(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	int num;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (!buffer || copy_from_user(tmp, buffer, count))
-+		goto exit;
-+
-+	num = sscanf(tmp, "%d", &cap_spt_op_class_ch_detail);
-+
-+exit:
-+	return count;
-+}
-+
-+static int reg_spt_op_class_ch_detail = 0;
-+
-+static int proc_get_reg_spt_op_class_ch(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_reg_spt_op_class_ch(m , adapter_to_rfctl(adapter), reg_spt_op_class_ch_detail);
-+	return 0;
-+}
-+
-+static ssize_t proc_set_reg_spt_op_class_ch(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	int num;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (!buffer || copy_from_user(tmp, buffer, count))
-+		goto exit;
-+
-+	num = sscanf(tmp, "%d", &reg_spt_op_class_ch_detail);
-+
-+exit:
-+	return count;
-+}
-+
-+static int cur_spt_op_class_ch_detail = 0;
-+
-+static int proc_get_cur_spt_op_class_ch(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_cur_spt_op_class_ch(m , adapter_to_rfctl(adapter), cur_spt_op_class_ch_detail);
-+	return 0;
-+}
-+
-+static ssize_t proc_set_cur_spt_op_class_ch(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	int num;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (!buffer || copy_from_user(tmp, buffer, count))
-+		goto exit;
-+
-+	num = sscanf(tmp, "%d", &cur_spt_op_class_ch_detail);
-+
-+exit:
-+	return count;
-+}
-+
-+#if CONFIG_RTW_MACADDR_ACL
-+static int proc_get_macaddr_acl(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_macaddr_acl(m, adapter);
-+	return 0;
-+}
-+
-+ssize_t proc_set_macaddr_acl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[17 * NUM_ACL + 32] = {0};
-+	u8 period;
-+	char cmd[32];
-+	u8 mode;
-+	u8 addr[ETH_ALEN];
-+
-+#define MAC_ACL_CMD_MODE	0
-+#define MAC_ACL_CMD_ADD		1
-+#define MAC_ACL_CMD_DEL		2
-+#define MAC_ACL_CMD_CLR		3
-+#define MAC_ACL_CMD_NUM		4
-+
-+	static const char * const mac_acl_cmd_str[] = {
-+		"mode",
-+		"add",
-+		"del",
-+		"clr",
-+	};
-+	u8 cmd_id = MAC_ACL_CMD_NUM;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		/*
-+		* <period> mode <mode> <macaddr> [<macaddr>]
-+		* <period> mode <mode>
-+		* <period> add <macaddr> [<macaddr>]
-+		* <period> del <macaddr> [<macaddr>]
-+		* <period> clr
-+		*/
-+		char *c, *next;
-+		int i;
-+		u8 is_bcast;
-+
-+		next = tmp;
-+		c = strsep(&next, " \t");
-+		if (!c || sscanf(c, "%hhu", &period) != 1)
-+			goto exit;
-+
-+		if (period >= RTW_ACL_PERIOD_NUM) {
-+			RTW_WARN(FUNC_ADPT_FMT" invalid period:%u", FUNC_ADPT_ARG(adapter), period);
-+			goto exit;
-+		}
-+
-+		c = strsep(&next, " \t");
-+		if (!c || sscanf(c, "%s", cmd) != 1)
-+			goto exit;
-+
-+		for (i = 0; i < MAC_ACL_CMD_NUM; i++)
-+			if (strcmp(mac_acl_cmd_str[i], cmd) == 0)
-+				cmd_id = i;
-+
-+		switch (cmd_id) {
-+		case MAC_ACL_CMD_MODE:
-+			c = strsep(&next, " \t");
-+			if (!c || sscanf(c, "%hhu", &mode) != 1)
-+				goto exit;
-+
-+			if (mode >= RTW_ACL_MODE_MAX) {
-+				RTW_WARN(FUNC_ADPT_FMT" invalid mode:%u", FUNC_ADPT_ARG(adapter), mode);
-+				goto exit;
-+			}
-+			break;
-+
-+		case MAC_ACL_CMD_ADD:
-+		case MAC_ACL_CMD_DEL:
-+			break;
-+
-+		case MAC_ACL_CMD_CLR:
-+			/* clear settings */
-+			rtw_macaddr_acl_clear(adapter, period);
-+			goto exit;
-+
-+		default:
-+			RTW_WARN(FUNC_ADPT_FMT" invalid cmd:\"%s\"", FUNC_ADPT_ARG(adapter), cmd);
-+			goto exit;
-+		}
-+
-+		/* check for macaddr list */
-+		c = strsep(&next, " \t");
-+		if (!c && cmd_id == MAC_ACL_CMD_MODE) {
-+			/* set mode only  */
-+			rtw_set_macaddr_acl(adapter, period, mode);
-+			goto exit;
-+		}
-+
-+		if (cmd_id == MAC_ACL_CMD_MODE) {
-+			/* set mode and entire macaddr list */
-+			rtw_macaddr_acl_clear(adapter, period);
-+			rtw_set_macaddr_acl(adapter, period, mode);
-+		}
-+
-+		while (c != NULL) {
-+			if (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6)
-+				break;
-+
-+			is_bcast = is_broadcast_mac_addr(addr);
-+			if (is_bcast
-+				|| rtw_check_invalid_mac_address(addr, 0) == _FALSE
-+			) {
-+				if (cmd_id == MAC_ACL_CMD_DEL) {
-+					rtw_acl_remove_sta(adapter, period, addr);
-+					if (is_bcast)
-+						break;
-+				 } else if (!is_bcast)
-+					rtw_acl_add_sta(adapter, period, addr);
-+			}
-+
-+			c = strsep(&next, " \t");
-+		}
-+	}
-+
-+exit:
-+	return count;
-+}
-+#endif /* CONFIG_RTW_MACADDR_ACL */
-+
-+#if CONFIG_RTW_PRE_LINK_STA
-+static int proc_get_pre_link_sta(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_pre_link_sta_ctl(m, &adapter->stapriv);
-+	return 0;
-+}
-+
-+ssize_t proc_set_pre_link_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+	struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-+	char tmp[17 * RTW_PRE_LINK_STA_NUM + 32] = {0};
-+	char arg0[16] = {0};
-+	u8 addr[ETH_ALEN];
-+
-+#define PRE_LINK_STA_CMD_RESET	0
-+#define PRE_LINK_STA_CMD_ADD	1
-+#define PRE_LINK_STA_CMD_DEL	2
-+#define PRE_LINK_STA_CMD_NUM	3
-+
-+	static const char * const pre_link_sta_cmd_str[] = {
-+		"reset",
-+		"add",
-+		"del"
-+	};
-+	u8 cmd_id = PRE_LINK_STA_CMD_NUM;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		/* cmd [<macaddr>] */
-+		char *c, *next;
-+		int i;
-+
-+		next = tmp;
-+		c = strsep(&next, " \t");
-+
-+		if (sscanf(c, "%s", arg0) != 1)
-+			goto exit;
-+
-+		for (i = 0; i < PRE_LINK_STA_CMD_NUM; i++)
-+			if (strcmp(pre_link_sta_cmd_str[i], arg0) == 0)
-+				cmd_id = i;
-+
-+		switch (cmd_id) {
-+		case PRE_LINK_STA_CMD_RESET:
-+			rtw_pre_link_sta_ctl_reset(&adapter->stapriv);
-+			goto exit;
-+		case PRE_LINK_STA_CMD_ADD:
-+		case PRE_LINK_STA_CMD_DEL:
-+			break;
-+		default:
-+			goto exit;
-+		}
-+
-+		/* macaddr list */
-+		c = strsep(&next, " \t");
-+		while (c != NULL) {
-+			if (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6)
-+				break;
-+
-+			if (rtw_check_invalid_mac_address(addr, 0) == _FALSE) {
-+				if (cmd_id == PRE_LINK_STA_CMD_ADD)
-+					rtw_pre_link_sta_add(&adapter->stapriv, addr);
-+				else
-+					rtw_pre_link_sta_del(&adapter->stapriv, addr);
-+			}
-+
-+			c = strsep(&next, " \t");
-+		}
-+	}
-+
-+exit:
-+	return count;
-+}
-+#endif /* CONFIG_RTW_PRE_LINK_STA */
-+
-+static int proc_get_ch_sel_policy(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	RTW_PRINT_SEL(m, "%-16s\n", "within_same_band");
-+
-+	RTW_PRINT_SEL(m, "%16d\n", rfctl->ch_sel_within_same_band);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_ch_sel_policy(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	char tmp[32];
-+	u8 within_sb;
-+	int num;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (!buffer || copy_from_user(tmp, buffer, count))
-+		goto exit;
-+
-+	num = sscanf(tmp, "%hhu", &within_sb);
-+	if (num >=	1)
-+		rfctl->ch_sel_within_same_band = within_sb ? 1 : 0;
-+
-+exit:
-+	return count;
-+}
-+
-+#ifdef CONFIG_DFS_MASTER
-+static int proc_get_dfs_test_case(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	RTW_PRINT_SEL(m, "%-24s %-19s\n", "radar_detect_trigger_non", "choose_dfs_ch_first");
-+	RTW_PRINT_SEL(m, "%24hhu %19hhu\n"
-+		, rfctl->dbg_dfs_radar_detect_trigger_non
-+		, rfctl->dbg_dfs_choose_dfs_ch_first
-+	);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_dfs_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	char tmp[32];
-+	u8 radar_detect_trigger_non;
-+	u8 choose_dfs_ch_first;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%hhu %hhu", &radar_detect_trigger_non, &choose_dfs_ch_first);
-+
-+		if (num >= 1)
-+			rfctl->dbg_dfs_radar_detect_trigger_non = radar_detect_trigger_non;
-+		if (num >= 2)
-+			rfctl->dbg_dfs_choose_dfs_ch_first = choose_dfs_ch_first;
-+	}
-+
-+	return count;
-+}
-+
-+ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	char tmp[32];
-+	u8 ch, bw = CHANNEL_WIDTH_20, offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-+	int ms = -1;
-+	bool updated = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu %hhu %hhu %d", &ch, &bw, &offset, &ms);
-+
-+		if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3))
-+			goto exit;
-+
-+		if (bw == CHANNEL_WIDTH_20)
-+			updated = rtw_chset_update_non_ocp_ms(rfctl->channel_set
-+				, ch, bw, HAL_PRIME_CHNL_OFFSET_DONT_CARE, ms);
-+		else
-+			updated = rtw_chset_update_non_ocp_ms(rfctl->channel_set
-+				, ch, bw, offset, ms);
-+
-+		if (updated) {
-+			u8 cch = rtw_get_center_ch(ch, bw, offset);
-+
-+			rtw_nlrtw_nop_start_event(adapter, cch, bw);
-+		}
-+	}
-+
-+exit:
-+	return count;
-+}
-+
-+ssize_t proc_set_radar_detect(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	char tmp[32];
-+	u8 fake_radar_detect_cnt = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu", &fake_radar_detect_cnt);
-+
-+		if (num < 1)
-+			goto exit;
-+
-+		rfctl->dbg_dfs_fake_radar_detect_cnt = fake_radar_detect_cnt;
-+	}
-+
-+exit:
-+	return count;
-+}
-+
-+static int proc_get_dfs_ch_sel_e_flags(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	RTW_PRINT_SEL(m, "0x%02x\n", rfctl->dfs_ch_sel_e_flags);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_dfs_ch_sel_e_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	char tmp[32];
-+	u8 e_flags;
-+	int num;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (!buffer || copy_from_user(tmp, buffer, count))
-+		goto exit;
-+
-+	num = sscanf(tmp, "%hhx", &e_flags);
-+	if (num != 1)
-+		goto exit;
-+
-+	rfctl->dfs_ch_sel_e_flags = e_flags;
-+
-+exit:
-+	return count;
-+}
-+
-+static int proc_get_dfs_ch_sel_d_flags(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	RTW_PRINT_SEL(m, "0x%02x\n", rfctl->dfs_ch_sel_d_flags);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_dfs_ch_sel_d_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	char tmp[32];
-+	u8 d_flags;
-+	int num;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (!buffer || copy_from_user(tmp, buffer, count))
-+		goto exit;
-+
-+	num = sscanf(tmp, "%hhx", &d_flags);
-+	if (num != 1)
-+		goto exit;
-+
-+	rfctl->dfs_ch_sel_d_flags = d_flags;
-+
-+exit:
-+	return count;
-+}
-+
-+#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
-+static int proc_get_dfs_slave_with_rd(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	RTW_PRINT_SEL(m, "%u\n", rfctl->dfs_slave_with_rd);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_dfs_slave_with_rd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+	char tmp[32];
-+	u8 rd;
-+	int num;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (!buffer || copy_from_user(tmp, buffer, count))
-+		goto exit;
-+
-+	num = sscanf(tmp, "%hhu", &rd);
-+	if (num != 1)
-+		goto exit;
-+
-+	rd = rd ? 1 : 0;
-+
-+	if (rfctl->dfs_slave_with_rd != rd) {
-+		rfctl->dfs_slave_with_rd = rd;
-+		rtw_dfs_rd_en_decision_cmd(adapter);
-+	}
-+
-+exit:
-+	return count;
-+}
-+#endif /* CONFIG_DFS_SLAVE_WITH_RADAR_DETECT */
-+#endif /* CONFIG_DFS_MASTER */
-+
-+#ifdef CONFIG_80211N_HT
-+int proc_get_rx_ampdu_size_limit(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_regsty_rx_ampdu_size_limit(m, adapter);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_rx_ampdu_size_limit(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv *regsty = adapter_to_regsty(adapter);
-+	char tmp[32];
-+	u8 nss;
-+	u8 limit_by_bw[4] = {0xFF};
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int i;
-+		int num = sscanf(tmp, "%hhu %hhu %hhu %hhu %hhu"
-+			, &nss, &limit_by_bw[0], &limit_by_bw[1], &limit_by_bw[2], &limit_by_bw[3]);
-+
-+		if (num < 2)
-+			goto exit;
-+		if (nss == 0 || nss > 4)
-+			goto exit;
-+
-+		for (i = 0; i < num - 1; i++)
-+			regsty->rx_ampdu_sz_limit_by_nss_bw[nss - 1][i] = limit_by_bw[i];
-+
-+		rtw_rx_ampdu_apply(adapter);
-+	}
-+
-+exit:
-+	return count;
-+}
-+#endif /* CONFIG_80211N_HT */
-+
-+static int proc_get_rx_chk_limit(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m, "Rx chk limit : %d\n", rtw_get_rx_chk_limit(padapter));
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_rx_chk_limit(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	char tmp[32];
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	int rx_chk_limit;
-+
-+	if (count < 1) {
-+		RTW_INFO("argument size is less than 1\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%d", &rx_chk_limit);
-+
-+		rtw_set_rx_chk_limit(padapter, rx_chk_limit);
-+	}
-+
-+	return count;
-+}
-+
-+static int proc_get_udpport(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct recv_priv *precvpriv = &(padapter->recvpriv);
-+
-+	RTW_PRINT_SEL(m, "%d\n", precvpriv->sink_udpport);
-+	return 0;
-+}
-+static ssize_t proc_set_udpport(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct recv_priv *precvpriv = &(padapter->recvpriv);
-+	int sink_udpport = 0;
-+	char tmp[32];
-+
-+
-+	if (!padapter)
-+		return -EFAULT;
-+
-+	if (count < 1) {
-+		RTW_INFO("argument size is less than 1\n");
-+		return -EFAULT;
-+	}
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%d", &sink_udpport);
-+
-+		if (num !=  1) {
-+			RTW_INFO("invalid input parameter number!\n");
-+			return count;
-+		}
-+
-+	}
-+	precvpriv->sink_udpport = sink_udpport;
-+
-+	return count;
-+
-+}
-+
-+static int proc_get_mi_ap_bc_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	u8 i;
-+
-+	for (i = 0; i < dvobj->iface_nums; i++)
-+		RTW_PRINT_SEL(m, "iface_id:%d, mac_id && sec_cam_id = %d\n", i, macid_ctl->iface_bmc[i]);
-+
-+	return 0;
-+}
-+static int proc_get_macid_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-+	u8 i;
-+	u8 null_addr[ETH_ALEN] = {0};
-+	u8 *macaddr;
-+
-+	RTW_PRINT_SEL(m, "max_num:%u\n", macid_ctl->num);
-+	RTW_PRINT_SEL(m, "\n");
-+
-+	RTW_PRINT_SEL(m, "used:\n");
-+	dump_macid_map(m, &macid_ctl->used, macid_ctl->num);
-+	RTW_PRINT_SEL(m, "\n");
-+
-+	RTW_PRINT_SEL(m, "%-3s %-3s %-5s %-4s %-17s %-6s %-3s"
-+		, "id", "bmc", "ifbmp", "ch_g", "macaddr", "bw", "vht");
-+
-+	if (GET_HAL_TX_NSS(adapter) > 2)
-+		_RTW_PRINT_SEL(m, " %-10s", "rate_bmp1");
-+
-+	_RTW_PRINT_SEL(m, " %-10s %s\n", "rate_bmp0", "status");
-+
-+	for (i = 0; i < macid_ctl->num; i++) {
-+		if (rtw_macid_is_used(macid_ctl, i)
-+			|| macid_ctl->h2c_msr[i]
-+		) {
-+			if (macid_ctl->sta[i])
-+				macaddr = macid_ctl->sta[i]->cmn.mac_addr;
-+			else
-+				macaddr = null_addr;
-+
-+			RTW_PRINT_SEL(m, "%3u %3u  0x%02x %4d "MAC_FMT" %6s %3u"
-+				, i
-+				, rtw_macid_is_bmc(macid_ctl, i)
-+				, rtw_macid_get_iface_bmp(macid_ctl, i)
-+				, rtw_macid_get_ch_g(macid_ctl, i)
-+				, MAC_ARG(macaddr)
-+				, ch_width_str(macid_ctl->bw[i])
-+				, macid_ctl->vht_en[i]
-+			);
-+
-+			if (GET_HAL_TX_NSS(adapter) > 2)
-+				_RTW_PRINT_SEL(m, " 0x%08X", macid_ctl->rate_bmp1[i]);
-+
-+			_RTW_PRINT_SEL(m, " 0x%08X "H2C_MSR_FMT" %s\n"
-+				, macid_ctl->rate_bmp0[i]
-+				, H2C_MSR_ARG(&macid_ctl->h2c_msr[i])
-+				, rtw_macid_is_used(macid_ctl, i) ? "" : "[unused]"
-+			);
-+		}
-+	}
-+	RTW_PRINT_SEL(m, "\n");
-+
-+	for (i = 0; i < H2C_MSR_ROLE_MAX; i++) {
-+		if (macid_ctl->op_num[i]) {
-+			RTW_PRINT_SEL(m, "%-5s op_num:%u\n"
-+				, h2c_msr_role_str(i), macid_ctl->op_num[i]);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int proc_get_sec_cam(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+
-+	RTW_PRINT_SEL(m, "sec_cap:0x%02x\n", cam_ctl->sec_cap);
-+	RTW_PRINT_SEL(m, "flags:0x%08x\n", cam_ctl->flags);
-+	RTW_PRINT_SEL(m, "\n");
-+
-+	RTW_PRINT_SEL(m, "max_num:%u\n", cam_ctl->num);
-+	RTW_PRINT_SEL(m, "used:\n");
-+	dump_sec_cam_map(m, &cam_ctl->used, cam_ctl->num);
-+	RTW_PRINT_SEL(m, "\n");
-+
-+	RTW_PRINT_SEL(m, "reg_scr:0x%04x\n", rtw_read16(adapter, 0x680));
-+	RTW_PRINT_SEL(m, "\n");
-+
-+	dump_sec_cam(m, adapter);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_sec_cam(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
-+	char tmp[32] = {0};
-+	char cmd[4];
-+	u8 id_1 = 0, id_2 = 0;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		/* c <id_1>: clear specific cam entry */
-+		/* wfc <id_1>: write specific cam entry from cam cache */
-+		/* sw <id_1> <id_2>: sec_cam 1/2 swap */
-+
-+		int num = sscanf(tmp, "%s %hhu %hhu", cmd, &id_1, &id_2);
-+
-+		if (num < 2)
-+			return count;
-+
-+		if ((id_1 >= cam_ctl->num) || (id_2 >= cam_ctl->num)) {
-+			RTW_ERR(FUNC_ADPT_FMT" invalid id_1:%u id_2:%u\n", FUNC_ADPT_ARG(adapter), id_1, id_2);
-+			return count;
-+		}
-+
-+		if (strcmp("c", cmd) == 0) {
-+			_clear_cam_entry(adapter, id_1);
-+			adapter->securitypriv.hw_decrypted = _FALSE; /* temporarily set this for TX path to use SW enc */
-+		} else if (strcmp("wfc", cmd) == 0)
-+			write_cam_from_cache(adapter, id_1);
-+		else if (strcmp("sw", cmd) == 0)
-+			rtw_sec_cam_swap(adapter, id_1, id_2);
-+		else if (strcmp("cdk", cmd) == 0)
-+			rtw_clean_dk_section(adapter);
-+#ifdef DBG_SEC_CAM_MOVE
-+		else if (strcmp("sgd", cmd) == 0)
-+			rtw_hal_move_sta_gk_to_dk(adapter);
-+		else if (strcmp("rsd", cmd) == 0)
-+			rtw_hal_read_sta_dk_key(adapter, id_1);
-+#endif
-+	}
-+
-+	return count;
-+}
-+
-+static int proc_get_sec_cam_cache(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_sec_cam_cache(m, adapter);
-+	return 0;
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+static ssize_t proc_set_change_bss_chbw(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	int i;
-+	char tmp[32];
-+	s16 ch;
-+	s8 bw = REQ_BW_NONE, offset = REQ_OFFSET_NONE;
-+	u8 ifbmp = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hd %hhd %hhd %hhx", &ch, &bw, &offset, &ifbmp);
-+
-+		if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3))
-+			goto exit;
-+
-+		if (num < 4)
-+			ifbmp = BIT(adapter->iface_id);
-+		else
-+			ifbmp &= (1 << dvobj->iface_nums) - 1;
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			if (!(ifbmp & BIT(i)) || !dvobj->padapters[i])
-+				continue;
-+
-+			if (!CHK_MLME_STATE(dvobj->padapters[i], WIFI_AP_STATE | WIFI_MESH_STATE)
-+				|| !MLME_IS_ASOC(dvobj->padapters[i]))
-+				ifbmp &= ~BIT(i);
-+		}
-+
-+		if (ifbmp)
-+			rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_WAIT_ACK, ifbmp, 0, ch, bw, offset);
-+	}
-+
-+exit:
-+	return count;
-+}
-+#endif
-+
-+#if CONFIG_TX_AC_LIFETIME
-+static int proc_get_tx_aclt_force_val(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	dump_tx_aclt_force_val(m, dvobj);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_tx_aclt_force_val(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	char tmp[32] = {0};
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+		struct tx_aclt_conf_t input;
-+		int num = sscanf(tmp, "%hhx %u %u", &input.en, &input.vo_vi, &input.be_bk);
-+
-+		if (num < 1)
-+			return count;
-+
-+		rtw_hal_set_tx_aclt_force_val(adapter, &input, num);
-+		rtw_run_in_thread_cmd(adapter, ((void *)(rtw_hal_update_tx_aclt)), adapter);
-+	}
-+
-+	return count;
-+}
-+
-+static int proc_get_tx_aclt_flags(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	RTW_PRINT_SEL(m, "0x%02x\n", dvobj->tx_aclt_flags);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_tx_aclt_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	char tmp[32] = {0};
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+		u8 flags;
-+		int num = sscanf(tmp, "%hhx", &flags);
-+
-+		if (num < 1)
-+			return count;
-+
-+		if (dvobj->tx_aclt_flags == flags)
-+			return count;
-+
-+		dvobj->tx_aclt_flags = flags;
-+
-+		rtw_run_in_thread_cmd(adapter, ((void *)(rtw_hal_update_tx_aclt)), adapter);
-+	}
-+
-+	return count;
-+}
-+
-+static int proc_get_tx_aclt_confs(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	RTW_PRINT_SEL(m, "flags:0x%02x\n", dvobj->tx_aclt_flags);
-+	dump_tx_aclt_confs(m, dvobj);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_tx_aclt_confs(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	char tmp[32] = {0};
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+		u8 id;
-+		struct tx_aclt_conf_t input;
-+		int num = sscanf(tmp, "%hhu %hhx %u %u", &id, &input.en, &input.vo_vi, &input.be_bk);
-+
-+		if (num < 2)
-+			return count;
-+
-+		rtw_hal_set_tx_aclt_conf(adapter, id, &input, num - 1);
-+		rtw_run_in_thread_cmd(adapter, ((void *)(rtw_hal_update_tx_aclt)), adapter);
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_TX_AC_LIFETIME */
-+
-+static int proc_get_tx_bw_mode(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m, "0x%02x\n", adapter->driver_tx_bw_mode);
-+	RTW_PRINT_SEL(m, "2.4G:%s\n", ch_width_str(ADAPTER_TX_BW_2G(adapter)));
-+	RTW_PRINT_SEL(m, "5G:%s\n", ch_width_str(ADAPTER_TX_BW_5G(adapter)));
-+
-+	return 0;
-+}
-+
-+static void rtw_set_tx_bw_mode(struct _ADAPTER *adapter, u8 bw_mode)
-+{
-+	struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv);
-+	struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
-+	u8 update = _FALSE;
-+
-+	if ((MLME_STATE(adapter) & WIFI_ASOC_STATE)
-+		&& ((mlmeext->cur_channel <= 14 && BW_MODE_2G(bw_mode) != ADAPTER_TX_BW_2G(adapter))
-+			|| (mlmeext->cur_channel >= 36 && BW_MODE_5G(bw_mode) != ADAPTER_TX_BW_5G(adapter)))
-+	) {
-+		/* RA mask update needed */
-+		update = _TRUE;
-+	}
-+	adapter->driver_tx_bw_mode = bw_mode;
-+
-+	if (update == _TRUE) {
-+		struct sta_info *sta;
-+		int i;
-+
-+		for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
-+			sta = macid_ctl->sta[i];
-+			if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr))
-+				rtw_dm_ra_mask_wk_cmd(adapter, (u8 *)sta);
-+		}
-+	}
-+}
-+
-+static ssize_t proc_set_tx_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 bw_mode;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhx", &bw_mode);
-+
-+		if (num < 1 || bw_mode == adapter->driver_tx_bw_mode)
-+			goto exit;
-+
-+		rtw_set_tx_bw_mode(adapter, bw_mode);
-+	}
-+
-+exit:
-+	return count;
-+}
-+
-+static int proc_get_hal_txpwr_info(struct seq_file *m, void *v)
-+{
-+#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+
-+	if (hal_data->txpwr_pg_mode == TXPWR_PG_WITH_PWR_IDX) {
-+		if (hal_is_band_support(adapter, BAND_ON_2_4G))
-+			dump_hal_txpwr_info_2g(m, adapter, hal_spec->rfpath_num_2g, hal_data->max_tx_cnt);
-+
-+		#if CONFIG_IEEE80211_BAND_5GHZ
-+		if (hal_is_band_support(adapter, BAND_ON_5G))
-+			dump_hal_txpwr_info_5g(m, adapter, hal_spec->rfpath_num_5g, hal_data->max_tx_cnt);
-+		#endif
-+	}
-+#endif
-+
-+	return 0;
-+}
-+
-+static int proc_get_target_tx_power(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_target_tx_power(m, adapter);
-+
-+	return 0;
-+}
-+
-+static int proc_get_tx_power_by_rate(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_tx_power_by_rate(m, adapter);
-+
-+	return 0;
-+}
-+
-+#if CONFIG_TXPWR_LIMIT
-+static int proc_get_tx_power_limit(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_txpwr_lmt(m, adapter);
-+
-+	return 0;
-+}
-+#endif /* CONFIG_TXPWR_LIMIT */
-+
-+static int proc_get_tpc_settings(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_txpwr_tpc_settings(m, adapter);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_tpc_settings(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	char tmp[32] = {0};
-+	u8 mode;
-+	u16 m_constraint;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu %hu", &mode, &m_constraint);
-+
-+		if (num < 1)
-+			return count;
-+
-+		if (mode >= TPC_MODE_INVALID)
-+			return count;
-+
-+		if (mode == TPC_MODE_MANUAL && num >= 2)
-+			rfctl->tpc_manual_constraint = rtw_min(m_constraint, TPC_MANUAL_CONSTRAINT_MAX);
-+		rfctl->tpc_mode = mode;
-+
-+		if (rtw_get_hw_init_completed(adapter))
-+			rtw_run_in_thread_cmd_wait(adapter, ((void *)(rtw_hal_update_txpwr_level)), adapter, 2000);
-+	}
-+
-+	return count;
-+}
-+
-+static int proc_get_antenna_gain(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_txpwr_antenna_gain(m, adapter);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_antenna_gain(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-+
-+	char tmp[32] = {0};
-+	s16 gain;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hd", &gain);
-+
-+		if (num < 1)
-+			return count;
-+
-+		rfctl->antenna_gain = gain;
-+
-+		if (rtw_get_hw_init_completed(adapter))
-+			rtw_run_in_thread_cmd_wait(adapter, ((void *)(rtw_hal_update_txpwr_level)), adapter, 2000);
-+	}
-+
-+	return count;
-+}
-+
-+static int proc_get_tx_power_ext_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_tx_power_ext_info(m, adapter);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	char tmp[32] = {0};
-+	char cmd[16] = {0};
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%s", cmd);
-+
-+		if (num < 1)
-+			return count;
-+
-+		#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
-+		phy_free_filebuf_mask(adapter, LOAD_BB_PG_PARA_FILE | LOAD_RF_TXPWR_LMT_PARA_FILE);
-+		#endif
-+
-+		rtw_ps_deny(adapter, PS_DENY_IOCTL);
-+		if (rtw_pwr_wakeup(adapter) == _FALSE)
-+			goto clear_ps_deny;
-+
-+		if (strcmp("default", cmd) == 0)
-+			rtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_default_tx_power_ext_info)), adapter);
-+		else
-+			rtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_tx_power_ext_info)), adapter);
-+
-+		rtw_run_in_thread_cmd_wait(adapter, ((void *)(rtw_hal_update_txpwr_level)), adapter, 2000);
-+
-+clear_ps_deny:
-+		rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
-+	}
-+
-+	return count;
-+}
-+
-+static void *proc_start_tx_power_idx(struct seq_file *m, loff_t *pos)
-+{
-+	u8 path = ((*pos) & 0xFF00) >> 8;
-+
-+	if (path >= RF_PATH_MAX)
-+		return NULL;
-+
-+	return pos;
-+}
-+static void proc_stop_tx_power_idx(struct seq_file *m, void *v)
-+{
-+}
-+
-+static void *proc_next_tx_power_idx(struct seq_file *m, void *v, loff_t *pos)
-+{
-+	u8 path = ((*pos) & 0xFF00) >> 8;
-+	u8 rs = *pos & 0xFF;
-+
-+	rs++;
-+	if (rs >= RATE_SECTION_NUM) {
-+		rs = 0;
-+		path++;
-+	}
-+
-+	if (path >= RF_PATH_MAX)
-+		return NULL;
-+
-+	*pos = (path << 8) | rs;
-+
-+	return pos;
-+}
-+
-+static int proc_get_tx_power_idx(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u32 pos = *((loff_t *)(v));
-+	u8 path = (pos & 0xFF00) >> 8;
-+	u8 rs = pos & 0xFF;
-+	enum channel_width bw = hal_data->current_channel_bw;
-+	u8 cch = hal_data->current_channel;
-+
-+	if (0)
-+		RTW_INFO("%s path=%u, rs=%u\n", __func__, path, rs);
-+
-+	if (path == RF_PATH_A && rs == CCK)
-+		dump_tx_power_idx_title(m, adapter, bw, cch, 0);
-+	dump_tx_power_idx_by_path_rs(m, adapter, path, rs, bw, cch, 0);
-+
-+	return 0;
-+}
-+
-+static struct seq_operations seq_ops_tx_power_idx = {
-+	.start = proc_start_tx_power_idx,
-+	.stop  = proc_stop_tx_power_idx,
-+	.next  = proc_next_tx_power_idx,
-+	.show  = proc_get_tx_power_idx,
-+};
-+
-+static ssize_t proc_set_tx_power_idx_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	char tmp[32] = {0};
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		u8 ch, bw, offset;
-+		u8 cch;
-+
-+		int num = sscanf(tmp, "%hhu %hhu %hhu", &ch, &bw, &offset);
-+
-+		if (num < 3)
-+			return count;
-+
-+		cch = rtw_get_center_ch(ch, bw, offset);
-+		dump_tx_power_idx(RTW_DBGDUMP, adapter, bw, cch, ch);
-+	}
-+
-+	return count;
-+}
-+
-+static void *proc_start_txpwr_total_dbm(struct seq_file *m, loff_t *pos)
-+{
-+	u8 rs = *pos;
-+
-+	if (rs >= RATE_SECTION_NUM)
-+		return NULL;
-+
-+	return pos;
-+}
-+
-+static void proc_stop_txpwr_total_dbm(struct seq_file *m, void *v)
-+{
-+}
-+
-+static void *proc_next_txpwr_total_dbm(struct seq_file *m, void *v, loff_t *pos)
-+{
-+	u8 rs = *pos;
-+
-+	rs++;
-+	if (rs >= RATE_SECTION_NUM)
-+		return NULL;
-+
-+	*pos = rs;
-+
-+	return pos;
-+}
-+
-+static int proc_get_txpwr_total_dbm(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-+	u32 pos = *((loff_t *)(v));
-+	u8 rs = pos;
-+	enum channel_width bw = hal_data->current_channel_bw;
-+	u8 cch = hal_data->current_channel;
-+
-+	if (rs == CCK)
-+		dump_txpwr_total_dbm_title(m, adapter, bw, cch, 0);
-+	dump_txpwr_total_dbm_by_rs(m, adapter, rs, bw, cch, 0);
-+
-+	return 0;
-+}
-+
-+static struct seq_operations seq_ops_txpwr_total_dbm = {
-+	.start = proc_start_txpwr_total_dbm,
-+	.stop  = proc_stop_txpwr_total_dbm,
-+	.next  = proc_next_txpwr_total_dbm,
-+	.show  = proc_get_txpwr_total_dbm,
-+};
-+
-+static ssize_t proc_set_txpwr_total_dbm_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	char tmp[32] = {0};
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		u8 ch, bw, offset;
-+		u8 cch;
-+
-+		int num = sscanf(tmp, "%hhu %hhu %hhu", &ch, &bw, &offset);
-+
-+		if (num < 3)
-+			return count;
-+
-+		cch = rtw_get_center_ch(ch, bw, offset);
-+		dump_txpwr_total_dbm(RTW_DBGDUMP, adapter, bw, cch, ch);
-+	}
-+
-+	return count;
-+}
-+
-+#ifdef CONFIG_RF_POWER_TRIM
-+static int proc_get_kfree_flag(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
-+
-+	RTW_PRINT_SEL(m, "0x%02x\n", kfree_data->flag);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_kfree_flag(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
-+	char tmp[32] = {0};
-+	u8 flag;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhx", &flag);
-+
-+		if (num < 1)
-+			return count;
-+
-+		kfree_data->flag = flag;
-+	}
-+
-+	return count;
-+}
-+
-+static int proc_get_kfree_bb_gain(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
-+	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
-+	u8 i, j;
-+
-+	for (i = 0; i < BB_GAIN_NUM; i++) {
-+
-+			if (i == 0)
-+				_RTW_PRINT_SEL(m, "2G: ");
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+			switch (i) {
-+			case 1:
-+					_RTW_PRINT_SEL(m, "5GLB1: ");
-+					break;
-+			case 2:
-+					_RTW_PRINT_SEL(m, "5GLB2: ");
-+					break;
-+			case 3:
-+					_RTW_PRINT_SEL(m, "5GMB1: ");
-+					break;
-+			case 4:
-+					_RTW_PRINT_SEL(m, "5GMB2: ");
-+					break;
-+			case 5:
-+					_RTW_PRINT_SEL(m, "5GHB: ");
-+					break;
-+		}
-+#endif
-+		for (j = 0; j < hal_spec->rf_reg_path_num; j++)
-+			_RTW_PRINT_SEL(m, "%d ", kfree_data->bb_gain[i][j]);
-+		_RTW_PRINT_SEL(m, "\n");
-+	}
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_kfree_bb_gain(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
-+	char tmp[BB_GAIN_NUM * RF_PATH_MAX] = {0};
-+	u8 chidx;
-+	s8 bb_gain[BB_GAIN_NUM];
-+	char ch_band_Group[6];
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		char *c, *next;
-+		int i = 0;
-+
-+		next = tmp;
-+		c = strsep(&next, " \t");
-+
-+		if (sscanf(c, "%s", ch_band_Group) != 1) {
-+			RTW_INFO("Error Head Format, channel Group select\n,Please input:\t 2G , 5GLB1 , 5GLB2 , 5GMB1 , 5GMB2 , 5GHB\n");
-+			return count;
-+		}
-+		if (strcmp("2G", ch_band_Group) == 0)
-+			chidx = BB_GAIN_2G;
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+		else if (strcmp("5GLB1", ch_band_Group) == 0)
-+			chidx = BB_GAIN_5GLB1;
-+		else if (strcmp("5GLB2", ch_band_Group) == 0)
-+			chidx = BB_GAIN_5GLB2;
-+		else if (strcmp("5GMB1", ch_band_Group) == 0)
-+			chidx = BB_GAIN_5GMB1;
-+		else if (strcmp("5GMB2", ch_band_Group) == 0)
-+			chidx = BB_GAIN_5GMB2;
-+		else if (strcmp("5GHB", ch_band_Group) == 0)
-+			chidx = BB_GAIN_5GHB;
-+#endif /*CONFIG_IEEE80211_BAND_5GHZ*/
-+		else {
-+			RTW_INFO("Error Head Format, channel Group select\n,Please input:\t 2G , 5GLB1 , 5GLB2 , 5GMB1 , 5GMB2 , 5GHB\n");
-+			return count;
-+		}
-+		c = strsep(&next, " \t");
-+
-+		while (c != NULL) {
-+			if (sscanf(c, "%hhx", &bb_gain[i]) != 1)
-+				break;
-+
-+			kfree_data->bb_gain[chidx][i] = bb_gain[i];
-+			RTW_INFO("%s,kfree_data->bb_gain[%d][%d]=%x\n", __func__, chidx, i, kfree_data->bb_gain[chidx][i]);
-+
-+			c = strsep(&next, " \t");
-+			i++;
-+		}
-+
-+	}
-+
-+	return count;
-+
-+}
-+
-+static int proc_get_kfree_thermal(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
-+
-+	_RTW_PRINT_SEL(m, "%d\n", kfree_data->thermal);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_kfree_thermal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter);
-+	char tmp[32] = {0};
-+	s8 thermal;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhd", &thermal);
-+
-+		if (num < 1)
-+			return count;
-+
-+		kfree_data->thermal = thermal;
-+	}
-+
-+	return count;
-+}
-+
-+static ssize_t proc_set_tx_gain_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter;
-+	char tmp[32] = {0};
-+	u8 rf_path;
-+	s8 offset;
-+
-+	adapter = (_adapter *)rtw_netdev_priv(dev);
-+	if (!adapter)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = sscanf(tmp, "%hhu %hhd", &rf_path, &offset);
-+
-+		if (num < 2)
-+			return count;
-+
-+		RTW_INFO("write rf_path:%u tx gain offset:%d\n", rf_path, offset);
-+		rtw_rf_set_tx_gain_offset(adapter, rf_path, offset);
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_RF_POWER_TRIM */
-+
-+#ifdef CONFIG_BT_COEXIST
-+ssize_t proc_set_btinfo_evt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 btinfo[8];
-+
-+	if (count < 6)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		int num = 0;
-+
-+		_rtw_memset(btinfo, 0, 8);
-+
-+		num = sscanf(tmp, "%hhx %hhx %hhx %hhx %hhx %hhx %hhx %hhx"
-+			, &btinfo[0], &btinfo[1], &btinfo[2], &btinfo[3]
-+			, &btinfo[4], &btinfo[5], &btinfo[6], &btinfo[7]);
-+
-+		if (num < 6)
-+			return -EINVAL;
-+
-+		btinfo[1] = num - 2;
-+
-+		rtw_btinfo_cmd(padapter, btinfo, btinfo[1] + 2);
-+	}
-+
-+	return count;
-+}
-+
-+static u8 btreg_read_type = 0;
-+static u16 btreg_read_addr = 0;
-+static int btreg_read_error = 0;
-+static u8 btreg_write_type = 0;
-+static u16 btreg_write_addr = 0;
-+static int btreg_write_error = 0;
-+
-+static u8 *btreg_type[] = {
-+	"rf",
-+	"modem",
-+	"bluewize",
-+	"vendor",
-+	"le"
-+};
-+
-+static int btreg_parse_str(char const *input, u8 *type, u16 *addr, u16 *val)
-+{
-+	u32 num;
-+	u8 str[80] = {0};
-+	u8 t = 0;
-+	u32 a, v;
-+	u8 i, n;
-+
-+
-+	num = sscanf(input, "%s %x %x", str, &a, &v);
-+	if (num < 2) {
-+		RTW_INFO("%s: INVALID input!(%s)\n", __FUNCTION__, input);
-+		return -EINVAL;
-+	}
-+	if ((num < 3) && val) {
-+		RTW_INFO("%s: INVALID input!(%s)\n", __FUNCTION__, input);
-+		return -EINVAL;
-+	}
-+
-+	n = sizeof(btreg_type) / sizeof(btreg_type[0]);
-+	for (i = 0; i < n; i++) {
-+		if (!strcasecmp(str, btreg_type[i])) {
-+			t = i;
-+			break;
-+		}
-+	}
-+	if (i == n) {
-+		RTW_INFO("%s: unknown type(%s)!\n", __FUNCTION__, str);
-+		return -EINVAL;
-+	}
-+
-+	switch (t) {
-+	case 0:
-+		/* RF */
-+		if (a & 0xFFFFFF80) {
-+			RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n",
-+				 __FUNCTION__, a, btreg_type[t], t);
-+			return -EINVAL;
-+		}
-+		break;
-+	case 1:
-+		/* Modem */
-+		if (a & 0xFFFFFE00) {
-+			RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n",
-+				 __FUNCTION__, a, btreg_type[t], t);
-+			return -EINVAL;
-+		}
-+		break;
-+	default:
-+		/* Others(Bluewize, Vendor, LE) */
-+		if (a & 0xFFFFF000) {
-+			RTW_INFO("%s: INVALID address(0x%X) for type %s(%d)!\n",
-+				 __FUNCTION__, a, btreg_type[t], t);
-+			return -EINVAL;
-+		}
-+		break;
-+	}
-+
-+	if (val) {
-+		if (v & 0xFFFF0000) {
-+			RTW_INFO("%s: INVALID value(0x%x)!\n", __FUNCTION__, v);
-+			return -EINVAL;
-+		}
-+		*val = (u16)v;
-+	}
-+
-+	*type = (u8)t;
-+	*addr = (u16)a;
-+
-+	return 0;
-+}
-+
-+int proc_get_btreg_read(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev;
-+	PADAPTER padapter;
-+	u16 ret;
-+	u32 data;
-+
-+
-+	if (btreg_read_error)
-+		return btreg_read_error;
-+
-+	dev = m->private;
-+	padapter = (PADAPTER)rtw_netdev_priv(dev);
-+
-+	ret = rtw_btcoex_btreg_read(padapter, btreg_read_type, btreg_read_addr, &data);
-+	if (CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))
-+		RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X = 0x%08x\n", btreg_type[btreg_read_type], btreg_read_addr, data);
-+	else
-+		RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X read fail. error code = 0x%04x.\n", btreg_type[btreg_read_type], btreg_read_addr, ret);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_btreg_read(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	PADAPTER padapter;
-+	u8 tmp[80] = {0};
-+	u32 num;
-+	int err;
-+
-+
-+	padapter = (PADAPTER)rtw_netdev_priv(dev);
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n",
-+			 FUNC_ADPT_ARG(padapter));
-+		err = -EFAULT;
-+		goto exit;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n",
-+			 FUNC_ADPT_ARG(padapter));
-+		err = -EFAULT;
-+		goto exit;
-+	}
-+
-+	num = count;
-+	if (num > (sizeof(tmp) - 1))
-+		num = (sizeof(tmp) - 1);
-+
-+	if (copy_from_user(tmp, buffer, num)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n",
-+			 FUNC_ADPT_ARG(padapter));
-+		err = -EFAULT;
-+		goto exit;
-+	}
-+	/* [Coverity] sure tmp end with '\0'(string terminal) */
-+	tmp[sizeof(tmp) - 1] = 0;
-+
-+	err = btreg_parse_str(tmp, &btreg_read_type, &btreg_read_addr, NULL);
-+	if (err)
-+		goto exit;
-+
-+	RTW_INFO(FUNC_ADPT_FMT ": addr=(%s)0x%X\n",
-+		FUNC_ADPT_ARG(padapter), btreg_type[btreg_read_type], btreg_read_addr);
-+
-+exit:
-+	btreg_read_error = err;
-+
-+	return count;
-+}
-+
-+int proc_get_btreg_write(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev;
-+	PADAPTER padapter;
-+	u16 ret;
-+	u32 data;
-+
-+
-+	if (btreg_write_error < 0)
-+		return btreg_write_error;
-+	else if (btreg_write_error > 0) {
-+		RTW_PRINT_SEL(m, "BTREG write: (%s)0x%04X write fail. error code = 0x%04x.\n", btreg_type[btreg_write_type], btreg_write_addr, btreg_write_error);
-+		return 0;
-+	}
-+
-+	dev = m->private;
-+	padapter = (PADAPTER)rtw_netdev_priv(dev);
-+
-+	ret = rtw_btcoex_btreg_read(padapter, btreg_write_type, btreg_write_addr, &data);
-+	if (CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))
-+		RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X = 0x%08x\n", btreg_type[btreg_write_type], btreg_write_addr, data);
-+	else
-+		RTW_PRINT_SEL(m, "BTREG read: (%s)0x%04X read fail. error code = 0x%04x.\n", btreg_type[btreg_write_type], btreg_write_addr, ret);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	PADAPTER padapter;
-+	u8 tmp[80] = {0};
-+	u32 num;
-+	u16 val;
-+	u16 ret;
-+	int err;
-+
-+
-+	padapter = (PADAPTER)rtw_netdev_priv(dev);
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n",
-+			 FUNC_ADPT_ARG(padapter));
-+		err = -EFAULT;
-+		goto exit;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n",
-+			 FUNC_ADPT_ARG(padapter));
-+		err = -EFAULT;
-+		goto exit;
-+	}
-+
-+	num = count;
-+	if (num > (sizeof(tmp) - 1))
-+		num = (sizeof(tmp) - 1);
-+
-+	if (copy_from_user(tmp, buffer, num)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n",
-+			 FUNC_ADPT_ARG(padapter));
-+		err = -EFAULT;
-+		goto exit;
-+	}
-+
-+	err = btreg_parse_str(tmp, &btreg_write_type, &btreg_write_addr, &val);
-+	if (err)
-+		goto exit;
-+
-+	RTW_INFO(FUNC_ADPT_FMT ": Set (%s)0x%X = 0x%x\n",
-+		FUNC_ADPT_ARG(padapter), btreg_type[btreg_write_type], btreg_write_addr, val);
-+
-+	ret = rtw_btcoex_btreg_write(padapter, btreg_write_type, btreg_write_addr, val);
-+	if (!CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS))
-+		err = ret;
-+
-+exit:
-+	btreg_write_error = err;
-+
-+	return count;
-+}
-+
-+int proc_get_btc_reduce_wl_txpwr(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev;
-+	PADAPTER padapter;
-+	u8 data;
-+
-+	dev = m->private;
-+	padapter = (PADAPTER)rtw_netdev_priv(dev);
-+
-+	data = rtw_btcoex_get_reduce_wl_txpwr(padapter);
-+	RTW_PRINT_SEL(m, "BTC reduce WL TxPwr = %d dB\n", data);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_btc_reduce_wl_txpwr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	PADAPTER padapter;
-+	HAL_DATA_TYPE *hal_data;
-+	u8 tmp[80] = {0};
-+	u32 val = 0;
-+	u32 num;
-+
-+	padapter = (PADAPTER)rtw_netdev_priv(dev);
-+	hal_data = GET_HAL_DATA(padapter);
-+
-+	/*	RTW_INFO("+" FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(padapter)); */
-+
-+	if (NULL == buffer) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n",
-+			 FUNC_ADPT_ARG(padapter));
-+
-+		return -EFAULT;
-+	}
-+
-+	if (count < 1) {
-+		RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n",
-+			 FUNC_ADPT_ARG(padapter));
-+
-+		return -EFAULT;
-+	}
-+
-+	num = count;
-+	if (num > (sizeof(tmp) - 1))
-+		num = (sizeof(tmp) - 1);
-+
-+	if (copy_from_user(tmp, buffer, num)) {
-+		RTW_INFO(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n",
-+			 FUNC_ADPT_ARG(padapter));
-+
-+		return -EFAULT;
-+	}
-+
-+	num = sscanf(tmp, "%d", &val);
-+
-+	if ((IS_HARDWARE_TYPE_8822C(padapter)) && (hal_data->EEPROMBluetoothCoexist == _TRUE))
-+		rtw_btc_reduce_wl_txpwr_cmd(padapter, val);
-+
-+	return count;
-+}
-+
-+#endif /* CONFIG_BT_COEXIST */
-+
-+#ifdef CONFIG_MBSSID_CAM
-+int proc_get_mbid_cam_cache(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	rtw_mbid_cam_cache_dump(m, __func__, adapter);
-+	rtw_mbid_cam_dump(m, __func__, adapter);
-+	return 0;
-+}
-+#endif /* CONFIG_MBSSID_CAM */
-+
-+int proc_get_mac_addr(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	rtw_hal_dump_macaddr(m, adapter);
-+	return 0;
-+}
-+
-+static int proc_get_skip_band(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	int bandskip;
-+
-+	bandskip = RTW_GET_SCAN_BAND_SKIP(adapter);
-+	RTW_PRINT_SEL(m, "bandskip:0x%02x\n", bandskip);
-+	return 0;
-+}
-+
-+static ssize_t proc_set_skip_band(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[6];
-+	u8 skip_band;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu", &skip_band);
-+
-+		if (num < 1)
-+			return -EINVAL;
-+
-+		if (1 == skip_band)
-+			RTW_SET_SCAN_BAND_SKIP(padapter, BAND_24G);
-+		else if (2 == skip_band)
-+			RTW_SET_SCAN_BAND_SKIP(padapter, BAND_5G);
-+		else if (3 == skip_band)
-+			RTW_CLR_SCAN_BAND_SKIP(padapter, BAND_24G);
-+		else if (4 == skip_band)
-+			RTW_CLR_SCAN_BAND_SKIP(padapter, BAND_5G);
-+	}
-+	return count;
-+
-+}
-+
-+#ifdef CONFIG_RTW_ACS
-+static int proc_get_chan_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	rtw_acs_chan_info_dump(m, adapter);
-+	return 0;
-+}
-+
-+static int proc_get_best_chan(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (IS_ACS_ENABLE(adapter))
-+		rtw_acs_info_dump(m, adapter);
-+	else
-+		_RTW_PRINT_SEL(m,"ACS disabled\n");
-+	return 0;
-+}
-+
-+static ssize_t proc_set_acs(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+#ifdef CONFIG_RTW_ACS_DBG
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 acs_state = 0;
-+	u16 scan_ch_ms= 0, acs_scan_ch_ms = 0;
-+	u8 scan_type = SCAN_ACTIVE, igi= 0, bw = 0;
-+	u8 acs_scan_type = SCAN_ACTIVE, acs_igi= 0, acs_bw = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu %hhu %hu %hhx %hhu",
-+			&acs_state, &scan_type, &scan_ch_ms, &igi, &bw);
-+
-+		if (num < 1)
-+			return -EINVAL;
-+
-+		if (acs_state)
-+			rtw_acs_start(padapter);
-+		else
-+			rtw_acs_stop(padapter);
-+		num = num -1;
-+
-+		if(num) {
-+			if (num-- > 0)
-+				acs_scan_type = scan_type;
-+			if (num-- > 0)
-+				acs_scan_ch_ms = scan_ch_ms;
-+			if (num-- > 0)
-+				acs_igi = igi;
-+			if (num-- > 0)
-+				acs_bw = bw;
-+			rtw_acs_adv_setting(padapter, acs_scan_type, acs_scan_ch_ms, acs_igi, acs_bw);
-+		}
-+	}
-+#endif /*CONFIG_RTW_ACS_DBG*/
-+	return count;
-+}
-+#endif /*CONFIG_RTW_ACS*/
-+
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+static int proc_get_nm(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	rtw_noise_info_dump(m, adapter);
-+	return 0;
-+}
-+
-+static ssize_t proc_set_nm(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 nm_state = 0;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu", &nm_state);
-+
-+		if (num < 1)
-+			return -EINVAL;
-+
-+		if (nm_state)
-+			rtw_nm_enable(padapter);
-+		else
-+			rtw_nm_disable(padapter);
-+
-+	}
-+	return count;
-+}
-+#endif /*CONFIG_RTW_ACS*/
-+
-+static int proc_get_hal_spec(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_hal_spec(m, adapter);
-+	return 0;
-+}
-+
-+static int proc_get_hal_trx_mode(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+
-+	dump_hal_trx_mode(m, adapter);
-+	return 0;
-+}
-+
-+static int proc_get_phy_cap(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	rtw_dump_phy_cap(m, adapter);
-+#ifdef CONFIG_80211N_HT
-+	rtw_dump_drv_phy_cap(m, adapter);
-+	rtw_get_dft_phy_cap(m, adapter);
-+#endif /* CONFIG_80211N_HT */
-+	return 0;
-+}
-+
-+#ifdef CONFIG_SUPPORT_TRX_SHARED
-+#include "../../hal/hal_halmac.h"
-+static int proc_get_trx_share_mode(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_trx_share_mode(m, adapter);
-+	return 0;
-+}
-+#endif
-+
-+static int proc_dump_rsvd_page(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	rtw_dump_rsvd_page(m, adapter, adapter->rsvd_page_offset, adapter->rsvd_page_num);
-+	return 0;
-+}
-+static ssize_t proc_set_rsvd_page_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 page_offset, page_num;
-+
-+	if (count < 2)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu %hhu", &page_offset, &page_num);
-+
-+		if (num < 2)
-+			return -EINVAL;
-+		padapter->rsvd_page_offset = page_offset;
-+		padapter->rsvd_page_num = page_num;
-+	}
-+	return count;
-+}
-+
-+#ifdef CONFIG_SUPPORT_FIFO_DUMP
-+static int proc_dump_fifo(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	rtw_dump_fifo(m, adapter, adapter->fifo_sel, adapter->fifo_addr, adapter->fifo_size);
-+	return 0;
-+}
-+static ssize_t proc_set_fifo_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u8 fifo_sel = 0;
-+	u32 fifo_addr = 0;
-+	u32 fifo_size = 0;
-+
-+	if (count < 3)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%hhu %x %d", &fifo_sel, &fifo_addr, &fifo_size);
-+
-+		if (num < 3)
-+			return -EINVAL;
-+
-+		padapter->fifo_sel = fifo_sel;
-+		padapter->fifo_addr = fifo_addr;
-+		padapter->fifo_size = fifo_size;
-+	}
-+	return count;
-+}
-+#endif
-+
-+#ifdef CONFIG_WOW_PATTERN_HW_CAM
-+int proc_dump_pattern_cam(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	int i;
-+	struct  rtl_wow_pattern context;
-+
-+	for (i = 0 ; i < pwrpriv->wowlan_pattern_idx; i++) {
-+		rtw_wow_pattern_read_cam_ent(padapter, i, &context);
-+		rtw_dump_wow_pattern(m, &context, i);
-+	}
-+
-+	return 0;
-+}
-+#endif
-+
-+static int proc_get_napi_info(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv *pregistrypriv = &adapter->registrypriv;
-+	u8 napi = 0, gro = 0;
-+	u32 weight = 0;
-+	struct dvobj_priv *d;
-+	d = adapter_to_dvobj(adapter);
-+
-+
-+#ifdef CONFIG_RTW_NAPI
-+	if (pregistrypriv->en_napi) {
-+		napi = 1;
-+		weight = RTL_NAPI_WEIGHT;
-+	}
-+
-+#ifdef CONFIG_RTW_GRO
-+	if (pregistrypriv->en_gro)
-+		gro = 1;
-+#endif /* CONFIG_RTW_GRO */
-+#endif /* CONFIG_RTW_NAPI */
-+
-+	if (napi) {
-+		RTW_PRINT_SEL(m, "NAPI enable, weight=%d\n", weight);
-+#ifdef CONFIG_RTW_NAPI_DYNAMIC
-+		RTW_PRINT_SEL(m, "Dynamaic NAPI mechanism is on, current NAPI %s\n",
-+			      d->en_napi_dynamic ? "enable" : "disable");
-+		RTW_PRINT_SEL(m, "Dynamaic NAPI info:\n"
-+				 "\ttcp_rx_threshold = %d Mbps\n"
-+				 "\tcur_rx_tp = %d Mbps\n",
-+			      pregistrypriv->napi_threshold,
-+			      d->traffic_stat.cur_rx_tp);
-+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
-+	} else {
-+		RTW_PRINT_SEL(m, "NAPI disable\n");
-+	}
-+	RTW_PRINT_SEL(m, "GRO %s\n", gro?"enable":"disable");
-+
-+	return 0;
-+
-+}
-+
-+#ifdef CONFIG_RTW_NAPI_DYNAMIC
-+static ssize_t proc_set_napi_th(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	struct _ADAPTER *adapter = (struct _ADAPTER *)rtw_netdev_priv(dev);
-+	struct registry_priv *registry = &adapter->registrypriv;
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	PADAPTER iface = NULL;
-+	char tmp[32] = {0};
-+	int thrshld = 0;
-+	int num = 0, i = 0;
-+
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	RTW_INFO("%s: Last threshold = %d Mbps\n", __FUNCTION__, registry->napi_threshold);
-+
-+
-+	for (i = 0; i < dvobj->iface_nums; i++) {
-+		iface = dvobj->padapters[i];
-+		if (iface) {
-+			if (buffer && !copy_from_user(tmp, buffer, count)) {
-+				registry = &iface->registrypriv;
-+				num = sscanf(tmp, "%d", &thrshld);
-+				if (num > 0) {
-+					if (thrshld > 0)
-+						registry->napi_threshold = thrshld;
-+				}
-+			}
-+		}
-+	}
-+	RTW_INFO("%s: New threshold = %d Mbps\n", __FUNCTION__, registry->napi_threshold);
-+	RTW_INFO("%s: Current RX throughput = %d Mbps\n",
-+		 __FUNCTION__, adapter_to_dvobj(adapter)->traffic_stat.cur_rx_tp);
-+
-+	return count;
-+}
-+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
-+
-+
-+ssize_t proc_set_dynamic_agg_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	int enable = 0, i = 0;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-+		PADAPTER iface = NULL;
-+		int num = sscanf(tmp, "%d", &enable);
-+
-+		if (num !=  1) {
-+			RTW_INFO("invalid parameter!\n");
-+			return count;
-+		}
-+
-+		RTW_INFO("dynamic_agg_enable:%d\n", enable);
-+
-+		for (i = 0; i < dvobj->iface_nums; i++) {
-+			iface = dvobj->padapters[i];
-+			if (iface)
-+				iface->registrypriv.dynamic_agg_enable = enable;
-+		}
-+
-+	}
-+
-+	return count;
-+
-+}
-+
-+static int proc_get_dynamic_agg_enable(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv *pregistrypriv = &adapter->registrypriv;
-+
-+	RTW_PRINT_SEL(m, "dynamic_agg_enable:%d\n", pregistrypriv->dynamic_agg_enable);
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_RTW_WDS
-+static int proc_get_wds_en(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+
-+	if (MLME_STATE(adapter) & (WIFI_AP_STATE | WIFI_STATION_STATE))
-+		RTW_PRINT_SEL(m, "%d\n", adapter_use_wds(adapter));
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_wds_en(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	char tmp[32];
-+
-+	if (!(MLME_STATE(adapter) & (WIFI_AP_STATE | WIFI_STATION_STATE)))
-+		return -EFAULT;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		u8 enable;
-+		int num = sscanf(tmp, "%hhu", &enable);
-+
-+		if (num >= 1)
-+			adapter_set_use_wds(adapter, enable);
-+	}
-+
-+	return count;
-+}
-+
-+static ssize_t proc_set_sta_wds_en(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		u8 enable;
-+		u8 addr[ETH_ALEN];
-+		struct sta_info *sta;
-+		int num = sscanf(tmp, "%hhu "MAC_SFMT, &enable, MAC_SARG(addr));
-+
-+		if (num != 7)
-+			return -EINVAL;
-+
-+		if (IS_MCAST(addr) || _rtw_memcmp(adapter_mac_addr(adapter), addr, ETH_ALEN))
-+			return -EINVAL;
-+
-+		sta = rtw_get_stainfo(&adapter->stapriv, addr);
-+		if (!sta)
-+			return -EINVAL;
-+
-+		if (enable)
-+			sta->flags |= WLAN_STA_WDS;
-+		else
-+			sta->flags &= ~WLAN_STA_WDS;
-+	}
-+
-+	return count;
-+}
-+
-+static int proc_get_wds_gptr(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_STA(adapter) && MLME_IS_ASOC(adapter))
-+		dump_wgptr(m, adapter);
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_AP_MODE
-+static int proc_get_wds_path(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_AP(adapter) && MLME_IS_ASOC(adapter))
-+		dump_wpath(m, adapter);
-+
-+	return 0;
-+}
-+#endif /* CONFIG_AP_MODE */
-+#endif /* CONFIG_RTW_WDS */
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+static int proc_get_multi_ap_opmode(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+
-+	if (MLME_STATE(adapter) & (WIFI_AP_STATE | WIFI_STATION_STATE))
-+		RTW_PRINT_SEL(m, "0x%02x\n", adapter->multi_ap);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_multi_ap_opmode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	char tmp[32];
-+
-+	if (!(MLME_STATE(adapter) & (WIFI_AP_STATE | WIFI_STATION_STATE)))
-+		return -EFAULT;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		u8 mode;
-+		int num = sscanf(tmp, "%hhx", &mode);
-+
-+		if (num >= 1) {
-+			if (MLME_IS_AP(adapter))
-+				adapter->multi_ap = mode & (MULTI_AP_FRONTHAUL_BSS | MULTI_AP_BACKHAUL_BSS);
-+			else
-+				adapter->multi_ap = mode & MULTI_AP_BACKHAUL_STA;
-+			if (adapter->multi_ap & (MULTI_AP_BACKHAUL_BSS | MULTI_AP_BACKHAUL_STA))
-+				adapter_set_use_wds(adapter, 1);
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+static int proc_get_unassoc_sta(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = GET_PRIMARY_ADAPTER(rtw_netdev_priv(dev));
-+
-+	dump_unassoc_sta(m, adapter);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_unassoc_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = GET_PRIMARY_ADAPTER(rtw_netdev_priv(dev));
-+	char tmp[17 * 10 + 32] = {0};
-+	char cmd[32];
-+	u8 mode;
-+	u8 stype = 0;
-+	u8 addr[ETH_ALEN];
-+
-+#define UNASOC_STA_CMD_MODE	0
-+#define UNASOC_STA_CMD_ADD	1
-+#define UNASOC_STA_CMD_DEL	2
-+#define UNASOC_STA_CMD_CLR	3
-+#define UNASOC_STA_CMD_UNINT	4
-+#define UNASOC_STA_CMD_NUM	5
-+
-+	static const char * const unasoc_sta_cmd_str[] = {
-+		"mode",
-+		"add",
-+		"del",
-+		"clr",
-+		"uninterest",
-+	};
-+	u8 cmd_id = UNASOC_STA_CMD_NUM;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		RTW_WARN(FUNC_ADPT_FMT" input string too long\n", FUNC_ADPT_ARG(adapter));
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		/*
-+		* mode <stype>,<mode>
-+		* add <macaddr> [<macaddr>]
-+		* del <macaddr> [<macaddr>]
-+		* clr
-+		*/
-+		char *c, *next;
-+		int i;
-+		u8 is_bcast;
-+
-+		next = tmp;
-+		c = strsep(&next, " \t");
-+		if (!c || sscanf(c, "%s", cmd) != 1)
-+			goto exit;
-+
-+		for (i = 0; i < UNASOC_STA_CMD_NUM; i++)
-+			if (strcmp(unasoc_sta_cmd_str[i], cmd) == 0)
-+				cmd_id = i;
-+
-+		switch (cmd_id) {
-+		case UNASOC_STA_CMD_MODE:
-+			c = strsep(&next, " \t");
-+			if (!c || sscanf(c, "%hhu,%hhu", &stype, &mode) != 2) {
-+				RTW_WARN(FUNC_ADPT_FMT" invalid arguments of mode cmd\n", FUNC_ADPT_ARG(adapter));
-+				goto exit;
-+			}
-+			if (stype >= UNASOC_STA_SRC_NUM) {
-+				RTW_WARN(FUNC_ADPT_FMT" invalid stype:%u\n", FUNC_ADPT_ARG(adapter), stype);
-+				goto exit;
-+			}
-+			if (mode >= UNASOC_STA_MODE_NUM) {
-+				RTW_WARN(FUNC_ADPT_FMT" invalid mode:%u\n", FUNC_ADPT_ARG(adapter), mode);
-+				goto exit;
-+			}
-+			rtw_unassoc_sta_set_mode(adapter, stype, mode);
-+			break;
-+
-+		case UNASOC_STA_CMD_ADD:
-+		case UNASOC_STA_CMD_DEL:
-+		case UNASOC_STA_CMD_UNINT:
-+			/* check for macaddr list */
-+			c = strsep(&next, " \t");
-+			while (c != NULL) {
-+				if (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6)
-+					break;
-+
-+				is_bcast = is_broadcast_mac_addr(addr);
-+				if (is_bcast
-+					|| rtw_check_invalid_mac_address(addr, 0) == _FALSE
-+				) {
-+					if (cmd_id == UNASOC_STA_CMD_DEL) {
-+						if (is_bcast) {
-+							rtw_del_unassoc_sta_queue(adapter);
-+							break;
-+						} else
-+							rtw_del_unassoc_sta(adapter, addr);
-+					} else if (cmd_id == UNASOC_STA_CMD_UNINT) {
-+						if (is_bcast) {
-+							rtw_undo_all_interested_unassoc_sta(adapter);
-+							break;
-+						} else
-+							rtw_undo_interested_unassoc_sta(adapter, addr);
-+					} else if (!is_bcast)
-+					 	rtw_add_interested_unassoc_sta(adapter, addr);
-+				}
-+
-+				c = strsep(&next, " \t");
-+			}
-+			break;
-+
-+		case UNASOC_STA_CMD_CLR:
-+			/* clear sta list */
-+			rtw_del_unassoc_sta_queue(adapter);
-+			goto exit;
-+
-+		default:
-+			RTW_WARN(FUNC_ADPT_FMT" invalid cmd:\"%s\"\n", FUNC_ADPT_ARG(adapter), cmd);
-+			goto exit;
-+		}
-+	}
-+
-+exit:
-+	return count;
-+}
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+static u8 assoc_req_mac_addr[6];
-+int proc_get_sta_assoc_req_frame_body(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_AP(adapter)) {
-+		struct sta_info *psta;
-+		_irqL irqL;
-+		u8 *passoc_req = NULL;
-+		u32 assoc_req_len = 0;
-+
-+		psta = rtw_get_stainfo(&adapter->stapriv, assoc_req_mac_addr);
-+		if (psta == NULL) {
-+			RTW_PRINT(FUNC_ADPT_FMT" sta("MAC_FMT") not found\n",
-+				  FUNC_ADPT_ARG(adapter), MAC_ARG(assoc_req_mac_addr));
-+			return 0;
-+		}
-+		RTW_PRINT(FUNC_ADPT_FMT" sta("MAC_FMT") found\n",
-+			  FUNC_ADPT_ARG(adapter), MAC_ARG(assoc_req_mac_addr));
-+		_enter_critical_bh(&psta->lock, &irqL);
-+		if (psta->passoc_req && psta->assoc_req_len > 0) {
-+			passoc_req = rtw_zmalloc(psta->assoc_req_len);
-+			if (passoc_req) {
-+				assoc_req_len = psta->assoc_req_len;
-+				_rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len);
-+			}
-+		}
-+		_exit_critical_bh(&psta->lock, &irqL);
-+		if (passoc_req && assoc_req_len > IEEE80211_3ADDR_LEN) {
-+			u8 *body = passoc_req + IEEE80211_3ADDR_LEN;
-+			u32 body_len = assoc_req_len - IEEE80211_3ADDR_LEN;
-+			u16 i;
-+
-+			for (i = 0; i < body_len; i++)
-+				_RTW_PRINT_SEL(m, "%02X", body[i]);
-+			_RTW_PRINT_SEL(m, "\n");
-+		}
-+		if (passoc_req && assoc_req_len > 0)
-+			rtw_mfree(passoc_req, assoc_req_len);
-+	}
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_sta_assoc_req_frame_body(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[18] = {0};
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		if (sscanf(tmp, MAC_SFMT, MAC_SARG(assoc_req_mac_addr)) != 6) {
-+			_rtw_memset(assoc_req_mac_addr, 0, 6);
-+			RTW_PRINT(FUNC_ADPT_FMT" Invalid format\n",
-+				  FUNC_ADPT_ARG(adapter));
-+		}
-+
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_IOCTL_CFG80211 */
-+
-+static int proc_get_ch_util_threshold(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = GET_PRIMARY_ADAPTER(rtw_netdev_priv(dev));
-+
-+	RTW_PRINT_SEL(m, "%hhu\n", adapter->ch_util_threshold);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_ch_util_threshold(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = GET_PRIMARY_ADAPTER(rtw_netdev_priv(dev));
-+	char tmp[4];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		u8 threshold;
-+		int num = sscanf(tmp, "%hhu", &threshold);
-+
-+		if (num == 1)
-+			adapter->ch_util_threshold = threshold;
-+	}
-+
-+	return count;
-+}
-+
-+static int proc_get_ch_utilization(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	RTW_PRINT_SEL(m, "%hhu\n", rtw_get_ch_utilization(adapter));
-+
-+	return 0;
-+}
-+#endif /* CONFIG_RTW_MULTI_AP */
-+
-+#ifdef CONFIG_RTW_MESH
-+static int proc_get_mesh_peer_sel_policy(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_mesh_peer_sel_policy(m, adapter);
-+
-+	return 0;
-+}
-+
-+#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+static int proc_get_mesh_acnode_prevent(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_MESH(adapter))
-+		dump_mesh_acnode_prevent_settings(m, adapter);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_mesh_acnode_prevent(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
-+		u8 enable;
-+		u32 conf_timeout_ms;
-+		u32 notify_timeout_ms;
-+		int num = sscanf(tmp, "%hhu %u %u", &enable, &conf_timeout_ms, &notify_timeout_ms);
-+
-+		if (num >= 1)
-+			peer_sel_policy->acnode_prevent = enable;
-+		if (num >= 2)
-+			peer_sel_policy->acnode_conf_timeout_ms = conf_timeout_ms;
-+		if (num >= 3)
-+			peer_sel_policy->acnode_notify_timeout_ms = notify_timeout_ms;
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_RTW_MESH_ACNODE_PREVENT */
-+
-+#if CONFIG_RTW_MESH_OFFCH_CAND
-+static int proc_get_mesh_offch_cand(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_MESH(adapter))
-+		dump_mesh_offch_cand_settings(m, adapter);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_mesh_offch_cand(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
-+		u8 enable;
-+		u32 find_int_ms;
-+		int num = sscanf(tmp, "%hhu %u", &enable, &find_int_ms);
-+
-+		if (num >= 1)
-+			peer_sel_policy->offch_cand = enable;
-+		if (num >= 2)
-+			peer_sel_policy->offch_find_int_ms = find_int_ms;
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_RTW_MESH_OFFCH_CAND */
-+
-+#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+static int proc_get_mesh_peer_blacklist(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_MESH(adapter)) {
-+		dump_mesh_peer_blacklist_settings(m, adapter);
-+		if (MLME_IS_ASOC(adapter))
-+			dump_mesh_peer_blacklist(m, adapter);
-+	}
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_mesh_peer_blacklist(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
-+		u32 conf_timeout_ms;
-+		u32 blacklist_timeout_ms;
-+		int num = sscanf(tmp, "%u %u", &conf_timeout_ms, &blacklist_timeout_ms);
-+
-+		if (num >= 1)
-+			peer_sel_policy->peer_conf_timeout_ms = conf_timeout_ms;
-+		if (num >= 2)
-+			peer_sel_policy->peer_blacklist_timeout_ms = blacklist_timeout_ms;
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */
-+
-+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+static int proc_get_mesh_cto_mgate_require(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_MESH(adapter))
-+		RTW_PRINT_SEL(m, "%u\n", adapter->mesh_cfg.peer_sel_policy.cto_mgate_require);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_mesh_cto_mgate_require(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
-+		u8 require;
-+		int num = sscanf(tmp, "%hhu", &require);
-+
-+		if (num >= 1) {
-+			peer_sel_policy->cto_mgate_require = require;
-+			#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER
-+			if (rtw_mesh_cto_mgate_required(adapter))
-+				rtw_netif_carrier_off(adapter->pnetdev);
-+			else
-+				rtw_netif_carrier_on(adapter->pnetdev);
-+			#endif
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+static int proc_get_mesh_cto_mgate_blacklist(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_MESH(adapter)) {
-+		dump_mesh_cto_mgate_blacklist_settings(m, adapter);
-+		if (MLME_IS_ASOC(adapter))
-+			dump_mesh_cto_mgate_blacklist(m, adapter);
-+	}
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_mesh_cto_mgate_blacklist(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
-+		u32 conf_timeout_ms;
-+		u32 blacklist_timeout_ms;
-+		int num = sscanf(tmp, "%u %u", &conf_timeout_ms, &blacklist_timeout_ms);
-+
-+		if (num >= 1)
-+			peer_sel_policy->cto_mgate_conf_timeout_ms = conf_timeout_ms;
-+		if (num >= 2)
-+			peer_sel_policy->cto_mgate_blacklist_timeout_ms = blacklist_timeout_ms;
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
-+
-+static int proc_get_mesh_networks(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	dump_mesh_networks(m, adapter);
-+
-+	return 0;
-+}
-+
-+static int proc_get_mesh_plink_ctl(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_MESH(adapter))
-+		dump_mesh_plink_ctl(m, adapter);
-+
-+	return 0;
-+}
-+
-+static int proc_get_mesh_mpath(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))
-+		dump_mpath(m, adapter);
-+
-+	return 0;
-+}
-+
-+static int proc_get_mesh_mpp(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))
-+		dump_mpp(m, adapter);
-+
-+	return 0;
-+}
-+
-+static int proc_get_mesh_known_gates(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_MESH(adapter))
-+		dump_known_gates(m, adapter);
-+
-+	return 0;
-+}
-+
-+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+static int proc_get_mesh_b2u_flags(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_MESH(adapter))
-+		dump_mesh_b2u_flags(m, adapter);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_mesh_b2u_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+		u8 msrc, mfwd;
-+		int num = sscanf(tmp, "%hhx %hhx", &msrc, &mfwd);
-+
-+		if (num >= 1)
-+			mcfg->b2u_flags_msrc = msrc;
-+		if (num >= 2)
-+			mcfg->b2u_flags_mfwd = mfwd;
-+	}
-+
-+	return count;
-+}
-+#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */
-+
-+static int proc_get_mesh_stats(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_MESH(adapter))
-+		dump_mesh_stats(m, adapter);
-+
-+	return 0;
-+}
-+
-+static int proc_get_mesh_gate_timeout(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	if (MLME_IS_MESH(adapter))
-+		RTW_PRINT_SEL(m, "%u factor\n",
-+			       adapter->mesh_cfg.path_gate_timeout_factor);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_mesh_gate_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+		u32 timeout;
-+		int num = sscanf(tmp, "%u", &timeout);
-+
-+		if (num < 1)
-+			goto exit;
-+
-+		mcfg->path_gate_timeout_factor = timeout;
-+	}
-+
-+exit:
-+	return count;
-+}
-+
-+static int proc_get_mesh_gate_state(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
-+	u8 cto_mgate = 0;
-+
-+	if (MLME_IS_MESH(adapter)) {
-+		if (rtw_mesh_is_primary_gate(adapter))
-+			RTW_PRINT_SEL(m, "PG\n");
-+		else if (mcfg->dot11MeshGateAnnouncementProtocol)
-+			RTW_PRINT_SEL(m, "G\n");
-+		else if (rtw_mesh_gate_num(adapter))
-+			RTW_PRINT_SEL(m, "C\n");
-+		else
-+			RTW_PRINT_SEL(m, "N\n");
-+	}
-+
-+	return 0;
-+}
-+
-+static int proc_get_peer_alive_based_preq(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	struct _ADAPTER *adapter= (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv  *rp = &adapter->registrypriv;
-+
-+	RTW_PRINT_SEL(m, "peer_alive_based_preq = %u\n",
-+		      rp->peer_alive_based_preq);
-+
-+	return 0;
-+}
-+
-+static ssize_t
-+proc_set_peer_alive_based_preq(struct file *file, const char __user *buffer,
-+			       size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	struct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct registry_priv  *rp = &adapter->registrypriv;
-+	char tmp[8];
-+	int num = 0;
-+	u8 enable = 0;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (!buffer || copy_from_user(tmp, buffer, count))
-+		goto exit;
-+
-+	num = sscanf(tmp, "%hhu", &enable);
-+	if (num !=  1) {
-+		RTW_ERR("%s: invalid parameter!\n", __FUNCTION__);
-+		goto exit;
-+	}
-+
-+	if (enable > 1) {
-+		RTW_ERR("%s: invalid value!\n", __FUNCTION__);
-+		goto exit;
-+	}
-+	rp->peer_alive_based_preq = enable;
-+
-+exit:
-+	return count;
-+}
-+#endif /* CONFIG_RTW_MESH */
-+
-+#ifdef RTW_BUSY_DENY_SCAN
-+static int proc_get_scan_interval_thr(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	struct _ADAPTER *adapter= (struct _ADAPTER *)rtw_netdev_priv(dev);
-+	struct registry_priv *rp = &adapter->registrypriv;
-+
-+
-+	RTW_PRINT_SEL(m, "scan interval threshold = %u ms\n",
-+		      rp->scan_interval_thr);
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_scan_interval_thr(struct file *file,
-+				          const char __user *buffer,
-+				          size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	struct _ADAPTER *adapter= (struct _ADAPTER *)rtw_netdev_priv(dev);
-+	struct registry_priv *rp = &adapter->registrypriv;
-+	char tmp[12];
-+	int num = 0;
-+	u32 thr = 0;
-+
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (!buffer || copy_from_user(tmp, buffer, count))
-+		goto exit;
-+
-+	num = sscanf(tmp, "%u", &thr);
-+	if (num != 1) {
-+		RTW_ERR("%s: invalid parameter!\n", __FUNCTION__);
-+		goto exit;
-+	}
-+
-+	rp->scan_interval_thr = thr;
-+
-+	RTW_PRINT("%s: scan interval threshold = %u ms\n",
-+		  __FUNCTION__, rp->scan_interval_thr);
-+
-+exit:
-+	return count;
-+}
-+
-+#endif /* RTW_BUSY_DENY_SCAN */
-+
-+static int proc_get_scan_deny(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	struct _ADAPTER *adapter= (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	RTW_PRINT_SEL(m, "scan_deny is %s\n", (dvobj->scan_deny == _TRUE) ? "enable":"disable");
-+
-+	return 0;
-+}
-+
-+static ssize_t proc_set_scan_deny(struct file *file, const char __user *buffer,
-+				size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	struct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	char tmp[8];
-+	int num = 0;
-+	int enable = 0;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (!buffer || copy_from_user(tmp, buffer, count))
-+		goto exit;
-+
-+	num = sscanf(tmp, "%d", &enable);
-+	if (num !=  1) {
-+		RTW_ERR("%s: invalid parameter!\n", __FUNCTION__);
-+		goto exit;
-+	}
-+
-+	dvobj->scan_deny = enable ? _TRUE : _FALSE;
-+
-+	RTW_PRINT("%s: scan_deny is %s\n",
-+		  __FUNCTION__, (dvobj->scan_deny == _TRUE) ? "enable":"disable");
-+
-+exit:
-+	return count;
-+}
-+
-+#ifdef CONFIG_RTW_TPT_MODE
-+static int proc_get_tpt_mode(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	struct _ADAPTER *adapter= (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	RTW_PRINT_SEL(m, "current tpt_mode = %d\n", dvobj->tpt_mode);
-+
-+	return 0;
-+}
-+
-+static void tpt_mode_default(struct _ADAPTER *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	/* 1. disable scan deny */
-+	dvobj->scan_deny = _FALSE;
-+
-+	/* 2. back to original LPS mode */
-+#ifdef CONFIG_LPS
-+	rtw_pm_set_lps(adapter, adapter->registrypriv.power_mgnt);
-+#endif
-+
-+	/* 3. back to original 2.4 tx bw mode */
-+	rtw_set_tx_bw_mode(adapter, adapter->registrypriv.tx_bw_mode);
-+}
-+
-+static void rtw_tpt_mode(struct _ADAPTER *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+
-+	if (dvobj->tpt_mode > 0) {
-+
-+		/* when enable each tpt mode
-+			1. scan deny
-+			2. disable LPS */
-+
-+		dvobj->scan_deny = _TRUE;
-+
-+#ifdef CONFIG_LPS
-+		rtw_pm_set_lps(adapter, PS_MODE_ACTIVE);
-+#endif
-+
-+	}
-+
-+	switch (dvobj->tpt_mode) {
-+		case 0: /* default mode */
-+			tpt_mode_default(adapter);
-+			break;
-+		case 1: /* High TP*/
-+			/*tpt_mode1(adapter);*/
-+			dvobj->edca_be_ul = 0x5e431c;
-+			dvobj->edca_be_dl = 0x00431c;
-+			break;
-+		case 2: /* noise */
-+			/* tpt_mode2(adapter); */
-+			dvobj->edca_be_ul = 0x00431c;
-+			dvobj->edca_be_dl = 0x00431c;
-+
-+			rtw_set_tx_bw_mode(adapter, 0x20); /* for 2.4g, fixed tx_bw_mode to 20Mhz */
-+			break;
-+		case 3: /* long distance */
-+			/* tpt_mode3(adapter); */
-+			dvobj->edca_be_ul = 0x00431c;
-+			dvobj->edca_be_dl = 0x00431c;
-+
-+			rtw_set_tx_bw_mode(adapter, 0x20); /* for 2.4g, fixed tx_bw_mode to 20Mhz */
-+			break;
-+		case 4: /* noise + long distance */
-+			/* tpt_mode4(adapter); */
-+			dvobj->edca_be_ul = 0x00431c;
-+			dvobj->edca_be_dl = 0x00431c;
-+
-+			rtw_set_tx_bw_mode(adapter, 0x20); /* for 2.4g, fixed tx_bw_mode to 20Mhz */
-+			break;
-+		default: /* default mode */
-+			tpt_mode_default(adapter);
-+			break;
-+	}
-+
-+}
-+
-+static ssize_t proc_set_tpt_mode(struct file *file, const char __user *buffer,
-+				size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	struct _ADAPTER *adapter = (_adapter *)rtw_netdev_priv(dev);
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	char tmp[32];
-+	int num = 0;
-+	int mode = 0;
-+
-+#define MAX_TPT_MODE_NUM 4
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (!buffer || copy_from_user(tmp, buffer, count))
-+		goto exit;
-+
-+	num = sscanf(tmp, "%d", &mode);
-+	if (num !=  1) {
-+		RTW_ERR("%s: invalid parameter!\n", __FUNCTION__);
-+		goto exit;
-+	}
-+
-+	if (mode > MAX_TPT_MODE_NUM )
-+		mode = 0;
-+
-+	RTW_PRINT("%s: previous mode =  %d\n",
-+		  __FUNCTION__, dvobj->tpt_mode);
-+
-+	RTW_PRINT("%s: enabled mode = %d\n",
-+		  __FUNCTION__, mode);
-+
-+	dvobj->tpt_mode = mode;
-+
-+	rtw_tpt_mode(adapter);
-+
-+exit:
-+	return count;
-+
-+}
-+#endif /* CONFIG_RTW_TPT_MODE */
-+
-+int proc_get_cur_beacon_keys(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	struct mlme_priv *mlme = &adapter->mlmepriv;
-+
-+	rtw_dump_bcn_keys(m, &mlme->cur_beacon_keys);
-+
-+	return 0;
-+}
-+
-+/*
-+* rtw_adapter_proc:
-+* init/deinit when register/unregister net_device
-+*/
-+const struct rtw_proc_hdl adapter_proc_hdls[] = {
-+#if RTW_SEQ_FILE_TEST
-+	RTW_PROC_HDL_SEQ("seq_file_test", &seq_file_test, NULL),
-+#endif
-+	RTW_PROC_HDL_SSEQ("write_reg", NULL, proc_set_write_reg),
-+	RTW_PROC_HDL_SSEQ("read_reg", proc_get_read_reg, proc_set_read_reg),
-+	RTW_PROC_HDL_SSEQ("tx_rate_bmp", proc_get_dump_tx_rate_bmp, NULL),
-+	RTW_PROC_HDL_SSEQ("adapters_status", proc_get_dump_adapters_status, NULL),
-+#ifdef CONFIG_RTW_CUSTOMER_STR
-+	RTW_PROC_HDL_SSEQ("customer_str", proc_get_customer_str, NULL),
-+#endif
-+	RTW_PROC_HDL_SSEQ("fwstate", proc_get_fwstate, NULL),
-+	RTW_PROC_HDL_SSEQ("sec_info", proc_get_sec_info, NULL),
-+	RTW_PROC_HDL_SSEQ("mlmext_state", proc_get_mlmext_state, NULL),
-+	RTW_PROC_HDL_SSEQ("qos_option", proc_get_qos_option, NULL),
-+	RTW_PROC_HDL_SSEQ("ht_option", proc_get_ht_option, NULL),
-+	RTW_PROC_HDL_SSEQ("rf_info", proc_get_rf_info, NULL),
-+	RTW_PROC_HDL_SSEQ("scan_param", proc_get_scan_param, proc_set_scan_param),
-+	RTW_PROC_HDL_SSEQ("scan_abort", proc_get_scan_abort, NULL),
-+#ifdef CONFIG_SCAN_BACKOP
-+	RTW_PROC_HDL_SSEQ("backop_flags_sta", proc_get_backop_flags_sta, proc_set_backop_flags_sta),
-+	#ifdef CONFIG_AP_MODE
-+	RTW_PROC_HDL_SSEQ("backop_flags_ap", proc_get_backop_flags_ap, proc_set_backop_flags_ap),
-+	#endif
-+	#ifdef CONFIG_RTW_MESH
-+	RTW_PROC_HDL_SSEQ("backop_flags_mesh", proc_get_backop_flags_mesh, proc_set_backop_flags_mesh),
-+	#endif
-+#endif
-+#ifdef CONFIG_RTW_REPEATER_SON
-+	RTW_PROC_HDL_SSEQ("rson_data", proc_get_rson_data, proc_set_rson_data),
-+#endif
-+	RTW_PROC_HDL_SSEQ("survey_info", proc_get_survey_info, proc_set_survey_info),
-+	RTW_PROC_HDL_SSEQ("ap_info", proc_get_ap_info, NULL),
-+#ifdef ROKU_PRIVATE
-+	RTW_PROC_HDL_SSEQ("infra_ap", proc_get_infra_ap, NULL),
-+#endif /* ROKU_PRIVATE */
-+	RTW_PROC_HDL_SSEQ("trx_info", proc_get_trx_info, proc_reset_trx_info),
-+	RTW_PROC_HDL_SSEQ("tx_power_offset", proc_get_tx_power_offset, proc_set_tx_power_offset),
-+	RTW_PROC_HDL_SSEQ("rate_ctl", proc_get_rate_ctl, proc_set_rate_ctl),
-+	RTW_PROC_HDL_SSEQ("bw_ctl", proc_get_bw_ctl, proc_set_bw_ctl),
-+	RTW_PROC_HDL_SSEQ("mac_qinfo", proc_get_mac_qinfo, NULL),
-+	RTW_PROC_HDL_SSEQ("macid_info", proc_get_macid_info, NULL),
-+	RTW_PROC_HDL_SSEQ("bcmc_info", proc_get_mi_ap_bc_info, NULL),
-+	RTW_PROC_HDL_SSEQ("sec_cam", proc_get_sec_cam, proc_set_sec_cam),
-+	RTW_PROC_HDL_SSEQ("sec_cam_cache", proc_get_sec_cam_cache, NULL),
-+	RTW_PROC_HDL_SSEQ("ps_dbg_info", proc_get_ps_dbg_info, proc_set_ps_dbg_info),
-+	RTW_PROC_HDL_SSEQ("wifi_spec", proc_get_wifi_spec, NULL),
-+#ifdef CONFIG_LAYER2_ROAMING
-+	RTW_PROC_HDL_SSEQ("roam_flags", proc_get_roam_flags, proc_set_roam_flags),
-+	RTW_PROC_HDL_SSEQ("roam_param", proc_get_roam_param, proc_set_roam_param),
-+	RTW_PROC_HDL_SSEQ("roam_tgt_addr", NULL, proc_set_roam_tgt_addr),
-+#endif /* CONFIG_LAYER2_ROAMING */
-+#ifdef CONFIG_RTW_MBO
-+	RTW_PROC_HDL_SSEQ("non_pref_ch", rtw_mbo_proc_non_pref_chans_get, rtw_mbo_proc_non_pref_chans_set),
-+	RTW_PROC_HDL_SSEQ("cell_data", rtw_mbo_proc_cell_data_get, rtw_mbo_proc_cell_data_set),
-+#endif
-+#ifdef CONFIG_RTW_80211R
-+	RTW_PROC_HDL_SSEQ("ft_flags", rtw_ft_proc_flags_get, rtw_ft_proc_flags_set),
-+#endif
-+	RTW_PROC_HDL_SSEQ("defs_param", proc_get_defs_param, proc_set_defs_param),
-+#ifdef CONFIG_SDIO_HCI
-+	RTW_PROC_HDL_SSEQ("sd_f0_reg_dump", proc_get_sd_f0_reg_dump, NULL),
-+	RTW_PROC_HDL_SSEQ("sdio_local_reg_dump", proc_get_sdio_local_reg_dump, NULL),
-+	RTW_PROC_HDL_SSEQ("sdio_card_info", proc_get_sdio_card_info, NULL),
-+	#ifdef CONFIG_SDIO_RECVBUF_AGGREGATION
-+	RTW_PROC_HDL_SSEQ("sdio_recvbuf_aggregation", proc_get_sdio_recvbuf_aggregation, proc_set_sdio_recvbuf_aggregation),
-+	#endif
-+	#ifdef CONFIG_SDIO_RECVBUF_PWAIT
-+	RTW_PROC_HDL_SSEQ("sdio_recvbuf_pwait", proc_get_sdio_recvbuf_pwait, proc_set_sdio_recvbuf_pwait),
-+	#endif
-+#ifdef DBG_SDIO
-+	RTW_PROC_HDL_SSEQ("sdio_dbg", proc_get_sdio_dbg, proc_set_sdio_dbg),
-+#endif /* DBG_SDIO */
-+#endif /* CONFIG_SDIO_HCI */
-+
-+	RTW_PROC_HDL_SSEQ("fwdl_test_case", NULL, proc_set_fwdl_test_case),
-+	RTW_PROC_HDL_SSEQ("del_rx_ampdu_test_case", NULL, proc_set_del_rx_ampdu_test_case),
-+	RTW_PROC_HDL_SSEQ("wait_hiq_empty", NULL, proc_set_wait_hiq_empty),
-+	RTW_PROC_HDL_SSEQ("sta_linking_test", NULL, proc_set_sta_linking_test),
-+#ifdef CONFIG_AP_MODE
-+	RTW_PROC_HDL_SSEQ("ap_linking_test", NULL, proc_set_ap_linking_test),
-+#endif
-+
-+	RTW_PROC_HDL_SSEQ("mac_reg_dump", proc_get_mac_reg_dump, NULL),
-+	RTW_PROC_HDL_SSEQ("bb_reg_dump", proc_get_bb_reg_dump, NULL),
-+	RTW_PROC_HDL_SSEQ("bb_reg_dump_ex", proc_get_bb_reg_dump_ex, NULL),
-+	RTW_PROC_HDL_SSEQ("rf_reg_dump", proc_get_rf_reg_dump, NULL),
-+
-+#ifdef CONFIG_RTW_LED
-+	RTW_PROC_HDL_SSEQ("led_config", proc_get_led_config, proc_set_led_config),
-+#endif
-+
-+#ifdef CONFIG_AP_MODE
-+	RTW_PROC_HDL_SSEQ("aid_status", proc_get_aid_status, proc_set_aid_status),
-+	RTW_PROC_HDL_SSEQ("ap_isolate", proc_get_ap_isolate, proc_set_ap_isolate),
-+	RTW_PROC_HDL_SSEQ("all_sta_info", proc_get_all_sta_info, NULL),
-+	RTW_PROC_HDL_SSEQ("bmc_tx_rate", proc_get_bmc_tx_rate, proc_set_bmc_tx_rate),
-+	#if CONFIG_RTW_AP_DATA_BMC_TO_UC
-+	RTW_PROC_HDL_SSEQ("ap_b2u_flags", proc_get_ap_b2u_flags, proc_set_ap_b2u_flags),
-+	#endif
-+#endif /* CONFIG_AP_MODE */
-+
-+#ifdef DBG_MEMORY_LEAK
-+	RTW_PROC_HDL_SSEQ("_malloc_cnt", proc_get_malloc_cnt, NULL),
-+#endif /* DBG_MEMORY_LEAK */
-+
-+#ifdef CONFIG_FIND_BEST_CHANNEL
-+	RTW_PROC_HDL_SSEQ("best_channel", proc_get_best_channel, proc_set_best_channel),
-+#endif
-+
-+	RTW_PROC_HDL_SSEQ("rx_signal", proc_get_rx_signal, proc_set_rx_signal),
-+	RTW_PROC_HDL_SSEQ("rx_chk_limit", proc_get_rx_chk_limit, proc_set_rx_chk_limit),
-+	RTW_PROC_HDL_SSEQ("hw_info", proc_get_hw_status, proc_set_hw_status),
-+	RTW_PROC_HDL_SSEQ("mac_rptbuf", proc_get_mac_rptbuf, NULL),
-+#ifdef CONFIG_80211N_HT
-+	RTW_PROC_HDL_SSEQ("ht_enable", proc_get_ht_enable, proc_set_ht_enable),
-+	RTW_PROC_HDL_SSEQ("bw_mode", proc_get_bw_mode, proc_set_bw_mode),
-+	RTW_PROC_HDL_SSEQ("ampdu_enable", proc_get_ampdu_enable, proc_set_ampdu_enable),
-+	RTW_PROC_HDL_SSEQ("rx_ampdu", proc_get_rx_ampdu, proc_set_rx_ampdu),
-+	RTW_PROC_HDL_SSEQ("rx_ampdu_size_limit", proc_get_rx_ampdu_size_limit, proc_set_rx_ampdu_size_limit),
-+	RTW_PROC_HDL_SSEQ("rx_ampdu_factor", proc_get_rx_ampdu_factor, proc_set_rx_ampdu_factor),
-+	RTW_PROC_HDL_SSEQ("rx_ampdu_density", proc_get_rx_ampdu_density, proc_set_rx_ampdu_density),
-+	RTW_PROC_HDL_SSEQ("tx_ampdu_density", proc_get_tx_ampdu_density, proc_set_tx_ampdu_density),
-+	RTW_PROC_HDL_SSEQ("tx_max_agg_num", proc_get_tx_max_agg_num, proc_set_tx_max_agg_num),
-+	RTW_PROC_HDL_SSEQ("tx_quick_addba_req", proc_get_tx_quick_addba_req, proc_set_tx_quick_addba_req),
-+#ifdef CONFIG_TX_AMSDU
-+	RTW_PROC_HDL_SSEQ("tx_amsdu", proc_get_tx_amsdu, proc_set_tx_amsdu),
-+	RTW_PROC_HDL_SSEQ("tx_amsdu_rate", proc_get_tx_amsdu_rate, proc_set_tx_amsdu_rate),
-+#endif
-+#endif /* CONFIG_80211N_HT */
-+
-+#ifdef CONFIG_80211AC_VHT
-+	RTW_PROC_HDL_SSEQ("vht_24g_enable", proc_get_vht_24g_enable, proc_set_vht_24g_enable),
-+#endif
-+
-+	#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
-+	RTW_PROC_HDL_SSEQ("tx_aval_int_threshold", proc_get_tx_aval_th, proc_set_tx_aval_th),
-+	#endif
-+
-+	RTW_PROC_HDL_SSEQ("dynamic_rrsr", proc_get_dyn_rrsr, proc_set_dyn_rrsr),
-+	RTW_PROC_HDL_SSEQ("en_fwps", proc_get_en_fwps, proc_set_en_fwps),
-+
-+	/* RTW_PROC_HDL_SSEQ("path_rssi", proc_get_two_path_rssi, NULL),
-+	* 	RTW_PROC_HDL_SSEQ("rssi_disp",proc_get_rssi_disp, proc_set_rssi_disp), */
-+
-+#ifdef CONFIG_BT_COEXIST
-+	RTW_PROC_HDL_SSEQ("btcoex_dbg", proc_get_btcoex_dbg, proc_set_btcoex_dbg),
-+	RTW_PROC_HDL_SSEQ("btcoex", proc_get_btcoex_info, NULL),
-+	RTW_PROC_HDL_SSEQ("btinfo_evt", NULL, proc_set_btinfo_evt),
-+	RTW_PROC_HDL_SSEQ("btreg_read", proc_get_btreg_read, proc_set_btreg_read),
-+	RTW_PROC_HDL_SSEQ("btreg_write", proc_get_btreg_write, proc_set_btreg_write),
-+	RTW_PROC_HDL_SSEQ("btc_reduce_wl_txpwr", proc_get_btc_reduce_wl_txpwr, proc_set_btc_reduce_wl_txpwr),
-+#ifdef CONFIG_RF4CE_COEXIST
-+	RTW_PROC_HDL_SSEQ("rf4ce_state", proc_get_rf4ce_state, proc_set_rf4ce_state),
-+#endif
-+#endif /* CONFIG_BT_COEXIST */
-+
-+#if defined(DBG_CONFIG_ERROR_DETECT)
-+	RTW_PROC_HDL_SSEQ("sreset", proc_get_sreset, proc_set_sreset),
-+#endif /* DBG_CONFIG_ERROR_DETECT */
-+	RTW_PROC_HDL_SSEQ("trx_info_debug", proc_get_trx_info_debug, NULL),
-+
-+#ifdef CONFIG_HUAWEI_PROC
-+	RTW_PROC_HDL_SSEQ("huawei_trx_info", proc_get_huawei_trx_info, NULL),
-+#endif
-+	RTW_PROC_HDL_SSEQ("linked_info_dump", proc_get_linked_info_dump, proc_set_linked_info_dump),
-+	RTW_PROC_HDL_SSEQ("sta_tp_dump", proc_get_sta_tp_dump, proc_set_sta_tp_dump),
-+	RTW_PROC_HDL_SSEQ("sta_tp_info", proc_get_sta_tp_info, NULL),
-+	RTW_PROC_HDL_SSEQ("dis_turboedca", proc_get_turboedca_ctrl, proc_set_turboedca_ctrl),
-+	RTW_PROC_HDL_SSEQ("tx_info_msg", proc_get_tx_info_msg, NULL),
-+	RTW_PROC_HDL_SSEQ("rx_info_msg", proc_get_rx_info_msg, proc_set_rx_info_msg),
-+
-+#if defined(CONFIG_LPS_PG) && defined(CONFIG_RTL8822C)
-+	RTW_PROC_HDL_SSEQ("lps_pg_debug", proc_get_lps_pg_debug, NULL),
-+#endif
-+
-+#ifdef CONFIG_GPIO_API
-+	RTW_PROC_HDL_SSEQ("gpio_info", proc_get_gpio, proc_set_gpio),
-+	RTW_PROC_HDL_SSEQ("gpio_set_output_value", NULL, proc_set_gpio_output_value),
-+	RTW_PROC_HDL_SSEQ("gpio_set_direction", NULL, proc_set_config_gpio),
-+#endif
-+
-+#ifdef CONFIG_DBG_COUNTER
-+	RTW_PROC_HDL_SSEQ("rx_logs", proc_get_rx_logs, NULL),
-+	RTW_PROC_HDL_SSEQ("tx_logs", proc_get_tx_logs, NULL),
-+	RTW_PROC_HDL_SSEQ("int_logs", proc_get_int_logs, NULL),
-+#endif
-+
-+#ifdef CONFIG_DBG_RF_CAL
-+	RTW_PROC_HDL_SSEQ("iqk", proc_get_iqk_info, proc_set_iqk),
-+	RTW_PROC_HDL_SSEQ("lck", proc_get_lck_info, proc_set_lck),
-+#endif
-+
-+#ifdef CONFIG_PCI_HCI
-+	RTW_PROC_HDL_SSEQ("rx_ring", proc_get_rx_ring, NULL),
-+	RTW_PROC_HDL_SSEQ("tx_ring", proc_get_tx_ring, NULL),
-+#ifdef DBG_TXBD_DESC_DUMP
-+	RTW_PROC_HDL_SSEQ("tx_ring_ext", proc_get_tx_ring_ext, proc_set_tx_ring_ext),
-+#endif
-+	RTW_PROC_HDL_SSEQ("pci_aspm", proc_get_pci_aspm, NULL),
-+
-+	RTW_PROC_HDL_SSEQ("pci_conf_space", proc_get_pci_conf_space, proc_set_pci_conf_space),
-+
-+	RTW_PROC_HDL_SSEQ("pci_bridge_conf_space", proc_get_pci_bridge_conf_space, proc_set_pci_bridge_conf_space),
-+
-+#endif
-+
-+#ifdef CONFIG_WOWLAN
-+	RTW_PROC_HDL_SSEQ("wow_enable", proc_get_wow_enable, proc_set_wow_enable),
-+	RTW_PROC_HDL_SSEQ("wow_pattern_info", proc_get_pattern_info, proc_set_pattern_info),
-+	RTW_PROC_HDL_SSEQ("wow_wakeup_event", proc_get_wakeup_event,
-+			  proc_set_wakeup_event),
-+	RTW_PROC_HDL_SSEQ("wowlan_last_wake_reason", proc_get_wakeup_reason, NULL),
-+#ifdef CONFIG_WOW_PATTERN_HW_CAM
-+	RTW_PROC_HDL_SSEQ("wow_pattern_cam", proc_dump_pattern_cam, NULL),
-+#endif
-+#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
-+	RTW_PROC_HDL_SSEQ("wow_keep_alive_info", proc_dump_wow_keep_alive_info, NULL),
-+#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
-+
-+#endif
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+	RTW_PROC_HDL_SSEQ("wowlan_gpio_info", proc_get_wowlan_gpio_info, proc_set_wowlan_gpio_info),
-+#endif
-+#ifdef CONFIG_P2P_WOWLAN
-+	RTW_PROC_HDL_SSEQ("p2p_wowlan_info", proc_get_p2p_wowlan_info, NULL),
-+#endif
-+	RTW_PROC_HDL_SSEQ("country_code", proc_get_country_code, proc_set_country_code),
-+	RTW_PROC_HDL_SSEQ("chan_plan", proc_get_chan_plan, proc_set_chan_plan),
-+	RTW_PROC_HDL_SSEQ("cap_spt_op_class_ch", proc_get_cap_spt_op_class_ch, proc_set_cap_spt_op_class_ch),
-+	RTW_PROC_HDL_SSEQ("reg_spt_op_class_ch", proc_get_reg_spt_op_class_ch, proc_set_reg_spt_op_class_ch),
-+	RTW_PROC_HDL_SSEQ("cur_spt_op_class_ch", proc_get_cur_spt_op_class_ch, proc_set_cur_spt_op_class_ch),
-+#if CONFIG_RTW_MACADDR_ACL
-+	RTW_PROC_HDL_SSEQ("macaddr_acl", proc_get_macaddr_acl, proc_set_macaddr_acl),
-+#endif
-+#if CONFIG_RTW_PRE_LINK_STA
-+	RTW_PROC_HDL_SSEQ("pre_link_sta", proc_get_pre_link_sta, proc_set_pre_link_sta),
-+#endif
-+	RTW_PROC_HDL_SSEQ("ch_sel_policy", proc_get_ch_sel_policy, proc_set_ch_sel_policy),
-+#ifdef CONFIG_DFS_MASTER
-+	RTW_PROC_HDL_SSEQ("dfs_test_case", proc_get_dfs_test_case, proc_set_dfs_test_case),
-+	RTW_PROC_HDL_SSEQ("update_non_ocp", NULL, proc_set_update_non_ocp),
-+	RTW_PROC_HDL_SSEQ("radar_detect", NULL, proc_set_radar_detect),
-+	RTW_PROC_HDL_SSEQ("dfs_ch_sel_e_flags", proc_get_dfs_ch_sel_e_flags, proc_set_dfs_ch_sel_e_flags),
-+	RTW_PROC_HDL_SSEQ("dfs_ch_sel_d_flags", proc_get_dfs_ch_sel_d_flags, proc_set_dfs_ch_sel_d_flags),
-+	#if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
-+	RTW_PROC_HDL_SSEQ("dfs_slave_with_rd", proc_get_dfs_slave_with_rd, proc_set_dfs_slave_with_rd),
-+	#endif
-+#endif
-+#ifdef CONFIG_BCN_CNT_CONFIRM_HDL
-+	RTW_PROC_HDL_SSEQ("new_bcn_max", proc_get_new_bcn_max, proc_set_new_bcn_max),
-+#endif
-+	RTW_PROC_HDL_SSEQ("sink_udpport", proc_get_udpport, proc_set_udpport),
-+#ifdef DBG_RX_COUNTER_DUMP
-+	RTW_PROC_HDL_SSEQ("dump_rx_cnt_mode", proc_get_rx_cnt_dump, proc_set_rx_cnt_dump),
-+#endif
-+#ifdef CONFIG_AP_MODE
-+	RTW_PROC_HDL_SSEQ("change_bss_chbw", NULL, proc_set_change_bss_chbw),
-+#endif
-+#if CONFIG_TX_AC_LIFETIME
-+	RTW_PROC_HDL_SSEQ("tx_aclt_force_val", proc_get_tx_aclt_force_val, proc_set_tx_aclt_force_val),
-+	RTW_PROC_HDL_SSEQ("tx_aclt_flags", proc_get_tx_aclt_flags, proc_set_tx_aclt_flags),
-+	RTW_PROC_HDL_SSEQ("tx_aclt_confs", proc_get_tx_aclt_confs, proc_set_tx_aclt_confs),
-+#endif
-+	RTW_PROC_HDL_SSEQ("tx_bw_mode", proc_get_tx_bw_mode, proc_set_tx_bw_mode),
-+	RTW_PROC_HDL_SSEQ("hal_txpwr_info", proc_get_hal_txpwr_info, NULL),
-+	RTW_PROC_HDL_SSEQ("target_tx_power", proc_get_target_tx_power, NULL),
-+	RTW_PROC_HDL_SSEQ("tx_power_by_rate", proc_get_tx_power_by_rate, NULL),
-+#if CONFIG_TXPWR_LIMIT
-+	RTW_PROC_HDL_SSEQ("tx_power_limit", proc_get_tx_power_limit, NULL),
-+#endif
-+	RTW_PROC_HDL_SSEQ("tpc_settings", proc_get_tpc_settings, proc_set_tpc_settings),
-+	RTW_PROC_HDL_SSEQ("antenna_gain", proc_get_antenna_gain, proc_set_antenna_gain),
-+	RTW_PROC_HDL_SSEQ("tx_power_ext_info", proc_get_tx_power_ext_info, proc_set_tx_power_ext_info),
-+	RTW_PROC_HDL_SEQ("tx_power_idx", &seq_ops_tx_power_idx, proc_set_tx_power_idx_dump),
-+	RTW_PROC_HDL_SEQ("txpwr_total_dbm", &seq_ops_txpwr_total_dbm, proc_set_txpwr_total_dbm_dump),
-+#ifdef CONFIG_RF_POWER_TRIM
-+	RTW_PROC_HDL_SSEQ("tx_gain_offset", NULL, proc_set_tx_gain_offset),
-+	RTW_PROC_HDL_SSEQ("kfree_flag", proc_get_kfree_flag, proc_set_kfree_flag),
-+	RTW_PROC_HDL_SSEQ("kfree_bb_gain", proc_get_kfree_bb_gain, proc_set_kfree_bb_gain),
-+	RTW_PROC_HDL_SSEQ("kfree_thermal", proc_get_kfree_thermal, proc_set_kfree_thermal),
-+#endif
-+#ifdef CONFIG_POWER_SAVING
-+	RTW_PROC_HDL_SSEQ("ps_info", proc_get_ps_info, proc_set_ps_info),
-+#ifdef CONFIG_WMMPS_STA
-+	RTW_PROC_HDL_SSEQ("wmmps_info", proc_get_wmmps_info, proc_set_wmmps_info),
-+#endif /* CONFIG_WMMPS_STA */
-+#endif
-+#ifdef CONFIG_TDLS
-+	RTW_PROC_HDL_SSEQ("tdls_info", proc_get_tdls_info, NULL),
-+	RTW_PROC_HDL_SSEQ("tdls_enable", proc_get_tdls_enable, proc_set_tdls_enable),
-+#endif
-+	RTW_PROC_HDL_SSEQ("monitor", proc_get_monitor, proc_set_monitor),
-+#ifdef RTW_SIMPLE_CONFIG
-+	RTW_PROC_HDL_SSEQ("rtw_simple_config", proc_get_simple_config, proc_set_simple_config),
-+#endif
-+
-+#ifdef CONFIG_RTW_ACS
-+	RTW_PROC_HDL_SSEQ("acs", proc_get_best_chan, proc_set_acs),
-+	RTW_PROC_HDL_SSEQ("chan_info", proc_get_chan_info, NULL),
-+#endif
-+
-+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
-+	RTW_PROC_HDL_SSEQ("noise_monitor", proc_get_nm, proc_set_nm),
-+#endif
-+
-+#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
-+	RTW_PROC_HDL_SSEQ("rtkm_info", proc_get_rtkm_info, NULL),
-+#endif
-+	RTW_PROC_HDL_SSEQ("efuse_map", proc_get_efuse_map, NULL),
-+#ifdef CONFIG_IEEE80211W
-+	RTW_PROC_HDL_SSEQ("11w_tx_sa_query", proc_get_tx_sa_query, proc_set_tx_sa_query),
-+	RTW_PROC_HDL_SSEQ("11w_tx_deauth", proc_get_tx_deauth, proc_set_tx_deauth),
-+	RTW_PROC_HDL_SSEQ("11w_tx_auth", proc_get_tx_auth, proc_set_tx_auth),
-+#endif /* CONFIG_IEEE80211W */
-+
-+#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
-+	RTW_PROC_HDL_SSEQ("pathb_phase", proc_get_pathb_phase, proc_set_pathb_phase),
-+#endif
-+
-+#ifdef CONFIG_MBSSID_CAM
-+	RTW_PROC_HDL_SSEQ("mbid_cam", proc_get_mbid_cam_cache, NULL),
-+#endif
-+	RTW_PROC_HDL_SSEQ("mac_addr", proc_get_mac_addr, NULL),
-+	RTW_PROC_HDL_SSEQ("skip_band", proc_get_skip_band, proc_set_skip_band),
-+	RTW_PROC_HDL_SSEQ("hal_spec", proc_get_hal_spec, NULL),
-+	RTW_PROC_HDL_SSEQ("hal_trx_mode", proc_get_hal_trx_mode, NULL),
-+
-+	RTW_PROC_HDL_SSEQ("rx_stat", proc_get_rx_stat, NULL),
-+
-+	RTW_PROC_HDL_SSEQ("tx_stat", proc_get_tx_stat, NULL),
-+	/**** PHY Capability ****/
-+	RTW_PROC_HDL_SSEQ("phy_cap", proc_get_phy_cap, NULL),
-+#ifdef CONFIG_80211N_HT
-+	RTW_PROC_HDL_SSEQ("rx_stbc", proc_get_rx_stbc, proc_set_rx_stbc),
-+	RTW_PROC_HDL_SSEQ("stbc_cap", proc_get_stbc_cap, proc_set_stbc_cap),
-+	RTW_PROC_HDL_SSEQ("ldpc_cap", proc_get_ldpc_cap, proc_set_ldpc_cap),
-+#endif /* CONFIG_80211N_HT */
-+#ifdef CONFIG_BEAMFORMING
-+	RTW_PROC_HDL_SSEQ("txbf_cap", proc_get_txbf_cap, proc_set_txbf_cap),
-+#endif
-+
-+#ifdef CONFIG_SUPPORT_TRX_SHARED
-+	RTW_PROC_HDL_SSEQ("trx_share_mode", proc_get_trx_share_mode, NULL),
-+#endif
-+	RTW_PROC_HDL_SSEQ("napi_info", proc_get_napi_info, NULL),
-+#ifdef CONFIG_RTW_NAPI_DYNAMIC
-+	RTW_PROC_HDL_SSEQ("napi_th", proc_get_napi_info, proc_set_napi_th),
-+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
-+
-+	RTW_PROC_HDL_SSEQ("rsvd_page", proc_dump_rsvd_page, proc_set_rsvd_page_info),
-+
-+#ifdef CONFIG_SUPPORT_FIFO_DUMP
-+	RTW_PROC_HDL_SSEQ("fifo_dump", proc_dump_fifo, proc_set_fifo_info),
-+#endif
-+	RTW_PROC_HDL_SSEQ("fw_info", proc_get_fw_info, NULL),
-+
-+#ifdef DBG_XMIT_BLOCK
-+	RTW_PROC_HDL_SSEQ("xmit_block", proc_get_xmit_block, proc_set_xmit_block),
-+#endif
-+
-+	RTW_PROC_HDL_SSEQ("ack_timeout", proc_get_ack_timeout, proc_set_ack_timeout),
-+
-+	RTW_PROC_HDL_SSEQ("dynamic_agg_enable", proc_get_dynamic_agg_enable, proc_set_dynamic_agg_enable),
-+	RTW_PROC_HDL_SSEQ("fw_offload", proc_get_fw_offload, proc_set_fw_offload),
-+
-+#ifdef CONFIG_RTW_WDS
-+	RTW_PROC_HDL_SSEQ("wds_en", proc_get_wds_en, proc_set_wds_en),
-+	RTW_PROC_HDL_SSEQ("sta_wds_en", NULL, proc_set_sta_wds_en),
-+	RTW_PROC_HDL_SSEQ("wds_gptr", proc_get_wds_gptr, NULL),
-+	#ifdef CONFIG_AP_MODE
-+	RTW_PROC_HDL_SSEQ("wds_path", proc_get_wds_path, NULL),
-+	#endif
-+#endif
-+
-+#ifdef CONFIG_RTW_MULTI_AP
-+	RTW_PROC_HDL_SSEQ("multi_ap_opmode", proc_get_multi_ap_opmode, proc_set_multi_ap_opmode),
-+	RTW_PROC_HDL_SSEQ("unassoc_sta", proc_get_unassoc_sta, proc_set_unassoc_sta),
-+#ifdef CONFIG_IOCTL_CFG80211
-+	RTW_PROC_HDL_SSEQ("sta_assoc_req_frame_body", proc_get_sta_assoc_req_frame_body, proc_set_sta_assoc_req_frame_body),
-+#endif
-+	RTW_PROC_HDL_SSEQ("ch_util_threshold", proc_get_ch_util_threshold, proc_set_ch_util_threshold),
-+	RTW_PROC_HDL_SSEQ("ch_utilization", proc_get_ch_utilization, NULL),
-+#endif
-+
-+#ifdef CONFIG_RTW_MESH
-+	#if CONFIG_RTW_MESH_ACNODE_PREVENT
-+	RTW_PROC_HDL_SSEQ("mesh_acnode_prevent", proc_get_mesh_acnode_prevent, proc_set_mesh_acnode_prevent),
-+	#endif
-+	#if CONFIG_RTW_MESH_OFFCH_CAND
-+	RTW_PROC_HDL_SSEQ("mesh_offch_cand", proc_get_mesh_offch_cand, proc_set_mesh_offch_cand),
-+	#endif
-+	#if CONFIG_RTW_MESH_PEER_BLACKLIST
-+	RTW_PROC_HDL_SSEQ("mesh_peer_blacklist", proc_get_mesh_peer_blacklist, proc_set_mesh_peer_blacklist),
-+	#endif
-+	#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
-+	RTW_PROC_HDL_SSEQ("mesh_cto_mgate_require", proc_get_mesh_cto_mgate_require, proc_set_mesh_cto_mgate_require),
-+	RTW_PROC_HDL_SSEQ("mesh_cto_mgate_blacklist", proc_get_mesh_cto_mgate_blacklist, proc_set_mesh_cto_mgate_blacklist),
-+	#endif
-+	RTW_PROC_HDL_SSEQ("mesh_peer_sel_policy", proc_get_mesh_peer_sel_policy, NULL),
-+	RTW_PROC_HDL_SSEQ("mesh_networks", proc_get_mesh_networks, NULL),
-+	RTW_PROC_HDL_SSEQ("mesh_plink_ctl", proc_get_mesh_plink_ctl, NULL),
-+	RTW_PROC_HDL_SSEQ("mesh_mpath", proc_get_mesh_mpath, NULL),
-+	RTW_PROC_HDL_SSEQ("mesh_mpp", proc_get_mesh_mpp, NULL),
-+	RTW_PROC_HDL_SSEQ("mesh_known_gates", proc_get_mesh_known_gates, NULL),
-+	#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
-+	RTW_PROC_HDL_SSEQ("mesh_b2u_flags", proc_get_mesh_b2u_flags, proc_set_mesh_b2u_flags),
-+	#endif
-+	RTW_PROC_HDL_SSEQ("mesh_stats", proc_get_mesh_stats, NULL),
-+	RTW_PROC_HDL_SSEQ("mesh_gate_timeout_factor", proc_get_mesh_gate_timeout, proc_set_mesh_gate_timeout),
-+	RTW_PROC_HDL_SSEQ("mesh_gate_state", proc_get_mesh_gate_state, NULL),
-+	RTW_PROC_HDL_SSEQ("mesh_peer_alive_based_preq", proc_get_peer_alive_based_preq, proc_set_peer_alive_based_preq),
-+#endif
-+#ifdef CONFIG_FW_HANDLE_TXBCN
-+	RTW_PROC_HDL_SSEQ("fw_tbtt_rpt", proc_get_fw_tbtt_rpt, proc_set_fw_tbtt_rpt),
-+#endif
-+#ifdef CONFIG_LPS_CHK_BY_TP
-+	RTW_PROC_HDL_SSEQ("lps_chk_tp", proc_get_lps_chk_tp, proc_set_lps_chk_tp),
-+#endif
-+#ifdef CONFIG_SUPPORT_STATIC_SMPS
-+	RTW_PROC_HDL_SSEQ("smps", proc_get_smps, proc_set_smps),
-+#endif
-+
-+#ifdef RTW_BUSY_DENY_SCAN
-+	RTW_PROC_HDL_SSEQ("scan_interval_thr", proc_get_scan_interval_thr, \
-+			  proc_set_scan_interval_thr),
-+#endif
-+	RTW_PROC_HDL_SSEQ("scan_deny", proc_get_scan_deny, proc_set_scan_deny),
-+#ifdef CONFIG_RTW_TPT_MODE
-+	RTW_PROC_HDL_SSEQ("tpt_mode", proc_get_tpt_mode, proc_set_tpt_mode),
-+#endif
-+
-+#ifdef CONFIG_CTRL_TXSS_BY_TP
-+	RTW_PROC_HDL_SSEQ("txss_tp", proc_get_txss_tp, proc_set_txss_tp),
-+	#ifdef DBG_CTRL_TXSS
-+	RTW_PROC_HDL_SSEQ("txss_ctrl", proc_get_txss_ctrl, proc_set_txss_ctrl),
-+	#endif
-+#endif
-+
-+	RTW_PROC_HDL_SSEQ("cur_beacon_keys", proc_get_cur_beacon_keys, NULL),
-+
-+#ifdef CONFIG_WAR_OFFLOAD
-+	RTW_PROC_HDL_SSEQ("war_offload_enable", proc_get_war_offload_enable, proc_set_war_offload_enable),
-+	RTW_PROC_HDL_SSEQ("war_offload_ipv4_addr", NULL, proc_set_war_offload_ipv4_addr),
-+	RTW_PROC_HDL_SSEQ("war_offload_ipv6_addr", NULL, proc_set_war_offload_ipv6_addr),
-+#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
-+	RTW_PROC_HDL_SSEQ("war_offload_mdns_domain_name", proc_get_war_offload_mdns_domain_name, proc_set_war_offload_mdns_domain_name),
-+	RTW_PROC_HDL_SSEQ("war_offload_mdns_machine_name", proc_get_war_offload_mdns_machine_name, proc_set_war_offload_mdns_machine_name),
-+	RTW_PROC_HDL_SSEQ("war_offload_mdns_service_info", proc_get_war_offload_mdns_service_info, proc_set_war_offload_mdns_service_info),
-+	RTW_PROC_HDL_SSEQ("war_offload_mdns_service_info_txt_rsp", proc_get_war_offload_mdns_txt_rsp, proc_set_war_offload_mdns_txt_rsp),
-+#endif /* CONFIG_OFFLOAD_MDNS_V4 || CONFIG_OFFLOAD_MDNS_V6 */
-+#endif /* CONFIG_WAR_OFFLOAD */
-+
-+};
-+
-+const int adapter_proc_hdls_num = sizeof(adapter_proc_hdls) / sizeof(struct rtw_proc_hdl);
-+
-+static int rtw_adapter_proc_open(struct inode *inode, struct file *file)
-+{
-+	ssize_t index = (ssize_t)PDE_DATA(inode);
-+	const struct rtw_proc_hdl *hdl = adapter_proc_hdls + index;
-+	void *private = proc_get_parent_data(inode);
-+
-+	if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
-+		int res = seq_open(file, hdl->u.seq_op);
-+
-+		if (res == 0)
-+			((struct seq_file *)file->private_data)->private = private;
-+
-+		return res;
-+	} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
-+		int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
-+
-+		return single_open(file, show, private);
-+	} else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) {
-+		int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy;
-+
-+		return single_open_size(file, show, private, hdl->u.sz.size);
-+	} else {
-+		return -EROFS;
-+	}
-+}
-+
-+static ssize_t rtw_adapter_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
-+{
-+	ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
-+	const struct rtw_proc_hdl *hdl = adapter_proc_hdls + index;
-+	ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
-+
-+	if (write)
-+		return write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private);
-+
-+	return -EROFS;
-+}
-+
-+static const struct rtw_proc_ops rtw_adapter_proc_seq_fops = {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
-+	.proc_open = rtw_adapter_proc_open,
-+	.proc_read = seq_read,
-+	.proc_lseek = seq_lseek,
-+	.proc_release = seq_release,
-+	.proc_write = rtw_adapter_proc_write,
-+#else
-+	.owner = THIS_MODULE,
-+	.open = rtw_adapter_proc_open,
-+	.read = seq_read,
-+	.llseek = seq_lseek,
-+	.release = seq_release,
-+	.write = rtw_adapter_proc_write,
-+#endif
-+};
-+
-+static const struct rtw_proc_ops rtw_adapter_proc_sseq_fops = {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
-+	.proc_open = rtw_adapter_proc_open,
-+	.proc_read = seq_read,
-+	.proc_lseek = seq_lseek,
-+	.proc_release = single_release,
-+	.proc_write = rtw_adapter_proc_write,
-+#else
-+	.owner = THIS_MODULE,
-+	.open = rtw_adapter_proc_open,
-+	.read = seq_read,
-+	.llseek = seq_lseek,
-+	.release = single_release,
-+	.write = rtw_adapter_proc_write,
-+#endif
-+};
-+
-+int proc_get_odm_adaptivity(struct seq_file *m, void *v)
-+{
-+	struct net_device *dev = m->private;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+
-+	rtw_odm_adaptivity_parm_msg(m, padapter);
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *dev = data;
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
-+	char tmp[32];
-+	u32 th_l2h_ini;
-+	s8 th_edcca_hl_diff;
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp)) {
-+		rtw_warn_on(1);
-+		return -EFAULT;
-+	}
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+
-+		int num = sscanf(tmp, "%x %hhd", &th_l2h_ini, &th_edcca_hl_diff);
-+
-+		if (num != 2)
-+			return count;
-+
-+		rtw_odm_adaptivity_parm_set(padapter, (s8)th_l2h_ini, th_edcca_hl_diff);
-+	}
-+
-+	return count;
-+}
-+
-+static char *phydm_msg = NULL;
-+#define PHYDM_MSG_LEN	80*24*4
-+
-+int proc_get_phydm_cmd(struct seq_file *m, void *v)
-+{
-+	struct net_device *netdev;
-+	PADAPTER padapter;
-+	struct dm_struct *phydm;
-+
-+
-+	netdev = m->private;
-+	padapter = (PADAPTER)rtw_netdev_priv(netdev);
-+	phydm = adapter_to_phydm(padapter);
-+
-+	if (NULL == phydm_msg) {
-+		phydm_msg = rtw_zmalloc(PHYDM_MSG_LEN);
-+		if (NULL == phydm_msg)
-+			return -ENOMEM;
-+
-+		phydm_cmd(phydm, NULL, 0, 0, phydm_msg, PHYDM_MSG_LEN);
-+	}
-+
-+	_RTW_PRINT_SEL(m, "%s\n", phydm_msg);
-+
-+	rtw_mfree(phydm_msg, PHYDM_MSG_LEN);
-+	phydm_msg = NULL;
-+
-+	return 0;
-+}
-+
-+ssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
-+{
-+	struct net_device *netdev;
-+	PADAPTER padapter;
-+	struct dm_struct *phydm;
-+	char tmp[64] = {0};
-+
-+
-+	netdev = (struct net_device *)data;
-+	padapter = (PADAPTER)rtw_netdev_priv(netdev);
-+	phydm = adapter_to_phydm(padapter);
-+
-+	if (count < 1)
-+		return -EFAULT;
-+
-+	if (count > sizeof(tmp))
-+		return -EFAULT;
-+
-+	if (buffer && !copy_from_user(tmp, buffer, count)) {
-+		if (NULL == phydm_msg) {
-+			phydm_msg = rtw_zmalloc(PHYDM_MSG_LEN);
-+			if (NULL == phydm_msg)
-+				return -ENOMEM;
-+		} else
-+			_rtw_memset(phydm_msg, 0, PHYDM_MSG_LEN);
-+
-+		phydm_cmd(phydm, tmp, count, 1, phydm_msg, PHYDM_MSG_LEN);
-+
-+		if (strlen(phydm_msg) == 0) {
-+			rtw_mfree(phydm_msg, PHYDM_MSG_LEN);
-+			phydm_msg = NULL;
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+/*
-+* rtw_odm_proc:
-+* init/deinit when register/unregister net_device, along with rtw_adapter_proc
-+*/
-+const struct rtw_proc_hdl odm_proc_hdls[] = {
-+	RTW_PROC_HDL_SSEQ("adaptivity", proc_get_odm_adaptivity, proc_set_odm_adaptivity),
-+	RTW_PROC_HDL_SZSEQ("cmd", proc_get_phydm_cmd, proc_set_phydm_cmd, PHYDM_MSG_LEN),
-+};
-+
-+const int odm_proc_hdls_num = sizeof(odm_proc_hdls) / sizeof(struct rtw_proc_hdl);
-+
-+static int rtw_odm_proc_open(struct inode *inode, struct file *file)
-+{
-+	ssize_t index = (ssize_t)PDE_DATA(inode);
-+	const struct rtw_proc_hdl *hdl = odm_proc_hdls + index;
-+	void *private = proc_get_parent_data(inode);
-+
-+	if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
-+		int res = seq_open(file, hdl->u.seq_op);
-+
-+		if (res == 0)
-+			((struct seq_file *)file->private_data)->private = private;
-+
-+		return res;
-+	} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
-+		int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
-+
-+		return single_open(file, show, private);
-+	} else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) {
-+		int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy;
-+
-+		return single_open_size(file, show, private, hdl->u.sz.size);
-+	} else {
-+		return -EROFS;
-+	}
-+}
-+
-+static ssize_t rtw_odm_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
-+{
-+	ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
-+	const struct rtw_proc_hdl *hdl = odm_proc_hdls + index;
-+	ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
-+
-+	if (write)
-+		return write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private);
-+
-+	return -EROFS;
-+}
-+
-+static const struct rtw_proc_ops rtw_odm_proc_seq_fops = {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
-+	.proc_open = rtw_odm_proc_open,
-+	.proc_read = seq_read,
-+	.proc_lseek = seq_lseek,
-+	.proc_release = seq_release,
-+	.proc_write = rtw_odm_proc_write,
-+#else
-+	.owner = THIS_MODULE,
-+	.open = rtw_odm_proc_open,
-+	.read = seq_read,
-+	.llseek = seq_lseek,
-+	.release = seq_release,
-+	.write = rtw_odm_proc_write,
-+#endif
-+};
-+
-+static const struct rtw_proc_ops rtw_odm_proc_sseq_fops = {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
-+	.proc_open = rtw_odm_proc_open,
-+	.proc_read = seq_read,
-+	.proc_lseek = seq_lseek,
-+	.proc_release = single_release,
-+	.proc_write = rtw_odm_proc_write,
-+#else
-+	.owner = THIS_MODULE,
-+	.open = rtw_odm_proc_open,
-+	.read = seq_read,
-+	.llseek = seq_lseek,
-+	.release = single_release,
-+	.write = rtw_odm_proc_write,
-+#endif
-+};
-+
-+struct proc_dir_entry *rtw_odm_proc_init(struct net_device *dev)
-+{
-+	struct proc_dir_entry *dir_odm = NULL;
-+	struct proc_dir_entry *entry = NULL;
-+	_adapter	*adapter = rtw_netdev_priv(dev);
-+	ssize_t i;
-+
-+	if (adapter->dir_dev == NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (adapter->dir_odm != NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	dir_odm = rtw_proc_create_dir("odm", adapter->dir_dev, dev);
-+	if (dir_odm == NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	adapter->dir_odm = dir_odm;
-+
-+	for (i = 0; i < odm_proc_hdls_num; i++) {
-+		if (odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
-+			entry = rtw_proc_create_entry(odm_proc_hdls[i].name, dir_odm, &rtw_odm_proc_seq_fops, (void *)i);
-+		else if (odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ ||
-+			 odm_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SZSEQ)
-+			entry = rtw_proc_create_entry(odm_proc_hdls[i].name, dir_odm, &rtw_odm_proc_sseq_fops, (void *)i);
-+		else
-+			entry = NULL;
-+
-+		if (!entry) {
-+			rtw_warn_on(1);
-+			goto exit;
-+		}
-+	}
-+
-+exit:
-+	return dir_odm;
-+}
-+
-+void rtw_odm_proc_deinit(_adapter	*adapter)
-+{
-+	struct proc_dir_entry *dir_odm = NULL;
-+	int i;
-+
-+	dir_odm = adapter->dir_odm;
-+
-+	if (dir_odm == NULL) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	for (i = 0; i < odm_proc_hdls_num; i++)
-+		remove_proc_entry(odm_proc_hdls[i].name, dir_odm);
-+
-+	remove_proc_entry("odm", adapter->dir_dev);
-+
-+	adapter->dir_odm = NULL;
-+
-+	if (phydm_msg) {
-+		rtw_mfree(phydm_msg, PHYDM_MSG_LEN);
-+		phydm_msg = NULL;
-+	}
-+}
-+
-+#ifdef CONFIG_MCC_MODE
-+/*
-+* rtw_mcc_proc:
-+* init/deinit when register/unregister net_device, along with rtw_adapter_proc
-+*/
-+const struct rtw_proc_hdl mcc_proc_hdls[] = {
-+	RTW_PROC_HDL_SSEQ("mcc_info", proc_get_mcc_info, NULL),
-+	RTW_PROC_HDL_SSEQ("mcc_enable", proc_get_mcc_info, proc_set_mcc_enable),
-+	RTW_PROC_HDL_SSEQ("mcc_duration", proc_get_mcc_info, proc_set_mcc_duration),
-+	#ifdef CONFIG_MCC_PHYDM_OFFLOAD
-+	RTW_PROC_HDL_SSEQ("mcc_phydm_offload", proc_get_mcc_info, proc_set_mcc_phydm_offload_enable),
-+	#endif
-+	RTW_PROC_HDL_SSEQ("mcc_single_tx_criteria", proc_get_mcc_info, proc_set_mcc_single_tx_criteria),
-+	RTW_PROC_HDL_SSEQ("mcc_ap_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw20_target_tp),
-+	RTW_PROC_HDL_SSEQ("mcc_ap_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw40_target_tp),
-+	RTW_PROC_HDL_SSEQ("mcc_ap_bw80_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw80_target_tp),
-+	RTW_PROC_HDL_SSEQ("mcc_sta_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw20_target_tp),
-+	RTW_PROC_HDL_SSEQ("mcc_sta_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw40_target_tp),
-+	RTW_PROC_HDL_SSEQ("mcc_sta_bw80_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw80_target_tp),
-+	RTW_PROC_HDL_SSEQ("mcc_policy_table", proc_get_mcc_policy_table, NULL),
-+};
-+
-+const int mcc_proc_hdls_num = sizeof(mcc_proc_hdls) / sizeof(struct rtw_proc_hdl);
-+
-+static int rtw_mcc_proc_open(struct inode *inode, struct file *file)
-+{
-+	ssize_t index = (ssize_t)PDE_DATA(inode);
-+	const struct rtw_proc_hdl *hdl = mcc_proc_hdls + index;
-+	void *private = proc_get_parent_data(inode);
-+
-+	if (hdl->type == RTW_PROC_HDL_TYPE_SEQ) {
-+		int res = seq_open(file, hdl->u.seq_op);
-+
-+		if (res == 0)
-+			((struct seq_file *)file->private_data)->private = private;
-+
-+		return res;
-+	} else if (hdl->type == RTW_PROC_HDL_TYPE_SSEQ) {
-+		int (*show)(struct seq_file *, void *) = hdl->u.show ? hdl->u.show : proc_get_dummy;
-+
-+		return single_open(file, show, private);
-+	} else if (hdl->type == RTW_PROC_HDL_TYPE_SZSEQ) {
-+		int (*show)(struct seq_file *, void *) = hdl->u.sz.show ? hdl->u.sz.show : proc_get_dummy;
-+
-+		return single_open_size(file, show, private, hdl->u.sz.size);
-+	} else {
-+		return -EROFS;
-+	}
-+}
-+
-+static ssize_t rtw_mcc_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos)
-+{
-+	ssize_t index = (ssize_t)PDE_DATA(file_inode(file));
-+	const struct rtw_proc_hdl *hdl = mcc_proc_hdls + index;
-+	ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write;
-+
-+	if (write)
-+		return write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private);
-+
-+	return -EROFS;
-+}
-+
-+static const struct rtw_proc_ops rtw_mcc_proc_seq_fops = {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
-+	.proc_open = rtw_mcc_proc_open,
-+	.proc_read = seq_read,
-+	.proc_lseek = seq_lseek,
-+	.proc_release = seq_release,
-+	.proc_write = rtw_mcc_proc_write,
-+#else
-+	.owner = THIS_MODULE,
-+	.open = rtw_mcc_proc_open,
-+	.read = seq_read,
-+	.llseek = seq_lseek,
-+	.release = seq_release,
-+	.write = rtw_mcc_proc_write,
-+#endif
-+};
-+
-+static const struct rtw_proc_ops rtw_mcc_proc_sseq_fops = {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
-+	.proc_open = rtw_mcc_proc_open,
-+	.proc_read = seq_read,
-+	.proc_lseek = seq_lseek,
-+	.proc_release = single_release,
-+	.proc_write = rtw_mcc_proc_write,
-+#else
-+	.owner = THIS_MODULE,
-+	.open = rtw_mcc_proc_open,
-+	.read = seq_read,
-+	.llseek = seq_lseek,
-+	.release = single_release,
-+	.write = rtw_mcc_proc_write,
-+#endif
-+};
-+
-+struct proc_dir_entry *rtw_mcc_proc_init(struct net_device *dev)
-+{
-+	struct proc_dir_entry *dir_mcc = NULL;
-+	struct proc_dir_entry *entry = NULL;
-+	_adapter	*adapter = rtw_netdev_priv(dev);
-+	ssize_t i;
-+
-+	if (adapter->dir_dev == NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (adapter->dir_mcc != NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	dir_mcc = rtw_proc_create_dir("mcc", adapter->dir_dev, dev);
-+	if (dir_mcc == NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	adapter->dir_mcc = dir_mcc;
-+
-+	for (i = 0; i < mcc_proc_hdls_num; i++) {
-+		if (mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
-+			entry = rtw_proc_create_entry(mcc_proc_hdls[i].name, dir_mcc, &rtw_mcc_proc_seq_fops, (void *)i);
-+		else if (mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ ||
-+			 mcc_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SZSEQ)
-+			entry = rtw_proc_create_entry(mcc_proc_hdls[i].name, dir_mcc, &rtw_mcc_proc_sseq_fops, (void *)i);
-+		else
-+			entry = NULL;
-+
-+		if (!entry) {
-+			rtw_warn_on(1);
-+			goto exit;
-+		}
-+	}
-+
-+exit:
-+	return dir_mcc;
-+}
-+
-+void rtw_mcc_proc_deinit(_adapter	*adapter)
-+{
-+	struct proc_dir_entry *dir_mcc = NULL;
-+	int i;
-+
-+	dir_mcc = adapter->dir_mcc;
-+
-+	if (dir_mcc == NULL) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	for (i = 0; i < mcc_proc_hdls_num; i++)
-+		remove_proc_entry(mcc_proc_hdls[i].name, dir_mcc);
-+
-+	remove_proc_entry("mcc", adapter->dir_dev);
-+
-+	adapter->dir_mcc = NULL;
-+}
-+#endif /* CONFIG_MCC_MODE */
-+
-+struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev)
-+{
-+	struct proc_dir_entry *drv_proc = get_rtw_drv_proc();
-+	struct proc_dir_entry *dir_dev = NULL;
-+	struct proc_dir_entry *entry = NULL;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	ssize_t i;
-+
-+	if (drv_proc == NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (adapter->dir_dev != NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	dir_dev = rtw_proc_create_dir(dev->name, drv_proc, dev);
-+	if (dir_dev == NULL) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	adapter->dir_dev = dir_dev;
-+
-+	for (i = 0; i < adapter_proc_hdls_num; i++) {
-+		if (adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SEQ)
-+			entry = rtw_proc_create_entry(adapter_proc_hdls[i].name, dir_dev, &rtw_adapter_proc_seq_fops, (void *)i);
-+		else if (adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SSEQ ||
-+			 adapter_proc_hdls[i].type == RTW_PROC_HDL_TYPE_SZSEQ)
-+			entry = rtw_proc_create_entry(adapter_proc_hdls[i].name, dir_dev, &rtw_adapter_proc_sseq_fops, (void *)i);
-+		else
-+			entry = NULL;
-+
-+		if (!entry) {
-+			rtw_warn_on(1);
-+			goto exit;
-+		}
-+	}
-+
-+	rtw_odm_proc_init(dev);
-+
-+#ifdef CONFIG_MCC_MODE
-+	rtw_mcc_proc_init(dev);
-+#endif /* CONFIG_MCC_MODE */
-+
-+exit:
-+	return dir_dev;
-+}
-+
-+void rtw_adapter_proc_deinit(struct net_device *dev)
-+{
-+	struct proc_dir_entry *drv_proc = get_rtw_drv_proc();
-+	struct proc_dir_entry *dir_dev = NULL;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	int i;
-+
-+	dir_dev = adapter->dir_dev;
-+
-+	if (dir_dev == NULL) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	for (i = 0; i < adapter_proc_hdls_num; i++)
-+		remove_proc_entry(adapter_proc_hdls[i].name, dir_dev);
-+
-+	rtw_odm_proc_deinit(adapter);
-+
-+#ifdef CONFIG_MCC_MODE
-+	rtw_mcc_proc_deinit(adapter);
-+#endif /* CONFIG_MCC_MODE */
-+
-+	remove_proc_entry(dev->name, drv_proc);
-+
-+	adapter->dir_dev = NULL;
-+}
-+
-+void rtw_adapter_proc_replace(struct net_device *dev)
-+{
-+	struct proc_dir_entry *drv_proc = get_rtw_drv_proc();
-+	struct proc_dir_entry *dir_dev = NULL;
-+	_adapter *adapter = rtw_netdev_priv(dev);
-+	int i;
-+
-+	dir_dev = adapter->dir_dev;
-+
-+	if (dir_dev == NULL) {
-+		rtw_warn_on(1);
-+		return;
-+	}
-+
-+	for (i = 0; i < adapter_proc_hdls_num; i++)
-+		remove_proc_entry(adapter_proc_hdls[i].name, dir_dev);
-+
-+	rtw_odm_proc_deinit(adapter);
-+
-+#ifdef CONFIG_MCC_MODE
-+	rtw_mcc_proc_deinit(adapter);
-+#endif /* CONIG_MCC_MODE */
-+
-+	remove_proc_entry(adapter->old_ifname, drv_proc);
-+
-+	adapter->dir_dev = NULL;
-+
-+	rtw_adapter_proc_init(dev);
-+
-+}
-+
-+#endif /* CONFIG_PROC_DEBUG */
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/rtw_proc.h b/drivers/staging/rtl8723cs/os_dep/linux/rtw_proc.h
-new file mode 100644
-index 000000000000..9247e3637e31
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/rtw_proc.h
-@@ -0,0 +1,72 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_PROC_H__
-+#define __RTW_PROC_H__
-+
-+#include <linux/proc_fs.h>
-+#include <linux/seq_file.h>
-+
-+#define RTW_PROC_HDL_TYPE_SEQ	0
-+#define RTW_PROC_HDL_TYPE_SSEQ	1
-+#define RTW_PROC_HDL_TYPE_SZSEQ	2
-+
-+struct rtw_proc_hdl {
-+	char *name;
-+	u8 type;
-+	union {
-+		int (*show)(struct seq_file *, void *);
-+		struct seq_operations *seq_op;
-+		struct {
-+			int (*show)(struct seq_file *, void *);
-+			size_t size;
-+		} sz;
-+	} u;
-+	ssize_t (*write)(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data);
-+};
-+
-+#define RTW_PROC_HDL_SEQ(_name, _seq_op, _write) \
-+	{ .name = _name, .type = RTW_PROC_HDL_TYPE_SEQ, .u.seq_op = _seq_op, .write = _write}
-+
-+#define RTW_PROC_HDL_SSEQ(_name, _show, _write) \
-+	{ .name = _name, .type = RTW_PROC_HDL_TYPE_SSEQ, .u.show = _show, .write = _write}
-+
-+#define RTW_PROC_HDL_SZSEQ(_name, _show, _write, _size) \
-+	{ .name = _name, .type = RTW_PROC_HDL_TYPE_SZSEQ, .u.sz.show = _show, .write = _write, .u.sz.size = _size}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0))
-+#define rtw_proc_ops proc_ops
-+#else
-+#define rtw_proc_ops file_operations
-+#endif
-+
-+#ifdef CONFIG_PROC_DEBUG
-+
-+int rtw_drv_proc_init(void);
-+void rtw_drv_proc_deinit(void);
-+struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev);
-+void rtw_adapter_proc_deinit(struct net_device *dev);
-+void rtw_adapter_proc_replace(struct net_device *dev);
-+
-+#else /* !CONFIG_PROC_DEBUG */
-+
-+static inline int rtw_drv_proc_init(void) {return _FAIL;}
-+#define rtw_drv_proc_deinit() do {} while (0)
-+static inline struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev) {return NULL;}
-+#define rtw_adapter_proc_deinit(dev) do {} while (0)
-+#define rtw_adapter_proc_replace(dev) do {} while (0)
-+
-+#endif /* !CONFIG_PROC_DEBUG */
-+
-+#endif /* __RTW_PROC_H__ */
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/rtw_rhashtable.c b/drivers/staging/rtl8723cs/os_dep/linux/rtw_rhashtable.c
-new file mode 100644
-index 000000000000..df303b237366
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/rtw_rhashtable.c
-@@ -0,0 +1,77 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+
-+#if defined(CONFIG_RTW_WDS) || defined(CONFIG_RTW_MESH) /* for now, only promised for kernel versions we support mesh */
-+
-+int rtw_rhashtable_walk_enter(rtw_rhashtable *ht, rtw_rhashtable_iter *iter)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0))
-+	rhashtable_walk_enter((ht), (iter));
-+	return 0;
-+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0))
-+	return rhashtable_walk_init((ht), (iter), GFP_ATOMIC);
-+#else
-+	/* kernel >= 4.4.0 rhashtable_walk_init use GFP_KERNEL to alloc, spin_lock for assignment */
-+	iter->ht = ht;
-+	iter->p = NULL;
-+	iter->slot = 0;
-+	iter->skip = 0;
-+
-+	iter->walker = kmalloc(sizeof(*iter->walker), GFP_ATOMIC);
-+	if (!iter->walker)
-+		return -ENOMEM;
-+
-+	spin_lock(&ht->lock);
-+	iter->walker->tbl =
-+		rcu_dereference_protected(ht->tbl, lockdep_is_held(&ht->lock));
-+	list_add(&iter->walker->list, &iter->walker->tbl->walkers);
-+	spin_unlock(&ht->lock);
-+
-+	return 0;
-+#endif
-+}
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0))
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25))
-+static inline int is_vmalloc_addr(const void *x)
-+{
-+#ifdef CONFIG_MMU
-+	unsigned long addr = (unsigned long)x;
-+
-+	return addr >= VMALLOC_START && addr < VMALLOC_END;
-+#else
-+	return 0;
-+#endif
-+}
-+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) */
-+
-+void kvfree(const void *addr)
-+{
-+	if (is_vmalloc_addr(addr))
-+		vfree(addr);
-+	else
-+		kfree(addr);
-+}
-+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) */
-+
-+#include "rhashtable.c"
-+
-+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */
-+
-+#endif /* defined(CONFIG_RTW_WDS) || defined(CONFIG_RTW_MESH) */
-+
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/rtw_rhashtable.h b/drivers/staging/rtl8723cs/os_dep/linux/rtw_rhashtable.h
-new file mode 100644
-index 000000000000..af5ba7e4dbb0
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/rtw_rhashtable.h
-@@ -0,0 +1,67 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __RTW_RHASHTABLE_H__
-+#define __RTW_RHASHTABLE_H__
-+
-+#if defined(CONFIG_RTW_WDS) || defined(CONFIG_RTW_MESH) /* for now, only promised for kernel versions we support mesh */
-+
-+/* directly reference rhashtable in kernel */
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
-+#include <linux/rhashtable.h>
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) */
-+
-+/* Use rhashtable from kernel 4.4 */
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0))
-+#define NULLS_MARKER(value) (1UL | (((long)value) << 1))
-+#endif
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0))
-+static inline void *kmalloc_array(size_t n, size_t size, gfp_t flags)
-+{
-+	if (size != 0 && n > ULONG_MAX / size)
-+		return NULL;
-+	return __kmalloc(n * size, flags);
-+}
-+#endif
-+#include "rhashtable.h"
-+#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */
-+
-+typedef struct rhashtable rtw_rhashtable;
-+typedef struct rhash_head rtw_rhash_head;
-+typedef struct rhashtable_params rtw_rhashtable_params;
-+
-+#define rtw_rhashtable_init(ht, params) rhashtable_init(ht, params)
-+
-+typedef struct rhashtable_iter rtw_rhashtable_iter;
-+
-+int rtw_rhashtable_walk_enter(rtw_rhashtable *ht, rtw_rhashtable_iter *iter);
-+#define rtw_rhashtable_walk_exit(iter) rhashtable_walk_exit(iter)
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 16, 0))
-+#define rtw_rhashtable_walk_start(iter) rhashtable_walk_start_check(iter)
-+#else
-+#define rtw_rhashtable_walk_start(iter) rhashtable_walk_start(iter)
-+#endif
-+#define rtw_rhashtable_walk_next(iter) rhashtable_walk_next(iter)
-+#define rtw_rhashtable_walk_stop(iter) rhashtable_walk_stop(iter)
-+
-+#define rtw_rhashtable_free_and_destroy(ht, free_fn, arg) rhashtable_free_and_destroy((ht), (free_fn), (arg))
-+#define rtw_rhashtable_lookup_fast(ht, key, params) rhashtable_lookup_fast((ht), (key), (params))
-+#define rtw_rhashtable_lookup_insert_fast(ht, obj, params) rhashtable_lookup_insert_fast((ht), (obj), (params))
-+#define rtw_rhashtable_remove_fast(ht, obj, params) rhashtable_remove_fast((ht), (obj), (params))
-+
-+#endif /* defined(CONFIG_RTW_WDS) || defined(CONFIG_RTW_MESH) */
-+
-+#endif /* __RTW_RHASHTABLE_H__ */
-+
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/sdio_intf.c b/drivers/staging/rtl8723cs/os_dep/linux/sdio_intf.c
-new file mode 100644
-index 000000000000..d6494bad9591
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/sdio_intf.c
-@@ -0,0 +1,1424 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _HCI_INTF_C_
-+
-+#include <drv_types.h>
-+#include <hal_data.h>
-+#include <platform_ops.h>
-+
-+#include <linux/of.h>
-+#include <linux/of_irq.h>
-+
-+#ifndef CONFIG_SDIO_HCI
-+#error "CONFIG_SDIO_HCI shall be on!\n"
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+#include <rtl8822b_hal.h>	/* rtl8822bs_set_hal_ops() */
-+#endif /* CONFIG_RTL8822B */
-+
-+#ifdef CONFIG_RTL8822C
-+#include <rtl8822c_hal.h>
-+#endif /* CONFIG_RTL8822C */
-+
-+#ifdef CONFIG_RTL8723F
-+#include <rtl8723f_hal.h>	/* rtl8723fs_set_hal_ops() */
-+#endif /* CONFIG_RTL8723F */
-+
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+#ifdef CONFIG_ACPI
-+#include <linux/acpi.h>
-+#include <linux/acpi_gpio.h>
-+#include "rtw_android.h"
-+#endif
-+static int wlan_en_gpio = -1;
-+#endif /* CONFIG_PLATFORM_INTEL_BYT */
-+
-+#ifndef dev_to_sdio_func
-+#define dev_to_sdio_func(d)     container_of(d, struct sdio_func, dev)
-+#endif
-+
-+static const struct sdio_device_id sdio_ids[] = {
-+#ifdef CONFIG_RTL8723B
-+	{ SDIO_DEVICE(0x024c, 0xB723), .driver_data = RTL8723B},
-+#endif
-+#ifdef CONFIG_RTL8188E
-+	{ SDIO_DEVICE(0x024c, 0x8179), .driver_data = RTL8188E},
-+#endif /* CONFIG_RTL8188E */
-+
-+#ifdef CONFIG_RTL8821A
-+	{ SDIO_DEVICE(0x024c, 0x8821), .driver_data = RTL8821},
-+#endif /* CONFIG_RTL8821A */
-+
-+#ifdef CONFIG_RTL8192E
-+	{ SDIO_DEVICE(0x024c, 0x818B), .driver_data = RTL8192E},
-+#endif /* CONFIG_RTL8192E */
-+
-+#ifdef CONFIG_RTL8703B
-+	{ SDIO_DEVICE(0x024c, 0xB703), .driver_data = RTL8703B},
-+#endif
-+
-+#ifdef CONFIG_RTL8188F
-+	{SDIO_DEVICE(0x024c, 0xF179), .driver_data = RTL8188F},
-+#endif
-+
-+#ifdef CONFIG_RTL8188GTV
-+	{SDIO_DEVICE(0x024c, 0x018C), .driver_data = RTL8188GTV},
-+#endif
-+
-+#ifdef CONFIG_RTL8822B
-+	{SDIO_DEVICE(0x024c, 0xB822), .driver_data = RTL8822B},
-+#endif
-+
-+#ifdef CONFIG_RTL8723D
-+	{ SDIO_DEVICE(0x024c, 0xD723), .driver_data = RTL8723D},
-+	{ SDIO_DEVICE(0x024c, 0xD724), .driver_data = RTL8723D},
-+#endif
-+
-+#ifdef CONFIG_RTL8192F
-+	{ SDIO_DEVICE(0x024c, 0x818C), .driver_data = RTL8192F},/*A CUT*/
-+	{ SDIO_DEVICE(0x024c, 0xF192), .driver_data = RTL8192F},/*B CUT*/
-+	{ SDIO_DEVICE(0x024c, 0xA725), .driver_data = RTL8192F},/*8725AS*/
-+#endif /* CONFIG_RTL8192F */
-+
-+#ifdef CONFIG_RTL8821C
-+	{SDIO_DEVICE(0x024C, 0xB821), .driver_data = RTL8821C},
-+	{SDIO_DEVICE(0x024C, 0xC821), .driver_data = RTL8821C},
-+	{SDIO_DEVICE(0x024C, 0x8733), .driver_data = RTL8821C}, /* 8733AS */
-+	{SDIO_DEVICE(0x024C, 0xC80C), .driver_data = RTL8821C}, /* 8821CSH-VQ */
-+#endif
-+
-+#ifdef CONFIG_RTL8822C
-+	{SDIO_DEVICE(0x024c, 0xC822), .class = SDIO_CLASS_WLAN, .driver_data = RTL8822C},
-+	{SDIO_DEVICE(0x024c, 0xD821), .class = SDIO_CLASS_WLAN, .driver_data = RTL8822C}, /* 8821DS */
-+#endif
-+
-+#ifdef CONFIG_RTL8723F
-+	{SDIO_DEVICE(0x024c, 0xB733), .class = SDIO_CLASS_WLAN, .driver_data = RTL8723F},
-+#endif
-+
-+#if defined(RTW_ENABLE_WIFI_CONTROL_FUNC) /* temporarily add this to accept all sdio wlan id */
-+	{ SDIO_DEVICE_CLASS(SDIO_CLASS_WLAN) },
-+#endif
-+	{ /* end: all zeroes */				},
-+};
-+
-+MODULE_DEVICE_TABLE(sdio, sdio_ids);
-+
-+static int rtw_drv_init(struct sdio_func *func, const struct sdio_device_id *id);
-+static void rtw_dev_remove(struct sdio_func *func);
-+#ifdef CONFIG_SDIO_HOOK_DEV_SHUTDOWN
-+static void rtw_dev_shutdown(struct device *dev);
-+#endif
-+static int rtw_sdio_resume(struct device *dev);
-+static int rtw_sdio_suspend(struct device *dev);
-+extern void rtw_dev_unload(PADAPTER padapter);
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+static const struct dev_pm_ops rtw_sdio_pm_ops = {
-+	.suspend	= rtw_sdio_suspend,
-+	.resume	= rtw_sdio_resume,
-+};
-+#endif
-+
-+struct sdio_drv_priv {
-+	struct sdio_driver r871xs_drv;
-+	int drv_registered;
-+};
-+
-+static struct sdio_drv_priv sdio_drvpriv = {
-+	.r871xs_drv.probe = rtw_drv_init,
-+	.r871xs_drv.remove = rtw_dev_remove,
-+	.r871xs_drv.name = (char *)DRV_NAME,
-+	.r871xs_drv.id_table = sdio_ids,
-+	.r871xs_drv.drv = {
-+#ifdef CONFIG_SDIO_HOOK_DEV_SHUTDOWN
-+		.shutdown = rtw_dev_shutdown,
-+#endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29))
-+		.pm = &rtw_sdio_pm_ops,
-+#endif
-+	}
-+};
-+
-+static struct rtw_if_operations sdio_ops = {
-+	.read		= rtw_sdio_raw_read,
-+	.write		= rtw_sdio_raw_write,
-+};
-+
-+static void sd_sync_int_hdl(struct sdio_func *func)
-+{
-+	struct dvobj_priv *psdpriv;
-+
-+	psdpriv = sdio_get_drvdata(func);
-+
-+	if (!dvobj_get_primary_adapter(psdpriv)) {
-+		RTW_INFO("%s primary adapter == NULL\n", __func__);
-+		return;
-+	}
-+
-+	rtw_sdio_set_irq_thd(psdpriv, current);
-+	sd_int_hdl(dvobj_get_primary_adapter(psdpriv));
-+	rtw_sdio_set_irq_thd(psdpriv, NULL);
-+}
-+
-+int sdio_alloc_irq(struct dvobj_priv *dvobj)
-+{
-+	PSDIO_DATA psdio_data;
-+	struct sdio_func *func;
-+	int err;
-+
-+	psdio_data = &dvobj->intf_data;
-+	func = psdio_data->func;
-+
-+	sdio_claim_host(func);
-+
-+	err = sdio_claim_irq(func, &sd_sync_int_hdl);
-+	if (err) {
-+		dvobj->drv_dbg.dbg_sdio_alloc_irq_error_cnt++;
-+		RTW_PRINT("%s: sdio_claim_irq FAIL(%d)!\n", __func__, err);
-+	} else {
-+		dvobj->drv_dbg.dbg_sdio_alloc_irq_cnt++;
-+		dvobj->irq_alloc = 1;
-+	}
-+
-+	sdio_release_host(func);
-+
-+	return err ? _FAIL : _SUCCESS;
-+}
-+
-+void sdio_free_irq(struct dvobj_priv *dvobj)
-+{
-+	PSDIO_DATA psdio_data;
-+	struct sdio_func *func;
-+	int err;
-+
-+	if (dvobj->irq_alloc) {
-+		psdio_data = &dvobj->intf_data;
-+		func = psdio_data->func;
-+
-+		if (func) {
-+			sdio_claim_host(func);
-+			err = sdio_release_irq(func);
-+			if (err) {
-+				dvobj->drv_dbg.dbg_sdio_free_irq_error_cnt++;
-+				RTW_ERR("%s: sdio_release_irq FAIL(%d)!\n", __func__, err);
-+			} else
-+				dvobj->drv_dbg.dbg_sdio_free_irq_cnt++;
-+			sdio_release_host(func);
-+		}
-+		dvobj->irq_alloc = 0;
-+	}
-+}
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+extern unsigned int oob_irq;
-+extern unsigned int oob_gpio;
-+static irqreturn_t gpio_hostwakeup_irq_thread(int irq, void *data)
-+{
-+	PADAPTER padapter = (PADAPTER)data;
-+	RTW_PRINT("gpio_hostwakeup_irq_thread\n");
-+	/* Disable interrupt before calling handler */
-+	/* disable_irq_nosync(oob_irq); */
-+#ifdef CONFIG_PLATFORM_ARM_SUN6I
-+	return 0;
-+#else
-+	return IRQ_HANDLED;
-+#endif
-+}
-+
-+static u8 gpio_hostwakeup_alloc_irq(PADAPTER padapter)
-+{
-+	int err;
-+	u32 status = 0;
-+
-+	if (oob_irq == 0) {
-+		RTW_INFO("oob_irq ZERO!\n");
-+		return _FAIL;
-+	}
-+
-+	RTW_INFO("%s : oob_irq = %d\n", __func__, oob_irq);
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32))
-+	status = IRQF_NO_SUSPEND;
-+#endif
-+
-+	if (HIGH_ACTIVE_DEV2HST)
-+		status |= IRQF_TRIGGER_RISING;
-+	else
-+		status |= IRQF_TRIGGER_FALLING;
-+
-+	err = request_threaded_irq(oob_irq, gpio_hostwakeup_irq_thread, NULL,
-+		status, "rtw_wifi_gpio_wakeup", padapter);
-+
-+	if (err < 0) {
-+		RTW_INFO("Oops: can't allocate gpio irq %d err:%d\n", oob_irq, err);
-+		return _FALSE;
-+	} else
-+		RTW_INFO("allocate gpio irq %d ok\n", oob_irq);
-+
-+	enable_irq_wake(oob_irq);
-+
-+	return _SUCCESS;
-+}
-+
-+static void gpio_hostwakeup_free_irq(PADAPTER padapter)
-+{
-+	wifi_free_gpio(oob_gpio);
-+
-+	if (oob_irq == 0)
-+		return;
-+
-+	disable_irq_wake(oob_irq);
-+
-+	free_irq(oob_irq, padapter);
-+}
-+#endif
-+
-+void dump_sdio_card_info(void *sel, struct dvobj_priv *dvobj)
-+{
-+	PSDIO_DATA psdio_data = &dvobj->intf_data;
-+	struct mmc_card *card = psdio_data->card;
-+	int i;
-+
-+	RTW_PRINT_SEL(sel, "== SDIO Card Info ==\n");
-+	RTW_PRINT_SEL(sel, "  card: %p\n", card);
-+	RTW_PRINT_SEL(sel, "  clock: %d Hz\n", psdio_data->clock);
-+
-+	RTW_PRINT_SEL(sel, "  timing spec: ");
-+	switch (psdio_data->timing) {
-+	case MMC_TIMING_LEGACY:
-+		_RTW_PRINT_SEL(sel, "legacy");
-+		break;
-+	case MMC_TIMING_MMC_HS:
-+		_RTW_PRINT_SEL(sel, "mmc high-speed");
-+		break;
-+	case MMC_TIMING_SD_HS:
-+		_RTW_PRINT_SEL(sel, "sd high-speed");
-+		break;
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)
-+	#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
-+	case MMC_TIMING_UHS_SDR12:
-+		_RTW_PRINT_SEL(sel, "sd uhs SDR12");
-+		break;
-+	case MMC_TIMING_UHS_SDR25:
-+		_RTW_PRINT_SEL(sel, "sd uhs SDR25");
-+		break;
-+	#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0) */
-+
-+	case MMC_TIMING_UHS_SDR50:
-+		_RTW_PRINT_SEL(sel, "sd uhs SDR50");
-+		break;
-+
-+	#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)
-+	case MMC_TIMING_MMC_DDR52:
-+		_RTW_PRINT_SEL(sel, "mmc DDR52");
-+		break;
-+	#endif
-+
-+	case MMC_TIMING_UHS_SDR104:
-+		_RTW_PRINT_SEL(sel, "sd uhs SDR104");
-+		break;
-+	case MMC_TIMING_UHS_DDR50:
-+		_RTW_PRINT_SEL(sel, "sd uhs DDR50");
-+		break;
-+
-+	#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)
-+	case MMC_TIMING_MMC_HS200:
-+		_RTW_PRINT_SEL(sel, "mmc HS200");
-+		break;
-+	#endif
-+
-+	#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)
-+	case MMC_TIMING_MMC_HS400:
-+		_RTW_PRINT_SEL(sel, "mmc HS400");
-+		break;
-+	#endif
-+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
-+	default:
-+		_RTW_PRINT_SEL(sel, "unknown(%d)", psdio_data->timing);
-+		break;
-+	}
-+	_RTW_PRINT_SEL(sel, "\n");
-+
-+	RTW_PRINT_SEL(sel, "  sd3_bus_mode: %s\n", (psdio_data->sd3_bus_mode) ? "TRUE" : "FALSE");
-+
-+	rtw_warn_on(card->sdio_funcs != sdio_get_num_of_func(dvobj));
-+	RTW_PRINT_SEL(sel, "  func num: %u\n", card->sdio_funcs);
-+	for (i = 0; card->sdio_func[i]; i++) {
-+		RTW_PRINT_SEL(sel, "  func%u: %p%s\n"
-+			, card->sdio_func[i]->num, card->sdio_func[i]
-+			, psdio_data->func == card->sdio_func[i] ? " (*)" : "");
-+	}
-+
-+	RTW_PRINT_SEL(sel, "================\n");
-+}
-+
-+#define SDIO_CARD_INFO_DUMP(dvobj)	dump_sdio_card_info(RTW_DBGDUMP, dvobj)
-+
-+#ifdef DBG_SDIO
-+#if (DBG_SDIO >= 2)
-+void rtw_sdio_dbg_reg_free(struct dvobj_priv *d)
-+{
-+	struct sdio_data *sdio;
-+	u8 *buf;
-+	u32 size;
-+
-+
-+	sdio = &d->intf_data;
-+
-+	buf = sdio->dbg_msg;
-+	size = sdio->dbg_msg_size;
-+	if (buf){
-+		sdio->dbg_msg = NULL;
-+		sdio->dbg_msg_size = 0;
-+		rtw_mfree(buf, size);
-+	}
-+
-+	buf = sdio->reg_mac;
-+	if (buf) {
-+		sdio->reg_mac = NULL;
-+		rtw_mfree(buf, 0x800);
-+	}
-+
-+	buf = sdio->reg_mac_ext;
-+	if (buf) {
-+		sdio->reg_mac_ext = NULL;
-+		rtw_mfree(buf, 0x800);
-+	}
-+
-+	buf = sdio->reg_local;
-+	if (buf) {
-+		sdio->reg_local = NULL;
-+		rtw_mfree(buf, 0x100);
-+	}
-+
-+	buf = sdio->reg_cia;
-+	if (buf) {
-+		sdio->reg_cia = NULL;
-+		rtw_mfree(buf, 0x200);
-+	}
-+}
-+
-+void rtw_sdio_dbg_reg_alloc(struct dvobj_priv *d)
-+{
-+	struct sdio_data *sdio;
-+	u8 *buf;
-+
-+
-+	sdio = &d->intf_data;
-+
-+	buf = _rtw_zmalloc(0x800);
-+	if (buf)
-+		sdio->reg_mac = buf;
-+
-+	buf = _rtw_zmalloc(0x800);
-+	if (buf)
-+		sdio->reg_mac_ext = buf;
-+
-+	buf = _rtw_zmalloc(0x100);
-+	if (buf)
-+		sdio->reg_local = buf;
-+
-+	buf = _rtw_zmalloc(0x200);
-+	if (buf)
-+		sdio->reg_cia = buf;
-+}
-+#endif /* DBG_SDIO >= 2 */
-+
-+static void sdio_dbg_init(struct dvobj_priv *d)
-+{
-+	struct sdio_data *sdio;
-+
-+
-+	sdio = &d->intf_data;
-+
-+	sdio->cmd52_err_cnt = 0;
-+	sdio->cmd53_err_cnt = 0;
-+
-+#if (DBG_SDIO >= 1)
-+	sdio->reg_dump_mark = 0;
-+#endif /* DBG_SDIO >= 1 */
-+
-+#if (DBG_SDIO >= 3)
-+	sdio->dbg_enable = 0;
-+	sdio->err_stop = 0;
-+	sdio->err_test = 0;
-+	sdio->err_test_triggered = 0;
-+#endif /* DBG_SDIO >= 3 */
-+}
-+
-+static void sdio_dbg_deinit(struct dvobj_priv *d)
-+{
-+#if (DBG_SDIO >= 2)
-+	rtw_sdio_dbg_reg_free(d);
-+#endif /* DBG_SDIO >= 2 */
-+}
-+#endif /* DBG_SDIO */
-+
-+u32 sdio_init(struct dvobj_priv *dvobj)
-+{
-+	PSDIO_DATA psdio_data;
-+	struct sdio_func *func;
-+	int err;
-+
-+
-+	psdio_data = &dvobj->intf_data;
-+	func = psdio_data->func;
-+
-+	/* 3 1. init SDIO bus */
-+	sdio_claim_host(func);
-+
-+	err = sdio_enable_func(func);
-+	if (err) {
-+		dvobj->drv_dbg.dbg_sdio_init_error_cnt++;
-+		RTW_PRINT("%s: sdio_enable_func FAIL(%d)!\n", __func__, err);
-+		goto release;
-+	}
-+
-+	err = sdio_set_block_size(func, 512);
-+	if (err) {
-+		dvobj->drv_dbg.dbg_sdio_init_error_cnt++;
-+		RTW_PRINT("%s: sdio_set_block_size FAIL(%d)!\n", __func__, err);
-+		goto release;
-+	}
-+	psdio_data->block_transfer_len = 512;
-+	psdio_data->tx_block_mode = 1;
-+	psdio_data->rx_block_mode = 1;
-+
-+	psdio_data->card = func->card;
-+	psdio_data->timing = func->card->host->ios.timing;
-+	psdio_data->clock = func->card->host->ios.clock;
-+	psdio_data->func_number = func->card->sdio_funcs;
-+
-+	psdio_data->sd3_bus_mode = _FALSE;
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)
-+	if (psdio_data->timing <= MMC_TIMING_UHS_DDR50
-+		#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
-+		&& psdio_data->timing >= MMC_TIMING_UHS_SDR12
-+		#else
-+		&& psdio_data->timing >= MMC_TIMING_UHS_SDR50
-+		#endif
-+	)
-+		psdio_data->sd3_bus_mode = _TRUE;
-+#endif
-+
-+#ifdef DBG_SDIO
-+	sdio_dbg_init(dvobj);
-+#endif /* DBG_SDIO */
-+
-+	SDIO_CARD_INFO_DUMP(dvobj);
-+
-+
-+release:
-+	sdio_release_host(func);
-+
-+	if (err)
-+		return _FAIL;
-+	return _SUCCESS;
-+}
-+
-+void sdio_deinit(struct dvobj_priv *dvobj)
-+{
-+	struct sdio_func *func;
-+	int err;
-+
-+
-+
-+	func = dvobj->intf_data.func;
-+
-+	if (func) {
-+		sdio_claim_host(func);
-+		err = sdio_disable_func(func);
-+		if (err) {
-+			dvobj->drv_dbg.dbg_sdio_deinit_error_cnt++;
-+			RTW_ERR("%s: sdio_disable_func(%d)\n", __func__, err);
-+		}
-+
-+		sdio_release_host(func);
-+	}
-+
-+#ifdef DBG_SDIO
-+	sdio_dbg_deinit(dvobj);
-+#endif /* DBG_SDIO */
-+}
-+
-+u8 sdio_get_num_of_func(struct dvobj_priv *dvobj)
-+{
-+	return dvobj->intf_data.func_number;
-+}
-+
-+static void rtw_decide_chip_type_by_device_id(struct dvobj_priv *dvobj, const struct sdio_device_id  *pdid)
-+{
-+	dvobj->chip_type = pdid->driver_data;
-+
-+#if defined(CONFIG_RTL8188E)
-+	if (dvobj->chip_type == RTL8188E) {
-+		dvobj->HardwareType = HARDWARE_TYPE_RTL8188ES;
-+		RTW_INFO("CHIP TYPE: RTL8188E\n");
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8723B)
-+	if (dvobj->chip_type == RTL8723B) {
-+		dvobj->HardwareType = HARDWARE_TYPE_RTL8723BS;
-+		RTW_INFO("CHIP TYPE: RTL8723B\n");
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8821A)
-+	if (dvobj->chip_type == RTL8821) {
-+		dvobj->HardwareType = HARDWARE_TYPE_RTL8821S;
-+		RTW_INFO("CHIP TYPE: RTL8821A\n");
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8192E)
-+	if (dvobj->chip_type == RTL8192E) {
-+		dvobj->HardwareType = HARDWARE_TYPE_RTL8192ES;
-+		RTW_INFO("CHIP TYPE: RTL8192E\n");
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8703B)
-+	if (dvobj->chip_type == RTL8703B) {
-+		dvobj->HardwareType = HARDWARE_TYPE_RTL8703BS;
-+		RTW_INFO("CHIP TYPE: RTL8703B\n");
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8723D)
-+	if (dvobj->chip_type == RTL8723D) {
-+		dvobj->HardwareType = HARDWARE_TYPE_RTL8723DS;
-+		RTW_INFO("CHIP TYPE: RTL8723D\n");
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8188F)
-+	if (dvobj->chip_type == RTL8188F) {
-+		dvobj->HardwareType = HARDWARE_TYPE_RTL8188FS;
-+		RTW_INFO("CHIP TYPE: RTL8188F\n");
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8188GTV)
-+	if (dvobj->chip_type == RTL8188GTV) {
-+		dvobj->HardwareType = HARDWARE_TYPE_RTL8188GTVS;
-+		RTW_INFO("CHIP TYPE: RTL8188GTV\n");
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8822B)
-+	if (dvobj->chip_type == RTL8822B) {
-+		dvobj->HardwareType = HARDWARE_TYPE_RTL8822BS;
-+		RTW_INFO("CHIP TYPE: RTL8822B\n");
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8821C)
-+	if (dvobj->chip_type == RTL8821C) {
-+		dvobj->HardwareType = HARDWARE_TYPE_RTL8821CS;
-+		RTW_INFO("CHIP TYPE: RTL8821C\n");
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8192F)
-+	if (dvobj->chip_type == RTL8192F) {
-+		dvobj->HardwareType = HARDWARE_TYPE_RTL8192FS;
-+		RTW_INFO("CHIP TYPE: RTL8192F\n");
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8822C)
-+	if (dvobj->chip_type == RTL8822C) {
-+		dvobj->HardwareType = HARDWARE_TYPE_RTL8822CS;
-+		RTW_INFO("CHIP TYPE: RTL8822C\n");
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8723F)
-+	if (dvobj->chip_type == RTL8723F) {
-+		dvobj->HardwareType = HARDWARE_TYPE_RTL8723FS;
-+		RTW_INFO("CHIP TYPE: RTL8723F\n");
-+	}
-+#endif
-+}
-+
-+static struct dvobj_priv *sdio_dvobj_init(struct sdio_func *func, const struct sdio_device_id  *pdid)
-+{
-+	int status = _FAIL;
-+	struct dvobj_priv *dvobj = NULL;
-+	PSDIO_DATA psdio;
-+
-+	dvobj = devobj_init();
-+	if (dvobj == NULL)
-+		goto exit;
-+	dvobj->intf_ops = &sdio_ops;
-+
-+	sdio_set_drvdata(func, dvobj);
-+
-+	psdio = &dvobj->intf_data;
-+	psdio->func = func;
-+
-+	if (sdio_init(dvobj) != _SUCCESS) {
-+		goto free_dvobj;
-+	}
-+
-+	dvobj->interface_type = RTW_SDIO;
-+	rtw_decide_chip_type_by_device_id(dvobj, pdid);
-+
-+	rtw_reset_continual_io_error(dvobj);
-+	status = _SUCCESS;
-+
-+free_dvobj:
-+	if (status != _SUCCESS && dvobj) {
-+		sdio_set_drvdata(func, NULL);
-+
-+		devobj_deinit(dvobj);
-+
-+		dvobj = NULL;
-+	}
-+exit:
-+	return dvobj;
-+}
-+
-+static void sdio_dvobj_deinit(struct sdio_func *func)
-+{
-+	struct dvobj_priv *dvobj = sdio_get_drvdata(func);
-+
-+	sdio_set_drvdata(func, NULL);
-+	if (dvobj) {
-+		sdio_deinit(dvobj);
-+		sdio_free_irq(dvobj);
-+		devobj_deinit(dvobj);
-+	}
-+
-+	return;
-+}
-+
-+u8 rtw_set_hal_ops(PADAPTER padapter)
-+{
-+	/* alloc memory for HAL DATA */
-+	if (rtw_hal_data_init(padapter) == _FAIL)
-+		return _FAIL;
-+
-+#if defined(CONFIG_RTL8188E)
-+	if (rtw_get_chip_type(padapter) == RTL8188E)
-+		rtl8188es_set_hal_ops(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8723B)
-+	if (rtw_get_chip_type(padapter) == RTL8723B)
-+		rtl8723bs_set_hal_ops(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8821A)
-+	if (rtw_get_chip_type(padapter) == RTL8821)
-+		rtl8821as_set_hal_ops(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8192E)
-+	if (rtw_get_chip_type(padapter) == RTL8192E)
-+		rtl8192es_set_hal_ops(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8703B)
-+	if (rtw_get_chip_type(padapter) == RTL8703B)
-+		rtl8703bs_set_hal_ops(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8723D)
-+	if (rtw_get_chip_type(padapter) == RTL8723D)
-+		rtl8723ds_set_hal_ops(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8188F)
-+	if (rtw_get_chip_type(padapter) == RTL8188F)
-+		rtl8188fs_set_hal_ops(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8188GTV)
-+	if (rtw_get_chip_type(padapter) == RTL8188GTV)
-+		rtl8188gtvs_set_hal_ops(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8822B)
-+	if (rtw_get_chip_type(padapter) == RTL8822B)
-+		rtl8822bs_set_hal_ops(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8821C)
-+	if (rtw_get_chip_type(padapter) == RTL8821C) {
-+		if (rtl8821cs_set_hal_ops(padapter) == _FAIL)
-+			return _FAIL;
-+	}
-+#endif
-+
-+#if defined(CONFIG_RTL8192F)
-+	if (rtw_get_chip_type(padapter) == RTL8192F)
-+		rtl8192fs_set_hal_ops(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8822C)
-+	if (rtw_get_chip_type(padapter) == RTL8822C)
-+		rtl8822cs_set_hal_ops(padapter);
-+#endif
-+
-+#if defined(CONFIG_RTL8723F)
-+	if (rtw_get_chip_type(padapter) == RTL8723F)
-+		rtl8723fs_set_hal_ops(padapter);
-+#endif
-+
-+	if (rtw_hal_ops_check(padapter) == _FAIL)
-+		return _FAIL;
-+
-+	if (hal_spec_init(padapter) == _FAIL)
-+		return _FAIL;
-+
-+	return _SUCCESS;
-+}
-+
-+static void sd_intf_start(PADAPTER padapter)
-+{
-+	if (padapter == NULL) {
-+		RTW_ERR("%s: padapter is NULL!\n", __func__);
-+		return;
-+	}
-+
-+	/* hal dep */
-+	rtw_hal_enable_interrupt(padapter);
-+}
-+
-+static void sd_intf_stop(PADAPTER padapter)
-+{
-+	if (padapter == NULL) {
-+		RTW_ERR("%s: padapter is NULL!\n", __func__);
-+		return;
-+	}
-+
-+	/* hal dep */
-+	rtw_hal_disable_interrupt(padapter);
-+}
-+
-+
-+#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
-+PADAPTER g_test_adapter = NULL;
-+#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
-+
-+_adapter *rtw_sdio_primary_adapter_init(struct dvobj_priv *dvobj)
-+{
-+	int status = _FAIL;
-+	PADAPTER padapter = NULL;
-+	PSDIO_DATA psdio = &dvobj->intf_data;
-+	struct device_node *np = psdio->func->dev.of_node;
-+	const unsigned char *addr;
-+	int len;
-+
-+	padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter));
-+	if (padapter == NULL)
-+		goto exit;
-+
-+	if (loadparam(padapter) != _SUCCESS)
-+		goto free_adapter;
-+
-+#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
-+	g_test_adapter = padapter;
-+#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
-+	padapter->dvobj = dvobj;
-+
-+	rtw_set_drv_stopped(padapter);/*init*/
-+
-+	dvobj->padapters[dvobj->iface_nums++] = padapter;
-+	padapter->iface_id = IFACE_ID0;
-+
-+	/* set adapter_type/iface type for primary padapter */
-+	padapter->isprimary = _TRUE;
-+	padapter->adapter_type = PRIMARY_ADAPTER;
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+	padapter->hw_port = HW_PORT0;
-+#else
-+	padapter->hw_port = HW_PORT0;
-+#endif
-+
-+	/* 3 3. init driver special setting, interface, OS and hardware relative */
-+
-+	/* 4 3.1 set hardware operation functions */
-+	if (rtw_set_hal_ops(padapter) == _FAIL)
-+		goto free_hal_data;
-+
-+	/* 3 5. initialize Chip version */
-+	padapter->intf_start = &sd_intf_start;
-+	padapter->intf_stop = &sd_intf_stop;
-+
-+	if (rtw_init_io_priv(padapter, sdio_set_intf_ops) == _FAIL) {
-+		goto free_hal_data;
-+	}
-+
-+	rtw_hal_read_chip_version(padapter);
-+
-+	rtw_hal_chip_configure(padapter);
-+
-+#ifdef CONFIG_BT_COEXIST
-+	rtw_btcoex_Initialize(padapter);
-+#endif
-+	rtw_btcoex_wifionly_initialize(padapter);
-+
-+	/* 3 6. read efuse/eeprom data */
-+	if (rtw_hal_read_chip_info(padapter) == _FAIL)
-+		goto free_hal_data;
-+
-+	/* 3 7. init driver common data */
-+	if (rtw_init_drv_sw(padapter) == _FAIL) {
-+		goto free_hal_data;
-+	}
-+
-+	/* 3 8. get WLan MAC address */
-+	if (np && (addr = of_get_property(np, "local-mac-address", &len)) && len == ETH_ALEN) {
-+		memcpy(adapter_mac_addr(padapter), addr, ETH_ALEN);
-+	} else {
-+		rtw_macaddr_cfg(adapter_mac_addr(padapter),  get_hal_mac_addr(padapter));
-+	}
-+
-+#ifdef CONFIG_MI_WITH_MBSSID_CAM
-+	rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));
-+#endif
-+#ifdef CONFIG_P2P
-+	rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
-+#endif /* CONFIG_P2P */
-+
-+	rtw_hal_disable_interrupt(padapter);
-+
-+	RTW_INFO("bDriverStopped:%s, bSurpriseRemoved:%s, bup:%d, hw_init_completed:%d\n"
-+		, rtw_is_drv_stopped(padapter) ? "True" : "False"
-+		, rtw_is_surprise_removed(padapter) ? "True" : "False"
-+		, padapter->bup
-+		, rtw_get_hw_init_completed(padapter)
-+	);
-+
-+	status = _SUCCESS;
-+
-+free_hal_data:
-+	if (status != _SUCCESS && padapter->HalData)
-+		rtw_hal_free_data(padapter);
-+
-+free_adapter:
-+	if (status != _SUCCESS && padapter) {
-+		#ifdef RTW_HALMAC
-+		rtw_halmac_deinit_adapter(dvobj);
-+		#endif
-+		rtw_vmfree((u8 *)padapter, sizeof(*padapter));
-+		padapter = NULL;
-+	}
-+exit:
-+	return padapter;
-+}
-+
-+static void rtw_sdio_primary_adapter_deinit(_adapter *padapter)
-+{
-+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-+
-+	if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
-+		rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY);
-+
-+#ifdef CONFIG_AP_MODE
-+	if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
-+		free_mlme_ap_info(padapter);
-+		#ifdef CONFIG_HOSTAPD_MLME
-+		hostapd_mode_unload(padapter);
-+		#endif
-+	}
-+#endif
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+#ifdef CONFIG_PLATFORM_ARM_SUN6I
-+	sw_gpio_eint_set_enable(gpio_eint_wlan, 0);
-+	sw_gpio_irq_free(eint_wlan_handle);
-+#else
-+	gpio_hostwakeup_free_irq(padapter);
-+#endif
-+#endif
-+
-+	/*rtw_cancel_all_timer(if1);*/
-+
-+#ifdef CONFIG_WOWLAN
-+	adapter_to_pwrctl(padapter)->wowlan_mode = _FALSE;
-+	RTW_PRINT("%s wowlan_mode:%d\n", __func__, adapter_to_pwrctl(padapter)->wowlan_mode);
-+#endif /* CONFIG_WOWLAN */
-+
-+	rtw_dev_unload(padapter);
-+	RTW_INFO("+r871xu_dev_remove, hw_init_completed=%d\n", rtw_get_hw_init_completed(padapter));
-+
-+	rtw_free_drv_sw(padapter);
-+
-+	/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
-+	rtw_os_ndev_free(padapter);
-+
-+#ifdef RTW_HALMAC
-+	rtw_halmac_deinit_adapter(adapter_to_dvobj(padapter));
-+#endif /* RTW_HALMAC */
-+
-+	rtw_vmfree((u8 *)padapter, sizeof(_adapter));
-+
-+#ifdef CONFIG_PLATFORM_RTD2880B
-+	RTW_INFO("wlan link down\n");
-+	rtd2885_wlan_netlink_sendMsg("linkdown", "8712");
-+#endif
-+
-+#ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
-+	g_test_adapter = NULL;
-+#endif /* RTW_SUPPORT_PLATFORM_SHUTDOWN */
-+}
-+
-+/*
-+ * drv_init() - a device potentially for us
-+ *
-+ * notes: drv_init() is called when the bus driver has located a card for us to support.
-+ *        We accept the new device by returning 0.
-+ */
-+static int rtw_drv_init(
-+	struct sdio_func *func,
-+	const struct sdio_device_id *id)
-+{
-+	int status = _FAIL;
-+#ifdef CONFIG_CONCURRENT_MODE
-+	int i;
-+#endif
-+	PADAPTER padapter = NULL;
-+	struct dvobj_priv *dvobj;
-+#ifdef CONFIG_OF
-+	struct device_node *np;
-+#endif
-+
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+
-+#ifdef CONFIG_ACPI
-+	acpi_handle handle;
-+	struct acpi_device *adev;
-+#endif
-+#if defined(CONFIG_ACPI) && defined(CONFIG_GPIO_WAKEUP)
-+	handle = ACPI_HANDLE(&func->dev);
-+
-+	if (handle) {
-+		/* Dont try to do acpi pm for the wifi module */
-+		if (!handle || acpi_bus_get_device(handle, &adev))
-+			RTW_INFO("Could not get acpi pointer!\n");
-+		else {
-+			adev->flags.power_manageable = 0;
-+			RTW_INFO("Disabling ACPI power management support!\n");
-+		}
-+		oob_gpio = acpi_get_gpio_by_index(&func->dev, 0, NULL);
-+		RTW_INFO("rtw_drv_init: ACPI_HANDLE found oob_gpio %d!\n", oob_gpio);
-+		wifi_configure_gpio();
-+	} else
-+		RTW_INFO("rtw_drv_init: ACPI_HANDLE NOT found!\n");
-+#endif
-+
-+#if defined(CONFIG_ACPI)
-+	if (&func->dev && ACPI_HANDLE(&func->dev)) {
-+		wlan_en_gpio = acpi_get_gpio_by_index(&func->dev, 1, NULL);
-+		RTW_INFO("rtw_drv_init: ACPI_HANDLE found wlan_en %d!\n", wlan_en_gpio);
-+	} else
-+		RTW_INFO("rtw_drv_init: ACPI_HANDLE NOT found!\n");
-+#endif
-+#endif /* CONFIG_PLATFORM_INTEL_BYT */
-+
-+#ifdef CONFIG_OF
-+	np = func->dev.of_node;
-+	if (np) {
-+		/* make sure there are interrupts defined in the node */
-+		if (of_find_property(np, "interrupts", NULL))
-+			oob_irq = irq_of_parse_and_map(np, 0);
-+	}
-+#endif
-+
-+	dvobj = sdio_dvobj_init(func, id);
-+	if (dvobj == NULL) {
-+		goto exit;
-+	}
-+
-+	padapter = rtw_sdio_primary_adapter_init(dvobj);
-+	if (padapter == NULL) {
-+		RTW_INFO("rtw_init_primary_adapter Failed!\n");
-+		goto free_dvobj;
-+	}
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	if (padapter->registrypriv.virtual_iface_num > (CONFIG_IFACE_NUMBER - 1))
-+		padapter->registrypriv.virtual_iface_num = (CONFIG_IFACE_NUMBER - 1);
-+
-+	for (i = 0; i < padapter->registrypriv.virtual_iface_num; i++) {
-+		if (rtw_drv_add_vir_if(padapter, sdio_set_intf_ops) == NULL) {
-+			RTW_INFO("rtw_drv_add_iface failed! (%d)\n", i);
-+			goto free_if_vir;
-+		}
-+	}
-+#endif
-+
-+	/* dev_alloc_name && register_netdev */
-+	if (rtw_os_ndevs_init(dvobj) != _SUCCESS)
-+		goto free_if_vir;
-+
-+#ifdef CONFIG_HOSTAPD_MLME
-+	hostapd_mode_init(padapter);
-+#endif
-+
-+#ifdef CONFIG_PLATFORM_RTD2880B
-+	RTW_INFO("wlan link up\n");
-+	rtd2885_wlan_netlink_sendMsg("linkup", "8712");
-+#endif
-+
-+	if (sdio_alloc_irq(dvobj) != _SUCCESS)
-+		goto os_ndevs_deinit;
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+#ifdef CONFIG_PLATFORM_ARM_SUN6I
-+	eint_wlan_handle = sw_gpio_irq_request(gpio_eint_wlan, TRIG_EDGE_NEGATIVE, (peint_handle)gpio_hostwakeup_irq_thread, NULL);
-+	if (!eint_wlan_handle) {
-+		RTW_INFO("%s: request irq failed\n", __func__);
-+		return -1;
-+	}
-+#else
-+	gpio_hostwakeup_alloc_irq(padapter);
-+#endif
-+#endif
-+
-+#ifdef CONFIG_GLOBAL_UI_PID
-+	if (ui_pid[1] != 0) {
-+		RTW_INFO("ui_pid[1]:%d\n", ui_pid[1]);
-+		rtw_signal_process(ui_pid[1], SIGUSR2);
-+	}
-+#endif
-+
-+
-+	status = _SUCCESS;
-+
-+os_ndevs_deinit:
-+	if (status != _SUCCESS)
-+		rtw_os_ndevs_deinit(dvobj);
-+free_if_vir:
-+	if (status != _SUCCESS) {
-+		#ifdef CONFIG_CONCURRENT_MODE
-+		rtw_drv_stop_vir_ifaces(dvobj);
-+		rtw_drv_free_vir_ifaces(dvobj);
-+		#endif
-+	}
-+
-+	if (status != _SUCCESS && padapter)
-+		rtw_sdio_primary_adapter_deinit(padapter);
-+
-+free_dvobj:
-+	if (status != _SUCCESS)
-+		sdio_dvobj_deinit(func);
-+exit:
-+	return status == _SUCCESS ? 0 : -ENODEV;
-+}
-+
-+static void rtw_dev_remove(struct sdio_func *func)
-+{
-+	struct dvobj_priv *dvobj = sdio_get_drvdata(func);
-+	struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(dvobj);
-+	PADAPTER padapter = dvobj_get_primary_adapter(dvobj);
-+
-+
-+
-+	dvobj->processing_dev_remove = _TRUE;
-+
-+	/* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
-+	rtw_os_ndevs_unregister(dvobj);
-+
-+	if (!rtw_is_surprise_removed(padapter)) {
-+		int err;
-+
-+		/* test surprise remove */
-+		sdio_claim_host(func);
-+		sdio_readb(func, 0, &err);
-+		sdio_release_host(func);
-+		if (err == -ENOMEDIUM) {
-+			rtw_set_surprise_removed(padapter);
-+			RTW_INFO("%s: device had been removed!\n", __func__);
-+		}
-+	}
-+
-+#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
-+	rtw_unregister_early_suspend(pwrctl);
-+#endif
-+
-+	if (GET_HAL_DATA(padapter)->bFWReady == _TRUE) {
-+		rtw_ps_deny(padapter, PS_DENY_DRV_REMOVE);
-+		rtw_pm_set_ips(padapter, IPS_NONE);
-+		rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
-+		LeaveAllPowerSaveMode(padapter);
-+	}
-+	rtw_set_drv_stopped(padapter);	/*for stop thread*/
-+	rtw_stop_cmd_thread(padapter);
-+#ifdef CONFIG_CONCURRENT_MODE
-+	rtw_drv_stop_vir_ifaces(dvobj);
-+#endif
-+
-+#ifdef CONFIG_BT_COEXIST
-+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
-+	if (GET_HAL_DATA(padapter)->EEPROMBluetoothCoexist)
-+		rtw_btcoex_close_socket(padapter);
-+#endif
-+	rtw_btcoex_HaltNotify(padapter);
-+#endif
-+
-+	rtw_sdio_primary_adapter_deinit(padapter);
-+
-+#ifdef CONFIG_CONCURRENT_MODE
-+	rtw_drv_free_vir_ifaces(dvobj);
-+#endif
-+
-+	sdio_dvobj_deinit(func);
-+
-+
-+}
-+
-+#ifdef CONFIG_SDIO_HOOK_DEV_SHUTDOWN
-+static void rtw_dev_shutdown(struct device *dev)
-+{
-+	struct sdio_func *func = dev_to_sdio_func(dev);
-+
-+	if (func == NULL)
-+		return;
-+
-+	RTW_INFO("==> %s !\n", __func__);
-+
-+	rtw_dev_remove(func);
-+
-+	RTW_INFO("<== %s !\n", __func__);
-+}
-+#endif
-+
-+extern int pm_netdev_open(struct net_device *pnetdev, u8 bnormal);
-+extern int pm_netdev_close(struct net_device *pnetdev, u8 bnormal);
-+
-+static int rtw_sdio_suspend(struct device *dev)
-+{
-+	struct sdio_func *func = dev_to_sdio_func(dev);
-+	struct dvobj_priv *psdpriv;
-+	struct pwrctrl_priv *pwrpriv = NULL;
-+	_adapter *padapter = NULL;
-+	struct debug_priv *pdbgpriv = NULL;
-+	int ret = 0;
-+#ifdef CONFIG_RTW_SDIO_PM_KEEP_POWER
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34))
-+	mmc_pm_flag_t pm_flag = 0;
-+#endif
-+#endif
-+
-+	if (dev == NULL)
-+		goto exit;
-+
-+	psdpriv = sdio_get_drvdata(func);
-+	if (psdpriv == NULL)
-+		goto exit;
-+
-+	pwrpriv = dvobj_to_pwrctl(psdpriv);
-+	padapter = dvobj_get_primary_adapter(psdpriv);
-+	pdbgpriv = &psdpriv->drv_dbg;
-+	if (rtw_is_drv_stopped(padapter)) {
-+		RTW_INFO("%s bDriverStopped == _TRUE\n", __func__);
-+		goto exit;
-+	}
-+
-+	if (pwrpriv->bInSuspend == _TRUE) {
-+		RTW_INFO("%s bInSuspend = %d\n", __func__, pwrpriv->bInSuspend);
-+		pdbgpriv->dbg_suspend_error_cnt++;
-+		goto exit;
-+	}
-+
-+	ret = rtw_suspend_common(padapter);
-+
-+#ifdef CONFIG_RTW_SDIO_PM_KEEP_POWER
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34))
-+	/* Android 4.0 don't support WIFI close power */
-+	/* or power down or clock will close after wifi resume, */
-+	/* this is sprd's bug in Android 4.0, but sprd don't */
-+	/* want to fix it. */
-+	/* we have test power under 8723as, power consumption is ok */
-+	pm_flag = sdio_get_host_pm_caps(func);
-+	RTW_INFO("cmd: %s: suspend: PM flag = 0x%x\n", sdio_func_id(func), pm_flag);
-+	if (!(pm_flag & MMC_PM_KEEP_POWER)) {
-+		RTW_INFO("%s: cannot remain alive while host is suspended\n", sdio_func_id(func));
-+		if (pdbgpriv)
-+			pdbgpriv->dbg_suspend_error_cnt++;
-+		return -ENOSYS;
-+	} else {
-+		RTW_INFO("cmd: suspend with MMC_PM_KEEP_POWER\n");
-+		sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
-+	}
-+#endif
-+#endif
-+exit:
-+	return ret;
-+}
-+int rtw_resume_process(_adapter *padapter)
-+{
-+	struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-+	struct dvobj_priv *psdpriv = padapter->dvobj;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+
-+	if (pwrpriv->bInSuspend == _FALSE) {
-+		pdbgpriv->dbg_resume_error_cnt++;
-+		RTW_INFO("%s bInSuspend = %d\n", __FUNCTION__, pwrpriv->bInSuspend);
-+		return -1;
-+	}
-+
-+	return rtw_resume_common(padapter);
-+}
-+
-+static int rtw_sdio_resume(struct device *dev)
-+{
-+	struct sdio_func *func = dev_to_sdio_func(dev);
-+	struct dvobj_priv *psdpriv = sdio_get_drvdata(func);
-+	struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(psdpriv);
-+	_adapter *padapter = dvobj_get_primary_adapter(psdpriv);
-+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
-+	int ret = 0;
-+	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-+
-+	RTW_INFO("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid);
-+
-+	pdbgpriv->dbg_resume_cnt++;
-+
-+#ifdef CONFIG_PLATFORM_ROCKCHIPS
-+	if (0)
-+#else
-+	if (pwrpriv->wowlan_mode || pwrpriv->wowlan_ap_mode)
-+#endif
-+	{
-+		rtw_resume_lock_suspend();
-+		ret = rtw_resume_process(padapter);
-+		rtw_resume_unlock_suspend();
-+	} else {
-+#ifdef CONFIG_RESUME_IN_WORKQUEUE
-+		rtw_resume_in_workqueue(pwrpriv);
-+#else
-+		if (rtw_is_earlysuspend_registered(pwrpriv)) {
-+			/* jeff: bypass resume here, do in late_resume */
-+			rtw_set_do_late_resume(pwrpriv, _TRUE);
-+		} else {
-+			rtw_resume_lock_suspend();
-+			ret = rtw_resume_process(padapter);
-+			rtw_resume_unlock_suspend();
-+		}
-+#endif
-+	}
-+	pmlmeext->last_scan_time = rtw_get_current_time();
-+	RTW_INFO("<========  %s return %d\n", __FUNCTION__, ret);
-+	return ret;
-+
-+}
-+
-+static int rtw_drv_entry(void)
-+{
-+	int ret = 0;
-+
-+	RTW_PRINT("module init start\n");
-+	dump_drv_version(RTW_DBGDUMP);
-+#ifdef BTCOEXVERSION
-+	RTW_PRINT(DRV_NAME" BT-Coex version = %s\n", BTCOEXVERSION);
-+#endif /* BTCOEXVERSION */
-+
-+#ifndef CONFIG_PLATFORM_INTEL_BYT
-+	rtw_android_wifictrl_func_add();
-+#endif /* !CONFIG_PLATFORM_INTEL_BYT */
-+
-+	ret = platform_wifi_power_on();
-+	if (ret) {
-+		RTW_INFO("%s: power on failed!!(%d)\n", __FUNCTION__, ret);
-+		ret = -1;
-+		goto exit;
-+	}
-+
-+	sdio_drvpriv.drv_registered = _TRUE;
-+	rtw_suspend_lock_init();
-+	rtw_drv_proc_init();
-+	rtw_nlrtw_init();
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+	cmap_intfs_init();
-+#endif
-+	rtw_ndev_notifier_register();
-+	rtw_inetaddr_notifier_register();
-+
-+	ret = sdio_register_driver(&sdio_drvpriv.r871xs_drv);
-+	if (ret != 0) {
-+		sdio_drvpriv.drv_registered = _FALSE;
-+		rtw_suspend_lock_uninit();
-+		rtw_drv_proc_deinit();
-+		rtw_nlrtw_deinit();
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+		cmap_intfs_deinit();
-+#endif
-+		rtw_ndev_notifier_unregister();
-+		rtw_inetaddr_notifier_unregister();
-+		RTW_INFO("%s: register driver failed!!(%d)\n", __FUNCTION__, ret);
-+		goto poweroff;
-+	}
-+
-+	goto exit;
-+
-+poweroff:
-+	platform_wifi_power_off();
-+
-+exit:
-+	RTW_PRINT("module init ret=%d\n", ret);
-+	return ret;
-+}
-+
-+static void rtw_drv_halt(void)
-+{
-+	RTW_PRINT("module exit start\n");
-+
-+	sdio_drvpriv.drv_registered = _FALSE;
-+
-+	sdio_unregister_driver(&sdio_drvpriv.r871xs_drv);
-+
-+	rtw_android_wifictrl_func_del();
-+
-+	platform_wifi_power_off();
-+
-+	rtw_suspend_lock_uninit();
-+	rtw_drv_proc_deinit();
-+	rtw_nlrtw_deinit();
-+#ifdef CONFIG_PLATFORM_CMAP_INTFS
-+	cmap_intfs_deinit();
-+#endif
-+	rtw_ndev_notifier_unregister();
-+	rtw_inetaddr_notifier_unregister();
-+
-+	RTW_PRINT("module exit success\n");
-+
-+	rtw_mstat_dump(RTW_DBGDUMP);
-+}
-+
-+#ifdef CONFIG_PLATFORM_INTEL_BYT
-+int rtw_sdio_set_power(int on)
-+{
-+
-+	if (wlan_en_gpio >= 0) {
-+		if (on)
-+			gpio_set_value(wlan_en_gpio, 1);
-+		else
-+			gpio_set_value(wlan_en_gpio, 0);
-+	}
-+
-+	return 0;
-+}
-+#endif /* CONFIG_PLATFORM_INTEL_BYT */
-+
-+module_init(rtw_drv_entry);
-+module_exit(rtw_drv_halt);
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/sdio_ops_linux.c b/drivers/staging/rtl8723cs/os_dep/linux/sdio_ops_linux.c
-new file mode 100644
-index 000000000000..af6a9636ec37
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/sdio_ops_linux.c
-@@ -0,0 +1,1347 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2019 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _SDIO_OPS_LINUX_C_
-+
-+#include <drv_types.h>
-+
-+inline bool rtw_is_sdio30(_adapter *adapter)
-+{
-+	struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
-+	PSDIO_DATA psdio_data = &dvobj->intf_data;
-+
-+	return (psdio_data->sd3_bus_mode) ? _TRUE : _FALSE;
-+}
-+
-+static bool rtw_sdio_claim_host_needed(struct sdio_func *func)
-+{
-+	struct dvobj_priv *dvobj = sdio_get_drvdata(func);
-+	PSDIO_DATA sdio_data = &dvobj->intf_data;
-+
-+	if (sdio_data->sys_sdio_irq_thd && sdio_data->sys_sdio_irq_thd == current)
-+		return _FALSE;
-+	return _TRUE;
-+}
-+
-+inline void rtw_sdio_set_irq_thd(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl)
-+{
-+	PSDIO_DATA sdio_data = &dvobj->intf_data;
-+
-+	sdio_data->sys_sdio_irq_thd = thd_hdl;
-+}
-+#ifndef RTW_HALMAC
-+u8 sd_f0_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	u8 v = 0;
-+	struct sdio_func *func;
-+	bool claim_needed;
-+
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return v;
-+	}
-+
-+	func = psdio->func;
-+	claim_needed = rtw_sdio_claim_host_needed(func);
-+
-+	if (claim_needed)
-+		sdio_claim_host(func);
-+	v = sdio_f0_readb(func, addr, err);
-+	if (claim_needed)
-+		sdio_release_host(func);
-+	if (err && *err)
-+		RTW_ERR("%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr);
-+
-+
-+	return v;
-+}
-+
-+void sd_f0_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	struct sdio_func *func;
-+	bool claim_needed;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return;
-+	}
-+
-+	func = psdio->func;
-+	claim_needed = rtw_sdio_claim_host_needed(func);
-+
-+	if (claim_needed)
-+		sdio_claim_host(func);
-+	sdio_f0_writeb(func, v, addr, err);
-+	if (claim_needed)
-+		sdio_release_host(func);
-+	if (err && *err)
-+		RTW_ERR("%s: FAIL!(%d) addr=0x%05x val=0x%02x\n", __func__, *err, addr, v);
-+
-+}
-+
-+/*
-+ * Return:
-+ *	0		Success
-+ *	others	Fail
-+ */
-+s32 _sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	int err = 0, i;
-+	struct sdio_func *func;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return err;
-+	}
-+
-+	func = psdio->func;
-+
-+	for (i = 0; i < cnt; i++) {
-+		pdata[i] = sdio_readb(func, addr + i, &err);
-+		if (err) {
-+			RTW_ERR("%s: FAIL!(%d) addr=0x%05x\n", __func__, err, addr + i);
-+			break;
-+		}
-+	}
-+
-+
-+	return err;
-+}
-+
-+/*
-+ * Return:
-+ *	0		Success
-+ *	others	Fail
-+ */
-+s32 sd_cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	int err = 0, i;
-+	struct sdio_func *func;
-+	bool claim_needed;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return err;
-+	}
-+
-+	func = psdio->func;
-+	claim_needed = rtw_sdio_claim_host_needed(func);
-+
-+	if (claim_needed)
-+		sdio_claim_host(func);
-+	err = _sd_cmd52_read(pintfhdl, addr, cnt, pdata);
-+	if (claim_needed)
-+		sdio_release_host(func);
-+
-+
-+	return err;
-+}
-+
-+/*
-+ * Return:
-+ *	0		Success
-+ *	others	Fail
-+ */
-+s32 _sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	int err = 0, i;
-+	struct sdio_func *func;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return err;
-+	}
-+
-+	func = psdio->func;
-+
-+	for (i = 0; i < cnt; i++) {
-+		sdio_writeb(func, pdata[i], addr + i, &err);
-+		if (err) {
-+			RTW_ERR("%s: FAIL!(%d) addr=0x%05x val=0x%02x\n", __func__, err, addr + i, pdata[i]);
-+			break;
-+		}
-+	}
-+
-+
-+	return err;
-+}
-+
-+/*
-+ * Return:
-+ *	0		Success
-+ *	others	Fail
-+ */
-+s32 sd_cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pdata)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	int err = 0, i;
-+	struct sdio_func *func;
-+	bool claim_needed;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return err;
-+	}
-+
-+	func = psdio->func;
-+	claim_needed = rtw_sdio_claim_host_needed(func);
-+
-+	if (claim_needed)
-+		sdio_claim_host(func);
-+	err = _sd_cmd52_write(pintfhdl, addr, cnt, pdata);
-+	if (claim_needed)
-+		sdio_release_host(func);
-+
-+
-+	return err;
-+}
-+
-+u8 _sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	u8 v = 0;
-+	struct sdio_func *func;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return v;
-+	}
-+
-+	func = psdio->func;
-+
-+	v = sdio_readb(func, addr, err);
-+
-+	if (err && *err)
-+		RTW_ERR("%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr);
-+
-+
-+	return v;
-+}
-+
-+u8 sd_read8(struct intf_hdl *pintfhdl, u32 addr, s32 *err)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	u8 v = 0;
-+	struct sdio_func *func;
-+	bool claim_needed;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return v;
-+	}
-+
-+	func = psdio->func;
-+	claim_needed = rtw_sdio_claim_host_needed(func);
-+
-+	if (claim_needed)
-+		sdio_claim_host(func);
-+	v = sdio_readb(func, addr, err);
-+	if (claim_needed)
-+		sdio_release_host(func);
-+	if (err && *err)
-+		RTW_ERR("%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr);
-+
-+
-+	return v;
-+}
-+
-+u16 sd_read16(struct intf_hdl *pintfhdl, u32 addr, s32 *err)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	u16 v = 0;
-+	struct sdio_func *func;
-+	bool claim_needed;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return v;
-+	}
-+
-+	func = psdio->func;
-+	claim_needed = rtw_sdio_claim_host_needed(func);
-+
-+	if (claim_needed)
-+		sdio_claim_host(func);
-+	v = sdio_readw(func, addr, err);
-+	if (claim_needed)
-+		sdio_release_host(func);
-+	if (err && *err)
-+		RTW_ERR("%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr);
-+
-+
-+	return  v;
-+}
-+
-+u32 _sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	u32 v = 0;
-+	struct sdio_func *func;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return v;
-+	}
-+
-+	func = psdio->func;
-+
-+	v = sdio_readl(func, addr, err);
-+
-+	if (err && *err) {
-+		int i;
-+
-+		RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x\n", __func__, *err, addr, v);
-+
-+		*err = 0;
-+		for (i = 0; i < SD_IO_TRY_CNT; i++) {
-+			/* sdio_claim_host(func); */
-+			v = sdio_readl(func, addr, err);
-+			/* sdio_release_host(func); */
-+			if (*err == 0) {
-+				rtw_reset_continual_io_error(psdiodev);
-+				break;
-+			} else {
-+				RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
-+				if ((-ESHUTDOWN == *err) || (-ENODEV == *err))
-+					rtw_set_surprise_removed(padapter);
-+
-+				if (rtw_inc_and_chk_continual_io_error(psdiodev) == _TRUE) {
-+					rtw_set_surprise_removed(padapter);
-+					break;
-+				}
-+
-+			}
-+		}
-+
-+		if (i == SD_IO_TRY_CNT)
-+			RTW_ERR("%s: FAIL!(%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
-+		else
-+			RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
-+
-+	}
-+
-+
-+	return  v;
-+}
-+
-+u32 sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	u32 v = 0;
-+	struct sdio_func *func;
-+	bool claim_needed;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return v;
-+	}
-+
-+	func = psdio->func;
-+	claim_needed = rtw_sdio_claim_host_needed(func);
-+
-+	if (claim_needed)
-+		sdio_claim_host(func);
-+	v = sdio_readl(func, addr, err);
-+	if (claim_needed)
-+		sdio_release_host(func);
-+
-+	if (err && *err) {
-+		int i;
-+
-+		RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x\n", __func__, *err, addr, v);
-+
-+		*err = 0;
-+		for (i = 0; i < SD_IO_TRY_CNT; i++) {
-+			if (claim_needed)
-+				sdio_claim_host(func);
-+			v = sdio_readl(func, addr, err);
-+			if (claim_needed)
-+				sdio_release_host(func);
-+
-+			if (*err == 0) {
-+				rtw_reset_continual_io_error(psdiodev);
-+				break;
-+			} else {
-+				RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
-+				if ((-ESHUTDOWN == *err) || (-ENODEV == *err))
-+					rtw_set_surprise_removed(padapter);
-+
-+				if (rtw_inc_and_chk_continual_io_error(psdiodev) == _TRUE) {
-+					rtw_set_surprise_removed(padapter);
-+					break;
-+				}
-+			}
-+		}
-+
-+		if (i == SD_IO_TRY_CNT)
-+			RTW_ERR("%s: FAIL!(%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
-+		else
-+			RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
-+
-+	}
-+
-+
-+	return  v;
-+}
-+
-+void sd_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	struct sdio_func *func;
-+	bool claim_needed;
-+
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return ;
-+	}
-+
-+	func = psdio->func;
-+	claim_needed = rtw_sdio_claim_host_needed(func);
-+
-+	if (claim_needed)
-+		sdio_claim_host(func);
-+	sdio_writeb(func, v, addr, err);
-+	if (claim_needed)
-+		sdio_release_host(func);
-+	if (err && *err)
-+		RTW_ERR("%s: FAIL!(%d) addr=0x%05x val=0x%02x\n", __func__, *err, addr, v);
-+
-+}
-+
-+void sd_write16(struct intf_hdl *pintfhdl, u32 addr, u16 v, s32 *err)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	struct sdio_func *func;
-+	bool claim_needed;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return ;
-+	}
-+
-+	func = psdio->func;
-+	claim_needed = rtw_sdio_claim_host_needed(func);
-+
-+	if (claim_needed)
-+		sdio_claim_host(func);
-+	sdio_writew(func, v, addr, err);
-+	if (claim_needed)
-+		sdio_release_host(func);
-+	if (err && *err)
-+		RTW_ERR("%s: FAIL!(%d) addr=0x%05x val=0x%04x\n", __func__, *err, addr, v);
-+
-+}
-+
-+void _sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	struct sdio_func *func;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return ;
-+	}
-+
-+	func = psdio->func;
-+
-+	sdio_writel(func, v, addr, err);
-+
-+	if (err && *err) {
-+		int i;
-+
-+		RTW_ERR("%s: (%d) addr=0x%05x val=0x%08x\n", __func__, *err, addr, v);
-+
-+		*err = 0;
-+		for (i = 0; i < SD_IO_TRY_CNT; i++) {
-+			sdio_writel(func, v, addr, err);
-+			if (*err == 0) {
-+				rtw_reset_continual_io_error(psdiodev);
-+				break;
-+			} else {
-+				RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
-+				if ((-ESHUTDOWN == *err) || (-ENODEV == *err))
-+					rtw_set_surprise_removed(padapter);
-+
-+				if (rtw_inc_and_chk_continual_io_error(psdiodev) == _TRUE) {
-+					rtw_set_surprise_removed(padapter);
-+					break;
-+				}
-+			}
-+		}
-+
-+		if (i == SD_IO_TRY_CNT)
-+			RTW_ERR("%s: FAIL!(%d) addr=0x%05x val=0x%08x, try_cnt=%d\n", __func__, *err, addr, v, i);
-+		else
-+			RTW_ERR("%s: (%d) addr=0x%05x val=0x%08x, try_cnt=%d\n", __func__, *err, addr, v, i);
-+
-+	}
-+
-+}
-+
-+void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+	struct sdio_func *func;
-+	bool claim_needed;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return ;
-+	}
-+
-+	func = psdio->func;
-+	claim_needed = rtw_sdio_claim_host_needed(func);
-+
-+	if (claim_needed)
-+		sdio_claim_host(func);
-+	sdio_writel(func, v, addr, err);
-+	if (claim_needed)
-+		sdio_release_host(func);
-+
-+	if (err && *err) {
-+		int i;
-+
-+		RTW_ERR("%s: (%d) addr=0x%05x val=0x%08x\n", __func__, *err, addr, v);
-+
-+		*err = 0;
-+		for (i = 0; i < SD_IO_TRY_CNT; i++) {
-+			if (claim_needed)
-+				sdio_claim_host(func);
-+			sdio_writel(func, v, addr, err);
-+			if (claim_needed)
-+				sdio_release_host(func);
-+			if (*err == 0) {
-+				rtw_reset_continual_io_error(psdiodev);
-+				break;
-+			} else {
-+				RTW_ERR("%s: (%d) addr=0x%05x, val=0x%x, try_cnt=%d\n", __func__, *err, addr, v, i);
-+				if ((-ESHUTDOWN == *err) || (-ENODEV == *err))
-+					rtw_set_surprise_removed(padapter);
-+
-+				if (rtw_inc_and_chk_continual_io_error(psdiodev) == _TRUE) {
-+					rtw_set_surprise_removed(padapter);
-+					break;
-+				}
-+			}
-+		}
-+
-+		if (i == SD_IO_TRY_CNT)
-+			RTW_ERR("%s: FAIL!(%d) addr=0x%05x val=0x%08x, try_cnt=%d\n", __func__, *err, addr, v, i);
-+		else
-+			RTW_ERR("%s: (%d) addr=0x%05x val=0x%08x, try_cnt=%d\n", __func__, *err, addr, v, i);
-+	}
-+
-+}
-+#endif /* !RTW_HALMAC */
-+
-+/*
-+ * Use CMD53 to read data from SDIO device.
-+ * This function MUST be called after sdio_claim_host() or
-+ * in SDIO ISR(host had been claimed).
-+ *
-+ * Parameters:
-+ *	psdio	pointer of SDIO_DATA
-+ *	addr	address to read
-+ *	cnt		amount to read
-+ *	pdata	pointer to put data, this should be a "DMA:able scratch buffer"!
-+ *
-+ * Return:
-+ *	0		Success
-+ *	others	Fail
-+ */
-+s32 _sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	int err = -EPERM;
-+	struct sdio_func *func;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return err;
-+	}
-+
-+	func = psdio->func;
-+
-+	if (unlikely((cnt == 1) || (cnt == 2))) {
-+		int i;
-+		u8 *pbuf = (u8 *)pdata;
-+
-+		for (i = 0; i < cnt; i++) {
-+			*(pbuf + i) = sdio_readb(func, addr + i, &err);
-+
-+			if (err) {
-+				RTW_ERR("%s: FAIL!(%d) addr=0x%05x\n", __func__, err, addr);
-+				break;
-+			}
-+		}
-+		return err;
-+	}
-+
-+	err = sdio_memcpy_fromio(func, pdata, addr, cnt);
-+	if (err)
-+		RTW_ERR("%s: FAIL(%d)! ADDR=%#x Size=%d\n", __func__, err, addr, cnt);
-+
-+	if (err == (-ESHUTDOWN) || err == (-ENODEV) || err == (-ENOMEDIUM) || err == (-ETIMEDOUT))
-+		rtw_set_surprise_removed(padapter);
-+
-+
-+	return err;
-+}
-+
-+/*
-+ * Use CMD53 to read data from SDIO device.
-+ *
-+ * Parameters:
-+ *	psdio	pointer of SDIO_DATA
-+ *	addr	address to read
-+ *	cnt		amount to read
-+ *	pdata	pointer to put data, this should be a "DMA:able scratch buffer"!
-+ *
-+ * Return:
-+ *	0		Success
-+ *	others	Fail
-+ */
-+s32 sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	struct sdio_func *func;
-+	bool claim_needed;
-+	s32 err = -EPERM;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return err;
-+	}
-+	func = psdio->func;
-+	claim_needed = rtw_sdio_claim_host_needed(func);
-+
-+	if (claim_needed)
-+		sdio_claim_host(func);
-+	err = _sd_read(pintfhdl, addr, cnt, pdata);
-+	if (claim_needed)
-+		sdio_release_host(func);
-+	return err;
-+}
-+
-+/*
-+ * Use CMD53 to write data to SDIO device.
-+ * This function MUST be called after sdio_claim_host() or
-+ * in SDIO ISR(host had been claimed).
-+ *
-+ * Parameters:
-+ *	psdio	pointer of SDIO_DATA
-+ *	addr	address to write
-+ *	cnt		amount to write
-+ *	pdata	data pointer, this should be a "DMA:able scratch buffer"!
-+ *
-+ * Return:
-+ *	0		Success
-+ *	others	Fail
-+ */
-+s32 _sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	struct sdio_func *func;
-+	u32 size;
-+	s32 err = -EPERM;
-+
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return err;
-+	}
-+
-+	func = psdio->func;
-+	/*	size = sdio_align_size(func, cnt); */
-+
-+	if (unlikely((cnt == 1) || (cnt == 2))) {
-+		int i;
-+		u8 *pbuf = (u8 *)pdata;
-+
-+		for (i = 0; i < cnt; i++) {
-+			sdio_writeb(func, *(pbuf + i), addr + i, &err);
-+			if (err) {
-+				RTW_ERR("%s: FAIL!(%d) addr=0x%05x val=0x%02x\n", __func__, err, addr, *(pbuf + i));
-+				break;
-+			}
-+		}
-+
-+		return err;
-+	}
-+
-+	size = cnt;
-+	err = sdio_memcpy_toio(func, addr, pdata, size);
-+	if (err)
-+		RTW_ERR("%s: FAIL(%d)! ADDR=%#x Size=%d(%d)\n", __func__, err, addr, cnt, size);
-+
-+
-+	return err;
-+}
-+
-+/*
-+ * Use CMD53 to write data to SDIO device.
-+ *
-+ * Parameters:
-+ *  psdio	pointer of SDIO_DATA
-+ *  addr	address to write
-+ *  cnt		amount to write
-+ *  pdata	data pointer, this should be a "DMA:able scratch buffer"!
-+ *
-+ * Return:
-+ *  0		Success
-+ *  others	Fail
-+ */
-+s32 sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata)
-+{
-+	PADAPTER padapter;
-+	struct dvobj_priv *psdiodev;
-+	PSDIO_DATA psdio;
-+
-+	struct sdio_func *func;
-+	bool claim_needed;
-+	s32 err = -EPERM;
-+	padapter = pintfhdl->padapter;
-+	psdiodev = pintfhdl->pintf_dev;
-+	psdio = &psdiodev->intf_data;
-+
-+	if (rtw_is_surprise_removed(padapter)) {
-+		/* RTW_INFO(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n",__FUNCTION__); */
-+		return err;
-+	}
-+
-+	func = psdio->func;
-+	claim_needed = rtw_sdio_claim_host_needed(func);
-+
-+	if (claim_needed)
-+		sdio_claim_host(func);
-+	err = _sd_write(pintfhdl, addr, cnt, pdata);
-+	if (claim_needed)
-+		sdio_release_host(func);
-+	return err;
-+}
-+
-+#if 1
-+/*#define RTW_SDIO_DUMP*/
-+#ifdef RTW_SDIO_DUMP
-+#define DUMP_LEN_LMT	0	/* buffer dump size limit */
-+				/* unit: byte, 0 for no limit */
-+#else 
-+#define DUMP_LEN_LMT	32
-+#endif
-+#define GET_DUMP_LEN(len)	(DUMP_LEN_LMT ? rtw_min(len, DUMP_LEN_LMT) : len)
-+
-+#ifdef DBG_SDIO
-+#if (DBG_SDIO >= 1)
-+static void sdio_dump_reg_by_cmd52(struct dvobj_priv *d,
-+				   u32 addr, size_t len, u8 *buf)
-+{
-+	struct sdio_func *func;
-+	size_t i;
-+	u8 val;
-+	u8 str[80], used = 0;
-+	u8 read_twice = 0;
-+	int error;
-+
-+
-+	if (buf)
-+		_rtw_memset(buf, 0xAE, len);
-+	func = dvobj_to_sdio_func(d);
-+	/*
-+	 * When register is WLAN IOREG,
-+	 * read twice to guarantee the result is correct.
-+	 */
-+	if (addr & 0x10000)
-+		read_twice = 1;
-+
-+	_rtw_memset(str, 0, 80);
-+	used = 0;
-+	if (addr & 0xF) {
-+		used += snprintf(str+used, (80-used), "0x%02x:\t", addr&~0xF);
-+		used += snprintf(str+used, (80-used), "%*s", (addr&0xF)*5, "");
-+	}
-+	for (i = 0; i < len; i++, addr++) {
-+		val = sdio_readb(func, addr, &error);
-+		if (read_twice)
-+			val = sdio_readb(func, addr, &error);
-+		if (error)
-+			break;
-+
-+		if (buf)
-+			buf[i] = val;
-+
-+		if (!(addr & 0xF))
-+			used += snprintf(str+used, (80-used), "0x%02x:\t", addr&~0xF);
-+		used += snprintf(str+used, (80-used), "%02x ", val);
-+		if (((i + 1) < len) && ((addr + 1) & 0xF) == 0) {
-+			dev_err(&func->dev, "%s", str);
-+			_rtw_memset(str, 0, 80);
-+			used = 0;
-+		}
-+	}
-+
-+	if (used) {
-+		dev_err(&func->dev, "%s", str);
-+		_rtw_memset(str, 0, 80);
-+		used = 0;
-+	}
-+
-+	if (error)
-+		dev_err(&func->dev, "rtw_sdio_dbg: READ 0x%02x FAIL!", addr);
-+}
-+
-+static void sdio_dump_cia(struct dvobj_priv *d, u32 addr, size_t len, u8 *buf)
-+{
-+	struct sdio_func *func;
-+	size_t i;
-+	u8 val;
-+	u8 str[80], used = 0;
-+	int error;
-+
-+
-+	if (buf)
-+		_rtw_memset(buf, 0xAE, len);
-+	func = dvobj_to_sdio_func(d);
-+
-+	_rtw_memset(str, 0, 80);
-+	used = 0;
-+	if (addr & 0xF) {
-+		used += snprintf(str+used, (80-used), "0x%02x:\t", addr&~0xF);
-+		used += snprintf(str+used, (80-used), "%*s", (addr&0xF)*5, "");
-+	}
-+	for (i = 0; i < len; i++, addr++) {
-+		val = sdio_f0_readb(func, addr, &error);
-+		if (error)
-+			break;
-+
-+		if (buf)
-+			buf[i] = val;
-+
-+		if (!(addr & 0xF))
-+			used += snprintf(str+used, (80-used), "0x%02x:\t", addr&~0xF);
-+		used += snprintf(str+used, (80-used), "%02x ", val);
-+		if (((i + 1) < len) && ((addr + 1) & 0xF) == 0) {
-+			dev_err(&func->dev, "%s", str);
-+			_rtw_memset(str, 0, 80);
-+			used = 0;
-+		}
-+	}
-+
-+	if (used) {
-+		dev_err(&func->dev, "%s", str);
-+		_rtw_memset(str, 0, 80);
-+		used = 0;
-+	}
-+
-+	if (error)
-+		dev_err(&func->dev, "rtw_sdio_dbg: READ CIA 0x%02x FAIL!",
-+			addr);
-+}
-+
-+#if (DBG_SDIO >= 2)
-+void rtw_sdio_dbg_reg_alloc(struct dvobj_priv *d);
-+#endif /* DBG_SDIO >= 2 */
-+
-+/*
-+ * Dump register when CMD53 fail
-+ */
-+static void sdio_dump_dbg_reg(struct dvobj_priv *d, u8 write,
-+			      unsigned int addr, size_t len)
-+{
-+	struct sdio_data *sdio;
-+	struct sdio_func *func;
-+	u8 *buf = NULL;
-+#if (DBG_SDIO >= 2)
-+	u8 *msg;
-+#endif /* DBG_SDIO >= 2 */
-+
-+
-+	sdio = &d->intf_data;
-+	if (sdio->reg_dump_mark)
-+		return;
-+	func = dvobj_to_sdio_func(d);
-+
-+	sdio->reg_dump_mark = sdio->cmd53_err_cnt;
-+
-+#if (DBG_SDIO >= 2)
-+	if (!sdio->dbg_msg) {
-+		msg = rtw_zmalloc(80);
-+		if (msg) {
-+			sdio->dbg_msg = msg;
-+			sdio->dbg_msg_size = 80;
-+		}
-+	}
-+	if (sdio->dbg_msg_size) {
-+		snprintf(sdio->dbg_msg, sdio->dbg_msg_size,
-+			 "CMD53 %s 0x%05x, %zu bytes FAIL "
-+			 "at err_cnt=%d",
-+			 write?"WRITE":"READ",
-+			 addr, len, sdio->reg_dump_mark);
-+	}
-+
-+	rtw_sdio_dbg_reg_alloc(d);
-+#endif /* DBG_SDIO >= 2 */
-+
-+	/* MAC register */
-+	dev_err(&func->dev, "MAC register:");
-+#if (DBG_SDIO >= 2)
-+	buf = sdio->reg_mac;
-+#endif /* DBG_SDIO >= 2 */
-+	sdio_dump_reg_by_cmd52(d, 0x10000, 0x800, buf);
-+	dev_err(&func->dev, "MAC Extend register:");
-+#if (DBG_SDIO >= 2)
-+	buf = sdio->reg_mac_ext;
-+#endif /* DBG_SDIO >= 2 */
-+	sdio_dump_reg_by_cmd52(d, 0x11000, 0x800, buf);
-+
-+	/* SDIO local register */
-+	dev_err(&func->dev, "SDIO Local register:");
-+#if (DBG_SDIO >= 2)
-+	buf = sdio->reg_local;
-+#endif /* DBG_SDIO >= 2 */
-+	sdio_dump_reg_by_cmd52(d, 0x0, 0x100, buf);
-+
-+	/* F0 */
-+	dev_err(&func->dev, "f0 register:");
-+#if (DBG_SDIO >= 2)
-+	buf = sdio->reg_cia;
-+#endif /* DBG_SDIO >= 2 */
-+	sdio_dump_cia(d, 0x0, 0x200, buf);
-+}
-+#endif /* DBG_SDIO >= 1 */
-+#endif /* DBG_SDIO */
-+
-+/**
-+ *	Returns driver error code,
-+ *	0	no error
-+ *	-1	Level 1 error, critical error and can't be recovered
-+ *	-2	Level 2 error, normal error, retry to recover is possible
-+ */
-+static int linux_io_err_to_drv_err(int err)
-+{
-+	if (!err)
-+		return 0;
-+
-+	/* critical error */
-+	if ((err == -ESHUTDOWN) ||
-+	    (err == -ENODEV) ||
-+	    (err == -ENOMEDIUM))
-+		return -1;
-+
-+	/* other error */
-+	return -2;
-+}
-+
-+/**
-+ *	rtw_sdio_raw_read - Read from SDIO device
-+ *	@d: driver object private data
-+ *	@addr: address to read
-+ *	@buf: buffer to store the data
-+ *	@len: number of bytes to read
-+ *	@fixed:
-+ *
-+ *	Reads from the address space of a SDIO device.
-+ *	Return value indicates if the transfer succeeded or not.
-+ */
-+int __must_check rtw_sdio_raw_read(struct dvobj_priv *d, unsigned int addr,
-+				   void *buf, size_t len, bool fixed)
-+{
-+	int error = -EPERM;
-+	bool f0, cmd52;
-+	struct sdio_func *func;
-+	bool claim_needed;
-+	u32 offset, i;
-+
-+
-+	func = dvobj_to_sdio_func(d);
-+	claim_needed = rtw_sdio_claim_host_needed(func);
-+	f0 = RTW_SDIO_ADDR_F0_CHK(addr);
-+	cmd52 = RTW_SDIO_ADDR_CMD52_CHK(addr);
-+
-+	/*
-+	 * Mask addr to remove driver defined bit and
-+	 * make sure addr is in valid range
-+	 */
-+	if (f0)
-+		addr &= 0xFFF;
-+	else
-+		addr &= 0x1FFFF;
-+
-+#ifdef RTW_SDIO_DUMP
-+	if (f0)
-+		dev_dbg(&func->dev, "rtw_sdio: READ F0\n");
-+	else if (cmd52)
-+		dev_dbg(&func->dev, "rtw_sdio: READ use CMD52\n");
-+	else
-+		dev_dbg(&func->dev, "rtw_sdio: READ use CMD53\n");
-+
-+	dev_dbg(&func->dev, "rtw_sdio: READ from 0x%05x\n", addr);
-+#endif /* RTW_SDIO_DUMP */
-+
-+	if (claim_needed)
-+		sdio_claim_host(func);
-+
-+	if (f0) {
-+		offset = addr;
-+		for (i = 0; i < len; i++, offset++) {
-+			((u8 *)buf)[i] = sdio_f0_readb(func, offset, &error);
-+			if (error)
-+				break;
-+#if 0
-+			dev_info(&func->dev, "%s: sdio f0 read 52 addr 0x%x, byte 0x%02x\n",
-+				 __func__, offset, ((u8 *)buf)[i]);
-+#endif
-+		}
-+	} else {
-+		if (cmd52) {
-+#ifdef RTW_SDIO_IO_DBG
-+			dev_info(&func->dev, "%s: sdio read 52 addr 0x%x, %zu bytes\n",
-+				 __func__, addr, len);
-+#endif
-+			offset = addr;
-+			for (i = 0; i < len; i++) {
-+				((u8 *)buf)[i] = sdio_readb(func, offset, &error);
-+				if (error)
-+					break;
-+#if 0
-+				dev_info(&func->dev, "%s: sdio read 52 addr 0x%x, byte 0x%02x\n",
-+					 __func__, offset, ((u8 *)buf)[i]);
-+#endif
-+				if (!fixed)
-+					offset++;
-+			}
-+		} else {
-+#ifdef RTW_SDIO_IO_DBG
-+			dev_info(&func->dev, "%s: sdio read 53 addr 0x%x, %zu bytes\n",
-+				 __func__, addr, len);
-+#endif
-+			if (fixed)
-+				error = sdio_readsb(func, buf, addr, len);
-+			else
-+				error = sdio_memcpy_fromio(func, buf, addr, len);
-+		}
-+	}
-+
-+#ifdef DBG_SDIO
-+#if (DBG_SDIO >= 3)
-+	if (!error && !f0 && !cmd52
-+	    && (d->intf_data.dbg_enable
-+		&& d->intf_data.err_test && !d->intf_data.err_test_triggered
-+		&& ((addr & 0x10000)
-+		    || (!(addr & 0xE000)
-+			&& !((addr >= 0x40) && (addr < 0x48)))))) {
-+		d->intf_data.err_test_triggered = 1;
-+		error = -ETIMEDOUT;
-+		dev_warn(&func->dev, "Simulate error(%d) READ addr=0x%05x %zu bytes",
-+			 error, addr, len);
-+	}
-+#endif /* DBG_SDIO >= 3 */
-+
-+	if (error) {
-+		if (f0 || cmd52) {
-+			d->intf_data.cmd52_err_cnt++;
-+		} else {
-+			d->intf_data.cmd53_err_cnt++;
-+#if (DBG_SDIO >= 1)
-+			sdio_dump_dbg_reg(d, 0, addr, len);
-+#endif /* DBG_SDIO >= 1 */
-+		}
-+	}
-+#endif /* DBG_SDIO */
-+
-+	if (claim_needed)
-+		sdio_release_host(func);
-+
-+#ifdef RTW_SDIO_DUMP
-+	print_hex_dump(KERN_DEBUG, "rtw_sdio: READ ",
-+		       DUMP_PREFIX_OFFSET, 16, 1,
-+		       buf, GET_DUMP_LEN(len), false);
-+#endif /* RTW_SDIO_DUMP */
-+
-+	if (WARN_ON(error)) {
-+		dev_err(&func->dev, "%s: sdio read failed (%d)\n", __func__, error);
-+#ifndef RTW_SDIO_DUMP
-+		if (f0)
-+			dev_err(&func->dev, "rtw_sdio: READ F0\n");
-+		if (cmd52)
-+			dev_err(&func->dev, "rtw_sdio: READ use CMD52\n");
-+		else
-+			dev_err(&func->dev, "rtw_sdio: READ use CMD53\n");
-+		dev_err(&func->dev, "rtw_sdio: READ from 0x%05x, %zu bytes\n", addr, len);
-+		print_hex_dump(KERN_ERR, "rtw_sdio: READ ",
-+			       DUMP_PREFIX_OFFSET, 16, 1,
-+			       buf, GET_DUMP_LEN(len), false);
-+#endif /* !RTW_SDIO_DUMP */
-+	}
-+
-+	return linux_io_err_to_drv_err(error);
-+}
-+
-+/**
-+ *	rtw_sdio_raw_write - Write to SDIO device
-+ *	@d: driver object private data
-+ *	@addr: address to write
-+ *	@buf: buffer that contains the data to write
-+ *	@len: number of bytes to write
-+ *	@fixed: address is fixed(FIFO) or incremented
-+ *
-+ *	Writes to the address space of a SDIO device.
-+ *	Return value indicates if the transfer succeeded or not.
-+ */
-+int __must_check rtw_sdio_raw_write(struct dvobj_priv *d, unsigned int addr,
-+				    void *buf, size_t len, bool fixed)
-+{
-+	int error = -EPERM;
-+	bool f0, cmd52;
-+	struct sdio_func *func;
-+	bool claim_needed;
-+	u32 offset, i;
-+
-+
-+	func = dvobj_to_sdio_func(d);
-+	claim_needed = rtw_sdio_claim_host_needed(func);
-+	f0 = RTW_SDIO_ADDR_F0_CHK(addr);
-+	cmd52 = RTW_SDIO_ADDR_CMD52_CHK(addr);
-+
-+	/*
-+	 * Mask addr to remove driver defined bit and
-+	 * make sure addr is in valid range
-+	 */
-+	if (f0)
-+		addr &= 0xFFF;
-+	else
-+		addr &= 0x1FFFF;
-+
-+#ifdef RTW_SDIO_DUMP
-+	if (f0)
-+		dev_dbg(&func->dev, "rtw_sdio: WRITE F0\n");
-+	else if (cmd52)
-+		dev_dbg(&func->dev, "rtw_sdio: WRITE use CMD52\n");
-+	else
-+		dev_dbg(&func->dev, "rtw_sdio: WRITE use CMD53\n");
-+	dev_dbg(&func->dev, "rtw_sdio: WRITE to 0x%05x\n", addr);
-+	print_hex_dump(KERN_DEBUG, "rtw_sdio: WRITE ",
-+		       DUMP_PREFIX_OFFSET, 16, 1,
-+		       buf, GET_DUMP_LEN(len), false);
-+#endif /* RTW_SDIO_DUMP */
-+
-+	if (claim_needed)
-+		sdio_claim_host(func);
-+
-+	if (f0) {
-+		offset = addr;
-+		for (i = 0; i < len; i++, offset++) {
-+			sdio_f0_writeb(func, ((u8 *)buf)[i], offset, &error);
-+			if (error)
-+				break;
-+#if 0
-+			dev_info(&func->dev, "%s: sdio f0 write 52 addr 0x%x, byte 0x%02x\n",
-+				 __func__, offset, ((u8 *)buf)[i]);
-+#endif
-+		}
-+	} else {
-+		if (cmd52) {
-+#ifdef RTW_SDIO_IO_DBG
-+			dev_info(&func->dev, "%s: sdio write 52 addr 0x%x, %zu bytes\n",
-+				 __func__, addr, len);
-+#endif
-+			offset = addr;
-+			for (i = 0; i < len; i++) {
-+				sdio_writeb(func, ((u8 *)buf)[i], offset, &error);
-+				if (error)
-+					break;
-+#if 0
-+				dev_info(&func->dev, "%s: sdio write 52 addr 0x%x, byte 0x%02x\n",
-+					 __func__, offset, ((u8 *)buf)[i]);
-+#endif
-+				if (!fixed)
-+					offset++;
-+			}
-+		} else {
-+#ifdef RTW_SDIO_IO_DBG
-+			dev_info(&func->dev, "%s: sdio write 53 addr 0x%x, %zu bytes\n",
-+				 __func__, addr, len);
-+#endif
-+			if (fixed)
-+				error = sdio_writesb(func, addr, buf, len);
-+			else
-+				error = sdio_memcpy_toio(func, addr, buf, len);
-+		}
-+	}
-+
-+#ifdef DBG_SDIO
-+	if (error) {
-+		if (f0 || cmd52) {
-+			d->intf_data.cmd52_err_cnt++;
-+		} else {
-+			d->intf_data.cmd53_err_cnt++;
-+#if (DBG_SDIO >= 1)
-+			sdio_dump_dbg_reg(d, 1, addr, len);
-+#endif /* DBG_SDIO >= 1 */
-+		}
-+	}
-+#endif /* DBG_SDIO */
-+
-+	if (claim_needed)
-+		sdio_release_host(func);
-+
-+	if (WARN_ON(error)) {
-+		dev_err(&func->dev, "%s: sdio write failed (%d)\n", __func__, error);
-+#ifndef RTW_SDIO_DUMP
-+		if (f0)
-+			dev_err(&func->dev, "rtw_sdio: WRITE F0\n");
-+		if (cmd52)
-+			dev_err(&func->dev, "rtw_sdio: WRITE use CMD52\n");
-+		else
-+			dev_err(&func->dev, "rtw_sdio: WRITE use CMD53\n");
-+		dev_err(&func->dev, "rtw_sdio: WRITE to 0x%05x, %zu bytes\n", addr, len);
-+		print_hex_dump(KERN_ERR, "rtw_sdio: WRITE ",
-+			       DUMP_PREFIX_OFFSET, 16, 1,
-+			       buf, GET_DUMP_LEN(len), false);
-+#endif /* !RTW_SDIO_DUMP */
-+	}
-+
-+	return linux_io_err_to_drv_err(error);
-+}
-+#endif
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/wifi_regd.c b/drivers/staging/rtl8723cs/os_dep/linux/wifi_regd.c
-new file mode 100644
-index 000000000000..b4b0bcd5114d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/wifi_regd.c
-@@ -0,0 +1,410 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2009-2010 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_IOCTL_CFG80211
-+static void rtw_regd_overide_flags(struct wiphy *wiphy, struct rf_ctl_t *rfctl)
-+{
-+	RT_CHANNEL_INFO *channel_set = rfctl->channel_set;
-+	u8 max_chan_nums = rfctl->max_chan_nums;
-+	struct ieee80211_supported_band *sband;
-+	struct ieee80211_channel *ch;
-+	unsigned int i, j;
-+	u16 channel;
-+	u32 freq;
-+
-+	/* all channels disable */
-+	for (i = 0; i < NUM_NL80211_BANDS; i++) {
-+		sband = wiphy->bands[i];
-+		if (!sband)
-+			continue;
-+		for (j = 0; j < sband->n_channels; j++) {
-+			ch = &sband->channels[j];
-+			if (!ch)
-+				continue;
-+			ch->flags = IEEE80211_CHAN_DISABLED;
-+		}
-+	}
-+
-+	/* channels apply by channel plans. */
-+	for (i = 0; i < max_chan_nums; i++) {
-+		channel = channel_set[i].ChannelNum;
-+		freq = rtw_ch2freq(channel);
-+		ch = ieee80211_get_channel(wiphy, freq);
-+		if (!ch) {
-+			rtw_warn_on(1);
-+			continue;
-+		}
-+
-+		/* enable */
-+		ch->flags = 0;
-+
-+		if (channel_set[i].flags & RTW_CHF_DFS) {
-+			/*
-+			* before integrating with nl80211 flow
-+			* bypass IEEE80211_CHAN_RADAR when configured with radar detection
-+			* to prevent from hostapd blocking DFS channels
-+			*/
-+			if (rtw_rfctl_dfs_domain_unknown(rfctl))
-+				ch->flags |= IEEE80211_CHAN_RADAR;
-+		}
-+
-+		if (channel_set[i].flags & RTW_CHF_NO_IR) {
-+			#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
-+			ch->flags |= IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN;
-+			#else
-+			ch->flags |= IEEE80211_CHAN_NO_IR;
-+			#endif
-+		}
-+	}
-+}
-+
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+static void rtw_regd_apply_dfs_flags(struct rf_ctl_t *rfctl)
-+{
-+	RT_CHANNEL_INFO *channel_set = rfctl->channel_set;
-+	u8 max_chan_nums = rfctl->max_chan_nums;
-+	unsigned int i;
-+	struct ieee80211_channel *chan;
-+
-+	/* channels apply by channel plans. */
-+	for (i = 0; i < max_chan_nums; i++) {
-+		chan = channel_set[i].os_chan;
-+		if (channel_set[i].flags & RTW_CHF_DFS) {
-+			/*
-+			* before integrating with nl80211 flow
-+			* clear IEEE80211_CHAN_RADAR when configured with radar detection
-+			* to prevent from hostapd blocking DFS channels
-+			*/
-+			if (!rtw_rfctl_dfs_domain_unknown(rfctl))
-+				chan->flags &= ~IEEE80211_CHAN_RADAR;
-+		}
-+	}
-+}
-+#endif
-+
-+void rtw_regd_apply_flags(struct wiphy *wiphy)
-+{
-+	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
-+	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
-+
-+	if (rfctl->regd_src == REGD_SRC_RTK_PRIV)
-+		rtw_regd_overide_flags(wiphy, rfctl);
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+	else if (rfctl->regd_src == REGD_SRC_OS)
-+		rtw_regd_apply_dfs_flags(rfctl);
-+#endif
-+	else
-+		rtw_warn_on(1);
-+}
-+
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+/* init_channel_set_from_wiphy */
-+u8 rtw_os_init_channel_set(_adapter *padapter, RT_CHANNEL_INFO *channel_set)
-+{
-+	struct wiphy *wiphy = adapter_to_wiphy(padapter);
-+	struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
-+	struct registry_priv *regsty = adapter_to_regsty(padapter);
-+	struct ieee80211_channel *chan;
-+	u8 chanset_size = 0;
-+	int i, j;
-+
-+	_rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
-+
-+	for (i = NL80211_BAND_2GHZ; i <= NL80211_BAND_5GHZ; i++) {
-+		if (!wiphy->bands[i])
-+			continue;
-+		for (j = 0; j < wiphy->bands[i]->n_channels; j++) {
-+			chan = &wiphy->bands[i]->channels[j];
-+			if (chan->flags & IEEE80211_CHAN_DISABLED)
-+				continue;
-+			if (rtw_regsty_is_excl_chs(regsty, chan->hw_value))
-+				continue;
-+
-+			if (chanset_size >= MAX_CHANNEL_NUM) {
-+				RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM);
-+				i = NL80211_BAND_5GHZ + 1;
-+				break;
-+			}
-+
-+			channel_set[chanset_size].ChannelNum = chan->hw_value;
-+			#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
-+			if (chan->flags & (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN))
-+			#else
-+			if (chan->flags & IEEE80211_CHAN_NO_IR)
-+			#endif
-+				channel_set[chanset_size].flags |= RTW_CHF_NO_IR;
-+			if (chan->flags & IEEE80211_CHAN_RADAR)
-+				channel_set[chanset_size].flags |= RTW_CHF_DFS;
-+			#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
-+			if (chan->flags & IEEE80211_CHAN_NO_HT40PLUS)
-+				channel_set[chanset_size].flags |= RTW_CHF_NO_HT40U;
-+			if (chan->flags & IEEE80211_CHAN_NO_HT40MINUS)
-+				channel_set[chanset_size].flags |= RTW_CHF_NO_HT40L;
-+			#endif
-+			#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
-+			if (chan->flags & IEEE80211_CHAN_NO_80MHZ)
-+				channel_set[chanset_size].flags |= RTW_CHF_NO_80MHZ;
-+			if (chan->flags & IEEE80211_CHAN_NO_160MHZ)
-+				channel_set[chanset_size].flags |= RTW_CHF_NO_160MHZ;
-+			#endif
-+			channel_set[chanset_size].os_chan = chan;
-+			chanset_size++;
-+		}
-+	}
-+
-+#if CONFIG_IEEE80211_BAND_5GHZ
-+	#ifdef CONFIG_DFS_MASTER
-+	for (i = 0; i < chanset_size; i++)
-+		channel_set[i].non_ocp_end_time = rtw_get_current_time();
-+	#endif
-+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-+
-+	if (chanset_size)
-+		RTW_INFO(FUNC_ADPT_FMT" ch num:%d\n"
-+			, FUNC_ADPT_ARG(padapter), chanset_size);
-+	else
-+		RTW_WARN(FUNC_ADPT_FMT" final chset has no channel\n"
-+			, FUNC_ADPT_ARG(padapter));
-+
-+	return chanset_size;
-+}
-+
-+s16 rtw_os_get_total_txpwr_regd_lmt_mbm(_adapter *adapter, u8 cch, enum channel_width bw)
-+{
-+	struct wiphy *wiphy = adapter_to_wiphy(adapter);
-+	s16 mbm = UNSPECIFIED_MBM;
-+	u8 *op_chs;
-+	u8 op_ch_num;
-+	u8 i;
-+	u32 freq;
-+	struct ieee80211_channel *ch;
-+
-+	if (!rtw_get_op_chs_by_cch_bw(cch, bw, &op_chs, &op_ch_num))
-+		goto exit;
-+
-+	for (i = 0; i < op_ch_num; i++) {
-+		freq = rtw_ch2freq(op_chs[i]);
-+		ch = ieee80211_get_channel(wiphy, freq);
-+		if (!ch) {
-+			rtw_warn_on(1);
-+			continue;
-+		}
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0))
-+		mbm = rtw_min(mbm, ch->max_reg_power * MBM_PDBM);
-+		#else
-+		/* require max_power == 0 (therefore orig_mpwr set to 0) when wiphy registration */
-+		mbm = rtw_min(mbm, ch->max_power * MBM_PDBM);
-+		#endif
-+	}
-+
-+exit:
-+	return mbm;
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
-+static enum rtw_dfs_regd nl80211_dfs_regions_to_rtw_dfs_region(enum nl80211_dfs_regions region)
-+{
-+	switch (region) {
-+	case NL80211_DFS_FCC:
-+		return RTW_DFS_REGD_FCC;
-+	case NL80211_DFS_ETSI:
-+		return RTW_DFS_REGD_ETSI;
-+	case NL80211_DFS_JP:
-+		return RTW_DFS_REGD_MKK;
-+	case NL80211_DFS_UNSET:
-+	default:
-+		return RTW_DFS_REGD_NONE;
-+	}
-+};
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) */
-+#endif /* CONFIG_REGD_SRC_FROM_OS */
-+
-+#ifdef CONFIG_RTW_DEBUG
-+static const char *nl80211_reg_initiator_str(enum nl80211_reg_initiator initiator)
-+{
-+	switch (initiator) {
-+	case NL80211_REGDOM_SET_BY_DRIVER:
-+		return "DRIVER";
-+	case NL80211_REGDOM_SET_BY_CORE:
-+		return "CORE";
-+	case NL80211_REGDOM_SET_BY_USER:
-+		return "USER";
-+	case NL80211_REGDOM_SET_BY_COUNTRY_IE:
-+		return "COUNTRY_IE";
-+	}
-+	rtw_warn_on(1);
-+	return "UNKNOWN";
-+}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+static const char *nl80211_user_reg_hint_type_str(enum nl80211_user_reg_hint_type type)
-+{
-+	switch (type) {
-+	case NL80211_USER_REG_HINT_USER:
-+		return "USER";
-+	case NL80211_USER_REG_HINT_CELL_BASE:
-+		return "CELL_BASE";
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
-+	case NL80211_USER_REG_HINT_INDOOR:
-+		return "INDOOR";
-+	#endif
-+	}
-+	rtw_warn_on(1);
-+	return "UNKNOWN";
-+}
-+#endif
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
-+static const char *nl80211_dfs_regions_str(enum nl80211_dfs_regions region)
-+{
-+	switch (region) {
-+	case NL80211_DFS_UNSET:
-+		return "UNSET";
-+	case NL80211_DFS_FCC:
-+		return "FCC";
-+	case NL80211_DFS_ETSI:
-+		return "ETSI";
-+	case NL80211_DFS_JP:
-+		return "JP";
-+	}
-+	rtw_warn_on(1);
-+	return "UNKNOWN";
-+};
-+#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) */
-+
-+static const char *environment_cap_str(enum environment_cap cap)
-+{
-+	switch (cap) {
-+	case ENVIRON_ANY:
-+		return "ANY";
-+	case ENVIRON_INDOOR:
-+		return "INDOOR";
-+	case ENVIRON_OUTDOOR:
-+		return "OUTDOOR";
-+	}
-+	rtw_warn_on(1);
-+	return "UNKNOWN";
-+}
-+
-+static void dump_requlatory_request(void *sel, struct regulatory_request *request)
-+{
-+	u8 alpha2_len;
-+
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 16, 0))
-+	alpha2_len = 3;
-+	#else
-+	alpha2_len = 2;
-+	#endif
-+
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
-+	RTW_PRINT_SEL(sel, "initiator:%s, wiphy_idx:%d, type:%s\n"
-+		, nl80211_reg_initiator_str(request->initiator)
-+		, request->wiphy_idx
-+		, nl80211_user_reg_hint_type_str(request->user_reg_hint_type));
-+	#else
-+	RTW_PRINT_SEL(sel, "initiator:%s, wiphy_idx:%d\n"
-+		, nl80211_reg_initiator_str(request->initiator)
-+		, request->wiphy_idx);
-+	#endif
-+
-+	RTW_PRINT_SEL(sel, "alpha2:%.*s\n", alpha2_len, request->alpha2);
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
-+	RTW_PRINT_SEL(sel, "dfs_region:%s\n", nl80211_dfs_regions_str(request->dfs_region));
-+	#endif
-+
-+	RTW_PRINT_SEL(sel, "intersect:%d\n", request->intersect);
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
-+	RTW_PRINT_SEL(sel, "processed:%d\n", request->processed);
-+	#endif
-+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36))
-+	RTW_PRINT_SEL(sel, "country_ie_checksum:0x%08x\n", request->country_ie_checksum);
-+	#endif
-+
-+	RTW_PRINT_SEL(sel, "country_ie_env:%s\n", environment_cap_str(request->country_ie_env));
-+}
-+#endif /* CONFIG_RTW_DEBUG */
-+
-+static void rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
-+{
-+	struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy);
-+	struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
-+	struct registry_priv *regsty = dvobj_to_regsty(dvobj);
-+
-+#ifdef CONFIG_RTW_DEBUG
-+	if (rtw_drv_log_level >= _DRV_INFO_) {
-+		RTW_INFO(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy));
-+		dump_requlatory_request(RTW_DBGDUMP, request);
-+	}
-+#endif
-+
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+	if (REGSTY_REGD_SRC_FROM_OS(regsty)) {
-+		enum rtw_dfs_regd dfs_region =  RTW_DFS_REGD_NONE;
-+
-+		#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0))
-+		dfs_region = nl80211_dfs_regions_to_rtw_dfs_region(request->dfs_region);
-+		#endif
-+
-+		/* trigger command to sync regulatory form OS */
-+		rtw_sync_os_regd_cmd(wiphy_to_adapter(wiphy), RTW_CMDF_WAIT_ACK, request->alpha2, dfs_region);
-+	} else
-+#endif
-+	{
-+		/* use alpha2 as input to select the corresponding channel plan settings defined by Realtek */
-+		switch (request->initiator) {
-+		case NL80211_REGDOM_SET_BY_DRIVER:
-+			break;
-+		case NL80211_REGDOM_SET_BY_CORE:
-+			break;
-+		case NL80211_REGDOM_SET_BY_USER:
-+			rtw_set_country(wiphy_to_adapter(wiphy), request->alpha2);
-+			break;
-+		case NL80211_REGDOM_SET_BY_COUNTRY_IE:
-+			break;
-+		}
-+
-+		rtw_regd_apply_flags(wiphy);
-+	}
-+}
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
-+static int rtw_reg_notifier_return(struct wiphy *wiphy, struct regulatory_request *request)
-+{
-+	rtw_reg_notifier(wiphy, request);
-+	return 0;
-+}
-+#endif
-+
-+int rtw_regd_init(struct wiphy *wiphy)
-+{
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0))
-+	wiphy->reg_notifier = rtw_reg_notifier_return;
-+#else
-+	wiphy->reg_notifier = rtw_reg_notifier;
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
-+	wiphy->flags &= ~WIPHY_FLAG_STRICT_REGULATORY;
-+	wiphy->flags &= ~WIPHY_FLAG_DISABLE_BEACON_HINTS;
-+#else
-+	wiphy->regulatory_flags &= ~REGULATORY_STRICT_REG;
-+	wiphy->regulatory_flags &= ~REGULATORY_DISABLE_BEACON_HINTS;
-+#endif
-+
-+	return 0;
-+}
-+#endif /* CONFIG_IOCTL_CFG80211 */
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/wifi_regd.h b/drivers/staging/rtl8723cs/os_dep/linux/wifi_regd.h
-new file mode 100644
-index 000000000000..4e147fc51dbc
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/wifi_regd.h
-@@ -0,0 +1,27 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2009-2010 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#ifndef __WIFI_REGD_H__
-+#define __WIFI_REGD_H__
-+
-+void rtw_regd_apply_flags(struct wiphy *wiphy);
-+#ifdef CONFIG_REGD_SRC_FROM_OS
-+struct _RT_CHANNEL_INFO;
-+u8 rtw_os_init_channel_set(_adapter *padapter, struct _RT_CHANNEL_INFO *channel_set);
-+s16 rtw_os_get_total_txpwr_regd_lmt_mbm(_adapter *adapter, u8 cch, enum channel_width bw);
-+#endif
-+int rtw_regd_init(struct wiphy *wiphy);
-+
-+#endif /* __WIFI_REGD_H__ */
-diff --git a/drivers/staging/rtl8723cs/os_dep/linux/xmit_linux.c b/drivers/staging/rtl8723cs/os_dep/linux/xmit_linux.c
-new file mode 100644
-index 000000000000..fdcba46c556a
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/linux/xmit_linux.c
-@@ -0,0 +1,538 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#define _XMIT_OSDEP_C_
-+
-+#include <drv_types.h>
-+
-+#define DBG_DUMP_OS_QUEUE_CTL 0
-+
-+uint rtw_remainder_len(struct pkt_file *pfile)
-+{
-+	return pfile->buf_len - ((SIZE_PTR)(pfile->cur_addr) - (SIZE_PTR)(pfile->buf_start));
-+}
-+
-+void _rtw_open_pktfile(_pkt *pktptr, struct pkt_file *pfile)
-+{
-+
-+	pfile->pkt = pktptr;
-+	pfile->cur_addr = pfile->buf_start = pktptr->data;
-+	pfile->pkt_len = pfile->buf_len = pktptr->len;
-+
-+	pfile->cur_buffer = pfile->buf_start ;
-+
-+}
-+
-+uint _rtw_pktfile_read(struct pkt_file *pfile, u8 *rmem, uint rlen)
-+{
-+	uint	len = 0;
-+
-+
-+	len =  rtw_remainder_len(pfile);
-+	len = (rlen > len) ? len : rlen;
-+
-+	if (rmem)
-+		skb_copy_bits(pfile->pkt, pfile->buf_len - pfile->pkt_len, rmem, len);
-+
-+	pfile->cur_addr += len;
-+	pfile->pkt_len -= len;
-+
-+
-+	return len;
-+}
-+
-+sint rtw_endofpktfile(struct pkt_file *pfile)
-+{
-+
-+	if (pfile->pkt_len == 0) {
-+		return _TRUE;
-+	}
-+
-+
-+	return _FALSE;
-+}
-+
-+void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib)
-+{
-+#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX	
-+	struct sk_buff *skb = (struct sk_buff *)pkt;
-+	struct iphdr *iph = NULL;
-+	struct ipv6hdr *i6ph = NULL;
-+	struct udphdr *uh = NULL;
-+	struct tcphdr *th = NULL;
-+	u8 	protocol = 0xFF;
-+
-+	if (skb->protocol == htons(ETH_P_IP)) {
-+		iph = (struct iphdr *)skb_network_header(skb);
-+		protocol = iph->protocol;
-+	} else if (skb->protocol == htons(ETH_P_IPV6)) {
-+		i6ph = (struct ipv6hdr *)skb_network_header(skb);
-+		protocol = i6ph->nexthdr;
-+	} else
-+		{}
-+
-+	/*	HW unable to compute CSUM if header & payload was be encrypted by SW(cause TXDMA error) */
-+	if (pattrib->bswenc == _TRUE) {
-+		if (skb->ip_summed == CHECKSUM_PARTIAL)
-+			skb_checksum_help(skb);
-+		return;
-+	}
-+
-+	/*	For HW rule, clear ipv4_csum & UDP/TCP_csum if it is UDP/TCP packet	*/
-+	switch (protocol) {
-+	case IPPROTO_UDP:
-+		uh = (struct udphdr *)skb_transport_header(skb);
-+		uh->check = 0;
-+		if (iph)
-+			iph->check = 0;
-+		pattrib->hw_csum = _TRUE;
-+		break;
-+	case IPPROTO_TCP:
-+		th = (struct tcphdr *)skb_transport_header(skb);
-+		th->check = 0;
-+		if (iph)
-+			iph->check = 0;
-+		pattrib->hw_csum = _TRUE;
-+		break;
-+	default:
-+		break;
-+	}
-+#endif
-+
-+}
-+
-+int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag)
-+{
-+	if (alloc_sz > 0) {
-+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX
-+		struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
-+		struct usb_device	*pusbd = pdvobjpriv->pusbdev;
-+
-+		pxmitbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)alloc_sz, &pxmitbuf->dma_transfer_addr);
-+		pxmitbuf->pbuf = pxmitbuf->pallocated_buf;
-+		if (pxmitbuf->pallocated_buf == NULL)
-+			return _FAIL;
-+#else /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
-+
-+		pxmitbuf->pallocated_buf = rtw_zmalloc(alloc_sz);
-+		if (pxmitbuf->pallocated_buf == NULL)
-+			return _FAIL;
-+
-+		pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ);
-+
-+#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
-+	}
-+
-+	if (flag) {
-+#ifdef CONFIG_USB_HCI
-+		int i;
-+		for (i = 0; i < 8; i++) {
-+			pxmitbuf->pxmit_urb[i] = usb_alloc_urb(0, GFP_KERNEL);
-+			if (pxmitbuf->pxmit_urb[i] == NULL) {
-+				RTW_INFO("pxmitbuf->pxmit_urb[i]==NULL");
-+				return _FAIL;
-+			}
-+		}
-+#endif
-+	}
-+
-+	return _SUCCESS;
-+}
-+
-+void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 free_sz, u8 flag)
-+{
-+	if (flag) {
-+#ifdef CONFIG_USB_HCI
-+		int i;
-+
-+		for (i = 0; i < 8; i++) {
-+			if (pxmitbuf->pxmit_urb[i]) {
-+				/* usb_kill_urb(pxmitbuf->pxmit_urb[i]); */
-+				usb_free_urb(pxmitbuf->pxmit_urb[i]);
-+			}
-+		}
-+#endif
-+	}
-+
-+	if (free_sz > 0) {
-+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX
-+		struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
-+		struct usb_device	*pusbd = pdvobjpriv->pusbdev;
-+
-+		rtw_usb_buffer_free(pusbd, (size_t)free_sz, pxmitbuf->pallocated_buf, pxmitbuf->dma_transfer_addr);
-+		pxmitbuf->pallocated_buf =  NULL;
-+		pxmitbuf->dma_transfer_addr = 0;
-+#else	/* CONFIG_USE_USB_BUFFER_ALLOC_TX */
-+		if (pxmitbuf->pallocated_buf)
-+			rtw_mfree(pxmitbuf->pallocated_buf, free_sz);
-+#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */
-+	}
-+}
-+
-+void dump_os_queue(void *sel, _adapter *padapter)
-+{
-+	struct net_device *ndev = padapter->pnetdev;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	int i;
-+
-+	for (i = 0; i < 4; i++) {
-+		RTW_PRINT_SEL(sel, "os_queue[%d]:%s\n"
-+			, i, __netif_subqueue_stopped(ndev, i) ? "stopped" : "waked");
-+	}
-+#else
-+	RTW_PRINT_SEL(sel, "os_queue:%s\n"
-+		      , netif_queue_stopped(ndev) ? "stopped" : "waked");
-+#endif
-+}
-+
-+#define WMM_XMIT_THRESHOLD	(NR_XMITFRAME*2/5)
-+
-+static inline bool rtw_os_need_wake_queue(_adapter *padapter, u16 os_qid)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+
-+	if (padapter->registrypriv.wifi_spec) {
-+		if (pxmitpriv->hwxmits[os_qid].accnt < WMM_XMIT_THRESHOLD)
-+			return _TRUE;
-+#ifdef DBG_CONFIG_ERROR_DETECT
-+#ifdef DBG_CONFIG_ERROR_RESET
-+	} else if (rtw_hal_sreset_inprogress(padapter) == _TRUE) {
-+		return _FALSE;
-+#endif/* #ifdef DBG_CONFIG_ERROR_RESET */
-+#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
-+	} else {
-+#ifdef CONFIG_MCC_MODE
-+		if (MCC_EN(padapter)) {
-+			if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)
-+			    && MCC_STOP(padapter))
-+				return _FALSE;
-+		}
-+#endif /* CONFIG_MCC_MODE */
-+		return _TRUE;
-+	}
-+	return _FALSE;
-+#else
-+#ifdef CONFIG_MCC_MODE
-+	if (MCC_EN(padapter)) {
-+		if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)
-+		    && MCC_STOP(padapter))
-+			return _FALSE;
-+	}
-+#endif /* CONFIG_MCC_MODE */
-+	return _TRUE;
-+#endif
-+}
-+
-+static inline bool rtw_os_need_stop_queue(_adapter *padapter, u16 os_qid)
-+{
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	if (padapter->registrypriv.wifi_spec) {
-+		/* No free space for Tx, tx_worker is too slow */
-+		if (pxmitpriv->hwxmits[os_qid].accnt > WMM_XMIT_THRESHOLD)
-+			return _TRUE;
-+	} else {
-+		if (pxmitpriv->free_xmitframe_cnt <= 4)
-+			return _TRUE;
-+	}
-+#else
-+	if (pxmitpriv->free_xmitframe_cnt <= 4)
-+		return _TRUE;
-+#endif
-+	return _FALSE;
-+}
-+
-+void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt)
-+{
-+	rtw_skb_free(pkt);
-+}
-+
-+void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe)
-+{
-+	if (pxframe->pkt)
-+		rtw_os_pkt_complete(padapter, pxframe->pkt);
-+
-+	pxframe->pkt = NULL;
-+}
-+
-+void rtw_os_xmit_schedule(_adapter *padapter)
-+{
-+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
-+	_adapter *pri_adapter;
-+
-+	if (!padapter)
-+		return;
-+	pri_adapter = GET_PRIMARY_ADAPTER(padapter);
-+
-+	if (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE)
-+		_rtw_up_sema(&pri_adapter->xmitpriv.xmit_sema);
-+
-+
-+#else
-+	_irqL  irqL;
-+	struct xmit_priv *pxmitpriv;
-+
-+	if (!padapter)
-+		return;
-+
-+	pxmitpriv = &padapter->xmitpriv;
-+
-+	_enter_critical_bh(&pxmitpriv->lock, &irqL);
-+
-+	if (rtw_txframes_pending(padapter))
-+		tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
-+
-+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
-+	
-+#if defined(CONFIG_PCI_HCI) && defined(CONFIG_XMIT_THREAD_MODE)
-+	if (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE)
-+		_rtw_up_sema(&padapter->xmitpriv.xmit_sema);
-+#endif
-+	
-+
-+#endif
-+}
-+
-+void rtw_os_check_wakup_queue(_adapter *adapter, u16 os_qid)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	if (rtw_os_need_wake_queue(adapter, os_qid)) {
-+		if (DBG_DUMP_OS_QUEUE_CTL)
-+			RTW_INFO(FUNC_ADPT_FMT": netif_wake_subqueue[%d]\n", FUNC_ADPT_ARG(adapter), os_qid);
-+		netif_wake_subqueue(adapter->pnetdev, os_qid);
-+	}
-+#else
-+	if (rtw_os_need_wake_queue(adapter, 0)) {
-+		if (DBG_DUMP_OS_QUEUE_CTL)
-+			RTW_INFO(FUNC_ADPT_FMT": netif_wake_queue\n", FUNC_ADPT_ARG(adapter));
-+		netif_wake_queue(adapter->pnetdev);
-+	}
-+#endif
-+}
-+
-+bool rtw_os_check_stop_queue(_adapter *adapter, u16 os_qid)
-+{
-+	bool busy = _FALSE;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	if (rtw_os_need_stop_queue(adapter, os_qid)) {
-+		if (DBG_DUMP_OS_QUEUE_CTL)
-+			RTW_INFO(FUNC_ADPT_FMT": netif_stop_subqueue[%d]\n", FUNC_ADPT_ARG(adapter), os_qid);
-+		netif_stop_subqueue(adapter->pnetdev, os_qid);
-+		busy = _TRUE;
-+	}
-+#else
-+	if (rtw_os_need_stop_queue(adapter, 0)) {
-+		if (DBG_DUMP_OS_QUEUE_CTL)
-+			RTW_INFO(FUNC_ADPT_FMT": netif_stop_queue\n", FUNC_ADPT_ARG(adapter));
-+		rtw_netif_stop_queue(adapter->pnetdev);
-+		busy = _TRUE;
-+	}
-+#endif
-+	return busy;
-+}
-+
-+void rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed)
-+{
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	int i;
-+
-+	for (i = 0; i < 4; i++) {
-+		if (qcnt_freed[i] == 0)
-+			continue;
-+
-+		if (rtw_os_need_wake_queue(padapter, i)) {
-+			if (DBG_DUMP_OS_QUEUE_CTL)
-+				RTW_INFO(FUNC_ADPT_FMT": netif_wake_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), i);
-+			netif_wake_subqueue(padapter->pnetdev, i);
-+		}
-+	}
-+#else
-+	if (qcnt_freed[0] || qcnt_freed[1] || qcnt_freed[2] || qcnt_freed[3]) {
-+		if (rtw_os_need_wake_queue(padapter, 0)) {
-+			if (DBG_DUMP_OS_QUEUE_CTL)
-+				RTW_INFO(FUNC_ADPT_FMT": netif_wake_queue\n", FUNC_ADPT_ARG(padapter));
-+			netif_wake_queue(padapter->pnetdev);
-+		}
-+	}
-+#endif
-+}
-+
-+int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
-+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
-+#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX	
-+	struct sk_buff *skb = pkt;
-+	struct sk_buff *segs, *nskb;
-+	netdev_features_t features = padapter->pnetdev->features;
-+#endif
-+	u16 os_qid = 0;
-+	s32 res = 0;
-+
-+	if (padapter->registrypriv.mp_mode) {
-+		RTW_INFO("MP_TX_DROP_OS_FRAME\n");
-+		goto drop_packet;
-+	}
-+	DBG_COUNTER(padapter->tx_logs.os_tx);
-+
-+	if (rtw_if_up(padapter) == _FALSE) {
-+		DBG_COUNTER(padapter->tx_logs.os_tx_err_up);
-+		#ifdef DBG_TX_DROP_FRAME
-+		RTW_INFO("DBG_TX_DROP_FRAME %s if_up fail\n", __FUNCTION__);
-+		#endif
-+		goto drop_packet;
-+	}
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	os_qid = skb_get_queue_mapping(pkt);
-+#endif
-+
-+#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
-+	if (skb_shinfo(skb)->gso_size) {
-+	/*	split a big(65k) skb into several small(1.5k) skbs */
-+		features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
-+		segs = skb_gso_segment(skb, features);
-+		if (IS_ERR(segs) || !segs)
-+			goto drop_packet;
-+
-+		do {
-+			nskb = segs;
-+			segs = segs->next;
-+			nskb->next = NULL;
-+			rtw_mstat_update( MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, nskb->truesize);
-+			res = rtw_xmit(padapter, &nskb, os_qid);
-+			if (res < 0) {
-+				#ifdef DBG_TX_DROP_FRAME
-+				RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__);
-+				#endif
-+				pxmitpriv->tx_drop++;
-+				rtw_os_pkt_complete(padapter, nskb);
-+			}
-+		} while (segs);
-+		rtw_os_pkt_complete(padapter, skb);
-+		goto exit;
-+	}
-+#endif
-+
-+	res = rtw_xmit(padapter, &pkt, os_qid);
-+	if (res < 0) {
-+		#ifdef DBG_TX_DROP_FRAME
-+		RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__);
-+		#endif
-+		goto drop_packet;
-+	}
-+
-+	goto exit;
-+
-+drop_packet:
-+	pxmitpriv->tx_drop++;
-+	rtw_os_pkt_complete(padapter, pkt);
-+
-+exit:
-+
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
-+int check_alibaba_meshpkt(struct sk_buff *skb)
-+{
-+	u16 protocol;
-+
-+	if (skb)
-+		return (htons(skb->protocol) == ETH_P_ALL);
-+
-+	return _FALSE;
-+}
-+
-+s32 rtw_alibaba_mesh_xmit_entry(_pkt *pkt, struct net_device *ndev)
-+{
-+	u16 frame_ctl;
-+	
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
-+	struct pkt_file pktfile;
-+	struct rtw_ieee80211_hdr *pwlanhdr;
-+	struct pkt_attrib		*pattrib;
-+	struct xmit_frame		*pmgntframe;
-+	struct mlme_ext_priv    *pmlmeext = &(padapter->mlmeextpriv);
-+	struct xmit_priv		*pxmitpriv = &(padapter->xmitpriv);
-+	unsigned char   *pframe;
-+	struct sk_buff *skb =  (struct sk_buff *)pkt;
-+	int len = skb->len;
-+	
-+	rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize);
-+	
-+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);
-+	if (pmgntframe == NULL) {
-+		goto fail;
-+		return -1;
-+	}
-+	
-+	pattrib = &pmgntframe->attrib;
-+	update_mgntframe_attrib(padapter, pattrib);
-+	_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-+	pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-+
-+	_rtw_open_pktfile(pkt, &pktfile);
-+	_rtw_pktfile_read(&pktfile, pframe, len);
-+
-+	pattrib->type = pframe[0] & 0x0C;
-+	pattrib->subtype = pframe[0] & 0xF0;
-+	pattrib->raid =  rtw_get_mgntframe_raid(padapter, WIRELESS_11G);
-+	pattrib->rate = MGN_24M;
-+	pattrib->pktlen = len;
-+	SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
-+	pmlmeext->mgnt_seq++;
-+
-+	RTW_DBG_DUMP("rtw_alibaba_mesh_xmit_entry payload:", skb->data, len);
-+
-+	pattrib->last_txcmdsz = pattrib->pktlen;
-+	dump_mgntframe(padapter, pmgntframe);
-+
-+fail:
-+	rtw_skb_free(skb);
-+	return 0;
-+}
-+#endif
-+
-+int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev)
-+{
-+	_adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev);
-+	struct	mlme_priv	*pmlmepriv = &(padapter->mlmepriv);
-+	int ret = 0;
-+
-+	if (pkt) {
-+#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
-+		if (check_alibaba_meshpkt(pkt)) {
-+			return rtw_alibaba_mesh_xmit_entry(pkt, pnetdev);
-+		}
-+#endif
-+		if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
-+			rtw_monitor_xmit_entry((struct sk_buff *)pkt, pnetdev);
-+#endif
-+		}
-+		else {
-+			rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, pkt->truesize);
-+			ret = _rtw_xmit_entry(pkt, pnetdev);
-+		}
-+
-+	}
-+
-+	return ret;
-+}
-diff --git a/drivers/staging/rtl8723cs/os_dep/osdep_service.c b/drivers/staging/rtl8723cs/os_dep/osdep_service.c
-new file mode 100644
-index 000000000000..82c887874d41
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/os_dep/osdep_service.c
-@@ -0,0 +1,3430 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2007 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+
-+#define _OSDEP_SERVICE_C_
-+
-+#include <drv_types.h>
-+
-+#define RT_TAG	'1178'
-+
-+#ifdef DBG_MEMORY_LEAK
-+#ifdef PLATFORM_LINUX
-+atomic_t _malloc_cnt = ATOMIC_INIT(0);
-+atomic_t _malloc_size = ATOMIC_INIT(0);
-+#endif
-+#endif /* DBG_MEMORY_LEAK */
-+
-+
-+#if defined(PLATFORM_LINUX)
-+/*
-+* Translate the OS dependent @param error_code to OS independent RTW_STATUS_CODE
-+* @return: one of RTW_STATUS_CODE
-+*/
-+inline int RTW_STATUS_CODE(int error_code)
-+{
-+	if (error_code >= 0)
-+		return _SUCCESS;
-+
-+	switch (error_code) {
-+	/* case -ETIMEDOUT: */
-+	/*	return RTW_STATUS_TIMEDOUT; */
-+	default:
-+		return _FAIL;
-+	}
-+}
-+#else
-+inline int RTW_STATUS_CODE(int error_code)
-+{
-+	return error_code;
-+}
-+#endif
-+
-+u32 rtw_atoi(u8 *s)
-+{
-+
-+	int num = 0, flag = 0;
-+	int i;
-+	for (i = 0; i <= strlen(s); i++) {
-+		if (s[i] >= '0' && s[i] <= '9')
-+			num = num * 10 + s[i] - '0';
-+		else if (s[0] == '-' && i == 0)
-+			flag = 1;
-+		else
-+			break;
-+	}
-+
-+	if (flag == 1)
-+		num = num * -1;
-+
-+	return num;
-+
-+}
-+
-+inline void *_rtw_vmalloc(u32 sz)
-+{
-+	void *pbuf;
-+#ifdef PLATFORM_LINUX
-+	pbuf = vmalloc(sz);
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	pbuf = malloc(sz, M_DEVBUF, M_NOWAIT);
-+#endif
-+
-+#ifdef PLATFORM_WINDOWS
-+	NdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG);
-+#endif
-+
-+#ifdef DBG_MEMORY_LEAK
-+#ifdef PLATFORM_LINUX
-+	if (pbuf != NULL) {
-+		atomic_inc(&_malloc_cnt);
-+		atomic_add(sz, &_malloc_size);
-+	}
-+#endif
-+#endif /* DBG_MEMORY_LEAK */
-+
-+	return pbuf;
-+}
-+
-+inline void *_rtw_zvmalloc(u32 sz)
-+{
-+	void *pbuf;
-+#ifdef PLATFORM_LINUX
-+	pbuf = _rtw_vmalloc(sz);
-+	if (pbuf != NULL)
-+		memset(pbuf, 0, sz);
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	pbuf = malloc(sz, M_DEVBUF, M_ZERO | M_NOWAIT);
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+	NdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG);
-+	if (pbuf != NULL)
-+		NdisFillMemory(pbuf, sz, 0);
-+#endif
-+
-+	return pbuf;
-+}
-+
-+inline void _rtw_vmfree(void *pbuf, u32 sz)
-+{
-+#ifdef PLATFORM_LINUX
-+	vfree(pbuf);
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	free(pbuf, M_DEVBUF);
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+	NdisFreeMemory(pbuf, sz, 0);
-+#endif
-+
-+#ifdef DBG_MEMORY_LEAK
-+#ifdef PLATFORM_LINUX
-+	atomic_dec(&_malloc_cnt);
-+	atomic_sub(sz, &_malloc_size);
-+#endif
-+#endif /* DBG_MEMORY_LEAK */
-+}
-+
-+void *_rtw_malloc(u32 sz)
-+{
-+	void *pbuf = NULL;
-+
-+#ifdef PLATFORM_LINUX
-+#ifdef RTK_DMP_PLATFORM
-+	if (sz > 0x4000)
-+		pbuf = dvr_malloc(sz);
-+	else
-+#endif
-+		pbuf = kmalloc(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	pbuf = malloc(sz, M_DEVBUF, M_NOWAIT);
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisAllocateMemoryWithTag(&pbuf, sz, RT_TAG);
-+
-+#endif
-+
-+#ifdef DBG_MEMORY_LEAK
-+#ifdef PLATFORM_LINUX
-+	if (pbuf != NULL) {
-+		atomic_inc(&_malloc_cnt);
-+		atomic_add(sz, &_malloc_size);
-+	}
-+#endif
-+#endif /* DBG_MEMORY_LEAK */
-+
-+	return pbuf;
-+
-+}
-+
-+
-+void *_rtw_zmalloc(u32 sz)
-+{
-+#ifdef PLATFORM_FREEBSD
-+	return malloc(sz, M_DEVBUF, M_ZERO | M_NOWAIT);
-+#else /* PLATFORM_FREEBSD */
-+	void *pbuf = _rtw_malloc(sz);
-+
-+	if (pbuf != NULL) {
-+
-+#ifdef PLATFORM_LINUX
-+		memset(pbuf, 0, sz);
-+#endif
-+
-+#ifdef PLATFORM_WINDOWS
-+		NdisFillMemory(pbuf, sz, 0);
-+#endif
-+
-+	}
-+
-+	return pbuf;
-+#endif /* PLATFORM_FREEBSD */
-+}
-+
-+void _rtw_mfree(void *pbuf, u32 sz)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+#ifdef RTK_DMP_PLATFORM
-+	if (sz > 0x4000)
-+		dvr_free(pbuf);
-+	else
-+#endif
-+		kfree(pbuf);
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	free(pbuf, M_DEVBUF);
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisFreeMemory(pbuf, sz, 0);
-+
-+#endif
-+
-+#ifdef DBG_MEMORY_LEAK
-+#ifdef PLATFORM_LINUX
-+	atomic_dec(&_malloc_cnt);
-+	atomic_sub(sz, &_malloc_size);
-+#endif
-+#endif /* DBG_MEMORY_LEAK */
-+
-+}
-+
-+#ifdef PLATFORM_FREEBSD
-+/* review again */
-+struct sk_buff *dev_alloc_skb(unsigned int size)
-+{
-+	struct sk_buff *skb = NULL;
-+	u8 *data = NULL;
-+
-+	/* skb = _rtw_zmalloc(sizeof(struct sk_buff)); */ /* for skb->len, etc. */
-+	skb = _rtw_malloc(sizeof(struct sk_buff));
-+	if (!skb)
-+		goto out;
-+	data = _rtw_malloc(size);
-+	if (!data)
-+		goto nodata;
-+
-+	skb->head = (unsigned char *)data;
-+	skb->data = (unsigned char *)data;
-+	skb->tail = (unsigned char *)data;
-+	skb->end = (unsigned char *)data + size;
-+	skb->len = 0;
-+	/* printf("%s()-%d: skb=%p, skb->head = %p\n", __FUNCTION__, __LINE__, skb, skb->head); */
-+
-+out:
-+	return skb;
-+nodata:
-+	_rtw_mfree(skb, sizeof(struct sk_buff));
-+	skb = NULL;
-+	goto out;
-+
-+}
-+
-+void dev_kfree_skb_any(struct sk_buff *skb)
-+{
-+	/* printf("%s()-%d: skb->head = %p\n", __FUNCTION__, __LINE__, skb->head); */
-+	if (skb->head)
-+		_rtw_mfree(skb->head, 0);
-+	/* printf("%s()-%d: skb = %p\n", __FUNCTION__, __LINE__, skb); */
-+	if (skb)
-+		_rtw_mfree(skb, 0);
-+}
-+struct sk_buff *skb_clone(const struct sk_buff *skb)
-+{
-+	return NULL;
-+}
-+
-+#endif /* PLATFORM_FREEBSD */
-+
-+inline struct sk_buff *_rtw_skb_alloc(u32 sz)
-+{
-+#ifdef PLATFORM_LINUX
-+	return __dev_alloc_skb(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
-+#endif /* PLATFORM_LINUX */
-+
-+#ifdef PLATFORM_FREEBSD
-+	return dev_alloc_skb(sz);
-+#endif /* PLATFORM_FREEBSD */
-+}
-+
-+inline void _rtw_skb_free(struct sk_buff *skb)
-+{
-+	dev_kfree_skb_any(skb);
-+}
-+
-+inline struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb)
-+{
-+#ifdef PLATFORM_LINUX
-+	return skb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
-+#endif /* PLATFORM_LINUX */
-+
-+#ifdef PLATFORM_FREEBSD
-+	return NULL;
-+#endif /* PLATFORM_FREEBSD */
-+}
-+
-+inline struct sk_buff *_rtw_skb_clone(struct sk_buff *skb)
-+{
-+#ifdef PLATFORM_LINUX
-+	return skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
-+#endif /* PLATFORM_LINUX */
-+
-+#ifdef PLATFORM_FREEBSD
-+	return skb_clone(skb);
-+#endif /* PLATFORM_FREEBSD */
-+}
-+inline struct sk_buff *_rtw_pskb_copy(struct sk_buff *skb)
-+{
-+#ifdef PLATFORM_LINUX
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
-+	return pskb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
-+#else
-+	return skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
-+#endif
-+#endif /* PLATFORM_LINUX */
-+
-+#ifdef PLATFORM_FREEBSD
-+	return NULL;
-+#endif /* PLATFORM_FREEBSD */
-+}
-+
-+inline int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb)
-+{
-+#if defined(PLATFORM_LINUX)
-+	skb->dev = ndev;
-+	return netif_rx(skb);
-+#elif defined(PLATFORM_FREEBSD)
-+	return (*ndev->if_input)(ndev, skb);
-+#else
-+	rtw_warn_on(1);
-+	return -1;
-+#endif
-+}
-+
-+#ifdef CONFIG_RTW_NAPI
-+inline int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb)
-+{
-+#if defined(PLATFORM_LINUX)
-+	skb->dev = ndev;
-+	return netif_receive_skb(skb);
-+#else
-+	rtw_warn_on(1);
-+	return -1;
-+#endif
-+}
-+
-+#ifdef CONFIG_RTW_GRO
-+inline gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb)
-+{
-+#if defined(PLATFORM_LINUX)
-+	return napi_gro_receive(napi, skb);
-+#else
-+	rtw_warn_on(1);
-+	return -1;
-+#endif
-+}
-+#endif /* CONFIG_RTW_GRO */
-+#endif /* CONFIG_RTW_NAPI */
-+
-+void _rtw_skb_queue_purge(struct sk_buff_head *list)
-+{
-+	struct sk_buff *skb;
-+
-+	while ((skb = skb_dequeue(list)) != NULL)
-+		_rtw_skb_free(skb);
-+}
-+
-+#ifdef CONFIG_USB_HCI
-+inline void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma)
-+{
-+#ifdef PLATFORM_LINUX
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	return usb_alloc_coherent(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);
-+#else
-+	return usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);
-+#endif
-+#endif /* PLATFORM_LINUX */
-+
-+#ifdef PLATFORM_FREEBSD
-+	return malloc(size, M_USBDEV, M_NOWAIT | M_ZERO);
-+#endif /* PLATFORM_FREEBSD */
-+}
-+inline void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma)
-+{
-+#ifdef PLATFORM_LINUX
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	usb_free_coherent(dev, size, addr, dma);
-+#else
-+	usb_buffer_free(dev, size, addr, dma);
-+#endif
-+#endif /* PLATFORM_LINUX */
-+
-+#ifdef PLATFORM_FREEBSD
-+	free(addr, M_USBDEV);
-+#endif /* PLATFORM_FREEBSD */
-+}
-+#endif /* CONFIG_USB_HCI */
-+
-+#if defined(DBG_MEM_ALLOC)
-+
-+struct rtw_mem_stat {
-+	ATOMIC_T alloc; /* the memory bytes we allocate currently */
-+	ATOMIC_T peak; /* the peak memory bytes we allocate */
-+	ATOMIC_T alloc_cnt; /* the alloc count for alloc currently */
-+	ATOMIC_T alloc_err_cnt; /* the error times we fail to allocate memory */
-+};
-+
-+struct rtw_mem_stat rtw_mem_type_stat[mstat_tf_idx(MSTAT_TYPE_MAX)];
-+#ifdef RTW_MEM_FUNC_STAT
-+struct rtw_mem_stat rtw_mem_func_stat[mstat_ff_idx(MSTAT_FUNC_MAX)];
-+#endif
-+
-+char *MSTAT_TYPE_str[] = {
-+	"VIR",
-+	"PHY",
-+	"SKB",
-+	"USB",
-+};
-+
-+#ifdef RTW_MEM_FUNC_STAT
-+char *MSTAT_FUNC_str[] = {
-+	"UNSP",
-+	"IO",
-+	"TXIO",
-+	"RXIO",
-+	"TX",
-+	"RX",
-+};
-+#endif
-+
-+void rtw_mstat_dump(void *sel)
-+{
-+	int i;
-+	int value_t[4][mstat_tf_idx(MSTAT_TYPE_MAX)];
-+#ifdef RTW_MEM_FUNC_STAT
-+	int value_f[4][mstat_ff_idx(MSTAT_FUNC_MAX)];
-+#endif
-+
-+	for (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++) {
-+		value_t[0][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc));
-+		value_t[1][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].peak));
-+		value_t[2][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc_cnt));
-+		value_t[3][i] = ATOMIC_READ(&(rtw_mem_type_stat[i].alloc_err_cnt));
-+	}
-+
-+#ifdef RTW_MEM_FUNC_STAT
-+	for (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++) {
-+		value_f[0][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc));
-+		value_f[1][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].peak));
-+		value_f[2][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc_cnt));
-+		value_f[3][i] = ATOMIC_READ(&(rtw_mem_func_stat[i].alloc_err_cnt));
-+	}
-+#endif
-+
-+	RTW_PRINT_SEL(sel, "===================== MSTAT =====================\n");
-+	RTW_PRINT_SEL(sel, "%4s %10s %10s %10s %10s\n", "TAG", "alloc", "peak", "aloc_cnt", "err_cnt");
-+	RTW_PRINT_SEL(sel, "-------------------------------------------------\n");
-+	for (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++)
-+		RTW_PRINT_SEL(sel, "%4s %10d %10d %10d %10d\n", MSTAT_TYPE_str[i], value_t[0][i], value_t[1][i], value_t[2][i], value_t[3][i]);
-+#ifdef RTW_MEM_FUNC_STAT
-+	RTW_PRINT_SEL(sel, "-------------------------------------------------\n");
-+	for (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++)
-+		RTW_PRINT_SEL(sel, "%4s %10d %10d %10d %10d\n", MSTAT_FUNC_str[i], value_f[0][i], value_f[1][i], value_f[2][i], value_f[3][i]);
-+#endif
-+}
-+
-+void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz)
-+{
-+	static systime update_time = 0;
-+	int peak, alloc;
-+	int i;
-+
-+	/* initialization */
-+	if (!update_time) {
-+		for (i = 0; i < mstat_tf_idx(MSTAT_TYPE_MAX); i++) {
-+			ATOMIC_SET(&(rtw_mem_type_stat[i].alloc), 0);
-+			ATOMIC_SET(&(rtw_mem_type_stat[i].peak), 0);
-+			ATOMIC_SET(&(rtw_mem_type_stat[i].alloc_cnt), 0);
-+			ATOMIC_SET(&(rtw_mem_type_stat[i].alloc_err_cnt), 0);
-+		}
-+		#ifdef RTW_MEM_FUNC_STAT
-+		for (i = 0; i < mstat_ff_idx(MSTAT_FUNC_MAX); i++) {
-+			ATOMIC_SET(&(rtw_mem_func_stat[i].alloc), 0);
-+			ATOMIC_SET(&(rtw_mem_func_stat[i].peak), 0);
-+			ATOMIC_SET(&(rtw_mem_func_stat[i].alloc_cnt), 0);
-+			ATOMIC_SET(&(rtw_mem_func_stat[i].alloc_err_cnt), 0);
-+		}
-+		#endif
-+	}
-+
-+	switch (status) {
-+	case MSTAT_ALLOC_SUCCESS:
-+		ATOMIC_INC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_cnt));
-+		alloc = ATOMIC_ADD_RETURN(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc), sz);
-+		peak = ATOMIC_READ(&(rtw_mem_type_stat[mstat_tf_idx(flags)].peak));
-+		if (peak < alloc)
-+			ATOMIC_SET(&(rtw_mem_type_stat[mstat_tf_idx(flags)].peak), alloc);
-+
-+		#ifdef RTW_MEM_FUNC_STAT
-+		ATOMIC_INC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_cnt));
-+		alloc = ATOMIC_ADD_RETURN(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc), sz);
-+		peak = ATOMIC_READ(&(rtw_mem_func_stat[mstat_ff_idx(flags)].peak));
-+		if (peak < alloc)
-+			ATOMIC_SET(&(rtw_mem_func_stat[mstat_ff_idx(flags)].peak), alloc);
-+		#endif
-+		break;
-+
-+	case MSTAT_ALLOC_FAIL:
-+		ATOMIC_INC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_err_cnt));
-+		#ifdef RTW_MEM_FUNC_STAT
-+		ATOMIC_INC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_err_cnt));
-+		#endif
-+		break;
-+
-+	case MSTAT_FREE:
-+		ATOMIC_DEC(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc_cnt));
-+		ATOMIC_SUB(&(rtw_mem_type_stat[mstat_tf_idx(flags)].alloc), sz);
-+		#ifdef RTW_MEM_FUNC_STAT
-+		ATOMIC_DEC(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc_cnt));
-+		ATOMIC_SUB(&(rtw_mem_func_stat[mstat_ff_idx(flags)].alloc), sz);
-+		#endif
-+		break;
-+	};
-+
-+	/* if (rtw_get_passing_time_ms(update_time) > 5000) { */
-+	/*	rtw_mstat_dump(RTW_DBGDUMP); */
-+	update_time = rtw_get_current_time();
-+	/* } */
-+}
-+
-+#ifndef SIZE_MAX
-+	#define SIZE_MAX (~(size_t)0)
-+#endif
-+
-+struct mstat_sniff_rule {
-+	enum mstat_f flags;
-+	size_t lb;
-+	size_t hb;
-+};
-+
-+struct mstat_sniff_rule mstat_sniff_rules[] = {
-+	{MSTAT_TYPE_PHY, 4097, SIZE_MAX},
-+};
-+
-+int mstat_sniff_rule_num = sizeof(mstat_sniff_rules) / sizeof(struct mstat_sniff_rule);
-+
-+bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size)
-+{
-+	int i;
-+	for (i = 0; i < mstat_sniff_rule_num; i++) {
-+		if (mstat_sniff_rules[i].flags == flags
-+			&& mstat_sniff_rules[i].lb <= size
-+			&& mstat_sniff_rules[i].hb >= size)
-+			return _TRUE;
-+	}
-+
-+	return _FALSE;
-+}
-+
-+inline void *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
-+{
-+	void *p;
-+
-+	if (match_mstat_sniff_rules(flags, sz))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
-+
-+	p = _rtw_vmalloc((sz));
-+
-+	rtw_mstat_update(
-+		flags
-+		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
-+		, sz
-+	);
-+
-+	return p;
-+}
-+
-+inline void *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
-+{
-+	void *p;
-+
-+	if (match_mstat_sniff_rules(flags, sz))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
-+
-+	p = _rtw_zvmalloc((sz));
-+
-+	rtw_mstat_update(
-+		flags
-+		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
-+		, sz
-+	);
-+
-+	return p;
-+}
-+
-+inline void dbg_rtw_vmfree(void *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line)
-+{
-+
-+	if (match_mstat_sniff_rules(flags, sz))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
-+
-+	_rtw_vmfree((pbuf), (sz));
-+
-+	rtw_mstat_update(
-+		flags
-+		, MSTAT_FREE
-+		, sz
-+	);
-+}
-+
-+inline void *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
-+{
-+	void *p;
-+
-+	if (match_mstat_sniff_rules(flags, sz))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
-+
-+	p = _rtw_malloc((sz));
-+
-+	rtw_mstat_update(
-+		flags
-+		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
-+		, sz
-+	);
-+
-+	return p;
-+}
-+
-+inline void *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line)
-+{
-+	void *p;
-+
-+	if (match_mstat_sniff_rules(flags, sz))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
-+
-+	p = _rtw_zmalloc((sz));
-+
-+	rtw_mstat_update(
-+		flags
-+		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
-+		, sz
-+	);
-+
-+	return p;
-+}
-+
-+inline void dbg_rtw_mfree(void *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line)
-+{
-+	if (match_mstat_sniff_rules(flags, sz))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz));
-+
-+	_rtw_mfree((pbuf), (sz));
-+
-+	rtw_mstat_update(
-+		flags
-+		, MSTAT_FREE
-+		, sz
-+	);
-+}
-+
-+inline struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, int line)
-+{
-+	struct sk_buff *skb;
-+	unsigned int truesize = 0;
-+
-+	skb = _rtw_skb_alloc(size);
-+
-+	if (skb)
-+		truesize = skb->truesize;
-+
-+	if (!skb || truesize < size || match_mstat_sniff_rules(flags, truesize))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, size, skb, truesize);
-+
-+	rtw_mstat_update(
-+		flags
-+		, skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
-+		, truesize
-+	);
-+
-+	return skb;
-+}
-+
-+inline void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
-+{
-+	unsigned int truesize = skb->truesize;
-+
-+	if (match_mstat_sniff_rules(flags, truesize))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
-+
-+	_rtw_skb_free(skb);
-+
-+	rtw_mstat_update(
-+		flags
-+		, MSTAT_FREE
-+		, truesize
-+	);
-+}
-+
-+inline struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line)
-+{
-+	struct sk_buff *skb_cp;
-+	unsigned int truesize = skb->truesize;
-+	unsigned int cp_truesize = 0;
-+
-+	skb_cp = _rtw_skb_copy(skb);
-+	if (skb_cp)
-+		cp_truesize = skb_cp->truesize;
-+
-+	if (!skb_cp || cp_truesize < truesize || match_mstat_sniff_rules(flags, cp_truesize))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u), skb_cp:%p, cp_truesize=%u\n", func, line, __FUNCTION__, truesize, skb_cp, cp_truesize);
-+
-+	rtw_mstat_update(
-+		flags
-+		, skb_cp ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
-+		, cp_truesize
-+	);
-+
-+	return skb_cp;
-+}
-+
-+inline struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line)
-+{
-+	struct sk_buff *skb_cl;
-+	unsigned int truesize = skb->truesize;
-+	unsigned int cl_truesize = 0;
-+
-+	skb_cl = _rtw_skb_clone(skb);
-+	if (skb_cl)
-+		cl_truesize = skb_cl->truesize;
-+
-+	if (!skb_cl || cl_truesize < truesize || match_mstat_sniff_rules(flags, cl_truesize))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u), skb_cl:%p, cl_truesize=%u\n", func, line, __FUNCTION__, truesize, skb_cl, cl_truesize);
-+
-+	rtw_mstat_update(
-+		flags
-+		, skb_cl ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
-+		, cl_truesize
-+	);
-+
-+	return skb_cl;
-+}
-+
-+inline int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
-+{
-+	int ret;
-+	unsigned int truesize = skb->truesize;
-+
-+	if (match_mstat_sniff_rules(flags, truesize))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
-+
-+	ret = _rtw_netif_rx(ndev, skb);
-+
-+	rtw_mstat_update(
-+		flags
-+		, MSTAT_FREE
-+		, truesize
-+	);
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_RTW_NAPI
-+inline int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
-+{
-+	int ret;
-+	unsigned int truesize = skb->truesize;
-+
-+	if (match_mstat_sniff_rules(flags, truesize))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
-+
-+	ret = _rtw_netif_receive_skb(ndev, skb);
-+
-+	rtw_mstat_update(
-+		flags
-+		, MSTAT_FREE
-+		, truesize
-+	);
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_RTW_GRO
-+inline gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line)
-+{
-+	int ret;
-+	unsigned int truesize = skb->truesize;
-+
-+	if (match_mstat_sniff_rules(flags, truesize))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize);
-+
-+	ret = _rtw_napi_gro_receive(napi, skb);
-+
-+	rtw_mstat_update(
-+		flags
-+		, MSTAT_FREE
-+		, truesize
-+	);
-+
-+	return ret;
-+}
-+#endif /* CONFIG_RTW_GRO */
-+#endif /* CONFIG_RTW_NAPI */
-+
-+inline void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line)
-+{
-+	struct sk_buff *skb;
-+
-+	while ((skb = skb_dequeue(list)) != NULL)
-+		dbg_rtw_skb_free(skb, flags, func, line);
-+}
-+
-+#ifdef CONFIG_USB_HCI
-+inline void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, int line)
-+{
-+	void *p;
-+
-+	if (match_mstat_sniff_rules(flags, size))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%zu)\n", func, line, __FUNCTION__, size);
-+
-+	p = _rtw_usb_buffer_alloc(dev, size, dma);
-+
-+	rtw_mstat_update(
-+		flags
-+		, p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
-+		, size
-+	);
-+
-+	return p;
-+}
-+
-+inline void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, int line)
-+{
-+
-+	if (match_mstat_sniff_rules(flags, size))
-+		RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%zu)\n", func, line, __FUNCTION__, size);
-+
-+	_rtw_usb_buffer_free(dev, size, addr, dma);
-+
-+	rtw_mstat_update(
-+		flags
-+		, MSTAT_FREE
-+		, size
-+	);
-+}
-+#endif /* CONFIG_USB_HCI */
-+
-+#endif /* defined(DBG_MEM_ALLOC) */
-+
-+void *rtw_malloc2d(int h, int w, size_t size)
-+{
-+	int j;
-+
-+	void **a = (void **) rtw_zmalloc(h * sizeof(void *) + h * w * size);
-+	if (a == NULL) {
-+		RTW_INFO("%s: alloc memory fail!\n", __FUNCTION__);
-+		return NULL;
-+	}
-+
-+	for (j = 0; j < h; j++)
-+		a[j] = ((char *)(a + h)) + j * w * size;
-+
-+	return a;
-+}
-+
-+void rtw_mfree2d(void *pbuf, int h, int w, int size)
-+{
-+	rtw_mfree((u8 *)pbuf, h * sizeof(void *) + w * h * size);
-+}
-+
-+inline void rtw_os_pkt_free(_pkt *pkt)
-+{
-+#if defined(PLATFORM_LINUX)
-+	rtw_skb_free(pkt);
-+#elif defined(PLATFORM_FREEBSD)
-+	m_freem(pkt);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+inline _pkt *rtw_os_pkt_copy(_pkt *pkt)
-+{
-+#if defined(PLATFORM_LINUX)
-+	return rtw_skb_copy(pkt);
-+#elif defined(PLATFORM_FREEBSD)
-+	return m_dup(pkt, M_NOWAIT);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+inline void *rtw_os_pkt_data(_pkt *pkt)
-+{
-+#if defined(PLATFORM_LINUX)
-+	return pkt->data;
-+#elif defined(PLATFORM_FREEBSD)
-+	return pkt->m_data;
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+inline u32 rtw_os_pkt_len(_pkt *pkt)
-+{
-+#if defined(PLATFORM_LINUX)
-+	return pkt->len;
-+#elif defined(PLATFORM_FREEBSD)
-+	return pkt->m_pkthdr.len;
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+void _rtw_memcpy(void *dst, const void *src, u32 sz)
-+{
-+
-+#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)
-+
-+	memcpy(dst, src, sz);
-+
-+#endif
-+
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisMoveMemory(dst, src, sz);
-+
-+#endif
-+
-+}
-+
-+inline void _rtw_memmove(void *dst, const void *src, u32 sz)
-+{
-+#if defined(PLATFORM_LINUX)
-+	memmove(dst, src, sz);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+int	_rtw_memcmp(const void *dst, const void *src, u32 sz)
-+{
-+
-+#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)
-+	/* under Linux/GNU/GLibc, the return value of memcmp for two same mem. chunk is 0 */
-+
-+	if (!(memcmp(dst, src, sz)))
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+#endif
-+
-+
-+#ifdef PLATFORM_WINDOWS
-+	/* under Windows, the return value of NdisEqualMemory for two same mem. chunk is 1 */
-+
-+	if (NdisEqualMemory(dst, src, sz))
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+
-+#endif
-+
-+
-+
-+}
-+
-+int _rtw_memcmp2(const void *dst, const void *src, u32 sz)
-+{
-+	const unsigned char *p1 = dst, *p2 = src;
-+
-+	if (sz == 0)
-+		return 0;
-+
-+	while (*p1 == *p2) {
-+		p1++;
-+		p2++;
-+		sz--;
-+		if (sz == 0)
-+			return 0;
-+	}
-+
-+	return *p1 - *p2;
-+}
-+
-+void _rtw_memset(void *pbuf, int c, u32 sz)
-+{
-+
-+#if defined(PLATFORM_LINUX) || defined (PLATFORM_FREEBSD)
-+
-+	memset(pbuf, c, sz);
-+
-+#endif
-+
-+#ifdef PLATFORM_WINDOWS
-+#if 0
-+	NdisZeroMemory(pbuf, sz);
-+	if (c != 0)
-+		memset(pbuf, c, sz);
-+#else
-+	NdisFillMemory(pbuf, sz, c);
-+#endif
-+#endif
-+
-+}
-+
-+#ifdef PLATFORM_FREEBSD
-+static inline void __list_add(_list *pnew, _list *pprev, _list *pnext)
-+{
-+	pnext->prev = pnew;
-+	pnew->next = pnext;
-+	pnew->prev = pprev;
-+	pprev->next = pnew;
-+}
-+#endif /* PLATFORM_FREEBSD */
-+
-+
-+void _rtw_init_listhead(_list *list)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+
-+	INIT_LIST_HEAD(list);
-+
-+#endif
-+
-+#ifdef PLATFORM_FREEBSD
-+	list->next = list;
-+	list->prev = list;
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisInitializeListHead(list);
-+
-+#endif
-+
-+}
-+
-+
-+/*
-+For the following list_xxx operations,
-+caller must guarantee the atomic context.
-+Otherwise, there will be racing condition.
-+*/
-+u32	rtw_is_list_empty(_list *phead)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+
-+	if (list_empty(phead))
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+
-+	if (phead->next == phead)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+
-+#endif
-+
-+
-+#ifdef PLATFORM_WINDOWS
-+
-+	if (IsListEmpty(phead))
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+
-+#endif
-+
-+
-+}
-+
-+void rtw_list_insert_head(_list *plist, _list *phead)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+	list_add(plist, phead);
-+#endif
-+
-+#ifdef PLATFORM_FREEBSD
-+	__list_add(plist, phead, phead->next);
-+#endif
-+
-+#ifdef PLATFORM_WINDOWS
-+	InsertHeadList(phead, plist);
-+#endif
-+}
-+
-+void rtw_list_insert_tail(_list *plist, _list *phead)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+
-+	list_add_tail(plist, phead);
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+
-+	__list_add(plist, phead->prev, phead);
-+
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+
-+	InsertTailList(phead, plist);
-+
-+#endif
-+
-+}
-+
-+inline void rtw_list_splice(_list *list, _list *head)
-+{
-+#ifdef PLATFORM_LINUX
-+	list_splice(list, head);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+inline void rtw_list_splice_init(_list *list, _list *head)
-+{
-+#ifdef PLATFORM_LINUX
-+	list_splice_init(list, head);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+inline void rtw_list_splice_tail(_list *list, _list *head)
-+{
-+#ifdef PLATFORM_LINUX
-+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27))
-+	if (!list_empty(list))
-+		__list_splice(list, head);
-+	#else
-+	list_splice_tail(list, head);
-+	#endif
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+inline void rtw_hlist_head_init(rtw_hlist_head *h)
-+{
-+#ifdef PLATFORM_LINUX
-+	INIT_HLIST_HEAD(h);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+inline void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h)
-+{
-+#ifdef PLATFORM_LINUX
-+	hlist_add_head(n, h);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+inline void rtw_hlist_del(rtw_hlist_node *n)
-+{
-+#ifdef PLATFORM_LINUX
-+	hlist_del(n);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+inline void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h)
-+{
-+#ifdef PLATFORM_LINUX
-+	hlist_add_head_rcu(n, h);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+inline void rtw_hlist_del_rcu(rtw_hlist_node *n)
-+{
-+#ifdef PLATFORM_LINUX
-+	hlist_del_rcu(n);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx)
-+{
-+	_adapter *adapter = (_adapter *)padapter;
-+
-+#ifdef PLATFORM_LINUX
-+	_init_timer(ptimer, adapter->pnetdev, pfunc, ctx);
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	_init_timer(ptimer, adapter->pifp, pfunc, ctx);
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+	_init_timer(ptimer, adapter->hndis_adapter, pfunc, ctx);
-+#endif
-+}
-+
-+/*
-+
-+Caller must check if the list is empty before calling rtw_list_delete
-+
-+*/
-+
-+
-+void _rtw_init_sema(_sema	*sema, int init_val)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+
-+	sema_init(sema, init_val);
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	sema_init(sema, init_val, "rtw_drv");
-+#endif
-+#ifdef PLATFORM_OS_XP
-+
-+	KeInitializeSemaphore(sema, init_val,  SEMA_UPBND); /* count=0; */
-+
-+#endif
-+
-+#ifdef PLATFORM_OS_CE
-+	if (*sema == NULL)
-+		*sema = CreateSemaphore(NULL, init_val, SEMA_UPBND, NULL);
-+#endif
-+
-+}
-+
-+void _rtw_free_sema(_sema	*sema)
-+{
-+#ifdef PLATFORM_FREEBSD
-+	sema_destroy(sema);
-+#endif
-+#ifdef PLATFORM_OS_CE
-+	CloseHandle(*sema);
-+#endif
-+
-+}
-+
-+void _rtw_up_sema(_sema	*sema)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+
-+	up(sema);
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	sema_post(sema);
-+#endif
-+#ifdef PLATFORM_OS_XP
-+
-+	KeReleaseSemaphore(sema, IO_NETWORK_INCREMENT, 1,  FALSE);
-+
-+#endif
-+
-+#ifdef PLATFORM_OS_CE
-+	ReleaseSemaphore(*sema,  1,  NULL);
-+#endif
-+}
-+
-+u32 _rtw_down_sema(_sema *sema)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+
-+	if (down_interruptible(sema))
-+		return _FAIL;
-+	else
-+		return _SUCCESS;
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	sema_wait(sema);
-+	return  _SUCCESS;
-+#endif
-+#ifdef PLATFORM_OS_XP
-+
-+	if (STATUS_SUCCESS == KeWaitForSingleObject(sema, Executive, KernelMode, TRUE, NULL))
-+		return  _SUCCESS;
-+	else
-+		return _FAIL;
-+#endif
-+
-+#ifdef PLATFORM_OS_CE
-+	if (WAIT_OBJECT_0 == WaitForSingleObject(*sema, INFINITE))
-+		return _SUCCESS;
-+	else
-+		return _FAIL;
-+#endif
-+}
-+
-+inline void thread_exit(_completion *comp)
-+{
-+#ifdef PLATFORM_LINUX
-+	complete_and_exit(comp, 0);
-+#endif
-+
-+#ifdef PLATFORM_FREEBSD
-+	printf("%s", "RTKTHREAD_exit");
-+#endif
-+
-+#ifdef PLATFORM_OS_CE
-+	ExitThread(STATUS_SUCCESS);
-+#endif
-+
-+#ifdef PLATFORM_OS_XP
-+	PsTerminateSystemThread(STATUS_SUCCESS);
-+#endif
-+}
-+
-+inline void _rtw_init_completion(_completion *comp)
-+{
-+#ifdef PLATFORM_LINUX
-+	init_completion(comp);
-+#endif
-+}
-+inline void _rtw_wait_for_comp_timeout(_completion *comp)
-+{
-+#ifdef PLATFORM_LINUX
-+	wait_for_completion_timeout(comp, msecs_to_jiffies(3000));
-+#endif
-+}
-+inline void _rtw_wait_for_comp(_completion *comp)
-+{
-+#ifdef PLATFORM_LINUX
-+	wait_for_completion(comp);
-+#endif
-+}
-+
-+void	_rtw_mutex_init(_mutex *pmutex)
-+{
-+#ifdef PLATFORM_LINUX
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
-+	mutex_init(pmutex);
-+#else
-+	init_MUTEX(pmutex);
-+#endif
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	mtx_init(pmutex, "", NULL, MTX_DEF | MTX_RECURSE);
-+#endif
-+#ifdef PLATFORM_OS_XP
-+
-+	KeInitializeMutex(pmutex, 0);
-+
-+#endif
-+
-+#ifdef PLATFORM_OS_CE
-+	*pmutex =  CreateMutex(NULL, _FALSE, NULL);
-+#endif
-+}
-+
-+void	_rtw_mutex_free(_mutex *pmutex);
-+void	_rtw_mutex_free(_mutex *pmutex)
-+{
-+#ifdef PLATFORM_LINUX
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
-+	mutex_destroy(pmutex);
-+#else
-+#endif
-+
-+#ifdef PLATFORM_FREEBSD
-+	sema_destroy(pmutex);
-+#endif
-+
-+#endif
-+
-+#ifdef PLATFORM_OS_XP
-+
-+#endif
-+
-+#ifdef PLATFORM_OS_CE
-+
-+#endif
-+}
-+
-+void	_rtw_spinlock_init(_lock *plock)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+
-+	spin_lock_init(plock);
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	mtx_init(plock, "", NULL, MTX_DEF | MTX_RECURSE);
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisAllocateSpinLock(plock);
-+
-+#endif
-+
-+}
-+
-+void	_rtw_spinlock_free(_lock *plock)
-+{
-+#ifdef PLATFORM_FREEBSD
-+	mtx_destroy(plock);
-+#endif
-+
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisFreeSpinLock(plock);
-+
-+#endif
-+
-+}
-+#ifdef PLATFORM_FREEBSD
-+extern PADAPTER prtw_lock;
-+
-+void rtw_mtx_lock(_lock *plock)
-+{
-+	if (prtw_lock)
-+		mtx_lock(&prtw_lock->glock);
-+	else
-+		printf("%s prtw_lock==NULL", __FUNCTION__);
-+}
-+void rtw_mtx_unlock(_lock *plock)
-+{
-+	if (prtw_lock)
-+		mtx_unlock(&prtw_lock->glock);
-+	else
-+		printf("%s prtw_lock==NULL", __FUNCTION__);
-+
-+}
-+#endif /* PLATFORM_FREEBSD */
-+
-+
-+void	_rtw_spinlock(_lock	*plock)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+
-+	spin_lock(plock);
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	mtx_lock(plock);
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisAcquireSpinLock(plock);
-+
-+#endif
-+
-+}
-+
-+void	_rtw_spinunlock(_lock *plock)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+
-+	spin_unlock(plock);
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	mtx_unlock(plock);
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisReleaseSpinLock(plock);
-+
-+#endif
-+}
-+
-+
-+void	_rtw_spinlock_ex(_lock	*plock)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+
-+	spin_lock(plock);
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	mtx_lock(plock);
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisDprAcquireSpinLock(plock);
-+
-+#endif
-+
-+}
-+
-+void	_rtw_spinunlock_ex(_lock *plock)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+
-+	spin_unlock(plock);
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	mtx_unlock(plock);
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisDprReleaseSpinLock(plock);
-+
-+#endif
-+}
-+
-+
-+
-+void _rtw_init_queue(_queue *pqueue)
-+{
-+	_rtw_init_listhead(&(pqueue->queue));
-+	_rtw_spinlock_init(&(pqueue->lock));
-+}
-+
-+void _rtw_deinit_queue(_queue *pqueue)
-+{
-+	_rtw_spinlock_free(&(pqueue->lock));
-+}
-+
-+u32	  _rtw_queue_empty(_queue	*pqueue)
-+{
-+	return rtw_is_list_empty(&(pqueue->queue));
-+}
-+
-+
-+u32 rtw_end_of_queue_search(_list *head, _list *plist)
-+{
-+	if (head == plist)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+
-+systime _rtw_get_current_time(void)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+	return jiffies;
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	struct timeval tvp;
-+	getmicrotime(&tvp);
-+	return tvp.tv_sec;
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+	LARGE_INTEGER	SystemTime;
-+	NdisGetCurrentSystemTime(&SystemTime);
-+	return SystemTime.LowPart;/* count of 100-nanosecond intervals */
-+#endif
-+}
-+
-+inline u32 _rtw_systime_to_ms(systime stime)
-+{
-+#ifdef PLATFORM_LINUX
-+	return jiffies_to_msecs(stime);
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	return stime * 1000;
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+	return stime / 10000 ;
-+#endif
-+}
-+
-+inline systime _rtw_ms_to_systime(u32 ms)
-+{
-+#ifdef PLATFORM_LINUX
-+	return msecs_to_jiffies(ms);
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	return ms / 1000;
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+	return ms * 10000 ;
-+#endif
-+}
-+
-+inline systime _rtw_us_to_systime(u32 us)
-+{
-+#ifdef PLATFORM_LINUX
-+	return usecs_to_jiffies(us);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+/* the input parameter start use the same unit as returned by rtw_get_current_time */
-+inline s32 _rtw_get_passing_time_ms(systime start)
-+{
-+	return _rtw_systime_to_ms(_rtw_get_current_time() - start);
-+}
-+
-+inline s32 _rtw_get_remaining_time_ms(systime end)
-+{
-+	return _rtw_systime_to_ms(end - _rtw_get_current_time());
-+}
-+
-+inline s32 _rtw_get_time_interval_ms(systime start, systime end)
-+{
-+	return _rtw_systime_to_ms(end - start);
-+}
-+
-+inline bool _rtw_time_after(systime a, systime b)
-+{
-+#ifdef PLATFORM_LINUX
-+	return time_after(a, b);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+sysptime rtw_sptime_get(void)
-+{
-+	/* CLOCK_MONOTONIC */
-+#ifdef PLATFORM_LINUX
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0))
-+	struct timespec64 cur;
-+
-+	ktime_get_ts64(&cur);
-+	return timespec64_to_ktime(cur);
-+	#else
-+	struct timespec cur;
-+
-+	ktime_get_ts(&cur);
-+	return timespec_to_ktime(cur);
-+	#endif
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+sysptime rtw_sptime_set(s64 secs, const u32 nsecs)
-+{
-+#ifdef PLATFORM_LINUX
-+	return ktime_set(secs, nsecs);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+sysptime rtw_sptime_zero(void)
-+{
-+#ifdef PLATFORM_LINUX
-+	return ktime_set(0, 0);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+/*
-+ *   cmp1  < cmp2: return <0
-+ *   cmp1 == cmp2: return 0
-+ *   cmp1  > cmp2: return >0
-+ */
-+int rtw_sptime_cmp(const sysptime cmp1, const sysptime cmp2)
-+{
-+#ifdef PLATFORM_LINUX
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	return ktime_compare(cmp1, cmp2);
-+	#else
-+	if (cmp1.tv64 < cmp2.tv64)
-+		return -1;
-+	if (cmp1.tv64 > cmp2.tv64)
-+		return 1;
-+	return 0;
-+	#endif
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+bool rtw_sptime_eql(const sysptime cmp1, const sysptime cmp2)
-+{
-+#ifdef PLATFORM_LINUX
-+	return rtw_sptime_cmp(cmp1, cmp2) == 0;
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+bool rtw_sptime_is_zero(const sysptime sptime)
-+{
-+#ifdef PLATFORM_LINUX
-+	return rtw_sptime_cmp(sptime, rtw_sptime_zero()) == 0;
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+/*
-+ * sub = lhs - rhs, in normalized form
-+ */
-+sysptime rtw_sptime_sub(const sysptime lhs, const sysptime rhs)
-+{
-+#ifdef PLATFORM_LINUX
-+	return ktime_sub(lhs, rhs);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+/*
-+ * add = lhs + rhs, in normalized form
-+ */
-+sysptime rtw_sptime_add(const sysptime lhs, const sysptime rhs)
-+{
-+#ifdef PLATFORM_LINUX
-+	return ktime_add(lhs, rhs);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+s64 rtw_sptime_to_ms(const sysptime sptime)
-+{
-+#ifdef PLATFORM_LINUX
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	return ktime_to_ms(sptime);
-+	#else
-+	struct timeval tv = ktime_to_timeval(sptime);
-+
-+	return (s64) tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
-+	#endif
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+sysptime rtw_ms_to_sptime(u64 ms)
-+{
-+#ifdef PLATFORM_LINUX
-+	return ns_to_ktime(ms * NSEC_PER_MSEC);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+s64 rtw_sptime_to_us(const sysptime sptime)
-+{
-+#ifdef PLATFORM_LINUX
-+	#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22))
-+	return ktime_to_us(sptime);
-+	#else
-+	struct timeval tv = ktime_to_timeval(sptime);
-+
-+	return (s64) tv.tv_sec * USEC_PER_SEC + tv.tv_usec;
-+	#endif
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+sysptime rtw_us_to_sptime(u64 us)
-+{
-+#ifdef PLATFORM_LINUX
-+	return ns_to_ktime(us * NSEC_PER_USEC);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+s64 rtw_sptime_to_ns(const sysptime sptime)
-+{
-+#ifdef PLATFORM_LINUX
-+	return ktime_to_ns(sptime);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+sysptime rtw_ns_to_sptime(u64 ns)
-+{
-+#ifdef PLATFORM_LINUX
-+	return ns_to_ktime(ns);
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+s64 rtw_sptime_diff_ms(const sysptime start, const sysptime end)
-+{
-+	sysptime diff;
-+
-+	diff = rtw_sptime_sub(end, start);
-+
-+	return rtw_sptime_to_ms(diff);
-+}
-+
-+s64 rtw_sptime_pass_ms(const sysptime start)
-+{
-+	sysptime cur, diff;
-+
-+	cur = rtw_sptime_get();
-+	diff = rtw_sptime_sub(cur, start);
-+
-+	return rtw_sptime_to_ms(diff);
-+}
-+
-+s64 rtw_sptime_diff_us(const sysptime start, const sysptime end)
-+{
-+	sysptime diff;
-+
-+	diff = rtw_sptime_sub(end, start);
-+
-+	return rtw_sptime_to_us(diff);
-+}
-+
-+s64 rtw_sptime_pass_us(const sysptime start)
-+{
-+	sysptime cur, diff;
-+
-+	cur = rtw_sptime_get();
-+	diff = rtw_sptime_sub(cur, start);
-+
-+	return rtw_sptime_to_us(diff);
-+}
-+
-+s64 rtw_sptime_diff_ns(const sysptime start, const sysptime end)
-+{
-+	sysptime diff;
-+
-+	diff = rtw_sptime_sub(end, start);
-+
-+	return rtw_sptime_to_ns(diff);
-+}
-+
-+s64 rtw_sptime_pass_ns(const sysptime start)
-+{
-+	sysptime cur, diff;
-+
-+	cur = rtw_sptime_get();
-+	diff = rtw_sptime_sub(cur, start);
-+
-+	return rtw_sptime_to_ns(diff);
-+}
-+
-+void rtw_sleep_schedulable(int ms)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+
-+	u32 delta;
-+
-+	delta = (ms * HZ) / 1000; /* (ms) */
-+	if (delta == 0) {
-+		delta = 1;/* 1 ms */
-+	}
-+	set_current_state(TASK_INTERRUPTIBLE);
-+        schedule_timeout(delta);
-+	return;
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	DELAY(ms * 1000);
-+	return ;
-+#endif
-+
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisMSleep(ms * 1000); /* (us)*1000=(ms) */
-+
-+#endif
-+
-+}
-+
-+
-+void rtw_msleep_os(int ms)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
-+	if (ms < 20) {
-+		unsigned long us = ms * 1000UL;
-+		usleep_range(us, us + 1000UL);
-+	} else
-+#endif
-+		msleep((unsigned int)ms);
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	/* Delay for delay microseconds */
-+	DELAY(ms * 1000);
-+	return ;
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisMSleep(ms * 1000); /* (us)*1000=(ms) */
-+
-+#endif
-+
-+
-+}
-+void rtw_usleep_os(int us)
-+{
-+#ifdef PLATFORM_LINUX
-+
-+	/* msleep((unsigned int)us); */
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36))
-+	usleep_range(us, us + 1);
-+#else
-+	if (1 < (us / 1000))
-+		msleep(1);
-+	else
-+		msleep((us / 1000) + 1);
-+#endif
-+#endif
-+
-+#ifdef PLATFORM_FREEBSD
-+	/* Delay for delay microseconds */
-+	DELAY(us);
-+
-+	return ;
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisMSleep(us); /* (us) */
-+
-+#endif
-+
-+
-+}
-+
-+
-+#ifdef DBG_DELAY_OS
-+void _rtw_mdelay_os(int ms, const char *func, const int line)
-+{
-+#if 0
-+	if (ms > 10)
-+		RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms);
-+	rtw_msleep_os(ms);
-+	return;
-+#endif
-+
-+
-+	RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms);
-+
-+#if defined(PLATFORM_LINUX)
-+
-+	mdelay((unsigned long)ms);
-+
-+#elif defined(PLATFORM_WINDOWS)
-+
-+	NdisStallExecution(ms * 1000); /* (us)*1000=(ms) */
-+
-+#endif
-+
-+
-+}
-+void _rtw_udelay_os(int us, const char *func, const int line)
-+{
-+
-+#if 0
-+	if (us > 1000) {
-+		RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, us);
-+		rtw_usleep_os(us);
-+		return;
-+	}
-+#endif
-+
-+
-+	RTW_INFO("%s:%d %s(%d)\n", func, line, __FUNCTION__, us);
-+
-+
-+#if defined(PLATFORM_LINUX)
-+
-+	udelay((unsigned long)us);
-+
-+#elif defined(PLATFORM_WINDOWS)
-+
-+	NdisStallExecution(us); /* (us) */
-+
-+#endif
-+
-+}
-+#else
-+void rtw_mdelay_os(int ms)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+
-+	mdelay((unsigned long)ms);
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	DELAY(ms * 1000);
-+	return ;
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisStallExecution(ms * 1000); /* (us)*1000=(ms) */
-+
-+#endif
-+
-+
-+}
-+void rtw_udelay_os(int us)
-+{
-+
-+#ifdef PLATFORM_LINUX
-+
-+	udelay((unsigned long)us);
-+
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	/* Delay for delay microseconds */
-+	DELAY(us);
-+	return ;
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+
-+	NdisStallExecution(us); /* (us) */
-+
-+#endif
-+
-+}
-+#endif
-+
-+void rtw_yield_os(void)
-+{
-+#ifdef PLATFORM_LINUX
-+	yield();
-+#endif
-+#ifdef PLATFORM_FREEBSD
-+	yield();
-+#endif
-+#ifdef PLATFORM_WINDOWS
-+	SwitchToThread();
-+#endif
-+}
-+
-+const char *_rtw_pwait_type_str[] = {
-+	[RTW_PWAIT_TYPE_MSLEEP] = "MS",
-+	[RTW_PWAIT_TYPE_USLEEP] = "US",
-+	[RTW_PWAIT_TYPE_YIELD] = "Y",
-+	[RTW_PWAIT_TYPE_MDELAY] = "MD",
-+	[RTW_PWAIT_TYPE_UDELAY] = "UD",
-+	[RTW_PWAIT_TYPE_NUM] = "unknown",
-+};
-+
-+static void rtw_pwctx_yield(int us)
-+{
-+	rtw_yield_os();
-+}
-+
-+static void (*const rtw_pwait_hdl[])(int)= {
-+	[RTW_PWAIT_TYPE_MSLEEP] = rtw_msleep_os,
-+	[RTW_PWAIT_TYPE_USLEEP] = rtw_usleep_os,
-+	[RTW_PWAIT_TYPE_YIELD] = rtw_pwctx_yield,
-+	[RTW_PWAIT_TYPE_MDELAY] = rtw_mdelay_os,
-+	[RTW_PWAIT_TYPE_UDELAY] = rtw_udelay_os,
-+};
-+
-+int rtw_pwctx_config(struct rtw_pwait_ctx *pwctx, enum rtw_pwait_type type, s32 time, s32 cnt_lmt)
-+{
-+	int ret = _FAIL;
-+
-+	if (!RTW_PWAIT_TYPE_VALID(type))
-+		goto exit;
-+
-+	pwctx->conf.type = type;
-+	pwctx->conf.wait_time = time;
-+	pwctx->conf.wait_cnt_lmt = cnt_lmt;
-+	pwctx->wait_hdl = rtw_pwait_hdl[type];
-+
-+	ret = _SUCCESS;
-+
-+exit:
-+	return ret;
-+}
-+
-+bool rtw_macaddr_is_larger(const u8 *a, const u8 *b)
-+{
-+	u32 va, vb;
-+
-+	va = be32_to_cpu(*((u32 *)a));
-+	vb = be32_to_cpu(*((u32 *)b));
-+	if (va > vb)
-+		return 1;
-+	else if (va < vb)
-+		return 0;
-+
-+	return be16_to_cpu(*((u16 *)(a + 4))) > be16_to_cpu(*((u16 *)(b + 4)));
-+}
-+
-+#define RTW_SUSPEND_LOCK_NAME "rtw_wifi"
-+#define RTW_SUSPEND_TRAFFIC_LOCK_NAME "rtw_wifi_traffic"
-+#define RTW_SUSPEND_RESUME_LOCK_NAME "rtw_wifi_resume"
-+#ifdef CONFIG_WAKELOCK
-+static struct wake_lock rtw_suspend_lock;
-+static struct wake_lock rtw_suspend_traffic_lock;
-+static struct wake_lock rtw_suspend_resume_lock;
-+#elif defined(CONFIG_ANDROID_POWER)
-+static android_suspend_lock_t rtw_suspend_lock = {
-+	.name = RTW_SUSPEND_LOCK_NAME
-+};
-+static android_suspend_lock_t rtw_suspend_traffic_lock = {
-+	.name = RTW_SUSPEND_TRAFFIC_LOCK_NAME
-+};
-+static android_suspend_lock_t rtw_suspend_resume_lock = {
-+	.name = RTW_SUSPEND_RESUME_LOCK_NAME
-+};
-+#endif
-+
-+inline void rtw_suspend_lock_init(void)
-+{
-+#ifdef CONFIG_WAKELOCK
-+	wake_lock_init(&rtw_suspend_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_LOCK_NAME);
-+	wake_lock_init(&rtw_suspend_traffic_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_TRAFFIC_LOCK_NAME);
-+	wake_lock_init(&rtw_suspend_resume_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_RESUME_LOCK_NAME);
-+#elif defined(CONFIG_ANDROID_POWER)
-+	android_init_suspend_lock(&rtw_suspend_lock);
-+	android_init_suspend_lock(&rtw_suspend_traffic_lock);
-+	android_init_suspend_lock(&rtw_suspend_resume_lock);
-+#endif
-+}
-+
-+inline void rtw_suspend_lock_uninit(void)
-+{
-+#ifdef CONFIG_WAKELOCK
-+	wake_lock_destroy(&rtw_suspend_lock);
-+	wake_lock_destroy(&rtw_suspend_traffic_lock);
-+	wake_lock_destroy(&rtw_suspend_resume_lock);
-+#elif defined(CONFIG_ANDROID_POWER)
-+	android_uninit_suspend_lock(&rtw_suspend_lock);
-+	android_uninit_suspend_lock(&rtw_suspend_traffic_lock);
-+	android_uninit_suspend_lock(&rtw_suspend_resume_lock);
-+#endif
-+}
-+
-+inline void rtw_lock_suspend(void)
-+{
-+#ifdef CONFIG_WAKELOCK
-+	wake_lock(&rtw_suspend_lock);
-+#elif defined(CONFIG_ANDROID_POWER)
-+	android_lock_suspend(&rtw_suspend_lock);
-+#endif
-+
-+#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
-+	/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
-+#endif
-+}
-+
-+inline void rtw_unlock_suspend(void)
-+{
-+#ifdef CONFIG_WAKELOCK
-+	wake_unlock(&rtw_suspend_lock);
-+#elif defined(CONFIG_ANDROID_POWER)
-+	android_unlock_suspend(&rtw_suspend_lock);
-+#endif
-+
-+#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
-+	/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
-+#endif
-+}
-+
-+inline void rtw_resume_lock_suspend(void)
-+{
-+#ifdef CONFIG_WAKELOCK
-+	wake_lock(&rtw_suspend_resume_lock);
-+#elif defined(CONFIG_ANDROID_POWER)
-+	android_lock_suspend(&rtw_suspend_resume_lock);
-+#endif
-+
-+#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
-+	/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
-+#endif
-+}
-+
-+inline void rtw_resume_unlock_suspend(void)
-+{
-+#ifdef CONFIG_WAKELOCK
-+	wake_unlock(&rtw_suspend_resume_lock);
-+#elif defined(CONFIG_ANDROID_POWER)
-+	android_unlock_suspend(&rtw_suspend_resume_lock);
-+#endif
-+
-+#if  defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER)
-+	/* RTW_INFO("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); */
-+#endif
-+}
-+
-+inline void rtw_lock_suspend_timeout(u32 timeout_ms)
-+{
-+#ifdef CONFIG_WAKELOCK
-+	wake_lock_timeout(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms));
-+#elif defined(CONFIG_ANDROID_POWER)
-+	android_lock_suspend_auto_expire(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms));
-+#endif
-+}
-+
-+
-+inline void rtw_lock_traffic_suspend_timeout(u32 timeout_ms)
-+{
-+#ifdef CONFIG_WAKELOCK
-+	wake_lock_timeout(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms));
-+#elif defined(CONFIG_ANDROID_POWER)
-+	android_lock_suspend_auto_expire(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms));
-+#endif
-+	/* RTW_INFO("traffic lock timeout:%d\n", timeout_ms); */
-+}
-+
-+inline void rtw_set_bit(int nr, unsigned long *addr)
-+{
-+#ifdef PLATFORM_LINUX
-+	set_bit(nr, addr);
-+#else
-+	#error "TBD\n";
-+#endif
-+}
-+
-+inline void rtw_clear_bit(int nr, unsigned long *addr)
-+{
-+#ifdef PLATFORM_LINUX
-+	clear_bit(nr, addr);
-+#else
-+	#error "TBD\n";
-+#endif
-+}
-+
-+inline int rtw_test_and_clear_bit(int nr, unsigned long *addr)
-+{
-+#ifdef PLATFORM_LINUX
-+	return test_and_clear_bit(nr, addr);
-+#else
-+	#error "TBD\n";
-+#endif
-+}
-+
-+inline void ATOMIC_SET(ATOMIC_T *v, int i)
-+{
-+#ifdef PLATFORM_LINUX
-+	atomic_set(v, i);
-+#elif defined(PLATFORM_WINDOWS)
-+	*v = i; /* other choice???? */
-+#elif defined(PLATFORM_FREEBSD)
-+	atomic_set_int(v, i);
-+#endif
-+}
-+
-+inline int ATOMIC_READ(ATOMIC_T *v)
-+{
-+#ifdef PLATFORM_LINUX
-+	return atomic_read(v);
-+#elif defined(PLATFORM_WINDOWS)
-+	return *v; /* other choice???? */
-+#elif defined(PLATFORM_FREEBSD)
-+	return atomic_load_acq_32(v);
-+#endif
-+}
-+
-+inline void ATOMIC_ADD(ATOMIC_T *v, int i)
-+{
-+#ifdef PLATFORM_LINUX
-+	atomic_add(i, v);
-+#elif defined(PLATFORM_WINDOWS)
-+	InterlockedAdd(v, i);
-+#elif defined(PLATFORM_FREEBSD)
-+	atomic_add_int(v, i);
-+#endif
-+}
-+inline void ATOMIC_SUB(ATOMIC_T *v, int i)
-+{
-+#ifdef PLATFORM_LINUX
-+	atomic_sub(i, v);
-+#elif defined(PLATFORM_WINDOWS)
-+	InterlockedAdd(v, -i);
-+#elif defined(PLATFORM_FREEBSD)
-+	atomic_subtract_int(v, i);
-+#endif
-+}
-+
-+inline void ATOMIC_INC(ATOMIC_T *v)
-+{
-+#ifdef PLATFORM_LINUX
-+	atomic_inc(v);
-+#elif defined(PLATFORM_WINDOWS)
-+	InterlockedIncrement(v);
-+#elif defined(PLATFORM_FREEBSD)
-+	atomic_add_int(v, 1);
-+#endif
-+}
-+
-+inline void ATOMIC_DEC(ATOMIC_T *v)
-+{
-+#ifdef PLATFORM_LINUX
-+	atomic_dec(v);
-+#elif defined(PLATFORM_WINDOWS)
-+	InterlockedDecrement(v);
-+#elif defined(PLATFORM_FREEBSD)
-+	atomic_subtract_int(v, 1);
-+#endif
-+}
-+
-+inline int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i)
-+{
-+#ifdef PLATFORM_LINUX
-+	return atomic_add_return(i, v);
-+#elif defined(PLATFORM_WINDOWS)
-+	return InterlockedAdd(v, i);
-+#elif defined(PLATFORM_FREEBSD)
-+	atomic_add_int(v, i);
-+	return atomic_load_acq_32(v);
-+#endif
-+}
-+
-+inline int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i)
-+{
-+#ifdef PLATFORM_LINUX
-+	return atomic_sub_return(i, v);
-+#elif defined(PLATFORM_WINDOWS)
-+	return InterlockedAdd(v, -i);
-+#elif defined(PLATFORM_FREEBSD)
-+	atomic_subtract_int(v, i);
-+	return atomic_load_acq_32(v);
-+#endif
-+}
-+
-+inline int ATOMIC_INC_RETURN(ATOMIC_T *v)
-+{
-+#ifdef PLATFORM_LINUX
-+	return atomic_inc_return(v);
-+#elif defined(PLATFORM_WINDOWS)
-+	return InterlockedIncrement(v);
-+#elif defined(PLATFORM_FREEBSD)
-+	atomic_add_int(v, 1);
-+	return atomic_load_acq_32(v);
-+#endif
-+}
-+
-+inline int ATOMIC_DEC_RETURN(ATOMIC_T *v)
-+{
-+#ifdef PLATFORM_LINUX
-+	return atomic_dec_return(v);
-+#elif defined(PLATFORM_WINDOWS)
-+	return InterlockedDecrement(v);
-+#elif defined(PLATFORM_FREEBSD)
-+	atomic_subtract_int(v, 1);
-+	return atomic_load_acq_32(v);
-+#endif
-+}
-+
-+inline bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u)
-+{
-+#ifdef PLATFORM_LINUX
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 15))
-+	return atomic_add_unless(v, 1, u);
-+#else
-+	/* only make sure not exceed after this function */
-+	if (ATOMIC_INC_RETURN(v) > u) {
-+		ATOMIC_DEC(v);
-+		return 0;
-+	}
-+	return 1;
-+#endif
-+#else
-+	#error "TBD\n"
-+#endif
-+}
-+
-+#ifdef PLATFORM_LINUX
-+/*
-+* Open a file with the specific @param path, @param flag, @param mode
-+* @param fpp the pointer of struct file pointer to get struct file pointer while file opening is success
-+* @param path the path of the file to open
-+* @param flag file operation flags, please refer to linux document
-+* @param mode please refer to linux document
-+* @return Linux specific error code
-+*/
-+static int openFile(struct file **fpp, const char *path, int flag, int mode)
-+{
-+	struct file *fp;
-+
-+	fp = filp_open(path, flag, mode);
-+	if (IS_ERR(fp)) {
-+		*fpp = NULL;
-+		return PTR_ERR(fp);
-+	} else {
-+		*fpp = fp;
-+		return 0;
-+	}
-+}
-+
-+/*
-+* Close the file with the specific @param fp
-+* @param fp the pointer of struct file to close
-+* @return always 0
-+*/
-+static int closeFile(struct file *fp)
-+{
-+	filp_close(fp, NULL);
-+	return 0;
-+}
-+
-+static int readFile(struct file *fp, char *buf, int len)
-+{
-+	int rlen = 0, sum = 0;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
-+	if (!(fp->f_mode & FMODE_CAN_READ))
-+#else
-+	if (!fp->f_op || !fp->f_op->read)
-+#endif
-+		return -EPERM;
-+
-+	while (sum < len) {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
-+		rlen = kernel_read(fp, buf + sum, len - sum, &fp->f_pos);
-+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
-+		rlen = __vfs_read(fp, buf + sum, len - sum, &fp->f_pos);
-+#else
-+		rlen = fp->f_op->read(fp, buf + sum, len - sum, &fp->f_pos);
-+#endif
-+		if (rlen > 0)
-+			sum += rlen;
-+		else if (0 != rlen)
-+			return rlen;
-+		else
-+			break;
-+	}
-+
-+	return  sum;
-+
-+}
-+
-+static int writeFile(struct file *fp, char *buf, int len)
-+{
-+	int wlen = 0, sum = 0;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
-+	if (!(fp->f_mode & FMODE_CAN_WRITE))
-+#else
-+	if (!fp->f_op || !fp->f_op->write)
-+#endif
-+		return -EPERM;
-+
-+	while (sum < len) {
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
-+		wlen = kernel_write(fp, buf + sum, len - sum, &fp->f_pos);
-+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
-+		wlen = __vfs_write(fp, buf + sum, len - sum, &fp->f_pos);
-+#else
-+		wlen = fp->f_op->write(fp, buf + sum, len - sum, &fp->f_pos);
-+#endif
-+		if (wlen > 0)
-+			sum += wlen;
-+		else if (0 != wlen)
-+			return wlen;
-+		else
-+			break;
-+	}
-+
-+	return sum;
-+
-+}
-+
-+/*
-+* Test if the specifi @param pathname is a direct and readable
-+* If readable, @param sz is not used
-+* @param pathname the name of the path to test
-+* @return Linux specific error code
-+*/
-+static int isDirReadable(const char *pathname, u32 *sz)
-+{
-+	struct path path;
-+	int error = 0;
-+
-+	return kern_path(pathname, LOOKUP_FOLLOW, &path);
-+}
-+
-+/*
-+* Test if the specifi @param path is a file and readable
-+* If readable, @param sz is got
-+* @param path the path of the file to test
-+* @return Linux specific error code
-+*/
-+static int isFileReadable(const char *path, u32 *sz)
-+{
-+	struct file *fp;
-+	int ret = 0;
-+	char buf;
-+
-+	fp = filp_open(path, O_RDONLY, 0);
-+	if (IS_ERR(fp))
-+		ret = PTR_ERR(fp);
-+	else {
-+		if (1 != readFile(fp, &buf, 1))
-+			ret = PTR_ERR(fp);
-+
-+		if (ret == 0 && sz) {
-+			#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0))
-+			*sz = i_size_read(fp->f_path.dentry->d_inode);
-+			#else
-+			*sz = i_size_read(fp->f_dentry->d_inode);
-+			#endif
-+		}
-+
-+		filp_close(fp, NULL);
-+	}
-+	return ret;
-+}
-+
-+/*
-+* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most
-+* @param path the path of the file to open and read
-+* @param buf the starting address of the buffer to store file content
-+* @param sz how many bytes to read at most
-+* @return the byte we've read, or Linux specific error code
-+*/
-+static int retriveFromFile(const char *path, u8 *buf, u32 sz)
-+{
-+	int ret = -1;
-+	struct file *fp;
-+
-+	if (path && buf) {
-+		ret = openFile(&fp, path, O_RDONLY, 0);
-+		if (0 == ret) {
-+			RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp);
-+
-+			ret = readFile(fp, buf, sz);
-+			closeFile(fp);
-+
-+			RTW_INFO("%s readFile, ret:%d\n", __FUNCTION__, ret);
-+
-+		} else
-+			RTW_INFO("%s openFile path:%s Fail, ret:%d\n", __FUNCTION__, path, ret);
-+	} else {
-+		RTW_INFO("%s NULL pointer\n", __FUNCTION__);
-+		ret =  -EINVAL;
-+	}
-+	return ret;
-+}
-+
-+/*
-+* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file
-+* @param path the path of the file to open and write
-+* @param buf the starting address of the data to write into file
-+* @param sz how many bytes to write at most
-+* @return the byte we've written, or Linux specific error code
-+*/
-+static int storeToFile(const char *path, u8 *buf, u32 sz)
-+{
-+	int ret = 0;
-+	struct file *fp;
-+
-+	if (path && buf) {
-+		ret = openFile(&fp, path, O_CREAT | O_WRONLY, 0666);
-+		if (0 == ret) {
-+			RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp);
-+
-+			ret = writeFile(fp, buf, sz);
-+			closeFile(fp);
-+
-+			RTW_INFO("%s writeFile, ret:%d\n", __FUNCTION__, ret);
-+
-+		} else
-+			RTW_INFO("%s openFile path:%s Fail, ret:%d\n", __FUNCTION__, path, ret);
-+	} else {
-+		RTW_INFO("%s NULL pointer\n", __FUNCTION__);
-+		ret =  -EINVAL;
-+	}
-+	return ret;
-+}
-+#endif /* PLATFORM_LINUX */
-+
-+/*
-+* Test if the specifi @param path is a direct and readable
-+* @param path the path of the direct to test
-+* @return _TRUE or _FALSE
-+*/
-+int rtw_is_dir_readable(const char *path)
-+{
-+#ifdef PLATFORM_LINUX
-+	if (isDirReadable(path, NULL) == 0)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+#else
-+	/* Todo... */
-+	return _FALSE;
-+#endif
-+}
-+
-+/*
-+* Test if the specifi @param path is a file and readable
-+* @param path the path of the file to test
-+* @return _TRUE or _FALSE
-+*/
-+int rtw_is_file_readable(const char *path)
-+{
-+#ifdef PLATFORM_LINUX
-+	if (isFileReadable(path, NULL) == 0)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+#else
-+	/* Todo... */
-+	return _FALSE;
-+#endif
-+}
-+
-+/*
-+* Test if the specifi @param path is a file and readable.
-+* If readable, @param sz is got
-+* @param path the path of the file to test
-+* @return _TRUE or _FALSE
-+*/
-+int rtw_is_file_readable_with_size(const char *path, u32 *sz)
-+{
-+#ifdef PLATFORM_LINUX
-+	if (isFileReadable(path, sz) == 0)
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+#else
-+	/* Todo... */
-+	return _FALSE;
-+#endif
-+}
-+
-+/*
-+* Test if the specifi @param path is a readable file with valid size.
-+* If readable, @param sz is got
-+* @param path the path of the file to test
-+* @return _TRUE or _FALSE
-+*/
-+int rtw_readable_file_sz_chk(const char *path, u32 sz)
-+{
-+	u32 fsz;
-+
-+	if (rtw_is_file_readable_with_size(path, &fsz) == _FALSE)
-+		return _FALSE;
-+
-+	if (fsz > sz)
-+		return _FALSE;
-+	
-+	return _TRUE;
-+}
-+
-+/*
-+* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most
-+* @param path the path of the file to open and read
-+* @param buf the starting address of the buffer to store file content
-+* @param sz how many bytes to read at most
-+* @return the byte we've read
-+*/
-+int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz)
-+{
-+#ifdef PLATFORM_LINUX
-+	int ret = retriveFromFile(path, buf, sz);
-+	return ret >= 0 ? ret : 0;
-+#else
-+	/* Todo... */
-+	return 0;
-+#endif
-+}
-+
-+/*
-+* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file
-+* @param path the path of the file to open and write
-+* @param buf the starting address of the data to write into file
-+* @param sz how many bytes to write at most
-+* @return the byte we've written
-+*/
-+int rtw_store_to_file(const char *path, u8 *buf, u32 sz)
-+{
-+#ifdef PLATFORM_LINUX
-+	int ret = storeToFile(path, buf, sz);
-+	return ret >= 0 ? ret : 0;
-+#else
-+	/* Todo... */
-+	return 0;
-+#endif
-+}
-+
-+#ifdef PLATFORM_LINUX
-+struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv)
-+{
-+	struct net_device *pnetdev;
-+	struct rtw_netdev_priv_indicator *pnpi;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4);
-+#else
-+	pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));
-+#endif
-+	if (!pnetdev)
-+		goto RETURN;
-+
-+	pnpi = netdev_priv(pnetdev);
-+	pnpi->priv = old_priv;
-+	pnpi->sizeof_priv = sizeof_priv;
-+
-+RETURN:
-+	return pnetdev;
-+}
-+
-+struct net_device *rtw_alloc_etherdev(int sizeof_priv)
-+{
-+	struct net_device *pnetdev;
-+	struct rtw_netdev_priv_indicator *pnpi;
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
-+	pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4);
-+#else
-+	pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator));
-+#endif
-+	if (!pnetdev)
-+		goto RETURN;
-+
-+	pnpi = netdev_priv(pnetdev);
-+
-+	pnpi->priv = rtw_zvmalloc(sizeof_priv);
-+	if (!pnpi->priv) {
-+		free_netdev(pnetdev);
-+		pnetdev = NULL;
-+		goto RETURN;
-+	}
-+
-+	pnpi->sizeof_priv = sizeof_priv;
-+RETURN:
-+	return pnetdev;
-+}
-+
-+void rtw_free_netdev(struct net_device *netdev)
-+{
-+	struct rtw_netdev_priv_indicator *pnpi;
-+
-+	if (!netdev)
-+		goto RETURN;
-+
-+	pnpi = netdev_priv(netdev);
-+
-+	if (!pnpi->priv)
-+		goto RETURN;
-+
-+	free_netdev(netdev);
-+
-+RETURN:
-+	return;
-+}
-+
-+#endif
-+
-+#ifdef PLATFORM_FREEBSD
-+/*
-+ * Copy a buffer from userspace and write into kernel address
-+ * space.
-+ *
-+ * This emulation just calls the FreeBSD copyin function (to
-+ * copy data from user space buffer into a kernel space buffer)
-+ * and is designed to be used with the above io_write_wrapper.
-+ *
-+ * This function should return the number of bytes not copied.
-+ * I.e. success results in a zero value.
-+ * Negative error values are not returned.
-+ */
-+unsigned long
-+copy_from_user(void *to, const void *from, unsigned long n)
-+{
-+	if (copyin(from, to, n) != 0) {
-+		/* Any errors will be treated as a failure
-+		   to copy any of the requested bytes */
-+		return n;
-+	}
-+
-+	return 0;
-+}
-+
-+unsigned long
-+copy_to_user(void *to, const void *from, unsigned long n)
-+{
-+	if (copyout(from, to, n) != 0) {
-+		/* Any errors will be treated as a failure
-+		   to copy any of the requested bytes */
-+		return n;
-+	}
-+
-+	return 0;
-+}
-+
-+
-+/*
-+ * The usb_register and usb_deregister functions are used to register
-+ * usb drivers with the usb subsystem. In this compatibility layer
-+ * emulation a list of drivers (struct usb_driver) is maintained
-+ * and is used for probing/attaching etc.
-+ *
-+ * usb_register and usb_deregister simply call these functions.
-+ */
-+int
-+usb_register(struct usb_driver *driver)
-+{
-+	rtw_usb_linux_register(driver);
-+	return 0;
-+}
-+
-+
-+int
-+usb_deregister(struct usb_driver *driver)
-+{
-+	rtw_usb_linux_deregister(driver);
-+	return 0;
-+}
-+
-+void module_init_exit_wrapper(void *arg)
-+{
-+	int (*func)(void) = arg;
-+	func();
-+	return;
-+}
-+
-+#endif /* PLATFORM_FREEBSD */
-+
-+#ifdef CONFIG_PLATFORM_SPRD
-+	#ifdef do_div
-+		#undef do_div
-+	#endif
-+	#include <asm-generic/div64.h>
-+#endif
-+
-+u64 rtw_modular64(u64 x, u64 y)
-+{
-+#ifdef PLATFORM_LINUX
-+	return do_div(x, y);
-+#elif defined(PLATFORM_WINDOWS)
-+	return x % y;
-+#elif defined(PLATFORM_FREEBSD)
-+	return x % y;
-+#endif
-+}
-+
-+u64 rtw_division64(u64 x, u64 y)
-+{
-+#ifdef PLATFORM_LINUX
-+	do_div(x, y);
-+	return x;
-+#elif defined(PLATFORM_WINDOWS)
-+	return x / y;
-+#elif defined(PLATFORM_FREEBSD)
-+	return x / y;
-+#endif
-+}
-+
-+inline u32 rtw_random32(void)
-+{
-+#ifdef PLATFORM_LINUX
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0))
-+	return prandom_u32();
-+#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 18))
-+	u32 random_int;
-+	get_random_bytes(&random_int , 4);
-+	return random_int;
-+#else
-+	return random32();
-+#endif
-+#elif defined(PLATFORM_WINDOWS)
-+#error "to be implemented\n"
-+#elif defined(PLATFORM_FREEBSD)
-+#error "to be implemented\n"
-+#endif
-+}
-+
-+void rtw_buf_free(u8 **buf, u32 *buf_len)
-+{
-+	u32 ori_len;
-+
-+	if (!buf || !buf_len)
-+		return;
-+
-+	ori_len = *buf_len;
-+
-+	if (*buf) {
-+		u32 tmp_buf_len = *buf_len;
-+		*buf_len = 0;
-+		rtw_mfree(*buf, tmp_buf_len);
-+		*buf = NULL;
-+	}
-+}
-+
-+void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len)
-+{
-+	u32 ori_len = 0, dup_len = 0;
-+	u8 *ori = NULL;
-+	u8 *dup = NULL;
-+
-+	if (!buf || !buf_len)
-+		return;
-+
-+	if (!src || !src_len)
-+		goto keep_ori;
-+
-+	/* duplicate src */
-+	dup = rtw_malloc(src_len);
-+	if (dup) {
-+		dup_len = src_len;
-+		_rtw_memcpy(dup, src, dup_len);
-+	}
-+
-+keep_ori:
-+	ori = *buf;
-+	ori_len = *buf_len;
-+
-+	/* replace buf with dup */
-+	*buf_len = 0;
-+	*buf = dup;
-+	*buf_len = dup_len;
-+
-+	/* free ori */
-+	if (ori && ori_len > 0)
-+		rtw_mfree(ori, ori_len);
-+}
-+
-+
-+/**
-+ * rtw_cbuf_full - test if cbuf is full
-+ * @cbuf: pointer of struct rtw_cbuf
-+ *
-+ * Returns: _TRUE if cbuf is full
-+ */
-+inline bool rtw_cbuf_full(struct rtw_cbuf *cbuf)
-+{
-+	return (cbuf->write == cbuf->read - 1) ? _TRUE : _FALSE;
-+}
-+
-+/**
-+ * rtw_cbuf_empty - test if cbuf is empty
-+ * @cbuf: pointer of struct rtw_cbuf
-+ *
-+ * Returns: _TRUE if cbuf is empty
-+ */
-+inline bool rtw_cbuf_empty(struct rtw_cbuf *cbuf)
-+{
-+	return (cbuf->write == cbuf->read) ? _TRUE : _FALSE;
-+}
-+
-+/**
-+ * rtw_cbuf_push - push a pointer into cbuf
-+ * @cbuf: pointer of struct rtw_cbuf
-+ * @buf: pointer to push in
-+ *
-+ * Lock free operation, be careful of the use scheme
-+ * Returns: _TRUE push success
-+ */
-+bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf)
-+{
-+	if (rtw_cbuf_full(cbuf))
-+		return _FAIL;
-+
-+	if (0)
-+		RTW_INFO("%s on %u\n", __func__, cbuf->write);
-+	cbuf->bufs[cbuf->write] = buf;
-+	cbuf->write = (cbuf->write + 1) % cbuf->size;
-+
-+	return _SUCCESS;
-+}
-+
-+/**
-+ * rtw_cbuf_pop - pop a pointer from cbuf
-+ * @cbuf: pointer of struct rtw_cbuf
-+ *
-+ * Lock free operation, be careful of the use scheme
-+ * Returns: pointer popped out
-+ */
-+void *rtw_cbuf_pop(struct rtw_cbuf *cbuf)
-+{
-+	void *buf;
-+	if (rtw_cbuf_empty(cbuf))
-+		return NULL;
-+
-+	if (0)
-+		RTW_INFO("%s on %u\n", __func__, cbuf->read);
-+	buf = cbuf->bufs[cbuf->read];
-+	cbuf->read = (cbuf->read + 1) % cbuf->size;
-+
-+	return buf;
-+}
-+
-+/**
-+ * rtw_cbuf_alloc - allocte a rtw_cbuf with given size and do initialization
-+ * @size: size of pointer
-+ *
-+ * Returns: pointer of srtuct rtw_cbuf, NULL for allocation failure
-+ */
-+struct rtw_cbuf *rtw_cbuf_alloc(u32 size)
-+{
-+	struct rtw_cbuf *cbuf;
-+
-+	cbuf = (struct rtw_cbuf *)rtw_malloc(sizeof(*cbuf) + sizeof(void *) * size);
-+
-+	if (cbuf) {
-+		cbuf->write = cbuf->read = 0;
-+		cbuf->size = size;
-+	}
-+
-+	return cbuf;
-+}
-+
-+/**
-+ * rtw_cbuf_free - free the given rtw_cbuf
-+ * @cbuf: pointer of struct rtw_cbuf to free
-+ */
-+void rtw_cbuf_free(struct rtw_cbuf *cbuf)
-+{
-+	rtw_mfree((u8 *)cbuf, sizeof(*cbuf) + sizeof(void *) * cbuf->size);
-+}
-+
-+/**
-+ * map_readN - read a range of map data
-+ * @map: map to read
-+ * @offset: start address to read
-+ * @len: length to read
-+ * @buf: pointer of buffer to store data read
-+ *
-+ * Returns: _SUCCESS or _FAIL
-+ */
-+int map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf)
-+{
-+	const struct map_seg_t *seg;
-+	int ret = _FAIL;
-+	int i;
-+
-+	if (len == 0) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	if (offset + len > map->len) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	_rtw_memset(buf, map->init_value, len);
-+
-+	for (i = 0; i < map->seg_num; i++) {
-+		u8 *c_dst, *c_src;
-+		u16 c_len;
-+
-+		seg = map->segs + i;
-+		if (seg->sa + seg->len <= offset || seg->sa >= offset + len)
-+			continue;
-+
-+		if (seg->sa >= offset) {
-+			c_dst = buf + (seg->sa - offset);
-+			c_src = seg->c;
-+			if (seg->sa + seg->len <= offset + len)
-+				c_len = seg->len;
-+			else
-+				c_len = offset + len - seg->sa;
-+		} else {
-+			c_dst = buf;
-+			c_src = seg->c + (offset - seg->sa);
-+			if (seg->sa + seg->len >= offset + len)
-+				c_len = len;
-+			else
-+				c_len = seg->sa + seg->len - offset;
-+		}
-+			
-+		_rtw_memcpy(c_dst, c_src, c_len);
-+	}
-+
-+exit:
-+	return ret;
-+}
-+
-+/**
-+ * map_read8 - read 1 byte of map data
-+ * @map: map to read
-+ * @offset: address to read
-+ *
-+ * Returns: value of data of specified offset. map.init_value if offset is out of range
-+ */
-+u8 map_read8(const struct map_t *map, u16 offset)
-+{
-+	const struct map_seg_t *seg;
-+	u8 val = map->init_value;
-+	int i;
-+
-+	if (offset + 1 > map->len) {
-+		rtw_warn_on(1);
-+		goto exit;
-+	}
-+
-+	for (i = 0; i < map->seg_num; i++) {
-+		seg = map->segs + i;
-+		if (seg->sa + seg->len <= offset || seg->sa >= offset + 1)
-+			continue;
-+
-+		val = *(seg->c + offset - seg->sa);
-+		break;
-+	}
-+
-+exit:
-+	return val;
-+}
-+
-+#ifdef CONFIG_RTW_MESH
-+int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms)
-+{
-+	struct blacklist_ent *ent;
-+	_list *list, *head;
-+	u8 exist = _FALSE, timeout = _FALSE;
-+
-+	enter_critical_bh(&blist->lock);
-+
-+	head = &blist->queue;
-+	list = get_next(head);
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
-+		list = get_next(list);
-+
-+		if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {
-+			exist = _TRUE;
-+			if (rtw_time_after(rtw_get_current_time(), ent->exp_time))
-+				timeout = _TRUE;
-+			ent->exp_time = rtw_get_current_time()
-+				+ rtw_ms_to_systime(timeout_ms);
-+			break;
-+		}
-+
-+		if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
-+			rtw_list_delete(&ent->list);
-+			rtw_mfree(ent, sizeof(struct blacklist_ent));
-+		}
-+	}
-+
-+	if (exist == _FALSE) {
-+		ent = rtw_malloc(sizeof(struct blacklist_ent));
-+		if (ent) {
-+			_rtw_memcpy(ent->addr, addr, ETH_ALEN);
-+			ent->exp_time = rtw_get_current_time()
-+				+ rtw_ms_to_systime(timeout_ms);
-+			rtw_list_insert_tail(&ent->list, head);
-+		}
-+	}
-+
-+	exit_critical_bh(&blist->lock);
-+
-+	return (exist == _TRUE && timeout == _FALSE) ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL);
-+}
-+
-+int rtw_blacklist_del(_queue *blist, const u8 *addr)
-+{
-+	struct blacklist_ent *ent = NULL;
-+	_list *list, *head;
-+	u8 exist = _FALSE;
-+
-+	enter_critical_bh(&blist->lock);
-+	head = &blist->queue;
-+	list = get_next(head);
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
-+		list = get_next(list);
-+
-+		if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {
-+			rtw_list_delete(&ent->list);
-+			rtw_mfree(ent, sizeof(struct blacklist_ent));
-+			exist = _TRUE;
-+			break;
-+		}
-+
-+		if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
-+			rtw_list_delete(&ent->list);
-+			rtw_mfree(ent, sizeof(struct blacklist_ent));
-+		}
-+	}
-+
-+	exit_critical_bh(&blist->lock);
-+
-+	return exist == _TRUE ? _SUCCESS : RTW_ALREADY;
-+}
-+
-+int rtw_blacklist_search(_queue *blist, const u8 *addr)
-+{
-+	struct blacklist_ent *ent = NULL;
-+	_list *list, *head;
-+	u8 exist = _FALSE;
-+
-+	enter_critical_bh(&blist->lock);
-+	head = &blist->queue;
-+	list = get_next(head);
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
-+		list = get_next(list);
-+
-+		if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) {
-+			if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
-+				rtw_list_delete(&ent->list);
-+				rtw_mfree(ent, sizeof(struct blacklist_ent));
-+			} else
-+				exist = _TRUE;
-+			break;
-+		}
-+
-+		if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
-+			rtw_list_delete(&ent->list);
-+			rtw_mfree(ent, sizeof(struct blacklist_ent));
-+		}
-+	}
-+
-+	exit_critical_bh(&blist->lock);
-+
-+	return exist;
-+}
-+
-+void rtw_blacklist_flush(_queue *blist)
-+{
-+	struct blacklist_ent *ent;
-+	_list *list, *head;
-+	_list tmp;
-+
-+	_rtw_init_listhead(&tmp);
-+
-+	enter_critical_bh(&blist->lock);
-+	rtw_list_splice_init(&blist->queue, &tmp);
-+	exit_critical_bh(&blist->lock);
-+
-+	head = &tmp;
-+	list = get_next(head);
-+	while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
-+		list = get_next(list);
-+		rtw_list_delete(&ent->list);
-+		rtw_mfree(ent, sizeof(struct blacklist_ent));
-+	}
-+}
-+
-+void dump_blacklist(void *sel, _queue *blist, const char *title)
-+{
-+	struct blacklist_ent *ent = NULL;
-+	_list *list, *head;
-+
-+	enter_critical_bh(&blist->lock);
-+	head = &blist->queue;
-+	list = get_next(head);
-+
-+	if (rtw_end_of_queue_search(head, list) == _FALSE) {
-+		if (title)
-+			RTW_PRINT_SEL(sel, "%s:\n", title);
-+	
-+		while (rtw_end_of_queue_search(head, list) == _FALSE) {
-+			ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
-+			list = get_next(list);
-+
-+			if (rtw_time_after(rtw_get_current_time(), ent->exp_time))
-+				RTW_PRINT_SEL(sel, MAC_FMT" expired\n", MAC_ARG(ent->addr));
-+			else
-+				RTW_PRINT_SEL(sel, MAC_FMT" %u\n", MAC_ARG(ent->addr)
-+					, rtw_get_remaining_time_ms(ent->exp_time));
-+		}
-+
-+	}
-+	exit_critical_bh(&blist->lock);
-+}
-+#endif
-+
-+/**
-+* is_null -
-+*
-+* Return	TRUE if c is null character
-+*		FALSE otherwise.
-+*/
-+inline BOOLEAN is_null(char c)
-+{
-+	if (c == '\0')
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+inline BOOLEAN is_all_null(char *c, int len)
-+{
-+	for (; len > 0; len--)
-+		if (c[len - 1] != '\0')
-+			return _FALSE;
-+
-+	return _TRUE;
-+}
-+
-+/**
-+* is_eol -
-+*
-+* Return	TRUE if c is represent for EOL (end of line)
-+*		FALSE otherwise.
-+*/
-+inline BOOLEAN is_eol(char c)
-+{
-+	if (c == '\r' || c == '\n')
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+/**
-+* is_space -
-+*
-+* Return	TRUE if c is represent for space
-+*		FALSE otherwise.
-+*/
-+inline BOOLEAN is_space(char c)
-+{
-+	if (c == ' ' || c == '\t')
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+/**
-+* IsHexDigit -
-+*
-+* Return	TRUE if chTmp is represent for hex digit
-+*		FALSE otherwise.
-+*/
-+inline BOOLEAN IsHexDigit(char chTmp)
-+{
-+	if ((chTmp >= '0' && chTmp <= '9') ||
-+		(chTmp >= 'a' && chTmp <= 'f') ||
-+		(chTmp >= 'A' && chTmp <= 'F'))
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+/**
-+* is_alpha -
-+*
-+* Return	TRUE if chTmp is represent for alphabet
-+*		FALSE otherwise.
-+*/
-+inline BOOLEAN is_alpha(char chTmp)
-+{
-+	if ((chTmp >= 'a' && chTmp <= 'z') ||
-+		(chTmp >= 'A' && chTmp <= 'Z'))
-+		return _TRUE;
-+	else
-+		return _FALSE;
-+}
-+
-+inline char alpha_to_upper(char c)
-+{
-+	if ((c >= 'a' && c <= 'z'))
-+		c = 'A' + (c - 'a');
-+	return c;
-+}
-+
-+int hex2num_i(char c)
-+{
-+	if (c >= '0' && c <= '9')
-+		return c - '0';
-+	if (c >= 'a' && c <= 'f')
-+		return c - 'a' + 10;
-+	if (c >= 'A' && c <= 'F')
-+		return c - 'A' + 10;
-+	return -1;
-+}
-+
-+int hex2byte_i(const char *hex)
-+{
-+	int a, b;
-+	a = hex2num_i(*hex++);
-+	if (a < 0)
-+		return -1;
-+	b = hex2num_i(*hex++);
-+	if (b < 0)
-+		return -1;
-+	return (a << 4) | b;
-+}
-+
-+int hexstr2bin(const char *hex, u8 *buf, size_t len)
-+{
-+	size_t i;
-+	int a;
-+	const char *ipos = hex;
-+	u8 *opos = buf;
-+
-+	for (i = 0; i < len; i++) {
-+		a = hex2byte_i(ipos);
-+		if (a < 0)
-+			return -1;
-+		*opos++ = a;
-+		ipos += 2;
-+	}
-+	return 0;
-+}
-+
-+/**
-+ * hwaddr_aton - Convert ASCII string to MAC address
-+ * @txt: MAC address as a string (e.g., "00:11:22:33:44:55")
-+ * @addr: Buffer for the MAC address (ETH_ALEN = 6 bytes)
-+ * Returns: 0 on success, -1 on failure (e.g., string not a MAC address)
-+ */
-+int hwaddr_aton_i(const char *txt, u8 *addr)
-+{
-+	int i;
-+
-+	for (i = 0; i < 6; i++) {
-+		int a, b;
-+
-+		a = hex2num_i(*txt++);
-+		if (a < 0)
-+			return -1;
-+		b = hex2num_i(*txt++);
-+		if (b < 0)
-+			return -1;
-+		*addr++ = (a << 4) | b;
-+		if (i < 5 && *txt++ != ':')
-+			return -1;
-+	}
-+
-+	return 0;
-+}
-+
-diff --git a/drivers/staging/rtl8723cs/platform/custom_country_chplan.h b/drivers/staging/rtl8723cs/platform/custom_country_chplan.h
-new file mode 100644
-index 000000000000..67f621fe54e4
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/custom_country_chplan.h
-@@ -0,0 +1,22 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+
-+#error "You have defined CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP to use a customized map of your own instead of the default one"
-+#error "Before removing these error notifications, please make sure regulatory certification requirements of your target markets"
-+
-+static const struct country_chplan CUSTOMIZED_country_chplan_map[] = {
-+	COUNTRY_CHPLAN_ENT("TW", 0x76, 1), /* Taiwan */
-+};
-+
-diff --git a/drivers/staging/rtl8723cs/platform/platform_ARM_SUN50IW1P1_sdio.c b/drivers/staging/rtl8723cs/platform/platform_ARM_SUN50IW1P1_sdio.c
-new file mode 100644
-index 000000000000..2586455de8c3
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_ARM_SUN50IW1P1_sdio.c
-@@ -0,0 +1,86 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*
-+ * Description:
-+ *	This file can be applied to following platforms:
-+ *	CONFIG_PLATFORM_ARM_SUN50IW1P1
-+ */
-+#include <drv_types.h>
-+#ifdef CONFIG_GPIO_WAKEUP
-+#include <linux/gpio.h>
-+#endif
-+
-+#ifdef CONFIG_MMC
-+#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
-+extern void sunxi_mmc_rescan_card(unsigned ids);
-+extern void sunxi_wlan_set_power(int on);
-+extern int sunxi_wlan_get_bus_index(void);
-+extern int sunxi_wlan_get_oob_irq(void);
-+extern int sunxi_wlan_get_oob_irq_flags(void);
-+#endif
-+#ifdef CONFIG_GPIO_WAKEUP
-+extern unsigned int oob_irq;
-+#endif
-+#endif /* CONFIG_MMC */
-+
-+/*
-+ * Return:
-+ *	0:	power on successfully
-+ *	others: power on failed
-+ */
-+int platform_wifi_power_on(void)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_MMC
-+	{
-+
-+#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
-+		int wlan_bus_index = sunxi_wlan_get_bus_index();
-+		if (wlan_bus_index < 0)
-+			return wlan_bus_index;
-+
-+		sunxi_wlan_set_power(1);
-+		mdelay(100);
-+		sunxi_mmc_rescan_card(wlan_bus_index);
-+#endif
-+		RTW_INFO("%s: power up, rescan card.\n", __FUNCTION__);
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
-+		oob_irq = sunxi_wlan_get_oob_irq();
-+#endif
-+#endif /* CONFIG_GPIO_WAKEUP */
-+	}
-+#endif /* CONFIG_MMC */
-+
-+	return ret;
-+}
-+
-+void platform_wifi_power_off(void)
-+{
-+#ifdef CONFIG_MMC
-+#if defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
-+	int wlan_bus_index = sunxi_wlan_get_bus_index();
-+	if (wlan_bus_index < 0)
-+		return;
-+
-+	sunxi_mmc_rescan_card(wlan_bus_index);
-+	mdelay(100);
-+	sunxi_wlan_set_power(0);
-+#endif
-+	RTW_INFO("%s: remove card, power off.\n", __FUNCTION__);
-+#endif /* CONFIG_MMC */
-+}
-diff --git a/drivers/staging/rtl8723cs/platform/platform_ARM_SUNnI_sdio.c b/drivers/staging/rtl8723cs/platform/platform_ARM_SUNnI_sdio.c
-new file mode 100644
-index 000000000000..8a52aa90cb0d
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_ARM_SUNnI_sdio.c
-@@ -0,0 +1,130 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*
-+ * Description:
-+ *	This file can be applied to following platforms:
-+ *	CONFIG_PLATFORM_ARM_SUN6I
-+ *	CONFIG_PLATFORM_ARM_SUN7I
-+ *	CONFIG_PLATFORM_ARM_SUN8I
-+ */
-+#include <drv_types.h>
-+#include <mach/sys_config.h>
-+#ifdef CONFIG_GPIO_WAKEUP
-+#include <linux/gpio.h>
-+#endif
-+
-+#ifdef CONFIG_MMC
-+static int sdc_id = -1;
-+static signed int gpio_eint_wlan = -1;
-+static u32 eint_wlan_handle = 0;
-+
-+#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
-+extern void sw_mci_rescan_card(unsigned id, unsigned insert);
-+#elif defined(CONFIG_PLATFORM_ARM_SUN8I)
-+extern void sunxi_mci_rescan_card(unsigned id, unsigned insert);
-+#endif
-+
-+#ifdef CONFIG_PLATFORM_ARM_SUN8I_W5P1
-+extern int get_rf_mod_type(void);
-+#else
-+extern int wifi_pm_get_mod_type(void);
-+#endif
-+
-+extern void wifi_pm_power(int on);
-+#ifdef CONFIG_GPIO_WAKEUP
-+extern unsigned int oob_irq;
-+#endif
-+#endif /* CONFIG_MMC */
-+
-+/*
-+ * Return:
-+ *	0:	power on successfully
-+ *	others: power on failed
-+ */
-+int platform_wifi_power_on(void)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_MMC
-+	{
-+		script_item_u val;
-+		script_item_value_type_e type;
-+
-+#ifdef CONFIG_PLATFORM_ARM_SUN8I_W5P1
-+		unsigned int mod_sel = get_rf_mod_type();
-+#else
-+		unsigned int mod_sel = wifi_pm_get_mod_type();
-+#endif
-+
-+		type = script_get_item("wifi_para", "wifi_sdc_id", &val);
-+		if (SCIRPT_ITEM_VALUE_TYPE_INT != type) {
-+			RTW_INFO("get wifi_sdc_id failed\n");
-+			ret = -1;
-+		} else {
-+			sdc_id = val.val;
-+			RTW_INFO("----- %s sdc_id: %d, mod_sel: %d\n", __FUNCTION__, sdc_id, mod_sel);
-+
-+#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
-+			sw_mci_rescan_card(sdc_id, 1);
-+#elif defined(CONFIG_PLATFORM_ARM_SUN8I)
-+			sunxi_mci_rescan_card(sdc_id, 1);
-+#endif
-+			mdelay(100);
-+			wifi_pm_power(1);
-+
-+			RTW_INFO("%s: power up, rescan card.\n", __FUNCTION__);
-+		}
-+
-+#ifdef CONFIG_GPIO_WAKEUP
-+#ifdef CONFIG_PLATFORM_ARM_SUN8I_W5P1
-+		type = script_get_item("wifi_para", "wl_host_wake", &val);
-+#else
-+#ifdef CONFIG_RTL8723B
-+		type = script_get_item("wifi_para", "rtl8723bs_wl_host_wake", &val);
-+#endif
-+#ifdef CONFIG_RTL8188E
-+		type = script_get_item("wifi_para", "rtl8189es_host_wake", &val);
-+#endif
-+#endif /* CONFIG_PLATFORM_ARM_SUN8I_W5P1 */
-+		if (SCIRPT_ITEM_VALUE_TYPE_PIO != type) {
-+			RTW_INFO("No definition of wake up host PIN\n");
-+			ret = -1;
-+		} else {
-+			gpio_eint_wlan = val.gpio.gpio;
-+#ifdef CONFIG_PLATFORM_ARM_SUN8I
-+			oob_irq = gpio_to_irq(gpio_eint_wlan);
-+#endif
-+		}
-+#endif /* CONFIG_GPIO_WAKEUP */
-+	}
-+#endif /* CONFIG_MMC */
-+
-+	return ret;
-+}
-+
-+void platform_wifi_power_off(void)
-+{
-+#ifdef CONFIG_MMC
-+#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
-+	sw_mci_rescan_card(sdc_id, 0);
-+#elif defined(CONFIG_PLATFORM_ARM_SUN8I)
-+	sunxi_mci_rescan_card(sdc_id, 0);
-+#endif
-+	mdelay(100);
-+	wifi_pm_power(0);
-+
-+	RTW_INFO("%s: remove card, power off.\n", __FUNCTION__);
-+#endif /* CONFIG_MMC */
-+}
-diff --git a/drivers/staging/rtl8723cs/platform/platform_ARM_SUNxI_sdio.c b/drivers/staging/rtl8723cs/platform/platform_ARM_SUNxI_sdio.c
-new file mode 100644
-index 000000000000..795b7e7f7998
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_ARM_SUNxI_sdio.c
-@@ -0,0 +1,90 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL
-+#ifdef CONFIG_WITS_EVB_V13
-+	#define SDIOID	0
-+#else /* !CONFIG_WITS_EVB_V13 */
-+	#define SDIOID (CONFIG_CHIP_ID == 1123 ? 3 : 1)
-+#endif /* !CONFIG_WITS_EVB_V13 */
-+
-+#define SUNXI_SDIO_WIFI_NUM_RTL8189ES  10
-+extern void sunximmc_rescan_card(unsigned id, unsigned insert);
-+extern int mmc_pm_get_mod_type(void);
-+extern int mmc_pm_gpio_ctrl(char *name, int level);
-+/*
-+ *	rtl8189es_shdn	= port:PH09<1><default><default><0>
-+ *	rtl8189es_wakeup	= port:PH10<1><default><default><1>
-+ *	rtl8189es_vdd_en  = port:PH11<1><default><default><0>
-+ *	rtl8189es_vcc_en  = port:PH12<1><default><default><0>
-+ */
-+
-+int rtl8189es_sdio_powerup(void)
-+{
-+	mmc_pm_gpio_ctrl("rtl8189es_vdd_en", 1);
-+	udelay(100);
-+	mmc_pm_gpio_ctrl("rtl8189es_vcc_en", 1);
-+	udelay(50);
-+	mmc_pm_gpio_ctrl("rtl8189es_shdn", 1);
-+	return 0;
-+}
-+
-+int rtl8189es_sdio_poweroff(void)
-+{
-+	mmc_pm_gpio_ctrl("rtl8189es_shdn", 0);
-+	mmc_pm_gpio_ctrl("rtl8189es_vcc_en", 0);
-+	mmc_pm_gpio_ctrl("rtl8189es_vdd_en", 0);
-+	return 0;
-+}
-+#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */
-+
-+/*
-+ * Return:
-+ *	0:	power on successfully
-+ *	others:	power on failed
-+ */
-+int platform_wifi_power_on(void)
-+{
-+	int ret = 0;
-+#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL
-+	unsigned int mod_sel = mmc_pm_get_mod_type();
-+#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */
-+
-+
-+#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL
-+	if (mod_sel == SUNXI_SDIO_WIFI_NUM_RTL8189ES) {
-+		rtl8189es_sdio_powerup();
-+		sunximmc_rescan_card(SDIOID, 1);
-+		printk("[rtl8189es] %s: power up, rescan card.\n", __FUNCTION__);
-+	} else {
-+		ret = -1;
-+		printk("[rtl8189es] %s: mod_sel = %d is incorrect.\n", __FUNCTION__, mod_sel);
-+	}
-+#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */
-+
-+	return ret;
-+}
-+
-+void platform_wifi_power_off(void)
-+{
-+#ifdef CONFIG_MMC_SUNXI_POWER_CONTROL
-+	sunximmc_rescan_card(SDIOID, 0);
-+#ifdef CONFIG_RTL8188E
-+	rtl8189es_sdio_poweroff();
-+	printk("[rtl8189es] %s: remove card, power off.\n", __FUNCTION__);
-+#endif /* CONFIG_RTL8188E */
-+#endif /* CONFIG_MMC_SUNXI_POWER_CONTROL */
-+}
-diff --git a/drivers/staging/rtl8723cs/platform/platform_ARM_SUNxI_usb.c b/drivers/staging/rtl8723cs/platform/platform_ARM_SUNxI_usb.c
-new file mode 100644
-index 000000000000..9c2abc4f6f44
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_ARM_SUNxI_usb.c
-@@ -0,0 +1,136 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*
-+ * Description:
-+ *	This file can be applied to following platforms:
-+ *	CONFIG_PLATFORM_ARM_SUNXI Series platform
-+ *
-+ */
-+
-+#include <drv_types.h>
-+#include <mach/sys_config.h>
-+
-+#ifdef CONFIG_PLATFORM_ARM_SUNxI
-+extern int sw_usb_disable_hcd(__u32 usbc_no);
-+extern int sw_usb_enable_hcd(__u32 usbc_no);
-+static int usb_wifi_host = 2;
-+#endif
-+
-+#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
-+extern int sw_usb_disable_hcd(__u32 usbc_no);
-+extern int sw_usb_enable_hcd(__u32 usbc_no);
-+extern void wifi_pm_power(int on);
-+static script_item_u item;
-+#endif
-+
-+#ifdef CONFIG_PLATFORM_ARM_SUN8I
-+extern int sunxi_usb_disable_hcd(__u32 usbc_no);
-+extern int sunxi_usb_enable_hcd(__u32 usbc_no);
-+extern void wifi_pm_power(int on);
-+static script_item_u item;
-+#endif
-+
-+
-+int platform_wifi_power_on(void)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_PLATFORM_ARM_SUNxI
-+#ifndef CONFIG_RTL8723A
-+	{
-+		/* ----------get usb_wifi_usbc_num------------- */
-+		ret = script_parser_fetch("usb_wifi_para", "usb_wifi_usbc_num", (int *)&usb_wifi_host, 64);
-+		if (ret != 0) {
-+			RTW_INFO("ERR: script_parser_fetch usb_wifi_usbc_num failed\n");
-+			ret = -ENOMEM;
-+			goto exit;
-+		}
-+		RTW_INFO("sw_usb_enable_hcd: usbc_num = %d\n", usb_wifi_host);
-+		sw_usb_enable_hcd(usb_wifi_host);
-+	}
-+#endif /* CONFIG_RTL8723A */
-+#endif /* CONFIG_PLATFORM_ARM_SUNxI */
-+
-+#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
-+	{
-+		script_item_value_type_e type;
-+
-+		type = script_get_item("wifi_para", "wifi_usbc_id", &item);
-+		if (SCIRPT_ITEM_VALUE_TYPE_INT != type) {
-+			printk("ERR: script_get_item wifi_usbc_id failed\n");
-+			ret = -ENOMEM;
-+			goto exit;
-+		}
-+
-+		printk("sw_usb_enable_hcd: usbc_num = %d\n", item.val);
-+		wifi_pm_power(1);
-+		mdelay(10);
-+
-+#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))
-+		sw_usb_enable_hcd(item.val);
-+#endif
-+	}
-+#endif /* defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) */
-+
-+#if defined(CONFIG_PLATFORM_ARM_SUN8I)
-+	{
-+		script_item_value_type_e type;
-+
-+		type = script_get_item("wifi_para", "wifi_usbc_id", &item);
-+		if (SCIRPT_ITEM_VALUE_TYPE_INT != type) {
-+			printk("ERR: script_get_item wifi_usbc_id failed\n");
-+			ret = -ENOMEM;
-+			goto exit;
-+		}
-+
-+		printk("sw_usb_enable_hcd: usbc_num = %d\n", item.val);
-+		wifi_pm_power(1);
-+		mdelay(10);
-+
-+#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))
-+		sunxi_usb_enable_hcd(item.val);
-+#endif
-+	}
-+#endif /* CONFIG_PLATFORM_ARM_SUN8I */
-+
-+exit:
-+	return ret;
-+}
-+
-+void platform_wifi_power_off(void)
-+{
-+
-+#ifdef CONFIG_PLATFORM_ARM_SUNxI
-+#ifndef CONFIG_RTL8723A
-+	RTW_INFO("sw_usb_disable_hcd: usbc_num = %d\n", usb_wifi_host);
-+	sw_usb_disable_hcd(usb_wifi_host);
-+#endif /* ifndef CONFIG_RTL8723A */
-+#endif /* CONFIG_PLATFORM_ARM_SUNxI */
-+
-+#if defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I)
-+	#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))
-+	sw_usb_disable_hcd(item.val);
-+	#endif
-+	wifi_pm_power(0);
-+#endif /* defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) */
-+
-+#if defined(CONFIG_PLATFORM_ARM_SUN8I)
-+	#if !(defined(CONFIG_RTL8723A)) && !(defined(CONFIG_RTL8723B))
-+	sunxi_usb_disable_hcd(item.val);
-+	#endif
-+	wifi_pm_power(0);
-+#endif /* defined(CONFIG_PLATFORM_ARM_SUN8I) */
-+
-+}
-diff --git a/drivers/staging/rtl8723cs/platform/platform_ARM_WMT_sdio.c b/drivers/staging/rtl8723cs/platform/platform_ARM_WMT_sdio.c
-new file mode 100644
-index 000000000000..d85002c15fd3
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_ARM_WMT_sdio.c
-@@ -0,0 +1,46 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include <drv_types.h>
-+#include <mach/wmt_iomux.h>
-+#include <linux/gpio.h>
-+
-+extern void wmt_detect_sdio2(void);
-+extern void force_remove_sdio2(void);
-+
-+int platform_wifi_power_on(void)
-+{
-+	int err = 0;
-+	err = gpio_request(WMT_PIN_GP62_SUSGPIO1, "wifi_chip_en");
-+	if (err < 0) {
-+		printk("request gpio for rtl8188eu failed!\n");
-+		return err;
-+	}
-+	gpio_direction_output(WMT_PIN_GP62_SUSGPIO1, 0);/* pull sus_gpio1 to 0 to open vcc_wifi. */
-+	printk("power on rtl8189.\n");
-+	msleep(500);
-+	wmt_detect_sdio2();
-+	printk("[rtl8189es] %s: new card, power on.\n", __FUNCTION__);
-+	return err;
-+}
-+
-+void platform_wifi_power_off(void)
-+{
-+	force_remove_sdio2();
-+
-+	gpio_direction_output(WMT_PIN_GP62_SUSGPIO1, 1);/* pull sus_gpio1 to 1 to close vcc_wifi. */
-+	printk("power off rtl8189.\n");
-+	gpio_free(WMT_PIN_GP62_SUSGPIO1);
-+	printk("[rtl8189es] %s: remove card, power off.\n", __FUNCTION__);
-+}
-diff --git a/drivers/staging/rtl8723cs/platform/platform_RTK_DMP_usb.c b/drivers/staging/rtl8723cs/platform/platform_RTK_DMP_usb.c
-new file mode 100644
-index 000000000000..cb740b2eebb5
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_RTK_DMP_usb.c
-@@ -0,0 +1,30 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include <drv_types.h>
-+
-+int platform_wifi_power_on(void)
-+{
-+	int ret = 0;
-+	u32 tmp;
-+	tmp = readl((volatile unsigned int *)0xb801a608);
-+	tmp &= 0xffffff00;
-+	tmp |= 0x55;
-+	writel(tmp, (volatile unsigned int *)0xb801a608); /* write dummy register for 1055 */
-+	return ret;
-+}
-+
-+void platform_wifi_power_off(void)
-+{
-+}
-diff --git a/drivers/staging/rtl8723cs/platform/platform_aml_s905_sdio.c b/drivers/staging/rtl8723cs/platform/platform_aml_s905_sdio.c
-new file mode 100644
-index 000000000000..334ca03c9801
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_aml_s905_sdio.c
-@@ -0,0 +1,54 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2018 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include <linux/printk.h>		/* pr_info(() */
-+#include <linux/delay.h>		/* msleep() */
-+#include "platform_aml_s905_sdio.h"	/* sdio_reinit() and etc */
-+
-+
-+/*
-+ * Return:
-+ *	0:	power on successfully
-+ *	others:	power on failed
-+ */
-+int platform_wifi_power_on(void)
-+{
-+	int ret = 0;
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
-+	ret = wifi_setup_dt();
-+	if (ret) {
-+		pr_err("%s: setup dt failed!!(%d)\n", __func__, ret);
-+		return -1;
-+	}
-+#endif /* kernel < 3.14.0 */
-+
-+#if 0 /* Seems redundancy? Already done before insert driver */
-+	pr_info("######%s:\n", __func__);
-+	extern_wifi_set_enable(0);
-+	msleep(500);
-+	extern_wifi_set_enable(1);
-+	msleep(500);
-+	sdio_reinit();
-+#endif
-+
-+	return ret;
-+}
-+
-+void platform_wifi_power_off(void)
-+{
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
-+	wifi_teardown_dt();
-+#endif /* kernel < 3.14.0 */
-+}
-diff --git a/drivers/staging/rtl8723cs/platform/platform_aml_s905_sdio.h b/drivers/staging/rtl8723cs/platform/platform_aml_s905_sdio.h
-new file mode 100644
-index 000000000000..2b87576dd629
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_aml_s905_sdio.h
-@@ -0,0 +1,28 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2018 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __PLATFORM_AML_S905_SDIO_H__
-+#define __PLATFORM_AML_S905_SDIO_H__
-+
-+#include <linux/version.h>	/* Linux vresion */
-+
-+extern void sdio_reinit(void);
-+extern void extern_wifi_set_enable(int is_on);
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0))
-+extern void wifi_teardown_dt(void);
-+extern int wifi_setup_dt(void);
-+#endif /* kernel < 3.14.0 */
-+
-+#endif /* __PLATFORM_AML_S905_SDIO_H__ */
-diff --git a/drivers/staging/rtl8723cs/platform/platform_arm_act_sdio.c b/drivers/staging/rtl8723cs/platform/platform_arm_act_sdio.c
-new file mode 100644
-index 000000000000..ad7b6cfed455
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_arm_act_sdio.c
-@@ -0,0 +1,53 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+/*
-+ * Description:
-+ *	This file can be applied to following platforms:
-+ *    CONFIG_PLATFORM_ACTIONS_ATM703X
-+ */
-+#include <drv_types.h>
-+
-+#ifdef CONFIG_PLATFORM_ACTIONS_ATM705X
-+extern int acts_wifi_init(void);
-+extern void acts_wifi_cleanup(void);
-+#endif
-+
-+/*
-+ * Return:
-+ *	0:	power on successfully
-+ *	others: power on failed
-+ */
-+int platform_wifi_power_on(void)
-+{
-+	int ret = 0;
-+
-+#ifdef CONFIG_PLATFORM_ACTIONS_ATM705X
-+	ret = acts_wifi_init();
-+	if (unlikely(ret < 0)) {
-+		pr_err("%s Failed to register the power control driver.\n", __FUNCTION__);
-+		goto exit;
-+	}
-+#endif
-+
-+exit:
-+	return ret;
-+}
-+
-+void platform_wifi_power_off(void)
-+{
-+#ifdef CONFIG_PLATFORM_ACTIONS_ATM705X
-+	acts_wifi_cleanup();
-+#endif
-+}
-diff --git a/drivers/staging/rtl8723cs/platform/platform_hisilicon_hi3798_sdio.c b/drivers/staging/rtl8723cs/platform/platform_hisilicon_hi3798_sdio.c
-new file mode 100644
-index 000000000000..11a08320ed82
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_hisilicon_hi3798_sdio.c
-@@ -0,0 +1,110 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2017 - 2018 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include <linux/delay.h>		/* mdelay() */
-+#include <mach/hardware.h>		/* __io_address(), readl(), writel() */
-+#include "platform_hisilicon_hi3798_sdio.h"	/* HI_S32() and etc. */
-+
-+typedef enum hi_GPIO_DIR_E {
-+	HI_DIR_OUT = 0,
-+	HI_DIR_IN  = 1,
-+} HI_GPIO_DIR_E;
-+
-+#define RTL_REG_ON_GPIO		(4*8 + 3)
-+
-+#define REG_BASE_CTRL		__io_address(0xf8a20008)
-+
-+int gpio_wlan_reg_on = RTL_REG_ON_GPIO;
-+#if 0
-+module_param(gpio_wlan_reg_on, uint, 0644);
-+MODULE_PARM_DESC(gpio_wlan_reg_on, "wlan reg_on gpio num (default:gpio4_3)");
-+#endif
-+
-+static int hi_gpio_set_value(u32 gpio, u32 value)
-+{
-+	HI_S32 s32Status;
-+
-+	s32Status = HI_DRV_GPIO_SetDirBit(gpio, HI_DIR_OUT);
-+	if (s32Status != HI_SUCCESS) {
-+		pr_err("gpio(%d) HI_DRV_GPIO_SetDirBit HI_DIR_OUT failed\n",
-+			gpio);
-+		return -1;
-+	}
-+
-+	s32Status = HI_DRV_GPIO_WriteBit(gpio, value);
-+	if (s32Status != HI_SUCCESS) {
-+		pr_err("gpio(%d) HI_DRV_GPIO_WriteBit value(%d) failed\n",
-+			gpio, value);
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+static int hisi_wlan_set_carddetect(bool present)
-+{
-+	u32 regval;
-+	u32 mask;
-+
-+
-+#ifndef CONFIG_HISI_SDIO_ID
-+	return;
-+#endif
-+	pr_info("SDIO ID=%d\n", CONFIG_HISI_SDIO_ID);
-+#if (CONFIG_HISI_SDIO_ID == 1)
-+	mask = 1;
-+#elif (CONFIG_HISI_SDIO_ID == 0)
-+	mask = 2;
-+#endif
-+
-+	regval = readl(REG_BASE_CTRL);
-+	if (present) {
-+		pr_info("====== Card detection to detect SDIO card! ======\n");
-+		/* set card_detect low to detect card */
-+		regval |= mask;
-+	} else {
-+		pr_info("====== Card detection to remove SDIO card! ======\n");
-+		/* set card_detect high to remove card */
-+		regval &= ~(mask);
-+	}
-+	writel(regval, REG_BASE_CTRL);
-+
-+	return 0;
-+}
-+
-+/*
-+ * Return:
-+ *	0:	power on successfully
-+ *	others: power on failed
-+ */
-+int platform_wifi_power_on(void)
-+{
-+	int ret = 0;
-+
-+
-+	hi_gpio_set_value(gpio_wlan_reg_on, 1);
-+	mdelay(100);
-+	hisi_wlan_set_carddetect(1);
-+	mdelay(2000);
-+	pr_info("======== set_carddetect delay 2s! ========\n");
-+
-+	return ret;
-+}
-+
-+void platform_wifi_power_off(void)
-+{
-+	hisi_wlan_set_carddetect(0);
-+	mdelay(100);
-+	hi_gpio_set_value(gpio_wlan_reg_on, 0);
-+}
-diff --git a/drivers/staging/rtl8723cs/platform/platform_hisilicon_hi3798_sdio.h b/drivers/staging/rtl8723cs/platform/platform_hisilicon_hi3798_sdio.h
-new file mode 100644
-index 000000000000..1ad42406f014
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_hisilicon_hi3798_sdio.h
-@@ -0,0 +1,28 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2017 - 2018 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __PLATFORM_HISILICON_HI3798_SDIO_H__
-+#define __PLATFORM_HISILICON_HI3798_SDIO_H__
-+
-+typedef unsigned int	HI_U32;
-+
-+typedef int		HI_S32;
-+
-+#define HI_SUCCESS	0
-+#define HI_FAILURE	(-1)
-+
-+extern HI_S32 HI_DRV_GPIO_SetDirBit(HI_U32 u32GpioNo, HI_U32 u32DirBit);
-+extern HI_S32 HI_DRV_GPIO_WriteBit(HI_U32 u32GpioNo, HI_U32 u32BitValue);
-+
-+#endif /* __PLATFORM_HISILICON_HI3798_SDIO_H__ */
-diff --git a/drivers/staging/rtl8723cs/platform/platform_ops.c b/drivers/staging/rtl8723cs/platform/platform_ops.c
-new file mode 100644
-index 000000000000..de08abc00759
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_ops.c
-@@ -0,0 +1,34 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef CONFIG_PLATFORM_OPS
-+/*
-+ * Return:
-+ *	0:	power on successfully
-+ *	others: power on failed
-+ */
-+#include <linux/rfkill.h>
-+extern unsigned int oob_irq;
-+int platform_wifi_power_on(void)
-+{
-+	int ret = 0;
-+
-+	//oob_irq = rockchip_wifi_get_oob_irq();
-+	return ret;
-+}
-+
-+void platform_wifi_power_off(void)
-+{
-+}
-+#endif /* !CONFIG_PLATFORM_OPS */
-diff --git a/drivers/staging/rtl8723cs/platform/platform_ops.h b/drivers/staging/rtl8723cs/platform/platform_ops.h
-new file mode 100644
-index 000000000000..12caf3c853a1
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_ops.h
-@@ -0,0 +1,26 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __PLATFORM_OPS_H__
-+#define __PLATFORM_OPS_H__
-+
-+/*
-+ * Return:
-+ *	0:	power on successfully
-+ *	others: power on failed
-+ */
-+int platform_wifi_power_on(void);
-+void platform_wifi_power_off(void);
-+
-+#endif /* __PLATFORM_OPS_H__ */
-diff --git a/drivers/staging/rtl8723cs/platform/platform_sprd_sdio.c b/drivers/staging/rtl8723cs/platform/platform_sprd_sdio.c
-new file mode 100644
-index 000000000000..34061d05d428
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_sprd_sdio.c
-@@ -0,0 +1,84 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2013 - 2017 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include <drv_types.h>
-+
-+extern void sdhci_bus_scan(void);
-+#ifndef ANDROID_2X
-+extern int sdhci_device_attached(void);
-+#endif
-+
-+/*
-+ * Return:
-+ *	0:	power on successfully
-+ *	others:	power on failed
-+ */
-+int platform_wifi_power_on(void)
-+{
-+	int ret = 0;
-+
-+
-+#ifdef CONFIG_RTL8188E
-+	rtw_wifi_gpio_wlan_ctrl(WLAN_POWER_ON);
-+#endif /* CONFIG_RTL8188E */
-+
-+	/* Pull up pwd pin, make wifi leave power down mode. */
-+	rtw_wifi_gpio_init();
-+	rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_ON);
-+
-+#if (MP_DRIVER == 1) && (defined(CONFIG_RTL8723A) || defined(CONFIG_RTL8723B))
-+	/* Pull up BT reset pin. */
-+	rtw_wifi_gpio_wlan_ctrl(WLAN_BT_PWDN_ON);
-+#endif
-+	rtw_mdelay_os(5);
-+
-+	sdhci_bus_scan();
-+#ifdef CONFIG_RTL8723B
-+	/* YJ,test,130305 */
-+	rtw_mdelay_os(1000);
-+#endif
-+#ifdef ANDROID_2X
-+	rtw_mdelay_os(200);
-+#else /* !ANDROID_2X */
-+	if (1) {
-+		int i = 0;
-+
-+		for (i = 0; i <= 50; i++) {
-+			msleep(10);
-+			if (sdhci_device_attached())
-+				break;
-+			printk("%s delay times:%d\n", __func__, i);
-+		}
-+	}
-+#endif /* !ANDROID_2X */
-+
-+	return ret;
-+}
-+
-+void platform_wifi_power_off(void)
-+{
-+	/* Pull down pwd pin, make wifi enter power down mode. */
-+	rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_OFF);
-+	rtw_mdelay_os(5);
-+	rtw_wifi_gpio_deinit();
-+
-+#ifdef CONFIG_RTL8188E
-+	rtw_wifi_gpio_wlan_ctrl(WLAN_POWER_OFF);
-+#endif /* CONFIG_RTL8188E */
-+
-+#ifdef CONFIG_WOWLAN
-+	if (mmc_host)
-+		mmc_host->pm_flags &= ~MMC_PM_KEEP_POWER;
-+#endif /* CONFIG_WOWLAN */
-+}
-diff --git a/drivers/staging/rtl8723cs/platform/platform_zte_zx296716_sdio.c b/drivers/staging/rtl8723cs/platform/platform_zte_zx296716_sdio.c
-new file mode 100644
-index 000000000000..472d24d8563c
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_zte_zx296716_sdio.c
-@@ -0,0 +1,53 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2018 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#include <linux/printk.h>		/* pr_info(() */
-+#include <linux/delay.h>		/* msleep() */
-+#include "platform_zte_zx296716_sdio.h"	/* sdio_reinit() and etc */
-+
-+
-+/*
-+ * Return:
-+ *	0:	power on successfully
-+ *	others:	power on failed
-+ */
-+int platform_wifi_power_on(void)
-+{
-+	int ret = 0;
-+
-+	pr_info("######%s: disable--1--\n", __func__);
-+	extern_wifi_set_enable(0);
-+	/*msleep(500);*/ /* add in function:extern_wifi_set_enable */
-+	pr_info("######%s: enable--2---\n", __func__);
-+	extern_wifi_set_enable(1);
-+	/*msleep(500);*/
-+	sdio_reinit();
-+
-+	return ret;
-+}
-+
-+void platform_wifi_power_off(void)
-+{
-+	int card_val;
-+
-+	pr_info("######%s:\n", __func__);
-+#ifdef CONFIG_A16T03_BOARD
-+	card_val = sdio_host_is_null();
-+	if (card_val)
-+		remove_card();
-+#endif /* CONFIG_A16T03_BOARD */
-+	extern_wifi_set_enable(0);
-+
-+	/*msleep(500);*/
-+}
-diff --git a/drivers/staging/rtl8723cs/platform/platform_zte_zx296716_sdio.h b/drivers/staging/rtl8723cs/platform/platform_zte_zx296716_sdio.h
-new file mode 100644
-index 000000000000..3a4fba1a5743
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/platform/platform_zte_zx296716_sdio.h
-@@ -0,0 +1,25 @@
-+/******************************************************************************
-+ *
-+ * Copyright(c) 2016 - 2018 Realtek Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of version 2 of the GNU General Public License as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-+ * more details.
-+ *
-+ *****************************************************************************/
-+#ifndef __PLATFORM_ZTE_ZX296716_SDIO_H__
-+#define __PLATFORM_ZTE_ZX296716_SDIO_H__
-+
-+extern void sdio_reinit(void);
-+extern void extern_wifi_set_enable(int val);
-+#ifdef CONFIG_A16T03_BOARD
-+extern int sdio_host_is_null(void);
-+extern void remove_card(void);
-+#endif /* CONFIG_A16T03_BOARD */
-+
-+#endif /* __PLATFORM_ZTE_ZX296716_SDIO_H__ */
-diff --git a/drivers/staging/rtl8723cs/runwpa b/drivers/staging/rtl8723cs/runwpa
-new file mode 100644
-index 000000000000..f825e8bdb123
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/runwpa
-@@ -0,0 +1,20 @@
-+#!/bin/bash
-+
-+if [ "`which iwconfig`" = "" ] ; then 
-+	echo "WARNING:Wireless tool not exist!"
-+	echo "        Please install it!"
-+	exit
-+else
-+	if [ `uname -r | cut -d. -f2` -eq 4 ]; then
-+		wpa_supplicant -D ipw -c wpa1.conf -i wlan0	
-+	else
-+	if [ `iwconfig -v |awk '{print $4}' | head -n 1` -lt  18 ] ; then
-+		wpa_supplicant -D ipw -c wpa1.conf -i wlan0  
-+	else	  
-+		wpa_supplicant -D wext -c wpa1.conf -i wlan0 
-+	fi
-+
-+	fi
-+fi
-+
-+
-diff --git a/drivers/staging/rtl8723cs/wlan0dhcp b/drivers/staging/rtl8723cs/wlan0dhcp
-new file mode 100644
-index 000000000000..60433829cfe6
---- /dev/null
-+++ b/drivers/staging/rtl8723cs/wlan0dhcp
-@@ -0,0 +1,16 @@
-+#!/bin/bash
-+
-+var0=`ps aux|awk '/dhclient wlan0/'|awk '$11!="awk"{print $2}'`
-+
-+kill $var0
-+cp ifcfg-wlan0 /etc/sysconfig/network-scripts/
-+
-+dhclient wlan0
-+
-+var1=`ifconfig wlan0 |awk '/inet/{print $2}'|awk -F: '{print $2}'`
-+
-+
-+rm -f /etc/sysconfig/network-scripts/ifcfg-wlan0
-+
-+echo "get ip: $var1"
-+
--- 
-2.33.0
-
diff --git a/0006-HDMI-Audio-on-RK356x-Quartz64-Model-A.patch b/0006-HDMI-Audio-on-RK356x-Quartz64-Model-A.patch
deleted file mode 100644
index f7b70f8..0000000
--- a/0006-HDMI-Audio-on-RK356x-Quartz64-Model-A.patch
+++ /dev/null
@@ -1,308 +0,0 @@
-From patchwork Fri Nov 26 12:27:17 2021
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
-X-Patchwork-Id: 12640681
-Return-Path: 
- <linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org>
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-From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
-To: Rob Herring <robh+dt@kernel.org>,
-	Heiko Stuebner <heiko@sntech.de>
-Cc: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>,
- Michael Riesch <michael.riesch@wolfvision.net>, devicetree@vger.kernel.org,
- linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org,
- linux-kernel@vger.kernel.org
-Subject: [PATCH v2 1/2] arm64: dts: rockchip: rk356x: Add HDMI audio nodes
-Date: Fri, 26 Nov 2021 13:27:17 +0100
-Message-Id: <20211126122718.631506-2-frattaroli.nicolas@gmail.com>
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-List-Id: Upstream kernel work for Rockchip platforms
- <linux-rockchip.lists.infradead.org>
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-
-This adds the i2s0 node and an hdmi-sound sound device to the
-rk356x device tree. On the rk356[68], the i2s0 controller is
-connected to HDMI audio.
-
-Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
-Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
----
-
-Changes in v2:
- - reordered nodes to conform
- - reordered properties to conform
- - add Michael Riesch's Tested-by
-
- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 33 ++++++++++++++++++++++++
- 1 file changed, 33 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-index 3c09cf6d4c37..aafb622dfa83 100644
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -174,6 +174,22 @@ scmi_clk: protocol@14 {
- 		};
- 	};
- 
-+	hdmi_sound: hdmi-sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "HDMI";
-+		simple-audio-card,format = "i2s";
-+		simple-audio-card,mclk-fs = <256>;
-+		status = "disabled";
-+
-+		simple-audio-card,codec {
-+			sound-dai = <&hdmi>;
-+		};
-+
-+		simple-audio-card,cpu {
-+			sound-dai = <&i2s0_8ch>;
-+		};
-+	};
-+
- 	pmu {
- 		compatible = "arm,cortex-a55-pmu";
- 		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
-@@ -789,6 +805,23 @@ spdif: spdif@fe460000 {
- 		status = "disabled";
- 	};
- 
-+	i2s0_8ch: i2s@fe400000 {
-+		compatible = "rockchip,rk3568-i2s-tdm";
-+		reg = <0x0 0xfe400000 0x0 0x1000>;
-+		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-+		assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
-+		assigned-clock-rates = <1188000000>, <1188000000>;
-+		clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
-+		clock-names = "mclk_tx", "mclk_rx", "hclk";
-+		dmas = <&dmac1 0>;
-+		dma-names = "tx";
-+		resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
-+		reset-names = "tx-m", "rx-m";
-+		rockchip,grf = <&grf>;
-+		#sound-dai-cells = <0>;
-+		status = "disabled";
-+	};
-+
- 	i2s1_8ch: i2s@fe410000 {
- 		compatible = "rockchip,rk3568-i2s-tdm";
- 		reg = <0x0 0xfe410000 0x0 0x1000>;
-
-From patchwork Fri Nov 26 12:27:18 2021
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- Fri, 26 Nov 2021 04:27:44 -0800 (PST)
-From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
-To: Rob Herring <robh+dt@kernel.org>,
-	Heiko Stuebner <heiko@sntech.de>
-Cc: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>,
- devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
- linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
-Subject: [PATCH v2 2/2] arm64: dts: rockchip: Enable HDMI audio on Quartz64 A
-Date: Fri, 26 Nov 2021 13:27:18 +0100
-Message-Id: <20211126122718.631506-3-frattaroli.nicolas@gmail.com>
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-List-Id: Upstream kernel work for Rockchip platforms
- <linux-rockchip.lists.infradead.org>
-List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-rockchip>,
- <mailto:linux-rockchip-request@lists.infradead.org?subject=unsubscribe>
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- linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org
-
-This enables the i2s0 controller and the hdmi-sound node on
-the PINE64 Quartz64 Model A single-board computer.
-
-Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
----
- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
-index a4453c82b03d..0598510dce58 100644
---- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
-@@ -215,6 +215,10 @@ &hdmi_in_vp0 {
- 	status = "okay";
- };
- 
-+&hdmi_sound {
-+	status = "okay";
-+};
-+
- &gpu {
- 	mali-supply = <&vdd_gpu>;
- 	status = "okay";
-@@ -444,6 +448,10 @@ regulator-state-mem {
- 	};
- };
- 
-+&i2s0_8ch {
-+	status = "okay";
-+};
-+
- &i2s1_8ch {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&i2s1m0_sclktx
diff --git a/0006-gpu-drm-add-new-display-resolution-2560x1440.patch b/0006-gpu-drm-add-new-display-resolution-2560x1440.patch
deleted file mode 100644
index 514f0ad..0000000
--- a/0006-gpu-drm-add-new-display-resolution-2560x1440.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From ce9ad5ce77cb92963b1ce2cc85d2c024ccec7dae Mon Sep 17 00:00:00 2001
-From: Dongjin Kim <tobetter@gmail.com>
-Date: Thu, 10 Sep 2020 11:01:33 +0900
-Subject: [PATCH] ODROID-COMMON: gpu/drm: add new display resolution 2560x1440
-
-Signed-off-by: Joy Cho <joy.cho@hardkernel.com>
-Signed-off-by: Dongjin Kim <tobetter@gmail.com>
----
- drivers/gpu/drm/meson/meson_vclk.c | 18 ++++++++++++++++++
- drivers/gpu/drm/meson/meson_venc.c |  5 +++--
- 2 files changed, 21 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
-index 0eb86943a3588..e734d1be553d2 100644
---- a/drivers/gpu/drm/meson/meson_vclk.c
-+++ b/drivers/gpu/drm/meson/meson_vclk.c
-@@ -357,6 +357,8 @@ enum {
- 	MESON_VCLK_HDMI_594000,
- /* 2970 /1 /1 /1 /5 /1  => /1 /2 */
- 	MESON_VCLK_HDMI_594000_YUV420,
-+/* 4830 /2 /1 /2 /5 /1  => /1 /1 */
-+	MESON_VCLK_HDMI_241500,
- };
- 
- struct meson_vclk_params {
-@@ -467,6 +469,18 @@ struct meson_vclk_params {
- 		.vid_pll_div = VID_PLL_DIV_5,
- 		.vclk_div = 1,
- 	},
-+	[MESON_VCLK_HDMI_241500] = {
-+		.pll_freq = 4830000,
-+		.phy_freq = 2415000,
-+		.venc_freq = 241500,
-+		.vclk_freq = 241500,
-+		.pixel_freq = 241500,
-+		.pll_od1 = 2,
-+		.pll_od2 = 1,
-+		.pll_od3 = 2,
-+		.vid_pll_div = VID_PLL_DIV_5,
-+		.vclk_div = 1,
-+	},
- 	{ /* sentinel */ },
- };
- 
-@@ -873,6 +887,10 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
- 			m = 0xf7;
- 			frac = vic_alternate_clock ? 0x8148 : 0x10000;
- 			break;
-+		case 4830000:
-+			m = 0xc9;
-+			frac = 0xd560;
-+			break;
- 		}
- 
- 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
-diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
-index f93c725b6f02d..ebe4f2a92fe06 100644
---- a/drivers/gpu/drm/meson/meson_venc.c
-+++ b/drivers/gpu/drm/meson/meson_venc.c
-@@ -866,10 +866,11 @@ meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode)
- 			    DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))
- 		return MODE_BAD;
- 
--	if (mode->hdisplay < 640 || mode->hdisplay > 1920)
-+	/* support higher resolution than 1920x1080 */
-+	if (mode->hdisplay < 640 || mode->hdisplay > 2560)
- 		return MODE_BAD_HVALUE;
- 
--	if (mode->vdisplay < 480 || mode->vdisplay > 1200)
-+	if (mode->vdisplay < 480 || mode->vdisplay > 1600)
- 		return MODE_BAD_VVALUE;
- 
- 	return MODE_OK;
diff --git a/0006-pinetab-accelerometer.patch b/0006-pinetab-accelerometer.patch
deleted file mode 100644
index ca8a900..0000000
--- a/0006-pinetab-accelerometer.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
-index a72c2ec8c..b3a7bef13 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
-@@ -227,7 +227,15 @@ &i2c0_pins {
- &i2c1 {
- 	status = "okay";
- 
--	/* TODO: add Bochs BMA223 accelerometer here */
-+	bma223@18 {
-+		compatible = "bosch,bma223", "bosch,bma222e";
-+		reg = <0x18>;
-+		interrupt-parent = <&pio>;
-+		interrupts = <7 5 IRQ_TYPE_LEVEL_HIGH>; /* PH5 */
-+		mount-matrix = "0", "-1", "0",
-+			       "-1", "0", "0",
-+			       "0", "0", "-1";
-+	};
- };
- 
- &lradc {
diff --git a/0007-arm64-dts-rockchip-Add-Firefly-Station-p1-support.patch b/0007-arm64-dts-rockchip-Add-Firefly-Station-p1-support.patch
deleted file mode 100644
index 1809e6b..0000000
--- a/0007-arm64-dts-rockchip-Add-Firefly-Station-p1-support.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 5d4286766eb4211aa010ed0ee2be43ead77441c0 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Sun, 14 Nov 2021 23:41:48 +0100
-Subject: [PATCH] arm64: dts: rockchip: Add Firefly Station p1 support
-
-Signed-off-by: Dan Johansen <strit@manjaro.org>
----
- arch/arm64/boot/dts/rockchip/Makefile              |  1 +
- arch/arm64/boot/dts/rockchip/rk3399-station-p1.dts | 14 ++++++++++++++
- 2 files changed, 15 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-station-p1.dts
-
-diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
-index 479906f3ad7b..e7b8bd1a2588 100644
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -55,6 +55,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-station-p1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-station-p1.dts b/arch/arm64/boot/dts/rockchip/rk3399-station-p1.dts
-new file mode 100644
-index 000000000000..16d46f30e222
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-station-p1.dts
-@@ -0,0 +1,14 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
-+ * Copyright (c) 2019 Radxa Limited
-+ * Copyright (c) 2019 Amarula Solutions(India)
-+ */
-+
-+/dts-v1/;
-+#include "rk3399-rock-pi-4.dtsi"
-+
-+/ {
-+	model = "Firefly Station P1";
-+	compatible = "radxa,rockpi4c", "radxa,rockpi4", "rockchip,rk3399";
-+}; 
--- 
-2.33.0
-
diff --git a/0007-enable-jack-detection-pinetab.patch b/0007-enable-jack-detection-pinetab.patch
deleted file mode 100644
index 873d74c..0000000
--- a/0007-enable-jack-detection-pinetab.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 7dd3866d9c2bef4bb73a781861aeeec595510509 Mon Sep 17 00:00:00 2001
-From: Arnaud Ferraris <arnaud.ferraris@collabora.com>
-Date: Fri, 3 Apr 2020 17:13:55 +0200
-Subject: [PATCH] arm64: dts: allwinner: pinetab: enable jack detection
-
----
- arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
-index a87790df9..a72c2ec8c 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
-@@ -117,11 +117,13 @@ wifi_pwrseq: wifi_pwrseq {
- };
- 
- &codec {
-+	allwinner,inverted-jack-detection;
- 	status = "okay";
- };
- 
- &codec_analog {
- 	cpvdd-supply = <&reg_eldo1>;
-+	allwinner,internal-bias-resistor;
- 	status = "okay";
- };
- 
-@@ -448,6 +450,7 @@ &reg_rtc_ldo {
- 
- &sound {
- 	status = "okay";
-+	simple-audio-card,name = "PineTab";
- 	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
- 	simple-audio-card,widgets = "Microphone", "Internal Microphone Left",
- 				    "Microphone", "Internal Microphone Right",
--- 
-2.28.0
-
diff --git a/0007-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch b/0007-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch
deleted file mode 100644
index 07c67f7..0000000
--- a/0007-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch
+++ /dev/null
@@ -1,681 +0,0 @@
-From 79c20c9bb7fd5da37c33b8d043b786ca510de161 Mon Sep 17 00:00:00 2001
-From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
-Date: Fri, 9 Oct 2020 14:39:29 +0800
-Subject: [PATCH] phy: rockchip: add naneng combo phy for RK3568
-
-This patch implements a combo phy driver for Rockchip SoCs
-with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
-sata-phy or sgmii-phy.
-
-Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
-Change-Id: I86726e7eee643ea4cb3fadc56b0ee729903afc4f
-
-Squash all commits from downstream kernel into this patch.
-Signed-off-by: Peter Geis <pgwipeout@gmail.com>
----
- drivers/phy/rockchip/Kconfig                  |   8 +
- drivers/phy/rockchip/Makefile                 |   1 +
- .../rockchip/phy-rockchip-naneng-combphy.c    | 620 ++++++++++++++++++
- 3 files changed, 629 insertions(+)
- create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-
-diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
-index e812adad7242..9022e395c056 100644
---- a/drivers/phy/rockchip/Kconfig
-+++ b/drivers/phy/rockchip/Kconfig
-@@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
- 	  Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
- 	  Innosilicon IP block.
- 
-+config PHY_ROCKCHIP_NANENG_COMBO_PHY
-+	tristate "Rockchip NANENG COMBO PHY Driver"
-+	depends on ARCH_ROCKCHIP && OF
-+	select GENERIC_PHY
-+	help
-+	  Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
-+	  combo PHY with NaNeng IP block.
-+
- config PHY_ROCKCHIP_PCIE
- 	tristate "Rockchip PCIe PHY Driver"
- 	depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
-diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
-index f0eec212b2aa..a5041efb5b8f 100644
---- a/drivers/phy/rockchip/Makefile
-+++ b/drivers/phy/rockchip/Makefile
-@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY)	+= phy-rockchip-inno-csidphy.o
- obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
- obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)	+= phy-rockchip-inno-hdmi.o
- obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
-+obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY)	+= phy-rockchip-naneng-combphy.o
- obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
- obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
- obj-$(CONFIG_PHY_ROCKCHIP_USB)		+= phy-rockchip-usb.o
-diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-new file mode 100644
-index 000000000000..d28fe5728e7a
---- /dev/null
-+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
-@@ -0,0 +1,620 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Rockchip PIPE USB3.0 PCIE SATA combphy driver
-+ *
-+ * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/module.h>
-+#include <linux/of_device.h>
-+#include <linux/phy/phy.h>
-+#include <linux/regmap.h>
-+#include <linux/reset.h>
-+#include <dt-bindings/phy/phy.h>
-+
-+#define BIT_WRITEABLE_SHIFT		16
-+
-+struct rockchip_combphy_priv;
-+
-+struct combphy_reg {
-+	u16 offset;
-+	u16 bitend;
-+	u16 bitstart;
-+	u16 disable;
-+	u16 enable;
-+};
-+
-+struct rockchip_combphy_grfcfg {
-+	struct combphy_reg pcie_mode_set;
-+	struct combphy_reg usb_mode_set;
-+	struct combphy_reg sgmii_mode_set;
-+	struct combphy_reg qsgmii_mode_set;
-+	struct combphy_reg pipe_rxterm_set;
-+	struct combphy_reg pipe_txelec_set;
-+	struct combphy_reg pipe_txcomp_set;
-+	struct combphy_reg pipe_clk_25m;
-+	struct combphy_reg pipe_clk_100m;
-+	struct combphy_reg pipe_phymode_sel;
-+	struct combphy_reg pipe_rate_sel;
-+	struct combphy_reg pipe_rxterm_sel;
-+	struct combphy_reg pipe_txelec_sel;
-+	struct combphy_reg pipe_txcomp_sel;
-+	struct combphy_reg pipe_clk_ext;
-+	struct combphy_reg pipe_sel_usb;
-+	struct combphy_reg pipe_sel_qsgmii;
-+	struct combphy_reg pipe_phy_status;
-+	struct combphy_reg con0_for_pcie;
-+	struct combphy_reg con1_for_pcie;
-+	struct combphy_reg con2_for_pcie;
-+	struct combphy_reg con3_for_pcie;
-+	struct combphy_reg con0_for_sata;
-+	struct combphy_reg con1_for_sata;
-+	struct combphy_reg con2_for_sata;
-+	struct combphy_reg con3_for_sata;
-+	struct combphy_reg pipe_con0_for_sata;
-+	struct combphy_reg pipe_sgmii_mac_sel;
-+	struct combphy_reg pipe_xpcs_phy_ready;
-+	struct combphy_reg u3otg0_port_en;
-+	struct combphy_reg u3otg1_port_en;
-+};
-+
-+struct rockchip_combphy_cfg {
-+	const int num_clks;
-+	const struct clk_bulk_data *clks;
-+	const struct rockchip_combphy_grfcfg *grfcfg;
-+	int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
-+};
-+
-+struct rockchip_combphy_priv {
-+	u8 mode;
-+	void __iomem *mmio;
-+	int num_clks;
-+	struct clk_bulk_data *clks;
-+	struct device *dev;
-+	struct regmap *pipe_grf;
-+	struct regmap *phy_grf;
-+	struct phy *phy;
-+	struct reset_control *apb_rst;
-+	struct reset_control *phy_rst;
-+	const struct rockchip_combphy_cfg *cfg;
-+};
-+
-+static inline bool param_read(struct regmap *base,
-+			      const struct combphy_reg *reg, u32 val)
-+{
-+	int ret;
-+	u32 mask, orig, tmp;
-+
-+	ret = regmap_read(base, reg->offset, &orig);
-+	if (ret)
-+		return false;
-+
-+	mask = GENMASK(reg->bitend, reg->bitstart);
-+	tmp = (orig & mask) >> reg->bitstart;
-+
-+	return tmp == val;
-+}
-+
-+static int param_write(struct regmap *base,
-+		       const struct combphy_reg *reg, bool en)
-+{
-+	u32 val, mask, tmp;
-+
-+	tmp = en ? reg->enable : reg->disable;
-+	mask = GENMASK(reg->bitend, reg->bitstart);
-+	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
-+
-+	return regmap_write(base, reg->offset, val);
-+}
-+
-+static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
-+{
-+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
-+	u32 mask, val;
-+
-+	mask = GENMASK(cfg->pipe_phy_status.bitend,
-+		       cfg->pipe_phy_status.bitstart);
-+
-+	regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
-+	val = (val & mask) >> cfg->pipe_phy_status.bitstart;
-+
-+	return val;
-+}
-+
-+static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv)
-+{
-+	int ret = 0;
-+
-+	if (priv->cfg->combphy_cfg) {
-+		ret = priv->cfg->combphy_cfg(priv);
-+		if (ret) {
-+			dev_err(priv->dev, "failed to init phy for pcie\n");
-+			return ret;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv)
-+{
-+	int ret = 0;
-+
-+	if (priv->cfg->combphy_cfg) {
-+		ret = priv->cfg->combphy_cfg(priv);
-+		if (ret) {
-+			dev_err(priv->dev, "failed to init phy for usb3\n");
-+			return ret;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv)
-+{
-+	int ret = 0;
-+
-+	if (priv->cfg->combphy_cfg) {
-+		ret = priv->cfg->combphy_cfg(priv);
-+		if (ret) {
-+			dev_err(priv->dev, "failed to init phy for sata\n");
-+			return ret;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv)
-+{
-+	int ret = 0;
-+
-+	if (priv->cfg->combphy_cfg) {
-+		ret = priv->cfg->combphy_cfg(priv);
-+		if (ret) {
-+			dev_err(priv->dev, "failed to init phy for sgmii\n");
-+			return ret;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv)
-+{
-+	switch (priv->mode) {
-+	case PHY_TYPE_PCIE:
-+		rockchip_combphy_pcie_init(priv);
-+		break;
-+	case PHY_TYPE_USB3:
-+		rockchip_combphy_usb3_init(priv);
-+		break;
-+	case PHY_TYPE_SATA:
-+		rockchip_combphy_sata_init(priv);
-+		break;
-+	case PHY_TYPE_SGMII:
-+	case PHY_TYPE_QSGMII:
-+		return rockchip_combphy_sgmii_init(priv);
-+	default:
-+		dev_err(priv->dev, "incompatible PHY type\n");
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int rockchip_combphy_init(struct phy *phy)
-+{
-+	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
-+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
-+	u32 val;
-+	int ret;
-+
-+	ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
-+	if (ret) {
-+		dev_err(priv->dev, "failed to enable clks\n");
-+		return ret;
-+	}
-+
-+	ret = rockchip_combphy_set_mode(priv);
-+	if (ret)
-+		goto err_clk;
-+
-+	ret = reset_control_deassert(priv->phy_rst);
-+	if (ret)
-+		goto err_clk;
-+
-+	if (priv->mode == PHY_TYPE_USB3) {
-+		ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
-+						priv, val,
-+						val == cfg->pipe_phy_status.enable,
-+						10, 1000);
-+		if (ret)
-+			dev_warn(priv->dev, "wait phy status ready timeout\n");
-+	}
-+
-+	return 0;
-+
-+err_clk:
-+	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
-+
-+	return ret;
-+}
-+
-+static int rockchip_combphy_exit(struct phy *phy)
-+{
-+	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
-+
-+	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
-+	reset_control_assert(priv->phy_rst);
-+
-+	return 0;
-+}
-+
-+static const struct phy_ops rochchip_combphy_ops = {
-+	.init = rockchip_combphy_init,
-+	.exit = rockchip_combphy_exit,
-+	.owner = THIS_MODULE,
-+};
-+
-+static struct phy *rockchip_combphy_xlate(struct device *dev,
-+					  struct of_phandle_args *args)
-+{
-+	struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
-+
-+	if (args->args_count != 1) {
-+		dev_err(dev, "invalid number of arguments\n");
-+		return ERR_PTR(-EINVAL);
-+	}
-+
-+	if (priv->mode != PHY_NONE && priv->mode != args->args[0])
-+		dev_warn(dev, "phy type select %d overwriting type %d\n",
-+			 args->args[0], priv->mode);
-+
-+	priv->mode = args->args[0];
-+
-+	return priv->phy;
-+}
-+
-+static int rockchip_combphy_parse_dt(struct device *dev,
-+				     struct rockchip_combphy_priv *priv)
-+{
-+	const struct rockchip_combphy_cfg *phy_cfg = priv->cfg;
-+	int ret, mac_id;
-+
-+	ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
-+	if (ret == -EPROBE_DEFER)
-+		return -EPROBE_DEFER;
-+	if (ret)
-+		priv->num_clks = 0;
-+
-+	priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
-+							 "rockchip,pipe-grf");
-+	if (IS_ERR(priv->pipe_grf)) {
-+		dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
-+		return PTR_ERR(priv->pipe_grf);
-+	}
-+
-+	priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
-+							"rockchip,pipe-phy-grf");
-+	if (IS_ERR(priv->phy_grf)) {
-+		dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
-+		return PTR_ERR(priv->phy_grf);
-+	}
-+
-+	if (device_property_present(dev, "rockchip,dis-u3otg0-port"))
-+		param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en,
-+			    false);
-+	else if (device_property_present(dev, "rockchip,dis-u3otg1-port"))
-+		param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en,
-+			    false);
-+
-+	if (!device_property_read_u32(dev, "rockchip,sgmii-mac-sel", &mac_id) &&
-+	    (mac_id > 0))
-+		param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel,
-+			    true);
-+
-+	priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb");
-+	if (IS_ERR(priv->apb_rst)) {
-+		ret = PTR_ERR(priv->apb_rst);
-+
-+		if (ret != -EPROBE_DEFER)
-+			dev_warn(dev, "failed to get apb reset\n");
-+
-+		return ret;
-+	}
-+
-+	priv->phy_rst = devm_reset_control_get_optional(dev, "combphy");
-+	if (IS_ERR(priv->phy_rst)) {
-+		ret = PTR_ERR(priv->phy_rst);
-+
-+		if (ret != -EPROBE_DEFER)
-+			dev_warn(dev, "failed to get phy reset\n");
-+
-+		return ret;
-+	}
-+
-+	return reset_control_assert(priv->phy_rst);
-+}
-+
-+static int rockchip_combphy_probe(struct platform_device *pdev)
-+{
-+	struct phy_provider *phy_provider;
-+	struct device *dev = &pdev->dev;
-+	struct rockchip_combphy_priv *priv;
-+	const struct rockchip_combphy_cfg *phy_cfg;
-+	struct resource *res;
-+	int ret;
-+
-+	phy_cfg = of_device_get_match_data(dev);
-+	if (!phy_cfg) {
-+		dev_err(dev, "No OF match data provided\n");
-+		return -EINVAL;
-+	}
-+
-+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	priv->mmio = devm_ioremap_resource(dev, res);
-+	if (IS_ERR(priv->mmio)) {
-+		ret = PTR_ERR(priv->mmio);
-+		return ret;
-+	}
-+
-+	priv->num_clks = phy_cfg->num_clks;
-+
-+	priv->clks = devm_kmemdup(dev, phy_cfg->clks,
-+				  phy_cfg->num_clks * sizeof(struct clk_bulk_data),
-+				  GFP_KERNEL);
-+
-+	if (!priv->clks)
-+		return -ENOMEM;
-+
-+	priv->dev = dev;
-+	priv->mode = PHY_NONE;
-+	priv->cfg = phy_cfg;
-+
-+	ret = rockchip_combphy_parse_dt(dev, priv);
-+	if (ret)
-+		return ret;
-+
-+	priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
-+	if (IS_ERR(priv->phy)) {
-+		dev_err(dev, "failed to create combphy\n");
-+		return PTR_ERR(priv->phy);
-+	}
-+
-+	dev_set_drvdata(dev, priv);
-+	phy_set_drvdata(priv->phy, priv);
-+
-+	phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
-+
-+	return PTR_ERR_OR_ZERO(phy_provider);
-+}
-+
-+static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
-+{
-+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
-+	struct clk *refclk = NULL;
-+	unsigned long rate;
-+	int i;
-+	u32 val;
-+
-+	/* Configure PHY reference clock frequency */
-+	for (i = 0; i < priv->num_clks; i++) {
-+		if (!strncmp(priv->clks[i].id, "refclk", 6)) {
-+			refclk = priv->clks[i].clk;
-+			break;
-+		}
-+	}
-+
-+	if (!refclk) {
-+		dev_err(priv->dev, "No refclk found\n");
-+		return -EINVAL;
-+	}
-+
-+	switch (priv->mode) {
-+	case PHY_TYPE_PCIE:
-+		/* Set SSC downward spread spectrum */
-+		val = readl(priv->mmio + (0x1f << 2));
-+		val &= ~GENMASK(5, 4);
-+		val |= 0x01 << 4;
-+		writel(val, priv->mmio + 0x7c);
-+
-+		param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
-+		param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
-+		param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
-+		param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
-+		break;
-+	case PHY_TYPE_USB3:
-+		/* Set SSC downward spread spectrum */
-+		val = readl(priv->mmio + (0x1f << 2));
-+		val &= ~GENMASK(5, 4);
-+		val |= 0x01 << 4;
-+		writel(val, priv->mmio + 0x7c);
-+
-+		/* Enable adaptive CTLE for USB3.0 Rx */
-+		val = readl(priv->mmio + (0x0e << 2));
-+		val &= ~GENMASK(0, 0);
-+		val |= 0x01;
-+		writel(val, priv->mmio + (0x0e << 2));
-+
-+		param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
-+		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
-+		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
-+		param_write(priv->phy_grf, &cfg->usb_mode_set, true);
-+		break;
-+	case PHY_TYPE_SATA:
-+		writel(0x41, priv->mmio + 0x38);
-+		writel(0x8F, priv->mmio + 0x18);
-+		param_write(priv->phy_grf, &cfg->con0_for_sata, true);
-+		param_write(priv->phy_grf, &cfg->con1_for_sata, true);
-+		param_write(priv->phy_grf, &cfg->con2_for_sata, true);
-+		param_write(priv->phy_grf, &cfg->con3_for_sata, true);
-+		param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
-+		break;
-+	case PHY_TYPE_SGMII:
-+		param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
-+		param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
-+		param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
-+		param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
-+		break;
-+	case PHY_TYPE_QSGMII:
-+		param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
-+		param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
-+		param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
-+		param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
-+		param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
-+		break;
-+	default:
-+		dev_err(priv->dev, "incompatible PHY type\n");
-+		return -EINVAL;
-+	}
-+
-+	rate = clk_get_rate(refclk);
-+
-+	switch (rate) {
-+	case 24000000:
-+		if (priv->mode == PHY_TYPE_USB3) {
-+			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
-+			val = readl(priv->mmio + (0x0e << 2));
-+			val &= ~GENMASK(7, 6);
-+			val |= 0x01 << 6;
-+			writel(val, priv->mmio + (0x0e << 2));
-+
-+			val = readl(priv->mmio + (0x0f << 2));
-+			val &= ~GENMASK(7, 0);
-+			val |= 0x5f;
-+			writel(val, priv->mmio + (0x0f << 2));
-+		}
-+		break;
-+	case 25000000:
-+		param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
-+		break;
-+	case 100000000:
-+		param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
-+		if (priv->mode == PHY_TYPE_PCIE) {
-+			/* PLL KVCO tuning fine */
-+			val = readl(priv->mmio + (0x20 << 2));
-+			val &= ~(0x7 << 2);
-+			val |= 0x2 << 2;
-+			writel(val, priv->mmio + (0x20 << 2));
-+
-+			/* Enable controlling random jitter, aka RMJ */
-+			writel(0x4, priv->mmio + (0xb << 2));
-+
-+			val = readl(priv->mmio + (0x5 << 2));
-+			val &= ~(0x3 << 6);
-+			val |= 0x1 << 6;
-+			writel(val, priv->mmio + (0x5 << 2));
-+
-+			writel(0x32, priv->mmio + (0x11 << 2));
-+			writel(0xf0, priv->mmio + (0xa << 2));
-+
-+		}
-+		break;
-+	default:
-+		dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
-+		return -EINVAL;
-+	}
-+
-+	if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
-+		param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
-+		if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
-+			val = readl(priv->mmio + (0xc << 2));
-+			val |= 0x3 << 4 | 0x1 << 7;
-+			writel(val, priv->mmio + (0xc << 2));
-+
-+			val = readl(priv->mmio + (0xd << 2));
-+			val |= 0x1;
-+			writel(val, priv->mmio + (0xd << 2));
-+		}
-+	}
-+
-+	if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
-+		val = readl(priv->mmio + (0x7 << 2));
-+		val |= BIT(4);
-+		writel(val, priv->mmio + (0x7 << 2));
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
-+	/* pipe-phy-grf */
-+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
-+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
-+	.sgmii_mode_set		= { 0x0000, 5, 0, 0x00, 0x01 },
-+	.qsgmii_mode_set	= { 0x0000, 5, 0, 0x00, 0x21 },
-+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
-+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
-+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
-+	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
-+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
-+	.pipe_phymode_sel	= { 0x0008, 1, 1, 0x00, 0x01 },
-+	.pipe_rate_sel		= { 0x0008, 2, 2, 0x00, 0x01 },
-+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
-+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
-+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
-+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
-+	.pipe_sel_usb		= { 0x000c, 14, 13, 0x00, 0x01 },
-+	.pipe_sel_qsgmii	= { 0x000c, 15, 13, 0x00, 0x07 },
-+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
-+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x1000 },
-+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x0000 },
-+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x0101 },
-+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
-+	.con0_for_sata		= { 0x0000, 15, 0, 0x00, 0x0119 },
-+	.con1_for_sata		= { 0x0004, 15, 0, 0x00, 0x0040 },
-+	.con2_for_sata		= { 0x0008, 15, 0, 0x00, 0x80c3 },
-+	.con3_for_sata		= { 0x000c, 15, 0, 0x00, 0x4407 },
-+	/* pipe-grf */
-+	.pipe_con0_for_sata	= { 0x0000, 15, 0, 0x00, 0x2220 },
-+	.pipe_sgmii_mac_sel	= { 0x0040, 1, 1, 0x00, 0x01 },
-+	.pipe_xpcs_phy_ready	= { 0x0040, 2, 2, 0x00, 0x01 },
-+	.u3otg0_port_en		= { 0x0104, 15, 0, 0x0181, 0x1100 },
-+	.u3otg1_port_en		= { 0x0144, 15, 0, 0x0181, 0x1100 },
-+};
-+
-+static const struct clk_bulk_data rk3568_clks[] = {
-+	{ .id = "refclk" },
-+	{ .id = "apbclk" },
-+	{ .id = "pipe_clk" },
-+};
-+
-+static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
-+	.num_clks	= ARRAY_SIZE(rk3568_clks),
-+	.clks		= rk3568_clks,
-+	.grfcfg		= &rk3568_combphy_grfcfgs,
-+	.combphy_cfg	= rk3568_combphy_cfg,
-+};
-+
-+static const struct of_device_id rockchip_combphy_of_match[] = {
-+	{
-+		.compatible = "rockchip,rk3568-naneng-combphy",
-+		.data = &rk3568_combphy_cfgs,
-+	},
-+	{ },
-+};
-+MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
-+
-+static struct platform_driver rockchip_combphy_driver = {
-+	.probe	= rockchip_combphy_probe,
-+	.driver = {
-+		.name = "naneng-combphy",
-+		.of_match_table = rockchip_combphy_of_match,
-+	},
-+};
-+module_platform_driver(rockchip_combphy_driver);
-+
-+MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
-+MODULE_LICENSE("GPL v2");
--- 
-GitLab
-
diff --git a/0007-pinetab-accelerometer.patch b/0007-pinetab-accelerometer.patch
deleted file mode 100644
index ca8a900..0000000
--- a/0007-pinetab-accelerometer.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
-index a72c2ec8c..b3a7bef13 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
-@@ -227,7 +227,15 @@ &i2c0_pins {
- &i2c1 {
- 	status = "okay";
- 
--	/* TODO: add Bochs BMA223 accelerometer here */
-+	bma223@18 {
-+		compatible = "bosch,bma223", "bosch,bma222e";
-+		reg = <0x18>;
-+		interrupt-parent = <&pio>;
-+		interrupts = <7 5 IRQ_TYPE_LEVEL_HIGH>; /* PH5 */
-+		mount-matrix = "0", "-1", "0",
-+			       "-1", "0", "0",
-+			       "0", "0", "-1";
-+	};
- };
- 
- &lradc {
diff --git a/0008-arm64-dts-rockchip-enable-sdmmc1-on-Quartz64-Model-A.patch b/0008-arm64-dts-rockchip-enable-sdmmc1-on-Quartz64-Model-A.patch
deleted file mode 100644
index 741f432..0000000
--- a/0008-arm64-dts-rockchip-enable-sdmmc1-on-Quartz64-Model-A.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-diff -up linux-5.16/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts.81~ linux-5.16/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
---- linux-5.16/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts.81~	2022-01-10 12:19:39.166385145 +0100
-+++ linux-5.16/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts	2022-01-10 12:20:08.665497777 +0100
-@@ -91,6 +91,18 @@
- 		};
- 	};
- 
-+	sdio_pwrseq: sdio-pwrseq {
-+		status = "okay";
-+		compatible = "mmc-pwrseq-simple";
-+		clocks = <&rk817 1>;
-+		clock-names = "ext_clock";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&wifi_enable_h>;
-+		reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
-+		post-power-on-delay-ms = <100>;
-+		power-off-delay-us = <5000000>;
-+	};
-+
- 	vcc12v_dcin: vcc12v_dcin {
- 		compatible = "regulator-fixed";
- 		regulator-name = "vcc12v_dcin";
-@@ -163,6 +175,17 @@
- 		regulator-max-microvolt = <4400000>;
- 		vin-supply = <&vbus>;
- 	};
-+
-+	/* sourced from vcc_sys, sdio module operates internally at 3.3v */
-+	vcc_wl: vcc_wl {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc_wl";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vcc_sys>;
-+	};
- };
- 
- &cpu0 {
-@@ -516,6 +539,12 @@
- 		};
- 	};
- 
-+	sdio-pwrseq {
-+		wifi_enable_h: wifi-enable-h {
-+			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
- 	usb2 {
- 		vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
- 			rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
-@@ -554,6 +583,22 @@
- 	status = "okay";
- };
- 
-+&sdmmc1 {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	cap-sdio-irq;
-+	disable-wp;
-+	keep-power-in-suspend;
-+	mmc-pwrseq = <&sdio_pwrseq>;
-+	non-removable;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
-+	sd-uhs-sdr104;
-+	vmmc-supply = <&vcc_wl>;
-+	vqmmc-supply = <&vcc_1v8>;
-+	status = "okay";
-+};
-+
- &tsadc {
- 	/* tshut mode 0:CRU 1:GPIO */
- 	rockchip,hw-tshut-mode = <1>;
diff --git a/0008-enable-jack-detection-pinetab.patch b/0008-enable-jack-detection-pinetab.patch
deleted file mode 100644
index 873d74c..0000000
--- a/0008-enable-jack-detection-pinetab.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 7dd3866d9c2bef4bb73a781861aeeec595510509 Mon Sep 17 00:00:00 2001
-From: Arnaud Ferraris <arnaud.ferraris@collabora.com>
-Date: Fri, 3 Apr 2020 17:13:55 +0200
-Subject: [PATCH] arm64: dts: allwinner: pinetab: enable jack detection
-
----
- arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
-index a87790df9..a72c2ec8c 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
-@@ -117,11 +117,13 @@ wifi_pwrseq: wifi_pwrseq {
- };
- 
- &codec {
-+	allwinner,inverted-jack-detection;
- 	status = "okay";
- };
- 
- &codec_analog {
- 	cpvdd-supply = <&reg_eldo1>;
-+	allwinner,internal-bias-resistor;
- 	status = "okay";
- };
- 
-@@ -448,6 +450,7 @@ &reg_rtc_ldo {
- 
- &sound {
- 	status = "okay";
-+	simple-audio-card,name = "PineTab";
- 	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
- 	simple-audio-card,widgets = "Microphone", "Internal Microphone Left",
- 				    "Microphone", "Internal Microphone Right",
--- 
-2.28.0
-
diff --git a/0008-typec-displayport-some-devices-have-pin-assignments-reversed.patch b/0008-typec-displayport-some-devices-have-pin-assignments-reversed.patch
deleted file mode 100644
index 8ec5932..0000000
--- a/0008-typec-displayport-some-devices-have-pin-assignments-reversed.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 210c2cf45fc29f4b71aaa2c38350450cc386b34c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Kamil=20Trzci=C5=84ski?= <ayufan@ayufan.eu>
-Date: Sun, 18 Oct 2020 21:36:47 +0200
-Subject: [PATCH] ayufan: typec: displayport: some devices have
- `pin-assignments` reversed
-
----
- drivers/usb/typec/altmodes/displayport.c | 16 ++++++++++++----
- 1 file changed, 12 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/usb/typec/altmodes/displayport.c b/drivers/usb/typec/altmodes/displayport.c
-index c87cd57302cd8..1cc964d18f847 100644
---- a/drivers/usb/typec/altmodes/displayport.c
-+++ b/drivers/usb/typec/altmodes/displayport.c
-@@ -91,6 +91,12 @@ static int dp_altmode_configure(struct dp_altmode *dp, u8 con)
- 		conf |= DP_CONF_UFP_U_AS_UFP_D;
- 		pin_assign = DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo) &
- 			     DP_CAP_UFP_D_PIN_ASSIGN(dp->port->vdo);
-+
-+		// Some devices have assignments reversed
-+		if (!pin_assign) {
-+			pin_assign = DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo) &
-+			     DP_CAP_DFP_D_PIN_ASSIGN(dp->port->vdo);
-+		}
- 		break;
- 	default:
- 		break;
-@@ -478,10 +484,11 @@ pin_assignment_store(struct device *dev, struct device_attribute *attr,
- 		goto out_unlock;
- 	}
- 
-+	// Some devices have pin assignments reversed
- 	if (DP_CONF_CURRENTLY(dp->data.conf) == DP_CONF_DFP_D)
--		assignments = DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo);
-+		assignments = DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo) || DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo);
- 	else
--		assignments = DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo);
-+		assignments = DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo) || DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo);
- 
- 	if (!(DP_CONF_GET_PIN_ASSIGN(conf) & assignments)) {
- 		ret = -EINVAL;
-@@ -518,10 +525,11 @@ static ssize_t pin_assignment_show(struct device *dev,
- 
- 	cur = get_count_order(DP_CONF_GET_PIN_ASSIGN(dp->data.conf));
- 
-+	// Some devices have pin assignments reversed
- 	if (DP_CONF_CURRENTLY(dp->data.conf) == DP_CONF_DFP_D)
--		assignments = DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo);
-+		assignments = DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo) || DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo);
- 	else
--		assignments = DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo);
-+		assignments = DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo) || DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo);
- 
- 	for (i = 0; assignments; assignments >>= 1, i++) {
- 		if (assignments & 1) {
diff --git a/0009-Add-megis-extcon-changes-to-fusb302.patch b/0009-Add-megis-extcon-changes-to-fusb302.patch
deleted file mode 100644
index 3759e57..0000000
--- a/0009-Add-megis-extcon-changes-to-fusb302.patch
+++ /dev/null
@@ -1,218 +0,0 @@
-From 8149051c34bc3d4c55adc56d04ffb7f7a04c2fd9 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Sun, 2 Jan 2022 16:45:28 +0100
-Subject: [PATCH 1/2] Add megis extcon changes to fusb302
-
-Signed-off-by: Dan Johansen <strit@manjaro.org>
----
- drivers/phy/rockchip/phy-rockchip-typec.c |  5 +++
- drivers/usb/typec/Kconfig                 |  7 ++++
- drivers/usb/typec/Makefile                |  1 +
- drivers/usb/typec/tcpm/fusb302.c          | 47 ++++++++++++++++-------
- drivers/usb/typec/tcpm/fusb302_reg.h      | 16 ++++----
- 5 files changed, 53 insertions(+), 23 deletions(-)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
-index d2bbdc96a167..fa10ee9a5794 100644
---- a/drivers/phy/rockchip/phy-rockchip-typec.c
-+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
-@@ -350,6 +350,7 @@ struct usb3phy_reg {
-  * struct rockchip_usb3phy_port_cfg - usb3-phy port configuration.
-  * @reg: the base address for usb3-phy config.
-  * @typec_conn_dir: the register of type-c connector direction.
-+ * @typec_conn_dir_sel: the register of type-c connector direction source.
-  * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
-  * @external_psm: the register of type-c phy external psm clock.
-  * @pipe_status: the register of type-c phy pipe status.
-@@ -360,6 +361,7 @@ struct usb3phy_reg {
- struct rockchip_usb3phy_port_cfg {
- 	unsigned int reg;
- 	struct usb3phy_reg typec_conn_dir;
-+	struct usb3phy_reg typec_conn_dir_sel;
- 	struct usb3phy_reg usb3tousb2_en;
- 	struct usb3phy_reg external_psm;
- 	struct usb3phy_reg pipe_status;
-@@ -434,6 +436,7 @@ static const struct rockchip_usb3phy_port_cfg rk3399_usb3phy_port_cfgs[] = {
- 	{
- 		.reg = 0xff7c0000,
- 		.typec_conn_dir	= { 0xe580, 0, 16 },
-+		.typec_conn_dir_sel	= { 0xe580, 8, 16+8 },
- 		.usb3tousb2_en	= { 0xe580, 3, 19 },
- 		.external_psm	= { 0xe588, 14, 30 },
- 		.pipe_status	= { 0xe5c0, 0, 0 },
-@@ -444,6 +447,7 @@ static const struct rockchip_usb3phy_port_cfg rk3399_usb3phy_port_cfgs[] = {
- 	{
- 		.reg = 0xff800000,
- 		.typec_conn_dir	= { 0xe58c, 0, 16 },
-+		.typec_conn_dir_sel	= { 0xe58c, 8, 16+8 },
- 		.usb3tousb2_en	= { 0xe58c, 3, 19 },
- 		.external_psm	= { 0xe594, 14, 30 },
- 		.pipe_status	= { 0xe5c0, 16, 16 },
-@@ -739,6 +743,7 @@ static int tcphy_phy_init(struct rockchip_typec_phy *tcphy, u8 mode)
- 
- 	reset_control_deassert(tcphy->tcphy_rst);
- 
-+	property_enable(tcphy, &cfg->typec_conn_dir_sel, 0);
- 	property_enable(tcphy, &cfg->typec_conn_dir, tcphy->flip);
- 	tcphy_dp_aux_set_flip(tcphy);
- 
-diff --git a/drivers/usb/typec/Kconfig b/drivers/usb/typec/Kconfig
-index ab480f38523a..01ecc5e590f1 100644
---- a/drivers/usb/typec/Kconfig
-+++ b/drivers/usb/typec/Kconfig
-@@ -88,6 +88,13 @@ config TYPEC_QCOM_PMIC
- 	  It will also enable the VBUS output to connected devices when a
- 	  DFP connection is made.
- 
-+config TYPEC_EXTCON
-+	tristate "Type-C switch/mux -> extcon interface bridge driver"
-+	depends on USB_ROLE_SWITCH
-+	help
-+	  Say Y or M here if your system needs bridging between typec class
-+	  and extcon interfaces.
-+
- source "drivers/usb/typec/mux/Kconfig"
- 
- source "drivers/usb/typec/altmodes/Kconfig"
-diff --git a/drivers/usb/typec/Makefile b/drivers/usb/typec/Makefile
-index a0adb8947a30..d9d829386b73 100644
---- a/drivers/usb/typec/Makefile
-+++ b/drivers/usb/typec/Makefile
-@@ -8,4 +8,5 @@ obj-$(CONFIG_TYPEC_TPS6598X)	+= tipd/
- obj-$(CONFIG_TYPEC_HD3SS3220)	+= hd3ss3220.o
- obj-$(CONFIG_TYPEC_QCOM_PMIC)	+= qcom-pmic-typec.o
- obj-$(CONFIG_TYPEC_STUSB160X) 	+= stusb160x.o
-+obj-$(CONFIG_TYPEC_EXTCON)	+= typec-extcon.o
- obj-$(CONFIG_TYPEC)		+= mux/
-diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
-index 72f9001b0792..cb26793f90f8 100644
---- a/drivers/usb/typec/tcpm/fusb302.c
-+++ b/drivers/usb/typec/tcpm/fusb302.c
-@@ -440,6 +440,16 @@ static int tcpm_get_current_limit(struct tcpc_dev *dev)
- 	int current_limit = 0;
- 	unsigned long timeout;
- 
-+	/*
-+	 * To avoid cycles in OF dependencies, we get extcon when necessary
-+	 * outside of probe function.
-+	 */
-+	if (of_property_read_bool(chip->dev->of_node, "extcon") && !chip->extcon) {
-+		chip->extcon = extcon_get_edev_by_phandle(chip->dev, 0);
-+		if (IS_ERR(chip->extcon))
-+			chip->extcon = NULL;
-+	}
-+
- 	if (!chip->extcon)
- 		return 0;
- 
-@@ -498,6 +508,7 @@ static int fusb302_set_toggling(struct fusb302_chip *chip,
- 				enum toggling_mode mode)
- {
- 	int ret = 0;
-+	u8 reg;
- 
- 	/* first disable toggling */
- 	ret = fusb302_i2c_clear_bits(chip, FUSB_REG_CONTROL2,
-@@ -556,6 +567,12 @@ static int fusb302_set_toggling(struct fusb302_chip *chip,
- 	} else {
- 		/* Datasheet says vconn MUST be off when toggling */
- 		WARN(chip->vconn_on, "Vconn is on during toggle start");
-+
-+		/* clear interrupts */
-+                ret = fusb302_i2c_read(chip, FUSB_REG_INTERRUPT, &reg);
-+		if (ret < 0)
-+			return ret;
-+
- 		/* unmask TOGDONE interrupt */
- 		ret = fusb302_i2c_clear_bits(chip, FUSB_REG_MASKA,
- 					     FUSB_REG_MASKA_TOGDONE);
-@@ -635,6 +652,14 @@ static int tcpm_set_cc(struct tcpc_dev *dev, enum typec_cc_status cc)
- 		goto done;
- 	}
- 
-+	/* adjust current for SRC */
-+	ret = fusb302_set_src_current(chip, cc_src_current[cc]);
-+	if (ret < 0) {
-+		fusb302_log(chip, "cannot set src current %s, ret=%d",
-+			    typec_cc_status_name[cc], ret);
-+		goto done;
-+	}
-+
- 	ret = fusb302_i2c_mask_write(chip, FUSB_REG_SWITCHES0,
- 				     switches0_mask, switches0_data);
- 	if (ret < 0) {
-@@ -645,14 +670,6 @@ static int tcpm_set_cc(struct tcpc_dev *dev, enum typec_cc_status cc)
- 	chip->cc1 = TYPEC_CC_OPEN;
- 	chip->cc2 = TYPEC_CC_OPEN;
- 
--	/* adjust current for SRC */
--	ret = fusb302_set_src_current(chip, cc_src_current[cc]);
--	if (ret < 0) {
--		fusb302_log(chip, "cannot set src current %s, ret=%d",
--			    typec_cc_status_name[cc], ret);
--		goto done;
--	}
--
- 	/* enable/disable interrupts, BC_LVL for SNK and COMP_CHNG for SRC */
- 	switch (cc) {
- 	case TYPEC_CC_RP_DEF:
-@@ -1528,14 +1545,16 @@ static void fusb302_irq_work(struct work_struct *work)
- 		    "IRQ: 0x%02x, a: 0x%02x, b: 0x%02x, status0: 0x%02x",
- 		    interrupt, interrupta, interruptb, status0);
- 
--	if (interrupt & FUSB_REG_INTERRUPT_VBUSOK) {
--		vbus_present = !!(status0 & FUSB_REG_STATUS0_VBUSOK);
-+	vbus_present = !!(status0 & FUSB_REG_STATUS0_VBUSOK);
-+	if (interrupt & FUSB_REG_INTERRUPT_VBUSOK)
- 		fusb302_log(chip, "IRQ: VBUS_OK, vbus=%s",
- 			    vbus_present ? "On" : "Off");
--		if (vbus_present != chip->vbus_present) {
--			chip->vbus_present = vbus_present;
--			tcpm_vbus_change(chip->tcpm_port);
--		}
-+	if (vbus_present != chip->vbus_present) {
-+		chip->vbus_present = vbus_present;
-+		if (!(interrupt & FUSB_REG_INTERRUPT_VBUSOK))
-+		fusb302_log(chip, "IRQ: VBUS changed without interrupt, vbus=%s",
-+			    vbus_present ? "On" : "Off");
-+		tcpm_vbus_change(chip->tcpm_port);
- 	}
- 
- 	if ((interrupta & FUSB_REG_INTERRUPTA_TOGDONE) && intr_togdone) {
-diff --git a/drivers/usb/typec/tcpm/fusb302_reg.h b/drivers/usb/typec/tcpm/fusb302_reg.h
-index edc0e4b0f1e6..f37d226c5027 100644
---- a/drivers/usb/typec/tcpm/fusb302_reg.h
-+++ b/drivers/usb/typec/tcpm/fusb302_reg.h
-@@ -27,14 +27,13 @@
- #define FUSB_REG_SWITCHES1_TXCC2_EN		BIT(1)
- #define FUSB_REG_SWITCHES1_TXCC1_EN		BIT(0)
- #define FUSB_REG_MEASURE			0x04
--#define FUSB_REG_MEASURE_MDAC5			BIT(7)
--#define FUSB_REG_MEASURE_MDAC4			BIT(6)
--#define FUSB_REG_MEASURE_MDAC3			BIT(5)
--#define FUSB_REG_MEASURE_MDAC2			BIT(4)
--#define FUSB_REG_MEASURE_MDAC1			BIT(3)
--#define FUSB_REG_MEASURE_MDAC0			BIT(2)
--#define FUSB_REG_MEASURE_VBUS			BIT(1)
--#define FUSB_REG_MEASURE_XXXX5			BIT(0)
-+#define FUSB_REG_MEASURE_VBUS			BIT(6)
-+#define FUSB_REG_MEASURE_MDAC5			BIT(5)
-+#define FUSB_REG_MEASURE_MDAC4			BIT(4)
-+#define FUSB_REG_MEASURE_MDAC3			BIT(3)
-+#define FUSB_REG_MEASURE_MDAC2			BIT(2)
-+#define FUSB_REG_MEASURE_MDAC1			BIT(1)
-+#define FUSB_REG_MEASURE_MDAC0			BIT(0)
- #define FUSB_REG_CONTROL0			0x06
- #define FUSB_REG_CONTROL0_TX_FLUSH		BIT(6)
- #define FUSB_REG_CONTROL0_INT_MASK		BIT(5)
-@@ -105,7 +104,6 @@
- #define FUSB_REG_STATUS0A_RX_SOFT_RESET		BIT(1)
- #define FUSB_REG_STATUS0A_RX_HARD_RESET		BIT(0)
- #define FUSB_REG_STATUS1A			0x3D
--#define FUSB_REG_STATUS1A_TOGSS			BIT(3)
- #define FUSB_REG_STATUS1A_TOGSS_RUNNING		0x0
- #define FUSB_REG_STATUS1A_TOGSS_SRC1		0x1
- #define FUSB_REG_STATUS1A_TOGSS_SRC2		0x2
--- 
-2.34.1
-
diff --git a/0009-typec-displayport-some-devices-have-pin-assignments-reversed.patch b/0009-typec-displayport-some-devices-have-pin-assignments-reversed.patch
deleted file mode 100644
index 8ec5932..0000000
--- a/0009-typec-displayport-some-devices-have-pin-assignments-reversed.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 210c2cf45fc29f4b71aaa2c38350450cc386b34c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Kamil=20Trzci=C5=84ski?= <ayufan@ayufan.eu>
-Date: Sun, 18 Oct 2020 21:36:47 +0200
-Subject: [PATCH] ayufan: typec: displayport: some devices have
- `pin-assignments` reversed
-
----
- drivers/usb/typec/altmodes/displayport.c | 16 ++++++++++++----
- 1 file changed, 12 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/usb/typec/altmodes/displayport.c b/drivers/usb/typec/altmodes/displayport.c
-index c87cd57302cd8..1cc964d18f847 100644
---- a/drivers/usb/typec/altmodes/displayport.c
-+++ b/drivers/usb/typec/altmodes/displayport.c
-@@ -91,6 +91,12 @@ static int dp_altmode_configure(struct dp_altmode *dp, u8 con)
- 		conf |= DP_CONF_UFP_U_AS_UFP_D;
- 		pin_assign = DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo) &
- 			     DP_CAP_UFP_D_PIN_ASSIGN(dp->port->vdo);
-+
-+		// Some devices have assignments reversed
-+		if (!pin_assign) {
-+			pin_assign = DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo) &
-+			     DP_CAP_DFP_D_PIN_ASSIGN(dp->port->vdo);
-+		}
- 		break;
- 	default:
- 		break;
-@@ -478,10 +484,11 @@ pin_assignment_store(struct device *dev, struct device_attribute *attr,
- 		goto out_unlock;
- 	}
- 
-+	// Some devices have pin assignments reversed
- 	if (DP_CONF_CURRENTLY(dp->data.conf) == DP_CONF_DFP_D)
--		assignments = DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo);
-+		assignments = DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo) || DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo);
- 	else
--		assignments = DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo);
-+		assignments = DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo) || DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo);
- 
- 	if (!(DP_CONF_GET_PIN_ASSIGN(conf) & assignments)) {
- 		ret = -EINVAL;
-@@ -518,10 +525,11 @@ static ssize_t pin_assignment_show(struct device *dev,
- 
- 	cur = get_count_order(DP_CONF_GET_PIN_ASSIGN(dp->data.conf));
- 
-+	// Some devices have pin assignments reversed
- 	if (DP_CONF_CURRENTLY(dp->data.conf) == DP_CONF_DFP_D)
--		assignments = DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo);
-+		assignments = DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo) || DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo);
- 	else
--		assignments = DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo);
-+		assignments = DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo) || DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo);
- 
- 	for (i = 0; assignments; assignments >>= 1, i++) {
- 		if (assignments & 1) {
diff --git a/0010-usb-typec-Add-megis-typex-to-extcon-bridge-driver.patch b/0010-usb-typec-Add-megis-typex-to-extcon-bridge-driver.patch
deleted file mode 100644
index 15b420b..0000000
--- a/0010-usb-typec-Add-megis-typex-to-extcon-bridge-driver.patch
+++ /dev/null
@@ -1,357 +0,0 @@
-From 6af2e6a2d59bd755234e5e15a47dfa669788143c Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Sun, 2 Jan 2022 16:47:40 +0100
-Subject: [PATCH 2/2] usb: typec: Add megis typex to extcon bridge driver
-
-Signed-off-by: Dan Johansen <strit@manjaro.org>
----
- drivers/usb/typec/typec-extcon.c | 337 +++++++++++++++++++++++++++++++
- 1 file changed, 337 insertions(+)
- create mode 100644 drivers/usb/typec/typec-extcon.c
-
-diff --git a/drivers/usb/typec/typec-extcon.c b/drivers/usb/typec/typec-extcon.c
-new file mode 100644
-index 000000000000..143ff2486f2f
---- /dev/null
-+++ b/drivers/usb/typec/typec-extcon.c
-@@ -0,0 +1,337 @@
-+/*
-+ * typec -> extcon bridge
-+ * Copyright (c) 2021 Ondřej Jirman <megi@xff.cz>
-+ *
-+ * This driver bridges standard type-c interfaces to drivers that
-+ * expect extcon interface.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/power_supply.h>
-+#include <linux/platform_device.h>
-+#include <linux/usb/pd.h>
-+#include <linux/usb/role.h>
-+#include <linux/usb/typec.h>
-+#include <linux/usb/typec_dp.h>
-+#include <linux/usb/typec_mux.h>
-+#include <linux/extcon-provider.h>
-+
-+struct typec_extcon {
-+        struct device *dev;
-+
-+	/* consumers */
-+	struct usb_role_switch *role_sw;
-+        struct typec_switch *sw;
-+        struct typec_mux *mux;
-+
-+	/* providers */
-+	struct extcon_dev *extcon;
-+	struct notifier_block extcon_nb;
-+
-+	/* cached state from typec controller */
-+	enum usb_role role;
-+	enum typec_orientation orientation;
-+	struct typec_altmode alt;
-+	unsigned long mode;
-+	bool has_alt;
-+	struct mutex lock;
-+};
-+
-+static const unsigned int typec_extcon_cable[] = {
-+	EXTCON_DISP_DP,
-+
-+	EXTCON_USB,
-+	EXTCON_USB_HOST,
-+
-+	EXTCON_CHG_USB_SDP,
-+	EXTCON_CHG_USB_CDP,
-+	EXTCON_CHG_USB_DCP,
-+	EXTCON_CHG_USB_ACA,
-+
-+	EXTCON_NONE,
-+};
-+
-+static void typec_extcon_set_cable(struct typec_extcon *tce, int id, bool on,
-+				   union extcon_property_value prop_ss,
-+				   union extcon_property_value prop_or)
-+{
-+	union extcon_property_value cur_ss, cur_or;
-+	bool prop_diff = false;
-+	int ret;
-+
-+	ret = extcon_get_property(tce->extcon, id,
-+				  EXTCON_PROP_USB_SS, &cur_ss);
-+	if (ret || cur_ss.intval != prop_ss.intval)
-+		prop_diff = true;
-+
-+	ret = extcon_get_property(tce->extcon, id,
-+				  EXTCON_PROP_USB_TYPEC_POLARITY, &cur_or);
-+	if (ret || cur_or.intval != prop_or.intval)
-+		prop_diff = true;
-+
-+	if (!on && extcon_get_state(tce->extcon, id)) {
-+		extcon_set_state_sync(tce->extcon, id, false);
-+	} else if (on && (!extcon_get_state(tce->extcon, id) || prop_diff)) {
-+		extcon_set_state(tce->extcon, id, true);
-+		extcon_set_property(tce->extcon, id,
-+				    EXTCON_PROP_USB_SS, prop_ss);
-+		extcon_set_property(tce->extcon, id,
-+				    EXTCON_PROP_USB_TYPEC_POLARITY, prop_or);
-+		extcon_sync(tce->extcon, id);
-+	}
-+}
-+
-+static int typec_extcon_sync_extcon(struct typec_extcon *tce)
-+{
-+	union extcon_property_value prop_ss, prop_or;
-+	bool has_dp = false;
-+
-+        mutex_lock(&tce->lock);
-+
-+	/* connector is disconnected */
-+	if (tce->orientation == TYPEC_ORIENTATION_NONE) {
-+		typec_extcon_set_cable(tce, EXTCON_USB, false, prop_ss, prop_or);
-+		typec_extcon_set_cable(tce, EXTCON_USB_HOST, false, prop_ss, prop_or);
-+		typec_extcon_set_cable(tce, EXTCON_DISP_DP, false, prop_ss, prop_or);
-+
-+		extcon_set_state_sync(tce->extcon, EXTCON_CHG_USB_SDP, false);
-+		extcon_set_state_sync(tce->extcon, EXTCON_CHG_USB_DCP, false);
-+		extcon_set_state_sync(tce->extcon, EXTCON_CHG_USB_CDP, false);
-+		extcon_set_state_sync(tce->extcon, EXTCON_CHG_USB_ACA, false);
-+
-+                goto out_unlock;
-+	}
-+
-+	prop_or.intval = tce->orientation == TYPEC_ORIENTATION_NORMAL ? 0 : 1;
-+	prop_ss.intval = 0;
-+
-+	if (tce->has_alt && tce->alt.svid == USB_TYPEC_DP_SID) {
-+		switch (tce->mode) {
-+		case TYPEC_STATE_SAFE:
-+			break;
-+		case TYPEC_DP_STATE_C:
-+		case TYPEC_DP_STATE_E:
-+			has_dp = true;
-+			break;
-+		case TYPEC_DP_STATE_D:
-+			has_dp = true;
-+			fallthrough;
-+		case TYPEC_STATE_USB:
-+			prop_ss.intval = 1;
-+			break;
-+		default:
-+			dev_err(tce->dev, "unhandled mux mode=%lu\n", tce->mode);
-+			break;
-+		}
-+	}
-+
-+	typec_extcon_set_cable(tce, EXTCON_USB,
-+			tce->role == USB_ROLE_DEVICE, prop_ss, prop_or);
-+	typec_extcon_set_cable(tce, EXTCON_USB_HOST,
-+			tce->role == USB_ROLE_HOST, prop_ss, prop_or);
-+
-+	typec_extcon_set_cable(tce, EXTCON_DISP_DP, has_dp, prop_ss, prop_or);
-+
-+out_unlock:
-+	mutex_unlock(&tce->lock);
-+	return 0;
-+}
-+
-+static int typec_extcon_sw_set(struct typec_switch *sw,
-+			       enum typec_orientation orientation)
-+{
-+        struct typec_extcon *tce = typec_switch_get_drvdata(sw);
-+
-+	dev_dbg(tce->dev, "SW SET: orientation=%d\n", orientation);
-+
-+        mutex_lock(&tce->lock);
-+	tce->orientation = orientation;
-+        mutex_unlock(&tce->lock);
-+
-+	typec_extcon_sync_extcon(tce);
-+
-+        return 0;
-+}
-+
-+static int typec_extcon_mux_set(struct typec_mux *mux,
-+				struct typec_mux_state *state)
-+{
-+        struct typec_extcon *tce = typec_mux_get_drvdata(mux);
-+	struct typec_altmode *alt = state->alt;
-+
-+	dev_dbg(tce->dev, "MUX SET: state->mode=%lu\n", state->mode);
-+	if (alt)
-+		dev_dbg(tce->dev, "      ...alt: svid=%04hx mode=%d vdo=%08x active=%u\n",
-+			alt->svid, alt->mode, alt->vdo, alt->active);
-+
-+        mutex_lock(&tce->lock);
-+	tce->mode = state->mode;
-+	tce->has_alt = alt != NULL;
-+        if (alt)
-+		tce->alt = *alt;
-+	mutex_unlock(&tce->lock);
-+
-+	typec_extcon_sync_extcon(tce);
-+
-+        return 0;
-+}
-+
-+static int typec_extcon_usb_set_role(struct usb_role_switch *sw,
-+				     enum usb_role role)
-+{
-+        struct typec_extcon *tce = usb_role_switch_get_drvdata(sw);
-+
-+	dev_dbg(tce->dev, "ROLE SET: role=%d\n", role);
-+
-+        mutex_lock(&tce->lock);
-+	tce->role = role;
-+	mutex_unlock(&tce->lock);
-+
-+	typec_extcon_sync_extcon(tce);
-+
-+        return 0;
-+}
-+
-+static int typec_extcon_notifier(struct notifier_block *nb,
-+					 unsigned long action, void *data)
-+{
-+	struct typec_extcon *tce = container_of(nb, struct typec_extcon, extcon_nb);
-+
-+	bool sdp = extcon_get_state(tce->extcon, EXTCON_CHG_USB_SDP);
-+	bool cdp = extcon_get_state(tce->extcon, EXTCON_CHG_USB_CDP);
-+	bool dcp = extcon_get_state(tce->extcon, EXTCON_CHG_USB_DCP);
-+	bool usb = extcon_get_state(tce->extcon, EXTCON_USB);
-+	bool usb_host = extcon_get_state(tce->extcon, EXTCON_USB_HOST);
-+	bool dp = extcon_get_state(tce->extcon, EXTCON_DISP_DP);
-+
-+	dev_info(tce->dev, "extcon changed sdp=%d cdp=%d dcp=%d usb=%d usb_host=%d dp=%d\n",
-+		 sdp, cdp, dcp, usb, usb_host, dp);
-+
-+	return NOTIFY_OK;
-+}
-+
-+static int typec_extcon_probe(struct platform_device *pdev)
-+{
-+        struct typec_switch_desc sw_desc = { };
-+        struct typec_mux_desc mux_desc = { };
-+        struct usb_role_switch_desc role_desc = { };
-+        struct device *dev = &pdev->dev;
-+        struct typec_extcon *tce;
-+        int ret = 0;
-+
-+        tce = devm_kzalloc(dev, sizeof(*tce), GFP_KERNEL);
-+        if (!tce)
-+                return -ENOMEM;
-+
-+        tce->dev = &pdev->dev;
-+	mutex_init(&tce->lock);
-+	tce->mode = TYPEC_STATE_SAFE;
-+
-+	sw_desc.drvdata = tce;
-+	sw_desc.fwnode = dev->fwnode;
-+	sw_desc.set = typec_extcon_sw_set;
-+
-+	tce->sw = typec_switch_register(dev, &sw_desc);
-+	if (IS_ERR(tce->sw))
-+		return dev_err_probe(dev, PTR_ERR(tce->sw),
-+				     "Error registering typec switch\n");
-+
-+	mux_desc.drvdata = tce;
-+	mux_desc.fwnode = dev->fwnode;
-+	mux_desc.set = typec_extcon_mux_set;
-+
-+	tce->mux = typec_mux_register(dev, &mux_desc);
-+	if (IS_ERR(tce->mux)) {
-+		ret = dev_err_probe(dev, PTR_ERR(tce->mux),
-+				    "Error registering typec mux\n");
-+		goto err_sw;
-+	}
-+
-+	role_desc.driver_data = tce;
-+	role_desc.fwnode = dev->fwnode;
-+	role_desc.name = fwnode_get_name(dev->fwnode);
-+	role_desc.set = typec_extcon_usb_set_role;
-+
-+	tce->role_sw = usb_role_switch_register(dev, &role_desc);
-+	if (IS_ERR(tce->role_sw)) {
-+		ret = dev_err_probe(dev, PTR_ERR(tce->role_sw),
-+				    "Error registering USB role switch\n");
-+		goto err_mux;
-+	}
-+
-+	tce->extcon = devm_extcon_dev_allocate(dev, typec_extcon_cable);
-+	if (IS_ERR(tce->extcon)) {
-+		ret = PTR_ERR(tce->extcon);
-+		goto err_role;
-+	}
-+
-+	ret = devm_extcon_dev_register(dev, tce->extcon);
-+	if (ret) {
-+		ret = dev_err_probe(dev, ret, "failed to register extcon device\n");
-+		goto err_role;
-+	}
-+
-+	extcon_set_property_capability(tce->extcon, EXTCON_USB,
-+				       EXTCON_PROP_USB_SS);
-+	extcon_set_property_capability(tce->extcon, EXTCON_USB,
-+				       EXTCON_PROP_USB_TYPEC_POLARITY);
-+	extcon_set_property_capability(tce->extcon, EXTCON_USB_HOST,
-+				       EXTCON_PROP_USB_SS);
-+	extcon_set_property_capability(tce->extcon, EXTCON_USB_HOST,
-+				       EXTCON_PROP_USB_TYPEC_POLARITY);
-+	extcon_set_property_capability(tce->extcon, EXTCON_DISP_DP,
-+				       EXTCON_PROP_USB_SS);
-+	extcon_set_property_capability(tce->extcon, EXTCON_DISP_DP,
-+				       EXTCON_PROP_USB_TYPEC_POLARITY);
-+
-+	tce->extcon_nb.notifier_call = typec_extcon_notifier;
-+	ret = devm_extcon_register_notifier_all(dev, tce->extcon, &tce->extcon_nb);
-+	if (ret) {
-+		dev_err_probe(dev, ret, "Failed to register extcon notifier\n");
-+		goto err_role;
-+	}
-+
-+	return 0;
-+
-+err_role:
-+	usb_role_switch_unregister(tce->role_sw);
-+err_mux:
-+	typec_mux_unregister(tce->mux);
-+err_sw:
-+	typec_switch_unregister(tce->sw);
-+	return ret;
-+}
-+
-+static int typec_extcon_remove(struct platform_device *pdev)
-+{
-+        struct typec_extcon *tce = platform_get_drvdata(pdev);
-+
-+	usb_role_switch_unregister(tce->role_sw);
-+	typec_mux_unregister(tce->mux);
-+	typec_switch_unregister(tce->sw);
-+
-+        return 0;
-+}
-+
-+static struct of_device_id typec_extcon_of_match_table[] = {
-+        { .compatible = "linux,typec-extcon-bridge" },
-+        { },
-+};
-+MODULE_DEVICE_TABLE(of, typec_extcon_of_match_table);
-+
-+static struct platform_driver typec_extcon_driver = {
-+        .driver = {
-+                .name = "typec-extcon",
-+                .of_match_table = typec_extcon_of_match_table,
-+        },
-+        .probe = typec_extcon_probe,
-+        .remove = typec_extcon_remove,
-+};
-+
-+module_platform_driver(typec_extcon_driver);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Ondrej Jirman <megous@megous.com>");
-+MODULE_DESCRIPTION("typec -> extcon bridge driver");
--- 
-2.34.1
-
diff --git a/0010-usb-typec-add-extcon-to-tcpm.patch b/0010-usb-typec-add-extcon-to-tcpm.patch
deleted file mode 100644
index 8e72990..0000000
--- a/0010-usb-typec-add-extcon-to-tcpm.patch
+++ /dev/null
@@ -1,226 +0,0 @@
-From ed2bd8b9262b5367b0e253ffbb238ee85d82f52f Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Tue, 25 May 2021 22:50:01 +0200
-Subject: [PATCH] usb/typec: add extcon to tcpm
-
----
- drivers/usb/typec/tcpm/tcpm.c | 133 +++++++++++++++++++++++++++++++++-
- 1 file changed, 132 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
-index 64133e586c64..8fa1d0993b97 100644
---- a/drivers/usb/typec/tcpm/tcpm.c
-+++ b/drivers/usb/typec/tcpm/tcpm.c
-@@ -8,6 +8,7 @@
- #include <linux/completion.h>
- #include <linux/debugfs.h>
- #include <linux/device.h>
-+#include <linux/extcon-provider.h>
- #include <linux/hrtimer.h>
- #include <linux/jiffies.h>
- #include <linux/kernel.h>
-@@ -468,6 +469,12 @@ struct tcpm_port {
- 	 * SNK_READY for non-pd link.
- 	 */
- 	bool slow_charger_loop;
-+
-+#ifdef CONFIG_EXTCON
-+	struct extcon_dev *extcon;
-+	unsigned int *extcon_cables;
-+#endif
-+
- #ifdef CONFIG_DEBUG_FS
- 	struct dentry *dentry;
- 	struct mutex logbuffer_lock;	/* log buffer access lock */
-@@ -824,6 +831,33 @@ static void tcpm_ams_finish(struct tcpm_port *port)
- 	port->ams = NONE_AMS;
- }
- 
-+static void tcpm_update_extcon_data(struct tcpm_port *port, bool attached) {
-+#ifdef CONFIG_EXTCON
-+	unsigned int *capability = port->extcon_cables;
-+	if (port->data_role == TYPEC_HOST) {
-+		extcon_set_state(port->extcon, EXTCON_USB, false);
-+		extcon_set_state(port->extcon, EXTCON_USB_HOST, attached);
-+	} else {
-+		extcon_set_state(port->extcon, EXTCON_USB, true);
-+		extcon_set_state(port->extcon, EXTCON_USB_HOST, attached);
-+	}
-+	while(*capability != EXTCON_NONE) {
-+		union extcon_property_value val;
-+		val.intval = true;
-+		extcon_set_property(port->extcon, *capability, EXTCON_PROP_USB_SS, val);
-+		val.intval = (port->polarity == TYPEC_POLARITY_CC2);
-+		extcon_set_property(port->extcon, *capability,
-+			EXTCON_PROP_USB_TYPEC_POLARITY, val);
-+		extcon_sync(port->extcon, *capability);
-+		capability++;
-+	}
-+	tcpm_log(port, "Extcon update (%s): %s, %s",
-+		attached ? "attached" : "detached",
-+		port->data_role == TYPEC_HOST ? "host" : "device",
-+		port->polarity == TYPEC_POLARITY_CC1 ? "normal" : "flipped");
-+#endif
-+}
-+
- static int tcpm_pd_transmit(struct tcpm_port *port,
- 			    enum tcpm_transmit_type type,
- 			    const struct pd_message *msg)
-@@ -1036,6 +1070,8 @@ static int tcpm_set_roles(struct tcpm_port *port, bool attached,
- 	typec_set_data_role(port->typec_port, data);
- 	typec_set_pwr_role(port->typec_port, role);
- 
-+	tcpm_update_extcon_data(port, attached);
-+
- 	return 0;
- }
- 
-@@ -1484,7 +1520,7 @@ static void svdm_consume_modes(struct tcpm_port *port, const u32 *p, int cnt)
- 		paltmode->mode = i;
- 		paltmode->vdo = p[i];
- 
--		tcpm_log(port, " Alternate mode %d: SVID 0x%04x, VDO %d: 0x%08x",
-+		tcpm_log(port, "Alternate mode %d: SVID 0x%04x, VDO %d: 0x%08x",
- 			 pmdata->altmodes, paltmode->svid,
- 			 paltmode->mode, paltmode->vdo);
- 
-@@ -1629,6 +1665,7 @@ static int tcpm_pd_svdm(struct tcpm_port *port, struct typec_altmode *adev,
- 			modep->svid_index++;
- 			if (modep->svid_index < modep->nsvids) {
- 				u16 svid = modep->svids[modep->svid_index];
-+                 tcpm_log(port, "More modes available, sending discover");
- 				response[0] = VDO(svid, 1, svdm_version, CMD_DISCOVER_MODES);
- 				rlen = 1;
- 			} else {
-@@ -3610,6 +3647,8 @@ static void tcpm_detach(struct tcpm_port *port)
- 	}
- 
- 	tcpm_reset_port(port);
-+
-+	tcpm_update_extcon_data(port, false);
- }
- 
- static void tcpm_src_detach(struct tcpm_port *port)
-@@ -5808,6 +5847,64 @@ void tcpm_tcpc_reset(struct tcpm_port *port)
- }
- EXPORT_SYMBOL_GPL(tcpm_tcpc_reset);
- 
-+static int tcpm_fw_get_caps_late(struct tcpm_port *port,
-+			    struct fwnode_handle *fwnode)
-+{
-+	int ret, i;
-+	ret = fwnode_property_count_u32(fwnode, "typec-altmodes");
-+	if (ret > 0) {
-+		u32 *props;
-+		if (ret % 4) {
-+			dev_err(port->dev, "Length of typec altmode array must be divisible by 4");
-+			return -EINVAL;
-+		}
-+
-+		props = devm_kzalloc(port->dev, sizeof(u32) * ret, GFP_KERNEL);
-+		if (!props) {
-+			dev_err(port->dev, "Failed to allocate memory for altmode properties");
-+			return -ENOMEM;
-+		}
-+
-+		if(fwnode_property_read_u32_array(fwnode, "typec-altmodes", props, ret) < 0) {
-+			dev_err(port->dev, "Failed to read altmodes from port");
-+			return -EINVAL;
-+		}
-+
-+		i = 0;
-+		while (ret > 0 && i < ARRAY_SIZE(port->port_altmode)) {
-+			struct typec_altmode *alt;
-+			struct typec_altmode_desc alt_desc = {
-+				.svid = props[i * 4],
-+				.mode = props[i * 4 + 1],
-+				.vdo  = props[i * 4 + 2],
-+				.roles = props[i * 4 + 3],
-+			};
-+
-+
-+			tcpm_log(port, "Adding altmode SVID: 0x%04x, mode: %d, vdo: %u, role: %d",
-+				alt_desc.svid, alt_desc.mode, alt_desc.vdo, alt_desc.roles);
-+			alt = typec_port_register_altmode(port->typec_port,
-+							  &alt_desc);
-+			if (IS_ERR(alt)) {
-+				tcpm_log(port,
-+					 "%s: failed to register port alternate mode 0x%x",
-+					 dev_name(port->dev), alt_desc.svid);
-+				break;
-+			}
-+			typec_altmode_set_drvdata(alt, port);
-+			alt->ops = &tcpm_altmode_ops;
-+			port->port_altmode[i] = alt;
-+			i++;
-+			ret -= 4;
-+		}
-+	}
-+	return 0;
-+}
-+
-+unsigned int default_supported_cables[] = {
-+	EXTCON_NONE
-+};
-+
- static int tcpm_fw_get_caps(struct tcpm_port *port,
- 			    struct fwnode_handle *fwnode)
- {
-@@ -5827,6 +5924,23 @@ static int tcpm_fw_get_caps(struct tcpm_port *port,
- 	 */
- 	fw_devlink_purge_absent_suppliers(fwnode);
- 
-+#ifdef CONFIG_EXTCON
-+	ret = fwnode_property_count_u32(fwnode, "extcon-cables");
-+	if (ret > 0) {
-+		port->extcon_cables = devm_kzalloc(port->dev, sizeof(u32) * ret, GFP_KERNEL);
-+		if (!port->extcon_cables) {
-+			dev_err(port->dev, "Failed to allocate memory for extcon cable types. "\
-+				"Using default tyes");
-+			goto extcon_default;
-+		}
-+		fwnode_property_read_u32_array(fwnode, "extcon-cables", port->extcon_cables, ret);
-+	} else {
-+extcon_default:
-+		dev_info(port->dev, "No cable types defined, using default cables");
-+		port->extcon_cables = default_supported_cables;
-+	}
-+#endif
-+
- 	/* USB data support is optional */
- 	ret = fwnode_property_read_string(fwnode, "data-role", &cap_str);
- 	if (ret == 0) {
-@@ -6226,6 +6340,17 @@ struct tcpm_port *tcpm_register_port(struct device *dev, struct tcpc_dev *tcpc)
- 		goto out_destroy_wq;
- 
- 	port->try_role = port->typec_caps.prefer_role;
-+#ifdef CONFIG_EXTCON
-+	port->extcon = devm_extcon_dev_allocate(dev, port->extcon_cables);
-+	if (IS_ERR(port->extcon)) {
-+		dev_err(dev, "Failed to allocate extcon device: %ld", PTR_ERR(port->extcon));
-+		goto out_destroy_wq;
-+	}
-+	if((err = devm_extcon_dev_register(dev, port->extcon))) {
-+		dev_err(dev, "Failed to register extcon device: %d", err);
-+		goto out_destroy_wq;
-+	}
-+#endif
- 
- 	port->typec_caps.fwnode = tcpc->fwnode;
- 	port->typec_caps.revision = 0x0120;	/* Type-C spec release 1.2 */
-@@ -6259,6 +6384,12 @@ struct tcpm_port *tcpm_register_port(struct device *dev, struct tcpc_dev *tcpc)
- 				     &tcpm_altmode_ops, port,
- 				     port->port_altmode, ALTMODE_DISCOVERY_MAX);
- 
-+	err = tcpm_fw_get_caps_late(port, tcpc->fwnode);
-+	if (err < 0) {
-+		dev_err(dev, "Failed to get altmodes from fwnode");
-+		goto out_destroy_wq;
-+	}
-+
- 	mutex_lock(&port->lock);
- 	tcpm_init(port);
- 	mutex_unlock(&port->lock);
--- 
-2.31.1
-
diff --git a/0011-arm64-rockchip-add-DP-ALT-rockpro64.patch b/0011-arm64-rockchip-add-DP-ALT-rockpro64.patch
deleted file mode 100644
index e2eb1a7..0000000
--- a/0011-arm64-rockchip-add-DP-ALT-rockpro64.patch
+++ /dev/null
@@ -1,144 +0,0 @@
-From ff683bc9cd8130038de50b3d6588093cd9ddc6c6 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Sun, 2 Jan 2022 21:33:53 +0100
-Subject: [PATCH] arm64: rockchip: add DP ALT rockpro64
-
-Signed-off-by: Dan Johansen <strit@manjaro.org>
----
- .../boot/dts/rockchip/rk3399-rockpro64.dtsi   | 88 +++++++++++++++++++
- 1 file changed, 88 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
-index 83db4ca67334..cb2a64689eb3 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
-@@ -6,6 +6,7 @@
- 
- #include <dt-bindings/input/linux-event-codes.h>
- #include <dt-bindings/pwm/pwm.h>
-+#include <dt-bindings/usb/pd.h>
- #include "rk3399.dtsi"
- #include "rk3399-opp.dtsi"
- 
-@@ -220,6 +221,20 @@ vdd_log: vdd-log {
- 		regulator-max-microvolt = <1700000>;
- 		vin-supply = <&vcc5v0_sys>;
- 	};
-+	
-+    typec_extcon_bridge: typec-extcon {
-+		compatible = "linux,typec-extcon-bridge";
-+		usb-role-switch;
-+		orientation-switch;
-+		mode-switch;
-+		svid = /bits/ 16 <0xff01>;
-+	};
-+};
-+
-+&cdn_dp {
-+	status = "okay";
-+	extcon = <&typec_extcon_bridge>;
-+	phys = <&tcphy0_dp>;
- };
- 
- &cpu_l0 {
-@@ -563,7 +578,57 @@ fusb0: typec-portc@22 {
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&fusb0_int>;
- 		vbus-supply = <&vcc5v0_typec>;
-+		extcon = <&typec_extcon_bridge>;
-+		usb-role-switch = <&typec_extcon_bridge>;
- 		status = "okay";
-+
-+		connector {
-+			compatible = "usb-c-connector";
-+			data-role = "host";
-+			label = "USB-C";
-+			power-role = "source";
-+			source-pdos = <PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>;
-+			try-power-role = "sink";
-+			
-+			mode-switch = <&typec_extcon_bridge>;
-+			orientation-switch = <&typec_extcon_bridge>;
-+
-+			altmodes {
-+				dp {
-+					svid = <0xff01>;
-+					vdo = <0x0c0046>;
-+				};
-+			};
-+
-+			ports {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				port@0 {
-+					reg = <0>;
-+
-+					usbc_hs: endpoint {
-+						remote-endpoint = <&u2phy0_typec_hs>;
-+					};
-+				};
-+
-+				port@1 {
-+					reg = <1>;
-+
-+					usbc_ss: endpoint {
-+						remote-endpoint = <&tcphy0_typec_ss>;
-+					};
-+				};
-+
-+				port@2 {
-+					reg = <2>;
-+
-+					usbc_dp: endpoint {
-+						remote-endpoint = <&tcphy0_typec_dp>;
-+					};
-+				};
-+			};
-+		};
- 	};
- };
- 
-@@ -784,9 +849,26 @@ flash@0 {
- };
- 
- &tcphy0 {
-+	extcon = <&typec_extcon_bridge>;
- 	status = "okay";
- };
- 
-+&tcphy0_dp {
-+	port {
-+		tcphy0_typec_dp: endpoint {
-+			remote-endpoint = <&usbc_dp>;
-+		};
-+	};
-+};
-+
-+&tcphy0_usb3 {
-+	port {
-+		tcphy0_typec_ss: endpoint {
-+			remote-endpoint = <&usbc_ss>;
-+		};
-+	};
-+};
-+
- &tcphy1 {
- 	status = "okay";
- };
-@@ -810,6 +892,12 @@ u2phy0_host: host-port {
- 		phy-supply = <&vcc5v0_host>;
- 		status = "okay";
- 	};
-+
-+	port {
-+		u2phy0_typec_hs: endpoint {
-+			remote-endpoint = <&usbc_hs>;
-+		};
-+	};
- };
- 
- &u2phy1 {
--- 
-2.34.1
-
diff --git a/0012-ayufan-drm-rockchip-add-support-for-modeline-32MHz-e.patch b/0012-ayufan-drm-rockchip-add-support-for-modeline-32MHz-e.patch
deleted file mode 100644
index 5fe02ec..0000000
--- a/0012-ayufan-drm-rockchip-add-support-for-modeline-32MHz-e.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From bdd540aa2a4eb304afb6e9d6e469b856c7b441c7 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Kamil=20Trzci=C5=84ski?= <ayufan@ayufan.eu>
-Date: Fri, 10 Apr 2020 00:24:03 +0200
-Subject: [PATCH 2/2] ayufan: drm: rockchip: add support for modeline 32MHz
- (ex. `1024x600@43`)
-
----
- drivers/clk/rockchip/clk-rk3399.c           | 1 +
- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 6 ++++++
- 2 files changed, 7 insertions(+)
-
-diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
-index 7df2f1e00347..5dcf9b5778a3 100644
---- a/drivers/clk/rockchip/clk-rk3399.c
-+++ b/drivers/clk/rockchip/clk-rk3399.c
-@@ -101,6 +101,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
- 	RK3036_PLL_RATE(  74250000, 2, 99, 4, 4, 1, 0),
- 	RK3036_PLL_RATE(  65000000, 1, 65, 6, 4, 1, 0),
- 	RK3036_PLL_RATE(  54000000, 1, 54, 6, 4, 1, 0),
-+	RK3036_PLL_RATE(  32000000, 3, 112, 7, 4, 0, 0),
- 	RK3036_PLL_RATE(  27000000, 1, 27, 6, 4, 1, 0),
- 	{ /* sentinel */ },
- };
-diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
-index 23de359a1dec..9ad35ed3018e 100644
---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
-+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
-@@ -84,6 +84,12 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
- 			{ 0x2153, 0x0000},
- 			{ 0x40f3, 0x0000}
- 		},
-+	}, {
-+		32000000, {
-+			{ 0x0072, 0x0001},
-+			{ 0x2153, 0x0000},
-+			{ 0x40f3, 0x0000}
-+		},
- 	}, {
- 		36000000, {
- 			{ 0x00b3, 0x0000},
--- 
-2.25.1
-
diff --git a/0013-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch b/0013-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch
deleted file mode 100644
index d8d0721..0000000
--- a/0013-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch
+++ /dev/null
@@ -1,187 +0,0 @@
-From ceae51b1cc0e5a5b42999274657bd55606193661 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Jari=20H=C3=A4m=C3=A4l=C3=A4inen?= <nuumiofi@gmail.com>
-Date: Sun, 22 Nov 2020 15:24:49 +0200
-Subject: [PATCH] nuumio: pcie: Reimplement rockchip PCIe bus scan delay
-
-Reimplementation of my old Rockchip PCIe bus scan delay patch for
-kernels >= 5.9.
-
-Delay may fix panix with some PCIe devices, like LSI SAS 9201-8i with
-SAS2008 chipset in my case.
-
-Crash dump (customized Manjaro kernel before this patch):
-[    1.229856] SError Interrupt on CPU4, code 0xbf000002 -- SError
-[    1.229860] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 5.9.9-2.0-MANJARO-ARM #1
-[    1.229862] Hardware name: Pine64 RockPro64 v2.1 (DT)
-[    1.229864] pstate: 60000085 (nZCv daIf -PAN -UAO BTYPE=--)
-[    1.229866] pc : rockchip_pcie_rd_conf+0xb4/0x270
-[    1.229868] lr : rockchip_pcie_rd_conf+0x1b4/0x270
-[    1.229870] sp : ffff80001004b850
-[    1.229872] x29: ffff80001004b850 x28: 0000000000000001
-[    1.229877] x27: 0000000000000000 x26: ffff00007a795000
-[    1.229882] x25: ffff00007a7910b0 x24: 0000000000000000
-[    1.229887] x23: 0000000000000000 x22: ffff00007b3a4380
-[    1.229891] x21: ffff80001004b8c4 x20: 0000000000000004
-[    1.229895] x19: 0000000000100000 x18: 0000000000000020
-[    1.229900] x17: 0000000000000001 x16: 0000000000000019
-[    1.229904] x15: ffff00007b222fd8 x14: ffffffffffffffff
-[    1.229908] x13: ffff00007a79ba1c x12: ffff00007a79b290
-[    1.229912] x11: 0101010101010101 x10: 7f7f7f7f7f7f7f7f
-[    1.229917] x9 : ff72646268756463 x8 : 0000000000000391
-[    1.229921] x7 : ffff80001004b880 x6 : 0000000000000001
-[    1.229925] x5 : 0000000000000000 x4 : 0000000000000000
-[    1.229930] x3 : 0000000000c00008 x2 : 000000000080000a
-[    1.229934] x1 : 0000000000000000 x0 : ffff800014000000
-[    1.229939] Kernel panic - not syncing: Asynchronous SError Interrupt
-[    1.229942] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 5.9.9-2.0-MANJARO-ARM #1
-[    1.229944] Hardware name: Pine64 RockPro64 v2.1 (DT)
-[    1.229946] Call trace:
-[    1.229948]  dump_backtrace+0x0/0x1d0
-[    1.229949]  show_stack+0x18/0x24
-[    1.229951]  dump_stack+0xc0/0x118
-[    1.229953]  panic+0x148/0x320
-[    1.229955]  nmi_panic+0x8c/0x90
-[    1.229956]  arm64_serror_panic+0x78/0x84
-[    1.229958]  do_serror+0x15c/0x160
-[    1.229960]  el1_error+0x84/0x100
-[    1.229962]  rockchip_pcie_rd_conf+0xb4/0x270
-[    1.229964]  pci_bus_read_config_dword+0x6c/0xd0
-[    1.229966]  pci_bus_generic_read_dev_vendor_id+0x34/0x1b0
-[    1.229968]  pci_scan_single_device+0xa4/0x144
-[    1.229970]  pci_scan_slot+0x40/0x12c
-[    1.229972]  pci_scan_child_bus_extend+0x58/0x34c
-[    1.229974]  pci_scan_bridge_extend+0x310/0x590
-[    1.229976]  pci_scan_child_bus_extend+0x210/0x34c
-[    1.229978]  pci_scan_root_bus_bridge+0x68/0xdc
-[    1.229980]  pci_host_probe+0x18/0xc4
-[    1.229981]  rockchip_pcie_probe+0x204/0x330
-[    1.229984]  platform_drv_probe+0x54/0xb0
-[    1.229985]  really_probe+0xe8/0x500
-[    1.229987]  driver_probe_device+0xd8/0xf0
-[    1.229989]  device_driver_attach+0xc0/0xcc
-[    1.229991]  __driver_attach+0xa4/0x170
-[    1.229993]  bus_for_each_dev+0x70/0xc0
-[    1.229994]  driver_attach+0x24/0x30
-[    1.229996]  bus_add_driver+0x140/0x234
-[    1.229998]  driver_register+0x78/0x130
-[    1.230000]  __platform_driver_register+0x4c/0x60
-[    1.230002]  rockchip_pcie_driver_init+0x1c/0x28
-[    1.230004]  do_one_initcall+0x54/0x1c0
-[    1.230005]  do_initcalls+0xf4/0x130
-[    1.230007]  kernel_init_freeable+0x144/0x19c
-[    1.230009]  kernel_init+0x14/0x11c
-[    1.230011]  ret_from_fork+0x10/0x34
-[    1.230035] SMP: stopping secondary CPUs
-[    1.230037] Kernel Offset: disabled
-[    1.230039] CPU features: 0x0240022,2100200c
-[    1.230041] Memory Limit: none
----
- .../admin-guide/kernel-parameters.txt         |  8 ++++++
- .../boot/dts/rockchip/rk3399-rockpro64.dtsi   |  1 +
- drivers/pci/controller/pcie-rockchip-host.c   | 25 +++++++++++++++++++
- drivers/pci/controller/pcie-rockchip.c        |  6 +++++
- drivers/pci/controller/pcie-rockchip.h        |  2 ++
- 5 files changed, 42 insertions(+)
-
-diff -up linux-5.16/Documentation/admin-guide/kernel-parameters.txt.55~ linux-5.16/Documentation/admin-guide/kernel-parameters.txt
---- linux-5.16/Documentation/admin-guide/kernel-parameters.txt.55~	2022-01-09 23:55:34.000000000 +0100
-+++ linux-5.16/Documentation/admin-guide/kernel-parameters.txt	2022-01-10 12:02:41.008956711 +0100
-@@ -4109,6 +4109,14 @@
- 		nomsi	Do not use MSI for native PCIe PME signaling (this makes
- 			all PCIe root ports use INTx for all services).
- 
-+	pcie_rockchip_host.bus_scan_delay=	[PCIE] Delay in ms before
-+			scanning PCIe bus in Rockchip PCIe host driver. Some PCIe
-+			cards seem to need delays that can be several hundred ms.
-+			If set to greater than or equal to 0 this parameter will
-+			override delay that can be set in device tree.
-+			Values less than 0 mean that this parameter is ignored.
-+			default=-1
-+
- 	pcmv=		[HW,PCMCIA] BadgePAD 4
- 
- 	pd_ignore_unused
-diff -up linux-5.16/drivers/pci/controller/pcie-rockchip.c.55~ linux-5.16/drivers/pci/controller/pcie-rockchip.c
---- linux-5.16/drivers/pci/controller/pcie-rockchip.c.55~	2022-01-10 12:02:40.988956649 +0100
-+++ linux-5.16/drivers/pci/controller/pcie-rockchip.c	2022-01-10 12:02:41.008956711 +0100
-@@ -148,6 +148,12 @@ int rockchip_pcie_parse_dt(struct rockch
- 		return PTR_ERR(rockchip->clk_pcie_pm);
- 	}
- 
-+	err = of_property_read_u32(node, "bus-scan-delay-ms", &rockchip->bus_scan_delay);
-+	if (err) {
-+		dev_info(dev, "no bus scan delay, default to 0 ms\n");
-+		rockchip->bus_scan_delay = 0;
-+	}
-+
- 	return 0;
- }
- EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);
-diff -up linux-5.16/drivers/pci/controller/pcie-rockchip.h.55~ linux-5.16/drivers/pci/controller/pcie-rockchip.h
---- linux-5.16/drivers/pci/controller/pcie-rockchip.h.55~	2022-01-09 23:55:34.000000000 +0100
-+++ linux-5.16/drivers/pci/controller/pcie-rockchip.h	2022-01-10 12:02:41.008956711 +0100
-@@ -300,6 +300,8 @@ struct rockchip_pcie {
- 	phys_addr_t msg_bus_addr;
- 	bool is_rc;
- 	struct resource *mem_res;
-+	/* Bus scan delay is a workaround for some pcie devices causing crashes */
-+	u32 bus_scan_delay;
- };
- 
- static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
-diff -up linux-5.16/drivers/pci/controller/pcie-rockchip-host.c.55~ linux-5.16/drivers/pci/controller/pcie-rockchip-host.c
---- linux-5.16/drivers/pci/controller/pcie-rockchip-host.c.55~	2022-01-09 23:55:34.000000000 +0100
-+++ linux-5.16/drivers/pci/controller/pcie-rockchip-host.c	2022-01-10 12:03:40.622140631 +0100
-@@ -24,6 +24,7 @@
- #include <linux/kernel.h>
- #include <linux/mfd/syscon.h>
- #include <linux/module.h>
-+#include <linux/moduleparam.h>
- #include <linux/of_address.h>
- #include <linux/of_device.h>
- #include <linux/of_pci.h>
-@@ -39,6 +40,9 @@
- #include "../pci.h"
- #include "pcie-rockchip.h"
- 
-+static int bus_scan_delay = -1;
-+module_param_named(bus_scan_delay, bus_scan_delay, int, S_IRUGO);
-+
- static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
- {
- 	u32 status;
-@@ -935,6 +939,7 @@ static int rockchip_pcie_probe(struct pl
- 	struct device *dev = &pdev->dev;
- 	struct pci_host_bridge *bridge;
- 	int err;
-+	u32 delay = 0;
- 
- 	if (!dev->of_node)
- 		return -ENODEV;
-@@ -984,6 +989,26 @@ static int rockchip_pcie_probe(struct pl
- 	bridge->sysdata = rockchip;
- 	bridge->ops = &rockchip_pcie_ops;
- 
-+	/* Checking if bus scan delay was given from command line and prefer
-+	 * that over the value in device tree (which defaults to 0 if not set).
-+	 */
-+	if (bus_scan_delay >= 0) {
-+		delay = bus_scan_delay;
-+		dev_info(dev, "wait %u ms (from command-line) before bus scan\n", delay);
-+	} else {
-+		delay = rockchip->bus_scan_delay;
-+		dev_info(dev, "wait %u ms (from device tree) before bus scan\n", delay);
-+	}
-+	/* Workaround for some devices crashing on pci_host_probe / pci_scan_root_bus_bridge
-+	 * calls: sleep a bit before bus scan. Call trace gets to rockchip_pcie_rd_conf when
-+	 * trying to read vendor id (pci_bus_generic_read_dev_vendor_id is in call stack)
-+	 * before panicing. I have no idea why this works or what causes the panic. I just
-+	 * found this hack by luck when trying to "make it break differently if possible".
-+	 */
-+	if (delay > 0) {
-+		msleep(delay);
-+	}
-+
- 	err = rockchip_pcie_setup_irq(rockchip);
- 	if (err)
- 		goto err_remove_irq_domain;
diff --git a/0014-arm64-dts-rockchip-add-typec-extcon-hack.patch b/0014-arm64-dts-rockchip-add-typec-extcon-hack.patch
deleted file mode 100644
index 13db3d4..0000000
--- a/0014-arm64-dts-rockchip-add-typec-extcon-hack.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-diff -up linux-5.16/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts.56~ linux-5.16/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
---- linux-5.16/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts.56~	2022-01-10 12:04:19.877261533 +0100
-+++ linux-5.16/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts	2022-01-10 12:05:57.558561759 +0100
-@@ -384,10 +384,20 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&dc_det_pin>;
- 	};
-+
-+	typec_extcon_bridge: typec-extcon {
-+		compatible = "linux,typec-extcon-bridge";
-+		usb-role-switch;
-+		orientation-switch;
-+		mode-switch;
-+		svid = /bits/ 16 <0xff01>;
-+	};
- };
- 
- &cdn_dp {
- 	status = "okay";
-+	extcon = <&typec_extcon_bridge>;
-+	phys = <&tcphy0_dp>;
- };
- 
- &cpu_b0 {
-@@ -709,6 +719,8 @@
- 		pinctrl-names = "default";
- 		pinctrl-0 = <&fusb0_int_pin>;
- 		vbus-supply = <&vbus_typec>;
-+		extcon = <&typec_extcon_bridge>;
-+		usb-role-switch = <&typec_extcon_bridge>;
- 
- 		connector {
- 			compatible = "usb-c-connector";
-@@ -717,10 +729,20 @@
- 			op-sink-microwatt = <1000000>;
- 			power-role = "dual";
- 			sink-pdos =
--				<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
-+				<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>;
- 			source-pdos =
--				<PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
-+				<PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>;
- 			try-power-role = "sink";
-+			
-+			mode-switch = <&typec_extcon_bridge>;
-+			orientation-switch = <&typec_extcon_bridge>;
-+
-+			altmodes {
-+				dp {
-+					svid = <0xff01>;
-+					vdo = <0x0c0046>;
-+				};
-+			};
- 
- 			ports {
- 				#address-cells = <1>;
-@@ -988,6 +1010,7 @@
- };
- 
- &tcphy0 {
-+	extcon = <&typec_extcon_bridge>;
- 	status = "okay";
- };
- 
diff --git a/0014-drm-meson-add-YUV422-output-support.patch b/0014-drm-meson-add-YUV422-output-support.patch
deleted file mode 100644
index 921076b..0000000
--- a/0014-drm-meson-add-YUV422-output-support.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 6e5868cad185179d9354280db495760e2e0f572d Mon Sep 17 00:00:00 2001
-From: Dongjin Kim <tobetter@gmail.com>
-Date: Wed, 29 Jul 2020 04:05:03 +0900
-Subject: [PATCH] HACK: drm/meson: add YUV422 output support
-
-Support YUV422 output from the Amlogic Meson SoC VPU to the HDMI
-controller. This incorrectly fixes the green-line on GX devices.
-
-Signed-off-by: Dongjin Kim <tobetter@gmail.com>
----
- drivers/gpu/drm/meson/meson_dw_hdmi.c | 8 +++++++-
- 1 file changed, 7 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
-index aad75a22dc338..97d6700818242 100644
---- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
-+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
-@@ -703,6 +703,7 @@ dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
- 
- static const u32 meson_dw_hdmi_out_bus_fmts[] = {
- 	MEDIA_BUS_FMT_YUV8_1X24,
-+	MEDIA_BUS_FMT_UYVY8_1X16,
- 	MEDIA_BUS_FMT_UYYVYY8_0_5X24,
- };
- 
-@@ -802,7 +803,8 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_bridge *bridge,
- 	if (dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) {
- 		ycrcb_map = VPU_HDMI_OUTPUT_CRYCB;
- 		yuv420_mode = true;
--	}
-+	} else if (dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16)
-+		ycrcb_map = VPU_HDMI_OUTPUT_CRYCB;
- 
- 	/* VENC + VENC-DVI Mode setup */
- 	meson_venc_hdmi_mode_set(priv, vic, ycrcb_map, yuv420_mode, mode);
-@@ -814,6 +816,10 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_bridge *bridge,
- 		/* Setup YUV420 to HDMI-TX, no 10bit diphering */
- 		writel_relaxed(2 | (2 << 2),
- 			       priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
-+	else if (dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16)
-+		/* Setup YUV422 to HDMI-TX, no 10bit diphering */
-+		writel_relaxed(1 | (2 << 2),
-+				priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
- 	else
- 		/* Setup YUV444 to HDMI-TX, no 10bit diphering */
- 		writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
- 
diff --git a/0015-drm-meson-add-YUV422-output-support.patch b/0015-drm-meson-add-YUV422-output-support.patch
deleted file mode 100644
index 921076b..0000000
--- a/0015-drm-meson-add-YUV422-output-support.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 6e5868cad185179d9354280db495760e2e0f572d Mon Sep 17 00:00:00 2001
-From: Dongjin Kim <tobetter@gmail.com>
-Date: Wed, 29 Jul 2020 04:05:03 +0900
-Subject: [PATCH] HACK: drm/meson: add YUV422 output support
-
-Support YUV422 output from the Amlogic Meson SoC VPU to the HDMI
-controller. This incorrectly fixes the green-line on GX devices.
-
-Signed-off-by: Dongjin Kim <tobetter@gmail.com>
----
- drivers/gpu/drm/meson/meson_dw_hdmi.c | 8 +++++++-
- 1 file changed, 7 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
-index aad75a22dc338..97d6700818242 100644
---- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
-+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
-@@ -703,6 +703,7 @@ dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
- 
- static const u32 meson_dw_hdmi_out_bus_fmts[] = {
- 	MEDIA_BUS_FMT_YUV8_1X24,
-+	MEDIA_BUS_FMT_UYVY8_1X16,
- 	MEDIA_BUS_FMT_UYYVYY8_0_5X24,
- };
- 
-@@ -802,7 +803,8 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_bridge *bridge,
- 	if (dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) {
- 		ycrcb_map = VPU_HDMI_OUTPUT_CRYCB;
- 		yuv420_mode = true;
--	}
-+	} else if (dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16)
-+		ycrcb_map = VPU_HDMI_OUTPUT_CRYCB;
- 
- 	/* VENC + VENC-DVI Mode setup */
- 	meson_venc_hdmi_mode_set(priv, vic, ycrcb_map, yuv420_mode, mode);
-@@ -814,6 +816,10 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_bridge *bridge,
- 		/* Setup YUV420 to HDMI-TX, no 10bit diphering */
- 		writel_relaxed(2 | (2 << 2),
- 			       priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
-+	else if (dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16)
-+		/* Setup YUV422 to HDMI-TX, no 10bit diphering */
-+		writel_relaxed(1 | (2 << 2),
-+				priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
- 	else
- 		/* Setup YUV444 to HDMI-TX, no 10bit diphering */
- 		writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
- 
diff --git a/0016-add-ugoos-device.patch b/0016-add-ugoos-device.patch
deleted file mode 100644
index eff8323..0000000
--- a/0016-add-ugoos-device.patch
+++ /dev/null
@@ -1,205 +0,0 @@
-diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
---- a/arch/arm64/boot/dts/amlogic/Makefile	2020-12-24 23:21:13.460543131 +0300
-+++ b/arch/arm64/boot/dts/amlogic/Makefile	2020-12-24 23:21:13.460543131 +0300
-@@ -11,6 +11,7 @@
- dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb
-+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6-plus.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
-
- 
-diff --git /dev/null b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6-plus.dts
---- /dev/null	2020-12-24 23:21:13.460543131 +0300
-+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6-plus.dts	2020-12-24 23:21:13.460543131 +0300
-@@ -0,0 +1,188 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2019 BayLibre, SAS
-+ * Author: Neil Armstrong <narmstrong@baylibre.com>
-+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
-+ */
-+
-+/dts-v1/;
-+
-+#include "meson-g12b-w400.dtsi"
-+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-+
-+/ {
-+	compatible = "ugoos,am6", "amlogic,s922x", "amlogic,g12b";
-+	model = "Ugoos AM6 Plus";
-+
-+	spdif_dit: audio-codec-1 {
-+		#sound-dai-cells = <0>;
-+		compatible = "linux,spdif-dit";
-+		status = "okay";
-+		sound-name-prefix = "DIT";
-+	};
-+
-+	sound {
-+		compatible = "amlogic,axg-sound-card";
-+		model = "AM6-PLUS";
-+		audio-aux-devs = <&tdmout_b>;
-+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
-+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
-+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",
-+				"TDM_B Playback", "TDMOUT_B OUT",
-+				"SPDIFOUT IN 0", "FRDDR_A OUT 3",
-+				"SPDIFOUT IN 1", "FRDDR_B OUT 3",
-+				"SPDIFOUT IN 2", "FRDDR_C OUT 3";
-+
-+		assigned-clocks = <&clkc CLKID_MPLL2>,
-+				  <&clkc CLKID_MPLL0>,
-+				  <&clkc CLKID_MPLL1>;
-+		assigned-clock-parents = <0>, <0>, <0>;
-+		assigned-clock-rates = <294912000>,
-+				       <270950400>,
-+				       <393216000>;
-+		status = "okay";
-+
-+		dai-link-0 {
-+			sound-dai = <&frddr_a>;
-+		};
-+
-+		dai-link-1 {
-+			sound-dai = <&frddr_b>;
-+		};
-+
-+		dai-link-2 {
-+			sound-dai = <&frddr_c>;
-+		};
-+
-+		/* 8ch hdmi interface */
-+		dai-link-3 {
-+			sound-dai = <&tdmif_b>;
-+			dai-format = "i2s";
-+			dai-tdm-slot-tx-mask-0 = <1 1>;
-+			dai-tdm-slot-tx-mask-1 = <1 1>;
-+			dai-tdm-slot-tx-mask-2 = <1 1>;
-+			dai-tdm-slot-tx-mask-3 = <1 1>;
-+			mclk-fs = <256>;
-+
-+			codec {
-+				sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
-+			};
-+		};
-+
-+		/* spdif hdmi or toslink interface */
-+		dai-link-4 {
-+			sound-dai = <&spdifout>;
-+
-+			codec-0 {
-+				sound-dai = <&spdif_dit>;
-+			};
-+
-+			codec-1 {
-+				sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>;
-+			};
-+		};
-+
-+		/* spdif hdmi interface */
-+		dai-link-5 {
-+			sound-dai = <&spdifout_b>;
-+
-+			codec {
-+				sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>;
-+			};
-+		};
-+
-+		/* hdmi glue */
-+		dai-link-6 {
-+			sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-+
-+			codec {
-+				sound-dai = <&hdmi_tx>;
-+			};
-+		};
-+	};
-+};
-+
-+&arb {
-+	status = "okay";
-+};
-+
-+&clkc_audio {
-+	status = "okay";
-+};
-+
-+&frddr_a {
-+	status = "okay";
-+};
-+
-+&frddr_b {
-+	status = "okay";
-+};
-+
-+&frddr_c {
-+	status = "okay";
-+};
-+
-+&ir {
-+	linux,rc-map-name = "rc-khadas";
-+};
-+
-+&spdifout {
-+	pinctrl-0 = <&spdif_out_h_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
-+&spdifout_b {
-+	status = "okay";
-+};
-+
-+&tdmif_b {
-+	status = "okay";
-+};
-+
-+&tdmout_b {
-+	status = "okay";
-+};
-+
-+&tohdmitx {
-+	status = "okay";
-+};
-+
-+&uart_A {
-+	status = "okay";
-+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
-+	pinctrl-names = "default";
-+	uart-has-rtscts;
-+
-+	bluetooth {
-+		compatible = "brcm,bcm43438-bt";
-+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
-+		max-speed = <2000000>;
-+		clocks = <&wifi32k>;
-+	clock-names = "lpo";
-+	};
-+};
-+
-+&uart_AO {
-+	status = "okay";
-+	pinctrl-0 = <&uart_ao_a_pins>;
-+	pinctrl-names = "default";
-+};
-+
-+&usb {
-+	status = "okay";
-+	dr_mode = "host";
-+	vbus-supply = <&usb_pwr_en>;
-+};
-+
-+&usb2_phy0 {
-+	phy-supply = <&usb1_pow>;
-+};
-+
-+&usb2_phy1 {
-+	phy-supply = <&usb1_pow>;
-+};
-+
-+&sd_emmc_a {
-+	max-frequency = <45454545>;
-+};
diff --git a/0016-arm64-dts-meson-add-initial-Beelink-GT1-Ultimate-dev.patch b/0016-arm64-dts-meson-add-initial-Beelink-GT1-Ultimate-dev.patch
deleted file mode 100644
index 1dca2ce..0000000
--- a/0016-arm64-dts-meson-add-initial-Beelink-GT1-Ultimate-dev.patch
+++ /dev/null
@@ -1,427 +0,0 @@
-From 7f03ac7b6da2944d338dfd171fddfb5448046be3 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Mon, 15 Nov 2021 00:00:54 +0100
-Subject: [PATCH] arm64: dts: meson: add initial Beelink GT1 Ultimate device
- tree
-
-Signed-off-by: Dan Johansen <strit@manjaro.org>
----
- arch/arm64/boot/dts/amlogic/Makefile          |   1 +
- .../dts/amlogic/meson-gxm-gt1-ultimate.dts    | 393 ++++++++++++++++++
- 2 files changed, 394 insertions(+)
- create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-gt1-ultimate.dts
-
-diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
-index 5148cd9e5146..e44d60939bba 100644
---- a/arch/arm64/boot/dts/amlogic/Makefile
-+++ b/arch/arm64/boot/dts/amlogic/Makefile
-@@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-jethome-jethub-j80.dtb
-+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-gt1-ultimate.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxm-mecool-kiii-pro.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxm-minix-neo-u9h.dtb
-diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-gt1-ultimate.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-gt1-ultimate.dts
-new file mode 100644
-index 000000000000..052c8d266110
---- /dev/null
-+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-gt1-ultimate.dts
-@@ -0,0 +1,393 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
-+ * Copyright (c) 2017 BayLibre, SAS
-+ * Author: Neil Armstrong <narmstrong@baylibre.com>
-+ */
-+
-+/dts-v1/;
-+
-+#include "meson-gxm.dtsi"
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/sound/meson-aiu.h>
-+
-+/ {
-+	compatible = "azw,gt1ultimate", "amlogic,s912", "amlogic,meson-gxm";
-+	model = "Beelink GT1 Ultimate";
-+
-+	aliases {
-+		serial0 = &uart_AO;
-+		serial2 = &uart_AO_B;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	memory@0 {
-+		device_type = "memory";
-+		reg = <0x0 0x0 0x0 0x80000000>;
-+	};
-+
-+	adc-keys {
-+		compatible = "adc-keys";
-+		io-channels = <&saradc 0>;
-+		io-channel-names = "buttons";
-+		keyup-threshold-microvolt = <1710000>;
-+
-+		button-function {
-+			label = "Function";
-+			linux,code = <KEY_FN>;
-+			press-threshold-microvolt = <10000>;
-+		};
-+	};
-+
-+	emmc_pwrseq: emmc-pwrseq {
-+		compatible = "mmc-pwrseq-emmc";
-+		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
-+	};
-+
-+	gpio-keys-polled {
-+		compatible = "gpio-keys-polled";
-+		poll-interval = <100>;
-+
-+		power-button {
-+			label = "power";
-+			linux,code = <KEY_POWER>;
-+			gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+
-+	hdmi-connector {
-+		compatible = "hdmi-connector";
-+		type = "a";
-+
-+		port {
-+			hdmi_connector_in: endpoint {
-+				remote-endpoint = <&hdmi_tx_tmds_out>;
-+			};
-+		};
-+	};
-+
-+	pwmleds {
-+		compatible = "pwm-leds";
-+
-+		power {
-+			label = "vim:red:power";
-+			pwms = <&pwm_AO_ab 1 7812500 0>;
-+			max-brightness = <255>;
-+			linux,default-trigger = "default-on";
-+		};
-+	};
-+
-+	sdio_pwrseq: sdio-pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
-+		clocks = <&wifi32k>;
-+		clock-names = "ext_clock";
-+	};
-+
-+	hdmi_5v: regulator-hdmi-5v {
-+		compatible = "regulator-fixed";
-+
-+		regulator-name = "HDMI_5V";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+
-+		gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
-+		enable-active-high;
-+		regulator-always-on;
-+	};
-+
-+	vcc_3v3: regulator-vcc_3v3 {
-+		compatible = "regulator-fixed";
-+		regulator-name = "VCC_3V3";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+	};
-+
-+	vddio_ao18: regulator-vddio_ao18 {
-+		compatible = "regulator-fixed";
-+		regulator-name = "VDDIO_AO18";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+	};
-+
-+	vddio_boot: regulator-vddio_boot {
-+		compatible = "regulator-fixed";
-+		regulator-name = "VDDIO_BOOT";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+	};
-+
-+	vddao_3v3: regulator-vddao_3v3 {
-+		compatible = "regulator-fixed";
-+		regulator-name = "VDDAO_3V3";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+	};
-+
-+	wifi32k: wifi32k {
-+		compatible = "pwm-clock";
-+		#clock-cells = <0>;
-+		clock-frequency = <32768>;
-+		pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
-+	};
-+
-+	sound {
-+		compatible = "amlogic,gx-sound-card";
-+		model = "GT1-ULTIMATE";
-+		assigned-clocks = <&clkc CLKID_MPLL0>,
-+				  <&clkc CLKID_MPLL1>,
-+				  <&clkc CLKID_MPLL2>;
-+		assigned-clock-parents = <0>, <0>, <0>;
-+		assigned-clock-rates = <294912000>,
-+				       <270950400>,
-+				       <393216000>;
-+		status = "okay";
-+
-+		dai-link-0 {
-+			sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
-+		};
-+
-+		dai-link-1 {
-+			sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
-+			dai-format = "i2s";
-+			mclk-fs = <256>;
-+
-+			codec-0 {
-+				sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
-+			};
-+		};
-+
-+		dai-link-2 {
-+			sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
-+
-+			codec-0 {
-+				sound-dai = <&hdmi_tx>;
-+			};
-+		};
-+	};
-+};
-+
-+&aiu {
-+	status = "okay";
-+};
-+
-+&cec_AO {
-+	status = "okay";
-+	pinctrl-0 = <&ao_cec_pins>;
-+	pinctrl-names = "default";
-+	hdmi-phandle = <&hdmi_tx>;
-+};
-+
-+&ethmac {
-+	pinctrl-0 = <&eth_pins>;
-+	pinctrl-names = "default";
-+
-+	/* Select external PHY by default */
-+	phy-handle = <&external_phy>;
-+
-+	amlogic,tx-delay-ns = <2>;
-+
-+	/* External PHY is in RGMII */
-+	phy-mode = "rgmii";
-+
-+	status = "okay";
-+};
-+
-+&external_mdio {
-+	external_phy: ethernet-phy@0 {
-+		/* Realtek RTL8211F (0x001cc916) */
-+		reg = <0>;
-+
-+		reset-assert-us = <10000>;
-+		reset-deassert-us = <80000>;
-+		reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
-+
-+		interrupt-parent = <&gpio_intc>;
-+		/* MAC_INTR on GPIOZ_15 */
-+		interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
-+	};
-+};
-+
-+&hdmi_tx {
-+	status = "okay";
-+	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
-+	pinctrl-names = "default";
-+	hdmi-supply = <&hdmi_5v>;
-+};
-+
-+&hdmi_tx_tmds_port {
-+	hdmi_tx_tmds_out: endpoint {
-+		remote-endpoint = <&hdmi_connector_in>;
-+	};
-+};
-+
-+&i2c_A {
-+	status = "okay";
-+	pinctrl-0 = <&i2c_a_pins>;
-+	pinctrl-names = "default";
-+};
-+
-+&i2c_B {
-+	status = "okay";
-+	pinctrl-0 = <&i2c_b_pins>;
-+	pinctrl-names = "default";
-+
-+	rtc: rtc@51 {
-+		status = "okay";
-+		compatible = "haoyu,hym8563";
-+		reg = <0x51>;
-+		#clock-cells = <0>;
-+		clock-frequency = <32768>;
-+		clock-output-names = "xin32k";
-+	};
-+};
-+
-+&ir {
-+	status = "okay";
-+	pinctrl-0 = <&remote_input_ao_pins>;
-+	pinctrl-names = "default";
-+	linux,rc-map-name = "rc-khadas";
-+};
-+
-+&pwm_AO_ab {
-+	status = "okay";
-+	pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
-+	pinctrl-names = "default";
-+	clocks = <&clkc CLKID_FCLK_DIV4>;
-+	clock-names = "clkin0";
-+};
-+
-+&pwm_ef {
-+	status = "okay";
-+	pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>;
-+	pinctrl-names = "default";
-+	clocks = <&clkc CLKID_FCLK_DIV4>;
-+	clock-names = "clkin0";
-+};
-+
-+&sd_emmc_a {
-+	status = "okay";
-+	pinctrl-0 = <&sdio_pins>;
-+	pinctrl-1 = <&sdio_clk_gate_pins>;
-+	pinctrl-names = "default", "clk-gate";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	bus-width = <4>;
-+	max-frequency = <60000000>;
-+
-+	non-removable;
-+	disable-wp;
-+
-+	/* WiFi firmware requires power to be kept while in suspend */
-+	keep-power-in-suspend;
-+
-+	mmc-pwrseq = <&sdio_pwrseq>;
-+
-+	vmmc-supply = <&vddao_3v3>;
-+	vqmmc-supply = <&vddio_boot>;
-+
-+	brcmf: wifi@1 {
-+		reg = <1>;
-+		compatible = "brcm,bcm4329-fmac";
-+	};
-+};
-+
-+/* SD card */
-+&sd_emmc_b {
-+	status = "okay";
-+	pinctrl-0 = <&sdcard_pins>;
-+	pinctrl-1 = <&sdcard_clk_gate_pins>;
-+	pinctrl-names = "default", "clk-gate";
-+
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	max-frequency = <50000000>;
-+	disable-wp;
-+
-+	cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
-+
-+	vmmc-supply = <&vddao_3v3>;
-+	vqmmc-supply = <&vddio_boot>;
-+};
-+
-+/* eMMC */
-+&sd_emmc_c {
-+	status = "okay";
-+	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
-+	pinctrl-1 = <&emmc_clk_gate_pins>;
-+	pinctrl-names = "default", "clk-gate";
-+
-+	bus-width = <8>;
-+	cap-mmc-highspeed;
-+	max-frequency = <200000000>;
-+	non-removable;
-+	disable-wp;
-+	mmc-ddr-1_8v;
-+	mmc-hs200-1_8v;
-+
-+	mmc-pwrseq = <&emmc_pwrseq>;
-+	vmmc-supply = <&vcc_3v3>;
-+	vqmmc-supply = <&vddio_boot>;
-+};
-+
-+/*
-+ * EMMC_DS pin is shared between SPI NOR CS and eMMC Data Strobe
-+ * Remove emmc_ds_pins from sd_emmc_c pinctrl-0 then spifc can be enabled
-+ */
-+&spifc {
-+	status = "disabled";
-+	pinctrl-0 = <&nor_pins>;
-+	pinctrl-names = "default";
-+
-+	w25q32: spi-flash@0 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		compatible = "winbond,w25q16", "jedec,spi-nor";
-+		reg = <0>;
-+		spi-max-frequency = <104000000>;
-+	};
-+};
-+
-+/* This one is connected to the Bluetooth module */
-+&uart_A {
-+	status = "okay";
-+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
-+	pinctrl-names = "default";
-+	uart-has-rtscts;
-+
-+	bluetooth {
-+		compatible = "brcm,bcm43438-bt";
-+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
-+		max-speed = <2000000>;
-+		clocks = <&wifi32k>;
-+		clock-names = "lpo";
-+	};
-+};
-+
-+/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */
-+&uart_AO {
-+	status = "okay";
-+	pinctrl-0 = <&uart_ao_a_pins>;
-+	pinctrl-names = "default";
-+};
-+
-+/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */
-+&uart_AO_B {
-+	status = "okay";
-+	pinctrl-0 = <&uart_ao_b_pins>;
-+	pinctrl-names = "default";
-+};
-+
-+&saradc {
-+	status = "okay";
-+	vref-supply = <&vddio_ao18>;
-+};
-+
-+&usb {
-+	status = "okay";
-+	dr_mode = "peripheral";
-+}; 
--- 
-2.33.0
-
diff --git a/0017-add-ugoos-device.patch b/0017-add-ugoos-device.patch
deleted file mode 100644
index eff8323..0000000
--- a/0017-add-ugoos-device.patch
+++ /dev/null
@@ -1,205 +0,0 @@
-diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
---- a/arch/arm64/boot/dts/amlogic/Makefile	2020-12-24 23:21:13.460543131 +0300
-+++ b/arch/arm64/boot/dts/amlogic/Makefile	2020-12-24 23:21:13.460543131 +0300
-@@ -11,6 +11,7 @@
- dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb
-+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6-plus.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
- dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
-
- 
-diff --git /dev/null b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6-plus.dts
---- /dev/null	2020-12-24 23:21:13.460543131 +0300
-+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6-plus.dts	2020-12-24 23:21:13.460543131 +0300
-@@ -0,0 +1,188 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2019 BayLibre, SAS
-+ * Author: Neil Armstrong <narmstrong@baylibre.com>
-+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
-+ */
-+
-+/dts-v1/;
-+
-+#include "meson-g12b-w400.dtsi"
-+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-+
-+/ {
-+	compatible = "ugoos,am6", "amlogic,s922x", "amlogic,g12b";
-+	model = "Ugoos AM6 Plus";
-+
-+	spdif_dit: audio-codec-1 {
-+		#sound-dai-cells = <0>;
-+		compatible = "linux,spdif-dit";
-+		status = "okay";
-+		sound-name-prefix = "DIT";
-+	};
-+
-+	sound {
-+		compatible = "amlogic,axg-sound-card";
-+		model = "AM6-PLUS";
-+		audio-aux-devs = <&tdmout_b>;
-+		audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
-+				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
-+				"TDMOUT_B IN 2", "FRDDR_C OUT 1",
-+				"TDM_B Playback", "TDMOUT_B OUT",
-+				"SPDIFOUT IN 0", "FRDDR_A OUT 3",
-+				"SPDIFOUT IN 1", "FRDDR_B OUT 3",
-+				"SPDIFOUT IN 2", "FRDDR_C OUT 3";
-+
-+		assigned-clocks = <&clkc CLKID_MPLL2>,
-+				  <&clkc CLKID_MPLL0>,
-+				  <&clkc CLKID_MPLL1>;
-+		assigned-clock-parents = <0>, <0>, <0>;
-+		assigned-clock-rates = <294912000>,
-+				       <270950400>,
-+				       <393216000>;
-+		status = "okay";
-+
-+		dai-link-0 {
-+			sound-dai = <&frddr_a>;
-+		};
-+
-+		dai-link-1 {
-+			sound-dai = <&frddr_b>;
-+		};
-+
-+		dai-link-2 {
-+			sound-dai = <&frddr_c>;
-+		};
-+
-+		/* 8ch hdmi interface */
-+		dai-link-3 {
-+			sound-dai = <&tdmif_b>;
-+			dai-format = "i2s";
-+			dai-tdm-slot-tx-mask-0 = <1 1>;
-+			dai-tdm-slot-tx-mask-1 = <1 1>;
-+			dai-tdm-slot-tx-mask-2 = <1 1>;
-+			dai-tdm-slot-tx-mask-3 = <1 1>;
-+			mclk-fs = <256>;
-+
-+			codec {
-+				sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
-+			};
-+		};
-+
-+		/* spdif hdmi or toslink interface */
-+		dai-link-4 {
-+			sound-dai = <&spdifout>;
-+
-+			codec-0 {
-+				sound-dai = <&spdif_dit>;
-+			};
-+
-+			codec-1 {
-+				sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>;
-+			};
-+		};
-+
-+		/* spdif hdmi interface */
-+		dai-link-5 {
-+			sound-dai = <&spdifout_b>;
-+
-+			codec {
-+				sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>;
-+			};
-+		};
-+
-+		/* hdmi glue */
-+		dai-link-6 {
-+			sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-+
-+			codec {
-+				sound-dai = <&hdmi_tx>;
-+			};
-+		};
-+	};
-+};
-+
-+&arb {
-+	status = "okay";
-+};
-+
-+&clkc_audio {
-+	status = "okay";
-+};
-+
-+&frddr_a {
-+	status = "okay";
-+};
-+
-+&frddr_b {
-+	status = "okay";
-+};
-+
-+&frddr_c {
-+	status = "okay";
-+};
-+
-+&ir {
-+	linux,rc-map-name = "rc-khadas";
-+};
-+
-+&spdifout {
-+	pinctrl-0 = <&spdif_out_h_pins>;
-+	pinctrl-names = "default";
-+	status = "okay";
-+};
-+
-+&spdifout_b {
-+	status = "okay";
-+};
-+
-+&tdmif_b {
-+	status = "okay";
-+};
-+
-+&tdmout_b {
-+	status = "okay";
-+};
-+
-+&tohdmitx {
-+	status = "okay";
-+};
-+
-+&uart_A {
-+	status = "okay";
-+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
-+	pinctrl-names = "default";
-+	uart-has-rtscts;
-+
-+	bluetooth {
-+		compatible = "brcm,bcm43438-bt";
-+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
-+		max-speed = <2000000>;
-+		clocks = <&wifi32k>;
-+	clock-names = "lpo";
-+	};
-+};
-+
-+&uart_AO {
-+	status = "okay";
-+	pinctrl-0 = <&uart_ao_a_pins>;
-+	pinctrl-names = "default";
-+};
-+
-+&usb {
-+	status = "okay";
-+	dr_mode = "host";
-+	vbus-supply = <&usb_pwr_en>;
-+};
-+
-+&usb2_phy0 {
-+	phy-supply = <&usb1_pow>;
-+};
-+
-+&usb2_phy1 {
-+	phy-supply = <&usb1_pow>;
-+};
-+
-+&sd_emmc_a {
-+	max-frequency = <45454545>;
-+};
diff --git a/0018-drm-bridge-dw-hdmi-disable-loading-of-DW-HDMI-CEC-sub-driver.patch b/0018-drm-bridge-dw-hdmi-disable-loading-of-DW-HDMI-CEC-sub-driver.patch
deleted file mode 100644
index b87cb99..0000000
--- a/0018-drm-bridge-dw-hdmi-disable-loading-of-DW-HDMI-CEC-sub-driver.patch
+++ /dev/null
@@ -1,295 +0,0 @@
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-From: Neil Armstrong <narmstrong@baylibre.com>
-To: jonas@kwiboo.se, jernej.skrabec@siol.net, robert.foss@linaro.org,
- Laurent.pinchart@ideasonboard.com
-Subject: [PATCH 1/2] drm/bridge/synopsys: dw-hdmi: Add an option to suppress
- loading CEC driver
-Date: Fri, 16 Apr 2021 11:27:36 +0200
-Message-Id: <20210416092737.1971876-2-narmstrong@baylibre.com>
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-Cc: linux-amlogic@lists.infradead.org,
- Neil Armstrong <narmstrong@baylibre.com>,
- linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org,
- linux-kernel@vger.kernel.org
-Errors-To: dri-devel-bounces@lists.freedesktop.org
-Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org>
-
-From: Jernej Skrabec <jernej.skrabec@siol.net>
-
-This adds DW-HDMI driver a glue option to disable loading of the CEC sub-driver.
-
-On some SoCs, the CEC functionality is enabled in the IP config bits, but the
-CEC bus is non-functional like on Amlogic SoCs, where the CEC config bit is set
-but the DW-HDMI CEC signal is not connected to a physical pin, leading to some
-confusion when the DW-HDMI CEC controller can't communicate on the bus.
-
-Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
-Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +-
- include/drm/bridge/dw_hdmi.h              | 2 ++
- 2 files changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
-index dda4fa9a1a08..ae97513ef886 100644
---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
-+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
-@@ -3421,7 +3421,7 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
- 		hdmi->audio = platform_device_register_full(&pdevinfo);
- 	}
- 
--	if (config0 & HDMI_CONFIG0_CEC) {
-+	if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) {
- 		cec.hdmi = hdmi;
- 		cec.ops = &dw_hdmi_cec_ops;
- 		cec.irq = irq;
-diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
-index ea34ca146b82..6a5716655619 100644
---- a/include/drm/bridge/dw_hdmi.h
-+++ b/include/drm/bridge/dw_hdmi.h
-@@ -153,6 +153,8 @@ struct dw_hdmi_plat_data {
- 	const struct dw_hdmi_phy_config *phy_config;
- 	int (*configure_phy)(struct dw_hdmi *hdmi, void *data,
- 			     unsigned long mpixelclock);
-+
-+	unsigned int disable_cec : 1;
- };
- 
- struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
-
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- Fri, 16 Apr 2021 02:27:43 -0700 (PDT)
-From: Neil Armstrong <narmstrong@baylibre.com>
-To: jonas@kwiboo.se, jernej.skrabec@siol.net, robert.foss@linaro.org,
- Laurent.pinchart@ideasonboard.com
-Subject: [PATCH 2/2] drm/meson: dw-hdmi: disable DW-HDMI CEC sub-driver
-Date: Fri, 16 Apr 2021 11:27:37 +0200
-Message-Id: <20210416092737.1971876-3-narmstrong@baylibre.com>
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-Cc: linux-amlogic@lists.infradead.org,
- Neil Armstrong <narmstrong@baylibre.com>,
- linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org,
- linux-kernel@vger.kernel.org
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-
-On the Amlogic SoCs, the DW-HDMI HW support is here but the DW-HDMI CEC signal
-is not connected to a physical pin, leading to confusion when the dw-hdmi cec
-controller can't communicate on the bus.
-
-Disable it to avoid exposing a non-functinal bus.
-
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
----
- drivers/gpu/drm/meson/meson_dw_hdmi.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
-index aad75a22dc33..2ed87cfdd735 100644
---- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
-+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
-@@ -1103,6 +1103,7 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
- 	dw_plat_data->phy_data = meson_dw_hdmi;
- 	dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709;
- 	dw_plat_data->ycbcr_420_allowed = true;
-+	dw_plat_data->disable_cec = true;
- 
- 	if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
- 	    dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||
diff --git a/0018-drm-panfrost-scheduler-fix.patch b/0018-drm-panfrost-scheduler-fix.patch
deleted file mode 100644
index 3efd213..0000000
--- a/0018-drm-panfrost-scheduler-fix.patch
+++ /dev/null
@@ -1,109 +0,0 @@
-diff -pruN -X linux-5.15-rc1-ORIG/Documentation/dontdiff linux-5.15-rc1-ORIG/drivers/gpu/drm/panfrost/panfrost_job.c linux-5.15-rc1-panfrost/drivers/gpu/drm/panfrost/panfrost_job.c
---- linux-5.15-rc1-ORIG/drivers/gpu/drm/panfrost/panfrost_job.c	2021-09-13 01:28:37.000000000 +0200
-+++ linux-5.15-rc1-panfrost/drivers/gpu/drm/panfrost/panfrost_job.c	2021-09-17 17:47:38.287735915 +0200
-@@ -234,7 +234,7 @@ static void panfrost_job_hw_submit(struc
- 	if (!atomic_read(&pfdev->reset.pending)) {
- 		job_write(pfdev, JS_COMMAND_NEXT(js), JS_COMMAND_START);
- 		dev_dbg(pfdev->dev,
--			"JS: Submitting atom %p to js[%d][%d] with head=0x%llx AS %d",
-+			"Job slot: submitting atom %p to js[%d][%d] with head=0x%llx, as=%d\n",
- 			job, js, subslot, jc_head, cfg & 0xf);
- 	}
- 	spin_unlock(&pfdev->js->job_lock);
-@@ -425,12 +425,12 @@ static void panfrost_job_handle_err(stru
- 	bool signal_fence = true;
- 
- 	if (!panfrost_exception_is_fault(js_status)) {
--		dev_dbg(pfdev->dev, "js event, js=%d, status=%s, head=0x%x, tail=0x%x",
-+		dev_dbg(pfdev->dev, "Job slot event: js=%d, status=%s, head=0x%x, tail=0x%x\n",
- 			js, exception_name,
- 			job_read(pfdev, JS_HEAD_LO(js)),
- 			job_read(pfdev, JS_TAIL_LO(js)));
- 	} else {
--		dev_err(pfdev->dev, "js fault, js=%d, status=%s, head=0x%x, tail=0x%x",
-+		dev_err(pfdev->dev, "Job slot fault: js=%d, status=%s, head=0x%x, tail=0x%x\n",
- 			js, exception_name,
- 			job_read(pfdev, JS_HEAD_LO(js)),
- 			job_read(pfdev, JS_TAIL_LO(js)));
-@@ -671,7 +671,7 @@ panfrost_reset(struct panfrost_device *p
- 				 10, 10000);
- 
- 	if (ret)
--		dev_err(pfdev->dev, "Soft-stop failed\n");
-+		dev_err(pfdev->dev, "Failed to complete soft-stop: %d\n", ret);
- 
- 	/* Handle the remaining interrupts before we reset. */
- 	panfrost_job_handle_irqs(pfdev);
-@@ -740,7 +740,7 @@ static enum drm_gpu_sched_stat panfrost_
- 	if (dma_fence_is_signaled(job->done_fence))
- 		return DRM_GPU_SCHED_STAT_NOMINAL;
- 
--	dev_err(pfdev->dev, "gpu sched timeout, js=%d, config=0x%x, status=0x%x, head=0x%x, tail=0x%x, sched_job=%p",
-+	dev_err(pfdev->dev, "GPU scheduler timeout: js=%d, config=0x%x, status=0x%x, head=0x%x, tail=0x%x, sched_job=%p\n",
- 		js,
- 		job_read(pfdev, JS_CONFIG(js)),
- 		job_read(pfdev, JS_STATUS(js)),
-@@ -822,7 +822,7 @@ int panfrost_job_init(struct panfrost_de
- 					IRQF_SHARED, KBUILD_MODNAME "-job",
- 					pfdev);
- 	if (ret) {
--		dev_err(pfdev->dev, "failed to request job irq");
-+		dev_err(pfdev->dev, "Failed to request job IRQ: %d\n", ret);
- 		return ret;
- 	}
- 
-@@ -840,7 +840,7 @@ int panfrost_job_init(struct panfrost_de
- 				     pfdev->reset.wq,
- 				     NULL, "pan_js");
- 		if (ret) {
--			dev_err(pfdev->dev, "Failed to create scheduler: %d.", ret);
-+			dev_err(pfdev->dev, "Failed to create scheduler: %d\n", ret);
- 			goto err_sched;
- 		}
- 	}
-diff -pruN -X linux-5.15-rc1-ORIG/Documentation/dontdiff linux-5.15-rc1-ORIG/drivers/gpu/drm/scheduler/sched_main.c linux-5.15-rc1-panfrost/drivers/gpu/drm/scheduler/sched_main.c
---- linux-5.15-rc1-ORIG/drivers/gpu/drm/scheduler/sched_main.c	2021-09-13 01:28:37.000000000 +0200
-+++ linux-5.15-rc1-panfrost/drivers/gpu/drm/scheduler/sched_main.c	2021-09-17 17:50:54.947121296 +0200
-@@ -489,8 +489,7 @@ void drm_sched_start(struct drm_gpu_sche
- 			if (r == -ENOENT)
- 				drm_sched_job_done(s_job);
- 			else if (r)
--				DRM_ERROR("fence add callback failed (%d)\n",
--					  r);
-+				DRM_ERROR("Failed to add fence callback: %d\n", r);
- 		} else
- 			drm_sched_job_done(s_job);
- 	}
-@@ -776,7 +775,7 @@ static int drm_sched_main(void *param)
- 	struct drm_gpu_scheduler *sched = (struct drm_gpu_scheduler *)param;
- 	int r;
- 
--	sched_set_fifo_low(current);
-+	sched_set_fifo(current);
- 
- 	while (!kthread_should_stop()) {
- 		struct drm_sched_entity *entity = NULL;
-@@ -824,13 +823,11 @@ static int drm_sched_main(void *param)
- 			if (r == -ENOENT)
- 				drm_sched_job_done(sched_job);
- 			else if (r)
--				DRM_ERROR("fence add callback failed (%d)\n",
--					  r);
-+				DRM_ERROR("Failed to add fence callback: %d\n", r);
- 			dma_fence_put(fence);
- 		} else {
- 			if (IS_ERR(fence))
- 				dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
--
- 			drm_sched_job_done(sched_job);
- 		}
- 
-@@ -885,7 +882,7 @@ int drm_sched_init(struct drm_gpu_schedu
- 	if (IS_ERR(sched->thread)) {
- 		ret = PTR_ERR(sched->thread);
- 		sched->thread = NULL;
--		DRM_ERROR("Failed to create scheduler for %s.\n", name);
-+		DRM_ERROR("Failed to create scheduler for %s: %d\n", name, ret);
- 		return ret;
- 	}
- 
diff --git a/0019-arm64-dts-rockchip-Add-pcie-bus-scan-delay-to-rockpr.patch b/0019-arm64-dts-rockchip-Add-pcie-bus-scan-delay-to-rockpr.patch
deleted file mode 100644
index 9a17503..0000000
--- a/0019-arm64-dts-rockchip-Add-pcie-bus-scan-delay-to-rockpr.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From b59f3f0adac345a962223e6e50b8bfbed603a879 Mon Sep 17 00:00:00 2001
-From: Dan Johansen <strit@manjaro.org>
-Date: Thu, 2 Sep 2021 09:44:47 +0200
-Subject: [PATCH] arm64: dts: rockchip: Add pcie bus scan delay to rockpro64
-
-Signed-off-by: Dan Johansen <strit@manjaro.org>
----
- arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
-index 6bff8db7d33e..ee1a52222b3e 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
-@@ -578,6 +578,7 @@ &pcie0 {
- 	pinctrl-0 = <&pcie_perst>;
- 	vpcie12v-supply = <&vcc12v_dcin>;
- 	vpcie3v3-supply = <&vcc3v3_pcie>;
-+    bus-scan-delay-ms = <1000>;
- 	status = "okay";
- };
- 
--- 
-2.33.0
-
diff --git a/0020-drm-rockchip-support-gamma-control-on-RK3399.patch b/0020-drm-rockchip-support-gamma-control-on-RK3399.patch
deleted file mode 100644
index 30c9fbf..0000000
--- a/0020-drm-rockchip-support-gamma-control-on-RK3399.patch
+++ /dev/null
@@ -1,667 +0,0 @@
-From patchwork Tue Oct 19 21:58:41 2021
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-From: Hugh Cole-Baker <sigmaris@gmail.com>
-To: heiko@sntech.de,
-	hjc@rock-chips.com
-Cc: dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org,
- linux-arm-kernel@lists.infradead.org, ezequiel@collabora.com,
- Hugh Cole-Baker <sigmaris@gmail.com>
-Subject: [PATCH v2 1/3] drm/rockchip: define gamma registers for RK3399
-Date: Tue, 19 Oct 2021 22:58:41 +0100
-Message-Id: <20211019215843.42718-2-sigmaris@gmail.com>
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-
-The VOP on RK3399 has a different approach from previous versions for
-setting a gamma lookup table, using an update_gamma_lut register. As
-this differs from RK3288, give RK3399 its own set of "common" register
-definitions.
-
-Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
----
-
-Changes from v1: no changes in this patch
-
- drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  2 ++
- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 24 +++++++++++++++++++--
- drivers/gpu/drm/rockchip/rockchip_vop_reg.h |  1 +
- 3 files changed, 25 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
-index 857d97cdc67c..14179e89bd21 100644
---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
-@@ -99,6 +99,8 @@ struct vop_common {
- 	struct vop_reg dither_down_en;
- 	struct vop_reg dither_up;
- 	struct vop_reg dsp_lut_en;
-+	struct vop_reg update_gamma_lut;
-+	struct vop_reg lut_buffer_index;
- 	struct vop_reg gate_en;
- 	struct vop_reg mmu_en;
- 	struct vop_reg out_mode;
-diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
-index ca7cc82125cb..bfb7e130f09b 100644
---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
-@@ -865,6 +865,24 @@ static const struct vop_output rk3399_output = {
- 	.mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3),
- };
- 
-+static const struct vop_common rk3399_common = {
-+	.standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22),
-+	.gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
-+	.mmu_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 20),
-+	.dither_down_sel = VOP_REG(RK3399_DSP_CTRL1, 0x1, 4),
-+	.dither_down_mode = VOP_REG(RK3399_DSP_CTRL1, 0x1, 3),
-+	.dither_down_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 2),
-+	.pre_dither_down = VOP_REG(RK3399_DSP_CTRL1, 0x1, 1),
-+	.dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
-+	.dsp_lut_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 0),
-+	.update_gamma_lut = VOP_REG(RK3399_DSP_CTRL1, 0x1, 7),
-+	.lut_buffer_index = VOP_REG(RK3399_DBG_POST_REG1, 0x1, 1),
-+	.data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
-+	.dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18),
-+	.out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
-+	.cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0),
-+};
-+
- static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = {
- 	.y2r_coefficients = {
- 		VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0),
-@@ -944,7 +962,7 @@ static const struct vop_data rk3399_vop_big = {
- 	.version = VOP_VERSION(3, 5),
- 	.feature = VOP_FEATURE_OUTPUT_RGB10,
- 	.intr = &rk3366_vop_intr,
--	.common = &rk3288_common,
-+	.common = &rk3399_common,
- 	.modeset = &rk3288_modeset,
- 	.output = &rk3399_output,
- 	.afbc = &rk3399_vop_afbc,
-@@ -952,6 +970,7 @@ static const struct vop_data rk3399_vop_big = {
- 	.win = rk3399_vop_win_data,
- 	.win_size = ARRAY_SIZE(rk3399_vop_win_data),
- 	.win_yuv2yuv = rk3399_vop_big_win_yuv2yuv_data,
-+	.lut_size = 1024,
- };
- 
- static const struct vop_win_data rk3399_vop_lit_win_data[] = {
-@@ -970,13 +989,14 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = {
- static const struct vop_data rk3399_vop_lit = {
- 	.version = VOP_VERSION(3, 6),
- 	.intr = &rk3366_vop_intr,
--	.common = &rk3288_common,
-+	.common = &rk3399_common,
- 	.modeset = &rk3288_modeset,
- 	.output = &rk3399_output,
- 	.misc = &rk3368_misc,
- 	.win = rk3399_vop_lit_win_data,
- 	.win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
- 	.win_yuv2yuv = rk3399_vop_lit_win_yuv2yuv_data,
-+	.lut_size = 256,
- };
- 
- static const struct vop_win_data rk3228_vop_win_data[] = {
-diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
-index 0b3cd65ba5c1..406e981c75bd 100644
---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
-+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
-@@ -628,6 +628,7 @@
- #define RK3399_YUV2YUV_WIN			0x02c0
- #define RK3399_YUV2YUV_POST			0x02c4
- #define RK3399_AUTO_GATING_EN			0x02cc
-+#define RK3399_DBG_POST_REG1			0x036c
- #define RK3399_WIN0_CSC_COE			0x03a0
- #define RK3399_WIN1_CSC_COE			0x03c0
- #define RK3399_WIN2_CSC_COE			0x03e0
-
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-From: Hugh Cole-Baker <sigmaris@gmail.com>
-To: heiko@sntech.de,
-	hjc@rock-chips.com
-Cc: dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org,
- linux-arm-kernel@lists.infradead.org, ezequiel@collabora.com,
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-Subject: [PATCH v2 2/3] drm/rockchip: support gamma control on RK3399
-Date: Tue, 19 Oct 2021 22:58:42 +0100
-Message-Id: <20211019215843.42718-3-sigmaris@gmail.com>
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-
-The RK3399 has a 1024-entry gamma LUT with 10 bits per component on its
-"big" VOP and a 256-entry, 8 bit per component LUT on the "little" VOP.
-Compared to the RK3288, it no longer requires disabling gamma while
-updating the LUT. On the RK3399, the LUT can be updated at any time as
-the hardware has two LUT buffers, one can be written while the other is
-in use. A swap of the buffers is triggered by writing 1 to the
-update_gamma_lut register.
-
-Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
----
-
-Changes from v1: Moved the vop_crtc_gamma_set call to the end of
-vop_crtc_atomic_enable after the clocks and CRTC are enabled.
-
- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 105 +++++++++++++-------
- 1 file changed, 71 insertions(+), 34 deletions(-)
-
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-index ba9e14da41b4..e2c97f1b26da 100644
---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-@@ -9,6 +9,7 @@
- #include <linux/delay.h>
- #include <linux/iopoll.h>
- #include <linux/kernel.h>
-+#include <linux/log2.h>
- #include <linux/module.h>
- #include <linux/of.h>
- #include <linux/of_device.h>
-@@ -66,6 +67,9 @@
- #define VOP_REG_SET(vop, group, name, v) \
- 		    vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
- 
-+#define VOP_HAS_REG(vop, group, name) \
-+		(!!(vop->data->group->name.mask))
-+
- #define VOP_INTR_SET_TYPE(vop, name, type, v) \
- 	do { \
- 		int i, reg = 0, mask = 0; \
-@@ -1204,17 +1208,22 @@ static bool vop_dsp_lut_is_enabled(struct vop *vop)
- 	return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);
- }
- 
-+static u32 vop_lut_buffer_index(struct vop *vop)
-+{
-+	return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index);
-+}
-+
- static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc)
- {
- 	struct drm_color_lut *lut = crtc->state->gamma_lut->data;
--	unsigned int i;
-+	unsigned int i, bpc = ilog2(vop->data->lut_size);
- 
- 	for (i = 0; i < crtc->gamma_size; i++) {
- 		u32 word;
- 
--		word = (drm_color_lut_extract(lut[i].red, 10) << 20) |
--		       (drm_color_lut_extract(lut[i].green, 10) << 10) |
--			drm_color_lut_extract(lut[i].blue, 10);
-+		word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) |
-+		       (drm_color_lut_extract(lut[i].green, bpc) << bpc) |
-+			drm_color_lut_extract(lut[i].blue, bpc);
- 		writel(word, vop->lut_regs + i * 4);
- 	}
- }
-@@ -1224,38 +1233,66 @@ static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc,
- {
- 	struct drm_crtc_state *state = crtc->state;
- 	unsigned int idle;
-+	u32 lut_idx, old_idx;
- 	int ret;
- 
- 	if (!vop->lut_regs)
- 		return;
--	/*
--	 * To disable gamma (gamma_lut is null) or to write
--	 * an update to the LUT, clear dsp_lut_en.
--	 */
--	spin_lock(&vop->reg_lock);
--	VOP_REG_SET(vop, common, dsp_lut_en, 0);
--	vop_cfg_done(vop);
--	spin_unlock(&vop->reg_lock);
- 
--	/*
--	 * In order to write the LUT to the internal memory,
--	 * we need to first make sure the dsp_lut_en bit is cleared.
--	 */
--	ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,
--				 idle, !idle, 5, 30 * 1000);
--	if (ret) {
--		DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");
--		return;
--	}
-+	if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) {
-+		/*
-+		 * To disable gamma (gamma_lut is null) or to write
-+		 * an update to the LUT, clear dsp_lut_en.
-+		 */
-+		spin_lock(&vop->reg_lock);
-+		VOP_REG_SET(vop, common, dsp_lut_en, 0);
-+		vop_cfg_done(vop);
-+		spin_unlock(&vop->reg_lock);
- 
--	if (!state->gamma_lut)
--		return;
-+		/*
-+		 * In order to write the LUT to the internal memory,
-+		 * we need to first make sure the dsp_lut_en bit is cleared.
-+		 */
-+		ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,
-+					 idle, !idle, 5, 30 * 1000);
-+		if (ret) {
-+			DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");
-+			return;
-+		}
-+
-+		if (!state->gamma_lut)
-+			return;
-+	} else {
-+		/*
-+		 * On RK3399 the gamma LUT can updated without clearing dsp_lut_en,
-+		 * by setting update_gamma_lut then waiting for lut_buffer_index change
-+		 */
-+		old_idx = vop_lut_buffer_index(vop);
-+	}
- 
- 	spin_lock(&vop->reg_lock);
- 	vop_crtc_write_gamma_lut(vop, crtc);
- 	VOP_REG_SET(vop, common, dsp_lut_en, 1);
-+	VOP_REG_SET(vop, common, update_gamma_lut, 1);
- 	vop_cfg_done(vop);
- 	spin_unlock(&vop->reg_lock);
-+
-+	if (VOP_HAS_REG(vop, common, update_gamma_lut)) {
-+		ret = readx_poll_timeout(vop_lut_buffer_index, vop,
-+					 lut_idx, lut_idx != old_idx, 5, 30 * 1000);
-+		if (ret) {
-+			DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n");
-+			return;
-+		}
-+
-+		/*
-+		 * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit
-+		 * in our backup of the regs.
-+		 */
-+		spin_lock(&vop->reg_lock);
-+		VOP_REG_SET(vop, common, update_gamma_lut, 0);
-+		spin_unlock(&vop->reg_lock);
-+	}
- }
- 
- static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
-@@ -1305,14 +1342,6 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
- 		return;
- 	}
- 
--	/*
--	 * If we have a GAMMA LUT in the state, then let's make sure
--	 * it's updated. We might be coming out of suspend,
--	 * which means the LUT internal memory needs to be re-written.
--	 */
--	if (crtc->state->gamma_lut)
--		vop_crtc_gamma_set(vop, crtc, old_state);
--
- 	mutex_lock(&vop->vop_lock);
- 
- 	WARN_ON(vop->event);
-@@ -1403,6 +1432,14 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
- 
- 	VOP_REG_SET(vop, common, standby, 0);
- 	mutex_unlock(&vop->vop_lock);
-+
-+	/*
-+	 * If we have a GAMMA LUT in the state, then let's make sure
-+	 * it's updated. We might be coming out of suspend,
-+	 * which means the LUT internal memory needs to be re-written.
-+	 */
-+	if (crtc->state->gamma_lut)
-+		vop_crtc_gamma_set(vop, crtc, old_state);
- }
- 
- static bool vop_fs_irq_is_pending(struct vop *vop)
-@@ -2125,8 +2162,8 @@ static int vop_bind(struct device *dev, struct device *master, void *data)
- 
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- 	if (res) {
--		if (!vop_data->lut_size) {
--			DRM_DEV_ERROR(dev, "no gamma LUT size defined\n");
-+		if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) {
-+			DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size);
- 			return -EINVAL;
- 		}
- 		vop->lut_regs = devm_ioremap_resource(dev, res);
-
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-From: Hugh Cole-Baker <sigmaris@gmail.com>
-To: heiko@sntech.de,
-	hjc@rock-chips.com
-Cc: dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org,
- linux-arm-kernel@lists.infradead.org, ezequiel@collabora.com,
- Hugh Cole-Baker <sigmaris@gmail.com>
-Subject: [PATCH v2 3/3] arm64: dts: rockchip: enable gamma control on RK3399
-Date: Tue, 19 Oct 2021 22:58:43 +0100
-Message-Id: <20211019215843.42718-4-sigmaris@gmail.com>
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-
-Define the memory region on RK3399 VOPs containing the gamma LUT at
-base+0x2000.
-
-Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
----
-
-Changes from v1: no changes in this patch
-
- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-index 3871c7fd83b0..9cbf6ccdd256 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -1619,7 +1619,7 @@ i2s2: i2s@ff8a0000 {
- 
- 	vopl: vop@ff8f0000 {
- 		compatible = "rockchip,rk3399-vop-lit";
--		reg = <0x0 0xff8f0000 0x0 0x3efc>;
-+		reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>;
- 		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
- 		assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
- 		assigned-clock-rates = <400000000>, <100000000>;
-@@ -1676,7 +1676,7 @@ vopl_mmu: iommu@ff8f3f00 {
- 
- 	vopb: vop@ff900000 {
- 		compatible = "rockchip,rk3399-vop-big";
--		reg = <0x0 0xff900000 0x0 0x3efc>;
-+		reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>;
- 		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
- 		assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
- 		assigned-clock-rates = <400000000>, <100000000>;
diff --git a/0021-drm-panfrost-scheduler-fix.patch b/0021-drm-panfrost-scheduler-fix.patch
deleted file mode 100644
index 3efd213..0000000
--- a/0021-drm-panfrost-scheduler-fix.patch
+++ /dev/null
@@ -1,109 +0,0 @@
-diff -pruN -X linux-5.15-rc1-ORIG/Documentation/dontdiff linux-5.15-rc1-ORIG/drivers/gpu/drm/panfrost/panfrost_job.c linux-5.15-rc1-panfrost/drivers/gpu/drm/panfrost/panfrost_job.c
---- linux-5.15-rc1-ORIG/drivers/gpu/drm/panfrost/panfrost_job.c	2021-09-13 01:28:37.000000000 +0200
-+++ linux-5.15-rc1-panfrost/drivers/gpu/drm/panfrost/panfrost_job.c	2021-09-17 17:47:38.287735915 +0200
-@@ -234,7 +234,7 @@ static void panfrost_job_hw_submit(struc
- 	if (!atomic_read(&pfdev->reset.pending)) {
- 		job_write(pfdev, JS_COMMAND_NEXT(js), JS_COMMAND_START);
- 		dev_dbg(pfdev->dev,
--			"JS: Submitting atom %p to js[%d][%d] with head=0x%llx AS %d",
-+			"Job slot: submitting atom %p to js[%d][%d] with head=0x%llx, as=%d\n",
- 			job, js, subslot, jc_head, cfg & 0xf);
- 	}
- 	spin_unlock(&pfdev->js->job_lock);
-@@ -425,12 +425,12 @@ static void panfrost_job_handle_err(stru
- 	bool signal_fence = true;
- 
- 	if (!panfrost_exception_is_fault(js_status)) {
--		dev_dbg(pfdev->dev, "js event, js=%d, status=%s, head=0x%x, tail=0x%x",
-+		dev_dbg(pfdev->dev, "Job slot event: js=%d, status=%s, head=0x%x, tail=0x%x\n",
- 			js, exception_name,
- 			job_read(pfdev, JS_HEAD_LO(js)),
- 			job_read(pfdev, JS_TAIL_LO(js)));
- 	} else {
--		dev_err(pfdev->dev, "js fault, js=%d, status=%s, head=0x%x, tail=0x%x",
-+		dev_err(pfdev->dev, "Job slot fault: js=%d, status=%s, head=0x%x, tail=0x%x\n",
- 			js, exception_name,
- 			job_read(pfdev, JS_HEAD_LO(js)),
- 			job_read(pfdev, JS_TAIL_LO(js)));
-@@ -671,7 +671,7 @@ panfrost_reset(struct panfrost_device *p
- 				 10, 10000);
- 
- 	if (ret)
--		dev_err(pfdev->dev, "Soft-stop failed\n");
-+		dev_err(pfdev->dev, "Failed to complete soft-stop: %d\n", ret);
- 
- 	/* Handle the remaining interrupts before we reset. */
- 	panfrost_job_handle_irqs(pfdev);
-@@ -740,7 +740,7 @@ static enum drm_gpu_sched_stat panfrost_
- 	if (dma_fence_is_signaled(job->done_fence))
- 		return DRM_GPU_SCHED_STAT_NOMINAL;
- 
--	dev_err(pfdev->dev, "gpu sched timeout, js=%d, config=0x%x, status=0x%x, head=0x%x, tail=0x%x, sched_job=%p",
-+	dev_err(pfdev->dev, "GPU scheduler timeout: js=%d, config=0x%x, status=0x%x, head=0x%x, tail=0x%x, sched_job=%p\n",
- 		js,
- 		job_read(pfdev, JS_CONFIG(js)),
- 		job_read(pfdev, JS_STATUS(js)),
-@@ -822,7 +822,7 @@ int panfrost_job_init(struct panfrost_de
- 					IRQF_SHARED, KBUILD_MODNAME "-job",
- 					pfdev);
- 	if (ret) {
--		dev_err(pfdev->dev, "failed to request job irq");
-+		dev_err(pfdev->dev, "Failed to request job IRQ: %d\n", ret);
- 		return ret;
- 	}
- 
-@@ -840,7 +840,7 @@ int panfrost_job_init(struct panfrost_de
- 				     pfdev->reset.wq,
- 				     NULL, "pan_js");
- 		if (ret) {
--			dev_err(pfdev->dev, "Failed to create scheduler: %d.", ret);
-+			dev_err(pfdev->dev, "Failed to create scheduler: %d\n", ret);
- 			goto err_sched;
- 		}
- 	}
-diff -pruN -X linux-5.15-rc1-ORIG/Documentation/dontdiff linux-5.15-rc1-ORIG/drivers/gpu/drm/scheduler/sched_main.c linux-5.15-rc1-panfrost/drivers/gpu/drm/scheduler/sched_main.c
---- linux-5.15-rc1-ORIG/drivers/gpu/drm/scheduler/sched_main.c	2021-09-13 01:28:37.000000000 +0200
-+++ linux-5.15-rc1-panfrost/drivers/gpu/drm/scheduler/sched_main.c	2021-09-17 17:50:54.947121296 +0200
-@@ -489,8 +489,7 @@ void drm_sched_start(struct drm_gpu_sche
- 			if (r == -ENOENT)
- 				drm_sched_job_done(s_job);
- 			else if (r)
--				DRM_ERROR("fence add callback failed (%d)\n",
--					  r);
-+				DRM_ERROR("Failed to add fence callback: %d\n", r);
- 		} else
- 			drm_sched_job_done(s_job);
- 	}
-@@ -776,7 +775,7 @@ static int drm_sched_main(void *param)
- 	struct drm_gpu_scheduler *sched = (struct drm_gpu_scheduler *)param;
- 	int r;
- 
--	sched_set_fifo_low(current);
-+	sched_set_fifo(current);
- 
- 	while (!kthread_should_stop()) {
- 		struct drm_sched_entity *entity = NULL;
-@@ -824,13 +823,11 @@ static int drm_sched_main(void *param)
- 			if (r == -ENOENT)
- 				drm_sched_job_done(sched_job);
- 			else if (r)
--				DRM_ERROR("fence add callback failed (%d)\n",
--					  r);
-+				DRM_ERROR("Failed to add fence callback: %d\n", r);
- 			dma_fence_put(fence);
- 		} else {
- 			if (IS_ERR(fence))
- 				dma_fence_set_error(&s_fence->finished, PTR_ERR(fence));
--
- 			drm_sched_job_done(sched_job);
- 		}
- 
-@@ -885,7 +882,7 @@ int drm_sched_init(struct drm_gpu_schedu
- 	if (IS_ERR(sched->thread)) {
- 		ret = PTR_ERR(sched->thread);
- 		sched->thread = NULL;
--		DRM_ERROR("Failed to create scheduler for %s.\n", name);
-+		DRM_ERROR("Failed to create scheduler for %s: %d\n", name, ret);
- 		return ret;
- 	}
- 
diff --git a/0021-media-rockchip-rga-do-proper-error-checking-in-probe.patch b/0021-media-rockchip-rga-do-proper-error-checking-in-probe.patch
deleted file mode 100644
index a697954..0000000
--- a/0021-media-rockchip-rga-do-proper-error-checking-in-probe.patch
+++ /dev/null
@@ -1,132 +0,0 @@
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-From: Kyle Copperfield <kmcopper@danwin1210.me>
-To: Ezequiel Garcia <ezequiel@collabora.com>,
- Mauro Carvalho Chehab <mchehab@kernel.org>,
- Heiko Stuebner <heiko@sntech.de>, Dan Carpenter <dan.carpenter@oracle.com>
-Cc: Kyle Copperfield <kmcopper@danwin1210.me>,
- Dragan Simic <dragan.simic@gmail.com>, linux-media@vger.kernel.org,
- linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org,
- linux-kernel@vger.kernel.org
-Subject: [PATCH] media: rockchip/rga: do proper error checking in probe
-Date: Sat, 20 Nov 2021 12:23:02 +0000
-Message-Id: <20211120122321.20253-1-kmcopper@danwin1210.me>
-MIME-Version: 1.0
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-X-BeenThere: linux-rockchip@lists.infradead.org
-X-Mailman-Version: 2.1.34
-Precedence: list
-List-Id: Upstream kernel work for Rockchip platforms
- <linux-rockchip.lists.infradead.org>
-List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-rockchip>,
- <mailto:linux-rockchip-request@lists.infradead.org?subject=unsubscribe>
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-Errors-To: 
- linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org
-
-The latest fix for probe error handling contained a typo that causes
-probing to fail with the following message:
-
-  rockchip-rga: probe of ff680000.rga failed with error -12
-
-This patch fixes the typo.
-
-Fixes: e58430e1d4fd (media: rockchip/rga: fix error handling in probe)
-Reviewed-by: Dragan Simic <dragan.simic@gmail.com>
-Signed-off-by: Kyle Copperfield <kmcopper@danwin1210.me>
-Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
-Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com>
----
- drivers/media/platform/rockchip/rga/rga.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
-index 6759091b15e0..d99ea8973b67 100644
---- a/drivers/media/platform/rockchip/rga/rga.c
-+++ b/drivers/media/platform/rockchip/rga/rga.c
-@@ -895,7 +895,7 @@ static int rga_probe(struct platform_device *pdev)
- 	}
- 	rga->dst_mmu_pages =
- 		(unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
--	if (rga->dst_mmu_pages) {
-+	if (!rga->dst_mmu_pages) {
- 		ret = -ENOMEM;
- 		goto free_src_pages;
- 	}
diff --git a/0022-arm-dts-rockchip-firefly-station-m2.patch b/0022-arm-dts-rockchip-firefly-station-m2.patch
deleted file mode 100644
index 06cc20b..0000000
--- a/0022-arm-dts-rockchip-firefly-station-m2.patch
+++ /dev/null
@@ -1,647 +0,0 @@
-diff -up linux-5.16/arch/arm64/boot/dts/rockchip/Makefile.64~ linux-5.16/arch/arm64/boot/dts/rockchip/Makefile
---- linux-5.16/arch/arm64/boot/dts/rockchip/Makefile.64~	2022-01-10 12:06:23.512641394 +0100
-+++ linux-5.16/arch/arm64/boot/dts/rockchip/Makefile	2022-01-10 12:06:23.525641434 +0100
-@@ -58,4 +58,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sa
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-station-p1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
-diff -up linux-5.16/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts.64~ linux-5.16/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
---- linux-5.16/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts.64~	2022-01-10 12:06:23.526641437 +0100
-+++ linux-5.16/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts	2022-01-10 12:07:58.860933530 +0100
-@@ -0,0 +1,619 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ *
-+ */
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include "rk3566.dtsi"
-+
-+/ {
-+	model = "Firefly Station M2";
-+	compatible = "firefly,rk3566-roc-pc", "rockchip,rk3566";
-+
-+	aliases {
-+		mmc0 = &sdmmc0;
-+		mmc1 = &sdhci;
-+		mmc2 = &sdmmc1;
-+	};
-+
-+	chosen: chosen {
-+		stdout-path = "serial2:1500000n8";
-+	};
-+
-+	gmac1_clkin: external-gmac1-clock {
-+		compatible = "fixed-clock";
-+		clock-frequency = <125000000>;
-+		clock-output-names = "gmac1_clkin";
-+		#clock-cells = <0>;
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+
-+		led-user {
-+			label = "user-led";
-+			default-state = "on";
-+			gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
-+			linux,default-trigger = "heartbeat";
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&user_led_enable_h>;
-+			retain-state-suspended;
-+		};
-+	};
-+
-+	sdio_pwrseq: sdio-pwrseq {
-+		status = "okay";
-+		compatible = "mmc-pwrseq-simple";
-+		clocks = <&rk809 1>;
-+		clock-names = "ext_clock";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&wifi_enable_h>;
-+		reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
-+	};
-+
-+	usb_5v: usb_5v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "usb_5v";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+
-+	vcc5v0_sys: vcc5v0_sys {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&usb_5v>;
-+	};
-+
-+	vcc3v3_sys: vcc3v3_sys {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_sys";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-always-on;
-+		vin-supply = <&vcc5v0_sys>;
-+	};
-+
-+	vcc5v0_usb30_host: vcc5v0_usb30_host {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_usb30_host";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&vcc5v0_usb30_host_en_h>;
-+		regulator-always-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vcc5v0_sys>;
-+	};
-+
-+	vcc3v3_pcie: vcc3v3_pcie {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_pcie";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&vcc3v3_pcie_en_h>;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vcc5v0_sys>;
-+	};
-+
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&gmac1 {
-+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
-+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
-+	clock_in_out = "input";
-+	phy-mode = "rgmii-id";
-+	phy-supply = <&vcc_3v3>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&gmac1m0_miim
-+		     &gmac1m0_tx_bus2
-+		     &gmac1m0_rx_bus2
-+		     &gmac1m0_rgmii_clk
-+		     &gmac1m0_clkinout
-+		     &gmac1m0_rgmii_bus>;
-+	snps,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
-+	snps,reset-active-low;
-+	/* Reset time is 20ms, 100ms for rtl8211f */
-+	snps,reset-delays-us = <0 20000 100000>;
-+	tx_delay = <0x4f>;
-+	rx_delay = <0x24>;
-+	phy-handle = <&rgmii_phy1>;
-+	status = "okay";
-+};
-+
-+&hdmi {
-+	status = "okay";
-+	avdd-0v9-supply = <&vdda_0v9>;
-+	avdd-1v8-supply = <&vcc_1v8>;
-+};
-+
-+&hdmi_in_vp0 {
-+	status = "okay";
-+};
-+
-+&hdmi_sound {
-+	status = "okay";
-+};
-+
-+&gpu {
-+	mali-supply = <&vdd_gpu>;
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+
-+	vdd_cpu: regulator@1c {
-+		compatible = "tcs,tcs4525";
-+		reg = <0x1c>;
-+		fcs,suspend-voltage-selector = <1>;
-+		regulator-name = "vdd_cpu";
-+		regulator-min-microvolt = <800000>;
-+		regulator-max-microvolt = <1150000>;
-+		regulator-ramp-delay = <2300>;
-+		regulator-always-on;
-+		regulator-boot-on;
-+		vin-supply = <&vcc5v0_sys>;
-+
-+		regulator-state-mem {
-+			regulator-off-in-suspend;
-+		};
-+	};
-+
-+	rk809: pmic@20 {
-+		compatible = "rockchip,rk809";
-+		reg = <0x20>;
-+		interrupt-parent = <&gpio0>;
-+		interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
-+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
-+
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pmic_int>;
-+		rockchip,system-power-controller;
-+		wakeup-source;
-+		#clock-cells = <1>;
-+
-+		vcc1-supply = <&vcc3v3_sys>;
-+		vcc2-supply = <&vcc3v3_sys>;
-+		vcc3-supply = <&vcc3v3_sys>;
-+		vcc4-supply = <&vcc3v3_sys>;
-+		vcc5-supply = <&vcc3v3_sys>;
-+		vcc6-supply = <&vcc3v3_sys>;
-+		vcc7-supply = <&vcc3v3_sys>;
-+		vcc8-supply = <&vcc3v3_sys>;
-+		vcc9-supply = <&vcc3v3_sys>;
-+
-+		regulators {
-+			vdd_log: DCDC_REG1 {
-+				regulator-name = "vdd_log";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-init-microvolt = <900000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <900000>;
-+				};
-+			};
-+
-+			vdd_gpu: DCDC_REG2 {
-+				regulator-name = "vdd_gpu";
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-init-microvolt = <900000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+					regulator-suspend-microvolt = <900000>;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-name = "vcc_ddr";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1100000>;
-+				regulator-max-microvolt = <1100000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vdd_npu: DCDC_REG4 {
-+				regulator-name = "vdd_npu";
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_1v8: DCDC_REG5 {
-+				regulator-name = "vcc_1v8";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vdda0v9_image: LDO_REG1 {
-+				regulator-name = "vdda0v9_image";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <900000>;
-+				};
-+			};
-+
-+			vdda_0v9: LDO_REG2 {
-+				regulator-name = "vdda_0v9";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <900000>;
-+				};
-+			};
-+
-+			vdda0v9_pmu: LDO_REG3 {
-+				regulator-name = "vdda0v9_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <900000>;
-+				};
-+			};
-+
-+			vccio_acodec: LDO_REG4 {
-+				regulator-name = "vccio_acodec";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+
-+				};
-+			};
-+
-+			vccio_sd: LDO_REG5 {
-+				regulator-name = "vccio_sd";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vcc3v3_pmu: LDO_REG6 {
-+				regulator-name = "vcc3v3_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vcca_1v8: LDO_REG7 {
-+				regulator-name = "vcca_1v8";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcca1v8_pmu: LDO_REG8 {
-+				regulator-name = "vcca1v8_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcca1v8_image: LDO_REG9 {
-+				regulator-name = "vcca1v8_image";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcc_3v3: SWITCH_REG1 {
-+				regulator-boot-on;
-+				regulator-name = "vcc3v3";
-+			};
-+
-+			vcc3v3_sd: SWITCH_REG2 {
-+				regulator-name = "vcc3v3_sd";
-+				regulator-always-on;
-+				regulator-boot-on;
-+			};
-+		};
-+	};
-+};
-+
-+
-+&i2c1 {
-+//	status = "okay";
-+};
-+
-+&i2c2 {
-+//	status = "okay";
-+};
-+
-+&i2c3 {
-+//	status = "okay";
-+//	pinctrl-names = "default";
-+//	pinctrl-0 = <&i2c3m1_xfer>;
-+};
-+
-+&i2c5 {
-+//	status = "okay";
-+};
-+
-+&i2s0_8ch {
-+	status = "okay";
-+};
-+
-+&mdio1 {
-+	rgmii_phy1: ethernet-phy@0 {
-+		compatible = "ethernet-phy-ieee802.3-c22";
-+		reg = <0x0>;
-+	};
-+};
-+
-+&pinctrl {
-+	bt {
-+		bt_enable_h: bt-enable-h {
-+			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		bt_host_wake_l: bt-host-wake-l {
-+			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
-+		};
-+
-+		bt_wake_l: bt-wake-l {
-+			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	leds {
-+		user_led_enable_h: user-led-enable-h {
-+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	pcie {
-+		vcc3v3_pcie_en_h: vcc3v3-pcie-en-h {
-+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		pcie_reset_h: pcie-reset-h {
-+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	pmic {
-+		pmic_int: pmic_int {
-+			rockchip,pins =
-+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
-+	sdio-pwrseq {
-+		wifi_enable_h: wifi-enable-h {
-+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	usb {
-+		vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {
-+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+};
-+
-+&pmu_io_domains {
-+	status = "okay";
-+	pmuio1-supply = <&vcc3v3_pmu>;
-+	pmuio2-supply = <&vcc3v3_pmu>;
-+	vccio1-supply = <&vccio_acodec>;
-+	vccio2-supply = <&vcc_1v8>;
-+	vccio3-supply = <&vccio_sd>;
-+	vccio4-supply = <&vcc_1v8>;
-+	vccio5-supply = <&vcc_3v3>;
-+	vccio6-supply = <&vcc_1v8>;
-+	vccio7-supply = <&vcc_3v3>;
-+};
-+
-+&sdhci {
-+	bus-width = <8>;
-+	mmc-hs200-1_8v;
-+	non-removable;
-+	vmmc-supply = <&vcc_3v3>;
-+	vqmmc-supply = <&vcc_1v8>;
-+	status = "okay";
-+};
-+
-+&sdmmc0 {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-+	disable-wp;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-+	sd-uhs-sdr104;
-+	vmmc-supply = <&vcc3v3_sd>;
-+	vqmmc-supply = <&vccio_sd>;
-+	status = "okay";
-+};
-+
-+&sdmmc1 {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	cap-sdio-irq;
-+	keep-power-in-suspend;
-+	mmc-pwrseq = <&sdio_pwrseq>;
-+	non-removable;
-+	vmmc-supply = <&vcc3v3_sys>;
-+	vqmmc-supply = <&vcca1v8_pmu>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &uart9m1_xfer &uart8m1_xfer>;
-+	status = "okay";
-+};
-+
-+&tsadc {
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart0_xfer>;
-+//	status = "okay";
-+};
-+
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
-+	status = "okay";
-+	uart-has-rtscts;
-+
-+	bluetooth {
-+		compatible = "brcm,bcm43438-bt";
-+		clocks = <&rk809 1>;
-+		clock-names = "lpo";
-+		device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
-+		host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
-+		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
-+		vbat-supply = <&vcc3v3_sys>;
-+		vddio-supply = <&vcca1v8_pmu>;
-+	};
-+};
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&vop {
-+	status = "okay";
-+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+};
-+
-+&vop_mmu {
-+	status = "okay";
-+};
-+
-+&vp0_out_hdmi {
-+	status = "okay";
-+};
-+
-+&u2phy0_host {
-+	phy-supply = <&vcc5v0_usb30_host>;
-+	status = "okay";
-+};
-+
-+&u2phy0_otg {
-+	status = "okay";
-+};
-+
-+&u2phy1_host {
-+	phy-supply = <&vcc5v0_usb30_host>;
-+	status = "okay";
-+};
-+
-+&u2phy1_otg {
-+	phy-supply = <&vcc5v0_usb30_host>;
-+	status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+	status = "okay";
-+};
-diff -up linux-5.16/Documentation/devicetree/bindings/arm/rockchip.yaml.64~ linux-5.16/Documentation/devicetree/bindings/arm/rockchip.yaml
---- linux-5.16/Documentation/devicetree/bindings/arm/rockchip.yaml.64~	2022-01-10 12:06:23.526641437 +0100
-+++ linux-5.16/Documentation/devicetree/bindings/arm/rockchip.yaml	2022-01-10 12:07:26.298833834 +0100
-@@ -133,6 +133,11 @@ properties:
-               - firefly,roc-rk3399-pc-plus
-           - const: rockchip,rk3399
- 
-+      - description: Firefly ROC-RK3566-PC
-+        items:
-+          - const: firefly,rk3566-roc-pc
-+          - const: rockchip,rk3566
-+
-       - description: FriendlyElec NanoPi R2S
-         items:
-           - const: friendlyarm,nanopi-r2s
diff --git a/0023-add-dts-rk3568-station-p2.patch b/0023-add-dts-rk3568-station-p2.patch
deleted file mode 100644
index 67d4e63..0000000
--- a/0023-add-dts-rk3568-station-p2.patch
+++ /dev/null
@@ -1,587 +0,0 @@
---- a/arch/arm64/boot/dts/rockchip/Makefile    2021-11-28 00:08:54.223075781 +0300
-+++ b/arch/arm64/boot/dts/rockchip/Makefile 2021-11-28 00:09:49.583353821 +0300
-@@ -60,3 +60,4 @@
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
-
---- /dev/null	2021-11-27 21:12:18.297734621 +0300
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts	2021-11-27 23:47:17.494127854 +0300
-@@ -0,0 +1,575 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
-+ *
-+ */
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include "rk3568.dtsi"
-+
-+/ {
-+	model = "Firefly Station P2";
-+	compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568";
-+
-+	aliases {
-+		ethernet0 = &gmac0;
-+		ethernet1 = &gmac1;
-+		mmc0 = &sdmmc0;
-+		mmc1 = &sdhci;
-+	};
-+
-+	chosen: chosen {
-+		stdout-path = "serial2:1500000n8";
-+	};
-+
-+	gmac0_clkin: external-gmac0-clock {
-+		compatible = "fixed-clock";
-+		clock-frequency = <125000000>;
-+		clock-output-names = "gmac0_clkin";
-+		#clock-cells = <0>;
-+	};
-+
-+	gmac1_clkin: external-gmac1-clock {
-+		compatible = "fixed-clock";
-+		clock-frequency = <125000000>;
-+		clock-output-names = "gmac1_clkin";
-+		#clock-cells = <0>;
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+
-+		led-user {
-+			label = "user-led";
-+			default-state = "on";
-+			gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
-+			linux,default-trigger = "heartbeat";
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&user_led_enable_h>;
-+			retain-state-suspended;
-+		};
-+	};
-+
-+	sdio_pwrseq: sdio-pwrseq {
-+		status = "okay";
-+		compatible = "mmc-pwrseq-simple";
-+		clocks = <&rk809 1>;
-+		clock-names = "ext_clock";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&wifi_enable_h>;
-+		reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
-+	};
-+
-+	dc_12v: dc-12v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "dc_12v";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <12000000>;
-+		regulator-max-microvolt = <12000000>;
-+	};
-+
-+	vcc3v3_sys: vcc3v3-sys {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&dc_12v>;
-+	};
-+
-+	vcc5v0_sys: vcc5v0-sys {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&dc_12v>;
-+	};
-+
-+	vcc5v0_usb: vcc5v0-usb {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_usb";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vcc5v0_sys>;
-+	};
-+
-+	vcc5v0_host: vcc5v0-host {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_host";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&vcc5v0_host_en>;
-+		regulator-always-on;
-+		vin-supply = <&vcc5v0_usb>;
-+	};
-+
-+	vcc5v0_otg: vcc5v0-otg {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_otg";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&vcc5v0_otg_en>;
-+		vin-supply = <&vcc5v0_usb>;
-+	};
-+	
-+	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_lcd0_n";
-+		regulator-boot-on;
-+
-+		regulator-state-mem {
-+			regulator-off-in-suspend;
-+		};
-+	};
-+
-+	vcc3v3_lcd1_n: vcc3v3-lcd1-n {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_lcd1_n";
-+		regulator-boot-on;
-+
-+		regulator-state-mem {
-+			regulator-off-in-suspend;
-+		};
-+	};
-+};
-+
-+&gmac0 {
-+	phy-mode = "rgmii";
-+	clock_in_out = "input";
-+
-+	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
-+	snps,reset-active-low;
-+	/* Reset time is 20ms, 100ms for rtl8211f */
-+	snps,reset-delays-us = <0 20000 100000>;
-+
-+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
-+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
-+
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&gmac0_miim
-+		     &gmac0_tx_bus2
-+		     &gmac0_rx_bus2
-+		     &gmac0_rgmii_clk
-+		     &gmac0_rgmii_bus
-+		     &gmac0_clkinout>;
-+
-+	tx_delay = <0x3c>;
-+	rx_delay = <0x2f>;
-+
-+	phy-handle = <&rgmii_phy0>;
-+	status = "okay";
-+};
-+
-+&gmac1 {
-+	phy-mode = "rgmii";
-+	clock_in_out = "input";
-+
-+	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
-+	snps,reset-active-low;
-+	/* Reset time is 20ms, 100ms for rtl8211f */
-+	snps,reset-delays-us = <0 20000 100000>;
-+
-+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
-+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
-+
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&gmac1m1_miim
-+		     &gmac1m1_tx_bus2
-+		     &gmac1m1_rx_bus2
-+		     &gmac1m1_rgmii_clk
-+		     &gmac1m1_rgmii_bus
-+		     &gmac1m1_clkinout>;
-+
-+	tx_delay = <0x4f>;
-+	rx_delay = <0x26>;
-+
-+	phy-handle = <&rgmii_phy1>;
-+	status = "okay";
-+};
-+
-+&hdmi {
-+	status = "okay";
-+	avdd-0v9-supply = <&vdda0v9_image>;
-+	avdd-1v8-supply = <&vcca1v8_image>;
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+
-+	rk809: pmic@20 {
-+		compatible = "rockchip,rk809";
-+		reg = <0x20>;
-+		interrupt-parent = <&gpio0>;
-+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+		#clock-cells = <1>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pmic_int>;
-+		rockchip,system-power-controller;
-+		vcc1-supply = <&vcc3v3_sys>;
-+		vcc2-supply = <&vcc3v3_sys>;
-+		vcc3-supply = <&vcc3v3_sys>;
-+		vcc4-supply = <&vcc3v3_sys>;
-+		vcc5-supply = <&vcc3v3_sys>;
-+		vcc6-supply = <&vcc3v3_sys>;
-+		vcc7-supply = <&vcc3v3_sys>;
-+		vcc8-supply = <&vcc3v3_sys>;
-+		vcc9-supply = <&vcc3v3_sys>;
-+		wakeup-source;
-+
-+		regulators {
-+			vdd_logic: DCDC_REG1 {
-+				regulator-name = "vdd_logic";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdd_gpu: DCDC_REG2 {
-+				regulator-name = "vdd_gpu";
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-name = "vcc_ddr";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-initial-mode = <0x2>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vdd_npu: DCDC_REG4 {
-+				regulator-name = "vdd_npu";
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_1v8: DCDC_REG5 {
-+				regulator-name = "vcc_1v8";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda0v9_image: LDO_REG1 {
-+				regulator-name = "vdda0v9_image";
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda_0v9: LDO_REG2 {
-+				regulator-name = "vdda_0v9";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda0v9_pmu: LDO_REG3 {
-+				regulator-name = "vdda0v9_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <900000>;
-+				};
-+			};
-+
-+			vccio_acodec: LDO_REG4 {
-+				regulator-name = "vccio_acodec";
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vccio_sd: LDO_REG5 {
-+				regulator-name = "vccio_sd";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_pmu: LDO_REG6 {
-+				regulator-name = "vcc3v3_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vcca_1v8: LDO_REG7 {
-+				regulator-name = "vcca_1v8";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcca1v8_pmu: LDO_REG8 {
-+				regulator-name = "vcca1v8_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcca1v8_image: LDO_REG9 {
-+				regulator-name = "vcca1v8_image";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_3v3: SWITCH_REG1 {
-+				regulator-name = "vcc_3v3";
-+				regulator-always-on;
-+				regulator-boot-on;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_sd: SWITCH_REG2 {
-+				regulator-name = "vcc3v3_sd";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+&mdio0 {
-+	rgmii_phy0: phy@0 {
-+		compatible = "ethernet-phy-ieee802.3-c22";
-+		reg = <0x0>;
-+	};
-+};
-+
-+&mdio1 {
-+	rgmii_phy1: phy@0 {
-+		compatible = "ethernet-phy-ieee802.3-c22";
-+		reg = <0x0>;
-+	};
-+};
-+
-+&pinctrl {
-+	leds {
-+		user_led_enable_h: user-led-enable-h {
-+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	sdio-pwrseq {
-+		wifi_enable_h: wifi-enable-h {
-+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	usb {
-+		vcc5v0_host_en: vcc5v0-host-en {
-+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+		vcc5v0_otg_en: vcc5v0-otg-en {
-+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	pmic {
-+		pmic_int: pmic_int {
-+			rockchip,pins =
-+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+};
-+
-+&i2s0_8ch {
-+	status = "okay";
-+};
-+
-+&pmu_io_domains {
-+	pmuio1-supply = <&vcc3v3_pmu>;
-+	pmuio2-supply = <&vcc3v3_pmu>;
-+	vccio1-supply = <&vccio_acodec>;
-+	vccio2-supply = <&vcc_1v8>;
-+	vccio3-supply = <&vccio_sd>;
-+	vccio4-supply = <&vcc_1v8>;
-+	vccio5-supply = <&vcc_3v3>;
-+	vccio6-supply = <&vcc_1v8>;
-+	vccio7-supply = <&vcc_3v3>;
-+	status = "okay";
-+};
-+
-+&saradc {
-+	vref-supply = <&vcca_1v8>;
-+	status = "okay";
-+};
-+
-+&sdhci {
-+	bus-width = <8>;
-+	max-frequency = <200000000>;
-+	non-removable;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-+	status = "okay";
-+};
-+
-+&sdmmc0 {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-+	disable-wp;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-+	sd-uhs-sdr104;
-+	vmmc-supply = <&vcc3v3_sd>;
-+	vqmmc-supply = <&vccio_sd>;
-+	status = "okay";
-+};
-+
-+&tsadc {
-+        status = "okay";
-+};
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&vop {
-+	status = "okay";
-+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+};
-+
-+&vop_mmu {
-+	status = "okay";
-+};
-+
-+&hdmi_in_vp0 {
-+	status = "okay";
-+};
-+
-+&vp0_out_hdmi {
-+	status = "okay";
-+};
-+
-+&hdmi_sound {
-+	status = "okay";
-+};
-+
-+&gpu {
-+	mali-supply = <&vdd_gpu>;
-+	status = "okay";
-+};
-+
-+&u2phy0_host {
-+	phy-supply = <&vcc5v0_host>;
-+	status = "okay";
-+};
-+
-+&u2phy0_otg {
-+	status = "okay";
-+};
-+
-+&u2phy1_host {
-+	phy-supply = <&vcc5v0_host>;
-+	status = "okay";
-+};
-+
-+&u2phy1_otg {
-+	phy-supply = <&vcc5v0_host>;
-+	status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+	status = "okay";
-+};
-
diff --git a/0023-drm-rockchip-support-gamma-control-on-RK3399.patch b/0023-drm-rockchip-support-gamma-control-on-RK3399.patch
deleted file mode 100644
index 30c9fbf..0000000
--- a/0023-drm-rockchip-support-gamma-control-on-RK3399.patch
+++ /dev/null
@@ -1,667 +0,0 @@
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-From: Hugh Cole-Baker <sigmaris@gmail.com>
-To: heiko@sntech.de,
-	hjc@rock-chips.com
-Cc: dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org,
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-Subject: [PATCH v2 1/3] drm/rockchip: define gamma registers for RK3399
-Date: Tue, 19 Oct 2021 22:58:41 +0100
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-
-The VOP on RK3399 has a different approach from previous versions for
-setting a gamma lookup table, using an update_gamma_lut register. As
-this differs from RK3288, give RK3399 its own set of "common" register
-definitions.
-
-Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
----
-
-Changes from v1: no changes in this patch
-
- drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  2 ++
- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 24 +++++++++++++++++++--
- drivers/gpu/drm/rockchip/rockchip_vop_reg.h |  1 +
- 3 files changed, 25 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
-index 857d97cdc67c..14179e89bd21 100644
---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
-@@ -99,6 +99,8 @@ struct vop_common {
- 	struct vop_reg dither_down_en;
- 	struct vop_reg dither_up;
- 	struct vop_reg dsp_lut_en;
-+	struct vop_reg update_gamma_lut;
-+	struct vop_reg lut_buffer_index;
- 	struct vop_reg gate_en;
- 	struct vop_reg mmu_en;
- 	struct vop_reg out_mode;
-diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
-index ca7cc82125cb..bfb7e130f09b 100644
---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
-@@ -865,6 +865,24 @@ static const struct vop_output rk3399_output = {
- 	.mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3),
- };
- 
-+static const struct vop_common rk3399_common = {
-+	.standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22),
-+	.gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
-+	.mmu_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 20),
-+	.dither_down_sel = VOP_REG(RK3399_DSP_CTRL1, 0x1, 4),
-+	.dither_down_mode = VOP_REG(RK3399_DSP_CTRL1, 0x1, 3),
-+	.dither_down_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 2),
-+	.pre_dither_down = VOP_REG(RK3399_DSP_CTRL1, 0x1, 1),
-+	.dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
-+	.dsp_lut_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 0),
-+	.update_gamma_lut = VOP_REG(RK3399_DSP_CTRL1, 0x1, 7),
-+	.lut_buffer_index = VOP_REG(RK3399_DBG_POST_REG1, 0x1, 1),
-+	.data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
-+	.dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18),
-+	.out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
-+	.cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0),
-+};
-+
- static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = {
- 	.y2r_coefficients = {
- 		VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0),
-@@ -944,7 +962,7 @@ static const struct vop_data rk3399_vop_big = {
- 	.version = VOP_VERSION(3, 5),
- 	.feature = VOP_FEATURE_OUTPUT_RGB10,
- 	.intr = &rk3366_vop_intr,
--	.common = &rk3288_common,
-+	.common = &rk3399_common,
- 	.modeset = &rk3288_modeset,
- 	.output = &rk3399_output,
- 	.afbc = &rk3399_vop_afbc,
-@@ -952,6 +970,7 @@ static const struct vop_data rk3399_vop_big = {
- 	.win = rk3399_vop_win_data,
- 	.win_size = ARRAY_SIZE(rk3399_vop_win_data),
- 	.win_yuv2yuv = rk3399_vop_big_win_yuv2yuv_data,
-+	.lut_size = 1024,
- };
- 
- static const struct vop_win_data rk3399_vop_lit_win_data[] = {
-@@ -970,13 +989,14 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = {
- static const struct vop_data rk3399_vop_lit = {
- 	.version = VOP_VERSION(3, 6),
- 	.intr = &rk3366_vop_intr,
--	.common = &rk3288_common,
-+	.common = &rk3399_common,
- 	.modeset = &rk3288_modeset,
- 	.output = &rk3399_output,
- 	.misc = &rk3368_misc,
- 	.win = rk3399_vop_lit_win_data,
- 	.win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
- 	.win_yuv2yuv = rk3399_vop_lit_win_yuv2yuv_data,
-+	.lut_size = 256,
- };
- 
- static const struct vop_win_data rk3228_vop_win_data[] = {
-diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
-index 0b3cd65ba5c1..406e981c75bd 100644
---- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
-+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
-@@ -628,6 +628,7 @@
- #define RK3399_YUV2YUV_WIN			0x02c0
- #define RK3399_YUV2YUV_POST			0x02c4
- #define RK3399_AUTO_GATING_EN			0x02cc
-+#define RK3399_DBG_POST_REG1			0x036c
- #define RK3399_WIN0_CSC_COE			0x03a0
- #define RK3399_WIN1_CSC_COE			0x03c0
- #define RK3399_WIN2_CSC_COE			0x03e0
-
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-From: Hugh Cole-Baker <sigmaris@gmail.com>
-To: heiko@sntech.de,
-	hjc@rock-chips.com
-Cc: dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org,
- linux-arm-kernel@lists.infradead.org, ezequiel@collabora.com,
- Hugh Cole-Baker <sigmaris@gmail.com>
-Subject: [PATCH v2 2/3] drm/rockchip: support gamma control on RK3399
-Date: Tue, 19 Oct 2021 22:58:42 +0100
-Message-Id: <20211019215843.42718-3-sigmaris@gmail.com>
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-
-The RK3399 has a 1024-entry gamma LUT with 10 bits per component on its
-"big" VOP and a 256-entry, 8 bit per component LUT on the "little" VOP.
-Compared to the RK3288, it no longer requires disabling gamma while
-updating the LUT. On the RK3399, the LUT can be updated at any time as
-the hardware has two LUT buffers, one can be written while the other is
-in use. A swap of the buffers is triggered by writing 1 to the
-update_gamma_lut register.
-
-Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
----
-
-Changes from v1: Moved the vop_crtc_gamma_set call to the end of
-vop_crtc_atomic_enable after the clocks and CRTC are enabled.
-
- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 105 +++++++++++++-------
- 1 file changed, 71 insertions(+), 34 deletions(-)
-
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-index ba9e14da41b4..e2c97f1b26da 100644
---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
-@@ -9,6 +9,7 @@
- #include <linux/delay.h>
- #include <linux/iopoll.h>
- #include <linux/kernel.h>
-+#include <linux/log2.h>
- #include <linux/module.h>
- #include <linux/of.h>
- #include <linux/of_device.h>
-@@ -66,6 +67,9 @@
- #define VOP_REG_SET(vop, group, name, v) \
- 		    vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
- 
-+#define VOP_HAS_REG(vop, group, name) \
-+		(!!(vop->data->group->name.mask))
-+
- #define VOP_INTR_SET_TYPE(vop, name, type, v) \
- 	do { \
- 		int i, reg = 0, mask = 0; \
-@@ -1204,17 +1208,22 @@ static bool vop_dsp_lut_is_enabled(struct vop *vop)
- 	return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);
- }
- 
-+static u32 vop_lut_buffer_index(struct vop *vop)
-+{
-+	return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index);
-+}
-+
- static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc)
- {
- 	struct drm_color_lut *lut = crtc->state->gamma_lut->data;
--	unsigned int i;
-+	unsigned int i, bpc = ilog2(vop->data->lut_size);
- 
- 	for (i = 0; i < crtc->gamma_size; i++) {
- 		u32 word;
- 
--		word = (drm_color_lut_extract(lut[i].red, 10) << 20) |
--		       (drm_color_lut_extract(lut[i].green, 10) << 10) |
--			drm_color_lut_extract(lut[i].blue, 10);
-+		word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) |
-+		       (drm_color_lut_extract(lut[i].green, bpc) << bpc) |
-+			drm_color_lut_extract(lut[i].blue, bpc);
- 		writel(word, vop->lut_regs + i * 4);
- 	}
- }
-@@ -1224,38 +1233,66 @@ static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc,
- {
- 	struct drm_crtc_state *state = crtc->state;
- 	unsigned int idle;
-+	u32 lut_idx, old_idx;
- 	int ret;
- 
- 	if (!vop->lut_regs)
- 		return;
--	/*
--	 * To disable gamma (gamma_lut is null) or to write
--	 * an update to the LUT, clear dsp_lut_en.
--	 */
--	spin_lock(&vop->reg_lock);
--	VOP_REG_SET(vop, common, dsp_lut_en, 0);
--	vop_cfg_done(vop);
--	spin_unlock(&vop->reg_lock);
- 
--	/*
--	 * In order to write the LUT to the internal memory,
--	 * we need to first make sure the dsp_lut_en bit is cleared.
--	 */
--	ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,
--				 idle, !idle, 5, 30 * 1000);
--	if (ret) {
--		DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");
--		return;
--	}
-+	if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) {
-+		/*
-+		 * To disable gamma (gamma_lut is null) or to write
-+		 * an update to the LUT, clear dsp_lut_en.
-+		 */
-+		spin_lock(&vop->reg_lock);
-+		VOP_REG_SET(vop, common, dsp_lut_en, 0);
-+		vop_cfg_done(vop);
-+		spin_unlock(&vop->reg_lock);
- 
--	if (!state->gamma_lut)
--		return;
-+		/*
-+		 * In order to write the LUT to the internal memory,
-+		 * we need to first make sure the dsp_lut_en bit is cleared.
-+		 */
-+		ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,
-+					 idle, !idle, 5, 30 * 1000);
-+		if (ret) {
-+			DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");
-+			return;
-+		}
-+
-+		if (!state->gamma_lut)
-+			return;
-+	} else {
-+		/*
-+		 * On RK3399 the gamma LUT can updated without clearing dsp_lut_en,
-+		 * by setting update_gamma_lut then waiting for lut_buffer_index change
-+		 */
-+		old_idx = vop_lut_buffer_index(vop);
-+	}
- 
- 	spin_lock(&vop->reg_lock);
- 	vop_crtc_write_gamma_lut(vop, crtc);
- 	VOP_REG_SET(vop, common, dsp_lut_en, 1);
-+	VOP_REG_SET(vop, common, update_gamma_lut, 1);
- 	vop_cfg_done(vop);
- 	spin_unlock(&vop->reg_lock);
-+
-+	if (VOP_HAS_REG(vop, common, update_gamma_lut)) {
-+		ret = readx_poll_timeout(vop_lut_buffer_index, vop,
-+					 lut_idx, lut_idx != old_idx, 5, 30 * 1000);
-+		if (ret) {
-+			DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n");
-+			return;
-+		}
-+
-+		/*
-+		 * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit
-+		 * in our backup of the regs.
-+		 */
-+		spin_lock(&vop->reg_lock);
-+		VOP_REG_SET(vop, common, update_gamma_lut, 0);
-+		spin_unlock(&vop->reg_lock);
-+	}
- }
- 
- static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
-@@ -1305,14 +1342,6 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
- 		return;
- 	}
- 
--	/*
--	 * If we have a GAMMA LUT in the state, then let's make sure
--	 * it's updated. We might be coming out of suspend,
--	 * which means the LUT internal memory needs to be re-written.
--	 */
--	if (crtc->state->gamma_lut)
--		vop_crtc_gamma_set(vop, crtc, old_state);
--
- 	mutex_lock(&vop->vop_lock);
- 
- 	WARN_ON(vop->event);
-@@ -1403,6 +1432,14 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
- 
- 	VOP_REG_SET(vop, common, standby, 0);
- 	mutex_unlock(&vop->vop_lock);
-+
-+	/*
-+	 * If we have a GAMMA LUT in the state, then let's make sure
-+	 * it's updated. We might be coming out of suspend,
-+	 * which means the LUT internal memory needs to be re-written.
-+	 */
-+	if (crtc->state->gamma_lut)
-+		vop_crtc_gamma_set(vop, crtc, old_state);
- }
- 
- static bool vop_fs_irq_is_pending(struct vop *vop)
-@@ -2125,8 +2162,8 @@ static int vop_bind(struct device *dev, struct device *master, void *data)
- 
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- 	if (res) {
--		if (!vop_data->lut_size) {
--			DRM_DEV_ERROR(dev, "no gamma LUT size defined\n");
-+		if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) {
-+			DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size);
- 			return -EINVAL;
- 		}
- 		vop->lut_regs = devm_ioremap_resource(dev, res);
-
-From patchwork Tue Oct 19 21:58:43 2021
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-From: Hugh Cole-Baker <sigmaris@gmail.com>
-To: heiko@sntech.de,
-	hjc@rock-chips.com
-Cc: dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org,
- linux-arm-kernel@lists.infradead.org, ezequiel@collabora.com,
- Hugh Cole-Baker <sigmaris@gmail.com>
-Subject: [PATCH v2 3/3] arm64: dts: rockchip: enable gamma control on RK3399
-Date: Tue, 19 Oct 2021 22:58:43 +0100
-Message-Id: <20211019215843.42718-4-sigmaris@gmail.com>
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-
-Define the memory region on RK3399 VOPs containing the gamma LUT at
-base+0x2000.
-
-Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
----
-
-Changes from v1: no changes in this patch
-
- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-index 3871c7fd83b0..9cbf6ccdd256 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -1619,7 +1619,7 @@ i2s2: i2s@ff8a0000 {
- 
- 	vopl: vop@ff8f0000 {
- 		compatible = "rockchip,rk3399-vop-lit";
--		reg = <0x0 0xff8f0000 0x0 0x3efc>;
-+		reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>;
- 		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
- 		assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
- 		assigned-clock-rates = <400000000>, <100000000>;
-@@ -1676,7 +1676,7 @@ vopl_mmu: iommu@ff8f3f00 {
- 
- 	vopb: vop@ff900000 {
- 		compatible = "rockchip,rk3399-vop-big";
--		reg = <0x0 0xff900000 0x0 0x3efc>;
-+		reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>;
- 		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
- 		assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
- 		assigned-clock-rates = <400000000>, <100000000>;
diff --git a/0024-add-dts-rk3568-radxa-rock3a.patch b/0024-add-dts-rk3568-radxa-rock3a.patch
deleted file mode 100644
index c8b0f06..0000000
--- a/0024-add-dts-rk3568-radxa-rock3a.patch
+++ /dev/null
@@ -1,563 +0,0 @@
-From: Furkan <shareahack@hotmail.com>
-Date: Wed, 01 Dec 2021 22:35:57 +0300
-Subject: arm64: dts: rockchip: add dts for Radxa Rock3A
- rk3568
-
-Add dts for Radxa Rock3A, This is similar to Firefly Station P2
-Tested on my device
-Working IO:
-* UART
-* LED
-* LAN
-* SD Card
-* USB2
-
-Signed-off-by: Furkan Kardame <f.kardame@manjaro.org>
-
---- a/arch/arm64/boot/dts/rockchip/Makefile 2021-12-01 22:35:57.786902813 +0300
-+++ b/arch/arm64/boot/dts/rockchip/Makefile 2021-12-01 22:48:58.540217879 +0300
-@@ -60,4 +60,5 @@
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
-
---- /dev/null	2021-12-01 22:35:57.786902813 +0300
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts	2021-12-01 22:48:58.540217879 +0300
-@@ -0,0 +1,534 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
-+ *
-+ */
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include "rk3568.dtsi"
-+
-+/ {
-+	model = "Radxa Rock3A";
-+	compatible = "radxa,rk3568-rock-3a", "rockchip,rk3568";
-+
-+	aliases {
-+		ethernet1 = &gmac1;
-+		mmc0 = &sdmmc0;
-+		mmc1 = &sdhci;
-+	};
-+
-+	chosen: chosen {
-+		stdout-path = "serial2:1500000n8";
-+	};
-+
-+	gmac1_clkin: external-gmac1-clock {
-+		compatible = "fixed-clock";
-+		clock-frequency = <125000000>;
-+		clock-output-names = "gmac1_clkin";
-+		#clock-cells = <0>;
-+	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+
-+		led-user {
-+			label = "user-led";
-+			default-state = "on";
-+			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
-+			linux,default-trigger = "heartbeat";
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&user_led_enable_h>;
-+			retain-state-suspended;
-+		};
-+	};
-+
-+	sdio_pwrseq: sdio-pwrseq {
-+		status = "okay";
-+		compatible = "mmc-pwrseq-simple";
-+		clocks = <&rk809 1>;
-+		clock-names = "ext_clock";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&wifi_enable_h>;
-+		reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
-+	};
-+
-+	dc_12v: dc-12v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "dc_12v";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <12000000>;
-+		regulator-max-microvolt = <12000000>;
-+	};
-+
-+	vcc3v3_sys: vcc3v3-sys {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&dc_12v>;
-+	};
-+
-+	vcc5v0_sys: vcc5v0-sys {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&dc_12v>;
-+	};
-+
-+	vcc5v0_usb: vcc5v0-usb {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_usb";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&vcc5v0_sys>;
-+	};
-+
-+	vcc5v0_host: vcc5v0-host {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_host";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&vcc5v0_host_en>;
-+		regulator-always-on;
-+		vin-supply = <&vcc5v0_usb>;
-+	};
-+
-+	vcc5v0_otg: vcc5v0-otg {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_otg";
-+		enable-active-high;
-+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&vcc5v0_otg_en>;
-+		vin-supply = <&vcc5v0_usb>;
-+	};
-+	
-+	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_lcd0_n";
-+		regulator-boot-on;
-+
-+		regulator-state-mem {
-+			regulator-off-in-suspend;
-+		};
-+	};
-+
-+	vcc3v3_lcd1_n: vcc3v3-lcd1-n {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_lcd1_n";
-+		regulator-boot-on;
-+
-+		regulator-state-mem {
-+			regulator-off-in-suspend;
-+		};
-+	};
-+};
-+
-+&gmac1 {
-+	phy-mode = "rgmii";
-+	clock_in_out = "input";
-+
-+	snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
-+	snps,reset-active-low;
-+	/* Reset time is 20ms, 100ms for rtl8211f */
-+	snps,reset-delays-us = <0 20000 100000>;
-+
-+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
-+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
-+
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&gmac1m1_miim
-+		     &gmac1m1_tx_bus2
-+		     &gmac1m1_rx_bus2
-+		     &gmac1m1_rgmii_clk
-+		     &gmac1m1_rgmii_bus
-+		     &gmac1m1_clkinout>;
-+
-+	tx_delay = <0x4f>;
-+	rx_delay = <0x26>;
-+
-+	phy-handle = <&rgmii_phy1>;
-+	status = "okay";
-+};
-+
-+&hdmi {
-+	status = "okay";
-+	avdd-0v9-supply = <&vdda0v9_image>;
-+	avdd-1v8-supply = <&vcca1v8_image>;
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+
-+	rk809: pmic@20 {
-+		compatible = "rockchip,rk809";
-+		reg = <0x20>;
-+		interrupt-parent = <&gpio0>;
-+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+		#clock-cells = <1>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pmic_int>;
-+		rockchip,system-power-controller;
-+		vcc1-supply = <&vcc3v3_sys>;
-+		vcc2-supply = <&vcc3v3_sys>;
-+		vcc3-supply = <&vcc3v3_sys>;
-+		vcc4-supply = <&vcc3v3_sys>;
-+		vcc5-supply = <&vcc3v3_sys>;
-+		vcc6-supply = <&vcc3v3_sys>;
-+		vcc7-supply = <&vcc3v3_sys>;
-+		vcc8-supply = <&vcc3v3_sys>;
-+		vcc9-supply = <&vcc3v3_sys>;
-+		wakeup-source;
-+
-+		regulators {
-+			vdd_logic: DCDC_REG1 {
-+				regulator-name = "vdd_logic";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdd_gpu: DCDC_REG2 {
-+				regulator-name = "vdd_gpu";
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-name = "vcc_ddr";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-initial-mode = <0x2>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vdd_npu: DCDC_REG4 {
-+				regulator-name = "vdd_npu";
-+				regulator-init-microvolt = <900000>;
-+				regulator-initial-mode = <0x2>;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-ramp-delay = <6001>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_1v8: DCDC_REG5 {
-+				regulator-name = "vcc_1v8";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda0v9_image: LDO_REG1 {
-+				regulator-name = "vdda0v9_image";
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda_0v9: LDO_REG2 {
-+				regulator-name = "vdda_0v9";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda0v9_pmu: LDO_REG3 {
-+				regulator-name = "vdda0v9_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <900000>;
-+				};
-+			};
-+
-+			vccio_acodec: LDO_REG4 {
-+				regulator-name = "vccio_acodec";
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vccio_sd: LDO_REG5 {
-+				regulator-name = "vccio_sd";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_pmu: LDO_REG6 {
-+				regulator-name = "vcc3v3_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vcca_1v8: LDO_REG7 {
-+				regulator-name = "vcca_1v8";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcca1v8_pmu: LDO_REG8 {
-+				regulator-name = "vcca1v8_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcca1v8_image: LDO_REG9 {
-+				regulator-name = "vcca1v8_image";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_3v3: SWITCH_REG1 {
-+				regulator-name = "vcc_3v3";
-+				regulator-always-on;
-+				regulator-boot-on;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_sd: SWITCH_REG2 {
-+				regulator-name = "vcc3v3_sd";
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+
-+&mdio1 {
-+	rgmii_phy1: phy@0 {
-+		compatible = "ethernet-phy-ieee802.3-c22";
-+		reg = <0x0>;
-+	};
-+};
-+
-+&pinctrl {
-+	leds {
-+		user_led_enable_h: user-led-enable-h {
-+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	sdio-pwrseq {
-+		wifi_enable_h: wifi-enable-h {
-+			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	usb {
-+		vcc5v0_host_en: vcc5v0-host-en {
-+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+		vcc5v0_otg_en: vcc5v0-otg-en {
-+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	pmic {
-+		pmic_int: pmic_int {
-+			rockchip,pins =
-+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+};
-+
-+&i2s0_8ch {
-+	status = "okay";
-+};
-+
-+&pmu_io_domains {
-+	pmuio1-supply = <&vcc3v3_pmu>;
-+	pmuio2-supply = <&vcc3v3_pmu>;
-+	vccio1-supply = <&vccio_acodec>;
-+	vccio2-supply = <&vcc_1v8>;
-+	vccio3-supply = <&vccio_sd>;
-+	vccio4-supply = <&vcc_1v8>;
-+	vccio5-supply = <&vcc_3v3>;
-+	vccio6-supply = <&vcc_1v8>;
-+	vccio7-supply = <&vcc_3v3>;
-+	status = "okay";
-+};
-+
-+&saradc {
-+	vref-supply = <&vcca_1v8>;
-+	status = "okay";
-+};
-+
-+&sdhci {
-+	bus-width = <8>;
-+	max-frequency = <200000000>;
-+	non-removable;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-+	status = "okay";
-+};
-+
-+&sdmmc0 {
-+	bus-width = <4>;
-+	cap-sd-highspeed;
-+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-+	disable-wp;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-+	sd-uhs-sdr104;
-+	vmmc-supply = <&vcc3v3_sd>;
-+	vqmmc-supply = <&vccio_sd>;
-+	status = "okay";
-+};
-+
-+&tsadc {
-+        status = "okay";
-+};
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&vop {
-+	status = "okay";
-+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+};
-+
-+&vop_mmu {
-+	status = "okay";
-+};
-+
-+&hdmi_in_vp0 {
-+	status = "okay";
-+};
-+
-+&vp0_out_hdmi {
-+	status = "okay";
-+};
-+
-+&hdmi_sound {
-+	status = "okay";
-+};
-+
-+&gpu {
-+	mali-supply = <&vdd_gpu>;
-+	status = "okay";
-+};
-+
-+&u2phy0_host {
-+	phy-supply = <&vcc5v0_host>;
-+	status = "okay";
-+};
-+
-+&u2phy0_otg {
-+	status = "okay";
-+};
-+
-+&u2phy1_host {
-+	phy-supply = <&vcc5v0_host>;
-+	status = "okay";
-+};
-+
-+&u2phy1_otg {
-+	phy-supply = <&vcc5v0_host>;
-+	status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+	status = "okay";
-+};
-
diff --git a/00e0ee4050216dc768704c503860ac4ec82e7e41.patch b/00e0ee4050216dc768704c503860ac4ec82e7e41.patch
new file mode 100644
index 0000000..aefe6c8
--- /dev/null
+++ b/00e0ee4050216dc768704c503860ac4ec82e7e41.patch
@@ -0,0 +1,22 @@
+From 00e0ee4050216dc768704c503860ac4ec82e7e41 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Sat, 14 Oct 2023 19:14:10 +0800
+Subject: [PATCH] arm64: dts: add rootfs uuid for rk3566-box-demo
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
+index 7d468093382393..41b4cd5a4220eb 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
+@@ -26,6 +26,7 @@
+ 
+ 	chosen: chosen {
+ 		stdout-path = "serial2:1500000n8";
++		bootargs = "root=PARTUUID=614e0000-0000";
+ 	};
+ 
+ 	gmac1_clkin: external-gmac1-clock {
diff --git a/0103-silence-rapl.patch b/0103-silence-rapl.patch
deleted file mode 100644
index 3dae206..0000000
--- a/0103-silence-rapl.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Arjan van de Ven <arjan@linux.intel.com>
-Date: Mon, 14 Mar 2016 11:22:09 -0600
-Subject: [PATCH] silence rapl
-
----
- drivers/powercap/intel_rapl_common.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
-index 70d6d52bc1e2..8f49575319b5 100644
---- a/drivers/powercap/intel_rapl_common.c
-+++ b/drivers/powercap/intel_rapl_common.c
-@@ -1446,7 +1446,7 @@ static int __init rapl_init(void)
- 
- 	id = x86_match_cpu(rapl_ids);
- 	if (!id) {
--		pr_err("driver does not support CPU family %d model %d\n",
-+		pr_info("driver does not support CPU family %d model %d\n",
- 		       boot_cpu_data.x86, boot_cpu_data.x86_model);
- 
- 		return -ENODEV;
--- 
-https://clearlinux.org
-
diff --git a/0104-pci-pme-wakeups.patch b/0104-pci-pme-wakeups.patch
index ec15c6c..954ab82 100644
--- a/0104-pci-pme-wakeups.patch
+++ b/0104-pci-pme-wakeups.patch
@@ -1,27 +1,12 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Arjan van de Ven <arjan@linux.intel.com>
-Date: Mon, 14 Mar 2016 11:10:58 -0600
-Subject: [PATCH] pci pme wakeups
-
-Reduce wakeups for PME checks, which are a workaround for miswired
-boards (sadly, too many of them) in laptops.
----
- drivers/pci/pci.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
-index 6427cbd0a5be..b70b330422cb 100644
---- a/drivers/pci/pci.c
-+++ b/drivers/pci/pci.c
-@@ -59,7 +59,7 @@ struct pci_pme_device {
+diff -up linux-6.5-rc1/drivers/pci/pci.c.56~ linux-6.5-rc1/drivers/pci/pci.c
+--- linux-6.5-rc1/drivers/pci/pci.c.56~	2023-07-11 11:51:51.764578834 +0200
++++ linux-6.5-rc1/drivers/pci/pci.c	2023-07-11 11:52:43.424099055 +0200
+@@ -62,7 +62,7 @@ struct pci_pme_device {
  	struct pci_dev *dev;
  };
  
 -#define PME_TIMEOUT 1000 /* How long between PME checks */
 +#define PME_TIMEOUT 4000 /* How long between PME checks */
  
- static void pci_dev_d3_sleep(struct pci_dev *dev)
- {
--- 
-https://clearlinux.org
-
+ /*
+  * Following exit from Conventional Reset, devices must be ready within 1 sec
diff --git a/0105-ksm-wakeups.patch b/0105-ksm-wakeups.patch
index 201ecd0..a602351 100644
--- a/0105-ksm-wakeups.patch
+++ b/0105-ksm-wakeups.patch
@@ -1,52 +1,33 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Arjan van de Ven <arjan@linux.intel.com>
-Date: Mon, 6 May 2019 12:57:09 -0500
-Subject: [PATCH] ksm-wakeups
-
-reduce wakeups in ksm by adding rounding (aligning) when
-the sleep times are 1 second or longer
-
-Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
----
- kernel/watchdog.c |  2 +-
- mm/ksm.c          | 11 ++++++++---
- 2 files changed, 9 insertions(+), 4 deletions(-)
-
-diff --git a/kernel/watchdog.c b/kernel/watchdog.c
-index 71109065bd8e..44ae1e267d48 100644
---- a/kernel/watchdog.c
-+++ b/kernel/watchdog.c
-@@ -41,7 +41,7 @@ unsigned long __read_mostly watchdog_enabled;
+diff -up linux-6.16-rc2/kernel/watchdog.c.54~ linux-6.16-rc2/kernel/watchdog.c
+--- linux-6.16-rc2/kernel/watchdog.c.54~	2025-06-15 22:49:41.000000000 +0200
++++ linux-6.16-rc2/kernel/watchdog.c	2025-06-18 16:05:12.520085805 +0200
+@@ -46,7 +46,7 @@ unsigned long __read_mostly watchdog_ena
  int __read_mostly watchdog_user_enabled = 1;
- int __read_mostly nmi_watchdog_user_enabled = NMI_WATCHDOG_DEFAULT;
- int __read_mostly soft_watchdog_user_enabled = 1;
+ static int __read_mostly watchdog_hardlockup_user_enabled = WATCHDOG_HARDLOCKUP_DEFAULT;
+ static int __read_mostly watchdog_softlockup_user_enabled = 1;
 -int __read_mostly watchdog_thresh = 10;
 +int __read_mostly watchdog_thresh = 40;
- static int __read_mostly nmi_watchdog_available;
+ static int __read_mostly watchdog_thresh_next;
+ static int __read_mostly watchdog_hardlockup_available;
  
- struct cpumask watchdog_cpumask __read_mostly;
-diff --git a/mm/ksm.c b/mm/ksm.c
-index 0960750bb316..3c51c716b8c5 100644
---- a/mm/ksm.c
-+++ b/mm/ksm.c
-@@ -2423,9 +2423,14 @@ static int ksm_scan_thread(void *nothing)
+diff -up linux-6.16-rc2/mm/ksm.c.54~ linux-6.16-rc2/mm/ksm.c
+--- linux-6.16-rc2/mm/ksm.c.54~	2025-06-15 22:49:41.000000000 +0200
++++ linux-6.16-rc2/mm/ksm.c	2025-06-18 16:04:19.857297578 +0200
+@@ -2685,9 +2685,14 @@ static int ksm_scan_thread(void *nothing
  
  		if (ksmd_should_run()) {
  			sleep_ms = READ_ONCE(ksm_thread_sleep_millisecs);
--			wait_event_interruptible_timeout(ksm_iter_wait,
+-			wait_event_freezable_timeout(ksm_iter_wait,
 -				sleep_ms != READ_ONCE(ksm_thread_sleep_millisecs),
 -				msecs_to_jiffies(sleep_ms));
 +			if (sleep_ms >= 1000)
-+				wait_event_interruptible_timeout(ksm_iter_wait,
++				wait_event_freezable_timeout(ksm_iter_wait,
 +					sleep_ms != READ_ONCE(ksm_thread_sleep_millisecs),
 +					msecs_to_jiffies(round_jiffies_relative(sleep_ms)));
 +			else
-+				wait_event_interruptible_timeout(ksm_iter_wait,
++				wait_event_freezable_timeout(ksm_iter_wait,
 +					sleep_ms != READ_ONCE(ksm_thread_sleep_millisecs),
 +					msecs_to_jiffies(sleep_ms));
  		} else {
  			wait_event_freezable(ksm_thread_wait,
  				ksmd_should_run() || kthread_should_stop());
--- 
-https://clearlinux.org
-
diff --git a/0106-intel_idle-tweak-cpuidle-cstates.patch b/0106-intel_idle-tweak-cpuidle-cstates.patch
deleted file mode 100644
index a3340e5..0000000
--- a/0106-intel_idle-tweak-cpuidle-cstates.patch
+++ /dev/null
@@ -1,220 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Arjan van de Ven <arjan@linux.intel.com>
-Date: Sat, 19 Mar 2016 21:32:19 -0400
-Subject: [PATCH] intel_idle: tweak cpuidle cstates
-
-Increase target_residency in cpuidle cstate
-
-Tune intel_idle to be a bit less agressive;
-Clear linux is cleaner in hygiene (wakupes) than the average linux,
-so we can afford changing these in a way that increases
-performance while keeping power efficiency
----
- drivers/idle/intel_idle.c | 44 +++++++++++++++++++--------------------
- 1 file changed, 22 insertions(+), 22 deletions(-)
-
-diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
-index 0b66e25c0e2d..406b41b387d5 100644
---- a/drivers/idle/intel_idle.c
-+++ b/drivers/idle/intel_idle.c
-@@ -511,7 +511,7 @@ static struct cpuidle_state hsw_cstates[] __initdata = {
- 		.desc = "MWAIT 0x01",
- 		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
- 		.exit_latency = 10,
--		.target_residency = 20,
-+		.target_residency = 120,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -519,7 +519,7 @@ static struct cpuidle_state hsw_cstates[] __initdata = {
- 		.desc = "MWAIT 0x10",
- 		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 33,
--		.target_residency = 100,
-+		.target_residency = 900,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -527,7 +527,7 @@ static struct cpuidle_state hsw_cstates[] __initdata = {
- 		.desc = "MWAIT 0x20",
- 		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 133,
--		.target_residency = 400,
-+		.target_residency = 1000,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -535,7 +535,7 @@ static struct cpuidle_state hsw_cstates[] __initdata = {
- 		.desc = "MWAIT 0x32",
- 		.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 166,
--		.target_residency = 500,
-+		.target_residency = 1500,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -543,7 +543,7 @@ static struct cpuidle_state hsw_cstates[] __initdata = {
- 		.desc = "MWAIT 0x40",
- 		.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 300,
--		.target_residency = 900,
-+		.target_residency = 2000,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -551,7 +551,7 @@ static struct cpuidle_state hsw_cstates[] __initdata = {
- 		.desc = "MWAIT 0x50",
- 		.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 600,
--		.target_residency = 1800,
-+		.target_residency = 5000,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -559,7 +559,7 @@ static struct cpuidle_state hsw_cstates[] __initdata = {
- 		.desc = "MWAIT 0x60",
- 		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 2600,
--		.target_residency = 7700,
-+		.target_residency = 9000,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -579,7 +579,7 @@ static struct cpuidle_state bdw_cstates[] __initdata = {
- 		.desc = "MWAIT 0x01",
- 		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
- 		.exit_latency = 10,
--		.target_residency = 20,
-+		.target_residency = 120,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -587,7 +587,7 @@ static struct cpuidle_state bdw_cstates[] __initdata = {
- 		.desc = "MWAIT 0x10",
- 		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 40,
--		.target_residency = 100,
-+		.target_residency = 1000,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -595,7 +595,7 @@ static struct cpuidle_state bdw_cstates[] __initdata = {
- 		.desc = "MWAIT 0x20",
- 		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 133,
--		.target_residency = 400,
-+		.target_residency = 1000,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -603,7 +603,7 @@ static struct cpuidle_state bdw_cstates[] __initdata = {
- 		.desc = "MWAIT 0x32",
- 		.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 166,
--		.target_residency = 500,
-+		.target_residency = 2000,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -611,7 +611,7 @@ static struct cpuidle_state bdw_cstates[] __initdata = {
- 		.desc = "MWAIT 0x40",
- 		.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 300,
--		.target_residency = 900,
-+		.target_residency = 4000,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -619,7 +619,7 @@ static struct cpuidle_state bdw_cstates[] __initdata = {
- 		.desc = "MWAIT 0x50",
- 		.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 600,
--		.target_residency = 1800,
-+		.target_residency = 7000,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -627,7 +627,7 @@ static struct cpuidle_state bdw_cstates[] __initdata = {
- 		.desc = "MWAIT 0x60",
- 		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 2600,
--		.target_residency = 7700,
-+		.target_residency = 9000,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -648,7 +648,7 @@ static struct cpuidle_state skl_cstates[] __initdata = {
- 		.desc = "MWAIT 0x01",
- 		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
- 		.exit_latency = 10,
--		.target_residency = 20,
-+		.target_residency = 120,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -656,7 +656,7 @@ static struct cpuidle_state skl_cstates[] __initdata = {
- 		.desc = "MWAIT 0x10",
- 		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 70,
--		.target_residency = 100,
-+		.target_residency = 1000,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -664,7 +664,7 @@ static struct cpuidle_state skl_cstates[] __initdata = {
- 		.desc = "MWAIT 0x20",
- 		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 85,
--		.target_residency = 200,
-+		.target_residency = 600,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -672,7 +672,7 @@ static struct cpuidle_state skl_cstates[] __initdata = {
- 		.desc = "MWAIT 0x33",
- 		.flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 124,
--		.target_residency = 800,
-+		.target_residency = 3000,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -680,7 +680,7 @@ static struct cpuidle_state skl_cstates[] __initdata = {
- 		.desc = "MWAIT 0x40",
- 		.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 200,
--		.target_residency = 800,
-+		.target_residency = 3200,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -688,7 +688,7 @@ static struct cpuidle_state skl_cstates[] __initdata = {
- 		.desc = "MWAIT 0x50",
- 		.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 480,
--		.target_residency = 5000,
-+		.target_residency = 9000,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -696,7 +696,7 @@ static struct cpuidle_state skl_cstates[] __initdata = {
- 		.desc = "MWAIT 0x60",
- 		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
- 		.exit_latency = 890,
--		.target_residency = 5000,
-+		.target_residency = 9000,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
-@@ -717,7 +717,7 @@ static struct cpuidle_state skx_cstates[] __initdata = {
- 		.desc = "MWAIT 0x01",
- 		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
- 		.exit_latency = 10,
--		.target_residency = 20,
-+		.target_residency = 300,
- 		.enter = &intel_idle,
- 		.enter_s2idle = intel_idle_s2idle, },
- 	{
--- 
-https://clearlinux.org
-
diff --git a/0109-initialize-ata-before-graphics.patch b/0109-initialize-ata-before-graphics.patch
index 85d92db..b62552d 100644
--- a/0109-initialize-ata-before-graphics.patch
+++ b/0109-initialize-ata-before-graphics.patch
@@ -1,7 +1,7 @@
-diff -up linux-5.15/drivers/Makefile.78~ linux-5.15/drivers/Makefile
---- linux-5.15/drivers/Makefile.78~	2021-10-31 21:53:10.000000000 +0100
-+++ linux-5.15/drivers/Makefile	2021-11-03 20:42:22.304893882 +0100
-@@ -60,15 +60,8 @@ obj-y				+= char/
+diff -up linux-6.8-rc3/drivers/Makefile.57~ linux-6.8-rc3/drivers/Makefile
+--- linux-6.8-rc3/drivers/Makefile.57~	2024-02-04 13:20:36.000000000 +0100
++++ linux-6.8-rc3/drivers/Makefile	2024-02-09 15:19:15.282465061 +0100
+@@ -66,14 +66,8 @@ obj-y				+= char/
  # iommu/ comes before gpu as gpu are using iommu controllers
  obj-y				+= iommu/
  
@@ -10,14 +10,13 @@ diff -up linux-5.15/drivers/Makefile.78~ linux-5.15/drivers/Makefile
 -
  obj-$(CONFIG_CONNECTOR)		+= connector/
  
--# i810fb and intelfb depend on char/agp/
+-# i810fb depends on char/agp/
 -obj-$(CONFIG_FB_I810)           += video/fbdev/i810/
--obj-$(CONFIG_FB_INTEL)          += video/fbdev/intelfb/
 -
  obj-$(CONFIG_PARPORT)		+= parport/
  obj-y				+= base/ block/ misc/ mfd/ nfc/
  obj-$(CONFIG_LIBNVDIMM)		+= nvdimm/
-@@ -80,6 +73,14 @@ obj-y				+= macintosh/
+@@ -85,6 +79,13 @@ obj-y				+= macintosh/
  obj-y				+= scsi/
  obj-y				+= nvme/
  obj-$(CONFIG_ATA)		+= ata/
@@ -25,9 +24,8 @@ diff -up linux-5.15/drivers/Makefile.78~ linux-5.15/drivers/Makefile
 +# gpu/ comes after char for AGP vs DRM startup and after iommu
 +obj-y				+= gpu/
 +
-+# i810fb and intelfb depend on char/agp/
++# i810fb depends on char/agp/
 +obj-$(CONFIG_FB_I810)           += video/fbdev/i810/
-+obj-$(CONFIG_FB_INTEL)          += video/fbdev/intelfb/
 +
  obj-$(CONFIG_TARGET_CORE)	+= target/
  obj-$(CONFIG_MTD)		+= mtd/
diff --git a/0111-ipv4-tcp-allow-the-memory-tuning-for-tcp-to-go-a-lit.patch b/0111-ipv4-tcp-allow-the-memory-tuning-for-tcp-to-go-a-lit.patch
index 6050214..992bd0a 100644
--- a/0111-ipv4-tcp-allow-the-memory-tuning-for-tcp-to-go-a-lit.patch
+++ b/0111-ipv4-tcp-allow-the-memory-tuning-for-tcp-to-go-a-lit.patch
@@ -1,14 +1,12 @@
-diff -up linux-6.0-rc1/net/ipv4/tcp.c.48~ linux-6.0-rc1/net/ipv4/tcp.c
---- linux-6.0-rc1/net/ipv4/tcp.c.48~	2022-08-15 14:16:44.494026534 +0200
-+++ linux-6.0-rc1/net/ipv4/tcp.c	2022-08-15 14:18:22.288260450 +0200
-@@ -4783,8 +4783,8 @@ void __init tcp_init(void)
+diff -up linux-6.16-rc2/net/ipv4/tcp.c.57~ linux-6.16-rc2/net/ipv4/tcp.c
+--- linux-6.16-rc2/net/ipv4/tcp.c.57~	2025-06-15 22:49:41.000000000 +0200
++++ linux-6.16-rc2/net/ipv4/tcp.c	2025-06-18 16:06:40.726133163 +0200
+@@ -5226,7 +5226,7 @@ void __init tcp_init(void)
  	tcp_init_mem();
  	/* Set per-socket limits to no more than 1/128 the pressure threshold */
  	limit = nr_free_buffer_pages() << (PAGE_SHIFT - 7);
 -	max_wshare = min(4UL*1024*1024, limit);
--	max_rshare = min(6UL*1024*1024, limit);
 +	max_wshare = min(16UL*1024*1024, limit);
-+	max_rshare = min(16UL*1024*1024, limit);
+ 	max_rshare = min(32UL*1024*1024, limit);
  
  	init_net.ipv4.sysctl_tcp_wmem[0] = PAGE_SIZE;
- 	init_net.ipv4.sysctl_tcp_wmem[1] = 16*1024;
diff --git a/0120-use-lfence-instead-of-rep-and-nop.patch b/0120-use-lfence-instead-of-rep-and-nop.patch
deleted file mode 100644
index 463f384..0000000
--- a/0120-use-lfence-instead-of-rep-and-nop.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Arjan van de Ven <arjan@linux.intel.com>
-Date: Sat, 8 Dec 2018 18:21:32 +0000
-Subject: [PATCH] use lfence instead of rep and nop
-
----
- arch/x86/include/asm/vdso/processor.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/x86/include/asm/vdso/processor.h b/arch/x86/include/asm/vdso/processor.h
-index 57b1a7034c64..e2c45674f989 100644
---- a/arch/x86/include/asm/vdso/processor.h
-+++ b/arch/x86/include/asm/vdso/processor.h
-@@ -10,7 +10,7 @@
- /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
- static __always_inline void rep_nop(void)
- {
--	asm volatile("rep; nop" ::: "memory");
-+	asm volatile("lfence" ::: "memory");
- }
- 
- static __always_inline void cpu_relax(void)
--- 
-https://clearlinux.org
-
diff --git a/0124-Extend-FEC-enum.patch b/0124-Extend-FEC-enum.patch
deleted file mode 100644
index 254171c..0000000
--- a/0124-Extend-FEC-enum.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- linux-4.13/include/uapi/linux/dvb/frontend.h.0144~	2017-10-27 15:34:59.870736727 +0200
-+++ linux-4.13/include/uapi/linux/dvb/frontend.h	2017-10-27 15:35:53.337625087 +0200
-@@ -312,6 +312,8 @@ enum fe_code_rate {
- 	FEC_3_5,
- 	FEC_9_10,
- 	FEC_2_5,
-+	FEC_1_3,
-+	FEC_1_4,
- };
- 
- /**
diff --git a/046fbc970839b287d29053c7a1083e78eecb5822.patch b/046fbc970839b287d29053c7a1083e78eecb5822.patch
new file mode 100644
index 0000000..db9a5e2
--- /dev/null
+++ b/046fbc970839b287d29053c7a1083e78eecb5822.patch
@@ -0,0 +1,27 @@
+From 046fbc970839b287d29053c7a1083e78eecb5822 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Wed, 20 Dec 2023 16:06:33 +0800
+Subject: [PATCH] clk: rockchip: rk3036: make armclk as critical
+
+We found armclk maybe closed in some case,
+for example, armclk and mac_clk_ref both under
+apll, mac_clk_ref may close apll when it probe
+finished.
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ drivers/clk/rockchip/clk-rk3036.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
+index d789a09b35d080..6a9c8705e9ee22 100644
+--- a/drivers/clk/rockchip/clk-rk3036.c
++++ b/drivers/clk/rockchip/clk-rk3036.c
+@@ -429,6 +429,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
+ static const char *const rk3036_critical_clocks[] __initconst = {
+ 	"aclk_cpu",
+ 	"aclk_peri",
++	"armclk",
+ 	"hclk_peri",
+ 	"pclk_peri",
+ 	"pclk_ddrupctl",
diff --git a/06fb8acf220d3bd8d1bffe098c41fbe398b36d07.patch b/06fb8acf220d3bd8d1bffe098c41fbe398b36d07.patch
new file mode 100644
index 0000000..8bd69a3
--- /dev/null
+++ b/06fb8acf220d3bd8d1bffe098c41fbe398b36d07.patch
@@ -0,0 +1,33 @@
+From 06fb8acf220d3bd8d1bffe098c41fbe398b36d07 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Thu, 28 Nov 2024 21:02:13 +0800
+Subject: [PATCH] drm/rockchip: vop2: Add check for 32 bpp format
+
+RK3588 only support DRM_FORMAT_XRGB2101010/XBGR2101010 in afbc mode.
+
+Fixes: 5a028e8f062f ("drm/rockchip: vop2: Add support for rk3588")
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+index 69ef1ab819f59f..79dab37a52e14c 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+@@ -1154,7 +1154,15 @@ static int vop2_plane_atomic_check(struct drm_plane *plane,
+ 				return -EINVAL;
+ 			}
+ 		}
++	}
+ 
++	if (fb->format->format == DRM_FORMAT_XRGB2101010 || fb->format->format == DRM_FORMAT_XBGR2101010) {
++		if (vop2->data->soc_id == 3588) {
++			if (!rockchip_afbc(plane, fb->modifier)) {
++				drm_err(vop2->drm, "Unsupported linear 32 bpp for %s\n", win->data->name);
++				return -EINVAL;
++			}
++		}
+ 	}
+ 
+ 	/*
diff --git a/0b7853f3fa5807bfcc193af0ebe4174fb7df21f3.patch b/0b7853f3fa5807bfcc193af0ebe4174fb7df21f3.patch
new file mode 100644
index 0000000..8f59a17
--- /dev/null
+++ b/0b7853f3fa5807bfcc193af0ebe4174fb7df21f3.patch
@@ -0,0 +1,45 @@
+From 0b7853f3fa5807bfcc193af0ebe4174fb7df21f3 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Sun, 17 Dec 2023 18:32:31 +0800
+Subject: [PATCH] ARM: dts: rockchip: Add psci for rk3036
+
+The system will hang at bringup secondary CPUs
+without psci node.
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+
+Series-version: 2
+
+Cover-letter:
+Fix mainline support for rk3036 kylin board
+
+When I want to test some patch of inno hdmi driver on
+mainline, I found the support of rk3036 kylin board
+was broken by somehow:
+
+PATCH 1 is add psci dt node, as we switch to psci for
+cpu on/off for many yeas.
+PATCH 2 add stdou-path for uart boot console.
+PATCH 3 fix the emmc per board rockchip,default-sample-phase property
+issue.
+END
+---
+ arch/arm/boot/dts/rockchip/rk3036.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi
+index 89531138f30f82..7df99a0c66e4da 100644
+--- a/arch/arm/boot/dts/rockchip/rk3036.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3036.dtsi
+@@ -70,6 +70,11 @@
+ 		ports = <&vop_out>;
+ 	};
+ 
++	psci {
++		compatible = "arm,psci-1.0";
++		method = "smc";
++	};
++
+ 	timer {
+ 		compatible = "arm,armv7-timer";
+ 		arm,cpu-registers-not-fw-configured;
diff --git a/0f13fb4aa5e9aec8fcc30d4cd244a1c94a9ab01f.patch b/0f13fb4aa5e9aec8fcc30d4cd244a1c94a9ab01f.patch
new file mode 100644
index 0000000..316c876
--- /dev/null
+++ b/0f13fb4aa5e9aec8fcc30d4cd244a1c94a9ab01f.patch
@@ -0,0 +1,29 @@
+From 0f13fb4aa5e9aec8fcc30d4cd244a1c94a9ab01f Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Mon, 30 Sep 2024 09:40:01 +0800
+Subject: [PATCH] [DONT UPSTREAM]net: r8169: Force MAC address
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ drivers/net/ethernet/realtek/r8169_main.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
+index 739707a7b40fb9..180a7d6c60e36c 100644
+--- a/drivers/net/ethernet/realtek/r8169_main.c
++++ b/drivers/net/ethernet/realtek/r8169_main.c
+@@ -5329,6 +5329,14 @@ static void rtl_init_mac_address(struct rtl8169_private *tp)
+ 	if (is_valid_ether_addr(mac_addr))
+ 		goto done;
+ 
++	mac_addr[0] = 0x9A;
++	mac_addr[1] = 0x4E;
++	mac_addr[2] = 0xDA;
++	mac_addr[3] = 0x07;
++	mac_addr[4] = 0x28;
++	mac_addr[5] = 0xFC;
++	goto done;
++
+ 	eth_random_addr(mac_addr);
+ 	dev->addr_assign_type = NET_ADDR_RANDOM;
+ 	dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
diff --git a/146008b9d4241d4e14e5b173038aa78262c2bbcd.patch b/146008b9d4241d4e14e5b173038aa78262c2bbcd.patch
new file mode 100644
index 0000000..4729efc
--- /dev/null
+++ b/146008b9d4241d4e14e5b173038aa78262c2bbcd.patch
@@ -0,0 +1,57 @@
+From 146008b9d4241d4e14e5b173038aa78262c2bbcd Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Mon, 24 Jun 2024 10:32:55 +0800
+Subject: [PATCH] arm64: rockchip_defconfig: Enable NLS_ISO8859_1 for vfat
+ mount
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm64/configs/rockchip_defconfig | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig
+index 59bcecfd0828be..39702bc5bc7092 100644
+--- a/arch/arm64/configs/rockchip_defconfig
++++ b/arch/arm64/configs/rockchip_defconfig
+@@ -390,7 +390,7 @@ CONFIG_IONIC=m
+ CONFIG_BNA=m
+ CONFIG_QCA7000_UART=m
+ CONFIG_QCOM_EMAC=m
+-CONFIG_R8169=m
++CONFIG_R8169=y
+ CONFIG_SFC_SIENA=m
+ CONFIG_SMC91X=y
+ CONFIG_SMSC911X=y
+@@ -426,7 +426,6 @@ CONFIG_NATIONAL_PHY=m
+ CONFIG_NXP_C45_TJA11XX_PHY=m
+ CONFIG_AT803X_PHY=m
+ CONFIG_QSEMI_PHY=m
+-CONFIG_REALTEK_PHY=y
+ CONFIG_ROCKCHIP_PHY=y
+ CONFIG_SMSC_PHY=m
+ CONFIG_DP83TC811_PHY=m
+@@ -518,8 +517,6 @@ CONFIG_SERIAL_JSM=m
+ CONFIG_SERIAL_SIFIVE=m
+ CONFIG_SERIAL_SCCNXP=y
+ CONFIG_SERIAL_SCCNXP_CONSOLE=y
+-CONFIG_SERIAL_SC16IS7XX=m
+-CONFIG_SERIAL_SC16IS7XX_SPI=y
+ CONFIG_SERIAL_ALTERA_JTAGUART=m
+ CONFIG_SERIAL_ALTERA_UART=m
+ CONFIG_SERIAL_XILINX_PS_UART=y
+@@ -1045,6 +1042,7 @@ CONFIG_SQUASHFS_EMBEDDED=y
+ CONFIG_PSTORE=y
+ CONFIG_NLS_DEFAULT="utf8"
+ CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_ISO8859_1=y
+ CONFIG_UNICODE=y
+ CONFIG_KEYS_REQUEST_CACHE=y
+ CONFIG_PERSISTENT_KEYRINGS=y
+@@ -1120,7 +1118,6 @@ CONFIG_CRYPTO_USER_API_HASH=m
+ CONFIG_CRYPTO_USER_API_SKCIPHER=m
+ CONFIG_CRYPTO_USER_API_RNG=m
+ CONFIG_CRYPTO_USER_API_AEAD=m
+-CONFIG_CRYPTO_STATS=y
+ CONFIG_CRYPTO_NHPOLY1305_NEON=m
+ CONFIG_CRYPTO_CHACHA20_NEON=y
+ CONFIG_CRYPTO_GHASH_ARM64_CE=y
diff --git a/250083364dc2764b6ae61a124dfb8afc575e565a.patch b/250083364dc2764b6ae61a124dfb8afc575e565a.patch
new file mode 100644
index 0000000..89e4f03
--- /dev/null
+++ b/250083364dc2764b6ae61a124dfb8afc575e565a.patch
@@ -0,0 +1,99 @@
+From 250083364dc2764b6ae61a124dfb8afc575e565a Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Sat, 13 Apr 2024 17:34:57 +0800
+Subject: [PATCH] arm64: rockchip_defconfig: update for linux 6.9
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm64/configs/rockchip_defconfig | 20 +++++++++++---------
+ 1 file changed, 11 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig
+index 1a4d1c6fa8f81f..59bcecfd0828be 100644
+--- a/arch/arm64/configs/rockchip_defconfig
++++ b/arch/arm64/configs/rockchip_defconfig
+@@ -44,11 +44,16 @@ CONFIG_BOOT_CONFIG=y
+ CONFIG_EXPERT=y
+ CONFIG_KALLSYMS_ALL=y
+ CONFIG_PROFILING=y
+-CONFIG_CRASH_DUMP=y
+ CONFIG_ARCH_ROCKCHIP=y
++CONFIG_ARM64_ERRATUM_834220=y
++CONFIG_ARM64_ERRATUM_2441007=y
++CONFIG_ARM64_ERRATUM_1286807=y
++CONFIG_ARM64_ERRATUM_1542419=y
++CONFIG_ARM64_ERRATUM_2441009=y
+ # CONFIG_ARM64_ERRATUM_2966298 is not set
+ CONFIG_ARM64_VA_BITS_48=y
+ CONFIG_SCHED_MC=y
++CONFIG_NR_CPUS=256
+ CONFIG_NUMA=y
+ CONFIG_NODES_SHIFT=2
+ CONFIG_XEN=y
+@@ -66,9 +71,9 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+ CONFIG_CPU_FREQ_GOV_USERSPACE=y
+ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+-CONFIG_CPUFREQ_DT=m
+-CONFIG_CPUFREQ_DT_PLATDEV=y
++CONFIG_CPUFREQ_DT=y
+ CONFIG_ARM_SCPI_CPUFREQ=y
++CONFIG_ARM_ROCKCHIP_CPUFREQ=y
+ CONFIG_VIRTUALIZATION=y
+ CONFIG_KVM=y
+ CONFIG_KPROBES=y
+@@ -207,7 +212,6 @@ CONFIG_NET_ACT_GACT=m
+ CONFIG_GACT_PROB=y
+ CONFIG_NET_ACT_MIRRED=m
+ CONFIG_NET_ACT_SAMPLE=m
+-CONFIG_NET_ACT_IPT=m
+ CONFIG_NET_ACT_NAT=m
+ CONFIG_NET_ACT_PEDIT=m
+ CONFIG_NET_ACT_SIMP=m
+@@ -631,7 +635,6 @@ CONFIG_GENERIC_ADC_BATTERY=m
+ # CONFIG_CHARGER_CROS_PCHG is not set
+ CONFIG_THERMAL=y
+ CONFIG_THERMAL_STATISTICS=y
+-CONFIG_THERMAL_WRITABLE_TRIPS=y
+ CONFIG_THERMAL_GOV_FAIR_SHARE=y
+ CONFIG_THERMAL_GOV_BANG_BANG=y
+ CONFIG_THERMAL_GOV_USER_SPACE=y
+@@ -727,12 +730,12 @@ CONFIG_ROCKCHIP_INNO_HDMI=y
+ CONFIG_ROCKCHIP_LVDS=y
+ CONFIG_ROCKCHIP_RGB=y
+ CONFIG_ROCKCHIP_RK3066_HDMI=y
+-CONFIG_DRM_PANEL_EDP=y
+ CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
++CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
+ CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
+ CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
+-CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
+ CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
++CONFIG_DRM_PANEL_EDP=y
+ CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
+ CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
+ CONFIG_DRM_CHIPONE_ICN6211=m
+@@ -975,6 +978,7 @@ CONFIG_ARM_CCI_PMU=m
+ # CONFIG_ARM_CCI400_PMU is not set
+ # CONFIG_ARM_CCI5xx_PMU is not set
+ CONFIG_HISI_PCIE_PMU=m
++CONFIG_CXL_PMU=m
+ CONFIG_DAX=y
+ CONFIG_DEV_DAX=m
+ CONFIG_NVMEM_RMEM=m
+@@ -1106,7 +1110,6 @@ CONFIG_CRYPTO_VMAC=y
+ CONFIG_CRYPTO_WP512=y
+ CONFIG_CRYPTO_XCBC=y
+ CONFIG_CRYPTO_DEFLATE=y
+-CONFIG_CRYPTO_LZO=y
+ CONFIG_CRYPTO_842=m
+ CONFIG_CRYPTO_LZ4=m
+ CONFIG_CRYPTO_LZ4HC=m
+@@ -1129,7 +1132,6 @@ CONFIG_CRYPTO_SHA3_ARM64=m
+ CONFIG_CRYPTO_SM3_NEON=m
+ CONFIG_CRYPTO_SM3_ARM64_CE=m
+ CONFIG_CRYPTO_AES_ARM64=y
+-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+ CONFIG_CRYPTO_AES_ARM64_BS=y
+ CONFIG_CRYPTO_SM4_ARM64_CE=m
+ CONFIG_CRYPTO_SM4_ARM64_CE_BLK=m
diff --git a/4071b7a0642a41773d61b16ae1d02218bc25345e.patch b/4071b7a0642a41773d61b16ae1d02218bc25345e.patch
new file mode 100644
index 0000000..5205a30
--- /dev/null
+++ b/4071b7a0642a41773d61b16ae1d02218bc25345e.patch
@@ -0,0 +1,1784 @@
+From 4071b7a0642a41773d61b16ae1d02218bc25345e Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Sat, 14 Oct 2023 18:47:37 +0800
+Subject: [PATCH] arm64: rockchip_defconfig: update for linux-6.6
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm64/configs/rockchip_defconfig | 1426 ++++++++++++++++---------
+ 1 file changed, 903 insertions(+), 523 deletions(-)
+
+diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig
+index 46f97961dee1db..3765667cb9e087 100644
+--- a/arch/arm64/configs/rockchip_defconfig
++++ b/arch/arm64/configs/rockchip_defconfig
+@@ -1,23 +1,34 @@
++# CONFIG_LOCALVERSION_AUTO is not set
+ CONFIG_SYSVIPC=y
+ CONFIG_POSIX_MQUEUE=y
+-CONFIG_AUDIT=y
+-CONFIG_NO_HZ_IDLE=y
++CONFIG_USELIB=y
++CONFIG_TIME_KUNIT_TEST=m
++CONFIG_NO_HZ=y
+ CONFIG_HIGH_RES_TIMERS=y
+ CONFIG_BPF_SYSCALL=y
+ CONFIG_BPF_JIT=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_BPF_LSM=y
+ CONFIG_PREEMPT=y
+-CONFIG_IRQ_TIME_ACCOUNTING=y
+ CONFIG_BSD_PROCESS_ACCT=y
+ CONFIG_BSD_PROCESS_ACCT_V3=y
+ CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
+ CONFIG_TASK_XACCT=y
+ CONFIG_TASK_IO_ACCOUNTING=y
++# CONFIG_CPU_ISOLATION is not set
+ CONFIG_IKCONFIG=y
+ CONFIG_IKCONFIG_PROC=y
++CONFIG_IKHEADERS=m
++CONFIG_LOG_BUF_SHIFT=19
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=19
+ CONFIG_NUMA_BALANCING=y
+ CONFIG_MEMCG=y
+ CONFIG_BLK_CGROUP=y
++CONFIG_CFS_BANDWIDTH=y
++CONFIG_RT_GROUP_SCHED=y
+ CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_RDMA=y
+ CONFIG_CGROUP_FREEZER=y
+ CONFIG_CGROUP_HUGETLB=y
+ CONFIG_CPUSETS=y
+@@ -25,596 +36,817 @@ CONFIG_CGROUP_DEVICE=y
+ CONFIG_CGROUP_CPUACCT=y
+ CONFIG_CGROUP_PERF=y
+ CONFIG_CGROUP_BPF=y
++CONFIG_NAMESPACES=y
+ CONFIG_USER_NS=y
+ CONFIG_SCHED_AUTOGROUP=y
+-CONFIG_BLK_DEV_INITRD=y
++CONFIG_RELAY=y
++CONFIG_BOOT_CONFIG=y
++CONFIG_EXPERT=y
+ CONFIG_KALLSYMS_ALL=y
+ CONFIG_PROFILING=y
++CONFIG_CRASH_DUMP=y
+ CONFIG_ARCH_ROCKCHIP=y
++# CONFIG_ARM64_ERRATUM_2966298 is not set
+ CONFIG_ARM64_VA_BITS_48=y
+ CONFIG_SCHED_MC=y
+-CONFIG_SCHED_SMT=y
+ CONFIG_NUMA=y
+-CONFIG_KEXEC=y
+-CONFIG_KEXEC_FILE=y
+-CONFIG_CRASH_DUMP=y
++CONFIG_NODES_SHIFT=2
+ CONFIG_XEN=y
+ CONFIG_COMPAT=y
+-CONFIG_RANDOMIZE_BASE=y
++CONFIG_ARMV8_DEPRECATED=y
++CONFIG_SWP_EMULATION=y
++CONFIG_CP15_BARRIER_EMULATION=y
++CONFIG_SETEND_EMULATION=y
+ CONFIG_HIBERNATION=y
+-CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+-CONFIG_ENERGY_MODEL=y
+-CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_CPU_IDLE=y
+ CONFIG_CPU_FREQ=y
+ CONFIG_CPU_FREQ_STAT=y
+-CONFIG_CPU_FREQ_GOV_POWERSAVE=m
++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+ CONFIG_CPU_FREQ_GOV_USERSPACE=y
+-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+-CONFIG_CPUFREQ_DT=y
+-CONFIG_ACPI_CPPC_CPUFREQ=m
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
++CONFIG_CPUFREQ_DT=m
++CONFIG_CPUFREQ_DT_PLATDEV=y
+ CONFIG_ARM_SCPI_CPUFREQ=y
+-CONFIG_ARM_SCMI_CPUFREQ=y
+-CONFIG_ACPI=y
+-CONFIG_ACPI_HOTPLUG_MEMORY=y
+-CONFIG_ACPI_HMAT=y
+-CONFIG_ACPI_APEI=y
+-CONFIG_ACPI_APEI_GHES=y
+-CONFIG_ACPI_APEI_PCIEAER=y
+-CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+-CONFIG_ACPI_APEI_EINJ=y
+ CONFIG_VIRTUALIZATION=y
+ CONFIG_KVM=y
++CONFIG_KPROBES=y
+ CONFIG_JUMP_LABEL=y
+ CONFIG_MODULES=y
+ CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++CONFIG_BLK_DEV_ZONED=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
+ # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++CONFIG_BINFMT_MISC=m
++CONFIG_ZSWAP=y
++CONFIG_ZSWAP_DEFAULT_ON=y
++CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
++CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD=y
++CONFIG_ZBUD=y
++CONFIG_ZSMALLOC=y
+ # CONFIG_COMPAT_BRK is not set
+-CONFIG_MEMORY_HOTPLUG=y
+-CONFIG_MEMORY_HOTREMOVE=y
+ CONFIG_KSM=y
+-CONFIG_MEMORY_FAILURE=y
+ CONFIG_TRANSPARENT_HUGEPAGE=y
++CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
++CONFIG_CMA=y
++CONFIG_CMA_AREAS=7
++CONFIG_ANON_VMA_NAME=y
++CONFIG_LRU_GEN=y
++CONFIG_LRU_GEN_ENABLED=y
+ CONFIG_NET=y
+ CONFIG_PACKET=y
+ CONFIG_UNIX=y
++CONFIG_XDP_SOCKETS=y
+ CONFIG_INET=y
+ CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_IP_FIB_TRIE_STATS=y
++CONFIG_IP_MULTIPLE_TABLES=y
++CONFIG_IP_ROUTE_MULTIPATH=y
++CONFIG_IP_ROUTE_VERBOSE=y
+ CONFIG_IP_PNP=y
+ CONFIG_IP_PNP_DHCP=y
+ CONFIG_IP_PNP_BOOTP=y
+-CONFIG_IPV6=m
++CONFIG_IP_PNP_RARP=y
++CONFIG_IP_MROUTE=y
++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
++CONFIG_IP_PIMSM_V1=y
++CONFIG_IP_PIMSM_V2=y
++CONFIG_SYN_COOKIES=y
++CONFIG_NET_FOU=m
++# CONFIG_INET_DIAG is not set
++CONFIG_TCP_CONG_ADVANCED=y
++# CONFIG_TCP_CONG_BIC is not set
++# CONFIG_TCP_CONG_CUBIC is not set
++# CONFIG_TCP_CONG_WESTWOOD is not set
++# CONFIG_TCP_CONG_HTCP is not set
++CONFIG_TCP_CONG_VEGAS=m
++CONFIG_TCP_MD5SIG=y
++CONFIG_IPV6_ROUTER_PREF=y
++CONFIG_IPV6_ROUTE_INFO=y
++CONFIG_IPV6_OPTIMISTIC_DAD=y
++# CONFIG_IPV6_SIT is not set
++CONFIG_IPV6_SUBTREES=y
++CONFIG_IPV6_MROUTE=y
++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
++CONFIG_IPV6_PIMSM_V2=y
++CONFIG_IPV6_SEG6_LWTUNNEL=y
++CONFIG_IPV6_SEG6_HMAC=y
++CONFIG_NETWORK_PHY_TIMESTAMPING=y
+ CONFIG_NETFILTER=y
+-CONFIG_BRIDGE_NETFILTER=m
+-CONFIG_NF_CONNTRACK=m
+-CONFIG_NF_CONNTRACK_EVENTS=y
+-CONFIG_NETFILTER_XT_MARK=m
+-CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+-CONFIG_NETFILTER_XT_TARGET_LOG=m
+-CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+-CONFIG_NETFILTER_XT_MATCH_IPVS=m
+-CONFIG_IP_VS=m
+-CONFIG_IP_NF_IPTABLES=m
+-CONFIG_IP_NF_FILTER=m
+-CONFIG_IP_NF_TARGET_REJECT=m
+-CONFIG_IP_NF_NAT=m
+-CONFIG_IP_NF_TARGET_MASQUERADE=m
+-CONFIG_IP_NF_MANGLE=m
+-CONFIG_IP6_NF_IPTABLES=m
+-CONFIG_IP6_NF_FILTER=m
+-CONFIG_IP6_NF_TARGET_REJECT=m
+-CONFIG_IP6_NF_MANGLE=m
+-CONFIG_IP6_NF_NAT=m
+-CONFIG_IP6_NF_TARGET_MASQUERADE=m
+-CONFIG_BRIDGE=m
+-CONFIG_BRIDGE_VLAN_FILTERING=y
+-CONFIG_NET_DSA=m
+-CONFIG_NET_DSA_TAG_OCELOT=m
+-CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
+-CONFIG_VLAN_8021Q=m
++CONFIG_NETFILTER_NETLINK_LOG=y
++CONFIG_NF_LOG_SYSLOG=m
++CONFIG_NETFILTER_XTABLES=m
++CONFIG_NETFILTER_XTABLES_COMPAT=y
++CONFIG_NETFILTER_XT_MATCH_ECN=m
++CONFIG_NETFILTER_XT_MATCH_HL=m
++# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
++CONFIG_NF_REJECT_IPV4=m
++CONFIG_NF_REJECT_IPV6=m
++CONFIG_BPFILTER=y
++# CONFIG_BPFILTER_UMH is not set
++CONFIG_IP_SCTP=y
++CONFIG_SCTP_DBG_OBJCNT=y
++CONFIG_SCTP_COOKIE_HMAC_SHA1=y
++CONFIG_VLAN_8021Q=y
+ CONFIG_VLAN_8021Q_GVRP=y
+ CONFIG_VLAN_8021Q_MVRP=y
+ CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=m
++CONFIG_NET_SCH_HFSC=m
++CONFIG_NET_SCH_PRIO=m
++CONFIG_NET_SCH_MULTIQ=m
++CONFIG_NET_SCH_RED=m
++CONFIG_NET_SCH_SFB=m
++CONFIG_NET_SCH_SFQ=m
++CONFIG_NET_SCH_TEQL=m
++CONFIG_NET_SCH_TBF=m
+ CONFIG_NET_SCH_CBS=m
+ CONFIG_NET_SCH_ETF=m
+ CONFIG_NET_SCH_TAPRIO=m
++CONFIG_NET_SCH_GRED=m
++CONFIG_NET_SCH_NETEM=m
++CONFIG_NET_SCH_DRR=m
+ CONFIG_NET_SCH_MQPRIO=m
++CONFIG_NET_SCH_SKBPRIO=m
++CONFIG_NET_SCH_CHOKE=m
++CONFIG_NET_SCH_QFQ=m
++CONFIG_NET_SCH_CODEL=m
++CONFIG_NET_SCH_FQ_CODEL=m
++CONFIG_NET_SCH_CAKE=m
++CONFIG_NET_SCH_FQ=m
++CONFIG_NET_SCH_HHF=m
++CONFIG_NET_SCH_PIE=m
++CONFIG_NET_SCH_FQ_PIE=m
+ CONFIG_NET_SCH_INGRESS=m
++CONFIG_NET_SCH_PLUG=m
++CONFIG_NET_SCH_ETS=m
++CONFIG_NET_SCH_DEFAULT=y
+ CONFIG_NET_CLS_BASIC=m
++CONFIG_NET_CLS_ROUTE4=m
++CONFIG_NET_CLS_FW=m
++CONFIG_NET_CLS_U32=m
++CONFIG_CLS_U32_PERF=y
++CONFIG_CLS_U32_MARK=y
++CONFIG_NET_CLS_FLOW=m
++CONFIG_NET_CLS_CGROUP=m
++CONFIG_NET_CLS_BPF=m
+ CONFIG_NET_CLS_FLOWER=m
++CONFIG_NET_CLS_MATCHALL=m
++CONFIG_NET_EMATCH=y
++CONFIG_NET_EMATCH_CMP=m
++CONFIG_NET_EMATCH_NBYTE=m
++CONFIG_NET_EMATCH_U32=m
++CONFIG_NET_EMATCH_META=m
++CONFIG_NET_EMATCH_TEXT=m
++CONFIG_NET_EMATCH_IPT=m
+ CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=m
+ CONFIG_NET_ACT_GACT=m
++CONFIG_GACT_PROB=y
+ CONFIG_NET_ACT_MIRRED=m
+-CONFIG_NET_ACT_GATE=m
+-CONFIG_QRTR_SMD=m
+-CONFIG_QRTR_TUN=m
+-CONFIG_CAN=m
+-CONFIG_BT=m
+-CONFIG_BT_HIDP=m
+-# CONFIG_BT_LE is not set
+-CONFIG_BT_LEDS=y
+-# CONFIG_BT_DEBUGFS is not set
+-CONFIG_BT_HCIBTUSB=m
+-CONFIG_BT_HCIUART=m
+-CONFIG_BT_HCIUART_LL=y
+-CONFIG_BT_HCIUART_BCM=y
+-CONFIG_BT_HCIUART_QCA=y
+-CONFIG_BT_HCIUART_MRVL=y
+-CONFIG_BT_MRVL=m
+-CONFIG_BT_MRVL_SDIO=m
+-CONFIG_CFG80211=m
+-CONFIG_MAC80211=m
+-CONFIG_MAC80211_LEDS=y
+-CONFIG_RFKILL=m
+-CONFIG_NET_9P=y
+-CONFIG_NET_9P_VIRTIO=y
+-CONFIG_NFC=m
+-CONFIG_NFC_NCI=m
+-CONFIG_NFC_S3FWRN5_I2C=m
++CONFIG_NET_ACT_SAMPLE=m
++CONFIG_NET_ACT_IPT=m
++CONFIG_NET_ACT_NAT=m
++CONFIG_NET_ACT_PEDIT=m
++CONFIG_NET_ACT_SIMP=m
++CONFIG_NET_ACT_SKBEDIT=m
++CONFIG_NET_ACT_CSUM=m
++CONFIG_NET_ACT_MPLS=m
++CONFIG_NET_ACT_VLAN=m
++CONFIG_NET_ACT_BPF=m
++CONFIG_NET_ACT_SKBMOD=m
++CONFIG_NET_ACT_IFE=m
++CONFIG_NET_ACT_TUNNEL_KEY=m
++CONFIG_NET_IFE_SKBMARK=m
++CONFIG_NET_IFE_SKBPRIO=m
++CONFIG_NET_IFE_SKBTCINDEX=m
++CONFIG_DCB=y
++CONFIG_DNS_RESOLVER=y
++CONFIG_MPLS=y
++CONFIG_NET_SWITCHDEV=y
++CONFIG_NET_L3_MASTER_DEV=y
++CONFIG_CGROUP_NET_PRIO=y
++CONFIG_NET_DROP_MONITOR=y
++CONFIG_HAMRADIO=y
++CONFIG_AX25=m
++CONFIG_NETROM=m
++CONFIG_ROSE=m
++CONFIG_MKISS=m
++CONFIG_6PACK=m
++CONFIG_BPQETHER=m
++CONFIG_BAYCOM_SER_FDX=m
++CONFIG_BAYCOM_SER_HDX=m
++CONFIG_YAM=m
++CONFIG_AF_RXRPC=y
++CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
++CONFIG_NET_IFE=y
+ CONFIG_PAGE_POOL_STATS=y
+ CONFIG_PCI=y
+ CONFIG_PCIEPORTBUS=y
+ CONFIG_PCIEAER=y
++CONFIG_PCIEASPM_PERFORMANCE=y
+ CONFIG_PCI_IOV=y
+-CONFIG_PCI_PASID=y
+ CONFIG_HOTPLUG_PCI=y
+-CONFIG_HOTPLUG_PCI_ACPI=y
+-CONFIG_PCI_HOST_GENERIC=y
+-CONFIG_PCI_XGENE=y
+-CONFIG_PCIE_ALTERA=y
+-CONFIG_PCIE_ALTERA_MSI=y
+-CONFIG_PCI_HOST_THUNDER_PEM=y
+-CONFIG_PCI_HOST_THUNDER_ECAM=y
+-CONFIG_PCI_HISI=y
++CONFIG_PCIE_ROCKCHIP_HOST=y
++CONFIG_PCIE_ROCKCHIP_EP=y
+ CONFIG_PCIE_ROCKCHIP_DW_HOST=y
+-CONFIG_PCIE_KIRIN=y
+-CONFIG_PCI_MESON=m
+ CONFIG_PCI_ENDPOINT=y
+ CONFIG_PCI_ENDPOINT_CONFIGFS=y
+-CONFIG_PCI_EPF_TEST=m
++CONFIG_PCI_EPF_NTB=m
++CONFIG_CXL_BUS=m
++# CONFIG_CXL_PCI is not set
++CONFIG_UEVENT_HELPER=y
+ CONFIG_DEVTMPFS=y
+ CONFIG_DEVTMPFS_MOUNT=y
+-CONFIG_FW_LOADER_USER_HELPER=y
+ CONFIG_BRCMSTB_GISB_ARB=y
+ CONFIG_VEXPRESS_CONFIG=y
++CONFIG_MHI_BUS=m
++CONFIG_MHI_BUS_PCI_GENERIC=m
++CONFIG_MHI_BUS_EP=m
+ CONFIG_ARM_SCMI_PROTOCOL=y
+ CONFIG_ARM_SCPI_PROTOCOL=y
++CONFIG_ARM_FFA_TRANSPORT=m
+ CONFIG_EFI_CAPSULE_LOADER=y
+-CONFIG_GNSS=m
+-CONFIG_GNSS_MTK_SERIAL=m
+ CONFIG_MTD=y
+ CONFIG_MTD_BLOCK=y
+-CONFIG_MTD_CFI=y
+-CONFIG_MTD_CFI_ADV_OPTIONS=y
+-CONFIG_MTD_CFI_INTELEXT=y
+-CONFIG_MTD_CFI_AMDSTD=y
+-CONFIG_MTD_CFI_STAA=y
+-CONFIG_MTD_PHYSMAP=y
+-CONFIG_MTD_PHYSMAP_OF=y
+-CONFIG_MTD_DATAFLASH=y
+-CONFIG_MTD_SST25L=y
+-CONFIG_MTD_RAW_NAND=y
+-CONFIG_MTD_NAND_DENALI_DT=y
+-CONFIG_MTD_NAND_BRCMNAND=m
+-CONFIG_MTD_NAND_BRCMNAND_BCMBCA=m
+-CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=m
+-CONFIG_MTD_NAND_BRCMNAND_IPROC=m
+ CONFIG_MTD_SPI_NOR=y
++CONFIG_MTD_HYPERBUS=m
++CONFIG_OF_OVERLAY=y
++CONFIG_ZRAM=m
++CONFIG_ZRAM_WRITEBACK=y
+ CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_DRBD=m
+ CONFIG_BLK_DEV_NBD=m
++CONFIG_BLK_DEV_RAM=m
++CONFIG_BLK_DEV_RAM_COUNT=8
++CONFIG_ATA_OVER_ETH=m
++CONFIG_XEN_BLKDEV_BACKEND=m
+ CONFIG_VIRTIO_BLK=y
+-CONFIG_BLK_DEV_NVME=m
++CONFIG_BLK_DEV_RBD=m
++CONFIG_BLK_DEV_NVME=y
++CONFIG_NVME_MULTIPATH=y
++CONFIG_NVME_HWMON=y
++CONFIG_NVME_FC=m
++CONFIG_NVME_TARGET=m
++CONFIG_NVME_TARGET_LOOP=m
++CONFIG_NVME_TARGET_FC=m
+ CONFIG_SRAM=y
+-CONFIG_PCI_ENDPOINT_TEST=m
+ CONFIG_EEPROM_AT24=m
+ CONFIG_EEPROM_AT25=m
+-CONFIG_UACCE=m
++CONFIG_EEPROM_LEGACY=m
++CONFIG_EEPROM_93CX6=m
++CONFIG_EEPROM_EE1004=m
+ # CONFIG_SCSI_PROC_FS is not set
+ CONFIG_BLK_DEV_SD=y
++CONFIG_BLK_DEV_SR=m
++CONFIG_CHR_DEV_SG=m
+ CONFIG_SCSI_SAS_ATA=y
++CONFIG_ISCSI_TCP=m
+ CONFIG_SCSI_HISI_SAS=y
+-CONFIG_SCSI_HISI_SAS_PCI=y
+-CONFIG_MEGARAID_SAS=y
+-CONFIG_SCSI_MPT3SAS=m
++CONFIG_SCSI_MPT2SAS=m
++CONFIG_SCSI_MPI3MR=m
++CONFIG_SCSI_FDOMAIN_PCI=m
+ CONFIG_ATA=y
+ CONFIG_SATA_AHCI=y
+ CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_DWC=y
+ CONFIG_AHCI_CEVA=y
+-CONFIG_AHCI_XGENE=y
+-CONFIG_AHCI_QORIQ=y
+ CONFIG_SATA_SIL24=y
+ CONFIG_PATA_OF_PLATFORM=y
+ CONFIG_MD=y
+-CONFIG_BLK_DEV_MD=m
++CONFIG_MD_LINEAR=m
++CONFIG_MD_MULTIPATH=m
++CONFIG_MD_FAULTY=m
++CONFIG_BCACHE=y
+ CONFIG_BLK_DEV_DM=m
++CONFIG_DM_UNSTRIPED=m
++CONFIG_DM_CRYPT=m
++CONFIG_DM_SNAPSHOT=m
++CONFIG_DM_THIN_PROVISIONING=m
++CONFIG_DM_CACHE=m
++CONFIG_DM_WRITECACHE=m
++CONFIG_DM_ERA=m
++CONFIG_DM_CLONE=m
+ CONFIG_DM_MIRROR=m
++CONFIG_DM_LOG_USERSPACE=m
++CONFIG_DM_RAID=m
+ CONFIG_DM_ZERO=m
++CONFIG_DM_MULTIPATH=m
++CONFIG_DM_MULTIPATH_QL=m
++CONFIG_DM_MULTIPATH_ST=m
++CONFIG_DM_MULTIPATH_IOA=m
++CONFIG_DM_DELAY=m
++CONFIG_DM_DUST=m
++CONFIG_DM_UEVENT=y
++CONFIG_DM_FLAKEY=m
++CONFIG_DM_VERITY=m
++CONFIG_DM_VERITY_FEC=y
++CONFIG_DM_SWITCH=m
++CONFIG_DM_LOG_WRITES=m
++CONFIG_DM_INTEGRITY=m
++CONFIG_DM_ZONED=m
+ CONFIG_NETDEVICES=y
+-CONFIG_MACVLAN=m
+-CONFIG_MACVTAP=m
+ CONFIG_TUN=y
+-CONFIG_VETH=m
+-CONFIG_VIRTIO_NET=y
+-CONFIG_B53_SRAB_DRIVER=m
+-CONFIG_NET_DSA_BCM_SF2=m
++CONFIG_TUN_VNET_CROSS_LE=y
+ CONFIG_AMD_XGBE=y
++CONFIG_AQTION=m
++CONFIG_SPI_AX88796C=m
++CONFIG_ATL2=m
++CONFIG_ATL1=m
++CONFIG_ATL1E=m
+ CONFIG_ATL1C=m
++CONFIG_ALX=m
++CONFIG_B44=m
+ CONFIG_BCMGENET=m
++CONFIG_CNIC=m
++CONFIG_TIGON3=m
+ CONFIG_BNX2X=m
+ CONFIG_SYSTEMPORT=m
++CONFIG_BNXT=m
+ CONFIG_MACB=y
+ CONFIG_THUNDER_NIC_PF=y
++CONFIG_CAVIUM_PTP=y
++CONFIG_DL2K=m
++CONFIG_TSNEP=m
+ CONFIG_HIX5HD2_GMAC=y
+ CONFIG_HNS_DSAF=y
+ CONFIG_HNS_ENET=y
+-CONFIG_HNS3=y
+-CONFIG_HNS3_HCLGE=y
+-CONFIG_HNS3_ENET=y
+-CONFIG_E1000=y
+ CONFIG_E1000E=y
+ CONFIG_IGB=y
+ CONFIG_IGBVF=y
++CONFIG_IXGBE=m
++CONFIG_LITEX_LITEETH=m
+ CONFIG_MVMDIO=y
+ CONFIG_SKY2=y
+-CONFIG_MLX4_EN=m
+-CONFIG_MLX5_CORE=m
+-CONFIG_MLX5_CORE_EN=y
++CONFIG_OCTEONTX2_PF=m
++CONFIG_OCTEONTX2_VF=m
++CONFIG_OCTEON_EP=m
++CONFIG_ENC28J60=m
++CONFIG_ENC28J60_WRITEVERIFY=y
++CONFIG_LAN966X_SWITCH=m
++CONFIG_MSCC_OCELOT_SWITCH=m
++CONFIG_IONIC=m
++CONFIG_BNA=m
++CONFIG_QCA7000_UART=m
+ CONFIG_QCOM_EMAC=m
+-CONFIG_RMNET=m
+ CONFIG_R8169=m
++CONFIG_SFC_SIENA=m
+ CONFIG_SMC91X=y
+ CONFIG_SMSC911X=y
+-CONFIG_STMMAC_ETH=m
+-CONFIG_AQUANTIA_PHY=y
++CONFIG_STMMAC_ETH=y
++CONFIG_DWMAC_LOONGSON=m
++CONFIG_MSE102X=m
++CONFIG_XILINX_EMACLITE=m
++CONFIG_XILINX_AXI_EMAC=m
++CONFIG_XILINX_LL_TEMAC=m
++CONFIG_LED_TRIGGER_PHY=y
++CONFIG_SFP=m
++CONFIG_AMD_PHY=m
++CONFIG_ADIN_PHY=m
++CONFIG_ADIN1100_PHY=m
++CONFIG_AQUANTIA_PHY=m
++CONFIG_AX88796B_PHY=m
+ CONFIG_BROADCOM_PHY=m
+-CONFIG_BCM54140_PHY=m
++CONFIG_BCM84881_PHY=m
++CONFIG_BCM87XX_PHY=m
++CONFIG_CICADA_PHY=m
++CONFIG_DAVICOM_PHY=m
++CONFIG_ICPLUS_PHY=m
++CONFIG_LXT_PHY=m
++CONFIG_LSI_ET1011C_PHY=m
+ CONFIG_MARVELL_PHY=m
+-CONFIG_MARVELL_10G_PHY=y
++CONFIG_MARVELL_10G_PHY=m
++CONFIG_MARVELL_88X2222_PHY=m
++CONFIG_MAXLINEAR_GPHY=m
++CONFIG_MEDIATEK_GE_PHY=m
+ CONFIG_MICREL_PHY=y
+-CONFIG_MICROSEMI_PHY=y
+-CONFIG_AT803X_PHY=y
++CONFIG_MICROCHIP_PHY=m
++CONFIG_MICROCHIP_T1_PHY=m
++CONFIG_MOTORCOMM_PHY=m
++CONFIG_NATIONAL_PHY=m
++CONFIG_NXP_C45_TJA11XX_PHY=m
++CONFIG_AT803X_PHY=m
++CONFIG_QSEMI_PHY=m
+ CONFIG_REALTEK_PHY=y
+ CONFIG_ROCKCHIP_PHY=y
+-CONFIG_DP83867_PHY=y
+-CONFIG_VITESSE_PHY=y
+-CONFIG_CAN_FLEXCAN=m
+-CONFIG_CAN_MCP251XFD=m
++CONFIG_SMSC_PHY=m
++CONFIG_DP83TC811_PHY=m
++CONFIG_DP83848_PHY=m
++CONFIG_DP83869_PHY=m
++CONFIG_DP83TD510_PHY=m
++CONFIG_VITESSE_PHY=m
+ CONFIG_MDIO_BITBANG=y
+-CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
++CONFIG_MDIO_MVUSB=m
++CONFIG_MDIO_MSCC_MIIM=m
++CONFIG_MDIO_IPQ8064=m
++CONFIG_MDIO_BUS_MUX_MULTIPLEXER=m
+ CONFIG_MDIO_BUS_MUX_MMIOREG=y
+-CONFIG_USB_PEGASUS=m
+-CONFIG_USB_RTL8150=m
+-CONFIG_USB_RTL8152=m
+-CONFIG_USB_LAN78XX=m
+-CONFIG_USB_USBNET=m
+-CONFIG_USB_NET_DM9601=m
+-CONFIG_USB_NET_SR9800=m
+-CONFIG_USB_NET_SMSC75XX=m
+-CONFIG_USB_NET_SMSC95XX=m
+-CONFIG_USB_NET_PLUSB=m
+-CONFIG_USB_NET_MCS7830=m
+-CONFIG_ATH10K=m
+-CONFIG_ATH10K_PCI=m
+-CONFIG_ATH10K_SDIO=m
+-CONFIG_WCN36XX=m
+-CONFIG_ATH11K=m
+-CONFIG_ATH11K_AHB=m
+-CONFIG_ATH11K_PCI=m
+-CONFIG_BRCMFMAC=m
+-CONFIG_MWIFIEX=m
+-CONFIG_MWIFIEX_SDIO=m
+-CONFIG_MWIFIEX_PCIE=m
+-CONFIG_WL18XX=m
+-CONFIG_WLCORE_SDIO=m
++CONFIG_USB_USBNET=y
++# CONFIG_USB_NET_AX8817X is not set
++# CONFIG_USB_NET_AX88179_178A is not set
++# CONFIG_USB_NET_CDC_NCM is not set
++# CONFIG_USB_NET_NET1080 is not set
++CONFIG_USB_NET_RNDIS_HOST=y
++# CONFIG_USB_NET_CDC_SUBSET is not set
++# CONFIG_USB_NET_ZAURUS is not set
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++# CONFIG_WLAN_VENDOR_BROADCOM is not set
++# CONFIG_WLAN_VENDOR_CISCO is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++# CONFIG_WLAN_VENDOR_PURELIFI is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_SILABS is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++# CONFIG_XEN_NETDEV_FRONTEND is not set
++CONFIG_INPUT_FF_MEMLESS=y
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
+ CONFIG_INPUT_EVDEV=y
+ CONFIG_KEYBOARD_ADC=m
++CONFIG_KEYBOARD_ADP5520=m
++CONFIG_KEYBOARD_QT1050=m
+ CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_PINEPHONE=m
++CONFIG_KEYBOARD_IQS62X=m
+ CONFIG_KEYBOARD_CROS_EC=y
++CONFIG_KEYBOARD_CYPRESS_SF=m
++CONFIG_INPUT_JOYSTICK=y
++CONFIG_JOYSTICK_IFORCE=m
++CONFIG_JOYSTICK_IFORCE_USB=m
++CONFIG_JOYSTICK_XPAD=m
++CONFIG_JOYSTICK_XPAD_FF=y
++CONFIG_JOYSTICK_XPAD_LEDS=y
++CONFIG_JOYSTICK_QWIIC=m
++CONFIG_JOYSTICK_SENSEHAT=m
+ CONFIG_INPUT_TOUCHSCREEN=y
+-CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+-CONFIG_TOUCHSCREEN_GOODIX=m
+-CONFIG_TOUCHSCREEN_ELAN=m
+-CONFIG_TOUCHSCREEN_EDT_FT5X06=m
+ CONFIG_INPUT_MISC=y
+-CONFIG_INPUT_PWM_BEEPER=m
+-CONFIG_INPUT_PWM_VIBRA=m
+-# CONFIG_SERIO_SERPORT is not set
++CONFIG_INPUT_UINPUT=m
++CONFIG_INPUT_RK805_PWRKEY=y
++CONFIG_INPUT_DA7280_HAPTICS=m
++CONFIG_RMI4_CORE=y
++CONFIG_RMI4_F03=y
++CONFIG_RMI4_F11=y
++CONFIG_RMI4_F12=y
++CONFIG_RMI4_F30=y
++CONFIG_SERIO_SERPORT=m
+ CONFIG_SERIO_AMBAKMI=y
+-CONFIG_LEGACY_PTY_COUNT=16
++CONFIG_LEGACY_PTY_COUNT=0
+ CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_FINTEK=y
+ CONFIG_SERIAL_8250_CONSOLE=y
+-CONFIG_SERIAL_8250_EXTENDED=y
+-CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_PCI=m
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
+ CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_8250_PERICOM=m
+ CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_AMBA_PL010=y
++CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
+ CONFIG_SERIAL_AMBA_PL011=y
+ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_SERIAL_JSM=m
++CONFIG_SERIAL_SIFIVE=m
++CONFIG_SERIAL_SCCNXP=y
++CONFIG_SERIAL_SCCNXP_CONSOLE=y
++CONFIG_SERIAL_SC16IS7XX=m
++CONFIG_SERIAL_SC16IS7XX_SPI=y
++CONFIG_SERIAL_ALTERA_JTAGUART=m
++CONFIG_SERIAL_ALTERA_UART=m
+ CONFIG_SERIAL_XILINX_PS_UART=y
+ CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+-CONFIG_SERIAL_FSL_LPUART=y
+-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+-CONFIG_SERIAL_FSL_LINFLEXUART=y
+-CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
++CONFIG_SERIAL_ARC=m
++CONFIG_SERIAL_RP2=m
++CONFIG_SERIAL_FSL_LPUART=m
++CONFIG_SERIAL_FSL_LINFLEXUART=m
++CONFIG_SERIAL_CONEXANT_DIGICOLOR=m
++CONFIG_SERIAL_SPRD=m
++CONFIG_SERIAL_LITEUART=m
++CONFIG_SERIAL_NONSTANDARD=y
++CONFIG_MOXA_INTELLIO=m
++CONFIG_MOXA_SMARTIO=m
++CONFIG_N_HDLC=m
++CONFIG_N_GSM=m
++CONFIG_NOZOMI=m
++CONFIG_NULL_TTY=m
+ CONFIG_SERIAL_DEV_BUS=y
++CONFIG_TTY_PRINTK=m
+ CONFIG_VIRTIO_CONSOLE=y
+-CONFIG_IPMI_HANDLER=m
+-CONFIG_IPMI_DEVICE_INTERFACE=m
+-CONFIG_IPMI_SI=m
+-CONFIG_TCG_TPM=y
+-CONFIG_TCG_TIS=m
+-CONFIG_TCG_TIS_SPI=m
+-CONFIG_TCG_TIS_SPI_CR50=y
+-CONFIG_TCG_TIS_I2C_CR50=m
+-CONFIG_TCG_TIS_I2C_INFINEON=y
++CONFIG_HW_RANDOM=y
++CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
++CONFIG_HW_RANDOM_CN10K=m
++CONFIG_XILLYUSB=m
+ CONFIG_I2C_CHARDEV=y
+-CONFIG_I2C_MUX=y
+-CONFIG_I2C_MUX_PCA954x=y
++CONFIG_I2C_ARB_GPIO_CHALLENGE=m
++CONFIG_I2C_MUX_GPIO=m
++CONFIG_I2C_MUX_GPMUX=m
++CONFIG_I2C_MUX_LTC4306=m
++CONFIG_I2C_MUX_PCA9541=m
++CONFIG_I2C_MUX_PCA954x=m
++CONFIG_I2C_MUX_PINCTRL=m
++CONFIG_I2C_MUX_REG=m
++CONFIG_I2C_DEMUX_PINCTRL=m
++CONFIG_I2C_MUX_MLXCPLD=m
+ CONFIG_I2C_CADENCE=m
++CONFIG_I2C_CBUS_GPIO=m
+ CONFIG_I2C_DESIGNWARE_PLATFORM=y
+-CONFIG_I2C_GPIO=m
+ CONFIG_I2C_RK3X=y
++CONFIG_I2C_DIOLAN_U2C=m
++CONFIG_I2C_DLN2=m
++CONFIG_I2C_CP2615=m
++CONFIG_I2C_ROBOTFUZZ_OSIF=m
++CONFIG_I2C_TAOS_EVM=m
++CONFIG_I2C_TINY_USB=m
+ CONFIG_I2C_CROS_EC_TUNNEL=y
++CONFIG_I2C_VIRTIO=m
++CONFIG_I2C_STUB=m
+ CONFIG_I2C_SLAVE=y
++CONFIG_I2C_SLAVE_EEPROM=m
+ CONFIG_SPI=y
+-CONFIG_SPI_CADENCE_QUADSPI=y
+-CONFIG_SPI_DESIGNWARE=m
+-CONFIG_SPI_DW_DMA=y
+-CONFIG_SPI_DW_MMIO=m
+-CONFIG_SPI_NXP_FLEXSPI=y
+ CONFIG_SPI_PL022=y
+ CONFIG_SPI_ROCKCHIP=y
+-CONFIG_SPI_SPIDEV=m
++CONFIG_SPI_SLAVE=y
+ CONFIG_SPMI=y
++CONFIG_PPS_CLIENT_LDISC=m
++CONFIG_PPS_CLIENT_GPIO=m
++# CONFIG_PTP_1588_CLOCK_KVM is not set
++CONFIG_PINCTRL_AS3722=m
+ CONFIG_PINCTRL_MAX77620=y
++CONFIG_PINCTRL_RK805=y
+ CONFIG_PINCTRL_SINGLE=y
++CONFIG_PINCTRL_STMFX=m
++CONFIG_PINCTRL_SX150X=y
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_74XX_MMIO=m
+ CONFIG_GPIO_ALTERA=m
+-CONFIG_GPIO_DWAPB=y
+-CONFIG_GPIO_MB86S7X=y
++CONFIG_GPIO_CADENCE=m
++CONFIG_GPIO_DWAPB=m
++CONFIG_GPIO_EXAR=m
++CONFIG_GPIO_GRGPIO=m
++CONFIG_GPIO_HLWD=m
++CONFIG_GPIO_LOGICVC=m
++CONFIG_GPIO_MB86S7X=m
+ CONFIG_GPIO_PL061=y
+-CONFIG_GPIO_WCD934X=m
+-CONFIG_GPIO_XGENE=y
+-CONFIG_GPIO_MAX732X=y
++CONFIG_GPIO_SYSCON=m
++CONFIG_GPIO_XILINX=y
++CONFIG_GPIO_AMD_FCH=m
++CONFIG_GPIO_ADNP=m
++CONFIG_GPIO_GW_PLD=m
++CONFIG_GPIO_MAX7300=m
++CONFIG_GPIO_MAX732X=m
+ CONFIG_GPIO_PCA953X=y
+ CONFIG_GPIO_PCA953X_IRQ=y
+-CONFIG_GPIO_BD9571MWV=m
++CONFIG_GPIO_PCF857X=m
++CONFIG_GPIO_TPIC2810=m
++CONFIG_GPIO_ADP5520=m
++CONFIG_GPIO_BD71815=m
++CONFIG_GPIO_BD71828=m
++CONFIG_GPIO_DLN2=m
+ CONFIG_GPIO_MAX77620=y
++CONFIG_GPIO_MAX77650=m
++CONFIG_GPIO_TQMX86=m
++CONFIG_GPIO_BT8XX=m
++CONFIG_GPIO_PCI_IDIO_16=m
++CONFIG_GPIO_PCIE_IDIO_24=m
++CONFIG_GPIO_RDC321X=m
++CONFIG_GPIO_74X164=m
++CONFIG_GPIO_MAX3191X=m
++CONFIG_GPIO_MAX7301=m
++CONFIG_GPIO_MC33880=m
++CONFIG_GPIO_PISOSR=m
++CONFIG_GPIO_XRA1403=m
++CONFIG_GPIO_MOCKUP=m
++CONFIG_GPIO_VIRTIO=m
++CONFIG_GPIO_SIM=m
++CONFIG_POWER_RESET_ATC260X=m
+ CONFIG_POWER_RESET_BRCMSTB=y
++CONFIG_POWER_RESET_VEXPRESS=y
+ CONFIG_POWER_RESET_XGENE=y
+ CONFIG_POWER_RESET_SYSCON=y
+-CONFIG_SYSCON_REBOOT_MODE=y
+-CONFIG_BATTERY_SBS=m
+-CONFIG_BATTERY_BQ27XXX=y
+-CONFIG_BATTERY_MAX17042=m
+-CONFIG_CHARGER_MT6360=m
+-CONFIG_CHARGER_BQ25890=m
+-CONFIG_CHARGER_BQ25980=m
+-CONFIG_SENSORS_ARM_SCMI=y
+-CONFIG_SENSORS_ARM_SCPI=y
+-CONFIG_SENSORS_GPIO_FAN=m
+-CONFIG_SENSORS_JC42=m
+-CONFIG_SENSORS_LM75=m
+-CONFIG_SENSORS_LM90=m
+-CONFIG_SENSORS_PWM_FAN=m
+-CONFIG_SENSORS_INA2XX=m
+-CONFIG_SENSORS_INA3221=m
+-CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
++CONFIG_GENERIC_ADC_BATTERY=m
++# CONFIG_CHARGER_CROS_PCHG is not set
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_WRITABLE_TRIPS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_THERMAL_GOV_USER_SPACE=y
+ CONFIG_CPU_THERMAL=y
+ CONFIG_DEVFREQ_THERMAL=y
+ CONFIG_THERMAL_EMULATION=y
+-CONFIG_ROCKCHIP_THERMAL=m
+-CONFIG_GENERIC_ADC_THERMAL=m
++CONFIG_ROCKCHIP_THERMAL=y
+ CONFIG_WATCHDOG=y
+-CONFIG_ARM_SP805_WATCHDOG=y
+-CONFIG_ARM_SBSA_WATCHDOG=y
++CONFIG_WATCHDOG_SYSFS=y
++CONFIG_SOFT_WATCHDOG=m
++CONFIG_BD957XMUF_WATCHDOG=m
++CONFIG_RAVE_SP_WATCHDOG=m
+ CONFIG_DW_WATCHDOG=y
+-CONFIG_ARM_SMC_WATCHDOG=y
+-CONFIG_MFD_BD9571MWV=y
+-CONFIG_MFD_AXP20X_I2C=y
+-CONFIG_MFD_HI6421_PMIC=y
++CONFIG_BCMA=y
++CONFIG_MFD_AS3711=y
++CONFIG_MFD_AS3722=m
++CONFIG_PMIC_ADP5520=y
++CONFIG_MFD_AAT2870_CORE=y
++CONFIG_MFD_DLN2=m
++CONFIG_MFD_IQS62X=m
+ CONFIG_MFD_MAX77620=y
+-CONFIG_MFD_MT6360=y
+-CONFIG_MFD_MT6397=y
+-CONFIG_MFD_RK808=y
++CONFIG_MFD_MAX77650=m
++CONFIG_MFD_NTXEC=m
++CONFIG_MFD_RT4831=m
++CONFIG_MFD_RT5033=m
++CONFIG_MFD_RC5T583=y
++CONFIG_MFD_RK8XX_I2C=y
++CONFIG_MFD_RK8XX_SPI=y
++CONFIG_MFD_RN5T618=m
+ CONFIG_MFD_SEC_CORE=y
+-CONFIG_MFD_WM8994=m
+-CONFIG_MFD_ROHM_BD718XX=y
+-CONFIG_MFD_WCD934X=m
++CONFIG_MFD_WL1273_CORE=m
++CONFIG_MFD_LM3533=m
++CONFIG_MFD_TQMX86=m
++CONFIG_MFD_VX855=m
++CONFIG_MFD_ROHM_BD71828=m
++CONFIG_MFD_ROHM_BD957XMUF=m
++CONFIG_MFD_ATC260X_I2C=m
++CONFIG_MFD_QCOM_PM8008=m
++CONFIG_RAVE_SP_CORE=m
++CONFIG_MFD_RSMU_I2C=m
++CONFIG_MFD_RSMU_SPI=m
++CONFIG_REGULATOR=y
+ CONFIG_REGULATOR_FIXED_VOLTAGE=y
+-CONFIG_REGULATOR_AXP20X=y
+-CONFIG_REGULATOR_BD718XX=y
+-CONFIG_REGULATOR_BD9571MWV=y
++CONFIG_REGULATOR_88PG86X=m
++CONFIG_REGULATOR_AAT2870=m
++CONFIG_REGULATOR_AS3711=m
++CONFIG_REGULATOR_AS3722=m
++CONFIG_REGULATOR_ATC260X=m
++CONFIG_REGULATOR_BD71815=m
++CONFIG_REGULATOR_BD71828=m
++CONFIG_REGULATOR_BD957XMUF=m
++CONFIG_REGULATOR_DA9121=m
+ CONFIG_REGULATOR_FAN53555=y
+ CONFIG_REGULATOR_GPIO=y
+-CONFIG_REGULATOR_HI6421V530=y
+ CONFIG_REGULATOR_MAX77620=y
+-CONFIG_REGULATOR_MAX8973=y
+-CONFIG_REGULATOR_MP8859=y
+-CONFIG_REGULATOR_MT6358=y
+-CONFIG_REGULATOR_MT6359=y
+-CONFIG_REGULATOR_MT6360=y
+-CONFIG_REGULATOR_MT6397=y
+-CONFIG_REGULATOR_PCA9450=y
+-CONFIG_REGULATOR_PF8X00=y
+-CONFIG_REGULATOR_PFUZE100=y
++CONFIG_REGULATOR_MAX77650=m
++CONFIG_REGULATOR_MAX8893=m
++CONFIG_REGULATOR_MAX20086=m
++CONFIG_REGULATOR_MCP16502=m
++CONFIG_REGULATOR_MP5416=m
++CONFIG_REGULATOR_MP8859=m
++CONFIG_REGULATOR_MP886X=m
++CONFIG_REGULATOR_MPQ7920=m
++CONFIG_REGULATOR_MT6315=m
++CONFIG_REGULATOR_PF8X00=m
+ CONFIG_REGULATOR_PWM=y
+ CONFIG_REGULATOR_QCOM_SPMI=y
++CONFIG_REGULATOR_RC5T583=m
+ CONFIG_REGULATOR_RK808=y
++CONFIG_REGULATOR_RN5T618=m
++CONFIG_REGULATOR_RT4831=m
++CONFIG_REGULATOR_RT5033=m
++CONFIG_REGULATOR_RT5759=m
++CONFIG_REGULATOR_RT6160=m
++CONFIG_REGULATOR_RT6245=m
++CONFIG_REGULATOR_RTQ2134=m
++CONFIG_REGULATOR_RTQ6752=m
+ CONFIG_REGULATOR_S2MPS11=y
+-CONFIG_REGULATOR_TPS65132=m
+-CONFIG_REGULATOR_VCTRL=m
+-CONFIG_RC_CORE=m
+-CONFIG_RC_DECODERS=y
+-CONFIG_RC_DEVICES=y
+-CONFIG_MEDIA_SUPPORT=m
+-CONFIG_MEDIA_CAMERA_SUPPORT=y
+-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+-CONFIG_MEDIA_SDR_SUPPORT=y
+-CONFIG_MEDIA_PLATFORM_SUPPORT=y
+-# CONFIG_DVB_NET is not set
+-CONFIG_MEDIA_USB_SUPPORT=y
+-CONFIG_USB_VIDEO_CLASS=m
+-CONFIG_V4L_PLATFORM_DRIVERS=y
+-CONFIG_SDR_PLATFORM_DRIVERS=y
+-CONFIG_V4L_MEM2MEM_DRIVERS=y
+-CONFIG_VIDEO_HANTRO=m
+-CONFIG_VIDEO_IMX219=m
+-CONFIG_VIDEO_OV5640=m
+-CONFIG_VIDEO_OV5645=m
++CONFIG_REGULATOR_SLG51000=m
++CONFIG_REGULATOR_SY8824X=m
++CONFIG_MEDIA_CEC_SUPPORT=y
++CONFIG_USB_PULSE8_CEC=m
++CONFIG_USB_RAINSHADOW_CEC=m
+ CONFIG_DRM=y
+-CONFIG_DRM_I2C_NXP_TDA998X=m
+-CONFIG_DRM_HDLCD=m
+-CONFIG_DRM_MALI_DISPLAY=m
+ CONFIG_DRM_KOMEDA=m
+-CONFIG_DRM_NOUVEAU=m
+ CONFIG_DRM_ROCKCHIP=y
+-# CONFIG_ROCKCHIP_VOP is not set
+ CONFIG_ROCKCHIP_VOP2=y
++CONFIG_ROCKCHIP_ANALOGIX_DP=y
+ CONFIG_ROCKCHIP_CDN_DP=y
+ CONFIG_ROCKCHIP_DW_HDMI=y
+ CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+ CONFIG_ROCKCHIP_INNO_HDMI=y
+ CONFIG_ROCKCHIP_LVDS=y
+-CONFIG_DRM_RCAR_DW_HDMI=m
+-CONFIG_DRM_RCAR_USE_LVDS=y
+-CONFIG_DRM_RCAR_USE_MIPI_DSI=y
+-CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
+-CONFIG_DRM_PANEL_LVDS=m
+-CONFIG_DRM_PANEL_SIMPLE=m
+-CONFIG_DRM_PANEL_EDP=m
+-CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
++CONFIG_ROCKCHIP_RGB=y
++CONFIG_ROCKCHIP_RK3066_HDMI=y
++CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
++CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
++CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
++CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
+ CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
+-CONFIG_DRM_PANEL_SITRONIX_ST7703=m
++CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
++CONFIG_DRM_PANEL_RONBO_RB070D30=m
++CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
++CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
++CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
++CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
++CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
++CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
++CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
++CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
++CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
++CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
++CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
++CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
++CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
++CONFIG_DRM_PANEL_SITRONIX_ST7701=m
++CONFIG_DRM_PANEL_SONY_ACX565AKM=m
++CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
++CONFIG_DRM_PANEL_TDO_TL070WSH30=m
++CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
++CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
++CONFIG_DRM_PANEL_TPO_TPG110=m
+ CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
++CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
++CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
++CONFIG_DRM_CHIPONE_ICN6211=m
++CONFIG_DRM_CROS_EC_ANX7688=m
+ CONFIG_DRM_DISPLAY_CONNECTOR=m
+ CONFIG_DRM_LONTIUM_LT8912B=m
+-CONFIG_DRM_LONTIUM_LT9611=m
++CONFIG_DRM_LONTIUM_LT9211=m
+ CONFIG_DRM_LONTIUM_LT9611UXC=m
+-CONFIG_DRM_NWL_MIPI_DSI=m
++CONFIG_DRM_ITE_IT66121=m
++CONFIG_DRM_LVDS_CODEC=m
+ CONFIG_DRM_PARADE_PS8640=m
+-CONFIG_DRM_SII902X=m
+-CONFIG_DRM_SIMPLE_BRIDGE=m
++CONFIG_DRM_SII9234=m
+ CONFIG_DRM_THINE_THC63LVD1024=m
+-CONFIG_DRM_TI_TFP410=m
+-CONFIG_DRM_TI_SN65DSI86=m
+-CONFIG_DRM_ANALOGIX_ANX7625=m
++CONFIG_DRM_TOSHIBA_TC358764=m
++CONFIG_DRM_TOSHIBA_TC358768=m
++CONFIG_DRM_TI_SN65DSI83=m
++CONFIG_DRM_TI_TPD12S015=m
++CONFIG_DRM_ANALOGIX_ANX6345=m
++CONFIG_DRM_ANALOGIX_ANX78XX=m
+ CONFIG_DRM_I2C_ADV7511=m
+-CONFIG_DRM_I2C_ADV7511_AUDIO=y
+-CONFIG_DRM_CDNS_MHDP8546=m
+-CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
+-CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
++CONFIG_DRM_CDNS_DSI=m
+ CONFIG_DRM_DW_HDMI_CEC=m
+-CONFIG_DRM_ETNAVIV=m
+-CONFIG_DRM_HISI_HIBMC=m
+-CONFIG_DRM_HISI_KIRIN=m
+-CONFIG_DRM_MXSFB=m
+-CONFIG_DRM_PL111=m
+-CONFIG_DRM_LIMA=m
+ CONFIG_DRM_PANFROST=y
+-CONFIG_DRM_TIDSS=m
+ CONFIG_FB=y
+-CONFIG_FB_MODE_HELPERS=y
+-CONFIG_FB_EFI=y
+-CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_FB_ARMCLCD=y
++CONFIG_FB_UVESA=m
++CONFIG_FIRMWARE_EDID=y
++CONFIG_LCD_CLASS_DEVICE=m
++CONFIG_LCD_OTM3225A=m
++CONFIG_BACKLIGHT_LM3533=m
+ CONFIG_BACKLIGHT_PWM=m
+-CONFIG_BACKLIGHT_LP855X=m
++CONFIG_BACKLIGHT_QCOM_WLED=m
++CONFIG_BACKLIGHT_RT4831=m
++CONFIG_BACKLIGHT_ADP5520=m
++CONFIG_BACKLIGHT_AAT2870=m
++CONFIG_BACKLIGHT_LP855X=y
++CONFIG_BACKLIGHT_AS3711=m
++CONFIG_BACKLIGHT_GPIO=m
++CONFIG_BACKLIGHT_RAVE_SP=m
++CONFIG_BACKLIGHT_LED=m
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+ CONFIG_LOGO=y
+-# CONFIG_LOGO_LINUX_MONO is not set
+-# CONFIG_LOGO_LINUX_VGA16 is not set
+-CONFIG_SOUND=y
+-CONFIG_SND=y
+-CONFIG_SND_DYNAMIC_MINORS=y
+-CONFIG_SND_ALOOP=m
+-CONFIG_SND_SOC=y
+-CONFIG_SND_SOC_FSL_ASRC=m
+-CONFIG_SND_SOC_FSL_SAI=m
+-CONFIG_SND_SOC_FSL_AUDMIX=m
+-CONFIG_SND_SOC_FSL_SSI=m
+-CONFIG_SND_SOC_FSL_SPDIF=m
+-CONFIG_SND_SOC_FSL_ESAI=m
+-CONFIG_SND_SOC_FSL_MICFIL=m
+-CONFIG_SND_SOC_FSL_EASRC=m
+-CONFIG_SND_SOC_IMX_AUDMUX=m
+-CONFIG_SND_SOC_ROCKCHIP=m
+-CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
+-CONFIG_SND_SOC_ROCKCHIP_RT5645=m
+-CONFIG_SND_SOC_RK3399_GRU_SOUND=m
+-CONFIG_SND_SOC_ADAU7002=m
+-CONFIG_SND_SOC_AK4613=m
+-CONFIG_SND_SOC_BT_SCO=m
+-CONFIG_SND_SOC_CROS_EC_CODEC=m
+-CONFIG_SND_SOC_ES7134=m
+-CONFIG_SND_SOC_ES7241=m
+-CONFIG_SND_SOC_GTM601=m
+-CONFIG_SND_SOC_MAX98927=m
+-CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
+-CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
+-CONFIG_SND_SOC_PCM3168A_I2C=m
+-CONFIG_SND_SOC_RT5640=m
+-CONFIG_SND_SOC_RT5659=m
+-CONFIG_SND_SOC_SGTL5000=m
+-CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+-CONFIG_SND_SOC_SIMPLE_MUX=m
+-CONFIG_SND_SOC_SPDIF=m
+-CONFIG_SND_SOC_TAS2552=m
+-CONFIG_SND_SOC_TAS571X=m
+-CONFIG_SND_SOC_TLV320AIC31XX=m
+-CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
+-CONFIG_SND_SOC_TS3A227E=m
+-CONFIG_SND_SOC_WCD9335=m
+-CONFIG_SND_SOC_WCD934X=m
+-CONFIG_SND_SOC_WCD938X_SDW=m
+-CONFIG_SND_SOC_WM8524=m
+-CONFIG_SND_SOC_WM8904=m
+-CONFIG_SND_SOC_WM8960=m
+-CONFIG_SND_SOC_WM8962=m
+-CONFIG_SND_SOC_WM8978=m
+-CONFIG_SND_SOC_WSA881X=m
+-CONFIG_SND_SOC_MT6358=m
+-CONFIG_SND_SOC_NAU8822=m
+-CONFIG_SND_SOC_LPASS_WSA_MACRO=m
+-CONFIG_SND_SOC_LPASS_VA_MACRO=m
+-CONFIG_SND_SOC_LPASS_RX_MACRO=m
+-CONFIG_SND_SOC_LPASS_TX_MACRO=m
+-CONFIG_SND_SIMPLE_CARD=m
+-CONFIG_SND_AUDIO_GRAPH_CARD=m
+-CONFIG_SND_AUDIO_GRAPH_CARD2=m
+-CONFIG_HID_MULTITOUCH=m
+-CONFIG_I2C_HID_ACPI=m
++CONFIG_HID_BATTERY_STRENGTH=y
++CONFIG_HIDRAW=y
++CONFIG_UHID=m
++CONFIG_HID_PID=y
++CONFIG_USB_HIDDEV=y
+ CONFIG_I2C_HID_OF=m
+-CONFIG_USB_CONN_GPIO=y
++CONFIG_I2C_HID_OF_GOODIX=m
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB_CONN_GPIO=m
+ CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+ CONFIG_USB_OTG=y
++CONFIG_USB_LEDS_TRIGGER_USBPORT=y
+ CONFIG_USB_XHCI_HCD=y
+-CONFIG_USB_XHCI_PCI_RENESAS=m
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_HCD_PLATFORM=y
+ CONFIG_USB_OHCI_HCD=y
+ CONFIG_USB_OHCI_HCD_PLATFORM=y
+-CONFIG_USB_ACM=m
+ CONFIG_USB_STORAGE=y
+-CONFIG_USB_CDNS_SUPPORT=m
+-CONFIG_USB_CDNS3=m
+-CONFIG_USB_CDNS3_GADGET=y
+-CONFIG_USB_CDNS3_HOST=y
+-CONFIG_USB_MUSB_HDRC=y
+ CONFIG_USB_DWC3=y
+ CONFIG_USB_DWC2=y
++CONFIG_USB_DWC2_PCI=m
+ CONFIG_USB_CHIPIDEA=y
+ CONFIG_USB_CHIPIDEA_UDC=y
+ CONFIG_USB_CHIPIDEA_HOST=y
+ CONFIG_USB_ISP1760=y
+ CONFIG_USB_SERIAL=m
+-CONFIG_USB_SERIAL_CP210X=m
+-CONFIG_USB_SERIAL_FTDI_SIO=m
+-CONFIG_USB_SERIAL_OPTION=m
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_EZUSB_FX2=m
+ CONFIG_USB_HSIC_USB3503=y
+ CONFIG_NOP_USB_XCEIV=y
+ CONFIG_USB_ULPI=y
+ CONFIG_USB_GADGET=y
+-CONFIG_USB_SNP_UDC_PLAT=y
+-CONFIG_USB_BDC_UDC=y
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_AMD5536UDC=m
++CONFIG_USB_NET2280=m
++CONFIG_USB_GOKU=m
++CONFIG_USB_EG20T=m
++CONFIG_USB_MAX3420_UDC=m
+ CONFIG_USB_CONFIGFS=m
+ CONFIG_USB_CONFIGFS_SERIAL=y
+ CONFIG_USB_CONFIGFS_ACM=y
+@@ -625,245 +857,393 @@ CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+ CONFIG_USB_CONFIGFS_RNDIS=y
+ CONFIG_USB_CONFIGFS_EEM=y
+ CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
+ CONFIG_USB_CONFIGFS_F_FS=y
+-CONFIG_TYPEC=m
+-CONFIG_TYPEC_TCPM=m
+-CONFIG_TYPEC_TCPCI=m
+-CONFIG_TYPEC_FUSB302=m
+-CONFIG_TYPEC_TPS6598X=m
+-CONFIG_TYPEC_HD3SS3220=m
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_USB_ZERO=m
++CONFIG_USB_ETH=m
++CONFIG_USB_ETH_EEM=y
++CONFIG_USB_G_NCM=m
++CONFIG_USB_GADGETFS=m
++CONFIG_USB_FUNCTIONFS=m
++CONFIG_USB_FUNCTIONFS_ETH=y
++CONFIG_USB_FUNCTIONFS_RNDIS=y
++CONFIG_USB_FUNCTIONFS_GENERIC=y
++CONFIG_USB_MASS_STORAGE=m
++CONFIG_USB_G_SERIAL=m
++CONFIG_USB_G_PRINTER=m
++CONFIG_USB_CDC_COMPOSITE=m
++CONFIG_USB_G_ACM_MS=m
++CONFIG_USB_G_MULTI=m
++CONFIG_USB_G_MULTI_CDC=y
++CONFIG_USB_G_HID=m
++CONFIG_USB_RAW_GADGET=m
+ CONFIG_MMC=y
+ CONFIG_MMC_BLOCK_MINORS=32
+ CONFIG_MMC_ARMMMCI=y
+ CONFIG_MMC_SDHCI=y
+-CONFIG_MMC_SDHCI_ACPI=y
+ CONFIG_MMC_SDHCI_PLTFM=y
+ CONFIG_MMC_SDHCI_OF_ARASAN=y
+ CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+ CONFIG_MMC_SDHCI_CADENCE=y
+-CONFIG_MMC_SDHCI_F_SDH30=y
++CONFIG_MMC_SDHCI_MILBEAUT=m
+ CONFIG_MMC_SPI=y
+ CONFIG_MMC_DW=y
+ CONFIG_MMC_DW_EXYNOS=y
+-CONFIG_MMC_DW_HI3798CV200=y
++CONFIG_MMC_DW_HI3798CV200=m
+ CONFIG_MMC_DW_K3=y
+ CONFIG_MMC_DW_ROCKCHIP=y
+-CONFIG_MMC_MTK=y
++CONFIG_MMC_HSQ=m
+ CONFIG_MMC_SDHCI_XENON=y
+-CONFIG_MMC_SDHCI_AM654=y
+-CONFIG_SCSI_UFSHCD=y
+-CONFIG_SCSI_UFSHCD_PLATFORM=y
++CONFIG_MMC_SDHCI_AM654=m
+ CONFIG_NEW_LEDS=y
+ CONFIG_LEDS_CLASS=y
+-CONFIG_LEDS_CLASS_MULTICOLOR=m
+-CONFIG_LEDS_LM3692X=m
+-CONFIG_LEDS_PCA9532=m
+ CONFIG_LEDS_GPIO=y
+-CONFIG_LEDS_PWM=y
+ CONFIG_LEDS_SYSCON=y
+-CONFIG_LEDS_QCOM_LPG=m
++CONFIG_LEDS_USER=y
++CONFIG_LEDS_TRIGGERS=y
+ CONFIG_LEDS_TRIGGER_TIMER=y
+ CONFIG_LEDS_TRIGGER_DISK=y
++CONFIG_LEDS_TRIGGER_MTD=y
+ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+ CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
+ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+ CONFIG_LEDS_TRIGGER_PANIC=y
+ CONFIG_EDAC=y
+-CONFIG_EDAC_GHES=y
++CONFIG_EDAC_DMC520=m
+ CONFIG_RTC_CLASS=y
+-CONFIG_RTC_DRV_DS1307=m
+-CONFIG_RTC_DRV_HYM8563=m
++CONFIG_RTC_LIB_KUNIT_TEST=m
++CONFIG_RTC_DRV_DS1307=y
++CONFIG_RTC_DRV_HYM8563=y
+ CONFIG_RTC_DRV_MAX77686=y
+-CONFIG_RTC_DRV_RK808=m
+-CONFIG_RTC_DRV_PCF85063=m
+-CONFIG_RTC_DRV_PCF85363=m
+-CONFIG_RTC_DRV_M41T80=m
+-CONFIG_RTC_DRV_RX8581=m
+-CONFIG_RTC_DRV_RV3028=m
+-CONFIG_RTC_DRV_RV8803=m
+-CONFIG_RTC_DRV_S5M=y
+-CONFIG_RTC_DRV_DS3232=y
+-CONFIG_RTC_DRV_PCF2127=m
++CONFIG_RTC_DRV_RK808=y
+ CONFIG_RTC_DRV_EFI=y
+-CONFIG_RTC_DRV_CROS_EC=y
+ CONFIG_RTC_DRV_PL031=y
+-CONFIG_RTC_DRV_MT6397=m
+ CONFIG_DMADEVICES=y
++CONFIG_ALTERA_MSGDMA=m
+ CONFIG_BCM_SBA_RAID=m
+-CONFIG_FSL_EDMA=y
++CONFIG_DW_AXI_DMAC=m
++CONFIG_FSL_QDMA=m
+ CONFIG_MV_XOR_V2=y
+ CONFIG_PL330_DMA=y
++CONFIG_PLX_DMA=m
+ CONFIG_QCOM_HIDMA_MGMT=y
+ CONFIG_QCOM_HIDMA=y
++CONFIG_DW_EDMA=m
++CONFIG_DW_EDMA_PCIE=m
++CONFIG_SF_PDMA=m
++CONFIG_DMABUF_SELFTESTS=m
++CONFIG_UIO=y
+ CONFIG_VFIO=y
+ CONFIG_VFIO_PCI=y
++CONFIG_VIRT_DRIVERS=y
++CONFIG_NITRO_ENCLAVES=m
+ CONFIG_VIRTIO_PCI=y
+ CONFIG_VIRTIO_BALLOON=y
++CONFIG_VIRTIO_INPUT=m
+ CONFIG_VIRTIO_MMIO=y
++CONFIG_VHOST_NET=m
+ CONFIG_XEN_GNTDEV=y
+ CONFIG_XEN_GRANT_DEV_ALLOC=y
+ CONFIG_STAGING=y
+-CONFIG_STAGING_MEDIA=y
+-CONFIG_VIDEO_MAX96712=m
++CONFIG_AD9832=m
++CONFIG_AD9834=m
+ CONFIG_CHROME_PLATFORMS=y
+ CONFIG_CROS_EC=y
+-CONFIG_CROS_EC_I2C=y
+-CONFIG_CROS_EC_SPI=y
+-CONFIG_CROS_EC_CHARDEV=m
+-CONFIG_CLK_VEXPRESS_OSC=y
++CONFIG_CLK_VEXPRESS_OSC=m
++CONFIG_LMK04832=m
+ CONFIG_COMMON_CLK_RK808=y
+ CONFIG_COMMON_CLK_SCMI=y
+ CONFIG_COMMON_CLK_SCPI=y
++CONFIG_COMMON_CLK_SI544=m
+ CONFIG_COMMON_CLK_CS2000_CP=y
+ CONFIG_COMMON_CLK_S2MPS11=y
++CONFIG_COMMON_CLK_AXI_CLKGEN=m
+ CONFIG_COMMON_CLK_XGENE=y
+ CONFIG_COMMON_CLK_PWM=y
+-CONFIG_COMMON_CLK_RS9_PCIE=y
+-CONFIG_COMMON_CLK_VC5=y
+ CONFIG_COMMON_CLK_BD718XX=m
+-CONFIG_HWSPINLOCK=y
++CONFIG_COMMON_CLK_XLNX_CLKWZRD=m
++CONFIG_MAILBOX=y
+ CONFIG_ARM_MHU=y
++CONFIG_ARM_MHU_V2=m
+ CONFIG_PLATFORM_MHU=y
+-CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
+-CONFIG_IOMMU_IO_PGTABLE_DART=y
++CONFIG_ROCKCHIP_MBOX=y
+ CONFIG_ROCKCHIP_IOMMU=y
+ CONFIG_ARM_SMMU=y
+ CONFIG_ARM_SMMU_V3=y
+-CONFIG_REMOTEPROC=y
+-CONFIG_RPMSG_CHAR=m
+-CONFIG_RPMSG_CTRL=m
+-CONFIG_RPMSG_QCOM_GLINK_RPM=y
+-CONFIG_SOUNDWIRE=m
+-CONFIG_SOUNDWIRE_QCOM=m
+ CONFIG_SOC_BRCMSTB=y
+-CONFIG_FSL_RCPM=y
++CONFIG_LITEX_SOC_CONTROLLER=m
+ CONFIG_ROCKCHIP_IODOMAIN=y
+ CONFIG_ROCKCHIP_PM_DOMAINS=y
+-CONFIG_SOC_TI=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=m
++CONFIG_DEVFREQ_GOV_POWERSAVE=m
+ CONFIG_DEVFREQ_GOV_USERSPACE=m
+ CONFIG_DEVFREQ_GOV_PASSIVE=m
++CONFIG_ARM_RK3399_DMC_DEVFREQ=y
+ CONFIG_EXTCON_PTN5150=m
+ CONFIG_EXTCON_USB_GPIO=y
+-CONFIG_EXTCON_USBC_CROS_EC=y
+-CONFIG_MEMORY=y
+ CONFIG_IIO=y
+-CONFIG_MAX9611=m
+-CONFIG_QCOM_SPMI_VADC=m
+-CONFIG_QCOM_SPMI_ADC5=m
+-CONFIG_ROCKCHIP_SARADC=m
+-CONFIG_TI_ADS1015=m
+-CONFIG_IIO_CROS_EC_SENSORS_CORE=m
+-CONFIG_IIO_CROS_EC_SENSORS=m
+-CONFIG_IIO_ST_LSM6DSX=m
+-CONFIG_IIO_CROS_EC_LIGHT_PROX=m
+-CONFIG_SENSORS_ISL29018=m
+-CONFIG_VCNL4000=m
++CONFIG_IIO_BUFFER_CB=m
++CONFIG_IIO_ST_ACCEL_3AXIS=m
++CONFIG_ROCKCHIP_SARADC=y
++CONFIG_AD3552R=m
++CONFIG_ADIS16080=m
++CONFIG_ADIS16130=m
++CONFIG_ADIS16136=m
++CONFIG_ADIS16260=m
++CONFIG_ADXRS450=m
++CONFIG_BMG160=m
++CONFIG_FXAS21002C=m
++CONFIG_MPU3050_I2C=m
++CONFIG_IIO_ST_GYRO_3AXIS=m
++CONFIG_ITG3200=m
+ CONFIG_IIO_ST_MAGN_3AXIS=m
+-CONFIG_IIO_CROS_EC_BARO=m
+-CONFIG_MPL3115=m
+ CONFIG_PWM=y
+-CONFIG_PWM_CROS_EC=m
++CONFIG_PWM_NTXEC=m
+ CONFIG_PWM_ROCKCHIP=y
+-CONFIG_PHY_XGENE=y
+-CONFIG_PHY_CADENCE_TORRENT=m
+-CONFIG_PHY_CADENCE_SIERRA=m
+-CONFIG_PHY_QCOM_USB_HS=m
++CONFIG_RESET_SIMPLE=y
++CONFIG_PHY_ROCKCHIP_DP=y
+ CONFIG_PHY_ROCKCHIP_EMMC=y
+-CONFIG_PHY_ROCKCHIP_INNO_HDMI=m
++CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
+ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+-CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m
+ CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+ CONFIG_PHY_ROCKCHIP_PCIE=y
++CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+ CONFIG_PHY_ROCKCHIP_TYPEC=y
++CONFIG_PHY_ROCKCHIP_USB=y
+ CONFIG_PHY_SAMSUNG_USB2=y
+ CONFIG_ARM_CCI_PMU=m
+-CONFIG_ARM_CCN=m
+-CONFIG_ARM_CMN=m
+-CONFIG_ARM_SMMU_V3_PMU=m
+-CONFIG_ARM_DSU_PMU=m
+-CONFIG_ARM_SPE_PMU=m
+-CONFIG_ARM_DMC620_PMU=m
+-CONFIG_HISI_PMU=y
++# CONFIG_ARM_CCI400_PMU is not set
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_HISI_PCIE_PMU=m
++CONFIG_DAX=y
++CONFIG_DEV_DAX=m
+ CONFIG_NVMEM_RMEM=m
+ CONFIG_NVMEM_ROCKCHIP_EFUSE=y
+-CONFIG_FPGA=y
+-CONFIG_FPGA_MGR_ALTERA_CVP=m
+-CONFIG_FPGA_BRIDGE=m
+-CONFIG_ALTERA_FREEZE_BRIDGE=m
+-CONFIG_FPGA_REGION=m
+-CONFIG_OF_FPGA_REGION=m
+-CONFIG_TEE=y
+-CONFIG_OPTEE=y
+-CONFIG_MUX_MMIO=y
+-CONFIG_SLIM_QCOM_CTRL=m
+-CONFIG_INTERCONNECT=y
+-CONFIG_HTE=y
++CONFIG_NVMEM_ROCKCHIP_OTP=y
++CONFIG_NVMEM_SPMI_SDAM=m
++CONFIG_NVMEM_U_BOOT_ENV=y
++CONFIG_MUX_ADG792A=m
++CONFIG_MUX_ADGS1408=m
++CONFIG_MUX_GPIO=m
++CONFIG_MUX_MMIO=m
++CONFIG_VALIDATE_FS_PARSER=y
+ CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
+ CONFIG_EXT3_FS=y
+-CONFIG_EXT4_FS_POSIX_ACL=y
+-CONFIG_BTRFS_FS=m
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_BTRFS_FS=y
+ CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_EXPORTFS_BLOCK_OPS=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FS_VERITY=y
++CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
+ CONFIG_FANOTIFY=y
+ CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+ CONFIG_QUOTA=y
+-CONFIG_AUTOFS4_FS=y
+-CONFIG_FUSE_FS=m
+-CONFIG_CUSE=m
+-CONFIG_OVERLAY_FS=m
++CONFIG_QUOTA_NETLINK_INTERFACE=y
++CONFIG_FUSE_FS=y
++CONFIG_OVERLAY_FS=y
++CONFIG_OVERLAY_FS_XINO_AUTO=y
++CONFIG_FSCACHE=m
++CONFIG_FSCACHE_STATS=y
++CONFIG_CACHEFILES=m
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_MSDOS_FS=m
+ CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_UTF8=y
++CONFIG_FAT_KUNIT_TEST=m
++CONFIG_EXFAT_FS=m
++CONFIG_NTFS3_FS=m
++CONFIG_NTFS3_LZX_XPRESS=y
++CONFIG_NTFS3_FS_POSIX_ACL=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
+ CONFIG_TMPFS_POSIX_ACL=y
+ CONFIG_HUGETLBFS=y
+-CONFIG_EFIVAR_FS=y
++CONFIG_ECRYPT_FS=y
++CONFIG_ECRYPT_FS_MESSAGING=y
+ CONFIG_SQUASHFS=y
+-CONFIG_NFS_FS=y
+-CONFIG_NFS_V4=y
+-CONFIG_NFS_V4_1=y
+-CONFIG_NFS_V4_2=y
+-CONFIG_ROOT_NFS=y
+-CONFIG_9P_FS=y
++CONFIG_SQUASHFS_FILE_DIRECT=y
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZ4=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZSTD=y
++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
++CONFIG_SQUASHFS_EMBEDDED=y
++CONFIG_PSTORE=y
++CONFIG_NLS_DEFAULT="utf8"
+ CONFIG_NLS_CODEPAGE_437=y
+-CONFIG_NLS_ISO8859_1=y
++CONFIG_UNICODE=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
+ CONFIG_SECURITY=y
+-CONFIG_CRYPTO_DES=m
++CONFIG_LSM_MMAP_MIN_ADDR=0
++CONFIG_HARDENED_USERCOPY=y
++CONFIG_FORTIFY_SOURCE=y
++CONFIG_SECURITY_SELINUX=y
++CONFIG_SECURITY_SELINUX_BOOTPARAM=y
++CONFIG_SECURITY_SMACK=y
++CONFIG_SECURITY_SMACK_NETFILTER=y
++CONFIG_SECURITY_SMACK_APPEND_SIGNALS=y
++CONFIG_SECURITY_TOMOYO=y
++CONFIG_SECURITY_APPARMOR=y
++CONFIG_SECURITY_YAMA=y
++CONFIG_SECURITY_SAFESETID=y
++CONFIG_INTEGRITY_SIGNATURE=y
++CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y
++CONFIG_INTEGRITY_PLATFORM_KEYRING=y
++CONFIG_DEFAULT_SECURITY_APPARMOR=y
++CONFIG_LSM="lockdown,yama,integrity,apparmor"
++CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y
++CONFIG_CRYPTO_USER=m
++CONFIG_CRYPTO_PCRYPT=m
++CONFIG_CRYPTO_CRYPTD=y
++CONFIG_CRYPTO_AUTHENC=y
++CONFIG_CRYPTO_TEST=m
++CONFIG_CRYPTO_ECDH=y
++CONFIG_CRYPTO_ECDSA=m
++CONFIG_CRYPTO_ECRDSA=m
++CONFIG_CRYPTO_CURVE25519=m
++CONFIG_CRYPTO_AES_TI=y
++CONFIG_CRYPTO_ANUBIS=y
++CONFIG_CRYPTO_BLOWFISH=y
++CONFIG_CRYPTO_CAMELLIA=y
++CONFIG_CRYPTO_CAST5=y
++CONFIG_CRYPTO_CAST6=y
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_FCRYPT=y
++CONFIG_CRYPTO_KHAZAD=y
++CONFIG_CRYPTO_SEED=y
++CONFIG_CRYPTO_SERPENT=y
++CONFIG_CRYPTO_TEA=y
++CONFIG_CRYPTO_TWOFISH=y
++CONFIG_CRYPTO_ADIANTUM=m
++CONFIG_CRYPTO_ARC4=m
++CONFIG_CRYPTO_CFB=m
++CONFIG_CRYPTO_KEYWRAP=m
++CONFIG_CRYPTO_LRW=m
++CONFIG_CRYPTO_OFB=m
++CONFIG_CRYPTO_PCBC=m
++CONFIG_CRYPTO_AEGIS128=m
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++CONFIG_CRYPTO_SEQIV=y
+ CONFIG_CRYPTO_ECHAINIV=y
+-CONFIG_CRYPTO_MICHAEL_MIC=m
+-CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_CMAC=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_MICHAEL_MIC=y
++CONFIG_CRYPTO_RMD160=y
++CONFIG_CRYPTO_VMAC=y
++CONFIG_CRYPTO_WP512=y
++CONFIG_CRYPTO_XCBC=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_842=m
++CONFIG_CRYPTO_LZ4=m
++CONFIG_CRYPTO_LZ4HC=m
++CONFIG_CRYPTO_ANSI_CPRNG=m
++CONFIG_CRYPTO_DRBG_HASH=y
++CONFIG_CRYPTO_DRBG_CTR=y
++CONFIG_CRYPTO_USER_API_HASH=m
++CONFIG_CRYPTO_USER_API_SKCIPHER=m
+ CONFIG_CRYPTO_USER_API_RNG=m
+-CONFIG_CRYPTO_CHACHA20_NEON=m
++CONFIG_CRYPTO_USER_API_AEAD=m
++CONFIG_CRYPTO_STATS=y
++CONFIG_CRYPTO_NHPOLY1305_NEON=m
++CONFIG_CRYPTO_CHACHA20_NEON=y
+ CONFIG_CRYPTO_GHASH_ARM64_CE=y
++CONFIG_CRYPTO_POLY1305_NEON=m
+ CONFIG_CRYPTO_SHA1_ARM64_CE=y
+ CONFIG_CRYPTO_SHA2_ARM64_CE=y
+-CONFIG_CRYPTO_SHA512_ARM64_CE=m
++CONFIG_CRYPTO_SHA512_ARM64=y
+ CONFIG_CRYPTO_SHA3_ARM64=m
++CONFIG_CRYPTO_SM3_NEON=m
+ CONFIG_CRYPTO_SM3_ARM64_CE=m
++CONFIG_CRYPTO_AES_ARM64=y
+ CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+-CONFIG_CRYPTO_AES_ARM64_BS=m
++CONFIG_CRYPTO_AES_ARM64_BS=y
++CONFIG_CRYPTO_SM4_ARM64_CE=m
++CONFIG_CRYPTO_SM4_ARM64_CE_BLK=m
++CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=m
+ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+-CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
++CONFIG_CRYPTO_DEV_ATMEL_ECC=m
++CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
++CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m
++CONFIG_CRYPTO_DEV_CAVIUM_ZIP=m
++CONFIG_CRYPTO_DEV_ROCKCHIP=m
++CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG=y
++CONFIG_CRYPTO_DEV_VIRTIO=m
++CONFIG_CRYPTO_DEV_SAFEXCEL=m
+ CONFIG_CRYPTO_DEV_CCREE=m
+-CONFIG_CRYPTO_DEV_HISI_SEC2=m
+-CONFIG_CRYPTO_DEV_HISI_ZIP=m
+-CONFIG_CRYPTO_DEV_HISI_HPRE=m
+-CONFIG_CRYPTO_DEV_HISI_TRNG=m
+-CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
+-CONFIG_INDIRECT_PIO=y
+-CONFIG_CRC_CCITT=m
+-CONFIG_CMA_SIZE_MBYTES=32
++CONFIG_CRYPTO_DEV_HISI_SEC=m
++CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
++CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG=y
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
++CONFIG_PKCS7_TEST_KEY=m
++CONFIG_SIGNED_PE_FILE_VERIFICATION=y
++CONFIG_SYSTEM_EXTRA_CERTIFICATE=y
++CONFIG_SECONDARY_TRUSTED_KEYRING=y
++CONFIG_SYSTEM_BLACKLIST_KEYRING=y
++CONFIG_CORDIC=m
++CONFIG_CRYPTO_LIB_CURVE25519=m
++CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
++CONFIG_CRC4=m
++CONFIG_XZ_DEC_TEST=m
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=128
++CONFIG_GLOB_SELFTEST=m
++CONFIG_FONTS=y
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_FONT_ACORN_8x8=y
++CONFIG_FONT_6x10=y
++CONFIG_FONT_TER16x32=y
+ CONFIG_PRINTK_TIME=y
+-CONFIG_DEBUG_KERNEL=y
+-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
+-CONFIG_DEBUG_INFO_REDUCED=y
++CONFIG_DYNAMIC_DEBUG=y
+ CONFIG_MAGIC_SYSRQ=y
+ CONFIG_DEBUG_FS=y
+-# CONFIG_SCHED_DEBUG is not set
+-# CONFIG_DEBUG_PREEMPT is not set
+-# CONFIG_FTRACE is not set
+-CONFIG_CORESIGHT=m
+-CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m
+-CONFIG_CORESIGHT_CATU=m
+-CONFIG_CORESIGHT_SINK_TPIU=m
+-CONFIG_CORESIGHT_SINK_ETBV10=m
+-CONFIG_CORESIGHT_STM=m
+-CONFIG_CORESIGHT_CPU_DEBUG=m
+-CONFIG_CORESIGHT_CTI=m
++CONFIG_DEBUG_MEMORY_INIT=y
++CONFIG_TEST_LOCKUP=m
++CONFIG_DEBUG_PREEMPT=y
++CONFIG_RCU_TORTURE_TEST=m
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++CONFIG_KUNIT=m
++CONFIG_FUNCTION_ERROR_INJECTION=y
++CONFIG_TEST_DIV64=m
++CONFIG_BACKTRACE_SELF_TEST=m
++CONFIG_TEST_REF_TRACKER=m
++CONFIG_RBTREE_TEST=m
++CONFIG_REED_SOLOMON_TEST=m
++CONFIG_INTERVAL_TREE_TEST=m
++CONFIG_PERCPU_TEST=m
++CONFIG_ASYNC_RAID6_TEST=m
++CONFIG_TEST_SCANF=m
++CONFIG_TEST_XARRAY=m
++CONFIG_TEST_VMALLOC=m
++CONFIG_TEST_BPF=m
++CONFIG_TEST_BLACKHOLE_DEV=m
++CONFIG_HASH_KUNIT_TEST=m
++CONFIG_RESOURCE_KUNIT_TEST=m
++CONFIG_CMDLINE_KUNIT_TEST=m
++CONFIG_SLUB_KUNIT_TEST=m
++CONFIG_RATIONAL_KUNIT_TEST=m
++CONFIG_MEMCPY_KUNIT_TEST=m
++CONFIG_TEST_MEMCAT_P=m
+ CONFIG_MEMTEST=y
diff --git a/516ae4f2e84130ee33375cf28fbeb95ea443620a.patch b/516ae4f2e84130ee33375cf28fbeb95ea443620a.patch
new file mode 100644
index 0000000..cf4c10e
--- /dev/null
+++ b/516ae4f2e84130ee33375cf28fbeb95ea443620a.patch
@@ -0,0 +1,199 @@
+From 516ae4f2e84130ee33375cf28fbeb95ea443620a Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Sat, 26 Oct 2024 18:46:27 +0800
+Subject: [PATCH] Revert Revert "ARM: dts: rockchip: restyle emac nodes"
+
+This revert commit 29833ca08e47 ("Revert "ARM: dts: rockchip: restyle
+emac nodes"")
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm/boot/dts/rockchip/rk3036-evb.dts     | 16 ++++++++++------
+ arch/arm/boot/dts/rockchip/rk3036-kylin.dts   | 11 ++++++++---
+ arch/arm/boot/dts/rockchip/rk3036.dtsi        |  2 --
+ .../boot/dts/rockchip/rk3066a-marsboard.dts   | 17 ++++++++++-------
+ .../boot/dts/rockchip/rk3066a-rayeager.dts    | 15 ++++++++++-----
+ .../boot/dts/rockchip/rk3188-radxarock.dts    | 19 +++++++++++--------
+ arch/arm/boot/dts/rockchip/rk3xxx.dtsi        |  3 ---
+ 7 files changed, 49 insertions(+), 34 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3036-evb.dts b/arch/arm/boot/dts/rockchip/rk3036-evb.dts
+index 94216f870b57cc..becdc0b664bfa4 100644
+--- a/arch/arm/boot/dts/rockchip/rk3036-evb.dts
++++ b/arch/arm/boot/dts/rockchip/rk3036-evb.dts
+@@ -15,16 +15,20 @@
+ };
+ 
+ &emac {
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
+ 	phy = <&phy0>;
+-	phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
+ 	phy-reset-duration = <10>; /* millisecond */
+-
++	phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
++	pinctrl-names = "default";
++	pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
+ 	status = "okay";
+ 
+-	phy0: ethernet-phy@0 {
+-		reg = <0>;
++	mdio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		phy0: ethernet-phy@0 {
++			reg = <0>;
++		};
+ 	};
+ };
+ 
+diff --git a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts
+index 270aac86a334af..ae7bf7667b6c69 100644
+--- a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts
++++ b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts
+@@ -115,12 +115,17 @@
+ 	phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
+-	phy = <&phy0>;
+ 
+ 	status = "okay";
+ 	mac-address = [ fe 46 f2 84 84 fe ];
+-	phy0: ethernet-phy@0 {
+-		reg = <0>;
++
++	mdio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		phy0: ethernet-phy@0 {
++			reg = <0>;
++		};
+ 	};
+ };
+ 
+diff --git a/arch/arm/boot/dts/rockchip/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi
+index 7df99a0c66e4da..6039a0908af1c5 100644
+--- a/arch/arm/boot/dts/rockchip/rk3036.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3036.dtsi
+@@ -236,8 +236,6 @@
+ 		compatible = "rockchip,rk3036-emac";
+ 		reg = <0x10200000 0x4000>;
+ 		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+ 		rockchip,grf = <&grf>;
+ 		clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
+ 		clock-names = "hclk", "macref", "macclk";
+diff --git a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts
+index 36ba1a45cc6343..ada7dbfc06a56b 100644
+--- a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts
++++ b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts
+@@ -150,18 +150,21 @@
+ #include "../tps65910.dtsi"
+ 
+ &emac {
+-	status = "okay";
+-
+ 	phy = <&phy0>;
+ 	phy-supply = <&vcc_rmii>;
+-
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
++	status = "okay";
++
++	mdio {
++		#address-cells = <1>;
++		#size-cells = <0>;
+ 
+-	phy0: ethernet-phy@0 {
+-		reg = <0>;
+-		interrupt-parent = <&gpio1>;
+-		interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
++		phy0: ethernet-phy@0 {
++			reg = <0>;
++			interrupt-parent = <&gpio1>;
++			interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
++		};
+ 	};
+ };
+ 
+diff --git a/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts b/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts
+index 954af67e53b63d..b0b029f146436f 100644
+--- a/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts
++++ b/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts
+@@ -142,15 +142,20 @@
+ };
+ 
+ &emac {
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
+ 	phy = <&phy0>;
+ 	phy-supply = <&vcc_rmii>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
+ 	status = "okay";
+ 
+-	phy0: ethernet-phy@0 {
+-		reg = <0>;
+-		reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
++	mdio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		phy0: ethernet-phy@0 {
++			reg = <0>;
++			reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
++		};
+ 	};
+ };
+ 
+diff --git a/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts b/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts
+index 8af552e33b8109..1f31c0a6774f78 100644
+--- a/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts
++++ b/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts
+@@ -126,18 +126,21 @@
+ };
+ 
+ &emac {
+-	status = "okay";
+-
++	phy = <&phy0>;
++	phy-supply = <&vcc_rmii>;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
++	status = "okay";
+ 
+-	phy = <&phy0>;
+-	phy-supply = <&vcc_rmii>;
++	mdio {
++		#address-cells = <1>;
++		#size-cells = <0>;
+ 
+-	phy0: ethernet-phy@0 {
+-		reg = <0>;
+-		interrupt-parent = <&gpio3>;
+-		interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
++		phy0: ethernet-phy@0 {
++			reg = <0>;
++			interrupt-parent = <&gpio3>;
++			interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
++		};
+ 	};
+ };
+ 
+diff --git a/arch/arm/boot/dts/rockchip/rk3xxx.dtsi b/arch/arm/boot/dts/rockchip/rk3xxx.dtsi
+index 327215a810b1c0..e6a78bcf916382 100644
+--- a/arch/arm/boot/dts/rockchip/rk3xxx.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3xxx.dtsi
+@@ -197,9 +197,6 @@
+ 		compatible = "rockchip,rk3066-emac";
+ 		reg = <0x10204000 0x3c>;
+ 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-
+ 		clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
+ 		clock-names = "hclk", "macref";
+ 		max-speed = <100>;
diff --git a/52a77da4f18b009c85fbfd30701b93e5fe5e715a.patch b/52a77da4f18b009c85fbfd30701b93e5fe5e715a.patch
new file mode 100644
index 0000000..25a096d
--- /dev/null
+++ b/52a77da4f18b009c85fbfd30701b93e5fe5e715a.patch
@@ -0,0 +1,51 @@
+From 52a77da4f18b009c85fbfd30701b93e5fe5e715a Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Fri, 29 Nov 2024 08:57:49 +0800
+Subject: [PATCH] drm/rockchip: vop2: Check linear format for Cluster windows
+ on rk3566/8
+
+The Cluster windows on rk3566/8 only support afbc mode.
+
+Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver")
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+index 056a9434ff876d..69ef1ab819f59f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+@@ -1095,6 +1095,7 @@ static int vop2_plane_atomic_check(struct drm_plane *plane,
+ 	struct vop2_video_port *vp;
+ 	struct vop2 *vop2;
+ 	const struct vop2_data *vop2_data;
++	struct vop2_win *win;
+ 	struct drm_rect *dest = &pstate->dst;
+ 	struct drm_rect *src = &pstate->src;
+ 	int min_scale = FRAC_16_16(1, 8);
+@@ -1108,6 +1109,7 @@ static int vop2_plane_atomic_check(struct drm_plane *plane,
+ 	vp = to_vop2_video_port(crtc);
+ 	vop2 = vp->vop2;
+ 	vop2_data = vop2->data;
++	win = to_vop2_win(plane);
+ 
+ 	cstate = drm_atomic_get_existing_crtc_state(pstate->state, crtc);
+ 	if (WARN_ON(!cstate))
+@@ -1145,6 +1147,16 @@ static int vop2_plane_atomic_check(struct drm_plane *plane,
+ 		return -EINVAL;
+ 	}
+ 
++	if (vop2->data->soc_id == 3568 || vop2->data->soc_id == 3566) {
++		if (vop2_cluster_window(win)) {
++			if (!rockchip_afbc(plane, fb->modifier)) {
++				drm_err(vop2->drm, "Unsupported linear format for %s\n", win->data->name);
++				return -EINVAL;
++			}
++		}
++
++	}
++
+ 	/*
+ 	 * Src.x1 can be odd when do clip, but yuv plane start point
+ 	 * need align with 2 pixel.
diff --git a/6.13-rc2-compile.patch b/6.13-rc2-compile.patch
new file mode 100644
index 0000000..9448299
--- /dev/null
+++ b/6.13-rc2-compile.patch
@@ -0,0 +1,14 @@
+diff -up linux-6.13-rc2/arch/x86/kernel/asm-offsets.c.omv~ linux-6.13-rc2/arch/x86/kernel/asm-offsets.c
+diff -up linux-6.13-rc2/arch/x86/kernel/relocate_kernel_64.S.omv~ linux-6.13-rc2/arch/x86/kernel/relocate_kernel_64.S
+--- linux-6.13-rc2/arch/x86/kernel/relocate_kernel_64.S.omv~	2024-12-11 14:27:49.006483262 +0100
++++ linux-6.13-rc2/arch/x86/kernel/relocate_kernel_64.S	2024-12-11 14:28:17.814723849 +0100
+@@ -13,6 +13,9 @@
+ #include <asm/pgtable_types.h>
+ #include <asm/nospec-branch.h>
+ #include <asm/unwind_hints.h>
++#ifdef CONFIG_KEXEC_JUMP
++#include <asm/asm-offsets.h>
++#endif
+ 
+ /*
+  * Must be relocatable PIC code callable as a C function, in particular
diff --git a/6d478d25de6b7550769b77edcbf8d330238542a8.patch b/6d478d25de6b7550769b77edcbf8d330238542a8.patch
new file mode 100644
index 0000000..5c2e548
--- /dev/null
+++ b/6d478d25de6b7550769b77edcbf8d330238542a8.patch
@@ -0,0 +1,74 @@
+From 6d478d25de6b7550769b77edcbf8d330238542a8 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Tue, 29 Oct 2024 14:25:23 +0800
+Subject: [PATCH] arm64: rockchip_defconfig: update for Linux 6.12
+
+Enable:
+CONFIG_ROCKCHIP_DW_HDMI_QP=y
+CONFIG_DRM_PANTHOR=y
+
+Remove:
+CONFIG_ARM_ROCKCHIP_CPUFREQ
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm64/configs/rockchip_defconfig | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig
+index e6d71cb298e87e..ae949f0148f874 100644
+--- a/arch/arm64/configs/rockchip_defconfig
++++ b/arch/arm64/configs/rockchip_defconfig
+@@ -45,7 +45,6 @@ CONFIG_EXPERT=y
+ CONFIG_KALLSYMS_ALL=y
+ CONFIG_PROFILING=y
+ CONFIG_ARCH_ROCKCHIP=y
+-CONFIG_ARM64_ERRATUM_834220=y
+ CONFIG_ARM64_ERRATUM_2441007=y
+ CONFIG_ARM64_ERRATUM_1286807=y
+ CONFIG_ARM64_ERRATUM_1542419=y
+@@ -73,9 +72,7 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+ CONFIG_CPUFREQ_DT=y
+ CONFIG_ARM_SCPI_CPUFREQ=y
+-CONFIG_ARM_ROCKCHIP_CPUFREQ=y
+ CONFIG_VIRTUALIZATION=y
+-CONFIG_KVM=y
+ CONFIG_KPROBES=y
+ CONFIG_JUMP_LABEL=y
+ CONFIG_MODULES=y
+@@ -89,7 +86,7 @@ CONFIG_BINFMT_MISC=m
+ CONFIG_ZSWAP=y
+ CONFIG_ZSWAP_DEFAULT_ON=y
+ CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
+-CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD=y
++CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD_DEPRECATED=y
+ CONFIG_ZBUD=y
+ CONFIG_ZSMALLOC=y
+ # CONFIG_COMPAT_BRK is not set
+@@ -555,7 +552,7 @@ CONFIG_I2C_DEMUX_PINCTRL=m
+ CONFIG_I2C_MUX_MLXCPLD=m
+ CONFIG_I2C_CADENCE=m
+ CONFIG_I2C_CBUS_GPIO=m
+-CONFIG_I2C_DESIGNWARE_PLATFORM=y
++CONFIG_I2C_DESIGNWARE_CORE=y
+ CONFIG_I2C_RK3X=y
+ CONFIG_I2C_DIOLAN_U2C=m
+ CONFIG_I2C_DLN2=m
+@@ -722,6 +719,7 @@ CONFIG_ROCKCHIP_VOP2=y
+ CONFIG_ROCKCHIP_ANALOGIX_DP=y
+ CONFIG_ROCKCHIP_CDN_DP=y
+ CONFIG_ROCKCHIP_DW_HDMI=y
++CONFIG_ROCKCHIP_DW_HDMI_QP=y
+ CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+ CONFIG_ROCKCHIP_INNO_HDMI=y
+ CONFIG_ROCKCHIP_LVDS=y
+@@ -756,7 +754,7 @@ CONFIG_DRM_I2C_ADV7511=m
+ CONFIG_DRM_CDNS_DSI=m
+ CONFIG_DRM_DW_HDMI_CEC=m
+ CONFIG_DRM_PANFROST=y
+-CONFIG_DRM_PANTHOR=m
++CONFIG_DRM_PANTHOR=y
+ CONFIG_DRM_POWERVR=y
+ CONFIG_FB=y
+ CONFIG_FB_UVESA=m
diff --git a/6da0ae6e419442449ffa7778de518ca37292352b.patch b/6da0ae6e419442449ffa7778de518ca37292352b.patch
new file mode 100644
index 0000000..7a66db7
--- /dev/null
+++ b/6da0ae6e419442449ffa7778de518ca37292352b.patch
@@ -0,0 +1,176 @@
+From 6da0ae6e419442449ffa7778de518ca37292352b Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Sat, 13 Apr 2024 14:48:09 +0800
+Subject: [PATCH] arm64: rockchip_defconfig: Enable edp display
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm64/configs/rockchip_defconfig | 56 ++-------------------------
+ 1 file changed, 3 insertions(+), 53 deletions(-)
+
+diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig
+index 3765667cb9e087..8d1c26296a1e2a 100644
+--- a/arch/arm64/configs/rockchip_defconfig
++++ b/arch/arm64/configs/rockchip_defconfig
+@@ -146,8 +146,6 @@ CONFIG_NETFILTER_XT_MATCH_HL=m
+ # CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+ CONFIG_NF_REJECT_IPV4=m
+ CONFIG_NF_REJECT_IPV6=m
+-CONFIG_BPFILTER=y
+-# CONFIG_BPFILTER_UMH is not set
+ CONFIG_IP_SCTP=y
+ CONFIG_SCTP_DBG_OBJCNT=y
+ CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+@@ -262,7 +260,6 @@ CONFIG_CXL_BUS=m
+ CONFIG_UEVENT_HELPER=y
+ CONFIG_DEVTMPFS=y
+ CONFIG_DEVTMPFS_MOUNT=y
+-CONFIG_BRCMSTB_GISB_ARB=y
+ CONFIG_VEXPRESS_CONFIG=y
+ CONFIG_MHI_BUS=m
+ CONFIG_MHI_BUS_PCI_GENERIC=m
+@@ -297,7 +294,6 @@ CONFIG_NVME_TARGET_FC=m
+ CONFIG_SRAM=y
+ CONFIG_EEPROM_AT24=m
+ CONFIG_EEPROM_AT25=m
+-CONFIG_EEPROM_LEGACY=m
+ CONFIG_EEPROM_93CX6=m
+ CONFIG_EEPROM_EE1004=m
+ # CONFIG_SCSI_PROC_FS is not set
+@@ -318,9 +314,6 @@ CONFIG_AHCI_CEVA=y
+ CONFIG_SATA_SIL24=y
+ CONFIG_PATA_OF_PLATFORM=y
+ CONFIG_MD=y
+-CONFIG_MD_LINEAR=m
+-CONFIG_MD_MULTIPATH=m
+-CONFIG_MD_FAULTY=m
+ CONFIG_BCACHE=y
+ CONFIG_BLK_DEV_DM=m
+ CONFIG_DM_UNSTRIPED=m
+@@ -398,10 +391,8 @@ CONFIG_SFC_SIENA=m
+ CONFIG_SMC91X=y
+ CONFIG_SMSC911X=y
+ CONFIG_STMMAC_ETH=y
+-CONFIG_DWMAC_LOONGSON=m
+ CONFIG_MSE102X=m
+ CONFIG_XILINX_EMACLITE=m
+-CONFIG_XILINX_AXI_EMAC=m
+ CONFIG_XILINX_LL_TEMAC=m
+ CONFIG_LED_TRIGGER_PHY=y
+ CONFIG_SFP=m
+@@ -457,7 +448,6 @@ CONFIG_USB_NET_RNDIS_HOST=y
+ # CONFIG_WLAN_VENDOR_ATH is not set
+ # CONFIG_WLAN_VENDOR_ATMEL is not set
+ # CONFIG_WLAN_VENDOR_BROADCOM is not set
+-# CONFIG_WLAN_VENDOR_CISCO is not set
+ # CONFIG_WLAN_VENDOR_INTEL is not set
+ # CONFIG_WLAN_VENDOR_INTERSIL is not set
+ # CONFIG_WLAN_VENDOR_MARVELL is not set
+@@ -634,7 +624,6 @@ CONFIG_GPIO_MOCKUP=m
+ CONFIG_GPIO_VIRTIO=m
+ CONFIG_GPIO_SIM=m
+ CONFIG_POWER_RESET_ATC260X=m
+-CONFIG_POWER_RESET_BRCMSTB=y
+ CONFIG_POWER_RESET_VEXPRESS=y
+ CONFIG_POWER_RESET_XGENE=y
+ CONFIG_POWER_RESET_SYSCON=y
+@@ -738,36 +727,14 @@ CONFIG_ROCKCHIP_INNO_HDMI=y
+ CONFIG_ROCKCHIP_LVDS=y
+ CONFIG_ROCKCHIP_RGB=y
+ CONFIG_ROCKCHIP_RK3066_HDMI=y
+-CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
+-CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
+-CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
++CONFIG_DRM_PANEL_EDP=y
+ CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
+-CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
+-CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
+-CONFIG_DRM_PANEL_RONBO_RB070D30=m
+-CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
+-CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
+ CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
+ CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
+-CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
+-CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
+ CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
+-CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
+-CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
+-CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
+ CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
+-CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
+-CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
+-CONFIG_DRM_PANEL_SITRONIX_ST7701=m
+-CONFIG_DRM_PANEL_SONY_ACX565AKM=m
+-CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
+-CONFIG_DRM_PANEL_TDO_TL070WSH30=m
+-CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
+ CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
+-CONFIG_DRM_PANEL_TPO_TPG110=m
+ CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
+-CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
+-CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
+ CONFIG_DRM_CHIPONE_ICN6211=m
+ CONFIG_DRM_CROS_EC_ANX7688=m
+ CONFIG_DRM_DISPLAY_CONNECTOR=m
+@@ -790,22 +757,12 @@ CONFIG_DRM_CDNS_DSI=m
+ CONFIG_DRM_DW_HDMI_CEC=m
+ CONFIG_DRM_PANFROST=y
+ CONFIG_FB=y
+-CONFIG_FB_ARMCLCD=y
+ CONFIG_FB_UVESA=m
+ CONFIG_FIRMWARE_EDID=y
+ CONFIG_LCD_CLASS_DEVICE=m
+ CONFIG_LCD_OTM3225A=m
+-CONFIG_BACKLIGHT_LM3533=m
+-CONFIG_BACKLIGHT_PWM=m
+-CONFIG_BACKLIGHT_QCOM_WLED=m
+-CONFIG_BACKLIGHT_RT4831=m
+-CONFIG_BACKLIGHT_ADP5520=m
+-CONFIG_BACKLIGHT_AAT2870=m
+-CONFIG_BACKLIGHT_LP855X=y
+-CONFIG_BACKLIGHT_AS3711=m
+-CONFIG_BACKLIGHT_GPIO=m
+-CONFIG_BACKLIGHT_RAVE_SP=m
+-CONFIG_BACKLIGHT_LED=m
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
+ CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+ CONFIG_LOGO=y
+ CONFIG_HID_BATTERY_STRENGTH=y
+@@ -896,7 +853,6 @@ CONFIG_MMC_DW_K3=y
+ CONFIG_MMC_DW_ROCKCHIP=y
+ CONFIG_MMC_HSQ=m
+ CONFIG_MMC_SDHCI_XENON=y
+-CONFIG_MMC_SDHCI_AM654=m
+ CONFIG_NEW_LEDS=y
+ CONFIG_LEDS_CLASS=y
+ CONFIG_LEDS_GPIO=y
+@@ -973,7 +929,6 @@ CONFIG_ROCKCHIP_MBOX=y
+ CONFIG_ROCKCHIP_IOMMU=y
+ CONFIG_ARM_SMMU=y
+ CONFIG_ARM_SMMU_V3=y
+-CONFIG_SOC_BRCMSTB=y
+ CONFIG_LITEX_SOC_CONTROLLER=m
+ CONFIG_ROCKCHIP_IODOMAIN=y
+ CONFIG_ROCKCHIP_PM_DOMAINS=y
+@@ -1054,9 +1009,6 @@ CONFIG_QUOTA_NETLINK_INTERFACE=y
+ CONFIG_FUSE_FS=y
+ CONFIG_OVERLAY_FS=y
+ CONFIG_OVERLAY_FS_XINO_AUTO=y
+-CONFIG_FSCACHE=m
+-CONFIG_FSCACHE_STATS=y
+-CONFIG_CACHEFILES=m
+ CONFIG_ISO9660_FS=m
+ CONFIG_JOLIET=y
+ CONFIG_ZISOFS=y
+@@ -1135,10 +1087,8 @@ CONFIG_CRYPTO_TEA=y
+ CONFIG_CRYPTO_TWOFISH=y
+ CONFIG_CRYPTO_ADIANTUM=m
+ CONFIG_CRYPTO_ARC4=m
+-CONFIG_CRYPTO_CFB=m
+ CONFIG_CRYPTO_KEYWRAP=m
+ CONFIG_CRYPTO_LRW=m
+-CONFIG_CRYPTO_OFB=m
+ CONFIG_CRYPTO_PCBC=m
+ CONFIG_CRYPTO_AEGIS128=m
+ CONFIG_CRYPTO_CHACHA20POLY1305=y
diff --git a/7.0-rc1-compile-x86.patch b/7.0-rc1-compile-x86.patch
new file mode 100644
index 0000000..62429fc
--- /dev/null
+++ b/7.0-rc1-compile-x86.patch
@@ -0,0 +1,14 @@
+diff -up linux-7.0-rc1/drivers/gpu/drm/vboxvideo/vbox_fb.c.omv~ linux-7.0-rc1/drivers/gpu/drm/vboxvideo/vbox_fb.c
+--- linux-7.0-rc1/drivers/gpu/drm/vboxvideo/vbox_fb.c.omv~	2026-02-24 23:34:04.935691652 +0100
++++ linux-7.0-rc1/drivers/gpu/drm/vboxvideo/vbox_fb.c	2026-02-24 23:34:11.869764207 +0100
+@@ -211,8 +211,8 @@ static struct fb_ops vboxfb_ops = {
+ 	.fb_pan_display = drm_fb_helper_pan_display,
+ 	.fb_blank = drm_fb_helper_blank,
+ 	.fb_setcmap = drm_fb_helper_setcmap,
+-	.fb_debug_enter = drm_fb_helper_debug_enter,
+-	.fb_debug_leave = drm_fb_helper_debug_leave,
++//	.fb_debug_enter = drm_fb_helper_debug_enter,
++//	.fb_debug_leave = drm_fb_helper_debug_leave,
+ };
+ 
+ static int vboxfb_create_object(struct vbox_fbdev *fbdev,
diff --git a/7.0-rc1-compile.patch b/7.0-rc1-compile.patch
new file mode 100644
index 0000000..fc0bcb6
--- /dev/null
+++ b/7.0-rc1-compile.patch
@@ -0,0 +1,12 @@
+diff -up linux-7.0-rc1/kernel/signal.c.omv~ linux-7.0-rc1/kernel/signal.c
+--- linux-7.0-rc1/kernel/signal.c.omv~	2026-02-24 19:31:01.754478945 +0100
++++ linux-7.0-rc1/kernel/signal.c	2026-02-24 19:31:18.136613520 +0100
+@@ -1386,7 +1386,7 @@ struct sighand_struct *lock_task_sighand
+ 
+ 	return sighand;
+ }
+-EXPORT_SYMBOL_GPL(__lock_task_sighand);
++EXPORT_SYMBOL_GPL(lock_task_sighand);
+ 
+ #ifdef CONFIG_LOCKDEP
+ void lockdep_assert_task_sighand_held(struct task_struct *task)
diff --git a/725cb07d90c7949a971378635e7755ff9a54d25d.patch b/725cb07d90c7949a971378635e7755ff9a54d25d.patch
new file mode 100644
index 0000000..3c3526f
--- /dev/null
+++ b/725cb07d90c7949a971378635e7755ff9a54d25d.patch
@@ -0,0 +1,25 @@
+From 725cb07d90c7949a971378635e7755ff9a54d25d Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Wed, 20 Dec 2023 15:59:23 +0800
+Subject: [PATCH] clk: rockchip: rk3036: Add 1000 MHZ cpu clk rate
+
+Set armclk to 1000 MHZ, so mac_clk_ref can get 50 MHZ
+from it to work well.
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ drivers/clk/rockchip/clk-rk3036.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
+index d341ce0708aac3..d789a09b35d080 100644
+--- a/drivers/clk/rockchip/clk-rk3036.c
++++ b/drivers/clk/rockchip/clk-rk3036.c
+@@ -96,6 +96,7 @@ static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
+ 	}
+ 
+ static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = {
++	RK3036_CPUCLK_RATE(1000000000, 4),
+ 	RK3036_CPUCLK_RATE(816000000, 4),
+ 	RK3036_CPUCLK_RATE(600000000, 4),
+ 	RK3036_CPUCLK_RATE(312000000, 4),
diff --git a/839301464ba91c64483923c9a2a344b1c28e56ed.patch b/839301464ba91c64483923c9a2a344b1c28e56ed.patch
new file mode 100644
index 0000000..e533d05
--- /dev/null
+++ b/839301464ba91c64483923c9a2a344b1c28e56ed.patch
@@ -0,0 +1,229 @@
+From 839301464ba91c64483923c9a2a344b1c28e56ed Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Wed, 20 Dec 2023 18:22:32 +0800
+Subject: [PATCH] Revert "ARM: dts: rockchip: restyle emac nodes"
+
+When try to run rk3036 kylin board with mainline,
+I found the ethernet is broken:
+
+[    2.324583] loop: module loaded
+[    2.328435] SPI driver spidev has no spi_device_id for rockchip,spidev
+[    2.338688] tun: Universal TUN/TAP device driver, 1.6
+[    2.345397] rockchip_emac 10200000.ethernet: no regulator found
+[    2.351892] rockchip_emac 10200000.ethernet: ARC EMAC detected with id: 0x7fd02
+[    2.359331] rockchip_emac 10200000.ethernet: IRQ is 43
+[    2.364719] rockchip_emac 10200000.ethernet: MAC address is now e6:58:d6:ec:d9:7c
+[    2.396993] mdio_bus Synopsys MII Bus: mdio has invalid PHY address
+[    2.403306] mdio_bus Synopsys MII Bus: scan phy mdio at address 0
+[    2.508656] rockchip_emac 10200000.ethernet: of_phy_connect() failed
+[    2.516334] rockchip_emac 10200000.ethernet: failed to probe arc emac (-19)
+
+This reverts commit 1dabb74971b3 ("ARM: dts: rockchip: restyle emac nodes")
+make emac on rk3036 kylin board probe right again:
+[    1.920385] CAN device driver interface
+[    1.925499] rockchip_emac 10200000.ethernet: no regulator found
+[    1.932535] rockchip_emac 10200000.ethernet: ARC EMAC detected with id: 0x7fd02
+[    1.940735] rockchip_emac 10200000.ethernet: IRQ is 42
+[    1.946743] rockchip_emac 10200000.ethernet: MAC address is now 96:7d:4f:0a:69:b3
+[    2.581340] rockchip_emac 10200000.ethernet: connected to Generic PHY phy with id 0xffffc816
+[    2.592560] e1000e: Intel(R) PRO/1000 Network Driver
+[    2.598136] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
+
+Fixes: 1dabb74971b3 ("ARM: dts: rockchip: restyle emac nodes")
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm/boot/dts/rockchip/rk3036-evb.dts     | 16 ++++++----------
+ arch/arm/boot/dts/rockchip/rk3036-kylin.dts   | 16 ++++++----------
+ arch/arm/boot/dts/rockchip/rk3036.dtsi        |  2 ++
+ .../boot/dts/rockchip/rk3066a-marsboard.dts   | 17 +++++++----------
+ .../boot/dts/rockchip/rk3066a-rayeager.dts    | 15 +++++----------
+ .../boot/dts/rockchip/rk3188-radxarock.dts    | 19 ++++++++-----------
+ arch/arm/boot/dts/rockchip/rk3xxx.dtsi        |  3 +++
+ 7 files changed, 37 insertions(+), 51 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3036-evb.dts b/arch/arm/boot/dts/rockchip/rk3036-evb.dts
+index becdc0b664bfa4..94216f870b57cc 100644
+--- a/arch/arm/boot/dts/rockchip/rk3036-evb.dts
++++ b/arch/arm/boot/dts/rockchip/rk3036-evb.dts
+@@ -15,20 +15,16 @@
+ };
+ 
+ &emac {
+-	phy = <&phy0>;
+-	phy-reset-duration = <10>; /* millisecond */
+-	phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
+-	status = "okay";
++	phy = <&phy0>;
++	phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
++	phy-reset-duration = <10>; /* millisecond */
+ 
+-	mdio {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
++	status = "okay";
+ 
+-		phy0: ethernet-phy@0 {
+-			reg = <0>;
+-		};
++	phy0: ethernet-phy@0 {
++		reg = <0>;
+ 	};
+ };
+ 
+diff --git a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts
+index 4f928c7898e90a..b66b9a981d71ae 100644
+--- a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts
++++ b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts
+@@ -95,20 +95,16 @@
+ };
+ 
+ &emac {
+-	phy = <&phy0>;
+-	phy-reset-duration = <10>; /* millisecond */
+-	phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
+-	status = "okay";
++	phy = <&phy0>;
++	phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
++	phy-reset-duration = <10>; /* millisecond */
+ 
+-	mdio {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
++	status = "okay";
+ 
+-		phy0: ethernet-phy@0 {
+-			reg = <0>;
+-		};
++	phy0: ethernet-phy@0 {
++		reg = <0>;
+ 	};
+ };
+ 
+diff --git a/arch/arm/boot/dts/rockchip/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi
+index 63b9912be06a7c..89531138f30f82 100644
+--- a/arch/arm/boot/dts/rockchip/rk3036.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3036.dtsi
+@@ -231,6 +231,8 @@
+ 		compatible = "rockchip,rk3036-emac";
+ 		reg = <0x10200000 0x4000>;
+ 		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++		#address-cells = <1>;
++		#size-cells = <0>;
+ 		rockchip,grf = <&grf>;
+ 		clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
+ 		clock-names = "hclk", "macref", "macclk";
+diff --git a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts
+index ada7dbfc06a56b..36ba1a45cc6343 100644
+--- a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts
++++ b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts
+@@ -150,21 +150,18 @@
+ #include "../tps65910.dtsi"
+ 
+ &emac {
++	status = "okay";
++
+ 	phy = <&phy0>;
+ 	phy-supply = <&vcc_rmii>;
++
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+-	status = "okay";
+-
+-	mdio {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+ 
+-		phy0: ethernet-phy@0 {
+-			reg = <0>;
+-			interrupt-parent = <&gpio1>;
+-			interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+-		};
++	phy0: ethernet-phy@0 {
++		reg = <0>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+ 	};
+ };
+ 
+diff --git a/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts b/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts
+index b0b029f146436f..954af67e53b63d 100644
+--- a/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts
++++ b/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts
+@@ -142,20 +142,15 @@
+ };
+ 
+ &emac {
+-	phy = <&phy0>;
+-	phy-supply = <&vcc_rmii>;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
++	phy = <&phy0>;
++	phy-supply = <&vcc_rmii>;
+ 	status = "okay";
+ 
+-	mdio {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-
+-		phy0: ethernet-phy@0 {
+-			reg = <0>;
+-			reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
+-		};
++	phy0: ethernet-phy@0 {
++		reg = <0>;
++		reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
+ 	};
+ };
+ 
+diff --git a/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts b/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts
+index 1f31c0a6774f78..8af552e33b8109 100644
+--- a/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts
++++ b/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts
+@@ -126,21 +126,18 @@
+ };
+ 
+ &emac {
+-	phy = <&phy0>;
+-	phy-supply = <&vcc_rmii>;
++	status = "okay";
++
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+-	status = "okay";
+ 
+-	mdio {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
++	phy = <&phy0>;
++	phy-supply = <&vcc_rmii>;
+ 
+-		phy0: ethernet-phy@0 {
+-			reg = <0>;
+-			interrupt-parent = <&gpio3>;
+-			interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+-		};
++	phy0: ethernet-phy@0 {
++		reg = <0>;
++		interrupt-parent = <&gpio3>;
++		interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+ 	};
+ };
+ 
+diff --git a/arch/arm/boot/dts/rockchip/rk3xxx.dtsi b/arch/arm/boot/dts/rockchip/rk3xxx.dtsi
+index e6a78bcf916382..327215a810b1c0 100644
+--- a/arch/arm/boot/dts/rockchip/rk3xxx.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3xxx.dtsi
+@@ -197,6 +197,9 @@
+ 		compatible = "rockchip,rk3066-emac";
+ 		reg = <0x10204000 0x3c>;
+ 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
+ 		clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
+ 		clock-names = "hclk", "macref";
+ 		max-speed = <100>;
diff --git a/899558f6782528d5324322ae6e4c270e150c3d6f.patch b/899558f6782528d5324322ae6e4c270e150c3d6f.patch
new file mode 100644
index 0000000..ed85734
--- /dev/null
+++ b/899558f6782528d5324322ae6e4c270e150c3d6f.patch
@@ -0,0 +1,39 @@
+From 899558f6782528d5324322ae6e4c270e150c3d6f Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Fri, 20 Sep 2024 16:20:23 +0800
+Subject: [PATCH] drm/rockchip: Set dma mask to 64 bit
+
+The vop mmu support translate physical address upper 4 GB to iova
+below 4 GB. So set dma mask to 64 bit to indicate we support address
+> 4GB.
+
+This can avoid warnging message like this on some boards with DDR
+> 4 GB:
+
+rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 130 (slots)
+rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 0 (slots)
+rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 130 (slots)
+rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 130 (slots)
+rockchip-drm display-subsystem: swiotlb buffer is full (sz: 266240 bytes), total 32768 (slots), used 0 (slots)
+
+Tested-by: Derek Foreman <derek.foreman@collabora.com>
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+index 32d8394c4c4996..3e9f590c734e92 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+@@ -474,7 +474,9 @@ static int rockchip_drm_platform_probe(struct platform_device *pdev)
+ 		return ret;
+ 	}
+ 
+-	return 0;
++	ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
++
++	return ret;
+ }
+ 
+ static void rockchip_drm_platform_remove(struct platform_device *pdev)
diff --git a/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch b/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch
index 700665e..4c09c6c 100644
--- a/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch
+++ b/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch
@@ -1,43 +1,25 @@
-From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@immortalwrt.org>
-Date: Mon, 18 Oct 2021 12:47:30 +0800
-Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz
-
-It's stable enough to overclock cpu frequency to 2.2/1.8 GHz,
-and for better performance.
-
-Co-development-by: gzelvis <gzelvis@gmail.com>
-Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
----
- arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
-diff -Naur a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
---- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi	2022-10-02 21:09:07.000000000 +0000
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi	2022-10-29 14:28:08.099944121 +0000
-@@ -33,6 +33,14 @@
- 			opp-hz = /bits/ 64 <1416000000>;
- 			opp-microvolt = <1125000 1125000 1250000>;
+diff -up linux-6.13-rc1/arch/arm64/boot/dts/rockchip/rk3399-op1.dtsi.49~ linux-6.13-rc1/arch/arm64/boot/dts/rockchip/rk3399-op1.dtsi
+--- linux-6.13-rc1/arch/arm64/boot/dts/rockchip/rk3399-op1.dtsi.49~	2024-12-02 01:00:45.347623914 +0100
++++ linux-6.13-rc1/arch/arm64/boot/dts/rockchip/rk3399-op1.dtsi	2024-12-02 01:02:40.288987948 +0100
+@@ -39,6 +39,14 @@
+ 			opp-hz = /bits/ 64 <1512000000>;
+ 			opp-microvolt = <1150000 1150000 1150000>;
  		};
-+		opp06 {
++		opp07 {
 +			opp-hz = /bits/ 64 <1608000000>;
 +			opp-microvolt = <1225000>;
 +		};
-+		opp07 {
++		opp08 {
 +			opp-hz = /bits/ 64 <1800000000>;
 +			opp-microvolt = <1275000>;
 +		};
  	};
  
  	cluster1_opp: opp-table-1 {
-@@ -72,6 +80,14 @@
- 			opp-hz = /bits/ 64 <1800000000>;
- 			opp-microvolt = <1200000 1200000 1250000>;
+@@ -82,6 +90,10 @@
+ 			opp-hz = /bits/ 64 <2016000000>;
+ 			opp-microvolt = <1250000 1250000 1250000>;
  		};
-+		opp08 {
-+			opp-hz = /bits/ 64 <2016000000>;
-+			opp-microvolt = <1250000>;
-+		};
 +		opp09 {
 +			opp-hz = /bits/ 64 <2208000000>;
 +			opp-microvolt = <1325000>;
diff --git a/a7a7cf522d7636dc1280adb1b1de7fe45f9b3305.patch b/a7a7cf522d7636dc1280adb1b1de7fe45f9b3305.patch
new file mode 100644
index 0000000..cf912d1
--- /dev/null
+++ b/a7a7cf522d7636dc1280adb1b1de7fe45f9b3305.patch
@@ -0,0 +1,61 @@
+From a7a7cf522d7636dc1280adb1b1de7fe45f9b3305 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 24 Oct 2023 16:13:50 +0200
+Subject: [PATCH] clk: divider: Fix divisor masking on 64 bit platforms
+
+The clock framework handles clock rates as "unsigned long", so u32 on
+32-bit architectures and u64 on 64-bit architectures.
+
+The current code casts the dividend to u64 on 32-bit to avoid a
+potential overflow. For example DIV_ROUND_UP(3000000000, 1500000000)
+= (3.0G + 1.5G - 1) / 1.5G = = OVERFLOW / 1.5G, which has been
+introduced in commit 9556f9dad8f5 ("clk: divider: handle integer overflow
+when dividing large clock rates").
+
+On 64 bit platforms this masks the divisor, so that only the lower
+32 bit are used. Thus requesting a frequency >= 4.3GHz results
+in incorrect values. For example requesting 4300000000 (4.3 GHz) will
+effectively request ca. 5 MHz. Requesting clk_round_rate(clk, ULONG_MAX)
+is a bit of a special case, since that still returns correct values as
+long as the parent clock is below 8.5 GHz.
+
+Fix this by switching to DIV_ROUND_UP_NO_OVERFLOW, which cannot
+overflow. This avoids any requirements on the arguments (except
+that divisor should not be 0 obviously).
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ drivers/clk/clk-divider.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
+index c1f426b8a5043c..b71c814cfc31ba 100644
+--- a/drivers/clk/clk-divider.c
++++ b/drivers/clk/clk-divider.c
+@@ -226,7 +226,7 @@ static int _div_round_up(const struct clk_div_table *table,
+ 			 unsigned long parent_rate, unsigned long rate,
+ 			 unsigned long flags)
+ {
+-	int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
++	int div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
+ 
+ 	if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ 		div = __roundup_pow_of_two(div);
+@@ -243,7 +243,7 @@ static int _div_round_closest(const struct clk_div_table *table,
+ 	int up, down;
+ 	unsigned long up_rate, down_rate;
+ 
+-	up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
++	up = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
+ 	down = parent_rate / rate;
+ 
+ 	if (flags & CLK_DIVIDER_POWER_OF_TWO) {
+@@ -479,7 +479,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,
+ {
+ 	unsigned int div, value;
+ 
+-	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
++	div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate);
+ 
+ 	if (!_is_valid_div(table, div, flags))
+ 		return -EINVAL;
diff --git a/aarch64-desktop-omv-defconfig b/aarch64-desktop-omv-defconfig
deleted file mode 100644
index 14b3868..0000000
--- a/aarch64-desktop-omv-defconfig
+++ /dev/null
@@ -1,11989 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# Linux/arm64 5.16.1 Kernel Configuration
-#
-CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GCC) 11.2.0 20210728 (OpenMandriva)"
-CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=110200
-CONFIG_CLANG_VERSION=0
-CONFIG_AS_IS_GNU=y
-CONFIG_AS_VERSION=23700
-CONFIG_LD_VERSION=0
-CONFIG_LD_IS_LLD=y
-CONFIG_LLD_VERSION=130000
-CONFIG_CC_CAN_LINK=y
-CONFIG_CC_CAN_LINK_STATIC=y
-CONFIG_CC_HAS_ASM_GOTO=y
-CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
-CONFIG_TOOLS_SUPPORT_RELR=y
-CONFIG_CC_HAS_ASM_INLINE=y
-CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
-CONFIG_IRQ_WORK=y
-CONFIG_BUILDTIME_TABLE_SORT=y
-CONFIG_THREAD_INFO_IN_TASK=y
-
-#
-# General setup
-#
-CONFIG_INIT_ENV_ARG_LIMIT=32
-# CONFIG_COMPILE_TEST is not set
-# CONFIG_WERROR is not set
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_BUILD_SALT="c52579728e1caee1ba4000bbacba09140f0e0af3"
-CONFIG_DEFAULT_INIT=""
-CONFIG_DEFAULT_HOSTNAME="omv"
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_POSIX_MQUEUE_SYSCTL=y
-CONFIG_WATCH_QUEUE=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-# CONFIG_USELIB is not set
-# CONFIG_AUDIT is not set
-# CONFIG_HAVE_ARCH_AUDITSYSCALL is not set
-# CONFIG_AUDITSYSCALL is not set
-
-#
-# IRQ subsystem
-#
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_GENERIC_IRQ_IPI=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_IRQ_MSI_IOMMU=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_SPARSE_IRQ=y
-# end of IRQ subsystem
-
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-
-#
-# Timers subsystem
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ_COMMON=y
-# CONFIG_HZ_PERIODIC is not set
-# CONFIG_NO_HZ_IDLE is not set
-CONFIG_NO_HZ_FULL=y
-CONFIG_CONTEXT_TRACKING=y
-# CONFIG_CONTEXT_TRACKING_FORCE is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
-# end of Timers subsystem
-
-CONFIG_BPF=y
-CONFIG_HAVE_EBPF_JIT=y
-CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
-
-#
-# BPF subsystem
-#
-CONFIG_BPF_SYSCALL=y
-CONFIG_BPF_JIT=y
-# CONFIG_BPF_JIT_ALWAYS_ON is not set
-CONFIG_BPF_JIT_DEFAULT_ON=y
-# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
-# CONFIG_BPF_PRELOAD is not set
-# end of BPF subsystem
-
-CONFIG_PREEMPT_VOLUNTARY_BUILD=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-# CONFIG_PREEMPT is not set
-CONFIG_PREEMPT_DYNAMIC=y
-CONFIG_SCHED_CORE=y
-
-#
-# CPU/Task time and stats accounting
-#
-CONFIG_VIRT_CPU_ACCOUNTING=y
-CONFIG_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_SCHED_AVG_IRQ=y
-CONFIG_SCHED_THERMAL_PRESSURE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_PSI=y
-# CONFIG_PSI_DEFAULT_DISABLED is not set
-# end of CPU/Task time and stats accounting
-
-CONFIG_CPU_ISOLATION=y
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_RCU_EXPERT is not set
-CONFIG_SRCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TASKS_RCU_GENERIC=y
-CONFIG_TASKS_RCU=y
-CONFIG_TASKS_RUDE_RCU=y
-CONFIG_TASKS_TRACE_RCU=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RCU_NEED_SEGCBLIST=y
-CONFIG_RCU_NOCB_CPU=y
-CONFIG_RCU_NOCB_CPU_DEFAULT_ALL=y
-# end of RCU Subsystem
-
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-# CONFIG_IKHEADERS is not set
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
-CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
-CONFIG_GENERIC_SCHED_CLOCK=y
-
-#
-# Scheduler features
-#
-CONFIG_UCLAMP_TASK=y
-CONFIG_UCLAMP_BUCKETS_COUNT=5
-# end of Scheduler features
-
-CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
-CONFIG_CC_HAS_INT128=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_ARCH_SUPPORTS_INT128=y
-CONFIG_NUMA_BALANCING=y
-CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
-CONFIG_CGROUPS=y
-CONFIG_PAGE_COUNTER=y
-CONFIG_MEMCG=y
-CONFIG_MEMCG_SWAP=y
-CONFIG_MEMCG_KMEM=y
-CONFIG_BLK_CGROUP=y
-CONFIG_CGROUP_WRITEBACK=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_CFS_BANDWIDTH=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_UCLAMP_TASK_GROUP=y
-CONFIG_CGROUP_PIDS=y
-CONFIG_CGROUP_RDMA=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_HUGETLB=y
-CONFIG_CPUSETS=y
-CONFIG_PROC_PID_CPUSET=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_PERF=y
-CONFIG_CGROUP_BPF=y
-CONFIG_CGROUP_MISC=y
-# CONFIG_CGROUP_DEBUG is not set
-CONFIG_SOCK_CGROUP_DATA=y
-CONFIG_NAMESPACES=y
-CONFIG_UTS_NS=y
-CONFIG_TIME_NS=y
-CONFIG_IPC_NS=y
-CONFIG_USER_NS=y
-CONFIG_PID_NS=y
-CONFIG_NET_NS=y
-CONFIG_CHECKPOINT_RESTORE=y
-CONFIG_SCHED_AUTOGROUP=y
-# CONFIG_SYSFS_DEPRECATED is not set
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_XZ=y
-CONFIG_RD_LZO=y
-CONFIG_RD_LZ4=y
-CONFIG_RD_ZSTD=y
-CONFIG_BOOT_CONFIG=y
-# CONFIG_CC_OPTIMIZE_BASAL is not set
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_LD_ORPHAN_WARN=y
-CONFIG_SYSCTL=y
-CONFIG_HAVE_UID16=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_EXPERT=y
-CONFIG_UID16=y
-CONFIG_MULTIUSER=y
-CONFIG_SGETMASK_SYSCALL=y
-# CONFIG_SYSFS_SYSCALL is not set
-CONFIG_FHANDLE=y
-CONFIG_POSIX_TIMERS=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_FUTEX_PI=y
-CONFIG_HAVE_FUTEX_CMPXCHG=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_IO_URING=y
-CONFIG_ADVISE_SYSCALLS=y
-CONFIG_MEMBARRIER=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_BASE_RELATIVE=y
-# CONFIG_USERFAULTFD is not set
-CONFIG_LRU_GEN=y
-CONFIG_LRU_GEN_ENABLED=y
-# CONFIG_LRU_GEN_STATS is not set
-CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
-CONFIG_KCMP=y
-CONFIG_RSEQ=y
-# CONFIG_DEBUG_RSEQ is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PC104=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_PERF_EVENTS=y
-# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
-# end of Kernel Performance Events And Counters
-
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_SLAB_MERGE_DEFAULT is not set
-# CONFIG_SLAB_FREELIST_RANDOM is not set
-# CONFIG_SLAB_FREELIST_HARDENED is not set
-# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
-CONFIG_SLUB_CPU_PARTIAL=y
-CONFIG_SYSTEM_DATA_VERIFICATION=y
-CONFIG_PROFILING=y
-# end of General setup
-
-CONFIG_ARM64=y
-CONFIG_64BIT=y
-CONFIG_MMU=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_CONT_PTE_SHIFT=4
-CONFIG_ARM64_CONT_PMD_SHIFT=4
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=33
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_SMP=y
-CONFIG_KERNEL_MODE_NEON=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_PGTABLE_LEVELS=4
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-
-#
-# Platform selection
-#
-CONFIG_ARCH_ACTIONS=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_ALPINE=y
-CONFIG_ARCH_APPLE=y
-CONFIG_ARCH_BCM=y
-CONFIG_ARCH_NXP=y
-CONFIG_ARCH_BCM2835=y
-CONFIG_ARCH_BCM4908=y
-CONFIG_ARCH_BCM_IPROC=y
-CONFIG_ARCH_BERLIN=y
-CONFIG_ARCH_BITMAIN=y
-CONFIG_ARCH_BRCMSTB=y
-CONFIG_ARCH_EXYNOS=y
-CONFIG_ARCH_SPARX5=y
-CONFIG_ARCH_K3=y
-CONFIG_ARCH_LAYERSCAPE=y
-CONFIG_ARCH_LG1K=y
-CONFIG_ARCH_HISI=y
-CONFIG_ARCH_KEEMBAY=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MESON=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_ARCH_MXC=y
-CONFIG_ARCH_NPCM=y
-CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_REALTEK=y
-CONFIG_ARCH_RENESAS=y
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_ARCH_S32=y
-CONFIG_ARCH_SEATTLE=y
-CONFIG_ARCH_INTEL_SOCFPGA=y
-CONFIG_ARCH_SYNQUACER=y
-CONFIG_ARCH_TEGRA=y
-CONFIG_ARCH_TESLA_FSD=y
-CONFIG_ARCH_SPRD=y
-CONFIG_ARCH_THUNDER=y
-CONFIG_ARCH_THUNDER2=y
-CONFIG_ARCH_UNIPHIER=y
-# CONFIG_ARCH_VEXPRESS is not set
-CONFIG_ARCH_VISCONTI=y
-CONFIG_ARCH_XGENE=y
-CONFIG_ARCH_ZYNQMP=y
-# end of Platform selection
-
-#
-# Kernel Features
-#
-
-#
-# ARM errata workarounds via the alternatives framework
-#
-CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
-CONFIG_ARM64_ERRATUM_826319=y
-CONFIG_ARM64_ERRATUM_827319=y
-CONFIG_ARM64_ERRATUM_824069=y
-CONFIG_ARM64_ERRATUM_819472=y
-CONFIG_ARM64_ERRATUM_832075=y
-CONFIG_ARM64_ERRATUM_834220=y
-CONFIG_ARM64_ERRATUM_1742098=y
-CONFIG_ARM64_ERRATUM_2441009=y
-CONFIG_ARM64_ERRATUM_845719=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_ERRATUM_1024718=y
-CONFIG_ARM64_ERRATUM_1418040=y
-CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
-CONFIG_ARM64_ERRATUM_1165522=y
-CONFIG_ARM64_ERRATUM_1319367=y
-CONFIG_ARM64_ERRATUM_1530923=y
-CONFIG_ARM64_ERRATUM_2441007=y
-CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
-CONFIG_ARM64_ERRATUM_1286807=y
-CONFIG_ARM64_ERRATUM_1463225=y
-CONFIG_ARM64_ERRATUM_1542419=y
-CONFIG_ARM64_ERRATUM_1508412=y
-CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
-CONFIG_ARM64_ERRATUM_2054223=y
-CONFIG_ARM64_ERRATUM_2067961=y
-CONFIG_ARM64_ERRATUM_2457168=y
-CONFIG_ARM64_ERRATUM_2051678=y
-CONFIG_ARM64_ERRATUM_2077057=y
-CONFIG_ARM64_ERRATUM_2658417=y
-CONFIG_ARM64_ERRATUM_2064142=y
-CONFIG_ARM64_ERRATUM_2038923=y
-CONFIG_ARM64_ERRATUM_1902691=y
-CONFIG_CAVIUM_ERRATUM_22375=y
-CONFIG_CAVIUM_ERRATUM_23144=y
-CONFIG_CAVIUM_ERRATUM_23154=y
-CONFIG_CAVIUM_ERRATUM_27456=y
-CONFIG_CAVIUM_ERRATUM_30115=y
-CONFIG_CAVIUM_TX2_ERRATUM_219=y
-CONFIG_FUJITSU_ERRATUM_010001=y
-CONFIG_HISILICON_ERRATUM_161600802=y
-CONFIG_QCOM_FALKOR_ERRATUM_1003=y
-CONFIG_QCOM_FALKOR_ERRATUM_1009=y
-CONFIG_QCOM_QDF2400_ERRATUM_0065=y
-CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
-CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
-CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
-# end of ARM errata workarounds via the alternatives framework
-
-CONFIG_ARM64_4K_PAGES=y
-# CONFIG_ARM64_16K_PAGES is not set
-# CONFIG_ARM64_64K_PAGES is not set
-# CONFIG_ARM64_VA_BITS_39 is not set
-CONFIG_ARM64_VA_BITS_48=y
-CONFIG_ARM64_VA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PA_BITS=48
-# CONFIG_CPU_BIG_ENDIAN is not set
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_CLUSTER=y
-CONFIG_SCHED_SMT=y
-CONFIG_NR_CPUS=256
-CONFIG_HOTPLUG_CPU=y
-CONFIG_NUMA=y
-CONFIG_NODES_SHIFT=2
-CONFIG_USE_PERCPU_NUMA_NODE_ID=y
-CONFIG_HAVE_SETUP_PER_CPU_AREA=y
-CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
-CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_250 is not set
-CONFIG_HZ_300=y
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=300
-CONFIG_ARCH_FORCE_MAX_ORDER=12
-CONFIG_SCHED_HRTICK=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_HW_PERF_EVENTS=y
-CONFIG_ARCH_HAS_FILTER_PGPROT=y
-CONFIG_PARAVIRT=y
-# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
-CONFIG_KEXEC=y
-CONFIG_KEXEC_FILE=y
-# CONFIG_KEXEC_SIG is not set
-# CONFIG_CRASH_DUMP is not set
-CONFIG_TRANS_TABLE=y
-# CONFIG_XEN is not set
-CONFIG_FORCE_MAX_ZONEORDER=11
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-# CONFIG_ARM64_SW_TTBR0_PAN is not set
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_COMPAT=y
-CONFIG_KUSER_HELPERS=y
-CONFIG_ARMV8_DEPRECATED=y
-CONFIG_SWP_EMULATION=y
-CONFIG_CP15_BARRIER_EMULATION=y
-CONFIG_SETEND_EMULATION=y
-
-#
-# ARMv8.1 architectural features
-#
-CONFIG_ARM64_HW_AFDBM=y
-CONFIG_ARM64_PAN=y
-CONFIG_AS_HAS_LDAPR=y
-CONFIG_AS_HAS_LSE_ATOMICS=y
-CONFIG_ARM64_LSE_ATOMICS=y
-CONFIG_ARM64_USE_LSE_ATOMICS=y
-# end of ARMv8.1 architectural features
-
-#
-# ARMv8.2 architectural features
-#
-CONFIG_ARM64_PMEM=y
-CONFIG_ARM64_RAS_EXTN=y
-CONFIG_ARM64_CNP=y
-# end of ARMv8.2 architectural features
-
-#
-# ARMv8.3 architectural features
-#
-CONFIG_ARM64_PTR_AUTH=y
-CONFIG_ARM64_PTR_AUTH_KERNEL=y
-CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
-CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
-CONFIG_AS_HAS_PAC=y
-CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
-# end of ARMv8.3 architectural features
-
-#
-# ARMv8.4 architectural features
-#
-CONFIG_ARM64_AMU_EXTN=y
-CONFIG_AS_HAS_ARMV8_4=y
-# CONFIG_ARM64_TLB_RANGE is not set
-# end of ARMv8.4 architectural features
-
-#
-# ARMv8.5 architectural features
-#
-CONFIG_AS_HAS_ARMV8_5=y
-CONFIG_ARM64_BTI=y
-CONFIG_ARM64_BTI_KERNEL=y
-CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
-CONFIG_ARM64_E0PD=y
-CONFIG_ARCH_RANDOM=y
-CONFIG_ARM64_AS_HAS_MTE=y
-CONFIG_ARM64_MTE=y
-# end of ARMv8.5 architectural features
-
-#
-# ARMv8.7 architectural features
-#
-CONFIG_ARM64_EPAN=y
-# end of ARMv8.7 architectural features
-
-CONFIG_ARM64_SVE=y
-CONFIG_ARM64_SME=y
-CONFIG_ARM64_MODULE_PLTS=y
-# CONFIG_ARM64_PSEUDO_NMI is not set
-CONFIG_RELOCATABLE=y
-CONFIG_RANDOMIZE_BASE=y
-CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_STACKPROTECTOR_PER_TASK=y
-# CONFIG_COMPAT_VDSO is not set
-# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
-# end of Kernel Features
-
-#
-# Boot options
-#
-CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
-CONFIG_CMDLINE=""
-CONFIG_EFI_STUB=y
-CONFIG_EFI=y
-CONFIG_DMI=y
-# end of Boot options
-
-CONFIG_SYSVIPC_COMPAT=y
-
-#
-# Power management options
-#
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_SUSPEND_SKIP_SYNC is not set
-CONFIG_HIBERNATE_CALLBACKS=y
-CONFIG_HIBERNATION=y
-CONFIG_HIBERNATION_SNAPSHOT_DEV=y
-CONFIG_PM_STD_PARTITION=""
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-# CONFIG_PM_AUTOSLEEP is not set
-# CONFIG_PM_WAKELOCKS is not set
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_CPU_PM=y
-# CONFIG_ENERGY_MODEL is not set
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_HIBERNATION_HEADER=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# end of Power management options
-
-#
-# CPU Power Management
-#
-
-#
-# CPU Idle
-#
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_GOV_TEO=y
-CONFIG_DT_IDLE_STATES=y
-
-#
-# ARM CPU Idle Drivers
-#
-CONFIG_ARM_CPUIDLE=y
-CONFIG_ARM_PSCI_CPUIDLE=y
-CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
-# end of ARM CPU Idle Drivers
-# end of CPU Idle
-
-#
-# CPU Frequency scaling
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=m
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-
-#
-# CPU frequency scaling drivers
-#
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_ACPI_CPPC_CPUFREQ=m
-CONFIG_ACPI_CPPC_CPUFREQ_FIE=y
-CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m
-CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
-# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set
-CONFIG_ARM_SCPI_CPUFREQ=y
-CONFIG_ARM_BRCMSTB_AVS_CPUFREQ=y
-CONFIG_ARM_IMX_CPUFREQ_DT=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=m
-CONFIG_ARM_MEDIATEK_CPUFREQ_HW=m
-CONFIG_ARM_QCOM_CPUFREQ_NVMEM=m
-CONFIG_ARM_QCOM_CPUFREQ_HW=m
-CONFIG_ARM_RASPBERRYPI_CPUFREQ=m
-CONFIG_ARM_TEGRA20_CPUFREQ=y
-CONFIG_ARM_TEGRA124_CPUFREQ=y
-CONFIG_ARM_TEGRA186_CPUFREQ=y
-CONFIG_ARM_TEGRA194_CPUFREQ=y
-CONFIG_QORIQ_CPUFREQ=m
-# end of CPU Frequency scaling
-# end of CPU Power Management
-
-CONFIG_ARCH_SUPPORTS_ACPI=y
-CONFIG_ACPI=y
-CONFIG_ACPI_GENERIC_GSI=y
-CONFIG_ACPI_CCA_REQUIRED=y
-# CONFIG_ACPI_DEBUGGER is not set
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_EC_DEBUGFS=m
-CONFIG_ACPI_AC=y
-CONFIG_ACPI_BATTERY=y
-CONFIG_ACPI_BUTTON=y
-CONFIG_ACPI_VIDEO=m
-CONFIG_ACPI_FAN=y
-# CONFIG_ACPI_TAD is not set
-CONFIG_ACPI_DOCK=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
-CONFIG_ACPI_MCFG=y
-CONFIG_ACPI_CPPC_LIB=y
-CONFIG_ACPI_PROCESSOR=y
-CONFIG_ACPI_IPMI=m
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_THERMAL=y
-CONFIG_ACPI_PLATFORM_PROFILE=m
-CONFIG_ACPI_CUSTOM_DSDT_FILE=""
-CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
-CONFIG_ACPI_TABLE_UPGRADE=y
-# CONFIG_ACPI_DEBUG is not set
-CONFIG_ACPI_PCI_SLOT=y
-CONFIG_ACPI_CONTAINER=y
-# CONFIG_ACPI_HOTPLUG_MEMORY is not set
-CONFIG_ACPI_HED=y
-CONFIG_ACPI_BGRT=y
-CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
-CONFIG_ACPI_NFIT=m
-# CONFIG_NFIT_SECURITY_DEBUG is not set
-CONFIG_ACPI_NUMA=y
-CONFIG_ACPI_HMAT=y
-CONFIG_HAVE_ACPI_APEI=y
-CONFIG_ACPI_APEI=y
-CONFIG_ACPI_APEI_GHES=y
-CONFIG_ACPI_APEI_PCIEAER=y
-CONFIG_ACPI_APEI_SEA=y
-CONFIG_ACPI_APEI_MEMORY_FAILURE=y
-# CONFIG_ACPI_APEI_ERST_DEBUG is not set
-CONFIG_ACPI_CONFIGFS=m
-CONFIG_ACPI_PFRUT=m
-CONFIG_ACPI_AGDI=y
-CONFIG_ACPI_PCC=y
-CONFIG_ACPI_PRMT=y
-CONFIG_ACPI_IORT=y
-CONFIG_ACPI_GTDT=y
-CONFIG_ACPI_PPTT=y
-# CONFIG_PMIC_OPREGION is not set
-CONFIG_ACPI_VIOT=y
-CONFIG_IRQ_BYPASS_MANAGER=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_KVM_IRQCHIP=y
-CONFIG_HAVE_KVM_IRQFD=y
-CONFIG_HAVE_KVM_IRQ_ROUTING=y
-CONFIG_HAVE_KVM_EVENTFD=y
-CONFIG_KVM_MMIO=y
-CONFIG_HAVE_KVM_MSI=y
-CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
-CONFIG_KVM_VFIO=y
-CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
-CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
-CONFIG_HAVE_KVM_IRQ_BYPASS=y
-CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
-CONFIG_KVM_XFER_TO_GUEST_WORK=y
-CONFIG_VIRTUALIZATION=y
-CONFIG_KVM=y
-# CONFIG_NVHE_EL2_DEBUG is not set
-CONFIG_ARM64_CRYPTO=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA512_ARM64=y
-CONFIG_CRYPTO_SHA1_ARM64_CE=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA512_ARM64_CE=y
-CONFIG_CRYPTO_SHA3_ARM64=m
-CONFIG_CRYPTO_SM3_NEON=m
-CONFIG_CRYPTO_SM3_ARM64_CE=m
-CONFIG_CRYPTO_SM4_ARM64_CE=m
-CONFIG_CRYPTO_SM4_ARM64_CE_BLK=m
-CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=m
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_POLYVAL_ARM64_CE=m
-CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
-CONFIG_CRYPTO_CHACHA20_NEON=y
-CONFIG_CRYPTO_POLY1305_NEON=y
-CONFIG_CRYPTO_NHPOLY1305_NEON=y
-CONFIG_CRYPTO_AES_ARM64_BS=y
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-
-#
-# General architecture-dependent options
-#
-CONFIG_CRASH_CORE=y
-CONFIG_KEXEC_CORE=y
-CONFIG_KPROBES=y
-CONFIG_JUMP_LABEL=y
-# CONFIG_STATIC_KEYS_SELFTEST is not set
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_KRETPROBES=y
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
-CONFIG_HAVE_NMI=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_KEEPINITRD=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
-CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_HAVE_ASM_MODVERSIONS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
-CONFIG_MMU_GATHER_TABLE_FREE=y
-CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
-CONFIG_HAVE_CMPXCHG_LOCAL=y
-CONFIG_HAVE_CMPXCHG_DOUBLE=y
-CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
-CONFIG_HAVE_ARCH_SECCOMP=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_SECCOMP=y
-CONFIG_SECCOMP_FILTER=y
-# CONFIG_SECCOMP_CACHE_DEBUG is not set
-CONFIG_HAVE_ARCH_STACKLEAK=y
-CONFIG_HAVE_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR_STRONG=y
-CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
-CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
-CONFIG_LTO_NONE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MOVE_PUD=y
-CONFIG_HAVE_MOVE_PMD=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-CONFIG_HAVE_ARCH_HUGE_VMAP=y
-CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_COMPAT_OLD_SIGACTION=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_HAVE_ARCH_VMAP_STACK=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET=y
-CONFIG_VMAP_STACK=y
-CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_STRICT_MODULE_RWX=y
-CONFIG_HAVE_ARCH_COMPILER_H=y
-CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
-CONFIG_ARCH_USE_MEMREMAP_PROT=y
-CONFIG_ARCH_HAS_RELR=y
-CONFIG_RELR=y
-CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
-# CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC is not set
-
-#
-# GCOV-based kernel profiling
-#
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-# end of GCOV-based kernel profiling
-
-CONFIG_HAVE_GCC_PLUGINS=y
-CONFIG_GCC_PLUGINS=y
-# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
-# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
-# end of General architecture-dependent options
-CONFIG_RANDSTRUCT_NONE=y
-# CONFIG_RANDSTRUCT_FULL is not set
-# CONFIG_RANDSTRUCT_PERFORMANCE is not set
-
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULE_SIG_FORMAT=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_ASM_MODVERSIONS=y
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_MODULE_SIG=y
-# CONFIG_MODULE_SIG_FORCE is not set
-# CONFIG_MODULE_SIG_ALL is not set
-CONFIG_MODULE_SIG_SHA1=y
-# CONFIG_MODULE_SIG_SHA224 is not set
-# CONFIG_MODULE_SIG_SHA256 is not set
-# CONFIG_MODULE_SIG_SHA384 is not set
-# CONFIG_MODULE_SIG_SHA512 is not set
-CONFIG_MODULE_SIG_HASH="sha1"
-CONFIG_MODULE_COMPRESS_NONE=y
-# CONFIG_MODULE_COMPRESS_GZIP is not set
-# CONFIG_MODULE_COMPRESS_XZ is not set
-# CONFIG_MODULE_COMPRESS_ZSTD is not set
-# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
-CONFIG_MODPROBE_PATH="/sbin/modprobe"
-# CONFIG_TRIM_UNUSED_KSYMS is not set
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_BLOCK=y
-# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set
-CONFIG_BLK_CGROUP_RWSTAT=y
-CONFIG_BLK_DEV_BSG_COMMON=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=y
-# CONFIG_BLK_DEV_ZONED is not set
-CONFIG_BLK_DEV_THROTTLING=y
-# CONFIG_BLK_DEV_THROTTLING_LOW is not set
-# CONFIG_BLK_WBT is not set
-# CONFIG_BLK_CGROUP_IOLATENCY is not set
-# CONFIG_BLK_CGROUP_FC_APPID is not set
-# CONFIG_BLK_CGROUP_IOCOST is not set
-# CONFIG_BLK_CGROUP_IOPRIO is not set
-# CONFIG_BLK_SED_OPAL is not set
-CONFIG_BLK_INLINE_ENCRYPTION=y
-CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_AIX_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-CONFIG_MAC_PARTITION=y
-CONFIG_MSDOS_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-# CONFIG_UNIXWARE_DISKLABEL is not set
-CONFIG_LDM_PARTITION=y
-# CONFIG_LDM_DEBUG is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_CMDLINE_PARTITION=y
-# end of Partition Types
-
-CONFIG_BLOCK_COMPAT=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_MQ_RDMA=y
-CONFIG_BLK_PM=y
-CONFIG_BLOCK_HOLDER_DEPRECATED=y
-
-#
-# IO Schedulers
-#
-CONFIG_MQ_IOSCHED_DEADLINE=y
-CONFIG_MQ_IOSCHED_KYBER=y
-CONFIG_IOSCHED_BFQ=y
-CONFIG_BFQ_GROUP_IOSCHED=y
-# CONFIG_BFQ_CGROUP_DEBUG is not set
-# end of IO Schedulers
-
-CONFIG_PREEMPT_NOTIFIERS=y
-CONFIG_ASN1=y
-CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
-CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
-CONFIG_ARCH_INLINE_SPIN_LOCK=y
-CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
-CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
-CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
-CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
-CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
-CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
-CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
-CONFIG_ARCH_INLINE_READ_LOCK=y
-CONFIG_ARCH_INLINE_READ_LOCK_BH=y
-CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
-CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
-CONFIG_ARCH_INLINE_READ_UNLOCK=y
-CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
-CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
-CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
-CONFIG_ARCH_INLINE_WRITE_LOCK=y
-CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
-CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
-CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
-CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
-CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
-CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
-CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
-CONFIG_INLINE_SPIN_TRYLOCK=y
-CONFIG_INLINE_SPIN_TRYLOCK_BH=y
-CONFIG_INLINE_SPIN_LOCK=y
-CONFIG_INLINE_SPIN_LOCK_BH=y
-CONFIG_INLINE_SPIN_LOCK_IRQ=y
-CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
-CONFIG_INLINE_SPIN_UNLOCK_BH=y
-CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
-CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
-CONFIG_INLINE_READ_LOCK=y
-CONFIG_INLINE_READ_LOCK_BH=y
-CONFIG_INLINE_READ_LOCK_IRQ=y
-CONFIG_INLINE_READ_LOCK_IRQSAVE=y
-CONFIG_INLINE_READ_UNLOCK=y
-CONFIG_INLINE_READ_UNLOCK_BH=y
-CONFIG_INLINE_READ_UNLOCK_IRQ=y
-CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
-CONFIG_INLINE_WRITE_LOCK=y
-CONFIG_INLINE_WRITE_LOCK_BH=y
-CONFIG_INLINE_WRITE_LOCK_IRQ=y
-CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
-CONFIG_INLINE_WRITE_UNLOCK=y
-CONFIG_INLINE_WRITE_UNLOCK_BH=y
-CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
-CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
-CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
-CONFIG_FREEZER=y
-
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_COMPAT_BINFMT_ELF=y
-CONFIG_ARCH_BINFMT_ELF_STATE=y
-CONFIG_ARCH_HAVE_ELF_PROT=y
-CONFIG_ARCH_USE_GNU_PROPERTY=y
-CONFIG_ELFCORE=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_BINFMT_SCRIPT=y
-CONFIG_BINFMT_MISC=m
-CONFIG_COREDUMP=y
-# end of Executable file formats
-
-#
-# Memory Management options
-#
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_HAVE_FAST_GUP=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_NUMA_KEEP_MEMINFO=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_MEMORY_HOTPLUG=y
-CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-CONFIG_MEMORY_HOTREMOVE=y
-CONFIG_MHP_MEMMAP_ON_MEMORY=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
-CONFIG_MEMORY_BALLOON=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_COMPACTION=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_MIGRATION=y
-CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
-CONFIG_ARCH_ENABLE_THP_MIGRATION=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_MMU_NOTIFIER=y
-CONFIG_KSM=y
-CONFIG_UKSM=y
-# CONFIG_KSM_LEGACY is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
-CONFIG_MEMORY_FAILURE=y
-# CONFIG_HWPOISON_INJECT is not set
-CONFIG_TRANSPARENT_HUGEPAGE=y
-CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
-# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-CONFIG_CLEANCACHE=y
-CONFIG_FRONTSWAP=y
-CONFIG_CMA=y
-# CONFIG_CMA_DEBUG is not set
-CONFIG_CMA_SYSFS=y
-CONFIG_CMA_AREAS=7
-CONFIG_ZSWAP=y
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
-CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
-CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
-# CONFIG_ZSWAP_DEFAULT_ON is not set
-CONFIG_ZPOOL=y
-CONFIG_ZBUD=y
-CONFIG_Z3FOLD=m
-CONFIG_ZSMALLOC=y
-# CONFIG_ZSMALLOC_STAT is not set
-CONFIG_GENERIC_EARLY_IOREMAP=y
-# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
-CONFIG_PAGE_IDLE_FLAG=y
-# CONFIG_IDLE_PAGE_TRACKING is not set
-CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
-CONFIG_ARCH_HAS_PTE_DEVMAP=y
-CONFIG_ARCH_HAS_ZONE_DMA_SET=y
-CONFIG_ZONE_DMA=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZONE_DEVICE=y
-CONFIG_DEV_PAGEMAP_OPS=y
-CONFIG_HMM_MIRROR=y
-# CONFIG_DEVICE_PRIVATE is not set
-CONFIG_VMAP_PFN=y
-CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
-# CONFIG_PERCPU_STATS is not set
-
-#
-# GUP_TEST needs to have DEBUG_FS enabled
-#
-# CONFIG_READ_ONLY_THP_FOR_FS is not set
-CONFIG_ARCH_HAS_PTE_SPECIAL=y
-CONFIG_MAPPING_DIRTY_HELPERS=y
-CONFIG_SECRETMEM=y
-
-#
-# Data Access Monitoring
-#
-CONFIG_DAMON=y
-CONFIG_DAMON_SYSFS=y
-CONFIG_DAMON_VADDR=y
-CONFIG_DAMON_PADDR=y
-CONFIG_DAMON_RECLAIM=y
-# end of Data Access Monitoring
-# end of Memory Management options
-
-CONFIG_NET=y
-CONFIG_COMPAT_NETLINK_MESSAGES=y
-CONFIG_NET_INGRESS=y
-CONFIG_NET_EGRESS=y
-CONFIG_NET_REDIRECT=y
-CONFIG_SKB_EXTENSIONS=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-CONFIG_PACKET_DIAG=m
-CONFIG_UNIX=y
-CONFIG_UNIX_SCM=y
-CONFIG_AF_UNIX_OOB=y
-CONFIG_UNIX_DIAG=m
-CONFIG_TLS=m
-# CONFIG_TLS_DEVICE is not set
-# CONFIG_TLS_TOE is not set
-CONFIG_XFRM=y
-CONFIG_XFRM_OFFLOAD=y
-CONFIG_XFRM_ALGO=m
-CONFIG_XFRM_USER=m
-CONFIG_XFRM_INTERFACE=m
-CONFIG_XFRM_SUB_POLICY=y
-CONFIG_XFRM_MIGRATE=y
-# CONFIG_XFRM_STATISTICS is not set
-CONFIG_XFRM_AH=m
-CONFIG_XFRM_ESP=m
-CONFIG_XFRM_IPCOMP=m
-CONFIG_NET_KEY=m
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_SMC=m
-CONFIG_SMC_DIAG=m
-CONFIG_XDP_SOCKETS=y
-CONFIG_XDP_SOCKETS_DIAG=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-# CONFIG_IP_FIB_TRIE_STATS is not set
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-# CONFIG_IP_ROUTE_VERBOSE is not set
-CONFIG_IP_ROUTE_CLASSID=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE_DEMUX=m
-CONFIG_NET_IP_TUNNEL=m
-CONFIG_NET_IPGRE=m
-CONFIG_NET_IPGRE_BROADCAST=y
-CONFIG_IP_MROUTE_COMMON=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_NET_IPVTI=m
-CONFIG_NET_UDP_TUNNEL=m
-CONFIG_NET_FOU=m
-CONFIG_NET_FOU_IP_TUNNELS=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_ESP_OFFLOAD=m
-# CONFIG_INET_ESPINTCP is not set
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_TABLE_PERTURB_ORDER=16
-CONFIG_INET_XFRM_TUNNEL=m
-CONFIG_INET_TUNNEL=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-CONFIG_INET_UDP_DIAG=m
-CONFIG_INET_RAW_DIAG=m
-# CONFIG_INET_DIAG_DESTROY is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-CONFIG_IPV6=m
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_ESP_OFFLOAD=m
-# CONFIG_INET6_ESPINTCP is not set
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-# CONFIG_IPV6_ILA is not set
-CONFIG_INET6_XFRM_TUNNEL=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_IPV6_VTI=m
-CONFIG_IPV6_SIT=m
-# CONFIG_IPV6_SIT_6RD is not set
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_GRE=m
-CONFIG_IPV6_FOU=m
-CONFIG_IPV6_FOU_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-CONFIG_IPV6_MROUTE=y
-CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IPV6_PIMSM_V2=y
-# CONFIG_IPV6_SEG6_LWTUNNEL is not set
-# CONFIG_IPV6_SEG6_HMAC is not set
-# CONFIG_IPV6_RPL_LWTUNNEL is not set
-CONFIG_IPV6_IOAM6_LWTUNNEL=y
-CONFIG_NETLABEL=y
-# CONFIG_MPTCP is not set
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NET_PTP_CLASSIFY=y
-# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_ADVANCED=y
-CONFIG_BRIDGE_NETFILTER=m
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_INGRESS=y
-CONFIG_NETFILTER_EGRESS=y
-CONFIG_NETFILTER_SKIP_EGRESS=y
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_FAMILY_BRIDGE=y
-CONFIG_NETFILTER_FAMILY_ARP=y
-CONFIG_NETFILTER_NETLINK_HOOK=m
-CONFIG_NETFILTER_NETLINK_ACCT=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NETFILTER_NETLINK_OSF=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_LOG_SYSLOG=m
-CONFIG_NETFILTER_CONNCOUNT=m
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_ZONES=y
-# CONFIG_NF_CONNTRACK_PROCFS is not set
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CONNTRACK_TIMEOUT=y
-CONFIG_NF_CONNTRACK_TIMESTAMP=y
-CONFIG_NF_CONNTRACK_LABELS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_GRE=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_BROADCAST=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_SNMP=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NF_CT_NETLINK_TIMEOUT=m
-CONFIG_NF_CT_NETLINK_HELPER=m
-CONFIG_NETFILTER_NETLINK_GLUE_CT=y
-CONFIG_NF_NAT=m
-CONFIG_NF_NAT_AMANDA=m
-CONFIG_NF_NAT_FTP=m
-CONFIG_NF_NAT_IRC=m
-CONFIG_NF_NAT_SIP=m
-CONFIG_NF_NAT_TFTP=m
-CONFIG_NF_NAT_REDIRECT=y
-CONFIG_NF_NAT_MASQUERADE=y
-CONFIG_NETFILTER_SYNPROXY=m
-CONFIG_NF_TABLES=m
-CONFIG_NF_TABLES_INET=y
-CONFIG_NF_TABLES_NETDEV=y
-CONFIG_NFT_NUMGEN=m
-CONFIG_NFT_CT=m
-CONFIG_NFT_FLOW_OFFLOAD=m
-CONFIG_NFT_COUNTER=m
-CONFIG_NFT_CONNLIMIT=m
-CONFIG_NFT_LOG=m
-CONFIG_NFT_LIMIT=m
-CONFIG_NFT_MASQ=m
-CONFIG_NFT_REDIR=m
-CONFIG_NFT_NAT=m
-CONFIG_NFT_TUNNEL=m
-CONFIG_NFT_OBJREF=m
-CONFIG_NFT_QUEUE=m
-CONFIG_NFT_QUOTA=m
-CONFIG_NFT_REJECT=m
-CONFIG_NFT_REJECT_INET=m
-CONFIG_NFT_COMPAT=m
-CONFIG_NFT_HASH=m
-CONFIG_NFT_FIB=m
-CONFIG_NFT_FIB_INET=m
-CONFIG_NFT_XFRM=m
-CONFIG_NFT_SOCKET=m
-CONFIG_NFT_OSF=m
-CONFIG_NFT_TPROXY=m
-CONFIG_NFT_SYNPROXY=m
-CONFIG_NF_DUP_NETDEV=m
-CONFIG_NFT_DUP_NETDEV=m
-CONFIG_NFT_FWD_NETDEV=m
-CONFIG_NFT_FIB_NETDEV=m
-CONFIG_NFT_REJECT_NETDEV=m
-CONFIG_NF_FLOW_TABLE_INET=m
-CONFIG_NF_FLOW_TABLE=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XTABLES_COMPAT=y
-
-#
-# Xtables combined modules
-#
-CONFIG_NETFILTER_XT_MARK=m
-CONFIG_NETFILTER_XT_CONNMARK=m
-CONFIG_NETFILTER_XT_SET=m
-
-#
-# Xtables targets
-#
-CONFIG_NETFILTER_XT_TARGET_AUDIT=m
-CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CT=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_HL=m
-CONFIG_NETFILTER_XT_TARGET_HMARK=m
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
-CONFIG_NETFILTER_XT_TARGET_LOG=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_NAT=m
-CONFIG_NETFILTER_XT_TARGET_NETMAP=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
-CONFIG_NETFILTER_XT_TARGET_RATEEST=m
-CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
-CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
-CONFIG_NETFILTER_XT_TARGET_TEE=m
-CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-CONFIG_NETFILTER_XT_TARGET_TRACE=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-
-#
-# Xtables matches
-#
-CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
-CONFIG_NETFILTER_XT_MATCH_BPF=m
-CONFIG_NETFILTER_XT_MATCH_CGROUP=m
-CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_CPU=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ECN=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_HL=m
-CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_IPVS=m
-CONFIG_NETFILTER_XT_MATCH_L2TP=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-CONFIG_NETFILTER_XT_MATCH_OSF=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-# end of Core Netfilter Configuration
-
-CONFIG_IP_SET=m
-CONFIG_IP_SET_MAX=256
-CONFIG_IP_SET_BITMAP_IP=m
-CONFIG_IP_SET_BITMAP_IPMAC=m
-CONFIG_IP_SET_BITMAP_PORT=m
-CONFIG_IP_SET_HASH_IP=m
-CONFIG_IP_SET_HASH_IPMARK=m
-CONFIG_IP_SET_HASH_IPPORT=m
-CONFIG_IP_SET_HASH_IPPORTIP=m
-CONFIG_IP_SET_HASH_IPPORTNET=m
-CONFIG_IP_SET_HASH_IPMAC=m
-CONFIG_IP_SET_HASH_MAC=m
-CONFIG_IP_SET_HASH_NETPORTNET=m
-CONFIG_IP_SET_HASH_NET=m
-CONFIG_IP_SET_HASH_NETNET=m
-CONFIG_IP_SET_HASH_NETPORT=m
-CONFIG_IP_SET_HASH_NETIFACE=m
-CONFIG_IP_SET_LIST_SET=m
-CONFIG_IP_VS=m
-CONFIG_IP_VS_IPV6=y
-# CONFIG_IP_VS_DEBUG is not set
-CONFIG_IP_VS_TAB_BITS=12
-
-#
-# IPVS transport protocol load balancing support
-#
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_AH_ESP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_PROTO_SCTP=y
-
-#
-# IPVS scheduler
-#
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_FO=m
-CONFIG_IP_VS_OVF=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_MH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_TWOS=m
-
-#
-# IPVS SH scheduler
-#
-CONFIG_IP_VS_SH_TAB_BITS=8
-
-#
-# IPVS MH scheduler
-#
-CONFIG_IP_VS_MH_TAB_INDEX=12
-
-#
-# IPVS application helper
-#
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_VS_NFCT=y
-CONFIG_IP_VS_PE_SIP=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_DEFRAG_IPV4=m
-CONFIG_NF_SOCKET_IPV4=m
-CONFIG_NF_TPROXY_IPV4=m
-CONFIG_NF_TABLES_IPV4=y
-CONFIG_NFT_REJECT_IPV4=m
-CONFIG_NFT_DUP_IPV4=m
-CONFIG_NFT_FIB_IPV4=m
-CONFIG_NF_TABLES_ARP=y
-CONFIG_NF_FLOW_TABLE_IPV4=m
-CONFIG_NF_DUP_IPV4=m
-# CONFIG_NF_LOG_ARP is not set
-CONFIG_NF_LOG_IPV4=m
-CONFIG_NF_REJECT_IPV4=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_NF_NAT_PPTP=m
-CONFIG_NF_NAT_H323=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_RPFILTER=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_SYNPROXY=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_SECURITY=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-# end of IP: Netfilter Configuration
-
-#
-# IPv6: Netfilter Configuration
-#
-CONFIG_NF_SOCKET_IPV6=m
-CONFIG_NF_TPROXY_IPV6=m
-CONFIG_NF_TABLES_IPV6=y
-CONFIG_NFT_REJECT_IPV6=m
-CONFIG_NFT_DUP_IPV6=m
-CONFIG_NFT_FIB_IPV6=m
-CONFIG_NF_FLOW_TABLE_IPV6=m
-CONFIG_NF_DUP_IPV6=m
-CONFIG_NF_REJECT_IPV6=m
-CONFIG_NF_LOG_IPV6=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RPFILTER=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_MATCH_SRH=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_TARGET_SYNPROXY=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_IP6_NF_SECURITY=m
-CONFIG_IP6_NF_NAT=m
-CONFIG_IP6_NF_TARGET_MASQUERADE=m
-CONFIG_IP6_NF_TARGET_NPT=m
-# end of IPv6: Netfilter Configuration
-
-CONFIG_NF_DEFRAG_IPV6=m
-
-#
-# DECnet: Netfilter Configuration
-#
-CONFIG_DECNET_NF_GRABULATOR=m
-# end of DECnet: Netfilter Configuration
-
-CONFIG_NF_TABLES_BRIDGE=m
-CONFIG_NFT_BRIDGE_META=m
-CONFIG_NFT_BRIDGE_REJECT=m
-CONFIG_NF_CONNTRACK_BRIDGE=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_IP6=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_BRIDGE_EBT_NFLOG=m
-# CONFIG_BPFILTER is not set
-CONFIG_IP_DCCP=m
-CONFIG_INET_DCCP_DIAG=m
-
-#
-# DCCP CCIDs Configuration
-#
-# CONFIG_IP_DCCP_CCID2_DEBUG is not set
-CONFIG_IP_DCCP_CCID3=y
-# CONFIG_IP_DCCP_CCID3_DEBUG is not set
-CONFIG_IP_DCCP_TFRC_LIB=y
-# end of DCCP CCIDs Configuration
-
-#
-# DCCP Kernel Hacking
-#
-# CONFIG_IP_DCCP_DEBUG is not set
-# end of DCCP Kernel Hacking
-
-CONFIG_IP_SCTP=m
-# CONFIG_SCTP_DBG_OBJCNT is not set
-CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
-CONFIG_SCTP_COOKIE_HMAC_MD5=y
-CONFIG_SCTP_COOKIE_HMAC_SHA1=y
-CONFIG_INET_SCTP_DIAG=m
-# CONFIG_RDS is not set
-CONFIG_TIPC=m
-CONFIG_TIPC_MEDIA_IB=y
-CONFIG_TIPC_MEDIA_UDP=y
-CONFIG_TIPC_CRYPTO=y
-CONFIG_TIPC_DIAG=m
-CONFIG_ATM=m
-CONFIG_ATM_CLIP=m
-# CONFIG_ATM_CLIP_NO_ICMP is not set
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-CONFIG_ATM_BR2684_IPFILTER=y
-CONFIG_L2TP=m
-# CONFIG_L2TP_V3 is not set
-CONFIG_STP=m
-CONFIG_GARP=m
-CONFIG_MRP=m
-CONFIG_BRIDGE=m
-CONFIG_BRIDGE_IGMP_SNOOPING=y
-CONFIG_BRIDGE_VLAN_FILTERING=y
-# CONFIG_BRIDGE_MRP is not set
-# CONFIG_BRIDGE_CFM is not set
-CONFIG_NET_DSA=m
-CONFIG_NET_DSA_TAG_AR9331=m
-CONFIG_NET_DSA_TAG_BRCM_COMMON=m
-# CONFIG_NET_DSA_TAG_BRCM is not set
-CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
-# CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set
-CONFIG_NET_DSA_TAG_HELLCREEK=m
-# CONFIG_NET_DSA_TAG_GSWIP is not set
-CONFIG_NET_DSA_TAG_DSA_COMMON=m
-CONFIG_NET_DSA_TAG_DSA=m
-CONFIG_NET_DSA_TAG_EDSA=m
-# CONFIG_NET_DSA_TAG_MTK is not set
-# CONFIG_NET_DSA_TAG_KSZ is not set
-CONFIG_NET_DSA_TAG_OCELOT=m
-CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
-# CONFIG_NET_DSA_TAG_QCA is not set
-CONFIG_NET_DSA_TAG_RTL4_A=m
-CONFIG_NET_DSA_TAG_RTL8_4=m
-# CONFIG_NET_DSA_TAG_LAN9303 is not set
-# CONFIG_NET_DSA_TAG_SJA1105 is not set
-CONFIG_NET_DSA_TAG_TRAILER=m
-CONFIG_NET_DSA_TAG_XRS700X=m
-CONFIG_NET_DSA_REALTEK=m
-CONFIG_NET_DSA_REALTEK_MDIO=m
-CONFIG_NET_DSA_REALTEK_RTL8365MB=m
-CONFIG_NET_DSA_REALTEK_RTL8366RB=m
-CONFIG_VLAN_8021Q=m
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_VLAN_8021Q_MVRP=y
-CONFIG_DECNET=m
-# CONFIG_DECNET_ROUTER is not set
-CONFIG_LLC=m
-CONFIG_LLC2=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_PHONET=m
-# CONFIG_6LOWPAN is not set
-CONFIG_IEEE802154=m
-CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
-CONFIG_IEEE802154_SOCKET=m
-CONFIG_MAC802154=m
-CONFIG_NET_SCHED=y
-
-#
-# Queueing/Scheduling
-#
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-# CONFIG_NET_SCH_ATM is not set
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_MULTIQ=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFB=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_CBS=m
-CONFIG_NET_SCH_ETF=m
-CONFIG_NET_SCH_TAPRIO=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_DRR=m
-CONFIG_NET_SCH_MQPRIO=m
-CONFIG_NET_SCH_SKBPRIO=m
-CONFIG_NET_SCH_CHOKE=m
-CONFIG_NET_SCH_QFQ=m
-CONFIG_NET_SCH_CODEL=m
-CONFIG_NET_SCH_FQ_CODEL=y
-CONFIG_NET_SCH_CAKE=m
-CONFIG_NET_SCH_FQ=m
-CONFIG_NET_SCH_HHF=m
-CONFIG_NET_SCH_PIE=m
-# CONFIG_NET_SCH_FQ_PIE is not set
-CONFIG_NET_SCH_INGRESS=m
-CONFIG_NET_SCH_PLUG=m
-CONFIG_NET_SCH_ETS=m
-# CONFIG_NET_SCH_DEFAULT is not set
-
-#
-# Classification
-#
-CONFIG_NET_CLS=y
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-# CONFIG_CLS_U32_PERF is not set
-# CONFIG_CLS_U32_MARK is not set
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_CLS_FLOW=m
-CONFIG_NET_CLS_CGROUP=y
-CONFIG_NET_CLS_BPF=m
-CONFIG_NET_CLS_FLOWER=m
-CONFIG_NET_CLS_MATCHALL=m
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_STACK=32
-CONFIG_NET_EMATCH_CMP=m
-CONFIG_NET_EMATCH_NBYTE=m
-CONFIG_NET_EMATCH_U32=m
-CONFIG_NET_EMATCH_META=m
-CONFIG_NET_EMATCH_TEXT=m
-CONFIG_NET_EMATCH_CANID=m
-CONFIG_NET_EMATCH_IPSET=m
-CONFIG_NET_EMATCH_IPT=m
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=m
-CONFIG_GACT_PROB=y
-CONFIG_NET_ACT_MIRRED=m
-CONFIG_NET_ACT_SAMPLE=m
-CONFIG_NET_ACT_IPT=m
-CONFIG_NET_ACT_NAT=m
-CONFIG_NET_ACT_PEDIT=m
-CONFIG_NET_ACT_SIMP=m
-CONFIG_NET_ACT_SKBEDIT=m
-CONFIG_NET_ACT_CSUM=m
-CONFIG_NET_ACT_MPLS=m
-CONFIG_NET_ACT_VLAN=m
-CONFIG_NET_ACT_BPF=m
-CONFIG_NET_ACT_CONNMARK=m
-CONFIG_NET_ACT_CTINFO=m
-CONFIG_NET_ACT_SKBMOD=m
-CONFIG_NET_ACT_IFE=m
-CONFIG_NET_ACT_TUNNEL_KEY=m
-CONFIG_NET_ACT_CT=m
-# CONFIG_NET_ACT_GATE is not set
-CONFIG_NET_IFE_SKBMARK=m
-CONFIG_NET_IFE_SKBPRIO=m
-CONFIG_NET_IFE_SKBTCINDEX=m
-# CONFIG_NET_TC_SKB_EXT is not set
-CONFIG_NET_SCH_FIFO=y
-CONFIG_DCB=y
-CONFIG_DNS_RESOLVER=y
-# CONFIG_BATMAN_ADV is not set
-CONFIG_OPENVSWITCH=m
-CONFIG_OPENVSWITCH_GRE=m
-CONFIG_OPENVSWITCH_VXLAN=m
-CONFIG_OPENVSWITCH_GENEVE=m
-CONFIG_VSOCKETS=m
-CONFIG_VSOCKETS_DIAG=m
-CONFIG_VSOCKETS_LOOPBACK=m
-CONFIG_VMWARE_VMCI_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS_COMMON=m
-CONFIG_HYPERV_VSOCKETS=m
-CONFIG_NETLINK_DIAG=m
-CONFIG_MPLS=y
-CONFIG_NET_MPLS_GSO=m
-CONFIG_MPLS_ROUTING=m
-CONFIG_MPLS_IPTUNNEL=m
-CONFIG_NET_NSH=m
-CONFIG_HSR=m
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_L3_MASTER_DEV=y
-CONFIG_QRTR=m
-CONFIG_QRTR_SMD=m
-CONFIG_QRTR_TUN=m
-CONFIG_QRTR_MHI=m
-# CONFIG_NET_NCSI is not set
-CONFIG_PCPU_DEV_REFCNT=y
-CONFIG_RPS=y
-CONFIG_RFS_ACCEL=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_XPS=y
-# CONFIG_CGROUP_NET_PRIO is not set
-CONFIG_CGROUP_NET_CLASSID=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_BQL=y
-CONFIG_BPF_STREAM_PARSER=y
-CONFIG_NET_FLOW_LIMIT=y
-
-#
-# Network testing
-#
-CONFIG_NET_PKTGEN=m
-# end of Network testing
-# end of Networking options
-
-CONFIG_HAMRADIO=y
-
-#
-# Packet Radio protocols
-#
-CONFIG_AX25=m
-CONFIG_AX25_DAMA_SLAVE=y
-CONFIG_NETROM=m
-CONFIG_ROSE=m
-
-#
-# AX.25 network device drivers
-#
-CONFIG_MKISS=m
-# CONFIG_6PACK is not set
-CONFIG_BPQETHER=m
-CONFIG_BAYCOM_SER_FDX=m
-CONFIG_BAYCOM_SER_HDX=m
-CONFIG_BAYCOM_PAR=m
-CONFIG_YAM=m
-# end of AX.25 network device drivers
-
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_GW=m
-CONFIG_CAN_J1939=m
-CONFIG_CAN_ISOTP=m
-
-#
-# CAN Device Drivers
-#
-CONFIG_CAN_VCAN=m
-CONFIG_CAN_VXCAN=m
-# CONFIG_CAN_SLCAN is not set
-# CONFIG_CAN_DEV is not set
-# CONFIG_CAN_DEBUG_DEVICES is not set
-# end of CAN Device Drivers
-
-CONFIG_BT=m
-CONFIG_BT_BREDR=y
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_CMTP=m
-CONFIG_BT_HIDP=m
-CONFIG_BT_HS=y
-CONFIG_BT_LE=y
-CONFIG_BT_LEDS=y
-# CONFIG_BT_MSFTEXT is not set
-CONFIG_BT_AOSPEXT=y
-# CONFIG_BT_SELFTEST is not set
-# CONFIG_BT_FEATURE_DEBUG is not set
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_INTEL=m
-CONFIG_BT_BCM=m
-CONFIG_BT_RTL=m
-CONFIG_BT_QCA=m
-CONFIG_BT_HCIBTUSB=m
-CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
-CONFIG_BT_HCIBTUSB_BCM=y
-CONFIG_BT_HCIBTUSB_MTK=y
-CONFIG_BT_HCIBTUSB_RTL=y
-CONFIG_BT_HCIBTSDIO=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_SERDEV=y
-CONFIG_BT_HCIUART_H4=y
-# CONFIG_BT_HCIUART_NOKIA is not set
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_ATH3K=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIUART_3WIRE=y
-CONFIG_BT_HCIUART_INTEL=y
-CONFIG_BT_HCIUART_BCM=y
-CONFIG_BT_HCIUART_RTL=y
-CONFIG_BT_HCIUART_QCA=y
-CONFIG_BT_HCIUART_AG6XX=y
-CONFIG_BT_HCIUART_MRVL=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIVHCI=m
-# CONFIG_BT_MRVL is not set
-# CONFIG_BT_ATH3K is not set
-CONFIG_BT_MTKSDIO=m
-# CONFIG_BT_MTKUART is not set
-CONFIG_BT_QCOMSMD=m
-CONFIG_BT_VIRTIO=m
-# end of Bluetooth device drivers
-
-CONFIG_AF_RXRPC=m
-CONFIG_AF_RXRPC_IPV6=y
-# CONFIG_AF_RXRPC_INJECT_LOSS is not set
-# CONFIG_AF_RXRPC_DEBUG is not set
-# CONFIG_RXKAD is not set
-CONFIG_AF_KCM=m
-CONFIG_STREAM_PARSER=y
-CONFIG_MCTP=y
-CONFIG_FIB_RULES=y
-CONFIG_WIRELESS=y
-CONFIG_WIRELESS_EXT=y
-# CONFIG_WEXT_CORE is not set
-# CONFIG_WEXT_PROC is not set
-# CONFIG_WEXT_SPY is not set
-# CONFIG_WEXT_PRIV is not set
-CONFIG_CFG80211=m
-# CONFIG_NL80211_TESTMODE is not set
-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
-CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
-CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
-CONFIG_CFG80211_DEFAULT_PS=y
-CONFIG_CFG80211_CRDA_SUPPORT=y
-# CONFIG_CFG80211_WEXT is not set
-# CONFIG_CFG80211_WEXT_EXPORT is not set
-CONFIG_LIB80211=m
-CONFIG_LIB80211_CRYPT_WEP=m
-CONFIG_LIB80211_CRYPT_CCMP=m
-CONFIG_LIB80211_CRYPT_TKIP=m
-# CONFIG_LIB80211_DEBUG is not set
-CONFIG_MAC80211=m
-CONFIG_MAC80211_HAS_RC=y
-CONFIG_MAC80211_RC_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
-CONFIG_MAC80211_MESH=y
-CONFIG_MAC80211_LEDS=y
-# CONFIG_MAC80211_MESSAGE_TRACING is not set
-# CONFIG_MAC80211_DEBUG_MENU is not set
-CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
-CONFIG_RFKILL=m
-CONFIG_RFKILL_LEDS=y
-CONFIG_RFKILL_INPUT=y
-CONFIG_RFKILL_GPIO=m
-CONFIG_NET_9P=y
-CONFIG_NET_9P_VIRTIO=m
-CONFIG_NET_9P_RDMA=m
-# CONFIG_NET_9P_DEBUG is not set
-# CONFIG_CAIF is not set
-CONFIG_CEPH_LIB=m
-# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
-# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
-CONFIG_NFC=m
-CONFIG_NFC_DIGITAL=m
-CONFIG_NFC_NCI=m
-# CONFIG_NFC_NCI_SPI is not set
-CONFIG_NFC_NCI_UART=m
-CONFIG_NFC_HCI=m
-CONFIG_NFC_SHDLC=y
-
-#
-# Near Field Communication (NFC) devices
-#
-# CONFIG_NFC_TRF7970A is not set
-# CONFIG_NFC_SIM is not set
-CONFIG_NFC_PORT100=m
-CONFIG_NFC_VIRTUAL_NCI=m
-CONFIG_NFC_FDP=m
-CONFIG_NFC_FDP_I2C=m
-CONFIG_NFC_PN544=m
-CONFIG_NFC_PN544_I2C=m
-# CONFIG_NFC_PN533_USB is not set
-# CONFIG_NFC_PN533_I2C is not set
-# CONFIG_NFC_PN532_UART is not set
-CONFIG_NFC_MICROREAD=m
-CONFIG_NFC_MICROREAD_I2C=m
-CONFIG_NFC_MRVL=m
-CONFIG_NFC_MRVL_USB=m
-CONFIG_NFC_MRVL_UART=m
-CONFIG_NFC_MRVL_I2C=m
-# CONFIG_NFC_ST21NFCA_I2C is not set
-# CONFIG_NFC_ST_NCI_I2C is not set
-# CONFIG_NFC_ST_NCI_SPI is not set
-# CONFIG_NFC_NXP_NCI is not set
-CONFIG_NFC_S3FWRN5=m
-CONFIG_NFC_S3FWRN5_I2C=m
-CONFIG_NFC_S3FWRN82_UART=m
-CONFIG_NFC_ST95HF=m
-# end of Near Field Communication (NFC) devices
-
-CONFIG_PSAMPLE=m
-CONFIG_NET_IFE=m
-CONFIG_LWTUNNEL=y
-CONFIG_LWTUNNEL_BPF=y
-# CONFIG_PAGE_POOL_STATS is not set
-CONFIG_DST_CACHE=y
-CONFIG_GRO_CELLS=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SOCK_MSG=y
-CONFIG_NET_DEVLINK=y
-CONFIG_PAGE_POOL=y
-CONFIG_FAILOVER=y
-CONFIG_ETHTOOL_NETLINK=y
-
-#
-# Device Drivers
-#
-CONFIG_ARM_AMBA=y
-CONFIG_TEGRA_AHB=y
-CONFIG_HAVE_PCI=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_SYSCALL=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_HOTPLUG_PCI_PCIE=y
-CONFIG_PCIEAER=y
-# CONFIG_PCIEAER_INJECT is not set
-# CONFIG_PCIE_ECRC is not set
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-CONFIG_PCIE_PME=y
-# CONFIG_PCIE_DPC is not set
-# CONFIG_PCIE_PTM is not set
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_QUIRKS=y
-# CONFIG_PCI_DEBUG is not set
-# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
-# CONFIG_PCI_STUB is not set
-# CONFIG_PCI_PF_STUB is not set
-CONFIG_PCI_ATS=y
-CONFIG_PCI_ECAM=y
-CONFIG_PCI_BRIDGE_EMUL=y
-CONFIG_PCI_IOV=y
-# CONFIG_PCI_PRI is not set
-# CONFIG_PCI_PASID is not set
-# CONFIG_PCI_P2PDMA is not set
-CONFIG_PCI_HYPERV=m
-CONFIG_PCI_LABEL=y
-# CONFIG_PCIE_BUS_TUNE_OFF is not set
-CONFIG_PCIE_BUS_DEFAULT=y
-# CONFIG_PCIE_BUS_SAFE is not set
-# CONFIG_PCIE_BUS_PERFORMANCE is not set
-# CONFIG_PCIE_BUS_PEER2PEER is not set
-CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_ACPI=y
-CONFIG_HOTPLUG_PCI_ACPI_IBM=m
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-CONFIG_HOTPLUG_PCI_SHPC=y
-
-#
-# PCI controller drivers
-#
-CONFIG_PCI_AARDVARK=y
-# CONFIG_PCIE_XILINX_NWL is not set
-# CONFIG_PCI_FTPCI100 is not set
-CONFIG_PCI_TEGRA=y
-CONFIG_PCIE_RCAR_HOST=y
-CONFIG_PCI_HOST_COMMON=y
-CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCIE_XILINX=y
-CONFIG_PCIE_XILINX_CPM=y
-CONFIG_PCI_XGENE=y
-CONFIG_PCI_XGENE_MSI=y
-CONFIG_PCIE_IPROC=y
-CONFIG_PCIE_IPROC_PLATFORM=y
-CONFIG_PCIE_IPROC_MSI=y
-CONFIG_PCIE_ALTERA=m
-CONFIG_PCIE_ALTERA_MSI=m
-CONFIG_PCI_HOST_THUNDER_PEM=y
-CONFIG_PCI_HOST_THUNDER_ECAM=y
-CONFIG_PCIE_ROCKCHIP=y
-CONFIG_PCIE_ROCKCHIP_HOST=m
-CONFIG_PCIE_MEDIATEK=m
-CONFIG_PCIE_MEDIATEK_GEN3=m
-CONFIG_PCIE_BRCMSTB=m
-CONFIG_PCIE_MICROCHIP_HOST=y
-CONFIG_PCIE_HISI_ERR=y
-CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR=0xfffff000
-CONFIG_PCIE_APPLE=m
-
-#
-# DesignWare PCI Core Support
-#
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-# CONFIG_PCIE_DW_PLAT_HOST is not set
-CONFIG_PCI_EXYNOS=m
-CONFIG_PCI_IMX6=y
-# CONFIG_PCI_KEYSTONE_HOST is not set
-CONFIG_PCI_LAYERSCAPE=y
-CONFIG_PCI_HISI=y
-CONFIG_PCIE_QCOM=y
-CONFIG_PCIE_ARMADA_8K=y
-CONFIG_PCIE_ROCKCHIP_DW_HOST=y
-CONFIG_PCIE_KEEMBAY=y
-CONFIG_PCIE_KEEMBAY_HOST=y
-CONFIG_PCIE_KIRIN=y
-# CONFIG_PCIE_HISI_STB is not set
-# CONFIG_PCI_MESON is not set
-# CONFIG_PCIE_TEGRA194_HOST is not set
-# CONFIG_PCIE_VISCONTI_HOST is not set
-# CONFIG_PCIE_UNIPHIER is not set
-# CONFIG_PCIE_AL is not set
-# end of DesignWare PCI Core Support
-
-#
-# Mobiveil PCIe Core Support
-#
-# CONFIG_PCIE_MOBIVEIL_PLAT is not set
-# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set
-# end of Mobiveil PCIe Core Support
-
-#
-# Cadence PCIe controllers support
-#
-CONFIG_PCIE_CADENCE=y
-CONFIG_PCIE_CADENCE_HOST=y
-# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
-CONFIG_PCI_J721E=y
-CONFIG_PCI_J721E_HOST=y
-# end of Cadence PCIe controllers support
-# end of PCI controller drivers
-
-#
-# PCI Endpoint
-#
-# CONFIG_PCI_ENDPOINT is not set
-# end of PCI Endpoint
-
-#
-# PCI switch controller drivers
-#
-# CONFIG_PCI_SW_SWITCHTEC is not set
-# end of PCI switch controller drivers
-
-CONFIG_CXL_BUS=m
-CONFIG_CXL_PCI=m
-CONFIG_CXL_MEM=m
-CONFIG_CXL_MEM_RAW_COMMANDS=y
-CONFIG_CXL_ACPI=m
-CONFIG_CXL_PMEM=m
-# CONFIG_PCCARD is not set
-CONFIG_RAPIDIO=m
-# CONFIG_RAPIDIO_TSI721 is not set
-CONFIG_RAPIDIO_DISC_TIMEOUT=30
-# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set
-# CONFIG_RAPIDIO_DMA_ENGINE is not set
-# CONFIG_RAPIDIO_DEBUG is not set
-# CONFIG_RAPIDIO_ENUM_BASIC is not set
-# CONFIG_RAPIDIO_CHMAN is not set
-# CONFIG_RAPIDIO_MPORT_CDEV is not set
-
-#
-# RapidIO Switch drivers
-#
-# CONFIG_RAPIDIO_TSI57X is not set
-# CONFIG_RAPIDIO_CPS_XX is not set
-# CONFIG_RAPIDIO_TSI568 is not set
-# CONFIG_RAPIDIO_CPS_GEN2 is not set
-# CONFIG_RAPIDIO_RXS_GEN3 is not set
-# end of RapidIO Switch drivers
-
-#
-# Generic Driver Options
-#
-CONFIG_AUXILIARY_BUS=y
-# CONFIG_UEVENT_HELPER is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_STANDALONE is not set
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-
-#
-# Firmware loader
-#
-CONFIG_FW_LOADER=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_FW_LOADER_USER_HELPER is not set
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_FW_LOADER_COMPRESS=y
-CONFIG_FW_CACHE=y
-# end of Firmware loader
-
-CONFIG_WANT_DEV_COREDUMP=y
-CONFIG_ALLOW_DEV_COREDUMP=y
-CONFIG_DEV_COREDUMP=y
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
-CONFIG_HMEM_REPORTING=y
-# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_SOC_BUS=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_AC97=m
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGMAP_SPMI=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_SOUNDWIRE=m
-CONFIG_REGMAP_SOUNDWIRE_MBQ=m
-CONFIG_REGMAP_I3C=m
-CONFIG_REGMAP_SPI_AVMM=m
-CONFIG_DMA_SHARED_BUFFER=y
-# CONFIG_DMA_FENCE_TRACE is not set
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_ARCH_NUMA=y
-# end of Generic Driver Options
-
-#
-# Bus devices
-#
-CONFIG_ARM_CCI=y
-# CONFIG_BRCMSTB_GISB_ARB is not set
-# CONFIG_MOXTET is not set
-# CONFIG_HISILICON_LPC is not set
-CONFIG_IMX_WEIM=y
-CONFIG_QCOM_EBI2=y
-CONFIG_SUN50I_DE2_BUS=y
-CONFIG_SUNXI_RSB=y
-CONFIG_TEGRA_ACONNECT=y
-# CONFIG_TEGRA_GMI is not set
-CONFIG_UNIPHIER_SYSTEM_BUS=y
-CONFIG_VEXPRESS_CONFIG=y
-# CONFIG_FSL_MC_BUS is not set
-CONFIG_MHI_BUS=m
-CONFIG_MHI_BUS_PCI_GENERIC=m
-# end of Bus devices
-
-CONFIG_CONNECTOR=m
-
-#
-# Firmware Drivers
-#
-
-#
-# ARM System Control and Management Interface Protocol
-#
-# CONFIG_ARM_SCMI_PROTOCOL is not set
-# end of ARM System Control and Management Interface Protocol
-
-CONFIG_ARM_SCPI_PROTOCOL=y
-CONFIG_ARM_SCPI_POWER_DOMAIN=y
-# CONFIG_ARM_SDE_INTERFACE is not set
-# CONFIG_FIRMWARE_MEMMAP is not set
-CONFIG_DMIID=y
-# CONFIG_DMI_SYSFS is not set
-# CONFIG_ISCSI_IBFT is not set
-CONFIG_RASPBERRYPI_FIRMWARE=y
-# CONFIG_FW_CFG_SYSFS is not set
-# CONFIG_INTEL_STRATIX10_SERVICE is not set
-CONFIG_QCOM_SCM=y
-# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-CONFIG_SYSFB=y
-CONFIG_SYSFB_SIMPLEFB=y
-CONFIG_TI_SCI_PROTOCOL=y
-# CONFIG_TURRIS_MOX_RWTM is not set
-CONFIG_ARM_FFA_TRANSPORT=m
-CONFIG_ARM_FFA_SMCCC=y
-CONFIG_TEE_BNXT_FW=m
-CONFIG_GOOGLE_FIRMWARE=y
-CONFIG_GOOGLE_COREBOOT_TABLE=m
-CONFIG_GOOGLE_MEMCONSOLE=m
-CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m
-CONFIG_GOOGLE_VPD=m
-
-#
-# EFI (Extensible Firmware Interface) Support
-#
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_VARS_PSTORE=m
-CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
-CONFIG_EFI_SOFT_RESERVE=y
-CONFIG_EFI_ZBOOT=y
-# CONFIG_EFI_ZBOOT_SIGNING is not set
-CONFIG_EFI_PARAMS_FROM_FDT=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_GENERIC_STUB=y
-CONFIG_EFI_ARMSTUB_DTB_LOADER=y
-CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
-CONFIG_EFI_BOOTLOADER_CONTROL=m
-CONFIG_EFI_CAPSULE_LOADER=m
-CONFIG_EFI_TEST=m
-# CONFIG_RESET_ATTACK_MITIGATION is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# end of EFI (Extensible Firmware Interface) Support
-
-CONFIG_UEFI_CPER=y
-CONFIG_UEFI_CPER_ARM=y
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-CONFIG_IMX_DSP=m
-CONFIG_IMX_SCU=y
-CONFIG_IMX_SCU_PD=y
-CONFIG_MESON_SM=y
-CONFIG_ARM_PSCI_FW=y
-# CONFIG_ARM_PSCI_CHECKER is not set
-CONFIG_HAVE_ARM_SMCCC=y
-CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
-CONFIG_ARM_SMCCC_SOC_ID=y
-
-#
-# Tegra firmware driver
-#
-CONFIG_TEGRA_IVC=y
-CONFIG_TEGRA_BPMP=y
-# end of Tegra firmware driver
-
-#
-# Zynq MPSoC Firmware Drivers
-#
-CONFIG_ZYNQMP_FIRMWARE=y
-# end of Zynq MPSoC Firmware Drivers
-# end of Firmware Drivers
-
-# CONFIG_GNSS is not set
-CONFIG_MTD=y
-CONFIG_MTD_TESTS=m
-
-#
-# Partition parsers
-#
-# CONFIG_MTD_AR7_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_OF_PARTS_BCM4908=y
-CONFIG_MTD_OF_PARTS_LINKSYS_NS=y
-# CONFIG_MTD_AFS_PARTS is not set
-CONFIG_MTD_PARSER_TRX=m
-CONFIG_MTD_REDBOOT_PARTS=m
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
-# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
-CONFIG_MTD_QCOMSMEM_PARTS=m
-# end of Partition parsers
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-
-#
-# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
-#
-CONFIG_FTL=m
-CONFIG_NFTL=m
-CONFIG_NFTL_RW=y
-CONFIG_INFTL=m
-CONFIG_RFD_FTL=m
-CONFIG_SSFDC=m
-# CONFIG_SM_FTL is not set
-CONFIG_MTD_OOPS=m
-CONFIG_MTD_SWAP=m
-# CONFIG_MTD_PARTITIONED_MASTER is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=m
-CONFIG_MTD_CFI_UTIL=y
-CONFIG_MTD_RAM=m
-CONFIG_MTD_ROM=m
-CONFIG_MTD_ABSENT=m
-# end of RAM/ROM/Flash chip drivers
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-# CONFIG_MTD_PHYSMAP_OF is not set
-CONFIG_MTD_INTEL_VR_NOR=m
-# CONFIG_MTD_PLATRAM is not set
-# end of Mapping drivers for chip access
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_DATAFLASH is not set
-CONFIG_MTD_MCHP23K256=m
-CONFIG_MTD_MCHP48L640=m
-# CONFIG_MTD_SST25L is not set
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTDRAM_TOTAL_SIZE=4096
-CONFIG_MTDRAM_ERASE_SIZE=128
-CONFIG_MTD_BLOCK2MTD=m
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOCG3 is not set
-# end of Self-contained MTD device drivers
-
-#
-# NAND
-#
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_ONENAND=m
-# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
-CONFIG_MTD_ONENAND_GENERIC=m
-CONFIG_MTD_ONENAND_OTP=y
-CONFIG_MTD_ONENAND_2X_PROGRAM=y
-CONFIG_MTD_RAW_NAND=m
-
-#
-# Raw/parallel NAND flash controllers
-#
-CONFIG_MTD_NAND_DENALI=m
-CONFIG_MTD_NAND_DENALI_PCI=m
-CONFIG_MTD_NAND_DENALI_DT=m
-CONFIG_MTD_NAND_OMAP2=m
-CONFIG_MTD_NAND_OMAP_BCH=y
-# CONFIG_MTD_NAND_CAFE is not set
-CONFIG_MTD_NAND_MARVELL=m
-CONFIG_MTD_NAND_BRCMNAND=m
-CONFIG_MTD_NAND_BRCMNAND_BCM63XX=m
-CONFIG_MTD_NAND_BRCMNAND_BCMBCA=m
-CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=m
-CONFIG_MTD_NAND_BRCMNAND_IPROC=m
-CONFIG_MTD_NAND_GPMI_NAND=m
-# CONFIG_MTD_NAND_FSL_IFC is not set
-CONFIG_MTD_NAND_MXC=m
-CONFIG_MTD_NAND_SUNXI=m
-# CONFIG_MTD_NAND_HISI504 is not set
-# CONFIG_MTD_NAND_QCOM is not set
-# CONFIG_MTD_NAND_MTK is not set
-# CONFIG_MTD_NAND_MXIC is not set
-# CONFIG_MTD_NAND_TEGRA is not set
-# CONFIG_MTD_NAND_MESON is not set
-# CONFIG_MTD_NAND_GPIO is not set
-# CONFIG_MTD_NAND_PLATFORM is not set
-# CONFIG_MTD_NAND_CADENCE is not set
-# CONFIG_MTD_NAND_ARASAN is not set
-CONFIG_MTD_NAND_INTEL_LGM=m
-CONFIG_MTD_NAND_ROCKCHIP=m
-
-#
-# Misc
-#
-CONFIG_MTD_NAND_NANDSIM=m
-# CONFIG_MTD_NAND_RICOH is not set
-CONFIG_MTD_NAND_DISKONCHIP=m
-# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
-# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set
-# CONFIG_MTD_SPI_NAND is not set
-
-#
-# ECC engine support
-#
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
-CONFIG_MTD_NAND_ECC_SW_BCH=y
-CONFIG_MTD_NAND_ECC_MXIC=y
-# end of ECC engine support
-# end of NAND
-
-#
-# LPDDR & LPDDR2 PCM memory drivers
-#
-CONFIG_MTD_LPDDR=m
-CONFIG_MTD_QINFO_PROBE=m
-# end of LPDDR & LPDDR2 PCM memory drivers
-
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SPI_NOR_SWP_DISABLE=y
-# CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE is not set
-# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
-CONFIG_SPI_HISI_SFC=m
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_FASTMAP is not set
-# CONFIG_MTD_UBI_GLUEBI is not set
-# CONFIG_MTD_UBI_BLOCK is not set
-# CONFIG_MTD_HYPERBUS is not set
-CONFIG_DTC=y
-CONFIG_OF=y
-# CONFIG_OF_UNITTEST is not set
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OF_RESOLVE=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_NUMA=y
-CONFIG_PARPORT=m
-CONFIG_PARPORT_PC=m
-CONFIG_PARPORT_PC_FIFO=y
-CONFIG_PARPORT_SERIAL=m
-# CONFIG_PARPORT_AX88796 is not set
-CONFIG_PARPORT_1284=y
-CONFIG_PARPORT_NOT_PC=y
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG_MESSAGES is not set
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_NULL_BLK is not set
-# CONFIG_PARIDE is not set
-CONFIG_CDROM=m
-CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
-CONFIG_ZRAM=m
-# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
-CONFIG_ZRAM_DEF_COMP_ZSTD=y
-# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
-# CONFIG_ZRAM_DEF_COMP_LZO is not set
-# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
-# CONFIG_ZRAM_DEF_COMP_842 is not set
-CONFIG_ZRAM_DEF_COMP="zstd"
-# CONFIG_ZRAM_WRITEBACK is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
-CONFIG_BLK_DEV_DRBD=m
-# CONFIG_DRBD_FAULT_INJECTION is not set
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_SX8 is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=m
-CONFIG_VIRTIO_BLK=m
-# CONFIG_BLK_DEV_RBD is not set
-# CONFIG_BLK_DEV_RSXX is not set
-CONFIG_BLK_DEV_RNBD=y
-CONFIG_BLK_DEV_RNBD_CLIENT=m
-CONFIG_BLK_DEV_RNBD_SERVER=m
-
-#
-# NVME Support
-#
-CONFIG_NVME_CORE=y
-CONFIG_BLK_DEV_NVME=y
-# CONFIG_NVME_MULTIPATH is not set
-CONFIG_NVME_VERBOSE_ERRORS=y
-CONFIG_NVME_HWMON=y
-CONFIG_NVME_FABRICS=m
-CONFIG_NVME_RDMA=m
-CONFIG_NVME_FC=m
-CONFIG_NVME_TCP=m
-CONFIG_NVME_APPLE=m
-CONFIG_NVME_TARGET=m
-# CONFIG_NVME_TARGET_PASSTHRU is not set
-CONFIG_NVME_TARGET_LOOP=m
-CONFIG_NVME_TARGET_RDMA=m
-CONFIG_NVME_TARGET_FC=m
-CONFIG_NVME_TARGET_FCLOOP=m
-CONFIG_NVME_TARGET_TCP=m
-# end of NVME Support
-
-#
-# Misc devices
-#
-# CONFIG_AD525X_DPOT is not set
-CONFIG_DUMMY_IRQ=m
-# CONFIG_PHANTOM is not set
-CONFIG_TIFM_CORE=m
-CONFIG_TIFM_7XX1=m
-# CONFIG_ICS932S401 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-CONFIG_HI6421V600_IRQ=m
-# CONFIG_HP_ILO is not set
-CONFIG_QCOM_COINCELL=m
-CONFIG_QCOM_FASTRPC=m
-# CONFIG_APDS9802ALS is not set
-# CONFIG_ISL29003 is not set
-# CONFIG_ISL29020 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_SENSORS_BH1770 is not set
-# CONFIG_SENSORS_APDS990X is not set
-# CONFIG_HMC6352 is not set
-# CONFIG_DS1682 is not set
-# CONFIG_LATTICE_ECP3_CONFIG is not set
-CONFIG_SRAM=y
-CONFIG_DW_XDATA_PCIE=m
-# CONFIG_PCI_ENDPOINT_TEST is not set
-# CONFIG_XILINX_SDFEC is not set
-CONFIG_MISC_RTSX=m
-CONFIG_HISI_HIKEY_USB=m
-CONFIG_OPEN_DICE=m
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-# CONFIG_EEPROM_AT24 is not set
-CONFIG_EEPROM_AT25=m
-CONFIG_EEPROM_LEGACY=m
-# CONFIG_EEPROM_MAX6875 is not set
-CONFIG_EEPROM_93CX6=m
-# CONFIG_EEPROM_93XX46 is not set
-# CONFIG_EEPROM_IDT_89HPESX is not set
-CONFIG_EEPROM_EE1004=m
-# end of EEPROM support
-
-# CONFIG_CB710_CORE is not set
-
-#
-# Texas Instruments shared transport line discipline
-#
-CONFIG_TI_ST=m
-# end of Texas Instruments shared transport line discipline
-
-# CONFIG_SENSORS_LIS3_I2C is not set
-CONFIG_ALTERA_STAPL=m
-CONFIG_VMWARE_VMCI=m
-# CONFIG_GENWQE is not set
-CONFIG_ECHO=m
-CONFIG_BCM_VK=m
-CONFIG_BCM_VK_TTY=y
-# CONFIG_MISC_ALCOR_PCI is not set
-CONFIG_MISC_RTSX_PCI=m
-CONFIG_MISC_RTSX_USB=m
-# CONFIG_HABANA_AI is not set
-CONFIG_UACCE=m
-CONFIG_PVPANIC=y
-CONFIG_PVPANIC_MMIO=m
-CONFIG_PVPANIC_PCI=m
-CONFIG_GP_PCI1XXXX=m
-# end of Misc devices
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=m
-CONFIG_RAID_ATTRS=m
-CONFIG_SCSI_COMMON=m
-CONFIG_SCSI=m
-CONFIG_SCSI_DMA=y
-CONFIG_SCSI_NETLINK=y
-# CONFIG_SCSI_PROC_FS is not set
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_BLK_DEV_BSG=y
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-# CONFIG_SCSI_SCAN_ASYNC is not set
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_ISCSI_ATTRS=m
-CONFIG_SCSI_SAS_ATTRS=m
-CONFIG_SCSI_SAS_LIBSAS=m
-CONFIG_SCSI_SAS_ATA=y
-CONFIG_SCSI_SAS_HOST_SMP=y
-CONFIG_SCSI_SRP_ATTRS=m
-# end of SCSI Transports
-
-CONFIG_SCSI_LOWLEVEL=y
-CONFIG_ISCSI_TCP=m
-CONFIG_ISCSI_BOOT_SYSFS=m
-# CONFIG_SCSI_CXGB3_ISCSI is not set
-# CONFIG_SCSI_CXGB4_ISCSI is not set
-CONFIG_SCSI_BNX2_ISCSI=m
-CONFIG_BE2ISCSI=m
-CONFIG_BLK_DEV_3W_XXXX_RAID=m
-CONFIG_SCSI_HPSA=m
-CONFIG_SCSI_3W_9XXX=m
-CONFIG_SCSI_3W_SAS=m
-CONFIG_SCSI_ACARD=m
-CONFIG_SCSI_AACRAID=m
-CONFIG_SCSI_AIC7XXX=m
-CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
-CONFIG_AIC7XXX_RESET_DELAY_MS=5000
-CONFIG_AIC7XXX_DEBUG_ENABLE=y
-CONFIG_AIC7XXX_DEBUG_MASK=0
-CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
-CONFIG_SCSI_AIC79XX=m
-CONFIG_AIC79XX_CMDS_PER_DEVICE=32
-CONFIG_AIC79XX_RESET_DELAY_MS=5000
-CONFIG_AIC79XX_DEBUG_ENABLE=y
-CONFIG_AIC79XX_DEBUG_MASK=0
-CONFIG_AIC79XX_REG_PRETTY_PRINT=y
-CONFIG_SCSI_AIC94XX=m
-CONFIG_AIC94XX_DEBUG=y
-CONFIG_SCSI_HISI_SAS=m
-CONFIG_SCSI_HISI_SAS_PCI=m
-# CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE is not set
-CONFIG_SCSI_MVSAS=m
-CONFIG_SCSI_MVSAS_DEBUG=y
-# CONFIG_SCSI_MVSAS_TASKLET is not set
-CONFIG_SCSI_MVUMI=m
-CONFIG_SCSI_ADVANSYS=m
-CONFIG_SCSI_ARCMSR=m
-CONFIG_SCSI_ESAS2R=m
-CONFIG_MEGARAID_NEWGEN=y
-CONFIG_MEGARAID_MM=m
-CONFIG_MEGARAID_MAILBOX=m
-CONFIG_MEGARAID_LEGACY=m
-CONFIG_MEGARAID_SAS=m
-CONFIG_SCSI_MPT3SAS=m
-CONFIG_SCSI_MPT2SAS_MAX_SGE=128
-CONFIG_SCSI_MPT3SAS_MAX_SGE=128
-CONFIG_SCSI_MPT2SAS=m
-CONFIG_SCSI_MPI3MR=m
-CONFIG_SCSI_SMARTPQI=m
-CONFIG_SCSI_UFSHCD=m
-CONFIG_SCSI_UFSHCD_PCI=m
-CONFIG_SCSI_UFS_DWC_TC_PCI=m
-CONFIG_SCSI_UFSHCD_PLATFORM=m
-CONFIG_SCSI_UFS_CDNS_PLATFORM=m
-CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m
-CONFIG_SCSI_UFS_QCOM=m
-CONFIG_SCSI_UFS_MEDIATEK=m
-CONFIG_SCSI_UFS_HISI=m
-CONFIG_SCSI_UFS_RENESAS=m
-CONFIG_SCSI_UFS_TI_J721E=m
-CONFIG_SCSI_UFS_BSG=y
-CONFIG_SCSI_UFS_EXYNOS=m
-CONFIG_SCSI_UFS_CRYPTO=y
-CONFIG_SCSI_UFS_HPB=y
-CONFIG_SCSI_UFS_HWMON=y
-CONFIG_SCSI_HPTIOP=m
-CONFIG_SCSI_MYRB=m
-CONFIG_SCSI_MYRS=m
-CONFIG_HYPERV_STORAGE=m
-CONFIG_LIBFC=m
-# CONFIG_LIBFCOE is not set
-CONFIG_SCSI_SNIC=m
-CONFIG_SCSI_DMX3191D=m
-CONFIG_SCSI_FDOMAIN=m
-CONFIG_SCSI_FDOMAIN_PCI=m
-CONFIG_SCSI_IPS=m
-CONFIG_SCSI_INITIO=m
-CONFIG_SCSI_INIA100=m
-CONFIG_SCSI_PPA=m
-CONFIG_SCSI_IMM=m
-# CONFIG_SCSI_IZIP_EPP16 is not set
-# CONFIG_SCSI_IZIP_SLOW_CTR is not set
-CONFIG_SCSI_STEX=m
-CONFIG_SCSI_SYM53C8XX_2=m
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-# CONFIG_SCSI_IPR is not set
-# CONFIG_SCSI_QLOGIC_1280 is not set
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_QLA_ISCSI is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-CONFIG_SCSI_AM53C974=m
-CONFIG_SCSI_WD719X=m
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_PMCRAID is not set
-# CONFIG_SCSI_PM8001 is not set
-# CONFIG_SCSI_BFA_FC is not set
-CONFIG_SCSI_VIRTIO=m
-# CONFIG_SCSI_CHELSIO_FCOE is not set
-# CONFIG_SCSI_DH is not set
-# end of SCSI device support
-
-CONFIG_HAVE_PATA_PLATFORM=y
-CONFIG_PATA_OF_PLATFORM=m
-CONFIG_ATA=m
-CONFIG_SATA_HOST=y
-CONFIG_PATA_TIMINGS=y
-# CONFIG_ATA_VERBOSE_ERROR is not set
-CONFIG_ATA_FORCE=y
-CONFIG_ATA_ACPI=y
-# CONFIG_SATA_ZPODD is not set
-CONFIG_SATA_PMP=y
-
-#
-# Controllers with non-SFF native interface
-#
-CONFIG_SATA_AHCI=m
-CONFIG_SATA_MOBILE_LPM_POLICY=0
-CONFIG_SATA_AHCI_PLATFORM=m
-CONFIG_AHCI_BRCM=m
-CONFIG_AHCI_DWC=m
-CONFIG_AHCI_IMX=m
-CONFIG_AHCI_CEVA=m
-CONFIG_AHCI_MTK=m
-CONFIG_AHCI_MVEBU=m
-CONFIG_AHCI_SUNXI=m
-CONFIG_AHCI_TEGRA=m
-CONFIG_AHCI_XGENE=m
-CONFIG_AHCI_QORIQ=m
-CONFIG_SATA_AHCI_SEATTLE=m
-CONFIG_SATA_INIC162X=m
-CONFIG_SATA_ACARD_AHCI=m
-CONFIG_SATA_SIL24=m
-CONFIG_ATA_SFF=y
-
-#
-# SFF controllers with custom DMA interface
-#
-CONFIG_PDC_ADMA=m
-CONFIG_SATA_QSTOR=m
-# CONFIG_SATA_SX4 is not set
-CONFIG_ATA_BMDMA=y
-
-#
-# SATA SFF controllers with BMDMA
-#
-# CONFIG_ATA_PIIX is not set
-CONFIG_SATA_DWC=m
-# CONFIG_SATA_DWC_OLD_DMA is not set
-# CONFIG_SATA_DWC_DEBUG is not set
-CONFIG_SATA_MV=m
-# CONFIG_SATA_NV is not set
-CONFIG_SATA_PROMISE=m
-CONFIG_SATA_RCAR=m
-CONFIG_SATA_SIL=m
-# CONFIG_SATA_SIS is not set
-CONFIG_SATA_SVW=m
-# CONFIG_SATA_ULI is not set
-CONFIG_SATA_VIA=m
-CONFIG_SATA_VITESSE=m
-
-#
-# PATA SFF controllers with BMDMA
-#
-CONFIG_PATA_ALI=m
-CONFIG_PATA_AMD=m
-CONFIG_PATA_ARTOP=m
-CONFIG_PATA_ATIIXP=m
-CONFIG_PATA_ATP867X=m
-CONFIG_PATA_CMD64X=m
-CONFIG_PATA_CYPRESS=m
-CONFIG_PATA_EFAR=m
-CONFIG_PATA_HPT366=m
-CONFIG_PATA_HPT37X=m
-CONFIG_PATA_HPT3X2N=m
-CONFIG_PATA_HPT3X3=m
-CONFIG_PATA_HPT3X3_DMA=y
-CONFIG_PATA_IMX=m
-CONFIG_PATA_IT8213=m
-CONFIG_PATA_IT821X=m
-CONFIG_PATA_JMICRON=m
-CONFIG_PATA_MARVELL=m
-CONFIG_PATA_NETCELL=m
-CONFIG_PATA_NINJA32=m
-CONFIG_PATA_NS87415=m
-CONFIG_PATA_OLDPIIX=m
-CONFIG_PATA_OPTIDMA=m
-CONFIG_PATA_PDC2027X=m
-CONFIG_PATA_PDC_OLD=m
-CONFIG_PATA_RADISYS=m
-CONFIG_PATA_RDC=m
-CONFIG_PATA_SCH=m
-CONFIG_PATA_SERVERWORKS=m
-CONFIG_PATA_SIL680=m
-CONFIG_PATA_SIS=m
-CONFIG_PATA_TOSHIBA=m
-CONFIG_PATA_TRIFLEX=m
-CONFIG_PATA_VIA=m
-CONFIG_PATA_WINBOND=m
-
-#
-# PIO-only SFF controllers
-#
-CONFIG_PATA_CMD640_PCI=m
-CONFIG_PATA_MPIIX=m
-CONFIG_PATA_NS87410=m
-CONFIG_PATA_OPTI=m
-CONFIG_PATA_PLATFORM=m
-CONFIG_PATA_OF_PLATFORM=m
-CONFIG_PATA_RZ1000=m
-
-#
-# Generic fallback / legacy drivers
-#
-CONFIG_PATA_ACPI=m
-CONFIG_ATA_GENERIC=m
-# CONFIG_PATA_LEGACY is not set
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=y
-# CONFIG_MD_AUTODETECT is not set
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID456=m
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_MD_CLUSTER=m
-CONFIG_BCACHE=m
-# CONFIG_BCACHE_DEBUG is not set
-# CONFIG_BCACHE_CLOSURES_DEBUG is not set
-CONFIG_BCACHE_ASYNC_REGISTRATION=y
-CONFIG_BLK_DEV_DM_BUILTIN=y
-CONFIG_BLK_DEV_DM=m
-# CONFIG_DM_DEBUG is not set
-CONFIG_DM_BUFIO=m
-# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
-CONFIG_DM_BIO_PRISON=m
-CONFIG_DM_PERSISTENT_DATA=m
-CONFIG_DM_UNSTRIPED=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_THIN_PROVISIONING=m
-CONFIG_DM_CACHE=m
-CONFIG_DM_CACHE_SMQ=m
-CONFIG_DM_WRITECACHE=m
-# CONFIG_DM_EBS is not set
-CONFIG_DM_ERA=m
-CONFIG_DM_CLONE=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_LOG_USERSPACE=m
-CONFIG_DM_RAID=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_QL=m
-CONFIG_DM_MULTIPATH_ST=m
-# CONFIG_DM_MULTIPATH_HST is not set
-CONFIG_DM_MULTIPATH_IOA=m
-# CONFIG_DM_DELAY is not set
-# CONFIG_DM_DUST is not set
-CONFIG_DM_UEVENT=y
-CONFIG_DM_FLAKEY=m
-CONFIG_DM_VERITY=m
-CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
-# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING is not set
-# CONFIG_DM_VERITY_FEC is not set
-CONFIG_DM_SWITCH=m
-# CONFIG_DM_LOG_WRITES is not set
-CONFIG_DM_INTEGRITY=m
-CONFIG_DM_AUDIT=y
-# CONFIG_TARGET_CORE is not set
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_FIREWIRE is not set
-# CONFIG_FIREWIRE_NOSY is not set
-# end of IEEE 1394 (FireWire) support
-
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_NET_CORE=y
-CONFIG_BONDING=m
-CONFIG_DUMMY=m
-CONFIG_WIREGUARD=m
-# CONFIG_WIREGUARD_DEBUG is not set
-CONFIG_EQUALIZER=m
-CONFIG_NET_FC=y
-CONFIG_IFB=m
-CONFIG_NET_TEAM=m
-CONFIG_NET_TEAM_MODE_BROADCAST=m
-CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
-CONFIG_NET_TEAM_MODE_RANDOM=m
-CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
-CONFIG_NET_TEAM_MODE_LOADBALANCE=m
-CONFIG_MACVLAN=m
-CONFIG_MACVTAP=m
-CONFIG_IPVLAN_L3S=y
-CONFIG_IPVLAN=m
-CONFIG_IPVTAP=m
-CONFIG_VXLAN=m
-CONFIG_GENEVE=m
-# CONFIG_BAREUDP is not set
-CONFIG_GTP=m
-CONFIG_AMT=m
-CONFIG_MACSEC=m
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_NETPOLL=y
-CONFIG_NET_POLL_CONTROLLER=y
-# CONFIG_RIONET is not set
-CONFIG_TUN=m
-CONFIG_TAP=m
-# CONFIG_TUN_VNET_CROSS_LE is not set
-CONFIG_VETH=m
-CONFIG_VIRTIO_NET=m
-CONFIG_NLMON=m
-CONFIG_NET_VRF=m
-CONFIG_VSOCKMON=m
-CONFIG_MHI_NET=m
-CONFIG_ARCNET=m
-CONFIG_ARCNET_1201=m
-CONFIG_ARCNET_1051=m
-CONFIG_ARCNET_RAW=m
-CONFIG_ARCNET_CAP=m
-CONFIG_ARCNET_COM90xx=m
-CONFIG_ARCNET_COM90xxIO=m
-CONFIG_ARCNET_RIM_I=m
-CONFIG_ARCNET_COM20020=m
-CONFIG_ARCNET_COM20020_PCI=m
-CONFIG_ATM_DRIVERS=y
-CONFIG_ATM_DUMMY=m
-CONFIG_ATM_TCP=m
-CONFIG_ATM_LANAI=m
-CONFIG_ATM_ENI=m
-# CONFIG_ATM_ENI_DEBUG is not set
-# CONFIG_ATM_ENI_TUNE_BURST is not set
-CONFIG_ATM_NICSTAR=m
-CONFIG_ATM_NICSTAR_USE_SUNI=y
-CONFIG_ATM_NICSTAR_USE_IDT77105=y
-CONFIG_ATM_IDT77252=m
-# CONFIG_ATM_IDT77252_DEBUG is not set
-# CONFIG_ATM_IDT77252_RCV_ALL is not set
-CONFIG_ATM_IDT77252_USE_SUNI=y
-CONFIG_ATM_IA=m
-# CONFIG_ATM_IA_DEBUG is not set
-CONFIG_ATM_FORE200E=m
-CONFIG_ATM_FORE200E_USE_TASKLET=y
-CONFIG_ATM_FORE200E_TX_RETRY=16
-CONFIG_ATM_FORE200E_DEBUG=0
-CONFIG_ATM_HE=m
-CONFIG_ATM_HE_USE_SUNI=y
-CONFIG_ATM_SOLOS=m
-
-#
-# Distributed Switch Architecture drivers
-#
-# CONFIG_B53 is not set
-# CONFIG_NET_DSA_BCM_SF2 is not set
-# CONFIG_NET_DSA_LOOP is not set
-CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
-# CONFIG_NET_DSA_LANTIQ_GSWIP is not set
-# CONFIG_NET_DSA_MT7530 is not set
-CONFIG_NET_DSA_MV88E6060=m
-# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set
-# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set
-CONFIG_NET_DSA_MV88E6XXX=m
-# CONFIG_NET_DSA_MV88E6XXX_PTP is not set
-CONFIG_NET_DSA_MSCC_FELIX=m
-CONFIG_NET_DSA_MSCC_SEVILLE=m
-CONFIG_NET_DSA_AR9331=m
-# CONFIG_NET_DSA_SJA1105 is not set
-CONFIG_NET_DSA_XRS700X=m
-CONFIG_NET_DSA_XRS700X_I2C=m
-CONFIG_NET_DSA_XRS700X_MDIO=m
-# CONFIG_NET_DSA_QCA8K is not set
-CONFIG_NET_DSA_REALTEK_SMI=m
-# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
-# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set
-# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set
-# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set
-# end of Distributed Switch Architecture drivers
-
-CONFIG_ETHERNET=y
-CONFIG_NET_VENDOR_3COM=y
-CONFIG_VORTEX=m
-CONFIG_TYPHOON=m
-CONFIG_NET_VENDOR_ACTIONS=y
-CONFIG_OWL_EMAC=m
-CONFIG_NET_VENDOR_ADAPTEC=y
-CONFIG_ADAPTEC_STARFIRE=m
-CONFIG_NET_VENDOR_AGERE=y
-CONFIG_ET131X=m
-CONFIG_NET_VENDOR_ALACRITECH=y
-# CONFIG_SLICOSS is not set
-CONFIG_NET_VENDOR_ALLWINNER=y
-# CONFIG_SUN4I_EMAC is not set
-# CONFIG_NET_VENDOR_ALTEON is not set
-# CONFIG_ALTERA_TSE is not set
-CONFIG_NET_VENDOR_AMAZON=y
-CONFIG_ENA_ETHERNET=m
-# CONFIG_NET_VENDOR_AMD is not set
-CONFIG_NET_XGENE=y
-CONFIG_NET_XGENE_V2=m
-CONFIG_NET_VENDOR_AQUANTIA=y
-CONFIG_AQTION=m
-CONFIG_NET_VENDOR_ARC=y
-CONFIG_ARC_EMAC_CORE=y
-CONFIG_EMAC_ROCKCHIP=y
-CONFIG_NET_VENDOR_ASIX=y
-CONFIG_SPI_AX88796C=m
-CONFIG_SPI_AX88796C_COMPRESSION=y
-# CONFIG_NET_VENDOR_ATHEROS is not set
-CONFIG_NET_VENDOR_BROADCOM=y
-CONFIG_B44=y
-CONFIG_B44_PCI_AUTOSELECT=y
-CONFIG_B44_PCICORE_AUTOSELECT=y
-CONFIG_B44_PCI=y
-CONFIG_BCM4908_ENET=m
-CONFIG_BCMGENET=y
-CONFIG_BNX2=y
-CONFIG_CNIC=m
-# CONFIG_TIGON3 is not set
-# CONFIG_BNX2X is not set
-CONFIG_BGMAC=y
-CONFIG_BGMAC_PLATFORM=y
-# CONFIG_SYSTEMPORT is not set
-CONFIG_BNXT=m
-CONFIG_BNXT_SRIOV=y
-CONFIG_BNXT_FLOWER_OFFLOAD=y
-CONFIG_BNXT_DCB=y
-CONFIG_BNXT_HWMON=y
-# CONFIG_NET_VENDOR_BROCADE is not set
-CONFIG_NET_VENDOR_CADENCE=y
-CONFIG_MACB=y
-CONFIG_MACB_USE_HWSTAMP=y
-# CONFIG_MACB_PCI is not set
-CONFIG_NET_VENDOR_CAVIUM=y
-CONFIG_THUNDER_NIC_PF=y
-CONFIG_THUNDER_NIC_VF=m
-CONFIG_THUNDER_NIC_BGX=y
-CONFIG_THUNDER_NIC_RGX=y
-CONFIG_CAVIUM_PTP=y
-# CONFIG_LIQUIDIO is not set
-# CONFIG_LIQUIDIO_VF is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_CISCO is not set
-CONFIG_NET_VENDOR_CORTINA=y
-CONFIG_NET_VENDOR_DAVICOM=y
-CONFIG_DM9051=m
-# CONFIG_GEMINI_ETHERNET is not set
-# CONFIG_DNET is not set
-# CONFIG_NET_VENDOR_DEC is not set
-CONFIG_NET_VENDOR_DLINK=y
-# CONFIG_DL2K is not set
-CONFIG_SUNDANCE=m
-# CONFIG_SUNDANCE_MMIO is not set
-CONFIG_NET_VENDOR_EMULEX=y
-CONFIG_BE2NET=m
-CONFIG_BE2NET_HWMON=y
-CONFIG_BE2NET_BE2=y
-CONFIG_BE2NET_BE3=y
-CONFIG_BE2NET_LANCER=y
-CONFIG_BE2NET_SKYHAWK=y
-CONFIG_NET_VENDOR_EZCHIP=y
-# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
-CONFIG_NET_VENDOR_FREESCALE=y
-CONFIG_NET_VENDOR_FUNGIBLE=y
-CONFIG_FUN_ETH=m
-CONFIG_FEC=m
-# CONFIG_FSL_FMAN is not set
-# CONFIG_FSL_PQ_MDIO is not set
-# CONFIG_FSL_XGMAC_MDIO is not set
-# CONFIG_GIANFAR is not set
-CONFIG_FSL_DPAA2_SWITCH=m
-# CONFIG_FSL_ENETC is not set
-# CONFIG_FSL_ENETC_VF is not set
-CONFIG_FSL_ENETC_IERB=m
-CONFIG_FSL_ENETC_MDIO=m
-CONFIG_NET_VENDOR_GOOGLE=y
-CONFIG_GVE=m
-CONFIG_NET_VENDOR_HISILICON=y
-CONFIG_HIX5HD2_GMAC=m
-CONFIG_HISI_FEMAC=m
-CONFIG_HIP04_ETH=m
-CONFIG_HI13X1_GMAC=y
-CONFIG_HNS_MDIO=y
-CONFIG_HNS=y
-CONFIG_HNS_DSAF=y
-CONFIG_HNS_ENET=y
-CONFIG_HNS3=m
-CONFIG_HNS3_HCLGE=m
-# CONFIG_HNS3_DCB is not set
-CONFIG_HNS3_HCLGEVF=m
-# CONFIG_HNS3_ENET is not set
-CONFIG_NET_VENDOR_HUAWEI=y
-CONFIG_HINIC=m
-CONFIG_NET_VENDOR_I825XX=y
-CONFIG_NET_VENDOR_INTEL=y
-CONFIG_E100=m
-# CONFIG_E1000 is not set
-CONFIG_E1000E=y
-CONFIG_IGB=y
-CONFIG_IGB_HWMON=y
-CONFIG_IGBVF=y
-# CONFIG_IXGB is not set
-# CONFIG_IXGBE is not set
-# CONFIG_IXGBEVF is not set
-# CONFIG_I40E is not set
-# CONFIG_I40EVF is not set
-# CONFIG_ICE is not set
-# CONFIG_FM10K is not set
-# CONFIG_IGC is not set
-CONFIG_NET_VENDOR_MICROSOFT=y
-# CONFIG_JME is not set
-CONFIG_NET_VENDOR_LITEX=y
-CONFIG_LITEX_LITEETH=m
-CONFIG_NET_VENDOR_MARVELL=y
-CONFIG_MVMDIO=y
-CONFIG_MVNETA=y
-CONFIG_MVPP2=y
-CONFIG_MVPP2_PTP=y
-# CONFIG_PXA168_ETH is not set
-# CONFIG_SKGE is not set
-CONFIG_SKY2=y
-CONFIG_OCTEONTX2_MBOX=m
-# CONFIG_OCTEONTX2_AF is not set
-CONFIG_OCTEONTX2_PF=m
-# CONFIG_OCTEONTX2_VF is not set
-CONFIG_OCTEON_EP=m
-CONFIG_PRESTERA=m
-CONFIG_PRESTERA_PCI=m
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NET_MEDIATEK_SOC=m
-CONFIG_NET_MEDIATEK_STAR_EMAC=m
-CONFIG_NET_VENDOR_MELLANOX=y
-CONFIG_MLX4_EN=m
-CONFIG_MLX4_EN_DCB=y
-CONFIG_MLX4_CORE=m
-# CONFIG_MLX4_DEBUG is not set
-CONFIG_MLX4_CORE_GEN2=y
-CONFIG_MLX5_CORE=m
-CONFIG_MLX5_ACCEL=y
-CONFIG_MLX5_FPGA=y
-CONFIG_MLX5_CORE_EN=y
-CONFIG_MLX5_EN_ARFS=y
-CONFIG_MLX5_EN_RXNFC=y
-CONFIG_MLX5_MPFS=y
-CONFIG_MLX5_ESWITCH=y
-CONFIG_MLX5_BRIDGE=y
-CONFIG_MLX5_CLS_ACT=y
-CONFIG_MLX5_TC_SAMPLE=y
-CONFIG_MLX5_CORE_EN_DCB=y
-CONFIG_MLX5_CORE_IPOIB=y
-CONFIG_MLX5_EN_MACSEC=y
-CONFIG_MLX5_EN_IPSEC=y
-# CONFIG_MLX5_FPGA_IPSEC is not set
-# CONFIG_MLX5_IPSEC is not set
-CONFIG_MLX5_SW_STEERING=y
-CONFIG_MLX5_SF=y
-CONFIG_MLX5_SF_MANAGER=y
-CONFIG_MLXSW_CORE=m
-CONFIG_MLXSW_CORE_HWMON=y
-CONFIG_MLXSW_CORE_THERMAL=y
-CONFIG_MLXSW_PCI=m
-CONFIG_MLXSW_I2C=m
-CONFIG_MLXSW_SPECTRUM=m
-CONFIG_MLXSW_SPECTRUM_DCB=y
-CONFIG_MLXSW_MINIMAL=m
-CONFIG_MLXFW=m
-CONFIG_MLXBF_GIGE=m
-CONFIG_NVSW_SN2201=m
-# CONFIG_NET_VENDOR_MICREL is not set
-CONFIG_NET_VENDOR_MICROCHIP=y
-# CONFIG_ENC28J60 is not set
-# CONFIG_ENCX24J600 is not set
-# CONFIG_LAN743X is not set
-CONFIG_SPARX5_SWITCH=m
-CONFIG_NET_VENDOR_MICROSEMI=y
-CONFIG_MSCC_OCELOT_SWITCH_LIB=m
-# CONFIG_MSCC_OCELOT_SWITCH is not set
-# CONFIG_NET_VENDOR_MYRI is not set
-CONFIG_FEALNX=m
-CONFIG_NET_VENDOR_NATSEMI=y
-CONFIG_NATSEMI=m
-CONFIG_NS83820=m
-CONFIG_NET_VENDOR_NETERION=y
-# CONFIG_S2IO is not set
-# CONFIG_VXGE is not set
-CONFIG_NET_VENDOR_NETRONOME=y
-# CONFIG_NFP is not set
-CONFIG_NET_VENDOR_NI=y
-# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
-CONFIG_NET_VENDOR_8390=y
-CONFIG_NE2K_PCI=m
-# CONFIG_NET_VENDOR_NVIDIA is not set
-# CONFIG_NET_VENDOR_OKI is not set
-# CONFIG_ETHOC is not set
-CONFIG_NET_VENDOR_PACKET_ENGINES=y
-CONFIG_HAMACHI=m
-CONFIG_YELLOWFIN=m
-CONFIG_NET_VENDOR_PENSANDO=y
-# CONFIG_IONIC is not set
-# CONFIG_NET_VENDOR_QLOGIC is not set
-CONFIG_NET_VENDOR_QUALCOMM=y
-CONFIG_QCA7000=m
-CONFIG_QCA7000_SPI=m
-CONFIG_QCA7000_UART=m
-CONFIG_QCOM_EMAC=m
-CONFIG_RMNET=m
-# CONFIG_NET_VENDOR_RDC is not set
-# CONFIG_NET_VENDOR_REALTEK is not set
-CONFIG_NET_VENDOR_RENESAS=y
-CONFIG_SH_ETH=m
-CONFIG_RAVB=y
-CONFIG_NET_VENDOR_ROCKER=y
-# CONFIG_ROCKER is not set
-CONFIG_NET_VENDOR_SAMSUNG=y
-# CONFIG_SXGBE_ETH is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_NET_VENDOR_SOLARFLARE=y
-# CONFIG_SFC is not set
-# CONFIG_SFC_FALCON is not set
-# CONFIG_NET_VENDOR_SILAN is not set
-# CONFIG_NET_VENDOR_SIS is not set
-CONFIG_NET_VENDOR_SMSC=y
-CONFIG_SMC91X=y
-CONFIG_EPIC100=m
-CONFIG_SMSC911X=y
-CONFIG_SMSC9420=m
-CONFIG_NET_VENDOR_SOCIONEXT=y
-CONFIG_SNI_AVE=y
-CONFIG_SNI_NETSEC=y
-CONFIG_NET_VENDOR_STMICRO=y
-CONFIG_STMMAC_ETH=m
-# CONFIG_STMMAC_SELFTESTS is not set
-CONFIG_STMMAC_PLATFORM=m
-CONFIG_DWMAC_DWC_QOS_ETH=m
-CONFIG_DWMAC_GENERIC=m
-CONFIG_DWMAC_IPQ806X=m
-CONFIG_DWMAC_MEDIATEK=m
-CONFIG_DWMAC_MESON=m
-CONFIG_DWMAC_QCOM_ETHQOS=m
-CONFIG_DWMAC_ROCKCHIP=y
-CONFIG_DWMAC_SOCFPGA=m
-CONFIG_DWMAC_SUNXI=m
-CONFIG_DWMAC_SUN8I=m
-CONFIG_DWMAC_IMX8=m
-# CONFIG_DWMAC_INTEL_PLAT is not set
-CONFIG_DWMAC_VISCONTI=m
-CONFIG_DWMAC_LOONGSON=m
-CONFIG_STMMAC_PCI=m
-CONFIG_NET_VENDOR_SUN=y
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NIU is not set
-CONFIG_NET_VENDOR_SYNOPSYS=y
-# CONFIG_DWC_XLGMAC is not set
-# CONFIG_NET_VENDOR_TEHUTI is not set
-CONFIG_NET_VENDOR_TI=y
-# CONFIG_TI_DAVINCI_MDIO is not set
-# CONFIG_TI_CPSW_PHY_SEL is not set
-# CONFIG_TI_K3_AM65_CPTS is not set
-# CONFIG_TLAN is not set
-# CONFIG_NET_VENDOR_VIA is not set
-CONFIG_NET_VENDOR_WIZNET=y
-# CONFIG_WIZNET_W5100 is not set
-# CONFIG_WIZNET_W5300 is not set
-CONFIG_NET_VENDOR_XILINX=y
-CONFIG_XILINX_EMACLITE=m
-CONFIG_XILINX_AXI_EMAC=m
-# CONFIG_XILINX_LL_TEMAC is not set
-CONFIG_FDDI=y
-CONFIG_DEFXX=m
-CONFIG_SKFP=m
-CONFIG_HIPPI=y
-# CONFIG_ROADRUNNER is not set
-# CONFIG_NET_SB1000 is not set
-CONFIG_PHYLINK=y
-CONFIG_PHYLIB=y
-CONFIG_SWPHY=y
-# CONFIG_LED_TRIGGER_PHY is not set
-CONFIG_FIXED_PHY=y
-CONFIG_SFP=m
-
-#
-# MII PHY device drivers
-#
-# CONFIG_AMD_PHY is not set
-CONFIG_MESON_GXL_PHY=m
-# CONFIG_ADIN_PHY is not set
-CONFIG_AQUANTIA_PHY=m
-CONFIG_AX88796B_PHY=m
-CONFIG_BROADCOM_PHY=y
-# CONFIG_BCM54140_PHY is not set
-CONFIG_BCM7XXX_PHY=y
-CONFIG_BCM84881_PHY=y
-# CONFIG_BCM87XX_PHY is not set
-CONFIG_BCM_NET_PHYLIB=y
-# CONFIG_CICADA_PHY is not set
-CONFIG_CORTINA_PHY=m
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_LXT_PHY is not set
-CONFIG_INTEL_XWAY_PHY=m
-# CONFIG_LSI_ET1011C_PHY is not set
-CONFIG_MARVELL_PHY=m
-CONFIG_MARVELL_10G_PHY=m
-CONFIG_MARVELL_88X2222_PHY=m
-CONFIG_MAXLINEAR_GPHY=m
-CONFIG_MEDIATEK_GE_PHY=m
-CONFIG_MICREL_PHY=y
-CONFIG_MICROCHIP_PHY=m
-CONFIG_MICROCHIP_T1_PHY=m
-# CONFIG_MICROSEMI_PHY is not set
-CONFIG_MOTORCOMM_PHY=m
-# CONFIG_NATIONAL_PHY is not set
-CONFIG_NXP_C45_TJA11XX_PHY=m
-# CONFIG_NXP_TJA11XX_PHY is not set
-CONFIG_AT803X_PHY=m
-# CONFIG_QSEMI_PHY is not set
-CONFIG_REALTEK_PHY=m
-# CONFIG_RENESAS_PHY is not set
-CONFIG_ROCKCHIP_PHY=y
-CONFIG_SMSC_PHY=m
-# CONFIG_STE10XP is not set
-CONFIG_TERANETICS_PHY=m
-# CONFIG_DP83822_PHY is not set
-# CONFIG_DP83TC811_PHY is not set
-CONFIG_DP83848_PHY=m
-# CONFIG_DP83867_PHY is not set
-CONFIG_DP83869_PHY=m
-CONFIG_VITESSE_PHY=m
-# CONFIG_XILINX_GMII2RGMII is not set
-# CONFIG_MICREL_KS8995MA is not set
-
-#
-# MCTP Device Drivers
-#
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_BUS=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_OF_MDIO=y
-CONFIG_ACPI_MDIO=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_SUN4I=m
-CONFIG_MDIO_XGENE=y
-CONFIG_MDIO_BITBANG=y
-# CONFIG_MDIO_BCM_IPROC is not set
-CONFIG_MDIO_BCM_UNIMAC=y
-CONFIG_MDIO_CAVIUM=y
-CONFIG_MDIO_GPIO=m
-CONFIG_MDIO_HISI_FEMAC=m
-CONFIG_MDIO_I2C=m
-# CONFIG_MDIO_MVUSB is not set
-CONFIG_MDIO_MSCC_MIIM=m
-# CONFIG_MDIO_OCTEON is not set
-# CONFIG_MDIO_IPQ4019 is not set
-# CONFIG_MDIO_IPQ8064 is not set
-CONFIG_MDIO_THUNDER=y
-
-#
-# MDIO Multiplexers
-#
-CONFIG_MDIO_BUS_MUX=y
-CONFIG_MDIO_BUS_MUX_MESON_G12A=m
-CONFIG_MDIO_BUS_MUX_BCM_IPROC=m
-# CONFIG_MDIO_BUS_MUX_GPIO is not set
-# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
-CONFIG_MDIO_BUS_MUX_MMIOREG=y
-
-#
-# PCS device drivers
-#
-CONFIG_PCS_XPCS=m
-CONFIG_PCS_LYNX=m
-# end of PCS device drivers
-
-CONFIG_PLIP=m
-CONFIG_PPP=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_MPPE=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPPOATM=m
-CONFIG_PPPOE=m
-CONFIG_PPTP=m
-CONFIG_PPPOL2TP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_SLIP=m
-CONFIG_SLHC=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_RTL8152=m
-CONFIG_USB_LAN78XX=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_AX8817X=m
-CONFIG_USB_NET_AX88179_178A=m
-CONFIG_USB_NET_CDCETHER=m
-CONFIG_USB_NET_CDC_EEM=m
-CONFIG_USB_NET_CDC_NCM=m
-CONFIG_USB_NET_HUAWEI_CDC_NCM=m
-CONFIG_USB_NET_CDC_MBIM=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_SR9700=m
-CONFIG_USB_NET_SR9800=m
-CONFIG_USB_NET_SMSC75XX=m
-CONFIG_USB_NET_SMSC95XX=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_NET1080=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_MCS7830=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
-CONFIG_USB_NET_CDC_SUBSET=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_BELKIN=y
-CONFIG_USB_ARMLINUX=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-CONFIG_USB_NET_ZAURUS=m
-CONFIG_USB_NET_CX82310_ETH=m
-CONFIG_USB_NET_KALMIA=m
-CONFIG_USB_NET_QMI_WWAN=m
-CONFIG_USB_HSO=m
-CONFIG_USB_NET_INT51X1=m
-CONFIG_USB_CDC_PHONET=m
-CONFIG_USB_IPHETH=m
-CONFIG_USB_SIERRA_NET=m
-CONFIG_USB_VL600=m
-CONFIG_USB_NET_CH9200=m
-CONFIG_USB_NET_AQC111=m
-CONFIG_USB_RTL8153_ECM=m
-CONFIG_WLAN=y
-CONFIG_WLAN_VENDOR_ADMTEK=y
-CONFIG_ADM8211=m
-CONFIG_ATH_COMMON=m
-CONFIG_WLAN_VENDOR_ATH=y
-# CONFIG_ATH_DEBUG is not set
-CONFIG_ATH5K=m
-# CONFIG_ATH5K_DEBUG is not set
-CONFIG_ATH5K_PCI=y
-CONFIG_ATH9K_HW=m
-CONFIG_ATH9K_COMMON=m
-CONFIG_ATH9K_BTCOEX_SUPPORT=y
-CONFIG_ATH9K=m
-CONFIG_ATH9K_PCI=y
-CONFIG_ATH9K_AHB=y
-CONFIG_ATH9K_DYNACK=y
-CONFIG_ATH9K_WOW=y
-CONFIG_ATH9K_RFKILL=y
-CONFIG_ATH9K_CHANNEL_CONTEXT=y
-CONFIG_ATH9K_PCOEM=y
-CONFIG_ATH9K_PCI_NO_EEPROM=m
-CONFIG_ATH9K_HTC=m
-CONFIG_ATH9K_HWRNG=y
-CONFIG_CARL9170=m
-CONFIG_CARL9170_LEDS=y
-CONFIG_CARL9170_WPC=y
-CONFIG_CARL9170_HWRNG=y
-CONFIG_ATH6KL=m
-CONFIG_ATH6KL_SDIO=m
-CONFIG_ATH6KL_USB=m
-# CONFIG_ATH6KL_DEBUG is not set
-CONFIG_AR5523=m
-CONFIG_WIL6210=m
-CONFIG_WIL6210_ISR_COR=y
-CONFIG_ATH10K=m
-CONFIG_ATH10K_CE=y
-CONFIG_ATH10K_PCI=m
-# CONFIG_ATH10K_AHB is not set
-CONFIG_ATH10K_SDIO=m
-CONFIG_ATH10K_USB=m
-CONFIG_ATH10K_SNOC=m
-# CONFIG_ATH10K_DEBUG is not set
-CONFIG_WCN36XX=m
-# CONFIG_WCN36XX_DEBUGFS is not set
-CONFIG_ATH11K=m
-CONFIG_ATH11K_PCI=m
-# CONFIG_ATH11K_DEBUG is not set
-CONFIG_WLAN_VENDOR_ATMEL=y
-CONFIG_ATMEL=m
-CONFIG_PCI_ATMEL=m
-CONFIG_AT76C50X_USB=m
-CONFIG_WLAN_VENDOR_BROADCOM=y
-CONFIG_B43=m
-CONFIG_B43_BCMA=y
-CONFIG_B43_SSB=y
-CONFIG_B43_BUSES_BCMA_AND_SSB=y
-# CONFIG_B43_BUSES_BCMA is not set
-# CONFIG_B43_BUSES_SSB is not set
-CONFIG_B43_PCI_AUTOSELECT=y
-CONFIG_B43_PCICORE_AUTOSELECT=y
-CONFIG_B43_SDIO=y
-CONFIG_B43_BCMA_PIO=y
-CONFIG_B43_PIO=y
-CONFIG_B43_PHY_G=y
-CONFIG_B43_PHY_N=y
-CONFIG_B43_PHY_LP=y
-CONFIG_B43_PHY_HT=y
-CONFIG_B43_LEDS=y
-CONFIG_B43_HWRNG=y
-# CONFIG_B43_DEBUG is not set
-# CONFIG_B43LEGACY is not set
-CONFIG_BRCMUTIL=m
-CONFIG_BRCMSMAC=m
-CONFIG_BRCMSMAC_LEDS=y
-CONFIG_BRCMFMAC=m
-CONFIG_BRCMFMAC_PROTO_BCDC=y
-CONFIG_BRCMFMAC_PROTO_MSGBUF=y
-CONFIG_BRCMFMAC_SDIO=y
-CONFIG_BRCMFMAC_USB=y
-CONFIG_BRCMFMAC_PCIE=y
-# CONFIG_BRCM_TRACING is not set
-# CONFIG_BRCMDBG is not set
-CONFIG_WLAN_VENDOR_CISCO=y
-CONFIG_WLAN_VENDOR_INTEL=y
-CONFIG_IPW2100=m
-CONFIG_IPW2100_MONITOR=y
-# CONFIG_IPW2100_DEBUG is not set
-CONFIG_IPW2200=m
-CONFIG_IPW2200_MONITOR=y
-CONFIG_IPW2200_RADIOTAP=y
-CONFIG_IPW2200_PROMISCUOUS=y
-CONFIG_IPW2200_QOS=y
-# CONFIG_IPW2200_DEBUG is not set
-CONFIG_LIBIPW=m
-# CONFIG_LIBIPW_DEBUG is not set
-CONFIG_IWLEGACY=m
-CONFIG_IWL4965=m
-CONFIG_IWL3945=m
-
-#
-# iwl3945 / iwl4965 Debugging Options
-#
-# CONFIG_IWLEGACY_DEBUG is not set
-# end of iwl3945 / iwl4965 Debugging Options
-
-CONFIG_IWLWIFI=m
-CONFIG_IWLWIFI_LEDS=y
-CONFIG_IWLDVM=m
-CONFIG_IWLMVM=m
-CONFIG_IWLWIFI_OPMODE_MODULAR=y
-# CONFIG_IWLWIFI_BCAST_FILTERING is not set
-CONFIG_IWLMEI=m
-
-#
-# Debugging Options
-#
-# CONFIG_IWLWIFI_DEBUG is not set
-# end of Debugging Options
-
-CONFIG_WLAN_VENDOR_INTERSIL=y
-CONFIG_HOSTAP=m
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_HOSTAP_PLX=m
-# CONFIG_HOSTAP_PCI is not set
-CONFIG_HERMES=m
-CONFIG_HERMES_PRISM=y
-CONFIG_HERMES_CACHE_FW_ON_INIT=y
-CONFIG_PLX_HERMES=m
-CONFIG_TMD_HERMES=m
-CONFIG_NORTEL_HERMES=m
-# CONFIG_PCI_HERMES is not set
-CONFIG_ORINOCO_USB=m
-CONFIG_P54_COMMON=m
-CONFIG_P54_USB=m
-# CONFIG_P54_PCI is not set
-# CONFIG_P54_SPI is not set
-CONFIG_P54_LEDS=y
-CONFIG_WLAN_VENDOR_MARVELL=y
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_USB=m
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_LIBERTAS_SPI=m
-# CONFIG_LIBERTAS_DEBUG is not set
-CONFIG_LIBERTAS_MESH=y
-# CONFIG_LIBERTAS_THINFIRM is not set
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
-CONFIG_MWIFIEX_PCIE=m
-CONFIG_MWIFIEX_USB=m
-CONFIG_MWL8K=m
-CONFIG_WLAN_VENDOR_MEDIATEK=y
-CONFIG_MT7601U=m
-CONFIG_MT76_CORE=m
-CONFIG_MT76_LEDS=y
-CONFIG_MT76_USB=m
-CONFIG_MT76_SDIO=m
-CONFIG_MT76x02_LIB=m
-CONFIG_MT76x02_USB=m
-CONFIG_MT76_CONNAC_LIB=m
-CONFIG_MT76x0_COMMON=m
-CONFIG_MT76x0U=m
-CONFIG_MT76x0E=m
-CONFIG_MT76x2_COMMON=m
-CONFIG_MT76x2E=m
-CONFIG_MT76x2U=m
-CONFIG_MT7603E=m
-CONFIG_MT7615_COMMON=m
-CONFIG_MT7615E=m
-CONFIG_MT7622_WMAC=y
-CONFIG_MT7663_USB_SDIO_COMMON=m
-CONFIG_MT7663U=m
-CONFIG_MT7663S=m
-CONFIG_MT7915E=m
-CONFIG_MT7986_WMAC=y
-CONFIG_MT7921_COMMON=m
-CONFIG_MT7921E=m
-CONFIG_MT7921S=m
-CONFIG_MT7921U=m
-CONFIG_WLAN_VENDOR_MICROCHIP=y
-# CONFIG_WILC1000_SDIO is not set
-# CONFIG_WILC1000_SPI is not set
-CONFIG_WLAN_VENDOR_RALINK=y
-CONFIG_RT2X00=m
-# CONFIG_RT2400PCI is not set
-# CONFIG_RT2500PCI is not set
-# CONFIG_RT61PCI is not set
-CONFIG_RT2800PCI=m
-CONFIG_RT2800PCI_RT33XX=y
-CONFIG_RT2800PCI_RT35XX=y
-CONFIG_RT2800PCI_RT53XX=y
-CONFIG_RT2800PCI_RT3290=y
-CONFIG_RT2500USB=m
-CONFIG_RT73USB=m
-CONFIG_RT2800USB=m
-CONFIG_RT2800USB_RT33XX=y
-CONFIG_RT2800USB_RT35XX=y
-CONFIG_RT2800USB_RT3573=y
-CONFIG_RT2800USB_RT53XX=y
-CONFIG_RT2800USB_RT55XX=y
-CONFIG_RT2800USB_UNKNOWN=y
-CONFIG_RT2800_LIB=m
-CONFIG_RT2800_LIB_MMIO=m
-CONFIG_RT2X00_LIB_MMIO=m
-CONFIG_RT2X00_LIB_PCI=m
-CONFIG_RT2X00_LIB_USB=m
-CONFIG_RT2X00_LIB=m
-CONFIG_RT2X00_LIB_FIRMWARE=y
-CONFIG_RT2X00_LIB_CRYPTO=y
-CONFIG_RT2X00_LIB_LEDS=y
-# CONFIG_RT2X00_DEBUG is not set
-CONFIG_WLAN_VENDOR_REALTEK=y
-CONFIG_RTL8180=m
-CONFIG_RTL8187=m
-CONFIG_RTL8187_LEDS=y
-CONFIG_RTL_CARDS=m
-CONFIG_RTL8192CE=m
-CONFIG_RTL8192SE=m
-CONFIG_RTL8192DE=m
-CONFIG_RTL8723AE=m
-CONFIG_RTL8723BE=m
-CONFIG_RTL8188EE=m
-CONFIG_RTL8192EE=m
-CONFIG_RTL8821AE=m
-CONFIG_RTL8192CU=m
-CONFIG_RTLWIFI=m
-CONFIG_RTLWIFI_PCI=m
-CONFIG_RTLWIFI_USB=m
-# CONFIG_RTLWIFI_DEBUG is not set
-CONFIG_RTL8192C_COMMON=m
-CONFIG_RTL8723_COMMON=m
-CONFIG_RTLBTCOEXIST=m
-CONFIG_RTL8XXXU=m
-# CONFIG_RTL8XXXU_UNTESTED is not set
-CONFIG_RTW88=m
-CONFIG_RTW88_CORE=m
-CONFIG_RTW88_PCI=m
-CONFIG_RTW88_8822B=m
-CONFIG_RTW88_8822C=m
-CONFIG_RTW88_8822BE=m
-CONFIG_RTW88_8822CE=m
-# CONFIG_RTW88_8723DE is not set
-# CONFIG_RTW88_8821CE is not set
-CONFIG_RTW88_DEBUG=y
-CONFIG_RTW88_DEBUGFS=y
-CONFIG_RTW89=m
-CONFIG_RTW89_CORE=m
-CONFIG_RTW89_PCI=m
-CONFIG_RTW89_8852AE=m
-CONFIG_RTW89_DEBUG=y
-# CONFIG_RTW89_DEBUGMSG is not set
-CONFIG_RTW89_DEBUGFS=y
-CONFIG_WLAN_VENDOR_RSI=y
-# CONFIG_RSI_91X is not set
-CONFIG_WLAN_VENDOR_ST=y
-CONFIG_CW1200=m
-CONFIG_CW1200_WLAN_SDIO=m
-# CONFIG_CW1200_WLAN_SPI is not set
-CONFIG_WLAN_VENDOR_TI=y
-CONFIG_WL1251=m
-CONFIG_WL1251_SPI=m
-CONFIG_WL1251_SDIO=m
-CONFIG_WL12XX=m
-CONFIG_WL18XX=m
-CONFIG_WLCORE=m
-CONFIG_WLCORE_SPI=m
-CONFIG_WLCORE_SDIO=m
-CONFIG_WILINK_PLATFORM_DATA=y
-CONFIG_WLAN_VENDOR_ZYDAS=y
-CONFIG_USB_ZD1201=m
-CONFIG_ZD1211RW=m
-# CONFIG_ZD1211RW_DEBUG is not set
-CONFIG_WLAN_VENDOR_QUANTENNA=y
-CONFIG_QTNFMAC=m
-CONFIG_QTNFMAC_PCIE=m
-CONFIG_MAC80211_HWSIM=m
-CONFIG_USB_NET_RNDIS_WLAN=m
-# CONFIG_VIRT_WIFI is not set
-CONFIG_WAN=y
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_PCI200SYN=m
-CONFIG_WANXL=m
-CONFIG_PC300TOO=m
-CONFIG_FARSYNC=m
-CONFIG_FSL_UCC_HDLC=m
-CONFIG_SLIC_DS26522=m
-CONFIG_LAPBETHER=m
-CONFIG_IEEE802154_DRIVERS=m
-CONFIG_IEEE802154_FAKELB=m
-# CONFIG_IEEE802154_AT86RF230 is not set
-# CONFIG_IEEE802154_MRF24J40 is not set
-# CONFIG_IEEE802154_CC2520 is not set
-# CONFIG_IEEE802154_ATUSB is not set
-# CONFIG_IEEE802154_ADF7242 is not set
-# CONFIG_IEEE802154_CA8210 is not set
-# CONFIG_IEEE802154_MCR20A is not set
-# CONFIG_IEEE802154_HWSIM is not set
-
-#
-# Wireless WAN
-#
-CONFIG_WWAN=y
-CONFIG_WWAN_HWSIM=m
-CONFIG_MHI_WWAN_CTRL=m
-CONFIG_IOSM=m
-CONFIG_MHI_WWAN_MBIM=m
-CONFIG_QCOM_BAM_DMUX=m
-CONFIG_RPMSG_WWAN_CTRL=m
-# end of Wireless WAN
-
-CONFIG_VMXNET3=m
-CONFIG_FUJITSU_ES=m
-# CONFIG_USB4_NET is not set
-CONFIG_HYPERV_NET=m
-CONFIG_NET_FAILOVER=y
-CONFIG_ISDN=y
-CONFIG_ISDN_CAPI=y
-CONFIG_CAPI_TRACE=y
-CONFIG_ISDN_CAPI_MIDDLEWARE=y
-CONFIG_MISDN=m
-CONFIG_MISDN_DSP=m
-CONFIG_MISDN_L1OIP=m
-
-#
-# mISDN hardware drivers
-#
-CONFIG_MISDN_HFCPCI=m
-CONFIG_MISDN_HFCMULTI=m
-CONFIG_MISDN_HFCUSB=m
-CONFIG_MISDN_AVMFRITZ=m
-CONFIG_MISDN_SPEEDFAX=m
-# CONFIG_MISDN_INFINEON is not set
-# CONFIG_MISDN_W6692 is not set
-# CONFIG_MISDN_NETJET is not set
-CONFIG_MISDN_IPAC=m
-CONFIG_MISDN_ISAR=m
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_LEDS=m
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_SPARSEKMAP is not set
-CONFIG_INPUT_MATRIXKMAP=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ADC=m
-# CONFIG_KEYBOARD_ADP5588 is not set
-# CONFIG_KEYBOARD_ADP5589 is not set
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_QT1050 is not set
-# CONFIG_KEYBOARD_QT1070 is not set
-# CONFIG_KEYBOARD_QT2160 is not set
-CONFIG_KEYBOARD_DLINK_DIR685=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_GPIO_POLLED=m
-# CONFIG_KEYBOARD_TCA6416 is not set
-# CONFIG_KEYBOARD_TCA8418 is not set
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_KEYBOARD_LM8323 is not set
-# CONFIG_KEYBOARD_LM8333 is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_MCS is not set
-# CONFIG_KEYBOARD_MPR121 is not set
-# CONFIG_KEYBOARD_SNVS_PWRKEY is not set
-CONFIG_KEYBOARD_IMX=m
-CONFIG_KEYBOARD_IMX_SC_KEY=m
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_TEGRA=m
-# CONFIG_KEYBOARD_OPENCORES is not set
-CONFIG_KEYBOARD_PINEPHONE=m
-# CONFIG_KEYBOARD_SAMSUNG is not set
-CONFIG_KEYBOARD_STOWAWAY=m
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_SUN4I_LRADC=m
-# CONFIG_KEYBOARD_OMAP4 is not set
-# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_KEYBOARD_CROS_EC=y
-CONFIG_KEYBOARD_CAP11XX=m
-CONFIG_KEYBOARD_BCM=m
-CONFIG_KEYBOARD_MT6779=m
-CONFIG_KEYBOARD_CYPRESS_SF=m
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADC=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=m
-CONFIG_JOYSTICK_IFORCE_232=m
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_TWIDJOY=m
-CONFIG_JOYSTICK_ZHENHUA=m
-CONFIG_JOYSTICK_DB9=m
-CONFIG_JOYSTICK_GAMECON=m
-CONFIG_JOYSTICK_TURBOGRAFX=m
-CONFIG_JOYSTICK_AS5011=m
-CONFIG_JOYSTICK_JOYDUMP=m
-CONFIG_JOYSTICK_XPAD=m
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_JOYSTICK_WALKERA0701=m
-# CONFIG_JOYSTICK_PSXPAD_SPI is not set
-CONFIG_JOYSTICK_PXRC=m
-CONFIG_JOYSTICK_QWIIC=m
-# CONFIG_JOYSTICK_FSIA6B is not set
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=m
-CONFIG_TABLET_USB_AIPTEK=m
-# CONFIG_TABLET_USB_HANWANG is not set
-CONFIG_TABLET_USB_KBTAB=m
-CONFIG_TABLET_USB_PEGASUS=m
-# CONFIG_TABLET_SERIAL_WACOM4 is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
-# CONFIG_TOUCHSCREEN_AD7877 is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-CONFIG_TOUCHSCREEN_ADC=m
-# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
-# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
-# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
-# CONFIG_TOUCHSCREEN_BU21013 is not set
-# CONFIG_TOUCHSCREEN_BU21029 is not set
-# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
-# CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set
-# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
-# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
-# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
-# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
-# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-# CONFIG_TOUCHSCREEN_EGALAX is not set
-# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
-# CONFIG_TOUCHSCREEN_EXC3000 is not set
-CONFIG_TOUCHSCREEN_FUJITSU=m
-# CONFIG_TOUCHSCREEN_GOODIX is not set
-# CONFIG_TOUCHSCREEN_HIDEEP is not set
-CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
-# CONFIG_TOUCHSCREEN_ILI210X is not set
-CONFIG_TOUCHSCREEN_ILITEK=m
-CONFIG_TOUCHSCREEN_IPROC=m
-# CONFIG_TOUCHSCREEN_S6SY761 is not set
-CONFIG_TOUCHSCREEN_GUNZE=m
-# CONFIG_TOUCHSCREEN_EKTF2127 is not set
-CONFIG_TOUCHSCREEN_ELAN=m
-CONFIG_TOUCHSCREEN_ELO=m
-CONFIG_TOUCHSCREEN_WACOM_W8001=m
-CONFIG_TOUCHSCREEN_WACOM_I2C=m
-CONFIG_TOUCHSCREEN_MAX11801=m
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MMS114 is not set
-# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
-CONFIG_TOUCHSCREEN_MSG2638=m
-CONFIG_TOUCHSCREEN_MTOUCH=m
-CONFIG_TOUCHSCREEN_IMAGIS=m
-CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
-CONFIG_TOUCHSCREEN_INEXIO=m
-CONFIG_TOUCHSCREEN_MK712=m
-CONFIG_TOUCHSCREEN_PENMOUNT=m
-# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
-CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m
-CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
-CONFIG_TOUCHSCREEN_TOUCHWIN=m
-CONFIG_TOUCHSCREEN_PIXCIR=m
-# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
-# CONFIG_TOUCHSCREEN_WM97XX is not set
-CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-CONFIG_TOUCHSCREEN_MC13783=m
-CONFIG_TOUCHSCREEN_USB_EGALAX=y
-CONFIG_TOUCHSCREEN_USB_PANJIT=y
-CONFIG_TOUCHSCREEN_USB_3M=y
-CONFIG_TOUCHSCREEN_USB_ITM=y
-CONFIG_TOUCHSCREEN_USB_ETURBO=y
-CONFIG_TOUCHSCREEN_USB_GUNZE=y
-CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
-CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
-CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
-CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
-CONFIG_TOUCHSCREEN_USB_GOTOP=y
-CONFIG_TOUCHSCREEN_USB_JASTEC=y
-CONFIG_TOUCHSCREEN_USB_ELO=y
-CONFIG_TOUCHSCREEN_USB_E2I=y
-CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
-CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
-CONFIG_TOUCHSCREEN_USB_NEXIO=y
-CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
-CONFIG_TOUCHSCREEN_TOUCHIT213=m
-CONFIG_TOUCHSCREEN_TSC_SERIO=m
-# CONFIG_TOUCHSCREEN_TSC2004 is not set
-# CONFIG_TOUCHSCREEN_TSC2005 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-CONFIG_TOUCHSCREEN_RM_TS=m
-# CONFIG_TOUCHSCREEN_SILEAD is not set
-# CONFIG_TOUCHSCREEN_SIS_I2C is not set
-CONFIG_TOUCHSCREEN_ST1232=m
-CONFIG_TOUCHSCREEN_STMFTS=m
-CONFIG_TOUCHSCREEN_SUN4I=m
-CONFIG_TOUCHSCREEN_SUR40=m
-CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
-# CONFIG_TOUCHSCREEN_SX8654 is not set
-# CONFIG_TOUCHSCREEN_TPS6507X is not set
-# CONFIG_TOUCHSCREEN_ZET6223 is not set
-CONFIG_TOUCHSCREEN_ZFORCE=m
-CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
-CONFIG_TOUCHSCREEN_ROHM_BU21023=m
-# CONFIG_TOUCHSCREEN_IQS5XX is not set
-CONFIG_TOUCHSCREEN_ZINITIX=m
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_AD714X is not set
-CONFIG_INPUT_ATC260X_ONKEY=m
-# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
-# CONFIG_INPUT_BMA150 is not set
-# CONFIG_INPUT_E3X0_BUTTON is not set
-CONFIG_INPUT_PM8941_PWRKEY=y
-CONFIG_INPUT_PM8XXX_VIBRATOR=m
-# CONFIG_INPUT_MC13783_PWRBUTTON is not set
-CONFIG_INPUT_MMA8450=m
-# CONFIG_INPUT_GPIO_BEEPER is not set
-# CONFIG_INPUT_GPIO_DECODER is not set
-# CONFIG_INPUT_GPIO_VIBRA is not set
-CONFIG_INPUT_ATI_REMOTE2=m
-CONFIG_INPUT_KEYSPAN_REMOTE=m
-# CONFIG_INPUT_KXTJ9 is not set
-CONFIG_INPUT_POWERMATE=m
-CONFIG_INPUT_YEALINK=m
-CONFIG_INPUT_CM109=m
-# CONFIG_INPUT_REGULATOR_HAPTIC is not set
-CONFIG_INPUT_AXP20X_PEK=m
-CONFIG_INPUT_UINPUT=m
-# CONFIG_INPUT_PCF8574 is not set
-# CONFIG_INPUT_PWM_BEEPER is not set
-# CONFIG_INPUT_PWM_VIBRA is not set
-CONFIG_INPUT_RK805_PWRKEY=y
-# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-CONFIG_INPUT_DA7280_HAPTICS=m
-# CONFIG_INPUT_ADXL34X is not set
-CONFIG_INPUT_IBM_PANEL=m
-CONFIG_INPUT_IMS_PCU=m
-# CONFIG_INPUT_IQS269A is not set
-CONFIG_INPUT_IQS626A=m
-CONFIG_INPUT_CMA3000=m
-# CONFIG_INPUT_CMA3000_I2C is not set
-# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
-# CONFIG_INPUT_DRV260X_HAPTICS is not set
-# CONFIG_INPUT_DRV2665_HAPTICS is not set
-# CONFIG_INPUT_DRV2667_HAPTICS is not set
-CONFIG_INPUT_HISI_POWERKEY=m
-CONFIG_INPUT_RT5120_PWRKEY=m
-# CONFIG_RMI4_CORE is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=m
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_PARKBD=m
-CONFIG_SERIO_AMBAKMI=y
-CONFIG_SERIO_PCIPS2=m
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_RAW=m
-# CONFIG_SERIO_ALTERA_PS2 is not set
-# CONFIG_SERIO_PS2MULT is not set
-# CONFIG_SERIO_ARC_PS2 is not set
-CONFIG_SERIO_APBPS2=m
-CONFIG_HYPERV_KEYBOARD=m
-CONFIG_SERIO_SUN4I_PS2=m
-# CONFIG_SERIO_GPIO_PS2 is not set
-CONFIG_USERIO=m
-CONFIG_GAMEPORT=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_GAMEPORT_EMU10K1=m
-CONFIG_GAMEPORT_FM801=m
-# end of Hardware I/O ports
-# end of Input device support
-
-#
-# Character devices
-#
-CONFIG_TTY=y
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=16
-CONFIG_LDISC_AUTOLOAD=y
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_EARLYCON=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_PNP=y
-# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
-# CONFIG_SERIAL_8250_FINTEK is not set
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_DMA=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_ASPEED_VUART=m
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_BCM2835AUX=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_EM=m
-CONFIG_SERIAL_8250_RT288X=y
-# CONFIG_SERIAL_8250_OMAP is not set
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_UNIPHIER=y
-CONFIG_SERIAL_8250_TEGRA=y
-CONFIG_SERIAL_8250_BCM7271=m
-CONFIG_SERIAL_OF_PLATFORM=y
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_AMBA_PL010=y
-CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
-CONFIG_SERIAL_MESON=y
-CONFIG_SERIAL_MESON_CONSOLE=y
-CONFIG_SERIAL_SAMSUNG=y
-CONFIG_SERIAL_SAMSUNG_UARTS_4=y
-CONFIG_SERIAL_SAMSUNG_UARTS=4
-CONFIG_SERIAL_SAMSUNG_CONSOLE=y
-CONFIG_SERIAL_TEGRA=y
-# CONFIG_SERIAL_TEGRA_TCU is not set
-# CONFIG_SERIAL_MAX3100 is not set
-# CONFIG_SERIAL_MAX310X is not set
-CONFIG_SERIAL_IMX=m
-CONFIG_SERIAL_IMX_CONSOLE=m
-CONFIG_SERIAL_IMX_EARLYCON=y
-CONFIG_SERIAL_UARTLITE=m
-CONFIG_SERIAL_UARTLITE_NR_UARTS=1
-CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=11
-CONFIG_SERIAL_SH_SCI_CONSOLE=y
-CONFIG_SERIAL_SH_SCI_EARLYCON=y
-CONFIG_SERIAL_SH_SCI_DMA=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_JSM=m
-CONFIG_SERIAL_MSM=y
-CONFIG_SERIAL_MSM_CONSOLE=y
-# CONFIG_SERIAL_QCOM_GENI is not set
-# CONFIG_SERIAL_SIFIVE is not set
-CONFIG_SERIAL_QE=m
-# CONFIG_SERIAL_SCCNXP is not set
-# CONFIG_SERIAL_SC16IS7XX is not set
-CONFIG_SERIAL_BCM63XX=m
-# CONFIG_SERIAL_ALTERA_JTAGUART is not set
-# CONFIG_SERIAL_ALTERA_UART is not set
-CONFIG_SERIAL_XILINX_PS_UART=y
-CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
-# CONFIG_SERIAL_ARC is not set
-# CONFIG_SERIAL_RP2 is not set
-CONFIG_SERIAL_FSL_LPUART=m
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_FSL_LINFLEXUART=m
-# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
-CONFIG_SERIAL_SPRD=m
-CONFIG_SERIAL_MVEBU_UART=y
-CONFIG_SERIAL_MVEBU_CONSOLE=y
-# CONFIG_SERIAL_OWL is not set
-CONFIG_SERIAL_LITEUART=m
-CONFIG_SERIAL_LITEUART_MAX_PORTS=1
-# end of Serial drivers
-
-CONFIG_SERIAL_MCTRL_GPIO=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_N_GSM is not set
-CONFIG_NOZOMI=m
-# CONFIG_NULL_TTY is not set
-CONFIG_HVC_DRIVER=y
-# CONFIG_HVC_DCC is not set
-CONFIG_RPMSG_TTY=m
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-# CONFIG_TTY_PRINTK is not set
-CONFIG_PRINTER=m
-CONFIG_LP_CONSOLE=y
-CONFIG_PPDEV=m
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_IPMI_HANDLER=m
-CONFIG_IPMI_DMI_DECODE=y
-CONFIG_IPMI_PLAT_DATA=y
-CONFIG_IPMI_PANIC_EVENT=y
-CONFIG_IPMI_PANIC_STRING=y
-CONFIG_IPMI_DEVICE_INTERFACE=m
-CONFIG_IPMI_SI=m
-CONFIG_IPMI_SSIF=m
-CONFIG_IPMI_IPMB=m
-CONFIG_IPMI_WATCHDOG=m
-CONFIG_IPMI_POWEROFF=m
-CONFIG_NPCM7XX_KCS_IPMI_BMC=m
-CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m
-CONFIG_IPMI_KCS_BMC_SERIO=m
-CONFIG_IPMB_DEVICE_INTERFACE=m
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=m
-CONFIG_HW_RANDOM_BA431=m
-CONFIG_HW_RANDOM_BCM2835=m
-CONFIG_HW_RANDOM_IPROC_RNG200=m
-# CONFIG_HW_RANDOM_OMAP is not set
-CONFIG_HW_RANDOM_VIRTIO=m
-CONFIG_HW_RANDOM_HISI=m
-CONFIG_HW_RANDOM_XGENE=m
-CONFIG_HW_RANDOM_ROCKCHIP=y
-CONFIG_HW_RANDOM_MESON=m
-CONFIG_HW_RANDOM_CAVIUM=m
-CONFIG_HW_RANDOM_MTK=m
-CONFIG_HW_RANDOM_EXYNOS=m
-CONFIG_HW_RANDOM_OPTEE=m
-CONFIG_HW_RANDOM_NPCM=m
-# CONFIG_HW_RANDOM_CCTRNG is not set
-CONFIG_HW_RANDOM_XIPHERA=m
-CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
-CONFIG_HW_RANDOM_CN10K=m
-CONFIG_APPLICOM=m
-CONFIG_DEVMEM=y
-CONFIG_DEVPORT=y
-CONFIG_TCG_TPM=m
-CONFIG_HW_RANDOM_TPM=y
-CONFIG_TCG_TIS_CORE=m
-# CONFIG_TCG_TIS is not set
-CONFIG_TCG_TIS_SPI=m
-# CONFIG_TCG_TIS_SPI_CR50 is not set
-CONFIG_TCG_TIS_SYNQUACER=m
-CONFIG_TCG_TIS_I2C_CR50=m
-CONFIG_TCG_TIS_I2C_ATMEL=m
-CONFIG_TCG_TIS_I2C_INFINEON=m
-CONFIG_TCG_TIS_I2C_NUVOTON=m
-# CONFIG_TCG_ATMEL is not set
-# CONFIG_TCG_INFINEON is not set
-# CONFIG_TCG_CRB is not set
-CONFIG_TCG_VTPM_PROXY=m
-# CONFIG_TCG_FTPM_TEE is not set
-CONFIG_TCG_TIS_ST33ZP24=m
-CONFIG_TCG_TIS_ST33ZP24_I2C=m
-CONFIG_TCG_TIS_ST33ZP24_SPI=m
-CONFIG_XILLYBUS_CLASS=m
-# CONFIG_XILLYBUS is not set
-CONFIG_XILLYUSB=m
-# CONFIG_RANDOM_TRUST_CPU is not set
-CONFIG_RANDOM_TRUST_BOOTLOADER=y
-# end of Character devices
-
-#
-# I2C support
-#
-CONFIG_I2C=y
-CONFIG_ACPI_I2C_OPREGION=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MUX=y
-
-#
-# Multiplexer I2C Chip support
-#
-# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
-# CONFIG_I2C_MUX_GPIO is not set
-CONFIG_I2C_MUX_GPMUX=m
-# CONFIG_I2C_MUX_LTC4306 is not set
-# CONFIG_I2C_MUX_PCA9541 is not set
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_I2C_MUX_PINCTRL=m
-CONFIG_PINCTRL_AMD=y
-CONFIG_I2C_MUX_REG=m
-CONFIG_I2C_DEMUX_PINCTRL=m
-# CONFIG_I2C_MUX_MLXCPLD is not set
-# end of Multiplexer I2C Chip support
-
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_SMBUS=y
-CONFIG_I2C_ALGOBIT=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# PC SMBus host controller drivers
-#
-# CONFIG_I2C_ALI1535 is not set
-# CONFIG_I2C_ALI1563 is not set
-# CONFIG_I2C_ALI15X3 is not set
-# CONFIG_I2C_AMD756 is not set
-# CONFIG_I2C_AMD8111 is not set
-# CONFIG_I2C_AMD_MP2 is not set
-CONFIG_I2C_HIX5HD2=m
-# CONFIG_I2C_I801 is not set
-# CONFIG_I2C_ISCH is not set
-# CONFIG_I2C_PIIX4 is not set
-# CONFIG_I2C_NFORCE2 is not set
-# CONFIG_I2C_NVIDIA_GPU is not set
-# CONFIG_I2C_SIS5595 is not set
-# CONFIG_I2C_SIS630 is not set
-# CONFIG_I2C_SIS96X is not set
-# CONFIG_I2C_VIA is not set
-# CONFIG_I2C_VIAPRO is not set
-
-#
-# ACPI drivers
-#
-# CONFIG_I2C_SCMI is not set
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-CONFIG_I2C_ALTERA=m
-CONFIG_I2C_BCM2835=m
-CONFIG_I2C_BCM_IPROC=m
-CONFIG_I2C_BRCMSTB=m
-# CONFIG_I2C_CADENCE is not set
-CONFIG_I2C_CBUS_GPIO=m
-CONFIG_I2C_DESIGNWARE_CORE=y
-# CONFIG_I2C_DESIGNWARE_SLAVE is not set
-CONFIG_I2C_DESIGNWARE_PLATFORM=y
-CONFIG_I2C_DESIGNWARE_AMDPSP=y
-# CONFIG_I2C_DESIGNWARE_PCI is not set
-CONFIG_I2C_EMEV2=m
-CONFIG_I2C_EXYNOS5=m
-# CONFIG_I2C_GPIO is not set
-CONFIG_I2C_HISI=m
-CONFIG_I2C_IMX=y
-CONFIG_I2C_IMX_LPI2C=m
-CONFIG_I2C_MESON=y
-CONFIG_I2C_MT65XX=m
-CONFIG_I2C_MV64XXX=y
-CONFIG_I2C_NOMADIK=m
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_OMAP is not set
-# CONFIG_I2C_OWL is not set
-CONFIG_I2C_APPLE=m
-# CONFIG_I2C_PCA_PLATFORM is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_QCOM_CCI is not set
-# CONFIG_I2C_QCOM_GENI is not set
-CONFIG_I2C_QUP=y
-CONFIG_I2C_RIIC=m
-CONFIG_I2C_RK3X=y
-CONFIG_I2C_S3C2410=m
-CONFIG_I2C_SH_MOBILE=y
-# CONFIG_I2C_SIMTEC is not set
-# CONFIG_I2C_SPRD is not set
-# CONFIG_I2C_SYNQUACER is not set
-CONFIG_I2C_TEGRA=y
-CONFIG_I2C_TEGRA_BPMP=m
-CONFIG_I2C_UNIPHIER=m
-CONFIG_I2C_UNIPHIER_F=y
-CONFIG_I2C_VERSATILE=m
-CONFIG_I2C_THUNDERX=m
-# CONFIG_I2C_XILINX is not set
-CONFIG_I2C_XLP9XX=m
-CONFIG_I2C_RCAR=y
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_DIOLAN_U2C is not set
-CONFIG_I2C_CP2615=m
-CONFIG_I2C_PARPORT=m
-CONFIG_I2C_PCI1XXXX=m
-CONFIG_I2C_ROBOTFUZZ_OSIF=m
-CONFIG_I2C_TAOS_EVM=m
-CONFIG_I2C_TINY_USB=m
-
-#
-# Other I2C/SMBus bus drivers
-#
-CONFIG_I2C_CROS_EC_TUNNEL=y
-CONFIG_I2C_XGENE_SLIMPRO=m
-CONFIG_I2C_VIRTIO=m
-# end of I2C Hardware Bus support
-
-# CONFIG_I2C_STUB is not set
-CONFIG_I2C_SLAVE=y
-# CONFIG_I2C_SLAVE_EEPROM is not set
-# CONFIG_I2C_SLAVE_TESTUNIT is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# end of I2C support
-
-CONFIG_I3C=m
-CONFIG_CDNS_I3C_MASTER=m
-CONFIG_DW_I3C_MASTER=m
-CONFIG_SVC_I3C_MASTER=m
-CONFIG_MIPI_I3C_HCI=m
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_ALTERA is not set
-CONFIG_SPI_ARMADA_3700=m
-# CONFIG_SPI_AXI_SPI_ENGINE is not set
-CONFIG_SPI_BCM2835=m
-CONFIG_SPI_BCM2835AUX=m
-CONFIG_SPI_BCM_QSPI=m
-CONFIG_SPI_BITBANG=m
-# CONFIG_SPI_BUTTERFLY is not set
-# CONFIG_SPI_CADENCE is not set
-# CONFIG_SPI_CADENCE_QUADSPI is not set
-CONFIG_SPI_CADENCE_XSPI=m
-# CONFIG_SPI_DESIGNWARE is not set
-CONFIG_SPI_FSL_LPSPI=m
-# CONFIG_SPI_FSL_QUADSPI is not set
-CONFIG_SPI_HISI_KUNPENG=m
-CONFIG_SPI_HISI_SFC_V3XX=m
-# CONFIG_SPI_NXP_FLEXSPI is not set
-# CONFIG_SPI_GPIO is not set
-CONFIG_SPI_IMX=m
-# CONFIG_SPI_LM70_LLP is not set
-# CONFIG_SPI_FSL_SPI is not set
-CONFIG_SPI_FSL_DSPI=m
-CONFIG_SPI_MESON_SPICC=m
-CONFIG_SPI_MESON_SPIFC=m
-CONFIG_SPI_MT65XX=m
-# CONFIG_SPI_MTK_NOR is not set
-# CONFIG_SPI_OC_TINY is not set
-# CONFIG_SPI_OMAP24XX is not set
-CONFIG_SPI_ORION=y
-CONFIG_SPI_PL022=y
-# CONFIG_SPI_PXA2XX is not set
-CONFIG_SPI_ROCKCHIP=y
-# CONFIG_SPI_ROCKCHIP_SFC is not set
-CONFIG_SPI_RPCIF=m
-CONFIG_SPI_RSPI=m
-CONFIG_SPI_QCOM_QSPI=m
-CONFIG_SPI_QUP=y
-# CONFIG_SPI_QCOM_GENI is not set
-CONFIG_SPI_S3C64XX=y
-# CONFIG_SPI_SC18IS602 is not set
-CONFIG_SPI_SH_MSIOF=m
-CONFIG_SPI_SH_HSPI=m
-# CONFIG_SPI_SIFIVE is not set
-CONFIG_SPI_SPRD=m
-CONFIG_SPI_SPRD_ADI=m
-CONFIG_SPI_SUN4I=m
-CONFIG_SPI_SUN6I=m
-# CONFIG_SPI_SYNQUACER is not set
-# CONFIG_SPI_MXIC is not set
-CONFIG_SPI_TEGRA210_QUAD=m
-CONFIG_SPI_TEGRA114=m
-CONFIG_SPI_TEGRA20_SFLASH=m
-CONFIG_SPI_TEGRA20_SLINK=m
-CONFIG_SPI_THUNDERX=m
-CONFIG_SPI_UNIPHIER=m
-# CONFIG_SPI_XCOMM is not set
-# CONFIG_SPI_XILINX is not set
-CONFIG_SPI_XLP=m
-# CONFIG_SPI_ZYNQMP_GQSPI is not set
-# CONFIG_SPI_AMD is not set
-
-#
-# SPI Multiplexer support
-#
-# CONFIG_SPI_MUX is not set
-
-#
-# SPI Protocol Masters
-#
-CONFIG_SPI_SPIDEV=m
-# CONFIG_SPI_LOOPBACK_TEST is not set
-# CONFIG_SPI_TLE62X0 is not set
-# CONFIG_SPI_SLAVE is not set
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPMI=y
-CONFIG_SPMI_HISI3670=m
-CONFIG_SPMI_MSM_PMIC_ARB=y
-CONFIG_HSI=m
-CONFIG_HSI_BOARDINFO=y
-
-#
-# HSI controllers
-#
-
-#
-# HSI clients
-#
-CONFIG_HSI_CHAR=m
-CONFIG_PPS=y
-# CONFIG_PPS_DEBUG is not set
-
-#
-# PPS clients support
-#
-# CONFIG_PPS_CLIENT_KTIMER is not set
-CONFIG_PPS_CLIENT_LDISC=m
-CONFIG_PPS_CLIENT_PARPORT=m
-# CONFIG_PPS_CLIENT_GPIO is not set
-
-#
-# PPS generators support
-#
-
-#
-# PTP clock support
-#
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PTP_1588_CLOCK_DTE=y
-
-#
-# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
-#
-CONFIG_PTP_1588_CLOCK_KVM=m
-# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set
-# CONFIG_PTP_1588_CLOCK_IDTCM is not set
-CONFIG_PTP_1588_CLOCK_OCP=m
-# end of PTP clock support
-
-CONFIG_PINCTRL=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_PINMUX=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_PINCONF=y
-CONFIG_GENERIC_PINCONF=y
-# CONFIG_DEBUG_PINCTRL is not set
-CONFIG_PINCTRL_APPLE_GPIO=m
-CONFIG_PINCTRL_AS3722=m
-CONFIG_PINCTRL_AXP209=m
-CONFIG_PINCTRL_CY8C95X0=m
-CONFIG_PINCTRL_AMD=y
-CONFIG_PINCTRL_BM1880=y
-CONFIG_PINCTRL_MCP23S08_I2C=m
-CONFIG_PINCTRL_MCP23S08_SPI=m
-CONFIG_PINCTRL_MCP23S08=m
-CONFIG_PINCTRL_ROCKCHIP=y
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_PINCTRL_SX150X=y
-# CONFIG_PINCTRL_STMFX is not set
-CONFIG_PINCTRL_MAX77620=m
-CONFIG_PINCTRL_ZYNQMP=m
-CONFIG_PINCTRL_RK805=y
-# CONFIG_PINCTRL_OCELOT is not set
-CONFIG_PINCTRL_MICROCHIP_SGPIO=y
-CONFIG_PINCTRL_KEEMBAY=m
-# CONFIG_PINCTRL_OWL is not set
-CONFIG_PINCTRL_BCM4908=m
-CONFIG_PINCTRL_BCM2835=y
-CONFIG_PINCTRL_BCM4908=m
-CONFIG_PINCTRL_IPROC_GPIO=y
-CONFIG_PINCTRL_NS2_MUX=y
-CONFIG_PINCTRL_BERLIN=y
-# CONFIG_PINCTRL_AS370 is not set
-CONFIG_PINCTRL_BERLIN_BG4CT=y
-CONFIG_PINCTRL_IMX=y
-CONFIG_PINCTRL_IMX_SCU=y
-CONFIG_PINCTRL_IMX8MM=y
-CONFIG_PINCTRL_IMX8MN=y
-CONFIG_PINCTRL_IMX8MP=y
-CONFIG_PINCTRL_IMX8MQ=y
-CONFIG_PINCTRL_IMX8QM=y
-CONFIG_PINCTRL_IMX8QXP=y
-# CONFIG_PINCTRL_IMX8DXL is not set
-CONFIG_PINCTRL_IMX8ULP=m
-CONFIG_PINCTRL_MVEBU=y
-CONFIG_PINCTRL_ARMADA_AP806=y
-CONFIG_PINCTRL_ARMADA_CP110=y
-CONFIG_PINCTRL_ARMADA_37XX=y
-CONFIG_PINCTRL_MSM=y
-CONFIG_PINCTRL_APQ8064=m
-CONFIG_PINCTRL_APQ8084=m
-CONFIG_PINCTRL_IPQ4019=m
-CONFIG_PINCTRL_IPQ8064=m
-CONFIG_PINCTRL_IPQ8074=m
-# CONFIG_PINCTRL_IPQ6018 is not set
-CONFIG_PINCTRL_MSM8226=m
-CONFIG_PINCTRL_MSM8660=m
-CONFIG_PINCTRL_MSM8960=m
-CONFIG_PINCTRL_MDM9607=m
-CONFIG_PINCTRL_MDM9615=m
-CONFIG_PINCTRL_MSM8X74=m
-CONFIG_PINCTRL_MSM8916=m
-CONFIG_PINCTRL_MSM8953=m
-CONFIG_PINCTRL_MSM8976=m
-CONFIG_PINCTRL_MSM8994=m
-CONFIG_PINCTRL_MSM8996=m
-# CONFIG_PINCTRL_MSM8998 is not set
-CONFIG_PINCTRL_QCM2290=m
-# CONFIG_PINCTRL_QCS404 is not set
-CONFIG_PINCTRL_QDF2XXX=m
-CONFIG_PINCTRL_QCOM_SPMI_PMIC=m
-CONFIG_PINCTRL_QCOM_SSBI_PMIC=m
-# CONFIG_PINCTRL_SC7180 is not set
-CONFIG_PINCTRL_SC7280=m
-CONFIG_PINCTRL_SC8180X=m
-CONFIG_PINCTRL_SC8280XP=m
-# CONFIG_PINCTRL_SDM660 is not set
-# CONFIG_PINCTRL_SDM845 is not set
-CONFIG_PINCTRL_SDX55=m
-CONFIG_PINCTRL_SM6115=m
-CONFIG_PINCTRL_SM6125=m
-CONFIG_PINCTRL_SM6350=m
-# CONFIG_PINCTRL_SM8150 is not set
-# CONFIG_PINCTRL_SM8250 is not set
-CONFIG_PINCTRL_SM8350=m
-CONFIG_PINCTRL_LPASS_LPI=m
-
-#
-# Renesas pinctrl drivers
-#
-CONFIG_PINCTRL_RENESAS=y
-CONFIG_PINCTRL_SH_PFC=y
-CONFIG_PINCTRL_PFC_R8A77995=y
-CONFIG_PINCTRL_PFC_R8A77990=y
-CONFIG_PINCTRL_PFC_R8A77950=y
-CONFIG_PINCTRL_PFC_R8A77951=y
-CONFIG_PINCTRL_PFC_R8A77965=y
-CONFIG_PINCTRL_PFC_R8A77960=y
-CONFIG_PINCTRL_PFC_R8A77961=y
-CONFIG_PINCTRL_PFC_R8A77980=y
-CONFIG_PINCTRL_PFC_R8A77970=y
-CONFIG_PINCTRL_PFC_R8A779A0=y
-CONFIG_PINCTRL_RZG2L=y
-CONFIG_PINCTRL_PFC_R8A774C0=y
-CONFIG_PINCTRL_PFC_R8A774E1=y
-CONFIG_PINCTRL_PFC_R8A774A1=y
-CONFIG_PINCTRL_PFC_R8A774B1=y
-# end of Renesas pinctrl drivers
-
-CONFIG_PINCTRL_SAMSUNG=y
-CONFIG_PINCTRL_EXYNOS=y
-CONFIG_PINCTRL_EXYNOS_ARM64=y
-CONFIG_PINCTRL_SPRD=y
-CONFIG_PINCTRL_SPRD_SC9860=y
-CONFIG_PINCTRL_SUNXI=y
-# CONFIG_PINCTRL_SUN4I_A10 is not set
-# CONFIG_PINCTRL_SUN5I is not set
-# CONFIG_PINCTRL_SUN6I_A31 is not set
-# CONFIG_PINCTRL_SUN6I_A31_R is not set
-# CONFIG_PINCTRL_SUN8I_A23 is not set
-# CONFIG_PINCTRL_SUN8I_A33 is not set
-# CONFIG_PINCTRL_SUN8I_A83T is not set
-# CONFIG_PINCTRL_SUN8I_A83T_R is not set
-# CONFIG_PINCTRL_SUN8I_A23_R is not set
-# CONFIG_PINCTRL_SUN8I_H3 is not set
-CONFIG_PINCTRL_SUN8I_H3_R=y
-# CONFIG_PINCTRL_SUN8I_V3S is not set
-# CONFIG_PINCTRL_SUN9I_A80 is not set
-# CONFIG_PINCTRL_SUN9I_A80_R is not set
-CONFIG_PINCTRL_SUN50I_A64=y
-CONFIG_PINCTRL_SUN50I_A64_R=y
-CONFIG_PINCTRL_SUN50I_A100=y
-CONFIG_PINCTRL_SUN50I_A100_R=y
-CONFIG_PINCTRL_SUN50I_H5=y
-CONFIG_PINCTRL_SUN50I_H6=y
-CONFIG_PINCTRL_SUN50I_H6_R=y
-CONFIG_PINCTRL_SUN50I_H616=y
-CONFIG_PINCTRL_SUN50I_H616_R=y
-CONFIG_PINCTRL_TEGRA=y
-CONFIG_PINCTRL_TEGRA124=y
-CONFIG_PINCTRL_TEGRA210=y
-CONFIG_PINCTRL_TEGRA194=y
-CONFIG_PINCTRL_TEGRA_XUSB=y
-CONFIG_PINCTRL_UNIPHIER=y
-# CONFIG_PINCTRL_UNIPHIER_LD4 is not set
-# CONFIG_PINCTRL_UNIPHIER_PRO4 is not set
-# CONFIG_PINCTRL_UNIPHIER_SLD8 is not set
-# CONFIG_PINCTRL_UNIPHIER_PRO5 is not set
-# CONFIG_PINCTRL_UNIPHIER_PXS2 is not set
-# CONFIG_PINCTRL_UNIPHIER_LD6B is not set
-CONFIG_PINCTRL_UNIPHIER_LD11=y
-CONFIG_PINCTRL_UNIPHIER_LD20=y
-CONFIG_PINCTRL_UNIPHIER_PXS3=y
-CONFIG_PINCTRL_UNIPHIER_NX1=y
-
-#
-# MediaTek pinctrl drivers
-#
-CONFIG_EINT_MTK=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_PARIS=y
-CONFIG_PINCTRL_MT2712=y
-CONFIG_PINCTRL_MT6765=y
-CONFIG_PINCTRL_MT6779=m
-CONFIG_PINCTRL_MT6795=y
-CONFIG_PINCTRL_MT6797=y
-CONFIG_PINCTRL_MT7622=y
-CONFIG_PINCTRL_MT7986=y
-CONFIG_PINCTRL_MT8167=y
-CONFIG_PINCTRL_MT8173=y
-CONFIG_PINCTRL_MT8183=y
-CONFIG_PINCTRL_MT8186=y
-CONFIG_PINCTRL_MT8188=y
-CONFIG_PINCTRL_MT8192=y
-CONFIG_PINCTRL_MT8195=y
-CONFIG_PINCTRL_MT8365=y
-CONFIG_PINCTRL_MT8516=y
-# end of MediaTek pinctrl drivers
-
-CONFIG_PINCTRL_MESON=y
-CONFIG_PINCTRL_MESON_GXBB=y
-CONFIG_PINCTRL_MESON_GXL=y
-CONFIG_PINCTRL_MESON8_PMX=y
-CONFIG_PINCTRL_MESON_AXG=y
-CONFIG_PINCTRL_MESON_AXG_PMX=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_PINCTRL_MESON_A1=y
-CONFIG_PINCTRL_MESON_S4=m
-CONFIG_PINCTRL_MADERA=m
-CONFIG_PINCTRL_CS47L35=y
-CONFIG_PINCTRL_CS47L85=y
-CONFIG_PINCTRL_CS47L90=y
-CONFIG_PINCTRL_VISCONTI=y
-CONFIG_PINCTRL_TMPV7700=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_FASTPATH_LIMIT=512
-CONFIG_OF_GPIO=y
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIOLIB_IRQCHIP=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_CDEV=y
-# CONFIG_GPIO_CDEV_V1 is not set
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_REGMAP=m
-
-#
-# Memory mapped GPIO drivers
-#
-CONFIG_GPIO_74XX_MMIO=m
-# CONFIG_GPIO_ALTERA is not set
-# CONFIG_GPIO_AMDPT is not set
-CONFIG_GPIO_RASPBERRYPI_EXP=m
-CONFIG_GPIO_BCM_XGS_IPROC=m
-CONFIG_GPIO_BRCMSTB=m
-# CONFIG_GPIO_CADENCE is not set
-# CONFIG_GPIO_DAVINCI is not set
-CONFIG_GPIO_DWAPB=y
-CONFIG_GPIO_EIC_SPRD=m
-# CONFIG_GPIO_EXAR is not set
-# CONFIG_GPIO_FTGPIO010 is not set
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_GRGPIO=m
-CONFIG_GPIO_HISI=m
-CONFIG_GPIO_HLWD=m
-CONFIG_GPIO_LOGICVC=m
-CONFIG_GPIO_MB86S7X=y
-# CONFIG_GPIO_MPC8XXX is not set
-CONFIG_GPIO_MVEBU=y
-CONFIG_GPIO_MXC=y
-CONFIG_GPIO_PL061=y
-CONFIG_GPIO_RCAR=y
-CONFIG_GPIO_ROCKCHIP=m
-# CONFIG_GPIO_SAMA5D2_PIOBU is not set
-CONFIG_GPIO_SIFIVE=y
-CONFIG_GPIO_SPRD=m
-# CONFIG_GPIO_SYSCON is not set
-CONFIG_GPIO_TEGRA=y
-CONFIG_GPIO_TEGRA186=m
-CONFIG_GPIO_THUNDERX=m
-CONFIG_GPIO_UNIPHIER=y
-CONFIG_GPIO_VISCONTI=m
-CONFIG_GPIO_XGENE=y
-CONFIG_GPIO_XGENE_SB=y
-# CONFIG_GPIO_XILINX is not set
-CONFIG_GPIO_XLP=y
-CONFIG_GPIO_ZYNQ=m
-CONFIG_GPIO_ZYNQMP_MODEPIN=m
-# CONFIG_GPIO_AMD_FCH is not set
-# end of Memory mapped GPIO drivers
-
-#
-# I2C GPIO expanders
-#
-# CONFIG_GPIO_ADP5588 is not set
-# CONFIG_GPIO_ADNP is not set
-# CONFIG_GPIO_GW_PLD is not set
-# CONFIG_GPIO_MAX7300 is not set
-CONFIG_GPIO_MAX732X=m
-CONFIG_GPIO_PCA953X=y
-CONFIG_GPIO_PCA953X_IRQ=y
-CONFIG_GPIO_PCA9570=m
-CONFIG_GPIO_PCF857X=m
-# CONFIG_GPIO_TPIC2810 is not set
-# end of I2C GPIO expanders
-
-#
-# MFD GPIO expanders
-#
-CONFIG_GPIO_ALTERA_A10SR=m
-# CONFIG_GPIO_MADERA is not set
-CONFIG_GPIO_MAX77620=y
-CONFIG_GPIO_SL28CPLD=m
-# CONFIG_GPIO_WM8994 is not set
-# end of MFD GPIO expanders
-
-#
-# PCI GPIO expanders
-#
-# CONFIG_GPIO_PCI_IDIO_16 is not set
-# CONFIG_GPIO_PCIE_IDIO_24 is not set
-# CONFIG_GPIO_RDC321X is not set
-# end of PCI GPIO expanders
-
-#
-# SPI GPIO expanders
-#
-# CONFIG_GPIO_74X164 is not set
-# CONFIG_GPIO_MAX3191X is not set
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MC33880 is not set
-# CONFIG_GPIO_PISOSR is not set
-# CONFIG_GPIO_XRA1403 is not set
-# end of SPI GPIO expanders
-
-#
-# USB GPIO expanders
-#
-# end of USB GPIO expanders
-
-#
-# Virtual GPIO drivers
-#
-# CONFIG_GPIO_AGGREGATOR is not set
-# CONFIG_GPIO_MOCKUP is not set
-CONFIG_GPIO_VIRTIO=m
-# end of Virtual GPIO drivers
-
-CONFIG_W1=m
-CONFIG_W1_CON=y
-
-#
-# 1-wire Bus Masters
-#
-CONFIG_W1_MASTER_MATROX=m
-CONFIG_W1_MASTER_DS2490=m
-CONFIG_W1_MASTER_DS2482=m
-CONFIG_W1_MASTER_MXC=m
-CONFIG_W1_MASTER_DS1WM=m
-# CONFIG_W1_MASTER_GPIO is not set
-CONFIG_W1_MASTER_SGI=m
-# end of 1-wire Bus Masters
-
-#
-# 1-wire Slaves
-#
-CONFIG_W1_SLAVE_THERM=m
-CONFIG_W1_SLAVE_SMEM=m
-# CONFIG_W1_SLAVE_DS2405 is not set
-CONFIG_W1_SLAVE_DS2408=m
-CONFIG_W1_SLAVE_DS2408_READBACK=y
-CONFIG_W1_SLAVE_DS2413=m
-# CONFIG_W1_SLAVE_DS2406 is not set
-# CONFIG_W1_SLAVE_DS2423 is not set
-# CONFIG_W1_SLAVE_DS2805 is not set
-# CONFIG_W1_SLAVE_DS2430 is not set
-CONFIG_W1_SLAVE_DS2431=m
-CONFIG_W1_SLAVE_DS2433=m
-# CONFIG_W1_SLAVE_DS2433_CRC is not set
-# CONFIG_W1_SLAVE_DS2438 is not set
-# CONFIG_W1_SLAVE_DS250X is not set
-# CONFIG_W1_SLAVE_DS2780 is not set
-# CONFIG_W1_SLAVE_DS2781 is not set
-# CONFIG_W1_SLAVE_DS28E04 is not set
-# CONFIG_W1_SLAVE_DS28E17 is not set
-# end of 1-wire Slaves
-
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_AS3722 is not set
-CONFIG_POWER_RESET_ATC260X=m
-# CONFIG_POWER_RESET_BRCMSTB is not set
-CONFIG_POWER_RESET_GPIO=y
-# CONFIG_POWER_RESET_GPIO_RESTART is not set
-CONFIG_POWER_RESET_HISI=y
-CONFIG_POWER_RESET_LINKSTATION=m
-CONFIG_POWER_RESET_MSM=y
-CONFIG_POWER_RESET_QCOM_PON=m
-CONFIG_POWER_RESET_OCELOT_RESET=y
-# CONFIG_POWER_RESET_LTC2952 is not set
-CONFIG_POWER_RESET_REGULATOR=y
-CONFIG_POWER_RESET_RESTART=y
-CONFIG_POWER_RESET_VEXPRESS=y
-# CONFIG_POWER_RESET_XGENE is not set
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-CONFIG_REBOOT_MODE=y
-CONFIG_SYSCON_REBOOT_MODE=y
-# CONFIG_NVMEM_REBOOT_MODE is not set
-CONFIG_POWER_MLXBF=m
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-CONFIG_POWER_SUPPLY_HWMON=y
-# CONFIG_PDA_POWER is not set
-CONFIG_GENERIC_ADC_BATTERY=m
-CONFIG_IP5XXX_POWER=m
-# CONFIG_TEST_POWER is not set
-CONFIG_CHARGER_ADP5061=m
-# CONFIG_BATTERY_CW2015 is not set
-# CONFIG_BATTERY_DS2760 is not set
-# CONFIG_BATTERY_DS2780 is not set
-# CONFIG_BATTERY_DS2781 is not set
-# CONFIG_BATTERY_DS2782 is not set
-CONFIG_BATTERY_SAMSUNG_SDI=y
-# CONFIG_BATTERY_SBS is not set
-# CONFIG_CHARGER_SBS is not set
-# CONFIG_MANAGER_SBS is not set
-CONFIG_BATTERY_BQ27XXX=y
-CONFIG_BATTERY_BQ27XXX_I2C=m
-CONFIG_BATTERY_BQ27XXX_HDQ=m
-# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set
-CONFIG_CHARGER_AXP20X=m
-CONFIG_BATTERY_AXP20X=m
-CONFIG_AXP20X_POWER=m
-# CONFIG_BATTERY_MAX17040 is not set
-# CONFIG_BATTERY_MAX17042 is not set
-# CONFIG_BATTERY_MAX1721X is not set
-# CONFIG_CHARGER_ISP1704 is not set
-# CONFIG_CHARGER_MAX8903 is not set
-# CONFIG_CHARGER_LP8727 is not set
-# CONFIG_CHARGER_GPIO is not set
-# CONFIG_CHARGER_MANAGER is not set
-# CONFIG_CHARGER_LT3651 is not set
-CONFIG_CHARGER_LTC4162L=m
-# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
-CONFIG_CHARGER_QCOM_SMBB=m
-# CONFIG_CHARGER_BQ2415X is not set
-# CONFIG_CHARGER_BQ24190 is not set
-# CONFIG_CHARGER_BQ24257 is not set
-CONFIG_CHARGER_BQ24735=m
-CONFIG_CHARGER_BQ2515X=m
-# CONFIG_CHARGER_BQ25890 is not set
-CONFIG_CHARGER_BQ25980=m
-CONFIG_CHARGER_BQ256XX=m
-CONFIG_CHARGER_RK817=m
-# CONFIG_CHARGER_SMB347 is not set
-# CONFIG_BATTERY_GAUGE_LTC2941 is not set
-CONFIG_BATTERY_GOLDFISH=m
-CONFIG_BATTERY_RT5033=m
-# CONFIG_CHARGER_RT9455 is not set
-CONFIG_CHARGER_CROS_USBPD=m
-CONFIG_CHARGER_CROS_PCHG=m
-# CONFIG_CHARGER_UCS1002 is not set
-# CONFIG_CHARGER_BD99954 is not set
-CONFIG_BATTERY_UG3105=m
-CONFIG_BATTERY_SURFACE=m
-CONFIG_CHARGER_SURFACE=m
-CONFIG_HWMON=y
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Native drivers
-#
-# CONFIG_SENSORS_AD7314 is not set
-# CONFIG_SENSORS_AD7414 is not set
-# CONFIG_SENSORS_AD7418 is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM1177 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7310 is not set
-# CONFIG_SENSORS_ADT7410 is not set
-# CONFIG_SENSORS_ADT7411 is not set
-# CONFIG_SENSORS_ADT7462 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7475 is not set
-CONFIG_SENSORS_AHT10=m
-CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m
-# CONFIG_SENSORS_AS370 is not set
-# CONFIG_SENSORS_ASC7621 is not set
-# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
-CONFIG_SENSORS_ARM_SCPI=y
-# CONFIG_SENSORS_ASPEED is not set
-# CONFIG_SENSORS_ATXP1 is not set
-CONFIG_SENSORS_CORSAIR_CPRO=m
-CONFIG_SENSORS_CORSAIR_PSU=m
-CONFIG_SENSORS_DRIVETEMP=m
-# CONFIG_SENSORS_DS620 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_I5K_AMB is not set
-CONFIG_SENSORS_SPARX5=m
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-CONFIG_SENSORS_MC13783_ADC=m
-CONFIG_SENSORS_FTSTEUTATES=m
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_G760A is not set
-# CONFIG_SENSORS_G762 is not set
-# CONFIG_SENSORS_GPIO_FAN is not set
-# CONFIG_SENSORS_HIH6130 is not set
-# CONFIG_SENSORS_IBMAEM is not set
-# CONFIG_SENSORS_IBMPEX is not set
-CONFIG_SENSORS_IIO_HWMON=m
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_JC42 is not set
-# CONFIG_SENSORS_POWR1220 is not set
-# CONFIG_SENSORS_LINEAGE is not set
-# CONFIG_SENSORS_LTC2945 is not set
-# CONFIG_SENSORS_LTC2947_I2C is not set
-# CONFIG_SENSORS_LTC2947_SPI is not set
-# CONFIG_SENSORS_LTC2990 is not set
-CONFIG_SENSORS_LTC2992=m
-# CONFIG_SENSORS_LTC4151 is not set
-# CONFIG_SENSORS_LTC4215 is not set
-# CONFIG_SENSORS_LTC4222 is not set
-# CONFIG_SENSORS_LTC4245 is not set
-# CONFIG_SENSORS_LTC4260 is not set
-# CONFIG_SENSORS_LTC4261 is not set
-# CONFIG_SENSORS_MAX1111 is not set
-CONFIG_SENSORS_MAX127=m
-# CONFIG_SENSORS_MAX16065 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_MAX1668 is not set
-# CONFIG_SENSORS_MAX197 is not set
-# CONFIG_SENSORS_MAX31722 is not set
-# CONFIG_SENSORS_MAX31730 is not set
-CONFIG_SENSORS_MAX31760=m
-CONFIG_SENSORS_MAX6620=m
-# CONFIG_SENSORS_MAX6621 is not set
-# CONFIG_SENSORS_MAX6639 is not set
-# CONFIG_SENSORS_MAX6642 is not set
-# CONFIG_SENSORS_MAX6650 is not set
-# CONFIG_SENSORS_MAX6697 is not set
-# CONFIG_SENSORS_MAX31790 is not set
-# CONFIG_SENSORS_MCP3021 is not set
-# CONFIG_SENSORS_TC654 is not set
-CONFIG_SENSORS_TPS23861=m
-CONFIG_SENSORS_MR75203=m
-# CONFIG_SENSORS_ADCXX is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM70 is not set
-# CONFIG_SENSORS_LM73 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-CONFIG_SENSORS_LM90=m
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-# CONFIG_SENSORS_LM95234 is not set
-# CONFIG_SENSORS_LM95241 is not set
-# CONFIG_SENSORS_LM95245 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_NTC_THERMISTOR is not set
-# CONFIG_SENSORS_NCT6683 is not set
-# CONFIG_SENSORS_NCT6775 is not set
-# CONFIG_SENSORS_NCT7802 is not set
-# CONFIG_SENSORS_NCT7904 is not set
-# CONFIG_SENSORS_NPCM7XX is not set
-CONFIG_SENSORS_NZXT_KRAKEN2=m
-# CONFIG_SENSORS_OCC_P8_I2C is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_PMBUS is not set
-# CONFIG_SENSORS_PWM_FAN is not set
-CONFIG_SENSORS_RASPBERRYPI_HWMON=m
-CONFIG_SENSORS_SL28CPLD=m
-# CONFIG_SENSORS_SBTSI is not set
-CONFIG_SENSORS_SBRMI=m
-# CONFIG_SENSORS_SHT15 is not set
-# CONFIG_SENSORS_SHT21 is not set
-# CONFIG_SENSORS_SHT3x is not set
-CONFIG_SENSORS_SHT4x=m
-# CONFIG_SENSORS_SHTC1 is not set
-# CONFIG_SENSORS_SIS5595 is not set
-CONFIG_SENSORS_SY7636A=m
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_EMC1403 is not set
-# CONFIG_SENSORS_EMC2103 is not set
-CONFIG_SENSORS_EMC2305=m
-# CONFIG_SENSORS_EMC6W201 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_SCH5627 is not set
-# CONFIG_SENSORS_SCH5636 is not set
-# CONFIG_SENSORS_STTS751 is not set
-# CONFIG_SENSORS_SMM665 is not set
-# CONFIG_SENSORS_ADC128D818 is not set
-# CONFIG_SENSORS_ADS7828 is not set
-# CONFIG_SENSORS_ADS7871 is not set
-# CONFIG_SENSORS_AMC6821 is not set
-CONFIG_SENSORS_INA209=m
-CONFIG_SENSORS_INA2XX=m
-# CONFIG_SENSORS_INA3221 is not set
-# CONFIG_SENSORS_TC74 is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_TMP102 is not set
-# CONFIG_SENSORS_TMP103 is not set
-# CONFIG_SENSORS_TMP108 is not set
-# CONFIG_SENSORS_TMP401 is not set
-# CONFIG_SENSORS_TMP421 is not set
-CONFIG_SENSORS_TMP464=m
-# CONFIG_SENSORS_TMP513 is not set
-CONFIG_SENSORS_VEXPRESS=m
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_VT8231 is not set
-# CONFIG_SENSORS_W83773G is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83795 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83L786NG is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-CONFIG_SENSORS_XGENE=m
-# CONFIG_SENSORS_INTEL_M10_BMC_HWMON is not set
-
-#
-# ACPI drivers
-#
-CONFIG_SENSORS_ACPI_POWER=m
-CONFIG_THERMAL=y
-CONFIG_THERMAL_NETLINK=y
-# CONFIG_THERMAL_STATISTICS is not set
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-# CONFIG_THERMAL_WRITABLE_TRIPS is not set
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-# CONFIG_THERMAL_GOV_BANG_BANG is not set
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_FREQ_THERMAL=y
-CONFIG_DEVFREQ_THERMAL=y
-CONFIG_THERMAL_EMULATION=y
-# CONFIG_THERMAL_MMIO is not set
-CONFIG_HISI_THERMAL=m
-CONFIG_IMX_THERMAL=m
-# CONFIG_IMX_SC_THERMAL is not set
-# CONFIG_IMX8MM_THERMAL is not set
-# CONFIG_K3_THERMAL is not set
-CONFIG_MAX77620_THERMAL=m
-# CONFIG_QORIQ_THERMAL is not set
-CONFIG_SUN8I_THERMAL=m
-CONFIG_ROCKCHIP_THERMAL=y
-CONFIG_RCAR_THERMAL=m
-CONFIG_RCAR_GEN3_THERMAL=y
-CONFIG_ARMADA_THERMAL=m
-CONFIG_MTK_THERMAL=m
-CONFIG_AMLOGIC_THERMAL=y
-
-#
-# Broadcom thermal drivers
-#
-CONFIG_BCM2711_THERMAL=m
-CONFIG_BCM2835_THERMAL=m
-CONFIG_BRCMSTB_THERMAL=m
-CONFIG_BCM_NS_THERMAL=m
-CONFIG_BCM_SR_THERMAL=y
-# end of Broadcom thermal drivers
-
-# CONFIG_TI_SOC_THERMAL is not set
-
-#
-# Samsung thermal drivers
-#
-CONFIG_EXYNOS_THERMAL=y
-# end of Samsung thermal drivers
-
-#
-# NVIDIA Tegra thermal drivers
-#
-CONFIG_TEGRA_SOCTHERM=y
-CONFIG_TEGRA_BPMP_THERMAL=m
-# end of NVIDIA Tegra thermal drivers
-
-# CONFIG_GENERIC_ADC_THERMAL is not set
-
-#
-# Qualcomm thermal drivers
-#
-CONFIG_QCOM_TSENS=y
-CONFIG_QCOM_SPMI_ADC_TM5=m
-CONFIG_QCOM_SPMI_TEMP_ALARM=m
-CONFIG_QCOM_LMH=m
-# end of Qualcomm thermal drivers
-
-CONFIG_UNIPHIER_THERMAL=y
-# CONFIG_SPRD_THERMAL is not set
-# CONFIG_KHADAS_MCU_FAN_THERMAL is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_CORE=m
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
-CONFIG_WATCHDOG_OPEN_TIMEOUT=0
-CONFIG_WATCHDOG_SYSFS=y
-# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
-
-#
-# Watchdog Pretimeout Governors
-#
-# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
-
-#
-# Watchdog Device Drivers
-#
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_BD957XMUF_WATCHDOG=m
-CONFIG_GPIO_WATCHDOG=m
-# CONFIG_WDAT_WDT is not set
-# CONFIG_XILINX_WATCHDOG is not set
-CONFIG_ZIIRAVE_WATCHDOG=m
-CONFIG_SL28CPLD_WATCHDOG=m
-CONFIG_ARM_SP805_WATCHDOG=m
-CONFIG_ARM_SBSA_WATCHDOG=m
-# CONFIG_ARMADA_37XX_WATCHDOG is not set
-# CONFIG_CADENCE_WATCHDOG is not set
-CONFIG_S3C2410_WATCHDOG=y
-CONFIG_DW_WATCHDOG=m
-# CONFIG_K3_RTI_WATCHDOG is not set
-CONFIG_SUNXI_WATCHDOG=m
-CONFIG_NPCM7XX_WATCHDOG=m
-# CONFIG_MAX63XX_WATCHDOG is not set
-CONFIG_MAX77620_WATCHDOG=m
-CONFIG_IMX2_WDT=m
-CONFIG_IMX_SC_WDT=m
-CONFIG_IMX7ULP_WDT=m
-CONFIG_TEGRA_WATCHDOG=m
-CONFIG_QCOM_WDT=m
-CONFIG_MESON_GXBB_WATCHDOG=m
-CONFIG_MESON_WATCHDOG=m
-CONFIG_MEDIATEK_WATCHDOG=m
-# CONFIG_ARM_SMC_WATCHDOG is not set
-CONFIG_RENESAS_WDT=y
-CONFIG_RENESAS_RZAWDT=m
-CONFIG_UNIPHIER_WATCHDOG=y
-CONFIG_RTD119X_WATCHDOG=y
-CONFIG_SPRD_WATCHDOG=m
-# CONFIG_PM8916_WATCHDOG is not set
-CONFIG_VISCONTI_WATCHDOG=m
-CONFIG_APPLE_WATCHDOG=m
-# CONFIG_ALIM7101_WDT is not set
-# CONFIG_I6300ESB_WDT is not set
-CONFIG_HP_WATCHDOG=m
-CONFIG_BCM2835_WDT=y
-CONFIG_BCM7038_WDT=m
-# CONFIG_MEN_A21_WDT is not set
-
-#
-# PCI-based Watchdog Cards
-#
-# CONFIG_PCIPCWATCHDOG is not set
-# CONFIG_WDTPCI is not set
-
-#
-# USB-based Watchdog Cards
-#
-CONFIG_USBPCWATCHDOG=m
-CONFIG_KEEMBAY_WATCHDOG=m
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SSB=y
-CONFIG_SSB_SPROM=y
-CONFIG_SSB_BLOCKIO=y
-CONFIG_SSB_PCIHOST_POSSIBLE=y
-CONFIG_SSB_PCIHOST=y
-CONFIG_SSB_B43_PCI_BRIDGE=y
-CONFIG_SSB_SDIOHOST_POSSIBLE=y
-CONFIG_SSB_SDIOHOST=y
-CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
-CONFIG_SSB_DRIVER_PCICORE=y
-# CONFIG_SSB_DRIVER_GPIO is not set
-CONFIG_BCMA_POSSIBLE=y
-CONFIG_BCMA=m
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_SOC=y
-CONFIG_BCMA_DRIVER_PCI=y
-CONFIG_BCMA_SFLASH=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_DRIVER_GPIO=y
-# CONFIG_BCMA_DEBUG is not set
-
-#
-# Multifunction device drivers
-#
-CONFIG_MFD_CORE=y
-CONFIG_MFD_ALTERA_A10SR=y
-# CONFIG_MFD_ALTERA_SYSMGR is not set
-# CONFIG_MFD_ACT8945A is not set
-CONFIG_MFD_SUN4I_GPADC=m
-# CONFIG_MFD_AS3711 is not set
-CONFIG_MFD_AS3722=m
-# CONFIG_PMIC_ADP5520 is not set
-# CONFIG_MFD_AAT2870_CORE is not set
-CONFIG_MFD_ATMEL_FLEXCOM=m
-# CONFIG_MFD_ATMEL_HLCDC is not set
-# CONFIG_MFD_BCM590XX is not set
-# CONFIG_MFD_BD9571MWV is not set
-CONFIG_MFD_AC100=m
-CONFIG_MFD_AXP20X=y
-# CONFIG_MFD_AXP20X_I2C is not set
-CONFIG_MFD_AXP20X_RSB=y
-CONFIG_MFD_CROS_EC_DEV=y
-CONFIG_MFD_MADERA=m
-CONFIG_MFD_MADERA_I2C=m
-CONFIG_MFD_MADERA_SPI=m
-# CONFIG_MFD_CS47L15 is not set
-CONFIG_MFD_CS47L35=y
-CONFIG_MFD_CS47L85=y
-CONFIG_MFD_CS47L90=y
-# CONFIG_MFD_CS47L92 is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_MFD_DA9052_SPI is not set
-# CONFIG_MFD_DA9052_I2C is not set
-# CONFIG_MFD_DA9055 is not set
-# CONFIG_MFD_DA9062 is not set
-# CONFIG_MFD_DA9063 is not set
-# CONFIG_MFD_DA9150 is not set
-# CONFIG_MFD_DLN2 is not set
-CONFIG_MFD_EXYNOS_LPASS=m
-# CONFIG_MFD_GATEWORKS_GSC is not set
-CONFIG_MFD_MC13XXX=m
-# CONFIG_MFD_MC13XXX_SPI is not set
-CONFIG_MFD_MC13XXX_I2C=m
-# CONFIG_MFD_MP2629 is not set
-CONFIG_MFD_HI6421_PMIC=y
-CONFIG_MFD_HI6421_SPMI=m
-CONFIG_MFD_HI655X_PMIC=y
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_HTC_I2CPLD is not set
-# CONFIG_LPC_ICH is not set
-# CONFIG_LPC_SCH is not set
-# CONFIG_MFD_IQS62X is not set
-# CONFIG_MFD_JANZ_CMODIO is not set
-# CONFIG_MFD_KEMPLD is not set
-# CONFIG_MFD_88PM800 is not set
-# CONFIG_MFD_88PM805 is not set
-# CONFIG_MFD_88PM860X is not set
-# CONFIG_MFD_MAX14577 is not set
-CONFIG_MFD_MAX77620=y
-# CONFIG_MFD_MAX77650 is not set
-# CONFIG_MFD_MAX77686 is not set
-# CONFIG_MFD_MAX77693 is not set
-CONFIG_MFD_MAX77714=m
-# CONFIG_MFD_MAX77843 is not set
-# CONFIG_MFD_MAX8907 is not set
-# CONFIG_MFD_MAX8925 is not set
-# CONFIG_MFD_MAX8997 is not set
-# CONFIG_MFD_MAX8998 is not set
-# CONFIG_MFD_MT6360 is not set
-CONFIG_MFD_MT6370=m
-# CONFIG_MFD_MT6397 is not set
-# CONFIG_MFD_MENF21BMC is not set
-CONFIG_MFD_OCELOT=m
-# CONFIG_EZX_PCAP is not set
-# CONFIG_MFD_CPCAP is not set
-# CONFIG_MFD_VIPERBOARD is not set
-CONFIG_MFD_NTXEC=m
-# CONFIG_MFD_RETU is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_UCB1400_CORE is not set
-CONFIG_MFD_QCOM_RPM=m
-CONFIG_MFD_SPMI_PMIC=y
-CONFIG_MFD_SY7636A=m
-# CONFIG_MFD_RDC321X is not set
-CONFIG_MFD_RT4831=m
-# CONFIG_MFD_RT5033 is not set
-CONFIG_MFD_RT5120=m
-# CONFIG_MFD_RC5T583 is not set
-CONFIG_MFD_RK808=y
-# CONFIG_MFD_RN5T618 is not set
-CONFIG_MFD_SEC_CORE=y
-CONFIG_MFD_SI476X_CORE=m
-CONFIG_MFD_SIMPLE_MFD_I2C=m
-CONFIG_MFD_SL28CPLD=m
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_SKY81452 is not set
-# CONFIG_MFD_SC27XX_PMIC is not set
-# CONFIG_MFD_STMPE is not set
-CONFIG_MFD_SUN6I_PRCM=y
-CONFIG_MFD_SYSCON=y
-# CONFIG_MFD_TI_AM335X_TSCADC is not set
-# CONFIG_MFD_LP3943 is not set
-# CONFIG_MFD_LP8788 is not set
-# CONFIG_MFD_TI_LMU is not set
-# CONFIG_MFD_PALMAS is not set
-# CONFIG_TPS6105X is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TPS6507X is not set
-# CONFIG_MFD_TPS65086 is not set
-# CONFIG_MFD_TPS65090 is not set
-# CONFIG_MFD_TPS65217 is not set
-# CONFIG_MFD_TI_LP873X is not set
-# CONFIG_MFD_TI_LP87565 is not set
-# CONFIG_MFD_TPS65218 is not set
-# CONFIG_MFD_TPS6586X is not set
-# CONFIG_MFD_TPS65910 is not set
-# CONFIG_MFD_TPS65912_I2C is not set
-# CONFIG_MFD_TPS65912_SPI is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_TWL6040_CORE is not set
-# CONFIG_MFD_WL1273_CORE is not set
-# CONFIG_MFD_LM3533 is not set
-# CONFIG_MFD_TC3589X is not set
-# CONFIG_MFD_TQMX86 is not set
-# CONFIG_MFD_VX855 is not set
-# CONFIG_MFD_LOCHNAGAR is not set
-# CONFIG_MFD_ARIZONA_I2C is not set
-# CONFIG_MFD_ARIZONA_SPI is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X_I2C is not set
-# CONFIG_MFD_WM831X_SPI is not set
-# CONFIG_MFD_WM8350_I2C is not set
-CONFIG_MFD_WM8994=m
-# CONFIG_MFD_ROHM_BD718XX is not set
-# CONFIG_MFD_ROHM_BD70528 is not set
-# CONFIG_MFD_ROHM_BD71828 is not set
-CONFIG_MFD_ROHM_BD957XMUF=m
-# CONFIG_MFD_STPMIC1 is not set
-# CONFIG_MFD_STMFX is not set
-CONFIG_MFD_ATC260X=m
-CONFIG_MFD_ATC260X_I2C=m
-CONFIG_MFD_KHADAS_MCU=m
-CONFIG_MFD_QCOM_PM8008=m
-CONFIG_MFD_VEXPRESS_SYSREG=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_MFD_INTEL_M10_BMC=m
-CONFIG_MFD_RSMU_I2C=m
-CONFIG_MFD_RSMU_SPI=m
-# end of Multifunction device drivers
-
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_REGULATOR_88PG86X is not set
-# CONFIG_REGULATOR_ACT8865 is not set
-# CONFIG_REGULATOR_AD5398 is not set
-# CONFIG_REGULATOR_ANATOP is not set
-# CONFIG_REGULATOR_ARIZONA_LDO1 is not set
-# CONFIG_REGULATOR_ARIZONA_MICSUPP is not set
-CONFIG_REGULATOR_AS3722=m
-CONFIG_REGULATOR_ATC260X=m
-CONFIG_REGULATOR_AXP20X=y
-CONFIG_REGULATOR_BD957XMUF=m
-CONFIG_REGULATOR_CROS_EC=m
-CONFIG_REGULATOR_DA9121=m
-# CONFIG_REGULATOR_DA9210 is not set
-# CONFIG_REGULATOR_DA9211 is not set
-CONFIG_REGULATOR_FAN53555=y
-CONFIG_REGULATOR_FAN53880=m
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_HI6421=m
-CONFIG_REGULATOR_HI6421V530=y
-CONFIG_REGULATOR_HI655X=y
-CONFIG_REGULATOR_HI6421V600=m
-# CONFIG_REGULATOR_ISL9305 is not set
-# CONFIG_REGULATOR_ISL6271A is not set
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_LP3972 is not set
-# CONFIG_REGULATOR_LP872X is not set
-# CONFIG_REGULATOR_LP8755 is not set
-# CONFIG_REGULATOR_LTC3589 is not set
-# CONFIG_REGULATOR_LTC3676 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-CONFIG_REGULATOR_MAX77620=y
-# CONFIG_REGULATOR_MAX8649 is not set
-# CONFIG_REGULATOR_MAX8660 is not set
-CONFIG_REGULATOR_MAX8893=m
-# CONFIG_REGULATOR_MAX8952 is not set
-# CONFIG_REGULATOR_MAX8973 is not set
-# CONFIG_REGULATOR_MAX77826 is not set
-# CONFIG_REGULATOR_MC13783 is not set
-# CONFIG_REGULATOR_MC13892 is not set
-# CONFIG_REGULATOR_MCP16502 is not set
-# CONFIG_REGULATOR_MP5416 is not set
-CONFIG_REGULATOR_MP8859=y
-# CONFIG_REGULATOR_MP886X is not set
-# CONFIG_REGULATOR_MPQ7920 is not set
-CONFIG_REGULATOR_MT6311=m
-CONFIG_REGULATOR_MT6315=m
-CONFIG_REGULATOR_MT6370=m
-# CONFIG_REGULATOR_MT6380 is not set
-CONFIG_REGULATOR_PCA9450=m
-CONFIG_REGULATOR_PF8X00=m
-# CONFIG_REGULATOR_PFUZE100 is not set
-# CONFIG_REGULATOR_PV88060 is not set
-# CONFIG_REGULATOR_PV88080 is not set
-# CONFIG_REGULATOR_PV88090 is not set
-CONFIG_REGULATOR_PWM=y
-CONFIG_REGULATOR_QCOM_RPM=m
-# CONFIG_REGULATOR_QCOM_RPMH is not set
-CONFIG_REGULATOR_QCOM_SMD_RPM=y
-CONFIG_REGULATOR_QCOM_SPMI=y
-CONFIG_REGULATOR_QCOM_USB_VBUS=m
-CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
-CONFIG_REGULATOR_RK808=y
-CONFIG_REGULATOR_RT4801=m
-CONFIG_REGULATOR_RT4831=m
-CONFIG_REGULATOR_RT5120=m
-CONFIG_REGULATOR_RT5190A=m
-CONFIG_REGULATOR_RT6160=m
-CONFIG_REGULATOR_RT6245=m
-CONFIG_REGULATOR_RTQ2134=m
-CONFIG_REGULATOR_RTMV20=m
-CONFIG_REGULATOR_RTQ6752=m
-CONFIG_REGULATOR_S2MPA01=y
-CONFIG_REGULATOR_S2MPS11=y
-CONFIG_REGULATOR_S5M8767=y
-# CONFIG_REGULATOR_SLG51000 is not set
-CONFIG_REGULATOR_SY7636A=m
-# CONFIG_REGULATOR_SY8106A is not set
-# CONFIG_REGULATOR_SY8824X is not set
-CONFIG_REGULATOR_SY8827N=m
-# CONFIG_REGULATOR_TPS51632 is not set
-# CONFIG_REGULATOR_TPS62360 is not set
-CONFIG_REGULATOR_TPS6286X=m
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-# CONFIG_REGULATOR_TPS65132 is not set
-# CONFIG_REGULATOR_TPS6524X is not set
-CONFIG_REGULATOR_UNIPHIER=y
-# CONFIG_REGULATOR_VCTRL is not set
-CONFIG_REGULATOR_VEXPRESS=m
-CONFIG_REGULATOR_VQMMC_IPQ4019=m
-# CONFIG_REGULATOR_WM8994 is not set
-CONFIG_REGULATOR_QCOM_LABIBB=m
-CONFIG_RC_CORE=m
-CONFIG_RC_MAP=m
-CONFIG_LIRC=y
-CONFIG_RC_DECODERS=y
-CONFIG_IR_NEC_DECODER=m
-CONFIG_IR_RC5_DECODER=m
-CONFIG_IR_RC6_DECODER=m
-CONFIG_IR_JVC_DECODER=m
-CONFIG_IR_SONY_DECODER=m
-CONFIG_IR_SANYO_DECODER=m
-CONFIG_IR_SHARP_DECODER=m
-CONFIG_IR_MCE_KBD_DECODER=m
-CONFIG_IR_XMP_DECODER=m
-CONFIG_IR_IMON_DECODER=m
-CONFIG_IR_RCMM_DECODER=m
-CONFIG_RC_DEVICES=y
-CONFIG_RC_ATI_REMOTE=m
-# CONFIG_IR_ENE is not set
-# CONFIG_IR_HIX5HD2 is not set
-# CONFIG_IR_IMON is not set
-CONFIG_IR_IMON_RAW=m
-# CONFIG_IR_MCEUSB is not set
-# CONFIG_IR_ITE_CIR is not set
-# CONFIG_IR_FINTEK is not set
-CONFIG_IR_MESON=m
-CONFIG_IR_MESON_TX=m
-CONFIG_IR_MTK=m
-# CONFIG_IR_NUVOTON is not set
-# CONFIG_IR_REDRAT3 is not set
-# CONFIG_IR_SPI is not set
-# CONFIG_IR_STREAMZAP is not set
-# CONFIG_IR_IGORPLUGUSB is not set
-# CONFIG_IR_IGUANA is not set
-# CONFIG_IR_TTUSBIR is not set
-# CONFIG_RC_LOOPBACK is not set
-# CONFIG_IR_GPIO_CIR is not set
-# CONFIG_IR_GPIO_TX is not set
-# CONFIG_IR_PWM_TX is not set
-CONFIG_IR_SUNXI=m
-# CONFIG_IR_SERIAL is not set
-# CONFIG_RC_XBOX_DVD is not set
-CONFIG_IR_TOY=m
-CONFIG_CEC_CORE=y
-CONFIG_CEC_NOTIFIER=y
-CONFIG_CEC_PIN=y
-
-#
-# CEC support
-#
-CONFIG_MEDIA_CEC_SUPPORT=y
-# CONFIG_CEC_CH7322 is not set
-# CONFIG_CEC_CROS_EC is not set
-# CONFIG_CEC_MESON_AO is not set
-# CONFIG_CEC_MESON_G12A_AO is not set
-CONFIG_CEC_GPIO=m
-# CONFIG_CEC_SAMSUNG_S5P is not set
-# CONFIG_CEC_TEGRA is not set
-# CONFIG_USB_PULSE8_CEC is not set
-# CONFIG_USB_RAINSHADOW_CEC is not set
-# end of CEC support
-
-CONFIG_MEDIA_SUPPORT=m
-# CONFIG_MEDIA_SUPPORT_FILTER is not set
-CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
-
-#
-# Media device types
-#
-CONFIG_MEDIA_PLATFORM_DRIVERS=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_SDR_SUPPORT=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-CONFIG_MEDIA_TEST_SUPPORT=y
-# end of Media device types
-
-#
-# Media core support
-#
-CONFIG_VIDEO_DEV=m
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_DVB_CORE=m
-# end of Media core support
-
-#
-# Video4Linux options
-#
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L2_I2C=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_TUNER=m
-CONFIG_V4L2_JPEG_HELPER=m
-CONFIG_V4L2_H264=m
-CONFIG_V4L2_MEM2MEM_DEV=m
-CONFIG_V4L2_FWNODE=m
-CONFIG_V4L2_ASYNC=m
-CONFIG_VIDEOBUF_GEN=m
-CONFIG_VIDEOBUF_DMA_SG=m
-CONFIG_VIDEOBUF_VMALLOC=m
-# end of Video4Linux options
-
-#
-# Media controller options
-#
-CONFIG_MEDIA_CONTROLLER_DVB=y
-CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
-# end of Media controller options
-
-#
-# Digital TV options
-#
-# CONFIG_DVB_MMAP is not set
-# CONFIG_DVB_NET is not set
-CONFIG_DVB_MAX_ADAPTERS=8
-# CONFIG_DVB_DYNAMIC_MINORS is not set
-# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
-# CONFIG_DVB_ULE_DEBUG is not set
-# end of Digital TV options
-
-#
-# Media drivers
-#
-CONFIG_MEDIA_USB_SUPPORT=y
-
-#
-# Webcam devices
-#
-CONFIG_USB_VIDEO_CLASS=m
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-CONFIG_USB_M5602=m
-CONFIG_USB_STV06XX=m
-CONFIG_USB_GL860=m
-CONFIG_USB_GSPCA_BENQ=m
-CONFIG_USB_GSPCA_CONEX=m
-CONFIG_USB_GSPCA_CPIA1=m
-# CONFIG_USB_GSPCA_DTCS033 is not set
-CONFIG_USB_GSPCA_ETOMS=m
-CONFIG_USB_GSPCA_FINEPIX=m
-CONFIG_USB_GSPCA_JEILINJ=m
-CONFIG_USB_GSPCA_JL2005BCD=m
-CONFIG_USB_GSPCA_KINECT=m
-CONFIG_USB_GSPCA_KONICA=m
-CONFIG_USB_GSPCA_MARS=m
-CONFIG_USB_GSPCA_MR97310A=m
-CONFIG_USB_GSPCA_NW80X=m
-CONFIG_USB_GSPCA_OV519=m
-CONFIG_USB_GSPCA_OV534=m
-CONFIG_USB_GSPCA_OV534_9=m
-CONFIG_USB_GSPCA_PAC207=m
-CONFIG_USB_GSPCA_PAC7302=m
-CONFIG_USB_GSPCA_PAC7311=m
-CONFIG_USB_GSPCA_SE401=m
-CONFIG_USB_GSPCA_SN9C2028=m
-CONFIG_USB_GSPCA_SN9C20X=m
-CONFIG_USB_GSPCA_SONIXB=m
-CONFIG_USB_GSPCA_SONIXJ=m
-CONFIG_USB_GSPCA_SPCA500=m
-CONFIG_USB_GSPCA_SPCA501=m
-CONFIG_USB_GSPCA_SPCA505=m
-CONFIG_USB_GSPCA_SPCA506=m
-CONFIG_USB_GSPCA_SPCA508=m
-CONFIG_USB_GSPCA_SPCA561=m
-CONFIG_USB_GSPCA_SPCA1528=m
-CONFIG_USB_GSPCA_SQ905=m
-CONFIG_USB_GSPCA_SQ905C=m
-CONFIG_USB_GSPCA_SQ930X=m
-CONFIG_USB_GSPCA_STK014=m
-CONFIG_USB_GSPCA_STK1135=m
-CONFIG_USB_GSPCA_STV0680=m
-CONFIG_USB_GSPCA_SUNPLUS=m
-CONFIG_USB_GSPCA_T613=m
-CONFIG_USB_GSPCA_TOPRO=m
-CONFIG_USB_GSPCA_TOUPTEK=m
-CONFIG_USB_GSPCA_TV8532=m
-CONFIG_USB_GSPCA_VC032X=m
-CONFIG_USB_GSPCA_VICAM=m
-CONFIG_USB_GSPCA_XIRLINK_CIT=m
-CONFIG_USB_GSPCA_ZC3XX=m
-CONFIG_USB_PWC=m
-# CONFIG_USB_PWC_DEBUG is not set
-CONFIG_USB_PWC_INPUT_EVDEV=y
-CONFIG_VIDEO_CPIA2=m
-CONFIG_USB_ZR364XX=m
-CONFIG_USB_STKWEBCAM=m
-CONFIG_USB_S2255=m
-CONFIG_VIDEO_USBTV=m
-
-#
-# Analog TV USB devices
-#
-CONFIG_VIDEO_PVRUSB2=m
-CONFIG_VIDEO_PVRUSB2_SYSFS=y
-CONFIG_VIDEO_PVRUSB2_DVB=y
-# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
-CONFIG_VIDEO_HDPVR=m
-CONFIG_VIDEO_STK1160_COMMON=m
-CONFIG_VIDEO_STK1160=m
-# CONFIG_VIDEO_GO7007 is not set
-
-#
-# Analog/digital TV USB devices
-#
-CONFIG_VIDEO_AU0828=m
-CONFIG_VIDEO_AU0828_V4L2=y
-# CONFIG_VIDEO_AU0828_RC is not set
-CONFIG_VIDEO_CX231XX=m
-CONFIG_VIDEO_CX231XX_RC=y
-CONFIG_VIDEO_CX231XX_ALSA=m
-CONFIG_VIDEO_CX231XX_DVB=m
-# CONFIG_VIDEO_TM6000 is not set
-
-#
-# Digital TV USB devices
-#
-CONFIG_DVB_USB=m
-# CONFIG_DVB_USB_DEBUG is not set
-CONFIG_DVB_USB_DIB3000MC=m
-CONFIG_DVB_USB_A800=m
-CONFIG_DVB_USB_DIBUSB_MB=m
-# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
-CONFIG_DVB_USB_DIBUSB_MC=m
-CONFIG_DVB_USB_DIB0700=m
-CONFIG_DVB_USB_UMT_010=m
-CONFIG_DVB_USB_CXUSB=m
-# CONFIG_DVB_USB_CXUSB_ANALOG is not set
-CONFIG_DVB_USB_M920X=m
-CONFIG_DVB_USB_DIGITV=m
-CONFIG_DVB_USB_VP7045=m
-CONFIG_DVB_USB_VP702X=m
-CONFIG_DVB_USB_GP8PSK=m
-CONFIG_DVB_USB_NOVA_T_USB2=m
-CONFIG_DVB_USB_TTUSB2=m
-CONFIG_DVB_USB_DTT200U=m
-CONFIG_DVB_USB_OPERA1=m
-CONFIG_DVB_USB_AF9005=m
-CONFIG_DVB_USB_AF9005_REMOTE=m
-CONFIG_DVB_USB_PCTV452E=m
-CONFIG_DVB_USB_DW2102=m
-CONFIG_DVB_USB_CINERGY_T2=m
-CONFIG_DVB_USB_DTV5100=m
-CONFIG_DVB_USB_AZ6027=m
-CONFIG_DVB_USB_TECHNISAT_USB2=m
-CONFIG_DVB_USB_V2=m
-CONFIG_DVB_USB_AF9015=m
-CONFIG_DVB_USB_AF9035=m
-CONFIG_DVB_USB_ANYSEE=m
-CONFIG_DVB_USB_AU6610=m
-# CONFIG_DVB_USB_AZ6007 is not set
-CONFIG_DVB_USB_CE6230=m
-CONFIG_DVB_USB_EC168=m
-CONFIG_DVB_USB_GL861=m
-CONFIG_DVB_USB_LME2510=m
-CONFIG_DVB_USB_MXL111SF=m
-CONFIG_DVB_USB_RTL28XXU=m
-# CONFIG_DVB_USB_DVBSKY is not set
-# CONFIG_DVB_USB_ZD1301 is not set
-CONFIG_DVB_TTUSB_BUDGET=m
-CONFIG_DVB_TTUSB_DEC=m
-CONFIG_SMS_USB_DRV=m
-CONFIG_DVB_B2C2_FLEXCOP_USB=m
-# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
-# CONFIG_DVB_AS102 is not set
-
-#
-# Webcam, TV (analog/digital) USB devices
-#
-CONFIG_VIDEO_EM28XX=m
-CONFIG_VIDEO_EM28XX_V4L2=m
-CONFIG_VIDEO_EM28XX_ALSA=m
-CONFIG_VIDEO_EM28XX_DVB=m
-CONFIG_VIDEO_EM28XX_RC=m
-
-#
-# Software defined radio USB devices
-#
-# CONFIG_USB_AIRSPY is not set
-# CONFIG_USB_HACKRF is not set
-# CONFIG_USB_MSI2500 is not set
-CONFIG_MEDIA_PCI_SUPPORT=y
-
-#
-# Media capture support
-#
-# CONFIG_VIDEO_SOLO6X10 is not set
-# CONFIG_VIDEO_TW5864 is not set
-# CONFIG_VIDEO_TW68 is not set
-# CONFIG_VIDEO_TW686X is not set
-
-#
-# Media capture/analog TV support
-#
-CONFIG_VIDEO_IVTV=m
-CONFIG_VIDEO_IVTV_ALSA=m
-CONFIG_VIDEO_FB_IVTV=m
-CONFIG_VIDEO_HEXIUM_GEMINI=m
-CONFIG_VIDEO_HEXIUM_ORION=m
-CONFIG_VIDEO_MXB=m
-# CONFIG_VIDEO_DT3155 is not set
-
-#
-# Media capture/analog/hybrid TV support
-#
-CONFIG_VIDEO_CX18=m
-# CONFIG_VIDEO_CX18_ALSA is not set
-CONFIG_VIDEO_CX23885=m
-CONFIG_MEDIA_ALTERA_CI=m
-# CONFIG_VIDEO_CX25821 is not set
-CONFIG_VIDEO_CX88=m
-CONFIG_VIDEO_CX88_ALSA=m
-CONFIG_VIDEO_CX88_BLACKBIRD=m
-CONFIG_VIDEO_CX88_DVB=m
-CONFIG_VIDEO_CX88_ENABLE_VP3054=y
-CONFIG_VIDEO_CX88_VP3054=m
-CONFIG_VIDEO_CX88_MPEG=m
-CONFIG_VIDEO_BT848=m
-CONFIG_DVB_BT8XX=m
-CONFIG_VIDEO_SAA7134=m
-CONFIG_VIDEO_SAA7134_ALSA=m
-CONFIG_VIDEO_SAA7134_RC=y
-CONFIG_VIDEO_SAA7134_DVB=m
-# CONFIG_VIDEO_SAA7164 is not set
-
-#
-# Media digital TV PCI Adapters
-#
-CONFIG_DVB_BUDGET_CORE=m
-CONFIG_DVB_BUDGET=m
-CONFIG_DVB_BUDGET_CI=m
-CONFIG_DVB_BUDGET_AV=m
-CONFIG_DVB_B2C2_FLEXCOP_PCI=m
-# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
-CONFIG_DVB_PLUTO2=m
-CONFIG_DVB_DM1105=m
-# CONFIG_DVB_PT1 is not set
-# CONFIG_DVB_PT3 is not set
-# CONFIG_MANTIS_CORE is not set
-# CONFIG_DVB_NGENE is not set
-# CONFIG_DVB_DDBRIDGE is not set
-# CONFIG_DVB_SMIPCIE is not set
-CONFIG_DVB_NETUP_UNIDVB=m
-CONFIG_RADIO_ADAPTERS=y
-CONFIG_RADIO_TEA575X=m
-# CONFIG_RADIO_SI470X is not set
-# CONFIG_RADIO_SI4713 is not set
-# CONFIG_RADIO_SI476X is not set
-CONFIG_USB_MR800=m
-CONFIG_USB_DSBR=m
-CONFIG_RADIO_MAXIRADIO=m
-CONFIG_RADIO_SHARK=m
-CONFIG_RADIO_SHARK2=m
-# CONFIG_USB_KEENE is not set
-# CONFIG_USB_RAREMONO is not set
-# CONFIG_USB_MA901 is not set
-CONFIG_RADIO_TEA5764=m
-# CONFIG_RADIO_SAA7706H is not set
-# CONFIG_RADIO_TEF6862 is not set
-# CONFIG_RADIO_WL1273 is not set
-CONFIG_RADIO_WL128X=m
-CONFIG_MEDIA_COMMON_OPTIONS=y
-
-#
-# common driver options
-#
-CONFIG_VIDEO_CX2341X=m
-CONFIG_VIDEO_TVEEPROM=m
-CONFIG_TTPCI_EEPROM=m
-CONFIG_CYPRESS_FIRMWARE=m
-CONFIG_VIDEOBUF2_CORE=m
-CONFIG_VIDEOBUF2_V4L2=m
-CONFIG_VIDEOBUF2_MEMOPS=m
-CONFIG_VIDEOBUF2_DMA_CONTIG=m
-CONFIG_VIDEOBUF2_VMALLOC=m
-CONFIG_VIDEOBUF2_DMA_SG=m
-CONFIG_VIDEOBUF2_DVB=m
-CONFIG_DVB_B2C2_FLEXCOP=m
-CONFIG_VIDEO_SAA7146=m
-CONFIG_VIDEO_SAA7146_VV=m
-CONFIG_SMS_SIANO_MDTV=m
-CONFIG_SMS_SIANO_RC=y
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_CAFE_CCIC=m
-# CONFIG_VIDEO_CADENCE is not set
-# CONFIG_VIDEO_ASPEED is not set
-CONFIG_VIDEO_CADENCE_CSI2RX=m
-CONFIG_VIDEO_CADENCE_CSI2TX=m
-CONFIG_VIDEO_MUX=m
-CONFIG_VIDEO_QCOM_CAMSS=m
-CONFIG_VIDEO_ROCKCHIP_ISP1=m
-CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS=m
-CONFIG_VIDEO_EXYNOS4_IS_COMMON=m
-CONFIG_VIDEO_S5P_FIMC=m
-CONFIG_VIDEO_S5P_MIPI_CSIS=m
-CONFIG_VIDEO_EXYNOS4_FIMC_IS=m
-CONFIG_VIDEO_EXYNOS4_ISP_DMA_CAPTURE=y
-CONFIG_VIDEO_XILINX=m
-CONFIG_VIDEO_XILINX_CSI2RXSS=m
-CONFIG_VIDEO_XILINX_TPG=m
-CONFIG_VIDEO_XILINX_VTC=m
-# CONFIG_VIDEO_RCAR_CSI2 is not set
-CONFIG_VIDEO_RCAR_VIN=m
-CONFIG_VIDEO_SUN4I_CSI=m
-CONFIG_VIDEO_SUN6I_CSI=m
-# CONFIG_VIDEO_TI_CAL is not set
-CONFIG_VIDEO_RCAR_ISP=m
-CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_VIDEO_ALLEGRO_DVT=m
-# CONFIG_VIDEO_CODA is not set
-CONFIG_VIDEO_IMX_PXP=m
-CONFIG_VIDEO_DW100=m
-CONFIG_VIDEO_IMX8_JPEG=m
-# CONFIG_VIDEO_MEDIATEK_JPEG is not set
-CONFIG_VIDEO_MEDIATEK_VPU=m
-CONFIG_VIDEO_MEDIATEK_MDP3=m
-CONFIG_VIDEO_TEGRA_VDE=m
-CONFIG_VIDEO_IMX_MIPI_CSIS=m
-# CONFIG_VIDEO_MEDIATEK_MDP is not set
-# CONFIG_VIDEO_MEDIATEK_VCODEC is not set
-CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
-CONFIG_VIDEO_MESON_GE2D=m
-CONFIG_VIDEO_AMPHION_VPU=m
-CONFIG_VIDEO_SAMSUNG_S5P_G2D=m
-CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
-CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
-CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
-CONFIG_VIDEO_RENESAS_FDP1=m
-CONFIG_VIDEO_RENESAS_JPU=m
-CONFIG_VIDEO_RENESAS_FCP=m
-CONFIG_VIDEO_RENESAS_VSP1=m
-CONFIG_VIDEO_ROCKCHIP_IEP=m
-CONFIG_VIDEO_ROCKCHIP_RGA=m
-CONFIG_VIDEO_QCOM_VENUS=m
-CONFIG_VIDEO_SUN8I_DEINTERLACE=m
-# CONFIG_VIDEO_SUN8I_ROTATE is not set
-CONFIG_DVB_PLATFORM_DRIVERS=y
-# CONFIG_SDR_PLATFORM_DRIVERS is not set
-
-#
-# MMC/SDIO DVB adapters
-#
-CONFIG_SMS_SDIO_DRV=m
-# CONFIG_V4L_TEST_DRIVERS is not set
-# CONFIG_DVB_TEST_DRIVERS is not set
-# end of Media drivers
-
-#
-# Media ancillary drivers
-#
-CONFIG_MEDIA_ATTACH=y
-
-#
-# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
-#
-CONFIG_VIDEO_IR_I2C=m
-
-#
-# Audio decoders, processors and mixers
-#
-CONFIG_VIDEO_TVAUDIO=m
-CONFIG_VIDEO_TDA7432=m
-CONFIG_VIDEO_TDA9840=m
-# CONFIG_VIDEO_TDA1997X is not set
-CONFIG_VIDEO_TEA6415C=m
-CONFIG_VIDEO_TEA6420=m
-CONFIG_VIDEO_MSP3400=m
-CONFIG_VIDEO_CS3308=m
-CONFIG_VIDEO_CS5345=m
-CONFIG_VIDEO_CS53L32A=m
-CONFIG_VIDEO_TLV320AIC23B=m
-CONFIG_VIDEO_UDA1342=m
-CONFIG_VIDEO_WM8775=m
-CONFIG_VIDEO_WM8739=m
-CONFIG_VIDEO_VP27SMPX=m
-CONFIG_VIDEO_SONY_BTF_MPX=m
-# end of Audio decoders, processors and mixers
-
-#
-# RDS decoders
-#
-CONFIG_VIDEO_SAA6588=m
-# end of RDS decoders
-
-#
-# Video decoders
-#
-CONFIG_VIDEO_ADV7180=m
-CONFIG_VIDEO_ADV7183=m
-CONFIG_VIDEO_ADV748X=m
-CONFIG_VIDEO_ADV7604=m
-CONFIG_VIDEO_ADV7604_CEC=y
-CONFIG_VIDEO_ADV7842=m
-CONFIG_VIDEO_ADV7842_CEC=y
-CONFIG_VIDEO_BT819=m
-CONFIG_VIDEO_BT856=m
-CONFIG_VIDEO_BT866=m
-CONFIG_VIDEO_ISL7998X=m
-CONFIG_VIDEO_KS0127=m
-CONFIG_VIDEO_ML86V7667=m
-CONFIG_VIDEO_SAA7110=m
-CONFIG_VIDEO_SAA711X=m
-CONFIG_VIDEO_TC358743=m
-CONFIG_VIDEO_TC358743_CEC=y
-CONFIG_VIDEO_TVP514X=m
-CONFIG_VIDEO_TVP5150=m
-CONFIG_VIDEO_TVP7002=m
-CONFIG_VIDEO_TW2804=m
-CONFIG_VIDEO_TW9903=m
-CONFIG_VIDEO_TW9906=m
-CONFIG_VIDEO_TW9910=m
-CONFIG_VIDEO_VPX3220=m
-CONFIG_VIDEO_MAX9286=m
-
-#
-# Video and audio decoders
-#
-CONFIG_VIDEO_SAA717X=m
-CONFIG_VIDEO_CX25840=m
-# end of Video decoders
-
-#
-# Video encoders
-#
-CONFIG_VIDEO_SAA7127=m
-CONFIG_VIDEO_SAA7185=m
-CONFIG_VIDEO_ADV7170=m
-CONFIG_VIDEO_ADV7175=m
-CONFIG_VIDEO_ADV7343=m
-CONFIG_VIDEO_ADV7393=m
-CONFIG_VIDEO_AD9389B=m
-CONFIG_VIDEO_AK881X=m
-CONFIG_VIDEO_THS8200=m
-# end of Video encoders
-
-#
-# Video improvement chips
-#
-CONFIG_VIDEO_UPD64031A=m
-CONFIG_VIDEO_UPD64083=m
-# end of Video improvement chips
-
-#
-# Audio/Video compression chips
-#
-CONFIG_VIDEO_SAA6752HS=m
-# end of Audio/Video compression chips
-
-#
-# SDR tuner chips
-#
-# CONFIG_SDR_MAX2175 is not set
-# end of SDR tuner chips
-
-#
-# Miscellaneous helper chips
-#
-CONFIG_VIDEO_THS7303=m
-CONFIG_VIDEO_M52790=m
-CONFIG_VIDEO_I2C=m
-# CONFIG_VIDEO_ST_MIPID02 is not set
-# end of Miscellaneous helper chips
-
-#
-# Camera sensor devices
-#
-CONFIG_VIDEO_CCS_PLL=m
-# CONFIG_VIDEO_HI556 is not set
-CONFIG_VIDEO_HI846=m
-CONFIG_VIDEO_HI847=m
-CONFIG_VIDEO_IMX208=m
-CONFIG_VIDEO_IMX214=m
-# CONFIG_VIDEO_IMX219 is not set
-# CONFIG_VIDEO_IMX258 is not set
-# CONFIG_VIDEO_IMX274 is not set
-# CONFIG_VIDEO_IMX290 is not set
-# CONFIG_VIDEO_IMX319 is not set
-CONFIG_VIDEO_IMX334=m
-CONFIG_VIDEO_IMX335=m
-# CONFIG_VIDEO_IMX355 is not set
-CONFIG_VIDEO_IMX412=m
-CONFIG_VIDEO_OV02A10=m
-CONFIG_VIDEO_OV08D10=m
-CONFIG_VIDEO_OV2640=m
-# CONFIG_VIDEO_OV2659 is not set
-# CONFIG_VIDEO_OV2680 is not set
-# CONFIG_VIDEO_OV2685 is not set
-# CONFIG_VIDEO_OV2740 is not set
-# CONFIG_VIDEO_OV5640 is not set
-# CONFIG_VIDEO_OV5645 is not set
-# CONFIG_VIDEO_OV5647 is not set
-CONFIG_VIDEO_OV5648=m
-# CONFIG_VIDEO_OV6650 is not set
-# CONFIG_VIDEO_OV5670 is not set
-# CONFIG_VIDEO_OV5675 is not set
-# CONFIG_VIDEO_OV5695 is not set
-# CONFIG_VIDEO_OV7251 is not set
-# CONFIG_VIDEO_OV772X is not set
-# CONFIG_VIDEO_OV7640 is not set
-CONFIG_VIDEO_OV7670=m
-# CONFIG_VIDEO_OV7740 is not set
-# CONFIG_VIDEO_OV8856 is not set
-CONFIG_VIDEO_OV8865=m
-CONFIG_VIDEO_OV9282=m
-# CONFIG_VIDEO_OV9640 is not set
-# CONFIG_VIDEO_OV9650 is not set
-CONFIG_VIDEO_OV9734=m
-# CONFIG_VIDEO_OV13858 is not set
-CONFIG_VIDEO_OV13B10=m
-# CONFIG_VIDEO_VS6624 is not set
-# CONFIG_VIDEO_MT9M001 is not set
-# CONFIG_VIDEO_MT9M032 is not set
-# CONFIG_VIDEO_MT9M111 is not set
-# CONFIG_VIDEO_MT9P031 is not set
-# CONFIG_VIDEO_MT9T001 is not set
-# CONFIG_VIDEO_MT9T112 is not set
-CONFIG_VIDEO_MT9V011=m
-# CONFIG_VIDEO_MT9V032 is not set
-# CONFIG_VIDEO_MT9V111 is not set
-# CONFIG_VIDEO_SR030PC30 is not set
-# CONFIG_VIDEO_NOON010PC30 is not set
-CONFIG_VIDEO_OG01A1B=m
-# CONFIG_VIDEO_M5MOLS is not set
-CONFIG_VIDEO_MAX9271_LIB=m
-CONFIG_VIDEO_RDACM20=m
-CONFIG_VIDEO_RDACM21=m
-# CONFIG_VIDEO_RJ54N1 is not set
-# CONFIG_VIDEO_S5K6AA is not set
-# CONFIG_VIDEO_S5K6A3 is not set
-# CONFIG_VIDEO_S5K4ECGX is not set
-# CONFIG_VIDEO_S5K5BAF is not set
-CONFIG_VIDEO_CCS=m
-# CONFIG_VIDEO_ET8EK8 is not set
-# CONFIG_VIDEO_S5C73M3 is not set
-# end of Camera sensor devices
-
-#
-# Lens drivers
-#
-# CONFIG_VIDEO_AD5820 is not set
-# CONFIG_VIDEO_AK7375 is not set
-# CONFIG_VIDEO_DW9714 is not set
-CONFIG_VIDEO_DW9768=m
-# CONFIG_VIDEO_DW9807_VCM is not set
-# end of Lens drivers
-
-#
-# Flash devices
-#
-# CONFIG_VIDEO_ADP1653 is not set
-# CONFIG_VIDEO_LM3560 is not set
-# CONFIG_VIDEO_LM3646 is not set
-# end of Flash devices
-
-#
-# SPI helper chips
-#
-# CONFIG_VIDEO_GS1662 is not set
-# end of SPI helper chips
-
-#
-# Media SPI Adapters
-#
-# CONFIG_CXD2880_SPI_DRV is not set
-# end of Media SPI Adapters
-
-CONFIG_MEDIA_TUNER=m
-
-#
-# Customize TV tuners
-#
-CONFIG_MEDIA_TUNER_SIMPLE=m
-CONFIG_MEDIA_TUNER_TDA18250=m
-CONFIG_MEDIA_TUNER_TDA8290=m
-CONFIG_MEDIA_TUNER_TDA827X=m
-CONFIG_MEDIA_TUNER_TDA18271=m
-CONFIG_MEDIA_TUNER_TDA9887=m
-CONFIG_MEDIA_TUNER_TEA5761=m
-CONFIG_MEDIA_TUNER_TEA5767=m
-# CONFIG_MEDIA_TUNER_MSI001 is not set
-CONFIG_MEDIA_TUNER_MT20XX=m
-CONFIG_MEDIA_TUNER_MT2060=m
-CONFIG_MEDIA_TUNER_MT2063=m
-CONFIG_MEDIA_TUNER_MT2266=m
-CONFIG_MEDIA_TUNER_MT2131=m
-CONFIG_MEDIA_TUNER_QT1010=m
-CONFIG_MEDIA_TUNER_XC2028=m
-CONFIG_MEDIA_TUNER_XC5000=m
-CONFIG_MEDIA_TUNER_XC4000=m
-CONFIG_MEDIA_TUNER_MXL5005S=m
-CONFIG_MEDIA_TUNER_MXL5007T=m
-CONFIG_MEDIA_TUNER_MC44S803=m
-CONFIG_MEDIA_TUNER_MAX2165=m
-CONFIG_MEDIA_TUNER_TDA18218=m
-CONFIG_MEDIA_TUNER_FC0011=m
-CONFIG_MEDIA_TUNER_FC0012=m
-CONFIG_MEDIA_TUNER_FC0013=m
-CONFIG_MEDIA_TUNER_TDA18212=m
-CONFIG_MEDIA_TUNER_E4000=m
-CONFIG_MEDIA_TUNER_FC2580=m
-CONFIG_MEDIA_TUNER_M88RS6000T=m
-CONFIG_MEDIA_TUNER_TUA9001=m
-CONFIG_MEDIA_TUNER_SI2157=m
-CONFIG_MEDIA_TUNER_IT913X=m
-CONFIG_MEDIA_TUNER_R820T=m
-# CONFIG_MEDIA_TUNER_MXL301RF is not set
-CONFIG_MEDIA_TUNER_QM1D1C0042=m
-# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
-CONFIG_MEDIA_TUNER_AV201X=m
-CONFIG_MEDIA_TUNER_STV6120=m
-# end of Customize TV tuners
-
-#
-# Customise DVB Frontends
-#
-
-#
-# Multistandard (satellite) frontends
-#
-CONFIG_DVB_STB0899=m
-CONFIG_DVB_STB6100=m
-CONFIG_DVB_STV090x=m
-# CONFIG_DVB_STV0910 is not set
-CONFIG_DVB_STV6110x=m
-# CONFIG_DVB_STV6111 is not set
-# CONFIG_DVB_MXL5XX is not set
-CONFIG_DVB_M88DS3103=m
-
-#
-# Multistandard (cable + terrestrial) frontends
-#
-CONFIG_DVB_DRXK=m
-CONFIG_DVB_TDA18271C2DD=m
-CONFIG_DVB_SI2165=m
-CONFIG_DVB_MN88472=m
-CONFIG_DVB_MN88473=m
-
-#
-# DVB-S (satellite) frontends
-#
-CONFIG_DVB_CX24110=m
-CONFIG_DVB_CX24123=m
-CONFIG_DVB_MT312=m
-CONFIG_DVB_ZL10036=m
-CONFIG_DVB_ZL10039=m
-CONFIG_DVB_S5H1420=m
-CONFIG_DVB_STV0288=m
-CONFIG_DVB_STB6000=m
-CONFIG_DVB_STV0299=m
-CONFIG_DVB_STV6110=m
-CONFIG_DVB_STV0900=m
-CONFIG_DVB_TDA8083=m
-CONFIG_DVB_TDA10086=m
-CONFIG_DVB_TDA8261=m
-CONFIG_DVB_VES1X93=m
-CONFIG_DVB_TUNER_ITD1000=m
-CONFIG_DVB_TUNER_CX24113=m
-CONFIG_DVB_TDA826X=m
-CONFIG_DVB_TUA6100=m
-CONFIG_DVB_CX24116=m
-CONFIG_DVB_CX24117=m
-CONFIG_DVB_CX24120=m
-CONFIG_DVB_SI21XX=m
-CONFIG_DVB_TS2020=m
-CONFIG_DVB_DS3000=m
-# CONFIG_DVB_MB86A16 is not set
-CONFIG_DVB_TDA10071=m
-
-#
-# DVB-T (terrestrial) frontends
-#
-CONFIG_DVB_SP887X=m
-CONFIG_DVB_CX22700=m
-CONFIG_DVB_CX22702=m
-CONFIG_DVB_S5H1432=m
-CONFIG_DVB_DRXD=m
-CONFIG_DVB_L64781=m
-CONFIG_DVB_TDA1004X=m
-CONFIG_DVB_NXT6000=m
-CONFIG_DVB_MT352=m
-CONFIG_DVB_ZL10353=m
-CONFIG_DVB_DIB3000MB=m
-CONFIG_DVB_DIB3000MC=m
-CONFIG_DVB_DIB7000M=m
-CONFIG_DVB_DIB7000P=m
-CONFIG_DVB_DIB9000=m
-CONFIG_DVB_TDA10048=m
-CONFIG_DVB_AF9013=m
-CONFIG_DVB_EC100=m
-CONFIG_DVB_STV0367=m
-CONFIG_DVB_CXD2820R=m
-CONFIG_DVB_CXD2841ER=m
-CONFIG_DVB_RTL2830=m
-CONFIG_DVB_RTL2832=m
-CONFIG_DVB_RTL2832_SDR=m
-CONFIG_DVB_SI2168=m
-# CONFIG_DVB_ZD1301_DEMOD is not set
-CONFIG_DVB_GP8PSK_FE=m
-CONFIG_DVB_CXD2880=m
-
-#
-# DVB-C (cable) frontends
-#
-CONFIG_DVB_VES1820=m
-CONFIG_DVB_TDA10021=m
-CONFIG_DVB_TDA10023=m
-CONFIG_DVB_STV0297=m
-
-#
-# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
-#
-CONFIG_DVB_NXT200X=m
-CONFIG_DVB_OR51211=m
-CONFIG_DVB_OR51132=m
-CONFIG_DVB_BCM3510=m
-CONFIG_DVB_LGDT330X=m
-CONFIG_DVB_LGDT3305=m
-CONFIG_DVB_LGDT3306A=m
-CONFIG_DVB_LG2160=m
-CONFIG_DVB_S5H1409=m
-CONFIG_DVB_AU8522=m
-CONFIG_DVB_AU8522_DTV=m
-CONFIG_DVB_AU8522_V4L=m
-CONFIG_DVB_S5H1411=m
-CONFIG_DVB_MXL692=m
-
-#
-# ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_S921=m
-CONFIG_DVB_DIB8000=m
-CONFIG_DVB_MB86A20S=m
-
-#
-# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_TC90522=m
-CONFIG_DVB_MN88443X=m
-
-#
-# Digital terrestrial only tuners/PLL
-#
-CONFIG_DVB_PLL=m
-CONFIG_DVB_TUNER_DIB0070=m
-CONFIG_DVB_TUNER_DIB0090=m
-
-#
-# SEC control devices for DVB-S
-#
-CONFIG_DVB_DRX39XYJ=m
-CONFIG_DVB_LNBH25=m
-# CONFIG_DVB_LNBH29 is not set
-CONFIG_DVB_LNBP21=m
-CONFIG_DVB_LNBP22=m
-CONFIG_DVB_ISL6405=m
-CONFIG_DVB_ISL6421=m
-CONFIG_DVB_ISL6422=m
-CONFIG_DVB_ISL6423=m
-CONFIG_DVB_A8293=m
-CONFIG_DVB_LGS8GL5=m
-CONFIG_DVB_LGS8GXX=m
-CONFIG_DVB_ATBM8830=m
-# CONFIG_DVB_TDA665x is not set
-CONFIG_DVB_IX2505V=m
-CONFIG_DVB_M88RS2000=m
-CONFIG_DVB_AF9033=m
-CONFIG_DVB_TAS2101=m
-CONFIG_DVB_HORUS3A=m
-CONFIG_DVB_ASCOT2E=m
-CONFIG_DVB_HELENE=m
-
-#
-# Common Interface (EN50221) controller drivers
-#
-# CONFIG_DVB_CXD2099 is not set
-# CONFIG_DVB_SP2 is not set
-# end of Customise DVB Frontends
-
-#
-# Tools to develop new frontends
-#
-# CONFIG_DVB_DUMMY_FE is not set
-# end of Media ancillary drivers
-
-#
-# Graphics support
-#
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=8
-CONFIG_TEGRA_HOST1X=m
-CONFIG_TEGRA_HOST1X_FIREWALL=y
-CONFIG_DRM=y
-CONFIG_DRM_MIPI_DBI=m
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_DP_AUX_BUS=m
-# CONFIG_DRM_DP_AUX_CHARDEV is not set
-# CONFIG_DRM_DEBUG_MM is not set
-# CONFIG_DRM_DEBUG_SELFTEST is not set
-CONFIG_DRM_KMS_HELPER=y
-# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
-# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
-CONFIG_DRM_LOAD_EDID_FIRMWARE=y
-# CONFIG_DRM_DP_CEC is not set
-CONFIG_DRM_TTM=m
-CONFIG_DRM_VRAM_HELPER=m
-CONFIG_DRM_TTM_HELPER=m
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-CONFIG_DRM_SCHED=m
-
-#
-# I2C encoder or helper chips
-#
-# CONFIG_DRM_I2C_CH7006 is not set
-# CONFIG_DRM_I2C_SIL164 is not set
-# CONFIG_DRM_I2C_NXP_TDA998X is not set
-# CONFIG_DRM_I2C_NXP_TDA9950 is not set
-# end of I2C encoder or helper chips
-
-#
-# ARM devices
-#
-CONFIG_DRM_HDLCD=m
-# CONFIG_DRM_HDLCD_SHOW_UNDERRUN is not set
-CONFIG_DRM_MALI_DISPLAY=m
-CONFIG_DRM_KOMEDA=m
-# end of ARM devices
-
-CONFIG_DRM_RADEON=m
-# CONFIG_DRM_RADEON_USERPTR is not set
-CONFIG_DRM_AMDGPU=m
-CONFIG_DRM_AMDGPU_SI=y
-CONFIG_DRM_AMDGPU_CIK=y
-CONFIG_DRM_AMDGPU_USERPTR=y
-
-#
-# ACP (Audio CoProcessor) Configuration
-#
-CONFIG_DRM_AMD_ACP=y
-# end of ACP (Audio CoProcessor) Configuration
-
-#
-# Display Engine Configuration
-#
-CONFIG_DRM_AMD_DC=y
-CONFIG_DRM_AMD_DC_HDCP=y
-CONFIG_DRM_AMD_DC_SI=y
-# end of Display Engine Configuration
-
-CONFIG_HSA_AMD=y
-CONFIG_DRM_NOUVEAU=m
-# CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT is not set
-CONFIG_NOUVEAU_PLATFORM_DRIVER=y
-CONFIG_NOUVEAU_DEBUG=5
-CONFIG_NOUVEAU_DEBUG_DEFAULT=3
-# CONFIG_NOUVEAU_DEBUG_MMU is not set
-# CONFIG_NOUVEAU_DEBUG_PUSH is not set
-# CONFIG_DRM_NOUVEAU_BACKLIGHT is not set
-CONFIG_DRM_KMB_DISPLAY=m
-CONFIG_DRM_VGEM=m
-CONFIG_DRM_VKMS=m
-CONFIG_DRM_EXYNOS=m
-
-#
-# CRTCs
-#
-CONFIG_DRM_EXYNOS_FIMD=y
-CONFIG_DRM_EXYNOS5433_DECON=y
-CONFIG_DRM_EXYNOS7_DECON=y
-CONFIG_DRM_EXYNOS_MIXER=y
-CONFIG_DRM_EXYNOS_VIDI=y
-
-#
-# Encoders and Bridges
-#
-CONFIG_DRM_EXYNOS_DPI=y
-CONFIG_DRM_EXYNOS_DSI=y
-CONFIG_DRM_EXYNOS_DP=y
-CONFIG_DRM_EXYNOS_HDMI=y
-CONFIG_DRM_EXYNOS_MIC=y
-
-#
-# Sub-drivers
-#
-CONFIG_DRM_EXYNOS_IPP=y
-CONFIG_DRM_EXYNOS_FIMC=y
-CONFIG_DRM_EXYNOS_ROTATOR=y
-CONFIG_DRM_EXYNOS_SCALER=y
-CONFIG_DRM_ROCKCHIP=y
-CONFIG_ROCKCHIP_VOP=y
-CONFIG_ROCKCHIP_VOP2=y
-CONFIG_ROCKCHIP_ANALOGIX_DP=y
-CONFIG_ROCKCHIP_CDN_DP=y
-CONFIG_ROCKCHIP_DW_HDMI=y
-CONFIG_ROCKCHIP_DW_MIPI_DSI=y
-CONFIG_ROCKCHIP_INNO_HDMI=y
-CONFIG_ROCKCHIP_LVDS=y
-CONFIG_ROCKCHIP_RGB=y
-CONFIG_ROCKCHIP_RK3066_HDMI=y
-CONFIG_DRM_VMWGFX=m
-CONFIG_DRM_VMWGFX_FBCON=y
-CONFIG_DRM_UDL=m
-# CONFIG_DRM_AST is not set
-# CONFIG_DRM_MGAG200 is not set
-CONFIG_DRM_RCAR_DU=m
-CONFIG_DRM_RCAR_USE_CMM=y
-CONFIG_DRM_RCAR_CMM=m
-CONFIG_DRM_RCAR_DW_HDMI=m
-CONFIG_DRM_RCAR_LVDS=m
-CONFIG_DRM_RCAR_VSP=y
-CONFIG_DRM_RCAR_WRITEBACK=y
-CONFIG_DRM_SUN4I=m
-CONFIG_DRM_SUN4I_HDMI=m
-CONFIG_DRM_SUN4I_HDMI_CEC=y
-CONFIG_DRM_SUN4I_BACKEND=m
-CONFIG_DRM_SUN6I_DSI=m
-CONFIG_DRM_SUN8I_DW_HDMI=m
-CONFIG_DRM_SUN8I_MIXER=m
-CONFIG_DRM_SUN8I_TCON_TOP=m
-# CONFIG_DRM_QXL is not set
-CONFIG_DRM_VIRTIO_GPU=m
-CONFIG_DRM_MSM=m
-CONFIG_DRM_MSM_GPU_STATE=y
-# CONFIG_DRM_MSM_REGISTER_LOGGING is not set
-# CONFIG_DRM_MSM_GPU_SUDO is not set
-CONFIG_DRM_MSM_MDP4=y
-CONFIG_DRM_MSM_MDP5=y
-CONFIG_DRM_MSM_DPU=y
-CONFIG_DRM_MSM_HDMI_HDCP=y
-CONFIG_DRM_MSM_DP=y
-CONFIG_DRM_MSM_DSI=y
-CONFIG_DRM_MSM_DSI_28NM_PHY=y
-CONFIG_DRM_MSM_DSI_20NM_PHY=y
-CONFIG_DRM_MSM_DSI_28NM_8960_PHY=y
-CONFIG_DRM_MSM_DSI_14NM_PHY=y
-CONFIG_DRM_MSM_DSI_10NM_PHY=y
-CONFIG_DRM_MSM_DSI_7NM_PHY=y
-CONFIG_DRM_MSM_HDMI=y
-CONFIG_DRM_TEGRA=m
-# CONFIG_DRM_TEGRA_DEBUG is not set
-CONFIG_DRM_TEGRA_STAGING=y
-CONFIG_DRM_PANEL=y
-
-#
-# Display Panels
-#
-CONFIG_DRM_PANEL_ABT_Y030XX067A=m
-CONFIG_DRM_PANEL_ARM_VERSATILE=m
-CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
-CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
-CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
-CONFIG_DRM_PANEL_DSI_CM=m
-CONFIG_DRM_PANEL_LVDS=m
-CONFIG_DRM_PANEL_SIMPLE=m
-CONFIG_DRM_PANEL_EDP=m
-CONFIG_DRM_PANEL_ELIDA_KD35T133=m
-CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
-CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
-CONFIG_DRM_PANEL_ILITEK_IL9322=m
-CONFIG_DRM_PANEL_ILITEK_ILI9341=m
-CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
-CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
-CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
-CONFIG_DRM_PANEL_JDI_LT070ME05000=m
-CONFIG_DRM_PANEL_KHADAS_TS050=m
-CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
-CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
-CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
-CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
-CONFIG_DRM_PANEL_LG_LB035Q02=m
-CONFIG_DRM_PANEL_LG_LG4573=m
-CONFIG_DRM_PANEL_NEC_NL8048HL11=m
-CONFIG_DRM_PANEL_NOVATEK_NT35510=m
-CONFIG_DRM_PANEL_NOVATEK_NT35560=m
-CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
-CONFIG_DRM_PANEL_NOVATEK_NT39016=m
-CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
-CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
-CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
-CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
-CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
-CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
-CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
-CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
-CONFIG_DRM_PANEL_RONBO_RB070D30=m
-CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
-CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
-CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
-CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
-CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
-CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
-CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
-CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
-CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
-CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
-CONFIG_DRM_PANEL_SITRONIX_ST7701=m
-CONFIG_DRM_PANEL_SITRONIX_ST7703=m
-CONFIG_DRM_PANEL_SITRONIX_ST7789V=m
-CONFIG_DRM_PANEL_SONY_ACX424AKP=m
-CONFIG_DRM_PANEL_SONY_ACX565AKM=m
-CONFIG_DRM_PANEL_TDO_TL070WSH30=m
-CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
-CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
-CONFIG_DRM_PANEL_TPO_TPG110=m
-CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
-CONFIG_DRM_PANEL_VISIONOX_RM69299=m
-CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
-CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
-# end of Display Panels
-
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_PANEL_BRIDGE=y
-
-#
-# Display Interface Bridges
-#
-CONFIG_DRM_CDNS_DSI=m
-CONFIG_DRM_CHIPONE_ICN6211=m
-CONFIG_DRM_CHRONTEL_CH7033=m
-CONFIG_DRM_CROS_EC_ANX7688=m
-CONFIG_DRM_DISPLAY_CONNECTOR=m
-CONFIG_DRM_ITE_IT6505=m
-CONFIG_DRM_LONTIUM_LT8912B=m
-CONFIG_DRM_LONTIUM_LT9611=m
-CONFIG_DRM_LONTIUM_LT9611UXC=m
-CONFIG_DRM_ITE_IT66121=m
-CONFIG_DRM_LVDS_CODEC=m
-CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m
-CONFIG_DRM_NWL_MIPI_DSI=m
-CONFIG_DRM_NXP_PTN3460=m
-CONFIG_DRM_PARADE_PS8622=m
-CONFIG_DRM_PARADE_PS8640=m
-CONFIG_DRM_SIL_SII8620=m
-CONFIG_DRM_SII902X=m
-CONFIG_DRM_SII9234=m
-CONFIG_DRM_SIMPLE_BRIDGE=m
-CONFIG_DRM_THINE_THC63LVD1024=m
-CONFIG_DRM_TOSHIBA_TC358762=m
-CONFIG_DRM_TOSHIBA_TC358764=m
-CONFIG_DRM_TOSHIBA_TC358767=m
-CONFIG_DRM_TOSHIBA_TC358768=m
-CONFIG_DRM_TOSHIBA_TC358775=m
-CONFIG_DRM_TI_TFP410=m
-CONFIG_DRM_TI_SN65DSI83=m
-CONFIG_DRM_TI_SN65DSI86=m
-CONFIG_DRM_TI_TPD12S015=m
-CONFIG_DRM_ANALOGIX_ANX6345=m
-CONFIG_DRM_ANALOGIX_ANX78XX=m
-CONFIG_DRM_ANALOGIX_DP=y
-CONFIG_DRM_ANALOGIX_ANX7625=m
-CONFIG_DRM_I2C_ADV7511=m
-CONFIG_DRM_I2C_ADV7511_AUDIO=y
-CONFIG_DRM_I2C_ADV7511_CEC=y
-CONFIG_DRM_CDNS_MHDP8546=m
-CONFIG_DRM_CDNS_MHDP8546_J721E=y
-CONFIG_DRM_DW_HDMI=y
-CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
-CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
-CONFIG_DRM_DW_HDMI_CEC=m
-CONFIG_DRM_DW_MIPI_DSI=y
-# end of Display Interface Bridges
-
-CONFIG_DRM_IMX_DCSS=m
-CONFIG_DRM_V3D=m
-CONFIG_DRM_VC4=m
-CONFIG_DRM_VC4_HDMI_CEC=y
-CONFIG_DRM_ETNAVIV=m
-CONFIG_DRM_ETNAVIV_THERMAL=y
-CONFIG_DRM_HISI_HIBMC=m
-CONFIG_DRM_HISI_KIRIN=m
-CONFIG_DRM_LOGICVC=m
-CONFIG_DRM_MEDIATEK=m
-CONFIG_DRM_MEDIATEK_DP=m
-CONFIG_DRM_MEDIATEK_HDMI=m
-CONFIG_DRM_MXS=y
-CONFIG_DRM_MXSFB=m
-CONFIG_DRM_IMX_LCDIF=m
-CONFIG_DRM_MESON=m
-CONFIG_DRM_MESON_DW_HDMI=m
-CONFIG_DRM_ARCPGU=m
-CONFIG_DRM_BOCHS=m
-CONFIG_DRM_CIRRUS_QEMU=m
-CONFIG_DRM_GM12U320=m
-CONFIG_DRM_PANEL_MIPI_DBI=m
-CONFIG_DRM_SIMPLEDRM=y
-CONFIG_TINYDRM_HX8357D=m
-CONFIG_TINYDRM_ILI9225=m
-CONFIG_TINYDRM_ILI9341=m
-CONFIG_TINYDRM_ILI9486=m
-CONFIG_TINYDRM_MI0283QT=m
-CONFIG_TINYDRM_REPAPER=m
-CONFIG_TINYDRM_ST7586=m
-CONFIG_TINYDRM_ST7735R=m
-CONFIG_DRM_PL111=m
-CONFIG_DRM_LIMA=m
-CONFIG_DRM_PANFROST=y
-CONFIG_DRM_TIDSS=m
-CONFIG_DRM_ZYNQMP_DPSUB=m
-CONFIG_DRM_GUD=m
-CONFIG_DRM_SSD130X=m
-CONFIG_DRM_SSD130X_I2C=m
-CONFIG_DRM_SPRD=m
-CONFIG_DRM_HYPERV=m
-# CONFIG_DRM_LEGACY is not set
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-
-#
-# Frame buffer Devices
-#
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_NOTIFY=y
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_BACKLIGHT=m
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_CIRRUS is not set
-# CONFIG_FB_PM2 is not set
-# CONFIG_FB_ARMCLCD is not set
-# CONFIG_FB_IMX is not set
-# CONFIG_FB_CYBER2000 is not set
-# CONFIG_FB_ASILIANT is not set
-# CONFIG_FB_IMSTT is not set
-# CONFIG_FB_UVESA is not set
-# CONFIG_FB_EFI is not set
-# CONFIG_FB_OPENCORES is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-# CONFIG_FB_I740 is not set
-# CONFIG_FB_MATROX is not set
-# CONFIG_FB_RADEON is not set
-# CONFIG_FB_ATY128 is not set
-# CONFIG_FB_ATY is not set
-# CONFIG_FB_S3 is not set
-# CONFIG_FB_SAVAGE is not set
-# CONFIG_FB_SIS is not set
-# CONFIG_FB_NEOMAGIC is not set
-# CONFIG_FB_KYRO is not set
-# CONFIG_FB_3DFX is not set
-# CONFIG_FB_VOODOO1 is not set
-# CONFIG_FB_VT8623 is not set
-# CONFIG_FB_TRIDENT is not set
-# CONFIG_FB_ARK is not set
-# CONFIG_FB_PM3 is not set
-# CONFIG_FB_CARMINE is not set
-# CONFIG_FB_SH_MOBILE_LCDC is not set
-# CONFIG_FB_SMSCUFX is not set
-# CONFIG_FB_UDL is not set
-# CONFIG_FB_IBM_GXT4500 is not set
-# CONFIG_FB_XILINX is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-# CONFIG_FB_MX3 is not set
-# CONFIG_FB_HYPERV is not set
-# CONFIG_FB_SSD1307 is not set
-# CONFIG_FB_SM712 is not set
-# end of Frame buffer Devices
-
-#
-# Backlight & LCD device support
-#
-CONFIG_LCD_CLASS_DEVICE=m
-CONFIG_LCD_L4F00242T03=m
-CONFIG_LCD_LMS283GF05=m
-CONFIG_LCD_LTV350QV=m
-CONFIG_LCD_ILI922X=m
-CONFIG_LCD_ILI9320=m
-CONFIG_LCD_TDO24M=m
-CONFIG_LCD_VGG2432A4=m
-CONFIG_LCD_PLATFORM=m
-CONFIG_LCD_AMS369FG06=m
-CONFIG_LCD_LMS501KF03=m
-CONFIG_LCD_HX8357=m
-CONFIG_LCD_OTM3225A=m
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_KTD253=m
-CONFIG_BACKLIGHT_PWM=m
-CONFIG_BACKLIGHT_MT6370=m
-CONFIG_BACKLIGHT_QCOM_WLED=m
-CONFIG_BACKLIGHT_RT4831=m
-CONFIG_BACKLIGHT_ADP8860=m
-CONFIG_BACKLIGHT_ADP8870=m
-CONFIG_BACKLIGHT_LM3630A=m
-CONFIG_BACKLIGHT_LM3639=m
-CONFIG_BACKLIGHT_LP855X=m
-CONFIG_BACKLIGHT_GPIO=m
-CONFIG_BACKLIGHT_LV5207LP=m
-CONFIG_BACKLIGHT_BD6107=m
-CONFIG_BACKLIGHT_ARCXCNN=m
-CONFIG_BACKLIGHT_LED=m
-# end of Backlight & LCD device support
-
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_HDMI=y
-
-#
-# Console display driver support
-#
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DUMMY_CONSOLE_COLUMNS=80
-CONFIG_DUMMY_CONSOLE_ROWS=25
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
-# end of Console display driver support
-
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LINUX_CLUT224=y
-# end of Graphics support
-
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_PCM_ELD=y
-CONFIG_SND_PCM_IEC958=y
-CONFIG_SND_DMAENGINE_PCM=y
-CONFIG_SND_HWDEP=m
-CONFIG_SND_SEQ_DEVICE=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_COMPRESS_OFFLOAD=y
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_PCM_TIMER=y
-CONFIG_SND_HRTIMER=m
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_MAX_CARDS=32
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_PROC_FS=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-CONFIG_SND_CTL_FAST_LOOKUP=y
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_CTL_INPUT_VALIDATION=y
-CONFIG_SND_VMASTER=y
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_SEQUENCER_OSS=m
-CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
-CONFIG_SND_SEQ_MIDI_EVENT=m
-CONFIG_SND_SEQ_MIDI=m
-CONFIG_SND_SEQ_VIRMIDI=m
-CONFIG_SND_MPU401_UART=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DRIVERS=y
-CONFIG_SND_DUMMY=m
-# CONFIG_SND_ALOOP is not set
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_MTS64=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_PORTMAN2X4=m
-CONFIG_SND_AC97_POWER_SAVE=y
-CONFIG_SND_AC97_POWER_SAVE_DEFAULT=10
-# CONFIG_SND_PCI is not set
-
-#
-# HD-Audio
-#
-CONFIG_SND_HDA=m
-CONFIG_SND_HDA_TEGRA=m
-# CONFIG_SND_HDA_HWDEP is not set
-# CONFIG_SND_HDA_RECONFIG is not set
-# CONFIG_SND_HDA_INPUT_BEEP is not set
-# CONFIG_SND_HDA_PATCH_LOADER is not set
-CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m
-CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m
-# CONFIG_SND_HDA_CODEC_REALTEK is not set
-# CONFIG_SND_HDA_CODEC_ANALOG is not set
-# CONFIG_SND_HDA_CODEC_SIGMATEL is not set
-# CONFIG_SND_HDA_CODEC_VIA is not set
-# CONFIG_SND_HDA_CODEC_HDMI is not set
-# CONFIG_SND_HDA_CODEC_CIRRUS is not set
-CONFIG_SND_HDA_CODEC_CS8409=m
-# CONFIG_SND_HDA_CODEC_CONEXANT is not set
-# CONFIG_SND_HDA_CODEC_CA0110 is not set
-# CONFIG_SND_HDA_CODEC_CA0132 is not set
-# CONFIG_SND_HDA_CODEC_CMEDIA is not set
-# CONFIG_SND_HDA_CODEC_SI3054 is not set
-CONFIG_SND_HDA_GENERIC=m
-CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
-# end of HD-Audio
-
-CONFIG_SND_HDA_CORE=m
-CONFIG_SND_HDA_ALIGNED_MMIO=y
-CONFIG_SND_HDA_COMPONENT=y
-CONFIG_SND_HDA_PREALLOC_SIZE=2048
-CONFIG_SND_SPI=y
-CONFIG_SND_USB=y
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
-# CONFIG_SND_USB_UA101 is not set
-CONFIG_SND_USB_CAIAQ=m
-# CONFIG_SND_USB_CAIAQ_INPUT is not set
-CONFIG_SND_USB_6FIRE=m
-# CONFIG_SND_USB_HIFACE is not set
-# CONFIG_SND_BCD2000 is not set
-# CONFIG_SND_USB_POD is not set
-# CONFIG_SND_USB_PODHD is not set
-# CONFIG_SND_USB_TONEPORT is not set
-# CONFIG_SND_USB_VARIAX is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_AC97_BUS=y
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_COMPRESS=y
-CONFIG_SND_SOC_TOPOLOGY=y
-CONFIG_SND_SOC_ADI=m
-CONFIG_SND_SOC_ADI_AXI_I2S=m
-CONFIG_SND_SOC_ADI_AXI_SPDIF=m
-# CONFIG_SND_SOC_AMD_ACP is not set
-CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m
-CONFIG_SND_ATMEL_SOC=m
-# CONFIG_SND_SOC_MIKROE_PROTO is not set
-CONFIG_SND_BCM2835_SOC_I2S=m
-# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
-CONFIG_SND_DESIGNWARE_I2S=m
-# CONFIG_SND_DESIGNWARE_PCM is not set
-
-#
-# SoC Audio for Freescale CPUs
-#
-
-#
-# Common SoC Audio options for Freescale CPUs:
-#
-# CONFIG_SND_SOC_FSL_ASRC is not set
-CONFIG_SND_SOC_FSL_SAI=m
-CONFIG_SND_SOC_FSL_MQS=m
-CONFIG_SND_SOC_FSL_AUDMIX=m
-CONFIG_SND_SOC_FSL_SSI=m
-CONFIG_SND_SOC_FSL_SPDIF=m
-# CONFIG_SND_SOC_FSL_ESAI is not set
-# CONFIG_SND_SOC_FSL_MICFIL is not set
-CONFIG_SND_SOC_FSL_XCVR=m
-CONFIG_SND_SOC_FSL_AUD2HTX=m
-CONFIG_SND_SOC_FSL_RPMSG=m
-CONFIG_SND_SOC_IMX_PCM_DMA=m
-CONFIG_SND_SOC_IMX_AUDIO_RPMSG=m
-CONFIG_SND_SOC_IMX_PCM_RPMSG=m
-CONFIG_SND_SOC_IMX_AUDMUX=m
-CONFIG_SND_IMX_SOC=m
-
-#
-# SoC Audio support for Freescale i.MX boards:
-#
-CONFIG_SND_SOC_IMX_ES8328=m
-CONFIG_SND_SOC_IMX_SGTL5000=m
-CONFIG_SND_SOC_IMX_SPDIF=m
-# CONFIG_SND_SOC_FSL_ASOC_CARD is not set
-CONFIG_SND_SOC_IMX_AUDMIX=m
-CONFIG_SND_SOC_IMX_HDMI=m
-CONFIG_SND_SOC_IMX_RPMSG=m
-CONFIG_SND_SOC_IMX_CARD=m
-# end of SoC Audio for Freescale CPUs
-
-CONFIG_SND_I2S_HI6210_I2S=m
-# CONFIG_SND_KIRKWOOD_SOC is not set
-# CONFIG_SND_SOC_IMG is not set
-CONFIG_SND_SOC_INTEL_KEEMBAY=m
-CONFIG_SND_SOC_INTEL_AVS=m
-CONFIG_SND_SOC_MEDIATEK=m
-CONFIG_SND_SOC_MT2701=m
-CONFIG_SND_SOC_MT2701_CS42448=m
-CONFIG_SND_SOC_MT2701_WM8960=m
-CONFIG_SND_SOC_MT6797=m
-# CONFIG_SND_SOC_MT6797_MT6351 is not set
-CONFIG_SND_SOC_MT8173=m
-CONFIG_SND_SOC_MT8173_MAX98090=m
-CONFIG_SND_SOC_MT8173_RT5650=m
-CONFIG_SND_SOC_MT8173_RT5650_RT5514=m
-CONFIG_SND_SOC_MT8173_RT5650_RT5676=m
-CONFIG_SND_SOC_MT8183=m
-CONFIG_SND_SOC_MT8186=m
-CONFIG_SND_SOC_MT8186_MT6366_DA7219_MAX98357=m
-CONFIG_SND_SOC_MT8186_MT6366_RT1019_RT5682S=m
-CONFIG_SND_SOC_MT8183_MT6358_TS3A227E_MAX98357A=m
-CONFIG_SND_SOC_MT8183_DA7219_MAX98357A=m
-CONFIG_SND_SOC_MTK_BTCVSD=m
-CONFIG_SND_SOC_MT8192=m
-# CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682 is not set
-CONFIG_SND_SOC_MT8195=m
-CONFIG_SND_SOC_MT8195_MT6359=m
-# CONFIG_SND_SOC_MT8195_MT6359_RT1019_RT5682 is not set
-# CONFIG_SND_SOC_MT8195_MT6359_RT1011_RT5682 is not set
-
-#
-# ASoC support for Amlogic platforms
-#
-# CONFIG_SND_MESON_AIU is not set
-# CONFIG_SND_MESON_AXG_FRDDR is not set
-# CONFIG_SND_MESON_AXG_TODDR is not set
-# CONFIG_SND_MESON_AXG_TDMIN is not set
-# CONFIG_SND_MESON_AXG_TDMOUT is not set
-# CONFIG_SND_MESON_AXG_SOUND_CARD is not set
-# CONFIG_SND_MESON_AXG_SPDIFOUT is not set
-# CONFIG_SND_MESON_AXG_SPDIFIN is not set
-# CONFIG_SND_MESON_AXG_PDM is not set
-# CONFIG_SND_MESON_GX_SOUND_CARD is not set
-# CONFIG_SND_MESON_G12A_TOACODEC is not set
-# CONFIG_SND_MESON_G12A_TOHDMITX is not set
-# CONFIG_SND_SOC_MESON_T9015 is not set
-# end of ASoC support for Amlogic platforms
-
-CONFIG_SND_SOC_QCOM=m
-CONFIG_SND_SOC_LPASS_CPU=m
-CONFIG_SND_SOC_LPASS_HDMI=m
-CONFIG_SND_SOC_LPASS_PLATFORM=m
-CONFIG_SND_SOC_LPASS_IPQ806X=m
-CONFIG_SND_SOC_LPASS_APQ8016=m
-CONFIG_SND_SOC_LPASS_SC7180=m
-CONFIG_SND_SOC_STORM=m
-CONFIG_SND_SOC_APQ8016_SBC=m
-CONFIG_SND_SOC_QCOM_COMMON=m
-CONFIG_SND_SOC_QDSP6_COMMON=m
-CONFIG_SND_SOC_QDSP6_CORE=m
-CONFIG_SND_SOC_QDSP6_AFE=m
-CONFIG_SND_SOC_QDSP6_AFE_DAI=m
-CONFIG_SND_SOC_QDSP6_AFE_CLOCKS=m
-CONFIG_SND_SOC_QDSP6_ADM=m
-CONFIG_SND_SOC_QDSP6_ROUTING=m
-CONFIG_SND_SOC_QDSP6_ASM=m
-CONFIG_SND_SOC_QDSP6_ASM_DAI=m
-CONFIG_SND_SOC_QDSP6_APM_DAI=m
-CONFIG_SND_SOC_QDSP6_APM_LPASS_DAI=m
-CONFIG_SND_SOC_QDSP6_APM=m
-CONFIG_SND_SOC_QDSP6_PRM_LPASS_CLOCKS=m
-CONFIG_SND_SOC_QDSP6_PRM=m
-CONFIG_SND_SOC_QDSP6=m
-CONFIG_SND_SOC_MSM8996=m
-CONFIG_SND_SOC_SDM845=m
-CONFIG_SND_SOC_SM8250=m
-CONFIG_SND_SOC_SC8280XP=m
-CONFIG_SND_SOC_SC7180=m
-CONFIG_SND_SOC_SC7280=m
-CONFIG_SND_SOC_ROCKCHIP=y
-CONFIG_SND_SOC_ROCKCHIP_I2S=y
-CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
-CONFIG_SND_SOC_ROCKCHIP_PDM=m
-CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
-CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
-CONFIG_SND_SOC_ROCKCHIP_RT5645=m
-CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
-CONFIG_SND_SOC_RK3399_GRU_SOUND=m
-CONFIG_SND_SOC_SAMSUNG=y
-CONFIG_SND_SAMSUNG_PCM=m
-CONFIG_SND_SAMSUNG_SPDIF=m
-CONFIG_SND_SAMSUNG_I2S=m
-CONFIG_SND_SOC_SAMSUNG_SMDK_WM8994=m
-CONFIG_SND_SOC_SAMSUNG_SMDK_SPDIF=m
-CONFIG_SND_SOC_SMDK_WM8994_PCM=m
-CONFIG_SND_SOC_SNOW=m
-CONFIG_SND_SOC_ODROID=m
-CONFIG_SND_SOC_ARNDALE=m
-CONFIG_SND_SOC_SAMSUNG_ARIES_WM8994=m
-CONFIG_SND_SOC_SAMSUNG_MIDAS_WM1811=m
-
-#
-# SoC Audio support for Renesas SoCs
-#
-# CONFIG_SND_SOC_SH4_FSI is not set
-CONFIG_SND_SOC_RCAR=m
-CONFIG_SND_SOC_RZ=m
-# end of SoC Audio support for Renesas SoCs
-
-# CONFIG_SND_SOC_SOF_TOPLEVEL is not set
-# CONFIG_SND_SOC_SPRD is not set
-
-#
-# STMicroelectronics STM32 SOC audio support
-#
-# end of STMicroelectronics STM32 SOC audio support
-
-#
-# Allwinner SoC Audio support
-#
-CONFIG_SND_SUN4I_CODEC=m
-CONFIG_SND_SUN8I_CODEC=m
-CONFIG_SND_SUN8I_CODEC_ANALOG=m
-CONFIG_SND_SUN50I_CODEC_ANALOG=m
-CONFIG_SND_SUN4I_I2S=m
-CONFIG_SND_SUN4I_SPDIF=m
-CONFIG_SND_SUN50I_DMIC=m
-CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m
-# end of Allwinner SoC Audio support
-
-CONFIG_SND_SOC_TEGRA=m
-CONFIG_SND_SOC_TEGRA20_AC97=m
-CONFIG_SND_SOC_TEGRA20_DAS=m
-CONFIG_SND_SOC_TEGRA20_I2S=m
-CONFIG_SND_SOC_TEGRA20_SPDIF=m
-# CONFIG_SND_SOC_TEGRA30_AHUB is not set
-# CONFIG_SND_SOC_TEGRA30_I2S is not set
-CONFIG_SND_SOC_TEGRA210_AHUB=m
-CONFIG_SND_SOC_TEGRA210_DMIC=m
-CONFIG_SND_SOC_TEGRA210_I2S=m
-CONFIG_SND_SOC_TEGRA210_OPE=m
-CONFIG_SND_SOC_TEGRA186_ASRC=m
-CONFIG_SND_SOC_TEGRA186_DSPK=m
-CONFIG_SND_SOC_TEGRA210_ADMAIF=m
-CONFIG_SND_SOC_TEGRA210_MVC=m
-CONFIG_SND_SOC_TEGRA210_SFC=m
-CONFIG_SND_SOC_TEGRA210_AMX=m
-CONFIG_SND_SOC_TEGRA210_ADX=m
-CONFIG_SND_SOC_TEGRA210_MIXER=m
-CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m
-CONFIG_SND_SOC_TEGRA_MACHINE_DRV=m
-CONFIG_SND_SOC_TEGRA_RT5640=m
-CONFIG_SND_SOC_TEGRA_WM8753=m
-CONFIG_SND_SOC_TEGRA_WM8903=m
-CONFIG_SND_SOC_TEGRA_WM9712=m
-CONFIG_SND_SOC_TEGRA_TRIMSLICE=m
-CONFIG_SND_SOC_TEGRA_ALC5632=m
-CONFIG_SND_SOC_TEGRA_MAX98090=m
-CONFIG_SND_SOC_TEGRA_RT5677=m
-CONFIG_SND_SOC_TEGRA_SGTL5000=m
-CONFIG_SND_SOC_UNIPHIER=m
-CONFIG_SND_SOC_UNIPHIER_AIO=m
-CONFIG_SND_SOC_UNIPHIER_LD11=m
-CONFIG_SND_SOC_UNIPHIER_PXS2=m
-# CONFIG_SND_SOC_UNIPHIER_EVEA_CODEC is not set
-# CONFIG_SND_SOC_XILINX_I2S is not set
-# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set
-# CONFIG_SND_SOC_XILINX_SPDIF is not set
-# CONFIG_SND_SOC_XTFPGA_I2S is not set
-CONFIG_SND_SOC_I2C_AND_SPI=y
-
-#
-# CODEC drivers
-#
-CONFIG_SND_SOC_WM_HUBS=m
-CONFIG_SND_SOC_AC97_CODEC=m
-CONFIG_SND_SOC_ADAU_UTILS=m
-CONFIG_SND_SOC_ADAU1372=m
-CONFIG_SND_SOC_ADAU1372_I2C=m
-CONFIG_SND_SOC_ADAU1372_SPI=m
-# CONFIG_SND_SOC_ADAU1701 is not set
-# CONFIG_SND_SOC_ADAU1761_I2C is not set
-# CONFIG_SND_SOC_ADAU1761_SPI is not set
-CONFIG_SND_SOC_ADAU7002=m
-# CONFIG_SND_SOC_ADAU7118_HW is not set
-# CONFIG_SND_SOC_ADAU7118_I2C is not set
-# CONFIG_SND_SOC_AK4104 is not set
-# CONFIG_SND_SOC_AK4118 is not set
-CONFIG_SND_SOC_AK4458=m
-# CONFIG_SND_SOC_AK4554 is not set
-CONFIG_SND_SOC_AK4613=m
-# CONFIG_SND_SOC_AK4642 is not set
-# CONFIG_SND_SOC_AK5386 is not set
-CONFIG_SND_SOC_AK5558=m
-CONFIG_SND_SOC_ALC5623=m
-CONFIG_SND_SOC_AW8738=m
-CONFIG_SND_SOC_ALC5632=m
-# CONFIG_SND_SOC_BD28623 is not set
-CONFIG_SND_SOC_BT_SCO=m
-CONFIG_SND_SOC_CROS_EC_CODEC=m
-# CONFIG_SND_SOC_CS35L32 is not set
-CONFIG_SND_SOC_CS35L33=m
-# CONFIG_SND_SOC_CS35L34 is not set
-# CONFIG_SND_SOC_CS35L35 is not set
-# CONFIG_SND_SOC_CS35L36 is not set
-CONFIG_SND_SOC_CS35L41_SPI=m
-CONFIG_SND_SOC_CS35L41_I2C=m
-# CONFIG_SND_SOC_CS42L42 is not set
-# CONFIG_SND_SOC_CS42L51_I2C is not set
-# CONFIG_SND_SOC_CS42L52 is not set
-# CONFIG_SND_SOC_CS42L56 is not set
-# CONFIG_SND_SOC_CS42L73 is not set
-CONFIG_SND_SOC_CS42L83=m
-CONFIG_SND_SOC_CS4234=m
-# CONFIG_SND_SOC_CS4265 is not set
-# CONFIG_SND_SOC_CS4270 is not set
-# CONFIG_SND_SOC_CS4271_I2C is not set
-# CONFIG_SND_SOC_CS4271_SPI is not set
-CONFIG_SND_SOC_CS42XX8=m
-CONFIG_SND_SOC_CS42XX8_I2C=m
-# CONFIG_SND_SOC_CS43130 is not set
-# CONFIG_SND_SOC_CS4341 is not set
-CONFIG_SND_SOC_CS4349=m
-CONFIG_SND_SOC_CS53L30=m
-CONFIG_SND_SOC_CX2072X=m
-# CONFIG_SND_SOC_DA7213 is not set
-CONFIG_SND_SOC_DA7219=m
-CONFIG_SND_SOC_DMIC=m
-CONFIG_SND_SOC_HDMI_CODEC=y
-# CONFIG_SND_SOC_ES7134 is not set
-# CONFIG_SND_SOC_ES7241 is not set
-CONFIG_SND_SOC_ES8316=m
-CONFIG_SND_SOC_ES8326=m
-CONFIG_SND_SOC_ES8328=m
-CONFIG_SND_SOC_ES8328_I2C=m
-CONFIG_SND_SOC_ES8328_SPI=m
-CONFIG_SND_SOC_GTM601=m
-CONFIG_SND_SOC_HDA=m
-CONFIG_SND_SOC_ICS43432=m
-# CONFIG_SND_SOC_INNO_RK3036 is not set
-# CONFIG_SND_SOC_MAX98088 is not set
-CONFIG_SND_SOC_MAX98090=m
-CONFIG_SND_SOC_MAX98095=m
-CONFIG_SND_SOC_MAX98357A=m
-CONFIG_SND_SOC_MAX98504=m
-# CONFIG_SND_SOC_MAX9867 is not set
-CONFIG_SND_SOC_MAX98927=m
-CONFIG_SND_SOC_MAX98520=m
-# CONFIG_SND_SOC_MAX98373_I2C is not set
-# CONFIG_SND_SOC_MAX98373_SDW is not set
-# CONFIG_SND_SOC_MAX98390 is not set
-CONFIG_SND_SOC_MAX9860=m
-# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set
-# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
-# CONFIG_SND_SOC_PCM1681 is not set
-# CONFIG_SND_SOC_PCM1789_I2C is not set
-# CONFIG_SND_SOC_PCM179X_I2C is not set
-# CONFIG_SND_SOC_PCM179X_SPI is not set
-# CONFIG_SND_SOC_PCM186X_I2C is not set
-# CONFIG_SND_SOC_PCM186X_SPI is not set
-# CONFIG_SND_SOC_PCM3060_I2C is not set
-# CONFIG_SND_SOC_PCM3060_SPI is not set
-# CONFIG_SND_SOC_PCM3168A_I2C is not set
-# CONFIG_SND_SOC_PCM3168A_SPI is not set
-CONFIG_SND_SOC_PCM5102A=m
-# CONFIG_SND_SOC_PCM512x_I2C is not set
-# CONFIG_SND_SOC_PCM512x_SPI is not set
-CONFIG_SND_SOC_RK3328=m
-CONFIG_SND_SOC_RK817=m
-CONFIG_SND_SOC_RL6231=m
-CONFIG_SND_SOC_RT1015=m
-CONFIG_SND_SOC_RT1015P=m
-# CONFIG_SND_SOC_RT1308_SDW is not set
-CONFIG_SND_SOC_RT1316_SDW=m
-CONFIG_SND_SOC_RT5514=m
-CONFIG_SND_SOC_RT5514_SPI=m
-# CONFIG_SND_SOC_RT5616 is not set
-CONFIG_SND_SOC_RT5631=m
-CONFIG_SND_SOC_RT5640=m
-CONFIG_SND_SOC_RT5645=m
-CONFIG_SND_SOC_RT5659=m
-CONFIG_SND_SOC_RT5663=m
-CONFIG_SND_SOC_RT5677=m
-CONFIG_SND_SOC_RT5677_SPI=m
-CONFIG_SND_SOC_RT5682=m
-CONFIG_SND_SOC_RT5682_I2C=m
-# CONFIG_SND_SOC_RT5682_SDW is not set
-# CONFIG_SND_SOC_RT700_SDW is not set
-# CONFIG_SND_SOC_RT711_SDW is not set
-CONFIG_SND_SOC_RT711_SDCA_SDW=m
-# CONFIG_SND_SOC_RT715_SDW is not set
-CONFIG_SND_SOC_RT715_SDCA_SDW=m
-CONFIG_SND_SOC_RT9120=m
-CONFIG_SND_SOC_SDW_MOCKUP=m
-CONFIG_SND_SOC_SGTL5000=m
-CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
-CONFIG_SND_SOC_SIMPLE_MUX=m
-CONFIG_SND_SOC_SPDIF=m
-CONFIG_SND_SOC_SRC4XXX_I2C=m
-# CONFIG_SND_SOC_SSM2305 is not set
-# CONFIG_SND_SOC_SSM2518 is not set
-# CONFIG_SND_SOC_SSM2602_SPI is not set
-# CONFIG_SND_SOC_SSM2602_I2C is not set
-# CONFIG_SND_SOC_SSM4567 is not set
-# CONFIG_SND_SOC_STA32X is not set
-# CONFIG_SND_SOC_STA350 is not set
-CONFIG_SND_SOC_STI_SAS=m
-# CONFIG_SND_SOC_TAS2552 is not set
-# CONFIG_SND_SOC_TAS2562 is not set
-CONFIG_SND_SOC_TAS2764=m
-# CONFIG_SND_SOC_TAS2770 is not set
-CONFIG_SND_SOC_TAS2780=m
-CONFIG_SND_SOC_WSA883X=m
-# CONFIG_SND_SOC_TAS5086 is not set
-# CONFIG_SND_SOC_TAS571X is not set
-# CONFIG_SND_SOC_TAS5720 is not set
-CONFIG_SND_SOC_TAS5805M=m
-# CONFIG_SND_SOC_TAS6424 is not set
-# CONFIG_SND_SOC_TDA7419 is not set
-# CONFIG_SND_SOC_TFA9879 is not set
-CONFIG_SND_SOC_TFA989X=m
-CONFIG_SND_SOC_TLV320AIC23=m
-CONFIG_SND_SOC_TLV320AIC23_I2C=m
-# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
-# CONFIG_SND_SOC_TLV320AIC31XX is not set
-# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
-# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
-CONFIG_SND_SOC_TLV320AIC3X=m
-CONFIG_SND_SOC_TLV320AIC3X_I2C=m
-CONFIG_SND_SOC_TLV320AIC3X_SPI=m
-# CONFIG_SND_SOC_TLV320ADCX140 is not set
-CONFIG_SND_SOC_TS3A227E=m
-# CONFIG_SND_SOC_TSCS42XX is not set
-# CONFIG_SND_SOC_TSCS454 is not set
-# CONFIG_SND_SOC_UDA1334 is not set
-CONFIG_SND_SOC_WCD_MBHC=m
-CONFIG_SND_SOC_WCD938X=m
-CONFIG_SND_SOC_WCD938X_SDW=m
-# CONFIG_SND_SOC_WM8510 is not set
-# CONFIG_SND_SOC_WM8523 is not set
-CONFIG_SND_SOC_WM8524=m
-# CONFIG_SND_SOC_WM8580 is not set
-# CONFIG_SND_SOC_WM8711 is not set
-# CONFIG_SND_SOC_WM8728 is not set
-# CONFIG_SND_SOC_WM8731 is not set
-# CONFIG_SND_SOC_WM8737 is not set
-# CONFIG_SND_SOC_WM8741 is not set
-# CONFIG_SND_SOC_WM8750 is not set
-CONFIG_SND_SOC_WM8753=m
-# CONFIG_SND_SOC_WM8770 is not set
-# CONFIG_SND_SOC_WM8776 is not set
-CONFIG_SND_SOC_WM8782=m
-# CONFIG_SND_SOC_WM8804_I2C is not set
-# CONFIG_SND_SOC_WM8804_SPI is not set
-CONFIG_SND_SOC_WM8903=m
-# CONFIG_SND_SOC_WM8904 is not set
-CONFIG_SND_SOC_WM8960=m
-# CONFIG_SND_SOC_WM8962 is not set
-# CONFIG_SND_SOC_WM8974 is not set
-# CONFIG_SND_SOC_WM8978 is not set
-# CONFIG_SND_SOC_WM8985 is not set
-CONFIG_SND_SOC_WM8994=m
-CONFIG_SND_SOC_WM9712=m
-# CONFIG_SND_SOC_WSA881X is not set
-# CONFIG_SND_SOC_ZL38060 is not set
-# CONFIG_SND_SOC_MAX9759 is not set
-# CONFIG_SND_SOC_MT6351 is not set
-CONFIG_SND_SOC_MT6358=m
-# CONFIG_SND_SOC_MT6359 is not set
-# CONFIG_SND_SOC_MT6359_ACCDET is not set
-# CONFIG_SND_SOC_MT6660 is not set
-CONFIG_SND_SOC_NAU8315=m
-# CONFIG_SND_SOC_NAU8540 is not set
-# CONFIG_SND_SOC_NAU8810 is not set
-CONFIG_SND_SOC_NAU8821=m
-# CONFIG_SND_SOC_NAU8822 is not set
-# CONFIG_SND_SOC_NAU8824 is not set
-# CONFIG_SND_SOC_TPA6130A2 is not set
-CONFIG_SND_SOC_LPASS_WSA_MACRO=m
-CONFIG_SND_SOC_LPASS_VA_MACRO=m
-CONFIG_SND_SOC_LPASS_RX_MACRO=m
-CONFIG_SND_SOC_LPASS_TX_MACRO=m
-# end of CODEC drivers
-
-CONFIG_SND_SIMPLE_CARD_UTILS=m
-CONFIG_SND_SIMPLE_CARD=m
-CONFIG_SND_AUDIO_GRAPH_CARD=m
-CONFIG_SND_AUDIO_GRAPH_CARD2=m
-CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
-CONFIG_SND_TEST_COMPONENT=m
-CONFIG_SND_VIRTIO=m
-CONFIG_AC97_BUS=y
-
-#
-# HID support
-#
-CONFIG_HID=m
-# CONFIG_HID_BATTERY_STRENGTH is not set
-CONFIG_HIDRAW=y
-CONFIG_UHID=m
-CONFIG_HID_GENERIC=m
-
-#
-# Special HID drivers
-#
-CONFIG_HID_A4TECH=m
-# CONFIG_HID_ACCUTOUCH is not set
-CONFIG_HID_ACRUX=m
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=m
-CONFIG_HID_APPLEIR=m
-CONFIG_HID_ASUS=m
-CONFIG_HID_AUREAL=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_BETOP_FF=m
-CONFIG_HID_BIGBEN_FF=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CORSAIR=m
-CONFIG_HID_COUGAR=m
-CONFIG_HID_MACALLY=m
-CONFIG_HID_PRODIKEYS=m
-# CONFIG_HID_CMEDIA is not set
-# CONFIG_HID_CP2112 is not set
-# CONFIG_HID_CREATIVE_SB0540 is not set
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_DRAGONRISE=m
-# CONFIG_DRAGONRISE_FF is not set
-CONFIG_HID_EMS_FF=m
-CONFIG_HID_ELAN=m
-CONFIG_HID_ELECOM=m
-CONFIG_HID_ELO=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_FT260=m
-CONFIG_HID_GEMBIRD=m
-CONFIG_HID_GFRM=m
-# CONFIG_HID_GLORIOUS is not set
-CONFIG_HID_HOLTEK=m
-CONFIG_HOLTEK_FF=y
-CONFIG_HID_GOOGLE_HAMMER=m
-CONFIG_HID_VIVALDI=m
-# CONFIG_HID_GT683R is not set
-CONFIG_HID_KEYTOUCH=m
-CONFIG_HID_KYE=m
-CONFIG_HID_UCLOGIC=m
-CONFIG_HID_WALTOP=m
-# CONFIG_HID_VIEWSONIC is not set
-CONFIG_HID_VRC2=m
-CONFIG_HID_XIAOMI=m
-CONFIG_HID_GYRATION=m
-CONFIG_HID_ICADE=m
-CONFIG_HID_ITE=m
-CONFIG_HID_JABRA=m
-CONFIG_HID_TWINHAN=m
-CONFIG_HID_KENSINGTON=m
-CONFIG_HID_LCPOWER=m
-CONFIG_HID_LED=m
-# CONFIG_HID_LENOVO is not set
-CONFIG_HID_LOGITECH=m
-CONFIG_HID_LOGITECH_DJ=m
-CONFIG_HID_LOGITECH_HIDPP=m
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-# CONFIG_LOGIG940_FF is not set
-CONFIG_LOGIWHEELS_FF=y
-# CONFIG_HID_MAGICMOUSE is not set
-# CONFIG_HID_MALTRON is not set
-# CONFIG_HID_MAYFLASH is not set
-CONFIG_HID_REDRAGON=m
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_MULTITOUCH=m
-CONFIG_HID_NINTENDO=m
-CONFIG_NINTENDO_FF=y
-# CONFIG_HID_NTI is not set
-CONFIG_HID_NTRIG=m
-CONFIG_HID_ORTEK=m
-CONFIG_HID_PANTHERLORD=m
-CONFIG_PANTHERLORD_FF=y
-# CONFIG_HID_PENMOUNT is not set
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_PICOLCD=m
-CONFIG_HID_PICOLCD_FB=y
-CONFIG_HID_PICOLCD_BACKLIGHT=y
-CONFIG_HID_PICOLCD_LCD=y
-CONFIG_HID_PICOLCD_LEDS=y
-CONFIG_HID_PICOLCD_CIR=y
-CONFIG_HID_PLANTRONICS=m
-CONFIG_HID_PLAYSTATION=m
-CONFIG_HID_PXRC=m
-CONFIG_HID_RAZER=m
-CONFIG_PLAYSTATION_FF=y
-CONFIG_HID_PRIMAX=m
-CONFIG_HID_RETRODE=m
-CONFIG_HID_ROCCAT=m
-CONFIG_HID_SAITEK=m
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SEMITEK=m
-CONFIG_HID_SIGMAMICRO=m
-CONFIG_HID_SONY=m
-CONFIG_SONY_FF=y
-CONFIG_HID_SPEEDLINK=m
-CONFIG_HID_STEAM=m
-CONFIG_HID_STEELSERIES=m
-CONFIG_HID_SUNPLUS=m
-# CONFIG_HID_RMI is not set
-CONFIG_HID_GREENASIA=m
-# CONFIG_GREENASIA_FF is not set
-CONFIG_HID_HYPERV_MOUSE=m
-CONFIG_HID_SMARTJOYPLUS=m
-# CONFIG_SMARTJOYPLUS_FF is not set
-CONFIG_HID_TIVO=m
-CONFIG_HID_TOPSEED=m
-CONFIG_HID_TOPRE=m
-CONFIG_HID_THINGM=m
-CONFIG_HID_THRUSTMASTER=m
-# CONFIG_THRUSTMASTER_FF is not set
-# CONFIG_HID_UDRAW_PS3 is not set
-# CONFIG_HID_U2FZERO is not set
-CONFIG_HID_WACOM=m
-CONFIG_HID_WIIMOTE=m
-# CONFIG_HID_XINMO is not set
-CONFIG_HID_ZEROPLUS=m
-# CONFIG_ZEROPLUS_FF is not set
-CONFIG_HID_ZYDACRON=m
-CONFIG_HID_SENSOR_HUB=m
-# CONFIG_HID_SENSOR_CUSTOM_SENSOR is not set
-CONFIG_HID_ALPS=m
-# CONFIG_HID_MCP2221 is not set
-# end of Special HID drivers
-
-#
-# USB HID support
-#
-CONFIG_USB_HID=m
-CONFIG_HID_PID=y
-CONFIG_USB_HIDDEV=y
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# end of USB HID Boot Protocol drivers
-# end of USB HID support
-
-#
-# I2C HID support
-#
-CONFIG_I2C_HID_ACPI=m
-CONFIG_I2C_HID_OF=m
-CONFIG_I2C_HID_OF_ELAN=m
-CONFIG_I2C_HID_OF_GOODIX=m
-# end of I2C HID support
-
-CONFIG_I2C_HID_CORE=m
-
-#
-# Surface System Aggregator Module HID support
-#
-CONFIG_SURFACE_HID=m
-CONFIG_SURFACE_KBD=m
-# end of Surface System Aggregator Module HID support
-
-CONFIG_SURFACE_HID_CORE=m
-# end of HID support
-
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_COMMON=y
-# CONFIG_USB_LED_TRIG is not set
-CONFIG_USB_ULPI_BUS=y
-CONFIG_USB_CONN_GPIO=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB=y
-CONFIG_USB_PCI=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEFAULT_PERSIST=y
-CONFIG_USB_FEW_INIT_RETRIES=y
-CONFIG_USB_DYNAMIC_MINORS=y
-CONFIG_USB_OTG=y
-# CONFIG_USB_OTG_PRODUCTLIST is not set
-# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
-CONFIG_USB_OTG_FSM=y
-CONFIG_USB_LEDS_TRIGGER_USBPORT=m
-CONFIG_USB_AUTOSUSPEND_DELAY=2
-CONFIG_USB_MON=m
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_C67X00_HCD=m
-CONFIG_USB_XHCI_HCD=m
-# CONFIG_USB_XHCI_DBGCAP is not set
-CONFIG_USB_XHCI_PCI=m
-# CONFIG_USB_XHCI_PCI_RENESAS is not set
-CONFIG_USB_XHCI_PLATFORM=m
-CONFIG_USB_XHCI_HISTB=m
-CONFIG_USB_XHCI_MTK=m
-CONFIG_USB_XHCI_MVEBU=m
-CONFIG_USB_XHCI_RCAR=m
-CONFIG_USB_XHCI_TEGRA=m
-# CONFIG_USB_BRCMSTB is not set
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_EHCI_FSL=m
-CONFIG_USB_EHCI_HCD_NPCM7XX=m
-CONFIG_USB_EHCI_HCD_ORION=m
-CONFIG_USB_EHCI_TEGRA=m
-CONFIG_USB_EHCI_EXYNOS=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_OXU210HP_HCD=m
-CONFIG_USB_ISP116X_HCD=m
-CONFIG_USB_FOTG210_HCD=m
-CONFIG_USB_MAX3421_HCD=m
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PCI=y
-# CONFIG_USB_OHCI_HCD_SSB is not set
-CONFIG_USB_OHCI_EXYNOS=m
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_UHCI_HCD=m
-CONFIG_USB_U132_HCD=m
-CONFIG_USB_SL811_HCD=m
-# CONFIG_USB_SL811_HCD_ISO is not set
-CONFIG_USB_R8A66597_HCD=m
-CONFIG_USB_RENESAS_USBHS_HCD=m
-CONFIG_USB_HCD_BCMA=m
-CONFIG_USB_HCD_SSB=m
-# CONFIG_USB_HCD_TEST_MODE is not set
-CONFIG_USB_RENESAS_USBHS=m
-
-#
-# USB Device Class drivers
-#
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_WDM=m
-CONFIG_USB_TMC=m
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-CONFIG_USB_STORAGE_REALTEK=m
-CONFIG_REALTEK_AUTOPM=y
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_ISD200=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_STORAGE_ALAUDA=m
-CONFIG_USB_STORAGE_ONETOUCH=m
-CONFIG_USB_STORAGE_KARMA=m
-CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-CONFIG_USB_STORAGE_ENE_UB6250=m
-# CONFIG_USB_UAS is not set
-
-#
-# USB Imaging devices
-#
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USBIP_CORE=m
-CONFIG_USBIP_VHCI_HCD=m
-CONFIG_USBIP_VHCI_HC_PORTS=8
-CONFIG_USBIP_VHCI_NR_HCS=1
-# CONFIG_USBIP_HOST is not set
-# CONFIG_USBIP_VUDC is not set
-# CONFIG_USBIP_DEBUG is not set
-CONFIG_USB_CDNS_SUPPORT=m
-CONFIG_USB_CDNS_HOST=y
-# CONFIG_USB_CDNS3 is not set
-CONFIG_USB_CDNSP_PCI=m
-CONFIG_USB_CDNSP_GADGET=y
-CONFIG_USB_CDNSP_HOST=y
-CONFIG_USB_MTU3=m
-# CONFIG_USB_MTU3_HOST is not set
-# CONFIG_USB_MTU3_GADGET is not set
-CONFIG_USB_MTU3_DUAL_ROLE=y
-# CONFIG_USB_MTU3_DEBUG is not set
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_HOST=y
-
-#
-# Platform Glue Layer
-#
-CONFIG_USB_MUSB_SUNXI=m
-CONFIG_USB_MUSB_MEDIATEK=m
-
-#
-# MUSB DMA mode
-#
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_ULPI=y
-CONFIG_USB_DWC3_HOST=y
-
-#
-# Platform Glue Driver Support
-#
-CONFIG_USB_DWC3_EXYNOS=m
-CONFIG_USB_DWC3_PCI=y
-CONFIG_USB_DWC3_HAPS=y
-CONFIG_USB_DWC3_KEYSTONE=y
-CONFIG_USB_DWC3_MESON_G12A=y
-CONFIG_USB_DWC3_OF_SIMPLE=m
-CONFIG_USB_DWC3_QCOM=m
-CONFIG_USB_DWC3_IMX8MP=m
-CONFIG_USB_DWC3_XILINX=m
-CONFIG_USB_DWC3_AM62=m
-CONFIG_USB_DWC2=y
-CONFIG_USB_DWC2_HOST=y
-
-#
-# Gadget/Dual-role mode requires USB Gadget support to be enabled
-#
-CONFIG_USB_DWC2_PCI=m
-# CONFIG_USB_DWC2_DEBUG is not set
-# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
-CONFIG_USB_CHIPIDEA=m
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_PCI=m
-CONFIG_USB_CHIPIDEA_MSM=m
-CONFIG_USB_CHIPIDEA_IMX=m
-CONFIG_USB_CHIPIDEA_GENERIC=m
-CONFIG_USB_CHIPIDEA_TEGRA=m
-CONFIG_USB_ISP1760=y
-CONFIG_USB_ISP1760_HCD=y
-CONFIG_USB_ISP1760_HOST_ROLE=y
-
-#
-# USB port drivers
-#
-CONFIG_USB_USS720=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_SIMPLE=m
-CONFIG_USB_SERIAL_AIRCABLE=m
-CONFIG_USB_SERIAL_ARK3116=m
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_CH341=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CP210X=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_F81232=m
-CONFIG_USB_SERIAL_F8153X=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_IUU=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_METRO=m
-CONFIG_USB_SERIAL_MOS7720=m
-# CONFIG_USB_SERIAL_MOS7715_PARPORT is not set
-CONFIG_USB_SERIAL_MOS7840=m
-CONFIG_USB_SERIAL_MXUPORT=m
-CONFIG_USB_SERIAL_NAVMAN=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_OTI6858=m
-CONFIG_USB_SERIAL_QCAUX=m
-CONFIG_USB_SERIAL_QUALCOMM=m
-CONFIG_USB_SERIAL_SPCP8X5=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_SAFE_PADDED=y
-CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-CONFIG_USB_SERIAL_SYMBOL=m
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_WWAN=m
-CONFIG_USB_SERIAL_OPTION=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_SERIAL_OPTICON=m
-CONFIG_USB_SERIAL_XSENS_MT=m
-CONFIG_USB_SERIAL_WISHBONE=m
-CONFIG_USB_SERIAL_SSU100=m
-CONFIG_USB_SERIAL_QT2=m
-CONFIG_USB_SERIAL_UPD78F0730=m
-CONFIG_USB_SERIAL_XR=m
-CONFIG_USB_SERIAL_DEBUG=m
-
-#
-# USB Miscellaneous drivers
-#
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_ADUTUX=m
-CONFIG_USB_SEVSEG=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_CYPRESS_CY7C63=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_IDMOUSE=m
-CONFIG_USB_FTDI_ELAN=m
-CONFIG_USB_APPLEDISPLAY=m
-CONFIG_USB_QCOM_EUD=m
-# CONFIG_APPLE_MFI_FASTCHARGE is not set
-CONFIG_USB_SISUSBVGA=m
-CONFIG_USB_LD=m
-CONFIG_USB_TRANCEVIBRATOR=m
-CONFIG_USB_IOWARRIOR=m
-CONFIG_USB_TEST=m
-# CONFIG_USB_EHSET_TEST_FIXTURE is not set
-CONFIG_USB_ISIGHTFW=m
-CONFIG_USB_YUREX=m
-CONFIG_USB_EZUSB_FX2=m
-# CONFIG_USB_HUB_USB251XB is not set
-CONFIG_USB_HSIC_USB3503=y
-CONFIG_USB_HSIC_USB4604=m
-# CONFIG_USB_LINK_LAYER_TEST is not set
-# CONFIG_USB_CHAOSKEY is not set
-CONFIG_BRCM_USB_PINMAP=m
-CONFIG_USB_ONBOARD_HUB=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_CXACRU=m
-CONFIG_USB_UEAGLEATM=m
-CONFIG_USB_XUSBATM=m
-
-#
-# USB Physical Layer drivers
-#
-CONFIG_USB_PHY=y
-CONFIG_NOP_USB_XCEIV=m
-# CONFIG_USB_GPIO_VBUS is not set
-CONFIG_USB_ISP1301=m
-CONFIG_USB_MXS_PHY=m
-CONFIG_USB_TEGRA_PHY=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_ULPI_VIEWPORT=y
-# end of USB Physical Layer drivers
-
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
-# CONFIG_U_SERIAL_CONSOLE is not set
-
-#
-# USB Peripheral Controller
-#
-# CONFIG_USB_FOTG210_UDC is not set
-# CONFIG_USB_GR_UDC is not set
-# CONFIG_USB_R8A66597 is not set
-CONFIG_USB_RENESAS_USBHS_UDC=m
-CONFIG_USB_RENESAS_USB3=m
-# CONFIG_USB_PXA27X is not set
-# CONFIG_USB_MV_UDC is not set
-# CONFIG_USB_MV_U3D is not set
-CONFIG_USB_SNP_CORE=m
-CONFIG_USB_SNP_UDC_PLAT=m
-# CONFIG_USB_M66592 is not set
-CONFIG_USB_BDC_UDC=m
-# CONFIG_USB_AMD5536UDC is not set
-# CONFIG_USB_NET2272 is not set
-# CONFIG_USB_NET2280 is not set
-# CONFIG_USB_GOKU is not set
-# CONFIG_USB_EG20T is not set
-# CONFIG_USB_GADGET_XILINX is not set
-# CONFIG_USB_MAX3420_UDC is not set
-# CONFIG_USB_TEGRA_XUDC is not set
-# CONFIG_USB_DUMMY_HCD is not set
-# end of USB Peripheral Controller
-
-CONFIG_USB_LIBCOMPOSITE=m
-CONFIG_USB_F_ACM=m
-CONFIG_USB_F_SS_LB=m
-CONFIG_USB_U_SERIAL=m
-CONFIG_USB_U_ETHER=m
-CONFIG_USB_F_SERIAL=m
-CONFIG_USB_F_OBEX=m
-CONFIG_USB_F_NCM=m
-CONFIG_USB_F_ECM=m
-CONFIG_USB_F_PHONET=m
-CONFIG_USB_F_SUBSET=m
-CONFIG_USB_F_RNDIS=m
-CONFIG_USB_F_MASS_STORAGE=m
-CONFIG_USB_F_FS=m
-CONFIG_USB_F_UAC1_LEGACY=m
-CONFIG_USB_F_UVC=m
-CONFIG_USB_F_MIDI=m
-CONFIG_USB_F_HID=m
-CONFIG_USB_F_PRINTER=m
-# CONFIG_USB_CONFIGFS is not set
-
-#
-# USB Gadget precomposed configurations
-#
-CONFIG_USB_ZERO=m
-CONFIG_USB_ZERO_HNPTEST=y
-CONFIG_USB_AUDIO=m
-CONFIG_GADGET_UAC1=y
-CONFIG_GADGET_UAC1_LEGACY=y
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-# CONFIG_USB_ETH_EEM is not set
-CONFIG_USB_G_NCM=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FUNCTIONFS=m
-# CONFIG_USB_FUNCTIONFS_ETH is not set
-# CONFIG_USB_FUNCTIONFS_RNDIS is not set
-CONFIG_USB_FUNCTIONFS_GENERIC=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_MIDI_GADGET=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_NOKIA=m
-CONFIG_USB_G_ACM_MS=m
-CONFIG_USB_G_MULTI=m
-CONFIG_USB_G_MULTI_RNDIS=y
-CONFIG_USB_G_MULTI_CDC=y
-CONFIG_USB_G_HID=m
-# CONFIG_USB_G_DBGP is not set
-CONFIG_USB_G_WEBCAM=m
-CONFIG_USB_RAW_GADGET=m
-# end of USB Gadget precomposed configurations
-
-CONFIG_TYPEC=y
-CONFIG_TYPEC_TCPM=m
-CONFIG_TYPEC_TCPCI=m
-CONFIG_TYPEC_RT1711H=m
-CONFIG_TYPEC_TCPCI_MT6370=m
-CONFIG_TYPEC_TCPCI_MAXIM=m
-CONFIG_TYPEC_FUSB302=m
-CONFIG_TYPEC_UCSI=m
-CONFIG_UCSI_CCG=m
-CONFIG_UCSI_ACPI=m
-CONFIG_UCSI_STM32G0=m
-# CONFIG_TYPEC_TPS6598X is not set
-CONFIG_TYPEC_ANX7411=m
-CONFIG_TYPEC_RT1719=m
-# CONFIG_TYPEC_HD3SS3220 is not set
-CONFIG_TYPEC_STUSB160X=m
-CONFIG_TYPEC_WUSB3801=m
-CONFIG_TYPEC_QCOM_PMIC=m
-CONFIG_TYPEC_WUSB3801=m
-CONFIG_TYPEC_EXTCON=m
-
-#
-# USB Type-C Multiplexer/DeMultiplexer Switch support
-#
-# CONFIG_TYPEC_MUX_PI3USB30532 is not set
-# end of USB Type-C Multiplexer/DeMultiplexer Switch support
-
-#
-# USB Type-C Alternate Mode drivers
-#
-CONFIG_TYPEC_DP_ALTMODE=m
-CONFIG_TYPEC_NVIDIA_ALTMODE=m
-# end of USB Type-C Alternate Mode drivers
-
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_MMC=y
-CONFIG_PWRSEQ_EMMC=y
-CONFIG_PWRSEQ_SD8787=m
-CONFIG_PWRSEQ_SIMPLE=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_SDIO_UART=m
-# CONFIG_MMC_TEST is not set
-CONFIG_MMC_CRYPTO=y
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_ARMMMCI=y
-CONFIG_MMC_QCOM_DML=y
-CONFIG_MMC_STM32_SDMMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PCI=y
-# CONFIG_MMC_RICOH_MMC is not set
-CONFIG_MMC_SDHCI_ACPI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_OF_ARASAN=y
-CONFIG_MMC_SDHCI_OF_ASPEED=m
-CONFIG_MMC_SDHCI_OF_AT91=m
-CONFIG_MMC_SDHCI_OF_ESDHC=m
-CONFIG_MMC_SDHCI_OF_DWCMSHC=y
-CONFIG_MMC_SDHCI_OF_SPARX5=m
-CONFIG_MMC_SDHCI_CADENCE=m
-CONFIG_MMC_SDHCI_ESDHC_IMX=m
-CONFIG_MMC_SDHCI_TEGRA=m
-CONFIG_MMC_SDHCI_S3C=m
-# CONFIG_MMC_SDHCI_PXAV3 is not set
-CONFIG_MMC_SDHCI_S3C_DMA=y
-CONFIG_MMC_SDHCI_F_SDH30=m
-CONFIG_MMC_SDHCI_MILBEAUT=m
-CONFIG_MMC_SDHCI_IPROC=m
-CONFIG_MMC_MESON_GX=y
-CONFIG_MMC_MESON_MX_SDIO=m
-CONFIG_MMC_SDHCI_MSM=m
-CONFIG_MMC_MXC=m
-# CONFIG_MMC_TIFM_SD is not set
-CONFIG_MMC_SPI=y
-# CONFIG_MMC_SDHCI_SPRD is not set
-CONFIG_MMC_TMIO_CORE=y
-CONFIG_MMC_SDHI=y
-# CONFIG_MMC_SDHI_SYS_DMAC is not set
-CONFIG_MMC_SDHI_INTERNAL_DMAC=y
-# CONFIG_MMC_UNIPHIER is not set
-# CONFIG_MMC_CB710 is not set
-CONFIG_MMC_VIA_SDMMC=m
-CONFIG_MMC_CAVIUM_THUNDERX=m
-CONFIG_MMC_DW=y
-CONFIG_MMC_DW_PLTFM=y
-# CONFIG_MMC_DW_BLUEFIELD is not set
-CONFIG_MMC_DW_EXYNOS=y
-# CONFIG_MMC_DW_HI3798CV200 is not set
-CONFIG_MMC_DW_K3=y
-CONFIG_MMC_DW_PCI=y
-CONFIG_MMC_DW_ROCKCHIP=y
-# CONFIG_MMC_SH_MMCIF is not set
-# CONFIG_MMC_VUB300 is not set
-CONFIG_MMC_USHC=m
-# CONFIG_MMC_USDHI6ROL0 is not set
-CONFIG_MMC_REALTEK_PCI=m
-# CONFIG_MMC_REALTEK_USB is not set
-CONFIG_MMC_SUNXI=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_HSQ=m
-# CONFIG_MMC_TOSHIBA_PCI is not set
-CONFIG_MMC_BCM2835=y
-CONFIG_MMC_MTK=m
-CONFIG_MMC_SDHCI_BRCMSTB=m
-CONFIG_MMC_SDHCI_XENON=m
-CONFIG_MMC_SDHCI_OMAP=m
-CONFIG_MMC_SDHCI_AM654=m
-CONFIG_MMC_OWL=m
-CONFIG_MMC_LITEX=m
-CONFIG_MMC_SDHCI_EXTERNAL_DMA=y
-# CONFIG_MEMSTICK is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-# CONFIG_LEDS_CLASS_FLASH is not set
-CONFIG_LEDS_CLASS_MULTICOLOR=m
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-
-#
-# LED drivers
-#
-# CONFIG_LEDS_AN30259A is not set
-# CONFIG_LEDS_AW2013 is not set
-# CONFIG_LEDS_BCM6328 is not set
-# CONFIG_LEDS_BCM6358 is not set
-# CONFIG_LEDS_CR0014114 is not set
-# CONFIG_LEDS_EL15203000 is not set
-# CONFIG_LEDS_LM3530 is not set
-# CONFIG_LEDS_LM3532 is not set
-CONFIG_LEDS_LM3642=m
-# CONFIG_LEDS_LM3692X is not set
-# CONFIG_LEDS_PCA9532 is not set
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEDS_LP3944 is not set
-# CONFIG_LEDS_LP3952 is not set
-CONFIG_LEDS_LP50XX=m
-CONFIG_LEDS_LP55XX_COMMON=m
-# CONFIG_LEDS_LP5521 is not set
-# CONFIG_LEDS_LP5523 is not set
-# CONFIG_LEDS_LP5562 is not set
-# CONFIG_LEDS_LP8501 is not set
-# CONFIG_LEDS_LP8860 is not set
-# CONFIG_LEDS_PCA955X is not set
-# CONFIG_LEDS_PCA963X is not set
-# CONFIG_LEDS_DAC124S085 is not set
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_REGULATOR=m
-# CONFIG_LEDS_BD2802 is not set
-# CONFIG_LEDS_LT3593 is not set
-# CONFIG_LEDS_MC13783 is not set
-CONFIG_LEDS_TCA6507=m
-# CONFIG_LEDS_TLC591XX is not set
-CONFIG_LEDS_LM355x=m
-# CONFIG_LEDS_IS31FL319X is not set
-# CONFIG_LEDS_IS31FL32XX is not set
-
-#
-# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
-#
-CONFIG_LEDS_BLINKM=m
-CONFIG_LEDS_SYSCON=y
-# CONFIG_LEDS_MLXREG is not set
-CONFIG_LEDS_USER=m
-# CONFIG_LEDS_SPI_BYTE is not set
-# CONFIG_LEDS_TI_LMU_COMMON is not set
-CONFIG_LEDS_BCM63138=m
-
-#
-# Flash and Torch LED drivers
-#
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_ONESHOT=m
-CONFIG_LEDS_TRIGGER_DISK=y
-# CONFIG_LEDS_TRIGGER_MTD is not set
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=m
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_ACTIVITY=y
-CONFIG_LEDS_TRIGGER_GPIO=m
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-CONFIG_LEDS_TRIGGER_TRANSIENT=m
-CONFIG_LEDS_TRIGGER_CAMERA=m
-CONFIG_LEDS_TRIGGER_PANIC=y
-CONFIG_LEDS_TRIGGER_NETDEV=m
-CONFIG_LEDS_TRIGGER_PATTERN=m
-CONFIG_LEDS_TRIGGER_AUDIO=m
-CONFIG_LEDS_TRIGGER_TTY=m
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_A11Y_BRAILLE_CONSOLE=y
-
-#
-# Speakup console speech
-#
-# CONFIG_SPEAKUP is not set
-# end of Speakup console speech
-
-CONFIG_INFINIBAND=m
-CONFIG_INFINIBAND_USER_MAD=m
-CONFIG_INFINIBAND_USER_ACCESS=m
-CONFIG_INFINIBAND_USER_MEM=y
-CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
-CONFIG_INFINIBAND_ADDR_TRANS=y
-CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
-CONFIG_INFINIBAND_VIRT_DMA=y
-CONFIG_INFINIBAND_MTHCA=m
-# CONFIG_INFINIBAND_MTHCA_DEBUG is not set
-CONFIG_INFINIBAND_EFA=m
-CONFIG_INFINIBAND_ERDMA=m
-CONFIG_MLX4_INFINIBAND=m
-CONFIG_MLX5_INFINIBAND=m
-CONFIG_INFINIBAND_OCRDMA=m
-CONFIG_INFINIBAND_VMWARE_PVRDMA=m
-CONFIG_INFINIBAND_HNS=m
-CONFIG_INFINIBAND_HNS_HIP06=y
-CONFIG_INFINIBAND_HNS_HIP08=y
-CONFIG_INFINIBAND_BNXT_RE=m
-CONFIG_RDMA_RXE=m
-CONFIG_RDMA_SIW=m
-CONFIG_INFINIBAND_IPOIB=m
-CONFIG_INFINIBAND_IPOIB_CM=y
-# CONFIG_INFINIBAND_IPOIB_DEBUG is not set
-CONFIG_INFINIBAND_SRP=m
-CONFIG_INFINIBAND_ISER=m
-CONFIG_INFINIBAND_RTRS=m
-CONFIG_INFINIBAND_RTRS_CLIENT=m
-CONFIG_INFINIBAND_RTRS_SERVER=m
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EDAC=m
-CONFIG_EDAC_LEGACY_SYSFS=y
-# CONFIG_EDAC_DEBUG is not set
-# CONFIG_EDAC_GHES is not set
-CONFIG_EDAC_AL_MC=m
-# CONFIG_EDAC_LAYERSCAPE is not set
-CONFIG_EDAC_THUNDERX=m
-# CONFIG_EDAC_ALTERA is not set
-# CONFIG_EDAC_SYNOPSYS is not set
-CONFIG_EDAC_XGENE=m
-# CONFIG_EDAC_QCOM is not set
-# CONFIG_EDAC_DMC520 is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-CONFIG_RTC_SYSTOHC=y
-CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-CONFIG_RTC_NVMEM=y
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-# CONFIG_RTC_INTF_PROC is not set
-CONFIG_RTC_INTF_DEV=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_ABB5ZES3 is not set
-# CONFIG_RTC_DRV_ABEOZ9 is not set
-# CONFIG_RTC_DRV_ABX80X is not set
-# CONFIG_RTC_DRV_AC100 is not set
-CONFIG_RTC_DRV_BRCMSTB=y
-# CONFIG_RTC_DRV_AS3722 is not set
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-CONFIG_RTC_DRV_HYM8563=m
-# CONFIG_RTC_DRV_MAX6900 is not set
-CONFIG_RTC_DRV_MAX77686=y
-CONFIG_RTC_DRV_NCT3018Y=m
-CONFIG_RTC_DRV_TI_K3=m
-CONFIG_RTC_DRV_RK808=m
-# CONFIG_RTC_DRV_RS5C372 is not set
-CONFIG_RTC_DRV_ISL1208=m
-CONFIG_RTC_DRV_ISL12022=m
-# CONFIG_RTC_DRV_ISL12026 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-CONFIG_RTC_DRV_PCF8523=m
-CONFIG_RTC_DRV_PCF85063=m
-# CONFIG_RTC_DRV_PCF85363 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-CONFIG_RTC_DRV_BQ32K=m
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-CONFIG_RTC_DRV_RX8010=m
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-# CONFIG_RTC_DRV_EM3027 is not set
-# CONFIG_RTC_DRV_RV3028 is not set
-CONFIG_RTC_DRV_RV3032=m
-CONFIG_RTC_DRV_RV8803=m
-CONFIG_RTC_DRV_S5M=m
-# CONFIG_RTC_DRV_SD3078 is not set
-
-#
-# SPI RTC drivers
-#
-CONFIG_RTC_DRV_M41T93=m
-CONFIG_RTC_DRV_M41T94=m
-CONFIG_RTC_DRV_DS1302=m
-CONFIG_RTC_DRV_DS1305=m
-CONFIG_RTC_DRV_DS1343=m
-CONFIG_RTC_DRV_DS1347=m
-CONFIG_RTC_DRV_DS1390=m
-CONFIG_RTC_DRV_MAX6916=m
-CONFIG_RTC_DRV_R9701=m
-CONFIG_RTC_DRV_RX4581=m
-CONFIG_RTC_DRV_RS5C348=m
-CONFIG_RTC_DRV_MAX6902=m
-CONFIG_RTC_DRV_PCF2123=m
-CONFIG_RTC_DRV_MCP795=m
-CONFIG_RTC_I2C_AND_SPI=y
-
-#
-# SPI and I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS3232 is not set
-CONFIG_RTC_DRV_PCF2127=m
-# CONFIG_RTC_DRV_RV3029C2 is not set
-CONFIG_RTC_DRV_RX6110=m
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1685_FAMILY is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_DS2404 is not set
-CONFIG_RTC_DRV_EFI=y
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_MSM6242 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_RP5C01 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-CONFIG_RTC_DRV_OPTEE=m
-CONFIG_RTC_DRV_ZYNQMP=m
-CONFIG_RTC_DRV_CROS_EC=m
-CONFIG_RTC_DRV_NTXEC=m
-
-#
-# on-CPU RTC drivers
-#
-CONFIG_RTC_DRV_IMXDI=m
-CONFIG_RTC_DRV_FSL_FTM_ALARM=m
-CONFIG_RTC_DRV_MESON_VRTC=m
-CONFIG_RTC_DRV_S3C=y
-# CONFIG_RTC_DRV_SH is not set
-CONFIG_RTC_DRV_PL030=m
-CONFIG_RTC_DRV_PL031=y
-CONFIG_RTC_DRV_SUN6I=y
-CONFIG_RTC_DRV_MV=m
-CONFIG_RTC_DRV_ARMADA38X=y
-# CONFIG_RTC_DRV_CADENCE is not set
-# CONFIG_RTC_DRV_FTRTC010 is not set
-CONFIG_RTC_DRV_MC13XXX=m
-CONFIG_RTC_DRV_PM8XXX=m
-CONFIG_RTC_DRV_TEGRA=y
-CONFIG_RTC_DRV_MXC=m
-CONFIG_RTC_DRV_MXC_V2=m
-CONFIG_RTC_DRV_SNVS=m
-CONFIG_RTC_DRV_IMX_SC=m
-# CONFIG_RTC_DRV_MT2712 is not set
-# CONFIG_RTC_DRV_MT7622 is not set
-CONFIG_RTC_DRV_XGENE=y
-# CONFIG_RTC_DRV_R7301 is not set
-CONFIG_RTC_DRV_RTD119X=y
-
-#
-# HID Sensor RTC drivers
-#
-CONFIG_RTC_DRV_HID_SENSOR_TIME=m
-CONFIG_RTC_DRV_GOLDFISH=m
-CONFIG_DMADEVICES=y
-# CONFIG_DMADEVICES_DEBUG is not set
-
-#
-# DMA Devices
-#
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DMA_ACPI=y
-CONFIG_DMA_OF=y
-# CONFIG_ALTERA_MSGDMA is not set
-# CONFIG_AMBA_PL08X is not set
-CONFIG_APPLE_ADMAC=m
-# CONFIG_AXI_DMAC is not set
-# CONFIG_BCM_SBA_RAID is not set
-CONFIG_DMA_BCM2835=m
-CONFIG_DMA_SUN6I=m
-# CONFIG_DW_AXI_DMAC is not set
-# CONFIG_FSL_EDMA is not set
-# CONFIG_FSL_QDMA is not set
-CONFIG_HISI_DMA=m
-CONFIG_IMX_DMA=m
-CONFIG_IMX_SDMA=m
-# CONFIG_INTEL_IDMA64 is not set
-CONFIG_K3_DMA=y
-CONFIG_MV_XOR=y
-CONFIG_MV_XOR_V2=y
-CONFIG_MXS_DMA=y
-CONFIG_MX3_IPU=y
-CONFIG_MX3_IPU_IRQS=4
-# CONFIG_OWL_DMA is not set
-CONFIG_PL330_DMA=y
-# CONFIG_PLX_DMA is not set
-# CONFIG_SPRD_DMA is not set
-CONFIG_TEGRA20_APB_DMA=y
-CONFIG_TEGRA210_ADMA=y
-# CONFIG_UNIPHIER_MDMAC is not set
-# CONFIG_UNIPHIER_XDMAC is not set
-CONFIG_XGENE_DMA=m
-# CONFIG_XILINX_DMA is not set
-# CONFIG_XILINX_ZYNQMP_DMA is not set
-CONFIG_XILINX_ZYNQMP_DPDMA=m
-# CONFIG_MTK_HSDMA is not set
-# CONFIG_MTK_CQDMA is not set
-# CONFIG_MTK_UART_APDMA is not set
-CONFIG_QCOM_BAM_DMA=y
-CONFIG_QCOM_GPI_DMA=m
-CONFIG_QCOM_HIDMA_MGMT=y
-CONFIG_QCOM_HIDMA=y
-# CONFIG_DW_DMAC is not set
-# CONFIG_DW_DMAC_PCI is not set
-# CONFIG_DW_EDMA is not set
-# CONFIG_DW_EDMA_PCIE is not set
-# CONFIG_SF_PDMA is not set
-CONFIG_RENESAS_DMA=y
-CONFIG_RCAR_DMAC=y
-CONFIG_RENESAS_USB_DMAC=m
-CONFIG_RZ_DMAC=m
-# CONFIG_TI_K3_UDMA is not set
-
-#
-# DMA Clients
-#
-CONFIG_ASYNC_TX_DMA=y
-CONFIG_DMATEST=m
-CONFIG_DMA_ENGINE_RAID=y
-
-#
-# DMABUF options
-#
-CONFIG_SYNC_FILE=y
-CONFIG_UDMABUF=y
-# CONFIG_DMABUF_MOVE_NOTIFY is not set
-# CONFIG_DMABUF_DEBUG is not set
-# CONFIG_DMABUF_SELFTESTS is not set
-CONFIG_DMABUF_HEAPS=y
-# CONFIG_DMABUF_SYSFS_STATS is not set
-CONFIG_DMABUF_HEAPS_SYSTEM=y
-CONFIG_DMABUF_HEAPS_CMA=y
-# end of DMABUF options
-
-CONFIG_AUXDISPLAY=y
-CONFIG_CHARLCD=m
-CONFIG_HD44780_COMMON=m
-# CONFIG_HD44780 is not set
-CONFIG_KS0108=m
-CONFIG_KS0108_PORT=0x378
-CONFIG_KS0108_DELAY=2
-# CONFIG_IMG_ASCII_LCD is not set
-# CONFIG_HT16K33 is not set
-CONFIG_LCD2S=m
-CONFIG_PARPORT_PANEL=m
-CONFIG_PANEL_PARPORT=0
-CONFIG_PANEL_PROFILE=5
-# CONFIG_PANEL_CHANGE_MESSAGE is not set
-# CONFIG_CHARLCD_BL_OFF is not set
-# CONFIG_CHARLCD_BL_ON is not set
-CONFIG_CHARLCD_BL_FLASH=y
-CONFIG_PANEL=m
-CONFIG_UIO=m
-CONFIG_UIO_CIF=m
-# CONFIG_UIO_PDRV_GENIRQ is not set
-# CONFIG_UIO_DMEM_GENIRQ is not set
-# CONFIG_UIO_AEC is not set
-CONFIG_UIO_SERCOS3=m
-# CONFIG_UIO_PCI_GENERIC is not set
-# CONFIG_UIO_NETX is not set
-# CONFIG_UIO_PRUSS is not set
-# CONFIG_UIO_MF624 is not set
-CONFIG_UIO_HV_GENERIC=m
-CONFIG_VFIO=y
-CONFIG_VFIO_IOMMU_TYPE1=y
-CONFIG_VFIO_VIRQFD=y
-CONFIG_VFIO_NOIOMMU=y
-CONFIG_VFIO_PCI_CORE=y
-CONFIG_VFIO_PCI_MMAP=y
-CONFIG_VFIO_PCI_INTX=y
-CONFIG_VFIO_PCI=y
-CONFIG_MLX5_VFIO_PCI=m
-CONFIG_HISI_ACC_VFIO_PCI=m
-# CONFIG_VFIO_PLATFORM is not set
-# CONFIG_VFIO_MDEV is not set
-CONFIG_VIRT_DRIVERS=y
-CONFIG_VMGENID=m
-CONFIG_NITRO_ENCLAVES=m
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_PCI_LIB=y
-CONFIG_VIRTIO_PCI_LIB_LEGACY=y
-CONFIG_VIRTIO_MENU=y
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_PMEM=m
-CONFIG_VIRTIO_BALLOON=y
-CONFIG_VIRTIO_MEM=m
-CONFIG_VIRTIO_INPUT=m
-CONFIG_VIRTIO_MMIO=y
-CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
-CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
-# CONFIG_VDPA is not set
-CONFIG_VHOST_IOTLB=m
-CONFIG_VHOST=m
-CONFIG_VHOST_MENU=y
-CONFIG_VHOST_NET=m
-CONFIG_VHOST_VSOCK=m
-# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
-
-#
-# Microsoft Hyper-V guest support
-#
-CONFIG_HYPERV=m
-CONFIG_HYPERV_UTILS=m
-CONFIG_HYPERV_BALLOON=m
-# end of Microsoft Hyper-V guest support
-
-# CONFIG_GREYBUS is not set
-# CONFIG_COMEDI is not set
-CONFIG_STAGING=y
-CONFIG_PRISM2_USB=m
-CONFIG_RTL8192U=m
-CONFIG_RTLLIB=m
-CONFIG_RTLLIB_CRYPTO_CCMP=m
-CONFIG_RTLLIB_CRYPTO_TKIP=m
-CONFIG_RTLLIB_CRYPTO_WEP=m
-CONFIG_RTL8192E=m
-CONFIG_RTL8723BS=m
-CONFIG_R8712U=m
-CONFIG_R8188EU=m
-CONFIG_RTS5208=m
-# CONFIG_VT6655 is not set
-# CONFIG_VT6656 is not set
-
-#
-# IIO staging drivers
-#
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16203=m
-CONFIG_ADIS16240=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD7816=m
-CONFIG_AD7280=m
-# end of Analog to digital converters
-
-#
-# Analog digital bi-direction converters
-#
-CONFIG_ADT7316=m
-CONFIG_ADT7316_SPI=m
-CONFIG_ADT7316_I2C=m
-# end of Analog digital bi-direction converters
-
-#
-# Capacitance to digital converters
-#
-CONFIG_AD7746=m
-# end of Capacitance to digital converters
-
-#
-# Direct Digital Synthesis
-#
-CONFIG_AD9832=m
-CONFIG_AD9834=m
-# end of Direct Digital Synthesis
-
-#
-# Network Analyzer, Impedance Converters
-#
-CONFIG_AD5933=m
-# end of Network Analyzer, Impedance Converters
-
-#
-# Active energy metering IC
-#
-CONFIG_ADE7854=m
-CONFIG_ADE7854_I2C=m
-CONFIG_ADE7854_SPI=m
-# end of Active energy metering IC
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S1210=m
-# end of Resolver to digital converters
-# end of IIO staging drivers
-
-CONFIG_FB_SM750=m
-CONFIG_USB_EMXX=m
-CONFIG_MFD_NVEC=m
-CONFIG_KEYBOARD_NVEC=m
-CONFIG_SERIO_NVEC_PS2=m
-CONFIG_NVEC_POWER=m
-CONFIG_NVEC_PAZ00=m
-CONFIG_STAGING_MEDIA=y
-CONFIG_VIDEO_HANTRO=m
-CONFIG_VIDEO_HANTRO_IMX8M=y
-CONFIG_VIDEO_HANTRO_ROCKCHIP=y
-CONFIG_VIDEO_HANTRO_SUNXI=y
-CONFIG_VIDEO_IMX_MEDIA=m
-
-#
-# i.MX5/6/7/8 Media Sub devices
-#
-CONFIG_VIDEO_IMX7_CSI=m
-# end of i.MX5/6/7/8 Media Sub devices
-
-CONFIG_VIDEO_MESON_VDEC=m
-CONFIG_VIDEO_ROCKCHIP_VDEC=m
-CONFIG_VIDEO_STKWEBCAM=m
-CONFIG_VIDEO_SUNXI=y
-CONFIG_VIDEO_SUNXI_CEDRUS=m
-CONFIG_TEGRA_VDE=m
-CONFIG_VIDEO_ZORAN=m
-CONFIG_VIDEO_ZORAN_DC30=y
-CONFIG_VIDEO_ZORAN_ZR36060=y
-CONFIG_VIDEO_ZORAN_BUZ=y
-CONFIG_VIDEO_ZORAN_DC10=y
-CONFIG_VIDEO_ZORAN_LML33=y
-CONFIG_VIDEO_ZORAN_LML33R10=y
-CONFIG_VIDEO_ZORAN_AVS6EYES=y
-CONFIG_VIDEO_TEGRA=m
-CONFIG_VIDEO_TEGRA_TPG=y
-CONFIG_DVB_AV7110_IR=y
-CONFIG_DVB_AV7110=m
-CONFIG_DVB_AV7110_OSD=y
-CONFIG_DVB_BUDGET_PATCH=m
-CONFIG_DVB_SP8870=m
-
-#
-# Android
-#
-CONFIG_ASHMEM=m
-# end of Android
-
-# CONFIG_STAGING_BOARD is not set
-CONFIG_LTE_GDM724X=m
-CONFIG_GS_FPGABOOT=m
-# CONFIG_UNISYSSPAR is not set
-CONFIG_COMMON_CLK_XLNX_CLKWZRD=m
-CONFIG_FB_TFT=m
-CONFIG_FB_TFT_AGM1264K_FL=m
-CONFIG_FB_TFT_BD663474=m
-CONFIG_FB_TFT_HX8340BN=m
-CONFIG_FB_TFT_HX8347D=m
-CONFIG_FB_TFT_HX8353D=m
-CONFIG_FB_TFT_HX8357D=m
-CONFIG_FB_TFT_ILI9163=m
-CONFIG_FB_TFT_ILI9320=m
-CONFIG_FB_TFT_ILI9325=m
-CONFIG_FB_TFT_ILI9340=m
-CONFIG_FB_TFT_ILI9341=m
-CONFIG_FB_TFT_ILI9481=m
-CONFIG_FB_TFT_ILI9486=m
-CONFIG_FB_TFT_PCD8544=m
-CONFIG_FB_TFT_RA8875=m
-CONFIG_FB_TFT_S6D02A1=m
-CONFIG_FB_TFT_S6D1121=m
-CONFIG_FB_TFT_SEPS525=m
-CONFIG_FB_TFT_SH1106=m
-CONFIG_FB_TFT_SSD1289=m
-CONFIG_FB_TFT_SSD1305=m
-CONFIG_FB_TFT_SSD1306=m
-CONFIG_FB_TFT_SSD1331=m
-CONFIG_FB_TFT_SSD1351=m
-CONFIG_FB_TFT_ST7735R=m
-CONFIG_FB_TFT_ST7789V=m
-CONFIG_FB_TFT_TINYLCD=m
-CONFIG_FB_TFT_TLS8204=m
-CONFIG_FB_TFT_UC1611=m
-CONFIG_FB_TFT_UC1701=m
-CONFIG_FB_TFT_UPD161704=m
-CONFIG_FB_TFT_WATTEROTT=m
-# CONFIG_MOST_COMPONENTS is not set
-CONFIG_KS7010=m
-CONFIG_BCM_VIDEOCORE=y
-CONFIG_BCM2835_VCHIQ=m
-CONFIG_VCHIQ_CDEV=y
-CONFIG_SND_BCM2835=m
-CONFIG_VIDEO_BCM2835=m
-CONFIG_BCM2835_VCHIQ_MMAL=m
-CONFIG_PI433=m
-CONFIG_XIL_AXIS_FIFO=m
-CONFIG_FIELDBUS_DEV=m
-# CONFIG_HMS_ANYBUSS_BUS is not set
-CONFIG_QLGE=m
-CONFIG_WFX=m
-CONFIG_RTL8723CS=m
-# CONFIG_GOLDFISH is not set
-CONFIG_CHROME_PLATFORMS=y
-CONFIG_CHROMEOS_ACPI=m
-# CONFIG_CHROMEOS_TBMC is not set
-CONFIG_CROS_EC=y
-CONFIG_CROS_EC_I2C=m
-CONFIG_CROS_EC_RPMSG=m
-CONFIG_CROS_EC_SPI=m
-CONFIG_CROS_EC_PROTO=y
-# CONFIG_CROS_KBD_LED_BACKLIGHT is not set
-CONFIG_CROS_EC_CHARDEV=y
-CONFIG_CROS_EC_LIGHTBAR=m
-CONFIG_CROS_EC_VBC=m
-CONFIG_CROS_EC_SENSORHUB=y
-CONFIG_CROS_EC_SYSFS=m
-CONFIG_CROS_EC_TYPEC=m
-CONFIG_CROS_USBPD_LOGGER=m
-CONFIG_CROS_USBPD_NOTIFY=y
-CONFIG_CHROMEOS_PRIVACY_SCREEN=m
-CONFIG_CROS_TYPEC_SWITCH=m
-# CONFIG_MELLANOX_PLATFORM is not set
-CONFIG_SURFACE_PLATFORMS=y
-CONFIG_SURFACE_3_BUTTON=m
-CONFIG_SURFACE_3_POWER_OPREGION=m
-CONFIG_SURFACE_ACPI_NOTIFY=m
-CONFIG_SURFACE_AGGREGATOR_CDEV=m
-CONFIG_SURFACE_AGGREGATOR_HUB=m
-CONFIG_SURFACE_AGGREGATOR_REGISTRY=m
-CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m
-CONFIG_SURFACE_DTX=m
-CONFIG_SURFACE_GPE=m
-CONFIG_SURFACE_HOTPLUG=m
-CONFIG_SURFACE_PLATFORM_PROFILE=m
-CONFIG_SURFACE_PRO3_BUTTON=m
-CONFIG_SURFACE_AGGREGATOR=m
-CONFIG_SURFACE_AGGREGATOR_BUS=y
-# CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION is not set
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_COMMON_CLK=y
-
-#
-# Clock driver for ARM Reference designs
-#
-CONFIG_CLK_ICST=y
-CONFIG_CLK_SP810=y
-CONFIG_CLK_VEXPRESS_OSC=y
-# end of Clock driver for ARM Reference designs
-
-CONFIG_LMK04832=m
-CONFIG_COMMON_CLK_APPLE_NCO=m
-# CONFIG_COMMON_CLK_MAX77686 is not set
-# CONFIG_COMMON_CLK_MAX9485 is not set
-CONFIG_COMMON_CLK_RK808=y
-CONFIG_COMMON_CLK_HI655X=y
-CONFIG_COMMON_CLK_SCPI=y
-# CONFIG_COMMON_CLK_SI5341 is not set
-# CONFIG_COMMON_CLK_SI5351 is not set
-# CONFIG_COMMON_CLK_SI514 is not set
-# CONFIG_COMMON_CLK_SI544 is not set
-# CONFIG_COMMON_CLK_SI570 is not set
-CONFIG_COMMON_CLK_BM1880=y
-# CONFIG_COMMON_CLK_CDCE706 is not set
-CONFIG_COMMON_CLK_TPS68470=m
-# CONFIG_COMMON_CLK_CDCE925 is not set
-CONFIG_COMMON_CLK_CS2000_CP=y
-CONFIG_COMMON_CLK_FSL_FLEXSPI=m
-# CONFIG_COMMON_CLK_FSL_SAI is not set
-CONFIG_COMMON_CLK_S2MPS11=y
-CONFIG_COMMON_CLK_AXI_CLKGEN=m
-CONFIG_CLK_QORIQ=y
-CONFIG_CLK_LS1028A_PLLDIG=y
-# CONFIG_COMMON_CLK_XGENE is not set
-CONFIG_COMMON_CLK_PWM=y
-CONFIG_COMMON_CLK_RS9_PCIE=m
-# CONFIG_COMMON_CLK_VC5 is not set
-CONFIG_COMMON_CLK_VC7=m
-# CONFIG_COMMON_CLK_FIXED_MMIO is not set
-CONFIG_CLK_ACTIONS=y
-CONFIG_CLK_OWL_S500=y
-CONFIG_CLK_OWL_S700=y
-CONFIG_CLK_OWL_S900=y
-CONFIG_CLK_BCM2711_DVP=m
-CONFIG_CLK_BCM2835=y
-CONFIG_CLK_BCM_63XX=y
-CONFIG_COMMON_CLK_IPROC=y
-CONFIG_CLK_BCM_NS2=y
-CONFIG_CLK_BCM_SR=y
-CONFIG_CLK_RASPBERRYPI=m
-CONFIG_COMMON_CLK_HI3516CV300=y
-CONFIG_COMMON_CLK_HI3519=y
-CONFIG_COMMON_CLK_HI3559A=y
-CONFIG_COMMON_CLK_HI3660=y
-CONFIG_COMMON_CLK_HI3670=y
-CONFIG_COMMON_CLK_HI3798CV200=y
-CONFIG_COMMON_CLK_HI6220=y
-CONFIG_RESET_HISI=y
-CONFIG_STUB_CLK_HI6220=y
-# CONFIG_STUB_CLK_HI3660 is not set
-CONFIG_MXC_CLK=y
-CONFIG_MXC_CLK_SCU=y
-CONFIG_CLK_IMX8MM=y
-CONFIG_CLK_IMX8MN=y
-CONFIG_CLK_IMX8MP=y
-CONFIG_CLK_IMX8MQ=y
-CONFIG_CLK_IMX8QXP=y
-CONFIG_CLK_IMX8ULP=m
-CONFIG_CLK_IMX93=m
-# CONFIG_TI_SCI_CLK is not set
-CONFIG_TI_SYSCON_CLK=y
-
-#
-# Clock driver for MediaTek SoC
-#
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2712=y
-# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set
-# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set
-# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set
-# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set
-# CONFIG_COMMON_CLK_MT2712_MMSYS is not set
-# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set
-# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set
-CONFIG_COMMON_CLK_MT6765=y
-# CONFIG_COMMON_CLK_MT6765_AUDIOSYS is not set
-# CONFIG_COMMON_CLK_MT6765_CAMSYS is not set
-# CONFIG_COMMON_CLK_MT6765_GCESYS is not set
-# CONFIG_COMMON_CLK_MT6765_MMSYS is not set
-# CONFIG_COMMON_CLK_MT6765_IMGSYS is not set
-# CONFIG_COMMON_CLK_MT6765_VCODECSYS is not set
-# CONFIG_COMMON_CLK_MT6765_MFGSYS is not set
-# CONFIG_COMMON_CLK_MT6765_MIPI0ASYS is not set
-# CONFIG_COMMON_CLK_MT6765_MIPI0BSYS is not set
-# CONFIG_COMMON_CLK_MT6765_MIPI1ASYS is not set
-# CONFIG_COMMON_CLK_MT6765_MIPI1BSYS is not set
-# CONFIG_COMMON_CLK_MT6765_MIPI2ASYS is not set
-# CONFIG_COMMON_CLK_MT6765_MIPI2BSYS is not set
-CONFIG_COMMON_CLK_MT6779=y
-CONFIG_COMMON_CLK_MT6779_MMSYS=y
-CONFIG_COMMON_CLK_MT6779_IMGSYS=y
-CONFIG_COMMON_CLK_MT6779_IPESYS=y
-CONFIG_COMMON_CLK_MT6779_CAMSYS=y
-CONFIG_COMMON_CLK_MT6779_VDECSYS=y
-CONFIG_COMMON_CLK_MT6779_VENCSYS=y
-CONFIG_COMMON_CLK_MT6779_MFGCFG=y
-CONFIG_COMMON_CLK_MT6779_AUDSYS=y
-CONFIG_COMMON_CLK_MT6795=m
-CONFIG_COMMON_CLK_MT6795_MFGCFG=m
-CONFIG_COMMON_CLK_MT6795_MMSYS=m
-CONFIG_COMMON_CLK_MT6795_VDECSYS=m
-CONFIG_COMMON_CLK_MT6795_VENCSYS=m
-CONFIG_COMMON_CLK_MT6797=y
-# CONFIG_COMMON_CLK_MT6797_MMSYS is not set
-# CONFIG_COMMON_CLK_MT6797_IMGSYS is not set
-# CONFIG_COMMON_CLK_MT6797_VDECSYS is not set
-# CONFIG_COMMON_CLK_MT6797_VENCSYS is not set
-CONFIG_COMMON_CLK_MT7622=y
-# CONFIG_COMMON_CLK_MT7622_ETHSYS is not set
-# CONFIG_COMMON_CLK_MT7622_HIFSYS is not set
-# CONFIG_COMMON_CLK_MT7622_AUDSYS is not set
-CONFIG_COMMON_CLK_MT8167=y
-CONFIG_COMMON_CLK_MT8167_AUDSYS=y
-CONFIG_COMMON_CLK_MT8167_IMGSYS=y
-CONFIG_COMMON_CLK_MT8167_MFGCFG=y
-CONFIG_COMMON_CLK_MT8167_MMSYS=y
-CONFIG_COMMON_CLK_MT8167_VDECSYS=y
-CONFIG_COMMON_CLK_MT8173=y
-CONFIG_COMMON_CLK_MT8173_MMSYS=y
-CONFIG_COMMON_CLK_MT8365=m
-CONFIG_COMMON_CLK_MT8365_APU=m
-CONFIG_COMMON_CLK_MT8365_CAM=m
-CONFIG_COMMON_CLK_MT8365_MFG=m
-CONFIG_COMMON_CLK_MT8365_MMSYS=m
-CONFIG_COMMON_CLK_MT8365_VDEC=m
-CONFIG_COMMON_CLK_MT8365_VENC=m
-CONFIG_COMMON_CLK_MT8183=y
-# CONFIG_COMMON_CLK_MT8183_AUDIOSYS is not set
-# CONFIG_COMMON_CLK_MT8183_CAMSYS is not set
-# CONFIG_COMMON_CLK_MT8183_IMGSYS is not set
-# CONFIG_COMMON_CLK_MT8183_IPU_CORE0 is not set
-# CONFIG_COMMON_CLK_MT8183_IPU_CORE1 is not set
-# CONFIG_COMMON_CLK_MT8183_IPU_ADL is not set
-# CONFIG_COMMON_CLK_MT8183_IPU_CONN is not set
-# CONFIG_COMMON_CLK_MT8183_MFGCFG is not set
-# CONFIG_COMMON_CLK_MT8183_MMSYS is not set
-# CONFIG_COMMON_CLK_MT8183_VDECSYS is not set
-# CONFIG_COMMON_CLK_MT8183_VENCSYS is not set
-CONFIG_COMMON_CLK_MT8186=y
-CONFIG_COMMON_CLK_MT8192=y
-CONFIG_COMMON_CLK_MT8192_AUDSYS=y
-CONFIG_COMMON_CLK_MT8192_CAMSYS=y
-CONFIG_COMMON_CLK_MT8192_IMGSYS=y
-CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP=y
-CONFIG_COMMON_CLK_MT8192_IPESYS=y
-CONFIG_COMMON_CLK_MT8192_MDPSYS=y
-CONFIG_COMMON_CLK_MT8192_MFGCFG=y
-CONFIG_COMMON_CLK_MT8192_MMSYS=y
-CONFIG_COMMON_CLK_MT8192_MSDC=y
-CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y
-CONFIG_COMMON_CLK_MT8192_VDECSYS=y
-CONFIG_COMMON_CLK_MT8192_VENCSYS=y
-CONFIG_COMMON_CLK_MT8195=y
-CONFIG_COMMON_CLK_MT8516=y
-# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set
-# end of Clock driver for MediaTek SoC
-
-#
-# Clock support for Amlogic platforms
-#
-CONFIG_COMMON_CLK_MESON_REGMAP=y
-CONFIG_COMMON_CLK_MESON_DUALDIV=y
-CONFIG_COMMON_CLK_MESON_MPLL=y
-CONFIG_COMMON_CLK_MESON_PLL=y
-CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y
-CONFIG_COMMON_CLK_MESON_AO_CLKC=y
-CONFIG_COMMON_CLK_MESON_EE_CLKC=y
-CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y
-CONFIG_COMMON_CLK_GXBB=y
-CONFIG_COMMON_CLK_AXG=y
-# CONFIG_COMMON_CLK_AXG_AUDIO is not set
-CONFIG_COMMON_CLK_G12A=y
-# end of Clock support for Amlogic platforms
-
-CONFIG_ARMADA_AP_CP_HELPER=y
-CONFIG_ARMADA_37XX_CLK=y
-CONFIG_ARMADA_AP806_SYSCON=y
-CONFIG_ARMADA_CP110_SYSCON=y
-CONFIG_QCOM_GDSC=y
-CONFIG_QCOM_RPMCC=y
-CONFIG_COMMON_CLK_QCOM=y
-CONFIG_QCOM_A53PLL=y
-CONFIG_QCOM_A7PLL=m
-CONFIG_QCOM_CLK_APCS_MSM8916=m
-CONFIG_QCOM_CLK_APCC_MSM8996=m
-CONFIG_QCOM_CLK_APCS_SDX55=m
-CONFIG_QCOM_CLK_RPM=m
-CONFIG_QCOM_CLK_SMD_RPM=y
-# CONFIG_QCOM_CLK_RPMH is not set
-# CONFIG_APQ_GCC_8084 is not set
-# CONFIG_APQ_MMCC_8084 is not set
-CONFIG_IPQ_APSS_PLL=m
-CONFIG_IPQ_APSS_6018=m
-# CONFIG_IPQ_GCC_4019 is not set
-# CONFIG_IPQ_GCC_6018 is not set
-# CONFIG_IPQ_GCC_806X is not set
-# CONFIG_IPQ_LCC_806X is not set
-CONFIG_IPQ_GCC_8074=y
-# CONFIG_MSM_GCC_8660 is not set
-CONFIG_MSM_GCC_8909=m
-CONFIG_MSM_GCC_8916=y
-# CONFIG_MSM_GCC_8939 is not set
-# CONFIG_MSM_GCC_8960 is not set
-# CONFIG_MSM_LCC_8960 is not set
-CONFIG_MDM_GCC_9607=m
-# CONFIG_MDM_GCC_9615 is not set
-# CONFIG_MDM_LCC_9615 is not set
-# CONFIG_MSM_MMCC_8960 is not set
-CONFIG_MSM_GCC_8953=m
-# CONFIG_MSM_GCC_8974 is not set
-# CONFIG_MSM_MMCC_8974 is not set
-CONFIG_MSM_GCC_8976=m
-CONFIG_MSM_MMCC_8976=m
-CONFIG_MSM_MMCC_8994=m
-CONFIG_MSM_GCC_8994=y
-CONFIG_MSM_GCC_8996=y
-CONFIG_MSM_MMCC_8996=y
-CONFIG_MSM_GCC_8998=y
-CONFIG_MSM_GPUCC_8998=y
-CONFIG_MSM_MMCC_8998=y
-CONFIG_QCM_GCC_2290=m
-CONFIG_QCM_DISPCC_2290=m
-# CONFIG_QCS_GCC_404 is not set
-CONFIG_SC_CAMCC_7180=m
-CONFIG_SC_CAMCC_7280=m
-# CONFIG_SC_DISPCC_7180 is not set
-CONFIG_SC_DISPCC_7280=m
-CONFIG_SC_GCC_7180=m
-CONFIG_SC_GCC_7280=m
-CONFIG_SC_GCC_8180X=m
-CONFIG_SC_GCC_8280XP=m
-# CONFIG_SC_GPUCC_7180 is not set
-CONFIG_SC_GPUCC_7280=m
-CONFIG_SC_GPUCC_8280XP=m
-CONFIG_SC_LPASSCC_7280=m
-# CONFIG_SC_LPASS_CORECC_7180 is not set
-CONFIG_SC_LPASS_CORECC_7280=m
-# CONFIG_SC_MSS_7180 is not set
-# CONFIG_SC_VIDEOCC_7180 is not set
-CONFIG_SC_VIDEOCC_7280=m
-# CONFIG_SDM_CAMCC_845 is not set
-CONFIG_SDM_GCC_660=m
-CONFIG_SDM_MMCC_660=m
-CONFIG_SDM_GPUCC_660=m
-# CONFIG_QCS_TURING_404 is not set
-# CONFIG_QCS_Q6SSTOP_404 is not set
-# CONFIG_SDM_GCC_845 is not set
-# CONFIG_SDM_GPUCC_845 is not set
-# CONFIG_SDM_VIDEOCC_845 is not set
-# CONFIG_SDM_DISPCC_845 is not set
-# CONFIG_SDM_LPASSCC_845 is not set
-CONFIG_SDX_GCC_55=m
-CONFIG_SM_CAMCC_8250=m
-CONFIG_SM_CAMCC_8450=m
-CONFIG_SM_DISPCC_6115=m
-CONFIG_SM_DISPCC_6125=m
-CONFIG_SDX_GCC_65=m
-CONFIG_SM_DISPCC_8250=m
-CONFIG_SM_DISPCC_6350=m
-CONFIG_SM_DISPCC_8450=m
-CONFIG_SM_GCC_6115=m
-CONFIG_SM_GCC_6125=m
-CONFIG_SM_GCC_6350=m
-CONFIG_SM_GCC_6375=m
-CONFIG_SM_GCC_8150=m
-CONFIG_SM_GCC_8250=m
-CONFIG_SM_GCC_8350=m
-CONFIG_SM_GCC_8450=m
-CONFIG_SM_GPUCC_6350=m
-# CONFIG_SM_GPUCC_8150 is not set
-# CONFIG_SM_GPUCC_8250 is not set
-CONFIG_SM_GPUCC_8350=m
-CONFIG_SM_VIDEOCC_8150=m
-CONFIG_SM_VIDEOCC_8250=m
-# CONFIG_SPMI_PMIC_CLKDIV is not set
-# CONFIG_QCOM_HFPLL is not set
-# CONFIG_KPSS_XCC is not set
-CONFIG_CLK_GFM_LPASS_SM8250=m
-CONFIG_CLK_RENESAS=y
-CONFIG_CLK_R8A774A1=y
-CONFIG_CLK_R8A774B1=y
-CONFIG_CLK_R8A774C0=y
-CONFIG_CLK_R8A774E1=y
-CONFIG_CLK_R8A7795=y
-CONFIG_CLK_R8A77960=y
-CONFIG_CLK_R8A77961=y
-CONFIG_CLK_R8A77965=y
-CONFIG_CLK_R8A77970=y
-CONFIG_CLK_R8A77980=y
-CONFIG_CLK_R8A77990=y
-CONFIG_CLK_R8A77995=y
-CONFIG_CLK_R8A779A0=y
-CONFIG_CLK_R9A07G044=y
-CONFIG_CLK_RCAR_CPG_LIB=y
-CONFIG_CLK_RCAR_GEN3_CPG=y
-# CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set
-CONFIG_CLK_RZG2L=y
-CONFIG_CLK_RENESAS_CPG_MSSR=y
-CONFIG_CLK_RENESAS_DIV6=y
-CONFIG_COMMON_CLK_ROCKCHIP=y
-CONFIG_CLK_PX30=y
-CONFIG_CLK_RK3308=y
-CONFIG_CLK_RK3328=y
-CONFIG_CLK_RK3368=y
-CONFIG_CLK_RK3399=y
-CONFIG_CLK_RK3568=y
-CONFIG_COMMON_CLK_SAMSUNG=y
-CONFIG_EXYNOS_ARM64_COMMON_CLK=y
-CONFIG_EXYNOS_AUDSS_CLK_CON=y
-CONFIG_EXYNOS_CLKOUT=m
-CONFIG_CLK_INTEL_SOCFPGA=y
-CONFIG_CLK_INTEL_SOCFPGA64=y
-CONFIG_SPRD_COMMON_CLK=y
-CONFIG_SPRD_SC9860_CLK=y
-CONFIG_SPRD_SC9863A_CLK=y
-CONFIG_SPRD_UMS512_CLK=m
-CONFIG_CLK_SUNXI=y
-CONFIG_CLK_SUNXI_CLOCKS=y
-CONFIG_CLK_SUNXI_PRCM_SUN6I=y
-CONFIG_CLK_SUNXI_PRCM_SUN8I=y
-CONFIG_CLK_SUNXI_PRCM_SUN9I=y
-CONFIG_SUNXI_CCU=y
-CONFIG_SUN50I_A64_CCU=y
-CONFIG_SUN50I_A100_CCU=y
-CONFIG_SUN50I_A100_R_CCU=y
-CONFIG_SUN50I_H6_CCU=y
-CONFIG_SUN50I_H616_CCU=y
-CONFIG_SUN50I_H6_R_CCU=y
-CONFIG_SUN6I_RTC_CCU=m
-CONFIG_SUN8I_H3_CCU=y
-CONFIG_SUN8I_DE2_CCU=y
-CONFIG_SUN8I_R_CCU=y
-CONFIG_CLK_TEGRA_BPMP=y
-CONFIG_TEGRA_CLK_DFLL=y
-CONFIG_CLK_UNIPHIER=y
-CONFIG_COMMON_CLK_VISCONTI=y
-CONFIG_XILINX_VCU=m
-# CONFIG_COMMON_CLK_ZYNQMP is not set
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_TEGRA186_TIMER=y
-CONFIG_HWSPINLOCK=y
-# CONFIG_HWSPINLOCK_OMAP is not set
-CONFIG_HWSPINLOCK_QCOM=y
-# CONFIG_HWSPINLOCK_SPRD is not set
-CONFIG_HWSPINLOCK_SUN6I=m
-
-#
-# Clock Source drivers
-#
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_ACPI=y
-CONFIG_TIMER_PROBE=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_DW_APB_TIMER=y
-CONFIG_DW_APB_TIMER_OF=y
-CONFIG_ROCKCHIP_TIMER=y
-CONFIG_OWL_TIMER=y
-CONFIG_SUN4I_TIMER=y
-CONFIG_TEGRA_TIMER=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
-CONFIG_FSL_ERRATUM_A008585=y
-CONFIG_HISILICON_ERRATUM_161010101=y
-CONFIG_ARM64_ERRATUM_858921=y
-CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
-CONFIG_ARM_TIMER_SP804=y
-CONFIG_SYS_SUPPORTS_SH_CMT=y
-CONFIG_MTK_TIMER=y
-CONFIG_SPRD_TIMER=y
-CONFIG_SYS_SUPPORTS_SH_TMU=y
-CONFIG_SH_TIMER_CMT=y
-CONFIG_SH_TIMER_TMU=y
-CONFIG_TIMER_IMX_SYS_CTR=y
-CONFIG_MICROCHIP_PIT64B=y
-# end of Clock Source drivers
-
-CONFIG_MAILBOX=y
-CONFIG_APPLE_MAILBOX=m
-CONFIG_ARM_MHU=y
-CONFIG_ARM_MHU_V2=m
-CONFIG_IMX_MBOX=m
-CONFIG_PLATFORM_MHU=y
-CONFIG_PL320_MBOX=y
-CONFIG_ARMADA_37XX_RWTM_MBOX=m
-CONFIG_OMAP2PLUS_MBOX=m
-CONFIG_OMAP_MBOX_KFIFO_SIZE=256
-CONFIG_ROCKCHIP_MBOX=y
-CONFIG_PCC=y
-CONFIG_ALTERA_MBOX=m
-CONFIG_BCM2835_MBOX=y
-CONFIG_TI_MESSAGE_MANAGER=y
-CONFIG_HI3660_MBOX=m
-CONFIG_HI6220_MBOX=m
-CONFIG_MAILBOX_TEST=m
-CONFIG_QCOM_APCS_IPC=m
-CONFIG_TEGRA_HSP_MBOX=y
-CONFIG_XGENE_SLIMPRO_MBOX=m
-CONFIG_BCM_PDC_MBOX=m
-CONFIG_BCM_FLEXRM_MBOX=m
-CONFIG_MTK_ADSP_MBOX=m
-CONFIG_MTK_CMDQ_MBOX=m
-CONFIG_ZYNQMP_IPI_MBOX=y
-CONFIG_SUN6I_MSGBOX=y
-CONFIG_SPRD_MBOX=m
-CONFIG_QCOM_IPCC=m
-CONFIG_IOMMU_IOVA=y
-CONFIG_IOASID=y
-CONFIG_IOMMU_API=y
-CONFIG_IOMMU_SUPPORT=y
-
-#
-# Generic IOMMU Pagetable Support
-#
-CONFIG_IOMMU_IO_PGTABLE=y
-CONFIG_IOMMU_IO_PGTABLE_LPAE=y
-# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
-CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
-# end of Generic IOMMU Pagetable Support
-
-# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
-CONFIG_OF_IOMMU=y
-CONFIG_IOMMU_DMA=y
-CONFIG_IOMMU_SVA_LIB=y
-CONFIG_ROCKCHIP_IOMMU=y
-CONFIG_SUN50I_IOMMU=y
-CONFIG_TEGRA_IOMMU_SMMU=y
-CONFIG_EXYNOS_IOMMU=y
-# CONFIG_EXYNOS_IOMMU_DEBUG is not set
-CONFIG_IPMMU_VMSA=y
-CONFIG_APPLE_DART=m
-CONFIG_ARM_SMMU=y
-# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
-CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
-# CONFIG_ARM_SMMU_QCOM_DEBUG is not set
-CONFIG_ARM_SMMU_QCOM=y
-CONFIG_ARM_SMMU_V3=y
-CONFIG_ARM_SMMU_V3_SVA=y
-CONFIG_MTK_IOMMU=m
-CONFIG_QCOM_IOMMU=y
-CONFIG_VIRTIO_IOMMU=y
-CONFIG_SPRD_IOMMU=m
-
-#
-# Remoteproc drivers
-#
-# CONFIG_REMOTEPROC is not set
-# end of Remoteproc drivers
-
-#
-# Rpmsg drivers
-#
-CONFIG_RPMSG=y
-# CONFIG_RPMSG_CHAR is not set
-CONFIG_RPMSG_CTRL=m
-CONFIG_RPMSG_NS=m
-CONFIG_RPMSG_QCOM_GLINK=m
-CONFIG_RPMSG_QCOM_GLINK_RPM=m
-CONFIG_RPMSG_QCOM_GLINK_SMEM=m
-CONFIG_RPMSG_QCOM_SMD=y
-CONFIG_RPMSG_VIRTIO=m
-# end of Rpmsg drivers
-
-CONFIG_SOUNDWIRE=y
-
-#
-# SoundWire Devices
-#
-# CONFIG_SOUNDWIRE_INTEL is not set
-CONFIG_SOUNDWIRE_QCOM=m
-
-#
-# SOC (System On Chip) specific Drivers
-#
-# CONFIG_OWL_PM_DOMAINS is not set
-
-#
-# Amlogic SoC drivers
-#
-CONFIG_MESON_CANVAS=m
-CONFIG_MESON_CLK_MEASURE=y
-CONFIG_MESON_GX_SOCINFO=y
-CONFIG_MESON_GX_PM_DOMAINS=y
-CONFIG_MESON_EE_PM_DOMAINS=y
-CONFIG_MESON_SECURE_PM_DOMAINS=y
-# end of Amlogic SoC drivers
-
-#
-# Broadcom SoC drivers
-#
-CONFIG_BCM2835_POWER=y
-CONFIG_RASPBERRYPI_POWER=y
-CONFIG_SOC_BRCMSTB=y
-CONFIG_BCM_PMB=y
-CONFIG_BRCMSTB_PM=y
-# end of Broadcom SoC drivers
-
-#
-# NXP/Freescale QorIQ SoC drivers
-#
-# CONFIG_FSL_DPAA is not set
-CONFIG_QUICC_ENGINE=y
-CONFIG_UCC_SLOW=y
-CONFIG_UCC_FAST=y
-CONFIG_UCC=y
-CONFIG_QE_TDM=y
-CONFIG_FSL_GUTS=y
-CONFIG_DPAA2_CONSOLE=y
-CONFIG_FSL_RCPM=y
-# end of NXP/Freescale QorIQ SoC drivers
-
-#
-# i.MX SoC drivers
-#
-CONFIG_IMX_GPCV2_PM_DOMAINS=y
-CONFIG_SOC_IMX8M=y
-CONFIG_SOC_IMX9=m
-# end of i.MX SoC drivers
-
-#
-# Enable LiteX SoC Builder specific drivers
-#
-CONFIG_LITEX=y
-CONFIG_LITEX_SOC_CONTROLLER=m
-# end of Enable LiteX SoC Builder specific drivers
-
-#
-# MediaTek SoC drivers
-#
-CONFIG_MTK_CMDQ=m
-CONFIG_MTK_DEVAPC=m
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_PMIC_WRAP=m
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_MMSYS=y
-CONFIG_MTK_SVS=m
-# end of MediaTek SoC drivers
-
-#
-# Qualcomm SoC drivers
-#
-CONFIG_QCOM_AOSS_QMP=m
-CONFIG_QCOM_COMMAND_DB=y
-CONFIG_QCOM_CPR=m
-CONFIG_QCOM_GENI_SE=m
-CONFIG_QCOM_GSBI=m
-CONFIG_QCOM_LLCC=m
-CONFIG_QCOM_KRYO_L2_ACCESSORS=y
-CONFIG_QCOM_MDT_LOADER=m
-CONFIG_QCOM_OCMEM=m
-CONFIG_QCOM_PDR_HELPERS=m
-CONFIG_QCOM_QMI_HELPERS=m
-CONFIG_QCOM_RMTFS_MEM=m
-CONFIG_QCOM_RPMH=m
-CONFIG_QCOM_RPMHPD=m
-CONFIG_QCOM_RPMPD=m
-CONFIG_QCOM_SMEM=y
-CONFIG_QCOM_SMD_RPM=y
-CONFIG_QCOM_SMEM_STATE=y
-CONFIG_QCOM_SMP2P=y
-CONFIG_QCOM_SMSM=y
-CONFIG_QCOM_SOCINFO=m
-CONFIG_QCOM_SPM=m
-CONFIG_QCOM_WCNSS_CTRL=m
-CONFIG_QCOM_APR=m
-CONFIG_QCOM_ICC_BWMON=m
-# end of Qualcomm SoC drivers
-
-CONFIG_SOC_RENESAS=y
-CONFIG_ARCH_RCAR_GEN3=y
-CONFIG_ARCH_R8A77995=y
-CONFIG_ARCH_R8A77990=y
-CONFIG_ARCH_R8A77950=y
-CONFIG_ARCH_R8A77951=y
-CONFIG_ARCH_R8A77965=y
-CONFIG_ARCH_R8A77960=y
-CONFIG_ARCH_R8A77961=y
-CONFIG_ARCH_R8A779F0=y
-CONFIG_ARCH_R8A77980=y
-CONFIG_ARCH_R8A77970=y
-CONFIG_ARCH_R8A779A0=y
-CONFIG_ARCH_R8A774C0=y
-CONFIG_ARCH_R8A774E1=y
-CONFIG_ARCH_R8A774A1=y
-CONFIG_ARCH_R8A774B1=y
-CONFIG_ARCH_R8A779G0=y
-CONFIG_ARCH_R9A07G043=y
-CONFIG_ARCH_R9A09G011=y
-CONFIG_ARCH_R9A07G044=y
-CONFIG_ARCH_R9A07G054=y
-CONFIG_RST_RCAR=y
-CONFIG_SYSC_RCAR=y
-CONFIG_SYSC_R8A77995=y
-CONFIG_SYSC_R8A77990=y
-CONFIG_SYSC_R8A7795=y
-CONFIG_SYSC_R8A77965=y
-CONFIG_SYSC_R8A77960=y
-CONFIG_SYSC_R8A77961=y
-CONFIG_SYSC_R8A77980=y
-CONFIG_SYSC_R8A77970=y
-CONFIG_SYSC_R8A779A0=y
-CONFIG_SYSC_R8A774C0=y
-CONFIG_SYSC_R8A774E1=y
-CONFIG_SYSC_R8A774A1=y
-CONFIG_SYSC_R8A774B1=y
-CONFIG_ROCKCHIP_GRF=y
-CONFIG_ROCKCHIP_IODOMAIN=y
-CONFIG_ROCKCHIP_PM_DOMAINS=y
-CONFIG_ROCKCHIP_DTPM=m
-CONFIG_SOC_SAMSUNG=y
-CONFIG_EXYNOS_CHIPID=y
-CONFIG_EXYNOS_PMU=y
-CONFIG_EXYNOS_PM_DOMAINS=y
-CONFIG_SUNXI_MBUS=y
-CONFIG_SUNXI_SRAM=y
-CONFIG_ARCH_TEGRA_132_SOC=y
-CONFIG_ARCH_TEGRA_210_SOC=y
-CONFIG_ARCH_TEGRA_186_SOC=y
-CONFIG_ARCH_TEGRA_194_SOC=y
-CONFIG_ARCH_TEGRA_234_SOC=y
-CONFIG_SOC_TEGRA_CBB=m
-CONFIG_SOC_TEGRA_FUSE=y
-CONFIG_SOC_TEGRA_FLOWCTRL=y
-CONFIG_SOC_TEGRA_PMC=y
-CONFIG_SOC_TEGRA_POWERGATE_BPMP=y
-CONFIG_SOC_TI=y
-CONFIG_TI_SCI_PM_DOMAINS=m
-CONFIG_TI_K3_RINGACC=y
-CONFIG_TI_K3_SOCINFO=y
-CONFIG_TI_PRUSS=m
-CONFIG_TI_SCI_INTA_MSI_DOMAIN=y
-
-#
-# Xilinx SoC drivers
-#
-CONFIG_ZYNQMP_POWER=y
-CONFIG_ZYNQMP_PM_DOMAINS=y
-CONFIG_XLNX_EVENT_MANAGER=y
-# end of Xilinx SoC drivers
-# end of SOC (System On Chip) specific Drivers
-
-CONFIG_PM_DEVFREQ=y
-
-#
-# DEVFREQ Governors
-#
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_PERFORMANCE=y
-CONFIG_DEVFREQ_GOV_POWERSAVE=m
-CONFIG_DEVFREQ_GOV_USERSPACE=m
-CONFIG_DEVFREQ_GOV_PASSIVE=m
-
-#
-# DEVFREQ Drivers
-#
-# CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set
-# CONFIG_ARM_IMX_BUS_DEVFREQ is not set
-CONFIG_ARM_IMX8M_DDRC_DEVFREQ=m
-# CONFIG_ARM_TEGRA_DEVFREQ is not set
-CONFIG_ARM_RK3399_DMC_DEVFREQ=y
-CONFIG_PM_DEVFREQ_EVENT=y
-CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=m
-CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU=m
-CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
-CONFIG_EXTCON=y
-
-#
-# Extcon Device Drivers
-#
-# CONFIG_EXTCON_ADC_JACK is not set
-# CONFIG_EXTCON_FSA9480 is not set
-# CONFIG_EXTCON_GPIO is not set
-# CONFIG_EXTCON_MAX3355 is not set
-# CONFIG_EXTCON_PTN5150 is not set
-CONFIG_EXTCON_QCOM_SPMI_MISC=m
-# CONFIG_EXTCON_RT8973A is not set
-# CONFIG_EXTCON_SM5502 is not set
-CONFIG_EXTCON_USB_GPIO=y
-# CONFIG_EXTCON_USBC_CROS_EC is not set
-CONFIG_EXTCON_USBC_TUSB320=m
-CONFIG_MEMORY=y
-# CONFIG_ARM_PL172_MPMC is not set
-CONFIG_BRCMSTB_DPFE=y
-CONFIG_BRCMSTB_MEMC=m
-CONFIG_OMAP_GPMC=m
-# CONFIG_OMAP_GPMC_DEBUG is not set
-CONFIG_MTK_SMI=m
-CONFIG_RENESAS_RPCIF=m
-CONFIG_TEGRA_MC=y
-CONFIG_TEGRA210_EMC_TABLE=y
-CONFIG_TEGRA210_EMC=m
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_BUFFER_CB=m
-CONFIG_IIO_BUFFER_DMA=m
-CONFIG_IIO_BUFFER_DMAENGINE=m
-CONFIG_IIO_BUFFER_HW_CONSUMER=m
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_TRIGGERED_BUFFER=y
-# CONFIG_IIO_CONFIGFS is not set
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
-# CONFIG_IIO_SW_DEVICE is not set
-# CONFIG_IIO_SW_TRIGGER is not set
-CONFIG_IIO_TRIGGERED_EVENT=m
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16201=m
-CONFIG_ADIS16209=m
-CONFIG_ADXL313=m
-CONFIG_ADXL313_I2C=m
-CONFIG_ADXL313_SPI=m
-CONFIG_ADXL345=m
-CONFIG_ADXL345_I2C=m
-CONFIG_ADXL345_SPI=m
-CONFIG_ADXL355=m
-CONFIG_ADXL355_I2C=m
-CONFIG_ADXL355_SPI=m
-CONFIG_ADXL367_SPI=m
-CONFIG_ADXL367_I2C=m
-CONFIG_ADXL372=m
-CONFIG_ADXL372_SPI=m
-CONFIG_ADXL372_I2C=m
-CONFIG_BMA180=m
-CONFIG_BMA220=m
-CONFIG_BMA400=m
-CONFIG_BMA400_I2C=m
-CONFIG_BMA400_SPI=m
-CONFIG_BMC150_ACCEL=m
-CONFIG_BMC150_ACCEL_I2C=m
-CONFIG_BMC150_ACCEL_SPI=m
-CONFIG_BMI088_ACCEL=m
-CONFIG_BMI088_ACCEL_SPI=m
-CONFIG_DA280=m
-CONFIG_DA311=m
-CONFIG_DMARD06=m
-CONFIG_DMARD09=m
-CONFIG_DMARD10=m
-CONFIG_FXLS8962AF=m
-CONFIG_FXLS8962AF_I2C=m
-CONFIG_FXLS8962AF_SPI=m
-CONFIG_HID_SENSOR_ACCEL_3D=m
-# CONFIG_IIO_CROS_EC_ACCEL_LEGACY is not set
-CONFIG_IIO_ST_ACCEL_3AXIS=m
-CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
-CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
-CONFIG_KXSD9=m
-CONFIG_KXSD9_SPI=m
-CONFIG_KXSD9_I2C=m
-CONFIG_KXCJK1013=m
-CONFIG_MC3230=m
-CONFIG_MMA7455=m
-CONFIG_MMA7455_I2C=m
-CONFIG_MMA7455_SPI=m
-CONFIG_MMA7660=m
-CONFIG_MMA8452=m
-CONFIG_MMA9551_CORE=m
-CONFIG_MMA9551=m
-CONFIG_MMA9553=m
-CONFIG_MSA311=m
-CONFIG_MXC4005=m
-CONFIG_MXC6255=m
-CONFIG_SCA3000=m
-CONFIG_SCA3300=m
-CONFIG_STK8312=m
-CONFIG_STK8BA50=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD_SIGMA_DELTA=m
-CONFIG_AD7091R5=m
-CONFIG_AD7124=m
-CONFIG_AD7192=m
-CONFIG_AD7266=m
-CONFIG_AD7291=m
-CONFIG_AD7292=m
-CONFIG_AD7298=m
-CONFIG_AD7476=m
-CONFIG_AD7606=m
-CONFIG_AD7606_IFACE_PARALLEL=m
-CONFIG_AD7606_IFACE_SPI=m
-CONFIG_AD7766=m
-CONFIG_AD7768_1=m
-CONFIG_AD7780=m
-CONFIG_AD7791=m
-CONFIG_AD7793=m
-CONFIG_AD7887=m
-CONFIG_AD7923=m
-CONFIG_AD7949=m
-CONFIG_AD799X=m
-CONFIG_AD9467=m
-CONFIG_ADI_AXI_ADC=m
-CONFIG_AXP20X_ADC=m
-CONFIG_AXP288_ADC=m
-CONFIG_BCM_IPROC_ADC=m
-CONFIG_BERLIN2_ADC=m
-CONFIG_CC10001_ADC=m
-CONFIG_ENVELOPE_DETECTOR=m
-CONFIG_EXYNOS_ADC=m
-CONFIG_HI8435=m
-CONFIG_HX711=m
-CONFIG_INA2XX_ADC=m
-CONFIG_IMX7D_ADC=m
-CONFIG_IMX8QXP_ADC=m
-CONFIG_LTC2471=m
-CONFIG_LTC2485=m
-CONFIG_LTC2496=m
-CONFIG_LTC2497=m
-CONFIG_MAX1027=m
-CONFIG_MAX11100=m
-CONFIG_MAX1118=m
-CONFIG_MAX11205=m
-CONFIG_MAX1241=m
-CONFIG_MAX1363=m
-CONFIG_MAX9611=m
-CONFIG_MCP320X=m
-CONFIG_MCP3422=m
-CONFIG_MCP3911=m
-CONFIG_MEDIATEK_MT6577_AUXADC=m
-CONFIG_MESON_SARADC=m
-CONFIG_NAU7802=m
-CONFIG_QCOM_VADC_COMMON=m
-CONFIG_QCOM_SPMI_IADC=m
-CONFIG_QCOM_SPMI_VADC=m
-CONFIG_QCOM_SPMI_ADC5=m
-CONFIG_ROCKCHIP_SARADC=y
-CONFIG_RICHTEK_RTQ6056=m
-CONFIG_RZG2L_ADC=m
-CONFIG_SD_ADC_MODULATOR=m
-CONFIG_SUN4I_GPADC=m
-CONFIG_TI_ADC081C=m
-CONFIG_TI_ADC0832=m
-CONFIG_TI_ADC084S021=m
-CONFIG_TI_ADC12138=m
-CONFIG_TI_ADC108S102=m
-CONFIG_TI_ADC128S052=m
-CONFIG_TI_ADC161S626=m
-CONFIG_TI_ADS1015=m
-CONFIG_TI_ADS7950=m
-CONFIG_TI_ADS8344=m
-CONFIG_TI_ADS8688=m
-CONFIG_TI_ADS124S08=m
-CONFIG_TI_ADS131E08=m
-CONFIG_TI_TLC4541=m
-CONFIG_TI_TSC2046=m
-CONFIG_VF610_ADC=m
-CONFIG_XILINX_XADC=m
-CONFIG_XILINX_AMS=m
-# end of Analog to digital converters
-
-#
-# Analog Front Ends
-#
-CONFIG_IIO_RESCALE=m
-# end of Analog Front Ends
-
-#
-# Amplifiers
-#
-CONFIG_AD8366=m
-CONFIG_ADA4250=m
-CONFIG_HMC425=m
-# end of Amplifiers
-
-#
-# Capacitance to digital converters
-#
-CONFIG_AD7150=m
-# end of Capacitance to digital converters
-
-#
-# Chemical Sensors
-#
-CONFIG_ATLAS_PH_SENSOR=m
-CONFIG_ATLAS_EZO_SENSOR=m
-CONFIG_BME680=m
-CONFIG_BME680_I2C=m
-CONFIG_BME680_SPI=m
-CONFIG_CCS811=m
-CONFIG_IAQCORE=m
-CONFIG_PMS7003=m
-CONFIG_SCD30_CORE=m
-CONFIG_SCD30_I2C=m
-CONFIG_SCD30_SERIAL=m
-CONFIG_SCD4X=m
-CONFIG_SENSIRION_SGP30=m
-CONFIG_SENSIRION_SGP40=m
-CONFIG_SPS30=m
-CONFIG_SPS30_I2C=m
-CONFIG_SPS30_SERIAL=m
-CONFIG_SENSEAIR_SUNRISE_CO2=m
-CONFIG_VZ89X=m
-# end of Chemical Sensors
-
-CONFIG_IIO_CROS_EC_SENSORS_CORE=m
-CONFIG_IIO_CROS_EC_SENSORS=m
-CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m
-
-#
-# Hid Sensor IIO Common
-#
-CONFIG_HID_SENSOR_IIO_COMMON=m
-CONFIG_HID_SENSOR_IIO_TRIGGER=m
-# end of Hid Sensor IIO Common
-
-CONFIG_IIO_MS_SENSORS_I2C=m
-
-#
-# IIO SCMI Sensors
-#
-# end of IIO SCMI Sensors
-
-#
-# SSP Sensor Common
-#
-CONFIG_IIO_SSP_SENSORS_COMMONS=m
-CONFIG_IIO_SSP_SENSORHUB=m
-# end of SSP Sensor Common
-
-CONFIG_IIO_ST_SENSORS_I2C=m
-CONFIG_IIO_ST_SENSORS_SPI=m
-CONFIG_IIO_ST_SENSORS_CORE=m
-
-#
-# Digital to analog converters
-#
-CONFIG_AD5064=m
-CONFIG_AD5360=m
-CONFIG_AD5380=m
-CONFIG_AD5421=m
-CONFIG_AD5446=m
-CONFIG_AD5449=m
-CONFIG_AD5592R_BASE=m
-CONFIG_AD5592R=m
-CONFIG_AD5593R=m
-CONFIG_AD5504=m
-CONFIG_AD5624R_SPI=m
-CONFIG_LTC2688=m
-CONFIG_AD5686=m
-CONFIG_AD5686_SPI=m
-CONFIG_AD5696_I2C=m
-CONFIG_AD5755=m
-CONFIG_AD5758=m
-CONFIG_AD5761=m
-CONFIG_AD5764=m
-CONFIG_AD5766=m
-CONFIG_AD5770R=m
-CONFIG_AD5791=m
-CONFIG_AD7303=m
-CONFIG_AD8801=m
-CONFIG_DPOT_DAC=m
-CONFIG_DS4424=m
-CONFIG_LTC1660=m
-CONFIG_LTC2632=m
-CONFIG_M62332=m
-CONFIG_MAX517=m
-CONFIG_MAX5821=m
-CONFIG_MCP4725=m
-CONFIG_MCP4922=m
-CONFIG_TI_DAC082S085=m
-CONFIG_TI_DAC5571=m
-CONFIG_TI_DAC7311=m
-CONFIG_TI_DAC7612=m
-CONFIG_VF610_DAC=m
-# end of Digital to analog converters
-
-#
-# IIO dummy driver
-#
-# end of IIO dummy driver
-
-#
-# Frequency Synthesizers DDS/PLL
-#
-
-#
-# Clock Generator/Distribution
-#
-CONFIG_AD9523=m
-# end of Clock Generator/Distribution
-
-#
-# Phase-Locked Loop (PLL) frequency synthesizers
-#
-CONFIG_ADF4350=m
-CONFIG_ADF4371=m
-CONFIG_ADRF6780=m
-# end of Phase-Locked Loop (PLL) frequency synthesizers
-# end of Frequency Synthesizers DDS/PLL
-
-#
-# Digital gyroscope sensors
-#
-CONFIG_ADIS16080=m
-CONFIG_ADIS16130=m
-CONFIG_ADIS16136=m
-CONFIG_ADIS16260=m
-CONFIG_ADXRS290=m
-CONFIG_ADXRS450=m
-CONFIG_BMG160=m
-CONFIG_BMG160_I2C=m
-CONFIG_BMG160_SPI=m
-CONFIG_FXAS21002C=m
-CONFIG_FXAS21002C_I2C=m
-CONFIG_FXAS21002C_SPI=m
-CONFIG_HID_SENSOR_GYRO_3D=m
-CONFIG_MPU3050=m
-CONFIG_MPU3050_I2C=m
-CONFIG_IIO_ST_GYRO_3AXIS=m
-CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
-CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
-CONFIG_ITG3200=m
-# end of Digital gyroscope sensors
-
-#
-# Health Sensors
-#
-
-#
-# Heart Rate Monitors
-#
-CONFIG_AFE4403=m
-CONFIG_AFE4404=m
-CONFIG_MAX30100=m
-CONFIG_MAX30102=m
-# end of Heart Rate Monitors
-# end of Health Sensors
-
-#
-# Humidity sensors
-#
-CONFIG_AM2315=m
-CONFIG_DHT11=m
-CONFIG_HDC100X=m
-CONFIG_HDC2010=m
-CONFIG_HID_SENSOR_HUMIDITY=m
-CONFIG_HTS221=m
-CONFIG_HTS221_I2C=m
-CONFIG_HTS221_SPI=m
-CONFIG_HTU21=m
-CONFIG_SI7005=m
-CONFIG_SI7020=m
-# end of Humidity sensors
-
-#
-# Inertial measurement units
-#
-CONFIG_ADIS16400=m
-CONFIG_ADIS16460=m
-CONFIG_ADIS16475=m
-CONFIG_ADIS16480=m
-CONFIG_BMI160=m
-CONFIG_BMI160_I2C=m
-CONFIG_BMI160_SPI=m
-CONFIG_BOSCH_BNO055_SERIAL=m
-CONFIG_BOSCH_BNO055_I2C=m
-CONFIG_FXOS8700=m
-CONFIG_FXOS8700_I2C=m
-CONFIG_FXOS8700_SPI=m
-CONFIG_KMX61=m
-CONFIG_INV_ICM42600=m
-CONFIG_INV_ICM42600_I2C=m
-CONFIG_INV_ICM42600_SPI=m
-CONFIG_INV_MPU6050_IIO=m
-CONFIG_INV_MPU6050_I2C=m
-CONFIG_INV_MPU6050_SPI=m
-CONFIG_IIO_ST_LSM6DSX=m
-CONFIG_IIO_ST_LSM6DSX_I2C=m
-CONFIG_IIO_ST_LSM6DSX_SPI=m
-CONFIG_IIO_ST_LSM6DSX_I3C=m
-CONFIG_IIO_ST_LSM9DS0=m
-CONFIG_IIO_ST_LSM9DS0_I2C=m
-CONFIG_IIO_ST_LSM9DS0_SPI=m
-# end of Inertial measurement units
-
-CONFIG_IIO_ADIS_LIB=m
-CONFIG_IIO_ADIS_LIB_BUFFER=y
-
-#
-# Light sensors
-#
-CONFIG_ACPI_ALS=m
-CONFIG_ADJD_S311=m
-CONFIG_ADUX1020=m
-CONFIG_AL3010=m
-CONFIG_AL3320A=m
-CONFIG_APDS9300=m
-CONFIG_APDS9960=m
-CONFIG_AS73211=m
-CONFIG_BH1750=m
-CONFIG_BH1780=m
-CONFIG_CM32181=m
-CONFIG_CM3232=m
-CONFIG_CM3323=m
-CONFIG_CM3605=m
-CONFIG_CM36651=m
-CONFIG_IIO_CROS_EC_LIGHT_PROX=m
-CONFIG_GP2AP002=m
-CONFIG_GP2AP020A00F=m
-CONFIG_SENSORS_ISL29018=m
-CONFIG_SENSORS_ISL29028=m
-CONFIG_ISL29125=m
-CONFIG_HID_SENSOR_ALS=m
-CONFIG_HID_SENSOR_PROX=m
-CONFIG_JSA1212=m
-CONFIG_RPR0521=m
-CONFIG_LTR501=m
-CONFIG_LTRF216A=m
-CONFIG_LV0104CS=m
-CONFIG_MAX44000=m
-CONFIG_MAX44009=m
-CONFIG_NOA1305=m
-CONFIG_OPT3001=m
-CONFIG_PA12203001=m
-CONFIG_SI1133=m
-CONFIG_SI1145=m
-CONFIG_STK3310=m
-CONFIG_ST_UVIS25=m
-CONFIG_ST_UVIS25_I2C=m
-CONFIG_ST_UVIS25_SPI=m
-CONFIG_TCS3414=m
-CONFIG_TCS3472=m
-CONFIG_SENSORS_TSL2563=m
-CONFIG_TSL2583=m
-CONFIG_TSL2591=m
-CONFIG_TSL2772=m
-CONFIG_TSL4531=m
-CONFIG_US5182D=m
-CONFIG_VCNL4000=m
-CONFIG_VCNL4035=m
-CONFIG_VEML6030=m
-CONFIG_VEML6070=m
-CONFIG_VL6180=m
-CONFIG_ZOPT2201=m
-# end of Light sensors
-
-#
-# Magnetometer sensors
-#
-CONFIG_AK8974=m
-CONFIG_AK8975=m
-CONFIG_AK09911=m
-CONFIG_BMC150_MAGN=m
-CONFIG_BMC150_MAGN_I2C=m
-CONFIG_BMC150_MAGN_SPI=m
-CONFIG_MAG3110=m
-CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
-CONFIG_MMC35240=m
-CONFIG_IIO_ST_MAGN_3AXIS=m
-CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
-CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
-CONFIG_SENSORS_HMC5843=m
-CONFIG_SENSORS_HMC5843_I2C=m
-CONFIG_SENSORS_HMC5843_SPI=m
-CONFIG_SENSORS_RM3100=m
-CONFIG_SENSORS_RM3100_I2C=m
-CONFIG_SENSORS_RM3100_SPI=m
-CONFIG_YAMAHA_YAS530=m
-# end of Magnetometer sensors
-
-#
-# Multiplexers
-#
-CONFIG_IIO_MUX=m
-# end of Multiplexers
-
-#
-# Inclinometer sensors
-#
-CONFIG_HID_SENSOR_INCLINOMETER_3D=m
-CONFIG_HID_SENSOR_DEVICE_ROTATION=m
-# end of Inclinometer sensors
-
-#
-# Triggers - standalone
-#
-CONFIG_IIO_INTERRUPT_TRIGGER=m
-CONFIG_IIO_SYSFS_TRIGGER=m
-# end of Triggers - standalone
-
-#
-# Linear and angular position sensors
-#
-CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
-# end of Linear and angular position sensors
-
-#
-# Digital potentiometers
-#
-CONFIG_AD5110=m
-CONFIG_AD5272=m
-CONFIG_DS1803=m
-CONFIG_MAX5432=m
-CONFIG_MAX5481=m
-CONFIG_MAX5487=m
-CONFIG_MCP4018=m
-CONFIG_MCP4131=m
-CONFIG_MCP4531=m
-CONFIG_MCP41010=m
-CONFIG_TPL0102=m
-# end of Digital potentiometers
-
-#
-# Digital potentiostats
-#
-CONFIG_LMP91000=m
-# end of Digital potentiostats
-
-#
-# Pressure sensors
-#
-CONFIG_ABP060MG=m
-CONFIG_BMP280=m
-CONFIG_BMP280_I2C=m
-CONFIG_BMP280_SPI=m
-CONFIG_IIO_CROS_EC_BARO=m
-CONFIG_DLHL60D=m
-CONFIG_DPS310=m
-CONFIG_HID_SENSOR_PRESS=m
-CONFIG_HP03=m
-CONFIG_ICP10100=m
-CONFIG_MPL115=m
-CONFIG_MPL115_I2C=m
-CONFIG_MPL115_SPI=m
-CONFIG_MPL3115=m
-CONFIG_MS5611=m
-CONFIG_MS5611_I2C=m
-CONFIG_MS5611_SPI=m
-CONFIG_MS5637=m
-CONFIG_IIO_ST_PRESS=m
-CONFIG_IIO_ST_PRESS_I2C=m
-CONFIG_IIO_ST_PRESS_SPI=m
-CONFIG_T5403=m
-CONFIG_HP206C=m
-CONFIG_ZPA2326=m
-CONFIG_ZPA2326_I2C=m
-CONFIG_ZPA2326_SPI=m
-# end of Pressure sensors
-
-#
-# Lightning sensors
-#
-CONFIG_AS3935=m
-# end of Lightning sensors
-
-#
-# Proximity and distance sensors
-#
-CONFIG_CROS_EC_MKBP_PROXIMITY=m
-CONFIG_ISL29501=m
-CONFIG_LIDAR_LITE_V2=m
-CONFIG_MB1232=m
-CONFIG_PING=m
-CONFIG_RFD77402=m
-CONFIG_SRF04=m
-CONFIG_SX9310=m
-CONFIG_SX9324=m
-CONFIG_SX9360=m
-CONFIG_SX9500=m
-CONFIG_SRF08=m
-CONFIG_VCNL3020=m
-CONFIG_VL53L0X_I2C=m
-# end of Proximity and distance sensors
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S90=m
-CONFIG_AD2S1200=m
-# end of Resolver to digital converters
-
-#
-# Temperature sensors
-#
-CONFIG_LTC2983=m
-CONFIG_MAXIM_THERMOCOUPLE=m
-CONFIG_HID_SENSOR_TEMP=m
-CONFIG_MLX90614=m
-CONFIG_MLX90632=m
-CONFIG_TMP006=m
-CONFIG_TMP007=m
-CONFIG_TMP117=m
-CONFIG_TSYS01=m
-CONFIG_TSYS02D=m
-CONFIG_MAX31856=m
-CONFIG_MAX31865=m
-# end of Temperature sensors
-
-# CONFIG_NTB is not set
-# CONFIG_VME_BUS is not set
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_PWM_DEBUG is not set
-CONFIG_PWM_ATMEL_TCB=m
-CONFIG_PWM_BCM_IPROC=y
-CONFIG_PWM_BCM2835=m
-# CONFIG_PWM_BERLIN is not set
-# CONFIG_PWM_BRCMSTB is not set
-CONFIG_PWM_CROS_EC=m
-CONFIG_PWM_DWC=m
-# CONFIG_PWM_FSL_FTM is not set
-# CONFIG_PWM_HIBVT is not set
-CONFIG_PWM_IMX1=m
-CONFIG_PWM_IMX27=m
-CONFIG_PWM_IMX_TPM=m
-CONFIG_PWM_KEEMBAY=m
-CONFIG_PWM_MESON=m
-# CONFIG_PWM_MTK_DISP is not set
-# CONFIG_PWM_MEDIATEK is not set
-CONFIG_PWM_NTXEC=m
-# CONFIG_PWM_PCA9685 is not set
-CONFIG_PWM_RASPBERRYPI_POE=m
-CONFIG_PWM_RCAR=m
-# CONFIG_PWM_RENESAS_TPU is not set
-CONFIG_PWM_ROCKCHIP=y
-CONFIG_PWM_SAMSUNG=y
-CONFIG_PWM_SL28CPLD=m
-# CONFIG_PWM_SPRD is not set
-CONFIG_PWM_SUN4I=m
-CONFIG_PWM_TEGRA=m
-# CONFIG_PWM_TIECAP is not set
-# CONFIG_PWM_TIEHRPWM is not set
-CONFIG_PWM_VISCONTI=m
-
-#
-# IRQ chip support
-#
-CONFIG_IRQCHIP=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_PM=y
-CONFIG_ARM_GIC_MAX_NR=1
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ALPINE_MSI=y
-# CONFIG_AL_FIC is not set
-CONFIG_BCM7038_L1_IRQ=y
-CONFIG_BCM7120_L2_IRQ=m
-CONFIG_BRCMSTB_L2_IRQ=y
-CONFIG_DW_APB_ICTL=y
-CONFIG_HISILICON_IRQ_MBIGEN=y
-CONFIG_MADERA_IRQ=m
-CONFIG_RENESAS_IRQC=y
-CONFIG_XILINX_INTC=y
-CONFIG_IMX_GPCV2=y
-CONFIG_MVEBU_GICP=y
-CONFIG_MVEBU_ICU=y
-CONFIG_MVEBU_ODMI=y
-CONFIG_MVEBU_PIC=y
-CONFIG_MVEBU_SEI=y
-CONFIG_LS_EXTIRQ=y
-CONFIG_LS_SCFG_MSI=y
-CONFIG_PARTITION_PERCPU=y
-# CONFIG_QCOM_IRQ_COMBINER is not set
-CONFIG_IRQ_UNIPHIER_AIDET=y
-CONFIG_MESON_IRQ_GPIO=y
-# CONFIG_QCOM_PDC is not set
-CONFIG_QCOM_MPM=m
-CONFIG_IMX_IRQSTEER=y
-CONFIG_IMX_MU_MSI=m
-CONFIG_IMX_INTMUX=y
-CONFIG_TI_SCI_INTR_IRQCHIP=y
-CONFIG_TI_SCI_INTA_IRQCHIP=y
-CONFIG_TI_PRUSS_INTC=m
-CONFIG_MST_IRQ=y
-CONFIG_APPLE_AIC=y
-# end of IRQ chip support
-
-# CONFIG_IPACK_BUS is not set
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_A10SR=m
-CONFIG_RESET_BERLIN=y
-CONFIG_RESET_BRCMSTB=y
-CONFIG_RESET_BRCMSTB_RESCAL=y
-CONFIG_RESET_IMX7=y
-CONFIG_RESET_MCHP_SPARX5=y
-CONFIG_RESET_MESON=y
-# CONFIG_RESET_MESON_AUDIO_ARB is not set
-# CONFIG_RESET_QCOM_AOSS is not set
-# CONFIG_RESET_QCOM_PDC is not set
-CONFIG_RESET_RASPBERRYPI=m
-CONFIG_RESET_RZG2L_USBPHY_CTRL=m
-CONFIG_RESET_SIMPLE=y
-CONFIG_RESET_SUNXI=y
-# CONFIG_RESET_TI_SCI is not set
-CONFIG_RESET_TI_SYSCON=m
-CONFIG_RESET_UNIPHIER=y
-CONFIG_RESET_UNIPHIER_GLUE=y
-CONFIG_COMMON_RESET_HI3660=y
-CONFIG_COMMON_RESET_HI6220=y
-CONFIG_RESET_TEGRA_BPMP=y
-
-#
-# PHY Subsystem
-#
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PHY_MIPI_DPHY=y
-# CONFIG_PHY_XGENE is not set
-CONFIG_PHY_CAN_TRANSCEIVER=m
-CONFIG_PHY_SUN4I_USB=y
-CONFIG_PHY_SUN6I_MIPI_DPHY=m
-# CONFIG_PHY_SUN9I_USB is not set
-CONFIG_PHY_SUN50I_USB3=m
-CONFIG_PHY_MESON8B_USB2=m
-CONFIG_PHY_MESON_GXL_USB2=y
-CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=m
-CONFIG_PHY_MIXEL_LVDS_PHY=m
-CONFIG_PHY_MTK_PCIE=m
-CONFIG_PHY_MTK_DP=m
-CONFIG_PHY_MESON_G12A_USB2=y
-CONFIG_PHY_MESON_G12A_USB3_PCIE=y
-CONFIG_PHY_MESON_AXG_PCIE=y
-CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
-CONFIG_PHY_MESON_AXG_MIPI_DPHY=m
-
-#
-# PHY drivers for Broadcom platforms
-#
-CONFIG_PHY_BCM_SR_USB=y
-# CONFIG_BCM_KONA_USB2_PHY is not set
-# CONFIG_PHY_BCM_NS_USB2 is not set
-# CONFIG_PHY_BCM_NS_USB3 is not set
-CONFIG_PHY_NS2_PCIE=m
-CONFIG_PHY_NS2_USB_DRD=y
-CONFIG_PHY_BRCM_SATA=y
-CONFIG_PHY_BRCM_USB=m
-CONFIG_PHY_BCM_SR_PCIE=y
-# end of PHY drivers for Broadcom platforms
-
-# CONFIG_PHY_CADENCE_TORRENT is not set
-# CONFIG_PHY_CADENCE_DPHY is not set
-CONFIG_PHY_CADENCE_DPHY_RX=m
-# CONFIG_PHY_CADENCE_SIERRA is not set
-# CONFIG_PHY_CADENCE_SALVO is not set
-CONFIG_PHY_FSL_IMX8MQ_USB=m
-# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
-CONFIG_PHY_HI6220_USB=y
-# CONFIG_PHY_HI3660_USB is not set
-CONFIG_PHY_HI3670_USB=m
-CONFIG_PHY_HI3670_PCIE=m
-# CONFIG_PHY_HISTB_COMBPHY is not set
-# CONFIG_PHY_HISI_INNO_USB2 is not set
-# CONFIG_PHY_BERLIN_SATA is not set
-# CONFIG_PHY_BERLIN_USB is not set
-CONFIG_PHY_MVEBU_A3700_COMPHY=y
-CONFIG_PHY_MVEBU_A3700_UTMI=y
-# CONFIG_PHY_MVEBU_A38X_COMPHY is not set
-CONFIG_PHY_MVEBU_CP110_COMPHY=y
-CONFIG_PHY_MVEBU_CP110_UTMI=m
-# CONFIG_PHY_PXA_28NM_HSIC is not set
-# CONFIG_PHY_PXA_28NM_USB2 is not set
-# CONFIG_PHY_MTK_TPHY is not set
-CONFIG_PHY_MTK_UFS=m
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PHY_MTK_HDMI=m
-CONFIG_PHY_MTK_MIPI_DSI=m
-CONFIG_PHY_SPARX5_SERDES=m
-CONFIG_PHY_CPCAP_USB=m
-# CONFIG_PHY_MAPPHONE_MDM6600 is not set
-# CONFIG_PHY_OCELOT_SERDES is not set
-CONFIG_PHY_QCOM_APQ8064_SATA=m
-# CONFIG_PHY_QCOM_IPQ4019_USB is not set
-CONFIG_PHY_QCOM_IPQ806X_SATA=m
-# CONFIG_PHY_QCOM_PCIE2 is not set
-CONFIG_PHY_QCOM_QMP=m
-CONFIG_PHY_QCOM_QUSB2=m
-CONFIG_PHY_QCOM_USB_HS=y
-# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
-CONFIG_PHY_QCOM_USB_HSIC=m
-# CONFIG_PHY_QCOM_USB_HS_28NM is not set
-# CONFIG_PHY_QCOM_USB_SS is not set
-# CONFIG_PHY_QCOM_IPQ806X_USB is not set
-# CONFIG_PHY_RCAR_GEN2 is not set
-# CONFIG_PHY_RCAR_GEN3_PCIE is not set
-CONFIG_PHY_RCAR_GEN3_USB2=y
-CONFIG_PHY_RCAR_GEN3_USB3=m
-CONFIG_PHY_ROCKCHIP_DP=y
-CONFIG_PHY_ROCKCHIP_DPHY_RX0=m
-CONFIG_PHY_ROCKCHIP_EMMC=y
-CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
-CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m
-CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m
-CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
-CONFIG_PHY_ROCKCHIP_PCIE=m
-CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m
-CONFIG_PHY_ROCKCHIP_TYPEC=m
-CONFIG_PHY_ROCKCHIP_USB=y
-CONFIG_PHY_EXYNOS_DP_VIDEO=y
-CONFIG_PHY_EXYNOS_MIPI_VIDEO=y
-# CONFIG_PHY_EXYNOS_PCIE is not set
-CONFIG_PHY_SAMSUNG_UFS=m
-CONFIG_PHY_SAMSUNG_USB2=m
-CONFIG_PHY_EXYNOS5_USBDRD=m
-# CONFIG_PHY_UNIPHIER_USB2 is not set
-# CONFIG_PHY_UNIPHIER_USB3 is not set
-# CONFIG_PHY_UNIPHIER_PCIE is not set
-CONFIG_PHY_UNIPHIER_AHCI=m
-CONFIG_PHY_TEGRA_XUSB=y
-# CONFIG_PHY_TEGRA194_P2U is not set
-# CONFIG_PHY_AM654_SERDES is not set
-# CONFIG_PHY_J721E_WIZ is not set
-# CONFIG_OMAP_USB2 is not set
-# CONFIG_PHY_TUSB1210 is not set
-# CONFIG_PHY_INTEL_KEEMBAY_EMMC is not set
-CONFIG_PHY_INTEL_KEEMBAY_USB=m
-CONFIG_PHY_XILINX_ZYNQMP=m
-# end of PHY Subsystem
-
-CONFIG_POWERCAP=y
-# CONFIG_IDLE_INJECT is not set
-CONFIG_DTPM=y
-# CONFIG_MCB is not set
-
-#
-# Performance monitor support
-#
-CONFIG_ARM_CCI_PMU=m
-# CONFIG_ARM_CCI400_PMU is not set
-# CONFIG_ARM_CCI5xx_PMU is not set
-# CONFIG_ARM_CCN is not set
-CONFIG_ARM_CMN=m
-CONFIG_ARM_PMU=y
-CONFIG_ARM_PMU_ACPI=y
-# CONFIG_ARM_SMMU_V3_PMU is not set
-# CONFIG_ARM_DSU_PMU is not set
-CONFIG_FSL_IMX8_DDR_PMU=m
-# CONFIG_QCOM_L2_PMU is not set
-# CONFIG_QCOM_L3_PMU is not set
-CONFIG_THUNDERX2_PMU=m
-# CONFIG_XGENE_PMU is not set
-# CONFIG_ARM_SPE_PMU is not set
-CONFIG_ARM_DMC620_PMU=m
-CONFIG_MARVELL_CN10K_TAD_PMU=m
-CONFIG_APPLE_M1_CPU_PMU=y
-CONFIG_ALIBABA_UNCORE_DRW_PMU=m
-CONFIG_HISI_PMU=m
-CONFIG_HISI_PCIE_PMU=m
-CONFIG_HNS3_PMU=m
-CONFIG_MARVELL_CN10K_DDR_PMU=m
-# end of Performance monitor support
-
-CONFIG_RAS=y
-CONFIG_USB4=m
-# CONFIG_USB4_DEBUGFS_WRITE is not set
-
-#
-# Android
-#
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=m
-CONFIG_ANDROID_BINDERFS=y
-CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
-# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
-# end of Android
-
-CONFIG_LIBNVDIMM=y
-CONFIG_BLK_DEV_PMEM=m
-CONFIG_ND_BLK=m
-CONFIG_ND_CLAIM=y
-CONFIG_ND_BTT=m
-CONFIG_BTT=y
-CONFIG_ND_PFN=m
-CONFIG_NVDIMM_PFN=y
-CONFIG_NVDIMM_DAX=y
-CONFIG_OF_PMEM=y
-CONFIG_DAX_DRIVER=y
-CONFIG_DAX=y
-# CONFIG_DEV_DAX is not set
-# CONFIG_DEV_DAX_HMEM is not set
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_IMX_IIM=m
-CONFIG_NVMEM_IMX_OCOTP=m
-CONFIG_NVMEM_IMX_OCOTP_SCU=m
-CONFIG_NVMEM_LAN9662_OTPC=m
-CONFIG_NVMEM_MESON_MX_EFUSE=m
-CONFIG_NVMEM_MICROCHIP_OTPC=m
-CONFIG_NVMEM_MTK_EFUSE=m
-CONFIG_NVMEM_QCOM_QFPROM=m
-CONFIG_NVMEM_RAVE_SP_EEPROM=m
-CONFIG_NVMEM_ROCKCHIP_EFUSE=m
-CONFIG_NVMEM_ROCKCHIP_OTP=m
-CONFIG_NVMEM_SC27XX_EFUSE=m
-CONFIG_MTK_EFUSE=m
-CONFIG_QCOM_QFPROM=y
-CONFIG_NVMEM_SPMI_SDAM=m
-CONFIG_ROCKCHIP_EFUSE=m
-CONFIG_ROCKCHIP_OTP=m
-CONFIG_NVMEM_BCM_OCOTP=y
-CONFIG_NVMEM_SUNXI_SID=m
-CONFIG_NVMEM_U_BOOT_ENV=m
-CONFIG_NVMEM_UNIPHIER_EFUSE=m
-CONFIG_UNIPHIER_EFUSE=y
-CONFIG_MESON_EFUSE=m
-CONFIG_MESON_MX_EFUSE=m
-CONFIG_NVMEM_SNVS_LPGPR=m
-# CONFIG_NVMEM_ZYNQMP is not set
-CONFIG_SPRD_EFUSE=m
-CONFIG_NVMEM_RMEM=m
-CONFIG_NVMEM_LAYERSCAPE_SFP=m
-CONFIG_NVMEM_MESON_EFUSE=m
-CONFIG_NVMEM_SPRD_EFUSE=m
-CONFIG_NVMEM_APPLE_EFUSES=m
-
-#
-# HW tracing support
-#
-CONFIG_STM=m
-CONFIG_STM_PROTO_BASIC=m
-CONFIG_STM_PROTO_SYS_T=m
-CONFIG_STM_DUMMY=m
-CONFIG_STM_SOURCE_CONSOLE=m
-CONFIG_STM_SOURCE_HEARTBEAT=m
-CONFIG_INTEL_TH=m
-CONFIG_INTEL_TH_PCI=m
-# CONFIG_INTEL_TH_ACPI is not set
-CONFIG_INTEL_TH_GTH=m
-CONFIG_INTEL_TH_STH=m
-CONFIG_INTEL_TH_MSU=m
-CONFIG_INTEL_TH_PTI=m
-CONFIG_HISI_PTT=m
-# end of HW tracing support
-
-CONFIG_FPGA=m
-CONFIG_FPGA_MGR_SOCFPGA=m
-CONFIG_FPGA_MGR_SOCFPGA_A10=m
-# CONFIG_ALTERA_PR_IP_CORE is not set
-# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set
-# CONFIG_FPGA_MGR_ALTERA_CVP is not set
-# CONFIG_FPGA_MGR_XILINX_SPI is not set
-# CONFIG_FPGA_MGR_ICE40_SPI is not set
-# CONFIG_FPGA_MGR_MACHXO2_SPI is not set
-# CONFIG_FPGA_BRIDGE is not set
-# CONFIG_FPGA_DFL is not set
-# CONFIG_FPGA_MGR_ZYNQMP_FPGA is not set
-CONFIG_FPGA_MGR_VERSAL_FPGA=m
-CONFIG_FPGA_M10_BMC_SEC_UPDATE=m
-CONFIG_FPGA_MGR_MICROCHIP_SPI=m
-# CONFIG_FSI is not set
-CONFIG_TEE=y
-
-#
-# TEE drivers
-#
-CONFIG_OPTEE=y
-CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
-# end of TEE drivers
-
-CONFIG_MULTIPLEXER=m
-
-#
-# Multiplexer drivers
-#
-# CONFIG_MUX_ADG792A is not set
-# CONFIG_MUX_ADGS1408 is not set
-# CONFIG_MUX_GPIO is not set
-# CONFIG_MUX_MMIO is not set
-# end of Multiplexer drivers
-
-CONFIG_PM_OPP=y
-# CONFIG_SIOX is not set
-# CONFIG_SLIMBUS is not set
-CONFIG_INTERCONNECT=y
-CONFIG_INTERCONNECT_IMX=m
-CONFIG_INTERCONNECT_IMX8MM=m
-CONFIG_INTERCONNECT_IMX8MN=m
-CONFIG_INTERCONNECT_IMX8MQ=m
-CONFIG_INTERCONNECT_IMX8MP=m
-CONFIG_INTERCONNECT_QCOM_SM6350=m
-CONFIG_INTERCONNECT_QCOM=y
-CONFIG_INTERCONNECT_QCOM_MSM8916=m
-CONFIG_INTERCONNECT_QCOM_MSM8939=m
-CONFIG_INTERCONNECT_QCOM_MSM8974=m
-CONFIG_INTERCONNECT_QCOM_MSM8996=m
-CONFIG_INTERCONNECT_QCOM_OSM_L3=m
-CONFIG_INTERCONNECT_QCOM_QCM2290=m
-CONFIG_INTERCONNECT_QCOM_QCS404=m
-CONFIG_INTERCONNECT_QCOM_RPMH_POSSIBLE=m
-# CONFIG_INTERCONNECT_QCOM_SC7180 is not set
-# CONFIG_INTERCONNECT_QCOM_SC7280 is not set
-# CONFIG_INTERCONNECT_QCOM_SC8180X is not set
-CONFIG_INTERCONNECT_QCOM_SC8280XP=m
-CONFIG_INTERCONNECT_QCOM_SDM660=m
-# CONFIG_INTERCONNECT_QCOM_SDM845 is not set
-# CONFIG_INTERCONNECT_QCOM_SDX55 is not set
-CONFIG_INTERCONNECT_QCOM_SDX65=m
-# CONFIG_INTERCONNECT_QCOM_SM8150 is not set
-# CONFIG_INTERCONNECT_QCOM_SM8250 is not set
-# CONFIG_INTERCONNECT_QCOM_SM8350 is not set
-CONFIG_INTERCONNECT_QCOM_SM8450=m
-CONFIG_INTERCONNECT_QCOM_SMD_RPM=m
-CONFIG_INTERCONNECT_SAMSUNG=y
-CONFIG_INTERCONNECT_EXYNOS=m
-# CONFIG_COUNTER is not set
-CONFIG_MOST=m
-CONFIG_MOST_USB_HDM=m
-CONFIG_MOST_CDEV=m
-CONFIG_MOST_SND=m
-# end of Device Drivers
-
-#
-# File systems
-#
-CONFIG_DCACHE_WORD_ACCESS=y
-# CONFIG_VALIDATE_FS_PARSER is not set
-CONFIG_FS_IOMAP=y
-# CONFIG_EXT2_FS is not set
-# CONFIG_EXT3_FS is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_EXT4_USE_FOR_EXT2=y
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD2=y
-# CONFIG_JBD2_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-# CONFIG_REISERFS_FS_XATTR is not set
-# CONFIG_REISERFS_FS_POSIX_ACL is not set
-# CONFIG_REISERFS_FS_SECURITY is not set
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-# CONFIG_JFS_SECURITY is not set
-# CONFIG_JFS_DEBUG is not set
-CONFIG_JFS_STATISTICS=y
-# CONFIG_XFS_FS is not set
-CONFIG_GFS2_FS=m
-# CONFIG_GFS2_FS_LOCKING_DLM is not set
-CONFIG_OCFS2_FS=m
-CONFIG_OCFS2_FS_O2CB=m
-CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
-CONFIG_OCFS2_DEBUG_MASKLOG=y
-# CONFIG_OCFS2_DEBUG_FS is not set
-CONFIG_BTRFS_FS=m
-CONFIG_BTRFS_FS_POSIX_ACL=y
-# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
-# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
-# CONFIG_BTRFS_DEBUG is not set
-# CONFIG_BTRFS_ASSERT is not set
-# CONFIG_BTRFS_FS_REF_VERIFY is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_F2FS_FS=y
-CONFIG_F2FS_STAT_FS=y
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_FS_POSIX_ACL=y
-CONFIG_F2FS_FS_SECURITY=y
-# CONFIG_F2FS_CHECK_FS is not set
-# CONFIG_F2FS_FAULT_INJECTION is not set
-CONFIG_F2FS_FS_COMPRESSION=y
-CONFIG_F2FS_FS_LZO=y
-CONFIG_F2FS_FS_LZORLE=y
-CONFIG_F2FS_FS_LZ4=y
-CONFIG_F2FS_FS_LZ4HC=y
-CONFIG_F2FS_FS_ZSTD=y
-# CONFIG_F2FS_IOSTAT is not set
-# CONFIG_F2FS_UNFAIR_RWSEM is not set
-CONFIG_FS_DAX=y
-CONFIG_FS_DAX_PMD=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_EXPORTFS=y
-CONFIG_EXPORTFS_BLOCK_OPS=y
-CONFIG_FILE_LOCKING=y
-# CONFIG_FS_ENCRYPTION is not set
-# CONFIG_FS_VERITY is not set
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY_USER=y
-CONFIG_FANOTIFY=y
-CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-CONFIG_PRINT_QUOTA_WARNING=y
-# CONFIG_QUOTA_DEBUG is not set
-CONFIG_QUOTA_TREE=y
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=y
-CONFIG_QUOTACTL=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_AUTOFS_FS=y
-CONFIG_FUSE_FS=m
-CONFIG_CUSE=m
-CONFIG_VIRTIO_FS=m
-CONFIG_FUSE_DAX=y
-CONFIG_OVERLAY_FS=m
-# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
-CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
-# CONFIG_OVERLAY_FS_INDEX is not set
-# CONFIG_OVERLAY_FS_XINO_AUTO is not set
-# CONFIG_OVERLAY_FS_METACOPY is not set
-
-#
-# Caches
-#
-CONFIG_NETFS_SUPPORT=m
-CONFIG_NETFS_STATS=y
-CONFIG_FSCACHE=m
-# CONFIG_FSCACHE_STATS is not set
-# CONFIG_FSCACHE_DEBUG is not set
-# CONFIG_CACHEFILES is not set
-# end of Caches
-
-#
-# CD-ROM/DVD Filesystems
-#
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-# end of CD-ROM/DVD Filesystems
-
-#
-# DOS/FAT/EXFAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-CONFIG_FAT_DEFAULT_UTF8=y
-CONFIG_EXFAT_FS=m
-CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-# CONFIG_NTFS_RW is not set
-CONFIG_NTFS3_FS=m
-# CONFIG_NTFS3_64BIT_CLUSTER is not set
-CONFIG_NTFS3_LZX_XPRESS=y
-CONFIG_NTFS3_FS_POSIX_ACL=y
-# end of DOS/FAT/EXFAT/NT Filesystems
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-# CONFIG_PROC_KCORE is not set
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_CHILDREN=y
-CONFIG_KERNFS=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TMPFS_XATTR=y
-CONFIG_TMPFS_INODE64=y
-CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_EFIVAR_FS=m
-# end of Pseudo filesystems
-
-CONFIG_MISC_FILESYSTEMS=y
-CONFIG_ORANGEFS_FS=m
-CONFIG_ADFS_FS=m
-# CONFIG_ADFS_FS_RW is not set
-CONFIG_AFFS_FS=m
-CONFIG_ECRYPT_FS=m
-# CONFIG_ECRYPT_FS_MESSAGING is not set
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-# CONFIG_BEFS_DEBUG is not set
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RTIME=y
-CONFIG_JFFS2_RUBIN=y
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-CONFIG_UBIFS_FS=y
-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UBIFS_FS_ZSTD=y
-# CONFIG_UBIFS_ATIME_SUPPORT is not set
-CONFIG_UBIFS_FS_XATTR=y
-CONFIG_UBIFS_FS_SECURITY=y
-CONFIG_UBIFS_FS_AUTHENTICATION=y
-CONFIG_CRAMFS=y
-CONFIG_CRAMFS_BLOCKDEV=y
-# CONFIG_CRAMFS_MTD is not set
-CONFIG_SQUASHFS=m
-# CONFIG_SQUASHFS_FILE_CACHE is not set
-CONFIG_SQUASHFS_FILE_DIRECT=y
-# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
-CONFIG_SQUASHFS_DECOMP_MULTI=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_XATTR=y
-CONFIG_SQUASHFS_ZLIB=y
-CONFIG_SQUASHFS_LZ4=y
-CONFIG_SQUASHFS_LZO=y
-CONFIG_SQUASHFS_XZ=y
-CONFIG_SQUASHFS_ZSTD=y
-# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
-# CONFIG_SQUASHFS_EMBEDDED is not set
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_OMFS_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_QNX6FS_FS=m
-# CONFIG_QNX6FS_DEBUG is not set
-CONFIG_ROMFS_FS=m
-CONFIG_ROMFS_BACKED_BY_BLOCK=y
-# CONFIG_ROMFS_BACKED_BY_MTD is not set
-# CONFIG_ROMFS_BACKED_BY_BOTH is not set
-CONFIG_ROMFS_ON_BLOCK=y
-CONFIG_PSTORE=m
-CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-# CONFIG_PSTORE_LZO_COMPRESS is not set
-# CONFIG_PSTORE_LZ4_COMPRESS is not set
-# CONFIG_PSTORE_LZ4HC_COMPRESS is not set
-# CONFIG_PSTORE_842_COMPRESS is not set
-# CONFIG_PSTORE_ZSTD_COMPRESS is not set
-CONFIG_PSTORE_COMPRESS=y
-CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
-# CONFIG_PSTORE_CONSOLE is not set
-# CONFIG_PSTORE_PMSG is not set
-# CONFIG_PSTORE_RAM is not set
-# CONFIG_PSTORE_BLK is not set
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-# CONFIG_UFS_FS_WRITE is not set
-# CONFIG_UFS_DEBUG is not set
-# CONFIG_EROFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V2=m
-CONFIG_NFS_V3=m
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=m
-CONFIG_NFS_SWAP=y
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_V4_2=y
-CONFIG_PNFS_FILE_LAYOUT=m
-CONFIG_PNFS_BLOCK=m
-CONFIG_PNFS_FLEXFILE_LAYOUT=m
-CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
-CONFIG_NFS_V4_1_MIGRATION=y
-CONFIG_NFS_V4_SECURITY_LABEL=y
-CONFIG_NFS_FSCACHE=y
-# CONFIG_NFS_USE_LEGACY_DNS is not set
-CONFIG_NFS_USE_KERNEL_DNS=y
-CONFIG_NFS_DISABLE_UDP_SUPPORT=y
-CONFIG_NFS_V4_2_READ_PLUS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V2_ACL=y
-CONFIG_NFSD_V3=y
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_PNFS=y
-CONFIG_NFSD_BLOCKLAYOUT=y
-CONFIG_NFSD_SCSILAYOUT=y
-CONFIG_NFSD_FLEXFILELAYOUT=y
-CONFIG_NFSD_V4_2_INTER_SSC=y
-# CONFIG_NFSD_V4_SECURITY_LABEL is not set
-CONFIG_GRACE_PERIOD=m
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_ACL_SUPPORT=m
-CONFIG_NFS_COMMON=y
-CONFIG_NFS_V4_2_SSC_HELPER=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_SUNRPC_BACKCHANNEL=y
-CONFIG_SUNRPC_SWAP=y
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
-# CONFIG_SUNRPC_DEBUG is not set
-CONFIG_SUNRPC_XPRT_RDMA=m
-CONFIG_CEPH_FS=m
-CONFIG_CEPH_FSCACHE=y
-CONFIG_CEPH_FS_POSIX_ACL=y
-CONFIG_CEPH_FS_SECURITY_LABEL=y
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS2=y
-CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
-CONFIG_CIFS_UPCALL=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-# CONFIG_CIFS_DEBUG is not set
-CONFIG_CIFS_DFS_UPCALL=y
-CONFIG_CIFS_SWN_UPCALL=y
-CONFIG_CIFS_SMB_DIRECT=y
-CONFIG_CIFS_FSCACHE=y
-CONFIG_SMB_SERVER=m
-CONFIG_SMB_SERVER_SMBDIRECT=y
-CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
-CONFIG_SMB_SERVER_KERBEROS5=y
-CONFIG_SMBFS_COMMON=m
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-# CONFIG_AFS_DEBUG is not set
-# CONFIG_AFS_FSCACHE is not set
-# CONFIG_AFS_DEBUG_CURSOR is not set
-CONFIG_9P_FS=m
-# CONFIG_9P_FSCACHE is not set
-# CONFIG_9P_FS_POSIX_ACL is not set
-# CONFIG_9P_FS_SECURITY is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_MAC_ROMAN=m
-CONFIG_NLS_MAC_CELTIC=m
-CONFIG_NLS_MAC_CENTEURO=m
-CONFIG_NLS_MAC_CROATIAN=m
-CONFIG_NLS_MAC_CYRILLIC=m
-CONFIG_NLS_MAC_GAELIC=m
-CONFIG_NLS_MAC_GREEK=m
-CONFIG_NLS_MAC_ICELAND=m
-CONFIG_NLS_MAC_INUIT=m
-CONFIG_NLS_MAC_ROMANIAN=m
-CONFIG_NLS_MAC_TURKISH=m
-CONFIG_NLS_UTF8=m
-CONFIG_DLM=m
-# CONFIG_DLM_DEPRECATED_API is not set
-# CONFIG_DLM_DEBUG is not set
-# CONFIG_UNICODE is not set
-CONFIG_IO_WQ=y
-# end of File systems
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-# CONFIG_KEYS_REQUEST_CACHE is not set
-# CONFIG_PERSISTENT_KEYRINGS is not set
-CONFIG_TRUSTED_KEYS=m
-CONFIG_ENCRYPTED_KEYS=m
-CONFIG_USER_DECRYPTED_DATA=y
-CONFIG_KEY_DH_OPERATIONS=y
-# CONFIG_KEY_NOTIFICATIONS is not set
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-CONFIG_SECURITY=y
-CONFIG_SECURITYFS=y
-CONFIG_SECURITY_NETWORK=y
-CONFIG_SECURITY_INFINIBAND=y
-CONFIG_SECURITY_NETWORK_XFRM=y
-# CONFIG_SECURITY_PATH is not set
-CONFIG_LSM_MMAP_MIN_ADDR=32768
-CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
-CONFIG_HARDENED_USERCOPY=y
-# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
-CONFIG_FORTIFY_SOURCE=y
-# CONFIG_STATIC_USERMODEHELPER is not set
-# CONFIG_SECURITY_SELINUX is not set
-# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set
-# CONFIG_SECURITY_SELINUX_DISABLE is not set
-# CONFIG_SECURITY_SELINUX_DEVELOP is not set
-# CONFIG_SECURITY_SELINUX_AVC_STATS is not set
-CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
-CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
-CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
-# CONFIG_SECURITY_SMACK is not set
-# CONFIG_SECURITY_TOMOYO is not set
-# CONFIG_SECURITY_APPARMOR is not set
-CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y
-CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y
-CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y
-# CONFIG_SECURITY_LOADPIN is not set
-# CONFIG_SECURITY_YAMA is not set
-# CONFIG_SECURITY_SAFESETID is not set
-# CONFIG_SECURITY_LOCKDOWN_LSM is not set
-# CONFIG_SECURITY_LANDLOCK is not set
-CONFIG_INTEGRITY=y
-# CONFIG_INTEGRITY_SIGNATURE is not set
-CONFIG_INTEGRITY_AUDIT=y
-# CONFIG_IMA is not set
-# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
-# CONFIG_EVM is not set
-CONFIG_DEFAULT_SECURITY_SELINUX=y
-# CONFIG_DEFAULT_SECURITY_DAC is not set
-CONFIG_LSM="yama,loadpin,safesetid,integrity,bpf"
-
-#
-# Kernel hardening options
-#
-
-#
-# Memory initialization
-#
-CONFIG_INIT_STACK_NONE=y
-# CONFIG_INIT_STACK_ALL_PATTERN is not set
-# CONFIG_INIT_STACK_ALL_ZERO is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
-# CONFIG_GCC_PLUGIN_STACKLEAK is not set
-# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
-# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
-CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
-# CONFIG_ZERO_CALL_USED_REGS is not set
-# end of Memory initialization
-# end of Kernel hardening options
-# end of Security options
-
-CONFIG_XOR_BLOCKS=m
-CONFIG_ASYNC_CORE=m
-CONFIG_ASYNC_MEMCPY=m
-CONFIG_ASYNC_XOR=m
-CONFIG_ASYNC_PQ=m
-CONFIG_ASYNC_RAID6_RECOV=m
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_SKCIPHER=y
-CONFIG_CRYPTO_SKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_AKCIPHER2=y
-CONFIG_CRYPTO_AKCIPHER=y
-CONFIG_CRYPTO_KPP2=y
-CONFIG_CRYPTO_KPP=m
-CONFIG_CRYPTO_ACOMP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_USER=m
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-CONFIG_CRYPTO_GF128MUL=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_NULL2=y
-# CONFIG_CRYPTO_PCRYPT is not set
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_ENGINE=y
-
-#
-# Public-key cryptography
-#
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_DH=m
-CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
-CONFIG_CRYPTO_ECC=m
-CONFIG_CRYPTO_ECDH=m
-CONFIG_CRYPTO_ECDSA=m
-CONFIG_CRYPTO_ECRDSA=m
-CONFIG_CRYPTO_SM2=m
-CONFIG_CRYPTO_CURVE25519=m
-
-#
-# Authenticated Encryption with Associated Data
-#
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_GCM=m
-CONFIG_CRYPTO_CHACHA20POLY1305=m
-CONFIG_CRYPTO_AEGIS128=m
-CONFIG_CRYPTO_AEGIS128_SIMD=y
-CONFIG_CRYPTO_SEQIV=m
-CONFIG_CRYPTO_ECHAINIV=y
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CFB=m
-CONFIG_CRYPTO_CTR=m
-CONFIG_CRYPTO_CTS=m
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_OFB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_KEYWRAP=m
-CONFIG_CRYPTO_NHPOLY1305=y
-CONFIG_CRYPTO_ADIANTUM=m
-CONFIG_CRYPTO_HCTR2=m
-CONFIG_CRYPTO_ARIA=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
-CONFIG_CRYPTO_DEV_QAT_C3XXX=m
-CONFIG_CRYPTO_DEV_QAT_C62X=m
-CONFIG_CRYPTO_DEV_QAT_4XXX=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
-CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
-CONFIG_CRYPTO_DEV_QAT_C62XVF=m
-CONFIG_CRYPTO_ESSIV=m
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_CMAC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_XXHASH=m
-CONFIG_CRYPTO_BLAKE2B=m
-CONFIG_CRYPTO_BLAKE2S=m
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_GHASH=m
-CONFIG_CRYPTO_POLY1305=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SHA3=m
-CONFIG_CRYPTO_SM3=m
-CONFIG_CRYPTO_STREEBOG=m
-CONFIG_CRYPTO_WP512=m
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_AES_TI=m
-CONFIG_CRYPTO_ANUBIS=m
-# CONFIG_CRYPTO_ARC4 is not set
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_BLOWFISH_COMMON=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST_COMMON=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_CHACHA20=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_SM4=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_842=y
-CONFIG_CRYPTO_LZ4=m
-CONFIG_CRYPTO_LZ4HC=m
-CONFIG_CRYPTO_ZSTD=y
-
-#
-# Random Number Generation
-#
-CONFIG_CRYPTO_ANSI_CPRNG=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-# CONFIG_CRYPTO_DRBG_HASH is not set
-# CONFIG_CRYPTO_DRBG_CTR is not set
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_USER_API=m
-CONFIG_CRYPTO_USER_API_HASH=y
-CONFIG_CRYPTO_USER_API_SKCIPHER=m
-CONFIG_CRYPTO_USER_API_RNG=m
-# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
-# CONFIG_CRYPTO_USER_API_AEAD is not set
-CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
-# CONFIG_CRYPTO_STATS is not set
-CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
-CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_SM4=m
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_DEV_ALLWINNER=y
-CONFIG_CRYPTO_DEV_SUN4I_SS=m
-CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
-CONFIG_CRYPTO_DEV_SUN8I_CE=m
-CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
-CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
-CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
-CONFIG_CRYPTO_DEV_SUN8I_SS=m
-CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y
-CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y
-# CONFIG_CRYPTO_DEV_FSL_CAAM is not set
-CONFIG_CRYPTO_DEV_SAHARA=m
-# CONFIG_CRYPTO_DEV_EXYNOS_RNG is not set
-# CONFIG_CRYPTO_DEV_S5P is not set
-CONFIG_CRYPTO_DEV_ATMEL_I2C=m
-CONFIG_CRYPTO_DEV_ATMEL_ECC=m
-CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
-# CONFIG_CRYPTO_DEV_CCP is not set
-CONFIG_CRYPTO_DEV_MXS_DCP=m
-CONFIG_CRYPTO_DEV_CPT=m
-CONFIG_CAVIUM_CPT=m
-CONFIG_CRYPTO_DEV_NITROX=m
-CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m
-CONFIG_CRYPTO_DEV_MARVELL=m
-CONFIG_CRYPTO_DEV_MARVELL_CESA=m
-# CONFIG_CRYPTO_DEV_OCTEONTX_CPT is not set
-# CONFIG_CRYPTO_DEV_OCTEONTX2_CPT is not set
-# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set
-CONFIG_CRYPTO_DEV_QCE=m
-CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
-CONFIG_CRYPTO_DEV_QCE_SHA=y
-CONFIG_CRYPTO_DEV_QCE_AEAD=y
-CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
-CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
-CONFIG_CRYPTO_DEV_QCOM_RNG=m
-CONFIG_CRYPTO_DEV_ROCKCHIP=y
-# CONFIG_CRYPTO_DEV_ZYNQMP_AES is not set
-CONFIG_CRYPTO_DEV_ZYNQMP_SHA3=m
-CONFIG_CRYPTO_DEV_VIRTIO=m
-CONFIG_CRYPTO_DEV_BCM_SPU=m
-CONFIG_CRYPTO_DEV_SAFEXCEL=m
-CONFIG_CRYPTO_DEV_CCREE=m
-CONFIG_CRYPTO_DEV_HISI_SEC=m
-CONFIG_CRYPTO_DEV_HISI_SEC2=m
-CONFIG_CRYPTO_DEV_HISI_QM=m
-# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
-CONFIG_CRYPTO_DEV_HISI_HPRE=m
-CONFIG_CRYPTO_DEV_HISI_TRNG=m
-CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
-CONFIG_CRYPTO_DEV_ASPEED=m
-# CONFIG_CRYPTO_DEV_ASPEED_DEBUG is not set
-CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH=y
-CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO=y
-# CONFIG_CRYPTO_DEV_SA2UL is not set
-CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4=m
-CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_ECB=y
-CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_CTS=y
-CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC=m
-CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU=m
-CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224=y
-CONFIG_ASYMMETRIC_KEY_TYPE=y
-CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
-CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE=m
-CONFIG_X509_CERTIFICATE_PARSER=y
-CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
-CONFIG_TPM_KEY_PARSER=m
-CONFIG_PKCS7_MESSAGE_PARSER=y
-# CONFIG_PKCS7_TEST_KEY is not set
-CONFIG_SIGNED_PE_FILE_VERIFICATION=y
-
-#
-# Certificates for signature checking
-#
-CONFIG_MODULE_SIG_KEY="certs/signing_key.pem"
-CONFIG_MODULE_SIG_KEY_TYPE_RSA=y
-# CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set
-CONFIG_SYSTEM_TRUSTED_KEYRING=y
-CONFIG_SYSTEM_TRUSTED_KEYS=""
-# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
-# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
-# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
-# end of Certificates for signature checking
-
-CONFIG_BINARY_PRINTF=y
-
-#
-# Library routines
-#
-CONFIG_RAID6_PQ=m
-# CONFIG_RAID6_PQ_BENCHMARK is not set
-CONFIG_LINEAR_RANGES=y
-CONFIG_PACKING=y
-CONFIG_BITREVERSE=y
-CONFIG_HAVE_ARCH_BITREVERSE=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_CORDIC=m
-# CONFIG_PRIME_NUMBERS is not set
-CONFIG_RATIONAL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_STMP_DEVICE=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
-CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
-# CONFIG_INDIRECT_PIO is not set
-# CONFIG_TRACE_MMIO_ACCESS is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC64_ROCKSOFT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC32=y
-# CONFIG_CRC32_SELFTEST is not set
-CONFIG_CRC32_SLICEBY8=y
-# CONFIG_CRC32_SLICEBY4 is not set
-# CONFIG_CRC32_SARWATE is not set
-# CONFIG_CRC32_BIT is not set
-CONFIG_CRC64=m
-CONFIG_CRC4=m
-CONFIG_CRC7=y
-CONFIG_LIBCRC32C=m
-CONFIG_CRC8=y
-CONFIG_XXHASH=y
-# CONFIG_RANDOM32_SELFTEST is not set
-CONFIG_842_COMPRESS=y
-CONFIG_842_DECOMPRESS=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_LZ4_COMPRESS=y
-CONFIG_LZ4HC_COMPRESS=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
-CONFIG_XZ_DEC=y
-CONFIG_XZ_DEC_X86=y
-# CONFIG_XZ_DEC_POWERPC is not set
-# CONFIG_XZ_DEC_IA64 is not set
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-# CONFIG_XZ_DEC_SPARC is not set
-CONFIG_XZ_DEC_MICROLZMA=y
-CONFIG_XZ_DEC_BCJ=y
-# CONFIG_XZ_DEC_TEST is not set
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_LZ4=y
-CONFIG_DECOMPRESS_ZSTD=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_REED_SOLOMON=m
-CONFIG_REED_SOLOMON_DEC16=y
-CONFIG_BCH=y
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_BTREE=y
-CONFIG_INTERVAL_TREE=y
-CONFIG_XARRAY_MULTI=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAS_DMA=y
-CONFIG_DMA_OPS=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_DMA_DECLARE_COHERENT=y
-CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
-CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
-CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
-CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
-CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
-CONFIG_SWIOTLB=y
-CONFIG_DMA_RESTRICTED_POOL=y
-CONFIG_DMA_NONCOHERENT_MMAP=y
-CONFIG_DMA_COHERENT_POOL=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_PERNUMA_CMA=y
-
-#
-# Default contiguous memory area size:
-#
-CONFIG_CMA_SIZE_MBYTES=256
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_ALIGNMENT=8
-# CONFIG_DMA_API_DEBUG is not set
-CONFIG_SGL_ALLOC=y
-CONFIG_CHECK_SIGNATURE=y
-CONFIG_CPU_RMAP=y
-CONFIG_DQL=y
-CONFIG_GLOB=y
-# CONFIG_GLOB_SELFTEST is not set
-CONFIG_NLATTR=y
-CONFIG_LRU_CACHE=m
-CONFIG_CLZ_TAB=y
-CONFIG_IRQ_POLL=y
-CONFIG_MPILIB=y
-CONFIG_DIMLIB=y
-CONFIG_LIBFDT=y
-CONFIG_OID_REGISTRY=y
-CONFIG_UCS2_STRING=y
-CONFIG_HAVE_GENERIC_VDSO=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_VDSO_TIME_NS=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_6x10 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_TER16x32 is not set
-# CONFIG_FONT_6x8 is not set
-CONFIG_SG_SPLIT=y
-CONFIG_SG_POOL=y
-CONFIG_ARCH_HAS_PMEM_API=y
-CONFIG_MEMREGION=y
-CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_SBITMAP=y
-CONFIG_PARMAN=m
-CONFIG_OBJAGG=m
-# end of Library routines
-
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_ASN1_ENCODER=m
-
-#
-# Kernel hacking
-#
-
-#
-# printk and dmesg options
-#
-CONFIG_PRINTK_TIME=y
-# CONFIG_PRINTK_CALLER is not set
-CONFIG_STACKTRACE_BUILD_ID=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
-CONFIG_CONSOLE_LOGLEVEL_QUIET=4
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_DYNAMIC_DEBUG_CORE is not set
-CONFIG_SYMBOLIC_ERRNAME=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# end of printk and dmesg options
-
-#
-# Compile-time checks and compiler options
-#
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_INFO_REDUCED is not set
-# CONFIG_DEBUG_INFO_COMPRESSED is not set
-# CONFIG_DEBUG_INFO_SPLIT is not set
-# CONFIG_DEBUG_INFO_NONE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-# CONFIG_DEBUG_INFO_DWARF4 is not set
-# CONFIG_DEBUG_INFO_DWARF5 is not set
-CONFIG_DEBUG_INFO_BTF=y
-CONFIG_MODULE_ALLOW_BTF_MISMATCH=y
-CONFIG_PAHOLE_HAS_SPLIT_BTF=y
-CONFIG_DEBUG_INFO_BTF_MODULES=y
-# CONFIG_GDB_SCRIPTS is not set
-CONFIG_FRAME_WARN=1024
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_READABLE_ASM is not set
-# CONFIG_HEADERS_INSTALL is not set
-# CONFIG_DEBUG_SECTION_MISMATCH is not set
-CONFIG_SECTION_MISMATCH_WARN_ONLY=y
-# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
-CONFIG_ARCH_WANT_FRAME_POINTERS=y
-CONFIG_FRAME_POINTER=y
-CONFIG_VMLINUX_MAP=y
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# end of Compile-time checks and compiler options
-
-#
-# Generic Kernel Debugging Instruments
-#
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
-CONFIG_MAGIC_SYSRQ_SERIAL=y
-CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
-# CONFIG_DEBUG_FS is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_KCSAN_COMPILER=y
-# end of Generic Kernel Debugging Instruments
-
-# CONFIG_DEBUG_KERNEL is not set
-# CONFIG_DEBUG_MISC is not set
-
-#
-# Memory Debugging
-#
-# CONFIG_PAGE_EXTENSION is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
-# CONFIG_PAGE_OWNER is not set
-# CONFIG_PAGE_TABLE_CHECK is not set
-# CONFIG_PAGE_POISONING is not set
-# CONFIG_DEBUG_RODATA_TEST is not set
-CONFIG_ARCH_HAS_DEBUG_WX=y
-CONFIG_DEBUG_WX=y
-CONFIG_GENERIC_PTDUMP=y
-CONFIG_PTDUMP_CORE=y
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SHRINKER_DEBUG is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_HAVE_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_SCHED_STACK_END_CHECK is not set
-# CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_VM_PGTABLE is not set
-# CONFIG_ARCH_HAS_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_PER_CPU_MAPS is not set
-CONFIG_HAVE_ARCH_KASAN=y
-CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
-CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
-CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
-CONFIG_CC_HAS_KASAN_GENERIC=y
-CONFIG_CC_HAS_KASAN_SW_TAGS=y
-CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
-# CONFIG_KASAN is not set
-CONFIG_HAVE_ARCH_KFENCE=y
-# CONFIG_KFENCE is not set
-# end of Memory Debugging
-
-# CONFIG_DEBUG_SHIRQ is not set
-
-#
-# Debug Oops, Lockups and Hangs
-#
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=0
-# CONFIG_SOFTLOCKUP_DETECTOR is not set
-# CONFIG_DETECT_HUNG_TASK is not set
-# CONFIG_WQ_WATCHDOG is not set
-# CONFIG_TEST_LOCKUP is not set
-# end of Debug Oops, Lockups and Hangs
-
-#
-# Scheduler Debugging
-#
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHED_INFO=y
-CONFIG_SCHEDSTATS=y
-# end of Scheduler Debugging
-
-# CONFIG_DEBUG_TIMEKEEPING is not set
-# CONFIG_DEBUG_PREEMPT is not set
-
-#
-# Lock Debugging (spinlocks, mutexes, etc...)
-#
-# CONFIG_LOCK_DEBUGGING_SUPPORT is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
-# CONFIG_DEBUG_RWSEMS is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_DEBUG_ATOMIC_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_LOCK_TORTURE_TEST is not set
-# CONFIG_WW_MUTEX_SELFTEST is not set
-# CONFIG_SCF_TORTURE_TEST is not set
-# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
-# end of Lock Debugging (spinlocks, mutexes, etc...)
-
-# CONFIG_DEBUG_IRQFLAGS is not set
-CONFIG_STACKTRACE=y
-# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
-# CONFIG_DEBUG_KOBJECT is not set
-
-#
-# Debug kernel data structures
-#
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_PLIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BUG_ON_DATA_CORRUPTION is not set
-# end of Debug kernel data structures
-
-# CONFIG_DEBUG_CREDENTIALS is not set
-
-#
-# RCU Debugging
-#
-CONFIG_TORTURE_TEST=m
-CONFIG_RCU_SCALE_TEST=m
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_REF_SCALE_TEST=m
-CONFIG_RCU_CPU_STALL_TIMEOUT=21
-# CONFIG_RCU_TRACE is not set
-# CONFIG_RCU_EQS_DEBUG is not set
-# end of RCU Debugging
-
-# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-CONFIG_LATENCYTOP=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-# CONFIG_SAMPLES is not set
-CONFIG_STRICT_DEVMEM=y
-CONFIG_IO_STRICT_DEVMEM=y
-
-#
-# arm64 Debugging
-#
-# CONFIG_PID_IN_CONTEXTIDR is not set
-# CONFIG_DEBUG_EFI is not set
-# CONFIG_ARM64_RELOC_TEST is not set
-# CONFIG_CORESIGHT is not set
-# end of arm64 Debugging
-
-#
-# Kernel Testing and Coverage
-#
-# CONFIG_KUNIT is not set
-# CONFIG_NOTIFIER_ERROR_INJECTION is not set
-CONFIG_FUNCTION_ERROR_INJECTION=y
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_ARCH_HAS_KCOV=y
-CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-# CONFIG_KCOV is not set
-CONFIG_RUNTIME_TESTING_MENU=y
-# CONFIG_TEST_MIN_HEAP is not set
-# CONFIG_TEST_DIV64 is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_TEST_REF_TRACKER is not set
-# CONFIG_RBTREE_TEST is not set
-# CONFIG_REED_SOLOMON_TEST is not set
-# CONFIG_INTERVAL_TREE_TEST is not set
-# CONFIG_PERCPU_TEST is not set
-# CONFIG_ATOMIC64_SELFTEST is not set
-# CONFIG_ASYNC_RAID6_TEST is not set
-# CONFIG_TEST_HEXDUMP is not set
-# CONFIG_STRING_SELFTEST is not set
-# CONFIG_TEST_STRING_HELPERS is not set
-# CONFIG_TEST_STRSCPY is not set
-# CONFIG_TEST_KSTRTOX is not set
-# CONFIG_TEST_PRINTF is not set
-# CONFIG_TEST_SCANF is not set
-# CONFIG_TEST_BITMAP is not set
-# CONFIG_TEST_UUID is not set
-CONFIG_TEST_XARRAY=m
-# CONFIG_TEST_MAPLE_TREE is not set
-# CONFIG_TEST_OVERFLOW is not set
-# CONFIG_TEST_RHASHTABLE is not set
-# CONFIG_TEST_SIPHASH is not set
-# CONFIG_TEST_HASH is not set
-# CONFIG_TEST_IDA is not set
-# CONFIG_TEST_PARMAN is not set
-# CONFIG_TEST_LKM is not set
-# CONFIG_TEST_BITOPS is not set
-# CONFIG_TEST_VMALLOC is not set
-# CONFIG_TEST_USER_COPY is not set
-# CONFIG_TEST_BPF is not set
-# CONFIG_TEST_BLACKHOLE_DEV is not set
-# CONFIG_FIND_BIT_BENCHMARK is not set
-# CONFIG_TEST_FIRMWARE is not set
-# CONFIG_TEST_SYSCTL is not set
-# CONFIG_TEST_UDELAY is not set
-# CONFIG_TEST_STATIC_KEYS is not set
-# CONFIG_TEST_KMOD is not set
-# CONFIG_TEST_MEMCAT_P is not set
-# CONFIG_TEST_OBJAGG is not set
-# CONFIG_TEST_STACKINIT is not set
-# CONFIG_TEST_MEMINIT is not set
-CONFIG_TEST_FREE_PAGES=m
-CONFIG_ARCH_USE_MEMTEST=y
-CONFIG_MEMTEST=y
-# end of Kernel Testing and Coverage
-# end of Kernel hacking
-# CONFIG_ANON_VMA_NAME is not set
-CONFIG_NET_9P_FD=m
-CONFIG_DEVTMPFS_SAFE=y
-CONFIG_GNSS_USB=m
-CONFIG_MTD_NAND_RENESAS=m
-CONFIG_NET_VENDOR_ENGLEDER=y
-CONFIG_TSNEP=m
-# CONFIG_TSNEP_SELFTESTS is not set
-CONFIG_LAN966X_SWITCH=m
-CONFIG_NET_VENDOR_VERTEXCOM=y
-CONFIG_MSE102X=m
-CONFIG_MCTP_SERIAL=m
-CONFIG_MCTP_TRANSPORT_I2C=m
-# CONFIG_WWAN_DEBUGFS is not set
-CONFIG_SERIAL_8250_PERICOM=m
-CONFIG_SPMI_MTK_PMIF=m
-CONFIG_PINCTRL_IMXRT1050=y
-CONFIG_PINCTRL_IMX93=m
-CONFIG_PINCTRL_SDX65=m
-CONFIG_PINCTRL_SM8450=m
-CONFIG_PINCTRL_SM8450_LPASS_LPI=m
-CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
-CONFIG_PINCTRL_SM8280XP_LPASS_LPI=m
-CONFIG_GPIO_SIM=m
-CONFIG_CHARGER_MAX77976=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_SENSORS_NZXT_SMART2=m
-CONFIG_SENSORS_DELTA_AHE50DC_FAN=m
-CONFIG_SENSORS_IR38064_REGULATOR=y
-CONFIG_SENSORS_MP5023=m
-CONFIG_SENSORS_INA238=m
-CONFIG_RZG2L_THERMAL=m
-CONFIG_RENESAS_RZG2LWDT=m
-CONFIG_REGULATOR_MAX20086=m
-CONFIG_VIDEO_STM32_DMA2D=m
-CONFIG_VIDEO_OV5693=m
-CONFIG_DRM_RCAR_USE_LVDS=y
-CONFIG_DRM_RCAR_USE_MIPI_DSI=y
-CONFIG_DRM_RCAR_MIPI_DSI=m
-CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
-CONFIG_DRM_PANEL_JDI_R63452=m
-CONFIG_DRM_PANEL_NOVATEK_NT35950=m
-CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
-CONFIG_TINYDRM_ILI9163=m
-CONFIG_SND_AMD_ACP_CONFIG=m
-CONFIG_SND_SOC_APPLE_MCA=m
-CONFIG_SND_SOC_AK4375=m
-CONFIG_SND_SOC_TLV320ADC3XXX=m
-CONFIG_HID_LETSKETCH=m
-CONFIG_LEDS_MT6360=m
-CONFIG_VIDEO_MAX96712=m
-CONFIG_COMMON_CLK_LAN966X=y
-CONFIG_COMMON_CLK_MT7986=y
-CONFIG_COMMON_CLK_MT7986_ETHSYS=y
-CONFIG_RENESAS_OSTM=y
-CONFIG_EXYNOS_USI=m
-CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
-CONFIG_AD74413R=m
-CONFIG_AD3552R=m
-CONFIG_AD7293=m
-CONFIG_ADMV1013=m
-CONFIG_ADMV1014=m
-CONFIG_ADMV4420=m
-CONFIG_PHY_MESON8_HDMI_TX=m
-CONFIG_PHY_FSL_IMX8M_PCIE=m
-CONFIG_PHY_FSL_LYNX_28G=m
-CONFIG_PHY_LAN966X_SERDES=m
-CONFIG_PHY_QCOM_EDP=m
-# CONFIG_CACHEFILES_ERROR_INJECTION is not set
-CONFIG_UNICODE_UTF8_DATA=m
-# CONFIG_NET_DEV_REFCNT_TRACKER is not set
-# CONFIG_NET_NS_REFCNT_TRACKER is not set
-# CONFIG_KFENCE is not set
-# CONFIG_FTRACE_SORT_STARTUP_TEST is not set
-CONFIG_BACKTRACE_VERBOSE=y
-CONFIG_APPLE_PMGR_PWRSTATE=y
-CONFIG_APPLE_RTKIT=m
-CONFIG_APPLE_SART=m
-CONFIG_ADMV8818=m
-# CONFIG_KCSAN is not set
-CONFIG_PECI=m
-CONFIG_PECI_CPU=m
-CONFIG_PECI_ASPEED=m
-CONFIG_SENSORS_PECI_CPUTEMP=m
-CONFIG_SENSORS_PECI_DIMMTEMP=m
-# CONFIG_BOOT_CONFIG_EMBED is not set
-CONFIG_INITRAMFS_PRESERVE_MTIME=y
-CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y
-CONFIG_ARCH_BCMBCA=y
-CONFIG_ARCH_HPE=y
-CONFIG_ARCH_HPE_GXP=y
-CONFIG_ARM_ERRATA_764319=y
-# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
-CONFIG_CAN_CTUCANFD_PCI=m
-CONFIG_CAN_CTUCANFD_PLATFORM=m
-CONFIG_FW_LOADER_COMPRESS_XZ=y
-CONFIG_FW_LOADER_COMPRESS_ZSTD=y
-CONFIG_FW_UPLOAD=y
-CONFIG_QCOM_SSC_BLOCK_BUS=y
-CONFIG_MHI_BUS_EP=m
-CONFIG_MTK_ADSP_IPC=m
-CONFIG_EFI_COCO_SECRET=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=m
-CONFIG_SFC_SIENA=m
-CONFIG_SFC_SIENA_MTD=y
-CONFIG_SFC_SIENA_MCDI_MON=y
-CONFIG_SFC_SIENA_SRIOV=y
-# CONFIG_SFC_SIENA_MCDI_LOGGING is not set
-CONFIG_ADIN1100_PHY=m
-CONFIG_DP83TD510_PHY=m
-CONFIG_WLAN_VENDOR_PURELIFI=y
-CONFIG_PLFXLC=m
-CONFIG_RTW89_8852CE=m
-CONFIG_WLAN_VENDOR_SILABS=y
-CONFIG_MTK_T7XX=m
-CONFIG_JOYSTICK_SENSEHAT=m
-CONFIG_INPUT_IQS7222=m
-# CONFIG_HVC_DCC_SERIALIZE_SMP is not set
-CONFIG_SPI_MTK_SNFI=m
-CONFIG_SPI_NPCM_FIU=m
-CONFIG_SPI_NPCM_PSPI=m
-CONFIG_PINCTRL_IMXRT1170=y
-CONFIG_PINCTRL_SC7280_LPASS_LPI=m
-CONFIG_PINCTRL_SM8250_LPASS_LPI=m
-CONFIG_SENSORS_LAN966X=m
-CONFIG_SENSORS_NCT6775_I2C=m
-CONFIG_SENSORS_XDPE152=m
-CONFIG_RENESAS_RZN1WDT=m
-CONFIG_GXP_WATCHDOG=m
-CONFIG_REGULATOR_RT5759=m
-CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
-CONFIG_DRM_FSL_LDB=m
-CONFIG_DRM_LONTIUM_LT9211=m
-CONFIG_DRM_DW_HDMI_GP_AUDIO=m
-CONFIG_DRM_SSD130X_SPI=m
-CONFIG_SND_SERIAL_GENERIC=m
-CONFIG_SND_SOC_CS35L45_SPI=m
-CONFIG_SND_SOC_CS35L45_I2C=m
-CONFIG_SND_SOC_MAX98396=m
-CONFIG_SND_SOC_WM8731_I2C=m
-CONFIG_SND_SOC_WM8731_SPI=m
-CONFIG_SND_SOC_WM8940=m
-CONFIG_HID_MEGAWORLD_FF=m
-CONFIG_TYPEC_MUX_FSA4480=m
-CONFIG_LEDS_PWM_MULTICOLOR=m
-CONFIG_LEDS_QCOM_LPG=m
-CONFIG_TEGRA186_GPC_DMA=m
-# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set
-CONFIG_PWM_XILINX=m
-CONFIG_HTE=y
-CONFIG_HTE_TEGRA194=m
-# CONFIG_HTE_TEGRA194_TEST is not set
-# CONFIG_CACHEFILES_ONDEMAND is not set
-CONFIG_TRUSTED_KEYS_TPM=y
-CONFIG_TRUSTED_KEYS_TEE=y
-CONFIG_TRUSTED_KEYS_CAAM=y
-CONFIG_CRYPTO_SM3_GENERIC=m
-CONFIG_CRYPTO_SM4_GENERIC=m
-# CONFIG_FIPS_SIGNATURE_SELFTEST is not set
-CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y
-# CONFIG_DEBUG_NET is not set
-CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
-CONFIG_SND_SOC_CS35L45_I2C=m
-CONFIG_SND_SOC_WM8731_I2C=m
-CONFIG_SND_SOC_WM8731_SPI=m
-CONFIG_SND_SOC_WM8940=m
-# CONFIG_CGROUP_FAVOR_DYNMODS is not set
-CONFIG_ARCH_BCMBCA_CORTEXA7=y
-CONFIG_ARCH_BCMBCA_CORTEXA9=y
-CONFIG_ARCH_BCMBCA_BRAHMAB15=y
-CONFIG_ARCH_MSM8909=y
-CONFIG_ARCH_SUNPLUS=y
-CONFIG_SOC_SP7021=y
-# CONFIG_UNUSED_BOARD_FILES is not set
-# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
-CONFIG_DAMON_LRU_SORT=y
-CONFIG_NF_FLOW_TABLE_PROCFS=y
-CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
-CONFIG_PCI_EPF_VNTB=m
-CONFIG_ARM_SCMI_POWER_CONTROL=m
-CONFIG_BLK_DEV_UBLK=m
-CONFIG_NVME_AUTH=y
-CONFIG_NVME_TARGET_AUTH=y
-CONFIG_VCPU_STALL_DETECTOR=m
-CONFIG_SCSI_BUSLOGIC=m
-CONFIG_SCSI_FLASHPOINT=y
-CONFIG_AHCI_BRCM=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
-CONFIG_NET_VENDOR_WANGXUN=y
-CONFIG_NET_VENDOR_ADI=y
-CONFIG_ADIN1110=m
-CONFIG_NGBE=m
-CONFIG_TXGBE=m
-CONFIG_NET_VENDOR_SUNPLUS=y
-CONFIG_SP7021_EMAC=m
-CONFIG_CAN_NETLINK=y
-CONFIG_CAN_CAN327=m
-CONFIG_CAN_ESD_USB=m
-CONFIG_HW_RANDOM_BCM2835=m
-CONFIG_TCG_TIS_I2C=m
-# CONFIG_RANDOM_TRUST_CPU is not set
-CONFIG_I2C_BRCMSTB=m
-CONFIG_I2C_NPCM=m
-CONFIG_I2C_RZV2M=m
-CONFIG_SPI_BCM63XX_HSSPI=m
-CONFIG_SPI_GXP=m
-CONFIG_SPI_MICROCHIP_CORE=m
-CONFIG_SPI_MICROCHIP_CORE_QSPI=m
-CONFIG_SPI_SUNPLUS_SP7021=m
-CONFIG_PINCTRL_MSM8909=m
-CONFIG_PINCTRL_SM6375=m
-CONFIG_PINCTRL_SUN20I_D1=y
-CONFIG_SENSORS_LT7182S=m
-CONFIG_SUNPLUS_WATCHDOG=m
-CONFIG_VIDEO_SUN6I_MIPI_CSI2=m
-CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m
-CONFIG_VIDEO_AR0521=m
-CONFIG_DRM_PANEL_EBBG_FT8719=m
-CONFIG_DRM_TI_DLPC3433=m
-CONFIG_DRM_IMX8QM_LDB=m
-CONFIG_DRM_IMX8QXP_LDB=m
-CONFIG_DRM_IMX8QXP_PIXEL_COMBINER=m
-CONFIG_DRM_IMX8QXP_PIXEL_LINK=m
-CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI=m
-# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set
-CONFIG_A64FX_DIAG=y
-CONFIG_MTK_SVS=m
-CONFIG_QCOM_ICC_BWMON=m
-CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=m
-CONFIG_NPCM_ADC=m
-CONFIG_QCOM_SPMI_RRADC=m
-CONFIG_PWM_CLK=m
-CONFIG_PWM_OMAP_DMTIMER=m
-CONFIG_RESET_TI_TPS380X=m
-CONFIG_A64FX_DIAG=y
-# CONFIG_RV is not set
-# Ethernet Power Sourcing Equipment Support
-CONFIG_PSE_CONTROLLER=y
-CONFIG_PSE_REGULATOR=m
-CONFIG_STAGING_MEDIA_DEPRECATED=y
-# CONFIG_FORCE_NR_CPUS is not set
-# CONFIG_DEBUG_MAPLE_TREE is not set
-CONFIG_QCOM_TSENS=m
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_KERNEL_ZSTD=y
diff --git a/aarch64-server-omv-defconfig b/aarch64-server-omv-defconfig
deleted file mode 100644
index 0f94eeb..0000000
--- a/aarch64-server-omv-defconfig
+++ /dev/null
@@ -1,13115 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# Linux/arm64 5.16.1 Kernel Configuration
-#
-CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GCC) 11.2.0 20210728 (OpenMandriva)"
-CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=110200
-CONFIG_CLANG_VERSION=0
-CONFIG_AS_IS_GNU=y
-CONFIG_AS_VERSION=23700
-CONFIG_LD_VERSION=0
-CONFIG_LD_IS_LLD=y
-CONFIG_LLD_VERSION=130000
-CONFIG_CC_CAN_LINK=y
-CONFIG_CC_CAN_LINK_STATIC=y
-CONFIG_CC_HAS_ASM_GOTO=y
-CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
-CONFIG_TOOLS_SUPPORT_RELR=y
-CONFIG_CC_HAS_ASM_INLINE=y
-CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
-CONFIG_IRQ_WORK=y
-CONFIG_BUILDTIME_TABLE_SORT=y
-CONFIG_THREAD_INFO_IN_TASK=y
-
-#
-# General setup
-#
-CONFIG_INIT_ENV_ARG_LIMIT=32
-# CONFIG_COMPILE_TEST is not set
-# CONFIG_WERROR is not set
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_BUILD_SALT=""
-CONFIG_DEFAULT_INIT=""
-CONFIG_DEFAULT_HOSTNAME="omv"
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_POSIX_MQUEUE_SYSCTL=y
-CONFIG_WATCH_QUEUE=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-# CONFIG_USELIB is not set
-# CONFIG_AUDIT is not set
-# CONFIG_HAVE_ARCH_AUDITSYSCALL is not set
-# CONFIG_AUDITSYSCALL is not set
-
-#
-# IRQ subsystem
-#
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_INJECTION=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_SIM=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_GENERIC_IRQ_IPI=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_IRQ_MSI_IOMMU=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_SPARSE_IRQ=y
-# CONFIG_GENERIC_IRQ_DEBUGFS is not set
-# end of IRQ subsystem
-
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-
-#
-# Timers subsystem
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ_COMMON=y
-# CONFIG_HZ_PERIODIC is not set
-CONFIG_NO_HZ_IDLE=y
-# CONFIG_NO_HZ_FULL is not set
-CONFIG_CONTEXT_TRACKING=y
-# CONFIG_CONTEXT_TRACKING_FORCE is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
-# end of Timers subsystem
-
-CONFIG_BPF=y
-CONFIG_HAVE_EBPF_JIT=y
-CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
-
-#
-# BPF subsystem
-#
-CONFIG_BPF_SYSCALL=y
-CONFIG_BPF_JIT=y
-CONFIG_BPF_JIT_ALWAYS_ON=y
-CONFIG_BPF_JIT_DEFAULT_ON=y
-# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
-CONFIG_USERMODE_DRIVER=y
-# CONFIG_BPF_PRELOAD is not set
-CONFIG_BPF_LSM=y
-# end of BPF subsystem
-
-CONFIG_PREEMPT_VOLUNTARY_BUILD=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-# CONFIG_PREEMPT is not set
-CONFIG_PREEMPT_DYNAMIC=y
-CONFIG_SCHED_CORE=y
-
-#
-# CPU/Task time and stats accounting
-#
-CONFIG_VIRT_CPU_ACCOUNTING=y
-# CONFIG_TICK_CPU_ACCOUNTING is not set
-CONFIG_VIRT_CPU_ACCOUNTING_GEN=y
-# CONFIG_IRQ_TIME_ACCOUNTING is not set
-CONFIG_SCHED_THERMAL_PRESSURE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_PSI=y
-# CONFIG_PSI_DEFAULT_DISABLED is not set
-# end of CPU/Task time and stats accounting
-
-CONFIG_CPU_ISOLATION=y
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_RCU_EXPERT is not set
-CONFIG_SRCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TASKS_RCU_GENERIC=y
-CONFIG_TASKS_RCU=y
-CONFIG_TASKS_RUDE_RCU=y
-CONFIG_TASKS_TRACE_RCU=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RCU_NEED_SEGCBLIST=y
-# end of RCU Subsystem
-
-CONFIG_BUILD_BIN2C=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-# CONFIG_IKHEADERS is not set
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
-CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
-CONFIG_PRINTK_INDEX=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-
-#
-# Scheduler features
-#
-# CONFIG_UCLAMP_TASK is not set
-# end of Scheduler features
-
-CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
-CONFIG_CC_HAS_INT128=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_ARCH_SUPPORTS_INT128=y
-CONFIG_NUMA_BALANCING=y
-CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
-CONFIG_CGROUPS=y
-CONFIG_PAGE_COUNTER=y
-CONFIG_MEMCG=y
-CONFIG_MEMCG_SWAP=y
-CONFIG_MEMCG_KMEM=y
-CONFIG_BLK_CGROUP=y
-CONFIG_CGROUP_WRITEBACK=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_CFS_BANDWIDTH=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_CGROUP_PIDS=y
-CONFIG_CGROUP_RDMA=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_HUGETLB=y
-CONFIG_CPUSETS=y
-CONFIG_PROC_PID_CPUSET=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_PERF=y
-CONFIG_CGROUP_BPF=y
-CONFIG_CGROUP_MISC=y
-# CONFIG_CGROUP_DEBUG is not set
-CONFIG_SOCK_CGROUP_DATA=y
-CONFIG_NAMESPACES=y
-CONFIG_UTS_NS=y
-CONFIG_TIME_NS=y
-CONFIG_IPC_NS=y
-CONFIG_USER_NS=y
-CONFIG_PID_NS=y
-CONFIG_NET_NS=y
-CONFIG_CHECKPOINT_RESTORE=y
-# CONFIG_SCHED_AUTOGROUP is not set
-# CONFIG_SYSFS_DEPRECATED is not set
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_XZ=y
-CONFIG_RD_LZO=y
-CONFIG_RD_LZ4=y
-CONFIG_RD_ZSTD=y
-CONFIG_BOOT_CONFIG=y
-# CONFIG_CC_OPTIMIZE_BASAL is not set
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_LD_ORPHAN_WARN=y
-CONFIG_SYSCTL=y
-CONFIG_HAVE_UID16=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_EXPERT=y
-CONFIG_UID16=y
-CONFIG_MULTIUSER=y
-CONFIG_SGETMASK_SYSCALL=y
-# CONFIG_SYSFS_SYSCALL is not set
-CONFIG_FHANDLE=y
-CONFIG_POSIX_TIMERS=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_FUTEX_PI=y
-CONFIG_HAVE_FUTEX_CMPXCHG=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_IO_URING=y
-CONFIG_ADVISE_SYSCALLS=y
-CONFIG_HAVE_ARCH_USERFAULTFD_MINOR=y
-CONFIG_LRU_GEN=y
-CONFIG_LRU_GEN_ENABLED=y
-# CONFIG_LRU_GEN_STATS is not set
-CONFIG_MEMBARRIER=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_BASE_RELATIVE=y
-CONFIG_USERFAULTFD=y
-CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
-CONFIG_KCMP=y
-CONFIG_RSEQ=y
-# CONFIG_DEBUG_RSEQ is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_HAVE_PERF_EVENTS=y
-# CONFIG_PC104 is not set
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_PERF_EVENTS=y
-# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
-# end of Kernel Performance Events And Counters
-
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-CONFIG_SLAB_MERGE_DEFAULT=y
-CONFIG_SLAB_FREELIST_RANDOM=y
-CONFIG_SLAB_FREELIST_HARDENED=y
-CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
-CONFIG_SLUB_CPU_PARTIAL=y
-CONFIG_SYSTEM_DATA_VERIFICATION=y
-CONFIG_PROFILING=y
-CONFIG_TRACEPOINTS=y
-# end of General setup
-
-CONFIG_ARM64=y
-CONFIG_64BIT=y
-CONFIG_MMU=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_CONT_PTE_SHIFT=4
-CONFIG_ARM64_CONT_PMD_SHIFT=4
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=33
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_SMP=y
-CONFIG_KERNEL_MODE_NEON=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_PGTABLE_LEVELS=4
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-
-#
-# Platform selection
-#
-CONFIG_ARCH_ACTIONS=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_ALPINE=y
-CONFIG_ARCH_APPLE=y
-CONFIG_ARCH_BCM=y
-CONFIG_ARCH_NXP=y
-CONFIG_ARCH_BCM2835=y
-CONFIG_ARCH_BCM4908=y
-CONFIG_ARCH_BCM_IPROC=y
-CONFIG_ARCH_BERLIN=y
-CONFIG_ARCH_BITMAIN=y
-CONFIG_ARCH_BRCMSTB=y
-CONFIG_ARCH_EXYNOS=y
-CONFIG_ARCH_SPARX5=y
-CONFIG_ARCH_K3=y
-CONFIG_ARCH_LAYERSCAPE=y
-CONFIG_ARCH_LG1K=y
-CONFIG_ARCH_HISI=y
-CONFIG_ARCH_KEEMBAY=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MESON=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_ARCH_MXC=y
-CONFIG_ARCH_NPCM=y
-CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_REALTEK=y
-CONFIG_ARCH_RENESAS=y
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_ARCH_S32=y
-CONFIG_ARCH_SEATTLE=y
-CONFIG_ARCH_INTEL_SOCFPGA=y
-CONFIG_ARCH_SYNQUACER=y
-CONFIG_ARCH_TEGRA=y
-CONFIG_ARCH_TESLA_FSD=y
-CONFIG_ARCH_SPRD=y
-CONFIG_ARCH_THUNDER=y
-CONFIG_ARCH_THUNDER2=y
-CONFIG_ARCH_UNIPHIER=y
-# CONFIG_ARCH_VEXPRESS is not set
-CONFIG_ARCH_VISCONTI=y
-CONFIG_ARCH_XGENE=y
-CONFIG_ARCH_ZYNQMP=y
-# end of Platform selection
-
-#
-# Kernel Features
-#
-
-#
-# ARM errata workarounds via the alternatives framework
-#
-CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
-CONFIG_ARM64_ERRATUM_826319=y
-CONFIG_ARM64_ERRATUM_827319=y
-CONFIG_ARM64_ERRATUM_824069=y
-CONFIG_ARM64_ERRATUM_819472=y
-CONFIG_ARM64_ERRATUM_832075=y
-CONFIG_ARM64_ERRATUM_834220=y
-CONFIG_ARM64_ERRATUM_1742098=y
-CONFIG_ARM64_ERRATUM_2441009=y
-CONFIG_ARM64_ERRATUM_845719=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_ERRATUM_1024718=y
-CONFIG_ARM64_ERRATUM_1418040=y
-CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
-CONFIG_ARM64_ERRATUM_1165522=y
-CONFIG_ARM64_ERRATUM_1319367=y
-CONFIG_ARM64_ERRATUM_1530923=y
-CONFIG_ARM64_ERRATUM_2441007=y
-CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
-CONFIG_ARM64_ERRATUM_1286807=y
-CONFIG_ARM64_ERRATUM_1463225=y
-CONFIG_ARM64_ERRATUM_1542419=y
-CONFIG_ARM64_ERRATUM_1508412=y
-CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE=y
-CONFIG_ARM64_ERRATUM_2119858=y
-CONFIG_ARM64_ERRATUM_2139208=y
-CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
-CONFIG_ARM64_ERRATUM_2054223=y
-CONFIG_ARM64_ERRATUM_2067961=y
-CONFIG_ARM64_ERRATUM_2457168=y
-CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE=y
-CONFIG_ARM64_ERRATUM_2253138=y
-CONFIG_ARM64_ERRATUM_2224489=y
-CONFIG_ARM64_ERRATUM_2064142=y
-CONFIG_ARM64_ERRATUM_2038923=y
-CONFIG_ARM64_ERRATUM_1902691=y
-CONFIG_ARM64_ERRATUM_2051678=y
-CONFIG_ARM64_ERRATUM_2077057=y
-CONFIG_ARM64_ERRATUM_2658417=y
-CONFIG_CAVIUM_ERRATUM_22375=y
-CONFIG_CAVIUM_ERRATUM_23144=y
-CONFIG_CAVIUM_ERRATUM_23154=y
-CONFIG_CAVIUM_ERRATUM_27456=y
-CONFIG_CAVIUM_ERRATUM_30115=y
-CONFIG_CAVIUM_TX2_ERRATUM_219=y
-CONFIG_FUJITSU_ERRATUM_010001=y
-CONFIG_HISILICON_ERRATUM_161600802=y
-CONFIG_QCOM_FALKOR_ERRATUM_1003=y
-CONFIG_QCOM_FALKOR_ERRATUM_1009=y
-CONFIG_QCOM_QDF2400_ERRATUM_0065=y
-CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
-CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
-CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
-# end of ARM errata workarounds via the alternatives framework
-
-CONFIG_ARM64_4K_PAGES=y
-# CONFIG_ARM64_16K_PAGES is not set
-# CONFIG_ARM64_64K_PAGES is not set
-# CONFIG_ARM64_VA_BITS_39 is not set
-CONFIG_ARM64_VA_BITS_48=y
-CONFIG_ARM64_VA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PA_BITS=48
-# CONFIG_CPU_BIG_ENDIAN is not set
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_SCHED_MC=y
-# CONFIG_SCHED_CLUSTER is not set
-CONFIG_SCHED_SMT=y
-CONFIG_NR_CPUS=480
-CONFIG_HOTPLUG_CPU=y
-CONFIG_NUMA=y
-CONFIG_NODES_SHIFT=6
-CONFIG_USE_PERCPU_NUMA_NODE_ID=y
-CONFIG_HAVE_SETUP_PER_CPU_AREA=y
-CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
-CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
-CONFIG_HZ_100=y
-# CONFIG_HZ_250 is not set
-# CONFIG_HZ_300 is not set
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=100
-CONFIG_ARCH_FORCE_MAX_ORDER=12
-CONFIG_SCHED_HRTICK=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_HW_PERF_EVENTS=y
-CONFIG_ARCH_HAS_FILTER_PGPROT=y
-CONFIG_PARAVIRT=y
-# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
-CONFIG_KEXEC=y
-CONFIG_KEXEC_FILE=y
-# CONFIG_KEXEC_SIG is not set
-# CONFIG_CRASH_DUMP is not set
-CONFIG_TRANS_TABLE=y
-# CONFIG_XEN is not set
-CONFIG_FORCE_MAX_ZONEORDER=11
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_ARM64_SW_TTBR0_PAN=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_COMPAT=y
-CONFIG_KUSER_HELPERS=y
-CONFIG_ARMV8_DEPRECATED=y
-CONFIG_SWP_EMULATION=y
-CONFIG_CP15_BARRIER_EMULATION=y
-CONFIG_SETEND_EMULATION=y
-
-#
-# ARMv8.1 architectural features
-#
-CONFIG_ARM64_HW_AFDBM=y
-CONFIG_ARM64_PAN=y
-CONFIG_AS_HAS_LDAPR=y
-CONFIG_AS_HAS_LSE_ATOMICS=y
-CONFIG_ARM64_LSE_ATOMICS=y
-CONFIG_ARM64_USE_LSE_ATOMICS=y
-# end of ARMv8.1 architectural features
-
-#
-# ARMv8.2 architectural features
-#
-CONFIG_ARM64_PMEM=y
-CONFIG_ARM64_RAS_EXTN=y
-CONFIG_ARM64_CNP=y
-# end of ARMv8.2 architectural features
-
-#
-# ARMv8.3 architectural features
-#
-CONFIG_ARM64_PTR_AUTH=y
-CONFIG_ARM64_PTR_AUTH_KERNEL=y
-CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
-CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
-CONFIG_AS_HAS_PAC=y
-CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
-# end of ARMv8.3 architectural features
-
-#
-# ARMv8.4 architectural features
-#
-CONFIG_ARM64_AMU_EXTN=y
-CONFIG_AS_HAS_ARMV8_4=y
-CONFIG_ARM64_TLB_RANGE=y
-# end of ARMv8.4 architectural features
-
-#
-# ARMv8.5 architectural features
-#
-CONFIG_AS_HAS_ARMV8_5=y
-CONFIG_ARM64_BTI=y
-CONFIG_ARM64_BTI_KERNEL=y
-CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
-CONFIG_ARM64_E0PD=y
-CONFIG_ARCH_RANDOM=y
-CONFIG_ARM64_AS_HAS_MTE=y
-CONFIG_ARM64_MTE=y
-# end of ARMv8.5 architectural features
-
-#
-# ARMv8.7 architectural features
-#
-CONFIG_ARM64_EPAN=y
-# end of ARMv8.7 architectural features
-
-CONFIG_ARM64_SVE=y
-CONFIG_ARM64_SME=y
-CONFIG_ARM64_MODULE_PLTS=y
-CONFIG_ARM64_PSEUDO_NMI=y
-# CONFIG_ARM64_DEBUG_PRIORITY_MASKING is not set
-CONFIG_RELOCATABLE=y
-CONFIG_RANDOMIZE_BASE=y
-CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_STACKPROTECTOR_PER_TASK=y
-# CONFIG_COMPAT_VDSO is not set
-# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
-# end of Kernel Features
-
-#
-# Boot options
-#
-CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
-CONFIG_CMDLINE=""
-CONFIG_EFI_STUB=y
-CONFIG_EFI=y
-CONFIG_DMI=y
-# end of Boot options
-
-CONFIG_SYSVIPC_COMPAT=y
-
-#
-# Power management options
-#
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_SUSPEND_SKIP_SYNC is not set
-CONFIG_HIBERNATE_CALLBACKS=y
-CONFIG_HIBERNATION=y
-CONFIG_HIBERNATION_SNAPSHOT_DEV=y
-CONFIG_PM_STD_PARTITION=""
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_PM_AUTOSLEEP=y
-CONFIG_PM_WAKELOCKS=y
-CONFIG_PM_WAKELOCKS_LIMIT=100
-CONFIG_PM_WAKELOCKS_GC=y
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_CPU_PM=y
-CONFIG_ENERGY_MODEL=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_HIBERNATION_HEADER=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# end of Power management options
-
-#
-# CPU Power Management
-#
-
-#
-# CPU Idle
-#
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_GOV_TEO=y
-CONFIG_DT_IDLE_STATES=y
-
-#
-# ARM CPU Idle Drivers
-#
-CONFIG_ARM_CPUIDLE=y
-CONFIG_ARM_PSCI_CPUIDLE=y
-CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
-# end of ARM CPU Idle Drivers
-# end of CPU Idle
-
-#
-# CPU Frequency scaling
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=m
-CONFIG_CPU_FREQ_GOV_USERSPACE=m
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-
-#
-# CPU frequency scaling drivers
-#
-CONFIG_CPUFREQ_DT=m
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_ACPI_CPPC_CPUFREQ=m
-CONFIG_ACPI_CPPC_CPUFREQ_FIE=y
-CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m
-CONFIG_ARM_ARMADA_37XX_CPUFREQ=m
-CONFIG_ARM_ARMADA_8K_CPUFREQ=m
-CONFIG_ARM_SCPI_CPUFREQ=m
-CONFIG_ARM_BRCMSTB_AVS_CPUFREQ=m
-CONFIG_ARM_IMX_CPUFREQ_DT=m
-CONFIG_ARM_MEDIATEK_CPUFREQ=m
-CONFIG_ARM_MEDIATEK_CPUFREQ_HW=m
-CONFIG_ARM_QCOM_CPUFREQ_NVMEM=m
-CONFIG_ARM_QCOM_CPUFREQ_HW=m
-CONFIG_ARM_RASPBERRYPI_CPUFREQ=m
-CONFIG_ARM_SCMI_CPUFREQ=m
-# CONFIG_ARM_TEGRA20_CPUFREQ is not set
-CONFIG_ARM_TEGRA124_CPUFREQ=y
-CONFIG_ARM_TEGRA186_CPUFREQ=m
-CONFIG_ARM_TEGRA194_CPUFREQ=m
-CONFIG_QORIQ_CPUFREQ=m
-# end of CPU Frequency scaling
-# end of CPU Power Management
-
-CONFIG_ARCH_SUPPORTS_ACPI=y
-CONFIG_ACPI=y
-CONFIG_ACPI_GENERIC_GSI=y
-CONFIG_ACPI_CCA_REQUIRED=y
-# CONFIG_ACPI_DEBUGGER is not set
-CONFIG_ACPI_SPCR_TABLE=y
-# CONFIG_ACPI_EC_DEBUGFS is not set
-CONFIG_ACPI_AC=m
-CONFIG_ACPI_BATTERY=m
-CONFIG_ACPI_BUTTON=y
-CONFIG_ACPI_VIDEO=m
-CONFIG_ACPI_FAN=y
-CONFIG_ACPI_TAD=m
-CONFIG_ACPI_DOCK=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
-CONFIG_ACPI_MCFG=y
-CONFIG_ACPI_CPPC_LIB=y
-CONFIG_ACPI_PROCESSOR=y
-CONFIG_ACPI_IPMI=m
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_THERMAL=y
-CONFIG_ACPI_PLATFORM_PROFILE=m
-CONFIG_ACPI_CUSTOM_DSDT_FILE=""
-CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
-CONFIG_ACPI_TABLE_UPGRADE=y
-# CONFIG_ACPI_DEBUG is not set
-CONFIG_ACPI_PCI_SLOT=y
-CONFIG_ACPI_CONTAINER=y
-CONFIG_ACPI_HOTPLUG_MEMORY=y
-CONFIG_ACPI_HED=y
-CONFIG_ACPI_CUSTOM_METHOD=m
-CONFIG_ACPI_BGRT=y
-CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
-CONFIG_ACPI_NFIT=m
-# CONFIG_NFIT_SECURITY_DEBUG is not set
-CONFIG_ACPI_NUMA=y
-CONFIG_ACPI_HMAT=y
-CONFIG_HAVE_ACPI_APEI=y
-CONFIG_ACPI_APEI=y
-CONFIG_ACPI_APEI_GHES=y
-CONFIG_ACPI_APEI_PCIEAER=y
-CONFIG_ACPI_APEI_SEA=y
-CONFIG_ACPI_APEI_MEMORY_FAILURE=y
-CONFIG_ACPI_APEI_EINJ=m
-# CONFIG_ACPI_APEI_ERST_DEBUG is not set
-CONFIG_ACPI_WATCHDOG=y
-CONFIG_ACPI_CONFIGFS=m
-CONFIG_ACPI_PCC=y
-CONFIG_ACPI_PRMT=y
-CONFIG_ACPI_PFRUT=m
-CONFIG_ACPI_AGDI=y
-CONFIG_ACPI_IORT=y
-CONFIG_ACPI_GTDT=y
-CONFIG_ACPI_PPTT=y
-CONFIG_PMIC_OPREGION=y
-CONFIG_ACPI_VIOT=y
-CONFIG_IRQ_BYPASS_MANAGER=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_KVM_IRQCHIP=y
-CONFIG_HAVE_KVM_IRQFD=y
-CONFIG_HAVE_KVM_IRQ_ROUTING=y
-CONFIG_HAVE_KVM_EVENTFD=y
-CONFIG_KVM_MMIO=y
-CONFIG_HAVE_KVM_MSI=y
-CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
-CONFIG_KVM_VFIO=y
-CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
-CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
-CONFIG_HAVE_KVM_IRQ_BYPASS=y
-CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
-CONFIG_KVM_XFER_TO_GUEST_WORK=y
-CONFIG_VIRTUALIZATION=y
-CONFIG_KVM=y
-# CONFIG_NVHE_EL2_DEBUG is not set
-CONFIG_ARM64_CRYPTO=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA512_ARM64=y
-CONFIG_CRYPTO_SHA1_ARM64_CE=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA512_ARM64_CE=y
-CONFIG_CRYPTO_SHA3_ARM64=m
-CONFIG_CRYPTO_SM3_NEON=m
-CONFIG_CRYPTO_SM3_ARM64_CE=m
-CONFIG_CRYPTO_SM4_ARM64_CE=m
-CONFIG_CRYPTO_SM4_ARM64_CE_BLK=m
-CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=m
-CONFIG_CRYPTO_GHASH_ARM64_CE=m
-CONFIG_CRYPTO_POLYVAL_ARM64_CE=m
-CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
-CONFIG_CRYPTO_CHACHA20_NEON=y
-CONFIG_CRYPTO_POLY1305_NEON=y
-CONFIG_CRYPTO_NHPOLY1305_NEON=y
-CONFIG_CRYPTO_AES_ARM64_BS=y
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-
-#
-# General architecture-dependent options
-#
-CONFIG_CRASH_CORE=y
-CONFIG_KEXEC_CORE=y
-CONFIG_HAVE_IMA_KEXEC=y
-CONFIG_KPROBES=y
-CONFIG_JUMP_LABEL=y
-# CONFIG_STATIC_KEYS_SELFTEST is not set
-CONFIG_UPROBES=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_KRETPROBES=y
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
-CONFIG_HAVE_NMI=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_KEEPINITRD=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
-CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_HAVE_ASM_MODVERSIONS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
-CONFIG_MMU_GATHER_TABLE_FREE=y
-CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
-CONFIG_HAVE_CMPXCHG_LOCAL=y
-CONFIG_HAVE_CMPXCHG_DOUBLE=y
-CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
-CONFIG_HAVE_ARCH_SECCOMP=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_SECCOMP=y
-CONFIG_SECCOMP_FILTER=y
-# CONFIG_SECCOMP_CACHE_DEBUG is not set
-CONFIG_HAVE_ARCH_STACKLEAK=y
-CONFIG_HAVE_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR_STRONG=y
-CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
-CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
-CONFIG_LTO_NONE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MOVE_PUD=y
-CONFIG_HAVE_MOVE_PMD=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-CONFIG_HAVE_ARCH_HUGE_VMAP=y
-CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_COMPAT_OLD_SIGACTION=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_HAVE_ARCH_VMAP_STACK=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET=y
-CONFIG_VMAP_STACK=y
-CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_STRICT_MODULE_RWX=y
-CONFIG_HAVE_ARCH_COMPILER_H=y
-CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
-CONFIG_ARCH_USE_MEMREMAP_PROT=y
-# CONFIG_LOCK_EVENT_COUNTS is not set
-CONFIG_ARCH_HAS_RELR=y
-CONFIG_RELR=y
-CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
-# CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC is not set
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-# end of GCOV-based kernel profiling
-
-CONFIG_HAVE_GCC_PLUGINS=y
-CONFIG_GCC_PLUGINS=y
-# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
-# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
-# end of General architecture-dependent options
-CONFIG_RANDSTRUCT_NONE=y
-# CONFIG_RANDSTRUCT_FULL is not set
-# CONFIG_RANDSTRUCT_PERFORMANCE is not set
-
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULE_SIG_FORMAT=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_ASM_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_MODULE_SIG=y
-# CONFIG_MODULE_SIG_FORCE is not set
-# CONFIG_MODULE_SIG_ALL is not set
-CONFIG_MODULE_SIG_SHA1=y
-# CONFIG_MODULE_SIG_SHA224 is not set
-# CONFIG_MODULE_SIG_SHA256 is not set
-# CONFIG_MODULE_SIG_SHA384 is not set
-# CONFIG_MODULE_SIG_SHA512 is not set
-CONFIG_MODULE_SIG_HASH="sha1"
-CONFIG_MODULE_COMPRESS_NONE=y
-# CONFIG_MODULE_COMPRESS_GZIP is not set
-# CONFIG_MODULE_COMPRESS_XZ is not set
-# CONFIG_MODULE_COMPRESS_ZSTD is not set
-# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
-CONFIG_MODPROBE_PATH="/sbin/modprobe"
-# CONFIG_TRIM_UNUSED_KSYMS is not set
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_BLOCK=y
-# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set
-CONFIG_BLK_RQ_ALLOC_TIME=y
-CONFIG_BLK_CGROUP_RWSTAT=y
-CONFIG_BLK_DEV_BSG_COMMON=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=y
-CONFIG_BLK_DEV_ZONED=y
-CONFIG_BLK_DEV_THROTTLING=y
-# CONFIG_BLK_DEV_THROTTLING_LOW is not set
-CONFIG_BLK_WBT=y
-CONFIG_BLK_WBT_MQ=y
-CONFIG_BLK_CGROUP_IOLATENCY=y
-CONFIG_BLK_CGROUP_FC_APPID=y
-CONFIG_BLK_CGROUP_IOCOST=y
-CONFIG_BLK_CGROUP_IOPRIO=y
-# CONFIG_BLK_DEBUG_FS is not set
-CONFIG_BLK_SED_OPAL=y
-CONFIG_BLK_INLINE_ENCRYPTION=y
-CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_AIX_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-CONFIG_ATARI_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_MSDOS_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-# CONFIG_MINIX_SUBPARTITION is not set
-CONFIG_SOLARIS_X86_PARTITION=y
-# CONFIG_UNIXWARE_DISKLABEL is not set
-CONFIG_LDM_PARTITION=y
-# CONFIG_LDM_DEBUG is not set
-# CONFIG_SGI_PARTITION is not set
-CONFIG_ULTRIX_PARTITION=y
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-CONFIG_SYSV68_PARTITION=y
-# CONFIG_CMDLINE_PARTITION is not set
-# end of Partition Types
-
-CONFIG_BLOCK_COMPAT=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_MQ_RDMA=y
-CONFIG_BLK_PM=y
-CONFIG_BLOCK_HOLDER_DEPRECATED=y
-
-#
-# IO Schedulers
-#
-CONFIG_MQ_IOSCHED_DEADLINE=y
-CONFIG_MQ_IOSCHED_KYBER=y
-CONFIG_IOSCHED_BFQ=y
-CONFIG_BFQ_GROUP_IOSCHED=y
-# CONFIG_BFQ_CGROUP_DEBUG is not set
-# end of IO Schedulers
-
-CONFIG_PREEMPT_NOTIFIERS=y
-CONFIG_PADATA=y
-CONFIG_ASN1=y
-CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
-CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
-CONFIG_ARCH_INLINE_SPIN_LOCK=y
-CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
-CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
-CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
-CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
-CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
-CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
-CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
-CONFIG_ARCH_INLINE_READ_LOCK=y
-CONFIG_ARCH_INLINE_READ_LOCK_BH=y
-CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
-CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
-CONFIG_ARCH_INLINE_READ_UNLOCK=y
-CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
-CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
-CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
-CONFIG_ARCH_INLINE_WRITE_LOCK=y
-CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
-CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
-CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
-CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
-CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
-CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
-CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
-CONFIG_INLINE_SPIN_TRYLOCK=y
-CONFIG_INLINE_SPIN_TRYLOCK_BH=y
-CONFIG_INLINE_SPIN_LOCK=y
-CONFIG_INLINE_SPIN_LOCK_BH=y
-CONFIG_INLINE_SPIN_LOCK_IRQ=y
-CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
-CONFIG_INLINE_SPIN_UNLOCK_BH=y
-CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
-CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
-CONFIG_INLINE_READ_LOCK=y
-CONFIG_INLINE_READ_LOCK_BH=y
-CONFIG_INLINE_READ_LOCK_IRQ=y
-CONFIG_INLINE_READ_LOCK_IRQSAVE=y
-CONFIG_INLINE_READ_UNLOCK=y
-CONFIG_INLINE_READ_UNLOCK_BH=y
-CONFIG_INLINE_READ_UNLOCK_IRQ=y
-CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
-CONFIG_INLINE_WRITE_LOCK=y
-CONFIG_INLINE_WRITE_LOCK_BH=y
-CONFIG_INLINE_WRITE_LOCK_IRQ=y
-CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
-CONFIG_INLINE_WRITE_UNLOCK=y
-CONFIG_INLINE_WRITE_UNLOCK_BH=y
-CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
-CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
-CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
-CONFIG_FREEZER=y
-
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_COMPAT_BINFMT_ELF=y
-CONFIG_ARCH_BINFMT_ELF_STATE=y
-CONFIG_ARCH_HAVE_ELF_PROT=y
-CONFIG_ARCH_USE_GNU_PROPERTY=y
-CONFIG_ELFCORE=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_BINFMT_SCRIPT=y
-CONFIG_BINFMT_MISC=m
-CONFIG_COREDUMP=y
-# end of Executable file formats
-
-#
-# Memory Management options
-#
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_HAVE_FAST_GUP=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_NUMA_KEEP_MEMINFO=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_MEMORY_HOTPLUG=y
-# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set
-CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-CONFIG_MEMORY_HOTREMOVE=y
-CONFIG_MHP_MEMMAP_ON_MEMORY=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
-CONFIG_MEMORY_BALLOON=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_COMPACTION=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_MIGRATION=y
-CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
-CONFIG_ARCH_ENABLE_THP_MIGRATION=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_MMU_NOTIFIER=y
-CONFIG_KSM=y
-CONFIG_UKSM=y
-# CONFIG_KSM_LEGACY is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
-CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
-CONFIG_MEMORY_FAILURE=y
-# CONFIG_HWPOISON_INJECT is not set
-CONFIG_TRANSPARENT_HUGEPAGE=y
-CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
-# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-CONFIG_CLEANCACHE=y
-CONFIG_FRONTSWAP=y
-CONFIG_CMA=y
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_CMA_AREAS=7
-CONFIG_ZSWAP=y
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
-CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
-CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
-# CONFIG_ZSWAP_DEFAULT_ON is not set
-CONFIG_ZPOOL=y
-CONFIG_ZBUD=y
-CONFIG_Z3FOLD=m
-CONFIG_ZSMALLOC=y
-# CONFIG_ZSMALLOC_STAT is not set
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_DEFERRED_STRUCT_PAGE_INIT=y
-# CONFIG_IDLE_PAGE_TRACKING is not set
-CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
-CONFIG_ARCH_HAS_PTE_DEVMAP=y
-CONFIG_ARCH_HAS_ZONE_DMA_SET=y
-CONFIG_ZONE_DMA=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZONE_DEVICE=y
-CONFIG_DEV_PAGEMAP_OPS=y
-CONFIG_HMM_MIRROR=y
-CONFIG_DEVICE_PRIVATE=y
-CONFIG_VMAP_PFN=y
-CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
-# CONFIG_PERCPU_STATS is not set
-# CONFIG_GUP_TEST is not set
-CONFIG_READ_ONLY_THP_FOR_FS=y
-CONFIG_ARCH_HAS_PTE_SPECIAL=y
-CONFIG_MAPPING_DIRTY_HELPERS=y
-CONFIG_SECRETMEM=y
-
-#
-# Data Access Monitoring
-#
-# CONFIG_DAMON is not set
-CONFIG_DAMON_SYSFS=y
-# end of Data Access Monitoring
-# end of Memory Management options
-
-CONFIG_NET=y
-CONFIG_COMPAT_NETLINK_MESSAGES=y
-CONFIG_NET_INGRESS=y
-CONFIG_NET_EGRESS=y
-CONFIG_NET_REDIRECT=y
-CONFIG_SKB_EXTENSIONS=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=m
-CONFIG_PACKET_DIAG=m
-CONFIG_UNIX=y
-CONFIG_UNIX_SCM=y
-CONFIG_AF_UNIX_OOB=y
-CONFIG_UNIX_DIAG=m
-CONFIG_TLS=m
-CONFIG_TLS_DEVICE=y
-# CONFIG_TLS_TOE is not set
-CONFIG_XFRM=y
-CONFIG_XFRM_OFFLOAD=y
-CONFIG_XFRM_ALGO=m
-CONFIG_XFRM_USER=m
-CONFIG_XFRM_INTERFACE=m
-CONFIG_XFRM_SUB_POLICY=y
-CONFIG_XFRM_MIGRATE=y
-# CONFIG_XFRM_STATISTICS is not set
-CONFIG_XFRM_AH=m
-CONFIG_XFRM_ESP=m
-CONFIG_XFRM_IPCOMP=m
-CONFIG_NET_KEY=m
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_XFRM_ESPINTCP=y
-CONFIG_SMC=m
-CONFIG_SMC_DIAG=m
-CONFIG_XDP_SOCKETS=y
-CONFIG_XDP_SOCKETS_DIAG=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-# CONFIG_IP_FIB_TRIE_STATS is not set
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-# CONFIG_IP_ROUTE_VERBOSE is not set
-CONFIG_IP_ROUTE_CLASSID=y
-# CONFIG_IP_PNP is not set
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE_DEMUX=m
-CONFIG_NET_IP_TUNNEL=m
-CONFIG_NET_IPGRE=m
-CONFIG_NET_IPGRE_BROADCAST=y
-CONFIG_IP_MROUTE_COMMON=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_NET_IPVTI=m
-CONFIG_NET_UDP_TUNNEL=m
-CONFIG_NET_FOU=m
-CONFIG_NET_FOU_IP_TUNNELS=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_ESP_OFFLOAD=m
-CONFIG_INET_ESPINTCP=y
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_TABLE_PERTURB_ORDER=16
-CONFIG_INET_XFRM_TUNNEL=m
-CONFIG_INET_TUNNEL=m
-CONFIG_INET_DIAG=m
-CONFIG_INET_TCP_DIAG=m
-CONFIG_INET_UDP_DIAG=m
-CONFIG_INET_RAW_DIAG=m
-CONFIG_INET_DIAG_DESTROY=y
-CONFIG_TCP_CONG_ADVANCED=y
-CONFIG_TCP_CONG_BIC=m
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_TCP_CONG_WESTWOOD=m
-CONFIG_TCP_CONG_HTCP=m
-CONFIG_TCP_CONG_HSTCP=m
-CONFIG_TCP_CONG_HYBLA=m
-CONFIG_TCP_CONG_VEGAS=m
-CONFIG_TCP_CONG_NV=m
-CONFIG_TCP_CONG_SCALABLE=m
-CONFIG_TCP_CONG_LP=m
-CONFIG_TCP_CONG_VENO=m
-CONFIG_TCP_CONG_YEAH=m
-CONFIG_TCP_CONG_ILLINOIS=m
-CONFIG_TCP_CONG_DCTCP=m
-CONFIG_TCP_CONG_CDG=m
-CONFIG_TCP_CONG_BBR=m
-CONFIG_DEFAULT_CUBIC=y
-# CONFIG_DEFAULT_RENO is not set
-CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-CONFIG_IPV6=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_ESP_OFFLOAD=m
-CONFIG_INET6_ESPINTCP=y
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_IPV6_ILA=m
-CONFIG_INET6_XFRM_TUNNEL=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_IPV6_VTI=m
-CONFIG_IPV6_SIT=m
-CONFIG_IPV6_SIT_6RD=y
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_GRE=m
-CONFIG_IPV6_FOU=m
-CONFIG_IPV6_FOU_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-CONFIG_IPV6_MROUTE=y
-CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IPV6_PIMSM_V2=y
-CONFIG_IPV6_SEG6_LWTUNNEL=y
-CONFIG_IPV6_SEG6_HMAC=y
-CONFIG_IPV6_SEG6_BPF=y
-CONFIG_IPV6_RPL_LWTUNNEL=y
-# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
-CONFIG_NETLABEL=y
-CONFIG_MPTCP=y
-CONFIG_INET_MPTCP_DIAG=m
-CONFIG_MPTCP_IPV6=y
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NET_PTP_CLASSIFY=y
-# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_ADVANCED=y
-CONFIG_BRIDGE_NETFILTER=m
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_INGRESS=y
-CONFIG_NETFILTER_EGRESS=y
-CONFIG_NETFILTER_SKIP_EGRESS=y
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_FAMILY_BRIDGE=y
-CONFIG_NETFILTER_FAMILY_ARP=y
-CONFIG_NETFILTER_NETLINK_HOOK=m
-CONFIG_NETFILTER_NETLINK_ACCT=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NETFILTER_NETLINK_OSF=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_LOG_SYSLOG=m
-CONFIG_NETFILTER_CONNCOUNT=m
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_ZONES=y
-CONFIG_NF_CONNTRACK_PROCFS=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CONNTRACK_TIMEOUT=y
-CONFIG_NF_CONNTRACK_TIMESTAMP=y
-CONFIG_NF_CONNTRACK_LABELS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_GRE=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_BROADCAST=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_SNMP=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NF_CT_NETLINK_TIMEOUT=m
-CONFIG_NF_CT_NETLINK_HELPER=m
-CONFIG_NETFILTER_NETLINK_GLUE_CT=y
-CONFIG_NF_NAT=m
-CONFIG_NF_NAT_AMANDA=m
-CONFIG_NF_NAT_FTP=m
-CONFIG_NF_NAT_IRC=m
-CONFIG_NF_NAT_SIP=m
-CONFIG_NF_NAT_TFTP=m
-CONFIG_NF_NAT_REDIRECT=y
-CONFIG_NF_NAT_MASQUERADE=y
-CONFIG_NETFILTER_SYNPROXY=m
-CONFIG_NF_TABLES=m
-CONFIG_NF_TABLES_INET=y
-CONFIG_NF_TABLES_NETDEV=y
-CONFIG_NFT_NUMGEN=m
-CONFIG_NFT_CT=m
-CONFIG_NFT_FLOW_OFFLOAD=m
-CONFIG_NFT_COUNTER=m
-CONFIG_NFT_CONNLIMIT=m
-CONFIG_NFT_LOG=m
-CONFIG_NFT_LIMIT=m
-CONFIG_NFT_MASQ=m
-CONFIG_NFT_REDIR=m
-CONFIG_NFT_NAT=m
-CONFIG_NFT_TUNNEL=m
-CONFIG_NFT_OBJREF=m
-CONFIG_NFT_QUEUE=m
-CONFIG_NFT_QUOTA=m
-CONFIG_NFT_REJECT=m
-CONFIG_NFT_REJECT_INET=m
-CONFIG_NFT_COMPAT=m
-CONFIG_NFT_HASH=m
-CONFIG_NFT_FIB=m
-CONFIG_NFT_FIB_INET=m
-CONFIG_NFT_XFRM=m
-CONFIG_NFT_SOCKET=m
-CONFIG_NFT_OSF=m
-CONFIG_NFT_TPROXY=m
-CONFIG_NFT_SYNPROXY=m
-CONFIG_NF_DUP_NETDEV=m
-CONFIG_NFT_DUP_NETDEV=m
-CONFIG_NFT_FWD_NETDEV=m
-CONFIG_NFT_FIB_NETDEV=m
-CONFIG_NFT_REJECT_NETDEV=m
-CONFIG_NF_FLOW_TABLE_INET=m
-CONFIG_NF_FLOW_TABLE=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XTABLES_COMPAT=y
-
-#
-# Xtables combined modules
-#
-CONFIG_NETFILTER_XT_MARK=m
-CONFIG_NETFILTER_XT_CONNMARK=m
-CONFIG_NETFILTER_XT_SET=m
-
-#
-# Xtables targets
-#
-CONFIG_NETFILTER_XT_TARGET_AUDIT=m
-CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CT=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_HL=m
-CONFIG_NETFILTER_XT_TARGET_HMARK=m
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
-CONFIG_NETFILTER_XT_TARGET_LOG=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_NAT=m
-CONFIG_NETFILTER_XT_TARGET_NETMAP=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-CONFIG_NETFILTER_XT_TARGET_RATEEST=m
-CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
-CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
-CONFIG_NETFILTER_XT_TARGET_TEE=m
-CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-CONFIG_NETFILTER_XT_TARGET_TRACE=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-
-#
-# Xtables matches
-#
-CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
-CONFIG_NETFILTER_XT_MATCH_BPF=m
-CONFIG_NETFILTER_XT_MATCH_CGROUP=m
-CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_CPU=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ECN=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_HL=m
-CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_IPVS=m
-CONFIG_NETFILTER_XT_MATCH_L2TP=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-CONFIG_NETFILTER_XT_MATCH_OSF=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-# end of Core Netfilter Configuration
-
-CONFIG_IP_SET=m
-CONFIG_IP_SET_MAX=256
-CONFIG_IP_SET_BITMAP_IP=m
-CONFIG_IP_SET_BITMAP_IPMAC=m
-CONFIG_IP_SET_BITMAP_PORT=m
-CONFIG_IP_SET_HASH_IP=m
-CONFIG_IP_SET_HASH_IPMARK=m
-CONFIG_IP_SET_HASH_IPPORT=m
-CONFIG_IP_SET_HASH_IPPORTIP=m
-CONFIG_IP_SET_HASH_IPPORTNET=m
-CONFIG_IP_SET_HASH_IPMAC=m
-CONFIG_IP_SET_HASH_MAC=m
-CONFIG_IP_SET_HASH_NETPORTNET=m
-CONFIG_IP_SET_HASH_NET=m
-CONFIG_IP_SET_HASH_NETNET=m
-CONFIG_IP_SET_HASH_NETPORT=m
-CONFIG_IP_SET_HASH_NETIFACE=m
-CONFIG_IP_SET_LIST_SET=m
-CONFIG_IP_VS=m
-CONFIG_IP_VS_IPV6=y
-# CONFIG_IP_VS_DEBUG is not set
-CONFIG_IP_VS_TAB_BITS=12
-
-#
-# IPVS transport protocol load balancing support
-#
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_AH_ESP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_PROTO_SCTP=y
-
-#
-# IPVS scheduler
-#
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_FO=m
-CONFIG_IP_VS_OVF=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_MH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_TWOS=m
-
-#
-# IPVS SH scheduler
-#
-CONFIG_IP_VS_SH_TAB_BITS=8
-
-#
-# IPVS MH scheduler
-#
-CONFIG_IP_VS_MH_TAB_INDEX=12
-
-#
-# IPVS application helper
-#
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_VS_NFCT=y
-CONFIG_IP_VS_PE_SIP=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_DEFRAG_IPV4=m
-CONFIG_NF_SOCKET_IPV4=m
-CONFIG_NF_TPROXY_IPV4=m
-CONFIG_NF_TABLES_IPV4=y
-CONFIG_NFT_REJECT_IPV4=m
-CONFIG_NFT_DUP_IPV4=m
-CONFIG_NFT_FIB_IPV4=m
-CONFIG_NF_TABLES_ARP=y
-CONFIG_NF_FLOW_TABLE_IPV4=m
-CONFIG_NF_DUP_IPV4=m
-CONFIG_NF_LOG_ARP=m
-CONFIG_NF_LOG_IPV4=m
-CONFIG_NF_REJECT_IPV4=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_NF_NAT_PPTP=m
-CONFIG_NF_NAT_H323=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_RPFILTER=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_SYNPROXY=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_SECURITY=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-# end of IP: Netfilter Configuration
-
-#
-# IPv6: Netfilter Configuration
-#
-CONFIG_NF_SOCKET_IPV6=m
-CONFIG_NF_TPROXY_IPV6=m
-CONFIG_NF_TABLES_IPV6=y
-CONFIG_NFT_REJECT_IPV6=m
-CONFIG_NFT_DUP_IPV6=m
-CONFIG_NFT_FIB_IPV6=m
-CONFIG_NF_FLOW_TABLE_IPV6=m
-CONFIG_NF_DUP_IPV6=m
-CONFIG_NF_REJECT_IPV6=m
-CONFIG_NF_LOG_IPV6=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RPFILTER=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_MATCH_SRH=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_TARGET_SYNPROXY=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_IP6_NF_SECURITY=m
-CONFIG_IP6_NF_NAT=m
-CONFIG_IP6_NF_TARGET_MASQUERADE=m
-CONFIG_IP6_NF_TARGET_NPT=m
-# end of IPv6: Netfilter Configuration
-
-CONFIG_NF_DEFRAG_IPV6=m
-
-#
-# DECnet: Netfilter Configuration
-#
-# CONFIG_DECNET_NF_GRABULATOR is not set
-# end of DECnet: Netfilter Configuration
-
-CONFIG_NF_TABLES_BRIDGE=m
-CONFIG_NFT_BRIDGE_META=m
-CONFIG_NFT_BRIDGE_REJECT=m
-CONFIG_NF_CONNTRACK_BRIDGE=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_IP6=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_BRIDGE_EBT_NFLOG=m
-CONFIG_BPFILTER=y
-CONFIG_BPFILTER_UMH=m
-CONFIG_IP_DCCP=m
-CONFIG_INET_DCCP_DIAG=m
-
-#
-# DCCP CCIDs Configuration
-#
-# CONFIG_IP_DCCP_CCID2_DEBUG is not set
-CONFIG_IP_DCCP_CCID3=y
-# CONFIG_IP_DCCP_CCID3_DEBUG is not set
-CONFIG_IP_DCCP_TFRC_LIB=y
-# end of DCCP CCIDs Configuration
-
-#
-# DCCP Kernel Hacking
-#
-# CONFIG_IP_DCCP_DEBUG is not set
-# end of DCCP Kernel Hacking
-
-CONFIG_IP_SCTP=m
-# CONFIG_SCTP_DBG_OBJCNT is not set
-CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
-CONFIG_SCTP_COOKIE_HMAC_MD5=y
-# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set
-CONFIG_INET_SCTP_DIAG=m
-CONFIG_RDS=m
-CONFIG_RDS_RDMA=m
-CONFIG_RDS_TCP=m
-# CONFIG_RDS_DEBUG is not set
-CONFIG_TIPC=m
-# CONFIG_TIPC_MEDIA_IB is not set
-CONFIG_TIPC_MEDIA_UDP=y
-CONFIG_TIPC_CRYPTO=y
-CONFIG_TIPC_DIAG=m
-CONFIG_ATM=m
-CONFIG_ATM_CLIP=m
-# CONFIG_ATM_CLIP_NO_ICMP is not set
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-# CONFIG_ATM_BR2684_IPFILTER is not set
-CONFIG_L2TP=m
-# CONFIG_L2TP_DEBUGFS is not set
-CONFIG_L2TP_V3=y
-CONFIG_L2TP_IP=m
-CONFIG_L2TP_ETH=m
-CONFIG_STP=m
-CONFIG_GARP=m
-CONFIG_MRP=m
-CONFIG_BRIDGE=m
-CONFIG_BRIDGE_IGMP_SNOOPING=y
-CONFIG_BRIDGE_VLAN_FILTERING=y
-CONFIG_BRIDGE_MRP=y
-CONFIG_BRIDGE_CFM=y
-CONFIG_NET_DSA=m
-# CONFIG_NET_DSA_TAG_AR9331 is not set
-CONFIG_NET_DSA_TAG_BRCM_COMMON=m
-CONFIG_NET_DSA_TAG_BRCM=m
-CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
-CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
-CONFIG_NET_DSA_TAG_HELLCREEK=m
-CONFIG_NET_DSA_TAG_GSWIP=m
-CONFIG_NET_DSA_TAG_DSA_COMMON=m
-CONFIG_NET_DSA_TAG_DSA=m
-CONFIG_NET_DSA_TAG_EDSA=m
-CONFIG_NET_DSA_TAG_MTK=m
-CONFIG_NET_DSA_TAG_KSZ=m
-CONFIG_NET_DSA_TAG_OCELOT=m
-CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
-CONFIG_NET_DSA_TAG_QCA=m
-CONFIG_NET_DSA_TAG_RTL4_A=m
-CONFIG_NET_DSA_TAG_RTL8_4=m
-CONFIG_NET_DSA_TAG_LAN9303=m
-CONFIG_NET_DSA_TAG_SJA1105=m
-CONFIG_NET_DSA_TAG_TRAILER=m
-CONFIG_NET_DSA_TAG_XRS700X=m
-CONFIG_NET_DSA_REALTEK=m
-CONFIG_NET_DSA_REALTEK_MDIO=m
-CONFIG_NET_DSA_REALTEK_RTL8365MB=m
-CONFIG_NET_DSA_REALTEK_RTL8366RB=m
-CONFIG_VLAN_8021Q=m
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_VLAN_8021Q_MVRP=y
-CONFIG_DECNET=m
-# CONFIG_DECNET_ROUTER is not set
-CONFIG_LLC=m
-CONFIG_LLC2=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_PHONET=m
-CONFIG_6LOWPAN=m
-# CONFIG_6LOWPAN_DEBUGFS is not set
-CONFIG_6LOWPAN_NHC=m
-CONFIG_6LOWPAN_NHC_DEST=m
-CONFIG_6LOWPAN_NHC_FRAGMENT=m
-CONFIG_6LOWPAN_NHC_HOP=m
-CONFIG_6LOWPAN_NHC_IPV6=m
-CONFIG_6LOWPAN_NHC_MOBILITY=m
-CONFIG_6LOWPAN_NHC_ROUTING=m
-CONFIG_6LOWPAN_NHC_UDP=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
-CONFIG_6LOWPAN_GHC_UDP=m
-CONFIG_6LOWPAN_GHC_ICMPV6=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
-CONFIG_IEEE802154=m
-CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
-CONFIG_IEEE802154_SOCKET=m
-CONFIG_IEEE802154_6LOWPAN=m
-CONFIG_MAC802154=m
-CONFIG_NET_SCHED=y
-
-#
-# Queueing/Scheduling
-#
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_MULTIQ=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFB=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_CBS=m
-CONFIG_NET_SCH_ETF=m
-CONFIG_NET_SCH_TAPRIO=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_DRR=m
-CONFIG_NET_SCH_MQPRIO=m
-CONFIG_NET_SCH_SKBPRIO=m
-CONFIG_NET_SCH_CHOKE=m
-CONFIG_NET_SCH_QFQ=m
-CONFIG_NET_SCH_CODEL=m
-CONFIG_NET_SCH_FQ_CODEL=m
-CONFIG_NET_SCH_CAKE=m
-CONFIG_NET_SCH_FQ=m
-CONFIG_NET_SCH_HHF=m
-CONFIG_NET_SCH_PIE=m
-CONFIG_NET_SCH_FQ_PIE=m
-CONFIG_NET_SCH_INGRESS=m
-CONFIG_NET_SCH_PLUG=m
-CONFIG_NET_SCH_ETS=m
-# CONFIG_NET_SCH_DEFAULT is not set
-
-#
-# Classification
-#
-CONFIG_NET_CLS=y
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_CLS_U32_PERF=y
-CONFIG_CLS_U32_MARK=y
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_CLS_FLOW=m
-CONFIG_NET_CLS_CGROUP=m
-CONFIG_NET_CLS_BPF=m
-CONFIG_NET_CLS_FLOWER=m
-CONFIG_NET_CLS_MATCHALL=m
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_STACK=32
-CONFIG_NET_EMATCH_CMP=m
-CONFIG_NET_EMATCH_NBYTE=m
-CONFIG_NET_EMATCH_U32=m
-CONFIG_NET_EMATCH_META=m
-CONFIG_NET_EMATCH_TEXT=m
-CONFIG_NET_EMATCH_CANID=m
-CONFIG_NET_EMATCH_IPSET=m
-CONFIG_NET_EMATCH_IPT=m
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=m
-CONFIG_NET_ACT_GACT=m
-CONFIG_GACT_PROB=y
-CONFIG_NET_ACT_MIRRED=m
-CONFIG_NET_ACT_SAMPLE=m
-CONFIG_NET_ACT_IPT=m
-CONFIG_NET_ACT_NAT=m
-CONFIG_NET_ACT_PEDIT=m
-CONFIG_NET_ACT_SIMP=m
-CONFIG_NET_ACT_SKBEDIT=m
-CONFIG_NET_ACT_CSUM=m
-CONFIG_NET_ACT_MPLS=m
-CONFIG_NET_ACT_VLAN=m
-CONFIG_NET_ACT_BPF=m
-CONFIG_NET_ACT_CONNMARK=m
-CONFIG_NET_ACT_CTINFO=m
-CONFIG_NET_ACT_SKBMOD=m
-CONFIG_NET_ACT_IFE=m
-CONFIG_NET_ACT_TUNNEL_KEY=m
-CONFIG_NET_ACT_CT=m
-CONFIG_NET_ACT_GATE=m
-CONFIG_NET_IFE_SKBMARK=m
-CONFIG_NET_IFE_SKBPRIO=m
-CONFIG_NET_IFE_SKBTCINDEX=m
-CONFIG_NET_TC_SKB_EXT=y
-CONFIG_NET_SCH_FIFO=y
-CONFIG_DCB=y
-CONFIG_DNS_RESOLVER=m
-CONFIG_BATMAN_ADV=m
-CONFIG_BATMAN_ADV_BATMAN_V=y
-CONFIG_BATMAN_ADV_BLA=y
-CONFIG_BATMAN_ADV_DAT=y
-CONFIG_BATMAN_ADV_NC=y
-CONFIG_BATMAN_ADV_MCAST=y
-# CONFIG_BATMAN_ADV_DEBUG is not set
-# CONFIG_BATMAN_ADV_TRACING is not set
-CONFIG_OPENVSWITCH=m
-CONFIG_OPENVSWITCH_GRE=m
-CONFIG_OPENVSWITCH_VXLAN=m
-CONFIG_OPENVSWITCH_GENEVE=m
-CONFIG_VSOCKETS=m
-CONFIG_VSOCKETS_DIAG=m
-CONFIG_VSOCKETS_LOOPBACK=m
-CONFIG_VMWARE_VMCI_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS_COMMON=m
-CONFIG_HYPERV_VSOCKETS=m
-CONFIG_NETLINK_DIAG=m
-CONFIG_MPLS=y
-CONFIG_NET_MPLS_GSO=m
-CONFIG_MPLS_ROUTING=m
-CONFIG_MPLS_IPTUNNEL=m
-CONFIG_NET_NSH=m
-CONFIG_HSR=m
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_L3_MASTER_DEV=y
-CONFIG_QRTR=m
-CONFIG_QRTR_SMD=m
-CONFIG_QRTR_TUN=m
-CONFIG_QRTR_MHI=m
-CONFIG_NET_NCSI=y
-CONFIG_NCSI_OEM_CMD_GET_MAC=y
-CONFIG_NCSI_OEM_CMD_KEEP_PHY=y
-CONFIG_PCPU_DEV_REFCNT=y
-CONFIG_RPS=y
-CONFIG_RFS_ACCEL=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_XPS=y
-CONFIG_CGROUP_NET_PRIO=y
-CONFIG_CGROUP_NET_CLASSID=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_BQL=y
-CONFIG_BPF_STREAM_PARSER=y
-CONFIG_NET_FLOW_LIMIT=y
-
-#
-# Network testing
-#
-CONFIG_NET_PKTGEN=m
-CONFIG_NET_DROP_MONITOR=y
-# end of Network testing
-# end of Networking options
-
-CONFIG_HAMRADIO=y
-
-#
-# Packet Radio protocols
-#
-CONFIG_AX25=m
-CONFIG_AX25_DAMA_SLAVE=y
-CONFIG_NETROM=m
-CONFIG_ROSE=m
-
-#
-# AX.25 network device drivers
-#
-CONFIG_MKISS=m
-CONFIG_6PACK=m
-CONFIG_BPQETHER=m
-CONFIG_BAYCOM_SER_FDX=m
-CONFIG_BAYCOM_SER_HDX=m
-CONFIG_BAYCOM_PAR=m
-CONFIG_YAM=m
-# end of AX.25 network device drivers
-
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_GW=m
-CONFIG_CAN_J1939=m
-CONFIG_CAN_ISOTP=m
-
-#
-# CAN Device Drivers
-#
-CONFIG_CAN_VCAN=m
-CONFIG_CAN_VXCAN=m
-CONFIG_CAN_SLCAN=m
-CONFIG_CAN_DEV=m
-CONFIG_CAN_CALC_BITTIMING=y
-CONFIG_CAN_FLEXCAN=m
-# CONFIG_CAN_GRCAN is not set
-CONFIG_CAN_KVASER_PCIEFD=m
-CONFIG_CAN_XILINXCAN=m
-CONFIG_CAN_C_CAN=m
-# CONFIG_CAN_C_CAN_PLATFORM is not set
-CONFIG_CAN_C_CAN_PCI=m
-# CONFIG_CAN_CC770 is not set
-CONFIG_CAN_IFI_CANFD=m
-CONFIG_CAN_M_CAN=m
-CONFIG_CAN_M_CAN_PCI=m
-CONFIG_CAN_M_CAN_PLATFORM=m
-CONFIG_CAN_M_CAN_TCAN4X5X=m
-CONFIG_CAN_PEAK_PCIEFD=m
-CONFIG_CAN_RCAR=m
-CONFIG_CAN_RCAR_CANFD=m
-CONFIG_CAN_SJA1000=m
-CONFIG_CAN_EMS_PCI=m
-CONFIG_CAN_F81601=m
-CONFIG_CAN_KVASER_PCI=m
-CONFIG_CAN_PEAK_PCI=m
-CONFIG_CAN_PEAK_PCIEC=y
-CONFIG_CAN_PLX_PCI=m
-# CONFIG_CAN_SJA1000_ISA is not set
-# CONFIG_CAN_SJA1000_PLATFORM is not set
-CONFIG_CAN_SOFTING=m
-
-#
-# CAN SPI interfaces
-#
-CONFIG_CAN_HI311X=m
-# CONFIG_CAN_MCP251X is not set
-CONFIG_CAN_MCP251XFD=m
-# CONFIG_CAN_MCP251XFD_SANITY is not set
-# end of CAN SPI interfaces
-
-#
-# CAN USB interfaces
-#
-CONFIG_CAN_8DEV_USB=m
-CONFIG_CAN_EMS_USB=m
-CONFIG_CAN_ESD_USB2=m
-CONFIG_CAN_ETAS_ES58X=m
-CONFIG_CAN_GS_USB=m
-CONFIG_CAN_KVASER_USB=m
-CONFIG_CAN_MCBA_USB=m
-CONFIG_CAN_PEAK_USB=m
-CONFIG_CAN_UCAN=m
-# end of CAN USB interfaces
-
-# CONFIG_CAN_DEBUG_DEVICES is not set
-# end of CAN Device Drivers
-
-CONFIG_BT=m
-CONFIG_BT_BREDR=y
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_CMTP=m
-CONFIG_BT_HIDP=m
-CONFIG_BT_HS=y
-CONFIG_BT_LE=y
-CONFIG_BT_6LOWPAN=m
-CONFIG_BT_LEDS=y
-CONFIG_BT_MSFTEXT=y
-CONFIG_BT_AOSPEXT=y
-# CONFIG_BT_DEBUGFS is not set
-# CONFIG_BT_SELFTEST is not set
-# CONFIG_BT_FEATURE_DEBUG is not set
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_INTEL=m
-CONFIG_BT_BCM=m
-CONFIG_BT_RTL=m
-CONFIG_BT_QCA=m
-CONFIG_BT_HCIBTUSB=m
-CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
-CONFIG_BT_HCIBTUSB_BCM=y
-CONFIG_BT_HCIBTUSB_MTK=y
-CONFIG_BT_HCIBTUSB_RTL=y
-CONFIG_BT_HCIBTSDIO=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_SERDEV=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_NOKIA=m
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_ATH3K=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIUART_3WIRE=y
-CONFIG_BT_HCIUART_INTEL=y
-CONFIG_BT_HCIUART_BCM=y
-CONFIG_BT_HCIUART_RTL=y
-CONFIG_BT_HCIUART_QCA=y
-CONFIG_BT_HCIUART_AG6XX=y
-CONFIG_BT_HCIUART_MRVL=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_BT_MRVL=m
-CONFIG_BT_MRVL_SDIO=m
-CONFIG_BT_ATH3K=m
-CONFIG_BT_MTKSDIO=m
-CONFIG_BT_MTKUART=m
-CONFIG_BT_QCOMSMD=m
-CONFIG_BT_HCIRSI=m
-CONFIG_BT_VIRTIO=m
-# end of Bluetooth device drivers
-
-CONFIG_AF_RXRPC=m
-CONFIG_AF_RXRPC_IPV6=y
-# CONFIG_AF_RXRPC_INJECT_LOSS is not set
-# CONFIG_AF_RXRPC_DEBUG is not set
-CONFIG_RXKAD=y
-CONFIG_AF_KCM=m
-CONFIG_STREAM_PARSER=y
-# CONFIG_MCTP is not set
-CONFIG_FIB_RULES=y
-CONFIG_WIRELESS=y
-CONFIG_WIRELESS_EXT=y
-# CONFIG_WEXT_CORE is not set
-# CONFIG_WEXT_PROC is not set
-# CONFIG_WEXT_SPY is not set
-# CONFIG_WEXT_PRIV is not set
-CONFIG_CFG80211=m
-# CONFIG_NL80211_TESTMODE is not set
-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
-CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
-CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
-CONFIG_CFG80211_DEFAULT_PS=y
-# CONFIG_CFG80211_DEBUGFS is not set
-CONFIG_CFG80211_CRDA_SUPPORT=y
-# CONFIG_CFG80211_WEXT is not set
-# CONFIG_CFG80211_WEXT_EXPORT is not set
-CONFIG_LIB80211=m
-CONFIG_LIB80211_CRYPT_WEP=m
-CONFIG_LIB80211_CRYPT_CCMP=m
-CONFIG_LIB80211_CRYPT_TKIP=m
-# CONFIG_LIB80211_DEBUG is not set
-CONFIG_MAC80211=m
-CONFIG_MAC80211_HAS_RC=y
-CONFIG_MAC80211_RC_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
-CONFIG_MAC80211_MESH=y
-CONFIG_MAC80211_LEDS=y
-# CONFIG_MAC80211_DEBUGFS is not set
-# CONFIG_MAC80211_MESSAGE_TRACING is not set
-# CONFIG_MAC80211_DEBUG_MENU is not set
-CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
-CONFIG_RFKILL=m
-CONFIG_RFKILL_LEDS=y
-CONFIG_RFKILL_INPUT=y
-CONFIG_RFKILL_GPIO=m
-CONFIG_NET_9P=m
-CONFIG_NET_9P_VIRTIO=m
-CONFIG_NET_9P_RDMA=m
-# CONFIG_NET_9P_DEBUG is not set
-CONFIG_CAIF=m
-# CONFIG_CAIF_DEBUG is not set
-CONFIG_CAIF_NETDEV=m
-CONFIG_CAIF_USB=m
-CONFIG_CEPH_LIB=m
-# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
-# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
-CONFIG_NFC=m
-CONFIG_NFC_DIGITAL=m
-CONFIG_NFC_NCI=m
-# CONFIG_NFC_NCI_SPI is not set
-CONFIG_NFC_NCI_UART=m
-CONFIG_NFC_HCI=m
-CONFIG_NFC_SHDLC=y
-
-#
-# Near Field Communication (NFC) devices
-#
-# CONFIG_NFC_TRF7970A is not set
-CONFIG_NFC_SIM=m
-CONFIG_NFC_PORT100=m
-CONFIG_NFC_VIRTUAL_NCI=m
-# CONFIG_NFC_FDP is not set
-CONFIG_NFC_PN544=m
-CONFIG_NFC_PN544_I2C=m
-CONFIG_NFC_PN533=m
-CONFIG_NFC_PN533_USB=m
-CONFIG_NFC_PN533_I2C=m
-CONFIG_NFC_PN532_UART=m
-CONFIG_NFC_MICROREAD=m
-CONFIG_NFC_MICROREAD_I2C=m
-CONFIG_NFC_MRVL=m
-CONFIG_NFC_MRVL_USB=m
-CONFIG_NFC_MRVL_UART=m
-CONFIG_NFC_MRVL_I2C=m
-CONFIG_NFC_ST21NFCA=m
-CONFIG_NFC_ST21NFCA_I2C=m
-CONFIG_NFC_ST_NCI=m
-CONFIG_NFC_ST_NCI_I2C=m
-CONFIG_NFC_ST_NCI_SPI=m
-CONFIG_NFC_NXP_NCI=m
-CONFIG_NFC_NXP_NCI_I2C=m
-CONFIG_NFC_S3FWRN5=m
-CONFIG_NFC_S3FWRN5_I2C=m
-CONFIG_NFC_S3FWRN82_UART=m
-CONFIG_NFC_ST95HF=m
-# end of Near Field Communication (NFC) devices
-
-CONFIG_PSAMPLE=m
-CONFIG_NET_IFE=m
-CONFIG_LWTUNNEL=y
-CONFIG_LWTUNNEL_BPF=y
-# CONFIG_PAGE_POOL_STATS is not set
-CONFIG_DST_CACHE=y
-CONFIG_GRO_CELLS=y
-CONFIG_SOCK_VALIDATE_XMIT=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SOCK_MSG=y
-CONFIG_NET_DEVLINK=y
-CONFIG_PAGE_POOL=y
-CONFIG_FAILOVER=m
-CONFIG_ETHTOOL_NETLINK=y
-
-#
-# Device Drivers
-#
-CONFIG_ARM_AMBA=y
-CONFIG_TEGRA_AHB=y
-CONFIG_HAVE_PCI=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_SYSCALL=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_HOTPLUG_PCI_PCIE=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEAER_INJECT=m
-# CONFIG_PCIE_ECRC is not set
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-CONFIG_PCIE_PME=y
-CONFIG_PCIE_DPC=y
-CONFIG_PCIE_PTM=y
-CONFIG_PCIE_EDR=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_QUIRKS=y
-# CONFIG_PCI_DEBUG is not set
-# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
-CONFIG_PCI_STUB=y
-CONFIG_PCI_PF_STUB=m
-CONFIG_PCI_ATS=y
-CONFIG_PCI_ECAM=y
-CONFIG_PCI_BRIDGE_EMUL=y
-CONFIG_PCI_IOV=y
-CONFIG_PCI_PRI=y
-CONFIG_PCI_PASID=y
-CONFIG_PCI_P2PDMA=y
-CONFIG_PCI_HYPERV=m
-CONFIG_PCI_LABEL=y
-# CONFIG_PCIE_BUS_TUNE_OFF is not set
-CONFIG_PCIE_BUS_DEFAULT=y
-# CONFIG_PCIE_BUS_SAFE is not set
-# CONFIG_PCIE_BUS_PERFORMANCE is not set
-# CONFIG_PCIE_BUS_PEER2PEER is not set
-CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_ACPI=y
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-CONFIG_HOTPLUG_PCI_CPCI=y
-CONFIG_HOTPLUG_PCI_SHPC=y
-
-#
-# PCI controller drivers
-#
-CONFIG_PCI_AARDVARK=y
-CONFIG_PCIE_XILINX_NWL=y
-CONFIG_PCI_FTPCI100=y
-CONFIG_PCI_TEGRA=y
-CONFIG_PCIE_RCAR_HOST=y
-CONFIG_PCIE_RCAR_EP=y
-CONFIG_PCI_HOST_COMMON=y
-CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCIE_XILINX=y
-CONFIG_PCIE_XILINX_CPM=y
-CONFIG_PCI_XGENE=y
-CONFIG_PCI_XGENE_MSI=y
-CONFIG_PCIE_IPROC=m
-CONFIG_PCIE_IPROC_PLATFORM=m
-CONFIG_PCIE_IPROC_MSI=y
-CONFIG_PCIE_ALTERA=y
-CONFIG_PCIE_ALTERA_MSI=y
-CONFIG_PCI_HOST_THUNDER_PEM=y
-CONFIG_PCI_HOST_THUNDER_ECAM=y
-CONFIG_PCIE_ROCKCHIP=y
-CONFIG_PCIE_ROCKCHIP_HOST=m
-CONFIG_PCIE_ROCKCHIP_EP=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_MEDIATEK_GEN3=m
-CONFIG_PCIE_BRCMSTB=m
-CONFIG_PCIE_MICROCHIP_HOST=y
-CONFIG_PCIE_HISI_ERR=y
-# CONFIG_PCIE_APPLE is not set
-
-#
-# DesignWare PCI Core Support
-#
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_DW_EP=y
-CONFIG_PCIE_DW_PLAT=y
-CONFIG_PCIE_DW_PLAT_HOST=y
-CONFIG_PCIE_DW_PLAT_EP=y
-CONFIG_PCI_EXYNOS=m
-CONFIG_PCI_IMX6=y
-CONFIG_PCI_KEYSTONE=y
-CONFIG_PCI_KEYSTONE_HOST=y
-CONFIG_PCI_KEYSTONE_EP=y
-CONFIG_PCI_LAYERSCAPE=y
-CONFIG_PCI_LAYERSCAPE_EP=y
-CONFIG_PCI_HISI=y
-CONFIG_PCIE_QCOM=y
-# CONFIG_PCIE_QCOM_EP is not set
-CONFIG_PCIE_ARMADA_8K=y
-CONFIG_PCIE_ROCKCHIP_DW_HOST=y
-CONFIG_PCIE_KEEMBAY=y
-CONFIG_PCIE_KEEMBAY_HOST=y
-CONFIG_PCIE_KEEMBAY_EP=y
-CONFIG_PCIE_KIRIN=y
-CONFIG_PCIE_HISI_STB=y
-CONFIG_PCI_MESON=y
-CONFIG_PCIE_TEGRA194=m
-CONFIG_PCIE_TEGRA194_HOST=m
-CONFIG_PCIE_TEGRA194_EP=m
-CONFIG_PCIE_VISCONTI_HOST=y
-CONFIG_PCIE_UNIPHIER=y
-CONFIG_PCIE_UNIPHIER_EP=y
-CONFIG_PCIE_AL=y
-# end of DesignWare PCI Core Support
-
-#
-# Mobiveil PCIe Core Support
-#
-CONFIG_PCIE_MOBIVEIL=y
-CONFIG_PCIE_MOBIVEIL_HOST=y
-CONFIG_PCIE_MOBIVEIL_PLAT=y
-CONFIG_PCIE_LAYERSCAPE_GEN4=y
-# end of Mobiveil PCIe Core Support
-
-#
-# Cadence PCIe controllers support
-#
-CONFIG_PCIE_CADENCE=y
-CONFIG_PCIE_CADENCE_HOST=y
-CONFIG_PCIE_CADENCE_EP=y
-CONFIG_PCIE_CADENCE_PLAT=y
-CONFIG_PCIE_CADENCE_PLAT_HOST=y
-CONFIG_PCIE_CADENCE_PLAT_EP=y
-CONFIG_PCI_J721E=y
-CONFIG_PCI_J721E_HOST=y
-CONFIG_PCI_J721E_EP=y
-# end of Cadence PCIe controllers support
-# end of PCI controller drivers
-
-#
-# PCI Endpoint
-#
-CONFIG_PCI_ENDPOINT=y
-CONFIG_PCI_ENDPOINT_CONFIGFS=y
-CONFIG_PCI_EPF_TEST=m
-CONFIG_PCI_EPF_NTB=m
-# end of PCI Endpoint
-
-#
-# PCI switch controller drivers
-#
-CONFIG_PCI_SW_SWITCHTEC=m
-# end of PCI switch controller drivers
-
-CONFIG_CXL_BUS=m
-CONFIG_CXL_PCI=m
-CONFIG_CXL_MEM=m
-# CONFIG_CXL_MEM_RAW_COMMANDS is not set
-CONFIG_CXL_ACPI=m
-CONFIG_CXL_PMEM=m
-# CONFIG_PCCARD is not set
-CONFIG_RAPIDIO=m
-CONFIG_RAPIDIO_TSI721=m
-CONFIG_RAPIDIO_DISC_TIMEOUT=30
-# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set
-CONFIG_RAPIDIO_DMA_ENGINE=y
-# CONFIG_RAPIDIO_DEBUG is not set
-CONFIG_RAPIDIO_ENUM_BASIC=m
-CONFIG_RAPIDIO_CHMAN=m
-CONFIG_RAPIDIO_MPORT_CDEV=m
-
-#
-# RapidIO Switch drivers
-#
-CONFIG_RAPIDIO_TSI57X=m
-CONFIG_RAPIDIO_CPS_XX=m
-CONFIG_RAPIDIO_TSI568=m
-CONFIG_RAPIDIO_CPS_GEN2=m
-CONFIG_RAPIDIO_RXS_GEN3=m
-# end of RapidIO Switch drivers
-
-#
-# Generic Driver Options
-#
-CONFIG_AUXILIARY_BUS=y
-# CONFIG_UEVENT_HELPER is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_STANDALONE is not set
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-
-#
-# Firmware loader
-#
-CONFIG_FW_LOADER=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_FW_LOADER_USER_HELPER is not set
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_FW_LOADER_COMPRESS=y
-CONFIG_FW_CACHE=y
-# end of Firmware loader
-
-CONFIG_WANT_DEV_COREDUMP=y
-CONFIG_ALLOW_DEV_COREDUMP=y
-CONFIG_DEV_COREDUMP=y
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
-CONFIG_HMEM_REPORTING=y
-# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_SOC_BUS=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_SLIMBUS=m
-CONFIG_REGMAP_SPI=y
-CONFIG_REGMAP_SPMI=m
-CONFIG_REGMAP_W1=m
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_SOUNDWIRE=m
-CONFIG_REGMAP_SOUNDWIRE_MBQ=m
-CONFIG_REGMAP_SCCB=m
-CONFIG_REGMAP_I3C=m
-CONFIG_DMA_SHARED_BUFFER=y
-# CONFIG_DMA_FENCE_TRACE is not set
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_ARCH_NUMA=y
-# end of Generic Driver Options
-
-#
-# Bus devices
-#
-CONFIG_ARM_CCI=y
-CONFIG_ARM_CCI400_COMMON=y
-CONFIG_BRCMSTB_GISB_ARB=y
-CONFIG_MOXTET=m
-CONFIG_HISILICON_LPC=y
-CONFIG_IMX_WEIM=y
-CONFIG_QCOM_EBI2=y
-CONFIG_SUN50I_DE2_BUS=y
-CONFIG_SUNXI_RSB=m
-CONFIG_TEGRA_ACONNECT=y
-CONFIG_TEGRA_GMI=m
-CONFIG_UNIPHIER_SYSTEM_BUS=m
-CONFIG_VEXPRESS_CONFIG=y
-CONFIG_FSL_MC_BUS=y
-CONFIG_FSL_MC_UAPI_SUPPORT=y
-CONFIG_MHI_BUS=m
-# CONFIG_MHI_BUS_DEBUG is not set
-CONFIG_MHI_BUS_PCI_GENERIC=m
-# end of Bus devices
-
-CONFIG_CONNECTOR=y
-CONFIG_PROC_EVENTS=y
-
-#
-# Firmware Drivers
-#
-
-#
-# ARM System Control and Management Interface Protocol
-#
-CONFIG_ARM_SCMI_PROTOCOL=y
-CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
-CONFIG_ARM_SCMI_HAVE_SHMEM=y
-CONFIG_ARM_SCMI_HAVE_MSG=y
-CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
-CONFIG_ARM_SCMI_TRANSPORT_SMC=y
-# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
-CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y
-CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y
-# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE is not set
-CONFIG_ARM_SCMI_POWER_DOMAIN=m
-# end of ARM System Control and Management Interface Protocol
-
-CONFIG_ARM_SCPI_PROTOCOL=m
-CONFIG_ARM_SCPI_POWER_DOMAIN=m
-CONFIG_ARM_SDE_INTERFACE=y
-CONFIG_FIRMWARE_MEMMAP=y
-CONFIG_DMIID=y
-CONFIG_DMI_SYSFS=m
-CONFIG_ISCSI_IBFT=m
-CONFIG_RASPBERRYPI_FIRMWARE=y
-CONFIG_FW_CFG_SYSFS=m
-CONFIG_FW_CFG_SYSFS_CMDLINE=y
-CONFIG_INTEL_STRATIX10_SERVICE=m
-CONFIG_INTEL_STRATIX10_RSU=m
-CONFIG_QCOM_SCM=y
-# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-CONFIG_SYSFB=y
-CONFIG_SYSFB_SIMPLEFB=y
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_TURRIS_MOX_RWTM=m
-CONFIG_ARM_FFA_TRANSPORT=m
-CONFIG_ARM_FFA_SMCCC=y
-CONFIG_TEE_BNXT_FW=m
-# CONFIG_GOOGLE_FIRMWARE is not set
-
-#
-# EFI (Extensible Firmware Interface) Support
-#
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_VARS_PSTORE=m
-CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
-CONFIG_EFI_SOFT_RESERVE=y
-CONFIG_EFI_ZBOOT=y
-# CONFIG_EFI_ZBOOT_SIGNING is not set
-CONFIG_EFI_PARAMS_FROM_FDT=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_GENERIC_STUB=y
-CONFIG_EFI_ARMSTUB_DTB_LOADER=y
-CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
-CONFIG_EFI_BOOTLOADER_CONTROL=m
-CONFIG_EFI_CAPSULE_LOADER=m
-# CONFIG_EFI_TEST is not set
-# CONFIG_RESET_ATTACK_MITIGATION is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# end of EFI (Extensible Firmware Interface) Support
-
-CONFIG_UEFI_CPER=y
-CONFIG_UEFI_CPER_ARM=y
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-CONFIG_IMX_DSP=m
-CONFIG_IMX_SCU=y
-CONFIG_IMX_SCU_PD=y
-CONFIG_MESON_SM=y
-CONFIG_ARM_PSCI_FW=y
-# CONFIG_ARM_PSCI_CHECKER is not set
-CONFIG_HAVE_ARM_SMCCC=y
-CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
-CONFIG_ARM_SMCCC_SOC_ID=y
-
-#
-# Tegra firmware driver
-#
-CONFIG_TEGRA_IVC=y
-CONFIG_TEGRA_BPMP=y
-# end of Tegra firmware driver
-
-#
-# Zynq MPSoC Firmware Drivers
-#
-CONFIG_ZYNQMP_FIRMWARE=y
-# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
-# end of Zynq MPSoC Firmware Drivers
-# end of Firmware Drivers
-
-CONFIG_GNSS=m
-CONFIG_GNSS_SERIAL=m
-CONFIG_GNSS_MTK_SERIAL=m
-CONFIG_GNSS_SIRF_SERIAL=m
-CONFIG_GNSS_UBX_SERIAL=m
-CONFIG_MTD=m
-CONFIG_MTD_TESTS=m
-
-#
-# Partition parsers
-#
-CONFIG_MTD_AR7_PARTS=m
-CONFIG_MTD_CMDLINE_PARTS=m
-CONFIG_MTD_OF_PARTS=m
-CONFIG_MTD_OF_PARTS_BCM4908=y
-CONFIG_MTD_OF_PARTS_LINKSYS_NS=y
-CONFIG_MTD_AFS_PARTS=m
-CONFIG_MTD_PARSER_TRX=m
-CONFIG_MTD_REDBOOT_PARTS=m
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
-# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
-CONFIG_MTD_QCOMSMEM_PARTS=m
-# end of Partition parsers
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
-CONFIG_MTD_BLOCK_RO=m
-
-#
-# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
-#
-CONFIG_FTL=m
-CONFIG_NFTL=m
-CONFIG_NFTL_RW=y
-CONFIG_INFTL=m
-CONFIG_RFD_FTL=m
-CONFIG_SSFDC=m
-# CONFIG_SM_FTL is not set
-CONFIG_MTD_OOPS=m
-CONFIG_MTD_SWAP=m
-CONFIG_MTD_PARTITIONED_MASTER=y
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_GEN_PROBE=m
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-CONFIG_MTD_MAP_BANK_WIDTH_8=y
-CONFIG_MTD_MAP_BANK_WIDTH_16=y
-CONFIG_MTD_MAP_BANK_WIDTH_32=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-CONFIG_MTD_OTP=y
-CONFIG_MTD_CFI_INTELEXT=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_CFI_STAA=m
-CONFIG_MTD_CFI_UTIL=m
-CONFIG_MTD_RAM=m
-CONFIG_MTD_ROM=m
-CONFIG_MTD_ABSENT=m
-# end of RAM/ROM/Flash chip drivers
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=m
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-CONFIG_MTD_PHYSMAP_OF=y
-# CONFIG_MTD_PHYSMAP_VERSATILE is not set
-# CONFIG_MTD_PHYSMAP_GEMINI is not set
-CONFIG_MTD_PHYSMAP_GPIO_ADDR=y
-CONFIG_MTD_PCI=m
-CONFIG_MTD_INTEL_VR_NOR=m
-CONFIG_MTD_PLATRAM=m
-# end of Mapping drivers for chip access
-
-#
-# Self-contained MTD device drivers
-#
-CONFIG_MTD_PMC551=m
-CONFIG_MTD_PMC551_BUGFIX=y
-# CONFIG_MTD_PMC551_DEBUG is not set
-# CONFIG_MTD_DATAFLASH is not set
-CONFIG_MTD_MCHP23K256=m
-CONFIG_MTD_MCHP48L640=m
-# CONFIG_MTD_SST25L is not set
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTDRAM_TOTAL_SIZE=4096
-CONFIG_MTDRAM_ERASE_SIZE=128
-CONFIG_MTD_BLOCK2MTD=m
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOCG3 is not set
-# end of Self-contained MTD device drivers
-
-#
-# NAND
-#
-CONFIG_MTD_NAND_CORE=m
-CONFIG_MTD_ONENAND=m
-CONFIG_MTD_ONENAND_VERIFY_WRITE=y
-CONFIG_MTD_ONENAND_GENERIC=m
-CONFIG_MTD_ONENAND_OTP=y
-CONFIG_MTD_ONENAND_2X_PROGRAM=y
-CONFIG_MTD_RAW_NAND=m
-
-#
-# Raw/parallel NAND flash controllers
-#
-CONFIG_MTD_NAND_DENALI=m
-# CONFIG_MTD_NAND_DENALI_PCI is not set
-CONFIG_MTD_NAND_DENALI_DT=m
-CONFIG_MTD_NAND_OMAP2=m
-CONFIG_MTD_NAND_OMAP_BCH=y
-CONFIG_MTD_NAND_CAFE=m
-CONFIG_MTD_NAND_MARVELL=m
-CONFIG_MTD_NAND_BRCMNAND=m
-CONFIG_MTD_NAND_BRCMNAND_BCM63XX=m
-CONFIG_MTD_NAND_BRCMNAND_BCMBCA=m
-CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=m
-CONFIG_MTD_NAND_BRCMNAND_IPROC=m
-CONFIG_MTD_NAND_GPMI_NAND=m
-CONFIG_MTD_NAND_FSL_IFC=m
-CONFIG_MTD_NAND_MXC=m
-CONFIG_MTD_NAND_SUNXI=m
-CONFIG_MTD_NAND_HISI504=m
-CONFIG_MTD_NAND_QCOM=m
-CONFIG_MTD_NAND_MTK=m
-CONFIG_MTD_NAND_MXIC=m
-CONFIG_MTD_NAND_TEGRA=m
-CONFIG_MTD_NAND_MESON=m
-CONFIG_MTD_NAND_GPIO=m
-CONFIG_MTD_NAND_PLATFORM=m
-CONFIG_MTD_NAND_CADENCE=m
-CONFIG_MTD_NAND_ARASAN=m
-# CONFIG_MTD_NAND_INTEL_LGM is not set
-CONFIG_MTD_NAND_ROCKCHIP=m
-
-#
-# Misc
-#
-CONFIG_MTD_SM_COMMON=m
-CONFIG_MTD_NAND_NANDSIM=m
-CONFIG_MTD_NAND_RICOH=m
-CONFIG_MTD_NAND_DISKONCHIP=m
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
-CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
-CONFIG_MTD_SPI_NAND=m
-
-#
-# ECC engine support
-#
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
-CONFIG_MTD_NAND_ECC_SW_BCH=y
-CONFIG_MTD_NAND_ECC_MXIC=y
-# end of ECC engine support
-# end of NAND
-
-#
-# LPDDR & LPDDR2 PCM memory drivers
-#
-CONFIG_MTD_LPDDR=m
-CONFIG_MTD_QINFO_PROBE=m
-# end of LPDDR & LPDDR2 PCM memory drivers
-
-CONFIG_MTD_SPI_NOR=m
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
-CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
-# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
-CONFIG_SPI_HISI_SFC=m
-CONFIG_MTD_UBI=m
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_FASTMAP is not set
-CONFIG_MTD_UBI_GLUEBI=m
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_HYPERBUS=m
-CONFIG_HBMC_AM654=m
-CONFIG_DTC=y
-CONFIG_OF=y
-# CONFIG_OF_UNITTEST is not set
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OF_RESOLVE=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_NUMA=y
-CONFIG_PARPORT=m
-CONFIG_PARPORT_PC=m
-CONFIG_PARPORT_PC_FIFO=y
-CONFIG_PARPORT_SERIAL=m
-CONFIG_PARPORT_AX88796=m
-CONFIG_PARPORT_1284=y
-CONFIG_PARPORT_NOT_PC=y
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG_MESSAGES is not set
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-CONFIG_BLK_DEV=y
-CONFIG_BLK_DEV_NULL_BLK=m
-# CONFIG_PARIDE is not set
-CONFIG_CDROM=m
-CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
-CONFIG_ZRAM=m
-# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
-CONFIG_ZRAM_DEF_COMP_ZSTD=y
-# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
-# CONFIG_ZRAM_DEF_COMP_LZO is not set
-# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
-# CONFIG_ZRAM_DEF_COMP_842 is not set
-CONFIG_ZRAM_DEF_COMP="zstd"
-CONFIG_ZRAM_WRITEBACK=y
-# CONFIG_ZRAM_MEMORY_TRACKING is not set
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
-CONFIG_BLK_DEV_DRBD=m
-# CONFIG_DRBD_FAULT_INJECTION is not set
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_SX8=m
-CONFIG_BLK_DEV_RAM=m
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=131072
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-CONFIG_CDROM_PKTCDVD_WCACHE=y
-CONFIG_ATA_OVER_ETH=m
-CONFIG_VIRTIO_BLK=m
-CONFIG_BLK_DEV_RBD=m
-CONFIG_BLK_DEV_RSXX=m
-CONFIG_BLK_DEV_RNBD=y
-CONFIG_BLK_DEV_RNBD_CLIENT=m
-CONFIG_BLK_DEV_RNBD_SERVER=m
-
-#
-# NVME Support
-#
-CONFIG_NVME_CORE=m
-CONFIG_BLK_DEV_NVME=m
-CONFIG_NVME_MULTIPATH=y
-CONFIG_NVME_VERBOSE_ERRORS=y
-CONFIG_NVME_HWMON=y
-CONFIG_NVME_FABRICS=m
-CONFIG_NVME_RDMA=m
-CONFIG_NVME_FC=m
-CONFIG_NVME_TCP=m
-CONFIG_NVME_APPLE=m
-CONFIG_NVME_TARGET=m
-# CONFIG_NVME_TARGET_PASSTHRU is not set
-CONFIG_NVME_TARGET_LOOP=m
-CONFIG_NVME_TARGET_RDMA=m
-CONFIG_NVME_TARGET_FC=m
-CONFIG_NVME_TARGET_FCLOOP=m
-CONFIG_NVME_TARGET_TCP=m
-# end of NVME Support
-
-#
-# Misc devices
-#
-CONFIG_SENSORS_LIS3LV02D=m
-CONFIG_AD525X_DPOT=m
-CONFIG_AD525X_DPOT_I2C=m
-# CONFIG_AD525X_DPOT_SPI is not set
-CONFIG_DUMMY_IRQ=m
-CONFIG_PHANTOM=m
-CONFIG_TIFM_CORE=m
-CONFIG_TIFM_7XX1=m
-CONFIG_ICS932S401=m
-CONFIG_ENCLOSURE_SERVICES=m
-CONFIG_HI6421V600_IRQ=m
-CONFIG_HP_ILO=m
-# CONFIG_QCOM_COINCELL is not set
-CONFIG_QCOM_FASTRPC=m
-# CONFIG_APDS9802ALS is not set
-# CONFIG_ISL29003 is not set
-CONFIG_ISL29020=m
-CONFIG_SENSORS_TSL2550=m
-CONFIG_SENSORS_BH1770=m
-CONFIG_SENSORS_APDS990X=m
-CONFIG_HMC6352=m
-CONFIG_DS1682=m
-# CONFIG_LATTICE_ECP3_CONFIG is not set
-CONFIG_SRAM=y
-CONFIG_DW_XDATA_PCIE=m
-CONFIG_PCI_ENDPOINT_TEST=m
-CONFIG_XILINX_SDFEC=m
-CONFIG_MISC_RTSX=m
-CONFIG_HISI_HIKEY_USB=m
-CONFIG_OPEN_DICE=m
-CONFIG_C2PORT=m
-
-#
-# EEPROM support
-#
-CONFIG_EEPROM_AT24=m
-# CONFIG_EEPROM_AT25 is not set
-CONFIG_EEPROM_LEGACY=m
-CONFIG_EEPROM_MAX6875=m
-CONFIG_EEPROM_93CX6=m
-# CONFIG_EEPROM_93XX46 is not set
-CONFIG_EEPROM_IDT_89HPESX=m
-CONFIG_EEPROM_EE1004=m
-# end of EEPROM support
-
-CONFIG_CB710_CORE=m
-# CONFIG_CB710_DEBUG is not set
-CONFIG_CB710_DEBUG_ASSUMPTIONS=y
-
-#
-# Texas Instruments shared transport line discipline
-#
-CONFIG_TI_ST=m
-# end of Texas Instruments shared transport line discipline
-
-CONFIG_SENSORS_LIS3_I2C=m
-CONFIG_ALTERA_STAPL=m
-CONFIG_VMWARE_VMCI=m
-CONFIG_GENWQE=m
-CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0
-CONFIG_ECHO=m
-CONFIG_BCM_VK=m
-# CONFIG_BCM_VK_TTY is not set
-CONFIG_MISC_ALCOR_PCI=m
-CONFIG_MISC_RTSX_PCI=m
-CONFIG_MISC_RTSX_USB=m
-CONFIG_HABANA_AI=m
-CONFIG_UACCE=m
-CONFIG_PVPANIC=y
-CONFIG_PVPANIC_MMIO=m
-CONFIG_PVPANIC_PCI=m
-CONFIG_GP_PCI1XXXX=m
-# end of Misc devices
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=y
-CONFIG_RAID_ATTRS=m
-CONFIG_SCSI_COMMON=y
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_BLK_DEV_BSG=y
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_ENCLOSURE=m
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_ISCSI_ATTRS=m
-CONFIG_SCSI_SAS_ATTRS=m
-CONFIG_SCSI_SAS_LIBSAS=m
-CONFIG_SCSI_SAS_ATA=y
-CONFIG_SCSI_SAS_HOST_SMP=y
-CONFIG_SCSI_SRP_ATTRS=m
-# end of SCSI Transports
-
-CONFIG_SCSI_LOWLEVEL=y
-CONFIG_ISCSI_TCP=m
-CONFIG_ISCSI_BOOT_SYSFS=m
-CONFIG_SCSI_CXGB3_ISCSI=m
-CONFIG_SCSI_CXGB4_ISCSI=m
-CONFIG_SCSI_BNX2_ISCSI=m
-CONFIG_SCSI_BNX2X_FCOE=m
-CONFIG_BE2ISCSI=m
-CONFIG_BLK_DEV_3W_XXXX_RAID=m
-CONFIG_SCSI_HPSA=m
-CONFIG_SCSI_3W_9XXX=m
-CONFIG_SCSI_3W_SAS=m
-CONFIG_SCSI_ACARD=m
-CONFIG_SCSI_AACRAID=m
-CONFIG_SCSI_AIC7XXX=m
-CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
-CONFIG_AIC7XXX_RESET_DELAY_MS=15000
-# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
-CONFIG_AIC7XXX_DEBUG_MASK=0
-CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
-CONFIG_SCSI_AIC79XX=m
-CONFIG_AIC79XX_CMDS_PER_DEVICE=32
-CONFIG_AIC79XX_RESET_DELAY_MS=5000
-# CONFIG_AIC79XX_DEBUG_ENABLE is not set
-CONFIG_AIC79XX_DEBUG_MASK=0
-CONFIG_AIC79XX_REG_PRETTY_PRINT=y
-CONFIG_SCSI_AIC94XX=m
-# CONFIG_AIC94XX_DEBUG is not set
-CONFIG_SCSI_HISI_SAS=m
-CONFIG_SCSI_HISI_SAS_PCI=m
-# CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE is not set
-CONFIG_SCSI_MVSAS=m
-# CONFIG_SCSI_MVSAS_DEBUG is not set
-CONFIG_SCSI_MVSAS_TASKLET=y
-CONFIG_SCSI_MVUMI=m
-CONFIG_SCSI_ADVANSYS=m
-CONFIG_SCSI_ARCMSR=m
-CONFIG_SCSI_ESAS2R=m
-CONFIG_MEGARAID_NEWGEN=y
-CONFIG_MEGARAID_MM=m
-CONFIG_MEGARAID_MAILBOX=m
-CONFIG_MEGARAID_LEGACY=m
-CONFIG_MEGARAID_SAS=m
-CONFIG_SCSI_MPT3SAS=m
-CONFIG_SCSI_MPT2SAS_MAX_SGE=128
-CONFIG_SCSI_MPT3SAS_MAX_SGE=128
-CONFIG_SCSI_MPT2SAS=m
-CONFIG_SCSI_MPI3MR=m
-CONFIG_SCSI_SMARTPQI=m
-CONFIG_SCSI_UFSHCD=m
-CONFIG_SCSI_UFSHCD_PCI=m
-# CONFIG_SCSI_UFS_DWC_TC_PCI is not set
-CONFIG_SCSI_UFSHCD_PLATFORM=m
-CONFIG_SCSI_UFS_CDNS_PLATFORM=m
-# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set
-# CONFIG_SCSI_UFS_QCOM is not set
-CONFIG_SCSI_UFS_MEDIATEK=m
-CONFIG_SCSI_UFS_HISI=m
-CONFIG_SCSI_UFS_RENESAS=m
-CONFIG_SCSI_UFS_TI_J721E=m
-CONFIG_SCSI_UFS_BSG=y
-CONFIG_SCSI_UFS_EXYNOS=m
-CONFIG_SCSI_UFS_CRYPTO=y
-CONFIG_SCSI_UFS_HPB=y
-# CONFIG_SCSI_UFS_HWMON is not set
-CONFIG_SCSI_HPTIOP=m
-CONFIG_SCSI_MYRB=m
-CONFIG_SCSI_MYRS=m
-CONFIG_HYPERV_STORAGE=m
-CONFIG_LIBFC=m
-CONFIG_LIBFCOE=m
-CONFIG_FCOE=m
-CONFIG_SCSI_SNIC=m
-CONFIG_SCSI_SNIC_DEBUG_FS=y
-CONFIG_SCSI_DMX3191D=m
-CONFIG_SCSI_FDOMAIN=m
-CONFIG_SCSI_FDOMAIN_PCI=m
-CONFIG_SCSI_IPS=m
-CONFIG_SCSI_INITIO=m
-CONFIG_SCSI_INIA100=m
-CONFIG_SCSI_PPA=m
-CONFIG_SCSI_IMM=m
-# CONFIG_SCSI_IZIP_EPP16 is not set
-# CONFIG_SCSI_IZIP_SLOW_CTR is not set
-CONFIG_SCSI_STEX=m
-CONFIG_SCSI_SYM53C8XX_2=m
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_IPR=m
-CONFIG_SCSI_IPR_TRACE=y
-CONFIG_SCSI_IPR_DUMP=y
-CONFIG_SCSI_QLOGIC_1280=m
-CONFIG_SCSI_QLA_FC=m
-CONFIG_TCM_QLA2XXX=m
-# CONFIG_TCM_QLA2XXX_DEBUG is not set
-CONFIG_SCSI_QLA_ISCSI=m
-CONFIG_QEDI=m
-CONFIG_QEDF=m
-CONFIG_SCSI_LPFC=m
-# CONFIG_SCSI_LPFC_DEBUG_FS is not set
-CONFIG_SCSI_EFCT=m
-CONFIG_SCSI_DC395x=m
-CONFIG_SCSI_AM53C974=m
-CONFIG_SCSI_WD719X=m
-CONFIG_SCSI_DEBUG=m
-CONFIG_SCSI_PMCRAID=m
-CONFIG_SCSI_PM8001=m
-CONFIG_SCSI_BFA_FC=m
-CONFIG_SCSI_VIRTIO=m
-CONFIG_SCSI_CHELSIO_FCOE=m
-CONFIG_SCSI_DH=y
-CONFIG_SCSI_DH_RDAC=m
-CONFIG_SCSI_DH_HP_SW=m
-CONFIG_SCSI_DH_EMC=m
-CONFIG_SCSI_DH_ALUA=m
-# end of SCSI device support
-
-CONFIG_HAVE_PATA_PLATFORM=y
-CONFIG_PATA_OF_PLATFORM=m
-CONFIG_ATA=m
-CONFIG_SATA_HOST=y
-CONFIG_PATA_TIMINGS=y
-# CONFIG_ATA_VERBOSE_ERROR is not set
-CONFIG_ATA_FORCE=y
-CONFIG_ATA_ACPI=y
-CONFIG_SATA_ZPODD=y
-CONFIG_SATA_PMP=y
-
-#
-# Controllers with non-SFF native interface
-#
-CONFIG_SATA_AHCI=m
-CONFIG_SATA_MOBILE_LPM_POLICY=0
-CONFIG_SATA_AHCI_PLATFORM=m
-CONFIG_AHCI_BRCM=m
-CONFIG_AHCI_DWC=m
-CONFIG_AHCI_IMX=m
-CONFIG_AHCI_CEVA=m
-CONFIG_AHCI_MTK=m
-CONFIG_AHCI_MVEBU=m
-CONFIG_AHCI_SUNXI=m
-CONFIG_AHCI_TEGRA=m
-CONFIG_AHCI_XGENE=m
-CONFIG_AHCI_QORIQ=m
-CONFIG_SATA_AHCI_SEATTLE=m
-CONFIG_SATA_INIC162X=m
-CONFIG_SATA_ACARD_AHCI=m
-CONFIG_SATA_SIL24=m
-CONFIG_ATA_SFF=y
-
-#
-# SFF controllers with custom DMA interface
-#
-CONFIG_PDC_ADMA=m
-CONFIG_SATA_QSTOR=m
-CONFIG_SATA_SX4=m
-CONFIG_ATA_BMDMA=y
-
-#
-# SATA SFF controllers with BMDMA
-#
-# CONFIG_ATA_PIIX is not set
-CONFIG_SATA_DWC=m
-CONFIG_SATA_DWC_OLD_DMA=y
-# CONFIG_SATA_DWC_DEBUG is not set
-CONFIG_SATA_MV=m
-# CONFIG_SATA_NV is not set
-CONFIG_SATA_PROMISE=m
-CONFIG_SATA_RCAR=m
-CONFIG_SATA_SIL=m
-# CONFIG_SATA_SIS is not set
-CONFIG_SATA_SVW=m
-# CONFIG_SATA_ULI is not set
-CONFIG_SATA_VIA=m
-CONFIG_SATA_VITESSE=m
-
-#
-# PATA SFF controllers with BMDMA
-#
-CONFIG_PATA_ALI=m
-CONFIG_PATA_AMD=m
-CONFIG_PATA_ARTOP=m
-CONFIG_PATA_ATIIXP=m
-CONFIG_PATA_ATP867X=m
-CONFIG_PATA_CMD64X=m
-CONFIG_PATA_CYPRESS=m
-CONFIG_PATA_EFAR=m
-CONFIG_PATA_HPT366=m
-CONFIG_PATA_HPT37X=m
-CONFIG_PATA_HPT3X2N=m
-CONFIG_PATA_HPT3X3=m
-# CONFIG_PATA_HPT3X3_DMA is not set
-CONFIG_PATA_IMX=m
-CONFIG_PATA_IT8213=m
-CONFIG_PATA_IT821X=m
-CONFIG_PATA_JMICRON=m
-CONFIG_PATA_MARVELL=m
-CONFIG_PATA_NETCELL=m
-CONFIG_PATA_NINJA32=m
-CONFIG_PATA_NS87415=m
-CONFIG_PATA_OLDPIIX=m
-CONFIG_PATA_OPTIDMA=m
-CONFIG_PATA_PDC2027X=m
-CONFIG_PATA_PDC_OLD=m
-CONFIG_PATA_RADISYS=m
-CONFIG_PATA_RDC=m
-CONFIG_PATA_SCH=m
-CONFIG_PATA_SERVERWORKS=m
-CONFIG_PATA_SIL680=m
-CONFIG_PATA_SIS=m
-CONFIG_PATA_TOSHIBA=m
-CONFIG_PATA_TRIFLEX=m
-CONFIG_PATA_VIA=m
-CONFIG_PATA_WINBOND=m
-
-#
-# PIO-only SFF controllers
-#
-CONFIG_PATA_CMD640_PCI=m
-CONFIG_PATA_MPIIX=m
-CONFIG_PATA_NS87410=m
-CONFIG_PATA_OPTI=m
-CONFIG_PATA_PLATFORM=m
-# CONFIG_PATA_OF_PLATFORM is not set
-CONFIG_PATA_RZ1000=m
-
-#
-# Generic fallback / legacy drivers
-#
-# CONFIG_PATA_ACPI is not set
-CONFIG_ATA_GENERIC=m
-# CONFIG_PATA_LEGACY is not set
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID456=m
-CONFIG_MD_MULTIPATH=m
-CONFIG_MD_FAULTY=m
-CONFIG_MD_CLUSTER=m
-CONFIG_BCACHE=m
-# CONFIG_BCACHE_DEBUG is not set
-# CONFIG_BCACHE_CLOSURES_DEBUG is not set
-CONFIG_BCACHE_ASYNC_REGISTRATION=y
-CONFIG_BLK_DEV_DM_BUILTIN=y
-CONFIG_BLK_DEV_DM=m
-# CONFIG_DM_DEBUG is not set
-CONFIG_DM_BUFIO=m
-# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
-CONFIG_DM_BIO_PRISON=m
-CONFIG_DM_PERSISTENT_DATA=m
-CONFIG_DM_UNSTRIPED=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_THIN_PROVISIONING=m
-CONFIG_DM_CACHE=m
-CONFIG_DM_CACHE_SMQ=m
-CONFIG_DM_WRITECACHE=m
-CONFIG_DM_EBS=m
-CONFIG_DM_ERA=m
-CONFIG_DM_CLONE=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_LOG_USERSPACE=m
-CONFIG_DM_RAID=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_QL=m
-CONFIG_DM_MULTIPATH_ST=m
-CONFIG_DM_MULTIPATH_HST=m
-CONFIG_DM_MULTIPATH_IOA=m
-CONFIG_DM_DELAY=m
-CONFIG_DM_DUST=m
-CONFIG_DM_UEVENT=y
-CONFIG_DM_FLAKEY=m
-CONFIG_DM_VERITY=m
-CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
-# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING is not set
-CONFIG_DM_VERITY_FEC=y
-CONFIG_DM_SWITCH=m
-CONFIG_DM_LOG_WRITES=m
-CONFIG_DM_INTEGRITY=m
-CONFIG_DM_ZONED=m
-CONFIG_DM_AUDIT=y
-CONFIG_TARGET_CORE=m
-CONFIG_TCM_IBLOCK=m
-CONFIG_TCM_FILEIO=m
-CONFIG_TCM_PSCSI=m
-CONFIG_TCM_USER2=m
-CONFIG_LOOPBACK_TARGET=m
-CONFIG_TCM_FC=m
-CONFIG_ISCSI_TARGET=m
-CONFIG_ISCSI_TARGET_CXGB4=m
-CONFIG_SBP_TARGET=m
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=m
-CONFIG_FUSION_FC=m
-CONFIG_FUSION_SAS=m
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_CTL=m
-CONFIG_FUSION_LAN=m
-# CONFIG_FUSION_LOGGING is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-CONFIG_FIREWIRE=m
-CONFIG_FIREWIRE_OHCI=m
-CONFIG_FIREWIRE_SBP2=m
-CONFIG_FIREWIRE_NET=m
-CONFIG_FIREWIRE_NOSY=m
-# end of IEEE 1394 (FireWire) support
-
-CONFIG_NETDEVICES=y
-CONFIG_MII=m
-CONFIG_NET_CORE=y
-CONFIG_BONDING=m
-CONFIG_DUMMY=m
-CONFIG_WIREGUARD=m
-# CONFIG_WIREGUARD_DEBUG is not set
-CONFIG_EQUALIZER=m
-CONFIG_NET_FC=y
-CONFIG_IFB=m
-CONFIG_NET_TEAM=m
-CONFIG_NET_TEAM_MODE_BROADCAST=m
-CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
-CONFIG_NET_TEAM_MODE_RANDOM=m
-CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
-CONFIG_NET_TEAM_MODE_LOADBALANCE=m
-CONFIG_MACVLAN=m
-CONFIG_MACVTAP=m
-CONFIG_IPVLAN_L3S=y
-CONFIG_IPVLAN=m
-CONFIG_IPVTAP=m
-CONFIG_VXLAN=m
-CONFIG_GENEVE=m
-CONFIG_BAREUDP=m
-CONFIG_GTP=m
-# CONFIG_AMT is not set
-CONFIG_MACSEC=m
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_NETPOLL=y
-CONFIG_NET_POLL_CONTROLLER=y
-CONFIG_NTB_NETDEV=m
-CONFIG_RIONET=m
-CONFIG_RIONET_TX_SIZE=128
-CONFIG_RIONET_RX_SIZE=128
-CONFIG_TUN=m
-CONFIG_TAP=m
-# CONFIG_TUN_VNET_CROSS_LE is not set
-CONFIG_VETH=m
-CONFIG_VIRTIO_NET=m
-CONFIG_NLMON=m
-CONFIG_NET_VRF=m
-CONFIG_VSOCKMON=m
-CONFIG_MHI_NET=m
-CONFIG_SUNGEM_PHY=m
-CONFIG_ARCNET=m
-CONFIG_ARCNET_1201=m
-CONFIG_ARCNET_1051=m
-CONFIG_ARCNET_RAW=m
-CONFIG_ARCNET_CAP=m
-CONFIG_ARCNET_COM90xx=m
-CONFIG_ARCNET_COM90xxIO=m
-CONFIG_ARCNET_RIM_I=m
-CONFIG_ARCNET_COM20020=m
-CONFIG_ARCNET_COM20020_PCI=m
-CONFIG_ATM_DRIVERS=y
-CONFIG_ATM_DUMMY=m
-CONFIG_ATM_TCP=m
-CONFIG_ATM_LANAI=m
-CONFIG_ATM_ENI=m
-# CONFIG_ATM_ENI_DEBUG is not set
-CONFIG_ATM_ENI_TUNE_BURST=y
-CONFIG_ATM_ENI_BURST_TX_16W=y
-CONFIG_ATM_ENI_BURST_TX_8W=y
-CONFIG_ATM_ENI_BURST_TX_4W=y
-CONFIG_ATM_ENI_BURST_TX_2W=y
-CONFIG_ATM_ENI_BURST_RX_16W=y
-CONFIG_ATM_ENI_BURST_RX_8W=y
-CONFIG_ATM_ENI_BURST_RX_4W=y
-CONFIG_ATM_ENI_BURST_RX_2W=y
-CONFIG_ATM_NICSTAR=m
-CONFIG_ATM_NICSTAR_USE_SUNI=y
-CONFIG_ATM_NICSTAR_USE_IDT77105=y
-CONFIG_ATM_IDT77252=m
-# CONFIG_ATM_IDT77252_DEBUG is not set
-# CONFIG_ATM_IDT77252_RCV_ALL is not set
-CONFIG_ATM_IDT77252_USE_SUNI=y
-CONFIG_ATM_IA=m
-# CONFIG_ATM_IA_DEBUG is not set
-CONFIG_ATM_FORE200E=m
-CONFIG_ATM_FORE200E_USE_TASKLET=y
-CONFIG_ATM_FORE200E_TX_RETRY=16
-CONFIG_ATM_FORE200E_DEBUG=0
-CONFIG_ATM_HE=m
-CONFIG_ATM_HE_USE_SUNI=y
-CONFIG_ATM_SOLOS=m
-# CONFIG_CAIF_DRIVERS is not set
-
-#
-# Distributed Switch Architecture drivers
-#
-CONFIG_B53=m
-CONFIG_B53_SPI_DRIVER=m
-CONFIG_B53_MDIO_DRIVER=m
-CONFIG_B53_MMAP_DRIVER=m
-CONFIG_B53_SRAB_DRIVER=m
-CONFIG_B53_SERDES=m
-CONFIG_NET_DSA_BCM_SF2=m
-CONFIG_NET_DSA_LOOP=m
-CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
-CONFIG_NET_DSA_LANTIQ_GSWIP=m
-CONFIG_NET_DSA_MT7530=m
-CONFIG_NET_DSA_MV88E6060=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-CONFIG_NET_DSA_MV88E6XXX=m
-CONFIG_NET_DSA_MV88E6XXX_PTP=y
-CONFIG_NET_DSA_MSCC_FELIX=m
-CONFIG_NET_DSA_MSCC_SEVILLE=m
-# CONFIG_NET_DSA_AR9331 is not set
-CONFIG_NET_DSA_SJA1105=m
-CONFIG_NET_DSA_SJA1105_PTP=y
-CONFIG_NET_DSA_SJA1105_TAS=y
-CONFIG_NET_DSA_SJA1105_VL=y
-CONFIG_NET_DSA_XRS700X=m
-CONFIG_NET_DSA_XRS700X_I2C=m
-CONFIG_NET_DSA_XRS700X_MDIO=m
-CONFIG_NET_DSA_QCA8K=m
-CONFIG_NET_DSA_REALTEK_SMI=m
-CONFIG_NET_DSA_SMSC_LAN9303=m
-CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
-CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
-CONFIG_NET_DSA_VITESSE_VSC73XX=m
-CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
-CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
-# end of Distributed Switch Architecture drivers
-
-CONFIG_ETHERNET=y
-CONFIG_MDIO=m
-CONFIG_NET_VENDOR_3COM=y
-CONFIG_VORTEX=m
-CONFIG_TYPHOON=m
-CONFIG_NET_VENDOR_ACTIONS=y
-CONFIG_OWL_EMAC=m
-CONFIG_NET_VENDOR_ADAPTEC=y
-CONFIG_ADAPTEC_STARFIRE=m
-CONFIG_NET_VENDOR_AGERE=y
-CONFIG_ET131X=m
-CONFIG_NET_VENDOR_ALACRITECH=y
-CONFIG_SLICOSS=m
-CONFIG_NET_VENDOR_ALLWINNER=y
-# CONFIG_SUN4I_EMAC is not set
-CONFIG_NET_VENDOR_ALTEON=y
-CONFIG_ACENIC=m
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
-# CONFIG_ALTERA_TSE is not set
-CONFIG_NET_VENDOR_AMAZON=y
-CONFIG_ENA_ETHERNET=m
-CONFIG_NET_VENDOR_AMD=y
-CONFIG_AMD8111_ETH=m
-CONFIG_PCNET32=m
-CONFIG_AMD_XGBE=m
-CONFIG_AMD_XGBE_DCB=y
-CONFIG_NET_XGENE=y
-CONFIG_NET_XGENE_V2=y
-CONFIG_NET_VENDOR_AQUANTIA=y
-CONFIG_AQTION=m
-CONFIG_NET_VENDOR_ARC=y
-# CONFIG_EMAC_ROCKCHIP is not set
-CONFIG_NET_VENDOR_ASIX=y
-# CONFIG_SPI_AX88796C is not set
-CONFIG_NET_VENDOR_ATHEROS=y
-CONFIG_ATL2=m
-CONFIG_ATL1=m
-CONFIG_ATL1E=m
-CONFIG_ATL1C=m
-CONFIG_ALX=m
-CONFIG_NET_VENDOR_BROADCOM=y
-CONFIG_B44=m
-CONFIG_B44_PCI_AUTOSELECT=y
-CONFIG_B44_PCICORE_AUTOSELECT=y
-CONFIG_B44_PCI=y
-CONFIG_BCM4908_ENET=m
-CONFIG_BCMGENET=m
-CONFIG_BNX2=m
-CONFIG_CNIC=m
-CONFIG_TIGON3=m
-CONFIG_TIGON3_HWMON=y
-CONFIG_BNX2X=m
-CONFIG_BNX2X_SRIOV=y
-CONFIG_BGMAC=m
-CONFIG_BGMAC_PLATFORM=m
-CONFIG_SYSTEMPORT=m
-CONFIG_BNXT=m
-CONFIG_BNXT_SRIOV=y
-CONFIG_BNXT_FLOWER_OFFLOAD=y
-CONFIG_BNXT_DCB=y
-CONFIG_BNXT_HWMON=y
-CONFIG_NET_VENDOR_BROCADE=y
-CONFIG_BNA=m
-CONFIG_NET_VENDOR_CADENCE=y
-CONFIG_MACB=m
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MACB_PCI=m
-CONFIG_NET_VENDOR_CAVIUM=y
-CONFIG_THUNDER_NIC_PF=m
-CONFIG_THUNDER_NIC_VF=m
-CONFIG_THUNDER_NIC_BGX=m
-CONFIG_THUNDER_NIC_RGX=m
-CONFIG_CAVIUM_PTP=m
-CONFIG_LIQUIDIO=m
-CONFIG_LIQUIDIO_VF=m
-CONFIG_NET_VENDOR_CHELSIO=y
-CONFIG_CHELSIO_T1=m
-CONFIG_CHELSIO_T1_1G=y
-CONFIG_CHELSIO_T3=m
-CONFIG_CHELSIO_T4=m
-CONFIG_CHELSIO_T4_DCB=y
-CONFIG_CHELSIO_T4_FCOE=y
-CONFIG_CHELSIO_T4VF=m
-CONFIG_CHELSIO_LIB=m
-CONFIG_CHELSIO_INLINE_CRYPTO=y
-CONFIG_CHELSIO_IPSEC_INLINE=m
-CONFIG_CHELSIO_TLS_DEVICE=m
-CONFIG_NET_VENDOR_CISCO=y
-CONFIG_ENIC=m
-CONFIG_NET_VENDOR_CORTINA=y
-CONFIG_NET_VENDOR_DAVICOM=y
-CONFIG_DM9051=m
-CONFIG_GEMINI_ETHERNET=m
-CONFIG_DNET=m
-CONFIG_NET_VENDOR_DEC=y
-CONFIG_NET_TULIP=y
-CONFIG_DE2104X=m
-CONFIG_DE2104X_DSL=0
-CONFIG_TULIP=m
-# CONFIG_TULIP_MWI is not set
-# CONFIG_TULIP_MMIO is not set
-CONFIG_TULIP_NAPI=y
-CONFIG_TULIP_NAPI_HW_MITIGATION=y
-CONFIG_WINBOND_840=m
-CONFIG_DM9102=m
-CONFIG_ULI526X=m
-CONFIG_NET_VENDOR_DLINK=y
-CONFIG_DL2K=m
-CONFIG_SUNDANCE=m
-# CONFIG_SUNDANCE_MMIO is not set
-CONFIG_NET_VENDOR_EMULEX=y
-CONFIG_BE2NET=m
-CONFIG_BE2NET_HWMON=y
-CONFIG_BE2NET_BE2=y
-CONFIG_BE2NET_BE3=y
-CONFIG_BE2NET_LANCER=y
-CONFIG_BE2NET_SKYHAWK=y
-CONFIG_NET_VENDOR_EZCHIP=y
-CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=m
-CONFIG_NET_VENDOR_FREESCALE=y
-CONFIG_NET_VENDOR_FUNGIBLE=y
-CONFIG_FUN_ETH=m
-CONFIG_FEC=m
-CONFIG_FSL_FMAN=m
-CONFIG_DPAA_ERRATUM_A050385=y
-CONFIG_FSL_PQ_MDIO=m
-CONFIG_FSL_XGMAC_MDIO=y
-CONFIG_GIANFAR=m
-CONFIG_FSL_DPAA_ETH=m
-CONFIG_FSL_DPAA2_ETH=m
-CONFIG_FSL_DPAA2_ETH_DCB=y
-CONFIG_FSL_DPAA2_PTP_CLOCK=m
-CONFIG_FSL_DPAA2_SWITCH=m
-CONFIG_FSL_ENETC=m
-CONFIG_FSL_ENETC_VF=m
-CONFIG_FSL_ENETC_IERB=m
-CONFIG_FSL_ENETC_MDIO=m
-CONFIG_FSL_ENETC_PTP_CLOCK=m
-CONFIG_FSL_ENETC_QOS=y
-CONFIG_NET_VENDOR_GOOGLE=y
-CONFIG_GVE=m
-CONFIG_NET_VENDOR_HISILICON=y
-CONFIG_HIX5HD2_GMAC=m
-CONFIG_HISI_FEMAC=m
-CONFIG_HIP04_ETH=m
-CONFIG_HI13X1_GMAC=y
-CONFIG_HNS_MDIO=m
-CONFIG_HNS=m
-CONFIG_HNS_DSAF=m
-CONFIG_HNS_ENET=m
-CONFIG_HNS3=m
-CONFIG_HNS3_HCLGE=m
-CONFIG_HNS3_DCB=y
-CONFIG_HNS3_HCLGEVF=m
-CONFIG_HNS3_ENET=m
-CONFIG_NET_VENDOR_HUAWEI=y
-CONFIG_HINIC=m
-CONFIG_NET_VENDOR_I825XX=y
-CONFIG_NET_VENDOR_INTEL=y
-CONFIG_E100=m
-CONFIG_E1000=m
-CONFIG_E1000E=m
-CONFIG_IGB=m
-CONFIG_IGB_HWMON=y
-CONFIG_IGBVF=m
-CONFIG_IXGB=m
-CONFIG_IXGBE=m
-CONFIG_IXGBE_HWMON=y
-CONFIG_IXGBE_DCB=y
-CONFIG_IXGBE_IPSEC=y
-CONFIG_IXGBEVF=m
-CONFIG_IXGBEVF_IPSEC=y
-CONFIG_I40E=m
-CONFIG_I40E_DCB=y
-CONFIG_IAVF=m
-CONFIG_I40EVF=m
-CONFIG_ICE=m
-CONFIG_ICE_SWITCHDEV=y
-CONFIG_ICE_HWTS=y
-CONFIG_FM10K=m
-CONFIG_IGC=m
-CONFIG_NET_VENDOR_MICROSOFT=y
-CONFIG_JME=m
-CONFIG_NET_VENDOR_LITEX=y
-CONFIG_LITEX_LITEETH=m
-CONFIG_NET_VENDOR_MARVELL=y
-CONFIG_MVMDIO=m
-CONFIG_MVNETA=m
-CONFIG_MVPP2=m
-CONFIG_MVPP2_PTP=y
-# CONFIG_PXA168_ETH is not set
-CONFIG_SKGE=m
-# CONFIG_SKGE_DEBUG is not set
-CONFIG_SKGE_GENESIS=y
-CONFIG_SKY2=m
-# CONFIG_SKY2_DEBUG is not set
-CONFIG_OCTEONTX2_MBOX=m
-CONFIG_OCTEONTX2_AF=m
-# CONFIG_NDC_DIS_DYNAMIC_CACHING is not set
-CONFIG_OCTEONTX2_PF=m
-CONFIG_OCTEONTX2_VF=m
-CONFIG_OCTEON_EP=m
-CONFIG_PRESTERA=m
-CONFIG_PRESTERA_PCI=m
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NET_MEDIATEK_SOC=m
-CONFIG_NET_MEDIATEK_STAR_EMAC=m
-CONFIG_NET_VENDOR_MELLANOX=y
-CONFIG_MLX4_EN=m
-CONFIG_MLX4_EN_DCB=y
-CONFIG_MLX4_CORE=m
-# CONFIG_MLX4_DEBUG is not set
-CONFIG_MLX4_CORE_GEN2=y
-CONFIG_MLX5_CORE=m
-CONFIG_MLX5_ACCEL=y
-CONFIG_MLX5_FPGA=y
-CONFIG_MLX5_CORE_EN=y
-CONFIG_MLX5_EN_ARFS=y
-CONFIG_MLX5_EN_RXNFC=y
-CONFIG_MLX5_MPFS=y
-CONFIG_MLX5_ESWITCH=y
-CONFIG_MLX5_BRIDGE=y
-CONFIG_MLX5_CLS_ACT=y
-CONFIG_MLX5_TC_CT=y
-CONFIG_MLX5_TC_SAMPLE=y
-CONFIG_MLX5_CORE_EN_DCB=y
-CONFIG_MLX5_CORE_IPOIB=y
-CONFIG_MLX5_EN_MACSEC=y
-CONFIG_MLX5_EN_IPSEC=y
-CONFIG_MLX5_FPGA_IPSEC=y
-CONFIG_MLX5_IPSEC=y
-CONFIG_MLX5_EN_IPSEC=y
-CONFIG_MLX5_FPGA_TLS=y
-CONFIG_MLX5_TLS=y
-CONFIG_MLX5_EN_TLS=y
-CONFIG_MLX5_SW_STEERING=y
-CONFIG_MLX5_SF=y
-CONFIG_MLX5_SF_MANAGER=y
-CONFIG_MLXSW_CORE=m
-CONFIG_MLXSW_CORE_HWMON=y
-CONFIG_MLXSW_CORE_THERMAL=y
-CONFIG_MLXSW_PCI=m
-CONFIG_MLXSW_I2C=m
-CONFIG_MLXSW_SPECTRUM=m
-CONFIG_MLXSW_SPECTRUM_DCB=y
-CONFIG_MLXSW_MINIMAL=m
-CONFIG_MLXFW=m
-CONFIG_MLXBF_GIGE=m
-CONFIG_NET_VENDOR_MICREL=y
-CONFIG_KS8842=m
-CONFIG_KS8851=m
-CONFIG_KS8851_MLL=m
-CONFIG_KSZ884X_PCI=m
-CONFIG_NET_VENDOR_MICROCHIP=y
-CONFIG_ENC28J60=m
-# CONFIG_ENC28J60_WRITEVERIFY is not set
-CONFIG_ENCX24J600=m
-CONFIG_LAN743X=m
-CONFIG_SPARX5_SWITCH=m
-CONFIG_NET_VENDOR_MICROSEMI=y
-CONFIG_MSCC_OCELOT_SWITCH_LIB=m
-CONFIG_MSCC_OCELOT_SWITCH=m
-CONFIG_NET_VENDOR_MYRI=y
-CONFIG_MYRI10GE=m
-CONFIG_FEALNX=m
-CONFIG_NET_VENDOR_NATSEMI=y
-CONFIG_NATSEMI=m
-CONFIG_NS83820=m
-CONFIG_NET_VENDOR_NETERION=y
-CONFIG_S2IO=m
-CONFIG_VXGE=m
-# CONFIG_VXGE_DEBUG_TRACE_ALL is not set
-CONFIG_NET_VENDOR_NETRONOME=y
-CONFIG_NFP=m
-CONFIG_NFP_APP_FLOWER=y
-CONFIG_NFP_APP_ABM_NIC=y
-# CONFIG_NFP_DEBUG is not set
-CONFIG_NET_VENDOR_NI=y
-CONFIG_NI_XGE_MANAGEMENT_ENET=m
-CONFIG_NET_VENDOR_8390=y
-CONFIG_NE2K_PCI=m
-CONFIG_NET_VENDOR_NVIDIA=y
-CONFIG_FORCEDETH=m
-CONFIG_NET_VENDOR_OKI=y
-CONFIG_ETHOC=m
-CONFIG_NET_VENDOR_PACKET_ENGINES=y
-CONFIG_HAMACHI=m
-CONFIG_YELLOWFIN=m
-CONFIG_NET_VENDOR_PENSANDO=y
-CONFIG_IONIC=m
-CONFIG_NET_VENDOR_QLOGIC=y
-CONFIG_QLA3XXX=m
-CONFIG_QLCNIC=m
-CONFIG_QLCNIC_SRIOV=y
-CONFIG_QLCNIC_DCB=y
-CONFIG_QLCNIC_HWMON=y
-CONFIG_NETXEN_NIC=m
-CONFIG_QED=m
-CONFIG_QED_LL2=y
-CONFIG_QED_SRIOV=y
-CONFIG_QEDE=m
-CONFIG_QED_RDMA=y
-CONFIG_QED_ISCSI=y
-CONFIG_QED_FCOE=y
-CONFIG_QED_OOO=y
-CONFIG_NET_VENDOR_QUALCOMM=y
-CONFIG_QCA7000=m
-CONFIG_QCA7000_SPI=m
-CONFIG_QCA7000_UART=m
-CONFIG_QCOM_EMAC=m
-CONFIG_RMNET=m
-CONFIG_NET_VENDOR_RDC=y
-CONFIG_R6040=m
-CONFIG_NET_VENDOR_REALTEK=y
-CONFIG_8139CP=m
-CONFIG_8139TOO=m
-# CONFIG_8139TOO_PIO is not set
-# CONFIG_8139TOO_TUNE_TWISTER is not set
-CONFIG_8139TOO_8129=y
-# CONFIG_8139_OLD_RX_RESET is not set
-CONFIG_R8169=m
-CONFIG_NET_VENDOR_RENESAS=y
-CONFIG_SH_ETH=m
-CONFIG_RAVB=m
-CONFIG_NET_VENDOR_ROCKER=y
-CONFIG_ROCKER=m
-CONFIG_NET_VENDOR_SAMSUNG=y
-CONFIG_SXGBE_ETH=m
-CONFIG_NET_VENDOR_SEEQ=y
-CONFIG_NET_VENDOR_SOLARFLARE=y
-CONFIG_SFC=m
-CONFIG_SFC_MTD=y
-CONFIG_SFC_MCDI_MON=y
-CONFIG_SFC_SRIOV=y
-CONFIG_SFC_MCDI_LOGGING=y
-CONFIG_SFC_FALCON=m
-CONFIG_SFC_FALCON_MTD=y
-CONFIG_NET_VENDOR_SILAN=y
-CONFIG_SC92031=m
-CONFIG_NET_VENDOR_SIS=y
-CONFIG_SIS900=m
-CONFIG_SIS190=m
-CONFIG_NET_VENDOR_SMSC=y
-CONFIG_SMC91X=m
-CONFIG_EPIC100=m
-CONFIG_SMSC911X=m
-CONFIG_SMSC9420=m
-CONFIG_NET_VENDOR_SOCIONEXT=y
-CONFIG_SNI_AVE=m
-CONFIG_SNI_NETSEC=m
-CONFIG_NET_VENDOR_STMICRO=y
-CONFIG_STMMAC_ETH=m
-# CONFIG_STMMAC_SELFTESTS is not set
-CONFIG_STMMAC_PLATFORM=m
-CONFIG_DWMAC_DWC_QOS_ETH=m
-CONFIG_DWMAC_GENERIC=m
-CONFIG_DWMAC_IPQ806X=m
-CONFIG_DWMAC_MEDIATEK=m
-CONFIG_DWMAC_MESON=m
-CONFIG_DWMAC_QCOM_ETHQOS=m
-CONFIG_DWMAC_ROCKCHIP=y
-CONFIG_DWMAC_SOCFPGA=m
-CONFIG_DWMAC_SUNXI=m
-CONFIG_DWMAC_SUN8I=m
-CONFIG_DWMAC_IMX8=m
-# CONFIG_DWMAC_INTEL_PLAT is not set
-CONFIG_DWMAC_VISCONTI=m
-# CONFIG_DWMAC_LOONGSON is not set
-CONFIG_STMMAC_PCI=m
-CONFIG_NET_VENDOR_SUN=y
-CONFIG_HAPPYMEAL=m
-CONFIG_SUNGEM=m
-CONFIG_CASSINI=m
-CONFIG_NIU=m
-CONFIG_NET_VENDOR_SYNOPSYS=y
-CONFIG_DWC_XLGMAC=m
-CONFIG_DWC_XLGMAC_PCI=m
-CONFIG_NET_VENDOR_TEHUTI=y
-CONFIG_TEHUTI=m
-CONFIG_NET_VENDOR_TI=y
-CONFIG_TI_DAVINCI_MDIO=m
-# CONFIG_TI_CPSW_PHY_SEL is not set
-CONFIG_TI_K3_AM65_CPSW_NUSS=m
-CONFIG_TI_K3_AM65_CPSW_SWITCHDEV=y
-CONFIG_TI_K3_AM65_CPTS=m
-CONFIG_TI_AM65_CPSW_TAS=y
-CONFIG_TLAN=m
-CONFIG_NET_VENDOR_VIA=y
-CONFIG_VIA_RHINE=m
-CONFIG_VIA_RHINE_MMIO=y
-CONFIG_VIA_VELOCITY=m
-CONFIG_NET_VENDOR_WIZNET=y
-CONFIG_WIZNET_W5100=m
-CONFIG_WIZNET_W5300=m
-# CONFIG_WIZNET_BUS_DIRECT is not set
-# CONFIG_WIZNET_BUS_INDIRECT is not set
-CONFIG_WIZNET_BUS_ANY=y
-CONFIG_WIZNET_W5100_SPI=m
-CONFIG_NET_VENDOR_XILINX=y
-CONFIG_XILINX_EMACLITE=m
-CONFIG_XILINX_AXI_EMAC=m
-CONFIG_XILINX_LL_TEMAC=m
-CONFIG_FDDI=m
-CONFIG_DEFXX=m
-CONFIG_SKFP=m
-CONFIG_HIPPI=y
-CONFIG_ROADRUNNER=m
-# CONFIG_ROADRUNNER_LARGE_RINGS is not set
-CONFIG_QCOM_IPA=m
-# CONFIG_NET_SB1000 is not set
-CONFIG_PHYLINK=m
-CONFIG_PHYLIB=y
-CONFIG_SWPHY=y
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_FIXED_PHY=y
-CONFIG_SFP=m
-
-#
-# MII PHY device drivers
-#
-CONFIG_AMD_PHY=m
-CONFIG_MESON_GXL_PHY=m
-CONFIG_ADIN_PHY=m
-CONFIG_AQUANTIA_PHY=m
-CONFIG_AX88796B_PHY=m
-CONFIG_BROADCOM_PHY=m
-CONFIG_BCM54140_PHY=m
-CONFIG_BCM7XXX_PHY=m
-CONFIG_BCM84881_PHY=y
-CONFIG_BCM87XX_PHY=m
-CONFIG_BCM_NET_PHYLIB=m
-CONFIG_CICADA_PHY=m
-CONFIG_CORTINA_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_ICPLUS_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_INTEL_XWAY_PHY=m
-CONFIG_LSI_ET1011C_PHY=m
-CONFIG_MARVELL_PHY=m
-CONFIG_MARVELL_10G_PHY=m
-CONFIG_MARVELL_88X2222_PHY=m
-CONFIG_MAXLINEAR_GPHY=m
-CONFIG_MEDIATEK_GE_PHY=m
-CONFIG_MICREL_PHY=m
-CONFIG_MICROCHIP_PHY=m
-CONFIG_MICROCHIP_T1_PHY=m
-CONFIG_MICROSEMI_PHY=m
-CONFIG_MOTORCOMM_PHY=m
-CONFIG_NATIONAL_PHY=m
-CONFIG_NXP_C45_TJA11XX_PHY=m
-CONFIG_NXP_TJA11XX_PHY=m
-CONFIG_AT803X_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_REALTEK_PHY=m
-CONFIG_RENESAS_PHY=m
-CONFIG_ROCKCHIP_PHY=y
-CONFIG_SMSC_PHY=m
-CONFIG_STE10XP=m
-CONFIG_TERANETICS_PHY=m
-CONFIG_DP83822_PHY=m
-CONFIG_DP83TC811_PHY=m
-CONFIG_DP83848_PHY=m
-CONFIG_DP83867_PHY=m
-CONFIG_DP83869_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_XILINX_GMII2RGMII=m
-CONFIG_MICREL_KS8995MA=m
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_BUS=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_OF_MDIO=y
-CONFIG_ACPI_MDIO=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_SUN4I=m
-CONFIG_MDIO_XGENE=y
-CONFIG_MDIO_BITBANG=m
-# CONFIG_MDIO_BCM_IPROC is not set
-CONFIG_MDIO_BCM_UNIMAC=m
-CONFIG_MDIO_CAVIUM=m
-CONFIG_MDIO_GPIO=m
-CONFIG_MDIO_HISI_FEMAC=m
-CONFIG_MDIO_I2C=m
-CONFIG_MDIO_MVUSB=m
-CONFIG_MDIO_MSCC_MIIM=m
-CONFIG_MDIO_OCTEON=m
-CONFIG_MDIO_IPQ4019=m
-CONFIG_MDIO_IPQ8064=m
-CONFIG_MDIO_THUNDER=m
-
-#
-# MDIO Multiplexers
-#
-CONFIG_MDIO_BUS_MUX=m
-CONFIG_MDIO_BUS_MUX_MESON_G12A=m
-CONFIG_MDIO_BUS_MUX_BCM_IPROC=m
-CONFIG_MDIO_BUS_MUX_GPIO=m
-CONFIG_MDIO_BUS_MUX_MULTIPLEXER=m
-CONFIG_MDIO_BUS_MUX_MMIOREG=m
-
-#
-# PCS device drivers
-#
-CONFIG_PCS_XPCS=m
-CONFIG_PCS_LYNX=m
-# end of PCS device drivers
-
-CONFIG_PLIP=m
-CONFIG_PPP=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_MPPE=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPPOATM=m
-CONFIG_PPPOE=m
-CONFIG_PPTP=m
-CONFIG_PPPOL2TP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_SLIP=m
-CONFIG_SLHC=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-
-#
-# Host-side USB support is needed for USB Network Adapter support
-#
-CONFIG_USB_NET_DRIVERS=m
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_RTL8152=m
-CONFIG_USB_LAN78XX=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_AX8817X=m
-CONFIG_USB_NET_AX88179_178A=m
-CONFIG_USB_NET_CDCETHER=m
-CONFIG_USB_NET_CDC_EEM=m
-CONFIG_USB_NET_CDC_NCM=m
-CONFIG_USB_NET_HUAWEI_CDC_NCM=m
-CONFIG_USB_NET_CDC_MBIM=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_SR9700=m
-CONFIG_USB_NET_SR9800=m
-CONFIG_USB_NET_SMSC75XX=m
-CONFIG_USB_NET_SMSC95XX=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_NET1080=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_MCS7830=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
-CONFIG_USB_NET_CDC_SUBSET=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_BELKIN=y
-CONFIG_USB_ARMLINUX=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-CONFIG_USB_NET_ZAURUS=m
-CONFIG_USB_NET_CX82310_ETH=m
-CONFIG_USB_NET_KALMIA=m
-CONFIG_USB_NET_QMI_WWAN=m
-CONFIG_USB_HSO=m
-CONFIG_USB_NET_INT51X1=m
-CONFIG_USB_CDC_PHONET=m
-CONFIG_USB_IPHETH=m
-CONFIG_USB_SIERRA_NET=m
-CONFIG_USB_VL600=m
-CONFIG_USB_NET_CH9200=m
-CONFIG_USB_NET_AQC111=m
-CONFIG_USB_RTL8153_ECM=m
-CONFIG_WLAN=y
-CONFIG_WLAN_VENDOR_ADMTEK=y
-CONFIG_ADM8211=m
-CONFIG_ATH_COMMON=m
-CONFIG_WLAN_VENDOR_ATH=y
-# CONFIG_ATH_DEBUG is not set
-CONFIG_ATH5K=m
-# CONFIG_ATH5K_DEBUG is not set
-# CONFIG_ATH5K_TRACER is not set
-CONFIG_ATH5K_PCI=y
-CONFIG_ATH9K_HW=m
-CONFIG_ATH9K_COMMON=m
-CONFIG_ATH9K_BTCOEX_SUPPORT=y
-CONFIG_ATH9K=m
-CONFIG_ATH9K_PCI=y
-# CONFIG_ATH9K_AHB is not set
-# CONFIG_ATH9K_DEBUGFS is not set
-# CONFIG_ATH9K_DYNACK is not set
-CONFIG_ATH9K_WOW=y
-CONFIG_ATH9K_RFKILL=y
-CONFIG_ATH9K_CHANNEL_CONTEXT=y
-CONFIG_ATH9K_PCOEM=y
-CONFIG_ATH9K_PCI_NO_EEPROM=m
-CONFIG_ATH9K_HTC=m
-# CONFIG_ATH9K_HTC_DEBUGFS is not set
-CONFIG_ATH9K_HWRNG=y
-CONFIG_CARL9170=m
-CONFIG_CARL9170_LEDS=y
-CONFIG_CARL9170_WPC=y
-CONFIG_CARL9170_HWRNG=y
-CONFIG_ATH6KL=m
-CONFIG_ATH6KL_SDIO=m
-CONFIG_ATH6KL_USB=m
-# CONFIG_ATH6KL_DEBUG is not set
-# CONFIG_ATH6KL_TRACING is not set
-CONFIG_AR5523=m
-CONFIG_WIL6210=m
-CONFIG_WIL6210_ISR_COR=y
-CONFIG_WIL6210_TRACING=y
-# CONFIG_WIL6210_DEBUGFS is not set
-CONFIG_ATH10K=m
-CONFIG_ATH10K_CE=y
-CONFIG_ATH10K_PCI=m
-CONFIG_ATH10K_AHB=y
-CONFIG_ATH10K_SDIO=m
-CONFIG_ATH10K_USB=m
-CONFIG_ATH10K_SNOC=m
-# CONFIG_ATH10K_DEBUG is not set
-# CONFIG_ATH10K_DEBUGFS is not set
-# CONFIG_ATH10K_TRACING is not set
-CONFIG_WCN36XX=m
-# CONFIG_WCN36XX_DEBUGFS is not set
-CONFIG_ATH11K=m
-CONFIG_ATH11K_AHB=m
-CONFIG_ATH11K_PCI=m
-# CONFIG_ATH11K_DEBUG is not set
-# CONFIG_ATH11K_TRACING is not set
-CONFIG_WLAN_VENDOR_ATMEL=y
-CONFIG_ATMEL=m
-CONFIG_PCI_ATMEL=m
-CONFIG_AT76C50X_USB=m
-CONFIG_WLAN_VENDOR_BROADCOM=y
-CONFIG_B43=m
-CONFIG_B43_BCMA=y
-CONFIG_B43_SSB=y
-CONFIG_B43_BUSES_BCMA_AND_SSB=y
-# CONFIG_B43_BUSES_BCMA is not set
-# CONFIG_B43_BUSES_SSB is not set
-CONFIG_B43_PCI_AUTOSELECT=y
-CONFIG_B43_PCICORE_AUTOSELECT=y
-CONFIG_B43_SDIO=y
-CONFIG_B43_BCMA_PIO=y
-CONFIG_B43_PIO=y
-CONFIG_B43_PHY_G=y
-CONFIG_B43_PHY_N=y
-CONFIG_B43_PHY_LP=y
-CONFIG_B43_PHY_HT=y
-CONFIG_B43_LEDS=y
-CONFIG_B43_HWRNG=y
-# CONFIG_B43_DEBUG is not set
-CONFIG_B43LEGACY=m
-CONFIG_B43LEGACY_PCI_AUTOSELECT=y
-CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
-CONFIG_B43LEGACY_LEDS=y
-CONFIG_B43LEGACY_HWRNG=y
-# CONFIG_B43LEGACY_DEBUG is not set
-CONFIG_B43LEGACY_DMA=y
-CONFIG_B43LEGACY_PIO=y
-CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
-# CONFIG_B43LEGACY_DMA_MODE is not set
-# CONFIG_B43LEGACY_PIO_MODE is not set
-CONFIG_BRCMUTIL=m
-CONFIG_BRCMSMAC=m
-CONFIG_BRCMSMAC_LEDS=y
-CONFIG_BRCMFMAC=m
-CONFIG_BRCMFMAC_PROTO_BCDC=y
-CONFIG_BRCMFMAC_PROTO_MSGBUF=y
-CONFIG_BRCMFMAC_SDIO=y
-CONFIG_BRCMFMAC_USB=y
-CONFIG_BRCMFMAC_PCIE=y
-# CONFIG_BRCM_TRACING is not set
-# CONFIG_BRCMDBG is not set
-CONFIG_WLAN_VENDOR_CISCO=y
-CONFIG_WLAN_VENDOR_INTEL=y
-CONFIG_IPW2100=m
-CONFIG_IPW2100_MONITOR=y
-# CONFIG_IPW2100_DEBUG is not set
-CONFIG_IPW2200=m
-CONFIG_IPW2200_MONITOR=y
-CONFIG_IPW2200_RADIOTAP=y
-CONFIG_IPW2200_PROMISCUOUS=y
-CONFIG_IPW2200_QOS=y
-# CONFIG_IPW2200_DEBUG is not set
-CONFIG_LIBIPW=m
-# CONFIG_LIBIPW_DEBUG is not set
-CONFIG_IWLEGACY=m
-CONFIG_IWL4965=m
-CONFIG_IWL3945=m
-
-#
-# iwl3945 / iwl4965 Debugging Options
-#
-# CONFIG_IWLEGACY_DEBUG is not set
-# end of iwl3945 / iwl4965 Debugging Options
-
-CONFIG_IWLWIFI=m
-CONFIG_IWLWIFI_LEDS=y
-CONFIG_IWLDVM=m
-CONFIG_IWLMVM=m
-CONFIG_IWLWIFI_OPMODE_MODULAR=y
-# CONFIG_IWLWIFI_BCAST_FILTERING is not set
-CONFIG_IWLMEI=m
-
-#
-# Debugging Options
-#
-# CONFIG_IWLWIFI_DEBUG is not set
-# CONFIG_IWLWIFI_DEVICE_TRACING is not set
-# end of Debugging Options
-
-CONFIG_WLAN_VENDOR_INTERSIL=y
-CONFIG_HOSTAP=m
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_HOSTAP_PLX=m
-CONFIG_HOSTAP_PCI=m
-CONFIG_HERMES=m
-CONFIG_HERMES_PRISM=y
-CONFIG_HERMES_CACHE_FW_ON_INIT=y
-CONFIG_PLX_HERMES=m
-CONFIG_TMD_HERMES=m
-CONFIG_NORTEL_HERMES=m
-CONFIG_PCI_HERMES=m
-CONFIG_ORINOCO_USB=m
-CONFIG_P54_COMMON=m
-CONFIG_P54_USB=m
-CONFIG_P54_PCI=m
-# CONFIG_P54_SPI is not set
-CONFIG_P54_LEDS=y
-CONFIG_WLAN_VENDOR_MARVELL=y
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_USB=m
-CONFIG_LIBERTAS_SDIO=m
-# CONFIG_LIBERTAS_SPI is not set
-# CONFIG_LIBERTAS_DEBUG is not set
-CONFIG_LIBERTAS_MESH=y
-CONFIG_LIBERTAS_THINFIRM=m
-# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
-CONFIG_LIBERTAS_THINFIRM_USB=m
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
-CONFIG_MWIFIEX_PCIE=m
-CONFIG_MWIFIEX_USB=m
-CONFIG_MWL8K=m
-CONFIG_WLAN_VENDOR_MEDIATEK=y
-CONFIG_MT7601U=m
-CONFIG_MT76_CORE=m
-CONFIG_MT76_LEDS=y
-CONFIG_MT76_USB=m
-CONFIG_MT76_SDIO=m
-CONFIG_MT76x02_LIB=m
-CONFIG_MT76x02_USB=m
-CONFIG_MT76_CONNAC_LIB=m
-CONFIG_MT76x0_COMMON=m
-CONFIG_MT76x0U=m
-CONFIG_MT76x0E=m
-CONFIG_MT76x2_COMMON=m
-CONFIG_MT76x2E=m
-CONFIG_MT76x2U=m
-CONFIG_MT7603E=m
-CONFIG_MT7615_COMMON=m
-CONFIG_MT7615E=m
-CONFIG_MT7622_WMAC=y
-CONFIG_MT7663_USB_SDIO_COMMON=m
-CONFIG_MT7663U=m
-CONFIG_MT7663S=m
-CONFIG_MT7915E=m
-CONFIG_MT7986_WMAC=y
-CONFIG_MT7921_COMMON=m
-CONFIG_MT7921E=m
-# CONFIG_MT7921S is not set
-CONFIG_MT7921U=m
-CONFIG_WLAN_VENDOR_MICROCHIP=y
-# CONFIG_WILC1000_SDIO is not set
-# CONFIG_WILC1000_SPI is not set
-CONFIG_WLAN_VENDOR_RALINK=y
-CONFIG_RT2X00=m
-CONFIG_RT2400PCI=m
-CONFIG_RT2500PCI=m
-CONFIG_RT61PCI=m
-CONFIG_RT2800PCI=m
-CONFIG_RT2800PCI_RT33XX=y
-CONFIG_RT2800PCI_RT35XX=y
-CONFIG_RT2800PCI_RT53XX=y
-CONFIG_RT2800PCI_RT3290=y
-CONFIG_RT2500USB=m
-CONFIG_RT73USB=m
-CONFIG_RT2800USB=m
-CONFIG_RT2800USB_RT33XX=y
-CONFIG_RT2800USB_RT35XX=y
-CONFIG_RT2800USB_RT3573=y
-CONFIG_RT2800USB_RT53XX=y
-CONFIG_RT2800USB_RT55XX=y
-CONFIG_RT2800USB_UNKNOWN=y
-CONFIG_RT2800_LIB=m
-CONFIG_RT2800_LIB_MMIO=m
-CONFIG_RT2X00_LIB_MMIO=m
-CONFIG_RT2X00_LIB_PCI=m
-CONFIG_RT2X00_LIB_USB=m
-CONFIG_RT2X00_LIB=m
-CONFIG_RT2X00_LIB_FIRMWARE=y
-CONFIG_RT2X00_LIB_CRYPTO=y
-CONFIG_RT2X00_LIB_LEDS=y
-# CONFIG_RT2X00_DEBUG is not set
-CONFIG_WLAN_VENDOR_REALTEK=y
-CONFIG_RTL8180=m
-CONFIG_RTL8187=m
-CONFIG_RTL8187_LEDS=y
-CONFIG_RTL_CARDS=m
-CONFIG_RTL8192CE=m
-CONFIG_RTL8192SE=m
-CONFIG_RTL8192DE=m
-CONFIG_RTL8723AE=m
-CONFIG_RTL8723BE=m
-CONFIG_RTL8188EE=m
-CONFIG_RTL8192EE=m
-CONFIG_RTL8821AE=m
-CONFIG_RTL8192CU=m
-CONFIG_RTLWIFI=m
-CONFIG_RTLWIFI_PCI=m
-CONFIG_RTLWIFI_USB=m
-# CONFIG_RTLWIFI_DEBUG is not set
-CONFIG_RTL8192C_COMMON=m
-CONFIG_RTL8723_COMMON=m
-CONFIG_RTLBTCOEXIST=m
-CONFIG_RTL8XXXU=m
-CONFIG_RTL8XXXU_UNTESTED=y
-CONFIG_RTW88=m
-CONFIG_RTW88_CORE=m
-CONFIG_RTW88_PCI=m
-CONFIG_RTW88_8822B=m
-CONFIG_RTW88_8822C=m
-CONFIG_RTW88_8723D=m
-CONFIG_RTW88_8821C=m
-CONFIG_RTW88_8822BE=m
-CONFIG_RTW88_8822CE=m
-CONFIG_RTW88_8723DE=m
-CONFIG_RTW88_8821CE=m
-# CONFIG_RTW88_DEBUG is not set
-# CONFIG_RTW88_DEBUGFS is not set
-CONFIG_RTW89=m
-CONFIG_RTW89_CORE=m
-CONFIG_RTW89_PCI=m
-CONFIG_RTW89_8852AE=m
-# CONFIG_RTW89_DEBUGMSG is not set
-# CONFIG_RTW89_DEBUGFS is not set
-CONFIG_WLAN_VENDOR_RSI=y
-CONFIG_RSI_91X=m
-# CONFIG_RSI_DEBUGFS is not set
-CONFIG_RSI_SDIO=m
-CONFIG_RSI_USB=m
-CONFIG_RSI_COEX=y
-CONFIG_WLAN_VENDOR_ST=y
-CONFIG_CW1200=m
-CONFIG_CW1200_WLAN_SDIO=m
-# CONFIG_CW1200_WLAN_SPI is not set
-CONFIG_WLAN_VENDOR_TI=y
-CONFIG_WL1251=m
-# CONFIG_WL1251_SPI is not set
-CONFIG_WL1251_SDIO=m
-CONFIG_WL12XX=m
-CONFIG_WL18XX=m
-CONFIG_WLCORE=m
-# CONFIG_WLCORE_SPI is not set
-CONFIG_WLCORE_SDIO=m
-# CONFIG_WILINK_PLATFORM_DATA is not set
-CONFIG_WLAN_VENDOR_ZYDAS=y
-CONFIG_USB_ZD1201=m
-CONFIG_ZD1211RW=m
-# CONFIG_ZD1211RW_DEBUG is not set
-CONFIG_WLAN_VENDOR_QUANTENNA=y
-CONFIG_QTNFMAC=m
-CONFIG_QTNFMAC_PCIE=m
-CONFIG_MAC80211_HWSIM=m
-CONFIG_USB_NET_RNDIS_WLAN=m
-CONFIG_VIRT_WIFI=m
-CONFIG_WAN=y
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_PCI200SYN=m
-CONFIG_WANXL=m
-CONFIG_PC300TOO=m
-CONFIG_FARSYNC=m
-CONFIG_FSL_UCC_HDLC=m
-CONFIG_SLIC_DS26522=m
-CONFIG_LAPBETHER=m
-CONFIG_IEEE802154_DRIVERS=m
-CONFIG_IEEE802154_FAKELB=m
-# CONFIG_IEEE802154_AT86RF230 is not set
-# CONFIG_IEEE802154_MRF24J40 is not set
-# CONFIG_IEEE802154_CC2520 is not set
-# CONFIG_IEEE802154_ATUSB is not set
-CONFIG_IEEE802154_ADF7242=m
-CONFIG_IEEE802154_CA8210=m
-# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
-CONFIG_IEEE802154_MCR20A=m
-CONFIG_IEEE802154_HWSIM=m
-
-#
-# Wireless WAN
-#
-CONFIG_WWAN=y
-CONFIG_WWAN_HWSIM=m
-CONFIG_MHI_WWAN_CTRL=m
-CONFIG_IOSM=m
-CONFIG_MHI_WWAN_MBIM=m
-CONFIG_QCOM_BAM_DMUX=m
-CONFIG_RPMSG_WWAN_CTRL=m
-# end of Wireless WAN
-
-CONFIG_VMXNET3=m
-# CONFIG_FUJITSU_ES is not set
-CONFIG_USB4_NET=m
-CONFIG_HYPERV_NET=m
-CONFIG_NETDEVSIM=m
-CONFIG_NET_FAILOVER=m
-CONFIG_ISDN=y
-CONFIG_ISDN_CAPI=y
-CONFIG_CAPI_TRACE=y
-CONFIG_ISDN_CAPI_MIDDLEWARE=y
-CONFIG_MISDN=m
-CONFIG_MISDN_DSP=m
-CONFIG_MISDN_L1OIP=m
-
-#
-# mISDN hardware drivers
-#
-CONFIG_MISDN_HFCPCI=m
-CONFIG_MISDN_HFCMULTI=m
-CONFIG_MISDN_HFCUSB=m
-CONFIG_MISDN_AVMFRITZ=m
-CONFIG_MISDN_SPEEDFAX=m
-# CONFIG_MISDN_INFINEON is not set
-# CONFIG_MISDN_W6692 is not set
-# CONFIG_MISDN_NETJET is not set
-CONFIG_MISDN_IPAC=m
-CONFIG_MISDN_ISAR=m
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_LEDS=y
-CONFIG_INPUT_FF_MEMLESS=m
-CONFIG_INPUT_SPARSEKMAP=m
-CONFIG_INPUT_MATRIXKMAP=m
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ADC is not set
-CONFIG_KEYBOARD_ADP5588=m
-CONFIG_KEYBOARD_ADP5589=m
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_KEYBOARD_QT1050=m
-CONFIG_KEYBOARD_QT1070=m
-CONFIG_KEYBOARD_QT2160=m
-CONFIG_KEYBOARD_DLINK_DIR685=m
-# CONFIG_KEYBOARD_LKKBD is not set
-CONFIG_KEYBOARD_GPIO=m
-CONFIG_KEYBOARD_GPIO_POLLED=m
-CONFIG_KEYBOARD_TCA6416=m
-CONFIG_KEYBOARD_TCA8418=m
-CONFIG_KEYBOARD_MATRIX=m
-CONFIG_KEYBOARD_LM8323=m
-CONFIG_KEYBOARD_LM8333=m
-CONFIG_KEYBOARD_MAX7359=m
-CONFIG_KEYBOARD_MCS=m
-CONFIG_KEYBOARD_MPR121=m
-CONFIG_KEYBOARD_SNVS_PWRKEY=m
-CONFIG_KEYBOARD_IMX=m
-CONFIG_KEYBOARD_IMX_SC_KEY=m
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_TEGRA=m
-CONFIG_KEYBOARD_OPENCORES=m
-CONFIG_KEYBOARD_PINEPHONE=m
-# CONFIG_KEYBOARD_SAMSUNG is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_SUN4I_LRADC=m
-CONFIG_KEYBOARD_IQS62X=m
-# CONFIG_KEYBOARD_OMAP4 is not set
-CONFIG_KEYBOARD_TM2_TOUCHKEY=m
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_KEYBOARD_CROS_EC=m
-CONFIG_KEYBOARD_CAP11XX=m
-# CONFIG_KEYBOARD_BCM is not set
-CONFIG_KEYBOARD_MT6779=m
-# CONFIG_KEYBOARD_CYPRESS_SF is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_JOYSTICK=y
-# CONFIG_JOYSTICK_ANALOG is not set
-# CONFIG_JOYSTICK_A3D is not set
-CONFIG_JOYSTICK_ADC=m
-# CONFIG_JOYSTICK_ADI is not set
-# CONFIG_JOYSTICK_COBRA is not set
-# CONFIG_JOYSTICK_GF2K is not set
-# CONFIG_JOYSTICK_GRIP is not set
-# CONFIG_JOYSTICK_GRIP_MP is not set
-# CONFIG_JOYSTICK_GUILLEMOT is not set
-# CONFIG_JOYSTICK_INTERACT is not set
-# CONFIG_JOYSTICK_SIDEWINDER is not set
-# CONFIG_JOYSTICK_TMDC is not set
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=m
-CONFIG_JOYSTICK_IFORCE_232=m
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_TWIDJOY=m
-CONFIG_JOYSTICK_ZHENHUA=m
-CONFIG_JOYSTICK_DB9=m
-CONFIG_JOYSTICK_GAMECON=m
-CONFIG_JOYSTICK_TURBOGRAFX=m
-CONFIG_JOYSTICK_AS5011=m
-# CONFIG_JOYSTICK_JOYDUMP is not set
-CONFIG_JOYSTICK_XPAD=m
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_JOYSTICK_WALKERA0701=m
-CONFIG_JOYSTICK_PSXPAD_SPI=m
-CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
-CONFIG_JOYSTICK_PXRC=m
-CONFIG_JOYSTICK_QWIIC=m
-CONFIG_JOYSTICK_FSIA6B=m
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=m
-CONFIG_TABLET_USB_AIPTEK=m
-CONFIG_TABLET_USB_HANWANG=m
-CONFIG_TABLET_USB_KBTAB=m
-CONFIG_TABLET_USB_PEGASUS=m
-CONFIG_TABLET_SERIAL_WACOM4=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=m
-# CONFIG_TOUCHSCREEN_AD7877 is not set
-CONFIG_TOUCHSCREEN_AD7879=m
-CONFIG_TOUCHSCREEN_AD7879_I2C=m
-# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
-CONFIG_TOUCHSCREEN_ADC=m
-CONFIG_TOUCHSCREEN_AR1021_I2C=m
-CONFIG_TOUCHSCREEN_ATMEL_MXT=m
-CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y
-CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
-CONFIG_TOUCHSCREEN_BU21013=m
-CONFIG_TOUCHSCREEN_BU21029=m
-CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
-CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
-CONFIG_TOUCHSCREEN_CY8CTMA140=m
-CONFIG_TOUCHSCREEN_CY8CTMG110=m
-CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
-# CONFIG_TOUCHSCREEN_CYTTSP_SPI is not set
-CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
-# CONFIG_TOUCHSCREEN_CYTTSP4_SPI is not set
-CONFIG_TOUCHSCREEN_DYNAPRO=m
-CONFIG_TOUCHSCREEN_HAMPSHIRE=m
-CONFIG_TOUCHSCREEN_EETI=m
-# CONFIG_TOUCHSCREEN_EGALAX is not set
-CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
-CONFIG_TOUCHSCREEN_EXC3000=m
-CONFIG_TOUCHSCREEN_FUJITSU=m
-CONFIG_TOUCHSCREEN_GOODIX=m
-CONFIG_TOUCHSCREEN_HIDEEP=m
-CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
-CONFIG_TOUCHSCREEN_ILI210X=m
-CONFIG_TOUCHSCREEN_ILITEK=m
-CONFIG_TOUCHSCREEN_IPROC=m
-CONFIG_TOUCHSCREEN_S6SY761=m
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_TOUCHSCREEN_EKTF2127=m
-CONFIG_TOUCHSCREEN_ELAN=m
-CONFIG_TOUCHSCREEN_ELO=m
-CONFIG_TOUCHSCREEN_WACOM_W8001=m
-CONFIG_TOUCHSCREEN_WACOM_I2C=m
-CONFIG_TOUCHSCREEN_MAX11801=m
-CONFIG_TOUCHSCREEN_MCS5000=m
-CONFIG_TOUCHSCREEN_MMS114=m
-CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
-CONFIG_TOUCHSCREEN_MSG2638=m
-CONFIG_TOUCHSCREEN_MTOUCH=m
-CONFIG_TOUCHSCREEN_IMAGIS=m
-# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
-CONFIG_TOUCHSCREEN_INEXIO=m
-CONFIG_TOUCHSCREEN_MK712=m
-CONFIG_TOUCHSCREEN_PENMOUNT=m
-CONFIG_TOUCHSCREEN_EDT_FT5X06=m
-CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m
-CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
-CONFIG_TOUCHSCREEN_TOUCHWIN=m
-# CONFIG_TOUCHSCREEN_TI_AM335X_TSC is not set
-CONFIG_TOUCHSCREEN_PIXCIR=m
-CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
-CONFIG_TOUCHSCREEN_WM97XX=m
-CONFIG_TOUCHSCREEN_WM9705=y
-CONFIG_TOUCHSCREEN_WM9712=y
-CONFIG_TOUCHSCREEN_WM9713=y
-CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-CONFIG_TOUCHSCREEN_USB_EGALAX=y
-CONFIG_TOUCHSCREEN_USB_PANJIT=y
-CONFIG_TOUCHSCREEN_USB_3M=y
-CONFIG_TOUCHSCREEN_USB_ITM=y
-CONFIG_TOUCHSCREEN_USB_ETURBO=y
-CONFIG_TOUCHSCREEN_USB_GUNZE=y
-CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
-CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
-CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
-CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
-CONFIG_TOUCHSCREEN_USB_GOTOP=y
-CONFIG_TOUCHSCREEN_USB_JASTEC=y
-CONFIG_TOUCHSCREEN_USB_ELO=y
-CONFIG_TOUCHSCREEN_USB_E2I=y
-CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
-CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
-CONFIG_TOUCHSCREEN_USB_NEXIO=y
-CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
-CONFIG_TOUCHSCREEN_TOUCHIT213=m
-CONFIG_TOUCHSCREEN_TSC_SERIO=m
-CONFIG_TOUCHSCREEN_TSC200X_CORE=m
-CONFIG_TOUCHSCREEN_TSC2004=m
-# CONFIG_TOUCHSCREEN_TSC2005 is not set
-CONFIG_TOUCHSCREEN_TSC2007=m
-CONFIG_TOUCHSCREEN_TSC2007_IIO=y
-CONFIG_TOUCHSCREEN_RM_TS=m
-CONFIG_TOUCHSCREEN_SILEAD=m
-CONFIG_TOUCHSCREEN_SIS_I2C=m
-CONFIG_TOUCHSCREEN_ST1232=m
-CONFIG_TOUCHSCREEN_STMFTS=m
-CONFIG_TOUCHSCREEN_SUN4I=m
-CONFIG_TOUCHSCREEN_SUR40=m
-# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
-CONFIG_TOUCHSCREEN_SX8654=m
-CONFIG_TOUCHSCREEN_TPS6507X=m
-CONFIG_TOUCHSCREEN_ZET6223=m
-CONFIG_TOUCHSCREEN_ZFORCE=m
-CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
-CONFIG_TOUCHSCREEN_ROHM_BU21023=m
-CONFIG_TOUCHSCREEN_IQS5XX=m
-CONFIG_TOUCHSCREEN_ZINITIX=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_AD714X=m
-CONFIG_INPUT_AD714X_I2C=m
-# CONFIG_INPUT_AD714X_SPI is not set
-CONFIG_INPUT_ATC260X_ONKEY=m
-CONFIG_INPUT_ATMEL_CAPTOUCH=m
-CONFIG_INPUT_BMA150=m
-# CONFIG_INPUT_E3X0_BUTTON is not set
-CONFIG_INPUT_PM8941_PWRKEY=m
-CONFIG_INPUT_PM8XXX_VIBRATOR=m
-CONFIG_INPUT_MAX77650_ONKEY=m
-CONFIG_INPUT_MMA8450=m
-# CONFIG_INPUT_GPIO_BEEPER is not set
-CONFIG_INPUT_GPIO_DECODER=m
-CONFIG_INPUT_GPIO_VIBRA=m
-CONFIG_INPUT_CPCAP_PWRBUTTON=m
-CONFIG_INPUT_ATI_REMOTE2=m
-CONFIG_INPUT_KEYSPAN_REMOTE=m
-CONFIG_INPUT_KXTJ9=m
-CONFIG_INPUT_POWERMATE=m
-CONFIG_INPUT_YEALINK=m
-CONFIG_INPUT_CM109=m
-CONFIG_INPUT_REGULATOR_HAPTIC=m
-CONFIG_INPUT_AXP20X_PEK=m
-CONFIG_INPUT_UINPUT=m
-CONFIG_INPUT_PCF8574=m
-CONFIG_INPUT_PWM_BEEPER=m
-CONFIG_INPUT_PWM_VIBRA=m
-CONFIG_INPUT_RK805_PWRKEY=m
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-CONFIG_INPUT_DA7280_HAPTICS=m
-CONFIG_INPUT_ADXL34X=m
-CONFIG_INPUT_IBM_PANEL=m
-CONFIG_INPUT_ADXL34X_I2C=m
-CONFIG_INPUT_ADXL34X_SPI=m
-CONFIG_INPUT_IMS_PCU=m
-CONFIG_INPUT_IQS269A=m
-CONFIG_INPUT_IQS626A=m
-CONFIG_INPUT_CMA3000=m
-CONFIG_INPUT_CMA3000_I2C=m
-CONFIG_INPUT_SOC_BUTTON_ARRAY=m
-CONFIG_INPUT_DRV260X_HAPTICS=m
-CONFIG_INPUT_DRV2665_HAPTICS=m
-CONFIG_INPUT_DRV2667_HAPTICS=m
-CONFIG_INPUT_HISI_POWERKEY=m
-CONFIG_INPUT_RT5120_PWRKEY=m
-CONFIG_INPUT_SC27XX_VIBRA=m
-CONFIG_INPUT_STPMIC1_ONKEY=m
-CONFIG_RMI4_CORE=m
-CONFIG_RMI4_I2C=m
-CONFIG_RMI4_SPI=m
-CONFIG_RMI4_SMB=m
-CONFIG_RMI4_F03=y
-CONFIG_RMI4_F03_SERIO=m
-CONFIG_RMI4_2D_SENSOR=y
-CONFIG_RMI4_F11=y
-CONFIG_RMI4_F12=y
-CONFIG_RMI4_F30=y
-CONFIG_RMI4_F34=y
-CONFIG_RMI4_F3A=y
-CONFIG_RMI4_F54=y
-CONFIG_RMI4_F55=y
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=m
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_PARKBD=m
-# CONFIG_SERIO_AMBAKMI is not set
-CONFIG_SERIO_PCIPS2=m
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_RAW=m
-CONFIG_SERIO_ALTERA_PS2=m
-CONFIG_SERIO_PS2MULT=m
-# CONFIG_SERIO_ARC_PS2 is not set
-CONFIG_SERIO_APBPS2=m
-CONFIG_HYPERV_KEYBOARD=m
-# CONFIG_SERIO_SUN4I_PS2 is not set
-CONFIG_SERIO_GPIO_PS2=m
-CONFIG_USERIO=m
-# CONFIG_GAMEPORT is not set
-# end of Hardware I/O ports
-# end of Input device support
-
-#
-# Character devices
-#
-CONFIG_TTY=y
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=0
-CONFIG_LDISC_AUTOLOAD=y
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_EARLYCON=y
-CONFIG_SERIAL_8250=y
-# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-CONFIG_SERIAL_8250_PNP=y
-# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
-# CONFIG_SERIAL_8250_FINTEK is not set
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_DMA=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_NR_UARTS=32
-CONFIG_SERIAL_8250_RUNTIME_UARTS=32
-CONFIG_SERIAL_8250_EXTENDED=y
-# CONFIG_SERIAL_8250_MANY_PORTS is not set
-# CONFIG_SERIAL_8250_ASPEED_VUART is not set
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_BCM2835AUX=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_EM=m
-# CONFIG_SERIAL_8250_RT288X is not set
-CONFIG_SERIAL_8250_OMAP=m
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_UNIPHIER=m
-CONFIG_SERIAL_8250_TEGRA=y
-CONFIG_SERIAL_8250_BCM7271=y
-CONFIG_SERIAL_OF_PLATFORM=y
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_AMBA_PL010=y
-CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
-# CONFIG_SERIAL_KGDB_NMI is not set
-CONFIG_SERIAL_MESON=y
-CONFIG_SERIAL_MESON_CONSOLE=y
-CONFIG_SERIAL_SAMSUNG=y
-CONFIG_SERIAL_SAMSUNG_UARTS_4=y
-CONFIG_SERIAL_SAMSUNG_UARTS=4
-CONFIG_SERIAL_SAMSUNG_CONSOLE=y
-CONFIG_SERIAL_TEGRA=m
-CONFIG_SERIAL_TEGRA_TCU=m
-# CONFIG_SERIAL_MAX3100 is not set
-# CONFIG_SERIAL_MAX310X is not set
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-CONFIG_SERIAL_IMX_EARLYCON=y
-# CONFIG_SERIAL_UARTLITE is not set
-CONFIG_SERIAL_SH_SCI=m
-CONFIG_SERIAL_SH_SCI_NR_UARTS=18
-CONFIG_SERIAL_SH_SCI_DMA=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_CONSOLE_POLL=y
-CONFIG_SERIAL_JSM=m
-CONFIG_SERIAL_MSM=y
-CONFIG_SERIAL_MSM_CONSOLE=y
-CONFIG_SERIAL_QCOM_GENI=y
-CONFIG_SERIAL_QCOM_GENI_CONSOLE=y
-# CONFIG_SERIAL_SIFIVE is not set
-# CONFIG_SERIAL_QE is not set
-# CONFIG_SERIAL_SCCNXP is not set
-CONFIG_SERIAL_SC16IS7XX_CORE=m
-CONFIG_SERIAL_SC16IS7XX=m
-CONFIG_SERIAL_SC16IS7XX_I2C=y
-CONFIG_SERIAL_SC16IS7XX_SPI=y
-CONFIG_SERIAL_BCM63XX=m
-# CONFIG_SERIAL_ALTERA_JTAGUART is not set
-# CONFIG_SERIAL_ALTERA_UART is not set
-CONFIG_SERIAL_XILINX_PS_UART=y
-CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
-# CONFIG_SERIAL_ARC is not set
-CONFIG_SERIAL_RP2=m
-CONFIG_SERIAL_RP2_NR_UARTS=32
-CONFIG_SERIAL_FSL_LPUART=m
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_FSL_LINFLEXUART=y
-CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
-# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
-CONFIG_SERIAL_SPRD=y
-CONFIG_SERIAL_SPRD_CONSOLE=y
-CONFIG_SERIAL_MVEBU_UART=y
-CONFIG_SERIAL_MVEBU_CONSOLE=y
-CONFIG_SERIAL_OWL=y
-CONFIG_SERIAL_OWL_CONSOLE=y
-# end of Serial drivers
-
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_MOXA_INTELLIO=m
-CONFIG_MOXA_SMARTIO=m
-CONFIG_SYNCLINK_GT=m
-CONFIG_N_HDLC=m
-CONFIG_N_GSM=m
-CONFIG_NOZOMI=m
-CONFIG_NULL_TTY=m
-CONFIG_HVC_DRIVER=y
-# CONFIG_HVC_DCC is not set
-# CONFIG_RPMSG_TTY is not set
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-# CONFIG_TTY_PRINTK is not set
-CONFIG_PRINTER=m
-# CONFIG_LP_CONSOLE is not set
-CONFIG_PPDEV=m
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_IPMI_HANDLER=m
-CONFIG_IPMI_DMI_DECODE=y
-CONFIG_IPMI_PLAT_DATA=y
-CONFIG_IPMI_PANIC_EVENT=y
-# CONFIG_IPMI_PANIC_STRING is not set
-CONFIG_IPMI_DEVICE_INTERFACE=m
-CONFIG_IPMI_SI=m
-CONFIG_IPMI_SSIF=m
-# CONFIG_IPMI_IPMB is not set
-CONFIG_IPMI_WATCHDOG=m
-CONFIG_IPMI_POWEROFF=m
-CONFIG_NPCM7XX_KCS_IPMI_BMC=m
-CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m
-CONFIG_IPMI_KCS_BMC_SERIO=m
-CONFIG_IPMB_DEVICE_INTERFACE=m
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=m
-CONFIG_HW_RANDOM_BA431=m
-CONFIG_HW_RANDOM_BCM2835=m
-CONFIG_HW_RANDOM_IPROC_RNG200=m
-CONFIG_HW_RANDOM_OMAP=m
-CONFIG_HW_RANDOM_VIRTIO=m
-CONFIG_HW_RANDOM_HISI=m
-CONFIG_HW_RANDOM_XGENE=m
-CONFIG_HW_RANDOM_ROCKCHIP=y
-CONFIG_HW_RANDOM_MESON=m
-CONFIG_HW_RANDOM_CAVIUM=m
-CONFIG_HW_RANDOM_MTK=m
-CONFIG_HW_RANDOM_EXYNOS=m
-CONFIG_HW_RANDOM_OPTEE=m
-CONFIG_HW_RANDOM_NPCM=m
-CONFIG_HW_RANDOM_CCTRNG=m
-CONFIG_HW_RANDOM_XIPHERA=m
-CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
-CONFIG_HW_RANDOM_CN10K=m
-CONFIG_APPLICOM=m
-CONFIG_DEVMEM=y
-CONFIG_DEVPORT=y
-CONFIG_TCG_TPM=y
-CONFIG_HW_RANDOM_TPM=y
-CONFIG_TCG_TIS_CORE=y
-CONFIG_TCG_TIS=y
-CONFIG_TCG_TIS_SPI=m
-CONFIG_TCG_TIS_SPI_CR50=y
-CONFIG_TCG_TIS_SYNQUACER=m
-CONFIG_TCG_TIS_I2C_CR50=m
-CONFIG_TCG_TIS_I2C_ATMEL=m
-CONFIG_TCG_TIS_I2C_INFINEON=m
-CONFIG_TCG_TIS_I2C_NUVOTON=m
-CONFIG_TCG_ATMEL=m
-CONFIG_TCG_INFINEON=m
-CONFIG_TCG_CRB=y
-CONFIG_TCG_VTPM_PROXY=m
-CONFIG_TCG_FTPM_TEE=m
-CONFIG_TCG_TIS_ST33ZP24=m
-CONFIG_TCG_TIS_ST33ZP24_I2C=m
-CONFIG_TCG_TIS_ST33ZP24_SPI=m
-CONFIG_XILLYBUS_CLASS=m
-CONFIG_XILLYBUS=m
-CONFIG_XILLYBUS_PCIE=m
-CONFIG_XILLYBUS_OF=m
-CONFIG_XILLYUSB=m
-CONFIG_RANDOM_TRUST_CPU=y
-CONFIG_RANDOM_TRUST_BOOTLOADER=y
-# end of Character devices
-
-#
-# I2C support
-#
-CONFIG_I2C=y
-CONFIG_ACPI_I2C_OPREGION=y
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_MUX=m
-
-#
-# Multiplexer I2C Chip support
-#
-# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
-CONFIG_I2C_MUX_GPIO=m
-CONFIG_I2C_MUX_GPMUX=m
-CONFIG_I2C_MUX_LTC4306=m
-CONFIG_I2C_MUX_PCA9541=m
-CONFIG_I2C_MUX_PCA954x=m
-CONFIG_I2C_MUX_PINCTRL=m
-CONFIG_PINCTRL_AMD=y
-CONFIG_I2C_MUX_REG=m
-CONFIG_I2C_DEMUX_PINCTRL=m
-CONFIG_I2C_MUX_MLXCPLD=m
-# end of Multiplexer I2C Chip support
-
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_SMBUS=m
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALGOPCA=m
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# PC SMBus host controller drivers
-#
-CONFIG_I2C_ALI1535=m
-CONFIG_I2C_ALI1563=m
-CONFIG_I2C_ALI15X3=m
-CONFIG_I2C_AMD756=m
-CONFIG_I2C_AMD8111=m
-# CONFIG_I2C_AMD_MP2 is not set
-CONFIG_I2C_HIX5HD2=m
-CONFIG_I2C_I801=m
-CONFIG_I2C_ISCH=m
-CONFIG_I2C_PIIX4=m
-# CONFIG_I2C_NFORCE2 is not set
-# CONFIG_I2C_NVIDIA_GPU is not set
-CONFIG_I2C_SIS5595=m
-CONFIG_I2C_SIS630=m
-CONFIG_I2C_SIS96X=m
-# CONFIG_I2C_VIA is not set
-CONFIG_I2C_VIAPRO=m
-
-#
-# ACPI drivers
-#
-# CONFIG_I2C_SCMI is not set
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-CONFIG_I2C_ALTERA=m
-CONFIG_I2C_BCM2835=m
-CONFIG_I2C_BCM_IPROC=m
-CONFIG_I2C_BRCMSTB=m
-CONFIG_I2C_CADENCE=m
-CONFIG_I2C_CBUS_GPIO=m
-CONFIG_I2C_DESIGNWARE_CORE=y
-CONFIG_I2C_DESIGNWARE_SLAVE=y
-CONFIG_I2C_DESIGNWARE_PLATFORM=y
-CONFIG_I2C_DESIGNWARE_AMDPSP=y
-CONFIG_I2C_DESIGNWARE_PCI=m
-# CONFIG_I2C_EMEV2 is not set
-# CONFIG_I2C_EXYNOS5 is not set
-CONFIG_I2C_GPIO=m
-# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
-CONFIG_I2C_HISI=m
-CONFIG_I2C_IMX=m
-CONFIG_I2C_IMX_LPI2C=m
-CONFIG_I2C_KEMPLD=m
-CONFIG_I2C_MLXBF=m
-CONFIG_I2C_MESON=m
-CONFIG_I2C_MT65XX=m
-CONFIG_I2C_MV64XXX=m
-# CONFIG_I2C_NOMADIK is not set
-CONFIG_I2C_OCORES=m
-CONFIG_I2C_OMAP=m
-CONFIG_I2C_OWL=m
-CONFIG_I2C_APPLE=y
-CONFIG_I2C_PCA_PLATFORM=m
-CONFIG_I2C_PXA=m
-# CONFIG_I2C_PXA_SLAVE is not set
-CONFIG_I2C_QCOM_CCI=m
-CONFIG_I2C_QCOM_GENI=m
-CONFIG_I2C_QUP=m
-CONFIG_I2C_RIIC=m
-CONFIG_I2C_RK3X=m
-CONFIG_I2C_S3C2410=m
-CONFIG_I2C_SH_MOBILE=m
-# CONFIG_I2C_SIMTEC is not set
-CONFIG_I2C_SPRD=y
-CONFIG_I2C_SYNQUACER=m
-CONFIG_I2C_TEGRA=m
-CONFIG_I2C_TEGRA_BPMP=m
-CONFIG_I2C_UNIPHIER=m
-CONFIG_I2C_UNIPHIER_F=m
-# CONFIG_I2C_VERSATILE is not set
-CONFIG_I2C_THUNDERX=m
-CONFIG_I2C_XILINX=m
-CONFIG_I2C_XLP9XX=m
-CONFIG_I2C_RCAR=m
-
-#
-# External I2C/SMBus adapter drivers
-#
-CONFIG_I2C_DIOLAN_U2C=m
-CONFIG_I2C_DLN2=m
-CONFIG_I2C_CP2615=m
-CONFIG_I2C_PARPORT=m
-CONFIG_I2C_PCI1XXXX=m
-CONFIG_I2C_ROBOTFUZZ_OSIF=m
-CONFIG_I2C_TAOS_EVM=m
-CONFIG_I2C_TINY_USB=m
-CONFIG_I2C_VIPERBOARD=m
-
-#
-# Other I2C/SMBus bus drivers
-#
-CONFIG_I2C_CROS_EC_TUNNEL=m
-CONFIG_I2C_XGENE_SLIMPRO=m
-CONFIG_I2C_VIRTIO=m
-# end of I2C Hardware Bus support
-
-CONFIG_I2C_STUB=m
-CONFIG_I2C_SLAVE=y
-CONFIG_I2C_SLAVE_EEPROM=m
-# CONFIG_I2C_SLAVE_TESTUNIT is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# end of I2C support
-
-CONFIG_I3C=m
-CONFIG_CDNS_I3C_MASTER=m
-CONFIG_DW_I3C_MASTER=m
-CONFIG_SVC_I3C_MASTER=m
-CONFIG_MIPI_I3C_HCI=m
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_ALTERA is not set
-CONFIG_SPI_ALTERA_CORE=m
-CONFIG_SPI_ALTERA_DFL=m
-CONFIG_SPI_ARMADA_3700=m
-# CONFIG_SPI_AXI_SPI_ENGINE is not set
-CONFIG_SPI_BCM2835=m
-CONFIG_SPI_BCM2835AUX=m
-CONFIG_SPI_BCM_QSPI=m
-CONFIG_SPI_BITBANG=m
-# CONFIG_SPI_BUTTERFLY is not set
-CONFIG_SPI_CADENCE=m
-CONFIG_SPI_CADENCE_QUADSPI=m
-# CONFIG_SPI_CADENCE_XSPI is not set
-CONFIG_SPI_DESIGNWARE=m
-CONFIG_SPI_DW_DMA=y
-CONFIG_SPI_DW_PCI=m
-CONFIG_SPI_DW_MMIO=m
-CONFIG_SPI_DLN2=m
-CONFIG_SPI_FSL_LPSPI=m
-CONFIG_SPI_FSL_QUADSPI=m
-CONFIG_SPI_HISI_KUNPENG=m
-CONFIG_SPI_HISI_SFC_V3XX=m
-CONFIG_SPI_NXP_FLEXSPI=m
-CONFIG_SPI_GPIO=m
-CONFIG_SPI_IMX=m
-# CONFIG_SPI_LM70_LLP is not set
-CONFIG_SPI_FSL_LIB=y
-CONFIG_SPI_FSL_SPI=y
-CONFIG_SPI_FSL_DSPI=m
-CONFIG_SPI_MESON_SPICC=m
-# CONFIG_SPI_MESON_SPIFC is not set
-CONFIG_SPI_MT65XX=m
-CONFIG_SPI_MTK_NOR=m
-CONFIG_SPI_OC_TINY=m
-CONFIG_SPI_OMAP24XX=m
-CONFIG_SPI_ORION=m
-CONFIG_SPI_PL022=m
-# CONFIG_SPI_PXA2XX is not set
-CONFIG_SPI_ROCKCHIP=m
-# CONFIG_SPI_ROCKCHIP_SFC is not set
-CONFIG_SPI_RPCIF=m
-CONFIG_SPI_RSPI=m
-CONFIG_SPI_QCOM_QSPI=m
-CONFIG_SPI_QUP=m
-CONFIG_SPI_QCOM_GENI=m
-CONFIG_SPI_S3C64XX=m
-CONFIG_SPI_SC18IS602=m
-CONFIG_SPI_SH_MSIOF=m
-CONFIG_SPI_SH_HSPI=m
-CONFIG_SPI_SIFIVE=m
-CONFIG_SPI_SLAVE_MT27XX=m
-CONFIG_SPI_SPRD=m
-CONFIG_SPI_SPRD_ADI=m
-CONFIG_SPI_SUN4I=m
-CONFIG_SPI_SUN6I=m
-CONFIG_SPI_SYNQUACER=m
-CONFIG_SPI_MXIC=m
-CONFIG_SPI_TEGRA210_QUAD=m
-CONFIG_SPI_TEGRA114=m
-CONFIG_SPI_TEGRA20_SFLASH=m
-CONFIG_SPI_TEGRA20_SLINK=m
-CONFIG_SPI_THUNDERX=m
-CONFIG_SPI_UNIPHIER=m
-CONFIG_SPI_XCOMM=m
-CONFIG_SPI_XILINX=m
-CONFIG_SPI_XLP=m
-CONFIG_SPI_ZYNQMP_GQSPI=m
-# CONFIG_SPI_AMD is not set
-
-#
-# SPI Multiplexer support
-#
-CONFIG_SPI_MUX=m
-
-#
-# SPI Protocol Masters
-#
-CONFIG_SPI_SPIDEV=m
-CONFIG_SPI_LOOPBACK_TEST=m
-# CONFIG_SPI_TLE62X0 is not set
-CONFIG_SPI_SLAVE=y
-CONFIG_SPI_SLAVE_TIME=m
-CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPMI=m
-# CONFIG_SPMI_HISI3670 is not set
-CONFIG_SPMI_MSM_PMIC_ARB=m
-CONFIG_HSI=m
-CONFIG_HSI_BOARDINFO=y
-
-#
-# HSI controllers
-#
-
-#
-# HSI clients
-#
-CONFIG_HSI_CHAR=m
-CONFIG_PPS=y
-# CONFIG_PPS_DEBUG is not set
-
-#
-# PPS clients support
-#
-# CONFIG_PPS_CLIENT_KTIMER is not set
-CONFIG_PPS_CLIENT_LDISC=m
-CONFIG_PPS_CLIENT_PARPORT=m
-CONFIG_PPS_CLIENT_GPIO=m
-
-#
-# PPS generators support
-#
-
-#
-# PTP clock support
-#
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PTP_1588_CLOCK_DTE=m
-CONFIG_PTP_1588_CLOCK_QORIQ=m
-
-#
-# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
-#
-CONFIG_PTP_1588_CLOCK_KVM=m
-CONFIG_PTP_1588_CLOCK_IDT82P33=m
-CONFIG_PTP_1588_CLOCK_IDTCM=m
-CONFIG_PTP_1588_CLOCK_OCP=m
-# end of PTP clock support
-
-CONFIG_PINCTRL=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_PINMUX=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_PINCONF=y
-CONFIG_GENERIC_PINCONF=y
-# CONFIG_DEBUG_PINCTRL is not set
-# CONFIG_PINCTRL_APPLE_GPIO is not set
-CONFIG_PINCTRL_AXP209=m
-CONFIG_PINCTRL_CY8C95X0=m
-CONFIG_PINCTRL_AMD=m
-CONFIG_PINCTRL_BM1880=y
-CONFIG_PINCTRL_MCP23S08_I2C=m
-CONFIG_PINCTRL_MCP23S08_SPI=m
-CONFIG_PINCTRL_MCP23S08=m
-CONFIG_PINCTRL_ROCKCHIP=y
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_PINCTRL_SX150X=y
-CONFIG_PINCTRL_STMFX=m
-CONFIG_PINCTRL_MAX77620=m
-CONFIG_PINCTRL_ZYNQMP=y
-CONFIG_PINCTRL_RK805=m
-# CONFIG_PINCTRL_OCELOT is not set
-# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
-CONFIG_PINCTRL_KEEMBAY=m
-CONFIG_PINCTRL_OWL=y
-CONFIG_PINCTRL_BCM4908=m
-CONFIG_PINCTRL_S700=y
-CONFIG_PINCTRL_S900=y
-CONFIG_PINCTRL_BCM2835=y
-CONFIG_PINCTRL_BCM4908=m
-CONFIG_PINCTRL_IPROC_GPIO=y
-CONFIG_PINCTRL_NS2_MUX=y
-CONFIG_PINCTRL_BERLIN=y
-CONFIG_PINCTRL_AS370=y
-CONFIG_PINCTRL_BERLIN_BG4CT=y
-CONFIG_PINCTRL_IMX=y
-CONFIG_PINCTRL_IMX_SCU=y
-CONFIG_PINCTRL_IMX8MM=y
-CONFIG_PINCTRL_IMX8MN=y
-CONFIG_PINCTRL_IMX8MP=y
-CONFIG_PINCTRL_IMX8MQ=y
-CONFIG_PINCTRL_IMX8QM=y
-CONFIG_PINCTRL_IMX8QXP=y
-CONFIG_PINCTRL_IMX8DXL=y
-CONFIG_PINCTRL_IMX8ULP=y
-CONFIG_PINCTRL_MVEBU=y
-CONFIG_PINCTRL_ARMADA_AP806=y
-CONFIG_PINCTRL_ARMADA_CP110=y
-CONFIG_PINCTRL_ARMADA_37XX=y
-CONFIG_PINCTRL_MSM=y
-# CONFIG_PINCTRL_APQ8064 is not set
-# CONFIG_PINCTRL_APQ8084 is not set
-# CONFIG_PINCTRL_IPQ4019 is not set
-# CONFIG_PINCTRL_IPQ8064 is not set
-# CONFIG_PINCTRL_IPQ8074 is not set
-CONFIG_PINCTRL_IPQ6018=m
-CONFIG_PINCTRL_MSM8226=m
-# CONFIG_PINCTRL_MSM8660 is not set
-# CONFIG_PINCTRL_MSM8960 is not set
-# CONFIG_PINCTRL_MDM9607 is not set
-# CONFIG_PINCTRL_MDM9615 is not set
-# CONFIG_PINCTRL_MSM8X74 is not set
-CONFIG_PINCTRL_MSM8916=m
-CONFIG_PINCTRL_MSM8953=m
-CONFIG_PINCTRL_MSM8976=m
-# CONFIG_PINCTRL_MSM8994 is not set
-# CONFIG_PINCTRL_MSM8996 is not set
-CONFIG_PINCTRL_MSM8998=m
-# CONFIG_PINCTRL_QCM2290 is not set
-# CONFIG_PINCTRL_QCS404 is not set
-CONFIG_PINCTRL_QDF2XXX=m
-CONFIG_PINCTRL_QCOM_SPMI_PMIC=m
-CONFIG_PINCTRL_QCOM_SSBI_PMIC=m
-CONFIG_PINCTRL_SC7180=m
-CONFIG_PINCTRL_SC7280=m
-CONFIG_PINCTRL_SC8180X=m
-CONFIG_PINCTRL_SC8280XP=m
-# CONFIG_PINCTRL_SDM660 is not set
-CONFIG_PINCTRL_SDM845=m
-CONFIG_PINCTRL_SDX55=m
-CONFIG_PINCTRL_SM6115=m
-CONFIG_PINCTRL_SM6125=m
-# CONFIG_PINCTRL_SM6350 is not set
-CONFIG_PINCTRL_SM8150=m
-CONFIG_PINCTRL_SM8250=m
-CONFIG_PINCTRL_SM8350=m
-CONFIG_PINCTRL_LPASS_LPI=m
-
-#
-# Renesas pinctrl drivers
-#
-CONFIG_PINCTRL_RENESAS=y
-CONFIG_PINCTRL_SH_PFC=y
-CONFIG_PINCTRL_PFC_R8A77995=y
-CONFIG_PINCTRL_PFC_R8A77990=y
-CONFIG_PINCTRL_PFC_R8A77950=y
-CONFIG_PINCTRL_PFC_R8A77951=y
-CONFIG_PINCTRL_PFC_R8A77965=y
-CONFIG_PINCTRL_PFC_R8A77960=y
-CONFIG_PINCTRL_PFC_R8A77961=y
-CONFIG_PINCTRL_PFC_R8A77980=y
-CONFIG_PINCTRL_PFC_R8A77970=y
-CONFIG_PINCTRL_PFC_R8A779A0=y
-CONFIG_PINCTRL_RZG2L=y
-CONFIG_PINCTRL_PFC_R8A774C0=y
-CONFIG_PINCTRL_PFC_R8A774E1=y
-CONFIG_PINCTRL_PFC_R8A774A1=y
-CONFIG_PINCTRL_PFC_R8A774B1=y
-# end of Renesas pinctrl drivers
-
-CONFIG_PINCTRL_SAMSUNG=y
-CONFIG_PINCTRL_EXYNOS=y
-CONFIG_PINCTRL_EXYNOS_ARM64=y
-CONFIG_PINCTRL_SPRD=y
-CONFIG_PINCTRL_SPRD_SC9860=y
-CONFIG_PINCTRL_SUNXI=y
-# CONFIG_PINCTRL_SUN4I_A10 is not set
-# CONFIG_PINCTRL_SUN5I is not set
-# CONFIG_PINCTRL_SUN6I_A31 is not set
-# CONFIG_PINCTRL_SUN6I_A31_R is not set
-# CONFIG_PINCTRL_SUN8I_A23 is not set
-# CONFIG_PINCTRL_SUN8I_A33 is not set
-# CONFIG_PINCTRL_SUN8I_A83T is not set
-# CONFIG_PINCTRL_SUN8I_A83T_R is not set
-# CONFIG_PINCTRL_SUN8I_A23_R is not set
-# CONFIG_PINCTRL_SUN8I_H3 is not set
-CONFIG_PINCTRL_SUN8I_H3_R=y
-# CONFIG_PINCTRL_SUN8I_V3S is not set
-# CONFIG_PINCTRL_SUN9I_A80 is not set
-# CONFIG_PINCTRL_SUN9I_A80_R is not set
-CONFIG_PINCTRL_SUN50I_A64=y
-CONFIG_PINCTRL_SUN50I_A64_R=y
-CONFIG_PINCTRL_SUN50I_A100=y
-CONFIG_PINCTRL_SUN50I_A100_R=y
-CONFIG_PINCTRL_SUN50I_H5=y
-CONFIG_PINCTRL_SUN50I_H6=y
-CONFIG_PINCTRL_SUN50I_H6_R=y
-CONFIG_PINCTRL_SUN50I_H616=y
-CONFIG_PINCTRL_SUN50I_H616_R=y
-CONFIG_PINCTRL_TEGRA=y
-CONFIG_PINCTRL_TEGRA124=y
-CONFIG_PINCTRL_TEGRA210=y
-CONFIG_PINCTRL_TEGRA194=y
-CONFIG_PINCTRL_TEGRA_XUSB=y
-CONFIG_PINCTRL_UNIPHIER=y
-CONFIG_PINCTRL_UNIPHIER_LD4=y
-CONFIG_PINCTRL_UNIPHIER_PRO4=y
-CONFIG_PINCTRL_UNIPHIER_SLD8=y
-CONFIG_PINCTRL_UNIPHIER_PRO5=y
-CONFIG_PINCTRL_UNIPHIER_PXS2=y
-CONFIG_PINCTRL_UNIPHIER_LD6B=y
-CONFIG_PINCTRL_UNIPHIER_LD11=y
-CONFIG_PINCTRL_UNIPHIER_LD20=y
-CONFIG_PINCTRL_UNIPHIER_PXS3=y
-CONFIG_PINCTRL_UNIPHIER_NX1=y
-
-#
-# MediaTek pinctrl drivers
-#
-CONFIG_EINT_MTK=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_PARIS=y
-CONFIG_PINCTRL_MT2712=y
-CONFIG_PINCTRL_MT6765=y
-CONFIG_PINCTRL_MT6779=y
-CONFIG_PINCTRL_MT6795=y
-CONFIG_PINCTRL_MT6797=y
-CONFIG_PINCTRL_MT7622=y
-CONFIG_PINCTRL_MT7986=y
-CONFIG_PINCTRL_MT8167=y
-CONFIG_PINCTRL_MT8173=y
-CONFIG_PINCTRL_MT8183=y
-CONFIG_PINCTRL_MT8186=y
-CONFIG_PINCTRL_MT8188=y
-CONFIG_PINCTRL_MT8192=y
-CONFIG_PINCTRL_MT8195=y
-CONFIG_PINCTRL_MT8365=y
-CONFIG_PINCTRL_MT8516=y
-# end of MediaTek pinctrl drivers
-
-CONFIG_PINCTRL_MESON=y
-CONFIG_PINCTRL_MESON_GXBB=y
-CONFIG_PINCTRL_MESON_GXL=y
-CONFIG_PINCTRL_MESON8_PMX=y
-CONFIG_PINCTRL_MESON_AXG=y
-CONFIG_PINCTRL_MESON_AXG_PMX=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_PINCTRL_MESON_A1=y
-CONFIG_PINCTRL_MESON_S4=m
-CONFIG_PINCTRL_LOCHNAGAR=m
-CONFIG_PINCTRL_MADERA=m
-CONFIG_PINCTRL_CS47L15=y
-CONFIG_PINCTRL_CS47L35=y
-CONFIG_PINCTRL_CS47L85=y
-CONFIG_PINCTRL_CS47L90=y
-CONFIG_PINCTRL_CS47L92=y
-CONFIG_PINCTRL_VISCONTI=y
-CONFIG_PINCTRL_TMPV7700=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_FASTPATH_LIMIT=512
-CONFIG_OF_GPIO=y
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIOLIB_IRQCHIP=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_CDEV_V1=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_MAX730X=m
-
-#
-# Memory mapped GPIO drivers
-#
-CONFIG_GPIO_74XX_MMIO=m
-# CONFIG_GPIO_ALTERA is not set
-# CONFIG_GPIO_AMDPT is not set
-CONFIG_GPIO_RASPBERRYPI_EXP=m
-CONFIG_GPIO_BCM_XGS_IPROC=m
-CONFIG_GPIO_BRCMSTB=m
-CONFIG_GPIO_CADENCE=m
-CONFIG_GPIO_DAVINCI=y
-CONFIG_GPIO_DWAPB=m
-CONFIG_GPIO_EIC_SPRD=m
-# CONFIG_GPIO_EXAR is not set
-CONFIG_GPIO_FTGPIO010=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_GRGPIO=m
-CONFIG_GPIO_HISI=m
-# CONFIG_GPIO_HLWD is not set
-# CONFIG_GPIO_LOGICVC is not set
-CONFIG_GPIO_MB86S7X=m
-CONFIG_GPIO_MPC8XXX=y
-CONFIG_GPIO_MVEBU=y
-CONFIG_GPIO_MXC=y
-CONFIG_GPIO_PL061=y
-CONFIG_GPIO_PMIC_EIC_SPRD=m
-CONFIG_GPIO_RCAR=m
-CONFIG_GPIO_ROCKCHIP=m
-# CONFIG_GPIO_SAMA5D2_PIOBU is not set
-# CONFIG_GPIO_SIFIVE is not set
-CONFIG_GPIO_SPRD=m
-CONFIG_GPIO_SYSCON=m
-CONFIG_GPIO_TEGRA=y
-CONFIG_GPIO_TEGRA186=m
-CONFIG_GPIO_THUNDERX=m
-CONFIG_GPIO_UNIPHIER=m
-CONFIG_GPIO_VISCONTI=m
-CONFIG_GPIO_WCD934X=m
-CONFIG_GPIO_XGENE=y
-CONFIG_GPIO_XGENE_SB=m
-CONFIG_GPIO_XILINX=m
-CONFIG_GPIO_XLP=m
-CONFIG_GPIO_ZYNQ=m
-CONFIG_GPIO_ZYNQMP_MODEPIN=y
-# CONFIG_GPIO_AMD_FCH is not set
-# end of Memory mapped GPIO drivers
-
-#
-# I2C GPIO expanders
-#
-CONFIG_GPIO_ADP5588=m
-# CONFIG_GPIO_ADNP is not set
-CONFIG_GPIO_GW_PLD=m
-CONFIG_GPIO_MAX7300=m
-CONFIG_GPIO_MAX732X=m
-CONFIG_GPIO_PCA953X=y
-CONFIG_GPIO_PCA953X_IRQ=y
-CONFIG_GPIO_PCA9570=m
-CONFIG_GPIO_PCF857X=m
-CONFIG_GPIO_TPIC2810=m
-# end of I2C GPIO expanders
-
-#
-# MFD GPIO expanders
-#
-CONFIG_GPIO_ALTERA_A10SR=m
-CONFIG_GPIO_BD70528=m
-CONFIG_GPIO_BD71815=m
-CONFIG_GPIO_BD71828=m
-CONFIG_GPIO_BD9571MWV=m
-CONFIG_GPIO_DLN2=m
-CONFIG_GPIO_KEMPLD=m
-CONFIG_GPIO_LP3943=m
-CONFIG_GPIO_LP873X=m
-CONFIG_GPIO_LP87565=m
-CONFIG_GPIO_MADERA=m
-CONFIG_GPIO_MAX77620=m
-CONFIG_GPIO_MAX77650=m
-CONFIG_GPIO_TQMX86=m
-# CONFIG_GPIO_WM8994 is not set
-# end of MFD GPIO expanders
-
-#
-# PCI GPIO expanders
-#
-CONFIG_GPIO_MLXBF=m
-CONFIG_GPIO_MLXBF2=m
-CONFIG_GPIO_PCI_IDIO_16=m
-CONFIG_GPIO_PCIE_IDIO_24=m
-# CONFIG_GPIO_RDC321X is not set
-# end of PCI GPIO expanders
-
-#
-# SPI GPIO expanders
-#
-# CONFIG_GPIO_74X164 is not set
-CONFIG_GPIO_MAX3191X=m
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MC33880 is not set
-CONFIG_GPIO_PISOSR=m
-CONFIG_GPIO_XRA1403=m
-CONFIG_GPIO_MOXTET=m
-# end of SPI GPIO expanders
-
-#
-# USB GPIO expanders
-#
-CONFIG_GPIO_VIPERBOARD=m
-# end of USB GPIO expanders
-
-#
-# Virtual GPIO drivers
-#
-CONFIG_GPIO_AGGREGATOR=m
-CONFIG_GPIO_MOCKUP=m
-CONFIG_GPIO_VIRTIO=m
-# end of Virtual GPIO drivers
-
-CONFIG_W1=m
-CONFIG_W1_CON=y
-
-#
-# 1-wire Bus Masters
-#
-CONFIG_W1_MASTER_MATROX=m
-CONFIG_W1_MASTER_DS2490=m
-CONFIG_W1_MASTER_DS2482=m
-CONFIG_W1_MASTER_MXC=m
-CONFIG_W1_MASTER_DS1WM=m
-CONFIG_W1_MASTER_GPIO=m
-# CONFIG_W1_MASTER_SGI is not set
-# end of 1-wire Bus Masters
-
-#
-# 1-wire Slaves
-#
-CONFIG_W1_SLAVE_THERM=m
-CONFIG_W1_SLAVE_SMEM=m
-CONFIG_W1_SLAVE_DS2405=m
-CONFIG_W1_SLAVE_DS2408=m
-CONFIG_W1_SLAVE_DS2408_READBACK=y
-CONFIG_W1_SLAVE_DS2413=m
-CONFIG_W1_SLAVE_DS2406=m
-CONFIG_W1_SLAVE_DS2423=m
-CONFIG_W1_SLAVE_DS2805=m
-CONFIG_W1_SLAVE_DS2430=m
-CONFIG_W1_SLAVE_DS2431=m
-CONFIG_W1_SLAVE_DS2433=m
-CONFIG_W1_SLAVE_DS2433_CRC=y
-CONFIG_W1_SLAVE_DS2438=m
-CONFIG_W1_SLAVE_DS250X=m
-CONFIG_W1_SLAVE_DS2780=m
-CONFIG_W1_SLAVE_DS2781=m
-CONFIG_W1_SLAVE_DS28E04=m
-CONFIG_W1_SLAVE_DS28E17=m
-# end of 1-wire Slaves
-
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_ATC260X=m
-CONFIG_POWER_RESET_BRCMSTB=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_POWER_RESET_GPIO_RESTART=y
-CONFIG_POWER_RESET_HISI=y
-CONFIG_POWER_RESET_LINKSTATION=m
-CONFIG_POWER_RESET_MSM=y
-CONFIG_POWER_RESET_QCOM_PON=m
-CONFIG_POWER_RESET_OCELOT_RESET=y
-CONFIG_POWER_RESET_LTC2952=y
-CONFIG_POWER_RESET_REGULATOR=y
-CONFIG_POWER_RESET_RESTART=y
-CONFIG_POWER_RESET_VEXPRESS=y
-# CONFIG_POWER_RESET_XGENE is not set
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-CONFIG_REBOOT_MODE=m
-CONFIG_SYSCON_REBOOT_MODE=m
-CONFIG_POWER_RESET_SC27XX=m
-CONFIG_NVMEM_REBOOT_MODE=m
-CONFIG_POWER_MLXBF=m
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PDA_POWER=m
-# CONFIG_GENERIC_ADC_BATTERY is not set
-CONFIG_IP5XXX_POWER=m
-# CONFIG_TEST_POWER is not set
-CONFIG_CHARGER_ADP5061=m
-CONFIG_BATTERY_CPCAP=m
-CONFIG_BATTERY_CW2015=m
-CONFIG_BATTERY_DS2760=m
-CONFIG_BATTERY_DS2780=m
-CONFIG_BATTERY_DS2781=m
-CONFIG_BATTERY_DS2782=m
-# CONFIG_BATTERY_SAMSUNG_SDI is not set
-CONFIG_BATTERY_SBS=m
-CONFIG_CHARGER_SBS=m
-CONFIG_MANAGER_SBS=m
-CONFIG_BATTERY_BQ27XXX=m
-CONFIG_BATTERY_BQ27XXX_I2C=m
-CONFIG_BATTERY_BQ27XXX_HDQ=m
-# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set
-CONFIG_CHARGER_AXP20X=m
-CONFIG_BATTERY_AXP20X=m
-CONFIG_AXP20X_POWER=m
-CONFIG_BATTERY_MAX17040=m
-CONFIG_BATTERY_MAX17042=m
-CONFIG_BATTERY_MAX1721X=m
-CONFIG_CHARGER_CPCAP=m
-CONFIG_CHARGER_ISP1704=m
-CONFIG_CHARGER_MAX8903=m
-CONFIG_CHARGER_LP8727=m
-CONFIG_CHARGER_GPIO=m
-# CONFIG_CHARGER_MANAGER is not set
-CONFIG_CHARGER_LT3651=m
-CONFIG_CHARGER_LTC4162L=m
-CONFIG_CHARGER_DETECTOR_MAX14656=m
-CONFIG_CHARGER_MAX77650=m
-CONFIG_CHARGER_MP2629=m
-CONFIG_CHARGER_MT6360=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_CHARGER_QCOM_SMBB=m
-# CONFIG_CHARGER_BQ2415X is not set
-CONFIG_CHARGER_BQ24190=m
-CONFIG_CHARGER_BQ24257=m
-CONFIG_CHARGER_BQ24735=m
-CONFIG_CHARGER_BQ2515X=m
-CONFIG_CHARGER_BQ25890=m
-CONFIG_CHARGER_BQ25980=m
-CONFIG_CHARGER_BQ256XX=m
-CONFIG_CHARGER_RK817=m
-CONFIG_CHARGER_SMB347=m
-# CONFIG_BATTERY_GAUGE_LTC2941 is not set
-# CONFIG_BATTERY_GOLDFISH is not set
-CONFIG_BATTERY_RT5033=m
-CONFIG_CHARGER_RT9455=m
-CONFIG_CHARGER_CROS_USBPD=m
-CONFIG_CHARGER_CROS_PCHG=m
-CONFIG_CHARGER_SC2731=m
-CONFIG_FUEL_GAUGE_SC27XX=m
-CONFIG_CHARGER_UCS1002=m
-CONFIG_CHARGER_BD99954=m
-CONFIG_BATTERY_UG3105=m
-CONFIG_BATTERY_SURFACE=m
-CONFIG_CHARGER_SURFACE=m
-CONFIG_HWMON=y
-CONFIG_HWMON_VID=m
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Native drivers
-#
-# CONFIG_SENSORS_AD7314 is not set
-CONFIG_SENSORS_AD7414=m
-CONFIG_SENSORS_AD7418=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1026=m
-CONFIG_SENSORS_ADM1029=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_ADM1177=m
-CONFIG_SENSORS_ADM9240=m
-CONFIG_SENSORS_ADT7X10=m
-# CONFIG_SENSORS_ADT7310 is not set
-CONFIG_SENSORS_ADT7410=m
-CONFIG_SENSORS_ADT7411=m
-CONFIG_SENSORS_ADT7462=m
-CONFIG_SENSORS_ADT7470=m
-CONFIG_SENSORS_ADT7475=m
-CONFIG_SENSORS_AHT10=m
-CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m
-CONFIG_SENSORS_AS370=m
-CONFIG_SENSORS_ASC7621=m
-CONFIG_SENSORS_AXI_FAN_CONTROL=m
-CONFIG_SENSORS_ARM_SCMI=m
-CONFIG_SENSORS_ARM_SCPI=m
-CONFIG_SENSORS_ASPEED=m
-CONFIG_SENSORS_ATXP1=m
-CONFIG_SENSORS_CORSAIR_CPRO=m
-CONFIG_SENSORS_CORSAIR_PSU=m
-CONFIG_SENSORS_DRIVETEMP=m
-CONFIG_SENSORS_DS620=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_I5K_AMB=m
-CONFIG_SENSORS_SPARX5=m
-CONFIG_SENSORS_F71805F=m
-CONFIG_SENSORS_F71882FG=m
-CONFIG_SENSORS_F75375S=m
-CONFIG_SENSORS_GSC=m
-CONFIG_SENSORS_FTSTEUTATES=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_GL520SM=m
-CONFIG_SENSORS_G760A=m
-CONFIG_SENSORS_G762=m
-CONFIG_SENSORS_GPIO_FAN=m
-CONFIG_SENSORS_HIH6130=m
-CONFIG_SENSORS_IBMAEM=m
-CONFIG_SENSORS_IBMPEX=m
-# CONFIG_SENSORS_IIO_HWMON is not set
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_JC42=m
-CONFIG_SENSORS_POWR1220=m
-CONFIG_SENSORS_LINEAGE=m
-CONFIG_SENSORS_LOCHNAGAR=m
-CONFIG_SENSORS_LTC2945=m
-CONFIG_SENSORS_LTC2947=m
-CONFIG_SENSORS_LTC2947_I2C=m
-CONFIG_SENSORS_LTC2947_SPI=m
-CONFIG_SENSORS_LTC2990=m
-CONFIG_SENSORS_LTC2992=m
-CONFIG_SENSORS_LTC4151=m
-CONFIG_SENSORS_LTC4215=m
-CONFIG_SENSORS_LTC4222=m
-CONFIG_SENSORS_LTC4245=m
-CONFIG_SENSORS_LTC4260=m
-CONFIG_SENSORS_LTC4261=m
-# CONFIG_SENSORS_MAX1111 is not set
-CONFIG_SENSORS_MAX127=m
-CONFIG_SENSORS_MAX16065=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_MAX1668=m
-# CONFIG_SENSORS_MAX197 is not set
-CONFIG_SENSORS_MAX31722=m
-CONFIG_SENSORS_MAX31730=m
-CONFIG_SENSORS_MAX31760=m
-# CONFIG_SENSORS_MAX6620 is not set
-CONFIG_SENSORS_MAX6621=m
-CONFIG_SENSORS_MAX6639=m
-CONFIG_SENSORS_MAX6642=m
-CONFIG_SENSORS_MAX6650=m
-CONFIG_SENSORS_MAX6697=m
-CONFIG_SENSORS_MAX31790=m
-CONFIG_SENSORS_MCP3021=m
-CONFIG_SENSORS_MLXREG_FAN=m
-CONFIG_SENSORS_TC654=m
-CONFIG_SENSORS_TPS23861=m
-# CONFIG_SENSORS_MENF21BMC_HWMON is not set
-CONFIG_SENSORS_MR75203=m
-# CONFIG_SENSORS_ADCXX is not set
-CONFIG_SENSORS_LM63=m
-# CONFIG_SENSORS_LM70 is not set
-CONFIG_SENSORS_LM73=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM87=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_LM92=m
-CONFIG_SENSORS_LM93=m
-CONFIG_SENSORS_LM95234=m
-CONFIG_SENSORS_LM95241=m
-CONFIG_SENSORS_LM95245=m
-CONFIG_SENSORS_PC87360=m
-CONFIG_SENSORS_PC87427=m
-# CONFIG_SENSORS_NTC_THERMISTOR is not set
-CONFIG_SENSORS_NCT6683=m
-CONFIG_SENSORS_NCT6775=m
-CONFIG_SENSORS_NCT7802=m
-CONFIG_SENSORS_NCT7904=m
-CONFIG_SENSORS_NPCM7XX=m
-CONFIG_SENSORS_NZXT_KRAKEN2=m
-# CONFIG_SENSORS_OCC_P8_I2C is not set
-CONFIG_SENSORS_PCF8591=m
-CONFIG_PMBUS=m
-CONFIG_SENSORS_PMBUS=m
-CONFIG_SENSORS_ADM1266=m
-CONFIG_SENSORS_ADM1275=m
-CONFIG_SENSORS_BEL_PFE=m
-CONFIG_SENSORS_BPA_RS600=m
-CONFIG_SENSORS_FSP_3Y=m
-# CONFIG_SENSORS_IBM_CFFPS is not set
-CONFIG_SENSORS_DPS920AB=m
-CONFIG_SENSORS_INSPUR_IPSPS=m
-CONFIG_SENSORS_IR35221=m
-CONFIG_SENSORS_IR36021=m
-CONFIG_SENSORS_IR38064=m
-CONFIG_SENSORS_IRPS5401=m
-CONFIG_SENSORS_ISL68137=m
-CONFIG_SENSORS_LM25066=m
-CONFIG_SENSORS_LM25066_REGULATOR=y
-CONFIG_SENSORS_LTC2978=m
-# CONFIG_SENSORS_LTC2978_REGULATOR is not set
-CONFIG_SENSORS_LTC3815=m
-CONFIG_SENSORS_MAX15301=m
-CONFIG_SENSORS_MAX16064=m
-CONFIG_SENSORS_MAX16601=m
-CONFIG_SENSORS_MAX20730=m
-CONFIG_SENSORS_MAX20751=m
-CONFIG_SENSORS_MAX31785=m
-CONFIG_SENSORS_MAX34440=m
-CONFIG_SENSORS_MAX8688=m
-CONFIG_SENSORS_MP2888=m
-CONFIG_SENSORS_MP2975=m
-CONFIG_SENSORS_PIM4328=m
-CONFIG_SENSORS_PLI1209BC_REGULATOR=y
-CONFIG_SENSORS_PLI1209BC=m
-CONFIG_SENSORS_PM6764TR=m
-CONFIG_SENSORS_PXE1610=m
-CONFIG_SENSORS_Q54SJ108A2=m
-CONFIG_SENSORS_STPDDC60=m
-CONFIG_SENSORS_TPS40422=m
-CONFIG_SENSORS_TPS53679=m
-CONFIG_SENSORS_TPS546D24=m
-CONFIG_SENSORS_UCD9000=m
-CONFIG_SENSORS_UCD9200=m
-CONFIG_SENSORS_XDPE122=m
-CONFIG_SENSORS_XDPE122_REGULATOR=y
-CONFIG_SENSORS_ZL6100=m
-CONFIG_SENSORS_PWM_FAN=m
-CONFIG_SENSORS_RASPBERRYPI_HWMON=m
-CONFIG_SENSORS_SBTSI=m
-CONFIG_SENSORS_SBRMI=m
-CONFIG_SENSORS_SHT15=m
-CONFIG_SENSORS_SHT21=m
-CONFIG_SENSORS_SHT3x=m
-CONFIG_SENSORS_SHT4x=m
-CONFIG_SENSORS_SHTC1=m
-CONFIG_SENSORS_SIS5595=m
-CONFIG_SENSORS_SY7636A=m
-CONFIG_SENSORS_DME1737=m
-CONFIG_SENSORS_EMC1403=m
-CONFIG_SENSORS_EMC2103=m
-CONFIG_SENSORS_EMC2305=m
-CONFIG_SENSORS_EMC6W201=m
-CONFIG_SENSORS_SMSC47M1=m
-CONFIG_SENSORS_SMSC47M192=m
-CONFIG_SENSORS_SMSC47B397=m
-CONFIG_SENSORS_SCH56XX_COMMON=m
-CONFIG_SENSORS_SCH5627=m
-CONFIG_SENSORS_SCH5636=m
-CONFIG_SENSORS_STTS751=m
-CONFIG_SENSORS_SMM665=m
-CONFIG_SENSORS_ADC128D818=m
-CONFIG_SENSORS_ADS7828=m
-# CONFIG_SENSORS_ADS7871 is not set
-CONFIG_SENSORS_AMC6821=m
-CONFIG_SENSORS_INA209=m
-CONFIG_SENSORS_INA2XX=m
-CONFIG_SENSORS_INA3221=m
-CONFIG_SENSORS_TC74=m
-CONFIG_SENSORS_THMC50=m
-CONFIG_SENSORS_TMP102=m
-CONFIG_SENSORS_TMP103=m
-CONFIG_SENSORS_TMP108=m
-CONFIG_SENSORS_TMP401=m
-CONFIG_SENSORS_TMP421=m
-CONFIG_SENSORS_TMP464=m
-CONFIG_SENSORS_TMP513=m
-CONFIG_SENSORS_VEXPRESS=m
-CONFIG_SENSORS_VIA686A=m
-CONFIG_SENSORS_VT1211=m
-CONFIG_SENSORS_VT8231=m
-CONFIG_SENSORS_W83773G=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83791D=m
-CONFIG_SENSORS_W83792D=m
-CONFIG_SENSORS_W83793=m
-CONFIG_SENSORS_W83795=m
-# CONFIG_SENSORS_W83795_FANCTRL is not set
-CONFIG_SENSORS_W83L785TS=m
-CONFIG_SENSORS_W83L786NG=m
-CONFIG_SENSORS_W83627HF=m
-CONFIG_SENSORS_W83627EHF=m
-CONFIG_SENSORS_XGENE=m
-
-#
-# ACPI drivers
-#
-# CONFIG_SENSORS_ACPI_POWER is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_NETLINK=y
-CONFIG_THERMAL_STATISTICS=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-# CONFIG_THERMAL_WRITABLE_TRIPS is not set
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_FREQ_THERMAL=y
-CONFIG_DEVFREQ_THERMAL=y
-# CONFIG_THERMAL_EMULATION is not set
-CONFIG_THERMAL_MMIO=m
-CONFIG_HISI_THERMAL=m
-CONFIG_IMX_THERMAL=m
-CONFIG_IMX_SC_THERMAL=m
-CONFIG_IMX8MM_THERMAL=m
-CONFIG_K3_THERMAL=m
-CONFIG_MAX77620_THERMAL=m
-CONFIG_QORIQ_THERMAL=m
-CONFIG_SUN8I_THERMAL=m
-CONFIG_ROCKCHIP_THERMAL=y
-CONFIG_RCAR_THERMAL=m
-CONFIG_RCAR_GEN3_THERMAL=m
-CONFIG_ARMADA_THERMAL=m
-CONFIG_MTK_THERMAL=m
-CONFIG_AMLOGIC_THERMAL=m
-
-#
-# Broadcom thermal drivers
-#
-CONFIG_BCM2711_THERMAL=m
-CONFIG_BCM2835_THERMAL=m
-CONFIG_BRCMSTB_THERMAL=m
-CONFIG_BCM_NS_THERMAL=m
-CONFIG_BCM_SR_THERMAL=m
-# end of Broadcom thermal drivers
-
-#
-# Samsung thermal drivers
-#
-CONFIG_EXYNOS_THERMAL=m
-# end of Samsung thermal drivers
-
-#
-# NVIDIA Tegra thermal drivers
-#
-CONFIG_TEGRA_SOCTHERM=m
-CONFIG_TEGRA_BPMP_THERMAL=m
-# end of NVIDIA Tegra thermal drivers
-
-CONFIG_GENERIC_ADC_THERMAL=m
-
-#
-# Qualcomm thermal drivers
-#
-CONFIG_QCOM_TSENS=m
-CONFIG_QCOM_SPMI_ADC_TM5=m
-# CONFIG_QCOM_SPMI_TEMP_ALARM is not set
-CONFIG_QCOM_LMH=m
-# end of Qualcomm thermal drivers
-
-CONFIG_UNIPHIER_THERMAL=m
-CONFIG_SPRD_THERMAL=m
-CONFIG_KHADAS_MCU_FAN_THERMAL=m
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_CORE=m
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
-CONFIG_WATCHDOG_OPEN_TIMEOUT=0
-CONFIG_WATCHDOG_SYSFS=y
-CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y
-
-#
-# Watchdog Pretimeout Governors
-#
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=m
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y
-# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC is not set
-
-#
-# Watchdog Device Drivers
-#
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y
-CONFIG_BD957XMUF_WATCHDOG=m
-# CONFIG_GPIO_WATCHDOG is not set
-# CONFIG_MENF21BMC_WATCHDOG is not set
-CONFIG_WDAT_WDT=m
-CONFIG_XILINX_WATCHDOG=m
-CONFIG_ZIIRAVE_WATCHDOG=m
-CONFIG_MLX_WDT=m
-CONFIG_ARM_SP805_WATCHDOG=m
-CONFIG_ARM_SBSA_WATCHDOG=m
-CONFIG_ARMADA_37XX_WATCHDOG=m
-CONFIG_CADENCE_WATCHDOG=m
-CONFIG_S3C2410_WATCHDOG=m
-CONFIG_DW_WATCHDOG=m
-CONFIG_K3_RTI_WATCHDOG=m
-CONFIG_SUNXI_WATCHDOG=m
-CONFIG_NPCM7XX_WATCHDOG=m
-# CONFIG_MAX63XX_WATCHDOG is not set
-CONFIG_MAX77620_WATCHDOG=m
-CONFIG_IMX2_WDT=m
-CONFIG_IMX_SC_WDT=m
-CONFIG_IMX7ULP_WDT=m
-CONFIG_TEGRA_WATCHDOG=m
-# CONFIG_QCOM_WDT is not set
-CONFIG_MESON_GXBB_WATCHDOG=m
-CONFIG_MESON_WATCHDOG=m
-CONFIG_MEDIATEK_WATCHDOG=m
-CONFIG_ARM_SMC_WATCHDOG=m
-CONFIG_RENESAS_WDT=m
-CONFIG_RENESAS_RZAWDT=m
-CONFIG_STPMIC1_WATCHDOG=m
-CONFIG_UNIPHIER_WATCHDOG=m
-CONFIG_RTD119X_WATCHDOG=y
-CONFIG_SPRD_WATCHDOG=m
-CONFIG_PM8916_WATCHDOG=m
-CONFIG_VISCONTI_WATCHDOG=m
-CONFIG_APPLE_WATCHDOG=m
-CONFIG_ALIM7101_WDT=m
-CONFIG_I6300ESB_WDT=m
-CONFIG_HP_WATCHDOG=m
-CONFIG_KEMPLD_WDT=m
-CONFIG_BCM2835_WDT=m
-CONFIG_BCM7038_WDT=m
-CONFIG_MEN_A21_WDT=m
-
-#
-# PCI-based Watchdog Cards
-#
-# CONFIG_PCIPCWATCHDOG is not set
-# CONFIG_WDTPCI is not set
-
-#
-# USB-based Watchdog Cards
-#
-CONFIG_USBPCWATCHDOG=m
-CONFIG_KEEMBAY_WATCHDOG=m
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SSB=m
-CONFIG_SSB_SPROM=y
-CONFIG_SSB_BLOCKIO=y
-CONFIG_SSB_PCIHOST_POSSIBLE=y
-CONFIG_SSB_PCIHOST=y
-CONFIG_SSB_B43_PCI_BRIDGE=y
-CONFIG_SSB_SDIOHOST_POSSIBLE=y
-CONFIG_SSB_SDIOHOST=y
-CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
-CONFIG_SSB_DRIVER_PCICORE=y
-CONFIG_SSB_DRIVER_GPIO=y
-CONFIG_BCMA_POSSIBLE=y
-CONFIG_BCMA=m
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_SOC=y
-CONFIG_BCMA_DRIVER_PCI=y
-CONFIG_BCMA_SFLASH=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_DRIVER_GPIO=y
-# CONFIG_BCMA_DEBUG is not set
-
-#
-# Multifunction device drivers
-#
-CONFIG_MFD_CORE=y
-CONFIG_MFD_ALTERA_A10SR=y
-CONFIG_MFD_ALTERA_SYSMGR=y
-# CONFIG_MFD_ACT8945A is not set
-CONFIG_MFD_SUN4I_GPADC=m
-# CONFIG_MFD_AS3711 is not set
-# CONFIG_MFD_AS3722 is not set
-# CONFIG_PMIC_ADP5520 is not set
-# CONFIG_MFD_AAT2870_CORE is not set
-# CONFIG_MFD_ATMEL_FLEXCOM is not set
-CONFIG_MFD_ATMEL_HLCDC=m
-# CONFIG_MFD_BCM590XX is not set
-CONFIG_MFD_BD9571MWV=m
-CONFIG_MFD_AC100=m
-CONFIG_MFD_AXP20X=m
-CONFIG_MFD_AXP20X_I2C=m
-CONFIG_MFD_AXP20X_RSB=m
-CONFIG_MFD_CROS_EC_DEV=m
-CONFIG_MFD_MADERA=m
-CONFIG_MFD_MADERA_I2C=m
-CONFIG_MFD_MADERA_SPI=m
-CONFIG_MFD_CS47L15=y
-CONFIG_MFD_CS47L35=y
-CONFIG_MFD_CS47L85=y
-CONFIG_MFD_CS47L90=y
-CONFIG_MFD_CS47L92=y
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_MFD_DA9052_SPI is not set
-# CONFIG_MFD_DA9052_I2C is not set
-# CONFIG_MFD_DA9055 is not set
-# CONFIG_MFD_DA9062 is not set
-# CONFIG_MFD_DA9063 is not set
-# CONFIG_MFD_DA9150 is not set
-CONFIG_MFD_DLN2=m
-CONFIG_MFD_EXYNOS_LPASS=m
-CONFIG_MFD_GATEWORKS_GSC=m
-# CONFIG_MFD_MC13XXX_SPI is not set
-# CONFIG_MFD_MC13XXX_I2C is not set
-CONFIG_MFD_MP2629=m
-CONFIG_MFD_HI6421_PMIC=m
-CONFIG_MFD_HI6421_SPMI=m
-CONFIG_MFD_HI655X_PMIC=m
-CONFIG_HTC_PASIC3=m
-# CONFIG_HTC_I2CPLD is not set
-CONFIG_LPC_ICH=m
-CONFIG_LPC_SCH=m
-CONFIG_MFD_IQS62X=m
-# CONFIG_MFD_JANZ_CMODIO is not set
-CONFIG_MFD_KEMPLD=m
-# CONFIG_MFD_88PM800 is not set
-# CONFIG_MFD_88PM805 is not set
-# CONFIG_MFD_88PM860X is not set
-# CONFIG_MFD_MAX14577 is not set
-CONFIG_MFD_MAX77620=y
-CONFIG_MFD_MAX77650=m
-# CONFIG_MFD_MAX77686 is not set
-# CONFIG_MFD_MAX77693 is not set
-CONFIG_MFD_MAX77714=m
-# CONFIG_MFD_MAX77843 is not set
-# CONFIG_MFD_MAX8907 is not set
-# CONFIG_MFD_MAX8925 is not set
-# CONFIG_MFD_MAX8997 is not set
-# CONFIG_MFD_MAX8998 is not set
-CONFIG_MFD_MT6360=m
-CONFIG_MFD_MT6370=m
-# CONFIG_MFD_MT6397 is not set
-CONFIG_MFD_MENF21BMC=m
-CONFIG_MFD_OCELOT=m
-# CONFIG_EZX_PCAP is not set
-CONFIG_MFD_CPCAP=m
-CONFIG_MFD_VIPERBOARD=m
-# CONFIG_MFD_NTXEC is not set
-# CONFIG_MFD_RETU is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_UCB1400_CORE is not set
-CONFIG_MFD_QCOM_RPM=m
-CONFIG_MFD_SPMI_PMIC=m
-CONFIG_MFD_SY7636A=m
-# CONFIG_MFD_RDC321X is not set
-CONFIG_MFD_RT4831=m
-# CONFIG_MFD_RT5033 is not set
-CONFIG_MFD_RT5120=m
-# CONFIG_MFD_RC5T583 is not set
-CONFIG_MFD_RK808=m
-# CONFIG_MFD_RN5T618 is not set
-# CONFIG_MFD_SEC_CORE is not set
-# CONFIG_MFD_SI476X_CORE is not set
-CONFIG_MFD_SIMPLE_MFD_I2C=m
-# CONFIG_MFD_SL28CPLD is not set
-# CONFIG_MFD_SM501 is not set
-CONFIG_MFD_SKY81452=m
-CONFIG_MFD_SC27XX_PMIC=m
-# CONFIG_MFD_STMPE is not set
-CONFIG_MFD_SUN6I_PRCM=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MFD_TI_AM335X_TSCADC=m
-CONFIG_MFD_LP3943=m
-# CONFIG_MFD_LP8788 is not set
-CONFIG_MFD_TI_LMU=m
-# CONFIG_MFD_PALMAS is not set
-# CONFIG_TPS6105X is not set
-CONFIG_TPS65010=m
-CONFIG_TPS6507X=m
-# CONFIG_MFD_TPS65086 is not set
-# CONFIG_MFD_TPS65090 is not set
-# CONFIG_MFD_TPS65217 is not set
-CONFIG_MFD_TI_LP873X=m
-CONFIG_MFD_TI_LP87565=m
-# CONFIG_MFD_TPS65218 is not set
-# CONFIG_MFD_TPS6586X is not set
-# CONFIG_MFD_TPS65910 is not set
-# CONFIG_MFD_TPS65912_I2C is not set
-# CONFIG_MFD_TPS65912_SPI is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_TWL6040_CORE is not set
-CONFIG_MFD_WL1273_CORE=m
-CONFIG_MFD_LM3533=m
-# CONFIG_MFD_TC3589X is not set
-CONFIG_MFD_TQMX86=m
-CONFIG_MFD_VX855=m
-CONFIG_MFD_LOCHNAGAR=y
-# CONFIG_MFD_ARIZONA_I2C is not set
-# CONFIG_MFD_ARIZONA_SPI is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X_I2C is not set
-# CONFIG_MFD_WM831X_SPI is not set
-# CONFIG_MFD_WM8350_I2C is not set
-CONFIG_MFD_WM8994=m
-CONFIG_MFD_ROHM_BD718XX=m
-CONFIG_MFD_ROHM_BD70528=m
-CONFIG_MFD_ROHM_BD71828=m
-CONFIG_MFD_ROHM_BD957XMUF=m
-CONFIG_MFD_STPMIC1=m
-CONFIG_MFD_STMFX=m
-CONFIG_MFD_WCD934X=m
-CONFIG_MFD_ATC260X=m
-CONFIG_MFD_ATC260X_I2C=m
-CONFIG_MFD_KHADAS_MCU=m
-CONFIG_MFD_QCOM_PM8008=m
-CONFIG_MFD_VEXPRESS_SYSREG=y
-# CONFIG_RAVE_SP_CORE is not set
-# CONFIG_MFD_INTEL_M10_BMC is not set
-# CONFIG_MFD_RSMU_I2C is not set
-# CONFIG_MFD_RSMU_SPI is not set
-# end of Multifunction device drivers
-
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=m
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-CONFIG_REGULATOR_88PG86X=m
-# CONFIG_REGULATOR_ACT8865 is not set
-# CONFIG_REGULATOR_AD5398 is not set
-# CONFIG_REGULATOR_ANATOP is not set
-CONFIG_REGULATOR_ARIZONA_LDO1=m
-CONFIG_REGULATOR_ARIZONA_MICSUPP=m
-CONFIG_REGULATOR_ARM_SCMI=m
-CONFIG_REGULATOR_ATC260X=m
-CONFIG_REGULATOR_AXP20X=m
-CONFIG_REGULATOR_BD71815=m
-CONFIG_REGULATOR_BD71828=m
-CONFIG_REGULATOR_BD718XX=m
-CONFIG_REGULATOR_BD9571MWV=m
-CONFIG_REGULATOR_BD957XMUF=m
-CONFIG_REGULATOR_CPCAP=m
-CONFIG_REGULATOR_CROS_EC=m
-CONFIG_REGULATOR_DA9121=m
-# CONFIG_REGULATOR_DA9210 is not set
-# CONFIG_REGULATOR_DA9211 is not set
-CONFIG_REGULATOR_FAN53555=m
-CONFIG_REGULATOR_FAN53880=m
-CONFIG_REGULATOR_GPIO=m
-CONFIG_REGULATOR_HI6421=m
-CONFIG_REGULATOR_HI6421V530=m
-CONFIG_REGULATOR_HI655X=m
-CONFIG_REGULATOR_HI6421V600=m
-CONFIG_REGULATOR_ISL9305=m
-# CONFIG_REGULATOR_ISL6271A is not set
-CONFIG_REGULATOR_LM363X=m
-CONFIG_REGULATOR_LOCHNAGAR=m
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_LP3972 is not set
-# CONFIG_REGULATOR_LP872X is not set
-CONFIG_REGULATOR_LP873X=m
-# CONFIG_REGULATOR_LP8755 is not set
-CONFIG_REGULATOR_LP87565=m
-CONFIG_REGULATOR_LTC3589=m
-CONFIG_REGULATOR_LTC3676=m
-# CONFIG_REGULATOR_MAX1586 is not set
-CONFIG_REGULATOR_MAX77620=m
-CONFIG_REGULATOR_MAX77650=m
-# CONFIG_REGULATOR_MAX8649 is not set
-# CONFIG_REGULATOR_MAX8660 is not set
-CONFIG_REGULATOR_MAX8893=m
-# CONFIG_REGULATOR_MAX8952 is not set
-# CONFIG_REGULATOR_MAX8973 is not set
-CONFIG_REGULATOR_MAX77826=m
-CONFIG_REGULATOR_MCP16502=m
-CONFIG_REGULATOR_MP5416=m
-CONFIG_REGULATOR_MP8859=y
-CONFIG_REGULATOR_MP886X=m
-CONFIG_REGULATOR_MPQ7920=m
-# CONFIG_REGULATOR_MT6311 is not set
-CONFIG_REGULATOR_MT6315=m
-CONFIG_REGULATOR_MT6360=m
-CONFIG_REGULATOR_MT6370=m
-CONFIG_REGULATOR_MT6380=m
-CONFIG_REGULATOR_PCA9450=m
-CONFIG_REGULATOR_PF8X00=m
-CONFIG_REGULATOR_PFUZE100=m
-# CONFIG_REGULATOR_PV88060 is not set
-# CONFIG_REGULATOR_PV88080 is not set
-# CONFIG_REGULATOR_PV88090 is not set
-CONFIG_REGULATOR_PWM=y
-CONFIG_REGULATOR_QCOM_RPM=m
-CONFIG_REGULATOR_QCOM_RPMH=m
-CONFIG_REGULATOR_QCOM_SMD_RPM=m
-CONFIG_REGULATOR_QCOM_SPMI=m
-CONFIG_REGULATOR_QCOM_USB_VBUS=m
-CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
-CONFIG_REGULATOR_RK808=y
-CONFIG_REGULATOR_ROHM=m
-CONFIG_REGULATOR_RT4801=m
-CONFIG_REGULATOR_RT4831=m
-CONFIG_REGULATOR_RT5120=m
-CONFIG_REGULATOR_RT5190A=m
-CONFIG_REGULATOR_RT6160=m
-CONFIG_REGULATOR_RT6245=m
-CONFIG_REGULATOR_RTQ2134=m
-CONFIG_REGULATOR_RTMV20=m
-CONFIG_REGULATOR_RTQ6752=m
-CONFIG_REGULATOR_SC2731=m
-CONFIG_REGULATOR_SKY81452=m
-CONFIG_REGULATOR_SLG51000=m
-CONFIG_REGULATOR_SY7636A=m
-CONFIG_REGULATOR_STPMIC1=m
-CONFIG_REGULATOR_SY8106A=m
-CONFIG_REGULATOR_SY8824X=m
-CONFIG_REGULATOR_SY8827N=m
-# CONFIG_REGULATOR_TPS51632 is not set
-# CONFIG_REGULATOR_TPS62360 is not set
-CONFIG_REGULATOR_TPS6286X=m
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-CONFIG_REGULATOR_TPS65132=m
-# CONFIG_REGULATOR_TPS6524X is not set
-CONFIG_REGULATOR_UNIPHIER=m
-CONFIG_REGULATOR_VCTRL=m
-CONFIG_REGULATOR_VEXPRESS=m
-CONFIG_REGULATOR_VQMMC_IPQ4019=m
-CONFIG_REGULATOR_WM8994=m
-CONFIG_REGULATOR_QCOM_LABIBB=m
-CONFIG_RC_CORE=m
-CONFIG_RC_MAP=m
-CONFIG_LIRC=y
-CONFIG_RC_DECODERS=y
-CONFIG_IR_NEC_DECODER=m
-CONFIG_IR_RC5_DECODER=m
-CONFIG_IR_RC6_DECODER=m
-CONFIG_IR_JVC_DECODER=m
-CONFIG_IR_SONY_DECODER=m
-CONFIG_IR_SANYO_DECODER=m
-CONFIG_IR_SHARP_DECODER=m
-CONFIG_IR_MCE_KBD_DECODER=m
-CONFIG_IR_XMP_DECODER=m
-CONFIG_IR_IMON_DECODER=m
-CONFIG_IR_RCMM_DECODER=m
-CONFIG_RC_DEVICES=y
-CONFIG_RC_ATI_REMOTE=m
-# CONFIG_IR_ENE is not set
-CONFIG_IR_HIX5HD2=m
-CONFIG_IR_IMON=m
-CONFIG_IR_IMON_RAW=m
-CONFIG_IR_MCEUSB=m
-# CONFIG_IR_ITE_CIR is not set
-# CONFIG_IR_FINTEK is not set
-CONFIG_IR_MESON=m
-CONFIG_IR_MESON_TX=m
-CONFIG_IR_MTK=m
-# CONFIG_IR_NUVOTON is not set
-CONFIG_IR_REDRAT3=m
-CONFIG_IR_SPI=m
-CONFIG_IR_STREAMZAP=m
-CONFIG_IR_IGORPLUGUSB=m
-CONFIG_IR_IGUANA=m
-CONFIG_IR_TTUSBIR=m
-CONFIG_RC_LOOPBACK=m
-CONFIG_IR_GPIO_CIR=m
-CONFIG_IR_GPIO_TX=m
-CONFIG_IR_PWM_TX=m
-CONFIG_IR_SUNXI=m
-CONFIG_IR_SERIAL=m
-CONFIG_IR_SERIAL_TRANSMITTER=y
-CONFIG_RC_XBOX_DVD=m
-CONFIG_IR_TOY=m
-CONFIG_CEC_CORE=y
-CONFIG_CEC_NOTIFIER=y
-CONFIG_CEC_PIN=y
-
-#
-# CEC support
-#
-# CONFIG_CEC_PIN_ERROR_INJ is not set
-CONFIG_MEDIA_CEC_SUPPORT=y
-CONFIG_CEC_CH7322=m
-CONFIG_CEC_CROS_EC=m
-CONFIG_CEC_MESON_AO=m
-CONFIG_CEC_MESON_G12A_AO=m
-CONFIG_CEC_GPIO=m
-CONFIG_CEC_SAMSUNG_S5P=m
-CONFIG_CEC_TEGRA=m
-CONFIG_USB_PULSE8_CEC=m
-CONFIG_USB_RAINSHADOW_CEC=m
-# end of CEC support
-
-CONFIG_MEDIA_SUPPORT=m
-CONFIG_MEDIA_SUPPORT_FILTER=y
-CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
-
-#
-# Media device types
-#
-CONFIG_MEDIA_PLATFORM_DRIVERS=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_SDR_SUPPORT=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-# CONFIG_MEDIA_TEST_SUPPORT is not set
-# end of Media device types
-
-CONFIG_VIDEO_DEV=m
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_DVB_CORE=m
-
-#
-# Video4Linux options
-#
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L2_I2C=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_TUNER=m
-CONFIG_V4L2_JPEG_HELPER=m
-CONFIG_V4L2_H264=m
-CONFIG_V4L2_MEM2MEM_DEV=m
-# CONFIG_V4L2_FLASH_LED_CLASS is not set
-CONFIG_V4L2_FWNODE=m
-CONFIG_V4L2_ASYNC=m
-CONFIG_VIDEOBUF_GEN=m
-CONFIG_VIDEOBUF_DMA_SG=m
-CONFIG_VIDEOBUF_VMALLOC=m
-# end of Video4Linux options
-
-#
-# Media controller options
-#
-CONFIG_MEDIA_CONTROLLER_DVB=y
-CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
-# end of Media controller options
-
-#
-# Digital TV options
-#
-# CONFIG_DVB_MMAP is not set
-CONFIG_DVB_NET=y
-CONFIG_DVB_MAX_ADAPTERS=8
-CONFIG_DVB_DYNAMIC_MINORS=y
-# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
-# CONFIG_DVB_ULE_DEBUG is not set
-# end of Digital TV options
-
-#
-# Media drivers
-#
-
-#
-# Drivers filtered as selected at 'Filter media drivers'
-#
-CONFIG_MEDIA_USB_SUPPORT=y
-
-#
-# Webcam devices
-#
-CONFIG_USB_VIDEO_CLASS=m
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-CONFIG_USB_M5602=m
-CONFIG_USB_STV06XX=m
-CONFIG_USB_GL860=m
-CONFIG_USB_GSPCA_BENQ=m
-CONFIG_USB_GSPCA_CONEX=m
-CONFIG_USB_GSPCA_CPIA1=m
-CONFIG_USB_GSPCA_DTCS033=m
-CONFIG_USB_GSPCA_ETOMS=m
-CONFIG_USB_GSPCA_FINEPIX=m
-CONFIG_USB_GSPCA_JEILINJ=m
-CONFIG_USB_GSPCA_JL2005BCD=m
-CONFIG_USB_GSPCA_KINECT=m
-CONFIG_USB_GSPCA_KONICA=m
-CONFIG_USB_GSPCA_MARS=m
-CONFIG_USB_GSPCA_MR97310A=m
-CONFIG_USB_GSPCA_NW80X=m
-CONFIG_USB_GSPCA_OV519=m
-CONFIG_USB_GSPCA_OV534=m
-CONFIG_USB_GSPCA_OV534_9=m
-CONFIG_USB_GSPCA_PAC207=m
-CONFIG_USB_GSPCA_PAC7302=m
-CONFIG_USB_GSPCA_PAC7311=m
-CONFIG_USB_GSPCA_SE401=m
-CONFIG_USB_GSPCA_SN9C2028=m
-CONFIG_USB_GSPCA_SN9C20X=m
-CONFIG_USB_GSPCA_SONIXB=m
-CONFIG_USB_GSPCA_SONIXJ=m
-CONFIG_USB_GSPCA_SPCA500=m
-CONFIG_USB_GSPCA_SPCA501=m
-CONFIG_USB_GSPCA_SPCA505=m
-CONFIG_USB_GSPCA_SPCA506=m
-CONFIG_USB_GSPCA_SPCA508=m
-CONFIG_USB_GSPCA_SPCA561=m
-CONFIG_USB_GSPCA_SPCA1528=m
-CONFIG_USB_GSPCA_SQ905=m
-CONFIG_USB_GSPCA_SQ905C=m
-CONFIG_USB_GSPCA_SQ930X=m
-CONFIG_USB_GSPCA_STK014=m
-CONFIG_USB_GSPCA_STK1135=m
-CONFIG_USB_GSPCA_STV0680=m
-CONFIG_USB_GSPCA_SUNPLUS=m
-CONFIG_USB_GSPCA_T613=m
-CONFIG_USB_GSPCA_TOPRO=m
-CONFIG_USB_GSPCA_TOUPTEK=m
-CONFIG_USB_GSPCA_TV8532=m
-CONFIG_USB_GSPCA_VC032X=m
-CONFIG_USB_GSPCA_VICAM=m
-CONFIG_USB_GSPCA_XIRLINK_CIT=m
-CONFIG_USB_GSPCA_ZC3XX=m
-CONFIG_USB_PWC=m
-# CONFIG_USB_PWC_DEBUG is not set
-CONFIG_USB_PWC_INPUT_EVDEV=y
-CONFIG_VIDEO_CPIA2=m
-CONFIG_USB_ZR364XX=m
-CONFIG_USB_STKWEBCAM=m
-CONFIG_USB_S2255=m
-CONFIG_VIDEO_USBTV=m
-
-#
-# Analog TV USB devices
-#
-CONFIG_VIDEO_PVRUSB2=m
-CONFIG_VIDEO_PVRUSB2_SYSFS=y
-CONFIG_VIDEO_PVRUSB2_DVB=y
-# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
-CONFIG_VIDEO_HDPVR=m
-CONFIG_VIDEO_STK1160_COMMON=m
-CONFIG_VIDEO_STK1160=m
-CONFIG_VIDEO_GO7007=m
-CONFIG_VIDEO_GO7007_USB=m
-CONFIG_VIDEO_GO7007_LOADER=m
-CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
-
-#
-# Analog/digital TV USB devices
-#
-CONFIG_VIDEO_AU0828=m
-CONFIG_VIDEO_AU0828_V4L2=y
-CONFIG_VIDEO_AU0828_RC=y
-CONFIG_VIDEO_CX231XX=m
-CONFIG_VIDEO_CX231XX_RC=y
-CONFIG_VIDEO_CX231XX_ALSA=m
-CONFIG_VIDEO_CX231XX_DVB=m
-CONFIG_VIDEO_TM6000=m
-CONFIG_VIDEO_TM6000_ALSA=m
-CONFIG_VIDEO_TM6000_DVB=m
-
-#
-# Digital TV USB devices
-#
-CONFIG_DVB_USB=m
-# CONFIG_DVB_USB_DEBUG is not set
-CONFIG_DVB_USB_DIB3000MC=m
-CONFIG_DVB_USB_A800=m
-CONFIG_DVB_USB_DIBUSB_MB=m
-# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
-CONFIG_DVB_USB_DIBUSB_MC=m
-CONFIG_DVB_USB_DIB0700=m
-CONFIG_DVB_USB_UMT_010=m
-CONFIG_DVB_USB_CXUSB=m
-CONFIG_DVB_USB_CXUSB_ANALOG=y
-CONFIG_DVB_USB_M920X=m
-CONFIG_DVB_USB_DIGITV=m
-CONFIG_DVB_USB_VP7045=m
-CONFIG_DVB_USB_VP702X=m
-CONFIG_DVB_USB_GP8PSK=m
-CONFIG_DVB_USB_NOVA_T_USB2=m
-CONFIG_DVB_USB_TTUSB2=m
-CONFIG_DVB_USB_DTT200U=m
-CONFIG_DVB_USB_OPERA1=m
-CONFIG_DVB_USB_AF9005=m
-CONFIG_DVB_USB_AF9005_REMOTE=m
-CONFIG_DVB_USB_PCTV452E=m
-CONFIG_DVB_USB_DW2102=m
-CONFIG_DVB_USB_CINERGY_T2=m
-CONFIG_DVB_USB_DTV5100=m
-CONFIG_DVB_USB_AZ6027=m
-CONFIG_DVB_USB_TECHNISAT_USB2=m
-CONFIG_DVB_USB_V2=m
-CONFIG_DVB_USB_AF9015=m
-CONFIG_DVB_USB_AF9035=m
-CONFIG_DVB_USB_ANYSEE=m
-CONFIG_DVB_USB_AU6610=m
-CONFIG_DVB_USB_AZ6007=m
-CONFIG_DVB_USB_CE6230=m
-CONFIG_DVB_USB_EC168=m
-CONFIG_DVB_USB_GL861=m
-CONFIG_DVB_USB_LME2510=m
-CONFIG_DVB_USB_MXL111SF=m
-CONFIG_DVB_USB_RTL28XXU=m
-CONFIG_DVB_USB_DVBSKY=m
-CONFIG_DVB_USB_ZD1301=m
-CONFIG_DVB_TTUSB_BUDGET=m
-CONFIG_DVB_TTUSB_DEC=m
-CONFIG_SMS_USB_DRV=m
-CONFIG_DVB_B2C2_FLEXCOP_USB=m
-# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
-CONFIG_DVB_AS102=m
-
-#
-# Webcam, TV (analog/digital) USB devices
-#
-CONFIG_VIDEO_EM28XX=m
-CONFIG_VIDEO_EM28XX_V4L2=m
-CONFIG_VIDEO_EM28XX_ALSA=m
-CONFIG_VIDEO_EM28XX_DVB=m
-CONFIG_VIDEO_EM28XX_RC=m
-
-#
-# Software defined radio USB devices
-#
-CONFIG_USB_AIRSPY=m
-CONFIG_USB_HACKRF=m
-CONFIG_USB_MSI2500=m
-CONFIG_MEDIA_PCI_SUPPORT=y
-
-#
-# Media capture support
-#
-CONFIG_VIDEO_SOLO6X10=m
-CONFIG_VIDEO_TW5864=m
-CONFIG_VIDEO_TW68=m
-CONFIG_VIDEO_TW686X=m
-
-#
-# Media capture/analog TV support
-#
-CONFIG_VIDEO_IVTV=m
-CONFIG_VIDEO_IVTV_ALSA=m
-CONFIG_VIDEO_FB_IVTV=m
-CONFIG_VIDEO_HEXIUM_GEMINI=m
-CONFIG_VIDEO_HEXIUM_ORION=m
-CONFIG_VIDEO_MXB=m
-CONFIG_VIDEO_DT3155=m
-
-#
-# Media capture/analog/hybrid TV support
-#
-CONFIG_VIDEO_CX18=m
-CONFIG_VIDEO_CX18_ALSA=m
-CONFIG_VIDEO_CX23885=m
-CONFIG_MEDIA_ALTERA_CI=m
-CONFIG_VIDEO_CX25821=m
-CONFIG_VIDEO_CX25821_ALSA=m
-CONFIG_VIDEO_CX88=m
-CONFIG_VIDEO_CX88_ALSA=m
-CONFIG_VIDEO_CX88_BLACKBIRD=m
-CONFIG_VIDEO_CX88_DVB=m
-CONFIG_VIDEO_CX88_ENABLE_VP3054=y
-CONFIG_VIDEO_CX88_VP3054=m
-CONFIG_VIDEO_CX88_MPEG=m
-CONFIG_VIDEO_BT848=m
-CONFIG_DVB_BT8XX=m
-CONFIG_VIDEO_SAA7134=m
-CONFIG_VIDEO_SAA7134_ALSA=m
-CONFIG_VIDEO_SAA7134_RC=y
-CONFIG_VIDEO_SAA7134_DVB=m
-CONFIG_VIDEO_SAA7134_GO7007=m
-CONFIG_VIDEO_SAA7164=m
-
-#
-# Media digital TV PCI Adapters
-#
-CONFIG_DVB_BUDGET_CORE=m
-CONFIG_DVB_BUDGET=m
-CONFIG_DVB_BUDGET_CI=m
-CONFIG_DVB_BUDGET_AV=m
-CONFIG_DVB_B2C2_FLEXCOP_PCI=m
-# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
-CONFIG_DVB_PLUTO2=m
-CONFIG_DVB_DM1105=m
-CONFIG_DVB_PT1=m
-CONFIG_DVB_PT3=m
-CONFIG_MANTIS_CORE=m
-CONFIG_DVB_MANTIS=m
-CONFIG_DVB_HOPPER=m
-CONFIG_DVB_NGENE=m
-CONFIG_DVB_DDBRIDGE=m
-# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set
-CONFIG_DVB_SMIPCIE=m
-CONFIG_DVB_NETUP_UNIDVB=m
-CONFIG_RADIO_ADAPTERS=y
-CONFIG_RADIO_TEA575X=m
-CONFIG_RADIO_SI470X=m
-CONFIG_USB_SI470X=m
-# CONFIG_I2C_SI470X is not set
-CONFIG_RADIO_SI4713=m
-CONFIG_USB_SI4713=m
-CONFIG_PLATFORM_SI4713=m
-CONFIG_I2C_SI4713=m
-CONFIG_USB_MR800=m
-CONFIG_USB_DSBR=m
-CONFIG_RADIO_MAXIRADIO=m
-CONFIG_RADIO_SHARK=m
-CONFIG_RADIO_SHARK2=m
-CONFIG_USB_KEENE=m
-CONFIG_USB_RAREMONO=m
-CONFIG_USB_MA901=m
-CONFIG_RADIO_TEA5764=m
-CONFIG_RADIO_SAA7706H=m
-CONFIG_RADIO_TEF6862=m
-CONFIG_RADIO_WL1273=m
-CONFIG_RADIO_WL128X=m
-CONFIG_MEDIA_COMMON_OPTIONS=y
-
-#
-# common driver options
-#
-CONFIG_VIDEO_CX2341X=m
-CONFIG_VIDEO_TVEEPROM=m
-CONFIG_TTPCI_EEPROM=m
-CONFIG_CYPRESS_FIRMWARE=m
-CONFIG_VIDEOBUF2_CORE=m
-CONFIG_VIDEOBUF2_V4L2=m
-CONFIG_VIDEOBUF2_MEMOPS=m
-CONFIG_VIDEOBUF2_DMA_CONTIG=m
-CONFIG_VIDEOBUF2_VMALLOC=m
-CONFIG_VIDEOBUF2_DMA_SG=m
-CONFIG_VIDEOBUF2_DVB=m
-CONFIG_DVB_B2C2_FLEXCOP=m
-CONFIG_VIDEO_SAA7146=m
-CONFIG_VIDEO_SAA7146_VV=m
-CONFIG_SMS_SIANO_MDTV=m
-CONFIG_SMS_SIANO_RC=y
-# CONFIG_SMS_SIANO_DEBUGFS is not set
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_CAFE_CCIC=m
-CONFIG_VIDEO_CADENCE=y
-CONFIG_VIDEO_CADENCE_CSI2RX=m
-CONFIG_VIDEO_CADENCE_CSI2TX=m
-CONFIG_VIDEO_ASPEED=m
-CONFIG_VIDEO_MUX=m
-CONFIG_VIDEO_QCOM_CAMSS=m
-CONFIG_VIDEO_ROCKCHIP_ISP1=m
-# CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS is not set
-CONFIG_VIDEO_XILINX=m
-CONFIG_VIDEO_XILINX_CSI2RXSS=m
-# CONFIG_VIDEO_XILINX_TPG is not set
-CONFIG_VIDEO_XILINX_VTC=m
-CONFIG_VIDEO_RCAR_CSI2=m
-CONFIG_VIDEO_RCAR_VIN=m
-CONFIG_VIDEO_SUN4I_CSI=m
-# CONFIG_VIDEO_SUN6I_CSI is not set
-CONFIG_VIDEO_TI_CAL=m
-CONFIG_VIDEO_TI_CAL_MC=y
-CONFIG_VIDEO_RCAR_ISP=m
-CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_VIDEO_ALLEGRO_DVT=m
-CONFIG_VIDEO_CODA=m
-CONFIG_VIDEO_IMX_PXP=m
-CONFIG_VIDEO_DW100=m
-CONFIG_VIDEO_IMX8_JPEG=m
-CONFIG_VIDEO_MEDIATEK_JPEG=m
-CONFIG_VIDEO_MEDIATEK_VPU=m
-CONFIG_VIDEO_MEDIATEK_MDP3=m
-CONFIG_VIDEO_TEGRA_VDE=m
-CONFIG_VIDEO_IMX_MIPI_CSIS=m
-CONFIG_VIDEO_MEDIATEK_MDP=m
-CONFIG_VIDEO_MEDIATEK_VCODEC=m
-CONFIG_VIDEO_MEDIATEK_VCODEC_VPU=y
-CONFIG_VIDEO_MEDIATEK_VCODEC_SCP=y
-CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
-CONFIG_VIDEO_MESON_GE2D=m
-CONFIG_VIDEO_AMPHION_VPU=m
-CONFIG_VIDEO_SAMSUNG_S5P_G2D=m
-CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
-CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
-CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
-CONFIG_VIDEO_RENESAS_FDP1=m
-CONFIG_VIDEO_RENESAS_JPU=m
-CONFIG_VIDEO_RENESAS_FCP=m
-CONFIG_VIDEO_RENESAS_VSP1=m
-CONFIG_VIDEO_ROCKCHIP_IEP=m
-CONFIG_VIDEO_ROCKCHIP_RGA=m
-CONFIG_VIDEO_QCOM_VENUS=m
-CONFIG_VIDEO_SUN8I_DEINTERLACE=m
-CONFIG_VIDEO_SUN8I_ROTATE=m
-CONFIG_DVB_PLATFORM_DRIVERS=y
-CONFIG_SDR_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_RCAR_DRIF=m
-
-#
-# MMC/SDIO DVB adapters
-#
-CONFIG_SMS_SDIO_DRV=m
-
-#
-# FireWire (IEEE 1394) Adapters
-#
-CONFIG_DVB_FIREDTV=m
-CONFIG_DVB_FIREDTV_INPUT=y
-# end of Media drivers
-
-#
-# Media ancillary drivers
-#
-CONFIG_MEDIA_ATTACH=y
-
-#
-# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
-#
-CONFIG_VIDEO_IR_I2C=m
-
-#
-# Audio decoders, processors and mixers
-#
-CONFIG_VIDEO_TVAUDIO=m
-CONFIG_VIDEO_TDA7432=m
-CONFIG_VIDEO_TDA9840=m
-CONFIG_VIDEO_TDA1997X=m
-CONFIG_VIDEO_TEA6415C=m
-CONFIG_VIDEO_TEA6420=m
-CONFIG_VIDEO_MSP3400=m
-CONFIG_VIDEO_CS3308=m
-CONFIG_VIDEO_CS5345=m
-CONFIG_VIDEO_CS53L32A=m
-CONFIG_VIDEO_TLV320AIC23B=m
-CONFIG_VIDEO_UDA1342=m
-CONFIG_VIDEO_WM8775=m
-CONFIG_VIDEO_WM8739=m
-CONFIG_VIDEO_VP27SMPX=m
-CONFIG_VIDEO_SONY_BTF_MPX=m
-# end of Audio decoders, processors and mixers
-
-#
-# RDS decoders
-#
-CONFIG_VIDEO_SAA6588=m
-# end of RDS decoders
-
-#
-# Video decoders
-#
-CONFIG_VIDEO_ADV7180=m
-CONFIG_VIDEO_ADV7183=m
-CONFIG_VIDEO_ADV748X=m
-CONFIG_VIDEO_ADV7604=m
-CONFIG_VIDEO_ADV7604_CEC=y
-CONFIG_VIDEO_ADV7842=m
-CONFIG_VIDEO_ADV7842_CEC=y
-CONFIG_VIDEO_BT819=m
-CONFIG_VIDEO_BT856=m
-CONFIG_VIDEO_BT866=m
-CONFIG_VIDEO_ISL7998X=m
-CONFIG_VIDEO_KS0127=m
-CONFIG_VIDEO_ML86V7667=m
-CONFIG_VIDEO_SAA7110=m
-CONFIG_VIDEO_SAA711X=m
-CONFIG_VIDEO_TC358743=m
-CONFIG_VIDEO_TC358743_CEC=y
-CONFIG_VIDEO_TVP514X=m
-CONFIG_VIDEO_TVP5150=m
-CONFIG_VIDEO_TVP7002=m
-CONFIG_VIDEO_TW2804=m
-CONFIG_VIDEO_TW9903=m
-CONFIG_VIDEO_TW9906=m
-CONFIG_VIDEO_TW9910=m
-CONFIG_VIDEO_VPX3220=m
-CONFIG_VIDEO_MAX9286=m
-
-#
-# Video and audio decoders
-#
-CONFIG_VIDEO_SAA717X=m
-CONFIG_VIDEO_CX25840=m
-# end of Video decoders
-
-#
-# Video encoders
-#
-CONFIG_VIDEO_SAA7127=m
-CONFIG_VIDEO_SAA7185=m
-CONFIG_VIDEO_ADV7170=m
-CONFIG_VIDEO_ADV7175=m
-CONFIG_VIDEO_ADV7343=m
-CONFIG_VIDEO_ADV7393=m
-CONFIG_VIDEO_AD9389B=m
-CONFIG_VIDEO_AK881X=m
-CONFIG_VIDEO_THS8200=m
-# end of Video encoders
-
-#
-# Video improvement chips
-#
-CONFIG_VIDEO_UPD64031A=m
-CONFIG_VIDEO_UPD64083=m
-# end of Video improvement chips
-
-#
-# Audio/Video compression chips
-#
-CONFIG_VIDEO_SAA6752HS=m
-# end of Audio/Video compression chips
-
-#
-# SDR tuner chips
-#
-CONFIG_SDR_MAX2175=m
-# end of SDR tuner chips
-
-#
-# Miscellaneous helper chips
-#
-CONFIG_VIDEO_THS7303=m
-CONFIG_VIDEO_M52790=m
-CONFIG_VIDEO_I2C=m
-# CONFIG_VIDEO_ST_MIPID02 is not set
-# end of Miscellaneous helper chips
-
-#
-# Camera sensor devices
-#
-CONFIG_VIDEO_APTINA_PLL=m
-CONFIG_VIDEO_CCS_PLL=m
-CONFIG_VIDEO_HI556=m
-# CONFIG_VIDEO_HI846 is not set
-CONFIG_VIDEO_HI847=m
-CONFIG_VIDEO_IMX208=m
-CONFIG_VIDEO_IMX214=m
-CONFIG_VIDEO_IMX219=m
-CONFIG_VIDEO_IMX258=m
-CONFIG_VIDEO_IMX274=m
-CONFIG_VIDEO_IMX290=m
-CONFIG_VIDEO_IMX319=m
-CONFIG_VIDEO_IMX334=m
-CONFIG_VIDEO_IMX335=m
-CONFIG_VIDEO_IMX355=m
-CONFIG_VIDEO_IMX412=m
-CONFIG_VIDEO_OV02A10=m
-CONFIG_VIDEO_OV08D10=m
-CONFIG_VIDEO_OV2640=m
-CONFIG_VIDEO_OV2659=m
-CONFIG_VIDEO_OV2680=m
-CONFIG_VIDEO_OV2685=m
-CONFIG_VIDEO_OV2740=m
-CONFIG_VIDEO_OV5640=m
-CONFIG_VIDEO_OV5645=m
-CONFIG_VIDEO_OV5647=m
-CONFIG_VIDEO_OV5648=m
-CONFIG_VIDEO_OV6650=m
-CONFIG_VIDEO_OV5670=m
-CONFIG_VIDEO_OV5675=m
-CONFIG_VIDEO_OV5695=m
-CONFIG_VIDEO_OV7251=m
-CONFIG_VIDEO_OV772X=m
-CONFIG_VIDEO_OV7640=m
-CONFIG_VIDEO_OV7670=m
-CONFIG_VIDEO_OV7740=m
-CONFIG_VIDEO_OV8856=m
-CONFIG_VIDEO_OV8865=m
-CONFIG_VIDEO_OV9282=m
-CONFIG_VIDEO_OV9640=m
-CONFIG_VIDEO_OV9650=m
-CONFIG_VIDEO_OV9734=m
-CONFIG_VIDEO_OV13858=m
-# CONFIG_VIDEO_OV13B10 is not set
-CONFIG_VIDEO_VS6624=m
-CONFIG_VIDEO_MT9M001=m
-CONFIG_VIDEO_MT9M032=m
-CONFIG_VIDEO_MT9M111=m
-CONFIG_VIDEO_MT9P031=m
-CONFIG_VIDEO_MT9T001=m
-CONFIG_VIDEO_MT9T112=m
-CONFIG_VIDEO_MT9V011=m
-CONFIG_VIDEO_MT9V032=m
-CONFIG_VIDEO_MT9V111=m
-CONFIG_VIDEO_SR030PC30=m
-CONFIG_VIDEO_NOON010PC30=m
-CONFIG_VIDEO_OG01A1B=m
-CONFIG_VIDEO_M5MOLS=m
-CONFIG_VIDEO_MAX9271_LIB=m
-CONFIG_VIDEO_RDACM20=m
-CONFIG_VIDEO_RDACM21=m
-CONFIG_VIDEO_RJ54N1=m
-CONFIG_VIDEO_S5K6AA=m
-CONFIG_VIDEO_S5K6A3=m
-CONFIG_VIDEO_S5K4ECGX=m
-CONFIG_VIDEO_S5K5BAF=m
-CONFIG_VIDEO_CCS=m
-CONFIG_VIDEO_ET8EK8=m
-CONFIG_VIDEO_S5C73M3=m
-# end of Camera sensor devices
-
-#
-# Lens drivers
-#
-CONFIG_VIDEO_AD5820=m
-CONFIG_VIDEO_AK7375=m
-CONFIG_VIDEO_DW9714=m
-CONFIG_VIDEO_DW9768=m
-CONFIG_VIDEO_DW9807_VCM=m
-# end of Lens drivers
-
-#
-# Flash devices
-#
-CONFIG_VIDEO_ADP1653=m
-CONFIG_VIDEO_LM3560=m
-CONFIG_VIDEO_LM3646=m
-# end of Flash devices
-
-#
-# SPI helper chips
-#
-CONFIG_VIDEO_GS1662=m
-# end of SPI helper chips
-
-#
-# Media SPI Adapters
-#
-CONFIG_CXD2880_SPI_DRV=m
-# end of Media SPI Adapters
-
-CONFIG_MEDIA_TUNER=m
-
-#
-# Customize TV tuners
-#
-CONFIG_MEDIA_TUNER_SIMPLE=m
-CONFIG_MEDIA_TUNER_TDA18250=m
-CONFIG_MEDIA_TUNER_TDA8290=m
-CONFIG_MEDIA_TUNER_TDA827X=m
-CONFIG_MEDIA_TUNER_TDA18271=m
-CONFIG_MEDIA_TUNER_TDA9887=m
-CONFIG_MEDIA_TUNER_TEA5761=m
-CONFIG_MEDIA_TUNER_TEA5767=m
-CONFIG_MEDIA_TUNER_MSI001=m
-CONFIG_MEDIA_TUNER_MT20XX=m
-CONFIG_MEDIA_TUNER_MT2060=m
-CONFIG_MEDIA_TUNER_MT2063=m
-CONFIG_MEDIA_TUNER_MT2266=m
-CONFIG_MEDIA_TUNER_MT2131=m
-CONFIG_MEDIA_TUNER_QT1010=m
-CONFIG_MEDIA_TUNER_XC2028=m
-CONFIG_MEDIA_TUNER_XC5000=m
-CONFIG_MEDIA_TUNER_XC4000=m
-CONFIG_MEDIA_TUNER_MXL5005S=m
-CONFIG_MEDIA_TUNER_MXL5007T=m
-CONFIG_MEDIA_TUNER_MC44S803=m
-CONFIG_MEDIA_TUNER_MAX2165=m
-CONFIG_MEDIA_TUNER_TDA18218=m
-CONFIG_MEDIA_TUNER_FC0011=m
-CONFIG_MEDIA_TUNER_FC0012=m
-CONFIG_MEDIA_TUNER_FC0013=m
-CONFIG_MEDIA_TUNER_TDA18212=m
-CONFIG_MEDIA_TUNER_E4000=m
-CONFIG_MEDIA_TUNER_FC2580=m
-CONFIG_MEDIA_TUNER_M88RS6000T=m
-CONFIG_MEDIA_TUNER_TUA9001=m
-CONFIG_MEDIA_TUNER_SI2157=m
-CONFIG_MEDIA_TUNER_IT913X=m
-CONFIG_MEDIA_TUNER_R820T=m
-CONFIG_MEDIA_TUNER_MXL301RF=m
-CONFIG_MEDIA_TUNER_QM1D1C0042=m
-CONFIG_MEDIA_TUNER_QM1D1B0004=m
-# CONFIG_MEDIA_TUNER_AV201X is not set
-# CONFIG_MEDIA_TUNER_STV6120 is not set
-# end of Customize TV tuners
-
-#
-# Customise DVB Frontends
-#
-
-#
-# Multistandard (satellite) frontends
-#
-CONFIG_DVB_STB0899=m
-CONFIG_DVB_STB6100=m
-CONFIG_DVB_STV090x=m
-CONFIG_DVB_STV0910=m
-CONFIG_DVB_STV6110x=m
-CONFIG_DVB_STV6111=m
-CONFIG_DVB_MXL5XX=m
-CONFIG_DVB_M88DS3103=m
-
-#
-# Multistandard (cable + terrestrial) frontends
-#
-CONFIG_DVB_DRXK=m
-CONFIG_DVB_TDA18271C2DD=m
-CONFIG_DVB_SI2165=m
-CONFIG_DVB_MN88472=m
-CONFIG_DVB_MN88473=m
-
-#
-# DVB-S (satellite) frontends
-#
-CONFIG_DVB_CX24110=m
-CONFIG_DVB_CX24123=m
-CONFIG_DVB_MT312=m
-CONFIG_DVB_ZL10036=m
-CONFIG_DVB_ZL10039=m
-CONFIG_DVB_S5H1420=m
-CONFIG_DVB_STV0288=m
-CONFIG_DVB_STB6000=m
-CONFIG_DVB_STV0299=m
-CONFIG_DVB_STV6110=m
-CONFIG_DVB_STV0900=m
-CONFIG_DVB_TDA8083=m
-CONFIG_DVB_TDA10086=m
-CONFIG_DVB_TDA8261=m
-CONFIG_DVB_VES1X93=m
-CONFIG_DVB_TUNER_ITD1000=m
-CONFIG_DVB_TUNER_CX24113=m
-CONFIG_DVB_TDA826X=m
-CONFIG_DVB_TUA6100=m
-CONFIG_DVB_CX24116=m
-CONFIG_DVB_CX24117=m
-CONFIG_DVB_CX24120=m
-CONFIG_DVB_SI21XX=m
-CONFIG_DVB_TS2020=m
-CONFIG_DVB_DS3000=m
-CONFIG_DVB_MB86A16=m
-CONFIG_DVB_TDA10071=m
-
-#
-# DVB-T (terrestrial) frontends
-#
-CONFIG_DVB_SP887X=m
-CONFIG_DVB_CX22700=m
-CONFIG_DVB_CX22702=m
-CONFIG_DVB_S5H1432=m
-CONFIG_DVB_DRXD=m
-CONFIG_DVB_L64781=m
-CONFIG_DVB_TDA1004X=m
-CONFIG_DVB_NXT6000=m
-CONFIG_DVB_MT352=m
-CONFIG_DVB_ZL10353=m
-CONFIG_DVB_DIB3000MB=m
-CONFIG_DVB_DIB3000MC=m
-CONFIG_DVB_DIB7000M=m
-CONFIG_DVB_DIB7000P=m
-CONFIG_DVB_DIB9000=m
-CONFIG_DVB_TDA10048=m
-CONFIG_DVB_AF9013=m
-CONFIG_DVB_EC100=m
-CONFIG_DVB_STV0367=m
-CONFIG_DVB_CXD2820R=m
-CONFIG_DVB_CXD2841ER=m
-CONFIG_DVB_RTL2830=m
-CONFIG_DVB_RTL2832=m
-CONFIG_DVB_RTL2832_SDR=m
-CONFIG_DVB_SI2168=m
-CONFIG_DVB_AS102_FE=m
-CONFIG_DVB_ZD1301_DEMOD=m
-CONFIG_DVB_GP8PSK_FE=m
-CONFIG_DVB_CXD2880=m
-
-#
-# DVB-C (cable) frontends
-#
-CONFIG_DVB_VES1820=m
-CONFIG_DVB_TDA10021=m
-CONFIG_DVB_TDA10023=m
-CONFIG_DVB_STV0297=m
-
-#
-# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
-#
-CONFIG_DVB_NXT200X=m
-CONFIG_DVB_OR51211=m
-CONFIG_DVB_OR51132=m
-CONFIG_DVB_BCM3510=m
-CONFIG_DVB_LGDT330X=m
-CONFIG_DVB_LGDT3305=m
-CONFIG_DVB_LGDT3306A=m
-CONFIG_DVB_LG2160=m
-CONFIG_DVB_S5H1409=m
-CONFIG_DVB_AU8522=m
-CONFIG_DVB_AU8522_DTV=m
-CONFIG_DVB_AU8522_V4L=m
-CONFIG_DVB_S5H1411=m
-CONFIG_DVB_MXL692=m
-
-#
-# ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_S921=m
-CONFIG_DVB_DIB8000=m
-CONFIG_DVB_MB86A20S=m
-
-#
-# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_TC90522=m
-CONFIG_DVB_MN88443X=m
-
-#
-# Digital terrestrial only tuners/PLL
-#
-CONFIG_DVB_PLL=m
-CONFIG_DVB_TUNER_DIB0070=m
-CONFIG_DVB_TUNER_DIB0090=m
-
-#
-# SEC control devices for DVB-S
-#
-CONFIG_DVB_DRX39XYJ=m
-CONFIG_DVB_LNBH25=m
-CONFIG_DVB_LNBH29=m
-CONFIG_DVB_LNBP21=m
-CONFIG_DVB_LNBP22=m
-CONFIG_DVB_ISL6405=m
-CONFIG_DVB_ISL6421=m
-# CONFIG_DVB_ISL6422 is not set
-CONFIG_DVB_ISL6423=m
-CONFIG_DVB_A8293=m
-CONFIG_DVB_LGS8GL5=m
-CONFIG_DVB_LGS8GXX=m
-CONFIG_DVB_ATBM8830=m
-CONFIG_DVB_TDA665x=m
-CONFIG_DVB_IX2505V=m
-CONFIG_DVB_M88RS2000=m
-CONFIG_DVB_AF9033=m
-# CONFIG_DVB_TAS2101 is not set
-CONFIG_DVB_HORUS3A=m
-CONFIG_DVB_ASCOT2E=m
-CONFIG_DVB_HELENE=m
-
-#
-# Common Interface (EN50221) controller drivers
-#
-CONFIG_DVB_CXD2099=m
-CONFIG_DVB_SP2=m
-# end of Customise DVB Frontends
-# end of Media ancillary drivers
-
-#
-# Graphics support
-#
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=8
-CONFIG_TEGRA_HOST1X=m
-CONFIG_TEGRA_HOST1X_FIREWALL=y
-CONFIG_DRM=y
-CONFIG_DRM_MIPI_DBI=m
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_DP_AUX_BUS=m
-# CONFIG_DRM_DP_AUX_CHARDEV is not set
-# CONFIG_DRM_DEBUG_MM is not set
-# CONFIG_DRM_DEBUG_SELFTEST is not set
-CONFIG_DRM_KMS_HELPER=y
-# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
-# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
-CONFIG_DRM_LOAD_EDID_FIRMWARE=y
-CONFIG_DRM_DP_CEC=y
-CONFIG_DRM_TTM=m
-CONFIG_DRM_VRAM_HELPER=m
-CONFIG_DRM_TTM_HELPER=m
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-CONFIG_DRM_SCHED=m
-
-#
-# I2C encoder or helper chips
-#
-CONFIG_DRM_I2C_CH7006=m
-CONFIG_DRM_I2C_SIL164=m
-CONFIG_DRM_I2C_NXP_TDA998X=m
-CONFIG_DRM_I2C_NXP_TDA9950=m
-# end of I2C encoder or helper chips
-
-#
-# ARM devices
-#
-CONFIG_DRM_HDLCD=m
-# CONFIG_DRM_HDLCD_SHOW_UNDERRUN is not set
-CONFIG_DRM_MALI_DISPLAY=m
-CONFIG_DRM_KOMEDA=m
-# end of ARM devices
-
-CONFIG_DRM_RADEON=m
-CONFIG_DRM_RADEON_USERPTR=y
-CONFIG_DRM_AMDGPU=m
-CONFIG_DRM_AMDGPU_SI=y
-CONFIG_DRM_AMDGPU_CIK=y
-CONFIG_DRM_AMDGPU_USERPTR=y
-
-#
-# ACP (Audio CoProcessor) Configuration
-#
-CONFIG_DRM_AMD_ACP=y
-# end of ACP (Audio CoProcessor) Configuration
-
-#
-# Display Engine Configuration
-#
-CONFIG_DRM_AMD_DC=y
-CONFIG_DRM_AMD_DC_HDCP=y
-CONFIG_DRM_AMD_DC_SI=y
-# CONFIG_DEBUG_KERNEL_DC is not set
-# end of Display Engine Configuration
-
-CONFIG_HSA_AMD=y
-CONFIG_HSA_AMD_SVM=y
-CONFIG_DRM_NOUVEAU=m
-# CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT is not set
-CONFIG_NOUVEAU_PLATFORM_DRIVER=y
-CONFIG_NOUVEAU_DEBUG=5
-CONFIG_NOUVEAU_DEBUG_DEFAULT=3
-# CONFIG_NOUVEAU_DEBUG_MMU is not set
-# CONFIG_NOUVEAU_DEBUG_PUSH is not set
-CONFIG_DRM_NOUVEAU_BACKLIGHT=y
-CONFIG_DRM_NOUVEAU_SVM=y
-CONFIG_DRM_KMB_DISPLAY=m
-CONFIG_DRM_VGEM=m
-CONFIG_DRM_VKMS=m
-CONFIG_DRM_EXYNOS=m
-
-#
-# CRTCs
-#
-# CONFIG_DRM_EXYNOS_FIMD is not set
-# CONFIG_DRM_EXYNOS5433_DECON is not set
-# CONFIG_DRM_EXYNOS7_DECON is not set
-# CONFIG_DRM_EXYNOS_MIXER is not set
-# CONFIG_DRM_EXYNOS_VIDI is not set
-
-#
-# Encoders and Bridges
-#
-
-#
-# Sub-drivers
-#
-# CONFIG_DRM_EXYNOS_FIMC is not set
-# CONFIG_DRM_EXYNOS_ROTATOR is not set
-# CONFIG_DRM_EXYNOS_SCALER is not set
-CONFIG_DRM_ROCKCHIP=y
-CONFIG_ROCKCHIP_VOP=y
-CONFIG_ROCKCHIP_VOP2=y
-CONFIG_ROCKCHIP_ANALOGIX_DP=y
-CONFIG_ROCKCHIP_CDN_DP=y
-CONFIG_ROCKCHIP_DW_HDMI=y
-CONFIG_ROCKCHIP_DW_MIPI_DSI=y
-CONFIG_ROCKCHIP_INNO_HDMI=y
-CONFIG_ROCKCHIP_LVDS=y
-CONFIG_ROCKCHIP_RGB=y
-CONFIG_ROCKCHIP_RK3066_HDMI=y
-CONFIG_DRM_VMWGFX=m
-CONFIG_DRM_VMWGFX_FBCON=y
-CONFIG_DRM_UDL=m
-# CONFIG_DRM_AST is not set
-# CONFIG_DRM_MGAG200 is not set
-CONFIG_DRM_RCAR_DU=m
-CONFIG_DRM_RCAR_USE_CMM=y
-CONFIG_DRM_RCAR_CMM=m
-CONFIG_DRM_RCAR_DW_HDMI=m
-CONFIG_DRM_RCAR_LVDS=m
-CONFIG_DRM_RCAR_VSP=y
-CONFIG_DRM_RCAR_WRITEBACK=y
-CONFIG_DRM_SUN4I=m
-CONFIG_DRM_SUN4I_HDMI=m
-CONFIG_DRM_SUN4I_HDMI_CEC=y
-CONFIG_DRM_SUN4I_BACKEND=m
-CONFIG_DRM_SUN6I_DSI=m
-CONFIG_DRM_SUN8I_DW_HDMI=m
-CONFIG_DRM_SUN8I_MIXER=m
-CONFIG_DRM_SUN8I_TCON_TOP=m
-# CONFIG_DRM_QXL is not set
-CONFIG_DRM_VIRTIO_GPU=m
-CONFIG_DRM_MSM=m
-CONFIG_DRM_MSM_GPU_STATE=y
-# CONFIG_DRM_MSM_REGISTER_LOGGING is not set
-# CONFIG_DRM_MSM_GPU_SUDO is not set
-CONFIG_DRM_MSM_MDP4=y
-CONFIG_DRM_MSM_MDP5=y
-CONFIG_DRM_MSM_DPU=y
-CONFIG_DRM_MSM_HDMI_HDCP=y
-CONFIG_DRM_MSM_DP=y
-CONFIG_DRM_MSM_DSI=y
-CONFIG_DRM_MSM_DSI_28NM_PHY=y
-CONFIG_DRM_MSM_DSI_20NM_PHY=y
-CONFIG_DRM_MSM_DSI_28NM_8960_PHY=y
-CONFIG_DRM_MSM_DSI_14NM_PHY=y
-CONFIG_DRM_MSM_DSI_10NM_PHY=y
-CONFIG_DRM_MSM_DSI_7NM_PHY=y
-CONFIG_DRM_MSM_HDMI=y
-CONFIG_DRM_TEGRA=m
-# CONFIG_DRM_TEGRA_DEBUG is not set
-# CONFIG_DRM_TEGRA_STAGING is not set
-CONFIG_DRM_PANEL=y
-
-#
-# Display Panels
-#
-CONFIG_DRM_PANEL_ABT_Y030XX067A=m
-CONFIG_DRM_PANEL_ARM_VERSATILE=m
-CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
-CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
-CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
-CONFIG_DRM_PANEL_DSI_CM=m
-CONFIG_DRM_PANEL_LVDS=m
-CONFIG_DRM_PANEL_SIMPLE=m
-CONFIG_DRM_PANEL_EDP=m
-CONFIG_DRM_PANEL_ELIDA_KD35T133=m
-CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
-CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
-CONFIG_DRM_PANEL_ILITEK_IL9322=m
-CONFIG_DRM_PANEL_ILITEK_ILI9341=m
-CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
-CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
-CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
-CONFIG_DRM_PANEL_JDI_LT070ME05000=m
-CONFIG_DRM_PANEL_KHADAS_TS050=m
-CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
-CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
-CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
-CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
-CONFIG_DRM_PANEL_LG_LB035Q02=m
-CONFIG_DRM_PANEL_LG_LG4573=m
-CONFIG_DRM_PANEL_NEC_NL8048HL11=m
-CONFIG_DRM_PANEL_NOVATEK_NT35510=m
-CONFIG_DRM_PANEL_NOVATEK_NT35560=m
-CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
-CONFIG_DRM_PANEL_NOVATEK_NT39016=m
-CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
-CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
-CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
-CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
-CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
-CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
-CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
-CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
-CONFIG_DRM_PANEL_RONBO_RB070D30=m
-CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
-CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
-CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
-CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
-CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
-CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
-CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
-CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
-CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
-CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
-CONFIG_DRM_PANEL_SITRONIX_ST7701=m
-CONFIG_DRM_PANEL_SITRONIX_ST7703=m
-CONFIG_DRM_PANEL_SITRONIX_ST7789V=m
-CONFIG_DRM_PANEL_SONY_ACX424AKP=m
-CONFIG_DRM_PANEL_SONY_ACX565AKM=m
-CONFIG_DRM_PANEL_TDO_TL070WSH30=m
-CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
-CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
-CONFIG_DRM_PANEL_TPO_TPG110=m
-CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
-CONFIG_DRM_PANEL_VISIONOX_RM69299=m
-CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
-CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
-# end of Display Panels
-
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_PANEL_BRIDGE=y
-
-#
-# Display Interface Bridges
-#
-CONFIG_DRM_CDNS_DSI=m
-CONFIG_DRM_CHIPONE_ICN6211=m
-CONFIG_DRM_CHRONTEL_CH7033=m
-CONFIG_DRM_CROS_EC_ANX7688=m
-CONFIG_DRM_DISPLAY_CONNECTOR=m
-CONFIG_DRM_ITE_IT6505=m
-CONFIG_DRM_LONTIUM_LT8912B=m
-CONFIG_DRM_LONTIUM_LT9611=m
-CONFIG_DRM_LONTIUM_LT9611UXC=m
-CONFIG_DRM_ITE_IT66121=m
-CONFIG_DRM_LVDS_CODEC=m
-CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m
-CONFIG_DRM_NWL_MIPI_DSI=m
-CONFIG_DRM_NXP_PTN3460=m
-CONFIG_DRM_PARADE_PS8622=m
-CONFIG_DRM_PARADE_PS8640=m
-CONFIG_DRM_SIL_SII8620=m
-CONFIG_DRM_SII902X=m
-CONFIG_DRM_SII9234=m
-CONFIG_DRM_SIMPLE_BRIDGE=m
-CONFIG_DRM_THINE_THC63LVD1024=m
-CONFIG_DRM_TOSHIBA_TC358762=m
-CONFIG_DRM_TOSHIBA_TC358764=m
-CONFIG_DRM_TOSHIBA_TC358767=m
-CONFIG_DRM_TOSHIBA_TC358768=m
-CONFIG_DRM_TOSHIBA_TC358775=m
-CONFIG_DRM_TI_TFP410=m
-CONFIG_DRM_TI_SN65DSI83=m
-CONFIG_DRM_TI_SN65DSI86=m
-CONFIG_DRM_TI_TPD12S015=m
-CONFIG_DRM_ANALOGIX_ANX6345=m
-CONFIG_DRM_ANALOGIX_ANX78XX=m
-CONFIG_DRM_ANALOGIX_DP=y
-CONFIG_DRM_ANALOGIX_ANX7625=m
-CONFIG_DRM_I2C_ADV7511=m
-CONFIG_DRM_I2C_ADV7511_AUDIO=y
-CONFIG_DRM_I2C_ADV7511_CEC=y
-CONFIG_DRM_CDNS_MHDP8546=m
-CONFIG_DRM_CDNS_MHDP8546_J721E=y
-CONFIG_DRM_DW_HDMI=y
-CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
-CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
-CONFIG_DRM_DW_HDMI_CEC=m
-CONFIG_DRM_DW_MIPI_DSI=y
-# end of Display Interface Bridges
-
-CONFIG_DRM_IMX_DCSS=m
-CONFIG_DRM_V3D=m
-CONFIG_DRM_VC4=m
-CONFIG_DRM_VC4_HDMI_CEC=y
-CONFIG_DRM_ETNAVIV=m
-CONFIG_DRM_ETNAVIV_THERMAL=y
-CONFIG_DRM_HISI_HIBMC=m
-CONFIG_DRM_HISI_KIRIN=m
-CONFIG_DRM_LOGICVC=m
-CONFIG_DRM_MEDIATEK=m
-CONFIG_DRM_MEDIATEK_DP=m
-CONFIG_DRM_MEDIATEK_HDMI=m
-CONFIG_DRM_MXS=y
-CONFIG_DRM_MXSFB=m
-CONFIG_DRM_IMX_LCDIF=m
-CONFIG_DRM_MESON=m
-CONFIG_DRM_MESON_DW_HDMI=m
-CONFIG_DRM_ARCPGU=m
-CONFIG_DRM_BOCHS=m
-CONFIG_DRM_CIRRUS_QEMU=m
-CONFIG_DRM_GM12U320=m
-CONFIG_DRM_PANEL_MIPI_DBI=m
-CONFIG_DRM_SIMPLEDRM=y
-CONFIG_TINYDRM_HX8357D=m
-CONFIG_TINYDRM_ILI9225=m
-CONFIG_TINYDRM_ILI9341=m
-CONFIG_TINYDRM_ILI9486=m
-CONFIG_TINYDRM_MI0283QT=m
-CONFIG_TINYDRM_REPAPER=m
-CONFIG_TINYDRM_ST7586=m
-CONFIG_TINYDRM_ST7735R=m
-CONFIG_DRM_PL111=m
-CONFIG_DRM_LIMA=m
-CONFIG_DRM_PANFROST=y
-CONFIG_DRM_TIDSS=m
-CONFIG_DRM_ZYNQMP_DPSUB=m
-CONFIG_DRM_GUD=m
-CONFIG_DRM_SSD130X=m
-CONFIG_DRM_SSD130X_I2C=m
-CONFIG_DRM_SPRD=m
-CONFIG_DRM_HYPERV=m
-# CONFIG_DRM_LEGACY is not set
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-
-#
-# Frame buffer Devices
-#
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_NOTIFY=y
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_BACKLIGHT=m
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_CIRRUS is not set
-# CONFIG_FB_PM2 is not set
-# CONFIG_FB_ARMCLCD is not set
-# CONFIG_FB_IMX is not set
-# CONFIG_FB_CYBER2000 is not set
-# CONFIG_FB_ASILIANT is not set
-# CONFIG_FB_IMSTT is not set
-# CONFIG_FB_UVESA is not set
-# CONFIG_FB_EFI is not set
-# CONFIG_FB_OPENCORES is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-# CONFIG_FB_I740 is not set
-# CONFIG_FB_MATROX is not set
-# CONFIG_FB_RADEON is not set
-# CONFIG_FB_ATY128 is not set
-# CONFIG_FB_ATY is not set
-# CONFIG_FB_S3 is not set
-# CONFIG_FB_SAVAGE is not set
-# CONFIG_FB_SIS is not set
-# CONFIG_FB_NEOMAGIC is not set
-# CONFIG_FB_KYRO is not set
-# CONFIG_FB_3DFX is not set
-# CONFIG_FB_VOODOO1 is not set
-# CONFIG_FB_VT8623 is not set
-# CONFIG_FB_TRIDENT is not set
-# CONFIG_FB_ARK is not set
-# CONFIG_FB_PM3 is not set
-# CONFIG_FB_CARMINE is not set
-# CONFIG_FB_SH_MOBILE_LCDC is not set
-# CONFIG_FB_SMSCUFX is not set
-# CONFIG_FB_UDL is not set
-# CONFIG_FB_IBM_GXT4500 is not set
-# CONFIG_FB_XILINX is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-# CONFIG_FB_MX3 is not set
-# CONFIG_FB_HYPERV is not set
-# CONFIG_FB_SSD1307 is not set
-# CONFIG_FB_SM712 is not set
-# end of Frame buffer Devices
-
-#
-# Backlight & LCD device support
-#
-CONFIG_LCD_CLASS_DEVICE=m
-CONFIG_LCD_L4F00242T03=m
-CONFIG_LCD_LMS283GF05=m
-CONFIG_LCD_LTV350QV=m
-CONFIG_LCD_ILI922X=m
-CONFIG_LCD_ILI9320=m
-CONFIG_LCD_TDO24M=m
-CONFIG_LCD_VGG2432A4=m
-CONFIG_LCD_PLATFORM=m
-CONFIG_LCD_AMS369FG06=m
-CONFIG_LCD_LMS501KF03=m
-CONFIG_LCD_HX8357=m
-CONFIG_LCD_OTM3225A=m
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_KTD253=m
-CONFIG_BACKLIGHT_LM3533=m
-CONFIG_BACKLIGHT_PWM=m
-CONFIG_BACKLIGHT_MT6370=m
-CONFIG_BACKLIGHT_QCOM_WLED=m
-CONFIG_BACKLIGHT_RT4831=m
-CONFIG_BACKLIGHT_ADP8860=m
-CONFIG_BACKLIGHT_ADP8870=m
-CONFIG_BACKLIGHT_LM3630A=m
-CONFIG_BACKLIGHT_LM3639=m
-CONFIG_BACKLIGHT_LP855X=m
-CONFIG_BACKLIGHT_SKY81452=m
-CONFIG_BACKLIGHT_GPIO=m
-CONFIG_BACKLIGHT_LV5207LP=m
-CONFIG_BACKLIGHT_BD6107=m
-CONFIG_BACKLIGHT_ARCXCNN=m
-CONFIG_BACKLIGHT_LED=m
-# end of Backlight & LCD device support
-
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_HDMI=y
-
-#
-# Console display driver support
-#
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DUMMY_CONSOLE_COLUMNS=80
-CONFIG_DUMMY_CONSOLE_ROWS=25
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
-# end of Console display driver support
-
-# CONFIG_LOGO is not set
-# end of Graphics support
-
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_PCM_ELD=y
-CONFIG_SND_PCM_IEC958=y
-CONFIG_SND_DMAENGINE_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_SEQ_DEVICE=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_COMPRESS_OFFLOAD=m
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_PCM_TIMER=y
-CONFIG_SND_HRTIMER=m
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_MAX_CARDS=32
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_PROC_FS=y
-CONFIG_SND_VERBOSE_PROCFS=y
-CONFIG_SND_CTL_FAST_LOOKUP=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_CTL_INPUT_VALIDATION=y
-CONFIG_SND_VMASTER=y
-CONFIG_SND_CTL_LED=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_SEQUENCER_OSS=m
-CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
-CONFIG_SND_SEQ_MIDI_EVENT=m
-CONFIG_SND_SEQ_MIDI=m
-CONFIG_SND_SEQ_MIDI_EMUL=m
-CONFIG_SND_SEQ_VIRMIDI=m
-CONFIG_SND_MPU401_UART=m
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_OPL3_LIB_SEQ=m
-CONFIG_SND_VX_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DRIVERS=y
-CONFIG_SND_DUMMY=m
-CONFIG_SND_ALOOP=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_MTS64=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_PORTMAN2X4=m
-CONFIG_SND_AC97_POWER_SAVE=y
-CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
-CONFIG_SND_PCI=y
-CONFIG_SND_AD1889=m
-# CONFIG_SND_ALS300 is not set
-# CONFIG_SND_ALI5451 is not set
-CONFIG_SND_ATIIXP=m
-CONFIG_SND_ATIIXP_MODEM=m
-CONFIG_SND_AU8810=m
-CONFIG_SND_AU8820=m
-CONFIG_SND_AU8830=m
-CONFIG_SND_AW2=m
-# CONFIG_SND_AZT3328 is not set
-CONFIG_SND_BT87X=m
-# CONFIG_SND_BT87X_OVERCLOCK is not set
-CONFIG_SND_CA0106=m
-CONFIG_SND_CMIPCI=m
-CONFIG_SND_OXYGEN_LIB=m
-CONFIG_SND_OXYGEN=m
-CONFIG_SND_CS4281=m
-CONFIG_SND_CS46XX=m
-CONFIG_SND_CS46XX_NEW_DSP=y
-CONFIG_SND_CTXFI=m
-CONFIG_SND_DARLA20=m
-CONFIG_SND_GINA20=m
-CONFIG_SND_LAYLA20=m
-CONFIG_SND_DARLA24=m
-CONFIG_SND_GINA24=m
-CONFIG_SND_LAYLA24=m
-CONFIG_SND_MONA=m
-CONFIG_SND_MIA=m
-CONFIG_SND_ECHO3G=m
-CONFIG_SND_INDIGO=m
-CONFIG_SND_INDIGOIO=m
-CONFIG_SND_INDIGODJ=m
-CONFIG_SND_INDIGOIOX=m
-CONFIG_SND_INDIGODJX=m
-# CONFIG_SND_EMU10K1 is not set
-# CONFIG_SND_EMU10K1X is not set
-CONFIG_SND_ENS1370=m
-CONFIG_SND_ENS1371=m
-# CONFIG_SND_ES1938 is not set
-# CONFIG_SND_ES1968 is not set
-CONFIG_SND_FM801=m
-CONFIG_SND_FM801_TEA575X_BOOL=y
-CONFIG_SND_HDSP=m
-CONFIG_SND_HDSPM=m
-# CONFIG_SND_ICE1712 is not set
-CONFIG_SND_ICE1724=m
-CONFIG_SND_INTEL8X0=m
-CONFIG_SND_INTEL8X0M=m
-CONFIG_SND_KORG1212=m
-CONFIG_SND_LOLA=m
-CONFIG_SND_LX6464ES=m
-# CONFIG_SND_MAESTRO3 is not set
-CONFIG_SND_MIXART=m
-CONFIG_SND_NM256=m
-CONFIG_SND_PCXHR=m
-CONFIG_SND_RIPTIDE=m
-CONFIG_SND_RME32=m
-CONFIG_SND_RME96=m
-CONFIG_SND_RME9652=m
-# CONFIG_SND_SONICVIBES is not set
-# CONFIG_SND_TRIDENT is not set
-CONFIG_SND_VIA82XX=m
-CONFIG_SND_VIA82XX_MODEM=m
-CONFIG_SND_VIRTUOSO=m
-CONFIG_SND_VX222=m
-CONFIG_SND_YMFPCI=m
-
-#
-# HD-Audio
-#
-CONFIG_SND_HDA=m
-CONFIG_SND_HDA_GENERIC_LEDS=y
-CONFIG_SND_HDA_INTEL=m
-CONFIG_SND_HDA_TEGRA=m
-CONFIG_SND_HDA_HWDEP=y
-CONFIG_SND_HDA_RECONFIG=y
-CONFIG_SND_HDA_INPUT_BEEP=y
-CONFIG_SND_HDA_INPUT_BEEP_MODE=1
-CONFIG_SND_HDA_PATCH_LOADER=y
-CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m
-CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m
-CONFIG_SND_HDA_CODEC_REALTEK=m
-CONFIG_SND_HDA_CODEC_ANALOG=m
-CONFIG_SND_HDA_CODEC_SIGMATEL=m
-CONFIG_SND_HDA_CODEC_VIA=m
-CONFIG_SND_HDA_CODEC_HDMI=m
-CONFIG_SND_HDA_CODEC_CIRRUS=m
-CONFIG_SND_HDA_CODEC_CS8409=m
-CONFIG_SND_HDA_CODEC_CONEXANT=m
-CONFIG_SND_HDA_CODEC_CA0110=m
-CONFIG_SND_HDA_CODEC_CA0132=m
-CONFIG_SND_HDA_CODEC_CA0132_DSP=y
-CONFIG_SND_HDA_CODEC_CMEDIA=m
-CONFIG_SND_HDA_CODEC_SI3054=m
-CONFIG_SND_HDA_GENERIC=m
-CONFIG_SND_HDA_POWER_SAVE_DEFAULT=1
-# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
-# end of HD-Audio
-
-CONFIG_SND_HDA_CORE=m
-CONFIG_SND_HDA_DSP_LOADER=y
-CONFIG_SND_HDA_ALIGNED_MMIO=y
-CONFIG_SND_HDA_COMPONENT=y
-CONFIG_SND_HDA_PREALLOC_SIZE=1024
-CONFIG_SND_INTEL_NHLT=y
-CONFIG_SND_INTEL_DSP_CONFIG=m
-CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m
-CONFIG_SND_SPI=y
-CONFIG_SND_USB=y
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
-CONFIG_SND_USB_UA101=m
-CONFIG_SND_USB_CAIAQ=m
-CONFIG_SND_USB_CAIAQ_INPUT=y
-CONFIG_SND_USB_6FIRE=m
-CONFIG_SND_USB_HIFACE=m
-CONFIG_SND_BCD2000=m
-CONFIG_SND_USB_LINE6=m
-CONFIG_SND_USB_POD=m
-CONFIG_SND_USB_PODHD=m
-CONFIG_SND_USB_TONEPORT=m
-CONFIG_SND_USB_VARIAX=m
-CONFIG_SND_FIREWIRE=y
-CONFIG_SND_FIREWIRE_LIB=m
-CONFIG_SND_DICE=m
-CONFIG_SND_OXFW=m
-CONFIG_SND_ISIGHT=m
-CONFIG_SND_FIREWORKS=m
-CONFIG_SND_BEBOB=m
-CONFIG_SND_FIREWIRE_DIGI00X=m
-CONFIG_SND_FIREWIRE_TASCAM=m
-CONFIG_SND_FIREWIRE_MOTU=m
-CONFIG_SND_FIREFACE=m
-CONFIG_SND_SOC=m
-CONFIG_SND_SOC_AC97_BUS=y
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_COMPRESS=y
-CONFIG_SND_SOC_TOPOLOGY=y
-CONFIG_SND_SOC_ADI=m
-CONFIG_SND_SOC_ADI_AXI_I2S=m
-CONFIG_SND_SOC_ADI_AXI_SPDIF=m
-CONFIG_SND_SOC_AMD_ACP=m
-CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m
-CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m
-CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
-# CONFIG_SND_ATMEL_SOC is not set
-CONFIG_SND_BCM2835_SOC_I2S=m
-CONFIG_SND_BCM63XX_I2S_WHISTLER=m
-CONFIG_SND_DESIGNWARE_I2S=m
-CONFIG_SND_DESIGNWARE_PCM=y
-
-#
-# SoC Audio for Freescale CPUs
-#
-
-#
-# Common SoC Audio options for Freescale CPUs:
-#
-CONFIG_SND_SOC_FSL_ASRC=m
-CONFIG_SND_SOC_FSL_SAI=m
-CONFIG_SND_SOC_FSL_MQS=m
-CONFIG_SND_SOC_FSL_AUDMIX=m
-CONFIG_SND_SOC_FSL_SSI=m
-CONFIG_SND_SOC_FSL_SPDIF=m
-CONFIG_SND_SOC_FSL_ESAI=m
-CONFIG_SND_SOC_FSL_MICFIL=m
-CONFIG_SND_SOC_FSL_EASRC=m
-# CONFIG_SND_SOC_FSL_XCVR is not set
-CONFIG_SND_SOC_FSL_AUD2HTX=m
-CONFIG_SND_SOC_FSL_RPMSG=m
-CONFIG_SND_SOC_IMX_PCM_DMA=m
-CONFIG_SND_SOC_IMX_AUDIO_RPMSG=m
-CONFIG_SND_SOC_IMX_PCM_RPMSG=m
-CONFIG_SND_SOC_IMX_AUDMUX=m
-CONFIG_SND_IMX_SOC=m
-
-#
-# SoC Audio support for Freescale i.MX boards:
-#
-CONFIG_SND_SOC_IMX_ES8328=m
-CONFIG_SND_SOC_IMX_SGTL5000=m
-CONFIG_SND_SOC_IMX_SPDIF=m
-CONFIG_SND_SOC_FSL_ASOC_CARD=m
-CONFIG_SND_SOC_IMX_AUDMIX=m
-CONFIG_SND_SOC_IMX_HDMI=m
-CONFIG_SND_SOC_IMX_RPMSG=m
-CONFIG_SND_SOC_IMX_CARD=m
-# end of SoC Audio for Freescale CPUs
-
-CONFIG_SND_I2S_HI6210_I2S=m
-CONFIG_SND_KIRKWOOD_SOC=m
-CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB=m
-# CONFIG_SND_SOC_IMG is not set
-CONFIG_SND_SOC_INTEL_KEEMBAY=m
-CONFIG_SND_SOC_INTEL_AVS=m
-CONFIG_SND_SOC_MEDIATEK=m
-# CONFIG_SND_SOC_MT2701 is not set
-CONFIG_SND_SOC_MT6797=m
-CONFIG_SND_SOC_MT6797_MT6351=m
-# CONFIG_SND_SOC_MT8173 is not set
-CONFIG_SND_SOC_MT8183=m
-CONFIG_SND_SOC_MT8186=m
-CONFIG_SND_SOC_MT8186_MT6366_DA7219_MAX98357=m
-CONFIG_SND_SOC_MT8186_MT6366_RT1019_RT5682S=m
-CONFIG_SND_SOC_MT8183_MT6358_TS3A227E_MAX98357A=m
-CONFIG_SND_SOC_MT8183_DA7219_MAX98357A=m
-CONFIG_SND_SOC_MTK_BTCVSD=m
-CONFIG_SND_SOC_MT8192=m
-CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682=m
-CONFIG_SND_SOC_MT8195=m
-CONFIG_SND_SOC_MT8195_MT6359=m
-CONFIG_SND_SOC_MT8195_MT6359_RT1019_RT5682=m
-# CONFIG_SND_SOC_MT8195_MT6359_RT1011_RT5682 is not set
-
-#
-# ASoC support for Amlogic platforms
-#
-CONFIG_SND_MESON_AIU=m
-CONFIG_SND_MESON_AXG_FIFO=m
-CONFIG_SND_MESON_AXG_FRDDR=m
-CONFIG_SND_MESON_AXG_TODDR=m
-CONFIG_SND_MESON_AXG_TDM_FORMATTER=m
-CONFIG_SND_MESON_AXG_TDM_INTERFACE=m
-CONFIG_SND_MESON_AXG_TDMIN=m
-CONFIG_SND_MESON_AXG_TDMOUT=m
-CONFIG_SND_MESON_AXG_SOUND_CARD=m
-CONFIG_SND_MESON_AXG_SPDIFOUT=m
-CONFIG_SND_MESON_AXG_SPDIFIN=m
-CONFIG_SND_MESON_AXG_PDM=m
-CONFIG_SND_MESON_CARD_UTILS=m
-CONFIG_SND_MESON_CODEC_GLUE=m
-CONFIG_SND_MESON_GX_SOUND_CARD=m
-CONFIG_SND_MESON_G12A_TOACODEC=m
-CONFIG_SND_MESON_G12A_TOHDMITX=m
-CONFIG_SND_SOC_MESON_T9015=m
-# end of ASoC support for Amlogic platforms
-
-CONFIG_SND_SOC_QCOM=m
-CONFIG_SND_SOC_LPASS_CPU=m
-CONFIG_SND_SOC_LPASS_HDMI=m
-CONFIG_SND_SOC_LPASS_PLATFORM=m
-CONFIG_SND_SOC_LPASS_IPQ806X=m
-CONFIG_SND_SOC_LPASS_APQ8016=m
-CONFIG_SND_SOC_LPASS_SC7180=m
-CONFIG_SND_SOC_STORM=m
-CONFIG_SND_SOC_APQ8016_SBC=m
-CONFIG_SND_SOC_QCOM_COMMON=m
-CONFIG_SND_SOC_QDSP6_COMMON=m
-CONFIG_SND_SOC_QDSP6_CORE=m
-CONFIG_SND_SOC_QDSP6_AFE=m
-CONFIG_SND_SOC_QDSP6_AFE_DAI=m
-CONFIG_SND_SOC_QDSP6_AFE_CLOCKS=m
-CONFIG_SND_SOC_QDSP6_ADM=m
-CONFIG_SND_SOC_QDSP6_ROUTING=m
-CONFIG_SND_SOC_QDSP6_ASM=m
-CONFIG_SND_SOC_QDSP6_ASM_DAI=m
-CONFIG_SND_SOC_QDSP6_APM_DAI=m
-CONFIG_SND_SOC_QDSP6_APM_LPASS_DAI=m
-CONFIG_SND_SOC_QDSP6_APM=m
-CONFIG_SND_SOC_QDSP6_PRM_LPASS_CLOCKS=m
-CONFIG_SND_SOC_QDSP6_PRM=m
-CONFIG_SND_SOC_QDSP6=m
-CONFIG_SND_SOC_MSM8996=m
-CONFIG_SND_SOC_SDM845=m
-CONFIG_SND_SOC_SM8250=m
-CONFIG_SND_SOC_SC8280XP=m
-CONFIG_SND_SOC_SC7180=m
-CONFIG_SND_SOC_SC7280=m
-CONFIG_SND_SOC_ROCKCHIP=m
-CONFIG_SND_SOC_ROCKCHIP_I2S=m
-CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
-CONFIG_SND_SOC_ROCKCHIP_PDM=m
-CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
-CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
-CONFIG_SND_SOC_ROCKCHIP_RT5645=m
-CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
-CONFIG_SND_SOC_RK3399_GRU_SOUND=m
-CONFIG_SND_SOC_SAMSUNG=m
-CONFIG_SND_SAMSUNG_PCM=m
-CONFIG_SND_SAMSUNG_SPDIF=m
-CONFIG_SND_SAMSUNG_I2S=m
-CONFIG_SND_SOC_SAMSUNG_SMDK_WM8994=m
-CONFIG_SND_SOC_SAMSUNG_SMDK_SPDIF=m
-CONFIG_SND_SOC_SMDK_WM8994_PCM=m
-CONFIG_SND_SOC_SNOW=m
-# CONFIG_SND_SOC_ODROID is not set
-# CONFIG_SND_SOC_ARNDALE is not set
-CONFIG_SND_SOC_SAMSUNG_ARIES_WM8994=m
-CONFIG_SND_SOC_SAMSUNG_MIDAS_WM1811=m
-
-#
-# SoC Audio support for Renesas SoCs
-#
-CONFIG_SND_SOC_SH4_FSI=m
-CONFIG_SND_SOC_RCAR=m
-CONFIG_SND_SOC_RZ=m
-# end of SoC Audio support for Renesas SoCs
-
-CONFIG_SND_SOC_SOF_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_PCI=m
-CONFIG_SND_SOC_SOF_ACPI=m
-CONFIG_SND_SOC_SOF_OF=m
-CONFIG_SND_SOC_SOF_COMPRESS=y
-# CONFIG_SND_SOC_SOF_DEBUG_PROBES is not set
-# CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT is not set
-CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m
-CONFIG_SND_SOC_SOF_AMD_RENOIR=m
-CONFIG_SND_SOC_SOF=m
-CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_IMX_OF=m
-CONFIG_SND_SOC_SOF_IMX_COMMON=m
-CONFIG_SND_SOC_SOF_IMX8_SUPPORT=y
-CONFIG_SND_SOC_SOF_IMX8=m
-CONFIG_SND_SOC_SOF_IMX8M_SUPPORT=y
-CONFIG_SND_SOC_SOF_IMX8M=m
-CONFIG_SND_SOC_SOF_IMX8ULP=m
-CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_MT8186=m
-CONFIG_SND_SOC_SOF_MT8195=m
-CONFIG_SND_SOC_SOF_XTENSA=m
-CONFIG_SND_SOC_SPRD=m
-CONFIG_SND_SOC_SPRD_MCDT=m
-
-#
-# STMicroelectronics STM32 SOC audio support
-#
-# end of STMicroelectronics STM32 SOC audio support
-
-#
-# Allwinner SoC Audio support
-#
-CONFIG_SND_SUN4I_CODEC=m
-CONFIG_SND_SUN8I_CODEC=m
-CONFIG_SND_SUN8I_CODEC_ANALOG=m
-CONFIG_SND_SUN50I_CODEC_ANALOG=m
-CONFIG_SND_SUN4I_I2S=m
-CONFIG_SND_SUN4I_SPDIF=m
-CONFIG_SND_SUN50I_DMIC=m
-CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m
-# end of Allwinner SoC Audio support
-
-CONFIG_SND_SOC_TEGRA=m
-# CONFIG_SND_SOC_TEGRA20_AC97 is not set
-# CONFIG_SND_SOC_TEGRA20_DAS is not set
-# CONFIG_SND_SOC_TEGRA20_I2S is not set
-# CONFIG_SND_SOC_TEGRA20_SPDIF is not set
-# CONFIG_SND_SOC_TEGRA30_AHUB is not set
-# CONFIG_SND_SOC_TEGRA30_I2S is not set
-CONFIG_SND_SOC_TEGRA210_AHUB=m
-CONFIG_SND_SOC_TEGRA210_DMIC=m
-CONFIG_SND_SOC_TEGRA210_I2S=m
-CONFIG_SND_SOC_TEGRA210_OPE=m
-CONFIG_SND_SOC_TEGRA186_ASRC=m
-CONFIG_SND_SOC_TEGRA186_DSPK=m
-CONFIG_SND_SOC_TEGRA210_ADMAIF=m
-# CONFIG_SND_SOC_TEGRA210_MVC is not set
-# CONFIG_SND_SOC_TEGRA210_SFC is not set
-# CONFIG_SND_SOC_TEGRA210_AMX is not set
-# CONFIG_SND_SOC_TEGRA210_ADX is not set
-# CONFIG_SND_SOC_TEGRA210_MIXER is not set
-CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m
-# CONFIG_SND_SOC_TEGRA_RT5640 is not set
-# CONFIG_SND_SOC_TEGRA_WM8753 is not set
-# CONFIG_SND_SOC_TEGRA_WM8903 is not set
-# CONFIG_SND_SOC_TEGRA_WM9712 is not set
-# CONFIG_SND_SOC_TEGRA_TRIMSLICE is not set
-# CONFIG_SND_SOC_TEGRA_ALC5632 is not set
-# CONFIG_SND_SOC_TEGRA_MAX98090 is not set
-# CONFIG_SND_SOC_TEGRA_RT5677 is not set
-# CONFIG_SND_SOC_TEGRA_SGTL5000 is not set
-
-#
-# Audio support for Texas Instruments SoCs
-#
-CONFIG_SND_SOC_TI_EDMA_PCM=m
-CONFIG_SND_SOC_TI_SDMA_PCM=m
-CONFIG_SND_SOC_TI_UDMA_PCM=m
-
-#
-# Texas Instruments DAI support for:
-#
-CONFIG_SND_SOC_DAVINCI_MCASP=m
-
-#
-# Audio support for boards with Texas Instruments SoCs
-#
-CONFIG_SND_SOC_J721E_EVM=m
-# end of Audio support for Texas Instruments SoCs
-
-CONFIG_SND_SOC_UNIPHIER=m
-CONFIG_SND_SOC_UNIPHIER_AIO=m
-CONFIG_SND_SOC_UNIPHIER_LD11=m
-CONFIG_SND_SOC_UNIPHIER_PXS2=m
-CONFIG_SND_SOC_UNIPHIER_EVEA_CODEC=m
-CONFIG_SND_SOC_XILINX_I2S=m
-CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
-CONFIG_SND_SOC_XILINX_SPDIF=m
-CONFIG_SND_SOC_XTFPGA_I2S=m
-CONFIG_SND_SOC_I2C_AND_SPI=m
-
-#
-# CODEC drivers
-#
-CONFIG_SND_SOC_WM_HUBS=m
-CONFIG_SND_SOC_AC97_CODEC=m
-CONFIG_SND_SOC_ADAU_UTILS=m
-# CONFIG_SND_SOC_ADAU1372_I2C is not set
-# CONFIG_SND_SOC_ADAU1372_SPI is not set
-CONFIG_SND_SOC_ADAU1701=m
-CONFIG_SND_SOC_ADAU17X1=m
-CONFIG_SND_SOC_ADAU1761=m
-CONFIG_SND_SOC_ADAU1761_I2C=m
-CONFIG_SND_SOC_ADAU1761_SPI=m
-CONFIG_SND_SOC_ADAU7002=m
-CONFIG_SND_SOC_ADAU7118=m
-CONFIG_SND_SOC_ADAU7118_HW=m
-CONFIG_SND_SOC_ADAU7118_I2C=m
-CONFIG_SND_SOC_AK4104=m
-CONFIG_SND_SOC_AK4118=m
-CONFIG_SND_SOC_AK4458=m
-CONFIG_SND_SOC_AK4554=m
-CONFIG_SND_SOC_AK4613=m
-CONFIG_SND_SOC_AK4642=m
-CONFIG_SND_SOC_AK5386=m
-CONFIG_SND_SOC_AK5558=m
-CONFIG_SND_SOC_ALC5623=m
-CONFIG_SND_SOC_AW8738=m
-CONFIG_SND_SOC_BD28623=m
-CONFIG_SND_SOC_BT_SCO=m
-CONFIG_SND_SOC_CPCAP=m
-CONFIG_SND_SOC_CROS_EC_CODEC=m
-CONFIG_SND_SOC_CS35L32=m
-CONFIG_SND_SOC_CS35L33=m
-CONFIG_SND_SOC_CS35L34=m
-CONFIG_SND_SOC_CS35L35=m
-CONFIG_SND_SOC_CS35L36=m
-# CONFIG_SND_SOC_CS35L41_SPI is not set
-# CONFIG_SND_SOC_CS35L41_I2C is not set
-CONFIG_SND_SOC_CS42L42=m
-CONFIG_SND_SOC_CS42L51=m
-CONFIG_SND_SOC_CS42L51_I2C=m
-CONFIG_SND_SOC_CS42L52=m
-CONFIG_SND_SOC_CS42L56=m
-CONFIG_SND_SOC_CS42L73=m
-CONFIG_SND_SOC_CS42L83=m
-# CONFIG_SND_SOC_CS4234 is not set
-CONFIG_SND_SOC_CS4265=m
-CONFIG_SND_SOC_CS4270=m
-CONFIG_SND_SOC_CS4271=m
-CONFIG_SND_SOC_CS4271_I2C=m
-CONFIG_SND_SOC_CS4271_SPI=m
-CONFIG_SND_SOC_CS42XX8=m
-CONFIG_SND_SOC_CS42XX8_I2C=m
-CONFIG_SND_SOC_CS43130=m
-CONFIG_SND_SOC_CS4341=m
-CONFIG_SND_SOC_CS4349=m
-CONFIG_SND_SOC_CS53L30=m
-CONFIG_SND_SOC_CX2072X=m
-CONFIG_SND_SOC_DA7213=m
-CONFIG_SND_SOC_DA7219=m
-CONFIG_SND_SOC_DMIC=m
-CONFIG_SND_SOC_HDMI_CODEC=m
-CONFIG_SND_SOC_ES7134=m
-CONFIG_SND_SOC_ES7241=m
-CONFIG_SND_SOC_ES8316=m
-CONFIG_SND_SOC_ES8326=m
-CONFIG_SND_SOC_ES8328=m
-CONFIG_SND_SOC_ES8328_I2C=m
-CONFIG_SND_SOC_ES8328_SPI=m
-CONFIG_SND_SOC_GTM601=m
-CONFIG_SND_SOC_HDA=m
-# CONFIG_SND_SOC_ICS43432 is not set
-# CONFIG_SND_SOC_INNO_RK3036 is not set
-CONFIG_SND_SOC_LOCHNAGAR_SC=m
-CONFIG_SND_SOC_MAX98088=m
-CONFIG_SND_SOC_MAX98090=m
-CONFIG_SND_SOC_MAX98095=m
-CONFIG_SND_SOC_MAX98357A=m
-CONFIG_SND_SOC_MAX98504=m
-CONFIG_SND_SOC_MAX9867=m
-CONFIG_SND_SOC_MAX98927=m
-# CONFIG_SND_SOC_MAX98520 is not set
-CONFIG_SND_SOC_MAX98373=m
-CONFIG_SND_SOC_MAX98373_I2C=m
-CONFIG_SND_SOC_MAX98373_SDW=m
-CONFIG_SND_SOC_MAX98390=m
-CONFIG_SND_SOC_MAX9860=m
-# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set
-# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set
-CONFIG_SND_SOC_PCM1681=m
-CONFIG_SND_SOC_PCM1789=m
-CONFIG_SND_SOC_PCM1789_I2C=m
-CONFIG_SND_SOC_PCM179X=m
-CONFIG_SND_SOC_PCM179X_I2C=m
-CONFIG_SND_SOC_PCM179X_SPI=m
-CONFIG_SND_SOC_PCM186X=m
-CONFIG_SND_SOC_PCM186X_I2C=m
-CONFIG_SND_SOC_PCM186X_SPI=m
-CONFIG_SND_SOC_PCM3060=m
-CONFIG_SND_SOC_PCM3060_I2C=m
-CONFIG_SND_SOC_PCM3060_SPI=m
-CONFIG_SND_SOC_PCM3168A=m
-CONFIG_SND_SOC_PCM3168A_I2C=m
-# CONFIG_SND_SOC_PCM3168A_SPI is not set
-# CONFIG_SND_SOC_PCM5102A is not set
-CONFIG_SND_SOC_PCM512x=m
-CONFIG_SND_SOC_PCM512x_I2C=m
-CONFIG_SND_SOC_PCM512x_SPI=m
-CONFIG_SND_SOC_RK3328=m
-CONFIG_SND_SOC_RK817=m
-CONFIG_SND_SOC_RL6231=m
-CONFIG_SND_SOC_RT1015=m
-CONFIG_SND_SOC_RT1015P=m
-CONFIG_SND_SOC_RT1308_SDW=m
-CONFIG_SND_SOC_RT1316_SDW=m
-CONFIG_SND_SOC_RT5514=m
-CONFIG_SND_SOC_RT5514_SPI=m
-CONFIG_SND_SOC_RT5616=m
-CONFIG_SND_SOC_RT5631=m
-CONFIG_SND_SOC_RT5640=m
-CONFIG_SND_SOC_RT5645=m
-CONFIG_SND_SOC_RT5659=m
-CONFIG_SND_SOC_RT5663=m
-CONFIG_SND_SOC_RT5682=m
-CONFIG_SND_SOC_RT5682_I2C=m
-CONFIG_SND_SOC_RT5682_SDW=m
-CONFIG_SND_SOC_RT700=m
-CONFIG_SND_SOC_RT700_SDW=m
-CONFIG_SND_SOC_RT711=m
-CONFIG_SND_SOC_RT711_SDW=m
-CONFIG_SND_SOC_RT711_SDCA_SDW=m
-CONFIG_SND_SOC_RT715=m
-CONFIG_SND_SOC_RT715_SDW=m
-CONFIG_SND_SOC_RT715_SDCA_SDW=m
-# CONFIG_SND_SOC_RT9120 is not set
-CONFIG_SND_SOC_SDW_MOCKUP=m
-CONFIG_SND_SOC_SGTL5000=m
-CONFIG_SND_SOC_SIGMADSP=m
-CONFIG_SND_SOC_SIGMADSP_I2C=m
-CONFIG_SND_SOC_SIGMADSP_REGMAP=m
-CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
-# CONFIG_SND_SOC_SIMPLE_MUX is not set
-CONFIG_SND_SOC_SPDIF=m
-CONFIG_SND_SOC_SRC4XXX_I2C=m
-CONFIG_SND_SOC_SSM2305=m
-CONFIG_SND_SOC_SSM2518=m
-CONFIG_SND_SOC_SSM2602=m
-CONFIG_SND_SOC_SSM2602_SPI=m
-CONFIG_SND_SOC_SSM2602_I2C=m
-CONFIG_SND_SOC_SSM4567=m
-CONFIG_SND_SOC_STA32X=m
-CONFIG_SND_SOC_STA350=m
-CONFIG_SND_SOC_STI_SAS=m
-CONFIG_SND_SOC_TAS2552=m
-CONFIG_SND_SOC_TAS2562=m
-# CONFIG_SND_SOC_TAS2764 is not set
-CONFIG_SND_SOC_TAS2770=m
-CONFIG_SND_SOC_TAS2780=m
-CONFIG_SND_SOC_WSA883X=m
-CONFIG_SND_SOC_TAS5086=m
-CONFIG_SND_SOC_TAS571X=m
-CONFIG_SND_SOC_TAS5720=m
-CONFIG_SND_SOC_TAS5805M=m
-CONFIG_SND_SOC_TAS6424=m
-CONFIG_SND_SOC_TDA7419=m
-CONFIG_SND_SOC_TFA9879=m
-CONFIG_SND_SOC_TFA989X=m
-CONFIG_SND_SOC_TLV320AIC23=m
-CONFIG_SND_SOC_TLV320AIC23_I2C=m
-CONFIG_SND_SOC_TLV320AIC23_SPI=m
-CONFIG_SND_SOC_TLV320AIC31XX=m
-CONFIG_SND_SOC_TLV320AIC32X4=m
-CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
-CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
-CONFIG_SND_SOC_TLV320AIC3X=m
-CONFIG_SND_SOC_TLV320AIC3X_I2C=m
-CONFIG_SND_SOC_TLV320AIC3X_SPI=m
-CONFIG_SND_SOC_TLV320ADCX140=m
-CONFIG_SND_SOC_TS3A227E=m
-CONFIG_SND_SOC_TSCS42XX=m
-CONFIG_SND_SOC_TSCS454=m
-CONFIG_SND_SOC_UDA1334=m
-CONFIG_SND_SOC_WCD9335=m
-CONFIG_SND_SOC_WCD_MBHC=m
-CONFIG_SND_SOC_WCD934X=m
-CONFIG_SND_SOC_WCD938X=m
-CONFIG_SND_SOC_WCD938X_SDW=m
-CONFIG_SND_SOC_WM8510=m
-CONFIG_SND_SOC_WM8523=m
-CONFIG_SND_SOC_WM8524=m
-CONFIG_SND_SOC_WM8580=m
-CONFIG_SND_SOC_WM8711=m
-CONFIG_SND_SOC_WM8728=m
-CONFIG_SND_SOC_WM8731=m
-CONFIG_SND_SOC_WM8737=m
-CONFIG_SND_SOC_WM8741=m
-CONFIG_SND_SOC_WM8750=m
-CONFIG_SND_SOC_WM8753=m
-CONFIG_SND_SOC_WM8770=m
-CONFIG_SND_SOC_WM8776=m
-CONFIG_SND_SOC_WM8782=m
-CONFIG_SND_SOC_WM8804=m
-CONFIG_SND_SOC_WM8804_I2C=m
-CONFIG_SND_SOC_WM8804_SPI=m
-CONFIG_SND_SOC_WM8903=m
-CONFIG_SND_SOC_WM8904=m
-CONFIG_SND_SOC_WM8960=m
-CONFIG_SND_SOC_WM8962=m
-CONFIG_SND_SOC_WM8974=m
-CONFIG_SND_SOC_WM8978=m
-CONFIG_SND_SOC_WM8985=m
-CONFIG_SND_SOC_WM8994=m
-CONFIG_SND_SOC_WSA881X=m
-CONFIG_SND_SOC_ZL38060=m
-CONFIG_SND_SOC_MAX9759=m
-CONFIG_SND_SOC_MT6351=m
-CONFIG_SND_SOC_MT6358=m
-CONFIG_SND_SOC_MT6359=m
-CONFIG_SND_SOC_MT6359_ACCDET=m
-CONFIG_SND_SOC_MT6660=m
-# CONFIG_SND_SOC_NAU8315 is not set
-CONFIG_SND_SOC_NAU8540=m
-CONFIG_SND_SOC_NAU8810=m
-# CONFIG_SND_SOC_NAU8821 is not set
-CONFIG_SND_SOC_NAU8822=m
-CONFIG_SND_SOC_NAU8824=m
-CONFIG_SND_SOC_TPA6130A2=m
-# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set
-# CONFIG_SND_SOC_LPASS_VA_MACRO is not set
-# CONFIG_SND_SOC_LPASS_RX_MACRO is not set
-# CONFIG_SND_SOC_LPASS_TX_MACRO is not set
-# end of CODEC drivers
-
-CONFIG_SND_SIMPLE_CARD_UTILS=m
-CONFIG_SND_SIMPLE_CARD=m
-CONFIG_SND_AUDIO_GRAPH_CARD=m
-# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
-# CONFIG_SND_TEST_COMPONENT is not set
-CONFIG_SND_VIRTIO=m
-CONFIG_AC97_BUS=m
-
-#
-# HID support
-#
-CONFIG_HID=y
-CONFIG_HID_BATTERY_STRENGTH=y
-CONFIG_HIDRAW=y
-CONFIG_UHID=m
-CONFIG_HID_GENERIC=m
-
-#
-# Special HID drivers
-#
-CONFIG_HID_A4TECH=m
-CONFIG_HID_ACCUTOUCH=m
-CONFIG_HID_ACRUX=m
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=m
-CONFIG_HID_APPLEIR=m
-CONFIG_HID_ASUS=m
-CONFIG_HID_AUREAL=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_BETOP_FF=m
-CONFIG_HID_BIGBEN_FF=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CORSAIR=m
-CONFIG_HID_COUGAR=m
-CONFIG_HID_MACALLY=m
-CONFIG_HID_PRODIKEYS=m
-# CONFIG_HID_CMEDIA is not set
-CONFIG_HID_CP2112=m
-CONFIG_HID_CREATIVE_SB0540=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_DRAGONRISE=m
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=m
-CONFIG_HID_ELAN=m
-CONFIG_HID_ELECOM=m
-CONFIG_HID_ELO=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_FT260=m
-CONFIG_HID_GEMBIRD=m
-CONFIG_HID_GFRM=m
-CONFIG_HID_GLORIOUS=m
-CONFIG_HID_HOLTEK=m
-CONFIG_HOLTEK_FF=y
-CONFIG_HID_GOOGLE_HAMMER=m
-CONFIG_HID_VIVALDI=m
-CONFIG_HID_GT683R=m
-CONFIG_HID_KEYTOUCH=m
-CONFIG_HID_KYE=m
-CONFIG_HID_UCLOGIC=m
-CONFIG_HID_WALTOP=m
-CONFIG_HID_VIEWSONIC=m
-CONFIG_HID_VRC2=m
-# CONFIG_HID_XIAOMI is not set
-CONFIG_HID_GYRATION=m
-CONFIG_HID_ICADE=m
-CONFIG_HID_ITE=m
-CONFIG_HID_JABRA=m
-CONFIG_HID_TWINHAN=m
-CONFIG_HID_KENSINGTON=m
-CONFIG_HID_LCPOWER=m
-CONFIG_HID_LED=m
-CONFIG_HID_LENOVO=m
-CONFIG_HID_LOGITECH=m
-CONFIG_HID_LOGITECH_DJ=m
-CONFIG_HID_LOGITECH_HIDPP=m
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWHEELS_FF=y
-CONFIG_HID_MAGICMOUSE=m
-CONFIG_HID_MALTRON=m
-CONFIG_HID_MAYFLASH=m
-CONFIG_HID_REDRAGON=m
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_MULTITOUCH=m
-# CONFIG_HID_NINTENDO is not set
-CONFIG_HID_NTI=m
-CONFIG_HID_NTRIG=m
-CONFIG_HID_ORTEK=m
-CONFIG_HID_PANTHERLORD=m
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PENMOUNT=m
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_PICOLCD=m
-CONFIG_HID_PICOLCD_FB=y
-CONFIG_HID_PICOLCD_BACKLIGHT=y
-CONFIG_HID_PICOLCD_LCD=y
-CONFIG_HID_PICOLCD_LEDS=y
-CONFIG_HID_PICOLCD_CIR=y
-CONFIG_HID_PLANTRONICS=m
-CONFIG_HID_PLAYSTATION=m
-CONFIG_HID_PXRC=m
-CONFIG_HID_RAZER=m
-# CONFIG_PLAYSTATION_FF is not set
-CONFIG_HID_PRIMAX=m
-CONFIG_HID_RETRODE=m
-CONFIG_HID_ROCCAT=m
-CONFIG_HID_SAITEK=m
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SEMITEK=m
-CONFIG_HID_SIGMAMICRO=m
-CONFIG_HID_SONY=m
-CONFIG_SONY_FF=y
-CONFIG_HID_SPEEDLINK=m
-CONFIG_HID_STEAM=m
-CONFIG_HID_STEELSERIES=m
-CONFIG_HID_SUNPLUS=m
-CONFIG_HID_RMI=m
-CONFIG_HID_GREENASIA=m
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_HYPERV_MOUSE=m
-CONFIG_HID_SMARTJOYPLUS=m
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TIVO=m
-CONFIG_HID_TOPSEED=m
-CONFIG_HID_TOPRE=m
-CONFIG_HID_THINGM=m
-CONFIG_HID_THRUSTMASTER=m
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_UDRAW_PS3=m
-CONFIG_HID_U2FZERO=m
-CONFIG_HID_WACOM=m
-CONFIG_HID_WIIMOTE=m
-CONFIG_HID_XINMO=m
-CONFIG_HID_ZEROPLUS=m
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=m
-CONFIG_HID_SENSOR_HUB=m
-CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
-CONFIG_HID_ALPS=m
-CONFIG_HID_MCP2221=m
-# end of Special HID drivers
-
-#
-# USB HID support
-#
-CONFIG_USB_HID=m
-CONFIG_HID_PID=y
-CONFIG_USB_HIDDEV=y
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# end of USB HID Boot Protocol drivers
-# end of USB HID support
-
-#
-# I2C HID support
-#
-CONFIG_I2C_HID_ACPI=m
-CONFIG_I2C_HID_OF=m
-CONFIG_I2C_HID_OF_ELAN=m
-CONFIG_I2C_HID_OF_GOODIX=m
-# end of I2C HID support
-
-CONFIG_I2C_HID_CORE=m
-
-#
-# Surface System Aggregator Module HID support
-#
-CONFIG_SURFACE_HID=m
-CONFIG_SURFACE_KBD=m
-# end of Surface System Aggregator Module HID support
-
-CONFIG_SURFACE_HID_CORE=m
-# end of HID support
-
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_LED_TRIG=y
-CONFIG_USB_ULPI_BUS=m
-CONFIG_USB_CONN_GPIO=m
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB=m
-CONFIG_USB_PCI=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEFAULT_PERSIST=y
-CONFIG_USB_FEW_INIT_RETRIES=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-CONFIG_USB_OTG=y
-# CONFIG_USB_OTG_PRODUCTLIST is not set
-# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
-CONFIG_USB_OTG_FSM=m
-CONFIG_USB_LEDS_TRIGGER_USBPORT=m
-CONFIG_USB_AUTOSUSPEND_DELAY=2
-CONFIG_USB_MON=m
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_C67X00_HCD=m
-CONFIG_USB_XHCI_HCD=m
-# CONFIG_USB_XHCI_DBGCAP is not set
-CONFIG_USB_XHCI_PCI=m
-CONFIG_USB_XHCI_PCI_RENESAS=m
-CONFIG_USB_XHCI_PLATFORM=m
-CONFIG_USB_XHCI_HISTB=m
-CONFIG_USB_XHCI_MTK=m
-CONFIG_USB_XHCI_MVEBU=m
-CONFIG_USB_XHCI_RCAR=m
-CONFIG_USB_XHCI_TEGRA=m
-# CONFIG_USB_BRCMSTB is not set
-CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-CONFIG_USB_EHCI_PCI=m
-CONFIG_USB_EHCI_FSL=m
-CONFIG_USB_EHCI_HCD_NPCM7XX=m
-CONFIG_USB_EHCI_HCD_ORION=m
-CONFIG_USB_EHCI_TEGRA=m
-CONFIG_USB_EHCI_EXYNOS=m
-CONFIG_USB_EHCI_HCD_PLATFORM=m
-CONFIG_USB_OXU210HP_HCD=m
-CONFIG_USB_ISP116X_HCD=m
-CONFIG_USB_FOTG210_HCD=m
-CONFIG_USB_MAX3421_HCD=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_OHCI_HCD_PCI=m
-CONFIG_USB_OHCI_HCD_SSB=y
-CONFIG_USB_OHCI_EXYNOS=m
-CONFIG_USB_OHCI_HCD_PLATFORM=m
-CONFIG_USB_UHCI_HCD=m
-CONFIG_USB_U132_HCD=m
-CONFIG_USB_SL811_HCD=m
-# CONFIG_USB_SL811_HCD_ISO is not set
-CONFIG_USB_R8A66597_HCD=m
-CONFIG_USB_RENESAS_USBHS_HCD=m
-CONFIG_USB_HCD_BCMA=m
-CONFIG_USB_HCD_SSB=m
-# CONFIG_USB_HCD_TEST_MODE is not set
-CONFIG_USB_RENESAS_USBHS=m
-
-#
-# USB Device Class drivers
-#
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_WDM=m
-CONFIG_USB_TMC=m
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-CONFIG_USB_STORAGE_REALTEK=m
-CONFIG_REALTEK_AUTOPM=y
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_ISD200=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_STORAGE_ALAUDA=m
-CONFIG_USB_STORAGE_ONETOUCH=m
-CONFIG_USB_STORAGE_KARMA=m
-CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-CONFIG_USB_STORAGE_ENE_UB6250=m
-CONFIG_USB_UAS=m
-
-#
-# USB Imaging devices
-#
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USBIP_CORE=m
-CONFIG_USBIP_VHCI_HCD=m
-CONFIG_USBIP_VHCI_HC_PORTS=8
-CONFIG_USBIP_VHCI_NR_HCS=1
-CONFIG_USBIP_HOST=m
-CONFIG_USBIP_VUDC=m
-# CONFIG_USBIP_DEBUG is not set
-CONFIG_USB_CDNS_SUPPORT=m
-CONFIG_USB_CDNS_HOST=y
-CONFIG_USB_CDNS3=m
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_USB_CDNS3_HOST=y
-CONFIG_USB_CDNS3_PCI_WRAP=m
-CONFIG_USB_CDNS3_TI=m
-CONFIG_USB_CDNS3_IMX=m
-CONFIG_USB_CDNSP_PCI=m
-CONFIG_USB_CDNSP_GADGET=y
-CONFIG_USB_CDNSP_HOST=y
-CONFIG_USB_MTU3=m
-CONFIG_USB_MTU3_HOST=y
-# CONFIG_USB_MTU3_GADGET is not set
-# CONFIG_USB_MTU3_DUAL_ROLE is not set
-# CONFIG_USB_MTU3_DEBUG is not set
-CONFIG_USB_MUSB_HDRC=m
-CONFIG_USB_MUSB_HOST=y
-# CONFIG_USB_MUSB_GADGET is not set
-# CONFIG_USB_MUSB_DUAL_ROLE is not set
-
-#
-# Platform Glue Layer
-#
-CONFIG_USB_MUSB_SUNXI=m
-CONFIG_USB_MUSB_MEDIATEK=m
-
-#
-# MUSB DMA mode
-#
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_DWC3=m
-CONFIG_USB_DWC3_ULPI=y
-# CONFIG_USB_DWC3_HOST is not set
-# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_DUAL_ROLE=y
-
-#
-# Platform Glue Driver Support
-#
-CONFIG_USB_DWC3_EXYNOS=m
-CONFIG_USB_DWC3_PCI=m
-CONFIG_USB_DWC3_HAPS=m
-CONFIG_USB_DWC3_KEYSTONE=m
-CONFIG_USB_DWC3_MESON_G12A=m
-CONFIG_USB_DWC3_OF_SIMPLE=m
-CONFIG_USB_DWC3_QCOM=m
-CONFIG_USB_DWC3_IMX8MP=m
-CONFIG_USB_DWC3_XILINX=m
-CONFIG_USB_DWC3_AM62=m
-CONFIG_USB_DWC2=m
-# CONFIG_USB_DWC2_HOST is not set
-
-#
-# Gadget/Dual-role mode requires USB Gadget support to be enabled
-#
-# CONFIG_USB_DWC2_PERIPHERAL is not set
-CONFIG_USB_DWC2_DUAL_ROLE=y
-CONFIG_USB_DWC2_PCI=m
-# CONFIG_USB_DWC2_DEBUG is not set
-# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
-CONFIG_USB_CHIPIDEA=m
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_PCI=m
-CONFIG_USB_CHIPIDEA_MSM=m
-CONFIG_USB_CHIPIDEA_IMX=m
-CONFIG_USB_CHIPIDEA_GENERIC=m
-CONFIG_USB_CHIPIDEA_TEGRA=m
-CONFIG_USB_ISP1760=m
-CONFIG_USB_ISP1760_HCD=y
-CONFIG_USB_ISP1761_UDC=y
-# CONFIG_USB_ISP1760_HOST_ROLE is not set
-# CONFIG_USB_ISP1760_GADGET_ROLE is not set
-CONFIG_USB_ISP1760_DUAL_ROLE=y
-
-#
-# USB port drivers
-#
-CONFIG_USB_USS720=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_SIMPLE=m
-CONFIG_USB_SERIAL_AIRCABLE=m
-CONFIG_USB_SERIAL_ARK3116=m
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_CH341=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CP210X=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_F81232=m
-CONFIG_USB_SERIAL_F8153X=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_IUU=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_METRO=m
-CONFIG_USB_SERIAL_MOS7720=m
-CONFIG_USB_SERIAL_MOS7715_PARPORT=y
-CONFIG_USB_SERIAL_MOS7840=m
-CONFIG_USB_SERIAL_MXUPORT=m
-CONFIG_USB_SERIAL_NAVMAN=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_OTI6858=m
-CONFIG_USB_SERIAL_QCAUX=m
-CONFIG_USB_SERIAL_QUALCOMM=m
-CONFIG_USB_SERIAL_SPCP8X5=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_SAFE_PADDED=y
-CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-CONFIG_USB_SERIAL_SYMBOL=m
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_WWAN=m
-CONFIG_USB_SERIAL_OPTION=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_SERIAL_OPTICON=m
-CONFIG_USB_SERIAL_XSENS_MT=m
-CONFIG_USB_SERIAL_WISHBONE=m
-CONFIG_USB_SERIAL_SSU100=m
-CONFIG_USB_SERIAL_QT2=m
-CONFIG_USB_SERIAL_UPD78F0730=m
-CONFIG_USB_SERIAL_XR=m
-CONFIG_USB_SERIAL_DEBUG=m
-
-#
-# USB Miscellaneous drivers
-#
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_ADUTUX=m
-CONFIG_USB_SEVSEG=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_CYPRESS_CY7C63=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_IDMOUSE=m
-CONFIG_USB_FTDI_ELAN=m
-CONFIG_USB_APPLEDISPLAY=m
-CONFIG_USB_QCOM_EUD=m
-CONFIG_APPLE_MFI_FASTCHARGE=m
-CONFIG_USB_SISUSBVGA=m
-CONFIG_USB_LD=m
-CONFIG_USB_TRANCEVIBRATOR=m
-CONFIG_USB_IOWARRIOR=m
-# CONFIG_USB_TEST is not set
-CONFIG_USB_EHSET_TEST_FIXTURE=m
-CONFIG_USB_ISIGHTFW=m
-CONFIG_USB_YUREX=m
-CONFIG_USB_EZUSB_FX2=m
-CONFIG_USB_HUB_USB251XB=m
-CONFIG_USB_HSIC_USB3503=m
-CONFIG_USB_HSIC_USB4604=m
-CONFIG_USB_LINK_LAYER_TEST=m
-CONFIG_USB_CHAOSKEY=m
-CONFIG_BRCM_USB_PINMAP=m
-CONFIG_USB_ONBOARD_HUB=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_CXACRU=m
-CONFIG_USB_UEAGLEATM=m
-CONFIG_USB_XUSBATM=m
-
-#
-# USB Physical Layer drivers
-#
-CONFIG_USB_PHY=y
-CONFIG_NOP_USB_XCEIV=m
-# CONFIG_USB_GPIO_VBUS is not set
-CONFIG_USB_ISP1301=m
-CONFIG_USB_MXS_PHY=m
-CONFIG_USB_TEGRA_PHY=m
-CONFIG_USB_ULPI=y
-CONFIG_USB_ULPI_VIEWPORT=y
-# end of USB Physical Layer drivers
-
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
-CONFIG_U_SERIAL_CONSOLE=y
-
-#
-# USB Peripheral Controller
-#
-# CONFIG_USB_FOTG210_UDC is not set
-# CONFIG_USB_GR_UDC is not set
-# CONFIG_USB_R8A66597 is not set
-CONFIG_USB_RENESAS_USBHS_UDC=m
-CONFIG_USB_RENESAS_USB3=m
-# CONFIG_USB_PXA27X is not set
-# CONFIG_USB_MV_UDC is not set
-# CONFIG_USB_MV_U3D is not set
-CONFIG_USB_SNP_CORE=m
-CONFIG_USB_SNP_UDC_PLAT=m
-# CONFIG_USB_M66592 is not set
-CONFIG_USB_BDC_UDC=m
-# CONFIG_USB_AMD5536UDC is not set
-# CONFIG_USB_NET2272 is not set
-# CONFIG_USB_NET2280 is not set
-# CONFIG_USB_GOKU is not set
-# CONFIG_USB_EG20T is not set
-CONFIG_USB_GADGET_XILINX=m
-CONFIG_USB_MAX3420_UDC=m
-CONFIG_USB_TEGRA_XUDC=m
-# CONFIG_USB_DUMMY_HCD is not set
-# end of USB Peripheral Controller
-
-CONFIG_USB_LIBCOMPOSITE=m
-CONFIG_USB_F_ACM=m
-CONFIG_USB_F_SS_LB=m
-CONFIG_USB_U_SERIAL=m
-CONFIG_USB_U_ETHER=m
-CONFIG_USB_U_AUDIO=m
-CONFIG_USB_F_SERIAL=m
-CONFIG_USB_F_OBEX=m
-CONFIG_USB_F_NCM=m
-CONFIG_USB_F_ECM=m
-CONFIG_USB_F_PHONET=m
-CONFIG_USB_F_EEM=m
-CONFIG_USB_F_SUBSET=m
-CONFIG_USB_F_RNDIS=m
-CONFIG_USB_F_MASS_STORAGE=m
-CONFIG_USB_F_FS=m
-CONFIG_USB_F_UAC1=m
-CONFIG_USB_F_UAC2=m
-CONFIG_USB_F_UVC=m
-CONFIG_USB_F_MIDI=m
-CONFIG_USB_F_HID=m
-CONFIG_USB_F_PRINTER=m
-CONFIG_USB_F_TCM=m
-CONFIG_USB_CONFIGFS=m
-CONFIG_USB_CONFIGFS_SERIAL=y
-CONFIG_USB_CONFIGFS_ACM=y
-CONFIG_USB_CONFIGFS_OBEX=y
-CONFIG_USB_CONFIGFS_NCM=y
-CONFIG_USB_CONFIGFS_ECM=y
-CONFIG_USB_CONFIGFS_ECM_SUBSET=y
-CONFIG_USB_CONFIGFS_RNDIS=y
-CONFIG_USB_CONFIGFS_EEM=y
-CONFIG_USB_CONFIGFS_PHONET=y
-CONFIG_USB_CONFIGFS_MASS_STORAGE=y
-CONFIG_USB_CONFIGFS_F_LB_SS=y
-CONFIG_USB_CONFIGFS_F_FS=y
-CONFIG_USB_CONFIGFS_F_UAC1=y
-# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
-CONFIG_USB_CONFIGFS_F_UAC2=y
-CONFIG_USB_CONFIGFS_F_MIDI=y
-CONFIG_USB_CONFIGFS_F_HID=y
-CONFIG_USB_CONFIGFS_F_UVC=y
-CONFIG_USB_CONFIGFS_F_PRINTER=y
-CONFIG_USB_CONFIGFS_F_TCM=y
-
-#
-# USB Gadget precomposed configurations
-#
-# CONFIG_USB_ZERO is not set
-CONFIG_USB_AUDIO=m
-# CONFIG_GADGET_UAC1 is not set
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-CONFIG_USB_ETH_EEM=y
-CONFIG_USB_G_NCM=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FUNCTIONFS=m
-CONFIG_USB_FUNCTIONFS_ETH=y
-CONFIG_USB_FUNCTIONFS_RNDIS=y
-CONFIG_USB_FUNCTIONFS_GENERIC=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_GADGET_TARGET=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_MIDI_GADGET=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_NOKIA=m
-CONFIG_USB_G_ACM_MS=m
-CONFIG_USB_G_MULTI=m
-CONFIG_USB_G_MULTI_RNDIS=y
-CONFIG_USB_G_MULTI_CDC=y
-CONFIG_USB_G_HID=m
-CONFIG_USB_G_DBGP=m
-# CONFIG_USB_G_DBGP_PRINTK is not set
-CONFIG_USB_G_DBGP_SERIAL=y
-CONFIG_USB_G_WEBCAM=m
-CONFIG_USB_RAW_GADGET=m
-# end of USB Gadget precomposed configurations
-
-CONFIG_TYPEC=y
-CONFIG_TYPEC_TCPM=m
-CONFIG_TYPEC_TCPCI=m
-CONFIG_TYPEC_RT1711H=m
-CONFIG_TYPEC_TCPCI_MT6370=m
-CONFIG_TYPEC_MT6360=m
-CONFIG_TYPEC_TCPCI_MT6370=m
-CONFIG_TYPEC_TCPCI_MAXIM=m
-CONFIG_TYPEC_FUSB302=m
-CONFIG_TYPEC_UCSI=m
-CONFIG_UCSI_CCG=m
-CONFIG_UCSI_ACPI=m
-CONFIG_UCSI_STM32G0=m
-CONFIG_TYPEC_TPS6598X=m
-CONFIG_TYPEC_ANX7411=m
-CONFIG_TYPEC_RT1719=m
-CONFIG_TYPEC_HD3SS3220=m
-CONFIG_TYPEC_STUSB160X=m
-CONFIG_TYPEC_WUSB3801=m
-CONFIG_TYPEC_QCOM_PMIC=m
-CONFIG_TYPEC_WUSB3801=m
-CONFIG_TYPEC_EXTCON=m
-
-#
-# USB Type-C Multiplexer/DeMultiplexer Switch support
-#
-CONFIG_TYPEC_MUX_PI3USB30532=m
-# end of USB Type-C Multiplexer/DeMultiplexer Switch support
-
-#
-# USB Type-C Alternate Mode drivers
-#
-CONFIG_TYPEC_DP_ALTMODE=m
-CONFIG_TYPEC_NVIDIA_ALTMODE=m
-# end of USB Type-C Alternate Mode drivers
-
-CONFIG_USB_ROLE_SWITCH=m
-CONFIG_MMC=m
-CONFIG_PWRSEQ_EMMC=m
-CONFIG_PWRSEQ_SD8787=m
-CONFIG_PWRSEQ_SIMPLE=m
-CONFIG_MMC_BLOCK=m
-CONFIG_MMC_BLOCK_MINORS=8
-CONFIG_SDIO_UART=m
-# CONFIG_MMC_TEST is not set
-CONFIG_MMC_CRYPTO=y
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_ARMMMCI=m
-CONFIG_MMC_QCOM_DML=y
-CONFIG_MMC_STM32_SDMMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PCI=m
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI_ACPI=m
-CONFIG_MMC_SDHCI_PLTFM=m
-CONFIG_MMC_SDHCI_OF_ARASAN=m
-# CONFIG_MMC_SDHCI_OF_ASPEED is not set
-# CONFIG_MMC_SDHCI_OF_AT91 is not set
-CONFIG_MMC_SDHCI_OF_ESDHC=m
-CONFIG_MMC_SDHCI_OF_DWCMSHC=y
-CONFIG_MMC_SDHCI_OF_SPARX5=m
-CONFIG_MMC_SDHCI_CADENCE=m
-CONFIG_MMC_SDHCI_ESDHC_IMX=m
-CONFIG_MMC_SDHCI_TEGRA=m
-CONFIG_MMC_SDHCI_S3C=m
-CONFIG_MMC_SDHCI_PXAV3=m
-# CONFIG_MMC_SDHCI_S3C_DMA is not set
-CONFIG_MMC_SDHCI_F_SDH30=m
-# CONFIG_MMC_SDHCI_MILBEAUT is not set
-CONFIG_MMC_SDHCI_IPROC=m
-CONFIG_MMC_MESON_GX=m
-# CONFIG_MMC_MESON_MX_SDIO is not set
-CONFIG_MMC_ALCOR=m
-CONFIG_MMC_SDHCI_MSM=m
-# CONFIG_MMC_MXC is not set
-CONFIG_MMC_TIFM_SD=m
-# CONFIG_MMC_SPI is not set
-CONFIG_MMC_SDHCI_SPRD=m
-CONFIG_MMC_TMIO_CORE=m
-CONFIG_MMC_SDHI=m
-CONFIG_MMC_SDHI_SYS_DMAC=m
-CONFIG_MMC_SDHI_INTERNAL_DMAC=m
-CONFIG_MMC_UNIPHIER=m
-CONFIG_MMC_CB710=m
-CONFIG_MMC_VIA_SDMMC=m
-CONFIG_MMC_CAVIUM_THUNDERX=m
-CONFIG_MMC_DW=y
-CONFIG_MMC_DW_PLTFM=m
-CONFIG_MMC_DW_BLUEFIELD=m
-CONFIG_MMC_DW_EXYNOS=m
-CONFIG_MMC_DW_HI3798CV200=m
-CONFIG_MMC_DW_K3=m
-CONFIG_MMC_DW_PCI=m
-CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_MMC_SH_MMCIF=m
-CONFIG_MMC_VUB300=m
-CONFIG_MMC_USHC=m
-CONFIG_MMC_USDHI6ROL0=m
-CONFIG_MMC_REALTEK_PCI=m
-CONFIG_MMC_REALTEK_USB=m
-CONFIG_MMC_SUNXI=m
-CONFIG_MMC_CQHCI=m
-CONFIG_MMC_HSQ=m
-# CONFIG_MMC_TOSHIBA_PCI is not set
-CONFIG_MMC_BCM2835=m
-CONFIG_MMC_MTK=m
-CONFIG_MMC_SDHCI_BRCMSTB=m
-CONFIG_MMC_SDHCI_XENON=m
-# CONFIG_MMC_SDHCI_OMAP is not set
-CONFIG_MMC_SDHCI_AM654=m
-CONFIG_MMC_OWL=m
-CONFIG_MMC_LITEX=m
-CONFIG_MEMSTICK=m
-# CONFIG_MEMSTICK_DEBUG is not set
-
-#
-# MemoryStick drivers
-#
-# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
-CONFIG_MSPRO_BLOCK=m
-CONFIG_MS_BLOCK=m
-
-#
-# MemoryStick Host Controller Drivers
-#
-CONFIG_MEMSTICK_TIFM_MS=m
-CONFIG_MEMSTICK_JMICRON_38X=m
-CONFIG_MEMSTICK_R592=m
-CONFIG_MEMSTICK_REALTEK_PCI=m
-CONFIG_MEMSTICK_REALTEK_USB=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_CLASS_FLASH=m
-CONFIG_LEDS_CLASS_MULTICOLOR=m
-CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y
-
-#
-# LED drivers
-#
-CONFIG_LEDS_AN30259A=m
-CONFIG_LEDS_AW2013=m
-# CONFIG_LEDS_BCM6328 is not set
-# CONFIG_LEDS_BCM6358 is not set
-CONFIG_LEDS_CPCAP=m
-CONFIG_LEDS_CR0014114=m
-CONFIG_LEDS_EL15203000=m
-CONFIG_LEDS_LM3530=m
-CONFIG_LEDS_LM3532=m
-CONFIG_LEDS_LM3533=m
-CONFIG_LEDS_LM3642=m
-CONFIG_LEDS_LM3692X=m
-CONFIG_LEDS_PCA9532=m
-CONFIG_LEDS_PCA9532_GPIO=y
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_LP3944=m
-CONFIG_LEDS_LP3952=m
-CONFIG_LEDS_LP50XX=m
-CONFIG_LEDS_LP55XX_COMMON=m
-CONFIG_LEDS_LP5521=m
-CONFIG_LEDS_LP5523=m
-CONFIG_LEDS_LP5562=m
-CONFIG_LEDS_LP8501=m
-CONFIG_LEDS_LP8860=m
-CONFIG_LEDS_PCA955X=m
-CONFIG_LEDS_PCA955X_GPIO=y
-CONFIG_LEDS_PCA963X=m
-# CONFIG_LEDS_DAC124S085 is not set
-CONFIG_LEDS_PWM=m
-# CONFIG_LEDS_REGULATOR is not set
-CONFIG_LEDS_BD2802=m
-CONFIG_LEDS_LT3593=m
-CONFIG_LEDS_TCA6507=m
-# CONFIG_LEDS_TLC591XX is not set
-CONFIG_LEDS_MAX77650=m
-CONFIG_LEDS_LM355x=m
-CONFIG_LEDS_MENF21BMC=m
-CONFIG_LEDS_IS31FL319X=m
-CONFIG_LEDS_IS31FL32XX=m
-CONFIG_LEDS_SC27XX_BLTC=m
-
-#
-# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
-#
-CONFIG_LEDS_BLINKM=m
-CONFIG_LEDS_SYSCON=y
-CONFIG_LEDS_MLXREG=m
-CONFIG_LEDS_USER=m
-CONFIG_LEDS_SPI_BYTE=m
-CONFIG_LEDS_TI_LMU_COMMON=m
-CONFIG_LEDS_BCM63138=m
-CONFIG_LEDS_LM3697=m
-CONFIG_LEDS_LM36274=m
-
-#
-# Flash and Torch LED drivers
-#
-# CONFIG_LEDS_AAT1290 is not set
-CONFIG_LEDS_AS3645A=m
-# CONFIG_LEDS_KTD2692 is not set
-CONFIG_LEDS_LM3601X=m
-CONFIG_LEDS_RT4505=m
-CONFIG_LEDS_RT8515=m
-CONFIG_LEDS_SGM3140=m
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_ONESHOT=m
-CONFIG_LEDS_TRIGGER_DISK=y
-CONFIG_LEDS_TRIGGER_MTD=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_LEDS_TRIGGER_BACKLIGHT=m
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_ACTIVITY=m
-CONFIG_LEDS_TRIGGER_GPIO=m
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-CONFIG_LEDS_TRIGGER_TRANSIENT=m
-CONFIG_LEDS_TRIGGER_CAMERA=m
-CONFIG_LEDS_TRIGGER_PANIC=y
-CONFIG_LEDS_TRIGGER_NETDEV=m
-CONFIG_LEDS_TRIGGER_PATTERN=m
-CONFIG_LEDS_TRIGGER_AUDIO=m
-CONFIG_LEDS_TRIGGER_TTY=m
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_INFINIBAND=m
-CONFIG_INFINIBAND_USER_MAD=m
-CONFIG_INFINIBAND_USER_ACCESS=m
-CONFIG_INFINIBAND_USER_MEM=y
-CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
-CONFIG_INFINIBAND_ADDR_TRANS=y
-CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
-CONFIG_INFINIBAND_VIRT_DMA=y
-CONFIG_INFINIBAND_MTHCA=m
-# CONFIG_INFINIBAND_MTHCA_DEBUG is not set
-CONFIG_INFINIBAND_CXGB4=m
-CONFIG_INFINIBAND_EFA=m
-CONFIG_INFINIBAND_ERDMA=m
-CONFIG_INFINIBAND_IRDMA=m
-CONFIG_MLX4_INFINIBAND=m
-CONFIG_MLX5_INFINIBAND=m
-CONFIG_INFINIBAND_OCRDMA=m
-# CONFIG_INFINIBAND_VMWARE_PVRDMA is not set
-CONFIG_INFINIBAND_HNS=m
-CONFIG_INFINIBAND_HNS_HIP06=y
-CONFIG_INFINIBAND_HNS_HIP08=y
-CONFIG_INFINIBAND_BNXT_RE=m
-CONFIG_INFINIBAND_QEDR=m
-CONFIG_RDMA_RXE=m
-CONFIG_RDMA_SIW=m
-CONFIG_INFINIBAND_IPOIB=m
-CONFIG_INFINIBAND_IPOIB_CM=y
-# CONFIG_INFINIBAND_IPOIB_DEBUG is not set
-CONFIG_INFINIBAND_SRP=m
-CONFIG_INFINIBAND_SRPT=m
-CONFIG_INFINIBAND_ISER=m
-CONFIG_INFINIBAND_ISERT=m
-CONFIG_INFINIBAND_RTRS=m
-CONFIG_INFINIBAND_RTRS_CLIENT=m
-CONFIG_INFINIBAND_RTRS_SERVER=m
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EDAC=m
-CONFIG_EDAC_LEGACY_SYSFS=y
-# CONFIG_EDAC_DEBUG is not set
-CONFIG_EDAC_GHES=y
-CONFIG_EDAC_AL_MC=m
-CONFIG_EDAC_LAYERSCAPE=m
-CONFIG_EDAC_THUNDERX=m
-CONFIG_EDAC_ALTERA=y
-CONFIG_EDAC_ALTERA_SDRAM=y
-CONFIG_EDAC_ALTERA_OCRAM=y
-CONFIG_EDAC_ALTERA_ETHERNET=y
-CONFIG_EDAC_ALTERA_NAND=y
-CONFIG_EDAC_ALTERA_USB=y
-CONFIG_EDAC_ALTERA_QSPI=y
-CONFIG_EDAC_ALTERA_SDMMC=y
-CONFIG_EDAC_SYNOPSYS=m
-CONFIG_EDAC_XGENE=m
-CONFIG_EDAC_QCOM=m
-CONFIG_EDAC_BLUEFIELD=m
-CONFIG_EDAC_DMC520=m
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-CONFIG_RTC_SYSTOHC=y
-CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-CONFIG_RTC_NVMEM=y
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-CONFIG_RTC_DRV_ABB5ZES3=m
-CONFIG_RTC_DRV_ABEOZ9=m
-CONFIG_RTC_DRV_ABX80X=m
-CONFIG_RTC_DRV_AC100=m
-CONFIG_RTC_DRV_BRCMSTB=m
-CONFIG_RTC_DRV_DS1307=m
-CONFIG_RTC_DRV_DS1307_CENTURY=y
-CONFIG_RTC_DRV_DS1374=m
-CONFIG_RTC_DRV_DS1374_WDT=y
-CONFIG_RTC_DRV_DS1672=m
-# CONFIG_RTC_DRV_HYM8563 is not set
-CONFIG_RTC_DRV_MAX6900=m
-CONFIG_RTC_DRV_MAX77686=m
-CONFIG_RTC_DRV_NCT3018Y=m
-CONFIG_RTC_DRV_TI_K3=m
-CONFIG_RTC_DRV_RK808=m
-CONFIG_RTC_DRV_RS5C372=m
-CONFIG_RTC_DRV_ISL1208=m
-# CONFIG_RTC_DRV_ISL12022 is not set
-CONFIG_RTC_DRV_ISL12026=m
-CONFIG_RTC_DRV_X1205=m
-CONFIG_RTC_DRV_PCF8523=m
-CONFIG_RTC_DRV_PCF85063=m
-CONFIG_RTC_DRV_PCF85363=m
-CONFIG_RTC_DRV_PCF8563=m
-CONFIG_RTC_DRV_PCF8583=m
-CONFIG_RTC_DRV_M41T80=m
-CONFIG_RTC_DRV_M41T80_WDT=y
-CONFIG_RTC_DRV_BD70528=m
-# CONFIG_RTC_DRV_BQ32K is not set
-CONFIG_RTC_DRV_S35390A=m
-CONFIG_RTC_DRV_FM3130=m
-CONFIG_RTC_DRV_RX8010=m
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-# CONFIG_RTC_DRV_EM3027 is not set
-CONFIG_RTC_DRV_RV3028=m
-CONFIG_RTC_DRV_RV3032=m
-CONFIG_RTC_DRV_RV8803=y
-CONFIG_RTC_DRV_SD3078=m
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T93 is not set
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1302 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_DS1343 is not set
-# CONFIG_RTC_DRV_DS1347 is not set
-# CONFIG_RTC_DRV_DS1390 is not set
-CONFIG_RTC_DRV_MAX6916=m
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RX4581 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_PCF2123 is not set
-# CONFIG_RTC_DRV_MCP795 is not set
-CONFIG_RTC_I2C_AND_SPI=y
-
-#
-# SPI and I2C RTC drivers
-#
-CONFIG_RTC_DRV_DS3232=m
-CONFIG_RTC_DRV_DS3232_HWMON=y
-CONFIG_RTC_DRV_PCF2127=m
-# CONFIG_RTC_DRV_RV3029C2 is not set
-# CONFIG_RTC_DRV_RX6110 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-CONFIG_RTC_DRV_DS1685_FAMILY=m
-CONFIG_RTC_DRV_DS1685=y
-# CONFIG_RTC_DRV_DS1689 is not set
-# CONFIG_RTC_DRV_DS17285 is not set
-# CONFIG_RTC_DRV_DS17485 is not set
-# CONFIG_RTC_DRV_DS17885 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_DS2404 is not set
-CONFIG_RTC_DRV_EFI=y
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_MSM6242 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_RP5C01 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-CONFIG_RTC_DRV_OPTEE=m
-CONFIG_RTC_DRV_SC27XX=m
-CONFIG_RTC_DRV_ZYNQMP=y
-CONFIG_RTC_DRV_CROS_EC=m
-
-#
-# on-CPU RTC drivers
-#
-CONFIG_RTC_DRV_IMXDI=m
-CONFIG_RTC_DRV_FSL_FTM_ALARM=m
-CONFIG_RTC_DRV_MESON_VRTC=m
-CONFIG_RTC_DRV_S3C=m
-CONFIG_RTC_DRV_SH=m
-CONFIG_RTC_DRV_PL030=y
-CONFIG_RTC_DRV_PL031=y
-CONFIG_RTC_DRV_SUN6I=y
-CONFIG_RTC_DRV_MV=y
-CONFIG_RTC_DRV_ARMADA38X=m
-CONFIG_RTC_DRV_CADENCE=m
-CONFIG_RTC_DRV_FTRTC010=m
-CONFIG_RTC_DRV_PM8XXX=m
-CONFIG_RTC_DRV_TEGRA=m
-CONFIG_RTC_DRV_MXC=m
-CONFIG_RTC_DRV_MXC_V2=m
-# CONFIG_RTC_DRV_SNVS is not set
-CONFIG_RTC_DRV_IMX_SC=y
-CONFIG_RTC_DRV_MT2712=y
-CONFIG_RTC_DRV_MT7622=m
-CONFIG_RTC_DRV_XGENE=y
-CONFIG_RTC_DRV_R7301=m
-CONFIG_RTC_DRV_CPCAP=m
-CONFIG_RTC_DRV_RTD119X=y
-
-#
-# HID Sensor RTC drivers
-#
-CONFIG_RTC_DRV_HID_SENSOR_TIME=m
-CONFIG_RTC_DRV_GOLDFISH=m
-CONFIG_DMADEVICES=y
-# CONFIG_DMADEVICES_DEBUG is not set
-
-#
-# DMA Devices
-#
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DMA_ACPI=y
-CONFIG_DMA_OF=y
-CONFIG_ALTERA_MSGDMA=m
-# CONFIG_AMBA_PL08X is not set
-CONFIG_APPLE_ADMAC=m
-CONFIG_AXI_DMAC=m
-CONFIG_BCM_SBA_RAID=m
-CONFIG_DMA_BCM2835=m
-CONFIG_DMA_SUN6I=m
-CONFIG_DW_AXI_DMAC=m
-CONFIG_FSL_EDMA=m
-CONFIG_FSL_QDMA=m
-CONFIG_HISI_DMA=m
-CONFIG_IMX_DMA=m
-CONFIG_IMX_SDMA=m
-# CONFIG_INTEL_IDMA64 is not set
-CONFIG_K3_DMA=m
-CONFIG_MV_XOR=y
-CONFIG_MV_XOR_V2=y
-CONFIG_MXS_DMA=y
-CONFIG_MX3_IPU=y
-CONFIG_MX3_IPU_IRQS=4
-CONFIG_OWL_DMA=m
-CONFIG_PL330_DMA=m
-CONFIG_PLX_DMA=m
-CONFIG_SPRD_DMA=m
-CONFIG_TEGRA20_APB_DMA=m
-CONFIG_TEGRA210_ADMA=m
-CONFIG_UNIPHIER_MDMAC=m
-CONFIG_UNIPHIER_XDMAC=m
-CONFIG_XGENE_DMA=m
-CONFIG_XILINX_DMA=m
-CONFIG_XILINX_ZYNQMP_DMA=m
-CONFIG_XILINX_ZYNQMP_DPDMA=m
-CONFIG_MTK_HSDMA=m
-CONFIG_MTK_CQDMA=m
-CONFIG_MTK_UART_APDMA=m
-CONFIG_QCOM_BAM_DMA=m
-CONFIG_QCOM_GPI_DMA=m
-CONFIG_QCOM_HIDMA_MGMT=m
-CONFIG_QCOM_HIDMA=m
-CONFIG_DW_DMAC_CORE=m
-# CONFIG_DW_DMAC is not set
-CONFIG_DW_DMAC_PCI=m
-CONFIG_DW_EDMA=m
-CONFIG_DW_EDMA_PCIE=m
-# CONFIG_SF_PDMA is not set
-CONFIG_RENESAS_DMA=y
-CONFIG_RCAR_DMAC=m
-CONFIG_RENESAS_USB_DMAC=m
-CONFIG_RZ_DMAC=m
-CONFIG_TI_K3_UDMA=y
-CONFIG_TI_K3_UDMA_GLUE_LAYER=y
-CONFIG_TI_K3_PSIL=y
-CONFIG_FSL_DPAA2_QDMA=m
-
-#
-# DMA Clients
-#
-CONFIG_ASYNC_TX_DMA=y
-# CONFIG_DMATEST is not set
-CONFIG_DMA_ENGINE_RAID=y
-
-#
-# DMABUF options
-#
-CONFIG_SYNC_FILE=y
-CONFIG_SW_SYNC=y
-CONFIG_UDMABUF=y
-# CONFIG_DMABUF_MOVE_NOTIFY is not set
-# CONFIG_DMABUF_DEBUG is not set
-# CONFIG_DMABUF_SELFTESTS is not set
-# CONFIG_DMABUF_HEAPS is not set
-# CONFIG_DMABUF_SYSFS_STATS is not set
-# end of DMABUF options
-
-CONFIG_AUXDISPLAY=y
-CONFIG_CHARLCD=m
-CONFIG_LINEDISP=m
-CONFIG_HD44780_COMMON=m
-CONFIG_HD44780=m
-CONFIG_KS0108=m
-CONFIG_KS0108_PORT=0x378
-CONFIG_KS0108_DELAY=2
-# CONFIG_IMG_ASCII_LCD is not set
-CONFIG_HT16K33=m
-# CONFIG_LCD2S is not set
-CONFIG_PARPORT_PANEL=m
-CONFIG_PANEL_PARPORT=0
-CONFIG_PANEL_PROFILE=5
-# CONFIG_PANEL_CHANGE_MESSAGE is not set
-# CONFIG_CHARLCD_BL_OFF is not set
-# CONFIG_CHARLCD_BL_ON is not set
-CONFIG_CHARLCD_BL_FLASH=y
-CONFIG_PANEL=m
-CONFIG_UIO=m
-CONFIG_UIO_CIF=m
-CONFIG_UIO_PDRV_GENIRQ=m
-CONFIG_UIO_DMEM_GENIRQ=m
-CONFIG_UIO_AEC=m
-CONFIG_UIO_SERCOS3=m
-CONFIG_UIO_PCI_GENERIC=m
-CONFIG_UIO_NETX=m
-# CONFIG_UIO_PRUSS is not set
-CONFIG_UIO_MF624=m
-CONFIG_UIO_HV_GENERIC=m
-CONFIG_UIO_DFL=m
-CONFIG_VFIO=m
-CONFIG_VFIO_IOMMU_TYPE1=m
-CONFIG_VFIO_VIRQFD=m
-# CONFIG_VFIO_NOIOMMU is not set
-CONFIG_VFIO_PCI_CORE=m
-CONFIG_VFIO_PCI_MMAP=y
-CONFIG_VFIO_PCI_INTX=y
-CONFIG_VFIO_PCI=m
-CONFIG_MLX5_VFIO_PCI=m
-CONFIG_HISI_ACC_VFIO_PCI=m
-# CONFIG_VFIO_PLATFORM is not set
-CONFIG_VFIO_MDEV=m
-CONFIG_VFIO_FSL_MC=m
-CONFIG_VIRT_DRIVERS=y
-CONFIG_VMGENID=m
-# CONFIG_NITRO_ENCLAVES is not set
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_PCI_LIB=y
-CONFIG_VIRTIO_PCI_LIB_LEGACY=y
-CONFIG_VIRTIO_MENU=y
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_VDPA=m
-CONFIG_VIRTIO_PMEM=m
-CONFIG_VIRTIO_BALLOON=m
-CONFIG_VIRTIO_MEM=m
-CONFIG_VIRTIO_INPUT=m
-CONFIG_VIRTIO_MMIO=m
-# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
-CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
-CONFIG_VDPA=m
-CONFIG_VDPA_SIM=m
-CONFIG_VDPA_SIM_NET=m
-CONFIG_VDPA_SIM_BLOCK=m
-CONFIG_VDPA_USER=m
-CONFIG_IFCVF=m
-CONFIG_MLX5_VDPA=y
-CONFIG_MLX5_VDPA_NET=m
-CONFIG_VP_VDPA=m
-CONFIG_VHOST_IOTLB=m
-CONFIG_VHOST_RING=m
-CONFIG_VHOST=m
-CONFIG_VHOST_MENU=y
-CONFIG_VHOST_NET=m
-CONFIG_VHOST_SCSI=m
-CONFIG_VHOST_VSOCK=m
-CONFIG_VHOST_VDPA=m
-# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
-
-#
-# Microsoft Hyper-V guest support
-#
-CONFIG_HYPERV=m
-CONFIG_HYPERV_UTILS=m
-CONFIG_HYPERV_BALLOON=m
-# end of Microsoft Hyper-V guest support
-
-# CONFIG_GREYBUS is not set
-CONFIG_COMEDI=m
-# CONFIG_COMEDI_DEBUG is not set
-CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
-CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
-# CONFIG_COMEDI_MISC_DRIVERS is not set
-# CONFIG_COMEDI_ISA_DRIVERS is not set
-# CONFIG_COMEDI_PCI_DRIVERS is not set
-CONFIG_COMEDI_USB_DRIVERS=m
-CONFIG_COMEDI_DT9812=m
-CONFIG_COMEDI_NI_USB6501=m
-CONFIG_COMEDI_USBDUX=m
-CONFIG_COMEDI_USBDUXFAST=m
-CONFIG_COMEDI_USBDUXSIGMA=m
-CONFIG_COMEDI_VMK80XX=m
-CONFIG_COMEDI_8255=m
-CONFIG_COMEDI_8255_SA=m
-CONFIG_COMEDI_KCOMEDILIB=m
-# CONFIG_COMEDI_TESTS is not set
-CONFIG_STAGING=y
-CONFIG_PRISM2_USB=m
-CONFIG_RTL8192U=m
-CONFIG_RTLLIB=m
-CONFIG_RTLLIB_CRYPTO_CCMP=m
-CONFIG_RTLLIB_CRYPTO_TKIP=m
-CONFIG_RTLLIB_CRYPTO_WEP=m
-CONFIG_RTL8192E=m
-CONFIG_RTL8723BS=m
-CONFIG_R8712U=m
-CONFIG_R8188EU=m
-CONFIG_RTS5208=m
-CONFIG_VT6655=m
-CONFIG_VT6656=m
-
-#
-# IIO staging drivers
-#
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16203=m
-CONFIG_ADIS16240=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD7816=m
-CONFIG_AD7280=m
-# end of Analog to digital converters
-
-#
-# Analog digital bi-direction converters
-#
-CONFIG_ADT7316=m
-CONFIG_ADT7316_SPI=m
-CONFIG_ADT7316_I2C=m
-# end of Analog digital bi-direction converters
-
-#
-# Capacitance to digital converters
-#
-CONFIG_AD7746=m
-# end of Capacitance to digital converters
-
-#
-# Direct Digital Synthesis
-#
-CONFIG_AD9832=m
-CONFIG_AD9834=m
-# end of Direct Digital Synthesis
-
-#
-# Network Analyzer, Impedance Converters
-#
-CONFIG_AD5933=m
-# end of Network Analyzer, Impedance Converters
-
-#
-# Active energy metering IC
-#
-CONFIG_ADE7854=m
-CONFIG_ADE7854_I2C=m
-CONFIG_ADE7854_SPI=m
-# end of Active energy metering IC
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S1210=m
-# end of Resolver to digital converters
-# end of IIO staging drivers
-
-CONFIG_FB_SM750=m
-CONFIG_USB_EMXX=m
-CONFIG_MFD_NVEC=m
-CONFIG_KEYBOARD_NVEC=m
-CONFIG_SERIO_NVEC_PS2=m
-CONFIG_NVEC_POWER=m
-CONFIG_NVEC_PAZ00=m
-CONFIG_STAGING_MEDIA=y
-CONFIG_VIDEO_HANTRO=m
-CONFIG_VIDEO_HANTRO_IMX8M=y
-CONFIG_VIDEO_HANTRO_ROCKCHIP=y
-CONFIG_VIDEO_HANTRO_SUNXI=y
-CONFIG_VIDEO_IMX_MEDIA=m
-
-#
-# i.MX5/6/7/8 Media Sub devices
-#
-CONFIG_VIDEO_IMX7_CSI=m
-# end of i.MX5/6/7/8 Media Sub devices
-
-CONFIG_VIDEO_MESON_VDEC=m
-CONFIG_VIDEO_ROCKCHIP_VDEC=m
-CONFIG_VIDEO_STKWEBCAM=m
-CONFIG_VIDEO_SUNXI=y
-CONFIG_VIDEO_SUNXI_CEDRUS=m
-CONFIG_TEGRA_VDE=m
-CONFIG_VIDEO_ZORAN=m
-CONFIG_VIDEO_ZORAN_DC30=y
-CONFIG_VIDEO_ZORAN_ZR36060=y
-CONFIG_VIDEO_ZORAN_BUZ=y
-CONFIG_VIDEO_ZORAN_DC10=y
-CONFIG_VIDEO_ZORAN_LML33=y
-CONFIG_VIDEO_ZORAN_LML33R10=y
-CONFIG_VIDEO_ZORAN_AVS6EYES=y
-CONFIG_VIDEO_TEGRA=m
-# CONFIG_VIDEO_TEGRA_TPG is not set
-CONFIG_DVB_AV7110_IR=y
-CONFIG_DVB_AV7110=m
-CONFIG_DVB_AV7110_OSD=y
-CONFIG_DVB_BUDGET_PATCH=m
-CONFIG_DVB_SP8870=m
-
-#
-# Android
-#
-CONFIG_ASHMEM=m
-# end of Android
-
-# CONFIG_STAGING_BOARD is not set
-CONFIG_LTE_GDM724X=m
-CONFIG_FIREWIRE_SERIAL=m
-CONFIG_FWTTY_MAX_TOTAL_PORTS=64
-CONFIG_FWTTY_MAX_CARD_PORTS=32
-CONFIG_GS_FPGABOOT=m
-# CONFIG_UNISYSSPAR is not set
-CONFIG_COMMON_CLK_XLNX_CLKWZRD=m
-CONFIG_FB_TFT=m
-CONFIG_FB_TFT_AGM1264K_FL=m
-CONFIG_FB_TFT_BD663474=m
-CONFIG_FB_TFT_HX8340BN=m
-CONFIG_FB_TFT_HX8347D=m
-CONFIG_FB_TFT_HX8353D=m
-CONFIG_FB_TFT_HX8357D=m
-CONFIG_FB_TFT_ILI9163=m
-CONFIG_FB_TFT_ILI9320=m
-CONFIG_FB_TFT_ILI9325=m
-CONFIG_FB_TFT_ILI9340=m
-CONFIG_FB_TFT_ILI9341=m
-CONFIG_FB_TFT_ILI9481=m
-CONFIG_FB_TFT_ILI9486=m
-CONFIG_FB_TFT_PCD8544=m
-CONFIG_FB_TFT_RA8875=m
-CONFIG_FB_TFT_S6D02A1=m
-CONFIG_FB_TFT_S6D1121=m
-CONFIG_FB_TFT_SEPS525=m
-CONFIG_FB_TFT_SH1106=m
-CONFIG_FB_TFT_SSD1289=m
-CONFIG_FB_TFT_SSD1305=m
-CONFIG_FB_TFT_SSD1306=m
-CONFIG_FB_TFT_SSD1331=m
-CONFIG_FB_TFT_SSD1351=m
-CONFIG_FB_TFT_ST7735R=m
-CONFIG_FB_TFT_ST7789V=m
-CONFIG_FB_TFT_TINYLCD=m
-CONFIG_FB_TFT_TLS8204=m
-CONFIG_FB_TFT_UC1611=m
-CONFIG_FB_TFT_UC1701=m
-CONFIG_FB_TFT_UPD161704=m
-CONFIG_FB_TFT_WATTEROTT=m
-CONFIG_KS7010=m
-CONFIG_BCM_VIDEOCORE=m
-CONFIG_BCM2835_VCHIQ=m
-CONFIG_VCHIQ_CDEV=y
-CONFIG_SND_BCM2835=m
-CONFIG_VIDEO_BCM2835=m
-CONFIG_BCM2835_VCHIQ_MMAL=m
-CONFIG_PI433=m
-CONFIG_XIL_AXIS_FIFO=m
-CONFIG_FIELDBUS_DEV=m
-CONFIG_HMS_ANYBUSS_BUS=m
-CONFIG_ARCX_ANYBUS_CONTROLLER=m
-CONFIG_HMS_PROFINET=m
-CONFIG_QLGE=m
-CONFIG_WFX=m
-CONFIG_RTL8723CS=m
-# CONFIG_GOLDFISH is not set
-CONFIG_CHROME_PLATFORMS=y
-CONFIG_CHROMEOS_ACPI=m
-CONFIG_CHROMEOS_TBMC=m
-CONFIG_CROS_EC=m
-CONFIG_CROS_EC_I2C=m
-CONFIG_CROS_EC_RPMSG=m
-CONFIG_CROS_EC_SPI=m
-CONFIG_CROS_EC_PROTO=y
-CONFIG_CROS_KBD_LED_BACKLIGHT=m
-CONFIG_CROS_EC_CHARDEV=m
-CONFIG_CROS_EC_LIGHTBAR=m
-CONFIG_CROS_EC_VBC=m
-# CONFIG_CROS_EC_DEBUGFS is not set
-CONFIG_CROS_EC_SENSORHUB=m
-CONFIG_CROS_EC_SYSFS=m
-CONFIG_CROS_EC_TYPEC=m
-CONFIG_CROS_USBPD_LOGGER=m
-CONFIG_CROS_USBPD_NOTIFY=m
-CONFIG_CHROMEOS_PRIVACY_SCREEN=m
-CONFIG_CROS_TYPEC_SWITCH=m
-CONFIG_MELLANOX_PLATFORM=y
-CONFIG_MLXREG_HOTPLUG=m
-CONFIG_MLXREG_IO=m
-CONFIG_MLXREG_LC=m
-CONFIG_MLXBF_TMFIFO=m
-CONFIG_MLXBF_BOOTCTL=m
-CONFIG_MLXBF_PMC=m
-CONFIG_NVSW_SN2201=m
-CONFIG_SURFACE_PLATFORMS=y
-CONFIG_SURFACE_3_BUTTON=m
-CONFIG_SURFACE_3_POWER_OPREGION=m
-CONFIG_SURFACE_ACPI_NOTIFY=m
-CONFIG_SURFACE_AGGREGATOR_CDEV=m
-CONFIG_SURFACE_AGGREGATOR_HUB=m
-CONFIG_SURFACE_AGGREGATOR_REGISTRY=m
-CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m
-CONFIG_SURFACE_DTX=m
-CONFIG_SURFACE_GPE=m
-CONFIG_SURFACE_HOTPLUG=m
-CONFIG_SURFACE_PLATFORM_PROFILE=m
-CONFIG_SURFACE_PRO3_BUTTON=m
-CONFIG_SURFACE_AGGREGATOR=m
-CONFIG_SURFACE_AGGREGATOR_BUS=y
-# CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION is not set
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_COMMON_CLK=y
-
-#
-# Clock driver for ARM Reference designs
-#
-# CONFIG_CLK_ICST is not set
-CONFIG_CLK_SP810=y
-CONFIG_CLK_VEXPRESS_OSC=y
-# end of Clock driver for ARM Reference designs
-
-CONFIG_LMK04832=m
-CONFIG_COMMON_CLK_APPLE_NCO=m
-CONFIG_COMMON_CLK_MAX77686=m
-CONFIG_COMMON_CLK_MAX9485=m
-CONFIG_COMMON_CLK_RK808=m
-CONFIG_COMMON_CLK_HI655X=m
-CONFIG_COMMON_CLK_SCMI=m
-CONFIG_COMMON_CLK_SCPI=m
-CONFIG_COMMON_CLK_SI5341=m
-CONFIG_COMMON_CLK_SI5351=m
-CONFIG_COMMON_CLK_SI514=m
-CONFIG_COMMON_CLK_SI544=m
-CONFIG_COMMON_CLK_SI570=m
-CONFIG_COMMON_CLK_BM1880=y
-CONFIG_COMMON_CLK_CDCE706=m
-CONFIG_COMMON_CLK_TPS68470=m
-CONFIG_COMMON_CLK_CDCE925=m
-CONFIG_COMMON_CLK_CS2000_CP=m
-CONFIG_COMMON_CLK_FSL_FLEXSPI=m
-CONFIG_COMMON_CLK_FSL_SAI=y
-CONFIG_COMMON_CLK_AXI_CLKGEN=m
-CONFIG_CLK_QORIQ=y
-CONFIG_CLK_LS1028A_PLLDIG=m
-# CONFIG_COMMON_CLK_XGENE is not set
-CONFIG_COMMON_CLK_LOCHNAGAR=m
-CONFIG_COMMON_CLK_PWM=m
-CONFIG_COMMON_CLK_RS9_PCIE=m
-CONFIG_COMMON_CLK_VC5=m
-CONFIG_COMMON_CLK_VC7=m
-CONFIG_COMMON_CLK_BD718XX=m
-CONFIG_COMMON_CLK_FIXED_MMIO=y
-CONFIG_CLK_ACTIONS=y
-# CONFIG_CLK_OWL_S500 is not set
-CONFIG_CLK_OWL_S700=y
-CONFIG_CLK_OWL_S900=y
-CONFIG_CLK_BCM2711_DVP=m
-CONFIG_CLK_BCM2835=y
-CONFIG_CLK_BCM_63XX=y
-CONFIG_COMMON_CLK_IPROC=y
-CONFIG_CLK_BCM_NS2=y
-CONFIG_CLK_BCM_SR=y
-CONFIG_CLK_RASPBERRYPI=m
-CONFIG_COMMON_CLK_HI3516CV300=m
-CONFIG_COMMON_CLK_HI3519=m
-CONFIG_COMMON_CLK_HI3559A=y
-CONFIG_COMMON_CLK_HI3660=y
-CONFIG_COMMON_CLK_HI3670=y
-CONFIG_COMMON_CLK_HI3798CV200=m
-CONFIG_COMMON_CLK_HI6220=y
-CONFIG_RESET_HISI=y
-CONFIG_STUB_CLK_HI6220=y
-CONFIG_STUB_CLK_HI3660=y
-CONFIG_MXC_CLK=y
-CONFIG_MXC_CLK_SCU=y
-CONFIG_CLK_IMX8MM=y
-CONFIG_CLK_IMX8MN=y
-CONFIG_CLK_IMX8MP=y
-CONFIG_CLK_IMX8MQ=y
-CONFIG_CLK_IMX8QXP=y
-CONFIG_CLK_IMX8ULP=m
-CONFIG_CLK_IMX93=m
-CONFIG_TI_SCI_CLK=m
-CONFIG_TI_SCI_CLK_PROBE_FROM_FW=y
-CONFIG_TI_SYSCON_CLK=m
-
-#
-# Clock driver for MediaTek SoC
-#
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2712=y
-CONFIG_COMMON_CLK_MT2712_BDPSYS=y
-CONFIG_COMMON_CLK_MT2712_IMGSYS=y
-CONFIG_COMMON_CLK_MT2712_JPGDECSYS=y
-CONFIG_COMMON_CLK_MT2712_MFGCFG=y
-CONFIG_COMMON_CLK_MT2712_MMSYS=y
-CONFIG_COMMON_CLK_MT2712_VDECSYS=y
-CONFIG_COMMON_CLK_MT2712_VENCSYS=y
-CONFIG_COMMON_CLK_MT6765=y
-CONFIG_COMMON_CLK_MT6765_AUDIOSYS=y
-CONFIG_COMMON_CLK_MT6765_CAMSYS=y
-CONFIG_COMMON_CLK_MT6765_GCESYS=y
-CONFIG_COMMON_CLK_MT6765_MMSYS=y
-CONFIG_COMMON_CLK_MT6765_IMGSYS=y
-CONFIG_COMMON_CLK_MT6765_VCODECSYS=y
-CONFIG_COMMON_CLK_MT6765_MFGSYS=y
-CONFIG_COMMON_CLK_MT6765_MIPI0ASYS=y
-CONFIG_COMMON_CLK_MT6765_MIPI0BSYS=y
-CONFIG_COMMON_CLK_MT6765_MIPI1ASYS=y
-CONFIG_COMMON_CLK_MT6765_MIPI1BSYS=y
-CONFIG_COMMON_CLK_MT6765_MIPI2ASYS=y
-CONFIG_COMMON_CLK_MT6765_MIPI2BSYS=y
-CONFIG_COMMON_CLK_MT6779=y
-CONFIG_COMMON_CLK_MT6779_MMSYS=y
-CONFIG_COMMON_CLK_MT6779_IMGSYS=y
-CONFIG_COMMON_CLK_MT6779_IPESYS=y
-CONFIG_COMMON_CLK_MT6779_CAMSYS=y
-CONFIG_COMMON_CLK_MT6779_VDECSYS=y
-CONFIG_COMMON_CLK_MT6779_VENCSYS=y
-CONFIG_COMMON_CLK_MT6779_MFGCFG=y
-CONFIG_COMMON_CLK_MT6779_AUDSYS=y
-CONFIG_COMMON_CLK_MT6795=m
-CONFIG_COMMON_CLK_MT6795_MFGCFG=m
-CONFIG_COMMON_CLK_MT6795_MMSYS=m
-CONFIG_COMMON_CLK_MT6795_VDECSYS=m
-CONFIG_COMMON_CLK_MT6795_VENCSYS=m
-CONFIG_COMMON_CLK_MT6797=y
-CONFIG_COMMON_CLK_MT6797_MMSYS=y
-CONFIG_COMMON_CLK_MT6797_IMGSYS=y
-CONFIG_COMMON_CLK_MT6797_VDECSYS=y
-CONFIG_COMMON_CLK_MT6797_VENCSYS=y
-CONFIG_COMMON_CLK_MT7622=y
-CONFIG_COMMON_CLK_MT7622_ETHSYS=y
-CONFIG_COMMON_CLK_MT7622_HIFSYS=y
-CONFIG_COMMON_CLK_MT7622_AUDSYS=y
-CONFIG_COMMON_CLK_MT8167=y
-CONFIG_COMMON_CLK_MT8167_AUDSYS=y
-CONFIG_COMMON_CLK_MT8167_IMGSYS=y
-CONFIG_COMMON_CLK_MT8167_MFGCFG=y
-CONFIG_COMMON_CLK_MT8167_MMSYS=y
-CONFIG_COMMON_CLK_MT8167_VDECSYS=y
-CONFIG_COMMON_CLK_MT8173=y
-CONFIG_COMMON_CLK_MT8173_MMSYS=y
-CONFIG_COMMON_CLK_MT8365=m
-CONFIG_COMMON_CLK_MT8365_APU=m
-CONFIG_COMMON_CLK_MT8365_CAM=m
-CONFIG_COMMON_CLK_MT8365_MFG=m
-CONFIG_COMMON_CLK_MT8365_MMSYS=m
-CONFIG_COMMON_CLK_MT8365_VDEC=m
-CONFIG_COMMON_CLK_MT8365_VENC=m
-CONFIG_COMMON_CLK_MT8183=y
-CONFIG_COMMON_CLK_MT8183_AUDIOSYS=y
-CONFIG_COMMON_CLK_MT8183_CAMSYS=y
-CONFIG_COMMON_CLK_MT8183_IMGSYS=y
-CONFIG_COMMON_CLK_MT8183_IPU_CORE0=y
-CONFIG_COMMON_CLK_MT8183_IPU_CORE1=y
-CONFIG_COMMON_CLK_MT8183_IPU_ADL=y
-CONFIG_COMMON_CLK_MT8183_IPU_CONN=y
-CONFIG_COMMON_CLK_MT8183_MFGCFG=y
-CONFIG_COMMON_CLK_MT8183_MMSYS=y
-CONFIG_COMMON_CLK_MT8183_VDECSYS=y
-CONFIG_COMMON_CLK_MT8183_VENCSYS=y
-CONFIG_COMMON_CLK_MT8186=y
-CONFIG_COMMON_CLK_MT8192=y
-CONFIG_COMMON_CLK_MT8192_AUDSYS=y
-CONFIG_COMMON_CLK_MT8192_CAMSYS=y
-CONFIG_COMMON_CLK_MT8192_IMGSYS=y
-CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP=y
-CONFIG_COMMON_CLK_MT8192_IPESYS=y
-CONFIG_COMMON_CLK_MT8192_MDPSYS=y
-CONFIG_COMMON_CLK_MT8192_MFGCFG=y
-CONFIG_COMMON_CLK_MT8192_MMSYS=y
-CONFIG_COMMON_CLK_MT8192_MSDC=y
-CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y
-CONFIG_COMMON_CLK_MT8192_VDECSYS=y
-CONFIG_COMMON_CLK_MT8192_VENCSYS=y
-CONFIG_COMMON_CLK_MT8195=y
-CONFIG_COMMON_CLK_MT8516=y
-CONFIG_COMMON_CLK_MT8516_AUDSYS=y
-# end of Clock driver for MediaTek SoC
-
-#
-# Clock support for Amlogic platforms
-#
-CONFIG_COMMON_CLK_MESON_REGMAP=y
-CONFIG_COMMON_CLK_MESON_DUALDIV=y
-CONFIG_COMMON_CLK_MESON_MPLL=y
-CONFIG_COMMON_CLK_MESON_PHASE=m
-CONFIG_COMMON_CLK_MESON_PLL=y
-CONFIG_COMMON_CLK_MESON_SCLK_DIV=m
-CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y
-CONFIG_COMMON_CLK_MESON_AO_CLKC=y
-CONFIG_COMMON_CLK_MESON_EE_CLKC=y
-CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y
-CONFIG_COMMON_CLK_GXBB=y
-CONFIG_COMMON_CLK_AXG=y
-CONFIG_COMMON_CLK_AXG_AUDIO=m
-CONFIG_COMMON_CLK_G12A=y
-# end of Clock support for Amlogic platforms
-
-CONFIG_ARMADA_AP_CP_HELPER=y
-CONFIG_ARMADA_37XX_CLK=y
-CONFIG_ARMADA_AP806_SYSCON=y
-CONFIG_ARMADA_AP_CPU_CLK=y
-CONFIG_ARMADA_CP110_SYSCON=y
-CONFIG_QCOM_GDSC=y
-CONFIG_QCOM_RPMCC=y
-CONFIG_COMMON_CLK_QCOM=m
-CONFIG_QCOM_A53PLL=m
-CONFIG_QCOM_A7PLL=m
-CONFIG_QCOM_CLK_APCS_MSM8916=m
-CONFIG_QCOM_CLK_APCC_MSM8996=m
-CONFIG_QCOM_CLK_APCS_SDX55=m
-CONFIG_QCOM_CLK_RPM=m
-CONFIG_QCOM_CLK_SMD_RPM=m
-CONFIG_QCOM_CLK_RPMH=m
-# CONFIG_APQ_GCC_8084 is not set
-# CONFIG_APQ_MMCC_8084 is not set
-CONFIG_IPQ_APSS_PLL=m
-CONFIG_IPQ_APSS_6018=m
-# CONFIG_IPQ_GCC_4019 is not set
-CONFIG_IPQ_GCC_6018=m
-# CONFIG_IPQ_GCC_806X is not set
-# CONFIG_IPQ_LCC_806X is not set
-# CONFIG_IPQ_GCC_8074 is not set
-# CONFIG_MSM_GCC_8660 is not set
-CONFIG_MSM_GCC_8909=m
-CONFIG_MSM_GCC_8916=m
-CONFIG_MSM_GCC_8939=m
-# CONFIG_MSM_GCC_8960 is not set
-# CONFIG_MSM_LCC_8960 is not set
-CONFIG_MDM_GCC_9607=m
-# CONFIG_MDM_GCC_9615 is not set
-# CONFIG_MDM_LCC_9615 is not set
-# CONFIG_MSM_MMCC_8960 is not set
-CONFIG_MSM_GCC_8953=m
-# CONFIG_MSM_GCC_8974 is not set
-# CONFIG_MSM_MMCC_8974 is not set
-CONFIG_MSM_GCC_8976=m
-CONFIG_MSM_MMCC_8976=m
-CONFIG_MSM_MMCC_8994=m
-CONFIG_MSM_GCC_8994=m
-# CONFIG_MSM_GCC_8996 is not set
-# CONFIG_MSM_MMCC_8996 is not set
-CONFIG_MSM_GCC_8998=m
-CONFIG_MSM_GPUCC_8998=m
-CONFIG_MSM_MMCC_8998=m
-# CONFIG_QCM_GCC_2290 is not set
-CONFIG_QCM_DISPCC_2290=m
-CONFIG_QCS_GCC_404=m
-CONFIG_SC_CAMCC_7180=m
-# CONFIG_SC_CAMCC_7280 is not set
-CONFIG_SC_DISPCC_7180=m
-CONFIG_SC_DISPCC_7280=m
-CONFIG_SC_GCC_7180=m
-CONFIG_SC_GCC_7280=m
-CONFIG_SC_GCC_8180X=m
-CONFIG_SC_GCC_8280XP=m
-CONFIG_SC_GPUCC_7180=m
-CONFIG_SC_GPUCC_7280=m
-CONFIG_SC_GPUCC_8280XP=m
-# CONFIG_SC_LPASSCC_7280 is not set
-CONFIG_SC_LPASS_CORECC_7180=m
-CONFIG_SC_LPASS_CORECC_7280=m
-CONFIG_SC_MSS_7180=m
-CONFIG_SC_VIDEOCC_7180=m
-CONFIG_SC_VIDEOCC_7280=m
-CONFIG_SDM_CAMCC_845=m
-CONFIG_SDM_GCC_660=m
-CONFIG_SDM_MMCC_660=m
-CONFIG_SDM_GPUCC_660=m
-CONFIG_QCS_TURING_404=m
-CONFIG_QCS_Q6SSTOP_404=m
-CONFIG_SDM_GCC_845=m
-CONFIG_SDM_GPUCC_845=m
-CONFIG_SDM_VIDEOCC_845=m
-CONFIG_SDM_DISPCC_845=m
-CONFIG_SDM_LPASSCC_845=m
-CONFIG_SDX_GCC_55=m
-CONFIG_SM_CAMCC_8250=m
-CONFIG_SM_CAMCC_8450=m
-CONFIG_SM_DISPCC_6115=m
-CONFIG_SM_DISPCC_6125=m
-CONFIG_SDX_GCC_65=m
-CONFIG_SM_DISPCC_8250=m
-CONFIG_SM_DISPCC_6350=m
-CONFIG_SM_DISPCC_8450=m
-CONFIG_SM_GCC_6115=m
-CONFIG_SM_GCC_6125=m
-CONFIG_SM_GCC_6350=m
-CONFIG_SM_GCC_6375=m
-CONFIG_SM_GCC_8150=m
-CONFIG_SM_GCC_8250=m
-CONFIG_SM_GCC_8350=m
-CONFIG_SM_GCC_8450=m
-CONFIG_SM_GPUCC_6350=m
-CONFIG_SM_GPUCC_8150=m
-CONFIG_SM_GPUCC_8250=m
-CONFIG_SM_GPUCC_8350=m
-CONFIG_SM_VIDEOCC_8150=m
-CONFIG_SM_VIDEOCC_8250=m
-CONFIG_SPMI_PMIC_CLKDIV=m
-CONFIG_QCOM_HFPLL=m
-# CONFIG_KPSS_XCC is not set
-CONFIG_CLK_GFM_LPASS_SM8250=m
-CONFIG_CLK_RENESAS=y
-CONFIG_CLK_R8A774A1=y
-CONFIG_CLK_R8A774B1=y
-CONFIG_CLK_R8A774C0=y
-CONFIG_CLK_R8A774E1=y
-CONFIG_CLK_R8A7795=y
-CONFIG_CLK_R8A77960=y
-CONFIG_CLK_R8A77961=y
-CONFIG_CLK_R8A77965=y
-CONFIG_CLK_R8A77970=y
-CONFIG_CLK_R8A77980=y
-CONFIG_CLK_R8A77990=y
-CONFIG_CLK_R8A77995=y
-CONFIG_CLK_R8A779A0=y
-CONFIG_CLK_R9A07G044=y
-CONFIG_CLK_RCAR_CPG_LIB=y
-CONFIG_CLK_RCAR_GEN3_CPG=y
-CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
-CONFIG_CLK_RZG2L=y
-CONFIG_CLK_RENESAS_CPG_MSSR=y
-CONFIG_CLK_RENESAS_DIV6=y
-CONFIG_COMMON_CLK_ROCKCHIP=y
-CONFIG_CLK_PX30=y
-CONFIG_CLK_RK3308=y
-CONFIG_CLK_RK3328=y
-CONFIG_CLK_RK3368=y
-CONFIG_CLK_RK3399=y
-CONFIG_CLK_RK3568=y
-CONFIG_COMMON_CLK_SAMSUNG=y
-CONFIG_EXYNOS_ARM64_COMMON_CLK=y
-CONFIG_EXYNOS_AUDSS_CLK_CON=m
-CONFIG_EXYNOS_CLKOUT=m
-CONFIG_CLK_INTEL_SOCFPGA=y
-CONFIG_CLK_INTEL_SOCFPGA64=y
-CONFIG_SPRD_COMMON_CLK=m
-CONFIG_SPRD_SC9860_CLK=m
-CONFIG_SPRD_SC9863A_CLK=m
-CONFIG_SPRD_UMS512_CLK=m
-CONFIG_CLK_SUNXI=y
-CONFIG_CLK_SUNXI_CLOCKS=y
-CONFIG_CLK_SUNXI_PRCM_SUN6I=y
-CONFIG_CLK_SUNXI_PRCM_SUN8I=y
-CONFIG_CLK_SUNXI_PRCM_SUN9I=y
-CONFIG_SUNXI_CCU=y
-CONFIG_SUN50I_A64_CCU=y
-CONFIG_SUN50I_A100_CCU=y
-CONFIG_SUN50I_A100_R_CCU=y
-CONFIG_SUN50I_H6_CCU=y
-CONFIG_SUN50I_H616_CCU=y
-CONFIG_SUN50I_H6_R_CCU=y
-CONFIG_SUN6I_RTC_CCU=m
-CONFIG_SUN8I_H3_CCU=y
-CONFIG_SUN8I_DE2_CCU=y
-CONFIG_SUN8I_R_CCU=y
-CONFIG_CLK_TEGRA_BPMP=y
-CONFIG_TEGRA_CLK_DFLL=y
-CONFIG_CLK_UNIPHIER=y
-CONFIG_COMMON_CLK_VISCONTI=y
-CONFIG_XILINX_VCU=m
-CONFIG_COMMON_CLK_ZYNQMP=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_TEGRA186_TIMER=y
-CONFIG_HWSPINLOCK=y
-CONFIG_HWSPINLOCK_OMAP=m
-CONFIG_HWSPINLOCK_QCOM=m
-CONFIG_HWSPINLOCK_SPRD=m
-CONFIG_HWSPINLOCK_SUN6I=m
-
-#
-# Clock Source drivers
-#
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_ACPI=y
-CONFIG_TIMER_PROBE=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_DW_APB_TIMER=y
-CONFIG_DW_APB_TIMER_OF=y
-CONFIG_ROCKCHIP_TIMER=y
-CONFIG_OWL_TIMER=y
-CONFIG_SUN4I_TIMER=y
-CONFIG_TEGRA_TIMER=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
-CONFIG_FSL_ERRATUM_A008585=y
-CONFIG_HISILICON_ERRATUM_161010101=y
-CONFIG_ARM64_ERRATUM_858921=y
-CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
-CONFIG_ARM_TIMER_SP804=y
-CONFIG_SYS_SUPPORTS_SH_CMT=y
-CONFIG_MTK_TIMER=y
-CONFIG_SPRD_TIMER=y
-CONFIG_SYS_SUPPORTS_SH_TMU=y
-CONFIG_SH_TIMER_CMT=y
-CONFIG_SH_TIMER_TMU=y
-CONFIG_TIMER_IMX_SYS_CTR=y
-CONFIG_MICROCHIP_PIT64B=y
-# end of Clock Source drivers
-
-CONFIG_MAILBOX=y
-CONFIG_APPLE_MAILBOX=y
-CONFIG_ARM_MHU=m
-CONFIG_ARM_MHU_V2=m
-CONFIG_IMX_MBOX=m
-CONFIG_PLATFORM_MHU=m
-CONFIG_PL320_MBOX=y
-CONFIG_ARMADA_37XX_RWTM_MBOX=m
-CONFIG_OMAP2PLUS_MBOX=m
-CONFIG_OMAP_MBOX_KFIFO_SIZE=256
-CONFIG_ROCKCHIP_MBOX=y
-CONFIG_PCC=y
-# CONFIG_ALTERA_MBOX is not set
-CONFIG_BCM2835_MBOX=y
-CONFIG_TI_MESSAGE_MANAGER=y
-CONFIG_HI3660_MBOX=m
-CONFIG_HI6220_MBOX=m
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_QCOM_APCS_IPC=m
-CONFIG_TEGRA_HSP_MBOX=y
-CONFIG_XGENE_SLIMPRO_MBOX=m
-CONFIG_BCM_PDC_MBOX=m
-CONFIG_BCM_FLEXRM_MBOX=m
-CONFIG_MTK_ADSP_MBOX=m
-CONFIG_MTK_CMDQ_MBOX=m
-CONFIG_ZYNQMP_IPI_MBOX=y
-CONFIG_SUN6I_MSGBOX=m
-CONFIG_SPRD_MBOX=m
-CONFIG_QCOM_IPCC=y
-CONFIG_IOMMU_IOVA=y
-CONFIG_IOASID=y
-CONFIG_IOMMU_API=y
-CONFIG_IOMMU_SUPPORT=y
-
-#
-# Generic IOMMU Pagetable Support
-#
-CONFIG_IOMMU_IO_PGTABLE=y
-CONFIG_IOMMU_IO_PGTABLE_LPAE=y
-# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
-CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
-# end of Generic IOMMU Pagetable Support
-
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
-CONFIG_OF_IOMMU=y
-CONFIG_IOMMU_DMA=y
-CONFIG_IOMMU_SVA_LIB=y
-CONFIG_ROCKCHIP_IOMMU=y
-CONFIG_SUN50I_IOMMU=y
-CONFIG_TEGRA_IOMMU_SMMU=y
-CONFIG_EXYNOS_IOMMU=y
-# CONFIG_EXYNOS_IOMMU_DEBUG is not set
-CONFIG_IPMMU_VMSA=y
-CONFIG_APPLE_DART=m
-CONFIG_ARM_SMMU=y
-# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
-# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set
-# CONFIG_ARM_SMMU_QCOM_DEBUG is not set
-CONFIG_ARM_SMMU_QCOM=y
-CONFIG_ARM_SMMU_V3=y
-CONFIG_ARM_SMMU_V3_SVA=y
-CONFIG_MTK_IOMMU=y
-CONFIG_QCOM_IOMMU=y
-CONFIG_VIRTIO_IOMMU=y
-CONFIG_SPRD_IOMMU=m
-
-#
-# Remoteproc drivers
-#
-CONFIG_REMOTEPROC=y
-CONFIG_REMOTEPROC_CDEV=y
-CONFIG_IMX_REMOTEPROC=m
-CONFIG_IMX_DSP_REMOTEPROC=m
-CONFIG_MTK_SCP=m
-CONFIG_PRU_REMOTEPROC=m
-CONFIG_QCOM_PIL_INFO=m
-CONFIG_QCOM_RPROC_COMMON=m
-CONFIG_QCOM_Q6V5_COMMON=m
-CONFIG_QCOM_Q6V5_ADSP=m
-CONFIG_QCOM_Q6V5_MSS=m
-CONFIG_QCOM_Q6V5_PAS=m
-CONFIG_QCOM_Q6V5_WCSS=m
-CONFIG_QCOM_SYSMON=m
-CONFIG_QCOM_WCNSS_PIL=m
-CONFIG_RCAR_REMOTEPROC=m
-CONFIG_TI_K3_DSP_REMOTEPROC=m
-CONFIG_TI_K3_R5_REMOTEPROC=m
-# end of Remoteproc drivers
-
-#
-# Rpmsg drivers
-#
-CONFIG_RPMSG=m
-CONFIG_RPMSG_CHAR=m
-CONFIG_RPMSG_CTRL=m
-CONFIG_RPMSG_NS=m
-CONFIG_RPMSG_MTK_SCP=m
-CONFIG_RPMSG_QCOM_GLINK=m
-CONFIG_RPMSG_QCOM_GLINK_RPM=m
-CONFIG_RPMSG_QCOM_GLINK_SMEM=m
-CONFIG_RPMSG_QCOM_SMD=m
-CONFIG_RPMSG_VIRTIO=m
-# end of Rpmsg drivers
-
-CONFIG_SOUNDWIRE=m
-
-#
-# SoundWire Devices
-#
-# CONFIG_SOUNDWIRE_INTEL is not set
-CONFIG_SOUNDWIRE_QCOM=m
-
-#
-# SOC (System On Chip) specific Drivers
-#
-CONFIG_OWL_PM_DOMAINS_HELPER=y
-CONFIG_OWL_PM_DOMAINS=y
-
-#
-# Amlogic SoC drivers
-#
-CONFIG_MESON_CANVAS=m
-CONFIG_MESON_CLK_MEASURE=y
-CONFIG_MESON_GX_SOCINFO=y
-CONFIG_MESON_GX_PM_DOMAINS=y
-CONFIG_MESON_EE_PM_DOMAINS=y
-CONFIG_MESON_SECURE_PM_DOMAINS=y
-# end of Amlogic SoC drivers
-
-#
-# Broadcom SoC drivers
-#
-CONFIG_BCM2835_POWER=y
-CONFIG_RASPBERRYPI_POWER=y
-CONFIG_SOC_BRCMSTB=y
-CONFIG_BCM_PMB=y
-CONFIG_BRCMSTB_PM=y
-# end of Broadcom SoC drivers
-
-#
-# NXP/Freescale QorIQ SoC drivers
-#
-CONFIG_FSL_DPAA=y
-# CONFIG_FSL_DPAA_CHECKING is not set
-# CONFIG_FSL_BMAN_TEST is not set
-# CONFIG_FSL_QMAN_TEST is not set
-CONFIG_QUICC_ENGINE=y
-CONFIG_UCC_FAST=y
-CONFIG_UCC=y
-CONFIG_QE_TDM=y
-CONFIG_FSL_GUTS=y
-CONFIG_FSL_MC_DPIO=m
-CONFIG_DPAA2_CONSOLE=m
-CONFIG_FSL_RCPM=y
-# end of NXP/Freescale QorIQ SoC drivers
-
-#
-# i.MX SoC drivers
-#
-CONFIG_IMX_GPCV2_PM_DOMAINS=y
-CONFIG_SOC_IMX8M=y
-CONFIG_SOC_IMX9=m
-# end of i.MX SoC drivers
-
-#
-# Enable LiteX SoC Builder specific drivers
-#
-# CONFIG_LITEX_SOC_CONTROLLER is not set
-# end of Enable LiteX SoC Builder specific drivers
-
-#
-# MediaTek SoC drivers
-#
-CONFIG_MTK_CMDQ=m
-CONFIG_MTK_DEVAPC=m
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_PMIC_WRAP=m
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_MMSYS=y
-CONFIG_MTK_SVS=m
-# end of MediaTek SoC drivers
-
-#
-# Qualcomm SoC drivers
-#
-CONFIG_QCOM_AOSS_QMP=m
-CONFIG_QCOM_COMMAND_DB=y
-CONFIG_QCOM_CPR=m
-CONFIG_QCOM_GENI_SE=y
-CONFIG_QCOM_GSBI=m
-CONFIG_QCOM_LLCC=m
-CONFIG_QCOM_KRYO_L2_ACCESSORS=y
-CONFIG_QCOM_MDT_LOADER=m
-CONFIG_QCOM_OCMEM=m
-CONFIG_QCOM_PDR_HELPERS=m
-CONFIG_QCOM_QMI_HELPERS=m
-CONFIG_QCOM_RMTFS_MEM=m
-CONFIG_QCOM_RPMH=y
-CONFIG_QCOM_RPMHPD=y
-CONFIG_QCOM_RPMPD=m
-CONFIG_QCOM_SMEM=m
-CONFIG_QCOM_SMD_RPM=m
-CONFIG_QCOM_SMEM_STATE=y
-CONFIG_QCOM_SMP2P=m
-CONFIG_QCOM_SMSM=m
-CONFIG_QCOM_SOCINFO=m
-# CONFIG_QCOM_SPM is not set
-# CONFIG_QCOM_STATS is not set
-CONFIG_QCOM_WCNSS_CTRL=m
-CONFIG_QCOM_APR=m
-CONFIG_QCOM_ICC_BWMON=m
-# end of Qualcomm SoC drivers
-
-CONFIG_SOC_RENESAS=y
-CONFIG_ARCH_RCAR_GEN3=y
-CONFIG_ARCH_R8A77995=y
-CONFIG_ARCH_R8A77990=y
-CONFIG_ARCH_R8A77950=y
-CONFIG_ARCH_R8A77951=y
-CONFIG_ARCH_R8A77965=y
-CONFIG_ARCH_R8A77960=y
-CONFIG_ARCH_R8A77961=y
-CONFIG_ARCH_R8A779F0=y
-CONFIG_ARCH_R8A779G0=y
-CONFIG_ARCH_R8A77980=y
-CONFIG_ARCH_R8A77970=y
-CONFIG_ARCH_R8A779A0=y
-CONFIG_ARCH_R8A774C0=y
-CONFIG_ARCH_R8A774E1=y
-CONFIG_ARCH_R8A774A1=y
-CONFIG_ARCH_R8A774B1=y
-CONFIG_ARCH_R9A07G043=y
-CONFIG_ARCH_R9A09G011=y
-CONFIG_ARCH_R9A07G044=y
-CONFIG_ARCH_R9A07G054=y
-CONFIG_RST_RCAR=y
-CONFIG_SYSC_RCAR=y
-CONFIG_SYSC_R8A77995=y
-CONFIG_SYSC_R8A77990=y
-CONFIG_SYSC_R8A7795=y
-CONFIG_SYSC_R8A77965=y
-CONFIG_SYSC_R8A77960=y
-CONFIG_SYSC_R8A77961=y
-CONFIG_SYSC_R8A77980=y
-CONFIG_SYSC_R8A77970=y
-CONFIG_SYSC_R8A779A0=y
-CONFIG_SYSC_R8A774C0=y
-CONFIG_SYSC_R8A774E1=y
-CONFIG_SYSC_R8A774A1=y
-CONFIG_SYSC_R8A774B1=y
-CONFIG_ROCKCHIP_GRF=y
-CONFIG_ROCKCHIP_IODOMAIN=y
-CONFIG_ROCKCHIP_PM_DOMAINS=y
-CONFIG_ROCKCHIP_DTPM=m
-CONFIG_SOC_SAMSUNG=y
-CONFIG_EXYNOS_CHIPID=y
-CONFIG_EXYNOS_PMU=y
-CONFIG_EXYNOS_PM_DOMAINS=y
-CONFIG_SUNXI_MBUS=y
-CONFIG_SUNXI_SRAM=y
-CONFIG_ARCH_TEGRA_132_SOC=y
-CONFIG_ARCH_TEGRA_210_SOC=y
-CONFIG_ARCH_TEGRA_186_SOC=y
-CONFIG_ARCH_TEGRA_194_SOC=y
-CONFIG_ARCH_TEGRA_234_SOC=y
-CONFIG_SOC_TEGRA_CBB=m
-CONFIG_SOC_TEGRA_FUSE=y
-CONFIG_SOC_TEGRA_FLOWCTRL=y
-CONFIG_SOC_TEGRA_PMC=y
-CONFIG_SOC_TEGRA_POWERGATE_BPMP=y
-CONFIG_SOC_TI=y
-CONFIG_TI_SCI_PM_DOMAINS=m
-CONFIG_TI_K3_RINGACC=y
-CONFIG_TI_K3_SOCINFO=y
-CONFIG_TI_PRUSS=m
-CONFIG_TI_SCI_INTA_MSI_DOMAIN=y
-
-#
-# Xilinx SoC drivers
-#
-CONFIG_ZYNQMP_POWER=y
-CONFIG_ZYNQMP_PM_DOMAINS=y
-CONFIG_XLNX_EVENT_MANAGER=y
-# end of Xilinx SoC drivers
-# end of SOC (System On Chip) specific Drivers
-
-CONFIG_PM_DEVFREQ=y
-
-#
-# DEVFREQ Governors
-#
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_PERFORMANCE=m
-CONFIG_DEVFREQ_GOV_POWERSAVE=m
-CONFIG_DEVFREQ_GOV_USERSPACE=m
-CONFIG_DEVFREQ_GOV_PASSIVE=y
-
-#
-# DEVFREQ Drivers
-#
-CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y
-CONFIG_ARM_IMX_BUS_DEVFREQ=m
-CONFIG_ARM_IMX8M_DDRC_DEVFREQ=m
-CONFIG_ARM_TEGRA_DEVFREQ=m
-CONFIG_ARM_RK3399_DMC_DEVFREQ=m
-CONFIG_PM_DEVFREQ_EVENT=y
-CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y
-CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU=y
-CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=m
-CONFIG_EXTCON=y
-
-#
-# Extcon Device Drivers
-#
-# CONFIG_EXTCON_ADC_JACK is not set
-CONFIG_EXTCON_FSA9480=m
-CONFIG_EXTCON_GPIO=m
-CONFIG_EXTCON_MAX3355=m
-CONFIG_EXTCON_PTN5150=m
-CONFIG_EXTCON_QCOM_SPMI_MISC=m
-# CONFIG_EXTCON_RT8973A is not set
-CONFIG_EXTCON_SM5502=m
-# CONFIG_EXTCON_USB_GPIO is not set
-CONFIG_EXTCON_USBC_CROS_EC=m
-CONFIG_EXTCON_USBC_TUSB320=m
-CONFIG_MEMORY=y
-CONFIG_ARM_PL172_MPMC=m
-CONFIG_BRCMSTB_DPFE=y
-CONFIG_BRCMSTB_MEMC=m
-CONFIG_OMAP_GPMC=m
-# CONFIG_OMAP_GPMC_DEBUG is not set
-CONFIG_FPGA_DFL_EMIF=m
-CONFIG_FSL_IFC=y
-CONFIG_MTK_SMI=y
-CONFIG_RENESAS_RPCIF=m
-CONFIG_TEGRA_MC=y
-CONFIG_TEGRA210_EMC_TABLE=y
-CONFIG_TEGRA210_EMC=m
-CONFIG_IIO=m
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_BUFFER_CB=m
-CONFIG_IIO_BUFFER_DMA=m
-CONFIG_IIO_BUFFER_DMAENGINE=m
-CONFIG_IIO_BUFFER_HW_CONSUMER=m
-CONFIG_IIO_KFIFO_BUF=m
-CONFIG_IIO_TRIGGERED_BUFFER=m
-CONFIG_IIO_CONFIGFS=m
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
-CONFIG_IIO_SW_DEVICE=m
-CONFIG_IIO_SW_TRIGGER=m
-CONFIG_IIO_TRIGGERED_EVENT=m
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16201=m
-CONFIG_ADIS16209=m
-CONFIG_ADXL313=m
-CONFIG_ADXL313_I2C=m
-CONFIG_ADXL313_SPI=m
-CONFIG_ADXL355=m
-CONFIG_ADXL355_I2C=m
-CONFIG_ADXL355_SPI=m
-CONFIG_ADXL367_SPI=m
-CONFIG_ADXL367_I2C=m
-CONFIG_ADXL372=m
-CONFIG_ADXL372_SPI=m
-CONFIG_ADXL372_I2C=m
-CONFIG_BMA220=m
-CONFIG_BMA400=m
-CONFIG_BMA400_I2C=m
-CONFIG_BMA400_SPI=m
-CONFIG_BMC150_ACCEL=m
-CONFIG_BMC150_ACCEL_I2C=m
-CONFIG_BMC150_ACCEL_SPI=m
-CONFIG_BMI088_ACCEL=m
-CONFIG_BMI088_ACCEL_SPI=m
-CONFIG_DA280=m
-CONFIG_DA311=m
-CONFIG_DMARD06=m
-CONFIG_DMARD09=m
-CONFIG_DMARD10=m
-CONFIG_FXLS8962AF=m
-CONFIG_FXLS8962AF_I2C=m
-CONFIG_FXLS8962AF_SPI=m
-CONFIG_HID_SENSOR_ACCEL_3D=m
-CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
-CONFIG_IIO_ST_ACCEL_3AXIS=m
-CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
-CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
-CONFIG_KXSD9=m
-CONFIG_KXSD9_SPI=m
-CONFIG_KXSD9_I2C=m
-CONFIG_KXCJK1013=m
-CONFIG_MC3230=m
-CONFIG_MMA7455=m
-CONFIG_MMA7455_I2C=m
-CONFIG_MMA7455_SPI=m
-CONFIG_MMA7660=m
-CONFIG_MMA8452=m
-CONFIG_MMA9551_CORE=m
-CONFIG_MMA9551=m
-CONFIG_MMA9553=m
-CONFIG_MSA311=m
-CONFIG_MXC4005=m
-CONFIG_MXC6255=m
-CONFIG_SCA3000=m
-CONFIG_SCA3300=m
-CONFIG_STK8312=m
-CONFIG_STK8BA50=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD_SIGMA_DELTA=m
-CONFIG_AD7091R5=m
-CONFIG_AD7124=m
-CONFIG_AD7192=m
-CONFIG_AD7266=m
-CONFIG_AD7291=m
-CONFIG_AD7292=m
-CONFIG_AD7298=m
-CONFIG_AD7476=m
-CONFIG_AD7606=m
-CONFIG_AD7606_IFACE_PARALLEL=m
-CONFIG_AD7606_IFACE_SPI=m
-CONFIG_AD7766=m
-CONFIG_AD7768_1=m
-CONFIG_AD7780=m
-CONFIG_AD7791=m
-CONFIG_AD7793=m
-CONFIG_AD7887=m
-CONFIG_AD7923=m
-CONFIG_AD7949=m
-CONFIG_AD799X=m
-CONFIG_AD9467=m
-CONFIG_ADI_AXI_ADC=m
-CONFIG_AXP20X_ADC=m
-CONFIG_AXP288_ADC=m
-CONFIG_BCM_IPROC_ADC=m
-CONFIG_BERLIN2_ADC=m
-CONFIG_CC10001_ADC=m
-CONFIG_CPCAP_ADC=m
-CONFIG_DLN2_ADC=m
-CONFIG_ENVELOPE_DETECTOR=m
-CONFIG_EXYNOS_ADC=m
-CONFIG_HI8435=m
-CONFIG_HX711=m
-CONFIG_INA2XX_ADC=m
-CONFIG_IMX7D_ADC=m
-CONFIG_IMX8QXP_ADC=m
-CONFIG_LTC2471=m
-CONFIG_LTC2485=m
-CONFIG_LTC2496=m
-CONFIG_LTC2497=m
-CONFIG_MAX1027=m
-CONFIG_MAX11100=m
-CONFIG_MAX1118=m
-CONFIG_MAX11205=m
-CONFIG_MAX1241=m
-CONFIG_MAX1363=m
-CONFIG_MAX9611=m
-CONFIG_MCP320X=m
-CONFIG_MCP3422=m
-CONFIG_MCP3911=m
-CONFIG_MEDIATEK_MT6360_ADC=m
-CONFIG_MEDIATEK_MT6577_AUXADC=m
-CONFIG_MESON_SARADC=m
-CONFIG_MP2629_ADC=m
-CONFIG_NAU7802=m
-CONFIG_QCOM_VADC_COMMON=m
-CONFIG_QCOM_SPMI_IADC=m
-CONFIG_QCOM_SPMI_VADC=m
-CONFIG_QCOM_SPMI_ADC5=m
-CONFIG_ROCKCHIP_SARADC=y
-CONFIG_RICHTEK_RTQ6056=m
-CONFIG_RZG2L_ADC=m
-CONFIG_SC27XX_ADC=m
-CONFIG_SD_ADC_MODULATOR=m
-CONFIG_SUN4I_GPADC=m
-CONFIG_TI_ADC081C=m
-CONFIG_TI_ADC0832=m
-CONFIG_TI_ADC084S021=m
-CONFIG_TI_ADC12138=m
-CONFIG_TI_ADC108S102=m
-CONFIG_TI_ADC128S052=m
-CONFIG_TI_ADC161S626=m
-CONFIG_TI_ADS1015=m
-CONFIG_TI_ADS7950=m
-CONFIG_TI_ADS8344=m
-CONFIG_TI_ADS8688=m
-CONFIG_TI_ADS124S08=m
-CONFIG_TI_ADS131E08=m
-CONFIG_TI_AM335X_ADC=m
-CONFIG_TI_TLC4541=m
-CONFIG_TI_TSC2046=m
-CONFIG_VF610_ADC=m
-CONFIG_VIPERBOARD_ADC=m
-CONFIG_XILINX_XADC=m
-CONFIG_XILINX_AMS=m
-# end of Analog to digital converters
-
-#
-# Analog Front Ends
-#
-CONFIG_IIO_RESCALE=m
-# end of Analog Front Ends
-
-#
-# Amplifiers
-#
-CONFIG_AD8366=m
-CONFIG_ADA4250=m
-CONFIG_HMC425=m
-# end of Amplifiers
-
-#
-# Capacitance to digital converters
-#
-CONFIG_AD7150=m
-# end of Capacitance to digital converters
-
-#
-# Chemical Sensors
-#
-CONFIG_ATLAS_PH_SENSOR=m
-CONFIG_ATLAS_EZO_SENSOR=m
-CONFIG_BME680=m
-CONFIG_BME680_I2C=m
-CONFIG_BME680_SPI=m
-CONFIG_CCS811=m
-CONFIG_IAQCORE=m
-CONFIG_PMS7003=m
-CONFIG_SCD30_CORE=m
-CONFIG_SCD30_I2C=m
-CONFIG_SCD30_SERIAL=m
-CONFIG_SCD4X=m
-CONFIG_SENSIRION_SGP30=m
-CONFIG_SENSIRION_SGP40=m
-CONFIG_SPS30=m
-CONFIG_SPS30_I2C=m
-CONFIG_SPS30_SERIAL=m
-CONFIG_SENSEAIR_SUNRISE_CO2=m
-CONFIG_VZ89X=m
-# end of Chemical Sensors
-
-CONFIG_IIO_CROS_EC_SENSORS_CORE=m
-CONFIG_IIO_CROS_EC_SENSORS=m
-CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m
-
-#
-# Hid Sensor IIO Common
-#
-CONFIG_HID_SENSOR_IIO_COMMON=m
-CONFIG_HID_SENSOR_IIO_TRIGGER=m
-# end of Hid Sensor IIO Common
-
-CONFIG_IIO_MS_SENSORS_I2C=m
-
-#
-# IIO SCMI Sensors
-#
-CONFIG_IIO_SCMI=m
-# end of IIO SCMI Sensors
-
-#
-# SSP Sensor Common
-#
-CONFIG_IIO_SSP_SENSORS_COMMONS=m
-CONFIG_IIO_SSP_SENSORHUB=m
-# end of SSP Sensor Common
-
-CONFIG_IIO_ST_SENSORS_I2C=m
-CONFIG_IIO_ST_SENSORS_SPI=m
-CONFIG_IIO_ST_SENSORS_CORE=m
-
-#
-# Digital to analog converters
-#
-CONFIG_AD5064=m
-CONFIG_AD5360=m
-CONFIG_AD5380=m
-CONFIG_AD5421=m
-CONFIG_AD5446=m
-CONFIG_AD5449=m
-CONFIG_AD5592R_BASE=m
-CONFIG_AD5592R=m
-CONFIG_AD5593R=m
-CONFIG_AD5504=m
-CONFIG_AD5624R_SPI=m
-CONFIG_LTC2688=m
-CONFIG_AD5686=m
-CONFIG_AD5686_SPI=m
-CONFIG_AD5696_I2C=m
-CONFIG_AD5755=m
-CONFIG_AD5758=m
-CONFIG_AD5761=m
-CONFIG_AD5764=m
-CONFIG_AD5766=m
-CONFIG_AD5770R=m
-CONFIG_AD5791=m
-CONFIG_AD7303=m
-CONFIG_AD8801=m
-CONFIG_DPOT_DAC=m
-CONFIG_DS4424=m
-CONFIG_LTC1660=m
-CONFIG_LTC2632=m
-CONFIG_M62332=m
-CONFIG_MAX517=m
-CONFIG_MAX5821=m
-CONFIG_MCP4725=m
-CONFIG_MCP4922=m
-CONFIG_TI_DAC082S085=m
-CONFIG_TI_DAC5571=m
-CONFIG_TI_DAC7311=m
-CONFIG_TI_DAC7612=m
-CONFIG_VF610_DAC=m
-# end of Digital to analog converters
-
-#
-# IIO dummy driver
-#
-# CONFIG_IIO_SIMPLE_DUMMY is not set
-# end of IIO dummy driver
-
-#
-# Frequency Synthesizers DDS/PLL
-#
-
-#
-# Clock Generator/Distribution
-#
-CONFIG_AD9523=m
-# end of Clock Generator/Distribution
-
-#
-# Phase-Locked Loop (PLL) frequency synthesizers
-#
-CONFIG_ADF4350=m
-CONFIG_ADF4371=m
-CONFIG_ADRF6780=m
-# end of Phase-Locked Loop (PLL) frequency synthesizers
-# end of Frequency Synthesizers DDS/PLL
-
-#
-# Digital gyroscope sensors
-#
-CONFIG_ADIS16080=m
-CONFIG_ADIS16130=m
-CONFIG_ADIS16136=m
-CONFIG_ADIS16260=m
-CONFIG_ADXRS290=m
-CONFIG_ADXRS450=m
-CONFIG_BMG160=m
-CONFIG_BMG160_I2C=m
-CONFIG_BMG160_SPI=m
-CONFIG_FXAS21002C=m
-CONFIG_FXAS21002C_I2C=m
-CONFIG_FXAS21002C_SPI=m
-CONFIG_HID_SENSOR_GYRO_3D=m
-CONFIG_MPU3050=m
-CONFIG_MPU3050_I2C=m
-CONFIG_IIO_ST_GYRO_3AXIS=m
-CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
-CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
-CONFIG_ITG3200=m
-# end of Digital gyroscope sensors
-
-#
-# Health Sensors
-#
-
-#
-# Heart Rate Monitors
-#
-CONFIG_AFE4403=m
-CONFIG_AFE4404=m
-CONFIG_MAX30100=m
-CONFIG_MAX30102=m
-# end of Heart Rate Monitors
-# end of Health Sensors
-
-#
-# Humidity sensors
-#
-CONFIG_AM2315=m
-CONFIG_DHT11=m
-CONFIG_HDC100X=m
-CONFIG_HDC2010=m
-CONFIG_HID_SENSOR_HUMIDITY=m
-CONFIG_HTS221=m
-CONFIG_HTS221_I2C=m
-CONFIG_HTS221_SPI=m
-CONFIG_HTU21=m
-CONFIG_SI7005=m
-CONFIG_SI7020=m
-# end of Humidity sensors
-
-#
-# Inertial measurement units
-#
-CONFIG_ADIS16400=m
-CONFIG_ADIS16460=m
-CONFIG_ADIS16475=m
-CONFIG_ADIS16480=m
-CONFIG_BMI160=m
-CONFIG_BMI160_I2C=m
-CONFIG_BMI160_SPI=m
-CONFIG_BOSCH_BNO055_SERIAL=m
-CONFIG_BOSCH_BNO055_I2C=m
-CONFIG_FXOS8700=m
-CONFIG_FXOS8700_I2C=m
-CONFIG_FXOS8700_SPI=m
-CONFIG_KMX61=m
-CONFIG_INV_ICM42600=m
-CONFIG_INV_ICM42600_I2C=m
-CONFIG_INV_ICM42600_SPI=m
-CONFIG_INV_MPU6050_IIO=m
-CONFIG_INV_MPU6050_I2C=m
-CONFIG_INV_MPU6050_SPI=m
-CONFIG_IIO_ST_LSM6DSX=m
-CONFIG_IIO_ST_LSM6DSX_I2C=m
-CONFIG_IIO_ST_LSM6DSX_SPI=m
-CONFIG_IIO_ST_LSM6DSX_I3C=m
-CONFIG_IIO_ST_LSM9DS0=m
-CONFIG_IIO_ST_LSM9DS0_I2C=m
-CONFIG_IIO_ST_LSM9DS0_SPI=m
-# end of Inertial measurement units
-
-CONFIG_IIO_ADIS_LIB=m
-CONFIG_IIO_ADIS_LIB_BUFFER=y
-
-#
-# Light sensors
-#
-CONFIG_ACPI_ALS=m
-CONFIG_ADJD_S311=m
-CONFIG_ADUX1020=m
-CONFIG_AL3010=m
-CONFIG_AL3320A=m
-CONFIG_APDS9300=m
-CONFIG_APDS9960=m
-CONFIG_AS73211=m
-CONFIG_BH1750=m
-CONFIG_BH1780=m
-CONFIG_CM32181=m
-CONFIG_CM3232=m
-CONFIG_CM3323=m
-CONFIG_CM3605=m
-CONFIG_CM36651=m
-CONFIG_IIO_CROS_EC_LIGHT_PROX=m
-CONFIG_GP2AP002=m
-CONFIG_GP2AP020A00F=m
-CONFIG_IQS621_ALS=m
-CONFIG_SENSORS_ISL29018=m
-CONFIG_SENSORS_ISL29028=m
-CONFIG_ISL29125=m
-CONFIG_HID_SENSOR_ALS=m
-CONFIG_HID_SENSOR_PROX=m
-CONFIG_JSA1212=m
-CONFIG_RPR0521=m
-CONFIG_SENSORS_LM3533=m
-CONFIG_LTR501=m
-CONFIG_LTRF216A=m
-CONFIG_LV0104CS=m
-CONFIG_MAX44000=m
-CONFIG_MAX44009=m
-CONFIG_NOA1305=m
-CONFIG_OPT3001=m
-CONFIG_PA12203001=m
-CONFIG_SI1133=m
-CONFIG_SI1145=m
-CONFIG_STK3310=m
-CONFIG_ST_UVIS25=m
-CONFIG_ST_UVIS25_I2C=m
-CONFIG_ST_UVIS25_SPI=m
-CONFIG_TCS3414=m
-CONFIG_TCS3472=m
-CONFIG_SENSORS_TSL2563=m
-CONFIG_TSL2583=m
-CONFIG_TSL2591=m
-CONFIG_TSL2772=m
-CONFIG_TSL4531=m
-CONFIG_US5182D=m
-CONFIG_VCNL4000=m
-CONFIG_VCNL4035=m
-CONFIG_VEML6030=m
-CONFIG_VEML6070=m
-CONFIG_VL6180=m
-CONFIG_ZOPT2201=m
-# end of Light sensors
-
-#
-# Magnetometer sensors
-#
-CONFIG_AK8974=m
-CONFIG_AK8975=m
-CONFIG_AK09911=m
-CONFIG_BMC150_MAGN=m
-CONFIG_BMC150_MAGN_I2C=m
-CONFIG_BMC150_MAGN_SPI=m
-CONFIG_MAG3110=m
-CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
-CONFIG_MMC35240=m
-CONFIG_IIO_ST_MAGN_3AXIS=m
-CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
-CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
-CONFIG_SENSORS_HMC5843=m
-CONFIG_SENSORS_HMC5843_I2C=m
-CONFIG_SENSORS_HMC5843_SPI=m
-CONFIG_SENSORS_RM3100=m
-CONFIG_SENSORS_RM3100_I2C=m
-CONFIG_SENSORS_RM3100_SPI=m
-CONFIG_YAMAHA_YAS530=m
-# end of Magnetometer sensors
-
-#
-# Multiplexers
-#
-CONFIG_IIO_MUX=m
-# end of Multiplexers
-
-#
-# Inclinometer sensors
-#
-CONFIG_HID_SENSOR_INCLINOMETER_3D=m
-CONFIG_HID_SENSOR_DEVICE_ROTATION=m
-# end of Inclinometer sensors
-
-#
-# Triggers - standalone
-#
-CONFIG_IIO_HRTIMER_TRIGGER=m
-CONFIG_IIO_INTERRUPT_TRIGGER=m
-CONFIG_IIO_TIGHTLOOP_TRIGGER=m
-CONFIG_IIO_SYSFS_TRIGGER=m
-# end of Triggers - standalone
-
-#
-# Linear and angular position sensors
-#
-CONFIG_IQS624_POS=m
-CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
-# end of Linear and angular position sensors
-
-#
-# Digital potentiometers
-#
-CONFIG_AD5110=m
-CONFIG_AD5272=m
-CONFIG_DS1803=m
-CONFIG_MAX5432=m
-CONFIG_MAX5481=m
-CONFIG_MAX5487=m
-CONFIG_MCP4018=m
-CONFIG_MCP4131=m
-CONFIG_MCP4531=m
-CONFIG_MCP41010=m
-CONFIG_TPL0102=m
-# end of Digital potentiometers
-
-#
-# Digital potentiostats
-#
-CONFIG_LMP91000=m
-# end of Digital potentiostats
-
-#
-# Pressure sensors
-#
-CONFIG_ABP060MG=m
-CONFIG_BMP280=m
-CONFIG_BMP280_I2C=m
-CONFIG_BMP280_SPI=m
-CONFIG_IIO_CROS_EC_BARO=m
-CONFIG_DLHL60D=m
-CONFIG_DPS310=m
-CONFIG_HID_SENSOR_PRESS=m
-CONFIG_HP03=m
-CONFIG_ICP10100=m
-CONFIG_MPL115=m
-CONFIG_MPL115_I2C=m
-CONFIG_MPL115_SPI=m
-CONFIG_MPL3115=m
-CONFIG_MS5611=m
-CONFIG_MS5611_I2C=m
-CONFIG_MS5611_SPI=m
-CONFIG_MS5637=m
-CONFIG_IIO_ST_PRESS=m
-CONFIG_IIO_ST_PRESS_I2C=m
-CONFIG_IIO_ST_PRESS_SPI=m
-CONFIG_T5403=m
-CONFIG_HP206C=m
-CONFIG_ZPA2326=m
-CONFIG_ZPA2326_I2C=m
-CONFIG_ZPA2326_SPI=m
-# end of Pressure sensors
-
-#
-# Lightning sensors
-#
-CONFIG_AS3935=m
-# end of Lightning sensors
-
-#
-# Proximity and distance sensors
-#
-CONFIG_CROS_EC_MKBP_PROXIMITY=m
-CONFIG_ISL29501=m
-CONFIG_LIDAR_LITE_V2=m
-CONFIG_MB1232=m
-CONFIG_PING=m
-CONFIG_RFD77402=m
-CONFIG_SRF04=m
-CONFIG_SX9310=m
-CONFIG_SX9360=m
-CONFIG_SX9324=m
-CONFIG_SX9500=m
-CONFIG_SRF08=m
-CONFIG_VCNL3020=m
-CONFIG_VL53L0X_I2C=m
-# end of Proximity and distance sensors
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S90=m
-CONFIG_AD2S1200=m
-# end of Resolver to digital converters
-
-#
-# Temperature sensors
-#
-CONFIG_IQS620AT_TEMP=m
-CONFIG_LTC2983=m
-CONFIG_MAXIM_THERMOCOUPLE=m
-CONFIG_HID_SENSOR_TEMP=m
-CONFIG_MLX90614=m
-CONFIG_MLX90632=m
-CONFIG_TMP006=m
-CONFIG_TMP007=m
-CONFIG_TMP117=m
-CONFIG_TSYS01=m
-CONFIG_TSYS02D=m
-CONFIG_MAX31856=m
-CONFIG_MAX31865=m
-# end of Temperature sensors
-
-CONFIG_NTB=y
-CONFIG_NTB_MSI=y
-CONFIG_NTB_IDT=m
-CONFIG_NTB_EPF=m
-CONFIG_NTB_SWITCHTEC=m
-# CONFIG_NTB_PINGPONG is not set
-# CONFIG_NTB_TOOL is not set
-CONFIG_NTB_PERF=m
-# CONFIG_NTB_MSI_TEST is not set
-CONFIG_NTB_TRANSPORT=m
-# CONFIG_VME_BUS is not set
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_PWM_DEBUG is not set
-CONFIG_PWM_ATMEL_HLCDC_PWM=m
-CONFIG_PWM_ATMEL_TCB=m
-CONFIG_PWM_BCM_IPROC=m
-CONFIG_PWM_BCM2835=m
-CONFIG_PWM_BERLIN=m
-CONFIG_PWM_BRCMSTB=m
-CONFIG_PWM_CROS_EC=m
-CONFIG_PWM_DWC=m
-# CONFIG_PWM_FSL_FTM is not set
-CONFIG_PWM_HIBVT=m
-# CONFIG_PWM_IMX1 is not set
-# CONFIG_PWM_IMX27 is not set
-CONFIG_PWM_IMX_TPM=m
-CONFIG_PWM_IQS620A=m
-CONFIG_PWM_KEEMBAY=m
-CONFIG_PWM_LP3943=m
-CONFIG_PWM_MESON=m
-CONFIG_PWM_MTK_DISP=m
-CONFIG_PWM_MEDIATEK=m
-# CONFIG_PWM_PCA9685 is not set
-CONFIG_PWM_RASPBERRYPI_POE=m
-CONFIG_PWM_RCAR=m
-CONFIG_PWM_RENESAS_TPU=m
-CONFIG_PWM_ROCKCHIP=y
-CONFIG_PWM_SAMSUNG=m
-CONFIG_PWM_SPRD=m
-CONFIG_PWM_SUN4I=m
-CONFIG_PWM_TEGRA=m
-CONFIG_PWM_TIECAP=m
-CONFIG_PWM_TIEHRPWM=m
-CONFIG_PWM_VISCONTI=m
-
-#
-# IRQ chip support
-#
-CONFIG_IRQCHIP=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_PM=y
-CONFIG_ARM_GIC_MAX_NR=1
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_GIC_V3_ITS_FSL_MC=y
-CONFIG_ALPINE_MSI=y
-CONFIG_AL_FIC=y
-CONFIG_BCM7038_L1_IRQ=y
-CONFIG_BCM7120_L2_IRQ=y
-CONFIG_BRCMSTB_L2_IRQ=y
-CONFIG_DW_APB_ICTL=y
-CONFIG_HISILICON_IRQ_MBIGEN=y
-CONFIG_MADERA_IRQ=m
-CONFIG_RENESAS_IRQC=y
-CONFIG_XILINX_INTC=y
-CONFIG_IMX_GPCV2=y
-CONFIG_MVEBU_GICP=y
-CONFIG_MVEBU_ICU=y
-CONFIG_MVEBU_ODMI=y
-CONFIG_MVEBU_PIC=y
-CONFIG_MVEBU_SEI=y
-CONFIG_LS_EXTIRQ=y
-CONFIG_LS_SCFG_MSI=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_QCOM_IRQ_COMBINER=y
-CONFIG_IRQ_UNIPHIER_AIDET=y
-CONFIG_MESON_IRQ_GPIO=y
-CONFIG_QCOM_PDC=y
-CONFIG_QCOM_MPM=m
-CONFIG_IMX_IRQSTEER=y
-CONFIG_IMX_MU_MSI=m
-CONFIG_IMX_INTMUX=y
-CONFIG_TI_SCI_INTR_IRQCHIP=y
-CONFIG_TI_SCI_INTA_IRQCHIP=y
-CONFIG_TI_PRUSS_INTC=m
-CONFIG_MST_IRQ=y
-CONFIG_APPLE_AIC=y
-# end of IRQ chip support
-
-CONFIG_IPACK_BUS=m
-CONFIG_BOARD_TPCI200=m
-CONFIG_SERIAL_IPOCTAL=m
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_A10SR=m
-CONFIG_RESET_BERLIN=y
-CONFIG_RESET_BRCMSTB=m
-CONFIG_RESET_BRCMSTB_RESCAL=y
-CONFIG_RESET_IMX7=y
-CONFIG_RESET_MCHP_SPARX5=y
-CONFIG_RESET_MESON=y
-CONFIG_RESET_MESON_AUDIO_ARB=m
-CONFIG_RESET_QCOM_AOSS=y
-CONFIG_RESET_QCOM_PDC=m
-CONFIG_RESET_RASPBERRYPI=y
-CONFIG_RESET_RZG2L_USBPHY_CTRL=m
-CONFIG_RESET_SCMI=m
-CONFIG_RESET_SIMPLE=y
-CONFIG_RESET_SUNXI=y
-CONFIG_RESET_TI_SCI=m
-CONFIG_RESET_TI_SYSCON=m
-CONFIG_RESET_UNIPHIER=m
-CONFIG_RESET_UNIPHIER_GLUE=m
-CONFIG_COMMON_RESET_HI3660=m
-CONFIG_COMMON_RESET_HI6220=m
-CONFIG_RESET_TEGRA_BPMP=y
-
-#
-# PHY Subsystem
-#
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PHY_MIPI_DPHY=y
-# CONFIG_PHY_XGENE is not set
-CONFIG_PHY_CAN_TRANSCEIVER=m
-CONFIG_PHY_SUN4I_USB=m
-CONFIG_PHY_SUN6I_MIPI_DPHY=m
-CONFIG_PHY_SUN9I_USB=m
-CONFIG_PHY_SUN50I_USB3=m
-CONFIG_PHY_MESON8B_USB2=m
-CONFIG_PHY_MESON_GXL_USB2=m
-CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=m
-CONFIG_PHY_MIXEL_LVDS_PHY=m
-CONFIG_PHY_MTK_PCIE=m
-CONFIG_PHY_MTK_DP=m
-CONFIG_PHY_MESON_G12A_USB2=m
-CONFIG_PHY_MESON_G12A_USB3_PCIE=m
-CONFIG_PHY_MESON_AXG_PCIE=m
-CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=m
-CONFIG_PHY_MESON_AXG_MIPI_DPHY=m
-
-#
-# PHY drivers for Broadcom platforms
-#
-CONFIG_PHY_BCM_SR_USB=m
-CONFIG_BCM_KONA_USB2_PHY=m
-CONFIG_PHY_BCM_NS_USB2=m
-CONFIG_PHY_BCM_NS_USB3=m
-CONFIG_PHY_NS2_PCIE=m
-CONFIG_PHY_NS2_USB_DRD=m
-CONFIG_PHY_BRCM_SATA=m
-CONFIG_PHY_BRCM_USB=m
-CONFIG_PHY_BCM_SR_PCIE=m
-# end of PHY drivers for Broadcom platforms
-
-CONFIG_PHY_CADENCE_TORRENT=m
-CONFIG_PHY_CADENCE_DPHY=m
-CONFIG_PHY_CADENCE_DPHY_RX=m
-CONFIG_PHY_CADENCE_SIERRA=m
-CONFIG_PHY_CADENCE_SALVO=m
-CONFIG_PHY_FSL_IMX8MQ_USB=m
-CONFIG_PHY_MIXEL_MIPI_DPHY=m
-CONFIG_PHY_HI6220_USB=m
-CONFIG_PHY_HI3660_USB=m
-CONFIG_PHY_HI3670_USB=m
-# CONFIG_PHY_HI3670_PCIE is not set
-CONFIG_PHY_HISTB_COMBPHY=m
-CONFIG_PHY_HISI_INNO_USB2=m
-CONFIG_PHY_BERLIN_SATA=m
-CONFIG_PHY_BERLIN_USB=m
-CONFIG_PHY_MVEBU_A3700_COMPHY=m
-CONFIG_PHY_MVEBU_A3700_UTMI=m
-CONFIG_PHY_MVEBU_A38X_COMPHY=m
-CONFIG_PHY_MVEBU_CP110_COMPHY=m
-CONFIG_PHY_MVEBU_CP110_UTMI=m
-CONFIG_PHY_PXA_28NM_HSIC=m
-CONFIG_PHY_PXA_28NM_USB2=m
-CONFIG_PHY_MTK_TPHY=m
-CONFIG_PHY_MTK_UFS=m
-CONFIG_PHY_MTK_XSPHY=m
-CONFIG_PHY_MTK_HDMI=m
-CONFIG_PHY_MTK_MIPI_DSI=m
-CONFIG_PHY_SPARX5_SERDES=m
-CONFIG_PHY_CPCAP_USB=m
-CONFIG_PHY_MAPPHONE_MDM6600=m
-CONFIG_PHY_OCELOT_SERDES=m
-CONFIG_PHY_QCOM_APQ8064_SATA=m
-# CONFIG_PHY_QCOM_IPQ4019_USB is not set
-CONFIG_PHY_QCOM_IPQ806X_SATA=m
-CONFIG_PHY_QCOM_PCIE2=m
-CONFIG_PHY_QCOM_QMP=m
-CONFIG_PHY_QCOM_QUSB2=m
-CONFIG_PHY_QCOM_USB_HS=m
-CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m
-CONFIG_PHY_QCOM_USB_HSIC=m
-CONFIG_PHY_QCOM_USB_HS_28NM=m
-CONFIG_PHY_QCOM_USB_SS=m
-CONFIG_PHY_QCOM_IPQ806X_USB=m
-CONFIG_PHY_RCAR_GEN2=m
-CONFIG_PHY_RCAR_GEN3_PCIE=m
-CONFIG_PHY_RCAR_GEN3_USB2=m
-CONFIG_PHY_RCAR_GEN3_USB3=m
-CONFIG_PHY_ROCKCHIP_DP=y
-CONFIG_PHY_ROCKCHIP_DPHY_RX0=m
-CONFIG_PHY_ROCKCHIP_EMMC=y
-CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
-CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m
-CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m
-CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
-CONFIG_PHY_ROCKCHIP_PCIE=m
-CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m
-CONFIG_PHY_ROCKCHIP_TYPEC=m
-CONFIG_PHY_ROCKCHIP_USB=m
-CONFIG_PHY_EXYNOS_DP_VIDEO=m
-CONFIG_PHY_EXYNOS_MIPI_VIDEO=m
-CONFIG_PHY_EXYNOS_PCIE=y
-CONFIG_PHY_SAMSUNG_UFS=m
-# CONFIG_PHY_SAMSUNG_USB2 is not set
-# CONFIG_PHY_EXYNOS5_USBDRD is not set
-CONFIG_PHY_UNIPHIER_USB2=m
-CONFIG_PHY_UNIPHIER_USB3=m
-CONFIG_PHY_UNIPHIER_PCIE=m
-CONFIG_PHY_UNIPHIER_AHCI=m
-CONFIG_PHY_TEGRA_XUSB=m
-CONFIG_PHY_TEGRA194_P2U=m
-CONFIG_PHY_AM654_SERDES=m
-CONFIG_PHY_J721E_WIZ=m
-CONFIG_OMAP_USB2=m
-# CONFIG_PHY_TUSB1210 is not set
-CONFIG_PHY_TI_GMII_SEL=m
-CONFIG_PHY_INTEL_KEEMBAY_EMMC=m
-CONFIG_PHY_INTEL_KEEMBAY_USB=m
-CONFIG_PHY_XILINX_ZYNQMP=m
-# end of PHY Subsystem
-
-# CONFIG_POWERCAP is not set
-# CONFIG_MCB is not set
-
-#
-# Performance monitor support
-#
-CONFIG_ARM_CCI_PMU=y
-CONFIG_ARM_CCI400_PMU=y
-CONFIG_ARM_CCI5xx_PMU=y
-CONFIG_ARM_CCN=y
-CONFIG_ARM_CMN=m
-CONFIG_ARM_PMU=y
-CONFIG_ARM_PMU_ACPI=y
-CONFIG_ARM_SMMU_V3_PMU=m
-CONFIG_ARM_DSU_PMU=m
-CONFIG_FSL_IMX8_DDR_PMU=m
-CONFIG_QCOM_L2_PMU=y
-CONFIG_QCOM_L3_PMU=y
-CONFIG_THUNDERX2_PMU=m
-CONFIG_XGENE_PMU=y
-CONFIG_ARM_SPE_PMU=m
-CONFIG_ARM_DMC620_PMU=m
-CONFIG_MARVELL_CN10K_TAD_PMU=m
-CONFIG_APPLE_M1_CPU_PMU=y
-CONFIG_ALIBABA_UNCORE_DRW_PMU=m
-CONFIG_HISI_PMU=y
-CONFIG_HISI_PCIE_PMU=m
-CONFIG_HNS3_PMU=m
-CONFIG_MARVELL_CN10K_DDR_PMU=m
-# end of Performance monitor support
-
-CONFIG_RAS=y
-CONFIG_USB4=m
-# CONFIG_USB4_DEBUGFS_WRITE is not set
-# CONFIG_USB4_DMA_TEST is not set
-
-#
-# Android
-#
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=m
-CONFIG_ANDROID_BINDERFS=y
-CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
-# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
-# end of Android
-
-CONFIG_LIBNVDIMM=m
-CONFIG_BLK_DEV_PMEM=m
-CONFIG_ND_BLK=m
-CONFIG_ND_CLAIM=y
-CONFIG_ND_BTT=m
-CONFIG_BTT=y
-CONFIG_ND_PFN=m
-CONFIG_NVDIMM_PFN=y
-CONFIG_NVDIMM_DAX=y
-CONFIG_OF_PMEM=m
-CONFIG_NVDIMM_KEYS=y
-CONFIG_DAX_DRIVER=y
-CONFIG_DAX=y
-CONFIG_DEV_DAX=m
-CONFIG_DEV_DAX_PMEM=m
-CONFIG_DEV_DAX_HMEM=m
-CONFIG_DEV_DAX_HMEM_DEVICES=y
-CONFIG_DEV_DAX_KMEM=m
-CONFIG_DEV_DAX_PMEM_COMPAT=m
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_IMX_IIM=m
-CONFIG_NVMEM_IMX_OCOTP=m
-CONFIG_NVMEM_IMX_OCOTP_SCU=m
-CONFIG_NVMEM_LAN9662_OTPC=m
-CONFIG_NVMEM_MESON_MX_EFUSE=m
-CONFIG_NVMEM_MICROCHIP_OTPC=m
-CONFIG_NVMEM_MTK_EFUSE=m
-CONFIG_NVMEM_QCOM_QFPROM=m
-CONFIG_NVMEM_RAVE_SP_EEPROM=m
-CONFIG_NVMEM_ROCKCHIP_EFUSE=m
-CONFIG_NVMEM_ROCKCHIP_OTP=m
-CONFIG_NVMEM_SC27XX_EFUSE=m
-CONFIG_MTK_EFUSE=m
-CONFIG_QCOM_QFPROM=m
-CONFIG_NVMEM_SPMI_SDAM=m
-CONFIG_ROCKCHIP_EFUSE=m
-CONFIG_ROCKCHIP_OTP=m
-CONFIG_NVMEM_BCM_OCOTP=m
-CONFIG_NVMEM_SUNXI_SID=m
-CONFIG_NVMEM_U_BOOT_ENV=m
-CONFIG_NVMEM_UNIPHIER_EFUSE=m
-CONFIG_UNIPHIER_EFUSE=m
-CONFIG_MESON_EFUSE=m
-CONFIG_MESON_MX_EFUSE=m
-CONFIG_NVMEM_SNVS_LPGPR=m
-CONFIG_SC27XX_EFUSE=m
-CONFIG_NVMEM_ZYNQMP=y
-CONFIG_SPRD_EFUSE=m
-CONFIG_NVMEM_RMEM=m
-CONFIG_NVMEM_LAYERSCAPE_SFP=m
-CONFIG_NVMEM_MESON_EFUSE=m
-CONFIG_NVMEM_SPRD_EFUSE=m
-CONFIG_NVMEM_APPLE_EFUSES=m
-
-#
-# HW tracing support
-#
-CONFIG_STM=y
-CONFIG_STM_PROTO_BASIC=m
-CONFIG_STM_PROTO_SYS_T=m
-# CONFIG_STM_DUMMY is not set
-CONFIG_STM_SOURCE_CONSOLE=y
-# CONFIG_STM_SOURCE_HEARTBEAT is not set
-CONFIG_STM_SOURCE_FTRACE=m
-# CONFIG_INTEL_TH is not set
-CONFIG_HISI_PTT=m
-# end of HW tracing support
-
-CONFIG_FPGA=m
-CONFIG_FPGA_MGR_SOCFPGA=m
-CONFIG_FPGA_MGR_SOCFPGA_A10=m
-CONFIG_ALTERA_PR_IP_CORE=m
-CONFIG_ALTERA_PR_IP_CORE_PLAT=m
-CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
-CONFIG_FPGA_MGR_ALTERA_CVP=m
-CONFIG_FPGA_MGR_STRATIX10_SOC=m
-CONFIG_FPGA_MGR_XILINX_SPI=m
-CONFIG_FPGA_MGR_ICE40_SPI=m
-CONFIG_FPGA_MGR_MACHXO2_SPI=m
-CONFIG_FPGA_BRIDGE=m
-CONFIG_SOCFPGA_FPGA_BRIDGE=m
-CONFIG_ALTERA_FREEZE_BRIDGE=m
-CONFIG_XILINX_PR_DECOUPLER=m
-CONFIG_FPGA_REGION=m
-CONFIG_OF_FPGA_REGION=m
-CONFIG_FPGA_DFL=m
-CONFIG_FPGA_DFL_FME=m
-CONFIG_FPGA_DFL_FME_MGR=m
-CONFIG_FPGA_DFL_FME_BRIDGE=m
-CONFIG_FPGA_DFL_FME_REGION=m
-CONFIG_FPGA_DFL_AFU=m
-CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
-CONFIG_FPGA_DFL_PCI=m
-CONFIG_FPGA_MGR_ZYNQMP_FPGA=m
-CONFIG_FPGA_MGR_VERSAL_FPGA=m
-CONFIG_FPGA_M10_BMC_SEC_UPDATE=m
-CONFIG_FPGA_MGR_MICROCHIP_SPI=m
-# CONFIG_FSI is not set
-CONFIG_TEE=m
-
-#
-# TEE drivers
-#
-CONFIG_OPTEE=m
-CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
-# end of TEE drivers
-
-CONFIG_MULTIPLEXER=m
-
-#
-# Multiplexer drivers
-#
-CONFIG_MUX_ADG792A=m
-CONFIG_MUX_ADGS1408=m
-CONFIG_MUX_GPIO=m
-CONFIG_MUX_MMIO=m
-# end of Multiplexer drivers
-
-CONFIG_PM_OPP=y
-# CONFIG_SIOX is not set
-CONFIG_SLIMBUS=m
-CONFIG_SLIM_QCOM_CTRL=m
-CONFIG_SLIM_QCOM_NGD_CTRL=m
-CONFIG_INTERCONNECT=y
-CONFIG_INTERCONNECT_IMX=m
-CONFIG_INTERCONNECT_IMX8MM=m
-CONFIG_INTERCONNECT_IMX8MN=m
-CONFIG_INTERCONNECT_IMX8MQ=m
-CONFIG_INTERCONNECT_IMX8MP=m
-CONFIG_INTERCONNECT_QCOM_SM6350=m
-CONFIG_INTERCONNECT_QCOM=y
-CONFIG_INTERCONNECT_QCOM_BCM_VOTER=m
-CONFIG_INTERCONNECT_QCOM_MSM8916=m
-CONFIG_INTERCONNECT_QCOM_MSM8939=m
-CONFIG_INTERCONNECT_QCOM_MSM8974=m
-CONFIG_INTERCONNECT_QCOM_MSM8996=m
-CONFIG_INTERCONNECT_QCOM_OSM_L3=m
-CONFIG_INTERCONNECT_QCOM_QCM2290=m
-CONFIG_INTERCONNECT_QCOM_QCS404=m
-CONFIG_INTERCONNECT_QCOM_RPMH_POSSIBLE=y
-CONFIG_INTERCONNECT_QCOM_RPMH=m
-CONFIG_INTERCONNECT_QCOM_SC7180=m
-CONFIG_INTERCONNECT_QCOM_SC7280=m
-CONFIG_INTERCONNECT_QCOM_SC8180X=m
-CONFIG_INTERCONNECT_QCOM_SC8280XP=m
-CONFIG_INTERCONNECT_QCOM_SDM660=m
-CONFIG_INTERCONNECT_QCOM_SDM845=m
-CONFIG_INTERCONNECT_QCOM_SDX55=m
-CONFIG_INTERCONNECT_QCOM_SDX65=m
-CONFIG_INTERCONNECT_QCOM_SM8150=m
-CONFIG_INTERCONNECT_QCOM_SM8250=m
-CONFIG_INTERCONNECT_QCOM_SM8350=m
-CONFIG_INTERCONNECT_QCOM_SM8450=m
-CONFIG_INTERCONNECT_QCOM_SMD_RPM=m
-CONFIG_INTERCONNECT_SAMSUNG=y
-CONFIG_INTERCONNECT_EXYNOS=m
-# CONFIG_COUNTER is not set
-# CONFIG_MOST is not set
-# end of Device Drivers
-
-#
-# File systems
-#
-CONFIG_DCACHE_WORD_ACCESS=y
-# CONFIG_VALIDATE_FS_PARSER is not set
-CONFIG_FS_IOMAP=y
-# CONFIG_EXT2_FS is not set
-# CONFIG_EXT3_FS is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_USE_FOR_EXT2=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD2=m
-# CONFIG_JBD2_DEBUG is not set
-CONFIG_FS_MBCACHE=m
-# CONFIG_REISERFS_FS is not set
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-# CONFIG_REISERFS_FS_XATTR is not set
-# CONFIG_REISERFS_FS_POSIX_ACL is not set
-# CONFIG_REISERFS_FS_SECURITY is not set
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_SECURITY=y
-# CONFIG_JFS_DEBUG is not set
-CONFIG_JFS_STATISTICS=y
-CONFIG_XFS_FS=m
-CONFIG_XFS_SUPPORT_V4=y
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-# CONFIG_XFS_RT is not set
-# CONFIG_XFS_ONLINE_SCRUB is not set
-# CONFIG_XFS_WARN is not set
-# CONFIG_XFS_DEBUG is not set
-CONFIG_GFS2_FS=m
-CONFIG_GFS2_FS_LOCKING_DLM=y
-CONFIG_OCFS2_FS=m
-CONFIG_OCFS2_FS_O2CB=m
-CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
-CONFIG_OCFS2_FS_STATS=y
-CONFIG_OCFS2_DEBUG_MASKLOG=y
-# CONFIG_OCFS2_DEBUG_FS is not set
-CONFIG_BTRFS_FS=m
-CONFIG_BTRFS_FS_POSIX_ACL=y
-# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
-# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
-# CONFIG_BTRFS_DEBUG is not set
-CONFIG_BTRFS_ASSERT=y
-# CONFIG_BTRFS_FS_REF_VERIFY is not set
-CONFIG_NILFS2_FS=m
-CONFIG_F2FS_FS=y
-CONFIG_F2FS_STAT_FS=y
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_FS_POSIX_ACL=y
-CONFIG_F2FS_FS_SECURITY=y
-# CONFIG_F2FS_CHECK_FS is not set
-CONFIG_F2FS_FAULT_INJECTION=y
-CONFIG_F2FS_FS_COMPRESSION=y
-CONFIG_F2FS_FS_LZO=y
-CONFIG_F2FS_FS_LZORLE=y
-CONFIG_F2FS_FS_LZ4=y
-CONFIG_F2FS_FS_LZ4HC=y
-CONFIG_F2FS_FS_ZSTD=y
-CONFIG_F2FS_IOSTAT=y
-# CONFIG_F2FS_UNFAIR_RWSEM is not set
-CONFIG_ZONEFS_FS=m
-CONFIG_FS_DAX=y
-CONFIG_FS_DAX_PMD=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_EXPORTFS=y
-CONFIG_EXPORTFS_BLOCK_OPS=y
-CONFIG_FILE_LOCKING=y
-CONFIG_FS_ENCRYPTION=y
-CONFIG_FS_ENCRYPTION_ALGS=m
-CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
-# CONFIG_FS_VERITY is not set
-# CONFIG_FS_VERITY_DEBUG is not set
-# CONFIG_FS_VERITY_BUILTIN_SIGNATURES is not set
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY_USER=y
-CONFIG_FANOTIFY=y
-CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-CONFIG_PRINT_QUOTA_WARNING=y
-# CONFIG_QUOTA_DEBUG is not set
-CONFIG_QUOTA_TREE=m
-# CONFIG_QFMT_V1 is not set
-CONFIG_QFMT_V2=m
-CONFIG_QUOTACTL=y
-# CONFIG_AUTOFS4_FS is not set
-CONFIG_AUTOFS_FS=y
-CONFIG_FUSE_FS=m
-CONFIG_CUSE=m
-CONFIG_VIRTIO_FS=m
-CONFIG_FUSE_DAX=y
-CONFIG_OVERLAY_FS=m
-# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set
-# CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set
-# CONFIG_OVERLAY_FS_INDEX is not set
-# CONFIG_OVERLAY_FS_XINO_AUTO is not set
-# CONFIG_OVERLAY_FS_METACOPY is not set
-
-#
-# Caches
-#
-CONFIG_NETFS_SUPPORT=m
-CONFIG_NETFS_STATS=y
-CONFIG_FSCACHE=m
-CONFIG_FSCACHE_STATS=y
-# CONFIG_FSCACHE_DEBUG is not set
-CONFIG_CACHEFILES=m
-# CONFIG_CACHEFILES_DEBUG is not set
-# end of Caches
-
-#
-# CD-ROM/DVD Filesystems
-#
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-# end of CD-ROM/DVD Filesystems
-
-#
-# DOS/FAT/EXFAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-CONFIG_FAT_DEFAULT_UTF8=y
-CONFIG_EXFAT_FS=m
-CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
-# CONFIG_NTFS_FS is not set
-CONFIG_NTFS3_FS=m
-# CONFIG_NTFS3_64BIT_CLUSTER is not set
-CONFIG_NTFS3_LZX_XPRESS=y
-CONFIG_NTFS3_FS_POSIX_ACL=y
-# end of DOS/FAT/EXFAT/NT Filesystems
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_CHILDREN=y
-CONFIG_KERNFS=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TMPFS_XATTR=y
-CONFIG_TMPFS_INODE64=y
-CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON=y
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_EFIVAR_FS=m
-# end of Pseudo filesystems
-
-CONFIG_MISC_FILESYSTEMS=y
-CONFIG_ORANGEFS_FS=m
-CONFIG_ADFS_FS=m
-CONFIG_ADFS_FS_RW=y
-CONFIG_AFFS_FS=m
-CONFIG_ECRYPT_FS=m
-CONFIG_ECRYPT_FS_MESSAGING=y
-# CONFIG_HFS_FS is not set
-CONFIG_HFSPLUS_FS=m
-# CONFIG_BEFS_FS is not set
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-CONFIG_UBIFS_FS=m
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UBIFS_FS_ZSTD=y
-CONFIG_UBIFS_ATIME_SUPPORT=y
-CONFIG_UBIFS_FS_XATTR=y
-CONFIG_UBIFS_FS_SECURITY=y
-CONFIG_UBIFS_FS_AUTHENTICATION=y
-CONFIG_CRAMFS=m
-CONFIG_CRAMFS_BLOCKDEV=y
-CONFIG_CRAMFS_MTD=y
-CONFIG_SQUASHFS=m
-# CONFIG_SQUASHFS_FILE_CACHE is not set
-CONFIG_SQUASHFS_FILE_DIRECT=y
-# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
-CONFIG_SQUASHFS_DECOMP_MULTI=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_XATTR=y
-CONFIG_SQUASHFS_ZLIB=y
-CONFIG_SQUASHFS_LZ4=y
-CONFIG_SQUASHFS_LZO=y
-CONFIG_SQUASHFS_XZ=y
-CONFIG_SQUASHFS_ZSTD=y
-# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
-# CONFIG_SQUASHFS_EMBEDDED is not set
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_OMFS_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_QNX6FS_FS=m
-# CONFIG_QNX6FS_DEBUG is not set
-CONFIG_ROMFS_FS=m
-# CONFIG_ROMFS_BACKED_BY_BLOCK is not set
-# CONFIG_ROMFS_BACKED_BY_MTD is not set
-CONFIG_ROMFS_BACKED_BY_BOTH=y
-CONFIG_ROMFS_ON_BLOCK=y
-CONFIG_ROMFS_ON_MTD=y
-CONFIG_PSTORE=m
-CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
-CONFIG_PSTORE_DEFLATE_COMPRESS=m
-CONFIG_PSTORE_LZO_COMPRESS=m
-CONFIG_PSTORE_LZ4_COMPRESS=m
-CONFIG_PSTORE_LZ4HC_COMPRESS=m
-CONFIG_PSTORE_842_COMPRESS=y
-CONFIG_PSTORE_ZSTD_COMPRESS=y
-CONFIG_PSTORE_COMPRESS=y
-# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
-CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="zstd"
-# CONFIG_PSTORE_CONSOLE is not set
-# CONFIG_PSTORE_PMSG is not set
-# CONFIG_PSTORE_FTRACE is not set
-CONFIG_PSTORE_RAM=m
-# CONFIG_PSTORE_BLK is not set
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-CONFIG_UFS_FS_WRITE=y
-# CONFIG_UFS_DEBUG is not set
-CONFIG_EROFS_FS=m
-# CONFIG_EROFS_FS_DEBUG is not set
-CONFIG_EROFS_FS_XATTR=y
-CONFIG_EROFS_FS_POSIX_ACL=y
-CONFIG_EROFS_FS_SECURITY=y
-CONFIG_EROFS_FS_ZIP=y
-CONFIG_EROFS_FS_ZIP_LZMA=y
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V2=m
-CONFIG_NFS_V3=m
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=m
-CONFIG_NFS_SWAP=y
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_V4_2=y
-CONFIG_PNFS_FILE_LAYOUT=m
-CONFIG_PNFS_BLOCK=m
-CONFIG_PNFS_FLEXFILE_LAYOUT=m
-CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
-# CONFIG_NFS_V4_1_MIGRATION is not set
-CONFIG_NFS_V4_SECURITY_LABEL=y
-CONFIG_NFS_FSCACHE=y
-# CONFIG_NFS_USE_LEGACY_DNS is not set
-CONFIG_NFS_USE_KERNEL_DNS=y
-# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set
-# CONFIG_NFS_V4_2_READ_PLUS is not set
-CONFIG_NFSD=m
-CONFIG_NFSD_V2_ACL=y
-CONFIG_NFSD_V3=y
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_PNFS=y
-CONFIG_NFSD_BLOCKLAYOUT=y
-CONFIG_NFSD_SCSILAYOUT=y
-CONFIG_NFSD_FLEXFILELAYOUT=y
-CONFIG_NFSD_V4_2_INTER_SSC=y
-CONFIG_NFSD_V4_SECURITY_LABEL=y
-CONFIG_GRACE_PERIOD=m
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_ACL_SUPPORT=m
-CONFIG_NFS_COMMON=y
-CONFIG_NFS_V4_2_SSC_HELPER=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_SUNRPC_BACKCHANNEL=y
-CONFIG_SUNRPC_SWAP=y
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
-# CONFIG_SUNRPC_DEBUG is not set
-CONFIG_SUNRPC_XPRT_RDMA=m
-CONFIG_CEPH_FS=m
-CONFIG_CEPH_FSCACHE=y
-CONFIG_CEPH_FS_POSIX_ACL=y
-CONFIG_CEPH_FS_SECURITY_LABEL=y
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS2=y
-CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
-CONFIG_CIFS_UPCALL=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-# CONFIG_CIFS_DEBUG is not set
-CONFIG_CIFS_DFS_UPCALL=y
-CONFIG_CIFS_SWN_UPCALL=y
-# CONFIG_CIFS_SMB_DIRECT is not set
-CONFIG_CIFS_FSCACHE=y
-CONFIG_SMB_SERVER=m
-# CONFIG_SMB_SERVER_SMBDIRECT is not set
-CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
-CONFIG_SMB_SERVER_KERBEROS5=y
-CONFIG_SMBFS_COMMON=m
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-# CONFIG_AFS_DEBUG is not set
-CONFIG_AFS_FSCACHE=y
-# CONFIG_AFS_DEBUG_CURSOR is not set
-CONFIG_9P_FS=m
-CONFIG_9P_FSCACHE=y
-CONFIG_9P_FS_POSIX_ACL=y
-CONFIG_9P_FS_SECURITY=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_MAC_ROMAN=m
-CONFIG_NLS_MAC_CELTIC=m
-CONFIG_NLS_MAC_CENTEURO=m
-CONFIG_NLS_MAC_CROATIAN=m
-CONFIG_NLS_MAC_CYRILLIC=m
-CONFIG_NLS_MAC_GAELIC=m
-CONFIG_NLS_MAC_GREEK=m
-CONFIG_NLS_MAC_ICELAND=m
-CONFIG_NLS_MAC_INUIT=m
-CONFIG_NLS_MAC_ROMANIAN=m
-CONFIG_NLS_MAC_TURKISH=m
-CONFIG_NLS_UTF8=m
-CONFIG_DLM=m
-# CONFIG_DLM_DEPRECATED_API is not set
-# CONFIG_DLM_DEBUG is not set
-CONFIG_UNICODE=y
-# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set
-CONFIG_IO_WQ=y
-# end of File systems
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-# CONFIG_KEYS_REQUEST_CACHE is not set
-CONFIG_PERSISTENT_KEYRINGS=y
-CONFIG_TRUSTED_KEYS=m
-CONFIG_ENCRYPTED_KEYS=y
-CONFIG_USER_DECRYPTED_DATA=y
-CONFIG_KEY_DH_OPERATIONS=y
-# CONFIG_KEY_NOTIFICATIONS is not set
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-CONFIG_SECURITY=y
-CONFIG_SECURITYFS=y
-CONFIG_SECURITY_NETWORK=y
-CONFIG_SECURITY_INFINIBAND=y
-CONFIG_SECURITY_NETWORK_XFRM=y
-CONFIG_SECURITY_PATH=y
-CONFIG_LSM_MMAP_MIN_ADDR=0
-CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
-CONFIG_HARDENED_USERCOPY=y
-# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
-CONFIG_FORTIFY_SOURCE=y
-# CONFIG_STATIC_USERMODEHELPER is not set
-# CONFIG_SECURITY_SELINUX is not set
-# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set
-# CONFIG_SECURITY_SELINUX_DISABLE is not set
-# CONFIG_SECURITY_SELINUX_DEVELOP is not set
-CONFIG_SECURITY_SELINUX_AVC_STATS=y
-CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
-CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
-CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
-# CONFIG_SECURITY_SMACK is not set
-CONFIG_SECURITY_TOMOYO=y
-CONFIG_SECURITY_TOMOYO_MAX_ACCEPT_ENTRY=2048
-CONFIG_SECURITY_TOMOYO_MAX_AUDIT_LOG=1024
-# CONFIG_SECURITY_TOMOYO_OMIT_USERSPACE_LOADER is not set
-CONFIG_SECURITY_TOMOYO_POLICY_LOADER="/sbin/tomoyo-init"
-CONFIG_SECURITY_TOMOYO_ACTIVATION_TRIGGER="/sbin/init"
-# CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING is not set
-CONFIG_SECURITY_APPARMOR=y
-CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y
-CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y
-CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y
-CONFIG_SECURITY_APPARMOR_HASH=y
-CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
-# CONFIG_SECURITY_APPARMOR_DEBUG is not set
-# CONFIG_SECURITY_LOADPIN is not set
-CONFIG_SECURITY_YAMA=y
-# CONFIG_SECURITY_SAFESETID is not set
-CONFIG_SECURITY_LOCKDOWN_LSM=y
-# CONFIG_SECURITY_LOCKDOWN_LSM_EARLY is not set
-CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y
-# CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set
-# CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set
-CONFIG_SECURITY_LANDLOCK=y
-CONFIG_INTEGRITY=y
-CONFIG_INTEGRITY_SIGNATURE=y
-CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y
-CONFIG_INTEGRITY_TRUSTED_KEYRING=y
-CONFIG_INTEGRITY_PLATFORM_KEYRING=y
-CONFIG_LOAD_UEFI_KEYS=y
-CONFIG_INTEGRITY_AUDIT=y
-CONFIG_IMA=y
-CONFIG_IMA_KEXEC=y
-CONFIG_IMA_MEASURE_PCR_IDX=10
-CONFIG_IMA_LSM_RULES=y
-# CONFIG_IMA_TEMPLATE is not set
-CONFIG_IMA_NG_TEMPLATE=y
-# CONFIG_IMA_SIG_TEMPLATE is not set
-CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng"
-# CONFIG_IMA_DEFAULT_HASH_SHA1 is not set
-CONFIG_IMA_DEFAULT_HASH_SHA256=y
-# CONFIG_IMA_DEFAULT_HASH_SHA512 is not set
-CONFIG_IMA_DEFAULT_HASH="sha256"
-# CONFIG_IMA_WRITE_POLICY is not set
-CONFIG_IMA_READ_POLICY=y
-CONFIG_IMA_APPRAISE=y
-# CONFIG_IMA_ARCH_POLICY is not set
-# CONFIG_IMA_APPRAISE_BUILD_POLICY is not set
-CONFIG_IMA_APPRAISE_BOOTPARAM=y
-CONFIG_IMA_APPRAISE_MODSIG=y
-CONFIG_IMA_TRUSTED_KEYRING=y
-# CONFIG_IMA_BLACKLIST_KEYRING is not set
-# CONFIG_IMA_LOAD_X509 is not set
-CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y
-CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y
-# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
-# CONFIG_IMA_DISABLE_HTABLE is not set
-CONFIG_EVM=y
-CONFIG_EVM_ATTR_FSUUID=y
-CONFIG_EVM_ADD_XATTRS=y
-# CONFIG_EVM_LOAD_X509 is not set
-# CONFIG_DEFAULT_SECURITY_SELINUX is not set
-# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
-CONFIG_DEFAULT_SECURITY_APPARMOR=y
-# CONFIG_DEFAULT_SECURITY_DAC is not set
-CONFIG_LSM="yama,loadpin,safesetid,integrity,bpf"
-
-#
-# Kernel hardening options
-#
-
-#
-# Memory initialization
-#
-CONFIG_INIT_STACK_NONE=y
-# CONFIG_INIT_STACK_ALL_PATTERN is not set
-# CONFIG_INIT_STACK_ALL_ZERO is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
-# CONFIG_GCC_PLUGIN_STACKLEAK is not set
-# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
-# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
-CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
-# CONFIG_ZERO_CALL_USED_REGS is not set
-# end of Memory initialization
-# end of Kernel hardening options
-# end of Security options
-
-CONFIG_XOR_BLOCKS=m
-CONFIG_ASYNC_CORE=m
-CONFIG_ASYNC_MEMCPY=m
-CONFIG_ASYNC_XOR=m
-CONFIG_ASYNC_PQ=m
-CONFIG_ASYNC_RAID6_RECOV=m
-CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA=y
-CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA=y
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_FIPS=y
-CONFIG_CRYPTO_FIPS_NAME="Linux Kernel Cryptographic API"
-# CONFIG_CRYPTO_FIPS_CUSTOM_VERSION is not set
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_SKCIPHER=y
-CONFIG_CRYPTO_SKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_AKCIPHER2=y
-CONFIG_CRYPTO_AKCIPHER=y
-CONFIG_CRYPTO_KPP2=y
-CONFIG_CRYPTO_KPP=y
-CONFIG_CRYPTO_ACOMP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_USER=m
-# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
-# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_PCRYPT=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_ENGINE=m
-
-#
-# Public-key cryptography
-#
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_DH=y
-CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=m
-CONFIG_CRYPTO_ECDSA=y
-CONFIG_CRYPTO_ECRDSA=m
-CONFIG_CRYPTO_SM2=m
-CONFIG_CRYPTO_CURVE25519=m
-
-#
-# Authenticated Encryption with Associated Data
-#
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_GCM=m
-CONFIG_CRYPTO_CHACHA20POLY1305=m
-CONFIG_CRYPTO_AEGIS128=m
-CONFIG_CRYPTO_AEGIS128_SIMD=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_ECHAINIV=m
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CFB=m
-CONFIG_CRYPTO_CTR=y
-CONFIG_CRYPTO_CTS=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_OFB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_KEYWRAP=m
-CONFIG_CRYPTO_NHPOLY1305=y
-CONFIG_CRYPTO_ADIANTUM=m
-CONFIG_CRYPTO_HCTR2=m
-CONFIG_CRYPTO_ARIA=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
-CONFIG_CRYPTO_DEV_QAT_C3XXX=m
-CONFIG_CRYPTO_DEV_QAT_C62X=m
-CONFIG_CRYPTO_DEV_QAT_4XXX=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
-CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
-CONFIG_CRYPTO_DEV_QAT_C62XVF=m
-CONFIG_CRYPTO_ESSIV=m
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_CMAC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_XXHASH=m
-CONFIG_CRYPTO_BLAKE2B=m
-CONFIG_CRYPTO_BLAKE2S=m
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_GHASH=m
-CONFIG_CRYPTO_POLY1305=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SHA3=m
-CONFIG_CRYPTO_SM3=m
-CONFIG_CRYPTO_STREEBOG=m
-CONFIG_CRYPTO_WP512=m
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_AES_TI=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_BLOWFISH_COMMON=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST_COMMON=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_CHACHA20=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_SM4=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_842=y
-CONFIG_CRYPTO_LZ4=m
-CONFIG_CRYPTO_LZ4HC=m
-CONFIG_CRYPTO_ZSTD=y
-
-#
-# Random Number Generation
-#
-CONFIG_CRYPTO_ANSI_CPRNG=m
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_HASH=y
-CONFIG_CRYPTO_DRBG_CTR=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_USER_API=m
-CONFIG_CRYPTO_USER_API_HASH=y
-CONFIG_CRYPTO_USER_API_SKCIPHER=m
-CONFIG_CRYPTO_USER_API_RNG=m
-# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
-CONFIG_CRYPTO_USER_API_AEAD=m
-# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set
-# CONFIG_CRYPTO_STATS is not set
-CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
-CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_SM4=m
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_DEV_ALLWINNER=y
-CONFIG_CRYPTO_DEV_SUN4I_SS=m
-CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
-# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set
-CONFIG_CRYPTO_DEV_SUN8I_CE=m
-# CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set
-CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
-CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
-CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
-CONFIG_CRYPTO_DEV_SUN8I_SS=m
-# CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG is not set
-CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y
-CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=m
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=m
-CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=m
-CONFIG_CRYPTO_DEV_FSL_CAAM=m
-# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
-CONFIG_CRYPTO_DEV_FSL_CAAM_JR=m
-CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
-CONFIG_CRYPTO_DEV_FSL_CAAM_INTC=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD=255
-CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD=2048
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
-CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API=y
-CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m
-CONFIG_CRYPTO_DEV_SAHARA=m
-CONFIG_CRYPTO_DEV_EXYNOS_RNG=m
-CONFIG_CRYPTO_DEV_S5P=m
-CONFIG_CRYPTO_DEV_ATMEL_I2C=m
-CONFIG_CRYPTO_DEV_ATMEL_ECC=m
-CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
-CONFIG_CRYPTO_DEV_CCP=y
-CONFIG_CRYPTO_DEV_CCP_DD=m
-CONFIG_CRYPTO_DEV_SP_CCP=y
-CONFIG_CRYPTO_DEV_CCP_CRYPTO=m
-# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set
-CONFIG_CRYPTO_DEV_MXS_DCP=m
-CONFIG_CRYPTO_DEV_CPT=m
-CONFIG_CAVIUM_CPT=m
-CONFIG_CRYPTO_DEV_NITROX=m
-CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m
-CONFIG_CRYPTO_DEV_MARVELL=m
-CONFIG_CRYPTO_DEV_MARVELL_CESA=m
-CONFIG_CRYPTO_DEV_OCTEONTX_CPT=m
-CONFIG_CRYPTO_DEV_OCTEONTX2_CPT=m
-CONFIG_CRYPTO_DEV_CAVIUM_ZIP=m
-CONFIG_CRYPTO_DEV_QCE=m
-CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
-CONFIG_CRYPTO_DEV_QCE_SHA=y
-CONFIG_CRYPTO_DEV_QCE_AEAD=y
-CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
-CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
-CONFIG_CRYPTO_DEV_QCOM_RNG=m
-CONFIG_CRYPTO_DEV_ROCKCHIP=y
-CONFIG_CRYPTO_DEV_ZYNQMP_AES=m
-CONFIG_CRYPTO_DEV_ZYNQMP_SHA3=m
-CONFIG_CRYPTO_DEV_CHELSIO=m
-CONFIG_CRYPTO_DEV_VIRTIO=m
-CONFIG_CRYPTO_DEV_BCM_SPU=m
-CONFIG_CRYPTO_DEV_SAFEXCEL=m
-CONFIG_CRYPTO_DEV_CCREE=m
-CONFIG_CRYPTO_DEV_HISI_SEC=m
-CONFIG_CRYPTO_DEV_HISI_SEC2=m
-CONFIG_CRYPTO_DEV_HISI_QM=m
-CONFIG_CRYPTO_DEV_HISI_ZIP=m
-CONFIG_CRYPTO_DEV_HISI_HPRE=m
-CONFIG_CRYPTO_DEV_HISI_TRNG=m
-CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
-CONFIG_CRYPTO_DEV_ASPEED=m
-# CONFIG_CRYPTO_DEV_ASPEED_DEBUG is not set
-CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH=y
-CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO=y
-# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set
-CONFIG_CRYPTO_DEV_SA2UL=m
-CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4=m
-CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_ECB=y
-CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_CTS=y
-# CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC is not set
-CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU=m
-# CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224 is not set
-CONFIG_ASYMMETRIC_KEY_TYPE=y
-CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
-CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE=m
-CONFIG_X509_CERTIFICATE_PARSER=y
-CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
-CONFIG_TPM_KEY_PARSER=m
-CONFIG_PKCS7_MESSAGE_PARSER=y
-# CONFIG_PKCS7_TEST_KEY is not set
-CONFIG_SIGNED_PE_FILE_VERIFICATION=y
-
-#
-# Certificates for signature checking
-#
-CONFIG_MODULE_SIG_KEY="certs/signing_key.pem"
-CONFIG_MODULE_SIG_KEY_TYPE_RSA=y
-# CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set
-CONFIG_SYSTEM_TRUSTED_KEYRING=y
-CONFIG_SYSTEM_TRUSTED_KEYS=""
-# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
-# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
-CONFIG_SYSTEM_BLACKLIST_KEYRING=y
-CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
-CONFIG_SYSTEM_REVOCATION_LIST=y
-CONFIG_SYSTEM_REVOCATION_KEYS=""
-# end of Certificates for signature checking
-
-CONFIG_BINARY_PRINTF=y
-
-#
-# Library routines
-#
-CONFIG_RAID6_PQ=m
-# CONFIG_RAID6_PQ_BENCHMARK is not set
-CONFIG_LINEAR_RANGES=y
-CONFIG_PACKING=y
-CONFIG_BITREVERSE=y
-CONFIG_HAVE_ARCH_BITREVERSE=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_CORDIC=m
-# CONFIG_PRIME_NUMBERS is not set
-CONFIG_RATIONAL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_STMP_DEVICE=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
-CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
-CONFIG_INDIRECT_PIO=y
-# CONFIG_TRACE_MMIO_ACCESS is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC64_ROCKSOFT=m
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC32_SELFTEST is not set
-CONFIG_CRC32_SLICEBY8=y
-# CONFIG_CRC32_SLICEBY4 is not set
-# CONFIG_CRC32_SARWATE is not set
-# CONFIG_CRC32_BIT is not set
-CONFIG_CRC64=m
-CONFIG_CRC4=m
-CONFIG_CRC7=m
-CONFIG_LIBCRC32C=m
-CONFIG_CRC8=y
-CONFIG_XXHASH=y
-# CONFIG_RANDOM32_SELFTEST is not set
-CONFIG_842_COMPRESS=y
-CONFIG_842_DECOMPRESS=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_LZ4_COMPRESS=m
-CONFIG_LZ4HC_COMPRESS=m
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
-CONFIG_XZ_DEC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_MICROLZMA=y
-CONFIG_XZ_DEC_BCJ=y
-# CONFIG_XZ_DEC_TEST is not set
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_LZ4=y
-CONFIG_DECOMPRESS_ZSTD=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_REED_SOLOMON=m
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_DEC16=y
-CONFIG_BCH=m
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_BTREE=y
-CONFIG_INTERVAL_TREE=y
-CONFIG_XARRAY_MULTI=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAS_DMA=y
-CONFIG_DMA_OPS=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_DMA_DECLARE_COHERENT=y
-CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
-CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
-CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
-CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
-CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
-CONFIG_SWIOTLB=y
-# CONFIG_DMA_RESTRICTED_POOL is not set
-CONFIG_DMA_NONCOHERENT_MMAP=y
-CONFIG_DMA_COHERENT_POOL=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_PERNUMA_CMA=y
-
-#
-# Default contiguous memory area size:
-#
-CONFIG_CMA_SIZE_MBYTES=0
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_ALIGNMENT=8
-# CONFIG_DMA_API_DEBUG is not set
-# CONFIG_DMA_MAP_BENCHMARK is not set
-CONFIG_SGL_ALLOC=y
-CONFIG_CHECK_SIGNATURE=y
-CONFIG_CPU_RMAP=y
-CONFIG_DQL=y
-CONFIG_GLOB=y
-# CONFIG_GLOB_SELFTEST is not set
-CONFIG_NLATTR=y
-CONFIG_LRU_CACHE=m
-CONFIG_CLZ_TAB=y
-CONFIG_IRQ_POLL=y
-CONFIG_MPILIB=y
-CONFIG_SIGNATURE=y
-CONFIG_DIMLIB=y
-CONFIG_LIBFDT=y
-CONFIG_OID_REGISTRY=y
-CONFIG_UCS2_STRING=y
-CONFIG_HAVE_GENERIC_VDSO=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_VDSO_TIME_NS=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_6x10 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-CONFIG_FONT_TER16x32=y
-CONFIG_FONT_6x8=y
-CONFIG_SG_SPLIT=y
-CONFIG_SG_POOL=y
-CONFIG_ARCH_HAS_PMEM_API=y
-CONFIG_MEMREGION=y
-CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_STACKDEPOT=y
-CONFIG_STACK_HASH_ORDER=20
-CONFIG_SBITMAP=y
-CONFIG_PARMAN=m
-CONFIG_OBJAGG=m
-# end of Library routines
-
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_PLDMFW=y
-CONFIG_ASN1_ENCODER=m
-
-#
-# Kernel hacking
-#
-
-#
-# printk and dmesg options
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_PRINTK_CALLER=y
-CONFIG_STACKTRACE_BUILD_ID=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
-CONFIG_CONSOLE_LOGLEVEL_QUIET=4
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_DYNAMIC_DEBUG_CORE is not set
-CONFIG_SYMBOLIC_ERRNAME=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# end of printk and dmesg options
-
-#
-# Compile-time checks and compiler options
-#
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_INFO_REDUCED is not set
-# CONFIG_DEBUG_INFO_COMPRESSED is not set
-# CONFIG_DEBUG_INFO_SPLIT is not set
-# CONFIG_DEBUG_INFO_NONE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-# CONFIG_DEBUG_INFO_DWARF4 is not set
-# CONFIG_DEBUG_INFO_DWARF5 is not set
-CONFIG_DEBUG_INFO_BTF=y
-CONFIG_MODULE_ALLOW_BTF_MISMATCH=y
-CONFIG_PAHOLE_HAS_SPLIT_BTF=y
-CONFIG_DEBUG_INFO_BTF_MODULES=y
-# CONFIG_GDB_SCRIPTS is not set
-CONFIG_FRAME_WARN=2048
-CONFIG_STRIP_ASM_SYMS=y
-# CONFIG_READABLE_ASM is not set
-# CONFIG_HEADERS_INSTALL is not set
-# CONFIG_DEBUG_SECTION_MISMATCH is not set
-CONFIG_SECTION_MISMATCH_WARN_ONLY=y
-# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
-CONFIG_ARCH_WANT_FRAME_POINTERS=y
-CONFIG_FRAME_POINTER=y
-CONFIG_VMLINUX_MAP=y
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# end of Compile-time checks and compiler options
-
-#
-# Generic Kernel Debugging Instruments
-#
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
-CONFIG_MAGIC_SYSRQ_SERIAL=y
-CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_FS_ALLOW_ALL is not set
-# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
-# CONFIG_DEBUG_FS_ALLOW_NONE is not set
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_KGDB=y
-CONFIG_KGDB_HONOUR_BLOCKLIST=y
-CONFIG_KGDB_SERIAL_CONSOLE=y
-# CONFIG_KGDB_TESTS is not set
-CONFIG_KGDB_KDB=y
-CONFIG_KDB_DEFAULT_ENABLE=0x1
-CONFIG_KDB_KEYBOARD=y
-CONFIG_KDB_CONTINUE_CATASTROPHIC=0
-CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_KCSAN_COMPILER=y
-# end of Generic Kernel Debugging Instruments
-
-# CONFIG_DEBUG_KERNEL is not set
-# CONFIG_DEBUG_MISC is not set
-
-#
-# Memory Debugging
-#
-CONFIG_PAGE_EXTENSION=y
-# CONFIG_DEBUG_PAGEALLOC is not set
-# CONFIG_PAGE_OWNER is not set
-# CONFIG_PAGE_TABLE_CHECK is not set
-# CONFIG_PAGE_POISONING is not set
-# CONFIG_DEBUG_PAGE_REF is not set
-# CONFIG_DEBUG_RODATA_TEST is not set
-CONFIG_ARCH_HAS_DEBUG_WX=y
-# CONFIG_DEBUG_WX is not set
-CONFIG_GENERIC_PTDUMP=y
-# CONFIG_PTDUMP_DEBUGFS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SHRINKER_DEBUG is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_HAVE_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-CONFIG_SCHED_STACK_END_CHECK=y
-# CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_VM_PGTABLE is not set
-# CONFIG_ARCH_HAS_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-CONFIG_MEMORY_NOTIFIER_ERROR_INJECT=m
-# CONFIG_DEBUG_PER_CPU_MAPS is not set
-CONFIG_HAVE_ARCH_KASAN=y
-CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
-CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
-CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
-CONFIG_CC_HAS_KASAN_GENERIC=y
-CONFIG_CC_HAS_KASAN_SW_TAGS=y
-CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
-# CONFIG_KASAN is not set
-CONFIG_HAVE_ARCH_KFENCE=y
-CONFIG_KFENCE=y
-CONFIG_KFENCE_SAMPLE_INTERVAL=0
-CONFIG_KFENCE_NUM_OBJECTS=255
-CONFIG_KFENCE_STATIC_KEYS=y
-CONFIG_KFENCE_STRESS_TEST_FAULTS=0
-# end of Memory Debugging
-
-# CONFIG_DEBUG_SHIRQ is not set
-
-#
-# Debug Oops, Lockups and Hangs
-#
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=90
-CONFIG_LOCKUP_DETECTOR=y
-CONFIG_SOFTLOCKUP_DETECTOR=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=480
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_WQ_WATCHDOG=y
-# CONFIG_TEST_LOCKUP is not set
-# end of Debug Oops, Lockups and Hangs
-
-#
-# Scheduler Debugging
-#
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHED_INFO=y
-CONFIG_SCHEDSTATS=y
-# end of Scheduler Debugging
-
-# CONFIG_DEBUG_TIMEKEEPING is not set
-# CONFIG_DEBUG_PREEMPT is not set
-
-#
-# Lock Debugging (spinlocks, mutexes, etc...)
-#
-# CONFIG_LOCK_DEBUGGING_SUPPORT is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
-# CONFIG_DEBUG_RWSEMS is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_DEBUG_ATOMIC_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_LOCK_TORTURE_TEST is not set
-# CONFIG_WW_MUTEX_SELFTEST is not set
-# CONFIG_SCF_TORTURE_TEST is not set
-# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
-# end of Lock Debugging (spinlocks, mutexes, etc...)
-
-# CONFIG_DEBUG_IRQFLAGS is not set
-CONFIG_STACKTRACE=y
-# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
-# CONFIG_DEBUG_KOBJECT is not set
-
-#
-# Debug kernel data structures
-#
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_PLIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BUG_ON_DATA_CORRUPTION is not set
-# end of Debug kernel data structures
-
-# CONFIG_DEBUG_CREDENTIALS is not set
-
-#
-# RCU Debugging
-#
-CONFIG_TORTURE_TEST=m
-CONFIG_RCU_SCALE_TEST=m
-CONFIG_RCU_TORTURE_TEST=m
-# CONFIG_RCU_REF_SCALE_TEST is not set
-CONFIG_RCU_CPU_STALL_TIMEOUT=60
-CONFIG_RCU_TRACE=y
-# CONFIG_RCU_EQS_DEBUG is not set
-# end of RCU Debugging
-
-# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-CONFIG_LATENCYTOP=y
-CONFIG_NOP_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_TRACER_MAX_TRACE=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_RING_BUFFER=y
-CONFIG_EVENT_TRACING=y
-CONFIG_CONTEXT_SWITCH_TRACER=y
-CONFIG_RING_BUFFER_ALLOW_SWAP=y
-CONFIG_TRACING=y
-CONFIG_GENERIC_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-CONFIG_FTRACE=y
-CONFIG_BOOTTIME_TRACING=y
-CONFIG_FUNCTION_TRACER=y
-CONFIG_FUNCTION_GRAPH_TRACER=y
-CONFIG_DYNAMIC_FTRACE=y
-CONFIG_DYNAMIC_FTRACE_WITH_REGS=y
-# CONFIG_FPROBE is not set
-CONFIG_FUNCTION_PROFILER=y
-CONFIG_STACK_TRACER=y
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-CONFIG_SCHED_TRACER=y
-# CONFIG_HWLAT_TRACER is not set
-CONFIG_OSNOISE_TRACER=y
-CONFIG_TIMERLAT_TRACER=y
-CONFIG_FTRACE_SYSCALLS=y
-CONFIG_TRACER_SNAPSHOT=y
-CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y
-CONFIG_BRANCH_PROFILE_NONE=y
-# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
-# CONFIG_PROFILE_ALL_BRANCHES is not set
-CONFIG_BLK_DEV_IO_TRACE=y
-CONFIG_KPROBE_EVENTS=y
-# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set
-CONFIG_UPROBE_EVENTS=y
-CONFIG_BPF_EVENTS=y
-CONFIG_DYNAMIC_EVENTS=y
-CONFIG_PROBE_EVENTS=y
-# CONFIG_BPF_KPROBE_OVERRIDE is not set
-CONFIG_FTRACE_MCOUNT_RECORD=y
-CONFIG_FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY=y
-CONFIG_TRACING_MAP=y
-CONFIG_SYNTH_EVENTS=y
-CONFIG_HIST_TRIGGERS=y
-# CONFIG_TRACE_EVENT_INJECT is not set
-# CONFIG_TRACEPOINT_BENCHMARK is not set
-CONFIG_RING_BUFFER_BENCHMARK=m
-# CONFIG_TRACE_EVAL_MAP_FILE is not set
-# CONFIG_FTRACE_RECORD_RECURSION is not set
-# CONFIG_FTRACE_STARTUP_TEST is not set
-# CONFIG_RING_BUFFER_STARTUP_TEST is not set
-# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
-# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
-# CONFIG_SYNTH_EVENT_GEN_TEST is not set
-# CONFIG_KPROBE_EVENT_GEN_TEST is not set
-# CONFIG_HIST_TRIGGERS_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_STRICT_DEVMEM=y
-CONFIG_IO_STRICT_DEVMEM=y
-
-#
-# arm64 Debugging
-#
-CONFIG_PID_IN_CONTEXTIDR=y
-# CONFIG_DEBUG_EFI is not set
-CONFIG_ARM64_RELOC_TEST=m
-CONFIG_CORESIGHT=m
-CONFIG_CORESIGHT_LINKS_AND_SINKS=m
-CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m
-CONFIG_CORESIGHT_CATU=m
-CONFIG_CORESIGHT_SINK_TPIU=m
-CONFIG_CORESIGHT_SINK_ETBV10=m
-CONFIG_CORESIGHT_SOURCE_ETM4X=m
-CONFIG_ETM4X_IMPDEF_FEATURE=y
-CONFIG_CORESIGHT_STM=m
-# CONFIG_CORESIGHT_CPU_DEBUG is not set
-CONFIG_CORESIGHT_CTI=m
-# CONFIG_CORESIGHT_CTI_INTEGRATION_REGS is not set
-CONFIG_CORESIGHT_TRBE=m
-# end of arm64 Debugging
-
-#
-# Kernel Testing and Coverage
-#
-# CONFIG_KUNIT is not set
-CONFIG_NOTIFIER_ERROR_INJECTION=m
-CONFIG_PM_NOTIFIER_ERROR_INJECT=m
-CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT=m
-CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m
-CONFIG_FUNCTION_ERROR_INJECTION=y
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_ARCH_HAS_KCOV=y
-CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-# CONFIG_KCOV is not set
-CONFIG_RUNTIME_TESTING_MENU=y
-CONFIG_LKDTM=m
-# CONFIG_TEST_MIN_HEAP is not set
-# CONFIG_TEST_DIV64 is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_TEST_REF_TRACKER is not set
-CONFIG_RBTREE_TEST=m
-# CONFIG_REED_SOLOMON_TEST is not set
-# CONFIG_INTERVAL_TREE_TEST is not set
-# CONFIG_PERCPU_TEST is not set
-# CONFIG_ATOMIC64_SELFTEST is not set
-CONFIG_ASYNC_RAID6_TEST=m
-# CONFIG_TEST_HEXDUMP is not set
-# CONFIG_STRING_SELFTEST is not set
-# CONFIG_TEST_STRING_HELPERS is not set
-# CONFIG_TEST_STRSCPY is not set
-# CONFIG_TEST_KSTRTOX is not set
-# CONFIG_TEST_PRINTF is not set
-# CONFIG_TEST_SCANF is not set
-# CONFIG_TEST_BITMAP is not set
-# CONFIG_TEST_UUID is not set
-# CONFIG_TEST_XARRAY is not set
-# CONFIG_TEST_MAPLE_TREE is not set
-# CONFIG_TEST_OVERFLOW is not set
-# CONFIG_TEST_RHASHTABLE is not set
-# CONFIG_TEST_SIPHASH is not set
-# CONFIG_TEST_HASH is not set
-# CONFIG_TEST_IDA is not set
-# CONFIG_TEST_PARMAN is not set
-CONFIG_TEST_LKM=m
-# CONFIG_TEST_BITOPS is not set
-# CONFIG_TEST_VMALLOC is not set
-# CONFIG_TEST_USER_COPY is not set
-# CONFIG_TEST_BPF is not set
-# CONFIG_TEST_BLACKHOLE_DEV is not set
-# CONFIG_FIND_BIT_BENCHMARK is not set
-CONFIG_TEST_FIRMWARE=m
-CONFIG_TEST_SYSCTL=m
-# CONFIG_TEST_UDELAY is not set
-# CONFIG_TEST_STATIC_KEYS is not set
-# CONFIG_TEST_KMOD is not set
-# CONFIG_TEST_MEMCAT_P is not set
-# CONFIG_TEST_OBJAGG is not set
-# CONFIG_TEST_STACKINIT is not set
-# CONFIG_TEST_MEMINIT is not set
-# CONFIG_TEST_HMM is not set
-# CONFIG_TEST_FREE_PAGES is not set
-CONFIG_ARCH_USE_MEMTEST=y
-# CONFIG_MEMTEST is not set
-# CONFIG_HYPERV_TESTING is not set
-# end of Kernel Testing and Coverage
-# end of Kernel hacking
-# CONFIG_ANON_VMA_NAME is not set
-CONFIG_NET_9P_FD=m
-CONFIG_DEVTMPFS_SAFE=y
-CONFIG_GNSS_USB=m
-CONFIG_MTD_NAND_RENESAS=m
-CONFIG_NET_VENDOR_ENGLEDER=y
-CONFIG_TSNEP=m
-# CONFIG_TSNEP_SELFTESTS is not set
-CONFIG_LAN966X_SWITCH=m
-CONFIG_NET_VENDOR_VERTEXCOM=y
-CONFIG_MSE102X=m
-CONFIG_MCTP_SERIAL=m
-CONFIG_MCTP_TRANSPORT_I2C=m
-# CONFIG_WWAN_DEBUGFS is not set
-CONFIG_SERIAL_8250_PERICOM=m
-CONFIG_SPMI_MTK_PMIF=m
-CONFIG_PINCTRL_IMXRT1050=y
-CONFIG_PINCTRL_IMX93=m
-CONFIG_PINCTRL_SDX65=m
-CONFIG_PINCTRL_SM8450=m
-CONFIG_PINCTRL_SM8450_LPASS_LPI=m
-CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
-CONFIG_PINCTRL_SM8280XP_LPASS_LPI=m
-CONFIG_GPIO_SIM=m
-CONFIG_CHARGER_MAX77976=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_SENSORS_NZXT_SMART2=m
-CONFIG_SENSORS_DELTA_AHE50DC_FAN=m
-CONFIG_SENSORS_IR38064_REGULATOR=y
-CONFIG_SENSORS_MP5023=m
-CONFIG_SENSORS_INA238=m
-CONFIG_RZG2L_THERMAL=m
-CONFIG_RENESAS_RZG2LWDT=m
-CONFIG_REGULATOR_MAX20086=m
-CONFIG_VIDEO_STM32_DMA2D=m
-CONFIG_VIDEO_OV5693=m
-CONFIG_DRM_RCAR_USE_LVDS=y
-CONFIG_DRM_RCAR_USE_MIPI_DSI=y
-CONFIG_DRM_RCAR_MIPI_DSI=m
-CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
-CONFIG_DRM_PANEL_JDI_R63452=m
-CONFIG_DRM_PANEL_NOVATEK_NT35950=m
-CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
-CONFIG_TINYDRM_ILI9163=m
-CONFIG_SND_AMD_ACP_CONFIG=m
-CONFIG_SND_SOC_APPLE_MCA=m
-CONFIG_SND_SOC_AK4375=m
-CONFIG_SND_SOC_TLV320ADC3XXX=m
-CONFIG_HID_LETSKETCH=m
-CONFIG_LEDS_MT6360=m
-CONFIG_VIDEO_MAX96712=m
-CONFIG_COMMON_CLK_LAN966X=y
-CONFIG_COMMON_CLK_MT7986=y
-CONFIG_COMMON_CLK_MT7986_ETHSYS=y
-CONFIG_RENESAS_OSTM=y
-CONFIG_EXYNOS_USI=m
-CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
-CONFIG_AD74413R=m
-CONFIG_AD3552R=m
-CONFIG_AD7293=m
-CONFIG_ADMV1013=m
-CONFIG_ADMV1014=m
-CONFIG_ADMV4420=m
-CONFIG_PHY_MESON8_HDMI_TX=m
-CONFIG_PHY_FSL_IMX8M_PCIE=m
-CONFIG_PHY_FSL_LYNX_28G=m
-CONFIG_PHY_LAN966X_SERDES=m
-CONFIG_PHY_QCOM_EDP=m
-# CONFIG_CACHEFILES_ERROR_INJECTION is not set
-CONFIG_UNICODE_UTF8_DATA=m
-# CONFIG_NET_DEV_REFCNT_TRACKER is not set
-# CONFIG_NET_NS_REFCNT_TRACKER is not set
-# CONFIG_KFENCE is not set
-# CONFIG_FTRACE_SORT_STARTUP_TEST is not set
-CONFIG_BACKTRACE_VERBOSE=y
-CONFIG_APPLE_PMGR_PWRSTATE=y
-CONFIG_APPLE_RTKIT=m
-CONFIG_APPLE_SART=m
-CONFIG_ADMV8818=m
-# CONFIG_KCSAN is not set
-CONFIG_PECI=m
-CONFIG_PECI_CPU=m
-CONFIG_PECI_ASPEED=m
-CONFIG_SENSORS_PECI_CPUTEMP=m
-CONFIG_SENSORS_PECI_DIMMTEMP=m
-# CONFIG_BOOT_CONFIG_EMBED is not set
-CONFIG_INITRAMFS_PRESERVE_MTIME=y
-CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y
-CONFIG_ARCH_BCMBCA=y
-CONFIG_ARCH_HPE=y
-CONFIG_ARCH_HPE_GXP=y
-CONFIG_ARM_ERRATA_764319=y
-# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
-CONFIG_CAN_CTUCANFD_PCI=m
-CONFIG_CAN_CTUCANFD_PLATFORM=m
-CONFIG_FW_LOADER_COMPRESS_XZ=y
-CONFIG_FW_LOADER_COMPRESS_ZSTD=y
-CONFIG_FW_UPLOAD=y
-CONFIG_QCOM_SSC_BLOCK_BUS=y
-CONFIG_MHI_BUS_EP=m
-CONFIG_MTK_ADSP_IPC=m
-CONFIG_EFI_COCO_SECRET=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=m
-CONFIG_SFC_SIENA=m
-CONFIG_SFC_SIENA_MTD=y
-CONFIG_SFC_SIENA_MCDI_MON=y
-CONFIG_SFC_SIENA_SRIOV=y
-# CONFIG_SFC_SIENA_MCDI_LOGGING is not set
-CONFIG_ADIN1100_PHY=m
-CONFIG_DP83TD510_PHY=m
-CONFIG_WLAN_VENDOR_PURELIFI=y
-CONFIG_PLFXLC=m
-CONFIG_RTW89_8852CE=m
-CONFIG_WLAN_VENDOR_SILABS=y
-CONFIG_MTK_T7XX=m
-CONFIG_JOYSTICK_SENSEHAT=m
-CONFIG_INPUT_IQS7222=m
-# CONFIG_HVC_DCC_SERIALIZE_SMP is not set
-CONFIG_SPI_MTK_SNFI=m
-CONFIG_SPI_NPCM_FIU=m
-CONFIG_SPI_NPCM_PSPI=m
-CONFIG_PINCTRL_IMXRT1170=y
-CONFIG_PINCTRL_SC7280_LPASS_LPI=m
-CONFIG_PINCTRL_SM8250_LPASS_LPI=m
-CONFIG_SENSORS_LAN966X=m
-CONFIG_SENSORS_NCT6775_I2C=m
-CONFIG_SENSORS_XDPE152=m
-CONFIG_RENESAS_RZN1WDT=m
-CONFIG_GXP_WATCHDOG=m
-CONFIG_REGULATOR_RT5759=m
-CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
-CONFIG_DRM_FSL_LDB=m
-CONFIG_DRM_LONTIUM_LT9211=m
-CONFIG_DRM_DW_HDMI_GP_AUDIO=m
-CONFIG_DRM_SSD130X_SPI=m
-CONFIG_SND_SERIAL_GENERIC=m
-CONFIG_SND_SOC_CS35L45_SPI=m
-CONFIG_SND_SOC_CS35L45_I2C=m
-CONFIG_SND_SOC_MAX98396=m
-CONFIG_SND_SOC_WM8731_I2C=m
-CONFIG_SND_SOC_WM8731_SPI=m
-CONFIG_SND_SOC_WM8940=m
-CONFIG_HID_MEGAWORLD_FF=m
-CONFIG_TYPEC_MUX_FSA4480=m
-CONFIG_LEDS_PWM_MULTICOLOR=m
-CONFIG_LEDS_QCOM_LPG=m
-CONFIG_TEGRA186_GPC_DMA=m
-# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set
-CONFIG_PWM_XILINX=m
-CONFIG_HTE=y
-CONFIG_HTE_TEGRA194=m
-# CONFIG_HTE_TEGRA194_TEST is not set
-# CONFIG_CACHEFILES_ONDEMAND is not set
-CONFIG_TRUSTED_KEYS_TPM=y
-CONFIG_TRUSTED_KEYS_TEE=y
-CONFIG_TRUSTED_KEYS_CAAM=y
-CONFIG_CRYPTO_SM3_GENERIC=m
-CONFIG_CRYPTO_SM4_GENERIC=m
-# CONFIG_FIPS_SIGNATURE_SELFTEST is not set
-CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y
-# CONFIG_DEBUG_NET is not set
-CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
-# CONFIG_CGROUP_FAVOR_DYNMODS is not set
-CONFIG_ARCH_BCMBCA_CORTEXA7=y
-CONFIG_ARCH_BCMBCA_CORTEXA9=y
-CONFIG_ARCH_BCMBCA_BRAHMAB15=y
-CONFIG_ARCH_MSM8909=y
-CONFIG_ARCH_SUNPLUS=y
-CONFIG_SOC_SP7021=y
-# CONFIG_UNUSED_BOARD_FILES is not set
-# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
-CONFIG_DAMON_LRU_SORT=y
-CONFIG_NF_FLOW_TABLE_PROCFS=y
-CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
-CONFIG_PCI_EPF_VNTB=m
-CONFIG_ARM_SCMI_POWER_CONTROL=m
-CONFIG_BLK_DEV_UBLK=m
-CONFIG_NVME_AUTH=y
-CONFIG_NVME_TARGET_AUTH=y
-CONFIG_VCPU_STALL_DETECTOR=m
-CONFIG_SCSI_BUSLOGIC=m
-CONFIG_SCSI_FLASHPOINT=y
-CONFIG_AHCI_BRCM=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
-CONFIG_NET_VENDOR_WANGXUN=y
-CONFIG_NET_VENDOR_ADI=y
-CONFIG_ADIN1110=m
-CONFIG_NGBE=m
-CONFIG_TXGBE=m
-CONFIG_NET_VENDOR_SUNPLUS=y
-CONFIG_SP7021_EMAC=m
-CONFIG_CAN_NETLINK=y
-CONFIG_CAN_CAN327=m
-CONFIG_CAN_ESD_USB=m
-CONFIG_HW_RANDOM_BCM2835=m
-CONFIG_TCG_TIS_I2C=m
-# CONFIG_RANDOM_TRUST_CPU is not set
-CONFIG_I2C_BRCMSTB=m
-CONFIG_I2C_NPCM=m
-CONFIG_I2C_RZV2M=m
-CONFIG_SPI_BCM63XX_HSSPI=m
-CONFIG_SPI_GXP=m
-CONFIG_SPI_MICROCHIP_CORE=m
-CONFIG_SPI_MICROCHIP_CORE_QSPI=m
-CONFIG_SPI_SUNPLUS_SP7021=m
-CONFIG_PINCTRL_MSM8909=m
-CONFIG_PINCTRL_SM6375=m
-CONFIG_PINCTRL_SUN20I_D1=y
-CONFIG_SENSORS_LT7182S=m
-CONFIG_SUNPLUS_WATCHDOG=m
-CONFIG_VIDEO_SUN6I_MIPI_CSI2=m
-CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m
-CONFIG_VIDEO_AR0521=m
-CONFIG_DRM_PANEL_EBBG_FT8719=m
-CONFIG_DRM_TI_DLPC3433=m
-CONFIG_DRM_IMX8QM_LDB=m
-CONFIG_DRM_IMX8QXP_LDB=m
-CONFIG_DRM_IMX8QXP_PIXEL_COMBINER=m
-CONFIG_DRM_IMX8QXP_PIXEL_LINK=m
-CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI=m
-CONFIG_DRM_IMX8QXP_LDB=m
-# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set
-CONFIG_RCU_NOCB_CPU_DEFAULT_ALL=y
-CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=m
-CONFIG_NPCM_ADC=m
-CONFIG_QCOM_SPMI_RRADC=m
-CONFIG_PWM_CLK=m
-CONFIG_PWM_OMAP_DMTIMER=m
-CONFIG_RESET_TI_TPS380X=m
-CONFIG_A64FX_DIAG=y
-# CONFIG_RV is not set
-# Ethernet Power Sourcing Equipment Support
-CONFIG_PSE_CONTROLLER=y
-CONFIG_PSE_REGULATOR=m
-CONFIG_STAGING_MEDIA_DEPRECATED=y
-# CONFIG_FORCE_NR_CPUS is not set
-# CONFIG_DEBUG_MAPLE_TREE is not set
-CONFIG_QCOM_TSENS=m
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_KERNEL_ZSTD=y
diff --git a/add-rockchip-iep-driver.patch b/add-rockchip-iep-driver.patch
index 4ef816e..384119b 100644
--- a/add-rockchip-iep-driver.patch
+++ b/add-rockchip-iep-driver.patch
@@ -1,6 +1,6 @@
-diff -Naur a/Documentation/devicetree/bindings/media/rockchip-iep.yaml b/Documentation/devicetree/bindings/media/rockchip-iep.yaml
---- a/Documentation/devicetree/bindings/media/rockchip-iep.yaml	1970-01-01 00:00:00.000000000 +0000
-+++ b/Documentation/devicetree/bindings/media/rockchip-iep.yaml	2022-10-29 14:05:58.847424857 +0000
+diff -up linux-6.17-rc1/Documentation/devicetree/bindings/media/rockchip-iep.yaml.45~ linux-6.17-rc1/Documentation/devicetree/bindings/media/rockchip-iep.yaml
+--- linux-6.17-rc1/Documentation/devicetree/bindings/media/rockchip-iep.yaml.45~	2025-08-10 20:51:22.747729668 +0200
++++ linux-6.17-rc1/Documentation/devicetree/bindings/media/rockchip-iep.yaml	2025-08-10 20:51:22.747729668 +0200
 @@ -0,0 +1,73 @@
 +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 +%YAML 1.2
@@ -75,10 +75,10 @@ diff -Naur a/Documentation/devicetree/bindings/media/rockchip-iep.yaml b/Documen
 +      iommus = <&iep_mmu>;
 +      power-domains = <&power RK3228_PD_VIO>;
 +    };
-diff -Naur a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
---- a/arch/arm/boot/dts/rk3288.dtsi	2022-10-02 21:09:07.000000000 +0000
-+++ b/arch/arm/boot/dts/rk3288.dtsi	2022-10-29 13:58:32.340591189 +0000
-@@ -984,14 +984,25 @@
+diff -up linux-6.17-rc1/arch/arm/boot/dts/rockchip/rk3288.dtsi.45~ linux-6.17-rc1/arch/arm/boot/dts/rockchip/rk3288.dtsi
+--- linux-6.17-rc1/arch/arm/boot/dts/rockchip/rk3288.dtsi.45~	2025-08-10 18:41:16.000000000 +0200
++++ linux-6.17-rc1/arch/arm/boot/dts/rockchip/rk3288.dtsi	2025-08-10 20:51:22.747575447 +0200
+@@ -990,14 +990,25 @@
  		reset-names = "crypto-rst";
  	};
  
@@ -105,10 +105,10 @@ diff -Naur a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
  	};
  
  	isp_mmu: iommu@ff914000 {
-diff -Naur a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi	2022-10-02 21:09:07.000000000 +0000
-+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi	2022-10-29 14:01:57.969268550 +0000
-@@ -720,6 +720,28 @@
+diff -up linux-6.17-rc1/arch/arm64/boot/dts/rockchip/rk3328.dtsi.45~ linux-6.17-rc1/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+--- linux-6.17-rc1/arch/arm64/boot/dts/rockchip/rk3328.dtsi.45~	2025-08-10 18:41:16.000000000 +0200
++++ linux-6.17-rc1/arch/arm64/boot/dts/rockchip/rk3328.dtsi	2025-08-10 20:51:22.747116581 +0200
+@@ -747,6 +747,28 @@
  		status = "disabled";
  	};
  
@@ -137,13 +137,14 @@ diff -Naur a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rock
  	hdmi: hdmi@ff3c0000 {
  		compatible = "rockchip,rk3328-dw-hdmi";
  		reg = <0x0 0xff3c0000 0x0 0x20000>;
-diff -Naur a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi	2022-10-29 13:25:04.860027076 +0000
-+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi	2022-10-29 14:03:58.988302621 +0000
-@@ -1359,12 +1359,24 @@
+diff -up linux-6.17-rc1/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi.45~ linux-6.17-rc1/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
+--- linux-6.17-rc1/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi.45~	2025-08-10 20:51:22.739834736 +0200
++++ linux-6.17-rc1/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi	2025-08-10 20:51:22.747367465 +0200
+@@ -1477,11 +1477,24 @@
  		#iommu-cells = <0>;
  	};
  
++
 +	iep: iep@ff670000 {
 +		compatible = "rockchip,rk3399-iep", "rockchip,rk3228-iep";
 +		reg = <0x0 0xff670000 0x0 0x800>;
@@ -160,56 +161,51 @@ diff -Naur a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rock
  		reg = <0x0 0xff670800 0x0 0x40>;
  		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
  		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
- 		clock-names = "aclk", "iface";
 +		power-domains = <&power RK3399_PD_IEP>;
+ 		clock-names = "aclk", "iface";
  		#iommu-cells = <0>;
  		status = "disabled";
- 	};
-diff -Naur a/drivers/media/platform/rockchip/Kconfig b/drivers/media/platform/rockchip/Kconfig
---- a/drivers/media/platform/rockchip/Kconfig	2022-10-02 21:09:07.000000000 +0000
-+++ b/drivers/media/platform/rockchip/Kconfig	2022-10-29 14:05:58.867424716 +0000
-@@ -4,3 +4,4 @@
- 
+diff -up linux-6.17-rc1/drivers/media/platform/rockchip/Kconfig.45~ linux-6.17-rc1/drivers/media/platform/rockchip/Kconfig
+--- linux-6.17-rc1/drivers/media/platform/rockchip/Kconfig.45~	2025-08-10 18:41:16.000000000 +0200
++++ linux-6.17-rc1/drivers/media/platform/rockchip/Kconfig	2025-08-10 20:52:04.856077174 +0200
+@@ -5,3 +5,17 @@ comment "Rockchip media platform drivers
  source "drivers/media/platform/rockchip/rga/Kconfig"
  source "drivers/media/platform/rockchip/rkisp1/Kconfig"
-+source "drivers/media/platform/rockchip/iep/Kconfig"
-diff -Naur a/drivers/media/platform/rockchip/Makefile b/drivers/media/platform/rockchip/Makefile
---- a/drivers/media/platform/rockchip/Makefile	2022-10-02 21:09:07.000000000 +0000
-+++ b/drivers/media/platform/rockchip/Makefile	2022-10-29 14:05:58.867424716 +0000
-@@ -1,3 +1,4 @@
- # SPDX-License-Identifier: GPL-2.0-only
+ source "drivers/media/platform/rockchip/rkvdec/Kconfig"
++
++config VIDEO_ROCKCHIP_IEP
++       tristate "Rockchip Image Enhancement Processor"
++       depends on VIDEO_DEV && VIDEO_V4L2
++       depends on ARCH_ROCKCHIP || COMPILE_TEST
++       select VIDEOBUF2_DMA_CONTIG
++       select V4L2_MEM2MEM_DEV
++       help
++         This is a v4l2 driver for Rockchip Image Enhancement Processor (IEP)
++         found in most Rockchip RK3xxx SoCs.
++         Rockchip IEP supports various enhancement operations for RGB and YUV
++         images. The driver currently implements YUV deinterlacing only.
++         To compile this driver as a module, choose M here: the module
++         will be called rockchip-iep
+diff -up linux-6.17-rc1/drivers/media/platform/rockchip/Makefile.45~ linux-6.17-rc1/drivers/media/platform/rockchip/Makefile
+--- linux-6.17-rc1/drivers/media/platform/rockchip/Makefile.45~	2025-08-10 18:41:16.000000000 +0200
++++ linux-6.17-rc1/drivers/media/platform/rockchip/Makefile	2025-08-10 20:52:26.816300514 +0200
+@@ -2,3 +2,4 @@
  obj-y += rga/
  obj-y += rkisp1/
-+obj-y += iep/
-diff -Naur a/drivers/media/platform/rockchip/iep/Kconfig b/drivers/media/platform/rockchip/iep/Kconfig
---- a/drivers/media/platform/rockchip/iep/Kconfig	1970-01-01 00:00:00.000000000 +0000
-+++ b/drivers/media/platform/rockchip/iep/Kconfig	2022-10-29 14:05:58.857424787 +0000
-@@ -0,0 +1,13 @@
-+config VIDEO_ROCKCHIP_IEP
-+	tristate "Rockchip Image Enhancement Processor"
-+	depends on VIDEO_DEV && VIDEO_V4L2
-+	depends on ARCH_ROCKCHIP || COMPILE_TEST
-+	select VIDEOBUF2_DMA_CONTIG
-+	select V4L2_MEM2MEM_DEV
-+	help
-+	  This is a v4l2 driver for Rockchip Image Enhancement Processor (IEP)
-+	  found in most Rockchip RK3xxx SoCs.
-+	  Rockchip IEP supports various enhancement operations for RGB and YUV
-+	  images. The driver currently implements YUV deinterlacing only.
-+	  To compile this driver as a module, choose M here: the module
-+	  will be called rockchip-iep
-diff -Naur a/drivers/media/platform/rockchip/iep/Makefile b/drivers/media/platform/rockchip/iep/Makefile
---- a/drivers/media/platform/rockchip/iep/Makefile	1970-01-01 00:00:00.000000000 +0000
-+++ b/drivers/media/platform/rockchip/iep/Makefile	2022-10-29 14:05:58.857424787 +0000
+ obj-y += rkvdec/
++obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += iep/
+diff -up linux-6.17-rc1/drivers/media/platform/rockchip/iep/Makefile.45~ linux-6.17-rc1/drivers/media/platform/rockchip/iep/Makefile
+--- linux-6.17-rc1/drivers/media/platform/rockchip/iep/Makefile.45~	2025-08-10 20:51:22.748264067 +0200
++++ linux-6.17-rc1/drivers/media/platform/rockchip/iep/Makefile	2025-08-10 20:51:22.748264067 +0200
 @@ -0,0 +1,5 @@
 +# SPDX-License-Identifier: GPL-2.0-only
 +
 +rockchip-iep-objs := iep.o
 +
 +obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip-iep.o
-diff -Naur a/drivers/media/platform/rockchip/iep/iep-regs.h b/drivers/media/platform/rockchip/iep/iep-regs.h
---- a/drivers/media/platform/rockchip/iep/iep-regs.h	1970-01-01 00:00:00.000000000 +0000
-+++ b/drivers/media/platform/rockchip/iep/iep-regs.h	2022-10-29 14:05:58.857424787 +0000
+diff -up linux-6.17-rc1/drivers/media/platform/rockchip/iep/iep-regs.h.45~ linux-6.17-rc1/drivers/media/platform/rockchip/iep/iep-regs.h
+--- linux-6.17-rc1/drivers/media/platform/rockchip/iep/iep-regs.h.45~	2025-08-10 20:51:22.748137228 +0200
++++ linux-6.17-rc1/drivers/media/platform/rockchip/iep/iep-regs.h	2025-08-10 20:51:22.748137228 +0200
 @@ -0,0 +1,291 @@
 +/* SPDX-License-Identifier: GPL-2.0-only */
 +/*
@@ -502,9 +498,9 @@ diff -Naur a/drivers/media/platform/rockchip/iep/iep-regs.h b/drivers/media/plat
 +#define YUV_SIN_HUE(v) ((v << IEP_YUV_SIN_HUE_SHFT) & IEP_YUV_SIN_HUE_MASK)
 +
 +#endif
-diff -Naur a/drivers/media/platform/rockchip/iep/iep.c b/drivers/media/platform/rockchip/iep/iep.c
---- a/drivers/media/platform/rockchip/iep/iep.c	1970-01-01 00:00:00.000000000 +0000
-+++ b/drivers/media/platform/rockchip/iep/iep.c	2022-10-29 14:05:58.857424787 +0000
+diff -up linux-6.17-rc1/drivers/media/platform/rockchip/iep/iep.c.45~ linux-6.17-rc1/drivers/media/platform/rockchip/iep/iep.c
+--- linux-6.17-rc1/drivers/media/platform/rockchip/iep/iep.c.45~	2025-08-10 20:51:22.747965513 +0200
++++ linux-6.17-rc1/drivers/media/platform/rockchip/iep/iep.c	2025-08-10 20:51:22.747965513 +0200
 @@ -0,0 +1,1089 @@
 +// SPDX-License-Identifier: GPL-2.0-only
 +/*
@@ -1595,9 +1591,9 @@ diff -Naur a/drivers/media/platform/rockchip/iep/iep.c b/drivers/media/platform/
 +MODULE_AUTHOR("Alex Bee <knaerzche@gmail.com>");
 +MODULE_DESCRIPTION("Rockchip Image Enhancement Processor");
 +MODULE_LICENSE("GPL v2");
-diff -Naur a/drivers/media/platform/rockchip/iep/iep.h b/drivers/media/platform/rockchip/iep/iep.h
---- a/drivers/media/platform/rockchip/iep/iep.h	1970-01-01 00:00:00.000000000 +0000
-+++ b/drivers/media/platform/rockchip/iep/iep.h	2022-10-29 14:05:58.857424787 +0000
+diff -up linux-6.17-rc1/drivers/media/platform/rockchip/iep/iep.h.45~ linux-6.17-rc1/drivers/media/platform/rockchip/iep/iep.h
+--- linux-6.17-rc1/drivers/media/platform/rockchip/iep/iep.h.45~	2025-08-10 20:51:22.748066664 +0200
++++ linux-6.17-rc1/drivers/media/platform/rockchip/iep/iep.h	2025-08-10 20:51:22.748066664 +0200
 @@ -0,0 +1,112 @@
 +/* SPDX-License-Identifier: GPL-2.0-only */
 +/*
diff --git a/amdgpu-ignore-min-pcap.patch b/amdgpu-ignore-min-pcap.patch
new file mode 100644
index 0000000..e039a7d
--- /dev/null
+++ b/amdgpu-ignore-min-pcap.patch
@@ -0,0 +1,75 @@
+diff -up linux-6.19-rc4/drivers/gpu/drm/amd/amdgpu/amdgpu.h.33~ linux-6.19-rc4/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+--- linux-6.19-rc4/drivers/gpu/drm/amd/amdgpu/amdgpu.h.33~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/drivers/gpu/drm/amd/amdgpu/amdgpu.h	2026-01-10 16:27:40.328473672 +0100
+@@ -164,6 +164,7 @@ struct amdgpu_watchdog_timer {
+  */
+ extern int amdgpu_modeset;
+ extern unsigned int amdgpu_vram_limit;
++extern int amdgpu_ignore_min_pcap;
+ extern int amdgpu_vis_vram_limit;
+ extern int amdgpu_gart_size;
+ extern int amdgpu_gtt_size;
+diff -up linux-6.19-rc4/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.33~ linux-6.19-rc4/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+--- linux-6.19-rc4/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.33~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c	2026-01-10 16:27:40.329185210 +0100
+@@ -150,6 +150,7 @@ enum AMDGPU_DEBUG_MASK {
+ };
+ 
+ unsigned int amdgpu_vram_limit = UINT_MAX;
++int amdgpu_ignore_min_pcap = 0; /* do not ignore by default */
+ int amdgpu_vis_vram_limit;
+ int amdgpu_gart_size = -1; /* auto */
+ int amdgpu_gtt_size = -1; /* auto */
+@@ -272,6 +273,15 @@ struct amdgpu_watchdog_timer amdgpu_watc
+ };
+ 
+ /**
++ * DOC: ignore_min_pcap (int)
++ * Ignore the minimum power cap.
++ * Useful on graphics cards where the minimum power cap is very high.
++ * The default is 0 (Do not ignore).
++ */
++MODULE_PARM_DESC(ignore_min_pcap, "Ignore the minimum power cap");
++module_param_named(ignore_min_pcap, amdgpu_ignore_min_pcap, int, 0600);
++
++/**
+  * DOC: vramlimit (int)
+  * Restrict the total amount of VRAM in MiB for testing.  The default is 0 (Use full VRAM).
+  */
+diff -up linux-6.19-rc4/drivers/gpu/drm/amd/pm/amdgpu_pm.c.33~ linux-6.19-rc4/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+--- linux-6.19-rc4/drivers/gpu/drm/amd/pm/amdgpu_pm.c.33~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/drivers/gpu/drm/amd/pm/amdgpu_pm.c	2026-01-10 16:27:40.329882898 +0100
+@@ -3342,6 +3342,9 @@ static ssize_t amdgpu_hwmon_show_power_c
+ 					 struct device_attribute *attr,
+ 					 char *buf)
+ {
++	if (amdgpu_ignore_min_pcap)
++		return sysfs_emit(buf, "%i\n", 0);
++
+ 	return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MIN);
+ }
+ 
+diff -up linux-6.19-rc4/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c.33~ linux-6.19-rc4/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+--- linux-6.19-rc4/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c.33~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c	2026-01-10 16:43:43.218199014 +0100
+@@ -2974,7 +2974,10 @@ int smu_get_power_limit(void *handle,
+ 			*limit = smu->max_power_limit;
+ 			break;
+ 		case SMU_PPT_LIMIT_MIN:
+-			*limit = smu->min_power_limit;
++			if (amdgpu_ignore_min_pcap)
++				*limit = 0;
++			else
++				*limit = smu->min_power_limit;
+ 			break;
+ 		default:
+ 			return -EINVAL;
+@@ -2995,7 +2998,7 @@ static int smu_set_power_limit(void *han
+ 	if (limit_type == SMU_DEFAULT_PPT_LIMIT) {
+ 		if (!limit)
+ 			limit = smu->current_power_limit;
+-		if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) {
++		if ((limit > smu->max_power_limit) || (!amdgpu_ignore_min_pcap && (limit < smu->min_power_limit))) {
+ 			dev_err(smu->adev->dev,
+ 				"New power limit (%d) is out of range [%d,%d]\n",
+ 				limit, smu->min_power_limit, smu->max_power_limit);
diff --git a/android-enable-building-ashmem-and-binder-as-modules.patch b/android-enable-building-ashmem-and-binder-as-modules.patch
index e7d0d0e..451f56b 100644
--- a/android-enable-building-ashmem-and-binder-as-modules.patch
+++ b/android-enable-building-ashmem-and-binder-as-modules.patch
@@ -1,18 +1,6 @@
-diff -up linux-6.0-rc4/drivers/android/binder_alloc.c.26~ linux-6.0-rc4/drivers/android/binder_alloc.c
---- linux-6.0-rc4/drivers/android/binder_alloc.c.26~	2022-09-04 22:10:01.000000000 +0200
-+++ linux-6.0-rc4/drivers/android/binder_alloc.c	2022-09-08 18:26:47.579376479 +0200
-@@ -38,7 +38,7 @@ enum {
- };
- static uint32_t binder_alloc_debug_mask = BINDER_DEBUG_USER_ERROR;
- 
--module_param_named(debug_mask, binder_alloc_debug_mask,
-+module_param_named(alloc_debug_mask, binder_alloc_debug_mask,
- 		   uint, 0644);
- 
- #define binder_alloc_debug(mask, x...) \
-diff -up linux-6.0-rc4/drivers/android/Kconfig.26~ linux-6.0-rc4/drivers/android/Kconfig
---- linux-6.0-rc4/drivers/android/Kconfig.26~	2022-09-08 18:26:47.579376479 +0200
-+++ linux-6.0-rc4/drivers/android/Kconfig	2022-09-08 18:27:08.453098362 +0200
+diff -up linux-6.18-rc1/drivers/android/Kconfig.26~ linux-6.18-rc1/drivers/android/Kconfig
+--- linux-6.18-rc1/drivers/android/Kconfig.26~	2025-10-12 22:42:36.000000000 +0200
++++ linux-6.18-rc1/drivers/android/Kconfig	2025-10-15 12:20:58.970177753 +0200
 @@ -2,7 +2,7 @@
  menu "Android"
  
@@ -20,42 +8,37 @@ diff -up linux-6.0-rc4/drivers/android/Kconfig.26~ linux-6.0-rc4/drivers/android
 -	bool "Android Binder IPC Driver"
 +	tristate "Android Binder IPC Driver"
  	depends on MMU
+ 	depends on NET
  	default n
- 	help
-diff -up linux-6.0-rc4/drivers/android/Makefile.26~ linux-6.0-rc4/drivers/android/Makefile
---- linux-6.0-rc4/drivers/android/Makefile.26~	2022-09-04 22:10:01.000000000 +0200
-+++ linux-6.0-rc4/drivers/android/Makefile	2022-09-08 18:26:47.579376479 +0200
-@@ -1,6 +1,7 @@
+diff -up linux-6.18-rc1/drivers/android/Makefile.26~ linux-6.18-rc1/drivers/android/Makefile
+--- linux-6.18-rc1/drivers/android/Makefile.26~	2025-10-12 22:42:36.000000000 +0200
++++ linux-6.18-rc1/drivers/android/Makefile	2025-10-15 12:21:50.770099285 +0200
+@@ -1,7 +1,8 @@
  # SPDX-License-Identifier: GPL-2.0-only
  ccflags-y += -I$(src)			# needed for trace events
  
 -obj-$(CONFIG_ANDROID_BINDERFS)		+= binderfs.o
--obj-$(CONFIG_ANDROID_BINDER_IPC)	+= binder.o binder_alloc.o
--obj-$(CONFIG_ANDROID_BINDER_IPC_SELFTEST) += binder_alloc_selftest.o
+-obj-$(CONFIG_ANDROID_BINDER_IPC)	+= binder.o binder_alloc.o binder_netlink.o
 +obj-$(CONFIG_ANDROID_BINDER_IPC)	+= binder_linux.o
-+binder_linux-y := binder.o binder_alloc.o
++binder_linux-y				:= binder.o binder_alloc.o binder_netlink.o
 +binder_linux-$(CONFIG_ANDROID_BINDERFS)	+= binderfs.o
-+binder_linux-$(CONFIG_ANDROID_BINDER_IPC_SELFTEST) += binder_alloc_selftest.o
-diff -up linux-6.0-rc4/drivers/staging/android/ashmem.c.26~ linux-6.0-rc4/drivers/staging/android/ashmem.c
---- linux-6.0-rc4/drivers/staging/android/ashmem.c.26~	2022-09-08 18:26:47.558376758 +0200
-+++ linux-6.0-rc4/drivers/staging/android/ashmem.c	2022-09-08 18:26:47.580376465 +0200
-@@ -24,6 +24,7 @@
- #include <linux/bitops.h>
- #include <linux/mutex.h>
- #include <linux/shmem_fs.h>
-+#include <linux/module.h>
- #include "ashmem.h"
+ obj-$(CONFIG_ANDROID_BINDER_ALLOC_KUNIT_TEST)	+= tests/
+ obj-$(CONFIG_ANDROID_BINDER_IPC_RUST)	+= binder/
+diff -up linux-6.18-rc1/drivers/android/binder_alloc.c.26~ linux-6.18-rc1/drivers/android/binder_alloc.c
+--- linux-6.18-rc1/drivers/android/binder_alloc.c.26~	2025-10-12 22:42:36.000000000 +0200
++++ linux-6.18-rc1/drivers/android/binder_alloc.c	2025-10-15 12:19:26.329236175 +0200
+@@ -39,7 +39,7 @@ enum {
+ };
+ static uint32_t binder_alloc_debug_mask = BINDER_DEBUG_USER_ERROR;
  
- #define ASHMEM_NAME_PREFIX "dev/ashmem/"
-@@ -968,3 +969,5 @@ out:
- 	return ret;
- }
- device_initcall(ashmem_init);
-+
-+MODULE_LICENSE("GPL v2");
-diff -up linux-6.0-rc4/drivers/staging/android/Kconfig.26~ linux-6.0-rc4/drivers/staging/android/Kconfig
---- linux-6.0-rc4/drivers/staging/android/Kconfig.26~	2022-09-08 18:26:47.558376758 +0200
-+++ linux-6.0-rc4/drivers/staging/android/Kconfig	2022-09-08 18:26:47.580376465 +0200
+-module_param_named(debug_mask, binder_alloc_debug_mask,
++module_param_named(alloc_debug_mask, binder_alloc_debug_mask,
+ 		   uint, 0644);
+ 
+ #define binder_alloc_debug(mask, x...) \
+diff -up linux-6.18-rc1/drivers/staging/android/Kconfig.26~ linux-6.18-rc1/drivers/staging/android/Kconfig
+--- linux-6.18-rc1/drivers/staging/android/Kconfig.26~	2025-10-15 12:19:26.316858476 +0200
++++ linux-6.18-rc1/drivers/staging/android/Kconfig	2025-10-15 12:19:26.329354859 +0200
 @@ -4,7 +4,7 @@ menu "Android"
  if ANDROID
  
@@ -65,9 +48,9 @@ diff -up linux-6.0-rc4/drivers/staging/android/Kconfig.26~ linux-6.0-rc4/drivers
  	depends on SHMEM
  	help
  	  The ashmem subsystem is a new shared memory allocator, similar to
-diff -up linux-6.0-rc4/drivers/staging/android/Makefile.26~ linux-6.0-rc4/drivers/staging/android/Makefile
---- linux-6.0-rc4/drivers/staging/android/Makefile.26~	2022-09-08 18:26:47.558376758 +0200
-+++ linux-6.0-rc4/drivers/staging/android/Makefile	2022-09-08 18:26:47.580376465 +0200
+diff -up linux-6.18-rc1/drivers/staging/android/Makefile.26~ linux-6.18-rc1/drivers/staging/android/Makefile
+--- linux-6.18-rc1/drivers/staging/android/Makefile.26~	2025-10-15 12:19:26.316901778 +0200
++++ linux-6.18-rc1/drivers/staging/android/Makefile	2025-10-15 12:19:26.329403702 +0200
 @@ -1,4 +1,5 @@
  # SPDX-License-Identifier: GPL-2.0
  ccflags-y += -I$(src)			# needed for trace events
@@ -75,3 +58,20 @@ diff -up linux-6.0-rc4/drivers/staging/android/Makefile.26~ linux-6.0-rc4/driver
 -obj-$(CONFIG_ASHMEM)			+= ashmem.o
 +obj-$(CONFIG_ASHMEM)			+= ashmem_linux.o
 +ashmem_linux-y				+= ashmem.o
+diff -up linux-6.18-rc1/drivers/staging/android/ashmem.c.26~ linux-6.18-rc1/drivers/staging/android/ashmem.c
+--- linux-6.18-rc1/drivers/staging/android/ashmem.c.26~	2025-10-15 12:19:26.316994964 +0200
++++ linux-6.18-rc1/drivers/staging/android/ashmem.c	2025-10-15 12:19:26.329485086 +0200
+@@ -24,6 +24,7 @@
+ #include <linux/bitops.h>
+ #include <linux/mutex.h>
+ #include <linux/shmem_fs.h>
++#include <linux/module.h>
+ #include "ashmem.h"
+ 
+ #define ASHMEM_NAME_PREFIX "dev/ashmem/"
+@@ -968,3 +969,5 @@ out:
+ 	return ret;
+ }
+ device_initcall(ashmem_init);
++
++MODULE_LICENSE("GPL v2");
diff --git a/armv7hnl-server-omv-defconfig b/arm-omv-defconfig
similarity index 52%
rename from armv7hnl-server-omv-defconfig
rename to arm-omv-defconfig
index 658fa04..65fe5e3 100644
--- a/armv7hnl-server-omv-defconfig
+++ b/arm-omv-defconfig
@@ -1,9451 +1,953 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# Linux/arm 5.10.0-rc1 Kernel Configuration
-#
-CONFIG_CC_VERSION_TEXT="gcc (GCC) 10.2.0 20200723 (OpenMandriva)"
-CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=100200
-CONFIG_LD_VERSION=235010000
-CONFIG_CLANG_VERSION=0
-CONFIG_CC_CAN_LINK=y
-CONFIG_CC_CAN_LINK_STATIC=y
-CONFIG_CC_HAS_ASM_GOTO=y
-CONFIG_CC_HAS_ASM_INLINE=y
-CONFIG_IRQ_WORK=y
-CONFIG_BUILDTIME_TABLE_SORT=y
-
-#
-# General setup
-#
-CONFIG_INIT_ENV_ARG_LIMIT=32
-# CONFIG_COMPILE_TEST is not set
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_BUILD_SALT="dd388ae5eb7aa77d6b419d430830819959712267"
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_DEFAULT_INIT=""
-CONFIG_DEFAULT_HOSTNAME="omv"
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_POSIX_MQUEUE_SYSCTL=y
-# CONFIG_WATCH_QUEUE is not set
-CONFIG_CROSS_MEMORY_ATTACH=y
-# CONFIG_USELIB is not set
-# CONFIG_AUDIT is not set
-# CONFIG_HAVE_ARCH_AUDITSYSCALL is not set
-# CONFIG_AUDITSYSCALL is not set
-
-#
-# IRQ subsystem
-#
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_SIM=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_GENERIC_IRQ_IPI=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_SPARSE_IRQ=y
-# CONFIG_GENERIC_IRQ_DEBUGFS is not set
-# end of IRQ subsystem
-
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_6PACK=m
+CONFIG_842_COMPRESS=y
+CONFIG_842_DECOMPRESS=y
+CONFIG_88EU_AP_MODE=y
+CONFIG_88PM886_GPADC=m
+CONFIG_A11Y_BRAILLE_CONSOLE=y
+CONFIG_AB8500_CORE=y
+CONFIG_ABP060MG=m
+CONFIG_ABX500_CORE=y
+CONFIG_AC97_BUS=m
+CONFIG_ACPI_FPDT=y
+CONFIG_AD2S1200=m
+CONFIG_AD2S1210=m
+CONFIG_AD2S90=m
+CONFIG_AD3552R=m
+CONFIG_AD4000=m
+CONFIG_AD4030=m
+CONFIG_AD4080=m
+CONFIG_AD4130=m
+CONFIG_AD4170_4=m
+CONFIG_AD4695=m
+CONFIG_AD4851=m
+CONFIG_AD5064=m
+CONFIG_AD5110=m
+CONFIG_AD525X_DPOT_I2C=m
+CONFIG_AD525X_DPOT=m
+CONFIG_AD525X_DPOT_SPI=m
+CONFIG_AD5272=m
+CONFIG_AD5360=m
+CONFIG_AD5380=m
+CONFIG_AD5421=m
+CONFIG_AD5446=m
+CONFIG_AD5449=m
+CONFIG_AD5504=m
+CONFIG_AD5592R_BASE=m
+CONFIG_AD5592R=m
+CONFIG_AD5593R=m
+CONFIG_AD5624R_SPI=m
+CONFIG_AD5686=m
+CONFIG_AD5686_SPI=m
+CONFIG_AD5696_I2C=m
+CONFIG_AD5755=m
+CONFIG_AD5758=m
+CONFIG_AD5761=m
+CONFIG_AD5764=m
+CONFIG_AD5766=m
+CONFIG_AD5770R=m
+CONFIG_AD5791=m
+CONFIG_AD5933=m
+CONFIG_AD7091R5=m
+CONFIG_AD7091R8=m
+CONFIG_AD7124=m
+CONFIG_AD7150=m
+CONFIG_AD7173=m
+CONFIG_AD7191=m
+CONFIG_AD7192=m
+CONFIG_AD7266=m
+CONFIG_AD7280=m
+CONFIG_AD7291=m
+CONFIG_AD7292=m
+CONFIG_AD7293=m
+CONFIG_AD7298=m
+CONFIG_AD7303=m
+CONFIG_AD7380=m
+CONFIG_AD7405=m
+CONFIG_AD74115=m
+CONFIG_AD74413R=m
+CONFIG_AD7476=m
+CONFIG_AD7606_IFACE_PARALLEL=m
+CONFIG_AD7606_IFACE_SPI=m
+CONFIG_AD7606=m
+CONFIG_AD7746=m
+CONFIG_AD7766=m
+CONFIG_AD7768_1=m
+CONFIG_AD7780=m
+CONFIG_AD7791=m
+CONFIG_AD7793=m
+CONFIG_AD7816=m
+CONFIG_AD7887=m
+CONFIG_AD7923=m
+CONFIG_AD7944=m
+CONFIG_AD7949=m
+CONFIG_AD799X=m
+CONFIG_AD8366=m
+CONFIG_AD8801=m
+CONFIG_AD9467=m
+CONFIG_AD9523=m
+CONFIG_AD9739A=m
+CONFIG_AD9832=m
+CONFIG_AD9834=m
+CONFIG_ADA4250=m
+CONFIG_ADE7854_I2C=m
+CONFIG_ADE7854=m
+CONFIG_ADE7854_SPI=m
+CONFIG_ADE9000=m
+CONFIG_ADF4350=m
+CONFIG_ADF4371=m
+CONFIG_ADF4377=m
+CONFIG_ADI_AXI_ADC=m
+CONFIG_ADI_AXI_DAC=m
+CONFIG_ADI_I3C_MASTER=m
+CONFIG_ADIN1100_PHY=m
+CONFIG_ADIN1110=m
+CONFIG_ADIN_PHY=m
+CONFIG_ADIS16080=m
+CONFIG_ADIS16130=m
+CONFIG_ADIS16136=m
+CONFIG_ADIS16201=m
+CONFIG_ADIS16203=m
+CONFIG_ADIS16209=m
+CONFIG_ADIS16240=m
+CONFIG_ADIS16260=m
+CONFIG_ADIS16400=m
+CONFIG_ADIS16460=m
+CONFIG_ADIS16475=m
+CONFIG_ADIS16480=m
+CONFIG_ADIS16550=m
+CONFIG_ADJD_S311=m
+CONFIG_ADM8211=m
+CONFIG_ADMFM2000=m
+CONFIG_ADMV1013=m
+CONFIG_ADMV1014=m
+CONFIG_ADMV4420=m
+CONFIG_ADMV8818=m
+CONFIG_ADRF6780=m
+CONFIG_AD_SIGMA_DELTA=m
+CONFIG_ADT7316_I2C=m
+CONFIG_ADT7316=m
+CONFIG_ADT7316_SPI=m
+CONFIG_ADUX1020=m
+CONFIG_ADXL313_I2C=m
+CONFIG_ADXL313_SPI=m
+CONFIG_ADXL355_I2C=m
+CONFIG_ADXL355_SPI=m
+CONFIG_ADXL367_I2C=m
+CONFIG_ADXL367_SPI=m
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372=m
+CONFIG_ADXL372_SPI=m
+CONFIG_ADXL380_I2C=m
+CONFIG_ADXL380_SPI=m
+CONFIG_ADXRS290=m
+CONFIG_ADXRS450=m
+CONFIG_AEABI=y
+CONFIG_AF8133J=m
+CONFIG_AFE4403=m
+CONFIG_AFE4404=m
+CONFIG_AF_KCM=m
+CONFIG_AF_RXRPC=m
+CONFIG_AHCI_BRCM=m
+CONFIG_AHCI_CEVA=m
+CONFIG_AHCI_DWC=m
+CONFIG_AHCI_QORIQ=m
+CONFIG_AIC79XX_CMDS_PER_DEVICE=4
+CONFIG_AIC79XX_DEBUG_MASK=0
+CONFIG_AIC79XX_RESET_DELAY_MS=15000
+CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
+CONFIG_AIC7XXX_DEBUG_MASK=0
+CONFIG_AIC7XXX_RESET_DELAY_MS=15000
+CONFIG_AIRO_CS=m
+CONFIG_AIROHA_CPU_PM_DOMAIN=m
+CONFIG_AIRO=m
+CONFIG_AK09911=m
+CONFIG_AK8975=m
+CONFIG_AL3000A=m
+CONFIG_AL3010=m
+CONFIG_AL3320A=m
+CONFIG_ALIBABA_UNCORE_DRW_PMU=m
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ALIM7101_WDT=m
+CONFIG_ALPINE_MSI=y
+CONFIG_ALTERA_FREEZE_BRIDGE=m
+CONFIG_ALTERA_MBOX=m
+CONFIG_ALTERA_MSGDMA=m
+CONFIG_ALTERA_PR_IP_CORE=m
+CONFIG_ALTERA_STAPL=m
+CONFIG_AM2315=m
+CONFIG_AM335X_CONTROL_USB=m
+CONFIG_AM335X_PHY_USB=m
+CONFIG_AMD_PHY=m
+CONFIG_AMD_QDMA=m
+CONFIG_AMLOGIC_THERMAL=y
+CONFIG_AMT=m
+CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
+CONFIG_ANDROID_BINDERFS=y
+CONFIG_ANDROID_BINDER_IPC=m
+CONFIG_ANDROID=y
+CONFIG_AOSONG_AGS02MA=m
+CONFIG_APDS9160=m
+CONFIG_APDS9300=m
+CONFIG_APDS9306=m
+CONFIG_APDS9802ALS=m
+CONFIG_APDS9960=m
+CONFIG_APPLE_ADMAC=m
+CONFIG_APPLE_MFI_FASTCHARGE=m
+CONFIG_APPLICOM=m
+CONFIG_AQUANTIA_PHY=m
+CONFIG_AR5523=m
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_ACTIONS=y
+CONFIG_ARCH_ALPINE=y
+CONFIG_ARCH_ARTPEC=y
+CONFIG_ARCH_ASPEED=y
+CONFIG_ARCH_AT91=y
+CONFIG_ARCH_ATLAS6=y
+CONFIG_ARCH_ATLAS7=y
+CONFIG_ARCH_BCMBCA_BRAHMAB15=y
+CONFIG_ARCH_BCMBCA_CORTEXA7=y
+CONFIG_ARCH_BCMBCA_CORTEXA9=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BERLIN=y
+CONFIG_ARCH_DIGICOLOR=y
+CONFIG_ARCH_EXYNOS3=y
+CONFIG_ARCH_EXYNOS4=y
+CONFIG_ARCH_EXYNOS5=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_FORCE_MAX_ORDER=12
+CONFIG_ARCH_HAS_BANDGAP=y
+CONFIG_ARCH_HAS_BINFMT_FLAT=y
+CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_ARCH_HAS_KEEPINITRD=y
+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
+CONFIG_ARCH_HAS_PHYS_TO_DMA=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
+CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
 CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-
-#
-# Timers subsystem
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ_COMMON=y
-# CONFIG_HZ_PERIODIC is not set
-CONFIG_NO_HZ_IDLE=y
-# CONFIG_NO_HZ_FULL is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
-# end of Timers subsystem
-
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_COUNT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_DYNAMIC=y
-CONFIG_SCHED_CORE=y
-
-#
-# CPU/Task time and stats accounting
-#
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_SCHED_AVG_IRQ=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_PSI=y
-# CONFIG_PSI_DEFAULT_DISABLED is not set
-# end of CPU/Task time and stats accounting
-
-CONFIG_CPU_ISOLATION=y
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-CONFIG_PREEMPT_RCU=y
-# CONFIG_RCU_EXPERT is not set
-CONFIG_SRCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TASKS_RCU_GENERIC=y
-CONFIG_TASKS_RCU=y
-CONFIG_TASKS_RUDE_RCU=y
-CONFIG_TASKS_TRACE_RCU=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RCU_NEED_SEGCBLIST=y
-# end of RCU Subsystem
-
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-# CONFIG_IKHEADERS is not set
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
-CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
-CONFIG_GENERIC_SCHED_CLOCK=y
-
-#
-# Scheduler features
-#
-# CONFIG_UCLAMP_TASK is not set
-# end of Scheduler features
-
-CONFIG_CGROUPS=y
-CONFIG_PAGE_COUNTER=y
-CONFIG_MEMCG=y
-CONFIG_MEMCG_SWAP=y
-CONFIG_MEMCG_KMEM=y
-CONFIG_BLK_CGROUP=y
-CONFIG_CGROUP_WRITEBACK=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_CFS_BANDWIDTH=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_CGROUP_PIDS=y
-CONFIG_CGROUP_RDMA=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CPUSETS=y
-CONFIG_PROC_PID_CPUSET=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_PERF=y
-CONFIG_CGROUP_BPF=y
-CONFIG_CGROUP_MISC=y
-# CONFIG_CGROUP_DEBUG is not set
-CONFIG_SOCK_CGROUP_DATA=y
-CONFIG_NAMESPACES=y
-CONFIG_UTS_NS=y
-CONFIG_IPC_NS=y
-CONFIG_USER_NS=y
-CONFIG_PID_NS=y
-CONFIG_NET_NS=y
-CONFIG_CHECKPOINT_RESTORE=y
-CONFIG_SCHED_AUTOGROUP=y
-# CONFIG_SYSFS_DEPRECATED is not set
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-CONFIG_RD_XZ=y
-# CONFIG_RD_LZO is not set
-# CONFIG_RD_LZ4 is not set
-CONFIG_RD_ZSTD=y
-CONFIG_BOOT_CONFIG=y
-# CONFIG_CC_OPTIMIZE_BASAL is not set
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_HAVE_UID16=y
-CONFIG_BPF=y
-CONFIG_EXPERT=y
-CONFIG_UID16=y
-CONFIG_MULTIUSER=y
-CONFIG_SGETMASK_SYSCALL=y
-# CONFIG_SYSFS_SYSCALL is not set
-CONFIG_FHANDLE=y
-CONFIG_POSIX_TIMERS=y
-CONFIG_PRINTK=y
-CONFIG_PRINTK_NMI=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_FUTEX_PI=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_IO_URING=y
-CONFIG_ADVISE_SYSCALLS=y
-CONFIG_MEMBARRIER=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_BASE_RELATIVE=y
-CONFIG_BPF_SYSCALL=y
-CONFIG_BPF_JIT_ALWAYS_ON=y
-# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
-CONFIG_BPF_JIT_DEFAULT_ON=y
-CONFIG_USERMODE_DRIVER=y
-# CONFIG_BPF_PRELOAD is not set
-CONFIG_USERFAULTFD=y
-CONFIG_LRU_GEN=y
-CONFIG_LRU_GEN_ENABLED=y
-# CONFIG_LRU_GEN_STATS is not set
-CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
-CONFIG_RSEQ=y
-# CONFIG_DEBUG_RSEQ is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-# CONFIG_PC104 is not set
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_PERF_EVENTS=y
-# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
-# end of Kernel Performance Events And Counters
-
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_SLUB_MEMCG_SYSFS_ON is not set
-# CONFIG_COMPAT_BRK is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-CONFIG_SLAB_MERGE_DEFAULT=y
-CONFIG_SLAB_FREELIST_RANDOM=y
-CONFIG_SLAB_FREELIST_HARDENED=y
-CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
-CONFIG_SLUB_CPU_PARTIAL=y
-CONFIG_SYSTEM_DATA_VERIFICATION=y
-# CONFIG_PROFILING is not set
-CONFIG_TRACEPOINTS=y
-# end of General setup
-
-CONFIG_ARM=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_HAVE_TCM=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_NO_IOPORT_MAP=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_ARCH_HAS_BANDGAP=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ZONE_DMA=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_GENERIC_BUG=y
-CONFIG_PGTABLE_LEVELS=3
-
-#
-# System Type
-#
-CONFIG_MMU=y
-CONFIG_ARCH_MMAP_RND_BITS_MIN=8
-CONFIG_ARCH_MMAP_RND_BITS_MAX=16
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_BCM=y
-CONFIG_ARCH_NXP=y
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_DOVE is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C24XX is not set
-# CONFIG_ARCH_OMAP1 is not set
-# CONFIG_ARCH_AIROHA is not set
-
-#
-# Multiple platform selection
-#
-
-#
-# CPU Core family selection
-#
-# CONFIG_ARCH_MULTI_V6 is not set
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MULTI_V6_V7=y
-# end of Multiple platform selection
-
-# CONFIG_ARCH_VIRT is not set
-CONFIG_ARCH_ACTIONS=y
-CONFIG_ARCH_ALPINE=y
-CONFIG_ARCH_APPLE=y
-CONFIG_ARCH_INTEL_SOCFPGA=y
-CONFIG_ARCH_ARTPEC=y
-# CONFIG_MACH_ARTPEC6 is not set
-CONFIG_ARCH_ASPEED=y
-# CONFIG_MACH_ASPEED_G6 is not set
-CONFIG_ARCH_AT91=y
-# CONFIG_SOC_SAMA5D2 is not set
-# CONFIG_SOC_SAMA5D3 is not set
-# CONFIG_SOC_SAMA5D4 is not set
-
-#
-# Clocksource driver selection
-#
-# CONFIG_ATMEL_CLOCKSOURCE_TCB is not set
-CONFIG_COMMON_CLK_AT91=y
-# CONFIG_ARCH_AXXIA is not set
-CONFIG_ARCH_BCM=y
-
-#
-# IPROC architected SoCs
-#
-# CONFIG_ARCH_BCM_CYGNUS is not set
-# CONFIG_ARCH_BCM_HR2 is not set
-# CONFIG_ARCH_BCM_NSP is not set
-# CONFIG_ARCH_BCM_5301X is not set
-
-#
-# KONA architected SoCs
-#
-# CONFIG_ARCH_BCM_281XX is not set
-# CONFIG_ARCH_BCM_21664 is not set
-# CONFIG_ARCH_BCM_23550 is not set
-
-#
-# Other Architectures
-#
-# CONFIG_ARCH_BCM2835 is not set
-# CONFIG_ARCH_BCM_53573 is not set
-# CONFIG_ARCH_BCM_63XX is not set
-# CONFIG_ARCH_BRCMSTB is not set
-CONFIG_ARCH_BERLIN=y
-# CONFIG_MACH_BERLIN_BG2 is not set
-# CONFIG_MACH_BERLIN_BG2CD is not set
-# CONFIG_MACH_BERLIN_BG2Q is not set
-CONFIG_ARCH_DIGICOLOR=y
-CONFIG_ARCH_EXYNOS=y
-CONFIG_S5P_DEV_MFC=y
-CONFIG_ARCH_EXYNOS3=y
-CONFIG_ARCH_EXYNOS4=y
-CONFIG_ARCH_EXYNOS5=y
-
-#
-# Exynos SoCs
-#
-CONFIG_SOC_EXYNOS3250=y
-CONFIG_CPU_EXYNOS4210=y
-CONFIG_SOC_EXYNOS4412=y
-CONFIG_SOC_EXYNOS5250=y
-CONFIG_SOC_EXYNOS5260=y
-CONFIG_SOC_EXYNOS5410=y
-CONFIG_SOC_EXYNOS5420=y
-CONFIG_SOC_EXYNOS5800=y
-CONFIG_EXYNOS_MCPM=y
-CONFIG_EXYNOS_CPU_SUSPEND=y
-CONFIG_ARCH_HIGHBANK=y
-CONFIG_ARCH_HISI=y
-
-#
-# Hisilicon platform type
-#
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
 CONFIG_ARCH_HI3xxx=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_HIP01=y
 CONFIG_ARCH_HIP04=y
+CONFIG_ARCH_HISI=y
 CONFIG_ARCH_HIX5HD2=y
-# end of Hisilicon platform type
-
-CONFIG_ARCH_MXC=y
-CONFIG_HAVE_IMX_SRC=y
-
-#
-# Cortex-A platforms
-#
-# CONFIG_SOC_IMX50 is not set
-# CONFIG_SOC_IMX51 is not set
-# CONFIG_SOC_IMX53 is not set
-# CONFIG_SOC_IMX6Q is not set
-# CONFIG_SOC_IMX6SL is not set
-# CONFIG_SOC_IMX6SLL is not set
-# CONFIG_SOC_IMX6SX is not set
-# CONFIG_SOC_IMX6UL is not set
-# CONFIG_SOC_LS1021A is not set
-
-#
-# Cortex-A/Cortex-M asymmetric multiprocessing platforms
-#
-# CONFIG_SOC_IMX7D is not set
-# CONFIG_SOC_IMX7ULP is not set
-# CONFIG_SOC_VF610 is not set
+CONFIG_ARCH_HPE_GXP=y
+CONFIG_ARCH_HPE=y
+CONFIG_ARCH_INTEL_SOCFPGA=y
+CONFIG_ARCH_IPQ40XX=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
 CONFIG_ARCH_KEYSTONE=y
+CONFIG_ARCH_MDM9615=y
 CONFIG_ARCH_MEDIATEK=y
-CONFIG_MACH_MT2701=y
-CONFIG_MACH_MT6589=y
-CONFIG_MACH_MT6592=y
-CONFIG_MACH_MT7623=y
-CONFIG_MACH_MT7629=y
-CONFIG_MACH_MT8127=y
-CONFIG_MACH_MT8135=y
 CONFIG_ARCH_MESON=y
-CONFIG_MACH_MESON6=y
-CONFIG_MACH_MESON8=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
 CONFIG_ARCH_MILBEAUT=y
-# CONFIG_ARCH_MILBEAUT_M10V is not set
+CONFIG_ARCH_MMAP_RND_BITS=8
+CONFIG_ARCH_MMAP_RND_BITS_MAX=16
+CONFIG_ARCH_MMAP_RND_BITS_MIN=8
 CONFIG_ARCH_MMP=y
-
-#
-# Marvell PXA168/910/MMP2 Implementations
-#
-# CONFIG_MACH_BROWNSTONE is not set
-# CONFIG_MACH_FLINT is not set
-# CONFIG_MACH_MARVELL_JASPER is not set
-# CONFIG_MACH_MMP2_DT is not set
-# CONFIG_MACH_MMP3_DT is not set
-# end of Marvell PXA168/910/MMP2 Implementations
-
+CONFIG_ARCH_MSM8909=y
+CONFIG_ARCH_MSM8916=y
+CONFIG_ARCH_MSM8960=y
+CONFIG_ARCH_MSM8974=y
+CONFIG_ARCH_MSM8X60=y
 CONFIG_ARCH_MSTARV7=y
-CONFIG_MACH_INFINITY=y
-CONFIG_MACH_MERCURY=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
 CONFIG_ARCH_MVEBU=y
-# CONFIG_MACH_ARMADA_370 is not set
-# CONFIG_MACH_ARMADA_375 is not set
-# CONFIG_MACH_ARMADA_38X is not set
-# CONFIG_MACH_ARMADA_39X is not set
-# CONFIG_MACH_ARMADA_XP is not set
-# CONFIG_MACH_DOVE is not set
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
 CONFIG_ARCH_NPCM=y
-# CONFIG_ARCH_NPCM7XX is not set
-CONFIG_ARCH_OMAP=y
-
-#
-# TI OMAP Common Features
-#
-
-#
-# OMAP Feature Selections
-#
-# CONFIG_POWER_AVS_OMAP is not set
-# CONFIG_OMAP_RESET_CLOCKS is not set
-CONFIG_OMAP_32K_TIMER=y
-# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
-# end of TI OMAP Common Features
-
-CONFIG_MACH_OMAP_GENERIC=y
-
-#
-# TI OMAP/AM/DM/DRA Family
-#
+CONFIG_ARCH_NR_GPIO=2048
+CONFIG_ARCH_NXP=y
+CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
+CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_ARCH_OMAP3=y
 CONFIG_ARCH_OMAP4=y
-CONFIG_SOC_OMAP5=y
-CONFIG_SOC_AM33XX=y
-CONFIG_SOC_AM43XX=y
-CONFIG_SOC_DRA7XX=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP_INTERCONNECT_BARRIER=y
-
-#
-# TI OMAP2/3/4 Specific Features
-#
-CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
-CONFIG_SOC_HAS_OMAP2_SDRC=y
-CONFIG_SOC_HAS_REALTIME_COUNTER=y
-CONFIG_SOC_OMAP3430=y
-CONFIG_SOC_TI81XX=y
-CONFIG_OMAP_PACKAGE_CBB=y
-
-#
-# OMAP Legacy Platform Data Board Type
-#
-CONFIG_MACH_OMAP3517EVM=y
-CONFIG_MACH_OMAP3_PANDORA=y
-CONFIG_OMAP3_SDRC_AC_TIMING=y
-# end of TI OMAP2/3/4 Specific Features
-
-# CONFIG_OMAP5_ERRATA_801819 is not set
-# end of TI OMAP/AM/DM/DRA Family
-
-CONFIG_ARCH_SIRF=y
-
-#
-# CSR SiRF atlas6/primaII/Atlas7 Specific Features
-#
-CONFIG_ARCH_ATLAS6=y
-CONFIG_ARCH_ATLAS7=y
+CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_PENSANDO=y
 CONFIG_ARCH_PRIMA2=y
-CONFIG_SIRF_IRQ=y
-CONFIG_PXA_SSP=m
+CONFIG_ARCH_QCOM_RESERVE_SMEM=y
 CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_IPQ40XX=y
-CONFIG_ARCH_MSM8X60=y
-CONFIG_ARCH_MSM8960=y
-CONFIG_ARCH_MSM8974=y
-CONFIG_ARCH_MDM9615=y
 CONFIG_ARCH_RDA=y
 CONFIG_ARCH_REALTEK=y
 CONFIG_ARCH_REALVIEW=y
-CONFIG_MACH_REALVIEW_EB=y
-CONFIG_REALVIEW_EB_A9MP=y
-CONFIG_MACH_REALVIEW_PBA8=y
-CONFIG_MACH_REALVIEW_PBX=y
+CONFIG_ARCH_RENESAS=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ARCH_S5PV210=y
-CONFIG_CPU_S5PV210=y
-CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SIRF=y
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_SOCFPGA_SUSPEND=y
-CONFIG_PLAT_SPEAR=y
 CONFIG_ARCH_SPEAR13XX=y
-CONFIG_MACH_SPEAR1310=y
-CONFIG_MACH_SPEAR1340=y
 CONFIG_ARCH_STI=y
-CONFIG_SOC_STIH415=y
-CONFIG_SOC_STIH416=y
-CONFIG_SOC_STIH407=y
 CONFIG_ARCH_STM32=y
-CONFIG_MACH_STM32MP157=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
-CONFIG_MACH_SUN5I=y
-CONFIG_MACH_SUN6I=y
-CONFIG_MACH_SUN7I=y
-CONFIG_MACH_SUN8I=y
-CONFIG_MACH_SUN9I=y
+CONFIG_ARCH_SUNPLUS=y
 CONFIG_ARCH_SUNXI_MC_SMP=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
 CONFIG_ARCH_TANGO=y
 CONFIG_ARCH_TEGRA=y
-CONFIG_ARCH_UNIPHIER=y
 CONFIG_ARCH_U8500=y
-CONFIG_UX500_SOC_DB8500=y
-CONFIG_UX500_DEBUG_UART=2
-CONFIG_ARCH_VEXPRESS=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
 CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y
-# CONFIG_ARCH_VEXPRESS_DCSCB is not set
-# CONFIG_ARCH_VEXPRESS_SPC is not set
-# CONFIG_ARCH_VEXPRESS_TC2_PM is not set
+CONFIG_ARCH_VEXPRESS=y
 CONFIG_ARCH_VT8500=y
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
 CONFIG_ARCH_WM8850=y
 CONFIG_ARCH_ZX=y
-CONFIG_SOC_ZX296702=y
 CONFIG_ARCH_ZYNQ=y
+CONFIG_ARCNET_1051=m
+CONFIG_ARCNET_1201=m
+CONFIG_ARCNET_CAP=m
+CONFIG_ARCNET_COM20020_CS=m
+CONFIG_ARCNET_COM20020=m
+CONFIG_ARCNET_COM20020_PCI=m
+CONFIG_ARCNET_COM90xxIO=m
+CONFIG_ARCNET_COM90xx=m
+CONFIG_ARCNET=m
+CONFIG_ARCNET_RAW=m
+CONFIG_ARCNET_RIM_I=m
 CONFIG_ARM64_EPAN=y
-CONFIG_PLAT_ORION=y
-CONFIG_PLAT_PXA=y
-CONFIG_PLAT_VERSATILE=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_V7=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_LPAE=y
-CONFIG_ARM_PV_FIXUP=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_SWP_EMULATE=y
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_ENDIAN_BE8=y
-CONFIG_CPU_ICACHE_DISABLE=y
-CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y
-CONFIG_CPU_BPREDICT_DISABLE=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDEN_BRANCH_HISTORY=y
-CONFIG_KUSER_HELPERS=y
-CONFIG_VDSO=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_CACHE_FEROCEON_L2=y
-# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_CACHE_L2X0=y
-# CONFIG_CACHE_L2X0_PMU is not set
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_PL310_ERRATA_727915=y
-CONFIG_PL310_ERRATA_753970=y
-CONFIG_PL310_ERRATA_769419=y
-CONFIG_CACHE_UNIPHIER=y
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_L1_CACHE_SHIFT_7=y
-CONFIG_ARM_L1_CACHE_SHIFT=7
-CONFIG_ARM_DMA_MEM_BUFFERABLE=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_ARM_ERRATA_430973=y
-CONFIG_ARM_ERRATA_643719=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_754327=y
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_ARM_ERRATA_798181=y
-CONFIG_ARM_ERRATA_773022=y
-CONFIG_ARM_ERRATA_818325_852422=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_AT91_CPUIDLE=y
+CONFIG_ARM_CCI400_COMMON=y
+CONFIG_ARM_CCI400_PMU=y
+CONFIG_ARM_CCI400_PORT_CTRL=y
+CONFIG_ARM_CCI5xx_PMU=y
+CONFIG_ARM_CCI_PMU=m
+CONFIG_ARM_CCI=y
+CONFIG_ARM_CCN=m
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_CPU_TOPOLOGY=y
+CONFIG_ARM_CRYPTO=y
+CONFIG_ARM_DMA350=m
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764319=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_773022=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_ERRATA_798181=y
+CONFIG_ARM_ERRATA_814220=y
+CONFIG_ARM_ERRATA_818325_852422=y
 CONFIG_ARM_ERRATA_821420=y
 CONFIG_ARM_ERRATA_825619=y
-CONFIG_ARM_ERRATA_857271=y
 CONFIG_ARM_ERRATA_852421=y
 CONFIG_ARM_ERRATA_852423=y
+CONFIG_ARM_ERRATA_857271=y
 CONFIG_ARM_ERRATA_857272=y
-# end of System Type
-
-#
-# Bus support
-#
-CONFIG_ARM_ERRATA_814220=y
-# end of Bus support
-
-#
-# Kernel Features
-#
-CONFIG_HAVE_SMP=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_ARM_CPU_TOPOLOGY=y
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_SMT=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-CONFIG_HAVE_ARM_TWD=y
-CONFIG_MCPM=y
-CONFIG_MCPM_QUAD_CLUSTER=y
-CONFIG_BIG_LITTLE=y
-# CONFIG_BL_SWITCHER is not set
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_NR_CPUS=32
-CONFIG_HOTPLUG_CPU=y
-CONFIG_ARM_PSCI=y
-CONFIG_ARCH_NR_GPIO=2048
-CONFIG_HZ_FIXED=0
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_200 is not set
-# CONFIG_HZ_250 is not set
-CONFIG_HZ_300=y
-# CONFIG_HZ_500 is not set
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=300
-CONFIG_ARCH_FORCE_MAX_ORDER=12
-CONFIG_SCHED_HRTICK=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HW_PERF_EVENTS=y
-CONFIG_SYS_SUPPORTS_HUGETLBFS=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARM_MODULE_PLTS=y
-CONFIG_FORCE_MAX_ZONEORDER=11
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-CONFIG_PARAVIRT=y
-# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
-# CONFIG_XEN is not set
-CONFIG_STACKPROTECTOR_PER_TASK=y
-# end of Kernel Features
-
-#
-# Boot options
-#
-CONFIG_USE_OF=y
-CONFIG_ATAGS=y
-# CONFIG_DEPRECATED_PARAM_STRUCT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-# CONFIG_ARM_APPENDED_DTB is not set
-CONFIG_CMDLINE=""
-CONFIG_KEXEC=y
-CONFIG_ATAGS_PROC=y
-# CONFIG_CRASH_DUMP is not set
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_EFI=y
-CONFIG_DMI=y
-CONFIG_DMIID=y
-CONFIG_DMI_SYSFS=m
-CONFIG_SYSFB_SIMPLEFB=y
-CONFIG_EFI_VARS_PSTORE=m
-# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
-CONFIG_EFI_ARMSTUB_DTB_LOADER=y
-CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
-CONFIG_EFI_BOOTLOADER_CONTROL=m
-CONFIG_EFI_CAPSULE_LOADER=m
-CONFIG_EFI_TEST=m
-CONFIG_RESET_ATTACK_MITIGATION=y
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-# end of Boot options
-
-#
-# CPU Power Management
-#
-
-#
-# CPU Frequency scaling
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-
-#
-# CPU frequency scaling drivers
-#
-CONFIG_CPUFREQ_DT=m
-CONFIG_CPUFREQ_DT_PLATDEV=y
-# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set
-# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set
+CONFIG_ARM_GIC_MAX_NR=2
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GLOBAL_TIMER=y
+CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_HEAVY_MB=y
 CONFIG_ARM_HIGHBANK_CPUFREQ=m
-# CONFIG_ARM_IMX_CPUFREQ_DT is not set
-# CONFIG_ARM_MEDIATEK_CPUFREQ is not set
+CONFIG_ARM_HIGHBANK_CPUIDLE=y
+CONFIG_ARM_KPROBES_TEST=m
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_L1_CACHE_SHIFT=7
+CONFIG_ARM_L1_CACHE_SHIFT_7=y
+CONFIG_ARM_LPAE=y
+CONFIG_ARM_MEDIATEK_CPUFREQ_HW=m
+CONFIG_ARM_MHU_V2=m
+CONFIG_ARM_MHU_V3=m
+CONFIG_ARM_MODULE_PLTS=y
 CONFIG_ARM_OMAP2PLUS_CPUFREQ=y
-# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
+CONFIG_ARM_PAN=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PMUV3=y
+CONFIG_ARM_PMU=y
+CONFIG_ARM_PSCI_CHECKER=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_PTDUMP_CORE=y
+CONFIG_ARM_PV_FIXUP=y
 CONFIG_ARM_S5PV210_CPUFREQ=y
-# CONFIG_ARM_SCMI_CPUFREQ is not set
+CONFIG_ARM_SCMI_PERF_DOMAIN=m
+CONFIG_ARM_SCMI_POWERCAP=m
+CONFIG_ARM_SCMI_POWER_CONTROL=m
+CONFIG_ARM_SCMI_POWER_DOMAIN=m
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SCMI_QUIRKS=y
+CONFIG_ARM_SCMI_RAW_MODE_SUPPORT_COEX=y
+CONFIG_ARM_SCMI_RAW_MODE_SUPPORT=y
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE=y
+CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y
+CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=m
+CONFIG_ARM_SCPI_PROTOCOL=m
+CONFIG_ARM_SMCCC_SOC_ID=y
+CONFIG_ARM_SMC_WATCHDOG=m
 CONFIG_ARM_SPEAR_CPUFREQ=y
-# CONFIG_ARM_STI_CPUFREQ is not set
+CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
 CONFIG_ARM_TANGO_CPUFREQ=y
-CONFIG_ARM_TEGRA20_CPUFREQ=m
 CONFIG_ARM_TEGRA124_CPUFREQ=y
+CONFIG_ARM_TEGRA20_CPUFREQ=m
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_THUMB=y
 CONFIG_ARM_TI_CPUFREQ=y
-# end of CPU Frequency scaling
-
-#
-# CPU Idle
-#
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-# CONFIG_CPU_IDLE_GOV_TEO is not set
-CONFIG_DT_IDLE_STATES=y
-
-#
-# ARM CPU Idle Drivers
-#
-CONFIG_ARM_CPUIDLE=y
-CONFIG_ARM_PSCI_CPUIDLE=y
-CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
-# CONFIG_ARM_BIG_LITTLE_CPUIDLE is not set
-CONFIG_ARM_HIGHBANK_CPUIDLE=y
-# CONFIG_ARM_ZYNQ_CPUIDLE is not set
-# CONFIG_ARM_U8500_CPUIDLE is not set
-CONFIG_ARM_AT91_CPUIDLE=y
-# CONFIG_ARM_EXYNOS_CPUIDLE is not set
-# CONFIG_ARM_MVEBU_V7_CPUIDLE is not set
-# CONFIG_ARM_TEGRA_CPUIDLE is not set
-# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
-# end of ARM CPU Idle Drivers
-
-CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
-# end of CPU Idle
-# end of CPU Power Management
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_NEON=y
-CONFIG_KERNEL_MODE_NEON=y
-# end of Floating point emulation
-
-#
-# Power management options
-#
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_SUSPEND_SKIP_SYNC is not set
-CONFIG_HIBERNATE_CALLBACKS=y
-CONFIG_HIBERNATION=y
-CONFIG_HIBERNATION_SNAPSHOT_DEV=y
-CONFIG_PM_STD_PARTITION=""
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_PM_AUTOSLEEP=y
-CONFIG_PM_WAKELOCKS=y
-CONFIG_PM_WAKELOCKS_LIMIT=100
-CONFIG_PM_WAKELOCKS_GC=y
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-# CONFIG_APM_EMULATION is not set
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_CPU_PM=y
-CONFIG_ENERGY_MODEL=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-# end of Power management options
-
-#
-# Firmware Drivers
-#
-CONFIG_ARM_SCMI_PROTOCOL=y
-CONFIG_ARM_SCMI_POWER_DOMAIN=m
-CONFIG_ARM_SCPI_PROTOCOL=m
-CONFIG_ARM_SCPI_POWER_DOMAIN=m
-CONFIG_FIRMWARE_MEMMAP=y
-CONFIG_QCOM_SCM=y
-# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-# CONFIG_TRUSTED_FOUNDATIONS is not set
-# CONFIG_TURRIS_MOX_RWTM is not set
-CONFIG_GOOGLE_FIRMWARE=y
-CONFIG_GOOGLE_COREBOOT_TABLE=m
-CONFIG_GOOGLE_MEMCONSOLE=m
-CONFIG_GOOGLE_FRAMEBUFFER_COREBOOT=m
-CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m
-CONFIG_GOOGLE_VPD=m
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ARM_PSCI_CHECKER=y
-CONFIG_HAVE_ARM_SMCCC=y
-CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
-CONFIG_ARM_SMCCC_SOC_ID=y
-
-#
-# Tegra firmware driver
-#
-# CONFIG_TEGRA_IVC is not set
-# end of Tegra firmware driver
-# end of Firmware Drivers
-
-CONFIG_ARM_CRYPTO=y
-CONFIG_CRYPTO_SHA1_ARM=m
-CONFIG_CRYPTO_SHA1_ARM_NEON=m
-CONFIG_CRYPTO_SHA1_ARM_CE=m
-CONFIG_CRYPTO_SHA2_ARM_CE=m
-CONFIG_CRYPTO_SHA256_ARM=m
-CONFIG_CRYPTO_SHA512_ARM=m
-CONFIG_CRYPTO_AES_ARM=m
-CONFIG_CRYPTO_AES_ARM_BS=m
-CONFIG_CRYPTO_AES_ARM_CE=m
-CONFIG_CRYPTO_GHASH_ARM_CE=m
-CONFIG_CRYPTO_CRCT10DIF_ARM_CE=m
-CONFIG_CRYPTO_CRC32_ARM_CE=m
-CONFIG_CRYPTO_CHACHA20_NEON=m
-CONFIG_CRYPTO_POLY1305_ARM=m
-CONFIG_CRYPTO_NHPOLY1305_NEON=m
-CONFIG_CRYPTO_CURVE25519_NEON=m
-
-#
-# General architecture-dependent options
-#
-CONFIG_CRASH_CORE=y
-CONFIG_KEXEC_CORE=y
-CONFIG_SET_FS=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_KPROBES=y
-# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set
-CONFIG_JUMP_LABEL=y
-# CONFIG_STATIC_KEYS_SELFTEST is not set
-CONFIG_OPTPROBES=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_KRETPROBES=y
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_NMI=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_KEEPINITRD=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_MMU_GATHER_TABLE_FREE=y
-CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_HAVE_ARCH_SECCOMP=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_SECCOMP=y
-# CONFIG_SECCOMP_CACHE_DEBUG is not set
-CONFIG_SECCOMP_FILTER=y
-CONFIG_HAVE_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR_STRONG=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
-CONFIG_HAVE_EXIT_THREAD=y
-CONFIG_ARCH_MMAP_RND_BITS=8
-CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_VMAP_STACK=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_STRICT_MODULE_RWX=y
-CONFIG_ARCH_HAS_PHYS_TO_DMA=y
-# CONFIG_LOCK_EVENT_COUNTS is not set
-# CONFIG_KCSAN is not set
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-# end of GCOV-based kernel profiling
-
-CONFIG_HAVE_GCC_PLUGINS=y
-CONFIG_GCC_PLUGINS=y
-# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
-CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y
-# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
-CONFIG_GCC_PLUGIN_ARM_SSP_PER_TASK=y
-# end of General architecture-dependent options
-CONFIG_RANDSTRUCT_NONE=y
-# CONFIG_RANDSTRUCT_FULL is not set
-# CONFIG_RANDSTRUCT_PERFORMANCE is not set
-
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_MODULE_SIG is not set
-CONFIG_MODULE_COMPRESS_NONE=y
-# CONFIG_MODULE_COMPRESS_GZIP is not set
-# CONFIG_MODULE_COMPRESS_XZ is not set
-# CONFIG_MODULE_COMPRESS_ZSTD is not set
-# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
-CONFIG_MODPROBE_PATH="/sbin/modprobe"
-# CONFIG_TRIM_UNUSED_KSYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_TRIM_UNUSED_KSYMS=y
-CONFIG_UNUSED_KSYMS_WHITELIST=""
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_BLOCK=y
-# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set
-CONFIG_BLK_SCSI_REQUEST=y
-CONFIG_BLK_CGROUP_RWSTAT=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=m
-CONFIG_BLK_DEV_ZONED=y
-CONFIG_BLK_DEV_THROTTLING=y
-# CONFIG_BLK_DEV_THROTTLING_LOW is not set
-CONFIG_BLK_CMDLINE_PARSER=y
-CONFIG_BLK_WBT=y
-CONFIG_BLK_CGROUP_IOLATENCY=y
-# CONFIG_BLK_CGROUP_FC_APPID is not set
-# CONFIG_BLK_CGROUP_IOCOST is not set
-# CONFIG_BLK_CGROUP_IOPRIO is not set
-CONFIG_BLK_WBT_MQ=y
-# CONFIG_BLK_DEBUG_FS is not set
-CONFIG_BLK_DEBUG_FS_ZONED=y
-# CONFIG_BLK_SED_OPAL is not set
-# CONFIG_BLK_INLINE_ENCRYPTION is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_AIX_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_LDM_DEBUG=y
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_CMDLINE_PARTITION=y
-# end of Partition Types
-
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_MQ_RDMA=y
-CONFIG_BLK_PM=y
-
-#
-# IO Schedulers
-#
-CONFIG_MQ_IOSCHED_DEADLINE=y
-CONFIG_MQ_IOSCHED_KYBER=m
-CONFIG_IOSCHED_BFQ=y
-CONFIG_BFQ_GROUP_IOSCHED=y
-# CONFIG_BFQ_CGROUP_DEBUG is not set
-# end of IO Schedulers
-
-CONFIG_PADATA=y
-CONFIG_ASN1=y
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
-CONFIG_FREEZER=y
-
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_ELF_FDPIC is not set
-CONFIG_ELFCORE=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_BINFMT_SCRIPT=y
-CONFIG_ARCH_HAS_BINFMT_FLAT=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-# CONFIG_BINFMT_FLAT_OLD is not set
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_BINFMT_MISC=m
-CONFIG_COREDUMP=y
-# end of Executable file formats
-
-#
-# Memory Management options
-#
-CONFIG_SELECT_MEMORY_MODEL=y
-# CONFIG_FLATMEM_MANUAL is not set
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_STATIC=y
-CONFIG_HAVE_FAST_GUP=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_MEMORY_BALLOON=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_COMPACTION=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_MIGRATION=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_BOUNCE=y
-CONFIG_MMU_NOTIFIER=y
-CONFIG_KSM=y
-CONFIG_UKSM=y
-# CONFIG_KSM_LEGACY is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
-# CONFIG_TRANSPARENT_HUGEPAGE is not set
-CONFIG_CLEANCACHE=y
-CONFIG_FRONTSWAP=y
-CONFIG_CMA=y
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SYSFS=y
-CONFIG_CMA_AREAS=7
-CONFIG_ZSWAP=y
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
-CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
-CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
-CONFIG_ZSWAP_DEFAULT_ON=y
-CONFIG_ZPOOL=y
-CONFIG_ZBUD=y
-CONFIG_Z3FOLD=m
-CONFIG_ZSMALLOC=y
-# CONFIG_ZSMALLOC_PGTABLE_MAPPING is not set
-# CONFIG_ZSMALLOC_STAT is not set
-CONFIG_GENERIC_EARLY_IOREMAP=y
-# CONFIG_IDLE_PAGE_TRACKING is not set
-CONFIG_HMM_MIRROR=y
-CONFIG_FRAME_VECTOR=y
-# CONFIG_PERCPU_STATS is not set
-# CONFIG_GUP_TEST is not set
-# CONFIG_GUP_BENCHMARK is not set
-CONFIG_ARCH_HAS_PTE_SPECIAL=y
-# end of Memory Management options
-
-CONFIG_NET=y
-CONFIG_NET_INGRESS=y
-CONFIG_NET_EGRESS=y
-CONFIG_NET_REDIRECT=y
-CONFIG_SKB_EXTENSIONS=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=m
-CONFIG_PACKET_DIAG=m
-CONFIG_UNIX=y
-CONFIG_UNIX_SCM=y
-CONFIG_UNIX_DIAG=m
-CONFIG_TLS=m
-CONFIG_TLS_DEVICE=y
-# CONFIG_TLS_TOE is not set
-CONFIG_XFRM=y
-CONFIG_XFRM_OFFLOAD=y
-CONFIG_XFRM_ALGO=m
-CONFIG_XFRM_USER=m
-CONFIG_XFRM_INTERFACE=m
-CONFIG_XFRM_SUB_POLICY=y
-CONFIG_XFRM_MIGRATE=y
-CONFIG_XFRM_STATISTICS=y
-CONFIG_XFRM_AH=m
-CONFIG_XFRM_ESP=m
-CONFIG_XFRM_IPCOMP=m
-CONFIG_NET_KEY=m
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_XFRM_ESPINTCP=y
-CONFIG_SMC=m
-CONFIG_SMC_DIAG=m
-CONFIG_XDP_SOCKETS=y
-CONFIG_XDP_SOCKETS_DIAG=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_FIB_TRIE_STATS=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-# CONFIG_IP_ROUTE_VERBOSE is not set
-CONFIG_IP_ROUTE_CLASSID=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE_DEMUX=m
-CONFIG_NET_IP_TUNNEL=m
-CONFIG_NET_IPGRE=m
-CONFIG_NET_IPGRE_BROADCAST=y
-CONFIG_IP_MROUTE_COMMON=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_NET_IPVTI=m
-CONFIG_NET_UDP_TUNNEL=m
-CONFIG_NET_FOU=m
-CONFIG_NET_FOU_IP_TUNNELS=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_ESP_OFFLOAD=m
-CONFIG_INET_ESPINTCP=y
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_TABLE_PERTURB_ORDER=16
-CONFIG_INET_XFRM_TUNNEL=m
-CONFIG_INET_TUNNEL=m
-CONFIG_INET_DIAG=m
-CONFIG_INET_TCP_DIAG=m
-CONFIG_INET_UDP_DIAG=m
-CONFIG_INET_RAW_DIAG=m
-CONFIG_INET_DIAG_DESTROY=y
-CONFIG_TCP_CONG_ADVANCED=y
-CONFIG_TCP_CONG_BIC=m
-CONFIG_TCP_CONG_CUBIC=m
-CONFIG_TCP_CONG_WESTWOOD=m
-CONFIG_TCP_CONG_HTCP=m
-CONFIG_TCP_CONG_HSTCP=m
-CONFIG_TCP_CONG_HYBLA=m
-CONFIG_TCP_CONG_VEGAS=m
-CONFIG_TCP_CONG_NV=m
-CONFIG_TCP_CONG_SCALABLE=m
-CONFIG_TCP_CONG_LP=m
-CONFIG_TCP_CONG_VENO=m
-CONFIG_TCP_CONG_YEAH=m
-CONFIG_TCP_CONG_ILLINOIS=m
-CONFIG_TCP_CONG_DCTCP=m
-# CONFIG_TCP_CONG_CDG is not set
-CONFIG_TCP_CONG_BBR=m
-CONFIG_DEFAULT_RENO=y
-CONFIG_DEFAULT_TCP_CONG="reno"
-CONFIG_TCP_MD5SIG=y
-CONFIG_IPV6=m
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_ESP_OFFLOAD=m
-# CONFIG_INET6_ESPINTCP is not set
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_IPV6_ILA=m
-CONFIG_INET6_XFRM_TUNNEL=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_IPV6_VTI=m
-CONFIG_IPV6_SIT=m
-CONFIG_IPV6_SIT_6RD=y
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_GRE=m
-CONFIG_IPV6_FOU=m
-CONFIG_IPV6_FOU_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-CONFIG_IPV6_MROUTE=y
-CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IPV6_PIMSM_V2=y
-CONFIG_IPV6_SEG6_LWTUNNEL=y
-CONFIG_IPV6_SEG6_HMAC=y
-CONFIG_IPV6_RPL_LWTUNNEL=y
-CONFIG_MPTCP=y
-CONFIG_INET_MPTCP_DIAG=m
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NETWORK_PHY_TIMESTAMPING=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_ADVANCED=y
-CONFIG_BRIDGE_NETFILTER=m
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_INGRESS=y
-CONFIG_NETFILTER_NETLINK_HOOK=m
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_FAMILY_BRIDGE=y
-CONFIG_NETFILTER_FAMILY_ARP=y
-CONFIG_NETFILTER_NETLINK_ACCT=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NETFILTER_NETLINK_OSF=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_LOG_SYSLOG=m
-CONFIG_NF_LOG_COMMON=m
-CONFIG_NF_LOG_NETDEV=m
-CONFIG_NETFILTER_CONNCOUNT=m
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_ZONES=y
-CONFIG_NF_CONNTRACK_PROCFS=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CONNTRACK_TIMEOUT=y
-CONFIG_NF_CONNTRACK_TIMESTAMP=y
-CONFIG_NF_CONNTRACK_LABELS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_GRE=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_BROADCAST=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_SNMP=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NF_CT_NETLINK_TIMEOUT=m
-CONFIG_NF_CT_NETLINK_HELPER=m
-CONFIG_NETFILTER_NETLINK_GLUE_CT=y
-CONFIG_NF_NAT=m
-CONFIG_NF_NAT_AMANDA=m
-CONFIG_NF_NAT_FTP=m
-CONFIG_NF_NAT_IRC=m
-CONFIG_NF_NAT_SIP=m
-CONFIG_NF_NAT_TFTP=m
-CONFIG_NF_NAT_REDIRECT=y
-CONFIG_NF_NAT_MASQUERADE=y
-CONFIG_NETFILTER_SYNPROXY=m
-CONFIG_NF_TABLES=m
-CONFIG_NF_TABLES_INET=y
-CONFIG_NF_TABLES_NETDEV=y
-CONFIG_NFT_NUMGEN=m
-CONFIG_NFT_CT=m
-CONFIG_NFT_FLOW_OFFLOAD=m
-CONFIG_NFT_COUNTER=m
-CONFIG_NFT_CONNLIMIT=m
-CONFIG_NFT_LOG=m
-CONFIG_NFT_LIMIT=m
-CONFIG_NFT_MASQ=m
-CONFIG_NFT_REDIR=m
-CONFIG_NFT_NAT=m
-CONFIG_NFT_TUNNEL=m
-CONFIG_NFT_OBJREF=m
-CONFIG_NFT_QUEUE=m
-CONFIG_NFT_QUOTA=m
-CONFIG_NFT_REJECT=m
-CONFIG_NFT_REJECT_INET=m
-CONFIG_NFT_COMPAT=m
-CONFIG_NFT_HASH=m
-CONFIG_NFT_FIB_INET=m
-CONFIG_NFT_FIB=m
-CONFIG_NFT_FIB_INET=m
-CONFIG_NFT_XFRM=m
-CONFIG_NFT_SOCKET=m
-CONFIG_NFT_OSF=m
-CONFIG_NFT_TPROXY=m
-CONFIG_NFT_SYNPROXY=m
-CONFIG_NF_DUP_NETDEV=m
-CONFIG_NFT_DUP_NETDEV=m
-CONFIG_NFT_FWD_NETDEV=m
-CONFIG_NFT_FIB_NETDEV=m
-CONFIG_NFT_REJECT_NETDEV=m
-CONFIG_NF_FLOW_TABLE_INET=m
-CONFIG_NF_FLOW_TABLE=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XTABLES_COMPAT=y
-
-#
-# Xtables combined modules
-#
-CONFIG_NETFILTER_XT_MARK=m
-CONFIG_NETFILTER_XT_CONNMARK=m
-CONFIG_NETFILTER_XT_SET=m
-
-#
-# Xtables targets
-#
-CONFIG_NETFILTER_XT_TARGET_AUDIT=m
-CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CT=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_HL=m
-CONFIG_NETFILTER_XT_TARGET_HMARK=m
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
-CONFIG_NETFILTER_XT_TARGET_LOG=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_NAT=m
-CONFIG_NETFILTER_XT_TARGET_NETMAP=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-CONFIG_NETFILTER_XT_TARGET_RATEEST=m
-CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
-CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
-CONFIG_NETFILTER_XT_TARGET_TEE=m
-CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-CONFIG_NETFILTER_XT_TARGET_TRACE=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-
-#
-# Xtables matches
-#
-CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
-CONFIG_NETFILTER_XT_MATCH_BPF=m
-CONFIG_NETFILTER_XT_MATCH_CGROUP=m
-CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_CPU=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ECN=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_HL=m
-CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_IPVS=m
-CONFIG_NETFILTER_XT_MATCH_L2TP=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-CONFIG_NETFILTER_XT_MATCH_OSF=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-# end of Core Netfilter Configuration
-
-CONFIG_IP_SET=m
-CONFIG_IP_SET_MAX=256
-CONFIG_IP_SET_BITMAP_IP=m
-CONFIG_IP_SET_BITMAP_IPMAC=m
-CONFIG_IP_SET_BITMAP_PORT=m
-CONFIG_IP_SET_HASH_IP=m
-CONFIG_IP_SET_HASH_IPMARK=m
-CONFIG_IP_SET_HASH_IPPORT=m
-CONFIG_IP_SET_HASH_IPPORTIP=m
-CONFIG_IP_SET_HASH_IPPORTNET=m
-CONFIG_IP_SET_HASH_IPMAC=m
-CONFIG_IP_SET_HASH_MAC=m
-CONFIG_IP_SET_HASH_NETPORTNET=m
-CONFIG_IP_SET_HASH_NET=m
-CONFIG_IP_SET_HASH_NETNET=m
-CONFIG_IP_SET_HASH_NETPORT=m
-CONFIG_IP_SET_HASH_NETIFACE=m
-CONFIG_IP_SET_LIST_SET=m
-CONFIG_IP_VS=m
-CONFIG_IP_VS_IPV6=y
-# CONFIG_IP_VS_DEBUG is not set
-CONFIG_IP_VS_TAB_BITS=12
-
-#
-# IPVS transport protocol load balancing support
-#
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_AH_ESP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_PROTO_SCTP=y
-
-#
-# IPVS scheduler
-#
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_FO=m
-CONFIG_IP_VS_OVF=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_MH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_TWOS=m
-
-#
-# IPVS SH scheduler
-#
-CONFIG_IP_VS_SH_TAB_BITS=8
-
-#
-# IPVS MH scheduler
-#
-CONFIG_IP_VS_MH_TAB_INDEX=12
-
-#
-# IPVS application helper
-#
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_VS_NFCT=y
-CONFIG_IP_VS_PE_SIP=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_DEFRAG_IPV4=m
-CONFIG_NF_SOCKET_IPV4=m
-CONFIG_NF_TPROXY_IPV4=m
-CONFIG_NF_TABLES_IPV4=y
-CONFIG_NFT_REJECT_IPV4=m
-CONFIG_NFT_DUP_IPV4=m
-CONFIG_NFT_FIB_IPV4=m
-CONFIG_NF_TABLES_ARP=y
-CONFIG_NF_FLOW_TABLE_IPV4=m
-CONFIG_NF_DUP_IPV4=m
-CONFIG_NF_LOG_ARP=m
-CONFIG_NF_LOG_IPV4=m
-CONFIG_NF_REJECT_IPV4=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_NF_NAT_PPTP=m
-CONFIG_NF_NAT_H323=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_RPFILTER=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_SYNPROXY=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-# end of IP: Netfilter Configuration
-
-#
-# IPv6: Netfilter Configuration
-#
-CONFIG_NF_SOCKET_IPV6=m
-CONFIG_NF_TPROXY_IPV6=m
-CONFIG_NF_TABLES_IPV6=y
-CONFIG_NFT_REJECT_IPV6=m
-CONFIG_NFT_DUP_IPV6=m
-CONFIG_NFT_FIB_IPV6=m
-CONFIG_NF_FLOW_TABLE_IPV6=m
-CONFIG_NF_DUP_IPV6=m
-CONFIG_NF_REJECT_IPV6=m
-CONFIG_NF_LOG_IPV6=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RPFILTER=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_MATCH_SRH=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_TARGET_SYNPROXY=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_IP6_NF_NAT=m
-CONFIG_IP6_NF_TARGET_MASQUERADE=m
-CONFIG_IP6_NF_TARGET_NPT=m
-# end of IPv6: Netfilter Configuration
-
-CONFIG_NF_DEFRAG_IPV6=m
-CONFIG_NF_TABLES_BRIDGE=m
-CONFIG_NFT_BRIDGE_META=m
-CONFIG_NFT_BRIDGE_REJECT=m
-CONFIG_NF_LOG_BRIDGE=m
-CONFIG_NF_CONNTRACK_BRIDGE=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_IP6=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_BRIDGE_EBT_NFLOG=m
-CONFIG_BPFILTER=y
-CONFIG_BPFILTER_UMH=m
-CONFIG_IP_DCCP=m
-CONFIG_INET_DCCP_DIAG=m
-
-#
-# DCCP CCIDs Configuration
-#
-# CONFIG_IP_DCCP_CCID2_DEBUG is not set
-CONFIG_IP_DCCP_CCID3=y
-# CONFIG_IP_DCCP_CCID3_DEBUG is not set
-CONFIG_IP_DCCP_TFRC_LIB=y
-# end of DCCP CCIDs Configuration
-
-#
-# DCCP Kernel Hacking
-#
-# CONFIG_IP_DCCP_DEBUG is not set
-# end of DCCP Kernel Hacking
-
-CONFIG_IP_SCTP=m
-# CONFIG_SCTP_DBG_OBJCNT is not set
-CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
-CONFIG_SCTP_COOKIE_HMAC_MD5=y
-CONFIG_SCTP_COOKIE_HMAC_SHA1=y
-CONFIG_INET_SCTP_DIAG=m
-CONFIG_RDS=m
-CONFIG_RDS_RDMA=m
-CONFIG_RDS_TCP=m
-# CONFIG_RDS_DEBUG is not set
-CONFIG_TIPC=m
-CONFIG_TIPC_MEDIA_IB=y
-CONFIG_TIPC_MEDIA_UDP=y
-CONFIG_TIPC_CRYPTO=y
-CONFIG_TIPC_DIAG=m
-CONFIG_ATM=m
-CONFIG_ATM_CLIP=m
-# CONFIG_ATM_CLIP_NO_ICMP is not set
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-# CONFIG_ATM_BR2684_IPFILTER is not set
-CONFIG_L2TP=m
-# CONFIG_L2TP_DEBUGFS is not set
-CONFIG_L2TP_V3=y
-CONFIG_L2TP_IP=m
-CONFIG_L2TP_ETH=m
-CONFIG_STP=m
-CONFIG_GARP=m
-CONFIG_MRP=m
-CONFIG_BRIDGE=m
-CONFIG_BRIDGE_IGMP_SNOOPING=y
-CONFIG_BRIDGE_VLAN_FILTERING=y
-# CONFIG_BRIDGE_MRP is not set
-# CONFIG_BRIDGE_CFM is not set
-CONFIG_HAVE_NET_DSA=y
-CONFIG_NET_DSA=m
-CONFIG_NET_DSA_TAG_8021Q=m
-CONFIG_NET_DSA_TAG_AR9331=m
-CONFIG_NET_DSA_TAG_BRCM_COMMON=m
-CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
-CONFIG_NET_DSA_TAG_BRCM=m
-CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
-CONFIG_NET_DSA_TAG_HELLCREEK=m
-CONFIG_NET_DSA_TAG_GSWIP=m
-CONFIG_NET_DSA_TAG_DSA=m
-CONFIG_NET_DSA_TAG_EDSA=m
-CONFIG_NET_DSA_TAG_MTK=m
-CONFIG_NET_DSA_TAG_KSZ=m
-CONFIG_NET_DSA_TAG_RTL4_A=m
-CONFIG_NET_DSA_TAG_RTL8_4=m
-CONFIG_NET_DSA_TAG_OCELOT=m
-CONFIG_NET_DSA_TAG_QCA=m
-CONFIG_NET_DSA_TAG_LAN9303=m
-CONFIG_NET_DSA_TAG_SJA1105=m
-CONFIG_NET_DSA_TAG_TRAILER=m
-CONFIG_NET_DSA_TAG_XRS700X=m
-CONFIG_NET_DSA_REALTEK=m
-CONFIG_NET_DSA_REALTEK_MDIO=m
-CONFIG_NET_DSA_REALTEK_RTL8365MB=m
-CONFIG_NET_DSA_REALTEK_RTL8366RB=m
-CONFIG_VLAN_8021Q=m
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_VLAN_8021Q_MVRP=y
-# CONFIG_DECNET is not set
-CONFIG_LLC=m
-CONFIG_LLC2=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_PHONET=m
-CONFIG_6LOWPAN=m
-# CONFIG_6LOWPAN_DEBUGFS is not set
-CONFIG_6LOWPAN_NHC=m
-CONFIG_6LOWPAN_NHC_DEST=m
-CONFIG_6LOWPAN_NHC_FRAGMENT=m
-CONFIG_6LOWPAN_NHC_HOP=m
-CONFIG_6LOWPAN_NHC_IPV6=m
-CONFIG_6LOWPAN_NHC_MOBILITY=m
-CONFIG_6LOWPAN_NHC_ROUTING=m
-CONFIG_6LOWPAN_NHC_UDP=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
-CONFIG_6LOWPAN_GHC_UDP=m
-CONFIG_6LOWPAN_GHC_ICMPV6=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
-CONFIG_IEEE802154=m
-CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
-CONFIG_IEEE802154_SOCKET=m
-CONFIG_IEEE802154_6LOWPAN=m
-CONFIG_MAC802154=m
-CONFIG_NET_SCHED=y
-
-#
-# Queueing/Scheduling
-#
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_MULTIQ=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFB=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_CBS=m
-CONFIG_NET_SCH_ETF=m
-CONFIG_NET_SCH_TAPRIO=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_DRR=m
-CONFIG_NET_SCH_MQPRIO=m
-CONFIG_NET_SCH_SKBPRIO=m
-CONFIG_NET_SCH_CHOKE=m
-CONFIG_NET_SCH_QFQ=m
-CONFIG_NET_SCH_CODEL=m
-CONFIG_NET_SCH_FQ_CODEL=y
-CONFIG_NET_SCH_CAKE=m
-CONFIG_NET_SCH_FQ=m
-CONFIG_NET_SCH_HHF=m
-CONFIG_NET_SCH_PIE=m
-CONFIG_NET_SCH_FQ_PIE=m
-CONFIG_NET_SCH_INGRESS=m
-CONFIG_NET_SCH_PLUG=m
-CONFIG_NET_SCH_ETS=m
-# CONFIG_NET_SCH_DEFAULT is not set
-
-#
-# Classification
-#
-CONFIG_NET_CLS=y
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_CLS_U32_PERF=y
-CONFIG_CLS_U32_MARK=y
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_CLS_FLOW=m
-CONFIG_NET_CLS_CGROUP=m
-CONFIG_NET_CLS_BPF=m
-CONFIG_NET_CLS_FLOWER=m
-CONFIG_NET_CLS_MATCHALL=m
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_STACK=32
-CONFIG_NET_EMATCH_CMP=m
-CONFIG_NET_EMATCH_NBYTE=m
-CONFIG_NET_EMATCH_U32=m
-CONFIG_NET_EMATCH_META=m
-CONFIG_NET_EMATCH_TEXT=m
-CONFIG_NET_EMATCH_CANID=m
-CONFIG_NET_EMATCH_IPSET=m
-CONFIG_NET_EMATCH_IPT=m
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=m
-CONFIG_NET_ACT_GACT=m
-CONFIG_GACT_PROB=y
-CONFIG_NET_ACT_MIRRED=m
-CONFIG_NET_ACT_SAMPLE=m
-CONFIG_NET_ACT_IPT=m
-CONFIG_NET_ACT_NAT=m
-CONFIG_NET_ACT_PEDIT=m
-# CONFIG_NET_ACT_SIMP is not set
-CONFIG_NET_ACT_SKBEDIT=m
-CONFIG_NET_ACT_CSUM=m
-CONFIG_NET_ACT_MPLS=m
-CONFIG_NET_ACT_VLAN=m
-CONFIG_NET_ACT_BPF=m
-CONFIG_NET_ACT_CONNMARK=m
-CONFIG_NET_ACT_CTINFO=m
-CONFIG_NET_ACT_SKBMOD=m
-CONFIG_NET_ACT_IFE=m
-CONFIG_NET_ACT_TUNNEL_KEY=m
-CONFIG_NET_ACT_CT=m
-CONFIG_NET_ACT_GATE=m
-CONFIG_NET_IFE_SKBMARK=m
-CONFIG_NET_IFE_SKBPRIO=m
-CONFIG_NET_IFE_SKBTCINDEX=m
-# CONFIG_NET_TC_SKB_EXT is not set
-CONFIG_NET_SCH_FIFO=y
-CONFIG_DCB=y
-CONFIG_DNS_RESOLVER=y
-CONFIG_BATMAN_ADV=m
-# CONFIG_BATMAN_ADV_BATMAN_V is not set
-CONFIG_BATMAN_ADV_BLA=y
-CONFIG_BATMAN_ADV_DAT=y
-CONFIG_BATMAN_ADV_NC=y
-CONFIG_BATMAN_ADV_MCAST=y
-CONFIG_BATMAN_ADV_DEBUGFS=y
-# CONFIG_BATMAN_ADV_DEBUG is not set
-CONFIG_BATMAN_ADV_SYSFS=y
-# CONFIG_BATMAN_ADV_TRACING is not set
-CONFIG_OPENVSWITCH=m
-CONFIG_OPENVSWITCH_GRE=m
-CONFIG_OPENVSWITCH_VXLAN=m
-CONFIG_OPENVSWITCH_GENEVE=m
-CONFIG_VSOCKETS=m
-CONFIG_VSOCKETS_DIAG=m
-CONFIG_VSOCKETS_LOOPBACK=m
-CONFIG_VIRTIO_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS_COMMON=m
-CONFIG_NETLINK_DIAG=m
-CONFIG_MPLS=y
-CONFIG_NET_MPLS_GSO=m
-CONFIG_MPLS_ROUTING=m
-CONFIG_MPLS_IPTUNNEL=m
-CONFIG_NET_NSH=m
-CONFIG_HSR=m
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_L3_MASTER_DEV=y
-CONFIG_QRTR=m
-CONFIG_QRTR_SMD=m
-CONFIG_QRTR_TUN=m
-CONFIG_QRTR_MHI=m
-# CONFIG_NET_NCSI is not set
-CONFIG_PCPU_DEV_REFCNT=y
-CONFIG_RPS=y
-CONFIG_RFS_ACCEL=y
-CONFIG_XPS=y
-CONFIG_CGROUP_NET_PRIO=y
-CONFIG_CGROUP_NET_CLASSID=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_BQL=y
-CONFIG_BPF_JIT=y
-CONFIG_BPF_STREAM_PARSER=y
-CONFIG_NET_FLOW_LIMIT=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NET_DROP_MONITOR is not set
-# end of Network testing
-# end of Networking options
-
-CONFIG_HAMRADIO=y
-
-#
-# Packet Radio protocols
-#
-CONFIG_AX25=m
+CONFIG_ARM_TIMER_SP804=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIC_NR=4
+CONFIG_ARM_VIC=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ARM=y
+CONFIG_AS3935=m
+CONFIG_AS73211=m
+CONFIG_ASHMEM=m
+CONFIG_ASPEED_SOCINFO=y
+CONFIG_ASPEED_UART_ROUTING=m
+CONFIG_ASPEED_WATCHDOG=y
+CONFIG_AST2600_I3C_MASTER=m
+CONFIG_AST2700_MBOX=m
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_ASYNC_TX_DMA=y
+CONFIG_ASYNC_XOR=m
+CONFIG_AT76C50X_USB=m
+CONFIG_AT803X_PHY=m
+CONFIG_AT91_SOC_ID=y
+CONFIG_ATAGS_PROC=y
+CONFIG_ATAGS=y
+CONFIG_ATA=m
+CONFIG_ATA_OVER_ETH=m
+CONFIG_ATA_PIIX=m
+CONFIG_ATH10K_CE=y
+CONFIG_ATH10K=m
+CONFIG_ATH10K_PCI=m
+CONFIG_ATH10K_SDIO=m
+CONFIG_ATH10K_USB=m
+CONFIG_ATH11K_AHB=m
+CONFIG_ATH11K=m
+CONFIG_ATH11K_PCI=m
+CONFIG_ATH12K=m
+CONFIG_ATH5K=m
+CONFIG_ATH5K_PCI=y
+CONFIG_ATH6KL=m
+CONFIG_ATH6KL_SDIO=m
+CONFIG_ATH6KL_USB=m
+CONFIG_ATH9K_AHB=y
+CONFIG_ATH9K_BTCOEX_SUPPORT=y
+CONFIG_ATH9K_CHANNEL_CONTEXT=y
+CONFIG_ATH9K_COMMON=m
+CONFIG_ATH9K_DYNACK=y
+CONFIG_ATH9K_HTC=m
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_HWRNG=y
+CONFIG_ATH9K=m
+CONFIG_ATH9K_PCI_NO_EEPROM=m
+CONFIG_ATH9K_PCI=y
+CONFIG_ATH9K_PCOEM=y
+CONFIG_ATH9K_RFKILL=y
+CONFIG_ATH9K_WOW=y
+CONFIG_ATH_COMMON=m
+CONFIG_ATLAS7_TIMER=y
+CONFIG_ATLAS_EZO_SENSOR=m
+CONFIG_ATLAS_PH_SENSOR=m
+CONFIG_ATMEL_EBI=y
+CONFIG_ATMEL=m
+CONFIG_ATMEL_SDRAMC=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_AUXDISPLAY=y
+CONFIG_AW96103=m
 CONFIG_AX25_DAMA_SLAVE=y
-CONFIG_NETROM=m
-CONFIG_ROSE=m
-
-#
-# AX.25 network device drivers
-#
-CONFIG_MKISS=m
-CONFIG_6PACK=m
-CONFIG_BPQETHER=m
+CONFIG_AX25=m
+CONFIG_AX88796B_PHY=m
+CONFIG_AXP20X_ADC=m
+CONFIG_AXP20X_POWER=m
+CONFIG_AXP288_ADC=m
+CONFIG_AXP288_FUEL_GAUGE=m
+CONFIG_B43_BCMA_PIO=y
+CONFIG_B43_BCMA=y
+CONFIG_B43_BUSES_BCMA_AND_SSB=y
+CONFIG_B43_HWRNG=y
+CONFIG_B43_LEDS=y
+CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
+CONFIG_B43LEGACY_DMA=y
+CONFIG_B43LEGACY_HWRNG=y
+CONFIG_B43LEGACY_LEDS=y
+CONFIG_B43LEGACY=m
+CONFIG_B43LEGACY_PCI_AUTOSELECT=y
+CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
+CONFIG_B43LEGACY_PIO=y
+CONFIG_B43=m
+CONFIG_B43_PCI_AUTOSELECT=y
+CONFIG_B43_PCICORE_AUTOSELECT=y
+CONFIG_B43_PHY_G=y
+CONFIG_B43_PHY_HT=y
+CONFIG_B43_PHY_LP=y
+CONFIG_B43_PHY_N=y
+CONFIG_B43_PIO=y
+CONFIG_B43_SDIO=y
+CONFIG_B43_SSB=y
+CONFIG_BACKLIGHT_ADP8860=m
+CONFIG_BACKLIGHT_ADP8870=m
+CONFIG_BACKLIGHT_APPLE_DWI=m
+CONFIG_BACKLIGHT_ARCXCNN=m
+CONFIG_BACKLIGHT_BD6107=m
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_DA9052=m
+CONFIG_BACKLIGHT_GPIO=m
+CONFIG_BACKLIGHT_KTD253=m
+CONFIG_BACKLIGHT_KTD2801=m
+CONFIG_BACKLIGHT_KTZ8866=m
+CONFIG_BACKLIGHT_LED=m
+CONFIG_BACKLIGHT_LM3533=m
+CONFIG_BACKLIGHT_LM3630A=m
+CONFIG_BACKLIGHT_LM3639=m
+CONFIG_BACKLIGHT_LP855X=m
+CONFIG_BACKLIGHT_LV5207LP=m
+CONFIG_BACKLIGHT_MP3309C=m
+CONFIG_BACKLIGHT_MT6370=m
+CONFIG_BACKLIGHT_PCF50633=m
+CONFIG_BACKLIGHT_PWM=m
+CONFIG_BACKLIGHT_QCOM_WLED=m
+CONFIG_BACKLIGHT_RAVE_SP=m
+CONFIG_BACKLIGHT_RT4831=m
+CONFIG_BACKLIGHT_SKY81452=m
+CONFIG_BACKLIGHT_TPS65217=m
+CONFIG_BACKLIGHT_WM831X=m
+CONFIG_BACKTRACE_VERBOSE=y
+CONFIG_BAREUDP=m
+CONFIG_BATTERY_AXP20X=m
+CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM=y
+CONFIG_BATTERY_BQ27XXX_HDQ=m
+CONFIG_BATTERY_BQ27XXX_I2C=m
+CONFIG_BATTERY_BQ27XXX=m
+CONFIG_BATTERY_CHAGALL=m
+CONFIG_BATTERY_CPCAP=m
+CONFIG_BATTERY_CW2015=m
+CONFIG_BATTERY_DA9052=m
+CONFIG_BATTERY_DA9150=m
+CONFIG_BATTERY_DS2760=m
+CONFIG_BATTERY_DS2780=m
+CONFIG_BATTERY_DS2781=m
+CONFIG_BATTERY_DS2782=m
+CONFIG_BATTERY_GAUGE_LTC2941=m
+CONFIG_BATTERY_GOLDFISH=m
+CONFIG_BATTERY_MAX17040=m
+CONFIG_BATTERY_MAX17042=m
+CONFIG_BATTERY_MAX1721X=m
+CONFIG_BATTERY_OLPC=m
+CONFIG_BATTERY_QCOM_BATTMGR=m
+CONFIG_BATTERY_RT5033=m
+CONFIG_BATTERY_SAMSUNG_SDI=y
+CONFIG_BATTERY_SBS=m
+CONFIG_BATTERY_SURFACE=m
+CONFIG_BATTERY_UG3105=m
+CONFIG_BAYCOM_EPP=m
+CONFIG_BAYCOM_PAR=m
 CONFIG_BAYCOM_SER_FDX=m
 CONFIG_BAYCOM_SER_HDX=m
-CONFIG_BAYCOM_PAR=m
-CONFIG_BAYCOM_EPP=m
-CONFIG_YAM=m
-# end of AX.25 network device drivers
-
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_GW=m
-CONFIG_CAN_J1939=m
-CONFIG_CAN_ISOTP=m
-CONFIG_CAN_ETAS_ES58X=m
-
-#
-# CAN Device Drivers
-#
-CONFIG_CAN_VCAN=m
-CONFIG_CAN_VXCAN=m
-CONFIG_CAN_SLCAN=m
-CONFIG_CAN_DEV=m
-CONFIG_CAN_CALC_BITTIMING=y
-# CONFIG_CAN_AT91 is not set
-CONFIG_CAN_FLEXCAN=m
-CONFIG_CAN_GRCAN=m
-CONFIG_CAN_JANZ_ICAN3=m
-CONFIG_CAN_KVASER_PCIEFD=m
-# CONFIG_CAN_SUN4I is not set
-CONFIG_CAN_TI_HECC=m
-# CONFIG_CAN_XILINXCAN is not set
-CONFIG_CAN_C_CAN=m
-CONFIG_CAN_C_CAN_PLATFORM=m
-CONFIG_CAN_C_CAN_PCI=m
-CONFIG_CAN_CC770=m
-CONFIG_CAN_CC770_ISA=m
-CONFIG_CAN_CC770_PLATFORM=m
-CONFIG_CAN_IFI_CANFD=m
-CONFIG_CAN_M_CAN=m
-CONFIG_CAN_M_CAN_PCI=m
-CONFIG_CAN_M_CAN_PLATFORM=m
-CONFIG_CAN_M_CAN_TCAN4X5X=m
-CONFIG_CAN_PEAK_PCIEFD=m
-CONFIG_CAN_RCAR=m
-CONFIG_CAN_RCAR_CANFD=m
-CONFIG_CAN_SJA1000=m
-CONFIG_CAN_EMS_PCI=m
-CONFIG_CAN_EMS_PCMCIA=m
-CONFIG_CAN_F81601=m
-CONFIG_CAN_KVASER_PCI=m
-CONFIG_CAN_PEAK_PCI=m
-CONFIG_CAN_PEAK_PCIEC=y
-CONFIG_CAN_PLX_PCI=m
-CONFIG_CAN_SJA1000_ISA=m
-CONFIG_CAN_SJA1000_PLATFORM=m
-CONFIG_CAN_SOFTING=m
-CONFIG_CAN_SOFTING_CS=m
-
-#
-# CAN SPI interfaces
-#
-CONFIG_CAN_HI311X=m
-CONFIG_CAN_MCP251X=m
-CONFIG_CAN_MCP251XFD=m
-# CONFIG_CAN_MCP251XFD_SANITY is not set
-# end of CAN SPI interfaces
-
-#
-# CAN USB interfaces
-#
-CONFIG_CAN_8DEV_USB=m
-CONFIG_CAN_EMS_USB=m
-CONFIG_CAN_ESD_USB2=m
-CONFIG_CAN_GS_USB=m
-CONFIG_CAN_KVASER_USB=m
-CONFIG_CAN_MCBA_USB=m
-CONFIG_CAN_PEAK_USB=m
-CONFIG_CAN_UCAN=m
-# end of CAN USB interfaces
-
-# CONFIG_CAN_DEBUG_DEVICES is not set
-# end of CAN Device Drivers
-
-CONFIG_BT=m
-CONFIG_BT_BREDR=y
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_CMTP=m
-CONFIG_BT_HIDP=m
-CONFIG_BT_HS=y
-CONFIG_BT_LE=y
-CONFIG_BT_6LOWPAN=m
-CONFIG_BT_LEDS=y
-CONFIG_BT_MSFTEXT=y
-CONFIG_BT_AOSPEXT=y
-CONFIG_BT_DEBUGFS=y
-# CONFIG_BT_SELFTEST is not set
-# CONFIG_BT_FEATURE_DEBUG is not set
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_INTEL=m
-CONFIG_BT_BCM=m
-CONFIG_BT_RTL=m
-CONFIG_BT_QCA=m
-CONFIG_BT_HCIBTUSB=m
-# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
-CONFIG_BT_HCIBTUSB_BCM=y
-CONFIG_BT_HCIBTUSB_MTK=y
-CONFIG_BT_HCIBTUSB_RTL=y
-CONFIG_BT_HCIBTSDIO=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_SERDEV=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_NOKIA=m
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_ATH3K=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIUART_3WIRE=y
-CONFIG_BT_HCIUART_INTEL=y
-CONFIG_BT_HCIUART_BCM=y
-CONFIG_BT_HCIUART_QCA=y
-CONFIG_BT_HCIUART_AG6XX=y
-CONFIG_BT_HCIUART_MRVL=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIDTL1=m
-CONFIG_BT_HCIBT3C=m
-CONFIG_BT_HCIBLUECARD=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_BT_MRVL=m
-CONFIG_BT_MRVL_SDIO=m
-CONFIG_BT_ATH3K=m
-CONFIG_BT_MTKSDIO=m
-CONFIG_BT_MTKUART=m
-CONFIG_BT_VIRTIO=m
-CONFIG_BT_HCIRSI=m
-# end of Bluetooth device drivers
-
-CONFIG_AF_RXRPC=m
-CONFIG_AF_RXRPC_IPV6=y
-# CONFIG_AF_RXRPC_INJECT_LOSS is not set
-# CONFIG_AF_RXRPC_DEBUG is not set
-# CONFIG_RXKAD is not set
-CONFIG_AF_KCM=m
-CONFIG_STREAM_PARSER=y
-CONFIG_FIB_RULES=y
-CONFIG_WIRELESS=y
-CONFIG_WIRELESS_EXT=y
-# CONFIG_WEXT_CORE is not set
-# CONFIG_WEXT_PROC is not set
-# CONFIG_WEXT_SPY is not set
-# CONFIG_WEXT_PRIV is not set
-CONFIG_CFG80211=m
-CONFIG_NL80211_TESTMODE=y
-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
-CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
-CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
-CONFIG_CFG80211_DEFAULT_PS=y
-# CONFIG_CFG80211_DEBUGFS is not set
-CONFIG_CFG80211_CRDA_SUPPORT=y
-# CONFIG_CFG80211_WEXT is not set
-# CONFIG_CFG80211_WEXT_EXPORT is not set
-CONFIG_LIB80211=m
-CONFIG_LIB80211_CRYPT_WEP=m
-CONFIG_LIB80211_CRYPT_CCMP=m
-CONFIG_LIB80211_CRYPT_TKIP=m
-# CONFIG_LIB80211_DEBUG is not set
-CONFIG_MAC80211=m
-CONFIG_MAC80211_HAS_RC=y
-CONFIG_MAC80211_RC_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
-CONFIG_MAC80211_MESH=y
-CONFIG_MAC80211_LEDS=y
-# CONFIG_MAC80211_DEBUGFS is not set
-# CONFIG_MAC80211_MESSAGE_TRACING is not set
-# CONFIG_MAC80211_DEBUG_MENU is not set
-CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
-CONFIG_WIMAX=m
-CONFIG_WIMAX_DEBUG_LEVEL=8
-CONFIG_RFKILL=m
-CONFIG_RFKILL_LEDS=y
-CONFIG_RFKILL_INPUT=y
-CONFIG_RFKILL_GPIO=m
-CONFIG_NET_9P=m
-CONFIG_NET_9P_VIRTIO=m
-CONFIG_NET_9P_RDMA=m
-# CONFIG_NET_9P_DEBUG is not set
-CONFIG_CAIF=m
-# CONFIG_CAIF_DEBUG is not set
-CONFIG_CAIF_NETDEV=m
+CONFIG_BCACHE_ASYNC_REGISTRATION=y
+CONFIG_BCACHE=m
+CONFIG_BCH_CONST_M=14
+CONFIG_BCH_CONST_T=4
+CONFIG_BCH=m
+CONFIG_BCM2712_MIP=m
+CONFIG_BCM54140_PHY=m
+CONFIG_BCM7038_WDT=m
+CONFIG_BCM7XXX_PHY=m
+CONFIG_BCM84881_PHY=m
+CONFIG_BCM87XX_PHY=m
+CONFIG_BCMA_BLOCKIO=y
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
+CONFIG_BCMA_DRIVER_GPIO=y
+CONFIG_BCMA_DRIVER_PCI=y
+CONFIG_BCMA_HOST_PCI_POSSIBLE=y
+CONFIG_BCMA_HOST_PCI=y
+CONFIG_BCMA_HOST_SOC=y
+CONFIG_BCMA=m
+CONFIG_BCMA_SFLASH=y
+CONFIG_BCM_KONA_USB2_PHY=m
+CONFIG_BCM_NET_PHYLIB=m
+CONFIG_BCM_PMB=y
+CONFIG_BCM_VK=m
+CONFIG_BCM_VK_TTY=y
+CONFIG_BD79703=m
+CONFIG_BD957XMUF_WATCHDOG=m
+CONFIG_BD96801_WATCHDOG=m
+CONFIG_BE2ISCSI=m
+CONFIG_BES2600_5GHZ_SUPPORT=y
+CONFIG_BES2600=m
+CONFIG_BES2600_USE_STE_EXTENSIONS=y
+CONFIG_BES2600_WAPI_SUPPORT=y
+CONFIG_BES2600_WLAN_SDIO=y
+CONFIG_BES2600_WLAN_SPI=y
+CONFIG_BES2600_WLAN_USB=y
+CONFIG_BFQ_GROUP_IOSCHED=y
+CONFIG_BH1745=m
+CONFIG_BH1750=m
+CONFIG_BH1780=m
+CONFIG_BIG_LITTLE=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BINFMT_FLAT=y
+CONFIG_BINFMT_MISC=m
+CONFIG_BINFMT_SHARED_FLAT=y
+CONFIG_BINFMT_ZFLAT=y
+CONFIG_BLK_CGROUP_IOLATENCY=y
+CONFIG_BLK_CGROUP_RWSTAT=y
+CONFIG_BLK_CGROUP=y
+CONFIG_BLK_CMDLINE_PARSER=y
+CONFIG_BLK_DEBUG_FS_ZONED=y
+CONFIG_BLK_DEV_3W_XXXX_RAID=m
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DM=m
+CONFIG_BLK_DEV_DRBD=m
+CONFIG_BLK_DEV_INTEGRITY_T10=m
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_RBD=m
+CONFIG_BLK_DEV_RNBD_CLIENT=m
+CONFIG_BLK_DEV_RNBD_SERVER=m
+CONFIG_BLK_DEV_RNBD=y
+CONFIG_BLK_DEV_RSXX=m
+CONFIG_BLK_DEV_SD=m
+CONFIG_BLK_DEV_SR=m
+CONFIG_BLK_DEV_SX8=m
+CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BLK_DEV_UBLK=m
+CONFIG_BLK_DEV_UMEM=m
+CONFIG_BLK_DEV_ZONED_LOOP=m
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_MQ_RDMA=y
+CONFIG_BLK_SCSI_REQUEST=y
+CONFIG_BLK_WBT_MQ=y
+CONFIG_BLK_WBT=y
+CONFIG_BMA220=m
+CONFIG_BMA400_I2C=m
+CONFIG_BMA400=m
+CONFIG_BMA400_SPI=m
+CONFIG_BMC150_ACCEL_I2C=m
+CONFIG_BMC150_ACCEL=m
+CONFIG_BMC150_ACCEL_SPI=m
+CONFIG_BMC150_MAGN_I2C=m
+CONFIG_BMC150_MAGN=m
+CONFIG_BMC150_MAGN_SPI=m
+CONFIG_BME680_I2C=m
+CONFIG_BME680=m
+CONFIG_BME680_SPI=m
+CONFIG_BMG160_I2C=m
+CONFIG_BMG160=m
+CONFIG_BMG160_SPI=m
+CONFIG_BMI088_ACCEL=m
+CONFIG_BMI160_I2C=m
+CONFIG_BMI160=m
+CONFIG_BMI160_SPI=m
+CONFIG_BMI323_I2C=m
+CONFIG_BMI323_SPI=m
+CONFIG_BMP280_I2C=m
+CONFIG_BMP280=m
+CONFIG_BMP280_SPI=m
+CONFIG_BONDING=m
+CONFIG_BOOT_CONFIG=y
+CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_BOOTSPLASH=y
+CONFIG_BOSCH_BNO055_I2C=m
+CONFIG_BOSCH_BNO055_SERIAL=m
+CONFIG_BOUNCE=y
+CONFIG_BPF_EVENTS=y
+CONFIG_BPF_JIT_DEFAULT_ON=y
+CONFIG_BPQETHER=m
+CONFIG_BRANCH_PROFILE_NONE=y
+CONFIG_BRCMFMAC=m
+CONFIG_BRCMFMAC_PCIE=y
+CONFIG_BRCMFMAC_PROTO_BCDC=y
+CONFIG_BRCMFMAC_PROTO_MSGBUF=y
+CONFIG_BRCMFMAC_SDIO=y
+CONFIG_BRCMFMAC_USB=y
+CONFIG_BRCMSMAC=m
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_BRCM_TRACING=y
+CONFIG_BRCMUTIL=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BTREE=y
+CONFIG_BUILD_SALT="916cd9db5c869881bfaa3db9888e5fb4d7e14920"
+CONFIG_C2PORT=m
+CONFIG_CACHE_FEROCEON_L2=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CACHE_UNIPHIER=y
+CONFIG_CADENCE_TTC_TIMER=y
+CONFIG_CADENCE_WATCHDOG=m
+CONFIG_CAIF=m
+CONFIG_CAIF_NETDEV=m
 CONFIG_CAIF_USB=m
+CONFIG_CAN_8DEV_USB=m
+CONFIG_CAN_BCM=m
+CONFIG_CAN_BXCAN=m
+CONFIG_CAN_CALC_BITTIMING=y
+CONFIG_CAN_CAN327=m
+CONFIG_CAN_CC770_ISA=m
+CONFIG_CAN_CC770=m
+CONFIG_CAN_CC770_PLATFORM=m
+CONFIG_CAN_C_CAN=m
+CONFIG_CAN_C_CAN_PCI=m
+CONFIG_CAN_C_CAN_PLATFORM=m
+CONFIG_CAN_CTUCANFD_PCI=m
+CONFIG_CAN_CTUCANFD_PLATFORM=m
+CONFIG_CAN_DEV=m
+CONFIG_CAN_EMS_PCI=m
+CONFIG_CAN_EMS_PCMCIA=m
+CONFIG_CAN_EMS_USB=m
+CONFIG_CAN_ESD_402_PCI=m
+CONFIG_CAN_ESD_USB2=m
+CONFIG_CAN_ESD_USB=m
+CONFIG_CAN_ETAS_ES58X=m
+CONFIG_CAN_F81601=m
+CONFIG_CAN_F81604=m
+CONFIG_CAN_FLEXCAN=m
+CONFIG_CAN_GRCAN=m
+CONFIG_CAN_GS_USB=m
+CONFIG_CAN_GW=m
+CONFIG_CAN_HI311X=m
+CONFIG_CAN_IFI_CANFD=m
+CONFIG_CAN_ISOTP=m
+CONFIG_CAN_J1939=m
+CONFIG_CAN_JANZ_ICAN3=m
+CONFIG_CAN_KVASER_PCIEFD=m
+CONFIG_CAN_KVASER_PCI=m
+CONFIG_CAN_KVASER_USB=m
+CONFIG_CAN=m
+CONFIG_CAN_M_CAN=m
+CONFIG_CAN_M_CAN_PCI=m
+CONFIG_CAN_M_CAN_PLATFORM=m
+CONFIG_CAN_M_CAN_TCAN4X5X=m
+CONFIG_CAN_MCBA_USB=m
+CONFIG_CAN_MCP251XFD=m
+CONFIG_CAN_MCP251X=m
+CONFIG_CAN_NCT6694=m
+CONFIG_CAN_NETLINK=y
+CONFIG_CAN_PEAK_PCIEC=y
+CONFIG_CAN_PEAK_PCIEFD=m
+CONFIG_CAN_PEAK_PCI=m
+CONFIG_CAN_PEAK_USB=m
+CONFIG_CAN_PLX_PCI=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_RCAR_CANFD=m
+CONFIG_CAN_RCAR=m
+CONFIG_CAN_ROCKCHIP_CANFD=m
+CONFIG_CAN_SJA1000_ISA=m
+CONFIG_CAN_SJA1000=m
+CONFIG_CAN_SJA1000_PLATFORM=m
+CONFIG_CAN_SLCAN=m
+CONFIG_CAN_SOFTING_CS=m
+CONFIG_CAN_SOFTING=m
+CONFIG_CAN_TI_HECC=m
+CONFIG_CAN_UCAN=m
+CONFIG_CAN_VCAN=m
+CONFIG_CAN_VXCAN=m
+CONFIG_CARDBUS=y
+CONFIG_CARDMAN_4000=m
+CONFIG_CARDMAN_4040=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170=m
+CONFIG_CARL9170_WPC=y
+CONFIG_CB710_CORE=m
+CONFIG_CB710_DEBUG_ASSUMPTIONS=y
+CONFIG_CC10001_ADC=m
+CONFIG_CC_CAN_LINK_STATIC=y
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_HAS_ASM_GOTO=y
+CONFIG_CC_IS_GCC=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CCS811=m
+CONFIG_CC_VERSION_TEXT="gcc (GCC) 10.2.0 20200723 (OpenMandriva)"
+CONFIG_CDNS_I3C_MASTER=m
+CONFIG_CDROM=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_WCACHE=y
+CONFIG_CEC_CH7322=m
+CONFIG_CEC_CORE=m
+CONFIG_CEC_CROS_EC=m
+CONFIG_CEC_GPIO=m
+CONFIG_CEC_NOTIFIER=y
+CONFIG_CEC_NXP_TDA9950=m
+CONFIG_CEC_PIN=y
 CONFIG_CEPH_LIB=m
-# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
 CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
-CONFIG_NFC=m
-CONFIG_NFC_DIGITAL=m
-CONFIG_NFC_NCI=m
-CONFIG_NFC_NCI_SPI=m
-CONFIG_NFC_NCI_UART=m
-CONFIG_NFC_HCI=m
-CONFIG_NFC_SHDLC=y
-
-#
-# Near Field Communication (NFC) devices
-#
-CONFIG_NFC_TRF7970A=m
-CONFIG_NFC_SIM=m
-CONFIG_NFC_PORT100=m
-CONFIG_NFC_VIRTUAL_NCI=m
-CONFIG_NFC_FDP=m
-CONFIG_NFC_FDP_I2C=m
-CONFIG_NFC_PN544=m
-CONFIG_NFC_PN544_I2C=m
-CONFIG_NFC_PN533=m
-CONFIG_NFC_PN533_USB=m
-CONFIG_NFC_PN533_I2C=m
-CONFIG_NFC_PN532_UART=m
-CONFIG_NFC_MICROREAD=m
-CONFIG_NFC_MICROREAD_I2C=m
-CONFIG_NFC_MRVL=m
-CONFIG_NFC_MRVL_USB=m
-CONFIG_NFC_MRVL_UART=m
-CONFIG_NFC_MRVL_I2C=m
-CONFIG_NFC_MRVL_SPI=m
-CONFIG_NFC_ST21NFCA=m
-CONFIG_NFC_ST21NFCA_I2C=m
-CONFIG_NFC_ST_NCI=m
-CONFIG_NFC_ST_NCI_I2C=m
-CONFIG_NFC_ST_NCI_SPI=m
-CONFIG_NFC_NXP_NCI=m
-CONFIG_NFC_NXP_NCI_I2C=m
-CONFIG_NFC_S3FWRN5=m
-CONFIG_NFC_S3FWRN5_I2C=m
-CONFIG_NFC_S3FWRN82_UART=m
-CONFIG_NFC_ST95HF=m
-# end of Near Field Communication (NFC) devices
-
-CONFIG_PSAMPLE=m
-CONFIG_NET_IFE=m
-CONFIG_LWTUNNEL=y
-CONFIG_LWTUNNEL_BPF=y
-# CONFIG_PAGE_POOL_STATS is not set
-CONFIG_DST_CACHE=y
-CONFIG_GRO_CELLS=y
-CONFIG_SOCK_VALIDATE_XMIT=y
-CONFIG_NET_SOCK_MSG=y
-CONFIG_NET_DEVLINK=y
-CONFIG_PAGE_POOL=y
-CONFIG_FAILOVER=m
-CONFIG_ETHTOOL_NETLINK=y
-CONFIG_HAVE_EBPF_JIT=y
-
-#
-# Device Drivers
-#
-CONFIG_ARM_AMBA=y
-CONFIG_TEGRA_AHB=y
-CONFIG_HAVE_PCI=y
-CONFIG_FORCE_PCI=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_SYSCALL=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_HOTPLUG_PCI_PCIE=y
-CONFIG_PCIEAER=y
-# CONFIG_PCIEAER_INJECT is not set
-CONFIG_PCIE_ECRC=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-CONFIG_PCIE_PME=y
-CONFIG_PCIE_DPC=y
-CONFIG_PCIE_PTM=y
-# CONFIG_PCIE_BW is not set
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_MSI_ARCH_FALLBACKS=y
-CONFIG_PCI_QUIRKS=y
-# CONFIG_PCI_DEBUG is not set
-CONFIG_PCI_REALLOC_ENABLE_AUTO=y
-CONFIG_PCI_STUB=m
-CONFIG_PCI_PF_STUB=m
-CONFIG_PCI_ATS=y
-CONFIG_PCI_ECAM=y
-CONFIG_PCI_IOV=y
-CONFIG_PCI_PRI=y
-CONFIG_PCI_PASID=y
-# CONFIG_PCIE_BUS_TUNE_OFF is not set
-CONFIG_PCIE_BUS_DEFAULT=y
-# CONFIG_PCIE_BUS_SAFE is not set
-# CONFIG_PCIE_BUS_PERFORMANCE is not set
-# CONFIG_PCIE_BUS_PEER2PEER is not set
-CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_CPCI=y
-CONFIG_HOTPLUG_PCI_SHPC=y
-
-#
-# PCI controller drivers
-#
-# CONFIG_PCI_MVEBU is not set
-CONFIG_PCI_FTPCI100=y
-# CONFIG_PCI_IXP4XX is not set
-# CONFIG_PCI_TEGRA is not set
-# CONFIG_PCI_RCAR_GEN2 is not set
-# CONFIG_PCIE_RCAR is not set
-# CONFIG_PCIE_RCAR_HOST is not set
-# CONFIG_PCIE_RCAR_EP is not set
-CONFIG_PCI_HOST_COMMON=y
-CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCIE_XILINX=y
-CONFIG_PCI_V3_SEMI=y
-CONFIG_PCIE_ALTERA=m
-CONFIG_PCIE_ALTERA_MSI=m
-# CONFIG_PCIE_ROCKCHIP_HOST is not set
-# CONFIG_PCIE_ROCKCHIP_EP is not set
-# CONFIG_PCIE_MEDIATEK is not set
-CONFIG_PCIE_MEDIATEK_GEN3=m
-CONFIG_PCIE_BRCMSTB=m
-CONFIG_PCIE_MICROCHIP_HOST=y
-
-#
-# DesignWare PCI Core Support
-#
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_DW_EP=y
-CONFIG_PCIE_DW_PLAT=y
-CONFIG_PCIE_DW_PLAT_HOST=y
-CONFIG_PCIE_DW_PLAT_EP=y
-CONFIG_PCI_EXYNOS=m
-# CONFIG_PCI_IMX6 is not set
-# CONFIG_PCIE_SPEAR13XX is not set
-# CONFIG_PCI_KEYSTONE_HOST is not set
-# CONFIG_PCI_KEYSTONE_EP is not set
-CONFIG_PCI_LAYERSCAPE=y
-CONFIG_PCI_LAYERSCAPE_EP=y
-# CONFIG_PCIE_QCOM is not set
-# CONFIG_PCIE_ARMADA_8K is not set
-# CONFIG_PCIE_HISI_STB is not set
-CONFIG_PCI_MESON=y
-# CONFIG_PCIE_UNIPHIER is not set
-# CONFIG_PCIE_UNIPHIER_EP is not set
-# end of DesignWare PCI Core Support
-
-#
-# Mobiveil PCIe Core Support
-#
-# end of Mobiveil PCIe Core Support
-
-#
-# Cadence PCIe controllers support
-#
-CONFIG_PCIE_CADENCE=y
-CONFIG_PCIE_CADENCE_HOST=y
-CONFIG_PCIE_CADENCE_EP=y
-CONFIG_PCIE_CADENCE_PLAT=y
-CONFIG_PCIE_CADENCE_PLAT_HOST=y
-CONFIG_PCIE_CADENCE_PLAT_EP=y
-CONFIG_PCI_J721E=y
-CONFIG_PCI_J721E_HOST=y
-CONFIG_PCI_J721E_EP=y
-# end of Cadence PCIe controllers support
-# end of PCI controller drivers
-
-#
-# PCI Endpoint
-#
-CONFIG_PCI_ENDPOINT=y
-CONFIG_PCI_ENDPOINT_CONFIGFS=y
-# CONFIG_PCI_EPF_TEST is not set
-CONFIG_PCI_EPF_NTB=m
-# end of PCI Endpoint
-CONFIG_CXL_BUS=m
-CONFIG_CXL_PCI=m
-CONFIG_CXL_MEM=m
-CONFIG_CXL_MEM_RAW_COMMANDS=y
-CONFIG_CXL_ACPI=m
-CONFIG_CXL_PMEM=m
-
-#
-# PCI switch controller drivers
-#
-CONFIG_PCI_SW_SWITCHTEC=m
-# end of PCI switch controller drivers
-
-CONFIG_PCCARD=m
-CONFIG_PCMCIA=m
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_CARDBUS=y
-
-#
-# PC-card bridges
-#
-CONFIG_YENTA=m
-CONFIG_YENTA_O2=y
-CONFIG_YENTA_RICOH=y
-CONFIG_YENTA_TI=y
-CONFIG_YENTA_ENE_TUNE=y
-CONFIG_YENTA_TOSHIBA=y
-CONFIG_PD6729=m
-CONFIG_I82092=m
-# CONFIG_AT91_CF is not set
-CONFIG_PCCARD_NONSTATIC=y
-CONFIG_RAPIDIO=m
-CONFIG_RAPIDIO_TSI721=m
-CONFIG_RAPIDIO_DISC_TIMEOUT=30
-CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y
-CONFIG_RAPIDIO_DMA_ENGINE=y
-# CONFIG_RAPIDIO_DEBUG is not set
-CONFIG_RAPIDIO_ENUM_BASIC=m
-CONFIG_RAPIDIO_CHMAN=m
-CONFIG_RAPIDIO_MPORT_CDEV=m
-
-#
-# RapidIO Switch drivers
-#
-CONFIG_RAPIDIO_TSI57X=m
-CONFIG_RAPIDIO_CPS_XX=m
-CONFIG_RAPIDIO_TSI568=m
-CONFIG_RAPIDIO_CPS_GEN2=m
-CONFIG_RAPIDIO_RXS_GEN3=m
-# end of RapidIO Switch drivers
-
-#
-# Generic Driver Options
-#
-# CONFIG_UEVENT_HELPER is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-
-#
-# Firmware loader
-#
-CONFIG_FW_LOADER=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_FW_LOADER_USER_HELPER is not set
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_FW_LOADER_COMPRESS=y
-CONFIG_FW_CACHE=y
-# end of Firmware loader
-
-CONFIG_WANT_DEV_COREDUMP=y
-CONFIG_ALLOW_DEV_COREDUMP=y
-CONFIG_DEV_COREDUMP=y
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
-CONFIG_TEST_ASYNC_DRIVER_PROBE=m
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_SOC_BUS=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_SLIMBUS=m
-CONFIG_REGMAP_SPI=y
-CONFIG_REGMAP_SPMI=m
-CONFIG_REGMAP_W1=m
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_SOUNDWIRE=m
-CONFIG_REGMAP_SCCB=m
-CONFIG_REGMAP_I3C=m
-CONFIG_REGMAP_SPI_AVMM=m
-CONFIG_DMA_SHARED_BUFFER=y
-# CONFIG_DMA_FENCE_TRACE is not set
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-# end of Generic Driver Options
-
-#
-# Bus devices
-#
-CONFIG_ARM_CCI=y
-CONFIG_ARM_CCI400_COMMON=y
-CONFIG_ARM_CCI400_PORT_CTRL=y
-CONFIG_BRCMSTB_GISB_ARB=y
-CONFIG_MOXTET=m
-# CONFIG_IMX_WEIM is not set
-CONFIG_MVEBU_MBUS=y
-CONFIG_OMAP_INTERCONNECT=y
-# CONFIG_OMAP_OCP2SCP is not set
-CONFIG_QCOM_EBI2=y
-CONFIG_SIMPLE_PM_BUS=m
-# CONFIG_SUN50I_DE2_BUS is not set
-CONFIG_SUNXI_RSB=y
-# CONFIG_TEGRA_GMI is not set
-CONFIG_TI_SYSC=y
-CONFIG_UNIPHIER_SYSTEM_BUS=y
-CONFIG_VEXPRESS_CONFIG=y
-CONFIG_MHI_BUS=m
-# CONFIG_MHI_BUS_DEBUG is not set
-CONFIG_MHI_BUS_PCI_GENERIC=m
-# end of Bus devices
-
-CONFIG_CONNECTOR=m
-CONFIG_GNSS=m
-CONFIG_GNSS_SERIAL=m
-CONFIG_GNSS_MTK_SERIAL=m
-CONFIG_GNSS_SIRF_SERIAL=m
-CONFIG_GNSS_UBX_SERIAL=m
-CONFIG_MTD=m
-CONFIG_MTD_TESTS=m
-
-#
-# Partition parsers
-#
-CONFIG_MTD_AR7_PARTS=m
-CONFIG_MTD_CMDLINE_PARTS=m
-CONFIG_MTD_OF_PARTS=m
-CONFIG_MTD_OF_PARTS_BCM4908=y
-CONFIG_MTD_OF_PARTS_LINKSYS_NS=y
-# CONFIG_MTD_AFS_PARTS is not set
-CONFIG_MTD_PARSER_TRX=m
-CONFIG_MTD_REDBOOT_PARTS=m
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-CONFIG_MTD_QCOMSMEM_PARTS=m
-# end of Partition parsers
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
-CONFIG_MTD_BLOCK_RO=m
-CONFIG_FTL=m
-CONFIG_NFTL=m
-CONFIG_NFTL_RW=y
-CONFIG_INFTL=m
-CONFIG_RFD_FTL=m
-CONFIG_SSFDC=m
-CONFIG_SM_FTL=m
-CONFIG_MTD_OOPS=m
-CONFIG_MTD_PSTORE=m
-CONFIG_MTD_SWAP=m
-CONFIG_MTD_PARTITIONED_MASTER=y
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_GEN_PROBE=m
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-CONFIG_MTD_CFI_INTELEXT=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_CFI_STAA=m
-CONFIG_MTD_CFI_UTIL=m
-CONFIG_MTD_RAM=m
-CONFIG_MTD_ROM=m
-CONFIG_MTD_ABSENT=m
-# end of RAM/ROM/Flash chip drivers
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=m
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-# CONFIG_MTD_PHYSMAP_OF is not set
-# CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set
-CONFIG_MTD_IMPA7=m
-CONFIG_MTD_PCI=m
-CONFIG_MTD_PCMCIA=m
-# CONFIG_MTD_PCMCIA_ANONYMOUS is not set
-CONFIG_MTD_INTEL_VR_NOR=m
-CONFIG_MTD_PLATRAM=m
-# end of Mapping drivers for chip access
-
-#
-# Self-contained MTD device drivers
-#
-CONFIG_MTD_PMC551=m
-CONFIG_MTD_PMC551_BUGFIX=y
-# CONFIG_MTD_PMC551_DEBUG is not set
-CONFIG_MTD_DATAFLASH=m
-CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
-CONFIG_MTD_DATAFLASH_OTP=y
-CONFIG_MTD_MCHP23K256=m
-CONFIG_MTD_MCHP48L640=m
-CONFIG_MTD_SPEAR_SMI=m
-CONFIG_MTD_SST25L=m
-CONFIG_MTD_BCM47XXSFLASH=m
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTDRAM_TOTAL_SIZE=4096
-CONFIG_MTDRAM_ERASE_SIZE=128
-CONFIG_MTD_BLOCK2MTD=m
-
-#
-# Disk-On-Chip Device Drivers
-#
-CONFIG_MTD_DOCG3=m
-# CONFIG_MTD_ST_SPI_FSM is not set
-CONFIG_BCH_CONST_M=14
-CONFIG_BCH_CONST_T=4
-# end of Self-contained MTD device drivers
-
-#
-# NAND
-#
-CONFIG_MTD_NAND_CORE=m
-CONFIG_MTD_ONENAND=m
-CONFIG_MTD_ONENAND_VERIFY_WRITE=y
-CONFIG_MTD_ONENAND_GENERIC=m
-# CONFIG_MTD_ONENAND_OMAP2 is not set
-# CONFIG_MTD_ONENAND_SAMSUNG is not set
-CONFIG_MTD_ONENAND_OTP=y
-CONFIG_MTD_ONENAND_2X_PROGRAM=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=m
-# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
-CONFIG_MTD_RAW_NAND=m
-CONFIG_MTD_NAND_ECC_SW_BCH=y
-CONFIG_MTD_NAND_ECC_MXIC=y
-
-#
-# Raw/parallel NAND flash controllers
-#
-CONFIG_MTD_NAND_DENALI=m
-# CONFIG_MTD_NAND_DENALI_PCI is not set
-CONFIG_MTD_NAND_DENALI_DT=m
-CONFIG_MTD_NAND_OMAP2=m
-CONFIG_MTD_NAND_OMAP_BCH=y
-# CONFIG_MTD_NAND_OMAP2 is not set
-# CONFIG_MTD_NAND_TANGO is not set
-CONFIG_MTD_NAND_CAFE=m
-# CONFIG_MTD_NAND_ATMEL is not set
-# CONFIG_MTD_NAND_ORION is not set
-# CONFIG_MTD_NAND_MARVELL is not set
-# CONFIG_MTD_NAND_TMIO is not set
-CONFIG_MTD_NAND_BRCMNAND=m
-CONFIG_MTD_NAND_BRCMNAND_BCM63XX=m
-CONFIG_MTD_NAND_BRCMNAND_BCMBCA=m
-CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=m
-CONFIG_MTD_NAND_BRCMNAND_IPROC=m
-# CONFIG_MTD_NAND_MXC is not set
-# CONFIG_MTD_NAND_FSMC is not set
-# CONFIG_MTD_NAND_SUNXI is not set
-# CONFIG_MTD_NAND_HISI504 is not set
-# CONFIG_MTD_NAND_QCOM is not set
-# CONFIG_MTD_NAND_MTK is not set
-CONFIG_MTD_NAND_MXIC=m
-# CONFIG_MTD_NAND_TEGRA is not set
-# CONFIG_MTD_NAND_STM32_FMC2 is not set
-# CONFIG_MTD_NAND_MESON is not set
-CONFIG_MTD_NAND_GPIO=m
-CONFIG_MTD_NAND_PLATFORM=m
-CONFIG_MTD_NAND_CADENCE=m
-CONFIG_MTD_NAND_ARASAN=m
-CONFIG_MTD_NAND_INTEL_LGM=m
-CONFIG_MTD_NAND_ROCKCHIP=m
-CONFIG_MTD_NAND_PL35X=m
-
-#
-# Misc
-#
-CONFIG_MTD_SM_COMMON=m
-CONFIG_MTD_NAND_NANDSIM=m
-CONFIG_MTD_NAND_RICOH=m
-CONFIG_MTD_NAND_DISKONCHIP=m
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
-CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
-CONFIG_MTD_SPI_NAND=m
-
-#
-# ECC engine support
-#
-CONFIG_MTD_NAND_ECC=y
-# end of ECC engine support
-# end of NAND
-
-#
-# LPDDR & LPDDR2 PCM memory drivers
-#
-CONFIG_MTD_LPDDR=m
-CONFIG_MTD_QINFO_PROBE=m
-CONFIG_MTD_LPDDR2_NVM=m
-# end of LPDDR & LPDDR2 PCM memory drivers
-
-CONFIG_MTD_SPI_NOR=m
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SPI_NOR_SWP_DISABLE=y
-# CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE is not set
-# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
-# CONFIG_SPI_ASPEED_SMC is not set
-# CONFIG_SPI_HISI_SFC is not set
-CONFIG_MTD_UBI=m
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_GLUEBI=m
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_HYPERBUS=m
-CONFIG_DTC=y
-CONFIG_OF=y
-# CONFIG_OF_UNITTEST is not set
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_NET=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OF_RESOLVE=y
-CONFIG_OF_OVERLAY=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_PARPORT=m
-CONFIG_PARPORT_PC=m
-CONFIG_PARPORT_SERIAL=m
-CONFIG_PARPORT_PC_FIFO=y
-CONFIG_PARPORT_PC_SUPERIO=y
-CONFIG_PARPORT_PC_PCMCIA=m
-CONFIG_PARPORT_AX88796=m
-CONFIG_PARPORT_1284=y
-CONFIG_PARPORT_NOT_PC=y
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_NULL_BLK is not set
-CONFIG_CDROM=m
-# CONFIG_PARIDE is not set
-CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
-CONFIG_ZRAM=m
-# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
-CONFIG_ZRAM_DEF_COMP_ZSTD=y
-# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
-# CONFIG_ZRAM_DEF_COMP_LZO is not set
-# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
-# CONFIG_ZRAM_DEF_COMP_842 is not set
-CONFIG_ZRAM_WRITEBACK=y
-# CONFIG_ZRAM_MEMORY_TRACKING is not set
-CONFIG_BLK_DEV_UMEM=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_DRBD=m
-# CONFIG_DRBD_FAULT_INJECTION is not set
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_SX8=m
-CONFIG_BLK_DEV_RAM=m
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-CONFIG_CDROM_PKTCDVD_WCACHE=y
-CONFIG_ATA_OVER_ETH=m
-CONFIG_VIRTIO_BLK=m
-CONFIG_BLK_DEV_RBD=m
-CONFIG_BLK_DEV_RSXX=m
-CONFIG_BLK_DEV_RNBD=y
-CONFIG_BLK_DEV_RNBD_CLIENT=m
-CONFIG_BLK_DEV_RNBD_SERVER=m
-
-#
-# NVME Support
-#
-CONFIG_NVME_CORE=m
-CONFIG_BLK_DEV_NVME=m
-CONFIG_NVME_MULTIPATH=y
-CONFIG_NVME_VERBOSE_ERRORS=y
-CONFIG_NVME_HWMON=y
-CONFIG_NVME_FABRICS=m
-CONFIG_NVME_RDMA=m
-CONFIG_NVME_FC=m
-CONFIG_NVME_TCP=m
-CONFIG_NVME_TARGET=m
-CONFIG_NVME_TARGET_PASSTHRU=y
-CONFIG_NVME_TARGET_LOOP=m
-CONFIG_NVME_TARGET_RDMA=m
-CONFIG_NVME_TARGET_FC=m
-CONFIG_NVME_TARGET_FCLOOP=m
-CONFIG_NVME_TARGET_TCP=m
-# end of NVME Support
-
-#
-# Misc devices
-#
-CONFIG_SENSORS_LIS3LV02D=m
-CONFIG_AD525X_DPOT=m
-CONFIG_AD525X_DPOT_I2C=m
-CONFIG_AD525X_DPOT_SPI=m
-# CONFIG_ATMEL_TCLIB is not set
-# CONFIG_DUMMY_IRQ is not set
-CONFIG_PHANTOM=m
-CONFIG_TIFM_CORE=m
-CONFIG_TIFM_7XX1=m
-CONFIG_ICS932S401=m
-# CONFIG_ATMEL_SSC is not set
-CONFIG_ENCLOSURE_SERVICES=m
-CONFIG_HP_ILO=m
-# CONFIG_QCOM_FASTRPC is not set
-CONFIG_APDS9802ALS=m
-CONFIG_ISL29003=m
-CONFIG_ISL29020=m
-CONFIG_SENSORS_TSL2550=m
-CONFIG_SENSORS_BH1770=m
-CONFIG_SENSORS_APDS990X=m
-CONFIG_HMC6352=m
-CONFIG_DS1682=m
-CONFIG_LATTICE_ECP3_CONFIG=m
-CONFIG_SRAM=y
-CONFIG_DW_XDATA_PCIE=m
-CONFIG_SRAM_EXEC=y
-CONFIG_PCI_ENDPOINT_TEST=m
-CONFIG_XILINX_SDFEC=m
-CONFIG_MISC_RTSX=m
-CONFIG_PVPANIC=m
-CONFIG_GP_PCI1XXXX=m
-CONFIG_HISI_HIKEY_USB=m
-CONFIG_OPEN_DICE=m
-CONFIG_C2PORT=m
-
-#
-# EEPROM support
-#
-CONFIG_EEPROM_AT24=m
-CONFIG_EEPROM_AT25=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_EEPROM_MAX6875=m
-CONFIG_EEPROM_93CX6=m
-CONFIG_EEPROM_93XX46=m
-CONFIG_EEPROM_IDT_89HPESX=m
-CONFIG_EEPROM_EE1004=m
-# end of EEPROM support
-
-CONFIG_CB710_CORE=m
-# CONFIG_CB710_DEBUG is not set
-CONFIG_CB710_DEBUG_ASSUMPTIONS=y
-
-#
-# Texas Instruments shared transport line discipline
-#
-CONFIG_TI_ST=m
-# end of Texas Instruments shared transport line discipline
-
-CONFIG_SENSORS_LIS3_SPI=m
-CONFIG_SENSORS_LIS3_I2C=m
-CONFIG_ALTERA_STAPL=m
-
-#
-# Intel MIC & related support
-#
-CONFIG_VOP_BUS=m
-CONFIG_VOP=m
-# end of Intel MIC & related support
-
-CONFIG_ECHO=m
-CONFIG_BCM_VK=m
-CONFIG_BCM_VK_TTY=y
-CONFIG_MISC_ALCOR_PCI=m
-CONFIG_MISC_RTSX_PCI=m
-CONFIG_MISC_RTSX_USB=m
-CONFIG_HABANA_AI=m
-CONFIG_UACCE=m
-CONFIG_PVPANIC=y
-CONFIG_PVPANIC_MMIO=m
-CONFIG_PVPANIC_PCI=m
-# end of Misc devices
-
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=m
-CONFIG_RAID_ATTRS=m
-CONFIG_SCSI=m
-CONFIG_SCSI_DMA=y
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_ENCLOSURE=m
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_ISCSI_ATTRS=m
-CONFIG_SCSI_SAS_ATTRS=m
-CONFIG_SCSI_SAS_LIBSAS=m
-CONFIG_SCSI_SAS_ATA=y
-CONFIG_SCSI_SAS_HOST_SMP=y
-CONFIG_SCSI_SRP_ATTRS=m
-# end of SCSI Transports
-
-CONFIG_SCSI_LOWLEVEL=y
-CONFIG_ISCSI_TCP=m
-CONFIG_ISCSI_BOOT_SYSFS=m
-CONFIG_SCSI_CXGB3_ISCSI=m
-CONFIG_SCSI_CXGB4_ISCSI=m
-CONFIG_SCSI_BNX2_ISCSI=m
-CONFIG_SCSI_BNX2X_FCOE=m
-CONFIG_BE2ISCSI=m
-CONFIG_BLK_DEV_3W_XXXX_RAID=m
-CONFIG_SCSI_HPSA=m
-CONFIG_SCSI_3W_9XXX=m
-CONFIG_SCSI_3W_SAS=m
-CONFIG_SCSI_ACARD=m
-CONFIG_SCSI_AACRAID=m
-CONFIG_SCSI_AIC7XXX=m
-CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
-CONFIG_AIC7XXX_RESET_DELAY_MS=15000
-# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
-CONFIG_AIC7XXX_DEBUG_MASK=0
-# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC79XX=m
-CONFIG_AIC79XX_CMDS_PER_DEVICE=4
-CONFIG_AIC79XX_RESET_DELAY_MS=15000
-# CONFIG_AIC79XX_DEBUG_ENABLE is not set
-CONFIG_AIC79XX_DEBUG_MASK=0
-# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC94XX=m
-# CONFIG_AIC94XX_DEBUG is not set
-CONFIG_SCSI_MVSAS=m
-# CONFIG_SCSI_MVSAS_DEBUG is not set
-CONFIG_SCSI_MVSAS_TASKLET=y
-CONFIG_SCSI_MVUMI=m
-CONFIG_SCSI_ADVANSYS=m
-CONFIG_SCSI_ARCMSR=m
-CONFIG_SCSI_ESAS2R=m
-CONFIG_MEGARAID_NEWGEN=y
-CONFIG_MEGARAID_MM=m
-CONFIG_MEGARAID_MAILBOX=m
-CONFIG_MEGARAID_LEGACY=m
-CONFIG_MEGARAID_SAS=m
-CONFIG_SCSI_MPT3SAS=m
-CONFIG_SCSI_MPT2SAS_MAX_SGE=128
-CONFIG_SCSI_MPT3SAS_MAX_SGE=128
-CONFIG_SCSI_MPT2SAS=m
-CONFIG_SCSI_MPI3MR=m
-CONFIG_SCSI_SMARTPQI=m
-CONFIG_SCSI_UFSHCD=m
-CONFIG_SCSI_UFSHCD_PCI=m
-CONFIG_SCSI_UFS_DWC_TC_PCI=m
-CONFIG_SCSI_UFSHCD_PLATFORM=m
-CONFIG_SCSI_UFS_CDNS_PLATFORM=m
-CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m
-# CONFIG_SCSI_UFS_QCOM is not set
-# CONFIG_SCSI_UFS_MEDIATEK is not set
-# CONFIG_SCSI_UFS_HISI is not set
-CONFIG_SCSI_UFS_RENESAS=m
-# CONFIG_SCSI_UFS_BSG is not set
-CONFIG_SCSI_UFS_EXYNOS=m
-CONFIG_SCSI_HPTIOP=m
-CONFIG_SCSI_MYRB=m
-CONFIG_SCSI_MYRS=m
-CONFIG_LIBFC=m
-CONFIG_LIBFCOE=m
-CONFIG_FCOE=m
-CONFIG_SCSI_SNIC=m
-# CONFIG_SCSI_SNIC_DEBUG_FS is not set
-CONFIG_SCSI_DMX3191D=m
-CONFIG_SCSI_FDOMAIN=m
-CONFIG_SCSI_FDOMAIN_PCI=m
-CONFIG_SCSI_GDTH=m
-CONFIG_SCSI_IPS=m
-CONFIG_SCSI_INITIO=m
-CONFIG_SCSI_INIA100=m
-CONFIG_SCSI_PPA=m
-CONFIG_SCSI_IMM=m
-# CONFIG_SCSI_IZIP_EPP16 is not set
-# CONFIG_SCSI_IZIP_SLOW_CTR is not set
-CONFIG_SCSI_STEX=m
-CONFIG_SCSI_SYM53C8XX_2=m
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_IPR=m
-# CONFIG_SCSI_IPR_TRACE is not set
-# CONFIG_SCSI_IPR_DUMP is not set
-CONFIG_SCSI_QLOGIC_1280=m
-CONFIG_SCSI_QLA_FC=m
-CONFIG_TCM_QLA2XXX=m
-# CONFIG_TCM_QLA2XXX_DEBUG is not set
-CONFIG_SCSI_QLA_ISCSI=m
-CONFIG_QEDI=m
-CONFIG_QEDF=m
-CONFIG_SCSI_LPFC=m
-CONFIG_SCSI_EFCT=m
-# CONFIG_SCSI_LPFC_DEBUG_FS is not set
-CONFIG_SCSI_DC395x=m
-CONFIG_SCSI_AM53C974=m
-# CONFIG_SCSI_NSP32 is not set
-CONFIG_SCSI_WD719X=m
-# CONFIG_SCSI_DEBUG is not set
-CONFIG_SCSI_PMCRAID=m
-CONFIG_SCSI_PM8001=m
-CONFIG_SCSI_BFA_FC=m
-CONFIG_SCSI_VIRTIO=m
-CONFIG_SCSI_CHELSIO_FCOE=m
-CONFIG_SCSI_LOWLEVEL_PCMCIA=y
-CONFIG_PCMCIA_AHA152X=m
-CONFIG_PCMCIA_FDOMAIN=m
-# CONFIG_PCMCIA_NINJA_SCSI is not set
-CONFIG_PCMCIA_QLOGIC=m
-CONFIG_PCMCIA_SYM53C500=m
-CONFIG_SCSI_DH=y
-CONFIG_SCSI_DH_RDAC=m
-CONFIG_SCSI_DH_HP_SW=m
-CONFIG_SCSI_DH_EMC=m
-CONFIG_SCSI_DH_ALUA=m
-# end of SCSI device support
-
-CONFIG_HAVE_PATA_PLATFORM=y
-CONFIG_ATA=m
-CONFIG_SATA_HOST=y
-# CONFIG_ATA_VERBOSE_ERROR is not set
-CONFIG_ATA_FORCE=y
-CONFIG_SATA_PMP=y
-
-#
-# Controllers with non-SFF native interface
-#
-CONFIG_SATA_AHCI=m
-CONFIG_SATA_MOBILE_LPM_POLICY=0
-CONFIG_SATA_AHCI_PLATFORM=m
-# CONFIG_AHCI_DM816 is not set
-CONFIG_AHCI_DWC=m
-# CONFIG_AHCI_ST is not set
-# CONFIG_AHCI_IMX is not set
-CONFIG_AHCI_CEVA=m
-# CONFIG_AHCI_MTK is not set
-# CONFIG_AHCI_MVEBU is not set
-# CONFIG_AHCI_SUNXI is not set
-# CONFIG_AHCI_TEGRA is not set
-CONFIG_AHCI_QORIQ=m
-CONFIG_SATA_INIC162X=m
-CONFIG_SATA_ACARD_AHCI=m
-CONFIG_SATA_SIL24=m
-CONFIG_ATA_SFF=y
-
-#
-# SFF controllers with custom DMA interface
-#
-CONFIG_PDC_ADMA=m
-CONFIG_SATA_QSTOR=m
-CONFIG_SATA_SX4=m
-CONFIG_ATA_BMDMA=y
-
-#
-# SATA SFF controllers with BMDMA
-#
-CONFIG_ATA_PIIX=m
-CONFIG_SATA_DWC=m
-# CONFIG_SATA_DWC_OLD_DMA is not set
-# CONFIG_SATA_DWC_DEBUG is not set
-# CONFIG_SATA_HIGHBANK is not set
-CONFIG_SATA_MV=m
-CONFIG_SATA_NV=m
-CONFIG_SATA_PROMISE=m
-# CONFIG_SATA_RCAR is not set
-CONFIG_SATA_SIL=m
-CONFIG_SATA_SIS=m
-CONFIG_SATA_SVW=m
-CONFIG_SATA_ULI=m
-CONFIG_SATA_VIA=m
-CONFIG_SATA_VITESSE=m
-
-#
-# PATA SFF controllers with BMDMA
-#
-# CONFIG_PATA_ALI is not set
-# CONFIG_PATA_AMD is not set
-# CONFIG_PATA_ARASAN_CF is not set
-# CONFIG_PATA_ARTOP is not set
-# CONFIG_PATA_ATIIXP is not set
-# CONFIG_PATA_ATP867X is not set
-# CONFIG_PATA_CMD64X is not set
-# CONFIG_PATA_CYPRESS is not set
-# CONFIG_PATA_EFAR is not set
-# CONFIG_PATA_HPT366 is not set
-# CONFIG_PATA_HPT37X is not set
-# CONFIG_PATA_HPT3X2N is not set
-# CONFIG_PATA_HPT3X3 is not set
-# CONFIG_PATA_IMX is not set
-# CONFIG_PATA_IT8213 is not set
-# CONFIG_PATA_IT821X is not set
-# CONFIG_PATA_JMICRON is not set
-# CONFIG_PATA_MARVELL is not set
-# CONFIG_PATA_NETCELL is not set
-CONFIG_PATA_NINJA32=m
-# CONFIG_PATA_NS87415 is not set
-# CONFIG_PATA_OLDPIIX is not set
-# CONFIG_PATA_OPTIDMA is not set
-# CONFIG_PATA_PDC2027X is not set
-# CONFIG_PATA_PDC_OLD is not set
-# CONFIG_PATA_RADISYS is not set
-# CONFIG_PATA_RDC is not set
-# CONFIG_PATA_SCH is not set
-# CONFIG_PATA_SERVERWORKS is not set
-# CONFIG_PATA_SIL680 is not set
-CONFIG_PATA_SIS=m
-CONFIG_PATA_TOSHIBA=m
-# CONFIG_PATA_TRIFLEX is not set
-# CONFIG_PATA_VIA is not set
-# CONFIG_PATA_WINBOND is not set
-
-#
-# PIO-only SFF controllers
-#
-# CONFIG_PATA_CMD640_PCI is not set
-# CONFIG_PATA_MPIIX is not set
-# CONFIG_PATA_NS87410 is not set
-# CONFIG_PATA_OPTI is not set
-# CONFIG_PATA_PCMCIA is not set
-# CONFIG_PATA_PLATFORM is not set
-CONFIG_PATA_OF_PLATFORM=m
-# CONFIG_PATA_RZ1000 is not set
-
-#
-# Generic fallback / legacy drivers
-#
-# CONFIG_ATA_GENERIC is not set
-# CONFIG_PATA_LEGACY is not set
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID456=m
-CONFIG_MD_MULTIPATH=m
-CONFIG_MD_FAULTY=m
-CONFIG_MD_CLUSTER=m
-CONFIG_BCACHE=m
-# CONFIG_BCACHE_DEBUG is not set
-# CONFIG_BCACHE_CLOSURES_DEBUG is not set
-CONFIG_BCACHE_ASYNC_REGISTRATION=y
-CONFIG_BLK_DEV_DM_BUILTIN=y
-CONFIG_BLK_DEV_DM=m
-# CONFIG_DM_DEBUG is not set
-CONFIG_DM_BUFIO=m
-# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
-CONFIG_DM_BIO_PRISON=m
-CONFIG_DM_PERSISTENT_DATA=m
-CONFIG_DM_UNSTRIPED=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_THIN_PROVISIONING=m
-CONFIG_DM_CACHE=m
-CONFIG_DM_CACHE_SMQ=m
-CONFIG_DM_WRITECACHE=m
-# CONFIG_DM_EBS is not set
-CONFIG_DM_ERA=m
-CONFIG_DM_CLONE=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_LOG_USERSPACE=m
-CONFIG_DM_RAID=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_QL=m
-CONFIG_DM_MULTIPATH_ST=m
-CONFIG_DM_MULTIPATH_HST=m
-CONFIG_DM_MULTIPATH_IOA=m
-CONFIG_DM_DELAY=m
-CONFIG_DM_DUST=m
-CONFIG_DM_UEVENT=y
-CONFIG_DM_FLAKEY=m
-CONFIG_DM_VERITY=m
-CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
-# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING is not set
-# CONFIG_DM_VERITY_FEC is not set
-CONFIG_DM_SWITCH=m
-CONFIG_DM_LOG_WRITES=m
-CONFIG_DM_INTEGRITY=m
-CONFIG_DM_ZONED=m
-CONFIG_TARGET_CORE=m
-CONFIG_TCM_IBLOCK=m
-CONFIG_TCM_FILEIO=m
-CONFIG_TCM_PSCSI=m
-CONFIG_TCM_USER2=m
-CONFIG_LOOPBACK_TARGET=m
-CONFIG_TCM_FC=m
-CONFIG_ISCSI_TARGET=m
-CONFIG_ISCSI_TARGET_CXGB4=m
-CONFIG_SBP_TARGET=m
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=m
-CONFIG_FUSION_FC=m
-CONFIG_FUSION_SAS=m
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_CTL=m
-CONFIG_FUSION_LAN=m
-CONFIG_FUSION_LOGGING=y
-
-#
-# IEEE 1394 (FireWire) support
-#
-CONFIG_FIREWIRE=m
-CONFIG_FIREWIRE_OHCI=m
-CONFIG_FIREWIRE_SBP2=m
-CONFIG_FIREWIRE_NET=m
-CONFIG_FIREWIRE_NOSY=m
-# end of IEEE 1394 (FireWire) support
-
-CONFIG_NETDEVICES=y
-CONFIG_MII=m
-CONFIG_NET_CORE=y
-CONFIG_BONDING=m
-CONFIG_DUMMY=m
-CONFIG_WIREGUARD=m
-# CONFIG_WIREGUARD_DEBUG is not set
-CONFIG_EQUALIZER=m
-CONFIG_NET_FC=y
-CONFIG_IFB=m
-CONFIG_NET_TEAM=m
-CONFIG_NET_TEAM_MODE_BROADCAST=m
-CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
-CONFIG_NET_TEAM_MODE_RANDOM=m
-CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
-CONFIG_NET_TEAM_MODE_LOADBALANCE=m
-CONFIG_MACVLAN=m
-CONFIG_MACVTAP=m
-CONFIG_IPVLAN_L3S=y
-CONFIG_IPVLAN=m
-CONFIG_IPVTAP=m
-CONFIG_VXLAN=m
-CONFIG_GENEVE=m
-CONFIG_BAREUDP=m
-CONFIG_GTP=m
-CONFIG_MACSEC=m
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_NETPOLL=y
-CONFIG_NET_POLL_CONTROLLER=y
-CONFIG_NTB_NETDEV=m
-CONFIG_RIONET=m
-CONFIG_RIONET_TX_SIZE=128
-CONFIG_RIONET_RX_SIZE=128
-CONFIG_TUN=m
-CONFIG_TAP=m
-# CONFIG_TUN_VNET_CROSS_LE is not set
-CONFIG_VETH=m
-CONFIG_VIRTIO_NET=m
-CONFIG_NLMON=m
-CONFIG_NET_VRF=m
-CONFIG_VSOCKMON=m
-CONFIG_MHI_NET=m
-CONFIG_SUNGEM_PHY=m
-CONFIG_ARCNET=m
-CONFIG_ARCNET_1201=m
-CONFIG_ARCNET_1051=m
-CONFIG_ARCNET_RAW=m
-CONFIG_ARCNET_CAP=m
-CONFIG_ARCNET_COM90xx=m
-CONFIG_ARCNET_COM90xxIO=m
-CONFIG_ARCNET_RIM_I=m
-CONFIG_ARCNET_COM20020=m
-CONFIG_ARCNET_COM20020_PCI=m
-CONFIG_ARCNET_COM20020_CS=m
-CONFIG_ATM_DRIVERS=y
-# CONFIG_ATM_DUMMY is not set
-CONFIG_ATM_TCP=m
-CONFIG_ATM_LANAI=m
-CONFIG_ATM_ENI=m
-# CONFIG_ATM_ENI_DEBUG is not set
-# CONFIG_ATM_ENI_TUNE_BURST is not set
-CONFIG_ATM_NICSTAR=m
-CONFIG_ATM_NICSTAR_USE_SUNI=y
-CONFIG_ATM_NICSTAR_USE_IDT77105=y
-CONFIG_ATM_IDT77252=m
-# CONFIG_ATM_IDT77252_DEBUG is not set
-# CONFIG_ATM_IDT77252_RCV_ALL is not set
-CONFIG_ATM_IDT77252_USE_SUNI=y
-CONFIG_ATM_IA=m
-# CONFIG_ATM_IA_DEBUG is not set
-CONFIG_ATM_FORE200E=m
-CONFIG_ATM_FORE200E_USE_TASKLET=y
-CONFIG_ATM_FORE200E_TX_RETRY=16
-CONFIG_ATM_FORE200E_DEBUG=0
-CONFIG_ATM_HE=m
-CONFIG_ATM_HE_USE_SUNI=y
-CONFIG_ATM_SOLOS=m
-# CONFIG_CAIF_DRIVERS is not set
-
-#
-# Distributed Switch Architecture drivers
-#
-CONFIG_B53=m
-CONFIG_B53_SPI_DRIVER=m
-CONFIG_B53_MDIO_DRIVER=m
-CONFIG_B53_MMAP_DRIVER=m
-CONFIG_B53_SRAB_DRIVER=m
-CONFIG_B53_SERDES=m
-CONFIG_NET_DSA_BCM_SF2=m
-CONFIG_NET_DSA_LOOP=m
-CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
-CONFIG_NET_DSA_LANTIQ_GSWIP=m
-CONFIG_NET_DSA_MT7530=m
-CONFIG_NET_DSA_MV88E6060=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-CONFIG_NET_DSA_MV88E6XXX=m
-CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
-CONFIG_NET_DSA_MV88E6XXX_PTP=y
-# CONFIG_NET_DSA_MSCC_FELIX is not set
-CONFIG_NET_DSA_MSCC_SEVILLE=m
-CONFIG_NET_DSA_AR9331=m
-CONFIG_NET_DSA_SJA1105=m
-CONFIG_NET_DSA_SJA1105_PTP=y
-CONFIG_NET_DSA_SJA1105_TAS=y
-# CONFIG_NET_DSA_SJA1105_VL is not set
-CONFIG_NET_DSA_XRS700X_I2C=m
-CONFIG_NET_DSA_XRS700X_MDIO=m
-CONFIG_NET_DSA_QCA8K=m
-CONFIG_NET_DSA_REALTEK_SMI=m
-CONFIG_NET_DSA_SMSC_LAN9303=m
-CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
-CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
-CONFIG_NET_DSA_VITESSE_VSC73XX=m
-CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
-CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
-# end of Distributed Switch Architecture drivers
-
-CONFIG_ETHERNET=y
-CONFIG_MDIO=m
-CONFIG_NET_VENDOR_3COM=y
-CONFIG_NET_VENDOR_ACTIONS=y
-CONFIG_OWL_EMAC=m
-CONFIG_PCMCIA_3C574=m
-CONFIG_PCMCIA_3C589=m
-CONFIG_TYPHOON=m
-CONFIG_NET_VENDOR_ADAPTEC=y
-CONFIG_ADAPTEC_STARFIRE=m
-CONFIG_NET_VENDOR_AGERE=y
-CONFIG_ET131X=m
-CONFIG_NET_VENDOR_ALACRITECH=y
-CONFIG_SLICOSS=m
-CONFIG_NET_VENDOR_ALLWINNER=y
-# CONFIG_SUN4I_EMAC is not set
-CONFIG_NET_VENDOR_ALTEON=y
-CONFIG_ACENIC=m
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
-CONFIG_ALTERA_TSE=m
-CONFIG_NET_VENDOR_AMAZON=y
-CONFIG_ENA_ETHERNET=m
-CONFIG_NET_VENDOR_AMD=y
-CONFIG_AMD8111_ETH=m
-CONFIG_PCNET32=m
-CONFIG_PCMCIA_NMCLAN=m
-CONFIG_NET_VENDOR_AQUANTIA=y
-CONFIG_AQTION=m
-CONFIG_NET_VENDOR_ARC=y
-# CONFIG_EMAC_ROCKCHIP is not set
-CONFIG_NET_VENDOR_ATHEROS=y
-CONFIG_ATL2=m
-CONFIG_ATL1=m
-CONFIG_ATL1E=m
-CONFIG_ATL1C=m
-CONFIG_ALX=m
-CONFIG_NET_VENDOR_AURORA=y
-CONFIG_AURORA_NB8800=m
-CONFIG_NET_VENDOR_BROADCOM=y
-CONFIG_B44=m
-CONFIG_BCM4908_ENET=m
-CONFIG_B44_PCI_AUTOSELECT=y
-CONFIG_B44_PCICORE_AUTOSELECT=y
-CONFIG_B44_PCI=y
-CONFIG_BCMGENET=m
-CONFIG_BNX2=m
-CONFIG_CNIC=m
-CONFIG_TIGON3=m
-CONFIG_TIGON3_HWMON=y
-CONFIG_BNX2X=m
-CONFIG_BNX2X_SRIOV=y
-CONFIG_SYSTEMPORT=m
-CONFIG_BNXT=m
-CONFIG_BNXT_SRIOV=y
-CONFIG_BNXT_FLOWER_OFFLOAD=y
-CONFIG_BNXT_DCB=y
-CONFIG_BNXT_HWMON=y
-CONFIG_NET_VENDOR_BROCADE=y
-CONFIG_BNA=m
-CONFIG_NET_VENDOR_CADENCE=y
-CONFIG_MACB=m
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MACB_PCI=m
-# CONFIG_NET_CALXEDA_XGMAC is not set
-CONFIG_NET_VENDOR_CAVIUM=y
-CONFIG_NET_VENDOR_CHELSIO=y
-CONFIG_CHELSIO_T1=m
-CONFIG_CHELSIO_T1_1G=y
-CONFIG_CHELSIO_T3=m
-CONFIG_CHELSIO_T4=m
-CONFIG_CHELSIO_T4_DCB=y
-# CONFIG_CHELSIO_T4_FCOE is not set
-CONFIG_CHELSIO_T4VF=m
-CONFIG_CHELSIO_LIB=m
-CONFIG_CHELSIO_INLINE_CRYPTO=y
-CONFIG_CHELSIO_IPSEC_INLINE=m
-CONFIG_CHELSIO_TLS_DEVICE=m
-CONFIG_NET_VENDOR_CIRRUS=y
-# CONFIG_CS89x0 is not set
-CONFIG_NET_VENDOR_CISCO=y
-CONFIG_ENIC=m
-# CONFIG_NET_VENDOR_CORTINA is not set
-CONFIG_NET_VENDOR_DAVICOM=y
-CONFIG_DM9051=m
-# CONFIG_DM9000 is not set
-CONFIG_DM9051=m
-CONFIG_DNET=m
-CONFIG_NET_VENDOR_DEC=y
-CONFIG_NET_TULIP=y
-CONFIG_DE2104X=m
-CONFIG_DE2104X_DSL=0
-CONFIG_TULIP=m
-CONFIG_TULIP_MWI=y
-CONFIG_TULIP_MMIO=y
-CONFIG_TULIP_NAPI=y
-CONFIG_TULIP_NAPI_HW_MITIGATION=y
-CONFIG_WINBOND_840=m
-CONFIG_DM9102=m
-CONFIG_ULI526X=m
-CONFIG_PCMCIA_XIRCOM=m
-CONFIG_NET_VENDOR_DLINK=y
-CONFIG_DL2K=m
-CONFIG_SUNDANCE=m
-# CONFIG_SUNDANCE_MMIO is not set
-CONFIG_NET_VENDOR_EMULEX=y
-CONFIG_BE2NET=m
-CONFIG_BE2NET_HWMON=y
-CONFIG_BE2NET_BE2=y
-CONFIG_BE2NET_BE3=y
-CONFIG_BE2NET_LANCER=y
-CONFIG_BE2NET_SKYHAWK=y
-CONFIG_NET_VENDOR_EZCHIP=y
-# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
-CONFIG_NET_VENDOR_FARADAY=y
-# CONFIG_FTMAC100 is not set
-# CONFIG_FTGMAC100 is not set
-CONFIG_NET_VENDOR_FREESCALE=y
-CONFIG_FEC=y
-# CONFIG_FSL_PQ_MDIO is not set
-# CONFIG_FSL_XGMAC_MDIO is not set
-# CONFIG_GIANFAR is not set
-CONFIG_FSL_DPAA2_SWITCH=m
-# CONFIG_FSL_ENETC is not set
-# CONFIG_FSL_ENETC_VF is not set
-CONFIG_FSL_ENETC_IERB=m
-# CONFIG_FSL_ENETC_MDIO is not set
-CONFIG_NET_VENDOR_FUJITSU=y
-CONFIG_NET_VENDOR_FUNGIBLE=y
-CONFIG_FUN_ETH=m
-CONFIG_PCMCIA_FMVJ18X=m
-CONFIG_NET_VENDOR_GOOGLE=y
-CONFIG_GVE=m
-CONFIG_NET_VENDOR_HISILICON=y
-# CONFIG_HIX5HD2_GMAC is not set
-# CONFIG_HISI_FEMAC is not set
-# CONFIG_HIP04_ETH is not set
-# CONFIG_HNS_DSAF is not set
-# CONFIG_HNS_ENET is not set
-# CONFIG_HNS3 is not set
-CONFIG_NET_VENDOR_HUAWEI=y
-CONFIG_NET_VENDOR_I825XX=y
-CONFIG_NET_VENDOR_INTEL=y
-CONFIG_E100=m
-CONFIG_E1000=m
-CONFIG_E1000E=m
-CONFIG_IGB=m
-CONFIG_IGB_HWMON=y
-CONFIG_IGBVF=m
-CONFIG_IXGB=m
-CONFIG_IXGBE=m
-CONFIG_IXGBE_HWMON=y
-CONFIG_IXGBE_DCB=y
-CONFIG_IXGBE_IPSEC=y
-CONFIG_IXGBEVF=m
-CONFIG_IXGBEVF_IPSEC=y
-CONFIG_I40E=m
-CONFIG_I40E_DCB=y
-CONFIG_IAVF=m
-CONFIG_I40EVF=m
-CONFIG_ICE=m
-CONFIG_FM10K=m
-CONFIG_IGC=m
-CONFIG_NET_VENDOR_MICROSOFT=y
-CONFIG_JME=m
-CONFIG_NET_VENDOR_MARVELL=y
-# CONFIG_MV643XX_ETH is not set
-CONFIG_MVMDIO=m
-# CONFIG_MVNETA is not set
-# CONFIG_MVPP2 is not set
-CONFIG_MVPP2_PTP=y
-# CONFIG_PXA168_ETH is not set
-CONFIG_SKGE=m
-# CONFIG_SKGE_DEBUG is not set
-CONFIG_SKGE_GENESIS=y
-CONFIG_SKY2=m
-# CONFIG_SKY2_DEBUG is not set
-CONFIG_PRESTERA=m
-CONFIG_PRESTERA_PCI=m
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NET_MEDIATEK_SOC=m
-CONFIG_NET_MEDIATEK_STAR_EMAC=m
-CONFIG_NET_VENDOR_MELLANOX=y
-CONFIG_MLX4_EN=m
-CONFIG_MLX4_EN_DCB=y
-CONFIG_MLX4_CORE=m
-# CONFIG_MLX4_DEBUG is not set
-CONFIG_MLX4_CORE_GEN2=y
-CONFIG_MLX5_CORE=m
-CONFIG_MLX5_ACCEL=y
-CONFIG_MLX5_FPGA=y
-# CONFIG_MLX5_CORE_EN is not set
-CONFIG_MLX5_FPGA_IPSEC=y
-CONFIG_MLXSW_CORE=m
-CONFIG_MLXSW_CORE_HWMON=y
-CONFIG_MLXSW_CORE_THERMAL=y
-CONFIG_MLXSW_PCI=m
-CONFIG_MLXSW_I2C=m
-CONFIG_MLXSW_SWITCHIB=m
-CONFIG_MLXSW_SWITCHX2=m
-CONFIG_MLXSW_SPECTRUM=m
-CONFIG_MLXSW_SPECTRUM_DCB=y
-CONFIG_MLXSW_MINIMAL=m
-CONFIG_MLXFW=m
-CONFIG_MLXFW_GIGE=m
-CONFIG_MLXBF_GIGE=m
-CONFIG_NET_VENDOR_MICREL=y
-CONFIG_KS8842=m
-CONFIG_KS8851=m
-CONFIG_KS8851_MLL=m
-CONFIG_KSZ884X_PCI=m
-CONFIG_NET_VENDOR_MICROCHIP=y
-CONFIG_ENC28J60=m
-# CONFIG_ENC28J60_WRITEVERIFY is not set
-CONFIG_ENCX24J600=m
-CONFIG_LAN743X=m
-CONFIG_SPARX5_SWITCH=m
-CONFIG_NET_VENDOR_MICROSEMI=y
-CONFIG_MSCC_OCELOT_SWITCH_LIB=m
-CONFIG_MSCC_OCELOT_SWITCH=m
-CONFIG_NET_VENDOR_MYRI=y
-CONFIG_MYRI10GE=m
-CONFIG_FEALNX=m
-CONFIG_NET_VENDOR_NATSEMI=y
-CONFIG_NATSEMI=m
-CONFIG_NS83820=m
-CONFIG_NET_VENDOR_NETERION=y
-CONFIG_S2IO=m
-CONFIG_VXGE=m
-# CONFIG_VXGE_DEBUG_TRACE_ALL is not set
-CONFIG_NET_VENDOR_NETRONOME=y
-CONFIG_NFP=m
-# CONFIG_NFP_APP_FLOWER is not set
-CONFIG_NFP_APP_ABM_NIC=y
-# CONFIG_NFP_DEBUG is not set
-CONFIG_NET_VENDOR_NI=y
-CONFIG_NI_XGE_MANAGEMENT_ENET=m
-CONFIG_NET_VENDOR_8390=y
-CONFIG_PCMCIA_AXNET=m
-# CONFIG_AX88796 is not set
-CONFIG_NE2K_PCI=m
-CONFIG_PCMCIA_PCNET=m
-CONFIG_NET_VENDOR_NVIDIA=y
-CONFIG_FORCEDETH=m
-CONFIG_NET_VENDOR_OKI=y
-CONFIG_ETHOC=m
-CONFIG_NET_VENDOR_PACKET_ENGINES=y
-CONFIG_HAMACHI=m
-CONFIG_YELLOWFIN=m
-CONFIG_NET_VENDOR_PENSANDO=y
-CONFIG_NET_VENDOR_QLOGIC=y
-CONFIG_QLA3XXX=m
-CONFIG_QLCNIC=m
-CONFIG_QLCNIC_SRIOV=y
-CONFIG_QLCNIC_DCB=y
-CONFIG_QLCNIC_HWMON=y
-CONFIG_NETXEN_NIC=m
-CONFIG_QED=m
-CONFIG_QED_LL2=y
-CONFIG_QED_SRIOV=y
-CONFIG_QEDE=m
-CONFIG_QED_ISCSI=y
-CONFIG_QED_FCOE=y
-CONFIG_QED_OOO=y
-CONFIG_NET_VENDOR_QUALCOMM=y
-# CONFIG_QCA7000_SPI is not set
-# CONFIG_QCA7000_UART is not set
-CONFIG_QCOM_EMAC=m
-CONFIG_RMNET=m
-CONFIG_NET_VENDOR_RDC=y
-CONFIG_R6040=m
-CONFIG_NET_VENDOR_REALTEK=y
-CONFIG_8139CP=m
-CONFIG_8139TOO=m
-# CONFIG_8139TOO_PIO is not set
-CONFIG_8139TOO_TUNE_TWISTER=y
-CONFIG_8139TOO_8129=y
-# CONFIG_8139_OLD_RX_RESET is not set
-CONFIG_R8169=m
-CONFIG_NET_VENDOR_RENESAS=y
-# CONFIG_SH_ETH is not set
-# CONFIG_RAVB is not set
-CONFIG_NET_VENDOR_ROCKER=y
-CONFIG_ROCKER=m
-CONFIG_NET_VENDOR_SAMSUNG=y
-CONFIG_SXGBE_ETH=m
-CONFIG_NET_VENDOR_SEEQ=y
-CONFIG_NET_VENDOR_SOLARFLARE=y
-CONFIG_SFC=m
-CONFIG_SFC_MTD=y
-CONFIG_SFC_MCDI_MON=y
-CONFIG_SFC_SRIOV=y
-CONFIG_SFC_MCDI_LOGGING=y
-CONFIG_SFC_FALCON=m
-CONFIG_SFC_FALCON_MTD=y
-CONFIG_NET_VENDOR_SILAN=y
-CONFIG_SC92031=m
-CONFIG_NET_VENDOR_SIS=y
-CONFIG_SIS900=m
-CONFIG_SIS190=m
-CONFIG_NET_VENDOR_SMSC=y
-# CONFIG_SMC91X is not set
-CONFIG_PCMCIA_SMC91C92=m
-CONFIG_EPIC100=m
-# CONFIG_SMC911X is not set
-CONFIG_SMSC911X=m
-CONFIG_SMSC9420=m
-# CONFIG_NET_VENDOR_SOCIONEXT is not set
-CONFIG_NET_VENDOR_STMICRO=y
-CONFIG_STMMAC_ETH=m
-# CONFIG_STMMAC_SELFTESTS is not set
-CONFIG_STMMAC_PLATFORM=m
-CONFIG_DWMAC_LOONGSON=m
-# CONFIG_DWMAC_DWC_QOS_ETH is not set
-CONFIG_DWMAC_GENERIC=m
-CONFIG_DWMAC_IPQ806X=m
-# CONFIG_DWMAC_MEDIATEK is not set
-CONFIG_DWMAC_MESON=m
-CONFIG_DWMAC_QCOM_ETHQOS=m
-CONFIG_DWMAC_ROCKCHIP=y
-CONFIG_DWMAC_SOCFPGA=m
-CONFIG_DWMAC_STI=m
-CONFIG_DWMAC_STM32=m
-CONFIG_DWMAC_SUNXI=m
-CONFIG_DWMAC_SUN8I=m
-CONFIG_DWMAC_IMX8=m
-CONFIG_DWMAC_INTEL_PLAT=m
-CONFIG_DWMAC_VISCONTI=m
-CONFIG_STMMAC_PCI=m
-CONFIG_NET_VENDOR_SUN=y
-CONFIG_HAPPYMEAL=m
-CONFIG_SUNGEM=m
-CONFIG_CASSINI=m
-CONFIG_NIU=m
-CONFIG_NET_VENDOR_SYNOPSYS=y
-CONFIG_DWC_XLGMAC=m
-CONFIG_DWC_XLGMAC_PCI=m
-CONFIG_NET_VENDOR_TEHUTI=y
-CONFIG_TEHUTI=m
-CONFIG_NET_VENDOR_TI=y
-# CONFIG_TI_DAVINCI_EMAC is not set
-# CONFIG_TI_DAVINCI_MDIO is not set
-# CONFIG_TI_CPSW_PHY_SEL is not set
-# CONFIG_TI_CPSW is not set
-# CONFIG_TI_CPSW_SWITCHDEV is not set
-# CONFIG_TI_CPTS is not set
-CONFIG_TLAN=m
-CONFIG_NET_VENDOR_VIA=y
-CONFIG_VIA_RHINE=m
-CONFIG_VIA_RHINE_MMIO=y
-CONFIG_VIA_VELOCITY=m
-CONFIG_NET_VENDOR_WIZNET=y
-CONFIG_WIZNET_W5100=m
-CONFIG_WIZNET_W5300=m
-# CONFIG_WIZNET_BUS_DIRECT is not set
-# CONFIG_WIZNET_BUS_INDIRECT is not set
-CONFIG_WIZNET_BUS_ANY=y
-CONFIG_WIZNET_W5100_SPI=m
-CONFIG_NET_VENDOR_XILINX=y
-CONFIG_XILINX_EMACLITE=m
-# CONFIG_XILINX_EMACLITE is not set
-CONFIG_XILINX_AXI_EMAC=m
-CONFIG_XILINX_LL_TEMAC=m
-CONFIG_NET_VENDOR_XIRCOM=y
-CONFIG_PCMCIA_XIRC2PS=m
-CONFIG_FDDI=m
-CONFIG_DEFXX=m
-# CONFIG_DEFXX_MMIO is not set
-CONFIG_SKFP=m
-CONFIG_HIPPI=y
-CONFIG_ROADRUNNER=m
-CONFIG_ROADRUNNER_LARGE_RINGS=y
-CONFIG_PHYLINK=m
-CONFIG_PHYLIB=y
-CONFIG_SWPHY=y
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_FIXED_PHY=y
-CONFIG_SFP=m
-
-#
-# MII PHY device drivers
-#
-CONFIG_AMD_PHY=m
-# CONFIG_MESON_GXL_PHY is not set
-CONFIG_ADIN_PHY=m
-CONFIG_AQUANTIA_PHY=m
-CONFIG_AX88796B_PHY=m
-CONFIG_BROADCOM_PHY=m
-CONFIG_BCM54140_PHY=m
-CONFIG_BCM7XXX_PHY=m
-CONFIG_BCM84881_PHY=m
-CONFIG_BCM87XX_PHY=m
-CONFIG_BCM_NET_PHYLIB=m
-CONFIG_CICADA_PHY=m
-CONFIG_CORTINA_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_ICPLUS_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_INTEL_XWAY_PHY=m
-CONFIG_LSI_ET1011C_PHY=m
-CONFIG_MARVELL_PHY=m
-CONFIG_MARVELL_10G_PHY=m
-CONFIG_MARVELL_88X2222_PHY=m
-CONFIG_MEDIATEK_GE_PHY=m
-CONFIG_MICREL_PHY=m
-CONFIG_MICROCHIP_PHY=m
-CONFIG_MICROCHIP_T1_PHY=m
-CONFIG_MICROSEMI_PHY=m
-CONFIG_MOTORCOMM_PHY=m
-CONFIG_NATIONAL_PHY=m
-CONFIG_NXP_C45_TJA11XX_PHY=m
-CONFIG_NXP_TJA11XX_PHY=m
-CONFIG_AT803X_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_REALTEK_PHY=m
-CONFIG_RENESAS_PHY=m
-CONFIG_ROCKCHIP_PHY=m
-CONFIG_SMSC_PHY=m
-CONFIG_STE10XP=m
-CONFIG_TERANETICS_PHY=m
-CONFIG_DP83822_PHY=m
-CONFIG_DP83TC811_PHY=m
-CONFIG_DP83848_PHY=m
-CONFIG_DP83867_PHY=m
-CONFIG_DP83869_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_XILINX_GMII2RGMII=m
-CONFIG_WWAN=y
-CONFIG_WWAN_HWSIM=m
-CONFIG_WWAN_CORE=m
-CONFIG_RPMSG_WWAN_CTRL=m
-CONFIG_IOSM=m
-# CONFIG_TEST_MAPLE_TREE is not set
-CONFIG_MHI_WWAN_CTRL=m
-CONFIG_MICREL_KS8995MA=m
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_BUS=y
-CONFIG_OF_MDIO=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MDIO_SUN4I is not set
-# CONFIG_MDIO_ASPEED is not set
-CONFIG_MDIO_BITBANG=m
-CONFIG_MDIO_BCM_UNIMAC=m
-CONFIG_MDIO_GPIO=m
-# CONFIG_MDIO_HISI_FEMAC is not set
-CONFIG_MDIO_I2C=m
-CONFIG_MDIO_MVUSB=m
-CONFIG_MDIO_MSCC_MIIM=m
-# CONFIG_MDIO_IPQ4019 is not set
-# CONFIG_MDIO_IPQ8064 is not set
-
-#
-# MDIO Multiplexers
-#
-CONFIG_MDIO_BUS_MUX=m
-CONFIG_MDIO_BUS_MUX_MESON_G12A=m
-# CONFIG_MDIO_BUS_MUX_GPIO is not set
-# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
-# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
-
-#
-# PCS device drivers
-#
-CONFIG_PCS_XPCS=m
-CONFIG_PCS_LYNX=m
-# end of PCS device drivers
-
-CONFIG_PLIP=m
-CONFIG_PPP=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_MPPE=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPPOATM=m
-CONFIG_PPPOE=m
-CONFIG_PPTP=m
-CONFIG_PPPOL2TP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_SLIP=m
-CONFIG_SLHC=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-
-#
-# Host-side USB support is needed for USB Network Adapter support
-#
-CONFIG_USB_NET_DRIVERS=m
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_RTL8152=m
-CONFIG_USB_LAN78XX=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_AX8817X=m
-CONFIG_USB_NET_AX88179_178A=m
-CONFIG_USB_NET_CDCETHER=m
-CONFIG_USB_NET_CDC_EEM=m
-CONFIG_USB_NET_CDC_NCM=m
-CONFIG_USB_NET_HUAWEI_CDC_NCM=m
-CONFIG_USB_NET_CDC_MBIM=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_SR9700=m
-CONFIG_USB_NET_SR9800=m
-CONFIG_USB_NET_SMSC75XX=m
-CONFIG_USB_NET_SMSC95XX=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_NET1080=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_MCS7830=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
-CONFIG_USB_NET_CDC_SUBSET=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_BELKIN=y
-CONFIG_USB_ARMLINUX=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-CONFIG_USB_NET_ZAURUS=m
-CONFIG_USB_NET_CX82310_ETH=m
-CONFIG_USB_NET_KALMIA=m
-CONFIG_USB_NET_QMI_WWAN=m
-CONFIG_USB_HSO=m
-CONFIG_USB_NET_INT51X1=m
-CONFIG_USB_CDC_PHONET=m
-CONFIG_USB_IPHETH=m
-CONFIG_USB_SIERRA_NET=m
-CONFIG_USB_VL600=m
-CONFIG_USB_NET_CH9200=m
-CONFIG_USB_NET_AQC111=m
-CONFIG_USB_RTL8153_ECM=m
-CONFIG_WLAN=y
-# CONFIG_WIRELESS_WDS is not set
-CONFIG_WLAN_VENDOR_ADMTEK=y
-CONFIG_ADM8211=m
-CONFIG_ATH_COMMON=m
-CONFIG_WLAN_VENDOR_ATH=y
-# CONFIG_ATH_DEBUG is not set
-CONFIG_ATH5K=m
-# CONFIG_ATH5K_DEBUG is not set
-# CONFIG_ATH5K_TRACER is not set
-CONFIG_ATH5K_PCI=y
-CONFIG_ATH9K_HW=m
-CONFIG_ATH9K_COMMON=m
-CONFIG_ATH9K_BTCOEX_SUPPORT=y
-CONFIG_ATH9K=m
-CONFIG_ATH9K_PCI=y
-CONFIG_ATH9K_AHB=y
-# CONFIG_ATH9K_DEBUGFS is not set
-CONFIG_ATH9K_DYNACK=y
-CONFIG_ATH9K_WOW=y
-CONFIG_ATH9K_RFKILL=y
-CONFIG_ATH9K_CHANNEL_CONTEXT=y
-CONFIG_ATH9K_PCOEM=y
-CONFIG_ATH9K_PCI_NO_EEPROM=m
-CONFIG_ATH9K_HTC=m
-# CONFIG_ATH9K_HTC_DEBUGFS is not set
-CONFIG_ATH9K_HWRNG=y
-CONFIG_CARL9170=m
-CONFIG_CARL9170_LEDS=y
-CONFIG_CARL9170_WPC=y
-# CONFIG_CARL9170_HWRNG is not set
-CONFIG_ATH6KL=m
-CONFIG_ATH6KL_SDIO=m
-CONFIG_ATH6KL_USB=m
-# CONFIG_ATH6KL_DEBUG is not set
-# CONFIG_ATH6KL_TRACING is not set
-CONFIG_AR5523=m
-CONFIG_WIL6210=m
-CONFIG_WIL6210_ISR_COR=y
-CONFIG_WIL6210_TRACING=y
-CONFIG_WIL6210_DEBUGFS=y
-CONFIG_ATH10K=m
-CONFIG_ATH10K_CE=y
-CONFIG_ATH10K_PCI=m
-# CONFIG_ATH10K_AHB is not set
-CONFIG_ATH10K_SDIO=m
-CONFIG_ATH10K_USB=m
-# CONFIG_ATH10K_SNOC is not set
-# CONFIG_ATH10K_DEBUG is not set
-# CONFIG_ATH10K_DEBUGFS is not set
-# CONFIG_ATH10K_TRACING is not set
-CONFIG_WCN36XX=m
-# CONFIG_WCN36XX_DEBUGFS is not set
-CONFIG_ATH11K=m
-CONFIG_ATH11K_PCI=m
-# CONFIG_ATH11K_DEBUG is not set
-# CONFIG_ATH11K_TRACING is not set
-CONFIG_WLAN_VENDOR_ATMEL=y
-CONFIG_ATMEL=m
-CONFIG_PCI_ATMEL=m
-CONFIG_PCMCIA_ATMEL=m
-CONFIG_AT76C50X_USB=m
-CONFIG_WLAN_VENDOR_BROADCOM=y
-CONFIG_B43=m
-CONFIG_B43_BCMA=y
-CONFIG_B43_SSB=y
-CONFIG_B43_BUSES_BCMA_AND_SSB=y
-# CONFIG_B43_BUSES_BCMA is not set
-# CONFIG_B43_BUSES_SSB is not set
-CONFIG_B43_PCI_AUTOSELECT=y
-CONFIG_B43_PCICORE_AUTOSELECT=y
-CONFIG_B43_SDIO=y
-CONFIG_B43_BCMA_PIO=y
-CONFIG_B43_PIO=y
-CONFIG_B43_PHY_G=y
-CONFIG_B43_PHY_N=y
-CONFIG_B43_PHY_LP=y
-CONFIG_B43_PHY_HT=y
-CONFIG_B43_LEDS=y
-CONFIG_B43_HWRNG=y
-# CONFIG_B43_DEBUG is not set
-CONFIG_B43LEGACY=m
-CONFIG_B43LEGACY_PCI_AUTOSELECT=y
-CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
-CONFIG_B43LEGACY_LEDS=y
-CONFIG_B43LEGACY_HWRNG=y
-# CONFIG_B43LEGACY_DEBUG is not set
-CONFIG_B43LEGACY_DMA=y
-CONFIG_B43LEGACY_PIO=y
-CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
-# CONFIG_B43LEGACY_DMA_MODE is not set
-# CONFIG_B43LEGACY_PIO_MODE is not set
-CONFIG_BRCMUTIL=m
-CONFIG_BRCMSMAC=m
-CONFIG_BRCMFMAC=m
-CONFIG_BRCMFMAC_PROTO_BCDC=y
-CONFIG_BRCMFMAC_PROTO_MSGBUF=y
-CONFIG_BRCMFMAC_SDIO=y
-CONFIG_BRCMFMAC_USB=y
-CONFIG_BRCMFMAC_PCIE=y
-CONFIG_BRCM_TRACING=y
-# CONFIG_BRCMDBG is not set
-CONFIG_WLAN_VENDOR_CISCO=y
-CONFIG_AIRO_CS=m
-CONFIG_WLAN_VENDOR_INTEL=y
-CONFIG_IPW2100=m
-CONFIG_IPW2100_MONITOR=y
-# CONFIG_IPW2100_DEBUG is not set
-CONFIG_IPW2200=m
-CONFIG_IPW2200_MONITOR=y
-CONFIG_IPW2200_RADIOTAP=y
-CONFIG_IPW2200_PROMISCUOUS=y
-CONFIG_IPW2200_QOS=y
-# CONFIG_IPW2200_DEBUG is not set
-CONFIG_LIBIPW=m
-# CONFIG_LIBIPW_DEBUG is not set
-CONFIG_IWLEGACY=m
-CONFIG_IWL4965=m
-CONFIG_IWL3945=m
-
-#
-# iwl3945 / iwl4965 Debugging Options
-#
-# CONFIG_IWLEGACY_DEBUG is not set
-# end of iwl3945 / iwl4965 Debugging Options
-
-CONFIG_IWLWIFI=m
-CONFIG_IWLWIFI_LEDS=y
-CONFIG_IWLDVM=m
-CONFIG_IWLMVM=m
-CONFIG_IWLWIFI_OPMODE_MODULAR=y
-# CONFIG_IWLWIFI_BCAST_FILTERING is not set
-CONFIG_IWLMEI=m
-
-#
-# Debugging Options
-#
-# CONFIG_IWLWIFI_DEBUG is not set
-CONFIG_IWLWIFI_DEVICE_TRACING=y
-# end of Debugging Options
-
-CONFIG_WLAN_VENDOR_INTERSIL=y
-CONFIG_HOSTAP=m
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_HOSTAP_PLX=m
-CONFIG_HOSTAP_PCI=m
-CONFIG_HOSTAP_CS=m
-CONFIG_HERMES=m
-CONFIG_HERMES_PRISM=y
-CONFIG_HERMES_CACHE_FW_ON_INIT=y
-CONFIG_PLX_HERMES=m
-CONFIG_TMD_HERMES=m
-CONFIG_NORTEL_HERMES=m
-CONFIG_PCI_HERMES=m
-CONFIG_ORINOCO_USB=m
-CONFIG_P54_COMMON=m
-CONFIG_P54_USB=m
-CONFIG_P54_PCI=m
-CONFIG_P54_SPI=m
-CONFIG_P54_SPI_DEFAULT_EEPROM=y
-CONFIG_P54_LEDS=y
-CONFIG_PRISM54=m
-CONFIG_WLAN_VENDOR_MARVELL=y
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_USB=m
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_LIBERTAS_SPI=m
-# CONFIG_LIBERTAS_DEBUG is not set
-CONFIG_LIBERTAS_MESH=y
-CONFIG_LIBERTAS_THINFIRM=m
-# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
-CONFIG_LIBERTAS_THINFIRM_USB=m
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
-CONFIG_MWIFIEX_PCIE=m
-CONFIG_MWIFIEX_USB=m
-CONFIG_MWL8K=m
-CONFIG_WLAN_VENDOR_MEDIATEK=y
-CONFIG_MT7601U=m
-CONFIG_MT76_CORE=m
-CONFIG_MT76_LEDS=y
-CONFIG_MT76_USB=m
-CONFIG_MT76_SDIO=m
-CONFIG_MT76x02_LIB=m
-CONFIG_MT76x02_USB=m
-CONFIG_MT76x0_COMMON=m
-CONFIG_MT76x0U=m
-CONFIG_MT76x0E=m
-CONFIG_MT76x2_COMMON=m
-CONFIG_MT76x2E=m
-CONFIG_MT76x2U=m
-CONFIG_MT7603E=m
-CONFIG_MT7615_COMMON=m
-CONFIG_MT7615E=m
-CONFIG_MT7622_WMAC=y
-CONFIG_MT7663_USB_SDIO_COMMON=m
-CONFIG_MT7663U=m
-CONFIG_MT7663S=m
-CONFIG_MT7915E=m
-CONFIG_MT7986_WMAC=y
-CONFIG_MT7921E=m
-CONFIG_WLAN_VENDOR_MICROCHIP=y
-CONFIG_WILC1000=m
-CONFIG_WILC1000_SDIO=m
-CONFIG_WILC1000_SPI=m
-# CONFIG_WILC1000_HW_OOB_INTR is not set
-CONFIG_WLAN_VENDOR_RALINK=y
-CONFIG_RT2X00=m
-CONFIG_RT2400PCI=m
-CONFIG_RT2500PCI=m
-CONFIG_RT61PCI=m
-CONFIG_RT2800PCI=m
-CONFIG_RT2800PCI_RT33XX=y
-CONFIG_RT2800PCI_RT35XX=y
-CONFIG_RT2800PCI_RT53XX=y
-CONFIG_RT2800PCI_RT3290=y
-CONFIG_RT2500USB=m
-CONFIG_RT73USB=m
-CONFIG_RT2800USB=m
-CONFIG_RT2800USB_RT33XX=y
-CONFIG_RT2800USB_RT35XX=y
-CONFIG_RT2800USB_RT3573=y
-CONFIG_RT2800USB_RT53XX=y
-CONFIG_RT2800USB_RT55XX=y
-CONFIG_RT2800USB_UNKNOWN=y
-CONFIG_RT2800_LIB=m
-CONFIG_RT2800_LIB_MMIO=m
-CONFIG_RT2X00_LIB_MMIO=m
-CONFIG_RT2X00_LIB_PCI=m
-CONFIG_RT2X00_LIB_USB=m
-CONFIG_RT2X00_LIB=m
-CONFIG_RT2X00_LIB_FIRMWARE=y
-CONFIG_RT2X00_LIB_CRYPTO=y
-CONFIG_RT2X00_LIB_LEDS=y
-# CONFIG_RT2X00_DEBUG is not set
-CONFIG_WLAN_VENDOR_REALTEK=y
-CONFIG_RTL8180=m
-CONFIG_RTL8187=m
-CONFIG_RTL8187_LEDS=y
-CONFIG_RTL_CARDS=m
-CONFIG_RTL8192CE=m
-CONFIG_RTL8192SE=m
-CONFIG_RTL8192DE=m
-CONFIG_RTL8723AE=m
-CONFIG_RTL8723BE=m
-CONFIG_RTL8188EE=m
-CONFIG_RTL8192EE=m
-CONFIG_RTL8821AE=m
-CONFIG_RTL8192CU=m
-CONFIG_RTLWIFI=m
-CONFIG_RTLWIFI_PCI=m
-CONFIG_RTLWIFI_USB=m
-# CONFIG_RTLWIFI_DEBUG is not set
-CONFIG_RTL8192C_COMMON=m
-CONFIG_RTL8723_COMMON=m
-CONFIG_RTLBTCOEXIST=m
-CONFIG_RTL8XXXU=m
-CONFIG_RTL8XXXU_UNTESTED=y
-CONFIG_RTW88=m
-CONFIG_RTW88_CORE=m
-CONFIG_RTW88_PCI=m
-CONFIG_RTW88_8822B=m
-CONFIG_RTW88_8822C=m
-CONFIG_RTW88_8723D=m
-CONFIG_RTW88_8821C=m
-CONFIG_RTW88_8822BE=m
-CONFIG_RTW88_8822CE=m
-CONFIG_RTW88_8723DE=m
-CONFIG_RTW88_8821CE=m
-# CONFIG_RTW88_DEBUG is not set
-# CONFIG_RTW88_DEBUGFS is not set
-CONFIG_WLAN_VENDOR_RSI=y
-CONFIG_RSI_91X=m
-# CONFIG_RSI_DEBUGFS is not set
-CONFIG_RSI_SDIO=m
-CONFIG_RSI_USB=m
-CONFIG_RSI_COEX=y
-CONFIG_WLAN_VENDOR_ST=y
-CONFIG_CW1200=m
-CONFIG_CW1200_WLAN_SDIO=m
-CONFIG_CW1200_WLAN_SPI=m
-CONFIG_WLAN_VENDOR_TI=y
-CONFIG_WL1251=m
-CONFIG_WL1251_SPI=m
-CONFIG_WL1251_SDIO=m
-CONFIG_WL12XX=m
-CONFIG_WL18XX=m
-CONFIG_WLCORE=m
-# CONFIG_WLCORE_SPI is not set
-CONFIG_WLCORE_SDIO=m
-CONFIG_WILINK_PLATFORM_DATA=y
-CONFIG_WLAN_VENDOR_ZYDAS=y
-CONFIG_USB_ZD1201=m
-CONFIG_ZD1211RW=m
-# CONFIG_ZD1211RW_DEBUG is not set
-CONFIG_WLAN_VENDOR_QUANTENNA=y
-CONFIG_QTNFMAC=m
-CONFIG_QTNFMAC_PCIE=m
-CONFIG_PCMCIA_RAYCS=m
-CONFIG_PCMCIA_WL3501=m
-# CONFIG_MAC80211_HWSIM is not set
-CONFIG_USB_NET_RNDIS_WLAN=m
-CONFIG_VIRT_WIFI=m
-
-#
-# WiMAX Wireless Broadband devices
-#
-CONFIG_WIMAX_I2400M=m
-CONFIG_WIMAX_I2400M_USB=m
-CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8
-# end of WiMAX Wireless Broadband devices
-
-CONFIG_WAN=y
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_PCI200SYN=m
-CONFIG_WANXL=m
-CONFIG_PC300TOO=m
-CONFIG_FARSYNC=m
-# CONFIG_SLIC_DS26522 is not set
-CONFIG_DLCI=m
-CONFIG_DLCI_MAX=8
-CONFIG_LAPBETHER=m
-CONFIG_X25_ASY=m
-CONFIG_IEEE802154_DRIVERS=m
-CONFIG_IEEE802154_FAKELB=m
-CONFIG_IEEE802154_AT86RF230=m
-# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set
-CONFIG_IEEE802154_MRF24J40=m
-CONFIG_IEEE802154_CC2520=m
-CONFIG_IEEE802154_ATUSB=m
-CONFIG_IEEE802154_ADF7242=m
-CONFIG_IEEE802154_CA8210=m
-# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
-CONFIG_IEEE802154_MCR20A=m
-CONFIG_IEEE802154_HWSIM=m
-CONFIG_VMXNET3=m
-CONFIG_USB4_NET=m
-CONFIG_NETDEVSIM=m
-CONFIG_NET_FAILOVER=m
-CONFIG_ISDN=y
-CONFIG_ISDN_CAPI=m
-# CONFIG_CAPI_TRACE is not set
-CONFIG_ISDN_CAPI_MIDDLEWARE=m
-CONFIG_MISDN=m
-CONFIG_MISDN_DSP=m
-CONFIG_MISDN_L1OIP=m
-
-#
-# mISDN hardware drivers
-#
-CONFIG_MISDN_HFCPCI=m
-CONFIG_MISDN_HFCMULTI=m
-CONFIG_MISDN_HFCUSB=m
-CONFIG_MISDN_AVMFRITZ=m
-CONFIG_MISDN_SPEEDFAX=m
-CONFIG_MISDN_INFINEON=m
-CONFIG_MISDN_W6692=m
-CONFIG_MISDN_NETJET=m
-CONFIG_MISDN_HDLC=m
-CONFIG_MISDN_IPAC=m
-CONFIG_MISDN_ISAR=m
-CONFIG_NVM=y
-CONFIG_NVM_PBLK=m
-# CONFIG_NVM_PBLK_DEBUG is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_LEDS=m
-CONFIG_INPUT_FF_MEMLESS=m
-CONFIG_INPUT_POLLDEV=m
-CONFIG_INPUT_SPARSEKMAP=m
-CONFIG_INPUT_MATRIXKMAP=m
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ADC=m
-CONFIG_KEYBOARD_ADP5588=m
-CONFIG_KEYBOARD_ADP5589=m
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_KEYBOARD_QT1050=m
-CONFIG_KEYBOARD_QT1070=m
-CONFIG_KEYBOARD_QT2160=m
-CONFIG_KEYBOARD_DLINK_DIR685=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_GPIO=m
-CONFIG_KEYBOARD_GPIO_POLLED=m
-CONFIG_KEYBOARD_TCA6416=m
-CONFIG_KEYBOARD_TCA8418=m
-CONFIG_KEYBOARD_MATRIX=m
-CONFIG_KEYBOARD_LM8323=m
-CONFIG_KEYBOARD_LM8333=m
-CONFIG_KEYBOARD_MAX7359=m
-CONFIG_KEYBOARD_MCS=m
-CONFIG_KEYBOARD_MPR121=m
-# CONFIG_KEYBOARD_SNVS_PWRKEY is not set
-# CONFIG_KEYBOARD_IMX is not set
-CONFIG_KEYBOARD_NEWTON=m
-# CONFIG_KEYBOARD_NOMADIK is not set
-# CONFIG_KEYBOARD_TEGRA is not set
-CONFIG_KEYBOARD_OPENCORES=m
-CONFIG_KEYBOARD_PINEPHONE=m
-# CONFIG_KEYBOARD_PXA27x is not set
-# CONFIG_KEYBOARD_PMIC8XXX is not set
-CONFIG_KEYBOARD_SAMSUNG=m
-CONFIG_KEYBOARD_STOWAWAY=m
-# CONFIG_KEYBOARD_ST_KEYSCAN is not set
-CONFIG_KEYBOARD_SUNKBD=m
-# CONFIG_KEYBOARD_STMPE is not set
-# CONFIG_KEYBOARD_SUN4I_LRADC is not set
-CONFIG_KEYBOARD_IQS62X=m
-CONFIG_KEYBOARD_OMAP4=m
-# CONFIG_KEYBOARD_SPEAR is not set
-CONFIG_KEYBOARD_TM2_TOUCHKEY=m
-# CONFIG_KEYBOARD_TWL4030 is not set
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_KEYBOARD_CROS_EC=m
-CONFIG_KEYBOARD_CAP11XX=m
-CONFIG_KEYBOARD_BCM=m
-CONFIG_KEYBOARD_MT6779=m
-CONFIG_KEYBOARD_MTK_PMIC=m
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_BYD=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
-CONFIG_MOUSE_PS2_CYPRESS=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-CONFIG_MOUSE_PS2_ELANTECH=y
-CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
-CONFIG_MOUSE_PS2_SENTELIC=y
-CONFIG_MOUSE_PS2_TOUCHKIT=y
-CONFIG_MOUSE_PS2_FOCALTECH=y
-CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_APPLETOUCH=m
-CONFIG_MOUSE_BCM5974=m
-CONFIG_MOUSE_CYAPA=m
-CONFIG_MOUSE_ELAN_I2C=m
-CONFIG_MOUSE_ELAN_I2C_I2C=y
-CONFIG_MOUSE_ELAN_I2C_SMBUS=y
-CONFIG_MOUSE_VSXXXAA=m
-CONFIG_MOUSE_GPIO=m
-CONFIG_MOUSE_SYNAPTICS_I2C=m
-CONFIG_MOUSE_SYNAPTICS_USB=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADC=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=m
-CONFIG_JOYSTICK_IFORCE_232=m
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_TWIDJOY=m
-CONFIG_JOYSTICK_ZHENHUA=m
-CONFIG_JOYSTICK_DB9=m
-CONFIG_JOYSTICK_GAMECON=m
-CONFIG_JOYSTICK_TURBOGRAFX=m
-CONFIG_JOYSTICK_AS5011=m
-# CONFIG_JOYSTICK_JOYDUMP is not set
-CONFIG_JOYSTICK_XPAD=m
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_JOYSTICK_WALKERA0701=m
-CONFIG_JOYSTICK_PSXPAD_SPI=m
-CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
-CONFIG_JOYSTICK_PXRC=m
-CONFIG_JOYSTICK_QWIIC=m
-CONFIG_JOYSTICK_FSIA6B=m
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=m
-CONFIG_TABLET_USB_AIPTEK=m
-CONFIG_TABLET_USB_GTCO=m
-CONFIG_TABLET_USB_HANWANG=m
-CONFIG_TABLET_USB_KBTAB=m
-CONFIG_TABLET_USB_PEGASUS=m
-CONFIG_TABLET_SERIAL_WACOM4=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_PROPERTIES=y
-CONFIG_TOUCHSCREEN_ADS7846=m
-CONFIG_TOUCHSCREEN_AD7877=m
-CONFIG_TOUCHSCREEN_AD7879=m
-CONFIG_TOUCHSCREEN_AD7879_I2C=m
-CONFIG_TOUCHSCREEN_AD7879_SPI=m
-CONFIG_TOUCHSCREEN_ADC=m
-CONFIG_TOUCHSCREEN_AR1021_I2C=m
-CONFIG_TOUCHSCREEN_ATMEL_MXT=m
-# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set
-CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
-CONFIG_TOUCHSCREEN_BU21013=m
-CONFIG_TOUCHSCREEN_BU21029=m
-CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
-CONFIG_TOUCHSCREEN_CY8CTMA140=m
-CONFIG_TOUCHSCREEN_CY8CTMG110=m
-CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
-CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
-CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
-CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
-CONFIG_TOUCHSCREEN_DA9052=m
-CONFIG_TOUCHSCREEN_DYNAPRO=m
-CONFIG_TOUCHSCREEN_HAMPSHIRE=m
-CONFIG_TOUCHSCREEN_EETI=m
-CONFIG_TOUCHSCREEN_EGALAX=m
-CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
-CONFIG_TOUCHSCREEN_EXC3000=m
-CONFIG_TOUCHSCREEN_FUJITSU=m
-CONFIG_TOUCHSCREEN_GOODIX=m
-CONFIG_TOUCHSCREEN_HIDEEP=m
-CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
-CONFIG_TOUCHSCREEN_ILI210X=m
-CONFIG_TOUCHSCREEN_ILITEK=m
-CONFIG_TOUCHSCREEN_S6SY761=m
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_TOUCHSCREEN_EKTF2127=m
-CONFIG_TOUCHSCREEN_ELAN=m
-CONFIG_TOUCHSCREEN_ELO=m
-CONFIG_TOUCHSCREEN_WACOM_W8001=m
-CONFIG_TOUCHSCREEN_WACOM_I2C=m
-CONFIG_TOUCHSCREEN_MAX11801=m
-CONFIG_TOUCHSCREEN_MCS5000=m
-CONFIG_TOUCHSCREEN_MMS114=m
-CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
-CONFIG_TOUCHSCREEN_MSG2638=m
-CONFIG_TOUCHSCREEN_MTOUCH=m
-CONFIG_TOUCHSCREEN_IMAGIS=m
-CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
-CONFIG_TOUCHSCREEN_INEXIO=m
-CONFIG_TOUCHSCREEN_MK712=m
-CONFIG_TOUCHSCREEN_PENMOUNT=m
-CONFIG_TOUCHSCREEN_EDT_FT5X06=m
-CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
-CONFIG_TOUCHSCREEN_TOUCHWIN=m
-CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m
-CONFIG_TOUCHSCREEN_UCB1400=m
-CONFIG_TOUCHSCREEN_PIXCIR=m
-CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
-CONFIG_TOUCHSCREEN_WM831X=m
-CONFIG_TOUCHSCREEN_WM97XX=m
-CONFIG_TOUCHSCREEN_WM9705=y
-CONFIG_TOUCHSCREEN_WM9712=y
-CONFIG_TOUCHSCREEN_WM9713=y
-CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-CONFIG_TOUCHSCREEN_MC13783=m
-CONFIG_TOUCHSCREEN_USB_EGALAX=y
-CONFIG_TOUCHSCREEN_USB_PANJIT=y
-CONFIG_TOUCHSCREEN_USB_3M=y
-CONFIG_TOUCHSCREEN_USB_ITM=y
-CONFIG_TOUCHSCREEN_USB_ETURBO=y
-CONFIG_TOUCHSCREEN_USB_GUNZE=y
-CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
-CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
-CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
-CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
-CONFIG_TOUCHSCREEN_USB_GOTOP=y
-CONFIG_TOUCHSCREEN_USB_JASTEC=y
-CONFIG_TOUCHSCREEN_USB_ELO=y
-CONFIG_TOUCHSCREEN_USB_E2I=y
-CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
-CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
-CONFIG_TOUCHSCREEN_USB_NEXIO=y
-CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
-CONFIG_TOUCHSCREEN_TOUCHIT213=m
-CONFIG_TOUCHSCREEN_TSC_SERIO=m
-CONFIG_TOUCHSCREEN_TSC200X_CORE=m
-CONFIG_TOUCHSCREEN_TSC2004=m
-CONFIG_TOUCHSCREEN_TSC2005=m
-CONFIG_TOUCHSCREEN_TSC2007=m
-CONFIG_TOUCHSCREEN_TSC2007_IIO=y
-CONFIG_TOUCHSCREEN_PCAP=m
-CONFIG_TOUCHSCREEN_RM_TS=m
-CONFIG_TOUCHSCREEN_SILEAD=m
-CONFIG_TOUCHSCREEN_SIS_I2C=m
-CONFIG_TOUCHSCREEN_ST1232=m
-CONFIG_TOUCHSCREEN_STMFTS=m
-# CONFIG_TOUCHSCREEN_STMPE is not set
-# CONFIG_TOUCHSCREEN_SUN4I is not set
-CONFIG_TOUCHSCREEN_SUR40=m
-CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
-CONFIG_TOUCHSCREEN_SX8654=m
-CONFIG_TOUCHSCREEN_TPS6507X=m
-CONFIG_TOUCHSCREEN_ZET6223=m
-CONFIG_TOUCHSCREEN_ZFORCE=m
-CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
-CONFIG_TOUCHSCREEN_ROHM_BU21023=m
-CONFIG_TOUCHSCREEN_IQS5XX=m
-CONFIG_TOUCHSCREEN_ZINITIX=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_ATC260X_ONKEY=m
-CONFIG_INPUT_88PM80X_ONKEY=m
-# CONFIG_INPUT_AB8500_PONKEY is not set
-CONFIG_INPUT_AD714X=m
-CONFIG_INPUT_AD714X_I2C=m
-CONFIG_INPUT_AD714X_SPI=m
-CONFIG_INPUT_ARIZONA_HAPTICS=m
-CONFIG_INPUT_ATMEL_CAPTOUCH=m
-CONFIG_INPUT_BMA150=m
-CONFIG_INPUT_E3X0_BUTTON=m
-# CONFIG_INPUT_PM8XXX_VIBRATOR is not set
-# CONFIG_INPUT_PMIC8XXX_PWRKEY is not set
-# CONFIG_INPUT_MAX77650_ONKEY is not set
-CONFIG_INPUT_MAX77693_HAPTIC=m
-CONFIG_INPUT_MC13783_PWRBUTTON=m
-CONFIG_INPUT_MMA8450=m
-CONFIG_INPUT_GPIO_BEEPER=m
-CONFIG_INPUT_GPIO_DECODER=m
-CONFIG_INPUT_GPIO_VIBRA=m
-# CONFIG_INPUT_CPCAP_PWRBUTTON is not set
-CONFIG_INPUT_ATI_REMOTE2=m
-CONFIG_INPUT_KEYSPAN_REMOTE=m
-CONFIG_INPUT_KXTJ9=m
-CONFIG_INPUT_POWERMATE=m
-CONFIG_INPUT_YEALINK=m
-CONFIG_INPUT_CM109=m
-CONFIG_INPUT_REGULATOR_HAPTIC=m
-CONFIG_INPUT_RETU_PWRBUTTON=m
-# CONFIG_INPUT_TPS65218_PWRBUTTON is not set
-CONFIG_INPUT_AXP20X_PEK=m
-# CONFIG_INPUT_TWL4030_PWRBUTTON is not set
-# CONFIG_INPUT_TWL4030_VIBRA is not set
-CONFIG_INPUT_UINPUT=m
-CONFIG_INPUT_PCF50633_PMU=m
-CONFIG_INPUT_PCF8574=m
-CONFIG_INPUT_PWM_BEEPER=m
-CONFIG_INPUT_PWM_VIBRA=m
-# CONFIG_INPUT_RK805_PWRKEY is not set
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-CONFIG_INPUT_DA7280_HAPTICS=m
-CONFIG_INPUT_DA9052_ONKEY=m
-CONFIG_INPUT_DA9063_ONKEY=m
-CONFIG_INPUT_WM831X_ON=m
-CONFIG_INPUT_PCAP=m
-CONFIG_INPUT_ADXL34X=m
-CONFIG_INPUT_IBM_PANEL=m
-CONFIG_INPUT_ADXL34X_I2C=m
-CONFIG_INPUT_ADXL34X_SPI=m
-CONFIG_INPUT_IMS_PCU=m
-CONFIG_INPUT_IQS269A=m
-CONFIG_INPUT_IQS626A=m
-CONFIG_INPUT_CMA3000=m
-CONFIG_INPUT_CMA3000_I2C=m
-CONFIG_INPUT_SIRFSOC_ONKEY=y
-CONFIG_INPUT_DRV260X_HAPTICS=m
-CONFIG_INPUT_DRV2665_HAPTICS=m
-CONFIG_INPUT_DRV2667_HAPTICS=m
-# CONFIG_INPUT_HISI_POWERKEY is not set
-CONFIG_INPUT_RT5120_PWRKEY=m
-CONFIG_INPUT_RAVE_SP_PWRBUTTON=m
-CONFIG_INPUT_RT5120_PWRKEY=m
-CONFIG_RMI4_CORE=m
-CONFIG_RMI4_I2C=m
-CONFIG_RMI4_SPI=m
-CONFIG_RMI4_SMB=m
-CONFIG_RMI4_F03=y
-CONFIG_RMI4_F03_SERIO=m
-CONFIG_RMI4_2D_SENSOR=y
-CONFIG_RMI4_F11=y
-CONFIG_RMI4_F12=y
-CONFIG_RMI4_F30=y
-CONFIG_RMI4_F34=y
-CONFIG_RMI4_F3A=y
-CONFIG_RMI4_F54=y
-CONFIG_RMI4_F55=y
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=m
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_PARKBD=m
-# CONFIG_SERIO_AMBAKMI is not set
-CONFIG_SERIO_PCIPS2=m
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_RAW=m
-CONFIG_SERIO_ALTERA_PS2=m
-CONFIG_SERIO_PS2MULT=m
-CONFIG_SERIO_ARC_PS2=m
-CONFIG_SERIO_APBPS2=m
-# CONFIG_SERIO_OLPC_APSP is not set
-# CONFIG_SERIO_SUN4I_PS2 is not set
-CONFIG_SERIO_GPIO_PS2=m
-CONFIG_USERIO=m
-CONFIG_GAMEPORT=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_GAMEPORT_EMU10K1=m
-CONFIG_GAMEPORT_FM801=m
-# end of Hardware I/O ports
-# end of Input device support
-
-#
-# Character devices
-#
-CONFIG_TTY=y
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LDISC_AUTOLOAD=y
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_EARLYCON=y
-CONFIG_SERIAL_8250=y
-# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
-CONFIG_SERIAL_8250_FINTEK=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_DMA=y
-CONFIG_SERIAL_8250_PCI=m
-CONFIG_SERIAL_8250_EXAR=m
-CONFIG_SERIAL_8250_CS=m
-CONFIG_SERIAL_8250_MEN_MCB=m
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-# CONFIG_SERIAL_8250_ASPEED_VUART is not set
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_DW=m
-# CONFIG_SERIAL_8250_EM is not set
-CONFIG_SERIAL_8250_RT288X=y
-# CONFIG_SERIAL_8250_OMAP is not set
-# CONFIG_SERIAL_8250_MT6577 is not set
-# CONFIG_SERIAL_8250_UNIPHIER is not set
-# CONFIG_SERIAL_8250_PXA is not set
-CONFIG_SERIAL_8250_TEGRA=y
-CONFIG_SERIAL_8250_BCM7271=m
-CONFIG_SERIAL_OF_PLATFORM=m
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_AMBA_PL010 is not set
-# CONFIG_SERIAL_AMBA_PL011 is not set
-CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y
-# CONFIG_SERIAL_ATMEL is not set
-# CONFIG_SERIAL_MESON is not set
-# CONFIG_SERIAL_SAMSUNG is not set
-# CONFIG_SERIAL_SIRFSOC is not set
-CONFIG_SERIAL_MAX3100=m
-CONFIG_SERIAL_MAX310X=y
-# CONFIG_SERIAL_PXA is not set
-# CONFIG_SERIAL_IMX is not set
-CONFIG_SERIAL_IMX_EARLYCON=y
-CONFIG_SERIAL_UARTLITE=m
-CONFIG_SERIAL_UARTLITE_NR_UARTS=1
-# CONFIG_SERIAL_SH_SCI is not set
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_JSM=m
-# CONFIG_SERIAL_MSM is not set
-# CONFIG_SERIAL_VT8500 is not set
-# CONFIG_SERIAL_OMAP is not set
-CONFIG_SERIAL_SIFIVE=m
-CONFIG_SERIAL_SCCNXP=m
-CONFIG_SERIAL_SC16IS7XX_CORE=m
-CONFIG_SERIAL_SC16IS7XX=m
-CONFIG_SERIAL_SC16IS7XX_I2C=y
-CONFIG_SERIAL_SC16IS7XX_SPI=y
-CONFIG_SERIAL_BCM63XX=m
-CONFIG_SERIAL_ALTERA_JTAGUART=m
-CONFIG_SERIAL_ALTERA_UART=m
-CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
-CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
-CONFIG_SERIAL_IFX6X60=m
-CONFIG_SERIAL_XILINX_PS_UART=m
-CONFIG_SERIAL_ARC=m
-CONFIG_SERIAL_ARC_NR_PORTS=1
-CONFIG_SERIAL_RP2=m
-CONFIG_SERIAL_RP2_NR_UARTS=32
-CONFIG_SERIAL_FSL_LPUART=m
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_FSL_LINFLEXUART=m
-CONFIG_SERIAL_CONEXANT_DIGICOLOR=m
-CONFIG_SERIAL_ST_ASC=m
-CONFIG_SERIAL_MEN_Z135=m
-CONFIG_SERIAL_SPRD=m
-# CONFIG_SERIAL_STM32 is not set
-# CONFIG_SERIAL_MVEBU_UART is not set
-# CONFIG_SERIAL_OWL is not set
-# CONFIG_SERIAL_RDA is not set
-CONFIG_SERIAL_MILBEAUT_USIO=y
-CONFIG_SERIAL_MILBEAUT_USIO_PORTS=4
-CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE=y
-CONFIG_SERIAL_LITEUART=m
-CONFIG_SERIAL_LITEUART_MAX_PORTS=1
-# end of Serial drivers
-
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_ROCKETPORT=m
-CONFIG_CYCLADES=m
-CONFIG_CYZ_INTR=y
-CONFIG_MOXA_INTELLIO=m
-CONFIG_MOXA_SMARTIO=m
-CONFIG_SYNCLINKMP=m
-CONFIG_SYNCLINK_GT=m
-CONFIG_ISI=m
-CONFIG_N_HDLC=m
-CONFIG_N_GSM=m
-CONFIG_NOZOMI=m
-CONFIG_NULL_TTY=m
-CONFIG_TRACE_ROUTER=m
-CONFIG_TRACE_SINK=m
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_DCC=y
-CONFIG_SERIAL_DEV_BUS=m
-# CONFIG_TTY_PRINTK is not set
-CONFIG_PRINTER=m
-CONFIG_LP_CONSOLE=y
-CONFIG_PPDEV=m
-CONFIG_VIRTIO_CONSOLE=m
-CONFIG_IPMI_HANDLER=m
-CONFIG_IPMI_PLAT_DATA=y
-CONFIG_IPMI_PANIC_EVENT=y
-CONFIG_IPMI_PANIC_STRING=y
-CONFIG_IPMI_DEVICE_INTERFACE=m
-CONFIG_IPMI_SI=m
-CONFIG_IPMI_SSIF=m
-CONFIG_IPMI_WATCHDOG=m
-CONFIG_IPMI_POWEROFF=m
-CONFIG_NPCM7XX_KCS_IPMI_BMC=m
-CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m
-CONFIG_IPMI_KCS_BMC_SERIO=m
-# CONFIG_ASPEED_KCS_IPMI_BMC is not set
-# CONFIG_ASPEED_BT_IPMI_BMC is not set
-CONFIG_IPMB_DEVICE_INTERFACE=m
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=y
-CONFIG_HW_RANDOM_ATMEL=y
-CONFIG_HW_RANDOM_BA431=y
-CONFIG_HW_RANDOM_OMAP=y
-CONFIG_HW_RANDOM_OMAP3_ROM=y
-# CONFIG_HW_RANDOM_VIRTIO is not set
-CONFIG_HW_RANDOM_HISI=y
-# CONFIG_HW_RANDOM_ST is not set
-CONFIG_HW_RANDOM_STM32=y
-CONFIG_HW_RANDOM_ROCKCHIP=m
-CONFIG_HW_RANDOM_MESON=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_HW_RANDOM_EXYNOS=y
-CONFIG_HW_RANDOM_NPCM=y
-CONFIG_HW_RANDOM_KEYSTONE=y
-# CONFIG_HW_RANDOM_CCTRNG is not set
-CONFIG_HW_RANDOM_XIPHERA=m
-CONFIG_APPLICOM=m
-
-#
-# PCMCIA character devices
-#
-CONFIG_SYNCLINK_CS=m
-CONFIG_CARDMAN_4000=m
-CONFIG_CARDMAN_4040=m
-CONFIG_SCR24X=m
-CONFIG_IPWIRELESS=m
-# end of PCMCIA character devices
-
-CONFIG_DEVMEM=y
-# CONFIG_DEVKMEM is not set
-CONFIG_RAW_DRIVER=m
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_DEVPORT=y
-CONFIG_TCG_TPM=m
-CONFIG_HW_RANDOM_TPM=y
-CONFIG_TCG_TIS_CORE=m
-CONFIG_TCG_TIS=m
-CONFIG_TCG_TIS_SPI=m
-CONFIG_TCG_TIS_SPI_CR50=y
-CONFIG_TCG_TIS_I2C_CR50=m
-CONFIG_TCG_TIS_I2C_ATMEL=m
-CONFIG_TCG_TIS_I2C_INFINEON=m
-CONFIG_TCG_TIS_I2C_NUVOTON=m
-CONFIG_TCG_VTPM_PROXY=m
-CONFIG_TCG_TIS_ST33ZP24=m
-CONFIG_TCG_TIS_ST33ZP24_I2C=m
-CONFIG_TCG_TIS_ST33ZP24_SPI=m
-CONFIG_XILLYBUS=m
-CONFIG_XILLYBUS_PCIE=m
-CONFIG_XILLYBUS_OF=m
-CONFIG_XILLYUSB=m
-# end of Character devices
-
-CONFIG_RANDOM_TRUST_BOOTLOADER=y
-
-#
-# I2C support
-#
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_MUX=m
-
-#
-# Multiplexer I2C Chip support
-#
-# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
-CONFIG_I2C_MUX_GPIO=m
-# CONFIG_I2C_MUX_GPMUX is not set
-CONFIG_I2C_MUX_LTC4306=m
-CONFIG_I2C_MUX_PCA9541=m
-CONFIG_I2C_MUX_PCA954x=m
-# CONFIG_I2C_MUX_PINCTRL is not set
-CONFIG_I2C_MUX_REG=m
-# CONFIG_I2C_DEMUX_PINCTRL is not set
-CONFIG_I2C_MUX_MLXCPLD=m
-# end of Multiplexer I2C Chip support
-
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_SMBUS=m
-CONFIG_I2C_ALGOBIT=m
-CONFIG_I2C_ALGOPCA=m
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# PC SMBus host controller drivers
-#
-CONFIG_I2C_ALI1535=m
-CONFIG_I2C_ALI1563=m
-CONFIG_I2C_ALI15X3=m
-CONFIG_I2C_AMD756=m
-CONFIG_I2C_AMD8111=m
-# CONFIG_I2C_HIX5HD2 is not set
-CONFIG_I2C_I801=m
-CONFIG_I2C_ISCH=m
-CONFIG_I2C_PIIX4=m
-CONFIG_I2C_NFORCE2=m
-CONFIG_I2C_NVIDIA_GPU=m
-CONFIG_I2C_SIS5595=m
-CONFIG_I2C_SIS630=m
-CONFIG_I2C_SIS96X=m
-CONFIG_I2C_VIA=m
-CONFIG_I2C_VIAPRO=m
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_ALTERA is not set
-# CONFIG_I2C_ASPEED is not set
-# CONFIG_I2C_AT91 is not set
-# CONFIG_I2C_CADENCE is not set
-CONFIG_I2C_CBUS_GPIO=m
-# CONFIG_I2C_DAVINCI is not set
-CONFIG_I2C_DESIGNWARE_CORE=m
-# CONFIG_I2C_DESIGNWARE_SLAVE is not set
-CONFIG_I2C_DESIGNWARE_PLATFORM=m
-CONFIG_I2C_DESIGNWARE_AMDPSP=y
-CONFIG_I2C_DESIGNWARE_PCI=m
-# CONFIG_I2C_DIGICOLOR is not set
-CONFIG_I2C_EMEV2=m
-CONFIG_I2C_EXYNOS5=y
-CONFIG_I2C_GPIO=m
-CONFIG_I2C_HISI=m
-# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
-# CONFIG_I2C_IMX is not set
-# CONFIG_I2C_IMX_LPI2C is not set
-CONFIG_I2C_KEMPLD=m
-# CONFIG_I2C_MESON is not set
-# CONFIG_I2C_MT65XX is not set
-# CONFIG_I2C_MV64XXX is not set
-CONFIG_I2C_NOMADIK=y
-CONFIG_I2C_OCORES=m
-CONFIG_I2C_OMAP=y
-# CONFIG_I2C_OWL is not set
-CONFIG_I2C_PCA_PLATFORM=m
-# CONFIG_I2C_PXA is not set
-# CONFIG_I2C_QCOM_CCI is not set
-# CONFIG_I2C_QUP is not set
-# CONFIG_I2C_RIIC is not set
-# CONFIG_I2C_RK3X is not set
-CONFIG_I2C_S3C2410=m
-CONFIG_HAVE_S3C2410_I2C=y
-# CONFIG_I2C_S3C2410 is not set
-# CONFIG_I2C_SH_MOBILE is not set
-CONFIG_I2C_SIMTEC=m
-# CONFIG_I2C_SIRF is not set
-# CONFIG_I2C_ST is not set
-# CONFIG_I2C_STM32F4 is not set
-# CONFIG_I2C_STM32F7 is not set
-# CONFIG_I2C_SUN6I_P2WI is not set
-# CONFIG_I2C_TEGRA is not set
-# CONFIG_I2C_UNIPHIER is not set
-# CONFIG_I2C_UNIPHIER_F is not set
-# CONFIG_I2C_VERSATILE is not set
-# CONFIG_I2C_WMT is not set
-CONFIG_I2C_XILINX=m
-# CONFIG_I2C_XLR is not set
-# CONFIG_I2C_RCAR is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-CONFIG_I2C_DIOLAN_U2C=m
-CONFIG_I2C_CP2615=m
-CONFIG_I2C_DLN2=m
-CONFIG_I2C_PARPORT=m
-CONFIG_I2C_PCI1XXXX=m
-CONFIG_I2C_ROBOTFUZZ_OSIF=m
-CONFIG_I2C_TAOS_EVM=m
-CONFIG_I2C_TINY_USB=m
-CONFIG_I2C_VIPERBOARD=m
-
-#
-# Other I2C/SMBus bus drivers
-#
-CONFIG_I2C_CROS_EC_TUNNEL=m
-CONFIG_I2C_ZX2967=y
-# end of I2C Hardware Bus support
-
-# CONFIG_I2C_STUB is not set
-CONFIG_I2C_SLAVE=y
-CONFIG_I2C_SLAVE_EEPROM=m
-CONFIG_I2C_SLAVE_TESTUNIT=m
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# end of I2C support
-
-CONFIG_I3C=m
-CONFIG_CDNS_I3C_MASTER=m
-CONFIG_DW_I3C_MASTER=m
-CONFIG_SVC_I3C_MASTER=m
-CONFIG_MIPI_I3C_HCI=m
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-
-#
-# SPI Master Controller Drivers
-#
-CONFIG_SPI_ALTERA=m
-CONFIG_SPI_ALTERA_CORE=m
-CONFIG_SPI_ALTERA_DFL=m
-# CONFIG_SPI_ARMADA_3700 is not set
-# CONFIG_SPI_ATMEL is not set
-# CONFIG_SPI_ATMEL_QUADSPI is not set
-CONFIG_SPI_AXI_SPI_ENGINE=m
-# CONFIG_SPI_BCM_QSPI is not set
-CONFIG_SPI_BITBANG=m
-CONFIG_SPI_BUTTERFLY=m
-CONFIG_SPI_CADENCE=m
-CONFIG_SPI_CADENCE_QUADSPI=m
-# CONFIG_SPI_DAVINCI is not set
-CONFIG_SPI_DESIGNWARE=m
-# CONFIG_SPI_DW_DMA is not set
-CONFIG_SPI_DW_PCI=m
-CONFIG_SPI_DW_MMIO=m
-CONFIG_SPI_DLN2=m
-# CONFIG_SPI_FSL_LPSPI is not set
-# CONFIG_SPI_FSL_QUADSPI is not set
-CONFIG_SPI_HISI_KUNPENG=m
-CONFIG_SPI_NXP_FLEXSPI=m
-CONFIG_SPI_GPIO=m
-# CONFIG_SPI_IMX is not set
-CONFIG_SPI_LM70_LLP=m
-# CONFIG_SPI_FSL_SPI is not set
-# CONFIG_SPI_MESON_SPICC is not set
-# CONFIG_SPI_MESON_SPIFC is not set
-# CONFIG_SPI_MT65XX is not set
-# CONFIG_SPI_MTK_NOR is not set
-# CONFIG_SPI_NPCM_FIU is not set
-# CONFIG_SPI_NPCM_PSPI is not set
-CONFIG_SPI_OC_TINY=m
-# CONFIG_SPI_OMAP24XX is not set
-# CONFIG_SPI_TI_QSPI is not set
-# CONFIG_SPI_ORION is not set
-CONFIG_SPI_PL022=y
-CONFIG_SPI_PXA2XX=m
-CONFIG_SPI_PXA2XX_PCI=m
-CONFIG_SPI_ROCKCHIP=m
-CONFIG_SPI_RPCIF=m
-# CONFIG_SPI_RSPI is not set
-# CONFIG_SPI_QCOM_QSPI is not set
-# CONFIG_SPI_QUP is not set
-# CONFIG_SPI_S3C64XX is not set
-CONFIG_SPI_SC18IS602=m
-# CONFIG_SPI_SH_MSIOF is not set
-# CONFIG_SPI_SH_HSPI is not set
-CONFIG_SPI_SIFIVE=m
-# CONFIG_SPI_SLAVE_MT27XX is not set
-# CONFIG_SPI_STM32 is not set
-# CONFIG_SPI_STM32_QSPI is not set
-# CONFIG_SPI_ST_SSC4 is not set
-# CONFIG_SPI_SUN4I is not set
-# CONFIG_SPI_SUN6I is not set
-CONFIG_SPI_MXIC=m
-CONFIG_SPI_TEGRA210_QUAD=m
-# CONFIG_SPI_TEGRA20_SFLASH is not set
-# CONFIG_SPI_UNIPHIER is not set
-CONFIG_SPI_XCOMM=m
-CONFIG_SPI_XILINX=m
-# CONFIG_SPI_ZYNQ_QSPI is not set
-CONFIG_SPI_ZYNQMP_GQSPI=m
-CONFIG_SPI_AMD=m
-
-#
-# SPI Multiplexer support
-#
-CONFIG_SPI_MUX=m
-
-#
-# SPI Protocol Masters
-#
-CONFIG_SPI_SPIDEV=m
-CONFIG_SPI_LOOPBACK_TEST=m
-CONFIG_SPI_TLE62X0=m
-CONFIG_SPI_SLAVE=y
-CONFIG_SPI_SLAVE_TIME=m
-CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPMI=m
-CONFIG_SPMI_MSM_PMIC_ARB=m
-CONFIG_HSI=m
-CONFIG_HSI_BOARDINFO=y
-
-#
-# HSI controllers
-#
-# CONFIG_OMAP_SSI is not set
-
-#
-# HSI clients
-#
-CONFIG_HSI_CHAR=m
-CONFIG_PPS=y
-# CONFIG_PPS_DEBUG is not set
-
-#
-# PPS clients support
-#
-# CONFIG_PPS_CLIENT_KTIMER is not set
-CONFIG_PPS_CLIENT_LDISC=m
-CONFIG_PPS_CLIENT_PARPORT=m
-CONFIG_PPS_CLIENT_GPIO=m
-
-#
-# PPS generators support
-#
-
-#
-# PTP clock support
-#
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_DP83640_PHY=m
-CONFIG_PTP_1588_CLOCK_INES=m
-CONFIG_PTP_1588_CLOCK_KVM=m
-CONFIG_PTP_1588_CLOCK_IDT82P33=m
-CONFIG_PTP_1588_CLOCK_IDTCM=m
-CONFIG_PTP_1588_CLOCK_OCP=m
-# end of PTP clock support
-
-CONFIG_PINCTRL=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_PINMUX=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_PINCONF=y
-CONFIG_GENERIC_PINCONF=y
-# CONFIG_DEBUG_PINCTRL is not set
-CONFIG_PINCTRL_AXP209=m
-CONFIG_PINCTRL_CY8C95X0=m
-# CONFIG_PINCTRL_AT91 is not set
-# CONFIG_PINCTRL_AT91PIO4 is not set
-CONFIG_PINCTRL_DA9062=m
-CONFIG_PINCTRL_DIGICOLOR=y
-CONFIG_PINCTRL_MCP23S08_I2C=m
-CONFIG_PINCTRL_MCP23S08_SPI=m
-CONFIG_PINCTRL_MCP23S08=m
-CONFIG_PINCTRL_ROCKCHIP=y
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_PINCTRL_SIRF=y
-# CONFIG_PINCTRL_SX150X is not set
-CONFIG_PINCTRL_ST=y
-CONFIG_PINCTRL_STMFX=m
-CONFIG_PINCTRL_ZYNQ=y
-# CONFIG_PINCTRL_RK805 is not set
-# CONFIG_PINCTRL_OCELOT is not set
-CONFIG_PINCTRL_MICROCHIP_SGPIO=y
-# CONFIG_PINCTRL_OWL is not set
-CONFIG_PINCTRL_BCM4908=m
-# CONFIG_PINCTRL_AS370 is not set
-# CONFIG_PINCTRL_BERLIN_BG4CT is not set
-# CONFIG_PINCTRL_IMX8MM is not set
-# CONFIG_PINCTRL_IMX8MN is not set
-# CONFIG_PINCTRL_IMX8MP is not set
-# CONFIG_PINCTRL_IMX8MQ is not set
-CONFIG_PINCTRL_ABX500=y
-CONFIG_PINCTRL_AB8500=y
-CONFIG_PINCTRL_AB8505=y
-CONFIG_PINCTRL_NOMADIK=y
-CONFIG_PINCTRL_DB8500=y
-CONFIG_PINCTRL_MSM=y
-# CONFIG_PINCTRL_APQ8064 is not set
-# CONFIG_PINCTRL_APQ8084 is not set
-# CONFIG_PINCTRL_IPQ4019 is not set
-# CONFIG_PINCTRL_IPQ8064 is not set
-# CONFIG_PINCTRL_IPQ8074 is not set
-# CONFIG_PINCTRL_IPQ6018 is not set
-CONFIG_PINCTRL_MSM8226=m
-# CONFIG_PINCTRL_MSM8660 is not set
-# CONFIG_PINCTRL_MSM8960 is not set
-# CONFIG_PINCTRL_MDM9615 is not set
-# CONFIG_PINCTRL_MSM8X74 is not set
-# CONFIG_PINCTRL_MSM8916 is not set
-CONFIG_PINCTRL_MSM8953=m
-# CONFIG_PINCTRL_MSM8976 is not set
-# CONFIG_PINCTRL_MSM8994 is not set
-# CONFIG_PINCTRL_MSM8996 is not set
-# CONFIG_PINCTRL_MSM8998 is not set
-# CONFIG_PINCTRL_QCS404 is not set
-# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
-# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
-# CONFIG_PINCTRL_SC7180 is not set
-CONFIG_PINCTRL_SC7280=m
-CONFIG_PINCTRL_SC8180X=m
-CONFIG_PINCTRL_SC8280XP=m
-# CONFIG_PINCTRL_SDM660 is not set
-# CONFIG_PINCTRL_SDM845 is not set
-CONFIG_PINCTRL_SDX55=m
-CONFIG_PINCTRL_SM6125=m
-# CONFIG_PINCTRL_SM8150 is not set
-# CONFIG_PINCTRL_SM8250 is not set
-CONFIG_PINCTRL_SM8350=m
-CONFIG_PINCTRL_LPASS_LPI=m
-
-#
-# Renesas pinctrl drivers
-#
-CONFIG_PINCTRL_RENESAS=y
-# end of Renesas pinctrl drivers
-
-CONFIG_PINCTRL_SAMSUNG=y
-CONFIG_PINCTRL_EXYNOS=y
-CONFIG_PINCTRL_EXYNOS_ARM=y
-CONFIG_PINCTRL_SPEAR=y
-CONFIG_PINCTRL_SPEAR1310=y
-CONFIG_PINCTRL_SPEAR1340=y
-CONFIG_PINCTRL_SPEAR_PLGPIO=y
-CONFIG_PINCTRL_STM32=y
-CONFIG_PINCTRL_STM32MP157=y
-CONFIG_PINCTRL_SUNXI=y
-CONFIG_PINCTRL_SUN4I_A10=y
-CONFIG_PINCTRL_SUN5I=y
-CONFIG_PINCTRL_SUN6I_A31=y
-CONFIG_PINCTRL_SUN6I_A31_R=y
-CONFIG_PINCTRL_SUN8I_A23=y
-CONFIG_PINCTRL_SUN8I_A33=y
-CONFIG_PINCTRL_SUN8I_A83T=y
-CONFIG_PINCTRL_SUN8I_A83T_R=y
-CONFIG_PINCTRL_SUN8I_A23_R=y
-CONFIG_PINCTRL_SUN8I_H3=y
-CONFIG_PINCTRL_SUN8I_H3_R=y
-CONFIG_PINCTRL_SUN8I_V3S=y
-CONFIG_PINCTRL_SUN9I_A80=y
-CONFIG_PINCTRL_SUN9I_A80_R=y
-# CONFIG_PINCTRL_SUN50I_A64 is not set
-# CONFIG_PINCTRL_SUN50I_A64_R is not set
-CONFIG_PINCTRL_SUN50I_A100=y
-CONFIG_PINCTRL_SUN50I_A100_R=y
-# CONFIG_PINCTRL_SUN50I_H5 is not set
-# CONFIG_PINCTRL_SUN50I_H6 is not set
-# CONFIG_PINCTRL_SUN50I_H6_R is not set
-CONFIG_PINCTRL_SUN50I_H616=y
-CONFIG_PINCTRL_SUN50I_H616_R=y
-CONFIG_PINCTRL_TEGRA_XUSB=y
-CONFIG_PINCTRL_TI_IODELAY=y
-CONFIG_PINCTRL_UNIPHIER=y
-CONFIG_PINCTRL_UNIPHIER_LD4=y
-CONFIG_PINCTRL_UNIPHIER_PRO4=y
-CONFIG_PINCTRL_UNIPHIER_SLD8=y
-CONFIG_PINCTRL_UNIPHIER_PRO5=y
-CONFIG_PINCTRL_UNIPHIER_PXS2=y
-CONFIG_PINCTRL_UNIPHIER_LD6B=y
-# CONFIG_PINCTRL_UNIPHIER_LD11 is not set
-# CONFIG_PINCTRL_UNIPHIER_LD20 is not set
-# CONFIG_PINCTRL_UNIPHIER_PXS3 is not set
-# CONFIG_PINCTRL_WM8850 is not set
-
-#
-# MediaTek pinctrl drivers
-#
-CONFIG_EINT_MTK=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MT2701=y
-CONFIG_PINCTRL_MT7623=y
-CONFIG_PINCTRL_MT7629=y
-CONFIG_PINCTRL_MT8135=y
-CONFIG_PINCTRL_MT8127=y
-CONFIG_PINCTRL_MT6397=y
-# end of MediaTek pinctrl drivers
-
-# CONFIG_PINCTRL_ZX296718 is not set
-CONFIG_PINCTRL_MESON=y
-CONFIG_PINCTRL_MESON8=y
-CONFIG_PINCTRL_MESON8B=y
-CONFIG_PINCTRL_MESON8_PMX=y
-CONFIG_PINCTRL_MADERA=m
-CONFIG_PINCTRL_CS47L15=y
-CONFIG_PINCTRL_CS47L35=y
-CONFIG_PINCTRL_CS47L85=y
-CONFIG_PINCTRL_CS47L90=y
-CONFIG_PINCTRL_CS47L92=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_FASTPATH_LIMIT=512
-CONFIG_OF_GPIO=y
-CONFIG_GPIOLIB_IRQCHIP=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_CDEV_V1=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_REGMAP=m
-CONFIG_GPIO_MAX730X=m
-
-#
-# Memory mapped GPIO drivers
-#
-CONFIG_GPIO_74XX_MMIO=m
-CONFIG_GPIO_ALTERA=m
-CONFIG_GPIO_ALTERA_A10SR=m
-# CONFIG_GPIO_ASPEED is not set
-# CONFIG_GPIO_ASPEED_SGPIO is not set
-CONFIG_GPIO_CADENCE=m
-# CONFIG_GPIO_DAVINCI is not set
-CONFIG_GPIO_DWAPB=m
-CONFIG_GPIO_EXAR=m
-CONFIG_GPIO_FTGPIO010=y
-CONFIG_GPIO_GENERIC_PLATFORM=m
-CONFIG_GPIO_GRGPIO=m
-CONFIG_GPIO_HLWD=m
-CONFIG_GPIO_LOGICVC=m
-CONFIG_GPIO_MB86S7X=m
-CONFIG_GPIO_MENZ127=m
-CONFIG_GPIO_MPC8XXX=y
-CONFIG_GPIO_MVEBU=y
-CONFIG_GPIO_MXC=y
-CONFIG_GPIO_OMAP=y
-CONFIG_GPIO_PL061=y
-CONFIG_GPIO_PXA=y
-# CONFIG_GPIO_RCAR is not set
-# CONFIG_GPIO_RDA is not set
-CONFIG_GPIO_SAMA5D2_PIOBU=m
-CONFIG_GPIO_SIFIVE=y
-CONFIG_GPIO_SIOX=m
-CONFIG_GPIO_SPEAR_SPICS=y
-CONFIG_GPIO_SYSCON=m
-CONFIG_GPIO_TEGRA=y
-# CONFIG_GPIO_UNIPHIER is not set
-CONFIG_GPIO_VISCONTI=m
-CONFIG_GPIO_WCD934X=m
-CONFIG_GPIO_XILINX=m
-CONFIG_GPIO_ZEVIO=y
-# CONFIG_GPIO_ZYNQ is not set
-# CONFIG_GPIO_ZX is not set
-CONFIG_GPIO_AMD_FCH=m
-CONFIG_GPIO_MSC313=y
-# end of Memory mapped GPIO drivers
-
-#
-# I2C GPIO expanders
-#
-CONFIG_GPIO_ADP5588=m
-CONFIG_GPIO_ADNP=m
-CONFIG_GPIO_GW_PLD=m
-CONFIG_GPIO_MAX7300=m
-CONFIG_GPIO_MAX732X=m
-CONFIG_GPIO_PCA953X=m
-# CONFIG_GPIO_PCA953X_IRQ is not set
-CONFIG_GPIO_PCA9570=m
-CONFIG_GPIO_PCF857X=m
-CONFIG_GPIO_TPIC2810=m
-# end of I2C GPIO expanders
-
-#
-# MFD GPIO expanders
-#
-CONFIG_GPIO_ARIZONA=m
-CONFIG_GPIO_BD9571MWV=m
-CONFIG_GPIO_DA9052=m
-CONFIG_GPIO_DLN2=m
-CONFIG_HTC_EGPIO=y
-CONFIG_GPIO_JANZ_TTL=m
-CONFIG_GPIO_KEMPLD=m
-CONFIG_GPIO_LP3943=m
-CONFIG_GPIO_LP873X=m
-# CONFIG_GPIO_LP87565 is not set
-CONFIG_GPIO_MADERA=m
-# CONFIG_GPIO_MAX77650 is not set
-CONFIG_GPIO_SL28CPLD=m
-# CONFIG_GPIO_STMPE is not set
-CONFIG_GPIO_TPS65086=m
-# CONFIG_GPIO_TPS65218 is not set
-CONFIG_GPIO_TPS65912=m
-CONFIG_GPIO_TPS68470=y
-CONFIG_GPIO_TQMX86=m
-# CONFIG_GPIO_TWL4030 is not set
-CONFIG_GPIO_UCB1400=m
-CONFIG_GPIO_WM831X=m
-CONFIG_GPIO_WM8994=m
-# end of MFD GPIO expanders
-
-#
-# PCI GPIO expanders
-#
-CONFIG_GPIO_PCI_IDIO_16=m
-CONFIG_GPIO_PCIE_IDIO_24=m
-CONFIG_GPIO_RDC321X=m
-# end of PCI GPIO expanders
-
-#
-# SPI GPIO expanders
-#
-# CONFIG_GPIO_74X164 is not set
-CONFIG_GPIO_MAX3191X=m
-CONFIG_GPIO_MAX7301=m
-CONFIG_GPIO_MC33880=m
-CONFIG_GPIO_PISOSR=m
-CONFIG_GPIO_XRA1403=m
-CONFIG_GPIO_MOXTET=m
-# end of SPI GPIO expanders
-
-#
-# USB GPIO expanders
-#
-CONFIG_GPIO_VIPERBOARD=m
-# end of USB GPIO expanders
-
-CONFIG_GPIO_AGGREGATOR=m
-CONFIG_GPIO_MOCKUP=m
-CONFIG_W1=m
-CONFIG_W1_CON=y
-
-#
-# 1-wire Bus Masters
-#
-# CONFIG_W1_MASTER_MATROX is not set
-CONFIG_W1_MASTER_DS2490=m
-CONFIG_W1_MASTER_DS2482=m
-# CONFIG_W1_MASTER_MXC is not set
-CONFIG_W1_MASTER_DS1WM=m
-CONFIG_W1_MASTER_GPIO=m
-# CONFIG_HDQ_MASTER_OMAP is not set
-CONFIG_W1_MASTER_SGI=m
-# end of 1-wire Bus Masters
-
-#
-# 1-wire Slaves
-#
-CONFIG_W1_SLAVE_THERM=m
-CONFIG_W1_SLAVE_SMEM=m
-CONFIG_W1_SLAVE_DS2405=m
-CONFIG_W1_SLAVE_DS2408=m
-CONFIG_W1_SLAVE_DS2408_READBACK=y
-CONFIG_W1_SLAVE_DS2413=m
-CONFIG_W1_SLAVE_DS2406=m
-CONFIG_W1_SLAVE_DS2423=m
-CONFIG_W1_SLAVE_DS2805=m
-CONFIG_W1_SLAVE_DS2430=m
-CONFIG_W1_SLAVE_DS2431=m
-CONFIG_W1_SLAVE_DS2433=m
-# CONFIG_W1_SLAVE_DS2433_CRC is not set
-CONFIG_W1_SLAVE_DS2438=m
-CONFIG_W1_SLAVE_DS250X=m
-CONFIG_W1_SLAVE_DS2780=m
-CONFIG_W1_SLAVE_DS2781=m
-CONFIG_W1_SLAVE_DS28E04=m
-CONFIG_W1_SLAVE_DS28E17=m
-# end of 1-wire Slaves
-
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_AT91_POWEROFF is not set
-CONFIG_POWER_RESET_ATC260X=m
-# CONFIG_POWER_RESET_AT91_RESET is not set
-# CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC is not set
-CONFIG_POWER_RESET_BRCMKONA=y
-CONFIG_POWER_RESET_BRCMSTB=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_POWER_RESET_GPIO_RESTART=y
-CONFIG_POWER_RESET_HISI=y
-CONFIG_POWER_RESET_LINKSTATION=m
-# CONFIG_POWER_RESET_MSM is not set
-CONFIG_POWER_RESET_LTC2952=y
-CONFIG_POWER_RESET_MT6323=y
-# CONFIG_POWER_RESET_QNAP is not set
-CONFIG_POWER_RESET_RESTART=y
-# CONFIG_POWER_RESET_ST is not set
-CONFIG_POWER_RESET_VERSATILE=y
-CONFIG_POWER_RESET_VEXPRESS=y
-# CONFIG_POWER_RESET_KEYSTONE is not set
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-# CONFIG_POWER_RESET_ZX is not set
-CONFIG_POWER_RESET_REGULATOR=y
-CONFIG_REBOOT_MODE=m
-CONFIG_SYSCON_REBOOT_MODE=m
-CONFIG_NVMEM_REBOOT_MODE=m
-CONFIG_POWER_MLXBF=m
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PDA_POWER=m
-CONFIG_GENERIC_ADC_BATTERY=m
-CONFIG_IP5XXX_POWER=m
-CONFIG_WM831X_BACKUP=m
-CONFIG_WM831X_POWER=m
-# CONFIG_TEST_POWER is not set
-CONFIG_CHARGER_ADP5061=m
-# CONFIG_BATTERY_ACT8945A is not set
-CONFIG_BATTERY_CPCAP=m
-CONFIG_BATTERY_CW2015=m
-CONFIG_BATTERY_DS2760=m
-CONFIG_BATTERY_DS2780=m
-CONFIG_BATTERY_DS2781=m
-CONFIG_BATTERY_DS2782=m
-# CONFIG_BATTERY_SAMSUNG_SDI is not set
-CONFIG_BATTERY_SBS=m
-CONFIG_CHARGER_SBS=m
-CONFIG_MANAGER_SBS=m
-CONFIG_BATTERY_BQ27XXX=m
-CONFIG_BATTERY_BQ27XXX_I2C=m
-CONFIG_BATTERY_BQ27XXX_HDQ=m
-CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM=y
-CONFIG_BATTERY_DA9052=m
-CONFIG_CHARGER_DA9150=m
-CONFIG_BATTERY_DA9150=m
-CONFIG_CHARGER_AXP20X=m
-CONFIG_BATTERY_AXP20X=m
-CONFIG_AXP20X_POWER=m
-CONFIG_AXP288_FUEL_GAUGE=m
-CONFIG_BATTERY_MAX17040=m
-CONFIG_BATTERY_MAX17042=m
-CONFIG_BATTERY_MAX1721X=m
-CONFIG_CHARGER_PCF50633=m
-CONFIG_CHARGER_ISP1704=m
-CONFIG_CHARGER_MAX8903=m
-# CONFIG_CHARGER_TWL4030 is not set
-CONFIG_CHARGER_LP8727=m
-CONFIG_CHARGER_GPIO=m
-CONFIG_CHARGER_MANAGER=y
-CONFIG_CHARGER_LT3651=m
-CONFIG_CHARGER_LTC4162L=m
-CONFIG_CHARGER_MAX14577=m
-# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
-# CONFIG_CHARGER_MAX77650 is not set
-CONFIG_CHARGER_MAX77693=m
-CONFIG_CHARGER_MP2629=m
-CONFIG_CHARGER_BQ2415X=m
-CONFIG_CHARGER_BQ24190=m
-CONFIG_CHARGER_BQ24257=m
-CONFIG_CHARGER_BQ24735=m
-CONFIG_CHARGER_BQ2515X=m
-CONFIG_CHARGER_BQ25890=m
-CONFIG_CHARGER_BQ25980=m
-CONFIG_CHARGER_BQ256XX=m
-CONFIG_CHARGER_RK817=m
-CONFIG_CHARGER_SMB347=m
-# CONFIG_CHARGER_TPS65217 is not set
-CONFIG_BATTERY_GAUGE_LTC2941=m
-CONFIG_BATTERY_GOLDFISH=m
-CONFIG_BATTERY_RT5033=m
-CONFIG_CHARGER_RT9455=m
-CONFIG_CHARGER_CROS_USBPD=m
-CONFIG_CHARGER_UCS1002=m
-CONFIG_CHARGER_BD99954=m
-CONFIG_BATTERY_UG3105=m
-CONFIG_SURFACE_HID=m
-CONFIG_CHARGER_SURFACE=m
-CONFIG_BATTERY_SURFACE=m
-CONFIG_RN5T618_POWER=m
-CONFIG_HWMON=y
-CONFIG_HWMON_VID=m
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Native drivers
-#
-CONFIG_SENSORS_AD7314=m
-CONFIG_SENSORS_AD7414=m
-CONFIG_SENSORS_AD7418=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1026=m
-CONFIG_SENSORS_ADM1029=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_ADM1177=m
-CONFIG_SENSORS_ADM9240=m
-CONFIG_SENSORS_ADT7X10=m
-CONFIG_SENSORS_ADT7310=m
-CONFIG_SENSORS_ADT7410=m
-CONFIG_SENSORS_ADT7411=m
-CONFIG_SENSORS_ADT7462=m
-CONFIG_SENSORS_ADT7470=m
-CONFIG_SENSORS_ADT7475=m
-CONFIG_SENSORS_AHT10=m
-CONFIG_SENSORS_AS370=m
-CONFIG_SENSORS_ASC7621=m
-CONFIG_SENSORS_AXI_FAN_CONTROL=m
-CONFIG_SENSORS_ARM_SCMI=m
-CONFIG_SENSORS_ARM_SCPI=m
-CONFIG_SENSORS_ASPEED=m
-CONFIG_SENSORS_ATXP1=m
-CONFIG_SENSORS_CORSAIR_CPRO=m
-CONFIG_SENSORS_CORSAIR_PSU=m
-CONFIG_SENSORS_DRIVETEMP=m
-CONFIG_SENSORS_DS620=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_DA9052_ADC=m
-CONFIG_SENSORS_I5K_AMB=m
-CONFIG_SENSORS_F71805F=m
-CONFIG_SENSORS_F71882FG=m
-CONFIG_SENSORS_F75375S=m
-# CONFIG_SENSORS_GSC is not set
-CONFIG_SENSORS_MC13783_ADC=m
-CONFIG_SENSORS_FTSTEUTATES=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_GL520SM=m
-CONFIG_SENSORS_G760A=m
-CONFIG_SENSORS_G762=m
-CONFIG_SENSORS_GPIO_FAN=m
-CONFIG_SENSORS_HIH6130=m
-CONFIG_SENSORS_IBMAEM=m
-CONFIG_SENSORS_IBMPEX=m
-CONFIG_SENSORS_IIO_HWMON=m
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_JC42=m
-CONFIG_SENSORS_POWR1220=m
-CONFIG_SENSORS_LINEAGE=m
-CONFIG_SENSORS_LTC2945=m
-CONFIG_SENSORS_LTC2947=m
-CONFIG_SENSORS_LTC2947_I2C=m
-CONFIG_SENSORS_LTC2947_SPI=m
-CONFIG_SENSORS_LTC2990=m
-CONFIG_SENSORS_LTC2992=m
-CONFIG_SENSORS_LTC4151=m
-CONFIG_SENSORS_LTC4215=m
-CONFIG_SENSORS_LTC4222=m
-CONFIG_SENSORS_LTC4245=m
-CONFIG_SENSORS_LTC4260=m
-CONFIG_SENSORS_LTC4261=m
-CONFIG_SENSORS_MAX1111=m
-CONFIG_SENSORS_MAX127=m
-CONFIG_SENSORS_MAX16065=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_MAX1668=m
-CONFIG_SENSORS_MAX197=m
-CONFIG_SENSORS_MAX31722=m
-CONFIG_SENSORS_MAX31730=m
-CONFIG_SENSORS_MAX31760=m
-CONFIG_SENSORS_MAX6621=m
-CONFIG_SENSORS_MAX6639=m
-CONFIG_SENSORS_MAX6642=m
-CONFIG_SENSORS_MAX6650=m
-CONFIG_SENSORS_MAX6697=m
-CONFIG_SENSORS_MAX31790=m
-CONFIG_SENSORS_PM6764TR=m
-CONFIG_SENSORS_Q54SJ108A2=m
-CONFIG_SENSORS_STPDDC60=m
-CONFIG_SENSORS_MCP3021=m
-CONFIG_SENSORS_MLXREG_FAN=m
-CONFIG_SENSORS_TC654=m
-CONFIG_SENSORS_TPS23861=m
-CONFIG_SENSORS_MENF21BMC_HWMON=m
-CONFIG_SENSORS_MR75203=m
-CONFIG_SENSORS_ADCXX=m
-CONFIG_SENSORS_LM63=m
-CONFIG_SENSORS_LM70=m
-CONFIG_SENSORS_LM73=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM87=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_LM92=m
-CONFIG_SENSORS_LM93=m
-CONFIG_SENSORS_LM95234=m
-CONFIG_SENSORS_LM95241=m
-CONFIG_SENSORS_LM95245=m
-CONFIG_SENSORS_PC87360=m
-CONFIG_SENSORS_PC87427=m
-CONFIG_SENSORS_NTC_THERMISTOR=m
-CONFIG_SENSORS_NCT6683=m
-CONFIG_SENSORS_NCT6775=m
-CONFIG_SENSORS_NCT7802=m
-CONFIG_SENSORS_NCT7904=m
-CONFIG_SENSORS_NPCM7XX=m
-CONFIG_SENSORS_NZXT_KRAKEN2=m
-CONFIG_SENSORS_BPA_RS600=m
-CONFIG_SENSORS_FSP_3Y=m
-# CONFIG_SENSORS_OCC_P8_I2C is not set
-CONFIG_SENSORS_PCF8591=m
-CONFIG_PMBUS=m
-CONFIG_SENSORS_PMBUS=m
-CONFIG_SENSORS_ADM1266=m
-CONFIG_SENSORS_ADM1275=m
-CONFIG_SENSORS_BEL_PFE=m
-CONFIG_SENSORS_IBM_CFFPS=m
-CONFIG_SENSORS_DPS920AB=m
-CONFIG_SENSORS_INSPUR_IPSPS=m
-CONFIG_SENSORS_IR35221=m
-CONFIG_SENSORS_IR36021=m
-CONFIG_SENSORS_IR38064=m
-CONFIG_SENSORS_IRPS5401=m
-CONFIG_SENSORS_ISL68137=m
-CONFIG_SENSORS_LM25066=m
-CONFIG_SENSORS_LM25066_REGULATOR=y
-CONFIG_SENSORS_LTC2978=m
-CONFIG_SENSORS_LTC2978_REGULATOR=y
-CONFIG_SENSORS_LTC3815=m
-CONFIG_SENSORS_MAX15301=m
-CONFIG_SENSORS_MAX16064=m
-CONFIG_SENSORS_MAX16601=m
-CONFIG_SENSORS_MAX20730=m
-CONFIG_SENSORS_MAX20751=m
-CONFIG_SENSORS_MAX31785=m
-CONFIG_SENSORS_MAX34440=m
-CONFIG_SENSORS_MAX8688=m
-CONFIG_SENSORS_MP2888=m
-CONFIG_SENSORS_MP2975=m
-CONFIG_SENSORS_PIM4328=m
-CONFIG_SENSORS_PLI1209BC=m
-CONFIG_SENSORS_PLI1209BC_REGULATOR=y
-CONFIG_SENSORS_PXE1610=m
-CONFIG_SENSORS_TPS40422=m
-CONFIG_SENSORS_TPS53679=m
-CONFIG_SENSORS_TPS546D24=m
-CONFIG_SENSORS_UCD9000=m
-CONFIG_SENSORS_UCD9200=m
-CONFIG_SENSORS_XDPE122=m
-CONFIG_SENSORS_XDPE122_REGULATOR=y
-CONFIG_SENSORS_ZL6100=m
-CONFIG_SENSORS_PWM_FAN=m
-CONFIG_SENSORS_SL28CPLD=m
-# CONFIG_SENSORS_SBTSI is not set
-# CONFIG_AMD_SFH_HID is not set
-CONFIG_SENSORS_SHT15=m
-CONFIG_SENSORS_SHT21=m
-CONFIG_SENSORS_SHT3x=m
-CONFIG_SENSORS_SHT4x=m
-CONFIG_SENSORS_SHTC1=m
-CONFIG_SENSORS_SIS5595=m
-CONFIG_SENSORS_SY7636A=m
-CONFIG_SENSORS_DME1737=m
-CONFIG_SENSORS_EMC1403=m
-CONFIG_SENSORS_EMC2103=m
-CONFIG_SENSORS_EMC2305=m
-CONFIG_SENSORS_EMC6W201=m
-CONFIG_SENSORS_SMSC47M1=m
-CONFIG_SENSORS_SMSC47M192=m
-CONFIG_SENSORS_SMSC47B397=m
-CONFIG_SENSORS_SCH56XX_COMMON=m
-CONFIG_SENSORS_SCH5627=m
-CONFIG_SENSORS_SCH5636=m
-CONFIG_SENSORS_STTS751=m
-CONFIG_SENSORS_SMM665=m
-CONFIG_SENSORS_ADC128D818=m
-CONFIG_SENSORS_ADS7828=m
-CONFIG_SENSORS_ADS7871=m
-CONFIG_SENSORS_AMC6821=m
-CONFIG_SENSORS_INA209=m
-CONFIG_SENSORS_INA2XX=m
-CONFIG_SENSORS_INA3221=m
-CONFIG_SENSORS_TC74=m
-CONFIG_SENSORS_THMC50=m
-CONFIG_SENSORS_TMP102=m
-CONFIG_SENSORS_TMP103=m
-CONFIG_SENSORS_TMP108=m
-CONFIG_SENSORS_TMP401=m
-CONFIG_SENSORS_TMP421=m
-CONFIG_SENSORS_TMP464=m
-CONFIG_SENSORS_TMP513=m
-CONFIG_SENSORS_VEXPRESS=m
-CONFIG_SENSORS_VIA686A=m
-CONFIG_SENSORS_VT1211=m
-CONFIG_SENSORS_VT8231=m
-CONFIG_SENSORS_W83773G=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83791D=m
-CONFIG_SENSORS_W83792D=m
-CONFIG_SENSORS_W83793=m
-CONFIG_SENSORS_W83795=m
-CONFIG_SENSORS_W83795_FANCTRL=y
-CONFIG_SENSORS_W83L785TS=m
-CONFIG_SENSORS_W83L786NG=m
-CONFIG_SENSORS_W83627HF=m
-CONFIG_SENSORS_W83627EHF=m
-CONFIG_SENSORS_WM831X=m
-CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m
-CONFIG_QCOM_SPMI_ADC_TM5=m
-CONFIG_THERMAL=y
-CONFIG_THERMAL_NETLINK=y
-CONFIG_THERMAL_STATISTICS=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=100
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
-# CONFIG_CPU_THERMAL is not set
-CONFIG_DEVFREQ_THERMAL=y
-# CONFIG_THERMAL_EMULATION is not set
-CONFIG_THERMAL_MMIO=m
-CONFIG_HISI_THERMAL=y
-# CONFIG_IMX_THERMAL is not set
-# CONFIG_IMX8MM_THERMAL is not set
-# CONFIG_SPEAR_THERMAL is not set
-# CONFIG_SUN8I_THERMAL is not set
-# CONFIG_ROCKCHIP_THERMAL is not set
-# CONFIG_RCAR_THERMAL is not set
-# CONFIG_RCAR_GEN3_THERMAL is not set
-CONFIG_DB8500_THERMAL=y
-# CONFIG_ARMADA_THERMAL is not set
-CONFIG_DA9062_THERMAL=m
-CONFIG_MTK_THERMAL=y
-CONFIG_AMLOGIC_THERMAL=y
-
-#
-# Broadcom thermal drivers
-#
-# end of Broadcom thermal drivers
-
-#
-# Texas Instruments thermal drivers
-#
-CONFIG_TI_SOC_THERMAL=m
-# CONFIG_TI_THERMAL is not set
-# CONFIG_OMAP3_THERMAL is not set
-# CONFIG_OMAP4_THERMAL is not set
-# CONFIG_OMAP5_THERMAL is not set
-# CONFIG_DRA752_THERMAL is not set
-# end of Texas Instruments thermal drivers
-
-#
-# Samsung thermal drivers
-#
-CONFIG_EXYNOS_THERMAL=y
-# end of Samsung thermal drivers
-
-#
-# STMicroelectronics thermal drivers
-#
-# CONFIG_ST_THERMAL is not set
-# CONFIG_ST_THERMAL_SYSCFG is not set
-# CONFIG_ST_THERMAL_MEMMAP is not set
-CONFIG_STM32_THERMAL=y
-# end of STMicroelectronics thermal drivers
-
-# CONFIG_TANGO_THERMAL is not set
-
-#
-# NVIDIA Tegra thermal drivers
-#
-# CONFIG_TEGRA_SOCTHERM is not set
-# end of NVIDIA Tegra thermal drivers
-
-CONFIG_GENERIC_ADC_THERMAL=m
-
-#
-# Qualcomm thermal drivers
-#
-# CONFIG_QCOM_SPMI_TEMP_ALARM is not set
-# end of Qualcomm thermal drivers
-
-# CONFIG_ZX2967_THERMAL is not set
-# CONFIG_UNIPHIER_THERMAL is not set
-CONFIG_KHADAS_MCU_FAN_THERMAL=m
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_CORE=m
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
-CONFIG_WATCHDOG_OPEN_TIMEOUT=0
-# CONFIG_WATCHDOG_SYSFS is not set
-# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
-
-#
-# Watchdog Pretimeout Governors
-#
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-
-#
-# Watchdog Device Drivers
-#
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_BD957XMUF_WATCHDOG=m
-# CONFIG_SOFT_WATCHDOG_PRETIMEOUT is not set
-CONFIG_DA9052_WATCHDOG=m
-CONFIG_DA9063_WATCHDOG=m
-CONFIG_DA9062_WATCHDOG=m
-CONFIG_GPIO_WATCHDOG=m
-CONFIG_MENF21BMC_WATCHDOG=m
-CONFIG_MENZ069_WATCHDOG=m
-# CONFIG_TANGOX_WATCHDOG is not set
-CONFIG_WM831X_WATCHDOG=m
-CONFIG_XILINX_WATCHDOG=m
-CONFIG_ZIIRAVE_WATCHDOG=m
-CONFIG_RAVE_SP_WATCHDOG=m
-CONFIG_MLX_WDT=m
-CONFIG_SL28CPLD_WATCHDOG=m
-# CONFIG_ARM_SP805_WATCHDOG is not set
-# CONFIG_ARMADA_37XX_WATCHDOG is not set
-# CONFIG_AT91SAM9X_WATCHDOG is not set
-# CONFIG_SAMA5D4_WATCHDOG is not set
-CONFIG_CADENCE_WATCHDOG=m
-CONFIG_FTWDT010_WATCHDOG=m
-# CONFIG_S3C2410_WATCHDOG is not set
-CONFIG_DW_WATCHDOG=m
-# CONFIG_OMAP_WATCHDOG is not set
-# CONFIG_DAVINCI_WATCHDOG is not set
-# CONFIG_ORION_WATCHDOG is not set
-# CONFIG_RN5T618_WATCHDOG is not set
-# CONFIG_SUNXI_WATCHDOG is not set
-# CONFIG_NPCM7XX_WATCHDOG is not set
-# CONFIG_TWL4030_WATCHDOG is not set
-CONFIG_MAX63XX_WATCHDOG=m
-CONFIG_MAX77620_WATCHDOG=m
-# CONFIG_IMX2_WDT is not set
-# CONFIG_IMX7ULP_WDT is not set
-CONFIG_UX500_WATCHDOG=y
-CONFIG_RETU_WATCHDOG=m
-CONFIG_SIRFSOC_WATCHDOG=y
-# CONFIG_ST_LPC_WATCHDOG is not set
-# CONFIG_TEGRA_WATCHDOG is not set
-# CONFIG_QCOM_WDT is not set
-# CONFIG_MESON_GXBB_WATCHDOG is not set
-# CONFIG_MESON_WATCHDOG is not set
-# CONFIG_MEDIATEK_WATCHDOG is not set
-# CONFIG_DIGICOLOR_WATCHDOG is not set
-CONFIG_ARM_SMC_WATCHDOG=m
-# CONFIG_ATLAS7_WATCHDOG is not set
-# CONFIG_RENESAS_WDT is not set
-# CONFIG_RENESAS_RZAWDT is not set
-CONFIG_ASPEED_WATCHDOG=y
-# CONFIG_ZX2967_WATCHDOG is not set
-CONFIG_STM32_WATCHDOG=y
-# CONFIG_UNIPHIER_WATCHDOG is not set
-CONFIG_RTD119X_WATCHDOG=y
-CONFIG_MSC313E_WATCHDOG=m
-CONFIG_ALIM7101_WDT=m
-CONFIG_I6300ESB_WDT=m
-CONFIG_HP_WATCHDOG=m
-CONFIG_KEMPLD_WDT=m
-CONFIG_BCM7038_WDT=m
-CONFIG_MEN_A21_WDT=m
-
-#
-# PCI-based Watchdog Cards
-#
-CONFIG_PCIPCWATCHDOG=m
-CONFIG_WDTPCI=m
-
-#
-# USB-based Watchdog Cards
-#
-CONFIG_USBPCWATCHDOG=m
-CONFIG_KEEMBAY_WATCHDOG=m
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SSB=m
-CONFIG_SSB_SPROM=y
-CONFIG_SSB_BLOCKIO=y
-CONFIG_SSB_PCIHOST_POSSIBLE=y
-CONFIG_SSB_PCIHOST=y
-CONFIG_SSB_B43_PCI_BRIDGE=y
-CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
-CONFIG_SSB_PCMCIAHOST=y
-CONFIG_SSB_SDIOHOST_POSSIBLE=y
-CONFIG_SSB_SDIOHOST=y
-CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
-CONFIG_SSB_DRIVER_PCICORE=y
-CONFIG_SSB_DRIVER_GPIO=y
-CONFIG_BCMA_POSSIBLE=y
-CONFIG_BCMA=m
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_SOC=y
-CONFIG_BCMA_DRIVER_PCI=y
-CONFIG_BCMA_SFLASH=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_DRIVER_GPIO=y
-# CONFIG_BCMA_DEBUG is not set
-
-#
-# Multifunction device drivers
-#
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_ALTERA_A10SR is not set
-CONFIG_MFD_ALTERA_A10SR=y
-# CONFIG_MFD_ALTERA_SYSMGR is not set
-CONFIG_MFD_ACT8945A=m
-# CONFIG_MFD_SUN4I_GPADC is not set
-# CONFIG_MFD_AS3711 is not set
-# CONFIG_MFD_AS3722 is not set
-# CONFIG_PMIC_ADP5520 is not set
-# CONFIG_MFD_AAT2870_CORE is not set
-# CONFIG_MFD_AT91_USART is not set
-CONFIG_MFD_ATMEL_FLEXCOM=m
-CONFIG_MFD_ATMEL_HLCDC=m
-CONFIG_MFD_ATMEL_SMC=y
-CONFIG_MFD_BCM590XX=m
-CONFIG_MFD_BD9571MWV=m
-# CONFIG_MFD_AC100 is not set
-CONFIG_MFD_AXP20X=m
-CONFIG_MFD_AXP20X_I2C=m
-# CONFIG_MFD_AXP20X_RSB is not set
-CONFIG_MFD_CROS_EC_DEV=m
-CONFIG_MFD_MADERA=m
-CONFIG_MFD_MADERA_I2C=m
-CONFIG_MFD_MADERA_SPI=m
-CONFIG_MFD_CS47L15=y
-CONFIG_MFD_CS47L35=y
-CONFIG_MFD_CS47L85=y
-CONFIG_MFD_CS47L90=y
-CONFIG_MFD_CS47L92=y
-CONFIG_MFD_ASIC3=y
-# CONFIG_PMIC_DA903X is not set
-CONFIG_PMIC_DA9052=y
-CONFIG_MFD_DA9052_SPI=y
-# CONFIG_MFD_DA9052_I2C is not set
-# CONFIG_MFD_DA9055 is not set
-CONFIG_MFD_DA9062=m
-CONFIG_MFD_DA9063=m
-CONFIG_MFD_DA9150=m
-CONFIG_MFD_DLN2=m
-# CONFIG_MFD_EXYNOS_LPASS is not set
-CONFIG_MFD_GATEWORKS_GSC=m
-CONFIG_MFD_MC13XXX=m
-CONFIG_MFD_MC13XXX_SPI=m
-CONFIG_MFD_MC13XXX_I2C=m
-CONFIG_MFD_MP2629=m
-CONFIG_MFD_HI6421_PMIC=m
-# CONFIG_MFD_HI655X_PMIC is not set
-CONFIG_HTC_PASIC3=m
-# CONFIG_HTC_I2CPLD is not set
-CONFIG_LPC_ICH=m
-CONFIG_LPC_SCH=m
-CONFIG_MFD_INTEL_PMT=m
-CONFIG_MFD_IQS62X=m
-CONFIG_MFD_JANZ_CMODIO=m
-CONFIG_MFD_KEMPLD=m
-CONFIG_MFD_88PM800=m
-CONFIG_MFD_88PM805=m
-# CONFIG_MFD_88PM860X is not set
-CONFIG_MFD_MAX14577=m
-# CONFIG_MFD_MAX77620 is not set
-CONFIG_MFD_MAX77650=m
-CONFIG_MFD_MAX77686=m
-CONFIG_MFD_MAX77693=m
-CONFIG_MFD_MAX77714=m
-# CONFIG_MFD_MAX77843 is not set
-CONFIG_MFD_MAX8907=m
-# CONFIG_MFD_MAX8925 is not set
-# CONFIG_MFD_MAX8997 is not set
-# CONFIG_MFD_MAX8998 is not set
-CONFIG_MFD_MT6360=m
-CONFIG_MFD_MT6370=m
-CONFIG_MFD_MT6397=m
-CONFIG_MFD_MENF21BMC=m
-CONFIG_MFD_OCELOT=m
-CONFIG_EZX_PCAP=y
-CONFIG_MFD_CPCAP=m
-CONFIG_MFD_VIPERBOARD=m
-CONFIG_MFD_NTXEC=m
-CONFIG_MFD_RETU=m
-CONFIG_MFD_PCF50633=m
-CONFIG_PCF50633_ADC=m
-CONFIG_PCF50633_GPIO=m
-CONFIG_UCB1400_CORE=m
-CONFIG_MFD_PM8XXX=m
-# CONFIG_MFD_QCOM_RPM is not set
-# CONFIG_MFD_SPMI_PMIC is not set
-CONFIG_MFD_SY7636A=m
-CONFIG_MFD_RDC321X=m
-CONFIG_MFD_RT4831=m
-CONFIG_MFD_RT5033=m
-CONFIG_MFD_RT5120=m
-# CONFIG_MFD_RC5T583 is not set
-CONFIG_MFD_RK808=m
-CONFIG_MFD_RN5T618=m
-# CONFIG_MFD_SEC_CORE is not set
-CONFIG_MFD_SI476X_CORE=m
-CONFIG_MFD_SIMPLE_MFD_I2C=m
-CONFIG_MFD_SL28CPLD=m
-CONFIG_MFD_SM501=m
-CONFIG_MFD_SM501_GPIO=y
-CONFIG_MFD_SKY81452=m
-CONFIG_ABX500_CORE=y
-# CONFIG_AB3100_CORE is not set
-CONFIG_AB8500_CORE=y
-CONFIG_MFD_DB8500_PRCMU=y
-CONFIG_MFD_STMPE=y
-
-#
-# STMicroelectronics STMPE Interface Drivers
-#
-CONFIG_STMPE_I2C=y
-CONFIG_STMPE_SPI=y
-# end of STMicroelectronics STMPE Interface Drivers
-
-CONFIG_MFD_SUN6I_PRCM=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MFD_TI_AM335X_TSCADC=m
-CONFIG_MFD_LP3943=m
-# CONFIG_MFD_LP8788 is not set
-CONFIG_MFD_TI_LMU=m
-CONFIG_MFD_OMAP_USB_HOST=y
-# CONFIG_MFD_PALMAS is not set
-CONFIG_TPS6105X=m
-CONFIG_TPS65010=m
-CONFIG_TPS6507X=m
-CONFIG_MFD_TPS65086=m
-# CONFIG_MFD_TPS65090 is not set
-CONFIG_MFD_TPS65217=m
-CONFIG_MFD_TI_LP873X=m
-CONFIG_MFD_TI_LP87565=m
-CONFIG_MFD_TPS65218=m
-# CONFIG_MFD_TPS6586X is not set
-# CONFIG_MFD_TPS65910 is not set
-CONFIG_MFD_TPS65912=y
-CONFIG_MFD_TPS65912_I2C=m
-CONFIG_MFD_TPS65912_SPI=y
-# CONFIG_MFD_TPS80031 is not set
-CONFIG_TWL4030_CORE=y
-CONFIG_TWL4030_POWER=y
-# CONFIG_MFD_TWL4030_AUDIO is not set
-# CONFIG_TWL6040_CORE is not set
-CONFIG_MFD_WL1273_CORE=m
-CONFIG_MFD_LM3533=m
-# CONFIG_MFD_TC3589X is not set
-CONFIG_MFD_TMIO=y
-CONFIG_MFD_T7L66XB=y
-CONFIG_MFD_TC6387XB=y
-CONFIG_MFD_TC6393XB=y
-CONFIG_MFD_TQMX86=m
-CONFIG_MFD_VX855=m
-# CONFIG_MFD_LOCHNAGAR is not set
-CONFIG_MFD_ARIZONA=y
-CONFIG_MFD_ARIZONA_I2C=m
-CONFIG_MFD_ARIZONA_SPI=m
-CONFIG_MFD_CS47L24=y
-CONFIG_MFD_WM5102=y
-CONFIG_MFD_WM5110=y
-CONFIG_MFD_WM8997=y
-CONFIG_MFD_WM8998=y
-# CONFIG_MFD_WM8400 is not set
-CONFIG_MFD_WM831X=y
-# CONFIG_MFD_WM831X_I2C is not set
-CONFIG_MFD_WM831X_SPI=y
-# CONFIG_MFD_WM8350_I2C is not set
-CONFIG_MFD_WM8994=m
-# CONFIG_MFD_ROHM_BD718XX is not set
-# CONFIG_MFD_ROHM_BD70528 is not set
-# CONFIG_MFD_ROHM_BD71828 is not set
-CONFIG_MFD_ROHM_BD957XMUF=m
-# CONFIG_MFD_STM32_LPTIMER is not set
-# CONFIG_MFD_STM32_TIMERS is not set
-# CONFIG_MFD_STPMIC1 is not set
-CONFIG_MFD_STMFX=m
-CONFIG_MFD_WCD934X=m
-CONFIG_MFD_ATC260X_I2C=m
-CONFIG_MFD_KHADAS_MCU=m
-CONFIG_MFD_QCOM_PM8008=m
-CONFIG_MFD_VEXPRESS_SYSREG=m
-CONFIG_RAVE_SP_CORE=m
-CONFIG_MFD_INTEL_M10_BMC=m
-# end of Multifunction device drivers
-
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
-CONFIG_REGULATOR_USERSPACE_CONSUMER=m
-CONFIG_REGULATOR_88PG86X=m
-CONFIG_REGULATOR_88PM800=m
-CONFIG_REGULATOR_ACT8865=m
-CONFIG_REGULATOR_ACT8945A=m
-CONFIG_REGULATOR_AD5398=m
-# CONFIG_REGULATOR_ANATOP is not set
-# CONFIG_REGULATOR_AB8500 is not set
-CONFIG_REGULATOR_ARIZONA_LDO1=m
-CONFIG_REGULATOR_ATC260X=m
-CONFIG_REGULATOR_ARIZONA_MICSUPP=m
-CONFIG_REGULATOR_ARM_SCMI=m
-CONFIG_REGULATOR_AXP20X=m
-CONFIG_REGULATOR_BCM590XX=m
-CONFIG_REGULATOR_BD9571MWV=m
-CONFIG_REGULATOR_BD957XMUF=m
-CONFIG_REGULATOR_CPCAP=m
-CONFIG_REGULATOR_CROS_EC=m
-CONFIG_REGULATOR_DA9052=m
-CONFIG_REGULATOR_DA9062=m
-CONFIG_REGULATOR_DA9063=m
-CONFIG_REGULATOR_DA9210=m
-CONFIG_REGULATOR_DA9211=m
-CONFIG_REGULATOR_DA9121=m
-CONFIG_REGULATOR_DBX500_PRCMU=y
-CONFIG_REGULATOR_DB8500_PRCMU=y
-CONFIG_REGULATOR_FAN53555=m
-CONFIG_REGULATOR_FAN53880=m
-CONFIG_REGULATOR_GPIO=m
-CONFIG_REGULATOR_HI6421=m
-CONFIG_REGULATOR_HI6421V530=m
-CONFIG_REGULATOR_ISL9305=m
-CONFIG_REGULATOR_ISL6271A=m
-CONFIG_REGULATOR_LM363X=m
-CONFIG_REGULATOR_LP3971=m
-CONFIG_REGULATOR_LP3972=m
-CONFIG_REGULATOR_LP872X=m
-CONFIG_REGULATOR_LP873X=m
-CONFIG_REGULATOR_LP8755=m
-CONFIG_REGULATOR_LP87565=m
-CONFIG_REGULATOR_LTC3589=m
-CONFIG_REGULATOR_LTC3676=m
-CONFIG_REGULATOR_MAX14577=m
-CONFIG_REGULATOR_MAX1586=m
-CONFIG_REGULATOR_MAX77650=m
-CONFIG_REGULATOR_MAX8649=m
-CONFIG_REGULATOR_MAX8660=m
-CONFIG_REGULATOR_MAX8893=m
-CONFIG_REGULATOR_MAX8907=m
-CONFIG_REGULATOR_MAX8952=m
-CONFIG_REGULATOR_MAX8973=m
-CONFIG_REGULATOR_MAX77686=m
-CONFIG_REGULATOR_MAX77693=m
-CONFIG_REGULATOR_MAX77802=m
-CONFIG_REGULATOR_MAX77826=m
-CONFIG_REGULATOR_MC13XXX_CORE=m
-CONFIG_REGULATOR_MC13783=m
-CONFIG_REGULATOR_MC13892=m
-CONFIG_REGULATOR_MCP16502=m
-CONFIG_REGULATOR_MP5416=m
-CONFIG_REGULATOR_MP8859=m
-CONFIG_REGULATOR_MP886X=m
-CONFIG_REGULATOR_MPQ7920=m
-CONFIG_REGULATOR_MT6311=m
-CONFIG_REGULATOR_MT6315=m
-CONFIG_REGULATOR_MT6370=m
-CONFIG_REGULATOR_MT6323=m
-CONFIG_REGULATOR_MT6331=m
-CONFIG_REGULATOR_MT6332=m
-CONFIG_REGULATOR_MT6358=m
-CONFIG_REGULATOR_MT6359=m
-CONFIG_REGULATOR_MT6360=m
-CONFIG_REGULATOR_MT6370=m
-CONFIG_REGULATOR_MT6397=m
-# CONFIG_REGULATOR_PBIAS is not set
-CONFIG_REGULATOR_PCA9450=m
-CONFIG_REGULATOR_PF8X00=m
-CONFIG_REGULATOR_PCAP=m
-CONFIG_REGULATOR_PCF50633=m
-CONFIG_REGULATOR_PFUZE100=m
-CONFIG_REGULATOR_PV88060=m
-CONFIG_REGULATOR_PV88080=m
-CONFIG_REGULATOR_PV88090=m
-CONFIG_REGULATOR_PWM=m
-CONFIG_REGULATOR_QCOM_RPMH=m
-CONFIG_REGULATOR_QCOM_SPMI=m
-CONFIG_REGULATOR_QCOM_USB_VBUS=m
-CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
-CONFIG_REGULATOR_RK808=y
-CONFIG_REGULATOR_RN5T618=m
-CONFIG_REGULATOR_RT4801=m
-CONFIG_REGULATOR_RT4831=m
-CONFIG_REGULATOR_RT5120=m
-CONFIG_REGULATOR_RT5190A=m
-CONFIG_REGULATOR_RT6160=m
-CONFIG_REGULATOR_RT6245=m
-CONFIG_REGULATOR_RT5033=m
-CONFIG_REGULATOR_RT5120=m
-CONFIG_REGULATOR_RT5190A=m
-CONFIG_REGULATOR_RT6245=m
-CONFIG_REGULATOR_RT6160=m
-CONFIG_REGULATOR_RTMV20=m
-CONFIG_REGULATOR_SKY81452=m
-CONFIG_REGULATOR_SLG51000=m
-CONFIG_REGULATOR_SY7636A=m
-# CONFIG_REGULATOR_STM32_BOOSTER is not set
-# CONFIG_REGULATOR_STM32_VREFBUF is not set
-# CONFIG_REGULATOR_STM32_PWR is not set
-# CONFIG_REGULATOR_TI_ABB is not set
-CONFIG_REGULATOR_SY7636A=m
-CONFIG_REGULATOR_SY8106A=m
-CONFIG_REGULATOR_SY8824X=m
-CONFIG_REGULATOR_SY8827N=m
-CONFIG_REGULATOR_TPS51632=m
-CONFIG_REGULATOR_TPS6105X=m
-CONFIG_REGULATOR_TPS62360=m
-CONFIG_REGULATOR_TPS6286X=m
-CONFIG_REGULATOR_TPS65023=m
-CONFIG_REGULATOR_TPS6507X=m
-CONFIG_REGULATOR_TPS65086=m
-CONFIG_REGULATOR_TPS65132=m
-CONFIG_REGULATOR_TPS65217=m
-CONFIG_REGULATOR_TPS65218=m
-CONFIG_REGULATOR_TPS6524X=m
-CONFIG_REGULATOR_TPS65912=m
-CONFIG_REGULATOR_TPS68470=m
-# CONFIG_REGULATOR_TWL4030 is not set
-CONFIG_REGULATOR_UNIPHIER=y
-CONFIG_REGULATOR_VCTRL=m
-CONFIG_REGULATOR_VEXPRESS=m
-# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
-CONFIG_REGULATOR_WM831X=m
-CONFIG_REGULATOR_WM8994=m
-CONFIG_REGULATOR_QCOM_LABIBB=m
-CONFIG_RC_CORE=m
-CONFIG_RC_MAP=m
-CONFIG_LIRC=y
-CONFIG_RC_DECODERS=y
-CONFIG_IR_NEC_DECODER=m
-CONFIG_IR_RC5_DECODER=m
-CONFIG_IR_RC6_DECODER=m
-CONFIG_IR_JVC_DECODER=m
-CONFIG_IR_SONY_DECODER=m
-CONFIG_IR_SANYO_DECODER=m
-CONFIG_IR_SHARP_DECODER=m
-CONFIG_IR_MCE_KBD_DECODER=m
-CONFIG_IR_XMP_DECODER=m
-CONFIG_IR_IMON_DECODER=m
-CONFIG_IR_RCMM_DECODER=m
-CONFIG_RC_DEVICES=y
-CONFIG_RC_ATI_REMOTE=m
-CONFIG_IR_HIX5HD2=m
-CONFIG_IR_IMON=m
-CONFIG_IR_IMON_RAW=m
-CONFIG_IR_MCEUSB=m
-# CONFIG_IR_MESON is not set
-# CONFIG_IR_MTK is not set
-CONFIG_IR_REDRAT3=m
-CONFIG_IR_SPI=m
-CONFIG_IR_STREAMZAP=m
-CONFIG_IR_IGORPLUGUSB=m
-CONFIG_IR_IGUANA=m
-CONFIG_IR_TTUSBIR=m
-CONFIG_RC_LOOPBACK=m
-CONFIG_IR_GPIO_CIR=m
-CONFIG_IR_GPIO_TX=m
-CONFIG_IR_PWM_TX=m
-# CONFIG_RC_ST is not set
-# CONFIG_IR_SUNXI is not set
-CONFIG_IR_SERIAL=m
-CONFIG_IR_SERIAL_TRANSMITTER=y
-CONFIG_IR_SIR=m
-# CONFIG_IR_TANGO is not set
-CONFIG_RC_XBOX_DVD=m
-# CONFIG_IR_ZX is not set
-CONFIG_IR_TOY=m
-CONFIG_CEC_CORE=m
-CONFIG_CEC_NOTIFIER=y
-CONFIG_CEC_PIN=y
-CONFIG_MEDIA_CEC_RC=y
-# CONFIG_CEC_PIN_ERROR_INJ is not set
-CONFIG_MEDIA_CEC_SUPPORT=y
-CONFIG_CEC_CH7322=m
-CONFIG_CEC_CROS_EC=m
-# CONFIG_CEC_MESON_AO is not set
-# CONFIG_CEC_MESON_G12A_AO is not set
-CONFIG_CEC_GPIO=m
-# CONFIG_CEC_SAMSUNG_S5P is not set
-# CONFIG_CEC_STI is not set
-# CONFIG_CEC_STM32 is not set
-# CONFIG_CEC_TEGRA is not set
-CONFIG_USB_PULSE8_CEC=m
-CONFIG_USB_RAINSHADOW_CEC=m
-CONFIG_MEDIA_SUPPORT=m
-CONFIG_MEDIA_SUPPORT_FILTER=y
-CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
-
-#
-# Media device types
-#
-CONFIG_MEDIA_PLATFORM_DRIVERS=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_SDR_SUPPORT=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-# CONFIG_MEDIA_TEST_SUPPORT is not set
-# end of Media device types
-
-CONFIG_VIDEO_DEV=m
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_DVB_CORE=m
-
-#
-# Video4Linux options
-#
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L2_I2C=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_TUNER=m
-CONFIG_V4L2_MEM2MEM_DEV=m
-CONFIG_V4L2_FLASH_LED_CLASS=m
-CONFIG_V4L2_FWNODE=m
-CONFIG_VIDEOBUF_GEN=m
-CONFIG_VIDEOBUF_DMA_SG=m
-CONFIG_VIDEOBUF_VMALLOC=m
-# end of Video4Linux options
-
-#
-# Media controller options
-#
-CONFIG_MEDIA_CONTROLLER_DVB=y
-# end of Media controller options
-
-#
-# Digital TV options
-#
-CONFIG_DVB_MMAP=y
-CONFIG_DVB_NET=y
-CONFIG_DVB_MAX_ADAPTERS=8
-CONFIG_DVB_DYNAMIC_MINORS=y
-# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
-# CONFIG_DVB_ULE_DEBUG is not set
-# end of Digital TV options
-
-#
-# Media drivers
-#
-
-#
-# Drivers filtered as selected at 'Filter media drivers'
-#
-CONFIG_TTPCI_EEPROM=m
-CONFIG_MEDIA_USB_SUPPORT=y
-
-#
-# Webcam devices
-#
-CONFIG_USB_VIDEO_CLASS=m
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-CONFIG_USB_M5602=m
-CONFIG_USB_STV06XX=m
-CONFIG_USB_GL860=m
-CONFIG_USB_GSPCA_BENQ=m
-CONFIG_USB_GSPCA_CONEX=m
-CONFIG_USB_GSPCA_CPIA1=m
-CONFIG_USB_GSPCA_DTCS033=m
-CONFIG_USB_GSPCA_ETOMS=m
-CONFIG_USB_GSPCA_FINEPIX=m
-CONFIG_USB_GSPCA_JEILINJ=m
-CONFIG_USB_GSPCA_JL2005BCD=m
-CONFIG_USB_GSPCA_KINECT=m
-CONFIG_USB_GSPCA_KONICA=m
-CONFIG_USB_GSPCA_MARS=m
-CONFIG_USB_GSPCA_MR97310A=m
-CONFIG_USB_GSPCA_NW80X=m
-CONFIG_USB_GSPCA_OV519=m
-CONFIG_USB_GSPCA_OV534=m
-CONFIG_USB_GSPCA_OV534_9=m
-CONFIG_USB_GSPCA_PAC207=m
-CONFIG_USB_GSPCA_PAC7302=m
-CONFIG_USB_GSPCA_PAC7311=m
-CONFIG_USB_GSPCA_SE401=m
-CONFIG_USB_GSPCA_SN9C2028=m
-CONFIG_USB_GSPCA_SN9C20X=m
-CONFIG_USB_GSPCA_SONIXB=m
-CONFIG_USB_GSPCA_SONIXJ=m
-CONFIG_USB_GSPCA_SPCA500=m
-CONFIG_USB_GSPCA_SPCA501=m
-CONFIG_USB_GSPCA_SPCA505=m
-CONFIG_USB_GSPCA_SPCA506=m
-CONFIG_USB_GSPCA_SPCA508=m
-CONFIG_USB_GSPCA_SPCA561=m
-CONFIG_USB_GSPCA_SPCA1528=m
-CONFIG_USB_GSPCA_SQ905=m
-CONFIG_USB_GSPCA_SQ905C=m
-CONFIG_USB_GSPCA_SQ930X=m
-CONFIG_USB_GSPCA_STK014=m
-CONFIG_USB_GSPCA_STK1135=m
-CONFIG_USB_GSPCA_STV0680=m
-CONFIG_USB_GSPCA_SUNPLUS=m
-CONFIG_USB_GSPCA_T613=m
-CONFIG_USB_GSPCA_TOPRO=m
-CONFIG_USB_GSPCA_TOUPTEK=m
-CONFIG_USB_GSPCA_TV8532=m
-CONFIG_USB_GSPCA_VC032X=m
-CONFIG_USB_GSPCA_VICAM=m
-CONFIG_USB_GSPCA_XIRLINK_CIT=m
-CONFIG_USB_GSPCA_ZC3XX=m
-CONFIG_USB_PWC=m
-# CONFIG_USB_PWC_DEBUG is not set
-CONFIG_USB_PWC_INPUT_EVDEV=y
-CONFIG_VIDEO_CPIA2=m
-CONFIG_USB_ZR364XX=m
-CONFIG_USB_STKWEBCAM=m
-CONFIG_USB_S2255=m
-CONFIG_VIDEO_USBTV=m
-
-#
-# Analog TV USB devices
-#
-CONFIG_VIDEO_PVRUSB2=m
-CONFIG_VIDEO_PVRUSB2_SYSFS=y
-CONFIG_VIDEO_PVRUSB2_DVB=y
-# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
-CONFIG_VIDEO_HDPVR=m
-CONFIG_VIDEO_STK1160_COMMON=m
-CONFIG_VIDEO_STK1160=m
-CONFIG_VIDEO_GO7007=m
-CONFIG_VIDEO_GO7007_USB=m
-CONFIG_VIDEO_GO7007_LOADER=m
-CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
-
-#
-# Analog/digital TV USB devices
-#
-CONFIG_VIDEO_AU0828=m
-CONFIG_VIDEO_AU0828_V4L2=y
-CONFIG_VIDEO_AU0828_RC=y
-CONFIG_VIDEO_CX231XX=m
-CONFIG_VIDEO_CX231XX_RC=y
-CONFIG_VIDEO_CX231XX_ALSA=m
-CONFIG_VIDEO_CX231XX_DVB=m
-CONFIG_VIDEO_TM6000=m
-CONFIG_VIDEO_TM6000_ALSA=m
-CONFIG_VIDEO_TM6000_DVB=m
-
-#
-# Digital TV USB devices
-#
-CONFIG_DVB_USB=m
-# CONFIG_DVB_USB_DEBUG is not set
-CONFIG_DVB_USB_DIB3000MC=m
-CONFIG_DVB_USB_A800=m
-CONFIG_DVB_USB_DIBUSB_MB=m
-CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
-CONFIG_DVB_USB_DIBUSB_MC=m
-CONFIG_DVB_USB_DIB0700=m
-CONFIG_DVB_USB_UMT_010=m
-CONFIG_DVB_USB_CXUSB=m
-CONFIG_DVB_USB_CXUSB_ANALOG=y
-CONFIG_DVB_USB_M920X=m
-CONFIG_DVB_USB_DIGITV=m
-CONFIG_DVB_USB_VP7045=m
-CONFIG_DVB_USB_VP702X=m
-CONFIG_DVB_USB_GP8PSK=m
-CONFIG_DVB_USB_NOVA_T_USB2=m
-CONFIG_DVB_USB_TTUSB2=m
-CONFIG_DVB_USB_DTT200U=m
-CONFIG_DVB_USB_OPERA1=m
-CONFIG_DVB_USB_AF9005=m
-CONFIG_DVB_USB_AF9005_REMOTE=m
-CONFIG_DVB_USB_PCTV452E=m
-CONFIG_DVB_USB_DW2102=m
-CONFIG_DVB_USB_CINERGY_T2=m
-CONFIG_DVB_USB_DTV5100=m
-CONFIG_DVB_USB_AZ6027=m
-CONFIG_DVB_USB_TECHNISAT_USB2=m
-CONFIG_DVB_USB_V2=m
-CONFIG_DVB_USB_AF9015=m
-CONFIG_DVB_USB_AF9035=m
-CONFIG_DVB_USB_ANYSEE=m
-CONFIG_DVB_USB_AU6610=m
-CONFIG_DVB_USB_AZ6007=m
-CONFIG_DVB_USB_CE6230=m
-CONFIG_DVB_USB_EC168=m
-CONFIG_DVB_USB_GL861=m
-CONFIG_DVB_USB_LME2510=m
-CONFIG_DVB_USB_MXL111SF=m
-CONFIG_DVB_USB_RTL28XXU=m
-CONFIG_DVB_USB_DVBSKY=m
-CONFIG_DVB_USB_ZD1301=m
-CONFIG_DVB_TTUSB_BUDGET=m
-CONFIG_DVB_TTUSB_DEC=m
-CONFIG_SMS_USB_DRV=m
-CONFIG_DVB_B2C2_FLEXCOP_USB=m
-# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
-CONFIG_DVB_AS102=m
-
-#
-# Webcam, TV (analog/digital) USB devices
-#
-CONFIG_VIDEO_EM28XX=m
-CONFIG_VIDEO_EM28XX_V4L2=m
-CONFIG_VIDEO_EM28XX_ALSA=m
-CONFIG_VIDEO_EM28XX_DVB=m
-CONFIG_VIDEO_EM28XX_RC=m
-
-#
-# Software defined radio USB devices
-#
-CONFIG_USB_AIRSPY=m
-CONFIG_USB_HACKRF=m
-CONFIG_USB_MSI2500=m
-CONFIG_MEDIA_PCI_SUPPORT=y
-
-#
-# Media capture support
-#
-CONFIG_VIDEO_SOLO6X10=m
-CONFIG_VIDEO_TW5864=m
-CONFIG_VIDEO_TW68=m
-CONFIG_VIDEO_TW686X=m
-
-#
-# Media capture/analog TV support
-#
-CONFIG_VIDEO_IVTV=m
-# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
-CONFIG_VIDEO_IVTV_ALSA=m
-CONFIG_VIDEO_FB_IVTV=m
-CONFIG_VIDEO_HEXIUM_GEMINI=m
-CONFIG_VIDEO_HEXIUM_ORION=m
-CONFIG_VIDEO_MXB=m
-CONFIG_VIDEO_DT3155=m
-
-#
-# Media capture/analog/hybrid TV support
-#
-CONFIG_VIDEO_CX18=m
-CONFIG_VIDEO_CX18_ALSA=m
-CONFIG_VIDEO_CX23885=m
-CONFIG_MEDIA_ALTERA_CI=m
-CONFIG_VIDEO_CX25821=m
-CONFIG_VIDEO_CX25821_ALSA=m
-CONFIG_VIDEO_CX88=m
-CONFIG_VIDEO_CX88_ALSA=m
-CONFIG_VIDEO_CX88_BLACKBIRD=m
-CONFIG_VIDEO_CX88_DVB=m
-CONFIG_VIDEO_CX88_ENABLE_VP3054=y
-CONFIG_VIDEO_CX88_VP3054=m
-CONFIG_VIDEO_CX88_MPEG=m
-CONFIG_VIDEO_BT848=m
-CONFIG_DVB_BT8XX=m
-CONFIG_VIDEO_SAA7134=m
-CONFIG_VIDEO_SAA7134_ALSA=m
-CONFIG_VIDEO_SAA7134_RC=y
-CONFIG_VIDEO_SAA7134_DVB=m
-CONFIG_VIDEO_SAA7134_GO7007=m
-CONFIG_VIDEO_SAA7164=m
-
-#
-# Media digital TV PCI Adapters
-#
-CONFIG_DVB_AV7110_IR=y
-CONFIG_DVB_AV7110=m
-CONFIG_DVB_AV7110_OSD=y
-CONFIG_DVB_BUDGET_CORE=m
-CONFIG_DVB_BUDGET=m
-CONFIG_DVB_BUDGET_CI=m
-CONFIG_DVB_BUDGET_AV=m
-CONFIG_DVB_BUDGET_PATCH=m
-CONFIG_DVB_B2C2_FLEXCOP_PCI=m
-# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
-CONFIG_DVB_PLUTO2=m
-CONFIG_DVB_DM1105=m
-CONFIG_DVB_PT1=m
-CONFIG_DVB_PT3=m
-CONFIG_MANTIS_CORE=m
-CONFIG_DVB_MANTIS=m
-CONFIG_DVB_HOPPER=m
-CONFIG_DVB_NGENE=m
-CONFIG_DVB_DDBRIDGE=m
-# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set
-CONFIG_DVB_SMIPCIE=m
-CONFIG_DVB_NETUP_UNIDVB=m
-CONFIG_RADIO_ADAPTERS=y
-CONFIG_RADIO_TEA575X=m
-CONFIG_RADIO_SI470X=m
-CONFIG_USB_SI470X=m
-CONFIG_I2C_SI470X=m
-CONFIG_RADIO_SI4713=m
-CONFIG_USB_SI4713=m
-CONFIG_PLATFORM_SI4713=m
-CONFIG_I2C_SI4713=m
-CONFIG_RADIO_SI476X=m
-CONFIG_USB_MR800=m
-CONFIG_USB_DSBR=m
-CONFIG_RADIO_MAXIRADIO=m
-CONFIG_RADIO_SHARK=m
-CONFIG_RADIO_SHARK2=m
-CONFIG_USB_KEENE=m
-CONFIG_USB_RAREMONO=m
-CONFIG_USB_MA901=m
-CONFIG_RADIO_TEA5764=m
-CONFIG_RADIO_SAA7706H=m
-CONFIG_RADIO_TEF6862=m
-CONFIG_RADIO_WL1273=m
-CONFIG_RADIO_WL128X=m
-CONFIG_MEDIA_COMMON_OPTIONS=y
-
-#
-# common driver options
-#
-CONFIG_VIDEO_CX2341X=m
-CONFIG_VIDEO_TVEEPROM=m
-CONFIG_CYPRESS_FIRMWARE=m
-CONFIG_VIDEOBUF2_CORE=m
-CONFIG_VIDEOBUF2_V4L2=m
-CONFIG_VIDEOBUF2_MEMOPS=m
-CONFIG_VIDEOBUF2_DMA_CONTIG=m
-CONFIG_VIDEOBUF2_VMALLOC=m
-CONFIG_VIDEOBUF2_DMA_SG=m
-CONFIG_VIDEOBUF2_DVB=m
-CONFIG_DVB_B2C2_FLEXCOP=m
-CONFIG_VIDEO_SAA7146=m
-CONFIG_VIDEO_SAA7146_VV=m
-CONFIG_SMS_SIANO_MDTV=m
-CONFIG_SMS_SIANO_RC=y
-# CONFIG_SMS_SIANO_DEBUGFS is not set
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_CAFE_CCIC=m
-# CONFIG_VIDEO_MMP_CAMERA is not set
-CONFIG_VIDEO_CADENCE=y
-CONFIG_VIDEO_CADENCE_CSI2RX=m
-CONFIG_VIDEO_CADENCE_CSI2TX=m
-CONFIG_VIDEO_ASPEED=m
-CONFIG_VIDEO_MUX=m
-# CONFIG_VIDEO_STM32_DCMI is not set
-# CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS is not set
-# CONFIG_VIDEO_AM437X_VPFE is not set
-CONFIG_VIDEO_XILINX=m
-CONFIG_VIDEO_XILINX_CSI2RXSS=m
-# CONFIG_VIDEO_XILINX_TPG is not set
-CONFIG_VIDEO_XILINX_VTC=m
-# CONFIG_VIDEO_RCAR_CSI2 is not set
-# CONFIG_VIDEO_RCAR_VIN is not set
-# CONFIG_VIDEO_ATMEL_ISC is not set
-# CONFIG_VIDEO_ATMEL_XISC is not set
-# CONFIG_VIDEO_ATMEL_ISI is not set
-# CONFIG_VIDEO_MICROCHIP_CSI2DC is not set
-# CONFIG_VIDEO_SUN4I_CSI is not set
-# CONFIG_VIDEO_SUN6I_CSI is not set
-# CONFIG_VIDEO_TI_CAL is not set
-CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_VIDEO_ALLEGRO_DVT=m
-# CONFIG_VIDEO_CODA is not set
-# CONFIG_VIDEO_IMX_PXP is not set
-CONFIG_VIDEO_DW100=m
-CONFIG_VIDEO_IMX8_JPEG=m
-# CONFIG_VIDEO_MEDIATEK_VPU is not set
-CONFIG_VIDEO_MEDIATEK_MDP3=m
-CONFIG_VIDEO_TEGRA_VDE=m
-CONFIG_VIDEO_IMX_MIPI_CSIS=m
-CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
-CONFIG_VIDEO_MESON_GE2D=m
-CONFIG_VIDEO_AMPHION_VPU=m
-# CONFIG_VIDEO_SAMSUNG_S5P_G2D is not set
-# CONFIG_VIDEO_SAMSUNG_S5P_JPEG is not set
-# CONFIG_VIDEO_SAMSUNG_S5P_MFC is not set
-# CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC is not set
-# CONFIG_VIDEO_STI_BDISP is not set
-# CONFIG_VIDEO_STI_HVA is not set
-# CONFIG_VIDEO_STI_DELTA is not set
-# CONFIG_VIDEO_RENESAS_FDP1 is not set
-# CONFIG_VIDEO_RENESAS_JPU is not set
-# CONFIG_VIDEO_RENESAS_FCP is not set
-# CONFIG_VIDEO_RENESAS_VSP1 is not set
-# CONFIG_VIDEO_ROCKCHIP_RGA is not set
-# CONFIG_VIDEO_TI_VPE is not set
-# CONFIG_VIDEO_SUN8I_DEINTERLACE is not set
-# CONFIG_VIDEO_SUN8I_ROTATE is not set
-CONFIG_DVB_PLATFORM_DRIVERS=y
-CONFIG_DVB_C8SECTPFE=m
-CONFIG_SDR_PLATFORM_DRIVERS=y
-# CONFIG_VIDEO_RCAR_DRIF is not set
-
-#
-# MMC/SDIO DVB adapters
-#
-CONFIG_SMS_SDIO_DRV=m
-
-#
-# FireWire (IEEE 1394) Adapters
-#
-CONFIG_DVB_FIREDTV=m
-CONFIG_DVB_FIREDTV_INPUT=y
-# end of Media drivers
-
-#
-# Media ancillary drivers
-#
-CONFIG_MEDIA_ATTACH=y
-
-#
-# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
-#
-CONFIG_VIDEO_IR_I2C=m
-
-#
-# Audio decoders, processors and mixers
-#
-CONFIG_VIDEO_TVAUDIO=m
-CONFIG_VIDEO_TDA7432=m
-CONFIG_VIDEO_TDA9840=m
-CONFIG_VIDEO_TDA1997X=m
-CONFIG_VIDEO_TEA6415C=m
-CONFIG_VIDEO_TEA6420=m
-CONFIG_VIDEO_MSP3400=m
-CONFIG_VIDEO_CS3308=m
-CONFIG_VIDEO_CS5345=m
-CONFIG_VIDEO_CS53L32A=m
-CONFIG_VIDEO_TLV320AIC23B=m
-CONFIG_VIDEO_UDA1342=m
-CONFIG_VIDEO_WM8775=m
-CONFIG_VIDEO_WM8739=m
-CONFIG_VIDEO_VP27SMPX=m
-CONFIG_VIDEO_SONY_BTF_MPX=m
-# end of Audio decoders, processors and mixers
-
-#
-# RDS decoders
-#
-CONFIG_VIDEO_SAA6588=m
-# end of RDS decoders
-
-#
-# Video decoders
-#
-CONFIG_VIDEO_ADV7180=m
-CONFIG_VIDEO_ADV7183=m
-CONFIG_VIDEO_ADV748X=m
-# CONFIG_VIDEO_ADV7604 is not set
-# CONFIG_VIDEO_ADV7842 is not set
-CONFIG_VIDEO_BT819=m
-CONFIG_VIDEO_BT856=m
-CONFIG_VIDEO_BT866=m
-CONFIG_VIDEO_ISL7998X=m
-CONFIG_VIDEO_KS0127=m
-CONFIG_VIDEO_ML86V7667=m
-CONFIG_VIDEO_SAA7110=m
-CONFIG_VIDEO_SAA711X=m
-CONFIG_VIDEO_TC358743=m
-CONFIG_VIDEO_TC358743_CEC=y
-CONFIG_VIDEO_TVP514X=m
-CONFIG_VIDEO_TVP5150=m
-CONFIG_VIDEO_TVP7002=m
-CONFIG_VIDEO_TW2804=m
-CONFIG_VIDEO_TW9903=m
-CONFIG_VIDEO_TW9906=m
-CONFIG_VIDEO_TW9910=m
-CONFIG_VIDEO_VPX3220=m
-CONFIG_VIDEO_MAX9286=m
-
-#
-# Video and audio decoders
-#
-CONFIG_VIDEO_SAA717X=m
-CONFIG_VIDEO_CX25840=m
-# end of Video decoders
-
-#
-# Video encoders
-#
-CONFIG_VIDEO_SAA7127=m
-CONFIG_VIDEO_SAA7185=m
-CONFIG_VIDEO_ADV7170=m
-CONFIG_VIDEO_ADV7175=m
-CONFIG_VIDEO_ADV7343=m
-CONFIG_VIDEO_ADV7393=m
-CONFIG_VIDEO_AD9389B=m
-CONFIG_VIDEO_AK881X=m
-CONFIG_VIDEO_THS8200=m
-# end of Video encoders
-
-#
-# Video improvement chips
-#
-CONFIG_VIDEO_UPD64031A=m
-CONFIG_VIDEO_UPD64083=m
-# end of Video improvement chips
-
-#
-# Audio/Video compression chips
-#
-CONFIG_VIDEO_SAA6752HS=m
-# end of Audio/Video compression chips
-
-#
-# SDR tuner chips
-#
-CONFIG_SDR_MAX2175=m
-# end of SDR tuner chips
-
-#
-# Miscellaneous helper chips
-#
-CONFIG_VIDEO_THS7303=m
-CONFIG_VIDEO_M52790=m
-CONFIG_VIDEO_I2C=m
-CONFIG_VIDEO_ST_MIPID02=m
-# end of Miscellaneous helper chips
-
-#
-# Camera sensor devices
-#
-CONFIG_VIDEO_APTINA_PLL=m
-CONFIG_VIDEO_SMIAPP_PLL=m
-CONFIG_VIDEO_HI556=m
-CONFIG_VIDEO_IMX208=m
-CONFIG_VIDEO_IMX214=m
-CONFIG_VIDEO_IMX219=m
-CONFIG_VIDEO_IMX258=m
-CONFIG_VIDEO_IMX274=m
-CONFIG_VIDEO_IMX290=m
-CONFIG_VIDEO_IMX319=m
-CONFIG_VIDEO_IMX334=m
-CONFIG_VIDEO_IMX355=m
-CONFIG_VIDEO_OV02A10=m
-CONFIG_VIDEO_OV08D10=m
-CONFIG_VIDEO_OV2640=m
-CONFIG_VIDEO_OV2659=m
-CONFIG_VIDEO_OV2680=m
-CONFIG_VIDEO_OV2685=m
-CONFIG_VIDEO_OV5640=m
-CONFIG_VIDEO_OV5645=m
-CONFIG_VIDEO_OV5647=m
-CONFIG_VIDEO_OV5648=m
-CONFIG_VIDEO_OV6650=m
-CONFIG_VIDEO_OV5670=m
-CONFIG_VIDEO_OV5675=m
-CONFIG_VIDEO_OV5695=m
-CONFIG_VIDEO_OV7251=m
-CONFIG_VIDEO_OV772X=m
-CONFIG_VIDEO_OV7640=m
-CONFIG_VIDEO_OV7670=m
-CONFIG_VIDEO_OV7740=m
-CONFIG_VIDEO_OV8856=m
-CONFIG_VIDEO_OV8865=m
-CONFIG_VIDEO_OV9640=m
-CONFIG_VIDEO_OV9650=m
-CONFIG_VIDEO_OV13858=m
-CONFIG_VIDEO_VS6624=m
-CONFIG_VIDEO_MT9M001=m
-CONFIG_VIDEO_MT9M032=m
-CONFIG_VIDEO_MT9M111=m
-CONFIG_VIDEO_MT9P031=m
-CONFIG_VIDEO_MT9T001=m
-CONFIG_VIDEO_MT9T112=m
-CONFIG_VIDEO_MT9V011=m
-CONFIG_VIDEO_MT9V032=m
-CONFIG_VIDEO_MT9V111=m
-CONFIG_VIDEO_SR030PC30=m
-CONFIG_VIDEO_NOON010PC30=m
-CONFIG_VIDEO_OG01A1B=m
-CONFIG_VIDEO_M5MOLS=m
-CONFIG_VIDEO_RDACM20=m
-CONFIG_VIDEO_RDACM21=m
-CONFIG_VIDEO_RJ54N1=m
-CONFIG_VIDEO_S5K6AA=m
-CONFIG_VIDEO_S5K6A3=m
-CONFIG_VIDEO_S5K4ECGX=m
-CONFIG_VIDEO_S5K5BAF=m
-CONFIG_VIDEO_CCS=m
-CONFIG_VIDEO_SMIAPP=m
-CONFIG_VIDEO_ET8EK8=m
-CONFIG_VIDEO_S5C73M3=m
-# end of Camera sensor devices
-
-#
-# Lens drivers
-#
-CONFIG_VIDEO_AD5820=m
-CONFIG_VIDEO_AK7375=m
-CONFIG_VIDEO_DW9714=m
-CONFIG_VIDEO_DW9768=m
-CONFIG_VIDEO_DW9807_VCM=m
-# end of Lens drivers
-
-#
-# Flash devices
-#
-CONFIG_VIDEO_ADP1653=m
-CONFIG_VIDEO_LM3560=m
-CONFIG_VIDEO_LM3646=m
-# end of Flash devices
-
-#
-# SPI helper chips
-#
-CONFIG_VIDEO_GS1662=m
-# end of SPI helper chips
-
-#
-# Media SPI Adapters
-#
-CONFIG_CXD2880_SPI_DRV=m
-# end of Media SPI Adapters
-
-CONFIG_MEDIA_TUNER=m
-
-#
-# Customize TV tuners
-#
-CONFIG_MEDIA_TUNER_SIMPLE=m
-CONFIG_MEDIA_TUNER_TDA18250=m
-CONFIG_MEDIA_TUNER_TDA8290=m
-CONFIG_MEDIA_TUNER_TDA827X=m
-CONFIG_MEDIA_TUNER_TDA18271=m
-CONFIG_MEDIA_TUNER_TDA9887=m
-CONFIG_MEDIA_TUNER_TEA5761=m
-CONFIG_MEDIA_TUNER_TEA5767=m
-CONFIG_MEDIA_TUNER_MSI001=m
-CONFIG_MEDIA_TUNER_MT20XX=m
-CONFIG_MEDIA_TUNER_MT2060=m
-CONFIG_MEDIA_TUNER_MT2063=m
-CONFIG_MEDIA_TUNER_MT2266=m
-CONFIG_MEDIA_TUNER_MT2131=m
-CONFIG_MEDIA_TUNER_QT1010=m
-CONFIG_MEDIA_TUNER_XC2028=m
-CONFIG_MEDIA_TUNER_XC5000=m
-CONFIG_MEDIA_TUNER_XC4000=m
-CONFIG_MEDIA_TUNER_MXL5005S=m
-CONFIG_MEDIA_TUNER_MXL5007T=m
-CONFIG_MEDIA_TUNER_MC44S803=m
-CONFIG_MEDIA_TUNER_MAX2165=m
-CONFIG_MEDIA_TUNER_TDA18218=m
-CONFIG_MEDIA_TUNER_FC0011=m
-CONFIG_MEDIA_TUNER_FC0012=m
-CONFIG_MEDIA_TUNER_FC0013=m
-CONFIG_MEDIA_TUNER_TDA18212=m
-CONFIG_MEDIA_TUNER_E4000=m
-CONFIG_MEDIA_TUNER_FC2580=m
-CONFIG_MEDIA_TUNER_M88RS6000T=m
-CONFIG_MEDIA_TUNER_TUA9001=m
-CONFIG_MEDIA_TUNER_SI2157=m
-CONFIG_MEDIA_TUNER_IT913X=m
-CONFIG_MEDIA_TUNER_R820T=m
-CONFIG_MEDIA_TUNER_MXL301RF=m
-CONFIG_MEDIA_TUNER_QM1D1C0042=m
-CONFIG_MEDIA_TUNER_QM1D1B0004=m
-CONFIG_MEDIA_TUNER_AV201X=m
-CONFIG_MEDIA_TUNER_STV6120=m
-# end of Customize TV tuners
-
-#
-# Customise DVB Frontends
-#
-
-#
-# Multistandard (satellite) frontends
-#
-CONFIG_DVB_STB0899=m
-CONFIG_DVB_STB6100=m
-CONFIG_DVB_STV090x=m
-CONFIG_DVB_STV0910=m
-CONFIG_DVB_STV6110x=m
-CONFIG_DVB_STV6111=m
-CONFIG_DVB_MXL5XX=m
-CONFIG_DVB_M88DS3103=m
-
-#
-# Multistandard (cable + terrestrial) frontends
-#
-CONFIG_DVB_DRXK=m
-CONFIG_DVB_TDA18271C2DD=m
-CONFIG_DVB_SI2165=m
-CONFIG_DVB_MN88472=m
-CONFIG_DVB_MN88473=m
-
-#
-# DVB-S (satellite) frontends
-#
-CONFIG_DVB_CX24110=m
-CONFIG_DVB_CX24123=m
-CONFIG_DVB_MT312=m
-CONFIG_DVB_ZL10036=m
-CONFIG_DVB_ZL10039=m
-CONFIG_DVB_S5H1420=m
-CONFIG_DVB_STV0288=m
-CONFIG_DVB_STB6000=m
-CONFIG_DVB_STV0299=m
-CONFIG_DVB_STV6110=m
-CONFIG_DVB_STV0900=m
-CONFIG_DVB_TDA8083=m
-CONFIG_DVB_TDA10086=m
-CONFIG_DVB_TDA8261=m
-CONFIG_DVB_VES1X93=m
-CONFIG_DVB_TUNER_ITD1000=m
-CONFIG_DVB_TUNER_CX24113=m
-CONFIG_DVB_TDA826X=m
-CONFIG_DVB_TUA6100=m
-CONFIG_DVB_CX24116=m
-CONFIG_DVB_CX24117=m
-CONFIG_DVB_CX24120=m
-CONFIG_DVB_SI21XX=m
-CONFIG_DVB_TS2020=m
-CONFIG_DVB_DS3000=m
-CONFIG_DVB_MB86A16=m
-CONFIG_DVB_TDA10071=m
-
-#
-# DVB-T (terrestrial) frontends
-#
-CONFIG_DVB_SP8870=m
-CONFIG_DVB_SP887X=m
-CONFIG_DVB_CX22700=m
-CONFIG_DVB_CX22702=m
-# CONFIG_DVB_S5H1432 is not set
-CONFIG_DVB_DRXD=m
-CONFIG_DVB_L64781=m
-CONFIG_DVB_TDA1004X=m
-CONFIG_DVB_NXT6000=m
-CONFIG_DVB_MT352=m
-CONFIG_DVB_ZL10353=m
-CONFIG_DVB_DIB3000MB=m
-CONFIG_DVB_DIB3000MC=m
-CONFIG_DVB_DIB7000M=m
-CONFIG_DVB_DIB7000P=m
-CONFIG_DVB_DIB9000=m
-CONFIG_DVB_TDA10048=m
-CONFIG_DVB_AF9013=m
-CONFIG_DVB_EC100=m
-CONFIG_DVB_STV0367=m
-CONFIG_DVB_CXD2820R=m
-CONFIG_DVB_CXD2841ER=m
-CONFIG_DVB_RTL2830=m
-CONFIG_DVB_RTL2832=m
-CONFIG_DVB_RTL2832_SDR=m
-CONFIG_DVB_SI2168=m
-CONFIG_DVB_AS102_FE=m
-CONFIG_DVB_ZD1301_DEMOD=m
-CONFIG_DVB_GP8PSK_FE=m
-CONFIG_DVB_CXD2880=m
-
-#
-# DVB-C (cable) frontends
-#
-CONFIG_DVB_VES1820=m
-CONFIG_DVB_TDA10021=m
-CONFIG_DVB_TDA10023=m
-CONFIG_DVB_STV0297=m
-
-#
-# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
-#
-CONFIG_DVB_NXT200X=m
-CONFIG_DVB_OR51211=m
-CONFIG_DVB_OR51132=m
-CONFIG_DVB_BCM3510=m
-CONFIG_DVB_LGDT330X=m
-CONFIG_DVB_LGDT3305=m
-CONFIG_DVB_LGDT3306A=m
-CONFIG_DVB_LG2160=m
-CONFIG_DVB_S5H1409=m
-CONFIG_DVB_AU8522=m
-CONFIG_DVB_AU8522_DTV=m
-CONFIG_DVB_AU8522_V4L=m
-CONFIG_DVB_S5H1411=m
-
-#
-# ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_S921=m
-CONFIG_DVB_DIB8000=m
-CONFIG_DVB_MB86A20S=m
-
-#
-# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_TC90522=m
-CONFIG_DVB_MN88443X=m
-
-#
-# Digital terrestrial only tuners/PLL
-#
-CONFIG_DVB_PLL=m
-CONFIG_DVB_TUNER_DIB0070=m
-CONFIG_DVB_TUNER_DIB0090=m
-
-#
-# SEC control devices for DVB-S
-#
-CONFIG_DVB_DRX39XYJ=m
-CONFIG_DVB_LNBH25=m
-CONFIG_DVB_LNBH29=m
-CONFIG_DVB_LNBP21=m
-CONFIG_DVB_LNBP22=m
-CONFIG_DVB_ISL6405=m
-CONFIG_DVB_ISL6421=m
-CONFIG_DVB_ISL6422=m
-CONFIG_DVB_ISL6423=m
-CONFIG_DVB_A8293=m
-CONFIG_DVB_LGS8GL5=m
-CONFIG_DVB_LGS8GXX=m
-CONFIG_DVB_ATBM8830=m
-CONFIG_DVB_TDA665x=m
-CONFIG_DVB_IX2505V=m
-CONFIG_DVB_M88RS2000=m
-CONFIG_DVB_AF9033=m
-CONFIG_DVB_TAS2101=m
-CONFIG_DVB_HORUS3A=m
-CONFIG_DVB_ASCOT2E=m
-CONFIG_DVB_HELENE=m
-
-#
-# Common Interface (EN50221) controller drivers
-#
-CONFIG_DVB_CXD2099=m
-CONFIG_DVB_SP2=m
-# end of Customise DVB Frontends
-# end of Media ancillary drivers
-
-#
-# Graphics support
-#
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-# CONFIG_TEGRA_HOST1X is not set
-CONFIG_IMX_IPUV3_CORE=m
-CONFIG_BOOTSPLASH=y
-CONFIG_DRM=m
-CONFIG_DRM_MIPI_DBI=m
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_DP_AUX_CHARDEV=y
-# CONFIG_DRM_DEBUG_MM is not set
-# CONFIG_DRM_DEBUG_SELFTEST is not set
-CONFIG_DRM_KMS_HELPER=m
-CONFIG_DRM_KMS_FB_HELPER=y
-# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
-# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
-# CONFIG_DRM_DP_CEC is not set
-CONFIG_DRM_TTM=m
-CONFIG_DRM_TTM_DMA_PAGE_POOL=y
-CONFIG_DRM_VRAM_HELPER=m
-CONFIG_DRM_TTM_HELPER=m
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-CONFIG_DRM_VM=y
-CONFIG_DRM_SCHED=m
-
-#
-# I2C encoder or helper chips
-#
-CONFIG_DRM_I2C_CH7006=m
-CONFIG_DRM_I2C_SIL164=m
-CONFIG_DRM_I2C_NXP_TDA998X=m
-CONFIG_DRM_I2C_NXP_TDA9950=m
-# end of I2C encoder or helper chips
-
-#
-# ARM devices
-#
-# CONFIG_DRM_HDLCD is not set
-# CONFIG_DRM_MALI_DISPLAY is not set
-# CONFIG_DRM_KOMEDA is not set
-# end of ARM devices
-
-CONFIG_DRM_RADEON=m
-# CONFIG_DRM_RADEON_USERPTR is not set
-CONFIG_DRM_AMDGPU=m
-CONFIG_DRM_AMDGPU_SI=y
-CONFIG_DRM_AMDGPU_CIK=y
-# CONFIG_DRM_AMDGPU_USERPTR is not set
-# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set
-
-#
-# ACP (Audio CoProcessor) Configuration
-#
-CONFIG_DRM_AMD_ACP=y
-# end of ACP (Audio CoProcessor) Configuration
-
-#
-# Display Engine Configuration
-#
-CONFIG_DRM_AMD_DC=y
-CONFIG_DRM_AMD_DC_HDCP=y
-CONFIG_DRM_AMD_DC_SI=y
-# CONFIG_DEBUG_KERNEL_DC is not set
-# end of Display Engine Configuration
-
-CONFIG_DRM_NOUVEAU=m
-CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT=y
-CONFIG_NOUVEAU_PLATFORM_DRIVER=y
-CONFIG_NOUVEAU_DEBUG=5
-CONFIG_NOUVEAU_DEBUG_DEFAULT=3
-# CONFIG_NOUVEAU_DEBUG_MMU is not set
-# CONFIG_NOUVEAU_DEBUG_PUSH is not set
-# CONFIG_DRM_NOUVEAU_BACKLIGHT is not set
-CONFIG_DRM_VGEM=m
-CONFIG_DRM_VKMS=m
-CONFIG_DRM_EXYNOS=m
-
-#
-# CRTCs
-#
-CONFIG_DRM_EXYNOS_FIMD=y
-CONFIG_DRM_EXYNOS5433_DECON=y
-CONFIG_DRM_EXYNOS7_DECON=y
-CONFIG_DRM_EXYNOS_MIXER=y
-CONFIG_DRM_EXYNOS_VIDI=y
-
-#
-# Encoders and Bridges
-#
-CONFIG_DRM_EXYNOS_DPI=y
-CONFIG_DRM_EXYNOS_DSI=y
-CONFIG_DRM_EXYNOS_DP=y
-CONFIG_DRM_EXYNOS_HDMI=y
-CONFIG_DRM_EXYNOS_MIC=y
-
-#
-# Sub-drivers
-#
-CONFIG_DRM_EXYNOS_G2D=y
-CONFIG_DRM_EXYNOS_IPP=y
-CONFIG_DRM_EXYNOS_FIMC=y
-CONFIG_DRM_EXYNOS_ROTATOR=y
-CONFIG_DRM_EXYNOS_SCALER=y
-CONFIG_DRM_EXYNOS_GSC=y
-CONFIG_DRM_UDL=m
-CONFIG_DRM_AST=m
-CONFIG_DRM_MGAG200=m
-CONFIG_DRM_ARMADA=m
-CONFIG_DRM_ATMEL_HLCDC=m
-# CONFIG_DRM_RCAR_DU is not set
-CONFIG_DRM_RCAR_USE_CMM=y
-CONFIG_DRM_RCAR_DW_HDMI=m
-CONFIG_DRM_RCAR_LVDS=m
-# CONFIG_DRM_SUN4I is not set
-CONFIG_DRM_OMAP=m
-CONFIG_OMAP2_DSS_INIT=y
-CONFIG_OMAP_DSS_BASE=m
-CONFIG_OMAP2_DSS=m
-# CONFIG_OMAP2_DSS_DEBUG is not set
-# CONFIG_OMAP2_DSS_DEBUGFS is not set
-CONFIG_OMAP2_DSS_DPI=y
-CONFIG_OMAP2_DSS_VENC=y
-CONFIG_OMAP2_DSS_HDMI_COMMON=y
-CONFIG_OMAP4_DSS_HDMI=y
-CONFIG_OMAP4_DSS_HDMI_CEC=y
-CONFIG_OMAP5_DSS_HDMI=y
-CONFIG_OMAP2_DSS_SDI=y
-CONFIG_OMAP2_DSS_DSI=y
-CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
-CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y
-
-#
-# OMAPDRM External Display Device Drivers
-#
-CONFIG_DRM_OMAP_PANEL_DSI_CM=m
-# end of OMAPDRM External Display Device Drivers
-
-CONFIG_DRM_TILCDC=m
-CONFIG_DRM_QXL=m
-CONFIG_DRM_BOCHS=m
-CONFIG_DRM_VIRTIO_GPU=m
-# CONFIG_DRM_MSM is not set
-CONFIG_DRM_FSL_DCU=m
-# CONFIG_DRM_TEGRA is not set
-CONFIG_DRM_STM=m
-CONFIG_DRM_STM_DSI=m
-CONFIG_DRM_PANEL=y
-
-#
-# Display Panels
-#
-CONFIG_DRM_PANEL_ABT_Y030XX067A=m
-CONFIG_DRM_PANEL_ARM_VERSATILE=m
-CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
-CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
-CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
-CONFIG_DRM_PANEL_DSI_CM=m
-CONFIG_DRM_PANEL_LVDS=m
-CONFIG_DRM_PANEL_SIMPLE=m
-CONFIG_DRM_PANEL_ELIDA_KD35T133=m
-CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
-CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
-CONFIG_DRM_PANEL_ILITEK_IL9322=m
-CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
-CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
-CONFIG_DRM_PANEL_JDI_LT070ME05000=m
-CONFIG_DRM_PANEL_KHADAS_TS050=m
-CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
-CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
-CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
-CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
-CONFIG_DRM_PANEL_LG_LB035Q02=m
-CONFIG_DRM_PANEL_LG_LG4573=m
-CONFIG_DRM_PANEL_NEC_NL8048HL11=m
-CONFIG_DRM_PANEL_NOVATEK_NT35510=m
-CONFIG_DRM_PANEL_NOVATEK_NT35560=m
-CONFIG_DRM_PANEL_NOVATEK_NT39016=m
-CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
-CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
-CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
-CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
-CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
-CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
-CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
-CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
-CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
-CONFIG_DRM_PANEL_RONBO_RB070D30=m
-CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
-CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
-CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
-CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
-CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
-CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
-CONFIG_DRM_PANEL_SITRONIX_ST7701=m
-CONFIG_DRM_PANEL_SITRONIX_ST7703=m
-CONFIG_DRM_PANEL_SITRONIX_ST7789V=m
-CONFIG_DRM_PANEL_SONY_ACX424AKP=m
-CONFIG_DRM_PANEL_SONY_ACX565AKM=m
-CONFIG_DRM_PANEL_TDO_TL070WSH30=m
-CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
-CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
-CONFIG_DRM_PANEL_TPO_TPG110=m
-CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
-CONFIG_DRM_PANEL_VISIONOX_RM69299=m
-CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
-# end of Display Panels
-
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_PANEL_BRIDGE=y
-
-#
-# Display Interface Bridges
-#
-CONFIG_DRM_CDNS_DSI=m
-CONFIG_DRM_CHIPONE_ICN6211=m
-CONFIG_DRM_CHRONTEL_CH7033=m
-CONFIG_DRM_CROS_EC_ANX7688=m
-CONFIG_DRM_DISPLAY_CONNECTOR=m
-CONFIG_DRM_ITE_IT6505=m
-CONFIG_DRM_LONTIUM_LT8912B=m
-CONFIG_DRM_LONTIUM_LT9611=m
-CONFIG_DRM_LONTIUM_LT9611UXC=m
-CONFIG_DRM_ITE_IT66121=m
-CONFIG_DRM_LVDS_CODEC=m
-CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m
-CONFIG_DRM_NWL_MIPI_DSI=m
-CONFIG_DRM_NXP_PTN3460=m
-CONFIG_DRM_PARADE_PS8622=m
-CONFIG_DRM_PARADE_PS8640=m
-CONFIG_DRM_SIL_SII8620=m
-CONFIG_DRM_SII902X=m
-CONFIG_DRM_SII9234=m
-CONFIG_DRM_SIMPLE_BRIDGE=m
-CONFIG_DRM_THINE_THC63LVD1024=m
-CONFIG_DRM_TOSHIBA_TC358762=m
-CONFIG_DRM_TOSHIBA_TC358764=m
-CONFIG_DRM_TOSHIBA_TC358767=m
-CONFIG_DRM_TOSHIBA_TC358768=m
-CONFIG_DRM_TOSHIBA_TC358775=m
-CONFIG_DRM_TI_TFP410=m
-CONFIG_DRM_TI_SN65DSI83=m
-CONFIG_DRM_TI_SN65DSI86=m
-CONFIG_DRM_TI_TPD12S015=m
-CONFIG_DRM_ANALOGIX_ANX6345=m
-CONFIG_DRM_ANALOGIX_ANX78XX=m
-CONFIG_DRM_ANALOGIX_ANX7625=m
-CONFIG_DRM_ANALOGIX_DP=m
-CONFIG_DRM_I2C_ADV7511=m
-CONFIG_DRM_I2C_ADV7511_AUDIO=y
-CONFIG_DRM_I2C_ADV7511_CEC=y
-CONFIG_DRM_CDNS_MHDP8546=m
-CONFIG_DRM_DW_HDMI=m
-CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
-CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
-CONFIG_DRM_DW_HDMI_CEC=m
-CONFIG_DRM_DW_MIPI_DSI=m
-# end of Display Interface Bridges
-
-CONFIG_DRM_STI=m
-CONFIG_DRM_IMX=m
-CONFIG_DRM_IMX_PARALLEL_DISPLAY=m
-CONFIG_DRM_IMX_TVE=m
-CONFIG_DRM_IMX_LDB=m
-CONFIG_DRM_IMX_HDMI=m
-# CONFIG_DRM_V3D is not set
-# CONFIG_DRM_VC4 is not set
-CONFIG_DRM_ETNAVIV=m
-CONFIG_DRM_ETNAVIV_THERMAL=y
-CONFIG_DRM_ARCPGU=m
-# CONFIG_DRM_MEDIATEK is not set
-CONFIG_DRM_MEDIATEK_DP=m
-# CONFIG_DRM_ZTE is not set
-CONFIG_DRM_MXS=y
-CONFIG_DRM_MXSFB=m
-# CONFIG_DRM_MESON is not set
-CONFIG_DRM_CIRRUS_QEMU=m
-CONFIG_DRM_GM12U320=m
-CONFIG_DRM_PANEL_MIPI_DBI=m
-CONFIG_DRM_SIMPLEDRM=y
-CONFIG_TINYDRM_HX8357D=m
-CONFIG_TINYDRM_ILI9225=m
-CONFIG_TINYDRM_ILI9341=m
-CONFIG_TINYDRM_ILI9486=m
-CONFIG_TINYDRM_MI0283QT=m
-CONFIG_TINYDRM_REPAPER=m
-CONFIG_TINYDRM_ST7586=m
-CONFIG_TINYDRM_ST7735R=m
-CONFIG_DRM_PL111=m
-CONFIG_DRM_TVE200=m
-CONFIG_DRM_LIMA=m
-CONFIG_DRM_PANFROST=m
-# CONFIG_DRM_ASPEED_GFX is not set
-CONFIG_DRM_MCDE=m
-CONFIG_DRM_TIDSS=m
-CONFIG_DRM_GUD=m
-CONFIG_DRM_SSD130X=m
-CONFIG_DRM_SSD130X_I2C=m
-CONFIG_DRM_SPRD=m
-CONFIG_DRM_HYPERV=m
-CONFIG_DRM_LEGACY=y
-# CONFIG_DRM_TDFX is not set
-# CONFIG_DRM_R128 is not set
-# CONFIG_DRM_MGA is not set
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-CONFIG_DRM_EXPORT_FOR_TESTS=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m
-CONFIG_DRM_LIB_RANDOM=y
-
-#
-# Frame buffer Devices
-#
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_NOTIFY=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_DDC=m
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SYS_FILLRECT=m
-CONFIG_FB_SYS_COPYAREA=m
-CONFIG_FB_SYS_IMAGEBLIT=m
-CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA=y
-CONFIG_FB_FOREIGN_ENDIAN=y
-CONFIG_FB_BOTH_ENDIAN=y
-# CONFIG_FB_BIG_ENDIAN is not set
-# CONFIG_FB_LITTLE_ENDIAN is not set
-CONFIG_FB_SYS_FOPS=m
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SVGALIB=m
-CONFIG_FB_BACKLIGHT=m
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
-
-#
-# Frame buffer hardware drivers
-#
-CONFIG_FB_CIRRUS=m
-CONFIG_FB_PM2=m
-CONFIG_FB_PM2_FIFO_DISCONNECT=y
-# CONFIG_FB_ARMCLCD is not set
-# CONFIG_FB_IMX is not set
-CONFIG_FB_CYBER2000=m
-CONFIG_FB_CYBER2000_DDC=y
-CONFIG_FB_ASILIANT=y
-CONFIG_FB_IMSTT=y
-CONFIG_FB_UVESA=m
-CONFIG_FB_EFI=y
-CONFIG_FB_OPENCORES=m
-CONFIG_FB_S1D13XXX=m
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-# CONFIG_FB_I740 is not set
-# CONFIG_FB_MATROX is not set
-CONFIG_FB_RADEON=m
-CONFIG_FB_RADEON_I2C=y
-CONFIG_FB_RADEON_BACKLIGHT=y
-# CONFIG_FB_RADEON_DEBUG is not set
-CONFIG_FB_ATY128=m
-CONFIG_FB_ATY128_BACKLIGHT=y
-# CONFIG_FB_ATY is not set
-# CONFIG_FB_S3 is not set
-# CONFIG_FB_SAVAGE is not set
-# CONFIG_FB_SIS is not set
-CONFIG_FB_NEOMAGIC=m
-CONFIG_FB_KYRO=m
-# CONFIG_FB_3DFX is not set
-# CONFIG_FB_VOODOO1 is not set
-CONFIG_FB_VT8623=m
-CONFIG_FB_TRIDENT=m
-CONFIG_FB_ARK=m
-CONFIG_FB_PM3=m
-CONFIG_FB_CARMINE=m
-CONFIG_FB_CARMINE_DRAM_EVAL=y
-# CONFIG_CARMINE_DRAM_CUSTOM is not set
-# CONFIG_FB_VT8500 is not set
-# CONFIG_FB_WM8505 is not set
-# CONFIG_FB_SH_MOBILE_LCDC is not set
-CONFIG_FB_TMIO=m
-CONFIG_FB_TMIO_ACCELL=y
-CONFIG_FB_SM501=m
-CONFIG_FB_SMSCUFX=m
-CONFIG_FB_UDL=m
-CONFIG_FB_IBM_GXT4500=m
-# CONFIG_FB_XILINX is not set
-# CONFIG_FB_DA8XX is not set
-# CONFIG_FB_VIRTUAL is not set
-CONFIG_FB_METRONOME=m
-CONFIG_FB_MB862XX=m
-CONFIG_FB_MB862XX_PCI_GDC=y
-CONFIG_FB_MB862XX_I2C=y
-CONFIG_FB_MX3=y
-CONFIG_FB_SIMPLE=y
-CONFIG_FB_SSD1307=m
-CONFIG_FB_SM712=m
-# end of Frame buffer Devices
-
-#
-# Backlight & LCD device support
-#
-CONFIG_LCD_CLASS_DEVICE=m
-CONFIG_LCD_L4F00242T03=m
-CONFIG_LCD_LMS283GF05=m
-CONFIG_LCD_LTV350QV=m
-CONFIG_LCD_ILI922X=m
-CONFIG_LCD_ILI9320=m
-CONFIG_LCD_TDO24M=m
-CONFIG_LCD_VGG2432A4=m
-CONFIG_LCD_PLATFORM=m
-CONFIG_LCD_AMS369FG06=m
-CONFIG_LCD_LMS501KF03=m
-CONFIG_LCD_HX8357=m
-CONFIG_LCD_OTM3225A=m
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_KTD253=m
-CONFIG_BACKLIGHT_LM3533=m
-CONFIG_BACKLIGHT_PWM=m
-CONFIG_BACKLIGHT_MT6370=m
-CONFIG_BACKLIGHT_DA9052=m
-CONFIG_BACKLIGHT_MT6370=m
-CONFIG_BACKLIGHT_QCOM_WLED=m
-CONFIG_BACKLIGHT_RT4831=m
-CONFIG_BACKLIGHT_WM831X=m
-CONFIG_BACKLIGHT_ADP8860=m
-CONFIG_BACKLIGHT_ADP8870=m
-CONFIG_BACKLIGHT_PCF50633=m
-CONFIG_BACKLIGHT_LM3630A=m
-CONFIG_BACKLIGHT_LM3639=m
-CONFIG_BACKLIGHT_LP855X=m
-# CONFIG_BACKLIGHT_PANDORA is not set
-CONFIG_BACKLIGHT_SKY81452=m
-CONFIG_BACKLIGHT_TPS65217=m
-CONFIG_BACKLIGHT_GPIO=m
-CONFIG_BACKLIGHT_LV5207LP=m
-CONFIG_BACKLIGHT_BD6107=m
-CONFIG_BACKLIGHT_ARCXCNN=m
-CONFIG_BACKLIGHT_RAVE_SP=m
-CONFIG_BACKLIGHT_LED=m
-# end of Backlight & LCD device support
-
-CONFIG_VGASTATE=m
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_HDMI=y
-
-#
-# Console display driver support
-#
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
-# end of Console display driver support
-
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# end of Graphics support
-
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_PCM_ELD=y
-CONFIG_SND_PCM_IEC958=y
-CONFIG_SND_DMAENGINE_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_SEQ_DEVICE=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_PCM_TIMER=y
-CONFIG_SND_HRTIMER=m
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_MAX_CARDS=32
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_PROC_FS=y
-CONFIG_SND_VERBOSE_PROCFS=y
-CONFIG_SND_CTL_FAST_LOOKUP=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_CTL_INPUT_VALIDATION=y
-CONFIG_SND_VMASTER=y
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_SEQUENCER_OSS=m
-CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
-CONFIG_SND_SEQ_MIDI_EVENT=m
-CONFIG_SND_SEQ_MIDI=m
-CONFIG_SND_SEQ_MIDI_EMUL=m
-CONFIG_SND_SEQ_VIRMIDI=m
-CONFIG_SND_MPU401_UART=m
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_OPL3_LIB_SEQ=m
-CONFIG_SND_VX_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DRIVERS=y
-CONFIG_SND_DUMMY=m
-CONFIG_SND_ALOOP=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_MTS64=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_PORTMAN2X4=m
-CONFIG_SND_AC97_POWER_SAVE=y
-CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
-CONFIG_SND_PCI=y
-CONFIG_SND_AD1889=m
-# CONFIG_SND_ALS300 is not set
-# CONFIG_SND_ALI5451 is not set
-CONFIG_SND_ATIIXP=m
-CONFIG_SND_ATIIXP_MODEM=m
-CONFIG_SND_AU8810=m
-CONFIG_SND_AU8820=m
-CONFIG_SND_AU8830=m
-CONFIG_SND_AW2=m
-# CONFIG_SND_AZT3328 is not set
-CONFIG_SND_BT87X=m
-CONFIG_SND_BT87X_OVERCLOCK=y
-CONFIG_SND_CA0106=m
-CONFIG_SND_CMIPCI=m
-CONFIG_SND_OXYGEN_LIB=m
-CONFIG_SND_OXYGEN=m
-CONFIG_SND_CS4281=m
-CONFIG_SND_CS46XX=m
-CONFIG_SND_CS46XX_NEW_DSP=y
-CONFIG_SND_CTXFI=m
-CONFIG_SND_DARLA20=m
-CONFIG_SND_GINA20=m
-CONFIG_SND_LAYLA20=m
-CONFIG_SND_DARLA24=m
-CONFIG_SND_GINA24=m
-CONFIG_SND_LAYLA24=m
-CONFIG_SND_MONA=m
-CONFIG_SND_MIA=m
-CONFIG_SND_ECHO3G=m
-CONFIG_SND_INDIGO=m
-CONFIG_SND_INDIGOIO=m
-CONFIG_SND_INDIGODJ=m
-CONFIG_SND_INDIGOIOX=m
-CONFIG_SND_INDIGODJX=m
-# CONFIG_SND_EMU10K1 is not set
-# CONFIG_SND_EMU10K1X is not set
-CONFIG_SND_ENS1370=m
-CONFIG_SND_ENS1371=m
-# CONFIG_SND_ES1938 is not set
-# CONFIG_SND_ES1968 is not set
-CONFIG_SND_FM801=m
-CONFIG_SND_FM801_TEA575X_BOOL=y
-CONFIG_SND_HDSP=m
-CONFIG_SND_HDSPM=m
-# CONFIG_SND_ICE1712 is not set
-CONFIG_SND_ICE1724=m
-CONFIG_SND_INTEL8X0=m
-CONFIG_SND_INTEL8X0M=m
-CONFIG_SND_KORG1212=m
-CONFIG_SND_LOLA=m
-# CONFIG_SND_MAESTRO3 is not set
-CONFIG_SND_MIXART=m
-CONFIG_SND_NM256=m
-CONFIG_SND_PCXHR=m
-CONFIG_SND_RIPTIDE=m
-CONFIG_SND_RME32=m
-CONFIG_SND_RME96=m
-CONFIG_SND_RME9652=m
-# CONFIG_SND_SONICVIBES is not set
-# CONFIG_SND_TRIDENT is not set
-CONFIG_SND_VIA82XX=m
-CONFIG_SND_VIA82XX_MODEM=m
-CONFIG_SND_VIRTUOSO=m
-CONFIG_SND_VX222=m
-CONFIG_SND_YMFPCI=m
-
-#
-# HD-Audio
-#
-CONFIG_SND_HDA=m
-CONFIG_SND_HDA_GENERIC_LEDS=y
-CONFIG_SND_HDA_INTEL=m
-# CONFIG_SND_HDA_TEGRA is not set
-CONFIG_SND_HDA_HWDEP=y
-CONFIG_SND_HDA_RECONFIG=y
-CONFIG_SND_HDA_INPUT_BEEP=y
-CONFIG_SND_HDA_INPUT_BEEP_MODE=1
-CONFIG_SND_HDA_PATCH_LOADER=y
-CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m
-CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m
-CONFIG_SND_HDA_CODEC_REALTEK=m
-CONFIG_SND_HDA_CODEC_ANALOG=m
-CONFIG_SND_HDA_CODEC_SIGMATEL=m
-CONFIG_SND_HDA_CODEC_VIA=m
-CONFIG_SND_HDA_CODEC_HDMI=m
-CONFIG_SND_HDA_CODEC_CIRRUS=m
-CONFIG_SND_HDA_CODEC_CONEXANT=m
-CONFIG_SND_HDA_CODEC_CA0110=m
-CONFIG_SND_HDA_CODEC_CA0132=m
-CONFIG_SND_HDA_CODEC_CA0132_DSP=y
-CONFIG_SND_HDA_CODEC_CMEDIA=m
-CONFIG_SND_HDA_CODEC_SI3054=m
-CONFIG_SND_HDA_GENERIC=m
-CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
-# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
-# end of HD-Audio
-
-CONFIG_SND_HDA_CORE=m
-CONFIG_SND_HDA_DSP_LOADER=y
-CONFIG_SND_HDA_COMPONENT=y
-CONFIG_SND_HDA_PREALLOC_SIZE=2048
-CONFIG_SND_VIRTIO=m
-CONFIG_SND_INTEL_DSP_CONFIG=m
-CONFIG_SND_ARM=y
-# CONFIG_SND_ARMAACI is not set
-
-#
-# Atmel devices (AT91)
-#
-# CONFIG_SND_ATMEL_AC97C is not set
-# end of Atmel devices (AT91)
-
-CONFIG_SND_SPI=y
-CONFIG_SND_USB=y
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
-CONFIG_SND_USB_UA101=m
-CONFIG_SND_USB_CAIAQ=m
-CONFIG_SND_USB_CAIAQ_INPUT=y
-CONFIG_SND_USB_6FIRE=m
-CONFIG_SND_USB_HIFACE=m
-CONFIG_SND_BCD2000=m
-CONFIG_SND_USB_LINE6=m
-CONFIG_SND_USB_POD=m
-CONFIG_SND_USB_PODHD=m
-CONFIG_SND_USB_TONEPORT=m
-CONFIG_SND_USB_VARIAX=m
-CONFIG_SND_FIREWIRE=y
-CONFIG_SND_FIREWIRE_LIB=m
-CONFIG_SND_DICE=m
-CONFIG_SND_OXFW=m
-CONFIG_SND_ISIGHT=m
-CONFIG_SND_FIREWORKS=m
-CONFIG_SND_BEBOB=m
-CONFIG_SND_FIREWIRE_DIGI00X=m
-CONFIG_SND_FIREWIRE_TASCAM=m
-CONFIG_SND_FIREWIRE_MOTU=m
-CONFIG_SND_FIREFACE=m
-CONFIG_SND_PCMCIA=y
-CONFIG_SND_VXPOCKET=m
-CONFIG_SND_PDAUDIOCF=m
-CONFIG_SND_SOC=m
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_TOPOLOGY=y
-# CONFIG_SND_SOC_ADI is not set
-CONFIG_SND_SOC_AMD_ACP=m
-CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m
-CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m
-CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
-CONFIG_SND_ATMEL_SOC=m
-# CONFIG_SND_ATMEL_SOC_CLASSD is not set
-# CONFIG_SND_ATMEL_SOC_PDMIC is not set
-# CONFIG_SND_ATMEL_SOC_I2S is not set
-CONFIG_SND_SOC_MIKROE_PROTO=m
-# CONFIG_SND_MCHP_SOC_I2S_MCC is not set
-CONFIG_SND_MCHP_SOC_PDMC=m
-CONFIG_SND_MCHP_SOC_SPDIFTX=m
-CONFIG_SND_MCHP_SOC_SPDIFRX=m
-CONFIG_SND_BCM63XX_I2S_WHISTLER=m
-CONFIG_SND_DESIGNWARE_I2S=m
-CONFIG_SND_DESIGNWARE_PCM=y
-
-#
-# SoC Audio for Freescale CPUs
-#
-
-#
-# Common SoC Audio options for Freescale CPUs:
-#
-CONFIG_SND_SOC_FSL_ASRC=m
-CONFIG_SND_SOC_FSL_SAI=m
-CONFIG_SND_SOC_FSL_MQS=m
-CONFIG_SND_SOC_FSL_AUDMIX=m
-CONFIG_SND_SOC_FSL_SSI=m
-CONFIG_SND_SOC_FSL_SPDIF=m
-CONFIG_SND_SOC_FSL_ESAI=m
-CONFIG_SND_SOC_FSL_MICFIL=m
-CONFIG_SND_SOC_FSL_EASRC=m
-CONFIG_SND_SOC_FSL_XCVR=m
-CONFIG_SND_SOC_FSL_AUD2HTX=m
-CONFIG_SND_SOC_FSL_RPMSG=m
-CONFIG_SND_SOC_IMX_AUDMUX=m
-CONFIG_SND_SOC_IMX_CARD=m
-# CONFIG_SND_IMX_SOC is not set
-# end of SoC Audio for Freescale CPUs
-
-CONFIG_SND_I2S_HI6210_I2S=m
-# CONFIG_SND_KIRKWOOD_SOC is not set
-CONFIG_SND_SOC_IMG=y
-CONFIG_SND_SOC_IMG_I2S_IN=m
-CONFIG_SND_SOC_IMG_I2S_OUT=m
-CONFIG_SND_SOC_IMG_PARALLEL_OUT=m
-CONFIG_SND_SOC_IMG_SPDIF_IN=m
-CONFIG_SND_SOC_IMG_SPDIF_OUT=m
-CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m
-# CONFIG_SND_SOC_MT2701 is not set
-# CONFIG_SND_SOC_MT6797 is not set
-# CONFIG_SND_SOC_MT8173 is not set
-# CONFIG_SND_SOC_MT8183 is not set
-CONFIG_SND_SOC_MT8186=m
-CONFIG_SND_SOC_MT8186_MT6366_DA7219_MAX98357=m
-CONFIG_SND_SOC_MT8186_MT6366_RT1019_RT5682S=m
-CONFIG_SND_SOC_MTK_BTCVSD=m
-CONFIG_SND_SOC_MT8192=m
-CONFIG_PINCTRL_MT8195=y
-CONFIG_PINCTRL_MT8365=y
-CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682=m
-
-#
-# ASoC support for Amlogic platforms
-#
-# CONFIG_SND_MESON_AIU is not set
-# CONFIG_SND_MESON_AXG_FRDDR is not set
-# CONFIG_SND_MESON_AXG_TODDR is not set
-# CONFIG_SND_MESON_AXG_TDMIN is not set
-# CONFIG_SND_MESON_AXG_TDMOUT is not set
-# CONFIG_SND_MESON_AXG_SOUND_CARD is not set
-# CONFIG_SND_MESON_AXG_SPDIFOUT is not set
-# CONFIG_SND_MESON_AXG_SPDIFIN is not set
-# CONFIG_SND_MESON_AXG_PDM is not set
-# CONFIG_SND_MESON_GX_SOUND_CARD is not set
-# CONFIG_SND_MESON_G12A_TOACODEC is not set
-# CONFIG_SND_MESON_G12A_TOHDMITX is not set
-# CONFIG_SND_SOC_MESON_T9015 is not set
-# end of ASoC support for Amlogic platforms
-
-# CONFIG_SND_PXA_SOC_SSP is not set
-# CONFIG_SND_MMP_SOC_SSPA is not set
-# CONFIG_SND_PXA910_SOC is not set
-# CONFIG_SND_SOC_QCOM is not set
-# CONFIG_SND_SOC_ROCKCHIP is not set
-# CONFIG_SND_SOC_SAMSUNG is not set
-
-#
-# SoC Audio support for Renesas SoCs
-#
-# CONFIG_SND_SOC_SH4_FSI is not set
-# CONFIG_SND_SOC_RCAR is not set
-# end of SoC Audio support for Renesas SoCs
-
-# CONFIG_SND_SOC_SIRF is not set
-CONFIG_SND_SOC_SOF_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_PCI=m
-CONFIG_SND_SOC_SOF_OF=m
-# CONFIG_SND_SOC_SOF_DEBUG_PROBES is not set
-# CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT is not set
-CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m
-CONFIG_SND_SOC_SOF_AMD_RENOIR=m
-CONFIG_SND_SOC_SOF=m
-# CONFIG_SND_SOC_STI is not set
-
-#
-# STMicroelectronics STM32 SOC audio support
-#
-# CONFIG_SND_SOC_STM32_SAI is not set
-# CONFIG_SND_SOC_STM32_I2S is not set
-# CONFIG_SND_SOC_STM32_SPDIFRX is not set
-# end of STMicroelectronics STM32 SOC audio support
-
-#
-# Allwinner SoC Audio support
-#
-# CONFIG_SND_SUN4I_CODEC is not set
-# CONFIG_SND_SUN8I_CODEC is not set
-# CONFIG_SND_SUN8I_CODEC_ANALOG is not set
-# CONFIG_SND_SUN4I_I2S is not set
-# CONFIG_SND_SUN4I_SPDIF is not set
-CONFIG_SND_SUN50I_DMIC=m
-# end of Allwinner SoC Audio support
-
-#
-# Audio support for Texas Instruments SoCs
-#
-
-#
-# Texas Instruments DAI support for:
-#
-# CONFIG_SND_SOC_DAVINCI_MCASP is not set
-# CONFIG_SND_SOC_OMAP_DMIC is not set
-# CONFIG_SND_SOC_OMAP_MCBSP is not set
-# CONFIG_SND_SOC_OMAP_MCPDM is not set
-
-#
-# Audio support for boards with Texas Instruments SoCs
-#
-# CONFIG_SND_SOC_NOKIA_RX51 is not set
-# CONFIG_SND_SOC_OMAP3_PANDORA is not set
-# CONFIG_SND_SOC_OMAP3_TWL4030 is not set
-# CONFIG_SND_SOC_OMAP_HDMI is not set
-# end of Audio support for Texas Instruments SoCs
-
-# CONFIG_SND_SOC_UNIPHIER is not set
-# CONFIG_SND_SOC_UX500 is not set
-CONFIG_SND_SOC_XILINX_I2S=m
-CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
-CONFIG_SND_SOC_XILINX_SPDIF=m
-CONFIG_SND_SOC_XTFPGA_I2S=m
-# CONFIG_ZX_SPDIF is not set
-# CONFIG_ZX_I2S is not set
-CONFIG_ZX_TDM=m
-CONFIG_SND_SOC_I2C_AND_SPI=m
-
-#
-# CODEC drivers
-#
-CONFIG_SND_SOC_AC97_CODEC=m
-CONFIG_SND_SOC_ADAU1372_I2C=m
-CONFIG_SND_SOC_ADAU1372_SPI=m
-CONFIG_SND_SOC_ADAU_UTILS=m
-CONFIG_SND_SOC_ADAU1701=m
-CONFIG_SND_SOC_ADAU17X1=m
-CONFIG_SND_SOC_ADAU1761=m
-CONFIG_SND_SOC_ADAU1761_I2C=m
-CONFIG_SND_SOC_ADAU1761_SPI=m
-CONFIG_SND_SOC_ADAU7002=m
-CONFIG_SND_SOC_ADAU7118=m
-CONFIG_SND_SOC_ADAU7118_HW=m
-CONFIG_SND_SOC_ADAU7118_I2C=m
-CONFIG_SND_SOC_AK4104=m
-CONFIG_SND_SOC_AK4118=m
-CONFIG_SND_SOC_AK4458=m
-CONFIG_SND_SOC_AK4554=m
-CONFIG_SND_SOC_AK4613=m
-CONFIG_SND_SOC_AK4642=m
-CONFIG_SND_SOC_AK5386=m
-CONFIG_SND_SOC_AK5558=m
-CONFIG_SND_SOC_ALC5623=m
-CONFIG_SND_SOC_AW8738=m
-CONFIG_SND_SOC_BD28623=m
-CONFIG_SND_SOC_BT_SCO=m
-CONFIG_SND_SOC_CPCAP=m
-CONFIG_SND_SOC_CROS_EC_CODEC=m
-CONFIG_SND_SOC_CS35L32=m
-CONFIG_SND_SOC_CS35L33=m
-CONFIG_SND_SOC_CS35L34=m
-CONFIG_SND_SOC_CS35L35=m
-CONFIG_SND_SOC_CS35L36=m
-CONFIG_SND_SOC_CS42L42=m
-CONFIG_SND_SOC_CS42L51=m
-CONFIG_SND_SOC_CS42L51_I2C=m
-CONFIG_SND_SOC_CS42L52=m
-CONFIG_SND_SOC_CS42L56=m
-CONFIG_SND_SOC_CS42L73=m
-CONFIG_SND_SOC_CS42L83=m
-CONFIG_SND_SOC_CS4234=m
-CONFIG_SND_SOC_CS4265=m
-CONFIG_SND_SOC_CS4270=m
-CONFIG_SND_SOC_CS4271=m
-CONFIG_SND_SOC_CS4271_I2C=m
-CONFIG_SND_SOC_CS4271_SPI=m
-CONFIG_SND_SOC_CS42XX8=m
-CONFIG_SND_SOC_CS42XX8_I2C=m
-CONFIG_SND_SOC_CS43130=m
-CONFIG_SND_SOC_CS4341=m
-CONFIG_SND_SOC_CS4349=m
-CONFIG_SND_SOC_CS53L30=m
-CONFIG_SND_SOC_CX2072X=m
-CONFIG_SND_SOC_DA7213=m
-CONFIG_SND_SOC_DA7219=m
-CONFIG_SND_SOC_DMIC=m
-CONFIG_SND_SOC_HDMI_CODEC=m
-CONFIG_SND_SOC_ES7134=m
-CONFIG_SND_SOC_ES7241=m
-CONFIG_SND_SOC_ES8316=m
-CONFIG_SND_SOC_ES8326=m
-CONFIG_SND_SOC_ES8328=m
-CONFIG_SND_SOC_ES8328_I2C=m
-CONFIG_SND_SOC_ES8328_SPI=m
-CONFIG_SND_SOC_GTM601=m
-CONFIG_SND_SOC_HDA=m
-CONFIG_SND_SOC_INNO_RK3036=m
-CONFIG_SND_SOC_MAX98088=m
-CONFIG_SND_SOC_MAX98357A=m
-CONFIG_SND_SOC_MAX98504=m
-CONFIG_SND_SOC_MAX9867=m
-CONFIG_SND_SOC_MAX98927=m
-CONFIG_SND_SOC_MAX98373=m
-CONFIG_SND_SOC_MAX98373_I2C=m
-CONFIG_SND_SOC_MAX98373_SDW=m
-CONFIG_SND_SOC_MAX98390=m
-CONFIG_SND_SOC_MAX9860=m
-CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
-CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
-CONFIG_SND_SOC_PCM1681=m
-CONFIG_SND_SOC_PCM1789=m
-CONFIG_SND_SOC_PCM1789_I2C=m
-CONFIG_SND_SOC_PCM179X=m
-CONFIG_SND_SOC_PCM179X_I2C=m
-CONFIG_SND_SOC_PCM179X_SPI=m
-CONFIG_SND_SOC_PCM186X=m
-CONFIG_SND_SOC_PCM186X_I2C=m
-CONFIG_SND_SOC_PCM186X_SPI=m
-CONFIG_SND_SOC_PCM3060=m
-CONFIG_SND_SOC_PCM3060_I2C=m
-CONFIG_SND_SOC_PCM3060_SPI=m
-CONFIG_SND_SOC_PCM3168A=m
-CONFIG_SND_SOC_PCM3168A_I2C=m
-CONFIG_SND_SOC_PCM3168A_SPI=m
-CONFIG_SND_SOC_PCM5102A=m
-CONFIG_SND_SOC_PCM512x=m
-CONFIG_SND_SOC_PCM512x_I2C=m
-CONFIG_SND_SOC_PCM512x_SPI=m
-CONFIG_SND_SOC_RK3328=m
-CONFIG_SND_SOC_RK817=m
-CONFIG_SND_SOC_RL6231=m
-CONFIG_SND_SOC_RT1308_SDW=m
-CONFIG_SND_SOC_RT1316_SDW=m
-CONFIG_SND_SOC_RT5616=m
-CONFIG_SND_SOC_RT5631=m
-CONFIG_SND_SOC_RT5640=m
-CONFIG_SND_SOC_RT5659=m
-CONFIG_SND_SOC_RT5645=m
-CONFIG_SND_SOC_RT5682=m
-CONFIG_SND_SOC_RT5682_SDW=m
-CONFIG_SND_SOC_RT700=m
-CONFIG_SND_SOC_RT700_SDW=m
-CONFIG_SND_SOC_RT711=m
-CONFIG_SND_SOC_RT711_SDW=m
-CONFIG_SND_SOC_RT711_SDCA_SDW=m
-CONFIG_SND_SOC_RT715=m
-CONFIG_SND_SOC_RT715_SDW=m
-CONFIG_SND_SOC_RT715_SDCA_SDW=m
-CONFIG_SND_SOC_SGTL5000=m
-CONFIG_SND_SOC_SI476X=m
-CONFIG_SND_SOC_SIGMADSP=m
-CONFIG_SND_SOC_SIGMADSP_I2C=m
-CONFIG_SND_SOC_SIGMADSP_REGMAP=m
-CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
-CONFIG_SND_SOC_SIMPLE_MUX=m
-CONFIG_SND_SOC_SIRF_AUDIO_CODEC=m
-CONFIG_SND_SOC_SPDIF=m
-CONFIG_SND_SOC_SRC4XXX_I2C=m
-CONFIG_SND_SOC_SSM2305=m
-CONFIG_SND_SOC_SSM2518=m
-CONFIG_SND_SOC_SSM2602=m
-CONFIG_SND_SOC_SSM2602_SPI=m
-CONFIG_SND_SOC_SSM2602_I2C=m
-CONFIG_SND_SOC_SSM4567=m
-CONFIG_SND_SOC_STA32X=m
-CONFIG_SND_SOC_STA350=m
-CONFIG_SND_SOC_STI_SAS=m
-CONFIG_SND_SOC_TAS2552=m
-CONFIG_SND_SOC_TAS2562=m
-CONFIG_SND_SOC_TAS2764=m
-CONFIG_SND_SOC_TAS2770=m
-CONFIG_SND_SOC_TAS2780=m
-CONFIG_SND_SOC_WSA883X=m
-CONFIG_SND_SOC_TAS5086=m
-CONFIG_SND_SOC_TAS571X=m
-CONFIG_SND_SOC_TAS5720=m
-CONFIG_SND_SOC_TAS5805M=m
-CONFIG_SND_SOC_TAS6424=m
-CONFIG_SND_SOC_TDA7419=m
-CONFIG_SND_SOC_TFA9879=m
-CONFIG_SND_SOC_TFA989X=m
-CONFIG_SND_SOC_TLV320AIC23=m
-CONFIG_SND_SOC_TLV320AIC23_I2C=m
-CONFIG_SND_SOC_TLV320AIC23_SPI=m
-CONFIG_SND_SOC_TLV320AIC31XX=m
-CONFIG_SND_SOC_TLV320AIC32X4=m
-CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
-CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
-CONFIG_SND_SOC_TLV320AIC3X_I2C=m
-CONFIG_SND_SOC_TLV320AIC3X_SPI=m
-CONFIG_SND_SOC_TLV320AIC3X=m
-CONFIG_SND_SOC_TLV320ADCX140=m
-CONFIG_SND_SOC_TS3A227E=m
-CONFIG_SND_SOC_TSCS42XX=m
-CONFIG_SND_SOC_TSCS454=m
-CONFIG_SND_SOC_UDA1334=m
-CONFIG_SND_SOC_WCD938X_SDW=m
-CONFIG_SND_SOC_WCD9335=m
-CONFIG_SND_SOC_WCD934X=m
-CONFIG_SND_SOC_WCD938X_SDW=m
-CONFIG_SND_SOC_WM8510=m
-CONFIG_SND_SOC_WM8523=m
-CONFIG_SND_SOC_WM8524=m
-CONFIG_SND_SOC_WM8580=m
-CONFIG_SND_SOC_WM8711=m
-CONFIG_SND_SOC_WM8728=m
-CONFIG_SND_SOC_WM8731=m
-CONFIG_SND_SOC_WM8737=m
-CONFIG_SND_SOC_WM8741=m
-CONFIG_SND_SOC_WM8750=m
-CONFIG_SND_SOC_WM8753=m
-CONFIG_SND_SOC_WM8770=m
-CONFIG_SND_SOC_WM8776=m
-CONFIG_SND_SOC_WM8782=m
-CONFIG_SND_SOC_WM8804=m
-CONFIG_SND_SOC_WM8804_I2C=m
-CONFIG_SND_SOC_WM8804_SPI=m
-CONFIG_SND_SOC_WM8903=m
-CONFIG_SND_SOC_WM8904=m
-CONFIG_SND_SOC_WM8960=m
-CONFIG_SND_SOC_WM8962=m
-CONFIG_SND_SOC_WM8974=m
-CONFIG_SND_SOC_WM8978=m
-CONFIG_SND_SOC_WM8985=m
-CONFIG_SND_SOC_WSA881X=m
-CONFIG_SND_SOC_ZL38060=m
-CONFIG_SND_SOC_ZX_AUD96P22=m
-CONFIG_SND_SOC_MAX9759=m
-CONFIG_SND_SOC_MT6351=m
-CONFIG_SND_SOC_MT6358=m
-CONFIG_SND_SOC_MT6660=m
-CONFIG_SND_SOC_NAU8315=m
-CONFIG_SND_SOC_NAU8540=m
-CONFIG_SND_SOC_NAU8810=m
-CONFIG_SND_SOC_NAU8822=m
-CONFIG_SND_SOC_NAU8824=m
-CONFIG_SND_SOC_TPA6130A2=m
-CONFIG_SND_SOC_LPASS_WSA_MACRO=m
-CONFIG_SND_SOC_LPASS_VA_MACRO=m
-CONFIG_SND_SOC_LPASS_RX_MACRO=m
-CONFIG_SND_SOC_LPASS_TX_MACRO=m
-# end of CODEC drivers
-
-CONFIG_SND_SIMPLE_CARD_UTILS=m
-CONFIG_SND_SIMPLE_CARD=m
-CONFIG_SND_AUDIO_GRAPH_CARD=m
-CONFIG_AC97_BUS=m
-
-#
-# HID support
-#
-CONFIG_HID=m
-CONFIG_HID_BATTERY_STRENGTH=y
-CONFIG_HIDRAW=y
-CONFIG_UHID=m
-CONFIG_HID_GENERIC=m
-
-#
-# Special HID drivers
-#
-CONFIG_HID_A4TECH=m
-CONFIG_HID_ACCUTOUCH=m
-CONFIG_HID_ACRUX=m
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=m
-CONFIG_HID_APPLEIR=m
-CONFIG_HID_ASUS=m
-CONFIG_HID_AUREAL=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_BETOP_FF=m
-CONFIG_HID_BIGBEN_FF=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CORSAIR=m
-CONFIG_HID_COUGAR=m
-CONFIG_HID_MACALLY=m
-CONFIG_HID_PRODIKEYS=m
-CONFIG_HID_CMEDIA=m
-CONFIG_HID_CP2112=m
-CONFIG_HID_CREATIVE_SB0540=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_DRAGONRISE=m
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=m
-CONFIG_HID_ELAN=m
-CONFIG_HID_ELECOM=m
-CONFIG_HID_ELO=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_FT260=m
-CONFIG_HID_GEMBIRD=m
-CONFIG_HID_GFRM=m
-CONFIG_HID_GLORIOUS=m
-CONFIG_HID_HOLTEK=m
-CONFIG_HOLTEK_FF=y
-CONFIG_HID_GOOGLE_HAMMER=m
-CONFIG_HID_VIVALDI=m
-CONFIG_HID_GT683R=m
-CONFIG_HID_KEYTOUCH=m
-CONFIG_HID_KYE=m
-CONFIG_HID_UCLOGIC=m
-CONFIG_HID_WALTOP=m
-CONFIG_HID_VIEWSONIC=m
-CONFIG_HID_VRC2=m
-CONFIG_HID_GYRATION=m
-CONFIG_HID_ICADE=m
-CONFIG_HID_ITE=m
-CONFIG_HID_JABRA=m
-CONFIG_HID_TWINHAN=m
-CONFIG_HID_KENSINGTON=m
-CONFIG_HID_LCPOWER=m
-CONFIG_HID_LED=m
-CONFIG_HID_LENOVO=m
-CONFIG_HID_LOGITECH=m
-CONFIG_HID_LOGITECH_DJ=m
-CONFIG_HID_LOGITECH_HIDPP=m
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWHEELS_FF=y
-CONFIG_HID_MAGICMOUSE=m
-CONFIG_HID_MALTRON=m
-CONFIG_HID_MAYFLASH=m
-CONFIG_HID_REDRAGON=m
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_MULTITOUCH=m
-CONFIG_HID_NTI=m
-CONFIG_HID_NTRIG=m
-CONFIG_HID_ORTEK=m
-CONFIG_HID_PANTHERLORD=m
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PENMOUNT=m
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_PICOLCD=m
-CONFIG_HID_PICOLCD_FB=y
-CONFIG_HID_PICOLCD_BACKLIGHT=y
-CONFIG_HID_PICOLCD_LCD=y
-CONFIG_HID_PICOLCD_LEDS=y
-CONFIG_HID_PICOLCD_CIR=y
-CONFIG_HID_PLANTRONICS=m
-CONFIG_HID_PLAYSTATION=m
-CONFIG_HID_PXRC=m
-CONFIG_HID_RAZER=m
-CONFIG_PLAYSTATION_FF=y
-CONFIG_HID_PRIMAX=m
-CONFIG_HID_RETRODE=m
-CONFIG_HID_ROCCAT=m
-CONFIG_HID_SAITEK=m
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SEMITEK=m
-CONFIG_HID_SIGMAMICRO=m
-CONFIG_HID_SONY=m
-CONFIG_SONY_FF=y
-CONFIG_HID_SPEEDLINK=m
-CONFIG_HID_STEAM=m
-CONFIG_HID_STEELSERIES=m
-CONFIG_HID_SUNPLUS=m
-CONFIG_HID_RMI=m
-CONFIG_HID_GREENASIA=m
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=m
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TIVO=m
-CONFIG_HID_TOPSEED=m
-CONFIG_HID_TOPRE=m
-CONFIG_HID_THINGM=m
-CONFIG_HID_THRUSTMASTER=m
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_UDRAW_PS3=m
-CONFIG_HID_U2FZERO=m
-CONFIG_HID_WACOM=m
-CONFIG_HID_WIIMOTE=m
-CONFIG_HID_XINMO=m
-CONFIG_HID_ZEROPLUS=m
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=m
-CONFIG_HID_SENSOR_HUB=m
-CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
-CONFIG_HID_ALPS=m
-CONFIG_HID_MCP2221=m
-# end of Special HID drivers
-
-#
-# USB HID support
-#
-CONFIG_USB_HID=m
-CONFIG_HID_PID=y
-CONFIG_USB_HIDDEV=y
-
-#
-# USB HID Boot Protocol drivers
-#
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
-# end of USB HID Boot Protocol drivers
-# end of USB HID support
-
-#
-# I2C HID support
-#
-CONFIG_I2C_HID=m
-CONFIG_I2C_HID_OF=m
-CONFIG_I2C_HID_OF_ELAN=m
-CONFIG_USB_ONBOARD_HUB=m
-CONFIG_I2C_HID_OF_GOODIX=m
-CONFIG_I2C_HID_ACPI=m
-# end of I2C HID support
-# end of HID support
-
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_LED_TRIG=y
-CONFIG_USB_ULPI_BUS=m
-CONFIG_USB_CONN_GPIO=m
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB=m
-CONFIG_USB_PCI=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEFAULT_PERSIST=y
-CONFIG_USB_FEW_INIT_RETRIES=y
-CONFIG_USB_DYNAMIC_MINORS=y
-CONFIG_USB_OTG=y
-# CONFIG_USB_OTG_PRODUCTLIST is not set
-# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
-CONFIG_USB_OTG_FSM=m
-CONFIG_USB_LEDS_TRIGGER_USBPORT=m
-CONFIG_USB_AUTOSUSPEND_DELAY=2
-CONFIG_USB_MON=m
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_C67X00_HCD=m
-CONFIG_USB_XHCI_HCD=m
-CONFIG_USB_XHCI_DBGCAP=y
-CONFIG_USB_XHCI_PCI=m
-CONFIG_USB_XHCI_PCI_RENESAS=m
-CONFIG_USB_XHCI_PLATFORM=m
-# CONFIG_USB_XHCI_HISTB is not set
-# CONFIG_USB_XHCI_MTK is not set
-# CONFIG_USB_XHCI_MVEBU is not set
-CONFIG_USB_XHCI_RCAR=m
-CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-CONFIG_USB_EHCI_PCI=m
-CONFIG_USB_EHCI_FSL=m
-CONFIG_USB_EHCI_HCD_NPCM7XX=m
-# CONFIG_USB_EHCI_MXC is not set
-CONFIG_USB_EHCI_HCD_OMAP=m
-CONFIG_USB_EHCI_HCD_ORION=m
-CONFIG_USB_EHCI_HCD_SPEAR=m
-# CONFIG_USB_EHCI_HCD_STI is not set
-CONFIG_USB_EHCI_HCD_AT91=m
-# CONFIG_USB_EHCI_TEGRA is not set
-# CONFIG_USB_EHCI_EXYNOS is not set
-# CONFIG_USB_EHCI_MV is not set
-CONFIG_USB_EHCI_HCD_PLATFORM=m
-CONFIG_USB_OXU210HP_HCD=m
-CONFIG_USB_ISP116X_HCD=m
-CONFIG_USB_FOTG210_HCD=m
-CONFIG_USB_MAX3421_HCD=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_OHCI_HCD_SPEAR=m
-# CONFIG_USB_OHCI_HCD_STI is not set
-CONFIG_USB_OHCI_HCD_AT91=m
-CONFIG_USB_OHCI_HCD_OMAP3=m
-CONFIG_USB_OHCI_HCD_PCI=m
-CONFIG_USB_OHCI_HCD_SSB=y
-# CONFIG_USB_OHCI_EXYNOS is not set
-CONFIG_USB_OHCI_HCD_PLATFORM=m
-CONFIG_USB_UHCI_HCD=m
-CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC=y
-CONFIG_USB_UHCI_PLATFORM=y
-CONFIG_USB_UHCI_ASPEED=y
-CONFIG_USB_U132_HCD=m
-CONFIG_USB_SL811_HCD=m
-# CONFIG_USB_SL811_HCD_ISO is not set
-CONFIG_USB_SL811_CS=m
-CONFIG_USB_R8A66597_HCD=m
-# CONFIG_USB_IMX21_HCD is not set
-CONFIG_USB_HCD_BCMA=m
-CONFIG_USB_HCD_SSB=m
-# CONFIG_USB_HCD_TEST_MODE is not set
-# CONFIG_USB_RENESAS_USBHS is not set
-
-#
-# USB Device Class drivers
-#
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_WDM=m
-CONFIG_USB_TMC=m
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-CONFIG_USB_STORAGE_REALTEK=m
-CONFIG_REALTEK_AUTOPM=y
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_ISD200=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_STORAGE_ALAUDA=m
-CONFIG_USB_STORAGE_ONETOUCH=m
-CONFIG_USB_STORAGE_KARMA=m
-CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-CONFIG_USB_STORAGE_ENE_UB6250=m
-CONFIG_USB_UAS=m
-
-#
-# USB Imaging devices
-#
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USBIP_CORE=m
-CONFIG_USBIP_VHCI_HCD=m
-CONFIG_USBIP_VHCI_HC_PORTS=8
-CONFIG_USBIP_VHCI_NR_HCS=1
-CONFIG_USBIP_HOST=m
-CONFIG_USBIP_VUDC=m
-# CONFIG_USBIP_DEBUG is not set
-CONFIG_USB_CDNS_SUPPORT=m
-CONFIG_USB_CDNS3=m
-CONFIG_USB_CDNSP_PCI=m
-CONFIG_USB_CDNSP_GADGET=y
-CONFIG_USB_CDNSP_HOST=y
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_USB_CDNS3_HOST=y
-CONFIG_USB_CDNS3_IMX=m
-# CONFIG_USB_MTU3 is not set
-CONFIG_USB_MUSB_HDRC=m
-# CONFIG_USB_MUSB_HOST is not set
-# CONFIG_USB_MUSB_GADGET is not set
-CONFIG_USB_MUSB_DUAL_ROLE=y
-
-#
-# Platform Glue Layer
-#
-# CONFIG_USB_MUSB_TUSB6010 is not set
-# CONFIG_USB_MUSB_OMAP2PLUS is not set
-# CONFIG_USB_MUSB_AM35X is not set
-# CONFIG_USB_MUSB_DSPS is not set
-# CONFIG_USB_MUSB_UX500 is not set
-# CONFIG_USB_MUSB_MEDIATEK is not set
-
-#
-# MUSB DMA mode
-#
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_DWC3=m
-# CONFIG_USB_DWC3_ULPI is not set
-# CONFIG_USB_DWC3_HOST is not set
-# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_DUAL_ROLE=y
-
-#
-# Platform Glue Driver Support
-#
-CONFIG_USB_DWC3_OMAP=m
-CONFIG_USB_DWC3_EXYNOS=m
-CONFIG_USB_DWC3_HAPS=m
-CONFIG_USB_DWC3_KEYSTONE=m
-CONFIG_USB_DWC3_MESON_G12A=m
-CONFIG_USB_DWC3_OF_SIMPLE=m
-CONFIG_USB_DWC3_ST=m
-CONFIG_USB_DWC3_QCOM=m
-CONFIG_USB_DWC3_IMX8MP=m
-CONFIG_USB_DWC3_XILINX=m
-CONFIG_USB_DWC2=m
-# CONFIG_USB_DWC2_HOST is not set
-
-#
-# Gadget/Dual-role mode requires USB Gadget support to be enabled
-#
-# CONFIG_USB_DWC2_PERIPHERAL is not set
-CONFIG_USB_DWC2_DUAL_ROLE=y
-CONFIG_USB_DWC2_PCI=m
-# CONFIG_USB_DWC2_DEBUG is not set
-# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
-CONFIG_USB_CHIPIDEA=m
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_PCI=m
-CONFIG_USB_CHIPIDEA_MSM=m
-CONFIG_USB_CHIPIDEA_IMX=m
-CONFIG_USB_CHIPIDEA_GENERIC=m
-CONFIG_USB_CHIPIDEA_TEGRA=m
-CONFIG_USB_ISP1760=m
-CONFIG_USB_ISP1760_HCD=y
-CONFIG_USB_ISP1761_UDC=y
-# CONFIG_USB_ISP1760_HOST_ROLE is not set
-# CONFIG_USB_ISP1760_GADGET_ROLE is not set
-CONFIG_USB_ISP1760_DUAL_ROLE=y
-
-#
-# USB port drivers
-#
-CONFIG_USB_USS720=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_SIMPLE=m
-CONFIG_USB_SERIAL_AIRCABLE=m
-CONFIG_USB_SERIAL_ARK3116=m
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_CH341=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CP210X=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_F81232=m
-CONFIG_USB_SERIAL_F8153X=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_IUU=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_METRO=m
-CONFIG_USB_SERIAL_MOS7720=m
-CONFIG_USB_SERIAL_MOS7715_PARPORT=y
-CONFIG_USB_SERIAL_MOS7840=m
-CONFIG_USB_SERIAL_MXUPORT=m
-CONFIG_USB_SERIAL_NAVMAN=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_OTI6858=m
-CONFIG_USB_SERIAL_QCAUX=m
-CONFIG_USB_SERIAL_QUALCOMM=m
-CONFIG_USB_SERIAL_SPCP8X5=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_SAFE_PADDED=y
-CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-CONFIG_USB_SERIAL_SYMBOL=m
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-CONFIG_USB_SERIAL_WWAN=m
-CONFIG_USB_SERIAL_OPTION=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_SERIAL_OPTICON=m
-CONFIG_USB_SERIAL_XSENS_MT=m
-CONFIG_USB_SERIAL_WISHBONE=m
-CONFIG_USB_SERIAL_SSU100=m
-CONFIG_USB_SERIAL_QT2=m
-# CONFIG_USB_SERIAL_UPD78F0730 is not set
-CONFIG_USB_SERIAL_XR=m
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_ADUTUX=m
-CONFIG_USB_SEVSEG=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_CYPRESS_CY7C63=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_IDMOUSE=m
-CONFIG_USB_FTDI_ELAN=m
-CONFIG_USB_APPLEDISPLAY=m
-CONFIG_USB_QCOM_EUD=m
-CONFIG_APPLE_MFI_FASTCHARGE=m
-CONFIG_USB_SISUSBVGA=m
-CONFIG_USB_SISUSBVGA_CON=y
-CONFIG_USB_LD=m
-CONFIG_USB_TRANCEVIBRATOR=m
-CONFIG_USB_IOWARRIOR=m
-CONFIG_USB_TEST=m
-CONFIG_USB_EHSET_TEST_FIXTURE=m
-CONFIG_USB_ISIGHTFW=m
-CONFIG_USB_YUREX=m
-CONFIG_USB_EZUSB_FX2=m
-CONFIG_USB_HUB_USB251XB=m
-CONFIG_USB_HSIC_USB3503=m
-CONFIG_USB_HSIC_USB4604=m
-CONFIG_USB_LINK_LAYER_TEST=m
-CONFIG_USB_CHAOSKEY=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_CXACRU=m
-CONFIG_USB_UEAGLEATM=m
-CONFIG_USB_XUSBATM=m
-
-#
-# USB Physical Layer drivers
-#
-CONFIG_USB_PHY=y
-# CONFIG_AB8500_USB is not set
-# CONFIG_KEYSTONE_USB_PHY is not set
-CONFIG_NOP_USB_XCEIV=m
-CONFIG_AM335X_CONTROL_USB=m
-CONFIG_AM335X_PHY_USB=m
-CONFIG_USB_GPIO_VBUS=m
-CONFIG_TAHVO_USB=m
-CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y
-CONFIG_USB_ISP1301=m
-# CONFIG_USB_MXS_PHY is not set
-CONFIG_USB_TEGRA_PHY=m
-CONFIG_USB_ULPI=y
-CONFIG_USB_ULPI_VIEWPORT=y
-# end of USB Physical Layer drivers
-
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
-CONFIG_U_SERIAL_CONSOLE=y
-
-#
-# USB Peripheral Controller
-#
-# CONFIG_USB_AT91 is not set
-# CONFIG_USB_ATMEL_USBA is not set
-# CONFIG_USB_FSL_USB2 is not set
-CONFIG_USB_FOTG210_UDC=m
-CONFIG_USB_GR_UDC=m
-CONFIG_USB_R8A66597=m
-# CONFIG_USB_RENESAS_USB3 is not set
-CONFIG_USB_PXA27X=m
-CONFIG_USB_MV_UDC=m
-CONFIG_USB_MV_U3D=m
-CONFIG_USB_SNP_CORE=m
-CONFIG_USB_SNP_UDC_PLAT=m
-CONFIG_USB_M66592=m
-CONFIG_USB_BDC_UDC=m
-
-#
-# Platform Support
-#
-CONFIG_USB_BDC_PCI=m
-CONFIG_USB_AMD5536UDC=m
-CONFIG_USB_NET2272=m
-CONFIG_USB_NET2272_DMA=y
-CONFIG_USB_NET2280=m
-CONFIG_USB_GOKU=m
-CONFIG_USB_EG20T=m
-CONFIG_USB_GADGET_XILINX=m
-CONFIG_USB_MAX3420_UDC=m
-# CONFIG_USB_ASPEED_VHUB is not set
-# CONFIG_USB_DUMMY_HCD is not set
-# end of USB Peripheral Controller
-
-CONFIG_USB_LIBCOMPOSITE=m
-CONFIG_USB_F_ACM=m
-CONFIG_USB_F_SS_LB=m
-CONFIG_USB_U_SERIAL=m
-CONFIG_USB_U_ETHER=m
-CONFIG_USB_U_AUDIO=m
-CONFIG_USB_F_SERIAL=m
-CONFIG_USB_F_OBEX=m
-CONFIG_USB_F_NCM=m
-CONFIG_USB_F_ECM=m
-CONFIG_USB_F_PHONET=m
-CONFIG_USB_F_EEM=m
-CONFIG_USB_F_SUBSET=m
-CONFIG_USB_F_RNDIS=m
-CONFIG_USB_F_MASS_STORAGE=m
-CONFIG_USB_F_FS=m
-CONFIG_USB_F_UAC1=m
-CONFIG_USB_F_UAC2=m
-CONFIG_USB_F_UVC=m
-CONFIG_USB_F_MIDI=m
-CONFIG_USB_F_HID=m
-CONFIG_USB_F_PRINTER=m
-CONFIG_USB_F_TCM=m
-CONFIG_USB_CONFIGFS=m
-CONFIG_USB_CONFIGFS_SERIAL=y
-CONFIG_USB_CONFIGFS_ACM=y
-CONFIG_USB_CONFIGFS_OBEX=y
-CONFIG_USB_CONFIGFS_NCM=y
-CONFIG_USB_CONFIGFS_ECM=y
-CONFIG_USB_CONFIGFS_ECM_SUBSET=y
-CONFIG_USB_CONFIGFS_RNDIS=y
-CONFIG_USB_CONFIGFS_EEM=y
-CONFIG_USB_CONFIGFS_PHONET=y
-CONFIG_USB_CONFIGFS_MASS_STORAGE=y
-CONFIG_USB_CONFIGFS_F_LB_SS=y
-CONFIG_USB_CONFIGFS_F_FS=y
-CONFIG_USB_CONFIGFS_F_UAC1=y
-# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
-CONFIG_USB_CONFIGFS_F_UAC2=y
-CONFIG_USB_CONFIGFS_F_MIDI=y
-CONFIG_USB_CONFIGFS_F_HID=y
-CONFIG_USB_CONFIGFS_F_UVC=y
-CONFIG_USB_CONFIGFS_F_PRINTER=y
-CONFIG_USB_CONFIGFS_F_TCM=y
-
-#
-# USB Gadget precomposed configurations
-#
-CONFIG_USB_ZERO=m
-CONFIG_USB_ZERO_HNPTEST=y
-CONFIG_USB_AUDIO=m
-CONFIG_GADGET_UAC1=y
-# CONFIG_GADGET_UAC1_LEGACY is not set
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-CONFIG_USB_ETH_EEM=y
-CONFIG_USB_G_NCM=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FUNCTIONFS=m
-CONFIG_USB_FUNCTIONFS_ETH=y
-CONFIG_USB_FUNCTIONFS_RNDIS=y
-CONFIG_USB_FUNCTIONFS_GENERIC=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_GADGET_TARGET=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_MIDI_GADGET=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_NOKIA=m
-CONFIG_USB_G_ACM_MS=m
-CONFIG_USB_G_MULTI=m
-CONFIG_USB_G_MULTI_RNDIS=y
-CONFIG_USB_G_MULTI_CDC=y
-CONFIG_USB_G_HID=m
-# CONFIG_USB_G_DBGP is not set
-CONFIG_USB_G_WEBCAM=m
-CONFIG_USB_RAW_GADGET=m
-# end of USB Gadget precomposed configurations
-
-CONFIG_TYPEC=m
-CONFIG_TYPEC_TCPM=m
-CONFIG_TYPEC_TCPCI=m
-CONFIG_TYPEC_RT1711H=m
-CONFIG_TYPEC_TCPCI_MT6370=m
-CONFIG_TYPEC_MT6360=m
-CONFIG_TYPEC_TCPCI_MT6370=m
-CONFIG_TYPEC_TCPCI_MAXIM=m
-CONFIG_TYPEC_FUSB302=m
-CONFIG_TYPEC_UCSI=m
-CONFIG_UCSI_CCG=m
-CONFIG_UCSI_ACPI=m
-CONFIG_UCSI_STM32G0=m
-CONFIG_TYPEC_HD3SS3220=m
-CONFIG_TYPEC_TPS6598X=m
-CONFIG_TYPEC_ANX7411=m
-CONFIG_TYPEC_RT1719=m
-CONFIG_TYPEC_STUSB160X=m
-CONFIG_TYPEC_WUSB3801=m
-CONFIG_TYPEC_QCOM_PMIC=m
-CONFIG_TYPEC_WUSB3801=m
-CONFIG_TYPEC_EXTCON=m
-
-#
-# USB Type-C Multiplexer/DeMultiplexer Switch support
-#
-CONFIG_TYPEC_MUX_PI3USB30532=m
-# end of USB Type-C Multiplexer/DeMultiplexer Switch support
-
-#
-# USB Type-C Alternate Mode drivers
-#
-CONFIG_TYPEC_DP_ALTMODE=m
-CONFIG_TYPEC_NVIDIA_ALTMODE=m
-# end of USB Type-C Alternate Mode drivers
-
-CONFIG_USB_ROLE_SWITCH=m
-CONFIG_MMC=m
-CONFIG_PWRSEQ_EMMC=m
-CONFIG_PWRSEQ_SD8787=m
-CONFIG_PWRSEQ_SIMPLE=m
-CONFIG_MMC_BLOCK=m
-CONFIG_MMC_BLOCK_MINORS=8
-CONFIG_SDIO_UART=m
-# CONFIG_MMC_TEST is not set
-CONFIG_MMC_CRYPTO=y
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_ARMMMCI is not set
-CONFIG_MMC_SDHCI=m
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PCI=m
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI_PLTFM=m
-CONFIG_MMC_SDHCI_OF_ARASAN=m
-CONFIG_MMC_SDHCI_OF_ASPEED=m
-CONFIG_MMC_SDHCI_OF_AT91=m
-# CONFIG_MMC_SDHCI_OF_ESDHC is not set
-CONFIG_MMC_SDHCI_OF_DWCMSHC=y
-CONFIG_MMC_SDHCI_CADENCE=m
-# CONFIG_MMC_SDHCI_ESDHC_IMX is not set
-# CONFIG_MMC_SDHCI_TEGRA is not set
-# CONFIG_MMC_SDHCI_S3C is not set
-# CONFIG_MMC_SDHCI_SIRF is not set
-# CONFIG_MMC_SDHCI_PXAV3 is not set
-# CONFIG_MMC_SDHCI_PXAV2 is not set
-# CONFIG_MMC_SDHCI_SPEAR is not set
-CONFIG_MMC_SDHCI_F_SDH30=m
-CONFIG_MMC_SDHCI_MILBEAUT=m
-# CONFIG_MMC_MESON_GX is not set
-# CONFIG_MMC_MESON_MX_SDHC is not set
-# CONFIG_MMC_MESON_MX_SDIO is not set
-# CONFIG_MMC_SDHCI_ST is not set
-# CONFIG_MMC_OMAP is not set
-# CONFIG_MMC_OMAP_HS is not set
-CONFIG_MMC_ALCOR=m
-# CONFIG_MMC_ATMELMCI is not set
-# CONFIG_MMC_SDHCI_MSM is not set
-# CONFIG_MMC_MXC is not set
-CONFIG_MMC_TIFM_SD=m
-# CONFIG_MMC_MVSDIO is not set
-CONFIG_MMC_SPI=m
-CONFIG_MMC_SDRICOH_CS=m
-CONFIG_MMC_TMIO_CORE=m
-CONFIG_MMC_TMIO=m
-# CONFIG_MMC_SDHI is not set
-# CONFIG_MMC_UNIPHIER is not set
-CONFIG_MMC_CB710=m
-CONFIG_MMC_VIA_SDMMC=m
-CONFIG_MMC_DW=m
-CONFIG_MMC_DW_PLTFM=m
-CONFIG_MMC_DW_BLUEFIELD=m
-CONFIG_MMC_DW_EXYNOS=m
-CONFIG_MMC_DW_HI3798CV200=m
-CONFIG_MMC_DW_K3=m
-CONFIG_MMC_DW_PCI=m
-# CONFIG_MMC_DW_ROCKCHIP is not set
-# CONFIG_MMC_DW_ZX is not set
-# CONFIG_MMC_SH_MMCIF is not set
-CONFIG_MMC_VUB300=m
-CONFIG_MMC_USHC=m
-CONFIG_MMC_WMT=m
-CONFIG_MMC_USDHI6ROL0=m
-CONFIG_MMC_REALTEK_PCI=m
-CONFIG_MMC_REALTEK_USB=m
-# CONFIG_MMC_SUNXI is not set
-CONFIG_MMC_CQHCI=m
-CONFIG_MMC_HSQ=m
-# CONFIG_MMC_TOSHIBA_PCI is not set
-CONFIG_MMC_MTK=m
-CONFIG_MMC_SDHCI_XENON=m
-CONFIG_MMC_SDHCI_OMAP=m
-CONFIG_MMC_SDHCI_AM654=m
-# CONFIG_MMC_OWL is not set
-CONFIG_MMC_LITEX=m
-CONFIG_MMC_SDHCI_EXTERNAL_DMA=y
-CONFIG_MEMSTICK=m
-# CONFIG_MEMSTICK_DEBUG is not set
-
-#
-# MemoryStick drivers
-#
-# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
-CONFIG_MSPRO_BLOCK=m
-CONFIG_MS_BLOCK=m
-
-#
-# MemoryStick Host Controller Drivers
-#
-CONFIG_MEMSTICK_TIFM_MS=m
-CONFIG_MEMSTICK_JMICRON_38X=m
-CONFIG_MEMSTICK_R592=m
-CONFIG_MEMSTICK_REALTEK_PCI=m
-CONFIG_MEMSTICK_REALTEK_USB=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_RT4505=m
-CONFIG_LEDS_CLASS_FLASH=m
-CONFIG_LEDS_CLASS_MULTICOLOR=m
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-
-#
-# LED drivers
-#
-CONFIG_LEDS_AAT1290=m
-CONFIG_LEDS_AN30259A=m
-CONFIG_LEDS_AS3645A=m
-CONFIG_LEDS_AW2013=m
-CONFIG_LEDS_BCM6328=m
-CONFIG_LEDS_BCM6358=m
-CONFIG_LEDS_CPCAP=m
-CONFIG_LEDS_CR0014114=m
-CONFIG_LEDS_EL15203000=m
-CONFIG_LEDS_LM3530=m
-CONFIG_LEDS_LM3532=m
-CONFIG_LEDS_LM3533=m
-CONFIG_LEDS_LM3642=m
-CONFIG_LEDS_LM3692X=m
-CONFIG_LEDS_LM3601X=m
-CONFIG_LEDS_MT6323=m
-CONFIG_LEDS_PCA9532=m
-CONFIG_LEDS_PCA9532_GPIO=y
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_LP3944=m
-CONFIG_LEDS_LP3952=m
-CONFIG_LEDS_LP50XX=m
-CONFIG_LEDS_LP55XX_COMMON=m
-CONFIG_LEDS_LP5521=m
-CONFIG_LEDS_LP5523=m
-CONFIG_LEDS_LP5562=m
-CONFIG_LEDS_LP8501=m
-CONFIG_LEDS_LP8860=m
-CONFIG_LEDS_PCA955X=m
-CONFIG_LEDS_PCA955X_GPIO=y
-CONFIG_LEDS_PCA963X=m
-CONFIG_LEDS_WM831X_STATUS=m
-CONFIG_LEDS_DA9052=m
-CONFIG_LEDS_DAC124S085=m
-CONFIG_LEDS_PWM=m
-CONFIG_LEDS_REGULATOR=m
-CONFIG_LEDS_BD2802=m
-CONFIG_LEDS_LT3593=m
-CONFIG_LEDS_MC13783=m
-CONFIG_LEDS_ASIC3=y
-CONFIG_LEDS_TCA6507=m
-CONFIG_LEDS_TLC591XX=m
-CONFIG_LEDS_MAX77650=m
-CONFIG_LEDS_MAX77693=m
-CONFIG_LEDS_LM355x=m
-CONFIG_LEDS_MENF21BMC=m
-CONFIG_LEDS_KTD2692=m
-CONFIG_LEDS_IS31FL319X=m
-CONFIG_LEDS_IS31FL32XX=m
-CONFIG_LEDS_RT8515=m
-
-#
-# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
-#
-CONFIG_LEDS_BLINKM=m
-CONFIG_LEDS_SYSCON=y
-CONFIG_LEDS_PM8058=m
-CONFIG_LEDS_MLXREG=m
-CONFIG_LEDS_USER=m
-CONFIG_LEDS_SPI_BYTE=m
-CONFIG_LEDS_TI_LMU_COMMON=m
-CONFIG_LEDS_BCM63138=m
-CONFIG_LEDS_LM3697=m
-CONFIG_LEDS_LM36274=m
-CONFIG_LEDS_TPS6105X=m
-CONFIG_LEDS_SGM3140=m
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_ONESHOT=m
-CONFIG_LEDS_TRIGGER_DISK=y
-CONFIG_LEDS_TRIGGER_MTD=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_LEDS_TRIGGER_BACKLIGHT=m
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_ACTIVITY=m
-CONFIG_LEDS_TRIGGER_GPIO=m
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-CONFIG_LEDS_TRIGGER_TRANSIENT=m
-CONFIG_LEDS_TRIGGER_CAMERA=m
-CONFIG_LEDS_TRIGGER_PANIC=y
-CONFIG_LEDS_TRIGGER_NETDEV=m
-CONFIG_LEDS_TRIGGER_PATTERN=m
-CONFIG_LEDS_TRIGGER_AUDIO=m
-CONFIG_LEDS_TRIGGER_TTY=m
-CONFIG_LEDS_BLINK=y
-CONFIG_LEDS_BLINK_LGM=m
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_A11Y_BRAILLE_CONSOLE=y
-
-#
-# Speakup console speech
-#
-CONFIG_SPEAKUP=m
-CONFIG_SPEAKUP_SYNTH_ACNTSA=m
-CONFIG_SPEAKUP_SYNTH_APOLLO=m
-CONFIG_SPEAKUP_SYNTH_AUDPTR=m
-CONFIG_SPEAKUP_SYNTH_BNS=m
-CONFIG_SPEAKUP_SYNTH_DECTLK=m
-CONFIG_SPEAKUP_SYNTH_DECEXT=m
-CONFIG_SPEAKUP_SYNTH_LTLK=m
-CONFIG_SPEAKUP_SYNTH_SOFT=m
-CONFIG_SPEAKUP_SYNTH_SPKOUT=m
-CONFIG_SPEAKUP_SYNTH_TXPRT=m
-# CONFIG_SPEAKUP_SYNTH_DUMMY is not set
-# end of Speakup console speech
-
-CONFIG_INFINIBAND=m
-CONFIG_INFINIBAND_USER_MAD=m
-CONFIG_INFINIBAND_USER_ACCESS=m
-CONFIG_INFINIBAND_USER_MEM=y
-CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
-CONFIG_INFINIBAND_ADDR_TRANS=y
-CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
-CONFIG_INFINIBAND_MTHCA=m
-# CONFIG_INFINIBAND_MTHCA_DEBUG is not set
-CONFIG_INFINIBAND_CXGB4=m
-CONFIG_INFINIBAND_IRDMA=m
-CONFIG_INFINIBAND_I40IW=m
-CONFIG_MLX4_INFINIBAND=m
-CONFIG_MLX5_INFINIBAND=m
-CONFIG_INFINIBAND_OCRDMA=m
-CONFIG_INFINIBAND_VMWARE_PVRDMA=m
-CONFIG_RDMA_RXE=m
-CONFIG_RDMA_SIW=m
-CONFIG_INFINIBAND_IPOIB=m
-CONFIG_INFINIBAND_IPOIB_CM=y
-# CONFIG_INFINIBAND_IPOIB_DEBUG is not set
-# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set
-CONFIG_INFINIBAND_SRP=m
-CONFIG_INFINIBAND_SRPT=m
-CONFIG_INFINIBAND_ISER=m
-CONFIG_INFINIBAND_ISERT=m
-CONFIG_INFINIBAND_RTRS=m
-CONFIG_INFINIBAND_RTRS_CLIENT=m
-CONFIG_INFINIBAND_RTRS_SERVER=m
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EDAC=m
-CONFIG_EDAC_LEGACY_SYSFS=y
-# CONFIG_EDAC_DEBUG is not set
-CONFIG_EDAC_AL_MC=m
-# CONFIG_EDAC_HIGHBANK_MC is not set
-# CONFIG_EDAC_HIGHBANK_L2 is not set
-# CONFIG_EDAC_ALTERA is not set
-# CONFIG_EDAC_SYNOPSYS is not set
-CONFIG_EDAC_ASPEED=m
-# CONFIG_EDAC_TI is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-CONFIG_RTC_SYSTOHC=y
-CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-CONFIG_RTC_NVMEM=y
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-CONFIG_RTC_DRV_88PM80X=m
-CONFIG_RTC_DRV_ABB5ZES3=m
-CONFIG_RTC_DRV_ABEOZ9=m
-CONFIG_RTC_DRV_ABX80X=m
-CONFIG_RTC_DRV_DS1307=m
-# CONFIG_RTC_DRV_DS1307_CENTURY is not set
-CONFIG_RTC_DRV_DS1374=m
-CONFIG_RTC_DRV_DS1374_WDT=y
-CONFIG_RTC_DRV_DS1672=m
-# CONFIG_RTC_DRV_HYM8563 is not set
-CONFIG_RTC_DRV_MAX6900=m
-CONFIG_RTC_DRV_MAX8907=m
-# CONFIG_RTC_DRV_MAX77686 is not set
-CONFIG_RTC_DRV_NCT3018Y=m
-CONFIG_RTC_DRV_TI_K3=m
-# CONFIG_RTC_DRV_RK808 is not set
-CONFIG_RTC_DRV_RS5C372=m
-CONFIG_RTC_DRV_ISL1208=m
-CONFIG_RTC_DRV_ISL12022=m
-# CONFIG_RTC_DRV_ISL12026 is not set
-CONFIG_RTC_DRV_X1205=m
-CONFIG_RTC_DRV_PCF8523=m
-CONFIG_RTC_DRV_PCF85063=m
-CONFIG_RTC_DRV_PCF85363=m
-CONFIG_RTC_DRV_PCF8563=m
-CONFIG_RTC_DRV_PCF8583=m
-CONFIG_RTC_DRV_M41T80=m
-CONFIG_RTC_DRV_M41T80_WDT=y
-CONFIG_RTC_DRV_BQ32K=m
-# CONFIG_RTC_DRV_TWL4030 is not set
-# CONFIG_RTC_DRV_RC5T619 is not set
-CONFIG_RTC_DRV_S35390A=m
-CONFIG_RTC_DRV_FM3130=m
-CONFIG_RTC_DRV_RX8010=m
-CONFIG_RTC_DRV_RX8581=m
-CONFIG_RTC_DRV_RX8025=m
-CONFIG_RTC_DRV_EM3027=m
-CONFIG_RTC_DRV_RV3028=m
-CONFIG_RTC_DRV_RV3032=m
-CONFIG_RTC_DRV_RV8803=m
-CONFIG_RTC_DRV_SD3078=m
-
-#
-# SPI RTC drivers
-#
-CONFIG_RTC_DRV_M41T93=m
-CONFIG_RTC_DRV_M41T94=m
-CONFIG_RTC_DRV_DS1302=m
-CONFIG_RTC_DRV_DS1305=m
-CONFIG_RTC_DRV_DS1343=m
-CONFIG_RTC_DRV_DS1347=m
-CONFIG_RTC_DRV_DS1390=m
-CONFIG_RTC_DRV_MAX6916=m
-CONFIG_RTC_DRV_R9701=m
-CONFIG_RTC_DRV_RX4581=m
-CONFIG_RTC_DRV_RX6110=m
-CONFIG_RTC_DRV_RS5C348=m
-CONFIG_RTC_DRV_MAX6902=m
-CONFIG_RTC_DRV_PCF2123=m
-CONFIG_RTC_DRV_MCP795=m
-CONFIG_RTC_I2C_AND_SPI=y
-
-#
-# SPI and I2C RTC drivers
-#
-CONFIG_RTC_DRV_DS3232=m
-CONFIG_RTC_DRV_DS3232_HWMON=y
-CONFIG_RTC_DRV_PCF2127=m
-CONFIG_RTC_DRV_RV3029C2=m
-CONFIG_RTC_DRV_RV3029_HWMON=y
-
-#
-# Platform RTC drivers
-#
-CONFIG_RTC_DRV_CMOS=y
-CONFIG_RTC_DRV_DS1286=m
-CONFIG_RTC_DRV_DS1511=m
-CONFIG_RTC_DRV_DS1553=m
-CONFIG_RTC_DRV_DS1685_FAMILY=m
-CONFIG_RTC_DRV_DS1685=y
-# CONFIG_RTC_DRV_DS1689 is not set
-# CONFIG_RTC_DRV_DS17285 is not set
-# CONFIG_RTC_DRV_DS17485 is not set
-# CONFIG_RTC_DRV_DS17885 is not set
-CONFIG_RTC_DRV_DS1742=m
-CONFIG_RTC_DRV_DS2404=m
-CONFIG_RTC_DRV_DA9052=m
-CONFIG_RTC_DRV_DA9063=m
-CONFIG_RTC_DRV_EFI=m
-CONFIG_RTC_DRV_STK17TA8=m
-CONFIG_RTC_DRV_M48T86=m
-CONFIG_RTC_DRV_M48T35=m
-CONFIG_RTC_DRV_M48T59=m
-CONFIG_RTC_DRV_MSM6242=m
-CONFIG_RTC_DRV_BQ4802=m
-CONFIG_RTC_DRV_RP5C01=m
-CONFIG_RTC_DRV_V3020=m
-CONFIG_RTC_DRV_OPTEE=m
-CONFIG_RTC_DRV_WM831X=m
-CONFIG_RTC_DRV_SPEAR=y
-CONFIG_RTC_DRV_PCF50633=m
-# CONFIG_RTC_DRV_AB8500 is not set
-# CONFIG_RTC_DRV_ZYNQMP is not set
-# CONFIG_RTC_DRV_CROS_EC is not set
-CONFIG_RTC_DRV_NTXEC=m
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_RTC_DRV_DIGICOLOR is not set
-# CONFIG_RTC_DRV_IMXDI is not set
-# CONFIG_RTC_DRV_MESON is not set
-CONFIG_RTC_DRV_MESON_VRTC=m
-# CONFIG_RTC_DRV_OMAP is not set
-CONFIG_HAVE_S3C_RTC=y
-# CONFIG_RTC_DRV_S3C is not set
-# CONFIG_RTC_DRV_SA1100 is not set
-# CONFIG_RTC_DRV_SH is not set
-# CONFIG_RTC_DRV_PL030 is not set
-# CONFIG_RTC_DRV_PL031 is not set
-# CONFIG_RTC_DRV_AT91RM9200 is not set
-# CONFIG_RTC_DRV_AT91SAM9 is not set
-# CONFIG_RTC_DRV_VT8500 is not set
-CONFIG_RTC_DRV_SUN6I=y
-# CONFIG_RTC_DRV_SUNXI is not set
-# CONFIG_RTC_DRV_MV is not set
-# CONFIG_RTC_DRV_ARMADA38X is not set
-# CONFIG_RTC_DRV_CADENCE is not set
-CONFIG_RTC_DRV_FTRTC010=m
-CONFIG_RTC_DRV_PCAP=m
-CONFIG_RTC_DRV_MC13XXX=m
-# CONFIG_RTC_DRV_PM8XXX is not set
-# CONFIG_RTC_DRV_TEGRA is not set
-# CONFIG_RTC_DRV_MXC is not set
-# CONFIG_RTC_DRV_MXC_V2 is not set
-# CONFIG_RTC_DRV_SNVS is not set
-# CONFIG_RTC_DRV_SIRFSOC is not set
-# CONFIG_RTC_DRV_ST_LPC is not set
-# CONFIG_RTC_DRV_MT2712 is not set
-CONFIG_RTC_DRV_MT6397=m
-# CONFIG_RTC_DRV_MT7622 is not set
-# CONFIG_RTC_DRV_R7301 is not set
-# CONFIG_RTC_DRV_STM32 is not set
-# CONFIG_RTC_DRV_CPCAP is not set
-CONFIG_RTC_DRV_RTD119X=y
-# CONFIG_RTC_DRV_ASPEED is not set
-
-#
-# HID Sensor RTC drivers
-#
-CONFIG_RTC_DRV_HID_SENSOR_TIME=m
-CONFIG_RTC_DRV_GOLDFISH=m
-CONFIG_DMADEVICES=y
-# CONFIG_DMADEVICES_DEBUG is not set
-
-#
-# DMA Devices
-#
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DMA_OF=y
-CONFIG_ALTERA_MSGDMA=m
-# CONFIG_AMBA_PL08X is not set
-# CONFIG_AT_HDMAC is not set
-# CONFIG_AT_XDMAC is not set
-# CONFIG_AXI_DMAC is not set
-CONFIG_DMA_SUN4I=y
-# CONFIG_DMA_SUN6I is not set
-# CONFIG_DW_AXI_DMAC is not set
-# CONFIG_FSL_EDMA is not set
-# CONFIG_FSL_QDMA is not set
-# CONFIG_IMX_DMA is not set
-# CONFIG_IMX_SDMA is not set
-# CONFIG_INTEL_IDMA64 is not set
-# CONFIG_K3_DMA is not set
-# CONFIG_MILBEAUT_HDMAC is not set
-# CONFIG_MILBEAUT_XDMAC is not set
-# CONFIG_MMP_PDMA is not set
-# CONFIG_MMP_TDMA is not set
-# CONFIG_MV_XOR is not set
-# CONFIG_MXS_DMA is not set
-CONFIG_MX3_IPU=y
-CONFIG_MX3_IPU_IRQS=4
-# CONFIG_NBPFAXI_DMA is not set
-# CONFIG_OWL_DMA is not set
-CONFIG_PL330_DMA=y
-# CONFIG_PXA_DMA is not set
-CONFIG_PLX_DMA=m
-# CONFIG_SIRF_DMA is not set
-# CONFIG_STE_DMA40 is not set
-# CONFIG_STM32_DMA is not set
-# CONFIG_STM32_MDMA is not set
-# CONFIG_TEGRA20_APB_DMA is not set
-# CONFIG_UNIPHIER_MDMAC is not set
-# CONFIG_UNIPHIER_XDMAC is not set
-# CONFIG_XILINX_DMA is not set
-# CONFIG_XILINX_ZYNQMP_DMA is not set
-CONFIG_XILINX_ZYNQMP_DPDMA=m
-# CONFIG_ZX_DMA is not set
-# CONFIG_MTK_HSDMA is not set
-# CONFIG_MTK_CQDMA is not set
-# CONFIG_QCOM_BAM_DMA is not set
-CONFIG_QCOM_GPI_DMA=m
-CONFIG_QCOM_HIDMA_MGMT=m
-CONFIG_QCOM_HIDMA=m
-CONFIG_DW_DMAC_CORE=y
-CONFIG_DW_DMAC=m
-CONFIG_DW_DMAC_PCI=y
-CONFIG_DW_EDMA=m
-CONFIG_DW_EDMA_PCIE=m
-CONFIG_SF_PDMA=m
-# CONFIG_RCAR_DMAC is not set
-# CONFIG_RENESAS_USB_DMAC is not set
-# CONFIG_TI_CPPI41 is not set
-CONFIG_TI_EDMA=y
-CONFIG_DMA_OMAP=y
-CONFIG_TI_DMA_CROSSBAR=y
-
-#
-# DMA Clients
-#
-CONFIG_ASYNC_TX_DMA=y
-# CONFIG_DMATEST is not set
-
-#
-# DMABUF options
-#
-CONFIG_SYNC_FILE=y
-# CONFIG_SW_SYNC is not set
-# CONFIG_UDMABUF is not set
-# CONFIG_DMABUF_MOVE_NOTIFY is not set
-# CONFIG_DMABUF_DEBUG is not set
-CONFIG_DMABUF_SELFTESTS=m
-# CONFIG_DMABUF_HEAPS is not set
-# end of DMABUF options
-
-CONFIG_AUXDISPLAY=y
-CONFIG_HD44780=m
-CONFIG_KS0108=m
-CONFIG_KS0108_PORT=0x378
-CONFIG_KS0108_DELAY=2
-CONFIG_IMG_ASCII_LCD=m
-# CONFIG_HT16K33 is not set
-CONFIG_LCD2S=m
-# CONFIG_ARM_CHARLCD is not set
-CONFIG_PARPORT_PANEL=m
-CONFIG_PANEL_PARPORT=0
-CONFIG_PANEL_PROFILE=5
-# CONFIG_PANEL_CHANGE_MESSAGE is not set
-# CONFIG_CHARLCD_BL_OFF is not set
-# CONFIG_CHARLCD_BL_ON is not set
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_CFG80211=m
+CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
+CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
+CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CGROUP_MISC=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_RDMA=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_WRITEBACK=y
+CONFIG_CHARGER_ADP5061=m
+CONFIG_CHARGER_AXP20X=m
+CONFIG_CHARGER_BD99954=m
+CONFIG_CHARGER_BQ2415X=m
+CONFIG_CHARGER_BQ24190=m
+CONFIG_CHARGER_BQ24257=m
+CONFIG_CHARGER_BQ24735=m
+CONFIG_CHARGER_BQ2515X=m
+CONFIG_CHARGER_BQ256XX=m
+CONFIG_CHARGER_BQ25890=m
+CONFIG_CHARGER_BQ25980=m
+CONFIG_CHARGER_CROS_PCHG=m
+CONFIG_CHARGER_CROS_USBPD=m
+CONFIG_CHARGER_DA9150=m
+CONFIG_CHARGER_GPIO=m
+CONFIG_CHARGER_ISP1704=m
+CONFIG_CHARGER_LP8727=m
+CONFIG_CHARGER_LT3651=m
+CONFIG_CHARGER_LTC4162L=m
+CONFIG_CHARGER_MANAGER=y
+CONFIG_CHARGER_MAX14577=m
+CONFIG_CHARGER_MAX77693=m
+CONFIG_CHARGER_MAX77705=m
+CONFIG_CHARGER_MAX77976=m
+CONFIG_CHARGER_MAX8903=m
+CONFIG_CHARGER_MP2629=m
+CONFIG_CHARGER_MT6360=m
+CONFIG_CHARGER_MT6370=m
+CONFIG_CHARGER_PCF50633=m
+CONFIG_CHARGER_RK817=m
+CONFIG_CHARGER_RT5033=m
+CONFIG_CHARGER_RT9455=m
+CONFIG_CHARGER_RT9467=m
+CONFIG_CHARGER_RT9471=m
+CONFIG_CHARGER_SBS=m
+CONFIG_CHARGER_SMB347=m
+CONFIG_CHARGER_SURFACE=m
+CONFIG_CHARGER_UCS1002=m
 CONFIG_CHARLCD_BL_FLASH=y
-CONFIG_PANEL=m
 CONFIG_CHARLCD=m
-CONFIG_UIO=m
-CONFIG_UIO_CIF=m
-CONFIG_UIO_PDRV_GENIRQ=m
-CONFIG_UIO_DMEM_GENIRQ=m
-CONFIG_UIO_AEC=m
-CONFIG_UIO_SERCOS3=m
-CONFIG_UIO_PCI_GENERIC=m
-CONFIG_UIO_NETX=m
-CONFIG_UIO_PRUSS=m
-CONFIG_UIO_MF624=m
-CONFIG_UIO_DFL=m
-CONFIG_VFIO_IOMMU_TYPE1=m
-CONFIG_VFIO_VIRQFD=m
-CONFIG_VFIO=m
-# CONFIG_VFIO_NOIOMMU is not set
-CONFIG_VFIO_PCI=m
-CONFIG_MLX5_VFIO_PCI=m
-CONFIG_HISI_ACC_VFIO_PCI=m
-CONFIG_VFIO_PCI_MMAP=y
-CONFIG_VFIO_PCI_INTX=y
-# CONFIG_VFIO_PLATFORM is not set
-CONFIG_VFIO_MDEV=m
-CONFIG_VFIO_MDEV_DEVICE=m
-CONFIG_IRQ_BYPASS_MANAGER=m
-CONFIG_VIRT_DRIVERS=y
-CONFIG_VMGENID=m
-CONFIG_VIRTIO=m
-CONFIG_VIRTIO_MENU=y
-CONFIG_VIRTIO_PCI=m
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_VDPA=m
-CONFIG_VP_VDPA=m
-CONFIG_VIRTIO_BALLOON=m
-CONFIG_VIRTIO_MEM=m
-CONFIG_VIRTIO_INPUT=m
-CONFIG_VIRTIO_MMIO=m
-CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
-CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
-CONFIG_VDPA=m
-CONFIG_IFCVF=m
-CONFIG_MLX5_VDPA=y
-CONFIG_MLX5_VDPA_NET=m
-CONFIG_VHOST_IOTLB=m
-CONFIG_VHOST_RING=m
-CONFIG_VHOST=m
-CONFIG_VHOST_MENU=y
-CONFIG_VHOST_NET=m
-CONFIG_VHOST_SCSI=m
-CONFIG_VHOST_VSOCK=m
-CONFIG_VHOST_VDPA=m
-# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
-
-#
-# Microsoft Hyper-V guest support
-#
-# end of Microsoft Hyper-V guest support
-
-# CONFIG_GREYBUS is not set
-CONFIG_STAGING=y
-CONFIG_PRISM2_USB=m
-CONFIG_COMEDI=m
-CONFIG_COMEDI_TESTS=m
-CONFIG_COMEDI_TESTS_EXAMPLE=m
-CONFIG_COMEDI_TESTS_NI_ROUTES=m
-# CONFIG_COMEDI_DEBUG is not set
-CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
-CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
-CONFIG_COMEDI_MISC_DRIVERS=y
-CONFIG_COMEDI_BOND=m
-CONFIG_COMEDI_TEST=m
-CONFIG_COMEDI_PARPORT=m
-CONFIG_COMEDI_ISA_DRIVERS=y
-CONFIG_COMEDI_PCL711=m
-CONFIG_COMEDI_PCL724=m
-CONFIG_COMEDI_PCL726=m
-CONFIG_COMEDI_PCL730=m
-CONFIG_COMEDI_PCL812=m
-CONFIG_COMEDI_PCL816=m
-CONFIG_COMEDI_PCL818=m
-CONFIG_COMEDI_PCM3724=m
-CONFIG_COMEDI_AMPLC_DIO200_ISA=m
-CONFIG_COMEDI_AMPLC_PC236_ISA=m
-CONFIG_COMEDI_AMPLC_PC263_ISA=m
-CONFIG_COMEDI_RTI800=m
-CONFIG_COMEDI_RTI802=m
-CONFIG_COMEDI_DAC02=m
-CONFIG_COMEDI_DAS16M1=m
-CONFIG_COMEDI_DAS08_ISA=m
-CONFIG_COMEDI_DAS16=m
-CONFIG_COMEDI_DAS800=m
-CONFIG_COMEDI_DAS1800=m
-CONFIG_COMEDI_DAS6402=m
-CONFIG_COMEDI_DT2801=m
-CONFIG_COMEDI_DT2811=m
-CONFIG_COMEDI_DT2814=m
-CONFIG_COMEDI_DT2815=m
-CONFIG_COMEDI_DT2817=m
-CONFIG_COMEDI_DT282X=m
-CONFIG_COMEDI_DMM32AT=m
-CONFIG_COMEDI_FL512=m
-CONFIG_COMEDI_AIO_AIO12_8=m
-CONFIG_COMEDI_AIO_IIRO_16=m
-CONFIG_COMEDI_II_PCI20KC=m
-CONFIG_COMEDI_C6XDIGIO=m
-CONFIG_COMEDI_MPC624=m
-CONFIG_COMEDI_ADQ12B=m
-CONFIG_COMEDI_NI_AT_A2150=m
-CONFIG_COMEDI_NI_AT_AO=m
-CONFIG_COMEDI_NI_ATMIO=m
-CONFIG_COMEDI_NI_ATMIO16D=m
-CONFIG_COMEDI_NI_LABPC_ISA=m
-CONFIG_COMEDI_PCMAD=m
-CONFIG_COMEDI_PCMDA12=m
-CONFIG_COMEDI_PCMMIO=m
-CONFIG_COMEDI_PCMUIO=m
-CONFIG_COMEDI_MULTIQ3=m
-CONFIG_COMEDI_S526=m
-CONFIG_COMEDI_PCI_DRIVERS=m
+CONFIG_CHECK_SIGNATURE=y
+CONFIG_CHR_DEV_SCH=m
+CONFIG_CHR_DEV_SG=m
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHROMEOS_PRIVACY_SCREEN=m
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CICADA_PHY=m
+CONFIG_CLANG_VERSION=0
+CONFIG_CLEANCACHE=y
+CONFIG_CLK_ACTIONS=y
+CONFIG_CLK_BCM_63XX=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLK_IMX8ULP=m
+CONFIG_CLK_IMX93=m
+CONFIG_CLK_IMX95_BLK_CTL=m
+CONFIG_CLK_OWL_S500=y
+CONFIG_CLK_PX30=y
+CONFIG_CLK_RENESAS=y
+CONFIG_CLK_RK3036=y
+CONFIG_CLK_RK312X=y
+CONFIG_CLK_RK3188=y
+CONFIG_CLK_RK322X=y
+CONFIG_CLK_RK3288=y
+CONFIG_CLK_RK3308=y
+CONFIG_CLK_RK3328=y
+CONFIG_CLK_RK3368=y
+CONFIG_CLK_RK3399=y
+CONFIG_CLK_RK3528=y
+CONFIG_CLK_RK3562=y
+CONFIG_CLK_RK3568=m
+CONFIG_CLK_RK3588=y
+CONFIG_CLK_RV110X=y
+CONFIG_CLK_RV1126=y
+CONFIG_CLK_SP810=y
+CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
+CONFIG_CLKSRC_DBX500_PRCMU=y
+CONFIG_CLKSRC_EXYNOS_MCT=y
+CONFIG_CLKSRC_IMX_GPT=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_NOMADIK_MTU=y
+CONFIG_CLKSRC_QCOM=y
+CONFIG_CLKSRC_SAMSUNG_PWM=y
+CONFIG_CLKSRC_ST_LPC=y
+CONFIG_CLKSRC_STM32=y
+CONFIG_CLKSRC_TANGO_XTAL=y
+CONFIG_CLKSRC_TI_32K=y
+CONFIG_CLKSRC_VERSATILE=y
+CONFIG_CLK_SUNXI_CLOCKS=y
+CONFIG_CLK_SUNXI_PRCM_SUN6I=y
+CONFIG_CLK_SUNXI_PRCM_SUN8I=y
+CONFIG_CLK_SUNXI_PRCM_SUN9I=y
+CONFIG_CLK_SUNXI=y
+CONFIG_CLK_TWL=m
+CONFIG_CLK_UNIPHIER=y
+CONFIG_CLK_VEXPRESS_OSC=y
+CONFIG_CLK_X1E80100_CAMCC=m
+CONFIG_CLK_X1E80100_DISPCC=m
+CONFIG_CLK_X1E80100_GPUCC=m
+CONFIG_CLK_X1E80100_TCSRCC=m
+CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CM32181=m
+CONFIG_CM3232=m
+CONFIG_CM3323=m
+CONFIG_CM36651=m
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+CONFIG_CMA_SIZE_MBYTES=0
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+CONFIG_CMA_SYSFS=y
+CONFIG_CMA=y
+CONFIG_CMDLINE=""
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_COMEDI_8254=m
+CONFIG_COMEDI_8255=m
 CONFIG_COMEDI_8255_PCI=m
-CONFIG_COMEDI_ADDI_WATCHDOG=m
+CONFIG_COMEDI_8255_SA=m
 CONFIG_COMEDI_ADDI_APCI_1032=m
 CONFIG_COMEDI_ADDI_APCI_1500=m
 CONFIG_COMEDI_ADDI_APCI_1516=m
@@ -9456,312 +958,136 @@ CONFIG_COMEDI_ADDI_APCI_2200=m
 CONFIG_COMEDI_ADDI_APCI_3120=m
 CONFIG_COMEDI_ADDI_APCI_3501=m
 CONFIG_COMEDI_ADDI_APCI_3XXX=m
-CONFIG_COMEDI_ADL_PCI6208=m
-CONFIG_COMEDI_ADL_PCI7X3X=m
-CONFIG_COMEDI_ADL_PCI8164=m
-CONFIG_COMEDI_ADL_PCI9111=m
-CONFIG_COMEDI_ADL_PCI9118=m
-CONFIG_COMEDI_ADV_PCI1710=m
-CONFIG_COMEDI_ADV_PCI1720=m
-CONFIG_COMEDI_ADV_PCI1723=m
-CONFIG_COMEDI_ADV_PCI1724=m
-CONFIG_COMEDI_ADV_PCI1760=m
-CONFIG_COMEDI_ADV_PCI_DIO=m
-CONFIG_COMEDI_AMPLC_DIO200_PCI=m
-CONFIG_COMEDI_AMPLC_PC236_PCI=m
-CONFIG_COMEDI_AMPLC_PC263_PCI=m
-CONFIG_COMEDI_AMPLC_PCI224=m
-CONFIG_COMEDI_AMPLC_PCI230=m
-CONFIG_COMEDI_CONTEC_PCI_DIO=m
-CONFIG_COMEDI_DAS08_PCI=m
-CONFIG_COMEDI_DT3000=m
-CONFIG_COMEDI_DYNA_PCI10XX=m
-CONFIG_COMEDI_GSC_HPDI=m
-CONFIG_COMEDI_MF6X4=m
-CONFIG_COMEDI_ICP_MULTI=m
-CONFIG_COMEDI_DAQBOARD2000=m
-CONFIG_COMEDI_JR3_PCI=m
-CONFIG_COMEDI_KE_COUNTER=m
-CONFIG_COMEDI_CB_PCIDAS64=m
-CONFIG_COMEDI_CB_PCIDAS=m
-CONFIG_COMEDI_CB_PCIDDA=m
-CONFIG_COMEDI_CB_PCIMDAS=m
-CONFIG_COMEDI_CB_PCIMDDA=m
-CONFIG_COMEDI_ME4000=m
-CONFIG_COMEDI_ME_DAQ=m
-CONFIG_COMEDI_NI_6527=m
-CONFIG_COMEDI_NI_65XX=m
-CONFIG_COMEDI_NI_660X=m
-CONFIG_COMEDI_NI_670X=m
-CONFIG_COMEDI_NI_LABPC_PCI=m
-CONFIG_COMEDI_NI_PCIDIO=m
-CONFIG_COMEDI_NI_PCIMIO=m
-CONFIG_COMEDI_RTD520=m
-CONFIG_COMEDI_S626=m
-CONFIG_COMEDI_MITE=m
-CONFIG_COMEDI_NI_TIOCMD=m
-CONFIG_COMEDI_PCMCIA_DRIVERS=m
-CONFIG_COMEDI_CB_DAS16_CS=m
-CONFIG_COMEDI_DAS08_CS=m
-CONFIG_COMEDI_NI_DAQ_700_CS=m
-CONFIG_COMEDI_NI_DAQ_DIO24_CS=m
-CONFIG_COMEDI_NI_LABPC_CS=m
-CONFIG_COMEDI_NI_MIO_CS=m
-CONFIG_COMEDI_QUATECH_DAQP_CS=m
-CONFIG_COMEDI_USB_DRIVERS=m
-CONFIG_COMEDI_DT9812=m
-CONFIG_COMEDI_NI_USB6501=m
-CONFIG_COMEDI_USBDUX=m
-CONFIG_COMEDI_USBDUXFAST=m
-CONFIG_COMEDI_USBDUXSIGMA=m
-CONFIG_COMEDI_VMK80XX=m
-CONFIG_COMEDI_8254=m
-CONFIG_COMEDI_8255=m
-CONFIG_COMEDI_8255_SA=m
-CONFIG_COMEDI_KCOMEDILIB=m
-CONFIG_COMEDI_AMPLC_DIO200=m
-CONFIG_COMEDI_AMPLC_PC236=m
-CONFIG_COMEDI_DAS08=m
-CONFIG_COMEDI_NI_LABPC=m
-CONFIG_COMEDI_NI_TIO=m
-CONFIG_COMEDI_NI_ROUTING=m
-CONFIG_RTL8192U=m
-CONFIG_RTLLIB=m
-CONFIG_RTLLIB_CRYPTO_CCMP=m
-CONFIG_RTLLIB_CRYPTO_TKIP=m
-CONFIG_RTLLIB_CRYPTO_WEP=m
-CONFIG_RTL8192E=m
-CONFIG_RTL8723BS=m
-CONFIG_R8712U=m
-CONFIG_R8188EU=m
-CONFIG_88EU_AP_MODE=y
-CONFIG_RTS5208=m
-CONFIG_VT6655=m
-CONFIG_VT6656=m
-
-#
-# IIO staging drivers
-#
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16203=m
-CONFIG_ADIS16240=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD7816=m
-CONFIG_AD7280=m
-# end of Analog to digital converters
-
-#
-# Analog digital bi-direction converters
-#
-CONFIG_ADT7316=m
-CONFIG_ADT7316_SPI=m
-CONFIG_ADT7316_I2C=m
-# end of Analog digital bi-direction converters
-
-#
-# Capacitance to digital converters
-#
-CONFIG_AD7150=m
-CONFIG_AD7746=m
-# end of Capacitance to digital converters
-
-#
-# Direct Digital Synthesis
-#
-CONFIG_AD9832=m
-CONFIG_AD9834=m
-# end of Direct Digital Synthesis
-
-#
-# Network Analyzer, Impedance Converters
-#
-CONFIG_AD5933=m
-# end of Network Analyzer, Impedance Converters
-
-#
-# Active energy metering IC
-#
-CONFIG_ADE7854=m
-CONFIG_ADE7854_I2C=m
-CONFIG_ADE7854_SPI=m
-# end of Active energy metering IC
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S1210=m
-# end of Resolver to digital converters
-# end of IIO staging drivers
-
-CONFIG_FB_SM750=m
-# CONFIG_USB_EMXX is not set
-# CONFIG_MFD_NVEC is not set
-CONFIG_STAGING_MEDIA=y
-# CONFIG_VIDEO_HANTRO is not set
-# CONFIG_VIDEO_IMX_MEDIA is not set
-# CONFIG_VIDEO_MESON_VDEC is not set
-# CONFIG_VIDEO_OMAP4 is not set
-# CONFIG_VIDEO_ROCKCHIP_VDEC is not set
-CONFIG_VIDEO_STKWEBCAM=m
-# CONFIG_VIDEO_SUNXI is not set
-# CONFIG_TEGRA_VDE is not set
-CONFIG_VIDEO_ZORAN=m
-CONFIG_VIDEO_ZORAN_DC30=y
-CONFIG_VIDEO_ZORAN_ZR36060=y
-CONFIG_VIDEO_ZORAN_BUZ=y
-CONFIG_VIDEO_ZORAN_DC10=y
-CONFIG_VIDEO_ZORAN_LML33=y
-CONFIG_VIDEO_ZORAN_LML33R10=y
-CONFIG_VIDEO_ZORAN_AVS6EYES=y
-# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set
-
-#
-# Android
-#
-CONFIG_ASHMEM=m
-# CONFIG_ION is not set
-# end of Android
-
-# CONFIG_STAGING_BOARD is not set
-CONFIG_LTE_GDM724X=m
-CONFIG_FIREWIRE_SERIAL=m
-CONFIG_FWTTY_MAX_TOTAL_PORTS=64
-CONFIG_FWTTY_MAX_CARD_PORTS=32
-CONFIG_GS_FPGABOOT=m
-CONFIG_UNISYSSPAR=y
-CONFIG_FB_TFT=m
-CONFIG_FB_TFT_AGM1264K_FL=m
-CONFIG_FB_TFT_BD663474=m
-CONFIG_FB_TFT_HX8340BN=m
-CONFIG_FB_TFT_HX8347D=m
-CONFIG_FB_TFT_HX8353D=m
-CONFIG_FB_TFT_HX8357D=m
-CONFIG_FB_TFT_ILI9163=m
-CONFIG_FB_TFT_ILI9320=m
-CONFIG_FB_TFT_ILI9325=m
-CONFIG_FB_TFT_ILI9340=m
-CONFIG_FB_TFT_ILI9341=m
-CONFIG_FB_TFT_ILI9481=m
-CONFIG_FB_TFT_ILI9486=m
-CONFIG_FB_TFT_PCD8544=m
-CONFIG_FB_TFT_RA8875=m
-CONFIG_FB_TFT_S6D02A1=m
-CONFIG_FB_TFT_S6D1121=m
-CONFIG_FB_TFT_SEPS525=m
-CONFIG_FB_TFT_SH1106=m
-CONFIG_FB_TFT_SSD1289=m
-CONFIG_FB_TFT_SSD1305=m
-CONFIG_FB_TFT_SSD1306=m
-CONFIG_FB_TFT_SSD1331=m
-CONFIG_FB_TFT_SSD1351=m
-# CONFIG_FB_TFT_ST7735R is not set
-CONFIG_FB_TFT_ST7789V=m
-CONFIG_FB_TFT_TINYLCD=m
-CONFIG_FB_TFT_TLS8204=m
-CONFIG_FB_TFT_UC1611=m
-CONFIG_FB_TFT_UC1701=m
-CONFIG_FB_TFT_UPD161704=m
-CONFIG_FB_TFT_WATTEROTT=m
-CONFIG_MOST_COMPONENTS=m
-CONFIG_MOST_NET=m
-CONFIG_MOST_SOUND=m
-CONFIG_MOST_VIDEO=m
-# CONFIG_MOST_DIM2 is not set
-CONFIG_MOST_I2C=m
-CONFIG_KS7010=m
-CONFIG_PI433=m
-
-#
-# Gasket devices
-#
-# end of Gasket devices
-
-# CONFIG_XIL_AXIS_FIFO is not set
-CONFIG_FIELDBUS_DEV=m
-# CONFIG_HMS_ANYBUSS_BUS is not set
-CONFIG_KPC2000=y
-CONFIG_KPC2000_CORE=m
-CONFIG_KPC2000_SPI=m
-CONFIG_KPC2000_I2C=m
-CONFIG_KPC2000_DMA=m
-CONFIG_QLGE=m
-CONFIG_WFX=m
-CONFIG_RTL8723CS=m
-CONFIG_SPMI_HISI3670=m
-CONFIG_MFD_HI6421_SPMI=m
-CONFIG_RTL8723CS=m
-CONFIG_REGULATOR_HI6421V600=m
-# CONFIG_GOLDFISH is not set
-CONFIG_CHROME_PLATFORMS=y
-CONFIG_CROS_EC=m
-CONFIG_CROS_EC_I2C=m
-# CONFIG_CROS_EC_RPMSG is not set
-CONFIG_CROS_EC_SPI=m
-CONFIG_CROS_EC_PROTO=y
-CONFIG_CROS_EC_CHARDEV=m
-CONFIG_CROS_EC_LIGHTBAR=m
-CONFIG_CROS_EC_VBC=m
-CONFIG_CROS_EC_DEBUGFS=m
-CONFIG_CROS_EC_SENSORHUB=m
-CONFIG_CROS_EC_SYSFS=m
-CONFIG_CROS_EC_TYPEC=m
-CONFIG_CROS_USBPD_LOGGER=m
-CONFIG_CROS_USBPD_NOTIFY=m
-CONFIG_CHROMEOS_PRIVACY_SCREEN=m
-CONFIG_CROS_TYPEC_SWITCH=m
-# CONFIG_MELLANOX_PLATFORM is not set
-CONFIG_MLXREG_HOTPLUG=m
-CONFIG_MLXREG_IO=m
-# CONFIG_OLPC_XO175 is not set
-CONFIG_HAVE_CLK=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_WM831X=m
-CONFIG_LMK04832=m
+CONFIG_COMEDI_ADDI_WATCHDOG=m
+CONFIG_COMEDI_ADL_PCI6208=m
+CONFIG_COMEDI_ADL_PCI7250=m
+CONFIG_COMEDI_ADL_PCI7X3X=m
+CONFIG_COMEDI_ADL_PCI8164=m
+CONFIG_COMEDI_ADL_PCI9111=m
+CONFIG_COMEDI_ADL_PCI9118=m
+CONFIG_COMEDI_ADQ12B=m
+CONFIG_COMEDI_ADV_PCI1710=m
+CONFIG_COMEDI_ADV_PCI1720=m
+CONFIG_COMEDI_ADV_PCI1723=m
+CONFIG_COMEDI_ADV_PCI1724=m
+CONFIG_COMEDI_ADV_PCI1760=m
+CONFIG_COMEDI_ADV_PCI_DIO=m
+CONFIG_COMEDI_AIO_AIO12_8=m
+CONFIG_COMEDI_AIO_IIRO_16=m
+CONFIG_COMEDI_AMPLC_DIO200_ISA=m
+CONFIG_COMEDI_AMPLC_DIO200=m
+CONFIG_COMEDI_AMPLC_DIO200_PCI=m
+CONFIG_COMEDI_AMPLC_PC236_ISA=m
+CONFIG_COMEDI_AMPLC_PC236=m
+CONFIG_COMEDI_AMPLC_PC236_PCI=m
+CONFIG_COMEDI_AMPLC_PC263_ISA=m
+CONFIG_COMEDI_AMPLC_PC263_PCI=m
+CONFIG_COMEDI_AMPLC_PCI224=m
+CONFIG_COMEDI_AMPLC_PCI230=m
+CONFIG_COMEDI_BOND=m
+CONFIG_COMEDI_C6XDIGIO=m
+CONFIG_COMEDI_CB_DAS16_CS=m
+CONFIG_COMEDI_CB_PCIDAS64=m
+CONFIG_COMEDI_CB_PCIDAS=m
+CONFIG_COMEDI_CB_PCIDDA=m
+CONFIG_COMEDI_CB_PCIMDAS=m
+CONFIG_COMEDI_CB_PCIMDDA=m
+CONFIG_COMEDI_CONTEC_PCI_DIO=m
+CONFIG_COMEDI_DAC02=m
+CONFIG_COMEDI_DAQBOARD2000=m
+CONFIG_COMEDI_DAS08_CS=m
+CONFIG_COMEDI_DAS08_ISA=m
+CONFIG_COMEDI_DAS08=m
+CONFIG_COMEDI_DAS08_PCI=m
+CONFIG_COMEDI_DAS16=m
+CONFIG_COMEDI_DAS16M1=m
+CONFIG_COMEDI_DAS1800=m
+CONFIG_COMEDI_DAS6402=m
+CONFIG_COMEDI_DAS800=m
+CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
+CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
+CONFIG_COMEDI_DMM32AT=m
+CONFIG_COMEDI_DT2801=m
+CONFIG_COMEDI_DT2811=m
+CONFIG_COMEDI_DT2814=m
+CONFIG_COMEDI_DT2815=m
+CONFIG_COMEDI_DT2817=m
+CONFIG_COMEDI_DT282X=m
+CONFIG_COMEDI_DT3000=m
+CONFIG_COMEDI_DT9812=m
+CONFIG_COMEDI_DYNA_PCI10XX=m
+CONFIG_COMEDI_FL512=m
+CONFIG_COMEDI_GSC_HPDI=m
+CONFIG_COMEDI_ICP_MULTI=m
+CONFIG_COMEDI_II_PCI20KC=m
+CONFIG_COMEDI_ISA_DRIVERS=y
+CONFIG_COMEDI_JR3_PCI=m
+CONFIG_COMEDI_KCOMEDILIB=m
+CONFIG_COMEDI_KE_COUNTER=m
+CONFIG_COMEDI=m
+CONFIG_COMEDI_ME4000=m
+CONFIG_COMEDI_ME_DAQ=m
+CONFIG_COMEDI_MF6X4=m
+CONFIG_COMEDI_MISC_DRIVERS=y
+CONFIG_COMEDI_MITE=m
+CONFIG_COMEDI_MPC624=m
+CONFIG_COMEDI_MULTIQ3=m
+CONFIG_COMEDI_NI_6527=m
+CONFIG_COMEDI_NI_65XX=m
+CONFIG_COMEDI_NI_660X=m
+CONFIG_COMEDI_NI_670X=m
+CONFIG_COMEDI_NI_AT_A2150=m
+CONFIG_COMEDI_NI_AT_AO=m
+CONFIG_COMEDI_NI_ATMIO16D=m
+CONFIG_COMEDI_NI_ATMIO=m
+CONFIG_COMEDI_NI_DAQ_700_CS=m
+CONFIG_COMEDI_NI_DAQ_DIO24_CS=m
+CONFIG_COMEDI_NI_LABPC_CS=m
+CONFIG_COMEDI_NI_LABPC_ISA=m
+CONFIG_COMEDI_NI_LABPC=m
+CONFIG_COMEDI_NI_LABPC_PCI=m
+CONFIG_COMEDI_NI_MIO_CS=m
+CONFIG_COMEDI_NI_PCIDIO=m
+CONFIG_COMEDI_NI_PCIMIO=m
+CONFIG_COMEDI_NI_ROUTING=m
+CONFIG_COMEDI_NI_TIOCMD=m
+CONFIG_COMEDI_NI_TIO=m
+CONFIG_COMEDI_NI_USB6501=m
+CONFIG_COMEDI_PARPORT=m
+CONFIG_COMEDI_PCI_DRIVERS=m
+CONFIG_COMEDI_PCL711=m
+CONFIG_COMEDI_PCL724=m
+CONFIG_COMEDI_PCL726=m
+CONFIG_COMEDI_PCL730=m
+CONFIG_COMEDI_PCL812=m
+CONFIG_COMEDI_PCL816=m
+CONFIG_COMEDI_PCL818=m
+CONFIG_COMEDI_PCM3724=m
+CONFIG_COMEDI_PCMAD=m
+CONFIG_COMEDI_PCMCIA_DRIVERS=m
+CONFIG_COMEDI_PCMDA12=m
+CONFIG_COMEDI_PCMMIO=m
+CONFIG_COMEDI_PCMUIO=m
+CONFIG_COMEDI_QUATECH_DAQP_CS=m
+CONFIG_COMEDI_RTD520=m
+CONFIG_COMEDI_RTI800=m
+CONFIG_COMEDI_RTI802=m
+CONFIG_COMEDI_S526=m
+CONFIG_COMEDI_S626=m
+CONFIG_COMEDI_TEST=m
+CONFIG_COMEDI_TESTS_EXAMPLE=m
+CONFIG_COMEDI_TESTS=m
+CONFIG_COMEDI_TESTS_NI_ROUTES=m
+CONFIG_COMEDI_USB_DRIVERS=m
+CONFIG_COMEDI_USBDUXFAST=m
+CONFIG_COMEDI_USBDUX=m
+CONFIG_COMEDI_USBDUXSIGMA=m
+CONFIG_COMEDI_VMK80XX=m
 CONFIG_COMMON_CLK_APPLE_NCO=m
-
-#
-# Clock driver for ARM Reference designs
-#
-CONFIG_ICST=y
-CONFIG_CLK_SP810=y
-CONFIG_CLK_VEXPRESS_OSC=y
-# end of Clock driver for ARM Reference designs
-
-# CONFIG_COMMON_CLK_MAX77686 is not set
-CONFIG_COMMON_CLK_MAX9485=m
-# CONFIG_COMMON_CLK_RK808 is not set
-# CONFIG_COMMON_CLK_SCMI is not set
-# CONFIG_COMMON_CLK_SCPI is not set
-CONFIG_COMMON_CLK_SI5341=m
-CONFIG_COMMON_CLK_SI5351=m
-# CONFIG_COMMON_CLK_SI514 is not set
-CONFIG_COMMON_CLK_SI544=m
-# CONFIG_COMMON_CLK_SI570 is not set
+CONFIG_COMMON_CLK_ASPEED=y
+CONFIG_COMMON_CLK_AT91=y
 CONFIG_COMMON_CLK_CDCE706=m
-CONFIG_COMMON_CLK_TPS68470=m
-# CONFIG_COMMON_CLK_CDCE925 is not set
 CONFIG_COMMON_CLK_CS2000_CP=m
-CONFIG_COMMON_CLK_ASPEED=y
-# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
-# CONFIG_CLK_QORIQ is not set
-CONFIG_COMMON_CLK_PWM=m
-CONFIG_COMMON_CLK_RS9_PCIE=m
-# CONFIG_COMMON_CLK_VC5 is not set
-CONFIG_COMMON_CLK_VC7=m
-CONFIG_COMMON_CLK_STM32MP157_SCMI=y
-CONFIG_COMMON_CLK_STM32MP157=y
-# CONFIG_COMMON_CLK_FIXED_MMIO is not set
-CONFIG_CLK_ACTIONS=y
-CONFIG_CLK_OWL_S500=y
 CONFIG_COMMON_CLK_HI3516CV300=y
 CONFIG_COMMON_CLK_HI3519=y
 CONFIG_COMMON_CLK_HI3559A=y
@@ -9769,2890 +1095,6321 @@ CONFIG_COMMON_CLK_HI3660=y
 CONFIG_COMMON_CLK_HI3670=y
 CONFIG_COMMON_CLK_HI3798CV200=y
 CONFIG_COMMON_CLK_HI6220=y
-CONFIG_RESET_HISI=y
-CONFIG_STUB_CLK_HI6220=y
-CONFIG_STUB_CLK_HI3660=y
-CONFIG_MXC_CLK=y
-# CONFIG_CLK_IMX8MM is not set
-# CONFIG_CLK_IMX8MN is not set
-# CONFIG_CLK_IMX8MP is not set
-# CONFIG_CLK_IMX8MQ is not set
 CONFIG_COMMON_CLK_KEYSTONE=y
-CONFIG_TI_SYSCON_CLK=y
-CONFIG_MSTAR_MSC313_MPLL=y
-
-#
-# Clock driver for MediaTek SoC
-#
+CONFIG_COMMON_CLK_LAN966X=y
+CONFIG_COMMON_CLK_MAX9485=m
+CONFIG_COMMON_CLK_MEDIATEK_FHCTL=y
 CONFIG_COMMON_CLK_MEDIATEK=y
+CONFIG_COMMON_CLK_MESON8B=y
+CONFIG_COMMON_CLK_MESON_MPLL=y
+CONFIG_COMMON_CLK_MESON_PLL=y
+CONFIG_COMMON_CLK_MESON_REGMAP=y
 CONFIG_COMMON_CLK_MT2701=y
-# CONFIG_COMMON_CLK_MT2701_MMSYS is not set
-# CONFIG_COMMON_CLK_MT2701_IMGSYS is not set
-# CONFIG_COMMON_CLK_MT2701_VDECSYS is not set
-# CONFIG_COMMON_CLK_MT2701_HIFSYS is not set
-# CONFIG_COMMON_CLK_MT2701_ETHSYS is not set
-# CONFIG_COMMON_CLK_MT2701_BDPSYS is not set
-# CONFIG_COMMON_CLK_MT2701_AUDSYS is not set
-# CONFIG_COMMON_CLK_MT2701_G3DSYS is not set
 CONFIG_COMMON_CLK_MT6795=m
 CONFIG_COMMON_CLK_MT6795_MFGCFG=m
 CONFIG_COMMON_CLK_MT6795_MMSYS=m
 CONFIG_COMMON_CLK_MT6795_VDECSYS=m
 CONFIG_COMMON_CLK_MT6795_VENCSYS=m
 CONFIG_COMMON_CLK_MT7622=y
-# CONFIG_COMMON_CLK_MT7622_ETHSYS is not set
-# CONFIG_COMMON_CLK_MT7622_HIFSYS is not set
-# CONFIG_COMMON_CLK_MT7622_AUDSYS is not set
 CONFIG_COMMON_CLK_MT7629=y
-# CONFIG_COMMON_CLK_MT7629_ETHSYS is not set
-# CONFIG_COMMON_CLK_MT7629_HIFSYS is not set
+CONFIG_COMMON_CLK_MT7981_ETHSYS=m
+CONFIG_COMMON_CLK_MT7981=y
+CONFIG_COMMON_CLK_MT7986_ETHSYS=y
+CONFIG_COMMON_CLK_MT7986=y
+CONFIG_COMMON_CLK_MT7988=m
 CONFIG_COMMON_CLK_MT8135=y
-CONFIG_COMMON_CLK_MT8173=y
+CONFIG_COMMON_CLK_MT8173_IMGSYS=m
 CONFIG_COMMON_CLK_MT8173_MMSYS=y
-CONFIG_COMMON_CLK_MT8365=m
+CONFIG_COMMON_CLK_MT8173_VDECSYS=m
+CONFIG_COMMON_CLK_MT8173_VENCSYS=m
+CONFIG_COMMON_CLK_MT8173=y
 CONFIG_COMMON_CLK_MT8365_APU=m
 CONFIG_COMMON_CLK_MT8365_CAM=m
+CONFIG_COMMON_CLK_MT8365=m
 CONFIG_COMMON_CLK_MT8365_MFG=m
 CONFIG_COMMON_CLK_MT8365_MMSYS=m
 CONFIG_COMMON_CLK_MT8365_VDEC=m
 CONFIG_COMMON_CLK_MT8365_VENC=m
 CONFIG_COMMON_CLK_MT8516=y
-# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set
-# end of Clock driver for MediaTek SoC
-
-#
-# Clock support for Amlogic platforms
-#
-CONFIG_COMMON_CLK_MESON_REGMAP=y
-CONFIG_COMMON_CLK_MESON_MPLL=y
-CONFIG_COMMON_CLK_MESON_PLL=y
-CONFIG_COMMON_CLK_MESON8B=y
-# end of Clock support for Amlogic platforms
-
-# CONFIG_COMMON_CLK_QCOM is not set
-CONFIG_CLK_RENESAS=y
-# CONFIG_CLK_R9A06G032 is not set
-# CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set
+CONFIG_COMMON_CLK_PWM=m
+CONFIG_COMMON_CLK_PXA1908=y
 CONFIG_COMMON_CLK_ROCKCHIP=y
-CONFIG_CLK_PX30=y
-CONFIG_CLK_RV110X=y
-CONFIG_CLK_RV1126=y
-CONFIG_CLK_RK3036=y
-CONFIG_CLK_RK312X=y
-CONFIG_CLK_RK3188=y
-CONFIG_CLK_RK322X=y
-CONFIG_CLK_RK3288=y
-CONFIG_CLK_RK3308=y
-CONFIG_CLK_RK3328=y
-CONFIG_CLK_RK3368=y
-CONFIG_CLK_RK3399=y
-CONFIG_CLK_RK3568=m
+CONFIG_COMMON_CLK_RP1=m
+CONFIG_COMMON_CLK_RS9_PCIE=m
 CONFIG_COMMON_CLK_SAMSUNG=y
-CONFIG_EXYNOS_AUDSS_CLK_CON=y
-CONFIG_EXYNOS_CLKOUT=m
-CONFIG_CLK_SUNXI=y
-CONFIG_CLK_SUNXI_CLOCKS=y
-CONFIG_CLK_SUNXI_PRCM_SUN6I=y
-CONFIG_CLK_SUNXI_PRCM_SUN8I=y
-CONFIG_CLK_SUNXI_PRCM_SUN9I=y
-CONFIG_SUNXI_CCU=y
-CONFIG_SUN4I_A10_CCU=y
-CONFIG_SUN5I_CCU=y
-CONFIG_SUN6I_A31_CCU=y
-CONFIG_SUN6I_RTC_CCU=m
-CONFIG_SUN8I_A23_CCU=y
-CONFIG_SUN8I_A33_CCU=y
-CONFIG_SUN8I_A83T_CCU=y
-CONFIG_SUN8I_H3_CCU=y
-CONFIG_SUN8I_V3S_CCU=y
-CONFIG_SUN8I_DE2_CCU=y
-CONFIG_SUN8I_R40_CCU=y
-CONFIG_SUN9I_A80_CCU=y
-CONFIG_SUN8I_R_CCU=y
+CONFIG_COMMON_CLK_SI521XX=m
+CONFIG_COMMON_CLK_SI5341=m
+CONFIG_COMMON_CLK_SI5351=m
+CONFIG_COMMON_CLK_SI544=m
+CONFIG_COMMON_CLK_SP7021=m
+CONFIG_COMMON_CLK_STM32MP135=y
+CONFIG_COMMON_CLK_STM32MP157_SCMI=y
+CONFIG_COMMON_CLK_STM32MP157=y
+CONFIG_COMMON_CLK_STM32MP215=y
+CONFIG_COMMON_CLK_STM32MP=y
 CONFIG_COMMON_CLK_TI_ADPLL=y
-CONFIG_CLK_UNIPHIER=y
+CONFIG_COMMON_CLK_TPS68470=m
+CONFIG_COMMON_CLK_VC3=m
+CONFIG_COMMON_CLK_VC7=m
 CONFIG_COMMON_CLK_VISCONTI=y
-CONFIG_HWSPINLOCK=y
-# CONFIG_HWSPINLOCK_OMAP is not set
-# CONFIG_HWSPINLOCK_QCOM is not set
-# CONFIG_HWSPINLOCK_SIRF is not set
-# CONFIG_HWSPINLOCK_STM32 is not set
-CONFIG_HWSPINLOCK_SUN6I=m
-# CONFIG_HSEM_U8500 is not set
-
-#
-# Clock Source drivers
-#
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_CLKSRC_MMIO=y
+CONFIG_COMMON_CLK_WM831X=m
+CONFIG_COMMON_CLK_XLNX_CLKWZRD=m
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_RESET_HI3660=y
+CONFIG_COMMON_RESET_HI6220=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONNECTOR=m
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CORDIC=m
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CORTINA_PHY=m
+CONFIG_COUNTER=m
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_BPREDICT_DISABLE=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_ENDIAN_BE8=y
+CONFIG_CPU_EXYNOS4210=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPUFREQ_DT=m
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_ICACHE_DISABLE=y
+CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_S5PV210=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRC16=m
+CONFIG_CRC4=m
+CONFIG_CRC64=m
+CONFIG_CRC64_ROCKSOFT=m
+CONFIG_CRC7=m
+CONFIG_CRC8=m
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CROS_EC_CHARDEV=m
+CONFIG_CROS_EC_DEBUGFS=m
+CONFIG_CROS_EC_I2C=m
+CONFIG_CROS_EC_LIGHTBAR=m
+CONFIG_CROS_EC=m
+CONFIG_CROS_EC_MKBP_PROXIMITY=m
+CONFIG_CROS_EC_PROTO=y
+CONFIG_CROS_EC_SENSORHUB=m
+CONFIG_CROS_EC_SPI=m
+CONFIG_CROS_EC_SYSFS=m
+CONFIG_CROS_EC_TYPEC=m
+CONFIG_CROS_EC_UART=m
+CONFIG_CROS_EC_UCSI=m
+CONFIG_CROS_EC_VBC=m
+CONFIG_CROS_EC_WATCHDOG=m
+CONFIG_CROS_HPS_I2C=m
+CONFIG_CROS_KBD_LED_BACKLIGHT=m
+CONFIG_CROS_TYPEC_SWITCH=m
+CONFIG_CROS_USBPD_LOGGER=m
+CONFIG_CROS_USBPD_NOTIFY=m
+CONFIG_CRYPTO_842=y
+CONFIG_CRYPTO_ADIANTUM=m
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEGIS128=m
+CONFIG_CRYPTO_AEGIS128_SIMD=y
+CONFIG_CRYPTO_AES_ARM_BS=m
+CONFIG_CRYPTO_AES_ARM_CE=m
+CONFIG_CRYPTO_AES_ARM=m
+CONFIG_CRYPTO_AES_TI=m
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
+CONFIG_CRYPTO_ARIA=m
+CONFIG_CRYPTO_BLAKE2B=m
+CONFIG_CRYPTO_BLAKE2B_NEON=m
+CONFIG_CRYPTO_BLAKE2S_ARM=m
+CONFIG_CRYPTO_BLAKE2S=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_CAST_COMMON=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CFB=m
+CONFIG_CRYPTO_CHACHA20=m
+CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_CRYPTO_CHACHA20POLY1305=m
+CONFIG_CRYPTO_CMAC=m
+CONFIG_CRYPTO_CRC32_ARM_CE=m
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CRC32=m
+CONFIG_CRYPTO_CRCT10DIF_ARM_CE=m
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_CURVE25519=m
+CONFIG_CRYPTO_CURVE25519_NEON=m
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_ALLWINNER=y
+CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
+CONFIG_CRYPTO_DEV_ASPEED_ACRY=y
+CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO=y
+CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH=y
+CONFIG_CRYPTO_DEV_ASPEED=m
+CONFIG_CRYPTO_DEV_ATMEL_ECC=m
+CONFIG_CRYPTO_DEV_ATMEL_I2C=m
+CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
+CONFIG_CRYPTO_DEV_CHELSIO=m
+CONFIG_CRYPTO_DEV_HISTB_TRNG=m
+CONFIG_CRYPTO_DEV_QAT_420XX=m
+CONFIG_CRYPTO_DEV_QAT_4XXX=m
+CONFIG_CRYPTO_DEV_QAT_C3XXX=m
+CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
+CONFIG_CRYPTO_DEV_QAT_C62X=m
+CONFIG_CRYPTO_DEV_QAT_C62XVF=m
+CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
+CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
+CONFIG_CRYPTO_DEV_SAFEXCEL=m
+CONFIG_CRYPTO_DEV_VIRTIO=m
+CONFIG_CRYPTO_DH=m
+CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
+CONFIG_CRYPTO_DRBG_CTR=y
+CONFIG_CRYPTO_DRBG_HASH=y
+CONFIG_CRYPTO_DRBG=m
+CONFIG_CRYPTO_DRBG_MENU=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECC=m
+CONFIG_CRYPTO_ECDH=m
+CONFIG_CRYPTO_ECDSA=m
+CONFIG_CRYPTO_ECHAINIV=m
+CONFIG_CRYPTO_ECRDSA=m
+CONFIG_CRYPTO_ENGINE=m
+CONFIG_CRYPTO_ESSIV=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_GHASH_ARM_CE=m
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HCTR2=m
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY=m
+CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE=y
+CONFIG_CRYPTO_KEYWRAP=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_KPP=m
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_BLAKE2S=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=m
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_LZ4HC=y
+CONFIG_CRYPTO_LZ4=y
+CONFIG_CRYPTO_LZO=m
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_NHPOLY1305=m
+CONFIG_CRYPTO_NHPOLY1305_NEON=m
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_OFB=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_PCRYPT=m
+CONFIG_CRYPTO_POLY1305_ARM=m
+CONFIG_CRYPTO_POLY1305=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_RNG_DEFAULT=m
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_SHA1_ARM_CE=m
+CONFIG_CRYPTO_SHA1_ARM=m
+CONFIG_CRYPTO_SHA1_ARM_NEON=m
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256_ARM=m
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA2_ARM_CE=m
+CONFIG_CRYPTO_SHA3=m
+CONFIG_CRYPTO_SHA512_ARM=m
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SIMD=m
+CONFIG_CRYPTO_SM2=m
+CONFIG_CRYPTO_SM3_GENERIC=m
+CONFIG_CRYPTO_SM3=m
+CONFIG_CRYPTO_SM4_GENERIC=m
+CONFIG_CRYPTO_SM4=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_USER_API_AEAD=m
+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API=m
+CONFIG_CRYPTO_USER_API_RNG=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_XXHASH=m
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CS89x0_PLATFORM=m
+CONFIG_CW1200=m
+CONFIG_CW1200_WLAN_SDIO=m
+CONFIG_CW1200_WLAN_SPI=m
+CONFIG_CXD2880_SPI_DRV=m
+CONFIG_CXL_ACPI=m
+CONFIG_CXL_BUS=m
+CONFIG_CXL_FEATURES=y
+CONFIG_CXL_MEM=m
+CONFIG_CXL_MEM_RAW_COMMANDS=y
+CONFIG_CXL_PCI=m
+CONFIG_CXL_PMEM=m
+CONFIG_CXL_PMU=m
+CONFIG_CXL_REGION=y
+CONFIG_CYCLADES=m
+CONFIG_CYPRESS_FIRMWARE=m
+CONFIG_CYZ_INTR=y
+CONFIG_DA280=m
+CONFIG_DA311=m
+CONFIG_DA9052_WATCHDOG=m
+CONFIG_DA9062_THERMAL=m
+CONFIG_DA9062_WATCHDOG=m
+CONFIG_DA9063_WATCHDOG=m
+CONFIG_DA9150_GPADC=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_DAX=y
+CONFIG_DB500_WATCHDOG=m
+CONFIG_DB8500_THERMAL=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_WX=y
+CONFIG_DEFAULT_HOSTNAME="omv"
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEV_COREDUMP=y
+CONFIG_DEVFREQ_GOV_PASSIVE=m
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_DEVTMPFS_SAFE=y
+CONFIG_DHT11=m
 CONFIG_DIGICOLOR_TIMER=y
-CONFIG_DW_APB_TIMER=y
+CONFIG_DIMLIB=y
+CONFIG_DLCI=m
+CONFIG_DLCI_MAX=8
+CONFIG_DLHL60D=m
+CONFIG_DLN2_ADC=m
+CONFIG_DMABUF_SELFTESTS=m
+CONFIG_DMA_CMA=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_NONCOHERENT_MMAP=y
+CONFIG_DMA_NUMA_CMA=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OMAP=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_PERNUMA_CMA=y
+CONFIG_DMARD09=m
+CONFIG_DMARD10=m
+CONFIG_DMA_REMAP=y
+CONFIG_DMA_RESTRICTED_POOL=y
+CONFIG_DMA_SUN4I=y
+CONFIG_DMA_VIRT_OPS=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DM_CACHE=m
+CONFIG_DM_CACHE_SMQ=m
+CONFIG_DM_CLONE=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_DELAY=m
+CONFIG_DM_DUST=m
+CONFIG_DM_ERA=m
+CONFIG_DM_FLAKEY=m
+CONFIG_DMIID=y
+CONFIG_DM_INTEGRITY=m
+CONFIG_DMI_SYSFS=m
+CONFIG_DMI=y
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_LOG_WRITES=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_MULTIPATH_HST=m
+CONFIG_DM_MULTIPATH_IOA=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_RAID=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_SWITCH=m
+CONFIG_DM_UEVENT=y
+CONFIG_DM_UNSTRIPED=m
+CONFIG_DM_VERITY=m
+CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
+CONFIG_DM_WRITECACHE=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_ZONED=m
+CONFIG_DP83640_PHY=m
+CONFIG_DP83822_PHY=m
+CONFIG_DP83848_PHY=m
+CONFIG_DP83867_PHY=m
+CONFIG_DP83869_PHY=m
+CONFIG_DP83TC811_PHY=m
+CONFIG_DP83TD510_PHY=m
+CONFIG_DP83TG720_PHY=m
+CONFIG_DPS310=m
+CONFIG_DRM_ACCEL_HABANALABS=m
+CONFIG_DRM_ACCEL_IVPU=m
+CONFIG_DRM_ACCEL_QAIC=m
+CONFIG_DRM_ACCEL=y
+CONFIG_DRM_ADP=m
+CONFIG_DRM_AMD_ACP=y
+CONFIG_DRM_AMD_DC_HDCP=y
+CONFIG_DRM_AMD_DC_SI=y
+CONFIG_DRM_AMD_DC=y
+CONFIG_DRM_AMDGPU_CIK=y
+CONFIG_DRM_AMDGPU=m
+CONFIG_DRM_AMDGPU_SI=y
+CONFIG_DRM_AMD_ISP=y
+CONFIG_DRM_ANALOGIX_ANX6345=m
+CONFIG_DRM_ANALOGIX_ANX7625=m
+CONFIG_DRM_ANALOGIX_ANX78XX=m
+CONFIG_DRM_ANALOGIX_DP=m
+CONFIG_DRM_APPLETBDRM=m
+CONFIG_DRM_ARCPGU=m
+CONFIG_DRM_ARMADA=m
+CONFIG_DRM_AST=m
+CONFIG_DRM_ATMEL_HLCDC=m
+CONFIG_DRM_BOCHS=m
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_CDNS_DSI_J721E=y
+CONFIG_DRM_CDNS_DSI=m
+CONFIG_DRM_CDNS_MHDP8546=m
+CONFIG_DRM_CHIPONE_ICN6211=m
+CONFIG_DRM_CHRONTEL_CH7033=m
+CONFIG_DRM_CIRRUS_QEMU=m
+CONFIG_DRM_CLIENT_DEFAULT_LOG=y
+CONFIG_DRM_CLIENT_LOG=y
+CONFIG_DRM_CROS_EC_ANX7688=m
+CONFIG_DRM_DISPLAY_CONNECTOR=m
+CONFIG_DRM_DISPLAY_DP_AUX_CEC=y
+CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV=y
+CONFIG_DRM_DP_AUX_CHARDEV=y
+CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
+CONFIG_DRM_DW_HDMI_CEC=m
+CONFIG_DRM_DW_HDMI_GP_AUDIO=m
+CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
+CONFIG_DRM_DW_HDMI=m
+CONFIG_DRM_DW_MIPI_DSI=m
+CONFIG_DRM_ETNAVIV=m
+CONFIG_DRM_ETNAVIV_THERMAL=y
+CONFIG_DRM_EVDI=m
+CONFIG_DRM_EXPORT_FOR_TESTS=y
+CONFIG_DRM_EXYNOS5433_DECON=y
+CONFIG_DRM_EXYNOS7_DECON=y
+CONFIG_DRM_EXYNOS_DPI=y
+CONFIG_DRM_EXYNOS_DP=y
+CONFIG_DRM_EXYNOS_DSI=y
+CONFIG_DRM_EXYNOS_FIMC=y
+CONFIG_DRM_EXYNOS_FIMD=y
+CONFIG_DRM_EXYNOS_G2D=y
+CONFIG_DRM_EXYNOS_GSC=y
+CONFIG_DRM_EXYNOS_HDMI=y
+CONFIG_DRM_EXYNOS_IPP=y
+CONFIG_DRM_EXYNOS=m
+CONFIG_DRM_EXYNOS_MIC=y
+CONFIG_DRM_EXYNOS_MIXER=y
+CONFIG_DRM_EXYNOS_ROTATOR=y
+CONFIG_DRM_EXYNOS_SCALER=y
+CONFIG_DRM_EXYNOS_VIDI=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_FSL_DCU=m
+CONFIG_DRM_FSL_LDB=m
+CONFIG_DRM_GEM_CMA_HELPER=y
+CONFIG_DRM_GEM_SHMEM_HELPER=y
+CONFIG_DRM_GM12U320=m
+CONFIG_DRM_GUD=m
+CONFIG_DRM_HISI_HIBMC=m
+CONFIG_DRM_HYPERV=m
+CONFIG_DRM_I2C_ADV7511_AUDIO=y
+CONFIG_DRM_I2C_ADV7511_CEC=y
+CONFIG_DRM_I2C_ADV7511=m
+CONFIG_DRM_I2C_CH7006=m
+CONFIG_DRM_I2C_NXP_TDA9950=m
+CONFIG_DRM_I2C_NXP_TDA998X=m
+CONFIG_DRM_I2C_SIL164=m
+CONFIG_DRM_IMX8_DC=m
+CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=m
+CONFIG_DRM_IMX8MP_HDMI_PVI=m
+CONFIG_DRM_IMX8QM_LDB=m
+CONFIG_DRM_IMX8QXP_LDB=m
+CONFIG_DRM_IMX8QXP_PIXEL_COMBINER=m
+CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI=m
+CONFIG_DRM_IMX93_MIPI_DSI=m
+CONFIG_DRM_IMX_HDMI=m
+CONFIG_DRM_IMX_LCDC=m
+CONFIG_DRM_IMX_LCDIF=m
+CONFIG_DRM_IMX_LDB=m
+CONFIG_DRM_IMX=m
+CONFIG_DRM_IMX_PARALLEL_DISPLAY=m
+CONFIG_DRM_IMX_TVE=m
+CONFIG_DRM_ITE_IT6505=m
+CONFIG_DRM_ITE_IT66121=m
+CONFIG_DRM_KMS_CMA_HELPER=y
+CONFIG_DRM_KMS_FB_HELPER=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_LEGACY=y
+CONFIG_DRM_LIB_RANDOM=y
+CONFIG_DRM_LIMA=m
+CONFIG_DRM_LOGICVC=m
+CONFIG_DRM_LONTIUM_LT8912B=m
+CONFIG_DRM_LONTIUM_LT9211=m
+CONFIG_DRM_LONTIUM_LT9611=m
+CONFIG_DRM_LONTIUM_LT9611UXC=m
+CONFIG_DRM_LOONGSON=m
+CONFIG_DRM_LVDS_CODEC=m
+CONFIG_DRM_MCDE=m
+CONFIG_DRM_MEDIATEK_DP=m
+CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m
+CONFIG_DRM_MGAG200=m
+CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER=m
+CONFIG_DRM_MIPI_DBI=m
+CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_MXSFB=m
+CONFIG_DRM_MXS=y
+CONFIG_DRM_NOUVEAU_CH7006=m
+CONFIG_DRM_NOUVEAU_GSP_DEFAULT=y
+CONFIG_DRM_NOUVEAU=m
+CONFIG_DRM_NOUVEAU_SIL164=m
+CONFIG_DRM_NWL_MIPI_DSI=m
+CONFIG_DRM_NXP_PTN3460=m
+CONFIG_DRM_OMAP=m
+CONFIG_DRM_OMAP_PANEL_DSI_CM=m
+CONFIG_DRM_PANEL_ABT_Y030XX067A=m
+CONFIG_DRM_PANEL_ARM_VERSATILE=m
+CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
+CONFIG_DRM_PANEL_AUO_A030JTN01=m
+CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
+CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
+CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A=m
+CONFIG_DRM_PANEL_BOE_TV101WUM_LL2=m
+CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_DSI_CM=m
+CONFIG_DRM_PANEL_EBBG_FT8719=m
+CONFIG_DRM_PANEL_EDP=m
+CONFIG_DRM_PANEL_ELIDA_KD35T133=m
+CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
+CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
+CONFIG_DRM_PANEL_HIMAX_HX83102=m
+CONFIG_DRM_PANEL_HIMAX_HX83112A=m
+CONFIG_DRM_PANEL_HIMAX_HX83112B=m
+CONFIG_DRM_PANEL_HIMAX_HX8394=m
+CONFIG_DRM_PANEL_HYDIS_HV101HD1=m
+CONFIG_DRM_PANEL_ILITEK_IL9322=m
+CONFIG_DRM_PANEL_ILITEK_ILI9341=m
+CONFIG_DRM_PANEL_ILITEK_ILI9805=m
+CONFIG_DRM_PANEL_ILITEK_ILI9806E=m
+CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
+CONFIG_DRM_PANEL_ILITEK_ILI9882T=m
+CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
+CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
+CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=m
+CONFIG_DRM_PANEL_JDI_LPM102A188A=m
+CONFIG_DRM_PANEL_JDI_LT070ME05000=m
+CONFIG_DRM_PANEL_JDI_R63452=m
+CONFIG_DRM_PANEL_KHADAS_TS050=m
+CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
+CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
+CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
+CONFIG_DRM_PANEL_LG_LB035Q02=m
+CONFIG_DRM_PANEL_LG_LG4573=m
+CONFIG_DRM_PANEL_LG_SW43408=m
+CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m
+CONFIG_DRM_PANEL_LVDS=m
+CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m
+CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
+CONFIG_DRM_PANEL_MIPI_DBI=m
+CONFIG_DRM_PANEL_NEC_NL8048HL11=m
+CONFIG_DRM_PANEL_NEWVISION_NV3051D=m
+CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
+CONFIG_DRM_PANEL_NOVATEK_NT35510=m
+CONFIG_DRM_PANEL_NOVATEK_NT35560=m
+CONFIG_DRM_PANEL_NOVATEK_NT35950=m
+CONFIG_DRM_PANEL_NOVATEK_NT36523=m
+CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
+CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
+CONFIG_DRM_PANEL_NOVATEK_NT39016=m
+CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m
+CONFIG_DRM_PANEL_ORISETECH_OTA5601A=m
+CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
+CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
+CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
+CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
+CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
+CONFIG_DRM_PANEL_RAYDIUM_RM67200=m
+CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
+CONFIG_DRM_PANEL_RAYDIUM_RM692E5=m
+CONFIG_DRM_PANEL_RAYDIUM_RM69380=m
+CONFIG_DRM_PANEL_RENESAS_R61307=m
+CONFIG_DRM_PANEL_RENESAS_R69328=m
+CONFIG_DRM_PANEL_RONBO_RB070D30=m
+CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
+CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
+CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
+CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
+CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
+CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01=m
+CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
+CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
+CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
+CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
+CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
+CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
+CONFIG_DRM_PANEL_SIMPLE=m
+CONFIG_DRM_PANEL_SITRONIX_ST7701=m
+CONFIG_DRM_PANEL_SITRONIX_ST7703=m
+CONFIG_DRM_PANEL_SITRONIX_ST7789V=m
+CONFIG_DRM_PANEL_SONY_ACX424AKP=m
+CONFIG_DRM_PANEL_SONY_ACX565AKM=m
+CONFIG_DRM_PANEL_SONY_TD4353_JDI=m
+CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
+CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m
+CONFIG_DRM_PANEL_SUMMIT=m
+CONFIG_DRM_PANEL_SYNAPTICS_R63353=m
+CONFIG_DRM_PANEL_TDO_TL070WSH30=m
+CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
+CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
+CONFIG_DRM_PANEL_TPO_TPG110=m
+CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
+CONFIG_DRM_PANEL_VISIONOX_R66451=m
+CONFIG_DRM_PANEL_VISIONOX_RM69299=m
+CONFIG_DRM_PANEL_VISIONOX_RM692E5=m
+CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
+CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
+CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANFROST=m
+CONFIG_DRM_PANIC_BACKGROUND_COLOR=0x000000
+CONFIG_DRM_PANIC_FOREGROUND_COLOR=0xa0a0a0
+CONFIG_DRM_PANIC_SCREEN="user"
+CONFIG_DRM_PANIC=y
+CONFIG_DRM_PANTHOR=m
+CONFIG_DRM_PARADE_PS8622=m
+CONFIG_DRM_PARADE_PS8640=m
+CONFIG_DRM_PIXPAPER=m
+CONFIG_DRM_PL111=m
+CONFIG_DRM_POWERVR=m
+CONFIG_DRM_QXL=m
+CONFIG_DRM_RADEON=m
+CONFIG_DRM_RCAR_DW_HDMI=m
+CONFIG_DRM_RCAR_LVDS=m
+CONFIG_DRM_RCAR_MIPI_DSI=m
+CONFIG_DRM_RCAR_USE_CMM=y
+CONFIG_DRM_RCAR_USE_LVDS=y
+CONFIG_DRM_RCAR_USE_MIPI_DSI=y
+CONFIG_DRM_RZG2L_DU=m
+CONFIG_DRM_RZG2L_MIPI_DSI=m
+CONFIG_DRM_SAMSUNG_DSIM=m
+CONFIG_DRM_SCHED=m
+CONFIG_DRM_SHMOBILE=m
+CONFIG_DRM_SII902X=m
+CONFIG_DRM_SII9234=m
+CONFIG_DRM_SIL_SII8620=m
+CONFIG_DRM_SIMPLE_BRIDGE=m
+CONFIG_DRM_SIMPLEDRM=y
+CONFIG_DRM_SOLOMON_SSD2825=m
+CONFIG_DRM_SPRD=m
+CONFIG_DRM_SSD130X_I2C=m
+CONFIG_DRM_SSD130X=m
+CONFIG_DRM_SSD130X_SPI=m
+CONFIG_DRM_STI=m
+CONFIG_DRM_STM_DSI=m
+CONFIG_DRM_STM_LVDS=m
+CONFIG_DRM_STM=m
+CONFIG_DRM_THINE_THC63LVD1024=m
+CONFIG_DRM_TI_DLPC3433=m
+CONFIG_DRM_TIDSS=m
+CONFIG_DRM_TILCDC=m
+CONFIG_DRM_TI_SN65DSI83=m
+CONFIG_DRM_TI_SN65DSI86=m
+CONFIG_DRM_TI_TFP410=m
+CONFIG_DRM_TI_TPD12S015=m
+CONFIG_DRM_TOSHIBA_TC358762=m
+CONFIG_DRM_TOSHIBA_TC358764=m
+CONFIG_DRM_TOSHIBA_TC358767=m
+CONFIG_DRM_TOSHIBA_TC358768=m
+CONFIG_DRM_TOSHIBA_TC358775=m
+CONFIG_DRM_TTM_DMA_PAGE_POOL=y
+CONFIG_DRM_TTM_HELPER=m
+CONFIG_DRM_TTM=m
+CONFIG_DRM_TVE200=m
+CONFIG_DRM_UDL=m
+CONFIG_DRM_VGEM=m
+CONFIG_DRM_VIRTIO_GPU_KMS=y
+CONFIG_DRM_VIRTIO_GPU=m
+CONFIG_DRM_VKMS=m
+CONFIG_DRM_VM=y
+CONFIG_DRM_VRAM_HELPER=m
+CONFIG_DRM_WAVESHARE_BRIDGE=m
+CONFIG_DRM_XE_DEVMEM_MIRROR=y
+CONFIG_DRM_XE_DISPLAY=y
+CONFIG_DRM_XE_DP_TUNNEL=y
+CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT=y
+CONFIG_DRM_XE_FORCE_PROBE=""
+CONFIG_DRM_XE_JOB_TIMEOUT_MAX=10000
+CONFIG_DRM_XE_JOB_TIMEOUT_MIN=1
+CONFIG_DRM_XE=m
+CONFIG_DRM_XE_PREEMPT_TIMEOUT=640000
+CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX=10000000
+CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN=1
+CONFIG_DRM_XE_SIMPLE_ERROR_CAPTURE=y
+CONFIG_DRM_XE_TIMESLICE_MAX=10000000
+CONFIG_DRM_XE_TIMESLICE_MIN=1
+CONFIG_DRM=y
+CONFIG_DS1682=m
+CONFIG_DS1803=m
+CONFIG_DS4424=m
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DTPM_CPU=y
+CONFIG_DTPM_DEVFREQ=y
+CONFIG_DTPM=y
+CONFIG_DUMMY_CONSOLE_ROWS=30
+CONFIG_DUMMY=m
+CONFIG_DVB_A8293=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_AF9033=m
+CONFIG_DVB_AS102_FE=m
+CONFIG_DVB_AS102=m
+CONFIG_DVB_ASCOT2E=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_AU8522_DTV=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_AU8522_V4L=m
+CONFIG_DVB_AV7110_IR=y
+CONFIG_DVB_AV7110=m
+CONFIG_DVB_AV7110_OSD=y
+CONFIG_DVB_B2C2_FLEXCOP=m
+CONFIG_DVB_B2C2_FLEXCOP_PCI=m
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_BT8XX=m
+CONFIG_DVB_BUDGET_AV=m
+CONFIG_DVB_BUDGET_CI=m
+CONFIG_DVB_BUDGET_CORE=m
+CONFIG_DVB_BUDGET=m
+CONFIG_DVB_BUDGET_PATCH=m
+CONFIG_DVB_C8SECTPFE=m
+CONFIG_DVB_CORE=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_CX24117=m
+CONFIG_DVB_CX24120=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_CXD2099=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_CXD2841ER=m
+CONFIG_DVB_CXD2880=m
+CONFIG_DVB_DDBRIDGE=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_DIB9000=m
+CONFIG_DVB_DM1105=m
+CONFIG_DVB_DRX39XYJ=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_DYNAMIC_MINORS=y
+CONFIG_DVB_EC100=m
+CONFIG_DVB_FIREDTV_INPUT=y
+CONFIG_DVB_FIREDTV=m
+CONFIG_DVB_GP8PSK_FE=m
+CONFIG_DVB_HELENE=m
+CONFIG_DVB_HOPPER=m
+CONFIG_DVB_HORUS3A=m
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6422=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_LG2160=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_LGDT3306A=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGS8GL5=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_LNBH25=m
+CONFIG_DVB_LNBH29=m
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_M88DS3103=m
+CONFIG_DVB_M88RS2000=m
+CONFIG_DVB_MANTIS=m
+CONFIG_DVB_MAX_ADAPTERS=8
+CONFIG_DVB_MB86A16=m
+CONFIG_DVB_MB86A20S=m
+CONFIG_DVB_MMAP=y
+CONFIG_DVB_MN88443X=m
+CONFIG_DVB_MN88472=m
+CONFIG_DVB_MN88473=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_MXL5XX=m
+CONFIG_DVB_NETUP_UNIDVB=m
+CONFIG_DVB_NET=y
+CONFIG_DVB_NGENE=m
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_PLATFORM_DRIVERS=y
+CONFIG_DVB_PLL=m
+CONFIG_DVB_PLUTO2=m
+CONFIG_DVB_PT1=m
+CONFIG_DVB_PT3=m
+CONFIG_DVB_RTL2830=m
+CONFIG_DVB_RTL2832=m
+CONFIG_DVB_RTL2832_SDR=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_S5H1411=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_S921=m
+CONFIG_DVB_SI2165=m
+CONFIG_DVB_SI2168=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_SMIPCIE=m
+CONFIG_DVB_SP2=m
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STV0297=m
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV0910=m
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV6110x=m
+CONFIG_DVB_STV6111=m
+CONFIG_DVB_TAS2101=m
+CONFIG_DVB_TC90522=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_TDA10071=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA18271C2DD=m
+CONFIG_DVB_TDA665x=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TS2020=m
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_CXUSB_ANALOG=y
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_DIB3000MC=m
+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
+CONFIG_DVB_USB_DIBUSB_MB=m
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_DVBSKY=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_V2=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_ZD1301=m
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_ZD1301_DEMOD=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DW_APB_ICTL=y
 CONFIG_DW_APB_TIMER_OF=y
-CONFIG_ROCKCHIP_TIMER=y
-CONFIG_MESON6_TIMER=y
-CONFIG_OWL_TIMER=y
-CONFIG_RDA_TIMER=y
-CONFIG_SUN4I_TIMER=y
-CONFIG_SUN5I_HSTIMER=y
-CONFIG_VT8500_TIMER=y
-CONFIG_CADENCE_TTC_TIMER=y
-CONFIG_CLKSRC_NOMADIK_MTU=y
-CONFIG_CLKSRC_DBX500_PRCMU=y
-CONFIG_ATLAS7_TIMER=y
-CONFIG_PRIMA2_TIMER=y
-CONFIG_KEYSTONE_TIMER=y
-CONFIG_CLKSRC_TI_32K=y
-CONFIG_CLKSRC_STM32=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GLOBAL_TIMER=y
-CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2
-CONFIG_ARM_TIMER_SP804=y
-CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
-CONFIG_CLKSRC_EXYNOS_MCT=y
-CONFIG_CLKSRC_SAMSUNG_PWM=y
-CONFIG_MTK_TIMER=y
-CONFIG_CLKSRC_QCOM=y
-CONFIG_CLKSRC_VERSATILE=y
-CONFIG_CLKSRC_TANGO_XTAL=y
-CONFIG_CLKSRC_IMX_GPT=y
-CONFIG_CLKSRC_ST_LPC=y
-# CONFIG_MICROCHIP_PIT64B is not set
-# end of Clock Source drivers
-
-CONFIG_MAILBOX=y
-# CONFIG_ARM_MHU is not set
-CONFIG_ARM_MHU_V2=m
-# CONFIG_IMX_MBOX is not set
-# CONFIG_PLATFORM_MHU is not set
-CONFIG_PL320_MBOX=y
-# CONFIG_ARMADA_37XX_RWTM_MBOX is not set
-# CONFIG_OMAP2PLUS_MBOX is not set
-# CONFIG_ROCKCHIP_MBOX is not set
-CONFIG_ALTERA_MBOX=m
-# CONFIG_STI_MBOX is not set
-# CONFIG_TI_MESSAGE_MANAGER is not set
+CONFIG_DW_APB_TIMER=y
+CONFIG_DWC_PCIE_PMU=m
+CONFIG_DW_DMAC_CORE=y
+CONFIG_DW_DMAC=m
+CONFIG_DW_DMAC_PCI=y
+CONFIG_DW_EDMA=m
+CONFIG_DW_EDMA_PCIE=m
+CONFIG_DW_I3C_MASTER=m
+CONFIG_DW_WATCHDOG=m
+CONFIG_DW_XDATA_PCIE=m
+CONFIG_DYNAMIC_EVENTS=y
+CONFIG_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_DYNAMIC_FTRACE=y
+CONFIG_ECHO=m
+CONFIG_EDAC_AL_MC=m
+CONFIG_EDAC_ASPEED=m
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_ECS=y
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC=m
+CONFIG_EDAC_MEM_REPAIR=y
+CONFIG_EDAC_NPCM=m
+CONFIG_EDAC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EDAC_VERSAL=m
+CONFIG_EEPROM_93CX6=m
+CONFIG_EEPROM_93XX46=m
+CONFIG_EEPROM_AT24=m
+CONFIG_EEPROM_AT25=m
+CONFIG_EEPROM_EE1004=m
+CONFIG_EEPROM_IDT_89HPESX=m
+CONFIG_EEPROM_LEGACY=m
+CONFIG_EEPROM_MAX6875=m
+CONFIG_EFI_ARMSTUB_DTB_LOADER=y
+CONFIG_EFI_BOOTLOADER_CONTROL=m
+CONFIG_EFI_CAPSULE_LOADER=m
+CONFIG_EFI_COCO_SECRET=y
+CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
+CONFIG_EFI_VARS_PSTORE=m
+CONFIG_EFI=y
+CONFIG_EINT_MTK=y
+CONFIG_ENCLOSURE_SERVICES=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_ENERGY_MODEL=y
+CONFIG_ENS160=m
+CONFIG_ENS210=m
+CONFIG_EQUALIZER=m
+CONFIG_EVENT_TRACING=y
+CONFIG_EXPERT=y
+CONFIG_EXTCON_ADC_JACK=m
+CONFIG_EXTCON_ARIZONA=m
+CONFIG_EXTCON_FSA9480=m
+CONFIG_EXTCON_GPIO=m
+CONFIG_EXTCON_LC824206XA=m
+CONFIG_EXTCON_MAX14526=m
+CONFIG_EXTCON_MAX14577=m
+CONFIG_EXTCON_MAX3355=m
+CONFIG_EXTCON_MAX77693=m
+CONFIG_EXTCON_PTN5150=m
+CONFIG_EXTCON_RT8973A=m
+CONFIG_EXTCON_RTK_TYPE_C=m
+CONFIG_EXTCON_SM5502=m
+CONFIG_EXTCON_USBC_CROS_EC=m
+CONFIG_EXTCON_USBC_TUSB320=m
+CONFIG_EXTCON_USB_GPIO=m
+CONFIG_EXTCON=y
+CONFIG_EXYNOS_ACPM_PROTOCOL=m
+CONFIG_EXYNOS_ASV_ARM=y
+CONFIG_EXYNOS_ASV=y
+CONFIG_EXYNOS_AUDSS_CLK_CON=y
+CONFIG_EXYNOS_CHIPID=y
+CONFIG_EXYNOS_CLKOUT=m
+CONFIG_EXYNOS_CPU_SUSPEND=y
+CONFIG_EXYNOS_IRQ_COMBINER=y
+CONFIG_EXYNOS_MBOX=m
+CONFIG_EXYNOS_MCPM=y
+CONFIG_EXYNOS_PM_DOMAINS=y
+CONFIG_EXYNOS_PMU_ARM_DRIVERS=y
+CONFIG_EXYNOS_PMU=y
+CONFIG_EXYNOS_REGULATOR_COUPLER=y
+CONFIG_EXYNOS_SROM=y
+CONFIG_EXYNOS_THERMAL=y
+CONFIG_EXYNOS_USI=m
+CONFIG_EZX_PCAP=y
+CONFIG_FAILOVER=m
+CONFIG_FARSYNC=m
+CONFIG_FB_ARK=m
+CONFIG_FB_ASILIANT=y
+CONFIG_FB_ATY128_BACKLIGHT=y
+CONFIG_FB_ATY128=m
+CONFIG_FB_BACKLIGHT=m
+CONFIG_FB_BOTH_ENDIAN=y
+CONFIG_FB_CARMINE_DRAM_EVAL=y
+CONFIG_FB_CARMINE=m
+CONFIG_FB_CIRRUS=m
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_CYBER2000_DDC=y
+CONFIG_FB_CYBER2000=m
+CONFIG_FB_DDC=m
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_EFI=y
+CONFIG_FB_FOREIGN_ENDIAN=y
+CONFIG_FB_IBM_GXT4500=m
+CONFIG_FB_IMSTT=y
+CONFIG_FB_KYRO=m
+CONFIG_FB_MB862XX_I2C=y
+CONFIG_FB_MB862XX=m
+CONFIG_FB_MB862XX_PCI_GDC=y
+CONFIG_FB_METRONOME=m
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_MX3=y
+CONFIG_FB_NEOMAGIC=m
+CONFIG_FB_OPENCORES=m
+CONFIG_FB_PM2_FIFO_DISCONNECT=y
+CONFIG_FB_PM2=m
+CONFIG_FB_PM3=m
+CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA=y
+CONFIG_FB_RADEON_BACKLIGHT=y
+CONFIG_FB_RADEON_I2C=y
+CONFIG_FB_RADEON=m
+CONFIG_FB_S1D13XXX=m
+CONFIG_FB_SM501=m
+CONFIG_FB_SM712=m
+CONFIG_FB_SM750=m
+CONFIG_FB_SMSCUFX=m
+CONFIG_FB_SSD1307=m
+CONFIG_FB_SVGALIB=m
+CONFIG_FB_SYS_COPYAREA=m
+CONFIG_FB_SYS_FILLRECT=m
+CONFIG_FB_SYS_FOPS=m
+CONFIG_FB_SYS_IMAGEBLIT=m
+CONFIG_FB_TFT_AGM1264K_FL=m
+CONFIG_FB_TFT_BD663474=m
+CONFIG_FB_TFT_HX8340BN=m
+CONFIG_FB_TFT_HX8347D=m
+CONFIG_FB_TFT_HX8353D=m
+CONFIG_FB_TFT_HX8357D=m
+CONFIG_FB_TFT_ILI9163=m
+CONFIG_FB_TFT_ILI9320=m
+CONFIG_FB_TFT_ILI9325=m
+CONFIG_FB_TFT_ILI9340=m
+CONFIG_FB_TFT_ILI9341=m
+CONFIG_FB_TFT_ILI9481=m
+CONFIG_FB_TFT_ILI9486=m
+CONFIG_FB_TFT=m
+CONFIG_FB_TFT_PCD8544=m
+CONFIG_FB_TFT_RA8875=m
+CONFIG_FB_TFT_S6D02A1=m
+CONFIG_FB_TFT_S6D1121=m
+CONFIG_FB_TFT_SEPS525=m
+CONFIG_FB_TFT_SH1106=m
+CONFIG_FB_TFT_SSD1289=m
+CONFIG_FB_TFT_SSD1305=m
+CONFIG_FB_TFT_SSD1306=m
+CONFIG_FB_TFT_SSD1331=m
+CONFIG_FB_TFT_SSD1351=m
+CONFIG_FB_TFT_ST7789V=m
+CONFIG_FB_TFT_TINYLCD=m
+CONFIG_FB_TFT_TLS8204=m
+CONFIG_FB_TFT_UC1611=m
+CONFIG_FB_TFT_UC1701=m
+CONFIG_FB_TFT_UPD161704=m
+CONFIG_FB_TFT_WATTEROTT=m
+CONFIG_FB_TILEBLITTING=y
+CONFIG_FB_TMIO_ACCELL=y
+CONFIG_FB_TMIO=m
+CONFIG_FB_TRIDENT=m
+CONFIG_FB_UDL=m
+CONFIG_FB_UVESA=m
+CONFIG_FB_VT8623=m
+CONFIG_FCOE=m
+CONFIG_FIB_RULES=y
+CONFIG_FIELDBUS_DEV=m
+CONFIG_FIREWIRE=m
+CONFIG_FIREWIRE_NET=m
+CONFIG_FIREWIRE_NOSY=m
+CONFIG_FIREWIRE_OHCI=m
+CONFIG_FIREWIRE_SBP2=m
+CONFIG_FIREWIRE_SERIAL=m
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_6x8=y
+CONFIG_FONTS=y
+CONFIG_FONT_TER16x32=y
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_FORCE_PCI=y
+CONFIG_FORTIFY_SOURCE=y
+CONFIG_FPGA_BRIDGE=m
+CONFIG_FPGA_DFL_AFU=m
+CONFIG_FPGA_DFL_EMIF=m
+CONFIG_FPGA_DFL_FME_BRIDGE=m
+CONFIG_FPGA_DFL_FME=m
+CONFIG_FPGA_DFL_FME_MGR=m
+CONFIG_FPGA_DFL_FME_REGION=m
+CONFIG_FPGA_DFL=m
+CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
+CONFIG_FPGA_DFL_PCI=m
+CONFIG_FPGA=m
+CONFIG_FPGA_M10_BMC_SEC_UPDATE=m
+CONFIG_FPGA_MGR_ALTERA_CVP=m
+CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
+CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=m
+CONFIG_FPGA_MGR_MACHXO2_SPI=m
+CONFIG_FPGA_MGR_MICROCHIP_SPI=m
+CONFIG_FPGA_MGR_SOCFPGA_A10=m
+CONFIG_FPGA_MGR_SOCFPGA=m
+CONFIG_FPGA_MGR_XILINX_SELECTMAP=m
+CONFIG_FPGA_MGR_XILINX_SPI=m
+CONFIG_FPGA_REGION=m
+CONFIG_FPROBE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FRAME_VECTOR=y
+CONFIG_FRONTSWAP=y
+CONFIG_FSL_IMX9_DDR_PMU=m
+CONFIG_FTL=m
+CONFIG_FTM_QUADDEC=m
+CONFIG_FTRACE_MCOUNT_RECORD=y
+CONFIG_FTRACE_RECORD_RECURSION_SIZE=128
+CONFIG_FTRACE_RECORD_RECURSION=y
+CONFIG_FTRACE_SYSCALLS=y
+CONFIG_FTWDT010_WATCHDOG=m
+CONFIG_FUEL_GAUGE_MM8013=m
+CONFIG_FUEL_GAUGE_STC3117=m
+CONFIG_FUNCTION_PROFILER=y
+CONFIG_FUNCTION_TRACER=y
+CONFIG_FUSION_CTL=m
+CONFIG_FUSION_FC=m
+CONFIG_FUSION_LAN=m
+CONFIG_FUSION_LOGGING=y
+CONFIG_FUSION_MAX_SGE=128
+CONFIG_FUSION_SAS=m
+CONFIG_FUSION_SPI=m
+CONFIG_FUSION=y
+CONFIG_FW_LOADER_COMPRESS_XZ=y
+CONFIG_FW_LOADER_COMPRESS=y
+CONFIG_FW_LOADER_COMPRESS_ZSTD=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FWTTY_MAX_CARD_PORTS=32
+CONFIG_FWTTY_MAX_TOTAL_PORTS=64
+CONFIG_FW_UPLOAD=y
+CONFIG_FXAS21002C_I2C=m
+CONFIG_FXAS21002C=m
+CONFIG_FXAS21002C_SPI=m
+CONFIG_FXLS8962AF_I2C=m
+CONFIG_FXLS8962AF_SPI=m
+CONFIG_FXOS8700_I2C=m
+CONFIG_FXOS8700=m
+CONFIG_FXOS8700_SPI=m
+CONFIG_GADGET_UAC1=y
+CONFIG_GAMEPORT_EMU10K1=m
+CONFIG_GAMEPORT_FM801=m
+CONFIG_GAMEPORT_L4=m
+CONFIG_GAMEPORT=m
+CONFIG_GAMEPORT_NS558=m
+CONFIG_GCC_PLUGIN_ARM_SSP_PER_TASK=y
+CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y
+CONFIG_GCC_VERSION=100200
+CONFIG_GENERIC_ADC_BATTERY=m
+CONFIG_GENERIC_ADC_THERMAL=m
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_IPI=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PHY_MIPI_DPHY=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_TRACER=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GENEVE=m
+CONFIG_GIC_NON_BANKED=y
+CONFIG_GNSS=m
+CONFIG_GNSS_MTK_SERIAL=m
+CONFIG_GNSS_SERIAL=m
+CONFIG_GNSS_SIRF_SERIAL=m
+CONFIG_GNSS_UBX_SERIAL=m
+CONFIG_GNSS_USB=m
+CONFIG_GOOGLE_CBMEM=m
+CONFIG_GOOGLE_COREBOOT_TABLE=m
+CONFIG_GOOGLE_FIRMWARE=y
+CONFIG_GOOGLE_FRAMEBUFFER_COREBOOT=m
+CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m
+CONFIG_GOOGLE_MEMCONSOLE=m
+CONFIG_GOOGLE_VPD=m
+CONFIG_GP2AP002=m
+CONFIG_GP2AP020A00F=m
+CONFIG_GPIO_74XX_MMIO=m
+CONFIG_GPIO_ADNP=m
+CONFIG_GPIO_ADP5585=m
+CONFIG_GPIO_ADP5588=m
+CONFIG_GPIO_AGGREGATOR=m
+CONFIG_GPIO_ALTERA_A10SR=m
+CONFIG_GPIO_ALTERA=m
+CONFIG_GPIO_AMD_FCH=m
+CONFIG_GPIO_ARIZONA=m
+CONFIG_GPIO_BD9571MWV=m
+CONFIG_GPIO_CADENCE=m
+CONFIG_GPIO_CDEV_V1=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CROS_EC=m
+CONFIG_GPIO_DA9052=m
+CONFIG_GPIO_DLN2=m
+CONFIG_GPIO_DS4520=m
+CONFIG_GPIO_DWAPB=m
+CONFIG_GPIO_ELKHARTLAKE=m
+CONFIG_GPIO_EXAR=m
+CONFIG_GPIO_FTGPIO010=y
+CONFIG_GPIO_FXL6408=m
+CONFIG_GPIO_GENERIC_PLATFORM=m
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GRGPIO=m
+CONFIG_GPIO_GW_PLD=m
+CONFIG_GPIO_HLWD=m
+CONFIG_GPIO_JANZ_TTL=m
+CONFIG_GPIO_KEMPLD=m
+CONFIG_GPIO_LATCH=m
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_LOGICVC=m
+CONFIG_GPIO_LP3943=m
+CONFIG_GPIO_LP873X=m
+CONFIG_GPIO_MADERA=m
+CONFIG_GPIO_MAX3191X=m
+CONFIG_GPIO_MAX7300=m
+CONFIG_GPIO_MAX7301=m
+CONFIG_GPIO_MAX730X=m
+CONFIG_GPIO_MAX732X=m
+CONFIG_GPIO_MB86S7X=m
+CONFIG_GPIO_MC33880=m
+CONFIG_GPIO_MENZ127=m
+CONFIG_GPIO_MOCKUP=m
+CONFIG_GPIO_MOXTET=m
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_GPIO_MSC313=y
+CONFIG_GPIO_MVEBU=y
+CONFIG_GPIO_MXC=y
+CONFIG_GPIO_NPCM_SGPIO=y
+CONFIG_GPIO_OMAP=y
+CONFIG_GPIO_PCA953X=m
+CONFIG_GPIO_PCA9570=m
+CONFIG_GPIO_PCF857X=m
+CONFIG_GPIO_PCIE_IDIO_24=m
+CONFIG_GPIO_PCI_IDIO_16=m
+CONFIG_GPIO_PISOSR=m
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_PXA=y
+CONFIG_GPIO_RDC321X=m
+CONFIG_GPIO_REGMAP=m
+CONFIG_GPIO_ROCKCHIP=m
+CONFIG_GPIO_RTD=m
+CONFIG_GPIO_SAMA5D2_PIOBU=m
+CONFIG_GPIO_SIFIVE=y
+CONFIG_GPIO_SIM=m
+CONFIG_GPIO_SIOX=m
+CONFIG_GPIO_SL28CPLD=m
+CONFIG_GPIO_SPEAR_SPICS=y
+CONFIG_GPIO_SYSCON=m
+CONFIG_GPIO_SYSFS_LEGACY=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_TEGRA=y
+CONFIG_GPIO_TPIC2810=m
+CONFIG_GPIO_TPS65086=m
+CONFIG_GPIO_TPS65219=m
+CONFIG_GPIO_TPS65912=m
+CONFIG_GPIO_TPS68470=y
+CONFIG_GPIO_TQMX86=m
+CONFIG_GPIO_UCB1400=m
+CONFIG_GPIO_UNIPHIER=m
+CONFIG_GPIO_VF610=y
+CONFIG_GPIO_VIPERBOARD=m
+CONFIG_GPIO_VIRTIO=m
+CONFIG_GPIO_VISCONTI=m
+CONFIG_GPIO_WATCHDOG=m
+CONFIG_GPIO_WCD934X=m
+CONFIG_GPIO_WM831X=m
+CONFIG_GPIO_WM8994=m
+CONFIG_GPIO_XILINX=m
+CONFIG_GPIO_XRA1403=m
+CONFIG_GPIO_ZEVIO=y
+CONFIG_GP_PCI1XXXX=m
+CONFIG_GS_FPGABOOT=m
+CONFIG_GTP=m
+CONFIG_GXP_WATCHDOG=m
+CONFIG_HABANA_AI=m
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDEN_BRANCH_HISTORY=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDENED_USERCOPY_FALLBACK=y
+CONFIG_HARDENED_USERCOPY=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HARDLOCKUP_DETECTOR=y
+CONFIG_HD44780=m
+CONFIG_HDC100X=m
+CONFIG_HDC2010=m
+CONFIG_HDC3020=m
+CONFIG_HDLC_CISCO=m
+CONFIG_HDLC_FR=m
+CONFIG_HDLC=m
+CONFIG_HDLC_PPP=m
+CONFIG_HDLC_RAW_ETH=m
+CONFIG_HDLC_RAW=m
+CONFIG_HDLC_X25=m
+CONFIG_HDMI=y
+CONFIG_HERMES_CACHE_FW_ON_INIT=y
+CONFIG_HERMES=m
+CONFIG_HERMES_PRISM=y
 CONFIG_HI3660_MBOX=y
 CONFIG_HI6220_MBOX=y
-# CONFIG_MAILBOX_TEST is not set
-# CONFIG_QCOM_APCS_IPC is not set
-# CONFIG_TEGRA_HSP_MBOX is not set
-# CONFIG_STM32_IPCC is not set
-CONFIG_MTK_ADSP_MBOX=m
-# CONFIG_MTK_CMDQ_MBOX is not set
-CONFIG_MTK_DEVAPC=m
-CONFIG_SUN6I_MSGBOX=y
-# CONFIG_QCOM_IPCC is not set
-CONFIG_IOMMU_API=y
-CONFIG_IOMMU_SUPPORT=y
-
-#
-# Generic IOMMU Pagetable Support
-#
-CONFIG_IOMMU_IO_PGTABLE=y
-CONFIG_IOMMU_IO_PGTABLE_LPAE=y
-# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# end of Generic IOMMU Pagetable Support
-
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_OF_IOMMU=y
-# CONFIG_MSM_IOMMU is not set
-# CONFIG_OMAP_IOMMU is not set
-# CONFIG_ROCKCHIP_IOMMU is not set
-# CONFIG_SUN50I_IOMMU is not set
-# CONFIG_TEGRA_IOMMU_SMMU is not set
-# CONFIG_EXYNOS_IOMMU is not set
-# CONFIG_IPMMU_VMSA is not set
-# CONFIG_ARM_SMMU is not set
-# CONFIG_MTK_IOMMU is not set
-# CONFIG_MTK_IOMMU_V1 is not set
-# CONFIG_QCOM_IOMMU is not set
-
-#
-# Remoteproc drivers
-#
-# CONFIG_REMOTEPROC is not set
-# end of Remoteproc drivers
-
-#
-# Rpmsg drivers
-#
-CONFIG_RPMSG=m
-CONFIG_RPMSG_CHAR=m
-CONFIG_RPMSG_CTRL=m
-CONFIG_RPMSG_QCOM_GLINK=m
-CONFIG_RPMSG_QCOM_GLINK_RPM=m
-CONFIG_RPMSG_VIRTIO=m
-# end of Rpmsg drivers
-
-CONFIG_SOUNDWIRE=y
-
-#
-# SoundWire Devices
-#
-CONFIG_SOUNDWIRE_QCOM=m
-
-#
-# SOC (System On Chip) specific Drivers
-#
-CONFIG_OWL_PM_DOMAINS_HELPER=y
-# CONFIG_OWL_PM_DOMAINS is not set
-
-#
-# Amlogic SoC drivers
-#
-# CONFIG_MESON_CANVAS is not set
-CONFIG_MESON_CLK_MEASURE=y
-CONFIG_MESON_GX_SOCINFO=y
-CONFIG_MESON_GX_PM_DOMAINS=y
-CONFIG_MESON_EE_PM_DOMAINS=y
-CONFIG_MESON_MX_SOCINFO=y
-# end of Amlogic SoC drivers
-
-#
-# Aspeed SoC drivers
-#
-CONFIG_SOC_ASPEED=y
-# CONFIG_ASPEED_LPC_CTRL is not set
-# CONFIG_ASPEED_LPC_SNOOP is not set
-# CONFIG_ASPEED_P2A_CTRL is not set
-CONFIG_ASPEED_SOCINFO=y
-# end of Aspeed SoC drivers
-
-CONFIG_AT91_SOC_ID=y
-# CONFIG_AT91_SOC_SFR is not set
-
-#
-# Broadcom SoC drivers
-#
-# CONFIG_SOC_BRCMSTB is not set
-CONFIG_BCM_PMB=y
-# end of Broadcom SoC drivers
-
-#
-# NXP/Freescale QorIQ SoC drivers
-#
-# CONFIG_QUICC_ENGINE is not set
-# CONFIG_FSL_RCPM is not set
-# end of NXP/Freescale QorIQ SoC drivers
-
-#
-# i.MX SoC drivers
-#
-# CONFIG_IMX_GPCV2_PM_DOMAINS is not set
-# CONFIG_SOC_IMX8M is not set
-CONFIG_SOC_IMX9=m
-# end of i.MX SoC drivers
-
-#
-# MediaTek SoC drivers
-#
-# CONFIG_MTK_CMDQ is not set
-CONFIG_MTK_INFRACFG=y
-# CONFIG_MTK_PMIC_WRAP is not set
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_MMSYS=y
-CONFIG_MTK_SVS=m
-# end of MediaTek SoC drivers
-
-#
-# Qualcomm SoC drivers
-#
-# CONFIG_QCOM_AOSS_QMP is not set
-# CONFIG_QCOM_COMMAND_DB is not set
-CONFIG_QCOM_CPR=m
-# CONFIG_QCOM_GENI_SE is not set
-# CONFIG_QCOM_GSBI is not set
-# CONFIG_QCOM_LLCC is not set
-# CONFIG_QCOM_OCMEM is not set
-CONFIG_QCOM_QMI_HELPERS=m
-# CONFIG_QCOM_RMTFS_MEM is not set
-CONFIG_QCOM_RPMH=y
-# CONFIG_QCOM_SMEM is not set
-# CONFIG_QCOM_SMD_RPM is not set
-# CONFIG_QCOM_WCNSS_CTRL is not set
-# CONFIG_QCOM_APR is not set
-CONFIG_QCOM_ICC_BWMON=m
-# end of Qualcomm SoC drivers
-
-CONFIG_SOC_RENESAS=y
-# CONFIG_ARCH_EMEV2 is not set
-# CONFIG_ARCH_R8A7794 is not set
-# CONFIG_ARCH_R8A7779 is not set
-# CONFIG_ARCH_R8A7790 is not set
-# CONFIG_ARCH_R8A7778 is not set
-# CONFIG_ARCH_R8A7793 is not set
-# CONFIG_ARCH_R8A7791 is not set
-# CONFIG_ARCH_R8A7792 is not set
-# CONFIG_ARCH_R8A7740 is not set
-# CONFIG_ARCH_R8A73A4 is not set
-# CONFIG_ARCH_R7S72100 is not set
-# CONFIG_ARCH_R7S9210 is not set
-# CONFIG_ARCH_R8A77470 is not set
-# CONFIG_ARCH_R8A7745 is not set
-# CONFIG_ARCH_R8A7742 is not set
-# CONFIG_ARCH_R8A7743 is not set
-# CONFIG_ARCH_R8A7744 is not set
-# CONFIG_ARCH_R9A06G032 is not set
-# CONFIG_ARCH_SH73A0 is not set
-CONFIG_ROCKCHIP_GRF=y
-# CONFIG_ROCKCHIP_IODOMAIN is not set
-# CONFIG_ROCKCHIP_PM_DOMAINS is not set
-CONFIG_ROCKCHIP_DTPM=m
-CONFIG_SOC_SAMSUNG=y
-CONFIG_EXYNOS_ASV=y
-CONFIG_EXYNOS_ASV_ARM=y
-CONFIG_EXYNOS_CHIPID=y
-CONFIG_EXYNOS_PMU=y
-CONFIG_EXYNOS_PMU_ARM_DRIVERS=y
-CONFIG_EXYNOS_PM_DOMAINS=y
-# CONFIG_SAMSUNG_PM_CHECK is not set
-CONFIG_EXYNOS_REGULATOR_COUPLER=y
-CONFIG_SUNXI_SRAM=y
-# CONFIG_ARCH_TEGRA_2x_SOC is not set
-# CONFIG_ARCH_TEGRA_3x_SOC is not set
-# CONFIG_ARCH_TEGRA_114_SOC is not set
-# CONFIG_ARCH_TEGRA_124_SOC is not set
-CONFIG_SOC_TEGRA_FUSE=y
-# CONFIG_SOC_TI is not set
-CONFIG_UX500_SOC_ID=y
-CONFIG_SOC_REALVIEW=y
-
-#
-# Xilinx SoC drivers
-#
-# CONFIG_XILINX_VCU is not set
-# end of Xilinx SoC drivers
-
-# CONFIG_SOC_ZTE is not set
-# end of SOC (System On Chip) specific Drivers
-
-CONFIG_PM_DEVFREQ=y
-
-#
-# DEVFREQ Governors
-#
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_PERFORMANCE=y
-CONFIG_DEVFREQ_GOV_POWERSAVE=y
-CONFIG_DEVFREQ_GOV_USERSPACE=y
-CONFIG_DEVFREQ_GOV_PASSIVE=m
-
-#
-# DEVFREQ Drivers
-#
-# CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set
-# CONFIG_ARM_IMX_BUS_DEVFREQ is not set
-# CONFIG_ARM_IMX8M_DDRC_DEVFREQ is not set
-# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
-CONFIG_PM_DEVFREQ_EVENT=y
-# CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP is not set
-# CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU is not set
-# CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI is not set
-CONFIG_EXTCON=y
-
-#
-# Extcon Device Drivers
-#
-CONFIG_EXTCON_ADC_JACK=m
-CONFIG_EXTCON_ARIZONA=m
-CONFIG_EXTCON_FSA9480=m
-CONFIG_EXTCON_GPIO=m
-CONFIG_EXTCON_MAX14577=m
-CONFIG_EXTCON_MAX3355=m
-CONFIG_EXTCON_MAX77693=m
-CONFIG_EXTCON_PTN5150=m
-# CONFIG_EXTCON_QCOM_SPMI_MISC is not set
-CONFIG_EXTCON_RT8973A=m
-CONFIG_EXTCON_SM5502=m
-CONFIG_EXTCON_USB_GPIO=m
-CONFIG_EXTCON_USBC_CROS_EC=m
-CONFIG_EXTCON_USBC_TUSB320=m
-CONFIG_MEMORY=y
-# CONFIG_ARM_PL172_MPMC is not set
-CONFIG_ATMEL_SDRAMC=y
-CONFIG_ATMEL_EBI=y
-# CONFIG_TI_AEMIF is not set
-# CONFIG_TI_EMIF is not set
-CONFIG_OMAP_GPMC=y
-# CONFIG_OMAP_GPMC_DEBUG is not set
-# CONFIG_TI_EMIF_SRAM is not set
-CONFIG_FPGA_DFL_EMIF=m
-CONFIG_MVEBU_DEVBUS=y
-CONFIG_PL353_SMC=y
-CONFIG_RENESAS_RPCIF=m
-CONFIG_STM32_FMC2_EBI=m
-CONFIG_SAMSUNG_MC=y
-# CONFIG_EXYNOS5422_DMC is not set
-CONFIG_EXYNOS_SROM=y
-CONFIG_TEGRA_MC=y
-CONFIG_IIO=m
-CONFIG_IIO_BUFFER=y
+CONFIG_HI6421V600_IRQ=m
+CONFIG_HI8435=m
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION_COMP_LZO=y
+CONFIG_HIBERNATION_SNAPSHOT_DEV=y
+CONFIG_HIBERNATION=y
+CONFIG_HID_LETSKETCH=m
+CONFIG_HID_MEGAWORLD_FF=m
+CONFIG_HID_NINTENDO=m
+CONFIG_HID_SENSOR_ACCEL_3D=m
+CONFIG_HID_SENSOR_ALS=m
+CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
+CONFIG_HID_SENSOR_DEVICE_ROTATION=m
+CONFIG_HID_SENSOR_GYRO_3D=m
+CONFIG_HID_SENSOR_HUMIDITY=m
+CONFIG_HID_SENSOR_IIO_COMMON=m
+CONFIG_HID_SENSOR_IIO_TRIGGER=m
+CONFIG_HID_SENSOR_INCLINOMETER_3D=m
+CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
+CONFIG_HID_SENSOR_PRESS=m
+CONFIG_HID_SENSOR_PROX=m
+CONFIG_HID_SENSOR_TEMP=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID_XIAOMI=m
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HISI_ACC_VFIO_PCI=m
+CONFIG_HISI_DMA=m
+CONFIG_HISI_HIKEY_USB=m
+CONFIG_HISI_PTT=m
+CONFIG_HISI_THERMAL=y
+CONFIG_HMC425=m
+CONFIG_HMC6352=m
+CONFIG_HMM_MIRROR=y
+CONFIG_HOSTAP_CS=m
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_PCI=m
+CONFIG_HOSTAP_PLX=m
+CONFIG_HOTPLUG_PCI_CPCI=y
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_HOTPLUG_PCI_SHPC=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HP03=m
+CONFIG_HP206C=m
+CONFIG_HP_ILO=m
+CONFIG_HP_WATCHDOG=m
+CONFIG_HSC030PA=m
+CONFIG_HSI_BOARDINFO=y
+CONFIG_HSI_CHAR=m
+CONFIG_HSI=m
+CONFIG_HTC_EGPIO=y
+CONFIG_HTC_PASIC3=m
+CONFIG_HTE=y
+CONFIG_HTS221_I2C=m
+CONFIG_HTS221=m
+CONFIG_HTS221_SPI=m
+CONFIG_HTU21=m
+CONFIG_HVC_DCC=y
+CONFIG_HWMON_VID=m
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
+CONFIG_HW_RANDOM_ATMEL=y
+CONFIG_HW_RANDOM_BA431=y
+CONFIG_HW_RANDOM_BCM2835=m
+CONFIG_HW_RANDOM_CN10K=m
+CONFIG_HW_RANDOM_EXYNOS=y
+CONFIG_HW_RANDOM_HISI=y
+CONFIG_HW_RANDOM_HISTB=m
+CONFIG_HW_RANDOM_KEYSTONE=y
+CONFIG_HW_RANDOM_MESON=y
+CONFIG_HW_RANDOM_MTK=y
+CONFIG_HW_RANDOM_NPCM=y
+CONFIG_HW_RANDOM_OMAP3_ROM=y
+CONFIG_HW_RANDOM_OMAP=y
+CONFIG_HW_RANDOM_ROCKCHIP=m
+CONFIG_HW_RANDOM_STM32=y
+CONFIG_HW_RANDOM_TIMERIOMEM=y
+CONFIG_HW_RANDOM_TPM=y
+CONFIG_HW_RANDOM_XIPHERA=y
+CONFIG_HW_RANDOM=y
+CONFIG_HWSPINLOCK_SUN6I=m
+CONFIG_HWSPINLOCK=y
+CONFIG_HX711=m
+CONFIG_HX9023S=m
+CONFIG_HZ=300
+CONFIG_HZ_300=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C_ALGOBIT=m
+CONFIG_I2C_ALGOPCA=m
+CONFIG_I2C_ALI1535=m
+CONFIG_I2C_ALI1563=m
+CONFIG_I2C_ALI15X3=m
+CONFIG_I2C_ALTERA=m
+CONFIG_I2C_AMD756=m
+CONFIG_I2C_AMD8111=m
+CONFIG_I2C_APPLE=m
+CONFIG_I2C_ATR=m
+CONFIG_I2C_BRCMSTB=m
+CONFIG_I2C_CBUS_GPIO=m
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_CP2615=m
+CONFIG_I2C_CROS_EC_TUNNEL=m
+CONFIG_I2C_DESIGNWARE_AMDPSP=y
+CONFIG_I2C_DESIGNWARE_CORE=m
+CONFIG_I2C_DESIGNWARE_PCI=m
+CONFIG_I2C_DESIGNWARE_PLATFORM=m
+CONFIG_I2C_DIOLAN_U2C=m
+CONFIG_I2C_DLN2=m
+CONFIG_I2C_EMEV2=m
+CONFIG_I2C_EXYNOS5=y
+CONFIG_I2C_GPIO=m
+CONFIG_I2C_GXP=m
+CONFIG_I2C_HID=m
+CONFIG_I2C_HID_OF_ELAN=m
+CONFIG_I2C_HISI=m
+CONFIG_I2C_I801=m
+CONFIG_I2C_ISCH=m
+CONFIG_I2C_KEMPLD=m
+CONFIG_I2C_LJCA=m
+CONFIG_I2C_MLXCPLD=m
+CONFIG_I2C_MUX_GPIO=m
+CONFIG_I2C_MUX_LTC4306=m
+CONFIG_I2C_MUX=m
+CONFIG_I2C_MUX_MLXCPLD=m
+CONFIG_I2C_MUX_MULE=m
+CONFIG_I2C_MUX_PCA9541=m
+CONFIG_I2C_MUX_PCA954x=m
+CONFIG_I2C_MUX_REG=m
+CONFIG_I2C_NCT6694=m
+CONFIG_I2C_NFORCE2=m
+CONFIG_I2C_NOMADIK=y
+CONFIG_I2C_NPCM=m
+CONFIG_I2C_NVIDIA_GPU=m
+CONFIG_I2C_OCORES=m
+CONFIG_I2C_OMAP=y
+CONFIG_I2C_PARPORT=m
+CONFIG_I2C_PCA_PLATFORM=m
+CONFIG_I2C_PCI1XXXX=m
+CONFIG_I2C_PIIX4=m
+CONFIG_I2C_ROBOTFUZZ_OSIF=m
+CONFIG_I2C_RZV2M=m
+CONFIG_I2C_S3C2410=m
+CONFIG_I2C_SI470X=m
+CONFIG_I2C_SI4713=m
+CONFIG_I2C_SIMTEC=m
+CONFIG_I2C_SIS5595=m
+CONFIG_I2C_SIS630=m
+CONFIG_I2C_SIS96X=m
+CONFIG_I2C_SLAVE_EEPROM=m
+CONFIG_I2C_SLAVE_TESTUNIT=m
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SMBUS=m
+CONFIG_I2C_TAOS_EVM=m
+CONFIG_I2C_TINY_USB=m
+CONFIG_I2C_VIA=m
+CONFIG_I2C_VIAPRO=m
+CONFIG_I2C_VIPERBOARD=m
+CONFIG_I2C_VIRTIO=m
+CONFIG_I2C_XILINX=m
+CONFIG_I2C=y
+CONFIG_I2C_ZX2967=y
+CONFIG_I3C=m
+CONFIG_I6300ESB_WDT=m
+CONFIG_I82092=m
+CONFIG_IAQCORE=m
+CONFIG_ICE_HWTS=y
+CONFIG_ICE_SWITCHDEV=y
+CONFIG_ICP10100=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_ICS932S401=m
+CONFIG_ICST=y
+CONFIG_IFB=m
+CONFIG_IFCVF=m
+CONFIG_IIO_ADIS_LIB_BUFFER=y
+CONFIG_IIO_ADIS_LIB=m
 CONFIG_IIO_BUFFER_CB=m
-CONFIG_IIO_BUFFER_DMA=m
 CONFIG_IIO_BUFFER_DMAENGINE=m
+CONFIG_IIO_BUFFER_DMA=m
 CONFIG_IIO_BUFFER_HW_CONSUMER=m
-CONFIG_IIO_KFIFO_BUF=m
-CONFIG_IIO_TRIGGERED_BUFFER=m
+CONFIG_IIO_BUFFER=y
 CONFIG_IIO_CONFIGFS=m
-CONFIG_IIO_TRIGGER=y
 CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
-CONFIG_IIO_SW_DEVICE=m
-CONFIG_IIO_SW_TRIGGER=m
-CONFIG_IIO_TRIGGERED_EVENT=m
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16201=m
-CONFIG_ADIS16209=m
-CONFIG_ADXL372=m
-CONFIG_ADXL372_SPI=m
-CONFIG_ADXL372_I2C=m
-CONFIG_BMA220=m
-CONFIG_BMA400=m
-CONFIG_BMA400_I2C=m
-CONFIG_BMA400_SPI=m
-CONFIG_BMC150_ACCEL=m
-CONFIG_BMI088_ACCEL=m
-CONFIG_BMC150_ACCEL_I2C=m
-CONFIG_BMC150_ACCEL_SPI=m
-CONFIG_DA280=m
-CONFIG_DA311=m
-# CONFIG_DMARD06 is not set
-CONFIG_DMARD09=m
-CONFIG_DMARD10=m
-CONFIG_FXLS8962AF_SPI=m
-CONFIG_FXLS8962AF_I2C=m
-CONFIG_HID_SENSOR_ACCEL_3D=m
 CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
-CONFIG_IIO_ST_ACCEL_3AXIS=m
-CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
-CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
-CONFIG_KXSD9=m
-CONFIG_KXSD9_SPI=m
-CONFIG_KXSD9_I2C=m
-CONFIG_KXCJK1013=m
-CONFIG_MC3230=m
-CONFIG_MMA7455=m
-CONFIG_MMA7455_I2C=m
-CONFIG_MMA7455_SPI=m
-CONFIG_MMA7660=m
-CONFIG_MMA8452=m
-CONFIG_MMA9551_CORE=m
-CONFIG_MMA9551=m
-CONFIG_MMA9553=m
-CONFIG_MSA311=m
-CONFIG_MXC4005=m
-CONFIG_MXC6255=m
-CONFIG_SCA3000=m
-CONFIG_SCA3300=m
-CONFIG_STK8312=m
-CONFIG_STK8BA50=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD_SIGMA_DELTA=m
-CONFIG_AD7091R5=m
-CONFIG_AD7124=m
-CONFIG_AD7192=m
-CONFIG_AD7266=m
-CONFIG_AD7291=m
-CONFIG_AD7292=m
-CONFIG_AD7298=m
-CONFIG_AD7476=m
-CONFIG_AD7606=m
-CONFIG_AD7606_IFACE_PARALLEL=m
-CONFIG_AD7606_IFACE_SPI=m
-CONFIG_AD7766=m
-CONFIG_AD7768_1=m
-CONFIG_AD7780=m
-CONFIG_AD7791=m
-CONFIG_AD7793=m
-CONFIG_AD7887=m
-CONFIG_AD7923=m
-CONFIG_AD7949=m
-CONFIG_AD799X=m
-CONFIG_AD9467=m
-CONFIG_ADI_AXI_ADC=m
-# CONFIG_ASPEED_ADC is not set
-# CONFIG_AT91_ADC is not set
-# CONFIG_AT91_SAMA5D2_ADC is not set
-CONFIG_AXP20X_ADC=m
-CONFIG_AXP288_ADC=m
-# CONFIG_BERLIN2_ADC is not set
-CONFIG_CC10001_ADC=m
-# CONFIG_CPCAP_ADC is not set
-CONFIG_DA9150_GPADC=m
-CONFIG_DLN2_ADC=m
-# CONFIG_ENVELOPE_DETECTOR is not set
-# CONFIG_EXYNOS_ADC is not set
-CONFIG_HI8435=m
-CONFIG_HX711=m
-CONFIG_INA2XX_ADC=m
-# CONFIG_IMX7D_ADC is not set
-CONFIG_IMX8QXP_ADC=m
-CONFIG_LTC2471=m
-CONFIG_LTC2485=m
-CONFIG_LTC2496=m
-CONFIG_LTC2497=m
-CONFIG_MAX1027=m
-CONFIG_MAX11100=m
-CONFIG_MAX1118=m
-CONFIG_MAX11205=m
-CONFIG_MAX1241=m
-CONFIG_MAX1363=m
-CONFIG_MAX9611=m
-CONFIG_MCP320X=m
-CONFIG_MCP3422=m
-CONFIG_MCP3911=m
-CONFIG_MEDIATEK_MT6360_ADC=m
-# CONFIG_MEDIATEK_MT6577_AUXADC is not set
-CONFIG_MEN_Z188_ADC=m
-CONFIG_MESON_SARADC=m
-CONFIG_MP2629_ADC=m
-CONFIG_NAU7802=m
-# CONFIG_NPCM_ADC is not set
-CONFIG_QCOM_VADC_COMMON=m
-# CONFIG_QCOM_PM8XXX_XOADC is not set
-CONFIG_QCOM_SPMI_IADC=m
-CONFIG_QCOM_SPMI_VADC=m
-CONFIG_QCOM_SPMI_ADC5=m
-# CONFIG_RN5T618_ADC is not set
-# CONFIG_ROCKCHIP_SARADC is not set
-CONFIG_RICHTEK_RTQ6056=m
-# CONFIG_SPEAR_ADC is not set
-# CONFIG_SD_ADC_MODULATOR is not set
-# CONFIG_STM32_ADC_CORE is not set
-# CONFIG_STM32_DFSDM_CORE is not set
-# CONFIG_STM32_DFSDM_ADC is not set
-# CONFIG_STMPE_ADC is not set
-# CONFIG_SUN4I_GPADC is not set
-CONFIG_TI_ADC081C=m
-CONFIG_TI_ADC0832=m
-CONFIG_TI_ADC084S021=m
-CONFIG_TI_ADC12138=m
-CONFIG_TI_ADC108S102=m
-CONFIG_TI_ADC128S052=m
-CONFIG_TI_ADC161S626=m
-CONFIG_TI_ADS1015=m
-CONFIG_TI_ADS7950=m
-CONFIG_TI_ADS8344=m
-# CONFIG_TI_ADS8688 is not set
-# CONFIG_TI_ADS124S08 is not set
-CONFIG_TI_ADS131E08=m
-CONFIG_TI_AM335X_ADC=m
-CONFIG_TI_TLC4541=m
-CONFIG_TI_TSC2046=m
-# CONFIG_TWL4030_MADC is not set
-# CONFIG_TWL6030_GPADC is not set
-# CONFIG_VF610_ADC is not set
-CONFIG_VIPERBOARD_ADC=m
-CONFIG_XILINX_XADC=m
-CONFIG_XILINX_AMS=m
-CONFIG_IIO_SCMI=m
-CONFIG_CROS_EC_MKBP_PROXIMITY=m
-# end of Analog to digital converters
-
-#
-# Analog Front Ends
-#
-# CONFIG_IIO_RESCALE is not set
-# end of Analog Front Ends
-
-#
-# Amplifiers
-#
-CONFIG_AD8366=m
-CONFIG_ADA4250=m
-CONFIG_HMC425=m
-# end of Amplifiers
-
-#
-# Chemical Sensors
-#
-CONFIG_ATLAS_PH_SENSOR=m
-CONFIG_ATLAS_EZO_SENSOR=m
-CONFIG_BME680=m
-CONFIG_BME680_I2C=m
-CONFIG_BME680_SPI=m
-CONFIG_CCS811=m
-CONFIG_IAQCORE=m
-CONFIG_PMS7003=m
-CONFIG_SCD30_CORE=m
-CONFIG_SCD30_I2C=m
-CONFIG_SCD30_SERIAL=m
-CONFIG_SENSIRION_SGP30=m
-CONFIG_SPS30_I2C=m
-CONFIG_SPS30_SERIAL=m
-CONFIG_SPS30=m
-CONFIG_VZ89X=m
-# end of Chemical Sensors
-
+CONFIG_IIO_CROS_EC_ACTIVITY=m
+CONFIG_IIO_CROS_EC_BARO=m
+CONFIG_IIO_CROS_EC_LIGHT_PROX=m
 CONFIG_IIO_CROS_EC_SENSORS_CORE=m
-CONFIG_IIO_CROS_EC_SENSORS=m
-CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m
-
-#
-# Hid Sensor IIO Common
-#
-CONFIG_HID_SENSOR_IIO_COMMON=m
-CONFIG_HID_SENSOR_IIO_TRIGGER=m
-# end of Hid Sensor IIO Common
-
+CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m
+CONFIG_IIO_CROS_EC_SENSORS=m
+CONFIG_IIO_HRTIMER_TRIGGER=m
+CONFIG_IIO_INTERRUPT_TRIGGER=m
+CONFIG_IIO_KFIFO_BUF=m
+CONFIG_IIO_KX022A_I2C=m
+CONFIG_IIO_KX022A_SPI=m
+CONFIG_IIO=m
 CONFIG_IIO_MS_SENSORS_I2C=m
-
-#
-# SSP Sensor Common
-#
-CONFIG_IIO_SSP_SENSORS_COMMONS=m
+CONFIG_IIO_SCMI=m
 CONFIG_IIO_SSP_SENSORHUB=m
-# end of SSP Sensor Common
-
-CONFIG_IIO_ST_SENSORS_I2C=m
-CONFIG_IIO_ST_SENSORS_SPI=m
-CONFIG_IIO_ST_SENSORS_CORE=m
-
-#
-# Digital to analog converters
-#
-CONFIG_AD5064=m
-CONFIG_AD5360=m
-CONFIG_AD5380=m
-CONFIG_AD5421=m
-CONFIG_AD5446=m
-CONFIG_AD5449=m
-CONFIG_AD5592R_BASE=m
-CONFIG_AD5592R=m
-CONFIG_AD5593R=m
-CONFIG_AD5504=m
-CONFIG_AD5624R_SPI=m
-CONFIG_LTC2688=m
-CONFIG_AD5686=m
-CONFIG_AD5686_SPI=m
-CONFIG_AD5696_I2C=m
-CONFIG_AD5755=m
-CONFIG_AD5758=m
-CONFIG_AD5761=m
-CONFIG_AD5764=m
-CONFIG_AD5766=m
-CONFIG_AD5770R=m
-CONFIG_AD5791=m
-CONFIG_AD7303=m
-CONFIG_AD8801=m
-# CONFIG_DPOT_DAC is not set
-CONFIG_DS4424=m
-CONFIG_LTC1660=m
-CONFIG_LTC2632=m
-CONFIG_M62332=m
-CONFIG_MAX517=m
-# CONFIG_MAX5821 is not set
-CONFIG_MCP4725=m
-CONFIG_MCP4922=m
-# CONFIG_STM32_DAC is not set
-CONFIG_TI_DAC082S085=m
-CONFIG_TI_DAC5571=m
-CONFIG_TI_DAC7311=m
-CONFIG_TI_DAC7612=m
-# CONFIG_VF610_DAC is not set
-# end of Digital to analog converters
-
-#
-# IIO dummy driver
-#
-# CONFIG_IIO_SIMPLE_DUMMY is not set
-# end of IIO dummy driver
-
-#
-# Frequency Synthesizers DDS/PLL
-#
-
-#
-# Clock Generator/Distribution
-#
-CONFIG_AD9523=m
-# end of Clock Generator/Distribution
-
-#
-# Phase-Locked Loop (PLL) frequency synthesizers
-#
-CONFIG_ADF4350=m
-CONFIG_ADF4371=m
-# end of Phase-Locked Loop (PLL) frequency synthesizers
-# end of Frequency Synthesizers DDS/PLL
-
-#
-# Digital gyroscope sensors
-#
-CONFIG_ADIS16080=m
-CONFIG_ADIS16130=m
-CONFIG_ADIS16136=m
-CONFIG_ADIS16260=m
-CONFIG_ADXRS290=m
-CONFIG_ADXRS450=m
-CONFIG_BMG160=m
-CONFIG_BMG160_I2C=m
-CONFIG_BMG160_SPI=m
-CONFIG_FXAS21002C=m
-CONFIG_FXAS21002C_I2C=m
-CONFIG_FXAS21002C_SPI=m
-CONFIG_HID_SENSOR_GYRO_3D=m
-CONFIG_MPU3050=m
-CONFIG_MPU3050_I2C=m
+CONFIG_IIO_SSP_SENSORS_COMMONS=m
+CONFIG_IIO_ST_ACCEL_3AXIS=m
+CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
+CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
 CONFIG_IIO_ST_GYRO_3AXIS=m
 CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
 CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
-CONFIG_ITG3200=m
-# end of Digital gyroscope sensors
-
-#
-# Health Sensors
-#
-
-#
-# Heart Rate Monitors
-#
-CONFIG_AFE4403=m
-CONFIG_AFE4404=m
-CONFIG_MAX30100=m
-CONFIG_MAX30102=m
-# end of Heart Rate Monitors
-# end of Health Sensors
-
-#
-# Humidity sensors
-#
-CONFIG_AM2315=m
-CONFIG_DHT11=m
-CONFIG_HDC100X=m
-CONFIG_HDC2010=m
-CONFIG_HID_SENSOR_HUMIDITY=m
-CONFIG_HTS221=m
-CONFIG_HTS221_I2C=m
-CONFIG_HTS221_SPI=m
-CONFIG_HTU21=m
-CONFIG_SI7005=m
-CONFIG_SI7020=m
-# end of Humidity sensors
-
-#
-# Inertial measurement units
-#
-CONFIG_ADIS16400=m
-CONFIG_ADIS16460=m
-CONFIG_ADIS16475=m
-CONFIG_ADIS16480=m
-CONFIG_BMI160=m
-CONFIG_BMI160_I2C=m
-CONFIG_BMI160_SPI=m
-CONFIG_BOSCH_BNO055_SERIAL=m
-CONFIG_BOSCH_BNO055_I2C=m
-CONFIG_FXOS8700=m
-CONFIG_FXOS8700_I2C=m
-CONFIG_FXOS8700_SPI=m
-CONFIG_KMX61=m
-CONFIG_INV_ICM42600=m
-CONFIG_INV_ICM42600_I2C=m
-CONFIG_INV_ICM42600_SPI=m
-CONFIG_INV_MPU6050_IIO=m
-CONFIG_INV_MPU6050_I2C=m
-CONFIG_INV_MPU6050_SPI=m
+CONFIG_IIO_ST_LSM6DSX_I2C=m
+CONFIG_IIO_ST_LSM6DSX_I3C=m
 CONFIG_IIO_ST_LSM6DSX=m
-CONFIG_IIO_ST_LSM9DS0=m
+CONFIG_IIO_ST_LSM6DSX_SPI=m
 CONFIG_IIO_ST_LSM9DS0_I2C=m
+CONFIG_IIO_ST_LSM9DS0=m
 CONFIG_IIO_ST_LSM9DS0_SPI=m
-CONFIG_IIO_ST_LSM6DSX_I2C=m
-CONFIG_IIO_ST_LSM6DSX_SPI=m
-CONFIG_IIO_ST_LSM6DSX_I3C=m
-# end of Inertial measurement units
-
-CONFIG_IIO_ADIS_LIB=m
-CONFIG_IIO_ADIS_LIB_BUFFER=y
-
-#
-# Light sensors
-#
-CONFIG_ADJD_S311=m
-CONFIG_ADUX1020=m
-CONFIG_AL3010=m
-CONFIG_AL3320A=m
-CONFIG_APDS9300=m
-CONFIG_APDS9960=m
-CONFIG_AS73211=m
-CONFIG_BH1750=m
-CONFIG_BH1780=m
-CONFIG_CM32181=m
-CONFIG_CM3232=m
-CONFIG_CM3323=m
-# CONFIG_CM3605 is not set
-CONFIG_CM36651=m
-CONFIG_IIO_CROS_EC_LIGHT_PROX=m
-CONFIG_GP2AP002=m
-CONFIG_GP2AP020A00F=m
+CONFIG_IIO_ST_MAGN_3AXIS=m
+CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
+CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
+CONFIG_IIO_ST_PRESS_I2C=m
+CONFIG_IIO_ST_PRESS=m
+CONFIG_IIO_ST_PRESS_SPI=m
+CONFIG_IIO_ST_SENSORS_CORE=m
+CONFIG_IIO_ST_SENSORS_I2C=m
+CONFIG_IIO_ST_SENSORS_SPI=m
+CONFIG_IIO_SW_DEVICE=m
+CONFIG_IIO_SW_TRIGGER=m
+CONFIG_IIO_SYSFS_TRIGGER=m
+CONFIG_IIO_TIGHTLOOP_TRIGGER=m
+CONFIG_IIO_TRIGGERED_BUFFER=m
+CONFIG_IIO_TRIGGERED_EVENT=m
+CONFIG_IIO_TRIGGER=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
+CONFIG_IMG_ASCII_LCD=m
+CONFIG_IMX8QXP_ADC=m
+CONFIG_IMX93_ADC=m
+CONFIG_IMX_AIPSTZ=m
+CONFIG_IMX_INTMUX=y
+CONFIG_IMX_IPUV3_CORE=m
+CONFIG_IMX_IRQSTEER=y
+CONFIG_IMX_MU_MSI=m
+CONFIG_IMX_SCMI_BBM_EXT=m
+CONFIG_IMX_SCMI_CPU_DRV=m
+CONFIG_IMX_SCMI_CPU_EXT=m
+CONFIG_IMX_SCMI_LMM_DRV=m
+CONFIG_IMX_SCMI_LMM_EXT=m
+CONFIG_IMX_SCMI_MISC_DRV=m
+CONFIG_IMX_SCMI_MISC_EXT=m
+CONFIG_INA2XX_ADC=m
+CONFIG_INFINEON_TLV493D=m
+CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
+CONFIG_INFINIBAND_ADDR_TRANS=y
+CONFIG_INFINIBAND_CXGB4=m
+CONFIG_INFINIBAND_I40IW=m
+CONFIG_INFINIBAND_IPOIB_CM=y
+CONFIG_INFINIBAND_IPOIB=m
+CONFIG_INFINIBAND_IRDMA=m
+CONFIG_INFINIBAND_ISER=m
+CONFIG_INFINIBAND_ISERT=m
+CONFIG_INFINIBAND=m
+CONFIG_INFINIBAND_MTHCA=m
+CONFIG_INFINIBAND_OCRDMA=m
+CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
+CONFIG_INFINIBAND_QEDR=m
+CONFIG_INFINIBAND_RTRS_CLIENT=m
+CONFIG_INFINIBAND_RTRS=m
+CONFIG_INFINIBAND_RTRS_SERVER=m
+CONFIG_INFINIBAND_SRP=m
+CONFIG_INFINIBAND_SRPT=m
+CONFIG_INFINIBAND_USER_ACCESS=m
+CONFIG_INFINIBAND_USER_MAD=m
+CONFIG_INFINIBAND_USER_MEM=y
+CONFIG_INFINIBAND_VMWARE_PVRDMA=m
+CONFIG_INFTL=m
+CONFIG_INIT_STACK_NONE=y
+CONFIG_INPUT_88PM80X_ONKEY=m
+CONFIG_INPUT_AD714X_I2C=m
+CONFIG_INPUT_AD714X=m
+CONFIG_INPUT_AD714X_SPI=m
+CONFIG_INPUT_ADXL34X_I2C=m
+CONFIG_INPUT_ADXL34X=m
+CONFIG_INPUT_ADXL34X_SPI=m
+CONFIG_INPUT_ARIZONA_HAPTICS=m
+CONFIG_INPUT_ATC260X_ONKEY=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_ATMEL_CAPTOUCH=m
+CONFIG_INPUT_AW86927=m
+CONFIG_INPUT_AXP20X_PEK=m
+CONFIG_INPUT_BBNSM_PWRKEY=m
+CONFIG_INPUT_BMA150=m
+CONFIG_INPUT_CM109=m
+CONFIG_INPUT_CMA3000_I2C=m
+CONFIG_INPUT_CMA3000=m
+CONFIG_INPUT_CS40L50_VIBRA=m
+CONFIG_INPUT_DA7280_HAPTICS=m
+CONFIG_INPUT_DA9052_ONKEY=m
+CONFIG_INPUT_DA9063_ONKEY=m
+CONFIG_INPUT_DRV260X_HAPTICS=m
+CONFIG_INPUT_DRV2665_HAPTICS=m
+CONFIG_INPUT_DRV2667_HAPTICS=m
+CONFIG_INPUT_E3X0_BUTTON=m
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_GPIO_BEEPER=m
+CONFIG_INPUT_GPIO_DECODER=m
+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
+CONFIG_INPUT_GPIO_VIBRA=m
+CONFIG_INPUT_IBM_PANEL=m
+CONFIG_INPUT_IMS_PCU=m
+CONFIG_INPUT_IQS269A=m
+CONFIG_INPUT_IQS626A=m
+CONFIG_INPUT_IQS7222=m
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_KXTJ9=m
+CONFIG_INPUT_LEDS=m
+CONFIG_INPUT_MATRIXKMAP=m
+CONFIG_INPUT_MAX7360_ROTARY=m
+CONFIG_INPUT_MAX77693_HAPTIC=m
+CONFIG_INPUT_MC13783_PWRBUTTON=m
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MMA8450=m
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_PCAP=m
+CONFIG_INPUT_PCF50633_PMU=m
+CONFIG_INPUT_PCF8574=m
+CONFIG_INPUT_POLLDEV=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_PWM_BEEPER=m
+CONFIG_INPUT_PWM_VIBRA=m
+CONFIG_INPUT_QNAP_MCU=m
+CONFIG_INPUT_RAVE_SP_PWRBUTTON=m
+CONFIG_INPUT_REGULATOR_HAPTIC=m
+CONFIG_INPUT_RETU_PWRBUTTON=m
+CONFIG_INPUT_RT5120_PWRKEY=m
+CONFIG_INPUT_SIRFSOC_ONKEY=y
+CONFIG_INPUT_SPARSEKMAP=m
+CONFIG_INPUT_TABLET=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_TPS65219_PWRBUTTON=m
+CONFIG_INPUT_TPS6594_PWRBUTTON=m
+CONFIG_INPUT_UINPUT=m
+CONFIG_INPUT_WM831X_ON=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INTEL_QEP=m
+CONFIG_INTEL_XWAY_PHY=m
+CONFIG_INTERCONNECT_EXYNOS=m
+CONFIG_INTERCONNECT_IMX8MM=m
+CONFIG_INTERCONNECT_IMX8MN=m
+CONFIG_INTERCONNECT_IMX8MP=m
+CONFIG_INTERCONNECT_IMX8MQ=m
+CONFIG_INTERCONNECT_IMX=m
+CONFIG_INTERCONNECT_MTK=y
+CONFIG_INTERCONNECT_QCOM_OSM_L3=m
+CONFIG_INTERCONNECT_QCOM_QCM2290=m
+CONFIG_INTERCONNECT_QCOM_QDU1000=m
+CONFIG_INTERCONNECT_QCOM_SA8775P=m
+CONFIG_INTERCONNECT_QCOM_SDM670=m
+CONFIG_INTERCONNECT_QCOM_SM8550=m
+CONFIG_INTERCONNECT_QCOM=y
+CONFIG_INTERCONNECT_SAMSUNG=y
+CONFIG_INTERCONNECT=y
+CONFIG_INTERRUPT_CNT=m
+CONFIG_INV_ICM42600_I2C=m
+CONFIG_INV_ICM42600=m
+CONFIG_INV_ICM42600_SPI=m
+CONFIG_INV_MPU6050_I2C=m
+CONFIG_INV_MPU6050_IIO=m
+CONFIG_INV_MPU6050_SPI=m
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+CONFIG_IOMMUFD=m
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+CONFIG_IOMMU_IO_PGTABLE=y
+CONFIG_IOSCHED_BFQ=y
+CONFIG_IOSM=m
+CONFIG_IP5XXX_POWER=m
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_HANDLER=m
+CONFIG_IPMI_IPMB=m
+CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m
+CONFIG_IPMI_KCS_BMC_SERIO=m
+CONFIG_IPMI_PANIC_EVENT=y
+CONFIG_IPMI_PANIC_STRING=y
+CONFIG_IPMI_PLAT_DATA=y
+CONFIG_IPMI_POWEROFF=m
+CONFIG_IPMI_SI=m
+CONFIG_IPMI_SSIF=m
+CONFIG_IPMI_WATCHDOG=m
+CONFIG_IPU_BRIDGE=m
+CONFIG_IPV6_IOAM6_LWTUNNEL=y
+CONFIG_IPVLAN_L3S=y
+CONFIG_IPVLAN=m
+CONFIG_IPVTAP=m
+CONFIG_IPW2100=m
+CONFIG_IPW2100_MONITOR=y
+CONFIG_IPW2200=m
+CONFIG_IPW2200_MONITOR=y
+CONFIG_IPW2200_PROMISCUOUS=y
+CONFIG_IPW2200_QOS=y
+CONFIG_IPW2200_RADIOTAP=y
+CONFIG_IPWIRELESS=m
+CONFIG_IQS620AT_TEMP=m
 CONFIG_IQS621_ALS=m
-CONFIG_SENSORS_ISL29018=m
-CONFIG_SENSORS_ISL29028=m
+CONFIG_IQS624_POS=m
+CONFIG_IR_GPIO_CIR=m
+CONFIG_IR_GPIO_TX=m
+CONFIG_IR_HIX5HD2=m
+CONFIG_IR_IGORPLUGUSB=m
+CONFIG_IR_IGUANA=m
+CONFIG_IR_IMON_DECODER=m
+CONFIG_IR_IMON=m
+CONFIG_IR_IMON_RAW=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_IR_MCEUSB=m
+CONFIG_IR_MESON_TX=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_PWM_TX=m
+CONFIG_IRQ_BYPASS_MANAGER=m
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_CROSSBAR=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
+CONFIG_IRQ_POLL=y
+CONFIG_IRQ_SIM=y
+CONFIG_IRQ_UNIPHIER_AIDET=y
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_RCMM_DECODER=m
+CONFIG_IR_REDRAT3=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IRSD200=m
+CONFIG_IR_SERIAL=m
+CONFIG_IR_SERIAL_TRANSMITTER=y
+CONFIG_IR_SHARP_DECODER=m
+CONFIG_IR_SIR=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_SPI=m
+CONFIG_IR_STREAMZAP=m
+CONFIG_IR_TOY=m
+CONFIG_IR_TTUSBIR=m
+CONFIG_IR_XMP_DECODER=m
+CONFIG_ISCSI_BOOT_SYSFS=m
+CONFIG_ISCSI_TARGET_CXGB4=m
+CONFIG_ISCSI_TARGET=m
+CONFIG_ISCSI_TCP=m
+CONFIG_ISDN_CAPI_MIDDLEWARE=m
+CONFIG_ISDN=y
+CONFIG_ISI=m
+CONFIG_ISL29003=m
+CONFIG_ISL29020=m
 CONFIG_ISL29125=m
-CONFIG_HID_SENSOR_ALS=m
-CONFIG_HID_SENSOR_PROX=m
+CONFIG_ISL29501=m
+CONFIG_ISL76682=m
+CONFIG_ITG3200=m
+CONFIG_IWL3945=m
+CONFIG_IWL4965=m
+CONFIG_IWLDVM=m
+CONFIG_IWLEGACY=m
+CONFIG_IWLMEI=m
+CONFIG_IWLMLD=m
+CONFIG_IWLMVM=m
+CONFIG_IWLWIFI_DEVICE_TRACING=y
+CONFIG_IWLWIFI_LEDS=y
+CONFIG_IWLWIFI=m
+CONFIG_IWLWIFI_OPMODE_MODULAR=y
+CONFIG_JOYSTICK_A3D=m
+CONFIG_JOYSTICK_ADC=m
+CONFIG_JOYSTICK_ADI=m
+CONFIG_JOYSTICK_ANALOG=m
+CONFIG_JOYSTICK_AS5011=m
+CONFIG_JOYSTICK_COBRA=m
+CONFIG_JOYSTICK_DB9=m
+CONFIG_JOYSTICK_FSIA6B=m
+CONFIG_JOYSTICK_GAMECON=m
+CONFIG_JOYSTICK_GF2K=m
+CONFIG_JOYSTICK_GRIP=m
+CONFIG_JOYSTICK_GRIP_MP=m
+CONFIG_JOYSTICK_GUILLEMOT=m
+CONFIG_JOYSTICK_IFORCE_232=m
+CONFIG_JOYSTICK_IFORCE=m
+CONFIG_JOYSTICK_IFORCE_USB=m
+CONFIG_JOYSTICK_INTERACT=m
+CONFIG_JOYSTICK_MAGELLAN=m
+CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
+CONFIG_JOYSTICK_PSXPAD_SPI=m
+CONFIG_JOYSTICK_PXRC=m
+CONFIG_JOYSTICK_QWIIC=m
+CONFIG_JOYSTICK_SEESAW=m
+CONFIG_JOYSTICK_SENSEHAT=m
+CONFIG_JOYSTICK_SIDEWINDER=m
+CONFIG_JOYSTICK_SPACEBALL=m
+CONFIG_JOYSTICK_SPACEORB=m
+CONFIG_JOYSTICK_STINGER=m
+CONFIG_JOYSTICK_TMDC=m
+CONFIG_JOYSTICK_TURBOGRAFX=m
+CONFIG_JOYSTICK_TWIDJOY=m
+CONFIG_JOYSTICK_WALKERA0701=m
+CONFIG_JOYSTICK_WARRIOR=m
+CONFIG_JOYSTICK_XPAD_FF=y
+CONFIG_JOYSTICK_XPAD_LEDS=y
+CONFIG_JOYSTICK_XPAD=m
+CONFIG_JOYSTICK_ZHENHUA=m
 CONFIG_JSA1212=m
-CONFIG_RPR0521=m
-CONFIG_SENSORS_LM3533=m
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KEEMBAY_WATCHDOG=m
+CONFIG_KEMPLD_WDT=m
+CONFIG_KERNEL_GZIP=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_KERNEL_ZSTD=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEXEC=y
+CONFIG_KEYBOARD_ADC=m
+CONFIG_KEYBOARD_ADP5588=m
+CONFIG_KEYBOARD_ADP5589=m
+CONFIG_KEYBOARD_BCM=m
+CONFIG_KEYBOARD_CAP11XX=m
+CONFIG_KEYBOARD_CROS_EC=m
+CONFIG_KEYBOARD_CYPRESS_SF=m
+CONFIG_KEYBOARD_DLINK_DIR685=m
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_KEYBOARD_GPIO_POLLED=m
+CONFIG_KEYBOARD_IMX_BBM_SCMI=m
+CONFIG_KEYBOARD_IQS62X=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_LM8323=m
+CONFIG_KEYBOARD_LM8333=m
+CONFIG_KEYBOARD_MATRIX=m
+CONFIG_KEYBOARD_MAX7359=m
+CONFIG_KEYBOARD_MCS=m
+CONFIG_KEYBOARD_MPR121=m
+CONFIG_KEYBOARD_MT6779=m
+CONFIG_KEYBOARD_MTK_PMIC=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_OMAP4=m
+CONFIG_KEYBOARD_OPENCORES=m
+CONFIG_KEYBOARD_PINEPHONE=m
+CONFIG_KEYBOARD_PXA27x=m
+CONFIG_KEYBOARD_QT1050=m
+CONFIG_KEYBOARD_QT1070=m
+CONFIG_KEYBOARD_QT2160=m
+CONFIG_KEYBOARD_SAMSUNG=m
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_TCA6416=m
+CONFIG_KEYBOARD_TCA8418=m
+CONFIG_KEYBOARD_TM2_TOUCHKEY=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEYSTONE_TIMER=y
+CONFIG_KHADAS_MCU_FAN_THERMAL=m
+CONFIG_KMX61=m
+CONFIG_KPC2000_CORE=m
+CONFIG_KPC2000_DMA=m
+CONFIG_KPC2000_I2C=m
+CONFIG_KPC2000_SPI=m
+CONFIG_KPC2000=y
+CONFIG_KPROBE_EVENT_GEN_TEST=m
+CONFIG_KPROBE_EVENTS=y
+CONFIG_KRETPROBES=y
+CONFIG_KS0108_DELAY=2
+CONFIG_KS0108=m
+CONFIG_KS0108_PORT=0x378
+CONFIG_KS7010=m
+CONFIG_KSM=y
+CONFIG_KUNPENG_HCCS=m
+CONFIG_KUSER_HELPERS=y
+CONFIG_KXCJK1013=m
+CONFIG_KXSD9_I2C=m
+CONFIG_KXSD9=m
+CONFIG_KXSD9_SPI=m
+CONFIG_LAN966X_DCB=y
+CONFIG_LAN966X_SWITCH=m
+CONFIG_LAPBETHER=m
+CONFIG_LATENCYTOP=y
+CONFIG_LATTICE_ECP3_CONFIG=m
+CONFIG_LCD2S=m
+CONFIG_LCD_AMS369FG06=m
+CONFIG_LCD_CLASS_DEVICE=m
+CONFIG_LCD_HX8357=m
+CONFIG_LCD_ILI922X=m
+CONFIG_LCD_ILI9320=m
+CONFIG_LCD_L4F00242T03=m
+CONFIG_LCD_LMS283GF05=m
+CONFIG_LCD_LMS501KF03=m
+CONFIG_LCD_LTV350QV=m
+CONFIG_LCD_OTM3225A=m
+CONFIG_LCD_PLATFORM=m
+CONFIG_LCD_TDO24M=m
+CONFIG_LCD_VGG2432A4=m
+CONFIG_LD_VERSION=235010000
+CONFIG_LEDS_AAT1290=m
+CONFIG_LEDS_AN30259A=m
+CONFIG_LEDS_AS3645A=m
+CONFIG_LEDS_ASIC3=y
+CONFIG_LEDS_AW200XX=m
+CONFIG_LEDS_AW2013=m
+CONFIG_LEDS_BCM63138=m
+CONFIG_LEDS_BCM6328=m
+CONFIG_LEDS_BCM6358=m
+CONFIG_LEDS_BD2606MVV=m
+CONFIG_LEDS_BD2802=m
+CONFIG_LEDS_BLINK_LGM=m
+CONFIG_LEDS_BLINKM=m
+CONFIG_LEDS_BLINK=y
+CONFIG_LEDS_CLASS_FLASH=m
+CONFIG_LEDS_CLASS_MULTICOLOR=m
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CPCAP=m
+CONFIG_LEDS_CR0014114=m
+CONFIG_LEDS_CROS_EC=m
+CONFIG_LEDS_DA9052=m
+CONFIG_LEDS_DAC124S085=m
+CONFIG_LEDS_EL15203000=m
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_GROUP_MULTICOLOR=m
+CONFIG_LEDS_IS31FL319X=m
+CONFIG_LEDS_IS31FL32XX=m
+CONFIG_LEDS_KTD202X=m
+CONFIG_LEDS_KTD2692=m
+CONFIG_LEDS_LM3530=m
+CONFIG_LEDS_LM3532=m
+CONFIG_LEDS_LM3533=m
+CONFIG_LEDS_LM355x=m
+CONFIG_LEDS_LM3601X=m
+CONFIG_LEDS_LM36274=m
+CONFIG_LEDS_LM3642=m
+CONFIG_LEDS_LM3692X=m
+CONFIG_LEDS_LM3697=m
+CONFIG_LEDS_LP3944=m
+CONFIG_LEDS_LP3952=m
+CONFIG_LEDS_LP50XX=m
+CONFIG_LEDS_LP5521=m
+CONFIG_LEDS_LP5523=m
+CONFIG_LEDS_LP5562=m
+CONFIG_LEDS_LP5569=m
+CONFIG_LEDS_LP55XX_COMMON=m
+CONFIG_LEDS_LP8501=m
+CONFIG_LEDS_LP8860=m
+CONFIG_LEDS_LP8864=m
+CONFIG_LEDS_LT3593=m
+CONFIG_LEDS_MAX5970=m
+CONFIG_LEDS_MAX77650=m
+CONFIG_LEDS_MAX77693=m
+CONFIG_LEDS_MAX77705=m
+CONFIG_LEDS_MC13783=m
+CONFIG_LEDS_MENF21BMC=m
+CONFIG_LEDS_MLXREG=m
+CONFIG_LEDS_MT6323=m
+CONFIG_LEDS_MT6360=m
+CONFIG_LEDS_MT6370_FLASH=m
+CONFIG_LEDS_MT6370_RGB=m
+CONFIG_LEDS_NCP5623=m
+CONFIG_LEDS_PCA9532_GPIO=y
+CONFIG_LEDS_PCA9532=m
+CONFIG_LEDS_PCA955X_GPIO=y
+CONFIG_LEDS_PCA955X=m
+CONFIG_LEDS_PCA963X=m
+CONFIG_LEDS_PCA995X=m
+CONFIG_LEDS_PM8058=m
+CONFIG_LEDS_PWM=m
+CONFIG_LEDS_PWM_MULTICOLOR=m
+CONFIG_LEDS_QCOM_LPG=m
+CONFIG_LEDS_REGULATOR=m
+CONFIG_LEDS_RT4505=m
+CONFIG_LEDS_RT8515=m
+CONFIG_LEDS_SGM3140=m
+CONFIG_LEDS_SPI_BYTE=m
+CONFIG_LEDS_ST1202=m
+CONFIG_LEDS_SUN50I_A100=m
+CONFIG_LEDS_SY7802=m
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TCA6507=m
+CONFIG_LEDS_TI_LMU_COMMON=m
+CONFIG_LEDS_TLC591XX=m
+CONFIG_LEDS_TPS6105X=m
+CONFIG_LEDS_TRIGGER_ACTIVITY=m
+CONFIG_LEDS_TRIGGER_AUDIO=m
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_CAMERA=m
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_GPIO=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_MTD=y
+CONFIG_LEDS_TRIGGER_NETDEV=m
+CONFIG_LEDS_TRIGGER_ONESHOT=m
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEDS_TRIGGER_PATTERN=m
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_TRANSIENT=m
+CONFIG_LEDS_TRIGGER_TTY=m
+CONFIG_LEDS_USER=m
+CONFIG_LEDS_WM831X_STATUS=m
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211=m
+CONFIG_LIBCRC32C=m
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_MESH=y
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+CONFIG_LIBERTAS_THINFIRM=m
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBFC=m
+CONFIG_LIBFCOE=m
+CONFIG_LIBFDT=y
+CONFIG_LIBIPW=m
+CONFIG_LIDAR_LITE_V2=m
+CONFIG_LINEAR_RANGES=y
+CONFIG_LIRC=y
+CONFIG_LITEX_LITEETH=m
+CONFIG_LITEX_SOC_CONTROLLER=m
+CONFIG_LITEX_SUBREG_SIZE=4
+CONFIG_LMK04832=m
+CONFIG_LMP91000=m
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_LOOPBACK_TARGET=m
+CONFIG_LPC_ICH=m
+CONFIG_LP_CONSOLE=y
+CONFIG_LPC_SCH=m
+CONFIG_LRU_CACHE=m
+CONFIG_LRU_GEN_ENABLED=y
+CONFIG_LRU_GEN=y
+CONFIG_LSI_ET1011C_PHY=m
+CONFIG_LSM="yama,loadpin,safesetid,integrity,bpf"
+CONFIG_LTC1660=m
+CONFIG_LTC2309=m
+CONFIG_LTC2471=m
+CONFIG_LTC2485=m
+CONFIG_LTC2496=m
+CONFIG_LTC2497=m
+CONFIG_LTC2632=m
+CONFIG_LTC2664=m
+CONFIG_LTC2688=m
+CONFIG_LTC2983=m
+CONFIG_LTE_GDM724X=m
+CONFIG_LTR390=m
 CONFIG_LTR501=m
 CONFIG_LTRF216A=m
 CONFIG_LV0104CS=m
+CONFIG_LWTUNNEL_BPF=y
+CONFIG_LWTUNNEL=y
+CONFIG_LXT_PHY=m
+CONFIG_M62332=m
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_MAC80211=m
+CONFIG_MAC80211_MESH=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MACH_INFINITY=y
+CONFIG_MACH_MERCURY=y
+CONFIG_MACH_MESON6=y
+CONFIG_MACH_MESON8=y
+CONFIG_MACH_MT2701=y
+CONFIG_MACH_MT6572=y
+CONFIG_MACH_MT6589=y
+CONFIG_MACH_MT6592=y
+CONFIG_MACH_MT7623=y
+CONFIG_MACH_MT7629=y
+CONFIG_MACH_MT8127=y
+CONFIG_MACH_MT8135=y
+CONFIG_MACH_OMAP3517EVM=y
+CONFIG_MACH_OMAP3_PANDORA=y
+CONFIG_MACH_OMAP_GENERIC=y
+CONFIG_MACH_REALVIEW_EB=y
+CONFIG_MACH_REALVIEW_PBA8=y
+CONFIG_MACH_REALVIEW_PBX=y
+CONFIG_MACH_SPEAR1310=y
+CONFIG_MACH_SPEAR1340=y
+CONFIG_MACH_STM32MP13=y
+CONFIG_MACH_STM32MP157=y
+CONFIG_MACH_SUN4I=y
+CONFIG_MACH_SUN5I=y
+CONFIG_MACH_SUN6I=y
+CONFIG_MACH_SUN7I=y
+CONFIG_MACH_SUN8I=y
+CONFIG_MACH_SUN9I=y
+CONFIG_MACSEC=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_MADERA_IRQ=m
+CONFIG_MAG3110=m
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
+CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAILBOX=y
+CONFIG_MANAGER_SBS=m
+CONFIG_MANTIS_CORE=m
+CONFIG_MARVELL_10G_PHY=m
+CONFIG_MARVELL_88Q2XXX_PHY=m
+CONFIG_MARVELL_88X2222_PHY=m
+CONFIG_MARVELL_CN10K_TAD_PMU=m
+CONFIG_MARVELL_GTI_WDT=m
+CONFIG_MARVELL_PHY=m
+CONFIG_MAX1027=m
+CONFIG_MAX11100=m
+CONFIG_MAX1118=m
+CONFIG_MAX11205=m
+CONFIG_MAX11410=m
+CONFIG_MAX1241=m
+CONFIG_MAX1363=m
+CONFIG_MAX30100=m
+CONFIG_MAX30102=m
+CONFIG_MAX30208=m
+CONFIG_MAX31856=m
+CONFIG_MAX31865=m
+CONFIG_MAX34408=m
 CONFIG_MAX44000=m
 CONFIG_MAX44009=m
-CONFIG_NOA1305=m
-CONFIG_OPT3001=m
-CONFIG_PA12203001=m
-CONFIG_SI1133=m
-CONFIG_SI1145=m
-CONFIG_STK3310=m
-CONFIG_ST_UVIS25=m
-CONFIG_ST_UVIS25_I2C=m
-CONFIG_ST_UVIS25_SPI=m
-CONFIG_TCS3414=m
-CONFIG_TCS3472=m
-CONFIG_SENSORS_TSL2563=m
-CONFIG_TSL2583=m
-CONFIG_TSL2591=m
-CONFIG_TSL2772=m
-CONFIG_TSL4531=m
-CONFIG_US5182D=m
-CONFIG_VCNL4000=m
-CONFIG_VCNL4035=m
-CONFIG_VEML6030=m
-CONFIG_VEML6070=m
-CONFIG_VL6180=m
-CONFIG_ZOPT2201=m
-# end of Light sensors
-
-#
-# Magnetometer sensors
-#
-# CONFIG_AK8974 is not set
-CONFIG_AK8975=m
-CONFIG_AK09911=m
-CONFIG_BMC150_MAGN=m
-CONFIG_BMC150_MAGN_I2C=m
-CONFIG_BMC150_MAGN_SPI=m
-CONFIG_MAG3110=m
-CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
-CONFIG_MMC35240=m
-CONFIG_IIO_ST_MAGN_3AXIS=m
-CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
-CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
-CONFIG_SENSORS_HMC5843=m
-CONFIG_SENSORS_HMC5843_I2C=m
-CONFIG_SENSORS_HMC5843_SPI=m
-CONFIG_SENSORS_RM3100=m
-CONFIG_SENSORS_RM3100_I2C=m
-CONFIG_SENSORS_RM3100_SPI=m
-CONFIG_YAMAHA_YAS530=m
-# end of Magnetometer sensors
-
-#
-# Multiplexers
-#
-# CONFIG_IIO_MUX is not set
-# end of Multiplexers
-
-#
-# Inclinometer sensors
-#
-CONFIG_HID_SENSOR_INCLINOMETER_3D=m
-CONFIG_HID_SENSOR_DEVICE_ROTATION=m
-# end of Inclinometer sensors
-
-#
-# Triggers - standalone
-#
-CONFIG_IIO_HRTIMER_TRIGGER=m
-CONFIG_IIO_INTERRUPT_TRIGGER=m
-CONFIG_IIO_TIGHTLOOP_TRIGGER=m
-CONFIG_IIO_SYSFS_TRIGGER=m
-# end of Triggers - standalone
-
-#
-# Linear and angular position sensors
-#
-CONFIG_IQS624_POS=m
-CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
-# end of Linear and angular position sensors
-
-#
-# Digital potentiometers
-#
-CONFIG_AD5272=m
-CONFIG_DS1803=m
+CONFIG_MAX517=m
 CONFIG_MAX5432=m
-CONFIG_MAX5481=m
-CONFIG_MAX5487=m
-CONFIG_MCP4018=m
-CONFIG_MCP4131=m
-CONFIG_MCP4531=m
-CONFIG_MCP41010=m
-CONFIG_TPL0102=m
-# end of Digital potentiometers
-
-#
-# Digital potentiostats
-#
-CONFIG_LMP91000=m
-# end of Digital potentiostats
-
-#
-# Pressure sensors
-#
-CONFIG_ABP060MG=m
-CONFIG_BMP280=m
-CONFIG_BMP280_I2C=m
-CONFIG_BMP280_SPI=m
-CONFIG_IIO_CROS_EC_BARO=m
-CONFIG_DLHL60D=m
-CONFIG_DPS310=m
-CONFIG_HID_SENSOR_PRESS=m
-CONFIG_HP03=m
-CONFIG_ICP10100=m
-CONFIG_MPL115=m
-CONFIG_MPL115_I2C=m
-CONFIG_MPL115_SPI=m
-CONFIG_MPL3115=m
-CONFIG_MS5611=m
-CONFIG_MS5611_I2C=m
-CONFIG_MS5611_SPI=m
-CONFIG_MS5637=m
-CONFIG_IIO_ST_PRESS=m
-CONFIG_IIO_ST_PRESS_I2C=m
-CONFIG_IIO_ST_PRESS_SPI=m
-CONFIG_T5403=m
-CONFIG_HP206C=m
-CONFIG_ZPA2326=m
-CONFIG_ZPA2326_I2C=m
-CONFIG_ZPA2326_SPI=m
-# end of Pressure sensors
-
-#
-# Lightning sensors
-#
-CONFIG_AS3935=m
-# end of Lightning sensors
-
-#
-# Proximity and distance sensors
-#
-CONFIG_ISL29501=m
-CONFIG_LIDAR_LITE_V2=m
-CONFIG_MB1232=m
-CONFIG_PING=m
-CONFIG_RFD77402=m
-CONFIG_SRF04=m
-CONFIG_SX9310=m
-CONFIG_SX9324=m
-CONFIG_SX9360=m
-CONFIG_SX9500=m
-CONFIG_SRF08=m
-CONFIG_VCNL3020=m
-CONFIG_VL53L0X_I2C=m
-# end of Proximity and distance sensors
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S90=m
-CONFIG_AD2S1200=m
-# end of Resolver to digital converters
-
-#
-# Temperature sensors
-#
-CONFIG_IQS620AT_TEMP=m
-CONFIG_LTC2983=m
+CONFIG_MAX5481=m
+CONFIG_MAX5487=m
+CONFIG_MAX5522=m
+CONFIG_MAX63XX_WATCHDOG=m
+CONFIG_MAX6959=m
+CONFIG_MAX77541_ADC=m
+CONFIG_MAX77620_WATCHDOG=m
+CONFIG_MAX9611=m
 CONFIG_MAXIM_THERMOCOUPLE=m
-CONFIG_HID_SENSOR_TEMP=m
+CONFIG_MAXLINEAR_GPHY=m
+CONFIG_MAX_RAW_DEVS=256
+CONFIG_MB1232=m
+CONFIG_MC3230=m
+CONFIG_MCB_LPC=m
+CONFIG_MCB=m
+CONFIG_MCB_PCI=m
+CONFIG_MCHP_EIC=y
+CONFIG_MCP320X=m
+CONFIG_MCP3422=m
+CONFIG_MCP3564=m
+CONFIG_MCP3911=m
+CONFIG_MCP4018=m
+CONFIG_MCP41010=m
+CONFIG_MCP4131=m
+CONFIG_MCP4531=m
+CONFIG_MCP4725=m
+CONFIG_MCP4728=m
+CONFIG_MCP4821=m
+CONFIG_MCP4922=m
+CONFIG_MCP9600=m
+CONFIG_MCPM_QUAD_CLUSTER=y
+CONFIG_MCPM=y
+CONFIG_MCTP_SERIAL=m
+CONFIG_MCTP_TRANSPORT_I2C=m
+CONFIG_MCTP_TRANSPORT_I3C=m
+CONFIG_MCTP_TRANSPORT_USB=m
+CONFIG_MCTP=y
+CONFIG_MD_CLUSTER=m
+CONFIG_MD_FAULTY=m
+CONFIG_MDIO_BCM_UNIMAC=m
+CONFIG_MDIO_BITBANG=m
+CONFIG_MDIO_BUS_MUX=m
+CONFIG_MDIO_BUS_MUX_MESON_G12A=m
+CONFIG_MDIO_BUS_MUX_MESON_GXL=m
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_GPIO=m
+CONFIG_MDIO_I2C=m
+CONFIG_MDIO_MSCC_MIIM=m
+CONFIG_MDIO_MVUSB=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID456=m
+CONFIG_MEDIA_ALTERA_CI=m
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CEC_RC=y
+CONFIG_MEDIA_CEC_SUPPORT=y
+CONFIG_MEDIA_COMMON_OPTIONS=y
+CONFIG_MEDIA_CONTROLLER_DVB=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_PCI_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIATEK_GE_PHY=m
+CONFIG_MEDIATEK_MT6359_AUXADC=m
+CONFIG_MEDIATEK_MT6360_ADC=m
+CONFIG_MEDIATEK_MT6370_ADC=m
+CONFIG_MEDIA_TUNER_AV201X=m
+CONFIG_MEDIA_TUNER_E4000=m
+CONFIG_MEDIA_TUNER_FC0011=m
+CONFIG_MEDIA_TUNER_FC0012=m
+CONFIG_MEDIA_TUNER_FC0013=m
+CONFIG_MEDIA_TUNER_FC2580=m
+CONFIG_MEDIA_TUNER_IT913X=m
+CONFIG_MEDIA_TUNER=m
+CONFIG_MEDIA_TUNER_M88RS6000T=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MSI001=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2063=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2131=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_MXL301RF=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_QM1D1B0004=m
+CONFIG_MEDIA_TUNER_QM1D1C0042=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_R820T=m
+CONFIG_MEDIA_TUNER_SI2157=m
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_STV6120=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TDA18250=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_MEGARAID_LEGACY=m
+CONFIG_MEGARAID_MAILBOX=m
+CONFIG_MEGARAID_MM=m
+CONFIG_MEGARAID_NEWGEN=y
+CONFIG_MEGARAID_SAS=m
+CONFIG_MEMCG_KMEM=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MEMORY=y
+CONFIG_MEMSTICK_JMICRON_38X=m
+CONFIG_MEMSTICK=m
+CONFIG_MEMSTICK_R592=m
+CONFIG_MEMSTICK_REALTEK_PCI=m
+CONFIG_MEMSTICK_REALTEK_USB=m
+CONFIG_MEMSTICK_TIFM_MS=m
+CONFIG_MEN_A21_WDT=m
+CONFIG_MENF21BMC_WATCHDOG=m
+CONFIG_MENZ069_WATCHDOG=m
+CONFIG_MEN_Z188_ADC=m
+CONFIG_MESON6_TIMER=y
+CONFIG_MESON_CLK_MEASURE=y
+CONFIG_MESON_DDR_PMU=m
+CONFIG_MESON_EE_PM_DOMAINS=y
+CONFIG_MESON_GX_PM_DOMAINS=y
+CONFIG_MESON_GX_SOCINFO=y
+CONFIG_MESON_IRQ_GPIO=y
+CONFIG_MESON_MX_SOCINFO=y
+CONFIG_MESON_SARADC=m
+CONFIG_MFD_88PM800=m
+CONFIG_MFD_88PM805=m
+CONFIG_MFD_88PM886_PMIC=y
+CONFIG_MFD_ACT8945A=m
+CONFIG_MFD_ALTERA_A10SR=y
+CONFIG_MFD_ARIZONA_I2C=m
+CONFIG_MFD_ARIZONA_SPI=m
+CONFIG_MFD_ARIZONA=y
+CONFIG_MFD_ASIC3=y
+CONFIG_MFD_ATC260X_I2C=m
+CONFIG_MFD_ATMEL_FLEXCOM=m
+CONFIG_MFD_ATMEL_HLCDC=m
+CONFIG_MFD_ATMEL_SMC=y
+CONFIG_MFD_AXP20X_I2C=m
+CONFIG_MFD_AXP20X=m
+CONFIG_MFD_BCM590XX=m
+CONFIG_MFD_BD9571MWV=m
+CONFIG_MFD_CORE=y
+CONFIG_MFD_CPCAP=m
+CONFIG_MFD_CROS_EC_DEV=m
+CONFIG_MFD_CS42L43_I2C=m
+CONFIG_MFD_CS42L43_SDW=m
+CONFIG_MFD_CS47L15=y
+CONFIG_MFD_CS47L24=y
+CONFIG_MFD_CS47L35=y
+CONFIG_MFD_CS47L85=y
+CONFIG_MFD_CS47L90=y
+CONFIG_MFD_CS47L92=y
+CONFIG_MFD_DA9052_SPI=y
+CONFIG_MFD_DA9062=m
+CONFIG_MFD_DA9063=m
+CONFIG_MFD_DA9150=m
+CONFIG_MFD_DB8500_PRCMU=y
+CONFIG_MFD_DLN2=m
+CONFIG_MFD_GATEWORKS_GSC=m
+CONFIG_MFD_HI6421_PMIC=m
+CONFIG_MFD_HI6421_SPMI=m
+CONFIG_MFD_INTEL_M10_BMC=m
+CONFIG_MFD_INTEL_M10_BMC_PMCI=m
+CONFIG_MFD_INTEL_M10_BMC_SPI=m
+CONFIG_MFD_INTEL_PMT=m
+CONFIG_MFD_IQS62X=m
+CONFIG_MFD_JANZ_CMODIO=m
+CONFIG_MFD_KEMPLD=m
+CONFIG_MFD_KHADAS_MCU=m
+CONFIG_MFD_LM3533=m
+CONFIG_MFD_LP3943=m
+CONFIG_MFD_MACSMC=m
+CONFIG_MFD_MADERA_I2C=m
+CONFIG_MFD_MADERA=m
+CONFIG_MFD_MADERA_SPI=m
+CONFIG_MFD_MAX14577=m
+CONFIG_MFD_MAX5970=m
+CONFIG_MFD_MAX597X=m
+CONFIG_MFD_MAX7360=m
+CONFIG_MFD_MAX77541=m
+CONFIG_MFD_MAX77650=m
+CONFIG_MFD_MAX77686=m
+CONFIG_MFD_MAX77693=m
+CONFIG_MFD_MAX77714=m
+CONFIG_MFD_MAX77759=m
+CONFIG_MFD_MAX8907=m
+CONFIG_MFD_MC13XXX_I2C=m
+CONFIG_MFD_MC13XXX=m
+CONFIG_MFD_MC13XXX_SPI=m
+CONFIG_MFD_MENF21BMC=m
+CONFIG_MFD_MP2629=m
+CONFIG_MFD_MT6360=m
+CONFIG_MFD_MT6370=m
+CONFIG_MFD_MT6397=m
+CONFIG_MFD_NTXEC=m
+CONFIG_MFD_OCELOT=m
+CONFIG_MFD_OMAP_USB_HOST=y
+CONFIG_MFD_PCF50633=m
+CONFIG_MFD_PM8XXX=m
+CONFIG_MFD_QCOM_PM8008=m
+CONFIG_MFD_QNAP_MCU=m
+CONFIG_MFD_RDC321X=m
+CONFIG_MFD_RETU=m
+CONFIG_MFD_RK808=m
+CONFIG_MFD_RK8XX_I2C=m
+CONFIG_MFD_RK8XX_SPI=m
+CONFIG_MFD_RN5T618=m
+CONFIG_MFD_ROHM_BD957XMUF=m
+CONFIG_MFD_ROHM_BD96801=m
+CONFIG_MFD_RSMU_I2C=m
+CONFIG_MFD_RSMU_SPI=m
+CONFIG_MFD_RT4831=m
+CONFIG_MFD_RT5033=m
+CONFIG_MFD_RT5120=m
+CONFIG_MFD_SEC_ACPM=m
+CONFIG_MFD_SEC_I2C=m
+CONFIG_MFD_SI476X_CORE=m
+CONFIG_MFD_SIMPLE_MFD_I2C=m
+CONFIG_MFD_SKY81452=m
+CONFIG_MFD_SL28CPLD=m
+CONFIG_MFD_SM501_GPIO=y
+CONFIG_MFD_SM501=m
+CONFIG_MFD_SMPRO=m
+CONFIG_MFD_STMFX=m
+CONFIG_MFD_STMPE=y
+CONFIG_MFD_SUN6I_PRCM=y
+CONFIG_MFD_SY7636A=m
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_T7L66XB=y
+CONFIG_MFD_TC6387XB=y
+CONFIG_MFD_TC6393XB=y
+CONFIG_MFD_TI_AM335X_TSCADC=m
+CONFIG_MFD_TI_LMU=m
+CONFIG_MFD_TI_LP873X=m
+CONFIG_MFD_TI_LP87565=m
+CONFIG_MFD_TMIO=y
+CONFIG_MFD_TPS65086=m
+CONFIG_MFD_TPS65217=m
+CONFIG_MFD_TPS65218=m
+CONFIG_MFD_TPS65219=m
+CONFIG_MFD_TPS65912_I2C=m
+CONFIG_MFD_TPS65912_SPI=y
+CONFIG_MFD_TPS65912=y
+CONFIG_MFD_TPS6594_I2C=m
+CONFIG_MFD_TPS6594_SPI=m
+CONFIG_MFD_TQMX86=m
+CONFIG_MFD_VEXPRESS_SYSREG=m
+CONFIG_MFD_VIPERBOARD=m
+CONFIG_MFD_VX855=m
+CONFIG_MFD_WCD934X=m
+CONFIG_MFD_WL1273_CORE=m
+CONFIG_MFD_WM5102=y
+CONFIG_MFD_WM5110=y
+CONFIG_MFD_WM831X_SPI=y
+CONFIG_MFD_WM831X=y
+CONFIG_MFD_WM8994=m
+CONFIG_MFD_WM8997=y
+CONFIG_MFD_WM8998=y
+CONFIG_MHI_BUS_EP=m
+CONFIG_MHI_BUS=m
+CONFIG_MHI_BUS_PCI_GENERIC=m
+CONFIG_MHI_NET=m
+CONFIG_MHI_WWAN_CTRL=m
+CONFIG_MHI_WWAN_MBIM=m
+CONFIG_MICREL_KS8995MA=m
+CONFIG_MICREL_PHY=m
+CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y
+CONFIG_MICROCHIP_OTPC=m
+CONFIG_MICROCHIP_PHY=m
+CONFIG_MICROCHIP_T1_PHY=m
+CONFIG_MICROCHIP_T1S_PHY=m
+CONFIG_MICROCHIP_TCB_CAPTURE=m
+CONFIG_MICROSEMI_PHY=m
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MII=m
+CONFIG_MIPI_I3C_HCI=m
+CONFIG_MIPI_I3C_HCI_PCI=m
+CONFIG_MISC_ALCOR_PCI=m
+CONFIG_MISC_RP1=m
+CONFIG_MISC_RTSX=m
+CONFIG_MISC_RTSX_PCI=m
+CONFIG_MISC_RTSX_USB=m
+CONFIG_MISDN_AVMFRITZ=m
+CONFIG_MISDN_DSP=m
+CONFIG_MISDN_HDLC=m
+CONFIG_MISDN_HFCMULTI=m
+CONFIG_MISDN_HFCPCI=m
+CONFIG_MISDN_HFCUSB=m
+CONFIG_MISDN_INFINEON=m
+CONFIG_MISDN_IPAC=m
+CONFIG_MISDN_ISAR=m
+CONFIG_MISDN_L1OIP=m
+CONFIG_MISDN=m
+CONFIG_MISDN_NETJET=m
+CONFIG_MISDN_SPEEDFAX=m
+CONFIG_MISDN_W6692=m
+CONFIG_MKISS=m
+CONFIG_MLX4_INFINIBAND=m
+CONFIG_MLX5_INFINIBAND=m
+CONFIG_MLX5_VDPA_NET=m
+CONFIG_MLX5_VDPA=y
+CONFIG_MLX5_VFIO_PCI=m
 CONFIG_MLX90614=m
 CONFIG_MLX90632=m
-CONFIG_TMP006=m
-CONFIG_TMP007=m
-CONFIG_TMP117=m
-CONFIG_TSYS01=m
-CONFIG_TSYS02D=m
-CONFIG_MAX31856=m
-# end of Temperature sensors
-
-CONFIG_NTB=m
-CONFIG_NTB_MSI=y
-CONFIG_NTB_IDT=m
-CONFIG_NTB_EPF=m
-CONFIG_NTB_SWITCHTEC=m
-CONFIG_NTB_PINGPONG=m
-CONFIG_NTB_TOOL=m
-CONFIG_NTB_PERF=m
-CONFIG_NTB_MSI_TEST=m
-CONFIG_NTB_TRANSPORT=m
-CONFIG_VME_BUS=y
-
-#
-# VME Bridge Drivers
-#
-CONFIG_VME_TSI148=m
-CONFIG_VME_FAKE=m
-
-#
-# VME Board Drivers
-#
-CONFIG_VMIVME_7805=m
-
-#
-# VME Device Drivers
-#
-CONFIG_VME_USER=m
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_PWM_DEBUG is not set
-# CONFIG_PWM_AB8500 is not set
-# CONFIG_PWM_ATMEL is not set
-CONFIG_PWM_ATMEL_TCB=m
-# CONFIG_PWM_ATMEL_HLCDC_PWM is not set
-# CONFIG_PWM_BERLIN is not set
-CONFIG_PWM_CROS_EC=m
-CONFIG_PWM_DWC=m
-# CONFIG_PWM_FSL_FTM is not set
-# CONFIG_PWM_HIBVT is not set
-# CONFIG_PWM_IMX1 is not set
-# CONFIG_PWM_IMX27 is not set
-# CONFIG_PWM_IMX_TPM is not set
-CONFIG_PWM_IQS620A=m
-CONFIG_PWM_LP3943=m
-# CONFIG_PWM_MESON is not set
-# CONFIG_PWM_MTK_DISP is not set
-# CONFIG_PWM_MEDIATEK is not set
-CONFIG_PWM_NTXEC=m
-# CONFIG_PWM_OMAP_DMTIMER is not set
-CONFIG_PWM_PCA9685=m
-CONFIG_PWM_RASPBERRYPI_POE=m
-# CONFIG_PWM_RCAR is not set
-# CONFIG_PWM_RENESAS_TPU is not set
-# CONFIG_PWM_ROCKCHIP is not set
-# CONFIG_PWM_SAMSUNG is not set
-CONFIG_PWM_SL28CPLD=m
-# CONFIG_PWM_SPEAR is not set
-# CONFIG_PWM_STI is not set
-# CONFIG_PWM_STMPE is not set
-# CONFIG_PWM_SUN4I is not set
-# CONFIG_PWM_TEGRA is not set
-# CONFIG_PWM_TIECAP is not set
-# CONFIG_PWM_TIEHRPWM is not set
-CONFIG_PWM_VISCONTI=m
-# CONFIG_PWM_TWL is not set
-# CONFIG_PWM_TWL_LED is not set
-# CONFIG_PWM_VT8500 is not set
-# CONFIG_PWM_ZX is not set
-
-#
-# IRQ chip support
-#
-CONFIG_IRQCHIP=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_MAX_NR=2
-CONFIG_GIC_NON_BANKED=y
-CONFIG_ARM_VIC=y
-CONFIG_ARM_VIC_NR=4
-CONFIG_ALPINE_MSI=y
-# CONFIG_AL_FIC is not set
-CONFIG_XILINX_INTC=y
-CONFIG_DW_APB_ICTL=y
-CONFIG_MADERA_IRQ=m
-CONFIG_OMAP_IRQCHIP=y
-CONFIG_RDA_INTC=y
-CONFIG_ST_IRQCHIP=y
-CONFIG_TANGO_IRQ=y
-CONFIG_IRQ_CROSSBAR=y
-# CONFIG_KEYSTONE_IRQ is not set
-CONFIG_STM32_EXTI=y
-CONFIG_IRQ_UNIPHIER_AIDET=y
-CONFIG_MESON_IRQ_GPIO=y
-# CONFIG_QCOM_PDC is not set
-CONFIG_QCOM_MPM=m
-CONFIG_IMX_IRQSTEER=y
-CONFIG_IMX_MU_MSI=m
-CONFIG_IMX_INTMUX=y
-CONFIG_TI_PRUSS_INTC=m
-CONFIG_EXYNOS_IRQ_COMBINER=y
-CONFIG_MST_IRQ=y
-# end of IRQ chip support
-
-# CONFIG_IPACK_BUS is not set
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_RESET_A10SR=m
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_MCHP_SPARX5=y
-CONFIG_RESET_BERLIN=y
-CONFIG_RESET_MCHP_SPARX5=y
-# CONFIG_RESET_BRCMSTB_RESCAL is not set
-# CONFIG_RESET_INTEL_GW is not set
-CONFIG_RESET_MESON=y
-# CONFIG_RESET_MESON_AUDIO_ARB is not set
-CONFIG_RESET_NPCM=y
-# CONFIG_RESET_QCOM_AOSS is not set
-# CONFIG_RESET_QCOM_PDC is not set
-CONFIG_RESET_SCMI=y
-CONFIG_RESET_SIMPLE=y
-CONFIG_RESET_STM32MP157=y
-CONFIG_RESET_SOCFPGA=y
-CONFIG_RESET_SUNXI=y
-CONFIG_RESET_TI_SYSCON=m
-CONFIG_RESET_UNIPHIER=y
-CONFIG_RESET_UNIPHIER_GLUE=y
-CONFIG_RESET_ZYNQ=y
-CONFIG_STI_RESET_SYSCFG=y
-CONFIG_STIH407_RESET=y
-CONFIG_COMMON_RESET_HI3660=y
-CONFIG_COMMON_RESET_HI6220=y
-
-#
-# PHY Subsystem
-#
-CONFIG_GENERIC_PHY=y
-CONFIG_PHY_CAN_TRANSCEIVER=m
-CONFIG_GENERIC_PHY_MIPI_DPHY=y
-CONFIG_USB_LGM_PHY=m
-# CONFIG_PHY_SUN4I_USB is not set
-# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
-# CONFIG_PHY_SUN9I_USB is not set
-# CONFIG_PHY_SUN50I_USB3 is not set
-CONFIG_PHY_MESON8B_USB2=y
-CONFIG_PHY_MESON_GXL_USB2=y
-CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=m
-CONFIG_PHY_MIXEL_LVDS_PHY=m
-CONFIG_PHY_MTK_PCIE=m
-CONFIG_PHY_MTK_DP=m
-CONFIG_PHY_MESON_G12A_USB2=y
-CONFIG_PHY_MESON_G12A_USB3_PCIE=y
-CONFIG_PHY_MESON_AXG_PCIE=y
-CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
-CONFIG_PHY_MESON_AXG_MIPI_DPHY=m
-CONFIG_BCM_KONA_USB2_PHY=m
-# CONFIG_PHY_CADENCE_TORRENT is not set
-# CONFIG_PHY_CADENCE_DPHY is not set
-CONFIG_PHY_CADENCE_DPHY_RX=m
-# CONFIG_PHY_CADENCE_SIERRA is not set
-# CONFIG_PHY_CADENCE_SALVO is not set
-# CONFIG_PHY_FSL_IMX8MQ_USB is not set
-# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
-# CONFIG_PHY_HIX5HD2_SATA is not set
-# CONFIG_PHY_BERLIN_SATA is not set
-# CONFIG_PHY_BERLIN_USB is not set
-CONFIG_PHY_MVEBU_A3700_COMPHY=y
-CONFIG_PHY_MVEBU_A3700_UTMI=y
-# CONFIG_PHY_MVEBU_A38X_COMPHY is not set
-# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
-CONFIG_PHY_MVEBU_CP110_UTMI=m
-CONFIG_PHY_PXA_28NM_HSIC=m
-CONFIG_PHY_PXA_28NM_USB2=m
-# CONFIG_PHY_PXA_USB is not set
-# CONFIG_PHY_MTK_TPHY is not set
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PHY_MTK_HDMI=m
-CONFIG_PHY_MTK_MIPI_DSI=m
-CONFIG_PHY_SPARX5_SERDES=m
-CONFIG_PHY_CPCAP_USB=m
-# CONFIG_PHY_MAPPHONE_MDM6600 is not set
-# CONFIG_PHY_OCELOT_SERDES is not set
-# CONFIG_PHY_QCOM_APQ8064_SATA is not set
-# CONFIG_PHY_QCOM_IPQ4019_USB is not set
-# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
-# CONFIG_PHY_QCOM_PCIE2 is not set
-# CONFIG_PHY_QCOM_QMP is not set
-# CONFIG_PHY_QCOM_QUSB2 is not set
-CONFIG_PHY_QCOM_USB_HS=m
-# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
-CONFIG_PHY_QCOM_USB_HSIC=m
-# CONFIG_PHY_QCOM_USB_HS_28NM is not set
-# CONFIG_PHY_QCOM_USB_SS is not set
-CONFIG_PHY_QCOM_IPQ806X_USB=m
-# CONFIG_PHY_RCAR_GEN2 is not set
-# CONFIG_PHY_RCAR_GEN3_PCIE is not set
-# CONFIG_PHY_RCAR_GEN3_USB2 is not set
-# CONFIG_PHY_RCAR_GEN3_USB3 is not set
-# CONFIG_PHY_ROCKCHIP_DP is not set
-# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
-# CONFIG_PHY_ROCKCHIP_EMMC is not set
-# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
-# CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set
-CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m
-# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
-CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
-# CONFIG_PHY_ROCKCHIP_PCIE is not set
-CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m
-# CONFIG_PHY_ROCKCHIP_TYPEC is not set
-# CONFIG_PHY_ROCKCHIP_USB is not set
-CONFIG_PHY_EXYNOS_DP_VIDEO=y
-CONFIG_PHY_EXYNOS_MIPI_VIDEO=y
-# CONFIG_PHY_EXYNOS_PCIE is not set
-CONFIG_PHY_SAMSUNG_UFS=m
-CONFIG_PHY_SAMSUNG_USB2=m
-CONFIG_PHY_EXYNOS4210_USB2=y
-CONFIG_PHY_EXYNOS4X12_USB2=y
-CONFIG_PHY_EXYNOS5250_USB2=y
-# CONFIG_PHY_S5PV210_USB2 is not set
-CONFIG_PHY_EXYNOS5_USBDRD=m
-# CONFIG_PHY_EXYNOS5250_SATA is not set
-# CONFIG_PHY_UNIPHIER_USB2 is not set
-# CONFIG_PHY_UNIPHIER_USB3 is not set
-# CONFIG_PHY_UNIPHIER_PCIE is not set
-CONFIG_PHY_UNIPHIER_AHCI=m
-# CONFIG_PHY_MIPHY28LP is not set
-CONFIG_PHY_ST_SPEAR1310_MIPHY=y
-CONFIG_PHY_ST_SPEAR1340_MIPHY=y
-# CONFIG_PHY_STIH407_USB is not set
-# CONFIG_PHY_STM32_USBPHYC is not set
-CONFIG_PHY_SUNPLUS_USB=m
-# CONFIG_PHY_TEGRA_XUSB is not set
-# CONFIG_PHY_DM816X_USB is not set
-# CONFIG_OMAP_CONTROL_PHY is not set
-# CONFIG_OMAP_USB2 is not set
-# CONFIG_TI_PIPE3 is not set
-CONFIG_PHY_TUSB1210=m
-# end of PHY Subsystem
-
-CONFIG_POWERCAP=y
-# CONFIG_IDLE_INJECT is not set
-CONFIG_DTPM=y
-CONFIG_DTPM_CPU=y
-CONFIG_DTPM_DEVFREQ=y
-CONFIG_MCB=m
-CONFIG_MCB_PCI=m
-CONFIG_MCB_LPC=m
-
-#
-# Performance monitor support
-#
-CONFIG_ARM_CCI_PMU=m
-CONFIG_ARM_CCI400_PMU=y
-CONFIG_ARM_CCI5xx_PMU=y
-CONFIG_ARM_CCN=m
-CONFIG_ARM_PMU=y
-# CONFIG_FSL_IMX8_DDR_PMU is not set
-# end of Performance monitor support
-
-CONFIG_RAS=y
-CONFIG_USB4=m
-# CONFIG_USB4_DEBUGFS_WRITE is not set
-# CONFIG_USB4_DMA_TEST is not set
-
-#
-# Android
-#
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=m
-CONFIG_ANDROID_BINDERFS=y
-CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
-# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
-# end of Android
-
-# CONFIG_LIBNVDIMM is not set
-CONFIG_DAX=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-# CONFIG_NVMEM_IMX_IIM is not set
-# CONFIG_NVMEM_IMX_OCOTP is not set
+CONFIG_MLX90635=m
+CONFIG_MLXREG_HOTPLUG=m
+CONFIG_MLXREG_IO=m
+CONFIG_MLX_WDT=m
+CONFIG_MMA7455_I2C=m
+CONFIG_MMA7455=m
+CONFIG_MMA7455_SPI=m
+CONFIG_MMA7660=m
+CONFIG_MMA8452=m
+CONFIG_MMA9551_CORE=m
+CONFIG_MMA9551=m
+CONFIG_MMA9553=m
+CONFIG_MMC35240=m
+CONFIG_MMC_ALCOR=m
+CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_CB710=m
+CONFIG_MMC_CQHCI=m
+CONFIG_MMC_CRYPTO=y
+CONFIG_MMC_DW_BLUEFIELD=m
+CONFIG_MMC_DW_EXYNOS=m
+CONFIG_MMC_DW_HI3798CV200=m
+CONFIG_MMC_DW_HI3798MV200=m
+CONFIG_MMC_DW_K3=m
+CONFIG_MMC_DW=m
+CONFIG_MMC_DW_PCI=m
+CONFIG_MMC_DW_PLTFM=m
+CONFIG_MMC_HSQ=m
+CONFIG_MMC_LITEX=m
+CONFIG_MMC=m
+CONFIG_MMC_MTK=m
+CONFIG_MMC_REALTEK_PCI=m
+CONFIG_MMC_REALTEK_USB=m
+CONFIG_MMC_RICOH_MMC=y
+CONFIG_MMC_SDHCI_AM654=m
+CONFIG_MMC_SDHCI_CADENCE=m
+CONFIG_MMC_SDHCI_EXTERNAL_DMA=y
+CONFIG_MMC_SDHCI_F_SDH30=m
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI=m
+CONFIG_MMC_SDHCI_MILBEAUT=m
+CONFIG_MMC_SDHCI_NPCM=m
+CONFIG_MMC_SDHCI_OF_ARASAN=m
+CONFIG_MMC_SDHCI_OF_ASPEED=m
+CONFIG_MMC_SDHCI_OF_AT91=m
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+CONFIG_MMC_SDHCI_OMAP=m
+CONFIG_MMC_SDHCI_PCI=m
+CONFIG_MMC_SDHCI_PLTFM=m
+CONFIG_MMC_SDHCI_XENON=m
+CONFIG_MMC_SDRICOH_CS=m
+CONFIG_MMC_SPI=m
+CONFIG_MMC_SUNPLUS=m
+CONFIG_MMC_TIFM_SD=m
+CONFIG_MMC_TMIO_CORE=m
+CONFIG_MMC_TMIO=m
+CONFIG_MMC_USDHI6ROL0=m
+CONFIG_MMC_USHC=m
+CONFIG_MMC_VIA_SDMMC=m
+CONFIG_MMC_VUB300=m
+CONFIG_MMC_WMT=m
+CONFIG_MMP_PDMA=m
+CONFIG_MMP_TDMA=m
+CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
+CONFIG_MMU_GATHER_TABLE_FREE=y
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MOST_CDEV=m
+CONFIG_MOST_COMPONENTS=m
+CONFIG_MOST_I2C=m
+CONFIG_MOST=m
+CONFIG_MOST_NET=m
+CONFIG_MOST_SND=m
+CONFIG_MOST_SOUND=m
+CONFIG_MOST_USB_HDM=m
+CONFIG_MOST_VIDEO=m
+CONFIG_MOTORCOMM_PHY=m
+CONFIG_MOUSE_APPLETOUCH=m
+CONFIG_MOUSE_BCM5974=m
+CONFIG_MOUSE_CYAPA=m
+CONFIG_MOUSE_ELAN_I2C_I2C=y
+CONFIG_MOUSE_ELAN_I2C=m
+CONFIG_MOUSE_ELAN_I2C_SMBUS=y
+CONFIG_MOUSE_GPIO=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_PIXART=y
+CONFIG_MOUSE_PS2_SENTELIC=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TOUCHKIT=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+CONFIG_MOUSE_SERIAL=m
+CONFIG_MOUSE_SYNAPTICS_I2C=m
+CONFIG_MOUSE_SYNAPTICS_USB=m
+CONFIG_MOUSE_VSXXXAA=m
+CONFIG_MOXA_INTELLIO=m
+CONFIG_MOXA_SMARTIO=m
+CONFIG_MOXTET=m
+CONFIG_MP2629_ADC=m
+CONFIG_MPL115_I2C=m
+CONFIG_MPL115=m
+CONFIG_MPL115_SPI=m
+CONFIG_MPL3115=m
+CONFIG_MPRLS0025PA=m
+CONFIG_MPU3050_I2C=m
+CONFIG_MPU3050=m
+CONFIG_MQ_IOSCHED_KYBER=m
+CONFIG_MS5611_I2C=m
+CONFIG_MS5611=m
+CONFIG_MS5611_SPI=m
+CONFIG_MS5637=m
+CONFIG_MSA311=m
+CONFIG_MS_BLOCK=m
+CONFIG_MSC313E_WATCHDOG=m
+CONFIG_MSE102X=m
+CONFIG_MSPRO_BLOCK=m
+CONFIG_MSTAR_MSC313_CPUPLL=y
+CONFIG_MSTAR_MSC313_MPLL=y
+CONFIG_MST_IRQ=y
+CONFIG_MT7601U=m
+CONFIG_MT7603E=m
+CONFIG_MT7615_COMMON=m
+CONFIG_MT7615E=m
+CONFIG_MT7622_WMAC=y
+CONFIG_MT7663S=m
+CONFIG_MT7663U=m
+CONFIG_MT7663_USB_SDIO_COMMON=m
+CONFIG_MT76_CORE=m
+CONFIG_MT76_LEDS=y
+CONFIG_MT76_SDIO=m
+CONFIG_MT76_USB=m
+CONFIG_MT76x02_LIB=m
+CONFIG_MT76x02_USB=m
+CONFIG_MT76x0_COMMON=m
+CONFIG_MT76x0E=m
+CONFIG_MT76x0U=m
+CONFIG_MT76x2_COMMON=m
+CONFIG_MT76x2E=m
+CONFIG_MT76x2U=m
+CONFIG_MT7915E=m
+CONFIG_MT7921E=m
+CONFIG_MT7921S=m
+CONFIG_MT7921U=m
+CONFIG_MT7925E=m
+CONFIG_MT7925U=m
+CONFIG_MT7986_WMAC=y
+CONFIG_MT798X_WMAC=y
+CONFIG_MT7996E=m
+CONFIG_MTD_ABSENT=m
+CONFIG_MTD_AR7_PARTS=m
+CONFIG_MTD_BCM47XXSFLASH=m
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK2MTD=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_BLOCK_RO=m
+CONFIG_MTD_BRCM_U_BOOT=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI=m
+CONFIG_MTD_CFI_STAA=m
+CONFIG_MTD_CFI_UTIL=m
+CONFIG_MTD_CMDLINE_PARTS=m
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_DATAFLASH=m
+CONFIG_MTD_DATAFLASH_OTP=y
+CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
+CONFIG_MTD_DOCG3=m
+CONFIG_MTD_GEN_PROBE=m
+CONFIG_MTD_HYPERBUS=m
+CONFIG_MTD_IMPA7=m
+CONFIG_MTD_INTEL_DG=m
+CONFIG_MTD_INTEL_VR_NOR=m
+CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_LPDDR2_NVM=m
+CONFIG_MTD_LPDDR=m
+CONFIG_MTD=m
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_MCHP23K256=m
+CONFIG_MTD_MCHP48L640=m
+CONFIG_MTD_MTDRAM=m
+CONFIG_MTD_NAND_ARASAN=m
+CONFIG_MTD_NAND_BRCMNAND_BCM63XX=m
+CONFIG_MTD_NAND_BRCMNAND_BCMBCA=m
+CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=m
+CONFIG_MTD_NAND_BRCMNAND_IPROC=m
+CONFIG_MTD_NAND_BRCMNAND=m
+CONFIG_MTD_NAND_CADENCE=m
+CONFIG_MTD_NAND_CAFE=m
+CONFIG_MTD_NAND_CORE=m
+CONFIG_MTD_NAND_DENALI_DT=m
+CONFIG_MTD_NAND_DENALI=m
+CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
+CONFIG_MTD_NAND_DISKONCHIP=m
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
+CONFIG_MTD_NAND_ECC_MEDIATEK=m
+CONFIG_MTD_NAND_ECC_MXIC=y
+CONFIG_MTD_NAND_ECC_SW_BCH=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=m
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_GPIO=m
+CONFIG_MTD_NAND_INTEL_LGM=m
+CONFIG_MTD_NAND_MXIC=m
+CONFIG_MTD_NAND_NANDSIM=m
+CONFIG_MTD_NAND_OMAP2=m
+CONFIG_MTD_NAND_OMAP_BCH=y
+CONFIG_MTD_NAND_PL35X=m
+CONFIG_MTD_NAND_PLATFORM=m
+CONFIG_MTD_NAND_RENESAS=m
+CONFIG_MTD_NAND_RICOH=m
+CONFIG_MTD_NAND_ROCKCHIP=m
+CONFIG_MTD_OF_PARTS_BCM4908=y
+CONFIG_MTD_OF_PARTS_LINKSYS_NS=y
+CONFIG_MTD_OF_PARTS=m
+CONFIG_MTD_ONENAND_2X_PROGRAM=y
+CONFIG_MTD_ONENAND_GENERIC=m
+CONFIG_MTD_ONENAND=m
+CONFIG_MTD_ONENAND_OTP=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+CONFIG_MTD_OOPS=m
+CONFIG_MTD_PARSER_TRX=m
+CONFIG_MTD_PARTITIONED_MASTER=y
+CONFIG_MTD_PCI=m
+CONFIG_MTD_PCMCIA=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PLATRAM=m
+CONFIG_MTD_PMC551_BUGFIX=y
+CONFIG_MTD_PMC551=m
+CONFIG_MTD_PSTORE=m
+CONFIG_MTD_QCOMSMEM_PARTS=m
+CONFIG_MTD_QINFO_PROBE=m
+CONFIG_MTDRAM_ERASE_SIZE=128
+CONFIG_MTD_RAM=m
+CONFIG_MTDRAM_TOTAL_SIZE=4096
+CONFIG_MTD_RAW_NAND=m
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+CONFIG_MTD_REDBOOT_PARTS=m
+CONFIG_MTD_REDBOOT_PARTS_READONLY=y
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+CONFIG_MTD_ROM=m
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_SM_COMMON=m
+CONFIG_MTD_SPEAR_SMI=m
+CONFIG_MTD_SPI_NAND=m
+CONFIG_MTD_SPI_NOR=m
+CONFIG_MTD_SPI_NOR_SWP_DISABLE=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SST25L=m
+CONFIG_MTD_SWAP=m
+CONFIG_MTD_TESTS=m
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_GLUEBI=m
+CONFIG_MTD_UBI=m
+CONFIG_MTD_UBI_NVMEM=m
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTK_ADSP_IPC=m
+CONFIG_MTK_ADSP_MBOX=m
+CONFIG_MTK_DEVAPC=m
+CONFIG_MTK_GPUEB_MBOX=m
+CONFIG_MTK_INFRACFG=y
+CONFIG_MTK_LVTS_THERMAL=m
+CONFIG_MTK_MMSYS=y
+CONFIG_MTK_SCPSYS_PM_DOMAINS=y
+CONFIG_MTK_SCPSYS=y
+CONFIG_MTK_SOCINFO=m
+CONFIG_MTK_SOC_THERMAL=m
+CONFIG_MTK_SVS=m
+CONFIG_MTK_T7XX=m
+CONFIG_MTK_THERMAL=y
+CONFIG_MTK_TIMER=y
+CONFIG_MULTIPLEXER=m
+CONFIG_MUSB_PIO_ONLY=y
+CONFIG_MUX_ADG792A=m
+CONFIG_MUX_ADGS1408=m
+CONFIG_MUX_GPIO=m
+CONFIG_MVEBU_DEVBUS=y
+CONFIG_MVEBU_MBUS=y
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_PCIE=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
+CONFIG_MWL8K=m
+CONFIG_MX3_IPU_IRQS=4
+CONFIG_MX3_IPU=y
+CONFIG_MXC4005=m
+CONFIG_MXC6255=m
+CONFIG_MXC_CLK=y
+CONFIG_NATIONAL_PHY=m
+CONFIG_NAU7802=m
+CONFIG_NCN26000_PHY=m
+CONFIG_NCT6694_WATCHDOG=m
+CONFIG_NEON=y
+CONFIG_NET_9P_FD=m
+CONFIG_NET_9P=m
+CONFIG_NET_9P_RDMA=m
+CONFIG_NET_9P_USBG=y
+CONFIG_NET_9P_VIRTIO=m
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETCONSOLE_EXTENDED_LOG=y
+CONFIG_NETCONSOLE=m
+CONFIG_NET_DEVLINK=y
+CONFIG_NETDEVSIM=m
+CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
+CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
+CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
+CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=y
+CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
+CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
+CONFIG_NET_FAILOVER=m
+CONFIG_NET_FC=y
+CONFIG_NETFILTER_EGRESS=y
+CONFIG_NETFS_STATS=y
+CONFIG_NETFS_SUPPORT=m
+CONFIG_NET_IFE=m
+CONFIG_NETKIT=y
+CONFIG_NET_POLL_CONTROLLER=y
+CONFIG_NETPOLL=y
+CONFIG_NETROM=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_NET_TEAM_MODE_RANDOM=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_VENDOR_ADI=y
+CONFIG_NET_VENDOR_ASIX=y
+CONFIG_NET_VENDOR_ENGLEDER=y
+CONFIG_NET_VENDOR_LITEX=y
+CONFIG_NET_VENDOR_SUNPLUS=y
+CONFIG_NET_VENDOR_VERTEXCOM=y
+CONFIG_NET_VENDOR_WANGXUN=y
+CONFIG_NEW_LEDS=y
+CONFIG_NFC_DIGITAL=m
+CONFIG_NFC_FDP_I2C=m
+CONFIG_NFC_FDP=m
+CONFIG_NFC_HCI=m
+CONFIG_NFC=m
+CONFIG_NFC_MICROREAD_I2C=m
+CONFIG_NFC_MICROREAD=m
+CONFIG_NFC_MRVL_I2C=m
+CONFIG_NFC_MRVL=m
+CONFIG_NFC_MRVL_SPI=m
+CONFIG_NFC_MRVL_UART=m
+CONFIG_NFC_MRVL_USB=m
+CONFIG_NFC_NCI=m
+CONFIG_NFC_NCI_SPI=m
+CONFIG_NFC_NCI_UART=m
+CONFIG_NFC_NXP_NCI_I2C=m
+CONFIG_NFC_NXP_NCI=m
+CONFIG_NFC_PN532_UART=m
+CONFIG_NFC_PN533_I2C=m
+CONFIG_NFC_PN533=m
+CONFIG_NFC_PN533_USB=m
+CONFIG_NFC_PN544_I2C=m
+CONFIG_NFC_PN544=m
+CONFIG_NFC_PORT100=m
+CONFIG_NFC_S3FWRN5_I2C=m
+CONFIG_NFC_S3FWRN5=m
+CONFIG_NFC_S3FWRN82_UART=m
+CONFIG_NFC_SHDLC=y
+CONFIG_NFC_SIM=m
+CONFIG_NFC_ST21NFCA_I2C=m
+CONFIG_NFC_ST21NFCA=m
+CONFIG_NFC_ST95HF=m
+CONFIG_NFC_ST_NCI_I2C=m
+CONFIG_NFC_ST_NCI=m
+CONFIG_NFC_ST_NCI_SPI=m
+CONFIG_NFC_TRF7970A=m
+CONFIG_NFC_VIRTUAL_NCI=m
+CONFIG_NF_FLOW_TABLE_PROCFS=y
+CONFIG_NFTL=m
+CONFIG_NFTL_RW=y
+CONFIG_NGBE=m
+CONFIG_N_GSM=m
+CONFIG_N_HDLC=m
+CONFIG_NINTENDO_FF=y
+CONFIG_NL80211_TESTMODE=y
+CONFIG_NLMON=m
+CONFIG_NOA1305=m
+CONFIG_NO_HZ_FULL=y
+CONFIG_NO_HZ=y
+CONFIG_NO_IOPORT_MAP=y
+CONFIG_NOP_TRACER=y
+CONFIG_NOP_USB_XCEIV=m
+CONFIG_NORTEL_HERMES=m
+CONFIG_NOUVEAU_DEBUG=3
+CONFIG_NOUVEAU_DEBUG_DEFAULT=1
+CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT=y
+CONFIG_NOUVEAU_PLATFORM_DRIVER=y
+CONFIG_NOZOMI=m
+CONFIG_NPCM7XX_KCS_IPMI_BMC=m
+CONFIG_NR_CPUS=32
+CONFIG_NSM=m
+CONFIG_NTB_EPF=m
+CONFIG_NTB_IDT=m
+CONFIG_NTB=m
+CONFIG_NTB_MSI_TEST=m
+CONFIG_NTB_MSI=y
+CONFIG_NTB_NETDEV=m
+CONFIG_NTB_PERF=m
+CONFIG_NTB_PINGPONG=m
+CONFIG_NTB_SWITCHTEC=m
+CONFIG_NTB_TOOL=m
+CONFIG_NTB_TRANSPORT=m
+CONFIG_NTSYNC=m
+CONFIG_NULL_TTY=m
+CONFIG_NVGRACE_GPU_VFIO_PCI=m
+CONFIG_NVME_AUTH=y
+CONFIG_NVMEM_IMX_OCOTP_ELE=m
 CONFIG_NVMEM_LAN9662_OTPC=m
+CONFIG_NVMEM_LAYERSCAPE_SFP=m
+CONFIG_NVMEM_LAYOUT_ONIE_TLV=m
+CONFIG_NVMEM_LAYOUT_SL28_VPD=m
+CONFIG_NVMEM_MESON_EFUSE=m
 CONFIG_NVMEM_MESON_MX_EFUSE=m
 CONFIG_NVMEM_MICROCHIP_OTPC=m
 CONFIG_NVMEM_MTK_EFUSE=m
 CONFIG_NVMEM_QCOM_QFPROM=m
+CONFIG_NVMEM_QCOM_SEC_QFPROM=m
 CONFIG_NVMEM_RAVE_SP_EEPROM=m
+CONFIG_NVMEM_REBOOT_MODE=m
+CONFIG_NVMEM_RMEM=m
 CONFIG_NVMEM_ROCKCHIP_EFUSE=m
 CONFIG_NVMEM_ROCKCHIP_OTP=m
 CONFIG_NVMEM_SC27XX_EFUSE=m
-# CONFIG_MTK_EFUSE is not set
-# CONFIG_QCOM_QFPROM is not set
 CONFIG_NVMEM_SPMI_SDAM=m
-# CONFIG_ROCKCHIP_EFUSE is not set
-# CONFIG_ROCKCHIP_OTP is not set
-# CONFIG_NVMEM_STM32_ROMEM is not set
-# CONFIG_NVMEM_SUNXI_SID is not set
+CONFIG_NVMEM_SPRD_EFUSE=m
+CONFIG_NVMEM_SUNPLUS_OCOTP=m
 CONFIG_NVMEM_U_BOOT_ENV=m
 CONFIG_NVMEM_UNIPHIER_EFUSE=m
-# CONFIG_UNIPHIER_EFUSE is not set
-# CONFIG_MESON_MX_EFUSE is not set
-# CONFIG_NVMEM_SNVS_LPGPR is not set
-CONFIG_RAVE_SP_EEPROM=m
-CONFIG_NVMEM_RMEM=m
-CONFIG_NVMEM_LAYERSCAPE_SFP=m
-CONFIG_NVMEM_MESON_EFUSE=m
-CONFIG_NVMEM_SPRD_EFUSE=m
-
-#
-# HW tracing support
-#
-CONFIG_STM=m
-CONFIG_STM_PROTO_BASIC=m
-CONFIG_STM_PROTO_SYS_T=m
-# CONFIG_STM_DUMMY is not set
-CONFIG_STM_SOURCE_CONSOLE=m
-CONFIG_STM_SOURCE_HEARTBEAT=m
-# CONFIG_STM_SOURCE_FTRACE is not set
-# CONFIG_INTEL_TH is not set
-CONFIG_HISI_PTT=m
-# end of HW tracing support
-
-CONFIG_FPGA=m
-CONFIG_FPGA_MGR_SOCFPGA=m
-CONFIG_FPGA_MGR_SOCFPGA_A10=m
-# CONFIG_FPGA_MGR_SOCFPGA is not set
-# CONFIG_FPGA_MGR_SOCFPGA_A10 is not set
-CONFIG_ALTERA_PR_IP_CORE=m
-# CONFIG_ALTERA_PR_IP_CORE_PLAT is not set
-CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
-CONFIG_FPGA_MGR_ALTERA_CVP=m
-# CONFIG_FPGA_MGR_ZYNQ_FPGA is not set
-CONFIG_FPGA_MGR_XILINX_SPI=m
-# CONFIG_FPGA_MGR_ICE40_SPI is not set
-CONFIG_FPGA_MGR_MACHXO2_SPI=m
-CONFIG_FPGA_BRIDGE=m
-# CONFIG_SOCFPGA_FPGA_BRIDGE is not set
-CONFIG_ALTERA_FREEZE_BRIDGE=m
-CONFIG_XILINX_PR_DECOUPLER=m
-CONFIG_FPGA_REGION=m
-# CONFIG_OF_FPGA_REGION is not set
-CONFIG_FPGA_DFL=m
-CONFIG_FPGA_DFL_FME=m
-CONFIG_FPGA_DFL_FME_MGR=m
-CONFIG_FPGA_DFL_FME_BRIDGE=m
-CONFIG_FPGA_DFL_FME_REGION=m
-CONFIG_FPGA_DFL_AFU=m
-CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
-CONFIG_FPGA_DFL_PCI=m
-# CONFIG_FSI is not set
-CONFIG_TEE=m
-
-#
-# TEE drivers
-#
-# CONFIG_OPTEE is not set
-# end of TEE drivers
-
-CONFIG_MULTIPLEXER=m
-
-#
-# Multiplexer drivers
-#
-CONFIG_MUX_ADG792A=m
-CONFIG_MUX_ADGS1408=m
-CONFIG_MUX_GPIO=m
-# CONFIG_MUX_MMIO is not set
-# end of Multiplexer drivers
-
-CONFIG_PM_OPP=y
-CONFIG_SIOX=m
-CONFIG_SIOX_BUS_GPIO=m
-CONFIG_SLIMBUS=m
-CONFIG_SLIM_QCOM_CTRL=m
-# CONFIG_SLIM_QCOM_NGD_CTRL is not set
-CONFIG_INTERCONNECT=y
-CONFIG_INTERCONNECT_IMX=m
-CONFIG_INTERCONNECT_IMX8MM=m
-CONFIG_INTERCONNECT_IMX8MN=m
-CONFIG_INTERCONNECT_IMX8MQ=m
-CONFIG_INTERCONNECT_QCOM=y
-CONFIG_INTERCONNECT_QCOM_OSM_L3=m
-CONFIG_INTERCONNECT_QCOM_QCM2290=m
-CONFIG_INTERCONNECT_SAMSUNG=y
-CONFIG_INTERCONNECT_EXYNOS=m
-CONFIG_COUNTER=m
-CONFIG_INTERRUPT_CNT=m
-CONFIG_INTEL_QEP=m
-CONFIG_TI_ECAP_CAPTURE=m
-# CONFIG_TI_EQEP is not set
-CONFIG_FTM_QUADDEC=m
-CONFIG_MICROCHIP_TCB_CAPTURE=m
-CONFIG_INTEL_QEP=m
-CONFIG_MOST=m
-CONFIG_MOST_USB_HDM=m
-CONFIG_MOST_CDEV=m
-CONFIG_MOST_SND=m
-CONFIG_NETFS_SUPPORT=m
-CONFIG_NETFS_STATS=y
-# end of Device Drivers
-
-#
-# File systems
-#
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_VALIDATE_FS_PARSER=y
-CONFIG_FS_IOMAP=y
-# CONFIG_EXT2_FS is not set
-# CONFIG_EXT3_FS is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_USE_FOR_EXT2=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD2=m
-# CONFIG_JBD2_DEBUG is not set
-CONFIG_FS_MBCACHE=m
-# CONFIG_REISERFS_FS is not set
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_SECURITY=y
-# CONFIG_JFS_DEBUG is not set
-CONFIG_JFS_STATISTICS=y
-CONFIG_XFS_FS=m
-# CONFIG_XFS_SUPPORT_V4 is not set
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_XFS_ONLINE_SCRUB=y
-# CONFIG_XFS_ONLINE_REPAIR is not set
-# CONFIG_XFS_WARN is not set
-# CONFIG_XFS_DEBUG is not set
-CONFIG_GFS2_FS=m
-CONFIG_GFS2_FS_LOCKING_DLM=y
-CONFIG_OCFS2_FS=m
-CONFIG_OCFS2_FS_O2CB=m
-CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
-CONFIG_OCFS2_FS_STATS=y
-CONFIG_OCFS2_DEBUG_MASKLOG=y
-CONFIG_OCFS2_DEBUG_FS=y
-CONFIG_BTRFS_FS=m
-CONFIG_BTRFS_FS_POSIX_ACL=y
-# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
-# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
-# CONFIG_BTRFS_DEBUG is not set
-# CONFIG_BTRFS_ASSERT is not set
-# CONFIG_BTRFS_FS_REF_VERIFY is not set
-CONFIG_NILFS2_FS=m
-CONFIG_F2FS_FS=m
-CONFIG_F2FS_STAT_FS=y
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_FS_POSIX_ACL=y
-CONFIG_F2FS_FS_SECURITY=y
-# CONFIG_F2FS_CHECK_FS is not set
-# CONFIG_F2FS_IO_TRACE is not set
-# CONFIG_F2FS_FAULT_INJECTION is not set
-CONFIG_F2FS_FS_COMPRESSION=y
-CONFIG_F2FS_FS_LZO=y
-CONFIG_F2FS_FS_LZ4=y
-CONFIG_F2FS_FS_LZ4HC=y
-CONFIG_F2FS_FS_ZSTD=y
-CONFIG_F2FS_FS_LZORLE=y
-CONFIG_ZONEFS_FS=m
-CONFIG_FS_POSIX_ACL=y
-CONFIG_EXPORTFS=y
-CONFIG_EXPORTFS_BLOCK_OPS=y
-CONFIG_FILE_LOCKING=y
-CONFIG_MANDATORY_FILE_LOCKING=y
-CONFIG_FS_ENCRYPTION=y
-CONFIG_FS_ENCRYPTION_ALGS=m
-# CONFIG_FS_VERITY is not set
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY_USER=y
-CONFIG_FANOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-# CONFIG_QUOTA_DEBUG is not set
-CONFIG_QUOTA_TREE=m
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=m
-CONFIG_QUOTACTL=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_AUTOFS_FS=y
-CONFIG_FUSE_FS=m
-CONFIG_CUSE=m
-CONFIG_VIRTIO_FS=m
-CONFIG_OVERLAY_FS=m
-CONFIG_OVERLAY_FS_REDIRECT_DIR=y
-CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
-CONFIG_OVERLAY_FS_INDEX=y
-CONFIG_OVERLAY_FS_NFS_EXPORT=y
-# CONFIG_OVERLAY_FS_METACOPY is not set
-
-#
-# Caches
-#
-CONFIG_FSCACHE=m
-CONFIG_FSCACHE_STATS=y
-# CONFIG_FSCACHE_HISTOGRAM is not set
-# CONFIG_FSCACHE_DEBUG is not set
-# CONFIG_FSCACHE_OBJECT_LIST is not set
-CONFIG_CACHEFILES=m
-# CONFIG_CACHEFILES_DEBUG is not set
-# CONFIG_CACHEFILES_HISTOGRAM is not set
-# end of Caches
-
-#
-# CD-ROM/DVD Filesystems
-#
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-# end of CD-ROM/DVD Filesystems
-
-#
-# DOS/FAT/EXFAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
-# CONFIG_FAT_DEFAULT_UTF8 is not set
-CONFIG_EXFAT_FS=m
-CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-CONFIG_NTFS_RW=y
-CONFIG_NTFS3_FS=m
-CONFIG_NTFS3_LZX_XPRESS=y
-CONFIG_NTFS3_FS_POSIX_ACL=y
-# CONFIG_NTFS3_64BIT_CLUSTER is not set
-# end of DOS/FAT/EXFAT/NT Filesystems
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_CHILDREN=y
-CONFIG_KERNFS=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TMPFS_XATTR=y
-# CONFIG_HUGETLBFS is not set
-CONFIG_HUGETLB_PAGE_FREE_VMEMMAP_DEFAULT_ON=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_EFIVAR_FS=m
-# end of Pseudo filesystems
-
-CONFIG_MISC_FILESYSTEMS=y
-CONFIG_ORANGEFS_FS=m
-CONFIG_ADFS_FS=m
-# CONFIG_ADFS_FS_RW is not set
-CONFIG_AFFS_FS=m
-CONFIG_ECRYPT_FS=m
-CONFIG_ECRYPT_FS_MESSAGING=y
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-# CONFIG_BEFS_FS is not set
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RTIME=y
-CONFIG_JFFS2_RUBIN=y
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-CONFIG_UBIFS_FS=m
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UBIFS_FS_ZSTD=y
-CONFIG_UBIFS_ATIME_SUPPORT=y
-CONFIG_UBIFS_FS_XATTR=y
-CONFIG_UBIFS_FS_SECURITY=y
-# CONFIG_UBIFS_FS_AUTHENTICATION is not set
-CONFIG_CRAMFS=m
-CONFIG_CRAMFS_BLOCKDEV=y
-CONFIG_CRAMFS_MTD=y
-CONFIG_SQUASHFS=m
-# CONFIG_SQUASHFS_FILE_CACHE is not set
-CONFIG_SQUASHFS_FILE_DIRECT=y
-# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
-CONFIG_SQUASHFS_DECOMP_MULTI=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_XATTR=y
-CONFIG_SQUASHFS_ZLIB=y
-CONFIG_SQUASHFS_LZ4=y
-CONFIG_SQUASHFS_LZO=y
-CONFIG_SQUASHFS_XZ=y
-CONFIG_SQUASHFS_ZSTD=y
-CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
-CONFIG_SQUASHFS_EMBEDDED=y
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_OMFS_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_QNX6FS_FS=m
-# CONFIG_QNX6FS_DEBUG is not set
-CONFIG_ROMFS_FS=m
-# CONFIG_ROMFS_BACKED_BY_BLOCK is not set
-# CONFIG_ROMFS_BACKED_BY_MTD is not set
-CONFIG_ROMFS_BACKED_BY_BOTH=y
-CONFIG_ROMFS_ON_BLOCK=y
-CONFIG_ROMFS_ON_MTD=y
-CONFIG_PSTORE=m
-CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_LZO_COMPRESS=y
-CONFIG_PSTORE_LZ4_COMPRESS=y
-CONFIG_PSTORE_LZ4HC_COMPRESS=y
-CONFIG_PSTORE_842_COMPRESS=y
-CONFIG_PSTORE_ZSTD_COMPRESS=y
-CONFIG_PSTORE_COMPRESS=y
-# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
-CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="zstd"
-# CONFIG_PSTORE_CONSOLE is not set
-CONFIG_PSTORE_PMSG=y
-# CONFIG_PSTORE_FTRACE is not set
-CONFIG_PSTORE_RAM=m
-CONFIG_PSTORE_ZONE=m
-CONFIG_PSTORE_BLK=m
-CONFIG_PSTORE_BLK_BLKDEV=""
-CONFIG_PSTORE_BLK_KMSG_SIZE=64
-CONFIG_PSTORE_BLK_MAX_REASON=2
-CONFIG_PSTORE_BLK_PMSG_SIZE=64
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-# CONFIG_UFS_FS_WRITE is not set
-# CONFIG_UFS_DEBUG is not set
-CONFIG_EROFS_FS=m
-# CONFIG_EROFS_FS_DEBUG is not set
-CONFIG_EROFS_FS_XATTR=y
-CONFIG_EROFS_FS_POSIX_ACL=y
-# CONFIG_EROFS_FS_SECURITY is not set
-# CONFIG_EROFS_FS_ZIP is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V2=m
-CONFIG_NFS_V3=m
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=m
-CONFIG_NFS_SWAP=y
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_V4_2=y
-CONFIG_PNFS_FILE_LAYOUT=m
-CONFIG_PNFS_BLOCK=m
-CONFIG_PNFS_FLEXFILE_LAYOUT=m
-CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
-CONFIG_NFS_V4_1_MIGRATION=y
-CONFIG_NFS_FSCACHE=y
-# CONFIG_NFS_USE_LEGACY_DNS is not set
-CONFIG_NFS_USE_KERNEL_DNS=y
-CONFIG_NFS_DISABLE_UDP_SUPPORT=y
-CONFIG_NFS_V4_2_READ_PLUS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V2_ACL=y
-CONFIG_NFSD_V3=y
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_PNFS=y
-CONFIG_NFSD_BLOCKLAYOUT=y
-CONFIG_NFSD_SCSILAYOUT=y
-CONFIG_NFSD_FLEXFILELAYOUT=y
-CONFIG_NFSD_V4_2_INTER_SSC=y
-CONFIG_GRACE_PERIOD=m
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_ACL_SUPPORT=m
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_SUNRPC_BACKCHANNEL=y
-CONFIG_SUNRPC_SWAP=y
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
-# CONFIG_SUNRPC_DEBUG is not set
-CONFIG_SUNRPC_XPRT_RDMA=m
-CONFIG_CEPH_FS=m
-CONFIG_CEPH_FSCACHE=y
-CONFIG_CEPH_FS_POSIX_ACL=y
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS2=y
-CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
-CONFIG_CIFS_WEAK_PW_HASH=y
-CONFIG_CIFS_UPCALL=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-# CONFIG_CIFS_DEBUG is not set
-CONFIG_CIFS_DFS_UPCALL=y
-CONFIG_CIFS_SWN_UPCALL=y
-# CONFIG_CIFS_SMB_DIRECT is not set
-CONFIG_CIFS_FSCACHE=y
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-# CONFIG_AFS_DEBUG is not set
-CONFIG_AFS_FSCACHE=y
-# CONFIG_AFS_DEBUG_CURSOR is not set
-CONFIG_9P_FS=m
-CONFIG_9P_FSCACHE=y
-CONFIG_9P_FS_POSIX_ACL=y
-CONFIG_9P_FS_SECURITY=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_MAC_ROMAN=m
-CONFIG_NLS_MAC_CELTIC=m
-CONFIG_NLS_MAC_CENTEURO=m
-CONFIG_NLS_MAC_CROATIAN=m
-CONFIG_NLS_MAC_CYRILLIC=m
-CONFIG_NLS_MAC_GAELIC=m
-CONFIG_NLS_MAC_GREEK=m
-CONFIG_NLS_MAC_ICELAND=m
-CONFIG_NLS_MAC_INUIT=m
-CONFIG_NLS_MAC_ROMANIAN=m
-CONFIG_NLS_MAC_TURKISH=m
-CONFIG_NLS_UTF8=m
-CONFIG_DLM=m
-# CONFIG_DLM_DEPRECATED_API is not set
-# CONFIG_DLM_DEBUG is not set
-CONFIG_UNICODE=y
-CONFIG_UNICODE_NORMALIZATION_SELFTEST=m
-CONFIG_IO_WQ=y
-# end of File systems
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-# CONFIG_KEYS_REQUEST_CACHE is not set
+CONFIG_NVME_TARGET_AUTH=y
+CONFIG_NVM_PBLK=m
+CONFIG_NVM=y
+CONFIG_NXP_C45_TJA11XX_PHY=m
+CONFIG_NXP_CBTX_PHY=m
+CONFIG_NXP_TJA11XX_PHY=m
+CONFIG_OBJAGG=m
+CONFIG_OCTEONEP_VDPA=m
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OF_RESOLVE=y
+CONFIG_OF=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OMAP2_DSS_DPI=y
+CONFIG_OMAP2_DSS_DSI=y
+CONFIG_OMAP2_DSS_HDMI_COMMON=y
+CONFIG_OMAP2_DSS_INIT=y
+CONFIG_OMAP2_DSS=m
+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
+CONFIG_OMAP2_DSS_SDI=y
+CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y
+CONFIG_OMAP2_DSS_VENC=y
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP3_SDRC_AC_TIMING=y
+CONFIG_OMAP4_DSS_HDMI_CEC=y
+CONFIG_OMAP4_DSS_HDMI=y
+CONFIG_OMAP5_DSS_HDMI=y
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_DSS_BASE=m
+CONFIG_OMAP_GPMC=y
+CONFIG_OMAP_INTERCONNECT_BARRIER=y
+CONFIG_OMAP_INTERCONNECT=y
+CONFIG_OMAP_IRQCHIP=y
+CONFIG_OMAP_PACKAGE_CBB=y
+CONFIG_OPEN_DICE=m
+CONFIG_OPT3001=m
+CONFIG_OPT4001=m
+CONFIG_OPT4060=m
+CONFIG_OPTPROBES=y
+CONFIG_ORINOCO_USB=m
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OVPN=m
+CONFIG_OWL_PM_DOMAINS_HELPER=y
+CONFIG_OWL_TIMER=y
+CONFIG_P54_COMMON=m
+CONFIG_P54_LEDS=y
+CONFIG_P54_PCI=m
+CONFIG_P54_SPI_DEFAULT_EEPROM=y
+CONFIG_P54_SPI=m
+CONFIG_P54_USB=m
+CONFIG_PA12203001=m
+CONFIG_PAC1921=m
+CONFIG_PAC1934=m
+CONFIG_PACKING=y
+CONFIG_PADATA=y
+CONFIG_PAGE_BLOCK_MAX_ORDER=12
+CONFIG_PAGE_BLOCK_ORDER=12
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PANEL=m
+CONFIG_PANEL_PARPORT=0
+CONFIG_PANEL_PROFILE=5
+CONFIG_PANIC_TIMEOUT=60
+CONFIG_PARAVIRT=y
+CONFIG_PARMAN=m
+CONFIG_PARPORT_1284=y
+CONFIG_PARPORT_AX88796=m
+CONFIG_PARPORT=m
+CONFIG_PARPORT_NOT_PC=y
+CONFIG_PARPORT_PANEL=m
+CONFIG_PARPORT_PC_FIFO=y
+CONFIG_PARPORT_PC=m
+CONFIG_PARPORT_PC_PCMCIA=m
+CONFIG_PARPORT_PC_SUPERIO=y
+CONFIG_PARPORT_SERIAL=m
+CONFIG_PATA_NINJA32=m
+CONFIG_PATA_OF_PLATFORM=m
+CONFIG_PATA_SIS=m
+CONFIG_PATA_TOSHIBA=m
+CONFIG_PC300TOO=m
+CONFIG_PCCARD=m
+CONFIG_PCCARD_NONSTATIC=y
+CONFIG_PCF50633_ADC=m
+CONFIG_PCF50633_GPIO=m
+CONFIG_PCI200SYN=m
+CONFIG_PCI_ATMEL=m
+CONFIG_PCI_ATS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_DYNAMIC_OF_NODES=y
+CONFIG_PCIEAER_CXL=y
+CONFIG_PCIEAER=y
+CONFIG_PCIE_ALTERA=m
+CONFIG_PCIE_ALTERA_MSI=m
+CONFIG_PCIEASPM_DEFAULT=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIE_BRCMSTB=m
+CONFIG_PCIE_BUS_DEFAULT=y
+CONFIG_PCIE_CADENCE_EP=y
+CONFIG_PCIE_CADENCE_HOST=y
+CONFIG_PCIE_CADENCE_PLAT_EP=y
+CONFIG_PCIE_CADENCE_PLAT_HOST=y
+CONFIG_PCIE_CADENCE_PLAT=y
+CONFIG_PCIE_CADENCE=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCIE_DPC=y
+CONFIG_PCIE_DW_EP=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_DW_PLAT_EP=y
+CONFIG_PCIE_DW_PLAT_HOST=y
+CONFIG_PCIE_DW_PLAT=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_ECRC=y
+CONFIG_PCIE_MEDIATEK_GEN3=m
+CONFIG_PCIE_MICROCHIP_HOST=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_ENDPOINT_MSI_DOORBELL=y
+CONFIG_PCI_ENDPOINT_TEST=m
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_EPF_MHI=m
+CONFIG_PCI_EPF_NTB=m
+CONFIG_PCI_EPF_VNTB=m
+CONFIG_PCIE_PME=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_PTM=y
+CONFIG_PCIE_QCOM_EP=m
+CONFIG_PCIE_RCAR_GEN4_EP=m
+CONFIG_PCIE_RCAR_GEN4_HOST=m
+CONFIG_PCIE_ROCKCHIP_DW_EP=y
+CONFIG_PCIE_ROCKCHIP_DW_HOST=y
+CONFIG_PCIE_STM32_EP=m
+CONFIG_PCIE_STM32_HOST=m
+CONFIG_PCIE_XILINX_DMA_PL=y
+CONFIG_PCIE_XILINX=y
+CONFIG_PCI_EXYNOS=m
+CONFIG_PCI_FTPCI100=y
+CONFIG_PCI_HERMES=m
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_IMX6_EP=y
+CONFIG_PCI_IMX6_HOST=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_J721E_EP=y
+CONFIG_PCI_J721E_HOST=y
+CONFIG_PCI_J721E=y
+CONFIG_PCI_LAYERSCAPE_EP=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_MESON=y
+CONFIG_PCI_MSI_ARCH_FALLBACKS=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_PASID=y
+CONFIG_PCIPCWATCHDOG=m
+CONFIG_PCI_PF_STUB=m
+CONFIG_PCI_PRI=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCI_STUB=m
+CONFIG_PCI_SW_SWITCHTEC=m
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCI_V3_SEMI=y
+CONFIG_PCMCIA_AHA152X=m
+CONFIG_PCMCIA_ATMEL=m
+CONFIG_PCMCIA_FDOMAIN=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_QLOGIC=m
+CONFIG_PCMCIA_RAYCS=m
+CONFIG_PCMCIA_SYM53C500=m
+CONFIG_PCMCIA_WL3501=m
+CONFIG_PCS_LYNX=m
+CONFIG_PCS_XPCS=m
+CONFIG_PD6729=m
+CONFIG_PDA_POWER=m
+CONFIG_PDC_ADMA=m
+CONFIG_PDS_VFIO_PCI=m
+CONFIG_PECI_ASPEED=m
+CONFIG_PECI_CPU=m
+CONFIG_PECI=m
+CONFIG_PECI_NPCM=m
+CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PERSISTENT_KEYRINGS=y
-CONFIG_TRUSTED_KEYS=m
-CONFIG_ENCRYPTED_KEYS=m
-CONFIG_USER_DECRYPTED_DATA=y
-# CONFIG_KEY_DH_OPERATIONS is not set
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-# CONFIG_SECURITY is not set
-CONFIG_SECURITYFS=y
-CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
-CONFIG_HARDENED_USERCOPY=y
-CONFIG_HARDENED_USERCOPY_FALLBACK=y
-# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
-CONFIG_FORTIFY_SOURCE=y
-# CONFIG_STATIC_USERMODEHELPER is not set
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_LSM="yama,loadpin,safesetid,integrity,bpf"
-
-#
-# Kernel hardening options
-#
-
-#
-# Memory initialization
-#
-CONFIG_INIT_STACK_NONE=y
-# CONFIG_INIT_STACK_ALL_PATTERN is not set
-# CONFIG_INIT_STACK_ALL_ZERO is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
-# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
-# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
-# end of Memory initialization
-# end of Kernel hardening options
-# end of Security options
-
-CONFIG_XOR_BLOCKS=m
-CONFIG_ASYNC_CORE=m
-CONFIG_ASYNC_MEMCPY=m
-CONFIG_ASYNC_XOR=m
-CONFIG_ASYNC_PQ=m
-CONFIG_ASYNC_RAID6_RECOV=m
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=m
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_SKCIPHER=y
-CONFIG_CRYPTO_SKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG=m
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=m
-CONFIG_CRYPTO_AKCIPHER2=y
-CONFIG_CRYPTO_AKCIPHER=y
-CONFIG_CRYPTO_KPP2=y
-CONFIG_CRYPTO_KPP=m
-CONFIG_CRYPTO_ACOMP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_USER=m
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_PCRYPT=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_SIMD=m
-CONFIG_CRYPTO_ENGINE=m
-
-#
-# Public-key cryptography
-#
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_DH=m
-CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
-CONFIG_CRYPTO_ECC=m
-CONFIG_CRYPTO_ECDH=m
-CONFIG_CRYPTO_ECDSA=m
-CONFIG_CRYPTO_ECRDSA=m
-CONFIG_CRYPTO_SM2=m
-CONFIG_CRYPTO_CURVE25519=m
-
-#
-# Authenticated Encryption with Associated Data
-#
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_GCM=m
-CONFIG_CRYPTO_CHACHA20POLY1305=m
-CONFIG_CRYPTO_AEGIS128=m
-CONFIG_CRYPTO_AEGIS128_SIMD=y
-CONFIG_CRYPTO_SEQIV=m
-CONFIG_CRYPTO_ECHAINIV=m
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CFB=m
-CONFIG_CRYPTO_CTR=m
-CONFIG_CRYPTO_CTS=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_OFB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_KEYWRAP=m
-CONFIG_CRYPTO_NHPOLY1305=m
-CONFIG_CRYPTO_ADIANTUM=m
-CONFIG_CRYPTO_HCTR2=m
-CONFIG_CRYPTO_ARIA=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
-CONFIG_CRYPTO_DEV_QAT_C3XXX=m
-CONFIG_CRYPTO_DEV_QAT_C62X=m
-CONFIG_CRYPTO_DEV_QAT_4XXX=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
-CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
-CONFIG_CRYPTO_DEV_QAT_C62XVF=m
-CONFIG_CRYPTO_ESSIV=m
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_CMAC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CRC32=m
-CONFIG_CRYPTO_XXHASH=m
-CONFIG_CRYPTO_BLAKE2B=m
-CONFIG_CRYPTO_BLAKE2S=m
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_GHASH=m
-CONFIG_CRYPTO_POLY1305=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_RMD128=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_RMD256=m
-CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SHA3=m
-CONFIG_CRYPTO_SM3_NEON=m
-CONFIG_CRYPTO_SM3=m
-# CONFIG_CRYPTO_STREEBOG is not set
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_AES_TI=m
-CONFIG_CRYPTO_ANUBIS=m
-# CONFIG_CRYPTO_ARC4 is not set
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_BLOWFISH_COMMON=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST_COMMON=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SALSA20=m
-CONFIG_CRYPTO_CHACHA20=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_SM4=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_842=y
-CONFIG_CRYPTO_LZ4=y
-CONFIG_CRYPTO_LZ4HC=y
-CONFIG_CRYPTO_ZSTD=y
-
-#
-# Random Number Generation
-#
-CONFIG_CRYPTO_ANSI_CPRNG=m
-CONFIG_CRYPTO_DRBG_MENU=m
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_HASH=y
-CONFIG_CRYPTO_DRBG_CTR=y
-CONFIG_CRYPTO_DRBG=m
-CONFIG_CRYPTO_JITTERENTROPY=m
-CONFIG_CRYPTO_USER_API=m
-CONFIG_CRYPTO_USER_API_HASH=y
-CONFIG_CRYPTO_USER_API_SKCIPHER=m
-CONFIG_CRYPTO_USER_API_RNG=m
-# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
-CONFIG_CRYPTO_USER_API_AEAD=m
-CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
-# CONFIG_CRYPTO_STATS is not set
-CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=m
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_DEV_ALLWINNER=y
-# CONFIG_CRYPTO_DEV_SUN4I_SS is not set
-# CONFIG_CRYPTO_DEV_SUN8I_CE is not set
-# CONFIG_CRYPTO_DEV_SUN8I_SS is not set
-# CONFIG_CRYPTO_DEV_FSL_CAAM is not set
-# CONFIG_CRYPTO_DEV_OMAP is not set
-# CONFIG_CRYPTO_DEV_SAHARA is not set
-# CONFIG_CRYPTO_DEV_EXYNOS_RNG is not set
-# CONFIG_CRYPTO_DEV_S5P is not set
-# CONFIG_CRYPTO_DEV_UX500 is not set
-# CONFIG_CRYPTO_DEV_ATMEL_AES is not set
-# CONFIG_CRYPTO_DEV_ATMEL_TDES is not set
-# CONFIG_CRYPTO_DEV_ATMEL_SHA is not set
-CONFIG_CRYPTO_DEV_ATMEL_I2C=m
-CONFIG_CRYPTO_DEV_ATMEL_ECC=m
-CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
-# CONFIG_CRYPTO_DEV_MXS_DCP is not set
-# CONFIG_CRYPTO_DEV_MARVELL_CESA is not set
-# CONFIG_CRYPTO_DEV_QCE is not set
-# CONFIG_CRYPTO_DEV_QCOM_RNG is not set
-# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
-# CONFIG_CRYPTO_DEV_MEDIATEK is not set
-CONFIG_CRYPTO_DEV_CHELSIO=m
-CONFIG_CRYPTO_DEV_VIRTIO=m
-# CONFIG_CRYPTO_DEV_STM32_CRC is not set
-# CONFIG_CRYPTO_DEV_STM32_HASH is not set
-# CONFIG_CRYPTO_DEV_STM32_CRYP is not set
-CONFIG_CRYPTO_DEV_SAFEXCEL=m
-# CONFIG_CRYPTO_DEV_ARTPEC6 is not set
-# CONFIG_CRYPTO_DEV_CCREE is not set
-CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
-CONFIG_CRYPTO_DEV_ASPEED=m
-# CONFIG_CRYPTO_DEV_ASPEED_DEBUG is not set
-CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH=y
-CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO=y
-# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set
-CONFIG_ASYMMETRIC_KEY_TYPE=y
-CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
-CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE=m
-CONFIG_X509_CERTIFICATE_PARSER=y
-CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
-CONFIG_TPM_KEY_PARSER=m
-CONFIG_PKCS7_MESSAGE_PARSER=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHANTOM=m
+CONFIG_PHY_BRCM_SATA=m
+CONFIG_PHY_BRCM_USB=m
+CONFIG_PHY_CADENCE_DPHY_RX=m
+CONFIG_PHY_CAN_TRANSCEIVER=m
+CONFIG_PHY_CPCAP_USB=m
+CONFIG_PHY_EXYNOS4210_USB2=y
+CONFIG_PHY_EXYNOS4X12_USB2=y
+CONFIG_PHY_EXYNOS5250_USB2=y
+CONFIG_PHY_EXYNOS5_USBDRD=m
+CONFIG_PHY_EXYNOS_DP_VIDEO=y
+CONFIG_PHY_EXYNOS_MIPI_VIDEO=y
+CONFIG_PHY_FSL_IMX8M_PCIE=m
+CONFIG_PHY_FSL_LYNX_28G=m
+CONFIG_PHY_HISI_INNO_USB2=m
+CONFIG_PHY_LAN966X_SERDES=m
+CONFIG_PHY_MESON8B_USB2=y
+CONFIG_PHY_MESON8_HDMI_TX=m
+CONFIG_PHY_MESON_AXG_MIPI_DPHY=m
+CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
+CONFIG_PHY_MESON_AXG_PCIE=y
+CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=m
+CONFIG_PHY_MESON_G12A_USB2=y
+CONFIG_PHY_MESON_G12A_USB3_PCIE=y
+CONFIG_PHY_MESON_GXL_USB2=y
+CONFIG_PHY_MIXEL_LVDS_PHY=m
+CONFIG_PHY_MTK_DP=m
+CONFIG_PHY_MTK_HDMI=m
+CONFIG_PHY_MTK_MIPI_CSI_0_5=m
+CONFIG_PHY_MTK_MIPI_DSI=m
+CONFIG_PHY_MTK_PCIE=m
+CONFIG_PHY_MTK_XFI_TPHY=m
+CONFIG_PHY_MVEBU_A3700_COMPHY=y
+CONFIG_PHY_MVEBU_A3700_UTMI=y
+CONFIG_PHY_MVEBU_CP110_UTMI=m
+CONFIG_PHY_PXA_28NM_HSIC=m
+CONFIG_PHY_PXA_28NM_USB2=m
+CONFIG_PHY_QCOM_EDP=m
+CONFIG_PHY_QCOM_EUSB2_REPEATER=m
+CONFIG_PHY_QCOM_IPQ806X_USB=m
+CONFIG_PHY_QCOM_M31_EUSB=m
+CONFIG_PHY_QCOM_M31_USB=m
+CONFIG_PHY_QCOM_QMP_COMBO=m
+CONFIG_PHY_QCOM_QMP_PCIE_8996=m
+CONFIG_PHY_QCOM_QMP_PCIE=m
+CONFIG_PHY_QCOM_QMP_UFS=m
+CONFIG_PHY_QCOM_QMP_USB_LEGACY=m
+CONFIG_PHY_QCOM_QMP_USB=m
+CONFIG_PHY_QCOM_SGMII_ETH=m
+CONFIG_PHY_QCOM_SNPS_EUSB2=m
+CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP=y
+CONFIG_PHY_QCOM_USB_HSIC=m
+CONFIG_PHY_QCOM_USB_HS=m
+CONFIG_PHY_R8A779F0_ETHERNET_SERDES=m
+CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
+CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY=m
+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=m
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m
+CONFIG_PHY_ROCKCHIP_USBDP=m
+CONFIG_PHY_RTK_RTD_USB2PHY=m
+CONFIG_PHY_RTK_RTD_USB3PHY=m
+CONFIG_PHY_SAMSUNG_UFS=m
+CONFIG_PHY_SAMSUNG_USB2=m
+CONFIG_PHY_SPARX5_SERDES=m
+CONFIG_PHY_ST_SPEAR1310_MIPHY=y
+CONFIG_PHY_ST_SPEAR1340_MIPHY=y
+CONFIG_PHY_SUNPLUS_USB=m
+CONFIG_PHY_TUSB1210=m
+CONFIG_PHY_UNIPHIER_AHCI=m
+CONFIG_PI433=m
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_AB8500=y
+CONFIG_PINCTRL_AB8505=y
+CONFIG_PINCTRL_ABX500=y
+CONFIG_PINCTRL_AMDISP=m
+CONFIG_PINCTRL_APPLE_GPIO=m
+CONFIG_PINCTRL_AW9523=m
+CONFIG_PINCTRL_AXP209=m
+CONFIG_PINCTRL_BCM4908=m
+CONFIG_PINCTRL_CS42L43=m
+CONFIG_PINCTRL_CS47L15=y
+CONFIG_PINCTRL_CS47L35=y
+CONFIG_PINCTRL_CS47L85=y
+CONFIG_PINCTRL_CS47L90=y
+CONFIG_PINCTRL_CS47L92=y
+CONFIG_PINCTRL_CY8C95X0=m
+CONFIG_PINCTRL_DA9062=m
+CONFIG_PINCTRL_DB8500=y
+CONFIG_PINCTRL_DIGICOLOR=y
+CONFIG_PINCTRL_EXYNOS_ARM=y
+CONFIG_PINCTRL_EXYNOS=y
+CONFIG_PINCTRL_IMX8ULP=m
+CONFIG_PINCTRL_IMX91=m
+CONFIG_PINCTRL_IMX93=m
+CONFIG_PINCTRL_IMXRT1050=y
+CONFIG_PINCTRL_IMXRT1170=y
+CONFIG_PINCTRL_IMX_SCMI=m
+CONFIG_PINCTRL_IPQ5332=m
+CONFIG_PINCTRL_IPQ9574=m
+CONFIG_PINCTRL_LPASS_LPI=m
+CONFIG_PINCTRL_MADERA=m
+CONFIG_PINCTRL_MAX7360=m
+CONFIG_PINCTRL_MCP23S08_I2C=m
+CONFIG_PINCTRL_MCP23S08=m
+CONFIG_PINCTRL_MCP23S08_SPI=m
+CONFIG_PINCTRL_MDM9607=m
+CONFIG_PINCTRL_MESON8B=y
+CONFIG_PINCTRL_MESON8_PMX=y
+CONFIG_PINCTRL_MESON8=y
+CONFIG_PINCTRL_MESON=y
+CONFIG_PINCTRL_MICROCHIP_SGPIO=y
+CONFIG_PINCTRL_MSM8226=m
+CONFIG_PINCTRL_MSM8909=m
+CONFIG_PINCTRL_MSM8917=m
+CONFIG_PINCTRL_MSM8953=m
+CONFIG_PINCTRL_MSM=y
+CONFIG_PINCTRL_MT2701=y
+CONFIG_PINCTRL_MT6397=y
+CONFIG_PINCTRL_MT7623=y
+CONFIG_PINCTRL_MT7629=y
+CONFIG_PINCTRL_MT7981=y
+CONFIG_PINCTRL_MT8127=y
+CONFIG_PINCTRL_MT8135=y
+CONFIG_PINCTRL_MT8195=y
+CONFIG_PINCTRL_MT8365=y
+CONFIG_PINCTRL_MTK_MOORE=y
+CONFIG_PINCTRL_MTK_V2=y
+CONFIG_PINCTRL_MTK=y
+CONFIG_PINCTRL_NOMADIK=y
+CONFIG_PINCTRL_NPCM8XX=m
+CONFIG_PINCTRL_PEF2256=m
+CONFIG_PINCTRL_QCM2290=m
+CONFIG_PINCTRL_QDU1000=m
+CONFIG_PINCTRL_RENESAS=y
+CONFIG_PINCTRL_ROCKCHIP=y
+CONFIG_PINCTRL_RP1=m
+CONFIG_PINCTRL_RTD1315E=m
+CONFIG_PINCTRL_RTD1319D=m
+CONFIG_PINCTRL_RTD1619B=m
+CONFIG_PINCTRL_RTD=m
+CONFIG_PINCTRL_S32G2=y
+CONFIG_PINCTRL_SA8775P=m
+CONFIG_PINCTRL_SAMSUNG=y
+CONFIG_PINCTRL_SC7280_LPASS_LPI=m
+CONFIG_PINCTRL_SC7280=m
+CONFIG_PINCTRL_SC8180X=m
+CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
+CONFIG_PINCTRL_SC8280XP=m
+CONFIG_PINCTRL_SCMI=m
+CONFIG_PINCTRL_SDM670=m
+CONFIG_PINCTRL_SDX55=m
+CONFIG_PINCTRL_SDX65=m
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_SIRF=y
+CONFIG_PINCTRL_SM6115_LPASS_LPI=m
+CONFIG_PINCTRL_SM6115=m
+CONFIG_PINCTRL_SM6125=m
+CONFIG_PINCTRL_SM6350=m
+CONFIG_PINCTRL_SM6375=m
+CONFIG_PINCTRL_SM7150=m
+CONFIG_PINCTRL_SM8250_LPASS_LPI=m
+CONFIG_PINCTRL_SM8280XP_LPASS_LPI=m
+CONFIG_PINCTRL_SM8350_LPASS_LPI=m
+CONFIG_PINCTRL_SM8350=m
+CONFIG_PINCTRL_SM8450_LPASS_LPI=m
+CONFIG_PINCTRL_SM8450=m
+CONFIG_PINCTRL_SM8550_LPASS_LPI=m
+CONFIG_PINCTRL_SM8550=m
+CONFIG_PINCTRL_SPEAR1310=y
+CONFIG_PINCTRL_SPEAR1340=y
+CONFIG_PINCTRL_SPEAR_PLGPIO=y
+CONFIG_PINCTRL_SPEAR=y
+CONFIG_PINCTRL_STM32_HDP=m
+CONFIG_PINCTRL_STM32MP157=y
+CONFIG_PINCTRL_STM32MP257=m
+CONFIG_PINCTRL_STM32=y
+CONFIG_PINCTRL_STMFX=m
+CONFIG_PINCTRL_ST=y
+CONFIG_PINCTRL_SUN20I_D1=y
+CONFIG_PINCTRL_SUN4I_A10=y
+CONFIG_PINCTRL_SUN50I_A100_R=y
+CONFIG_PINCTRL_SUN50I_A100=y
+CONFIG_PINCTRL_SUN50I_H616_R=y
+CONFIG_PINCTRL_SUN50I_H616=y
+CONFIG_PINCTRL_SUN55I_A523_R=y
+CONFIG_PINCTRL_SUN55I_A523=y
+CONFIG_PINCTRL_SUN5I=y
+CONFIG_PINCTRL_SUN6I_A31_R=y
+CONFIG_PINCTRL_SUN6I_A31=y
+CONFIG_PINCTRL_SUN8I_A23_R=y
+CONFIG_PINCTRL_SUN8I_A23=y
+CONFIG_PINCTRL_SUN8I_A33=y
+CONFIG_PINCTRL_SUN8I_A83T_R=y
+CONFIG_PINCTRL_SUN8I_A83T=y
+CONFIG_PINCTRL_SUN8I_H3_R=y
+CONFIG_PINCTRL_SUN8I_H3=y
+CONFIG_PINCTRL_SUN8I_V3S=y
+CONFIG_PINCTRL_SUN9I_A80_R=y
+CONFIG_PINCTRL_SUN9I_A80=y
+CONFIG_PINCTRL_SUNXI=y
+CONFIG_PINCTRL_TEGRA_XUSB=y
+CONFIG_PINCTRL_TI_IODELAY=y
+CONFIG_PINCTRL_TPS6594=m
+CONFIG_PINCTRL_UNIPHIER_LD4=y
+CONFIG_PINCTRL_UNIPHIER_LD6B=y
+CONFIG_PINCTRL_UNIPHIER_NX1=y
+CONFIG_PINCTRL_UNIPHIER_PRO4=y
+CONFIG_PINCTRL_UNIPHIER_PRO5=y
+CONFIG_PINCTRL_UNIPHIER_PXS2=y
+CONFIG_PINCTRL_UNIPHIER_SLD8=y
+CONFIG_PINCTRL_UNIPHIER=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ZYNQ=y
+CONFIG_PING=m
+CONFIG_PINMUX=y
 CONFIG_PKCS7_TEST_KEY=m
-CONFIG_SIGNED_PE_FILE_VERIFICATION=y
-
-#
-# Certificates for signature checking
-#
-CONFIG_SYSTEM_TRUSTED_KEYRING=y
-CONFIG_SYSTEM_TRUSTED_KEYS=""
-# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
-CONFIG_SECONDARY_TRUSTED_KEYRING=y
-CONFIG_SYSTEM_BLACKLIST_KEYRING=y
-# CONFIG_SYSTEM_REVOCATION_LIST is not set
-CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
-# end of Certificates for signature checking
-
-CONFIG_BINARY_PRINTF=y
-
-#
-# Library routines
-#
+CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_PL310_ERRATA_753970=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PL320_MBOX=y
+CONFIG_PL330_DMA=y
+CONFIG_PL353_SMC=y
+CONFIG_PLATFORM_SI4713=m
+CONFIG_PLAT_ORION=y
+CONFIG_PLAT_PXA=y
+CONFIG_PLAT_SPEAR=y
+CONFIG_PLAT_VERSATILE=y
+CONFIG_PLDMFW=y
+CONFIG_PLFXLC=m
+CONFIG_PLIP=m
+CONFIG_PLX_DMA=m
+CONFIG_PLX_HERMES=m
+CONFIG_PM_AUTOSLEEP=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PMIC_DA9052=y
+CONFIG_PM_OPP=y
+CONFIG_PMS7003=m
+CONFIG_PM_STD_PARTITION=""
+CONFIG_PM_WAKELOCKS_GC=y
+CONFIG_PM_WAKELOCKS_LIMIT=100
+CONFIG_PM_WAKELOCKS=y
+CONFIG_POWERCAP=y
+CONFIG_POWER_MLXBF=m
+CONFIG_POWER_RESET_ATC260X=m
+CONFIG_POWER_RESET_BRCMKONA=y
+CONFIG_POWER_RESET_BRCMSTB=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_HISI=y
+CONFIG_POWER_RESET_LINKSTATION=m
+CONFIG_POWER_RESET_LTC2952=y
+CONFIG_POWER_RESET_MACSMC=m
+CONFIG_POWER_RESET_MT6323=y
+CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF=y
+CONFIG_POWER_RESET_REGULATOR=y
+CONFIG_POWER_RESET_RESTART=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_TORADEX_EC=m
+CONFIG_POWER_RESET_TPS65086=y
+CONFIG_POWER_RESET_VERSATILE=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPDEV=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOATM=m
+CONFIG_PPPOE_HASH_BITS_4=y
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPS_CLIENT_GPIO=m
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PPS_CLIENT_PARPORT=m
+CONFIG_PPS=y
+CONFIG_PPTP=m
+CONFIG_PREEMPT_COUNT=y
+CONFIG_PREEMPT_DYNAMIC=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPTIRQ_DELAY_TEST=m
+CONFIG_PREEMPT_RCU=y
+CONFIG_PREEMPT=y
+CONFIG_PRIMA2_TIMER=y
+CONFIG_PRIME_NUMBERS=m
+CONFIG_PRINTER=m
+CONFIG_PRINTK_INDEX=y
+CONFIG_PRINTK_NMI=y
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
+CONFIG_PRISM2_USB=m
+CONFIG_PRISM54=m
+CONFIG_PROBE_EVENTS=y
+CONFIG_PSAMPLE=m
+CONFIG_PSE_CONTROLLER=y
+CONFIG_PSE_PD692X0=m
+CONFIG_PSE_REGULATOR=m
+CONFIG_PSE_SI3474=m
+CONFIG_PSE_TPS23881=m
+CONFIG_PSI=y
+CONFIG_PTP_1588_CLOCK_FC3W=m
+CONFIG_PTP_1588_CLOCK_IDT82P33=m
+CONFIG_PTP_1588_CLOCK_IDTCM=m
+CONFIG_PTP_1588_CLOCK_INES=m
+CONFIG_PTP_1588_CLOCK_KVM=m
+CONFIG_PTP_1588_CLOCK_MOCK=m
+CONFIG_PTP_1588_CLOCK_OCP=m
+CONFIG_PTP_1588_CLOCK_QORIQ=m
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_DFL_TOD=m
+CONFIG_PTP_NETC_V4_TIMER=m
+CONFIG_PVPANIC=m
+CONFIG_PVPANIC_MMIO=m
+CONFIG_PVPANIC_PCI=m
+CONFIG_PVPANIC=y
+CONFIG_PWM_ADP5585=m
+CONFIG_PWM_ATMEL_TCB=m
+CONFIG_PWM_AXI_PWMGEN=m
+CONFIG_PWM_CLK=m
+CONFIG_PWM_CROS_EC=m
+CONFIG_PWM_DWC=m
+CONFIG_PWM_GPIO=m
+CONFIG_PWM_IQS620A=m
+CONFIG_PWM_LP3943=m
+CONFIG_PWM_MAX7360=m
+CONFIG_PWM_NTXEC=m
+CONFIG_PWM_PCA9685=m
+CONFIG_PWM_PROVIDE_GPIO=y
+CONFIG_PWM_PXA=m
+CONFIG_PWM_RASPBERRYPI_POE=m
+CONFIG_PWM_SL28CPLD=m
+CONFIG_PWM_SUNPLUS=m
+CONFIG_PWM_SYSFS=y
+CONFIG_PWM_VISCONTI=m
+CONFIG_PWM_XILINX=m
+CONFIG_PWM=y
+CONFIG_PWRSEQ_EMMC=m
+CONFIG_PWRSEQ_SD8787=m
+CONFIG_PWRSEQ_SIMPLE=m
+CONFIG_PXA1908_PM_DOMAINS=m
+CONFIG_PXA_SSP=m
+CONFIG_QAT_VFIO_PCI=m
+CONFIG_QCA807X_PHY=m
+CONFIG_QCA808X_PHY=m
+CONFIG_QCA83XX_PHY=m
+CONFIG_QCOM_BAM_DMUX=m
+CONFIG_QCOM_CPR=m
+CONFIG_QCOM_EBI2=y
+CONFIG_QCOM_GPI_DMA=m
+CONFIG_QCOM_HIDMA=m
+CONFIG_QCOM_HIDMA_MGMT=m
+CONFIG_QCOM_ICC_BWMON=m
+CONFIG_QCOM_LMH=m
+CONFIG_QCOM_MPM=m
+CONFIG_QCOM_PBS=m
+CONFIG_QCOM_PMIC_GLINK=m
+CONFIG_QCOM_QMI_HELPERS=m
+CONFIG_QCOM_QSEECOM_UEFISECAPP=y
+CONFIG_QCOM_QSEECOM=y
+CONFIG_QCOM_RAMP_CTRL=m
+CONFIG_QCOM_RPMH=y
+CONFIG_QCOM_RPM_MASTER_STATS=m
+CONFIG_QCOM_SCM=y
+CONFIG_QCOM_SPMI_ADC5=m
+CONFIG_QCOM_SPMI_ADC_TM5=m
+CONFIG_QCOM_SPMI_IADC=m
+CONFIG_QCOM_SPMI_VADC=m
+CONFIG_QCOM_SPM=m
+CONFIG_QCOM_SSC_BLOCK_BUS=y
+CONFIG_QCOMTEE=m
+CONFIG_QCOM_TSENS=m
+CONFIG_QCOM_TZMEM_MODE_GENERIC=y
+CONFIG_QCOM_VADC_COMMON=m
+CONFIG_QEDF=m
+CONFIG_QLGE=m
+CONFIG_QPIC_SNAND=m
+CONFIG_QSEMI_PHY=m
+CONFIG_QTNFMAC=m
+CONFIG_QTNFMAC_PCIE=m
+CONFIG_R8188EU=m
+CONFIG_R8712U=m
+CONFIG_RADIO_ADAPTERS=y
+CONFIG_RADIO_MAXIRADIO=m
+CONFIG_RADIO_SAA7706H=m
+CONFIG_RADIO_SHARK2=m
+CONFIG_RADIO_SHARK=m
+CONFIG_RADIO_SI470X=m
+CONFIG_RADIO_SI4713=m
+CONFIG_RADIO_SI476X=m
+CONFIG_RADIO_TEA575X=m
+CONFIG_RADIO_TEA5764=m
+CONFIG_RADIO_TEF6862=m
+CONFIG_RADIO_WL1273=m
+CONFIG_RADIO_WL128X=m
 CONFIG_RAID6_PQ=m
-# CONFIG_RAID6_PQ_BENCHMARK is not set
-CONFIG_LINEAR_RANGES=y
-CONFIG_PACKING=y
-CONFIG_BITREVERSE=y
-CONFIG_HAVE_ARCH_BITREVERSE=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_CORDIC=m
-CONFIG_PRIME_NUMBERS=m
+CONFIG_RAID_ATTRS=m
+CONFIG_RANDOM_TRUST_BOOTLOADER=y
+CONFIG_RANDOM_TRUST_CPU=y
+CONFIG_RAPIDIO_CHMAN=m
+CONFIG_RAPIDIO_CPS_GEN2=m
+CONFIG_RAPIDIO_CPS_XX=m
+CONFIG_RAPIDIO_DISC_TIMEOUT=30
+CONFIG_RAPIDIO_DMA_ENGINE=y
+CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y
+CONFIG_RAPIDIO_ENUM_BASIC=m
+CONFIG_RAPIDIO=m
+CONFIG_RAPIDIO_MPORT_CDEV=m
+CONFIG_RAPIDIO_RXS_GEN3=m
+CONFIG_RAPIDIO_TSI568=m
+CONFIG_RAPIDIO_TSI57X=m
+CONFIG_RAPIDIO_TSI721=m
+CONFIG_RAS=y
 CONFIG_RATIONAL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC64_ROCKSOFT=m
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC32_SELFTEST is not set
-CONFIG_CRC32_SLICEBY8=y
-# CONFIG_CRC32_SLICEBY4 is not set
-# CONFIG_CRC32_SARWATE is not set
-# CONFIG_CRC32_BIT is not set
-CONFIG_CRC64=m
-CONFIG_CRC4=m
-CONFIG_CRC7=m
-CONFIG_LIBCRC32C=m
-CONFIG_CRC8=m
-CONFIG_XXHASH=y
-# CONFIG_RANDOM32_SELFTEST is not set
-CONFIG_842_COMPRESS=y
-CONFIG_842_DECOMPRESS=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_LZ4_COMPRESS=y
-CONFIG_LZ4HC_COMPRESS=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
-CONFIG_XZ_DEC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_BCJ=y
-# CONFIG_XZ_DEC_TEST is not set
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DECOMPRESS_ZSTD=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_REED_SOLOMON=m
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_DEC16=y
-CONFIG_BCH=m
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_BTREE=y
-CONFIG_INTERVAL_TREE=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_DMA=y
-CONFIG_DMA_OPS=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_DMA_DECLARE_COHERENT=y
-CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
-CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
-CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
-CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
-CONFIG_DMA_VIRT_OPS=y
-CONFIG_SWIOTLB=y
-CONFIG_DMA_NONCOHERENT_MMAP=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_PERNUMA_CMA=y
-
-#
-# Default contiguous memory area size:
-#
-CONFIG_CMA_SIZE_MBYTES=0
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_ALIGNMENT=8
-# CONFIG_DMA_API_DEBUG is not set
-# CONFIG_DMA_MAP_BENCHMARK is not set
-CONFIG_SGL_ALLOC=y
-CONFIG_CHECK_SIGNATURE=y
-CONFIG_CPU_RMAP=y
-CONFIG_DQL=y
-CONFIG_GLOB=y
-# CONFIG_GLOB_SELFTEST is not set
-CONFIG_NLATTR=y
-CONFIG_LRU_CACHE=m
-CONFIG_CLZ_TAB=y
-CONFIG_IRQ_POLL=y
-CONFIG_MPILIB=y
-CONFIG_DIMLIB=y
-CONFIG_LIBFDT=y
-CONFIG_OID_REGISTRY=y
-CONFIG_HAVE_GENERIC_VDSO=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_6x10 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-CONFIG_FONT_TER16x32=y
-CONFIG_FONT_6x8=y
-CONFIG_STACK_HASH_ORDER=16
-CONFIG_SG_POOL=y
-CONFIG_SBITMAP=y
-CONFIG_PARMAN=m
-CONFIG_OBJAGG=m
-# CONFIG_STRING_SELFTEST is not set
-# end of Library routines
-
-CONFIG_PLDMFW=y
-
-#
-# Kernel hacking
-#
-
-#
-# printk and dmesg options
-#
-# CONFIG_PRINTK_TIME is not set
-# CONFIG_PRINTK_CALLER is not set
-CONFIG_STACKTRACE_BUILD_ID=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
-CONFIG_CONSOLE_LOGLEVEL_QUIET=4
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_DYNAMIC_DEBUG_CORE is not set
-CONFIG_SYMBOLIC_ERRNAME=y
-CONFIG_DEBUG_BUGVERBOSE=y
-# end of printk and dmesg options
-
-#
-# Compile-time checks and compiler options
-#
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_INFO_REDUCED is not set
-CONFIG_DEBUG_INFO_COMPRESSED=y
-# CONFIG_DEBUG_INFO_SPLIT is not set
-# CONFIG_DEBUG_INFO_NONE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-# CONFIG_DEBUG_INFO_DWARF4 is not set
-# CONFIG_DEBUG_INFO_DWARF5 is not set
-CONFIG_DEBUG_INFO_BTF=y
-CONFIG_MODULE_ALLOW_BTF_MISMATCH=y
-# CONFIG_GDB_SCRIPTS is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_FRAME_WARN=0
-CONFIG_STRIP_ASM_SYMS=y
-# CONFIG_READABLE_ASM is not set
-# CONFIG_HEADERS_INSTALL is not set
-# CONFIG_DEBUG_SECTION_MISMATCH is not set
-CONFIG_SECTION_MISMATCH_WARN_ONLY=y
-# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set
-# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
-CONFIG_VMLINUX_MAP=y
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# end of Compile-time checks and compiler options
-
-#
-# Generic Kernel Debugging Instruments
-#
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
-CONFIG_MAGIC_SYSRQ_SERIAL=y
-CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_FS_ALLOW_ALL is not set
-# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
-# CONFIG_DEBUG_FS_ALLOW_NONE is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_UBSAN is not set
-# end of Generic Kernel Debugging Instruments
-
-# CONFIG_DEBUG_KERNEL is not set
-# CONFIG_DEBUG_MISC is not set
-
-#
-# Memory Debugging
-#
-# CONFIG_PAGE_EXTENSION is not set
-# CONFIG_PAGE_OWNER is not set
-# CONFIG_PAGE_TABLE_CHECK is not set
-# CONFIG_PAGE_POISONING is not set
-# CONFIG_DEBUG_PAGE_REF is not set
-# CONFIG_DEBUG_RODATA_TEST is not set
-CONFIG_DEBUG_WX=y
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SHRINKER_DEBUG is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_HAVE_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_SCHED_STACK_END_CHECK is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_ARCH_HAS_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_PER_CPU_MAPS is not set
-# CONFIG_DEBUG_KMAP_LOCAL is not set
-# CONFIG_DEBUG_HIGHMEM is not set
-CONFIG_CC_HAS_KASAN_GENERIC=y
-CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
-# CONFIG_KASAN is not set
-# end of Memory Debugging
-
-# CONFIG_DEBUG_SHIRQ is not set
-
-#
-# Debug Oops, Lockups and Hangs
-#
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=60
-# CONFIG_SOFTLOCKUP_DETECTOR is not set
-# CONFIG_DETECT_HUNG_TASK is not set
-# CONFIG_WQ_WATCHDOG is not set
-CONFIG_TEST_LOCKUP=m
-# end of Debug Oops, Lockups and Hangs
-
-#
-# Scheduler Debugging
-#
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHED_INFO=y
-CONFIG_SCHEDSTATS=y
-# end of Scheduler Debugging
-
-# CONFIG_DEBUG_TIMEKEEPING is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_IRQFLAGS is not set
-
-#
-# Lock Debugging (spinlocks, mutexes, etc...)
-#
-# CONFIG_LOCK_DEBUGGING_SUPPORT is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
-# CONFIG_DEBUG_RWSEMS is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_DEBUG_ATOMIC_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_LOCK_TORTURE_TEST is not set
-# CONFIG_WW_MUTEX_SELFTEST is not set
-CONFIG_SCF_TORTURE_TEST=m
-# end of Lock Debugging (spinlocks, mutexes, etc...)
-
-CONFIG_STACKTRACE=y
-# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
-# CONFIG_DEBUG_KOBJECT is not set
-
-#
-# Debug kernel data structures
-#
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_PLIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BUG_ON_DATA_CORRUPTION is not set
-# end of Debug kernel data structures
-
-# CONFIG_DEBUG_CREDENTIALS is not set
-
-#
-# RCU Debugging
-#
-CONFIG_TORTURE_TEST=m
-CONFIG_RCU_SCALE_TEST=m
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_REF_SCALE_TEST=m
+CONFIG_RAVE_SP_CORE=m
+CONFIG_RAVE_SP_EEPROM=m
+CONFIG_RAVE_SP_WATCHDOG=m
+CONFIG_RAW_DRIVER=m
+CONFIG_RC_ATI_REMOTE=m
+CONFIG_RC_CORE=m
+CONFIG_RC_DECODERS=y
+CONFIG_RC_DEVICES=y
+CONFIG_RC_LOOPBACK=m
+CONFIG_RC_MAP=m
 CONFIG_RCU_CPU_STALL_TIMEOUT=60
-# CONFIG_RCU_TRACE is not set
-# CONFIG_RCU_EQS_DEBUG is not set
-# end of RCU Debugging
-
-# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-CONFIG_LATENCYTOP=y
-CONFIG_NOP_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_RING_BUFFER=y
-CONFIG_EVENT_TRACING=y
-CONFIG_CONTEXT_SWITCH_TRACER=y
-CONFIG_TRACING=y
-CONFIG_GENERIC_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-CONFIG_FTRACE=y
-CONFIG_BOOTTIME_TRACING=y
-CONFIG_FUNCTION_TRACER=y
-# CONFIG_FUNCTION_GRAPH_TRACER is not set
-CONFIG_DYNAMIC_FTRACE=y
-CONFIG_DYNAMIC_FTRACE_WITH_REGS=y
-# CONFIG_FPROBE is not set
-CONFIG_FTRACE_RECORD_RECURSION=y
-CONFIG_FTRACE_RECORD_RECURSION_SIZE=128
+CONFIG_RCU_LAZY=y
+CONFIG_RC_XBOX_DVD=m
+CONFIG_RDA_INTC=y
+CONFIG_RDA_TIMER=y
+CONFIG_RDMA_RXE=m
+CONFIG_RDMA_SIW=m
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_REALTEK_PHY=m
+CONFIG_REALVIEW_EB_A9MP=y
+CONFIG_REBOOT_MODE=m
+CONFIG_REED_SOLOMON_DEC16=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REED_SOLOMON=m
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_I3C=m
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SCCB=m
+CONFIG_REGMAP_SLIMBUS=m
+CONFIG_REGMAP_SOUNDWIRE=m
+CONFIG_REGMAP_SPI_AVMM=m
+CONFIG_REGMAP_SPI=y
+CONFIG_REGMAP_SPMI=m
+CONFIG_REGMAP_W1=m
+CONFIG_REGULATOR_88PG86X=m
+CONFIG_REGULATOR_88PM800=m
+CONFIG_REGULATOR_88PM886=m
+CONFIG_REGULATOR_ACT8865=m
+CONFIG_REGULATOR_ACT8945A=m
+CONFIG_REGULATOR_AD5398=m
+CONFIG_REGULATOR_ADP5055=m
+CONFIG_REGULATOR_ARIZONA_LDO1=m
+CONFIG_REGULATOR_ARIZONA_MICSUPP=m
+CONFIG_REGULATOR_ARM_SCMI=m
+CONFIG_REGULATOR_ATC260X=m
+CONFIG_REGULATOR_AW37503=m
+CONFIG_REGULATOR_AXP20X=m
+CONFIG_REGULATOR_BCM590XX=m
+CONFIG_REGULATOR_BD9571MWV=m
+CONFIG_REGULATOR_BD957XMUF=m
+CONFIG_REGULATOR_BD96801=m
+CONFIG_REGULATOR_BQ257XX=m
+CONFIG_REGULATOR_CPCAP=m
+CONFIG_REGULATOR_CROS_EC=m
+CONFIG_REGULATOR_DA9052=m
+CONFIG_REGULATOR_DA9062=m
+CONFIG_REGULATOR_DA9063=m
+CONFIG_REGULATOR_DA9121=m
+CONFIG_REGULATOR_DA9210=m
+CONFIG_REGULATOR_DA9211=m
+CONFIG_REGULATOR_DB8500_PRCMU=y
+CONFIG_REGULATOR_DBX500_PRCMU=y
+CONFIG_REGULATOR_FAN53555=m
+CONFIG_REGULATOR_FAN53880=m
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=m
+CONFIG_REGULATOR_HI6421=m
+CONFIG_REGULATOR_HI6421V530=m
+CONFIG_REGULATOR_HI6421V600=m
+CONFIG_REGULATOR_ISL6271A=m
+CONFIG_REGULATOR_ISL9305=m
+CONFIG_REGULATOR_LM363X=m
+CONFIG_REGULATOR_LP3971=m
+CONFIG_REGULATOR_LP3972=m
+CONFIG_REGULATOR_LP872X=m
+CONFIG_REGULATOR_LP873X=m
+CONFIG_REGULATOR_LP8755=m
+CONFIG_REGULATOR_LP87565=m
+CONFIG_REGULATOR_LTC3589=m
+CONFIG_REGULATOR_LTC3676=m
+CONFIG_REGULATOR_MAX14577=m
+CONFIG_REGULATOR_MAX1586=m
+CONFIG_REGULATOR_MAX20086=m
+CONFIG_REGULATOR_MAX20411=m
+CONFIG_REGULATOR_MAX5970=m
+CONFIG_REGULATOR_MAX597X=m
+CONFIG_REGULATOR_MAX77503=m
+CONFIG_REGULATOR_MAX77541=m
+CONFIG_REGULATOR_MAX77650=m
+CONFIG_REGULATOR_MAX77686=m
+CONFIG_REGULATOR_MAX77693=m
+CONFIG_REGULATOR_MAX77802=m
+CONFIG_REGULATOR_MAX77826=m
+CONFIG_REGULATOR_MAX77838=m
+CONFIG_REGULATOR_MAX77857=m
+CONFIG_REGULATOR_MAX8649=m
+CONFIG_REGULATOR_MAX8660=m
+CONFIG_REGULATOR_MAX8893=m
+CONFIG_REGULATOR_MAX8907=m
+CONFIG_REGULATOR_MAX8952=m
+CONFIG_REGULATOR_MAX8973=m
+CONFIG_REGULATOR_MC13783=m
+CONFIG_REGULATOR_MC13892=m
+CONFIG_REGULATOR_MC13XXX_CORE=m
+CONFIG_REGULATOR_MCP16502=m
+CONFIG_REGULATOR_MP5416=m
+CONFIG_REGULATOR_MP8859=m
+CONFIG_REGULATOR_MP886X=m
+CONFIG_REGULATOR_MPQ7920=m
+CONFIG_REGULATOR_MT6311=m
+CONFIG_REGULATOR_MT6315=m
+CONFIG_REGULATOR_MT6323=m
+CONFIG_REGULATOR_MT6331=m
+CONFIG_REGULATOR_MT6332=m
+CONFIG_REGULATOR_MT6357=m
+CONFIG_REGULATOR_MT6358=m
+CONFIG_REGULATOR_MT6359=m
+CONFIG_REGULATOR_MT6360=m
+CONFIG_REGULATOR_MT6370=m
+CONFIG_REGULATOR_MT6397=m
+CONFIG_REGULATOR_NETLINK_EVENTS=y
+CONFIG_REGULATOR_PCA9450=m
+CONFIG_REGULATOR_PCAP=m
+CONFIG_REGULATOR_PCF50633=m
+CONFIG_REGULATOR_PF0900=m
+CONFIG_REGULATOR_PF530X=m
+CONFIG_REGULATOR_PF8X00=m
+CONFIG_REGULATOR_PF9453=m
+CONFIG_REGULATOR_PFUZE100=m
+CONFIG_REGULATOR_PV88060=m
+CONFIG_REGULATOR_PV88080=m
+CONFIG_REGULATOR_PV88090=m
+CONFIG_REGULATOR_PWM=m
+CONFIG_REGULATOR_QCOM_LABIBB=m
+CONFIG_REGULATOR_QCOM_PM8008=m
+CONFIG_REGULATOR_QCOM_REFGEN=m
+CONFIG_REGULATOR_QCOM_RPMH=m
+CONFIG_REGULATOR_QCOM_SPMI=m
+CONFIG_REGULATOR_QCOM_USB_VBUS=m
+CONFIG_REGULATOR_RAA215300=m
+CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
+CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2=m
+CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR_RN5T618=m
+CONFIG_REGULATOR_RT4801=m
+CONFIG_REGULATOR_RT4803=m
+CONFIG_REGULATOR_RT4831=m
+CONFIG_REGULATOR_RT5033=m
+CONFIG_REGULATOR_RT5120=m
+CONFIG_REGULATOR_RT5133=m
+CONFIG_REGULATOR_RT5190A=m
+CONFIG_REGULATOR_RT5739=m
+CONFIG_REGULATOR_RT5759=m
+CONFIG_REGULATOR_RT6160=m
+CONFIG_REGULATOR_RT6190=m
+CONFIG_REGULATOR_RT6245=m
+CONFIG_REGULATOR_RTMV20=m
+CONFIG_REGULATOR_RTQ2134=m
+CONFIG_REGULATOR_RTQ2208=m
+CONFIG_REGULATOR_RTQ6752=m
+CONFIG_REGULATOR_S2DOS05=m
+CONFIG_REGULATOR_SKY81452=m
+CONFIG_REGULATOR_SLG51000=m
+CONFIG_REGULATOR_SUN20I=m
+CONFIG_REGULATOR_SY7636A=m
+CONFIG_REGULATOR_SY8106A=m
+CONFIG_REGULATOR_SY8824X=m
+CONFIG_REGULATOR_SY8827N=m
+CONFIG_REGULATOR_TPS51632=m
+CONFIG_REGULATOR_TPS6105X=m
+CONFIG_REGULATOR_TPS62360=m
+CONFIG_REGULATOR_TPS6286X=m
+CONFIG_REGULATOR_TPS6287X=m
+CONFIG_REGULATOR_TPS65023=m
+CONFIG_REGULATOR_TPS6507X=m
+CONFIG_REGULATOR_TPS65086=m
+CONFIG_REGULATOR_TPS65132=m
+CONFIG_REGULATOR_TPS65217=m
+CONFIG_REGULATOR_TPS65218=m
+CONFIG_REGULATOR_TPS65219=m
+CONFIG_REGULATOR_TPS6524X=m
+CONFIG_REGULATOR_TPS65912=m
+CONFIG_REGULATOR_TPS6594=m
+CONFIG_REGULATOR_TPS68470=m
+CONFIG_REGULATOR_UNIPHIER=y
+CONFIG_REGULATOR_USERSPACE_CONSUMER=m
+CONFIG_REGULATOR_VCTRL=m
+CONFIG_REGULATOR_VEXPRESS=m
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
+CONFIG_REGULATOR_WM831X=m
+CONFIG_REGULATOR_WM8994=m
+CONFIG_REGULATOR=y
+CONFIG_RELAY=y
+CONFIG_REMOTE_TARGET=m
+CONFIG_RENESAS_I3C=m
+CONFIG_RENESAS_OSTM=y
+CONFIG_RENESAS_PHY=m
+CONFIG_RENESAS_RPCIF=m
+CONFIG_RENESAS_RZG2LWDT=m
+CONFIG_RENESAS_RZN1WDT=m
+CONFIG_RENESAS_RZV2HWDT=m
+CONFIG_RESET_A10SR=m
+CONFIG_RESET_ASPEED=m
+CONFIG_RESET_ATTACK_MITIGATION=y
+CONFIG_RESET_BERLIN=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_HISI=y
+CONFIG_RESET_IMX8MP_AUDIOMIX=m
+CONFIG_RESET_MCHP_SPARX5=y
+CONFIG_RESET_MESON=y
+CONFIG_RESET_NPCM=y
+CONFIG_RESET_SCMI=m
+CONFIG_RESET_SCMI=y
+CONFIG_RESET_SIMPLE=y
+CONFIG_RESET_SOCFPGA=y
+CONFIG_RESET_STM32MP157=y
+CONFIG_RESET_SUNXI=y
+CONFIG_RESET_TI_SYSCON=m
+CONFIG_RESET_TI_TPS380X=m
+CONFIG_RESET_UNIPHIER_GLUE=y
+CONFIG_RESET_UNIPHIER=y
+CONFIG_RESET_ZYNQ=y
+CONFIG_RETU_WATCHDOG=m
+CONFIG_RFD77402=m
+CONFIG_RFD_FTL=m
+CONFIG_RFKILL_GPIO=m
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL=m
+CONFIG_RICHTEK_RTQ6056=m
 CONFIG_RING_BUFFER_RECORD_RECURSION=y
-# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
-CONFIG_FUNCTION_PROFILER=y
-CONFIG_STACK_TRACER=y
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_HWLAT_TRACER is not set
-# CONFIG_OSNOISE_TRACER is not set
-# CONFIG_TIMERLAT_TRACER is not set
-CONFIG_FTRACE_SYSCALLS=y
-# CONFIG_TRACER_SNAPSHOT is not set
-CONFIG_BRANCH_PROFILE_NONE=y
-# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
-# CONFIG_PROFILE_ALL_BRANCHES is not set
-CONFIG_BLK_DEV_IO_TRACE=y
-CONFIG_KPROBE_EVENTS=y
-# CONFIG_UPROBE_EVENTS is not set
-CONFIG_BPF_EVENTS=y
-CONFIG_DYNAMIC_EVENTS=y
-CONFIG_PROBE_EVENTS=y
-CONFIG_FTRACE_MCOUNT_RECORD=y
-# CONFIG_SYNTH_EVENTS is not set
-# CONFIG_HIST_TRIGGERS is not set
-# CONFIG_TRACE_EVENT_INJECT is not set
-# CONFIG_TRACEPOINT_BENCHMARK is not set
-# CONFIG_RING_BUFFER_BENCHMARK is not set
-# CONFIG_TRACE_EVAL_MAP_FILE is not set
-# CONFIG_FTRACE_STARTUP_TEST is not set
-# CONFIG_RING_BUFFER_STARTUP_TEST is not set
-CONFIG_PREEMPTIRQ_DELAY_TEST=m
-CONFIG_KPROBE_EVENT_GEN_TEST=m
-# CONFIG_SAMPLES is not set
-CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
-CONFIG_STRICT_DEVMEM=y
-# CONFIG_IO_STRICT_DEVMEM is not set
-
-#
-# arm Debugging
-#
-CONFIG_ARM_PTDUMP_CORE=y
-# CONFIG_ARM_PTDUMP_DEBUGFS is not set
-# CONFIG_UNWINDER_FRAME_POINTER is not set
-CONFIG_UNWINDER_ARM=y
-CONFIG_ARM_UNWIND=y
-# CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_LL is not set
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_ARM_KPROBES_TEST=m
-# CONFIG_PID_IN_CONTEXTIDR is not set
-# CONFIG_CORESIGHT is not set
-# end of arm Debugging
-
-#
-# Kernel Testing and Coverage
-#
-# CONFIG_KUNIT is not set
-# CONFIG_NOTIFIER_ERROR_INJECTION is not set
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_ARCH_HAS_KCOV=y
-CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-# CONFIG_KCOV is not set
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_MEMTEST=y
-# end of Kernel Testing and Coverage
-# end of Kernel hacking
-CONFIG_SURFACE_PLATFORMS=y
-CONFIG_SURFACE_DTX=m
-CONFIG_SURFACE_PLATFORM_PROFILE=m
-CONFIG_SURFACE_KBD=m
-CONFIG_LITEX_SOC_CONTROLLER=m
-CONFIG_LITEX_SUBREG_SIZE=4
-
-# CONFIG_WERROR is not set
-CONFIG_PRINTK_INDEX=y
-CONFIG_SOC_SAMA7G5=y
-CONFIG_SOC_LAN966=y
-CONFIG_ARCH_MSM8916=y
-CONFIG_MACH_STM32MP13=y
-CONFIG_ARM_MEDIATEK_CPUFREQ_HW=m
-CONFIG_DAMON=y
-CONFIG_DAMON_SYSFS=y
-CONFIG_DAMON_VADDR=y
-CONFIG_DAMON_PADDR=y
-CONFIG_DAMON_DBGFS=y
-CONFIG_DAMON_RECLAIM=y
-CONFIG_IPV6_IOAM6_LWTUNNEL=y
-CONFIG_NETFILTER_EGRESS=y
-CONFIG_MCTP=y
-CONFIG_PCIE_QCOM_EP=m
-CONFIG_PCIE_ROCKCHIP_DW_HOST=y
-CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
-CONFIG_ARM_SCMI_TRANSPORT_SMC=y
-# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
-CONFIG_HI6421V600_IRQ=m
-CONFIG_SCSI_UFS_HPB=y
-CONFIG_SCSI_UFS_HWMON=y
-CONFIG_AMT=m
-CONFIG_NET_VENDOR_ASIX=y
-CONFIG_SPI_AX88796C=m
-CONFIG_SPI_AX88796C_COMPRESSION=y
-CONFIG_CS89x0_PLATFORM=m
-CONFIG_ICE_SWITCHDEV=y
-CONFIG_ICE_HWTS=y
-CONFIG_NET_VENDOR_LITEX=y
-CONFIG_LITEX_LITEETH=m
-CONFIG_MAXLINEAR_GPHY=m
-CONFIG_MT7921S=m
-CONFIG_MT7921U=m
-CONFIG_RTW89=m
+CONFIG_RING_BUFFER=y
+CONFIG_RIONET=m
+CONFIG_RIONET_RX_SIZE=128
+CONFIG_RIONET_TX_SIZE=128
+CONFIG_RN5T618_POWER=m
+CONFIG_ROCKCHIP_DTPM=m
+CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_PHY=m
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_ROCKETPORT=m
+CONFIG_ROHM_BD79112=m
+CONFIG_ROHM_BM1390=m
+CONFIG_ROHM_BU27008=m
+CONFIG_ROHM_BU27034=m
+CONFIG_ROSE=m
+CONFIG_RPMSG_CHAR=m
+CONFIG_RPMSG_CTRL=m
+CONFIG_RPMSG=m
+CONFIG_RPMSG_QCOM_GLINK=m
+CONFIG_RPMSG_QCOM_GLINK_RPM=m
+CONFIG_RPMSG_TTY=m
+CONFIG_RPMSG_VIRTIO=m
+CONFIG_RPMSG_WWAN_CTRL=m
+CONFIG_RPR0521=m
+CONFIG_RSI_91X=m
+CONFIG_RSI_COEX=y
+CONFIG_RSI_SDIO=m
+CONFIG_RSI_USB=m
+CONFIG_RT2400PCI=m
+CONFIG_RT2500PCI=m
+CONFIG_RT2500USB=m
+CONFIG_RT2800_LIB=m
+CONFIG_RT2800_LIB_MMIO=m
+CONFIG_RT2800PCI=m
+CONFIG_RT2800PCI_RT3290=y
+CONFIG_RT2800PCI_RT33XX=y
+CONFIG_RT2800PCI_RT35XX=y
+CONFIG_RT2800PCI_RT53XX=y
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT3573=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_LEDS=y
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_MMIO=m
+CONFIG_RT2X00_LIB_PCI=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00=m
+CONFIG_RT61PCI=m
+CONFIG_RT73USB=m
+CONFIG_RTC_DRV_88PM80X=m
+CONFIG_RTC_DRV_ABB5ZES3=m
+CONFIG_RTC_DRV_ABEOZ9=m
+CONFIG_RTC_DRV_ABX80X=m
+CONFIG_RTC_DRV_BBNSM=m
+CONFIG_RTC_DRV_BQ32K=m
+CONFIG_RTC_DRV_BQ4802=m
+CONFIG_RTC_DRV_CMOS=y
+CONFIG_RTC_DRV_CV1800=m
+CONFIG_RTC_DRV_DA9052=m
+CONFIG_RTC_DRV_DA9063=m
+CONFIG_RTC_DRV_DS1286=m
+CONFIG_RTC_DRV_DS1302=m
+CONFIG_RTC_DRV_DS1305=m
+CONFIG_RTC_DRV_DS1307=m
+CONFIG_RTC_DRV_DS1343=m
+CONFIG_RTC_DRV_DS1347=m
+CONFIG_RTC_DRV_DS1374=m
+CONFIG_RTC_DRV_DS1374_WDT=y
+CONFIG_RTC_DRV_DS1390=m
+CONFIG_RTC_DRV_DS1511=m
+CONFIG_RTC_DRV_DS1553=m
+CONFIG_RTC_DRV_DS1672=m
+CONFIG_RTC_DRV_DS1685_FAMILY=m
+CONFIG_RTC_DRV_DS1685=y
+CONFIG_RTC_DRV_DS1742=m
+CONFIG_RTC_DRV_DS2404=m
+CONFIG_RTC_DRV_DS3232_HWMON=y
+CONFIG_RTC_DRV_DS3232=m
+CONFIG_RTC_DRV_EFI=m
+CONFIG_RTC_DRV_EM3027=m
+CONFIG_RTC_DRV_FM3130=m
+CONFIG_RTC_DRV_FTRTC010=m
+CONFIG_RTC_DRV_GOLDFISH=m
+CONFIG_RTC_DRV_HID_SENSOR_TIME=m
+CONFIG_RTC_DRV_IMX_BBM_SCMI=m
+CONFIG_RTC_DRV_ISL12022=m
+CONFIG_RTC_DRV_ISL1208=m
+CONFIG_RTC_DRV_M41T80=m
+CONFIG_RTC_DRV_M41T80_WDT=y
+CONFIG_RTC_DRV_M41T93=m
+CONFIG_RTC_DRV_M41T94=m
+CONFIG_RTC_DRV_M48T35=m
+CONFIG_RTC_DRV_M48T59=m
+CONFIG_RTC_DRV_M48T86=m
+CONFIG_RTC_DRV_MAX31335=m
+CONFIG_RTC_DRV_MAX6900=m
+CONFIG_RTC_DRV_MAX6902=m
+CONFIG_RTC_DRV_MAX6916=m
+CONFIG_RTC_DRV_MAX8907=m
+CONFIG_RTC_DRV_MC13XXX=m
+CONFIG_RTC_DRV_MCP795=m
+CONFIG_RTC_DRV_MESON_VRTC=m
+CONFIG_RTC_DRV_MSC313=m
+CONFIG_RTC_DRV_MSM6242=m
+CONFIG_RTC_DRV_MT6397=m
+CONFIG_RTC_DRV_NCT3018Y=m
+CONFIG_RTC_DRV_NCT6694=m
+CONFIG_RTC_DRV_NTXEC=m
+CONFIG_RTC_DRV_OPTEE=m
+CONFIG_RTC_DRV_PCAP=m
+CONFIG_RTC_DRV_PCF2123=m
+CONFIG_RTC_DRV_PCF2127=m
+CONFIG_RTC_DRV_PCF50633=m
+CONFIG_RTC_DRV_PCF85063=m
+CONFIG_RTC_DRV_PCF8523=m
+CONFIG_RTC_DRV_PCF85363=m
+CONFIG_RTC_DRV_PCF8563=m
+CONFIG_RTC_DRV_PCF8583=m
+CONFIG_RTC_DRV_R9701=m
+CONFIG_RTC_DRV_RP5C01=m
+CONFIG_RTC_DRV_RS5C348=m
+CONFIG_RTC_DRV_RS5C372=m
+CONFIG_RTC_DRV_RTD119X=y
+CONFIG_RTC_DRV_RV3028=m
+CONFIG_RTC_DRV_RV3029C2=m
+CONFIG_RTC_DRV_RV3029_HWMON=y
+CONFIG_RTC_DRV_RV3032=m
+CONFIG_RTC_DRV_RV8803=m
+CONFIG_RTC_DRV_RX4581=m
+CONFIG_RTC_DRV_RX6110=m
+CONFIG_RTC_DRV_RX8010=m
+CONFIG_RTC_DRV_RX8025=m
+CONFIG_RTC_DRV_RX8581=m
+CONFIG_RTC_DRV_S35390A=m
+CONFIG_RTC_DRV_SD3078=m
+CONFIG_RTC_DRV_SPEAR=y
+CONFIG_RTC_DRV_SSD202D=m
+CONFIG_RTC_DRV_STK17TA8=m
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_RTC_DRV_SUNPLUS=m
+CONFIG_RTC_DRV_TI_K3=m
+CONFIG_RTC_DRV_TPS6594=m
+CONFIG_RTC_DRV_V3020=m
+CONFIG_RTC_DRV_WM831X=m
+CONFIG_RTC_DRV_X1205=m
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RTD119X_WATCHDOG=y
+CONFIG_RTL8180=m
+CONFIG_RTL8187_LEDS=y
+CONFIG_RTL8187=m
+CONFIG_RTL8188EE=m
+CONFIG_RTL8192C_COMMON=m
+CONFIG_RTL8192CE=m
+CONFIG_RTL8192CU=m
+CONFIG_RTL8192DE=m
+CONFIG_RTL8192DU=m
+CONFIG_RTL8192EE=m
+CONFIG_RTL8192E=m
+CONFIG_RTL8192SE=m
+CONFIG_RTL8192U=m
+CONFIG_RTL8723AE=m
+CONFIG_RTL8723BE=m
+CONFIG_RTL8723BS=m
+CONFIG_RTL8723_COMMON=m
+CONFIG_RTL8723CS=m
+CONFIG_RTL8821AE=m
+CONFIG_RTL8XXXU=m
+CONFIG_RTL8XXXU_UNTESTED=y
+CONFIG_RTLBTCOEXIST=m
+CONFIG_RTL_CARDS=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+CONFIG_RTLLIB=m
+CONFIG_RTLWIFI=m
+CONFIG_RTLWIFI_PCI=m
+CONFIG_RTLWIFI_USB=m
+CONFIG_RTS5208=m
+CONFIG_RTW88_8723CS=m
+CONFIG_RTW88_8723DE=m
+CONFIG_RTW88_8723D=m
+CONFIG_RTW88_8723DS=m
+CONFIG_RTW88_8723DU=m
+CONFIG_RTW88_8821CE=m
+CONFIG_RTW88_8821C=m
+CONFIG_RTW88_8821CS=m
+CONFIG_RTW88_8821CU=m
+CONFIG_RTW88_8822BE=m
+CONFIG_RTW88_8822B=m
+CONFIG_RTW88_8822BS=m
+CONFIG_RTW88_8822BU=m
+CONFIG_RTW88_8822CE=m
+CONFIG_RTW88_8822C=m
+CONFIG_RTW88_8822CS=m
+CONFIG_RTW88_8822CU=m
+CONFIG_RTW88_CORE=m
+CONFIG_RTW88=m
+CONFIG_RTW88_PCI=m
+CONFIG_RTW89_8851BE=m
 CONFIG_RTW89_8852AE=m
-# CONFIG_RTW89_DEBUGMSG is not set
+CONFIG_RTW89_8852BE=m
+CONFIG_RTW89_8852BTE=m
+CONFIG_RTW89_8852CE=m
+CONFIG_RTW89_8922AE=m
 CONFIG_RTW89_DEBUGFS=y
-CONFIG_MHI_WWAN_MBIM=m
-CONFIG_QCOM_BAM_DMUX=m
-CONFIG_KEYBOARD_CYPRESS_SF=m
-CONFIG_RPMSG_TTY=m
-CONFIG_IPMI_IPMB=m
-CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
-CONFIG_HW_RANDOM_CN10K=m
-CONFIG_I2C_VIRTIO=m
-CONFIG_SPI_CADENCE_XSPI=m
-CONFIG_SPI_ROCKCHIP_SFC=m
-CONFIG_PINCTRL_IMX8ULP=m
-CONFIG_PINCTRL_MDM9607=m
-CONFIG_PINCTRL_QCM2290=m
-CONFIG_PINCTRL_SM6115=m
-CONFIG_PINCTRL_SM6350=m
-CONFIG_PINCTRL_UNIPHIER_NX1=y
-CONFIG_GPIO_ROCKCHIP=m
-CONFIG_GPIO_VIRTIO=m
-CONFIG_POWER_RESET_TPS65086=y
-CONFIG_CHARGER_MT6360=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_CHARGER_CROS_PCHG=m
-CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m
-CONFIG_SENSORS_MAX6620=m
-CONFIG_SENSORS_SBRMI=m
-CONFIG_QCOM_LMH=m
-CONFIG_DB500_WATCHDOG=m
-CONFIG_MFD_RSMU_I2C=m
-CONFIG_MFD_RSMU_SPI=m
-CONFIG_REGULATOR_RTQ2134=m
-CONFIG_REGULATOR_RTQ6752=m
-CONFIG_IR_MESON_TX=m
-CONFIG_VIDEO_RCAR_ISP=m
-# CONFIG_VIDEO_ROCKCHIP_IEP is not set
-CONFIG_VIDEO_HI846=m
-CONFIG_VIDEO_HI847=m
-CONFIG_VIDEO_IMX335=m
-CONFIG_VIDEO_IMX412=m
-CONFIG_VIDEO_OV9282=m
-CONFIG_VIDEO_OV13B10=m
-# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
-CONFIG_DRM_PANEL_EDP=m
-CONFIG_DRM_PANEL_ILITEK_ILI9341=m
-CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
-CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
-CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
-CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
-CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
-CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
-CONFIG_SND_HDA_CODEC_CS8409=m
-CONFIG_SND_SOC_MT8195=m
-CONFIG_SND_SOC_CS35L41_SPI=m
-CONFIG_SND_SOC_CS35L41_I2C=m
-CONFIG_SND_SOC_ICS43432=m
-CONFIG_SND_SOC_MAX98520=m
-CONFIG_SND_SOC_RT9120=m
-CONFIG_SND_SOC_SDW_MOCKUP=m
-CONFIG_SND_SOC_NAU8821=m
-CONFIG_SND_AUDIO_GRAPH_CARD2=m
-CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
-CONFIG_SND_TEST_COMPONENT=m
-CONFIG_HID_XIAOMI=m
-CONFIG_HID_NINTENDO=m
-CONFIG_NINTENDO_FF=y
-CONFIG_RTC_DRV_MSC313=m
-# CONFIG_DMABUF_SYSFS_STATS is not set
-CONFIG_VDPA_USER=m
-CONFIG_COMMON_CLK_XLNX_CLKWZRD=m
-CONFIG_CLK_IMX8ULP=m
-CONFIG_CLK_IMX93=m
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_ASPEED_UART_ROUTING=m
-CONFIG_QCOM_SPM=m
-CONFIG_ADXL313_I2C=m
-CONFIG_ADXL313_SPI=m
-CONFIG_ADXL355_I2C=m
-CONFIG_ADXL355_SPI=m
-CONFIG_ADXL367_SPI=m
-CONFIG_ADXL367_I2C=m
+CONFIG_RTW89=m
+CONFIG_RZG2L_THERMAL=m
+CONFIG_RZG3E_THERMAL=m
+CONFIG_S5P_DEV_MFC=y
+CONFIG_SAMSUNG_MC=y
+CONFIG_SATA_ACARD_AHCI=m
+CONFIG_SATA_AHCI=m
+CONFIG_SATA_AHCI_PLATFORM=m
+CONFIG_SATA_DWC=m
+CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MV=m
+CONFIG_SATA_NV=m
+CONFIG_SATA_PROMISE=m
+CONFIG_SATA_QSTOR=m
+CONFIG_SATA_SIL24=m
+CONFIG_SATA_SIL=m
+CONFIG_SATA_SIS=m
+CONFIG_SATA_SVW=m
+CONFIG_SATA_SX4=m
+CONFIG_SATA_ULI=m
+CONFIG_SATA_VIA=m
+CONFIG_SATA_VITESSE=m
+CONFIG_SBP_TARGET=m
+CONFIG_SCA3000=m
+CONFIG_SCA3300=m
+CONFIG_SCD30_CORE=m
+CONFIG_SCD30_I2C=m
+CONFIG_SCD30_SERIAL=m
 CONFIG_SCD4X=m
-CONFIG_SENSIRION_SGP40=m
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SCHED_CORE=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_SMT=y
+CONFIG_SCHEDSTATS=y
+CONFIG_SCR24X=m
+CONFIG_SCSI_3W_9XXX=m
+CONFIG_SCSI_3W_SAS=m
+CONFIG_SCSI_AACRAID=m
+CONFIG_SCSI_ACARD=m
+CONFIG_SCSI_ADVANSYS=m
+CONFIG_SCSI_AIC79XX=m
+CONFIG_SCSI_AIC7XXX=m
+CONFIG_SCSI_AIC94XX=m
+CONFIG_SCSI_AM53C974=m
+CONFIG_SCSI_ARCMSR=m
+CONFIG_SCSI_BFA_FC=m
+CONFIG_SCSI_BNX2_ISCSI=m
+CONFIG_SCSI_BNX2X_FCOE=m
+CONFIG_SCSI_BUSLOGIC=m
+CONFIG_SCSI_CHELSIO_FCOE=m
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_CXGB3_ISCSI=m
+CONFIG_SCSI_CXGB4_ISCSI=m
+CONFIG_SCSI_DC395x=m
+CONFIG_SCSI_DH_ALUA=m
+CONFIG_SCSI_DH_EMC=m
+CONFIG_SCSI_DH_HP_SW=m
+CONFIG_SCSI_DH_RDAC=m
+CONFIG_SCSI_DH=y
+CONFIG_SCSI_DMX3191D=m
+CONFIG_SCSI_EFCT=m
+CONFIG_SCSI_ENCLOSURE=m
+CONFIG_SCSI_ESAS2R=m
+CONFIG_SCSI_FC_ATTRS=m
+CONFIG_SCSI_FDOMAIN=m
+CONFIG_SCSI_FDOMAIN_PCI=m
+CONFIG_SCSI_FLASHPOINT=y
+CONFIG_SCSI_GDTH=m
+CONFIG_SCSI_HPSA=m
+CONFIG_SCSI_HPTIOP=m
+CONFIG_SCSI_IMM=m
+CONFIG_SCSI_INIA100=m
+CONFIG_SCSI_INITIO=m
+CONFIG_SCSI_IPR=m
+CONFIG_SCSI_IPS=m
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_LOWLEVEL_PCMCIA=y
+CONFIG_SCSI_LPFC=m
+CONFIG_SCSI=m
+CONFIG_SCSI_MOD=m
+CONFIG_SCSI_MPI3MR=m
+CONFIG_SCSI_MPT2SAS=m
+CONFIG_SCSI_MPT2SAS_MAX_SGE=128
+CONFIG_SCSI_MPT3SAS=m
+CONFIG_SCSI_MPT3SAS_MAX_SGE=128
+CONFIG_SCSI_MVSAS=m
+CONFIG_SCSI_MVSAS_TASKLET=y
+CONFIG_SCSI_MVUMI=m
+CONFIG_SCSI_MYRB=m
+CONFIG_SCSI_MYRS=m
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PM8001=m
+CONFIG_SCSI_PMCRAID=m
+CONFIG_SCSI_PPA=m
+CONFIG_SCSI_PROC_FS=y
+CONFIG_SCSI_QLA_FC=m
+CONFIG_SCSI_QLA_ISCSI=m
+CONFIG_SCSI_QLOGIC_1280=m
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_SMARTPQI=m
+CONFIG_SCSI_SNIC=m
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_STEX=m
+CONFIG_SCSI_SYM53C8XX_2=m
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+CONFIG_SCSI_SYM53C8XX_MMIO=y
+CONFIG_SCSI_UFS_CDNS_PLATFORM=m
+CONFIG_SCSI_UFS_DWC_TC_PCI=m
+CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m
+CONFIG_SCSI_UFS_EXYNOS=m
+CONFIG_SCSI_UFSHCD=m
+CONFIG_SCSI_UFSHCD_PCI=m
+CONFIG_SCSI_UFSHCD_PLATFORM=m
+CONFIG_SCSI_UFS_HPB=y
+CONFIG_SCSI_UFS_HWMON=y
+CONFIG_SCSI_UFS_RENESAS=m
+CONFIG_SCSI_UFS_ROCKCHIP=m
+CONFIG_SCSI_UFS_SPRD=m
+CONFIG_SCSI_VIRTIO=m
+CONFIG_SCSI_WD719X=m
+CONFIG_SDIO_UART=m
+CONFIG_SDP500=m
+CONFIG_SDR_MAX2175=m
+CONFIG_SDR_PLATFORM_DRIVERS=y
+CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN=y
+CONFIG_SECONDARY_TRUSTED_KEYRING=y
+CONFIG_SECRETMEM=y
+CONFIG_SEG_LED_GPIO=m
+CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_SENSEAIR_SUNRISE_CO2=m
-CONFIG_ADRF6780=m
-CONFIG_AD5110=m
-CONFIG_MAX31865=m
-CONFIG_MCHP_EIC=y
-# CONFIG_F2FS_IOSTAT is not set
-# CONFIG_F2FS_UNFAIR_RWSEM is not set
-CONFIG_SMB_SERVER=m
-CONFIG_SMB_SERVER_SMBDIRECT=y
-CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
-CONFIG_SMB_SERVER_KERBEROS5=y
-# CONFIG_ZERO_CALL_USED_REGS is not set
-CONFIG_XZ_DEC_MICROLZMA=y
-CONFIG_DMA_RESTRICTED_POOL=y
-# CONFIG_ANON_VMA_NAME is not set
-CONFIG_NET_9P_FD=m
-CONFIG_DEVTMPFS_SAFE=y
-CONFIG_GNSS_USB=m
-CONFIG_MTD_NAND_RENESAS=m
-CONFIG_NET_VENDOR_ENGLEDER=y
-CONFIG_TSNEP=m
-# CONFIG_TSNEP_SELFTESTS is not set
-CONFIG_LAN966X_SWITCH=m
-CONFIG_NET_VENDOR_VERTEXCOM=y
-CONFIG_MSE102X=m
-CONFIG_MCTP_SERIAL=m
-CONFIG_MCTP_TRANSPORT_I2C=m
-# CONFIG_WWAN_DEBUGFS is not set
+CONFIG_SENSIRION_SGP30=m
+CONFIG_SENSIRION_SGP40=m
+CONFIG_SERIAL_8250_BCM7271=m
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_CS=m
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_DFL=m
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_DW=m
+CONFIG_SERIAL_8250_EXAR=m
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FINTEK=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_MEN_MCB=m
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI1XXXX=m
+CONFIG_SERIAL_8250_PCI=m
 CONFIG_SERIAL_8250_PERICOM=m
-CONFIG_SPMI_MTK_PMIF=m
-CONFIG_PINCTRL_IMXRT1050=y
-CONFIG_PINCTRL_IMX93=m
-CONFIG_PINCTRL_SDX65=m
-CONFIG_PINCTRL_SM8450=m
-CONFIG_PINCTRL_SM8450_LPASS_LPI=m
-CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
-CONFIG_PINCTRL_SM8280XP_LPASS_LPI=m
-CONFIG_GPIO_SIM=m
-CONFIG_CHARGER_MAX77976=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_SENSORS_NZXT_SMART2=m
-CONFIG_SENSORS_DELTA_AHE50DC_FAN=m
-CONFIG_SENSORS_IR38064_REGULATOR=y
-CONFIG_SENSORS_MP5023=m
-CONFIG_SENSORS_INA238=m
-CONFIG_RZG2L_THERMAL=m
-CONFIG_RENESAS_RZG2LWDT=m
-CONFIG_REGULATOR_MAX20086=m
-CONFIG_VIDEO_STM32_DMA2D=m
-CONFIG_VIDEO_OV5693=m
-CONFIG_DRM_RCAR_USE_LVDS=y
-CONFIG_DRM_RCAR_USE_MIPI_DSI=y
-CONFIG_DRM_RCAR_MIPI_DSI=m
-CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
-CONFIG_DRM_PANEL_JDI_R63452=m
-CONFIG_DRM_PANEL_NOVATEK_NT35950=m
-CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
-CONFIG_TINYDRM_ILI9163=m
-CONFIG_SND_AMD_ACP_CONFIG=m
-CONFIG_SND_SOC_APPLE_MCA=m
-CONFIG_SND_SOC_AK4375=m
-CONFIG_SND_SOC_TLV320ADC3XXX=m
-CONFIG_HID_LETSKETCH=m
-CONFIG_LEDS_MT6360=m
-CONFIG_VIDEO_MAX96712=m
-CONFIG_COMMON_CLK_LAN966X=y
-CONFIG_COMMON_CLK_MT7986=y
-CONFIG_COMMON_CLK_MT7986_ETHSYS=y
-CONFIG_RENESAS_OSTM=y
-CONFIG_EXYNOS_USI=m
-CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
-CONFIG_AD74413R=m
-CONFIG_AD3552R=m
-CONFIG_AD7293=m
-CONFIG_ADMV1013=m
-CONFIG_ADMV1014=m
-CONFIG_ADMV4420=m
-CONFIG_PHY_MESON8_HDMI_TX=m
-CONFIG_PHY_FSL_IMX8M_PCIE=m
-CONFIG_PHY_FSL_LYNX_28G=m
-CONFIG_PHY_LAN966X_SERDES=m
-CONFIG_PHY_QCOM_EDP=m
-# CONFIG_CACHEFILES_ERROR_INJECTION is not set
-CONFIG_UNICODE_UTF8_DATA=m
-# CONFIG_NET_DEV_REFCNT_TRACKER is not set
-# CONFIG_NET_NS_REFCNT_TRACKER is not set
-# CONFIG_KFENCE is not set
-# CONFIG_FTRACE_SORT_STARTUP_TEST is not set
-CONFIG_BACKTRACE_VERBOSE=y
-CONFIG_ADMV8818=m
-CONFIG_MARVELL_CN10K_TAD_PMU=m
-CONFIG_APPLE_M1_CPU_PMU=y
-CONFIG_ALIBABA_UNCORE_DRW_PMU=m
-# CONFIG_KCSAN is not set
-CONFIG_PECI=m
-CONFIG_PECI_CPU=m
-CONFIG_PECI_ASPEED=m
-CONFIG_SENSORS_PECI_CPUTEMP=m
-CONFIG_SENSORS_PECI_DIMMTEMP=m
-# CONFIG_BOOT_CONFIG_EMBED is not set
-CONFIG_INITRAMFS_PRESERVE_MTIME=y
-CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y
-CONFIG_ARCH_BCMBCA=y
-CONFIG_ARCH_HPE=y
-CONFIG_ARCH_HPE_GXP=y
-CONFIG_ARM_ERRATA_764319=y
-# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
-CONFIG_CAN_CTUCANFD_PCI=m
-CONFIG_CAN_CTUCANFD_PLATFORM=m
-CONFIG_FW_LOADER_COMPRESS_XZ=y
-CONFIG_FW_LOADER_COMPRESS_ZSTD=y
-CONFIG_FW_UPLOAD=y
-CONFIG_QCOM_SSC_BLOCK_BUS=y
-CONFIG_MHI_BUS_EP=m
-CONFIG_MTK_ADSP_IPC=m
-CONFIG_EFI_COCO_SECRET=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=m
+CONFIG_SERIAL_8250_PXA=m
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_TEGRA=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_ALTERA_JTAGUART=m
+CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
+CONFIG_SERIAL_ALTERA_UART=m
+CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
+CONFIG_SERIAL_ARC=m
+CONFIG_SERIAL_ARC_NR_PORTS=1
+CONFIG_SERIAL_BCM63XX=m
+CONFIG_SERIAL_CONEXANT_DIGICOLOR=m
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=m
+CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y
+CONFIG_SERIAL_EARLYCON_SEMIHOST=y
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_FSL_LINFLEXUART=m
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=m
+CONFIG_SERIAL_IFX6X60=m
+CONFIG_SERIAL_IMX_EARLYCON=y
+CONFIG_SERIAL_JSM=m
+CONFIG_SERIAL_LITEUART=m
+CONFIG_SERIAL_LITEUART_MAX_PORTS=1
+CONFIG_SERIAL_MAX3100=m
+CONFIG_SERIAL_MAX310X=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_MEN_Z135=m
+CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE=y
+CONFIG_SERIAL_MILBEAUT_USIO_PORTS=4
+CONFIG_SERIAL_MILBEAUT_USIO=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_OF_PLATFORM=m
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_RP2=m
+CONFIG_SERIAL_RP2_NR_UARTS=32
+CONFIG_SERIAL_SC16IS7XX_CORE=m
+CONFIG_SERIAL_SC16IS7XX_I2C=y
+CONFIG_SERIAL_SC16IS7XX=m
+CONFIG_SERIAL_SC16IS7XX_SPI=y
+CONFIG_SERIAL_SCCNXP=m
+CONFIG_SERIAL_SIFIVE=m
+CONFIG_SERIAL_SPRD=m
+CONFIG_SERIAL_ST_ASC=m
+CONFIG_SERIAL_TEGRA_UTC_CONSOLE=y
+CONFIG_SERIAL_TEGRA_UTC=m
+CONFIG_SERIAL_UARTLITE=m
+CONFIG_SERIAL_UARTLITE_NR_UARTS=1
+CONFIG_SERIAL_XILINX_PS_UART=m
+CONFIG_SERIO_ALTERA_PS2=m
+CONFIG_SERIO_APBPS2=m
+CONFIG_SERIO_ARC_PS2=m
+CONFIG_SERIO_GPIO_PS2=m
+CONFIG_SERIO=m
+CONFIG_SERIO_PARKBD=m
+CONFIG_SERIO_PCIPS2=m
+CONFIG_SERIO_PS2MULT=m
+CONFIG_SERIO_RAW=m
+CONFIG_SERIO_SERPORT=m
+CONFIG_SET_FS=y
 CONFIG_SFC_SIENA=m
-CONFIG_SFC_SIENA_MTD=y
 CONFIG_SFC_SIENA_MCDI_MON=y
+CONFIG_SFC_SIENA_MTD=y
 CONFIG_SFC_SIENA_SRIOV=y
-# CONFIG_SFC_SIENA_MCDI_LOGGING is not set
-CONFIG_ADIN1100_PHY=m
-CONFIG_DP83TD510_PHY=m
-CONFIG_WLAN_VENDOR_PURELIFI=y
-CONFIG_PLFXLC=m
-CONFIG_RTW89_8852CE=m
-CONFIG_WLAN_VENDOR_SILABS=y
-CONFIG_MTK_T7XX=m
-CONFIG_JOYSTICK_SENSEHAT=m
-CONFIG_INPUT_IQS7222=m
-# CONFIG_HVC_DCC_SERIALIZE_SMP is not set
-CONFIG_SPI_MTK_SNFI=m
-CONFIG_PINCTRL_IMXRT1170=y
-CONFIG_PINCTRL_SC7280_LPASS_LPI=m
-CONFIG_PINCTRL_SM8250_LPASS_LPI=m
-CONFIG_SENSORS_LAN966X=m
-CONFIG_SENSORS_NCT6775_I2C=m
-CONFIG_SENSORS_XDPE152=m
-CONFIG_RENESAS_RZN1WDT=m
-CONFIG_GXP_WATCHDOG=m
-CONFIG_REGULATOR_RT5759=m
-CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
-CONFIG_DRM_FSL_LDB=m
-CONFIG_DRM_LONTIUM_LT9211=m
-CONFIG_DRM_DW_HDMI_GP_AUDIO=m
-CONFIG_DRM_SSD130X_SPI=m
+CONFIG_SF_PDMA=m
+CONFIG_SGETMASK_SYSCALL=y
+CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
+CONFIG_SI1133=m
+CONFIG_SI1145=m
+CONFIG_SI7005=m
+CONFIG_SI7020=m
+CONFIG_SIGNED_PE_FILE_VERIFICATION=y
+CONFIG_SIMPLE_PM_BUS=m
+CONFIG_SIOX_BUS_GPIO=m
+CONFIG_SIOX=m
+CONFIG_SIRF_IRQ=y
+CONFIG_SIRFSOC_WATCHDOG=y
+CONFIG_SL28CPLD_WATCHDOG=m
+CONFIG_SLAB_FREELIST_HARDENED=y
+CONFIG_SLAB_FREELIST_RANDOM=y
+CONFIG_SLAB_MERGE_DEFAULT=y
+CONFIG_SLHC=m
+CONFIG_SLIMBUS=m
+CONFIG_SLIM_QCOM_CTRL=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLIP=m
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_SLIP_SMART=y
+CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
+CONFIG_SMB_SERVER_KERBEROS5=y
+CONFIG_SMB_SERVER=m
+CONFIG_SMB_SERVER_SMBDIRECT=y
+CONFIG_SM_FTL=m
+CONFIG_SMP_ON_UP=y
+CONFIG_SMPRO_ERRMON=m
+CONFIG_SMPRO_MISC=m
+CONFIG_SMSC_PHY=m
+CONFIG_SMS_SDIO_DRV=m
+CONFIG_SMS_SIANO_MDTV=m
+CONFIG_SMS_SIANO_RC=y
+CONFIG_SMS_USB_DRV=m
+CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
+CONFIG_SND_AC97_POWER_SAVE=y
+CONFIG_SND_AD1889=m
+CONFIG_SND_ALOOP=m
+CONFIG_SND_AMD_ACP_CONFIG=m
+CONFIG_SND_ARM=y
+CONFIG_SND_ATIIXP=m
+CONFIG_SND_ATIIXP_MODEM=m
+CONFIG_SND_ATMEL_SOC=m
+CONFIG_SND_AU8810=m
+CONFIG_SND_AU8820=m
+CONFIG_SND_AU8830=m
+CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
+CONFIG_SND_AUDIO_GRAPH_CARD2=m
+CONFIG_SND_AUDIO_GRAPH_CARD=m
+CONFIG_SND_AW2=m
+CONFIG_SND_BCD2000=m
+CONFIG_SND_BCM63XX_I2S_WHISTLER=m
+CONFIG_SND_BEBOB=m
+CONFIG_SND_BT87X=m
+CONFIG_SND_BT87X_OVERCLOCK=y
+CONFIG_SND_CA0106=m
+CONFIG_SND_CMIPCI=m
+CONFIG_SND_CS4281=m
+CONFIG_SND_CS46XX=m
+CONFIG_SND_CS46XX_NEW_DSP=y
+CONFIG_SND_CTL_FAST_LOOKUP=y
+CONFIG_SND_CTL_INPUT_VALIDATION=y
+CONFIG_SND_CTXFI=m
+CONFIG_SND_DARLA20=m
+CONFIG_SND_DARLA24=m
+CONFIG_SND_DESIGNWARE_I2S=m
+CONFIG_SND_DESIGNWARE_PCM=y
+CONFIG_SND_DICE=m
+CONFIG_SND_DMAENGINE_PCM=m
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_DUMMY=m
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_ECHO3G=m
+CONFIG_SND_ENS1370=m
+CONFIG_SND_ENS1371=m
+CONFIG_SND_FIREFACE=m
+CONFIG_SND_FIREWIRE_DIGI00X=m
+CONFIG_SND_FIREWIRE_LIB=m
+CONFIG_SND_FIREWIRE_MOTU=m
+CONFIG_SND_FIREWIRE_TASCAM=m
+CONFIG_SND_FIREWIRE=y
+CONFIG_SND_FIREWORKS=m
+CONFIG_SND_FM801=m
+CONFIG_SND_FM801_TEA575X_BOOL=y
+CONFIG_SND_GINA20=m
+CONFIG_SND_GINA24=m
+CONFIG_SND_HDA_CODEC_ALC260=m
+CONFIG_SND_HDA_CODEC_ALC262=m
+CONFIG_SND_HDA_CODEC_ALC268=m
+CONFIG_SND_HDA_CODEC_ALC269=m
+CONFIG_SND_HDA_CODEC_ALC662=m
+CONFIG_SND_HDA_CODEC_ALC680=m
+CONFIG_SND_HDA_CODEC_ALC861=m
+CONFIG_SND_HDA_CODEC_ALC861VD=m
+CONFIG_SND_HDA_CODEC_ALC880=m
+CONFIG_SND_HDA_CODEC_ALC882=m
+CONFIG_SND_HDA_CODEC_ANALOG=m
+CONFIG_SND_HDA_CODEC_CA0110=m
+CONFIG_SND_HDA_CODEC_CA0132_DSP=y
+CONFIG_SND_HDA_CODEC_CA0132=m
+CONFIG_SND_HDA_CODEC_CIRRUS=m
+CONFIG_SND_HDA_CODEC_CM9825=m
+CONFIG_SND_HDA_CODEC_CMEDIA=m
+CONFIG_SND_HDA_CODEC_CONEXANT=m
+CONFIG_SND_HDA_CODEC_CS420X=m
+CONFIG_SND_HDA_CODEC_CS421X=m
+CONFIG_SND_HDA_CODEC_CS8409=m
+CONFIG_SND_HDA_CODEC_HDMI_ATI=m
+CONFIG_SND_HDA_CODEC_HDMI_INTEL=m
+CONFIG_SND_HDA_CODEC_HDMI=m
+CONFIG_SND_HDA_CODEC_HDMI_NVIDIA=m
+CONFIG_SND_HDA_CODEC_HDMI_NVIDIA_MCP=m
+CONFIG_SND_HDA_CODEC_HDMI_TEGRA=m
+CONFIG_SND_HDA_CODEC_REALTEK=m
+CONFIG_SND_HDA_CODEC_SENARYTECH=m
+CONFIG_SND_HDA_CODEC_SI3054=m
+CONFIG_SND_HDA_CODEC_SIGMATEL=m
+CONFIG_SND_HDA_CODEC_VIA=m
+CONFIG_SND_HDA_COMPONENT=y
+CONFIG_SND_HDA_CORE=m
+CONFIG_SND_HDA_DSP_LOADER=y
+CONFIG_SND_HDA_GENERIC_LEDS=y
+CONFIG_SND_HDA_GENERIC=m
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_INPUT_BEEP_MODE=1
+CONFIG_SND_HDA_INPUT_BEEP=y
+CONFIG_SND_HDA_INTEL=m
+CONFIG_SND_HDA=m
+CONFIG_SND_HDA_PATCH_LOADER=y
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
+CONFIG_SND_HDA_PREALLOC_SIZE=2048
+CONFIG_SND_HDA_RECONFIG=y
+CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m
+CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m
+CONFIG_SND_HDA_SCODEC_CS35L56_I2C=m
+CONFIG_SND_HDA_SCODEC_CS35L56_SPI=m
+CONFIG_SND_HDA_SCODEC_TAS2781_I2C=m
+CONFIG_SND_HDSP=m
+CONFIG_SND_HDSPM=m
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_I2S_HI6210_I2S=m
+CONFIG_SND_ICE1724=m
+CONFIG_SND_INDIGODJ=m
+CONFIG_SND_INDIGODJX=m
+CONFIG_SND_INDIGOIO=m
+CONFIG_SND_INDIGOIOX=m
+CONFIG_SND_INDIGO=m
+CONFIG_SND_INTEL8X0=m
+CONFIG_SND_INTEL8X0M=m
+CONFIG_SND_INTEL_DSP_CONFIG=m
+CONFIG_SND_ISIGHT=m
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_JACK=y
+CONFIG_SND_KORG1212=m
+CONFIG_SND_LAYLA20=m
+CONFIG_SND_LAYLA24=m
+CONFIG_SND_LOLA=m
+CONFIG_SND=m
+CONFIG_SND_MAX_CARDS=32
+CONFIG_SND_MCHP_SOC_PDMC=m
+CONFIG_SND_MCHP_SOC_SPDIFRX=m
+CONFIG_SND_MCHP_SOC_SPDIFTX=m
+CONFIG_SND_MIA=m
+CONFIG_SND_MIXART=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_MMP_SOC_SSPA=m
+CONFIG_SND_MONA=m
+CONFIG_SND_MPU401=m
+CONFIG_SND_MPU401_UART=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_MTS64=m
+CONFIG_SND_NM256=m
+CONFIG_SND_OPL3_LIB=m
+CONFIG_SND_OPL3_LIB_SEQ=m
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_OXFW=m
+CONFIG_SND_OXYGEN_LIB=m
+CONFIG_SND_OXYGEN=m
+CONFIG_SND_PCI=y
+CONFIG_SND_PCMCIA=y
+CONFIG_SND_PCM_ELD=y
+CONFIG_SND_PCM_IEC958=y
+CONFIG_SND_PCM=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_PCMTEST=m
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_PCXHR=m
+CONFIG_SND_PDAUDIOCF=m
+CONFIG_SND_PORTMAN2X4=m
+CONFIG_SND_PROC_FS=y
+CONFIG_SND_PXA910_SOC=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_RIPTIDE=m
+CONFIG_SND_RME32=m
+CONFIG_SND_RME9652=m
+CONFIG_SND_RME96=m
+CONFIG_SND_SEQ_DEVICE=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+CONFIG_SND_SEQ_MIDI_EMUL=m
+CONFIG_SND_SEQ_MIDI_EVENT=m
+CONFIG_SND_SEQ_MIDI=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQUENCER_OSS=m
+CONFIG_SND_SEQ_UMP=y
+CONFIG_SND_SEQ_VIRMIDI=m
 CONFIG_SND_SERIAL_GENERIC=m
-CONFIG_SND_SOC_CS35L45_SPI=m
+CONFIG_SND_SERIAL_U16550=m
+CONFIG_SND_SIMPLE_CARD=m
+CONFIG_SND_SIMPLE_CARD_UTILS=m
+CONFIG_SND_SOC_AC97_CODEC=m
+CONFIG_SND_SOC_ADAU1372_I2C=m
+CONFIG_SND_SOC_ADAU1372_SPI=m
+CONFIG_SND_SOC_ADAU1701=m
+CONFIG_SND_SOC_ADAU1761_I2C=m
+CONFIG_SND_SOC_ADAU1761=m
+CONFIG_SND_SOC_ADAU1761_SPI=m
+CONFIG_SND_SOC_ADAU17X1=m
+CONFIG_SND_SOC_ADAU7002=m
+CONFIG_SND_SOC_ADAU7118_HW=m
+CONFIG_SND_SOC_ADAU7118_I2C=m
+CONFIG_SND_SOC_ADAU7118=m
+CONFIG_SND_SOC_ADAU_UTILS=m
+CONFIG_SND_SOC_ADI_AXI_I2S=m
+CONFIG_SND_SOC_ADI_AXI_SPDIF=m
+CONFIG_SND_SOC_AK4104=m
+CONFIG_SND_SOC_AK4118=m
+CONFIG_SND_SOC_AK4375=m
+CONFIG_SND_SOC_AK4458=m
+CONFIG_SND_SOC_AK4554=m
+CONFIG_SND_SOC_AK4613=m
+CONFIG_SND_SOC_AK4619=m
+CONFIG_SND_SOC_AK4642=m
+CONFIG_SND_SOC_AK5386=m
+CONFIG_SND_SOC_AK5558=m
+CONFIG_SND_SOC_ALC5623=m
+CONFIG_SND_SOC_AMD_ACP=m
+CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m
+CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
+CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m
+CONFIG_SND_SOC_APPLE_MCA=m
+CONFIG_SND_SOC_AUDIO_IIO_AUX=m
+CONFIG_SND_SOC_AW8738=m
+CONFIG_SND_SOC_AW87390=m
+CONFIG_SND_SOC_AW88166=m
+CONFIG_SND_SOC_AW88261=m
+CONFIG_SND_SOC_AW88395=m
+CONFIG_SND_SOC_AW88399=m
+CONFIG_SND_SOC_BD28623=m
+CONFIG_SND_SOC_BT_SCO=m
+CONFIG_SND_SOC_CHV3_CODEC=m
+CONFIG_SND_SOC_CHV3_I2S=m
+CONFIG_SND_SOC_CPCAP=m
+CONFIG_SND_SOC_CROS_EC_CODEC=m
+CONFIG_SND_SOC_CS35L32=m
+CONFIG_SND_SOC_CS35L33=m
+CONFIG_SND_SOC_CS35L34=m
+CONFIG_SND_SOC_CS35L35=m
+CONFIG_SND_SOC_CS35L36=m
+CONFIG_SND_SOC_CS35L41_I2C=m
+CONFIG_SND_SOC_CS35L41_SPI=m
 CONFIG_SND_SOC_CS35L45_I2C=m
+CONFIG_SND_SOC_CS35L45_SPI=m
+CONFIG_SND_SOC_CS35L56_I2C=m
+CONFIG_SND_SOC_CS35L56_SDW=m
+CONFIG_SND_SOC_CS35L56_SPI=m
+CONFIG_SND_SOC_CS40L50=m
+CONFIG_SND_SOC_CS4234=m
+CONFIG_SND_SOC_CS4265=m
+CONFIG_SND_SOC_CS4270=m
+CONFIG_SND_SOC_CS4271_I2C=m
+CONFIG_SND_SOC_CS4271=m
+CONFIG_SND_SOC_CS4271_SPI=m
+CONFIG_SND_SOC_CS42L42=m
+CONFIG_SND_SOC_CS42L42_SDW=m
+CONFIG_SND_SOC_CS42L43=m
+CONFIG_SND_SOC_CS42L43_SDW=m
+CONFIG_SND_SOC_CS42L51_I2C=m
+CONFIG_SND_SOC_CS42L51=m
+CONFIG_SND_SOC_CS42L52=m
+CONFIG_SND_SOC_CS42L56=m
+CONFIG_SND_SOC_CS42L73=m
+CONFIG_SND_SOC_CS42L83=m
+CONFIG_SND_SOC_CS42XX8_I2C=m
+CONFIG_SND_SOC_CS42XX8=m
+CONFIG_SND_SOC_CS43130=m
+CONFIG_SND_SOC_CS4341=m
+CONFIG_SND_SOC_CS4349=m
+CONFIG_SND_SOC_CS530X_I2C=m
+CONFIG_SND_SOC_CS53L30=m
+CONFIG_SND_SOC_CX2072X=m
+CONFIG_SND_SOC_DA7213=m
+CONFIG_SND_SOC_DA7219=m
+CONFIG_SND_SOC_DMIC=m
+CONFIG_SND_SOC_ES7134=m
+CONFIG_SND_SOC_ES7241=m
+CONFIG_SND_SOC_ES8311=m
+CONFIG_SND_SOC_ES8316=m
+CONFIG_SND_SOC_ES8326=m
+CONFIG_SND_SOC_ES8328_I2C=m
+CONFIG_SND_SOC_ES8328=m
+CONFIG_SND_SOC_ES8328_SPI=m
+CONFIG_SND_SOC_FRAMER=m
+CONFIG_SND_SOC_FS210X=m
+CONFIG_SND_SOC_FSL_ASRC=m
+CONFIG_SND_SOC_FSL_AUD2HTX=m
+CONFIG_SND_SOC_FSL_AUDMIX=m
+CONFIG_SND_SOC_FSL_EASRC=m
+CONFIG_SND_SOC_FSL_ESAI=m
+CONFIG_SND_SOC_FSL_MICFIL=m
+CONFIG_SND_SOC_FSL_MQS=m
+CONFIG_SND_SOC_FSL_RPMSG=m
+CONFIG_SND_SOC_FSL_SAI=m
+CONFIG_SND_SOC_FSL_SPDIF=m
+CONFIG_SND_SOC_FSL_SSI=m
+CONFIG_SND_SOC_FSL_XCVR=m
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_GTM601=m
+CONFIG_SND_SOC_HDA=m
+CONFIG_SND_SOC_HDMI_CODEC=m
+CONFIG_SND_SOC_I2C_AND_SPI=m
+CONFIG_SND_SOC_ICS43432=m
+CONFIG_SND_SOC_IDT821034=m
+CONFIG_SND_SOC_IMG_I2S_IN=m
+CONFIG_SND_SOC_IMG_I2S_OUT=m
+CONFIG_SND_SOC_IMG_PARALLEL_OUT=m
+CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m
+CONFIG_SND_SOC_IMG_SPDIF_IN=m
+CONFIG_SND_SOC_IMG_SPDIF_OUT=m
+CONFIG_SND_SOC_IMG=y
+CONFIG_SND_SOC_IMX_AUDMUX=m
+CONFIG_SND_SOC_IMX_CARD=m
+CONFIG_SND_SOC_INNO_RK3036=m
+CONFIG_SND_SOC_LPASS_RX_MACRO=m
+CONFIG_SND_SOC_LPASS_TX_MACRO=m
+CONFIG_SND_SOC_LPASS_VA_MACRO=m
+CONFIG_SND_SOC_LPASS_WSA_MACRO=m
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_MAX9759=m
+CONFIG_SND_SOC_MAX98088=m
+CONFIG_SND_SOC_MAX98090=m
+CONFIG_SND_SOC_MAX98357A=m
+CONFIG_SND_SOC_MAX98363=m
+CONFIG_SND_SOC_MAX98373_I2C=m
+CONFIG_SND_SOC_MAX98373=m
+CONFIG_SND_SOC_MAX98373_SDW=m
+CONFIG_SND_SOC_MAX98388=m
+CONFIG_SND_SOC_MAX98390=m
 CONFIG_SND_SOC_MAX98396=m
+CONFIG_SND_SOC_MAX98504=m
+CONFIG_SND_SOC_MAX98520=m
+CONFIG_SND_SOC_MAX9860=m
+CONFIG_SND_SOC_MAX9867=m
+CONFIG_SND_SOC_MAX98927=m
+CONFIG_SND_SOC_MIKROE_PROTO=m
+CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
+CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
+CONFIG_SND_SOC_MT6351=m
+CONFIG_SND_SOC_MT6357=m
+CONFIG_SND_SOC_MT6358=m
+CONFIG_SND_SOC_MT6660=m
+CONFIG_SND_SOC_MT7986=m
+CONFIG_SND_SOC_MT7986_WM8960=m
+CONFIG_SND_SOC_MT8136=m
+CONFIG_SND_SOC_MT8186=m
+CONFIG_SND_SOC_MT8186_MT6366_DA7219_MAX98357=m
+CONFIG_SND_SOC_MT8186_MT6366_RT1019_RT5682S=m
+CONFIG_SND_SOC_MT8188=m
+CONFIG_SND_SOC_MT8188_MT6359=m
+CONFIG_SND_SOC_MT8192=m
+CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682=m
+CONFIG_SND_SOC_MT8195=m
+CONFIG_SND_SOC_MT8365=m
+CONFIG_SND_SOC_MTK_BTCVSD=m
+CONFIG_SND_SOC_NAU8315=m
+CONFIG_SND_SOC_NAU8540=m
+CONFIG_SND_SOC_NAU8810=m
+CONFIG_SND_SOC_NAU8821=m
+CONFIG_SND_SOC_NAU8822=m
+CONFIG_SND_SOC_NAU8824=m
+CONFIG_SND_SOC_PCM1681=m
+CONFIG_SND_SOC_PCM1754=m
+CONFIG_SND_SOC_PCM1789_I2C=m
+CONFIG_SND_SOC_PCM1789=m
+CONFIG_SND_SOC_PCM179X_I2C=m
+CONFIG_SND_SOC_PCM179X=m
+CONFIG_SND_SOC_PCM179X_SPI=m
+CONFIG_SND_SOC_PCM186X_I2C=m
+CONFIG_SND_SOC_PCM186X=m
+CONFIG_SND_SOC_PCM186X_SPI=m
+CONFIG_SND_SOC_PCM3060_I2C=m
+CONFIG_SND_SOC_PCM3060=m
+CONFIG_SND_SOC_PCM3060_SPI=m
+CONFIG_SND_SOC_PCM3168A_I2C=m
+CONFIG_SND_SOC_PCM3168A=m
+CONFIG_SND_SOC_PCM3168A_SPI=m
+CONFIG_SND_SOC_PCM5102A=m
+CONFIG_SND_SOC_PCM512x_I2C=m
+CONFIG_SND_SOC_PCM512x=m
+CONFIG_SND_SOC_PCM512x_SPI=m
+CONFIG_SND_SOC_PCM6240=m
+CONFIG_SND_SOC_PEB2466=m
+CONFIG_SND_SOC_PM4125_SDW=m
+CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
+CONFIG_SND_SOC_RK3328=m
+CONFIG_SND_SOC_RK3399_GRU_SOUND=m
+CONFIG_SND_SOC_RK817=m
+CONFIG_SND_SOC_RL6231=m
+CONFIG_SND_SOC_ROCKCHIP_I2S=m
+CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
+CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
+CONFIG_SND_SOC_ROCKCHIP_PDM=m
+CONFIG_SND_SOC_ROCKCHIP_RT5645=m
+CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
+CONFIG_SND_SOC_RT1017_SDCA_SDW=m
+CONFIG_SND_SOC_RT1308_SDW=m
+CONFIG_SND_SOC_RT1316_SDW=m
+CONFIG_SND_SOC_RT1318_SDW=m
+CONFIG_SND_SOC_RT1320_SDW=m
+CONFIG_SND_SOC_RT5616=m
+CONFIG_SND_SOC_RT5631=m
+CONFIG_SND_SOC_RT5640=m
+CONFIG_SND_SOC_RT5645=m
+CONFIG_SND_SOC_RT5659=m
+CONFIG_SND_SOC_RT5682=m
+CONFIG_SND_SOC_RT5682_SDW=m
+CONFIG_SND_SOC_RT700=m
+CONFIG_SND_SOC_RT700_SDW=m
+CONFIG_SND_SOC_RT711=m
+CONFIG_SND_SOC_RT711_SDCA_SDW=m
+CONFIG_SND_SOC_RT711_SDW=m
+CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW=m
+CONFIG_SND_SOC_RT712_SDCA_SDW=m
+CONFIG_SND_SOC_RT715=m
+CONFIG_SND_SOC_RT715_SDCA_SDW=m
+CONFIG_SND_SOC_RT715_SDW=m
+CONFIG_SND_SOC_RT722_SDCA_SDW=m
+CONFIG_SND_SOC_RT9120=m
+CONFIG_SND_SOC_RTQ9128=m
+CONFIG_SND_SOC_SDW_MOCKUP=m
+CONFIG_SND_SOC_SGTL5000=m
+CONFIG_SND_SOC_SI476X=m
+CONFIG_SND_SOC_SIGMADSP_I2C=m
+CONFIG_SND_SOC_SIGMADSP=m
+CONFIG_SND_SOC_SIGMADSP_REGMAP=m
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+CONFIG_SND_SOC_SIMPLE_MUX=m
+CONFIG_SND_SOC_SIRF_AUDIO_CODEC=m
+CONFIG_SND_SOC_SMA1303=m
+CONFIG_SND_SOC_SOF_AMD_RENOIR=m
+CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m
+CONFIG_SND_SOC_SOF=m
+CONFIG_SND_SOC_SOF_OF=m
+CONFIG_SND_SOC_SOF_PCI=m
+CONFIG_SND_SOC_SOF_TOPLEVEL=y
+CONFIG_SND_SOC_SPDIF=m
+CONFIG_SND_SOC_SRC4XXX_I2C=m
+CONFIG_SND_SOC_SSM2305=m
+CONFIG_SND_SOC_SSM2518=m
+CONFIG_SND_SOC_SSM2602_I2C=m
+CONFIG_SND_SOC_SSM2602=m
+CONFIG_SND_SOC_SSM2602_SPI=m
+CONFIG_SND_SOC_SSM3515=m
+CONFIG_SND_SOC_SSM4567=m
+CONFIG_SND_SOC_STA32X=m
+CONFIG_SND_SOC_STA350=m
+CONFIG_SND_SOC_STI_SAS=m
+CONFIG_SND_SOC_TAS2552=m
+CONFIG_SND_SOC_TAS2562=m
+CONFIG_SND_SOC_TAS2764=m
+CONFIG_SND_SOC_TAS2770=m
+CONFIG_SND_SOC_TAS2780=m
+CONFIG_SND_SOC_TAS2781_I2C=m
+CONFIG_SND_SOC_TAS2783_SDW=m
+CONFIG_SND_SOC_TAS5086=m
+CONFIG_SND_SOC_TAS571X=m
+CONFIG_SND_SOC_TAS5720=m
+CONFIG_SND_SOC_TAS5805M=m
+CONFIG_SND_SOC_TAS6424=m
+CONFIG_SND_SOC_TDA7419=m
+CONFIG_SND_SOC_TFA9879=m
+CONFIG_SND_SOC_TFA989X=m
+CONFIG_SND_SOC_TLV320ADC3XXX=m
+CONFIG_SND_SOC_TLV320ADCX140=m
+CONFIG_SND_SOC_TLV320AIC23_I2C=m
+CONFIG_SND_SOC_TLV320AIC23=m
+CONFIG_SND_SOC_TLV320AIC23_SPI=m
+CONFIG_SND_SOC_TLV320AIC31XX=m
+CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
+CONFIG_SND_SOC_TLV320AIC32X4=m
+CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
+CONFIG_SND_SOC_TLV320AIC3X_I2C=m
+CONFIG_SND_SOC_TLV320AIC3X=m
+CONFIG_SND_SOC_TLV320AIC3X_SPI=m
+CONFIG_SND_SOC_TOPOLOGY=y
+CONFIG_SND_SOC_TPA6130A2=m
+CONFIG_SND_SOC_TS3A227E=m
+CONFIG_SND_SOC_TSCS42XX=m
+CONFIG_SND_SOC_TSCS454=m
+CONFIG_SND_SOC_UDA1334=m
+CONFIG_SND_SOC_UNIPHIER_AIO=m
+CONFIG_SND_SOC_UNIPHIER_EVEA_CODEC=m
+CONFIG_SND_SOC_UNIPHIER_LD11=m
+CONFIG_SND_SOC_UNIPHIER_PXS2=m
+CONFIG_SND_SOC_WCD9335=m
+CONFIG_SND_SOC_WCD934X=m
+CONFIG_SND_SOC_WCD937X_SDW=m
+CONFIG_SND_SOC_WCD938X_SDW=m
+CONFIG_SND_SOC_WCD939X_SDW=m
+CONFIG_SND_SOC_WM8510=m
+CONFIG_SND_SOC_WM8523=m
+CONFIG_SND_SOC_WM8524=m
+CONFIG_SND_SOC_WM8580=m
+CONFIG_SND_SOC_WM8711=m
+CONFIG_SND_SOC_WM8728=m
 CONFIG_SND_SOC_WM8731_I2C=m
+CONFIG_SND_SOC_WM8731=m
 CONFIG_SND_SOC_WM8731_SPI=m
+CONFIG_SND_SOC_WM8737=m
+CONFIG_SND_SOC_WM8741=m
+CONFIG_SND_SOC_WM8750=m
+CONFIG_SND_SOC_WM8753=m
+CONFIG_SND_SOC_WM8770=m
+CONFIG_SND_SOC_WM8776=m
+CONFIG_SND_SOC_WM8782=m
+CONFIG_SND_SOC_WM8804_I2C=m
+CONFIG_SND_SOC_WM8804=m
+CONFIG_SND_SOC_WM8804_SPI=m
+CONFIG_SND_SOC_WM8903=m
+CONFIG_SND_SOC_WM8904=m
 CONFIG_SND_SOC_WM8940=m
-CONFIG_HID_MEGAWORLD_FF=m
-CONFIG_TYPEC_MUX_FSA4480=m
-CONFIG_LEDS_PWM_MULTICOLOR=m
-CONFIG_LEDS_QCOM_LPG=m
+CONFIG_SND_SOC_WM8960=m
+CONFIG_SND_SOC_WM8961=m
+CONFIG_SND_SOC_WM8962=m
+CONFIG_SND_SOC_WM8974=m
+CONFIG_SND_SOC_WM8978=m
+CONFIG_SND_SOC_WM8985=m
+CONFIG_SND_SOC_WSA881X=m
+CONFIG_SND_SOC_WSA883X=m
+CONFIG_SND_SOC_WSA884X=m
+CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
+CONFIG_SND_SOC_XILINX_I2S=m
+CONFIG_SND_SOC_XILINX_SPDIF=m
+CONFIG_SND_SOC_XTFPGA_I2S=m
+CONFIG_SND_SOC_ZL38060=m
+CONFIG_SND_SOC_ZX_AUD96P22=m
+CONFIG_SND_SPI=y
+CONFIG_SND_SUN50I_DMIC=m
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_TEST_COMPONENT=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_UMP_LEGACY_RAWMIDI=y
+CONFIG_SND_USB_6FIRE=m
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_AUDIO_MIDI_V2=y
+CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_HIFACE=m
+CONFIG_SND_USB_LINE6=m
+CONFIG_SND_USB_PODHD=m
+CONFIG_SND_USB_POD=m
+CONFIG_SND_USB_TONEPORT=m
+CONFIG_SND_USB_UA101=m
+CONFIG_SND_USB_VARIAX=m
+CONFIG_SND_USB=y
+CONFIG_SND_UTIMER=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VIA82XX=m
+CONFIG_SND_VIA82XX_MODEM=m
+CONFIG_SND_VIRMIDI=m
+CONFIG_SND_VIRTIO=m
+CONFIG_SND_VIRTUOSO=m
+CONFIG_SND_VMASTER=y
+CONFIG_SND_VX222=m
+CONFIG_SND_VX_LIB=m
+CONFIG_SND_VXPOCKET=m
+CONFIG_SND_YMFPCI=m
+CONFIG_SNET_VDPA=m
+CONFIG_SOC_AM33XX=y
+CONFIG_SOC_AM43XX=y
+CONFIG_SOC_ASPEED=y
+CONFIG_SOC_BUS=y
+CONFIG_SOC_DRA7XX=y
+CONFIG_SOC_EXYNOS3250=y
+CONFIG_SOC_EXYNOS4212=y
+CONFIG_SOC_EXYNOS4412=y
+CONFIG_SOC_EXYNOS5250=y
+CONFIG_SOC_EXYNOS5260=y
+CONFIG_SOC_EXYNOS5410=y
+CONFIG_SOC_EXYNOS5420=y
+CONFIG_SOC_EXYNOS5800=y
+CONFIG_SOCFPGA_SUSPEND=y
+CONFIG_SOC_HAS_OMAP2_SDRC=y
+CONFIG_SOC_HAS_REALTIME_COUNTER=y
+CONFIG_SOC_IMX9=m
+CONFIG_SOCK_CGROUP_DATA=y
+CONFIG_SOCK_VALIDATE_XMIT=y
+CONFIG_SOC_LAN966=y
+CONFIG_SOC_OMAP3430=y
+CONFIG_SOC_OMAP5=y
+CONFIG_SOC_REALVIEW=y
+CONFIG_SOC_RENESAS=y
+CONFIG_SOC_SAMA7D65=y
+CONFIG_SOC_SAMA7G5=y
+CONFIG_SOC_SAMSUNG=y
+CONFIG_SOC_SP7021=y
+CONFIG_SOC_STIH407=y
+CONFIG_SOC_STIH415=y
+CONFIG_SOC_STIH416=y
+CONFIG_SOC_TEGRA_FUSE=y
+CONFIG_SOC_TI81XX=y
+CONFIG_SOC_ZX296702=y
+CONFIG_SOFT_WATCHDOG=m
+CONFIG_SOPHGO_CV1800B_DMAMUX=m
+CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUNDWIRE_AMD=m
+CONFIG_SOUNDWIRE_QCOM=m
+CONFIG_SOUNDWIRE=y
+CONFIG_SP7021_EMAC=m
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_SPEAKUP=m
+CONFIG_SPEAKUP_SYNTH_ACNTSA=m
+CONFIG_SPEAKUP_SYNTH_APOLLO=m
+CONFIG_SPEAKUP_SYNTH_AUDPTR=m
+CONFIG_SPEAKUP_SYNTH_BNS=m
+CONFIG_SPEAKUP_SYNTH_DECEXT=m
+CONFIG_SPEAKUP_SYNTH_DECTLK=m
+CONFIG_SPEAKUP_SYNTH_LTLK=m
+CONFIG_SPEAKUP_SYNTH_SOFT=m
+CONFIG_SPEAKUP_SYNTH_SPKOUT=m
+CONFIG_SPEAKUP_SYNTH_TXPRT=m
+CONFIG_SPI_ALTERA_CORE=m
+CONFIG_SPI_ALTERA_DFL=m
+CONFIG_SPI_ALTERA=m
+CONFIG_SPI_AMD=m
+CONFIG_SPI_AMLOGIC_SPIFC_A1=m
+CONFIG_SPI_AMLOGIC_SPIFC_A4=m
+CONFIG_SPI_AMLOGIC_SPISG=m
+CONFIG_SPI_APPLE=m
+CONFIG_SPI_AX88796C_COMPRESSION=y
+CONFIG_SPI_AX88796C=m
+CONFIG_SPI_AXI_SPI_ENGINE=m
+CONFIG_SPI_BCM63XX_HSSPI=m
+CONFIG_SPI_BCMBCA_HSSPI=m
+CONFIG_SPI_BITBANG=m
+CONFIG_SPI_BUTTERFLY=m
+CONFIG_SPI_CADENCE=m
+CONFIG_SPI_CADENCE_QUADSPI=m
+CONFIG_SPI_CADENCE_XSPI=m
+CONFIG_SPI_CH341=m
+CONFIG_SPI_CS42L43=m
+CONFIG_SPI_DESIGNWARE=m
+CONFIG_SPI_DLN2=m
+CONFIG_SPI_DW_MMIO=m
+CONFIG_SPI_DW_PCI=m
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_FSL_DSPI=m
+CONFIG_SPI_GPIO=m
+CONFIG_SPI_GXP=m
+CONFIG_SPI_HISI_KUNPENG=m
+CONFIG_SPI_LM70_LLP=m
+CONFIG_SPI_LOOPBACK_TEST=m
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_MICROCHIP_CORE=m
+CONFIG_SPI_MICROCHIP_CORE_QSPI=m
+CONFIG_SPI_MTK_SNFI=m
+CONFIG_SPI_MUX=m
+CONFIG_SPI_MXIC=m
+CONFIG_SPI_NXP_FLEXSPI=m
+CONFIG_SPI_OC_TINY=m
+CONFIG_SPI_OFFLOAD_TRIGGER_ADI_UTIL_SD=m
+CONFIG_SPI_OFFLOAD_TRIGGER_PWM=m
+CONFIG_SPI_PCI1XXXX=m
+CONFIG_SPI_PL022=y
+CONFIG_SPI_PXA2XX=m
+CONFIG_SPI_PXA2XX_PCI=m
+CONFIG_SPI_QPIC_SNAND=m
+CONFIG_SPI_ROCKCHIP=m
+CONFIG_SPI_ROCKCHIP_SFC=m
+CONFIG_SPI_RPCIF=m
+CONFIG_SPI_RZV2H_RSPI=m
+CONFIG_SPI_RZV2M_CSI=m
+CONFIG_SPI_SC18IS602=m
+CONFIG_SPI_SIFIVE=m
+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
+CONFIG_SPI_SLAVE_TIME=m
+CONFIG_SPI_SLAVE=y
+CONFIG_SPI_SN_F_OSPI=m
+CONFIG_SPI_SPIDEV=m
+CONFIG_SPI_STM32_OSPI=m
+CONFIG_SPI_SUNPLUS_SP7021=m
+CONFIG_SPI_TEGRA210_QUAD=m
+CONFIG_SPI_TLE62X0=m
+CONFIG_SPI_VIRTIO=m
+CONFIG_SPI_WPCM_FIU=m
+CONFIG_SPI_XCOMM=m
+CONFIG_SPI_XILINX=m
+CONFIG_SPI=y
+CONFIG_SPI_ZYNQMP_GQSPI=m
+CONFIG_SPMI_APPLE=m
+CONFIG_SPMI_HISI3670=m
+CONFIG_SPMI=m
+CONFIG_SPMI_MSM_PMIC_ARB=m
+CONFIG_SPMI_MTK_PMIF=m
+CONFIG_SPS30_I2C=m
+CONFIG_SPS30=m
+CONFIG_SPS30_SERIAL=m
+CONFIG_SRAM_EXEC=y
+CONFIG_SRAM=y
+CONFIG_SRCU=y
+CONFIG_SRF04=m
+CONFIG_SRF08=m
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_BLOCKIO=y
+CONFIG_SSB_DRIVER_GPIO=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB=m
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+CONFIG_SSB_PCMCIAHOST=y
+CONFIG_SSB_SDIOHOST_POSSIBLE=y
+CONFIG_SSB_SDIOHOST=y
+CONFIG_SSB_SPROM=y
+CONFIG_SSFDC=m
+CONFIG_STACK_HASH_ORDER=16
+CONFIG_STACKPROTECTOR_PER_TASK=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACK_TRACER=y
+CONFIG_STACKTRACE=y
+CONFIG_STAGING_MEDIA_DEPRECATED=y
+CONFIG_STAGING_MEDIA=y
+CONFIG_STAGING=y
+CONFIG_STANDALONE=y
+CONFIG_STE10XP=m
+CONFIG_STIH407_RESET=y
+CONFIG_STI_RESET_SYSCFG=y
+CONFIG_ST_IRQCHIP=y
+CONFIG_STK3310=m
+CONFIG_STK8312=m
+CONFIG_STK8BA50=m
+CONFIG_STM32_DMA3=m
+CONFIG_STM32_EXTI=y
+CONFIG_STM32_FMC2_EBI=m
+CONFIG_STM32MP_EXTI=m
+CONFIG_STM32_THERMAL=y
+CONFIG_STM32_WATCHDOG=y
+CONFIG_STM=m
+CONFIG_STMPE_I2C=y
+CONFIG_STMPE_SPI=y
+CONFIG_STM_PROTO_BASIC=m
+CONFIG_STM_PROTO_SYS_T=m
+CONFIG_STM_SOURCE_CONSOLE=m
+CONFIG_STM_SOURCE_HEARTBEAT=m
+CONFIG_STREAM_PARSER=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+CONFIG_STUB_CLK_HI3660=y
+CONFIG_STUB_CLK_HI6220=y
+CONFIG_ST_UVIS25_I2C=m
+CONFIG_ST_UVIS25=m
+CONFIG_ST_UVIS25_SPI=m
+CONFIG_SUN20I_D1_CCU=m
+CONFIG_SUN20I_D1_R_CCU=m
+CONFIG_SUN20I_GPADC=m
+CONFIG_SUN20I_PPU=y
+CONFIG_SUN4I_A10_CCU=y
+CONFIG_SUN4I_TIMER=y
+CONFIG_SUN5I_CCU=y
+CONFIG_SUN5I_HSTIMER=y
+CONFIG_SUN6I_A31_CCU=y
+CONFIG_SUN6I_MSGBOX=y
+CONFIG_SUN6I_RTC_CCU=m
+CONFIG_SUN8I_A23_CCU=y
+CONFIG_SUN8I_A33_CCU=y
+CONFIG_SUN8I_A83T_CCU=y
+CONFIG_SUN8I_DE2_CCU=y
+CONFIG_SUN8I_H3_CCU=y
+CONFIG_SUN8I_R40_CCU=y
+CONFIG_SUN8I_R_CCU=y
+CONFIG_SUN8I_V3S_CCU=y
+CONFIG_SUN9I_A80_CCU=y
+CONFIG_SUNGEM_PHY=m
+CONFIG_SUNPLUS_WATCHDOG=m
+CONFIG_SUNXI_CCU=y
+CONFIG_SUNXI_RSB=y
+CONFIG_SUNXI_SRAM=y
+CONFIG_SURFACE_DTX=m
+CONFIG_SURFACE_HID=m
+CONFIG_SURFACE_KBD=m
+CONFIG_SURFACE_PLATFORM_PROFILE=m
+CONFIG_SURFACE_PLATFORMS=y
+CONFIG_SVC_I3C_MASTER=m
+CONFIG_SWAP=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SX9310=m
+CONFIG_SX9324=m
+CONFIG_SX9360=m
+CONFIG_SX9500=m
+CONFIG_SYNC_FILE=y
+CONFIG_SYNCLINK_CS=m
+CONFIG_SYNCLINK_GT=m
+CONFIG_SYNCLINKMP=m
+CONFIG_SYSCON_REBOOT_MODE=m
+CONFIG_SYSFB_SIMPLEFB=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y
+CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
+CONFIG_SYSTEM_BLACKLIST_KEYRING=y
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_T5403=m
+CONFIG_TABLET_SERIAL_WACOM4=m
+CONFIG_TABLET_USB_ACECAD=m
+CONFIG_TABLET_USB_AIPTEK=m
+CONFIG_TABLET_USB_GTCO=m
+CONFIG_TABLET_USB_HANWANG=m
+CONFIG_TABLET_USB_KBTAB=m
+CONFIG_TABLET_USB_PEGASUS=m
+CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y
+CONFIG_TAHVO_USB=m
+CONFIG_TANGO_IRQ=y
+CONFIG_TAP=m
+CONFIG_TARGET_CORE=m
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASKS_RCU=y
+CONFIG_TASKS_RUDE_RCU=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_XACCT=y
+CONFIG_TCG_TIS_CORE=m
+CONFIG_TCG_TIS_I2C_ATMEL=m
+CONFIG_TCG_TIS_I2C_CR50=m
+CONFIG_TCG_TIS_I2C_INFINEON=m
+CONFIG_TCG_TIS_I2C=m
+CONFIG_TCG_TIS_I2C_NUVOTON=m
+CONFIG_TCG_TIS=m
+CONFIG_TCG_TIS_SPI_CR50=y
+CONFIG_TCG_TIS_SPI=m
+CONFIG_TCG_TIS_ST33ZP24_I2C=m
+CONFIG_TCG_TIS_ST33ZP24=m
+CONFIG_TCG_TIS_ST33ZP24_SPI=m
+CONFIG_TCG_TPM=m
+CONFIG_TCG_VTPM_PROXY=m
+CONFIG_TCM_FC=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_PSCSI=m
+CONFIG_TCM_QLA2XXX=m
+CONFIG_TCM_USER2=m
+CONFIG_TCS3414=m
+CONFIG_TCS3472=m
+CONFIG_TEE=m
 CONFIG_TEGRA186_GPC_DMA=m
-# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set
-CONFIG_PWM_XILINX=m
-CONFIG_HTE=y
-# CONFIG_CACHEFILES_ONDEMAND is not set
-CONFIG_TRUSTED_KEYS_TPM=y
+CONFIG_TEGRA186_TIMER=y
+CONFIG_TEGRA210_ADMA=m
+CONFIG_TEGRA_ACONNECT=m
+CONFIG_TEGRA_AHB=y
+CONFIG_TEGRA_MC=y
+CONFIG_TERANETICS_PHY=m
+CONFIG_TEST_ASYNC_DRIVER_PROBE=m
+CONFIG_TEST_LOCKUP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=100
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_MMIO=m
+CONFIG_THERMAL_NETLINK=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_STATISTICS=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL=y
+CONFIG_TI_ADC081C=m
+CONFIG_TI_ADC0832=m
+CONFIG_TI_ADC084S021=m
+CONFIG_TI_ADC108S102=m
+CONFIG_TI_ADC12138=m
+CONFIG_TI_ADC128S052=m
+CONFIG_TI_ADC161S626=m
+CONFIG_TI_ADS1015=m
+CONFIG_TI_ADS1100=m
+CONFIG_TI_ADS1119=m
+CONFIG_TI_ADS1298=m
+CONFIG_TI_ADS131E08=m
+CONFIG_TI_ADS7138=m
+CONFIG_TI_ADS7924=m
+CONFIG_TI_ADS7950=m
+CONFIG_TI_ADS8344=m
+CONFIG_TI_AM335X_ADC=m
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TI_DAC082S085=m
+CONFIG_TI_DAC5571=m
+CONFIG_TI_DAC7311=m
+CONFIG_TI_DAC7612=m
+CONFIG_TI_DMA_CROSSBAR=y
+CONFIG_TI_ECAP_CAPTURE=m
+CONFIG_TI_EDMA=y
+CONFIG_TIFM_7XX1=m
+CONFIG_TIFM_CORE=m
+CONFIG_TI_LMP92064=m
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINYDRM_HX8357D=m
+CONFIG_TINYDRM_ILI9163=m
+CONFIG_TINYDRM_ILI9225=m
+CONFIG_TINYDRM_ILI9341=m
+CONFIG_TINYDRM_ILI9486=m
+CONFIG_TINYDRM_MI0283QT=m
+CONFIG_TINYDRM_REPAPER=m
+CONFIG_TINYDRM_ST7586=m
+CONFIG_TINYDRM_ST7735R=m
+CONFIG_TI_PRUSS_INTC=m
+CONFIG_TI_SOC_THERMAL=m
+CONFIG_TI_ST=m
+CONFIG_TI_SYSCON_CLK=y
+CONFIG_TI_SYSC=y
+CONFIG_TI_TLC4541=m
+CONFIG_TI_TMAG5273=m
+CONFIG_TI_TSC2046=m
+CONFIG_TMD_HERMES=m
+CONFIG_TMP006=m
+CONFIG_TMP007=m
+CONFIG_TMP117=m
+CONFIG_TORTURE_TEST=m
+CONFIG_TOUCHSCREEN_AD7877=m
+CONFIG_TOUCHSCREEN_AD7879_I2C=m
+CONFIG_TOUCHSCREEN_AD7879=m
+CONFIG_TOUCHSCREEN_AD7879_SPI=m
+CONFIG_TOUCHSCREEN_ADC=m
+CONFIG_TOUCHSCREEN_ADS7846=m
+CONFIG_TOUCHSCREEN_APPLE_Z2=m
+CONFIG_TOUCHSCREEN_AR1021_I2C=m
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
+CONFIG_TOUCHSCREEN_BU21013=m
+CONFIG_TOUCHSCREEN_BU21029=m
+CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
+CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
+CONFIG_TOUCHSCREEN_CY8CTMA140=m
+CONFIG_TOUCHSCREEN_CY8CTMG110=m
+CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
+CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
+CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
+CONFIG_TOUCHSCREEN_CYTTSP5=m
+CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
+CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
+CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
+CONFIG_TOUCHSCREEN_DA9052=m
+CONFIG_TOUCHSCREEN_DYNAPRO=m
+CONFIG_TOUCHSCREEN_EDT_FT5X06=m
+CONFIG_TOUCHSCREEN_EETI=m
+CONFIG_TOUCHSCREEN_EGALAX=m
+CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
+CONFIG_TOUCHSCREEN_EKTF2127=m
+CONFIG_TOUCHSCREEN_ELAN=m
+CONFIG_TOUCHSCREEN_ELO=m
+CONFIG_TOUCHSCREEN_EXC3000=m
+CONFIG_TOUCHSCREEN_FUJITSU=m
+CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C=m
+CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI=m
+CONFIG_TOUCHSCREEN_GOODIX=m
+CONFIG_TOUCHSCREEN_GUNZE=m
+CONFIG_TOUCHSCREEN_HAMPSHIRE=m
+CONFIG_TOUCHSCREEN_HIDEEP=m
+CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m
+CONFIG_TOUCHSCREEN_HIMAX_HX852X=m
+CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
+CONFIG_TOUCHSCREEN_HYNITRON_CST816X=m
+CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=m
+CONFIG_TOUCHSCREEN_ILI210X=m
+CONFIG_TOUCHSCREEN_ILITEK=m
+CONFIG_TOUCHSCREEN_IMAGIS=m
+CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
+CONFIG_TOUCHSCREEN_INEXIO=m
+CONFIG_TOUCHSCREEN_IQS5XX=m
+CONFIG_TOUCHSCREEN_IQS7211=m
+CONFIG_TOUCHSCREEN_MAX11801=m
+CONFIG_TOUCHSCREEN_MC13783=m
+CONFIG_TOUCHSCREEN_MCS5000=m
+CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
+CONFIG_TOUCHSCREEN_MK712=m
+CONFIG_TOUCHSCREEN_MMS114=m
+CONFIG_TOUCHSCREEN_MSG2638=m
+CONFIG_TOUCHSCREEN_MTOUCH=m
+CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS=m
+CONFIG_TOUCHSCREEN_PCAP=m
+CONFIG_TOUCHSCREEN_PENMOUNT=m
+CONFIG_TOUCHSCREEN_PIXCIR=m
+CONFIG_TOUCHSCREEN_PROPERTIES=y
+CONFIG_TOUCHSCREEN_RM_TS=m
+CONFIG_TOUCHSCREEN_ROHM_BU21023=m
+CONFIG_TOUCHSCREEN_S6SY761=m
+CONFIG_TOUCHSCREEN_SILEAD=m
+CONFIG_TOUCHSCREEN_SIS_I2C=m
+CONFIG_TOUCHSCREEN_ST1232=m
+CONFIG_TOUCHSCREEN_STMFTS=m
+CONFIG_TOUCHSCREEN_SUR40=m
+CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
+CONFIG_TOUCHSCREEN_SX8654=m
+CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m
+CONFIG_TOUCHSCREEN_TOUCHIT213=m
+CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
+CONFIG_TOUCHSCREEN_TOUCHWIN=m
+CONFIG_TOUCHSCREEN_TPS6507X=m
+CONFIG_TOUCHSCREEN_TSC2004=m
+CONFIG_TOUCHSCREEN_TSC2005=m
+CONFIG_TOUCHSCREEN_TSC2007_IIO=y
+CONFIG_TOUCHSCREEN_TSC2007=m
+CONFIG_TOUCHSCREEN_TSC200X_CORE=m
+CONFIG_TOUCHSCREEN_TSC_SERIO=m
+CONFIG_TOUCHSCREEN_UCB1400=m
+CONFIG_TOUCHSCREEN_USB_3M=y
+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
+CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
+CONFIG_TOUCHSCREEN_USB_E2I=y
+CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
+CONFIG_TOUCHSCREEN_USB_EGALAX=y
+CONFIG_TOUCHSCREEN_USB_ELO=y
+CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
+CONFIG_TOUCHSCREEN_USB_ETURBO=y
+CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
+CONFIG_TOUCHSCREEN_USB_GOTOP=y
+CONFIG_TOUCHSCREEN_USB_GUNZE=y
+CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
+CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
+CONFIG_TOUCHSCREEN_USB_ITM=y
+CONFIG_TOUCHSCREEN_USB_JASTEC=y
+CONFIG_TOUCHSCREEN_USB_NEXIO=y
+CONFIG_TOUCHSCREEN_USB_PANJIT=y
+CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
+CONFIG_TOUCHSCREEN_WACOM_I2C=m
+CONFIG_TOUCHSCREEN_WACOM_W8001=m
+CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
+CONFIG_TOUCHSCREEN_WM831X=m
+CONFIG_TOUCHSCREEN_WM9705=y
+CONFIG_TOUCHSCREEN_WM9712=y
+CONFIG_TOUCHSCREEN_WM9713=y
+CONFIG_TOUCHSCREEN_WM97XX=m
+CONFIG_TOUCHSCREEN_ZET6223=m
+CONFIG_TOUCHSCREEN_ZFORCE=m
+CONFIG_TOUCHSCREEN_ZINITIX=m
+CONFIG_TPL0102=m
+CONFIG_TPM_KEY_PARSER=m
+CONFIG_TPS6105X=m
+CONFIG_TPS65010=m
+CONFIG_TPS6507X=m
+CONFIG_TPS6594_ESM=m
+CONFIG_TPS6594_PFSM=m
+CONFIG_TRACEPOINTS=y
+CONFIG_TRACE_ROUTER=m
+CONFIG_TRACE_SINK=m
+CONFIG_TRACING=y
+CONFIG_TRIM_UNUSED_KSYMS=y
+CONFIG_TRUSTED_KEYS=m
 CONFIG_TRUSTED_KEYS_TEE=y
-CONFIG_CRYPTO_SM3_GENERIC=m
-CONFIG_CRYPTO_SM4_GENERIC=m
-# CONFIG_FIPS_SIGNATURE_SELFTEST is not set
-CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y
-# CONFIG_DEBUG_NET is not set
-CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
-# CONFIG_CGROUP_FAVOR_DYNMODS is not set
-CONFIG_ARCH_BCMBCA_CORTEXA7=y
-CONFIG_ARCH_BCMBCA_CORTEXA9=y
-CONFIG_ARCH_BCMBCA_BRAHMAB15=y
-CONFIG_ARCH_MSM8909=y
-CONFIG_ARCH_SUNPLUS=y
-CONFIG_SOC_SP7021=y
-# CONFIG_UNUSED_BOARD_FILES is not set
-# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
-CONFIG_DAMON_LRU_SORT=y
-CONFIG_NF_FLOW_TABLE_PROCFS=y
-CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
-CONFIG_PCI_EPF_VNTB=m
-CONFIG_ARM_SCMI_POWER_CONTROL=m
-CONFIG_BLK_DEV_UBLK=m
-CONFIG_NVME_AUTH=y
-CONFIG_NVME_TARGET_AUTH=y
+CONFIG_TRUSTED_KEYS_TPM=y
+CONFIG_TSL2583=m
+CONFIG_TSL2591=m
+CONFIG_TSL2772=m
+CONFIG_TSL4531=m
+CONFIG_TSNEP=m
+CONFIG_TSYS01=m
+CONFIG_TSYS02D=m
+CONFIG_TTPCI_EEPROM=m
+CONFIG_TUN=m
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_POWER=y
+CONFIG_TXGBE=m
+CONFIG_TYPEC_ANX7411=m
+CONFIG_TYPEC_DP_ALTMODE=m
+CONFIG_TYPEC_EXTCON=m
+CONFIG_TYPEC_FUSB302=m
+CONFIG_TYPEC_HD3SS3220=m
+CONFIG_TYPEC=m
+CONFIG_TYPEC_MT6360=m
+CONFIG_TYPEC_MUX_FSA4480=m
+CONFIG_TYPEC_MUX_GPIO_SBU=m
+CONFIG_TYPEC_MUX_IT5205=m
+CONFIG_TYPEC_MUX_NB7VPQ904M=m
+CONFIG_TYPEC_MUX_PI3USB30532=m
+CONFIG_TYPEC_MUX_PS883X=m
+CONFIG_TYPEC_MUX_PTN36502=m
+CONFIG_TYPEC_MUX_WCD939X_USBSS=m
+CONFIG_TYPEC_NVIDIA_ALTMODE=m
+CONFIG_TYPEC_QCOM_PMIC=m
+CONFIG_TYPEC_RT1711H=m
+CONFIG_TYPEC_RT1719=m
+CONFIG_TYPEC_STUSB160X=m
+CONFIG_TYPEC_TBT_ALTMODE=m
+CONFIG_TYPEC_TCPCI_HUSB311=m
+CONFIG_TYPEC_TCPCI=m
+CONFIG_TYPEC_TCPCI_MAXIM=m
+CONFIG_TYPEC_TCPCI_MT6370=m
+CONFIG_TYPEC_TCPM=m
+CONFIG_TYPEC_TPS6598X=m
+CONFIG_TYPEC_UCSI=m
+CONFIG_TYPEC_WUSB3801=m
+CONFIG_UACCE=m
+CONFIG_UCB1400_CORE=m
+CONFIG_UCSI_ACPI=m
+CONFIG_UCSI_CCG=m
+CONFIG_UCSI_PMIC_GLINK=m
+CONFIG_UCSI_STM32G0=m
+CONFIG_UID16=y
+CONFIG_UIO_AEC=m
+CONFIG_UIO_CIF=m
+CONFIG_UIO_DFL=m
+CONFIG_UIO_DMEM_GENIRQ=m
+CONFIG_UIO_MF624=m
+CONFIG_UIO_NETX=m
+CONFIG_UIO_PCI_GENERIC=m
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_UIO_PRUSS=m
+CONFIG_UIO_SERCOS3=m
+CONFIG_UKSM=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNICODE_UTF8_DATA=m
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNIPHIER_SYSTEM_BUS=y
+CONFIG_UNISYSSPAR=y
+CONFIG_UNUSED_KSYMS_WHITELIST=""
+CONFIG_UNWINDER_ARM=y
+CONFIG_UPROBE_EVENTS=y
+CONFIG_US5182D=m
+CONFIG_USB4=m
+CONFIG_USB4_NET=m
+CONFIG_USB_ACM=m
+CONFIG_USB_ADUTUX=m
+CONFIG_USB_AIRSPY=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AMD5536UDC=m
+CONFIG_USB_AN2720=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_APPLEDISPLAY=m
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_ASPEED_UDC=m
+CONFIG_USB_ATM=m
+CONFIG_USB_AUDIO=m
+CONFIG_USB_BDC_PCI=m
+CONFIG_USB_BDC_UDC=m
+CONFIG_USB_BELKIN=y
+CONFIG_USB_C67X00_HCD=m
+CONFIG_USB_CATC=m
+CONFIG_USB_CDC_COMPOSITE=m
+CONFIG_USB_CDC_PHONET=m
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_USB_CDNS3_IMX=m
+CONFIG_USB_CDNS3=m
+CONFIG_USB_CDNSP_GADGET=y
+CONFIG_USB_CDNSP_HOST=y
+CONFIG_USB_CDNSP_PCI=m
+CONFIG_USB_CDNS_SUPPORT=m
+CONFIG_USB_CHAOSKEY=m
+CONFIG_USB_CHIPIDEA_GENERIC=m
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_IMX=m
+CONFIG_USB_CHIPIDEA=m
+CONFIG_USB_CHIPIDEA_MSM=m
+CONFIG_USB_CHIPIDEA_NPCM=m
+CONFIG_USB_CHIPIDEA_PCI=m
+CONFIG_USB_CHIPIDEA_TEGRA=m
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_MIDI2=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_USB_CONFIGFS_F_PRINTER=y
+CONFIG_USB_CONFIGFS_F_TCM=y
+CONFIG_USB_CONFIGFS_F_UAC1=y
+CONFIG_USB_CONFIGFS_F_UAC2=y
+CONFIG_USB_CONFIGFS_F_UVC=y
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_PHONET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONN_GPIO=m
+CONFIG_USB_CXACRU=m
+CONFIG_USB_CYPRESS_CY7C63=m
+CONFIG_USB_CYTHERM=m
+CONFIG_USB_DSBR=m
+CONFIG_USB_DWC2_DUAL_ROLE=y
+CONFIG_USB_DWC2=m
+CONFIG_USB_DWC2_PCI=m
+CONFIG_USB_DWC3_DUAL_ROLE=y
+CONFIG_USB_DWC3_EXYNOS=m
+CONFIG_USB_DWC3_GENERIC_PLAT=m
+CONFIG_USB_DWC3_HAPS=m
+CONFIG_USB_DWC3_IMX8MP=m
+CONFIG_USB_DWC3_KEYSTONE=m
+CONFIG_USB_DWC3=m
+CONFIG_USB_DWC3_MESON_G12A=m
+CONFIG_USB_DWC3_OF_SIMPLE=m
+CONFIG_USB_DWC3_OMAP=m
+CONFIG_USB_DWC3_QCOM=m
+CONFIG_USB_DWC3_RTK=m
+CONFIG_USB_DWC3_ST=m
+CONFIG_USB_DWC3_XILINX=m
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_EG20T=m
+CONFIG_USB_EHCI_FSL=m
+CONFIG_USB_EHCI_HCD_AT91=m
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_EHCI_HCD_NPCM7XX=m
+CONFIG_USB_EHCI_HCD_OMAP=m
+CONFIG_USB_EHCI_HCD_ORION=m
+CONFIG_USB_EHCI_HCD_PLATFORM=m
+CONFIG_USB_EHCI_HCD_SPEAR=m
+CONFIG_USB_EHCI_MV=m
+CONFIG_USB_EHCI_PCI=m
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHSET_TEST_FIXTURE=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_EMI62=m
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_ETH_EEM=y
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_EZUSB_FX2=m
+CONFIG_USB_F_ACM=m
+CONFIG_USB_F_ECM=m
+CONFIG_USB_F_EEM=m
+CONFIG_USB_FEW_INIT_RETRIES=y
+CONFIG_USB_F_FS=m
+CONFIG_USB_F_HID=m
+CONFIG_USB_F_MASS_STORAGE=m
+CONFIG_USB_F_MIDI=m
+CONFIG_USB_F_NCM=m
+CONFIG_USB_F_OBEX=m
+CONFIG_USB_FOTG210_HCD=y
+CONFIG_USB_FOTG210_UDC=y
+CONFIG_USB_F_PHONET=m
+CONFIG_USB_F_PRINTER=m
+CONFIG_USB_F_RNDIS=m
+CONFIG_USB_F_SERIAL=m
+CONFIG_USB_F_SS_LB=m
+CONFIG_USB_F_SUBSET=m
+CONFIG_USB_F_TCM=m
+CONFIG_USB_FTDI_ELAN=m
+CONFIG_USB_F_UAC1=m
+CONFIG_USB_F_UAC2=m
+CONFIG_USB_FUNCTIONFS_ETH=y
+CONFIG_USB_FUNCTIONFS_GENERIC=y
+CONFIG_USB_FUNCTIONFS=m
+CONFIG_USB_FUNCTIONFS_RNDIS=y
+CONFIG_USB_F_UVC=m
+CONFIG_USB_G_ACM_MS=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_GADGET=m
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+CONFIG_USB_GADGET_TARGET=m
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_XILINX=m
+CONFIG_USB_G_HID=m
+CONFIG_USB_GL860=m
+CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_RNDIS=y
+CONFIG_USB_G_NCM=m
+CONFIG_USB_G_NOKIA=m
+CONFIG_USB_GOKU=m
+CONFIG_USB_GPIO_VBUS=m
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_GR_UDC=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_GSPCA_BENQ=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_CPIA1=m
+CONFIG_USB_GSPCA_DTCS033=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_JEILINJ=m
+CONFIG_USB_GSPCA_JL2005BCD=m
+CONFIG_USB_GSPCA_KINECT=m
+CONFIG_USB_GSPCA_KONICA=m
+CONFIG_USB_GSPCA=m
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_MR97310A=m
+CONFIG_USB_GSPCA_NW80X=m
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534_9=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7302=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SE401=m
+CONFIG_USB_GSPCA_SN9C2028=m
+CONFIG_USB_GSPCA_SN9C20X=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA1528=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+CONFIG_USB_GSPCA_SQ905C=m
+CONFIG_USB_GSPCA_SQ905=m
+CONFIG_USB_GSPCA_SQ930X=m
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_STK1135=m
+CONFIG_USB_GSPCA_STV0680=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TOPRO=m
+CONFIG_USB_GSPCA_TOUPTEK=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+CONFIG_USB_GSPCA_VICAM=m
+CONFIG_USB_GSPCA_XIRLINK_CIT=m
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_USB_G_WEBCAM=m
+CONFIG_USB_HACKRF=m
+CONFIG_USB_HCD_BCMA=m
+CONFIG_USB_HCD_SSB=m
+CONFIG_USB_HSIC_USB3503=m
+CONFIG_USB_HSIC_USB4604=m
+CONFIG_USB_HSO=m
+CONFIG_USB_HUB_USB251XB=m
+CONFIG_USB_IDMOUSE=m
+CONFIG_USB_IOWARRIOR=m
+CONFIG_USBIP_CORE=m
+CONFIG_USB_IPHETH=m
+CONFIG_USBIP_HOST=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_VHCI_HC_PORTS=8
+CONFIG_USBIP_VHCI_NR_HCS=1
+CONFIG_USBIP_VUDC=m
+CONFIG_USB_ISIGHTFW=m
+CONFIG_USB_ISP116X_HCD=m
+CONFIG_USB_ISP1301=m
+CONFIG_USB_ISP1760_DUAL_ROLE=y
+CONFIG_USB_ISP1760_HCD=y
+CONFIG_USB_ISP1760=m
+CONFIG_USB_ISP1761_UDC=y
+CONFIG_USB_KAWETH=m
+CONFIG_USB_KC2190=y
+CONFIG_USB_KEENE=m
+CONFIG_USB_LAN78XX=m
+CONFIG_USB_LCD=m
+CONFIG_USB_LD=m
+CONFIG_USB_LEDS_TRIGGER_USBPORT=m
+CONFIG_USB_LED_TRIG=y
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LGM_PHY=m
+CONFIG_USB_LIBCOMPOSITE=m
+CONFIG_USB_LINK_LAYER_TEST=m
+CONFIG_USB_LJCA=m
+CONFIG_USB=m
+CONFIG_USB_M5602=m
+CONFIG_USB_M66592=m
+CONFIG_USB_MA901=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_MAX3420_UDC=m
+CONFIG_USB_MAX3421_HCD=m
+CONFIG_USB_MDC800=m
+CONFIG_USB_MICROTEK=m
+CONFIG_USB_MIDI_GADGET=m
+CONFIG_USB_MON=m
+CONFIG_USB_MR800=m
+CONFIG_USB_MSI2500=m
+CONFIG_USB_MUSB_DUAL_ROLE=y
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MV_U3D=m
+CONFIG_USB_MV_UDC=m
+CONFIG_USB_NET2272_DMA=y
+CONFIG_USB_NET2272=m
+CONFIG_USB_NET2280=m
+CONFIG_USB_NET_AQC111=m
+CONFIG_USB_NET_AX88179_178A=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_MBIM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_NET_CH9200=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_DRIVERS=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_SR9700=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_OHCI_HCD_AT91=m
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_OHCI_HCD_OMAP3=m
+CONFIG_USB_OHCI_HCD_PCI=m
+CONFIG_USB_OHCI_HCD_PLATFORM=m
+CONFIG_USB_OHCI_HCD_SPEAR=m
+CONFIG_USB_OHCI_HCD_SSB=y
+CONFIG_USB_ONBOARD_HUB=m
+CONFIG_USB_OTG_FSM=m
+CONFIG_USB_OTG=y
+CONFIG_USB_OXU210HP_HCD=m
+CONFIG_USBPCWATCHDOG=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_PHY=y
+CONFIG_USB_PRINTER=m
+CONFIG_USB_PULSE8_CEC=m
+CONFIG_USB_PWC_INPUT_EVDEV=y
+CONFIG_USB_PWC=m
+CONFIG_USB_PXA27X=m
+CONFIG_USB_QCOM_EUD=m
+CONFIG_USB_R8A66597_HCD=m
+CONFIG_USB_R8A66597=m
+CONFIG_USB_RAINSHADOW_CEC=m
+CONFIG_USB_RAREMONO=m
+CONFIG_USB_RAW_GADGET=m
+CONFIG_USB_RENESAS_USBF=m
+CONFIG_USB_ROLE_SWITCH=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_RTL8153_ECM=m
+CONFIG_USB_RZV2M_USB3DRD=m
+CONFIG_USB_S2255=m
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_F8153X=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_METRO=m
+CONFIG_USB_SERIAL_MOS7715_PARPORT=y
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MXUPORT=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QT2=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SAFE=m
+CONFIG_USB_SERIAL_SAFE_PADDED=y
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SIMPLE=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_WISHBONE=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_XR=m
+CONFIG_USB_SERIAL_XSENS_MT=m
+CONFIG_USB_SEVSEG=m
+CONFIG_USB_SI470X=m
+CONFIG_USB_SI4713=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_SISUSBVGA_CON=y
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_SL811_CS=m
+CONFIG_USB_SL811_HCD=m
+CONFIG_USB_SNP_CORE=m
+CONFIG_USB_SNP_UDC_PLAT=m
+CONFIG_USB_SPEEDTOUCH=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_STORAGE_ALAUDA=m
+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_ENE_UB6250=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_KARMA=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_STORAGE_ONETOUCH=m
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STV06XX=m
+CONFIG_USB_TEGRA_PHY=m
+CONFIG_USB_TEST=m
+CONFIG_USB_TMC=m
+CONFIG_USB_TRANCEVIBRATOR=m
+CONFIG_USB_U132_HCD=m
+CONFIG_USB_UAS=m
+CONFIG_USB_U_AUDIO=m
+CONFIG_USB_UEAGLEATM=m
+CONFIG_USB_U_ETHER=m
+CONFIG_USB_UHCI_ASPEED=y
+CONFIG_USB_UHCI_HCD=m
+CONFIG_USB_UHCI_PLATFORM=y
+CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC=y
+CONFIG_USB_ULPI_BUS=m
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_USBNET=m
+CONFIG_USB_U_SERIAL=m
+CONFIG_USB_USS720=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VL600=m
+CONFIG_USB_WDM=m
+CONFIG_USB_XHCI_DBGCAP=y
+CONFIG_USB_XHCI_HCD=m
+CONFIG_USB_XHCI_PCI=m
+CONFIG_USB_XHCI_PCI_RENESAS=m
+CONFIG_USB_XHCI_PLATFORM=m
+CONFIG_USB_XHCI_RCAR=m
+CONFIG_USB_XHCI_RZV2M=y
+CONFIG_USB_XUSBATM=m
+CONFIG_USB_YUREX=m
+CONFIG_USB_ZD1201=m
+CONFIG_USB_ZERO_HNPTEST=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ZR364XX=m
+CONFIG_USE_OF=y
+CONFIG_USER_DECRYPTED_DATA=y
+CONFIG_USERFAULTFD=y
+CONFIG_U_SERIAL_CONSOLE=y
+CONFIG_USERIO=m
+CONFIG_USERMODE_DRIVER=y
+CONFIG_UX500_DEBUG_UART=2
+CONFIG_UX500_PM_DOMAIN=y
+CONFIG_UX500_SOC_DB8500=y
+CONFIG_UX500_SOC_ID=y
+CONFIG_UX500_WATCHDOG=y
+CONFIG_V4L2_FLASH_LED_CLASS=m
+CONFIG_V4L2_FWNODE=m
+CONFIG_V4L2_LOOPBACK=m
+CONFIG_V4L2_MEM2MEM_DEV=m
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VCNL3020=m
+CONFIG_VCNL4000=m
+CONFIG_VCNL4035=m
 CONFIG_VCPU_STALL_DETECTOR=m
-CONFIG_SCSI_BUSLOGIC=m
-CONFIG_SCSI_FLASHPOINT=y
-CONFIG_AHCI_BRCM=m
-CONFIG_AHCI_DWC=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
-CONFIG_NET_VENDOR_WANGXUN=y
-CONFIG_NET_VENDOR_ADI=y
-CONFIG_ADIN1110=m
-CONFIG_NGBE=m
-CONFIG_TXGBE=m
-CONFIG_NET_VENDOR_SUNPLUS=y
-CONFIG_SP7021_EMAC=m
-CONFIG_CAN_NETLINK=y
-CONFIG_CAN_CAN327=m
-CONFIG_CAN_ESD_USB=m
-CONFIG_HW_RANDOM_BCM2835=m
-CONFIG_TCG_TIS_I2C=m
-# CONFIG_RANDOM_TRUST_CPU is not set
-CONFIG_I2C_BRCMSTB=m
-CONFIG_I2C_NPCM=m
-CONFIG_I2C_RZV2M=m
-CONFIG_SPI_BCM63XX_HSSPI=m
-CONFIG_SPI_GXP=m
-CONFIG_SPI_MICROCHIP_CORE=m
-CONFIG_SPI_MICROCHIP_CORE_QSPI=m
-CONFIG_SPI_SUNPLUS_SP7021=m
-CONFIG_PINCTRL_MSM8909=m
-CONFIG_PINCTRL_SM6375=m
-CONFIG_PINCTRL_SUN20I_D1=y
-CONFIG_SENSORS_LT7182S=m
-CONFIG_SUNPLUS_WATCHDOG=m
+CONFIG_VDPA=m
+CONFIG_VDPA_USER=m
+CONFIG_VDSO=y
+CONFIG_VEML6030=m
+CONFIG_VEML6040=m
+CONFIG_VEML6046X00=m
+CONFIG_VEML6070=m
+CONFIG_VEML6075=m
+CONFIG_VETH=m
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_VFIO_AMBA=m
+CONFIG_VFIO_CONTAINER=y
+CONFIG_VFIO_DEVICE_CDEV=y
+CONFIG_VFIO_GROUP=y
+CONFIG_VFIO_IOMMU_TYPE1=m
+CONFIG_VFIO=m
+CONFIG_VFIO_MDEV_DEVICE=m
+CONFIG_VFIO_MDEV=m
+CONFIG_VFIO_PCI_INTX=y
+CONFIG_VFIO_PCI=m
+CONFIG_VFIO_PCI_MMAP=y
+CONFIG_VFIO_VIRQFD=y
+CONFIG_VFPv3=y
+CONFIG_VFP=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VGASTATE=m
+CONFIG_VHOST_IOTLB=m
+CONFIG_VHOST=m
+CONFIG_VHOST_RING=m
+CONFIG_VHOST_SCSI=m
+CONFIG_VHOST_VDPA=m
+CONFIG_VIDEO_AD5820=m
+CONFIG_VIDEO_AD9389B=m
+CONFIG_VIDEO_ADP1653=m
+CONFIG_VIDEO_ADV7170=m
+CONFIG_VIDEO_ADV7175=m
+CONFIG_VIDEO_ADV7180=m
+CONFIG_VIDEO_ADV7183=m
+CONFIG_VIDEO_ADV7343=m
+CONFIG_VIDEO_ADV7393=m
+CONFIG_VIDEO_ADV748X=m
+CONFIG_VIDEO_AK7375=m
+CONFIG_VIDEO_AK881X=m
+CONFIG_VIDEO_ALLEGRO_DVT=m
+CONFIG_VIDEO_ALVIUM_CSI2=m
+CONFIG_VIDEO_AMPHION_VPU=m
+CONFIG_VIDEO_APTINA_PLL=m
+CONFIG_VIDEO_AR0521=m
+CONFIG_VIDEO_ASPEED=m
+CONFIG_VIDEO_AU0828=m
+CONFIG_VIDEO_AU0828_RC=y
+CONFIG_VIDEO_AU0828_V4L2=y
+CONFIG_VIDEO_BT819=m
+CONFIG_VIDEO_BT848=m
+CONFIG_VIDEO_BT856=m
+CONFIG_VIDEO_BT866=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_DMA_CONTIG=m
+CONFIG_VIDEOBUF2_DMA_SG=m
+CONFIG_VIDEOBUF2_DVB=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_V4L2=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEOBUF_DMA_SG=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_VMALLOC=m
+CONFIG_VIDEO_CADENCE_CSI2RX=m
+CONFIG_VIDEO_CADENCE_CSI2TX=m
+CONFIG_VIDEO_CADENCE=y
+CONFIG_VIDEO_CAFE_CCIC=m
+CONFIG_VIDEO_CAMERA_SENSOR=y
+CONFIG_VIDEO_CCS=m
+CONFIG_VIDEO_CPIA2=m
+CONFIG_VIDEO_CS3308=m
+CONFIG_VIDEO_CS5345=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_CX18_ALSA=m
+CONFIG_VIDEO_CX18=m
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX2341X=m
+CONFIG_VIDEO_CX23885=m
+CONFIG_VIDEO_CX25821_ALSA=m
+CONFIG_VIDEO_CX25821=m
+CONFIG_VIDEO_CX25840=m
+CONFIG_VIDEO_CX88_ALSA=m
+CONFIG_VIDEO_CX88_BLACKBIRD=m
+CONFIG_VIDEO_CX88_DVB=m
+CONFIG_VIDEO_CX88_ENABLE_VP3054=y
+CONFIG_VIDEO_CX88=m
+CONFIG_VIDEO_CX88_MPEG=m
+CONFIG_VIDEO_CX88_VP3054=m
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_DS90UB913=m
+CONFIG_VIDEO_DS90UB953=m
+CONFIG_VIDEO_DS90UB960=m
+CONFIG_VIDEO_DT3155=m
+CONFIG_VIDEO_DW100=m
+CONFIG_VIDEO_DW9714=m
+CONFIG_VIDEO_DW9719=m
+CONFIG_VIDEO_DW9768=m
+CONFIG_VIDEO_DW9807_VCM=m
+CONFIG_VIDEO_E5010_JPEG_ENC=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_RC=m
+CONFIG_VIDEO_EM28XX_V4L2=m
+CONFIG_VIDEO_ET8EK8=m
+CONFIG_VIDEO_FB_IVTV=m
+CONFIG_VIDEO_GC0308=m
+CONFIG_VIDEO_GC0310=m
+CONFIG_VIDEO_GC05A2=m
+CONFIG_VIDEO_GC08A3=m
+CONFIG_VIDEO_GC2145=m
+CONFIG_VIDEO_GO7007_LOADER=m
+CONFIG_VIDEO_GO7007=m
+CONFIG_VIDEO_GO7007_USB=m
+CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
+CONFIG_VIDEO_GS1662=m
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_HEXIUM_GEMINI=m
+CONFIG_VIDEO_HEXIUM_ORION=m
+CONFIG_VIDEO_HI556=m
+CONFIG_VIDEO_HI846=m
+CONFIG_VIDEO_HI847=m
+CONFIG_VIDEO_I2C=m
+CONFIG_VIDEO_IMX208=m
+CONFIG_VIDEO_IMX214=m
+CONFIG_VIDEO_IMX219=m
+CONFIG_VIDEO_IMX258=m
+CONFIG_VIDEO_IMX274=m
+CONFIG_VIDEO_IMX283=m
+CONFIG_VIDEO_IMX290=m
+CONFIG_VIDEO_IMX296=m
+CONFIG_VIDEO_IMX319=m
+CONFIG_VIDEO_IMX334=m
+CONFIG_VIDEO_IMX335=m
+CONFIG_VIDEO_IMX355=m
+CONFIG_VIDEO_IMX412=m
+CONFIG_VIDEO_IMX415=m
+CONFIG_VIDEO_IMX7_CSI=m
+CONFIG_VIDEO_IMX8_ISI=m
+CONFIG_VIDEO_IMX8_ISI_M2M=y
+CONFIG_VIDEO_IMX8_JPEG=m
+CONFIG_VIDEO_IMX8MQ_MIPI_CSI2=m
+CONFIG_VIDEO_IMX_MIPI_CSIS=m
+CONFIG_VIDEO_IR_I2C=m
+CONFIG_VIDEO_ISL7998X=m
+CONFIG_VIDEO_IVTV_ALSA=m
+CONFIG_VIDEO_IVTV=m
+CONFIG_VIDEO_KS0127=m
+CONFIG_VIDEO_LM3560=m
+CONFIG_VIDEO_LM3646=m
+CONFIG_VIDEO_LT6911UXE=m
+CONFIG_VIDEO_M52790=m
+CONFIG_VIDEO_M5MOLS=m
+CONFIG_VIDEO_MAX9286=m
+CONFIG_VIDEO_MAX96712=m
+CONFIG_VIDEO_MAX96714=m
+CONFIG_VIDEO_MAX96717=m
+CONFIG_VIDEO_MEDIATEK_MDP3=m
+CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
+CONFIG_VIDEO_MESON_GE2D=m
+CONFIG_VIDEO_MGB4=m
+CONFIG_VIDEO_MICROCHIP_ISC=m
+CONFIG_VIDEO_MICROCHIP_XISC=m
+CONFIG_VIDEO_ML86V7667=m
+CONFIG_VIDEO_MMP_CAMERA=m
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_MT9M001=m
+CONFIG_VIDEO_MT9M032=m
+CONFIG_VIDEO_MT9M111=m
+CONFIG_VIDEO_MT9M114=m
+CONFIG_VIDEO_MT9P031=m
+CONFIG_VIDEO_MT9T001=m
+CONFIG_VIDEO_MT9T112=m
+CONFIG_VIDEO_MT9V011=m
+CONFIG_VIDEO_MT9V032=m
+CONFIG_VIDEO_MT9V111=m
+CONFIG_VIDEO_MUX=m
+CONFIG_VIDEO_MXB=m
+CONFIG_VIDEO_NOON010PC30=m
+CONFIG_VIDEO_NPCM_VCD_ECE=m
+CONFIG_VIDEO_OG01A1B=m
+CONFIG_VIDEO_OG0VE1B=m
+CONFIG_VIDEO_OV01A10=m
+CONFIG_VIDEO_OV02A10=m
+CONFIG_VIDEO_OV08D10=m
+CONFIG_VIDEO_OV08X40=m
+CONFIG_VIDEO_OV13858=m
+CONFIG_VIDEO_OV13B10=m
+CONFIG_VIDEO_OV2640=m
+CONFIG_VIDEO_OV2659=m
+CONFIG_VIDEO_OV2680=m
+CONFIG_VIDEO_OV2685=m
+CONFIG_VIDEO_OV2735=m
+CONFIG_VIDEO_OV4689=m
+CONFIG_VIDEO_OV5640=m
+CONFIG_VIDEO_OV5645=m
+CONFIG_VIDEO_OV5647=m
+CONFIG_VIDEO_OV5648=m
+CONFIG_VIDEO_OV5670=m
+CONFIG_VIDEO_OV5675=m
+CONFIG_VIDEO_OV5693=m
+CONFIG_VIDEO_OV5695=m
+CONFIG_VIDEO_OV6211=m
+CONFIG_VIDEO_OV64A40=m
+CONFIG_VIDEO_OV6650=m
+CONFIG_VIDEO_OV7251=m
+CONFIG_VIDEO_OV7640=m
+CONFIG_VIDEO_OV7670=m
+CONFIG_VIDEO_OV772X=m
+CONFIG_VIDEO_OV7740=m
+CONFIG_VIDEO_OV8856=m
+CONFIG_VIDEO_OV8858=m
+CONFIG_VIDEO_OV8865=m
+CONFIG_VIDEO_OV9282=m
+CONFIG_VIDEO_OV9640=m
+CONFIG_VIDEO_OV9650=m
+CONFIG_VIDEO_PVRUSB2_DVB=y
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_QCOM_IRIS=m
+CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m
+CONFIG_VIDEO_RCAR_ISP=m
+CONFIG_VIDEO_RDACM20=m
+CONFIG_VIDEO_RDACM21=m
+CONFIG_VIDEO_RJ54N1=m
+CONFIG_VIDEO_RZG2L_CRU=m
+CONFIG_VIDEO_RZG2L_CSI2=m
+CONFIG_VIDEO_S5C73M3=m
+CONFIG_VIDEO_S5K4ECGX=m
+CONFIG_VIDEO_S5K5BAF=m
+CONFIG_VIDEO_S5K6A3=m
+CONFIG_VIDEO_S5K6AA=m
+CONFIG_VIDEO_SAA6588=m
+CONFIG_VIDEO_SAA6752HS=m
+CONFIG_VIDEO_SAA7110=m
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_SAA7127=m
+CONFIG_VIDEO_SAA7134_ALSA=m
+CONFIG_VIDEO_SAA7134_DVB=m
+CONFIG_VIDEO_SAA7134_GO7007=m
+CONFIG_VIDEO_SAA7134=m
+CONFIG_VIDEO_SAA7134_RC=y
+CONFIG_VIDEO_SAA7146=m
+CONFIG_VIDEO_SAA7146_VV=m
+CONFIG_VIDEO_SAA7164=m
+CONFIG_VIDEO_SAA717X=m
+CONFIG_VIDEO_SAA7185=m
+CONFIG_VIDEO_SMIAPP=m
+CONFIG_VIDEO_SMIAPP_PLL=m
+CONFIG_VIDEO_SOLO6X10=m
+CONFIG_VIDEO_SONY_BTF_MPX=m
+CONFIG_VIDEO_SR030PC30=m
+CONFIG_VIDEO_STK1160_COMMON=m
+CONFIG_VIDEO_STK1160=m
+CONFIG_VIDEO_STKWEBCAM=m
+CONFIG_VIDEO_STM32_CSI=m
+CONFIG_VIDEO_STM32_DCMIPP=m
+CONFIG_VIDEO_STM32_DMA2D=m
+CONFIG_VIDEO_ST_MIPID02=m
+CONFIG_VIDEO_ST_VGXY61=m
 CONFIG_VIDEO_SUN6I_MIPI_CSI2=m
 CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m
-CONFIG_VIDEO_AR0521=m
-CONFIG_DRM_PANEL_EBBG_FT8719=m
-CONFIG_DRM_TI_DLPC3433=m
-CONFIG_DRM_IMX8QM_LDB=m
-# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set
-CONFIG_RCU_NOCB_CPU_DEFAULT_ALL=y
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-CONFIG_A64FX_DIAG=y
-# CONFIG_RV is not set
-# Ethernet Power Sourcing Equipment Support
-CONFIG_PSE_CONTROLLER=y
-CONFIG_PSE_REGULATOR=m
-CONFIG_STAGING_MEDIA_DEPRECATED=y
-# CONFIG_FORCE_NR_CPUS is not set
-# CONFIG_DEBUG_MAPLE_TREE is not set
-CONFIG_QCOM_TSENS=m
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_KERNEL_ZSTD=y
+CONFIG_VIDEO_SYNOPSYS_HDMIRX_LOAD_DEFAULT_EDID=y
+CONFIG_VIDEO_SYNOPSYS_HDMIRX=m
+CONFIG_VIDEO_TC358743_CEC=y
+CONFIG_VIDEO_TC358743=m
+CONFIG_VIDEO_TC358746=m
+CONFIG_VIDEO_TDA1997X=m
+CONFIG_VIDEO_TDA7432=m
+CONFIG_VIDEO_TDA9840=m
+CONFIG_VIDEO_TEA6415C=m
+CONFIG_VIDEO_TEA6420=m
+CONFIG_VIDEO_TEGRA_VDE=m
+CONFIG_VIDEO_THP7312=m
+CONFIG_VIDEO_THS7303=m
+CONFIG_VIDEO_THS8200=m
+CONFIG_VIDEO_TI_J721E_CSI2RX=m
+CONFIG_VIDEO_TLV320AIC23B=m
+CONFIG_VIDEO_TM6000_ALSA=m
+CONFIG_VIDEO_TM6000_DVB=m
+CONFIG_VIDEO_TM6000=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_TVAUDIO=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TVP514X=m
+CONFIG_VIDEO_TVP5150=m
+CONFIG_VIDEO_TVP7002=m
+CONFIG_VIDEO_TW2804=m
+CONFIG_VIDEO_TW5864=m
+CONFIG_VIDEO_TW686X=m
+CONFIG_VIDEO_TW68=m
+CONFIG_VIDEO_TW9900=m
+CONFIG_VIDEO_TW9903=m
+CONFIG_VIDEO_TW9906=m
+CONFIG_VIDEO_TW9910=m
+CONFIG_VIDEO_UDA1342=m
+CONFIG_VIDEO_UPD64031A=m
+CONFIG_VIDEO_UPD64083=m
+CONFIG_VIDEO_USBTV=m
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_VIDEO_VGXY61=m
+CONFIG_VIDEO_VP27SMPX=m
+CONFIG_VIDEO_VPX3220=m
+CONFIG_VIDEO_VS6624=m
+CONFIG_VIDEO_WM8739=m
+CONFIG_VIDEO_WM8775=m
+CONFIG_VIDEO_XILINX_CSI2RXSS=m
+CONFIG_VIDEO_XILINX=m
+CONFIG_VIDEO_XILINX_VTC=m
+CONFIG_VIDEO_ZORAN_AVS6EYES=y
+CONFIG_VIDEO_ZORAN_BUZ=y
+CONFIG_VIDEO_ZORAN_DC10=y
+CONFIG_VIDEO_ZORAN_DC30=y
+CONFIG_VIDEO_ZORAN_LML33R10=y
+CONFIG_VIDEO_ZORAN_LML33=y
+CONFIG_VIDEO_ZORAN=m
+CONFIG_VIDEO_ZORAN_ZR36060=y
+CONFIG_VIPERBOARD_ADC=m
+CONFIG_VIRT_DRIVERS=y
+CONFIG_VIRTIO_BALLOON=m
+CONFIG_VIRTIO_BLK=m
+CONFIG_VIRTIO_CONSOLE=m
+CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
+CONFIG_VIRTIO_INPUT=m
+CONFIG_VIRTIO=m
+CONFIG_VIRTIO_MEM=m
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_VIRTIO_MMIO=m
+CONFIG_VIRTIO_NET=m
+CONFIG_VIRTIO_PCI=m
+CONFIG_VIRTIO_VDPA=m
+CONFIG_VIRT_WIFI=m
+CONFIG_VITESSE_PHY=m
+CONFIG_VL53L0X_I2C=m
+CONFIG_VL6180=m
+CONFIG_VMAP_STACK=y
+CONFIG_VME_BUS=y
+CONFIG_VME_FAKE=m
+CONFIG_VME_TSI148=m
+CONFIG_VME_USER=m
+CONFIG_VMGENID=m
+CONFIG_VMIVME_7805=m
+CONFIG_VMSPLIT_3G=y
+CONFIG_VMXNET3=m
+CONFIG_VOP_BUS=m
+CONFIG_VOP=m
+CONFIG_VP_VDPA=m
+CONFIG_VSOCKMON=m
+CONFIG_VT6655=m
+CONFIG_VT6656=m
+CONFIG_VT8500_TIMER=y
+CONFIG_VXLAN=m
+CONFIG_VZ89X=m
+CONFIG_W1_CON=y
+CONFIG_W1=m
+CONFIG_W1_MASTER_AMD_AXI=m
+CONFIG_W1_MASTER_DS1WM=m
+CONFIG_W1_MASTER_DS2482=m
+CONFIG_W1_MASTER_DS2490=m
+CONFIG_W1_MASTER_GPIO=m
+CONFIG_W1_MASTER_SGI=m
+CONFIG_W1_MASTER_UART=m
+CONFIG_W1_SLAVE_DS2405=m
+CONFIG_W1_SLAVE_DS2406=m
+CONFIG_W1_SLAVE_DS2408=m
+CONFIG_W1_SLAVE_DS2408_READBACK=y
+CONFIG_W1_SLAVE_DS2413=m
+CONFIG_W1_SLAVE_DS2423=m
+CONFIG_W1_SLAVE_DS2430=m
+CONFIG_W1_SLAVE_DS2431=m
+CONFIG_W1_SLAVE_DS2433=m
+CONFIG_W1_SLAVE_DS2438=m
+CONFIG_W1_SLAVE_DS250X=m
+CONFIG_W1_SLAVE_DS2780=m
+CONFIG_W1_SLAVE_DS2781=m
+CONFIG_W1_SLAVE_DS2805=m
+CONFIG_W1_SLAVE_DS28E04=m
+CONFIG_W1_SLAVE_DS28E17=m
+CONFIG_W1_SLAVE_SMEM=m
+CONFIG_W1_SLAVE_THERM=m
+CONFIG_WANT_DEV_COREDUMP=y
+CONFIG_WANXL=m
+CONFIG_WAN=y
+CONFIG_WATCHDOG_CORE=m
+CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=0
+CONFIG_WATCHDOG=y
+CONFIG_WCN36XX=m
+CONFIG_WDTPCI=m
+CONFIG_WFX=m
+CONFIG_WIL6210_DEBUGFS=y
+CONFIG_WIL6210_ISR_COR=y
+CONFIG_WIL6210=m
+CONFIG_WIL6210_TRACING=y
+CONFIG_WILC1000=m
+CONFIG_WILC1000_SDIO=m
+CONFIG_WILC1000_SPI=m
+CONFIG_WILINK_PLATFORM_DATA=y
+CONFIG_WIMAX_DEBUG_LEVEL=8
+CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8
+CONFIG_WIMAX_I2400M=m
+CONFIG_WIMAX_I2400M_USB=m
+CONFIG_WIMAX=m
+CONFIG_WIREGUARD=m
+CONFIG_WIRELESS_EXT=y
+CONFIG_WL1251=m
+CONFIG_WL1251_SDIO=m
+CONFIG_WL1251_SPI=m
+CONFIG_WL12XX=m
+CONFIG_WL18XX=m
+CONFIG_WLAN_VENDOR_BES=y
+CONFIG_WLAN_VENDOR_CISCO=y
+CONFIG_WLCORE=m
+CONFIG_WLCORE_SDIO=m
+CONFIG_WM831X_BACKUP=m
+CONFIG_WM831X_POWER=m
+CONFIG_WM831X_WATCHDOG=m
+CONFIG_WPCM450_SOC=m
+CONFIG_WWAN_CORE=m
+CONFIG_WWAN_HWSIM=m
+CONFIG_WWAN=y
+CONFIG_X25_ASY=m
+CONFIG_X9250=m
+CONFIG_XILINX_AMS=m
+CONFIG_XILINX_GMII2RGMII=m
+CONFIG_XILINX_INTC=y
+CONFIG_XILINX_PR_DECOUPLER=m
+CONFIG_XILINX_SDFEC=m
+CONFIG_XILINX_WATCHDOG=m
+CONFIG_XILINX_XADC=m
+CONFIG_XILINX_XDMA=m
+CONFIG_XILINX_ZYNQMP_DPDMA=m
+CONFIG_XILLYBUS=m
+CONFIG_XILLYBUS_OF=m
+CONFIG_XILLYBUS_PCIE=m
+CONFIG_XILLYUSB=m
+CONFIG_XOR_BLOCKS=m
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_MICROLZMA=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_YAMAHA_YAS530=m
+CONFIG_YAM=m
+CONFIG_YENTA_ENE_TUNE=y
+CONFIG_YENTA=m
+CONFIG_YENTA_O2=y
+CONFIG_YENTA_RICOH=y
+CONFIG_YENTA_TI=y
+CONFIG_YENTA_TOSHIBA=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZD1211RW=m
+CONFIG_ZIIRAVE_WATCHDOG=m
+CONFIG_ZL3073X_SPI=m
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZONE_DMA=y
+CONFIG_ZOPT2201=m
+CONFIG_ZPA2326_I2C=m
+CONFIG_ZPA2326=m
+CONFIG_ZPA2326_SPI=m
+CONFIG_ZRAM_MULTI_COMP=y
+CONFIG_ZRAM_TRACK_ENTRY_ACTIME=y
+CONFIG_ZRAM_WRITEBACK=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZX_TDM=m
+CONFIG_NEXUS=m
diff --git a/arm64-omv-defconfig b/arm64-omv-defconfig
new file mode 100644
index 0000000..c530510
--- /dev/null
+++ b/arm64-omv-defconfig
@@ -0,0 +1,6878 @@
+CONFIG_64BIT=y
+CONFIG_842_COMPRESS=y
+CONFIG_842_DECOMPRESS=y
+CONFIG_88PM886_GPADC=m
+CONFIG_ABP060MG=m
+CONFIG_AC97_BUS=m
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_AGDI=y
+CONFIG_ACPI_ALS=m
+CONFIG_ACPI_APEI_EINJ=m
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_PCIEAER=y
+CONFIG_ACPI_APEI_SEA=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APMT=y
+CONFIG_ACPI_BATTERY=y
+CONFIG_ACPI_BGRT=y
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_CCA_REQUIRED=y
+CONFIG_ACPI_CONFIGFS=m
+CONFIG_ACPI_CONTAINER=y
+CONFIG_ACPI_CPPC_CPUFREQ_FIE=y
+CONFIG_ACPI_CPPC_CPUFREQ=m
+CONFIG_ACPI_CPPC_LIB=y
+CONFIG_ACPI_CUSTOM_DSDT_FILE=""
+CONFIG_ACPI_CUSTOM_METHOD=m
+CONFIG_ACPI_DOCK=y
+CONFIG_ACPI_EC_DEBUGFS=m
+CONFIG_ACPI_FAN=y
+CONFIG_ACPI_FFH=y
+CONFIG_ACPI_FPDT=y
+CONFIG_ACPI_GENERIC_GSI=y
+CONFIG_ACPI_GTDT=y
+CONFIG_ACPI_HED=y
+CONFIG_ACPI_HMAT=y
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_ACPI_IORT=y
+CONFIG_ACPI_IPMI=m
+CONFIG_ACPI_MCFG=y
+CONFIG_ACPI_MDIO=y
+CONFIG_ACPI_NFIT=m
+CONFIG_ACPI_NUMA=y
+CONFIG_ACPI_PCC=y
+CONFIG_ACPI_PCI_SLOT=y
+CONFIG_ACPI_PFRUT=m
+CONFIG_ACPI_PLATFORM_PROFILE=m
+CONFIG_ACPI_PPTT=y
+CONFIG_ACPI_PRMT=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
+CONFIG_ACPI_SPCR_TABLE=y
+CONFIG_ACPI_TABLE_LIB=y
+CONFIG_ACPI_TABLE_UPGRADE=y
+CONFIG_ACPI_THERMAL=y
+CONFIG_ACPI_VIDEO=m
+CONFIG_ACPI_VIOT=y
+CONFIG_ACPI=y
+CONFIG_AD2S1200=m
+CONFIG_AD2S1210=m
+CONFIG_AD2S90=m
+CONFIG_AD3552R=m
+CONFIG_AD4000=m
+CONFIG_AD4030=m
+CONFIG_AD4080=m
+CONFIG_AD4130=m
+CONFIG_AD4170_4=m
+CONFIG_AD4695=m
+CONFIG_AD4851=m
+CONFIG_AD5064=m
+CONFIG_AD5110=m
+CONFIG_AD5272=m
+CONFIG_AD5360=m
+CONFIG_AD5380=m
+CONFIG_AD5421=m
+CONFIG_AD5446=m
+CONFIG_AD5449=m
+CONFIG_AD5504=m
+CONFIG_AD5592R_BASE=m
+CONFIG_AD5592R=m
+CONFIG_AD5593R=m
+CONFIG_AD5624R_SPI=m
+CONFIG_AD5686=m
+CONFIG_AD5686_SPI=m
+CONFIG_AD5696_I2C=m
+CONFIG_AD5755=m
+CONFIG_AD5758=m
+CONFIG_AD5761=m
+CONFIG_AD5764=m
+CONFIG_AD5766=m
+CONFIG_AD5770R=m
+CONFIG_AD5791=m
+CONFIG_AD5933=m
+CONFIG_AD7091R5=m
+CONFIG_AD7091R8=m
+CONFIG_AD7124=m
+CONFIG_AD7150=m
+CONFIG_AD7173=m
+CONFIG_AD7191=m
+CONFIG_AD7192=m
+CONFIG_AD7266=m
+CONFIG_AD7280=m
+CONFIG_AD7291=m
+CONFIG_AD7292=m
+CONFIG_AD7293=m
+CONFIG_AD7298=m
+CONFIG_AD7303=m
+CONFIG_AD7380=m
+CONFIG_AD7405=m
+CONFIG_AD74115=m
+CONFIG_AD74413R=m
+CONFIG_AD7476=m
+CONFIG_AD7606_IFACE_PARALLEL=m
+CONFIG_AD7606_IFACE_SPI=m
+CONFIG_AD7606=m
+CONFIG_AD7746=m
+CONFIG_AD7766=m
+CONFIG_AD7768_1=m
+CONFIG_AD7780=m
+CONFIG_AD7791=m
+CONFIG_AD7793=m
+CONFIG_AD7816=m
+CONFIG_AD7887=m
+CONFIG_AD7923=m
+CONFIG_AD7944=m
+CONFIG_AD7949=m
+CONFIG_AD799X=m
+CONFIG_AD8366=m
+CONFIG_AD8801=m
+CONFIG_AD9467=m
+CONFIG_AD9523=m
+CONFIG_AD9739A=m
+CONFIG_AD9832=m
+CONFIG_AD9834=m
+CONFIG_ADA4250=m
+CONFIG_ADE9000=m
+CONFIG_ADF4350=m
+CONFIG_ADF4371=m
+CONFIG_ADF4377=m
+CONFIG_ADI_AXI_ADC=m
+CONFIG_ADI_AXI_DAC=m
+CONFIG_ADI_I3C_MASTER=m
+CONFIG_ADIN1100_PHY=m
+CONFIG_ADIS16080=m
+CONFIG_ADIS16130=m
+CONFIG_ADIS16136=m
+CONFIG_ADIS16201=m
+CONFIG_ADIS16203=m
+CONFIG_ADIS16209=m
+CONFIG_ADIS16240=m
+CONFIG_ADIS16260=m
+CONFIG_ADIS16400=m
+CONFIG_ADIS16460=m
+CONFIG_ADIS16475=m
+CONFIG_ADIS16480=m
+CONFIG_ADIS16550=m
+CONFIG_ADJD_S311=m
+CONFIG_ADM8211=m
+CONFIG_ADMFM2000=m
+CONFIG_ADMV1013=m
+CONFIG_ADMV1014=m
+CONFIG_ADMV4420=m
+CONFIG_ADMV8818=m
+CONFIG_ADRF6780=m
+CONFIG_AD_SIGMA_DELTA=m
+CONFIG_ADT7316_I2C=m
+CONFIG_ADT7316=m
+CONFIG_ADT7316_SPI=m
+CONFIG_ADUX1020=m
+CONFIG_ADXL313_I2C=m
+CONFIG_ADXL313=m
+CONFIG_ADXL313_SPI=m
+CONFIG_ADXL345_I2C=m
+CONFIG_ADXL345=m
+CONFIG_ADXL345_SPI=m
+CONFIG_ADXL355_I2C=m
+CONFIG_ADXL355=m
+CONFIG_ADXL355_SPI=m
+CONFIG_ADXL367_I2C=m
+CONFIG_ADXL367=m
+CONFIG_ADXL367_SPI=m
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372=m
+CONFIG_ADXL372_SPI=m
+CONFIG_ADXL380_I2C=m
+CONFIG_ADXL380_SPI=m
+CONFIG_ADXRS290=m
+CONFIG_ADXRS450=m
+CONFIG_AF8133J=m
+CONFIG_AFE4403=m
+CONFIG_AFE4404=m
+CONFIG_AF_KCM=m
+CONFIG_AF_RXRPC=m
+CONFIG_AHCI_BRCM=m
+CONFIG_AHCI_CEVA=m
+CONFIG_AHCI_DWC=m
+CONFIG_AHCI_IMX=m
+CONFIG_AHCI_MTK=m
+CONFIG_AHCI_MVEBU=m
+CONFIG_AHCI_QORIQ=m
+CONFIG_AHCI_SUNXI=m
+CONFIG_AHCI_TEGRA=m
+CONFIG_AIC79XX_CMDS_PER_DEVICE=32
+CONFIG_AIC79XX_DEBUG_ENABLE=y
+CONFIG_AIC79XX_DEBUG_MASK=0
+CONFIG_AIC79XX_REG_PRETTY_PRINT=y
+CONFIG_AIC79XX_RESET_DELAY_MS=5000
+CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
+CONFIG_AIC7XXX_DEBUG_ENABLE=y
+CONFIG_AIC7XXX_DEBUG_MASK=0
+CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
+CONFIG_AIC7XXX_RESET_DELAY_MS=5000
+CONFIG_AIROHA_CPU_PM_DOMAIN=m
+CONFIG_AIRO=m
+CONFIG_AK09911=m
+CONFIG_AK8974=m
+CONFIG_AK8975=m
+CONFIG_AL3000A=m
+CONFIG_AL3010=m
+CONFIG_AL3320A=m
+CONFIG_ALIBABA_UNCORE_DRW_PMU=m
+CONFIG_ALPINE_MSI=y
+CONFIG_ALTERA_MBOX=m
+CONFIG_ALTERA_STAPL=m
+CONFIG_AM2315=m
+CONFIG_AMD_QDMA=m
+CONFIG_AMLOGIC_THERMAL=y
+CONFIG_AMPERE_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m
+CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y
+CONFIG_AMPERE_ERRATUM_AC04_CPU_23=y
+CONFIG_AMT=m
+CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
+CONFIG_ANDROID_BINDERFS=y
+CONFIG_ANDROID_BINDER_IPC=m
+CONFIG_AOSONG_AGS02MA=m
+CONFIG_APDS9160=m
+CONFIG_APDS9300=m
+CONFIG_APDS9306=m
+CONFIG_APDS9960=m
+CONFIG_APERTURE_HELPERS=y
+CONFIG_APPLE_ADMAC=m
+CONFIG_APPLE_DART=m
+CONFIG_APPLE_M1_CPU_PMU=y
+CONFIG_APPLE_MAILBOX=m
+CONFIG_APPLE_PMGR_PWRSTATE=y
+CONFIG_APPLE_RTKIT=m
+CONFIG_APPLE_SART=m
+CONFIG_APPLICOM=m
+CONFIG_AQUANTIA_PHY=m
+CONFIG_AR5523=m
+CONFIG_ARCH_ACTIONS=y
+CONFIG_ARCH_AIROHA=y
+CONFIG_ARCH_ALPINE=y
+CONFIG_ARCH_APPLE=y
+CONFIG_ARCH_ARTPEC=y
+CONFIG_ARCH_AXIADO=y
+CONFIG_ARCH_BCM2835=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_ARCH_BCM_IPROC=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BERLIN=y
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_BITMAIN=y
+CONFIG_ARCH_BLAIZE=y
+CONFIG_ARCH_BRCMSTB=y
+CONFIG_ARCH_CIX=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
+CONFIG_ARCH_ENABLE_THP_MIGRATION=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_FORCE_MAX_ORDER=10
+CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
+CONFIG_ARCH_HAS_DEBUG_WX=y
+CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_ARCH_HAS_KEEPINITRD=y
+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
+CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
+CONFIG_ARCH_HAS_PMEM_API=y
+CONFIG_ARCH_HAS_PTE_DEVMAP=y
+CONFIG_ARCH_HAS_RELR=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_ARCH_HAS_SUBPAGE_FAULTS=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
+CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
+CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y
+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
+CONFIG_ARCH_HAS_ZONE_DMA_SET=y
+CONFIG_ARCH_HAVE_ELF_PROT=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
+CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y
+CONFIG_ARCH_HIBERNATION_HEADER=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_HISI=y
+CONFIG_ARCH_INTEL_SOCFPGA=y
+CONFIG_ARCH_K3=y
+CONFIG_ARCH_KEEMBAY=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_LAN969X=y
+CONFIG_ARCH_LAYERSCAPE=y
+CONFIG_ARCH_LG1K=y
+CONFIG_ARCH_MA35=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_ARCH_MESON=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=33
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_MMP=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_NPCM=y
+CONFIG_ARCH_NXP=y
+CONFIG_ARCH_PENSANDO=y
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_QCOM_RESERVE_SMEM=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_R8A774A1=y
+CONFIG_ARCH_R8A774B1=y
+CONFIG_ARCH_R8A774C0=y
+CONFIG_ARCH_R8A774E1=y
+CONFIG_ARCH_R8A77951=y
+CONFIG_ARCH_R8A77960=y
+CONFIG_ARCH_R8A77961=y
+CONFIG_ARCH_R8A77965=y
+CONFIG_ARCH_R8A77970=y
+CONFIG_ARCH_R8A77980=y
+CONFIG_ARCH_R8A77990=y
+CONFIG_ARCH_R8A77995=y
+CONFIG_ARCH_R8A779A0=y
+CONFIG_ARCH_R8A779F0=y
+CONFIG_ARCH_R8A779G0=y
+CONFIG_ARCH_R8A779H0=y
+CONFIG_ARCH_R8A78000=y
+CONFIG_ARCH_R9A07G043=y
+CONFIG_ARCH_R9A07G044=y
+CONFIG_ARCH_R9A07G054=y
+CONFIG_ARCH_R9A08G045=y
+CONFIG_ARCH_R9A09G011=y
+CONFIG_ARCH_R9A09G047=y
+CONFIG_ARCH_R9A09G056=y
+CONFIG_ARCH_R9A09G057=y
+CONFIG_ARCH_R9A09G077=y
+CONFIG_ARCH_R9A09G087=y
+CONFIG_ARCH_RCAR_GEN3=y
+CONFIG_ARCH_REALTEK=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_RZG2L=y
+CONFIG_ARCH_S32=y
+CONFIG_ARCH_SEATTLE=y
+CONFIG_ARCH_SOPHGO=y
+CONFIG_ARCH_SPARX5=y
+CONFIG_ARCH_SPRD=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_STM32=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_SUPPORTS_ACPI=y
+CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_ARCH_SUPPORTS_INT128=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
+CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
+CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y
+CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
+CONFIG_ARCH_SYNQUACER=y
+CONFIG_ARCH_TEGRA_132_SOC=y
+CONFIG_ARCH_TEGRA_186_SOC=y
+CONFIG_ARCH_TEGRA_194_SOC=y
+CONFIG_ARCH_TEGRA_210_SOC=y
+CONFIG_ARCH_TEGRA_234_SOC=y
+CONFIG_ARCH_TEGRA_241_SOC=y
+CONFIG_ARCH_TEGRA_264_SOC=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_ARCH_TESLA_FSD=y
+CONFIG_ARCH_THUNDER2=y
+CONFIG_ARCH_THUNDER=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_USE_GNU_PROPERTY=y
+CONFIG_ARCH_USE_MEMREMAP_PROT=y
+CONFIG_ARCH_USE_MEMTEST=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
+CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
+CONFIG_ARCH_USES_PG_ARCH_X=y
+CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
+CONFIG_ARCH_VISCONTI=y
+CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
+CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ARCH_XGENE=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_ARCNET_1051=m
+CONFIG_ARCNET_1201=m
+CONFIG_ARCNET_CAP=m
+CONFIG_ARCNET_COM20020=m
+CONFIG_ARCNET_COM20020_PCI=m
+CONFIG_ARCNET_COM90xxIO=m
+CONFIG_ARCNET_COM90xx=m
+CONFIG_ARCNET=m
+CONFIG_ARCNET_RAW=m
+CONFIG_ARCNET_RIM_I=m
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_ACPI_PARKING_PROTOCOL=y
+CONFIG_ARM64_AMU_EXTN=y
+CONFIG_ARM64_AS_HAS_MTE=y
+CONFIG_ARM64_BRBE=y
+CONFIG_ARM64_BTI_KERNEL=y
+CONFIG_ARM64_BTI=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_CONT_PMD_SHIFT=4
+CONFIG_ARM64_CONT_PTE_SHIFT=4
+CONFIG_ARM64_CONTPTE=y
+CONFIG_ARM64_E0PD=y
+CONFIG_ARM64_EPAN=y
+CONFIG_ARM64_ERRATUM_1024718=y
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_1319367=y
+CONFIG_ARM64_ERRATUM_1418040=y
+CONFIG_ARM64_ERRATUM_1463225=y
+CONFIG_ARM64_ERRATUM_1508412=y
+CONFIG_ARM64_ERRATUM_1530923=y
+CONFIG_ARM64_ERRATUM_1542419=y
+CONFIG_ARM64_ERRATUM_1742098=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2441007=y
+CONFIG_ARM64_ERRATUM_2441009=y
+CONFIG_ARM64_ERRATUM_2457168=y
+CONFIG_ARM64_ERRATUM_2645198=y
+CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_ERRATUM_2966298=y
+CONFIG_ARM64_ERRATUM_3117295=y
+CONFIG_ARM64_ERRATUM_3194386=y
+CONFIG_ARM64_ERRATUM_3312417=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_834220=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_845719=y
+CONFIG_ARM64_ERRATUM_858921=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_LSE_ATOMICS=y
+CONFIG_ARM64_MTE=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PAN=y
+CONFIG_ARM64_PLATFORM_DEVICES=y
+CONFIG_ARM64_PMEM=y
+CONFIG_ARM64_POE=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_SME=y
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_USE_LSE_ATOMICS=y
+CONFIG_ARM64_VA_BITS=48
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+CONFIG_ARM64=y
+CONFIG_ARMADA_37XX_CLK=y
+CONFIG_ARMADA_37XX_RWTM_MBOX=m
+CONFIG_ARMADA_AP806_SYSCON=y
+CONFIG_ARMADA_AP_CP_HELPER=y
+CONFIG_ARMADA_CP110_SYSCON=y
+CONFIG_ARMADA_THERMAL=m
+CONFIG_ARM_AIROHA_SOC_CPUFREQ=m
+CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPLE_SOC_CPUFREQ=m
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
+CONFIG_ARM_BRCMSTB_AVS_CPUFREQ=y
+CONFIG_ARM_CCI_PMU=m
+CONFIG_ARM_CCI=y
+CONFIG_ARM_CMN=m
+CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m
+CONFIG_ARM_DMA350=m
+CONFIG_ARM_DMC620_PMU=m
+CONFIG_ARM_FFA_SMCCC=y
+CONFIG_ARM_FFA_TRANSPORT=m
+CONFIG_ARM_GIC_MAX_NR=1
+CONFIG_ARM_GIC_PM=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HISI_UNCORE_DEVFREQ=m
+CONFIG_ARM_IMX8M_DDRC_DEVFREQ=m
+CONFIG_ARM_IMX_CPUFREQ_DT=y
+CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=m
+CONFIG_ARM_MEDIATEK_CPUFREQ_HW=m
+CONFIG_ARM_MEDIATEK_CPUFREQ=m
+CONFIG_ARM_MHU_V2=y
+CONFIG_ARM_MHU_V3=y
+CONFIG_ARM_MHU=y
+CONFIG_ARM_NI=m
+CONFIG_ARM_PKVM_GUEST=y
+CONFIG_ARM_PMU_ACPI=y
+CONFIG_ARM_PMUV3=y
+CONFIG_ARM_PMU=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_QCOM_CPUFREQ_HW=m
+CONFIG_ARM_QCOM_CPUFREQ_NVMEM=m
+CONFIG_ARM_RASPBERRYPI_CPUFREQ=m
+CONFIG_ARM_RK3399_DMC_DEVFREQ=y
+CONFIG_ARM_SBSA_WATCHDOG=m
+CONFIG_ARM_SCMI_CPUFREQ=m
+CONFIG_ARM_SCMI_HAVE_MSG=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_PERF_DOMAIN=m
+CONFIG_ARM_SCMI_POWERCAP=m
+CONFIG_ARM_SCMI_POWER_CONTROL=m
+CONFIG_ARM_SCMI_POWER_DOMAIN=m
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SCMI_QUIRKS=y
+CONFIG_ARM_SCMI_RAW_MODE_SUPPORT_COEX=y
+CONFIG_ARM_SCMI_RAW_MODE_SUPPORT=y
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE=y
+CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y
+CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y
+CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SMCCC_SOC_ID=y
+CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
+CONFIG_ARM_SMMU_MMU_500_CPRE_ERRATA=y
+CONFIG_ARM_SMMU_QCOM=y
+CONFIG_ARM_SMMU_V3_SVA=y
+CONFIG_ARM_SMMU_V3=y
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SP805_WATCHDOG=m
+CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
+CONFIG_ARM_TEGRA124_CPUFREQ=y
+CONFIG_ARM_TEGRA186_CPUFREQ=y
+CONFIG_ARM_TEGRA194_CPUFREQ=y
+CONFIG_ARM_TEGRA20_CPUFREQ=y
+CONFIG_ARM_TI_CPUFREQ=y
+CONFIG_ARM_TIMER_SP804=y
+CONFIG_ARM_TSTEE=m
+CONFIG_ARMV8_DEPRECATED=y
+CONFIG_AS3935=m
+CONFIG_AS73211=m
+CONFIG_AS_HAS_ARMV8_2=y
+CONFIG_AS_HAS_ARMV8_3=y
+CONFIG_AS_HAS_ARMV8_4=y
+CONFIG_AS_HAS_ARMV8_5=y
+CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
+CONFIG_AS_HAS_LDAPR=y
+CONFIG_AS_HAS_LSE_ATOMICS=y
+CONFIG_AS_HAS_SHA3=y
+CONFIG_AS_IS_LLVM=y
+CONFIG_ASN1_ENCODER=m
+CONFIG_AST2700_MBOX=m
+CONFIG_AS_VERSION=160006
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_ASYNC_TX_DMA=y
+CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
+CONFIG_ASYNC_XOR=m
+CONFIG_AT76C50X_USB=m
+CONFIG_AT803X_PHY=m
+CONFIG_ATA_ACPI=y
+CONFIG_ATA=m
+CONFIG_ATA_OVER_ETH=m
+CONFIG_ATH10K_CE=y
+CONFIG_ATH10K=m
+CONFIG_ATH10K_PCI=m
+CONFIG_ATH10K_SDIO=m
+CONFIG_ATH10K_SNOC=m
+CONFIG_ATH10K_USB=m
+CONFIG_ATH11K_AHB=m
+CONFIG_ATH11K=m
+CONFIG_ATH11K_PCI=m
+CONFIG_ATH12K=m
+CONFIG_ATH5K=m
+CONFIG_ATH5K_PCI=y
+CONFIG_ATH6KL=m
+CONFIG_ATH6KL_SDIO=m
+CONFIG_ATH6KL_USB=m
+CONFIG_ATH9K_AHB=y
+CONFIG_ATH9K_BTCOEX_SUPPORT=y
+CONFIG_ATH9K_CHANNEL_CONTEXT=y
+CONFIG_ATH9K_COMMON=m
+CONFIG_ATH9K_DYNACK=y
+CONFIG_ATH9K_HTC=m
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_HWRNG=y
+CONFIG_ATH9K=m
+CONFIG_ATH9K_PCI_NO_EEPROM=m
+CONFIG_ATH9K_PCI=y
+CONFIG_ATH9K_PCOEM=y
+CONFIG_ATH9K_RFKILL=y
+CONFIG_ATH9K_WOW=y
+CONFIG_ATH_COMMON=m
+CONFIG_ATLAS_EZO_SENSOR=m
+CONFIG_ATLAS_PH_SENSOR=m
+CONFIG_ATMEL=m
+CONFIG_AT_XDMAC=m
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_AUXDISPLAY=y
+CONFIG_AUXILIARY_BUS=y
+CONFIG_AW96103=m
+CONFIG_AX88796B_PHY=m
+CONFIG_AXP20X_ADC=m
+CONFIG_AXP20X_POWER=m
+CONFIG_AXP288_ADC=m
+CONFIG_B43_BCMA_PIO=y
+CONFIG_B43_BCMA=y
+CONFIG_B43_BUSES_BCMA_AND_SSB=y
+CONFIG_B43_HWRNG=y
+CONFIG_B43_LEDS=y
+CONFIG_B43=m
+CONFIG_B43_PCI_AUTOSELECT=y
+CONFIG_B43_PCICORE_AUTOSELECT=y
+CONFIG_B43_PHY_G=y
+CONFIG_B43_PHY_HT=y
+CONFIG_B43_PHY_LP=y
+CONFIG_B43_PHY_N=y
+CONFIG_B43_PIO=y
+CONFIG_B43_SDIO=y
+CONFIG_B43_SSB=y
+CONFIG_BACKLIGHT_ADP8860=m
+CONFIG_BACKLIGHT_ADP8870=m
+CONFIG_BACKLIGHT_APPLE_DWI=m
+CONFIG_BACKLIGHT_ARCXCNN=m
+CONFIG_BACKLIGHT_BD6107=m
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GPIO=m
+CONFIG_BACKLIGHT_KTD253=m
+CONFIG_BACKLIGHT_KTD2801=m
+CONFIG_BACKLIGHT_KTZ8866=m
+CONFIG_BACKLIGHT_LED=m
+CONFIG_BACKLIGHT_LM3630A=m
+CONFIG_BACKLIGHT_LM3639=m
+CONFIG_BACKLIGHT_LP855X=m
+CONFIG_BACKLIGHT_LV5207LP=m
+CONFIG_BACKLIGHT_MP3309C=m
+CONFIG_BACKLIGHT_MT6370=m
+CONFIG_BACKLIGHT_PWM=m
+CONFIG_BACKLIGHT_QCOM_WLED=m
+CONFIG_BACKLIGHT_RT4831=m
+CONFIG_BATTERY_AXP20X=m
+CONFIG_BATTERY_BQ27XXX_HDQ=m
+CONFIG_BATTERY_BQ27XXX_I2C=m
+CONFIG_BATTERY_BQ27XXX=y
+CONFIG_BATTERY_GOLDFISH=m
+CONFIG_BATTERY_LENOVO_YOGA_C630=m
+CONFIG_BATTERY_OLPC=m
+CONFIG_BATTERY_PM8916_BMS_VM=m
+CONFIG_BATTERY_QCOM_BATTMGR=m
+CONFIG_BATTERY_RT5033=m
+CONFIG_BATTERY_SAMSUNG_SDI=y
+CONFIG_BATTERY_SURFACE=m
+CONFIG_BATTERY_UG3105=m
+CONFIG_BCACHE_ASYNC_REGISTRATION=y
+CONFIG_BCACHE=m
+CONFIG_BCH=y
+CONFIG_BCM2711_THERMAL=m
+CONFIG_BCM2712_MIP=m
+CONFIG_BCM2835_MBOX=y
+CONFIG_BCM2835_POWER=y
+CONFIG_BCM2835_THERMAL=m
+CONFIG_BCM2835_VCHIQ=m
+CONFIG_BCM2835_VCHIQ_MMAL=m
+CONFIG_BCM2835_WDT=y
+CONFIG_BCM7038_L1_IRQ=y
+CONFIG_BCM7038_WDT=m
+CONFIG_BCM7120_L2_IRQ=m
+CONFIG_BCM74110_MAILBOX=m
+CONFIG_BCM7XXX_PHY=y
+CONFIG_BCM84881_PHY=y
+CONFIG_BCMA_BLOCKIO=y
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
+CONFIG_BCMA_DRIVER_GPIO=y
+CONFIG_BCMA_DRIVER_PCI=y
+CONFIG_BCMA_HOST_PCI_POSSIBLE=y
+CONFIG_BCMA_HOST_PCI=y
+CONFIG_BCMA_HOST_SOC=y
+CONFIG_BCMA=m
+CONFIG_BCMA_SFLASH=y
+CONFIG_BCM_FLEXRM_MBOX=m
+CONFIG_BCM_IPROC_ADC=m
+CONFIG_BCM_NET_PHYLIB=y
+CONFIG_BCM_NS_THERMAL=m
+CONFIG_BCM_PDC_MBOX=m
+CONFIG_BCM_PMB=y
+CONFIG_BCM_SR_THERMAL=y
+CONFIG_BCM_VIDEOCORE=y
+CONFIG_BCM_VK=m
+CONFIG_BCM_VK_TTY=y
+CONFIG_BD79703=m
+CONFIG_BD957XMUF_WATCHDOG=m
+CONFIG_BD96801_WATCHDOG=m
+CONFIG_BE2ISCSI=m
+CONFIG_BERLIN2_ADC=m
+CONFIG_BFQ_GROUP_IOSCHED=y
+CONFIG_BH1745=m
+CONFIG_BH1750=m
+CONFIG_BH1780=m
+CONFIG_BINFMT_MISC=m
+CONFIG_BLK_CGROUP_PUNT_BIO=y
+CONFIG_BLK_CGROUP_RWSTAT=y
+CONFIG_BLK_DEV_3W_XXXX_RAID=m
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_DM=m
+CONFIG_BLK_DEV_DRBD=m
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
+CONFIG_BLK_DEV_PMEM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RNBD_CLIENT=m
+CONFIG_BLK_DEV_RNBD_SERVER=m
+CONFIG_BLK_DEV_RNBD=y
+CONFIG_BLK_DEV_SD=m
+CONFIG_BLK_DEV_SR=m
+CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BLK_DEV_UBLK=m
+CONFIG_BLK_DEV_ZONED_LOOP=m
+CONFIG_BLK_ICQ=y
+CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
+CONFIG_BLK_INLINE_ENCRYPTION=y
+CONFIG_BLK_MQ_STACKING=y
+CONFIG_BLOCK_HOLDER_DEPRECATED=y
+CONFIG_BMA180=m
+CONFIG_BMA220=m
+CONFIG_BMA400_I2C=m
+CONFIG_BMA400=m
+CONFIG_BMA400_SPI=m
+CONFIG_BMC150_ACCEL_I2C=m
+CONFIG_BMC150_ACCEL=m
+CONFIG_BMC150_ACCEL_SPI=m
+CONFIG_BMC150_MAGN_I2C=m
+CONFIG_BMC150_MAGN=m
+CONFIG_BMC150_MAGN_SPI=m
+CONFIG_BME680_I2C=m
+CONFIG_BME680=m
+CONFIG_BME680_SPI=m
+CONFIG_BMG160_I2C=m
+CONFIG_BMG160=m
+CONFIG_BMG160_SPI=m
+CONFIG_BMI088_ACCEL=m
+CONFIG_BMI088_ACCEL_SPI=m
+CONFIG_BMI160_I2C=m
+CONFIG_BMI160=m
+CONFIG_BMI160_SPI=m
+CONFIG_BMI323_I2C=m
+CONFIG_BMI323_SPI=m
+CONFIG_BMP280_I2C=m
+CONFIG_BMP280=m
+CONFIG_BMP280_SPI=m
+CONFIG_BONDING=m
+CONFIG_BOOT_CONFIG=y
+CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_BOSCH_BNO055_I2C=m
+CONFIG_BOSCH_BNO055=m
+CONFIG_BOSCH_BNO055_SERIAL=m
+CONFIG_BPF_JIT_DEFAULT_ON=y
+CONFIG_BRCMFMAC=m
+CONFIG_BRCMFMAC_PCIE=y
+CONFIG_BRCMFMAC_PROTO_BCDC=y
+CONFIG_BRCMFMAC_PROTO_MSGBUF=y
+CONFIG_BRCMFMAC_SDIO=y
+CONFIG_BRCMFMAC_USB=y
+CONFIG_BRCMSMAC_LEDS=y
+CONFIG_BRCMSMAC=m
+CONFIG_BRCMSTB_DPFE=y
+CONFIG_BRCMSTB_L2_IRQ=y
+CONFIG_BRCMSTB_MEMC=m
+CONFIG_BRCMSTB_THERMAL=m
+CONFIG_BRCM_USB_PINMAP=m
+CONFIG_BRCMUTIL=m
+CONFIG_BROADCOM_PHY=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BTREE=y
+CONFIG_BTT=y
+CONFIG_BUILD_SALT="eb4452dac310a2674e96f56d25c5c12ecea5f237"
+CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
+CONFIG_CAN_BCM=m
+CONFIG_CAN_GW=m
+CONFIG_CAN_ISOTP=m
+CONFIG_CAN_J1939=m
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CARL9170_HWRNG=y
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170=m
+CONFIG_CARL9170_WPC=y
+CONFIG_CAVIUM_CPT=m
+CONFIG_CAVIUM_ERRATUM_22375=y
+CONFIG_CAVIUM_ERRATUM_23144=y
+CONFIG_CAVIUM_ERRATUM_23154=y
+CONFIG_CAVIUM_ERRATUM_27456=y
+CONFIG_CAVIUM_ERRATUM_30115=y
+CONFIG_CAVIUM_TX2_ERRATUM_219=y
+CONFIG_CC10001_ADC=m
+CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
+CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
+CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
+CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
+CONFIG_CC_HAS_INT128=y
+CONFIG_CC_HAS_KASAN_SW_TAGS=y
+CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
+CONFIG_CC_HAS_RANDSTRUCT=y
+CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
+CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
+CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough"
+CONFIG_CC_IS_CLANG=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+CONFIG_CCS811=m
+CONFIG_CC_VERSION_TEXT="OpenMandriva 16.0.6-3 clang version 16.0.6 (/builddir/build/BUILD/llvm-project-16.0.6.src/clang 2d21ec58bba683586362941f17e8179860b49206)"
+CONFIG_CDNS_I3C_MASTER=m
+CONFIG_CDROM=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDX_BUS=y
+CONFIG_CDX_CONTROLLER=m
+CONFIG_CEC_CORE=y
+CONFIG_CEC_GPIO=m
+CONFIG_CEC_NOTIFIER=y
+CONFIG_CEC_NXP_TDA9950=m
+CONFIG_CEC_PIN=y
+CONFIG_CEC_STM32=m
+CONFIG_CEPH_LIB=m
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_CFG80211=m
+CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
+CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
+CONFIG_CFG80211_WEXT_EXPORT=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_CFI_ICALL_NORMALIZE_INTEGERS=y
+CONFIG_CHARGER_ADP5061=m
+CONFIG_CHARGER_AXP20X=m
+CONFIG_CHARGER_BQ24735=m
+CONFIG_CHARGER_BQ2515X=m
+CONFIG_CHARGER_BQ256XX=m
+CONFIG_CHARGER_BQ25980=m
+CONFIG_CHARGER_CROS_CONTROL=m
+CONFIG_CHARGER_CROS_PCHG=m
+CONFIG_CHARGER_CROS_USBPD=m
+CONFIG_CHARGER_LTC4162L=m
+CONFIG_CHARGER_MAX77976=m
+CONFIG_CHARGER_MT6370=m
+CONFIG_CHARGER_PM8916_LBC=m
+CONFIG_CHARGER_QCOM_SMB2=m
+CONFIG_CHARGER_QCOM_SMBB=m
+CONFIG_CHARGER_RK817=m
+CONFIG_CHARGER_RT9467=m
+CONFIG_CHARGER_RT9471=m
+CONFIG_CHARGER_SURFACE=m
+CONFIG_CHARLCD_BL_FLASH=y
+CONFIG_CHARLCD=m
+CONFIG_CHECK_SIGNATURE=y
+CONFIG_CHR_DEV_SCH=m
+CONFIG_CHR_DEV_SG=m
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHROMEOS_ACPI=m
+CONFIG_CHROMEOS_PRIVACY_SCREEN=m
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CIX_MBOX=y
+CONFIG_CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
+CONFIG_CLANG_VERSION=160006
+CONFIG_CLK_ACTIONS=y
+CONFIG_CLK_BCM2711_DVP=m
+CONFIG_CLK_BCM2835=y
+CONFIG_CLK_BCM_63XX=y
+CONFIG_CLK_BCM_NS2=y
+CONFIG_CLK_BCM_SR=y
+CONFIG_CLK_GFM_LPASS_SM8250=m
+CONFIG_CLK_GLYMUR_DISPCC=m
+CONFIG_CLK_GLYMUR_GCC=m
+CONFIG_CLK_GLYMUR_TCSRCC=m
+CONFIG_CLK_ICST=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MQ=y
+CONFIG_CLK_IMX8QXP=y
+CONFIG_CLK_IMX8ULP=m
+CONFIG_CLK_IMX93=m
+CONFIG_CLK_IMX95_BLK_CTL=m
+CONFIG_CLK_INTEL_SOCFPGA64=y
+CONFIG_CLK_INTEL_SOCFPGA=y
+CONFIG_CLK_LS1028A_PLLDIG=y
+CONFIG_CLK_MA35D1=y
+CONFIG_CLK_OWL_S500=y
+CONFIG_CLK_OWL_S700=y
+CONFIG_CLK_OWL_S900=y
+CONFIG_CLK_PX30=y
+CONFIG_CLK_QCM2290_GPUCC=m
+CONFIG_CLK_QORIQ=y
+CONFIG_CLK_R8A774A1=y
+CONFIG_CLK_R8A774B1=y
+CONFIG_CLK_R8A774C0=y
+CONFIG_CLK_R8A774E1=y
+CONFIG_CLK_R8A7795=y
+CONFIG_CLK_R8A77960=y
+CONFIG_CLK_R8A77961=y
+CONFIG_CLK_R8A77965=y
+CONFIG_CLK_R8A77970=y
+CONFIG_CLK_R8A77980=y
+CONFIG_CLK_R8A77990=y
+CONFIG_CLK_R8A77995=y
+CONFIG_CLK_R8A779A0=y
+CONFIG_CLK_R8A779F0=y
+CONFIG_CLK_R8A779G0=y
+CONFIG_CLK_R8A779H0=y
+CONFIG_CLK_R9A07G043=y
+CONFIG_CLK_R9A07G044=y
+CONFIG_CLK_R9A07G054=y
+CONFIG_CLK_R9A09G011=y
+CONFIG_CLK_RASPBERRYPI=m
+CONFIG_CLK_RCAR_CPG_LIB=y
+CONFIG_CLK_RCAR_GEN3_CPG=y
+CONFIG_CLK_RCAR_GEN4_CPG=y
+CONFIG_CLK_RENESAS_CPG_MSSR=y
+CONFIG_CLK_RENESAS_DIV6=y
+CONFIG_CLK_RENESAS=y
+CONFIG_CLK_RK3308=y
+CONFIG_CLK_RK3328=y
+CONFIG_CLK_RK3368=y
+CONFIG_CLK_RK3399=y
+CONFIG_CLK_RK3528=y
+CONFIG_CLK_RK3562=y
+CONFIG_CLK_RK3568=y
+CONFIG_CLK_RK3576=y
+CONFIG_CLK_RK3588=y
+CONFIG_CLK_RZG2L=y
+CONFIG_CLK_SOPHGO_CV1800=m
+CONFIG_CLK_SOPHGO_SG2042_CLKGEN=m
+CONFIG_CLK_SOPHGO_SG2042_PLL=m
+CONFIG_CLK_SOPHGO_SG2042_RPGATE=m
+CONFIG_CLK_SOPHGO_SG2044_CLKGEN=m
+CONFIG_CLK_SOPHGO_SG2044=m
+CONFIG_CLK_SOPHGO_SG2044_PLL=m
+CONFIG_CLK_SOPHGO_SG2044_RPGATE=m
+CONFIG_CLK_SP810=y
+CONFIG_CLKSRC_EXYNOS_MCT=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_STM32_LP=y
+CONFIG_CLK_TEGRA_BPMP=y
+CONFIG_CLK_UNIPHIER=y
+CONFIG_CLK_VEXPRESS_OSC=y
+CONFIG_CLK_X1E80100_CAMCC=m
+CONFIG_CLK_X1E80100_DISPCC=m
+CONFIG_CLK_X1E80100_GCC=m
+CONFIG_CLK_X1E80100_GPUCC=m
+CONFIG_CLK_X1E80100_TCSRCC=m
+CONFIG_CLK_X1P42100_GPUCC=m
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CM32181=m
+CONFIG_CM3232=m
+CONFIG_CM3323=m
+CONFIG_CM3605=m
+CONFIG_CM36651=m
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+CONFIG_CMA_SIZE_MBYTES=256
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+CONFIG_CMA_SYSFS=y
+CONFIG_CMA=y
+CONFIG_CMDLINE=""
+CONFIG_COMMON_CLK_A1_PERIPHERALS=m
+CONFIG_COMMON_CLK_A1_PLL=m
+CONFIG_COMMON_CLK_APPLE_NCO=m
+CONFIG_COMMON_CLK_AXG=y
+CONFIG_COMMON_CLK_AXI_CLKGEN=m
+CONFIG_COMMON_CLK_BM1880=y
+CONFIG_COMMON_CLK_C3_PERIPHERALS=m
+CONFIG_COMMON_CLK_C3_PLL=m
+CONFIG_COMMON_CLK_CS2000_CP=y
+CONFIG_COMMON_CLK_EN7523=y
+CONFIG_COMMON_CLK_FSL_FLEXSPI=m
+CONFIG_COMMON_CLK_G12A=y
+CONFIG_COMMON_CLK_GXBB=y
+CONFIG_COMMON_CLK_HI3516CV300=y
+CONFIG_COMMON_CLK_HI3519=y
+CONFIG_COMMON_CLK_HI3559A=y
+CONFIG_COMMON_CLK_HI3660=y
+CONFIG_COMMON_CLK_HI3670=y
+CONFIG_COMMON_CLK_HI3798CV200=y
+CONFIG_COMMON_CLK_HI6220=y
+CONFIG_COMMON_CLK_HI655X=y
+CONFIG_COMMON_CLK_IPROC=y
+CONFIG_COMMON_CLK_LAN966X=m
+CONFIG_COMMON_CLK_MEDIATEK_FHCTL=y
+CONFIG_COMMON_CLK_MEDIATEK=y
+CONFIG_COMMON_CLK_MESON_AO_CLKC=y
+CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y
+CONFIG_COMMON_CLK_MESON_DUALDIV=y
+CONFIG_COMMON_CLK_MESON_EE_CLKC=y
+CONFIG_COMMON_CLK_MESON_MPLL=y
+CONFIG_COMMON_CLK_MESON_PLL=y
+CONFIG_COMMON_CLK_MESON_REGMAP=y
+CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y
+CONFIG_COMMON_CLK_MT2712=y
+CONFIG_COMMON_CLK_MT6765=y
+CONFIG_COMMON_CLK_MT6779_AUDSYS=y
+CONFIG_COMMON_CLK_MT6779_CAMSYS=y
+CONFIG_COMMON_CLK_MT6779_IMGSYS=y
+CONFIG_COMMON_CLK_MT6779_IPESYS=y
+CONFIG_COMMON_CLK_MT6779_MFGCFG=y
+CONFIG_COMMON_CLK_MT6779_MMSYS=y
+CONFIG_COMMON_CLK_MT6779_VDECSYS=y
+CONFIG_COMMON_CLK_MT6779_VENCSYS=y
+CONFIG_COMMON_CLK_MT6779=y
+CONFIG_COMMON_CLK_MT6795=m
+CONFIG_COMMON_CLK_MT6795_MFGCFG=m
+CONFIG_COMMON_CLK_MT6795_MMSYS=m
+CONFIG_COMMON_CLK_MT6795_VDECSYS=m
+CONFIG_COMMON_CLK_MT6795_VENCSYS=m
+CONFIG_COMMON_CLK_MT6797=y
+CONFIG_COMMON_CLK_MT7622=y
+CONFIG_COMMON_CLK_MT7981_ETHSYS=m
+CONFIG_COMMON_CLK_MT7981=y
+CONFIG_COMMON_CLK_MT7986_ETHSYS=y
+CONFIG_COMMON_CLK_MT7986=y
+CONFIG_COMMON_CLK_MT7988=m
+CONFIG_COMMON_CLK_MT8167_AUDSYS=y
+CONFIG_COMMON_CLK_MT8167_IMGSYS=y
+CONFIG_COMMON_CLK_MT8167_MFGCFG=y
+CONFIG_COMMON_CLK_MT8167_MMSYS=y
+CONFIG_COMMON_CLK_MT8167_VDECSYS=y
+CONFIG_COMMON_CLK_MT8167=y
+CONFIG_COMMON_CLK_MT8173_IMGSYS=m
+CONFIG_COMMON_CLK_MT8173_MMSYS=y
+CONFIG_COMMON_CLK_MT8173_VDECSYS=m
+CONFIG_COMMON_CLK_MT8173_VENCSYS=m
+CONFIG_COMMON_CLK_MT8173=y
+CONFIG_COMMON_CLK_MT8183=y
+CONFIG_COMMON_CLK_MT8186_CAMSYS=m
+CONFIG_COMMON_CLK_MT8186_IMGSYS=m
+CONFIG_COMMON_CLK_MT8186_IMP_IIC_WRAP=m
+CONFIG_COMMON_CLK_MT8186_IPESYS=m
+CONFIG_COMMON_CLK_MT8186_MCUSYS=m
+CONFIG_COMMON_CLK_MT8186_MDPSYS=m
+CONFIG_COMMON_CLK_MT8186_MFGCFG=m
+CONFIG_COMMON_CLK_MT8186_MMSYS=m
+CONFIG_COMMON_CLK_MT8186_VDECSYS=m
+CONFIG_COMMON_CLK_MT8186_VENCSYS=m
+CONFIG_COMMON_CLK_MT8186_WPESYS=m
+CONFIG_COMMON_CLK_MT8186=y
+CONFIG_COMMON_CLK_MT8188_ADSP_AUDIO26M=m
+CONFIG_COMMON_CLK_MT8188_CAMSYS=m
+CONFIG_COMMON_CLK_MT8188_IMGSYS=m
+CONFIG_COMMON_CLK_MT8188_IMP_IIC_WRAP=m
+CONFIG_COMMON_CLK_MT8188_IPESYS=m
+CONFIG_COMMON_CLK_MT8188=m
+CONFIG_COMMON_CLK_MT8188_MFGCFG=m
+CONFIG_COMMON_CLK_MT8188_VDECSYS=m
+CONFIG_COMMON_CLK_MT8188_VDOSYS=m
+CONFIG_COMMON_CLK_MT8188_VENCSYS=m
+CONFIG_COMMON_CLK_MT8188_VPPSYS=m
+CONFIG_COMMON_CLK_MT8188_WPESYS=m
+CONFIG_COMMON_CLK_MT8192_AUDSYS=y
+CONFIG_COMMON_CLK_MT8192_CAMSYS=y
+CONFIG_COMMON_CLK_MT8192_IMGSYS=y
+CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP=y
+CONFIG_COMMON_CLK_MT8192_IPESYS=y
+CONFIG_COMMON_CLK_MT8192_MDPSYS=y
+CONFIG_COMMON_CLK_MT8192_MFGCFG=y
+CONFIG_COMMON_CLK_MT8192_MMSYS=y
+CONFIG_COMMON_CLK_MT8192_MSDC=y
+CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y
+CONFIG_COMMON_CLK_MT8192_VDECSYS=y
+CONFIG_COMMON_CLK_MT8192_VENCSYS=y
+CONFIG_COMMON_CLK_MT8192=y
+CONFIG_COMMON_CLK_MT8195_APUSYS=m
+CONFIG_COMMON_CLK_MT8195_AUDSYS=m
+CONFIG_COMMON_CLK_MT8195_CAMSYS=m
+CONFIG_COMMON_CLK_MT8195_IMGSYS=m
+CONFIG_COMMON_CLK_MT8195_IMP_IIC_WRAP=m
+CONFIG_COMMON_CLK_MT8195_IPESYS=m
+CONFIG_COMMON_CLK_MT8195_MFGCFG=m
+CONFIG_COMMON_CLK_MT8195_MSDC=m
+CONFIG_COMMON_CLK_MT8195_SCP_ADSP=m
+CONFIG_COMMON_CLK_MT8195_VDECSYS=m
+CONFIG_COMMON_CLK_MT8195_VDOSYS=m
+CONFIG_COMMON_CLK_MT8195_VENCSYS=m
+CONFIG_COMMON_CLK_MT8195_VPPSYS=m
+CONFIG_COMMON_CLK_MT8195_WPESYS=m
+CONFIG_COMMON_CLK_MT8195=y
+CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP=m
+CONFIG_COMMON_CLK_MT8196=m
+CONFIG_COMMON_CLK_MT8196_MCUSYS=m
+CONFIG_COMMON_CLK_MT8196_MDPSYS=m
+CONFIG_COMMON_CLK_MT8196_MFGCFG=m
+CONFIG_COMMON_CLK_MT8196_MMSYS=m
+CONFIG_COMMON_CLK_MT8196_PEXTPSYS=m
+CONFIG_COMMON_CLK_MT8196_UFSSYS=m
+CONFIG_COMMON_CLK_MT8196_VDECSYS=m
+CONFIG_COMMON_CLK_MT8196_VENCSYS=m
+CONFIG_COMMON_CLK_MT8365_APU=m
+CONFIG_COMMON_CLK_MT8365_CAM=m
+CONFIG_COMMON_CLK_MT8365=m
+CONFIG_COMMON_CLK_MT8365_MFG=m
+CONFIG_COMMON_CLK_MT8365_MMSYS=m
+CONFIG_COMMON_CLK_MT8365_VDEC=m
+CONFIG_COMMON_CLK_MT8365_VENC=m
+CONFIG_COMMON_CLK_MT8516=y
+CONFIG_COMMON_CLK_NUVOTON=y
+CONFIG_COMMON_CLK_PWM=y
+CONFIG_COMMON_CLK_PXA1908=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_ROCKCHIP=y
+CONFIG_COMMON_CLK_RP1=m
+CONFIG_COMMON_CLK_RS9_PCIE=m
+CONFIG_COMMON_CLK_S2MPS11=y
+CONFIG_COMMON_CLK_S4_PERIPHERALS=m
+CONFIG_COMMON_CLK_S4_PLL=m
+CONFIG_COMMON_CLK_SAMSUNG=y
+CONFIG_COMMON_CLK_SCMI=y
+CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMMON_CLK_SI521XX=m
+CONFIG_COMMON_CLK_STM32MP135=y
+CONFIG_COMMON_CLK_STM32MP215=y
+CONFIG_COMMON_CLK_STM32MP257=y
+CONFIG_COMMON_CLK_STM32MP=y
+CONFIG_COMMON_CLK_VC3=m
+CONFIG_COMMON_CLK_VC7=m
+CONFIG_COMMON_CLK_VISCONTI=y
+CONFIG_COMMON_CLK_XLNX_CLKWZRD=m
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_RESET_HI3660=y
+CONFIG_COMMON_RESET_HI6220=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+CONFIG_COMPAT=y
+CONFIG_CONNECTOR=m
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTEXT_TRACKING_USER=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CORDIC=m
+CONFIG_CORTINA_PHY=m
+CONFIG_CP15_BARRIER_EMULATION=y
+CONFIG_CPM_TSA=m
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_THERMAL=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRC16=y
+CONFIG_CRC4=m
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC64=y
+CONFIG_CRC7=y
+CONFIG_CRC8=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROS_EC_CHARDEV=y
+CONFIG_CROS_EC_DEBUGFS=m
+CONFIG_CROS_EC_I2C=m
+CONFIG_CROS_EC_LIGHTBAR=m
+CONFIG_CROS_EC_MKBP_PROXIMITY=m
+CONFIG_CROS_EC_PROTO=y
+CONFIG_CROS_EC_RPMSG=m
+CONFIG_CROS_EC_SENSORHUB=y
+CONFIG_CROS_EC_SPI=m
+CONFIG_CROS_EC_SYSFS=m
+CONFIG_CROS_EC_TYPEC=m
+CONFIG_CROS_EC_UART=m
+CONFIG_CROS_EC_UCSI=m
+CONFIG_CROS_EC_VBC=m
+CONFIG_CROS_EC_WATCHDOG=m
+CONFIG_CROS_EC=y
+CONFIG_CROS_HPS_I2C=m
+CONFIG_CROS_TYPEC_SWITCH=m
+CONFIG_CROS_USBPD_LOGGER=m
+CONFIG_CROS_USBPD_NOTIFY=y
+CONFIG_CRYPTO_842=y
+CONFIG_CRYPTO_ADIANTUM=m
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEGIS128=m
+CONFIG_CRYPTO_AEGIS128_SIMD=y
+CONFIG_CRYPTO_AES_ARM64_BS=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_TI=m
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
+CONFIG_CRYPTO_ARIA=m
+CONFIG_CRYPTO_BLAKE2B=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_CAST_COMMON=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CFB=m
+CONFIG_CRYPTO_CHACHA20=m
+CONFIG_CRYPTO_CHACHA20_NEON=y
+CONFIG_CRYPTO_CHACHA20POLY1305=m
+CONFIG_CRYPTO_CMAC=m
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_CURVE25519=m
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_ALLWINNER=y
+CONFIG_CRYPTO_DEV_AMLOGIC_GXL=y
+CONFIG_CRYPTO_DEV_ATMEL_AES=m
+CONFIG_CRYPTO_DEV_ATMEL_ECC=m
+CONFIG_CRYPTO_DEV_ATMEL_I2C=m
+CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
+CONFIG_CRYPTO_DEV_BCM_SPU=m
+CONFIG_CRYPTO_DEV_CCREE=m
+CONFIG_CRYPTO_DEV_CHELSIO=m
+CONFIG_CRYPTO_DEV_CPT=m
+CONFIG_CRYPTO_DEV_EIP93=m
+CONFIG_CRYPTO_DEV_HISI_HPRE=m
+CONFIG_CRYPTO_DEV_HISI_QM=m
+CONFIG_CRYPTO_DEV_HISI_SEC2=m
+CONFIG_CRYPTO_DEV_HISI_SEC=m
+CONFIG_CRYPTO_DEV_HISI_TRNG=m
+CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_CTS=y
+CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_ECB=y
+CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4=m
+CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC=m
+CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224=y
+CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU=m
+CONFIG_CRYPTO_DEV_MARVELL_CESA=m
+CONFIG_CRYPTO_DEV_MARVELL=m
+CONFIG_CRYPTO_DEV_MXS_DCP=m
+CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m
+CONFIG_CRYPTO_DEV_NITROX=m
+CONFIG_CRYPTO_DEV_QAT_420XX=m
+CONFIG_CRYPTO_DEV_QAT_4XXX=m
+CONFIG_CRYPTO_DEV_QAT_C3XXX=m
+CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
+CONFIG_CRYPTO_DEV_QAT_C62X=m
+CONFIG_CRYPTO_DEV_QAT_C62XVF=m
+CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
+CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
+CONFIG_CRYPTO_DEV_QAT=m
+CONFIG_CRYPTO_DEV_QCE_AEAD=y
+CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y
+CONFIG_CRYPTO_DEV_QCE=m
+CONFIG_CRYPTO_DEV_QCE_SHA=y
+CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
+CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
+CONFIG_CRYPTO_DEV_QCOM_RNG=m
+CONFIG_CRYPTO_DEV_ROCKCHIP=y
+CONFIG_CRYPTO_DEV_SAFEXCEL=m
+CONFIG_CRYPTO_DEV_SAHARA=m
+CONFIG_CRYPTO_DEV_STM32_CRC=m
+CONFIG_CRYPTO_DEV_STM32_CRYP=m
+CONFIG_CRYPTO_DEV_STM32_HASH=m
+CONFIG_CRYPTO_DEV_SUN4I_SS=m
+CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
+CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
+CONFIG_CRYPTO_DEV_SUN8I_CE=m
+CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
+CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
+CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y
+CONFIG_CRYPTO_DEV_SUN8I_SS=m
+CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y
+CONFIG_CRYPTO_DEV_TEGRA=m
+CONFIG_CRYPTO_DEV_TI_DTHEV2=m
+CONFIG_CRYPTO_DEV_VIRTIO=m
+CONFIG_CRYPTO_DEV_XILINX_TRNG=m
+CONFIG_CRYPTO_DEV_ZYNQMP_SHA3=m
+CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
+CONFIG_CRYPTO_DH=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECC=m
+CONFIG_CRYPTO_ECDH=m
+CONFIG_CRYPTO_ECDSA=m
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_ECRDSA=m
+CONFIG_CRYPTO_ENGINE=y
+CONFIG_CRYPTO_ESSIV=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_GENIV=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HCTR2=m
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_KDF800108_CTR=y
+CONFIG_CRYPTO_KEYWRAP=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_KPP=y
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_LZ4HC=m
+CONFIG_CRYPTO_LZ4=m
+CONFIG_CRYPTO_LZO=m
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_NHPOLY1305_NEON=y
+CONFIG_CRYPTO_NHPOLY1305=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_OFB=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_POLY1305=m
+CONFIG_CRYPTO_POLY1305_NEON=y
+CONFIG_CRYPTO_POLYVAL_ARM64_CE=m
+CONFIG_CRYPTO_POLYVAL=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA3_ARM64=m
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SHA512_ARM64_CE=y
+CONFIG_CRYPTO_SHA512_ARM64=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SIG2=y
+CONFIG_CRYPTO_SM2=m
+CONFIG_CRYPTO_SM3_ARM64_CE=m
+CONFIG_CRYPTO_SM3_GENERIC=m
+CONFIG_CRYPTO_SM3=m
+CONFIG_CRYPTO_SM3_NEON=m
+CONFIG_CRYPTO_SM4_ARM64_CE_BLK=m
+CONFIG_CRYPTO_SM4_ARM64_CE_CCM=m
+CONFIG_CRYPTO_SM4_ARM64_CE_GCM=m
+CONFIG_CRYPTO_SM4_ARM64_CE=m
+CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=m
+CONFIG_CRYPTO_SM4_GENERIC=m
+CONFIG_CRYPTO_SM4=m
+CONFIG_CRYPTO_STREEBOG=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_RNG=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_USER_API=y
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_XCTR=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_XXHASH=m
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CV1800_MBOX=m
+CONFIG_CW1200=m
+CONFIG_CW1200_WLAN_SDIO=m
+CONFIG_CXL_ACPI=m
+CONFIG_CXL_BUS=m
+CONFIG_CXL_FEATURES=y
+CONFIG_CXL_MEM=m
+CONFIG_CXL_MEM_RAW_COMMANDS=y
+CONFIG_CXL_PCI=m
+CONFIG_CXL_PMEM=m
+CONFIG_CXL_PMU=m
+CONFIG_CXL_PORT=m
+CONFIG_CXL_REGION=y
+CONFIG_CXL_SUSPEND=y
+CONFIG_CYPRESS_FIRMWARE=m
+CONFIG_DA280=m
+CONFIG_DA311=m
+CONFIG_DAX=y
+CONFIG_DEBUG_WX=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DEFAULT_HOSTNAME="omv"
+CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=m
+CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU=m
+CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
+CONFIG_DEVFREQ_GOV_PASSIVE=m
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=m
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_USERSPACE=m
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_DEVICE_MIGRATION=y
+CONFIG_DEVTMPFS_SAFE=y
+CONFIG_DHT11=m
+CONFIG_DIMLIB=y
+CONFIG_DLHL60D=m
+CONFIG_DMA_ACPI=y
+CONFIG_DMA_BCM2835=m
+CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
+CONFIG_DMABUF_HEAPS_CMA_LEGACY=y
+CONFIG_DMABUF_HEAPS_CMA=y
+CONFIG_DMABUF_HEAPS_SYSTEM=y
+CONFIG_DMABUF_HEAPS=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_COHERENT_POOL=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE_RAID=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_NONCOHERENT_MMAP=y
+CONFIG_DMA_NUMA_CMA=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_PERNUMA_CMA=y
+CONFIG_DMARD06=m
+CONFIG_DMARD09=m
+CONFIG_DMARD10=m
+CONFIG_DMA_RESTRICTED_POOL=y
+CONFIG_DMA_SUN6I=m
+CONFIG_DMATEST=m
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DM_CACHE=m
+CONFIG_DM_CACHE_SMQ=m
+CONFIG_DM_CLONE=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_ERA=m
+CONFIG_DM_FLAKEY=m
+CONFIG_DMIID=y
+CONFIG_DM_INTEGRITY=m
+CONFIG_DMI=y
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_MULTIPATH_IOA=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_RAID=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_SWITCH=m
+CONFIG_DM_UEVENT=y
+CONFIG_DM_UNSTRIPED=m
+CONFIG_DM_VERITY=m
+CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
+CONFIG_DM_WRITECACHE=m
+CONFIG_DM_ZERO=m
+CONFIG_DP83640_PHY=m
+CONFIG_DP83848_PHY=m
+CONFIG_DP83869_PHY=m
+CONFIG_DP83TD510_PHY=m
+CONFIG_DP83TG720_PHY=m
+CONFIG_DPAA2_CONSOLE=y
+CONFIG_DPOT_DAC=m
+CONFIG_DPS310=m
+CONFIG_DRM_ACCEL_QAIC=m
+CONFIG_DRM_ACCEL_ROCKET=m
+CONFIG_DRM_ACCEL=y
+CONFIG_DRM_ADP=m
+CONFIG_DRM_AMD_ACP=y
+CONFIG_DRM_AMD_DC_SI=y
+CONFIG_DRM_AMD_DC=y
+CONFIG_DRM_AMDGPU_CIK=y
+CONFIG_DRM_AMDGPU=m
+CONFIG_DRM_AMDGPU_SI=y
+CONFIG_DRM_AMDGPU_USERPTR=y
+CONFIG_DRM_AMD_ISP=y
+CONFIG_DRM_AMD_SECURE_DISPLAY=m
+CONFIG_DRM_ANALOGIX_ANX6345=m
+CONFIG_DRM_ANALOGIX_ANX7625=m
+CONFIG_DRM_ANALOGIX_ANX78XX=m
+CONFIG_DRM_ANALOGIX_DP=y
+CONFIG_DRM_APPLETBDRM=m
+CONFIG_DRM_ARCPGU=m
+CONFIG_DRM_BOCHS=m
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_BUDDY=m
+CONFIG_DRM_CDNS_DSI_J721E=y
+CONFIG_DRM_CDNS_DSI=m
+CONFIG_DRM_CDNS_MHDP8546_J721E=y
+CONFIG_DRM_CDNS_MHDP8546=m
+CONFIG_DRM_CHIPONE_ICN6211=m
+CONFIG_DRM_CHRONTEL_CH7033=m
+CONFIG_DRM_CIRRUS_QEMU=m
+CONFIG_DRM_CLIENT_DEFAULT_LOG=y
+CONFIG_DRM_CLIENT_LOG=y
+CONFIG_DRM_CROS_EC_ANX7688=m
+CONFIG_DRM_DISPLAY_CONNECTOR=m
+CONFIG_DRM_DISPLAY_DP_AUX_CEC=y
+CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV=y
+CONFIG_DRM_DISPLAY_DP_HELPER=y
+CONFIG_DRM_DISPLAY_HDCP_HELPER=y
+CONFIG_DRM_DISPLAY_HDMI_HELPER=y
+CONFIG_DRM_DISPLAY_HELPER=y
+CONFIG_DRM_DP_AUX_BUS=m
+CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
+CONFIG_DRM_DW_HDMI_CEC=m
+CONFIG_DRM_DW_HDMI_GP_AUDIO=m
+CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
+CONFIG_DRM_DW_HDMI=y
+CONFIG_DRM_DW_MIPI_DSI=y
+CONFIG_DRM_ETNAVIV=m
+CONFIG_DRM_ETNAVIV_THERMAL=y
+CONFIG_DRM_EVDI=m
+CONFIG_DRM_EXYNOS5433_DECON=y
+CONFIG_DRM_EXYNOS7_DECON=y
+CONFIG_DRM_EXYNOS_DPI=y
+CONFIG_DRM_EXYNOS_DP=y
+CONFIG_DRM_EXYNOS_DSI=y
+CONFIG_DRM_EXYNOS_FIMC=y
+CONFIG_DRM_EXYNOS_FIMD=y
+CONFIG_DRM_EXYNOS_HDMI=y
+CONFIG_DRM_EXYNOS_IPP=y
+CONFIG_DRM_EXYNOS=m
+CONFIG_DRM_EXYNOS_MIC=y
+CONFIG_DRM_EXYNOS_MIXER=y
+CONFIG_DRM_EXYNOS_ROTATOR=y
+CONFIG_DRM_EXYNOS_SCALER=y
+CONFIG_DRM_EXYNOS_VIDI=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_FSL_LDB=m
+CONFIG_DRM_GEM_DMA_HELPER=y
+CONFIG_DRM_GEM_SHMEM_HELPER=y
+CONFIG_DRM_GM12U320=m
+CONFIG_DRM_GUD=m
+CONFIG_DRM_HDLCD=m
+CONFIG_DRM_HISI_HIBMC=m
+CONFIG_DRM_HISI_KIRIN=m
+CONFIG_DRM_HYPERV=m
+CONFIG_DRM_I2C_ADV7511_AUDIO=y
+CONFIG_DRM_I2C_ADV7511_CEC=y
+CONFIG_DRM_I2C_ADV7511=m
+CONFIG_DRM_IMX8_DC=m
+CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=m
+CONFIG_DRM_IMX8MP_HDMI_PVI=m
+CONFIG_DRM_IMX8QM_LDB=m
+CONFIG_DRM_IMX8QXP_LDB=m
+CONFIG_DRM_IMX8QXP_PIXEL_COMBINER=m
+CONFIG_DRM_IMX8QXP_PIXEL_LINK=m
+CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI=m
+CONFIG_DRM_IMX93_MIPI_DSI=m
+CONFIG_DRM_IMX_DCSS=m
+CONFIG_DRM_IMX_LCDC=m
+CONFIG_DRM_IMX_LCDIF=m
+CONFIG_DRM_IMX_LDB_HELPER=m
+CONFIG_DRM_ITE_IT6505=m
+CONFIG_DRM_ITE_IT66121=m
+CONFIG_DRM_KMB_DISPLAY=m
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_KOMEDA=m
+CONFIG_DRM_LIMA=m
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+CONFIG_DRM_LOGICVC=m
+CONFIG_DRM_LONTIUM_LT8912B=m
+CONFIG_DRM_LONTIUM_LT9211=m
+CONFIG_DRM_LONTIUM_LT9611=m
+CONFIG_DRM_LONTIUM_LT9611UXC=m
+CONFIG_DRM_LOONGSON=m
+CONFIG_DRM_LVDS_CODEC=m
+CONFIG_DRM_MALI_DISPLAY=m
+CONFIG_DRM_MEDIATEK_DP=m
+CONFIG_DRM_MEDIATEK_HDMI=m
+CONFIG_DRM_MEDIATEK=m
+CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m
+CONFIG_DRM_MESON_DW_HDMI=m
+CONFIG_DRM_MESON_DW_MIPI_DSI=m
+CONFIG_DRM_MESON=m
+CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER=m
+CONFIG_DRM_MIPI_DBI=m
+CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_MSM_DPU=y
+CONFIG_DRM_MSM_DP=y
+CONFIG_DRM_MSM_DSI_10NM_PHY=y
+CONFIG_DRM_MSM_DSI_14NM_PHY=y
+CONFIG_DRM_MSM_DSI_20NM_PHY=y
+CONFIG_DRM_MSM_DSI_28NM_8960_PHY=y
+CONFIG_DRM_MSM_DSI_28NM_PHY=y
+CONFIG_DRM_MSM_DSI_7NM_PHY=y
+CONFIG_DRM_MSM_DSI=y
+CONFIG_DRM_MSM_GPU_STATE=y
+CONFIG_DRM_MSM_HDMI_HDCP=y
+CONFIG_DRM_MSM_HDMI=y
+CONFIG_DRM_MSM=m
+CONFIG_DRM_MSM_MDP4=y
+CONFIG_DRM_MSM_MDP5=y
+CONFIG_DRM_MSM_MDSS=y
+CONFIG_DRM_MXSFB=m
+CONFIG_DRM_MXS=y
+CONFIG_DRM_NOUVEAU_CH7006=m
+CONFIG_DRM_NOUVEAU_GSP_DEFAULT=y
+CONFIG_DRM_NOUVEAU=m
+CONFIG_DRM_NOUVEAU_SIL164=m
+CONFIG_DRM_NWL_MIPI_DSI=m
+CONFIG_DRM_NXP_PTN3460=m
+CONFIG_DRM_PANEL_ABT_Y030XX067A=m
+CONFIG_DRM_PANEL_ARM_VERSATILE=m
+CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
+CONFIG_DRM_PANEL_AUO_A030JTN01=m
+CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
+CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
+CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A=m
+CONFIG_DRM_PANEL_BOE_TV101WUM_LL2=m
+CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_DSI_CM=m
+CONFIG_DRM_PANEL_EBBG_FT8719=m
+CONFIG_DRM_PANEL_EDP=m
+CONFIG_DRM_PANEL_ELIDA_KD35T133=m
+CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
+CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
+CONFIG_DRM_PANEL_HIMAX_HX83102=m
+CONFIG_DRM_PANEL_HIMAX_HX83112A=m
+CONFIG_DRM_PANEL_HIMAX_HX83112B=m
+CONFIG_DRM_PANEL_HIMAX_HX8394=m
+CONFIG_DRM_PANEL_HYDIS_HV101HD1=m
+CONFIG_DRM_PANEL_ILITEK_IL9322=m
+CONFIG_DRM_PANEL_ILITEK_ILI9341=m
+CONFIG_DRM_PANEL_ILITEK_ILI9805=m
+CONFIG_DRM_PANEL_ILITEK_ILI9806E=m
+CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
+CONFIG_DRM_PANEL_ILITEK_ILI9882T=m
+CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
+CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
+CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=m
+CONFIG_DRM_PANEL_JDI_LPM102A188A=m
+CONFIG_DRM_PANEL_JDI_LT070ME05000=m
+CONFIG_DRM_PANEL_JDI_R63452=m
+CONFIG_DRM_PANEL_KHADAS_TS050=m
+CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
+CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
+CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
+CONFIG_DRM_PANEL_LG_LB035Q02=m
+CONFIG_DRM_PANEL_LG_LG4573=m
+CONFIG_DRM_PANEL_LG_SW43408=m
+CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m
+CONFIG_DRM_PANEL_LVDS=m
+CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m
+CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
+CONFIG_DRM_PANEL_MIPI_DBI=m
+CONFIG_DRM_PANEL_NEC_NL8048HL11=m
+CONFIG_DRM_PANEL_NEWVISION_NV3051D=m
+CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
+CONFIG_DRM_PANEL_NOVATEK_NT35510=m
+CONFIG_DRM_PANEL_NOVATEK_NT35560=m
+CONFIG_DRM_PANEL_NOVATEK_NT35950=m
+CONFIG_DRM_PANEL_NOVATEK_NT36523=m
+CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
+CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
+CONFIG_DRM_PANEL_NOVATEK_NT39016=m
+CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_PANEL_ORISETECH_OTA5601A=m
+CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
+CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
+CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
+CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
+CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
+CONFIG_DRM_PANEL_RAYDIUM_RM67200=m
+CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
+CONFIG_DRM_PANEL_RAYDIUM_RM692E5=m
+CONFIG_DRM_PANEL_RAYDIUM_RM69380=m
+CONFIG_DRM_PANEL_RENESAS_R61307=m
+CONFIG_DRM_PANEL_RENESAS_R69328=m
+CONFIG_DRM_PANEL_RONBO_RB070D30=m
+CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
+CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
+CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
+CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
+CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
+CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01=m
+CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
+CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
+CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
+CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
+CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
+CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
+CONFIG_DRM_PANEL_SIMPLE=m
+CONFIG_DRM_PANEL_SITRONIX_ST7701=m
+CONFIG_DRM_PANEL_SITRONIX_ST7703=m
+CONFIG_DRM_PANEL_SITRONIX_ST7789V=m
+CONFIG_DRM_PANEL_SONY_ACX565AKM=m
+CONFIG_DRM_PANEL_SONY_TD4353_JDI=m
+CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
+CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m
+CONFIG_DRM_PANEL_SUMMIT=m
+CONFIG_DRM_PANEL_SYNAPTICS_R63353=m
+CONFIG_DRM_PANEL_TDO_TL070WSH30=m
+CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
+CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
+CONFIG_DRM_PANEL_TPO_TPG110=m
+CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
+CONFIG_DRM_PANEL_VISIONOX_R66451=m
+CONFIG_DRM_PANEL_VISIONOX_RM69299=m
+CONFIG_DRM_PANEL_VISIONOX_RM692E5=m
+CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
+CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
+CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANFROST=m
+CONFIG_DRM_PANIC_BACKGROUND_COLOR=0x000000
+CONFIG_DRM_PANIC_FOREGROUND_COLOR=0xa0a0a0
+CONFIG_DRM_PANIC_SCREEN="user"
+CONFIG_DRM_PANIC=y
+CONFIG_DRM_PANTHOR=m
+CONFIG_DRM_PARADE_PS8622=m
+CONFIG_DRM_PARADE_PS8640=m
+CONFIG_DRM_PIXPAPER=m
+CONFIG_DRM_PL111=m
+CONFIG_DRM_PRIVACY_SCREEN=y
+CONFIG_DRM_RADEON=m
+CONFIG_DRM_RCAR_CMM=m
+CONFIG_DRM_RCAR_DU=m
+CONFIG_DRM_RCAR_DW_HDMI=m
+CONFIG_DRM_RCAR_LVDS=m
+CONFIG_DRM_RCAR_MIPI_DSI=m
+CONFIG_DRM_RCAR_USE_CMM=y
+CONFIG_DRM_RCAR_USE_LVDS=y
+CONFIG_DRM_RCAR_USE_MIPI_DSI=y
+CONFIG_DRM_RCAR_VSP=y
+CONFIG_DRM_RCAR_WRITEBACK=y
+CONFIG_DRM_ROCKCHIP=y
+CONFIG_DRM_RZG2L_DU=m
+CONFIG_DRM_RZG2L_MIPI_DSI=m
+CONFIG_DRM_SAMSUNG_DSIM=m
+CONFIG_DRM_SCHED=y
+CONFIG_DRM_SHMOBILE=m
+CONFIG_DRM_SII902X=m
+CONFIG_DRM_SII9234=m
+CONFIG_DRM_SIL_SII8620=m
+CONFIG_DRM_SIMPLE_BRIDGE=m
+CONFIG_DRM_SIMPLEDRM=y
+CONFIG_DRM_SOLOMON_SSD2825=m
+CONFIG_DRM_SPRD=m
+CONFIG_DRM_SSD130X_I2C=m
+CONFIG_DRM_SSD130X=m
+CONFIG_DRM_SSD130X_SPI=m
+CONFIG_DRM_STM_DSI=m
+CONFIG_DRM_STM_LVDS=m
+CONFIG_DRM_STM=m
+CONFIG_DRM_SUBALLOC_HELPER=m
+CONFIG_DRM_SUN4I=m
+CONFIG_DRM_SUN6I_DSI=m
+CONFIG_DRM_SUN8I_DW_HDMI=m
+CONFIG_DRM_SUN8I_MIXER=m
+CONFIG_DRM_SUN8I_TCON_TOP=m
+CONFIG_DRM_TEGRA=m
+CONFIG_DRM_TEGRA_STAGING=y
+CONFIG_DRM_THINE_THC63LVD1024=m
+CONFIG_DRM_TI_DLPC3433=m
+CONFIG_DRM_TIDSS=m
+CONFIG_DRM_TI_SN65DSI83=m
+CONFIG_DRM_TI_SN65DSI86=m
+CONFIG_DRM_TI_TFP410=m
+CONFIG_DRM_TI_TPD12S015=m
+CONFIG_DRM_TOSHIBA_TC358762=m
+CONFIG_DRM_TOSHIBA_TC358764=m
+CONFIG_DRM_TOSHIBA_TC358767=m
+CONFIG_DRM_TOSHIBA_TC358768=m
+CONFIG_DRM_TOSHIBA_TC358775=m
+CONFIG_DRM_TTM_HELPER=m
+CONFIG_DRM_TTM=m
+CONFIG_DRM_UDL=m
+CONFIG_DRM_V3D=m
+CONFIG_DRM_VC4_HDMI_CEC=y
+CONFIG_DRM_VC4=m
+CONFIG_DRM_VGEM=m
+CONFIG_DRM_VIRTIO_GPU_KMS=y
+CONFIG_DRM_VIRTIO_GPU=m
+CONFIG_DRM_VKMS=m
+CONFIG_DRM_VRAM_HELPER=m
+CONFIG_DRM_WAVESHARE_BRIDGE=m
+CONFIG_DRM_XE_DEVMEM_MIRROR=y
+CONFIG_DRM_XE_DISPLAY=y
+CONFIG_DRM_XE_DP_TUNNEL=y
+CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT=y
+CONFIG_DRM_XE_FORCE_PROBE=""
+CONFIG_DRM_XE_JOB_TIMEOUT_MAX=10000
+CONFIG_DRM_XE_JOB_TIMEOUT_MIN=1
+CONFIG_DRM_XE=m
+CONFIG_DRM_XE_PREEMPT_TIMEOUT=640000
+CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX=10000000
+CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN=1
+CONFIG_DRM_XE_TIMESLICE_MAX=10000000
+CONFIG_DRM_XE_TIMESLICE_MIN=1
+CONFIG_DRM=y
+CONFIG_DRM_ZYNQMP_DPSUB_AUDIO=y
+CONFIG_DRM_ZYNQMP_DPSUB=m
+CONFIG_DS1803=m
+CONFIG_DS4424=m
+CONFIG_DTC=y
+CONFIG_DT_IDLE_GENPD=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DTPM=y
+CONFIG_DUMMY_CONSOLE_ROWS=30
+CONFIG_DUMMY_IRQ=m
+CONFIG_DUMMY=m
+CONFIG_DVB_A8293=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_AF9033=m
+CONFIG_DVB_ASCOT2E=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_AU8522_DTV=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_AU8522_V4L=m
+CONFIG_DVB_AV7110_IR=y
+CONFIG_DVB_AV7110=m
+CONFIG_DVB_AV7110_OSD=y
+CONFIG_DVB_B2C2_FLEXCOP=m
+CONFIG_DVB_B2C2_FLEXCOP_PCI=m
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_BT8XX=m
+CONFIG_DVB_BUDGET_AV=m
+CONFIG_DVB_BUDGET_CI=m
+CONFIG_DVB_BUDGET_CORE=m
+CONFIG_DVB_BUDGET=m
+CONFIG_DVB_BUDGET_PATCH=m
+CONFIG_DVB_CORE=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_CX24117=m
+CONFIG_DVB_CX24120=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_CXD2841ER=m
+CONFIG_DVB_CXD2880=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_DIB9000=m
+CONFIG_DVB_DM1105=m
+CONFIG_DVB_DRX39XYJ=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_EC100=m
+CONFIG_DVB_GP8PSK_FE=m
+CONFIG_DVB_HELENE=m
+CONFIG_DVB_HORUS3A=m
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6422=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_LG2160=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_LGDT3306A=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGS8GL5=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_LNBH25=m
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_M88DS3103=m
+CONFIG_DVB_M88RS2000=m
+CONFIG_DVB_MAX_ADAPTERS=8
+CONFIG_DVB_MB86A20S=m
+CONFIG_DVB_MN88443X=m
+CONFIG_DVB_MN88472=m
+CONFIG_DVB_MN88473=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_MXL692=m
+CONFIG_DVB_NETUP_UNIDVB=m
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_PLATFORM_DRIVERS=y
+CONFIG_DVB_PLL=m
+CONFIG_DVB_PLUTO2=m
+CONFIG_DVB_RTL2830=m
+CONFIG_DVB_RTL2832=m
+CONFIG_DVB_RTL2832_SDR=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_S5H1411=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_S5H1432=m
+CONFIG_DVB_S921=m
+CONFIG_DVB_SI2165=m
+CONFIG_DVB_SI2168=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STV0297=m
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV6110x=m
+CONFIG_DVB_TAS2101=m
+CONFIG_DVB_TC90522=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_TDA10071=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA18271C2DD=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TS2020=m
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_DIB3000MC=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_V2=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DW_APB_ICTL=y
+CONFIG_DW_APB_TIMER_OF=y
+CONFIG_DW_APB_TIMER=y
+CONFIG_DWC_PCIE_PMU=m
+CONFIG_DW_I3C_MASTER=m
+CONFIG_DW_WATCHDOG=m
+CONFIG_DW_XDATA_PCIE=m
+CONFIG_EC_ACER_ASPIRE1=m
+CONFIG_ECHO=m
+CONFIG_EC_HUAWEI_GAOKUN=m
+CONFIG_EC_LENOVO_THINKPAD_T14S=m
+CONFIG_EC_LENOVO_YOGA_C630=m
+CONFIG_EDAC_AL_MC=m
+CONFIG_EDAC_CORTEX_A72=m
+CONFIG_EDAC_ECS=y
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC=m
+CONFIG_EDAC_MEM_REPAIR=y
+CONFIG_EDAC_NPCM=m
+CONFIG_EDAC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EDAC_THUNDERX=m
+CONFIG_EDAC_VERSAL=m
+CONFIG_EDAC_VERSALNET=m
+CONFIG_EDAC_XGENE=m
+CONFIG_EDAC_ZYNQMP=m
+CONFIG_EEPROM_93CX6=m
+CONFIG_EEPROM_AT25=m
+CONFIG_EEPROM_EE1004=m
+CONFIG_EEPROM_LEGACY=m
+CONFIG_EFI_ARMSTUB_DTB_LOADER=y
+CONFIG_EFI_BOOTLOADER_CONTROL=m
+CONFIG_EFI_CAPSULE_LOADER=m
+CONFIG_EFI_COCO_SECRET=y
+CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_GENERIC_STUB=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_SBAT_FILE=""
+CONFIG_EFI_SECRET=m
+CONFIG_EFI_SOFT_RESERVE=y
+CONFIG_EFI_STUB=y
+CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
+CONFIG_EFI_VARS_PSTORE=m
+CONFIG_EFI=y
+CONFIG_EFI_ZBOOT=y
+CONFIG_EINT_MTK=y
+CONFIG_EMBEDDED=y
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_ENS160=m
+CONFIG_ENS210=m
+CONFIG_ENVELOPE_DETECTOR=m
+CONFIG_EQUALIZER=m
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXPERT=y
+CONFIG_EXTCON_LC824206XA=m
+CONFIG_EXTCON_MAX14526=m
+CONFIG_EXTCON_QCOM_SPMI_MISC=m
+CONFIG_EXTCON_RTK_TYPE_C=m
+CONFIG_EXTCON_USBC_TUSB320=m
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_EXTCON=y
+CONFIG_EXYNOS_ACPM_PROTOCOL=m
+CONFIG_EXYNOS_ADC=m
+CONFIG_EXYNOS_ARM64_COMMON_CLK=y
+CONFIG_EXYNOS_AUDSS_CLK_CON=y
+CONFIG_EXYNOS_CHIPID=y
+CONFIG_EXYNOS_CLKOUT=m
+CONFIG_EXYNOS_IOMMU=y
+CONFIG_EXYNOS_MBOX=m
+CONFIG_EXYNOS_PM_DOMAINS=y
+CONFIG_EXYNOS_PMU=y
+CONFIG_EXYNOS_THERMAL=y
+CONFIG_EXYNOS_USI=m
+CONFIG_FAILOVER=y
+CONFIG_FARSYNC=m
+CONFIG_FB_BACKLIGHT=m
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_IO_HELPERS=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA=y
+CONFIG_FB_SM750=m
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_HELPERS_DEFERRED=y
+CONFIG_FB_SYS_HELPERS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FB_TFT_AGM1264K_FL=m
+CONFIG_FB_TFT_BD663474=m
+CONFIG_FB_TFT_HX8340BN=m
+CONFIG_FB_TFT_HX8347D=m
+CONFIG_FB_TFT_HX8353D=m
+CONFIG_FB_TFT_HX8357D=m
+CONFIG_FB_TFT_ILI9163=m
+CONFIG_FB_TFT_ILI9320=m
+CONFIG_FB_TFT_ILI9325=m
+CONFIG_FB_TFT_ILI9340=m
+CONFIG_FB_TFT_ILI9341=m
+CONFIG_FB_TFT_ILI9481=m
+CONFIG_FB_TFT_ILI9486=m
+CONFIG_FB_TFT=m
+CONFIG_FB_TFT_PCD8544=m
+CONFIG_FB_TFT_RA8875=m
+CONFIG_FB_TFT_S6D02A1=m
+CONFIG_FB_TFT_S6D1121=m
+CONFIG_FB_TFT_SEPS525=m
+CONFIG_FB_TFT_SH1106=m
+CONFIG_FB_TFT_SSD1289=m
+CONFIG_FB_TFT_SSD1305=m
+CONFIG_FB_TFT_SSD1306=m
+CONFIG_FB_TFT_SSD1331=m
+CONFIG_FB_TFT_SSD1351=m
+CONFIG_FB_TFT_ST7735R=m
+CONFIG_FB_TFT_ST7789V=m
+CONFIG_FB_TFT_TINYLCD=m
+CONFIG_FB_TFT_TLS8204=m
+CONFIG_FB_TFT_UC1611=m
+CONFIG_FB_TFT_UC1701=m
+CONFIG_FB_TFT_UPD161704=m
+CONFIG_FIB_RULES=y
+CONFIG_FIELDBUS_DEV=m
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONTS=y
+CONFIG_FORTIFY_SOURCE=y
+CONFIG_FPGA=m
+CONFIG_FPGA_M10_BMC_SEC_UPDATE=m
+CONFIG_FPGA_MGR_LATTICE_SYSCONFIG=m
+CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=m
+CONFIG_FPGA_MGR_MICROCHIP_SPI=m
+CONFIG_FPGA_MGR_SOCFPGA_A10=m
+CONFIG_FPGA_MGR_SOCFPGA=m
+CONFIG_FPGA_MGR_VERSAL_FPGA=m
+CONFIG_FPGA_MGR_XILINX_SELECTMAP=m
+CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FRONTSWAP=y
+CONFIG_FSL_ERRATUM_A008585=y
+CONFIG_FSL_GUTS=y
+CONFIG_FSL_IFC=y
+CONFIG_FSL_IMX8_DDR_PMU=m
+CONFIG_FSL_IMX9_DDR_PMU=m
+CONFIG_FSL_RCPM=y
+CONFIG_FSL_UCC_HDLC=m
+CONFIG_FTL=m
+CONFIG_FUEL_GAUGE_MM8013=m
+CONFIG_FUEL_GAUGE_STC3117=m
+CONFIG_FUJITSU_ERRATUM_010001=y
+CONFIG_FUJITSU_ES=m
+CONFIG_FUJITSU_UNCORE_PMU=m
+CONFIG_FUNCTION_ALIGNMENT=4
+CONFIG_FUNCTION_ALIGNMENT_4B=y
+CONFIG_FW_CFG_SYSFS_CMDLINE=y
+CONFIG_FW_CFG_SYSFS=m
+CONFIG_FW_CS_DSP=m
+CONFIG_FW_LOADER_COMPRESS_XZ=y
+CONFIG_FW_LOADER_COMPRESS=y
+CONFIG_FW_LOADER_COMPRESS_ZSTD=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_UPLOAD=y
+CONFIG_FXAS21002C_I2C=m
+CONFIG_FXAS21002C=m
+CONFIG_FXAS21002C_SPI=m
+CONFIG_FXLS8962AF_I2C=m
+CONFIG_FXLS8962AF=m
+CONFIG_FXLS8962AF_SPI=m
+CONFIG_FXOS8700_I2C=m
+CONFIG_FXOS8700=m
+CONFIG_FXOS8700_SPI=m
+CONFIG_GADGET_UAC1_LEGACY=y
+CONFIG_GADGET_UAC1=y
+CONFIG_GAMEPORT_EMU10K1=m
+CONFIG_GAMEPORT_FM801=m
+CONFIG_GAMEPORT_L4=m
+CONFIG_GAMEPORT=m
+CONFIG_GAMEPORT_NS558=m
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y
+CONFIG_GCC_VERSION=0
+CONFIG_GENERIC_ADC_BATTERY=m
+CONFIG_GENERIC_ARCH_NUMA=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_IPI=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PHY_MIPI_DPHY=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_PTDUMP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_VDSO_TIME_NS=y
+CONFIG_GENEVE=m
+CONFIG_GET_FREE_REGION=y
+CONFIG_GOOGLE_CBMEM=m
+CONFIG_GOOGLE_COREBOOT_TABLE=m
+CONFIG_GOOGLE_FIRMWARE=y
+CONFIG_GOOGLE_FRAMEBUFFER_COREBOOT=m
+CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m
+CONFIG_GOOGLE_MEMCONSOLE=m
+CONFIG_GOOGLE_VPD=m
+CONFIG_GP2AP002=m
+CONFIG_GP2AP020A00F=m
+CONFIG_GPIO_74XX_MMIO=m
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIO_ADP5585=m
+CONFIG_GPIO_ALTERA_A10SR=m
+CONFIG_GPIO_BCM_XGS_IPROC=m
+CONFIG_GPIO_BRCMSTB=m
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CROS_EC=m
+CONFIG_GPIO_DS4520=m
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_EIC_SPRD=m
+CONFIG_GPIO_EN7523=m
+CONFIG_GPIO_FXL6408=m
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GRGPIO=m
+CONFIG_GPIO_HISI=m
+CONFIG_GPIO_HLWD=m
+CONFIG_GPIO_IMX_SCU=y
+CONFIG_GPIO_LATCH=m
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_LJCA=m
+CONFIG_GPIO_LOGICVC=m
+CONFIG_GPIO_MAX732X=m
+CONFIG_GPIO_MAX77620=y
+CONFIG_GPIO_MB86S7X=y
+CONFIG_GPIO_MVEBU=y
+CONFIG_GPIO_MXC=y
+CONFIG_GPIO_NPCM_SGPIO=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA9570=m
+CONFIG_GPIO_PCF857X=m
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_RASPBERRYPI_EXP=m
+CONFIG_GPIO_RCAR=y
+CONFIG_GPIO_REGMAP=m
+CONFIG_GPIO_ROCKCHIP=m
+CONFIG_GPIO_RTD=m
+CONFIG_GPIO_SIFIVE=y
+CONFIG_GPIO_SIM=m
+CONFIG_GPIO_SL28CPLD=m
+CONFIG_GPIO_SPRD=m
+CONFIG_GPIO_SYSFS_LEGACY=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_TEGRA186=m
+CONFIG_GPIO_TEGRA=y
+CONFIG_GPIO_THUNDERX=m
+CONFIG_GPIO_TPS65219=m
+CONFIG_GPIO_UNIPHIER=y
+CONFIG_GPIO_VF610=y
+CONFIG_GPIO_VIRTIO=m
+CONFIG_GPIO_VISCONTI=m
+CONFIG_GPIO_WATCHDOG=m
+CONFIG_GPIO_XGENE_SB=y
+CONFIG_GPIO_XGENE=y
+CONFIG_GPIO_XLP=y
+CONFIG_GPIO_ZYNQ=m
+CONFIG_GPIO_ZYNQMP_MODEPIN=m
+CONFIG_GP_PCI1XXXX=m
+CONFIG_GTP=m
+CONFIG_GUEST_PERF_EVENTS=y
+CONFIG_HARDENED_USERCOPY=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HARDLOCKUP_DETECTOR_BUDDY=y
+CONFIG_HARDLOCKUP_DETECTOR_COUNTS_HRTIMER=y
+CONFIG_HARDLOCKUP_DETECTOR=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_LTO_CLANG=y
+CONFIG_HD44780_COMMON=m
+CONFIG_HDC100X=m
+CONFIG_HDC2010=m
+CONFIG_HDC3020=m
+CONFIG_HDLC_CISCO=m
+CONFIG_HDLC_FR=m
+CONFIG_HDLC=m
+CONFIG_HDLC_PPP=m
+CONFIG_HDLC_RAW_ETH=m
+CONFIG_HDLC_RAW=m
+CONFIG_HDLC_X25=m
+CONFIG_HDMI=y
+CONFIG_HERMES_CACHE_FW_ON_INIT=y
+CONFIG_HERMES=m
+CONFIG_HERMES_PRISM=y
+CONFIG_HI3660_MBOX=m
+CONFIG_HI6220_MBOX=m
+CONFIG_HI6421V600_IRQ=m
+CONFIG_HI8435=m
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION_COMP_LZO=y
+CONFIG_HIBERNATION_SNAPSHOT_DEV=y
+CONFIG_HIBERNATION=y
+CONFIG_HID_SENSOR_ACCEL_3D=m
+CONFIG_HID_SENSOR_ALS=m
+CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
+CONFIG_HID_SENSOR_DEVICE_ROTATION=m
+CONFIG_HID_SENSOR_GYRO_3D=m
+CONFIG_HID_SENSOR_HUMIDITY=m
+CONFIG_HID_SENSOR_IIO_COMMON=m
+CONFIG_HID_SENSOR_IIO_TRIGGER=m
+CONFIG_HID_SENSOR_INCLINOMETER_3D=m
+CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
+CONFIG_HID_SENSOR_PRESS=m
+CONFIG_HID_SENSOR_PROX=m
+CONFIG_HID_SENSOR_TEMP=m
+CONFIG_HISI_DMA=m
+CONFIG_HISI_HIKEY_USB=m
+CONFIG_HISILICON_ERRATUM_161010101=y
+CONFIG_HISILICON_ERRATUM_161600802=y
+CONFIG_HISILICON_IRQ_MBIGEN=y
+CONFIG_HISI_PCIE_PMU=m
+CONFIG_HISI_PMU=m
+CONFIG_HISI_PTT=m
+CONFIG_HISI_THERMAL=m
+CONFIG_HMC425=m
+CONFIG_HMEM_REPORTING=y
+CONFIG_HMM_MIRROR=y
+CONFIG_HNS3_PMU=m
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_PLX=m
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_PCI_ACPI_AMPERE_ALTRA=m
+CONFIG_HOTPLUG_PCI_ACPI_IBM=m
+CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_HOTPLUG_PCI_SHPC=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HP03=m
+CONFIG_HP206C=m
+CONFIG_HP_WATCHDOG=m
+CONFIG_HSA_AMD=y
+CONFIG_HSC030PA=m
+CONFIG_HSI_BOARDINFO=y
+CONFIG_HSI_CHAR=m
+CONFIG_HSI=m
+CONFIG_HTE_TEGRA194=m
+CONFIG_HTE=y
+CONFIG_HTS221_I2C=m
+CONFIG_HTS221=m
+CONFIG_HTS221_SPI=m
+CONFIG_HTU21=m
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
+CONFIG_HW_RANDOM_BA431=m
+CONFIG_HW_RANDOM_BCM2835=m
+CONFIG_HW_RANDOM_CAVIUM=m
+CONFIG_HW_RANDOM_CN10K=m
+CONFIG_HW_RANDOM_EXYNOS=m
+CONFIG_HW_RANDOM_HISI=m
+CONFIG_HW_RANDOM_HISTB=m
+CONFIG_HW_RANDOM_IPROC_RNG200=m
+CONFIG_HW_RANDOM_MESON=m
+CONFIG_HW_RANDOM_MTK=m
+CONFIG_HW_RANDOM_NPCM=m
+CONFIG_HW_RANDOM_OPTEE=m
+CONFIG_HW_RANDOM_ROCKCHIP=y
+CONFIG_HW_RANDOM_STM32=m
+CONFIG_HW_RANDOM_TIMERIOMEM=m
+CONFIG_HW_RANDOM_TPM=y
+CONFIG_HW_RANDOM_VIRTIO=m
+CONFIG_HW_RANDOM_XGENE=m
+CONFIG_HW_RANDOM_XIPHERA=m
+CONFIG_HW_RANDOM=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_HWSPINLOCK_SUN6I=m
+CONFIG_HWSPINLOCK=y
+CONFIG_HX711=m
+CONFIG_HX9023S=m
+CONFIG_HYPERV_BALLOON=m
+CONFIG_HYPERV_KEYBOARD=m
+CONFIG_HYPERV_NET=m
+CONFIG_HYPERV_STORAGE=m
+CONFIG_HYPERV_UTILS=m
+CONFIG_HYPERV_VMBUS=m
+CONFIG_HYPERV=y
+CONFIG_HZ=300
+CONFIG_HZ_300=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_ALTERA=m
+CONFIG_I2C_APPLE=m
+CONFIG_I2C_AT91=m
+CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL=y
+CONFIG_I2C_ATR=m
+CONFIG_I2C_BCM2835=m
+CONFIG_I2C_BCM_IPROC=m
+CONFIG_I2C_BRCMSTB=m
+CONFIG_I2C_CBUS_GPIO=m
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_CP2615=m
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_I2C_DEMUX_PINCTRL=m
+CONFIG_I2C_DESIGNWARE_CORE=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_EMEV2=m
+CONFIG_I2C_EXYNOS5=m
+CONFIG_I2C_HISI=m
+CONFIG_I2C_HIX5HD2=m
+CONFIG_I2C_IMX_LPI2C=m
+CONFIG_I2C_IMX=y
+CONFIG_I2C_LJCA=m
+CONFIG_I2C_MESON=y
+CONFIG_I2C_MLXCPLD=m
+CONFIG_I2C_MT65XX=m
+CONFIG_I2C_MT7621=m
+CONFIG_I2C_MUX_GPMUX=m
+CONFIG_I2C_MUX_MULE=m
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_MUX_PINCTRL=m
+CONFIG_I2C_MUX_REG=m
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_I2C_NCT6694=m
+CONFIG_I2C_NOMADIK=m
+CONFIG_I2C_NPCM=m
+CONFIG_I2C_PARPORT=m
+CONFIG_I2C_PCI1XXXX=m
+CONFIG_I2C_PXA=y
+CONFIG_I2C_QUP=y
+CONFIG_I2C_RCAR=y
+CONFIG_I2C_RIIC=m
+CONFIG_I2C_RK3X=y
+CONFIG_I2C_ROBOTFUZZ_OSIF=m
+CONFIG_I2C_RZV2M=m
+CONFIG_I2C_S3C2410=m
+CONFIG_I2C_SH_MOBILE=y
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SMBUS=y
+CONFIG_I2C_STM32F4=m
+CONFIG_I2C_STM32F7=m
+CONFIG_I2C_TAOS_EVM=m
+CONFIG_I2C_TEGRA_BPMP=m
+CONFIG_I2C_TEGRA=y
+CONFIG_I2C_THUNDERX=m
+CONFIG_I2C_TINY_USB=m
+CONFIG_I2C_UNIPHIER_F=y
+CONFIG_I2C_UNIPHIER=m
+CONFIG_I2C_USBIO=m
+CONFIG_I2C_VIRTIO=m
+CONFIG_I2C_XGENE_SLIMPRO=m
+CONFIG_I2C_XLP9XX=m
+CONFIG_I2C=y
+CONFIG_I2C_ZHAOXIN=m
+CONFIG_I3C=m
+CONFIG_IAQCORE=m
+CONFIG_ICP10100=m
+CONFIG_IFB=m
+CONFIG_IIO_ADIS_LIB_BUFFER=y
+CONFIG_IIO_ADIS_LIB=m
+CONFIG_IIO_BUFFER_CB=m
+CONFIG_IIO_BUFFER_DMAENGINE=m
+CONFIG_IIO_BUFFER_DMA=m
+CONFIG_IIO_BUFFER_HW_CONSUMER=m
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
+CONFIG_IIO_CROS_EC_ACTIVITY=m
+CONFIG_IIO_CROS_EC_BARO=m
+CONFIG_IIO_CROS_EC_LIGHT_PROX=m
+CONFIG_IIO_CROS_EC_SENSORS_CORE=m
+CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m
+CONFIG_IIO_CROS_EC_SENSORS=m
+CONFIG_IIO_GTS_HELPER=m
+CONFIG_IIO_INTERRUPT_TRIGGER=m
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_KX022A_I2C=m
+CONFIG_IIO_KX022A=m
+CONFIG_IIO_KX022A_SPI=m
+CONFIG_IIO_MS_SENSORS_I2C=m
+CONFIG_IIO_MUX=m
+CONFIG_IIO_RESCALE=m
+CONFIG_IIO_SCMI=m
+CONFIG_IIO_SSP_SENSORHUB=m
+CONFIG_IIO_SSP_SENSORS_COMMONS=m
+CONFIG_IIO_ST_ACCEL_3AXIS=m
+CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
+CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
+CONFIG_IIO_ST_GYRO_3AXIS=m
+CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
+CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
+CONFIG_IIO_ST_LSM6DSX_I2C=m
+CONFIG_IIO_ST_LSM6DSX_I3C=m
+CONFIG_IIO_ST_LSM6DSX=m
+CONFIG_IIO_ST_LSM6DSX_SPI=m
+CONFIG_IIO_ST_LSM9DS0_I2C=m
+CONFIG_IIO_ST_LSM9DS0=m
+CONFIG_IIO_ST_LSM9DS0_SPI=m
+CONFIG_IIO_STM32_LPTIMER_TRIGGER=m
+CONFIG_IIO_STM32_TIMER_TRIGGER=m
+CONFIG_IIO_ST_MAGN_3AXIS=m
+CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
+CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
+CONFIG_IIO_ST_PRESS_I2C=m
+CONFIG_IIO_ST_PRESS=m
+CONFIG_IIO_ST_PRESS_SPI=m
+CONFIG_IIO_ST_SENSORS_CORE=m
+CONFIG_IIO_ST_SENSORS_I2C=m
+CONFIG_IIO_ST_SENSORS_SPI=m
+CONFIG_IIO_SYSFS_TRIGGER=m
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_IIO_TRIGGERED_EVENT=m
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_IMX2_WDT=m
+CONFIG_IMX7D_ADC=m
+CONFIG_IMX7ULP_WDT=m
+CONFIG_IMX8M_BLK_CTRL=y
+CONFIG_IMX8QXP_ADC=m
+CONFIG_IMX93_ADC=m
+CONFIG_IMX9_BLK_CTRL=y
+CONFIG_IMX_AIPSTZ=m
+CONFIG_IMX_DMA=m
+CONFIG_IMX_DSP=m
+CONFIG_IMX_DSP_REMOTEPROC=m
+CONFIG_IMX_GPCV2_PM_DOMAINS=y
+CONFIG_IMX_GPCV2=y
+CONFIG_IMX_INTMUX=y
+CONFIG_IMX_IRQSTEER=y
+CONFIG_IMX_MBOX=y
+CONFIG_IMX_MU_MSI=m
+CONFIG_IMX_REMOTEPROC=m
+CONFIG_IMX_SCMI_BBM_EXT=m
+CONFIG_IMX_SCMI_CPU_DRV=m
+CONFIG_IMX_SCMI_CPU_EXT=m
+CONFIG_IMX_SCMI_LMM_DRV=m
+CONFIG_IMX_SCMI_LMM_EXT=m
+CONFIG_IMX_SCMI_MISC_DRV=m
+CONFIG_IMX_SCMI_MISC_EXT=m
+CONFIG_IMX_SCU_PD=y
+CONFIG_IMX_SCU=y
+CONFIG_IMX_SC_WDT=m
+CONFIG_IMX_SDMA=m
+CONFIG_IMX_THERMAL=m
+CONFIG_IMX_WEIM=y
+CONFIG_INA2XX_ADC=m
+CONFIG_INFINEON_TLV493D=m
+CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
+CONFIG_INFINIBAND_ADDR_TRANS=y
+CONFIG_INFINIBAND_BNXT_RE=m
+CONFIG_INFINIBAND_CXGB4=m
+CONFIG_INFINIBAND_EFA=m
+CONFIG_INFINIBAND_ERDMA=m
+CONFIG_INFINIBAND_HNS_HIP08=y
+CONFIG_INFINIBAND_HNS=m
+CONFIG_INFINIBAND_IONIC=m
+CONFIG_INFINIBAND_IPOIB_CM=y
+CONFIG_INFINIBAND_IPOIB=m
+CONFIG_INFINIBAND_IRDMA=m
+CONFIG_INFINIBAND_ISER=m
+CONFIG_INFINIBAND=m
+CONFIG_INFINIBAND_MTHCA=m
+CONFIG_INFINIBAND_OCRDMA=m
+CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
+CONFIG_INFINIBAND_QEDR=m
+CONFIG_INFINIBAND_RTRS_CLIENT=m
+CONFIG_INFINIBAND_RTRS=m
+CONFIG_INFINIBAND_RTRS_SERVER=m
+CONFIG_INFINIBAND_SRP=m
+CONFIG_INFINIBAND_USER_ACCESS=m
+CONFIG_INFINIBAND_USER_MAD=m
+CONFIG_INFINIBAND_USER_MEM=y
+CONFIG_INFINIBAND_VIRT_DMA=y
+CONFIG_INFINIBAND_VMWARE_PVRDMA=m
+CONFIG_INFTL=m
+CONFIG_INIT_STACK_NONE=y
+CONFIG_INPUT_ATC260X_ONKEY=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_AW86927=m
+CONFIG_INPUT_AXP20X_PEK=m
+CONFIG_INPUT_BBNSM_PWRKEY=m
+CONFIG_INPUT_CM109=m
+CONFIG_INPUT_CMA3000=m
+CONFIG_INPUT_CS40L50_VIBRA=m
+CONFIG_INPUT_DA7280_HAPTICS=m
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_HISI_POWERKEY=m
+CONFIG_INPUT_IBM_PANEL=m
+CONFIG_INPUT_IMS_PCU=m
+CONFIG_INPUT_IQS626A=m
+CONFIG_INPUT_IQS7222=m
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_LEDS=m
+CONFIG_INPUT_MATRIXKMAP=y
+CONFIG_INPUT_MAX7360_ROTARY=m
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MMA8450=m
+CONFIG_INPUT_PM8941_PWRKEY=y
+CONFIG_INPUT_PM8XXX_VIBRATOR=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_QNAP_MCU=m
+CONFIG_INPUT_RK805_PWRKEY=y
+CONFIG_INPUT_RT5120_PWRKEY=m
+CONFIG_INPUT_TABLET=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_TPS65219_PWRBUTTON=m
+CONFIG_INPUT_TPS6594_PWRBUTTON=m
+CONFIG_INPUT_UINPUT=m
+CONFIG_INPUT_VIVALDIFMAP=y
+CONFIG_INPUT_YEALINK=m
+CONFIG_INTEL_TH_GTH=m
+CONFIG_INTEL_TH=m
+CONFIG_INTEL_TH_MSU=m
+CONFIG_INTEL_TH_PCI=m
+CONFIG_INTEL_TH_PTI=m
+CONFIG_INTEL_TH_STH=m
+CONFIG_INTEL_XWAY_PHY=m
+CONFIG_INTERCONNECT_CLK=m
+CONFIG_INTERCONNECT_EXYNOS=m
+CONFIG_INTERCONNECT_IMX8MM=m
+CONFIG_INTERCONNECT_IMX8MN=m
+CONFIG_INTERCONNECT_IMX8MP=m
+CONFIG_INTERCONNECT_IMX8MQ=m
+CONFIG_INTERCONNECT_IMX=m
+CONFIG_INTERCONNECT_MTK=y
+CONFIG_INTERCONNECT_QCOM_BCM_VOTER=m
+CONFIG_INTERCONNECT_QCOM_GLYMUR=m
+CONFIG_INTERCONNECT_QCOM_MILOS=m
+CONFIG_INTERCONNECT_QCOM_MSM8909=m
+CONFIG_INTERCONNECT_QCOM_MSM8916=m
+CONFIG_INTERCONNECT_QCOM_MSM8937=m
+CONFIG_INTERCONNECT_QCOM_MSM8939=m
+CONFIG_INTERCONNECT_QCOM_MSM8953=m
+CONFIG_INTERCONNECT_QCOM_MSM8974=m
+CONFIG_INTERCONNECT_QCOM_MSM8976=m
+CONFIG_INTERCONNECT_QCOM_MSM8996=m
+CONFIG_INTERCONNECT_QCOM_OSM_L3=m
+CONFIG_INTERCONNECT_QCOM_QCM2290=m
+CONFIG_INTERCONNECT_QCOM_QCS404=m
+CONFIG_INTERCONNECT_QCOM_QDU1000=m
+CONFIG_INTERCONNECT_QCOM_RPMH=m
+CONFIG_INTERCONNECT_QCOM_RPMH_POSSIBLE=m
+CONFIG_INTERCONNECT_QCOM_SA8775P=m
+CONFIG_INTERCONNECT_QCOM_SC8280XP=m
+CONFIG_INTERCONNECT_QCOM_SDM660=m
+CONFIG_INTERCONNECT_QCOM_SDM670=m
+CONFIG_INTERCONNECT_QCOM_SDX65=m
+CONFIG_INTERCONNECT_QCOM_SDX75=m
+CONFIG_INTERCONNECT_QCOM_SM6115=m
+CONFIG_INTERCONNECT_QCOM_SM6350=m
+CONFIG_INTERCONNECT_QCOM_SM7150=m
+CONFIG_INTERCONNECT_QCOM_SM8450=m
+CONFIG_INTERCONNECT_QCOM_SM8550=m
+CONFIG_INTERCONNECT_QCOM_SM8650=m
+CONFIG_INTERCONNECT_QCOM_SM8750=m
+CONFIG_INTERCONNECT_QCOM_SMD_RPM=m
+CONFIG_INTERCONNECT_QCOM_X1E80100=m
+CONFIG_INTERCONNECT_QCOM=y
+CONFIG_INTERCONNECT_SAMSUNG=y
+CONFIG_INTERCONNECT=y
+CONFIG_INTERVAL_TREE_SPAN_ITER=y
+CONFIG_INV_ICM42600_I2C=m
+CONFIG_INV_ICM42600=m
+CONFIG_INV_ICM42600_SPI=m
+CONFIG_INV_MPU6050_I2C=m
+CONFIG_INV_MPU6050_IIO=m
+CONFIG_INV_MPU6050_SPI=m
+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMUFD=m
+CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+CONFIG_IOMMU_IO_PGTABLE=y
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_SVA=y
+CONFIG_IOSCHED_BFQ=y
+CONFIG_IOSM=m
+CONFIG_IP5XXX_POWER=m
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_DMI_DECODE=y
+CONFIG_IPMI_HANDLER=m
+CONFIG_IPMI_IPMB=m
+CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m
+CONFIG_IPMI_KCS_BMC=m
+CONFIG_IPMI_KCS_BMC_SERIO=m
+CONFIG_IPMI_PANIC_EVENT=y
+CONFIG_IPMI_PANIC_STRING=y
+CONFIG_IPMI_PLAT_DATA=y
+CONFIG_IPMI_POWEROFF=m
+CONFIG_IPMI_SI=m
+CONFIG_IPMI_SSIF=m
+CONFIG_IPMI_WATCHDOG=m
+CONFIG_IPMMU_VMSA=y
+CONFIG_IPQ_APSS_5424=m
+CONFIG_IPQ_APSS_6018=m
+CONFIG_IPQ_APSS_PLL=m
+CONFIG_IPQ_CMN_PLL=m
+CONFIG_IPQ_GCC_5018=m
+CONFIG_IPQ_GCC_5332=m
+CONFIG_IPQ_GCC_8074=m
+CONFIG_IPQ_GCC_9574=m
+CONFIG_IPQ_NSSCC_9574=m
+CONFIG_IPQ_NSSCC_QCA8K=m
+CONFIG_IPU_BRIDGE=m
+CONFIG_IPVLAN_L3S=y
+CONFIG_IPVLAN=m
+CONFIG_IPVTAP=m
+CONFIG_IPW2100=m
+CONFIG_IPW2100_MONITOR=y
+CONFIG_IPW2200=m
+CONFIG_IPW2200_MONITOR=y
+CONFIG_IPW2200_PROMISCUOUS=y
+CONFIG_IPW2200_QOS=y
+CONFIG_IPW2200_RADIOTAP=y
+CONFIG_IR_IMON_DECODER=m
+CONFIG_IR_IMON_RAW=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_IR_MESON=m
+CONFIG_IR_MESON_TX=m
+CONFIG_IR_MTK=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IRQ_BYPASS_MANAGER=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_POLL=y
+CONFIG_IRQ_SIM=y
+CONFIG_IRQ_UNIPHIER_AIDET=y
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_RCMM_DECODER=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IRSD200=m
+CONFIG_IR_SHARP_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_SUNXI=m
+CONFIG_IR_TOY=m
+CONFIG_IR_XMP_DECODER=m
+CONFIG_ISCSI_BOOT_SYSFS=m
+CONFIG_ISCSI_TCP=m
+CONFIG_ISL29125=m
+CONFIG_ISL29501=m
+CONFIG_ISL76682=m
+CONFIG_ITG3200=m
+CONFIG_IWL3945=m
+CONFIG_IWL4965=m
+CONFIG_IWLDVM=m
+CONFIG_IWLEGACY=m
+CONFIG_IWLMLD=m
+CONFIG_IWLMVM=m
+CONFIG_IWLWIFI_LEDS=y
+CONFIG_IWLWIFI=m
+CONFIG_IWLWIFI_OPMODE_MODULAR=y
+CONFIG_JOYSTICK_A3D=m
+CONFIG_JOYSTICK_ADC=m
+CONFIG_JOYSTICK_ADI=m
+CONFIG_JOYSTICK_ANALOG=m
+CONFIG_JOYSTICK_AS5011=m
+CONFIG_JOYSTICK_COBRA=m
+CONFIG_JOYSTICK_DB9=m
+CONFIG_JOYSTICK_GAMECON=m
+CONFIG_JOYSTICK_GF2K=m
+CONFIG_JOYSTICK_GRIP=m
+CONFIG_JOYSTICK_GRIP_MP=m
+CONFIG_JOYSTICK_GUILLEMOT=m
+CONFIG_JOYSTICK_IFORCE_232=m
+CONFIG_JOYSTICK_IFORCE=m
+CONFIG_JOYSTICK_IFORCE_USB=m
+CONFIG_JOYSTICK_INTERACT=m
+CONFIG_JOYSTICK_JOYDUMP=m
+CONFIG_JOYSTICK_MAGELLAN=m
+CONFIG_JOYSTICK_PXRC=m
+CONFIG_JOYSTICK_QWIIC=m
+CONFIG_JOYSTICK_SEESAW=m
+CONFIG_JOYSTICK_SENSEHAT=m
+CONFIG_JOYSTICK_SIDEWINDER=m
+CONFIG_JOYSTICK_SPACEBALL=m
+CONFIG_JOYSTICK_SPACEORB=m
+CONFIG_JOYSTICK_STINGER=m
+CONFIG_JOYSTICK_TMDC=m
+CONFIG_JOYSTICK_TURBOGRAFX=m
+CONFIG_JOYSTICK_TWIDJOY=m
+CONFIG_JOYSTICK_WALKERA0701=m
+CONFIG_JOYSTICK_WARRIOR=m
+CONFIG_JOYSTICK_XPAD_FF=y
+CONFIG_JOYSTICK_XPAD_LEDS=y
+CONFIG_JOYSTICK_XPAD=m
+CONFIG_JOYSTICK_ZHENHUA=m
+CONFIG_JSA1212=m
+CONFIG_K3_DMA=y
+CONFIG_KCMP=y
+CONFIG_KEEMBAY_WATCHDOG=m
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_KERNEL_ZSTD=y
+CONFIG_KEXEC_HANDOVER=y
+CONFIG_KEYBOARD_ADC=m
+CONFIG_KEYBOARD_BCM=m
+CONFIG_KEYBOARD_CAP11XX=m
+CONFIG_KEYBOARD_CROS_EC=y
+CONFIG_KEYBOARD_CYPRESS_SF=m
+CONFIG_KEYBOARD_DLINK_DIR685=m
+CONFIG_KEYBOARD_GPIO_POLLED=m
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_IMX_BBM_SCMI=m
+CONFIG_KEYBOARD_IMX=m
+CONFIG_KEYBOARD_IMX_SC_KEY=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_MT6779=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_NVEC=m
+CONFIG_KEYBOARD_PINEPHONE=m
+CONFIG_KEYBOARD_PXA27x=m
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_KEYBOARD_SUN4I_LRADC=m
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_TEGRA=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEY_DH_OPERATIONS=y
+CONFIG_KEYS_REQUEST_CACHE=y
+CONFIG_KMX61=m
+CONFIG_KRETPROBES=y
+CONFIG_KS0108_DELAY=2
+CONFIG_KS0108=m
+CONFIG_KS0108_PORT=0x378
+CONFIG_KS7010=m
+CONFIG_KSM=y
+CONFIG_KUNPENG_HCCS=m
+CONFIG_KUSER_HELPERS=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_VFIO=y
+CONFIG_KVM_XFER_TO_GUEST_WORK=y
+CONFIG_KVM=y
+CONFIG_KXCJK1013=m
+CONFIG_KXSD9_I2C=m
+CONFIG_KXSD9=m
+CONFIG_KXSD9_SPI=m
+CONFIG_LAPBETHER=m
+CONFIG_LATENCYTOP=y
+CONFIG_LCD2S=m
+CONFIG_LCD_AMS369FG06=m
+CONFIG_LCD_CLASS_DEVICE=m
+CONFIG_LCD_HX8357=m
+CONFIG_LCD_ILI922X=m
+CONFIG_LCD_ILI9320=m
+CONFIG_LCD_L4F00242T03=m
+CONFIG_LCD_LMS283GF05=m
+CONFIG_LCD_LMS501KF03=m
+CONFIG_LCD_LTV350QV=m
+CONFIG_LCD_OTM3225A=m
+CONFIG_LCD_PLATFORM=m
+CONFIG_LCD_TDO24M=m
+CONFIG_LCD_VGG2432A4=m
+CONFIG_LD_IS_LLD=y
+CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
+CONFIG_LD_ORPHAN_WARN=y
+CONFIG_LD_VERSION=0
+CONFIG_LEDS_AW200XX=m
+CONFIG_LEDS_BCM63138=m
+CONFIG_LEDS_BD2606MVV=m
+CONFIG_LEDS_BLINKM=m
+CONFIG_LEDS_CLASS_MULTICOLOR=m
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CROS_EC=m
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GROUP_MULTICOLOR=m
+CONFIG_LEDS_KTD202X=m
+CONFIG_LEDS_LM355x=m
+CONFIG_LEDS_LM3642=m
+CONFIG_LEDS_LM3697=m
+CONFIG_LEDS_LP50XX=m
+CONFIG_LEDS_LP5569=m
+CONFIG_LEDS_LP55XX_COMMON=m
+CONFIG_LEDS_LP8864=m
+CONFIG_LEDS_MAX5970=m
+CONFIG_LEDS_MT6370_RGB=m
+CONFIG_LEDS_NCP5623=m
+CONFIG_LEDS_PCA995X=m
+CONFIG_LEDS_PWM_MULTICOLOR=m
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_QCOM_LPG=m
+CONFIG_LEDS_REGULATOR=m
+CONFIG_LEDS_ST1202=m
+CONFIG_LEDS_SUN50I_A100=m
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TCA6507=m
+CONFIG_LEDS_TI_LMU_COMMON=m
+CONFIG_LEDS_TRIGGER_ACTIVITY=y
+CONFIG_LEDS_TRIGGER_AUDIO=m
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_CAMERA=m
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_GPIO=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_NETDEV=m
+CONFIG_LEDS_TRIGGER_ONESHOT=m
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEDS_TRIGGER_PATTERN=m
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_TRANSIENT=m
+CONFIG_LEDS_TRIGGER_TTY=m
+CONFIG_LEDS_USER=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211=m
+CONFIG_LIBCRC32C=m
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_MESH=y
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBFC=m
+CONFIG_LIBFDT=y
+CONFIG_LIBIPW=m
+CONFIG_LIBNVDIMM=y
+CONFIG_LIDAR_LITE_V2=m
+CONFIG_LINEAR_RANGES=y
+CONFIG_LIRC=y
+CONFIG_LITEX_SOC_CONTROLLER=m
+CONFIG_LITEX=y
+CONFIG_LLD_VERSION=160006
+CONFIG_LMK04832=m
+CONFIG_LMP91000=m
+CONFIG_LOCK_MM_AND_FIND_VMA=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_LP_CONSOLE=y
+CONFIG_LRU_CACHE=m
+CONFIG_LRU_GEN_ENABLED=y
+CONFIG_LRU_GEN=y
+CONFIG_LS_EXTIRQ=y
+CONFIG_LSM="landlock,yama,loadpin,safesetid,integrity,bpf"
+CONFIG_LS_SCFG_MSI=y
+CONFIG_LTC1660=m
+CONFIG_LTC2309=m
+CONFIG_LTC2471=m
+CONFIG_LTC2485=m
+CONFIG_LTC2496=m
+CONFIG_LTC2497=m
+CONFIG_LTC2632=m
+CONFIG_LTC2664=m
+CONFIG_LTC2688=m
+CONFIG_LTC2983=m
+CONFIG_LTE_GDM724X=m
+CONFIG_LTO_CLANG_THIN=y
+CONFIG_LTO_CLANG=y
+CONFIG_LTO=y
+CONFIG_LTR390=m
+CONFIG_LTR501=m
+CONFIG_LTRF216A=m
+CONFIG_LV0104CS=m
+CONFIG_LWTUNNEL_BPF=y
+CONFIG_LWTUNNEL=y
+CONFIG_M62332=m
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_HWSIM=m
+CONFIG_MAC80211_LEDS=y
+CONFIG_MAC80211=m
+CONFIG_MAC80211_MESH=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MACSEC=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_MADERA_IRQ=m
+CONFIG_MAG3110=m
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
+CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAILBOX_TEST=m
+CONFIG_MAILBOX=y
+CONFIG_MANA_INFINIBAND=m
+CONFIG_MARVELL_10G_PHY=m
+CONFIG_MARVELL_88Q2XXX_PHY=m
+CONFIG_MARVELL_88X2222_PHY=m
+CONFIG_MARVELL_CN10K_DDR_PMU=m
+CONFIG_MARVELL_CN10K_TAD_PMU=m
+CONFIG_MARVELL_GTI_WDT=m
+CONFIG_MARVELL_PHY=m
+CONFIG_MAX1027=m
+CONFIG_MAX11100=m
+CONFIG_MAX1118=m
+CONFIG_MAX11205=m
+CONFIG_MAX11410=m
+CONFIG_MAX1241=m
+CONFIG_MAX1363=m
+CONFIG_MAX30100=m
+CONFIG_MAX30102=m
+CONFIG_MAX30208=m
+CONFIG_MAX31856=m
+CONFIG_MAX31865=m
+CONFIG_MAX34408=m
+CONFIG_MAX44000=m
+CONFIG_MAX44009=m
+CONFIG_MAX517=m
+CONFIG_MAX5432=m
+CONFIG_MAX5481=m
+CONFIG_MAX5487=m
+CONFIG_MAX5522=m
+CONFIG_MAX5821=m
+CONFIG_MAX6959=m
+CONFIG_MAX77541_ADC=m
+CONFIG_MAX77620_THERMAL=m
+CONFIG_MAX77620_WATCHDOG=m
+CONFIG_MAX9611=m
+CONFIG_MAXIM_THERMOCOUPLE=m
+CONFIG_MAXLINEAR_GPHY=m
+CONFIG_MB1232=m
+CONFIG_MC3230=m
+CONFIG_MCP320X=m
+CONFIG_MCP3422=m
+CONFIG_MCP3564=m
+CONFIG_MCP3911=m
+CONFIG_MCP4018=m
+CONFIG_MCP41010=m
+CONFIG_MCP4131=m
+CONFIG_MCP4531=m
+CONFIG_MCP4725=m
+CONFIG_MCP4728=m
+CONFIG_MCP4821=m
+CONFIG_MCP4922=m
+CONFIG_MCP9600=m
+CONFIG_MCTP_FLOWS=y
+CONFIG_MCTP_SERIAL=m
+CONFIG_MCTP_TRANSPORT_I2C=m
+CONFIG_MCTP_TRANSPORT_I3C=m
+CONFIG_MCTP_TRANSPORT_USB=m
+CONFIG_MCTP=y
+CONFIG_MD_CLUSTER=m
+CONFIG_MDIO_BCM_UNIMAC=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS_MUX_BCM_IPROC=m
+CONFIG_MDIO_BUS_MUX_MESON_G12A=m
+CONFIG_MDIO_BUS_MUX_MESON_GXL=m
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_CAVIUM=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_GPIO=m
+CONFIG_MDIO_HISI_FEMAC=m
+CONFIG_MDIO_I2C=m
+CONFIG_MDIO_MSCC_MIIM=m
+CONFIG_MDIO_REGMAP=m
+CONFIG_MDIO_SUN4I=m
+CONFIG_MDIO_THUNDER=y
+CONFIG_MDIO_XGENE=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID456=m
+CONFIG_MEDIA_ALTERA_CI=m
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CEC_SUPPORT=y
+CONFIG_MEDIA_COMMON_OPTIONS=y
+CONFIG_MEDIA_CONTROLLER_DVB=y
+CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_PCI_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIATEK_GE_PHY=m
+CONFIG_MEDIATEK_GE_SOC_PHY=m
+CONFIG_MEDIATEK_MT6359_AUXADC=m
+CONFIG_MEDIATEK_MT6370_ADC=m
+CONFIG_MEDIATEK_MT6577_AUXADC=m
+CONFIG_MEDIATEK_WATCHDOG=m
+CONFIG_MEDIA_TEST_SUPPORT=y
+CONFIG_MEDIA_TUNER_AV201X=m
+CONFIG_MEDIA_TUNER_E4000=m
+CONFIG_MEDIA_TUNER_FC0011=m
+CONFIG_MEDIA_TUNER_FC0012=m
+CONFIG_MEDIA_TUNER_FC0013=m
+CONFIG_MEDIA_TUNER_FC2580=m
+CONFIG_MEDIA_TUNER_IT913X=m
+CONFIG_MEDIA_TUNER=m
+CONFIG_MEDIA_TUNER_M88RS6000T=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2063=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2131=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_QM1D1C0042=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_R820T=m
+CONFIG_MEDIA_TUNER_SI2157=m
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_STV6120=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TDA18250=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_MEGARAID_LEGACY=m
+CONFIG_MEGARAID_MAILBOX=m
+CONFIG_MEGARAID_MM=m
+CONFIG_MEGARAID_NEWGEN=y
+CONFIG_MEGARAID_SAS=m
+CONFIG_MEMORY_FAILURE=y
+CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y
+CONFIG_MEMORY_HOTPLUG=y
+CONFIG_MEMORY_HOTREMOVE=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MEMORY=y
+CONFIG_MEMREGION=y
+CONFIG_MESON_CANVAS=m
+CONFIG_MESON_CLK_MEASURE=y
+CONFIG_MESON_DDR_PMU=m
+CONFIG_MESON_EE_PM_DOMAINS=y
+CONFIG_MESON_GXBB_WATCHDOG=m
+CONFIG_MESON_GXL_PHY=m
+CONFIG_MESON_GX_PM_DOMAINS=y
+CONFIG_MESON_GX_SOCINFO=y
+CONFIG_MESON_IRQ_GPIO=y
+CONFIG_MESON_SARADC=m
+CONFIG_MESON_SECURE_PM_DOMAINS=y
+CONFIG_MESON_SM=y
+CONFIG_MESON_WATCHDOG=m
+CONFIG_MFD_88PM886_PMIC=y
+CONFIG_MFD_AC100=m
+CONFIG_MFD_ALTERA_A10SR=y
+CONFIG_MFD_AS3722=m
+CONFIG_MFD_ATC260X_I2C=m
+CONFIG_MFD_ATC260X=m
+CONFIG_MFD_ATMEL_FLEXCOM=m
+CONFIG_MFD_AXP20X_RSB=y
+CONFIG_MFD_AXP20X=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_CROS_EC_DEV=y
+CONFIG_MFD_CS42L43_I2C=m
+CONFIG_MFD_CS42L43_SDW=m
+CONFIG_MFD_CS47L35=y
+CONFIG_MFD_CS47L85=y
+CONFIG_MFD_CS47L90=y
+CONFIG_MFD_EXYNOS_LPASS=m
+CONFIG_MFD_HI6421_PMIC=y
+CONFIG_MFD_HI6421_SPMI=m
+CONFIG_MFD_HI655X_PMIC=y
+CONFIG_MFD_INTEL_M10_BMC_CORE=m
+CONFIG_MFD_INTEL_M10_BMC_SPI=m
+CONFIG_MFD_KHADAS_MCU=m
+CONFIG_MFD_MACSMC=m
+CONFIG_MFD_MADERA_I2C=m
+CONFIG_MFD_MADERA=m
+CONFIG_MFD_MADERA_SPI=m
+CONFIG_MFD_MAX5970=m
+CONFIG_MFD_MAX7360=m
+CONFIG_MFD_MAX77541=m
+CONFIG_MFD_MAX77620=y
+CONFIG_MFD_MAX77714=m
+CONFIG_MFD_MAX77759=m
+CONFIG_MFD_MC13XXX_I2C=m
+CONFIG_MFD_MC13XXX=m
+CONFIG_MFD_MT6370=m
+CONFIG_MFD_NTXEC=m
+CONFIG_MFD_NVEC=m
+CONFIG_MFD_OCELOT=m
+CONFIG_MFD_QCOM_PM8008=m
+CONFIG_MFD_QCOM_RPM=m
+CONFIG_MFD_QNAP_MCU=m
+CONFIG_MFD_RK8XX_I2C=m
+CONFIG_MFD_RK8XX_SPI=m
+CONFIG_MFD_RK8XX=y
+CONFIG_MFD_ROHM_BD957XMUF=m
+CONFIG_MFD_ROHM_BD96801=m
+CONFIG_MFD_RSMU_I2C=m
+CONFIG_MFD_RSMU_SPI=m
+CONFIG_MFD_RT4831=m
+CONFIG_MFD_RT5120=m
+CONFIG_MFD_SEC_ACPM=m
+CONFIG_MFD_SEC_CORE=y
+CONFIG_MFD_SEC_I2C=m
+CONFIG_MFD_SI476X_CORE=m
+CONFIG_MFD_SIMPLE_MFD_I2C=m
+CONFIG_MFD_SL28CPLD=m
+CONFIG_MFD_SMPRO=m
+CONFIG_MFD_SPMI_PMIC=y
+CONFIG_MFD_STM32_LPTIMER=m
+CONFIG_MFD_STM32_TIMERS=m
+CONFIG_MFD_SUN4I_GPADC=m
+CONFIG_MFD_SUN6I_PRCM=y
+CONFIG_MFD_SY7636A=m
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_TPS65219=m
+CONFIG_MFD_TPS6594_I2C=m
+CONFIG_MFD_TPS6594=m
+CONFIG_MFD_TPS6594_SPI=m
+CONFIG_MFD_VEXPRESS_SYSREG=y
+CONFIG_MFD_WM8994=m
+CONFIG_MHI_BUS_EP=m
+CONFIG_MHI_BUS=m
+CONFIG_MHI_BUS_PCI_GENERIC=m
+CONFIG_MHI_NET=m
+CONFIG_MHI_WWAN_CTRL=m
+CONFIG_MHI_WWAN_MBIM=m
+CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO=y
+CONFIG_MHP_MEMMAP_ON_MEMORY=y
+CONFIG_MICREL_PHY=y
+CONFIG_MICROCHIP_PHY=m
+CONFIG_MICROCHIP_T1_PHY=m
+CONFIG_MICROCHIP_T1S_PHY=m
+CONFIG_MICROSEMI_PHY=m
+CONFIG_MII=y
+CONFIG_MIPI_I3C_HCI=m
+CONFIG_MIPI_I3C_HCI_PCI=m
+CONFIG_MISC_RP1=m
+CONFIG_MISC_RTSX=m
+CONFIG_MISC_RTSX_PCI=m
+CONFIG_MISC_RTSX_USB=m
+CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
+CONFIG_MLX4_INFINIBAND=m
+CONFIG_MLX5_INFINIBAND=m
+CONFIG_MLX5_VFIO_PCI=m
+CONFIG_MLX90614=m
+CONFIG_MLX90632=m
+CONFIG_MLX90635=m
+CONFIG_MMA7455_I2C=m
+CONFIG_MMA7455=m
+CONFIG_MMA7455_SPI=m
+CONFIG_MMA7660=m
+CONFIG_MMA8452=m
+CONFIG_MMA9551_CORE=m
+CONFIG_MMA9551=m
+CONFIG_MMA9553=m
+CONFIG_MMC35240=m
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_BCM2835=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CAVIUM_THUNDERX=m
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_CRYPTO=y
+CONFIG_MMC_DW_EXYNOS=y
+CONFIG_MMC_DW_HI3798MV200=m
+CONFIG_MMC_DW_K3=y
+CONFIG_MMC_DW_PCI=y
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_HSQ=m
+CONFIG_MMC_LITEX=m
+CONFIG_MMC_MESON_GX=y
+CONFIG_MMC_MESON_MX_SDIO=m
+CONFIG_MMC_MTK=m
+CONFIG_MMC_MXC=m
+CONFIG_MMC_OWL=m
+CONFIG_MMC_QCOM_DML=y
+CONFIG_MMC_REALTEK_PCI=m
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_AM654=m
+CONFIG_MMC_SDHCI_BRCMSTB=m
+CONFIG_MMC_SDHCI_CADENCE=m
+CONFIG_MMC_SDHCI_ESDHC_IMX=m
+CONFIG_MMC_SDHCI_EXTERNAL_DMA=y
+CONFIG_MMC_SDHCI_F_SDH30=m
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_IPROC=m
+CONFIG_MMC_SDHCI_MILBEAUT=m
+CONFIG_MMC_SDHCI_MSM=m
+CONFIG_MMC_SDHCI_NPCM=m
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_AT91=m
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+CONFIG_MMC_SDHCI_OF_ESDHC=m
+CONFIG_MMC_SDHCI_OF_MA35D1=m
+CONFIG_MMC_SDHCI_OF_SPARX5=m
+CONFIG_MMC_SDHCI_OMAP=m
+CONFIG_MMC_SDHCI_PCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_S3C_DMA=y
+CONFIG_MMC_SDHCI_S3C=m
+CONFIG_MMC_SDHCI_TEGRA=m
+CONFIG_MMC_SDHCI_XENON=m
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHI_INTERNAL_DMAC=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SPI=y
+CONFIG_MMC_STM32_SDMMC=y
+CONFIG_MMC_SUNXI=y
+CONFIG_MMC_TMIO_CORE=y
+CONFIG_MMC_USHC=m
+CONFIG_MMC_VIA_SDMMC=m
+CONFIG_MMC=y
+CONFIG_MMP_PDMA=m
+CONFIG_MMP_TDMA=m
+CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
+CONFIG_MMU_GATHER_TABLE_FREE=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULE_SIG_KEY="certs/signing_key.pem"
+CONFIG_MODULE_SIG_KEY_TYPE_RSA=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOST_CDEV=m
+CONFIG_MOST=m
+CONFIG_MOST_SND=m
+CONFIG_MOST_USB_HDM=m
+CONFIG_MOTORCOMM_PHY=y
+CONFIG_MPL115_I2C=m
+CONFIG_MPL115=m
+CONFIG_MPL115_SPI=m
+CONFIG_MPL3115=m
+CONFIG_MPRLS0025PA=m
+CONFIG_MPU3050_I2C=m
+CONFIG_MPU3050=m
+CONFIG_MQ_IOSCHED_KYBER=y
+CONFIG_MS5611_I2C=m
+CONFIG_MS5611=m
+CONFIG_MS5611_SPI=m
+CONFIG_MS5637=m
+CONFIG_MSA311=m
+CONFIG_MSHV_ROOT=m
+CONFIG_MSM_GCC_8916=m
+CONFIG_MSM_GCC_8917=m
+CONFIG_MSM_GCC_8953=m
+CONFIG_MSM_GCC_8976=m
+CONFIG_MSM_GCC_8994=y
+CONFIG_MSM_GCC_8996=y
+CONFIG_MSM_GCC_8998=y
+CONFIG_MSM_GPUCC_8998=y
+CONFIG_MSM_MMCC_8994=m
+CONFIG_MSM_MMCC_8996=y
+CONFIG_MSM_MMCC_8998=y
+CONFIG_MST_IRQ=y
+CONFIG_MT7601U=m
+CONFIG_MT7603E=m
+CONFIG_MT7615_COMMON=m
+CONFIG_MT7615E=m
+CONFIG_MT7622_WMAC=y
+CONFIG_MT7663S=m
+CONFIG_MT7663U=m
+CONFIG_MT7663_USB_SDIO_COMMON=m
+CONFIG_MT76_CONNAC_LIB=m
+CONFIG_MT76_CORE=m
+CONFIG_MT76_LEDS=y
+CONFIG_MT76_SDIO=m
+CONFIG_MT76_USB=m
+CONFIG_MT76x02_LIB=m
+CONFIG_MT76x02_USB=m
+CONFIG_MT76x0_COMMON=m
+CONFIG_MT76x0E=m
+CONFIG_MT76x0U=m
+CONFIG_MT76x2_COMMON=m
+CONFIG_MT76x2E=m
+CONFIG_MT76x2U=m
+CONFIG_MT7915E=m
+CONFIG_MT7921_COMMON=m
+CONFIG_MT7921E=m
+CONFIG_MT7921S=m
+CONFIG_MT7921U=m
+CONFIG_MT7925E=m
+CONFIG_MT7925U=m
+CONFIG_MT7986_WMAC=y
+CONFIG_MT798X_WMAC=y
+CONFIG_MT7996E=m
+CONFIG_MTD_ABSENT=m
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK2MTD=m
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_BRCM_U_BOOT=m
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_STAA=m
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_INTEL_DG=m
+CONFIG_MTD_INTEL_VR_NOR=m
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_LPDDR=m
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_MCHP23K256=m
+CONFIG_MTD_MCHP48L640=m
+CONFIG_MTD_MTDRAM=m
+CONFIG_MTD_NAND_BRCMNAND_BCM63XX=m
+CONFIG_MTD_NAND_BRCMNAND_BCMBCA=m
+CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=m
+CONFIG_MTD_NAND_BRCMNAND_IPROC=m
+CONFIG_MTD_NAND_BRCMNAND=m
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_DENALI_DT=m
+CONFIG_MTD_NAND_DENALI=m
+CONFIG_MTD_NAND_DENALI_PCI=m
+CONFIG_MTD_NAND_DISKONCHIP=m
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
+CONFIG_MTD_NAND_ECC_MEDIATEK=m
+CONFIG_MTD_NAND_ECC_MXIC=y
+CONFIG_MTD_NAND_ECC_SW_BCH=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_GPMI_NAND=m
+CONFIG_MTD_NAND_INTEL_LGM=m
+CONFIG_MTD_NAND_MARVELL=m
+CONFIG_MTD_NAND_MXC=m
+CONFIG_MTD_NAND_NANDSIM=m
+CONFIG_MTD_NAND_NUVOTON_MA35=m
+CONFIG_MTD_NAND_OMAP2=m
+CONFIG_MTD_NAND_OMAP_BCH_BUILD=m
+CONFIG_MTD_NAND_OMAP_BCH=y
+CONFIG_MTD_NAND_RENESAS=m
+CONFIG_MTD_NAND_ROCKCHIP=m
+CONFIG_MTD_NAND_STM32_FMC2=m
+CONFIG_MTD_NAND_SUNXI=m
+CONFIG_MTD_OF_PARTS_BCM4908=y
+CONFIG_MTD_OF_PARTS_LINKSYS_NS=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_ONENAND_2X_PROGRAM=y
+CONFIG_MTD_ONENAND_GENERIC=m
+CONFIG_MTD_ONENAND=m
+CONFIG_MTD_ONENAND_OTP=y
+CONFIG_MTD_OOPS=m
+CONFIG_MTD_PARSER_TRX=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PSTORE=m
+CONFIG_MTD_QCOMSMEM_PARTS=m
+CONFIG_MTD_QINFO_PROBE=m
+CONFIG_MTDRAM_ERASE_SIZE=128
+CONFIG_MTD_RAM=m
+CONFIG_MTDRAM_TOTAL_SIZE=4096
+CONFIG_MTD_RAW_NAND=m
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+CONFIG_MTD_REDBOOT_PARTS=m
+CONFIG_MTD_ROM=m
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_SPI_NOR_SWP_DISABLE=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SWAP=m
+CONFIG_MTD_TESTS=m
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_NVMEM=m
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI=y
+CONFIG_MTD=y
+CONFIG_MTK_ADSP_IPC=m
+CONFIG_MTK_ADSP_MBOX=m
+CONFIG_MTK_CMDQ=m
+CONFIG_MTK_CMDQ_MBOX=m
+CONFIG_MTK_CPUX_TIMER=y
+CONFIG_MTK_DEVAPC=m
+CONFIG_MTK_GPUEB_MBOX=m
+CONFIG_MTK_INFRACFG=y
+CONFIG_MTK_IOMMU=m
+CONFIG_MTK_LVTS_THERMAL=m
+CONFIG_MTK_MMSYS=m
+CONFIG_MTK_PMIC_WRAP=m
+CONFIG_MTK_REGULATOR_COUPLER=y
+CONFIG_MTK_SCP=m
+CONFIG_MTK_SCPSYS_PM_DOMAINS=y
+CONFIG_MTK_SCPSYS=y
+CONFIG_MTK_SMI=m
+CONFIG_MTK_SOCINFO=m
+CONFIG_MTK_SOC_THERMAL=m
+CONFIG_MTK_SVS=m
+CONFIG_MTK_T7XX=m
+CONFIG_MTK_THERMAL=m
+CONFIG_MTK_TIMER=y
+CONFIG_MULTIPLEXER=m
+CONFIG_MUSB_PIO_ONLY=y
+CONFIG_MVEBU_GICP=y
+CONFIG_MVEBU_ICU=y
+CONFIG_MVEBU_ODMI=y
+CONFIG_MVEBU_PIC=y
+CONFIG_MVEBU_SEI=y
+CONFIG_MV_XOR_V2=y
+CONFIG_MV_XOR=y
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_PCIE=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
+CONFIG_MWL8K=m
+CONFIG_MX3_IPU_IRQS=4
+CONFIG_MX3_IPU=y
+CONFIG_MXC4005=m
+CONFIG_MXC6255=m
+CONFIG_MXC_CLK_SCU=y
+CONFIG_MXC_CLK=y
+CONFIG_MXS_DMA=y
+CONFIG_NATIONAL_PHY=m
+CONFIG_NAU7802=m
+CONFIG_NCN26000_PHY=m
+CONFIG_NCT6694_WATCHDOG=m
+CONFIG_ND_BTT=m
+CONFIG_ND_CLAIM=y
+CONFIG_ND_PFN=m
+CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_NEED_SG_DMA_FLAGS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_9P_FD=m
+CONFIG_NET_9P_RDMA=m
+CONFIG_NET_9P_USBG=y
+CONFIG_NET_9P_VIRTIO=m
+CONFIG_NET_9P=y
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETCONSOLE_EXTENDED_LOG=y
+CONFIG_NETCONSOLE=m
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FC=y
+CONFIG_NET_IFE=m
+CONFIG_NETKIT=y
+CONFIG_NET_POLL_CONTROLLER=y
+CONFIG_NETPOLL=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_NET_TEAM_MODE_RANDOM=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NEW_LEDS=y
+CONFIG_NFC_DIGITAL=m
+CONFIG_NFC_FDP_I2C=m
+CONFIG_NFC_FDP=m
+CONFIG_NFC_HCI=m
+CONFIG_NFC=m
+CONFIG_NFC_MICROREAD_I2C=m
+CONFIG_NFC_MICROREAD=m
+CONFIG_NFC_MRVL_I2C=m
+CONFIG_NFC_MRVL=m
+CONFIG_NFC_MRVL_UART=m
+CONFIG_NFC_MRVL_USB=m
+CONFIG_NFC_NCI=m
+CONFIG_NFC_NCI_UART=m
+CONFIG_NFC_PN544_I2C=m
+CONFIG_NFC_PN544=m
+CONFIG_NFC_PORT100=m
+CONFIG_NFC_S3FWRN5_I2C=m
+CONFIG_NFC_S3FWRN5=m
+CONFIG_NFC_S3FWRN82_UART=m
+CONFIG_NFC_SHDLC=y
+CONFIG_NFC_ST95HF=m
+CONFIG_NFC_VIRTUAL_NCI=m
+CONFIG_NFTL=m
+CONFIG_NFTL_RW=y
+CONFIG_NITRO_ENCLAVES=m
+CONFIG_NLMON=m
+CONFIG_NOA1305=m
+CONFIG_NODES_SHIFT=2
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NO_HZ=y
+CONFIG_NOP_USB_XCEIV=m
+CONFIG_NORTEL_HERMES=m
+CONFIG_NOUVEAU_DEBUG=3
+CONFIG_NOUVEAU_DEBUG_DEFAULT=1
+CONFIG_NOUVEAU_PLATFORM_DRIVER=y
+CONFIG_NOZOMI=m
+CONFIG_NPCM7XX_KCS_IPMI_BMC=m
+CONFIG_NPCM7XX_TIMER=y
+CONFIG_NPCM7XX_WATCHDOG=m
+CONFIG_NPCM_ADC=m
+CONFIG_NR_CPUS=256
+CONFIG_NSM=m
+CONFIG_NTSYNC=m
+CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
+CONFIG_NUMA_BALANCING=y
+CONFIG_NUMA_KEEP_MEMINFO=y
+CONFIG_NUMA=y
+CONFIG_NVDIMM_DAX=y
+CONFIG_NVDIMM_PFN=y
+CONFIG_NVEC_PAZ00=m
+CONFIG_NVEC_POWER=m
+CONFIG_NVGRACE_GPU_VFIO_PCI=m
+CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
+CONFIG_NVIDIA_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m
+CONFIG_NVMEM_APPLE_EFUSES=m
+CONFIG_NVMEM_APPLE_SPMI=m
+CONFIG_NVMEM_BCM_OCOTP=y
+CONFIG_NVMEM_IMX_IIM=m
+CONFIG_NVMEM_IMX_OCOTP_ELE=m
+CONFIG_NVMEM_IMX_OCOTP=m
+CONFIG_NVMEM_IMX_OCOTP_SCU=m
+CONFIG_NVMEM_LAYERSCAPE_SFP=m
+CONFIG_NVMEM_LAYOUT_ONIE_TLV=m
+CONFIG_NVMEM_LAYOUT_SL28_VPD=m
+CONFIG_NVMEM_MESON_EFUSE=m
+CONFIG_NVMEM_MESON_MX_EFUSE=m
+CONFIG_NVMEM_MTK_EFUSE=m
+CONFIG_NVMEM_QCOM_QFPROM=m
+CONFIG_NVMEM_QCOM_SEC_QFPROM=m
+CONFIG_NVMEM_RMEM=m
+CONFIG_NVMEM_ROCKCHIP_EFUSE=y
+CONFIG_NVMEM_ROCKCHIP_OTP=y
+CONFIG_NVMEM_S32G_OCOTP=m
+CONFIG_NVMEM_SNVS_LPGPR=m
+CONFIG_NVMEM_SPMI_SDAM=m
+CONFIG_NVMEM_SPRD_EFUSE=m
+CONFIG_NVMEM_STM32_BSEC_OPTEE_TA=y
+CONFIG_NVMEM_STM32_ROMEM=m
+CONFIG_NVMEM_SUNXI_SID=m
+CONFIG_NVMEM_U_BOOT_ENV=m
+CONFIG_NVMEM_UNIPHIER_EFUSE=m
+CONFIG_NXP_C45_TJA11XX_PHY=m
+CONFIG_NXP_CBTX_PHY=m
+CONFIG_OBJAGG=m
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NUMA=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_PMEM=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OF_RESOLVE=y
+CONFIG_OF=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OLPC_XO175_EC=m
+CONFIG_OLPC_XO175=y
+CONFIG_OMAP2PLUS_MBOX=m
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_GPMC=m
+CONFIG_OMAP_MBOX_KFIFO_SIZE=256
+CONFIG_OPEN_DICE=m
+CONFIG_OPT3001=m
+CONFIG_OPT4001=m
+CONFIG_OPT4060=m
+CONFIG_OPTEE=y
+CONFIG_ORINOCO_USB=m
+CONFIG_OVPN=m
+CONFIG_OWL_TIMER=y
+CONFIG_P54_COMMON=m
+CONFIG_P54_LEDS=y
+CONFIG_P54_USB=m
+CONFIG_PA12203001=m
+CONFIG_PAC1921=m
+CONFIG_PAC1934=m
+CONFIG_PACKING=y
+CONFIG_PAGE_BLOCK_MAX_ORDER=10
+CONFIG_PAGE_BLOCK_ORDER=10
+CONFIG_PAGE_POOL_STATS=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_VERSION=125
+CONFIG_PANEL=m
+CONFIG_PANEL_PARPORT=0
+CONFIG_PANEL_PROFILE=5
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PARMAN=m
+CONFIG_PARPORT_1284=y
+CONFIG_PARPORT=m
+CONFIG_PARPORT_NOT_PC=y
+CONFIG_PARPORT_PANEL=m
+CONFIG_PARPORT_PC_FIFO=y
+CONFIG_PARPORT_PC=m
+CONFIG_PARPORT_SERIAL=m
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PATA_ACPI=m
+CONFIG_PATA_OF_PLATFORM=m
+CONFIG_PATA_PLATFORM=m
+CONFIG_PATA_TIMINGS=y
+CONFIG_PC300TOO=m
+CONFIG_PCC=y
+CONFIG_PCI200SYN=m
+CONFIG_PCI_AARDVARK=y
+CONFIG_PCI_ATMEL=m
+CONFIG_PCI_ATS=y
+CONFIG_PCI_BRIDGE_EMUL=y
+CONFIG_PCI_DOE=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_DYNAMIC_OF_NODES=y
+CONFIG_PCIEAER_CXL=y
+CONFIG_PCIEAER=y
+CONFIG_PCIE_ALTERA=m
+CONFIG_PCIE_ALTERA_MSI=m
+CONFIG_PCIE_AMD_MDB=y
+CONFIG_PCIE_APPLE=m
+CONFIG_PCIE_ARMADA_8K=y
+CONFIG_PCIEASPM_DEFAULT=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIE_BRCMSTB=m
+CONFIG_PCIE_BUS_DEFAULT=y
+CONFIG_PCIE_CADENCE_HOST=y
+CONFIG_PCIE_CADENCE=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_HISI_ERR=y
+CONFIG_PCIE_IPROC_MSI=y
+CONFIG_PCIE_IPROC_PLATFORM=y
+CONFIG_PCIE_IPROC=y
+CONFIG_PCIE_KEEMBAY_HOST=y
+CONFIG_PCIE_KEEMBAY=y
+CONFIG_PCIE_KIRIN=y
+CONFIG_PCIE_MEDIATEK_GEN3=m
+CONFIG_PCIE_MEDIATEK=m
+CONFIG_PCIE_MICROCHIP_HOST=y
+CONFIG_PCIE_PME=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_QCOM=y
+CONFIG_PCIE_RCAR_GEN4_HOST=m
+CONFIG_PCIE_RCAR_HOST=y
+CONFIG_PCIE_ROCKCHIP_DW_EP=y
+CONFIG_PCIE_ROCKCHIP_DW_HOST=y
+CONFIG_PCIE_ROCKCHIP_HOST=m
+CONFIG_PCIE_ROCKCHIP=y
+CONFIG_PCIE_SG2042_HOST=m
+CONFIG_PCIE_SOPHGO_DW=y
+CONFIG_PCIE_STM32_HOST=m
+CONFIG_PCIE_XILINX_CPM=y
+CONFIG_PCIE_XILINX_DMA_PL=y
+CONFIG_PCIE_XILINX=y
+CONFIG_PCI_EXYNOS=m
+CONFIG_PCI_HISI=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_HOST_THUNDER_ECAM=y
+CONFIG_PCI_HOST_THUNDER_PEM=y
+CONFIG_PCI_HYPERV_INTERFACE=m
+CONFIG_PCI_HYPERV=m
+CONFIG_PCI_IMX6_HOST=y
+CONFIG_PCI_IMX6=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_J721E_HOST=y
+CONFIG_PCI_J721E=y
+CONFIG_PCI_LABEL=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCI_TEGRA=y
+CONFIG_PCI_XGENE_MSI=y
+CONFIG_PCI_XGENE=y
+CONFIG_PCS_LYNX=m
+CONFIG_PCS_MTK_LYNXI=m
+CONFIG_PCS_XPCS=m
+CONFIG_PDC_ADMA=m
+CONFIG_PDS_VFIO_PCI=m
+CONFIG_PECI_CPU=m
+CONFIG_PECI=m
+CONFIG_PECI_NPCM=m
+CONFIG_PERSISTENT_KEYRINGS=y
+CONFIG_PER_VMA_LOCK=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHY_AIROHA_PCIE=m
+CONFIG_PHY_BCM_SR_PCIE=y
+CONFIG_PHY_BCM_SR_USB=y
+CONFIG_PHY_BRCM_SATA=y
+CONFIG_PHY_BRCM_USB=m
+CONFIG_PHY_CADENCE_DPHY_RX=m
+CONFIG_PHY_CAN_TRANSCEIVER=m
+CONFIG_PHY_CPCAP_USB=m
+CONFIG_PHY_EXYNOS5_USBDRD=m
+CONFIG_PHY_EXYNOS_DP_VIDEO=y
+CONFIG_PHY_EXYNOS_MIPI_VIDEO=y
+CONFIG_PHY_FSL_IMX8M_PCIE=m
+CONFIG_PHY_FSL_IMX8MQ_USB=m
+CONFIG_PHY_FSL_IMX8QM_HSIO=m
+CONFIG_PHY_FSL_LYNX_28G=m
+CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY=m
+CONFIG_PHY_HI3670_PCIE=m
+CONFIG_PHY_HI3670_USB=m
+CONFIG_PHY_HI6220_USB=y
+CONFIG_PHY_INTEL_KEEMBAY_USB=m
+CONFIG_PHY_LAN966X_SERDES=m
+CONFIG_PHY_MA35_USB=m
+CONFIG_PHY_MESON8B_USB2=m
+CONFIG_PHY_MESON_AXG_MIPI_DPHY=m
+CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
+CONFIG_PHY_MESON_AXG_PCIE=y
+CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=m
+CONFIG_PHY_MESON_G12A_USB2=y
+CONFIG_PHY_MESON_G12A_USB3_PCIE=y
+CONFIG_PHY_MESON_GXL_USB2=y
+CONFIG_PHY_MIXEL_LVDS_PHY=m
+CONFIG_PHY_MTK_DP=m
+CONFIG_PHY_MTK_HDMI=m
+CONFIG_PHY_MTK_MIPI_CSI_0_5=m
+CONFIG_PHY_MTK_MIPI_DSI=m
+CONFIG_PHY_MTK_PCIE=m
+CONFIG_PHY_MTK_UFS=m
+CONFIG_PHY_MTK_XFI_TPHY=m
+CONFIG_PHY_MVEBU_A3700_COMPHY=y
+CONFIG_PHY_MVEBU_A3700_UTMI=y
+CONFIG_PHY_MVEBU_CP110_COMPHY=y
+CONFIG_PHY_MVEBU_CP110_UTMI=m
+CONFIG_PHY_NS2_PCIE=m
+CONFIG_PHY_NS2_USB_DRD=y
+CONFIG_PHY_PXA_USB=m
+CONFIG_PHY_QCOM_APQ8064_SATA=m
+CONFIG_PHY_QCOM_EDP=m
+CONFIG_PHY_QCOM_EUSB2_REPEATER=m
+CONFIG_PHY_QCOM_IPQ806X_SATA=m
+CONFIG_PHY_QCOM_IPQ806X_USB=m
+CONFIG_PHY_QCOM_M31_EUSB=m
+CONFIG_PHY_QCOM_M31_USB=m
+CONFIG_PHY_QCOM_QMP_COMBO=m
+CONFIG_PHY_QCOM_QMP=m
+CONFIG_PHY_QCOM_QMP_PCIE_8996=m
+CONFIG_PHY_QCOM_QMP_PCIE=m
+CONFIG_PHY_QCOM_QMP_UFS=m
+CONFIG_PHY_QCOM_QMP_USB_LEGACY=m
+CONFIG_PHY_QCOM_QMP_USB=m
+CONFIG_PHY_QCOM_QUSB2=m
+CONFIG_PHY_QCOM_SGMII_ETH=m
+CONFIG_PHY_QCOM_SNPS_EUSB2=m
+CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP=y
+CONFIG_PHY_QCOM_USB_HSIC=m
+CONFIG_PHY_QCOM_USB_HS=y
+CONFIG_PHY_R8A779F0_ETHERNET_SERDES=m
+CONFIG_PHY_RCAR_GEN3_USB2=y
+CONFIG_PHY_RCAR_GEN3_USB3=m
+CONFIG_PHY_ROCKCHIP_DPHY_RX0=m
+CONFIG_PHY_ROCKCHIP_DP=y
+CONFIG_PHY_ROCKCHIP_EMMC=y
+CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m
+CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m
+CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
+CONFIG_PHY_ROCKCHIP_PCIE=m
+CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY=m
+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=m
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+CONFIG_PHY_ROCKCHIP_TYPEC=m
+CONFIG_PHY_ROCKCHIP_USBDP=m
+CONFIG_PHY_ROCKCHIP_USB=y
+CONFIG_PHY_RTK_RTD_USB2PHY=m
+CONFIG_PHY_RTK_RTD_USB3PHY=m
+CONFIG_PHY_SAMSUNG_UFS=m
+CONFIG_PHY_SAMSUNG_USB2=m
+CONFIG_PHY_SOPHGO_CV1800_USB2=m
+CONFIG_PHY_SPARX5_SERDES=m
+CONFIG_PHY_STM32_USBPHYC=m
+CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_SUN50I_USB3=m
+CONFIG_PHY_SUN6I_MIPI_DPHY=m
+CONFIG_PHY_TEGRA_XUSB=y
+CONFIG_PHY_UNIPHIER_AHCI=m
+CONFIG_PHY_XILINX_ZYNQMP=m
+CONFIG_PI433=m
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_AC5=y
+CONFIG_PINCTRL_AMDISP=m
+CONFIG_PINCTRL_AMD=y
+CONFIG_PINCTRL_AMLOGIC_A4=y
+CONFIG_PINCTRL_AMLOGIC_C3=m
+CONFIG_PINCTRL_AMLOGIC_T7=m
+CONFIG_PINCTRL_APPLE_GPIO=m
+CONFIG_PINCTRL_ARMADA_37XX=y
+CONFIG_PINCTRL_ARMADA_AP806=y
+CONFIG_PINCTRL_ARMADA_CP110=y
+CONFIG_PINCTRL_AS3722=m
+CONFIG_PINCTRL_AW9523=m
+CONFIG_PINCTRL_AXP209=m
+CONFIG_PINCTRL_BCM2712=m
+CONFIG_PINCTRL_BCM2835=y
+CONFIG_PINCTRL_BCM4908=m
+CONFIG_PINCTRL_BERLIN_BG4CT=y
+CONFIG_PINCTRL_BERLIN=y
+CONFIG_PINCTRL_BM1880=y
+CONFIG_PINCTRL_BRCMSTB=m
+CONFIG_PINCTRL_CS42L43=m
+CONFIG_PINCTRL_CS47L35=y
+CONFIG_PINCTRL_CS47L85=y
+CONFIG_PINCTRL_CS47L90=y
+CONFIG_PINCTRL_CY8C95X0=m
+CONFIG_PINCTRL_EXYNOS_ARM64=y
+CONFIG_PINCTRL_EXYNOS=y
+CONFIG_PINCTRL_GLYMUR=m
+CONFIG_PINCTRL_IMX8MM=y
+CONFIG_PINCTRL_IMX8MN=y
+CONFIG_PINCTRL_IMX8MP=y
+CONFIG_PINCTRL_IMX8MQ=y
+CONFIG_PINCTRL_IMX8QM=y
+CONFIG_PINCTRL_IMX8QXP=y
+CONFIG_PINCTRL_IMX8ULP=m
+CONFIG_PINCTRL_IMX91=m
+CONFIG_PINCTRL_IMX93=m
+CONFIG_PINCTRL_IMXRT1050=y
+CONFIG_PINCTRL_IMXRT1170=y
+CONFIG_PINCTRL_IMX_SCMI=m
+CONFIG_PINCTRL_IMX_SCU=y
+CONFIG_PINCTRL_IMX=y
+CONFIG_PINCTRL_IPQ5018=m
+CONFIG_PINCTRL_IPQ5332=m
+CONFIG_PINCTRL_IPQ8074=m
+CONFIG_PINCTRL_IPQ9574=m
+CONFIG_PINCTRL_IPROC_GPIO=y
+CONFIG_PINCTRL_KEEMBAY=m
+CONFIG_PINCTRL_LPASS_LPI=m
+CONFIG_PINCTRL_MA35D1=y
+CONFIG_PINCTRL_MADERA=m
+CONFIG_PINCTRL_MAX7360=m
+CONFIG_PINCTRL_MAX77620=m
+CONFIG_PINCTRL_MCP23S08_I2C=m
+CONFIG_PINCTRL_MCP23S08=m
+CONFIG_PINCTRL_MCP23S08_SPI=m
+CONFIG_PINCTRL_MDM9607=m
+CONFIG_PINCTRL_MESON8_PMX=y
+CONFIG_PINCTRL_MESON_A1=y
+CONFIG_PINCTRL_MESON_AXG_PMX=y
+CONFIG_PINCTRL_MESON_AXG=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_PINCTRL_MESON_GXBB=y
+CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_PINCTRL_MESON_S4=m
+CONFIG_PINCTRL_MESON=y
+CONFIG_PINCTRL_MICROCHIP_SGPIO=y
+CONFIG_PINCTRL_MILOS=m
+CONFIG_PINCTRL_MSM8916=m
+CONFIG_PINCTRL_MSM8917=m
+CONFIG_PINCTRL_MSM8953=m
+CONFIG_PINCTRL_MSM8976=m
+CONFIG_PINCTRL_MSM8994=m
+CONFIG_PINCTRL_MSM8996=m
+CONFIG_PINCTRL_MSM=y
+CONFIG_PINCTRL_MT2712=y
+CONFIG_PINCTRL_MT6765=y
+CONFIG_PINCTRL_MT6779=m
+CONFIG_PINCTRL_MT6795=y
+CONFIG_PINCTRL_MT6797=y
+CONFIG_PINCTRL_MT7622=y
+CONFIG_PINCTRL_MT7981=y
+CONFIG_PINCTRL_MT7986=y
+CONFIG_PINCTRL_MT7988=y
+CONFIG_PINCTRL_MT8167=y
+CONFIG_PINCTRL_MT8173=y
+CONFIG_PINCTRL_MT8183=y
+CONFIG_PINCTRL_MT8186=y
+CONFIG_PINCTRL_MT8188=y
+CONFIG_PINCTRL_MT8189=y
+CONFIG_PINCTRL_MT8192=y
+CONFIG_PINCTRL_MT8195=y
+CONFIG_PINCTRL_MT8365=y
+CONFIG_PINCTRL_MT8516=y
+CONFIG_PINCTRL_MTK_MOORE=y
+CONFIG_PINCTRL_MTK_PARIS=y
+CONFIG_PINCTRL_MTK_V2=y
+CONFIG_PINCTRL_MTK=y
+CONFIG_PINCTRL_MVEBU=y
+CONFIG_PINCTRL_NPCM8XX=m
+CONFIG_PINCTRL_NS2_MUX=y
+CONFIG_PINCTRL_PEF2256=m
+CONFIG_PINCTRL_PFC_R8A774A1=y
+CONFIG_PINCTRL_PFC_R8A774B1=y
+CONFIG_PINCTRL_PFC_R8A774C0=y
+CONFIG_PINCTRL_PFC_R8A774E1=y
+CONFIG_PINCTRL_PFC_R8A77951=y
+CONFIG_PINCTRL_PFC_R8A77960=y
+CONFIG_PINCTRL_PFC_R8A77961=y
+CONFIG_PINCTRL_PFC_R8A77965=y
+CONFIG_PINCTRL_PFC_R8A77970=y
+CONFIG_PINCTRL_PFC_R8A77980=y
+CONFIG_PINCTRL_PFC_R8A77990=y
+CONFIG_PINCTRL_PFC_R8A77995=y
+CONFIG_PINCTRL_PFC_R8A779A0=y
+CONFIG_PINCTRL_PFC_R8A779F0=y
+CONFIG_PINCTRL_PFC_R8A779G0=y
+CONFIG_PINCTRL_PFC_R8A779H0=y
+CONFIG_PINCTRL_QCM2290=m
+CONFIG_PINCTRL_QCOM_SPMI_PMIC=m
+CONFIG_PINCTRL_QCOM_SSBI_PMIC=m
+CONFIG_PINCTRL_QDF2XXX=m
+CONFIG_PINCTRL_QDU1000=m
+CONFIG_PINCTRL_RENESAS=y
+CONFIG_PINCTRL_RK805=y
+CONFIG_PINCTRL_ROCKCHIP=y
+CONFIG_PINCTRL_RP1=m
+CONFIG_PINCTRL_RTD1315E=m
+CONFIG_PINCTRL_RTD1319D=m
+CONFIG_PINCTRL_RTD1619B=m
+CONFIG_PINCTRL_RTD=m
+CONFIG_PINCTRL_RZG2L=y
+CONFIG_PINCTRL_RZV2M=y
+CONFIG_PINCTRL_S32CC=y
+CONFIG_PINCTRL_S32G2=y
+CONFIG_PINCTRL_SA8775P=m
+CONFIG_PINCTRL_SAMSUNG=y
+CONFIG_PINCTRL_SC7280_LPASS_LPI=m
+CONFIG_PINCTRL_SC7280=m
+CONFIG_PINCTRL_SC8180X=m
+CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
+CONFIG_PINCTRL_SC8280XP=m
+CONFIG_PINCTRL_SCMI=m
+CONFIG_PINCTRL_SDM660_LPASS_LPI=m
+CONFIG_PINCTRL_SDM670=m
+CONFIG_PINCTRL_SDX75=m
+CONFIG_PINCTRL_SH_PFC=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_SM4250_LPASS_LPI=m
+CONFIG_PINCTRL_SM4450=m
+CONFIG_PINCTRL_SM6115_LPASS_LPI=m
+CONFIG_PINCTRL_SM6115=m
+CONFIG_PINCTRL_SM6125=m
+CONFIG_PINCTRL_SM6350=m
+CONFIG_PINCTRL_SM6375=m
+CONFIG_PINCTRL_SM7150=m
+CONFIG_PINCTRL_SM8250_LPASS_LPI=m
+CONFIG_PINCTRL_SM8350_LPASS_LPI=m
+CONFIG_PINCTRL_SM8350=m
+CONFIG_PINCTRL_SM8450_LPASS_LPI=m
+CONFIG_PINCTRL_SM8450=m
+CONFIG_PINCTRL_SM8550_LPASS_LPI=m
+CONFIG_PINCTRL_SM8550=m
+CONFIG_PINCTRL_SM8650_LPASS_LPI=m
+CONFIG_PINCTRL_SM8650=m
+CONFIG_PINCTRL_SOPHGO_CV1800B=m
+CONFIG_PINCTRL_SOPHGO_CV1812H=m
+CONFIG_PINCTRL_SOPHGO_SG2000=m
+CONFIG_PINCTRL_SOPHGO_SG2002=m
+CONFIG_PINCTRL_SOPHGO_SG2042=m
+CONFIG_PINCTRL_SOPHGO_SG2044=m
+CONFIG_PINCTRL_SPRD_SC9860=y
+CONFIG_PINCTRL_SPRD=y
+CONFIG_PINCTRL_STM32_HDP=m
+CONFIG_PINCTRL_STM32MP257=y
+CONFIG_PINCTRL_STM32=y
+CONFIG_PINCTRL_SUN20I_D1=y
+CONFIG_PINCTRL_SUN50I_A100_R=y
+CONFIG_PINCTRL_SUN50I_A100=y
+CONFIG_PINCTRL_SUN50I_A64_R=y
+CONFIG_PINCTRL_SUN50I_A64=y
+CONFIG_PINCTRL_SUN50I_H5=y
+CONFIG_PINCTRL_SUN50I_H616_R=y
+CONFIG_PINCTRL_SUN50I_H616=y
+CONFIG_PINCTRL_SUN50I_H6_R=y
+CONFIG_PINCTRL_SUN50I_H6=y
+CONFIG_PINCTRL_SUN55I_A523_R=y
+CONFIG_PINCTRL_SUN55I_A523=y
+CONFIG_PINCTRL_SUN8I_H3_R=y
+CONFIG_PINCTRL_SUNXI=y
+CONFIG_PINCTRL_SX150X=y
+CONFIG_PINCTRL_TEGRA124=y
+CONFIG_PINCTRL_TEGRA194=y
+CONFIG_PINCTRL_TEGRA210=y
+CONFIG_PINCTRL_TEGRA234=y
+CONFIG_PINCTRL_TEGRA_XUSB=y
+CONFIG_PINCTRL_TEGRA=y
+CONFIG_PINCTRL_TMPV7700=y
+CONFIG_PINCTRL_TPS6594=m
+CONFIG_PINCTRL_UNIPHIER_LD11=y
+CONFIG_PINCTRL_UNIPHIER_LD20=y
+CONFIG_PINCTRL_UNIPHIER_NX1=y
+CONFIG_PINCTRL_UNIPHIER_PXS3=y
+CONFIG_PINCTRL_UNIPHIER=y
+CONFIG_PINCTRL_VISCONTI=y
+CONFIG_PINCTRL_X1E80100=m
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ZYNQMP=m
+CONFIG_PING=m
+CONFIG_PINMUX=y
+CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
+CONFIG_PL320_MBOX=y
+CONFIG_PL330_DMA=y
+CONFIG_PLATFORM_MHU=y
+CONFIG_PLFXLC=m
+CONFIG_PLIP=m
+CONFIG_PLX_HERMES=m
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_OPP=y
+CONFIG_PMS7003=m
+CONFIG_PM_STD_PARTITION=""
+CONFIG_PNPACPI=y
+CONFIG_PNP=y
+CONFIG_POLYNOMIAL=m
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWERCAP=y
+CONFIG_POWER_RESET_ATC260X=m
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_HISI=y
+CONFIG_POWER_RESET_LINKSTATION=m
+CONFIG_POWER_RESET_MACSMC=m
+CONFIG_POWER_RESET_MSM=y
+CONFIG_POWER_RESET_OCELOT_RESET=y
+CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF=y
+CONFIG_POWER_RESET_QCOM_PON=m
+CONFIG_POWER_RESET_REGULATOR=y
+CONFIG_POWER_RESET_RESTART=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPDEV=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOATM=m
+CONFIG_PPPOE_HASH_BITS=4
+CONFIG_PPPOE_HASH_BITS_4=y
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PPS_CLIENT_PARPORT=m
+CONFIG_PPS=y
+CONFIG_PPTP=m
+CONFIG_PREEMPT_BUILD=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_PREEMPT_DYNAMIC=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_PREEMPT_RCU=y
+CONFIG_PREEMPT=y
+CONFIG_PRINTER=m
+CONFIG_PRISM2_USB=m
+CONFIG_PRU_REMOTEPROC=m
+CONFIG_PSAMPLE=m
+CONFIG_PSE_CONTROLLER=y
+CONFIG_PSE_PD692X0=m
+CONFIG_PSE_REGULATOR=m
+CONFIG_PSE_SI3474=m
+CONFIG_PSE_TPS23881=m
+CONFIG_PSI=y
+CONFIG_PTDUMP_CORE=y
+CONFIG_PTP_1588_CLOCK_DTE=y
+CONFIG_PTP_1588_CLOCK_FC3W=m
+CONFIG_PTP_1588_CLOCK_INES=m
+CONFIG_PTP_1588_CLOCK_KVM=m
+CONFIG_PTP_1588_CLOCK_MOCK=m
+CONFIG_PTP_1588_CLOCK_OCP=m
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PTP_1588_CLOCK_QORIQ=m
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_NETC_V4_TIMER=m
+CONFIG_PVPANIC_MMIO=m
+CONFIG_PVPANIC_PCI=m
+CONFIG_PVPANIC=y
+CONFIG_PWC_RZV2M=y
+CONFIG_PWM_ADP5585=m
+CONFIG_PWM_APPLE=m
+CONFIG_PWM_ATMEL_TCB=m
+CONFIG_PWM_AXI_PWMGEN=m
+CONFIG_PWM_BCM2835=m
+CONFIG_PWM_BCM_IPROC=y
+CONFIG_PWM_CLK=m
+CONFIG_PWM_CROS_EC=m
+CONFIG_PWM_DWC=m
+CONFIG_PWM_GPIO=m
+CONFIG_PWM_IMX1=m
+CONFIG_PWM_IMX27=m
+CONFIG_PWM_IMX_TPM=m
+CONFIG_PWM_KEEMBAY=m
+CONFIG_PWM_MAX7360=m
+CONFIG_PWM_MESON=m
+CONFIG_PWM_NTXEC=m
+CONFIG_PWM_OMAP_DMTIMER=m
+CONFIG_PWM_PROVIDE_GPIO=y
+CONFIG_PWM_PXA=m
+CONFIG_PWM_RASPBERRYPI_POE=m
+CONFIG_PWM_RCAR=m
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_PWM_RZ_MTU3=m
+CONFIG_PWM_SAMSUNG=y
+CONFIG_PWM_SL28CPLD=m
+CONFIG_PWM_SOPHGO_SG2042=m
+CONFIG_PWM_STM32_LP=m
+CONFIG_PWM_STM32=m
+CONFIG_PWM_SUN4I=m
+CONFIG_PWM_SYSFS=y
+CONFIG_PWM_TEGRA=m
+CONFIG_PWM_VISCONTI=m
+CONFIG_PWM_XILINX=m
+CONFIG_PWM=y
+CONFIG_PWRSEQ_EMMC=y
+CONFIG_PWRSEQ_SD8787=m
+CONFIG_PWRSEQ_SIMPLE=y
+CONFIG_PXA1908_PM_DOMAINS=m
+CONFIG_QAT_VFIO_PCI=m
+CONFIG_QCA807X_PHY=m
+CONFIG_QCA808X_PHY=m
+CONFIG_QCA83XX_PHY=m
+CONFIG_QCM_DISPCC_2290=m
+CONFIG_QCM_GCC_2290=m
+CONFIG_QCOM_A53PLL=y
+CONFIG_QCOM_A7PLL=m
+CONFIG_QCOM_AOSS_QMP=m
+CONFIG_QCOM_APCS_IPC=m
+CONFIG_QCOM_APR=m
+CONFIG_QCOM_BAM_DMA=y
+CONFIG_QCOM_BAM_DMUX=m
+CONFIG_QCOM_CLK_APCC_MSM8996=m
+CONFIG_QCOM_CLK_APCS_MSM8916=m
+CONFIG_QCOM_CLK_RPM=m
+CONFIG_QCOM_CLK_SMD_RPM=y
+CONFIG_QCOM_COINCELL=m
+CONFIG_QCOM_COMMAND_DB=y
+CONFIG_QCOM_CPR=m
+CONFIG_QCOM_CPUCP_MBOX=m
+CONFIG_QCOM_EBI2=y
+CONFIG_QCOM_FALKOR_ERRATUM_1003=y
+CONFIG_QCOM_FALKOR_ERRATUM_1009=y
+CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
+CONFIG_QCOM_FASTRPC=m
+CONFIG_QCOM_GDSC=y
+CONFIG_QCOM_GENI_SE=m
+CONFIG_QCOM_GPI_DMA=m
+CONFIG_QCOM_GSBI=m
+CONFIG_QCOM_HIDMA_MGMT=y
+CONFIG_QCOM_HIDMA=y
+CONFIG_QCOM_ICC_BWMON=m
+CONFIG_QCOM_INLINE_CRYPTO_ENGINE=m
+CONFIG_QCOM_IOMMU=y
+CONFIG_QCOM_IPCC=m
+CONFIG_QCOM_KRYO_L2_ACCESSORS=y
+CONFIG_QCOM_LLCC=m
+CONFIG_QCOM_LMH=m
+CONFIG_QCOM_MDT_LOADER=m
+CONFIG_QCOM_MPM=m
+CONFIG_QCOM_OCMEM=m
+CONFIG_QCOM_PBS=m
+CONFIG_QCOM_PDR_HELPERS=m
+CONFIG_QCOM_PIL_INFO=m
+CONFIG_QCOM_PMIC_GLINK=m
+CONFIG_QCOM_Q6V5_ADSP=m
+CONFIG_QCOM_Q6V5_COMMON=m
+CONFIG_QCOM_Q6V5_MSS=m
+CONFIG_QCOM_Q6V5_PAS=m
+CONFIG_QCOM_Q6V5_WCSS=m
+CONFIG_QCOM_QDF2400_ERRATUM_0065=y
+CONFIG_QCOM_QMI_HELPERS=m
+CONFIG_QCOM_QSEECOM_UEFISECAPP=y
+CONFIG_QCOM_QSEECOM=y
+CONFIG_QCOM_RAMP_CTRL=m
+CONFIG_QCOM_RMTFS_MEM=m
+CONFIG_QCOM_RPMCC=y
+CONFIG_QCOM_RPMH=m
+CONFIG_QCOM_RPMHPD=m
+CONFIG_QCOM_RPM_MASTER_STATS=m
+CONFIG_QCOM_RPMPD=m
+CONFIG_QCOM_RPROC_COMMON=m
+CONFIG_QCOM_SCM=y
+CONFIG_QCOM_SMD_RPM=y
+CONFIG_QCOM_SMEM_STATE=y
+CONFIG_QCOM_SMEM=y
+CONFIG_QCOM_SMP2P=y
+CONFIG_QCOM_SMSM=y
+CONFIG_QCOM_SOCINFO=m
+CONFIG_QCOM_SPMI_ADC5=m
+CONFIG_QCOM_SPMI_ADC_TM5=m
+CONFIG_QCOM_SPMI_IADC=m
+CONFIG_QCOM_SPMI_RRADC=m
+CONFIG_QCOM_SPMI_TEMP_ALARM=m
+CONFIG_QCOM_SPMI_VADC=m
+CONFIG_QCOM_SPM=m
+CONFIG_QCOM_SSC_BLOCK_BUS=y
+CONFIG_QCOM_STATS=m
+CONFIG_QCOM_SYSMON=m
+CONFIG_QCOMTEE=m
+CONFIG_QCOM_TSENS=m
+CONFIG_QCOM_TZMEM_MODE_GENERIC=y
+CONFIG_QCOM_VADC_COMMON=m
+CONFIG_QCOM_WCNSS_CTRL=m
+CONFIG_QCOM_WCNSS_PIL=m
+CONFIG_QCOM_WDT=m
+CONFIG_QCS_CAMCC_615=m
+CONFIG_QCS_DISPCC_615=m
+CONFIG_QCS_GPUCC_615=m
+CONFIG_QCS_VIDEOCC_615=m
+CONFIG_QDU_ECPRICC_1000=m
+CONFIG_QDU_GCC_1000=m
+CONFIG_QE_TDM=y
+CONFIG_QLGE=m
+CONFIG_QORIQ_CPUFREQ=m
+CONFIG_QPIC_SNAND=m
+CONFIG_QTNFMAC=m
+CONFIG_QTNFMAC_PCIE=m
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUICC_ENGINE=y
+CONFIG_R8712U=m
+CONFIG_RADIO_ADAPTERS=m
+CONFIG_RADIO_MAXIRADIO=m
+CONFIG_RADIO_SHARK2=m
+CONFIG_RADIO_SHARK=m
+CONFIG_RADIO_TEA575X=m
+CONFIG_RADIO_TEA5764=m
+CONFIG_RADIO_WL128X=m
+CONFIG_RAID6_PQ=m
+CONFIG_RAID_ATTRS=m
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y
+CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
+CONFIG_RAPIDIO_DISC_TIMEOUT=30
+CONFIG_RAPIDIO=m
+CONFIG_RASPBERRYPI_FIRMWARE=y
+CONFIG_RASPBERRYPI_POWER=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCAR_DMAC=y
+CONFIG_RCAR_GEN3_THERMAL=y
+CONFIG_RCAR_REMOTEPROC=m
+CONFIG_RCAR_THERMAL=m
+CONFIG_RC_ATI_REMOTE=m
+CONFIG_RC_CORE=m
+CONFIG_RC_DECODERS=y
+CONFIG_RC_DEVICES=y
+CONFIG_RC_MAP=m
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_LAZY=y
+CONFIG_RD_BZIP2=y
+CONFIG_RDMA_RXE=m
+CONFIG_RDMA_SIW=m
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_REALTEK_PHY=m
+CONFIG_REBOOT_MODE=y
+CONFIG_REED_SOLOMON_DEC16=y
+CONFIG_REED_SOLOMON=m
+CONFIG_REGMAP_AC97=m
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_I3C=m
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SOUNDWIRE=m
+CONFIG_REGMAP_SOUNDWIRE_MBQ=m
+CONFIG_REGMAP_SPI_AVMM=m
+CONFIG_REGMAP_SPI=y
+CONFIG_REGMAP_SPMI=y
+CONFIG_REGULATOR_88PM886=m
+CONFIG_REGULATOR_ADP5055=m
+CONFIG_REGULATOR_ARM_SCMI=m
+CONFIG_REGULATOR_AS3722=m
+CONFIG_REGULATOR_ATC260X=m
+CONFIG_REGULATOR_AW37503=m
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_BD957XMUF=m
+CONFIG_REGULATOR_BD96801=m
+CONFIG_REGULATOR_BQ257XX=m
+CONFIG_REGULATOR_CROS_EC=m
+CONFIG_REGULATOR_DA9121=m
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FAN53880=m
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_HI6421=m
+CONFIG_REGULATOR_HI6421V530=y
+CONFIG_REGULATOR_HI6421V600=m
+CONFIG_REGULATOR_HI655X=y
+CONFIG_REGULATOR_MAX20086=m
+CONFIG_REGULATOR_MAX20411=m
+CONFIG_REGULATOR_MAX5970=m
+CONFIG_REGULATOR_MAX77503=m
+CONFIG_REGULATOR_MAX77541=m
+CONFIG_REGULATOR_MAX77620=y
+CONFIG_REGULATOR_MAX77838=m
+CONFIG_REGULATOR_MAX77857=m
+CONFIG_REGULATOR_MAX8893=m
+CONFIG_REGULATOR_MP8859=y
+CONFIG_REGULATOR_MT6311=m
+CONFIG_REGULATOR_MT6315=m
+CONFIG_REGULATOR_MT6370=m
+CONFIG_REGULATOR_NETLINK_EVENTS=y
+CONFIG_REGULATOR_PCA9450=m
+CONFIG_REGULATOR_PF0900=m
+CONFIG_REGULATOR_PF530X=m
+CONFIG_REGULATOR_PF8X00=m
+CONFIG_REGULATOR_PF9453=m
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_QCOM_LABIBB=m
+CONFIG_REGULATOR_QCOM_PM8008=m
+CONFIG_REGULATOR_QCOM_REFGEN=m
+CONFIG_REGULATOR_QCOM_RPM=m
+CONFIG_REGULATOR_QCOM_SMD_RPM=y
+CONFIG_REGULATOR_QCOM_SPMI=y
+CONFIG_REGULATOR_QCOM_USB_VBUS=m
+CONFIG_REGULATOR_RAA215300=m
+CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
+CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2=m
+CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR_RT4801=m
+CONFIG_REGULATOR_RT4803=m
+CONFIG_REGULATOR_RT4831=m
+CONFIG_REGULATOR_RT5120=m
+CONFIG_REGULATOR_RT5133=m
+CONFIG_REGULATOR_RT5190A=m
+CONFIG_REGULATOR_RT5739=m
+CONFIG_REGULATOR_RT5759=m
+CONFIG_REGULATOR_RT6160=m
+CONFIG_REGULATOR_RT6190=m
+CONFIG_REGULATOR_RT6245=m
+CONFIG_REGULATOR_RTMV20=m
+CONFIG_REGULATOR_RTQ2134=m
+CONFIG_REGULATOR_RTQ2208=m
+CONFIG_REGULATOR_RTQ6752=m
+CONFIG_REGULATOR_RZG2L_VBCTRL=m
+CONFIG_REGULATOR_S2DOS05=m
+CONFIG_REGULATOR_S2MPA01=y
+CONFIG_REGULATOR_S2MPS11=y
+CONFIG_REGULATOR_S5M8767=y
+CONFIG_REGULATOR_STM32_BOOSTER=m
+CONFIG_REGULATOR_STM32_PWR=y
+CONFIG_REGULATOR_STM32_VREFBUF=m
+CONFIG_REGULATOR_SUN20I=m
+CONFIG_REGULATOR_SY7636A=m
+CONFIG_REGULATOR_SY8827N=m
+CONFIG_REGULATOR_TPS6286X=m
+CONFIG_REGULATOR_TPS6287X=m
+CONFIG_REGULATOR_TPS65219=m
+CONFIG_REGULATOR_TPS6594=m
+CONFIG_REGULATOR_UNIPHIER=y
+CONFIG_REGULATOR_VEXPRESS=m
+CONFIG_REGULATOR_VQMMC_IPQ4019=m
+CONFIG_REGULATOR=y
+CONFIG_RELAY=y
+CONFIG_RELOCATABLE=y
+CONFIG_RELR=y
+CONFIG_REMOTEPROC_CDEV=y
+CONFIG_REMOTEPROC=y
+CONFIG_RENESAS_DMA=y
+CONFIG_RENESAS_I3C=m
+CONFIG_RENESAS_IRQC=y
+CONFIG_RENESAS_OSTM=y
+CONFIG_RENESAS_RPCIF=m
+CONFIG_RENESAS_RZAWDT=m
+CONFIG_RENESAS_RZG2L_IRQC=y
+CONFIG_RENESAS_RZG2LWDT=m
+CONFIG_RENESAS_RZN1WDT=m
+CONFIG_RENESAS_RZV2HWDT=m
+CONFIG_RENESAS_USB_DMAC=m
+CONFIG_RENESAS_WDT=y
+CONFIG_RESET_A10SR=m
+CONFIG_RESET_ASPEED=m
+CONFIG_RESET_BERLIN=y
+CONFIG_RESET_BRCMSTB_RESCAL=y
+CONFIG_RESET_BRCMSTB=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_HISI=y
+CONFIG_RESET_IMX7=y
+CONFIG_RESET_IMX8MP_AUDIOMIX=m
+CONFIG_RESET_MCHP_SPARX5=y
+CONFIG_RESET_MESON=y
+CONFIG_RESET_NPCM=y
+CONFIG_RESET_NUVOTON_MA35D1=y
+CONFIG_RESET_RASPBERRYPI=m
+CONFIG_RESET_RZG2L_USBPHY_CTRL=m
+CONFIG_RESET_SCMI=m
+CONFIG_RESET_SIMPLE=y
+CONFIG_RESET_SUNXI=y
+CONFIG_RESET_TEGRA_BPMP=y
+CONFIG_RESET_TI_SYSCON=m
+CONFIG_RESET_TI_TPS380X=m
+CONFIG_RESET_UNIPHIER_GLUE=y
+CONFIG_RESET_UNIPHIER=y
+CONFIG_RFD77402=m
+CONFIG_RFD_FTL=m
+CONFIG_RFKILL_GPIO=m
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL=m
+CONFIG_RICHTEK_RTQ6056=m
+CONFIG_ROCKCHIP_ANALOGIX_DP=y
+CONFIG_ROCKCHIP_CDN_DP=y
+CONFIG_ROCKCHIP_DTPM=m
+CONFIG_ROCKCHIP_DW_DP=y
+CONFIG_ROCKCHIP_DW_HDMI_QP=y
+CONFIG_ROCKCHIP_DW_HDMI=y
+CONFIG_ROCKCHIP_DW_MIPI_DSI2=y
+CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+CONFIG_ROCKCHIP_ERRATUM_3568002=y
+CONFIG_ROCKCHIP_ERRATUM_3588001=y
+CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_INNO_HDMI=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_ROCKCHIP_LVDS=y
+CONFIG_ROCKCHIP_MBOX=y
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+CONFIG_ROCKCHIP_RGB=y
+CONFIG_ROCKCHIP_RK3066_HDMI=y
+CONFIG_ROCKCHIP_SARADC=y
+CONFIG_ROCKCHIP_THERMAL=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_ROCKCHIP_VOP2=y
+CONFIG_ROCKCHIP_VOP=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_ROHM_BD79112=m
+CONFIG_ROHM_BM1390=m
+CONFIG_ROHM_BU27008=m
+CONFIG_ROHM_BU27034=m
+CONFIG_RPMSG_CTRL=m
+CONFIG_RPMSG_MTK_SCP=m
+CONFIG_RPMSG_NS=m
+CONFIG_RPMSG_QCOM_GLINK=m
+CONFIG_RPMSG_QCOM_GLINK_RPM=m
+CONFIG_RPMSG_QCOM_GLINK_SMEM=m
+CONFIG_RPMSG_QCOM_SMD=y
+CONFIG_RPMSG_TTY=m
+CONFIG_RPMSG_VIRTIO=m
+CONFIG_RPMSG_WWAN_CTRL=m
+CONFIG_RPMSG=y
+CONFIG_RPR0521=m
+CONFIG_RST_RCAR=y
+CONFIG_RT2500USB=m
+CONFIG_RT2800_LIB=m
+CONFIG_RT2800_LIB_MMIO=m
+CONFIG_RT2800PCI=m
+CONFIG_RT2800PCI_RT3290=y
+CONFIG_RT2800PCI_RT33XX=y
+CONFIG_RT2800PCI_RT35XX=y
+CONFIG_RT2800PCI_RT53XX=y
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT3573=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_LEDS=y
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_MMIO=m
+CONFIG_RT2X00_LIB_PCI=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00=m
+CONFIG_RT73USB=m
+CONFIG_RTC_DRV_ARMADA38X=y
+CONFIG_RTC_DRV_BBNSM=m
+CONFIG_RTC_DRV_BQ32K=m
+CONFIG_RTC_DRV_BRCMSTB=y
+CONFIG_RTC_DRV_CROS_EC=m
+CONFIG_RTC_DRV_CV1800=m
+CONFIG_RTC_DRV_DS1302=m
+CONFIG_RTC_DRV_DS1305=m
+CONFIG_RTC_DRV_DS1343=m
+CONFIG_RTC_DRV_DS1347=m
+CONFIG_RTC_DRV_DS1390=m
+CONFIG_RTC_DRV_EFI=y
+CONFIG_RTC_DRV_FSL_FTM_ALARM=m
+CONFIG_RTC_DRV_GOLDFISH=m
+CONFIG_RTC_DRV_HID_SENSOR_TIME=m
+CONFIG_RTC_DRV_HYM8563=m
+CONFIG_RTC_DRV_IMX_BBM_SCMI=m
+CONFIG_RTC_DRV_IMXDI=m
+CONFIG_RTC_DRV_IMX_SC=m
+CONFIG_RTC_DRV_ISL12022=m
+CONFIG_RTC_DRV_ISL1208=m
+CONFIG_RTC_DRV_M41T93=m
+CONFIG_RTC_DRV_M41T94=m
+CONFIG_RTC_DRV_MA35D1=m
+CONFIG_RTC_DRV_MAX31335=m
+CONFIG_RTC_DRV_MAX6902=m
+CONFIG_RTC_DRV_MAX6916=m
+CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_MC13XXX=m
+CONFIG_RTC_DRV_MCP795=m
+CONFIG_RTC_DRV_MESON_VRTC=m
+CONFIG_RTC_DRV_MV=m
+CONFIG_RTC_DRV_MXC=m
+CONFIG_RTC_DRV_MXC_V2=m
+CONFIG_RTC_DRV_NCT3018Y=m
+CONFIG_RTC_DRV_NCT6694=m
+CONFIG_RTC_DRV_NTXEC=m
+CONFIG_RTC_DRV_OPTEE=m
+CONFIG_RTC_DRV_PCF2123=m
+CONFIG_RTC_DRV_PCF2127=m
+CONFIG_RTC_DRV_PCF85063=m
+CONFIG_RTC_DRV_PCF8523=m
+CONFIG_RTC_DRV_PL030=m
+CONFIG_RTC_DRV_PL031=y
+CONFIG_RTC_DRV_PM8XXX=m
+CONFIG_RTC_DRV_R9701=m
+CONFIG_RTC_DRV_RK808=y
+CONFIG_RTC_DRV_RS5C348=m
+CONFIG_RTC_DRV_RTD119X=y
+CONFIG_RTC_DRV_RV3032=m
+CONFIG_RTC_DRV_RV8803=m
+CONFIG_RTC_DRV_RX4581=m
+CONFIG_RTC_DRV_RX6110=m
+CONFIG_RTC_DRV_RX8010=m
+CONFIG_RTC_DRV_S3C=y
+CONFIG_RTC_DRV_S5M=m
+CONFIG_RTC_DRV_SA1100=m
+CONFIG_RTC_DRV_SNVS=m
+CONFIG_RTC_DRV_STM32=m
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_RTC_DRV_TEGRA=y
+CONFIG_RTC_DRV_TI_K3=m
+CONFIG_RTC_DRV_TPS6594=m
+CONFIG_RTC_DRV_XGENE=y
+CONFIG_RTC_DRV_ZYNQMP=m
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTD119X_WATCHDOG=y
+CONFIG_RTL8180=m
+CONFIG_RTL8187_LEDS=y
+CONFIG_RTL8187=m
+CONFIG_RTL8188EE=m
+CONFIG_RTL8192C_COMMON=m
+CONFIG_RTL8192CE=m
+CONFIG_RTL8192CU=m
+CONFIG_RTL8192DE=m
+CONFIG_RTL8192DU=m
+CONFIG_RTL8192EE=m
+CONFIG_RTL8192E=m
+CONFIG_RTL8192SE=m
+CONFIG_RTL8192U=m
+CONFIG_RTL8723AE=m
+CONFIG_RTL8723BE=m
+CONFIG_RTL8723BS=m
+CONFIG_RTL8723_COMMON=m
+CONFIG_RTL8821AE=m
+CONFIG_RTL8XXXU=m
+CONFIG_RTLBTCOEXIST=m
+CONFIG_RTL_CARDS=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+CONFIG_RTLLIB=m
+CONFIG_RTLWIFI=m
+CONFIG_RTLWIFI_PCI=m
+CONFIG_RTLWIFI_USB=m
+CONFIG_RTS5208=m
+CONFIG_RTW88_8723CS=m
+CONFIG_RTW88_8723D=m
+CONFIG_RTW88_8723DS=m
+CONFIG_RTW88_8723DU=m
+CONFIG_RTW88_8821CE=m
+CONFIG_RTW88_8821C=m
+CONFIG_RTW88_8821CS=m
+CONFIG_RTW88_8821CU=m
+CONFIG_RTW88_8822BE=m
+CONFIG_RTW88_8822B=m
+CONFIG_RTW88_8822BS=m
+CONFIG_RTW88_8822BU=m
+CONFIG_RTW88_8822CE=m
+CONFIG_RTW88_8822C=m
+CONFIG_RTW88_8822CS=m
+CONFIG_RTW88_8822CU=m
+CONFIG_RTW88_CORE=m
+CONFIG_RTW88_DEBUGFS=y
+CONFIG_RTW88_DEBUG=y
+CONFIG_RTW88=m
+CONFIG_RTW88_PCI=m
+CONFIG_RTW88_SDIO=m
+CONFIG_RTW88_USB=m
+CONFIG_RTW89_8851BE=m
+CONFIG_RTW89_8851B=m
+CONFIG_RTW89_8852AE=m
+CONFIG_RTW89_8852A=m
+CONFIG_RTW89_8852BE=m
+CONFIG_RTW89_8852B=m
+CONFIG_RTW89_8852BTE=m
+CONFIG_RTW89_8852CE=m
+CONFIG_RTW89_8852C=m
+CONFIG_RTW89_8922AE=m
+CONFIG_RTW89_CORE=m
+CONFIG_RTW89_DEBUGFS=y
+CONFIG_RTW89_DEBUG=y
+CONFIG_RTW89=m
+CONFIG_RTW89_PCI=m
+CONFIG_RZ_DMAC=m
+CONFIG_RZG2L_ADC=m
+CONFIG_RZG2L_THERMAL=m
+CONFIG_RZG3E_THERMAL=m
+CONFIG_RZG3S_THERMAL=m
+CONFIG_RZ_MTU3=y
+CONFIG_S3C2410_WATCHDOG=y
+CONFIG_SA_GCC_8775P=m
+CONFIG_SA_GPUCC_8775P=m
+CONFIG_SATA_ACARD_AHCI=m
+CONFIG_SATA_AHCI=m
+CONFIG_SATA_AHCI_PLATFORM=m
+CONFIG_SATA_AHCI_SEATTLE=m
+CONFIG_SATA_DWC=m
+CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MV=m
+CONFIG_SATA_PROMISE=m
+CONFIG_SATA_QSTOR=m
+CONFIG_SATA_RCAR=m
+CONFIG_SATA_SIL24=m
+CONFIG_SATA_SIL=m
+CONFIG_SATA_SVW=m
+CONFIG_SATA_VIA=m
+CONFIG_SATA_VITESSE=m
+CONFIG_SCA3000=m
+CONFIG_SCA3300=m
+CONFIG_SC_CAMCC_7180=m
+CONFIG_SC_CAMCC_7280=m
+CONFIG_SC_CAMCC_8180X=m
+CONFIG_SC_CAMCC_8280XP=m
+CONFIG_SCD30_CORE=m
+CONFIG_SCD30_I2C=m
+CONFIG_SCD30_SERIAL=m
+CONFIG_SCD4X=m
+CONFIG_SC_DISPCC_7280=m
+CONFIG_SC_DISPCC_8280XP=m
+CONFIG_SC_GCC_7180=m
+CONFIG_SC_GCC_7280=m
+CONFIG_SC_GCC_8180X=m
+CONFIG_SC_GCC_8280XP=m
+CONFIG_SC_GPUCC_7280=m
+CONFIG_SC_GPUCC_8280XP=m
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SCHED_CLUSTER=y
+CONFIG_SCHED_CORE=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_MM_CID=y
+CONFIG_SCHED_SMT=y
+CONFIG_SCHEDSTATS=y
+CONFIG_SCHED_THERMAL_PRESSURE=y
+CONFIG_SC_LPASSCC_7280=m
+CONFIG_SC_LPASSCC_8280XP=m
+CONFIG_SC_LPASS_CORECC_7280=m
+CONFIG_SCSI_3W_9XXX=m
+CONFIG_SCSI_3W_SAS=m
+CONFIG_SCSI_AACRAID=m
+CONFIG_SCSI_ACARD=m
+CONFIG_SCSI_ADVANSYS=m
+CONFIG_SCSI_AIC79XX=m
+CONFIG_SCSI_AIC7XXX=m
+CONFIG_SCSI_AIC94XX=m
+CONFIG_SCSI_AM53C974=m
+CONFIG_SCSI_ARCMSR=m
+CONFIG_SCSI_BNX2_ISCSI=m
+CONFIG_SCSI_BUSLOGIC=m
+CONFIG_SCSI_COMMON=m
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_DMX3191D=m
+CONFIG_SCSI_ESAS2R=m
+CONFIG_SCSI_FC_ATTRS=m
+CONFIG_SCSI_FDOMAIN=m
+CONFIG_SCSI_FDOMAIN_PCI=m
+CONFIG_SCSI_FLASHPOINT=y
+CONFIG_SCSI_HISI_SAS=m
+CONFIG_SCSI_HISI_SAS_PCI=m
+CONFIG_SCSI_HPSA=m
+CONFIG_SCSI_HPTIOP=m
+CONFIG_SCSI_IMM=m
+CONFIG_SCSI_INIA100=m
+CONFIG_SCSI_INITIO=m
+CONFIG_SCSI_IPS=m
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI=m
+CONFIG_SCSI_MOD=m
+CONFIG_SCSI_MPI3MR=m
+CONFIG_SCSI_MPT2SAS=m
+CONFIG_SCSI_MPT2SAS_MAX_SGE=128
+CONFIG_SCSI_MPT3SAS=m
+CONFIG_SCSI_MPT3SAS_MAX_SGE=128
+CONFIG_SCSI_MVSAS_DEBUG=y
+CONFIG_SCSI_MVSAS=m
+CONFIG_SCSI_MVUMI=m
+CONFIG_SCSI_MYRB=m
+CONFIG_SCSI_MYRS=m
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PPA=m
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SMARTPQI=m
+CONFIG_SCSI_SNIC=m
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_STEX=m
+CONFIG_SCSI_SYM53C8XX_2=m
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+CONFIG_SCSI_SYM53C8XX_MMIO=y
+CONFIG_SCSI_UFS_BSG=y
+CONFIG_SCSI_UFS_CDNS_PLATFORM=m
+CONFIG_SCSI_UFS_CRYPTO=y
+CONFIG_SCSI_UFS_DWC_TC_PCI=m
+CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m
+CONFIG_SCSI_UFS_EXYNOS=m
+CONFIG_SCSI_UFSHCD=m
+CONFIG_SCSI_UFSHCD_PCI=m
+CONFIG_SCSI_UFSHCD_PLATFORM=m
+CONFIG_SCSI_UFS_HISI=m
+CONFIG_SCSI_UFS_HPB=y
+CONFIG_SCSI_UFS_HWMON=y
+CONFIG_SCSI_UFS_MEDIATEK=m
+CONFIG_SCSI_UFS_QCOM=m
+CONFIG_SCSI_UFS_RENESAS=m
+CONFIG_SCSI_UFS_ROCKCHIP=m
+CONFIG_SCSI_UFS_SPRD=m
+CONFIG_SCSI_UFS_TI_J721E=m
+CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE=y
+CONFIG_SCSI_VIRTIO=m
+CONFIG_SCSI_WD719X=m
+CONFIG_SC_VIDEOCC_7280=m
+CONFIG_SD_ADC_MODULATOR=m
+CONFIG_SDIO_UART=m
+CONFIG_SDM_GCC_660=m
+CONFIG_SDM_GPUCC_660=m
+CONFIG_SDM_MMCC_660=m
+CONFIG_SDP500=m
+CONFIG_SDX_GCC_75=m
+CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN=y
+CONFIG_SECONDARY_TRUSTED_KEYRING=y
+CONFIG_SECRETMEM=y
+CONFIG_SEG_LED_GPIO=m
+CONFIG_SENSEAIR_SUNRISE_CO2=m
+CONFIG_SENSIRION_SGP30=m
+CONFIG_SENSIRION_SGP40=m
+CONFIG_SENSORS_ACPI_POWER=m
+CONFIG_SENSORS_RASPBERRYPI_HWMON=m
+CONFIG_SENSORS_SA67MCU=m
+CONFIG_SENSORS_XGENE=m
+CONFIG_SERIAL_8250_BCM2835AUX=y
+CONFIG_SERIAL_8250_BCM7271=m
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_EM=m
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_MT6577=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_PCI1XXXX=m
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PERICOM=m
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_8250_PXA=m
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_TEGRA=y
+CONFIG_SERIAL_8250_UNIPHIER=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
+CONFIG_SERIAL_AMBA_PL010=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_BCM63XX=m
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_EARLYCON_SEMIHOST=y
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_FSL_LINFLEXUART=m
+CONFIG_SERIAL_FSL_LPUART=m
+CONFIG_SERIAL_IMX_CONSOLE=m
+CONFIG_SERIAL_IMX_EARLYCON=y
+CONFIG_SERIAL_IMX=m
+CONFIG_SERIAL_JSM=m
+CONFIG_SERIAL_LITEUART=m
+CONFIG_SERIAL_LITEUART_MAX_PORTS=1
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_MESON_CONSOLE=y
+CONFIG_SERIAL_MESON=m
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MVEBU_CONSOLE=y
+CONFIG_SERIAL_MVEBU_UART=y
+CONFIG_SERIAL_NUVOTON_MA35D1=m
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_QE=m
+CONFIG_SERIAL_RSCI=m
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_SAMSUNG=m
+CONFIG_SERIAL_SAMSUNG_UARTS=4
+CONFIG_SERIAL_SC16IS7XX_CORE=m
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_SH_SCI_DMA=y
+CONFIG_SERIAL_SH_SCI_EARLYCON=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=11
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SPRD=m
+CONFIG_SERIAL_STM32_CONSOLE=y
+CONFIG_SERIAL_STM32=m
+CONFIG_SERIAL_TEGRA=m
+CONFIG_SERIAL_TEGRA_UTC_CONSOLE=y
+CONFIG_SERIAL_TEGRA_UTC=m
+CONFIG_SERIAL_UARTLITE=m
+CONFIG_SERIAL_UARTLITE_NR_UARTS=1
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIO_APBPS2=m
+CONFIG_SERIO=m
+CONFIG_SERIO_NVEC_PS2=m
+CONFIG_SERIO_OLPC_APSP=m
+CONFIG_SERIO_PARKBD=m
+CONFIG_SERIO_PCIPS2=m
+CONFIG_SERIO_RAW=m
+CONFIG_SERIO_SERPORT=m
+CONFIG_SERIO_SUN4I_PS2=m
+CONFIG_SETEND_EMULATION=y
+CONFIG_SG_SPLIT=y
+CONFIG_SH_TIMER_CMT=y
+CONFIG_SH_TIMER_TMU=y
+CONFIG_SI1133=m
+CONFIG_SI1145=m
+CONFIG_SI7005=m
+CONFIG_SI7020=m
+CONFIG_SIGNED_PE_FILE_VERIFICATION=y
+CONFIG_SL28CPLD_WATCHDOG=m
+CONFIG_SLHC=m
+CONFIG_SLIC_DS26522=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLIP=m
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_SLIP_SMART=y
+CONFIG_SM_CAMCC_4450=m
+CONFIG_SM_CAMCC_6350=m
+CONFIG_SM_CAMCC_7150=m
+CONFIG_SM_CAMCC_8150=m
+CONFIG_SM_CAMCC_8250=m
+CONFIG_SM_CAMCC_8450=m
+CONFIG_SM_CAMCC_8550=m
+CONFIG_SM_CAMCC_8650=m
+CONFIG_SM_CAMCC_MILOS=m
+CONFIG_SM_DISPCC_4450=m
+CONFIG_SM_DISPCC_6115=m
+CONFIG_SM_DISPCC_6125=m
+CONFIG_SM_DISPCC_6350=m
+CONFIG_SM_DISPCC_6375=m
+CONFIG_SM_DISPCC_7150=m
+CONFIG_SM_DISPCC_8250=m
+CONFIG_SM_DISPCC_8450=m
+CONFIG_SM_DISPCC_8550=m
+CONFIG_SM_DISPCC_8650=m
+CONFIG_SM_DISPCC_8750=m
+CONFIG_SM_DISPCC_MILOS=m
+CONFIG_SM_GCC_4450=m
+CONFIG_SM_GCC_6115=m
+CONFIG_SM_GCC_6125=m
+CONFIG_SM_GCC_6350=m
+CONFIG_SM_GCC_6375=m
+CONFIG_SM_GCC_7150=m
+CONFIG_SM_GCC_8150=m
+CONFIG_SM_GCC_8250=m
+CONFIG_SM_GCC_8350=m
+CONFIG_SM_GCC_8450=m
+CONFIG_SM_GCC_8550=m
+CONFIG_SM_GCC_8650=m
+CONFIG_SM_GCC_8750=m
+CONFIG_SM_GCC_MILOS=m
+CONFIG_SM_GPUCC_4450=m
+CONFIG_SM_GPUCC_6115=m
+CONFIG_SM_GPUCC_6125=m
+CONFIG_SM_GPUCC_6350=m
+CONFIG_SM_GPUCC_6375=m
+CONFIG_SM_GPUCC_8350=m
+CONFIG_SM_GPUCC_8450=m
+CONFIG_SM_GPUCC_8550=m
+CONFIG_SM_GPUCC_8650=m
+CONFIG_SM_GPUCC_MILOS=m
+CONFIG_SM_LPASSCC_6115=m
+CONFIG_SMPRO_ERRMON=m
+CONFIG_SMPRO_MISC=m
+CONFIG_SMSC_PHY=m
+CONFIG_SMS_SDIO_DRV=m
+CONFIG_SMS_SIANO_MDTV=m
+CONFIG_SMS_SIANO_RC=y
+CONFIG_SMS_USB_DRV=m
+CONFIG_SM_TCSRCC_8550=m
+CONFIG_SM_TCSRCC_8650=m
+CONFIG_SM_TCSRCC_8750=m
+CONFIG_SM_VIDEOCC_6350=m
+CONFIG_SM_VIDEOCC_7150=m
+CONFIG_SM_VIDEOCC_8150=m
+CONFIG_SM_VIDEOCC_8250=m
+CONFIG_SM_VIDEOCC_8350=m
+CONFIG_SM_VIDEOCC_8450=m
+CONFIG_SM_VIDEOCC_8550=m
+CONFIG_SM_VIDEOCC_MILOS=m
+CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_AC97_POWER_SAVE_DEFAULT=10
+CONFIG_SND_AC97_POWER_SAVE=y
+CONFIG_SND_ALOOP=m
+CONFIG_SND_AMD_ACP_CONFIG=m
+CONFIG_SND_ATMEL_SOC=m
+CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
+CONFIG_SND_AUDIO_GRAPH_CARD2=m
+CONFIG_SND_AUDIO_GRAPH_CARD=m
+CONFIG_SND_BCM2835=m
+CONFIG_SND_BCM2835_SOC_I2S=m
+CONFIG_SND_COMPRESS_OFFLOAD=m
+CONFIG_SND_CTL_FAST_LOOKUP=y
+CONFIG_SND_CTL_INPUT_VALIDATION=y
+CONFIG_SND_DESIGNWARE_I2S=m
+CONFIG_SND_DMAENGINE_PCM=m
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_DUMMY=m
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_HDA_ALIGNED_MMIO=y
+CONFIG_SND_HDA_CODEC_ALC260=m
+CONFIG_SND_HDA_CODEC_ALC262=m
+CONFIG_SND_HDA_CODEC_ALC268=m
+CONFIG_SND_HDA_CODEC_ALC269=m
+CONFIG_SND_HDA_CODEC_ALC662=m
+CONFIG_SND_HDA_CODEC_ALC680=m
+CONFIG_SND_HDA_CODEC_ALC861=m
+CONFIG_SND_HDA_CODEC_ALC861VD=m
+CONFIG_SND_HDA_CODEC_ALC880=m
+CONFIG_SND_HDA_CODEC_ALC882=m
+CONFIG_SND_HDA_CODEC_CM9825=m
+CONFIG_SND_HDA_CODEC_CS420X=m
+CONFIG_SND_HDA_CODEC_CS421X=m
+CONFIG_SND_HDA_CODEC_CS8409=m
+CONFIG_SND_HDA_CODEC_HDMI_INTEL=m
+CONFIG_SND_HDA_CODEC_SENARYTECH=m
+CONFIG_SND_HDA_COMPONENT=y
+CONFIG_SND_HDA_CORE=m
+CONFIG_SND_HDA_CS_DSP_CONTROLS=m
+CONFIG_SND_HDA_EXT_CORE=m
+CONFIG_SND_HDA_GENERIC=m
+CONFIG_SND_HDA=m
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
+CONFIG_SND_HDA_PREALLOC_SIZE=2048
+CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m
+CONFIG_SND_HDA_SCODEC_CS35L41=m
+CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m
+CONFIG_SND_HDA_SCODEC_CS35L56_I2C=m
+CONFIG_SND_HDA_SCODEC_CS35L56_SPI=m
+CONFIG_SND_HDA_SCODEC_TAS2781_I2C=m
+CONFIG_SND_HDA_SCODEC_TAS2781_SPI=m
+CONFIG_SND_HDA_TEGRA=m
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_I2S_HI6210_I2S=m
+CONFIG_SND_IMX_SOC=m
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_JACK=y
+CONFIG_SND=m
+CONFIG_SND_MAX_CARDS=32
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_MMP_SOC_SSPA=m
+CONFIG_SND_MPU401=m
+CONFIG_SND_MPU401_UART=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_MTS64=m
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_PCM_ELD=y
+CONFIG_SND_PCM_IEC958=y
+CONFIG_SND_PCM=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_PCMTEST=m
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_PORTMAN2X4=m
+CONFIG_SND_PROC_FS=y
+CONFIG_SND_PXA910_SOC=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_SAMSUNG_I2S=m
+CONFIG_SND_SAMSUNG_PCM=m
+CONFIG_SND_SAMSUNG_SPDIF=m
+CONFIG_SND_SEQ_DEVICE=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+CONFIG_SND_SEQ_MIDI_EVENT=m
+CONFIG_SND_SEQ_MIDI=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQUENCER_OSS=m
+CONFIG_SND_SEQ_UMP_CLIENT=m
+CONFIG_SND_SEQ_UMP=y
+CONFIG_SND_SEQ_VIRMIDI=m
+CONFIG_SND_SERIAL_GENERIC=m
+CONFIG_SND_SERIAL_U16550=m
+CONFIG_SND_SIMPLE_CARD=m
+CONFIG_SND_SIMPLE_CARD_UTILS=m
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AC97_CODEC=m
+CONFIG_SND_SOC_ACPI=m
+CONFIG_SND_SOC_ADAU1372_I2C=m
+CONFIG_SND_SOC_ADAU1372=m
+CONFIG_SND_SOC_ADAU1372_SPI=m
+CONFIG_SND_SOC_ADAU7002=m
+CONFIG_SND_SOC_ADAU_UTILS=m
+CONFIG_SND_SOC_ADI_AXI_I2S=m
+CONFIG_SND_SOC_ADI_AXI_SPDIF=m
+CONFIG_SND_SOC_ADI=m
+CONFIG_SND_SOC_AK4375=m
+CONFIG_SND_SOC_AK4458=m
+CONFIG_SND_SOC_AK4613=m
+CONFIG_SND_SOC_AK4619=m
+CONFIG_SND_SOC_AK5558=m
+CONFIG_SND_SOC_ALC5623=m
+CONFIG_SND_SOC_ALC5632=m
+CONFIG_SND_SOC_APPLE_MCA=m
+CONFIG_SND_SOC_APQ8016_SBC=m
+CONFIG_SND_SOC_ARNDALE=m
+CONFIG_SND_SOC_AUDIO_IIO_AUX=m
+CONFIG_SND_SOC_AW8738=m
+CONFIG_SND_SOC_AW87390=m
+CONFIG_SND_SOC_AW88166=m
+CONFIG_SND_SOC_AW88261=m
+CONFIG_SND_SOC_AW88395_LIB=m
+CONFIG_SND_SOC_AW88395=m
+CONFIG_SND_SOC_AW88399=m
+CONFIG_SND_SOC_BT_SCO=m
+CONFIG_SND_SOC_CHV3_CODEC=m
+CONFIG_SND_SOC_CHV3_I2S=m
+CONFIG_SND_SOC_COMPRESS=y
+CONFIG_SND_SOC_CROS_EC_CODEC=m
+CONFIG_SND_SOC_CS35L33=m
+CONFIG_SND_SOC_CS35L41_I2C=m
+CONFIG_SND_SOC_CS35L41_LIB=m
+CONFIG_SND_SOC_CS35L41=m
+CONFIG_SND_SOC_CS35L41_SPI=m
+CONFIG_SND_SOC_CS35L45_I2C=m
+CONFIG_SND_SOC_CS35L45=m
+CONFIG_SND_SOC_CS35L45_SPI=m
+CONFIG_SND_SOC_CS35L56_I2C=m
+CONFIG_SND_SOC_CS35L56=m
+CONFIG_SND_SOC_CS35L56_SDW=m
+CONFIG_SND_SOC_CS35L56_SHARED=m
+CONFIG_SND_SOC_CS35L56_SPI=m
+CONFIG_SND_SOC_CS40L50=m
+CONFIG_SND_SOC_CS4234=m
+CONFIG_SND_SOC_CS42L42_CORE=m
+CONFIG_SND_SOC_CS42L42_SDW=m
+CONFIG_SND_SOC_CS42L43=m
+CONFIG_SND_SOC_CS42L43_SDW=m
+CONFIG_SND_SOC_CS42L83=m
+CONFIG_SND_SOC_CS42XX8_I2C=m
+CONFIG_SND_SOC_CS42XX8=m
+CONFIG_SND_SOC_CS4349=m
+CONFIG_SND_SOC_CS530X_I2C=m
+CONFIG_SND_SOC_CS53L30=m
+CONFIG_SND_SOC_CX2072X=m
+CONFIG_SND_SOC_DA7219=m
+CONFIG_SND_SOC_DMIC=m
+CONFIG_SND_SOC_ES8311=m
+CONFIG_SND_SOC_ES8316=m
+CONFIG_SND_SOC_ES8326=m
+CONFIG_SND_SOC_ES8328_I2C=m
+CONFIG_SND_SOC_ES8328=m
+CONFIG_SND_SOC_ES8328_SPI=m
+CONFIG_SND_SOC_FRAMER=m
+CONFIG_SND_SOC_FS210X=m
+CONFIG_SND_SOC_FSL_AUD2HTX=m
+CONFIG_SND_SOC_FSL_AUDMIX=m
+CONFIG_SND_SOC_FSL_MQS=m
+CONFIG_SND_SOC_FSL_RPMSG=m
+CONFIG_SND_SOC_FSL_SAI=m
+CONFIG_SND_SOC_FSL_SPDIF=m
+CONFIG_SND_SOC_FSL_SSI=m
+CONFIG_SND_SOC_FSL_UTILS=m
+CONFIG_SND_SOC_FSL_XCVR=m
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_GTM601=m
+CONFIG_SND_SOC_HDA=m
+CONFIG_SND_SOC_HDMI_CODEC=m
+CONFIG_SND_SOC_I2C_AND_SPI=m
+CONFIG_SND_SOC_ICS43432=m
+CONFIG_SND_SOC_IDT821034=m
+CONFIG_SND_SOC_IMX_AUDIO_RPMSG=m
+CONFIG_SND_SOC_IMX_AUDMIX=m
+CONFIG_SND_SOC_IMX_AUDMUX=m
+CONFIG_SND_SOC_IMX_CARD=m
+CONFIG_SND_SOC_IMX_ES8328=m
+CONFIG_SND_SOC_IMX_HDMI=m
+CONFIG_SND_SOC_IMX_PCM_DMA=m
+CONFIG_SND_SOC_IMX_PCM_RPMSG=m
+CONFIG_SND_SOC_IMX_RPMSG=m
+CONFIG_SND_SOC_IMX_SGTL5000=m
+CONFIG_SND_SOC_IMX_SPDIF=m
+CONFIG_SND_SOC_INTEL_KEEMBAY=m
+CONFIG_SND_SOC_LPASS_APQ8016=m
+CONFIG_SND_SOC_LPASS_CDC_DMA=m
+CONFIG_SND_SOC_LPASS_CPU=m
+CONFIG_SND_SOC_LPASS_HDMI=m
+CONFIG_SND_SOC_LPASS_IPQ806X=m
+CONFIG_SND_SOC_LPASS_MACRO_COMMON=m
+CONFIG_SND_SOC_LPASS_PLATFORM=m
+CONFIG_SND_SOC_LPASS_RX_MACRO=m
+CONFIG_SND_SOC_LPASS_SC7180=m
+CONFIG_SND_SOC_LPASS_SC7280=m
+CONFIG_SND_SOC_LPASS_TX_MACRO=m
+CONFIG_SND_SOC_LPASS_VA_MACRO=m
+CONFIG_SND_SOC_LPASS_WSA_MACRO=m
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_MAX98088=m
+CONFIG_SND_SOC_MAX98090=m
+CONFIG_SND_SOC_MAX98095=m
+CONFIG_SND_SOC_MAX98357A=m
+CONFIG_SND_SOC_MAX98363=m
+CONFIG_SND_SOC_MAX98388=m
+CONFIG_SND_SOC_MAX98390=m
+CONFIG_SND_SOC_MAX98396=m
+CONFIG_SND_SOC_MAX98504=m
+CONFIG_SND_SOC_MAX98520=m
+CONFIG_SND_SOC_MAX9860=m
+CONFIG_SND_SOC_MAX98927=m
+CONFIG_SND_SOC_MEDIATEK=m
+CONFIG_SND_SOC_MSM8996=m
+CONFIG_SND_SOC_MT2701_CS42448=m
+CONFIG_SND_SOC_MT2701=m
+CONFIG_SND_SOC_MT2701_WM8960=m
+CONFIG_SND_SOC_MT6357=m
+CONFIG_SND_SOC_MT6358=m
+CONFIG_SND_SOC_MT6359=m
+CONFIG_SND_SOC_MT6797=m
+CONFIG_SND_SOC_MT7986=m
+CONFIG_SND_SOC_MT7986_WM8960=m
+CONFIG_SND_SOC_MT8173=m
+CONFIG_SND_SOC_MT8173_MAX98090=m
+CONFIG_SND_SOC_MT8173_RT5650=m
+CONFIG_SND_SOC_MT8173_RT5650_RT5514=m
+CONFIG_SND_SOC_MT8173_RT5650_RT5676=m
+CONFIG_SND_SOC_MT8183_DA7219_MAX98357A=m
+CONFIG_SND_SOC_MT8183=m
+CONFIG_SND_SOC_MT8183_MT6358_TS3A227E_MAX98357A=m
+CONFIG_SND_SOC_MT8186=m
+CONFIG_SND_SOC_MT8186_MT6366_DA7219_MAX98357=m
+CONFIG_SND_SOC_MT8186_MT6366=m
+CONFIG_SND_SOC_MT8186_MT6366_RT1019_RT5682S=m
+CONFIG_SND_SOC_MT8188=m
+CONFIG_SND_SOC_MT8188_MT6359=m
+CONFIG_SND_SOC_MT8192=m
+CONFIG_SND_SOC_MT8195=m
+CONFIG_SND_SOC_MT8195_MT6359=m
+CONFIG_SND_SOC_MT8365=m
+CONFIG_SND_SOC_MT8365_MT6357=m
+CONFIG_SND_SOC_MTK_BTCVSD=m
+CONFIG_SND_SOC_NAU8315=m
+CONFIG_SND_SOC_NAU8821=m
+CONFIG_SND_SOC_NAU8825=m
+CONFIG_SND_SOC_ODROID=m
+CONFIG_SND_SOC_PCM1754=m
+CONFIG_SND_SOC_PCM5102A=m
+CONFIG_SND_SOC_PCM6240=m
+CONFIG_SND_SOC_PEB2466=m
+CONFIG_SND_SOC_PM4125_SDW=m
+CONFIG_SND_SOC_QCOM_COMMON=m
+CONFIG_SND_SOC_QCOM=m
+CONFIG_SND_SOC_QCOM_SDW=m
+CONFIG_SND_SOC_QDSP6_ADM=m
+CONFIG_SND_SOC_QDSP6_AFE_CLOCKS=m
+CONFIG_SND_SOC_QDSP6_AFE_DAI=m
+CONFIG_SND_SOC_QDSP6_AFE=m
+CONFIG_SND_SOC_QDSP6_APM_DAI=m
+CONFIG_SND_SOC_QDSP6_APM_LPASS_DAI=m
+CONFIG_SND_SOC_QDSP6_APM=m
+CONFIG_SND_SOC_QDSP6_ASM_DAI=m
+CONFIG_SND_SOC_QDSP6_ASM=m
+CONFIG_SND_SOC_QDSP6_COMMON=m
+CONFIG_SND_SOC_QDSP6_CORE=m
+CONFIG_SND_SOC_QDSP6=m
+CONFIG_SND_SOC_QDSP6_PRM_LPASS_CLOCKS=m
+CONFIG_SND_SOC_QDSP6_PRM=m
+CONFIG_SND_SOC_QDSP6_ROUTING=m
+CONFIG_SND_SOC_RCAR=m
+CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m
+CONFIG_SND_SOC_RK3308=m
+CONFIG_SND_SOC_RK3328=m
+CONFIG_SND_SOC_RK3399_GRU_SOUND=m
+CONFIG_SND_SOC_RK817=m
+CONFIG_SND_SOC_RL6231=m
+CONFIG_SND_SOC_ROCKCHIP_I2S=m
+CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
+CONFIG_SND_SOC_ROCKCHIP=m
+CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
+CONFIG_SND_SOC_ROCKCHIP_PDM=m
+CONFIG_SND_SOC_ROCKCHIP_RT5645=m
+CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
+CONFIG_SND_SOC_RT1011=m
+CONFIG_SND_SOC_RT1015=m
+CONFIG_SND_SOC_RT1015P=m
+CONFIG_SND_SOC_RT1017_SDCA_SDW=m
+CONFIG_SND_SOC_RT1316_SDW=m
+CONFIG_SND_SOC_RT1318_SDW=m
+CONFIG_SND_SOC_RT1320_SDW=m
+CONFIG_SND_SOC_RT5514=m
+CONFIG_SND_SOC_RT5514_SPI=m
+CONFIG_SND_SOC_RT5631=m
+CONFIG_SND_SOC_RT5640=m
+CONFIG_SND_SOC_RT5645=m
+CONFIG_SND_SOC_RT5659=m
+CONFIG_SND_SOC_RT5663=m
+CONFIG_SND_SOC_RT5677=m
+CONFIG_SND_SOC_RT5677_SPI=m
+CONFIG_SND_SOC_RT5682_I2C=m
+CONFIG_SND_SOC_RT5682=m
+CONFIG_SND_SOC_RT5682S=m
+CONFIG_SND_SOC_RT711_SDCA_SDW=m
+CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW=m
+CONFIG_SND_SOC_RT712_SDCA_SDW=m
+CONFIG_SND_SOC_RT715_SDCA_SDW=m
+CONFIG_SND_SOC_RT722_SDCA_SDW=m
+CONFIG_SND_SOC_RT9120=m
+CONFIG_SND_SOC_RTQ9128=m
+CONFIG_SND_SOC_RZ=m
+CONFIG_SND_SOC_SAMSUNG_ARIES_WM8994=m
+CONFIG_SND_SOC_SAMSUNG=m
+CONFIG_SND_SOC_SAMSUNG_MIDAS_WM1811=m
+CONFIG_SND_SOC_SAMSUNG_SMDK_SPDIF=m
+CONFIG_SND_SOC_SAMSUNG_SMDK_WM8994=m
+CONFIG_SND_SOC_SC7180=m
+CONFIG_SND_SOC_SC7280=m
+CONFIG_SND_SOC_SC8280XP=m
+CONFIG_SND_SOC_SDM845=m
+CONFIG_SND_SOC_SDW_MOCKUP=m
+CONFIG_SND_SOC_SGTL5000=m
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+CONFIG_SND_SOC_SIMPLE_MUX=m
+CONFIG_SND_SOC_SM8250=m
+CONFIG_SND_SOC_SMA1303=m
+CONFIG_SND_SOC_SMDK_WM8994_PCM=m
+CONFIG_SND_SOC_SNOW=m
+CONFIG_SND_SOC_SPDIF=m
+CONFIG_SND_SOC_SRC4XXX_I2C=m
+CONFIG_SND_SOC_SRC4XXX=m
+CONFIG_SND_SOC_SSM3515=m
+CONFIG_SND_SOC_STI_SAS=m
+CONFIG_SND_SOC_STM32_DFSDM=m
+CONFIG_SND_SOC_STM32_I2S=m
+CONFIG_SND_SOC_STM32_SAI=m
+CONFIG_SND_SOC_STM32_SPDIFRX=m
+CONFIG_SND_SOC_STORM=m
+CONFIG_SND_SOC_TAS2764=m
+CONFIG_SND_SOC_TAS2780=m
+CONFIG_SND_SOC_TAS2781_COMLIB=m
+CONFIG_SND_SOC_TAS2781_FMWLIB=m
+CONFIG_SND_SOC_TAS2781_I2C=m
+CONFIG_SND_SOC_TAS2783_SDW=m
+CONFIG_SND_SOC_TAS5805M=m
+CONFIG_SND_SOC_TEGRA186_ASRC=m
+CONFIG_SND_SOC_TEGRA186_DSPK=m
+CONFIG_SND_SOC_TEGRA20_AC97=m
+CONFIG_SND_SOC_TEGRA20_DAS=m
+CONFIG_SND_SOC_TEGRA20_I2S=m
+CONFIG_SND_SOC_TEGRA20_SPDIF=m
+CONFIG_SND_SOC_TEGRA210_ADMAIF=m
+CONFIG_SND_SOC_TEGRA210_ADX=m
+CONFIG_SND_SOC_TEGRA210_AHUB=m
+CONFIG_SND_SOC_TEGRA210_AMX=m
+CONFIG_SND_SOC_TEGRA210_DMIC=m
+CONFIG_SND_SOC_TEGRA210_I2S=m
+CONFIG_SND_SOC_TEGRA210_MIXER=m
+CONFIG_SND_SOC_TEGRA210_MVC=m
+CONFIG_SND_SOC_TEGRA210_OPE=m
+CONFIG_SND_SOC_TEGRA210_SFC=m
+CONFIG_SND_SOC_TEGRA_ALC5632=m
+CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m
+CONFIG_SND_SOC_TEGRA=m
+CONFIG_SND_SOC_TEGRA_MACHINE_DRV=m
+CONFIG_SND_SOC_TEGRA_MAX98088=m
+CONFIG_SND_SOC_TEGRA_MAX98090=m
+CONFIG_SND_SOC_TEGRA_RT5631=m
+CONFIG_SND_SOC_TEGRA_RT5640=m
+CONFIG_SND_SOC_TEGRA_RT5677=m
+CONFIG_SND_SOC_TEGRA_SGTL5000=m
+CONFIG_SND_SOC_TEGRA_TRIMSLICE=m
+CONFIG_SND_SOC_TEGRA_WM8753=m
+CONFIG_SND_SOC_TEGRA_WM8903=m
+CONFIG_SND_SOC_TEGRA_WM9712=m
+CONFIG_SND_SOC_TFA989X=m
+CONFIG_SND_SOC_TLV320ADC3XXX=m
+CONFIG_SND_SOC_TLV320AIC23_I2C=m
+CONFIG_SND_SOC_TLV320AIC23=m
+CONFIG_SND_SOC_TLV320AIC3X_I2C=m
+CONFIG_SND_SOC_TLV320AIC3X=m
+CONFIG_SND_SOC_TLV320AIC3X_SPI=m
+CONFIG_SND_SOC_TOPOLOGY=y
+CONFIG_SND_SOC_TS3A227E=m
+CONFIG_SND_SOC_UNIPHIER_AIO=m
+CONFIG_SND_SOC_UNIPHIER_EVEA_CODEC=m
+CONFIG_SND_SOC_UNIPHIER_LD11=m
+CONFIG_SND_SOC_UNIPHIER=m
+CONFIG_SND_SOC_UNIPHIER_PXS2=m
+CONFIG_SND_SOC_WCD937X_SDW=m
+CONFIG_SND_SOC_WCD938X=m
+CONFIG_SND_SOC_WCD938X_SDW=m
+CONFIG_SND_SOC_WCD939X_SDW=m
+CONFIG_SND_SOC_WCD_MBHC=m
+CONFIG_SND_SOC_WM8524=m
+CONFIG_SND_SOC_WM8731_I2C=m
+CONFIG_SND_SOC_WM8731=m
+CONFIG_SND_SOC_WM8731_SPI=m
+CONFIG_SND_SOC_WM8753=m
+CONFIG_SND_SOC_WM8782=m
+CONFIG_SND_SOC_WM8903=m
+CONFIG_SND_SOC_WM8940=m
+CONFIG_SND_SOC_WM8960=m
+CONFIG_SND_SOC_WM8961=m
+CONFIG_SND_SOC_WM8994=m
+CONFIG_SND_SOC_WM9712=m
+CONFIG_SND_SOC_WM_ADSP=m
+CONFIG_SND_SOC_WM_HUBS=m
+CONFIG_SND_SOC_WSA883X=m
+CONFIG_SND_SOC_WSA884X=m
+CONFIG_SND_SOC_X1E80100=m
+CONFIG_SND_SPI=y
+CONFIG_SND_SUN4I_CODEC=m
+CONFIG_SND_SUN4I_I2S=m
+CONFIG_SND_SUN4I_SPDIF=m
+CONFIG_SND_SUN50I_CODEC_ANALOG=m
+CONFIG_SND_SUN50I_DMIC=m
+CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m
+CONFIG_SND_SUN8I_CODEC_ANALOG=m
+CONFIG_SND_SUN8I_CODEC=m
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_TEST_COMPONENT=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_UMP_LEGACY_RAWMIDI=y
+CONFIG_SND_UMP=m
+CONFIG_SND_USB_6FIRE=m
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_AUDIO_MIDI_V2=y
+CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB=y
+CONFIG_SND_UTIMER=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VIRMIDI=m
+CONFIG_SND_VIRTIO=m
+CONFIG_SND_VMASTER=y
+CONFIG_SOC_BRCMSTB=y
+CONFIG_SOC_BUS=y
+CONFIG_SOC_IMX8M=y
+CONFIG_SOC_IMX9=m
+CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
+CONFIG_SOCK_VALIDATE_XMIT=y
+CONFIG_SOC_RENESAS=y
+CONFIG_SOC_SAMSUNG=y
+CONFIG_SOC_TEGRA_CBB=m
+CONFIG_SOC_TEGRA_FLOWCTRL=y
+CONFIG_SOC_TEGRA_FUSE=y
+CONFIG_SOC_TEGRA_PMC=y
+CONFIG_SOC_TEGRA_POWERGATE_BPMP=y
+CONFIG_SOC_TI=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_SOFT_WATCHDOG=m
+CONFIG_SOPHGO_CV1800B_ADC=m
+CONFIG_SOPHGO_CV1800B_DMAMUX=m
+CONFIG_SOPHGO_CV1800_RTCSYS=m
+CONFIG_SOPHGO_SG2042_MSI=y
+CONFIG_SOPHGO_SG2044_TOPSYS=m
+CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUNDWIRE_AMD=m
+CONFIG_SOUNDWIRE_CADENCE=m
+CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=m
+CONFIG_SOUNDWIRE_INTEL=m
+CONFIG_SOUNDWIRE_QCOM=m
+CONFIG_SOUNDWIRE=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPI_AIROHA_SNFI=m
+CONFIG_SPI_AMLOGIC_SPIFC_A1=m
+CONFIG_SPI_AMLOGIC_SPIFC_A4=m
+CONFIG_SPI_AMLOGIC_SPISG=m
+CONFIG_SPI_APPLE=m
+CONFIG_SPI_ARMADA_3700=m
+CONFIG_SPI_ATMEL=m
+CONFIG_SPI_BCM2835AUX=m
+CONFIG_SPI_BCM2835=m
+CONFIG_SPI_BCM63XX_HSSPI=m
+CONFIG_SPI_BCMBCA_HSSPI=m
+CONFIG_SPI_BCM_QSPI=m
+CONFIG_SPI_BITBANG=m
+CONFIG_SPI_CADENCE_XSPI=m
+CONFIG_SPI_CH341=m
+CONFIG_SPI_CS42L43=m
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_FSL_DSPI=m
+CONFIG_SPI_FSL_LPSPI=m
+CONFIG_SPI_HISI_KUNPENG=m
+CONFIG_SPI_HISI_SFC=m
+CONFIG_SPI_HISI_SFC_V3XX=m
+CONFIG_SPI_IMX=m
+CONFIG_SPI_KSPI2=m
+CONFIG_SPI_LJCA=m
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_MESON_SPICC=m
+CONFIG_SPI_MESON_SPIFC=m
+CONFIG_SPI_MICROCHIP_CORE=m
+CONFIG_SPI_MICROCHIP_CORE_QSPI=m
+CONFIG_SPI_MT65XX=m
+CONFIG_SPI_MTK_SNFI=m
+CONFIG_SPI_NPCM_FIU=m
+CONFIG_SPI_NPCM_PSPI=m
+CONFIG_SPI_OFFLOAD_TRIGGER_ADI_UTIL_SD=m
+CONFIG_SPI_OFFLOAD_TRIGGER_PWM=m
+CONFIG_SPI_ORION=y
+CONFIG_SPI_PCI1XXXX=m
+CONFIG_SPI_PL022=y
+CONFIG_SPI_QCOM_QSPI=m
+CONFIG_SPI_QPIC_SNAND=m
+CONFIG_SPI_QUP=y
+CONFIG_SPI_ROCKCHIP_SFC=m
+CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_RPCIF=m
+CONFIG_SPI_RSPI=m
+CONFIG_SPI_RZV2H_RSPI=m
+CONFIG_SPI_RZV2M_CSI=m
+CONFIG_SPI_S3C64XX=y
+CONFIG_SPI_SG2044_NOR=m
+CONFIG_SPI_SH_HSPI=m
+CONFIG_SPI_SH_MSIOF=m
+CONFIG_SPI_SLAVE_MT27XX=m
+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
+CONFIG_SPI_SLAVE_TIME=m
+CONFIG_SPI_SLAVE=y
+CONFIG_SPI_SN_F_OSPI=m
+CONFIG_SPI_SPIDEV=m
+CONFIG_SPI_SPRD_ADI=m
+CONFIG_SPI_SPRD=m
+CONFIG_SPI_STM32=m
+CONFIG_SPI_STM32_OSPI=m
+CONFIG_SPI_STM32_QSPI=m
+CONFIG_SPI_SUN4I=m
+CONFIG_SPI_SUN6I=m
+CONFIG_SPI_TEGRA114=m
+CONFIG_SPI_TEGRA20_SFLASH=m
+CONFIG_SPI_TEGRA20_SLINK=m
+CONFIG_SPI_TEGRA210_QUAD=m
+CONFIG_SPI_THUNDERX=m
+CONFIG_SPI_UNIPHIER=m
+CONFIG_SPI_VIRTIO=m
+CONFIG_SPI_WPCM_FIU=m
+CONFIG_SPI_XLP=m
+CONFIG_SPI=y
+CONFIG_SPMI_APPLE=m
+CONFIG_SPMI_HISI3670=m
+CONFIG_SPMI_MSM_PMIC_ARB=y
+CONFIG_SPMI_MTK_PMIF=m
+CONFIG_SPMI=y
+CONFIG_SPRD_COMMON_CLK=y
+CONFIG_SPRD_IOMMU=m
+CONFIG_SPRD_MBOX=m
+CONFIG_SPRD_SC9860_CLK=y
+CONFIG_SPRD_SC9863A_CLK=y
+CONFIG_SPRD_TIMER=y
+CONFIG_SPRD_UMS512_CLK=m
+CONFIG_SPRD_WATCHDOG=m
+CONFIG_SPS30_I2C=m
+CONFIG_SPS30=m
+CONFIG_SPS30_SERIAL=m
+CONFIG_SRAM=y
+CONFIG_SRF04=m
+CONFIG_SRF08=m
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_BLOCKIO=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_SDIOHOST_POSSIBLE=y
+CONFIG_SSB_SDIOHOST=y
+CONFIG_SSB_SPROM=y
+CONFIG_SSB=y
+CONFIG_SSFDC=m
+CONFIG_STACKPROTECTOR_PER_TASK=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STAGING_MEDIA_DEPRECATED=y
+CONFIG_STAGING_MEDIA=y
+CONFIG_STAGING=y
+CONFIG_STK3310=m
+CONFIG_STK8312=m
+CONFIG_STK8BA50=m
+CONFIG_STM32_ADC_CORE=m
+CONFIG_STM32_ADC=m
+CONFIG_STM32_DAC_CORE=m
+CONFIG_STM32_DAC=m
+CONFIG_STM32_DFSDM_ADC=m
+CONFIG_STM32_DFSDM_CORE=m
+CONFIG_STM32_DMA3=m
+CONFIG_STM32_DMAMUX=y
+CONFIG_STM32_DMA=y
+CONFIG_STM32_FMC2_EBI=m
+CONFIG_STM32_MDMA=y
+CONFIG_STM32MP_EXTI=m
+CONFIG_STM32_RPROC=m
+CONFIG_STM32_WATCHDOG=m
+CONFIG_STM_DUMMY=m
+CONFIG_STM=m
+CONFIG_STMP_DEVICE=y
+CONFIG_STM_PROTO_BASIC=m
+CONFIG_STM_PROTO_SYS_T=m
+CONFIG_STM_SOURCE_CONSOLE=m
+CONFIG_STM_SOURCE_HEARTBEAT=m
+CONFIG_STREAM_PARSER=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+CONFIG_ST_THERMAL=m
+CONFIG_ST_THERMAL_MEMMAP=m
+CONFIG_STUB_CLK_HI6220=y
+CONFIG_ST_UVIS25_I2C=m
+CONFIG_ST_UVIS25=m
+CONFIG_ST_UVIS25_SPI=m
+CONFIG_SUN20I_GPADC=m
+CONFIG_SUN20I_PPU=y
+CONFIG_SUN4I_GPADC=m
+CONFIG_SUN4I_TIMER=y
+CONFIG_SUN50I_A100_CCU=y
+CONFIG_SUN50I_A100_R_CCU=y
+CONFIG_SUN50I_A64_CCU=y
+CONFIG_SUN50I_DE2_BUS=y
+CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
+CONFIG_SUN50I_H616_CCU=y
+CONFIG_SUN50I_H6_CCU=y
+CONFIG_SUN50I_H6_R_CCU=y
+CONFIG_SUN50I_IOMMU=y
+CONFIG_SUN55I_A523_CCU=m
+CONFIG_SUN55I_A523_MCU_CCU=m
+CONFIG_SUN55I_A523_R_CCU=m
+CONFIG_SUN6I_MSGBOX=y
+CONFIG_SUN6I_R_INTC=y
+CONFIG_SUN6I_RTC_CCU=m
+CONFIG_SUN8I_DE2_CCU=y
+CONFIG_SUN8I_H3_CCU=y
+CONFIG_SUN8I_R_CCU=y
+CONFIG_SUN8I_THERMAL=m
+CONFIG_SUNXI_CCU=y
+CONFIG_SUNXI_MBUS=y
+CONFIG_SUNXI_NMI_INTC=y
+CONFIG_SUNXI_RSB=y
+CONFIG_SUNXI_SRAM=y
+CONFIG_SUNXI_WATCHDOG=m
+CONFIG_SURFACE_3_POWER_OPREGION=m
+CONFIG_SURFACE_ACPI_NOTIFY=m
+CONFIG_SURFACE_AGGREGATOR_BUS=y
+CONFIG_SURFACE_AGGREGATOR_CDEV=m
+CONFIG_SURFACE_AGGREGATOR_HUB=m
+CONFIG_SURFACE_AGGREGATOR=m
+CONFIG_SURFACE_AGGREGATOR_REGISTRY=m
+CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m
+CONFIG_SURFACE_DTX=m
+CONFIG_SURFACE_GPE=m
+CONFIG_SURFACE_HOTPLUG=m
+CONFIG_SURFACE_PLATFORM_PROFILE=m
+CONFIG_SURFACE_PLATFORMS=y
+CONFIG_SURFACE_PRO3_BUTTON=m
+CONFIG_SVC_I3C_MASTER=m
+CONFIG_SWP_EMULATION=y
+CONFIG_SX9310=m
+CONFIG_SX9324=m
+CONFIG_SX9360=m
+CONFIG_SX9500=m
+CONFIG_SX_COMMON=m
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCON_REBOOT_MODE=y
+CONFIG_SYSC_R8A774A1=y
+CONFIG_SYSC_R8A774B1=y
+CONFIG_SYSC_R8A774C0=y
+CONFIG_SYSC_R8A774E1=y
+CONFIG_SYSC_R8A7795=y
+CONFIG_SYSC_R8A77960=y
+CONFIG_SYSC_R8A77961=y
+CONFIG_SYSC_R8A77965=y
+CONFIG_SYSC_R8A77970=y
+CONFIG_SYSC_R8A77980=y
+CONFIG_SYSC_R8A77990=y
+CONFIG_SYSC_R8A77995=y
+CONFIG_SYSC_R8A779A0=y
+CONFIG_SYSC_R8A779F0=y
+CONFIG_SYSC_R8A779G0=y
+CONFIG_SYSC_RCAR_GEN4=y
+CONFIG_SYSC_RCAR=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFB_SIMPLEFB=y
+CONFIG_SYSFB=y
+CONFIG_SYS_SUPPORTS_SH_CMT=y
+CONFIG_SYS_SUPPORTS_SH_TMU=y
+CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y
+CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
+CONFIG_SYSTEM_BLACKLIST_KEYRING=y
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_T5403=m
+CONFIG_TABLET_USB_ACECAD=m
+CONFIG_TABLET_USB_AIPTEK=m
+CONFIG_TABLET_USB_KBTAB=m
+CONFIG_TABLET_USB_PEGASUS=m
+CONFIG_TAP=m
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASKS_RCU=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_XACCT=y
+CONFIG_TCG_TIS_CORE=m
+CONFIG_TCG_TIS_I2C_ATMEL=m
+CONFIG_TCG_TIS_I2C_CR50=m
+CONFIG_TCG_TIS_I2C_INFINEON=m
+CONFIG_TCG_TIS_I2C=m
+CONFIG_TCG_TIS_I2C_NUVOTON=m
+CONFIG_TCG_TIS_SPI=m
+CONFIG_TCG_TIS_ST33ZP24_I2C=m
+CONFIG_TCG_TIS_ST33ZP24=m
+CONFIG_TCG_TIS_ST33ZP24_SPI=m
+CONFIG_TCG_TIS_SYNQUACER=m
+CONFIG_TCG_TPM=m
+CONFIG_TCG_VTPM_PROXY=m
+CONFIG_TCS3414=m
+CONFIG_TCS3472=m
+CONFIG_TEE_BNXT_FW=m
+CONFIG_TEE_STMM_EFI=m
+CONFIG_TEE=y
+CONFIG_TEGRA186_GPC_DMA=m
+CONFIG_TEGRA186_TIMER=y
+CONFIG_TEGRA20_APB_DMA=y
+CONFIG_TEGRA210_ADMA=m
+CONFIG_TEGRA210_ADMA=y
+CONFIG_TEGRA210_EMC=m
+CONFIG_TEGRA210_EMC_TABLE=y
+CONFIG_TEGRA241_CMDQV=y
+CONFIG_TEGRA_ACONNECT=m
+CONFIG_TEGRA_AHB=y
+CONFIG_TEGRA_BPMP_THERMAL=m
+CONFIG_TEGRA_BPMP=y
+CONFIG_TEGRA_CLK_DFLL=y
+CONFIG_TEGRA_HOST1X_CONTEXT_BUS=y
+CONFIG_TEGRA_HOST1X_FIREWALL=y
+CONFIG_TEGRA_HOST1X=m
+CONFIG_TEGRA_HSP_MBOX=y
+CONFIG_TEGRA_IOMMU_SMMU=y
+CONFIG_TEGRA_IVC=y
+CONFIG_TEGRA_MC=y
+CONFIG_TEGRA_SOCTHERM=y
+CONFIG_TEGRA_TIMER=y
+CONFIG_TEGRA_WATCHDOG=m
+CONFIG_TERANETICS_PHY=m
+CONFIG_TESLA_FSD_COMMON_CLK=y
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_MMIO=m
+CONFIG_THERMAL_NETLINK=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL=y
+CONFIG_THP_SWAP=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_THUNDERX2_PMU=m
+CONFIG_TI_ADC081C=m
+CONFIG_TI_ADC0832=m
+CONFIG_TI_ADC084S021=m
+CONFIG_TI_ADC108S102=m
+CONFIG_TI_ADC12138=m
+CONFIG_TI_ADC128S052=m
+CONFIG_TI_ADC161S626=m
+CONFIG_TI_ADS1015=m
+CONFIG_TI_ADS1100=m
+CONFIG_TI_ADS1119=m
+CONFIG_TI_ADS124S08=m
+CONFIG_TI_ADS1298=m
+CONFIG_TI_ADS131E08=m
+CONFIG_TI_ADS7138=m
+CONFIG_TI_ADS7924=m
+CONFIG_TI_ADS7950=m
+CONFIG_TI_ADS8344=m
+CONFIG_TI_ADS8688=m
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TI_DAC082S085=m
+CONFIG_TI_DAC5571=m
+CONFIG_TI_DAC7311=m
+CONFIG_TI_DAC7612=m
+CONFIG_TIFM_7XX1=m
+CONFIG_TIFM_CORE=m
+CONFIG_TI_K3_DSP_REMOTEPROC=m
+CONFIG_TI_K3_M4_REMOTEPROC=m
+CONFIG_TI_K3_R5_REMOTEPROC=m
+CONFIG_TI_K3_RINGACC=y
+CONFIG_TI_K3_SOCINFO=y
+CONFIG_TI_LMP92064=m
+CONFIG_TIMER_ACPI=y
+CONFIG_TIMER_IMX_SYS_CTR=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TI_MESSAGE_MANAGER=y
+CONFIG_TINYDRM_HX8357D=m
+CONFIG_TINYDRM_ILI9163=m
+CONFIG_TINYDRM_ILI9225=m
+CONFIG_TINYDRM_ILI9341=m
+CONFIG_TINYDRM_ILI9486=m
+CONFIG_TINYDRM_MI0283QT=m
+CONFIG_TINYDRM_REPAPER=m
+CONFIG_TINYDRM_ST7586=m
+CONFIG_TINYDRM_ST7735R=m
+CONFIG_TI_PRUSS_INTC=m
+CONFIG_TI_PRUSS=m
+CONFIG_TI_SCI_INTA_IRQCHIP=y
+CONFIG_TI_SCI_INTA_MSI_DOMAIN=y
+CONFIG_TI_SCI_INTR_IRQCHIP=y
+CONFIG_TI_SCI_PM_DOMAINS=m
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_TI_ST=m
+CONFIG_TI_SYSCON_CLK=y
+CONFIG_TI_SYSC=y
+CONFIG_TI_TLC4541=m
+CONFIG_TI_TMAG5273=m
+CONFIG_TI_TSC2046=m
+CONFIG_TMD_HERMES=m
+CONFIG_TMP006=m
+CONFIG_TMP007=m
+CONFIG_TMP117=m
+CONFIG_TOOLS_SUPPORT_RELR=y
+CONFIG_TORTURE_TEST=m
+CONFIG_TOUCHSCREEN_ADC=m
+CONFIG_TOUCHSCREEN_APPLE_Z2=m
+CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
+CONFIG_TOUCHSCREEN_CYTTSP5=m
+CONFIG_TOUCHSCREEN_ELAN=m
+CONFIG_TOUCHSCREEN_ELO=m
+CONFIG_TOUCHSCREEN_FUJITSU=m
+CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C=m
+CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI=m
+CONFIG_TOUCHSCREEN_GUNZE=m
+CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m
+CONFIG_TOUCHSCREEN_HIMAX_HX852X=m
+CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
+CONFIG_TOUCHSCREEN_HYNITRON_CST816X=m
+CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=m
+CONFIG_TOUCHSCREEN_ILITEK=m
+CONFIG_TOUCHSCREEN_IMAGIS=m
+CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
+CONFIG_TOUCHSCREEN_INEXIO=m
+CONFIG_TOUCHSCREEN_IPROC=m
+CONFIG_TOUCHSCREEN_IQS7211=m
+CONFIG_TOUCHSCREEN_MAX11801=m
+CONFIG_TOUCHSCREEN_MC13783=m
+CONFIG_TOUCHSCREEN_MSG2638=m
+CONFIG_TOUCHSCREEN_MTOUCH=m
+CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS=m
+CONFIG_TOUCHSCREEN_PENMOUNT=m
+CONFIG_TOUCHSCREEN_PIXCIR=m
+CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m
+CONFIG_TOUCHSCREEN_RM_TS=m
+CONFIG_TOUCHSCREEN_ROHM_BU21023=m
+CONFIG_TOUCHSCREEN_ST1232=m
+CONFIG_TOUCHSCREEN_STMFTS=m
+CONFIG_TOUCHSCREEN_SUN4I=m
+CONFIG_TOUCHSCREEN_SUR40=m
+CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
+CONFIG_TOUCHSCREEN_TOUCHIT213=m
+CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
+CONFIG_TOUCHSCREEN_TOUCHWIN=m
+CONFIG_TOUCHSCREEN_TSC_SERIO=m
+CONFIG_TOUCHSCREEN_USB_3M=y
+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
+CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
+CONFIG_TOUCHSCREEN_USB_E2I=y
+CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
+CONFIG_TOUCHSCREEN_USB_EGALAX=y
+CONFIG_TOUCHSCREEN_USB_ELO=y
+CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
+CONFIG_TOUCHSCREEN_USB_ETURBO=y
+CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
+CONFIG_TOUCHSCREEN_USB_GOTOP=y
+CONFIG_TOUCHSCREEN_USB_GUNZE=y
+CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
+CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
+CONFIG_TOUCHSCREEN_USB_ITM=y
+CONFIG_TOUCHSCREEN_USB_JASTEC=y
+CONFIG_TOUCHSCREEN_USB_NEXIO=y
+CONFIG_TOUCHSCREEN_USB_PANJIT=y
+CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
+CONFIG_TOUCHSCREEN_WACOM_I2C=m
+CONFIG_TOUCHSCREEN_WACOM_W8001=m
+CONFIG_TOUCHSCREEN_ZFORCE=m
+CONFIG_TOUCHSCREEN_ZINITIX=m
+CONFIG_TPL0102=m
+CONFIG_TPS6594_ESM=m
+CONFIG_TPS6594_PFSM=m
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANS_TABLE=y
+CONFIG_TRUSTED_KEYS_DCP=y
+CONFIG_TRUSTED_KEYS=m
+CONFIG_TRUSTED_KEYS_TEE=y
+CONFIG_TRUSTED_KEYS_TPM=y
+CONFIG_TSL2583=m
+CONFIG_TSL2591=m
+CONFIG_TSL2772=m
+CONFIG_TSL4531=m
+CONFIG_TSYS01=m
+CONFIG_TSYS02D=m
+CONFIG_TTPCI_EEPROM=m
+CONFIG_TUN=m
+CONFIG_TYPEC_ANX7411=m
+CONFIG_TYPEC_DP_ALTMODE=m
+CONFIG_TYPEC_FUSB302=m
+CONFIG_TYPEC_MUX_FSA4480=m
+CONFIG_TYPEC_MUX_GPIO_SBU=m
+CONFIG_TYPEC_MUX_IT5205=m
+CONFIG_TYPEC_MUX_NB7VPQ904M=m
+CONFIG_TYPEC_MUX_PI3USB30532=m
+CONFIG_TYPEC_MUX_PS883X=m
+CONFIG_TYPEC_MUX_PTN36502=m
+CONFIG_TYPEC_MUX_WCD939X_USBSS=m
+CONFIG_TYPEC_NVIDIA_ALTMODE=m
+CONFIG_TYPEC_QCOM_PMIC=m
+CONFIG_TYPEC_RT1711H=m
+CONFIG_TYPEC_RT1719=m
+CONFIG_TYPEC_STUSB160X=m
+CONFIG_TYPEC_TBT_ALTMODE=m
+CONFIG_TYPEC_TCPCI=m
+CONFIG_TYPEC_TCPCI_MAXIM=m
+CONFIG_TYPEC_TCPCI_MT6370=m
+CONFIG_TYPEC_TCPM=m
+CONFIG_TYPEC_UCSI=m
+CONFIG_TYPEC_WUSB3801=m
+CONFIG_TYPEC=y
+CONFIG_UACCE=m
+CONFIG_UCC_FAST=y
+CONFIG_UCC_SLOW=y
+CONFIG_UCC=y
+CONFIG_UCLAMP_BUCKETS_COUNT=5
+CONFIG_UCLAMP_TASK_GROUP=y
+CONFIG_UCLAMP_TASK=y
+CONFIG_UCS2_STRING=y
+CONFIG_UCSI_ACPI=m
+CONFIG_UCSI_CCG=m
+CONFIG_UCSI_LENOVO_YOGA_C630=m
+CONFIG_UCSI_PMIC_GLINK=m
+CONFIG_UCSI_STM32G0=m
+CONFIG_UDMABUF=y
+CONFIG_UEFI_CPER_ARM=y
+CONFIG_UEFI_CPER=y
+CONFIG_UID16=y
+CONFIG_UIO_CIF=m
+CONFIG_UIO_HV_GENERIC=m
+CONFIG_UIO_SERCOS3=m
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNIPHIER_SYSTEM_BUS=y
+CONFIG_UNIPHIER_THERMAL=y
+CONFIG_UNIPHIER_WATCHDOG=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_US5182D=m
+CONFIG_USB4=m
+CONFIG_USB_ACM=m
+CONFIG_USB_ADUTUX=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_APPLEDISPLAY=m
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_ATM=m
+CONFIG_USB_AUDIO=m
+CONFIG_USB_BDC_UDC=m
+CONFIG_USB_BELKIN=y
+CONFIG_USB_C67X00_HCD=m
+CONFIG_USB_CATC=m
+CONFIG_USB_CDC_COMPOSITE=m
+CONFIG_USB_CDC_PHONET=m
+CONFIG_USB_CDNS2_UDC=m
+CONFIG_USB_CDNS_HOST=y
+CONFIG_USB_CDNSP_GADGET=y
+CONFIG_USB_CDNSP_HOST=y
+CONFIG_USB_CDNSP_PCI=m
+CONFIG_USB_CDNS_SUPPORT=m
+CONFIG_USB_CHIPIDEA_GENERIC=m
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_IMX=m
+CONFIG_USB_CHIPIDEA=m
+CONFIG_USB_CHIPIDEA_MSM=m
+CONFIG_USB_CHIPIDEA_NPCM=m
+CONFIG_USB_CHIPIDEA_PCI=m
+CONFIG_USB_CHIPIDEA_TEGRA=m
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_MIDI2=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_USB_CONFIGFS_F_PRINTER=y
+CONFIG_USB_CONFIGFS_F_TCM=y
+CONFIG_USB_CONFIGFS_F_UAC1=y
+CONFIG_USB_CONFIGFS_F_UAC2=y
+CONFIG_USB_CONFIGFS_F_UVC=y
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_PHONET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONN_GPIO=y
+CONFIG_USB_CXACRU=m
+CONFIG_USB_CYPRESS_CY7C63=m
+CONFIG_USB_CYTHERM=m
+CONFIG_USB_DSBR=m
+CONFIG_USB_DWC2_HOST=y
+CONFIG_USB_DWC2_PCI=m
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3_AM62=m
+CONFIG_USB_DWC3_EXYNOS=m
+CONFIG_USB_DWC3_GENERIC_PLAT=m
+CONFIG_USB_DWC3_HAPS=y
+CONFIG_USB_DWC3_HOST=y
+CONFIG_USB_DWC3_IMX8MP=m
+CONFIG_USB_DWC3_KEYSTONE=y
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_DWC3_OF_SIMPLE=m
+CONFIG_USB_DWC3_PCI=y
+CONFIG_USB_DWC3_QCOM=m
+CONFIG_USB_DWC3_RTK=m
+CONFIG_USB_DWC3_ULPI=y
+CONFIG_USB_DWC3_XILINX=m
+CONFIG_USB_DWC3=y
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_EHCI_EXYNOS=m
+CONFIG_USB_EHCI_FSL=m
+CONFIG_USB_EHCI_HCD_NPCM7XX=m
+CONFIG_USB_EHCI_HCD_ORION=m
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MV=m
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TEGRA=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMXX=m
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_EZUSB_FX2=m
+CONFIG_USB_F_ACM=m
+CONFIG_USB_F_ECM=m
+CONFIG_USB_FEW_INIT_RETRIES=y
+CONFIG_USB_F_FS=m
+CONFIG_USB_F_HID=m
+CONFIG_USB_F_MASS_STORAGE=m
+CONFIG_USB_F_MIDI=m
+CONFIG_USB_F_NCM=m
+CONFIG_USB_F_OBEX=m
+CONFIG_USB_F_PHONET=m
+CONFIG_USB_F_PRINTER=m
+CONFIG_USB_F_RNDIS=m
+CONFIG_USB_F_SERIAL=m
+CONFIG_USB_F_SS_LB=m
+CONFIG_USB_F_SUBSET=m
+CONFIG_USB_F_UAC1_LEGACY=m
+CONFIG_USB_FUNCTIONFS_GENERIC=y
+CONFIG_USB_FUNCTIONFS=m
+CONFIG_USB_F_UVC=m
+CONFIG_USB_G_ACM_MS=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_GADGET=m
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_G_HID=m
+CONFIG_USB_GL860=m
+CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_RNDIS=y
+CONFIG_USB_G_NCM=m
+CONFIG_USB_G_NOKIA=m
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_GSPCA_BENQ=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_CPIA1=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_JEILINJ=m
+CONFIG_USB_GSPCA_JL2005BCD=m
+CONFIG_USB_GSPCA_KINECT=m
+CONFIG_USB_GSPCA_KONICA=m
+CONFIG_USB_GSPCA=m
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_MR97310A=m
+CONFIG_USB_GSPCA_NW80X=m
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534_9=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7302=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SE401=m
+CONFIG_USB_GSPCA_SN9C2028=m
+CONFIG_USB_GSPCA_SN9C20X=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA1528=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+CONFIG_USB_GSPCA_SQ905C=m
+CONFIG_USB_GSPCA_SQ905=m
+CONFIG_USB_GSPCA_SQ930X=m
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_STK1135=m
+CONFIG_USB_GSPCA_STV0680=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TOPRO=m
+CONFIG_USB_GSPCA_TOUPTEK=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+CONFIG_USB_GSPCA_VICAM=m
+CONFIG_USB_GSPCA_XIRLINK_CIT=m
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_USB_G_WEBCAM=m
+CONFIG_USB_HCD_BCMA=m
+CONFIG_USB_HCD_SSB=m
+CONFIG_USB_HSIC_USB3503=y
+CONFIG_USB_HSIC_USB4604=m
+CONFIG_USB_HSO=m
+CONFIG_USB_IDMOUSE=m
+CONFIG_USB_IOWARRIOR=m
+CONFIG_USBIP_CORE=m
+CONFIG_USB_IPHETH=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_VHCI_HC_PORTS=8
+CONFIG_USBIP_VHCI_NR_HCS=1
+CONFIG_USB_ISIGHTFW=m
+CONFIG_USB_ISP116X_HCD=m
+CONFIG_USB_ISP1301=m
+CONFIG_USB_ISP1760_HCD=y
+CONFIG_USB_ISP1760_HOST_ROLE=y
+CONFIG_USB_ISP1760=y
+CONFIG_USB_KAWETH=m
+CONFIG_USB_KC2190=y
+CONFIG_USB_LAN78XX=m
+CONFIG_USB_LCD=m
+CONFIG_USB_LD=m
+CONFIG_USB_LEDS_TRIGGER_USBPORT=m
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LIBCOMPOSITE=m
+CONFIG_USB_LJCA=m
+CONFIG_USB_M5602=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_MAX3421_HCD=m
+CONFIG_USB_MDC800=m
+CONFIG_USB_MICROTEK=m
+CONFIG_USB_MIDI_GADGET=m
+CONFIG_USB_MON=m
+CONFIG_USB_MR800=m
+CONFIG_USB_MTU3_DUAL_ROLE=y
+CONFIG_USB_MTU3=m
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_MEDIATEK=m
+CONFIG_USB_MUSB_SUNXI=m
+CONFIG_USB_MXS_PHY=m
+CONFIG_USB_NET_AQC111=m
+CONFIG_USB_NET_AX88179_178A=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_MBIM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_NET_CH9200=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_SR9700=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_OHCI_EXYNOS=m
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ONBOARD_HUB=m
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OXU210HP_HCD=m
+CONFIG_USBPCWATCHDOG=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_PHY=y
+CONFIG_USB_PRINTER=m
+CONFIG_USB_PWC_INPUT_EVDEV=y
+CONFIG_USB_PWC=m
+CONFIG_USB_QCOM_EUD=m
+CONFIG_USB_R8A66597_HCD=m
+CONFIG_USB_RAW_GADGET=m
+CONFIG_USB_RENESAS_USB3=m
+CONFIG_USB_RENESAS_USBF=m
+CONFIG_USB_RENESAS_USBHS_HCD=m
+CONFIG_USB_RENESAS_USBHS=m
+CONFIG_USB_RENESAS_USBHS_UDC=m
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_RTL8153_ECM=m
+CONFIG_USB_RZV2M_USB3DRD=m
+CONFIG_USB_S2255=m
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_F8153X=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_METRO=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MXUPORT=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QT2=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SAFE=m
+CONFIG_USB_SERIAL_SAFE_PADDED=y
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SIMPLE=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_UPD78F0730=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_WISHBONE=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_XR=m
+CONFIG_USB_SERIAL_XSENS_MT=m
+CONFIG_USB_SEVSEG=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_SL811_HCD=m
+CONFIG_USB_SNP_CORE=m
+CONFIG_USB_SNP_UDC_PLAT=m
+CONFIG_USB_SPEEDTOUCH=m
+CONFIG_USB_STORAGE_ALAUDA=m
+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_ENE_UB6250=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_KARMA=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_STORAGE_ONETOUCH=m
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STV06XX=m
+CONFIG_USB_TEGRA_PHY=y
+CONFIG_USB_TEST=m
+CONFIG_USB_TMC=m
+CONFIG_USB_TRANCEVIBRATOR=m
+CONFIG_USB_UEAGLEATM=m
+CONFIG_USB_U_ETHER=m
+CONFIG_USB_UHCI_HCD=m
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_USBIO=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_U_SERIAL=m
+CONFIG_USB_USS720=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VL600=m
+CONFIG_USB_WDM=m
+CONFIG_USB_XHCI_HCD=m
+CONFIG_USB_XHCI_HISTB=m
+CONFIG_USB_XHCI_MTK=m
+CONFIG_USB_XHCI_MVEBU=m
+CONFIG_USB_XHCI_PCI=m
+CONFIG_USB_XHCI_PLATFORM=m
+CONFIG_USB_XHCI_RCAR=m
+CONFIG_USB_XHCI_RZV2M=y
+CONFIG_USB_XHCI_TEGRA=m
+CONFIG_USB_XUSBATM=m
+CONFIG_USB=y
+CONFIG_USB_YUREX=m
+CONFIG_USB_ZD1201=m
+CONFIG_USB_ZERO_HNPTEST=y
+CONFIG_USB_ZERO=m
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+CONFIG_USER_DECRYPTED_DATA=y
+CONFIG_USERIO=m
+CONFIG_UVC_COMMON=m
+CONFIG_UX500_PM_DOMAIN=y
+CONFIG_V4L2_ASYNC=m
+CONFIG_V4L2_FWNODE=m
+CONFIG_V4L2_H264=m
+CONFIG_V4L2_JPEG_HELPER=m
+CONFIG_V4L2_LOOPBACK=m
+CONFIG_V4L2_MEM2MEM_DEV=m
+CONFIG_V4L2_VP9=m
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VBOXGUEST=m
+CONFIG_VCHIQ_CDEV=y
+CONFIG_VCNL3020=m
+CONFIG_VCNL4000=m
+CONFIG_VCNL4035=m
+CONFIG_VCPU_STALL_DETECTOR=m
+CONFIG_VEML6030=m
+CONFIG_VEML6040=m
+CONFIG_VEML6046X00=m
+CONFIG_VEML6070=m
+CONFIG_VEML6075=m
+CONFIG_VETH=m
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_VF610_ADC=m
+CONFIG_VF610_DAC=m
+CONFIG_VFIO_AMBA=m
+CONFIG_VFIO_CDX=m
+CONFIG_VFIO_CONTAINER=y
+CONFIG_VFIO_DEVICE_CDEV=y
+CONFIG_VFIO_GROUP=y
+CONFIG_VFIO_IOMMU_TYPE1=m
+CONFIG_VFIO=m
+CONFIG_VFIO_NOIOMMU=y
+CONFIG_VFIO_PCI_CORE=m
+CONFIG_VFIO_PCI_INTX=y
+CONFIG_VFIO_PCI=m
+CONFIG_VFIO_PCI_MMAP=y
+CONFIG_VFIO_PLATFORM_BASE=m
+CONFIG_VFIO_VIRQFD=y
+CONFIG_VGA_ARB_MAX_GPUS=8
+CONFIG_VHOST_IOTLB=m
+CONFIG_VHOST=m
+CONFIG_VHOST_TASK=y
+CONFIG_VIDEO_ADV7170=m
+CONFIG_VIDEO_ADV7175=m
+CONFIG_VIDEO_ADV7180=m
+CONFIG_VIDEO_ADV7183=m
+CONFIG_VIDEO_ADV7343=m
+CONFIG_VIDEO_ADV7393=m
+CONFIG_VIDEO_ADV748X=m
+CONFIG_VIDEO_ADV7604_CEC=y
+CONFIG_VIDEO_ADV7604=m
+CONFIG_VIDEO_ADV7842_CEC=y
+CONFIG_VIDEO_ADV7842=m
+CONFIG_VIDEO_AK881X=m
+CONFIG_VIDEO_ALLEGRO_DVT=m
+CONFIG_VIDEO_ALVIUM_CSI2=m
+CONFIG_VIDEO_AMPHION_VPU=m
+CONFIG_VIDEO_AR0521=m
+CONFIG_VIDEO_AU0828=m
+CONFIG_VIDEO_AU0828_V4L2=y
+CONFIG_VIDEO_BCM2835=m
+CONFIG_VIDEO_BCM2835_UNICAM=m
+CONFIG_VIDEO_BT819=m
+CONFIG_VIDEO_BT848=m
+CONFIG_VIDEO_BT856=m
+CONFIG_VIDEO_BT866=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_DMA_CONTIG=m
+CONFIG_VIDEOBUF2_DMA_SG=m
+CONFIG_VIDEOBUF2_DVB=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_V4L2=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEOBUF_DMA_SG=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEO_CADENCE_CSI2RX=m
+CONFIG_VIDEO_CADENCE_CSI2TX=m
+CONFIG_VIDEO_CAFE_CCIC=m
+CONFIG_VIDEO_CAMERA_SENSOR=y
+CONFIG_VIDEO_CCS=m
+CONFIG_VIDEO_CCS_PLL=m
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEO_CODA=m
+CONFIG_VIDEO_CS3308=m
+CONFIG_VIDEO_CS5345=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_CX18=m
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX2341X=m
+CONFIG_VIDEO_CX23885=m
+CONFIG_VIDEO_CX25840=m
+CONFIG_VIDEO_CX88_ALSA=m
+CONFIG_VIDEO_CX88_BLACKBIRD=m
+CONFIG_VIDEO_CX88_DVB=m
+CONFIG_VIDEO_CX88_ENABLE_VP3054=y
+CONFIG_VIDEO_CX88=m
+CONFIG_VIDEO_CX88_MPEG=m
+CONFIG_VIDEO_CX88_VP3054=m
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_DS90UB913=m
+CONFIG_VIDEO_DS90UB953=m
+CONFIG_VIDEO_DS90UB960=m
+CONFIG_VIDEO_DW100=m
+CONFIG_VIDEO_DW9719=m
+CONFIG_VIDEO_DW9768=m
+CONFIG_VIDEO_E5010_JPEG_ENC=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_RC=m
+CONFIG_VIDEO_EM28XX_V4L2=m
+CONFIG_VIDEO_EXYNOS4_FIMC_IS=m
+CONFIG_VIDEO_EXYNOS4_IS_COMMON=m
+CONFIG_VIDEO_EXYNOS4_ISP_DMA_CAPTURE=y
+CONFIG_VIDEO_FB_IVTV=m
+CONFIG_VIDEO_GC0308=m
+CONFIG_VIDEO_GC0310=m
+CONFIG_VIDEO_GC05A2=m
+CONFIG_VIDEO_GC08A3=m
+CONFIG_VIDEO_GC2145=m
+CONFIG_VIDEO_HANTRO_HEVC_RFC=y
+CONFIG_VIDEO_HANTRO_IMX8M=y
+CONFIG_VIDEO_HANTRO=m
+CONFIG_VIDEO_HANTRO_ROCKCHIP=y
+CONFIG_VIDEO_HANTRO_STM32MP25=y
+CONFIG_VIDEO_HANTRO_SUNXI=y
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_HEXIUM_GEMINI=m
+CONFIG_VIDEO_HEXIUM_ORION=m
+CONFIG_VIDEO_HI846=m
+CONFIG_VIDEO_HI847=m
+CONFIG_VIDEO_I2C=m
+CONFIG_VIDEO_IMX208=m
+CONFIG_VIDEO_IMX214=m
+CONFIG_VIDEO_IMX283=m
+CONFIG_VIDEO_IMX296=m
+CONFIG_VIDEO_IMX334=m
+CONFIG_VIDEO_IMX335=m
+CONFIG_VIDEO_IMX412=m
+CONFIG_VIDEO_IMX415=m
+CONFIG_VIDEO_IMX7_CSI=m
+CONFIG_VIDEO_IMX8_ISI=m
+CONFIG_VIDEO_IMX8_ISI_M2M=y
+CONFIG_VIDEO_IMX8_JPEG=m
+CONFIG_VIDEO_IMX8MQ_MIPI_CSI2=m
+CONFIG_VIDEO_IMX_MEDIA=m
+CONFIG_VIDEO_IMX_MIPI_CSIS=m
+CONFIG_VIDEO_IMX_PXP=m
+CONFIG_VIDEO_IR_I2C=m
+CONFIG_VIDEO_ISL7998X=m
+CONFIG_VIDEO_IVTV_ALSA=m
+CONFIG_VIDEO_IVTV=m
+CONFIG_VIDEO_KS0127=m
+CONFIG_VIDEO_LT6911UXE=m
+CONFIG_VIDEO_M52790=m
+CONFIG_VIDEO_MAX9271_LIB=m
+CONFIG_VIDEO_MAX9286=m
+CONFIG_VIDEO_MAX96712=m
+CONFIG_VIDEO_MAX96714=m
+CONFIG_VIDEO_MAX96717=m
+CONFIG_VIDEO_MEDIATEK_MDP3=m
+CONFIG_VIDEO_MEDIATEK_VPU=m
+CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
+CONFIG_VIDEO_MESON_GE2D=m
+CONFIG_VIDEO_MESON_VDEC=m
+CONFIG_VIDEO_MGB4=m
+CONFIG_VIDEO_ML86V7667=m
+CONFIG_VIDEO_MMP_CAMERA=m
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_MT9M114=m
+CONFIG_VIDEO_MT9V011=m
+CONFIG_VIDEO_MUX=m
+CONFIG_VIDEO_MXB=m
+CONFIG_VIDEO_NOMODESET=y
+CONFIG_VIDEO_NPCM_VCD_ECE=m
+CONFIG_VIDEO_OG01A1B=m
+CONFIG_VIDEO_OG0VE1B=m
+CONFIG_VIDEO_OV01A10=m
+CONFIG_VIDEO_OV02A10=m
+CONFIG_VIDEO_OV08D10=m
+CONFIG_VIDEO_OV08X40=m
+CONFIG_VIDEO_OV13B10=m
+CONFIG_VIDEO_OV2640=m
+CONFIG_VIDEO_OV2735=m
+CONFIG_VIDEO_OV4689=m
+CONFIG_VIDEO_OV5648=m
+CONFIG_VIDEO_OV5693=m
+CONFIG_VIDEO_OV6211=m
+CONFIG_VIDEO_OV64A40=m
+CONFIG_VIDEO_OV7670=m
+CONFIG_VIDEO_OV8858=m
+CONFIG_VIDEO_OV8865=m
+CONFIG_VIDEO_OV9282=m
+CONFIG_VIDEO_OV9734=m
+CONFIG_VIDEO_PVRUSB2_DVB=y
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_QCOM_CAMSS=m
+CONFIG_VIDEO_QCOM_IRIS=m
+CONFIG_VIDEO_QCOM_VENUS=m
+CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m
+CONFIG_VIDEO_RCAR_ISP=m
+CONFIG_VIDEO_RCAR_VIN=m
+CONFIG_VIDEO_RDACM20=m
+CONFIG_VIDEO_RDACM21=m
+CONFIG_VIDEO_RENESAS_FCP=m
+CONFIG_VIDEO_RENESAS_FDP1=m
+CONFIG_VIDEO_RENESAS_JPU=m
+CONFIG_VIDEO_RENESAS_VSP1=m
+CONFIG_VIDEO_ROCKCHIP_ISP1=m
+CONFIG_VIDEO_ROCKCHIP_RGA=m
+CONFIG_VIDEO_ROCKCHIP_VDEC=m
+CONFIG_VIDEO_RZG2L_CRU=m
+CONFIG_VIDEO_RZG2L_CSI2=m
+CONFIG_VIDEO_S5P_FIMC=m
+CONFIG_VIDEO_S5P_MIPI_CSIS=m
+CONFIG_VIDEO_SAA6588=m
+CONFIG_VIDEO_SAA6752HS=m
+CONFIG_VIDEO_SAA7110=m
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_SAA7127=m
+CONFIG_VIDEO_SAA7134_ALSA=m
+CONFIG_VIDEO_SAA7134_DVB=m
+CONFIG_VIDEO_SAA7134=m
+CONFIG_VIDEO_SAA7134_RC=y
+CONFIG_VIDEO_SAA7146=m
+CONFIG_VIDEO_SAA7146_VV=m
+CONFIG_VIDEO_SAA717X=m
+CONFIG_VIDEO_SAA7185=m
+CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS=m
+CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
+CONFIG_VIDEO_SAMSUNG_S5P_G2D=m
+CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
+CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
+CONFIG_VIDEO_SONY_BTF_MPX=m
+CONFIG_VIDEO_STK1160=m
+CONFIG_VIDEO_STM32_CSI=m
+CONFIG_VIDEO_STM32_DCMI=m
+CONFIG_VIDEO_STM32_DCMIPP=m
+CONFIG_VIDEO_STM32_DMA2D=m
+CONFIG_VIDEO_ST_VGXY61=m
+CONFIG_VIDEO_SUN4I_CSI=m
+CONFIG_VIDEO_SUN6I_CSI=m
+CONFIG_VIDEO_SUN6I_ISP=m
+CONFIG_VIDEO_SUN6I_MIPI_CSI2=m
+CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m
+CONFIG_VIDEO_SUN8I_DEINTERLACE=m
+CONFIG_VIDEO_SUNXI_CEDRUS=m
+CONFIG_VIDEO_SUNXI=y
+CONFIG_VIDEO_SYNOPSYS_HDMIRX_LOAD_DEFAULT_EDID=y
+CONFIG_VIDEO_SYNOPSYS_HDMIRX=m
+CONFIG_VIDEO_TC358743_CEC=y
+CONFIG_VIDEO_TC358743=m
+CONFIG_VIDEO_TC358746=m
+CONFIG_VIDEO_TDA7432=m
+CONFIG_VIDEO_TDA9840=m
+CONFIG_VIDEO_TEA6415C=m
+CONFIG_VIDEO_TEA6420=m
+CONFIG_VIDEO_TEGRA=m
+CONFIG_VIDEO_TEGRA_TPG=y
+CONFIG_VIDEO_TEGRA_VDE=m
+CONFIG_VIDEO_THP7312=m
+CONFIG_VIDEO_THS7303=m
+CONFIG_VIDEO_THS8200=m
+CONFIG_VIDEO_TI_J721E_CSI2RX=m
+CONFIG_VIDEO_TLV320AIC23B=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_TVAUDIO=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TVP514X=m
+CONFIG_VIDEO_TVP5150=m
+CONFIG_VIDEO_TVP7002=m
+CONFIG_VIDEO_TW2804=m
+CONFIG_VIDEO_TW9900=m
+CONFIG_VIDEO_TW9903=m
+CONFIG_VIDEO_TW9906=m
+CONFIG_VIDEO_TW9910=m
+CONFIG_VIDEO_UDA1342=m
+CONFIG_VIDEO_UPD64031A=m
+CONFIG_VIDEO_UPD64083=m
+CONFIG_VIDEO_USBTV=m
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_VIDEO_VGXY61=m
+CONFIG_VIDEO_VP27SMPX=m
+CONFIG_VIDEO_VPX3220=m
+CONFIG_VIDEO_WAVE_VPU=m
+CONFIG_VIDEO_WM8739=m
+CONFIG_VIDEO_WM8775=m
+CONFIG_VIDEO_XILINX_CSI2RXSS=m
+CONFIG_VIDEO_XILINX=m
+CONFIG_VIDEO_XILINX_TPG=m
+CONFIG_VIDEO_XILINX_VTC=m
+CONFIG_VIDEO_ZORAN_AVS6EYES=y
+CONFIG_VIDEO_ZORAN_BUZ=y
+CONFIG_VIDEO_ZORAN_DC10=y
+CONFIG_VIDEO_ZORAN_DC30=y
+CONFIG_VIDEO_ZORAN_LML33R10=y
+CONFIG_VIDEO_ZORAN_LML33=y
+CONFIG_VIDEO_ZORAN=m
+CONFIG_VIDEO_ZORAN_ZR36060=y
+CONFIG_VIRT_DRIVERS=y
+CONFIG_VIRTIO_ANCHOR=y
+CONFIG_VIRTIO_BALLOON=m
+CONFIG_VIRTIO_BLK=m
+CONFIG_VIRTIO_CONSOLE=m
+CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
+CONFIG_VIRTIO_INPUT=m
+CONFIG_VIRTIO_IOMMU=m
+CONFIG_VIRTIO=m
+CONFIG_VIRTIO_MEM=m
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_VIRTIO_MMIO=m
+CONFIG_VIRTIO_NET=m
+CONFIG_VIRTIO_PCI_LIB_LEGACY=m
+CONFIG_VIRTIO_PCI_LIB=m
+CONFIG_VIRTIO_PCI=m
+CONFIG_VIRTIO_PMEM=m
+CONFIG_VIRTUALIZATION=y
+CONFIG_VISCONTI_WATCHDOG=m
+CONFIG_VITESSE_PHY=m
+CONFIG_VL53L0X_I2C=m
+CONFIG_VL6180=m
+CONFIG_VMAP_STACK=y
+CONFIG_VMGENID=m
+CONFIG_VMWARE_VMCI=m
+CONFIG_VMXNET3=m
+CONFIG_VSOCKMON=m
+CONFIG_VXLAN=m
+CONFIG_VZ89X=m
+CONFIG_W1_CON=y
+CONFIG_W1=m
+CONFIG_W1_MASTER_AMD_AXI=m
+CONFIG_W1_MASTER_DS2482=m
+CONFIG_W1_MASTER_DS2490=m
+CONFIG_W1_MASTER_MATROX=m
+CONFIG_W1_MASTER_MXC=m
+CONFIG_W1_MASTER_SGI=m
+CONFIG_W1_MASTER_UART=m
+CONFIG_W1_SLAVE_DS2408=m
+CONFIG_W1_SLAVE_DS2408_READBACK=y
+CONFIG_W1_SLAVE_DS2413=m
+CONFIG_W1_SLAVE_DS2431=m
+CONFIG_W1_SLAVE_DS2433=m
+CONFIG_W1_SLAVE_SMEM=m
+CONFIG_W1_SLAVE_THERM=m
+CONFIG_WANT_DEV_COREDUMP=y
+CONFIG_WANXL=m
+CONFIG_WAN=y
+CONFIG_WCN36XX=m
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PRIV=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_WFX=m
+CONFIG_WIL6210_ISR_COR=y
+CONFIG_WIL6210=m
+CONFIG_WIREGUARD=m
+CONFIG_WIRELESS_EXT=y
+CONFIG_WL1251=m
+CONFIG_WL1251_SDIO=m
+CONFIG_WL1251_SPI=m
+CONFIG_WL12XX=m
+CONFIG_WL18XX=m
+CONFIG_WLAN_VENDOR_CISCO=y
+CONFIG_WLCORE=m
+CONFIG_WLCORE_SDIO=m
+CONFIG_WLCORE_SPI=m
+CONFIG_WPCM450_SOC=m
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+CONFIG_WWAN_HWSIM=m
+CONFIG_WWAN=y
+CONFIG_X9250=m
+CONFIG_XARRAY_MULTI=y
+CONFIG_XGENE_DMA=m
+CONFIG_XGENE_SLIMPRO_MBOX=m
+CONFIG_XIL_AXIS_FIFO=m
+CONFIG_XILINX_AMS=m
+CONFIG_XILINX_INTC=y
+CONFIG_XILINX_VCU=m
+CONFIG_XILINX_WINDOW_WATCHDOG=m
+CONFIG_XILINX_XADC=m
+CONFIG_XILINX_XDMA=m
+CONFIG_XILINX_ZYNQMP_DPDMA=m
+CONFIG_XILLYBUS_CLASS=m
+CONFIG_XILLYUSB=m
+CONFIG_XLNX_EVENT_MANAGER=y
+CONFIG_XLNX_R5_REMOTEPROC=m
+CONFIG_XOR_BLOCKS=m
+CONFIG_XZ_DEC_MICROLZMA=y
+CONFIG_YAMAHA_YAS530=m
+CONFIG_ZD1211RW=m
+CONFIG_ZIIRAVE_WATCHDOG=m
+CONFIG_ZL3073X_SPI=m
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZONE_DEVICE=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZONE_DMA=y
+CONFIG_ZOPT2201=m
+CONFIG_ZPA2326_I2C=m
+CONFIG_ZPA2326=m
+CONFIG_ZPA2326_SPI=m
+CONFIG_ZPOOL=y
+CONFIG_ZRAM_DEF_COMP="zstd"
+CONFIG_ZRAM_MULTI_COMP=y
+CONFIG_ZRAM_TRACK_ENTRY_ACTIME=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZYNQMP_FIRMWARE=y
+CONFIG_ZYNQMP_IPI_MBOX=y
+CONFIG_ZYNQMP_PM_DOMAINS=y
+CONFIG_ZYNQMP_POWER=y
+CONFIG_NEXUS=m
diff --git a/armv7hnl-desktop-omv-defconfig b/armv7hnl-desktop-omv-defconfig
deleted file mode 100644
index f258410..0000000
--- a/armv7hnl-desktop-omv-defconfig
+++ /dev/null
@@ -1,12720 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# Linux/arm 5.10.0-rc1 Kernel Configuration
-#
-CONFIG_CC_VERSION_TEXT="gcc (GCC) 10.2.0 20200723 (OpenMandriva)"
-CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=100200
-CONFIG_LD_VERSION=235010000
-CONFIG_CLANG_VERSION=0
-CONFIG_CC_CAN_LINK=y
-CONFIG_CC_CAN_LINK_STATIC=y
-CONFIG_CC_HAS_ASM_GOTO=y
-CONFIG_CC_HAS_ASM_INLINE=y
-CONFIG_IRQ_WORK=y
-CONFIG_BUILDTIME_TABLE_SORT=y
-
-#
-# General setup
-#
-CONFIG_INIT_ENV_ARG_LIMIT=32
-# CONFIG_COMPILE_TEST is not set
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_BUILD_SALT="916cd9db5c869881bfaa3db9888e5fb4d7e14920"
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_DEFAULT_INIT=""
-CONFIG_DEFAULT_HOSTNAME="omv"
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_POSIX_MQUEUE_SYSCTL=y
-# CONFIG_WATCH_QUEUE is not set
-CONFIG_CROSS_MEMORY_ATTACH=y
-# CONFIG_USELIB is not set
-# CONFIG_AUDIT is not set
-# CONFIG_HAVE_ARCH_AUDITSYSCALL is not set
-# CONFIG_AUDITSYSCALL is not set
-
-#
-# IRQ subsystem
-#
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_SIM=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_GENERIC_IRQ_IPI=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_SPARSE_IRQ=y
-# CONFIG_GENERIC_IRQ_DEBUGFS is not set
-# end of IRQ subsystem
-
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-
-#
-# Timers subsystem
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ_COMMON=y
-# CONFIG_HZ_PERIODIC is not set
-CONFIG_NO_HZ_IDLE=y
-# CONFIG_NO_HZ_FULL is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
-# end of Timers subsystem
-
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_COUNT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_DYNAMIC=y
-CONFIG_SCHED_CORE=y
-
-#
-# CPU/Task time and stats accounting
-#
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_SCHED_AVG_IRQ=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_PSI=y
-# CONFIG_PSI_DEFAULT_DISABLED is not set
-# end of CPU/Task time and stats accounting
-
-CONFIG_CPU_ISOLATION=y
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-CONFIG_PREEMPT_RCU=y
-# CONFIG_RCU_EXPERT is not set
-CONFIG_SRCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TASKS_RCU_GENERIC=y
-CONFIG_TASKS_RCU=y
-CONFIG_TASKS_RUDE_RCU=y
-CONFIG_TASKS_TRACE_RCU=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RCU_NEED_SEGCBLIST=y
-# end of RCU Subsystem
-
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-# CONFIG_IKHEADERS is not set
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
-CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
-CONFIG_GENERIC_SCHED_CLOCK=y
-
-#
-# Scheduler features
-#
-# CONFIG_UCLAMP_TASK is not set
-# end of Scheduler features
-
-CONFIG_CGROUPS=y
-CONFIG_PAGE_COUNTER=y
-CONFIG_MEMCG=y
-CONFIG_MEMCG_SWAP=y
-CONFIG_MEMCG_KMEM=y
-CONFIG_BLK_CGROUP=y
-CONFIG_CGROUP_WRITEBACK=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_CFS_BANDWIDTH=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_CGROUP_PIDS=y
-CONFIG_CGROUP_RDMA=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CPUSETS=y
-CONFIG_PROC_PID_CPUSET=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_PERF=y
-CONFIG_CGROUP_BPF=y
-CONFIG_CGROUP_MISC=y
-# CONFIG_CGROUP_DEBUG is not set
-CONFIG_SOCK_CGROUP_DATA=y
-CONFIG_NAMESPACES=y
-CONFIG_UTS_NS=y
-CONFIG_IPC_NS=y
-CONFIG_USER_NS=y
-CONFIG_PID_NS=y
-CONFIG_NET_NS=y
-CONFIG_CHECKPOINT_RESTORE=y
-CONFIG_SCHED_AUTOGROUP=y
-# CONFIG_SYSFS_DEPRECATED is not set
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-CONFIG_RD_XZ=y
-# CONFIG_RD_LZO is not set
-# CONFIG_RD_LZ4 is not set
-CONFIG_RD_ZSTD=y
-CONFIG_BOOT_CONFIG=y
-# CONFIG_CC_OPTIMIZE_BASAL is not set
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_HAVE_UID16=y
-CONFIG_BPF=y
-CONFIG_EXPERT=y
-CONFIG_UID16=y
-CONFIG_MULTIUSER=y
-CONFIG_SGETMASK_SYSCALL=y
-# CONFIG_SYSFS_SYSCALL is not set
-CONFIG_FHANDLE=y
-CONFIG_POSIX_TIMERS=y
-CONFIG_PRINTK=y
-CONFIG_PRINTK_NMI=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_FUTEX_PI=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_IO_URING=y
-CONFIG_ADVISE_SYSCALLS=y
-CONFIG_MEMBARRIER=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_BASE_RELATIVE=y
-CONFIG_BPF_SYSCALL=y
-CONFIG_BPF_JIT_ALWAYS_ON=y
-# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
-CONFIG_BPF_JIT_DEFAULT_ON=y
-CONFIG_USERMODE_DRIVER=y
-# CONFIG_BPF_PRELOAD is not set
-CONFIG_USERFAULTFD=y
-CONFIG_LRU_GEN=y
-CONFIG_LRU_GEN_ENABLED=y
-# CONFIG_LRU_GEN_STATS is not set
-CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
-CONFIG_RSEQ=y
-# CONFIG_DEBUG_RSEQ is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-# CONFIG_PC104 is not set
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_PERF_EVENTS=y
-# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
-# end of Kernel Performance Events And Counters
-
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_SLUB_MEMCG_SYSFS_ON is not set
-# CONFIG_COMPAT_BRK is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-CONFIG_SLAB_MERGE_DEFAULT=y
-CONFIG_SLAB_FREELIST_RANDOM=y
-CONFIG_SLAB_FREELIST_HARDENED=y
-CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
-CONFIG_SLUB_CPU_PARTIAL=y
-CONFIG_SYSTEM_DATA_VERIFICATION=y
-# CONFIG_PROFILING is not set
-CONFIG_TRACEPOINTS=y
-# end of General setup
-
-CONFIG_ARM=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_HAVE_TCM=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_NO_IOPORT_MAP=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_ARCH_HAS_BANDGAP=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ZONE_DMA=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_GENERIC_BUG=y
-CONFIG_PGTABLE_LEVELS=3
-
-#
-# System Type
-#
-CONFIG_MMU=y
-CONFIG_ARCH_MMAP_RND_BITS_MIN=8
-CONFIG_ARCH_MMAP_RND_BITS_MAX=16
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_DOVE is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C24XX is not set
-# CONFIG_ARCH_OMAP1 is not set
-# CONFIG_ARCH_AIROHA is not set
-
-#
-# Multiple platform selection
-#
-
-#
-# CPU Core family selection
-#
-# CONFIG_ARCH_MULTI_V6 is not set
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MULTI_V6_V7=y
-# end of Multiple platform selection
-
-# CONFIG_ARCH_VIRT is not set
-CONFIG_ARCH_ACTIONS=y
-CONFIG_ARCH_ALPINE=y
-CONFIG_ARCH_APPLE=y
-CONFIG_ARCH_BCM=y
-CONFIG_ARCH_NXP=y
-CONFIG_ARCH_INTEL_SOCFPGA=y
-CONFIG_ARCH_ARTPEC=y
-# CONFIG_MACH_ARTPEC6 is not set
-CONFIG_ARCH_ASPEED=y
-# CONFIG_MACH_ASPEED_G6 is not set
-CONFIG_ARCH_AT91=y
-# CONFIG_SOC_SAMA5D2 is not set
-# CONFIG_SOC_SAMA5D3 is not set
-# CONFIG_SOC_SAMA5D4 is not set
-
-#
-# Clocksource driver selection
-#
-# CONFIG_ATMEL_CLOCKSOURCE_TCB is not set
-CONFIG_COMMON_CLK_AT91=y
-# CONFIG_ARCH_AXXIA is not set
-CONFIG_ARCH_BCM=y
-
-#
-# IPROC architected SoCs
-#
-# CONFIG_ARCH_BCM_CYGNUS is not set
-# CONFIG_ARCH_BCM_HR2 is not set
-# CONFIG_ARCH_BCM_NSP is not set
-# CONFIG_ARCH_BCM_5301X is not set
-
-#
-# KONA architected SoCs
-#
-# CONFIG_ARCH_BCM_281XX is not set
-# CONFIG_ARCH_BCM_21664 is not set
-# CONFIG_ARCH_BCM_23550 is not set
-
-#
-# Other Architectures
-#
-# CONFIG_ARCH_BCM2835 is not set
-# CONFIG_ARCH_BCM_53573 is not set
-# CONFIG_ARCH_BCM_63XX is not set
-# CONFIG_ARCH_BRCMSTB is not set
-CONFIG_ARCH_BERLIN=y
-# CONFIG_MACH_BERLIN_BG2 is not set
-# CONFIG_MACH_BERLIN_BG2CD is not set
-# CONFIG_MACH_BERLIN_BG2Q is not set
-CONFIG_ARCH_DIGICOLOR=y
-CONFIG_ARCH_EXYNOS=y
-CONFIG_S5P_DEV_MFC=y
-CONFIG_ARCH_EXYNOS3=y
-CONFIG_ARCH_EXYNOS4=y
-CONFIG_ARCH_EXYNOS5=y
-
-#
-# Exynos SoCs
-#
-CONFIG_SOC_EXYNOS3250=y
-CONFIG_CPU_EXYNOS4210=y
-CONFIG_SOC_EXYNOS4412=y
-CONFIG_SOC_EXYNOS5250=y
-CONFIG_SOC_EXYNOS5260=y
-CONFIG_SOC_EXYNOS5410=y
-CONFIG_SOC_EXYNOS5420=y
-CONFIG_SOC_EXYNOS5800=y
-CONFIG_EXYNOS_MCPM=y
-CONFIG_EXYNOS_CPU_SUSPEND=y
-CONFIG_ARCH_HIGHBANK=y
-CONFIG_ARCH_HISI=y
-
-#
-# Hisilicon platform type
-#
-CONFIG_ARCH_HI3xxx=y
-CONFIG_ARCH_HIP01=y
-CONFIG_ARCH_HIP04=y
-CONFIG_ARCH_HIX5HD2=y
-# end of Hisilicon platform type
-
-CONFIG_ARCH_MXC=y
-CONFIG_HAVE_IMX_SRC=y
-
-#
-# Cortex-A platforms
-#
-# CONFIG_SOC_IMX50 is not set
-# CONFIG_SOC_IMX51 is not set
-# CONFIG_SOC_IMX53 is not set
-# CONFIG_SOC_IMX6Q is not set
-# CONFIG_SOC_IMX6SL is not set
-# CONFIG_SOC_IMX6SLL is not set
-# CONFIG_SOC_IMX6SX is not set
-# CONFIG_SOC_IMX6UL is not set
-# CONFIG_SOC_LS1021A is not set
-
-#
-# Cortex-A/Cortex-M asymmetric multiprocessing platforms
-#
-# CONFIG_SOC_IMX7D is not set
-# CONFIG_SOC_IMX7ULP is not set
-# CONFIG_SOC_VF610 is not set
-CONFIG_ARCH_KEYSTONE=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_MACH_MT2701=y
-CONFIG_MACH_MT6589=y
-CONFIG_MACH_MT6592=y
-CONFIG_MACH_MT7623=y
-CONFIG_MACH_MT7629=y
-CONFIG_MACH_MT8127=y
-CONFIG_MACH_MT8135=y
-CONFIG_ARCH_MESON=y
-CONFIG_MACH_MESON6=y
-CONFIG_MACH_MESON8=y
-CONFIG_ARCH_MILBEAUT=y
-# CONFIG_ARCH_MILBEAUT_M10V is not set
-CONFIG_ARCH_MMP=y
-
-#
-# Marvell PXA168/910/MMP2 Implementations
-#
-# CONFIG_MACH_BROWNSTONE is not set
-# CONFIG_MACH_FLINT is not set
-# CONFIG_MACH_MARVELL_JASPER is not set
-# CONFIG_MACH_MMP2_DT is not set
-# CONFIG_MACH_MMP3_DT is not set
-# end of Marvell PXA168/910/MMP2 Implementations
-
-CONFIG_ARCH_MSTARV7=y
-CONFIG_MACH_INFINITY=y
-CONFIG_MACH_MERCURY=y
-CONFIG_ARCH_MVEBU=y
-# CONFIG_MACH_ARMADA_370 is not set
-# CONFIG_MACH_ARMADA_375 is not set
-# CONFIG_MACH_ARMADA_38X is not set
-# CONFIG_MACH_ARMADA_39X is not set
-# CONFIG_MACH_ARMADA_XP is not set
-# CONFIG_MACH_DOVE is not set
-CONFIG_ARCH_NPCM=y
-# CONFIG_ARCH_NPCM7XX is not set
-CONFIG_ARCH_OMAP=y
-
-#
-# TI OMAP Common Features
-#
-
-#
-# OMAP Feature Selections
-#
-# CONFIG_POWER_AVS_OMAP is not set
-# CONFIG_OMAP_RESET_CLOCKS is not set
-CONFIG_OMAP_32K_TIMER=y
-# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
-# end of TI OMAP Common Features
-
-CONFIG_MACH_OMAP_GENERIC=y
-
-#
-# TI OMAP/AM/DM/DRA Family
-#
-CONFIG_ARCH_OMAP3=y
-CONFIG_ARCH_OMAP4=y
-CONFIG_SOC_OMAP5=y
-CONFIG_SOC_AM33XX=y
-CONFIG_SOC_AM43XX=y
-CONFIG_SOC_DRA7XX=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_OMAP_INTERCONNECT_BARRIER=y
-
-#
-# TI OMAP2/3/4 Specific Features
-#
-CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
-CONFIG_SOC_HAS_OMAP2_SDRC=y
-CONFIG_SOC_HAS_REALTIME_COUNTER=y
-CONFIG_SOC_OMAP3430=y
-CONFIG_SOC_TI81XX=y
-CONFIG_OMAP_PACKAGE_CBB=y
-
-#
-# OMAP Legacy Platform Data Board Type
-#
-CONFIG_MACH_OMAP3517EVM=y
-CONFIG_MACH_OMAP3_PANDORA=y
-CONFIG_OMAP3_SDRC_AC_TIMING=y
-# end of TI OMAP2/3/4 Specific Features
-
-# CONFIG_OMAP5_ERRATA_801819 is not set
-# end of TI OMAP/AM/DM/DRA Family
-
-CONFIG_ARCH_SIRF=y
-
-#
-# CSR SiRF atlas6/primaII/Atlas7 Specific Features
-#
-CONFIG_ARCH_ATLAS6=y
-CONFIG_ARCH_ATLAS7=y
-CONFIG_ARCH_PRIMA2=y
-CONFIG_SIRF_IRQ=y
-CONFIG_PXA_SSP=m
-CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_IPQ40XX=y
-CONFIG_ARCH_MSM8X60=y
-CONFIG_ARCH_MSM8960=y
-CONFIG_ARCH_MSM8974=y
-CONFIG_ARCH_MDM9615=y
-CONFIG_ARCH_RDA=y
-CONFIG_ARCH_REALTEK=y
-CONFIG_ARCH_REALVIEW=y
-CONFIG_MACH_REALVIEW_EB=y
-CONFIG_REALVIEW_EB_A9MP=y
-CONFIG_MACH_REALVIEW_PBA8=y
-CONFIG_MACH_REALVIEW_PBX=y
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_ARCH_S5PV210=y
-CONFIG_CPU_S5PV210=y
-CONFIG_ARCH_RENESAS=y
-CONFIG_ARCH_SOCFPGA=y
-CONFIG_SOCFPGA_SUSPEND=y
-CONFIG_PLAT_SPEAR=y
-CONFIG_ARCH_SPEAR13XX=y
-CONFIG_MACH_SPEAR1310=y
-CONFIG_MACH_SPEAR1340=y
-CONFIG_ARCH_STI=y
-CONFIG_SOC_STIH415=y
-CONFIG_SOC_STIH416=y
-CONFIG_SOC_STIH407=y
-CONFIG_ARCH_STM32=y
-CONFIG_MACH_STM32MP157=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
-CONFIG_MACH_SUN5I=y
-CONFIG_MACH_SUN6I=y
-CONFIG_MACH_SUN7I=y
-CONFIG_MACH_SUN8I=y
-CONFIG_MACH_SUN9I=y
-CONFIG_ARCH_SUNXI_MC_SMP=y
-CONFIG_ARCH_TANGO=y
-CONFIG_ARCH_TEGRA=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_ARCH_U8500=y
-CONFIG_UX500_SOC_DB8500=y
-CONFIG_UX500_DEBUG_UART=2
-CONFIG_ARCH_VEXPRESS=y
-CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y
-# CONFIG_ARCH_VEXPRESS_DCSCB is not set
-# CONFIG_ARCH_VEXPRESS_SPC is not set
-# CONFIG_ARCH_VEXPRESS_TC2_PM is not set
-CONFIG_ARCH_VT8500=y
-CONFIG_ARCH_WM8850=y
-CONFIG_ARCH_ZX=y
-CONFIG_SOC_ZX296702=y
-CONFIG_ARCH_ZYNQ=y
-CONFIG_ARM64_EPAN=y
-CONFIG_PLAT_ORION=y
-CONFIG_PLAT_PXA=y
-CONFIG_PLAT_VERSATILE=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_V7=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_LPAE=y
-CONFIG_ARM_PV_FIXUP=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_SWP_EMULATE=y
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_ENDIAN_BE8=y
-CONFIG_CPU_ICACHE_DISABLE=y
-CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y
-CONFIG_CPU_BPREDICT_DISABLE=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDEN_BRANCH_HISTORY=y
-CONFIG_KUSER_HELPERS=y
-CONFIG_VDSO=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_CACHE_FEROCEON_L2=y
-# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_CACHE_L2X0=y
-# CONFIG_CACHE_L2X0_PMU is not set
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_PL310_ERRATA_727915=y
-CONFIG_PL310_ERRATA_753970=y
-CONFIG_PL310_ERRATA_769419=y
-CONFIG_CACHE_UNIPHIER=y
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_L1_CACHE_SHIFT_7=y
-CONFIG_ARM_L1_CACHE_SHIFT=7
-CONFIG_ARM_DMA_MEM_BUFFERABLE=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_ARM_ERRATA_430973=y
-CONFIG_ARM_ERRATA_643719=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_754327=y
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_ARM_ERRATA_798181=y
-CONFIG_ARM_ERRATA_773022=y
-CONFIG_ARM_ERRATA_818325_852422=y
-CONFIG_ARM_ERRATA_821420=y
-CONFIG_ARM_ERRATA_825619=y
-CONFIG_ARM_ERRATA_857271=y
-CONFIG_ARM_ERRATA_852421=y
-CONFIG_ARM_ERRATA_852423=y
-CONFIG_ARM_ERRATA_857272=y
-# end of System Type
-
-#
-# Bus support
-#
-CONFIG_ARM_ERRATA_814220=y
-# end of Bus support
-
-#
-# Kernel Features
-#
-CONFIG_HAVE_SMP=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_ARM_CPU_TOPOLOGY=y
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_SMT=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-CONFIG_HAVE_ARM_TWD=y
-CONFIG_MCPM=y
-CONFIG_MCPM_QUAD_CLUSTER=y
-CONFIG_BIG_LITTLE=y
-# CONFIG_BL_SWITCHER is not set
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_NR_CPUS=32
-CONFIG_HOTPLUG_CPU=y
-CONFIG_ARM_PSCI=y
-CONFIG_ARCH_NR_GPIO=2048
-CONFIG_HZ_FIXED=0
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_200 is not set
-# CONFIG_HZ_250 is not set
-CONFIG_HZ_300=y
-# CONFIG_HZ_500 is not set
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=300
-CONFIG_ARCH_FORCE_MAX_ORDER=12
-CONFIG_SCHED_HRTICK=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HW_PERF_EVENTS=y
-CONFIG_SYS_SUPPORTS_HUGETLBFS=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARM_MODULE_PLTS=y
-CONFIG_FORCE_MAX_ZONEORDER=11
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-CONFIG_PARAVIRT=y
-# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
-# CONFIG_XEN is not set
-CONFIG_STACKPROTECTOR_PER_TASK=y
-# end of Kernel Features
-
-#
-# Boot options
-#
-CONFIG_USE_OF=y
-CONFIG_ATAGS=y
-# CONFIG_DEPRECATED_PARAM_STRUCT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-# CONFIG_ARM_APPENDED_DTB is not set
-CONFIG_CMDLINE=""
-CONFIG_KEXEC=y
-CONFIG_ATAGS_PROC=y
-# CONFIG_CRASH_DUMP is not set
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_EFI=y
-CONFIG_DMI=y
-CONFIG_DMIID=y
-CONFIG_DMI_SYSFS=m
-CONFIG_SYSFB_SIMPLEFB=y
-CONFIG_EFI_VARS_PSTORE=m
-# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
-CONFIG_EFI_ARMSTUB_DTB_LOADER=y
-CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
-CONFIG_EFI_BOOTLOADER_CONTROL=m
-CONFIG_EFI_CAPSULE_LOADER=m
-CONFIG_EFI_TEST=m
-CONFIG_RESET_ATTACK_MITIGATION=y
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-# end of Boot options
-
-#
-# CPU Power Management
-#
-
-#
-# CPU Frequency scaling
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-
-#
-# CPU frequency scaling drivers
-#
-CONFIG_CPUFREQ_DT=m
-CONFIG_CPUFREQ_DT_PLATDEV=y
-# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set
-# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set
-CONFIG_ARM_HIGHBANK_CPUFREQ=m
-# CONFIG_ARM_IMX_CPUFREQ_DT is not set
-# CONFIG_ARM_MEDIATEK_CPUFREQ is not set
-CONFIG_ARM_OMAP2PLUS_CPUFREQ=y
-# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
-CONFIG_ARM_S5PV210_CPUFREQ=y
-# CONFIG_ARM_SCMI_CPUFREQ is not set
-CONFIG_ARM_SPEAR_CPUFREQ=y
-# CONFIG_ARM_STI_CPUFREQ is not set
-CONFIG_ARM_TANGO_CPUFREQ=y
-CONFIG_ARM_TEGRA20_CPUFREQ=m
-CONFIG_ARM_TEGRA124_CPUFREQ=y
-CONFIG_ARM_TI_CPUFREQ=y
-# end of CPU Frequency scaling
-
-#
-# CPU Idle
-#
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-# CONFIG_CPU_IDLE_GOV_TEO is not set
-CONFIG_DT_IDLE_STATES=y
-
-#
-# ARM CPU Idle Drivers
-#
-CONFIG_ARM_CPUIDLE=y
-CONFIG_ARM_PSCI_CPUIDLE=y
-CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
-# CONFIG_ARM_BIG_LITTLE_CPUIDLE is not set
-CONFIG_ARM_HIGHBANK_CPUIDLE=y
-# CONFIG_ARM_ZYNQ_CPUIDLE is not set
-# CONFIG_ARM_U8500_CPUIDLE is not set
-CONFIG_ARM_AT91_CPUIDLE=y
-# CONFIG_ARM_EXYNOS_CPUIDLE is not set
-# CONFIG_ARM_MVEBU_V7_CPUIDLE is not set
-# CONFIG_ARM_TEGRA_CPUIDLE is not set
-# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
-# end of ARM CPU Idle Drivers
-
-CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
-# end of CPU Idle
-# end of CPU Power Management
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_NEON=y
-CONFIG_KERNEL_MODE_NEON=y
-# end of Floating point emulation
-
-#
-# Power management options
-#
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_SUSPEND_SKIP_SYNC is not set
-CONFIG_HIBERNATE_CALLBACKS=y
-CONFIG_HIBERNATION=y
-CONFIG_HIBERNATION_SNAPSHOT_DEV=y
-CONFIG_PM_STD_PARTITION=""
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_PM_AUTOSLEEP=y
-CONFIG_PM_WAKELOCKS=y
-CONFIG_PM_WAKELOCKS_LIMIT=100
-CONFIG_PM_WAKELOCKS_GC=y
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-# CONFIG_APM_EMULATION is not set
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_CPU_PM=y
-CONFIG_ENERGY_MODEL=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-# end of Power management options
-
-#
-# Firmware Drivers
-#
-CONFIG_ARM_SCMI_PROTOCOL=y
-CONFIG_ARM_SCMI_POWER_DOMAIN=m
-CONFIG_ARM_SCPI_PROTOCOL=m
-CONFIG_ARM_SCPI_POWER_DOMAIN=m
-CONFIG_FIRMWARE_MEMMAP=y
-CONFIG_QCOM_SCM=y
-# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-# CONFIG_TRUSTED_FOUNDATIONS is not set
-# CONFIG_TURRIS_MOX_RWTM is not set
-CONFIG_GOOGLE_FIRMWARE=y
-CONFIG_GOOGLE_COREBOOT_TABLE=m
-CONFIG_GOOGLE_MEMCONSOLE=m
-CONFIG_GOOGLE_FRAMEBUFFER_COREBOOT=m
-CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m
-CONFIG_GOOGLE_VPD=m
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ARM_PSCI_CHECKER=y
-CONFIG_HAVE_ARM_SMCCC=y
-CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
-CONFIG_ARM_SMCCC_SOC_ID=y
-
-#
-# Tegra firmware driver
-#
-# CONFIG_TEGRA_IVC is not set
-# end of Tegra firmware driver
-# end of Firmware Drivers
-
-CONFIG_ARM_CRYPTO=y
-CONFIG_CRYPTO_SHA1_ARM=m
-CONFIG_CRYPTO_SHA1_ARM_NEON=m
-CONFIG_CRYPTO_SHA1_ARM_CE=m
-CONFIG_CRYPTO_SHA2_ARM_CE=m
-CONFIG_CRYPTO_SHA256_ARM=m
-CONFIG_CRYPTO_SHA512_ARM=m
-CONFIG_CRYPTO_BLAKE2S_ARM=m
-CONFIG_CRYPTO_BLAKE2B_NEON=m
-CONFIG_CRYPTO_AES_ARM=m
-CONFIG_CRYPTO_AES_ARM_BS=m
-CONFIG_CRYPTO_AES_ARM_CE=m
-CONFIG_CRYPTO_GHASH_ARM_CE=m
-CONFIG_CRYPTO_CRCT10DIF_ARM_CE=m
-CONFIG_CRYPTO_CRC32_ARM_CE=m
-CONFIG_CRYPTO_CHACHA20_NEON=m
-CONFIG_CRYPTO_POLY1305_ARM=m
-CONFIG_CRYPTO_NHPOLY1305_NEON=m
-CONFIG_CRYPTO_CURVE25519_NEON=m
-
-#
-# General architecture-dependent options
-#
-CONFIG_CRASH_CORE=y
-CONFIG_KEXEC_CORE=y
-CONFIG_SET_FS=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_KPROBES=y
-# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set
-CONFIG_JUMP_LABEL=y
-# CONFIG_STATIC_KEYS_SELFTEST is not set
-CONFIG_OPTPROBES=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_KRETPROBES=y
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_NMI=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_KEEPINITRD=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_MMU_GATHER_TABLE_FREE=y
-CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_HAVE_ARCH_SECCOMP=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_SECCOMP=y
-# CONFIG_SECCOMP_CACHE_DEBUG is not set
-CONFIG_SECCOMP_FILTER=y
-CONFIG_HAVE_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR_STRONG=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
-CONFIG_HAVE_EXIT_THREAD=y
-CONFIG_ARCH_MMAP_RND_BITS=8
-CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_VMAP_STACK=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_STRICT_MODULE_RWX=y
-CONFIG_ARCH_HAS_PHYS_TO_DMA=y
-# CONFIG_LOCK_EVENT_COUNTS is not set
-# CONFIG_KCSAN is not set
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-# end of GCOV-based kernel profiling
-
-CONFIG_HAVE_GCC_PLUGINS=y
-CONFIG_GCC_PLUGINS=y
-# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
-CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y
-# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
-CONFIG_GCC_PLUGIN_ARM_SSP_PER_TASK=y
-# end of General architecture-dependent options
-CONFIG_RANDSTRUCT_NONE=y
-# CONFIG_RANDSTRUCT_FULL is not set
-# CONFIG_RANDSTRUCT_PERFORMANCE is not set
-
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_MODULE_SIG is not set
-CONFIG_MODULE_COMPRESS_NONE=y
-# CONFIG_MODULE_COMPRESS_GZIP is not set
-# CONFIG_MODULE_COMPRESS_XZ is not set
-# CONFIG_MODULE_COMPRESS_ZSTD is not set
-# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
-CONFIG_MODPROBE_PATH="/sbin/modprobe"
-# CONFIG_TRIM_UNUSED_KSYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_TRIM_UNUSED_KSYMS=y
-CONFIG_UNUSED_KSYMS_WHITELIST=""
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_BLOCK=y
-# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set
-CONFIG_BLK_SCSI_REQUEST=y
-CONFIG_BLK_CGROUP_RWSTAT=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=m
-CONFIG_BLK_DEV_ZONED=y
-CONFIG_BLK_DEV_THROTTLING=y
-# CONFIG_BLK_DEV_THROTTLING_LOW is not set
-CONFIG_BLK_CMDLINE_PARSER=y
-CONFIG_BLK_WBT=y
-CONFIG_BLK_CGROUP_IOLATENCY=y
-# CONFIG_BLK_CGROUP_FC_APPID is not set
-# CONFIG_BLK_CGROUP_IOCOST is not set
-# CONFIG_BLK_CGROUP_IOPRIO is not set
-CONFIG_BLK_WBT_MQ=y
-# CONFIG_BLK_DEBUG_FS is not set
-CONFIG_BLK_DEBUG_FS_ZONED=y
-# CONFIG_BLK_SED_OPAL is not set
-# CONFIG_BLK_INLINE_ENCRYPTION is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_AIX_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_LDM_DEBUG=y
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_CMDLINE_PARTITION=y
-# end of Partition Types
-
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_MQ_RDMA=y
-CONFIG_BLK_PM=y
-
-#
-# IO Schedulers
-#
-CONFIG_MQ_IOSCHED_DEADLINE=y
-CONFIG_MQ_IOSCHED_KYBER=m
-CONFIG_IOSCHED_BFQ=y
-CONFIG_BFQ_GROUP_IOSCHED=y
-# CONFIG_BFQ_CGROUP_DEBUG is not set
-# end of IO Schedulers
-
-CONFIG_PADATA=y
-CONFIG_ASN1=y
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
-CONFIG_FREEZER=y
-
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_ELF_FDPIC is not set
-CONFIG_ELFCORE=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_BINFMT_SCRIPT=y
-CONFIG_ARCH_HAS_BINFMT_FLAT=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-# CONFIG_BINFMT_FLAT_OLD is not set
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_BINFMT_MISC=m
-CONFIG_COREDUMP=y
-# end of Executable file formats
-
-#
-# Memory Management options
-#
-CONFIG_SELECT_MEMORY_MODEL=y
-# CONFIG_FLATMEM_MANUAL is not set
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_STATIC=y
-CONFIG_HAVE_FAST_GUP=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_MEMORY_BALLOON=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_COMPACTION=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_MIGRATION=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_BOUNCE=y
-CONFIG_MMU_NOTIFIER=y
-CONFIG_KSM=y
-CONFIG_UKSM=y
-# CONFIG_KSM_LEGACY is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
-# CONFIG_TRANSPARENT_HUGEPAGE is not set
-CONFIG_CLEANCACHE=y
-CONFIG_FRONTSWAP=y
-CONFIG_CMA=y
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SYSFS=y
-CONFIG_CMA_AREAS=7
-CONFIG_ZSWAP=y
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
-CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
-CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
-CONFIG_ZSWAP_DEFAULT_ON=y
-CONFIG_ZPOOL=y
-CONFIG_ZBUD=y
-CONFIG_Z3FOLD=m
-CONFIG_ZSMALLOC=y
-# CONFIG_ZSMALLOC_PGTABLE_MAPPING is not set
-# CONFIG_ZSMALLOC_STAT is not set
-CONFIG_GENERIC_EARLY_IOREMAP=y
-# CONFIG_IDLE_PAGE_TRACKING is not set
-CONFIG_HMM_MIRROR=y
-CONFIG_FRAME_VECTOR=y
-# CONFIG_PERCPU_STATS is not set
-# CONFIG_GUP_TEST is not set
-# CONFIG_GUP_BENCHMARK is not set
-CONFIG_ARCH_HAS_PTE_SPECIAL=y
-# end of Memory Management options
-
-CONFIG_NET=y
-CONFIG_NET_INGRESS=y
-CONFIG_NET_EGRESS=y
-CONFIG_NET_REDIRECT=y
-CONFIG_SKB_EXTENSIONS=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=m
-CONFIG_PACKET_DIAG=m
-CONFIG_UNIX=y
-CONFIG_UNIX_SCM=y
-CONFIG_UNIX_DIAG=m
-CONFIG_TLS=m
-CONFIG_TLS_DEVICE=y
-# CONFIG_TLS_TOE is not set
-CONFIG_XFRM=y
-CONFIG_XFRM_OFFLOAD=y
-CONFIG_XFRM_ALGO=m
-CONFIG_XFRM_USER=m
-CONFIG_XFRM_INTERFACE=m
-CONFIG_XFRM_SUB_POLICY=y
-CONFIG_XFRM_MIGRATE=y
-CONFIG_XFRM_STATISTICS=y
-CONFIG_XFRM_AH=m
-CONFIG_XFRM_ESP=m
-CONFIG_XFRM_IPCOMP=m
-CONFIG_NET_KEY=m
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_XFRM_ESPINTCP=y
-CONFIG_SMC=m
-CONFIG_SMC_DIAG=m
-CONFIG_XDP_SOCKETS=y
-CONFIG_XDP_SOCKETS_DIAG=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_FIB_TRIE_STATS=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-# CONFIG_IP_ROUTE_VERBOSE is not set
-CONFIG_IP_ROUTE_CLASSID=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE_DEMUX=m
-CONFIG_NET_IP_TUNNEL=m
-CONFIG_NET_IPGRE=m
-CONFIG_NET_IPGRE_BROADCAST=y
-CONFIG_IP_MROUTE_COMMON=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_NET_IPVTI=m
-CONFIG_NET_UDP_TUNNEL=m
-CONFIG_NET_FOU=m
-CONFIG_NET_FOU_IP_TUNNELS=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_ESP_OFFLOAD=m
-CONFIG_INET_ESPINTCP=y
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_TABLE_PERTURB_ORDER=16
-CONFIG_INET_XFRM_TUNNEL=m
-CONFIG_INET_TUNNEL=m
-CONFIG_INET_DIAG=m
-CONFIG_INET_TCP_DIAG=m
-CONFIG_INET_UDP_DIAG=m
-CONFIG_INET_RAW_DIAG=m
-CONFIG_INET_DIAG_DESTROY=y
-CONFIG_TCP_CONG_ADVANCED=y
-CONFIG_TCP_CONG_BIC=m
-CONFIG_TCP_CONG_CUBIC=m
-CONFIG_TCP_CONG_WESTWOOD=m
-CONFIG_TCP_CONG_HTCP=m
-CONFIG_TCP_CONG_HSTCP=m
-CONFIG_TCP_CONG_HYBLA=m
-CONFIG_TCP_CONG_VEGAS=m
-CONFIG_TCP_CONG_NV=m
-CONFIG_TCP_CONG_SCALABLE=m
-CONFIG_TCP_CONG_LP=m
-CONFIG_TCP_CONG_VENO=m
-CONFIG_TCP_CONG_YEAH=m
-CONFIG_TCP_CONG_ILLINOIS=m
-CONFIG_TCP_CONG_DCTCP=m
-# CONFIG_TCP_CONG_CDG is not set
-CONFIG_TCP_CONG_BBR=m
-CONFIG_DEFAULT_RENO=y
-CONFIG_DEFAULT_TCP_CONG="reno"
-CONFIG_TCP_MD5SIG=y
-CONFIG_IPV6=m
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_ESP_OFFLOAD=m
-# CONFIG_INET6_ESPINTCP is not set
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_IPV6_ILA=m
-CONFIG_INET6_XFRM_TUNNEL=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_IPV6_VTI=m
-CONFIG_IPV6_SIT=m
-CONFIG_IPV6_SIT_6RD=y
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_GRE=m
-CONFIG_IPV6_FOU=m
-CONFIG_IPV6_FOU_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-CONFIG_IPV6_MROUTE=y
-CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IPV6_PIMSM_V2=y
-CONFIG_IPV6_SEG6_LWTUNNEL=y
-CONFIG_IPV6_SEG6_HMAC=y
-CONFIG_IPV6_RPL_LWTUNNEL=y
-CONFIG_MPTCP=y
-CONFIG_INET_MPTCP_DIAG=m
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NETWORK_PHY_TIMESTAMPING=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_ADVANCED=y
-CONFIG_BRIDGE_NETFILTER=m
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_INGRESS=y
-CONFIG_NETFILTER_NETLINK_HOOK=m
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_FAMILY_BRIDGE=y
-CONFIG_NETFILTER_FAMILY_ARP=y
-CONFIG_NETFILTER_NETLINK_ACCT=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NETFILTER_NETLINK_OSF=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_LOG_SYSLOG=m
-CONFIG_NF_LOG_COMMON=m
-CONFIG_NF_LOG_NETDEV=m
-CONFIG_NETFILTER_CONNCOUNT=m
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_ZONES=y
-CONFIG_NF_CONNTRACK_PROCFS=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CONNTRACK_TIMEOUT=y
-CONFIG_NF_CONNTRACK_TIMESTAMP=y
-CONFIG_NF_CONNTRACK_LABELS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_GRE=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_BROADCAST=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_SNMP=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NF_CT_NETLINK_TIMEOUT=m
-CONFIG_NF_CT_NETLINK_HELPER=m
-CONFIG_NETFILTER_NETLINK_GLUE_CT=y
-CONFIG_NF_NAT=m
-CONFIG_NF_NAT_AMANDA=m
-CONFIG_NF_NAT_FTP=m
-CONFIG_NF_NAT_IRC=m
-CONFIG_NF_NAT_SIP=m
-CONFIG_NF_NAT_TFTP=m
-CONFIG_NF_NAT_REDIRECT=y
-CONFIG_NF_NAT_MASQUERADE=y
-CONFIG_NETFILTER_SYNPROXY=m
-CONFIG_NF_TABLES=m
-CONFIG_NF_TABLES_INET=y
-CONFIG_NF_TABLES_NETDEV=y
-CONFIG_NFT_NUMGEN=m
-CONFIG_NFT_CT=m
-CONFIG_NFT_FLOW_OFFLOAD=m
-CONFIG_NFT_COUNTER=m
-CONFIG_NFT_CONNLIMIT=m
-CONFIG_NFT_LOG=m
-CONFIG_NFT_LIMIT=m
-CONFIG_NFT_MASQ=m
-CONFIG_NFT_REDIR=m
-CONFIG_NFT_NAT=m
-CONFIG_NFT_TUNNEL=m
-CONFIG_NFT_OBJREF=m
-CONFIG_NFT_QUEUE=m
-CONFIG_NFT_QUOTA=m
-CONFIG_NFT_REJECT=m
-CONFIG_NFT_REJECT_INET=m
-CONFIG_NFT_COMPAT=m
-CONFIG_NFT_HASH=m
-CONFIG_NFT_FIB_INET=m
-CONFIG_NFT_FIB=m
-CONFIG_NFT_FIB_INET=m
-CONFIG_NFT_XFRM=m
-CONFIG_NFT_SOCKET=m
-CONFIG_NFT_OSF=m
-CONFIG_NFT_TPROXY=m
-CONFIG_NFT_SYNPROXY=m
-CONFIG_NF_DUP_NETDEV=m
-CONFIG_NFT_DUP_NETDEV=m
-CONFIG_NFT_FWD_NETDEV=m
-CONFIG_NFT_FIB_NETDEV=m
-CONFIG_NFT_REJECT_NETDEV=m
-CONFIG_NF_FLOW_TABLE_INET=m
-CONFIG_NF_FLOW_TABLE=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XTABLES_COMPAT=y
-
-#
-# Xtables combined modules
-#
-CONFIG_NETFILTER_XT_MARK=m
-CONFIG_NETFILTER_XT_CONNMARK=m
-CONFIG_NETFILTER_XT_SET=m
-
-#
-# Xtables targets
-#
-CONFIG_NETFILTER_XT_TARGET_AUDIT=m
-CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CT=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_HL=m
-CONFIG_NETFILTER_XT_TARGET_HMARK=m
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
-CONFIG_NETFILTER_XT_TARGET_LOG=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_NAT=m
-CONFIG_NETFILTER_XT_TARGET_NETMAP=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-CONFIG_NETFILTER_XT_TARGET_RATEEST=m
-CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
-CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
-CONFIG_NETFILTER_XT_TARGET_TEE=m
-CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-CONFIG_NETFILTER_XT_TARGET_TRACE=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-
-#
-# Xtables matches
-#
-CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
-CONFIG_NETFILTER_XT_MATCH_BPF=m
-CONFIG_NETFILTER_XT_MATCH_CGROUP=m
-CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_CPU=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ECN=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_HL=m
-CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_IPVS=m
-CONFIG_NETFILTER_XT_MATCH_L2TP=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-CONFIG_NETFILTER_XT_MATCH_OSF=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-# end of Core Netfilter Configuration
-
-CONFIG_IP_SET=m
-CONFIG_IP_SET_MAX=256
-CONFIG_IP_SET_BITMAP_IP=m
-CONFIG_IP_SET_BITMAP_IPMAC=m
-CONFIG_IP_SET_BITMAP_PORT=m
-CONFIG_IP_SET_HASH_IP=m
-CONFIG_IP_SET_HASH_IPMARK=m
-CONFIG_IP_SET_HASH_IPPORT=m
-CONFIG_IP_SET_HASH_IPPORTIP=m
-CONFIG_IP_SET_HASH_IPPORTNET=m
-CONFIG_IP_SET_HASH_IPMAC=m
-CONFIG_IP_SET_HASH_MAC=m
-CONFIG_IP_SET_HASH_NETPORTNET=m
-CONFIG_IP_SET_HASH_NET=m
-CONFIG_IP_SET_HASH_NETNET=m
-CONFIG_IP_SET_HASH_NETPORT=m
-CONFIG_IP_SET_HASH_NETIFACE=m
-CONFIG_IP_SET_LIST_SET=m
-CONFIG_IP_VS=m
-CONFIG_IP_VS_IPV6=y
-# CONFIG_IP_VS_DEBUG is not set
-CONFIG_IP_VS_TAB_BITS=12
-
-#
-# IPVS transport protocol load balancing support
-#
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_AH_ESP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_PROTO_SCTP=y
-
-#
-# IPVS scheduler
-#
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_FO=m
-CONFIG_IP_VS_OVF=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_MH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_TWOS=m
-
-#
-# IPVS SH scheduler
-#
-CONFIG_IP_VS_SH_TAB_BITS=8
-
-#
-# IPVS MH scheduler
-#
-CONFIG_IP_VS_MH_TAB_INDEX=12
-
-#
-# IPVS application helper
-#
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_VS_NFCT=y
-CONFIG_IP_VS_PE_SIP=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_DEFRAG_IPV4=m
-CONFIG_NF_SOCKET_IPV4=m
-CONFIG_NF_TPROXY_IPV4=m
-CONFIG_NF_TABLES_IPV4=y
-CONFIG_NFT_REJECT_IPV4=m
-CONFIG_NFT_DUP_IPV4=m
-CONFIG_NFT_FIB_IPV4=m
-CONFIG_NF_TABLES_ARP=y
-CONFIG_NF_FLOW_TABLE_IPV4=m
-CONFIG_NF_DUP_IPV4=m
-CONFIG_NF_LOG_ARP=m
-CONFIG_NF_LOG_IPV4=m
-CONFIG_NF_REJECT_IPV4=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_NF_NAT_PPTP=m
-CONFIG_NF_NAT_H323=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_RPFILTER=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_SYNPROXY=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-# end of IP: Netfilter Configuration
-
-#
-# IPv6: Netfilter Configuration
-#
-CONFIG_NF_SOCKET_IPV6=m
-CONFIG_NF_TPROXY_IPV6=m
-CONFIG_NF_TABLES_IPV6=y
-CONFIG_NFT_REJECT_IPV6=m
-CONFIG_NFT_DUP_IPV6=m
-CONFIG_NFT_FIB_IPV6=m
-CONFIG_NF_FLOW_TABLE_IPV6=m
-CONFIG_NF_DUP_IPV6=m
-CONFIG_NF_REJECT_IPV6=m
-CONFIG_NF_LOG_IPV6=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RPFILTER=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_MATCH_SRH=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_TARGET_SYNPROXY=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_IP6_NF_NAT=m
-CONFIG_IP6_NF_TARGET_MASQUERADE=m
-CONFIG_IP6_NF_TARGET_NPT=m
-# end of IPv6: Netfilter Configuration
-
-CONFIG_NF_DEFRAG_IPV6=m
-CONFIG_NF_TABLES_BRIDGE=m
-CONFIG_NFT_BRIDGE_META=m
-CONFIG_NFT_BRIDGE_REJECT=m
-CONFIG_NF_LOG_BRIDGE=m
-CONFIG_NF_CONNTRACK_BRIDGE=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_IP6=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_BRIDGE_EBT_NFLOG=m
-CONFIG_BPFILTER=y
-CONFIG_BPFILTER_UMH=m
-CONFIG_IP_DCCP=m
-CONFIG_INET_DCCP_DIAG=m
-
-#
-# DCCP CCIDs Configuration
-#
-# CONFIG_IP_DCCP_CCID2_DEBUG is not set
-CONFIG_IP_DCCP_CCID3=y
-# CONFIG_IP_DCCP_CCID3_DEBUG is not set
-CONFIG_IP_DCCP_TFRC_LIB=y
-# end of DCCP CCIDs Configuration
-
-#
-# DCCP Kernel Hacking
-#
-# CONFIG_IP_DCCP_DEBUG is not set
-# end of DCCP Kernel Hacking
-
-CONFIG_IP_SCTP=m
-# CONFIG_SCTP_DBG_OBJCNT is not set
-CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
-CONFIG_SCTP_COOKIE_HMAC_MD5=y
-CONFIG_SCTP_COOKIE_HMAC_SHA1=y
-CONFIG_INET_SCTP_DIAG=m
-CONFIG_RDS=m
-CONFIG_RDS_RDMA=m
-CONFIG_RDS_TCP=m
-# CONFIG_RDS_DEBUG is not set
-CONFIG_TIPC=m
-CONFIG_TIPC_MEDIA_IB=y
-CONFIG_TIPC_MEDIA_UDP=y
-CONFIG_TIPC_CRYPTO=y
-CONFIG_TIPC_DIAG=m
-CONFIG_ATM=m
-CONFIG_ATM_CLIP=m
-# CONFIG_ATM_CLIP_NO_ICMP is not set
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-# CONFIG_ATM_BR2684_IPFILTER is not set
-CONFIG_L2TP=m
-# CONFIG_L2TP_DEBUGFS is not set
-CONFIG_L2TP_V3=y
-CONFIG_L2TP_IP=m
-CONFIG_L2TP_ETH=m
-CONFIG_STP=m
-CONFIG_GARP=m
-CONFIG_MRP=m
-CONFIG_BRIDGE=m
-CONFIG_BRIDGE_IGMP_SNOOPING=y
-CONFIG_BRIDGE_VLAN_FILTERING=y
-# CONFIG_BRIDGE_MRP is not set
-# CONFIG_BRIDGE_CFM is not set
-CONFIG_HAVE_NET_DSA=y
-CONFIG_NET_DSA=m
-CONFIG_NET_DSA_TAG_8021Q=m
-CONFIG_NET_DSA_TAG_AR9331=m
-CONFIG_NET_DSA_TAG_BRCM_COMMON=m
-CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
-CONFIG_NET_DSA_TAG_BRCM=m
-CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
-CONFIG_NET_DSA_TAG_HELLCREEK=m
-CONFIG_NET_DSA_TAG_GSWIP=m
-CONFIG_NET_DSA_TAG_DSA=m
-CONFIG_NET_DSA_TAG_EDSA=m
-CONFIG_NET_DSA_TAG_MTK=m
-CONFIG_NET_DSA_TAG_KSZ=m
-CONFIG_NET_DSA_TAG_RTL4_A=m
-CONFIG_NET_DSA_TAG_RTL8_4=m
-CONFIG_NET_DSA_TAG_OCELOT=m
-CONFIG_NET_DSA_TAG_QCA=m
-CONFIG_NET_DSA_TAG_LAN9303=m
-CONFIG_NET_DSA_TAG_SJA1105=m
-CONFIG_NET_DSA_TAG_TRAILER=m
-CONFIG_NET_DSA_TAG_XRS700X=m
-CONFIG_NET_DSA_REALTEK=m
-CONFIG_NET_DSA_REALTEK_MDIO=m
-CONFIG_NET_DSA_REALTEK_RTL8365MB=m
-CONFIG_NET_DSA_REALTEK_RTL8366RB=m
-CONFIG_VLAN_8021Q=m
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_VLAN_8021Q_MVRP=y
-# CONFIG_DECNET is not set
-CONFIG_LLC=m
-CONFIG_LLC2=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_PHONET=m
-CONFIG_6LOWPAN=m
-# CONFIG_6LOWPAN_DEBUGFS is not set
-CONFIG_6LOWPAN_NHC=m
-CONFIG_6LOWPAN_NHC_DEST=m
-CONFIG_6LOWPAN_NHC_FRAGMENT=m
-CONFIG_6LOWPAN_NHC_HOP=m
-CONFIG_6LOWPAN_NHC_IPV6=m
-CONFIG_6LOWPAN_NHC_MOBILITY=m
-CONFIG_6LOWPAN_NHC_ROUTING=m
-CONFIG_6LOWPAN_NHC_UDP=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
-CONFIG_6LOWPAN_GHC_UDP=m
-CONFIG_6LOWPAN_GHC_ICMPV6=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
-CONFIG_IEEE802154=m
-CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
-CONFIG_IEEE802154_SOCKET=m
-CONFIG_IEEE802154_6LOWPAN=m
-CONFIG_MAC802154=m
-CONFIG_NET_SCHED=y
-
-#
-# Queueing/Scheduling
-#
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_MULTIQ=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFB=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_CBS=m
-CONFIG_NET_SCH_ETF=m
-CONFIG_NET_SCH_TAPRIO=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_DRR=m
-CONFIG_NET_SCH_MQPRIO=m
-CONFIG_NET_SCH_SKBPRIO=m
-CONFIG_NET_SCH_CHOKE=m
-CONFIG_NET_SCH_QFQ=m
-CONFIG_NET_SCH_CODEL=m
-CONFIG_NET_SCH_FQ_CODEL=y
-CONFIG_NET_SCH_CAKE=m
-CONFIG_NET_SCH_FQ=m
-CONFIG_NET_SCH_HHF=m
-CONFIG_NET_SCH_PIE=m
-CONFIG_NET_SCH_FQ_PIE=m
-CONFIG_NET_SCH_INGRESS=m
-CONFIG_NET_SCH_PLUG=m
-CONFIG_NET_SCH_ETS=m
-# CONFIG_NET_SCH_DEFAULT is not set
-
-#
-# Classification
-#
-CONFIG_NET_CLS=y
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_CLS_U32_PERF=y
-CONFIG_CLS_U32_MARK=y
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_CLS_FLOW=m
-CONFIG_NET_CLS_CGROUP=m
-CONFIG_NET_CLS_BPF=m
-CONFIG_NET_CLS_FLOWER=m
-CONFIG_NET_CLS_MATCHALL=m
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_STACK=32
-CONFIG_NET_EMATCH_CMP=m
-CONFIG_NET_EMATCH_NBYTE=m
-CONFIG_NET_EMATCH_U32=m
-CONFIG_NET_EMATCH_META=m
-CONFIG_NET_EMATCH_TEXT=m
-CONFIG_NET_EMATCH_CANID=m
-CONFIG_NET_EMATCH_IPSET=m
-CONFIG_NET_EMATCH_IPT=m
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=m
-CONFIG_NET_ACT_GACT=m
-CONFIG_GACT_PROB=y
-CONFIG_NET_ACT_MIRRED=m
-CONFIG_NET_ACT_SAMPLE=m
-CONFIG_NET_ACT_IPT=m
-CONFIG_NET_ACT_NAT=m
-CONFIG_NET_ACT_PEDIT=m
-# CONFIG_NET_ACT_SIMP is not set
-CONFIG_NET_ACT_SKBEDIT=m
-CONFIG_NET_ACT_CSUM=m
-CONFIG_NET_ACT_MPLS=m
-CONFIG_NET_ACT_VLAN=m
-CONFIG_NET_ACT_BPF=m
-CONFIG_NET_ACT_CONNMARK=m
-CONFIG_NET_ACT_CTINFO=m
-CONFIG_NET_ACT_SKBMOD=m
-CONFIG_NET_ACT_IFE=m
-CONFIG_NET_ACT_TUNNEL_KEY=m
-CONFIG_NET_ACT_CT=m
-CONFIG_NET_ACT_GATE=m
-CONFIG_NET_IFE_SKBMARK=m
-CONFIG_NET_IFE_SKBPRIO=m
-CONFIG_NET_IFE_SKBTCINDEX=m
-# CONFIG_NET_TC_SKB_EXT is not set
-CONFIG_NET_SCH_FIFO=y
-CONFIG_DCB=y
-CONFIG_DNS_RESOLVER=y
-CONFIG_BATMAN_ADV=m
-# CONFIG_BATMAN_ADV_BATMAN_V is not set
-CONFIG_BATMAN_ADV_BLA=y
-CONFIG_BATMAN_ADV_DAT=y
-CONFIG_BATMAN_ADV_NC=y
-CONFIG_BATMAN_ADV_MCAST=y
-CONFIG_BATMAN_ADV_DEBUGFS=y
-# CONFIG_BATMAN_ADV_DEBUG is not set
-CONFIG_BATMAN_ADV_SYSFS=y
-# CONFIG_BATMAN_ADV_TRACING is not set
-CONFIG_OPENVSWITCH=m
-CONFIG_OPENVSWITCH_GRE=m
-CONFIG_OPENVSWITCH_VXLAN=m
-CONFIG_OPENVSWITCH_GENEVE=m
-CONFIG_VSOCKETS=m
-CONFIG_VSOCKETS_DIAG=m
-CONFIG_VSOCKETS_LOOPBACK=m
-CONFIG_VIRTIO_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS_COMMON=m
-CONFIG_NETLINK_DIAG=m
-CONFIG_MPLS=y
-CONFIG_NET_MPLS_GSO=m
-CONFIG_MPLS_ROUTING=m
-CONFIG_MPLS_IPTUNNEL=m
-CONFIG_NET_NSH=m
-CONFIG_HSR=m
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_L3_MASTER_DEV=y
-CONFIG_QRTR=m
-CONFIG_QRTR_SMD=m
-CONFIG_QRTR_TUN=m
-CONFIG_QRTR_MHI=m
-# CONFIG_NET_NCSI is not set
-CONFIG_PCPU_DEV_REFCNT=y
-CONFIG_RPS=y
-CONFIG_RFS_ACCEL=y
-CONFIG_XPS=y
-CONFIG_CGROUP_NET_PRIO=y
-CONFIG_CGROUP_NET_CLASSID=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_BQL=y
-CONFIG_BPF_JIT=y
-CONFIG_BPF_STREAM_PARSER=y
-CONFIG_NET_FLOW_LIMIT=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NET_DROP_MONITOR is not set
-# end of Network testing
-# end of Networking options
-
-CONFIG_HAMRADIO=y
-
-#
-# Packet Radio protocols
-#
-CONFIG_AX25=m
-CONFIG_AX25_DAMA_SLAVE=y
-CONFIG_NETROM=m
-CONFIG_ROSE=m
-
-#
-# AX.25 network device drivers
-#
-CONFIG_MKISS=m
-CONFIG_6PACK=m
-CONFIG_BPQETHER=m
-CONFIG_BAYCOM_SER_FDX=m
-CONFIG_BAYCOM_SER_HDX=m
-CONFIG_BAYCOM_PAR=m
-CONFIG_BAYCOM_EPP=m
-CONFIG_YAM=m
-# end of AX.25 network device drivers
-
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_GW=m
-CONFIG_CAN_J1939=m
-CONFIG_CAN_ISOTP=m
-CONFIG_CAN_ETAS_ES58X=m
-
-#
-# CAN Device Drivers
-#
-CONFIG_CAN_VCAN=m
-CONFIG_CAN_VXCAN=m
-CONFIG_CAN_SLCAN=m
-CONFIG_CAN_DEV=m
-CONFIG_CAN_CALC_BITTIMING=y
-# CONFIG_CAN_AT91 is not set
-CONFIG_CAN_FLEXCAN=m
-CONFIG_CAN_GRCAN=m
-CONFIG_CAN_JANZ_ICAN3=m
-CONFIG_CAN_KVASER_PCIEFD=m
-# CONFIG_CAN_SUN4I is not set
-CONFIG_CAN_TI_HECC=m
-# CONFIG_CAN_XILINXCAN is not set
-CONFIG_CAN_C_CAN=m
-CONFIG_CAN_C_CAN_PLATFORM=m
-CONFIG_CAN_C_CAN_PCI=m
-CONFIG_CAN_CC770=m
-CONFIG_CAN_CC770_ISA=m
-CONFIG_CAN_CC770_PLATFORM=m
-CONFIG_CAN_IFI_CANFD=m
-CONFIG_CAN_M_CAN=m
-CONFIG_CAN_M_CAN_PCI=m
-CONFIG_CAN_M_CAN_PLATFORM=m
-CONFIG_CAN_M_CAN_TCAN4X5X=m
-CONFIG_CAN_PEAK_PCIEFD=m
-CONFIG_CAN_RCAR=m
-CONFIG_CAN_RCAR_CANFD=m
-CONFIG_CAN_SJA1000=m
-CONFIG_CAN_EMS_PCI=m
-CONFIG_CAN_EMS_PCMCIA=m
-CONFIG_CAN_F81601=m
-CONFIG_CAN_KVASER_PCI=m
-CONFIG_CAN_PEAK_PCI=m
-CONFIG_CAN_PEAK_PCIEC=y
-CONFIG_CAN_PLX_PCI=m
-CONFIG_CAN_SJA1000_ISA=m
-CONFIG_CAN_SJA1000_PLATFORM=m
-CONFIG_CAN_SOFTING=m
-CONFIG_CAN_SOFTING_CS=m
-
-#
-# CAN SPI interfaces
-#
-CONFIG_CAN_HI311X=m
-CONFIG_CAN_MCP251X=m
-CONFIG_CAN_MCP251XFD=m
-# CONFIG_CAN_MCP251XFD_SANITY is not set
-# end of CAN SPI interfaces
-
-#
-# CAN USB interfaces
-#
-CONFIG_CAN_8DEV_USB=m
-CONFIG_CAN_EMS_USB=m
-CONFIG_CAN_ESD_USB2=m
-CONFIG_CAN_GS_USB=m
-CONFIG_CAN_KVASER_USB=m
-CONFIG_CAN_MCBA_USB=m
-CONFIG_CAN_PEAK_USB=m
-CONFIG_CAN_UCAN=m
-# end of CAN USB interfaces
-
-# CONFIG_CAN_DEBUG_DEVICES is not set
-# end of CAN Device Drivers
-
-CONFIG_BT=m
-CONFIG_BT_BREDR=y
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_CMTP=m
-CONFIG_BT_HIDP=m
-CONFIG_BT_HS=y
-CONFIG_BT_LE=y
-CONFIG_BT_6LOWPAN=m
-CONFIG_BT_LEDS=y
-CONFIG_BT_MSFTEXT=y
-CONFIG_BT_AOSPEXT=y
-CONFIG_BT_DEBUGFS=y
-# CONFIG_BT_SELFTEST is not set
-# CONFIG_BT_FEATURE_DEBUG is not set
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_INTEL=m
-CONFIG_BT_BCM=m
-CONFIG_BT_RTL=m
-CONFIG_BT_QCA=m
-CONFIG_BT_HCIBTUSB=m
-# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
-CONFIG_BT_HCIBTUSB_BCM=y
-CONFIG_BT_HCIBTUSB_MTK=y
-CONFIG_BT_HCIBTUSB_RTL=y
-CONFIG_BT_HCIBTSDIO=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_SERDEV=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_NOKIA=m
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_ATH3K=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIUART_3WIRE=y
-CONFIG_BT_HCIUART_INTEL=y
-CONFIG_BT_HCIUART_BCM=y
-CONFIG_BT_HCIUART_QCA=y
-CONFIG_BT_HCIUART_AG6XX=y
-CONFIG_BT_HCIUART_MRVL=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIDTL1=m
-CONFIG_BT_HCIBT3C=m
-CONFIG_BT_HCIBLUECARD=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_BT_MRVL=m
-CONFIG_BT_MRVL_SDIO=m
-CONFIG_BT_ATH3K=m
-CONFIG_BT_MTKSDIO=m
-CONFIG_BT_MTKUART=m
-CONFIG_BT_VIRTIO=m
-CONFIG_BT_HCIRSI=m
-# end of Bluetooth device drivers
-
-CONFIG_AF_RXRPC=m
-CONFIG_AF_RXRPC_IPV6=y
-# CONFIG_AF_RXRPC_INJECT_LOSS is not set
-# CONFIG_AF_RXRPC_DEBUG is not set
-# CONFIG_RXKAD is not set
-CONFIG_AF_KCM=m
-CONFIG_STREAM_PARSER=y
-CONFIG_FIB_RULES=y
-CONFIG_WIRELESS=y
-CONFIG_WIRELESS_EXT=y
-# CONFIG_WEXT_CORE is not set
-# CONFIG_WEXT_PROC is not set
-# CONFIG_WEXT_SPY is not set
-# CONFIG_WEXT_PRIV is not set
-CONFIG_CFG80211=m
-CONFIG_NL80211_TESTMODE=y
-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
-CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
-CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
-CONFIG_CFG80211_DEFAULT_PS=y
-# CONFIG_CFG80211_DEBUGFS is not set
-CONFIG_CFG80211_CRDA_SUPPORT=y
-# CONFIG_CFG80211_WEXT is not set
-# CONFIG_CFG80211_WEXT_EXPORT is not set
-CONFIG_LIB80211=m
-CONFIG_LIB80211_CRYPT_WEP=m
-CONFIG_LIB80211_CRYPT_CCMP=m
-CONFIG_LIB80211_CRYPT_TKIP=m
-# CONFIG_LIB80211_DEBUG is not set
-CONFIG_MAC80211=m
-CONFIG_MAC80211_HAS_RC=y
-CONFIG_MAC80211_RC_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
-CONFIG_MAC80211_MESH=y
-CONFIG_MAC80211_LEDS=y
-# CONFIG_MAC80211_DEBUGFS is not set
-# CONFIG_MAC80211_MESSAGE_TRACING is not set
-# CONFIG_MAC80211_DEBUG_MENU is not set
-CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
-CONFIG_WIMAX=m
-CONFIG_WIMAX_DEBUG_LEVEL=8
-CONFIG_RFKILL=m
-CONFIG_RFKILL_LEDS=y
-CONFIG_RFKILL_INPUT=y
-CONFIG_RFKILL_GPIO=m
-CONFIG_NET_9P=m
-CONFIG_NET_9P_VIRTIO=m
-CONFIG_NET_9P_RDMA=m
-# CONFIG_NET_9P_DEBUG is not set
-CONFIG_CAIF=m
-# CONFIG_CAIF_DEBUG is not set
-CONFIG_CAIF_NETDEV=m
-CONFIG_CAIF_USB=m
-CONFIG_CEPH_LIB=m
-# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
-CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
-CONFIG_NFC=m
-CONFIG_NFC_DIGITAL=m
-CONFIG_NFC_NCI=m
-CONFIG_NFC_NCI_SPI=m
-CONFIG_NFC_NCI_UART=m
-CONFIG_NFC_HCI=m
-CONFIG_NFC_SHDLC=y
-
-#
-# Near Field Communication (NFC) devices
-#
-CONFIG_NFC_TRF7970A=m
-CONFIG_NFC_SIM=m
-CONFIG_NFC_PORT100=m
-CONFIG_NFC_VIRTUAL_NCI=m
-CONFIG_NFC_FDP=m
-CONFIG_NFC_FDP_I2C=m
-CONFIG_NFC_PN544=m
-CONFIG_NFC_PN544_I2C=m
-CONFIG_NFC_PN533=m
-CONFIG_NFC_PN533_USB=m
-CONFIG_NFC_PN533_I2C=m
-CONFIG_NFC_PN532_UART=m
-CONFIG_NFC_MICROREAD=m
-CONFIG_NFC_MICROREAD_I2C=m
-CONFIG_NFC_MRVL=m
-CONFIG_NFC_MRVL_USB=m
-CONFIG_NFC_MRVL_UART=m
-CONFIG_NFC_MRVL_I2C=m
-CONFIG_NFC_MRVL_SPI=m
-CONFIG_NFC_ST21NFCA=m
-CONFIG_NFC_ST21NFCA_I2C=m
-CONFIG_NFC_ST_NCI=m
-CONFIG_NFC_ST_NCI_I2C=m
-CONFIG_NFC_ST_NCI_SPI=m
-CONFIG_NFC_NXP_NCI=m
-CONFIG_NFC_NXP_NCI_I2C=m
-CONFIG_NFC_S3FWRN5=m
-CONFIG_NFC_S3FWRN5_I2C=m
-CONFIG_NFC_S3FWRN82_UART=m
-CONFIG_NFC_ST95HF=m
-# end of Near Field Communication (NFC) devices
-
-CONFIG_PSAMPLE=m
-CONFIG_NET_IFE=m
-CONFIG_LWTUNNEL=y
-CONFIG_LWTUNNEL_BPF=y
-# CONFIG_PAGE_POOL_STATS is not set
-CONFIG_DST_CACHE=y
-CONFIG_GRO_CELLS=y
-CONFIG_SOCK_VALIDATE_XMIT=y
-CONFIG_NET_SOCK_MSG=y
-CONFIG_NET_DEVLINK=y
-CONFIG_PAGE_POOL=y
-CONFIG_FAILOVER=m
-CONFIG_ETHTOOL_NETLINK=y
-CONFIG_HAVE_EBPF_JIT=y
-
-#
-# Device Drivers
-#
-CONFIG_ARM_AMBA=y
-CONFIG_TEGRA_AHB=y
-CONFIG_HAVE_PCI=y
-CONFIG_FORCE_PCI=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_SYSCALL=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_HOTPLUG_PCI_PCIE=y
-CONFIG_PCIEAER=y
-# CONFIG_PCIEAER_INJECT is not set
-CONFIG_PCIE_ECRC=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-CONFIG_PCIE_PME=y
-CONFIG_PCIE_DPC=y
-CONFIG_PCIE_PTM=y
-# CONFIG_PCIE_BW is not set
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_MSI_ARCH_FALLBACKS=y
-CONFIG_PCI_QUIRKS=y
-# CONFIG_PCI_DEBUG is not set
-CONFIG_PCI_REALLOC_ENABLE_AUTO=y
-CONFIG_PCI_STUB=m
-CONFIG_PCI_PF_STUB=m
-CONFIG_PCI_ATS=y
-CONFIG_PCI_ECAM=y
-CONFIG_PCI_IOV=y
-CONFIG_PCI_PRI=y
-CONFIG_PCI_PASID=y
-# CONFIG_PCIE_BUS_TUNE_OFF is not set
-CONFIG_PCIE_BUS_DEFAULT=y
-# CONFIG_PCIE_BUS_SAFE is not set
-# CONFIG_PCIE_BUS_PERFORMANCE is not set
-# CONFIG_PCIE_BUS_PEER2PEER is not set
-CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_CPCI=y
-CONFIG_HOTPLUG_PCI_SHPC=y
-
-#
-# PCI controller drivers
-#
-# CONFIG_PCI_MVEBU is not set
-CONFIG_PCI_FTPCI100=y
-# CONFIG_PCI_IXP4XX is not set
-# CONFIG_PCI_TEGRA is not set
-# CONFIG_PCI_RCAR_GEN2 is not set
-# CONFIG_PCIE_RCAR is not set
-# CONFIG_PCIE_RCAR_HOST is not set
-# CONFIG_PCIE_RCAR_EP is not set
-CONFIG_PCI_HOST_COMMON=y
-CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCIE_XILINX=y
-CONFIG_PCI_V3_SEMI=y
-CONFIG_PCIE_ALTERA=m
-CONFIG_PCIE_ALTERA_MSI=m
-# CONFIG_PCIE_ROCKCHIP_HOST is not set
-# CONFIG_PCIE_ROCKCHIP_EP is not set
-# CONFIG_PCIE_MEDIATEK is not set
-CONFIG_PCIE_MEDIATEK_GEN3=m
-CONFIG_PCIE_BRCMSTB=m
-CONFIG_PCIE_MICROCHIP_HOST=y
-
-#
-# DesignWare PCI Core Support
-#
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_DW_EP=y
-CONFIG_PCIE_DW_PLAT=y
-CONFIG_PCIE_DW_PLAT_HOST=y
-CONFIG_PCIE_DW_PLAT_EP=y
-CONFIG_PCI_EXYNOS=m
-# CONFIG_PCI_IMX6 is not set
-# CONFIG_PCIE_SPEAR13XX is not set
-# CONFIG_PCI_KEYSTONE_HOST is not set
-# CONFIG_PCI_KEYSTONE_EP is not set
-CONFIG_PCI_LAYERSCAPE=y
-CONFIG_PCI_LAYERSCAPE_EP=y
-# CONFIG_PCIE_QCOM is not set
-# CONFIG_PCIE_ARMADA_8K is not set
-# CONFIG_PCIE_HISI_STB is not set
-CONFIG_PCI_MESON=y
-# CONFIG_PCIE_UNIPHIER is not set
-# CONFIG_PCIE_UNIPHIER_EP is not set
-# end of DesignWare PCI Core Support
-
-#
-# Mobiveil PCIe Core Support
-#
-# end of Mobiveil PCIe Core Support
-
-#
-# Cadence PCIe controllers support
-#
-CONFIG_PCIE_CADENCE=y
-CONFIG_PCIE_CADENCE_HOST=y
-CONFIG_PCIE_CADENCE_EP=y
-CONFIG_PCIE_CADENCE_PLAT=y
-CONFIG_PCIE_CADENCE_PLAT_HOST=y
-CONFIG_PCIE_CADENCE_PLAT_EP=y
-CONFIG_PCI_J721E=y
-CONFIG_PCI_J721E_HOST=y
-CONFIG_PCI_J721E_EP=y
-# end of Cadence PCIe controllers support
-# end of PCI controller drivers
-
-#
-# PCI Endpoint
-#
-CONFIG_PCI_ENDPOINT=y
-CONFIG_PCI_ENDPOINT_CONFIGFS=y
-# CONFIG_PCI_EPF_TEST is not set
-CONFIG_PCI_EPF_NTB=m
-# end of PCI Endpoint
-CONFIG_CXL_BUS=m
-CONFIG_CXL_PCI=m
-CONFIG_CXL_MEM=m
-CONFIG_CXL_MEM_RAW_COMMANDS=y
-CONFIG_CXL_ACPI=m
-CONFIG_CXL_PMEM=m
-
-#
-# PCI switch controller drivers
-#
-CONFIG_PCI_SW_SWITCHTEC=m
-# end of PCI switch controller drivers
-
-CONFIG_PCCARD=m
-CONFIG_PCMCIA=m
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_CARDBUS=y
-
-#
-# PC-card bridges
-#
-CONFIG_YENTA=m
-CONFIG_YENTA_O2=y
-CONFIG_YENTA_RICOH=y
-CONFIG_YENTA_TI=y
-CONFIG_YENTA_ENE_TUNE=y
-CONFIG_YENTA_TOSHIBA=y
-CONFIG_PD6729=m
-CONFIG_I82092=m
-# CONFIG_AT91_CF is not set
-CONFIG_PCCARD_NONSTATIC=y
-CONFIG_RAPIDIO=m
-CONFIG_RAPIDIO_TSI721=m
-CONFIG_RAPIDIO_DISC_TIMEOUT=30
-CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y
-CONFIG_RAPIDIO_DMA_ENGINE=y
-# CONFIG_RAPIDIO_DEBUG is not set
-CONFIG_RAPIDIO_ENUM_BASIC=m
-CONFIG_RAPIDIO_CHMAN=m
-CONFIG_RAPIDIO_MPORT_CDEV=m
-
-#
-# RapidIO Switch drivers
-#
-CONFIG_RAPIDIO_TSI57X=m
-CONFIG_RAPIDIO_CPS_XX=m
-CONFIG_RAPIDIO_TSI568=m
-CONFIG_RAPIDIO_CPS_GEN2=m
-CONFIG_RAPIDIO_RXS_GEN3=m
-# end of RapidIO Switch drivers
-
-#
-# Generic Driver Options
-#
-# CONFIG_UEVENT_HELPER is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-
-#
-# Firmware loader
-#
-CONFIG_FW_LOADER=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_FW_LOADER_USER_HELPER is not set
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_FW_LOADER_COMPRESS=y
-CONFIG_FW_CACHE=y
-# end of Firmware loader
-
-CONFIG_WANT_DEV_COREDUMP=y
-CONFIG_ALLOW_DEV_COREDUMP=y
-CONFIG_DEV_COREDUMP=y
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
-CONFIG_TEST_ASYNC_DRIVER_PROBE=m
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_SOC_BUS=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_SLIMBUS=m
-CONFIG_REGMAP_SPI=y
-CONFIG_REGMAP_SPMI=m
-CONFIG_REGMAP_W1=m
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_SOUNDWIRE=m
-CONFIG_REGMAP_SCCB=m
-CONFIG_REGMAP_I3C=m
-CONFIG_REGMAP_SPI_AVMM=m
-CONFIG_DMA_SHARED_BUFFER=y
-# CONFIG_DMA_FENCE_TRACE is not set
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-# end of Generic Driver Options
-
-#
-# Bus devices
-#
-CONFIG_ARM_CCI=y
-CONFIG_ARM_CCI400_COMMON=y
-CONFIG_ARM_CCI400_PORT_CTRL=y
-CONFIG_BRCMSTB_GISB_ARB=y
-CONFIG_MOXTET=m
-# CONFIG_IMX_WEIM is not set
-CONFIG_MVEBU_MBUS=y
-CONFIG_OMAP_INTERCONNECT=y
-# CONFIG_OMAP_OCP2SCP is not set
-CONFIG_QCOM_EBI2=y
-CONFIG_SIMPLE_PM_BUS=m
-# CONFIG_SUN50I_DE2_BUS is not set
-CONFIG_SUNXI_RSB=y
-# CONFIG_TEGRA_GMI is not set
-CONFIG_TI_SYSC=y
-CONFIG_UNIPHIER_SYSTEM_BUS=y
-CONFIG_VEXPRESS_CONFIG=y
-CONFIG_MHI_BUS=m
-# CONFIG_MHI_BUS_DEBUG is not set
-CONFIG_MHI_BUS_PCI_GENERIC=m
-# end of Bus devices
-
-CONFIG_CONNECTOR=m
-CONFIG_GNSS=m
-CONFIG_GNSS_SERIAL=m
-CONFIG_GNSS_MTK_SERIAL=m
-CONFIG_GNSS_SIRF_SERIAL=m
-CONFIG_GNSS_UBX_SERIAL=m
-CONFIG_MTD=m
-CONFIG_MTD_TESTS=m
-
-#
-# Partition parsers
-#
-CONFIG_MTD_AR7_PARTS=m
-CONFIG_MTD_CMDLINE_PARTS=m
-CONFIG_MTD_OF_PARTS=m
-CONFIG_MTD_OF_PARTS_BCM4908=y
-CONFIG_MTD_OF_PARTS_LINKSYS_NS=y
-# CONFIG_MTD_AFS_PARTS is not set
-CONFIG_MTD_PARSER_TRX=m
-CONFIG_MTD_REDBOOT_PARTS=m
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-CONFIG_MTD_QCOMSMEM_PARTS=m
-# end of Partition parsers
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
-CONFIG_MTD_BLOCK_RO=m
-CONFIG_FTL=m
-CONFIG_NFTL=m
-CONFIG_NFTL_RW=y
-CONFIG_INFTL=m
-CONFIG_RFD_FTL=m
-CONFIG_SSFDC=m
-CONFIG_SM_FTL=m
-CONFIG_MTD_OOPS=m
-CONFIG_MTD_PSTORE=m
-CONFIG_MTD_SWAP=m
-CONFIG_MTD_PARTITIONED_MASTER=y
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_GEN_PROBE=m
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-CONFIG_MTD_CFI_INTELEXT=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_CFI_STAA=m
-CONFIG_MTD_CFI_UTIL=m
-CONFIG_MTD_RAM=m
-CONFIG_MTD_ROM=m
-CONFIG_MTD_ABSENT=m
-# end of RAM/ROM/Flash chip drivers
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=m
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-# CONFIG_MTD_PHYSMAP_OF is not set
-# CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set
-CONFIG_MTD_IMPA7=m
-CONFIG_MTD_PCI=m
-CONFIG_MTD_PCMCIA=m
-# CONFIG_MTD_PCMCIA_ANONYMOUS is not set
-CONFIG_MTD_INTEL_VR_NOR=m
-CONFIG_MTD_PLATRAM=m
-# end of Mapping drivers for chip access
-
-#
-# Self-contained MTD device drivers
-#
-CONFIG_MTD_PMC551=m
-CONFIG_MTD_PMC551_BUGFIX=y
-# CONFIG_MTD_PMC551_DEBUG is not set
-CONFIG_MTD_DATAFLASH=m
-CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
-CONFIG_MTD_DATAFLASH_OTP=y
-CONFIG_MTD_MCHP23K256=m
-CONFIG_MTD_MCHP48L640=m
-CONFIG_MTD_SPEAR_SMI=m
-CONFIG_MTD_SST25L=m
-CONFIG_MTD_BCM47XXSFLASH=m
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTDRAM_TOTAL_SIZE=4096
-CONFIG_MTDRAM_ERASE_SIZE=128
-CONFIG_MTD_BLOCK2MTD=m
-
-#
-# Disk-On-Chip Device Drivers
-#
-CONFIG_MTD_DOCG3=m
-# CONFIG_MTD_ST_SPI_FSM is not set
-CONFIG_BCH_CONST_M=14
-CONFIG_BCH_CONST_T=4
-# end of Self-contained MTD device drivers
-
-#
-# NAND
-#
-CONFIG_MTD_NAND_CORE=m
-CONFIG_MTD_ONENAND=m
-CONFIG_MTD_ONENAND_VERIFY_WRITE=y
-CONFIG_MTD_ONENAND_GENERIC=m
-# CONFIG_MTD_ONENAND_OMAP2 is not set
-# CONFIG_MTD_ONENAND_SAMSUNG is not set
-CONFIG_MTD_ONENAND_OTP=y
-CONFIG_MTD_ONENAND_2X_PROGRAM=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=m
-# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
-CONFIG_MTD_RAW_NAND=m
-CONFIG_MTD_NAND_ECC_SW_BCH=y
-CONFIG_MTD_NAND_ECC_MXIC=y
-
-#
-# Raw/parallel NAND flash controllers
-#
-CONFIG_MTD_NAND_DENALI=m
-# CONFIG_MTD_NAND_DENALI_PCI is not set
-CONFIG_MTD_NAND_DENALI_DT=m
-CONFIG_MTD_NAND_OMAP2=m
-CONFIG_MTD_NAND_OMAP_BCH=y
-# CONFIG_MTD_NAND_OMAP2 is not set
-# CONFIG_MTD_NAND_TANGO is not set
-CONFIG_MTD_NAND_CAFE=m
-# CONFIG_MTD_NAND_ATMEL is not set
-# CONFIG_MTD_NAND_ORION is not set
-# CONFIG_MTD_NAND_MARVELL is not set
-# CONFIG_MTD_NAND_TMIO is not set
-CONFIG_MTD_NAND_BRCMNAND=m
-CONFIG_MTD_NAND_BRCMNAND_BCM63XX=m
-CONFIG_MTD_NAND_BRCMNAND_BCMBCA=m
-CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=m
-CONFIG_MTD_NAND_BRCMNAND_IPROC=m
-# CONFIG_MTD_NAND_MXC is not set
-# CONFIG_MTD_NAND_FSMC is not set
-# CONFIG_MTD_NAND_SUNXI is not set
-# CONFIG_MTD_NAND_HISI504 is not set
-# CONFIG_MTD_NAND_QCOM is not set
-# CONFIG_MTD_NAND_MTK is not set
-CONFIG_MTD_NAND_MXIC=m
-# CONFIG_MTD_NAND_TEGRA is not set
-# CONFIG_MTD_NAND_STM32_FMC2 is not set
-# CONFIG_MTD_NAND_MESON is not set
-CONFIG_MTD_NAND_GPIO=m
-CONFIG_MTD_NAND_PLATFORM=m
-CONFIG_MTD_NAND_CADENCE=m
-CONFIG_MTD_NAND_ARASAN=m
-CONFIG_MTD_NAND_INTEL_LGM=m
-CONFIG_MTD_NAND_ROCKCHIP=m
-CONFIG_MTD_NAND_PL35X=m
-
-#
-# Misc
-#
-CONFIG_MTD_SM_COMMON=m
-CONFIG_MTD_NAND_NANDSIM=m
-CONFIG_MTD_NAND_RICOH=m
-CONFIG_MTD_NAND_DISKONCHIP=m
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
-CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
-CONFIG_MTD_SPI_NAND=m
-
-#
-# ECC engine support
-#
-CONFIG_MTD_NAND_ECC=y
-# end of ECC engine support
-# end of NAND
-
-#
-# LPDDR & LPDDR2 PCM memory drivers
-#
-CONFIG_MTD_LPDDR=m
-CONFIG_MTD_QINFO_PROBE=m
-CONFIG_MTD_LPDDR2_NVM=m
-# end of LPDDR & LPDDR2 PCM memory drivers
-
-CONFIG_MTD_SPI_NOR=m
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SPI_NOR_SWP_DISABLE=y
-# CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE is not set
-# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
-# CONFIG_SPI_ASPEED_SMC is not set
-# CONFIG_SPI_HISI_SFC is not set
-CONFIG_MTD_UBI=m
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_GLUEBI=m
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_HYPERBUS=m
-CONFIG_DTC=y
-CONFIG_OF=y
-# CONFIG_OF_UNITTEST is not set
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_NET=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OF_RESOLVE=y
-CONFIG_OF_OVERLAY=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_PARPORT=m
-CONFIG_PARPORT_PC=m
-CONFIG_PARPORT_PC_FIFO=y
-CONFIG_PARPORT_SERIAL=m
-CONFIG_PARPORT_PC_FIFO=y
-CONFIG_PARPORT_PC_SUPERIO=y
-CONFIG_PARPORT_PC_PCMCIA=m
-CONFIG_PARPORT_AX88796=m
-CONFIG_PARPORT_1284=y
-CONFIG_PARPORT_NOT_PC=y
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_NULL_BLK is not set
-CONFIG_CDROM=m
-# CONFIG_PARIDE is not set
-CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
-CONFIG_ZRAM=m
-# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
-CONFIG_ZRAM_DEF_COMP_ZSTD=y
-# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
-# CONFIG_ZRAM_DEF_COMP_LZO is not set
-# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
-# CONFIG_ZRAM_DEF_COMP_842 is not set
-CONFIG_ZRAM_WRITEBACK=y
-# CONFIG_ZRAM_MEMORY_TRACKING is not set
-CONFIG_BLK_DEV_UMEM=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_DRBD=m
-# CONFIG_DRBD_FAULT_INJECTION is not set
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_SX8=m
-CONFIG_BLK_DEV_RAM=m
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-CONFIG_CDROM_PKTCDVD_WCACHE=y
-CONFIG_ATA_OVER_ETH=m
-CONFIG_VIRTIO_BLK=m
-CONFIG_BLK_DEV_RBD=m
-CONFIG_BLK_DEV_RSXX=m
-CONFIG_BLK_DEV_RNBD=y
-CONFIG_BLK_DEV_RNBD_CLIENT=m
-CONFIG_BLK_DEV_RNBD_SERVER=m
-
-#
-# NVME Support
-#
-CONFIG_NVME_CORE=m
-CONFIG_BLK_DEV_NVME=m
-CONFIG_NVME_MULTIPATH=y
-CONFIG_NVME_VERBOSE_ERRORS=y
-CONFIG_NVME_HWMON=y
-CONFIG_NVME_FABRICS=m
-CONFIG_NVME_RDMA=m
-CONFIG_NVME_FC=m
-CONFIG_NVME_TCP=m
-CONFIG_NVME_TARGET=m
-CONFIG_NVME_TARGET_PASSTHRU=y
-CONFIG_NVME_TARGET_LOOP=m
-CONFIG_NVME_TARGET_RDMA=m
-CONFIG_NVME_TARGET_FC=m
-CONFIG_NVME_TARGET_FCLOOP=m
-CONFIG_NVME_TARGET_TCP=m
-# end of NVME Support
-
-#
-# Misc devices
-#
-CONFIG_SENSORS_LIS3LV02D=m
-CONFIG_AD525X_DPOT=m
-CONFIG_AD525X_DPOT_I2C=m
-CONFIG_AD525X_DPOT_SPI=m
-# CONFIG_ATMEL_TCLIB is not set
-# CONFIG_DUMMY_IRQ is not set
-CONFIG_PHANTOM=m
-CONFIG_TIFM_CORE=m
-CONFIG_TIFM_7XX1=m
-CONFIG_ICS932S401=m
-# CONFIG_ATMEL_SSC is not set
-CONFIG_ENCLOSURE_SERVICES=m
-CONFIG_HP_ILO=m
-# CONFIG_QCOM_FASTRPC is not set
-CONFIG_APDS9802ALS=m
-CONFIG_ISL29003=m
-CONFIG_ISL29020=m
-CONFIG_SENSORS_TSL2550=m
-CONFIG_SENSORS_BH1770=m
-CONFIG_SENSORS_APDS990X=m
-CONFIG_HMC6352=m
-CONFIG_DS1682=m
-CONFIG_LATTICE_ECP3_CONFIG=m
-CONFIG_SRAM=y
-CONFIG_DW_XDATA_PCIE=m
-CONFIG_SRAM_EXEC=y
-CONFIG_PCI_ENDPOINT_TEST=m
-CONFIG_XILINX_SDFEC=m
-CONFIG_MISC_RTSX=m
-CONFIG_PVPANIC=m
-CONFIG_GP_PCI1XXXX=m
-CONFIG_HISI_HIKEY_USB=m
-CONFIG_OPEN_DICE=m
-CONFIG_C2PORT=m
-
-#
-# EEPROM support
-#
-CONFIG_EEPROM_AT24=m
-CONFIG_EEPROM_AT25=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_EEPROM_MAX6875=m
-CONFIG_EEPROM_93CX6=m
-CONFIG_EEPROM_93XX46=m
-CONFIG_EEPROM_IDT_89HPESX=m
-CONFIG_EEPROM_EE1004=m
-# end of EEPROM support
-
-CONFIG_CB710_CORE=m
-# CONFIG_CB710_DEBUG is not set
-CONFIG_CB710_DEBUG_ASSUMPTIONS=y
-
-#
-# Texas Instruments shared transport line discipline
-#
-CONFIG_TI_ST=m
-# end of Texas Instruments shared transport line discipline
-
-CONFIG_SENSORS_LIS3_SPI=m
-CONFIG_SENSORS_LIS3_I2C=m
-CONFIG_ALTERA_STAPL=m
-
-#
-# Intel MIC & related support
-#
-CONFIG_VOP_BUS=m
-CONFIG_VOP=m
-# end of Intel MIC & related support
-
-CONFIG_ECHO=m
-CONFIG_BCM_VK=m
-CONFIG_BCM_VK_TTY=y
-CONFIG_MISC_ALCOR_PCI=m
-CONFIG_MISC_RTSX_PCI=m
-CONFIG_MISC_RTSX_USB=m
-CONFIG_HABANA_AI=m
-CONFIG_UACCE=m
-CONFIG_PVPANIC=y
-CONFIG_PVPANIC_MMIO=m
-CONFIG_PVPANIC_PCI=m
-# end of Misc devices
-
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=m
-CONFIG_RAID_ATTRS=m
-CONFIG_SCSI=m
-CONFIG_SCSI_DMA=y
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_ENCLOSURE=m
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_ISCSI_ATTRS=m
-CONFIG_SCSI_SAS_ATTRS=m
-CONFIG_SCSI_SAS_LIBSAS=m
-CONFIG_SCSI_SAS_ATA=y
-CONFIG_SCSI_SAS_HOST_SMP=y
-CONFIG_SCSI_SRP_ATTRS=m
-# end of SCSI Transports
-
-CONFIG_SCSI_LOWLEVEL=y
-CONFIG_ISCSI_TCP=m
-CONFIG_ISCSI_BOOT_SYSFS=m
-CONFIG_SCSI_CXGB3_ISCSI=m
-CONFIG_SCSI_CXGB4_ISCSI=m
-CONFIG_SCSI_BNX2_ISCSI=m
-CONFIG_SCSI_BNX2X_FCOE=m
-CONFIG_BE2ISCSI=m
-CONFIG_BLK_DEV_3W_XXXX_RAID=m
-CONFIG_SCSI_HPSA=m
-CONFIG_SCSI_3W_9XXX=m
-CONFIG_SCSI_3W_SAS=m
-CONFIG_SCSI_ACARD=m
-CONFIG_SCSI_AACRAID=m
-CONFIG_SCSI_AIC7XXX=m
-CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
-CONFIG_AIC7XXX_RESET_DELAY_MS=15000
-# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
-CONFIG_AIC7XXX_DEBUG_MASK=0
-# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC79XX=m
-CONFIG_AIC79XX_CMDS_PER_DEVICE=4
-CONFIG_AIC79XX_RESET_DELAY_MS=15000
-# CONFIG_AIC79XX_DEBUG_ENABLE is not set
-CONFIG_AIC79XX_DEBUG_MASK=0
-# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC94XX=m
-# CONFIG_AIC94XX_DEBUG is not set
-CONFIG_SCSI_MVSAS=m
-# CONFIG_SCSI_MVSAS_DEBUG is not set
-CONFIG_SCSI_MVSAS_TASKLET=y
-CONFIG_SCSI_MVUMI=m
-CONFIG_SCSI_ADVANSYS=m
-CONFIG_SCSI_ARCMSR=m
-CONFIG_SCSI_ESAS2R=m
-CONFIG_MEGARAID_NEWGEN=y
-CONFIG_MEGARAID_MM=m
-CONFIG_MEGARAID_MAILBOX=m
-CONFIG_MEGARAID_LEGACY=m
-CONFIG_MEGARAID_SAS=m
-CONFIG_SCSI_MPT3SAS=m
-CONFIG_SCSI_MPT2SAS_MAX_SGE=128
-CONFIG_SCSI_MPT3SAS_MAX_SGE=128
-CONFIG_SCSI_MPT2SAS=m
-CONFIG_SCSI_MPI3MR=m
-CONFIG_SCSI_SMARTPQI=m
-CONFIG_SCSI_UFSHCD=m
-CONFIG_SCSI_UFSHCD_PCI=m
-CONFIG_SCSI_UFS_DWC_TC_PCI=m
-CONFIG_SCSI_UFSHCD_PLATFORM=m
-CONFIG_SCSI_UFS_CDNS_PLATFORM=m
-CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m
-# CONFIG_SCSI_UFS_QCOM is not set
-# CONFIG_SCSI_UFS_MEDIATEK is not set
-# CONFIG_SCSI_UFS_HISI is not set
-CONFIG_SCSI_UFS_RENESAS=m
-# CONFIG_SCSI_UFS_BSG is not set
-CONFIG_SCSI_UFS_EXYNOS=m
-CONFIG_SCSI_HPTIOP=m
-CONFIG_SCSI_MYRB=m
-CONFIG_SCSI_MYRS=m
-CONFIG_LIBFC=m
-CONFIG_LIBFCOE=m
-CONFIG_FCOE=m
-CONFIG_SCSI_SNIC=m
-# CONFIG_SCSI_SNIC_DEBUG_FS is not set
-CONFIG_SCSI_DMX3191D=m
-CONFIG_SCSI_FDOMAIN=m
-CONFIG_SCSI_FDOMAIN_PCI=m
-CONFIG_SCSI_GDTH=m
-CONFIG_SCSI_IPS=m
-CONFIG_SCSI_INITIO=m
-CONFIG_SCSI_INIA100=m
-CONFIG_SCSI_PPA=m
-CONFIG_SCSI_IMM=m
-# CONFIG_SCSI_IZIP_EPP16 is not set
-# CONFIG_SCSI_IZIP_SLOW_CTR is not set
-CONFIG_SCSI_STEX=m
-CONFIG_SCSI_SYM53C8XX_2=m
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_IPR=m
-# CONFIG_SCSI_IPR_TRACE is not set
-# CONFIG_SCSI_IPR_DUMP is not set
-CONFIG_SCSI_QLOGIC_1280=m
-CONFIG_SCSI_QLA_FC=m
-CONFIG_TCM_QLA2XXX=m
-# CONFIG_TCM_QLA2XXX_DEBUG is not set
-CONFIG_SCSI_QLA_ISCSI=m
-CONFIG_QEDI=m
-CONFIG_QEDF=m
-CONFIG_SCSI_LPFC=m
-CONFIG_SCSI_EFCT=m
-# CONFIG_SCSI_LPFC_DEBUG_FS is not set
-CONFIG_SCSI_DC395x=m
-CONFIG_SCSI_AM53C974=m
-# CONFIG_SCSI_NSP32 is not set
-CONFIG_SCSI_WD719X=m
-# CONFIG_SCSI_DEBUG is not set
-CONFIG_SCSI_PMCRAID=m
-CONFIG_SCSI_PM8001=m
-CONFIG_SCSI_BFA_FC=m
-CONFIG_SCSI_VIRTIO=m
-CONFIG_SCSI_CHELSIO_FCOE=m
-CONFIG_SCSI_LOWLEVEL_PCMCIA=y
-CONFIG_PCMCIA_AHA152X=m
-CONFIG_PCMCIA_FDOMAIN=m
-# CONFIG_PCMCIA_NINJA_SCSI is not set
-CONFIG_PCMCIA_QLOGIC=m
-CONFIG_PCMCIA_SYM53C500=m
-CONFIG_SCSI_DH=y
-CONFIG_SCSI_DH_RDAC=m
-CONFIG_SCSI_DH_HP_SW=m
-CONFIG_SCSI_DH_EMC=m
-CONFIG_SCSI_DH_ALUA=m
-# end of SCSI device support
-
-CONFIG_HAVE_PATA_PLATFORM=y
-CONFIG_ATA=m
-CONFIG_SATA_HOST=y
-# CONFIG_ATA_VERBOSE_ERROR is not set
-CONFIG_ATA_FORCE=y
-CONFIG_SATA_PMP=y
-
-#
-# Controllers with non-SFF native interface
-#
-CONFIG_SATA_AHCI=m
-CONFIG_SATA_MOBILE_LPM_POLICY=0
-CONFIG_SATA_AHCI_PLATFORM=m
-# CONFIG_AHCI_DM816 is not set
-CONFIG_AHCI_DWC=m
-# CONFIG_AHCI_ST is not set
-# CONFIG_AHCI_IMX is not set
-CONFIG_AHCI_CEVA=m
-# CONFIG_AHCI_MTK is not set
-# CONFIG_AHCI_MVEBU is not set
-# CONFIG_AHCI_SUNXI is not set
-# CONFIG_AHCI_TEGRA is not set
-CONFIG_AHCI_QORIQ=m
-CONFIG_SATA_INIC162X=m
-CONFIG_SATA_ACARD_AHCI=m
-CONFIG_SATA_SIL24=m
-CONFIG_ATA_SFF=y
-
-#
-# SFF controllers with custom DMA interface
-#
-CONFIG_PDC_ADMA=m
-CONFIG_SATA_QSTOR=m
-CONFIG_SATA_SX4=m
-CONFIG_ATA_BMDMA=y
-
-#
-# SATA SFF controllers with BMDMA
-#
-CONFIG_ATA_PIIX=m
-CONFIG_SATA_DWC=m
-# CONFIG_SATA_DWC_OLD_DMA is not set
-# CONFIG_SATA_DWC_DEBUG is not set
-# CONFIG_SATA_HIGHBANK is not set
-CONFIG_SATA_MV=m
-CONFIG_SATA_NV=m
-CONFIG_SATA_PROMISE=m
-# CONFIG_SATA_RCAR is not set
-CONFIG_SATA_SIL=m
-CONFIG_SATA_SIS=m
-CONFIG_SATA_SVW=m
-CONFIG_SATA_ULI=m
-CONFIG_SATA_VIA=m
-CONFIG_SATA_VITESSE=m
-
-#
-# PATA SFF controllers with BMDMA
-#
-# CONFIG_PATA_ALI is not set
-# CONFIG_PATA_AMD is not set
-# CONFIG_PATA_ARASAN_CF is not set
-# CONFIG_PATA_ARTOP is not set
-# CONFIG_PATA_ATIIXP is not set
-# CONFIG_PATA_ATP867X is not set
-# CONFIG_PATA_CMD64X is not set
-# CONFIG_PATA_CYPRESS is not set
-# CONFIG_PATA_EFAR is not set
-# CONFIG_PATA_HPT366 is not set
-# CONFIG_PATA_HPT37X is not set
-# CONFIG_PATA_HPT3X2N is not set
-# CONFIG_PATA_HPT3X3 is not set
-# CONFIG_PATA_IMX is not set
-# CONFIG_PATA_IT8213 is not set
-# CONFIG_PATA_IT821X is not set
-# CONFIG_PATA_JMICRON is not set
-# CONFIG_PATA_MARVELL is not set
-# CONFIG_PATA_NETCELL is not set
-CONFIG_PATA_NINJA32=m
-# CONFIG_PATA_NS87415 is not set
-# CONFIG_PATA_OLDPIIX is not set
-# CONFIG_PATA_OPTIDMA is not set
-# CONFIG_PATA_PDC2027X is not set
-# CONFIG_PATA_PDC_OLD is not set
-# CONFIG_PATA_RADISYS is not set
-# CONFIG_PATA_RDC is not set
-# CONFIG_PATA_SCH is not set
-# CONFIG_PATA_SERVERWORKS is not set
-# CONFIG_PATA_SIL680 is not set
-CONFIG_PATA_SIS=m
-CONFIG_PATA_TOSHIBA=m
-# CONFIG_PATA_TRIFLEX is not set
-# CONFIG_PATA_VIA is not set
-# CONFIG_PATA_WINBOND is not set
-
-#
-# PIO-only SFF controllers
-#
-# CONFIG_PATA_CMD640_PCI is not set
-# CONFIG_PATA_MPIIX is not set
-# CONFIG_PATA_NS87410 is not set
-# CONFIG_PATA_OPTI is not set
-# CONFIG_PATA_PCMCIA is not set
-# CONFIG_PATA_PLATFORM is not set
-CONFIG_PATA_OF_PLATFORM=m
-# CONFIG_PATA_RZ1000 is not set
-
-#
-# Generic fallback / legacy drivers
-#
-# CONFIG_ATA_GENERIC is not set
-# CONFIG_PATA_LEGACY is not set
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID456=m
-CONFIG_MD_MULTIPATH=m
-CONFIG_MD_FAULTY=m
-CONFIG_MD_CLUSTER=m
-CONFIG_BCACHE=m
-# CONFIG_BCACHE_DEBUG is not set
-# CONFIG_BCACHE_CLOSURES_DEBUG is not set
-CONFIG_BCACHE_ASYNC_REGISTRATION=y
-CONFIG_BLK_DEV_DM_BUILTIN=y
-CONFIG_BLK_DEV_DM=m
-# CONFIG_DM_DEBUG is not set
-CONFIG_DM_BUFIO=m
-# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
-CONFIG_DM_BIO_PRISON=m
-CONFIG_DM_PERSISTENT_DATA=m
-CONFIG_DM_UNSTRIPED=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_THIN_PROVISIONING=m
-CONFIG_DM_CACHE=m
-CONFIG_DM_CACHE_SMQ=m
-CONFIG_DM_WRITECACHE=m
-# CONFIG_DM_EBS is not set
-CONFIG_DM_ERA=m
-CONFIG_DM_CLONE=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_LOG_USERSPACE=m
-CONFIG_DM_RAID=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_QL=m
-CONFIG_DM_MULTIPATH_ST=m
-CONFIG_DM_MULTIPATH_HST=m
-CONFIG_DM_MULTIPATH_IOA=m
-CONFIG_DM_DELAY=m
-CONFIG_DM_DUST=m
-CONFIG_DM_UEVENT=y
-CONFIG_DM_FLAKEY=m
-CONFIG_DM_VERITY=m
-CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
-# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING is not set
-# CONFIG_DM_VERITY_FEC is not set
-CONFIG_DM_SWITCH=m
-CONFIG_DM_LOG_WRITES=m
-CONFIG_DM_INTEGRITY=m
-CONFIG_DM_ZONED=m
-CONFIG_TARGET_CORE=m
-CONFIG_TCM_IBLOCK=m
-CONFIG_TCM_FILEIO=m
-CONFIG_TCM_PSCSI=m
-CONFIG_TCM_USER2=m
-CONFIG_LOOPBACK_TARGET=m
-CONFIG_TCM_FC=m
-CONFIG_ISCSI_TARGET=m
-CONFIG_ISCSI_TARGET_CXGB4=m
-CONFIG_SBP_TARGET=m
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=m
-CONFIG_FUSION_FC=m
-CONFIG_FUSION_SAS=m
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_CTL=m
-CONFIG_FUSION_LAN=m
-CONFIG_FUSION_LOGGING=y
-
-#
-# IEEE 1394 (FireWire) support
-#
-CONFIG_FIREWIRE=m
-CONFIG_FIREWIRE_OHCI=m
-CONFIG_FIREWIRE_SBP2=m
-CONFIG_FIREWIRE_NET=m
-CONFIG_FIREWIRE_NOSY=m
-# end of IEEE 1394 (FireWire) support
-
-CONFIG_NETDEVICES=y
-CONFIG_MII=m
-CONFIG_NET_CORE=y
-CONFIG_BONDING=m
-CONFIG_DUMMY=m
-CONFIG_WIREGUARD=m
-# CONFIG_WIREGUARD_DEBUG is not set
-CONFIG_EQUALIZER=m
-CONFIG_NET_FC=y
-CONFIG_IFB=m
-CONFIG_NET_TEAM=m
-CONFIG_NET_TEAM_MODE_BROADCAST=m
-CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
-CONFIG_NET_TEAM_MODE_RANDOM=m
-CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
-CONFIG_NET_TEAM_MODE_LOADBALANCE=m
-CONFIG_MACVLAN=m
-CONFIG_MACVTAP=m
-CONFIG_IPVLAN_L3S=y
-CONFIG_IPVLAN=m
-CONFIG_IPVTAP=m
-CONFIG_VXLAN=m
-CONFIG_GENEVE=m
-CONFIG_BAREUDP=m
-CONFIG_GTP=m
-CONFIG_MACSEC=m
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_NETPOLL=y
-CONFIG_NET_POLL_CONTROLLER=y
-CONFIG_NTB_NETDEV=m
-CONFIG_RIONET=m
-CONFIG_RIONET_TX_SIZE=128
-CONFIG_RIONET_RX_SIZE=128
-CONFIG_TUN=m
-CONFIG_TAP=m
-# CONFIG_TUN_VNET_CROSS_LE is not set
-CONFIG_VETH=m
-CONFIG_VIRTIO_NET=m
-CONFIG_NLMON=m
-CONFIG_NET_VRF=m
-CONFIG_VSOCKMON=m
-CONFIG_MHI_NET=m
-CONFIG_SUNGEM_PHY=m
-CONFIG_ARCNET=m
-CONFIG_ARCNET_1201=m
-CONFIG_ARCNET_1051=m
-CONFIG_ARCNET_RAW=m
-CONFIG_ARCNET_CAP=m
-CONFIG_ARCNET_COM90xx=m
-CONFIG_ARCNET_COM90xxIO=m
-CONFIG_ARCNET_RIM_I=m
-CONFIG_ARCNET_COM20020=m
-CONFIG_ARCNET_COM20020_PCI=m
-CONFIG_ARCNET_1201=m
-CONFIG_ARCNET_1051=m
-CONFIG_ARCNET_RAW=m
-CONFIG_ARCNET_CAP=m
-CONFIG_ARCNET_COM90xx=m
-CONFIG_ARCNET_COM90xxIO=m
-CONFIG_ARCNET_RIM_I=m
-CONFIG_ARCNET_COM20020=m
-CONFIG_ARCNET_COM20020_PCI=m
-CONFIG_ARCNET_COM20020_CS=m
-CONFIG_ATM_DRIVERS=y
-# CONFIG_ATM_DUMMY is not set
-CONFIG_ATM_TCP=m
-CONFIG_ATM_LANAI=m
-CONFIG_ATM_ENI=m
-# CONFIG_ATM_ENI_DEBUG is not set
-# CONFIG_ATM_ENI_TUNE_BURST is not set
-CONFIG_ATM_NICSTAR=m
-CONFIG_ATM_NICSTAR_USE_SUNI=y
-CONFIG_ATM_NICSTAR_USE_IDT77105=y
-CONFIG_ATM_IDT77252=m
-# CONFIG_ATM_IDT77252_DEBUG is not set
-# CONFIG_ATM_IDT77252_RCV_ALL is not set
-CONFIG_ATM_IDT77252_USE_SUNI=y
-CONFIG_ATM_IA=m
-# CONFIG_ATM_IA_DEBUG is not set
-CONFIG_ATM_FORE200E=m
-CONFIG_ATM_FORE200E_USE_TASKLET=y
-CONFIG_ATM_FORE200E_TX_RETRY=16
-CONFIG_ATM_FORE200E_DEBUG=0
-CONFIG_ATM_HE=m
-CONFIG_ATM_HE_USE_SUNI=y
-CONFIG_ATM_SOLOS=m
-# CONFIG_CAIF_DRIVERS is not set
-
-#
-# Distributed Switch Architecture drivers
-#
-CONFIG_B53=m
-CONFIG_B53_SPI_DRIVER=m
-CONFIG_B53_MDIO_DRIVER=m
-CONFIG_B53_MMAP_DRIVER=m
-CONFIG_B53_SRAB_DRIVER=m
-CONFIG_B53_SERDES=m
-CONFIG_NET_DSA_BCM_SF2=m
-CONFIG_NET_DSA_LOOP=m
-CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
-CONFIG_NET_DSA_LANTIQ_GSWIP=m
-CONFIG_NET_DSA_MT7530=m
-CONFIG_NET_DSA_MV88E6060=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-CONFIG_NET_DSA_MV88E6XXX=m
-CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
-CONFIG_NET_DSA_MV88E6XXX_PTP=y
-# CONFIG_NET_DSA_MSCC_FELIX is not set
-CONFIG_NET_DSA_MSCC_SEVILLE=m
-CONFIG_NET_DSA_AR9331=m
-CONFIG_NET_DSA_SJA1105=m
-CONFIG_NET_DSA_SJA1105_PTP=y
-CONFIG_NET_DSA_SJA1105_TAS=y
-# CONFIG_NET_DSA_SJA1105_VL is not set
-CONFIG_NET_DSA_XRS700X_I2C=m
-CONFIG_NET_DSA_XRS700X_MDIO=m
-CONFIG_NET_DSA_QCA8K=m
-CONFIG_NET_DSA_REALTEK_SMI=m
-CONFIG_NET_DSA_SMSC_LAN9303=m
-CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
-CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
-CONFIG_NET_DSA_VITESSE_VSC73XX=m
-CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
-CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
-# end of Distributed Switch Architecture drivers
-
-CONFIG_ETHERNET=y
-CONFIG_MDIO=m
-CONFIG_NET_VENDOR_3COM=y
-CONFIG_NET_VENDOR_ACTIONS=y
-CONFIG_OWL_EMAC=m
-CONFIG_PCMCIA_3C574=m
-CONFIG_PCMCIA_3C589=m
-CONFIG_TYPHOON=m
-CONFIG_NET_VENDOR_ADAPTEC=y
-CONFIG_ADAPTEC_STARFIRE=m
-CONFIG_NET_VENDOR_AGERE=y
-CONFIG_ET131X=m
-CONFIG_NET_VENDOR_ALACRITECH=y
-CONFIG_SLICOSS=m
-CONFIG_NET_VENDOR_ALLWINNER=y
-# CONFIG_SUN4I_EMAC is not set
-CONFIG_NET_VENDOR_ALTEON=y
-CONFIG_ACENIC=m
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
-CONFIG_ALTERA_TSE=m
-CONFIG_NET_VENDOR_AMAZON=y
-CONFIG_ENA_ETHERNET=m
-CONFIG_NET_VENDOR_AMD=y
-CONFIG_AMD8111_ETH=m
-CONFIG_PCNET32=m
-CONFIG_PCMCIA_NMCLAN=m
-CONFIG_NET_VENDOR_AQUANTIA=y
-CONFIG_AQTION=m
-CONFIG_NET_VENDOR_ARC=y
-# CONFIG_EMAC_ROCKCHIP is not set
-CONFIG_NET_VENDOR_ATHEROS=y
-CONFIG_ATL2=m
-CONFIG_ATL1=m
-CONFIG_ATL1E=m
-CONFIG_ATL1C=m
-CONFIG_ALX=m
-CONFIG_NET_VENDOR_AURORA=y
-CONFIG_AURORA_NB8800=m
-CONFIG_NET_VENDOR_BROADCOM=y
-CONFIG_B44=m
-CONFIG_BCM4908_ENET=m
-CONFIG_B44_PCI_AUTOSELECT=y
-CONFIG_B44_PCICORE_AUTOSELECT=y
-CONFIG_B44_PCI=y
-CONFIG_BCMGENET=m
-CONFIG_BNX2=m
-CONFIG_CNIC=m
-CONFIG_TIGON3=m
-CONFIG_TIGON3_HWMON=y
-CONFIG_BNX2X=m
-CONFIG_BNX2X_SRIOV=y
-CONFIG_SYSTEMPORT=m
-CONFIG_BNXT=m
-CONFIG_BNXT_SRIOV=y
-CONFIG_BNXT_FLOWER_OFFLOAD=y
-CONFIG_BNXT_DCB=y
-CONFIG_BNXT_HWMON=y
-CONFIG_NET_VENDOR_BROCADE=y
-CONFIG_BNA=m
-CONFIG_NET_VENDOR_CADENCE=y
-CONFIG_MACB=m
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MACB_PCI=m
-# CONFIG_NET_CALXEDA_XGMAC is not set
-CONFIG_NET_VENDOR_CAVIUM=y
-CONFIG_NET_VENDOR_CHELSIO=y
-CONFIG_CHELSIO_T1=m
-CONFIG_CHELSIO_T1_1G=y
-CONFIG_CHELSIO_T3=m
-CONFIG_CHELSIO_T4=m
-CONFIG_CHELSIO_T4_DCB=y
-# CONFIG_CHELSIO_T4_FCOE is not set
-CONFIG_CHELSIO_T4VF=m
-CONFIG_CHELSIO_LIB=m
-CONFIG_CHELSIO_INLINE_CRYPTO=y
-CONFIG_CHELSIO_IPSEC_INLINE=m
-CONFIG_CHELSIO_TLS_DEVICE=m
-CONFIG_NET_VENDOR_CIRRUS=y
-# CONFIG_CS89x0 is not set
-CONFIG_NET_VENDOR_CISCO=y
-CONFIG_ENIC=m
-# CONFIG_NET_VENDOR_CORTINA is not set
-CONFIG_NET_VENDOR_DAVICOM=y
-CONFIG_DM9051=m
-# CONFIG_DM9000 is not set
-CONFIG_DM9051=m
-CONFIG_DNET=m
-CONFIG_NET_VENDOR_DEC=y
-CONFIG_NET_TULIP=y
-CONFIG_DE2104X=m
-CONFIG_DE2104X_DSL=0
-CONFIG_TULIP=m
-CONFIG_TULIP_MWI=y
-CONFIG_TULIP_MMIO=y
-CONFIG_TULIP_NAPI=y
-CONFIG_TULIP_NAPI_HW_MITIGATION=y
-CONFIG_WINBOND_840=m
-CONFIG_DM9102=m
-CONFIG_ULI526X=m
-CONFIG_PCMCIA_XIRCOM=m
-CONFIG_NET_VENDOR_DLINK=y
-CONFIG_DL2K=m
-CONFIG_SUNDANCE=m
-# CONFIG_SUNDANCE_MMIO is not set
-CONFIG_NET_VENDOR_EMULEX=y
-CONFIG_BE2NET=m
-CONFIG_BE2NET_HWMON=y
-CONFIG_BE2NET_BE2=y
-CONFIG_BE2NET_BE3=y
-CONFIG_BE2NET_LANCER=y
-CONFIG_BE2NET_SKYHAWK=y
-CONFIG_NET_VENDOR_EZCHIP=y
-# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
-CONFIG_NET_VENDOR_FARADAY=y
-# CONFIG_FTMAC100 is not set
-# CONFIG_FTGMAC100 is not set
-CONFIG_NET_VENDOR_FREESCALE=y
-CONFIG_FEC=y
-# CONFIG_FSL_PQ_MDIO is not set
-# CONFIG_FSL_XGMAC_MDIO is not set
-# CONFIG_GIANFAR is not set
-CONFIG_FSL_DPAA2_SWITCH=m
-# CONFIG_FSL_ENETC is not set
-# CONFIG_FSL_ENETC_VF is not set
-CONFIG_FSL_ENETC_IERB=m
-# CONFIG_FSL_ENETC_MDIO is not set
-CONFIG_NET_VENDOR_FUJITSU=y
-CONFIG_NET_VENDOR_FUNGIBLE=y
-CONFIG_FUN_ETH=m
-CONFIG_PCMCIA_FMVJ18X=m
-CONFIG_NET_VENDOR_GOOGLE=y
-CONFIG_GVE=m
-CONFIG_NET_VENDOR_HISILICON=y
-# CONFIG_HIX5HD2_GMAC is not set
-# CONFIG_HISI_FEMAC is not set
-# CONFIG_HIP04_ETH is not set
-# CONFIG_HNS_DSAF is not set
-# CONFIG_HNS_ENET is not set
-# CONFIG_HNS3 is not set
-CONFIG_NET_VENDOR_HUAWEI=y
-CONFIG_NET_VENDOR_I825XX=y
-CONFIG_NET_VENDOR_INTEL=y
-CONFIG_E100=m
-CONFIG_E1000=m
-CONFIG_E1000E=m
-CONFIG_IGB=m
-CONFIG_IGB_HWMON=y
-CONFIG_IGBVF=m
-CONFIG_IXGB=m
-CONFIG_IXGBE=m
-CONFIG_IXGBE_HWMON=y
-CONFIG_IXGBE_DCB=y
-CONFIG_IXGBE_IPSEC=y
-CONFIG_IXGBEVF=m
-CONFIG_IXGBEVF_IPSEC=y
-CONFIG_I40E=m
-CONFIG_I40E_DCB=y
-CONFIG_IAVF=m
-CONFIG_I40EVF=m
-CONFIG_ICE=m
-CONFIG_FM10K=m
-CONFIG_IGC=m
-CONFIG_NET_VENDOR_MICROSOFT=y
-CONFIG_JME=m
-CONFIG_NET_VENDOR_MARVELL=y
-# CONFIG_MV643XX_ETH is not set
-CONFIG_MVMDIO=m
-# CONFIG_MVNETA is not set
-# CONFIG_MVPP2 is not set
-CONFIG_MVPP2_PTP=y
-# CONFIG_PXA168_ETH is not set
-CONFIG_SKGE=m
-# CONFIG_SKGE_DEBUG is not set
-CONFIG_SKGE_GENESIS=y
-CONFIG_SKY2=m
-# CONFIG_SKY2_DEBUG is not set
-CONFIG_PRESTERA=m
-CONFIG_PRESTERA_PCI=m
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NET_MEDIATEK_SOC=m
-CONFIG_NET_MEDIATEK_STAR_EMAC=m
-CONFIG_NET_VENDOR_MELLANOX=y
-CONFIG_MLX4_EN=m
-CONFIG_MLX4_EN_DCB=y
-CONFIG_MLX4_CORE=m
-# CONFIG_MLX4_DEBUG is not set
-CONFIG_MLX4_CORE_GEN2=y
-CONFIG_MLX5_CORE=m
-CONFIG_MLX5_ACCEL=y
-CONFIG_MLX5_FPGA=y
-# CONFIG_MLX5_CORE_EN is not set
-CONFIG_MLX5_FPGA_IPSEC=y
-CONFIG_MLXSW_CORE=m
-CONFIG_MLXSW_CORE_HWMON=y
-CONFIG_MLXSW_CORE_THERMAL=y
-CONFIG_MLXSW_PCI=m
-CONFIG_MLXSW_I2C=m
-CONFIG_MLXSW_SWITCHIB=m
-CONFIG_MLXSW_SWITCHX2=m
-CONFIG_MLXSW_SPECTRUM=m
-CONFIG_MLXSW_SPECTRUM_DCB=y
-CONFIG_MLXSW_MINIMAL=m
-CONFIG_MLXFW=m
-CONFIG_MLXFW_GIGE=m
-CONFIG_MLXBF_GIGE=m
-CONFIG_NET_VENDOR_MICREL=y
-CONFIG_KS8842=m
-CONFIG_KS8851=m
-CONFIG_KS8851_MLL=m
-CONFIG_KSZ884X_PCI=m
-CONFIG_NET_VENDOR_MICROCHIP=y
-CONFIG_ENC28J60=m
-# CONFIG_ENC28J60_WRITEVERIFY is not set
-CONFIG_ENCX24J600=m
-CONFIG_LAN743X=m
-CONFIG_SPARX5_SWITCH=m
-CONFIG_NET_VENDOR_MICROSEMI=y
-CONFIG_MSCC_OCELOT_SWITCH_LIB=m
-CONFIG_MSCC_OCELOT_SWITCH=m
-CONFIG_NET_VENDOR_MYRI=y
-CONFIG_MYRI10GE=m
-CONFIG_FEALNX=m
-CONFIG_NET_VENDOR_NATSEMI=y
-CONFIG_NATSEMI=m
-CONFIG_NS83820=m
-CONFIG_NET_VENDOR_NETERION=y
-CONFIG_S2IO=m
-CONFIG_VXGE=m
-# CONFIG_VXGE_DEBUG_TRACE_ALL is not set
-CONFIG_NET_VENDOR_NETRONOME=y
-CONFIG_NFP=m
-# CONFIG_NFP_APP_FLOWER is not set
-CONFIG_NFP_APP_ABM_NIC=y
-# CONFIG_NFP_DEBUG is not set
-CONFIG_NET_VENDOR_NI=y
-CONFIG_NI_XGE_MANAGEMENT_ENET=m
-CONFIG_NET_VENDOR_8390=y
-CONFIG_PCMCIA_AXNET=m
-# CONFIG_AX88796 is not set
-CONFIG_NE2K_PCI=m
-CONFIG_PCMCIA_PCNET=m
-CONFIG_NET_VENDOR_NVIDIA=y
-CONFIG_FORCEDETH=m
-CONFIG_NET_VENDOR_OKI=y
-CONFIG_ETHOC=m
-CONFIG_NET_VENDOR_PACKET_ENGINES=y
-CONFIG_HAMACHI=m
-CONFIG_YELLOWFIN=m
-CONFIG_NET_VENDOR_PENSANDO=y
-CONFIG_NET_VENDOR_QLOGIC=y
-CONFIG_QLA3XXX=m
-CONFIG_QLCNIC=m
-CONFIG_QLCNIC_SRIOV=y
-CONFIG_QLCNIC_DCB=y
-CONFIG_QLCNIC_HWMON=y
-CONFIG_NETXEN_NIC=m
-CONFIG_QED=m
-CONFIG_QED_LL2=y
-CONFIG_QED_SRIOV=y
-CONFIG_QEDE=m
-CONFIG_QED_ISCSI=y
-CONFIG_QED_FCOE=y
-CONFIG_QED_OOO=y
-CONFIG_NET_VENDOR_QUALCOMM=y
-# CONFIG_QCA7000_SPI is not set
-# CONFIG_QCA7000_UART is not set
-CONFIG_QCOM_EMAC=m
-CONFIG_RMNET=m
-CONFIG_NET_VENDOR_RDC=y
-CONFIG_R6040=m
-CONFIG_NET_VENDOR_REALTEK=y
-CONFIG_8139CP=m
-CONFIG_8139TOO=m
-# CONFIG_8139TOO_PIO is not set
-CONFIG_8139TOO_TUNE_TWISTER=y
-CONFIG_8139TOO_8129=y
-# CONFIG_8139_OLD_RX_RESET is not set
-CONFIG_R8169=m
-CONFIG_NET_VENDOR_RENESAS=y
-# CONFIG_SH_ETH is not set
-# CONFIG_RAVB is not set
-CONFIG_NET_VENDOR_ROCKER=y
-CONFIG_ROCKER=m
-CONFIG_NET_VENDOR_SAMSUNG=y
-CONFIG_SXGBE_ETH=m
-CONFIG_NET_VENDOR_SEEQ=y
-CONFIG_NET_VENDOR_SOLARFLARE=y
-CONFIG_SFC=m
-CONFIG_SFC_MTD=y
-CONFIG_SFC_MCDI_MON=y
-CONFIG_SFC_SRIOV=y
-CONFIG_SFC_MCDI_LOGGING=y
-CONFIG_SFC_FALCON=m
-CONFIG_SFC_FALCON_MTD=y
-CONFIG_NET_VENDOR_SILAN=y
-CONFIG_SC92031=m
-CONFIG_NET_VENDOR_SIS=y
-CONFIG_SIS900=m
-CONFIG_SIS190=m
-CONFIG_NET_VENDOR_SMSC=y
-# CONFIG_SMC91X is not set
-CONFIG_PCMCIA_SMC91C92=m
-CONFIG_EPIC100=m
-# CONFIG_SMC911X is not set
-CONFIG_SMSC911X=m
-CONFIG_SMSC9420=m
-# CONFIG_NET_VENDOR_SOCIONEXT is not set
-CONFIG_NET_VENDOR_STMICRO=y
-CONFIG_STMMAC_ETH=m
-# CONFIG_STMMAC_SELFTESTS is not set
-CONFIG_STMMAC_PLATFORM=m
-CONFIG_DWMAC_LOONGSON=m
-# CONFIG_DWMAC_DWC_QOS_ETH is not set
-CONFIG_DWMAC_GENERIC=m
-CONFIG_DWMAC_IPQ806X=m
-# CONFIG_DWMAC_MEDIATEK is not set
-CONFIG_DWMAC_MESON=m
-CONFIG_DWMAC_QCOM_ETHQOS=m
-CONFIG_DWMAC_ROCKCHIP=y
-CONFIG_DWMAC_SOCFPGA=m
-CONFIG_DWMAC_STI=m
-CONFIG_DWMAC_STM32=m
-CONFIG_DWMAC_SUNXI=m
-CONFIG_DWMAC_SUN8I=m
-CONFIG_DWMAC_IMX8=m
-CONFIG_DWMAC_INTEL_PLAT=m
-CONFIG_DWMAC_VISCONTI=m
-CONFIG_STMMAC_PCI=m
-CONFIG_NET_VENDOR_SUN=y
-CONFIG_HAPPYMEAL=m
-CONFIG_SUNGEM=m
-CONFIG_CASSINI=m
-CONFIG_NIU=m
-CONFIG_NET_VENDOR_SYNOPSYS=y
-CONFIG_DWC_XLGMAC=m
-CONFIG_DWC_XLGMAC_PCI=m
-CONFIG_NET_VENDOR_TEHUTI=y
-CONFIG_TEHUTI=m
-CONFIG_NET_VENDOR_TI=y
-# CONFIG_TI_DAVINCI_EMAC is not set
-# CONFIG_TI_DAVINCI_MDIO is not set
-# CONFIG_TI_CPSW_PHY_SEL is not set
-# CONFIG_TI_CPSW is not set
-# CONFIG_TI_CPSW_SWITCHDEV is not set
-# CONFIG_TI_CPTS is not set
-CONFIG_TLAN=m
-CONFIG_NET_VENDOR_VIA=y
-CONFIG_VIA_RHINE=m
-CONFIG_VIA_RHINE_MMIO=y
-CONFIG_VIA_VELOCITY=m
-CONFIG_NET_VENDOR_WIZNET=y
-CONFIG_WIZNET_W5100=m
-CONFIG_WIZNET_W5300=m
-# CONFIG_WIZNET_BUS_DIRECT is not set
-# CONFIG_WIZNET_BUS_INDIRECT is not set
-CONFIG_WIZNET_BUS_ANY=y
-CONFIG_WIZNET_W5100_SPI=m
-CONFIG_NET_VENDOR_XILINX=y
-CONFIG_XILINX_EMACLITE=m
-# CONFIG_XILINX_EMACLITE is not set
-CONFIG_XILINX_AXI_EMAC=m
-CONFIG_XILINX_LL_TEMAC=m
-CONFIG_NET_VENDOR_XIRCOM=y
-CONFIG_PCMCIA_XIRC2PS=m
-CONFIG_FDDI=m
-CONFIG_DEFXX=m
-# CONFIG_DEFXX_MMIO is not set
-CONFIG_SKFP=m
-CONFIG_HIPPI=y
-CONFIG_ROADRUNNER=m
-CONFIG_ROADRUNNER_LARGE_RINGS=y
-CONFIG_PHYLINK=m
-CONFIG_PHYLIB=y
-CONFIG_SWPHY=y
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_FIXED_PHY=y
-CONFIG_SFP=m
-
-#
-# MII PHY device drivers
-#
-CONFIG_AMD_PHY=m
-# CONFIG_MESON_GXL_PHY is not set
-CONFIG_ADIN_PHY=m
-CONFIG_AQUANTIA_PHY=m
-CONFIG_AX88796B_PHY=m
-CONFIG_BROADCOM_PHY=m
-CONFIG_BCM54140_PHY=m
-CONFIG_BCM7XXX_PHY=m
-CONFIG_BCM84881_PHY=m
-CONFIG_BCM87XX_PHY=m
-CONFIG_BCM_NET_PHYLIB=m
-CONFIG_CICADA_PHY=m
-CONFIG_CORTINA_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_ICPLUS_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_INTEL_XWAY_PHY=m
-CONFIG_LSI_ET1011C_PHY=m
-CONFIG_MARVELL_PHY=m
-CONFIG_MARVELL_10G_PHY=m
-CONFIG_MARVELL_88X2222_PHY=m
-CONFIG_MEDIATEK_GE_PHY=m
-CONFIG_MICREL_PHY=m
-CONFIG_MICROCHIP_PHY=m
-CONFIG_MICROCHIP_T1_PHY=m
-CONFIG_MICROSEMI_PHY=m
-CONFIG_MOTORCOMM_PHY=m
-CONFIG_NATIONAL_PHY=m
-CONFIG_NXP_C45_TJA11XX_PHY=m
-CONFIG_NXP_TJA11XX_PHY=m
-CONFIG_AT803X_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_REALTEK_PHY=m
-CONFIG_RENESAS_PHY=m
-CONFIG_ROCKCHIP_PHY=m
-CONFIG_SMSC_PHY=m
-CONFIG_STE10XP=m
-CONFIG_TERANETICS_PHY=m
-CONFIG_DP83822_PHY=m
-CONFIG_DP83TC811_PHY=m
-CONFIG_DP83848_PHY=m
-CONFIG_DP83867_PHY=m
-CONFIG_DP83869_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_XILINX_GMII2RGMII=m
-CONFIG_WWAN=y
-CONFIG_WWAN_HWSIM=m
-CONFIG_WWAN_CORE=m
-CONFIG_RPMSG_WWAN_CTRL=m
-CONFIG_IOSM=m
-# CONFIG_TEST_MAPLE_TREE is not set
-CONFIG_MHI_WWAN_CTRL=m
-CONFIG_MICREL_KS8995MA=m
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_BUS=y
-CONFIG_OF_MDIO=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MDIO_SUN4I is not set
-# CONFIG_MDIO_ASPEED is not set
-CONFIG_MDIO_BITBANG=m
-CONFIG_MDIO_BCM_UNIMAC=m
-CONFIG_MDIO_GPIO=m
-# CONFIG_MDIO_HISI_FEMAC is not set
-CONFIG_MDIO_I2C=m
-CONFIG_MDIO_MVUSB=m
-CONFIG_MDIO_MSCC_MIIM=m
-# CONFIG_MDIO_IPQ4019 is not set
-# CONFIG_MDIO_IPQ8064 is not set
-
-#
-# MDIO Multiplexers
-#
-CONFIG_MDIO_BUS_MUX=m
-CONFIG_MDIO_BUS_MUX_MESON_G12A=m
-# CONFIG_MDIO_BUS_MUX_GPIO is not set
-# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set
-# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
-
-#
-# PCS device drivers
-#
-CONFIG_PCS_XPCS=m
-CONFIG_PCS_LYNX=m
-# end of PCS device drivers
-
-CONFIG_PLIP=m
-CONFIG_PPP=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_MPPE=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPPOATM=m
-CONFIG_PPPOE=m
-CONFIG_PPTP=m
-CONFIG_PPPOL2TP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_SLIP=m
-CONFIG_SLHC=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-
-#
-# Host-side USB support is needed for USB Network Adapter support
-#
-CONFIG_USB_NET_DRIVERS=m
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_RTL8152=m
-CONFIG_USB_LAN78XX=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_AX8817X=m
-CONFIG_USB_NET_AX88179_178A=m
-CONFIG_USB_NET_CDCETHER=m
-CONFIG_USB_NET_CDC_EEM=m
-CONFIG_USB_NET_CDC_NCM=m
-CONFIG_USB_NET_HUAWEI_CDC_NCM=m
-CONFIG_USB_NET_CDC_MBIM=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_SR9700=m
-CONFIG_USB_NET_SR9800=m
-CONFIG_USB_NET_SMSC75XX=m
-CONFIG_USB_NET_SMSC95XX=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_NET1080=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_MCS7830=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
-CONFIG_USB_NET_CDC_SUBSET=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_BELKIN=y
-CONFIG_USB_ARMLINUX=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-CONFIG_USB_NET_ZAURUS=m
-CONFIG_USB_NET_CX82310_ETH=m
-CONFIG_USB_NET_KALMIA=m
-CONFIG_USB_NET_QMI_WWAN=m
-CONFIG_USB_HSO=m
-CONFIG_USB_NET_INT51X1=m
-CONFIG_USB_CDC_PHONET=m
-CONFIG_USB_IPHETH=m
-CONFIG_USB_SIERRA_NET=m
-CONFIG_USB_VL600=m
-CONFIG_USB_NET_CH9200=m
-CONFIG_USB_NET_AQC111=m
-CONFIG_USB_RTL8153_ECM=m
-CONFIG_WLAN=y
-# CONFIG_WIRELESS_WDS is not set
-CONFIG_WLAN_VENDOR_ADMTEK=y
-CONFIG_ADM8211=m
-CONFIG_ATH_COMMON=m
-CONFIG_WLAN_VENDOR_ATH=y
-# CONFIG_ATH_DEBUG is not set
-CONFIG_ATH5K=m
-# CONFIG_ATH5K_DEBUG is not set
-# CONFIG_ATH5K_TRACER is not set
-CONFIG_ATH5K_PCI=y
-CONFIG_ATH9K_HW=m
-CONFIG_ATH9K_COMMON=m
-CONFIG_ATH9K_BTCOEX_SUPPORT=y
-CONFIG_ATH9K=m
-CONFIG_ATH9K_PCI=y
-CONFIG_ATH9K_AHB=y
-# CONFIG_ATH9K_DEBUGFS is not set
-CONFIG_ATH9K_DYNACK=y
-CONFIG_ATH9K_WOW=y
-CONFIG_ATH9K_RFKILL=y
-CONFIG_ATH9K_CHANNEL_CONTEXT=y
-CONFIG_ATH9K_PCOEM=y
-CONFIG_ATH9K_PCI_NO_EEPROM=m
-CONFIG_ATH9K_HTC=m
-# CONFIG_ATH9K_HTC_DEBUGFS is not set
-CONFIG_ATH9K_HWRNG=y
-CONFIG_CARL9170=m
-CONFIG_CARL9170_LEDS=y
-CONFIG_CARL9170_WPC=y
-# CONFIG_CARL9170_HWRNG is not set
-CONFIG_ATH6KL=m
-CONFIG_ATH6KL_SDIO=m
-CONFIG_ATH6KL_USB=m
-# CONFIG_ATH6KL_DEBUG is not set
-# CONFIG_ATH6KL_TRACING is not set
-CONFIG_AR5523=m
-CONFIG_WIL6210=m
-CONFIG_WIL6210_ISR_COR=y
-CONFIG_WIL6210_TRACING=y
-CONFIG_WIL6210_DEBUGFS=y
-CONFIG_ATH10K=m
-CONFIG_ATH10K_CE=y
-CONFIG_ATH10K_PCI=m
-# CONFIG_ATH10K_AHB is not set
-CONFIG_ATH10K_SDIO=m
-CONFIG_ATH10K_USB=m
-# CONFIG_ATH10K_SNOC is not set
-# CONFIG_ATH10K_DEBUG is not set
-# CONFIG_ATH10K_DEBUGFS is not set
-# CONFIG_ATH10K_TRACING is not set
-CONFIG_WCN36XX=m
-# CONFIG_WCN36XX_DEBUGFS is not set
-CONFIG_ATH11K=m
-CONFIG_ATH11K_PCI=m
-# CONFIG_ATH11K_DEBUG is not set
-# CONFIG_ATH11K_TRACING is not set
-CONFIG_WLAN_VENDOR_ATMEL=y
-CONFIG_ATMEL=m
-CONFIG_PCI_ATMEL=m
-CONFIG_PCMCIA_ATMEL=m
-CONFIG_AT76C50X_USB=m
-CONFIG_WLAN_VENDOR_BROADCOM=y
-CONFIG_B43=m
-CONFIG_B43_BCMA=y
-CONFIG_B43_SSB=y
-CONFIG_B43_BUSES_BCMA_AND_SSB=y
-# CONFIG_B43_BUSES_BCMA is not set
-# CONFIG_B43_BUSES_SSB is not set
-CONFIG_B43_PCI_AUTOSELECT=y
-CONFIG_B43_PCICORE_AUTOSELECT=y
-CONFIG_B43_SDIO=y
-CONFIG_B43_BCMA_PIO=y
-CONFIG_B43_PIO=y
-CONFIG_B43_PHY_G=y
-CONFIG_B43_PHY_N=y
-CONFIG_B43_PHY_LP=y
-CONFIG_B43_PHY_HT=y
-CONFIG_B43_LEDS=y
-CONFIG_B43_HWRNG=y
-# CONFIG_B43_DEBUG is not set
-CONFIG_B43LEGACY=m
-CONFIG_B43LEGACY_PCI_AUTOSELECT=y
-CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
-CONFIG_B43LEGACY_LEDS=y
-CONFIG_B43LEGACY_HWRNG=y
-# CONFIG_B43LEGACY_DEBUG is not set
-CONFIG_B43LEGACY_DMA=y
-CONFIG_B43LEGACY_PIO=y
-CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
-# CONFIG_B43LEGACY_DMA_MODE is not set
-# CONFIG_B43LEGACY_PIO_MODE is not set
-CONFIG_BRCMUTIL=m
-CONFIG_BRCMSMAC=m
-CONFIG_BRCMFMAC=m
-CONFIG_BRCMFMAC_PROTO_BCDC=y
-CONFIG_BRCMFMAC_PROTO_MSGBUF=y
-CONFIG_BRCMFMAC_SDIO=y
-CONFIG_BRCMFMAC_USB=y
-CONFIG_BRCMFMAC_PCIE=y
-CONFIG_BRCM_TRACING=y
-# CONFIG_BRCMDBG is not set
-CONFIG_WLAN_VENDOR_CISCO=y
-CONFIG_AIRO_CS=m
-CONFIG_WLAN_VENDOR_INTEL=y
-CONFIG_IPW2100=m
-CONFIG_IPW2100_MONITOR=y
-# CONFIG_IPW2100_DEBUG is not set
-CONFIG_IPW2200=m
-CONFIG_IPW2200_MONITOR=y
-CONFIG_IPW2200_RADIOTAP=y
-CONFIG_IPW2200_PROMISCUOUS=y
-CONFIG_IPW2200_QOS=y
-# CONFIG_IPW2200_DEBUG is not set
-CONFIG_LIBIPW=m
-# CONFIG_LIBIPW_DEBUG is not set
-CONFIG_IWLEGACY=m
-CONFIG_IWL4965=m
-CONFIG_IWL3945=m
-
-#
-# iwl3945 / iwl4965 Debugging Options
-#
-# CONFIG_IWLEGACY_DEBUG is not set
-# end of iwl3945 / iwl4965 Debugging Options
-
-CONFIG_IWLWIFI=m
-CONFIG_IWLWIFI_LEDS=y
-CONFIG_IWLDVM=m
-CONFIG_IWLMVM=m
-CONFIG_IWLWIFI_OPMODE_MODULAR=y
-# CONFIG_IWLWIFI_BCAST_FILTERING is not set
-CONFIG_IWLMEI=m
-
-#
-# Debugging Options
-#
-# CONFIG_IWLWIFI_DEBUG is not set
-CONFIG_IWLWIFI_DEVICE_TRACING=y
-# end of Debugging Options
-
-CONFIG_WLAN_VENDOR_INTERSIL=y
-CONFIG_HOSTAP=m
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_HOSTAP_PLX=m
-CONFIG_HOSTAP_PCI=m
-CONFIG_HOSTAP_CS=m
-CONFIG_HERMES=m
-CONFIG_HERMES_PRISM=y
-CONFIG_HERMES_CACHE_FW_ON_INIT=y
-CONFIG_PLX_HERMES=m
-CONFIG_TMD_HERMES=m
-CONFIG_NORTEL_HERMES=m
-CONFIG_PCI_HERMES=m
-CONFIG_ORINOCO_USB=m
-CONFIG_P54_COMMON=m
-CONFIG_P54_USB=m
-CONFIG_P54_PCI=m
-CONFIG_P54_SPI=m
-CONFIG_P54_SPI_DEFAULT_EEPROM=y
-CONFIG_P54_LEDS=y
-CONFIG_PRISM54=m
-CONFIG_WLAN_VENDOR_MARVELL=y
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_USB=m
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_LIBERTAS_SPI=m
-# CONFIG_LIBERTAS_DEBUG is not set
-CONFIG_LIBERTAS_MESH=y
-CONFIG_LIBERTAS_THINFIRM=m
-# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
-CONFIG_LIBERTAS_THINFIRM_USB=m
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
-CONFIG_MWIFIEX_PCIE=m
-CONFIG_MWIFIEX_USB=m
-CONFIG_MWL8K=m
-CONFIG_WLAN_VENDOR_MEDIATEK=y
-CONFIG_MT7601U=m
-CONFIG_MT76_CORE=m
-CONFIG_MT76_LEDS=y
-CONFIG_MT76_USB=m
-CONFIG_MT76_SDIO=m
-CONFIG_MT76x02_LIB=m
-CONFIG_MT76x02_USB=m
-CONFIG_MT76x0_COMMON=m
-CONFIG_MT76x0U=m
-CONFIG_MT76x0E=m
-CONFIG_MT76x2_COMMON=m
-CONFIG_MT76x2E=m
-CONFIG_MT76x2U=m
-CONFIG_MT7603E=m
-CONFIG_MT7615_COMMON=m
-CONFIG_MT7615E=m
-CONFIG_MT7622_WMAC=y
-CONFIG_MT7663_USB_SDIO_COMMON=m
-CONFIG_MT7663U=m
-CONFIG_MT7663S=m
-CONFIG_MT7915E=m
-CONFIG_MT7986_WMAC=y
-CONFIG_MT7921E=m
-CONFIG_WLAN_VENDOR_MICROCHIP=y
-CONFIG_WILC1000=m
-CONFIG_WILC1000_SDIO=m
-CONFIG_WILC1000_SPI=m
-# CONFIG_WILC1000_HW_OOB_INTR is not set
-CONFIG_WLAN_VENDOR_RALINK=y
-CONFIG_RT2X00=m
-CONFIG_RT2400PCI=m
-CONFIG_RT2500PCI=m
-CONFIG_RT61PCI=m
-CONFIG_RT2800PCI=m
-CONFIG_RT2800PCI_RT33XX=y
-CONFIG_RT2800PCI_RT35XX=y
-CONFIG_RT2800PCI_RT53XX=y
-CONFIG_RT2800PCI_RT3290=y
-CONFIG_RT2500USB=m
-CONFIG_RT73USB=m
-CONFIG_RT2800USB=m
-CONFIG_RT2800USB_RT33XX=y
-CONFIG_RT2800USB_RT35XX=y
-CONFIG_RT2800USB_RT3573=y
-CONFIG_RT2800USB_RT53XX=y
-CONFIG_RT2800USB_RT55XX=y
-CONFIG_RT2800USB_UNKNOWN=y
-CONFIG_RT2800_LIB=m
-CONFIG_RT2800_LIB_MMIO=m
-CONFIG_RT2X00_LIB_MMIO=m
-CONFIG_RT2X00_LIB_PCI=m
-CONFIG_RT2X00_LIB_USB=m
-CONFIG_RT2X00_LIB=m
-CONFIG_RT2X00_LIB_FIRMWARE=y
-CONFIG_RT2X00_LIB_CRYPTO=y
-CONFIG_RT2X00_LIB_LEDS=y
-# CONFIG_RT2X00_DEBUG is not set
-CONFIG_WLAN_VENDOR_REALTEK=y
-CONFIG_RTL8180=m
-CONFIG_RTL8187=m
-CONFIG_RTL8187_LEDS=y
-CONFIG_RTL_CARDS=m
-CONFIG_RTL8192CE=m
-CONFIG_RTL8192SE=m
-CONFIG_RTL8192DE=m
-CONFIG_RTL8723AE=m
-CONFIG_RTL8723BE=m
-CONFIG_RTL8188EE=m
-CONFIG_RTL8192EE=m
-CONFIG_RTL8821AE=m
-CONFIG_RTL8192CU=m
-CONFIG_RTLWIFI=m
-CONFIG_RTLWIFI_PCI=m
-CONFIG_RTLWIFI_USB=m
-# CONFIG_RTLWIFI_DEBUG is not set
-CONFIG_RTL8192C_COMMON=m
-CONFIG_RTL8723_COMMON=m
-CONFIG_RTLBTCOEXIST=m
-CONFIG_RTL8XXXU=m
-CONFIG_RTL8XXXU_UNTESTED=y
-CONFIG_RTW88=m
-CONFIG_RTW88_CORE=m
-CONFIG_RTW88_PCI=m
-CONFIG_RTW88_8822B=m
-CONFIG_RTW88_8822C=m
-CONFIG_RTW88_8723D=m
-CONFIG_RTW88_8821C=m
-CONFIG_RTW88_8822BE=m
-CONFIG_RTW88_8822CE=m
-CONFIG_RTW88_8723DE=m
-CONFIG_RTW88_8821CE=m
-# CONFIG_RTW88_DEBUG is not set
-# CONFIG_RTW88_DEBUGFS is not set
-CONFIG_WLAN_VENDOR_RSI=y
-CONFIG_RSI_91X=m
-# CONFIG_RSI_DEBUGFS is not set
-CONFIG_RSI_SDIO=m
-CONFIG_RSI_USB=m
-CONFIG_RSI_COEX=y
-CONFIG_WLAN_VENDOR_ST=y
-CONFIG_CW1200=m
-CONFIG_CW1200_WLAN_SDIO=m
-CONFIG_CW1200_WLAN_SPI=m
-CONFIG_WLAN_VENDOR_TI=y
-CONFIG_WL1251=m
-CONFIG_WL1251_SPI=m
-CONFIG_WL1251_SDIO=m
-CONFIG_WL12XX=m
-CONFIG_WL18XX=m
-CONFIG_WLCORE=m
-# CONFIG_WLCORE_SPI is not set
-CONFIG_WLCORE_SDIO=m
-CONFIG_WILINK_PLATFORM_DATA=y
-CONFIG_WLAN_VENDOR_ZYDAS=y
-CONFIG_USB_ZD1201=m
-CONFIG_ZD1211RW=m
-# CONFIG_ZD1211RW_DEBUG is not set
-CONFIG_WLAN_VENDOR_QUANTENNA=y
-CONFIG_QTNFMAC=m
-CONFIG_QTNFMAC_PCIE=m
-CONFIG_PCMCIA_RAYCS=m
-CONFIG_PCMCIA_WL3501=m
-# CONFIG_MAC80211_HWSIM is not set
-CONFIG_USB_NET_RNDIS_WLAN=m
-CONFIG_VIRT_WIFI=m
-
-#
-# WiMAX Wireless Broadband devices
-#
-CONFIG_WIMAX_I2400M=m
-CONFIG_WIMAX_I2400M_USB=m
-CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8
-# end of WiMAX Wireless Broadband devices
-
-CONFIG_WAN=y
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_PCI200SYN=m
-CONFIG_WANXL=m
-CONFIG_PC300TOO=m
-CONFIG_FARSYNC=m
-# CONFIG_SLIC_DS26522 is not set
-CONFIG_DLCI=m
-CONFIG_DLCI_MAX=8
-CONFIG_LAPBETHER=m
-CONFIG_X25_ASY=m
-CONFIG_IEEE802154_DRIVERS=m
-CONFIG_IEEE802154_FAKELB=m
-CONFIG_IEEE802154_AT86RF230=m
-# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set
-CONFIG_IEEE802154_MRF24J40=m
-CONFIG_IEEE802154_CC2520=m
-CONFIG_IEEE802154_ATUSB=m
-CONFIG_IEEE802154_ADF7242=m
-CONFIG_IEEE802154_CA8210=m
-# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
-CONFIG_IEEE802154_MCR20A=m
-CONFIG_IEEE802154_HWSIM=m
-CONFIG_VMXNET3=m
-CONFIG_USB4_NET=m
-CONFIG_NETDEVSIM=m
-CONFIG_NET_FAILOVER=m
-CONFIG_ISDN=y
-CONFIG_ISDN_CAPI=m
-# CONFIG_CAPI_TRACE is not set
-CONFIG_ISDN_CAPI_MIDDLEWARE=m
-CONFIG_MISDN=m
-CONFIG_MISDN_DSP=m
-CONFIG_MISDN_L1OIP=m
-
-#
-# mISDN hardware drivers
-#
-CONFIG_MISDN_HFCPCI=m
-CONFIG_MISDN_HFCMULTI=m
-CONFIG_MISDN_HFCUSB=m
-CONFIG_MISDN_AVMFRITZ=m
-CONFIG_MISDN_SPEEDFAX=m
-CONFIG_MISDN_INFINEON=m
-CONFIG_MISDN_W6692=m
-CONFIG_MISDN_NETJET=m
-CONFIG_MISDN_HDLC=m
-CONFIG_MISDN_IPAC=m
-CONFIG_MISDN_ISAR=m
-CONFIG_NVM=y
-CONFIG_NVM_PBLK=m
-# CONFIG_NVM_PBLK_DEBUG is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_LEDS=m
-CONFIG_INPUT_FF_MEMLESS=m
-CONFIG_INPUT_POLLDEV=m
-CONFIG_INPUT_SPARSEKMAP=m
-CONFIG_INPUT_MATRIXKMAP=m
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ADC=m
-CONFIG_KEYBOARD_ADP5588=m
-CONFIG_KEYBOARD_ADP5589=m
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_KEYBOARD_QT1050=m
-CONFIG_KEYBOARD_QT1070=m
-CONFIG_KEYBOARD_QT2160=m
-CONFIG_KEYBOARD_DLINK_DIR685=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_GPIO=m
-CONFIG_KEYBOARD_GPIO_POLLED=m
-CONFIG_KEYBOARD_TCA6416=m
-CONFIG_KEYBOARD_TCA8418=m
-CONFIG_KEYBOARD_MATRIX=m
-CONFIG_KEYBOARD_LM8323=m
-CONFIG_KEYBOARD_LM8333=m
-CONFIG_KEYBOARD_MAX7359=m
-CONFIG_KEYBOARD_MCS=m
-CONFIG_KEYBOARD_MPR121=m
-# CONFIG_KEYBOARD_SNVS_PWRKEY is not set
-# CONFIG_KEYBOARD_IMX is not set
-CONFIG_KEYBOARD_NEWTON=m
-# CONFIG_KEYBOARD_NOMADIK is not set
-# CONFIG_KEYBOARD_TEGRA is not set
-CONFIG_KEYBOARD_OPENCORES=m
-CONFIG_KEYBOARD_PINEPHONE=m
-# CONFIG_KEYBOARD_PXA27x is not set
-# CONFIG_KEYBOARD_PMIC8XXX is not set
-CONFIG_KEYBOARD_SAMSUNG=m
-CONFIG_KEYBOARD_STOWAWAY=m
-# CONFIG_KEYBOARD_ST_KEYSCAN is not set
-CONFIG_KEYBOARD_SUNKBD=m
-# CONFIG_KEYBOARD_STMPE is not set
-# CONFIG_KEYBOARD_SUN4I_LRADC is not set
-CONFIG_KEYBOARD_IQS62X=m
-CONFIG_KEYBOARD_OMAP4=m
-# CONFIG_KEYBOARD_SPEAR is not set
-CONFIG_KEYBOARD_TM2_TOUCHKEY=m
-# CONFIG_KEYBOARD_TWL4030 is not set
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_KEYBOARD_CROS_EC=m
-CONFIG_KEYBOARD_CAP11XX=m
-CONFIG_KEYBOARD_BCM=m
-CONFIG_KEYBOARD_MT6779=m
-CONFIG_KEYBOARD_MTK_PMIC=m
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_BYD=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
-CONFIG_MOUSE_PS2_CYPRESS=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-CONFIG_MOUSE_PS2_ELANTECH=y
-CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
-CONFIG_MOUSE_PS2_SENTELIC=y
-CONFIG_MOUSE_PS2_TOUCHKIT=y
-CONFIG_MOUSE_PS2_FOCALTECH=y
-CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_APPLETOUCH=m
-CONFIG_MOUSE_BCM5974=m
-CONFIG_MOUSE_CYAPA=m
-CONFIG_MOUSE_ELAN_I2C=m
-CONFIG_MOUSE_ELAN_I2C_I2C=y
-CONFIG_MOUSE_ELAN_I2C_SMBUS=y
-CONFIG_MOUSE_VSXXXAA=m
-CONFIG_MOUSE_GPIO=m
-CONFIG_MOUSE_SYNAPTICS_I2C=m
-CONFIG_MOUSE_SYNAPTICS_USB=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADC=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=m
-CONFIG_JOYSTICK_IFORCE_232=m
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_TWIDJOY=m
-CONFIG_JOYSTICK_ZHENHUA=m
-CONFIG_JOYSTICK_DB9=m
-CONFIG_JOYSTICK_GAMECON=m
-CONFIG_JOYSTICK_TURBOGRAFX=m
-CONFIG_JOYSTICK_AS5011=m
-# CONFIG_JOYSTICK_JOYDUMP is not set
-CONFIG_JOYSTICK_XPAD=m
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_JOYSTICK_WALKERA0701=m
-CONFIG_JOYSTICK_PSXPAD_SPI=m
-CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
-CONFIG_JOYSTICK_PXRC=m
-CONFIG_JOYSTICK_QWIIC=m
-CONFIG_JOYSTICK_FSIA6B=m
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=m
-CONFIG_TABLET_USB_AIPTEK=m
-CONFIG_TABLET_USB_GTCO=m
-CONFIG_TABLET_USB_HANWANG=m
-CONFIG_TABLET_USB_KBTAB=m
-CONFIG_TABLET_USB_PEGASUS=m
-CONFIG_TABLET_SERIAL_WACOM4=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_PROPERTIES=y
-CONFIG_TOUCHSCREEN_ADS7846=m
-CONFIG_TOUCHSCREEN_AD7877=m
-CONFIG_TOUCHSCREEN_AD7879=m
-CONFIG_TOUCHSCREEN_AD7879_I2C=m
-CONFIG_TOUCHSCREEN_AD7879_SPI=m
-CONFIG_TOUCHSCREEN_ADC=m
-CONFIG_TOUCHSCREEN_AR1021_I2C=m
-CONFIG_TOUCHSCREEN_ATMEL_MXT=m
-# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set
-CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
-CONFIG_TOUCHSCREEN_BU21013=m
-CONFIG_TOUCHSCREEN_BU21029=m
-CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
-CONFIG_TOUCHSCREEN_CY8CTMA140=m
-CONFIG_TOUCHSCREEN_CY8CTMG110=m
-CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
-CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
-CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
-CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
-CONFIG_TOUCHSCREEN_DA9052=m
-CONFIG_TOUCHSCREEN_DYNAPRO=m
-CONFIG_TOUCHSCREEN_HAMPSHIRE=m
-CONFIG_TOUCHSCREEN_EETI=m
-CONFIG_TOUCHSCREEN_EGALAX=m
-CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
-CONFIG_TOUCHSCREEN_EXC3000=m
-CONFIG_TOUCHSCREEN_FUJITSU=m
-CONFIG_TOUCHSCREEN_GOODIX=m
-CONFIG_TOUCHSCREEN_HIDEEP=m
-CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
-CONFIG_TOUCHSCREEN_ILI210X=m
-CONFIG_TOUCHSCREEN_ILITEK=m
-CONFIG_TOUCHSCREEN_S6SY761=m
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_TOUCHSCREEN_EKTF2127=m
-CONFIG_TOUCHSCREEN_ELAN=m
-CONFIG_TOUCHSCREEN_ELO=m
-CONFIG_TOUCHSCREEN_WACOM_W8001=m
-CONFIG_TOUCHSCREEN_WACOM_I2C=m
-CONFIG_TOUCHSCREEN_MAX11801=m
-CONFIG_TOUCHSCREEN_MCS5000=m
-CONFIG_TOUCHSCREEN_MMS114=m
-CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
-CONFIG_TOUCHSCREEN_MSG2638=m
-CONFIG_TOUCHSCREEN_MTOUCH=m
-CONFIG_TOUCHSCREEN_IMAGIS=m
-CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
-CONFIG_TOUCHSCREEN_INEXIO=m
-CONFIG_TOUCHSCREEN_MK712=m
-CONFIG_TOUCHSCREEN_PENMOUNT=m
-CONFIG_TOUCHSCREEN_EDT_FT5X06=m
-CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
-CONFIG_TOUCHSCREEN_TOUCHWIN=m
-CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m
-CONFIG_TOUCHSCREEN_UCB1400=m
-CONFIG_TOUCHSCREEN_PIXCIR=m
-CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
-CONFIG_TOUCHSCREEN_WM831X=m
-CONFIG_TOUCHSCREEN_WM97XX=m
-CONFIG_TOUCHSCREEN_WM9705=y
-CONFIG_TOUCHSCREEN_WM9712=y
-CONFIG_TOUCHSCREEN_WM9713=y
-CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-CONFIG_TOUCHSCREEN_MC13783=m
-CONFIG_TOUCHSCREEN_USB_EGALAX=y
-CONFIG_TOUCHSCREEN_USB_PANJIT=y
-CONFIG_TOUCHSCREEN_USB_3M=y
-CONFIG_TOUCHSCREEN_USB_ITM=y
-CONFIG_TOUCHSCREEN_USB_ETURBO=y
-CONFIG_TOUCHSCREEN_USB_GUNZE=y
-CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
-CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
-CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
-CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
-CONFIG_TOUCHSCREEN_USB_GOTOP=y
-CONFIG_TOUCHSCREEN_USB_JASTEC=y
-CONFIG_TOUCHSCREEN_USB_ELO=y
-CONFIG_TOUCHSCREEN_USB_E2I=y
-CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
-CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
-CONFIG_TOUCHSCREEN_USB_NEXIO=y
-CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
-CONFIG_TOUCHSCREEN_TOUCHIT213=m
-CONFIG_TOUCHSCREEN_TSC_SERIO=m
-CONFIG_TOUCHSCREEN_TSC200X_CORE=m
-CONFIG_TOUCHSCREEN_TSC2004=m
-CONFIG_TOUCHSCREEN_TSC2005=m
-CONFIG_TOUCHSCREEN_TSC2007=m
-CONFIG_TOUCHSCREEN_TSC2007_IIO=y
-CONFIG_TOUCHSCREEN_PCAP=m
-CONFIG_TOUCHSCREEN_RM_TS=m
-CONFIG_TOUCHSCREEN_SILEAD=m
-CONFIG_TOUCHSCREEN_SIS_I2C=m
-CONFIG_TOUCHSCREEN_ST1232=m
-CONFIG_TOUCHSCREEN_STMFTS=m
-# CONFIG_TOUCHSCREEN_STMPE is not set
-# CONFIG_TOUCHSCREEN_SUN4I is not set
-CONFIG_TOUCHSCREEN_SUR40=m
-CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
-CONFIG_TOUCHSCREEN_SX8654=m
-CONFIG_TOUCHSCREEN_TPS6507X=m
-CONFIG_TOUCHSCREEN_ZET6223=m
-CONFIG_TOUCHSCREEN_ZFORCE=m
-CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
-CONFIG_TOUCHSCREEN_ROHM_BU21023=m
-CONFIG_TOUCHSCREEN_IQS5XX=m
-CONFIG_TOUCHSCREEN_ZINITIX=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_ATC260X_ONKEY=m
-CONFIG_INPUT_88PM80X_ONKEY=m
-# CONFIG_INPUT_AB8500_PONKEY is not set
-CONFIG_INPUT_AD714X=m
-CONFIG_INPUT_AD714X_I2C=m
-CONFIG_INPUT_AD714X_SPI=m
-CONFIG_INPUT_ARIZONA_HAPTICS=m
-CONFIG_INPUT_ATMEL_CAPTOUCH=m
-CONFIG_INPUT_BMA150=m
-CONFIG_INPUT_E3X0_BUTTON=m
-# CONFIG_INPUT_PM8XXX_VIBRATOR is not set
-# CONFIG_INPUT_PMIC8XXX_PWRKEY is not set
-# CONFIG_INPUT_MAX77650_ONKEY is not set
-CONFIG_INPUT_MAX77693_HAPTIC=m
-CONFIG_INPUT_MC13783_PWRBUTTON=m
-CONFIG_INPUT_MMA8450=m
-CONFIG_INPUT_GPIO_BEEPER=m
-CONFIG_INPUT_GPIO_DECODER=m
-CONFIG_INPUT_GPIO_VIBRA=m
-# CONFIG_INPUT_CPCAP_PWRBUTTON is not set
-CONFIG_INPUT_ATI_REMOTE2=m
-CONFIG_INPUT_KEYSPAN_REMOTE=m
-CONFIG_INPUT_KXTJ9=m
-CONFIG_INPUT_POWERMATE=m
-CONFIG_INPUT_YEALINK=m
-CONFIG_INPUT_CM109=m
-CONFIG_INPUT_REGULATOR_HAPTIC=m
-CONFIG_INPUT_RETU_PWRBUTTON=m
-# CONFIG_INPUT_TPS65218_PWRBUTTON is not set
-CONFIG_INPUT_AXP20X_PEK=m
-# CONFIG_INPUT_TWL4030_PWRBUTTON is not set
-# CONFIG_INPUT_TWL4030_VIBRA is not set
-CONFIG_INPUT_UINPUT=m
-CONFIG_INPUT_PCF50633_PMU=m
-CONFIG_INPUT_PCF8574=m
-CONFIG_INPUT_PWM_BEEPER=m
-CONFIG_INPUT_PWM_VIBRA=m
-# CONFIG_INPUT_RK805_PWRKEY is not set
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-CONFIG_INPUT_DA7280_HAPTICS=m
-CONFIG_INPUT_DA9052_ONKEY=m
-CONFIG_INPUT_DA9063_ONKEY=m
-CONFIG_INPUT_WM831X_ON=m
-CONFIG_INPUT_PCAP=m
-CONFIG_INPUT_ADXL34X=m
-CONFIG_INPUT_IBM_PANEL=m
-CONFIG_INPUT_ADXL34X_I2C=m
-CONFIG_INPUT_ADXL34X_SPI=m
-CONFIG_INPUT_IMS_PCU=m
-CONFIG_INPUT_IQS269A=m
-CONFIG_INPUT_IQS626A=m
-CONFIG_INPUT_CMA3000=m
-CONFIG_INPUT_CMA3000_I2C=m
-CONFIG_INPUT_SIRFSOC_ONKEY=y
-CONFIG_INPUT_DRV260X_HAPTICS=m
-CONFIG_INPUT_DRV2665_HAPTICS=m
-CONFIG_INPUT_DRV2667_HAPTICS=m
-# CONFIG_INPUT_HISI_POWERKEY is not set
-CONFIG_INPUT_RT5120_PWRKEY=m
-CONFIG_INPUT_RAVE_SP_PWRBUTTON=m
-CONFIG_INPUT_RT5120_PWRKEY=m
-CONFIG_RMI4_CORE=m
-CONFIG_RMI4_I2C=m
-CONFIG_RMI4_SPI=m
-CONFIG_RMI4_SMB=m
-CONFIG_RMI4_F03=y
-CONFIG_RMI4_F03_SERIO=m
-CONFIG_RMI4_2D_SENSOR=y
-CONFIG_RMI4_F11=y
-CONFIG_RMI4_F12=y
-CONFIG_RMI4_F30=y
-CONFIG_RMI4_F34=y
-CONFIG_RMI4_F3A=y
-CONFIG_RMI4_F54=y
-CONFIG_RMI4_F55=y
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=m
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_PARKBD=m
-# CONFIG_SERIO_AMBAKMI is not set
-CONFIG_SERIO_PCIPS2=m
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_RAW=m
-CONFIG_SERIO_ALTERA_PS2=m
-CONFIG_SERIO_PS2MULT=m
-CONFIG_SERIO_ARC_PS2=m
-CONFIG_SERIO_APBPS2=m
-# CONFIG_SERIO_OLPC_APSP is not set
-# CONFIG_SERIO_SUN4I_PS2 is not set
-CONFIG_SERIO_GPIO_PS2=m
-CONFIG_USERIO=m
-CONFIG_GAMEPORT=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_GAMEPORT_EMU10K1=m
-CONFIG_GAMEPORT_FM801=m
-# end of Hardware I/O ports
-# end of Input device support
-
-#
-# Character devices
-#
-CONFIG_TTY=y
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LDISC_AUTOLOAD=y
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_EARLYCON=y
-CONFIG_SERIAL_8250=y
-# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
-CONFIG_SERIAL_8250_FINTEK=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_DMA=y
-CONFIG_SERIAL_8250_PCI=m
-CONFIG_SERIAL_8250_EXAR=m
-CONFIG_SERIAL_8250_CS=m
-CONFIG_SERIAL_8250_MEN_MCB=m
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-# CONFIG_SERIAL_8250_ASPEED_VUART is not set
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_DW=m
-# CONFIG_SERIAL_8250_EM is not set
-CONFIG_SERIAL_8250_RT288X=y
-# CONFIG_SERIAL_8250_OMAP is not set
-# CONFIG_SERIAL_8250_MT6577 is not set
-# CONFIG_SERIAL_8250_UNIPHIER is not set
-# CONFIG_SERIAL_8250_PXA is not set
-CONFIG_SERIAL_8250_TEGRA=y
-CONFIG_SERIAL_8250_BCM7271=m
-CONFIG_I2C_ALTERA=m
-CONFIG_SERIAL_OF_PLATFORM=m
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_AMBA_PL010 is not set
-# CONFIG_SERIAL_AMBA_PL011 is not set
-CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y
-# CONFIG_SERIAL_ATMEL is not set
-# CONFIG_SERIAL_MESON is not set
-# CONFIG_SERIAL_SAMSUNG is not set
-# CONFIG_SERIAL_SIRFSOC is not set
-CONFIG_SERIAL_MAX3100=m
-CONFIG_SERIAL_MAX310X=y
-# CONFIG_SERIAL_PXA is not set
-# CONFIG_SERIAL_IMX is not set
-CONFIG_SERIAL_IMX_EARLYCON=y
-CONFIG_SERIAL_UARTLITE=m
-CONFIG_SERIAL_UARTLITE_NR_UARTS=1
-# CONFIG_SERIAL_SH_SCI is not set
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_JSM=m
-# CONFIG_SERIAL_MSM is not set
-# CONFIG_SERIAL_VT8500 is not set
-# CONFIG_SERIAL_OMAP is not set
-CONFIG_SERIAL_SIFIVE=m
-CONFIG_SERIAL_SCCNXP=m
-CONFIG_SERIAL_SC16IS7XX_CORE=m
-CONFIG_SERIAL_SC16IS7XX=m
-CONFIG_SERIAL_SC16IS7XX_I2C=y
-CONFIG_SERIAL_SC16IS7XX_SPI=y
-CONFIG_SERIAL_BCM63XX=m
-CONFIG_SERIAL_ALTERA_JTAGUART=m
-CONFIG_SERIAL_ALTERA_UART=m
-CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
-CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
-CONFIG_SERIAL_IFX6X60=m
-CONFIG_SERIAL_XILINX_PS_UART=m
-CONFIG_SERIAL_ARC=m
-CONFIG_SERIAL_ARC_NR_PORTS=1
-CONFIG_SERIAL_RP2=m
-CONFIG_SERIAL_RP2_NR_UARTS=32
-CONFIG_SERIAL_FSL_LPUART=m
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_FSL_LINFLEXUART=m
-CONFIG_SERIAL_CONEXANT_DIGICOLOR=m
-CONFIG_SERIAL_ST_ASC=m
-CONFIG_SERIAL_MEN_Z135=m
-CONFIG_SERIAL_SPRD=m
-# CONFIG_SERIAL_STM32 is not set
-# CONFIG_SERIAL_MVEBU_UART is not set
-# CONFIG_SERIAL_OWL is not set
-# CONFIG_SERIAL_RDA is not set
-CONFIG_SERIAL_MILBEAUT_USIO=y
-CONFIG_SERIAL_MILBEAUT_USIO_PORTS=4
-CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE=y
-CONFIG_SERIAL_LITEUART=m
-CONFIG_SERIAL_LITEUART_MAX_PORTS=1
-# end of Serial drivers
-
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_ROCKETPORT=m
-CONFIG_CYCLADES=m
-CONFIG_CYZ_INTR=y
-CONFIG_MOXA_INTELLIO=m
-CONFIG_MOXA_SMARTIO=m
-CONFIG_SYNCLINKMP=m
-CONFIG_SYNCLINK_GT=m
-CONFIG_ISI=m
-CONFIG_N_HDLC=m
-CONFIG_N_GSM=m
-CONFIG_NOZOMI=m
-CONFIG_NULL_TTY=m
-CONFIG_TRACE_ROUTER=m
-CONFIG_TRACE_SINK=m
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_DCC=y
-CONFIG_SERIAL_DEV_BUS=m
-# CONFIG_TTY_PRINTK is not set
-CONFIG_PRINTER=m
-CONFIG_LP_CONSOLE=y
-CONFIG_PPDEV=m
-CONFIG_VIRTIO_CONSOLE=m
-CONFIG_IPMI_HANDLER=m
-CONFIG_IPMI_PLAT_DATA=y
-CONFIG_IPMI_PANIC_EVENT=y
-CONFIG_IPMI_PANIC_STRING=y
-CONFIG_IPMI_DEVICE_INTERFACE=m
-CONFIG_IPMI_SI=m
-CONFIG_IPMI_SSIF=m
-CONFIG_IPMI_WATCHDOG=m
-CONFIG_IPMI_POWEROFF=m
-CONFIG_NPCM7XX_KCS_IPMI_BMC=m
-CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m
-CONFIG_IPMI_KCS_BMC_SERIO=m
-# CONFIG_ASPEED_KCS_IPMI_BMC is not set
-# CONFIG_ASPEED_BT_IPMI_BMC is not set
-CONFIG_IPMB_DEVICE_INTERFACE=m
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=y
-CONFIG_HW_RANDOM_ATMEL=y
-CONFIG_HW_RANDOM_BA431=y
-CONFIG_HW_RANDOM_OMAP=y
-CONFIG_HW_RANDOM_OMAP3_ROM=y
-# CONFIG_HW_RANDOM_VIRTIO is not set
-CONFIG_HW_RANDOM_HISI=y
-# CONFIG_HW_RANDOM_ST is not set
-CONFIG_HW_RANDOM_STM32=y
-CONFIG_HW_RANDOM_ROCKCHIP=m
-CONFIG_HW_RANDOM_MESON=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_HW_RANDOM_EXYNOS=y
-CONFIG_HW_RANDOM_NPCM=y
-CONFIG_HW_RANDOM_KEYSTONE=y
-# CONFIG_HW_RANDOM_CCTRNG is not set
-CONFIG_HW_RANDOM_XIPHERA=y
-CONFIG_APPLICOM=m
-
-#
-# PCMCIA character devices
-#
-CONFIG_SYNCLINK_CS=m
-CONFIG_CARDMAN_4000=m
-CONFIG_CARDMAN_4040=m
-CONFIG_SCR24X=m
-CONFIG_IPWIRELESS=m
-# end of PCMCIA character devices
-
-CONFIG_DEVMEM=y
-# CONFIG_DEVKMEM is not set
-CONFIG_RAW_DRIVER=m
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_DEVPORT=y
-CONFIG_TCG_TPM=m
-CONFIG_HW_RANDOM_TPM=y
-CONFIG_TCG_TIS_CORE=m
-CONFIG_TCG_TIS=m
-CONFIG_TCG_TIS_SPI=m
-CONFIG_TCG_TIS_SPI_CR50=y
-CONFIG_TCG_TIS_I2C_CR50=m
-CONFIG_TCG_TIS_I2C_ATMEL=m
-CONFIG_TCG_TIS_I2C_INFINEON=m
-CONFIG_TCG_TIS_I2C_NUVOTON=m
-CONFIG_TCG_VTPM_PROXY=m
-CONFIG_TCG_TIS_ST33ZP24=m
-CONFIG_TCG_TIS_ST33ZP24_I2C=m
-CONFIG_TCG_TIS_ST33ZP24_SPI=m
-CONFIG_XILLYBUS=m
-CONFIG_XILLYBUS_PCIE=m
-CONFIG_XILLYBUS_OF=m
-CONFIG_XILLYUSB=m
-# end of Character devices
-
-CONFIG_RANDOM_TRUST_BOOTLOADER=y
-
-#
-# I2C support
-#
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_MUX=m
-
-#
-# Multiplexer I2C Chip support
-#
-# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
-CONFIG_I2C_MUX_GPIO=m
-# CONFIG_I2C_MUX_GPMUX is not set
-CONFIG_I2C_MUX_LTC4306=m
-CONFIG_I2C_MUX_PCA9541=m
-CONFIG_I2C_MUX_PCA954x=m
-# CONFIG_I2C_MUX_PINCTRL is not set
-CONFIG_I2C_MUX_REG=m
-# CONFIG_I2C_DEMUX_PINCTRL is not set
-CONFIG_I2C_MUX_MLXCPLD=m
-# end of Multiplexer I2C Chip support
-
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_SMBUS=m
-CONFIG_I2C_ALGOBIT=m
-CONFIG_I2C_ALGOPCA=m
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# PC SMBus host controller drivers
-#
-CONFIG_I2C_ALI1535=m
-CONFIG_I2C_ALI1563=m
-CONFIG_I2C_ALI15X3=m
-CONFIG_I2C_AMD756=m
-CONFIG_I2C_AMD8111=m
-# CONFIG_I2C_HIX5HD2 is not set
-CONFIG_I2C_I801=m
-CONFIG_I2C_ISCH=m
-CONFIG_I2C_PIIX4=m
-CONFIG_I2C_NFORCE2=m
-CONFIG_I2C_NVIDIA_GPU=m
-CONFIG_I2C_SIS5595=m
-CONFIG_I2C_SIS630=m
-CONFIG_I2C_SIS96X=m
-CONFIG_I2C_VIA=m
-CONFIG_I2C_VIAPRO=m
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_ALTERA is not set
-# CONFIG_I2C_ASPEED is not set
-# CONFIG_I2C_AT91 is not set
-# CONFIG_I2C_CADENCE is not set
-CONFIG_I2C_CBUS_GPIO=m
-# CONFIG_I2C_DAVINCI is not set
-CONFIG_I2C_DESIGNWARE_CORE=m
-# CONFIG_I2C_DESIGNWARE_SLAVE is not set
-CONFIG_I2C_DESIGNWARE_PLATFORM=m
-CONFIG_I2C_DESIGNWARE_AMDPSP=y
-CONFIG_I2C_DESIGNWARE_PCI=m
-# CONFIG_I2C_DIGICOLOR is not set
-CONFIG_I2C_EMEV2=m
-CONFIG_I2C_EXYNOS5=y
-CONFIG_I2C_GPIO=m
-CONFIG_I2C_HISI=m
-# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
-# CONFIG_I2C_IMX is not set
-# CONFIG_I2C_IMX_LPI2C is not set
-CONFIG_I2C_KEMPLD=m
-# CONFIG_I2C_MESON is not set
-# CONFIG_I2C_MT65XX is not set
-# CONFIG_I2C_MV64XXX is not set
-CONFIG_I2C_NOMADIK=y
-CONFIG_I2C_OCORES=m
-CONFIG_I2C_OMAP=y
-# CONFIG_I2C_OWL is not set
-CONFIG_I2C_PCA_PLATFORM=m
-# CONFIG_I2C_PXA is not set
-# CONFIG_I2C_QCOM_CCI is not set
-# CONFIG_I2C_QUP is not set
-# CONFIG_I2C_RIIC is not set
-# CONFIG_I2C_RK3X is not set
-CONFIG_I2C_S3C2410=m
-CONFIG_HAVE_S3C2410_I2C=y
-# CONFIG_I2C_S3C2410 is not set
-# CONFIG_I2C_SH_MOBILE is not set
-CONFIG_I2C_SIMTEC=m
-# CONFIG_I2C_SIRF is not set
-# CONFIG_I2C_ST is not set
-# CONFIG_I2C_STM32F4 is not set
-# CONFIG_I2C_STM32F7 is not set
-# CONFIG_I2C_SUN6I_P2WI is not set
-# CONFIG_I2C_TEGRA is not set
-# CONFIG_I2C_UNIPHIER is not set
-# CONFIG_I2C_UNIPHIER_F is not set
-# CONFIG_I2C_VERSATILE is not set
-# CONFIG_I2C_WMT is not set
-CONFIG_I2C_XILINX=m
-# CONFIG_I2C_XLR is not set
-# CONFIG_I2C_RCAR is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-CONFIG_I2C_DIOLAN_U2C=m
-CONFIG_I2C_CP2615=m
-CONFIG_I2C_DLN2=m
-CONFIG_I2C_PARPORT=m
-CONFIG_I2C_PCI1XXXX=m
-CONFIG_I2C_ROBOTFUZZ_OSIF=m
-CONFIG_I2C_TAOS_EVM=m
-CONFIG_I2C_TINY_USB=m
-CONFIG_I2C_VIPERBOARD=m
-
-#
-# Other I2C/SMBus bus drivers
-#
-CONFIG_I2C_CROS_EC_TUNNEL=m
-CONFIG_I2C_ZX2967=y
-# end of I2C Hardware Bus support
-
-# CONFIG_I2C_STUB is not set
-CONFIG_I2C_SLAVE=y
-CONFIG_I2C_SLAVE_EEPROM=m
-CONFIG_I2C_SLAVE_TESTUNIT=m
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# end of I2C support
-
-CONFIG_I3C=m
-CONFIG_CDNS_I3C_MASTER=m
-CONFIG_DW_I3C_MASTER=m
-CONFIG_SVC_I3C_MASTER=m
-CONFIG_MIPI_I3C_HCI=m
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-
-#
-# SPI Master Controller Drivers
-#
-CONFIG_SPI_ALTERA=m
-CONFIG_SPI_ALTERA_CORE=m
-CONFIG_SPI_ALTERA_DFL=m
-# CONFIG_SPI_ARMADA_3700 is not set
-# CONFIG_SPI_ATMEL is not set
-# CONFIG_SPI_ATMEL_QUADSPI is not set
-CONFIG_SPI_AXI_SPI_ENGINE=m
-# CONFIG_SPI_BCM_QSPI is not set
-CONFIG_SPI_BITBANG=m
-CONFIG_SPI_BUTTERFLY=m
-CONFIG_SPI_CADENCE=m
-CONFIG_SPI_CADENCE_QUADSPI=m
-# CONFIG_SPI_DAVINCI is not set
-CONFIG_SPI_DESIGNWARE=m
-# CONFIG_SPI_DW_DMA is not set
-CONFIG_SPI_DW_PCI=m
-CONFIG_SPI_DW_MMIO=m
-CONFIG_SPI_DLN2=m
-# CONFIG_SPI_FSL_LPSPI is not set
-# CONFIG_SPI_FSL_QUADSPI is not set
-CONFIG_SPI_HISI_KUNPENG=m
-CONFIG_SPI_NXP_FLEXSPI=m
-CONFIG_SPI_GPIO=m
-# CONFIG_SPI_IMX is not set
-CONFIG_SPI_LM70_LLP=m
-# CONFIG_SPI_FSL_SPI is not set
-# CONFIG_SPI_MESON_SPICC is not set
-# CONFIG_SPI_MESON_SPIFC is not set
-# CONFIG_SPI_MT65XX is not set
-# CONFIG_SPI_MTK_NOR is not set
-# CONFIG_SPI_NPCM_FIU is not set
-# CONFIG_SPI_NPCM_PSPI is not set
-CONFIG_SPI_OC_TINY=m
-# CONFIG_SPI_OMAP24XX is not set
-# CONFIG_SPI_TI_QSPI is not set
-# CONFIG_SPI_ORION is not set
-CONFIG_SPI_PL022=y
-CONFIG_SPI_PXA2XX=m
-CONFIG_SPI_PXA2XX_PCI=m
-CONFIG_SPI_ROCKCHIP=m
-CONFIG_SPI_RPCIF=m
-# CONFIG_SPI_RSPI is not set
-# CONFIG_SPI_QCOM_QSPI is not set
-# CONFIG_SPI_QUP is not set
-# CONFIG_SPI_S3C64XX is not set
-CONFIG_SPI_SC18IS602=m
-# CONFIG_SPI_SH_MSIOF is not set
-# CONFIG_SPI_SH_HSPI is not set
-CONFIG_SPI_SIFIVE=m
-# CONFIG_SPI_SLAVE_MT27XX is not set
-# CONFIG_SPI_STM32 is not set
-# CONFIG_SPI_STM32_QSPI is not set
-# CONFIG_SPI_ST_SSC4 is not set
-# CONFIG_SPI_SUN4I is not set
-# CONFIG_SPI_SUN6I is not set
-CONFIG_SPI_MXIC=m
-CONFIG_SPI_TEGRA210_QUAD=m
-# CONFIG_SPI_TEGRA20_SFLASH is not set
-# CONFIG_SPI_UNIPHIER is not set
-CONFIG_SPI_XCOMM=m
-CONFIG_SPI_XILINX=m
-# CONFIG_SPI_ZYNQ_QSPI is not set
-CONFIG_SPI_ZYNQMP_GQSPI=m
-CONFIG_SPI_AMD=m
-
-#
-# SPI Multiplexer support
-#
-CONFIG_SPI_MUX=m
-
-#
-# SPI Protocol Masters
-#
-CONFIG_SPI_SPIDEV=m
-CONFIG_SPI_LOOPBACK_TEST=m
-CONFIG_SPI_TLE62X0=m
-CONFIG_SPI_SLAVE=y
-CONFIG_SPI_SLAVE_TIME=m
-CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPMI=m
-CONFIG_SPMI_MSM_PMIC_ARB=m
-CONFIG_HSI=m
-CONFIG_HSI_BOARDINFO=y
-
-#
-# HSI controllers
-#
-# CONFIG_OMAP_SSI is not set
-
-#
-# HSI clients
-#
-CONFIG_HSI_CHAR=m
-CONFIG_PPS=y
-# CONFIG_PPS_DEBUG is not set
-
-#
-# PPS clients support
-#
-# CONFIG_PPS_CLIENT_KTIMER is not set
-CONFIG_PPS_CLIENT_LDISC=m
-CONFIG_PPS_CLIENT_PARPORT=m
-CONFIG_PPS_CLIENT_GPIO=m
-
-#
-# PPS generators support
-#
-
-#
-# PTP clock support
-#
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_DP83640_PHY=m
-CONFIG_PTP_1588_CLOCK_INES=m
-CONFIG_PTP_1588_CLOCK_KVM=m
-CONFIG_PTP_1588_CLOCK_IDT82P33=m
-CONFIG_PTP_1588_CLOCK_IDTCM=m
-CONFIG_PTP_1588_CLOCK_OCP=m
-# end of PTP clock support
-
-CONFIG_PINCTRL=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_PINMUX=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_PINCONF=y
-CONFIG_GENERIC_PINCONF=y
-# CONFIG_DEBUG_PINCTRL is not set
-CONFIG_PINCTRL_AXP209=m
-CONFIG_PINCTRL_CY8C95X0=m
-# CONFIG_PINCTRL_AT91 is not set
-# CONFIG_PINCTRL_AT91PIO4 is not set
-CONFIG_PINCTRL_DA9062=m
-CONFIG_PINCTRL_DIGICOLOR=y
-CONFIG_PINCTRL_MCP23S08_I2C=m
-CONFIG_PINCTRL_MCP23S08_SPI=m
-CONFIG_PINCTRL_MCP23S08=m
-CONFIG_PINCTRL_ROCKCHIP=y
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_PINCTRL_SIRF=y
-# CONFIG_PINCTRL_SX150X is not set
-CONFIG_PINCTRL_ST=y
-CONFIG_PINCTRL_STMFX=m
-CONFIG_PINCTRL_ZYNQ=y
-# CONFIG_PINCTRL_RK805 is not set
-# CONFIG_PINCTRL_OCELOT is not set
-CONFIG_PINCTRL_MICROCHIP_SGPIO=y
-# CONFIG_PINCTRL_OWL is not set
-CONFIG_PINCTRL_BCM4908=m
-# CONFIG_PINCTRL_AS370 is not set
-# CONFIG_PINCTRL_BERLIN_BG4CT is not set
-# CONFIG_PINCTRL_IMX8MM is not set
-# CONFIG_PINCTRL_IMX8MN is not set
-# CONFIG_PINCTRL_IMX8MP is not set
-# CONFIG_PINCTRL_IMX8MQ is not set
-CONFIG_PINCTRL_ABX500=y
-CONFIG_PINCTRL_AB8500=y
-CONFIG_PINCTRL_AB8505=y
-CONFIG_PINCTRL_NOMADIK=y
-CONFIG_PINCTRL_DB8500=y
-CONFIG_PINCTRL_MSM=y
-# CONFIG_PINCTRL_APQ8064 is not set
-# CONFIG_PINCTRL_APQ8084 is not set
-# CONFIG_PINCTRL_IPQ4019 is not set
-# CONFIG_PINCTRL_IPQ8064 is not set
-# CONFIG_PINCTRL_IPQ8074 is not set
-# CONFIG_PINCTRL_IPQ6018 is not set
-CONFIG_PINCTRL_MSM8226=m
-# CONFIG_PINCTRL_MSM8660 is not set
-# CONFIG_PINCTRL_MSM8960 is not set
-# CONFIG_PINCTRL_MDM9615 is not set
-# CONFIG_PINCTRL_MSM8X74 is not set
-# CONFIG_PINCTRL_MSM8916 is not set
-CONFIG_PINCTRL_MSM8953=m
-# CONFIG_PINCTRL_MSM8976 is not set
-# CONFIG_PINCTRL_MSM8994 is not set
-# CONFIG_PINCTRL_MSM8996 is not set
-# CONFIG_PINCTRL_MSM8998 is not set
-# CONFIG_PINCTRL_QCS404 is not set
-# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
-# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
-# CONFIG_PINCTRL_SC7180 is not set
-CONFIG_PINCTRL_SC7280=m
-CONFIG_PINCTRL_SC8180X=m
-CONFIG_PINCTRL_SC8280XP=m
-# CONFIG_PINCTRL_SDM660 is not set
-# CONFIG_PINCTRL_SDM845 is not set
-CONFIG_PINCTRL_SDX55=m
-CONFIG_PINCTRL_SM6125=m
-# CONFIG_PINCTRL_SM8150 is not set
-# CONFIG_PINCTRL_SM8250 is not set
-CONFIG_PINCTRL_SM8350=m
-CONFIG_PINCTRL_LPASS_LPI=m
-
-#
-# Renesas pinctrl drivers
-#
-CONFIG_PINCTRL_RENESAS=y
-# end of Renesas pinctrl drivers
-
-CONFIG_PINCTRL_SAMSUNG=y
-CONFIG_PINCTRL_EXYNOS=y
-CONFIG_PINCTRL_EXYNOS_ARM=y
-CONFIG_PINCTRL_SPEAR=y
-CONFIG_PINCTRL_SPEAR1310=y
-CONFIG_PINCTRL_SPEAR1340=y
-CONFIG_PINCTRL_SPEAR_PLGPIO=y
-CONFIG_PINCTRL_STM32=y
-CONFIG_PINCTRL_STM32MP157=y
-CONFIG_PINCTRL_SUNXI=y
-CONFIG_PINCTRL_SUN4I_A10=y
-CONFIG_PINCTRL_SUN5I=y
-CONFIG_PINCTRL_SUN6I_A31=y
-CONFIG_PINCTRL_SUN6I_A31_R=y
-CONFIG_PINCTRL_SUN8I_A23=y
-CONFIG_PINCTRL_SUN8I_A33=y
-CONFIG_PINCTRL_SUN8I_A83T=y
-CONFIG_PINCTRL_SUN8I_A83T_R=y
-CONFIG_PINCTRL_SUN8I_A23_R=y
-CONFIG_PINCTRL_SUN8I_H3=y
-CONFIG_PINCTRL_SUN8I_H3_R=y
-CONFIG_PINCTRL_SUN8I_V3S=y
-CONFIG_PINCTRL_SUN9I_A80=y
-CONFIG_PINCTRL_SUN9I_A80_R=y
-# CONFIG_PINCTRL_SUN50I_A64 is not set
-# CONFIG_PINCTRL_SUN50I_A64_R is not set
-CONFIG_PINCTRL_SUN50I_A100=y
-CONFIG_PINCTRL_SUN50I_A100_R=y
-# CONFIG_PINCTRL_SUN50I_H5 is not set
-# CONFIG_PINCTRL_SUN50I_H6 is not set
-# CONFIG_PINCTRL_SUN50I_H6_R is not set
-CONFIG_PINCTRL_SUN50I_H616=y
-CONFIG_PINCTRL_SUN50I_H616_R=y
-CONFIG_PINCTRL_TEGRA_XUSB=y
-CONFIG_PINCTRL_TI_IODELAY=y
-CONFIG_PINCTRL_UNIPHIER=y
-CONFIG_PINCTRL_UNIPHIER_LD4=y
-CONFIG_PINCTRL_UNIPHIER_PRO4=y
-CONFIG_PINCTRL_UNIPHIER_SLD8=y
-CONFIG_PINCTRL_UNIPHIER_PRO5=y
-CONFIG_PINCTRL_UNIPHIER_PXS2=y
-CONFIG_PINCTRL_UNIPHIER_LD6B=y
-# CONFIG_PINCTRL_UNIPHIER_LD11 is not set
-# CONFIG_PINCTRL_UNIPHIER_LD20 is not set
-# CONFIG_PINCTRL_UNIPHIER_PXS3 is not set
-# CONFIG_PINCTRL_WM8850 is not set
-
-#
-# MediaTek pinctrl drivers
-#
-CONFIG_EINT_MTK=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MT2701=y
-CONFIG_PINCTRL_MT7623=y
-CONFIG_PINCTRL_MT7629=y
-CONFIG_PINCTRL_MT8135=y
-CONFIG_PINCTRL_MT8127=y
-CONFIG_PINCTRL_MT6397=y
-# end of MediaTek pinctrl drivers
-
-# CONFIG_PINCTRL_ZX296718 is not set
-CONFIG_PINCTRL_MESON=y
-CONFIG_PINCTRL_MESON8=y
-CONFIG_PINCTRL_MESON8B=y
-CONFIG_PINCTRL_MESON8_PMX=y
-CONFIG_PINCTRL_MADERA=m
-CONFIG_PINCTRL_CS47L15=y
-CONFIG_PINCTRL_CS47L35=y
-CONFIG_PINCTRL_CS47L85=y
-CONFIG_PINCTRL_CS47L90=y
-CONFIG_PINCTRL_CS47L92=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_FASTPATH_LIMIT=512
-CONFIG_OF_GPIO=y
-CONFIG_GPIOLIB_IRQCHIP=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_CDEV_V1=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_REGMAP=m
-CONFIG_GPIO_MAX730X=m
-
-#
-# Memory mapped GPIO drivers
-#
-CONFIG_GPIO_74XX_MMIO=m
-CONFIG_GPIO_ALTERA=m
-CONFIG_GPIO_ALTERA_A10SR=m
-# CONFIG_GPIO_ASPEED is not set
-# CONFIG_GPIO_ASPEED_SGPIO is not set
-CONFIG_GPIO_CADENCE=m
-# CONFIG_GPIO_DAVINCI is not set
-CONFIG_GPIO_DWAPB=m
-CONFIG_GPIO_EXAR=m
-CONFIG_GPIO_FTGPIO010=y
-CONFIG_GPIO_GENERIC_PLATFORM=m
-CONFIG_GPIO_GRGPIO=m
-CONFIG_GPIO_HLWD=m
-CONFIG_GPIO_LOGICVC=m
-CONFIG_GPIO_MB86S7X=m
-CONFIG_GPIO_MENZ127=m
-CONFIG_GPIO_MPC8XXX=y
-CONFIG_GPIO_MVEBU=y
-CONFIG_GPIO_MXC=y
-CONFIG_GPIO_OMAP=y
-CONFIG_GPIO_PL061=y
-CONFIG_GPIO_PXA=y
-# CONFIG_GPIO_RCAR is not set
-# CONFIG_GPIO_RDA is not set
-CONFIG_GPIO_SAMA5D2_PIOBU=m
-CONFIG_GPIO_SIFIVE=y
-CONFIG_GPIO_SIOX=m
-CONFIG_GPIO_SPEAR_SPICS=y
-CONFIG_GPIO_SYSCON=m
-CONFIG_GPIO_TEGRA=y
-# CONFIG_GPIO_UNIPHIER is not set
-CONFIG_GPIO_VISCONTI=m
-CONFIG_GPIO_WCD934X=m
-CONFIG_GPIO_XILINX=m
-CONFIG_GPIO_ZEVIO=y
-# CONFIG_GPIO_ZYNQ is not set
-# CONFIG_GPIO_ZX is not set
-CONFIG_GPIO_AMD_FCH=m
-CONFIG_GPIO_MSC313=y
-# end of Memory mapped GPIO drivers
-
-#
-# I2C GPIO expanders
-#
-CONFIG_GPIO_ADP5588=m
-CONFIG_GPIO_ADNP=m
-CONFIG_GPIO_GW_PLD=m
-CONFIG_GPIO_MAX7300=m
-CONFIG_GPIO_MAX732X=m
-CONFIG_GPIO_PCA953X=m
-# CONFIG_GPIO_PCA953X_IRQ is not set
-CONFIG_GPIO_PCA9570=m
-CONFIG_GPIO_PCF857X=m
-CONFIG_GPIO_TPIC2810=m
-# end of I2C GPIO expanders
-
-#
-# MFD GPIO expanders
-#
-CONFIG_GPIO_ARIZONA=m
-CONFIG_GPIO_BD9571MWV=m
-CONFIG_GPIO_DA9052=m
-CONFIG_GPIO_DLN2=m
-CONFIG_HTC_EGPIO=y
-CONFIG_GPIO_JANZ_TTL=m
-CONFIG_GPIO_KEMPLD=m
-CONFIG_GPIO_LP3943=m
-CONFIG_GPIO_LP873X=m
-# CONFIG_GPIO_LP87565 is not set
-CONFIG_GPIO_MADERA=m
-# CONFIG_GPIO_MAX77650 is not set
-CONFIG_GPIO_SL28CPLD=m
-# CONFIG_GPIO_STMPE is not set
-CONFIG_GPIO_TPS65086=m
-# CONFIG_GPIO_TPS65218 is not set
-CONFIG_GPIO_TPS65912=m
-CONFIG_GPIO_TPS68470=y
-CONFIG_GPIO_TQMX86=m
-# CONFIG_GPIO_TWL4030 is not set
-CONFIG_GPIO_UCB1400=m
-CONFIG_GPIO_WM831X=m
-CONFIG_GPIO_WM8994=m
-# end of MFD GPIO expanders
-
-#
-# PCI GPIO expanders
-#
-CONFIG_GPIO_PCI_IDIO_16=m
-CONFIG_GPIO_PCIE_IDIO_24=m
-CONFIG_GPIO_RDC321X=m
-# end of PCI GPIO expanders
-
-#
-# SPI GPIO expanders
-#
-# CONFIG_GPIO_74X164 is not set
-CONFIG_GPIO_MAX3191X=m
-CONFIG_GPIO_MAX7301=m
-CONFIG_GPIO_MC33880=m
-CONFIG_GPIO_PISOSR=m
-CONFIG_GPIO_XRA1403=m
-CONFIG_GPIO_MOXTET=m
-# end of SPI GPIO expanders
-
-#
-# USB GPIO expanders
-#
-CONFIG_GPIO_VIPERBOARD=m
-# end of USB GPIO expanders
-
-CONFIG_GPIO_AGGREGATOR=m
-CONFIG_GPIO_MOCKUP=m
-CONFIG_W1=m
-CONFIG_W1_CON=y
-
-#
-# 1-wire Bus Masters
-#
-# CONFIG_W1_MASTER_MATROX is not set
-CONFIG_W1_MASTER_DS2490=m
-CONFIG_W1_MASTER_DS2482=m
-# CONFIG_W1_MASTER_MXC is not set
-CONFIG_W1_MASTER_DS1WM=m
-CONFIG_W1_MASTER_GPIO=m
-# CONFIG_HDQ_MASTER_OMAP is not set
-CONFIG_W1_MASTER_SGI=m
-# end of 1-wire Bus Masters
-
-#
-# 1-wire Slaves
-#
-CONFIG_W1_SLAVE_THERM=m
-CONFIG_W1_SLAVE_SMEM=m
-CONFIG_W1_SLAVE_DS2405=m
-CONFIG_W1_SLAVE_DS2408=m
-CONFIG_W1_SLAVE_DS2408_READBACK=y
-CONFIG_W1_SLAVE_DS2413=m
-CONFIG_W1_SLAVE_DS2406=m
-CONFIG_W1_SLAVE_DS2423=m
-CONFIG_W1_SLAVE_DS2805=m
-CONFIG_W1_SLAVE_DS2430=m
-CONFIG_W1_SLAVE_DS2431=m
-CONFIG_W1_SLAVE_DS2433=m
-# CONFIG_W1_SLAVE_DS2433_CRC is not set
-CONFIG_W1_SLAVE_DS2438=m
-CONFIG_W1_SLAVE_DS250X=m
-CONFIG_W1_SLAVE_DS2780=m
-CONFIG_W1_SLAVE_DS2781=m
-CONFIG_W1_SLAVE_DS28E04=m
-CONFIG_W1_SLAVE_DS28E17=m
-# end of 1-wire Slaves
-
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_AT91_POWEROFF is not set
-CONFIG_POWER_RESET_ATC260X=m
-# CONFIG_POWER_RESET_AT91_RESET is not set
-# CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC is not set
-CONFIG_POWER_RESET_BRCMKONA=y
-CONFIG_POWER_RESET_BRCMSTB=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_POWER_RESET_GPIO_RESTART=y
-CONFIG_POWER_RESET_HISI=y
-CONFIG_POWER_RESET_LINKSTATION=m
-# CONFIG_POWER_RESET_MSM is not set
-CONFIG_POWER_RESET_LTC2952=y
-CONFIG_POWER_RESET_MT6323=y
-# CONFIG_POWER_RESET_QNAP is not set
-CONFIG_POWER_RESET_RESTART=y
-# CONFIG_POWER_RESET_ST is not set
-CONFIG_POWER_RESET_VERSATILE=y
-CONFIG_POWER_RESET_VEXPRESS=y
-# CONFIG_POWER_RESET_KEYSTONE is not set
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-# CONFIG_POWER_RESET_ZX is not set
-CONFIG_POWER_RESET_REGULATOR=y
-CONFIG_REBOOT_MODE=m
-CONFIG_SYSCON_REBOOT_MODE=m
-CONFIG_NVMEM_REBOOT_MODE=m
-CONFIG_POWER_MLXBF=m
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PDA_POWER=m
-CONFIG_GENERIC_ADC_BATTERY=m
-CONFIG_IP5XXX_POWER=m
-CONFIG_WM831X_BACKUP=m
-CONFIG_WM831X_POWER=m
-# CONFIG_TEST_POWER is not set
-CONFIG_CHARGER_ADP5061=m
-# CONFIG_BATTERY_ACT8945A is not set
-CONFIG_BATTERY_CPCAP=m
-CONFIG_BATTERY_CW2015=m
-CONFIG_BATTERY_DS2760=m
-CONFIG_BATTERY_DS2780=m
-CONFIG_BATTERY_DS2781=m
-CONFIG_BATTERY_DS2782=m
-CONFIG_BATTERY_SAMSUNG_SDI=y
-CONFIG_BATTERY_SBS=m
-CONFIG_CHARGER_SBS=m
-CONFIG_MANAGER_SBS=m
-CONFIG_BATTERY_BQ27XXX=m
-CONFIG_BATTERY_BQ27XXX_I2C=m
-CONFIG_BATTERY_BQ27XXX_HDQ=m
-CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM=y
-CONFIG_BATTERY_DA9052=m
-CONFIG_CHARGER_DA9150=m
-CONFIG_BATTERY_DA9150=m
-CONFIG_CHARGER_AXP20X=m
-CONFIG_BATTERY_AXP20X=m
-CONFIG_AXP20X_POWER=m
-CONFIG_AXP288_FUEL_GAUGE=m
-CONFIG_BATTERY_MAX17040=m
-CONFIG_BATTERY_MAX17042=m
-CONFIG_BATTERY_MAX1721X=m
-CONFIG_CHARGER_PCF50633=m
-CONFIG_CHARGER_ISP1704=m
-CONFIG_CHARGER_MAX8903=m
-# CONFIG_CHARGER_TWL4030 is not set
-CONFIG_CHARGER_LP8727=m
-CONFIG_CHARGER_GPIO=m
-CONFIG_CHARGER_MANAGER=y
-CONFIG_CHARGER_LT3651=m
-CONFIG_CHARGER_LTC4162L=m
-CONFIG_CHARGER_MAX14577=m
-# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
-# CONFIG_CHARGER_MAX77650 is not set
-CONFIG_CHARGER_MAX77693=m
-CONFIG_CHARGER_MP2629=m
-CONFIG_CHARGER_BQ2415X=m
-CONFIG_CHARGER_BQ24190=m
-CONFIG_CHARGER_BQ24257=m
-CONFIG_CHARGER_BQ24735=m
-CONFIG_CHARGER_BQ2515X=m
-CONFIG_CHARGER_BQ25890=m
-CONFIG_CHARGER_BQ25980=m
-CONFIG_CHARGER_BQ256XX=m
-CONFIG_CHARGER_RK817=m
-CONFIG_CHARGER_SMB347=m
-# CONFIG_CHARGER_TPS65217 is not set
-CONFIG_BATTERY_GAUGE_LTC2941=m
-CONFIG_BATTERY_GOLDFISH=m
-CONFIG_BATTERY_RT5033=m
-CONFIG_CHARGER_RT9455=m
-CONFIG_CHARGER_CROS_USBPD=m
-CONFIG_CHARGER_UCS1002=m
-CONFIG_CHARGER_BD99954=m
-CONFIG_BATTERY_UG3105=m
-CONFIG_CHARGER_SURFACE=m
-CONFIG_BATTERY_SURFACE=m
-CONFIG_SURFACE_HID=m
-CONFIG_RN5T618_POWER=m
-CONFIG_HWMON=y
-CONFIG_HWMON_VID=m
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Native drivers
-#
-CONFIG_SENSORS_AD7314=m
-CONFIG_SENSORS_AD7414=m
-CONFIG_SENSORS_AD7418=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1026=m
-CONFIG_SENSORS_ADM1029=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_ADM1177=m
-CONFIG_SENSORS_ADM9240=m
-CONFIG_SENSORS_ADT7X10=m
-CONFIG_SENSORS_ADT7310=m
-CONFIG_SENSORS_ADT7410=m
-CONFIG_SENSORS_ADT7411=m
-CONFIG_SENSORS_ADT7462=m
-CONFIG_SENSORS_ADT7470=m
-CONFIG_SENSORS_ADT7475=m
-CONFIG_SENSORS_AHT10=m
-CONFIG_SENSORS_AS370=m
-CONFIG_SENSORS_ASC7621=m
-CONFIG_SENSORS_AXI_FAN_CONTROL=m
-CONFIG_SENSORS_ARM_SCMI=m
-CONFIG_SENSORS_ARM_SCPI=m
-CONFIG_SENSORS_ASPEED=m
-CONFIG_SENSORS_ATXP1=m
-CONFIG_SENSORS_CORSAIR_CPRO=m
-CONFIG_SENSORS_CORSAIR_PSU=m
-CONFIG_SENSORS_DRIVETEMP=m
-CONFIG_SENSORS_DS620=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_DA9052_ADC=m
-CONFIG_SENSORS_I5K_AMB=m
-CONFIG_SENSORS_F71805F=m
-CONFIG_SENSORS_F71882FG=m
-CONFIG_SENSORS_F75375S=m
-# CONFIG_SENSORS_GSC is not set
-CONFIG_SENSORS_MC13783_ADC=m
-CONFIG_SENSORS_FTSTEUTATES=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_GL520SM=m
-CONFIG_SENSORS_G760A=m
-CONFIG_SENSORS_G762=m
-CONFIG_SENSORS_GPIO_FAN=m
-CONFIG_SENSORS_HIH6130=m
-CONFIG_SENSORS_IBMAEM=m
-CONFIG_SENSORS_IBMPEX=m
-CONFIG_SENSORS_IIO_HWMON=m
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_JC42=m
-CONFIG_SENSORS_POWR1220=m
-CONFIG_SENSORS_LINEAGE=m
-CONFIG_SENSORS_LTC2945=m
-CONFIG_SENSORS_LTC2947=m
-CONFIG_SENSORS_LTC2947_I2C=m
-CONFIG_SENSORS_LTC2947_SPI=m
-CONFIG_SENSORS_LTC2990=m
-CONFIG_SENSORS_LTC2992=m
-CONFIG_SENSORS_LTC4151=m
-CONFIG_SENSORS_LTC4215=m
-CONFIG_SENSORS_LTC4222=m
-CONFIG_SENSORS_LTC4245=m
-CONFIG_SENSORS_LTC4260=m
-CONFIG_SENSORS_LTC4261=m
-CONFIG_SENSORS_MAX1111=m
-CONFIG_SENSORS_MAX127=m
-CONFIG_SENSORS_MAX16065=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_MAX1668=m
-CONFIG_SENSORS_MAX197=m
-CONFIG_SENSORS_MAX31722=m
-CONFIG_SENSORS_MAX31730=m
-CONFIG_SENSORS_MAX31760=m
-CONFIG_SENSORS_MAX6621=m
-CONFIG_SENSORS_MAX6639=m
-CONFIG_SENSORS_MAX6642=m
-CONFIG_SENSORS_MAX6650=m
-CONFIG_SENSORS_MAX6697=m
-CONFIG_SENSORS_MAX31790=m
-CONFIG_SENSORS_PM6764TR=m
-CONFIG_SENSORS_Q54SJ108A2=m
-CONFIG_SENSORS_STPDDC60=m
-CONFIG_SENSORS_MCP3021=m
-CONFIG_SENSORS_MLXREG_FAN=m
-CONFIG_SENSORS_TC654=m
-CONFIG_SENSORS_TPS23861=m
-CONFIG_SENSORS_MENF21BMC_HWMON=m
-CONFIG_SENSORS_MR75203=m
-CONFIG_SENSORS_ADCXX=m
-CONFIG_SENSORS_LM63=m
-CONFIG_SENSORS_LM70=m
-CONFIG_SENSORS_LM73=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM87=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_LM92=m
-CONFIG_SENSORS_LM93=m
-CONFIG_SENSORS_LM95234=m
-CONFIG_SENSORS_LM95241=m
-CONFIG_SENSORS_LM95245=m
-CONFIG_SENSORS_PC87360=m
-CONFIG_SENSORS_PC87427=m
-CONFIG_SENSORS_NTC_THERMISTOR=m
-CONFIG_SENSORS_NCT6683=m
-CONFIG_SENSORS_NCT6775=m
-CONFIG_SENSORS_NCT7802=m
-CONFIG_SENSORS_NCT7904=m
-CONFIG_SENSORS_NPCM7XX=m
-CONFIG_SENSORS_NZXT_KRAKEN2=m
-CONFIG_SENSORS_BPA_RS600=m
-CONFIG_SENSORS_FSP_3Y=m
-# CONFIG_SENSORS_OCC_P8_I2C is not set
-CONFIG_SENSORS_PCF8591=m
-CONFIG_PMBUS=m
-CONFIG_SENSORS_PMBUS=m
-CONFIG_SENSORS_ADM1266=m
-CONFIG_SENSORS_ADM1275=m
-CONFIG_SENSORS_BEL_PFE=m
-CONFIG_SENSORS_IBM_CFFPS=m
-CONFIG_SENSORS_DPS920AB=m
-CONFIG_SENSORS_INSPUR_IPSPS=m
-CONFIG_SENSORS_IR35221=m
-CONFIG_SENSORS_IR36021=m
-CONFIG_SENSORS_IR38064=m
-CONFIG_SENSORS_IRPS5401=m
-CONFIG_SENSORS_ISL68137=m
-CONFIG_SENSORS_LM25066=m
-CONFIG_SENSORS_LM25066_REGULATOR=y
-CONFIG_SENSORS_LTC2978=m
-CONFIG_SENSORS_LTC2978_REGULATOR=y
-CONFIG_SENSORS_LTC3815=m
-CONFIG_SENSORS_MAX15301=m
-CONFIG_SENSORS_MAX16064=m
-CONFIG_SENSORS_MAX16601=m
-CONFIG_SENSORS_MAX20730=m
-CONFIG_SENSORS_MAX20751=m
-CONFIG_SENSORS_MAX31785=m
-CONFIG_SENSORS_MAX34440=m
-CONFIG_SENSORS_MAX8688=m
-CONFIG_SENSORS_MP2888=m
-CONFIG_SENSORS_MP2975=m
-CONFIG_SENSORS_PIM4328=m
-CONFIG_SENSORS_PLI1209BC_REGULATOR=y
-CONFIG_SENSORS_PLI1209BC=m
-CONFIG_SENSORS_PXE1610=m
-CONFIG_SENSORS_TPS40422=m
-CONFIG_SENSORS_TPS53679=m
-CONFIG_SENSORS_TPS546D24=m
-CONFIG_SENSORS_UCD9000=m
-CONFIG_SENSORS_UCD9200=m
-CONFIG_SENSORS_XDPE122=m
-CONFIG_SENSORS_XDPE122_REGULATOR=y
-CONFIG_SENSORS_ZL6100=m
-CONFIG_SENSORS_PWM_FAN=m
-CONFIG_SENSORS_SL28CPLD=m
-# CONFIG_SENSORS_SBTSI is not set
-# CONFIG_AMD_SFH_HID is not set
-CONFIG_SENSORS_SHT15=m
-CONFIG_SENSORS_SHT21=m
-CONFIG_SENSORS_SHT3x=m
-CONFIG_SENSORS_SHT4x=m
-CONFIG_SENSORS_SHTC1=m
-CONFIG_SENSORS_SIS5595=m
-CONFIG_SENSORS_SY7636A=m
-CONFIG_SENSORS_DME1737=m
-CONFIG_SENSORS_EMC1403=m
-CONFIG_SENSORS_EMC2103=m
-CONFIG_SENSORS_EMC2305=m
-CONFIG_SENSORS_EMC6W201=m
-CONFIG_SENSORS_SMSC47M1=m
-CONFIG_SENSORS_SMSC47M192=m
-CONFIG_SENSORS_SMSC47B397=m
-CONFIG_SENSORS_SCH56XX_COMMON=m
-CONFIG_SENSORS_SCH5627=m
-CONFIG_SENSORS_SCH5636=m
-CONFIG_SENSORS_STTS751=m
-CONFIG_SENSORS_SMM665=m
-CONFIG_SENSORS_ADC128D818=m
-CONFIG_SENSORS_ADS7828=m
-CONFIG_SENSORS_ADS7871=m
-CONFIG_SENSORS_AMC6821=m
-CONFIG_SENSORS_INA209=m
-CONFIG_SENSORS_INA2XX=m
-CONFIG_SENSORS_INA3221=m
-CONFIG_SENSORS_TC74=m
-CONFIG_SENSORS_THMC50=m
-CONFIG_SENSORS_TMP102=m
-CONFIG_SENSORS_TMP103=m
-CONFIG_SENSORS_TMP108=m
-CONFIG_SENSORS_TMP401=m
-CONFIG_SENSORS_TMP421=m
-CONFIG_SENSORS_TMP464=m
-CONFIG_SENSORS_TMP513=m
-CONFIG_SENSORS_VEXPRESS=m
-CONFIG_SENSORS_VIA686A=m
-CONFIG_SENSORS_VT1211=m
-CONFIG_SENSORS_VT8231=m
-CONFIG_SENSORS_W83773G=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83791D=m
-CONFIG_SENSORS_W83792D=m
-CONFIG_SENSORS_W83793=m
-CONFIG_SENSORS_W83795=m
-CONFIG_SENSORS_W83795_FANCTRL=y
-CONFIG_SENSORS_W83L785TS=m
-CONFIG_SENSORS_W83L786NG=m
-CONFIG_SENSORS_W83627HF=m
-CONFIG_SENSORS_W83627EHF=m
-CONFIG_SENSORS_WM831X=m
-CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m
-CONFIG_QCOM_SPMI_ADC_TM5=m
-CONFIG_THERMAL=y
-CONFIG_THERMAL_NETLINK=y
-CONFIG_THERMAL_STATISTICS=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=100
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
-# CONFIG_CPU_THERMAL is not set
-CONFIG_DEVFREQ_THERMAL=y
-# CONFIG_THERMAL_EMULATION is not set
-CONFIG_THERMAL_MMIO=m
-CONFIG_HISI_THERMAL=y
-# CONFIG_IMX_THERMAL is not set
-# CONFIG_IMX8MM_THERMAL is not set
-# CONFIG_SPEAR_THERMAL is not set
-# CONFIG_SUN8I_THERMAL is not set
-# CONFIG_ROCKCHIP_THERMAL is not set
-# CONFIG_RCAR_THERMAL is not set
-# CONFIG_RCAR_GEN3_THERMAL is not set
-CONFIG_DB8500_THERMAL=y
-# CONFIG_ARMADA_THERMAL is not set
-CONFIG_DA9062_THERMAL=m
-CONFIG_MTK_THERMAL=y
-CONFIG_AMLOGIC_THERMAL=y
-
-#
-# Broadcom thermal drivers
-#
-# end of Broadcom thermal drivers
-
-#
-# Texas Instruments thermal drivers
-#
-CONFIG_TI_SOC_THERMAL=m
-# CONFIG_TI_THERMAL is not set
-# CONFIG_OMAP3_THERMAL is not set
-# CONFIG_OMAP4_THERMAL is not set
-# CONFIG_OMAP5_THERMAL is not set
-# CONFIG_DRA752_THERMAL is not set
-# end of Texas Instruments thermal drivers
-
-#
-# Samsung thermal drivers
-#
-CONFIG_EXYNOS_THERMAL=y
-# end of Samsung thermal drivers
-
-#
-# STMicroelectronics thermal drivers
-#
-# CONFIG_ST_THERMAL is not set
-# CONFIG_ST_THERMAL_SYSCFG is not set
-# CONFIG_ST_THERMAL_MEMMAP is not set
-CONFIG_STM32_THERMAL=y
-# end of STMicroelectronics thermal drivers
-
-# CONFIG_TANGO_THERMAL is not set
-
-#
-# NVIDIA Tegra thermal drivers
-#
-# CONFIG_TEGRA_SOCTHERM is not set
-# end of NVIDIA Tegra thermal drivers
-
-CONFIG_GENERIC_ADC_THERMAL=m
-
-#
-# Qualcomm thermal drivers
-#
-# CONFIG_QCOM_SPMI_TEMP_ALARM is not set
-# end of Qualcomm thermal drivers
-
-# CONFIG_ZX2967_THERMAL is not set
-# CONFIG_UNIPHIER_THERMAL is not set
-CONFIG_KHADAS_MCU_FAN_THERMAL=m
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_CORE=m
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
-CONFIG_WATCHDOG_OPEN_TIMEOUT=0
-# CONFIG_WATCHDOG_SYSFS is not set
-# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
-
-#
-# Watchdog Pretimeout Governors
-#
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-
-#
-# Watchdog Device Drivers
-#
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_BD957XMUF_WATCHDOG=m
-# CONFIG_SOFT_WATCHDOG_PRETIMEOUT is not set
-CONFIG_DA9052_WATCHDOG=m
-CONFIG_DA9063_WATCHDOG=m
-CONFIG_DA9062_WATCHDOG=m
-CONFIG_GPIO_WATCHDOG=m
-CONFIG_MENF21BMC_WATCHDOG=m
-CONFIG_MENZ069_WATCHDOG=m
-# CONFIG_TANGOX_WATCHDOG is not set
-CONFIG_WM831X_WATCHDOG=m
-CONFIG_XILINX_WATCHDOG=m
-CONFIG_ZIIRAVE_WATCHDOG=m
-CONFIG_RAVE_SP_WATCHDOG=m
-CONFIG_MLX_WDT=m
-CONFIG_SL28CPLD_WATCHDOG=m
-# CONFIG_ARM_SP805_WATCHDOG is not set
-# CONFIG_ARMADA_37XX_WATCHDOG is not set
-# CONFIG_AT91SAM9X_WATCHDOG is not set
-# CONFIG_SAMA5D4_WATCHDOG is not set
-CONFIG_CADENCE_WATCHDOG=m
-CONFIG_FTWDT010_WATCHDOG=m
-# CONFIG_S3C2410_WATCHDOG is not set
-CONFIG_DW_WATCHDOG=m
-# CONFIG_OMAP_WATCHDOG is not set
-# CONFIG_DAVINCI_WATCHDOG is not set
-# CONFIG_ORION_WATCHDOG is not set
-# CONFIG_RN5T618_WATCHDOG is not set
-# CONFIG_SUNXI_WATCHDOG is not set
-# CONFIG_NPCM7XX_WATCHDOG is not set
-# CONFIG_TWL4030_WATCHDOG is not set
-CONFIG_MAX63XX_WATCHDOG=m
-CONFIG_MAX77620_WATCHDOG=m
-# CONFIG_IMX2_WDT is not set
-# CONFIG_IMX7ULP_WDT is not set
-CONFIG_UX500_WATCHDOG=y
-CONFIG_RETU_WATCHDOG=m
-CONFIG_SIRFSOC_WATCHDOG=y
-# CONFIG_ST_LPC_WATCHDOG is not set
-# CONFIG_TEGRA_WATCHDOG is not set
-# CONFIG_QCOM_WDT is not set
-# CONFIG_MESON_GXBB_WATCHDOG is not set
-# CONFIG_MESON_WATCHDOG is not set
-# CONFIG_MEDIATEK_WATCHDOG is not set
-# CONFIG_DIGICOLOR_WATCHDOG is not set
-CONFIG_ARM_SMC_WATCHDOG=m
-# CONFIG_ATLAS7_WATCHDOG is not set
-# CONFIG_RENESAS_WDT is not set
-# CONFIG_RENESAS_RZAWDT is not set
-CONFIG_ASPEED_WATCHDOG=y
-# CONFIG_ZX2967_WATCHDOG is not set
-CONFIG_STM32_WATCHDOG=y
-# CONFIG_UNIPHIER_WATCHDOG is not set
-CONFIG_RTD119X_WATCHDOG=y
-CONFIG_MSC313E_WATCHDOG=m
-CONFIG_ALIM7101_WDT=m
-CONFIG_I6300ESB_WDT=m
-CONFIG_HP_WATCHDOG=m
-CONFIG_KEMPLD_WDT=m
-CONFIG_BCM7038_WDT=m
-CONFIG_MEN_A21_WDT=m
-
-#
-# PCI-based Watchdog Cards
-#
-CONFIG_PCIPCWATCHDOG=m
-CONFIG_WDTPCI=m
-
-#
-# USB-based Watchdog Cards
-#
-CONFIG_USBPCWATCHDOG=m
-CONFIG_KEEMBAY_WATCHDOG=m
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SSB=m
-CONFIG_SSB_SPROM=y
-CONFIG_SSB_BLOCKIO=y
-CONFIG_SSB_PCIHOST_POSSIBLE=y
-CONFIG_SSB_PCIHOST=y
-CONFIG_SSB_B43_PCI_BRIDGE=y
-CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
-CONFIG_SSB_PCMCIAHOST=y
-CONFIG_SSB_SDIOHOST_POSSIBLE=y
-CONFIG_SSB_SDIOHOST=y
-CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
-CONFIG_SSB_DRIVER_PCICORE=y
-CONFIG_SSB_DRIVER_GPIO=y
-CONFIG_BCMA_POSSIBLE=y
-CONFIG_BCMA=m
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_SOC=y
-CONFIG_BCMA_DRIVER_PCI=y
-CONFIG_BCMA_SFLASH=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_DRIVER_GPIO=y
-# CONFIG_BCMA_DEBUG is not set
-
-#
-# Multifunction device drivers
-#
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_ALTERA_A10SR is not set
-CONFIG_MFD_ALTERA_A10SR=y
-# CONFIG_MFD_ALTERA_SYSMGR is not set
-CONFIG_MFD_ACT8945A=m
-# CONFIG_MFD_SUN4I_GPADC is not set
-# CONFIG_MFD_AS3711 is not set
-# CONFIG_MFD_AS3722 is not set
-# CONFIG_PMIC_ADP5520 is not set
-# CONFIG_MFD_AAT2870_CORE is not set
-# CONFIG_MFD_AT91_USART is not set
-CONFIG_MFD_ATMEL_FLEXCOM=m
-CONFIG_MFD_ATMEL_HLCDC=m
-CONFIG_MFD_ATMEL_SMC=y
-CONFIG_MFD_BCM590XX=m
-CONFIG_MFD_BD9571MWV=m
-# CONFIG_MFD_AC100 is not set
-CONFIG_MFD_AXP20X=m
-CONFIG_MFD_AXP20X_I2C=m
-# CONFIG_MFD_AXP20X_RSB is not set
-CONFIG_MFD_CROS_EC_DEV=m
-CONFIG_MFD_MADERA=m
-CONFIG_MFD_MADERA_I2C=m
-CONFIG_MFD_MADERA_SPI=m
-CONFIG_MFD_CS47L15=y
-CONFIG_MFD_CS47L35=y
-CONFIG_MFD_CS47L85=y
-CONFIG_MFD_CS47L90=y
-CONFIG_MFD_CS47L92=y
-CONFIG_MFD_ASIC3=y
-# CONFIG_PMIC_DA903X is not set
-CONFIG_PMIC_DA9052=y
-CONFIG_MFD_DA9052_SPI=y
-# CONFIG_MFD_DA9052_I2C is not set
-# CONFIG_MFD_DA9055 is not set
-CONFIG_MFD_DA9062=m
-CONFIG_MFD_DA9063=m
-CONFIG_MFD_DA9150=m
-CONFIG_MFD_DLN2=m
-# CONFIG_MFD_EXYNOS_LPASS is not set
-CONFIG_MFD_GATEWORKS_GSC=m
-CONFIG_MFD_MC13XXX=m
-CONFIG_MFD_MC13XXX_SPI=m
-CONFIG_MFD_MC13XXX_I2C=m
-CONFIG_MFD_MP2629=m
-CONFIG_MFD_HI6421_PMIC=m
-# CONFIG_MFD_HI655X_PMIC is not set
-CONFIG_HTC_PASIC3=m
-# CONFIG_HTC_I2CPLD is not set
-CONFIG_LPC_ICH=m
-CONFIG_LPC_SCH=m
-CONFIG_MFD_INTEL_PMT=m
-CONFIG_MFD_IQS62X=m
-CONFIG_MFD_JANZ_CMODIO=m
-CONFIG_MFD_KEMPLD=m
-CONFIG_MFD_88PM800=m
-CONFIG_MFD_88PM805=m
-# CONFIG_MFD_88PM860X is not set
-CONFIG_MFD_MAX14577=m
-# CONFIG_MFD_MAX77620 is not set
-CONFIG_MFD_MAX77650=m
-CONFIG_MFD_MAX77686=m
-CONFIG_MFD_MAX77693=m
-CONFIG_MFD_MAX77714=m
-# CONFIG_MFD_MAX77843 is not set
-CONFIG_MFD_MAX8907=m
-# CONFIG_MFD_MAX8925 is not set
-# CONFIG_MFD_MAX8997 is not set
-# CONFIG_MFD_MAX8998 is not set
-CONFIG_MFD_MT6360=m
-CONFIG_MFD_MT6370=m
-CONFIG_MFD_MT6397=m
-CONFIG_MFD_MENF21BMC=m
-CONFIG_MFD_OCELOT=m
-CONFIG_EZX_PCAP=y
-CONFIG_MFD_CPCAP=m
-CONFIG_MFD_VIPERBOARD=m
-CONFIG_MFD_NTXEC=m
-CONFIG_MFD_RETU=m
-CONFIG_MFD_PCF50633=m
-CONFIG_PCF50633_ADC=m
-CONFIG_PCF50633_GPIO=m
-CONFIG_UCB1400_CORE=m
-CONFIG_MFD_PM8XXX=m
-# CONFIG_MFD_QCOM_RPM is not set
-# CONFIG_MFD_SPMI_PMIC is not set
-CONFIG_MFD_SY7636A=m
-CONFIG_MFD_RDC321X=m
-CONFIG_MFD_RT4831=m
-CONFIG_MFD_RT5033=m
-CONFIG_MFD_RT5120=m
-# CONFIG_MFD_RC5T583 is not set
-CONFIG_MFD_RK808=m
-CONFIG_MFD_RN5T618=m
-# CONFIG_MFD_SEC_CORE is not set
-CONFIG_MFD_SI476X_CORE=m
-CONFIG_MFD_SIMPLE_MFD_I2C=m
-CONFIG_MFD_SL28CPLD=m
-CONFIG_MFD_SM501=m
-CONFIG_MFD_SM501_GPIO=y
-CONFIG_MFD_SKY81452=m
-CONFIG_ABX500_CORE=y
-# CONFIG_AB3100_CORE is not set
-CONFIG_AB8500_CORE=y
-CONFIG_MFD_DB8500_PRCMU=y
-CONFIG_MFD_STMPE=y
-
-#
-# STMicroelectronics STMPE Interface Drivers
-#
-CONFIG_STMPE_I2C=y
-CONFIG_STMPE_SPI=y
-# end of STMicroelectronics STMPE Interface Drivers
-
-CONFIG_MFD_SUN6I_PRCM=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MFD_TI_AM335X_TSCADC=m
-CONFIG_MFD_LP3943=m
-# CONFIG_MFD_LP8788 is not set
-CONFIG_MFD_TI_LMU=m
-CONFIG_MFD_OMAP_USB_HOST=y
-# CONFIG_MFD_PALMAS is not set
-CONFIG_TPS6105X=m
-CONFIG_TPS65010=m
-CONFIG_TPS6507X=m
-CONFIG_MFD_TPS65086=m
-# CONFIG_MFD_TPS65090 is not set
-CONFIG_MFD_TPS65217=m
-CONFIG_MFD_TI_LP873X=m
-CONFIG_MFD_TI_LP87565=m
-CONFIG_MFD_TPS65218=m
-# CONFIG_MFD_TPS6586X is not set
-# CONFIG_MFD_TPS65910 is not set
-CONFIG_MFD_TPS65912=y
-CONFIG_MFD_TPS65912_I2C=m
-CONFIG_MFD_TPS65912_SPI=y
-# CONFIG_MFD_TPS80031 is not set
-CONFIG_TWL4030_CORE=y
-CONFIG_TWL4030_POWER=y
-# CONFIG_MFD_TWL4030_AUDIO is not set
-# CONFIG_TWL6040_CORE is not set
-CONFIG_MFD_WL1273_CORE=m
-CONFIG_MFD_LM3533=m
-# CONFIG_MFD_TC3589X is not set
-CONFIG_MFD_TMIO=y
-CONFIG_MFD_T7L66XB=y
-CONFIG_MFD_TC6387XB=y
-CONFIG_MFD_TC6393XB=y
-CONFIG_MFD_TQMX86=m
-CONFIG_MFD_VX855=m
-# CONFIG_MFD_LOCHNAGAR is not set
-CONFIG_MFD_ARIZONA=y
-CONFIG_MFD_ARIZONA_I2C=m
-CONFIG_MFD_ARIZONA_SPI=m
-CONFIG_MFD_CS47L24=y
-CONFIG_MFD_WM5102=y
-CONFIG_MFD_WM5110=y
-CONFIG_MFD_WM8997=y
-CONFIG_MFD_WM8998=y
-# CONFIG_MFD_WM8400 is not set
-CONFIG_MFD_WM831X=y
-# CONFIG_MFD_WM831X_I2C is not set
-CONFIG_MFD_WM831X_SPI=y
-# CONFIG_MFD_WM8350_I2C is not set
-CONFIG_MFD_WM8994=m
-# CONFIG_MFD_ROHM_BD718XX is not set
-# CONFIG_MFD_ROHM_BD70528 is not set
-# CONFIG_MFD_ROHM_BD71828 is not set
-CONFIG_MFD_ROHM_BD957XMUF=m
-# CONFIG_MFD_STM32_LPTIMER is not set
-# CONFIG_MFD_STM32_TIMERS is not set
-# CONFIG_MFD_STPMIC1 is not set
-CONFIG_MFD_STMFX=m
-CONFIG_MFD_WCD934X=m
-CONFIG_MFD_ATC260X_I2C=m
-CONFIG_MFD_KHADAS_MCU=m
-CONFIG_MFD_QCOM_PM8008=m
-CONFIG_MFD_VEXPRESS_SYSREG=m
-CONFIG_RAVE_SP_CORE=m
-CONFIG_MFD_INTEL_M10_BMC=m
-# end of Multifunction device drivers
-
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
-CONFIG_REGULATOR_USERSPACE_CONSUMER=m
-CONFIG_REGULATOR_88PG86X=m
-CONFIG_REGULATOR_88PM800=m
-CONFIG_REGULATOR_ACT8865=m
-CONFIG_REGULATOR_ACT8945A=m
-CONFIG_REGULATOR_AD5398=m
-# CONFIG_REGULATOR_ANATOP is not set
-# CONFIG_REGULATOR_AB8500 is not set
-CONFIG_REGULATOR_ARIZONA_LDO1=m
-CONFIG_REGULATOR_ATC260X=m
-CONFIG_REGULATOR_ARIZONA_MICSUPP=m
-CONFIG_REGULATOR_ARM_SCMI=m
-CONFIG_REGULATOR_AXP20X=m
-CONFIG_REGULATOR_BCM590XX=m
-CONFIG_REGULATOR_BD9571MWV=m
-CONFIG_REGULATOR_BD957XMUF=m
-CONFIG_REGULATOR_CPCAP=m
-CONFIG_REGULATOR_CROS_EC=m
-CONFIG_REGULATOR_DA9052=m
-CONFIG_REGULATOR_DA9062=m
-CONFIG_REGULATOR_DA9063=m
-CONFIG_REGULATOR_DA9210=m
-CONFIG_REGULATOR_DA9211=m
-CONFIG_REGULATOR_DA9121=m
-CONFIG_REGULATOR_DBX500_PRCMU=y
-CONFIG_REGULATOR_DB8500_PRCMU=y
-CONFIG_REGULATOR_FAN53555=m
-CONFIG_REGULATOR_FAN53880=m
-CONFIG_REGULATOR_GPIO=m
-CONFIG_REGULATOR_HI6421=m
-CONFIG_REGULATOR_HI6421V530=m
-CONFIG_REGULATOR_ISL9305=m
-CONFIG_REGULATOR_ISL6271A=m
-CONFIG_REGULATOR_LM363X=m
-CONFIG_REGULATOR_LP3971=m
-CONFIG_REGULATOR_LP3972=m
-CONFIG_REGULATOR_LP872X=m
-CONFIG_REGULATOR_LP873X=m
-CONFIG_REGULATOR_LP8755=m
-CONFIG_REGULATOR_LP87565=m
-CONFIG_REGULATOR_LTC3589=m
-CONFIG_REGULATOR_LTC3676=m
-CONFIG_REGULATOR_MAX14577=m
-CONFIG_REGULATOR_MAX1586=m
-CONFIG_REGULATOR_MAX77650=m
-CONFIG_REGULATOR_MAX8649=m
-CONFIG_REGULATOR_MAX8660=m
-CONFIG_REGULATOR_MAX8893=m
-CONFIG_REGULATOR_MAX8907=m
-CONFIG_REGULATOR_MAX8952=m
-CONFIG_REGULATOR_MAX8973=m
-CONFIG_REGULATOR_MAX77686=m
-CONFIG_REGULATOR_MAX77693=m
-CONFIG_REGULATOR_MAX77802=m
-CONFIG_REGULATOR_MAX77826=m
-CONFIG_REGULATOR_MC13XXX_CORE=m
-CONFIG_REGULATOR_MC13783=m
-CONFIG_REGULATOR_MC13892=m
-CONFIG_REGULATOR_MCP16502=m
-CONFIG_REGULATOR_MP5416=m
-CONFIG_REGULATOR_MP8859=m
-CONFIG_REGULATOR_MP886X=m
-CONFIG_REGULATOR_MPQ7920=m
-CONFIG_REGULATOR_MT6311=m
-CONFIG_REGULATOR_MT6315=m
-CONFIG_REGULATOR_MT6370=m
-CONFIG_REGULATOR_MT6323=m
-CONFIG_REGULATOR_MT6331=m
-CONFIG_REGULATOR_MT6332=m
-CONFIG_REGULATOR_MT6358=m
-CONFIG_REGULATOR_MT6359=m
-CONFIG_REGULATOR_MT6360=m
-CONFIG_REGULATOR_MT6370=m
-CONFIG_REGULATOR_MT6397=m
-# CONFIG_REGULATOR_PBIAS is not set
-CONFIG_REGULATOR_PCA9450=m
-CONFIG_REGULATOR_PF8X00=m
-CONFIG_REGULATOR_PCAP=m
-CONFIG_REGULATOR_PCF50633=m
-CONFIG_REGULATOR_PFUZE100=m
-CONFIG_REGULATOR_PV88060=m
-CONFIG_REGULATOR_PV88080=m
-CONFIG_REGULATOR_PV88090=m
-CONFIG_REGULATOR_PWM=m
-CONFIG_REGULATOR_QCOM_RPMH=m
-CONFIG_REGULATOR_QCOM_SPMI=m
-CONFIG_REGULATOR_QCOM_USB_VBUS=m
-CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
-CONFIG_REGULATOR_RK808=y
-CONFIG_REGULATOR_RN5T618=m
-CONFIG_REGULATOR_RT4801=m
-CONFIG_REGULATOR_RT4831=m
-CONFIG_REGULATOR_RT5120=m
-CONFIG_REGULATOR_RT5190A=m
-CONFIG_REGULATOR_RT6160=m
-CONFIG_REGULATOR_RT6245=m
-CONFIG_REGULATOR_RT5033=m
-CONFIG_REGULATOR_RT5120=m
-CONFIG_REGULATOR_RT5190A=m
-CONFIG_REGULATOR_RT6245=m
-CONFIG_REGULATOR_RT6160=m
-CONFIG_REGULATOR_RTMV20=m
-CONFIG_REGULATOR_SKY81452=m
-CONFIG_REGULATOR_SLG51000=m
-CONFIG_REGULATOR_SY7636A=m
-# CONFIG_REGULATOR_STM32_BOOSTER is not set
-# CONFIG_REGULATOR_STM32_VREFBUF is not set
-# CONFIG_REGULATOR_STM32_PWR is not set
-# CONFIG_REGULATOR_TI_ABB is not set
-CONFIG_REGULATOR_SY7636A=m
-CONFIG_REGULATOR_SY8106A=m
-CONFIG_REGULATOR_SY8824X=m
-CONFIG_REGULATOR_SY8827N=m
-CONFIG_REGULATOR_TPS51632=m
-CONFIG_REGULATOR_TPS6105X=m
-CONFIG_REGULATOR_TPS62360=m
-CONFIG_REGULATOR_TPS6286X=m
-CONFIG_REGULATOR_TPS65023=m
-CONFIG_REGULATOR_TPS6507X=m
-CONFIG_REGULATOR_TPS65086=m
-CONFIG_REGULATOR_TPS65132=m
-CONFIG_REGULATOR_TPS65217=m
-CONFIG_REGULATOR_TPS65218=m
-CONFIG_REGULATOR_TPS6524X=m
-CONFIG_REGULATOR_TPS65912=m
-CONFIG_REGULATOR_TPS68470=m
-# CONFIG_REGULATOR_TWL4030 is not set
-CONFIG_REGULATOR_UNIPHIER=y
-CONFIG_REGULATOR_VCTRL=m
-CONFIG_REGULATOR_VEXPRESS=m
-# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
-CONFIG_REGULATOR_WM831X=m
-CONFIG_REGULATOR_WM8994=m
-CONFIG_REGULATOR_QCOM_LABIBB=m
-CONFIG_RC_CORE=m
-CONFIG_RC_MAP=m
-CONFIG_LIRC=y
-CONFIG_RC_DECODERS=y
-CONFIG_IR_NEC_DECODER=m
-CONFIG_IR_RC5_DECODER=m
-CONFIG_IR_RC6_DECODER=m
-CONFIG_IR_JVC_DECODER=m
-CONFIG_IR_SONY_DECODER=m
-CONFIG_IR_SANYO_DECODER=m
-CONFIG_IR_SHARP_DECODER=m
-CONFIG_IR_MCE_KBD_DECODER=m
-CONFIG_IR_XMP_DECODER=m
-CONFIG_IR_IMON_DECODER=m
-CONFIG_IR_RCMM_DECODER=m
-CONFIG_RC_DEVICES=y
-CONFIG_RC_ATI_REMOTE=m
-CONFIG_IR_HIX5HD2=m
-CONFIG_IR_IMON=m
-CONFIG_IR_IMON_RAW=m
-CONFIG_IR_MCEUSB=m
-# CONFIG_IR_MESON is not set
-# CONFIG_IR_MTK is not set
-CONFIG_IR_REDRAT3=m
-CONFIG_IR_SPI=m
-CONFIG_IR_STREAMZAP=m
-CONFIG_IR_IGORPLUGUSB=m
-CONFIG_IR_IGUANA=m
-CONFIG_IR_TTUSBIR=m
-CONFIG_RC_LOOPBACK=m
-CONFIG_IR_GPIO_CIR=m
-CONFIG_IR_GPIO_TX=m
-CONFIG_IR_PWM_TX=m
-# CONFIG_RC_ST is not set
-# CONFIG_IR_SUNXI is not set
-CONFIG_IR_SERIAL=m
-CONFIG_IR_SERIAL_TRANSMITTER=y
-CONFIG_IR_SIR=m
-# CONFIG_IR_TANGO is not set
-CONFIG_RC_XBOX_DVD=m
-# CONFIG_IR_ZX is not set
-CONFIG_IR_TOY=m
-CONFIG_CEC_CORE=m
-CONFIG_CEC_NOTIFIER=y
-CONFIG_CEC_PIN=y
-CONFIG_MEDIA_CEC_RC=y
-# CONFIG_CEC_PIN_ERROR_INJ is not set
-CONFIG_MEDIA_CEC_SUPPORT=y
-CONFIG_CEC_CH7322=m
-CONFIG_CEC_CROS_EC=m
-# CONFIG_CEC_MESON_AO is not set
-# CONFIG_CEC_MESON_G12A_AO is not set
-CONFIG_CEC_GPIO=m
-# CONFIG_CEC_SAMSUNG_S5P is not set
-# CONFIG_CEC_STI is not set
-# CONFIG_CEC_STM32 is not set
-# CONFIG_CEC_TEGRA is not set
-CONFIG_USB_PULSE8_CEC=m
-CONFIG_USB_RAINSHADOW_CEC=m
-CONFIG_MEDIA_SUPPORT=m
-CONFIG_MEDIA_SUPPORT_FILTER=y
-CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
-
-#
-# Media device types
-#
-CONFIG_MEDIA_PLATFORM_DRIVERS=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_SDR_SUPPORT=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-# CONFIG_MEDIA_TEST_SUPPORT is not set
-# end of Media device types
-
-CONFIG_VIDEO_DEV=m
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_DVB_CORE=m
-
-#
-# Video4Linux options
-#
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L2_I2C=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_TUNER=m
-CONFIG_V4L2_MEM2MEM_DEV=m
-CONFIG_V4L2_FLASH_LED_CLASS=m
-CONFIG_V4L2_FWNODE=m
-CONFIG_VIDEOBUF_GEN=m
-CONFIG_VIDEOBUF_DMA_SG=m
-CONFIG_VIDEOBUF_VMALLOC=m
-# end of Video4Linux options
-
-#
-# Media controller options
-#
-CONFIG_MEDIA_CONTROLLER_DVB=y
-# end of Media controller options
-
-#
-# Digital TV options
-#
-CONFIG_DVB_MMAP=y
-CONFIG_DVB_NET=y
-CONFIG_DVB_MAX_ADAPTERS=8
-CONFIG_DVB_DYNAMIC_MINORS=y
-# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
-# CONFIG_DVB_ULE_DEBUG is not set
-# end of Digital TV options
-
-#
-# Media drivers
-#
-
-#
-# Drivers filtered as selected at 'Filter media drivers'
-#
-CONFIG_TTPCI_EEPROM=m
-CONFIG_MEDIA_USB_SUPPORT=y
-
-#
-# Webcam devices
-#
-CONFIG_USB_VIDEO_CLASS=m
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-CONFIG_USB_M5602=m
-CONFIG_USB_STV06XX=m
-CONFIG_USB_GL860=m
-CONFIG_USB_GSPCA_BENQ=m
-CONFIG_USB_GSPCA_CONEX=m
-CONFIG_USB_GSPCA_CPIA1=m
-CONFIG_USB_GSPCA_DTCS033=m
-CONFIG_USB_GSPCA_ETOMS=m
-CONFIG_USB_GSPCA_FINEPIX=m
-CONFIG_USB_GSPCA_JEILINJ=m
-CONFIG_USB_GSPCA_JL2005BCD=m
-CONFIG_USB_GSPCA_KINECT=m
-CONFIG_USB_GSPCA_KONICA=m
-CONFIG_USB_GSPCA_MARS=m
-CONFIG_USB_GSPCA_MR97310A=m
-CONFIG_USB_GSPCA_NW80X=m
-CONFIG_USB_GSPCA_OV519=m
-CONFIG_USB_GSPCA_OV534=m
-CONFIG_USB_GSPCA_OV534_9=m
-CONFIG_USB_GSPCA_PAC207=m
-CONFIG_USB_GSPCA_PAC7302=m
-CONFIG_USB_GSPCA_PAC7311=m
-CONFIG_USB_GSPCA_SE401=m
-CONFIG_USB_GSPCA_SN9C2028=m
-CONFIG_USB_GSPCA_SN9C20X=m
-CONFIG_USB_GSPCA_SONIXB=m
-CONFIG_USB_GSPCA_SONIXJ=m
-CONFIG_USB_GSPCA_SPCA500=m
-CONFIG_USB_GSPCA_SPCA501=m
-CONFIG_USB_GSPCA_SPCA505=m
-CONFIG_USB_GSPCA_SPCA506=m
-CONFIG_USB_GSPCA_SPCA508=m
-CONFIG_USB_GSPCA_SPCA561=m
-CONFIG_USB_GSPCA_SPCA1528=m
-CONFIG_USB_GSPCA_SQ905=m
-CONFIG_USB_GSPCA_SQ905C=m
-CONFIG_USB_GSPCA_SQ930X=m
-CONFIG_USB_GSPCA_STK014=m
-CONFIG_USB_GSPCA_STK1135=m
-CONFIG_USB_GSPCA_STV0680=m
-CONFIG_USB_GSPCA_SUNPLUS=m
-CONFIG_USB_GSPCA_T613=m
-CONFIG_USB_GSPCA_TOPRO=m
-CONFIG_USB_GSPCA_TOUPTEK=m
-CONFIG_USB_GSPCA_TV8532=m
-CONFIG_USB_GSPCA_VC032X=m
-CONFIG_USB_GSPCA_VICAM=m
-CONFIG_USB_GSPCA_XIRLINK_CIT=m
-CONFIG_USB_GSPCA_ZC3XX=m
-CONFIG_USB_PWC=m
-# CONFIG_USB_PWC_DEBUG is not set
-CONFIG_USB_PWC_INPUT_EVDEV=y
-CONFIG_VIDEO_CPIA2=m
-CONFIG_USB_ZR364XX=m
-CONFIG_USB_STKWEBCAM=m
-CONFIG_USB_S2255=m
-CONFIG_VIDEO_USBTV=m
-
-#
-# Analog TV USB devices
-#
-CONFIG_VIDEO_PVRUSB2=m
-CONFIG_VIDEO_PVRUSB2_SYSFS=y
-CONFIG_VIDEO_PVRUSB2_DVB=y
-# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
-CONFIG_VIDEO_HDPVR=m
-CONFIG_VIDEO_STK1160_COMMON=m
-CONFIG_VIDEO_STK1160=m
-CONFIG_VIDEO_GO7007=m
-CONFIG_VIDEO_GO7007_USB=m
-CONFIG_VIDEO_GO7007_LOADER=m
-CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
-
-#
-# Analog/digital TV USB devices
-#
-CONFIG_VIDEO_AU0828=m
-CONFIG_VIDEO_AU0828_V4L2=y
-CONFIG_VIDEO_AU0828_RC=y
-CONFIG_VIDEO_CX231XX=m
-CONFIG_VIDEO_CX231XX_RC=y
-CONFIG_VIDEO_CX231XX_ALSA=m
-CONFIG_VIDEO_CX231XX_DVB=m
-CONFIG_VIDEO_TM6000=m
-CONFIG_VIDEO_TM6000_ALSA=m
-CONFIG_VIDEO_TM6000_DVB=m
-
-#
-# Digital TV USB devices
-#
-CONFIG_DVB_USB=m
-# CONFIG_DVB_USB_DEBUG is not set
-CONFIG_DVB_USB_DIB3000MC=m
-CONFIG_DVB_USB_A800=m
-CONFIG_DVB_USB_DIBUSB_MB=m
-CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
-CONFIG_DVB_USB_DIBUSB_MC=m
-CONFIG_DVB_USB_DIB0700=m
-CONFIG_DVB_USB_UMT_010=m
-CONFIG_DVB_USB_CXUSB=m
-CONFIG_DVB_USB_CXUSB_ANALOG=y
-CONFIG_DVB_USB_M920X=m
-CONFIG_DVB_USB_DIGITV=m
-CONFIG_DVB_USB_VP7045=m
-CONFIG_DVB_USB_VP702X=m
-CONFIG_DVB_USB_GP8PSK=m
-CONFIG_DVB_USB_NOVA_T_USB2=m
-CONFIG_DVB_USB_TTUSB2=m
-CONFIG_DVB_USB_DTT200U=m
-CONFIG_DVB_USB_OPERA1=m
-CONFIG_DVB_USB_AF9005=m
-CONFIG_DVB_USB_AF9005_REMOTE=m
-CONFIG_DVB_USB_PCTV452E=m
-CONFIG_DVB_USB_DW2102=m
-CONFIG_DVB_USB_CINERGY_T2=m
-CONFIG_DVB_USB_DTV5100=m
-CONFIG_DVB_USB_AZ6027=m
-CONFIG_DVB_USB_TECHNISAT_USB2=m
-CONFIG_DVB_USB_V2=m
-CONFIG_DVB_USB_AF9015=m
-CONFIG_DVB_USB_AF9035=m
-CONFIG_DVB_USB_ANYSEE=m
-CONFIG_DVB_USB_AU6610=m
-CONFIG_DVB_USB_AZ6007=m
-CONFIG_DVB_USB_CE6230=m
-CONFIG_DVB_USB_EC168=m
-CONFIG_DVB_USB_GL861=m
-CONFIG_DVB_USB_LME2510=m
-CONFIG_DVB_USB_MXL111SF=m
-CONFIG_DVB_USB_RTL28XXU=m
-CONFIG_DVB_USB_DVBSKY=m
-CONFIG_DVB_USB_ZD1301=m
-CONFIG_DVB_TTUSB_BUDGET=m
-CONFIG_DVB_TTUSB_DEC=m
-CONFIG_SMS_USB_DRV=m
-CONFIG_DVB_B2C2_FLEXCOP_USB=m
-# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
-CONFIG_DVB_AS102=m
-
-#
-# Webcam, TV (analog/digital) USB devices
-#
-CONFIG_VIDEO_EM28XX=m
-CONFIG_VIDEO_EM28XX_V4L2=m
-CONFIG_VIDEO_EM28XX_ALSA=m
-CONFIG_VIDEO_EM28XX_DVB=m
-CONFIG_VIDEO_EM28XX_RC=m
-
-#
-# Software defined radio USB devices
-#
-CONFIG_USB_AIRSPY=m
-CONFIG_USB_HACKRF=m
-CONFIG_USB_MSI2500=m
-CONFIG_MEDIA_PCI_SUPPORT=y
-
-#
-# Media capture support
-#
-CONFIG_VIDEO_SOLO6X10=m
-CONFIG_VIDEO_TW5864=m
-CONFIG_VIDEO_TW68=m
-CONFIG_VIDEO_TW686X=m
-
-#
-# Media capture/analog TV support
-#
-CONFIG_VIDEO_IVTV=m
-# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
-CONFIG_VIDEO_IVTV_ALSA=m
-CONFIG_VIDEO_FB_IVTV=m
-CONFIG_VIDEO_HEXIUM_GEMINI=m
-CONFIG_VIDEO_HEXIUM_ORION=m
-CONFIG_VIDEO_MXB=m
-CONFIG_VIDEO_DT3155=m
-
-#
-# Media capture/analog/hybrid TV support
-#
-CONFIG_VIDEO_CX18=m
-CONFIG_VIDEO_CX18_ALSA=m
-CONFIG_VIDEO_CX23885=m
-CONFIG_MEDIA_ALTERA_CI=m
-CONFIG_VIDEO_CX25821=m
-CONFIG_VIDEO_CX25821_ALSA=m
-CONFIG_VIDEO_CX88=m
-CONFIG_VIDEO_CX88_ALSA=m
-CONFIG_VIDEO_CX88_BLACKBIRD=m
-CONFIG_VIDEO_CX88_DVB=m
-CONFIG_VIDEO_CX88_ENABLE_VP3054=y
-CONFIG_VIDEO_CX88_VP3054=m
-CONFIG_VIDEO_CX88_MPEG=m
-CONFIG_VIDEO_BT848=m
-CONFIG_DVB_BT8XX=m
-CONFIG_VIDEO_SAA7134=m
-CONFIG_VIDEO_SAA7134_ALSA=m
-CONFIG_VIDEO_SAA7134_RC=y
-CONFIG_VIDEO_SAA7134_DVB=m
-CONFIG_VIDEO_SAA7134_GO7007=m
-CONFIG_VIDEO_SAA7164=m
-
-#
-# Media digital TV PCI Adapters
-#
-CONFIG_DVB_AV7110_IR=y
-CONFIG_DVB_AV7110=m
-CONFIG_DVB_AV7110_OSD=y
-CONFIG_DVB_BUDGET_CORE=m
-CONFIG_DVB_BUDGET=m
-CONFIG_DVB_BUDGET_CI=m
-CONFIG_DVB_BUDGET_AV=m
-CONFIG_DVB_BUDGET_PATCH=m
-CONFIG_DVB_B2C2_FLEXCOP_PCI=m
-# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
-CONFIG_DVB_PLUTO2=m
-CONFIG_DVB_DM1105=m
-CONFIG_DVB_PT1=m
-CONFIG_DVB_PT3=m
-CONFIG_MANTIS_CORE=m
-CONFIG_DVB_MANTIS=m
-CONFIG_DVB_HOPPER=m
-CONFIG_DVB_NGENE=m
-CONFIG_DVB_DDBRIDGE=m
-# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set
-CONFIG_DVB_SMIPCIE=m
-CONFIG_DVB_NETUP_UNIDVB=m
-CONFIG_RADIO_ADAPTERS=y
-CONFIG_RADIO_TEA575X=m
-CONFIG_RADIO_SI470X=m
-CONFIG_USB_SI470X=m
-CONFIG_I2C_SI470X=m
-CONFIG_RADIO_SI4713=m
-CONFIG_USB_SI4713=m
-CONFIG_PLATFORM_SI4713=m
-CONFIG_I2C_SI4713=m
-CONFIG_RADIO_SI476X=m
-CONFIG_USB_MR800=m
-CONFIG_USB_DSBR=m
-CONFIG_RADIO_MAXIRADIO=m
-CONFIG_RADIO_SHARK=m
-CONFIG_RADIO_SHARK2=m
-CONFIG_USB_KEENE=m
-CONFIG_USB_RAREMONO=m
-CONFIG_USB_MA901=m
-CONFIG_RADIO_TEA5764=m
-CONFIG_RADIO_SAA7706H=m
-CONFIG_RADIO_TEF6862=m
-CONFIG_RADIO_WL1273=m
-CONFIG_RADIO_WL128X=m
-CONFIG_MEDIA_COMMON_OPTIONS=y
-
-#
-# common driver options
-#
-CONFIG_VIDEO_CX2341X=m
-CONFIG_VIDEO_TVEEPROM=m
-CONFIG_CYPRESS_FIRMWARE=m
-CONFIG_VIDEOBUF2_CORE=m
-CONFIG_VIDEOBUF2_V4L2=m
-CONFIG_VIDEOBUF2_MEMOPS=m
-CONFIG_VIDEOBUF2_DMA_CONTIG=m
-CONFIG_VIDEOBUF2_VMALLOC=m
-CONFIG_VIDEOBUF2_DMA_SG=m
-CONFIG_VIDEOBUF2_DVB=m
-CONFIG_DVB_B2C2_FLEXCOP=m
-CONFIG_VIDEO_SAA7146=m
-CONFIG_VIDEO_SAA7146_VV=m
-CONFIG_SMS_SIANO_MDTV=m
-CONFIG_SMS_SIANO_RC=y
-# CONFIG_SMS_SIANO_DEBUGFS is not set
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_CAFE_CCIC=m
-# CONFIG_VIDEO_MMP_CAMERA is not set
-CONFIG_VIDEO_CADENCE=y
-CONFIG_VIDEO_CADENCE_CSI2RX=m
-CONFIG_VIDEO_CADENCE_CSI2TX=m
-CONFIG_VIDEO_ASPEED=m
-CONFIG_VIDEO_MUX=m
-# CONFIG_VIDEO_STM32_DCMI is not set
-# CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS is not set
-# CONFIG_VIDEO_AM437X_VPFE is not set
-CONFIG_VIDEO_XILINX=m
-CONFIG_VIDEO_XILINX_CSI2RXSS=m
-# CONFIG_VIDEO_XILINX_TPG is not set
-CONFIG_VIDEO_XILINX_VTC=m
-# CONFIG_VIDEO_RCAR_CSI2 is not set
-# CONFIG_VIDEO_RCAR_VIN is not set
-# CONFIG_VIDEO_ATMEL_ISC is not set
-# CONFIG_VIDEO_ATMEL_XISC is not set
-# CONFIG_VIDEO_ATMEL_ISI is not set
-# CONFIG_VIDEO_MICROCHIP_CSI2DC is not set
-# CONFIG_VIDEO_SUN4I_CSI is not set
-# CONFIG_VIDEO_SUN6I_CSI is not set
-# CONFIG_VIDEO_TI_CAL is not set
-CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_VIDEO_ALLEGRO_DVT=m
-# CONFIG_VIDEO_CODA is not set
-# CONFIG_VIDEO_IMX_PXP is not set
-CONFIG_VIDEO_DW100=m
-CONFIG_VIDEO_IMX8_JPEG=m
-# CONFIG_VIDEO_MEDIATEK_VPU is not set
-CONFIG_VIDEO_MEDIATEK_MDP3=m
-CONFIG_VIDEO_TEGRA_VDE=m
-CONFIG_VIDEO_IMX_MIPI_CSIS=m
-CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
-CONFIG_VIDEO_MESON_GE2D=m
-CONFIG_VIDEO_AMPHION_VPU=m
-# CONFIG_VIDEO_SAMSUNG_S5P_G2D is not set
-# CONFIG_VIDEO_SAMSUNG_S5P_JPEG is not set
-# CONFIG_VIDEO_SAMSUNG_S5P_MFC is not set
-# CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC is not set
-# CONFIG_VIDEO_STI_BDISP is not set
-# CONFIG_VIDEO_STI_HVA is not set
-# CONFIG_VIDEO_STI_DELTA is not set
-# CONFIG_VIDEO_RENESAS_FDP1 is not set
-# CONFIG_VIDEO_RENESAS_JPU is not set
-# CONFIG_VIDEO_RENESAS_FCP is not set
-# CONFIG_VIDEO_RENESAS_VSP1 is not set
-# CONFIG_VIDEO_ROCKCHIP_RGA is not set
-# CONFIG_VIDEO_TI_VPE is not set
-# CONFIG_VIDEO_SUN8I_DEINTERLACE is not set
-# CONFIG_VIDEO_SUN8I_ROTATE is not set
-CONFIG_DVB_PLATFORM_DRIVERS=y
-CONFIG_DVB_C8SECTPFE=m
-CONFIG_SDR_PLATFORM_DRIVERS=y
-# CONFIG_VIDEO_RCAR_DRIF is not set
-
-#
-# MMC/SDIO DVB adapters
-#
-CONFIG_SMS_SDIO_DRV=m
-
-#
-# FireWire (IEEE 1394) Adapters
-#
-CONFIG_DVB_FIREDTV=m
-CONFIG_DVB_FIREDTV_INPUT=y
-# end of Media drivers
-
-#
-# Media ancillary drivers
-#
-CONFIG_MEDIA_ATTACH=y
-
-#
-# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
-#
-CONFIG_VIDEO_IR_I2C=m
-
-#
-# Audio decoders, processors and mixers
-#
-CONFIG_VIDEO_TVAUDIO=m
-CONFIG_VIDEO_TDA7432=m
-CONFIG_VIDEO_TDA9840=m
-CONFIG_VIDEO_TDA1997X=m
-CONFIG_VIDEO_TEA6415C=m
-CONFIG_VIDEO_TEA6420=m
-CONFIG_VIDEO_MSP3400=m
-CONFIG_VIDEO_CS3308=m
-CONFIG_VIDEO_CS5345=m
-CONFIG_VIDEO_CS53L32A=m
-CONFIG_VIDEO_TLV320AIC23B=m
-CONFIG_VIDEO_UDA1342=m
-CONFIG_VIDEO_WM8775=m
-CONFIG_VIDEO_WM8739=m
-CONFIG_VIDEO_VP27SMPX=m
-CONFIG_VIDEO_SONY_BTF_MPX=m
-# end of Audio decoders, processors and mixers
-
-#
-# RDS decoders
-#
-CONFIG_VIDEO_SAA6588=m
-# end of RDS decoders
-
-#
-# Video decoders
-#
-CONFIG_VIDEO_ADV7180=m
-CONFIG_VIDEO_ADV7183=m
-CONFIG_VIDEO_ADV748X=m
-# CONFIG_VIDEO_ADV7604 is not set
-# CONFIG_VIDEO_ADV7842 is not set
-CONFIG_VIDEO_BT819=m
-CONFIG_VIDEO_BT856=m
-CONFIG_VIDEO_BT866=m
-CONFIG_VIDEO_ISL7998X=m
-CONFIG_VIDEO_KS0127=m
-CONFIG_VIDEO_ML86V7667=m
-CONFIG_VIDEO_SAA7110=m
-CONFIG_VIDEO_SAA711X=m
-CONFIG_VIDEO_TC358743=m
-CONFIG_VIDEO_TC358743_CEC=y
-CONFIG_VIDEO_TVP514X=m
-CONFIG_VIDEO_TVP5150=m
-CONFIG_VIDEO_TVP7002=m
-CONFIG_VIDEO_TW2804=m
-CONFIG_VIDEO_TW9903=m
-CONFIG_VIDEO_TW9906=m
-CONFIG_VIDEO_TW9910=m
-CONFIG_VIDEO_VPX3220=m
-CONFIG_VIDEO_MAX9286=m
-
-#
-# Video and audio decoders
-#
-CONFIG_VIDEO_SAA717X=m
-CONFIG_VIDEO_CX25840=m
-# end of Video decoders
-
-#
-# Video encoders
-#
-CONFIG_VIDEO_SAA7127=m
-CONFIG_VIDEO_SAA7185=m
-CONFIG_VIDEO_ADV7170=m
-CONFIG_VIDEO_ADV7175=m
-CONFIG_VIDEO_ADV7343=m
-CONFIG_VIDEO_ADV7393=m
-CONFIG_VIDEO_AD9389B=m
-CONFIG_VIDEO_AK881X=m
-CONFIG_VIDEO_THS8200=m
-# end of Video encoders
-
-#
-# Video improvement chips
-#
-CONFIG_VIDEO_UPD64031A=m
-CONFIG_VIDEO_UPD64083=m
-# end of Video improvement chips
-
-#
-# Audio/Video compression chips
-#
-CONFIG_VIDEO_SAA6752HS=m
-# end of Audio/Video compression chips
-
-#
-# SDR tuner chips
-#
-CONFIG_SDR_MAX2175=m
-# end of SDR tuner chips
-
-#
-# Miscellaneous helper chips
-#
-CONFIG_VIDEO_THS7303=m
-CONFIG_VIDEO_M52790=m
-CONFIG_VIDEO_I2C=m
-CONFIG_VIDEO_ST_MIPID02=m
-# end of Miscellaneous helper chips
-
-#
-# Camera sensor devices
-#
-CONFIG_VIDEO_APTINA_PLL=m
-CONFIG_VIDEO_SMIAPP_PLL=m
-CONFIG_VIDEO_HI556=m
-CONFIG_VIDEO_IMX208=m
-CONFIG_VIDEO_IMX214=m
-CONFIG_VIDEO_IMX219=m
-CONFIG_VIDEO_IMX258=m
-CONFIG_VIDEO_IMX274=m
-CONFIG_VIDEO_IMX290=m
-CONFIG_VIDEO_IMX319=m
-CONFIG_VIDEO_IMX334=m
-CONFIG_VIDEO_IMX355=m
-CONFIG_VIDEO_OV02A10=m
-CONFIG_VIDEO_OV08D10=m
-CONFIG_VIDEO_OV2640=m
-CONFIG_VIDEO_OV2659=m
-CONFIG_VIDEO_OV2680=m
-CONFIG_VIDEO_OV2685=m
-CONFIG_VIDEO_OV5640=m
-CONFIG_VIDEO_OV5645=m
-CONFIG_VIDEO_OV5647=m
-CONFIG_VIDEO_OV5648=m
-CONFIG_VIDEO_OV6650=m
-CONFIG_VIDEO_OV5670=m
-CONFIG_VIDEO_OV5675=m
-CONFIG_VIDEO_OV5695=m
-CONFIG_VIDEO_OV7251=m
-CONFIG_VIDEO_OV772X=m
-CONFIG_VIDEO_OV7640=m
-CONFIG_VIDEO_OV7670=m
-CONFIG_VIDEO_OV7740=m
-CONFIG_VIDEO_OV8856=m
-CONFIG_VIDEO_OV8865=m
-CONFIG_VIDEO_OV9640=m
-CONFIG_VIDEO_OV9650=m
-CONFIG_VIDEO_OV13858=m
-CONFIG_VIDEO_VS6624=m
-CONFIG_VIDEO_MT9M001=m
-CONFIG_VIDEO_MT9M032=m
-CONFIG_VIDEO_MT9M111=m
-CONFIG_VIDEO_MT9P031=m
-CONFIG_VIDEO_MT9T001=m
-CONFIG_VIDEO_MT9T112=m
-CONFIG_VIDEO_MT9V011=m
-CONFIG_VIDEO_MT9V032=m
-CONFIG_VIDEO_MT9V111=m
-CONFIG_VIDEO_SR030PC30=m
-CONFIG_VIDEO_NOON010PC30=m
-CONFIG_VIDEO_OG01A1B=m
-CONFIG_VIDEO_M5MOLS=m
-CONFIG_VIDEO_RDACM20=m
-CONFIG_VIDEO_RDACM21=m
-CONFIG_VIDEO_RJ54N1=m
-CONFIG_VIDEO_S5K6AA=m
-CONFIG_VIDEO_S5K6A3=m
-CONFIG_VIDEO_S5K4ECGX=m
-CONFIG_VIDEO_S5K5BAF=m
-CONFIG_VIDEO_CCS=m
-CONFIG_VIDEO_SMIAPP=m
-CONFIG_VIDEO_ET8EK8=m
-CONFIG_VIDEO_S5C73M3=m
-# end of Camera sensor devices
-
-#
-# Lens drivers
-#
-CONFIG_VIDEO_AD5820=m
-CONFIG_VIDEO_AK7375=m
-CONFIG_VIDEO_DW9714=m
-CONFIG_VIDEO_DW9768=m
-CONFIG_VIDEO_DW9807_VCM=m
-# end of Lens drivers
-
-#
-# Flash devices
-#
-CONFIG_VIDEO_ADP1653=m
-CONFIG_VIDEO_LM3560=m
-CONFIG_VIDEO_LM3646=m
-# end of Flash devices
-
-#
-# SPI helper chips
-#
-CONFIG_VIDEO_GS1662=m
-# end of SPI helper chips
-
-#
-# Media SPI Adapters
-#
-CONFIG_CXD2880_SPI_DRV=m
-# end of Media SPI Adapters
-
-CONFIG_MEDIA_TUNER=m
-
-#
-# Customize TV tuners
-#
-CONFIG_MEDIA_TUNER_SIMPLE=m
-CONFIG_MEDIA_TUNER_TDA18250=m
-CONFIG_MEDIA_TUNER_TDA8290=m
-CONFIG_MEDIA_TUNER_TDA827X=m
-CONFIG_MEDIA_TUNER_TDA18271=m
-CONFIG_MEDIA_TUNER_TDA9887=m
-CONFIG_MEDIA_TUNER_TEA5761=m
-CONFIG_MEDIA_TUNER_TEA5767=m
-CONFIG_MEDIA_TUNER_MSI001=m
-CONFIG_MEDIA_TUNER_MT20XX=m
-CONFIG_MEDIA_TUNER_MT2060=m
-CONFIG_MEDIA_TUNER_MT2063=m
-CONFIG_MEDIA_TUNER_MT2266=m
-CONFIG_MEDIA_TUNER_MT2131=m
-CONFIG_MEDIA_TUNER_QT1010=m
-CONFIG_MEDIA_TUNER_XC2028=m
-CONFIG_MEDIA_TUNER_XC5000=m
-CONFIG_MEDIA_TUNER_XC4000=m
-CONFIG_MEDIA_TUNER_MXL5005S=m
-CONFIG_MEDIA_TUNER_MXL5007T=m
-CONFIG_MEDIA_TUNER_MC44S803=m
-CONFIG_MEDIA_TUNER_MAX2165=m
-CONFIG_MEDIA_TUNER_TDA18218=m
-CONFIG_MEDIA_TUNER_FC0011=m
-CONFIG_MEDIA_TUNER_FC0012=m
-CONFIG_MEDIA_TUNER_FC0013=m
-CONFIG_MEDIA_TUNER_TDA18212=m
-CONFIG_MEDIA_TUNER_E4000=m
-CONFIG_MEDIA_TUNER_FC2580=m
-CONFIG_MEDIA_TUNER_M88RS6000T=m
-CONFIG_MEDIA_TUNER_TUA9001=m
-CONFIG_MEDIA_TUNER_SI2157=m
-CONFIG_MEDIA_TUNER_IT913X=m
-CONFIG_MEDIA_TUNER_R820T=m
-CONFIG_MEDIA_TUNER_MXL301RF=m
-CONFIG_MEDIA_TUNER_QM1D1C0042=m
-CONFIG_MEDIA_TUNER_QM1D1B0004=m
-CONFIG_MEDIA_TUNER_AV201X=m
-CONFIG_MEDIA_TUNER_STV6120=m
-# end of Customize TV tuners
-
-#
-# Customise DVB Frontends
-#
-
-#
-# Multistandard (satellite) frontends
-#
-CONFIG_DVB_STB0899=m
-CONFIG_DVB_STB6100=m
-CONFIG_DVB_STV090x=m
-CONFIG_DVB_STV0910=m
-CONFIG_DVB_STV6110x=m
-CONFIG_DVB_STV6111=m
-CONFIG_DVB_MXL5XX=m
-CONFIG_DVB_M88DS3103=m
-
-#
-# Multistandard (cable + terrestrial) frontends
-#
-CONFIG_DVB_DRXK=m
-CONFIG_DVB_TDA18271C2DD=m
-CONFIG_DVB_SI2165=m
-CONFIG_DVB_MN88472=m
-CONFIG_DVB_MN88473=m
-
-#
-# DVB-S (satellite) frontends
-#
-CONFIG_DVB_CX24110=m
-CONFIG_DVB_CX24123=m
-CONFIG_DVB_MT312=m
-CONFIG_DVB_ZL10036=m
-CONFIG_DVB_ZL10039=m
-CONFIG_DVB_S5H1420=m
-CONFIG_DVB_STV0288=m
-CONFIG_DVB_STB6000=m
-CONFIG_DVB_STV0299=m
-CONFIG_DVB_STV6110=m
-CONFIG_DVB_STV0900=m
-CONFIG_DVB_TDA8083=m
-CONFIG_DVB_TDA10086=m
-CONFIG_DVB_TDA8261=m
-CONFIG_DVB_VES1X93=m
-CONFIG_DVB_TUNER_ITD1000=m
-CONFIG_DVB_TUNER_CX24113=m
-CONFIG_DVB_TDA826X=m
-CONFIG_DVB_TUA6100=m
-CONFIG_DVB_CX24116=m
-CONFIG_DVB_CX24117=m
-CONFIG_DVB_CX24120=m
-CONFIG_DVB_SI21XX=m
-CONFIG_DVB_TS2020=m
-CONFIG_DVB_DS3000=m
-CONFIG_DVB_MB86A16=m
-CONFIG_DVB_TDA10071=m
-
-#
-# DVB-T (terrestrial) frontends
-#
-CONFIG_DVB_SP8870=m
-CONFIG_DVB_SP887X=m
-CONFIG_DVB_CX22700=m
-CONFIG_DVB_CX22702=m
-# CONFIG_DVB_S5H1432 is not set
-CONFIG_DVB_DRXD=m
-CONFIG_DVB_L64781=m
-CONFIG_DVB_TDA1004X=m
-CONFIG_DVB_NXT6000=m
-CONFIG_DVB_MT352=m
-CONFIG_DVB_ZL10353=m
-CONFIG_DVB_DIB3000MB=m
-CONFIG_DVB_DIB3000MC=m
-CONFIG_DVB_DIB7000M=m
-CONFIG_DVB_DIB7000P=m
-CONFIG_DVB_DIB9000=m
-CONFIG_DVB_TDA10048=m
-CONFIG_DVB_AF9013=m
-CONFIG_DVB_EC100=m
-CONFIG_DVB_STV0367=m
-CONFIG_DVB_CXD2820R=m
-CONFIG_DVB_CXD2841ER=m
-CONFIG_DVB_RTL2830=m
-CONFIG_DVB_RTL2832=m
-CONFIG_DVB_RTL2832_SDR=m
-CONFIG_DVB_SI2168=m
-CONFIG_DVB_AS102_FE=m
-CONFIG_DVB_ZD1301_DEMOD=m
-CONFIG_DVB_GP8PSK_FE=m
-CONFIG_DVB_CXD2880=m
-
-#
-# DVB-C (cable) frontends
-#
-CONFIG_DVB_VES1820=m
-CONFIG_DVB_TDA10021=m
-CONFIG_DVB_TDA10023=m
-CONFIG_DVB_STV0297=m
-
-#
-# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
-#
-CONFIG_DVB_NXT200X=m
-CONFIG_DVB_OR51211=m
-CONFIG_DVB_OR51132=m
-CONFIG_DVB_BCM3510=m
-CONFIG_DVB_LGDT330X=m
-CONFIG_DVB_LGDT3305=m
-CONFIG_DVB_LGDT3306A=m
-CONFIG_DVB_LG2160=m
-CONFIG_DVB_S5H1409=m
-CONFIG_DVB_AU8522=m
-CONFIG_DVB_AU8522_DTV=m
-CONFIG_DVB_AU8522_V4L=m
-CONFIG_DVB_S5H1411=m
-
-#
-# ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_S921=m
-CONFIG_DVB_DIB8000=m
-CONFIG_DVB_MB86A20S=m
-
-#
-# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_TC90522=m
-CONFIG_DVB_MN88443X=m
-
-#
-# Digital terrestrial only tuners/PLL
-#
-CONFIG_DVB_PLL=m
-CONFIG_DVB_TUNER_DIB0070=m
-CONFIG_DVB_TUNER_DIB0090=m
-
-#
-# SEC control devices for DVB-S
-#
-CONFIG_DVB_DRX39XYJ=m
-CONFIG_DVB_LNBH25=m
-CONFIG_DVB_LNBH29=m
-CONFIG_DVB_LNBP21=m
-CONFIG_DVB_LNBP22=m
-CONFIG_DVB_ISL6405=m
-CONFIG_DVB_ISL6421=m
-CONFIG_DVB_ISL6422=m
-CONFIG_DVB_ISL6423=m
-CONFIG_DVB_A8293=m
-CONFIG_DVB_LGS8GL5=m
-CONFIG_DVB_LGS8GXX=m
-CONFIG_DVB_ATBM8830=m
-CONFIG_DVB_TDA665x=m
-CONFIG_DVB_IX2505V=m
-CONFIG_DVB_M88RS2000=m
-CONFIG_DVB_AF9033=m
-CONFIG_DVB_TAS2101=m
-CONFIG_DVB_HORUS3A=m
-CONFIG_DVB_ASCOT2E=m
-CONFIG_DVB_HELENE=m
-
-#
-# Common Interface (EN50221) controller drivers
-#
-CONFIG_DVB_CXD2099=m
-CONFIG_DVB_SP2=m
-# end of Customise DVB Frontends
-# end of Media ancillary drivers
-
-#
-# Graphics support
-#
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-# CONFIG_TEGRA_HOST1X is not set
-CONFIG_IMX_IPUV3_CORE=m
-CONFIG_BOOTSPLASH=y
-CONFIG_DRM=m
-CONFIG_DRM_MIPI_DBI=m
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_DP_AUX_CHARDEV=y
-# CONFIG_DRM_DEBUG_MM is not set
-# CONFIG_DRM_DEBUG_SELFTEST is not set
-CONFIG_DRM_KMS_HELPER=m
-CONFIG_DRM_KMS_FB_HELPER=y
-# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
-# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
-# CONFIG_DRM_DP_CEC is not set
-CONFIG_DRM_TTM=m
-CONFIG_DRM_TTM_DMA_PAGE_POOL=y
-CONFIG_DRM_VRAM_HELPER=m
-CONFIG_DRM_TTM_HELPER=m
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-CONFIG_DRM_VM=y
-CONFIG_DRM_SCHED=m
-
-#
-# I2C encoder or helper chips
-#
-CONFIG_DRM_I2C_CH7006=m
-CONFIG_DRM_I2C_SIL164=m
-CONFIG_DRM_I2C_NXP_TDA998X=m
-CONFIG_DRM_I2C_NXP_TDA9950=m
-# end of I2C encoder or helper chips
-
-#
-# ARM devices
-#
-# CONFIG_DRM_HDLCD is not set
-# CONFIG_DRM_MALI_DISPLAY is not set
-# CONFIG_DRM_KOMEDA is not set
-# end of ARM devices
-
-CONFIG_DRM_RADEON=m
-# CONFIG_DRM_RADEON_USERPTR is not set
-CONFIG_DRM_AMDGPU=m
-CONFIG_DRM_AMDGPU_SI=y
-CONFIG_DRM_AMDGPU_CIK=y
-# CONFIG_DRM_AMDGPU_USERPTR is not set
-# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set
-
-#
-# ACP (Audio CoProcessor) Configuration
-#
-CONFIG_DRM_AMD_ACP=y
-# end of ACP (Audio CoProcessor) Configuration
-
-#
-# Display Engine Configuration
-#
-CONFIG_DRM_AMD_DC=y
-CONFIG_DRM_AMD_DC_HDCP=y
-CONFIG_DRM_AMD_DC_SI=y
-# CONFIG_DEBUG_KERNEL_DC is not set
-# end of Display Engine Configuration
-
-CONFIG_DRM_NOUVEAU=m
-CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT=y
-CONFIG_NOUVEAU_PLATFORM_DRIVER=y
-CONFIG_NOUVEAU_DEBUG=5
-CONFIG_NOUVEAU_DEBUG_DEFAULT=3
-# CONFIG_NOUVEAU_DEBUG_MMU is not set
-# CONFIG_NOUVEAU_DEBUG_PUSH is not set
-# CONFIG_DRM_NOUVEAU_BACKLIGHT is not set
-CONFIG_DRM_VGEM=m
-CONFIG_DRM_VKMS=m
-CONFIG_DRM_EXYNOS=m
-
-#
-# CRTCs
-#
-CONFIG_DRM_EXYNOS_FIMD=y
-CONFIG_DRM_EXYNOS5433_DECON=y
-CONFIG_DRM_EXYNOS7_DECON=y
-CONFIG_DRM_EXYNOS_MIXER=y
-CONFIG_DRM_EXYNOS_VIDI=y
-
-#
-# Encoders and Bridges
-#
-CONFIG_DRM_EXYNOS_DPI=y
-CONFIG_DRM_EXYNOS_DSI=y
-CONFIG_DRM_EXYNOS_DP=y
-CONFIG_DRM_EXYNOS_HDMI=y
-CONFIG_DRM_EXYNOS_MIC=y
-
-#
-# Sub-drivers
-#
-CONFIG_DRM_EXYNOS_G2D=y
-CONFIG_DRM_EXYNOS_IPP=y
-CONFIG_DRM_EXYNOS_FIMC=y
-CONFIG_DRM_EXYNOS_ROTATOR=y
-CONFIG_DRM_EXYNOS_SCALER=y
-CONFIG_DRM_EXYNOS_GSC=y
-CONFIG_DRM_UDL=m
-CONFIG_DRM_AST=m
-CONFIG_DRM_MGAG200=m
-CONFIG_DRM_ARMADA=m
-CONFIG_DRM_ATMEL_HLCDC=m
-# CONFIG_DRM_RCAR_DU is not set
-CONFIG_DRM_RCAR_USE_CMM=y
-CONFIG_DRM_RCAR_DW_HDMI=m
-CONFIG_DRM_RCAR_LVDS=m
-# CONFIG_DRM_SUN4I is not set
-CONFIG_DRM_OMAP=m
-CONFIG_OMAP2_DSS_INIT=y
-CONFIG_OMAP_DSS_BASE=m
-CONFIG_OMAP2_DSS=m
-# CONFIG_OMAP2_DSS_DEBUG is not set
-# CONFIG_OMAP2_DSS_DEBUGFS is not set
-CONFIG_OMAP2_DSS_DPI=y
-CONFIG_OMAP2_DSS_VENC=y
-CONFIG_OMAP2_DSS_HDMI_COMMON=y
-CONFIG_OMAP4_DSS_HDMI=y
-CONFIG_OMAP4_DSS_HDMI_CEC=y
-CONFIG_OMAP5_DSS_HDMI=y
-CONFIG_OMAP2_DSS_SDI=y
-CONFIG_OMAP2_DSS_DSI=y
-CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
-CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y
-
-#
-# OMAPDRM External Display Device Drivers
-#
-CONFIG_DRM_OMAP_PANEL_DSI_CM=m
-# end of OMAPDRM External Display Device Drivers
-
-CONFIG_DRM_TILCDC=m
-CONFIG_DRM_QXL=m
-CONFIG_DRM_BOCHS=m
-CONFIG_DRM_VIRTIO_GPU=m
-# CONFIG_DRM_MSM is not set
-CONFIG_DRM_FSL_DCU=m
-# CONFIG_DRM_TEGRA is not set
-CONFIG_DRM_STM=m
-CONFIG_DRM_STM_DSI=m
-CONFIG_DRM_PANEL=y
-
-#
-# Display Panels
-#
-CONFIG_DRM_PANEL_ABT_Y030XX067A=m
-CONFIG_DRM_PANEL_ARM_VERSATILE=m
-CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
-CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
-CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
-CONFIG_DRM_PANEL_DSI_CM=m
-CONFIG_DRM_PANEL_LVDS=m
-CONFIG_DRM_PANEL_SIMPLE=m
-CONFIG_DRM_PANEL_ELIDA_KD35T133=m
-CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
-CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
-CONFIG_DRM_PANEL_ILITEK_IL9322=m
-CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
-CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
-CONFIG_DRM_PANEL_JDI_LT070ME05000=m
-CONFIG_DRM_PANEL_KHADAS_TS050=m
-CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
-CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
-CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
-CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
-CONFIG_DRM_PANEL_LG_LB035Q02=m
-CONFIG_DRM_PANEL_LG_LG4573=m
-CONFIG_DRM_PANEL_NEC_NL8048HL11=m
-CONFIG_DRM_PANEL_NOVATEK_NT35510=m
-CONFIG_DRM_PANEL_NOVATEK_NT35560=m
-CONFIG_DRM_PANEL_NOVATEK_NT39016=m
-CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
-CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
-CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
-CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
-CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
-CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
-CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
-CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
-CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
-CONFIG_DRM_PANEL_RONBO_RB070D30=m
-CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
-CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
-CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
-CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
-CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
-CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
-CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
-CONFIG_DRM_PANEL_SITRONIX_ST7701=m
-CONFIG_DRM_PANEL_SITRONIX_ST7703=m
-CONFIG_DRM_PANEL_SITRONIX_ST7789V=m
-CONFIG_DRM_PANEL_SONY_ACX424AKP=m
-CONFIG_DRM_PANEL_SONY_ACX565AKM=m
-CONFIG_DRM_PANEL_TDO_TL070WSH30=m
-CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
-CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
-CONFIG_DRM_PANEL_TPO_TPG110=m
-CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
-CONFIG_DRM_PANEL_VISIONOX_RM69299=m
-CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
-# end of Display Panels
-
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_PANEL_BRIDGE=y
-
-#
-# Display Interface Bridges
-#
-CONFIG_DRM_CDNS_DSI=m
-CONFIG_DRM_CHIPONE_ICN6211=m
-CONFIG_DRM_CHRONTEL_CH7033=m
-CONFIG_DRM_CROS_EC_ANX7688=m
-CONFIG_DRM_DISPLAY_CONNECTOR=m
-CONFIG_DRM_ITE_IT6505=m
-CONFIG_DRM_LONTIUM_LT8912B=m
-CONFIG_DRM_LONTIUM_LT9611=m
-CONFIG_DRM_LONTIUM_LT9611UXC=m
-CONFIG_DRM_ITE_IT66121=m
-CONFIG_DRM_LVDS_CODEC=m
-CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m
-CONFIG_DRM_NWL_MIPI_DSI=m
-CONFIG_DRM_NXP_PTN3460=m
-CONFIG_DRM_PARADE_PS8622=m
-CONFIG_DRM_PARADE_PS8640=m
-CONFIG_DRM_SIL_SII8620=m
-CONFIG_DRM_SII902X=m
-CONFIG_DRM_SII9234=m
-CONFIG_DRM_SIMPLE_BRIDGE=m
-CONFIG_DRM_THINE_THC63LVD1024=m
-CONFIG_DRM_TOSHIBA_TC358762=m
-CONFIG_DRM_TOSHIBA_TC358764=m
-CONFIG_DRM_TOSHIBA_TC358767=m
-CONFIG_DRM_TOSHIBA_TC358768=m
-CONFIG_DRM_TOSHIBA_TC358775=m
-CONFIG_DRM_TI_TFP410=m
-CONFIG_DRM_TI_SN65DSI83=m
-CONFIG_DRM_TI_SN65DSI86=m
-CONFIG_DRM_TI_TPD12S015=m
-CONFIG_DRM_ANALOGIX_ANX6345=m
-CONFIG_DRM_ANALOGIX_ANX78XX=m
-CONFIG_DRM_ANALOGIX_ANX7625=m
-CONFIG_DRM_ANALOGIX_DP=m
-CONFIG_DRM_I2C_ADV7511=m
-CONFIG_DRM_I2C_ADV7511_AUDIO=y
-CONFIG_DRM_I2C_ADV7511_CEC=y
-CONFIG_DRM_CDNS_MHDP8546=m
-CONFIG_DRM_DW_HDMI=m
-CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
-CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
-CONFIG_DRM_DW_HDMI_CEC=m
-CONFIG_DRM_DW_MIPI_DSI=m
-# end of Display Interface Bridges
-
-CONFIG_DRM_STI=m
-CONFIG_DRM_IMX=m
-CONFIG_DRM_IMX_PARALLEL_DISPLAY=m
-CONFIG_DRM_IMX_TVE=m
-CONFIG_DRM_IMX_LDB=m
-CONFIG_DRM_IMX_HDMI=m
-# CONFIG_DRM_V3D is not set
-# CONFIG_DRM_VC4 is not set
-CONFIG_DRM_ETNAVIV=m
-CONFIG_DRM_ETNAVIV_THERMAL=y
-CONFIG_DRM_ARCPGU=m
-# CONFIG_DRM_MEDIATEK is not set
-CONFIG_DRM_MEDIATEK_DP=m
-# CONFIG_DRM_ZTE is not set
-CONFIG_DRM_MXS=y
-CONFIG_DRM_MXSFB=m
-# CONFIG_DRM_MESON is not set
-CONFIG_DRM_CIRRUS_QEMU=m
-CONFIG_DRM_GM12U320=m
-CONFIG_DRM_PANEL_MIPI_DBI=m
-CONFIG_DRM_SIMPLEDRM=y
-CONFIG_TINYDRM_HX8357D=m
-CONFIG_TINYDRM_ILI9225=m
-CONFIG_TINYDRM_ILI9341=m
-CONFIG_TINYDRM_ILI9486=m
-CONFIG_TINYDRM_MI0283QT=m
-CONFIG_TINYDRM_REPAPER=m
-CONFIG_TINYDRM_ST7586=m
-CONFIG_TINYDRM_ST7735R=m
-CONFIG_DRM_PL111=m
-CONFIG_DRM_TVE200=m
-CONFIG_DRM_LIMA=m
-CONFIG_DRM_PANFROST=m
-# CONFIG_DRM_ASPEED_GFX is not set
-CONFIG_DRM_MCDE=m
-CONFIG_DRM_TIDSS=m
-CONFIG_DRM_GUD=m
-CONFIG_DRM_SSD130X=m
-CONFIG_DRM_SSD130X_I2C=m
-CONFIG_DRM_SPRD=m
-CONFIG_DRM_HYPERV=m
-CONFIG_DRM_LEGACY=y
-# CONFIG_DRM_TDFX is not set
-# CONFIG_DRM_R128 is not set
-# CONFIG_DRM_MGA is not set
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-CONFIG_DRM_EXPORT_FOR_TESTS=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m
-CONFIG_DRM_LIB_RANDOM=y
-
-#
-# Frame buffer Devices
-#
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_NOTIFY=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_DDC=m
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SYS_FILLRECT=m
-CONFIG_FB_SYS_COPYAREA=m
-CONFIG_FB_SYS_IMAGEBLIT=m
-CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA=y
-CONFIG_FB_FOREIGN_ENDIAN=y
-CONFIG_FB_BOTH_ENDIAN=y
-# CONFIG_FB_BIG_ENDIAN is not set
-# CONFIG_FB_LITTLE_ENDIAN is not set
-CONFIG_FB_SYS_FOPS=m
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SVGALIB=m
-CONFIG_FB_BACKLIGHT=m
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
-
-#
-# Frame buffer hardware drivers
-#
-CONFIG_FB_CIRRUS=m
-CONFIG_FB_PM2=m
-CONFIG_FB_PM2_FIFO_DISCONNECT=y
-# CONFIG_FB_ARMCLCD is not set
-# CONFIG_FB_IMX is not set
-CONFIG_FB_CYBER2000=m
-CONFIG_FB_CYBER2000_DDC=y
-CONFIG_FB_ASILIANT=y
-CONFIG_FB_IMSTT=y
-CONFIG_FB_UVESA=m
-CONFIG_FB_EFI=y
-CONFIG_FB_OPENCORES=m
-CONFIG_FB_S1D13XXX=m
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-# CONFIG_FB_I740 is not set
-# CONFIG_FB_MATROX is not set
-CONFIG_FB_RADEON=m
-CONFIG_FB_RADEON_I2C=y
-CONFIG_FB_RADEON_BACKLIGHT=y
-# CONFIG_FB_RADEON_DEBUG is not set
-CONFIG_FB_ATY128=m
-CONFIG_FB_ATY128_BACKLIGHT=y
-# CONFIG_FB_ATY is not set
-# CONFIG_FB_S3 is not set
-# CONFIG_FB_SAVAGE is not set
-# CONFIG_FB_SIS is not set
-CONFIG_FB_NEOMAGIC=m
-CONFIG_FB_KYRO=m
-# CONFIG_FB_3DFX is not set
-# CONFIG_FB_VOODOO1 is not set
-CONFIG_FB_VT8623=m
-CONFIG_FB_TRIDENT=m
-CONFIG_FB_ARK=m
-CONFIG_FB_PM3=m
-CONFIG_FB_CARMINE=m
-CONFIG_FB_CARMINE_DRAM_EVAL=y
-# CONFIG_CARMINE_DRAM_CUSTOM is not set
-# CONFIG_FB_VT8500 is not set
-# CONFIG_FB_WM8505 is not set
-# CONFIG_FB_SH_MOBILE_LCDC is not set
-CONFIG_FB_TMIO=m
-CONFIG_FB_TMIO_ACCELL=y
-CONFIG_FB_SM501=m
-CONFIG_FB_SMSCUFX=m
-CONFIG_FB_UDL=m
-CONFIG_FB_IBM_GXT4500=m
-# CONFIG_FB_XILINX is not set
-# CONFIG_FB_DA8XX is not set
-# CONFIG_FB_VIRTUAL is not set
-CONFIG_FB_METRONOME=m
-CONFIG_FB_MB862XX=m
-CONFIG_FB_MB862XX_PCI_GDC=y
-CONFIG_FB_MB862XX_I2C=y
-CONFIG_FB_MX3=y
-CONFIG_FB_SIMPLE=y
-CONFIG_FB_SSD1307=m
-CONFIG_FB_SM712=m
-# end of Frame buffer Devices
-
-#
-# Backlight & LCD device support
-#
-CONFIG_LCD_CLASS_DEVICE=m
-CONFIG_LCD_L4F00242T03=m
-CONFIG_LCD_LMS283GF05=m
-CONFIG_LCD_LTV350QV=m
-CONFIG_LCD_ILI922X=m
-CONFIG_LCD_ILI9320=m
-CONFIG_LCD_TDO24M=m
-CONFIG_LCD_VGG2432A4=m
-CONFIG_LCD_PLATFORM=m
-CONFIG_LCD_AMS369FG06=m
-CONFIG_LCD_LMS501KF03=m
-CONFIG_LCD_HX8357=m
-CONFIG_LCD_OTM3225A=m
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_KTD253=m
-CONFIG_BACKLIGHT_LM3533=m
-CONFIG_BACKLIGHT_PWM=m
-CONFIG_BACKLIGHT_MT6370=m
-CONFIG_BACKLIGHT_DA9052=m
-CONFIG_BACKLIGHT_MT6370=m
-CONFIG_BACKLIGHT_QCOM_WLED=m
-CONFIG_BACKLIGHT_RT4831=m
-CONFIG_BACKLIGHT_WM831X=m
-CONFIG_BACKLIGHT_ADP8860=m
-CONFIG_BACKLIGHT_ADP8870=m
-CONFIG_BACKLIGHT_PCF50633=m
-CONFIG_BACKLIGHT_LM3630A=m
-CONFIG_BACKLIGHT_LM3639=m
-CONFIG_BACKLIGHT_LP855X=m
-# CONFIG_BACKLIGHT_PANDORA is not set
-CONFIG_BACKLIGHT_SKY81452=m
-CONFIG_BACKLIGHT_TPS65217=m
-CONFIG_BACKLIGHT_GPIO=m
-CONFIG_BACKLIGHT_LV5207LP=m
-CONFIG_BACKLIGHT_BD6107=m
-CONFIG_BACKLIGHT_ARCXCNN=m
-CONFIG_BACKLIGHT_RAVE_SP=m
-CONFIG_BACKLIGHT_LED=m
-# end of Backlight & LCD device support
-
-CONFIG_VGASTATE=m
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_HDMI=y
-
-#
-# Console display driver support
-#
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
-# end of Console display driver support
-
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# end of Graphics support
-
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_PCM_ELD=y
-CONFIG_SND_PCM_IEC958=y
-CONFIG_SND_DMAENGINE_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_SEQ_DEVICE=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_PCM_TIMER=y
-CONFIG_SND_HRTIMER=m
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_MAX_CARDS=32
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_PROC_FS=y
-CONFIG_SND_VERBOSE_PROCFS=y
-CONFIG_SND_CTL_FAST_LOOKUP=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_CTL_INPUT_VALIDATION=y
-CONFIG_SND_VMASTER=y
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_SEQUENCER_OSS=m
-CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
-CONFIG_SND_SEQ_MIDI_EVENT=m
-CONFIG_SND_SEQ_MIDI=m
-CONFIG_SND_SEQ_MIDI_EMUL=m
-CONFIG_SND_SEQ_VIRMIDI=m
-CONFIG_SND_MPU401_UART=m
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_OPL3_LIB_SEQ=m
-CONFIG_SND_VX_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DRIVERS=y
-CONFIG_SND_DUMMY=m
-CONFIG_SND_ALOOP=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_MTS64=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_PORTMAN2X4=m
-CONFIG_SND_AC97_POWER_SAVE=y
-CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
-CONFIG_SND_PCI=y
-CONFIG_SND_AD1889=m
-# CONFIG_SND_ALS300 is not set
-# CONFIG_SND_ALI5451 is not set
-CONFIG_SND_ATIIXP=m
-CONFIG_SND_ATIIXP_MODEM=m
-CONFIG_SND_AU8810=m
-CONFIG_SND_AU8820=m
-CONFIG_SND_AU8830=m
-CONFIG_SND_AW2=m
-# CONFIG_SND_AZT3328 is not set
-CONFIG_SND_BT87X=m
-CONFIG_SND_BT87X_OVERCLOCK=y
-CONFIG_SND_CA0106=m
-CONFIG_SND_CMIPCI=m
-CONFIG_SND_OXYGEN_LIB=m
-CONFIG_SND_OXYGEN=m
-CONFIG_SND_CS4281=m
-CONFIG_SND_CS46XX=m
-CONFIG_SND_CS46XX_NEW_DSP=y
-CONFIG_SND_CTXFI=m
-CONFIG_SND_DARLA20=m
-CONFIG_SND_GINA20=m
-CONFIG_SND_LAYLA20=m
-CONFIG_SND_DARLA24=m
-CONFIG_SND_GINA24=m
-CONFIG_SND_LAYLA24=m
-CONFIG_SND_MONA=m
-CONFIG_SND_MIA=m
-CONFIG_SND_ECHO3G=m
-CONFIG_SND_INDIGO=m
-CONFIG_SND_INDIGOIO=m
-CONFIG_SND_INDIGODJ=m
-CONFIG_SND_INDIGOIOX=m
-CONFIG_SND_INDIGODJX=m
-# CONFIG_SND_EMU10K1 is not set
-# CONFIG_SND_EMU10K1X is not set
-CONFIG_SND_ENS1370=m
-CONFIG_SND_ENS1371=m
-# CONFIG_SND_ES1938 is not set
-# CONFIG_SND_ES1968 is not set
-CONFIG_SND_FM801=m
-CONFIG_SND_FM801_TEA575X_BOOL=y
-CONFIG_SND_HDSP=m
-CONFIG_SND_HDSPM=m
-# CONFIG_SND_ICE1712 is not set
-CONFIG_SND_ICE1724=m
-CONFIG_SND_INTEL8X0=m
-CONFIG_SND_INTEL8X0M=m
-CONFIG_SND_KORG1212=m
-CONFIG_SND_LOLA=m
-# CONFIG_SND_MAESTRO3 is not set
-CONFIG_SND_MIXART=m
-CONFIG_SND_NM256=m
-CONFIG_SND_PCXHR=m
-CONFIG_SND_RIPTIDE=m
-CONFIG_SND_RME32=m
-CONFIG_SND_RME96=m
-CONFIG_SND_RME9652=m
-# CONFIG_SND_SONICVIBES is not set
-# CONFIG_SND_TRIDENT is not set
-CONFIG_SND_VIA82XX=m
-CONFIG_SND_VIA82XX_MODEM=m
-CONFIG_SND_VIRTUOSO=m
-CONFIG_SND_VX222=m
-CONFIG_SND_YMFPCI=m
-
-#
-# HD-Audio
-#
-CONFIG_SND_HDA=m
-CONFIG_SND_HDA_GENERIC_LEDS=y
-CONFIG_SND_HDA_INTEL=m
-# CONFIG_SND_HDA_TEGRA is not set
-CONFIG_SND_HDA_HWDEP=y
-CONFIG_SND_HDA_RECONFIG=y
-CONFIG_SND_HDA_INPUT_BEEP=y
-CONFIG_SND_HDA_INPUT_BEEP_MODE=1
-CONFIG_SND_HDA_PATCH_LOADER=y
-CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m
-CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m
-CONFIG_SND_HDA_CODEC_REALTEK=m
-CONFIG_SND_HDA_CODEC_ANALOG=m
-CONFIG_SND_HDA_CODEC_SIGMATEL=m
-CONFIG_SND_HDA_CODEC_VIA=m
-CONFIG_SND_HDA_CODEC_HDMI=m
-CONFIG_SND_HDA_CODEC_CIRRUS=m
-CONFIG_SND_HDA_CODEC_CONEXANT=m
-CONFIG_SND_HDA_CODEC_CA0110=m
-CONFIG_SND_HDA_CODEC_CA0132=m
-CONFIG_SND_HDA_CODEC_CA0132_DSP=y
-CONFIG_SND_HDA_CODEC_CMEDIA=m
-CONFIG_SND_HDA_CODEC_SI3054=m
-CONFIG_SND_HDA_GENERIC=m
-CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
-# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
-# end of HD-Audio
-
-CONFIG_SND_HDA_CORE=m
-CONFIG_SND_HDA_DSP_LOADER=y
-CONFIG_SND_HDA_COMPONENT=y
-CONFIG_SND_HDA_PREALLOC_SIZE=2048
-CONFIG_SND_VIRTIO=m
-CONFIG_SND_INTEL_DSP_CONFIG=m
-CONFIG_SND_ARM=y
-# CONFIG_SND_ARMAACI is not set
-
-#
-# Atmel devices (AT91)
-#
-# CONFIG_SND_ATMEL_AC97C is not set
-# end of Atmel devices (AT91)
-
-CONFIG_SND_SPI=y
-CONFIG_SND_USB=y
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
-CONFIG_SND_USB_UA101=m
-CONFIG_SND_USB_CAIAQ=m
-CONFIG_SND_USB_CAIAQ_INPUT=y
-CONFIG_SND_USB_6FIRE=m
-CONFIG_SND_USB_HIFACE=m
-CONFIG_SND_BCD2000=m
-CONFIG_SND_USB_LINE6=m
-CONFIG_SND_USB_POD=m
-CONFIG_SND_USB_PODHD=m
-CONFIG_SND_USB_TONEPORT=m
-CONFIG_SND_USB_VARIAX=m
-CONFIG_SND_FIREWIRE=y
-CONFIG_SND_FIREWIRE_LIB=m
-CONFIG_SND_DICE=m
-CONFIG_SND_OXFW=m
-CONFIG_SND_ISIGHT=m
-CONFIG_SND_FIREWORKS=m
-CONFIG_SND_BEBOB=m
-CONFIG_SND_FIREWIRE_DIGI00X=m
-CONFIG_SND_FIREWIRE_TASCAM=m
-CONFIG_SND_FIREWIRE_MOTU=m
-CONFIG_SND_FIREFACE=m
-CONFIG_SND_PCMCIA=y
-CONFIG_SND_VXPOCKET=m
-CONFIG_SND_PDAUDIOCF=m
-CONFIG_SND_SOC=m
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_TOPOLOGY=y
-# CONFIG_SND_SOC_ADI is not set
-CONFIG_SND_SOC_AMD_ACP=m
-CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m
-CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m
-CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
-CONFIG_SND_ATMEL_SOC=m
-# CONFIG_SND_ATMEL_SOC_CLASSD is not set
-# CONFIG_SND_ATMEL_SOC_PDMIC is not set
-# CONFIG_SND_ATMEL_SOC_I2S is not set
-CONFIG_SND_SOC_MIKROE_PROTO=m
-# CONFIG_SND_MCHP_SOC_I2S_MCC is not set
-CONFIG_SND_MCHP_SOC_SPDIFTX=m
-CONFIG_SND_MCHP_SOC_SPDIFRX=m
-CONFIG_SND_MCHP_SOC_PDMC=m
-CONFIG_SND_BCM63XX_I2S_WHISTLER=m
-CONFIG_SND_DESIGNWARE_I2S=m
-CONFIG_SND_DESIGNWARE_PCM=y
-
-#
-# SoC Audio for Freescale CPUs
-#
-
-#
-# Common SoC Audio options for Freescale CPUs:
-#
-CONFIG_SND_SOC_FSL_ASRC=m
-CONFIG_SND_SOC_FSL_SAI=m
-CONFIG_SND_SOC_FSL_MQS=m
-CONFIG_SND_SOC_FSL_AUDMIX=m
-CONFIG_SND_SOC_FSL_SSI=m
-CONFIG_SND_SOC_FSL_SPDIF=m
-CONFIG_SND_SOC_FSL_ESAI=m
-CONFIG_SND_SOC_FSL_MICFIL=m
-CONFIG_SND_SOC_FSL_EASRC=m
-CONFIG_SND_SOC_FSL_XCVR=m
-CONFIG_SND_SOC_FSL_AUD2HTX=m
-CONFIG_SND_SOC_FSL_RPMSG=m
-CONFIG_SND_SOC_IMX_AUDMUX=m
-CONFIG_SND_SOC_IMX_CARD=m
-# CONFIG_SND_IMX_SOC is not set
-# end of SoC Audio for Freescale CPUs
-
-CONFIG_SND_I2S_HI6210_I2S=m
-# CONFIG_SND_KIRKWOOD_SOC is not set
-CONFIG_SND_SOC_IMG=y
-CONFIG_SND_SOC_IMG_I2S_IN=m
-CONFIG_SND_SOC_IMG_I2S_OUT=m
-CONFIG_SND_SOC_IMG_PARALLEL_OUT=m
-CONFIG_SND_SOC_IMG_SPDIF_IN=m
-CONFIG_SND_SOC_IMG_SPDIF_OUT=m
-CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m
-# CONFIG_SND_SOC_MT2701 is not set
-# CONFIG_SND_SOC_MT6797 is not set
-# CONFIG_SND_SOC_MT8173 is not set
-# CONFIG_SND_SOC_MT8183 is not set
-CONFIG_SND_SOC_MT8186=m
-CONFIG_SND_SOC_MT8186_MT6366_DA7219_MAX98357=m
-CONFIG_SND_SOC_MT8186_MT6366_RT1019_RT5682S=m
-CONFIG_SND_SOC_MTK_BTCVSD=m
-CONFIG_SND_SOC_MT8192=m
-CONFIG_PINCTRL_MT8195=y
-CONFIG_PINCTRL_MT8365=y
-CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682=m
-
-#
-# ASoC support for Amlogic platforms
-#
-# CONFIG_SND_MESON_AIU is not set
-# CONFIG_SND_MESON_AXG_FRDDR is not set
-# CONFIG_SND_MESON_AXG_TODDR is not set
-# CONFIG_SND_MESON_AXG_TDMIN is not set
-# CONFIG_SND_MESON_AXG_TDMOUT is not set
-# CONFIG_SND_MESON_AXG_SOUND_CARD is not set
-# CONFIG_SND_MESON_AXG_SPDIFOUT is not set
-# CONFIG_SND_MESON_AXG_SPDIFIN is not set
-# CONFIG_SND_MESON_AXG_PDM is not set
-# CONFIG_SND_MESON_GX_SOUND_CARD is not set
-# CONFIG_SND_MESON_G12A_TOACODEC is not set
-# CONFIG_SND_MESON_G12A_TOHDMITX is not set
-# CONFIG_SND_SOC_MESON_T9015 is not set
-# end of ASoC support for Amlogic platforms
-
-# CONFIG_SND_PXA_SOC_SSP is not set
-# CONFIG_SND_MMP_SOC_SSPA is not set
-# CONFIG_SND_PXA910_SOC is not set
-# CONFIG_SND_SOC_QCOM is not set
-# CONFIG_SND_SOC_ROCKCHIP is not set
-# CONFIG_SND_SOC_SAMSUNG is not set
-
-#
-# SoC Audio support for Renesas SoCs
-#
-# CONFIG_SND_SOC_SH4_FSI is not set
-# CONFIG_SND_SOC_RCAR is not set
-# end of SoC Audio support for Renesas SoCs
-
-# CONFIG_SND_SOC_SIRF is not set
-CONFIG_SND_SOC_SOF_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_PCI=m
-CONFIG_SND_SOC_SOF_OF=m
-# CONFIG_SND_SOC_SOF_DEBUG_PROBES is not set
-# CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT is not set
-CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m
-CONFIG_SND_SOC_SOF_AMD_RENOIR=m
-CONFIG_SND_SOC_SOF=m
-# CONFIG_SND_SOC_STI is not set
-
-#
-# STMicroelectronics STM32 SOC audio support
-#
-# CONFIG_SND_SOC_STM32_SAI is not set
-# CONFIG_SND_SOC_STM32_I2S is not set
-# CONFIG_SND_SOC_STM32_SPDIFRX is not set
-# end of STMicroelectronics STM32 SOC audio support
-
-#
-# Allwinner SoC Audio support
-#
-# CONFIG_SND_SUN4I_CODEC is not set
-# CONFIG_SND_SUN8I_CODEC is not set
-# CONFIG_SND_SUN8I_CODEC_ANALOG is not set
-# CONFIG_SND_SUN4I_I2S is not set
-# CONFIG_SND_SUN4I_SPDIF is not set
-CONFIG_SND_SUN50I_DMIC=m
-# end of Allwinner SoC Audio support
-
-#
-# Audio support for Texas Instruments SoCs
-#
-
-#
-# Texas Instruments DAI support for:
-#
-# CONFIG_SND_SOC_DAVINCI_MCASP is not set
-# CONFIG_SND_SOC_OMAP_DMIC is not set
-# CONFIG_SND_SOC_OMAP_MCBSP is not set
-# CONFIG_SND_SOC_OMAP_MCPDM is not set
-
-#
-# Audio support for boards with Texas Instruments SoCs
-#
-# CONFIG_SND_SOC_NOKIA_RX51 is not set
-# CONFIG_SND_SOC_OMAP3_PANDORA is not set
-# CONFIG_SND_SOC_OMAP3_TWL4030 is not set
-# CONFIG_SND_SOC_OMAP_HDMI is not set
-# end of Audio support for Texas Instruments SoCs
-
-# CONFIG_SND_SOC_UNIPHIER is not set
-# CONFIG_SND_SOC_UX500 is not set
-CONFIG_SND_SOC_XILINX_I2S=m
-CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
-CONFIG_SND_SOC_XILINX_SPDIF=m
-CONFIG_SND_SOC_XTFPGA_I2S=m
-# CONFIG_ZX_SPDIF is not set
-# CONFIG_ZX_I2S is not set
-CONFIG_ZX_TDM=m
-CONFIG_SND_SOC_I2C_AND_SPI=m
-
-#
-# CODEC drivers
-#
-CONFIG_SND_SOC_AC97_CODEC=m
-CONFIG_SND_SOC_ADAU1372_I2C=m
-CONFIG_SND_SOC_ADAU1372_SPI=m
-CONFIG_SND_SOC_ADAU_UTILS=m
-CONFIG_SND_SOC_ADAU1701=m
-CONFIG_SND_SOC_ADAU17X1=m
-CONFIG_SND_SOC_ADAU1761=m
-CONFIG_SND_SOC_ADAU1761_I2C=m
-CONFIG_SND_SOC_ADAU1761_SPI=m
-CONFIG_SND_SOC_ADAU7002=m
-CONFIG_SND_SOC_ADAU7118=m
-CONFIG_SND_SOC_ADAU7118_HW=m
-CONFIG_SND_SOC_ADAU7118_I2C=m
-CONFIG_SND_SOC_AK4104=m
-CONFIG_SND_SOC_AK4118=m
-CONFIG_SND_SOC_AK4458=m
-CONFIG_SND_SOC_AK4554=m
-CONFIG_SND_SOC_AK4613=m
-CONFIG_SND_SOC_AK4642=m
-CONFIG_SND_SOC_AK5386=m
-CONFIG_SND_SOC_AK5558=m
-CONFIG_SND_SOC_ALC5623=m
-CONFIG_SND_SOC_AW8738=m
-CONFIG_SND_SOC_BD28623=m
-CONFIG_SND_SOC_BT_SCO=m
-CONFIG_SND_SOC_CPCAP=m
-CONFIG_SND_SOC_CROS_EC_CODEC=m
-CONFIG_SND_SOC_CS35L32=m
-CONFIG_SND_SOC_CS35L33=m
-CONFIG_SND_SOC_CS35L34=m
-CONFIG_SND_SOC_CS35L35=m
-CONFIG_SND_SOC_CS35L36=m
-CONFIG_SND_SOC_CS42L42=m
-CONFIG_SND_SOC_CS42L51=m
-CONFIG_SND_SOC_CS42L51_I2C=m
-CONFIG_SND_SOC_CS42L52=m
-CONFIG_SND_SOC_CS42L56=m
-CONFIG_SND_SOC_CS42L73=m
-CONFIG_SND_SOC_CS42L83=m
-CONFIG_SND_SOC_CS4234=m
-CONFIG_SND_SOC_CS4265=m
-CONFIG_SND_SOC_CS4270=m
-CONFIG_SND_SOC_CS4271=m
-CONFIG_SND_SOC_CS4271_I2C=m
-CONFIG_SND_SOC_CS4271_SPI=m
-CONFIG_SND_SOC_CS42XX8=m
-CONFIG_SND_SOC_CS42XX8_I2C=m
-CONFIG_SND_SOC_CS43130=m
-CONFIG_SND_SOC_CS4341=m
-CONFIG_SND_SOC_CS4349=m
-CONFIG_SND_SOC_CS53L30=m
-CONFIG_SND_SOC_CX2072X=m
-CONFIG_SND_SOC_DA7213=m
-CONFIG_SND_SOC_DA7219=m
-CONFIG_SND_SOC_DMIC=m
-CONFIG_SND_SOC_HDMI_CODEC=m
-CONFIG_SND_SOC_ES7134=m
-CONFIG_SND_SOC_ES7241=m
-CONFIG_SND_SOC_ES8316=m
-CONFIG_SND_SOC_ES8326=m
-CONFIG_SND_SOC_ES8328=m
-CONFIG_SND_SOC_ES8328_I2C=m
-CONFIG_SND_SOC_ES8328_SPI=m
-CONFIG_SND_SOC_GTM601=m
-CONFIG_SND_SOC_HDA=m
-CONFIG_SND_SOC_INNO_RK3036=m
-CONFIG_SND_SOC_MAX98088=m
-CONFIG_SND_SOC_MAX98357A=m
-CONFIG_SND_SOC_MAX98504=m
-CONFIG_SND_SOC_MAX9867=m
-CONFIG_SND_SOC_MAX98927=m
-CONFIG_SND_SOC_MAX98373=m
-CONFIG_SND_SOC_MAX98373_I2C=m
-CONFIG_SND_SOC_MAX98373_SDW=m
-CONFIG_SND_SOC_MAX98390=m
-CONFIG_SND_SOC_MAX9860=m
-CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
-CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
-CONFIG_SND_SOC_PCM1681=m
-CONFIG_SND_SOC_PCM1789=m
-CONFIG_SND_SOC_PCM1789_I2C=m
-CONFIG_SND_SOC_PCM179X=m
-CONFIG_SND_SOC_PCM179X_I2C=m
-CONFIG_SND_SOC_PCM179X_SPI=m
-CONFIG_SND_SOC_PCM186X=m
-CONFIG_SND_SOC_PCM186X_I2C=m
-CONFIG_SND_SOC_PCM186X_SPI=m
-CONFIG_SND_SOC_PCM3060=m
-CONFIG_SND_SOC_PCM3060_I2C=m
-CONFIG_SND_SOC_PCM3060_SPI=m
-CONFIG_SND_SOC_PCM3168A=m
-CONFIG_SND_SOC_PCM3168A_I2C=m
-CONFIG_SND_SOC_PCM3168A_SPI=m
-CONFIG_SND_SOC_PCM5102A=m
-CONFIG_SND_SOC_PCM512x=m
-CONFIG_SND_SOC_PCM512x_I2C=m
-CONFIG_SND_SOC_PCM512x_SPI=m
-CONFIG_SND_SOC_RK3328=m
-CONFIG_SND_SOC_RK817=m
-CONFIG_SND_SOC_RL6231=m
-CONFIG_SND_SOC_RT1308_SDW=m
-CONFIG_SND_SOC_RT1316_SDW=m
-CONFIG_SND_SOC_RT5616=m
-CONFIG_SND_SOC_RT5631=m
-CONFIG_SND_SOC_RT5640=m
-CONFIG_SND_SOC_RT5659=m
-CONFIG_SND_SOC_RT5645=m
-CONFIG_SND_SOC_RT5682=m
-CONFIG_SND_SOC_RT5682_SDW=m
-CONFIG_SND_SOC_RT700=m
-CONFIG_SND_SOC_RT700_SDW=m
-CONFIG_SND_SOC_RT711=m
-CONFIG_SND_SOC_RT711_SDW=m
-CONFIG_SND_SOC_RT711_SDCA_SDW=m
-CONFIG_SND_SOC_RT715=m
-CONFIG_SND_SOC_RT715_SDW=m
-CONFIG_SND_SOC_RT715_SDCA_SDW=m
-CONFIG_SND_SOC_SGTL5000=m
-CONFIG_SND_SOC_SI476X=m
-CONFIG_SND_SOC_SIGMADSP=m
-CONFIG_SND_SOC_SIGMADSP_I2C=m
-CONFIG_SND_SOC_SIGMADSP_REGMAP=m
-CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
-CONFIG_SND_SOC_SIMPLE_MUX=m
-CONFIG_SND_SOC_SIRF_AUDIO_CODEC=m
-CONFIG_SND_SOC_SPDIF=m
-CONFIG_SND_SOC_SRC4XXX_I2C=m
-CONFIG_SND_SOC_SSM2305=m
-CONFIG_SND_SOC_SSM2518=m
-CONFIG_SND_SOC_SSM2602=m
-CONFIG_SND_SOC_SSM2602_SPI=m
-CONFIG_SND_SOC_SSM2602_I2C=m
-CONFIG_SND_SOC_SSM4567=m
-CONFIG_SND_SOC_STA32X=m
-CONFIG_SND_SOC_STA350=m
-CONFIG_SND_SOC_STI_SAS=m
-CONFIG_SND_SOC_TAS2552=m
-CONFIG_SND_SOC_TAS2562=m
-CONFIG_SND_SOC_TAS2764=m
-CONFIG_SND_SOC_TAS2770=m
-CONFIG_SND_SOC_TAS2780=m
-CONFIG_SND_SOC_WSA883X=m
-CONFIG_SND_SOC_TAS5086=m
-CONFIG_SND_SOC_TAS571X=m
-CONFIG_SND_SOC_TAS5720=m
-CONFIG_SND_SOC_TAS5805M=m
-CONFIG_SND_SOC_TAS6424=m
-CONFIG_SND_SOC_TDA7419=m
-CONFIG_SND_SOC_TFA9879=m
-CONFIG_SND_SOC_TFA989X=m
-CONFIG_SND_SOC_TLV320AIC23=m
-CONFIG_SND_SOC_TLV320AIC23_I2C=m
-CONFIG_SND_SOC_TLV320AIC23_SPI=m
-CONFIG_SND_SOC_TLV320AIC31XX=m
-CONFIG_SND_SOC_TLV320AIC32X4=m
-CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
-CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
-CONFIG_SND_SOC_TLV320AIC3X_I2C=m
-CONFIG_SND_SOC_TLV320AIC3X_SPI=m
-CONFIG_SND_SOC_TLV320AIC3X=m
-CONFIG_SND_SOC_TLV320ADCX140=m
-CONFIG_SND_SOC_TS3A227E=m
-CONFIG_SND_SOC_TSCS42XX=m
-CONFIG_SND_SOC_TSCS454=m
-CONFIG_SND_SOC_UDA1334=m
-CONFIG_SND_SOC_WCD938X_SDW=m
-CONFIG_SND_SOC_WCD9335=m
-CONFIG_SND_SOC_WCD934X=m
-CONFIG_SND_SOC_WCD938X_SDW=m
-CONFIG_SND_SOC_WM8510=m
-CONFIG_SND_SOC_WM8523=m
-CONFIG_SND_SOC_WM8524=m
-CONFIG_SND_SOC_WM8580=m
-CONFIG_SND_SOC_WM8711=m
-CONFIG_SND_SOC_WM8728=m
-CONFIG_SND_SOC_WM8731=m
-CONFIG_SND_SOC_WM8737=m
-CONFIG_SND_SOC_WM8741=m
-CONFIG_SND_SOC_WM8750=m
-CONFIG_SND_SOC_WM8753=m
-CONFIG_SND_SOC_WM8770=m
-CONFIG_SND_SOC_WM8776=m
-CONFIG_SND_SOC_WM8782=m
-CONFIG_SND_SOC_WM8804=m
-CONFIG_SND_SOC_WM8804_I2C=m
-CONFIG_SND_SOC_WM8804_SPI=m
-CONFIG_SND_SOC_WM8903=m
-CONFIG_SND_SOC_WM8904=m
-CONFIG_SND_SOC_WM8960=m
-CONFIG_SND_SOC_WM8962=m
-CONFIG_SND_SOC_WM8974=m
-CONFIG_SND_SOC_WM8978=m
-CONFIG_SND_SOC_WM8985=m
-CONFIG_SND_SOC_WSA881X=m
-CONFIG_SND_SOC_ZL38060=m
-CONFIG_SND_SOC_ZX_AUD96P22=m
-CONFIG_SND_SOC_MAX9759=m
-CONFIG_SND_SOC_MT6351=m
-CONFIG_SND_SOC_MT6358=m
-CONFIG_SND_SOC_MT6660=m
-CONFIG_SND_SOC_NAU8315=m
-CONFIG_SND_SOC_NAU8540=m
-CONFIG_SND_SOC_NAU8810=m
-CONFIG_SND_SOC_NAU8822=m
-CONFIG_SND_SOC_NAU8824=m
-CONFIG_SND_SOC_TPA6130A2=m
-CONFIG_SND_SOC_LPASS_WSA_MACRO=m
-CONFIG_SND_SOC_LPASS_VA_MACRO=m
-CONFIG_SND_SOC_LPASS_RX_MACRO=m
-CONFIG_SND_SOC_LPASS_TX_MACRO=m
-# end of CODEC drivers
-
-CONFIG_SND_SIMPLE_CARD_UTILS=m
-CONFIG_SND_SIMPLE_CARD=m
-CONFIG_SND_AUDIO_GRAPH_CARD=m
-CONFIG_AC97_BUS=m
-
-#
-# HID support
-#
-CONFIG_HID=m
-CONFIG_HID_BATTERY_STRENGTH=y
-CONFIG_HIDRAW=y
-CONFIG_UHID=m
-CONFIG_HID_GENERIC=m
-
-#
-# Special HID drivers
-#
-CONFIG_HID_A4TECH=m
-CONFIG_HID_ACCUTOUCH=m
-CONFIG_HID_ACRUX=m
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=m
-CONFIG_HID_APPLEIR=m
-CONFIG_HID_ASUS=m
-CONFIG_HID_AUREAL=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_BETOP_FF=m
-CONFIG_HID_BIGBEN_FF=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CORSAIR=m
-CONFIG_HID_COUGAR=m
-CONFIG_HID_MACALLY=m
-CONFIG_HID_PRODIKEYS=m
-CONFIG_HID_CMEDIA=m
-CONFIG_HID_CP2112=m
-CONFIG_HID_CREATIVE_SB0540=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_DRAGONRISE=m
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=m
-CONFIG_HID_ELAN=m
-CONFIG_HID_ELECOM=m
-CONFIG_HID_ELO=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_FT260=m
-CONFIG_HID_GEMBIRD=m
-CONFIG_HID_GFRM=m
-CONFIG_HID_GLORIOUS=m
-CONFIG_HID_HOLTEK=m
-CONFIG_HOLTEK_FF=y
-CONFIG_HID_GOOGLE_HAMMER=m
-CONFIG_HID_VIVALDI=m
-CONFIG_HID_GT683R=m
-CONFIG_HID_KEYTOUCH=m
-CONFIG_HID_KYE=m
-CONFIG_HID_UCLOGIC=m
-CONFIG_HID_WALTOP=m
-CONFIG_HID_VIEWSONIC=m
-CONFIG_HID_VRC2=m
-CONFIG_HID_GYRATION=m
-CONFIG_HID_ICADE=m
-CONFIG_HID_ITE=m
-CONFIG_HID_JABRA=m
-CONFIG_HID_TWINHAN=m
-CONFIG_HID_KENSINGTON=m
-CONFIG_HID_LCPOWER=m
-CONFIG_HID_LED=m
-CONFIG_HID_LENOVO=m
-CONFIG_HID_LOGITECH=m
-CONFIG_HID_LOGITECH_DJ=m
-CONFIG_HID_LOGITECH_HIDPP=m
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWHEELS_FF=y
-CONFIG_HID_MAGICMOUSE=m
-CONFIG_HID_MALTRON=m
-CONFIG_HID_MAYFLASH=m
-CONFIG_HID_REDRAGON=m
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_MULTITOUCH=m
-CONFIG_HID_NTI=m
-CONFIG_HID_NTRIG=m
-CONFIG_HID_ORTEK=m
-CONFIG_HID_PANTHERLORD=m
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PENMOUNT=m
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_PICOLCD=m
-CONFIG_HID_PICOLCD_FB=y
-CONFIG_HID_PICOLCD_BACKLIGHT=y
-CONFIG_HID_PICOLCD_LCD=y
-CONFIG_HID_PICOLCD_LEDS=y
-CONFIG_HID_PICOLCD_CIR=y
-CONFIG_HID_PLANTRONICS=m
-CONFIG_HID_PLAYSTATION=m
-CONFIG_HID_PXRC=m
-CONFIG_HID_RAZER=m
-CONFIG_PLAYSTATION_FF=y
-CONFIG_HID_PRIMAX=m
-CONFIG_HID_RETRODE=m
-CONFIG_HID_ROCCAT=m
-CONFIG_HID_SAITEK=m
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SEMITEK=m
-CONFIG_HID_SIGMAMICRO=m
-CONFIG_HID_SONY=m
-CONFIG_SONY_FF=y
-CONFIG_HID_SPEEDLINK=m
-CONFIG_HID_STEAM=m
-CONFIG_HID_STEELSERIES=m
-CONFIG_HID_SUNPLUS=m
-CONFIG_HID_RMI=m
-CONFIG_HID_GREENASIA=m
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_SMARTJOYPLUS=m
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TIVO=m
-CONFIG_HID_TOPSEED=m
-CONFIG_HID_TOPRE=m
-CONFIG_HID_THINGM=m
-CONFIG_HID_THRUSTMASTER=m
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_UDRAW_PS3=m
-CONFIG_HID_U2FZERO=m
-CONFIG_HID_WACOM=m
-CONFIG_HID_WIIMOTE=m
-CONFIG_HID_XINMO=m
-CONFIG_HID_ZEROPLUS=m
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=m
-CONFIG_HID_SENSOR_HUB=m
-CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
-CONFIG_HID_ALPS=m
-CONFIG_HID_MCP2221=m
-# end of Special HID drivers
-
-#
-# USB HID support
-#
-CONFIG_USB_HID=m
-CONFIG_HID_PID=y
-CONFIG_USB_HIDDEV=y
-
-#
-# USB HID Boot Protocol drivers
-#
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
-# end of USB HID Boot Protocol drivers
-# end of USB HID support
-
-#
-# I2C HID support
-#
-CONFIG_I2C_HID=m
-CONFIG_I2C_HID_OF=m
-CONFIG_I2C_HID_OF_ELAN=m
-CONFIG_USB_ONBOARD_HUB=m
-CONFIG_I2C_HID_OF_GOODIX=m
-CONFIG_I2C_HID_ACPI=m
-# end of I2C HID support
-# end of HID support
-
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_LED_TRIG=y
-CONFIG_USB_ULPI_BUS=m
-CONFIG_USB_CONN_GPIO=m
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB=m
-CONFIG_USB_PCI=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEFAULT_PERSIST=y
-CONFIG_USB_FEW_INIT_RETRIES=y
-CONFIG_USB_DYNAMIC_MINORS=y
-CONFIG_USB_OTG=y
-# CONFIG_USB_OTG_PRODUCTLIST is not set
-# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
-CONFIG_USB_OTG_FSM=m
-CONFIG_USB_LEDS_TRIGGER_USBPORT=m
-CONFIG_USB_AUTOSUSPEND_DELAY=2
-CONFIG_USB_MON=m
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_C67X00_HCD=m
-CONFIG_USB_XHCI_HCD=m
-CONFIG_USB_XHCI_DBGCAP=y
-CONFIG_USB_XHCI_PCI=m
-CONFIG_USB_XHCI_PCI_RENESAS=m
-CONFIG_USB_XHCI_PLATFORM=m
-# CONFIG_USB_XHCI_HISTB is not set
-# CONFIG_USB_XHCI_MTK is not set
-# CONFIG_USB_XHCI_MVEBU is not set
-CONFIG_USB_XHCI_RCAR=m
-CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-CONFIG_USB_EHCI_PCI=m
-CONFIG_USB_EHCI_FSL=m
-CONFIG_USB_EHCI_HCD_NPCM7XX=m
-# CONFIG_USB_EHCI_MXC is not set
-CONFIG_USB_EHCI_HCD_OMAP=m
-CONFIG_USB_EHCI_HCD_ORION=m
-CONFIG_USB_EHCI_HCD_SPEAR=m
-# CONFIG_USB_EHCI_HCD_STI is not set
-CONFIG_USB_EHCI_HCD_AT91=m
-# CONFIG_USB_EHCI_TEGRA is not set
-# CONFIG_USB_EHCI_EXYNOS is not set
-# CONFIG_USB_EHCI_MV is not set
-CONFIG_USB_EHCI_HCD_PLATFORM=m
-CONFIG_USB_OXU210HP_HCD=m
-CONFIG_USB_ISP116X_HCD=m
-CONFIG_USB_FOTG210_HCD=m
-CONFIG_USB_MAX3421_HCD=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_OHCI_HCD_SPEAR=m
-# CONFIG_USB_OHCI_HCD_STI is not set
-CONFIG_USB_OHCI_HCD_AT91=m
-CONFIG_USB_OHCI_HCD_OMAP3=m
-CONFIG_USB_OHCI_HCD_PCI=m
-CONFIG_USB_OHCI_HCD_SSB=y
-# CONFIG_USB_OHCI_EXYNOS is not set
-CONFIG_USB_OHCI_HCD_PLATFORM=m
-CONFIG_USB_UHCI_HCD=m
-CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC=y
-CONFIG_USB_UHCI_PLATFORM=y
-CONFIG_USB_UHCI_ASPEED=y
-CONFIG_USB_U132_HCD=m
-CONFIG_USB_SL811_HCD=m
-# CONFIG_USB_SL811_HCD_ISO is not set
-CONFIG_USB_SL811_CS=m
-CONFIG_USB_R8A66597_HCD=m
-# CONFIG_USB_IMX21_HCD is not set
-CONFIG_USB_HCD_BCMA=m
-CONFIG_USB_HCD_SSB=m
-# CONFIG_USB_HCD_TEST_MODE is not set
-# CONFIG_USB_RENESAS_USBHS is not set
-
-#
-# USB Device Class drivers
-#
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_WDM=m
-CONFIG_USB_TMC=m
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-CONFIG_USB_STORAGE_REALTEK=m
-CONFIG_REALTEK_AUTOPM=y
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_ISD200=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_STORAGE_ALAUDA=m
-CONFIG_USB_STORAGE_ONETOUCH=m
-CONFIG_USB_STORAGE_KARMA=m
-CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-CONFIG_USB_STORAGE_ENE_UB6250=m
-CONFIG_USB_UAS=m
-
-#
-# USB Imaging devices
-#
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USBIP_CORE=m
-CONFIG_USBIP_VHCI_HCD=m
-CONFIG_USBIP_VHCI_HC_PORTS=8
-CONFIG_USBIP_VHCI_NR_HCS=1
-CONFIG_USBIP_HOST=m
-CONFIG_USBIP_VUDC=m
-# CONFIG_USBIP_DEBUG is not set
-CONFIG_USB_CDNS_SUPPORT=m
-CONFIG_USB_CDNS3=m
-CONFIG_USB_CDNSP_PCI=m
-CONFIG_USB_CDNSP_GADGET=y
-CONFIG_USB_CDNSP_HOST=y
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_USB_CDNS3_HOST=y
-CONFIG_USB_CDNS3_IMX=m
-# CONFIG_USB_MTU3 is not set
-CONFIG_USB_MUSB_HDRC=m
-# CONFIG_USB_MUSB_HOST is not set
-# CONFIG_USB_MUSB_GADGET is not set
-CONFIG_USB_MUSB_DUAL_ROLE=y
-
-#
-# Platform Glue Layer
-#
-# CONFIG_USB_MUSB_TUSB6010 is not set
-# CONFIG_USB_MUSB_OMAP2PLUS is not set
-# CONFIG_USB_MUSB_AM35X is not set
-# CONFIG_USB_MUSB_DSPS is not set
-# CONFIG_USB_MUSB_UX500 is not set
-# CONFIG_USB_MUSB_MEDIATEK is not set
-
-#
-# MUSB DMA mode
-#
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_DWC3=m
-# CONFIG_USB_DWC3_ULPI is not set
-# CONFIG_USB_DWC3_HOST is not set
-# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_DUAL_ROLE=y
-
-#
-# Platform Glue Driver Support
-#
-CONFIG_USB_DWC3_OMAP=m
-CONFIG_USB_DWC3_EXYNOS=m
-CONFIG_USB_DWC3_HAPS=m
-CONFIG_USB_DWC3_KEYSTONE=m
-CONFIG_USB_DWC3_MESON_G12A=m
-CONFIG_USB_DWC3_OF_SIMPLE=m
-CONFIG_USB_DWC3_ST=m
-CONFIG_USB_DWC3_QCOM=m
-CONFIG_USB_DWC3_IMX8MP=m
-CONFIG_USB_DWC3_XILINX=m
-CONFIG_USB_DWC2=m
-# CONFIG_USB_DWC2_HOST is not set
-
-#
-# Gadget/Dual-role mode requires USB Gadget support to be enabled
-#
-# CONFIG_USB_DWC2_PERIPHERAL is not set
-CONFIG_USB_DWC2_DUAL_ROLE=y
-CONFIG_USB_DWC2_PCI=m
-# CONFIG_USB_DWC2_DEBUG is not set
-# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
-CONFIG_USB_CHIPIDEA=m
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_PCI=m
-CONFIG_USB_CHIPIDEA_MSM=m
-CONFIG_USB_CHIPIDEA_IMX=m
-CONFIG_USB_CHIPIDEA_GENERIC=m
-CONFIG_USB_CHIPIDEA_TEGRA=m
-CONFIG_USB_ISP1760=m
-CONFIG_USB_ISP1760_HCD=y
-CONFIG_USB_ISP1761_UDC=y
-# CONFIG_USB_ISP1760_HOST_ROLE is not set
-# CONFIG_USB_ISP1760_GADGET_ROLE is not set
-CONFIG_USB_ISP1760_DUAL_ROLE=y
-
-#
-# USB port drivers
-#
-CONFIG_USB_USS720=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_SIMPLE=m
-CONFIG_USB_SERIAL_AIRCABLE=m
-CONFIG_USB_SERIAL_ARK3116=m
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_CH341=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CP210X=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_F81232=m
-CONFIG_USB_SERIAL_F8153X=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_IUU=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_METRO=m
-CONFIG_USB_SERIAL_MOS7720=m
-CONFIG_USB_SERIAL_MOS7715_PARPORT=y
-CONFIG_USB_SERIAL_MOS7840=m
-CONFIG_USB_SERIAL_MXUPORT=m
-CONFIG_USB_SERIAL_NAVMAN=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_OTI6858=m
-CONFIG_USB_SERIAL_QCAUX=m
-CONFIG_USB_SERIAL_QUALCOMM=m
-CONFIG_USB_SERIAL_SPCP8X5=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_SAFE_PADDED=y
-CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-CONFIG_USB_SERIAL_SYMBOL=m
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-CONFIG_USB_SERIAL_WWAN=m
-CONFIG_USB_SERIAL_OPTION=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_SERIAL_OPTICON=m
-CONFIG_USB_SERIAL_XSENS_MT=m
-CONFIG_USB_SERIAL_WISHBONE=m
-CONFIG_USB_SERIAL_SSU100=m
-CONFIG_USB_SERIAL_QT2=m
-# CONFIG_USB_SERIAL_UPD78F0730 is not set
-CONFIG_USB_SERIAL_XR=m
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_ADUTUX=m
-CONFIG_USB_SEVSEG=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_CYPRESS_CY7C63=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_IDMOUSE=m
-CONFIG_USB_FTDI_ELAN=m
-CONFIG_USB_APPLEDISPLAY=m
-CONFIG_USB_QCOM_EUD=m
-CONFIG_APPLE_MFI_FASTCHARGE=m
-CONFIG_USB_SISUSBVGA=m
-CONFIG_USB_SISUSBVGA_CON=y
-CONFIG_USB_LD=m
-CONFIG_USB_TRANCEVIBRATOR=m
-CONFIG_USB_IOWARRIOR=m
-CONFIG_USB_TEST=m
-CONFIG_USB_EHSET_TEST_FIXTURE=m
-CONFIG_USB_ISIGHTFW=m
-CONFIG_USB_YUREX=m
-CONFIG_USB_EZUSB_FX2=m
-CONFIG_USB_HUB_USB251XB=m
-CONFIG_USB_HSIC_USB3503=m
-CONFIG_USB_HSIC_USB4604=m
-CONFIG_USB_LINK_LAYER_TEST=m
-CONFIG_USB_CHAOSKEY=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_CXACRU=m
-CONFIG_USB_UEAGLEATM=m
-CONFIG_USB_XUSBATM=m
-
-#
-# USB Physical Layer drivers
-#
-CONFIG_USB_PHY=y
-# CONFIG_AB8500_USB is not set
-# CONFIG_KEYSTONE_USB_PHY is not set
-CONFIG_NOP_USB_XCEIV=m
-CONFIG_AM335X_CONTROL_USB=m
-CONFIG_AM335X_PHY_USB=m
-CONFIG_USB_GPIO_VBUS=m
-CONFIG_TAHVO_USB=m
-CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y
-CONFIG_USB_ISP1301=m
-# CONFIG_USB_MXS_PHY is not set
-CONFIG_USB_TEGRA_PHY=m
-CONFIG_USB_ULPI=y
-CONFIG_USB_ULPI_VIEWPORT=y
-# end of USB Physical Layer drivers
-
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
-CONFIG_U_SERIAL_CONSOLE=y
-
-#
-# USB Peripheral Controller
-#
-# CONFIG_USB_AT91 is not set
-# CONFIG_USB_ATMEL_USBA is not set
-# CONFIG_USB_FSL_USB2 is not set
-CONFIG_USB_FOTG210_UDC=m
-CONFIG_USB_GR_UDC=m
-CONFIG_USB_R8A66597=m
-# CONFIG_USB_RENESAS_USB3 is not set
-CONFIG_USB_PXA27X=m
-CONFIG_USB_MV_UDC=m
-CONFIG_USB_MV_U3D=m
-CONFIG_USB_SNP_CORE=m
-CONFIG_USB_SNP_UDC_PLAT=m
-CONFIG_USB_M66592=m
-CONFIG_USB_BDC_UDC=m
-
-#
-# Platform Support
-#
-CONFIG_USB_BDC_PCI=m
-CONFIG_USB_AMD5536UDC=m
-CONFIG_USB_NET2272=m
-CONFIG_USB_NET2272_DMA=y
-CONFIG_USB_NET2280=m
-CONFIG_USB_GOKU=m
-CONFIG_USB_EG20T=m
-CONFIG_USB_GADGET_XILINX=m
-CONFIG_USB_MAX3420_UDC=m
-# CONFIG_USB_ASPEED_VHUB is not set
-# CONFIG_USB_DUMMY_HCD is not set
-# end of USB Peripheral Controller
-
-CONFIG_USB_LIBCOMPOSITE=m
-CONFIG_USB_F_ACM=m
-CONFIG_USB_F_SS_LB=m
-CONFIG_USB_U_SERIAL=m
-CONFIG_USB_U_ETHER=m
-CONFIG_USB_U_AUDIO=m
-CONFIG_USB_F_SERIAL=m
-CONFIG_USB_F_OBEX=m
-CONFIG_USB_F_NCM=m
-CONFIG_USB_F_ECM=m
-CONFIG_USB_F_PHONET=m
-CONFIG_USB_F_EEM=m
-CONFIG_USB_F_SUBSET=m
-CONFIG_USB_F_RNDIS=m
-CONFIG_USB_F_MASS_STORAGE=m
-CONFIG_USB_F_FS=m
-CONFIG_USB_F_UAC1=m
-CONFIG_USB_F_UAC2=m
-CONFIG_USB_F_UVC=m
-CONFIG_USB_F_MIDI=m
-CONFIG_USB_F_HID=m
-CONFIG_USB_F_PRINTER=m
-CONFIG_USB_F_TCM=m
-CONFIG_USB_CONFIGFS=m
-CONFIG_USB_CONFIGFS_SERIAL=y
-CONFIG_USB_CONFIGFS_ACM=y
-CONFIG_USB_CONFIGFS_OBEX=y
-CONFIG_USB_CONFIGFS_NCM=y
-CONFIG_USB_CONFIGFS_ECM=y
-CONFIG_USB_CONFIGFS_ECM_SUBSET=y
-CONFIG_USB_CONFIGFS_RNDIS=y
-CONFIG_USB_CONFIGFS_EEM=y
-CONFIG_USB_CONFIGFS_PHONET=y
-CONFIG_USB_CONFIGFS_MASS_STORAGE=y
-CONFIG_USB_CONFIGFS_F_LB_SS=y
-CONFIG_USB_CONFIGFS_F_FS=y
-CONFIG_USB_CONFIGFS_F_UAC1=y
-# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
-CONFIG_USB_CONFIGFS_F_UAC2=y
-CONFIG_USB_CONFIGFS_F_MIDI=y
-CONFIG_USB_CONFIGFS_F_HID=y
-CONFIG_USB_CONFIGFS_F_UVC=y
-CONFIG_USB_CONFIGFS_F_PRINTER=y
-CONFIG_USB_CONFIGFS_F_TCM=y
-
-#
-# USB Gadget precomposed configurations
-#
-CONFIG_USB_ZERO=m
-CONFIG_USB_ZERO_HNPTEST=y
-CONFIG_USB_AUDIO=m
-CONFIG_GADGET_UAC1=y
-# CONFIG_GADGET_UAC1_LEGACY is not set
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-CONFIG_USB_ETH_EEM=y
-CONFIG_USB_G_NCM=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FUNCTIONFS=m
-CONFIG_USB_FUNCTIONFS_ETH=y
-CONFIG_USB_FUNCTIONFS_RNDIS=y
-CONFIG_USB_FUNCTIONFS_GENERIC=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_GADGET_TARGET=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_MIDI_GADGET=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_NOKIA=m
-CONFIG_USB_G_ACM_MS=m
-CONFIG_USB_G_MULTI=m
-CONFIG_USB_G_MULTI_RNDIS=y
-CONFIG_USB_G_MULTI_CDC=y
-CONFIG_USB_G_HID=m
-# CONFIG_USB_G_DBGP is not set
-CONFIG_USB_G_WEBCAM=m
-CONFIG_USB_RAW_GADGET=m
-# end of USB Gadget precomposed configurations
-
-CONFIG_TYPEC=m
-CONFIG_TYPEC_TCPM=m
-CONFIG_TYPEC_TCPCI=m
-CONFIG_TYPEC_RT1711H=m
-CONFIG_TYPEC_TCPCI_MT6370=m
-CONFIG_TYPEC_MT6360=m
-CONFIG_TYPEC_TCPCI_MT6370=m
-CONFIG_TYPEC_TCPCI_MAXIM=m
-CONFIG_TYPEC_FUSB302=m
-CONFIG_TYPEC_UCSI=m
-CONFIG_UCSI_CCG=m
-CONFIG_UCSI_ACPI=m
-CONFIG_UCSI_STM32G0=m
-CONFIG_TYPEC_HD3SS3220=m
-CONFIG_TYPEC_TPS6598X=m
-CONFIG_TYPEC_ANX7411=m
-CONFIG_TYPEC_RT1719=m
-CONFIG_TYPEC_STUSB160X=m
-CONFIG_TYPEC_WUSB3801=m
-CONFIG_TYPEC_QCOM_PMIC=m
-CONFIG_TYPEC_WUSB3801=m
-CONFIG_TYPEC_EXTCON=m
-
-#
-# USB Type-C Multiplexer/DeMultiplexer Switch support
-#
-CONFIG_TYPEC_MUX_PI3USB30532=m
-# end of USB Type-C Multiplexer/DeMultiplexer Switch support
-
-#
-# USB Type-C Alternate Mode drivers
-#
-CONFIG_TYPEC_DP_ALTMODE=m
-CONFIG_TYPEC_NVIDIA_ALTMODE=m
-# end of USB Type-C Alternate Mode drivers
-
-CONFIG_USB_ROLE_SWITCH=m
-CONFIG_MMC=m
-CONFIG_PWRSEQ_EMMC=m
-CONFIG_PWRSEQ_SD8787=m
-CONFIG_PWRSEQ_SIMPLE=m
-CONFIG_MMC_BLOCK=m
-CONFIG_MMC_BLOCK_MINORS=8
-CONFIG_SDIO_UART=m
-# CONFIG_MMC_TEST is not set
-CONFIG_MMC_CRYPTO=y
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_ARMMMCI is not set
-CONFIG_MMC_SDHCI=m
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PCI=m
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI_PLTFM=m
-CONFIG_MMC_SDHCI_OF_ARASAN=m
-CONFIG_MMC_SDHCI_OF_ASPEED=m
-CONFIG_MMC_SDHCI_OF_AT91=m
-# CONFIG_MMC_SDHCI_OF_ESDHC is not set
-CONFIG_MMC_SDHCI_OF_DWCMSHC=y
-CONFIG_MMC_SDHCI_CADENCE=m
-# CONFIG_MMC_SDHCI_ESDHC_IMX is not set
-# CONFIG_MMC_SDHCI_TEGRA is not set
-# CONFIG_MMC_SDHCI_S3C is not set
-# CONFIG_MMC_SDHCI_SIRF is not set
-# CONFIG_MMC_SDHCI_PXAV3 is not set
-# CONFIG_MMC_SDHCI_PXAV2 is not set
-# CONFIG_MMC_SDHCI_SPEAR is not set
-CONFIG_MMC_SDHCI_F_SDH30=m
-CONFIG_MMC_SDHCI_MILBEAUT=m
-# CONFIG_MMC_MESON_GX is not set
-# CONFIG_MMC_MESON_MX_SDHC is not set
-# CONFIG_MMC_MESON_MX_SDIO is not set
-# CONFIG_MMC_SDHCI_ST is not set
-# CONFIG_MMC_OMAP is not set
-# CONFIG_MMC_OMAP_HS is not set
-CONFIG_MMC_ALCOR=m
-# CONFIG_MMC_ATMELMCI is not set
-# CONFIG_MMC_SDHCI_MSM is not set
-# CONFIG_MMC_MXC is not set
-CONFIG_MMC_TIFM_SD=m
-# CONFIG_MMC_MVSDIO is not set
-CONFIG_MMC_SPI=m
-CONFIG_MMC_SDRICOH_CS=m
-CONFIG_MMC_TMIO_CORE=m
-CONFIG_MMC_TMIO=m
-# CONFIG_MMC_SDHI is not set
-# CONFIG_MMC_UNIPHIER is not set
-CONFIG_MMC_CB710=m
-CONFIG_MMC_VIA_SDMMC=m
-CONFIG_MMC_DW=m
-CONFIG_MMC_DW_PLTFM=m
-CONFIG_MMC_DW_BLUEFIELD=m
-CONFIG_MMC_DW_EXYNOS=m
-CONFIG_MMC_DW_HI3798CV200=m
-CONFIG_MMC_DW_K3=m
-CONFIG_MMC_DW_PCI=m
-# CONFIG_MMC_DW_ROCKCHIP is not set
-# CONFIG_MMC_DW_ZX is not set
-# CONFIG_MMC_SH_MMCIF is not set
-CONFIG_MMC_VUB300=m
-CONFIG_MMC_USHC=m
-CONFIG_MMC_WMT=m
-CONFIG_MMC_USDHI6ROL0=m
-CONFIG_MMC_REALTEK_PCI=m
-CONFIG_MMC_REALTEK_USB=m
-# CONFIG_MMC_SUNXI is not set
-CONFIG_MMC_CQHCI=m
-CONFIG_MMC_HSQ=m
-# CONFIG_MMC_TOSHIBA_PCI is not set
-CONFIG_MMC_MTK=m
-CONFIG_MMC_SDHCI_XENON=m
-CONFIG_MMC_SDHCI_OMAP=m
-CONFIG_MMC_SDHCI_AM654=m
-# CONFIG_MMC_OWL is not set
-CONFIG_MMC_LITEX=m
-CONFIG_MMC_SDHCI_EXTERNAL_DMA=y
-CONFIG_MEMSTICK=m
-# CONFIG_MEMSTICK_DEBUG is not set
-
-#
-# MemoryStick drivers
-#
-# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
-CONFIG_MSPRO_BLOCK=m
-CONFIG_MS_BLOCK=m
-
-#
-# MemoryStick Host Controller Drivers
-#
-CONFIG_MEMSTICK_TIFM_MS=m
-CONFIG_MEMSTICK_JMICRON_38X=m
-CONFIG_MEMSTICK_R592=m
-CONFIG_MEMSTICK_REALTEK_PCI=m
-CONFIG_MEMSTICK_REALTEK_USB=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_RT4505=m
-CONFIG_LEDS_CLASS_FLASH=m
-CONFIG_LEDS_CLASS_MULTICOLOR=m
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-
-#
-# LED drivers
-#
-CONFIG_LEDS_AAT1290=m
-CONFIG_LEDS_AN30259A=m
-CONFIG_LEDS_AS3645A=m
-CONFIG_LEDS_AW2013=m
-CONFIG_LEDS_BCM6328=m
-CONFIG_LEDS_BCM6358=m
-CONFIG_LEDS_CPCAP=m
-CONFIG_LEDS_CR0014114=m
-CONFIG_LEDS_EL15203000=m
-CONFIG_LEDS_LM3530=m
-CONFIG_LEDS_LM3532=m
-CONFIG_LEDS_LM3533=m
-CONFIG_LEDS_LM3642=m
-CONFIG_LEDS_LM3692X=m
-CONFIG_LEDS_LM3601X=m
-CONFIG_LEDS_MT6323=m
-CONFIG_LEDS_PCA9532=m
-CONFIG_LEDS_PCA9532_GPIO=y
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_LP3944=m
-CONFIG_LEDS_LP3952=m
-CONFIG_LEDS_LP50XX=m
-CONFIG_LEDS_LP55XX_COMMON=m
-CONFIG_LEDS_LP5521=m
-CONFIG_LEDS_LP5523=m
-CONFIG_LEDS_LP5562=m
-CONFIG_LEDS_LP8501=m
-CONFIG_LEDS_LP8860=m
-CONFIG_LEDS_PCA955X=m
-CONFIG_LEDS_PCA955X_GPIO=y
-CONFIG_LEDS_PCA963X=m
-CONFIG_LEDS_WM831X_STATUS=m
-CONFIG_LEDS_DA9052=m
-CONFIG_LEDS_DAC124S085=m
-CONFIG_LEDS_PWM=m
-CONFIG_LEDS_REGULATOR=m
-CONFIG_LEDS_BD2802=m
-CONFIG_LEDS_LT3593=m
-CONFIG_LEDS_MC13783=m
-CONFIG_LEDS_ASIC3=y
-CONFIG_LEDS_TCA6507=m
-CONFIG_LEDS_TLC591XX=m
-CONFIG_LEDS_MAX77650=m
-CONFIG_LEDS_MAX77693=m
-CONFIG_LEDS_LM355x=m
-CONFIG_LEDS_MENF21BMC=m
-CONFIG_LEDS_KTD2692=m
-CONFIG_LEDS_IS31FL319X=m
-CONFIG_LEDS_IS31FL32XX=m
-CONFIG_LEDS_RT8515=m
-
-#
-# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
-#
-CONFIG_LEDS_BLINKM=m
-CONFIG_LEDS_SYSCON=y
-CONFIG_LEDS_PM8058=m
-CONFIG_LEDS_MLXREG=m
-CONFIG_LEDS_USER=m
-CONFIG_LEDS_SPI_BYTE=m
-CONFIG_LEDS_TI_LMU_COMMON=m
-CONFIG_LEDS_BCM63138=m
-CONFIG_LEDS_LM3697=m
-CONFIG_LEDS_LM36274=m
-CONFIG_LEDS_TPS6105X=m
-CONFIG_LEDS_SGM3140=m
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_ONESHOT=m
-CONFIG_LEDS_TRIGGER_DISK=y
-CONFIG_LEDS_TRIGGER_MTD=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_LEDS_TRIGGER_BACKLIGHT=m
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_ACTIVITY=m
-CONFIG_LEDS_TRIGGER_GPIO=m
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-CONFIG_LEDS_TRIGGER_TRANSIENT=m
-CONFIG_LEDS_TRIGGER_CAMERA=m
-CONFIG_LEDS_TRIGGER_PANIC=y
-CONFIG_LEDS_TRIGGER_NETDEV=m
-CONFIG_LEDS_TRIGGER_PATTERN=m
-CONFIG_LEDS_TRIGGER_AUDIO=m
-CONFIG_LEDS_TRIGGER_TTY=m
-CONFIG_LEDS_BLINK=y
-CONFIG_LEDS_BLINK_LGM=m
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_A11Y_BRAILLE_CONSOLE=y
-
-#
-# Speakup console speech
-#
-CONFIG_SPEAKUP=m
-CONFIG_SPEAKUP_SYNTH_ACNTSA=m
-CONFIG_SPEAKUP_SYNTH_APOLLO=m
-CONFIG_SPEAKUP_SYNTH_AUDPTR=m
-CONFIG_SPEAKUP_SYNTH_BNS=m
-CONFIG_SPEAKUP_SYNTH_DECTLK=m
-CONFIG_SPEAKUP_SYNTH_DECEXT=m
-CONFIG_SPEAKUP_SYNTH_LTLK=m
-CONFIG_SPEAKUP_SYNTH_SOFT=m
-CONFIG_SPEAKUP_SYNTH_SPKOUT=m
-CONFIG_SPEAKUP_SYNTH_TXPRT=m
-# CONFIG_SPEAKUP_SYNTH_DUMMY is not set
-# end of Speakup console speech
-
-CONFIG_INFINIBAND=m
-CONFIG_INFINIBAND_USER_MAD=m
-CONFIG_INFINIBAND_USER_ACCESS=m
-CONFIG_INFINIBAND_USER_MEM=y
-CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
-CONFIG_INFINIBAND_ADDR_TRANS=y
-CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
-CONFIG_INFINIBAND_MTHCA=m
-# CONFIG_INFINIBAND_MTHCA_DEBUG is not set
-CONFIG_INFINIBAND_CXGB4=m
-CONFIG_INFINIBAND_IRDMA=m
-CONFIG_INFINIBAND_I40IW=m
-CONFIG_MLX4_INFINIBAND=m
-CONFIG_MLX5_INFINIBAND=m
-CONFIG_INFINIBAND_OCRDMA=m
-CONFIG_INFINIBAND_VMWARE_PVRDMA=m
-CONFIG_RDMA_RXE=m
-CONFIG_RDMA_SIW=m
-CONFIG_INFINIBAND_IPOIB=m
-CONFIG_INFINIBAND_IPOIB_CM=y
-# CONFIG_INFINIBAND_IPOIB_DEBUG is not set
-# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set
-CONFIG_INFINIBAND_SRP=m
-CONFIG_INFINIBAND_SRPT=m
-CONFIG_INFINIBAND_ISER=m
-CONFIG_INFINIBAND_ISERT=m
-CONFIG_INFINIBAND_RTRS=m
-CONFIG_INFINIBAND_RTRS_CLIENT=m
-CONFIG_INFINIBAND_RTRS_SERVER=m
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EDAC=m
-CONFIG_EDAC_LEGACY_SYSFS=y
-# CONFIG_EDAC_DEBUG is not set
-CONFIG_EDAC_AL_MC=m
-# CONFIG_EDAC_HIGHBANK_MC is not set
-# CONFIG_EDAC_HIGHBANK_L2 is not set
-# CONFIG_EDAC_ALTERA is not set
-# CONFIG_EDAC_SYNOPSYS is not set
-CONFIG_EDAC_ASPEED=m
-# CONFIG_EDAC_TI is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-CONFIG_RTC_SYSTOHC=y
-CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-CONFIG_RTC_NVMEM=y
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-CONFIG_RTC_DRV_88PM80X=m
-CONFIG_RTC_DRV_ABB5ZES3=m
-CONFIG_RTC_DRV_ABEOZ9=m
-CONFIG_RTC_DRV_ABX80X=m
-CONFIG_RTC_DRV_DS1307=m
-# CONFIG_RTC_DRV_DS1307_CENTURY is not set
-CONFIG_RTC_DRV_DS1374=m
-CONFIG_RTC_DRV_DS1374_WDT=y
-CONFIG_RTC_DRV_DS1672=m
-# CONFIG_RTC_DRV_HYM8563 is not set
-CONFIG_RTC_DRV_MAX6900=m
-CONFIG_RTC_DRV_MAX8907=m
-# CONFIG_RTC_DRV_MAX77686 is not set
-CONFIG_RTC_DRV_NCT3018Y=m
-CONFIG_RTC_DRV_TI_K3=m
-# CONFIG_RTC_DRV_RK808 is not set
-CONFIG_RTC_DRV_RS5C372=m
-CONFIG_RTC_DRV_ISL1208=m
-CONFIG_RTC_DRV_ISL12022=m
-# CONFIG_RTC_DRV_ISL12026 is not set
-CONFIG_RTC_DRV_X1205=m
-CONFIG_RTC_DRV_PCF8523=m
-CONFIG_RTC_DRV_PCF85063=m
-CONFIG_RTC_DRV_PCF85363=m
-CONFIG_RTC_DRV_PCF8563=m
-CONFIG_RTC_DRV_PCF8583=m
-CONFIG_RTC_DRV_M41T80=m
-CONFIG_RTC_DRV_M41T80_WDT=y
-CONFIG_RTC_DRV_BQ32K=m
-# CONFIG_RTC_DRV_TWL4030 is not set
-# CONFIG_RTC_DRV_RC5T619 is not set
-CONFIG_RTC_DRV_S35390A=m
-CONFIG_RTC_DRV_FM3130=m
-CONFIG_RTC_DRV_RX8010=m
-CONFIG_RTC_DRV_RX8581=m
-CONFIG_RTC_DRV_RX8025=m
-CONFIG_RTC_DRV_EM3027=m
-CONFIG_RTC_DRV_RV3028=m
-CONFIG_RTC_DRV_RV3032=m
-CONFIG_RTC_DRV_RV8803=m
-CONFIG_RTC_DRV_SD3078=m
-
-#
-# SPI RTC drivers
-#
-CONFIG_RTC_DRV_M41T93=m
-CONFIG_RTC_DRV_M41T94=m
-CONFIG_RTC_DRV_DS1302=m
-CONFIG_RTC_DRV_DS1305=m
-CONFIG_RTC_DRV_DS1343=m
-CONFIG_RTC_DRV_DS1347=m
-CONFIG_RTC_DRV_DS1390=m
-CONFIG_RTC_DRV_MAX6916=m
-CONFIG_RTC_DRV_R9701=m
-CONFIG_RTC_DRV_RX4581=m
-CONFIG_RTC_DRV_RX6110=m
-CONFIG_RTC_DRV_RS5C348=m
-CONFIG_RTC_DRV_MAX6902=m
-CONFIG_RTC_DRV_PCF2123=m
-CONFIG_RTC_DRV_MCP795=m
-CONFIG_RTC_I2C_AND_SPI=y
-
-#
-# SPI and I2C RTC drivers
-#
-CONFIG_RTC_DRV_DS3232=m
-CONFIG_RTC_DRV_DS3232_HWMON=y
-CONFIG_RTC_DRV_PCF2127=m
-CONFIG_RTC_DRV_RV3029C2=m
-CONFIG_RTC_DRV_RV3029_HWMON=y
-
-#
-# Platform RTC drivers
-#
-CONFIG_RTC_DRV_CMOS=y
-CONFIG_RTC_DRV_DS1286=m
-CONFIG_RTC_DRV_DS1511=m
-CONFIG_RTC_DRV_DS1553=m
-CONFIG_RTC_DRV_DS1685_FAMILY=m
-CONFIG_RTC_DRV_DS1685=y
-# CONFIG_RTC_DRV_DS1689 is not set
-# CONFIG_RTC_DRV_DS17285 is not set
-# CONFIG_RTC_DRV_DS17485 is not set
-# CONFIG_RTC_DRV_DS17885 is not set
-CONFIG_RTC_DRV_DS1742=m
-CONFIG_RTC_DRV_DS2404=m
-CONFIG_RTC_DRV_DA9052=m
-CONFIG_RTC_DRV_DA9063=m
-CONFIG_RTC_DRV_EFI=m
-CONFIG_RTC_DRV_STK17TA8=m
-CONFIG_RTC_DRV_M48T86=m
-CONFIG_RTC_DRV_M48T35=m
-CONFIG_RTC_DRV_M48T59=m
-CONFIG_RTC_DRV_MSM6242=m
-CONFIG_RTC_DRV_BQ4802=m
-CONFIG_RTC_DRV_RP5C01=m
-CONFIG_RTC_DRV_V3020=m
-CONFIG_RTC_DRV_OPTEE=m
-CONFIG_RTC_DRV_WM831X=m
-CONFIG_RTC_DRV_SPEAR=y
-CONFIG_RTC_DRV_PCF50633=m
-# CONFIG_RTC_DRV_AB8500 is not set
-# CONFIG_RTC_DRV_ZYNQMP is not set
-# CONFIG_RTC_DRV_CROS_EC is not set
-CONFIG_RTC_DRV_NTXEC=m
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_RTC_DRV_DIGICOLOR is not set
-# CONFIG_RTC_DRV_IMXDI is not set
-# CONFIG_RTC_DRV_MESON is not set
-CONFIG_RTC_DRV_MESON_VRTC=m
-# CONFIG_RTC_DRV_OMAP is not set
-CONFIG_HAVE_S3C_RTC=y
-# CONFIG_RTC_DRV_S3C is not set
-# CONFIG_RTC_DRV_SA1100 is not set
-# CONFIG_RTC_DRV_SH is not set
-# CONFIG_RTC_DRV_PL030 is not set
-# CONFIG_RTC_DRV_PL031 is not set
-# CONFIG_RTC_DRV_AT91RM9200 is not set
-# CONFIG_RTC_DRV_AT91SAM9 is not set
-# CONFIG_RTC_DRV_VT8500 is not set
-CONFIG_RTC_DRV_SUN6I=y
-# CONFIG_RTC_DRV_SUNXI is not set
-# CONFIG_RTC_DRV_MV is not set
-# CONFIG_RTC_DRV_ARMADA38X is not set
-# CONFIG_RTC_DRV_CADENCE is not set
-CONFIG_RTC_DRV_FTRTC010=m
-CONFIG_RTC_DRV_PCAP=m
-CONFIG_RTC_DRV_MC13XXX=m
-# CONFIG_RTC_DRV_PM8XXX is not set
-# CONFIG_RTC_DRV_TEGRA is not set
-# CONFIG_RTC_DRV_MXC is not set
-# CONFIG_RTC_DRV_MXC_V2 is not set
-# CONFIG_RTC_DRV_SNVS is not set
-# CONFIG_RTC_DRV_SIRFSOC is not set
-# CONFIG_RTC_DRV_ST_LPC is not set
-# CONFIG_RTC_DRV_MT2712 is not set
-CONFIG_RTC_DRV_MT6397=m
-# CONFIG_RTC_DRV_MT7622 is not set
-# CONFIG_RTC_DRV_R7301 is not set
-# CONFIG_RTC_DRV_STM32 is not set
-# CONFIG_RTC_DRV_CPCAP is not set
-CONFIG_RTC_DRV_RTD119X=y
-# CONFIG_RTC_DRV_ASPEED is not set
-
-#
-# HID Sensor RTC drivers
-#
-CONFIG_RTC_DRV_HID_SENSOR_TIME=m
-CONFIG_RTC_DRV_GOLDFISH=m
-CONFIG_DMADEVICES=y
-# CONFIG_DMADEVICES_DEBUG is not set
-
-#
-# DMA Devices
-#
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DMA_OF=y
-CONFIG_ALTERA_MSGDMA=m
-# CONFIG_AMBA_PL08X is not set
-# CONFIG_AT_HDMAC is not set
-# CONFIG_AT_XDMAC is not set
-# CONFIG_AXI_DMAC is not set
-CONFIG_DMA_SUN4I=y
-# CONFIG_DMA_SUN6I is not set
-# CONFIG_DW_AXI_DMAC is not set
-# CONFIG_FSL_EDMA is not set
-# CONFIG_FSL_QDMA is not set
-# CONFIG_IMX_DMA is not set
-# CONFIG_IMX_SDMA is not set
-# CONFIG_INTEL_IDMA64 is not set
-# CONFIG_K3_DMA is not set
-# CONFIG_MILBEAUT_HDMAC is not set
-# CONFIG_MILBEAUT_XDMAC is not set
-# CONFIG_MMP_PDMA is not set
-# CONFIG_MMP_TDMA is not set
-# CONFIG_MV_XOR is not set
-# CONFIG_MXS_DMA is not set
-CONFIG_MX3_IPU=y
-CONFIG_MX3_IPU_IRQS=4
-# CONFIG_NBPFAXI_DMA is not set
-# CONFIG_OWL_DMA is not set
-CONFIG_PL330_DMA=y
-# CONFIG_PXA_DMA is not set
-CONFIG_PLX_DMA=m
-# CONFIG_SIRF_DMA is not set
-# CONFIG_STE_DMA40 is not set
-# CONFIG_STM32_DMA is not set
-# CONFIG_STM32_MDMA is not set
-# CONFIG_TEGRA20_APB_DMA is not set
-# CONFIG_UNIPHIER_MDMAC is not set
-# CONFIG_UNIPHIER_XDMAC is not set
-# CONFIG_XILINX_DMA is not set
-# CONFIG_XILINX_ZYNQMP_DMA is not set
-CONFIG_XILINX_ZYNQMP_DPDMA=m
-# CONFIG_ZX_DMA is not set
-# CONFIG_MTK_HSDMA is not set
-# CONFIG_MTK_CQDMA is not set
-# CONFIG_QCOM_BAM_DMA is not set
-CONFIG_QCOM_GPI_DMA=m
-CONFIG_QCOM_HIDMA_MGMT=m
-CONFIG_QCOM_HIDMA=m
-CONFIG_DW_DMAC_CORE=y
-CONFIG_DW_DMAC=m
-CONFIG_DW_DMAC_PCI=y
-CONFIG_DW_EDMA=m
-CONFIG_DW_EDMA_PCIE=m
-CONFIG_SF_PDMA=m
-# CONFIG_RCAR_DMAC is not set
-# CONFIG_RENESAS_USB_DMAC is not set
-# CONFIG_TI_CPPI41 is not set
-CONFIG_TI_EDMA=y
-CONFIG_DMA_OMAP=y
-CONFIG_TI_DMA_CROSSBAR=y
-
-#
-# DMA Clients
-#
-CONFIG_ASYNC_TX_DMA=y
-# CONFIG_DMATEST is not set
-
-#
-# DMABUF options
-#
-CONFIG_SYNC_FILE=y
-# CONFIG_SW_SYNC is not set
-# CONFIG_UDMABUF is not set
-# CONFIG_DMABUF_MOVE_NOTIFY is not set
-# CONFIG_DMABUF_DEBUG is not set
-CONFIG_DMABUF_SELFTESTS=m
-# CONFIG_DMABUF_HEAPS is not set
-# end of DMABUF options
-
-CONFIG_AUXDISPLAY=y
-CONFIG_HD44780=m
-CONFIG_KS0108=m
-CONFIG_KS0108_PORT=0x378
-CONFIG_KS0108_DELAY=2
-CONFIG_IMG_ASCII_LCD=m
-# CONFIG_HT16K33 is not set
-CONFIG_LCD2S=m
-# CONFIG_ARM_CHARLCD is not set
-CONFIG_PARPORT_PANEL=m
-CONFIG_PANEL_PARPORT=0
-CONFIG_PANEL_PROFILE=5
-# CONFIG_PANEL_CHANGE_MESSAGE is not set
-# CONFIG_CHARLCD_BL_OFF is not set
-# CONFIG_CHARLCD_BL_ON is not set
-CONFIG_CHARLCD_BL_FLASH=y
-CONFIG_PANEL=m
-CONFIG_CHARLCD=m
-CONFIG_UIO=m
-CONFIG_UIO_CIF=m
-CONFIG_UIO_PDRV_GENIRQ=m
-CONFIG_UIO_DMEM_GENIRQ=m
-CONFIG_UIO_AEC=m
-CONFIG_UIO_SERCOS3=m
-CONFIG_UIO_PCI_GENERIC=m
-CONFIG_UIO_NETX=m
-CONFIG_UIO_PRUSS=m
-CONFIG_UIO_MF624=m
-CONFIG_UIO_DFL=m
-CONFIG_VFIO_IOMMU_TYPE1=m
-CONFIG_VFIO_VIRQFD=m
-CONFIG_VFIO=m
-# CONFIG_VFIO_NOIOMMU is not set
-CONFIG_MLX5_VFIO_PCI=m
-CONFIG_HISI_ACC_VFIO_PCI=m
-CONFIG_VFIO_PCI=m
-CONFIG_VFIO_PCI_MMAP=y
-CONFIG_VFIO_PCI_INTX=y
-# CONFIG_VFIO_PLATFORM is not set
-CONFIG_VFIO_MDEV=m
-CONFIG_VFIO_MDEV_DEVICE=m
-CONFIG_IRQ_BYPASS_MANAGER=m
-CONFIG_VIRT_DRIVERS=y
-CONFIG_VMGENID=m
-CONFIG_VIRTIO=m
-CONFIG_VIRTIO_MENU=y
-CONFIG_VIRTIO_PCI=m
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_VDPA=m
-CONFIG_VP_VDPA=m
-CONFIG_VIRTIO_BALLOON=m
-CONFIG_VIRTIO_MEM=m
-CONFIG_VIRTIO_INPUT=m
-CONFIG_VIRTIO_MMIO=m
-CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
-CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
-CONFIG_VDPA=m
-CONFIG_IFCVF=m
-CONFIG_MLX5_VDPA=y
-CONFIG_MLX5_VDPA_NET=m
-CONFIG_VHOST_IOTLB=m
-CONFIG_VHOST_RING=m
-CONFIG_VHOST=m
-CONFIG_VHOST_MENU=y
-CONFIG_VHOST_NET=m
-CONFIG_VHOST_SCSI=m
-CONFIG_VHOST_VSOCK=m
-CONFIG_VHOST_VDPA=m
-# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
-
-#
-# Microsoft Hyper-V guest support
-#
-# end of Microsoft Hyper-V guest support
-
-# CONFIG_GREYBUS is not set
-CONFIG_STAGING=y
-CONFIG_PRISM2_USB=m
-CONFIG_COMEDI=m
-CONFIG_COMEDI_TESTS=m
-CONFIG_COMEDI_TESTS_EXAMPLE=m
-CONFIG_COMEDI_TESTS_NI_ROUTES=m
-# CONFIG_COMEDI_DEBUG is not set
-CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
-CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
-CONFIG_COMEDI_MISC_DRIVERS=y
-CONFIG_COMEDI_BOND=m
-CONFIG_COMEDI_TEST=m
-CONFIG_COMEDI_PARPORT=m
-CONFIG_COMEDI_ISA_DRIVERS=y
-CONFIG_COMEDI_PCL711=m
-CONFIG_COMEDI_PCL724=m
-CONFIG_COMEDI_PCL726=m
-CONFIG_COMEDI_PCL730=m
-CONFIG_COMEDI_PCL812=m
-CONFIG_COMEDI_PCL816=m
-CONFIG_COMEDI_PCL818=m
-CONFIG_COMEDI_PCM3724=m
-CONFIG_COMEDI_AMPLC_DIO200_ISA=m
-CONFIG_COMEDI_AMPLC_PC236_ISA=m
-CONFIG_COMEDI_AMPLC_PC263_ISA=m
-CONFIG_COMEDI_RTI800=m
-CONFIG_COMEDI_RTI802=m
-CONFIG_COMEDI_DAC02=m
-CONFIG_COMEDI_DAS16M1=m
-CONFIG_COMEDI_DAS08_ISA=m
-CONFIG_COMEDI_DAS16=m
-CONFIG_COMEDI_DAS800=m
-CONFIG_COMEDI_DAS1800=m
-CONFIG_COMEDI_DAS6402=m
-CONFIG_COMEDI_DT2801=m
-CONFIG_COMEDI_DT2811=m
-CONFIG_COMEDI_DT2814=m
-CONFIG_COMEDI_DT2815=m
-CONFIG_COMEDI_DT2817=m
-CONFIG_COMEDI_DT282X=m
-CONFIG_COMEDI_DMM32AT=m
-CONFIG_COMEDI_FL512=m
-CONFIG_COMEDI_AIO_AIO12_8=m
-CONFIG_COMEDI_AIO_IIRO_16=m
-CONFIG_COMEDI_II_PCI20KC=m
-CONFIG_COMEDI_C6XDIGIO=m
-CONFIG_COMEDI_MPC624=m
-CONFIG_COMEDI_ADQ12B=m
-CONFIG_COMEDI_NI_AT_A2150=m
-CONFIG_COMEDI_NI_AT_AO=m
-CONFIG_COMEDI_NI_ATMIO=m
-CONFIG_COMEDI_NI_ATMIO16D=m
-CONFIG_COMEDI_NI_LABPC_ISA=m
-CONFIG_COMEDI_PCMAD=m
-CONFIG_COMEDI_PCMDA12=m
-CONFIG_COMEDI_PCMMIO=m
-CONFIG_COMEDI_PCMUIO=m
-CONFIG_COMEDI_MULTIQ3=m
-CONFIG_COMEDI_S526=m
-CONFIG_COMEDI_PCI_DRIVERS=m
-CONFIG_COMEDI_8255_PCI=m
-CONFIG_COMEDI_ADDI_WATCHDOG=m
-CONFIG_COMEDI_ADDI_APCI_1032=m
-CONFIG_COMEDI_ADDI_APCI_1500=m
-CONFIG_COMEDI_ADDI_APCI_1516=m
-CONFIG_COMEDI_ADDI_APCI_1564=m
-CONFIG_COMEDI_ADDI_APCI_16XX=m
-CONFIG_COMEDI_ADDI_APCI_2032=m
-CONFIG_COMEDI_ADDI_APCI_2200=m
-CONFIG_COMEDI_ADDI_APCI_3120=m
-CONFIG_COMEDI_ADDI_APCI_3501=m
-CONFIG_COMEDI_ADDI_APCI_3XXX=m
-CONFIG_COMEDI_ADL_PCI6208=m
-CONFIG_COMEDI_ADL_PCI7X3X=m
-CONFIG_COMEDI_ADL_PCI8164=m
-CONFIG_COMEDI_ADL_PCI9111=m
-CONFIG_COMEDI_ADL_PCI9118=m
-CONFIG_COMEDI_ADV_PCI1710=m
-CONFIG_COMEDI_ADV_PCI1720=m
-CONFIG_COMEDI_ADV_PCI1723=m
-CONFIG_COMEDI_ADV_PCI1724=m
-CONFIG_COMEDI_ADV_PCI1760=m
-CONFIG_COMEDI_ADV_PCI_DIO=m
-CONFIG_COMEDI_AMPLC_DIO200_PCI=m
-CONFIG_COMEDI_AMPLC_PC236_PCI=m
-CONFIG_COMEDI_AMPLC_PC263_PCI=m
-CONFIG_COMEDI_AMPLC_PCI224=m
-CONFIG_COMEDI_AMPLC_PCI230=m
-CONFIG_COMEDI_CONTEC_PCI_DIO=m
-CONFIG_COMEDI_DAS08_PCI=m
-CONFIG_COMEDI_DT3000=m
-CONFIG_COMEDI_DYNA_PCI10XX=m
-CONFIG_COMEDI_GSC_HPDI=m
-CONFIG_COMEDI_MF6X4=m
-CONFIG_COMEDI_ICP_MULTI=m
-CONFIG_COMEDI_DAQBOARD2000=m
-CONFIG_COMEDI_JR3_PCI=m
-CONFIG_COMEDI_KE_COUNTER=m
-CONFIG_COMEDI_CB_PCIDAS64=m
-CONFIG_COMEDI_CB_PCIDAS=m
-CONFIG_COMEDI_CB_PCIDDA=m
-CONFIG_COMEDI_CB_PCIMDAS=m
-CONFIG_COMEDI_CB_PCIMDDA=m
-CONFIG_COMEDI_ME4000=m
-CONFIG_COMEDI_ME_DAQ=m
-CONFIG_COMEDI_NI_6527=m
-CONFIG_COMEDI_NI_65XX=m
-CONFIG_COMEDI_NI_660X=m
-CONFIG_COMEDI_NI_670X=m
-CONFIG_COMEDI_NI_LABPC_PCI=m
-CONFIG_COMEDI_NI_PCIDIO=m
-CONFIG_COMEDI_NI_PCIMIO=m
-CONFIG_COMEDI_RTD520=m
-CONFIG_COMEDI_S626=m
-CONFIG_COMEDI_MITE=m
-CONFIG_COMEDI_NI_TIOCMD=m
-CONFIG_COMEDI_PCMCIA_DRIVERS=m
-CONFIG_COMEDI_CB_DAS16_CS=m
-CONFIG_COMEDI_DAS08_CS=m
-CONFIG_COMEDI_NI_DAQ_700_CS=m
-CONFIG_COMEDI_NI_DAQ_DIO24_CS=m
-CONFIG_COMEDI_NI_LABPC_CS=m
-CONFIG_COMEDI_NI_MIO_CS=m
-CONFIG_COMEDI_QUATECH_DAQP_CS=m
-CONFIG_COMEDI_USB_DRIVERS=m
-CONFIG_COMEDI_DT9812=m
-CONFIG_COMEDI_NI_USB6501=m
-CONFIG_COMEDI_USBDUX=m
-CONFIG_COMEDI_USBDUXFAST=m
-CONFIG_COMEDI_USBDUXSIGMA=m
-CONFIG_COMEDI_VMK80XX=m
-CONFIG_COMEDI_8254=m
-CONFIG_COMEDI_8255=m
-CONFIG_COMEDI_8255_SA=m
-CONFIG_COMEDI_KCOMEDILIB=m
-CONFIG_COMEDI_AMPLC_DIO200=m
-CONFIG_COMEDI_AMPLC_PC236=m
-CONFIG_COMEDI_DAS08=m
-CONFIG_COMEDI_NI_LABPC=m
-CONFIG_COMEDI_NI_TIO=m
-CONFIG_COMEDI_NI_ROUTING=m
-CONFIG_RTL8192U=m
-CONFIG_RTLLIB=m
-CONFIG_RTLLIB_CRYPTO_CCMP=m
-CONFIG_RTLLIB_CRYPTO_TKIP=m
-CONFIG_RTLLIB_CRYPTO_WEP=m
-CONFIG_RTL8192E=m
-CONFIG_RTL8723BS=m
-CONFIG_R8712U=m
-CONFIG_R8188EU=m
-CONFIG_88EU_AP_MODE=y
-CONFIG_RTS5208=m
-CONFIG_VT6655=m
-CONFIG_VT6656=m
-
-#
-# IIO staging drivers
-#
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16203=m
-CONFIG_ADIS16240=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD7816=m
-CONFIG_AD7280=m
-# end of Analog to digital converters
-
-#
-# Analog digital bi-direction converters
-#
-CONFIG_ADT7316=m
-CONFIG_ADT7316_SPI=m
-CONFIG_ADT7316_I2C=m
-# end of Analog digital bi-direction converters
-
-#
-# Capacitance to digital converters
-#
-CONFIG_AD7150=m
-CONFIG_AD7746=m
-# end of Capacitance to digital converters
-
-#
-# Direct Digital Synthesis
-#
-CONFIG_AD9832=m
-CONFIG_AD9834=m
-# end of Direct Digital Synthesis
-
-#
-# Network Analyzer, Impedance Converters
-#
-CONFIG_AD5933=m
-# end of Network Analyzer, Impedance Converters
-
-#
-# Active energy metering IC
-#
-CONFIG_ADE7854=m
-CONFIG_ADE7854_I2C=m
-CONFIG_ADE7854_SPI=m
-# end of Active energy metering IC
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S1210=m
-# end of Resolver to digital converters
-# end of IIO staging drivers
-
-CONFIG_FB_SM750=m
-# CONFIG_USB_EMXX is not set
-# CONFIG_MFD_NVEC is not set
-CONFIG_STAGING_MEDIA=y
-# CONFIG_VIDEO_HANTRO is not set
-# CONFIG_VIDEO_IMX_MEDIA is not set
-# CONFIG_VIDEO_MESON_VDEC is not set
-# CONFIG_VIDEO_OMAP4 is not set
-# CONFIG_VIDEO_ROCKCHIP_VDEC is not set
-CONFIG_VIDEO_STKWEBCAM=m
-# CONFIG_VIDEO_SUNXI is not set
-# CONFIG_TEGRA_VDE is not set
-CONFIG_VIDEO_ZORAN=m
-CONFIG_VIDEO_ZORAN_DC30=y
-CONFIG_VIDEO_ZORAN_ZR36060=y
-CONFIG_VIDEO_ZORAN_BUZ=y
-CONFIG_VIDEO_ZORAN_DC10=y
-CONFIG_VIDEO_ZORAN_LML33=y
-CONFIG_VIDEO_ZORAN_LML33R10=y
-CONFIG_VIDEO_ZORAN_AVS6EYES=y
-# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set
-
-#
-# Android
-#
-CONFIG_ASHMEM=m
-# CONFIG_ION is not set
-# end of Android
-
-# CONFIG_STAGING_BOARD is not set
-CONFIG_LTE_GDM724X=m
-CONFIG_FIREWIRE_SERIAL=m
-CONFIG_FWTTY_MAX_TOTAL_PORTS=64
-CONFIG_FWTTY_MAX_CARD_PORTS=32
-CONFIG_GS_FPGABOOT=m
-CONFIG_UNISYSSPAR=y
-CONFIG_FB_TFT=m
-CONFIG_FB_TFT_AGM1264K_FL=m
-CONFIG_FB_TFT_BD663474=m
-CONFIG_FB_TFT_HX8340BN=m
-CONFIG_FB_TFT_HX8347D=m
-CONFIG_FB_TFT_HX8353D=m
-CONFIG_FB_TFT_HX8357D=m
-CONFIG_FB_TFT_ILI9163=m
-CONFIG_FB_TFT_ILI9320=m
-CONFIG_FB_TFT_ILI9325=m
-CONFIG_FB_TFT_ILI9340=m
-CONFIG_FB_TFT_ILI9341=m
-CONFIG_FB_TFT_ILI9481=m
-CONFIG_FB_TFT_ILI9486=m
-CONFIG_FB_TFT_PCD8544=m
-CONFIG_FB_TFT_RA8875=m
-CONFIG_FB_TFT_S6D02A1=m
-CONFIG_FB_TFT_S6D1121=m
-CONFIG_FB_TFT_SEPS525=m
-CONFIG_FB_TFT_SH1106=m
-CONFIG_FB_TFT_SSD1289=m
-CONFIG_FB_TFT_SSD1305=m
-CONFIG_FB_TFT_SSD1306=m
-CONFIG_FB_TFT_SSD1331=m
-CONFIG_FB_TFT_SSD1351=m
-# CONFIG_FB_TFT_ST7735R is not set
-CONFIG_FB_TFT_ST7789V=m
-CONFIG_FB_TFT_TINYLCD=m
-CONFIG_FB_TFT_TLS8204=m
-CONFIG_FB_TFT_UC1611=m
-CONFIG_FB_TFT_UC1701=m
-CONFIG_FB_TFT_UPD161704=m
-CONFIG_FB_TFT_WATTEROTT=m
-CONFIG_MOST_COMPONENTS=m
-CONFIG_MOST_NET=m
-CONFIG_MOST_SOUND=m
-CONFIG_MOST_VIDEO=m
-# CONFIG_MOST_DIM2 is not set
-CONFIG_MOST_I2C=m
-CONFIG_KS7010=m
-CONFIG_PI433=m
-
-#
-# Gasket devices
-#
-# end of Gasket devices
-
-# CONFIG_XIL_AXIS_FIFO is not set
-CONFIG_FIELDBUS_DEV=m
-# CONFIG_HMS_ANYBUSS_BUS is not set
-CONFIG_KPC2000=y
-CONFIG_KPC2000_CORE=m
-CONFIG_KPC2000_SPI=m
-CONFIG_KPC2000_I2C=m
-CONFIG_KPC2000_DMA=m
-CONFIG_QLGE=m
-CONFIG_WFX=m
-CONFIG_RTL8723CS=m
-CONFIG_SPMI_HISI3670=m
-CONFIG_MFD_HI6421_SPMI=m
-CONFIG_RTL8723CS=m
-CONFIG_REGULATOR_HI6421V600=m
-# CONFIG_GOLDFISH is not set
-CONFIG_CHROME_PLATFORMS=y
-CONFIG_CROS_EC=m
-CONFIG_CROS_EC_I2C=m
-# CONFIG_CROS_EC_RPMSG is not set
-CONFIG_CROS_EC_SPI=m
-CONFIG_CROS_EC_PROTO=y
-CONFIG_CROS_EC_CHARDEV=m
-CONFIG_CROS_EC_LIGHTBAR=m
-CONFIG_CROS_EC_VBC=m
-CONFIG_CROS_EC_DEBUGFS=m
-CONFIG_CROS_EC_SENSORHUB=m
-CONFIG_CROS_EC_SYSFS=m
-CONFIG_CROS_EC_TYPEC=m
-CONFIG_CROS_USBPD_LOGGER=m
-CONFIG_CROS_USBPD_NOTIFY=m
-CONFIG_CHROMEOS_PRIVACY_SCREEN=m
-CONFIG_CROS_TYPEC_SWITCH=m
-# CONFIG_MELLANOX_PLATFORM is not set
-CONFIG_MLXREG_HOTPLUG=m
-CONFIG_MLXREG_IO=m
-# CONFIG_OLPC_XO175 is not set
-CONFIG_HAVE_CLK=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_COMMON_CLK=y
-CONFIG_LMK04832=m
-CONFIG_COMMON_CLK_APPLE_NCO=m
-CONFIG_COMMON_CLK_WM831X=m
-CONFIG_LMK04832=m
-
-#
-# Clock driver for ARM Reference designs
-#
-CONFIG_ICST=y
-CONFIG_CLK_SP810=y
-CONFIG_CLK_VEXPRESS_OSC=y
-# end of Clock driver for ARM Reference designs
-
-# CONFIG_COMMON_CLK_MAX77686 is not set
-CONFIG_COMMON_CLK_MAX9485=m
-# CONFIG_COMMON_CLK_RK808 is not set
-# CONFIG_COMMON_CLK_SCMI is not set
-# CONFIG_COMMON_CLK_SCPI is not set
-CONFIG_COMMON_CLK_SI5341=m
-CONFIG_COMMON_CLK_SI5351=m
-# CONFIG_COMMON_CLK_SI514 is not set
-CONFIG_COMMON_CLK_SI544=m
-# CONFIG_COMMON_CLK_SI570 is not set
-CONFIG_COMMON_CLK_CDCE706=m
-CONFIG_COMMON_CLK_TPS68470=m
-# CONFIG_COMMON_CLK_CDCE925 is not set
-CONFIG_COMMON_CLK_CS2000_CP=m
-CONFIG_COMMON_CLK_ASPEED=y
-# CONFIG_COMMON_CLK_AXI_CLKGEN is not set
-# CONFIG_CLK_QORIQ is not set
-CONFIG_COMMON_CLK_PWM=m
-CONFIG_COMMON_CLK_RS9_PCIE=m
-# CONFIG_COMMON_CLK_VC5 is not set
-CONFIG_COMMON_CLK_VC7=m
-CONFIG_COMMON_CLK_STM32MP157_SCMI=y
-CONFIG_COMMON_CLK_STM32MP157=y
-# CONFIG_COMMON_CLK_FIXED_MMIO is not set
-CONFIG_CLK_ACTIONS=y
-CONFIG_CLK_OWL_S500=y
-CONFIG_COMMON_CLK_HI3516CV300=y
-CONFIG_COMMON_CLK_HI3519=y
-CONFIG_COMMON_CLK_HI3559A=y
-CONFIG_COMMON_CLK_HI3660=y
-CONFIG_COMMON_CLK_HI3670=y
-CONFIG_COMMON_CLK_HI3798CV200=y
-CONFIG_COMMON_CLK_HI6220=y
-CONFIG_RESET_HISI=y
-CONFIG_STUB_CLK_HI6220=y
-CONFIG_STUB_CLK_HI3660=y
-CONFIG_MXC_CLK=y
-# CONFIG_CLK_IMX8MM is not set
-# CONFIG_CLK_IMX8MN is not set
-# CONFIG_CLK_IMX8MP is not set
-# CONFIG_CLK_IMX8MQ is not set
-CONFIG_COMMON_CLK_KEYSTONE=y
-CONFIG_TI_SYSCON_CLK=y
-CONFIG_MSTAR_MSC313_MPLL=y
-
-#
-# Clock driver for MediaTek SoC
-#
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2701=y
-# CONFIG_COMMON_CLK_MT2701_MMSYS is not set
-# CONFIG_COMMON_CLK_MT2701_IMGSYS is not set
-# CONFIG_COMMON_CLK_MT2701_VDECSYS is not set
-# CONFIG_COMMON_CLK_MT2701_HIFSYS is not set
-# CONFIG_COMMON_CLK_MT2701_ETHSYS is not set
-# CONFIG_COMMON_CLK_MT2701_BDPSYS is not set
-# CONFIG_COMMON_CLK_MT2701_AUDSYS is not set
-# CONFIG_COMMON_CLK_MT2701_G3DSYS is not set
-CONFIG_COMMON_CLK_MT6795=m
-CONFIG_COMMON_CLK_MT6795_MFGCFG=m
-CONFIG_COMMON_CLK_MT6795_MMSYS=m
-CONFIG_COMMON_CLK_MT6795_VDECSYS=m
-CONFIG_COMMON_CLK_MT6795_VENCSYS=m
-CONFIG_COMMON_CLK_MT7622=y
-# CONFIG_COMMON_CLK_MT7622_ETHSYS is not set
-# CONFIG_COMMON_CLK_MT7622_HIFSYS is not set
-# CONFIG_COMMON_CLK_MT7622_AUDSYS is not set
-CONFIG_COMMON_CLK_MT7629=y
-# CONFIG_COMMON_CLK_MT7629_ETHSYS is not set
-# CONFIG_COMMON_CLK_MT7629_HIFSYS is not set
-CONFIG_COMMON_CLK_MT8135=y
-CONFIG_COMMON_CLK_MT8173=y
-CONFIG_COMMON_CLK_MT8173_MMSYS=y
-CONFIG_COMMON_CLK_MT8365=m
-CONFIG_COMMON_CLK_MT8365_APU=m
-CONFIG_COMMON_CLK_MT8365_CAM=m
-CONFIG_COMMON_CLK_MT8365_MFG=m
-CONFIG_COMMON_CLK_MT8365_MMSYS=m
-CONFIG_COMMON_CLK_MT8365_VDEC=m
-CONFIG_COMMON_CLK_MT8365_VENC=m
-CONFIG_COMMON_CLK_MT8516=y
-# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set
-# end of Clock driver for MediaTek SoC
-
-#
-# Clock support for Amlogic platforms
-#
-CONFIG_COMMON_CLK_MESON_REGMAP=y
-CONFIG_COMMON_CLK_MESON_MPLL=y
-CONFIG_COMMON_CLK_MESON_PLL=y
-CONFIG_COMMON_CLK_MESON8B=y
-# end of Clock support for Amlogic platforms
-
-# CONFIG_COMMON_CLK_QCOM is not set
-CONFIG_CLK_RENESAS=y
-# CONFIG_CLK_R9A06G032 is not set
-# CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set
-CONFIG_COMMON_CLK_ROCKCHIP=y
-CONFIG_CLK_PX30=y
-CONFIG_CLK_RV110X=y
-CONFIG_CLK_RV1126=y
-CONFIG_CLK_RK3036=y
-CONFIG_CLK_RK312X=y
-CONFIG_CLK_RK3188=y
-CONFIG_CLK_RK322X=y
-CONFIG_CLK_RK3288=y
-CONFIG_CLK_RK3308=y
-CONFIG_CLK_RK3328=y
-CONFIG_CLK_RK3368=y
-CONFIG_CLK_RK3399=y
-CONFIG_CLK_RK3568=m
-CONFIG_COMMON_CLK_SAMSUNG=y
-CONFIG_EXYNOS_AUDSS_CLK_CON=y
-CONFIG_EXYNOS_CLKOUT=m
-CONFIG_CLK_SUNXI=y
-CONFIG_CLK_SUNXI_CLOCKS=y
-CONFIG_CLK_SUNXI_PRCM_SUN6I=y
-CONFIG_CLK_SUNXI_PRCM_SUN8I=y
-CONFIG_CLK_SUNXI_PRCM_SUN9I=y
-CONFIG_SUNXI_CCU=y
-CONFIG_SUN4I_A10_CCU=y
-CONFIG_SUN5I_CCU=y
-CONFIG_SUN6I_A31_CCU=y
-CONFIG_SUN6I_RTC_CCU=m
-CONFIG_SUN8I_A23_CCU=y
-CONFIG_SUN8I_A33_CCU=y
-CONFIG_SUN8I_A83T_CCU=y
-CONFIG_SUN8I_H3_CCU=y
-CONFIG_SUN8I_V3S_CCU=y
-CONFIG_SUN8I_DE2_CCU=y
-CONFIG_SUN8I_R40_CCU=y
-CONFIG_SUN9I_A80_CCU=y
-CONFIG_SUN8I_R_CCU=y
-CONFIG_COMMON_CLK_TI_ADPLL=y
-CONFIG_CLK_UNIPHIER=y
-CONFIG_COMMON_CLK_VISCONTI=y
-CONFIG_HWSPINLOCK=y
-# CONFIG_HWSPINLOCK_OMAP is not set
-# CONFIG_HWSPINLOCK_QCOM is not set
-# CONFIG_HWSPINLOCK_SIRF is not set
-# CONFIG_HWSPINLOCK_STM32 is not set
-CONFIG_HWSPINLOCK_SUN6I=m
-# CONFIG_HSEM_U8500 is not set
-
-#
-# Clock Source drivers
-#
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_DIGICOLOR_TIMER=y
-CONFIG_DW_APB_TIMER=y
-CONFIG_DW_APB_TIMER_OF=y
-CONFIG_ROCKCHIP_TIMER=y
-CONFIG_MESON6_TIMER=y
-CONFIG_OWL_TIMER=y
-CONFIG_RDA_TIMER=y
-CONFIG_SUN4I_TIMER=y
-CONFIG_SUN5I_HSTIMER=y
-CONFIG_VT8500_TIMER=y
-CONFIG_CADENCE_TTC_TIMER=y
-CONFIG_CLKSRC_NOMADIK_MTU=y
-CONFIG_CLKSRC_DBX500_PRCMU=y
-CONFIG_ATLAS7_TIMER=y
-CONFIG_PRIMA2_TIMER=y
-CONFIG_KEYSTONE_TIMER=y
-CONFIG_CLKSRC_TI_32K=y
-CONFIG_CLKSRC_STM32=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GLOBAL_TIMER=y
-CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2
-CONFIG_ARM_TIMER_SP804=y
-CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
-CONFIG_CLKSRC_EXYNOS_MCT=y
-CONFIG_CLKSRC_SAMSUNG_PWM=y
-CONFIG_MTK_TIMER=y
-CONFIG_CLKSRC_QCOM=y
-CONFIG_CLKSRC_VERSATILE=y
-CONFIG_CLKSRC_TANGO_XTAL=y
-CONFIG_CLKSRC_IMX_GPT=y
-CONFIG_CLKSRC_ST_LPC=y
-# CONFIG_MICROCHIP_PIT64B is not set
-# end of Clock Source drivers
-
-CONFIG_MAILBOX=y
-# CONFIG_ARM_MHU is not set
-CONFIG_ARM_MHU_V2=m
-# CONFIG_IMX_MBOX is not set
-# CONFIG_PLATFORM_MHU is not set
-CONFIG_PL320_MBOX=y
-# CONFIG_ARMADA_37XX_RWTM_MBOX is not set
-# CONFIG_OMAP2PLUS_MBOX is not set
-# CONFIG_ROCKCHIP_MBOX is not set
-CONFIG_ALTERA_MBOX=m
-# CONFIG_STI_MBOX is not set
-# CONFIG_TI_MESSAGE_MANAGER is not set
-CONFIG_HI3660_MBOX=y
-CONFIG_HI6220_MBOX=y
-# CONFIG_MAILBOX_TEST is not set
-# CONFIG_QCOM_APCS_IPC is not set
-# CONFIG_TEGRA_HSP_MBOX is not set
-# CONFIG_STM32_IPCC is not set
-CONFIG_MTK_ADSP_MBOX=m
-# CONFIG_MTK_CMDQ_MBOX is not set
-CONFIG_MTK_DEVAPC=m
-CONFIG_SUN6I_MSGBOX=y
-# CONFIG_QCOM_IPCC is not set
-CONFIG_IOMMU_API=y
-CONFIG_IOMMU_SUPPORT=y
-
-#
-# Generic IOMMU Pagetable Support
-#
-CONFIG_IOMMU_IO_PGTABLE=y
-CONFIG_IOMMU_IO_PGTABLE_LPAE=y
-# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# end of Generic IOMMU Pagetable Support
-
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_OF_IOMMU=y
-# CONFIG_MSM_IOMMU is not set
-# CONFIG_OMAP_IOMMU is not set
-# CONFIG_ROCKCHIP_IOMMU is not set
-# CONFIG_SUN50I_IOMMU is not set
-# CONFIG_TEGRA_IOMMU_SMMU is not set
-# CONFIG_EXYNOS_IOMMU is not set
-# CONFIG_IPMMU_VMSA is not set
-# CONFIG_ARM_SMMU is not set
-# CONFIG_MTK_IOMMU is not set
-# CONFIG_MTK_IOMMU_V1 is not set
-# CONFIG_QCOM_IOMMU is not set
-
-#
-# Remoteproc drivers
-#
-# CONFIG_REMOTEPROC is not set
-# end of Remoteproc drivers
-
-#
-# Rpmsg drivers
-#
-CONFIG_RPMSG=m
-CONFIG_RPMSG_CHAR=m
-CONFIG_RPMSG_CTRL=m
-CONFIG_RPMSG_QCOM_GLINK=m
-CONFIG_RPMSG_QCOM_GLINK_RPM=m
-CONFIG_RPMSG_VIRTIO=m
-# end of Rpmsg drivers
-
-CONFIG_SOUNDWIRE=y
-
-#
-# SoundWire Devices
-#
-CONFIG_SOUNDWIRE_QCOM=m
-
-#
-# SOC (System On Chip) specific Drivers
-#
-CONFIG_OWL_PM_DOMAINS_HELPER=y
-# CONFIG_OWL_PM_DOMAINS is not set
-
-#
-# Amlogic SoC drivers
-#
-# CONFIG_MESON_CANVAS is not set
-CONFIG_MESON_CLK_MEASURE=y
-CONFIG_MESON_GX_SOCINFO=y
-CONFIG_MESON_GX_PM_DOMAINS=y
-CONFIG_MESON_EE_PM_DOMAINS=y
-CONFIG_MESON_MX_SOCINFO=y
-# end of Amlogic SoC drivers
-
-#
-# Aspeed SoC drivers
-#
-CONFIG_SOC_ASPEED=y
-# CONFIG_ASPEED_LPC_CTRL is not set
-# CONFIG_ASPEED_LPC_SNOOP is not set
-# CONFIG_ASPEED_P2A_CTRL is not set
-CONFIG_ASPEED_SOCINFO=y
-# end of Aspeed SoC drivers
-
-CONFIG_AT91_SOC_ID=y
-# CONFIG_AT91_SOC_SFR is not set
-
-#
-# Broadcom SoC drivers
-#
-# CONFIG_SOC_BRCMSTB is not set
-CONFIG_BCM_PMB=y
-# end of Broadcom SoC drivers
-
-#
-# NXP/Freescale QorIQ SoC drivers
-#
-# CONFIG_QUICC_ENGINE is not set
-# CONFIG_FSL_RCPM is not set
-# end of NXP/Freescale QorIQ SoC drivers
-
-#
-# i.MX SoC drivers
-#
-# CONFIG_IMX_GPCV2_PM_DOMAINS is not set
-# CONFIG_SOC_IMX8M is not set
-CONFIG_SOC_IMX9=m
-# end of i.MX SoC drivers
-
-#
-# MediaTek SoC drivers
-#
-# CONFIG_MTK_CMDQ is not set
-CONFIG_MTK_INFRACFG=y
-# CONFIG_MTK_PMIC_WRAP is not set
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_MMSYS=y
-CONFIG_MTK_SVS=m
-# end of MediaTek SoC drivers
-
-#
-# Qualcomm SoC drivers
-#
-# CONFIG_QCOM_AOSS_QMP is not set
-# CONFIG_QCOM_COMMAND_DB is not set
-CONFIG_QCOM_CPR=m
-# CONFIG_QCOM_GENI_SE is not set
-# CONFIG_QCOM_GSBI is not set
-# CONFIG_QCOM_LLCC is not set
-# CONFIG_QCOM_OCMEM is not set
-CONFIG_QCOM_QMI_HELPERS=m
-# CONFIG_QCOM_RMTFS_MEM is not set
-CONFIG_QCOM_RPMH=y
-# CONFIG_QCOM_SMEM is not set
-# CONFIG_QCOM_SMD_RPM is not set
-# CONFIG_QCOM_WCNSS_CTRL is not set
-# CONFIG_QCOM_APR is not set
-CONFIG_QCOM_ICC_BWMON=m
-# end of Qualcomm SoC drivers
-
-CONFIG_SOC_RENESAS=y
-# CONFIG_ARCH_EMEV2 is not set
-# CONFIG_ARCH_R8A7794 is not set
-# CONFIG_ARCH_R8A7779 is not set
-# CONFIG_ARCH_R8A7790 is not set
-# CONFIG_ARCH_R8A7778 is not set
-# CONFIG_ARCH_R8A7793 is not set
-# CONFIG_ARCH_R8A7791 is not set
-# CONFIG_ARCH_R8A7792 is not set
-# CONFIG_ARCH_R8A7740 is not set
-# CONFIG_ARCH_R8A73A4 is not set
-# CONFIG_ARCH_R7S72100 is not set
-# CONFIG_ARCH_R7S9210 is not set
-# CONFIG_ARCH_R8A77470 is not set
-# CONFIG_ARCH_R8A7745 is not set
-# CONFIG_ARCH_R8A7742 is not set
-# CONFIG_ARCH_R8A7743 is not set
-# CONFIG_ARCH_R8A7744 is not set
-# CONFIG_ARCH_R9A06G032 is not set
-# CONFIG_ARCH_SH73A0 is not set
-CONFIG_ROCKCHIP_GRF=y
-# CONFIG_ROCKCHIP_IODOMAIN is not set
-# CONFIG_ROCKCHIP_PM_DOMAINS is not set
-CONFIG_ROCKCHIP_DTPM=m
-CONFIG_SOC_SAMSUNG=y
-CONFIG_EXYNOS_ASV=y
-CONFIG_EXYNOS_ASV_ARM=y
-CONFIG_EXYNOS_CHIPID=y
-CONFIG_EXYNOS_PMU=y
-CONFIG_EXYNOS_PMU_ARM_DRIVERS=y
-CONFIG_EXYNOS_PM_DOMAINS=y
-# CONFIG_SAMSUNG_PM_CHECK is not set
-CONFIG_EXYNOS_REGULATOR_COUPLER=y
-CONFIG_SUNXI_SRAM=y
-# CONFIG_ARCH_TEGRA_2x_SOC is not set
-# CONFIG_ARCH_TEGRA_3x_SOC is not set
-# CONFIG_ARCH_TEGRA_114_SOC is not set
-# CONFIG_ARCH_TEGRA_124_SOC is not set
-CONFIG_SOC_TEGRA_FUSE=y
-# CONFIG_SOC_TI is not set
-CONFIG_UX500_SOC_ID=y
-CONFIG_SOC_REALVIEW=y
-
-#
-# Xilinx SoC drivers
-#
-# CONFIG_XILINX_VCU is not set
-# end of Xilinx SoC drivers
-
-# CONFIG_SOC_ZTE is not set
-# end of SOC (System On Chip) specific Drivers
-
-CONFIG_PM_DEVFREQ=y
-
-#
-# DEVFREQ Governors
-#
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_PERFORMANCE=y
-CONFIG_DEVFREQ_GOV_POWERSAVE=y
-CONFIG_DEVFREQ_GOV_USERSPACE=y
-CONFIG_DEVFREQ_GOV_PASSIVE=m
-
-#
-# DEVFREQ Drivers
-#
-# CONFIG_ARM_EXYNOS_BUS_DEVFREQ is not set
-# CONFIG_ARM_IMX_BUS_DEVFREQ is not set
-# CONFIG_ARM_IMX8M_DDRC_DEVFREQ is not set
-# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
-CONFIG_PM_DEVFREQ_EVENT=y
-# CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP is not set
-# CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU is not set
-# CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI is not set
-CONFIG_EXTCON=y
-
-#
-# Extcon Device Drivers
-#
-CONFIG_EXTCON_ADC_JACK=m
-CONFIG_EXTCON_ARIZONA=m
-CONFIG_EXTCON_FSA9480=m
-CONFIG_EXTCON_GPIO=m
-CONFIG_EXTCON_MAX14577=m
-CONFIG_EXTCON_MAX3355=m
-CONFIG_EXTCON_MAX77693=m
-CONFIG_EXTCON_PTN5150=m
-# CONFIG_EXTCON_QCOM_SPMI_MISC is not set
-CONFIG_EXTCON_RT8973A=m
-CONFIG_EXTCON_SM5502=m
-CONFIG_EXTCON_USB_GPIO=m
-CONFIG_EXTCON_USBC_CROS_EC=m
-CONFIG_EXTCON_USBC_TUSB320=m
-CONFIG_MEMORY=y
-# CONFIG_ARM_PL172_MPMC is not set
-CONFIG_ATMEL_SDRAMC=y
-CONFIG_ATMEL_EBI=y
-# CONFIG_TI_AEMIF is not set
-# CONFIG_TI_EMIF is not set
-CONFIG_OMAP_GPMC=y
-# CONFIG_OMAP_GPMC_DEBUG is not set
-# CONFIG_TI_EMIF_SRAM is not set
-CONFIG_FPGA_DFL_EMIF=m
-CONFIG_MVEBU_DEVBUS=y
-CONFIG_PL353_SMC=y
-CONFIG_RENESAS_RPCIF=m
-CONFIG_STM32_FMC2_EBI=m
-CONFIG_SAMSUNG_MC=y
-# CONFIG_EXYNOS5422_DMC is not set
-CONFIG_EXYNOS_SROM=y
-CONFIG_TEGRA_MC=y
-CONFIG_IIO=m
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_BUFFER_CB=m
-CONFIG_IIO_BUFFER_DMA=m
-CONFIG_IIO_BUFFER_DMAENGINE=m
-CONFIG_IIO_BUFFER_HW_CONSUMER=m
-CONFIG_IIO_KFIFO_BUF=m
-CONFIG_IIO_TRIGGERED_BUFFER=m
-CONFIG_IIO_CONFIGFS=m
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
-CONFIG_IIO_SW_DEVICE=m
-CONFIG_IIO_SW_TRIGGER=m
-CONFIG_IIO_TRIGGERED_EVENT=m
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16201=m
-CONFIG_ADIS16209=m
-CONFIG_ADXL372=m
-CONFIG_ADXL372_SPI=m
-CONFIG_ADXL372_I2C=m
-CONFIG_BMA220=m
-CONFIG_BMA400=m
-CONFIG_BMA400_I2C=m
-CONFIG_BMA400_SPI=m
-CONFIG_BMC150_ACCEL=m
-CONFIG_BMI088_ACCEL=m
-CONFIG_BMC150_ACCEL_I2C=m
-CONFIG_BMC150_ACCEL_SPI=m
-CONFIG_DA280=m
-CONFIG_DA311=m
-# CONFIG_DMARD06 is not set
-CONFIG_DMARD09=m
-CONFIG_DMARD10=m
-CONFIG_FXLS8962AF_SPI=m
-CONFIG_FXLS8962AF_I2C=m
-CONFIG_HID_SENSOR_ACCEL_3D=m
-CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
-CONFIG_IIO_ST_ACCEL_3AXIS=m
-CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
-CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
-CONFIG_KXSD9=m
-CONFIG_KXSD9_SPI=m
-CONFIG_KXSD9_I2C=m
-CONFIG_KXCJK1013=m
-CONFIG_MC3230=m
-CONFIG_MMA7455=m
-CONFIG_MMA7455_I2C=m
-CONFIG_MMA7455_SPI=m
-CONFIG_MMA7660=m
-CONFIG_MMA8452=m
-CONFIG_MMA9551_CORE=m
-CONFIG_MMA9551=m
-CONFIG_MMA9553=m
-CONFIG_MSA311=m
-CONFIG_MXC4005=m
-CONFIG_MXC6255=m
-CONFIG_SCA3000=m
-CONFIG_SCA3300=m
-CONFIG_STK8312=m
-CONFIG_STK8BA50=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD_SIGMA_DELTA=m
-CONFIG_AD7091R5=m
-CONFIG_AD7124=m
-CONFIG_AD7192=m
-CONFIG_AD7266=m
-CONFIG_AD7291=m
-CONFIG_AD7292=m
-CONFIG_AD7298=m
-CONFIG_AD7476=m
-CONFIG_AD7606=m
-CONFIG_AD7606_IFACE_PARALLEL=m
-CONFIG_AD7606_IFACE_SPI=m
-CONFIG_AD7766=m
-CONFIG_AD7768_1=m
-CONFIG_AD7780=m
-CONFIG_AD7791=m
-CONFIG_AD7793=m
-CONFIG_AD7887=m
-CONFIG_AD7923=m
-CONFIG_AD7949=m
-CONFIG_AD799X=m
-CONFIG_AD9467=m
-CONFIG_ADI_AXI_ADC=m
-# CONFIG_ASPEED_ADC is not set
-# CONFIG_AT91_ADC is not set
-# CONFIG_AT91_SAMA5D2_ADC is not set
-CONFIG_AXP20X_ADC=m
-CONFIG_AXP288_ADC=m
-# CONFIG_BERLIN2_ADC is not set
-CONFIG_CC10001_ADC=m
-# CONFIG_CPCAP_ADC is not set
-CONFIG_DA9150_GPADC=m
-CONFIG_DLN2_ADC=m
-# CONFIG_ENVELOPE_DETECTOR is not set
-# CONFIG_EXYNOS_ADC is not set
-CONFIG_HI8435=m
-CONFIG_HX711=m
-CONFIG_INA2XX_ADC=m
-# CONFIG_IMX7D_ADC is not set
-CONFIG_IMX8QXP_ADC=m
-CONFIG_LTC2471=m
-CONFIG_LTC2485=m
-CONFIG_LTC2496=m
-CONFIG_LTC2497=m
-CONFIG_MAX1027=m
-CONFIG_MAX11100=m
-CONFIG_MAX1118=m
-CONFIG_MAX11205=m
-CONFIG_MAX1241=m
-CONFIG_MAX1363=m
-CONFIG_MAX9611=m
-CONFIG_MCP320X=m
-CONFIG_MCP3422=m
-CONFIG_MCP3911=m
-CONFIG_MEDIATEK_MT6360_ADC=m
-# CONFIG_MEDIATEK_MT6577_AUXADC is not set
-CONFIG_MEN_Z188_ADC=m
-CONFIG_MESON_SARADC=m
-CONFIG_MP2629_ADC=m
-CONFIG_NAU7802=m
-# CONFIG_NPCM_ADC is not set
-CONFIG_QCOM_VADC_COMMON=m
-# CONFIG_QCOM_PM8XXX_XOADC is not set
-CONFIG_QCOM_SPMI_IADC=m
-CONFIG_QCOM_SPMI_VADC=m
-CONFIG_QCOM_SPMI_ADC5=m
-# CONFIG_RN5T618_ADC is not set
-# CONFIG_ROCKCHIP_SARADC is not set
-CONFIG_RICHTEK_RTQ6056=m
-# CONFIG_SPEAR_ADC is not set
-# CONFIG_SD_ADC_MODULATOR is not set
-# CONFIG_STM32_ADC_CORE is not set
-# CONFIG_STM32_DFSDM_CORE is not set
-# CONFIG_STM32_DFSDM_ADC is not set
-# CONFIG_STMPE_ADC is not set
-# CONFIG_SUN4I_GPADC is not set
-CONFIG_TI_ADC081C=m
-CONFIG_TI_ADC0832=m
-CONFIG_TI_ADC084S021=m
-CONFIG_TI_ADC12138=m
-CONFIG_TI_ADC108S102=m
-CONFIG_TI_ADC128S052=m
-CONFIG_TI_ADC161S626=m
-CONFIG_TI_ADS1015=m
-CONFIG_TI_ADS7950=m
-CONFIG_TI_ADS8344=m
-# CONFIG_TI_ADS8688 is not set
-# CONFIG_TI_ADS124S08 is not set
-CONFIG_TI_ADS131E08=m
-CONFIG_TI_AM335X_ADC=m
-CONFIG_TI_TLC4541=m
-CONFIG_TI_TSC2046=m
-# CONFIG_TWL4030_MADC is not set
-# CONFIG_TWL6030_GPADC is not set
-# CONFIG_VF610_ADC is not set
-CONFIG_VIPERBOARD_ADC=m
-CONFIG_XILINX_XADC=m
-CONFIG_XILINX_AMS=m
-CONFIG_IIO_SCMI=m
-CONFIG_CROS_EC_MKBP_PROXIMITY=m
-# end of Analog to digital converters
-
-#
-# Analog Front Ends
-#
-# CONFIG_IIO_RESCALE is not set
-# end of Analog Front Ends
-
-#
-# Amplifiers
-#
-CONFIG_AD8366=m
-CONFIG_ADA4250=m
-CONFIG_HMC425=m
-# end of Amplifiers
-
-#
-# Chemical Sensors
-#
-CONFIG_ATLAS_PH_SENSOR=m
-CONFIG_ATLAS_EZO_SENSOR=m
-CONFIG_BME680=m
-CONFIG_BME680_I2C=m
-CONFIG_BME680_SPI=m
-CONFIG_CCS811=m
-CONFIG_IAQCORE=m
-CONFIG_PMS7003=m
-CONFIG_SCD30_CORE=m
-CONFIG_SCD30_I2C=m
-CONFIG_SCD30_SERIAL=m
-CONFIG_SENSIRION_SGP30=m
-CONFIG_SPS30_I2C=m
-CONFIG_SPS30_SERIAL=m
-CONFIG_SPS30=m
-CONFIG_VZ89X=m
-# end of Chemical Sensors
-
-CONFIG_IIO_CROS_EC_SENSORS_CORE=m
-CONFIG_IIO_CROS_EC_SENSORS=m
-CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m
-
-#
-# Hid Sensor IIO Common
-#
-CONFIG_HID_SENSOR_IIO_COMMON=m
-CONFIG_HID_SENSOR_IIO_TRIGGER=m
-# end of Hid Sensor IIO Common
-
-CONFIG_IIO_MS_SENSORS_I2C=m
-
-#
-# SSP Sensor Common
-#
-CONFIG_IIO_SSP_SENSORS_COMMONS=m
-CONFIG_IIO_SSP_SENSORHUB=m
-# end of SSP Sensor Common
-
-CONFIG_IIO_ST_SENSORS_I2C=m
-CONFIG_IIO_ST_SENSORS_SPI=m
-CONFIG_IIO_ST_SENSORS_CORE=m
-
-#
-# Digital to analog converters
-#
-CONFIG_AD5064=m
-CONFIG_AD5360=m
-CONFIG_AD5380=m
-CONFIG_AD5421=m
-CONFIG_AD5446=m
-CONFIG_AD5449=m
-CONFIG_AD5592R_BASE=m
-CONFIG_AD5592R=m
-CONFIG_AD5593R=m
-CONFIG_AD5504=m
-CONFIG_AD5624R_SPI=m
-CONFIG_LTC2688=m
-CONFIG_AD5686=m
-CONFIG_AD5686_SPI=m
-CONFIG_AD5696_I2C=m
-CONFIG_AD5755=m
-CONFIG_AD5758=m
-CONFIG_AD5761=m
-CONFIG_AD5764=m
-CONFIG_AD5766=m
-CONFIG_AD5770R=m
-CONFIG_AD5791=m
-CONFIG_AD7303=m
-CONFIG_AD8801=m
-# CONFIG_DPOT_DAC is not set
-CONFIG_DS4424=m
-CONFIG_LTC1660=m
-CONFIG_LTC2632=m
-CONFIG_M62332=m
-CONFIG_MAX517=m
-# CONFIG_MAX5821 is not set
-CONFIG_MCP4725=m
-CONFIG_MCP4922=m
-# CONFIG_STM32_DAC is not set
-CONFIG_TI_DAC082S085=m
-CONFIG_TI_DAC5571=m
-CONFIG_TI_DAC7311=m
-CONFIG_TI_DAC7612=m
-# CONFIG_VF610_DAC is not set
-# end of Digital to analog converters
-
-#
-# IIO dummy driver
-#
-# CONFIG_IIO_SIMPLE_DUMMY is not set
-# end of IIO dummy driver
-
-#
-# Frequency Synthesizers DDS/PLL
-#
-
-#
-# Clock Generator/Distribution
-#
-CONFIG_AD9523=m
-# end of Clock Generator/Distribution
-
-#
-# Phase-Locked Loop (PLL) frequency synthesizers
-#
-CONFIG_ADF4350=m
-CONFIG_ADF4371=m
-# end of Phase-Locked Loop (PLL) frequency synthesizers
-# end of Frequency Synthesizers DDS/PLL
-
-#
-# Digital gyroscope sensors
-#
-CONFIG_ADIS16080=m
-CONFIG_ADIS16130=m
-CONFIG_ADIS16136=m
-CONFIG_ADIS16260=m
-CONFIG_ADXRS290=m
-CONFIG_ADXRS450=m
-CONFIG_BMG160=m
-CONFIG_BMG160_I2C=m
-CONFIG_BMG160_SPI=m
-CONFIG_FXAS21002C=m
-CONFIG_FXAS21002C_I2C=m
-CONFIG_FXAS21002C_SPI=m
-CONFIG_HID_SENSOR_GYRO_3D=m
-CONFIG_MPU3050=m
-CONFIG_MPU3050_I2C=m
-CONFIG_IIO_ST_GYRO_3AXIS=m
-CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
-CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
-CONFIG_ITG3200=m
-# end of Digital gyroscope sensors
-
-#
-# Health Sensors
-#
-
-#
-# Heart Rate Monitors
-#
-CONFIG_AFE4403=m
-CONFIG_AFE4404=m
-CONFIG_MAX30100=m
-CONFIG_MAX30102=m
-# end of Heart Rate Monitors
-# end of Health Sensors
-
-#
-# Humidity sensors
-#
-CONFIG_AM2315=m
-CONFIG_DHT11=m
-CONFIG_HDC100X=m
-CONFIG_HDC2010=m
-CONFIG_HID_SENSOR_HUMIDITY=m
-CONFIG_HTS221=m
-CONFIG_HTS221_I2C=m
-CONFIG_HTS221_SPI=m
-CONFIG_HTU21=m
-CONFIG_SI7005=m
-CONFIG_SI7020=m
-# end of Humidity sensors
-
-#
-# Inertial measurement units
-#
-CONFIG_ADIS16400=m
-CONFIG_ADIS16460=m
-CONFIG_ADIS16475=m
-CONFIG_ADIS16480=m
-CONFIG_BMI160=m
-CONFIG_BMI160_I2C=m
-CONFIG_BMI160_SPI=m
-CONFIG_BOSCH_BNO055_SERIAL=m
-CONFIG_BOSCH_BNO055_I2C=m
-CONFIG_FXOS8700=m
-CONFIG_FXOS8700_I2C=m
-CONFIG_FXOS8700_SPI=m
-CONFIG_KMX61=m
-CONFIG_INV_ICM42600=m
-CONFIG_INV_ICM42600_I2C=m
-CONFIG_INV_ICM42600_SPI=m
-CONFIG_INV_MPU6050_IIO=m
-CONFIG_INV_MPU6050_I2C=m
-CONFIG_INV_MPU6050_SPI=m
-CONFIG_IIO_ST_LSM6DSX=m
-CONFIG_IIO_ST_LSM9DS0=m
-CONFIG_IIO_ST_LSM9DS0_I2C=m
-CONFIG_IIO_ST_LSM9DS0_SPI=m
-CONFIG_IIO_ST_LSM6DSX_I2C=m
-CONFIG_IIO_ST_LSM6DSX_SPI=m
-CONFIG_IIO_ST_LSM6DSX_I3C=m
-# end of Inertial measurement units
-
-CONFIG_IIO_ADIS_LIB=m
-CONFIG_IIO_ADIS_LIB_BUFFER=y
-
-#
-# Light sensors
-#
-CONFIG_ADJD_S311=m
-CONFIG_ADUX1020=m
-CONFIG_AL3010=m
-CONFIG_AL3320A=m
-CONFIG_APDS9300=m
-CONFIG_APDS9960=m
-CONFIG_AS73211=m
-CONFIG_BH1750=m
-CONFIG_BH1780=m
-CONFIG_CM32181=m
-CONFIG_CM3232=m
-CONFIG_CM3323=m
-# CONFIG_CM3605 is not set
-CONFIG_CM36651=m
-CONFIG_IIO_CROS_EC_LIGHT_PROX=m
-CONFIG_GP2AP002=m
-CONFIG_GP2AP020A00F=m
-CONFIG_IQS621_ALS=m
-CONFIG_SENSORS_ISL29018=m
-CONFIG_SENSORS_ISL29028=m
-CONFIG_ISL29125=m
-CONFIG_HID_SENSOR_ALS=m
-CONFIG_HID_SENSOR_PROX=m
-CONFIG_JSA1212=m
-CONFIG_RPR0521=m
-CONFIG_SENSORS_LM3533=m
-CONFIG_LTR501=m
-CONFIG_LTRF216A=m
-CONFIG_LV0104CS=m
-CONFIG_MAX44000=m
-CONFIG_MAX44009=m
-CONFIG_NOA1305=m
-CONFIG_OPT3001=m
-CONFIG_PA12203001=m
-CONFIG_SI1133=m
-CONFIG_SI1145=m
-CONFIG_STK3310=m
-CONFIG_ST_UVIS25=m
-CONFIG_ST_UVIS25_I2C=m
-CONFIG_ST_UVIS25_SPI=m
-CONFIG_TCS3414=m
-CONFIG_TCS3472=m
-CONFIG_SENSORS_TSL2563=m
-CONFIG_TSL2583=m
-CONFIG_TSL2591=m
-CONFIG_TSL2772=m
-CONFIG_TSL4531=m
-CONFIG_US5182D=m
-CONFIG_VCNL4000=m
-CONFIG_VCNL4035=m
-CONFIG_VEML6030=m
-CONFIG_VEML6070=m
-CONFIG_VL6180=m
-CONFIG_ZOPT2201=m
-# end of Light sensors
-
-#
-# Magnetometer sensors
-#
-# CONFIG_AK8974 is not set
-CONFIG_AK8975=m
-CONFIG_AK09911=m
-CONFIG_BMC150_MAGN=m
-CONFIG_BMC150_MAGN_I2C=m
-CONFIG_BMC150_MAGN_SPI=m
-CONFIG_MAG3110=m
-CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
-CONFIG_MMC35240=m
-CONFIG_IIO_ST_MAGN_3AXIS=m
-CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
-CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
-CONFIG_SENSORS_HMC5843=m
-CONFIG_SENSORS_HMC5843_I2C=m
-CONFIG_SENSORS_HMC5843_SPI=m
-CONFIG_SENSORS_RM3100=m
-CONFIG_SENSORS_RM3100_I2C=m
-CONFIG_SENSORS_RM3100_SPI=m
-CONFIG_YAMAHA_YAS530=m
-# end of Magnetometer sensors
-
-#
-# Multiplexers
-#
-# CONFIG_IIO_MUX is not set
-# end of Multiplexers
-
-#
-# Inclinometer sensors
-#
-CONFIG_HID_SENSOR_INCLINOMETER_3D=m
-CONFIG_HID_SENSOR_DEVICE_ROTATION=m
-# end of Inclinometer sensors
-
-#
-# Triggers - standalone
-#
-CONFIG_IIO_HRTIMER_TRIGGER=m
-CONFIG_IIO_INTERRUPT_TRIGGER=m
-CONFIG_IIO_TIGHTLOOP_TRIGGER=m
-CONFIG_IIO_SYSFS_TRIGGER=m
-# end of Triggers - standalone
-
-#
-# Linear and angular position sensors
-#
-CONFIG_IQS624_POS=m
-CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
-# end of Linear and angular position sensors
-
-#
-# Digital potentiometers
-#
-CONFIG_AD5272=m
-CONFIG_DS1803=m
-CONFIG_MAX5432=m
-CONFIG_MAX5481=m
-CONFIG_MAX5487=m
-CONFIG_MCP4018=m
-CONFIG_MCP4131=m
-CONFIG_MCP4531=m
-CONFIG_MCP41010=m
-CONFIG_TPL0102=m
-# end of Digital potentiometers
-
-#
-# Digital potentiostats
-#
-CONFIG_LMP91000=m
-# end of Digital potentiostats
-
-#
-# Pressure sensors
-#
-CONFIG_ABP060MG=m
-CONFIG_BMP280=m
-CONFIG_BMP280_I2C=m
-CONFIG_BMP280_SPI=m
-CONFIG_IIO_CROS_EC_BARO=m
-CONFIG_DLHL60D=m
-CONFIG_DPS310=m
-CONFIG_HID_SENSOR_PRESS=m
-CONFIG_HP03=m
-CONFIG_ICP10100=m
-CONFIG_MPL115=m
-CONFIG_MPL115_I2C=m
-CONFIG_MPL115_SPI=m
-CONFIG_MPL3115=m
-CONFIG_MS5611=m
-CONFIG_MS5611_I2C=m
-CONFIG_MS5611_SPI=m
-CONFIG_MS5637=m
-CONFIG_IIO_ST_PRESS=m
-CONFIG_IIO_ST_PRESS_I2C=m
-CONFIG_IIO_ST_PRESS_SPI=m
-CONFIG_T5403=m
-CONFIG_HP206C=m
-CONFIG_ZPA2326=m
-CONFIG_ZPA2326_I2C=m
-CONFIG_ZPA2326_SPI=m
-# end of Pressure sensors
-
-#
-# Lightning sensors
-#
-CONFIG_AS3935=m
-# end of Lightning sensors
-
-#
-# Proximity and distance sensors
-#
-CONFIG_ISL29501=m
-CONFIG_LIDAR_LITE_V2=m
-CONFIG_MB1232=m
-CONFIG_PING=m
-CONFIG_RFD77402=m
-CONFIG_SRF04=m
-CONFIG_SX9310=m
-CONFIG_SX9324=m
-CONFIG_SX9360=m
-CONFIG_SX9500=m
-CONFIG_SRF08=m
-CONFIG_VCNL3020=m
-CONFIG_VL53L0X_I2C=m
-# end of Proximity and distance sensors
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S90=m
-CONFIG_AD2S1200=m
-# end of Resolver to digital converters
-
-#
-# Temperature sensors
-#
-CONFIG_IQS620AT_TEMP=m
-CONFIG_LTC2983=m
-CONFIG_MAXIM_THERMOCOUPLE=m
-CONFIG_HID_SENSOR_TEMP=m
-CONFIG_MLX90614=m
-CONFIG_MLX90632=m
-CONFIG_TMP006=m
-CONFIG_TMP007=m
-CONFIG_TMP117=m
-CONFIG_TSYS01=m
-CONFIG_TSYS02D=m
-CONFIG_MAX31856=m
-# end of Temperature sensors
-
-CONFIG_NTB=m
-CONFIG_NTB_MSI=y
-CONFIG_NTB_IDT=m
-CONFIG_NTB_EPF=m
-CONFIG_NTB_SWITCHTEC=m
-CONFIG_NTB_PINGPONG=m
-CONFIG_NTB_TOOL=m
-CONFIG_NTB_PERF=m
-CONFIG_NTB_MSI_TEST=m
-CONFIG_NTB_TRANSPORT=m
-CONFIG_VME_BUS=y
-
-#
-# VME Bridge Drivers
-#
-CONFIG_VME_TSI148=m
-CONFIG_VME_FAKE=m
-
-#
-# VME Board Drivers
-#
-CONFIG_VMIVME_7805=m
-
-#
-# VME Device Drivers
-#
-CONFIG_VME_USER=m
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_PWM_DEBUG is not set
-# CONFIG_PWM_AB8500 is not set
-# CONFIG_PWM_ATMEL is not set
-CONFIG_PWM_ATMEL_TCB=m
-# CONFIG_PWM_ATMEL_HLCDC_PWM is not set
-# CONFIG_PWM_BERLIN is not set
-CONFIG_PWM_CROS_EC=m
-CONFIG_PWM_DWC=m
-# CONFIG_PWM_FSL_FTM is not set
-# CONFIG_PWM_HIBVT is not set
-# CONFIG_PWM_IMX1 is not set
-# CONFIG_PWM_IMX27 is not set
-# CONFIG_PWM_IMX_TPM is not set
-CONFIG_PWM_IQS620A=m
-CONFIG_PWM_LP3943=m
-# CONFIG_PWM_MESON is not set
-# CONFIG_PWM_MTK_DISP is not set
-# CONFIG_PWM_MEDIATEK is not set
-CONFIG_PWM_NTXEC=m
-# CONFIG_PWM_OMAP_DMTIMER is not set
-CONFIG_PWM_PCA9685=m
-CONFIG_PWM_RASPBERRYPI_POE=m
-# CONFIG_PWM_RCAR is not set
-# CONFIG_PWM_RENESAS_TPU is not set
-# CONFIG_PWM_ROCKCHIP is not set
-# CONFIG_PWM_SAMSUNG is not set
-CONFIG_PWM_SL28CPLD=m
-# CONFIG_PWM_SPEAR is not set
-# CONFIG_PWM_STI is not set
-# CONFIG_PWM_STMPE is not set
-# CONFIG_PWM_SUN4I is not set
-# CONFIG_PWM_TEGRA is not set
-# CONFIG_PWM_TIECAP is not set
-# CONFIG_PWM_TIEHRPWM is not set
-CONFIG_PWM_VISCONTI=m
-# CONFIG_PWM_TWL is not set
-# CONFIG_PWM_TWL_LED is not set
-# CONFIG_PWM_VT8500 is not set
-# CONFIG_PWM_ZX is not set
-
-#
-# IRQ chip support
-#
-CONFIG_IRQCHIP=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_MAX_NR=2
-CONFIG_GIC_NON_BANKED=y
-CONFIG_ARM_VIC=y
-CONFIG_ARM_VIC_NR=4
-CONFIG_ALPINE_MSI=y
-# CONFIG_AL_FIC is not set
-CONFIG_XILINX_INTC=y
-CONFIG_DW_APB_ICTL=y
-CONFIG_MADERA_IRQ=m
-CONFIG_OMAP_IRQCHIP=y
-CONFIG_RDA_INTC=y
-CONFIG_ST_IRQCHIP=y
-CONFIG_TANGO_IRQ=y
-CONFIG_IRQ_CROSSBAR=y
-# CONFIG_KEYSTONE_IRQ is not set
-CONFIG_STM32_EXTI=y
-CONFIG_IRQ_UNIPHIER_AIDET=y
-CONFIG_MESON_IRQ_GPIO=y
-# CONFIG_QCOM_PDC is not set
-CONFIG_QCOM_MPM=m
-CONFIG_IMX_IRQSTEER=y
-CONFIG_IMX_MU_MSI=m
-CONFIG_IMX_INTMUX=y
-CONFIG_TI_PRUSS_INTC=m
-CONFIG_EXYNOS_IRQ_COMBINER=y
-CONFIG_MST_IRQ=y
-# end of IRQ chip support
-
-# CONFIG_IPACK_BUS is not set
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_RESET_A10SR=m
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_MCHP_SPARX5=y
-CONFIG_RESET_BERLIN=y
-CONFIG_RESET_MCHP_SPARX5=y
-# CONFIG_RESET_BRCMSTB_RESCAL is not set
-# CONFIG_RESET_INTEL_GW is not set
-CONFIG_RESET_MESON=y
-# CONFIG_RESET_MESON_AUDIO_ARB is not set
-CONFIG_RESET_NPCM=y
-# CONFIG_RESET_QCOM_AOSS is not set
-# CONFIG_RESET_QCOM_PDC is not set
-CONFIG_RESET_SCMI=y
-CONFIG_RESET_SIMPLE=y
-CONFIG_RESET_STM32MP157=y
-CONFIG_RESET_SOCFPGA=y
-CONFIG_RESET_SUNXI=y
-CONFIG_RESET_TI_SYSCON=m
-CONFIG_RESET_UNIPHIER=y
-CONFIG_RESET_UNIPHIER_GLUE=y
-CONFIG_RESET_ZYNQ=y
-CONFIG_STI_RESET_SYSCFG=y
-CONFIG_STIH407_RESET=y
-CONFIG_COMMON_RESET_HI3660=y
-CONFIG_COMMON_RESET_HI6220=y
-
-#
-# PHY Subsystem
-#
-CONFIG_GENERIC_PHY=y
-CONFIG_PHY_CAN_TRANSCEIVER=m
-CONFIG_GENERIC_PHY_MIPI_DPHY=y
-CONFIG_USB_LGM_PHY=m
-# CONFIG_PHY_SUN4I_USB is not set
-# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
-# CONFIG_PHY_SUN9I_USB is not set
-# CONFIG_PHY_SUN50I_USB3 is not set
-CONFIG_PHY_MESON8B_USB2=y
-CONFIG_PHY_MESON_GXL_USB2=y
-CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=m
-CONFIG_PHY_MIXEL_LVDS_PHY=m
-CONFIG_PHY_MTK_PCIE=m
-CONFIG_PHY_MTK_DP=m
-CONFIG_PHY_MESON_G12A_USB2=y
-CONFIG_PHY_MESON_G12A_USB3_PCIE=y
-CONFIG_PHY_MESON_AXG_PCIE=y
-CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
-CONFIG_PHY_MESON_AXG_MIPI_DPHY=m
-CONFIG_BCM_KONA_USB2_PHY=m
-# CONFIG_PHY_CADENCE_TORRENT is not set
-# CONFIG_PHY_CADENCE_DPHY is not set
-CONFIG_PHY_CADENCE_DPHY_RX=m
-# CONFIG_PHY_CADENCE_SIERRA is not set
-# CONFIG_PHY_CADENCE_SALVO is not set
-# CONFIG_PHY_FSL_IMX8MQ_USB is not set
-# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
-# CONFIG_PHY_HIX5HD2_SATA is not set
-# CONFIG_PHY_BERLIN_SATA is not set
-# CONFIG_PHY_BERLIN_USB is not set
-CONFIG_PHY_MVEBU_A3700_COMPHY=y
-CONFIG_PHY_MVEBU_A3700_UTMI=y
-# CONFIG_PHY_MVEBU_A38X_COMPHY is not set
-# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
-CONFIG_PHY_MVEBU_CP110_UTMI=m
-CONFIG_PHY_PXA_28NM_HSIC=m
-CONFIG_PHY_PXA_28NM_USB2=m
-# CONFIG_PHY_PXA_USB is not set
-# CONFIG_PHY_MTK_TPHY is not set
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PHY_MTK_HDMI=m
-CONFIG_PHY_MTK_MIPI_DSI=m
-CONFIG_PHY_SPARX5_SERDES=m
-CONFIG_PHY_CPCAP_USB=m
-# CONFIG_PHY_MAPPHONE_MDM6600 is not set
-# CONFIG_PHY_OCELOT_SERDES is not set
-# CONFIG_PHY_QCOM_APQ8064_SATA is not set
-# CONFIG_PHY_QCOM_IPQ4019_USB is not set
-# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
-# CONFIG_PHY_QCOM_PCIE2 is not set
-# CONFIG_PHY_QCOM_QMP is not set
-# CONFIG_PHY_QCOM_QUSB2 is not set
-CONFIG_PHY_QCOM_USB_HS=m
-# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
-CONFIG_PHY_QCOM_USB_HSIC=m
-# CONFIG_PHY_QCOM_USB_HS_28NM is not set
-# CONFIG_PHY_QCOM_USB_SS is not set
-CONFIG_PHY_QCOM_IPQ806X_USB=m
-# CONFIG_PHY_RCAR_GEN2 is not set
-# CONFIG_PHY_RCAR_GEN3_PCIE is not set
-# CONFIG_PHY_RCAR_GEN3_USB2 is not set
-# CONFIG_PHY_RCAR_GEN3_USB3 is not set
-# CONFIG_PHY_ROCKCHIP_DP is not set
-# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
-# CONFIG_PHY_ROCKCHIP_EMMC is not set
-# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
-# CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set
-CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m
-# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
-CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
-# CONFIG_PHY_ROCKCHIP_PCIE is not set
-CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m
-# CONFIG_PHY_ROCKCHIP_TYPEC is not set
-# CONFIG_PHY_ROCKCHIP_USB is not set
-CONFIG_PHY_EXYNOS_DP_VIDEO=y
-CONFIG_PHY_EXYNOS_MIPI_VIDEO=y
-# CONFIG_PHY_EXYNOS_PCIE is not set
-CONFIG_PHY_SAMSUNG_UFS=m
-CONFIG_PHY_SAMSUNG_USB2=m
-CONFIG_PHY_EXYNOS4210_USB2=y
-CONFIG_PHY_EXYNOS4X12_USB2=y
-CONFIG_PHY_EXYNOS5250_USB2=y
-# CONFIG_PHY_S5PV210_USB2 is not set
-CONFIG_PHY_EXYNOS5_USBDRD=m
-# CONFIG_PHY_EXYNOS5250_SATA is not set
-# CONFIG_PHY_UNIPHIER_USB2 is not set
-# CONFIG_PHY_UNIPHIER_USB3 is not set
-# CONFIG_PHY_UNIPHIER_PCIE is not set
-CONFIG_PHY_UNIPHIER_AHCI=m
-# CONFIG_PHY_MIPHY28LP is not set
-CONFIG_PHY_ST_SPEAR1310_MIPHY=y
-CONFIG_PHY_ST_SPEAR1340_MIPHY=y
-# CONFIG_PHY_STIH407_USB is not set
-# CONFIG_PHY_STM32_USBPHYC is not set
-CONFIG_PHY_SUNPLUS_USB=m
-# CONFIG_PHY_TEGRA_XUSB is not set
-# CONFIG_PHY_DM816X_USB is not set
-# CONFIG_OMAP_CONTROL_PHY is not set
-# CONFIG_OMAP_USB2 is not set
-# CONFIG_TI_PIPE3 is not set
-CONFIG_PHY_TUSB1210=m
-# end of PHY Subsystem
-
-CONFIG_POWERCAP=y
-# CONFIG_IDLE_INJECT is not set
-CONFIG_DTPM=y
-CONFIG_DTPM_CPU=y
-CONFIG_DTPM_DEVFREQ=y
-CONFIG_MCB=m
-CONFIG_MCB_PCI=m
-CONFIG_MCB_LPC=m
-
-#
-# Performance monitor support
-#
-CONFIG_ARM_CCI_PMU=m
-CONFIG_ARM_CCI400_PMU=y
-CONFIG_ARM_CCI5xx_PMU=y
-CONFIG_ARM_CCN=m
-CONFIG_ARM_PMU=y
-# CONFIG_FSL_IMX8_DDR_PMU is not set
-# end of Performance monitor support
-
-CONFIG_RAS=y
-CONFIG_USB4=m
-# CONFIG_USB4_DEBUGFS_WRITE is not set
-# CONFIG_USB4_DMA_TEST is not set
-
-#
-# Android
-#
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=m
-CONFIG_ANDROID_BINDERFS=y
-CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
-# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
-# end of Android
-
-# CONFIG_LIBNVDIMM is not set
-CONFIG_DAX=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-# CONFIG_NVMEM_IMX_IIM is not set
-# CONFIG_NVMEM_IMX_OCOTP is not set
-CONFIG_NVMEM_LAN9662_OTPC=m
-CONFIG_NVMEM_MESON_MX_EFUSE=m
-CONFIG_NVMEM_MICROCHIP_OTPC=m
-CONFIG_NVMEM_MTK_EFUSE=m
-CONFIG_NVMEM_QCOM_QFPROM=m
-CONFIG_NVMEM_RAVE_SP_EEPROM=m
-CONFIG_NVMEM_ROCKCHIP_EFUSE=m
-CONFIG_NVMEM_ROCKCHIP_OTP=m
-CONFIG_NVMEM_SC27XX_EFUSE=m
-# CONFIG_MTK_EFUSE is not set
-# CONFIG_QCOM_QFPROM is not set
-CONFIG_NVMEM_SPMI_SDAM=m
-# CONFIG_ROCKCHIP_EFUSE is not set
-# CONFIG_ROCKCHIP_OTP is not set
-# CONFIG_NVMEM_STM32_ROMEM is not set
-# CONFIG_NVMEM_SUNXI_SID is not set
-CONFIG_NVMEM_U_BOOT_ENV=m
-CONFIG_NVMEM_UNIPHIER_EFUSE=m
-# CONFIG_UNIPHIER_EFUSE is not set
-# CONFIG_MESON_MX_EFUSE is not set
-# CONFIG_NVMEM_SNVS_LPGPR is not set
-CONFIG_RAVE_SP_EEPROM=m
-CONFIG_NVMEM_RMEM=m
-CONFIG_NVMEM_LAYERSCAPE_SFP=m
-CONFIG_NVMEM_MESON_EFUSE=m
-CONFIG_NVMEM_SPRD_EFUSE=m
-
-#
-# HW tracing support
-#
-CONFIG_STM=m
-CONFIG_STM_PROTO_BASIC=m
-CONFIG_STM_PROTO_SYS_T=m
-# CONFIG_STM_DUMMY is not set
-CONFIG_STM_SOURCE_CONSOLE=m
-CONFIG_STM_SOURCE_HEARTBEAT=m
-# CONFIG_STM_SOURCE_FTRACE is not set
-# CONFIG_INTEL_TH is not set
-CONFIG_HISI_PTT=m
-# end of HW tracing support
-
-CONFIG_FPGA=m
-CONFIG_FPGA_MGR_SOCFPGA=m
-CONFIG_FPGA_MGR_SOCFPGA_A10=m
-# CONFIG_FPGA_MGR_SOCFPGA is not set
-# CONFIG_FPGA_MGR_SOCFPGA_A10 is not set
-CONFIG_ALTERA_PR_IP_CORE=m
-# CONFIG_ALTERA_PR_IP_CORE_PLAT is not set
-CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
-CONFIG_FPGA_MGR_ALTERA_CVP=m
-# CONFIG_FPGA_MGR_ZYNQ_FPGA is not set
-CONFIG_FPGA_MGR_XILINX_SPI=m
-# CONFIG_FPGA_MGR_ICE40_SPI is not set
-CONFIG_FPGA_MGR_MACHXO2_SPI=m
-CONFIG_FPGA_BRIDGE=m
-# CONFIG_SOCFPGA_FPGA_BRIDGE is not set
-CONFIG_ALTERA_FREEZE_BRIDGE=m
-CONFIG_XILINX_PR_DECOUPLER=m
-CONFIG_FPGA_REGION=m
-# CONFIG_OF_FPGA_REGION is not set
-CONFIG_FPGA_DFL=m
-CONFIG_FPGA_DFL_FME=m
-CONFIG_FPGA_DFL_FME_MGR=m
-CONFIG_FPGA_DFL_FME_BRIDGE=m
-CONFIG_FPGA_DFL_FME_REGION=m
-CONFIG_FPGA_DFL_AFU=m
-CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
-CONFIG_FPGA_DFL_PCI=m
-# CONFIG_FSI is not set
-CONFIG_TEE=m
-
-#
-# TEE drivers
-#
-# CONFIG_OPTEE is not set
-# end of TEE drivers
-
-CONFIG_MULTIPLEXER=m
-
-#
-# Multiplexer drivers
-#
-CONFIG_MUX_ADG792A=m
-CONFIG_MUX_ADGS1408=m
-CONFIG_MUX_GPIO=m
-# CONFIG_MUX_MMIO is not set
-# end of Multiplexer drivers
-
-CONFIG_PM_OPP=y
-CONFIG_SIOX=m
-CONFIG_SIOX_BUS_GPIO=m
-CONFIG_SLIMBUS=m
-CONFIG_SLIM_QCOM_CTRL=m
-# CONFIG_SLIM_QCOM_NGD_CTRL is not set
-CONFIG_INTERCONNECT=y
-CONFIG_INTERCONNECT_IMX=m
-CONFIG_INTERCONNECT_IMX8MM=m
-CONFIG_INTERCONNECT_IMX8MN=m
-CONFIG_INTERCONNECT_IMX8MQ=m
-CONFIG_INTERCONNECT_QCOM=y
-CONFIG_INTERCONNECT_QCOM_OSM_L3=m
-CONFIG_INTERCONNECT_QCOM_QCM2290=m
-CONFIG_INTERCONNECT_SAMSUNG=y
-CONFIG_INTERCONNECT_EXYNOS=m
-CONFIG_COUNTER=m
-CONFIG_INTERRUPT_CNT=m
-CONFIG_INTEL_QEP=m
-CONFIG_TI_ECAP_CAPTURE=m
-# CONFIG_TI_EQEP is not set
-CONFIG_FTM_QUADDEC=m
-CONFIG_MICROCHIP_TCB_CAPTURE=m
-CONFIG_INTEL_QEP=m
-CONFIG_MOST=m
-CONFIG_MOST_USB_HDM=m
-CONFIG_MOST_CDEV=m
-CONFIG_MOST_SND=m
-CONFIG_NETFS_SUPPORT=m
-CONFIG_NETFS_STATS=y
-# end of Device Drivers
-
-#
-# File systems
-#
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_VALIDATE_FS_PARSER=y
-CONFIG_FS_IOMAP=y
-# CONFIG_EXT2_FS is not set
-# CONFIG_EXT3_FS is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_USE_FOR_EXT2=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD2=m
-# CONFIG_JBD2_DEBUG is not set
-CONFIG_FS_MBCACHE=m
-# CONFIG_REISERFS_FS is not set
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_SECURITY=y
-# CONFIG_JFS_DEBUG is not set
-CONFIG_JFS_STATISTICS=y
-CONFIG_XFS_FS=m
-# CONFIG_XFS_SUPPORT_V4 is not set
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_XFS_ONLINE_SCRUB=y
-# CONFIG_XFS_ONLINE_REPAIR is not set
-# CONFIG_XFS_WARN is not set
-# CONFIG_XFS_DEBUG is not set
-CONFIG_GFS2_FS=m
-CONFIG_GFS2_FS_LOCKING_DLM=y
-CONFIG_OCFS2_FS=m
-CONFIG_OCFS2_FS_O2CB=m
-CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
-CONFIG_OCFS2_FS_STATS=y
-CONFIG_OCFS2_DEBUG_MASKLOG=y
-CONFIG_OCFS2_DEBUG_FS=y
-CONFIG_BTRFS_FS=m
-CONFIG_BTRFS_FS_POSIX_ACL=y
-# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
-# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
-# CONFIG_BTRFS_DEBUG is not set
-# CONFIG_BTRFS_ASSERT is not set
-# CONFIG_BTRFS_FS_REF_VERIFY is not set
-CONFIG_NILFS2_FS=m
-CONFIG_F2FS_FS=m
-CONFIG_F2FS_STAT_FS=y
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_FS_POSIX_ACL=y
-CONFIG_F2FS_FS_SECURITY=y
-# CONFIG_F2FS_CHECK_FS is not set
-# CONFIG_F2FS_IO_TRACE is not set
-# CONFIG_F2FS_FAULT_INJECTION is not set
-CONFIG_F2FS_FS_COMPRESSION=y
-CONFIG_F2FS_FS_LZO=y
-CONFIG_F2FS_FS_LZ4=y
-CONFIG_F2FS_FS_LZ4HC=y
-CONFIG_F2FS_FS_ZSTD=y
-CONFIG_F2FS_FS_LZORLE=y
-CONFIG_ZONEFS_FS=m
-CONFIG_FS_POSIX_ACL=y
-CONFIG_EXPORTFS=y
-CONFIG_EXPORTFS_BLOCK_OPS=y
-CONFIG_FILE_LOCKING=y
-CONFIG_MANDATORY_FILE_LOCKING=y
-CONFIG_FS_ENCRYPTION=y
-CONFIG_FS_ENCRYPTION_ALGS=m
-# CONFIG_FS_VERITY is not set
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY_USER=y
-CONFIG_FANOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-# CONFIG_QUOTA_DEBUG is not set
-CONFIG_QUOTA_TREE=m
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=m
-CONFIG_QUOTACTL=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_AUTOFS_FS=y
-CONFIG_FUSE_FS=m
-CONFIG_CUSE=m
-CONFIG_VIRTIO_FS=m
-CONFIG_OVERLAY_FS=m
-CONFIG_OVERLAY_FS_REDIRECT_DIR=y
-CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
-CONFIG_OVERLAY_FS_INDEX=y
-CONFIG_OVERLAY_FS_NFS_EXPORT=y
-# CONFIG_OVERLAY_FS_METACOPY is not set
-
-#
-# Caches
-#
-CONFIG_FSCACHE=m
-CONFIG_FSCACHE_STATS=y
-# CONFIG_FSCACHE_HISTOGRAM is not set
-# CONFIG_FSCACHE_DEBUG is not set
-# CONFIG_FSCACHE_OBJECT_LIST is not set
-CONFIG_CACHEFILES=m
-# CONFIG_CACHEFILES_DEBUG is not set
-# CONFIG_CACHEFILES_HISTOGRAM is not set
-# end of Caches
-
-#
-# CD-ROM/DVD Filesystems
-#
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-# end of CD-ROM/DVD Filesystems
-
-#
-# DOS/FAT/EXFAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
-# CONFIG_FAT_DEFAULT_UTF8 is not set
-CONFIG_EXFAT_FS=m
-CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-CONFIG_NTFS_RW=y
-CONFIG_NTFS3_FS=m
-CONFIG_NTFS3_LZX_XPRESS=y
-CONFIG_NTFS3_FS_POSIX_ACL=y
-# CONFIG_NTFS3_64BIT_CLUSTER is not set
-# end of DOS/FAT/EXFAT/NT Filesystems
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_CHILDREN=y
-CONFIG_KERNFS=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TMPFS_XATTR=y
-# CONFIG_HUGETLBFS is not set
-CONFIG_HUGETLB_PAGE_FREE_VMEMMAP_DEFAULT_ON=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_EFIVAR_FS=m
-# end of Pseudo filesystems
-
-CONFIG_MISC_FILESYSTEMS=y
-CONFIG_ORANGEFS_FS=m
-CONFIG_ADFS_FS=m
-# CONFIG_ADFS_FS_RW is not set
-CONFIG_AFFS_FS=m
-CONFIG_ECRYPT_FS=m
-CONFIG_ECRYPT_FS_MESSAGING=y
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-# CONFIG_BEFS_FS is not set
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RTIME=y
-CONFIG_JFFS2_RUBIN=y
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-CONFIG_UBIFS_FS=m
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UBIFS_FS_ZSTD=y
-CONFIG_UBIFS_ATIME_SUPPORT=y
-CONFIG_UBIFS_FS_XATTR=y
-CONFIG_UBIFS_FS_SECURITY=y
-# CONFIG_UBIFS_FS_AUTHENTICATION is not set
-CONFIG_CRAMFS=m
-CONFIG_CRAMFS_BLOCKDEV=y
-CONFIG_CRAMFS_MTD=y
-CONFIG_SQUASHFS=m
-# CONFIG_SQUASHFS_FILE_CACHE is not set
-CONFIG_SQUASHFS_FILE_DIRECT=y
-# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
-CONFIG_SQUASHFS_DECOMP_MULTI=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_XATTR=y
-CONFIG_SQUASHFS_ZLIB=y
-CONFIG_SQUASHFS_LZ4=y
-CONFIG_SQUASHFS_LZO=y
-CONFIG_SQUASHFS_XZ=y
-CONFIG_SQUASHFS_ZSTD=y
-CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
-CONFIG_SQUASHFS_EMBEDDED=y
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_OMFS_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_QNX6FS_FS=m
-# CONFIG_QNX6FS_DEBUG is not set
-CONFIG_ROMFS_FS=m
-# CONFIG_ROMFS_BACKED_BY_BLOCK is not set
-# CONFIG_ROMFS_BACKED_BY_MTD is not set
-CONFIG_ROMFS_BACKED_BY_BOTH=y
-CONFIG_ROMFS_ON_BLOCK=y
-CONFIG_ROMFS_ON_MTD=y
-CONFIG_PSTORE=m
-CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_LZO_COMPRESS=y
-CONFIG_PSTORE_LZ4_COMPRESS=y
-CONFIG_PSTORE_LZ4HC_COMPRESS=y
-CONFIG_PSTORE_842_COMPRESS=y
-CONFIG_PSTORE_ZSTD_COMPRESS=y
-CONFIG_PSTORE_COMPRESS=y
-# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
-CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="zstd"
-# CONFIG_PSTORE_CONSOLE is not set
-CONFIG_PSTORE_PMSG=y
-# CONFIG_PSTORE_FTRACE is not set
-CONFIG_PSTORE_RAM=m
-CONFIG_PSTORE_ZONE=m
-CONFIG_PSTORE_BLK=m
-CONFIG_PSTORE_BLK_BLKDEV=""
-CONFIG_PSTORE_BLK_KMSG_SIZE=64
-CONFIG_PSTORE_BLK_MAX_REASON=2
-CONFIG_PSTORE_BLK_PMSG_SIZE=64
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-# CONFIG_UFS_FS_WRITE is not set
-# CONFIG_UFS_DEBUG is not set
-CONFIG_EROFS_FS=m
-# CONFIG_EROFS_FS_DEBUG is not set
-CONFIG_EROFS_FS_XATTR=y
-CONFIG_EROFS_FS_POSIX_ACL=y
-# CONFIG_EROFS_FS_SECURITY is not set
-# CONFIG_EROFS_FS_ZIP is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V2=m
-CONFIG_NFS_V3=m
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=m
-CONFIG_NFS_SWAP=y
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_V4_2=y
-CONFIG_PNFS_FILE_LAYOUT=m
-CONFIG_PNFS_BLOCK=m
-CONFIG_PNFS_FLEXFILE_LAYOUT=m
-CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
-CONFIG_NFS_V4_1_MIGRATION=y
-CONFIG_NFS_FSCACHE=y
-# CONFIG_NFS_USE_LEGACY_DNS is not set
-CONFIG_NFS_USE_KERNEL_DNS=y
-CONFIG_NFS_DISABLE_UDP_SUPPORT=y
-CONFIG_NFS_V4_2_READ_PLUS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V2_ACL=y
-CONFIG_NFSD_V3=y
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_PNFS=y
-CONFIG_NFSD_BLOCKLAYOUT=y
-CONFIG_NFSD_SCSILAYOUT=y
-CONFIG_NFSD_FLEXFILELAYOUT=y
-CONFIG_NFSD_V4_2_INTER_SSC=y
-CONFIG_GRACE_PERIOD=m
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_ACL_SUPPORT=m
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_SUNRPC_BACKCHANNEL=y
-CONFIG_SUNRPC_SWAP=y
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
-# CONFIG_SUNRPC_DEBUG is not set
-CONFIG_SUNRPC_XPRT_RDMA=m
-CONFIG_CEPH_FS=m
-CONFIG_CEPH_FSCACHE=y
-CONFIG_CEPH_FS_POSIX_ACL=y
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS2=y
-CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
-CONFIG_CIFS_WEAK_PW_HASH=y
-CONFIG_CIFS_UPCALL=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-# CONFIG_CIFS_DEBUG is not set
-CONFIG_CIFS_DFS_UPCALL=y
-CONFIG_CIFS_SWN_UPCALL=y
-# CONFIG_CIFS_SMB_DIRECT is not set
-CONFIG_CIFS_FSCACHE=y
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-# CONFIG_AFS_DEBUG is not set
-CONFIG_AFS_FSCACHE=y
-# CONFIG_AFS_DEBUG_CURSOR is not set
-CONFIG_9P_FS=m
-CONFIG_9P_FSCACHE=y
-CONFIG_9P_FS_POSIX_ACL=y
-CONFIG_9P_FS_SECURITY=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_MAC_ROMAN=m
-CONFIG_NLS_MAC_CELTIC=m
-CONFIG_NLS_MAC_CENTEURO=m
-CONFIG_NLS_MAC_CROATIAN=m
-CONFIG_NLS_MAC_CYRILLIC=m
-CONFIG_NLS_MAC_GAELIC=m
-CONFIG_NLS_MAC_GREEK=m
-CONFIG_NLS_MAC_ICELAND=m
-CONFIG_NLS_MAC_INUIT=m
-CONFIG_NLS_MAC_ROMANIAN=m
-CONFIG_NLS_MAC_TURKISH=m
-CONFIG_NLS_UTF8=m
-CONFIG_DLM=m
-# CONFIG_DLM_DEPRECATED_API is not set
-# CONFIG_DLM_DEBUG is not set
-CONFIG_UNICODE=y
-CONFIG_UNICODE_NORMALIZATION_SELFTEST=m
-CONFIG_IO_WQ=y
-# end of File systems
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-# CONFIG_KEYS_REQUEST_CACHE is not set
-CONFIG_PERSISTENT_KEYRINGS=y
-CONFIG_TRUSTED_KEYS=m
-CONFIG_ENCRYPTED_KEYS=m
-CONFIG_USER_DECRYPTED_DATA=y
-# CONFIG_KEY_DH_OPERATIONS is not set
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-# CONFIG_SECURITY is not set
-CONFIG_SECURITYFS=y
-CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
-CONFIG_HARDENED_USERCOPY=y
-CONFIG_HARDENED_USERCOPY_FALLBACK=y
-# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
-CONFIG_FORTIFY_SOURCE=y
-# CONFIG_STATIC_USERMODEHELPER is not set
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_LSM="yama,loadpin,safesetid,integrity,bpf"
-
-#
-# Kernel hardening options
-#
-
-#
-# Memory initialization
-#
-CONFIG_INIT_STACK_NONE=y
-# CONFIG_INIT_STACK_ALL_PATTERN is not set
-# CONFIG_INIT_STACK_ALL_ZERO is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
-# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
-# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
-# end of Memory initialization
-# end of Kernel hardening options
-# end of Security options
-
-CONFIG_XOR_BLOCKS=m
-CONFIG_ASYNC_CORE=m
-CONFIG_ASYNC_MEMCPY=m
-CONFIG_ASYNC_XOR=m
-CONFIG_ASYNC_PQ=m
-CONFIG_ASYNC_RAID6_RECOV=m
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=m
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_SKCIPHER=y
-CONFIG_CRYPTO_SKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG=m
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=m
-CONFIG_CRYPTO_AKCIPHER2=y
-CONFIG_CRYPTO_AKCIPHER=y
-CONFIG_CRYPTO_KPP2=y
-CONFIG_CRYPTO_KPP=m
-CONFIG_CRYPTO_ACOMP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_USER=m
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_PCRYPT=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_SIMD=m
-CONFIG_CRYPTO_ENGINE=m
-
-#
-# Public-key cryptography
-#
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_DH=m
-CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
-CONFIG_CRYPTO_ECC=m
-CONFIG_CRYPTO_ECDH=m
-CONFIG_CRYPTO_ECDSA=m
-CONFIG_CRYPTO_ECRDSA=m
-CONFIG_CRYPTO_SM2=m
-CONFIG_CRYPTO_CURVE25519=m
-
-#
-# Authenticated Encryption with Associated Data
-#
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_GCM=m
-CONFIG_CRYPTO_CHACHA20POLY1305=m
-CONFIG_CRYPTO_AEGIS128=m
-CONFIG_CRYPTO_AEGIS128_SIMD=y
-CONFIG_CRYPTO_SEQIV=m
-CONFIG_CRYPTO_ECHAINIV=m
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CFB=m
-CONFIG_CRYPTO_CTR=m
-CONFIG_CRYPTO_CTS=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_OFB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_KEYWRAP=m
-CONFIG_CRYPTO_NHPOLY1305=m
-CONFIG_CRYPTO_ADIANTUM=m
-CONFIG_CRYPTO_HCTR2=m
-CONFIG_CRYPTO_ARIA=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
-CONFIG_CRYPTO_DEV_QAT_C3XXX=m
-CONFIG_CRYPTO_DEV_QAT_C62X=m
-CONFIG_CRYPTO_DEV_QAT_4XXX=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
-CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
-CONFIG_CRYPTO_DEV_QAT_C62XVF=m
-CONFIG_CRYPTO_ESSIV=m
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_CMAC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CRC32=m
-CONFIG_CRYPTO_XXHASH=m
-CONFIG_CRYPTO_BLAKE2B=m
-CONFIG_CRYPTO_BLAKE2S=m
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_GHASH=m
-CONFIG_CRYPTO_POLY1305=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_RMD128=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_RMD256=m
-CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SHA3=m
-CONFIG_CRYPTO_SM3_NEON=m
-CONFIG_CRYPTO_SM3=m
-# CONFIG_CRYPTO_STREEBOG is not set
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_AES_TI=m
-CONFIG_CRYPTO_ANUBIS=m
-# CONFIG_CRYPTO_ARC4 is not set
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_BLOWFISH_COMMON=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST_COMMON=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SALSA20=m
-CONFIG_CRYPTO_CHACHA20=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_SM4=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_842=y
-CONFIG_CRYPTO_LZ4=y
-CONFIG_CRYPTO_LZ4HC=y
-CONFIG_CRYPTO_ZSTD=y
-
-#
-# Random Number Generation
-#
-CONFIG_CRYPTO_ANSI_CPRNG=m
-CONFIG_CRYPTO_DRBG_MENU=m
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_HASH=y
-CONFIG_CRYPTO_DRBG_CTR=y
-CONFIG_CRYPTO_DRBG=m
-CONFIG_CRYPTO_JITTERENTROPY=m
-CONFIG_CRYPTO_USER_API=m
-CONFIG_CRYPTO_USER_API_HASH=y
-CONFIG_CRYPTO_USER_API_SKCIPHER=m
-CONFIG_CRYPTO_USER_API_RNG=m
-# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
-CONFIG_CRYPTO_USER_API_AEAD=m
-CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
-# CONFIG_CRYPTO_STATS is not set
-CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=m
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_DEV_ALLWINNER=y
-# CONFIG_CRYPTO_DEV_SUN4I_SS is not set
-# CONFIG_CRYPTO_DEV_SUN8I_CE is not set
-# CONFIG_CRYPTO_DEV_SUN8I_SS is not set
-# CONFIG_CRYPTO_DEV_FSL_CAAM is not set
-# CONFIG_CRYPTO_DEV_OMAP is not set
-# CONFIG_CRYPTO_DEV_SAHARA is not set
-# CONFIG_CRYPTO_DEV_EXYNOS_RNG is not set
-# CONFIG_CRYPTO_DEV_S5P is not set
-# CONFIG_CRYPTO_DEV_UX500 is not set
-# CONFIG_CRYPTO_DEV_ATMEL_AES is not set
-# CONFIG_CRYPTO_DEV_ATMEL_TDES is not set
-# CONFIG_CRYPTO_DEV_ATMEL_SHA is not set
-CONFIG_CRYPTO_DEV_ATMEL_I2C=m
-CONFIG_CRYPTO_DEV_ATMEL_ECC=m
-CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
-# CONFIG_CRYPTO_DEV_MXS_DCP is not set
-# CONFIG_CRYPTO_DEV_MARVELL_CESA is not set
-# CONFIG_CRYPTO_DEV_QCE is not set
-# CONFIG_CRYPTO_DEV_QCOM_RNG is not set
-# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
-# CONFIG_CRYPTO_DEV_MEDIATEK is not set
-CONFIG_CRYPTO_DEV_CHELSIO=m
-CONFIG_CRYPTO_DEV_VIRTIO=m
-# CONFIG_CRYPTO_DEV_STM32_CRC is not set
-# CONFIG_CRYPTO_DEV_STM32_HASH is not set
-# CONFIG_CRYPTO_DEV_STM32_CRYP is not set
-CONFIG_CRYPTO_DEV_SAFEXCEL=m
-# CONFIG_CRYPTO_DEV_ARTPEC6 is not set
-# CONFIG_CRYPTO_DEV_CCREE is not set
-CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
-CONFIG_CRYPTO_DEV_ASPEED=m
-# CONFIG_CRYPTO_DEV_ASPEED_DEBUG is not set
-CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH=y
-CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO=y
-# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set
-CONFIG_ASYMMETRIC_KEY_TYPE=y
-CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
-CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE=m
-CONFIG_X509_CERTIFICATE_PARSER=y
-CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
-CONFIG_TPM_KEY_PARSER=m
-CONFIG_PKCS7_MESSAGE_PARSER=y
-CONFIG_PKCS7_TEST_KEY=m
-CONFIG_SIGNED_PE_FILE_VERIFICATION=y
-
-#
-# Certificates for signature checking
-#
-CONFIG_SYSTEM_TRUSTED_KEYRING=y
-CONFIG_SYSTEM_TRUSTED_KEYS=""
-# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
-CONFIG_SECONDARY_TRUSTED_KEYRING=y
-CONFIG_SYSTEM_BLACKLIST_KEYRING=y
-# CONFIG_SYSTEM_REVOCATION_LIST is not set
-CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
-# end of Certificates for signature checking
-
-CONFIG_BINARY_PRINTF=y
-
-#
-# Library routines
-#
-CONFIG_RAID6_PQ=m
-# CONFIG_RAID6_PQ_BENCHMARK is not set
-CONFIG_LINEAR_RANGES=y
-CONFIG_PACKING=y
-CONFIG_BITREVERSE=y
-CONFIG_HAVE_ARCH_BITREVERSE=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_CORDIC=m
-CONFIG_PRIME_NUMBERS=m
-CONFIG_RATIONAL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC64_ROCKSOFT=m
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC32_SELFTEST is not set
-CONFIG_CRC32_SLICEBY8=y
-# CONFIG_CRC32_SLICEBY4 is not set
-# CONFIG_CRC32_SARWATE is not set
-# CONFIG_CRC32_BIT is not set
-CONFIG_CRC64=m
-CONFIG_CRC4=m
-CONFIG_CRC7=m
-CONFIG_LIBCRC32C=m
-CONFIG_CRC8=m
-CONFIG_XXHASH=y
-# CONFIG_RANDOM32_SELFTEST is not set
-CONFIG_842_COMPRESS=y
-CONFIG_842_DECOMPRESS=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_LZ4_COMPRESS=y
-CONFIG_LZ4HC_COMPRESS=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
-CONFIG_XZ_DEC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_BCJ=y
-# CONFIG_XZ_DEC_TEST is not set
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DECOMPRESS_ZSTD=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_REED_SOLOMON=m
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_DEC16=y
-CONFIG_BCH=m
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_BTREE=y
-CONFIG_INTERVAL_TREE=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_DMA=y
-CONFIG_DMA_OPS=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_DMA_DECLARE_COHERENT=y
-CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
-CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
-CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
-CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
-CONFIG_DMA_VIRT_OPS=y
-CONFIG_SWIOTLB=y
-CONFIG_DMA_NONCOHERENT_MMAP=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_PERNUMA_CMA=y
-
-#
-# Default contiguous memory area size:
-#
-CONFIG_CMA_SIZE_MBYTES=0
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_ALIGNMENT=8
-# CONFIG_DMA_API_DEBUG is not set
-# CONFIG_DMA_MAP_BENCHMARK is not set
-CONFIG_SGL_ALLOC=y
-CONFIG_CHECK_SIGNATURE=y
-CONFIG_CPU_RMAP=y
-CONFIG_DQL=y
-CONFIG_GLOB=y
-# CONFIG_GLOB_SELFTEST is not set
-CONFIG_NLATTR=y
-CONFIG_LRU_CACHE=m
-CONFIG_CLZ_TAB=y
-CONFIG_IRQ_POLL=y
-CONFIG_MPILIB=y
-CONFIG_DIMLIB=y
-CONFIG_LIBFDT=y
-CONFIG_OID_REGISTRY=y
-CONFIG_HAVE_GENERIC_VDSO=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_6x10 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-CONFIG_FONT_TER16x32=y
-CONFIG_FONT_6x8=y
-CONFIG_STACK_HASH_ORDER=16
-CONFIG_SG_POOL=y
-CONFIG_SBITMAP=y
-CONFIG_PARMAN=m
-CONFIG_OBJAGG=m
-# CONFIG_STRING_SELFTEST is not set
-# end of Library routines
-
-CONFIG_PLDMFW=y
-
-#
-# Kernel hacking
-#
-
-#
-# printk and dmesg options
-#
-# CONFIG_PRINTK_TIME is not set
-# CONFIG_PRINTK_CALLER is not set
-CONFIG_STACKTRACE_BUILD_ID=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
-CONFIG_CONSOLE_LOGLEVEL_QUIET=4
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_DYNAMIC_DEBUG_CORE is not set
-CONFIG_SYMBOLIC_ERRNAME=y
-CONFIG_DEBUG_BUGVERBOSE=y
-# end of printk and dmesg options
-
-#
-# Compile-time checks and compiler options
-#
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_INFO_REDUCED is not set
-CONFIG_DEBUG_INFO_COMPRESSED=y
-# CONFIG_DEBUG_INFO_SPLIT is not set
-# CONFIG_DEBUG_INFO_NONE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-# CONFIG_DEBUG_INFO_DWARF4 is not set
-# CONFIG_DEBUG_INFO_DWARF5 is not set
-CONFIG_DEBUG_INFO_BTF=y
-CONFIG_MODULE_ALLOW_BTF_MISMATCH=y
-# CONFIG_GDB_SCRIPTS is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_FRAME_WARN=0
-CONFIG_STRIP_ASM_SYMS=y
-# CONFIG_READABLE_ASM is not set
-# CONFIG_HEADERS_INSTALL is not set
-# CONFIG_DEBUG_SECTION_MISMATCH is not set
-CONFIG_SECTION_MISMATCH_WARN_ONLY=y
-# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set
-# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
-CONFIG_VMLINUX_MAP=y
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# end of Compile-time checks and compiler options
-
-#
-# Generic Kernel Debugging Instruments
-#
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
-CONFIG_MAGIC_SYSRQ_SERIAL=y
-CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_FS_ALLOW_ALL is not set
-# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
-# CONFIG_DEBUG_FS_ALLOW_NONE is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_UBSAN is not set
-# end of Generic Kernel Debugging Instruments
-
-# CONFIG_DEBUG_KERNEL is not set
-# CONFIG_DEBUG_MISC is not set
-
-#
-# Memory Debugging
-#
-# CONFIG_PAGE_EXTENSION is not set
-# CONFIG_PAGE_OWNER is not set
-# CONFIG_PAGE_TABLE_CHECK is not set
-# CONFIG_PAGE_POISONING is not set
-# CONFIG_DEBUG_PAGE_REF is not set
-# CONFIG_DEBUG_RODATA_TEST is not set
-CONFIG_DEBUG_WX=y
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SHRINKER_DEBUG is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_HAVE_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_SCHED_STACK_END_CHECK is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_ARCH_HAS_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_PER_CPU_MAPS is not set
-# CONFIG_DEBUG_KMAP_LOCAL is not set
-# CONFIG_DEBUG_HIGHMEM is not set
-CONFIG_CC_HAS_KASAN_GENERIC=y
-CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
-# CONFIG_KASAN is not set
-# end of Memory Debugging
-
-# CONFIG_DEBUG_SHIRQ is not set
-
-#
-# Debug Oops, Lockups and Hangs
-#
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=60
-# CONFIG_SOFTLOCKUP_DETECTOR is not set
-# CONFIG_DETECT_HUNG_TASK is not set
-# CONFIG_WQ_WATCHDOG is not set
-CONFIG_TEST_LOCKUP=m
-# end of Debug Oops, Lockups and Hangs
-
-#
-# Scheduler Debugging
-#
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHED_INFO=y
-CONFIG_SCHEDSTATS=y
-# end of Scheduler Debugging
-
-# CONFIG_DEBUG_TIMEKEEPING is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_IRQFLAGS is not set
-
-#
-# Lock Debugging (spinlocks, mutexes, etc...)
-#
-# CONFIG_LOCK_DEBUGGING_SUPPORT is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
-# CONFIG_DEBUG_RWSEMS is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_DEBUG_ATOMIC_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_LOCK_TORTURE_TEST is not set
-# CONFIG_WW_MUTEX_SELFTEST is not set
-# CONFIG_SCF_TORTURE_TEST is not set
-# end of Lock Debugging (spinlocks, mutexes, etc...)
-
-CONFIG_STACKTRACE=y
-# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
-# CONFIG_DEBUG_KOBJECT is not set
-
-#
-# Debug kernel data structures
-#
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_PLIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BUG_ON_DATA_CORRUPTION is not set
-# end of Debug kernel data structures
-
-# CONFIG_DEBUG_CREDENTIALS is not set
-
-#
-# RCU Debugging
-#
-CONFIG_TORTURE_TEST=m
-CONFIG_RCU_SCALE_TEST=m
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_REF_SCALE_TEST=m
-CONFIG_RCU_CPU_STALL_TIMEOUT=60
-# CONFIG_RCU_TRACE is not set
-# CONFIG_RCU_EQS_DEBUG is not set
-# end of RCU Debugging
-
-# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-CONFIG_LATENCYTOP=y
-CONFIG_NOP_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_RING_BUFFER=y
-CONFIG_EVENT_TRACING=y
-CONFIG_CONTEXT_SWITCH_TRACER=y
-CONFIG_TRACING=y
-CONFIG_GENERIC_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-CONFIG_FTRACE=y
-CONFIG_BOOTTIME_TRACING=y
-CONFIG_FUNCTION_TRACER=y
-# CONFIG_FUNCTION_GRAPH_TRACER is not set
-CONFIG_DYNAMIC_FTRACE=y
-CONFIG_DYNAMIC_FTRACE_WITH_REGS=y
-# CONFIG_FPROBE is not set
-CONFIG_FTRACE_RECORD_RECURSION=y
-CONFIG_FTRACE_RECORD_RECURSION_SIZE=128
-CONFIG_RING_BUFFER_RECORD_RECURSION=y
-# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
-CONFIG_FUNCTION_PROFILER=y
-CONFIG_STACK_TRACER=y
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_HWLAT_TRACER is not set
-# CONFIG_OSNOISE_TRACER is not set
-# CONFIG_TIMERLAT_TRACER is not set
-CONFIG_FTRACE_SYSCALLS=y
-# CONFIG_TRACER_SNAPSHOT is not set
-CONFIG_BRANCH_PROFILE_NONE=y
-# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
-# CONFIG_PROFILE_ALL_BRANCHES is not set
-CONFIG_BLK_DEV_IO_TRACE=y
-CONFIG_KPROBE_EVENTS=y
-# CONFIG_UPROBE_EVENTS is not set
-CONFIG_BPF_EVENTS=y
-CONFIG_DYNAMIC_EVENTS=y
-CONFIG_PROBE_EVENTS=y
-CONFIG_FTRACE_MCOUNT_RECORD=y
-# CONFIG_SYNTH_EVENTS is not set
-# CONFIG_HIST_TRIGGERS is not set
-# CONFIG_TRACE_EVENT_INJECT is not set
-# CONFIG_TRACEPOINT_BENCHMARK is not set
-# CONFIG_RING_BUFFER_BENCHMARK is not set
-# CONFIG_TRACE_EVAL_MAP_FILE is not set
-# CONFIG_FTRACE_STARTUP_TEST is not set
-# CONFIG_RING_BUFFER_STARTUP_TEST is not set
-CONFIG_PREEMPTIRQ_DELAY_TEST=m
-CONFIG_KPROBE_EVENT_GEN_TEST=m
-# CONFIG_SAMPLES is not set
-CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
-CONFIG_STRICT_DEVMEM=y
-# CONFIG_IO_STRICT_DEVMEM is not set
-
-#
-# arm Debugging
-#
-CONFIG_ARM_PTDUMP_CORE=y
-# CONFIG_ARM_PTDUMP_DEBUGFS is not set
-# CONFIG_UNWINDER_FRAME_POINTER is not set
-CONFIG_UNWINDER_ARM=y
-CONFIG_ARM_UNWIND=y
-# CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_LL is not set
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_ARM_KPROBES_TEST=m
-# CONFIG_PID_IN_CONTEXTIDR is not set
-# CONFIG_CORESIGHT is not set
-# end of arm Debugging
-
-#
-# Kernel Testing and Coverage
-#
-# CONFIG_KUNIT is not set
-# CONFIG_NOTIFIER_ERROR_INJECTION is not set
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_ARCH_HAS_KCOV=y
-CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-# CONFIG_KCOV is not set
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_MEMTEST=y
-# end of Kernel Testing and Coverage
-# end of Kernel hacking
-CONFIG_SURFACE_PLATFORMS=y
-CONFIG_SURFACE_KBD=m
-CONFIG_SURFACE_DTX=m
-CONFIG_SURFACE_PLATFORM_PROFILE=m
-CONFIG_LITEX_SOC_CONTROLLER=m
-CONFIG_LITEX_SUBREG_SIZE=4
-
-# CONFIG_WERROR is not set
-CONFIG_PRINTK_INDEX=y
-CONFIG_SOC_SAMA7G5=y
-CONFIG_SOC_LAN966=y
-CONFIG_ARCH_MSM8916=y
-CONFIG_MACH_STM32MP13=y
-CONFIG_ARM_MEDIATEK_CPUFREQ_HW=m
-CONFIG_DAMON=y
-CONFIG_DAMON_SYSFS=y
-CONFIG_DAMON_VADDR=y
-CONFIG_DAMON_PADDR=y
-CONFIG_DAMON_DBGFS=y
-CONFIG_DAMON_RECLAIM=y
-CONFIG_IPV6_IOAM6_LWTUNNEL=y
-CONFIG_NETFILTER_EGRESS=y
-CONFIG_MCTP=y
-CONFIG_PCIE_QCOM_EP=m
-CONFIG_PCIE_ROCKCHIP_DW_HOST=y
-CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
-CONFIG_ARM_SCMI_TRANSPORT_SMC=y
-# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
-CONFIG_HI6421V600_IRQ=m
-CONFIG_SCSI_UFS_HPB=y
-CONFIG_SCSI_UFS_HWMON=y
-CONFIG_AMT=m
-CONFIG_NET_VENDOR_ASIX=y
-CONFIG_SPI_AX88796C=m
-CONFIG_SPI_AX88796C_COMPRESSION=y
-CONFIG_CS89x0_PLATFORM=m
-CONFIG_ICE_SWITCHDEV=y
-CONFIG_ICE_HWTS=y
-CONFIG_NET_VENDOR_LITEX=y
-CONFIG_LITEX_LITEETH=m
-CONFIG_MAXLINEAR_GPHY=m
-CONFIG_MT7921S=m
-CONFIG_MT7921U=m
-CONFIG_RTW89=m
-CONFIG_RTW89_8852AE=m
-# CONFIG_RTW89_DEBUGMSG is not set
-CONFIG_RTW89_DEBUGFS=y
-CONFIG_MHI_WWAN_MBIM=m
-CONFIG_QCOM_BAM_DMUX=m
-CONFIG_KEYBOARD_CYPRESS_SF=m
-CONFIG_RPMSG_TTY=m
-CONFIG_IPMI_IPMB=m
-CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
-CONFIG_HW_RANDOM_CN10K=m
-CONFIG_I2C_VIRTIO=m
-CONFIG_SPI_CADENCE_XSPI=m
-CONFIG_SPI_ROCKCHIP_SFC=m
-CONFIG_PINCTRL_IMX8ULP=m
-CONFIG_PINCTRL_MDM9607=m
-CONFIG_PINCTRL_QCM2290=m
-CONFIG_PINCTRL_SM6115=m
-CONFIG_PINCTRL_SM6350=m
-CONFIG_PINCTRL_UNIPHIER_NX1=y
-CONFIG_GPIO_ROCKCHIP=m
-CONFIG_GPIO_VIRTIO=m
-CONFIG_POWER_RESET_TPS65086=y
-CONFIG_CHARGER_MT6360=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_CHARGER_CROS_PCHG=m
-CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m
-CONFIG_SENSORS_MAX6620=m
-CONFIG_SENSORS_SBRMI=m
-CONFIG_QCOM_LMH=m
-CONFIG_DB500_WATCHDOG=m
-CONFIG_MFD_RSMU_I2C=m
-CONFIG_MFD_RSMU_SPI=m
-CONFIG_REGULATOR_RTQ2134=m
-CONFIG_REGULATOR_RTQ6752=m
-CONFIG_IR_MESON_TX=m
-CONFIG_VIDEO_RCAR_ISP=m
-# CONFIG_VIDEO_ROCKCHIP_IEP is not set
-CONFIG_VIDEO_HI846=m
-CONFIG_VIDEO_HI847=m
-CONFIG_VIDEO_IMX335=m
-CONFIG_VIDEO_IMX412=m
-CONFIG_VIDEO_OV9282=m
-CONFIG_VIDEO_OV13B10=m
-# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
-CONFIG_DRM_PANEL_EDP=m
-CONFIG_DRM_PANEL_ILITEK_ILI9341=m
-CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
-CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
-CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
-CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
-CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
-CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
-CONFIG_SND_HDA_CODEC_CS8409=m
-CONFIG_SND_SOC_MT8195=m
-CONFIG_SND_SOC_CS35L41_SPI=m
-CONFIG_SND_SOC_CS35L41_I2C=m
-CONFIG_SND_SOC_ICS43432=m
-CONFIG_SND_SOC_MAX98520=m
-CONFIG_SND_SOC_RT9120=m
-CONFIG_SND_SOC_SDW_MOCKUP=m
-CONFIG_SND_SOC_NAU8821=m
-CONFIG_SND_AUDIO_GRAPH_CARD2=m
-CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
-CONFIG_SND_TEST_COMPONENT=m
-CONFIG_HID_XIAOMI=m
-CONFIG_HID_NINTENDO=m
-CONFIG_NINTENDO_FF=y
-CONFIG_RTC_DRV_MSC313=m
-# CONFIG_DMABUF_SYSFS_STATS is not set
-CONFIG_VDPA_USER=m
-CONFIG_COMMON_CLK_XLNX_CLKWZRD=m
-CONFIG_CLK_IMX8ULP=m
-CONFIG_CLK_IMX93=m
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_ASPEED_UART_ROUTING=m
-CONFIG_QCOM_SPM=m
-CONFIG_ADXL313_I2C=m
-CONFIG_ADXL313_SPI=m
-CONFIG_ADXL355_I2C=m
-CONFIG_ADXL355_SPI=m
-CONFIG_ADXL367_SPI=m
-CONFIG_ADXL367_I2C=m
-CONFIG_SCD4X=m
-CONFIG_SENSIRION_SGP40=m
-CONFIG_SENSEAIR_SUNRISE_CO2=m
-CONFIG_ADRF6780=m
-CONFIG_AD5110=m
-CONFIG_MAX31865=m
-CONFIG_MCHP_EIC=y
-# CONFIG_F2FS_IOSTAT is not set
-# CONFIG_F2FS_UNFAIR_RWSEM is not set
-CONFIG_SMB_SERVER=m
-CONFIG_SMB_SERVER_SMBDIRECT=y
-CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
-CONFIG_SMB_SERVER_KERBEROS5=y
-# CONFIG_ZERO_CALL_USED_REGS is not set
-CONFIG_XZ_DEC_MICROLZMA=y
-CONFIG_DMA_RESTRICTED_POOL=y
-# CONFIG_ANON_VMA_NAME is not set
-CONFIG_NET_9P_FD=m
-CONFIG_DEVTMPFS_SAFE=y
-CONFIG_GNSS_USB=m
-CONFIG_MTD_NAND_RENESAS=m
-CONFIG_NET_VENDOR_ENGLEDER=y
-CONFIG_TSNEP=m
-# CONFIG_TSNEP_SELFTESTS is not set
-CONFIG_LAN966X_SWITCH=m
-CONFIG_NET_VENDOR_VERTEXCOM=y
-CONFIG_MSE102X=m
-CONFIG_MCTP_SERIAL=m
-CONFIG_MCTP_TRANSPORT_I2C=m
-# CONFIG_WWAN_DEBUGFS is not set
-CONFIG_SERIAL_8250_PERICOM=m
-CONFIG_SPMI_MTK_PMIF=m
-CONFIG_PINCTRL_IMXRT1050=y
-CONFIG_PINCTRL_IMX93=m
-CONFIG_PINCTRL_SDX65=m
-CONFIG_PINCTRL_SM8450=m
-CONFIG_PINCTRL_SM8450_LPASS_LPI=m
-CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
-CONFIG_PINCTRL_SM8280XP_LPASS_LPI=m
-CONFIG_GPIO_SIM=m
-CONFIG_CHARGER_MAX77976=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_SENSORS_NZXT_SMART2=m
-CONFIG_SENSORS_DELTA_AHE50DC_FAN=m
-CONFIG_SENSORS_IR38064_REGULATOR=y
-CONFIG_SENSORS_MP5023=m
-CONFIG_SENSORS_INA238=m
-CONFIG_RZG2L_THERMAL=m
-CONFIG_RENESAS_RZG2LWDT=m
-CONFIG_REGULATOR_MAX20086=m
-CONFIG_VIDEO_STM32_DMA2D=m
-CONFIG_VIDEO_OV5693=m
-CONFIG_DRM_RCAR_USE_LVDS=y
-CONFIG_DRM_RCAR_USE_MIPI_DSI=y
-CONFIG_DRM_RCAR_MIPI_DSI=m
-CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
-CONFIG_DRM_PANEL_JDI_R63452=m
-CONFIG_DRM_PANEL_NOVATEK_NT35950=m
-CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
-CONFIG_TINYDRM_ILI9163=m
-CONFIG_SND_AMD_ACP_CONFIG=m
-CONFIG_SND_SOC_APPLE_MCA=m
-CONFIG_SND_SOC_AK4375=m
-CONFIG_SND_SOC_TLV320ADC3XXX=m
-CONFIG_HID_LETSKETCH=m
-CONFIG_LEDS_MT6360=m
-CONFIG_VIDEO_MAX96712=m
-CONFIG_COMMON_CLK_LAN966X=y
-CONFIG_COMMON_CLK_MT7986=y
-CONFIG_COMMON_CLK_MT7986_ETHSYS=y
-CONFIG_RENESAS_OSTM=y
-CONFIG_EXYNOS_USI=m
-CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
-CONFIG_AD74413R=m
-CONFIG_AD3552R=m
-CONFIG_AD7293=m
-CONFIG_ADMV1013=m
-CONFIG_ADMV1014=m
-CONFIG_ADMV4420=m
-CONFIG_PHY_MESON8_HDMI_TX=m
-CONFIG_PHY_FSL_IMX8M_PCIE=m
-CONFIG_PHY_FSL_LYNX_28G=m
-CONFIG_PHY_LAN966X_SERDES=m
-CONFIG_PHY_QCOM_EDP=m
-# CONFIG_CACHEFILES_ERROR_INJECTION is not set
-CONFIG_UNICODE_UTF8_DATA=m
-# CONFIG_NET_DEV_REFCNT_TRACKER is not set
-# CONFIG_NET_NS_REFCNT_TRACKER is not set
-# CONFIG_KFENCE is not set
-# CONFIG_FTRACE_SORT_STARTUP_TEST is not set
-CONFIG_BACKTRACE_VERBOSE=y
-CONFIG_ADMV8818=m
-CONFIG_MARVELL_CN10K_TAD_PMU=m
-CONFIG_APPLE_M1_CPU_PMU=y
-CONFIG_ALIBABA_UNCORE_DRW_PMU=m
-# CONFIG_KCSAN is not set
-CONFIG_PECI=m
-CONFIG_PECI_CPU=m
-CONFIG_PECI_ASPEED=m
-CONFIG_SENSORS_PECI_CPUTEMP=m
-CONFIG_SENSORS_PECI_DIMMTEMP=m
-# CONFIG_BOOT_CONFIG_EMBED is not set
-CONFIG_INITRAMFS_PRESERVE_MTIME=y
-CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y
-CONFIG_ARCH_BCMBCA=y
-CONFIG_ARCH_HPE=y
-CONFIG_ARCH_HPE_GXP=y
-CONFIG_ARM_ERRATA_764319=y
-# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
-CONFIG_CAN_CTUCANFD_PCI=m
-CONFIG_CAN_CTUCANFD_PLATFORM=m
-CONFIG_FW_LOADER_COMPRESS_XZ=y
-CONFIG_FW_LOADER_COMPRESS_ZSTD=y
-CONFIG_FW_UPLOAD=y
-CONFIG_QCOM_SSC_BLOCK_BUS=y
-CONFIG_MHI_BUS_EP=m
-CONFIG_MTK_ADSP_IPC=m
-CONFIG_EFI_COCO_SECRET=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=m
-CONFIG_SFC_SIENA=m
-CONFIG_SFC_SIENA_MTD=y
-CONFIG_SFC_SIENA_MCDI_MON=y
-CONFIG_SFC_SIENA_SRIOV=y
-# CONFIG_SFC_SIENA_MCDI_LOGGING is not set
-CONFIG_ADIN1100_PHY=m
-CONFIG_DP83TD510_PHY=m
-CONFIG_WLAN_VENDOR_PURELIFI=y
-CONFIG_PLFXLC=m
-CONFIG_RTW89_8852CE=m
-CONFIG_WLAN_VENDOR_SILABS=y
-CONFIG_MTK_T7XX=m
-CONFIG_JOYSTICK_SENSEHAT=m
-CONFIG_INPUT_IQS7222=m
-# CONFIG_HVC_DCC_SERIALIZE_SMP is not set
-CONFIG_SPI_MTK_SNFI=m
-CONFIG_PINCTRL_IMXRT1170=y
-CONFIG_PINCTRL_SC7280_LPASS_LPI=m
-CONFIG_PINCTRL_SM8250_LPASS_LPI=m
-CONFIG_SENSORS_LAN966X=m
-CONFIG_SENSORS_NCT6775_I2C=m
-CONFIG_SENSORS_XDPE152=m
-CONFIG_RENESAS_RZN1WDT=m
-CONFIG_GXP_WATCHDOG=m
-CONFIG_REGULATOR_RT5759=m
-CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
-CONFIG_DRM_FSL_LDB=m
-CONFIG_DRM_LONTIUM_LT9211=m
-CONFIG_DRM_DW_HDMI_GP_AUDIO=m
-CONFIG_DRM_SSD130X_SPI=m
-CONFIG_SND_SERIAL_GENERIC=m
-CONFIG_SND_SOC_CS35L45_SPI=m
-CONFIG_SND_SOC_CS35L45_I2C=m
-CONFIG_SND_SOC_MAX98396=m
-CONFIG_SND_SOC_WM8731_I2C=m
-CONFIG_SND_SOC_WM8731_SPI=m
-CONFIG_SND_SOC_WM8940=m
-CONFIG_HID_MEGAWORLD_FF=m
-CONFIG_TYPEC_MUX_FSA4480=m
-CONFIG_LEDS_PWM_MULTICOLOR=m
-CONFIG_LEDS_QCOM_LPG=m
-CONFIG_TEGRA186_GPC_DMA=m
-# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set
-CONFIG_PWM_XILINX=m
-CONFIG_HTE=y
-# CONFIG_CACHEFILES_ONDEMAND is not set
-CONFIG_TRUSTED_KEYS_TPM=y
-CONFIG_TRUSTED_KEYS_TEE=y
-CONFIG_CRYPTO_SM3_GENERIC=m
-CONFIG_CRYPTO_SM4_GENERIC=m
-# CONFIG_FIPS_SIGNATURE_SELFTEST is not set
-CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y
-# CONFIG_DEBUG_NET is not set
-CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
-# CONFIG_CGROUP_FAVOR_DYNMODS is not set
-CONFIG_ARCH_BCMBCA_CORTEXA7=y
-CONFIG_ARCH_BCMBCA_CORTEXA9=y
-CONFIG_ARCH_BCMBCA_BRAHMAB15=y
-CONFIG_ARCH_MSM8909=y
-CONFIG_ARCH_SUNPLUS=y
-CONFIG_SOC_SP7021=y
-# CONFIG_UNUSED_BOARD_FILES is not set
-# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
-CONFIG_DAMON_LRU_SORT=y
-CONFIG_NF_FLOW_TABLE_PROCFS=y
-CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
-CONFIG_PCI_EPF_VNTB=m
-CONFIG_ARM_SCMI_POWER_CONTROL=m
-CONFIG_BLK_DEV_UBLK=m
-CONFIG_NVME_AUTH=y
-CONFIG_NVME_TARGET_AUTH=y
-CONFIG_VCPU_STALL_DETECTOR=m
-CONFIG_SCSI_BUSLOGIC=m
-CONFIG_SCSI_FLASHPOINT=y
-CONFIG_AHCI_BRCM=m
-CONFIG_AHCI_DWC=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
-CONFIG_NET_VENDOR_WANGXUN=y
-CONFIG_NET_VENDOR_ADI=y
-CONFIG_ADIN1110=m
-CONFIG_NGBE=m
-CONFIG_TXGBE=m
-CONFIG_NET_VENDOR_SUNPLUS=y
-CONFIG_SP7021_EMAC=m
-CONFIG_CAN_NETLINK=y
-CONFIG_CAN_CAN327=m
-CONFIG_CAN_ESD_USB=m
-CONFIG_HW_RANDOM_BCM2835=m
-CONFIG_TCG_TIS_I2C=m
-# CONFIG_RANDOM_TRUST_CPU is not set
-CONFIG_I2C_BRCMSTB=m
-CONFIG_I2C_NPCM=m
-CONFIG_I2C_RZV2M=m
-CONFIG_SPI_BCM63XX_HSSPI=m
-CONFIG_SPI_GXP=m
-CONFIG_SPI_MICROCHIP_CORE=m
-CONFIG_SPI_MICROCHIP_CORE_QSPI=m
-CONFIG_SPI_SUNPLUS_SP7021=m
-CONFIG_PINCTRL_MSM8909=m
-CONFIG_PINCTRL_SM6375=m
-CONFIG_PINCTRL_SUN20I_D1=y
-CONFIG_SENSORS_LT7182S=m
-CONFIG_SUNPLUS_WATCHDOG=m
-CONFIG_VIDEO_SUN6I_MIPI_CSI2=m
-CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m
-CONFIG_VIDEO_AR0521=m
-CONFIG_DRM_PANEL_EBBG_FT8719=m
-CONFIG_DRM_TI_DLPC3433=m
-CONFIG_DRM_IMX8QM_LDB=m
-CONFIG_DRM_IMX8QXP_LDB=m
-CONFIG_DRM_IMX8QXP_PIXEL_COMBINER=m
-CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI=m
-CONFIG_DRM_LOGICVC=m
-CONFIG_DRM_IMX_LCDIF=m
-CONFIG_SND_CTL_FAST_LOOKUP=y
-CONFIG_SND_CTL_INPUT_VALIDATION=y
-CONFIG_SND_SOC_MT8136=m
-CONFIG_SND_SOC_HDA=m
-CONFIG_SND_SOC_TAS2780=m
-CONFIG_SND_SOC_WSA883X=m
-CONFIG_I2C_HID_OF_ELAN=m
-CONFIG_USB_ONBOARD_HUB=m
-CONFIG_USB_ASPEED_UDC=m
-CONFIG_UCSI_STM32G0=m
-CONFIG_TYPEC_ANX7411=m
-CONFIG_SCSI_UFS_RENESAS=m
-CONFIG_RTC_DRV_NCT3018Y=m
-CONFIG_RTC_DRV_SUNPLUS=m
-CONFIG_VIDEO_STKWEBCAM=m
-CONFIG_CROS_KBD_LED_BACKLIGHT=m
-CONFIG_CLK_BCM_63XX=y
-CONFIG_TEGRA186_TIMER=y
-CONFIG_QCOM_ICC_BWMON=m
-CONFIG_PWM_CLK=m
-CONFIG_PWM_SUNPLUS=m
-CONFIG_RESET_TI_TPS380X=m
-CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=m
-CONFIG_PHY_BRCM_SATA=m
-CONFIG_PHY_BRCM_USB=m
-CONFIG_PHY_MTK_PCIE=m
-CONFIG_PHY_MTK_DP=m
-CONFIG_MICROCHIP_OTPC=m
-CONFIG_NVMEM_SUNPLUS_OCOTP=m
-CONFIG_FPGA_M10_BMC_SEC_UPDATE=m
-CONFIG_FPGA_MGR_MICROCHIP_SPI=m
-CONFIG_INTERCONNECT_IMX8MP=m
-# CONFIG_DLM_DEPRECATED_API is not set
-CONFIG_CRYPTO_HCTR2=m
-CONFIG_CRYPTO_ARIA=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
-CONFIG_CRYPTO_DEV_QAT_C3XXX=m
-CONFIG_CRYPTO_DEV_QAT_C62X=m
-CONFIG_CRYPTO_DEV_QAT_4XXX=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
-CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
-CONFIG_CRYPTO_DEV_QAT_C62XVF=m
-# CONFIG_SHRINKER_DEBUG is not set
-# CONFIG_RV is not set
-# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set
-CONFIG_RCU_NOCB_CPU_DEFAULT_ALL=y
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-CONFIG_A64FX_DIAG=y
-# Ethernet Power Sourcing Equipment Support
-CONFIG_PSE_CONTROLLER=y
-CONFIG_PSE_REGULATOR=m
-CONFIG_STAGING_MEDIA_DEPRECATED=y
-# CONFIG_FORCE_NR_CPUS is not set
-# CONFIG_DEBUG_MAPLE_TREE is not set
-CONFIG_QCOM_TSENS=m
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_KERNEL_ZSTD=y
diff --git a/bc1d59cd423b4a327af19bcd726f108f0f5a5da5.patch b/bc1d59cd423b4a327af19bcd726f108f0f5a5da5.patch
new file mode 100644
index 0000000..3ce88a9
--- /dev/null
+++ b/bc1d59cd423b4a327af19bcd726f108f0f5a5da5.patch
@@ -0,0 +1,770 @@
+From bc1d59cd423b4a327af19bcd726f108f0f5a5da5 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Sat, 27 Apr 2024 18:47:34 +0800
+Subject: [PATCH] arm: Add rockchip_defconfig
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm/configs/rockchip_defconfig | 753 ++++++++++++++++++++++++++++
+ 1 file changed, 753 insertions(+)
+ create mode 100644 arch/arm/configs/rockchip_defconfig
+
+diff --git a/arch/arm/configs/rockchip_defconfig b/arch/arm/configs/rockchip_defconfig
+new file mode 100644
+index 00000000000000..74003c0e1eda8f
+--- /dev/null
++++ b/arch/arm/configs/rockchip_defconfig
+@@ -0,0 +1,753 @@
++CONFIG_SYSVIPC=y
++CONFIG_NO_HZ_IDLE=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_CGROUPS=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_EXPERT=y
++CONFIG_PERF_EVENTS=y
++CONFIG_KEXEC=y
++CONFIG_ARCH_OMAP3=y
++CONFIG_ARCH_OMAP4=y
++CONFIG_SOC_OMAP5=y
++CONFIG_SOC_AM33XX=y
++CONFIG_SOC_AM43XX=y
++CONFIG_SOC_DRA7XX=y
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_ARM_THUMBEE=y
++CONFIG_PL310_ERRATA_753970=y
++CONFIG_PL310_ERRATA_769419=y
++CONFIG_ARM_ERRATA_754327=y
++CONFIG_ARM_ERRATA_764369=y
++CONFIG_ARM_ERRATA_814220=y
++CONFIG_SMP=y
++CONFIG_MCPM=y
++CONFIG_NR_CPUS=16
++CONFIG_ARM_PSCI=y
++CONFIG_ARM_APPENDED_DTB=y
++CONFIG_ARM_ATAG_DTB_COMPAT=y
++CONFIG_EFI=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=m
++CONFIG_CPU_FREQ_GOV_USERSPACE=m
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_ARM_SCMI_CPUFREQ=y
++CONFIG_CPU_IDLE=y
++CONFIG_ARM_CPUIDLE=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_PARTITION_ADVANCED=y
++CONFIG_CMDLINE_PARTITION=y
++CONFIG_CMA=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_INET=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++CONFIG_IP_PNP_RARP=y
++CONFIG_IPV6_ROUTER_PREF=y
++CONFIG_IPV6_OPTIMISTIC_DAD=y
++CONFIG_INET6_AH=m
++CONFIG_INET6_ESP=m
++CONFIG_INET6_IPCOMP=m
++CONFIG_IPV6_MIP6=m
++CONFIG_IPV6_TUNNEL=m
++CONFIG_IPV6_MULTIPLE_TABLES=y
++CONFIG_NET_DSA=m
++CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
++CONFIG_QRTR=m
++CONFIG_QRTR_SMD=m
++CONFIG_CAN=y
++CONFIG_BT=m
++CONFIG_BT_HCIUART=m
++CONFIG_BT_HCIUART_BCM=y
++CONFIG_BT_MRVL=m
++CONFIG_BT_MRVL_SDIO=m
++CONFIG_CFG80211=m
++CONFIG_MAC80211=m
++CONFIG_RFKILL=y
++CONFIG_RFKILL_INPUT=y
++CONFIG_RFKILL_GPIO=y
++CONFIG_NFC=m
++CONFIG_NFC_DIGITAL=m
++CONFIG_NFC_NCI=m
++CONFIG_NFC_NCI_SPI=m
++CONFIG_NFC_NCI_UART=m
++CONFIG_NFC_HCI=m
++CONFIG_NFC_SHDLC=y
++CONFIG_NFC_S3FWRN5_I2C=m
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_PCI=y
++CONFIG_PCIEPORTBUS=y
++CONFIG_PCI_MSI=y
++CONFIG_PCI_HOST_GENERIC=y
++CONFIG_PCI_MESON=m
++CONFIG_PCI_LAYERSCAPE=y
++CONFIG_PCI_DRA7XX_EP=y
++CONFIG_PCI_ENDPOINT=y
++CONFIG_PCI_ENDPOINT_CONFIGFS=y
++CONFIG_PCI_EPF_TEST=m
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_OMAP_OCP2SCP=y
++CONFIG_VEXPRESS_CONFIG=y
++CONFIG_ARM_SCMI_PROTOCOL=y
++CONFIG_TRUSTED_FOUNDATIONS=y
++CONFIG_EFI_CAPSULE_LOADER=m
++CONFIG_MTD=y
++CONFIG_MTD_CMDLINE_PARTS=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_CFI=y
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_PHYSMAP=y
++CONFIG_MTD_PHYSMAP_OF=y
++CONFIG_MTD_RAW_NAND=y
++CONFIG_MTD_NAND_DENALI_DT=y
++CONFIG_MTD_NAND_OMAP2=y
++CONFIG_MTD_NAND_OMAP_BCH=y
++CONFIG_MTD_NAND_BRCMNAND=y
++CONFIG_MTD_NAND_BRCMNAND_BCMBCA=y
++CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=y
++CONFIG_MTD_NAND_BRCMNAND_IPROC=y
++CONFIG_MTD_NAND_PL35X=y
++CONFIG_MTD_SPI_NOR=y
++CONFIG_MTD_UBI=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_SIZE=65536
++CONFIG_VIRTIO_BLK=y
++CONFIG_AD525X_DPOT=y
++CONFIG_AD525X_DPOT_I2C=y
++CONFIG_ICS932S401=y
++CONFIG_APDS9802ALS=y
++CONFIG_ISL29003=y
++CONFIG_SRAM=y
++CONFIG_PCI_ENDPOINT_TEST=m
++CONFIG_EEPROM_AT24=y
++CONFIG_BLK_DEV_SD=y
++CONFIG_BLK_DEV_SR=y
++CONFIG_ATA=y
++CONFIG_SATA_AHCI=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_DM816=y
++CONFIG_AHCI_DWC=m
++CONFIG_SATA_MV=y
++CONFIG_NETDEVICES=y
++CONFIG_VIRTIO_NET=y
++CONFIG_B53_SPI_DRIVER=m
++CONFIG_B53_MDIO_DRIVER=m
++CONFIG_B53_MMAP_DRIVER=m
++CONFIG_B53_SRAB_DRIVER=m
++CONFIG_B53_SERDES=m
++CONFIG_NET_DSA_BCM_SF2=m
++CONFIG_EMAC_ROCKCHIP=y
++CONFIG_SPI_AX88796C=m
++CONFIG_BCMGENET=m
++CONFIG_SYSTEMPORT=m
++CONFIG_MACB=y
++CONFIG_FTGMAC100=m
++CONFIG_HIX5HD2_GMAC=y
++CONFIG_E1000E=y
++CONFIG_IGB=y
++CONFIG_MVMDIO=y
++CONFIG_KS8851=y
++CONFIG_LAN966X_SWITCH=m
++CONFIG_R8169=y
++CONFIG_SMSC911X=y
++CONFIG_STMMAC_ETH=y
++CONFIG_DWMAC_DWC_QOS_ETH=y
++CONFIG_TI_CPSW=y
++CONFIG_TI_CPSW_SWITCHDEV=y
++CONFIG_TI_CPTS=y
++CONFIG_XILINX_EMACLITE=y
++CONFIG_SFP=m
++CONFIG_BROADCOM_PHY=y
++CONFIG_ICPLUS_PHY=y
++CONFIG_MARVELL_PHY=y
++CONFIG_AT803X_PHY=y
++CONFIG_ROCKCHIP_PHY=y
++CONFIG_DP83867_PHY=y
++CONFIG_CAN_FLEXCAN=m
++CONFIG_CAN_MCP251X=y
++CONFIG_MDIO_BCM_UNIMAC=y
++CONFIG_MDIO_MSCC_MIIM=m
++CONFIG_USB_PEGASUS=y
++CONFIG_USB_RTL8152=m
++CONFIG_USB_LAN78XX=m
++CONFIG_USB_USBNET=y
++CONFIG_USB_NET_SMSC75XX=y
++CONFIG_USB_NET_SMSC95XX=y
++CONFIG_WCN36XX=m
++CONFIG_BRCMFMAC=m
++CONFIG_MWIFIEX=m
++CONFIG_MWIFIEX_SDIO=m
++CONFIG_RT2X00=m
++CONFIG_RT2800USB=m
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++CONFIG_KEYBOARD_QT1070=m
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_SAMSUNG=m
++CONFIG_KEYBOARD_TM2_TOUCHKEY=m
++CONFIG_KEYBOARD_CROS_EC=m
++CONFIG_KEYBOARD_BCM=y
++CONFIG_MOUSE_PS2_ELANTECH=y
++CONFIG_MOUSE_CYAPA=m
++CONFIG_MOUSE_ELAN_I2C=y
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_ADC=m
++CONFIG_TOUCHSCREEN_ATMEL_MXT=m
++CONFIG_TOUCHSCREEN_ELAN=m
++CONFIG_TOUCHSCREEN_MMS114=m
++CONFIG_TOUCHSCREEN_EDT_FT5X06=m
++CONFIG_TOUCHSCREEN_WM97XX=m
++CONFIG_TOUCHSCREEN_ST1232=m
++CONFIG_TOUCHSCREEN_STMPE=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_MAX77693_HAPTIC=m
++CONFIG_INPUT_MAX8997_HAPTIC=m
++CONFIG_INPUT_CPCAP_PWRBUTTON=m
++CONFIG_INPUT_AXP20X_PEK=m
++CONFIG_INPUT_DA9063_ONKEY=m
++CONFIG_INPUT_ADXL34X=m
++CONFIG_INPUT_STPMIC1_ONKEY=y
++CONFIG_SERIO_AMBAKMI=y
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=5
++CONFIG_SERIAL_8250_RUNTIME_UARTS=5
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_8250_OMAP=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_SERIAL_XILINX_PS_UART=y
++CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
++CONFIG_SERIAL_FSL_LPUART=y
++CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
++CONFIG_SERIAL_CONEXANT_DIGICOLOR=y
++CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y
++CONFIG_SERIAL_ST_ASC=y
++CONFIG_SERIAL_ST_ASC_CONSOLE=y
++CONFIG_SERIAL_DEV_BUS=y
++CONFIG_VIRTIO_CONSOLE=y
++CONFIG_HW_RANDOM=y
++CONFIG_TCG_TPM=m
++CONFIG_TCG_TIS_I2C_INFINEON=m
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_ARB_GPIO_CHALLENGE=m
++CONFIG_I2C_MUX_GPIO=y
++CONFIG_I2C_MUX_PCA954x=y
++CONFIG_I2C_MUX_PINCTRL=y
++CONFIG_I2C_DEMUX_PINCTRL=y
++CONFIG_I2C_DESIGNWARE_PLATFORM=y
++CONFIG_I2C_EMEV2=m
++CONFIG_I2C_GPIO=m
++CONFIG_I2C_NOMADIK=y
++CONFIG_I2C_RK3X=y
++CONFIG_I2C_XILINX=y
++CONFIG_I2C_CROS_EC_TUNNEL=m
++CONFIG_I2C_SLAVE_EEPROM=y
++CONFIG_SPI=y
++CONFIG_SPI_CADENCE=y
++CONFIG_SPI_GPIO=m
++CONFIG_SPI_OMAP24XX=y
++CONFIG_SPI_PL022=y
++CONFIG_SPI_ROCKCHIP=m
++CONFIG_SPI_XILINX=y
++CONFIG_SPI_SPIDEV=y
++CONFIG_SPI_SLAVE=y
++CONFIG_SPMI=y
++CONFIG_PINCTRL_AS3722=y
++CONFIG_PINCTRL_MICROCHIP_SGPIO=y
++CONFIG_PINCTRL_OCELOT=y
++CONFIG_PINCTRL_PALMAS=y
++CONFIG_PINCTRL_SINGLE=y
++CONFIG_PINCTRL_STMFX=y
++CONFIG_GPIO_DWAPB=y
++CONFIG_GPIO_MPC8XXX=y
++CONFIG_GPIO_PL061=y
++CONFIG_GPIO_SYSCON=y
++CONFIG_GPIO_XILINX=y
++CONFIG_GPIO_PCA953X=y
++CONFIG_GPIO_PCA953X_IRQ=y
++CONFIG_GPIO_PCF857X=y
++CONFIG_GPIO_PALMAS=y
++CONFIG_GPIO_STMPE=y
++CONFIG_GPIO_TPS6586X=y
++CONFIG_GPIO_TPS65910=y
++CONFIG_GPIO_TWL4030=y
++CONFIG_POWER_RESET=y
++CONFIG_POWER_RESET_AS3722=y
++CONFIG_POWER_RESET_BRCMKONA=y
++CONFIG_POWER_RESET_GPIO=y
++CONFIG_POWER_RESET_GPIO_RESTART=y
++CONFIG_POWER_RESET_VEXPRESS=y
++CONFIG_POWER_RESET_SYSCON=y
++CONFIG_POWER_RESET_SYSCON_POWEROFF=y
++CONFIG_BATTERY_ACT8945A=y
++CONFIG_BATTERY_CPCAP=m
++CONFIG_BATTERY_SBS=y
++CONFIG_BATTERY_BQ27XXX=m
++CONFIG_AXP20X_POWER=m
++CONFIG_BATTERY_MAX17040=m
++CONFIG_BATTERY_MAX17042=m
++CONFIG_CHARGER_CPCAP=m
++CONFIG_CHARGER_GPIO=m
++CONFIG_CHARGER_MAX14577=m
++CONFIG_CHARGER_MAX77693=m
++CONFIG_CHARGER_MAX8997=m
++CONFIG_CHARGER_MAX8998=m
++CONFIG_CHARGER_SMB347=m
++CONFIG_CHARGER_TPS65090=y
++CONFIG_SENSORS_ARM_SCMI=y
++CONFIG_SENSORS_IIO_HWMON=y
++CONFIG_SENSORS_LM90=y
++CONFIG_SENSORS_LM95245=y
++CONFIG_SENSORS_NTC_THERMISTOR=m
++CONFIG_SENSORS_PWM_FAN=m
++CONFIG_SENSORS_INA2XX=m
++CONFIG_CPU_THERMAL=y
++CONFIG_DEVFREQ_THERMAL=y
++CONFIG_ROCKCHIP_THERMAL=y
++CONFIG_GENERIC_ADC_THERMAL=m
++CONFIG_WATCHDOG=y
++CONFIG_DA9063_WATCHDOG=m
++CONFIG_XILINX_WATCHDOG=y
++CONFIG_ARM_SP805_WATCHDOG=y
++CONFIG_DW_WATCHDOG=y
++CONFIG_RN5T618_WATCHDOG=y
++CONFIG_STPMIC1_WATCHDOG=y
++CONFIG_BCMA=y
++CONFIG_BCMA_HOST_SOC=y
++CONFIG_BCMA_DRIVER_GMAC_CMN=y
++CONFIG_BCMA_DRIVER_GPIO=y
++CONFIG_MFD_ACT8945A=y
++CONFIG_MFD_AS3711=y
++CONFIG_MFD_AS3722=y
++CONFIG_MFD_ATMEL_FLEXCOM=y
++CONFIG_MFD_ATMEL_HLCDC=m
++CONFIG_MFD_BCM590XX=y
++CONFIG_MFD_AXP20X_I2C=y
++CONFIG_MFD_DA9063=m
++CONFIG_MFD_MAX14577=y
++CONFIG_MFD_MAX77686=y
++CONFIG_MFD_MAX77693=m
++CONFIG_MFD_MAX8907=y
++CONFIG_MFD_MAX8997=y
++CONFIG_MFD_MAX8998=y
++CONFIG_MFD_CPCAP=y
++CONFIG_MFD_PM8XXX=y
++CONFIG_MFD_RK8XX_I2C=y
++CONFIG_MFD_RN5T618=y
++CONFIG_MFD_SEC_CORE=y
++CONFIG_MFD_STMPE=y
++CONFIG_MFD_PALMAS=y
++CONFIG_MFD_TPS65090=y
++CONFIG_MFD_TPS65217=y
++CONFIG_MFD_TPS65218=y
++CONFIG_MFD_TPS6586X=y
++CONFIG_MFD_TPS65910=y
++CONFIG_MFD_WM8994=m
++CONFIG_MFD_STPMIC1=y
++CONFIG_REGULATOR_ACT8865=y
++CONFIG_REGULATOR_ACT8945A=y
++CONFIG_REGULATOR_ARM_SCMI=y
++CONFIG_REGULATOR_AS3711=y
++CONFIG_REGULATOR_AS3722=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_BCM590XX=y
++CONFIG_REGULATOR_CPCAP=y
++CONFIG_REGULATOR_DA9210=y
++CONFIG_REGULATOR_FAN53555=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_LP872X=y
++CONFIG_REGULATOR_MAX14577=m
++CONFIG_REGULATOR_MAX8907=y
++CONFIG_REGULATOR_MAX8952=m
++CONFIG_REGULATOR_MAX8973=y
++CONFIG_REGULATOR_MAX8997=m
++CONFIG_REGULATOR_MAX8998=m
++CONFIG_REGULATOR_MAX77686=y
++CONFIG_REGULATOR_MAX77693=m
++CONFIG_REGULATOR_MAX77802=y
++CONFIG_REGULATOR_PALMAS=y
++CONFIG_REGULATOR_PBIAS=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_REGULATOR_QCOM_SPMI=y
++CONFIG_REGULATOR_RK808=y
++CONFIG_REGULATOR_RN5T618=y
++CONFIG_REGULATOR_S2MPA01=m
++CONFIG_REGULATOR_S2MPS11=y
++CONFIG_REGULATOR_S5M8767=y
++CONFIG_REGULATOR_STPMIC1=y
++CONFIG_REGULATOR_TI_ABB=y
++CONFIG_REGULATOR_TPS51632=y
++CONFIG_REGULATOR_TPS62360=y
++CONFIG_REGULATOR_TPS65090=y
++CONFIG_REGULATOR_TPS65217=y
++CONFIG_REGULATOR_TPS65218=y
++CONFIG_REGULATOR_TPS6586X=y
++CONFIG_REGULATOR_TPS65910=y
++CONFIG_REGULATOR_TWL4030=y
++CONFIG_REGULATOR_VEXPRESS=y
++CONFIG_REGULATOR_WM8994=m
++CONFIG_MEDIA_SUPPORT=m
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_V4L_TEST_DRIVERS=y
++CONFIG_VIDEO_VIVID=m
++CONFIG_VIDEO_S5C73M3=m
++CONFIG_VIDEO_S5K6A3=m
++CONFIG_VIDEO_ADV7180=m
++CONFIG_VIDEO_ADV7604=m
++CONFIG_VIDEO_ADV7604_CEC=y
++CONFIG_VIDEO_ML86V7667=m
++CONFIG_DRM=y
++CONFIG_DRM_I2C_NXP_TDA998X=m
++CONFIG_DRM_ROCKCHIP=y
++CONFIG_ROCKCHIP_ANALOGIX_DP=y
++CONFIG_ROCKCHIP_DW_HDMI=y
++CONFIG_ROCKCHIP_DW_MIPI_DSI=y
++CONFIG_ROCKCHIP_INNO_HDMI=y
++CONFIG_DRM_PANEL_LVDS=m
++CONFIG_DRM_PANEL_SIMPLE=y
++CONFIG_DRM_PANEL_EDP=y
++CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
++CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
++CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
++CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
++CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
++CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
++CONFIG_DRM_DISPLAY_CONNECTOR=m
++CONFIG_DRM_LVDS_CODEC=m
++CONFIG_DRM_NXP_PTN3460=m
++CONFIG_DRM_PARADE_PS8622=m
++CONFIG_DRM_SAMSUNG_DSIM=m
++CONFIG_DRM_SII902X=m
++CONFIG_DRM_SII9234=m
++CONFIG_DRM_SIMPLE_BRIDGE=m
++CONFIG_DRM_TOSHIBA_TC358764=m
++CONFIG_DRM_TOSHIBA_TC358768=m
++CONFIG_DRM_TI_TFP410=m
++CONFIG_DRM_TI_TPD12S015=m
++CONFIG_DRM_I2C_ADV7511=m
++CONFIG_DRM_I2C_ADV7511_AUDIO=y
++CONFIG_DRM_LIMA=y
++CONFIG_FB=y
++CONFIG_FB_EFI=y
++CONFIG_FB_SIMPLE=y
++CONFIG_FB_MODE_HELPERS=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_BACKLIGHT_AS3711=y
++CONFIG_BACKLIGHT_GPIO=y
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
++CONFIG_LOGO=y
++CONFIG_SOUND=m
++CONFIG_SND=m
++CONFIG_SND_DYNAMIC_MINORS=y
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_SOC=m
++CONFIG_SND_ATMEL_SOC=m
++CONFIG_SND_SOC_FSL_SAI=m
++CONFIG_SND_SOC_FSL_SSI=m
++CONFIG_SND_SOC_FSL_ESAI=m
++CONFIG_SND_SOC_IMX_AUDMUX=m
++CONFIG_SND_SOC_ROCKCHIP=m
++CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
++CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
++CONFIG_SND_SOC_ROCKCHIP_RT5645=m
++CONFIG_SND_SOC_DAVINCI_MCASP=m
++CONFIG_SND_SOC_AC97_CODEC=m
++CONFIG_SND_SOC_AK4642=m
++CONFIG_SND_SOC_CPCAP=m
++CONFIG_SND_SOC_CS42L51_I2C=m
++CONFIG_SND_SOC_DMIC=m
++CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
++CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
++CONFIG_SND_SOC_RT5631=m
++CONFIG_SND_SOC_RT5640=m
++CONFIG_SND_SOC_SGTL5000=m
++CONFIG_SND_SOC_SPDIF=m
++CONFIG_SND_SOC_STI_SAS=m
++CONFIG_SND_SOC_TLV320AIC23_I2C=m
++CONFIG_SND_SOC_TLV320AIC31XX=m
++CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
++CONFIG_SND_SOC_TLV320AIC3X_I2C=m
++CONFIG_SND_SOC_WM8753=m
++CONFIG_SND_SOC_WM8903=m
++CONFIG_SND_SOC_WM8904=m
++CONFIG_SND_SOC_WM8960=m
++CONFIG_SND_SOC_WM8962=m
++CONFIG_SND_SOC_WM8978=m
++CONFIG_SND_SIMPLE_CARD=m
++CONFIG_SND_AUDIO_GRAPH_CARD=m
++CONFIG_USB_CONN_GPIO=y
++CONFIG_USB=y
++CONFIG_USB_OTG=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_FSL=m
++CONFIG_USB_EHCI_HCD_PLATFORM=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_R8A66597_HCD=m
++CONFIG_USB_STORAGE=y
++CONFIG_USB_UAS=m
++CONFIG_USB_MUSB_HDRC=m
++CONFIG_USB_MUSB_TUSB6010=m
++CONFIG_USB_MUSB_OMAP2PLUS=m
++CONFIG_USB_MUSB_DSPS=m
++CONFIG_USB_INVENTRA_DMA=y
++CONFIG_USB_TI_CPPI41_DMA=y
++CONFIG_USB_TUSB_OMAP_DMA=y
++CONFIG_USB_DWC3=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_CHIPIDEA=y
++CONFIG_USB_CHIPIDEA_UDC=y
++CONFIG_USB_CHIPIDEA_HOST=y
++CONFIG_USB_ISP1760=y
++CONFIG_USB_HSIC_USB3503=y
++CONFIG_USB_ONBOARD_HUB=m
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_AM335X_PHY_USB=m
++CONFIG_TWL6030_USB=m
++CONFIG_USB_ISP1301=y
++CONFIG_USB_ULPI=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_SNP_UDC_PLAT=y
++CONFIG_USB_BDC_UDC=y
++CONFIG_USB_CONFIGFS=m
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_MIDI=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_UVC=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_USB_ETH=m
++CONFIG_TYPEC=m
++CONFIG_TYPEC_UCSI=m
++CONFIG_UCSI_STM32G0=m
++CONFIG_TYPEC_STUSB160X=m
++CONFIG_MMC=y
++CONFIG_MMC_BLOCK_MINORS=16
++CONFIG_MMC_ARMMMCI=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_OF_ARASAN=y
++CONFIG_MMC_SDHCI_OF_AT91=y
++CONFIG_MMC_OMAP=y
++CONFIG_MMC_OMAP_HS=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_EXYNOS=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_MMC_SDHCI_OMAP=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS_FLASH=m
++CONFIG_LEDS_CPCAP=m
++CONFIG_LEDS_PCA9532=m
++CONFIG_LEDS_PCA9532_GPIO=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_PWM=y
++CONFIG_LEDS_MAX8997=m
++CONFIG_LEDS_MAX77693=m
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_BACKLIGHT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_GPIO=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_TRANSIENT=y
++CONFIG_LEDS_TRIGGER_CAMERA=y
++CONFIG_LEDS_TRIGGER_AUDIO=m
++CONFIG_EDAC=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_DRV_AS3722=y
++CONFIG_RTC_DRV_DS1307=y
++CONFIG_RTC_DRV_HYM8563=m
++CONFIG_RTC_DRV_MAX8907=y
++CONFIG_RTC_DRV_MAX8998=m
++CONFIG_RTC_DRV_MAX8997=m
++CONFIG_RTC_DRV_MAX77686=y
++CONFIG_RTC_DRV_RK808=m
++CONFIG_RTC_DRV_RS5C372=m
++CONFIG_RTC_DRV_PCF85063=m
++CONFIG_RTC_DRV_PCF85363=m
++CONFIG_RTC_DRV_BQ32K=m
++CONFIG_RTC_DRV_TWL4030=y
++CONFIG_RTC_DRV_PALMAS=y
++CONFIG_RTC_DRV_TPS6586X=y
++CONFIG_RTC_DRV_TPS65910=y
++CONFIG_RTC_DRV_S35390A=m
++CONFIG_RTC_DRV_RX8581=m
++CONFIG_RTC_DRV_EM3027=y
++CONFIG_RTC_DRV_S5M=m
++CONFIG_RTC_DRV_DA9063=m
++CONFIG_RTC_DRV_EFI=m
++CONFIG_RTC_DRV_PL031=y
++CONFIG_RTC_DRV_PM8XXX=m
++CONFIG_RTC_DRV_CPCAP=m
++CONFIG_DMADEVICES=y
++CONFIG_FSL_EDMA=y
++CONFIG_PL330_DMA=y
++CONFIG_XILINX_DMA=y
++CONFIG_DW_DMAC=y
++CONFIG_VIRTIO_PCI=y
++CONFIG_VIRTIO_MMIO=y
++CONFIG_STAGING=y
++CONFIG_STAGING_BOARD=y
++CONFIG_CHROME_PLATFORMS=y
++CONFIG_CROS_EC=m
++CONFIG_CROS_EC_I2C=m
++CONFIG_CROS_EC_SPI=m
++CONFIG_CLK_ICST=y
++CONFIG_CLK_SP810=y
++CONFIG_CLK_VEXPRESS_OSC=y
++CONFIG_COMMON_CLK_MAX77686=y
++CONFIG_COMMON_CLK_RK808=m
++CONFIG_COMMON_CLK_SCMI=y
++CONFIG_COMMON_CLK_S2MPS11=m
++CONFIG_HWSPINLOCK=y
++CONFIG_HWSPINLOCK_OMAP=y
++CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2
++CONFIG_MICROCHIP_PIT64B=y
++CONFIG_PL320_MBOX=y
++CONFIG_OMAP2PLUS_MBOX=y
++CONFIG_IOMMU_IO_PGTABLE_LPAE=y
++CONFIG_OMAP_IOMMU=y
++CONFIG_OMAP_IOMMU_DEBUG=y
++CONFIG_ROCKCHIP_IOMMU=y
++CONFIG_REMOTEPROC=y
++CONFIG_OMAP_REMOTEPROC=m
++CONFIG_OMAP_REMOTEPROC_WATCHDOG=y
++CONFIG_RPMSG_VIRTIO=m
++CONFIG_ROCKCHIP_IODOMAIN=y
++CONFIG_ROCKCHIP_PM_DOMAINS=y
++CONFIG_DEVFREQ_GOV_PASSIVE=m
++CONFIG_PM_DEVFREQ_EVENT=y
++CONFIG_EXTCON_MAX14577=m
++CONFIG_EXTCON_MAX77693=m
++CONFIG_EXTCON_MAX8997=m
++CONFIG_EXTCON_USB_GPIO=y
++CONFIG_IIO=y
++CONFIG_IIO_BUFFER_HW_CONSUMER=m
++CONFIG_IIO_SW_TRIGGER=y
++CONFIG_CPCAP_ADC=m
++CONFIG_QCOM_SPMI_VADC=m
++CONFIG_ROCKCHIP_SARADC=m
++CONFIG_STMPE_ADC=m
++CONFIG_VF610_ADC=m
++CONFIG_XILINX_XADC=y
++CONFIG_IIO_CROS_EC_SENSORS_CORE=m
++CONFIG_IIO_CROS_EC_SENSORS=m
++CONFIG_MPU3050_I2C=y
++CONFIG_CM36651=m
++CONFIG_IIO_CROS_EC_LIGHT_PROX=m
++CONFIG_SENSORS_ISL29018=y
++CONFIG_SENSORS_ISL29028=y
++CONFIG_AK8975=y
++CONFIG_IIO_HRTIMER_TRIGGER=y
++CONFIG_PWM=y
++CONFIG_PWM_ATMEL_HLCDC_PWM=m
++CONFIG_PWM_ATMEL_TCB=m
++CONFIG_PWM_FSL_FTM=m
++CONFIG_PWM_ROCKCHIP=m
++CONFIG_RESET_SIMPLE=y
++CONFIG_PHY_LAN966X_SERDES=m
++CONFIG_PHY_CPCAP_USB=m
++CONFIG_PHY_QCOM_USB_HS=y
++CONFIG_PHY_ROCKCHIP_DP=m
++CONFIG_PHY_ROCKCHIP_USB=y
++CONFIG_PHY_SAMSUNG_USB2=m
++CONFIG_PHY_DM816X_USB=m
++CONFIG_OMAP_USB2=y
++CONFIG_TI_PIPE3=y
++CONFIG_TWL4030_USB=m
++CONFIG_RAS=y
++CONFIG_NVMEM_RMEM=m
++CONFIG_NVMEM_ROCKCHIP_EFUSE=m
++CONFIG_FSI=m
++CONFIG_FSI_MASTER_GPIO=m
++CONFIG_FSI_MASTER_HUB=m
++CONFIG_FSI_MASTER_ASPEED=m
++CONFIG_FSI_SCOM=m
++CONFIG_FSI_SBEFIFO=m
++CONFIG_FSI_OCC=m
++CONFIG_TEE=y
++CONFIG_OPTEE=y
++CONFIG_INTERCONNECT=y
++CONFIG_COUNTER=m
++CONFIG_EXT4_FS=y
++CONFIG_AUTOFS_FS=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_NTFS_FS=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_UBIFS_FS=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_PSTORE=y
++CONFIG_PSTORE_CONSOLE=y
++CONFIG_PSTORE_PMSG=y
++CONFIG_PSTORE_RAM=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_NFS_V4_1=y
++CONFIG_NFS_V4_2=y
++CONFIG_ROOT_NFS=y
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_UTF8=y
++CONFIG_CRYPTO_USER=m
++CONFIG_CRYPTO_XTS=m
++CONFIG_CRYPTO_USER_API_HASH=m
++CONFIG_CRYPTO_USER_API_SKCIPHER=m
++CONFIG_CRYPTO_USER_API_RNG=m
++CONFIG_CRYPTO_USER_API_AEAD=m
++CONFIG_CRYPTO_GHASH_ARM_CE=m
++CONFIG_CRYPTO_SHA1_ARM_NEON=m
++CONFIG_CRYPTO_SHA1_ARM_CE=m
++CONFIG_CRYPTO_SHA2_ARM_CE=m
++CONFIG_CRYPTO_SHA512_ARM=m
++CONFIG_CRYPTO_AES_ARM=m
++CONFIG_CRYPTO_AES_ARM_BS=m
++CONFIG_CRYPTO_AES_ARM_CE=m
++CONFIG_CRYPTO_CHACHA20_NEON=m
++CONFIG_CRYPTO_CRC32_ARM_CE=m
++CONFIG_CRYPTO_DEV_ROCKCHIP=m
++CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=64
++CONFIG_PRINTK_TIME=y
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
diff --git a/beba499cda3702062e7708b6b402d07b26d090e5.patch b/beba499cda3702062e7708b6b402d07b26d090e5.patch
new file mode 100644
index 0000000..e54ccd9
--- /dev/null
+++ b/beba499cda3702062e7708b6b402d07b26d090e5.patch
@@ -0,0 +1,38 @@
+From beba499cda3702062e7708b6b402d07b26d090e5 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Sat, 13 Apr 2024 19:42:21 +0800
+Subject: [PATCH] drm/panthor: Add defer probe for firmware load
+
+The firmware in the rootfs will not be accessible until we
+are in the SYSTEM_RUNNING state, so return EPROBE_DEFER until
+that point.
+This let the driver can load firmware when it is builtin.
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ drivers/gpu/drm/panthor/panthor_fw.c | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor/panthor_fw.c
+index ecca5565ce41a7..d1cd5a6e18d969 100644
+--- a/drivers/gpu/drm/panthor/panthor_fw.c
++++ b/drivers/gpu/drm/panthor/panthor_fw.c
+@@ -1399,8 +1399,17 @@ int panthor_fw_init(struct panthor_device *ptdev)
+ 	}
+ 
+ 	ret = panthor_fw_load(ptdev);
+-	if (ret)
++	if (ret) {
++		/*
++		 * The firmware in the rootfs will not be accessible until we
++		 * are in the SYSTEM_RUNNING state, so return EPROBE_DEFER until
++		 * that point.
++		 */
++		if (system_state < SYSTEM_RUNNING)
++			ret = -EPROBE_DEFER;
++
+ 		goto err_unplug_fw;
++	}
+ 
+ 	ret = panthor_vm_active(fw->vm);
+ 	if (ret)
diff --git a/bluetooth.fragment b/bluetooth.fragment
new file mode 100644
index 0000000..d780f95
--- /dev/null
+++ b/bluetooth.fragment
@@ -0,0 +1,69 @@
+CONFIG_BT=m
+CONFIG_BT_BREDR=y
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_CMTP=m
+CONFIG_BT_HIDP=m
+CONFIG_BT_HS=y
+CONFIG_BT_LE=y
+CONFIG_BT_LE_L2CAP_ECRED=y
+CONFIG_BT_6LOWPAN=m
+CONFIG_BT_LEDS=y
+CONFIG_BT_MSFTEXT=y
+CONFIG_BT_AOSPEXT=y
+CONFIG_BT_DEBUGFS=y
+# CONFIG_BT_SELFTEST is not set
+# CONFIG_BT_FEATURE_DEBUG is not set
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_INTEL=m
+CONFIG_BT_BCM=m
+CONFIG_BT_RTL=m
+CONFIG_BT_QCA=m
+CONFIG_BT_MTK=m
+CONFIG_BT_HCIBTUSB=m
+# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
+CONFIG_BT_HCIBTUSB_POLL_SYNC=y
+CONFIG_BT_HCIBTUSB_AUTO_ISOC_ALT=y
+CONFIG_BT_HCIBTUSB_BCM=y
+CONFIG_BT_HCIBTUSB_MTK=y
+CONFIG_BT_HCIBTUSB_RTL=y
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_SERDEV=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_NOKIA=m
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIUART_INTEL=y
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_BT_HCIUART_RTL=y
+CONFIG_BT_HCIUART_QCA=y
+CONFIG_BT_HCIUART_AG6XX=y
+CONFIG_BT_HCIUART_MRVL=y
+CONFIG_BT_HCIUART_AML=y
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBCM4377=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIDTL1=m
+CONFIG_BT_HCIBT3C=m
+CONFIG_BT_HCIBLUECARD=m
+CONFIG_BT_HCIVHCI=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+CONFIG_BT_ATH3K=m
+CONFIG_BT_MTKSDIO=m
+CONFIG_BT_MTKUART=m
+CONFIG_BT_QCOMSMD=m
+CONFIG_BT_HCIRSI=m
+CONFIG_BT_VIRTIO=m
+CONFIG_BT_NXPUART=m
+CONFIG_BT_INTEL_PCIE=m
+# end of Bluetooth device drivers
diff --git a/board-rockpi4-FixMMCFreq.patch b/board-rockpi4-FixMMCFreq.patch
deleted file mode 100644
index b23898d..0000000
--- a/board-rockpi4-FixMMCFreq.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi	2021-01-21 12:54:16.967891868 +0800
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi	2021-01-21 13:04:10.214771523 +0800
-@@ -697,6 +697,7 @@
- };
- 
- &sdhci {
-+	max-frequency = <150000000>;
- 	bus-width = <8>;
- 	mmc-hs400-1_8v;
- 	mmc-hs400-enhanced-strobe;
diff --git a/board-rockpro64-fix-spi1-flash-speed.patch b/board-rockpro64-fix-spi1-flash-speed.patch
deleted file mode 100644
index 51dc2a9..0000000
--- a/board-rockpro64-fix-spi1-flash-speed.patch
+++ /dev/null
@@ -1,13 +0,0 @@
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
-index 49050de8c..714616618 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
-@@ -646,7 +646,7 @@
- 	flash@0 {
- 		compatible = "jedec,spi-nor";
- 		reg = <0>;
--		spi-max-frequency = <10000000>;
-+		spi-max-frequency = <3000000>;
- 	};
- };
- 
diff --git a/bpftool-binutils-2.39.patch b/bpftool-binutils-2.39.patch
deleted file mode 100644
index 3fcfd61..0000000
--- a/bpftool-binutils-2.39.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-diff -up linux-5.19/tools/bpf/bpftool/jit_disasm.c.omv~ linux-5.19/tools/bpf/bpftool/jit_disasm.c
---- linux-5.19/tools/bpf/bpftool/jit_disasm.c.omv~	2022-08-14 17:05:07.060719763 +0200
-+++ linux-5.19/tools/bpf/bpftool/jit_disasm.c	2022-08-14 21:36:52.395937489 +0200
-@@ -73,6 +73,21 @@ static int fprintf_json(void *out, const
- 	return 0;
- }
- 
-+static int __attribute__ ((__format__ (__printf__, 3, 4))) __attribute__((__nonnull__ (3)))
-+fprintf_styled (FILE *f, enum disassembler_style style __attribute__((unused)),
-+                const char *fmt, ...)
-+{
-+	int res;
-+	va_list ap;
-+
-+	va_start (ap, fmt);
-+	res = vfprintf (f, fmt, ap);
-+	va_end (ap);
-+
-+	return res;
-+}
-+
-+
- void disasm_print_insn(unsigned char *image, ssize_t len, int opcodes,
- 		       const char *arch, const char *disassembler_options,
- 		       const struct btf *btf,
-@@ -100,10 +115,10 @@ void disasm_print_insn(unsigned char *im
- 
- 	if (json_output)
- 		init_disassemble_info(&info, stdout,
--				      (fprintf_ftype) fprintf_json);
-+				      (fprintf_ftype) fprintf_json, (fprintf_styled_ftype) fprintf_styled);
- 	else
- 		init_disassemble_info(&info, stdout,
--				      (fprintf_ftype) fprintf);
-+				      (fprintf_ftype) fprintf, (fprintf_styled_ftype) fprintf_styled);
- 
- 	/* Update architecture info for offload. */
- 	if (arch) {
diff --git a/c8699f87d802bbb6e5aab8292f2e285c56976a35.patch b/c8699f87d802bbb6e5aab8292f2e285c56976a35.patch
new file mode 100644
index 0000000..8586c1a
--- /dev/null
+++ b/c8699f87d802bbb6e5aab8292f2e285c56976a35.patch
@@ -0,0 +1,35 @@
+From c8699f87d802bbb6e5aab8292f2e285c56976a35 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 24 Oct 2023 16:09:35 +0200
+Subject: [PATCH] math.h: add DIV_ROUND_UP_NO_OVERFLOW
+
+Add a new DIV_ROUND_UP helper, which cannot overflow when
+big numbers are being used.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ include/linux/math.h | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/include/linux/math.h b/include/linux/math.h
+index f5f18dc3616b01..179bddeec31d71 100644
+--- a/include/linux/math.h
++++ b/include/linux/math.h
+@@ -36,6 +36,17 @@
+ 
+ #define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP
+ 
++/**
++ * DIV_ROUND_UP_NO_OVERFLOW - divide two numbers and always round up
++ * @n: numerator / dividend
++ * @d: denominator / divisor
++ *
++ * This functions does the same as DIV_ROUND_UP, but internally uses a
++ * division and a modulo operation instead of math tricks. This way it
++ * avoids overflowing when handling big numbers.
++ */
++#define DIV_ROUND_UP_NO_OVERFLOW(n, d) (((n) / (d)) + !!((n) % (d)))
++
+ #define DIV_ROUND_DOWN_ULL(ll, d) \
+ 	({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
+ 
diff --git a/cc17a3358bece56c8932b6a62da242f841feb2e2.patch b/cc17a3358bece56c8932b6a62da242f841feb2e2.patch
new file mode 100644
index 0000000..c9b6ee5
--- /dev/null
+++ b/cc17a3358bece56c8932b6a62da242f841feb2e2.patch
@@ -0,0 +1,1010 @@
+From cc17a3358bece56c8932b6a62da242f841feb2e2 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Fri, 28 Jun 2024 18:00:16 +0800
+Subject: [PATCH] arm64: add rpi_defconfig
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm64/configs/rpi_defconfig | 993 +++++++++++++++++++++++++++++++
+ 1 file changed, 993 insertions(+)
+ create mode 100644 arch/arm64/configs/rpi_defconfig
+
+diff --git a/arch/arm64/configs/rpi_defconfig b/arch/arm64/configs/rpi_defconfig
+new file mode 100644
+index 00000000000000..e66d23487a4447
+--- /dev/null
++++ b/arch/arm64/configs/rpi_defconfig
+@@ -0,0 +1,993 @@
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_AUDIT=y
++CONFIG_NO_HZ_IDLE=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_BPF_JIT=y
++CONFIG_PREEMPT=y
++CONFIG_IRQ_TIME_ACCOUNTING=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_NUMA_BALANCING=y
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CGROUP_HUGETLB=y
++CONFIG_CPUSETS=y
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_CGROUP_PERF=y
++CONFIG_CGROUP_BPF=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_KALLSYMS_ALL=y
++CONFIG_PROFILING=y
++CONFIG_KEXEC=y
++CONFIG_KEXEC_FILE=y
++CONFIG_ARCH_BCM=y
++CONFIG_ARCH_BCM2835=y
++CONFIG_ARCH_BCM_IPROC=y
++CONFIG_ARCH_BCMBCA=y
++CONFIG_ARCH_BRCMSTB=y
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SCHED_MC=y
++CONFIG_SCHED_SMT=y
++CONFIG_NUMA=y
++CONFIG_XEN=y
++CONFIG_COMPAT=y
++CONFIG_RANDOMIZE_BASE=y
++CONFIG_HIBERNATION=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_ENERGY_MODEL=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=m
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
++CONFIG_CPUFREQ_DT=y
++CONFIG_ARM_SCPI_CPUFREQ=y
++CONFIG_ARM_RASPBERRYPI_CPUFREQ=m
++CONFIG_ARM_SCMI_CPUFREQ=y
++CONFIG_ACPI_CPPC_CPUFREQ=m
++CONFIG_ACPI=y
++CONFIG_ACPI_HOTPLUG_MEMORY=y
++CONFIG_ACPI_HMAT=y
++CONFIG_ACPI_APEI=y
++CONFIG_ACPI_APEI_GHES=y
++CONFIG_ACPI_APEI_PCIEAER=y
++CONFIG_ACPI_APEI_MEMORY_FAILURE=y
++CONFIG_ACPI_APEI_EINJ=y
++CONFIG_VIRTUALIZATION=y
++CONFIG_KVM=y
++CONFIG_JUMP_LABEL=y
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++# CONFIG_COMPAT_BRK is not set
++CONFIG_MEMORY_HOTPLUG=y
++CONFIG_MEMORY_HOTREMOVE=y
++CONFIG_KSM=y
++CONFIG_MEMORY_FAILURE=y
++CONFIG_TRANSPARENT_HUGEPAGE=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++CONFIG_IPV6=m
++CONFIG_NETFILTER=y
++CONFIG_BRIDGE_NETFILTER=m
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_EVENTS=y
++CONFIG_NETFILTER_XT_MARK=m
++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
++CONFIG_NETFILTER_XT_TARGET_LOG=m
++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
++CONFIG_NETFILTER_XT_MATCH_IPVS=m
++CONFIG_IP_VS=m
++CONFIG_IP_NF_IPTABLES=m
++CONFIG_IP_NF_FILTER=m
++CONFIG_IP_NF_TARGET_REJECT=m
++CONFIG_IP_NF_NAT=m
++CONFIG_IP_NF_TARGET_MASQUERADE=m
++CONFIG_IP_NF_MANGLE=m
++CONFIG_IP6_NF_IPTABLES=m
++CONFIG_IP6_NF_FILTER=m
++CONFIG_IP6_NF_TARGET_REJECT=m
++CONFIG_IP6_NF_MANGLE=m
++CONFIG_IP6_NF_NAT=m
++CONFIG_IP6_NF_TARGET_MASQUERADE=m
++CONFIG_BRIDGE=m
++CONFIG_BRIDGE_VLAN_FILTERING=y
++CONFIG_NET_DSA=m
++CONFIG_NET_DSA_TAG_OCELOT=m
++CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
++CONFIG_VLAN_8021Q=m
++CONFIG_VLAN_8021Q_GVRP=y
++CONFIG_VLAN_8021Q_MVRP=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_CBS=m
++CONFIG_NET_SCH_ETF=m
++CONFIG_NET_SCH_TAPRIO=m
++CONFIG_NET_SCH_MQPRIO=m
++CONFIG_NET_SCH_INGRESS=m
++CONFIG_NET_CLS_BASIC=m
++CONFIG_NET_CLS_FLOWER=m
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_GACT=m
++CONFIG_NET_ACT_MIRRED=m
++CONFIG_NET_ACT_GATE=m
++CONFIG_QRTR_SMD=m
++CONFIG_QRTR_TUN=m
++CONFIG_CAN=m
++CONFIG_BT=m
++CONFIG_BT_HIDP=m
++# CONFIG_BT_LE is not set
++CONFIG_BT_LEDS=y
++# CONFIG_BT_DEBUGFS is not set
++CONFIG_BT_HCIBTUSB=m
++CONFIG_BT_HCIBTUSB_MTK=y
++CONFIG_BT_HCIUART=m
++CONFIG_BT_HCIUART_LL=y
++CONFIG_BT_HCIUART_BCM=y
++CONFIG_BT_HCIUART_QCA=y
++CONFIG_BT_HCIUART_MRVL=y
++CONFIG_BT_MRVL=m
++CONFIG_BT_MRVL_SDIO=m
++CONFIG_BT_NXPUART=m
++CONFIG_CFG80211=m
++CONFIG_MAC80211=m
++CONFIG_MAC80211_LEDS=y
++CONFIG_RFKILL=m
++CONFIG_NET_9P=y
++CONFIG_NET_9P_VIRTIO=y
++CONFIG_NFC=m
++CONFIG_NFC_NCI=m
++CONFIG_NFC_S3FWRN5_I2C=m
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_PCI=y
++CONFIG_PCIEPORTBUS=y
++CONFIG_PCIEAER=y
++CONFIG_PCI_IOV=y
++CONFIG_PCI_PASID=y
++CONFIG_HOTPLUG_PCI=y
++CONFIG_HOTPLUG_PCI_ACPI=y
++CONFIG_PCIE_ALTERA=y
++CONFIG_PCIE_ALTERA_MSI=y
++CONFIG_PCIE_BRCMSTB=m
++CONFIG_PCI_HOST_THUNDER_PEM=y
++CONFIG_PCI_HOST_THUNDER_ECAM=y
++CONFIG_PCI_HOST_GENERIC=y
++CONFIG_PCIE_ROCKCHIP_HOST=m
++CONFIG_PCI_XGENE=y
++CONFIG_PCI_MESON=m
++CONFIG_PCI_HISI=y
++CONFIG_PCIE_KIRIN=y
++CONFIG_PCIE_ROCKCHIP_DW_HOST=y
++CONFIG_PCI_ENDPOINT=y
++CONFIG_PCI_ENDPOINT_CONFIGFS=y
++CONFIG_PCI_EPF_TEST=m
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_FW_LOADER_USER_HELPER=y
++CONFIG_VEXPRESS_CONFIG=y
++CONFIG_MHI_BUS_PCI_GENERIC=m
++CONFIG_ARM_SCMI_PROTOCOL=y
++CONFIG_ARM_SCPI_PROTOCOL=y
++CONFIG_RASPBERRYPI_FIRMWARE=y
++CONFIG_GOOGLE_FIRMWARE=y
++CONFIG_GOOGLE_CBMEM=m
++CONFIG_GOOGLE_COREBOOT_TABLE=m
++CONFIG_EFI_CAPSULE_LOADER=y
++CONFIG_GNSS=m
++CONFIG_GNSS_MTK_SERIAL=m
++CONFIG_MTD=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_CFI=y
++CONFIG_MTD_CFI_ADV_OPTIONS=y
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++CONFIG_MTD_CFI_STAA=y
++CONFIG_MTD_PHYSMAP=y
++CONFIG_MTD_PHYSMAP_OF=y
++CONFIG_MTD_DATAFLASH=y
++CONFIG_MTD_SST25L=y
++CONFIG_MTD_RAW_NAND=y
++CONFIG_MTD_NAND_DENALI_DT=y
++CONFIG_MTD_NAND_BRCMNAND=m
++CONFIG_MTD_SPI_NOR=y
++CONFIG_MTD_UBI=m
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_NBD=m
++CONFIG_VIRTIO_BLK=y
++CONFIG_BLK_DEV_NVME=m
++CONFIG_SRAM=y
++CONFIG_PCI_ENDPOINT_TEST=m
++CONFIG_EEPROM_AT24=m
++CONFIG_EEPROM_AT25=m
++CONFIG_UACCE=m
++# CONFIG_SCSI_PROC_FS is not set
++CONFIG_BLK_DEV_SD=y
++CONFIG_SCSI_SAS_ATA=y
++CONFIG_SCSI_HISI_SAS=y
++CONFIG_SCSI_HISI_SAS_PCI=y
++CONFIG_MEGARAID_SAS=y
++CONFIG_SCSI_MPT3SAS=m
++CONFIG_ATA=y
++CONFIG_SATA_AHCI=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_BRCM=m
++CONFIG_AHCI_DWC=m
++CONFIG_AHCI_CEVA=y
++CONFIG_SATA_SIL24=y
++CONFIG_PATA_OF_PLATFORM=y
++CONFIG_MD=y
++CONFIG_BLK_DEV_MD=m
++CONFIG_BLK_DEV_DM=m
++CONFIG_DM_MIRROR=m
++CONFIG_DM_ZERO=m
++CONFIG_NETDEVICES=y
++CONFIG_MACVLAN=m
++CONFIG_MACVTAP=m
++CONFIG_TUN=y
++CONFIG_VETH=m
++CONFIG_VIRTIO_NET=y
++CONFIG_MHI_NET=m
++CONFIG_NET_DSA_BCM_SF2=m
++CONFIG_AMD_XGBE=y
++CONFIG_ATL1C=m
++CONFIG_BCMGENET=y
++CONFIG_BNX2X=m
++CONFIG_SYSTEMPORT=m
++CONFIG_MACB=y
++CONFIG_THUNDER_NIC_PF=y
++CONFIG_HIX5HD2_GMAC=y
++CONFIG_HNS_DSAF=y
++CONFIG_HNS_ENET=y
++CONFIG_HNS3=y
++CONFIG_HNS3_HCLGE=y
++CONFIG_HNS3_ENET=y
++CONFIG_E1000=y
++CONFIG_E1000E=y
++CONFIG_IGB=y
++CONFIG_IGBVF=y
++CONFIG_MVMDIO=y
++CONFIG_SKY2=y
++CONFIG_MLX4_EN=m
++CONFIG_MLX5_CORE=m
++CONFIG_MLX5_CORE_EN=y
++CONFIG_QCOM_EMAC=m
++CONFIG_RMNET=m
++CONFIG_R8169=m
++CONFIG_SMC91X=y
++CONFIG_SMSC911X=y
++CONFIG_STMMAC_ETH=m
++CONFIG_AQUANTIA_PHY=y
++CONFIG_BCM54140_PHY=m
++CONFIG_MARVELL_PHY=m
++CONFIG_MARVELL_10G_PHY=y
++CONFIG_MICREL_PHY=y
++CONFIG_MICROSEMI_PHY=y
++CONFIG_AT803X_PHY=y
++CONFIG_REALTEK_PHY=y
++CONFIG_ROCKCHIP_PHY=y
++CONFIG_DP83867_PHY=y
++CONFIG_DP83869_PHY=m
++CONFIG_DP83TD510_PHY=y
++CONFIG_VITESSE_PHY=y
++CONFIG_CAN_FLEXCAN=m
++CONFIG_CAN_M_CAN=m
++CONFIG_CAN_M_CAN_PLATFORM=m
++CONFIG_CAN_MCP251XFD=m
++CONFIG_MDIO_BITBANG=y
++CONFIG_MDIO_GPIO=y
++CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
++CONFIG_MDIO_BUS_MUX_MMIOREG=y
++CONFIG_USB_PEGASUS=m
++CONFIG_USB_RTL8150=m
++CONFIG_USB_RTL8152=m
++CONFIG_USB_LAN78XX=m
++CONFIG_USB_USBNET=m
++CONFIG_USB_NET_DM9601=m
++CONFIG_USB_NET_SR9800=m
++CONFIG_USB_NET_SMSC75XX=m
++CONFIG_USB_NET_SMSC95XX=m
++CONFIG_USB_NET_PLUSB=m
++CONFIG_USB_NET_MCS7830=m
++CONFIG_ATH10K=m
++CONFIG_ATH10K_PCI=m
++CONFIG_ATH10K_SDIO=m
++CONFIG_WCN36XX=m
++CONFIG_ATH11K=m
++CONFIG_ATH11K_AHB=m
++CONFIG_ATH11K_PCI=m
++CONFIG_ATH12K=m
++CONFIG_BRCMFMAC=m
++CONFIG_MWIFIEX=m
++CONFIG_MWIFIEX_SDIO=m
++CONFIG_MWIFIEX_PCIE=m
++CONFIG_MT7921E=m
++CONFIG_RSI_91X=m
++CONFIG_WL18XX=m
++CONFIG_WLCORE_SDIO=m
++CONFIG_WWAN=m
++CONFIG_MHI_WWAN_CTRL=m
++CONFIG_MHI_WWAN_MBIM=m
++CONFIG_INPUT_EVDEV=y
++CONFIG_KEYBOARD_ADC=m
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=m
++CONFIG_KEYBOARD_CROS_EC=y
++CONFIG_KEYBOARD_MTK_PMIC=m
++CONFIG_MOUSE_ELAN_I2C=m
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_ATMEL_MXT=m
++CONFIG_TOUCHSCREEN_GOODIX=m
++CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI=m
++CONFIG_TOUCHSCREEN_ELAN=m
++CONFIG_TOUCHSCREEN_EDT_FT5X06=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_TPS65219_PWRBUTTON=m
++CONFIG_INPUT_PWM_BEEPER=m
++CONFIG_INPUT_PWM_VIBRA=m
++CONFIG_INPUT_RK805_PWRKEY=m
++CONFIG_INPUT_DA9063_ONKEY=m
++# CONFIG_SERIO_SERPORT is not set
++CONFIG_SERIO_AMBAKMI=y
++CONFIG_LEGACY_PTY_COUNT=16
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_BCM2835AUX=y
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_SERIAL_XILINX_PS_UART=y
++CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
++CONFIG_SERIAL_FSL_LPUART=y
++CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
++CONFIG_SERIAL_FSL_LINFLEXUART=y
++CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
++CONFIG_SERIAL_DEV_BUS=y
++CONFIG_VIRTIO_CONSOLE=y
++CONFIG_IPMI_HANDLER=m
++CONFIG_IPMI_DEVICE_INTERFACE=m
++CONFIG_IPMI_SI=m
++CONFIG_HW_RANDOM=y
++CONFIG_HW_RANDOM_VIRTIO=y
++CONFIG_TCG_TPM=y
++CONFIG_TCG_TIS=m
++CONFIG_TCG_TIS_SPI=m
++CONFIG_TCG_TIS_SPI_CR50=y
++CONFIG_TCG_TIS_I2C_CR50=m
++CONFIG_TCG_TIS_I2C_INFINEON=y
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_MUX_PCA954x=y
++CONFIG_I2C_BCM2835=y
++CONFIG_I2C_CADENCE=m
++CONFIG_I2C_DESIGNWARE_PLATFORM=y
++CONFIG_I2C_GPIO=m
++CONFIG_I2C_RK3X=y
++CONFIG_I2C_CROS_EC_TUNNEL=y
++CONFIG_SPI=y
++CONFIG_SPI_BCM2835=y
++CONFIG_SPI_BCM2835AUX=m
++CONFIG_SPI_CADENCE_QUADSPI=y
++CONFIG_SPI_DESIGNWARE=m
++CONFIG_SPI_DW_DMA=y
++CONFIG_SPI_DW_MMIO=m
++CONFIG_SPI_PL022=y
++CONFIG_SPI_ROCKCHIP=y
++CONFIG_SPI_ROCKCHIP_SFC=m
++CONFIG_SPI_SPIDEV=m
++CONFIG_SPMI=y
++CONFIG_PINCTRL_DA9062=m
++CONFIG_PINCTRL_MAX77620=y
++CONFIG_PINCTRL_RK805=m
++CONFIG_PINCTRL_SINGLE=y
++CONFIG_GPIO_ALTERA=m
++CONFIG_GPIO_DWAPB=y
++CONFIG_GPIO_MB86S7X=y
++CONFIG_GPIO_PL061=y
++CONFIG_GPIO_SYSCON=y
++CONFIG_GPIO_WCD934X=m
++CONFIG_GPIO_XGENE=y
++CONFIG_GPIO_MAX732X=y
++CONFIG_GPIO_PCA953X=y
++CONFIG_GPIO_PCA953X_IRQ=y
++CONFIG_GPIO_BD9571MWV=m
++CONFIG_GPIO_MAX77620=y
++CONFIG_GPIO_AGGREGATOR=m
++CONFIG_POWER_RESET_XGENE=y
++CONFIG_POWER_RESET_SYSCON=y
++CONFIG_POWER_RESET_SYSCON_POWEROFF=y
++CONFIG_SYSCON_REBOOT_MODE=y
++CONFIG_NVMEM_REBOOT_MODE=m
++CONFIG_BATTERY_QCOM_BATTMGR=m
++CONFIG_BATTERY_SBS=m
++CONFIG_BATTERY_BQ27XXX=y
++CONFIG_BATTERY_MAX17042=m
++CONFIG_CHARGER_MT6360=m
++CONFIG_CHARGER_BQ25890=m
++CONFIG_CHARGER_BQ25980=m
++CONFIG_CHARGER_RK817=m
++CONFIG_SENSORS_ARM_SCMI=y
++CONFIG_SENSORS_ARM_SCPI=y
++CONFIG_SENSORS_GPIO_FAN=m
++CONFIG_SENSORS_JC42=m
++CONFIG_SENSORS_LM75=m
++CONFIG_SENSORS_LM90=m
++CONFIG_SENSORS_PWM_FAN=m
++CONFIG_SENSORS_RASPBERRYPI_HWMON=m
++CONFIG_SENSORS_INA2XX=m
++CONFIG_SENSORS_INA3221=m
++CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
++CONFIG_CPU_THERMAL=y
++CONFIG_DEVFREQ_THERMAL=y
++CONFIG_THERMAL_EMULATION=y
++CONFIG_ROCKCHIP_THERMAL=m
++CONFIG_BCM2711_THERMAL=m
++CONFIG_BCM2835_THERMAL=m
++CONFIG_BRCMSTB_THERMAL=m
++CONFIG_GENERIC_ADC_THERMAL=m
++CONFIG_KHADAS_MCU_FAN_THERMAL=m
++CONFIG_WATCHDOG=y
++CONFIG_ARM_SP805_WATCHDOG=y
++CONFIG_ARM_SBSA_WATCHDOG=y
++CONFIG_DW_WATCHDOG=y
++CONFIG_ARM_SMC_WATCHDOG=y
++CONFIG_BCM2835_WDT=y
++CONFIG_BCM7038_WDT=m
++CONFIG_MFD_BD9571MWV=y
++CONFIG_MFD_AXP20X_I2C=y
++CONFIG_MFD_DA9062=m
++CONFIG_MFD_HI6421_PMIC=y
++CONFIG_MFD_MAX77620=y
++CONFIG_MFD_MT6360=y
++CONFIG_MFD_MT6397=y
++CONFIG_MFD_RK8XX_I2C=y
++CONFIG_MFD_RK8XX_SPI=y
++CONFIG_MFD_SEC_CORE=y
++CONFIG_MFD_TPS65219=y
++CONFIG_MFD_TPS6594_I2C=m
++CONFIG_MFD_WM8994=m
++CONFIG_MFD_ROHM_BD718XX=y
++CONFIG_MFD_WCD934X=m
++CONFIG_MFD_KHADAS_MCU=m
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_BD718XX=y
++CONFIG_REGULATOR_BD9571MWV=y
++CONFIG_REGULATOR_CROS_EC=y
++CONFIG_REGULATOR_DA9211=m
++CONFIG_REGULATOR_FAN53555=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_HI6421V530=y
++CONFIG_REGULATOR_MAX77620=y
++CONFIG_REGULATOR_MAX8973=y
++CONFIG_REGULATOR_MAX20411=m
++CONFIG_REGULATOR_MP8859=y
++CONFIG_REGULATOR_MT6315=m
++CONFIG_REGULATOR_MT6357=y
++CONFIG_REGULATOR_MT6358=y
++CONFIG_REGULATOR_MT6359=y
++CONFIG_REGULATOR_MT6360=y
++CONFIG_REGULATOR_MT6397=y
++CONFIG_REGULATOR_PCA9450=y
++CONFIG_REGULATOR_PF8X00=y
++CONFIG_REGULATOR_PFUZE100=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_REGULATOR_QCOM_SPMI=y
++CONFIG_REGULATOR_QCOM_USB_VBUS=m
++CONFIG_REGULATOR_RAA215300=y
++CONFIG_REGULATOR_RK808=y
++CONFIG_REGULATOR_S2MPS11=y
++CONFIG_REGULATOR_TPS65132=m
++CONFIG_REGULATOR_TPS65219=y
++CONFIG_REGULATOR_VCTRL=m
++CONFIG_RC_CORE=m
++CONFIG_RC_DECODERS=y
++CONFIG_RC_DEVICES=y
++CONFIG_IR_GPIO_CIR=m
++CONFIG_MEDIA_CEC_SUPPORT=y
++CONFIG_MEDIA_SUPPORT=m
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
++CONFIG_MEDIA_SDR_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++# CONFIG_DVB_NET is not set
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_SDR_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_CADENCE_CSI2RX=m
++CONFIG_VIDEO_HANTRO=m
++CONFIG_VIDEO_IMX219=m
++CONFIG_VIDEO_IMX412=m
++CONFIG_VIDEO_OV5640=m
++CONFIG_VIDEO_OV5645=m
++CONFIG_DRM=y
++CONFIG_DRM_I2C_NXP_TDA998X=m
++CONFIG_DRM_HDLCD=m
++CONFIG_DRM_MALI_DISPLAY=m
++CONFIG_DRM_KOMEDA=m
++CONFIG_DRM_NOUVEAU=m
++CONFIG_DRM_ROCKCHIP=m
++CONFIG_ROCKCHIP_VOP2=y
++CONFIG_ROCKCHIP_ANALOGIX_DP=y
++CONFIG_ROCKCHIP_CDN_DP=y
++CONFIG_ROCKCHIP_DW_HDMI=y
++CONFIG_ROCKCHIP_DW_MIPI_DSI=y
++CONFIG_ROCKCHIP_INNO_HDMI=y
++CONFIG_ROCKCHIP_LVDS=y
++CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
++CONFIG_DRM_PANEL_LVDS=m
++CONFIG_DRM_PANEL_ILITEK_ILI9882T=m
++CONFIG_DRM_PANEL_KHADAS_TS050=m
++CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
++CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
++CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
++CONFIG_DRM_PANEL_SITRONIX_ST7703=m
++CONFIG_DRM_PANEL_EDP=m
++CONFIG_DRM_PANEL_SIMPLE=m
++CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
++CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
++CONFIG_DRM_DISPLAY_CONNECTOR=m
++CONFIG_DRM_LONTIUM_LT8912B=m
++CONFIG_DRM_LONTIUM_LT9611=m
++CONFIG_DRM_LONTIUM_LT9611UXC=m
++CONFIG_DRM_ITE_IT66121=m
++CONFIG_DRM_NWL_MIPI_DSI=m
++CONFIG_DRM_PARADE_PS8640=m
++CONFIG_DRM_SAMSUNG_DSIM=m
++CONFIG_DRM_SII902X=m
++CONFIG_DRM_SIMPLE_BRIDGE=m
++CONFIG_DRM_THINE_THC63LVD1024=m
++CONFIG_DRM_TOSHIBA_TC358767=m
++CONFIG_DRM_TOSHIBA_TC358768=m
++CONFIG_DRM_TI_TFP410=m
++CONFIG_DRM_TI_SN65DSI83=m
++CONFIG_DRM_TI_SN65DSI86=m
++CONFIG_DRM_ANALOGIX_ANX7625=m
++CONFIG_DRM_I2C_ADV7511=m
++CONFIG_DRM_I2C_ADV7511_AUDIO=y
++CONFIG_DRM_CDNS_MHDP8546=m
++CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
++CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
++CONFIG_DRM_DW_HDMI_CEC=m
++CONFIG_DRM_V3D=m
++CONFIG_DRM_VC4=y
++CONFIG_DRM_ETNAVIV=m
++CONFIG_DRM_HISI_HIBMC=m
++CONFIG_DRM_HISI_KIRIN=m
++CONFIG_DRM_PL111=m
++CONFIG_DRM_LIMA=m
++CONFIG_DRM_PANFROST=m
++CONFIG_DRM_PANTHOR=m
++CONFIG_DRM_TIDSS=m
++CONFIG_DRM_POWERVR=m
++CONFIG_FB=y
++CONFIG_FB_EFI=y
++CONFIG_FB_MODE_HELPERS=y
++CONFIG_BACKLIGHT_PWM=m
++CONFIG_BACKLIGHT_LP855X=m
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_DYNAMIC_MINORS=y
++CONFIG_SND_ALOOP=m
++CONFIG_SND_SOC=y
++CONFIG_SND_BCM2835_SOC_I2S=m
++CONFIG_SND_SOC_FSL_ASRC=m
++CONFIG_SND_SOC_FSL_SAI=m
++CONFIG_SND_SOC_FSL_AUDMIX=m
++CONFIG_SND_SOC_FSL_SSI=m
++CONFIG_SND_SOC_FSL_SPDIF=m
++CONFIG_SND_SOC_FSL_ESAI=m
++CONFIG_SND_SOC_FSL_MICFIL=m
++CONFIG_SND_SOC_FSL_EASRC=m
++CONFIG_SND_SOC_IMX_AUDMUX=m
++CONFIG_SND_SOC_ROCKCHIP=m
++CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
++CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
++CONFIG_SND_SOC_ROCKCHIP_RT5645=m
++CONFIG_SND_SOC_RK3399_GRU_SOUND=m
++CONFIG_SND_SOC_SOF_TOPLEVEL=y
++CONFIG_SND_SOC_SOF_OF=y
++CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=y
++CONFIG_SND_SOC_ADAU7002=m
++CONFIG_SND_SOC_AK4613=m
++CONFIG_SND_SOC_BT_SCO=m
++CONFIG_SND_SOC_CROS_EC_CODEC=m
++CONFIG_SND_SOC_DA7213=m
++CONFIG_SND_SOC_ES7134=m
++CONFIG_SND_SOC_ES7241=m
++CONFIG_SND_SOC_ES8316=m
++CONFIG_SND_SOC_GTM601=m
++CONFIG_SND_SOC_MAX98927=m
++CONFIG_SND_SOC_MAX98390=m
++CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
++CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
++CONFIG_SND_SOC_PCM3168A_I2C=m
++CONFIG_SND_SOC_RK3308=m
++CONFIG_SND_SOC_RK817=m
++CONFIG_SND_SOC_RT5640=m
++CONFIG_SND_SOC_RT5659=m
++CONFIG_SND_SOC_SGTL5000=m
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
++CONFIG_SND_SOC_SIMPLE_MUX=m
++CONFIG_SND_SOC_SPDIF=m
++CONFIG_SND_SOC_TAS2552=m
++CONFIG_SND_SOC_TAS571X=m
++CONFIG_SND_SOC_TLV320AIC31XX=m
++CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
++CONFIG_SND_SOC_TLV320AIC3X_I2C=m
++CONFIG_SND_SOC_TS3A227E=m
++CONFIG_SND_SOC_WCD9335=m
++CONFIG_SND_SOC_WCD934X=m
++CONFIG_SND_SOC_WCD938X_SDW=m
++CONFIG_SND_SOC_WCD939X_SDW=m
++CONFIG_SND_SOC_WM8524=m
++CONFIG_SND_SOC_WM8904=m
++CONFIG_SND_SOC_WM8960=m
++CONFIG_SND_SOC_WM8962=m
++CONFIG_SND_SOC_WM8978=m
++CONFIG_SND_SOC_WSA881X=m
++CONFIG_SND_SOC_WSA883X=m
++CONFIG_SND_SOC_WSA884X=m
++CONFIG_SND_SOC_MT6358=m
++CONFIG_SND_SOC_NAU8822=m
++CONFIG_SND_SOC_LPASS_WSA_MACRO=m
++CONFIG_SND_SOC_LPASS_VA_MACRO=m
++CONFIG_SND_SOC_LPASS_RX_MACRO=m
++CONFIG_SND_SOC_LPASS_TX_MACRO=m
++CONFIG_SND_SIMPLE_CARD=m
++CONFIG_SND_AUDIO_GRAPH_CARD=m
++CONFIG_SND_AUDIO_GRAPH_CARD2=m
++CONFIG_HID_MULTITOUCH=m
++CONFIG_I2C_HID_ACPI=m
++CONFIG_I2C_HID_OF=m
++CONFIG_USB_CONN_GPIO=y
++CONFIG_USB=y
++CONFIG_USB_OTG=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PCI_RENESAS=m
++CONFIG_USB_BRCMSTB=m
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_HCD_PLATFORM=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_HCD_PLATFORM=y
++CONFIG_USB_ACM=m
++CONFIG_USB_STORAGE=y
++CONFIG_USB_CDNS_SUPPORT=m
++CONFIG_USB_CDNS3=m
++CONFIG_USB_CDNS3_GADGET=y
++CONFIG_USB_CDNS3_HOST=y
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_DWC3=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_CHIPIDEA=y
++CONFIG_USB_CHIPIDEA_UDC=y
++CONFIG_USB_CHIPIDEA_HOST=y
++CONFIG_USB_ISP1760=y
++CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_CP210X=m
++CONFIG_USB_SERIAL_FTDI_SIO=m
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_USB_HSIC_USB3503=y
++CONFIG_USB_ONBOARD_DEV=m
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_ULPI=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_CONFIGFS=m
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_MASS_STORAGE=m
++CONFIG_TYPEC=m
++CONFIG_TYPEC_TCPM=m
++CONFIG_TYPEC_TCPCI=m
++CONFIG_TYPEC_FUSB302=m
++CONFIG_TYPEC_UCSI=m
++CONFIG_UCSI_CCG=m
++CONFIG_UCSI_PMIC_GLINK=m
++CONFIG_TYPEC_TPS6598X=m
++CONFIG_TYPEC_HD3SS3220=m
++CONFIG_TYPEC_MUX_FSA4480=m
++CONFIG_TYPEC_MUX_GPIO_SBU=m
++CONFIG_TYPEC_MUX_NB7VPQ904M=m
++CONFIG_TYPEC_MUX_WCD939X_USBSS=m
++CONFIG_TYPEC_DP_ALTMODE=m
++CONFIG_MMC=y
++CONFIG_MMC_BLOCK_MINORS=32
++CONFIG_MMC_ARMMMCI=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_ACPI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_OF_ARASAN=y
++CONFIG_MMC_SDHCI_OF_DWCMSHC=y
++CONFIG_MMC_SDHCI_CADENCE=y
++CONFIG_MMC_SDHCI_F_SDH30=y
++CONFIG_MMC_SPI=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_EXYNOS=y
++CONFIG_MMC_DW_HI3798CV200=y
++CONFIG_MMC_DW_K3=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_MMC_BCM2835=y
++CONFIG_MMC_MTK=y
++CONFIG_MMC_SDHCI_XENON=y
++CONFIG_SCSI_UFSHCD=y
++CONFIG_SCSI_UFS_BSG=y
++CONFIG_SCSI_UFSHCD_PLATFORM=y
++CONFIG_SCSI_UFS_CDNS_PLATFORM=m
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS_MULTICOLOR=m
++CONFIG_LEDS_LM3692X=m
++CONFIG_LEDS_PCA9532=m
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_PWM=y
++CONFIG_LEDS_SYSCON=y
++CONFIG_LEDS_QCOM_LPG=m
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_DISK=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_EDAC=y
++CONFIG_EDAC_GHES=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_DRV_DS1307=m
++CONFIG_RTC_DRV_HYM8563=m
++CONFIG_RTC_DRV_MAX77686=y
++CONFIG_RTC_DRV_RK808=m
++CONFIG_RTC_DRV_ISL1208=m
++CONFIG_RTC_DRV_PCF85063=m
++CONFIG_RTC_DRV_PCF85363=m
++CONFIG_RTC_DRV_PCF8563=m
++CONFIG_RTC_DRV_M41T80=m
++CONFIG_RTC_DRV_BQ32K=m
++CONFIG_RTC_DRV_RX8581=m
++CONFIG_RTC_DRV_RV3028=m
++CONFIG_RTC_DRV_RV8803=m
++CONFIG_RTC_DRV_S5M=y
++CONFIG_RTC_DRV_DS3232=y
++CONFIG_RTC_DRV_PCF2127=m
++CONFIG_RTC_DRV_DA9063=m
++CONFIG_RTC_DRV_EFI=y
++CONFIG_RTC_DRV_CROS_EC=y
++CONFIG_RTC_DRV_PL031=y
++CONFIG_RTC_DRV_MT6397=m
++CONFIG_DMADEVICES=y
++CONFIG_DMA_BCM2835=y
++CONFIG_FSL_EDMA=y
++CONFIG_MV_XOR_V2=y
++CONFIG_PL330_DMA=y
++CONFIG_QCOM_HIDMA_MGMT=y
++CONFIG_QCOM_HIDMA=y
++CONFIG_VFIO=y
++CONFIG_VFIO_PCI=y
++CONFIG_VIRTIO_PCI=y
++CONFIG_VIRTIO_BALLOON=y
++CONFIG_VIRTIO_MMIO=y
++CONFIG_XEN_GNTDEV=y
++CONFIG_XEN_GRANT_DEV_ALLOC=y
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_MAX96712=m
++CONFIG_SND_BCM2835=y
++CONFIG_CHROME_PLATFORMS=y
++CONFIG_CROS_EC=y
++CONFIG_CROS_EC_I2C=y
++CONFIG_CROS_EC_RPMSG=m
++CONFIG_CROS_EC_SPI=y
++CONFIG_CROS_KBD_LED_BACKLIGHT=m
++CONFIG_CROS_EC_CHARDEV=m
++CONFIG_CLK_VEXPRESS_OSC=y
++CONFIG_COMMON_CLK_RK808=y
++CONFIG_COMMON_CLK_SCMI=y
++CONFIG_COMMON_CLK_SCPI=y
++CONFIG_COMMON_CLK_CS2000_CP=y
++CONFIG_COMMON_CLK_S2MPS11=y
++CONFIG_COMMON_CLK_XGENE=y
++CONFIG_COMMON_CLK_PWM=y
++CONFIG_COMMON_CLK_RS9_PCIE=y
++CONFIG_COMMON_CLK_VC3=y
++CONFIG_COMMON_CLK_VC5=y
++CONFIG_COMMON_CLK_BD718XX=m
++CONFIG_CLK_RASPBERRYPI=y
++CONFIG_HWSPINLOCK=y
++CONFIG_ARM_MHU=y
++CONFIG_PLATFORM_MHU=y
++CONFIG_BCM2835_MBOX=y
++CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
++CONFIG_IOMMU_IO_PGTABLE_DART=y
++CONFIG_ROCKCHIP_IOMMU=y
++CONFIG_ARM_SMMU=y
++CONFIG_ARM_SMMU_V3=y
++CONFIG_REMOTEPROC=y
++CONFIG_RPMSG_CHAR=m
++CONFIG_RPMSG_CTRL=m
++CONFIG_RPMSG_QCOM_GLINK_RPM=y
++CONFIG_RPMSG_VIRTIO=y
++CONFIG_SOUNDWIRE=m
++CONFIG_SOUNDWIRE_QCOM=m
++CONFIG_FSL_RCPM=y
++CONFIG_QCOM_PMIC_GLINK=m
++CONFIG_QCOM_PBS=m
++CONFIG_ROCKCHIP_IODOMAIN=y
++CONFIG_SOC_TI=y
++CONFIG_RASPBERRYPI_POWER=y
++CONFIG_ROCKCHIP_PM_DOMAINS=y
++CONFIG_DEVFREQ_GOV_USERSPACE=y
++CONFIG_DEVFREQ_GOV_PASSIVE=m
++CONFIG_EXTCON_PTN5150=m
++CONFIG_EXTCON_USB_GPIO=y
++CONFIG_EXTCON_USBC_CROS_EC=y
++CONFIG_MEMORY=y
++CONFIG_IIO=y
++CONFIG_MAX9611=m
++CONFIG_QCOM_SPMI_VADC=m
++CONFIG_QCOM_SPMI_ADC5=m
++CONFIG_ROCKCHIP_SARADC=m
++CONFIG_TI_ADS1015=m
++CONFIG_IIO_CROS_EC_SENSORS_CORE=m
++CONFIG_IIO_CROS_EC_SENSORS=m
++CONFIG_IIO_ST_LSM6DSX=m
++CONFIG_IIO_CROS_EC_LIGHT_PROX=m
++CONFIG_SENSORS_ISL29018=m
++CONFIG_VCNL4000=m
++CONFIG_IIO_ST_MAGN_3AXIS=m
++CONFIG_IIO_CROS_EC_BARO=m
++CONFIG_MPL3115=m
++CONFIG_PWM=y
++CONFIG_PWM_BCM2835=y
++CONFIG_PWM_BRCMSTB=m
++CONFIG_PWM_CROS_EC=m
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_RESET_GPIO=m
++CONFIG_PHY_CAN_TRANSCEIVER=m
++CONFIG_PHY_CADENCE_TORRENT=m
++CONFIG_PHY_CADENCE_DPHY_RX=m
++CONFIG_PHY_CADENCE_SIERRA=m
++CONFIG_PHY_CADENCE_SALVO=m
++CONFIG_PHY_QCOM_USB_HS=m
++CONFIG_PHY_ROCKCHIP_EMMC=y
++CONFIG_PHY_ROCKCHIP_INNO_HDMI=m
++CONFIG_PHY_ROCKCHIP_INNO_USB2=y
++CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m
++CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
++CONFIG_PHY_ROCKCHIP_PCIE=m
++CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=m
++CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
++CONFIG_PHY_ROCKCHIP_TYPEC=y
++CONFIG_PHY_ROCKCHIP_USBDP=m
++CONFIG_PHY_SAMSUNG_USB2=y
++CONFIG_ARM_CCI_PMU=m
++CONFIG_ARM_CCN=m
++CONFIG_ARM_CMN=m
++CONFIG_ARM_SMMU_V3_PMU=m
++CONFIG_ARM_DSU_PMU=m
++CONFIG_ARM_SPE_PMU=m
++CONFIG_ARM_DMC620_PMU=m
++CONFIG_HISI_PMU=y
++CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m
++CONFIG_NVMEM_LAYOUT_SL28_VPD=m
++CONFIG_NVMEM_RMEM=m
++CONFIG_NVMEM_ROCKCHIP_EFUSE=y
++CONFIG_NVMEM_ROCKCHIP_OTP=y
++CONFIG_NVMEM_SPMI_SDAM=m
++CONFIG_FPGA=y
++CONFIG_FPGA_MGR_ALTERA_CVP=m
++CONFIG_FPGA_BRIDGE=m
++CONFIG_ALTERA_FREEZE_BRIDGE=m
++CONFIG_FPGA_REGION=m
++CONFIG_OF_FPGA_REGION=m
++CONFIG_TEE=y
++CONFIG_OPTEE=y
++CONFIG_MUX_GPIO=m
++CONFIG_MUX_MMIO=y
++CONFIG_SLIM_QCOM_CTRL=m
++CONFIG_INTERCONNECT=y
++CONFIG_COUNTER=m
++CONFIG_HTE=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++CONFIG_BTRFS_FS=m
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_FANOTIFY=y
++CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
++CONFIG_QUOTA=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=m
++CONFIG_CUSE=m
++CONFIG_OVERLAY_FS=m
++CONFIG_VFAT_FS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_HUGETLBFS=y
++CONFIG_EFIVAR_FS=y
++CONFIG_UBIFS_FS=m
++CONFIG_SQUASHFS=y
++CONFIG_PSTORE_RAM=m
++CONFIG_NFS_FS=y
++CONFIG_NFS_V4=y
++CONFIG_NFS_V4_1=y
++CONFIG_NFS_V4_2=y
++CONFIG_ROOT_NFS=y
++CONFIG_9P_FS=y
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_SECURITY=y
++CONFIG_CRYPTO_USER=y
++CONFIG_CRYPTO_TEST=m
++CONFIG_CRYPTO_DES=m
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_RNG=m
++CONFIG_CRYPTO_CHACHA20_NEON=m
++CONFIG_CRYPTO_GHASH_ARM64_CE=y
++CONFIG_CRYPTO_SHA1_ARM64_CE=y
++CONFIG_CRYPTO_SHA2_ARM64_CE=y
++CONFIG_CRYPTO_SHA512_ARM64_CE=m
++CONFIG_CRYPTO_SHA3_ARM64=m
++CONFIG_CRYPTO_SM3_ARM64_CE=m
++CONFIG_CRYPTO_AES_ARM64_BS=m
++CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
++CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
++CONFIG_CRYPTO_DEV_CCREE=m
++CONFIG_CRYPTO_DEV_HISI_SEC2=m
++CONFIG_CRYPTO_DEV_HISI_ZIP=m
++CONFIG_CRYPTO_DEV_HISI_HPRE=m
++CONFIG_CRYPTO_DEV_HISI_TRNG=m
++CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
++CONFIG_INDIRECT_PIO=y
++CONFIG_CRC_CCITT=m
++CONFIG_DMA_RESTRICTED_POOL=y
++CONFIG_CMA_SIZE_MBYTES=32
++CONFIG_PRINTK_TIME=y
++CONFIG_DEBUG_KERNEL=y
++CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
++CONFIG_DEBUG_INFO_REDUCED=y
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_FTRACE is not set
++CONFIG_CORESIGHT=m
++CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m
++CONFIG_CORESIGHT_CATU=m
++CONFIG_CORESIGHT_SINK_TPIU=m
++CONFIG_CORESIGHT_SINK_ETBV10=m
++CONFIG_CORESIGHT_STM=m
++CONFIG_CORESIGHT_CPU_DEBUG=m
++CONFIG_CORESIGHT_CTI=m
++CONFIG_MEMTEST=y
diff --git a/cd6e4f6d8babdb5e65525c6dd2d1e373558b38ab.patch b/cd6e4f6d8babdb5e65525c6dd2d1e373558b38ab.patch
new file mode 100644
index 0000000..05867c1
--- /dev/null
+++ b/cd6e4f6d8babdb5e65525c6dd2d1e373558b38ab.patch
@@ -0,0 +1,179 @@
+From cd6e4f6d8babdb5e65525c6dd2d1e373558b38ab Mon Sep 17 00:00:00 2001
+From: Andy Yan <andyshrk@gmail.com>
+Date: Sat, 17 Dec 2022 19:20:47 +0800
+Subject: [PATCH] arm64: rockchip: defconfig: update for Linux 6.1 and enable
+ pcie for rk3568
+
+Signed-off-by: Andy Yan <andyshrk@gmail.com>
+---
+ arch/arm64/configs/rockchip_defconfig | 30 ++++++++++++++++++++-------
+ 1 file changed, 23 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig
+index 739fb1eef862cc..46f97961dee1db 100644
+--- a/arch/arm64/configs/rockchip_defconfig
++++ b/arch/arm64/configs/rockchip_defconfig
+@@ -166,8 +166,8 @@ CONFIG_PCIE_ALTERA=y
+ CONFIG_PCIE_ALTERA_MSI=y
+ CONFIG_PCI_HOST_THUNDER_PEM=y
+ CONFIG_PCI_HOST_THUNDER_ECAM=y
+-CONFIG_PCIE_ROCKCHIP_HOST=m
+ CONFIG_PCI_HISI=y
++CONFIG_PCIE_ROCKCHIP_DW_HOST=y
+ CONFIG_PCIE_KIRIN=y
+ CONFIG_PCI_MESON=m
+ CONFIG_PCI_ENDPOINT=y
+@@ -201,7 +201,6 @@ CONFIG_MTD_NAND_BRCMNAND_BCMBCA=m
+ CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=m
+ CONFIG_MTD_NAND_BRCMNAND_IPROC=m
+ CONFIG_MTD_SPI_NOR=y
+-CONFIG_OF_OVERLAY=y
+ CONFIG_BLK_DEV_LOOP=y
+ CONFIG_BLK_DEV_NBD=m
+ CONFIG_VIRTIO_BLK=y
+@@ -266,12 +265,12 @@ CONFIG_RMNET=m
+ CONFIG_R8169=m
+ CONFIG_SMC91X=y
+ CONFIG_SMSC911X=y
+-CONFIG_STMMAC_ETH=y
++CONFIG_STMMAC_ETH=m
+ CONFIG_AQUANTIA_PHY=y
+ CONFIG_BROADCOM_PHY=m
+ CONFIG_BCM54140_PHY=m
+ CONFIG_MARVELL_PHY=m
+-CONFIG_MARVELL_10G_PHY=m
++CONFIG_MARVELL_10G_PHY=y
+ CONFIG_MICREL_PHY=y
+ CONFIG_MICROSEMI_PHY=y
+ CONFIG_AT803X_PHY=y
+@@ -297,6 +296,7 @@ CONFIG_USB_NET_PLUSB=m
+ CONFIG_USB_NET_MCS7830=m
+ CONFIG_ATH10K=m
+ CONFIG_ATH10K_PCI=m
++CONFIG_ATH10K_SDIO=m
+ CONFIG_WCN36XX=m
+ CONFIG_ATH11K=m
+ CONFIG_ATH11K_AHB=m
+@@ -314,6 +314,7 @@ CONFIG_KEYBOARD_CROS_EC=y
+ CONFIG_INPUT_TOUCHSCREEN=y
+ CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+ CONFIG_TOUCHSCREEN_GOODIX=m
++CONFIG_TOUCHSCREEN_ELAN=m
+ CONFIG_TOUCHSCREEN_EDT_FT5X06=m
+ CONFIG_INPUT_MISC=y
+ CONFIG_INPUT_PWM_BEEPER=m
+@@ -341,6 +342,10 @@ CONFIG_IPMI_HANDLER=m
+ CONFIG_IPMI_DEVICE_INTERFACE=m
+ CONFIG_IPMI_SI=m
+ CONFIG_TCG_TPM=y
++CONFIG_TCG_TIS=m
++CONFIG_TCG_TIS_SPI=m
++CONFIG_TCG_TIS_SPI_CR50=y
++CONFIG_TCG_TIS_I2C_CR50=m
+ CONFIG_TCG_TIS_I2C_INFINEON=y
+ CONFIG_I2C_CHARDEV=y
+ CONFIG_I2C_MUX=y
+@@ -398,6 +403,7 @@ CONFIG_CPU_THERMAL=y
+ CONFIG_DEVFREQ_THERMAL=y
+ CONFIG_THERMAL_EMULATION=y
+ CONFIG_ROCKCHIP_THERMAL=m
++CONFIG_GENERIC_ADC_THERMAL=m
+ CONFIG_WATCHDOG=y
+ CONFIG_ARM_SP805_WATCHDOG=y
+ CONFIG_ARM_SBSA_WATCHDOG=y
+@@ -472,7 +478,7 @@ CONFIG_ROCKCHIP_INNO_HDMI=y
+ CONFIG_ROCKCHIP_LVDS=y
+ CONFIG_DRM_RCAR_DW_HDMI=m
+ CONFIG_DRM_RCAR_USE_LVDS=y
+-CONFIG_DRM_RCAR_MIPI_DSI=m
++CONFIG_DRM_RCAR_USE_MIPI_DSI=y
+ CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
+ CONFIG_DRM_PANEL_LVDS=m
+ CONFIG_DRM_PANEL_SIMPLE=m
+@@ -490,7 +496,9 @@ CONFIG_DRM_PARADE_PS8640=m
+ CONFIG_DRM_SII902X=m
+ CONFIG_DRM_SIMPLE_BRIDGE=m
+ CONFIG_DRM_THINE_THC63LVD1024=m
++CONFIG_DRM_TI_TFP410=m
+ CONFIG_DRM_TI_SN65DSI86=m
++CONFIG_DRM_ANALOGIX_ANX7625=m
+ CONFIG_DRM_I2C_ADV7511=m
+ CONFIG_DRM_I2C_ADV7511_AUDIO=y
+ CONFIG_DRM_CDNS_MHDP8546=m
+@@ -517,6 +525,7 @@ CONFIG_LOGO=y
+ CONFIG_SOUND=y
+ CONFIG_SND=y
+ CONFIG_SND_DYNAMIC_MINORS=y
++CONFIG_SND_ALOOP=m
+ CONFIG_SND_SOC=y
+ CONFIG_SND_SOC_FSL_ASRC=m
+ CONFIG_SND_SOC_FSL_SAI=m
+@@ -533,6 +542,7 @@ CONFIG_SND_SOC_ROCKCHIP_RT5645=m
+ CONFIG_SND_SOC_RK3399_GRU_SOUND=m
+ CONFIG_SND_SOC_ADAU7002=m
+ CONFIG_SND_SOC_AK4613=m
++CONFIG_SND_SOC_BT_SCO=m
+ CONFIG_SND_SOC_CROS_EC_CODEC=m
+ CONFIG_SND_SOC_ES7134=m
+ CONFIG_SND_SOC_ES7241=m
+@@ -541,14 +551,17 @@ CONFIG_SND_SOC_MAX98927=m
+ CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
+ CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
+ CONFIG_SND_SOC_PCM3168A_I2C=m
++CONFIG_SND_SOC_RT5640=m
+ CONFIG_SND_SOC_RT5659=m
+ CONFIG_SND_SOC_SGTL5000=m
+ CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+ CONFIG_SND_SOC_SIMPLE_MUX=m
+ CONFIG_SND_SOC_SPDIF=m
++CONFIG_SND_SOC_TAS2552=m
+ CONFIG_SND_SOC_TAS571X=m
+ CONFIG_SND_SOC_TLV320AIC31XX=m
+ CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
++CONFIG_SND_SOC_TS3A227E=m
+ CONFIG_SND_SOC_WCD9335=m
+ CONFIG_SND_SOC_WCD934X=m
+ CONFIG_SND_SOC_WCD938X_SDW=m
+@@ -558,6 +571,7 @@ CONFIG_SND_SOC_WM8960=m
+ CONFIG_SND_SOC_WM8962=m
+ CONFIG_SND_SOC_WM8978=m
+ CONFIG_SND_SOC_WSA881X=m
++CONFIG_SND_SOC_MT6358=m
+ CONFIG_SND_SOC_NAU8822=m
+ CONFIG_SND_SOC_LPASS_WSA_MACRO=m
+ CONFIG_SND_SOC_LPASS_VA_MACRO=m
+@@ -704,6 +718,7 @@ CONFIG_COMMON_CLK_CS2000_CP=y
+ CONFIG_COMMON_CLK_S2MPS11=y
+ CONFIG_COMMON_CLK_XGENE=y
+ CONFIG_COMMON_CLK_PWM=y
++CONFIG_COMMON_CLK_RS9_PCIE=y
+ CONFIG_COMMON_CLK_VC5=y
+ CONFIG_COMMON_CLK_BD718XX=m
+ CONFIG_HWSPINLOCK=y
+@@ -726,6 +741,7 @@ CONFIG_ROCKCHIP_IODOMAIN=y
+ CONFIG_ROCKCHIP_PM_DOMAINS=y
+ CONFIG_SOC_TI=y
+ CONFIG_DEVFREQ_GOV_USERSPACE=m
++CONFIG_DEVFREQ_GOV_PASSIVE=m
+ CONFIG_EXTCON_PTN5150=m
+ CONFIG_EXTCON_USB_GPIO=y
+ CONFIG_EXTCON_USBC_CROS_EC=y
+@@ -757,9 +773,8 @@ CONFIG_PHY_ROCKCHIP_INNO_HDMI=m
+ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+ CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m
+ CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+-CONFIG_PHY_ROCKCHIP_PCIE=m
++CONFIG_PHY_ROCKCHIP_PCIE=y
+ CONFIG_PHY_ROCKCHIP_TYPEC=y
+-CONFIG_PHY_ROCKCHIP_USB=y
+ CONFIG_PHY_SAMSUNG_USB2=y
+ CONFIG_ARM_CCI_PMU=m
+ CONFIG_ARM_CCN=m
+@@ -782,6 +797,7 @@ CONFIG_OPTEE=y
+ CONFIG_MUX_MMIO=y
+ CONFIG_SLIM_QCOM_CTRL=m
+ CONFIG_INTERCONNECT=y
++CONFIG_HTE=y
+ CONFIG_EXT2_FS=y
+ CONFIG_EXT3_FS=y
+ CONFIG_EXT4_FS_POSIX_ACL=y
diff --git a/cef2dc6b338e1349b2e9feda9bf41e88510aaf5a.patch b/cef2dc6b338e1349b2e9feda9bf41e88510aaf5a.patch
new file mode 100644
index 0000000..2d28759
--- /dev/null
+++ b/cef2dc6b338e1349b2e9feda9bf41e88510aaf5a.patch
@@ -0,0 +1,23 @@
+From cef2dc6b338e1349b2e9feda9bf41e88510aaf5a Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@collabora.com>
+Date: Mon, 7 Aug 2023 17:36:50 +0200
+Subject: [PATCH] [DONT UPSTREAM]arm64: dts: rockchip: rk3588-evb1: Force MAC
+ address
+
+Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+index d6e464cdc53612..49e13ebf529e1f 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+@@ -304,6 +304,7 @@
+ 	rx_delay = <0x00>;
+ 	tx_delay = <0x43>;
+ 	status = "okay";
++	mac-address = [ fe 46 f2 84 84 fe ];
+ };
+ 
+ &gpu {
diff --git a/cgroups.fragment b/cgroups.fragment
new file mode 100644
index 0000000..c87e799
--- /dev/null
+++ b/cgroups.fragment
@@ -0,0 +1,19 @@
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_FAVOR_DYNMODS is not set
+CONFIG_MEMCG=y
+CONFIG_MEMCG_V1=y
+CONFIG_MEMCG_KMEM=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_RDMA=y
+CONFIG_CGROUP_DMEM=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CGROUP_WRITEBACK=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_MISC=y
+# CONFIG_CGROUP_DEBUG is not set
diff --git a/common-desktop.config b/common-desktop.config
deleted file mode 100644
index 185ad4c..0000000
--- a/common-desktop.config
+++ /dev/null
@@ -1,34 +0,0 @@
-# CONFIG_SCHED_MUQSS is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_PREEMPT_RCU=y
-# CONFIG_RCU_EXPERT is not set
-CONFIG_SRCU=y
-# CONFIG_TASKS_RCU is not set
-CONFIG_RCU_STALL_COMMON=y
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_RCU_EXPEDITE_BOOT is not set
-
-#
-# IO Schedulers
-#
-CONFIG_DEFAULT_IOSCHED="bfq"
-CONFIG_PREEMPT_NOTIFIERS=y
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-
-#
-# Memory management
-CONFIG_UKSM=y
-#
-
-#
-# Processor type and features
-#
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-# CONFIG_PREEMPT is not set
-CONFIG_PREEMPT_COUNT=y
-CONFIG_HZ_1000=y
-CONFIG_HZ=1000
diff --git a/common-server.config b/common-server.config
deleted file mode 100644
index 7f739c0..0000000
--- a/common-server.config
+++ /dev/null
@@ -1,36 +0,0 @@
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_RCU_EXPERT is not set
-CONFIG_SRCU=y
-# CONFIG_TASKS_RCU is not set
-CONFIG_RCU_STALL_COMMON=y
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_RCU_EXPEDITE_BOOT is not set
-
-#
-# IO Schedulers
-#
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_PREEMPT_NOTIFIERS=y
-# CONFIG_UNINLINE_SPIN_UNLOCK is not set
-CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
-CONFIG_INLINE_READ_UNLOCK=y
-CONFIG_INLINE_READ_UNLOCK_IRQ=y
-CONFIG_INLINE_WRITE_UNLOCK=y
-CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
-
-
-#
-# Processor type and features
-#
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-# CONFIG_PREEMPT_COUNT is not set
-CONFIG_SLAB=y
-CONFIG_HZ_300=y
-CONFIG_HZ=300
-# CONFIG_HZ_250 is not set
-# CONFIG_HZ_100 is not set
diff --git a/common.config b/common.config
deleted file mode 100644
index 77c2c14..0000000
--- a/common.config
+++ /dev/null
@@ -1,7059 +0,0 @@
-# CONFIG_KERNEL_GZIP is not set
-CONFIG_KERNEL_ZSTD=y
-CONFIG_DEFAULT_HOSTNAME="omv"
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3 is not set
-# CONFIG_USELIB is not set
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_IRQ_SIM=y
-CONFIG_GENERIC_IRQ_DEBUGFS=y
-CONFIG_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_SCHED_AVG_IRQ=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_TASKS_RCU=y
-CONFIG_BUILD_BIN2C=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_PAGE_COUNTER=y
-CONFIG_MEMCG=y
-CONFIG_MEMCG_SWAP=y
-CONFIG_MEMCG_SWAP_ENABLED=y
-CONFIG_MEMCG_KMEM=y
-CONFIG_BLK_CGROUP=y
-# CONFIG_DEBUG_BLK_CGROUP is not set
-CONFIG_CGROUP_WRITEBACK=y
-CONFIG_CFS_BANDWIDTH=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_CGROUP_PIDS=y
-CONFIG_CGROUP_RDMA=y
-CONFIG_CGROUP_HUGETLB=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CGROUP_PERF=y
-CONFIG_CGROUP_BPF=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_HAVE_GCC_PLUGINS=y
-CONFIG_GCC_PLUGINS=y
-CONFIG_SOCK_CGROUP_DATA=y
-CONFIG_USER_NS=y
-CONFIG_CHECKPOINT_RESTORE=y
-CONFIG_SCHED_AUTOGROUP=y
-# CONFIG_EXPERT is not set
-# CONFIG_SYSFS_SYSCALL is not set
-# CONFIG_SYSFS_DEPRECATED is not set
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_BPF_SYSCALL=y
-CONFIG_BPF_JIT_ALWAYS_ON=y
-# CONFIG_DEBUG_RSEQ is not set
-CONFIG_EMBEDDED=y
-CONFIG_PC104=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_SLUB_MEMCG_SYSFS_ON is not set
-# CONFIG_SLOB is not set
-CONFIG_SLAB_FREELIST_RANDOM=y
-CONFIG_SLAB_FREELIST_HARDENED=y
-CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
-CONFIG_DYNAMIC_PHYSICAL_MASK=y
-CONFIG_HYPERVISOR_GUEST=y
-CONFIG_PARAVIRT=y
-# CONFIG_PARAVIRT_DEBUG is not set
-# CONFIG_PARAVIRT_SPINLOCKS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_SPARSEMEM_ALLOC_MEM_MAP_TOGETHER=y
-CONFIG_XEN=y
-CONFIG_XEN_PV=y
-CONFIG_XEN_PV_SMP=y
-CONFIG_XEN_DOM0=y
-CONFIG_XEN_PVHVM=y
-CONFIG_XEN_PVHVM_SMP=y
-CONFIG_XEN_512GB=y
-CONFIG_XEN_SAVE_RESTORE=y
-CONFIG_XEN_DEBUG_FS=y
-CONFIG_XEN_PVH=y
-CONFIG_KVM_GUEST=y
-# CONFIG_KVM_DEBUG_FS is not set
-# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
-CONFIG_PARAVIRT_CLOCK=y
-CONFIG_JAILHOUSE_GUEST=y
-CONFIG_PROCESSOR_SELECT=y
-CONFIG_GART_IOMMU=y
-CONFIG_NR_CPUS=128
-CONFIG_PERF_EVENTS_INTEL_RAPL=m
-CONFIG_PERF_EVENTS_INTEL_CSTATE=m
-CONFIG_PERF_EVENTS_AMD_POWER=m
-CONFIG_I8K=m
-CONFIG_ARCH_USE_MEMREMAP_PROT=y
-CONFIG_ARCH_MEMORY_PROBE=y
-CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
-CONFIG_MTRR_SANITIZER=y
-CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0
-CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
-CONFIG_EFI_STUB=y
-# CONFIG_EFI_MIXED is not set
-CONFIG_KEXEC_JUMP=y
-CONFIG_PHYSICAL_START=0x200000
-CONFIG_PHYSICAL_ALIGN=0x1000000
-CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa
-CONFIG_LEGACY_VSYSCALL_NONE=y
-# CONFIG_MODIFY_LDT_SYSCALL is not set
-CONFIG_LIVEPATCH=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-CONFIG_ARCH_ENABLE_THP_MIGRATION=y
-# CONFIG_SUSPEND_SKIP_SYNC is not set
-CONFIG_PM_AUTOSLEEP=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_ACPI_AC=m
-CONFIG_ACPI_BATTERY=m
-CONFIG_ACPI_BUTTON=m
-CONFIG_ACPI_VIDEO=m
-CONFIG_ACPI_FAN=m
-CONFIG_ACPI_TAD=m
-CONFIG_ACPI_IPMI=m
-CONFIG_ACPI_PROCESSOR_AGGREGATOR=m
-CONFIG_ACPI_THERMAL=m
-CONFIG_ACPI_CUSTOM_DSDT_FILE=""
-CONFIG_ACPI_SBS=m
-CONFIG_ACPI_HED=y
-CONFIG_ACPI_BGRT=y
-# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
-CONFIG_ACPI_APEI=y
-CONFIG_ACPI_APEI_GHES=y
-CONFIG_ACPI_APEI_PCIEAER=y
-CONFIG_ACPI_APEI_MEMORY_FAILURE=y
-CONFIG_ACPI_APEI_EINJ=m
-# CONFIG_ACPI_APEI_ERST_DEBUG is not set
-CONFIG_ACPI_PCI_SLOT=y
-CONFIG_ACPI_HOTPLUG_MEMORY=y
-CONFIG_ACPI_CUSTOM_METHOD=m
-CONFIG_ACPI_NFIT=m
-CONFIG_ACPI_HMAT=m
-CONFIG_DPTF_POWER=m
-CONFIG_ACPI_WATCHDOG=y
-CONFIG_ACPI_EXTLOG=m
-CONFIG_PMIC_OPREGION=y
-CONFIG_CRC_PMIC_OPREGION=y
-CONFIG_XPOWER_PMIC_OPREGION=y
-CONFIG_CHT_WC_PMIC_OPREGION=y
-CONFIG_CHT_DC_TI_PMIC_OPREGION=y
-CONFIG_ACPI_CONFIGFS=m
-CONFIG_TPS68470_PMIC_OPREGION=y
-CONFIG_SFI=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_INTEL_IDLE=y
-CONFIG_INTEL_PCH_THERMAL=m
-CONFIG_INTEL_IDMA64=m
-CONFIG_INTEL_HID_EVENT=m
-CONFIG_PCI_XEN=y
-# CONFIG_PCI_CNB20LE_QUIRK is not set
-CONFIG_HOTPLUG_PCI_PCIE=y
-CONFIG_HOTPLUG_PCI_SHPC=y
-CONFIG_PCIE_ECRC=y
-CONFIG_PCIEASPM_DEFAULT=y
-CONFIG_PCIEASPM_DEBUG=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-CONFIG_PCIE_DPC=y
-CONFIG_PCIE_PTM=y
-# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
-CONFIG_PCI_STUB=m
-# CONFIG_PCI_PF_STUB is not set
-CONFIG_XEN_PCIDEV_FRONTEND=m
-CONFIG_PCI_IOV=y
-CONFIG_PCI_HYPERV=m
-CONFIG_HOTPLUG_PCI_ACPI=y
-CONFIG_HOTPLUG_PCI_ACPI_IBM=m
-CONFIG_HOTPLUG_PCI_CPCI=y
-CONFIG_HOTPLUG_PCI_CPCI_ZT5550=m
-CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_DW_PLAT=y
-CONFIG_PCIE_DW_PLAT_HOST=y
-# CONFIG_PCIE_DW_PLAT_EP is not set
-CONFIG_PCI_ENDPOINT=y
-CONFIG_PCI_ENDPOINT_CONFIGFS=y
-CONFIG_PCI_EPF_TEST=m
-CONFIG_PCI_SW_SWITCHTEC=m
-# CONFIG_ISA_BUS is not set
-CONFIG_PCCARD=m
-CONFIG_PCMCIA=m
-CONFIG_YENTA=m
-CONFIG_PD6729=m
-CONFIG_I82092=m
-CONFIG_RAPIDIO=y
-CONFIG_RAPIDIO_TSI721=y
-CONFIG_RAPIDIO_DISC_TIMEOUT=30
-# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set
-CONFIG_RAPIDIO_DMA_ENGINE=y
-# CONFIG_RAPIDIO_DEBUG is not set
-CONFIG_RAPIDIO_ENUM_BASIC=m
-CONFIG_RAPIDIO_CHMAN=m
-CONFIG_RAPIDIO_MPORT_CDEV=m
-CONFIG_64BIT_TIME=y
-CONFIG_COMPAT_32BIT_TIME=y
-
-#
-# RapidIO Switch drivers
-#
-CONFIG_RAPIDIO_TSI57X=y
-CONFIG_RAPIDIO_CPS_XX=y
-CONFIG_RAPIDIO_TSI568=y
-CONFIG_RAPIDIO_CPS_GEN2=y
-CONFIG_RAPIDIO_RXS_GEN3=m
-CONFIG_EDD=y
-# CONFIG_EDD_OFF is not set
-CONFIG_DCDBAS=m
-CONFIG_DMI_SYSFS=m
-CONFIG_ISCSI_IBFT_FIND=y
-CONFIG_ISCSI_IBFT=m
-CONFIG_FW_CFG_SYSFS=m
-CONFIG_FW_CFG_SYSFS_CMDLINE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_EFI_VARS=m
-CONFIG_EFI_CAPSULE_LOADER=m
-CONFIG_EFI_TEST=m
-CONFIG_APPLE_PROPERTIES=y
-CONFIG_RESET_ATTACK_MITIGATION=y
-CONFIG_UEFI_CPER=y
-CONFIG_EFI_DEV_PATH_PARSER=y
-CONFIG_HAVE_KVM_IRQCHIP=y
-CONFIG_HAVE_KVM_IRQFD=y
-CONFIG_HAVE_KVM_IRQ_ROUTING=y
-CONFIG_HAVE_KVM_EVENTFD=y
-CONFIG_KVM_MMIO=y
-CONFIG_KVM_ASYNC_PF=y
-CONFIG_HAVE_KVM_MSI=y
-CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
-CONFIG_KVM_VFIO=y
-CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
-CONFIG_KVM_COMPAT=y
-CONFIG_HAVE_KVM_IRQ_BYPASS=y
-CONFIG_KVM=m
-CONFIG_KVM_INTEL=m
-CONFIG_KVM_AMD=m
-CONFIG_KVM_AMD_SEV=y
-# CONFIG_KVM_MMU_AUDIT is not set
-CONFIG_VHOST_NET=m
-CONFIG_VHOST_SCSI=m
-CONFIG_VHOST_VSOCK=m
-CONFIG_VHOST=m
-CONFIG_OPROFILE=m
-CONFIG_OPROFILE_EVENT_MULTIPLEX=y
-CONFIG_KPROBES_ON_FTRACE=y
-CONFIG_USER_RETURN_NOTIFIER=y
-CONFIG_HAVE_RCU_TABLE_FREE=y
-CONFIG_HAVE_RCU_TABLE_INVALIDATE=y
-CONFIG_ISA_BUS_API=y
-CONFIG_REFCOUNT_FULL=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_ZONED=y
-CONFIG_BLK_DEV_THROTTLING=y
-CONFIG_BLK_DEV_THROTTLING_LOW=y
-CONFIG_BLK_WBT=y
-# CONFIG_BLK_CGROUP_IOLATENCY is not set
-CONFIG_BLK_WBT_SQ=y
-CONFIG_BLK_WBT_MQ=y
-CONFIG_BLK_DEBUG_FS_ZONED=y
-CONFIG_BLK_SED_OPAL=y
-CONFIG_WBT=y
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-CONFIG_LDM_PARTITION=y
-# CONFIG_LDM_DEBUG is not set
-CONFIG_SYSV68_PARTITION=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_MQ_RDMA=y
-CONFIG_CFQ_GROUP_IOSCHED=y
-CONFIG_IOSCHED_BFQ_SQ=y
-CONFIG_BFQ_SQ_GROUP_IOSCHED=y
-# CONFIG_DEFAULT_BFQ_SQ is not set
-CONFIG_MQ_BFQ_GROUP_IOSCHED=y
-CONFIG_MQ_IOSCHED_KYBER=m
-CONFIG_IOSCHED_BFQ=y
-CONFIG_BFQ_GROUP_IOSCHED=y
-CONFIG_PREEMPT_NOTIFIERS=y
-CONFIG_PADATA=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_BINFMT_MISC=m
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_HAVE_BOOTMEM_INFO_NODE=y
-CONFIG_MEMORY_HOTPLUG=y
-CONFIG_MEMORY_HOTPLUG_SPARSE=y
-CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y
-CONFIG_MEMORY_HOTREMOVE=y
-CONFIG_MEMORY_BALLOON=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_KSM=y
-CONFIG_UKSM=y
-# CONFIG_KSM_LEGACY is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
-CONFIG_MEMORY_FAILURE=y
-# CONFIG_HWPOISON_INJECT is not set
-CONFIG_TRANSPARENT_HUGEPAGE=y
-# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set
-CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
-CONFIG_THP_SWAP=y
-CONFIG_TRANSPARENT_HUGE_PAGECACHE=y
-CONFIG_CLEANCACHE=y
-CONFIG_FRONTSWAP=y
-CONFIG_CMA=y
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_AREAS=7
-# CONFIG_MEM_SOFT_DIRTY is not set
-CONFIG_ZSWAP=y
-CONFIG_ZPOOL=y
-CONFIG_ZBUD=y
-CONFIG_Z3FOLD=m
-CONFIG_ZSMALLOC=y
-# CONFIG_PGTABLE_MAPPING is not set
-# CONFIG_ZSMALLOC_STAT is not set
-CONFIG_ZONE_DEVICE=y
-CONFIG_ARCH_HAS_HMM=y
-CONFIG_MIGRATE_VMA_HELPER=y
-CONFIG_DEV_PAGEMAP_OPS=y
-CONFIG_HMM=y
-CONFIG_HMM_MIRROR=y
-CONFIG_DEVICE_PRIVATE=y
-CONFIG_DEVICE_PUBLIC=y
-CONFIG_FRAME_VECTOR=y
-CONFIG_PERCPU_STATS=y
-CONFIG_COMPAT_NETLINK_MESSAGES=y
-CONFIG_INTEL_ATOMISP2_PM=y
-CONFIG_NET_EGRESS=y
-CONFIG_PACKET=m
-CONFIG_PACKET_DIAG=m
-CONFIG_UNIX_DIAG=m
-CONFIG_TLS=y
-# CONFIG_TLS_DEVICE is not set
-CONFIG_XFRM_OFFLOAD=y
-CONFIG_XFRM_ALGO=m
-CONFIG_XFRM_USER=m
-CONFIG_XFRM_SUB_POLICY=y
-CONFIG_XFRM_MIGRATE=y
-CONFIG_XFRM_IPCOMP=m
-CONFIG_NET_KEY=m
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_SMC=m
-CONFIG_SMC_DIAG=m
-# CONFIG_XDP_SOCKETS is not set
-CONFIG_IP_ROUTE_CLASSID=y
-# CONFIG_IP_PNP is not set
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE_DEMUX=m
-CONFIG_NET_IP_TUNNEL=m
-CONFIG_NET_IPGRE=m
-CONFIG_NET_IPGRE_BROADCAST=y
-CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-CONFIG_NET_IPVTI=m
-CONFIG_NET_UDP_TUNNEL=m
-CONFIG_NET_FOU=m
-CONFIG_NET_FOU_IP_TUNNELS=y
-CONFIG_WIREGUARD=m
-# CONFIG_WIREGUARD_DEBUG is not set
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_ESP_OFFLOAD=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_XFRM_TUNNEL=m
-CONFIG_INET_TUNNEL=m
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-# CONFIG_INET_DIAG is not set
-CONFIG_INET_TCP_DIAG=y
-CONFIG_INET_UDP_DIAG=m
-CONFIG_INET_RAW_DIAG=m
-# CONFIG_INET_DIAG_DESTROY is not set
-CONFIG_TCP_CONG_BIC=m
-CONFIG_TCP_CONG_WESTWOOD=m
-CONFIG_TCP_CONG_HTCP=m
-CONFIG_TCP_CONG_HSTCP=m
-CONFIG_TCP_CONG_HYBLA=m
-CONFIG_TCP_CONG_VEGAS=m
-CONFIG_TCP_CONG_NV=m
-CONFIG_TCP_CONG_SCALABLE=m
-CONFIG_TCP_CONG_LP=m
-CONFIG_TCP_CONG_VENO=m
-CONFIG_TCP_CONG_YEAH=m
-CONFIG_TCP_CONG_ILLINOIS=m
-CONFIG_TCP_CONG_DCTCP=m
-CONFIG_TCP_CONG_BBR=m
-CONFIG_MPTCP=y
-CONFIG_IPV6=m
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_ESP_OFFLOAD=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_INET6_XFRM_TUNNEL=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-CONFIG_INET6_XFRM_MODE_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_BEET=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_VTI=m
-CONFIG_IPV6_SIT=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_GRE=m
-CONFIG_IPV6_FOU=m
-CONFIG_IPV6_FOU_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-CONFIG_IPV6_MROUTE=y
-CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IPV6_PIMSM_V2=y
-CONFIG_IPV6_SEG6_LWTUNNEL=y
-CONFIG_IPV6_SEG6_HMAC=y
-CONFIG_NETWORK_PHY_TIMESTAMPING=y
-CONFIG_NETFILTER_ADVANCED=y
-CONFIG_BRIDGE_NETFILTER=m
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_FAMILY_BRIDGE=y
-CONFIG_NETFILTER_FAMILY_ARP=y
-CONFIG_NETFILTER_NETLINK_ACCT=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NETFILTER_NETLINK_OSF=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_LOG_NETDEV=m
-CONFIG_NETFILTER_CONNCOUNT=m
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_ZONES=y
-# CONFIG_NF_CONNTRACK_PROCFS is not set
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CONNTRACK_TIMEOUT=y
-CONFIG_NF_CONNTRACK_TIMESTAMP=y
-CONFIG_NF_CONNTRACK_LABELS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_GRE=m
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_BROADCAST=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_SNMP=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NF_CT_NETLINK_TIMEOUT=m
-CONFIG_NF_NAT_PROTO_DCCP=y
-CONFIG_NF_NAT_PROTO_UDPLITE=y
-CONFIG_NF_NAT_PROTO_SCTP=y
-CONFIG_NF_NAT_AMANDA=m
-CONFIG_NF_NAT_TFTP=m
-CONFIG_NF_NAT_REDIRECT=y
-CONFIG_NETFILTER_SYNPROXY=m
-CONFIG_NF_TABLES=m
-CONFIG_NF_TABLES_SET=m
-CONFIG_NF_TABLES_INET=y
-# CONFIG_NF_TABLES_NETDEV is not set
-CONFIG_NFT_NUMGEN=m
-CONFIG_NFT_CT=m
-CONFIG_NFT_FLOW_OFFLOAD=m
-CONFIG_NFT_COUNTER=m
-# CONFIG_NFT_CONNLIMIT is not set
-CONFIG_NFT_LOG=m
-CONFIG_NFT_LIMIT=m
-CONFIG_NFT_MASQ=m
-CONFIG_NFT_REDIR=m
-CONFIG_NFT_NAT=m
-# CONFIG_NFT_TUNNEL is not set
-CONFIG_NFT_OBJREF=m
-CONFIG_NFT_QUEUE=m
-CONFIG_NFT_QUOTA=m
-CONFIG_NFT_REJECT=m
-CONFIG_NFT_REJECT_INET=m
-CONFIG_NFT_COMPAT=m
-CONFIG_NFT_HASH=m
-CONFIG_NFT_FIB=m
-CONFIG_NFT_FIB_INET=m
-# CONFIG_NFT_SOCKET is not set
-# CONFIG_NFT_OSF is not set
-# CONFIG_NFT_TPROXY is not set
-CONFIG_NF_FLOW_TABLE_INET=m
-CONFIG_NF_FLOW_TABLE=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XT_CONNMARK=m
-CONFIG_NETFILTER_XT_SET=m
-CONFIG_NETFILTER_XT_TARGET_AUDIT=m
-CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CT=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_HL=m
-CONFIG_NETFILTER_XT_TARGET_HMARK=m
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NETMAP=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
-CONFIG_NETFILTER_XT_TARGET_RATEEST=m
-CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
-CONFIG_NETFILTER_XT_TARGET_TEE=m
-CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-CONFIG_NETFILTER_XT_TARGET_TRACE=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-CONFIG_NETFILTER_XT_MATCH_BPF=m
-CONFIG_NETFILTER_XT_MATCH_CGROUP=m
-CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_CPU=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ECN=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_HL=m
-CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_IPVS=m
-CONFIG_NETFILTER_XT_MATCH_L2TP=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-CONFIG_NETFILTER_XT_MATCH_OSF=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-CONFIG_IP_SET=m
-CONFIG_IP_SET_MAX=256
-CONFIG_IP_SET_BITMAP_IP=m
-CONFIG_IP_SET_BITMAP_IPMAC=m
-CONFIG_IP_SET_BITMAP_PORT=m
-CONFIG_IP_SET_HASH_IP=m
-CONFIG_IP_SET_HASH_IPMARK=m
-CONFIG_IP_SET_HASH_IPPORT=m
-CONFIG_IP_SET_HASH_IPPORTIP=m
-CONFIG_IP_SET_HASH_IPPORTNET=m
-CONFIG_IP_SET_HASH_IPMAC=m
-CONFIG_IP_SET_HASH_MAC=m
-CONFIG_IP_SET_HASH_NETPORTNET=m
-CONFIG_IP_SET_HASH_NET=m
-CONFIG_IP_SET_HASH_NETNET=m
-CONFIG_IP_SET_HASH_NETPORT=m
-CONFIG_IP_SET_HASH_NETIFACE=m
-CONFIG_IP_SET_LIST_SET=m
-CONFIG_IP_VS=m
-CONFIG_IP_VS_IPV6=y
-# CONFIG_IP_VS_DEBUG is not set
-CONFIG_IP_VS_TAB_BITS=12
-
-#
-# IPVS transport protocol load balancing support
-#
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_AH_ESP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_PROTO_SCTP=y
-
-#
-# IPVS scheduler
-#
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_FO=m
-# CONFIG_IP_VS_OVF is not set
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-# CONFIG_IP_VS_MH is not set
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-
-#
-# IPVS SH scheduler
-#
-CONFIG_IP_VS_SH_TAB_BITS=8
-
-#
-# IPVS MH scheduler
-#
-CONFIG_IP_VS_MH_TAB_INDEX=12
-
-#
-# IPVS application helper
-#
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_VS_NFCT=y
-CONFIG_IP_VS_PE_SIP=m
-CONFIG_NF_DEFRAG_IPV4=m
-CONFIG_NF_SOCKET_IPV4=m
-CONFIG_NF_TPROXY_IPV4=m
-CONFIG_NF_TABLES_IPV4=y
-CONFIG_NFT_CHAIN_ROUTE_IPV4=m
-CONFIG_NFT_REJECT_IPV4=m
-# CONFIG_NFT_DUP_IPV4 is not set
-CONFIG_NFT_FIB_IPV4=m
-CONFIG_NF_TABLES_ARP=y
-CONFIG_NF_FLOW_TABLE_IPV4=m
-CONFIG_NF_DUP_IPV4=m
-CONFIG_NF_REJECT_IPV4=m
-CONFIG_NFT_CHAIN_NAT_IPV4=m
-CONFIG_NFT_MASQ_IPV4=m
-CONFIG_NFT_REDIR_IPV4=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_NF_NAT_PROTO_GRE=m
-CONFIG_NF_NAT_PPTP=m
-CONFIG_NF_NAT_H323=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_RPFILTER=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_SYNPROXY=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_SECURITY=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_NF_SOCKET_IPV6=m
-CONFIG_NF_TPROXY_IPV6=m
-CONFIG_NF_TABLES_IPV6=y
-CONFIG_NFT_CHAIN_ROUTE_IPV6=m
-CONFIG_NFT_CHAIN_NAT_IPV6=m
-CONFIG_NFT_MASQ_IPV6=m
-CONFIG_NFT_REDIR_IPV6=m
-CONFIG_NFT_REJECT_IPV6=m
-# CONFIG_NFT_DUP_IPV6 is not set
-CONFIG_NFT_FIB_IPV6=m
-CONFIG_NF_FLOW_TABLE_IPV6=m
-CONFIG_NF_DUP_IPV6=m
-CONFIG_NF_REJECT_IPV6=m
-CONFIG_NF_NAT_IPV6=m
-CONFIG_NF_NAT_MASQUERADE_IPV6=y
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RPFILTER=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_MATCH_SRH=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_TARGET_SYNPROXY=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_IP6_NF_SECURITY=m
-CONFIG_IP6_NF_NAT=m
-CONFIG_IP6_NF_TARGET_MASQUERADE=m
-CONFIG_IP6_NF_TARGET_NPT=m
-CONFIG_NF_DEFRAG_IPV6=m
-
-#
-# DECnet: Netfilter Configuration
-#
-CONFIG_DECNET_NF_GRABULATOR=m
-CONFIG_NF_TABLES_BRIDGE=y
-CONFIG_NFT_BRIDGE_REJECT=m
-CONFIG_NF_LOG_BRIDGE=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_IP6=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_BRIDGE_EBT_NFLOG=m
-CONFIG_IP_DCCP=m
-CONFIG_INET_DCCP_DIAG=m
-
-#
-# DCCP CCIDs Configuration
-#
-# CONFIG_IP_DCCP_CCID2_DEBUG is not set
-CONFIG_IP_DCCP_CCID3=y
-# CONFIG_IP_DCCP_CCID3_DEBUG is not set
-CONFIG_IP_DCCP_TFRC_LIB=y
-
-#
-# DCCP Kernel Hacking
-#
-# CONFIG_IP_DCCP_DEBUG is not set
-CONFIG_IP_SCTP=m
-# CONFIG_SCTP_DBG_OBJCNT is not set
-CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
-CONFIG_SCTP_COOKIE_HMAC_MD5=y
-CONFIG_SCTP_COOKIE_HMAC_SHA1=y
-CONFIG_INET_SCTP_DIAG=m
-CONFIG_RDS=m
-CONFIG_RDS_RDMA=m
-CONFIG_RDS_TCP=m
-# CONFIG_RDS_DEBUG is not set
-CONFIG_TIPC=m
-CONFIG_TIPC_MEDIA_IB=y
-CONFIG_TIPC_MEDIA_UDP=y
-CONFIG_TIPC_DIAG=m
-CONFIG_ATM=m
-CONFIG_ATM_CLIP=m
-# CONFIG_ATM_CLIP_NO_ICMP is not set
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-CONFIG_ATM_BR2684_IPFILTER=y
-CONFIG_L2TP=m
-CONFIG_L2TP_DEBUGFS=m
-# CONFIG_L2TP_V3 is not set
-CONFIG_STP=m
-CONFIG_GARP=m
-CONFIG_MRP=m
-CONFIG_BRIDGE=m
-CONFIG_BRIDGE_IGMP_SNOOPING=y
-CONFIG_BRIDGE_VLAN_FILTERING=y
-CONFIG_NET_DSA=m
-# CONFIG_NET_DSA_LEGACY is not set
-CONFIG_NET_DSA_TAG_BRCM=y
-CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
-CONFIG_NET_DSA_TAG_DSA=y
-CONFIG_NET_DSA_TAG_EDSA=y
-CONFIG_NET_DSA_TAG_KSZ=y
-CONFIG_NET_DSA_TAG_LAN9303=y
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_DSA_TAG_QCA=y
-CONFIG_VLAN_8021Q=m
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_VLAN_8021Q_MVRP=y
-CONFIG_DECNET=m
-# CONFIG_DECNET_ROUTER is not set
-CONFIG_LLC=m
-CONFIG_LLC2=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_PHONET=m
-CONFIG_6LOWPAN=m
-# CONFIG_6LOWPAN_DEBUGFS is not set
-CONFIG_6LOWPAN_NHC=m
-CONFIG_6LOWPAN_NHC_DEST=m
-CONFIG_6LOWPAN_NHC_FRAGMENT=m
-CONFIG_6LOWPAN_NHC_HOP=m
-CONFIG_6LOWPAN_NHC_IPV6=m
-CONFIG_6LOWPAN_NHC_MOBILITY=m
-CONFIG_6LOWPAN_NHC_ROUTING=m
-CONFIG_6LOWPAN_NHC_UDP=m
-# CONFIG_6LOWPAN_GHC_EXT_HDR_HOP is not set
-# CONFIG_6LOWPAN_GHC_UDP is not set
-# CONFIG_6LOWPAN_GHC_ICMPV6 is not set
-# CONFIG_6LOWPAN_GHC_EXT_HDR_DEST is not set
-# CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG is not set
-# CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE is not set
-CONFIG_IEEE802154=m
-# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set
-CONFIG_IEEE802154_SOCKET=m
-CONFIG_IEEE802154_6LOWPAN=m
-CONFIG_MAC802154=m
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_ETS=m
-CONFIG_NET_SCH_CAKE=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-# CONFIG_NET_SCH_ATM is not set
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_MULTIQ=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFB=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_CBS=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_DRR=m
-CONFIG_NET_SCH_MQPRIO=m
-CONFIG_NET_SCH_CHOKE=m
-CONFIG_NET_SCH_QFQ=m
-CONFIG_NET_SCH_CODEL=m
-CONFIG_NET_SCH_FQ_CODEL=y
-CONFIG_NET_SCH_FQ=m
-CONFIG_NET_SCH_FQ_PIE=m
-CONFIG_NET_SCH_HHF=m
-CONFIG_NET_SCH_PIE=m
-CONFIG_NET_SCH_INGRESS=m
-CONFIG_NET_SCH_PLUG=m
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-# CONFIG_CLS_U32_PERF is not set
-# CONFIG_CLS_U32_MARK is not set
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_CLS_FLOW=m
-CONFIG_NET_CLS_CGROUP=y
-CONFIG_NET_CLS_BPF=m
-CONFIG_NET_CLS_MATCHALL=m
-CONFIG_NET_EMATCH_CMP=m
-CONFIG_NET_EMATCH_NBYTE=m
-CONFIG_NET_EMATCH_U32=m
-CONFIG_NET_EMATCH_META=m
-CONFIG_NET_EMATCH_TEXT=m
-CONFIG_NET_EMATCH_CANID=m
-CONFIG_NET_EMATCH_IPSET=m
-CONFIG_NET_EMATCH_IPT=m
-CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_GACT=m
-CONFIG_GACT_PROB=y
-CONFIG_NET_ACT_MIRRED=m
-CONFIG_NET_ACT_SAMPLE=m
-CONFIG_NET_ACT_IPT=m
-CONFIG_NET_ACT_NAT=m
-CONFIG_NET_ACT_PEDIT=m
-CONFIG_NET_ACT_SIMP=m
-CONFIG_NET_ACT_SKBEDIT=m
-CONFIG_NET_ACT_CSUM=m
-CONFIG_NET_ACT_VLAN=m
-CONFIG_NET_ACT_BPF=m
-CONFIG_NET_ACT_CONNMARK=m
-CONFIG_NET_ACT_SKBMOD=m
-CONFIG_NET_ACT_IFE=m
-CONFIG_NET_ACT_TUNNEL_KEY=m
-CONFIG_NET_IFE_SKBMARK=m
-CONFIG_NET_IFE_SKBPRIO=m
-CONFIG_NET_IFE_SKBTCINDEX=m
-# CONFIG_NET_CLS_IND is not set
-CONFIG_DCB=y
-CONFIG_OPENVSWITCH=m
-CONFIG_OPENVSWITCH_GRE=m
-CONFIG_OPENVSWITCH_VXLAN=m
-CONFIG_OPENVSWITCH_GENEVE=m
-CONFIG_VSOCKETS=m
-CONFIG_VSOCKETS_DIAG=m
-CONFIG_VMWARE_VMCI_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS_COMMON=m
-CONFIG_HYPERV_VSOCKETS=m
-CONFIG_NETLINK_DIAG=m
-CONFIG_MPLS=y
-CONFIG_NET_MPLS_GSO=y
-CONFIG_MPLS_ROUTING=m
-CONFIG_MPLS_IPTUNNEL=m
-CONFIG_NET_NSH=m
-CONFIG_HSR=m
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_L3_MASTER_DEV=y
-CONFIG_NET_NCSI=y
-CONFIG_CGROUP_NET_PRIO=y
-CONFIG_CGROUP_NET_CLASSID=y
-CONFIG_BPF_JIT=y
-CONFIG_BPF_STREAM_PARSER=y
-CONFIG_NET_PKTGEN=m
-CONFIG_AX25=m
-CONFIG_AX25_DAMA_SLAVE=y
-CONFIG_NETROM=m
-CONFIG_ROSE=m
-
-#
-# AX.25 network device drivers
-#
-CONFIG_MKISS=m
-CONFIG_6PACK=m
-CONFIG_BPQETHER=m
-CONFIG_BAYCOM_SER_FDX=m
-CONFIG_BAYCOM_SER_HDX=m
-CONFIG_BAYCOM_PAR=m
-CONFIG_YAM=m
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_GW=m
-
-#
-# CAN Device Drivers
-#
-CONFIG_CAN_VCAN=m
-CONFIG_CAN_VXCAN=m
-CONFIG_CAN_SLCAN=m
-CONFIG_CAN_DEV=m
-# CONFIG_CAN_CALC_BITTIMING is not set
-CONFIG_CAN_C_CAN=m
-CONFIG_CAN_C_CAN_PLATFORM=m
-CONFIG_CAN_C_CAN_PCI=m
-CONFIG_CAN_CC770=m
-CONFIG_CAN_CC770_ISA=m
-CONFIG_CAN_CC770_PLATFORM=m
-CONFIG_CAN_IFI_CANFD=m
-CONFIG_CAN_M_CAN=m
-CONFIG_CAN_PEAK_PCIEFD=m
-CONFIG_CAN_SJA1000=m
-CONFIG_CAN_SJA1000_ISA=m
-# CONFIG_CAN_SJA1000_PLATFORM is not set
-CONFIG_CAN_EMS_PCMCIA=m
-CONFIG_CAN_EMS_PCI=m
-CONFIG_CAN_PEAK_PCMCIA=m
-CONFIG_CAN_PEAK_PCI=m
-CONFIG_CAN_PEAK_PCIEC=y
-CONFIG_CAN_KVASER_PCI=m
-CONFIG_CAN_PLX_PCI=m
-CONFIG_CAN_SOFTING=m
-CONFIG_CAN_SOFTING_CS=m
-
-#
-# CAN SPI interfaces
-#
-CONFIG_CAN_HI311X=m
-CONFIG_CAN_MCP251X=m
-
-#
-# CAN USB interfaces
-#
-CONFIG_CAN_8DEV_USB=m
-CONFIG_CAN_EMS_USB=m
-CONFIG_CAN_ESD_USB2=m
-CONFIG_CAN_GS_USB=m
-CONFIG_CAN_KVASER_USB=m
-CONFIG_CAN_MCBA_USB=m
-CONFIG_CAN_PEAK_USB=m
-# CONFIG_CAN_UCAN is not set
-# CONFIG_CAN_DEBUG_DEVICES is not set
-CONFIG_BT=m
-CONFIG_BT_BREDR=y
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_CMTP=m
-CONFIG_BT_HIDP=m
-CONFIG_BT_HS=y
-CONFIG_BT_LE=y
-CONFIG_BT_6LOWPAN=m
-CONFIG_BT_LEDS=y
-# CONFIG_BT_SELFTEST is not set
-# CONFIG_BT_DEBUGFS is not set
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_INTEL=m
-CONFIG_BT_BCM=m
-CONFIG_BT_RTL=m
-CONFIG_BT_HCIBTUSB=m
-CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
-CONFIG_BT_HCIBTUSB_BCM=y
-CONFIG_BT_HCIBTUSB_RTL=y
-CONFIG_BT_HCIBTSDIO=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_SERDEV=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_NOKIA=m
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_ATH3K=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIUART_3WIRE=y
-CONFIG_BT_HCIUART_INTEL=y
-# CONFIG_BT_HCIUART_RTL is not set
-# CONFIG_BT_HCIUART_QCA is not set
-CONFIG_BT_HCIUART_AG6XX=y
-CONFIG_BT_HCIUART_MRVL=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIDTL1=m
-CONFIG_BT_HCIBT3C=m
-CONFIG_BT_HCIBLUECARD=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_BT_MRVL=m
-CONFIG_BT_MRVL_SDIO=m
-CONFIG_BT_ATH3K=m
-CONFIG_BT_WILINK=m
-# CONFIG_BT_MTKUART is not set
-CONFIG_BT_HCIRSI=m
-CONFIG_AF_RXRPC=m
-CONFIG_AF_RXRPC_IPV6=y
-# CONFIG_AF_RXRPC_INJECT_LOSS is not set
-# CONFIG_AF_RXRPC_DEBUG is not set
-CONFIG_RXKAD=y
-CONFIG_AF_KCM=m
-CONFIG_STREAM_PARSER=y
-CONFIG_WIRELESS_EXT=y
-CONFIG_WEXT_CORE=y
-CONFIG_WEXT_PROC=y
-CONFIG_WEXT_SPY=y
-CONFIG_WEXT_PRIV=y
-CONFIG_CFG80211=m
-# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
-CONFIG_CFG80211_WEXT=y
-CONFIG_CFG80211_WEXT_EXPORT=y
-CONFIG_LIB80211=m
-CONFIG_LIB80211_CRYPT_WEP=m
-CONFIG_LIB80211_CRYPT_CCMP=m
-CONFIG_LIB80211_CRYPT_TKIP=m
-# CONFIG_LIB80211_DEBUG is not set
-CONFIG_MAC80211=m
-CONFIG_MAC80211_RC_MINSTREL_VHT=y
-CONFIG_MAC80211_MESH=y
-CONFIG_WIMAX=m
-CONFIG_WIMAX_DEBUG_LEVEL=8
-CONFIG_RFKILL=m
-CONFIG_RFKILL_GPIO=m
-CONFIG_NET_9P=m
-CONFIG_NET_9P_VIRTIO=m
-CONFIG_NET_9P_XEN=m
-CONFIG_NET_9P_RDMA=m
-# CONFIG_NET_9P_DEBUG is not set
-CONFIG_CAIF=m
-# CONFIG_CAIF_DEBUG is not set
-CONFIG_CAIF_NETDEV=m
-CONFIG_CAIF_USB=m
-CONFIG_CEPH_LIB=m
-# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
-# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
-CONFIG_NFC=m
-CONFIG_NFC_DIGITAL=m
-CONFIG_NFC_NCI=m
-# CONFIG_NFC_NCI_SPI is not set
-# CONFIG_NFC_NCI_UART is not set
-CONFIG_NFC_HCI=m
-CONFIG_NFC_SHDLC=y
-
-#
-# Near Field Communication (NFC) devices
-#
-CONFIG_NFC_TRF7970A=m
-CONFIG_NFC_MEI_PHY=m
-CONFIG_NFC_SIM=m
-CONFIG_NFC_PORT100=m
-# CONFIG_NFC_FDP is not set
-CONFIG_NFC_PN544=m
-CONFIG_NFC_PN544_I2C=m
-CONFIG_NFC_PN544_MEI=m
-CONFIG_NFC_PN533=m
-CONFIG_NFC_PN533_USB=m
-CONFIG_NFC_PN533_I2C=m
-CONFIG_NFC_MICROREAD=m
-CONFIG_NFC_MICROREAD_I2C=m
-CONFIG_NFC_MICROREAD_MEI=m
-CONFIG_NFC_MRVL=m
-CONFIG_NFC_MRVL_USB=m
-# CONFIG_NFC_MRVL_I2C is not set
-CONFIG_NFC_ST21NFCA=m
-CONFIG_NFC_ST21NFCA_I2C=m
-# CONFIG_NFC_ST_NCI_I2C is not set
-# CONFIG_NFC_ST_NCI_SPI is not set
-# CONFIG_NFC_NXP_NCI is not set
-# CONFIG_NFC_S3FWRN5_I2C is not set
-# CONFIG_NFC_ST95HF is not set
-CONFIG_PSAMPLE=m
-CONFIG_NET_IFE=m
-CONFIG_LWTUNNEL=y
-CONFIG_LWTUNNEL_BPF=y
-CONFIG_NET_DEVLINK=m
-CONFIG_MAY_USE_DEVLINK=m
-CONFIG_FAILOVER=m
-CONFIG_UEVENT_HELPER_PATH=""
-# CONFIG_DEVTMPFS_MOUNT is not set
-# CONFIG_STANDALONE is not set
-# CONFIG_FW_LOADER_USER_HELPER is not set
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_WANT_DEV_COREDUMP=y
-CONFIG_DEV_COREDUMP=y
-# CONFIG_DEBUG_DEVRES is not set
-CONFIG_TEST_ASYNC_DRIVER_PROBE=m
-CONFIG_SYS_HYPERVISOR=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGMAP_SPMI=m
-CONFIG_REGMAP_W1=m
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_SOUNDWIRE=m
-# CONFIG_DMA_CMA is not set
-CONFIG_DMA_DIRECT_OPS=y
-CONFIG_CONNECTOR=m
-CONFIG_MTD=m
-CONFIG_MTD_TESTS=m
-CONFIG_MTD_REDBOOT_PARTS=m
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
-# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-CONFIG_MTD_AR7_PARTS=m
-
-#
-# Partition parsers
-#
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
-CONFIG_MTD_BLOCK_RO=m
-CONFIG_FTL=m
-CONFIG_NFTL=m
-# CONFIG_NFTL_RW is not set
-CONFIG_INFTL=m
-CONFIG_RFD_FTL=m
-CONFIG_SSFDC=m
-CONFIG_SM_FTL=m
-CONFIG_MTD_OOPS=m
-CONFIG_MTD_SWAP=m
-# CONFIG_MTD_PARTITIONED_MASTER is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_GEN_PROBE=m
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-CONFIG_MTD_CFI_INTELEXT=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_CFI_STAA=m
-CONFIG_MTD_CFI_UTIL=m
-CONFIG_MTD_RAM=m
-CONFIG_MTD_ROM=m
-CONFIG_MTD_ABSENT=m
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_AMD76XROM=m
-CONFIG_MTD_ICHXROM=m
-CONFIG_MTD_ESB2ROM=m
-CONFIG_MTD_CK804XROM=m
-CONFIG_MTD_SCB2_FLASH=m
-CONFIG_MTD_NETtel=m
-CONFIG_MTD_L440GX=m
-CONFIG_MTD_INTEL_VR_NOR=m
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-CONFIG_MTD_PMC551=m
-# CONFIG_MTD_PMC551_BUGFIX is not set
-# CONFIG_MTD_PMC551_DEBUG is not set
-CONFIG_MTD_DATAFLASH=m
-# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
-# CONFIG_MTD_DATAFLASH_OTP is not set
-CONFIG_MTD_MCHP23K256=m
-CONFIG_MTD_SST25L=m
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTDRAM_TOTAL_SIZE=4096
-CONFIG_MTDRAM_ERASE_SIZE=128
-CONFIG_MTD_BLOCK2MTD=m
-
-#
-# Disk-On-Chip Device Drivers
-#
-CONFIG_MTD_DOCG3=m
-CONFIG_BCH_CONST_M=14
-CONFIG_BCH_CONST_T=4
-CONFIG_MTD_ONENAND=m
-# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
-# CONFIG_MTD_ONENAND_GENERIC is not set
-CONFIG_MTD_ONENAND_OTP=y
-CONFIG_MTD_ONENAND_2X_PROGRAM=y
-CONFIG_MTD_NAND_ECC=m
-CONFIG_MTD_NAND_ECC_SMC=y
-CONFIG_MTD_NAND=m
-# CONFIG_MTD_NAND_ECC_BCH is not set
-CONFIG_MTD_SM_COMMON=m
-CONFIG_MTD_NAND_DENALI=m
-CONFIG_MTD_NAND_DENALI_PCI=m
-CONFIG_MTD_NAND_GPIO=m
-CONFIG_MTD_NAND_RICOH=m
-CONFIG_MTD_NAND_DISKONCHIP=m
-# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
-# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set
-CONFIG_MTD_NAND_DOCG4=m
-CONFIG_MTD_NAND_CAFE=m
-CONFIG_MTD_NAND_NANDSIM=m
-# CONFIG_MTD_NAND_PLATFORM is not set
-# CONFIG_MTD_SPI_NAND is not set
-
-#
-# LPDDR & LPDDR2 PCM memory drivers
-#
-CONFIG_MTD_LPDDR=m
-CONFIG_MTD_QINFO_PROBE=m
-# CONFIG_MTD_SPI_NOR is not set
-CONFIG_MTD_UBI=m
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_FASTMAP is not set
-# CONFIG_MTD_UBI_GLUEBI is not set
-# CONFIG_MTD_UBI_BLOCK is not set
-CONFIG_PARPORT=m
-CONFIG_PARPORT_PC=m
-CONFIG_PARPORT_SERIAL=m
-CONFIG_PARPORT_PC_FIFO=y
-CONFIG_PARPORT_PC_SUPERIO=y
-CONFIG_PARPORT_PC_PCMCIA=m
-# CONFIG_PARPORT_AX88796 is not set
-CONFIG_PARPORT_1284=y
-CONFIG_PARPORT_NOT_PC=y
-CONFIG_BLK_DEV_FD=m
-CONFIG_PARIDE=m
-
-#
-# Parallel IDE high-level drivers
-#
-CONFIG_PARIDE_PD=m
-CONFIG_PARIDE_PCD=m
-CONFIG_PARIDE_PF=m
-CONFIG_PARIDE_PT=m
-CONFIG_PARIDE_PG=m
-
-#
-# Parallel IDE protocol modules
-#
-CONFIG_PARIDE_ATEN=m
-CONFIG_PARIDE_BPCK=m
-CONFIG_PARIDE_COMM=m
-CONFIG_PARIDE_DSTR=m
-CONFIG_PARIDE_FIT2=m
-CONFIG_PARIDE_FIT3=m
-CONFIG_PARIDE_EPAT=m
-CONFIG_PARIDE_EPATC8=y
-CONFIG_PARIDE_EPIA=m
-CONFIG_PARIDE_FRIQ=m
-CONFIG_PARIDE_FRPW=m
-CONFIG_PARIDE_KBIC=m
-CONFIG_PARIDE_KTTI=m
-CONFIG_PARIDE_ON20=m
-CONFIG_PARIDE_ON26=m
-CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
-CONFIG_ZRAM=m
-CONFIG_ZRAM_WRITEBACK=y
-# CONFIG_ZRAM_MEMORY_TRACKING is not set
-CONFIG_BLK_DEV_DAC960=m
-CONFIG_BLK_DEV_UMEM=m
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_DRBD=m
-# CONFIG_DRBD_FAULT_INJECTION is not set
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_SKD=m
-CONFIG_BLK_DEV_SX8=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=32000
-CONFIG_CDROM_PKTCDVD=y
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=m
-CONFIG_XEN_BLKDEV_FRONTEND=m
-CONFIG_XEN_BLKDEV_BACKEND=m
-CONFIG_VIRTIO_BLK=m
-CONFIG_VIRTIO_BLK_SCSI=y
-CONFIG_BLK_DEV_RBD=m
-CONFIG_BLK_DEV_RSXX=m
-CONFIG_NVME_CORE=m
-CONFIG_BLK_DEV_NVME=m
-# CONFIG_NVME_MULTIPATH is not set
-CONFIG_NVME_FABRICS=m
-CONFIG_NVME_RDMA=m
-CONFIG_NVME_FC=m
-CONFIG_NVME_TCP=m
-CONFIG_NVME_TARGET=m
-CONFIG_NVME_TARGET_LOOP=m
-CONFIG_NVME_TARGET_RDMA=m
-CONFIG_NVME_TARGET_FC=m
-CONFIG_NVME_TARGET_FCLOOP=m
-CONFIG_NVME_TARGET_TCP=m
-CONFIG_SENSORS_LIS3LV02D=m
-CONFIG_SENSORS_G760A=m
-CONFIG_SENSORS_LTC4215=m
-CONFIG_SENSORS_LTC3815=m
-CONFIG_SENSORS_MAX6697=m
-CONFIG_SENSORS_MAX31790=m
-CONFIG_SENSORS_MAX20751=m
-CONFIG_SENSORS_SHT15=m
-CONFIG_SENSORS_SHT21=m
-CONFIG_DUMMY_IRQ=m
-CONFIG_IBM_ASM=m
-CONFIG_PHANTOM=m
-CONFIG_SGI_IOC4=m
-CONFIG_TIFM_CORE=m
-CONFIG_TIFM_7XX1=m
-CONFIG_ICS932S401=m
-CONFIG_ENCLOSURE_SERVICES=m
-CONFIG_HP_ILO=m
-CONFIG_APDS9802ALS=m
-CONFIG_ISL29020=m
-CONFIG_SENSORS_TSL2550=m
-CONFIG_SENSORS_BH1770=m
-CONFIG_SENSORS_APDS990X=m
-CONFIG_HMC6352=m
-CONFIG_DS1682=m
-CONFIG_VMWARE_BALLOON=m
-CONFIG_USB_SWITCH_FSA9480=m
-CONFIG_LATTICE_ECP3_CONFIG=m
-CONFIG_SRAM=y
-CONFIG_PCI_ENDPOINT_TEST=m
-CONFIG_MISC_RTSX=m
-CONFIG_C2PORT=m
-CONFIG_C2PORT_DURAMAR_2150=m
-CONFIG_EEPROM_AT25=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_EEPROM_MAX6875=m
-CONFIG_EEPROM_93CX6=m
-CONFIG_EEPROM_93XX46=m
-CONFIG_EEPROM_IDT_89HPESX=m
-CONFIG_CB710_CORE=m
-# CONFIG_CB710_DEBUG is not set
-CONFIG_CB710_DEBUG_ASSUMPTIONS=y
-CONFIG_TI_ST=m
-CONFIG_SENSORS_LIS3_I2C=m
-CONFIG_ALTERA_STAPL=m
-CONFIG_INTEL_MEI=m
-CONFIG_INTEL_MEI_ME=m
-CONFIG_INTEL_MEI_TXE=m
-CONFIG_VMWARE_VMCI=m
-CONFIG_INTEL_MIC_BUS=m
-CONFIG_VOP_BUS=m
-CONFIG_VOP=m
-CONFIG_VHOST_RING=m
-CONFIG_GENWQE=m
-CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=1
-CONFIG_ECHO=m
-CONFIG_MISC_RTSX_PCI=m
-CONFIG_MISC_RTSX_USB=m
-CONFIG_IDE=m
-
-#
-# Please see Documentation/ide/ide.txt for help/info on IDE drives
-#
-CONFIG_IDE_XFER_MODE=y
-CONFIG_IDE_TIMINGS=y
-CONFIG_IDE_ATAPI=y
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_IDE_GD=m
-CONFIG_IDE_GD_ATA=y
-CONFIG_IDE_GD_ATAPI=y
-CONFIG_BLK_DEV_IDECS=m
-CONFIG_BLK_DEV_DELKIN=m
-CONFIG_BLK_DEV_IDECD=m
-# CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS is not set
-CONFIG_BLK_DEV_IDETAPE=m
-CONFIG_BLK_DEV_IDEACPI=y
-CONFIG_IDE_TASK_IOCTL=y
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-CONFIG_IDE_GENERIC=m
-# CONFIG_BLK_DEV_PLATFORM is not set
-CONFIG_BLK_DEV_CMD640=m
-# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEDMA_SFF=y
-
-#
-# PCI IDE chipsets support
-#
-CONFIG_BLK_DEV_IDEPCI=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
-CONFIG_BLK_DEV_GENERIC=m
-CONFIG_BLK_DEV_OPTI621=m
-CONFIG_BLK_DEV_RZ1000=m
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-CONFIG_BLK_DEV_AEC62XX=m
-CONFIG_BLK_DEV_ALI15X3=m
-CONFIG_BLK_DEV_AMD74XX=m
-CONFIG_BLK_DEV_ATIIXP=m
-CONFIG_BLK_DEV_CMD64X=m
-CONFIG_BLK_DEV_TRIFLEX=m
-CONFIG_BLK_DEV_HPT366=m
-CONFIG_BLK_DEV_JMICRON=m
-CONFIG_BLK_DEV_PIIX=m
-CONFIG_BLK_DEV_IT8172=m
-CONFIG_BLK_DEV_IT8213=m
-CONFIG_BLK_DEV_IT821X=m
-CONFIG_BLK_DEV_NS87415=m
-CONFIG_BLK_DEV_PDC202XX_OLD=m
-CONFIG_BLK_DEV_PDC202XX_NEW=m
-CONFIG_BLK_DEV_SVWKS=m
-CONFIG_BLK_DEV_SIIMAGE=m
-CONFIG_BLK_DEV_SIS5513=m
-CONFIG_BLK_DEV_SLC90E66=m
-CONFIG_BLK_DEV_TRM290=m
-CONFIG_BLK_DEV_VIA82CXXX=m
-CONFIG_BLK_DEV_TC86C001=m
-CONFIG_BLK_DEV_IDEDMA=y
-CONFIG_RAID_ATTRS=m
-CONFIG_SCSI_NETLINK=y
-CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_ENCLOSURE=m
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_ISCSI_ATTRS=m
-CONFIG_SCSI_SAS_ATTRS=m
-CONFIG_SCSI_SAS_LIBSAS=m
-CONFIG_SCSI_SAS_ATA=y
-CONFIG_SCSI_SAS_HOST_SMP=y
-CONFIG_SCSI_SRP_ATTRS=m
-CONFIG_SCSI_LOWLEVEL=y
-CONFIG_ISCSI_TCP=m
-CONFIG_ISCSI_BOOT_SYSFS=m
-CONFIG_SCSI_CXGB3_ISCSI=m
-CONFIG_SCSI_CXGB4_ISCSI=m
-CONFIG_SCSI_BNX2_ISCSI=m
-CONFIG_SCSI_BNX2X_FCOE=m
-CONFIG_BE2ISCSI=m
-CONFIG_BLK_DEV_3W_XXXX_RAID=m
-CONFIG_SCSI_HPSA=m
-CONFIG_SCSI_3W_9XXX=m
-CONFIG_SCSI_3W_SAS=m
-CONFIG_SCSI_ACARD=m
-CONFIG_SCSI_AACRAID=m
-CONFIG_SCSI_AIC7XXX=m
-CONFIG_AIC7XXX_CMDS_PER_DEVICE=253
-CONFIG_AIC7XXX_RESET_DELAY_MS=15000
-# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
-CONFIG_AIC7XXX_DEBUG_MASK=0
-CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
-CONFIG_SCSI_AIC79XX=m
-CONFIG_AIC79XX_CMDS_PER_DEVICE=32
-CONFIG_AIC79XX_RESET_DELAY_MS=15000
-# CONFIG_AIC79XX_DEBUG_ENABLE is not set
-CONFIG_AIC79XX_DEBUG_MASK=0
-CONFIG_AIC79XX_REG_PRETTY_PRINT=y
-CONFIG_SCSI_AIC94XX=m
-CONFIG_AIC94XX_DEBUG=y
-CONFIG_SCSI_MVSAS=m
-CONFIG_SCSI_MVSAS_DEBUG=y
-# CONFIG_SCSI_MVSAS_TASKLET is not set
-CONFIG_SCSI_MVUMI=m
-CONFIG_SCSI_DPT_I2O=m
-CONFIG_SCSI_ADVANSYS=m
-CONFIG_SCSI_ARCMSR=m
-CONFIG_SCSI_ESAS2R=m
-CONFIG_MEGARAID_NEWGEN=y
-CONFIG_MEGARAID_MM=m
-CONFIG_MEGARAID_MAILBOX=m
-CONFIG_MEGARAID_LEGACY=m
-CONFIG_MEGARAID_SAS=m
-CONFIG_SCSI_MPT3SAS=m
-CONFIG_SCSI_MPT2SAS_MAX_SGE=128
-CONFIG_SCSI_MPT3SAS_MAX_SGE=128
-CONFIG_SCSI_MPT2SAS=m
-CONFIG_SCSI_SMARTPQI=m
-CONFIG_SCSI_UFSHCD=m
-CONFIG_SCSI_UFSHCD_PCI=m
-CONFIG_SCSI_UFS_DWC_TC_PCI=m
-CONFIG_SCSI_UFSHCD_PLATFORM=m
-CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m
-CONFIG_SCSI_HPTIOP=m
-CONFIG_SCSI_BUSLOGIC=m
-CONFIG_SCSI_FLASHPOINT=y
-CONFIG_VMWARE_PVSCSI=m
-CONFIG_XEN_SCSI_FRONTEND=m
-CONFIG_HYPERV_STORAGE=m
-CONFIG_LIBFC=m
-CONFIG_LIBFCOE=m
-CONFIG_FCOE=m
-CONFIG_FCOE_FNIC=m
-# CONFIG_SCSI_SNIC is not set
-CONFIG_SCSI_DMX3191D=m
-CONFIG_SCSI_GDTH=m
-CONFIG_SCSI_ISCI=m
-CONFIG_SCSI_IPS=m
-CONFIG_SCSI_INITIO=m
-CONFIG_SCSI_INIA100=m
-CONFIG_SCSI_PPA=m
-CONFIG_SCSI_IMM=m
-# CONFIG_SCSI_IZIP_EPP16 is not set
-# CONFIG_SCSI_IZIP_SLOW_CTR is not set
-CONFIG_SCSI_STEX=m
-CONFIG_SCSI_SYM53C8XX_2=m
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_IPR=m
-# CONFIG_SCSI_IPR_TRACE is not set
-# CONFIG_SCSI_IPR_DUMP is not set
-CONFIG_SCSI_QLOGIC_1280=m
-CONFIG_SCSI_QLA_FC=m
-CONFIG_TCM_QLA2XXX=m
-# CONFIG_TCM_QLA2XXX_DEBUG is not set
-CONFIG_SCSI_QLA_ISCSI=m
-CONFIG_SCSI_LPFC=m
-# CONFIG_SCSI_LPFC_DEBUG_FS is not set
-CONFIG_SCSI_DC395x=m
-CONFIG_SCSI_AM53C974=m
-CONFIG_SCSI_WD719X=m
-# CONFIG_SCSI_DEBUG is not set
-CONFIG_SCSI_PMCRAID=m
-CONFIG_SCSI_PM8001=m
-CONFIG_SCSI_BFA_FC=m
-CONFIG_SCSI_VIRTIO=m
-CONFIG_SCSI_CHELSIO_FCOE=m
-CONFIG_SCSI_LOWLEVEL_PCMCIA=y
-CONFIG_PCMCIA_AHA152X=m
-CONFIG_PCMCIA_QLOGIC=m
-CONFIG_PCMCIA_SYM53C500=m
-CONFIG_SCSI_OSD_INITIATOR=m
-CONFIG_SCSI_OSD_ULD=m
-CONFIG_SCSI_OSD_DPRINT_SENSE=1
-# CONFIG_SCSI_OSD_DEBUG is not set
-CONFIG_SATA_ZPODD=y
-CONFIG_SATA_MOBILE_LPM_POLICY=3
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SATA_ACARD_AHCI=m
-CONFIG_SATA_SIL24=m
-CONFIG_PDC_ADMA=m
-CONFIG_SATA_QSTOR=m
-CONFIG_SATA_SX4=m
-CONFIG_ATA_PIIX=m
-CONFIG_SATA_DWC=m
-CONFIG_SATA_DWC_OLD_DMA=y
-# CONFIG_SATA_DWC_DEBUG is not set
-CONFIG_SATA_MV=m
-CONFIG_SATA_NV=m
-CONFIG_SATA_PROMISE=m
-CONFIG_SATA_SIL=y
-CONFIG_SATA_SIS=m
-CONFIG_SATA_SVW=m
-CONFIG_SATA_ULI=m
-CONFIG_SATA_VIA=m
-CONFIG_SATA_VITESSE=m
-CONFIG_PATA_ALI=m
-CONFIG_PATA_AMD=m
-CONFIG_PATA_ARTOP=m
-CONFIG_PATA_ATIIXP=m
-CONFIG_PATA_ATP867X=m
-CONFIG_PATA_CMD64X=m
-CONFIG_PATA_CYPRESS=m
-CONFIG_PATA_EFAR=m
-CONFIG_PATA_HPT366=m
-CONFIG_PATA_HPT37X=m
-CONFIG_PATA_HPT3X2N=m
-CONFIG_PATA_HPT3X3=m
-CONFIG_PATA_HPT3X3_DMA=y
-CONFIG_PATA_IT8213=m
-CONFIG_PATA_IT821X=m
-CONFIG_PATA_JMICRON=m
-CONFIG_PATA_MARVELL=m
-CONFIG_PATA_NETCELL=m
-CONFIG_PATA_NINJA32=m
-CONFIG_PATA_NS87415=m
-CONFIG_PATA_OLDPIIX=m
-CONFIG_PATA_OPTIDMA=m
-CONFIG_PATA_PDC2027X=m
-CONFIG_PATA_PDC_OLD=m
-CONFIG_PATA_RADISYS=m
-CONFIG_PATA_RDC=m
-CONFIG_PATA_SCH=m
-CONFIG_PATA_SERVERWORKS=m
-CONFIG_PATA_SIL680=m
-CONFIG_PATA_SIS=m
-CONFIG_PATA_TOSHIBA=m
-CONFIG_PATA_TRIFLEX=m
-CONFIG_PATA_VIA=m
-CONFIG_PATA_WINBOND=m
-CONFIG_PATA_CMD640_PCI=m
-CONFIG_PATA_MPIIX=m
-CONFIG_PATA_NS87410=m
-CONFIG_PATA_OPTI=m
-CONFIG_PATA_PCMCIA=m
-# CONFIG_PATA_PLATFORM is not set
-CONFIG_PATA_RZ1000=m
-CONFIG_PATA_ACPI=m
-CONFIG_ATA_GENERIC=m
-CONFIG_PATA_LEGACY=m
-# CONFIG_MD_AUTODETECT is not set
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID456=m
-CONFIG_MD_MULTIPATH=m
-CONFIG_MD_FAULTY=m
-CONFIG_MD_CLUSTER=m
-CONFIG_BCACHE=m
-# CONFIG_BCACHE_DEBUG is not set
-# CONFIG_BCACHE_CLOSURES_DEBUG is not set
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_MQ_DEFAULT=y
-CONFIG_DM_BUFIO=m
-# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
-CONFIG_DM_BIO_PRISON=m
-CONFIG_DM_PERSISTENT_DATA=m
-CONFIG_DM_UNSTRIPED=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_THIN_PROVISIONING=m
-CONFIG_DM_CACHE=m
-CONFIG_DM_CACHE_SMQ=m
-CONFIG_DM_WRITECACHE=m
-CONFIG_DM_ERA=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_LOG_USERSPACE=m
-CONFIG_DM_RAID=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_QL=m
-CONFIG_DM_MULTIPATH_ST=m
-CONFIG_DM_UEVENT=y
-CONFIG_DM_FLAKEY=m
-CONFIG_DM_VERITY=m
-# CONFIG_DM_VERITY_FEC is not set
-CONFIG_DM_SWITCH=m
-CONFIG_DM_LOG_WRITES=m
-CONFIG_DM_INTEGRITY=m
-CONFIG_DM_ZONED=m
-CONFIG_TARGET_CORE=m
-CONFIG_TCM_IBLOCK=m
-CONFIG_TCM_FILEIO=m
-CONFIG_TCM_PSCSI=m
-CONFIG_TCM_USER2=m
-CONFIG_LOOPBACK_TARGET=m
-CONFIG_TCM_FC=m
-CONFIG_ISCSI_TARGET=m
-CONFIG_ISCSI_TARGET_CXGB4=m
-CONFIG_SBP_TARGET=m
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=m
-CONFIG_FUSION_FC=m
-CONFIG_FUSION_SAS=m
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_CTL=m
-CONFIG_FUSION_LAN=m
-CONFIG_FUSION_LOGGING=y
-CONFIG_FIREWIRE=m
-CONFIG_FIREWIRE_OHCI=m
-CONFIG_FIREWIRE_SBP2=m
-CONFIG_FIREWIRE_NET=m
-CONFIG_FIREWIRE_NOSY=m
-CONFIG_MII=m
-CONFIG_BONDING=m
-CONFIG_DUMMY=m
-CONFIG_EQUALIZER=m
-CONFIG_NET_FC=y
-CONFIG_IFB=m
-CONFIG_NET_TEAM=m
-CONFIG_NET_TEAM_MODE_BROADCAST=m
-CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
-CONFIG_NET_TEAM_MODE_RANDOM=m
-CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
-CONFIG_NET_TEAM_MODE_LOADBALANCE=m
-CONFIG_MACVLAN=m
-CONFIG_MACVTAP=m
-CONFIG_IPVLAN=m
-CONFIG_IPVTAP=m
-CONFIG_VXLAN=m
-CONFIG_GENEVE=m
-CONFIG_GTP=m
-CONFIG_MACSEC=m
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_RIONET=m
-CONFIG_RIONET_TX_SIZE=128
-CONFIG_RIONET_RX_SIZE=128
-CONFIG_TUN=m
-CONFIG_TAP=m
-CONFIG_VETH=m
-CONFIG_VIRTIO_NET=m
-CONFIG_NLMON=m
-CONFIG_NET_VRF=m
-CONFIG_VSOCKMON=m
-CONFIG_SUNGEM_PHY=m
-CONFIG_ARCNET=m
-CONFIG_ARCNET_1201=m
-CONFIG_ARCNET_1051=m
-CONFIG_ARCNET_RAW=m
-CONFIG_ARCNET_CAP=m
-CONFIG_ARCNET_COM90xx=m
-CONFIG_ARCNET_COM90xxIO=m
-CONFIG_ARCNET_RIM_I=m
-CONFIG_ARCNET_COM20020=m
-CONFIG_ARCNET_COM20020_PCI=m
-CONFIG_ARCNET_COM20020_CS=m
-CONFIG_ATM_DRIVERS=y
-# CONFIG_ATM_DUMMY is not set
-CONFIG_ATM_TCP=m
-CONFIG_ATM_LANAI=m
-CONFIG_ATM_ENI=m
-# CONFIG_ATM_ENI_DEBUG is not set
-# CONFIG_ATM_ENI_TUNE_BURST is not set
-CONFIG_ATM_FIRESTREAM=m
-CONFIG_ATM_ZATM=m
-# CONFIG_ATM_ZATM_DEBUG is not set
-# CONFIG_ATM_NICSTAR is not set
-CONFIG_ATM_IDT77252=m
-# CONFIG_ATM_IDT77252_DEBUG is not set
-# CONFIG_ATM_IDT77252_RCV_ALL is not set
-CONFIG_ATM_IDT77252_USE_SUNI=y
-CONFIG_ATM_AMBASSADOR=m
-# CONFIG_ATM_AMBASSADOR_DEBUG is not set
-CONFIG_ATM_HORIZON=m
-# CONFIG_ATM_HORIZON_DEBUG is not set
-CONFIG_ATM_IA=m
-# CONFIG_ATM_IA_DEBUG is not set
-CONFIG_ATM_FORE200E=m
-CONFIG_ATM_FORE200E_USE_TASKLET=y
-CONFIG_ATM_FORE200E_TX_RETRY=16
-CONFIG_ATM_FORE200E_DEBUG=0
-CONFIG_ATM_HE=m
-CONFIG_ATM_HE_USE_SUNI=y
-CONFIG_ATM_SOLOS=m
-CONFIG_CAIF_TTY=m
-CONFIG_CAIF_SPI_SLAVE=m
-# CONFIG_CAIF_SPI_SYNC is not set
-CONFIG_CAIF_HSI=m
-CONFIG_CAIF_VIRTIO=m
-CONFIG_B53=m
-CONFIG_B53_SPI_DRIVER=m
-CONFIG_B53_MDIO_DRIVER=m
-CONFIG_B53_MMAP_DRIVER=m
-CONFIG_B53_SRAB_DRIVER=m
-CONFIG_B53_SERDES=m
-CONFIG_NET_DSA_BCM_SF2=m
-CONFIG_NET_DSA_LOOP=m
-CONFIG_NET_DSA_MT7530=m
-CONFIG_MICROCHIP_KSZ=m
-CONFIG_MICROCHIP_KSZ_SPI_DRIVER=m
-CONFIG_NET_DSA_MV88E6XXX=m
-CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
-CONFIG_NET_DSA_MV88E6XXX_PTP=y
-CONFIG_NET_DSA_QCA8K=m
-# CONFIG_NET_DSA_REALTEK_SMI is not set
-CONFIG_NET_DSA_SMSC_LAN9303=m
-CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
-CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
-CONFIG_MDIO=m
-CONFIG_PCMCIA_3C574=m
-CONFIG_PCMCIA_3C589=m
-CONFIG_VORTEX=m
-CONFIG_TYPHOON=m
-CONFIG_ADAPTEC_STARFIRE=m
-CONFIG_ET131X=m
-CONFIG_SLICOSS=m
-CONFIG_ACENIC=m
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
-CONFIG_ALTERA_TSE=m
-CONFIG_ENA_ETHERNET=m
-CONFIG_AMD8111_ETH=m
-CONFIG_PCNET32=m
-CONFIG_PCMCIA_NMCLAN=m
-CONFIG_AMD_XGBE=m
-CONFIG_AMD_XGBE_DCB=y
-CONFIG_AMD_XGBE_HAVE_ECC=y
-CONFIG_AQTION=m
-CONFIG_ATL2=m
-CONFIG_ATL1=m
-CONFIG_ATL1E=m
-CONFIG_ATL1C=m
-CONFIG_ALX=m
-# CONFIG_NET_VENDOR_AURORA is not set
-CONFIG_B44=m
-CONFIG_B44_PCI_AUTOSELECT=y
-CONFIG_B44_PCICORE_AUTOSELECT=y
-CONFIG_B44_PCI=y
-CONFIG_BCMGENET=m
-CONFIG_BNX2=m
-CONFIG_CNIC=m
-CONFIG_TIGON3=m
-CONFIG_BNX2X=m
-CONFIG_BNX2X_SRIOV=y
-CONFIG_BNXT=m
-CONFIG_BNXT_SRIOV=y
-CONFIG_BNXT_FLOWER_OFFLOAD=y
-CONFIG_BNXT_DCB=y
-CONFIG_BNXT_HWMON=y
-CONFIG_BNA=m
-CONFIG_CAVIUM_PTP=m
-CONFIG_LIQUIDIO_VF=m
-CONFIG_CHELSIO_T1=m
-CONFIG_CHELSIO_T1_1G=y
-CONFIG_CHELSIO_T3=m
-CONFIG_CHELSIO_T4=m
-CONFIG_CHELSIO_T4_DCB=y
-CONFIG_CHELSIO_T4_FCOE=y
-CONFIG_CHELSIO_T4VF=m
-CONFIG_CHELSIO_LIB=m
-CONFIG_ENIC=m
-CONFIG_CX_ECAT=m
-CONFIG_DE2104X=m
-CONFIG_DE2104X_DSL=0
-CONFIG_TULIP=m
-# CONFIG_TULIP_MWI is not set
-# CONFIG_TULIP_MMIO is not set
-# CONFIG_TULIP_NAPI is not set
-CONFIG_DE4X5=m
-CONFIG_WINBOND_840=m
-CONFIG_DM9102=m
-CONFIG_ULI526X=m
-CONFIG_PCMCIA_XIRCOM=m
-CONFIG_DL2K=m
-CONFIG_SUNDANCE=m
-# CONFIG_SUNDANCE_MMIO is not set
-CONFIG_BE2NET=m
-CONFIG_BE2NET_HWMON=y
-CONFIG_BE2NET_BE2=y
-CONFIG_BE2NET_BE3=y
-CONFIG_BE2NET_LANCER=y
-CONFIG_BE2NET_SKYHAWK=y
-CONFIG_PCMCIA_FMVJ18X=m
-CONFIG_HP100=m
-CONFIG_HINIC=m
-CONFIG_IGC=m
-CONFIG_E100=m
-CONFIG_E1000=m
-CONFIG_E1000E=m
-CONFIG_IGB=m
-CONFIG_IGB_HWMON=y
-CONFIG_IGB_DCA=y
-CONFIG_IGBVF=m
-CONFIG_IXGB=m
-CONFIG_IXGBE=m
-CONFIG_IXGBE_HWMON=y
-CONFIG_IXGBE_DCA=y
-CONFIG_IXGBE_DCB=y
-CONFIG_IXGBEVF=m
-CONFIG_I40E=m
-CONFIG_I40E_DCB=y
-CONFIG_I40EVF=m
-CONFIG_ICE=m
-CONFIG_FM10K=m
-CONFIG_JME=m
-CONFIG_MVMDIO=m
-CONFIG_SKGE=m
-# CONFIG_SKGE_DEBUG is not set
-CONFIG_SKGE_GENESIS=y
-CONFIG_SKY2=m
-CONFIG_MLX4_EN=m
-CONFIG_MLX4_EN_DCB=y
-CONFIG_MLX4_CORE=m
-# CONFIG_MLX4_DEBUG is not set
-CONFIG_MLX4_CORE_GEN2=y
-CONFIG_MLXFW=m
-CONFIG_KS8842=m
-CONFIG_KS8851=m
-CONFIG_KSZ884X_PCI=m
-CONFIG_NET_VENDOR_MICROCHIP=y
-CONFIG_ENC28J60=m
-# CONFIG_ENC28J60_WRITEVERIFY is not set
-# CONFIG_ENCX24J600 is not set
-CONFIG_LAN743X=m
-# CONFIG_MSCC_OCELOT_SWITCH is not set
-CONFIG_MYRI10GE=m
-CONFIG_MYRI10GE_DCA=y
-CONFIG_FEALNX=m
-CONFIG_NATSEMI=m
-CONFIG_NS83820=m
-CONFIG_S2IO=m
-CONFIG_VXGE=m
-# CONFIG_VXGE_DEBUG_TRACE_ALL is not set
-CONFIG_NFP=m
-CONFIG_NFP_APP_FLOWER=y
-CONFIG_NFP_APP_ABM_NIC=y
-# CONFIG_NFP_DEBUG is not set
-CONFIG_PCMCIA_AXNET=m
-CONFIG_NE2K_PCI=m
-CONFIG_PCMCIA_PCNET=m
-CONFIG_FORCEDETH=m
-CONFIG_ETHOC=m
-CONFIG_HAMACHI=m
-CONFIG_YELLOWFIN=m
-CONFIG_QLA3XXX=m
-CONFIG_QLCNIC=m
-CONFIG_QLCNIC_SRIOV=y
-CONFIG_QLCNIC_DCB=y
-CONFIG_QLCNIC_HWMON=y
-CONFIG_QLGE=m
-CONFIG_NETXEN_NIC=m
-CONFIG_QCOM_EMAC=m
-CONFIG_RMNET=m
-CONFIG_R6040=m
-CONFIG_ATP=m
-CONFIG_8139CP=m
-CONFIG_8139TOO=m
-# CONFIG_8139TOO_PIO is not set
-CONFIG_8139TOO_8129=y
-CONFIG_R8169=m
-CONFIG_ROCKER=m
-CONFIG_SXGBE_ETH=m
-CONFIG_SFC=m
-CONFIG_SFC_MTD=y
-CONFIG_SFC_MCDI_MON=y
-CONFIG_SFC_SRIOV=y
-CONFIG_SFC_MCDI_LOGGING=y
-CONFIG_SFC_FALCON=m
-CONFIG_SFC_FALCON_MTD=y
-CONFIG_SC92031=m
-CONFIG_SIS900=m
-CONFIG_SIS190=m
-CONFIG_PCMCIA_SMC91C92=m
-CONFIG_EPIC100=m
-CONFIG_SMSC911X=m
-CONFIG_SMSC9420=m
-CONFIG_STMMAC_ETH=m
-CONFIG_STMMAC_PLATFORM=m
-CONFIG_DWMAC_GENERIC=m
-# CONFIG_STMMAC_PCI is not set
-CONFIG_HAPPYMEAL=m
-CONFIG_SUNGEM=m
-CONFIG_CASSINI=m
-CONFIG_NIU=m
-CONFIG_DWC_XLGMAC=m
-CONFIG_DWC_XLGMAC_PCI=m
-CONFIG_TEHUTI=m
-CONFIG_TLAN=m
-CONFIG_VIA_RHINE=m
-# CONFIG_VIA_RHINE_MMIO is not set
-CONFIG_VIA_VELOCITY=m
-CONFIG_WIZNET_W5100=m
-CONFIG_WIZNET_W5300=m
-# CONFIG_WIZNET_BUS_DIRECT is not set
-# CONFIG_WIZNET_BUS_INDIRECT is not set
-CONFIG_WIZNET_BUS_ANY=y
-CONFIG_WIZNET_W5100_SPI=m
-CONFIG_PCMCIA_XIRC2PS=m
-CONFIG_DEFXX=m
-# CONFIG_DEFXX_MMIO is not set
-CONFIG_SKFP=m
-CONFIG_NET_SB1000=m
-CONFIG_MDIO_DEVICE=m
-CONFIG_MDIO_BUS=m
-CONFIG_MDIO_BCM_UNIMAC=m
-CONFIG_MDIO_BITBANG=m
-CONFIG_MDIO_CAVIUM=m
-CONFIG_MDIO_GPIO=m
-CONFIG_MDIO_THUNDER=m
-CONFIG_PHYLINK=m
-CONFIG_PHYLIB=m
-CONFIG_SWPHY=y
-CONFIG_LED_TRIGGER_PHY=y
-# CONFIG_SFP is not set
-CONFIG_AMD_PHY=m
-CONFIG_AT803X_PHY=m
-CONFIG_BCM7XXX_PHY=m
-CONFIG_BCM87XX_PHY=m
-CONFIG_BCM_NET_PHYLIB=m
-CONFIG_BROADCOM_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_CORTINA_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_DP83822_PHY=m
-CONFIG_FIXED_PHY=m
-CONFIG_ICPLUS_PHY=m
-CONFIG_INTEL_XWAY_PHY=m
-CONFIG_LSI_ET1011C_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_MARVELL_PHY=m
-CONFIG_MARVELL_10G_PHY=m
-CONFIG_MICREL_PHY=m
-CONFIG_MICROSEMI_PHY=m
-CONFIG_NATIONAL_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_REALTEK_PHY=m
-CONFIG_RENESAS_PHY=m
-CONFIG_ROCKCHIP_PHY=m
-CONFIG_SMSC_PHY=m
-CONFIG_STE10XP=m
-CONFIG_VITESSE_PHY=m
-CONFIG_XILINX_GMII2RGMII=m
-CONFIG_MICREL_KS8995MA=m
-CONFIG_PLIP=m
-CONFIG_PPP=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_MPPE=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPPOATM=m
-CONFIG_PPPOE=m
-CONFIG_PPTP=m
-CONFIG_PPPOL2TP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_SLIP=m
-CONFIG_SLHC=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-
-#
-# Host-side USB support is needed for USB Network Adapter support
-#
-CONFIG_USB_NET_DRIVERS=m
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_RTL8152=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_AX8817X=m
-CONFIG_USB_NET_AX88179_178A=m
-CONFIG_USB_NET_CDCETHER=m
-CONFIG_USB_NET_CDC_EEM=m
-CONFIG_USB_NET_CDC_NCM=m
-CONFIG_USB_NET_HUAWEI_CDC_NCM=m
-CONFIG_USB_NET_CDC_MBIM=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_SR9700=m
-CONFIG_USB_NET_SR9800=m
-CONFIG_USB_NET_SMSC75XX=m
-CONFIG_USB_NET_SMSC95XX=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_NET1080=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_MCS7830=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
-CONFIG_USB_NET_CDC_SUBSET=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_BELKIN=y
-CONFIG_USB_ARMLINUX=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-CONFIG_USB_NET_ZAURUS=m
-CONFIG_USB_NET_CX82310_ETH=m
-CONFIG_USB_NET_KALMIA=m
-CONFIG_USB_NET_QMI_WWAN=m
-CONFIG_USB_HSO=m
-CONFIG_USB_NET_INT51X1=m
-CONFIG_USB_CDC_PHONET=m
-CONFIG_USB_IPHETH=m
-CONFIG_USB_SIERRA_NET=m
-CONFIG_USB_VL600=m
-# CONFIG_USB_NET_CH9200 is not set
-# CONFIG_WIRELESS_WDS is not set
-CONFIG_ADM8211=m
-CONFIG_ATH_COMMON=m
-CONFIG_ATH5K=m
-# CONFIG_ATH5K_DEBUG is not set
-# CONFIG_ATH5K_TRACER is not set
-CONFIG_ATH5K_PCI=y
-CONFIG_ATH9K_HW=m
-CONFIG_ATH9K_COMMON=m
-CONFIG_ATH9K_BTCOEX_SUPPORT=y
-CONFIG_ATH9K=m
-CONFIG_ATH9K_PCI=y
-CONFIG_ATH9K_AHB=y
-# CONFIG_ATH9K_DEBUGFS is not set
-# CONFIG_ATH9K_DYNACK is not set
-CONFIG_ATH9K_WOW=y
-CONFIG_ATH9K_RFKILL=y
-# CONFIG_ATH9K_CHANNEL_CONTEXT is not set
-CONFIG_ATH9K_PCOEM=y
-CONFIG_ATH9K_HTC=m
-# CONFIG_ATH9K_HTC_DEBUGFS is not set
-CONFIG_ATH9K_HWRNG=y
-CONFIG_CARL9170=m
-CONFIG_CARL9170_LEDS=y
-CONFIG_CARL9170_WPC=y
-CONFIG_CARL9170_HWRNG=y
-CONFIG_ATH6KL=m
-CONFIG_ATH6KL_SDIO=m
-CONFIG_ATH6KL_USB=m
-# CONFIG_ATH6KL_DEBUG is not set
-# CONFIG_ATH6KL_TRACING is not set
-CONFIG_AR5523=m
-CONFIG_WIL6210=m
-CONFIG_WIL6210_ISR_COR=y
-CONFIG_WIL6210_TRACING=y
-# CONFIG_WIL6210_DEBUGFS is not set
-CONFIG_ATH10K=m
-CONFIG_ATH10K_CE=y
-CONFIG_ATH10K_PCI=m
-CONFIG_ATH10K_SDIO=m
-CONFIG_ATH10K_USB=m
-# CONFIG_ATH10K_DEBUG is not set
-# CONFIG_ATH10K_DEBUGFS is not set
-# CONFIG_ATH10K_TRACING is not set
-CONFIG_WCN36XX=m
-# CONFIG_WCN36XX_DEBUGFS is not set
-CONFIG_ATMEL=m
-CONFIG_PCI_ATMEL=m
-CONFIG_PCMCIA_ATMEL=m
-CONFIG_AT76C50X_USB=m
-CONFIG_B43=m
-CONFIG_B43_BCMA=y
-CONFIG_B43_SSB=y
-CONFIG_B43_BUSES_BCMA_AND_SSB=y
-# CONFIG_B43_BUSES_BCMA is not set
-# CONFIG_B43_BUSES_SSB is not set
-CONFIG_B43_PCI_AUTOSELECT=y
-CONFIG_B43_PCICORE_AUTOSELECT=y
-CONFIG_B43_SDIO=y
-CONFIG_B43_BCMA_PIO=y
-CONFIG_B43_PIO=y
-CONFIG_B43_PHY_G=y
-CONFIG_B43_PHY_N=y
-CONFIG_B43_PHY_LP=y
-CONFIG_B43_PHY_HT=y
-CONFIG_B43_LEDS=y
-CONFIG_B43_HWRNG=y
-# CONFIG_B43_DEBUG is not set
-CONFIG_B43LEGACY=m
-CONFIG_B43LEGACY_PCI_AUTOSELECT=y
-CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
-CONFIG_B43LEGACY_LEDS=y
-CONFIG_B43LEGACY_HWRNG=y
-# CONFIG_B43LEGACY_DEBUG is not set
-CONFIG_B43LEGACY_DMA=y
-CONFIG_B43LEGACY_PIO=y
-CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
-# CONFIG_B43LEGACY_DMA_MODE is not set
-# CONFIG_B43LEGACY_PIO_MODE is not set
-CONFIG_BRCMUTIL=m
-CONFIG_BRCMSMAC=m
-CONFIG_BRCMFMAC=m
-CONFIG_BRCMFMAC_PROTO_BCDC=y
-CONFIG_BRCMFMAC_PROTO_MSGBUF=y
-CONFIG_BRCMFMAC_SDIO=y
-CONFIG_BRCMFMAC_USB=y
-CONFIG_BRCMFMAC_PCIE=y
-# CONFIG_BRCM_TRACING is not set
-# CONFIG_BRCMDBG is not set
-CONFIG_AIRO=m
-CONFIG_AIRO_CS=m
-CONFIG_IPW2100=m
-CONFIG_IPW2100_MONITOR=y
-# CONFIG_IPW2100_DEBUG is not set
-CONFIG_IPW2200=m
-CONFIG_IPW2200_MONITOR=y
-CONFIG_IPW2200_RADIOTAP=y
-CONFIG_IPW2200_PROMISCUOUS=y
-CONFIG_IPW2200_QOS=y
-# CONFIG_IPW2200_DEBUG is not set
-CONFIG_LIBIPW=m
-# CONFIG_LIBIPW_DEBUG is not set
-CONFIG_IWLEGACY=m
-CONFIG_IWL4965=m
-CONFIG_IWL3945=m
-CONFIG_RTL8723DE=m
-CONFIG_RTL8821CE=m
-
-#
-# iwl3945 / iwl4965 Debugging Options
-#
-# CONFIG_IWLEGACY_DEBUG is not set
-CONFIG_IWLWIFI=m
-CONFIG_IWLWIFI_LEDS=y
-CONFIG_IWLDVM=m
-CONFIG_IWLMVM=m
-CONFIG_IWLWIFI_OPMODE_MODULAR=y
-# CONFIG_IWLWIFI_BCAST_FILTERING is not set
-CONFIG_IWLWIFI_PCIE_RTPM=y
-
-#
-# Debugging Options
-#
-# CONFIG_IWLWIFI_DEBUG is not set
-# CONFIG_IWLWIFI_DEVICE_TRACING is not set
-CONFIG_HOSTAP=m
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_HOSTAP_PLX=m
-CONFIG_HOSTAP_PCI=m
-CONFIG_HOSTAP_CS=m
-CONFIG_HERMES=m
-CONFIG_HERMES_PRISM=y
-CONFIG_HERMES_CACHE_FW_ON_INIT=y
-CONFIG_PLX_HERMES=m
-CONFIG_TMD_HERMES=m
-CONFIG_NORTEL_HERMES=m
-CONFIG_PCI_HERMES=m
-CONFIG_PCMCIA_HERMES=m
-CONFIG_PCMCIA_SPECTRUM=m
-CONFIG_ORINOCO_USB=m
-CONFIG_P54_COMMON=m
-CONFIG_P54_USB=m
-CONFIG_P54_PCI=m
-CONFIG_P54_SPI=m
-CONFIG_P54_SPI_DEFAULT_EEPROM=y
-CONFIG_P54_LEDS=y
-CONFIG_PRISM54=m
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_USB=m
-CONFIG_LIBERTAS_CS=m
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_LIBERTAS_SPI=m
-# CONFIG_LIBERTAS_DEBUG is not set
-CONFIG_LIBERTAS_MESH=y
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
-CONFIG_MWIFIEX_PCIE=m
-CONFIG_MWIFIEX_USB=m
-CONFIG_MWL8K=m
-CONFIG_MT76_CORE=m
-CONFIG_MT76x2_COMMON=m
-CONFIG_MT76x2E=m
-CONFIG_MT7601U=m
-CONFIG_RT2X00=m
-CONFIG_RT2400PCI=m
-CONFIG_RT2500PCI=m
-CONFIG_RT61PCI=m
-CONFIG_RT2800PCI=m
-CONFIG_RT2800PCI_RT33XX=y
-CONFIG_RT2800PCI_RT35XX=y
-CONFIG_RT2800PCI_RT53XX=y
-CONFIG_RT2800PCI_RT3290=y
-CONFIG_RT2500USB=m
-CONFIG_RT73USB=m
-CONFIG_RT2800USB=m
-CONFIG_RT2800USB_RT33XX=y
-CONFIG_RT2800USB_RT35XX=y
-CONFIG_RT2800USB_RT3573=y
-CONFIG_RT2800USB_RT53XX=y
-CONFIG_RT2800USB_RT55XX=y
-CONFIG_RT2800USB_UNKNOWN=y
-CONFIG_RT2800_LIB=m
-CONFIG_RT2800_LIB_MMIO=m
-CONFIG_RT2X00_LIB_MMIO=m
-CONFIG_RT2X00_LIB_PCI=m
-CONFIG_RT2X00_LIB_USB=m
-CONFIG_RT2X00_LIB=m
-CONFIG_RT2X00_LIB_FIRMWARE=y
-CONFIG_RT2X00_LIB_CRYPTO=y
-CONFIG_RT2X00_LIB_LEDS=y
-# CONFIG_RT2X00_DEBUG is not set
-CONFIG_RTL8180=m
-CONFIG_RTL8187=m
-CONFIG_RTL8187_LEDS=y
-CONFIG_RTL_CARDS=m
-CONFIG_RTL8192CE=m
-CONFIG_RTL8192SE=m
-CONFIG_RTL8192DE=m
-CONFIG_RTL8723AE=m
-CONFIG_RTL8723BE=m
-CONFIG_RTL8188EE=m
-CONFIG_RTL8192EE=m
-CONFIG_RTL8821AE=m
-CONFIG_RTL8192CU=m
-CONFIG_RTLWIFI=m
-CONFIG_RTLWIFI_PCI=m
-CONFIG_RTLWIFI_USB=m
-# CONFIG_RTLWIFI_DEBUG is not set
-CONFIG_RTL8192C_COMMON=m
-CONFIG_RTL8723_COMMON=m
-CONFIG_RTLBTCOEXIST=m
-CONFIG_RSI_91X=m
-CONFIG_RSI_DEBUGFS=y
-CONFIG_RSI_SDIO=m
-CONFIG_RSI_USB=m
-CONFIG_RSI_COEX=y
-CONFIG_CW1200=m
-CONFIG_CW1200_WLAN_SDIO=m
-CONFIG_CW1200_WLAN_SPI=m
-CONFIG_WL1251=m
-CONFIG_WL1251_SPI=m
-CONFIG_WL1251_SDIO=m
-CONFIG_WL12XX=m
-CONFIG_WL18XX=m
-CONFIG_WLCORE=m
-CONFIG_WLCORE_SDIO=m
-CONFIG_WILINK_PLATFORM_DATA=y
-CONFIG_USB_ZD1201=m
-CONFIG_ZD1211RW=m
-# CONFIG_ZD1211RW_DEBUG is not set
-CONFIG_QTNFMAC=m
-CONFIG_QTNFMAC_PEARL_PCIE=m
-CONFIG_PCMCIA_RAYCS=m
-CONFIG_PCMCIA_WL3501=m
-CONFIG_MAC80211_HWSIM=m
-CONFIG_USB_NET_RNDIS_WLAN=m
-
-#
-# WiMAX Wireless Broadband devices
-#
-CONFIG_WIMAX_I2400M=m
-CONFIG_WIMAX_I2400M_USB=m
-CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8
-CONFIG_WAN=y
-CONFIG_LANMEDIA=m
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_PCI200SYN=m
-CONFIG_WANXL=m
-CONFIG_PC300TOO=m
-CONFIG_FARSYNC=m
-CONFIG_DSCC4=m
-# CONFIG_DSCC4_PCISYNC is not set
-# CONFIG_DSCC4_PCI_RST is not set
-CONFIG_DLCI=m
-CONFIG_DLCI_MAX=8
-CONFIG_LAPBETHER=m
-CONFIG_X25_ASY=m
-CONFIG_SBNI=m
-CONFIG_SBNI_MULTILINE=y
-CONFIG_IEEE802154_DRIVERS=m
-CONFIG_IEEE802154_FAKELB=m
-CONFIG_IEEE802154_AT86RF230=m
-# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set
-CONFIG_IEEE802154_MRF24J40=m
-CONFIG_IEEE802154_CC2520=m
-# CONFIG_IEEE802154_ATUSB is not set
-# CONFIG_IEEE802154_ADF7242 is not set
-CONFIG_IEEE802154_CA8210=m
-CONFIG_IEEE802154_CA8210_DEBUGFS=y
-CONFIG_IEEE802154_MCR20A=m
-# CONFIG_IEEE802154_HWSIM is not set
-CONFIG_XEN_NETDEV_FRONTEND=m
-CONFIG_XEN_NETDEV_BACKEND=m
-CONFIG_VMXNET3=m
-CONFIG_THUNDERBOLT_NET=m
-CONFIG_HYPERV_NET=m
-CONFIG_NETDEVSIM=m
-CONFIG_NET_FAILOVER=m
-CONFIG_ISDN=y
-CONFIG_ISDN_I4L=m
-CONFIG_ISDN_PPP=y
-CONFIG_ISDN_PPP_VJ=y
-CONFIG_ISDN_MPP=y
-# CONFIG_IPPP_FILTER is not set
-CONFIG_ISDN_PPP_BSDCOMP=m
-CONFIG_ISDN_AUDIO=y
-CONFIG_ISDN_TTY_FAX=y
-# CONFIG_ISDN_X25 is not set
-
-#
-# ISDN feature submodules
-#
-CONFIG_ISDN_DIVERSION=m
-
-#
-# ISDN4Linux hardware drivers
-#
-
-#
-# Passive cards
-#
-CONFIG_ISDN_DRV_HISAX=m
-
-#
-# D-channel protocol features
-#
-CONFIG_HISAX_EURO=y
-CONFIG_DE_AOC=y
-# CONFIG_HISAX_NO_SENDCOMPLETE is not set
-# CONFIG_HISAX_NO_LLC is not set
-# CONFIG_HISAX_NO_KEYPAD is not set
-CONFIG_HISAX_1TR6=y
-CONFIG_HISAX_NI1=y
-CONFIG_HISAX_MAX_CARDS=8
-
-#
-# HiSax supported cards
-#
-CONFIG_HISAX_16_3=y
-CONFIG_HISAX_TELESPCI=y
-CONFIG_HISAX_S0BOX=y
-CONFIG_HISAX_FRITZPCI=y
-CONFIG_HISAX_AVM_A1_PCMCIA=y
-CONFIG_HISAX_ELSA=y
-CONFIG_HISAX_DIEHLDIVA=y
-CONFIG_HISAX_SEDLBAUER=y
-CONFIG_HISAX_NETJET=y
-CONFIG_HISAX_NETJET_U=y
-CONFIG_HISAX_NICCY=y
-CONFIG_HISAX_BKM_A4T=y
-CONFIG_HISAX_SCT_QUADRO=y
-CONFIG_HISAX_GAZEL=y
-CONFIG_HISAX_HFC_PCI=y
-CONFIG_HISAX_W6692=y
-CONFIG_HISAX_HFC_SX=y
-CONFIG_HISAX_ENTERNOW_PCI=y
-# CONFIG_HISAX_DEBUG is not set
-
-#
-# HiSax PCMCIA card service modules
-#
-CONFIG_HISAX_SEDLBAUER_CS=m
-CONFIG_HISAX_ELSA_CS=m
-CONFIG_HISAX_AVM_A1_CS=m
-CONFIG_HISAX_TELES_CS=m
-
-#
-# HiSax sub driver modules
-#
-CONFIG_HISAX_ST5481=m
-CONFIG_HISAX_HFCUSB=m
-CONFIG_HISAX_HFC4S8S=m
-CONFIG_HISAX_FRITZ_PCIPNP=m
-CONFIG_ISDN_CAPI=Y
-# CONFIG_CAPI_TRACE is not set
-CONFIG_ISDN_CAPI_CAPI20=m
-CONFIG_ISDN_CAPI_MIDDLEWARE=y
-CONFIG_ISDN_CAPI_CAPIDRV=m
-# CONFIG_ISDN_CAPI_CAPIDRV_VERBOSE is not set
-
-#
-# CAPI hardware drivers
-#
-CONFIG_CAPI_AVM=y
-CONFIG_ISDN_DRV_AVMB1_B1PCI=m
-# CONFIG_ISDN_DRV_AVMB1_B1PCIV4 is not set
-CONFIG_ISDN_DRV_AVMB1_B1PCMCIA=m
-CONFIG_ISDN_DRV_AVMB1_AVM_CS=m
-CONFIG_ISDN_DRV_AVMB1_T1PCI=m
-CONFIG_ISDN_DRV_AVMB1_C4=m
-CONFIG_CAPI_EICON=y
-CONFIG_ISDN_DIVAS=m
-CONFIG_ISDN_DIVAS_BRIPCI=y
-CONFIG_ISDN_DIVAS_PRIPCI=y
-CONFIG_ISDN_DIVAS_DIVACAPI=m
-CONFIG_ISDN_DIVAS_USERIDI=m
-CONFIG_ISDN_DIVAS_MAINT=m
-CONFIG_ISDN_DRV_GIGASET=m
-CONFIG_GIGASET_CAPI=y
-CONFIG_GIGASET_BASE=m
-CONFIG_GIGASET_M105=m
-CONFIG_GIGASET_M101=m
-# CONFIG_GIGASET_DEBUG is not set
-CONFIG_HYSDN=m
-CONFIG_HYSDN_CAPI=y
-CONFIG_MISDN=m
-CONFIG_MISDN_DSP=m
-CONFIG_MISDN_L1OIP=m
-
-#
-# mISDN hardware drivers
-#
-CONFIG_MISDN_HFCPCI=m
-CONFIG_MISDN_HFCMULTI=m
-CONFIG_MISDN_HFCUSB=m
-CONFIG_MISDN_AVMFRITZ=m
-CONFIG_MISDN_SPEEDFAX=m
-CONFIG_MISDN_INFINEON=m
-CONFIG_MISDN_W6692=m
-CONFIG_MISDN_NETJET=m
-CONFIG_MISDN_IPAC=m
-CONFIG_MISDN_ISAR=m
-CONFIG_ISDN_HDLC=m
-CONFIG_INPUT_FF_MEMLESS=m
-CONFIG_INPUT_POLLDEV=m
-CONFIG_INPUT_SPARSEKMAP=m
-CONFIG_INPUT_MATRIXKMAP=m
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=m
-CONFIG_KEYBOARD_ADC=m
-CONFIG_KEYBOARD_ADP5520=m
-CONFIG_KEYBOARD_QT2160=m
-CONFIG_KEYBOARD_DLINK_DIR685=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_GPIO=m
-CONFIG_KEYBOARD_GPIO_POLLED=m
-CONFIG_KEYBOARD_TCA6416=m
-CONFIG_KEYBOARD_TCA8418=m
-# CONFIG_KEYBOARD_MATRIX is not set
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_SAMSUNG=m
-CONFIG_KEYBOARD_STOWAWAY=m
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_TM2_TOUCHKEY=m
-CONFIG_KEYBOARD_TWL4030=m
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_KEYBOARD_CROS_EC=m
-CONFIG_MOUSE_PS2_ELANTECH=y
-CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
-CONFIG_MOUSE_PS2_SENTELIC=y
-CONFIG_MOUSE_PS2_TOUCHKIT=y
-CONFIG_MOUSE_PS2_VMMOUSE=y
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_APPLETOUCH=m
-CONFIG_MOUSE_BCM5974=m
-CONFIG_MOUSE_CYAPA=m
-CONFIG_MOUSE_ELAN_I2C=m
-CONFIG_MOUSE_ELAN_I2C_I2C=y
-CONFIG_MOUSE_ELAN_I2C_SMBUS=y
-CONFIG_MOUSE_VSXXXAA=m
-# CONFIG_MOUSE_GPIO is not set
-CONFIG_MOUSE_SYNAPTICS_I2C=m
-CONFIG_MOUSE_SYNAPTICS_USB=m
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=y
-CONFIG_JOYSTICK_IFORCE_232=y
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_TWIDJOY=m
-CONFIG_JOYSTICK_ZHENHUA=m
-CONFIG_JOYSTICK_DB9=m
-CONFIG_JOYSTICK_GAMECON=m
-CONFIG_JOYSTICK_TURBOGRAFX=m
-CONFIG_JOYSTICK_AS5011=m
-CONFIG_JOYSTICK_JOYDUMP=m
-CONFIG_JOYSTICK_XPAD=m
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_JOYSTICK_WALKERA0701=m
-CONFIG_JOYSTICK_PSXPAD_SPI=m
-CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
-CONFIG_JOYSTICK_PXRC=m
-CONFIG_TABLET_USB_ACECAD=m
-CONFIG_TABLET_USB_AIPTEK=m
-CONFIG_TABLET_USB_GTCO=m
-CONFIG_TABLET_USB_HANWANG=m
-CONFIG_TABLET_USB_KBTAB=m
-CONFIG_TABLET_USB_PEGASUS=m
-CONFIG_TABLET_SERIAL_WACOM4=m
-CONFIG_TOUCHSCREEN_88PM860X=m
-CONFIG_TOUCHSCREEN_ADS7846=m
-CONFIG_TOUCHSCREEN_AD7877=m
-CONFIG_TOUCHSCREEN_AD7879=m
-CONFIG_TOUCHSCREEN_AD7879_I2C=m
-CONFIG_TOUCHSCREEN_AD7879_SPI=m
-# CONFIG_TOUCHSCREEN_ADC is not set
-CONFIG_TOUCHSCREEN_ATMEL_MXT=m
-CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y
-CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
-CONFIG_TOUCHSCREEN_BU21013=m
-CONFIG_TOUCHSCREEN_CY8CTMG110=m
-CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
-CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
-CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
-CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
-CONFIG_TOUCHSCREEN_DA9034=m
-CONFIG_TOUCHSCREEN_DA9052=m
-CONFIG_TOUCHSCREEN_DYNAPRO=m
-CONFIG_TOUCHSCREEN_HAMPSHIRE=m
-CONFIG_TOUCHSCREEN_EETI=m
-CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
-CONFIG_TOUCHSCREEN_EXC3000=m
-CONFIG_TOUCHSCREEN_FUJITSU=m
-CONFIG_TOUCHSCREEN_GOODIX=m
-CONFIG_TOUCHSCREEN_HIDEEP=m
-CONFIG_TOUCHSCREEN_ILI210X=m
-CONFIG_TOUCHSCREEN_S6SY761=m
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_TOUCHSCREEN_EKTF2127=m
-CONFIG_TOUCHSCREEN_ELAN=m
-CONFIG_TOUCHSCREEN_ELO=m
-CONFIG_TOUCHSCREEN_WACOM_W8001=m
-CONFIG_TOUCHSCREEN_WACOM_I2C=m
-CONFIG_TOUCHSCREEN_MAX11801=m
-CONFIG_TOUCHSCREEN_MCS5000=m
-CONFIG_TOUCHSCREEN_MMS114=m
-CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
-CONFIG_TOUCHSCREEN_MTOUCH=m
-CONFIG_TOUCHSCREEN_INEXIO=m
-CONFIG_TOUCHSCREEN_MK712=m
-CONFIG_TOUCHSCREEN_PENMOUNT=m
-CONFIG_TOUCHSCREEN_EDT_FT5X06=m
-CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
-CONFIG_TOUCHSCREEN_TOUCHWIN=m
-CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m
-CONFIG_TOUCHSCREEN_PIXCIR=m
-CONFIG_TOUCHSCREEN_WM831X=m
-CONFIG_TOUCHSCREEN_WM97XX=m
-CONFIG_TOUCHSCREEN_WM9705=y
-CONFIG_TOUCHSCREEN_WM9712=y
-CONFIG_TOUCHSCREEN_WM9713=y
-CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-CONFIG_TOUCHSCREEN_MC13783=m
-CONFIG_TOUCHSCREEN_USB_EGALAX=y
-CONFIG_TOUCHSCREEN_USB_PANJIT=y
-CONFIG_TOUCHSCREEN_USB_3M=y
-CONFIG_TOUCHSCREEN_USB_ITM=y
-CONFIG_TOUCHSCREEN_USB_ETURBO=y
-CONFIG_TOUCHSCREEN_USB_GUNZE=y
-CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
-CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
-CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
-CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
-CONFIG_TOUCHSCREEN_USB_GOTOP=y
-CONFIG_TOUCHSCREEN_USB_JASTEC=y
-CONFIG_TOUCHSCREEN_USB_ELO=y
-CONFIG_TOUCHSCREEN_USB_E2I=y
-CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
-CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
-CONFIG_TOUCHSCREEN_USB_NEXIO=y
-CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
-CONFIG_TOUCHSCREEN_TOUCHIT213=m
-CONFIG_TOUCHSCREEN_TSC_SERIO=m
-CONFIG_TOUCHSCREEN_TSC200X_CORE=m
-CONFIG_TOUCHSCREEN_TSC2004=m
-CONFIG_TOUCHSCREEN_TSC2005=m
-CONFIG_TOUCHSCREEN_TSC2007=m
-CONFIG_TOUCHSCREEN_TSC2007_IIO=y
-CONFIG_TOUCHSCREEN_PCAP=m
-CONFIG_TOUCHSCREEN_RM_TS=m
-CONFIG_TOUCHSCREEN_SILEAD=m
-CONFIG_TOUCHSCREEN_SIS_I2C=m
-CONFIG_TOUCHSCREEN_ST1232=m
-CONFIG_TOUCHSCREEN_STMFTS=m
-CONFIG_TOUCHSCREEN_SUR40=m
-CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
-CONFIG_TOUCHSCREEN_SX8654=m
-CONFIG_TOUCHSCREEN_TPS6507X=m
-CONFIG_TOUCHSCREEN_ZET6223=m
-CONFIG_TOUCHSCREEN_ZFORCE=m
-CONFIG_TOUCHSCREEN_ROHM_BU21023=m
-CONFIG_INPUT_88PM860X_ONKEY=m
-CONFIG_INPUT_88PM80X_ONKEY=m
-CONFIG_INPUT_AD714X=m
-CONFIG_INPUT_AD714X_I2C=m
-CONFIG_INPUT_AD714X_SPI=m
-CONFIG_INPUT_ARIZONA_HAPTICS=m
-CONFIG_INPUT_BMA150=m
-CONFIG_INPUT_PCSPKR=m
-CONFIG_INPUT_MAX77693_HAPTIC=m
-CONFIG_INPUT_MAX8925_ONKEY=m
-CONFIG_INPUT_MAX8997_HAPTIC=m
-CONFIG_INPUT_MC13783_PWRBUTTON=m
-CONFIG_INPUT_APANEL=m
-CONFIG_INPUT_GP2A=m
-CONFIG_INPUT_GPIO_BEEPER=m
-CONFIG_INPUT_GPIO_DECODER=m
-CONFIG_INPUT_ATLAS_BTNS=m
-CONFIG_INPUT_ATI_REMOTE2=m
-CONFIG_INPUT_KEYSPAN_REMOTE=m
-CONFIG_INPUT_POWERMATE=m
-CONFIG_INPUT_YEALINK=m
-CONFIG_INPUT_CM109=m
-CONFIG_INPUT_REGULATOR_HAPTIC=m
-CONFIG_INPUT_RETU_PWRBUTTON=m
-# CONFIG_INPUT_AXP20X_PEK is not set
-CONFIG_INPUT_TWL4030_PWRBUTTON=m
-CONFIG_INPUT_TWL4030_VIBRA=m
-CONFIG_INPUT_TWL6040_VIBRA=m
-CONFIG_INPUT_UINPUT=m
-CONFIG_INPUT_PALMAS_PWRBUTTON=m
-CONFIG_INPUT_PCF8574=m
-CONFIG_INPUT_PWM_BEEPER=m
-CONFIG_INPUT_PWM_VIBRA=m
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-CONFIG_INPUT_DA9052_ONKEY=m
-CONFIG_INPUT_DA9055_ONKEY=m
-# CONFIG_INPUT_DA9063_ONKEY is not set
-CONFIG_INPUT_WM831X_ON=m
-CONFIG_INPUT_PCAP=m
-CONFIG_INPUT_IMS_PCU=m
-CONFIG_INPUT_CMA3000=m
-CONFIG_INPUT_CMA3000_I2C=m
-CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
-CONFIG_INPUT_IDEAPAD_SLIDEBAR=m
-CONFIG_INPUT_SOC_BUTTON_ARRAY=m
-CONFIG_INPUT_DRV260X_HAPTICS=m
-CONFIG_INPUT_DRV2667_HAPTICS=m
-CONFIG_INPUT_RAVE_SP_PWRBUTTON=m
-CONFIG_RMI4_CORE=m
-CONFIG_RMI4_I2C=m
-CONFIG_RMI4_SPI=m
-CONFIG_RMI4_SMB=m
-CONFIG_RMI4_F03=y
-CONFIG_RMI4_F03_SERIO=m
-CONFIG_RMI4_2D_SENSOR=y
-CONFIG_RMI4_F11=y
-CONFIG_RMI4_F12=y
-CONFIG_RMI4_F30=y
-CONFIG_RMI4_F34=y
-CONFIG_RMI4_F54=y
-CONFIG_RMI4_F55=y
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_CT82C710=m
-CONFIG_SERIO_PARKBD=m
-CONFIG_SERIO_PCIPS2=m
-CONFIG_SERIO_RAW=m
-CONFIG_SERIO_ALTERA_PS2=m
-CONFIG_SERIO_PS2MULT=m
-CONFIG_SERIO_ARC_PS2=m
-CONFIG_HYPERV_KEYBOARD=m
-CONFIG_SERIO_GPIO_PS2=m
-CONFIG_GAMEPORT=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_GAMEPORT_EMU10K1=m
-CONFIG_GAMEPORT_FM801=m
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_LEGACY_PTY_COUNT=0
-CONFIG_ROCKETPORT=m
-CONFIG_CYCLADES=m
-# CONFIG_CYZ_INTR is not set
-CONFIG_MOXA_INTELLIO=m
-CONFIG_MOXA_SMARTIO=m
-CONFIG_SYNCLINK=m
-CONFIG_SYNCLINKMP=m
-CONFIG_SYNCLINK_GT=m
-CONFIG_NOZOMI=m
-CONFIG_ISI=m
-CONFIG_N_HDLC=m
-CONFIG_N_GSM=m
-CONFIG_TRACE_ROUTER=m
-CONFIG_TRACE_SINK=m
-CONFIG_LDISC_AUTOLOAD=y
-# CONFIG_DEVMEM is not set
-# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-CONFIG_SERIAL_8250_FINTEK=y
-CONFIG_SERIAL_8250_EXAR=m
-CONFIG_SERIAL_8250_CS=m
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-CONFIG_SERIAL_8250_DW=m
-CONFIG_SERIAL_8250_LPSS=m
-# CONFIG_SERIAL_8250_MID is not set
-CONFIG_SERIAL_8250_MOXA=m
-CONFIG_SERIAL_MAX3100=m
-CONFIG_SERIAL_MAX310X=m
-CONFIG_SERIAL_JSM=m
-CONFIG_SERIAL_SCCNXP=m
-CONFIG_SERIAL_SC16IS7XX_CORE=m
-CONFIG_SERIAL_SC16IS7XX=m
-CONFIG_SERIAL_SC16IS7XX_I2C=y
-# CONFIG_SERIAL_SC16IS7XX_SPI is not set
-CONFIG_SERIAL_ALTERA_JTAGUART=m
-CONFIG_SERIAL_ALTERA_UART=m
-CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
-CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
-CONFIG_SERIAL_IFX6X60=m
-CONFIG_SERIAL_ARC=m
-CONFIG_SERIAL_ARC_NR_PORTS=1
-CONFIG_SERIAL_RP2=m
-CONFIG_SERIAL_RP2_NR_UARTS=32
-CONFIG_SERIAL_FSL_LPUART=m
-CONFIG_SERIAL_DEV_BUS=m
-# CONFIG_TTY_PRINTK is not set
-CONFIG_PRINTER=m
-CONFIG_LP_CONSOLE=y
-CONFIG_PPDEV=m
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_IRQ=y
-CONFIG_HVC_XEN=y
-CONFIG_HVC_XEN_FRONTEND=y
-CONFIG_VIRTIO_CONSOLE=m
-CONFIG_IPMI_HANDLER=m
-CONFIG_IPMI_DMI_DECODE=y
-CONFIG_IPMI_PANIC_EVENT=y
-CONFIG_IPMI_PANIC_STRING=y
-CONFIG_IPMI_DEVICE_INTERFACE=m
-CONFIG_IPMI_SI=m
-CONFIG_IPMI_SSIF=m
-CONFIG_IPMI_WATCHDOG=m
-CONFIG_IPMI_POWEROFF=m
-CONFIG_HW_RANDOM=m
-CONFIG_HW_RANDOM_TIMERIOMEM=m
-CONFIG_HW_RANDOM_INTEL=m
-CONFIG_HW_RANDOM_AMD=m
-CONFIG_HW_RANDOM_VIA=m
-CONFIG_HW_RANDOM_VIRTIO=m
-CONFIG_NVRAM=m
-CONFIG_R3964=m
-CONFIG_APPLICOM=m
-CONFIG_SYNCLINK_CS=m
-CONFIG_CARDMAN_4000=m
-CONFIG_CARDMAN_4040=m
-CONFIG_SCR24X=m
-CONFIG_IPWIRELESS=m
-CONFIG_MWAVE=m
-CONFIG_RAW_DRIVER=m
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_HPET_MMAP=y
-CONFIG_HPET_MMAP_DEFAULT=y
-CONFIG_HANGCHECK_TIMER=m
-CONFIG_TCG_TPM=m
-CONFIG_HW_RANDOM_TPM=y
-CONFIG_TCG_TIS_CORE=m
-CONFIG_TCG_TIS=m
-CONFIG_TCG_TIS_SPI=m
-CONFIG_TCG_TIS_I2C_ATMEL=m
-CONFIG_TCG_TIS_I2C_INFINEON=m
-CONFIG_TCG_TIS_I2C_NUVOTON=m
-CONFIG_TCG_NSC=m
-CONFIG_TCG_ATMEL=m
-CONFIG_TCG_INFINEON=m
-CONFIG_TCG_XEN=m
-CONFIG_TCG_CRB=m
-CONFIG_TCG_VTPM_PROXY=m
-CONFIG_TCG_TIS_ST33ZP24=m
-CONFIG_TCG_TIS_ST33ZP24_I2C=m
-CONFIG_TCG_TIS_ST33ZP24_SPI=m
-CONFIG_TELCLOCK=m
-CONFIG_XILLYBUS=m
-CONFIG_XILLYBUS_PCIE=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_MUX=m
-CONFIG_I2C_MUX_REG=m
-CONFIG_I2C_MULTI_INSTANTIATE=m
-
-#
-# Multiplexer I2C Chip support
-#
-CONFIG_I2C_MUX_GPIO=m
-CONFIG_I2C_MUX_LTC4306=m
-CONFIG_I2C_MUX_PCA9541=m
-CONFIG_I2C_MUX_PCA954x=m
-# CONFIG_I2C_MUX_REG is not set
-CONFIG_I2C_MUX_MLXCPLD=m
-CONFIG_I2C_SMBUS=m
-CONFIG_I2C_ALGOBIT=m
-CONFIG_I2C_ALI1535=m
-CONFIG_I2C_ALI1563=m
-CONFIG_I2C_ALI15X3=m
-CONFIG_I2C_AMD756=m
-CONFIG_I2C_AMD756_S4882=m
-CONFIG_I2C_AMD8111=m
-CONFIG_I2C_AMD_MP2=m
-CONFIG_I2C_I801=m
-CONFIG_I2C_ISCH=m
-CONFIG_I2C_ISMT=m
-CONFIG_I2C_PIIX4=m
-CONFIG_I2C_CHT_WC=m
-CONFIG_I2C_NFORCE2=m
-CONFIG_I2C_NFORCE2_S4985=m
-CONFIG_I2C_SIS5595=m
-CONFIG_I2C_SIS630=m
-CONFIG_I2C_SIS96X=m
-CONFIG_I2C_VIA=m
-CONFIG_I2C_VIAPRO=m
-CONFIG_I2C_SCMI=m
-CONFIG_I2C_CBUS_GPIO=m
-CONFIG_I2C_DESIGNWARE_CORE=m
-CONFIG_I2C_DESIGNWARE_PLATFORM=m
-CONFIG_I2C_DESIGNWARE_SLAVE=y
-CONFIG_I2C_DESIGNWARE_PCI=m
-CONFIG_I2C_DESIGNWARE_BAYTRAIL=y
-CONFIG_I2C_EMEV2=m
-CONFIG_I2C_GPIO=m
-CONFIG_I2C_KEMPLD=m
-CONFIG_I2C_XILINX=m
-CONFIG_I2C_DIOLAN_U2C=m
-CONFIG_I2C_DLN2=m
-CONFIG_I2C_PARPORT=m
-CONFIG_I2C_PARPORT_LIGHT=m
-CONFIG_I2C_ROBOTFUZZ_OSIF=m
-CONFIG_I2C_NVIDIA_GPU=m
-CONFIG_I2C_TAOS_EVM=m
-CONFIG_I2C_TINY_USB=m
-CONFIG_I2C_VIPERBOARD=m
-CONFIG_I2C_MLXCPLD=m
-CONFIG_I2C_CROS_EC_TUNNEL=m
-CONFIG_I2C_SLAVE=y
-CONFIG_I2C_SLAVE_EEPROM=m
-CONFIG_I2C_PCA_PLATFORM=m
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-# CONFIG_SPI_MEM is not set
-
-#
-# SPI Master Controller Drivers
-#
-CONFIG_SPI_ALTERA=m
-CONFIG_SPI_AXI_SPI_ENGINE=m
-CONFIG_SPI_BITBANG=m
-CONFIG_SPI_BUTTERFLY=m
-# CONFIG_SPI_CADENCE is not set
-CONFIG_SPI_DESIGNWARE=m
-CONFIG_SPI_DW_PCI=m
-CONFIG_SPI_DW_MID_DMA=y
-CONFIG_SPI_DW_MMIO=m
-# CONFIG_SPI_DLN2 is not set
-CONFIG_SPI_GPIO=m
-CONFIG_SPI_LM70_LLP=m
-CONFIG_SPI_OC_TINY=m
-CONFIG_SPI_PXA2XX=m
-CONFIG_SPI_PXA2XX_PCI=m
-# CONFIG_SPI_ROCKCHIP is not set
-CONFIG_SPI_SC18IS602=m
-CONFIG_SPI_XCOMM=m
-CONFIG_SPI_XILINX=m
-# CONFIG_SPI_ZYNQMP_GQSPI is not set
-
-#
-# SPI Protocol Masters
-#
-CONFIG_SPI_SPIDEV=m
-# CONFIG_SPI_LOOPBACK_TEST is not set
-CONFIG_SPI_TLE62X0=m
-CONFIG_SPI_SLAVE=y
-CONFIG_SPI_SLAVE_TIME=m
-CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
-CONFIG_SPMI=m
-CONFIG_HSI=m
-CONFIG_HSI_BOARDINFO=y
-
-#
-# HSI controllers
-#
-
-#
-# HSI clients
-#
-CONFIG_HSI_CHAR=m
-CONFIG_PPS_CLIENT_KTIMER=m
-CONFIG_PPS_CLIENT_LDISC=m
-CONFIG_PPS_CLIENT_PARPORT=m
-CONFIG_PPS_CLIENT_GPIO=m
-# CONFIG_DP83640_PHY is not set
-CONFIG_PTP_1588_CLOCK_KVM=m
-CONFIG_PINCTRL=y
-CONFIG_PINMUX=y
-CONFIG_PINCONF=y
-CONFIG_GENERIC_PINCONF=y
-# CONFIG_DEBUG_PINCTRL is not set
-CONFIG_PINCTRL_AMD=m
-CONFIG_PINCTRL_MCP23S08=m
-CONFIG_PINCTRL_SX150X=y
-CONFIG_PINCTRL_BAYTRAIL=y
-CONFIG_PINCTRL_CHERRYVIEW=m
-CONFIG_PINCTRL_INTEL=m
-# CONFIG_PINCTRL_BROXTON is not set
-CONFIG_PINCTRL_CANNONLAKE=m
-CONFIG_PINCTRL_CEDARFORK=m
-CONFIG_PINCTRL_DENVERTON=m
-CONFIG_PINCTRL_GEMINILAKE=m
-# CONFIG_PINCTRL_ICELAKE is not set
-CONFIG_PINCTRL_LEWISBURG=m
-CONFIG_PINCTRL_SUNRISEPOINT=m
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_FASTPATH_LIMIT=512
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIOLIB_IRQCHIP=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_SIOX=y
-CONFIG_GPIO_GENERIC=m
-CONFIG_GPIO_MAX730X=m
-
-#
-# Memory mapped GPIO drivers
-#
-CONFIG_GPIO_AMDPT=m
-# CONFIG_GPIO_DWAPB is not set
-CONFIG_GPIO_EXAR=m
-CONFIG_GPIO_GENERIC_PLATFORM=m
-CONFIG_GPIO_ICH=m
-CONFIG_GPIO_LYNXPOINT=y
-CONFIG_GPIO_MB86S7X=m
-CONFIG_GPIO_MOCKUP=m
-CONFIG_GPIO_VX855=m
-
-#
-# Port-mapped I/O GPIO drivers
-#
-CONFIG_GPIO_104_DIO_48E=m
-CONFIG_GPIO_104_IDIO_16=m
-CONFIG_GPIO_104_IDI_48=m
-CONFIG_GPIO_F7188X=m
-CONFIG_GPIO_GPIO_MM=m
-# CONFIG_GPIO_IT87 is not set
-CONFIG_GPIO_SCH=m
-CONFIG_GPIO_SCH311X=m
-CONFIG_GPIO_WINBOND=m
-CONFIG_GPIO_WS16C48=m
-
-#
-# I2C GPIO expanders
-#
-CONFIG_GPIO_ADP5588=m
-CONFIG_GPIO_MAX7300=m
-CONFIG_GPIO_MAX732X=m
-CONFIG_GPIO_PCA953X=m
-CONFIG_GPIO_PCF857X=m
-CONFIG_GPIO_TPIC2810=m
-
-#
-# MFD GPIO expanders
-#
-CONFIG_GPIO_ADP5520=m
-CONFIG_GPIO_ARIZONA=m
-CONFIG_GPIO_BD9571MWV=m
-CONFIG_GPIO_CRYSTAL_COVE=m
-CONFIG_GPIO_DA9052=m
-CONFIG_GPIO_DA9055=m
-CONFIG_GPIO_DLN2=m
-CONFIG_GPIO_KEMPLD=m
-CONFIG_GPIO_LP3943=m
-CONFIG_GPIO_LP873X=m
-CONFIG_GPIO_PALMAS=y
-CONFIG_GPIO_RC5T583=y
-CONFIG_GPIO_TPS65086=m
-CONFIG_GPIO_TPS6586X=y
-CONFIG_GPIO_TPS65910=y
-CONFIG_GPIO_TPS65912=m
-CONFIG_GPIO_TPS68470=y
-CONFIG_GPIO_TWL4030=m
-CONFIG_GPIO_TWL6040=m
-CONFIG_GPIO_WM831X=m
-CONFIG_GPIO_WM8350=m
-CONFIG_GPIO_WM8994=m
-
-#
-# PCI GPIO expanders
-#
-CONFIG_GPIO_AMD8111=m
-CONFIG_GPIO_ML_IOH=m
-CONFIG_GPIO_PCI_IDIO_16=m
-CONFIG_GPIO_PCIE_IDIO_24=m
-CONFIG_GPIO_RDC321X=m
-
-#
-# SPI GPIO expanders
-#
-CONFIG_GPIO_MAX3191X=m
-CONFIG_GPIO_MAX7301=m
-CONFIG_GPIO_MC33880=m
-CONFIG_GPIO_PISOSR=m
-CONFIG_GPIO_XRA1403=m
-
-#
-# USB GPIO expanders
-#
-CONFIG_GPIO_VIPERBOARD=m
-CONFIG_W1=m
-CONFIG_W1_CON=y
-
-#
-# 1-wire Bus Masters
-#
-CONFIG_W1_MASTER_MATROX=m
-CONFIG_W1_MASTER_DS2490=m
-CONFIG_W1_MASTER_DS2482=m
-CONFIG_W1_MASTER_DS1WM=m
-# CONFIG_W1_MASTER_GPIO is not set
-
-#
-# 1-wire Slaves
-#
-CONFIG_W1_SLAVE_THERM=m
-CONFIG_W1_SLAVE_SMEM=m
-CONFIG_W1_SLAVE_DS2405=m
-CONFIG_W1_SLAVE_DS2408=m
-CONFIG_W1_SLAVE_DS2408_READBACK=y
-CONFIG_W1_SLAVE_DS2413=m
-CONFIG_W1_SLAVE_DS2406=m
-CONFIG_W1_SLAVE_DS2423=m
-CONFIG_W1_SLAVE_DS2805=m
-CONFIG_W1_SLAVE_DS2431=m
-CONFIG_W1_SLAVE_DS2433=m
-# CONFIG_W1_SLAVE_DS2433_CRC is not set
-CONFIG_W1_SLAVE_DS2438=m
-CONFIG_W1_SLAVE_DS2780=m
-CONFIG_W1_SLAVE_DS2781=m
-CONFIG_W1_SLAVE_DS28E04=m
-CONFIG_W1_SLAVE_DS28E17=m
-CONFIG_POWER_AVS=y
-CONFIG_GENERIC_ADC_BATTERY=m
-CONFIG_MAX8925_POWER=m
-CONFIG_WM831X_BACKUP=m
-CONFIG_WM831X_POWER=m
-CONFIG_WM8350_POWER=m
-CONFIG_BATTERY_88PM860X=m
-# CONFIG_BATTERY_DS2760 is not set
-CONFIG_BATTERY_DS2780=m
-CONFIG_BATTERY_DS2781=m
-CONFIG_BATTERY_DS2782=m
-CONFIG_BATTERY_SBS=m
-CONFIG_CHARGER_SBS=m
-CONFIG_MANAGER_SBS=m
-CONFIG_BATTERY_DA9030=m
-CONFIG_BATTERY_DA9052=m
-CONFIG_CHARGER_AXP20X=m
-CONFIG_BATTERY_AXP20X=m
-# CONFIG_AXP20X_POWER is not set
-# CONFIG_AXP288_FUEL_GAUGE is not set
-CONFIG_BATTERY_MAX17042=m
-CONFIG_BATTERY_MAX1721X=m
-CONFIG_BATTERY_TWL4030_MADC=m
-CONFIG_CHARGER_88PM860X=m
-CONFIG_BATTERY_RX51=m
-CONFIG_CHARGER_ISP1704=m
-CONFIG_CHARGER_MAX8903=m
-CONFIG_CHARGER_TWL4030=m
-CONFIG_CHARGER_LP8727=m
-CONFIG_CHARGER_LP8788=m
-CONFIG_CHARGER_GPIO=m
-CONFIG_CHARGER_MANAGER=y
-CONFIG_CHARGER_LTC3651=m
-CONFIG_CHARGER_MAX14577=m
-# CONFIG_CHARGER_MAX77693 is not set
-CONFIG_CHARGER_MAX8997=m
-CONFIG_CHARGER_MAX8998=m
-CONFIG_CHARGER_BQ2415X=m
-CONFIG_CHARGER_BQ24190=m
-# CONFIG_CHARGER_BQ24257 is not set
-CONFIG_CHARGER_BQ24735=m
-# CONFIG_CHARGER_BQ25890 is not set
-CONFIG_CHARGER_SMB347=m
-CONFIG_CHARGER_TPS65090=m
-# CONFIG_CHARGER_RT9455 is not set
-# CONFIG_CHARGER_CROS_USBPD is not set
-CONFIG_HWMON_VID=m
-CONFIG_SENSORS_ABITUGURU=m
-CONFIG_SENSORS_ABITUGURU3=m
-CONFIG_SENSORS_AD7314=m
-CONFIG_SENSORS_AD7414=m
-CONFIG_SENSORS_AD7418=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1026=m
-CONFIG_SENSORS_ADM1029=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_ADM9240=m
-CONFIG_SENSORS_ADT7X10=m
-CONFIG_SENSORS_ADT7310=m
-CONFIG_SENSORS_ADT7410=m
-CONFIG_SENSORS_ADT7411=m
-CONFIG_SENSORS_ADT7462=m
-CONFIG_SENSORS_ADT7470=m
-CONFIG_SENSORS_ADT7475=m
-CONFIG_SENSORS_ASC7621=m
-CONFIG_SENSORS_K8TEMP=m
-CONFIG_SENSORS_K10TEMP=m
-CONFIG_SENSORS_FAM15H_POWER=m
-CONFIG_SENSORS_APPLESMC=m
-CONFIG_SENSORS_ASB100=m
-CONFIG_SENSORS_ASPEED=m
-CONFIG_SENSORS_ATXP1=m
-CONFIG_SENSORS_DS620=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_DELL_SMM=m
-CONFIG_SENSORS_DA9052_ADC=m
-CONFIG_SENSORS_DA9055=m
-CONFIG_SENSORS_I5K_AMB=m
-CONFIG_SENSORS_F71805F=m
-CONFIG_SENSORS_F71882FG=m
-CONFIG_SENSORS_F75375S=m
-CONFIG_SENSORS_MC13783_ADC=m
-CONFIG_SENSORS_FSCHMD=m
-CONFIG_SENSORS_FTSTEUTATES=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_GL520SM=m
-CONFIG_SENSORS_G762=m
-CONFIG_SENSORS_HIH6130=m
-CONFIG_SENSORS_IBMAEM=m
-CONFIG_SENSORS_IBMPEX=m
-CONFIG_SENSORS_IIO_HWMON=m
-CONFIG_SENSORS_I5500=m
-CONFIG_SENSORS_CORETEMP=m
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_JC42=m
-CONFIG_SENSORS_POWR1220=m
-CONFIG_SENSORS_LINEAGE=m
-CONFIG_SENSORS_LTC2945=m
-CONFIG_SENSORS_LTC2990=m
-CONFIG_SENSORS_LTC4151=m
-CONFIG_SENSORS_LTC4222=m
-CONFIG_SENSORS_LTC4245=m
-CONFIG_SENSORS_LTC4260=m
-CONFIG_SENSORS_LTC4261=m
-CONFIG_SENSORS_MAX1111=m
-CONFIG_SENSORS_MAX16065=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_MAX1668=m
-CONFIG_SENSORS_MAX197=m
-CONFIG_SENSORS_MAX31722=m
-CONFIG_SENSORS_MAX6621=m
-CONFIG_SENSORS_MAX6639=m
-CONFIG_SENSORS_MAX6642=m
-CONFIG_SENSORS_MAX6650=m
-CONFIG_SENSORS_MCP3021=m
-# CONFIG_SENSORS_MLXREG_FAN is not set
-CONFIG_SENSORS_TC654=m
-CONFIG_SENSORS_MENF21BMC_HWMON=m
-CONFIG_SENSORS_ADCXX=m
-CONFIG_SENSORS_LM63=m
-CONFIG_SENSORS_LM70=m
-CONFIG_SENSORS_LM73=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM87=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_LM92=m
-CONFIG_SENSORS_LM93=m
-CONFIG_SENSORS_LM95234=m
-CONFIG_SENSORS_LM95241=m
-CONFIG_SENSORS_LM95245=m
-CONFIG_SENSORS_PC87360=m
-CONFIG_SENSORS_PC87427=m
-CONFIG_SENSORS_NTC_THERMISTOR=m
-CONFIG_SENSORS_NCT6683=m
-CONFIG_SENSORS_NCT6775=m
-CONFIG_SENSORS_NCT7802=m
-CONFIG_SENSORS_NCT7904=m
-CONFIG_SENSORS_PCF8591=m
-CONFIG_PMBUS=m
-CONFIG_SENSORS_PMBUS=m
-CONFIG_SENSORS_ADM1275=m
-CONFIG_SENSORS_IBM_CFFPS=m
-CONFIG_SENSORS_IR35221=m
-CONFIG_SENSORS_LM25066=m
-CONFIG_SENSORS_LTC2978=m
-CONFIG_SENSORS_LTC2978_REGULATOR=y
-# CONFIG_SENSORS_LTC3815 is not set
-CONFIG_SENSORS_MAX16064=m
-# CONFIG_SENSORS_MAX20751 is not set
-CONFIG_SENSORS_MAX31785=m
-CONFIG_SENSORS_MAX34440=m
-CONFIG_SENSORS_MAX8688=m
-CONFIG_SENSORS_TPS40422=m
-CONFIG_SENSORS_TPS53679=m
-CONFIG_SENSORS_UCD9000=m
-CONFIG_SENSORS_UCD9200=m
-CONFIG_SENSORS_ZL6100=m
-# CONFIG_SENSORS_SHT15 is not set
-CONFIG_SENSORS_SHT3x=m
-CONFIG_SENSORS_SHTC1=m
-CONFIG_SENSORS_SIS5595=m
-CONFIG_SENSORS_DME1737=m
-CONFIG_SENSORS_EMC1403=m
-CONFIG_SENSORS_EMC2103=m
-CONFIG_SENSORS_EMC6W201=m
-CONFIG_SENSORS_SMSC47M1=m
-CONFIG_SENSORS_SMSC47M192=m
-CONFIG_SENSORS_SMSC47B397=m
-CONFIG_SENSORS_SCH56XX_COMMON=m
-CONFIG_SENSORS_SCH5627=m
-CONFIG_SENSORS_SCH5636=m
-CONFIG_SENSORS_STTS751=m
-CONFIG_SENSORS_SMM665=m
-CONFIG_SENSORS_ADC128D818=m
-CONFIG_SENSORS_ADS1015=m
-CONFIG_SENSORS_ADS7871=m
-CONFIG_SENSORS_INA209=m
-CONFIG_SENSORS_INA3221=m
-CONFIG_SENSORS_THMC50=m
-CONFIG_SENSORS_TMP102=m
-CONFIG_SENSORS_TMP103=m
-CONFIG_SENSORS_TMP108=m
-CONFIG_SENSORS_TMP401=m
-CONFIG_SENSORS_TMP421=m
-CONFIG_SENSORS_VIA_CPUTEMP=m
-CONFIG_SENSORS_VIA686A=m
-CONFIG_SENSORS_VT1211=m
-CONFIG_SENSORS_VT8231=m
-CONFIG_SENSORS_W83773G=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83791D=m
-CONFIG_SENSORS_W83792D=m
-CONFIG_SENSORS_W83793=m
-CONFIG_SENSORS_W83795=m
-# CONFIG_SENSORS_W83795_FANCTRL is not set
-CONFIG_SENSORS_W83L785TS=m
-CONFIG_SENSORS_W83L786NG=m
-CONFIG_SENSORS_W83627HF=m
-CONFIG_SENSORS_W83627EHF=m
-CONFIG_SENSORS_WM831X=m
-CONFIG_SENSORS_WM8350=m
-CONFIG_SENSORS_XGENE=m
-CONFIG_SENSORS_ACPI_POWER=m
-CONFIG_SENSORS_ATK0110=m
-CONFIG_THERMAL_STATISTICS=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=100
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_CLOCK_THERMAL=y
-CONFIG_DEVFREQ_THERMAL=y
-CONFIG_THERMAL_EMULATION=y
-CONFIG_INTEL_POWERCLAMP=m
-CONFIG_INTEL_RDT=m
-CONFIG_INTEL_SOC_DTS_IOSF_CORE=m
-CONFIG_INTEL_SOC_DTS_THERMAL=m
-CONFIG_INT340X_THERMAL=m
-CONFIG_ACPI_THERMAL_REL=m
-CONFIG_INT3406_THERMAL=m
-CONFIG_GENERIC_ADC_THERMAL=m
-CONFIG_WATCHDOG_CORE=m
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y
-CONFIG_DA9052_WATCHDOG=m
-CONFIG_DA9055_WATCHDOG=m
-CONFIG_DA9063_WATCHDOG=m
-CONFIG_MENF21BMC_WATCHDOG=m
-CONFIG_WDAT_WDT=m
-CONFIG_WM831X_WATCHDOG=m
-CONFIG_WM8350_WATCHDOG=m
-CONFIG_RAVE_SP_WATCHDOG=m
-CONFIG_DW_WATCHDOG=m
-CONFIG_TWL4030_WATCHDOG=m
-CONFIG_RETU_WATCHDOG=m
-CONFIG_ACQUIRE_WDT=m
-CONFIG_ADVANTECH_WDT=m
-CONFIG_ALIM1535_WDT=m
-CONFIG_ALIM7101_WDT=m
-CONFIG_EBC_C384_WDT=m
-CONFIG_F71808E_WDT=m
-# CONFIG_SP5100_TCO is not set
-CONFIG_SBC_FITPC2_WATCHDOG=m
-CONFIG_EUROTECH_WDT=m
-CONFIG_IB700_WDT=m
-CONFIG_IBMASR=m
-CONFIG_WAFER_WDT=m
-CONFIG_I6300ESB_WDT=m
-CONFIG_IE6XX_WDT=m
-CONFIG_ITCO_WDT=m
-CONFIG_ITCO_VENDOR_SUPPORT=y
-CONFIG_IT8712F_WDT=m
-CONFIG_IT87_WDT=m
-CONFIG_HP_WATCHDOG=m
-CONFIG_KEMPLD_WDT=m
-# CONFIG_HPWDT_NMI_DECODING is not set
-CONFIG_SC1200_WDT=m
-CONFIG_PC87413_WDT=m
-CONFIG_NV_TCO=m
-CONFIG_60XX_WDT=m
-CONFIG_CPU5_WDT=m
-CONFIG_SMSC_SCH311X_WDT=m
-CONFIG_SMSC37B787_WDT=m
-CONFIG_VIA_WDT=m
-CONFIG_W83627HF_WDT=m
-CONFIG_W83877F_WDT=m
-CONFIG_W83977F_WDT=m
-CONFIG_MACHZ_WDT=m
-CONFIG_SBC_EPX_C3_WATCHDOG=m
-CONFIG_INTEL_MEI_WDT=m
-CONFIG_NI903X_WDT=m
-CONFIG_NIC7018_WDT=m
-CONFIG_MEN_A21_WDT=m
-CONFIG_XEN_WDT=m
-CONFIG_PCIPCWATCHDOG=m
-CONFIG_WDTPCI=m
-CONFIG_USBPCWATCHDOG=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-CONFIG_SSB=m
-CONFIG_SSB_SPROM=y
-CONFIG_SSB_BLOCKIO=y
-CONFIG_SSB_PCIHOST_POSSIBLE=y
-CONFIG_SSB_PCIHOST=y
-CONFIG_SSB_B43_PCI_BRIDGE=y
-CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
-CONFIG_SSB_PCMCIAHOST=y
-CONFIG_SSB_SDIOHOST_POSSIBLE=y
-CONFIG_SSB_SDIOHOST=y
-CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
-CONFIG_SSB_DRIVER_PCICORE=y
-CONFIG_SSB_DRIVER_GPIO=y
-CONFIG_BCMA=m
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_SOC=y
-CONFIG_BCMA_DRIVER_PCI=y
-CONFIG_BCMA_SFLASH=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_DRIVER_GPIO=y
-# CONFIG_BCMA_DEBUG is not set
-CONFIG_MFD_CORE=y
-CONFIG_MFD_AS3711=y
-CONFIG_PMIC_ADP5520=y
-CONFIG_MFD_AAT2870_CORE=y
-CONFIG_MFD_BCM590XX=m
-CONFIG_MFD_BD9571MWV=m
-CONFIG_MFD_AXP20X=m
-CONFIG_MFD_AXP20X_I2C=m
-CONFIG_MFD_CROS_EC=m
-CONFIG_MFD_CROS_EC_CHARDEV=m
-CONFIG_PMIC_DA903X=y
-CONFIG_PMIC_DA9052=y
-CONFIG_MFD_DA9052_SPI=y
-CONFIG_MFD_DA9052_I2C=y
-CONFIG_MFD_DA9055=y
-CONFIG_MFD_DA9063=y
-CONFIG_MFD_DLN2=m
-CONFIG_MFD_MC13XXX=m
-CONFIG_MFD_MC13XXX_SPI=m
-CONFIG_HTC_I2CPLD=y
-CONFIG_MFD_INTEL_QUARK_I2C_GPIO=m
-CONFIG_MFD_INTEL_LPSS_ACPI=m
-CONFIG_MFD_INTEL_LPSS_PCI=m
-CONFIG_LPC_ICH=m
-CONFIG_LPC_SCH=m
-CONFIG_INTEL_SOC_PMIC=y
-CONFIG_INTEL_SOC_PMIC_CHTWC=y
-CONFIG_INTEL_SOC_PMIC_CHTDC_TI=m
-CONFIG_MFD_KEMPLD=m
-CONFIG_MFD_88PM800=m
-CONFIG_MFD_88PM805=m
-CONFIG_MFD_88PM860X=y
-CONFIG_MFD_MAX14577=y
-CONFIG_MFD_MAX77693=y
-CONFIG_MFD_MAX8907=m
-CONFIG_MFD_MAX8925=y
-CONFIG_MFD_MAX8997=y
-CONFIG_MFD_MAX8998=y
-CONFIG_MFD_MENF21BMC=m
-CONFIG_EZX_PCAP=y
-CONFIG_MFD_VIPERBOARD=m
-CONFIG_MFD_RETU=m
-# CONFIG_UCB1400_CORE is not set
-CONFIG_MFD_RDC321X=m
-CONFIG_MFD_RC5T583=y
-CONFIG_MFD_SEC_CORE=y
-CONFIG_MFD_SI476X_CORE=m
-CONFIG_MFD_SMSC=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MFD_TI_AM335X_TSCADC=m
-CONFIG_MFD_LP3943=m
-CONFIG_MFD_LP8788=y
-CONFIG_MFD_TI_LMU=m
-CONFIG_MFD_PALMAS=y
-# CONFIG_TPS65010 is not set
-CONFIG_MFD_TPS65086=m
-CONFIG_MFD_TPS65090=y
-CONFIG_MFD_TPS68470=y
-CONFIG_MFD_TI_LP873X=m
-CONFIG_MFD_TPS6586X=y
-CONFIG_MFD_TPS65910=y
-CONFIG_MFD_TPS65912=y
-CONFIG_MFD_TPS65912_I2C=y
-CONFIG_MFD_TPS65912_SPI=y
-CONFIG_MFD_TPS80031=y
-CONFIG_TWL4030_CORE=y
-CONFIG_MFD_TWL4030_AUDIO=y
-CONFIG_TWL6040_CORE=y
-CONFIG_MFD_WL1273_CORE=m
-CONFIG_MFD_VX855=m
-CONFIG_MFD_ARIZONA=y
-CONFIG_MFD_ARIZONA_I2C=m
-CONFIG_MFD_ARIZONA_SPI=m
-# CONFIG_MFD_CS47L24 is not set
-CONFIG_MFD_WM5102=y
-CONFIG_MFD_WM5110=y
-CONFIG_MFD_WM8997=y
-# CONFIG_MFD_WM8998 is not set
-CONFIG_MFD_WM8400=y
-CONFIG_MFD_WM831X=y
-CONFIG_MFD_WM831X_I2C=y
-CONFIG_MFD_WM831X_SPI=y
-CONFIG_MFD_WM8350=y
-CONFIG_MFD_WM8350_I2C=y
-CONFIG_MFD_WM8994=y
-CONFIG_RAVE_SP_CORE=m
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=m
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
-CONFIG_REGULATOR_USERSPACE_CONSUMER=m
-CONFIG_REGULATOR_88PG86X=m
-CONFIG_REGULATOR_88PM800=m
-CONFIG_REGULATOR_88PM8607=m
-CONFIG_REGULATOR_ACT8865=m
-CONFIG_REGULATOR_AD5398=m
-CONFIG_REGULATOR_ANATOP=m
-CONFIG_REGULATOR_AAT2870=m
-CONFIG_REGULATOR_ARIZONA_LDO1=m
-CONFIG_REGULATOR_ARIZONA_MICSUPP=m
-CONFIG_REGULATOR_AS3711=m
-CONFIG_REGULATOR_AXP20X=m
-CONFIG_REGULATOR_BCM590XX=m
-CONFIG_REGULATOR_BD9571MWV=m
-CONFIG_REGULATOR_DA903X=m
-CONFIG_REGULATOR_DA9052=m
-CONFIG_REGULATOR_DA9055=m
-CONFIG_REGULATOR_DA9063=m
-CONFIG_REGULATOR_DA9210=m
-CONFIG_REGULATOR_DA9211=m
-CONFIG_REGULATOR_FAN53555=m
-CONFIG_REGULATOR_GPIO=m
-CONFIG_REGULATOR_ISL9305=m
-CONFIG_REGULATOR_ISL6271A=m
-CONFIG_REGULATOR_LM363X=m
-CONFIG_REGULATOR_LP3971=m
-CONFIG_REGULATOR_LP3972=m
-CONFIG_REGULATOR_LP872X=m
-CONFIG_REGULATOR_LP8755=m
-CONFIG_REGULATOR_LP8788=m
-CONFIG_REGULATOR_LTC3589=m
-CONFIG_REGULATOR_LTC3676=m
-CONFIG_REGULATOR_MAX14577=m
-CONFIG_REGULATOR_MAX1586=m
-CONFIG_REGULATOR_MAX8649=m
-CONFIG_REGULATOR_MAX8660=m
-CONFIG_REGULATOR_MAX8907=m
-CONFIG_REGULATOR_MAX8925=m
-CONFIG_REGULATOR_MAX8952=m
-CONFIG_REGULATOR_MAX8997=m
-CONFIG_REGULATOR_MAX8998=m
-CONFIG_REGULATOR_MAX77693=m
-CONFIG_REGULATOR_MC13XXX_CORE=m
-CONFIG_REGULATOR_MC13783=m
-CONFIG_REGULATOR_MC13892=m
-# CONFIG_REGULATOR_MT6311 is not set
-CONFIG_REGULATOR_PALMAS=m
-CONFIG_REGULATOR_PCAP=m
-CONFIG_REGULATOR_PFUZE100=m
-# CONFIG_REGULATOR_PV88060 is not set
-CONFIG_REGULATOR_PV88080=m
-# CONFIG_REGULATOR_PV88090 is not set
-CONFIG_REGULATOR_PWM=m
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-CONFIG_REGULATOR_RC5T583=m
-CONFIG_REGULATOR_S2MPA01=m
-CONFIG_REGULATOR_S2MPS11=m
-CONFIG_REGULATOR_S5M8767=m
-CONFIG_REGULATOR_TPS51632=m
-CONFIG_REGULATOR_TPS62360=m
-CONFIG_REGULATOR_TPS65023=m
-CONFIG_REGULATOR_TPS6507X=m
-CONFIG_REGULATOR_TPS65086=m
-CONFIG_REGULATOR_TPS65090=m
-CONFIG_REGULATOR_TPS65132=m
-CONFIG_REGULATOR_TPS6524X=m
-CONFIG_REGULATOR_TPS6586X=m
-CONFIG_REGULATOR_TPS65910=m
-CONFIG_REGULATOR_TPS65912=m
-CONFIG_REGULATOR_TPS80031=m
-CONFIG_REGULATOR_TWL4030=m
-CONFIG_REGULATOR_WM831X=m
-CONFIG_REGULATOR_WM8350=m
-CONFIG_REGULATOR_WM8400=m
-CONFIG_REGULATOR_WM8994=m
-CONFIG_CEC_CORE=m
-CONFIG_RC_CORE=m
-CONFIG_RC_MAP=m
-CONFIG_LIRC=y
-CONFIG_RC_DECODERS=y
-CONFIG_IR_NEC_DECODER=m
-CONFIG_IR_RC5_DECODER=m
-CONFIG_IR_RC6_DECODER=m
-CONFIG_IR_JVC_DECODER=m
-CONFIG_IR_SONY_DECODER=m
-CONFIG_IR_SANYO_DECODER=m
-CONFIG_IR_SHARP_DECODER=m
-CONFIG_IR_MCE_KBD_DECODER=m
-CONFIG_IR_XMP_DECODER=m
-CONFIG_IR_IMON_DECODER=m
-CONFIG_RC_DEVICES=y
-CONFIG_RC_ATI_REMOTE=m
-CONFIG_IR_ENE=m
-CONFIG_IR_IMON=m
-CONFIG_IR_IMON_RAW=m
-CONFIG_IR_MCEUSB=m
-CONFIG_IR_ITE_CIR=m
-CONFIG_IR_FINTEK=m
-CONFIG_IR_NUVOTON=m
-CONFIG_IR_REDRAT3=m
-CONFIG_IR_STREAMZAP=m
-CONFIG_IR_WINBOND_CIR=m
-CONFIG_IR_IGORPLUGUSB=m
-CONFIG_IR_IGUANA=m
-CONFIG_IR_TTUSBIR=m
-CONFIG_RC_LOOPBACK=m
-CONFIG_IR_SERIAL=m
-CONFIG_IR_SERIAL_TRANSMITTER=y
-CONFIG_IR_SIR=m
-CONFIG_MEDIA_SUPPORT=m
-
-#
-# Multimedia core support
-#
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_SDR_SUPPORT=y
-CONFIG_MEDIA_CEC_SUPPORT=y
-CONFIG_MEDIA_CEC_RC=y
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_MEDIA_CONTROLLER_REQUEST_API=m
-# CONFIG_MEDIA_CONTROLLER_DVB is not set
-CONFIG_VIDEO_DEV=m
-# CONFIG_VIDEO_V4L2_SUBDEV_API is not set
-CONFIG_VIDEO_V4L2=m
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-# CONFIG_VIDEO_PCI_SKELETON is not set
-CONFIG_VIDEO_TUNER=m
-CONFIG_V4L2_MEM2MEM_DEV=m
-CONFIG_V4L2_FWNODE=m
-CONFIG_VIDEOBUF_GEN=m
-CONFIG_VIDEOBUF_DMA_SG=m
-CONFIG_VIDEOBUF_VMALLOC=m
-CONFIG_DVB_CORE=m
-CONFIG_DVB_MMAP=y
-CONFIG_DVB_NET=y
-CONFIG_TTPCI_EEPROM=m
-CONFIG_DVB_MAX_ADAPTERS=8
-# CONFIG_DVB_DYNAMIC_MINORS is not set
-# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
-# CONFIG_DVB_ULE_DEBUG is not set
-
-#
-# Media drivers
-#
-CONFIG_MEDIA_USB_SUPPORT=y
-
-#
-# Webcam devices
-#
-CONFIG_USB_VIDEO_CLASS=m
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-CONFIG_USB_M5602=m
-CONFIG_USB_STV06XX=m
-CONFIG_USB_GL860=m
-CONFIG_USB_GSPCA_BENQ=m
-CONFIG_USB_GSPCA_CONEX=m
-CONFIG_USB_GSPCA_CPIA1=m
-CONFIG_USB_GSPCA_DTCS033=m
-CONFIG_USB_GSPCA_ETOMS=m
-CONFIG_USB_GSPCA_FINEPIX=m
-CONFIG_USB_GSPCA_JEILINJ=m
-CONFIG_USB_GSPCA_JL2005BCD=m
-CONFIG_USB_GSPCA_KINECT=m
-CONFIG_USB_GSPCA_KONICA=m
-CONFIG_USB_GSPCA_MARS=m
-CONFIG_USB_GSPCA_MR97310A=m
-CONFIG_USB_GSPCA_NW80X=m
-CONFIG_USB_GSPCA_OV519=m
-CONFIG_USB_GSPCA_OV534=m
-CONFIG_USB_GSPCA_OV534_9=m
-CONFIG_USB_GSPCA_PAC207=m
-CONFIG_USB_GSPCA_PAC7302=m
-CONFIG_USB_GSPCA_PAC7311=m
-CONFIG_USB_GSPCA_SE401=m
-CONFIG_USB_GSPCA_SN9C2028=m
-CONFIG_USB_GSPCA_SN9C20X=m
-CONFIG_USB_GSPCA_SONIXB=m
-CONFIG_USB_GSPCA_SONIXJ=m
-CONFIG_USB_GSPCA_SPCA500=m
-CONFIG_USB_GSPCA_SPCA501=m
-CONFIG_USB_GSPCA_SPCA505=m
-CONFIG_USB_GSPCA_SPCA506=m
-CONFIG_USB_GSPCA_SPCA508=m
-CONFIG_USB_GSPCA_SPCA561=m
-CONFIG_USB_GSPCA_SPCA1528=m
-CONFIG_USB_GSPCA_SQ905=m
-CONFIG_USB_GSPCA_SQ905C=m
-CONFIG_USB_GSPCA_SQ930X=m
-CONFIG_USB_GSPCA_STK014=m
-CONFIG_USB_GSPCA_STK1135=m
-CONFIG_USB_GSPCA_STV0680=m
-CONFIG_USB_GSPCA_SUNPLUS=m
-CONFIG_USB_GSPCA_T613=m
-CONFIG_USB_GSPCA_TOPRO=m
-CONFIG_USB_GSPCA_TOUPTEK=m
-CONFIG_USB_GSPCA_TV8532=m
-CONFIG_USB_GSPCA_VC032X=m
-CONFIG_USB_GSPCA_VICAM=m
-CONFIG_USB_GSPCA_XIRLINK_CIT=m
-CONFIG_USB_GSPCA_ZC3XX=m
-CONFIG_USB_PWC=m
-# CONFIG_USB_PWC_DEBUG is not set
-CONFIG_USB_PWC_INPUT_EVDEV=y
-CONFIG_VIDEO_CPIA2=m
-CONFIG_USB_ZR364XX=m
-CONFIG_USB_STKWEBCAM=m
-CONFIG_USB_S2255=m
-CONFIG_VIDEO_USBTV=m
-
-#
-# Analog TV USB devices
-#
-CONFIG_VIDEO_PVRUSB2=m
-CONFIG_VIDEO_PVRUSB2_SYSFS=y
-CONFIG_VIDEO_PVRUSB2_DVB=y
-# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
-CONFIG_VIDEO_HDPVR=m
-CONFIG_VIDEO_USBVISION=m
-CONFIG_VIDEO_STK1160_COMMON=m
-CONFIG_VIDEO_STK1160=m
-CONFIG_VIDEO_GO7007=m
-CONFIG_VIDEO_GO7007_USB=m
-CONFIG_VIDEO_GO7007_LOADER=m
-CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
-
-#
-# Analog/digital TV USB devices
-#
-CONFIG_VIDEO_AU0828=m
-CONFIG_VIDEO_AU0828_V4L2=y
-CONFIG_VIDEO_AU0828_RC=y
-CONFIG_VIDEO_CX231XX=m
-CONFIG_VIDEO_CX231XX_RC=y
-CONFIG_VIDEO_CX231XX_ALSA=m
-CONFIG_VIDEO_CX231XX_DVB=m
-CONFIG_VIDEO_TM6000=m
-CONFIG_VIDEO_TM6000_ALSA=m
-CONFIG_VIDEO_TM6000_DVB=m
-
-#
-# Digital TV USB devices
-#
-CONFIG_DVB_USB=m
-# CONFIG_DVB_USB_DEBUG is not set
-CONFIG_DVB_USB_DIB3000MC=m
-CONFIG_DVB_USB_A800=m
-CONFIG_DVB_USB_DIBUSB_MB=m
-# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
-CONFIG_DVB_USB_DIBUSB_MC=m
-CONFIG_DVB_USB_DIB0700=m
-CONFIG_DVB_USB_UMT_010=m
-CONFIG_DVB_USB_CXUSB=m
-CONFIG_DVB_USB_M920X=m
-CONFIG_DVB_USB_DIGITV=m
-CONFIG_DVB_USB_VP7045=m
-CONFIG_DVB_USB_VP702X=m
-CONFIG_DVB_USB_GP8PSK=m
-CONFIG_DVB_USB_NOVA_T_USB2=m
-CONFIG_DVB_USB_TTUSB2=m
-CONFIG_DVB_USB_DTT200U=m
-CONFIG_DVB_USB_OPERA1=m
-CONFIG_DVB_USB_AF9005=m
-CONFIG_DVB_USB_AF9005_REMOTE=m
-CONFIG_DVB_USB_PCTV452E=m
-CONFIG_DVB_USB_DW2102=m
-CONFIG_DVB_USB_CINERGY_T2=m
-CONFIG_DVB_USB_DTV5100=m
-CONFIG_DVB_USB_AZ6027=m
-CONFIG_DVB_USB_TECHNISAT_USB2=m
-CONFIG_DVB_USB_V2=m
-CONFIG_DVB_USB_AF9015=m
-CONFIG_DVB_USB_AF9035=m
-CONFIG_DVB_USB_ANYSEE=m
-CONFIG_DVB_USB_AU6610=m
-CONFIG_DVB_USB_AZ6007=m
-CONFIG_DVB_USB_CE6230=m
-CONFIG_DVB_USB_EC168=m
-CONFIG_DVB_USB_GL861=m
-CONFIG_DVB_USB_LME2510=m
-CONFIG_DVB_USB_MXL111SF=m
-CONFIG_DVB_USB_RTL28XXU=m
-CONFIG_DVB_USB_DVBSKY=m
-CONFIG_DVB_USB_ZD1301=m
-CONFIG_DVB_TTUSB_BUDGET=m
-# CONFIG_DVB_TTUSB_DEC is not set
-CONFIG_SMS_USB_DRV=m
-CONFIG_DVB_B2C2_FLEXCOP_USB=m
-# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
-CONFIG_DVB_AS102=m
-
-#
-# Webcam, TV (analog/digital) USB devices
-#
-CONFIG_VIDEO_EM28XX=m
-CONFIG_VIDEO_EM28XX_V4L2=m
-CONFIG_VIDEO_EM28XX_ALSA=m
-CONFIG_VIDEO_EM28XX_DVB=m
-CONFIG_VIDEO_EM28XX_RC=m
-
-#
-# Software defined radio USB devices
-#
-CONFIG_USB_AIRSPY=m
-CONFIG_USB_HACKRF=m
-CONFIG_USB_MSI2500=m
-
-#
-# USB HDMI CEC adapters
-#
-CONFIG_USB_PULSE8_CEC=m
-CONFIG_USB_RAINSHADOW_CEC=m
-CONFIG_MEDIA_PCI_SUPPORT=y
-
-#
-# Media capture support
-#
-CONFIG_VIDEO_MEYE=m
-CONFIG_VIDEO_SOLO6X10=m
-CONFIG_VIDEO_TW5864=m
-CONFIG_VIDEO_TW68=m
-CONFIG_VIDEO_TW686X=m
-
-#
-# Media capture/analog TV support
-#
-CONFIG_VIDEO_IVTV=m
-# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
-CONFIG_VIDEO_IVTV_ALSA=m
-CONFIG_VIDEO_FB_IVTV=m
-CONFIG_VIDEO_HEXIUM_GEMINI=m
-CONFIG_VIDEO_HEXIUM_ORION=m
-CONFIG_VIDEO_MXB=m
-CONFIG_VIDEO_DT3155=m
-
-#
-# Media capture/analog/hybrid TV support
-#
-CONFIG_VIDEO_CX18=m
-CONFIG_VIDEO_CX18_ALSA=m
-CONFIG_VIDEO_CX23885=m
-CONFIG_MEDIA_ALTERA_CI=m
-CONFIG_VIDEO_CX25821=m
-CONFIG_VIDEO_CX25821_ALSA=m
-CONFIG_VIDEO_CX88=m
-CONFIG_VIDEO_CX88_ALSA=m
-CONFIG_VIDEO_CX88_BLACKBIRD=m
-CONFIG_VIDEO_CX88_DVB=m
-CONFIG_VIDEO_CX88_ENABLE_VP3054=y
-CONFIG_VIDEO_CX88_VP3054=m
-CONFIG_VIDEO_CX88_MPEG=m
-CONFIG_VIDEO_BT848=m
-CONFIG_DVB_BT8XX=m
-CONFIG_VIDEO_SAA7134=m
-CONFIG_VIDEO_SAA7134_ALSA=m
-CONFIG_VIDEO_SAA7134_RC=y
-CONFIG_VIDEO_SAA7134_DVB=m
-CONFIG_VIDEO_SAA7134_GO7007=m
-CONFIG_SAA716X_SUPPORT=y
-CONFIG_SAA716X_CORE=m
-CONFIG_DVB_SAA716X_BUDGET=m
-CONFIG_DVB_SAA716X_HYBRID=m
-CONFIG_DVB_SAA716X_FF=m
-CONFIG_VIDEO_SAA7164=m
-
-#
-# Media digital TV PCI Adapters
-#
-CONFIG_DVB_AV7110_IR=y
-CONFIG_DVB_AV7110=m
-CONFIG_DVB_AV7110_OSD=y
-CONFIG_DVB_BUDGET_CORE=m
-CONFIG_DVB_BUDGET=m
-CONFIG_DVB_BUDGET_CI=m
-CONFIG_DVB_BUDGET_AV=m
-CONFIG_DVB_BUDGET_PATCH=m
-CONFIG_DVB_B2C2_FLEXCOP_PCI=m
-# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
-CONFIG_DVB_PLUTO2=m
-CONFIG_DVB_DM1105=m
-CONFIG_DVB_PT1=m
-CONFIG_DVB_PT3=m
-CONFIG_MANTIS_CORE=m
-CONFIG_DVB_MANTIS=m
-CONFIG_DVB_HOPPER=m
-CONFIG_DVB_NGENE=m
-CONFIG_DVB_DDBRIDGE=m
-CONFIG_DVB_DDBRIDGE_MSIENABLE=y
-CONFIG_DVB_SMIPCIE=m
-# CONFIG_DVB_NETUP_UNIDVB is not set
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_CAFE_CCIC=m
-CONFIG_VIDEO_VIA_CAMERA=m
-# CONFIG_VIDEO_CADENCE is not set
-# CONFIG_SOC_CAMERA is not set
-CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
-CONFIG_VIDEO_SH_VEU=m
-CONFIG_V4L_TEST_DRIVERS=y
-CONFIG_VIDEO_VIVID=m
-CONFIG_VIDEO_VIVID_CEC=y
-CONFIG_VIDEO_VIVID_MAX_DEVS=64
-CONFIG_VIDEO_VIM2M=m
-CONFIG_DVB_PLATFORM_DRIVERS=y
-CONFIG_CEC_PLATFORM_DRIVERS=y
-# CONFIG_VIDEO_CROS_EC_CEC is not set
-CONFIG_SDR_PLATFORM_DRIVERS=y
-
-#
-# Supported MMC/SDIO adapters
-#
-CONFIG_SMS_SDIO_DRV=m
-CONFIG_RADIO_ADAPTERS=y
-CONFIG_RADIO_TEA575X=m
-CONFIG_RADIO_SI470X=m
-CONFIG_USB_SI470X=m
-# CONFIG_I2C_SI470X is not set
-# CONFIG_RADIO_SI4713 is not set
-CONFIG_RADIO_SI476X=m
-CONFIG_USB_MR800=m
-CONFIG_USB_DSBR=m
-CONFIG_RADIO_MAXIRADIO=m
-CONFIG_RADIO_SHARK=m
-CONFIG_RADIO_SHARK2=m
-CONFIG_USB_KEENE=m
-CONFIG_USB_RAREMONO=m
-CONFIG_USB_MA901=m
-CONFIG_RADIO_TEA5764=m
-CONFIG_RADIO_SAA7706H=m
-CONFIG_RADIO_TEF6862=m
-CONFIG_RADIO_WL1273=m
-
-#
-# Texas Instruments WL128x FM driver (ST based)
-#
-CONFIG_RADIO_WL128X=m
-
-#
-# Supported FireWire (IEEE 1394) Adapters
-#
-CONFIG_DVB_FIREDTV=m
-CONFIG_DVB_FIREDTV_INPUT=y
-CONFIG_MEDIA_COMMON_OPTIONS=y
-
-#
-# common driver options
-#
-CONFIG_VIDEO_CX2341X=m
-CONFIG_VIDEO_TVEEPROM=m
-CONFIG_CYPRESS_FIRMWARE=m
-CONFIG_VIDEOBUF2_CORE=m
-CONFIG_VIDEOBUF2_V4L2=m
-CONFIG_VIDEOBUF2_MEMOPS=m
-CONFIG_VIDEOBUF2_DMA_CONTIG=m
-CONFIG_VIDEOBUF2_VMALLOC=m
-CONFIG_VIDEOBUF2_DMA_SG=m
-CONFIG_VIDEOBUF2_DVB=m
-CONFIG_DVB_B2C2_FLEXCOP=m
-CONFIG_VIDEO_SAA7146=m
-CONFIG_VIDEO_SAA7146_VV=m
-CONFIG_SMS_SIANO_MDTV=m
-CONFIG_SMS_SIANO_RC=y
-# CONFIG_SMS_SIANO_DEBUGFS is not set
-CONFIG_VIDEO_V4L2_TPG=m
-
-#
-# Media ancillary drivers (tuners, sensors, i2c, spi, frontends)
-#
-CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
-CONFIG_MEDIA_ATTACH=y
-CONFIG_VIDEO_IR_I2C=m
-
-#
-# Audio decoders, processors and mixers
-#
-CONFIG_VIDEO_TVAUDIO=m
-CONFIG_VIDEO_TDA7432=m
-CONFIG_VIDEO_TDA9840=m
-CONFIG_VIDEO_TEA6415C=m
-CONFIG_VIDEO_TEA6420=m
-CONFIG_VIDEO_MSP3400=m
-CONFIG_VIDEO_CS3308=m
-CONFIG_VIDEO_CS5345=m
-CONFIG_VIDEO_CS53L32A=m
-CONFIG_VIDEO_UDA1342=m
-CONFIG_VIDEO_WM8775=m
-CONFIG_VIDEO_WM8739=m
-CONFIG_VIDEO_VP27SMPX=m
-CONFIG_VIDEO_SONY_BTF_MPX=m
-
-#
-# RDS decoders
-#
-CONFIG_VIDEO_SAA6588=m
-
-#
-# Video decoders
-#
-CONFIG_VIDEO_SAA711X=m
-CONFIG_VIDEO_TVP5150=m
-CONFIG_VIDEO_TW2804=m
-CONFIG_VIDEO_TW9903=m
-CONFIG_VIDEO_TW9906=m
-
-#
-# Video and audio decoders
-#
-CONFIG_VIDEO_SAA717X=m
-CONFIG_VIDEO_CX25840=m
-
-#
-# Video encoders
-#
-CONFIG_VIDEO_SAA7127=m
-
-#
-# Camera sensor devices
-#
-CONFIG_VIDEO_OV2640=m
-CONFIG_VIDEO_OV7640=m
-CONFIG_VIDEO_OV7670=m
-CONFIG_VIDEO_MT9V011=m
-
-#
-# Flash devices
-#
-
-#
-# Video improvement chips
-#
-CONFIG_VIDEO_UPD64031A=m
-CONFIG_VIDEO_UPD64083=m
-
-#
-# Audio/Video compression chips
-#
-CONFIG_VIDEO_SAA6752HS=m
-
-#
-# SDR tuner chips
-#
-
-#
-# Miscellaneous helper chips
-#
-CONFIG_VIDEO_M52790=m
-
-#
-# Sensors used on soc_camera driver
-#
-
-#
-# Media SPI Adapters
-#
-CONFIG_CXD2880_SPI_DRV=m
-CONFIG_MEDIA_TUNER=m
-CONFIG_MEDIA_TUNER_SIMPLE=m
-CONFIG_MEDIA_TUNER_TDA18250=m
-CONFIG_MEDIA_TUNER_TDA8290=m
-CONFIG_MEDIA_TUNER_TDA827X=m
-CONFIG_MEDIA_TUNER_TDA18271=m
-CONFIG_MEDIA_TUNER_TDA9887=m
-CONFIG_MEDIA_TUNER_TEA5761=m
-CONFIG_MEDIA_TUNER_TEA5767=m
-CONFIG_MEDIA_TUNER_MSI001=m
-CONFIG_MEDIA_TUNER_MT20XX=m
-CONFIG_MEDIA_TUNER_MT2060=m
-CONFIG_MEDIA_TUNER_MT2063=m
-CONFIG_MEDIA_TUNER_MT2266=m
-CONFIG_MEDIA_TUNER_MT2131=m
-CONFIG_MEDIA_TUNER_QT1010=m
-CONFIG_MEDIA_TUNER_XC2028=m
-CONFIG_MEDIA_TUNER_XC5000=m
-CONFIG_MEDIA_TUNER_XC4000=m
-CONFIG_MEDIA_TUNER_MXL5005S=m
-CONFIG_MEDIA_TUNER_MXL5007T=m
-CONFIG_MEDIA_TUNER_MC44S803=m
-CONFIG_MEDIA_TUNER_MAX2165=m
-CONFIG_MEDIA_TUNER_TDA18218=m
-CONFIG_MEDIA_TUNER_FC0011=m
-CONFIG_MEDIA_TUNER_FC0012=m
-CONFIG_MEDIA_TUNER_FC0013=m
-CONFIG_MEDIA_TUNER_TDA18212=m
-CONFIG_MEDIA_TUNER_E4000=m
-CONFIG_MEDIA_TUNER_FC2580=m
-CONFIG_MEDIA_TUNER_M88RS6000T=m
-CONFIG_MEDIA_TUNER_TUA9001=m
-CONFIG_MEDIA_TUNER_SI2157=m
-CONFIG_MEDIA_TUNER_IT913X=m
-CONFIG_MEDIA_TUNER_R820T=m
-CONFIG_MEDIA_TUNER_MXL301RF=m
-CONFIG_MEDIA_TUNER_QM1D1C0042=m
-CONFIG_MEDIA_TUNER_QM1D1B0004=m
-CONFIG_MEDIA_TUNER_AV201X=m
-CONFIG_MEDIA_TUNER_STV6120=m
-
-#
-# Multistandard (satellite) frontends
-#
-CONFIG_DVB_STB0899=m
-CONFIG_DVB_STB6100=m
-CONFIG_DVB_STV090x=m
-CONFIG_DVB_STV0910=m
-CONFIG_DVB_STV6110x=m
-CONFIG_DVB_STV6111=m
-CONFIG_DVB_MXL5XX=m
-CONFIG_DVB_M88DS3103=m
-
-#
-# Multistandard (cable + terrestrial) frontends
-#
-CONFIG_DVB_DRXK=m
-CONFIG_DVB_TDA18271C2DD=m
-CONFIG_DVB_SI2165=m
-CONFIG_DVB_MN88472=m
-CONFIG_DVB_MN88473=m
-
-#
-# DVB-S (satellite) frontends
-#
-CONFIG_DVB_CX24110=m
-CONFIG_DVB_CX24123=m
-CONFIG_DVB_MT312=m
-CONFIG_DVB_ZL10036=m
-CONFIG_DVB_ZL10039=m
-CONFIG_DVB_S5H1420=m
-CONFIG_DVB_STV0288=m
-CONFIG_DVB_STB6000=m
-CONFIG_DVB_STV0299=m
-CONFIG_DVB_STV6110=m
-CONFIG_DVB_STV0900=m
-CONFIG_DVB_TDA8083=m
-CONFIG_DVB_TDA10086=m
-CONFIG_DVB_TDA8261=m
-CONFIG_DVB_VES1X93=m
-CONFIG_DVB_TUNER_ITD1000=m
-CONFIG_DVB_TUNER_CX24113=m
-CONFIG_DVB_TDA826X=m
-CONFIG_DVB_TUA6100=m
-CONFIG_DVB_CX24116=m
-CONFIG_DVB_CX24117=m
-CONFIG_DVB_CX24120=m
-CONFIG_DVB_SI21XX=m
-CONFIG_DVB_TS2020=m
-CONFIG_DVB_DS3000=m
-CONFIG_DVB_MB86A16=m
-CONFIG_DVB_TDA10071=m
-
-#
-# DVB-T (terrestrial) frontends
-#
-CONFIG_DVB_SP8870=m
-CONFIG_DVB_SP887X=m
-CONFIG_DVB_CX22700=m
-CONFIG_DVB_CX22702=m
-CONFIG_DVB_DRXD=m
-CONFIG_DVB_L64781=m
-CONFIG_DVB_TDA1004X=m
-CONFIG_DVB_NXT6000=m
-CONFIG_DVB_MT352=m
-CONFIG_DVB_ZL10353=m
-CONFIG_DVB_DIB3000MB=m
-CONFIG_DVB_DIB3000MC=m
-CONFIG_DVB_DIB7000M=m
-CONFIG_DVB_DIB7000P=m
-CONFIG_DVB_TDA10048=m
-CONFIG_DVB_AF9013=m
-CONFIG_DVB_EC100=m
-CONFIG_DVB_STV0367=m
-CONFIG_DVB_CXD2820R=m
-CONFIG_DVB_CXD2841ER=m
-CONFIG_DVB_RTL2830=m
-CONFIG_DVB_RTL2832=m
-CONFIG_DVB_RTL2832_SDR=m
-CONFIG_DVB_SI2168=m
-CONFIG_DVB_AS102_FE=m
-CONFIG_DVB_ZD1301_DEMOD=m
-CONFIG_DVB_GP8PSK_FE=m
-
-#
-# DVB-C (cable) frontends
-#
-CONFIG_DVB_VES1820=m
-CONFIG_DVB_TDA10021=m
-CONFIG_DVB_TDA10023=m
-CONFIG_DVB_STV0297=m
-
-#
-# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
-#
-CONFIG_DVB_NXT200X=m
-CONFIG_DVB_OR51211=m
-CONFIG_DVB_OR51132=m
-CONFIG_DVB_BCM3510=m
-CONFIG_DVB_LGDT330X=m
-CONFIG_DVB_LGDT3305=m
-CONFIG_DVB_LGDT3306A=m
-CONFIG_DVB_LG2160=m
-CONFIG_DVB_S5H1409=m
-CONFIG_DVB_AU8522=m
-CONFIG_DVB_AU8522_DTV=m
-CONFIG_DVB_AU8522_V4L=m
-CONFIG_DVB_S5H1411=m
-
-#
-# ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_S921=m
-CONFIG_DVB_DIB8000=m
-CONFIG_DVB_MB86A20S=m
-
-#
-# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_TC90522=m
-
-#
-# Digital terrestrial only tuners/PLL
-#
-CONFIG_DVB_PLL=m
-CONFIG_DVB_TUNER_DIB0070=m
-CONFIG_DVB_TUNER_DIB0090=m
-
-#
-# SEC control devices for DVB-S
-#
-CONFIG_DVB_DRX39XYJ=m
-CONFIG_DVB_LNBH25=m
-CONFIG_DVB_LNBP21=m
-CONFIG_DVB_LNBP22=m
-CONFIG_DVB_ISL6405=m
-CONFIG_DVB_ISL6421=m
-CONFIG_DVB_ISL6422=m
-CONFIG_DVB_ISL6423=m
-CONFIG_DVB_A8293=m
-CONFIG_DVB_LGS8GXX=m
-CONFIG_DVB_ATBM8830=m
-CONFIG_DVB_TDA665x=m
-CONFIG_DVB_IX2505V=m
-CONFIG_DVB_M88RS2000=m
-CONFIG_DVB_AF9033=m
-CONFIG_DVB_TAS2101=m
-
-#
-# Common Interface (EN50221) controller drivers
-#
-CONFIG_DVB_CXD2099=m
-CONFIG_DVB_SP2=m
-
-#
-# Tools to develop new frontends
-#
-CONFIG_DVB_DUMMY_FE=m
-CONFIG_AGP_SIS=y
-CONFIG_AGP_VIA=y
-CONFIG_VGA_SWITCHEROO=y
-CONFIG_DRM=m
-CONFIG_DRM_DP_AUX_CHARDEV=y
-CONFIG_DRM_KMS_HELPER=m
-CONFIG_DRM_LOAD_EDID_FIRMWARE=y
-CONFIG_DRM_TTM=m
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
-CONFIG_DRM_VM=y
-CONFIG_DRM_SCHED=m
-CONFIG_DRM_I2C_CH7006=m
-CONFIG_DRM_I2C_SIL164=m
-CONFIG_DRM_I2C_NXP_TDA998X=m
-CONFIG_DRM_RADEON=m
-CONFIG_DRM_RADEON_USERPTR=y
-CONFIG_DRM_AMDGPU=m
-CONFIG_DRM_AMDGPU_SI=y
-CONFIG_DRM_AMDGPU_CIK=y
-CONFIG_DRM_AMDGPU_USERPTR=y
-CONFIG_DRM_AMDGPU_GART_DEBUGFS=y
-CONFIG_DRM_AMD_ACP=y
-
-#
-# Display Engine Configuration
-#
-CONFIG_DRM_AMD_DC=y
-CONFIG_DRM_AMD_DC_DCN1_0=y
-# CONFIG_DEBUG_KERNEL_DC is not set
-CONFIG_CHASH=m
-# CONFIG_CHASH_STATS is not set
-# CONFIG_CHASH_SELFTEST is not set
-CONFIG_DRM_NOUVEAU=m
-CONFIG_NOUVEAU_DEBUG=3
-CONFIG_NOUVEAU_DEBUG_DEFAULT=1
-# CONFIG_NOUVEAU_DEBUG_MMU is not set
-CONFIG_DRM_NOUVEAU_BACKLIGHT=y
-CONFIG_DRM_I915=m
-CONFIG_DRM_I915_ALPHA_SUPPORT=y
-CONFIG_DRM_I915_GVT=y
-CONFIG_DRM_I915_GVT_KVMGT=m
-
-#
-# drm/i915 Debugging
-#
-CONFIG_DRM_I915_WERROR=y
-# CONFIG_DRM_I915_DEBUG is not set
-# CONFIG_DRM_I915_DEBUG_GEM is not set
-# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
-# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
-# CONFIG_DRM_I915_DEBUG_GUC is not set
-# CONFIG_DRM_I915_SELFTEST is not set
-# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
-# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
-CONFIG_DRM_VGEM=m
-CONFIG_DRM_VKMS=m
-CONFIG_DRM_VMWGFX=m
-CONFIG_DRM_VMWGFX_FBCON=y
-CONFIG_DRM_GMA500=m
-CONFIG_DRM_GMA600=y
-CONFIG_DRM_GMA3600=y
-CONFIG_DRM_UDL=m
-CONFIG_DRM_AST=m
-CONFIG_DRM_MGAG200=m
-CONFIG_DRM_CIRRUS_QEMU=m
-CONFIG_DRM_QXL=m
-CONFIG_DRM_BOCHS=m
-CONFIG_DRM_VIRTIO_GPU=m
-CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
-CONFIG_DRM_ANALOGIX_ANX78XX=m
-CONFIG_HSA_AMD=m
-CONFIG_DRM_HISI_HIBMC=m
-CONFIG_DRM_TINYDRM=m
-CONFIG_TINYDRM_MIPI_DBI=m
-CONFIG_TINYDRM_ILI9225=m
-# CONFIG_TINYDRM_ILI9341 is not set
-CONFIG_TINYDRM_MI0283QT=m
-CONFIG_TINYDRM_REPAPER=m
-CONFIG_TINYDRM_ST7586=m
-CONFIG_TINYDRM_ST7735R=m
-# CONFIG_DRM_XEN is not set
-CONFIG_DRM_LEGACY=y
-CONFIG_DRM_TDFX=m
-CONFIG_DRM_R128=m
-CONFIG_DRM_I810=m
-CONFIG_DRM_MGA=m
-CONFIG_DRM_SIS=m
-CONFIG_DRM_VIA=m
-CONFIG_DRM_SAVAGE=m
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_DDC=m
-CONFIG_FB_BOOT_VESA_SUPPORT=y
-CONFIG_FB_FOREIGN_ENDIAN=y
-CONFIG_FB_BOTH_ENDIAN=y
-# CONFIG_FB_BIG_ENDIAN is not set
-# CONFIG_FB_LITTLE_ENDIAN is not set
-CONFIG_FB_SVGALIB=m
-CONFIG_FB_BACKLIGHT=y
-CONFIG_FB_CIRRUS=m
-CONFIG_FB_PM2=m
-# CONFIG_FB_PM2_FIFO_DISCONNECT is not set
-CONFIG_FB_CYBER2000=m
-CONFIG_FB_CYBER2000_DDC=y
-CONFIG_FB_ARC=m
-CONFIG_FB_VGA16=m
-CONFIG_FB_UVESA=m
-CONFIG_FB_VESA=y
-CONFIG_FB_OPENCORES=m
-CONFIG_FB_NVIDIA=m
-CONFIG_FB_NVIDIA_I2C=y
-# CONFIG_FB_NVIDIA_DEBUG is not set
-CONFIG_FB_NVIDIA_BACKLIGHT=y
-CONFIG_FB_RIVA=m
-# CONFIG_FB_RIVA_I2C is not set
-# CONFIG_FB_RIVA_DEBUG is not set
-CONFIG_FB_RIVA_BACKLIGHT=y
-CONFIG_FB_I740=m
-CONFIG_FB_LE80578=m
-CONFIG_FB_CARILLO_RANCH=m
-CONFIG_FB_INTEL=m
-# CONFIG_FB_INTEL_DEBUG is not set
-CONFIG_FB_INTEL_I2C=y
-CONFIG_FB_MATROX=m
-CONFIG_FB_MATROX_MILLENIUM=y
-CONFIG_FB_MATROX_MYSTIQUE=y
-CONFIG_FB_MATROX_G=y
-CONFIG_FB_MATROX_I2C=m
-CONFIG_FB_MATROX_MAVEN=m
-CONFIG_FB_RADEON=m
-CONFIG_FB_RADEON_I2C=y
-CONFIG_FB_RADEON_BACKLIGHT=y
-# CONFIG_FB_RADEON_DEBUG is not set
-CONFIG_FB_ATY128=m
-CONFIG_FB_ATY128_BACKLIGHT=y
-CONFIG_FB_ATY=m
-CONFIG_FB_ATY_CT=y
-CONFIG_FB_ATY_GENERIC_LCD=y
-CONFIG_FB_ATY_GX=y
-CONFIG_FB_ATY_BACKLIGHT=y
-CONFIG_FB_S3=m
-CONFIG_FB_S3_DDC=y
-CONFIG_FB_SAVAGE=m
-CONFIG_FB_SAVAGE_I2C=y
-CONFIG_FB_SAVAGE_ACCEL=y
-CONFIG_FB_SIS=m
-CONFIG_FB_SIS_300=y
-CONFIG_FB_SIS_315=y
-CONFIG_FB_VIA=m
-# CONFIG_FB_VIA_DIRECT_PROCFS is not set
-# CONFIG_FB_VIA_X_COMPATIBILITY is not set
-CONFIG_FB_NEOMAGIC=m
-CONFIG_FB_KYRO=m
-CONFIG_FB_3DFX=m
-# CONFIG_FB_3DFX_ACCEL is not set
-CONFIG_FB_3DFX_I2C=y
-CONFIG_FB_VOODOO1=m
-CONFIG_FB_VT8623=m
-CONFIG_FB_TRIDENT=m
-CONFIG_FB_ARK=m
-CONFIG_FB_PM3=m
-CONFIG_FB_CARMINE=m
-CONFIG_FB_CARMINE_DRAM_EVAL=y
-# CONFIG_CARMINE_DRAM_CUSTOM is not set
-CONFIG_FB_SMSCUFX=m
-CONFIG_FB_UDL=m
-CONFIG_XEN_FBDEV_FRONTEND=y
-CONFIG_FB_MB862XX=m
-CONFIG_FB_MB862XX_PCI_GDC=y
-CONFIG_FB_MB862XX_I2C=y
-CONFIG_FB_HYPERV=m
-CONFIG_FB_SIMPLE=y
-CONFIG_LCD_CLASS_DEVICE=m
-CONFIG_LCD_L4F00242T03=m
-CONFIG_LCD_LMS283GF05=m
-CONFIG_LCD_LTV350QV=m
-CONFIG_LCD_ILI922X=m
-CONFIG_LCD_ILI9320=m
-CONFIG_LCD_TDO24M=m
-CONFIG_LCD_VGG2432A4=m
-# CONFIG_LCD_PLATFORM is not set
-CONFIG_LCD_S6E63M0=m
-CONFIG_LCD_LD9040=m
-CONFIG_LCD_AMS369FG06=m
-CONFIG_LCD_LMS501KF03=m
-CONFIG_LCD_HX8357=m
-# CONFIG_LCD_OTM3225A is not set
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_CARILLO_RANCH=m
-CONFIG_BACKLIGHT_PWM=m
-CONFIG_BACKLIGHT_DA903X=m
-CONFIG_BACKLIGHT_DA9052=m
-CONFIG_BACKLIGHT_MAX8925=m
-CONFIG_BACKLIGHT_APPLE=m
-CONFIG_BACKLIGHT_SAHARA=m
-CONFIG_BACKLIGHT_WM831X=m
-CONFIG_BACKLIGHT_ADP5520=m
-CONFIG_BACKLIGHT_ADP8860=m
-CONFIG_BACKLIGHT_ADP8870=m
-CONFIG_BACKLIGHT_88PM860X=m
-CONFIG_BACKLIGHT_AAT2870=m
-CONFIG_BACKLIGHT_LM3630A=m
-CONFIG_BACKLIGHT_LM3639=m
-CONFIG_BACKLIGHT_LP855X=m
-CONFIG_BACKLIGHT_LP8788=m
-CONFIG_BACKLIGHT_PANDORA=m
-CONFIG_BACKLIGHT_AS3711=m
-CONFIG_BACKLIGHT_GPIO=m
-CONFIG_BACKLIGHT_LV5207LP=m
-CONFIG_BACKLIGHT_BD6107=m
-CONFIG_BACKLIGHT_ARCXCNN=m
-# CONFIG_BACKLIGHT_RAVE_SP is not set
-CONFIG_VGASTATE=m
-# CONFIG_VGACON_SOFT_SCROLLBACK is not set
-CONFIG_BOOTSPLASH=y
-# CONFIG_LOGO is not set
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set
-CONFIG_SND=m
-# CONFIG_SND_DEBUG_VERBOSE is not set
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_PCM_ELD=y
-CONFIG_SND_PCM_IEC958=y
-CONFIG_SND_DMAENGINE_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_SEQ_DEVICE=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_COMPRESS_OFFLOAD=m
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_HRTIMER=m
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_MAX_CARDS=32
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_SEQUENCER_OSS=m
-CONFIG_SND_SEQ_MIDI_EVENT=m
-CONFIG_SND_SEQ_MIDI=m
-CONFIG_SND_SEQ_MIDI_EMUL=m
-CONFIG_SND_SEQ_VIRMIDI=m
-CONFIG_SND_MPU401_UART=m
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_OPL3_LIB_SEQ=m
-CONFIG_SND_VX_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_PCSP=m
-CONFIG_SND_DUMMY=m
-CONFIG_SND_ALOOP=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_MTS64=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_PORTMAN2X4=m
-CONFIG_SND_AC97_POWER_SAVE=y
-CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
-CONFIG_SND_SB_COMMON=m
-CONFIG_SND_AD1889=m
-CONFIG_SND_ALS300=m
-CONFIG_SND_ALS4000=m
-CONFIG_SND_ALI5451=m
-CONFIG_SND_ASIHPI=m
-CONFIG_SND_ATIIXP=m
-CONFIG_SND_ATIIXP_MODEM=m
-CONFIG_SND_AU8810=m
-CONFIG_SND_AU8820=m
-CONFIG_SND_AU8830=m
-CONFIG_SND_AW2=m
-CONFIG_SND_AZT3328=m
-CONFIG_SND_BT87X=m
-# CONFIG_SND_BT87X_OVERCLOCK is not set
-CONFIG_SND_CA0106=m
-CONFIG_SND_CMIPCI=m
-CONFIG_SND_OXYGEN_LIB=m
-CONFIG_SND_OXYGEN=m
-CONFIG_SND_CS4281=m
-CONFIG_SND_CS46XX=m
-CONFIG_SND_CS46XX_NEW_DSP=y
-CONFIG_SND_CTXFI=m
-CONFIG_SND_DARLA20=m
-CONFIG_SND_GINA20=m
-CONFIG_SND_LAYLA20=m
-CONFIG_SND_DARLA24=m
-CONFIG_SND_GINA24=m
-CONFIG_SND_LAYLA24=m
-CONFIG_SND_MONA=m
-CONFIG_SND_MIA=m
-CONFIG_SND_ECHO3G=m
-CONFIG_SND_INDIGO=m
-CONFIG_SND_INDIGOIO=m
-CONFIG_SND_INDIGODJ=m
-CONFIG_SND_INDIGOIOX=m
-CONFIG_SND_INDIGODJX=m
-CONFIG_SND_EMU10K1=m
-CONFIG_SND_EMU10K1_SEQ=m
-CONFIG_SND_EMU10K1X=m
-CONFIG_SND_ENS1370=m
-CONFIG_SND_ENS1371=m
-CONFIG_SND_ES1938=m
-CONFIG_SND_ES1968=m
-CONFIG_SND_ES1968_INPUT=y
-CONFIG_SND_ES1968_RADIO=y
-CONFIG_SND_FM801=m
-CONFIG_SND_FM801_TEA575X_BOOL=y
-CONFIG_SND_HDSP=m
-CONFIG_SND_HDSPM=m
-CONFIG_SND_ICE1712=m
-CONFIG_SND_ICE1724=m
-CONFIG_SND_INTEL8X0=m
-CONFIG_SND_INTEL8X0M=m
-CONFIG_SND_KORG1212=m
-CONFIG_SND_LOLA=m
-CONFIG_SND_LX6464ES=m
-CONFIG_SND_MAESTRO3=m
-CONFIG_SND_MAESTRO3_INPUT=y
-CONFIG_SND_MIXART=m
-CONFIG_SND_NM256=m
-CONFIG_SND_PCXHR=m
-CONFIG_SND_RIPTIDE=m
-CONFIG_SND_RME32=m
-CONFIG_SND_RME96=m
-CONFIG_SND_RME9652=m
-CONFIG_SND_SONICVIBES=m
-CONFIG_SND_TRIDENT=m
-CONFIG_SND_VIA82XX=m
-CONFIG_SND_VIA82XX_MODEM=m
-CONFIG_SND_VIRTUOSO=m
-CONFIG_SND_VX222=m
-CONFIG_SND_YMFPCI=m
-CONFIG_SND_HDA=m
-CONFIG_SND_HDA_INTEL=m
-CONFIG_SND_HDA_RECONFIG=y
-CONFIG_SND_HDA_INPUT_BEEP=y
-CONFIG_SND_HDA_INPUT_BEEP_MODE=1
-CONFIG_SND_HDA_PATCH_LOADER=y
-CONFIG_SND_HDA_CODEC_REALTEK=m
-CONFIG_SND_HDA_CODEC_ANALOG=m
-CONFIG_SND_HDA_CODEC_SIGMATEL=m
-CONFIG_SND_HDA_CODEC_VIA=m
-CONFIG_SND_HDA_CODEC_HDMI=m
-CONFIG_SND_HDA_CODEC_CIRRUS=m
-CONFIG_SND_HDA_CODEC_CONEXANT=m
-CONFIG_SND_HDA_CODEC_CA0110=m
-CONFIG_SND_HDA_CODEC_CA0132=m
-CONFIG_SND_HDA_CODEC_CA0132_DSP=y
-CONFIG_SND_HDA_CODEC_CMEDIA=m
-CONFIG_SND_HDA_CODEC_SI3054=m
-CONFIG_SND_HDA_GENERIC=m
-CONFIG_SND_HDA_CORE=m
-CONFIG_SND_HDA_DSP_LOADER=y
-CONFIG_SND_HDA_EXT_CORE=m
-CONFIG_SND_HDA_PREALLOC_SIZE=2048
-CONFIG_SND_SPI=y
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_USB_UA101=m
-CONFIG_SND_USB_USX2Y=m
-CONFIG_SND_USB_CAIAQ=m
-CONFIG_SND_USB_CAIAQ_INPUT=y
-CONFIG_SND_USB_US122L=m
-CONFIG_SND_USB_6FIRE=m
-CONFIG_SND_USB_HIFACE=m
-CONFIG_SND_BCD2000=m
-CONFIG_SND_USB_LINE6=m
-CONFIG_SND_USB_VARIAX=m
-CONFIG_SND_FIREWIRE=y
-CONFIG_SND_FIREWIRE_LIB=m
-CONFIG_SND_DICE=m
-CONFIG_SND_OXFW=m
-CONFIG_SND_ISIGHT=m
-CONFIG_SND_FIREWORKS=m
-CONFIG_SND_BEBOB=m
-# CONFIG_SND_FIREWIRE_DIGI00X is not set
-# CONFIG_SND_FIREWIRE_TASCAM is not set
-CONFIG_SND_FIREWIRE_MOTU=m
-CONFIG_SND_FIREFACE=m
-CONFIG_SND_VXPOCKET=m
-CONFIG_SND_PDAUDIOCF=m
-CONFIG_SND_SOC=m
-CONFIG_SND_SOC_AC97_BUS=y
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_COMPRESS=y
-CONFIG_SND_SOC_TOPOLOGY=y
-CONFIG_SND_SOC_ACPI=m
-CONFIG_SND_SOC_AMD_ACP=m
-CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m
-CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
-CONFIG_SND_ATMEL_SOC=m
-CONFIG_SND_DESIGNWARE_I2S=m
-CONFIG_SND_DESIGNWARE_PCM=y
-
-#
-# SoC Audio for Freescale CPUs
-#
-
-#
-# Common SoC Audio options for Freescale CPUs:
-#
-CONFIG_SND_SOC_FSL_ASRC=m
-CONFIG_SND_SOC_FSL_SAI=m
-CONFIG_SND_SOC_FSL_SSI=m
-CONFIG_SND_SOC_FSL_SPDIF=m
-CONFIG_SND_SOC_FSL_ESAI=m
-CONFIG_SND_SOC_IMX_AUDMUX=m
-CONFIG_SND_I2S_HI6210_I2S=m
-CONFIG_SND_SOC_IMG=y
-CONFIG_SND_SOC_IMG_I2S_IN=m
-CONFIG_SND_SOC_IMG_I2S_OUT=m
-CONFIG_SND_SOC_IMG_PARALLEL_OUT=m
-CONFIG_SND_SOC_IMG_SPDIF_IN=m
-CONFIG_SND_SOC_IMG_SPDIF_OUT=m
-CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m
-CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y
-CONFIG_SND_SST_IPC=m
-CONFIG_SND_SST_IPC_PCI=m
-CONFIG_SND_SST_IPC_ACPI=m
-CONFIG_SND_SOC_INTEL_SST_ACPI=m
-CONFIG_SND_SOC_INTEL_SST=m
-CONFIG_SND_SOC_INTEL_SST_FIRMWARE=m
-CONFIG_SND_SOC_INTEL_HASWELL=m
-CONFIG_SND_SST_ATOM_HIFI2_PLATFORM=m
-CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI=m
-CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI=m
-CONFIG_SND_SOC_INTEL_SKYLAKE=m
-CONFIG_SND_SOC_ACPI_INTEL_MATCH=m
-CONFIG_SND_SOC_INTEL_MACH=y
-# CONFIG_SND_SOC_INTEL_HASWELL_MACH is not set
-CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=m
-# CONFIG_SND_SOC_INTEL_BROADWELL_MACH is not set
-# CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH is not set
-# CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH is not set
-# CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH is not set
-# CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH is not set
-# CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH is not set
-CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH=m
-# CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH is not set
-CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH=m
-# CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH is not set
-
-#
-# STMicroelectronics STM32 SOC audio support
-#
-CONFIG_SND_SOC_XTFPGA_I2S=m
-CONFIG_ZX_TDM=m
-CONFIG_SND_SOC_I2C_AND_SPI=m
-
-#
-# CODEC drivers
-#
-CONFIG_SND_SOC_AC97_CODEC=m
-CONFIG_SND_SOC_ADAU_UTILS=m
-CONFIG_SND_SOC_ADAU1701=m
-CONFIG_SND_SOC_ADAU17X1=m
-CONFIG_SND_SOC_ADAU1761=m
-CONFIG_SND_SOC_ADAU1761_I2C=m
-CONFIG_SND_SOC_ADAU1761_SPI=m
-CONFIG_SND_SOC_ADAU7002=m
-CONFIG_SND_SOC_AK4104=m
-CONFIG_SND_SOC_AK4458=m
-CONFIG_SND_SOC_AK4554=m
-CONFIG_SND_SOC_AK4613=m
-CONFIG_SND_SOC_AK4642=m
-CONFIG_SND_SOC_AK5386=m
-CONFIG_SND_SOC_AK5558=m
-CONFIG_SND_SOC_ALC5623=m
-CONFIG_SND_SOC_BD28623=m
-CONFIG_SND_SOC_BT_SCO=m
-CONFIG_SND_SOC_CS35L32=m
-CONFIG_SND_SOC_CS35L33=m
-CONFIG_SND_SOC_CS35L34=m
-CONFIG_SND_SOC_CS35L35=m
-CONFIG_SND_SOC_CS42L42=m
-CONFIG_SND_SOC_CS42L51=m
-CONFIG_SND_SOC_CS42L51_I2C=m
-CONFIG_SND_SOC_CS42L52=m
-CONFIG_SND_SOC_CS42L56=m
-CONFIG_SND_SOC_CS42L73=m
-CONFIG_SND_SOC_CS4265=m
-CONFIG_SND_SOC_CS4270=m
-CONFIG_SND_SOC_CS4271=m
-CONFIG_SND_SOC_CS4271_I2C=m
-CONFIG_SND_SOC_CS4271_SPI=m
-CONFIG_SND_SOC_CS42XX8=m
-CONFIG_SND_SOC_CS42XX8_I2C=m
-CONFIG_SND_SOC_CS43130=m
-CONFIG_SND_SOC_CS4349=m
-CONFIG_SND_SOC_CS53L30=m
-CONFIG_SND_SOC_DA7219=m
-CONFIG_SND_SOC_HDMI_CODEC=m
-CONFIG_SND_SOC_ES7134=m
-# CONFIG_SND_SOC_ES7241 is not set
-CONFIG_SND_SOC_ES8316=m
-CONFIG_SND_SOC_ES8328=m
-CONFIG_SND_SOC_ES8328_I2C=m
-CONFIG_SND_SOC_ES8328_SPI=m
-CONFIG_SND_SOC_GTM601=m
-CONFIG_SND_SOC_INNO_RK3036=m
-CONFIG_SND_SOC_MAX98357A=m
-CONFIG_SND_SOC_MAX98504=m
-CONFIG_SND_SOC_MAX9867=m
-CONFIG_SND_SOC_MAX98927=m
-CONFIG_SND_SOC_MAX98373=m
-CONFIG_SND_SOC_MAX9860=m
-CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
-CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
-CONFIG_SND_SOC_PCM1681=m
-CONFIG_SND_SOC_PCM1789=m
-CONFIG_SND_SOC_PCM1789_I2C=m
-CONFIG_SND_SOC_PCM179X=m
-CONFIG_SND_SOC_PCM179X_I2C=m
-CONFIG_SND_SOC_PCM179X_SPI=m
-CONFIG_SND_SOC_PCM186X=m
-CONFIG_SND_SOC_PCM186X_I2C=m
-CONFIG_SND_SOC_PCM186X_SPI=m
-CONFIG_SND_SOC_PCM3168A=m
-CONFIG_SND_SOC_PCM3168A_I2C=m
-CONFIG_SND_SOC_PCM3168A_SPI=m
-CONFIG_SND_SOC_PCM512x=m
-CONFIG_SND_SOC_PCM512x_I2C=m
-CONFIG_SND_SOC_PCM512x_SPI=m
-CONFIG_SND_SOC_RL6231=m
-CONFIG_SND_SOC_RT5616=m
-CONFIG_SND_SOC_RT5631=m
-CONFIG_SND_SOC_RT5645=m
-CONFIG_SND_SOC_RT5677=m
-CONFIG_SND_SOC_RT5677_SPI=m
-CONFIG_SND_SOC_SGTL5000=m
-CONFIG_SND_SOC_SI476X=m
-CONFIG_SND_SOC_SIGMADSP=m
-CONFIG_SND_SOC_SIGMADSP_I2C=m
-CONFIG_SND_SOC_SIGMADSP_REGMAP=m
-# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set
-CONFIG_SND_SOC_SIRF_AUDIO_CODEC=m
-CONFIG_SND_SOC_SPDIF=m
-# CONFIG_SND_SOC_SSM2305 is not set
-CONFIG_SND_SOC_SSM2602=m
-CONFIG_SND_SOC_SSM2602_SPI=m
-CONFIG_SND_SOC_SSM2602_I2C=m
-CONFIG_SND_SOC_SSM4567=m
-CONFIG_SND_SOC_STA32X=m
-CONFIG_SND_SOC_STA350=m
-CONFIG_SND_SOC_STI_SAS=m
-CONFIG_SND_SOC_TAS2552=m
-CONFIG_SND_SOC_TAS5086=m
-CONFIG_SND_SOC_TAS571X=m
-CONFIG_SND_SOC_TAS5720=m
-CONFIG_SND_SOC_TAS6424=m
-CONFIG_SND_SOC_TDA7419=m
-CONFIG_SND_SOC_TFA9879=m
-CONFIG_SND_SOC_TLV320AIC23=m
-CONFIG_SND_SOC_TLV320AIC23_I2C=m
-CONFIG_SND_SOC_TLV320AIC23_SPI=m
-CONFIG_SND_SOC_TLV320AIC31XX=m
-CONFIG_SND_SOC_TLV320AIC32X4=m
-CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
-CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
-CONFIG_SND_SOC_TLV320AIC3X=m
-CONFIG_SND_SOC_TS3A227E=m
-CONFIG_SND_SOC_TSCS42XX=m
-# CONFIG_SND_SOC_TSCS454 is not set
-CONFIG_SND_SOC_WM8510=m
-CONFIG_SND_SOC_WM8523=m
-CONFIG_SND_SOC_WM8524=m
-CONFIG_SND_SOC_WM8580=m
-CONFIG_SND_SOC_WM8711=m
-CONFIG_SND_SOC_WM8728=m
-CONFIG_SND_SOC_WM8731=m
-CONFIG_SND_SOC_WM8737=m
-CONFIG_SND_SOC_WM8741=m
-CONFIG_SND_SOC_WM8750=m
-CONFIG_SND_SOC_WM8753=m
-CONFIG_SND_SOC_WM8770=m
-CONFIG_SND_SOC_WM8776=m
-# CONFIG_SND_SOC_WM8782 is not set
-CONFIG_SND_SOC_WM8804=m
-CONFIG_SND_SOC_WM8804_I2C=m
-CONFIG_SND_SOC_WM8804_SPI=m
-CONFIG_SND_SOC_WM8903=m
-CONFIG_SND_SOC_WM8960=m
-CONFIG_SND_SOC_WM8962=m
-CONFIG_SND_SOC_WM8974=m
-CONFIG_SND_SOC_WM8978=m
-CONFIG_SND_SOC_WM8985=m
-CONFIG_SND_SOC_ZX_AUD96P22=m
-CONFIG_SND_SOC_MAX9759=m
-# CONFIG_SND_SOC_MT6351 is not set
-CONFIG_SND_SOC_NAU8540=m
-CONFIG_SND_SOC_NAU8810=m
-CONFIG_SND_SOC_NAU8824=m
-CONFIG_SND_SOC_TPA6130A2=m
-CONFIG_SND_SIMPLE_CARD_UTILS=m
-CONFIG_SND_SIMPLE_CARD=m
-CONFIG_HDMI_LPE_AUDIO=m
-CONFIG_SND_SYNTH_EMUX=m
-# CONFIG_SND_XEN_FRONTEND is not set
-CONFIG_AC97_BUS=m
-CONFIG_HID=m
-CONFIG_HID_BATTERY_STRENGTH=y
-CONFIG_UHID=m
-CONFIG_HID_GENERIC=m
-CONFIG_HID_A4TECH=m
-CONFIG_HID_ACCUTOUCH=m
-CONFIG_HID_ACRUX=m
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=m
-CONFIG_HID_APPLEIR=m
-CONFIG_HID_ASUS=m
-CONFIG_HID_AUREAL=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_BETOP_FF=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CORSAIR=m
-CONFIG_HID_PRODIKEYS=m
-CONFIG_HID_CMEDIA=m
-CONFIG_HID_CP2112=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_DRAGONRISE=m
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=m
-CONFIG_HID_ELAN=m
-CONFIG_HID_ELECOM=m
-CONFIG_HID_ELO=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_HOLTEK=m
-CONFIG_HOLTEK_FF=y
-CONFIG_HID_GOOGLE_HAMMER=m
-CONFIG_HID_GT683R=m
-CONFIG_HID_KEYTOUCH=m
-CONFIG_HID_KYE=m
-CONFIG_HID_UCLOGIC=m
-CONFIG_HID_WALTOP=m
-CONFIG_HID_GYRATION=m
-CONFIG_HID_ICADE=m
-CONFIG_HID_ITE=m
-CONFIG_HID_JABRA=m
-CONFIG_HID_TWINHAN=m
-CONFIG_HID_KENSINGTON=m
-CONFIG_HID_LCPOWER=m
-CONFIG_HID_LED=m
-CONFIG_HID_LENOVO=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_LOGITECH_DJ=m
-CONFIG_HID_LOGITECH_HIDPP=m
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_HID_MAGICMOUSE=m
-CONFIG_HID_MAYFLASH=m
-# CONFIG_HID_REDRAGON is not set
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_MULTITOUCH=m
-CONFIG_HID_NTI=m
-CONFIG_HID_NTRIG=m
-CONFIG_HID_ORTEK=m
-CONFIG_HID_PANTHERLORD=m
-CONFIG_HID_PENMOUNT=m
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_PICOLCD=m
-CONFIG_HID_PICOLCD_FB=y
-CONFIG_HID_PICOLCD_BACKLIGHT=y
-CONFIG_HID_PICOLCD_LCD=y
-CONFIG_HID_PICOLCD_LEDS=y
-CONFIG_HID_PICOLCD_CIR=y
-CONFIG_HID_PLANTRONICS=m
-CONFIG_HID_PRIMAX=m
-CONFIG_HID_RETRODE=m
-CONFIG_HID_ROCCAT=m
-CONFIG_HID_SAITEK=m
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=m
-CONFIG_SONY_FF=y
-CONFIG_HID_SPEEDLINK=m
-CONFIG_HID_STEELSERIES=m
-CONFIG_HID_SUNPLUS=m
-CONFIG_HID_RMI=m
-CONFIG_HID_GREENASIA=m
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_HYPERV_MOUSE=m
-CONFIG_HID_SMARTJOYPLUS=m
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TIVO=m
-CONFIG_HID_TOPSEED=m
-CONFIG_HID_THINGM=m
-CONFIG_HID_THRUSTMASTER=m
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_UDRAW_PS3=m
-CONFIG_HID_WACOM=m
-CONFIG_HID_WIIMOTE=m
-CONFIG_HID_XINMO=m
-CONFIG_HID_ZEROPLUS=m
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=m
-CONFIG_HID_SENSOR_HUB=m
-# CONFIG_HID_SENSOR_CUSTOM_SENSOR is not set
-CONFIG_HID_ALPS=m
-CONFIG_USB_HID=m
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-
-#
-CONFIG_I2C_HID=m
-CONFIG_INTEL_ISH_HID=m
-CONFIG_USB=m
-CONFIG_USB_DYNAMIC_MINORS=y
-CONFIG_USB_OTG=y
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-CONFIG_USB_OTG_FSM=m
-CONFIG_USB_LEDS_TRIGGER_USBPORT=m
-CONFIG_USB_MON=m
-CONFIG_USB_WUSB=m
-CONFIG_USB_WUSB_CBAF=m
-# CONFIG_USB_WUSB_CBAF_DEBUG is not set
-CONFIG_USB_XHCI_HCD=m
-# CONFIG_USB_XHCI_DBGCAP is not set
-CONFIG_USB_XHCI_PCI=m
-CONFIG_USB_XHCI_PLATFORM=m
-CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_PCI=m
-CONFIG_USB_EHCI_HCD_PLATFORM=m
-CONFIG_USB_FOTG210_HCD=m
-CONFIG_USB_MAX3421_HCD=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_OHCI_HCD_PCI=m
-# CONFIG_USB_OHCI_HCD_SSB is not set
-CONFIG_USB_OHCI_HCD_PLATFORM=m
-CONFIG_USB_UHCI_HCD=m
-CONFIG_USB_U132_HCD=m
-CONFIG_USB_SL811_HCD=m
-# CONFIG_USB_SL811_HCD_ISO is not set
-CONFIG_USB_SL811_CS=m
-CONFIG_USB_WHCI_HCD=m
-CONFIG_USB_HWA_HCD=m
-CONFIG_USB_HCD_BCMA=m
-CONFIG_USB_HCD_SSB=m
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_WDM=m
-CONFIG_USB_TMC=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_STORAGE_REALTEK=m
-CONFIG_REALTEK_AUTOPM=y
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_ISD200=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_STORAGE_ALAUDA=m
-CONFIG_USB_STORAGE_ONETOUCH=m
-CONFIG_USB_STORAGE_KARMA=m
-CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-CONFIG_USB_STORAGE_ENE_UB6250=m
-CONFIG_USB_UAS=m
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USBIP_CORE=m
-CONFIG_USBIP_VHCI_HCD=m
-CONFIG_USBIP_VHCI_HC_PORTS=8
-CONFIG_USBIP_VHCI_NR_HCS=1
-CONFIG_USBIP_HOST=m
-CONFIG_USBIP_VUDC=m
-# CONFIG_USBIP_DEBUG is not set
-CONFIG_USB_MUSB_HDRC=m
-CONFIG_USB_MUSB_HOST=y
-# CONFIG_USB_MUSB_GADGET is not set
-# CONFIG_USB_MUSB_DUAL_ROLE is not set
-
-#
-# Platform Glue Layer
-#
-
-#
-# MUSB DMA mode
-#
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_DWC3=m
-CONFIG_USB_DWC3_HOST=y
-# CONFIG_USB_DWC3_GADGET is not set
-# CONFIG_USB_DWC3_DUAL_ROLE is not set
-
-#
-# Platform Glue Driver Support
-#
-CONFIG_USB_DWC3_PCI=m
-CONFIG_USB_DWC3_HAPS=m
-CONFIG_USB_DWC2=m
-CONFIG_USB_DWC2_HOST=y
-
-#
-# Gadget/Dual-role mode requires USB Gadget support to be enabled
-#
-# CONFIG_USB_DWC2_PERIPHERAL is not set
-# CONFIG_USB_DWC2_DUAL_ROLE is not set
-CONFIG_USB_DWC2_PCI=m
-# CONFIG_USB_DWC2_DEBUG is not set
-# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
-CONFIG_USB_USS720=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_SIMPLE=m
-CONFIG_USB_SERIAL_AIRCABLE=m
-CONFIG_USB_SERIAL_ARK3116=m
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_CH341=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CP210X=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_F81232=m
-CONFIG_USB_SERIAL_F8153X=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_IUU=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_METRO=m
-CONFIG_USB_SERIAL_MOS7720=m
-CONFIG_USB_SERIAL_MOS7715_PARPORT=y
-CONFIG_USB_SERIAL_MOS7840=m
-CONFIG_USB_SERIAL_MXUPORT=m
-CONFIG_USB_SERIAL_NAVMAN=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_OTI6858=m
-CONFIG_USB_SERIAL_QCAUX=m
-CONFIG_USB_SERIAL_QUALCOMM=m
-CONFIG_USB_SERIAL_SPCP8X5=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_SAFE_PADDED=y
-CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-CONFIG_USB_SERIAL_SYMBOL=m
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-CONFIG_USB_SERIAL_WWAN=m
-CONFIG_USB_SERIAL_OPTION=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_SERIAL_OPTICON=m
-CONFIG_USB_SERIAL_XSENS_MT=m
-CONFIG_USB_SERIAL_WISHBONE=m
-CONFIG_USB_SERIAL_SSU100=m
-CONFIG_USB_SERIAL_QT2=m
-CONFIG_USB_SERIAL_UPD78F0730=m
-CONFIG_USB_SERIAL_DEBUG=m
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_ADUTUX=m
-CONFIG_USB_SEVSEG=m
-CONFIG_USB_RIO500=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_CYPRESS_CY7C63=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_IDMOUSE=m
-CONFIG_USB_FTDI_ELAN=m
-CONFIG_USB_APPLEDISPLAY=m
-CONFIG_USB_SISUSBVGA=m
-CONFIG_USB_SISUSBVGA_CON=y
-CONFIG_USB_LD=m
-CONFIG_USB_TRANCEVIBRATOR=m
-CONFIG_USB_IOWARRIOR=m
-CONFIG_USB_TEST=m
-CONFIG_USB_ISIGHTFW=m
-CONFIG_USB_YUREX=m
-CONFIG_USB_EZUSB_FX2=m
-CONFIG_USB_HUB_USB251XB=m
-CONFIG_USB_HSIC_USB3503=m
-CONFIG_USB_HSIC_USB4604=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_CXACRU=m
-CONFIG_USB_UEAGLEATM=m
-CONFIG_USB_XUSBATM=m
-CONFIG_USB_PHY=y
-CONFIG_NOP_USB_XCEIV=m
-# CONFIG_USB_GPIO_VBUS is not set
-CONFIG_TAHVO_USB=m
-# CONFIG_TAHVO_USB_HOST_BY_DEFAULT is not set
-CONFIG_USB_ISP1301=m
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
-# CONFIG_U_SERIAL_CONSOLE is not set
-
-#
-# USB Peripheral Controller
-#
-# CONFIG_USB_FOTG210_UDC is not set
-# CONFIG_USB_GR_UDC is not set
-# CONFIG_USB_R8A66597 is not set
-# CONFIG_USB_PXA27X is not set
-# CONFIG_USB_MV_UDC is not set
-# CONFIG_USB_MV_U3D is not set
-# CONFIG_USB_M66592 is not set
-# CONFIG_USB_BDC_UDC is not set
-# CONFIG_USB_AMD5536UDC is not set
-# CONFIG_USB_NET2272 is not set
-# CONFIG_USB_NET2280 is not set
-# CONFIG_USB_GOKU is not set
-# CONFIG_USB_EG20T is not set
-# CONFIG_USB_DUMMY_HCD is not set
-CONFIG_USB_LIBCOMPOSITE=m
-CONFIG_USB_F_ACM=m
-CONFIG_USB_U_SERIAL=m
-CONFIG_USB_U_ETHER=m
-CONFIG_USB_U_AUDIO=m
-CONFIG_USB_F_SERIAL=m
-CONFIG_USB_F_OBEX=m
-CONFIG_USB_F_NCM=m
-CONFIG_USB_F_ECM=m
-CONFIG_USB_F_PHONET=m
-CONFIG_USB_F_SUBSET=m
-CONFIG_USB_F_RNDIS=m
-CONFIG_USB_F_MASS_STORAGE=m
-CONFIG_USB_F_UAC2=m
-CONFIG_USB_F_UVC=m
-CONFIG_USB_F_MIDI=m
-CONFIG_USB_F_HID=m
-CONFIG_USB_F_PRINTER=m
-# CONFIG_USB_CONFIGFS is not set
-# CONFIG_USB_ZERO is not set
-CONFIG_USB_AUDIO=m
-# CONFIG_GADGET_UAC1 is not set
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-# CONFIG_USB_ETH_EEM is not set
-CONFIG_USB_G_NCM=m
-CONFIG_USB_GADGETFS=m
-# CONFIG_USB_FUNCTIONFS is not set
-CONFIG_USB_MASS_STORAGE=m
-# CONFIG_USB_GADGET_TARGET is not set
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_MIDI_GADGET=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_NOKIA=m
-CONFIG_USB_G_ACM_MS=m
-CONFIG_USB_G_MULTI=m
-CONFIG_USB_G_MULTI_RNDIS=y
-CONFIG_USB_G_MULTI_CDC=y
-CONFIG_USB_G_HID=m
-# CONFIG_USB_G_DBGP is not set
-CONFIG_USB_G_WEBCAM=m
-CONFIG_TYPEC=m
-CONFIG_TYPEC_TCPM=m
-CONFIG_TYPEC_TCPCI=m
-# CONFIG_TYPEC_RT1711H is not set
-CONFIG_TYPEC_FUSB302=m
-CONFIG_TYPEC_UCSI=m
-CONFIG_UCSI_ACPI=m
-CONFIG_TYPEC_TPS6598X=m
-
-#
-# USB Type-C Multiplexer/DeMultiplexer Switch support
-#
-CONFIG_TYPEC_MUX_PI3USB30532=m
-
-#
-# USB Type-C Alternate Mode drivers
-#
-# CONFIG_TYPEC_DP_ALTMODE is not set
-CONFIG_USB_ROLES_INTEL_XHCI=m
-CONFIG_USB_LED_TRIG=y
-CONFIG_USB_ROLE_SWITCH=m
-CONFIG_UWB=m
-CONFIG_UWB_HWA=m
-CONFIG_UWB_WHCI=m
-CONFIG_UWB_I1480U=m
-CONFIG_MMC=m
-CONFIG_MMC_BLOCK=m
-CONFIG_MMC_BLOCK_MINORS=8
-CONFIG_SDIO_UART=m
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_SDHCI=m
-CONFIG_MMC_SDHCI_PCI=m
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI_ACPI=m
-CONFIG_MMC_SDHCI_PLTFM=m
-CONFIG_MMC_SDHCI_F_SDH30=m
-CONFIG_MMC_WBSD=m
-CONFIG_MMC_TIFM_SD=m
-CONFIG_MMC_SPI=m
-CONFIG_MMC_SDRICOH_CS=m
-CONFIG_MMC_CB710=m
-CONFIG_MMC_VIA_SDMMC=m
-CONFIG_MMC_VUB300=m
-CONFIG_MMC_USHC=m
-CONFIG_MMC_USDHI6ROL0=m
-CONFIG_MMC_REALTEK_PCI=m
-CONFIG_MMC_REALTEK_USB=m
-CONFIG_MMC_CQHCI=m
-# CONFIG_MMC_TOSHIBA_PCI is not set
-# CONFIG_MMC_MTK is not set
-CONFIG_MMC_SDHCI_XENON=m
-CONFIG_MEMSTICK=m
-# CONFIG_MEMSTICK_DEBUG is not set
-
-#
-# MemoryStick drivers
-#
-# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
-CONFIG_MSPRO_BLOCK=m
-CONFIG_MS_BLOCK=m
-
-#
-# MemoryStick Host Controller Drivers
-#
-CONFIG_MEMSTICK_TIFM_MS=m
-CONFIG_MEMSTICK_JMICRON_38X=m
-CONFIG_MEMSTICK_R592=m
-CONFIG_MEMSTICK_REALTEK_PCI=m
-CONFIG_MEMSTICK_REALTEK_USB=m
-CONFIG_LEDS_CLASS_FLASH=m
-CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y
-CONFIG_LEDS_88PM860X=m
-CONFIG_LEDS_APU=m
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_AS3645A=m
-CONFIG_LEDS_LM3530=m
-CONFIG_LEDS_LM3642=m
-# CONFIG_LEDS_LM3601X is not set
-CONFIG_LEDS_LP3952=m
-CONFIG_LEDS_LP55XX_COMMON=m
-CONFIG_LEDS_LP5521=m
-CONFIG_LEDS_LP5523=m
-CONFIG_LEDS_LP5562=m
-CONFIG_LEDS_LP8501=m
-CONFIG_LEDS_LP8788=m
-CONFIG_LEDS_CLEVO_MAIL=m
-CONFIG_LEDS_PCA963X=m
-CONFIG_LEDS_WM831X_STATUS=m
-CONFIG_LEDS_WM8350=m
-CONFIG_LEDS_DA903X=m
-CONFIG_LEDS_DA9052=m
-CONFIG_LEDS_DAC124S085=m
-CONFIG_LEDS_PWM=m
-CONFIG_LEDS_REGULATOR=m
-CONFIG_LEDS_INTEL_SS4200=m
-CONFIG_LEDS_LT3593=m
-CONFIG_LEDS_ADP5520=m
-CONFIG_LEDS_MC13783=m
-CONFIG_LEDS_TCA6507=m
-CONFIG_LEDS_MAX8997=m
-CONFIG_LEDS_LM355x=m
-CONFIG_LEDS_MENF21BMC=m
-CONFIG_LEDS_BLINKM=m
-CONFIG_LEDS_MLXCPLD=m
-CONFIG_LEDS_MLXREG=m
-CONFIG_LEDS_USER=m
-CONFIG_LEDS_NIC78BX=m
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_ONESHOT=m
-CONFIG_LEDS_TRIGGER_DISK=y
-CONFIG_LEDS_TRIGGER_MTD=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_LEDS_TRIGGER_BACKLIGHT=m
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_ACTIVITY=m
-# CONFIG_LEDS_TRIGGER_GPIO is not set
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-CONFIG_LEDS_TRIGGER_TRANSIENT=m
-CONFIG_LEDS_TRIGGER_CAMERA=m
-CONFIG_LEDS_TRIGGER_PANIC=y
-CONFIG_LEDS_TRIGGER_PATTERN=m
-CONFIG_LEDS_TRIGGER_NETDEV=m
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_A11Y_BRAILLE_CONSOLE=y
-CONFIG_INFINIBAND=m
-CONFIG_INFINIBAND_USER_MAD=m
-CONFIG_INFINIBAND_USER_ACCESS=m
-CONFIG_INFINIBAND_EXP_LEGACY_VERBS_NEW_UAPI=y
-CONFIG_INFINIBAND_USER_MEM=y
-CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
-CONFIG_INFINIBAND_ADDR_TRANS=y
-CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
-CONFIG_INFINIBAND_MTHCA=m
-# CONFIG_INFINIBAND_MTHCA_DEBUG is not set
-CONFIG_INFINIBAND_QIB=m
-CONFIG_INFINIBAND_QIB_DCA=y
-CONFIG_INFINIBAND_CXGB3=m
-CONFIG_INFINIBAND_CXGB4=m
-CONFIG_INFINIBAND_I40IW=m
-CONFIG_MLX4_INFINIBAND=m
-CONFIG_INFINIBAND_NES=m
-# CONFIG_INFINIBAND_NES_DEBUG is not set
-CONFIG_INFINIBAND_OCRDMA=m
-CONFIG_INFINIBAND_VMWARE_PVRDMA=m
-CONFIG_INFINIBAND_USNIC=m
-CONFIG_INFINIBAND_IPOIB=m
-# CONFIG_INFINIBAND_IPOIB_CM is not set
-# CONFIG_INFINIBAND_IPOIB_DEBUG is not set
-CONFIG_INFINIBAND_SRP=m
-CONFIG_INFINIBAND_SRPT=m
-CONFIG_INFINIBAND_ISER=m
-CONFIG_INFINIBAND_ISERT=m
-CONFIG_INFINIBAND_OPA_VNIC=m
-CONFIG_INFINIBAND_RDMAVT=m
-CONFIG_RDMA_RXE=m
-CONFIG_INFINIBAND_HFI1=m
-# CONFIG_HFI1_DEBUG_SDMA_ORDER is not set
-# CONFIG_SDMA_VERBOSITY is not set
-CONFIG_INFINIBAND_BNXT_RE=m
-CONFIG_EDAC_GHES=y
-CONFIG_EDAC_AMD64=m
-# CONFIG_EDAC_AMD64_ERROR_INJECTION is not set
-CONFIG_EDAC_E752X=m
-CONFIG_EDAC_I82975X=m
-CONFIG_EDAC_I3000=m
-CONFIG_EDAC_I3200=m
-CONFIG_EDAC_IE31200=m
-CONFIG_EDAC_X38=m
-CONFIG_EDAC_I5400=m
-CONFIG_EDAC_I7CORE=m
-CONFIG_EDAC_I5000=m
-CONFIG_EDAC_I5100=m
-CONFIG_EDAC_I7300=m
-CONFIG_EDAC_SBRIDGE=m
-CONFIG_EDAC_SKX=m
-CONFIG_EDAC_PND2=m
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_INTF_PROC is not set
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-CONFIG_RTC_DRV_88PM860X=m
-CONFIG_RTC_DRV_88PM80X=m
-CONFIG_RTC_DRV_LP8788=m
-CONFIG_RTC_DRV_MAX8907=m
-CONFIG_RTC_DRV_MAX8925=m
-CONFIG_RTC_DRV_MAX8998=m
-CONFIG_RTC_DRV_MAX8997=m
-CONFIG_RTC_DRV_ISL1208=m
-CONFIG_RTC_DRV_ISL12022=m
-CONFIG_RTC_DRV_PCF8523=m
-CONFIG_RTC_DRV_PCF85063=m
-CONFIG_RTC_DRV_PCF85363=m
-CONFIG_RTC_DRV_BQ32K=m
-CONFIG_RTC_DRV_PALMAS=m
-CONFIG_RTC_DRV_TPS6586X=m
-CONFIG_RTC_DRV_TPS65910=m
-CONFIG_RTC_DRV_TPS80031=m
-CONFIG_RTC_DRV_RC5T583=m
-CONFIG_RTC_DRV_S5M=m
-CONFIG_RTC_DRV_M41T93=m
-CONFIG_RTC_DRV_M41T94=m
-CONFIG_RTC_DRV_DS1302=m
-CONFIG_RTC_DRV_DS1305=m
-CONFIG_RTC_DRV_DS1343=m
-CONFIG_RTC_DRV_DS1347=m
-CONFIG_RTC_DRV_DS1390=m
-CONFIG_RTC_DRV_MAX6916=m
-CONFIG_RTC_DRV_R9701=m
-CONFIG_RTC_DRV_RX4581=m
-CONFIG_RTC_DRV_RX6110=m
-CONFIG_RTC_DRV_RS5C348=m
-CONFIG_RTC_DRV_MAX6902=m
-CONFIG_RTC_DRV_PCF2123=m
-CONFIG_RTC_DRV_MCP795=m
-CONFIG_RTC_DRV_PCF2127=m
-CONFIG_RTC_DRV_DA9052=m
-CONFIG_RTC_DRV_DA9055=m
-CONFIG_RTC_DRV_DA9063=m
-CONFIG_RTC_DRV_WM831X=m
-CONFIG_RTC_DRV_WM8350=m
-CONFIG_RTC_DRV_CROS_EC=m
-CONFIG_RTC_DRV_FTRTC010=m
-CONFIG_RTC_DRV_PCAP=m
-CONFIG_RTC_DRV_MC13XXX=m
-CONFIG_RTC_DRV_HID_SENSOR_TIME=m
-CONFIG_ALTERA_MSGDMA=m
-CONFIG_INTEL_IOATDMA=m
-CONFIG_INTEL_MIC_X100_DMA=m
-CONFIG_QCOM_HIDMA_MGMT=m
-CONFIG_QCOM_HIDMA=m
-CONFIG_DW_DMAC_CORE=m
-CONFIG_DW_DMAC=m
-CONFIG_DW_DMAC_PCI=m
-CONFIG_DMATEST=m
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_SW_SYNC=y
-CONFIG_UDMABUF=y
-CONFIG_DCA=m
-CONFIG_AUXDISPLAY=y
-CONFIG_HD44780=m
-CONFIG_KS0108=m
-CONFIG_KS0108_PORT=0x378
-CONFIG_KS0108_DELAY=2
-CONFIG_CFAG12864B=m
-CONFIG_CFAG12864B_RATE=20
-CONFIG_IMG_ASCII_LCD=m
-CONFIG_PANEL=m
-CONFIG_PANEL_PARPORT=0
-CONFIG_PANEL_PROFILE=5
-# CONFIG_PANEL_CHANGE_MESSAGE is not set
-CONFIG_CHARLCD=m
-CONFIG_UIO=m
-CONFIG_UIO_CIF=m
-# CONFIG_UIO_PDRV_GENIRQ is not set
-CONFIG_UIO_DMEM_GENIRQ=m
-CONFIG_UIO_AEC=m
-CONFIG_UIO_SERCOS3=m
-CONFIG_UIO_PCI_GENERIC=m
-CONFIG_UIO_NETX=m
-# CONFIG_UIO_PRUSS is not set
-CONFIG_UIO_MF624=m
-CONFIG_UIO_HV_GENERIC=m
-CONFIG_VFIO_IOMMU_TYPE1=m
-CONFIG_VFIO_VIRQFD=m
-CONFIG_VFIO=m
-# CONFIG_VFIO_NOIOMMU is not set
-CONFIG_VFIO_PCI=m
-CONFIG_VFIO_PCI_VGA=y
-CONFIG_VFIO_PCI_MMAP=y
-CONFIG_VFIO_PCI_INTX=y
-CONFIG_VFIO_PCI_IGD=y
-CONFIG_VFIO_MDEV=m
-CONFIG_VFIO_MDEV_DEVICE=m
-CONFIG_IRQ_BYPASS_MANAGER=m
-CONFIG_VIRT_DRIVERS=y
-CONFIG_VBOXGUEST=m
-CONFIG_VIRTIO=m
-CONFIG_VIRTIO_PCI=m
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_BALLOON=m
-CONFIG_VIRTIO_INPUT=m
-CONFIG_VIRTIO_MMIO=m
-# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
-CONFIG_HYPERV=m
-CONFIG_HYPERV_TSCPAGE=y
-CONFIG_HYPERV_UTILS=m
-CONFIG_HYPERV_BALLOON=m
-
-#
-# Xen driver support
-#
-CONFIG_XEN_BALLOON=y
-CONFIG_XEN_SELFBALLOONING=y
-CONFIG_XEN_BALLOON_MEMORY_HOTPLUG=y
-CONFIG_XEN_BALLOON_MEMORY_HOTPLUG_LIMIT=512
-CONFIG_XEN_SCRUB_PAGES=y
-CONFIG_XEN_DEV_EVTCHN=m
-CONFIG_XEN_BACKEND=y
-CONFIG_XENFS=m
-CONFIG_XEN_COMPAT_XENFS=y
-CONFIG_XEN_SYS_HYPERVISOR=y
-CONFIG_XEN_XENBUS_FRONTEND=y
-CONFIG_XEN_GNTDEV=m
-CONFIG_XEN_GRANT_DEV_ALLOC=m
-# CONFIG_XEN_GRANT_DMA_ALLOC is not set
-CONFIG_SWIOTLB_XEN=y
-CONFIG_XEN_TMEM=m
-CONFIG_XEN_PCIDEV_BACKEND=m
-CONFIG_XEN_PVCALLS_FRONTEND=m
-CONFIG_XEN_PVCALLS_BACKEND=y
-CONFIG_XEN_SCSI_BACKEND=m
-CONFIG_XEN_PRIVCMD=m
-CONFIG_XEN_ACPI_PROCESSOR=m
-# CONFIG_XEN_MCE_LOG is not set
-CONFIG_XEN_HAVE_PVMMU=y
-CONFIG_XEN_EFI=y
-CONFIG_XEN_AUTO_XLATE=y
-CONFIG_XEN_ACPI=y
-CONFIG_XEN_SYMS=y
-CONFIG_XEN_HAVE_VPMU=y
-CONFIG_STAGING=y
-CONFIG_PRISM2_USB=m
-CONFIG_COMEDI=m
-# CONFIG_COMEDI_DEBUG is not set
-CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
-CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
-CONFIG_COMEDI_MISC_DRIVERS=y
-CONFIG_COMEDI_BOND=m
-CONFIG_COMEDI_TEST=m
-CONFIG_COMEDI_PARPORT=m
-CONFIG_COMEDI_ISA_DRIVERS=y
-CONFIG_COMEDI_PCL711=m
-CONFIG_COMEDI_PCL724=m
-CONFIG_COMEDI_PCL726=m
-CONFIG_COMEDI_PCL730=m
-CONFIG_COMEDI_PCL812=m
-CONFIG_COMEDI_PCL816=m
-CONFIG_COMEDI_PCL818=m
-CONFIG_COMEDI_PCM3724=m
-CONFIG_COMEDI_AMPLC_DIO200_ISA=m
-CONFIG_COMEDI_AMPLC_PC236_ISA=m
-CONFIG_COMEDI_AMPLC_PC263_ISA=m
-CONFIG_COMEDI_RTI800=m
-CONFIG_COMEDI_RTI802=m
-# CONFIG_COMEDI_DAC02 is not set
-CONFIG_CRYPTO_AEGIS128=m
-CONFIG_CRYPTO_AEGIS128L=m
-CONFIG_CRYPTO_AEGIS256=m
-CONFIG_CRYPTO_AEGIS128_AESNI_SSE2=m
-CONFIG_CRYPTO_AEGIS128L_AESNI_SSE2=m
-CONFIG_CRYPTO_AEGIS256_AESNI_SSE2=m
-CONFIG_COMEDI_DAS16M1=m
-CONFIG_COMEDI_DAS08_ISA=m
-CONFIG_COMEDI_DAS16=m
-CONFIG_COMEDI_DAS800=m
-CONFIG_COMEDI_DAS1800=m
-CONFIG_COMEDI_DAS6402=m
-CONFIG_COMEDI_DT2801=m
-CONFIG_COMEDI_DT2811=m
-CONFIG_COMEDI_DT2814=m
-CONFIG_COMEDI_DT2815=m
-CONFIG_COMEDI_DT2817=m
-CONFIG_COMEDI_DT282X=m
-CONFIG_COMEDI_DMM32AT=m
-CONFIG_COMEDI_FL512=m
-CONFIG_COMEDI_AIO_AIO12_8=m
-CONFIG_COMEDI_AIO_IIRO_16=m
-CONFIG_COMEDI_II_PCI20KC=m
-CONFIG_COMEDI_C6XDIGIO=m
-CONFIG_COMEDI_MPC624=m
-CONFIG_COMEDI_ADQ12B=m
-CONFIG_COMEDI_NI_AT_A2150=m
-CONFIG_COMEDI_NI_AT_AO=m
-CONFIG_COMEDI_NI_ATMIO=m
-CONFIG_COMEDI_NI_ATMIO16D=m
-CONFIG_COMEDI_NI_LABPC_ISA=m
-CONFIG_COMEDI_PCMAD=m
-CONFIG_COMEDI_PCMDA12=m
-CONFIG_COMEDI_PCMMIO=m
-CONFIG_COMEDI_PCMUIO=m
-CONFIG_COMEDI_MULTIQ3=m
-CONFIG_COMEDI_S526=m
-CONFIG_COMEDI_PCI_DRIVERS=m
-CONFIG_COMEDI_8255_PCI=m
-CONFIG_COMEDI_ADDI_WATCHDOG=m
-CONFIG_COMEDI_ADDI_APCI_1032=m
-CONFIG_COMEDI_ADDI_APCI_1500=m
-CONFIG_COMEDI_ADDI_APCI_1516=m
-CONFIG_COMEDI_ADDI_APCI_1564=m
-CONFIG_COMEDI_ADDI_APCI_16XX=m
-CONFIG_COMEDI_ADDI_APCI_2032=m
-CONFIG_COMEDI_ADDI_APCI_2200=m
-CONFIG_COMEDI_ADDI_APCI_3120=m
-CONFIG_COMEDI_ADDI_APCI_3501=m
-CONFIG_COMEDI_ADDI_APCI_3XXX=m
-CONFIG_COMEDI_ADL_PCI6208=m
-CONFIG_COMEDI_ADL_PCI7X3X=m
-CONFIG_COMEDI_ADL_PCI8164=m
-CONFIG_COMEDI_ADL_PCI9111=m
-CONFIG_COMEDI_ADL_PCI9118=m
-CONFIG_COMEDI_ADV_PCI1710=m
-# CONFIG_COMEDI_ADV_PCI1720 is not set
-CONFIG_COMEDI_ADV_PCI1723=m
-CONFIG_COMEDI_ADV_PCI1724=m
-# CONFIG_COMEDI_ADV_PCI1760 is not set
-CONFIG_COMEDI_ADV_PCI_DIO=m
-CONFIG_COMEDI_AMPLC_DIO200_PCI=m
-CONFIG_COMEDI_AMPLC_PC236_PCI=m
-CONFIG_COMEDI_AMPLC_PC263_PCI=m
-CONFIG_COMEDI_AMPLC_PCI224=m
-CONFIG_COMEDI_AMPLC_PCI230=m
-CONFIG_COMEDI_CONTEC_PCI_DIO=m
-CONFIG_COMEDI_DAS08_PCI=m
-CONFIG_COMEDI_DT3000=m
-CONFIG_COMEDI_DYNA_PCI10XX=m
-CONFIG_COMEDI_GSC_HPDI=m
-CONFIG_COMEDI_MF6X4=m
-CONFIG_COMEDI_ICP_MULTI=m
-CONFIG_COMEDI_DAQBOARD2000=m
-CONFIG_COMEDI_JR3_PCI=m
-CONFIG_COMEDI_KE_COUNTER=m
-CONFIG_COMEDI_CB_PCIDAS64=m
-CONFIG_COMEDI_CB_PCIDAS=m
-CONFIG_COMEDI_CB_PCIDDA=m
-CONFIG_COMEDI_CB_PCIMDAS=m
-CONFIG_COMEDI_CB_PCIMDDA=m
-CONFIG_COMEDI_ME4000=m
-CONFIG_COMEDI_ME_DAQ=m
-CONFIG_COMEDI_NI_6527=m
-CONFIG_COMEDI_NI_65XX=m
-CONFIG_COMEDI_NI_660X=m
-CONFIG_COMEDI_NI_670X=m
-CONFIG_COMEDI_NI_LABPC_PCI=m
-CONFIG_COMEDI_NI_PCIDIO=m
-CONFIG_COMEDI_NI_PCIMIO=m
-CONFIG_COMEDI_RTD520=m
-CONFIG_COMEDI_S626=m
-CONFIG_COMEDI_MITE=m
-CONFIG_COMEDI_NI_TIOCMD=m
-CONFIG_COMEDI_PCMCIA_DRIVERS=m
-CONFIG_COMEDI_CB_DAS16_CS=m
-CONFIG_COMEDI_DAS08_CS=m
-CONFIG_COMEDI_NI_DAQ_700_CS=m
-CONFIG_COMEDI_NI_DAQ_DIO24_CS=m
-CONFIG_COMEDI_NI_LABPC_CS=m
-CONFIG_COMEDI_NI_MIO_CS=m
-CONFIG_COMEDI_QUATECH_DAQP_CS=m
-CONFIG_COMEDI_USB_DRIVERS=m
-CONFIG_COMEDI_DT9812=m
-CONFIG_COMEDI_NI_USB6501=m
-CONFIG_COMEDI_USBDUX=m
-CONFIG_COMEDI_USBDUXFAST=m
-CONFIG_COMEDI_USBDUXSIGMA=m
-CONFIG_COMEDI_VMK80XX=m
-CONFIG_COMEDI_8254=m
-CONFIG_COMEDI_8255=m
-# CONFIG_COMEDI_8255_SA is not set
-CONFIG_COMEDI_KCOMEDILIB=m
-CONFIG_COMEDI_AMPLC_DIO200=m
-CONFIG_COMEDI_AMPLC_PC236=m
-CONFIG_COMEDI_DAS08=m
-CONFIG_COMEDI_ISADMA=m
-CONFIG_COMEDI_NI_LABPC=m
-CONFIG_COMEDI_NI_LABPC_ISADMA=m
-CONFIG_COMEDI_NI_TIO=m
-CONFIG_RTL8192U=m
-CONFIG_RTLLIB=m
-CONFIG_RTLLIB_CRYPTO_CCMP=m
-CONFIG_RTLLIB_CRYPTO_TKIP=m
-CONFIG_RTLLIB_CRYPTO_WEP=m
-CONFIG_RTL8192E=m
-CONFIG_RTL8723BS=m
-CONFIG_R8712U=m
-CONFIG_R8188EU=m
-CONFIG_88EU_AP_MODE=y
-CONFIG_R8822BE=m
-CONFIG_RTLWIFI_DEBUG_ST=y
-CONFIG_RTS5208=m
-CONFIG_VT6655=m
-CONFIG_VT6656=m
-
-#
-# IIO staging drivers
-#
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16203=m
-CONFIG_ADIS16240=m
-
-#
-# Analog to digital converters
-#
-CONFIG_AD7606=m
-CONFIG_AD7606_IFACE_PARALLEL=m
-CONFIG_AD7606_IFACE_SPI=m
-CONFIG_AD7780=m
-CONFIG_AD7816=m
-CONFIG_AD7192=m
-CONFIG_AD7280=m
-
-#
-# Analog digital bi-direction converters
-#
-CONFIG_ADT7316=m
-CONFIG_ADT7316_SPI=m
-CONFIG_ADT7316_I2C=m
-
-#
-# Capacitance to digital converters
-#
-CONFIG_AD7150=m
-CONFIG_AD7152=m
-CONFIG_AD7746=m
-
-#
-# Direct Digital Synthesis
-#
-CONFIG_AD9832=m
-CONFIG_AD9834=m
-
-#
-# Network Analyzer, Impedance Converters
-#
-CONFIG_AD5933=m
-
-#
-# Active energy metering IC
-#
-CONFIG_ADE7854=m
-CONFIG_ADE7854_I2C=m
-CONFIG_ADE7854_SPI=m
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S90=m
-CONFIG_AD2S1210=m
-# CONFIG_FB_SM750 is not set
-CONFIG_FB_XGI=m
-
-#
-# Speakup console speech
-#
-CONFIG_SPEAKUP=m
-CONFIG_SPEAKUP_SYNTH_ACNTSA=m
-CONFIG_SPEAKUP_SYNTH_APOLLO=m
-CONFIG_SPEAKUP_SYNTH_AUDPTR=m
-CONFIG_SPEAKUP_SYNTH_BNS=m
-CONFIG_SPEAKUP_SYNTH_DECTLK=m
-CONFIG_SPEAKUP_SYNTH_DECEXT=m
-CONFIG_SPEAKUP_SYNTH_LTLK=m
-CONFIG_SPEAKUP_SYNTH_SOFT=m
-CONFIG_SPEAKUP_SYNTH_SPKOUT=m
-CONFIG_SPEAKUP_SYNTH_TXPRT=m
-CONFIG_SPEAKUP_SYNTH_DUMMY=m
-CONFIG_STAGING_MEDIA=y
-CONFIG_I2C_BCM2048=m
-# CONFIG_VIDEO_ZORAN is not set
-
-#
-# Android
-#
-CONFIG_ASHMEM=m
-# CONFIG_ANDROID_VSOC is not set
-CONFIG_ION=y
-CONFIG_ION_SYSTEM_HEAP=y
-CONFIG_ION_CARVEOUT_HEAP=y
-CONFIG_ION_CHUNK_HEAP=y
-CONFIG_LTE_GDM724X=m
-CONFIG_FIREWIRE_SERIAL=m
-CONFIG_FWTTY_MAX_TOTAL_PORTS=64
-CONFIG_FWTTY_MAX_CARD_PORTS=32
-CONFIG_MTD_SPINAND_MT29F=m
-# CONFIG_MTD_SPINAND_ONDIEECC is not set
-CONFIG_DGNC=m
-# CONFIG_GS_FPGABOOT is not set
-CONFIG_UNISYSSPAR=y
-# CONFIG_FB_TFT is not set
-# CONFIG_WILC1000_SDIO is not set
-# CONFIG_WILC1000_SPI is not set
-# CONFIG_MOST is not set
-CONFIG_KS7010=m
-CONFIG_GREYBUS=m
-CONFIG_GREYBUS_ES2=m
-CONFIG_GREYBUS_AUDIO=m
-CONFIG_GREYBUS_BOOTROM=m
-CONFIG_GREYBUS_FIRMWARE=m
-CONFIG_GREYBUS_HID=m
-CONFIG_GREYBUS_LIGHT=m
-CONFIG_GREYBUS_LOG=m
-CONFIG_GREYBUS_LOOPBACK=m
-CONFIG_GREYBUS_POWER=m
-CONFIG_GREYBUS_RAW=m
-CONFIG_GREYBUS_VIBRATOR=m
-CONFIG_GREYBUS_BRIDGED_PHY=m
-CONFIG_GREYBUS_GPIO=m
-CONFIG_GREYBUS_I2C=m
-CONFIG_GREYBUS_PWM=m
-CONFIG_GREYBUS_SDIO=m
-CONFIG_GREYBUS_SPI=m
-CONFIG_GREYBUS_UART=m
-CONFIG_GREYBUS_USB=m
-CONFIG_DRM_VBOXVIDEO=m
-CONFIG_PI433=m
-CONFIG_MTK_MMC=m
-# CONFIG_MTK_AEE_KDUMP is not set
-# CONFIG_MTK_MMC_CD_POLL is not set
-
-#
-# Gasket devices
-#
-# CONFIG_STAGING_GASKET_FRAMEWORK is not set
-# CONFIG_XIL_AXIS_FIFO is not set
-CONFIG_ACER_WMI=m
-CONFIG_ACER_WIRELESS=m
-CONFIG_ACERHDF=m
-CONFIG_ALIENWARE_WMI=m
-CONFIG_ASUS_LAPTOP=m
-CONFIG_DELL_SMBIOS=m
-CONFIG_DELL_SMBIOS_WMI=y
-CONFIG_DELL_SMBIOS_SMM=y
-CONFIG_DELL_LAPTOP=m
-CONFIG_DELL_WMI=m
-CONFIG_DELL_WMI_DESCRIPTOR=m
-CONFIG_DELL_WMI_AIO=m
-CONFIG_DELL_WMI_LED=m
-CONFIG_DELL_SMO8800=m
-CONFIG_FUJITSU_LAPTOP=m
-CONFIG_FUJITSU_TABLET=m
-CONFIG_AMILO_RFKILL=m
-CONFIG_GPD_POCKET_FAN=m
-CONFIG_HP_ACCEL=m
-CONFIG_HP_WIRELESS=m
-CONFIG_HP_WMI=m
-CONFIG_LG_LAPTOP=m
-CONFIG_MSI_LAPTOP=m
-CONFIG_PANASONIC_LAPTOP=m
-CONFIG_COMPAL_LAPTOP=m
-CONFIG_SONY_LAPTOP=m
-CONFIG_SONYPI_COMPAT=y
-CONFIG_IDEAPAD_LAPTOP=m
-CONFIG_SURFACE3_WMI=m
-CONFIG_THINKPAD_ACPI=m
-CONFIG_THINKPAD_ACPI_ALSA_SUPPORT=y
-# CONFIG_THINKPAD_ACPI_DEBUGFACILITIES is not set
-# CONFIG_THINKPAD_ACPI_DEBUG is not set
-CONFIG_THINKPAD_ACPI_UNSAFE_LEDS=y
-CONFIG_THINKPAD_ACPI_VIDEO=y
-CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y
-CONFIG_SENSORS_HDAPS=m
-CONFIG_INTEL_MENLOW=m
-CONFIG_EEEPC_LAPTOP=m
-CONFIG_ASUS_WMI=m
-CONFIG_ASUS_NB_WMI=m
-CONFIG_EEEPC_WMI=m
-CONFIG_ACPI_WMI=m
-CONFIG_WMI_BMOF=m
-CONFIG_INTEL_WMI_THUNDERBOLT=m
-CONFIG_MSI_WMI=m
-CONFIG_PEAQ_WMI=m
-CONFIG_TOPSTAR_LAPTOP=m
-CONFIG_ACPI_TOSHIBA=m
-CONFIG_TOSHIBA_BT_RFKILL=m
-CONFIG_TOSHIBA_HAPS=m
-# CONFIG_TOSHIBA_WMI is not set
-CONFIG_ACPI_CMPC=m
-CONFIG_INTEL_CHT_INT33FE=m
-CONFIG_INTEL_INT0002_VGPIO=m
-CONFIG_INTEL_VBTN=m
-CONFIG_INTEL_IPS=m
-CONFIG_INTEL_PMC_CORE=y
-CONFIG_IBM_RTL=m
-CONFIG_SAMSUNG_LAPTOP=m
-CONFIG_MXM_WMI=m
-CONFIG_INTEL_OAKTRAIL=m
-CONFIG_SAMSUNG_Q10=m
-CONFIG_APPLE_GMUX=m
-CONFIG_INTEL_RST=m
-CONFIG_INTEL_SMARTCONNECT=m
-CONFIG_PVPANIC=m
-CONFIG_SURFACE_3_BUTTON=m
-CONFIG_INTEL_TURBO_MAX_3=y
-# CONFIG_TOUCHSCREEN_DMI is not set
-CONFIG_INTEL_CHTDC_TI_PWRBTN=m
-CONFIG_CHROME_PLATFORMS=y
-CONFIG_CHROMEOS_LAPTOP=m
-CONFIG_CHROMEOS_PSTORE=m
-# CONFIG_CHROMEOS_TBMC is not set
-CONFIG_CROS_EC_CTL=m
-# CONFIG_CROS_EC_I2C is not set
-# CONFIG_CROS_EC_SPI is not set
-CONFIG_CROS_EC_LPC=m
-# CONFIG_CROS_EC_LPC_MEC is not set
-CONFIG_CROS_EC_PROTO=y
-CONFIG_CROS_KBD_LED_BACKLIGHT=m
-CONFIG_MELLANOX_PLATFORM=y
-CONFIG_MLXREG_HOTPLUG=m
-# CONFIG_MLXREG_IO is not set
-CONFIG_COMMON_CLK_WM831X=m
-CONFIG_COMMON_CLK_SI5351=m
-CONFIG_COMMON_CLK_SI544=m
-CONFIG_COMMON_CLK_S2MPS11=m
-CONFIG_CLK_TWL6040=m
-CONFIG_COMMON_CLK_PALMAS=m
-CONFIG_COMMON_CLK_PWM=m
-CONFIG_HWSPINLOCK=y
-CONFIG_ALTERA_MBOX=m
-CONFIG_AMD_IOMMU_V2=m
-CONFIG_IRQ_REMAP=y
-CONFIG_REMOTEPROC=m
-CONFIG_RPMSG=m
-CONFIG_RPMSG_CHAR=m
-CONFIG_RPMSG_QCOM_GLINK_NATIVE=m
-CONFIG_RPMSG_QCOM_GLINK_RPM=m
-CONFIG_RPMSG_VIRTIO=m
-CONFIG_SOUNDWIRE=y
-
-#
-# SoundWire Devices
-#
-CONFIG_SOUNDWIRE_BUS=m
-CONFIG_SOUNDWIRE_CADENCE=m
-CONFIG_SOUNDWIRE_INTEL=m
-CONFIG_XILINX_VCU=m
-CONFIG_PM_DEVFREQ=y
-
-#
-# DEVFREQ Governors
-#
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_PERFORMANCE=y
-CONFIG_DEVFREQ_GOV_POWERSAVE=y
-CONFIG_DEVFREQ_GOV_USERSPACE=y
-CONFIG_DEVFREQ_GOV_PASSIVE=m
-
-#
-# DEVFREQ Drivers
-#
-# CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_EXTCON=y
-
-#
-# Extcon Device Drivers
-#
-CONFIG_EXTCON_ADC_JACK=m
-CONFIG_EXTCON_ARIZONA=m
-# CONFIG_EXTCON_AXP288 is not set
-CONFIG_EXTCON_GPIO=m
-CONFIG_EXTCON_INTEL_INT3496=m
-CONFIG_EXTCON_MAX14577=m
-# CONFIG_EXTCON_MAX3355 is not set
-# CONFIG_EXTCON_INTEL_CHT_WC is not set
-CONFIG_EXTCON_MAX77693=m
-CONFIG_EXTCON_MAX8997=m
-CONFIG_EXTCON_PALMAS=m
-CONFIG_EXTCON_RT8973A=m
-CONFIG_EXTCON_SM5502=m
-CONFIG_EXTCON_USB_GPIO=m
-CONFIG_EXTCON_USBC_CROS_EC=m
-CONFIG_MEMORY=y
-CONFIG_IIO=m
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_BUFFER_CB=m
-CONFIG_IIO_BUFFER_HW_CONSUMER=m
-CONFIG_IIO_KFIFO_BUF=m
-CONFIG_IIO_TRIGGERED_BUFFER=m
-CONFIG_IIO_CONFIGFS=m
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
-CONFIG_IIO_SW_DEVICE=m
-# CONFIG_IIO_SW_TRIGGER is not set
-CONFIG_IIO_TRIGGERED_EVENT=m
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16201=m
-CONFIG_ADIS16209=m
-CONFIG_ADXL345=m
-CONFIG_ADXL345_I2C=m
-CONFIG_ADXL345_SPI=m
-CONFIG_ADXL372_I2C=m
-CONFIG_ADXL372=m
-CONFIG_ADXL372_SPI=m
-CONFIG_BMA180=m
-CONFIG_BMA220=m
-CONFIG_BMC150_ACCEL=m
-CONFIG_BMC150_ACCEL_I2C=m
-CONFIG_BMC150_ACCEL_SPI=m
-CONFIG_DA280=m
-CONFIG_DA311=m
-CONFIG_DMARD09=m
-CONFIG_DMARD10=m
-CONFIG_HID_SENSOR_ACCEL_3D=m
-CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
-CONFIG_IIO_ST_ACCEL_3AXIS=m
-CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
-CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
-CONFIG_KXSD9=m
-CONFIG_KXSD9_SPI=m
-CONFIG_KXSD9_I2C=m
-CONFIG_KXCJK1013=m
-CONFIG_MC3230=m
-# CONFIG_MMA7455_I2C is not set
-# CONFIG_MMA7455_SPI is not set
-CONFIG_MMA7660=m
-CONFIG_MMA8452=m
-# CONFIG_MMA9551 is not set
-# CONFIG_MMA9553 is not set
-# CONFIG_MXC4005 is not set
-# CONFIG_MXC6255 is not set
-CONFIG_SCA3000=m
-# CONFIG_STK8312 is not set
-# CONFIG_STK8BA50 is not set
-
-#
-# Analog to digital converters
-#
-CONFIG_AD_SIGMA_DELTA=m
-CONFIG_AD7266=m
-CONFIG_AD7291=m
-CONFIG_AD7298=m
-CONFIG_AD7476=m
-CONFIG_AD7766=m
-CONFIG_AD7791=m
-CONFIG_AD7793=m
-CONFIG_AD7887=m
-CONFIG_AD7923=m
-CONFIG_AD799X=m
-CONFIG_AXP20X_ADC=m
-CONFIG_AXP288_ADC=m
-# CONFIG_CC10001_ADC is not set
-CONFIG_DLN2_ADC=m
-CONFIG_HI8435=m
-CONFIG_HX711=m
-# CONFIG_INA2XX_ADC is not set
-CONFIG_LP8788_ADC=m
-CONFIG_LTC2471=m
-CONFIG_LTC2485=m
-CONFIG_LTC2497=m
-CONFIG_MAX1027=m
-CONFIG_MAX11100=m
-CONFIG_MAX1118=m
-CONFIG_MAX1363=m
-CONFIG_MAX9611=m
-CONFIG_MCP320X=m
-CONFIG_MCP3422=m
-CONFIG_NAU7802=m
-# CONFIG_PALMAS_GPADC is not set
-CONFIG_QCOM_SPMI_IADC=m
-# CONFIG_QCOM_SPMI_VADC is not set
-CONFIG_STX104=m
-CONFIG_TI_ADC081C=m
-CONFIG_TI_ADC0832=m
-CONFIG_TI_ADC084S021=m
-CONFIG_TI_ADC12138=m
-CONFIG_TI_ADC108S102=m
-CONFIG_TI_ADC128S052=m
-CONFIG_TI_ADC161S626=m
-CONFIG_TI_ADS1015=m
-CONFIG_TI_ADS7950=m
-CONFIG_TI_AM335X_ADC=m
-CONFIG_TI_TLC4541=m
-CONFIG_TWL4030_MADC=m
-CONFIG_TWL6030_GPADC=m
-CONFIG_VIPERBOARD_ADC=m
-
-#
-# Analog Front Ends
-#
-
-#
-# Amplifiers
-#
-CONFIG_AD8366=m
-
-#
-# Chemical Sensors
-#
-CONFIG_ATLAS_PH_SENSOR=m
-# CONFIG_BME680 is not set
-CONFIG_CCS811=m
-# CONFIG_IAQCORE is not set
-# CONFIG_VZ89X is not set
-CONFIG_IIO_CROS_EC_SENSORS_CORE=m
-CONFIG_IIO_CROS_EC_SENSORS=m
-
-#
-# Hid Sensor IIO Common
-#
-CONFIG_HID_SENSOR_IIO_COMMON=m
-CONFIG_HID_SENSOR_IIO_TRIGGER=m
-
-#
-# SSP Sensor Common
-#
-# CONFIG_IIO_SSP_SENSORHUB is not set
-CONFIG_IIO_ST_SENSORS_I2C=m
-CONFIG_IIO_ST_SENSORS_SPI=m
-CONFIG_IIO_ST_SENSORS_CORE=m
-
-#
-# Counters
-#
-CONFIG_104_QUAD_8=m
-
-#
-# Digital to analog converters
-#
-CONFIG_AD5064=m
-CONFIG_AD5360=m
-CONFIG_AD5380=m
-CONFIG_AD5421=m
-CONFIG_AD5446=m
-CONFIG_AD5449=m
-CONFIG_AD5592R_BASE=m
-CONFIG_AD5592R=m
-CONFIG_AD5593R=m
-CONFIG_AD5504=m
-CONFIG_AD5624R_SPI=m
-CONFIG_LTC2632=m
-# CONFIG_AD5686_SPI is not set
-# CONFIG_AD5696_I2C is not set
-CONFIG_AD5755=m
-# CONFIG_AD5758 is not set
-CONFIG_AD5761=m
-CONFIG_AD5764=m
-CONFIG_AD5791=m
-CONFIG_AD7303=m
-CONFIG_CIO_DAC=m
-CONFIG_AD8801=m
-CONFIG_DS4424=m
-# CONFIG_M62332 is not set
-CONFIG_MAX517=m
-CONFIG_MCP4725=m
-CONFIG_MCP4922=m
-CONFIG_TI_DAC082S085=m
-# CONFIG_TI_DAC5571 is not set
-
-#
-# IIO dummy driver
-#
-CONFIG_IIO_SIMPLE_DUMMY=m
-# CONFIG_IIO_SIMPLE_DUMMY_EVENTS is not set
-# CONFIG_IIO_SIMPLE_DUMMY_BUFFER is not set
-
-#
-# Frequency Synthesizers DDS/PLL
-#
-
-#
-# Clock Generator/Distribution
-#
-CONFIG_AD9523=m
-
-#
-# Phase-Locked Loop (PLL) frequency synthesizers
-#
-CONFIG_ADF4350=m
-
-#
-# Digital gyroscope sensors
-#
-CONFIG_ADIS16080=m
-CONFIG_ADIS16130=m
-CONFIG_ADIS16136=m
-CONFIG_ADIS16260=m
-CONFIG_ADXRS450=m
-CONFIG_BMG160=m
-CONFIG_BMG160_I2C=m
-CONFIG_BMG160_SPI=m
-CONFIG_HID_SENSOR_GYRO_3D=m
-CONFIG_MPU3050=m
-CONFIG_MPU3050_I2C=m
-CONFIG_IIO_ST_GYRO_3AXIS=m
-CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
-CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
-CONFIG_ITG3200=m
-
-#
-# Health Sensors
-#
-
-#
-# Heart Rate Monitors
-#
-CONFIG_AFE4403=m
-CONFIG_AFE4404=m
-# CONFIG_MAX30100 is not set
-CONFIG_MAX30102=m
-
-#
-# Humidity sensors
-#
-CONFIG_AM2315=m
-CONFIG_DHT11=m
-# CONFIG_HDC100X is not set
-CONFIG_HID_SENSOR_HUMIDITY=m
-CONFIG_HTS221=m
-CONFIG_HTS221_I2C=m
-CONFIG_HTS221_SPI=m
-# CONFIG_HTU21 is not set
-CONFIG_SI7005=m
-CONFIG_SI7020=m
-
-#
-# Inertial measurement units
-#
-CONFIG_ADIS16400=m
-CONFIG_ADIS16480=m
-CONFIG_BMI160=m
-CONFIG_BMI160_I2C=m
-CONFIG_BMI160_SPI=m
-# CONFIG_KMX61 is not set
-CONFIG_INV_MPU6050_IIO=m
-CONFIG_INV_MPU6050_I2C=m
-CONFIG_INV_MPU6050_SPI=m
-CONFIG_IIO_ST_LSM6DSX=m
-CONFIG_IIO_ST_LSM6DSX_I2C=m
-CONFIG_IIO_ST_LSM6DSX_SPI=m
-CONFIG_IIO_ADIS_LIB=m
-CONFIG_IIO_ADIS_LIB_BUFFER=y
-
-#
-# Light sensors
-#
-CONFIG_ACPI_ALS=m
-CONFIG_ADJD_S311=m
-CONFIG_AL3320A=m
-CONFIG_APDS9300=m
-# CONFIG_APDS9960 is not set
-# CONFIG_BH1750 is not set
-CONFIG_BH1780=m
-CONFIG_CM32181=m
-# CONFIG_CM3232 is not set
-CONFIG_CM3323=m
-CONFIG_CM36651=m
-CONFIG_IIO_CROS_EC_LIGHT_PROX=m
-CONFIG_GP2AP020A00F=m
-CONFIG_SENSORS_ISL29018=m
-CONFIG_SENSORS_ISL29028=m
-CONFIG_ISL29125=m
-CONFIG_HID_SENSOR_ALS=m
-CONFIG_HID_SENSOR_PROX=m
-# CONFIG_JSA1212 is not set
-# CONFIG_RPR0521 is not set
-CONFIG_LTR501=m
-CONFIG_LV0104CS=m
-CONFIG_MAX44000=m
-# CONFIG_OPT3001 is not set
-# CONFIG_PA12203001 is not set
-# CONFIG_SI1133 is not set
-CONFIG_SI1145=m
-# CONFIG_STK3310 is not set
-CONFIG_ST_UVIS25=m
-CONFIG_ST_UVIS25_I2C=m
-CONFIG_ST_UVIS25_SPI=m
-CONFIG_TCS3414=m
-CONFIG_TCS3472=m
-CONFIG_SENSORS_TSL2563=m
-CONFIG_TSL2583=m
-# CONFIG_TSL2772 is not set
-CONFIG_TSL4531=m
-# CONFIG_US5182D is not set
-CONFIG_VCNL4000=m
-CONFIG_VEML6070=m
-CONFIG_VL6180=m
-CONFIG_ZOPT2201=m
-
-#
-# Magnetometer sensors
-#
-CONFIG_AK8975=m
-CONFIG_AK09911=m
-CONFIG_BMC150_MAGN=m
-CONFIG_BMC150_MAGN_I2C=m
-CONFIG_BMC150_MAGN_SPI=m
-CONFIG_MAG3110=m
-CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
-# CONFIG_MMC35240 is not set
-CONFIG_IIO_ST_MAGN_3AXIS=m
-CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
-CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
-CONFIG_SENSORS_HMC5843=m
-CONFIG_SENSORS_HMC5843_I2C=m
-CONFIG_SENSORS_HMC5843_SPI=m
-
-#
-# Multiplexers
-#
-
-#
-# Inclinometer sensors
-#
-CONFIG_HID_SENSOR_INCLINOMETER_3D=m
-CONFIG_HID_SENSOR_DEVICE_ROTATION=m
-
-#
-# Triggers - standalone
-#
-CONFIG_IIO_INTERRUPT_TRIGGER=m
-CONFIG_IIO_SYSFS_TRIGGER=m
-
-#
-# Digital potentiometers
-#
-CONFIG_AD5272=m
-CONFIG_DS1803=m
-CONFIG_MAX5481=m
-CONFIG_MAX5487=m
-CONFIG_MCP4018=m
-CONFIG_MCP4131=m
-# CONFIG_MCP4531 is not set
-CONFIG_TPL0102=m
-
-#
-# Digital potentiostats
-#
-CONFIG_LMP91000=m
-
-#
-# Pressure sensors
-#
-CONFIG_ABP060MG=m
-CONFIG_BMP280=m
-CONFIG_BMP280_I2C=m
-CONFIG_BMP280_SPI=m
-CONFIG_IIO_CROS_EC_BARO=m
-CONFIG_HID_SENSOR_PRESS=m
-CONFIG_HP03=m
-CONFIG_MPL115=m
-CONFIG_MPL115_I2C=m
-CONFIG_MPL115_SPI=m
-# CONFIG_MPL3115 is not set
-# CONFIG_MS5611 is not set
-# CONFIG_MS5637 is not set
-CONFIG_IIO_ST_PRESS=m
-CONFIG_IIO_ST_PRESS_I2C=m
-CONFIG_IIO_ST_PRESS_SPI=m
-CONFIG_T5403=m
-CONFIG_HP206C=m
-CONFIG_ZPA2326=m
-CONFIG_ZPA2326_I2C=m
-CONFIG_ZPA2326_SPI=m
-
-#
-# Lightning sensors
-#
-CONFIG_AS3935=m
-
-#
-# Proximity and distance sensors
-#
-# CONFIG_ISL29501 is not set
-# CONFIG_LIDAR_LITE_V2 is not set
-CONFIG_RFD77402=m
-CONFIG_SRF04=m
-# CONFIG_SX9500 is not set
-CONFIG_SRF08=m
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S1200=m
-
-#
-# Temperature sensors
-#
-CONFIG_MAXIM_THERMOCOUPLE=m
-CONFIG_HID_SENSOR_TEMP=m
-CONFIG_MLX90614=m
-CONFIG_MLX90632=m
-CONFIG_TMP006=m
-CONFIG_TMP007=m
-# CONFIG_TSYS01 is not set
-# CONFIG_TSYS02D is not set
-CONFIG_NTB=m
-# CONFIG_NTB_AMD is not set
-CONFIG_NTB_IDT=m
-# CONFIG_NTB_INTEL is not set
-CONFIG_NTB_SWITCHTEC=m
-# CONFIG_NTB_PINGPONG is not set
-# CONFIG_NTB_TOOL is not set
-# CONFIG_NTB_PERF is not set
-# CONFIG_NTB_TRANSPORT is not set
-CONFIG_VME_BUS=y
-
-#
-# VME Bridge Drivers
-#
-CONFIG_VME_CA91CX42=m
-CONFIG_VME_TSI148=m
-CONFIG_VME_FAKE=m
-
-#
-# VME Board Drivers
-#
-CONFIG_VMIVME_7805=m
-
-#
-# VME Device Drivers
-#
-CONFIG_VME_USER=m
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_PWM_CRC is not set
-CONFIG_PWM_CROS_EC=m
-CONFIG_PWM_LP3943=m
-CONFIG_PWM_LPSS=m
-CONFIG_PWM_LPSS_PCI=m
-CONFIG_PWM_LPSS_PLATFORM=m
-# CONFIG_PWM_PCA9685 is not set
-CONFIG_PWM_TWL=m
-CONFIG_PWM_TWL_LED=m
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_TI_SYSCON=m
-CONFIG_FMC=m
-CONFIG_FMC_FAKEDEV=m
-CONFIG_FMC_TRIVIAL=m
-CONFIG_FMC_WRITE_EEPROM=m
-CONFIG_FMC_CHARDEV=m
-CONFIG_GENERIC_PHY=y
-CONFIG_BCM_KONA_USB2_PHY=m
-CONFIG_PHY_CPCAP_USB=m
-CONFIG_PHY_SAMSUNG_USB2=m
-CONFIG_POWERCAP=y
-CONFIG_INTEL_RAPL=m
-# CONFIG_IDLE_INJECT is not set
-CONFIG_RAS_CEC=y
-CONFIG_THUNDERBOLT=m
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=m
-CONFIG_ANDROID_BINDER_DEVICES="binder"
-# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
-CONFIG_LIBNVDIMM=m
-CONFIG_BLK_DEV_PMEM=m
-CONFIG_ND_BLK=m
-CONFIG_ND_CLAIM=y
-CONFIG_ND_BTT=m
-CONFIG_BTT=y
-CONFIG_ND_PFN=m
-CONFIG_NVDIMM_PFN=y
-CONFIG_NVDIMM_DAX=y
-CONFIG_DAX_DRIVER=y
-CONFIG_DAX=y
-CONFIG_DEV_DAX=m
-CONFIG_DEV_DAX_PMEM=m
-# CONFIG_RAVE_SP_EEPROM is not set
-CONFIG_PM_OPP=y
-CONFIG_SIOX=m
-CONFIG_SIOX_BUS_GPIO=m
-CONFIG_SLIMBUS=m
-CONFIG_SLIM_QCOM_CTRL=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=m
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_EXT4_ENCRYPTION=y
-CONFIG_EXT4_FS_ENCRYPTION=y
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-CONFIG_REISERFS_PROC_INFO=y
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_SECURITY=y
-# CONFIG_JFS_DEBUG is not set
-CONFIG_JFS_STATISTICS=y
-CONFIG_XFS_FS=m
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_XFS_ONLINE_SCRUB=y
-# CONFIG_XFS_ONLINE_REPAIR is not set
-# CONFIG_XFS_WARN is not set
-# CONFIG_XFS_DEBUG is not set
-CONFIG_GFS2_FS=m
-CONFIG_GFS2_FS_LOCKING_DLM=y
-CONFIG_OCFS2_FS=m
-CONFIG_OCFS2_FS_O2CB=m
-CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
-CONFIG_OCFS2_FS_STATS=y
-# CONFIG_OCFS2_DEBUG_MASKLOG is not set
-# CONFIG_OCFS2_DEBUG_FS is not set
-CONFIG_BTRFS_FS=y
-CONFIG_BTRFS_FS_POSIX_ACL=y
-# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
-# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
-# CONFIG_BTRFS_DEBUG is not set
-# CONFIG_BTRFS_ASSERT is not set
-# CONFIG_BTRFS_FS_REF_VERIFY is not set
-CONFIG_NILFS2_FS=m
-CONFIG_F2FS_FS=y
-CONFIG_F2FS_STAT_FS=y
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_FS_POSIX_ACL=y
-CONFIG_F2FS_FS_SECURITY=y
-# CONFIG_F2FS_CHECK_FS is not set
-CONFIG_F2FS_FS_ENCRYPTION=y
-# CONFIG_F2FS_IO_TRACE is not set
-# CONFIG_F2FS_FAULT_INJECTION is not set
-CONFIG_FS_DAX=y
-CONFIG_FS_DAX_PMD=y
-CONFIG_EXPORTFS_BLOCK_OPS=y
-CONFIG_FS_ENCRYPTION=y
-CONFIG_FANOTIFY=y
-CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
-CONFIG_PRINT_QUOTA_WARNING=y
-CONFIG_QFMT_V1=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_AUTOFS_FS=y
-CONFIG_FUSE_FS=m
-CONFIG_CUSE=m
-CONFIG_OVERLAY_FS=y
-CONFIG_OVERLAY_FS_REDIRECT_DIR=y
-CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
-CONFIG_OVERLAY_FS_INDEX=y
-CONFIG_OVERLAY_FS_NFS_EXPORT=y
-CONFIG_OVERLAY_FS_XINO_AUTO=y
-# CONFIG_OVERLAY_FS_METACOPY is not set
-CONFIG_FSCACHE=m
-CONFIG_FSCACHE_STATS=y
-# CONFIG_FSCACHE_HISTOGRAM is not set
-# CONFIG_FSCACHE_DEBUG is not set
-# CONFIG_FSCACHE_OBJECT_LIST is not set
-CONFIG_CACHEFILES=m
-# CONFIG_CACHEFILES_DEBUG is not set
-# CONFIG_CACHEFILES_HISTOGRAM is not set
-CONFIG_ISO9660_FS=m
-CONFIG_UDF_FS=m
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_UTF8=y
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-# CONFIG_NTFS_RW is not set
-# CONFIG_EXFAT_DEBUG_MSG is not set
-CONFIG_EXFAT_DEFAULT_CODEPAGE=437
-CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
-# CONFIG_EXFAT_DELAYED_SYNC is not set
-CONFIG_EXFAT_DISCARD=y
-CONFIG_EXFAT_DONT_MOUNT_VFAT=y
-CONFIG_EXFAT_FS=m
-# CONFIG_EXFAT_KERNEL_DEBUG is not set
-CONFIG_PROC_CHILDREN=y
-# CONFIG_PROC_KCORE is not set
-CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_EFIVAR_FS=y
-CONFIG_ORANGEFS_FS=m
-CONFIG_ADFS_FS=m
-# CONFIG_ADFS_FS_RW is not set
-CONFIG_AFFS_FS=m
-CONFIG_ECRYPT_FS=m
-# CONFIG_ECRYPT_FS_MESSAGING is not set
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-# CONFIG_BEFS_DEBUG is not set
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_RTIME=y
-CONFIG_UBIFS_FS=m
-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-# CONFIG_UBIFS_ATIME_SUPPORT is not set
-CONFIG_UBIFS_FS_XATTR=y
-CONFIG_UBIFS_FS_ENCRYPTION=y
-CONFIG_UBIFS_FS_SECURITY=y
-CONFIG_CRAMFS=y
-CONFIG_CRAMFS_BLOCKDEV=y
-CONFIG_SQUASHFS=m
-# CONFIG_SQUASHFS_FILE_CACHE is not set
-CONFIG_SQUASHFS_FILE_DIRECT=y
-# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
-CONFIG_SQUASHFS_DECOMP_MULTI=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_XATTR=y
-CONFIG_SQUASHFS_ZLIB=y
-CONFIG_SQUASHFS_LZ4=y
-CONFIG_SQUASHFS_LZO=y
-CONFIG_SQUASHFS_XZ=y
-CONFIG_SQUASHFS_ZSTD=y
-CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
-# CONFIG_SQUASHFS_EMBEDDED is not set
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_OMFS_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_QNX6FS_FS=m
-# CONFIG_QNX6FS_DEBUG is not set
-CONFIG_ROMFS_FS=m
-# CONFIG_ROMFS_BACKED_BY_BLOCK is not set
-# CONFIG_ROMFS_BACKED_BY_MTD is not set
-CONFIG_ROMFS_BACKED_BY_BOTH=y
-CONFIG_ROMFS_ON_BLOCK=y
-CONFIG_ROMFS_ON_MTD=y
-CONFIG_PSTORE=m
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-# CONFIG_PSTORE_LZO_COMPRESS is not set
-# CONFIG_PSTORE_LZ4_COMPRESS is not set
-CONFIG_PSTORE_LZ4HC_COMPRESS=m
-CONFIG_PSTORE_842_COMPRESS=y
-# CONFIG_PSTORE_ZSTD_COMPRESS is not set
-CONFIG_PSTORE_COMPRESS=y
-CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
-# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
-CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
-# CONFIG_PSTORE_CONSOLE is not set
-# CONFIG_PSTORE_PMSG is not set
-# CONFIG_PSTORE_FTRACE is not set
-CONFIG_PSTORE_RAM=y
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-# CONFIG_UFS_FS_WRITE is not set
-# CONFIG_UFS_DEBUG is not set
-CONFIG_EXOFS_FS=m
-# CONFIG_EXOFS_DEBUG is not set
-CONFIG_VBOXSF_FS=m
-CONFIG_ORE=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V2=m
-CONFIG_NFS_V3=m
-CONFIG_NFS_V4=m
-CONFIG_NFS_FSCACHE=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V2_ACL=y
-CONFIG_NFSD_V3=y
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_PNFS=y
-CONFIG_NFSD_BLOCKLAYOUT=y
-CONFIG_NFSD_SCSILAYOUT=y
-CONFIG_NFSD_FLEXFILELAYOUT=y
-# CONFIG_NFSD_V4_SECURITY_LABEL is not set
-# CONFIG_NFSD_FAULT_INJECTION is not set
-CONFIG_GRACE_PERIOD=m
-CONFIG_LOCKD=m
-CONFIG_NFS_ACL_SUPPORT=m
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_RPCSEC_GSS_KRB5=m
-CONFIG_SUNRPC_XPRT_RDMA=m
-CONFIG_CEPH_FS=m
-CONFIG_CEPH_FSCACHE=y
-CONFIG_CEPH_FS_POSIX_ACL=y
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS2=y
-CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
-CONFIG_CIFS_WEAK_PW_HASH=y
-CONFIG_CIFS_UPCALL=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-CONFIG_CIFS_ACL=y
-# CONFIG_CIFS_DEBUG is not set
-CONFIG_CIFS_DFS_UPCALL=y
-CONFIG_CIFS_SMB_DIRECT=y
-CONFIG_CIFS_FSCACHE=y
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-# CONFIG_AFS_DEBUG is not set
-CONFIG_AFS_FSCACHE=y
-CONFIG_9P_FS=m
-CONFIG_9P_FSCACHE=y
-CONFIG_9P_FS_POSIX_ACL=y
-# CONFIG_9P_FS_SECURITY is not set
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_MAC_ROMAN=m
-CONFIG_NLS_MAC_CELTIC=m
-CONFIG_NLS_MAC_CENTEURO=m
-CONFIG_NLS_MAC_CROATIAN=m
-CONFIG_NLS_MAC_CYRILLIC=m
-CONFIG_NLS_MAC_GAELIC=m
-CONFIG_NLS_MAC_GREEK=m
-CONFIG_NLS_MAC_ICELAND=m
-CONFIG_NLS_MAC_INUIT=m
-CONFIG_NLS_MAC_ROMANIAN=m
-CONFIG_NLS_MAC_TURKISH=m
-CONFIG_NLS_UTF8=m
-CONFIG_DLM=m
-# CONFIG_DLM_DEBUG is not set
-CONFIG_TRUSTED_KEYS=m
-CONFIG_ENCRYPTED_KEYS=m
-CONFIG_KEY_DH_OPERATIONS=y
-CONFIG_SECURITYFS=y
-CONFIG_SECURITY_INFINIBAND=y
-CONFIG_SECURITY_NETWORK_XFRM=y
-CONFIG_SECURITY_PATH=y
-CONFIG_INTEL_TXT=y
-CONFIG_HARDENED_USERCOPY=y
-# CONFIG_HARDENED_USERCOPY_FALLBACK is not set
-# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
-CONFIG_FORTIFY_SOURCE=y
-# CONFIG_SECURITY_SELINUX is not set
-CONFIG_SECURITY_TOMOYO=y
-CONFIG_SECURITY_TOMOYO_MAX_ACCEPT_ENTRY=2048
-CONFIG_SECURITY_TOMOYO_MAX_AUDIT_LOG=1024
-# CONFIG_SECURITY_TOMOYO_OMIT_USERSPACE_LOADER is not set
-CONFIG_SECURITY_TOMOYO_POLICY_LOADER="/sbin/tomoyo-init"
-CONFIG_SECURITY_TOMOYO_ACTIVATION_TRIGGER="/sbin/init"
-# CONFIG_SECURITY_LOADPIN is not set
-# CONFIG_SECURITY_LOADPIN_ENABLED is not set
-CONFIG_DEFAULT_SECURITY_TOMOYO=y
-CONFIG_DEFAULT_SECURITY="tomoyo"
-CONFIG_XOR_BLOCKS=y
-CONFIG_ASYNC_CORE=m
-CONFIG_ASYNC_MEMCPY=m
-CONFIG_ASYNC_XOR=m
-CONFIG_ASYNC_PQ=m
-CONFIG_ASYNC_RAID6_RECOV=m
-CONFIG_CRYPTO_CHACHA20POLY1305=m
-CONFIG_CRYPTO_CHACHA20=m
-CONFIG_CRYPTO_MORUS1280_GLUE=m
-CONFIG_CRYPTO_MORUS1280_SSE2=m
-CONFIG_CRYPTO_MORUS640_GLUE=m
-CONFIG_CRYPTO_MORUS640_SSE2=m
-CONFIG_CRYPTO_OFB=m
-CONFIG_CRYPTO_KPP=y
-CONFIG_CRYPTO_DH=y
-CONFIG_CRYPTO_ECDH=m
-CONFIG_CRYPTO_USER=m
-CONFIG_CRYPTO_PCRYPT=m
-CONFIG_CRYPTO_POLY1305=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_MCRYPTD=m
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_SIMD=m
-CONFIG_CRYPTO_ENGINE=m
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_ECHAINIV=m
-CONFIG_CRYPTO_CFB=m
-CONFIG_CRYPTO_CTS=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_CMAC=m
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-CONFIG_CRYPTO_CRC32C_INTEL=m
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32_PCLMUL=m
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_CRCT10DIF_PCLMUL=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_RMD128=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_RMD256=m
-CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA1_SSSE3=m
-CONFIG_CRYPTO_SHA256_SSSE3=m
-CONFIG_CRYPTO_SHA512_SSSE3=m
-CONFIG_CRYPTO_SHA1_MB=m
-CONFIG_CRYPTO_SHA256_MB=m
-CONFIG_CRYPTO_SHA512_MB=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_SHA3=m
-CONFIG_CRYPTO_SM3=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m
-CONFIG_CRYPTO_AES_TI=m
-CONFIG_CRYPTO_AES_NI_INTEL=m
-CONFIG_CRYPTO_ANUBIS=m
-# CONFIG_CRYPTO_ARC4 is not set
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_BLOWFISH_COMMON=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST_COMMON=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SALSA20=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_SM4=m
-CONFIG_CRYPTO_SPECK=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_842=y
-CONFIG_CRYPTO_LZ4=m
-CONFIG_CRYPTO_LZ4HC=m
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CRYPTO_ANSI_CPRNG=m
-CONFIG_CRYPTO_USER_API=m
-CONFIG_CRYPTO_USER_API_HASH=y
-CONFIG_CRYPTO_USER_API_SKCIPHER=m
-CONFIG_CRYPTO_USER_API_RNG=m
-CONFIG_CRYPTO_DEV_PADLOCK=m
-CONFIG_CRYPTO_DEV_PADLOCK_AES=m
-CONFIG_CRYPTO_DEV_PADLOCK_SHA=m
-CONFIG_CRYPTO_DEV_CCP=y
-CONFIG_CRYPTO_DEV_CCP_DD=m
-CONFIG_CRYPTO_DEV_SP_CCP=y
-CONFIG_CRYPTO_DEV_CCP_CRYPTO=m
-CONFIG_CRYPTO_DEV_SP_PSP=y
-CONFIG_CRYPTO_DEV_QAT=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
-CONFIG_CRYPTO_DEV_NITROX=m
-CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m
-CONFIG_CRYPTO_DEV_CHELSIO=m
-CONFIG_CHELSIO_IPSEC_INLINE=y
-CONFIG_CRYPTO_DEV_CHELSIO_TLS=m
-CONFIG_CRYPTO_DEV_VIRTIO=m
-CONFIG_PKCS7_TEST_KEY=m
-CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
-CONFIG_X509_CERTIFICATE_PARSER=y
-CONFIG_RAID6_PQ=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC64=m
-CONFIG_CRC4=m
-CONFIG_CRC7=m
-CONFIG_LIBCRC32C=y
-CONFIG_CRC8=m
-CONFIG_842_COMPRESS=y
-CONFIG_842_DECOMPRESS=y
-CONFIG_LZ4_COMPRESS=m
-CONFIG_LZ4HC_COMPRESS=m
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_RD_ZSTD=y
-CONFIG_DECOMPRESS_ZSTD=y
-CONFIG_INITRAMFS_COMPRESSION_ZSTD=y
-# CONFIG_XZ_DEC_POWERPC is not set
-# CONFIG_XZ_DEC_IA64 is not set
-# CONFIG_XZ_DEC_ARM is not set
-# CONFIG_XZ_DEC_ARMTHUMB is not set
-# CONFIG_XZ_DEC_SPARC is not set
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_DEC16=y
-CONFIG_BCH=m
-CONFIG_BCH_CONST_PARAMS=y
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_BTREE=y
-CONFIG_RADIX_TREE_MULTIORDER=y
-CONFIG_DMA_VIRT_OPS=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_LRU_CACHE=m
-CONFIG_CORDIC=m
-CONFIG_DDR=y
-CONFIG_IRQ_POLL=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3
-CONFIG_BOOT_PRINTK_DELAY=y
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_UNUSED_SYMBOLS=y
-# CONFIG_MAGIC_SYSRQ_SERIAL is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-CONFIG_MEMORY_NOTIFIER_ERROR_INJECT=m
-# CONFIG_DEBUG_STACKOVERFLOW is not set
-CONFIG_LOCKUP_DETECTOR=y
-CONFIG_SOFTLOCKUP_DETECTOR=y
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
-CONFIG_HARDLOCKUP_DETECTOR_PERF=y
-CONFIG_HARDLOCKUP_DETECTOR=y
-CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y
-CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=1
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-# CONFIG_SCHEDSTATS is not set
-CONFIG_WW_MUTEX_SELFTEST=m
-CONFIG_TRACE_IRQFLAGS=y
-CONFIG_TORTURE_TEST=m
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_RCU_PERF_TEST=m
-CONFIG_RCU_CPU_STALL_TIMEOUT=60
-# CONFIG_RCU_TRACE is not set
-CONFIG_NOTIFIER_ERROR_INJECTION=m
-CONFIG_PM_NOTIFIER_ERROR_INJECT=m
-# CONFIG_NETDEV_NOTIFIER_ERROR_INJECT is not set
-CONFIG_TRACER_MAX_TRACE=y
-CONFIG_RING_BUFFER_ALLOW_SWAP=y
-CONFIG_PREEMPTIRQ_TRACEPOINTS=y
-CONFIG_FUNCTION_TRACER=y
-# CONFIG_FUNCTION_GRAPH_TRACER is not set
-CONFIG_PREEMPTIRQ_EVENTS=y
-CONFIG_SCHED_TRACER=y
-CONFIG_HWLAT_TRACER=y
-CONFIG_FTRACE_SYSCALLS=y
-CONFIG_TRACER_SNAPSHOT=y
-# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set
-CONFIG_STACK_TRACER=y
-# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set
-CONFIG_BPF_EVENTS=y
-CONFIG_DYNAMIC_FTRACE=y
-CONFIG_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_FUNCTION_PROFILER=y
-# CONFIG_BPF_KPROBE_OVERRIDE is not set
-CONFIG_FTRACE_MCOUNT_RECORD=y
-CONFIG_MMIOTRACE=y
-# CONFIG_MMIOTRACE_TEST is not set
-CONFIG_RING_BUFFER_BENCHMARK=m
-CONFIG_TRACING_EVENTS_GPIO=y
-# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_MEMTEST=y
-CONFIG_IO_STRICT_DEVMEM=y
-# CONFIG_EARLY_PRINTK is not set
-# CONFIG_EARLY_PRINTK_DBGP is not set
-# CONFIG_EARLY_PRINTK_USB_XDBC is not set
-# CONFIG_X86_VERBOSE_BOOTUP is not set
-# CONFIG_IOMMU_DEBUG is not set
-# CONFIG_DEBUG_BOOT_PARAMS is not set
-# CONFIG_UNWINDER_GUESS is not set
diff --git a/cpu-optimizations.patch b/cpu-optimizations.patch
new file mode 100644
index 0000000..80a1fc9
--- /dev/null
+++ b/cpu-optimizations.patch
@@ -0,0 +1,681 @@
+diff -up linux-6.8-rc7/arch/x86/Kconfig.cpu.1~ linux-6.8-rc7/arch/x86/Kconfig.cpu
+--- linux-6.8-rc7/arch/x86/Kconfig.cpu.1~	2024-03-03 22:02:52.000000000 +0100
++++ linux-6.8-rc7/arch/x86/Kconfig.cpu	2024-03-04 17:56:11.913274962 +0100
+@@ -157,7 +157,7 @@ config MPENTIUM4
+ 
+ 
+ config MK6
+-	bool "K6/K6-II/K6-III"
++	bool "AMD K6/K6-II/K6-III"
+ 	depends on X86_32
+ 	help
+ 	  Select this for an AMD K6-family processor.  Enables use of
+@@ -165,7 +165,7 @@ config MK6
+ 	  flags to GCC.
+ 
+ config MK7
+-	bool "Athlon/Duron/K7"
++	bool "AMD Athlon/Duron/K7"
+ 	depends on X86_32
+ 	help
+ 	  Select this for an AMD Athlon K7-family processor.  Enables use of
+@@ -173,12 +173,106 @@ config MK7
+ 	  flags to GCC.
+ 
+ config MK8
+-	bool "Opteron/Athlon64/Hammer/K8"
++	bool "AMD Opteron/Athlon64/Hammer/K8"
+ 	help
+ 	  Select this for an AMD Opteron or Athlon64 Hammer-family processor.
+ 	  Enables use of some extended instructions, and passes appropriate
+ 	  optimization flags to GCC.
+ 
++config MK8SSE3
++	bool "AMD Opteron/Athlon64/Hammer/K8 with SSE3"
++	help
++	  Select this for improved AMD Opteron or Athlon64 Hammer-family processors.
++	  Enables use of some extended instructions, and passes appropriate
++	  optimization flags to GCC.
++
++config MK10
++	bool "AMD 61xx/7x50/PhenomX3/X4/II/K10"
++	help
++	  Select this for an AMD 61xx Eight-Core Magny-Cours, Athlon X2 7x50,
++	  Phenom X3/X4/II, Athlon II X2/X3/X4, or Turion II-family processor.
++	  Enables use of some extended instructions, and passes appropriate
++	  optimization flags to GCC.
++
++config MBARCELONA
++	bool "AMD Barcelona"
++	help
++	  Select this for AMD Family 10h Barcelona processors.
++
++	  Enables -march=barcelona
++
++config MBOBCAT
++	bool "AMD Bobcat"
++	help
++	  Select this for AMD Family 14h Bobcat processors.
++
++	  Enables -march=btver1
++
++config MJAGUAR
++	bool "AMD Jaguar"
++	help
++	  Select this for AMD Family 16h Jaguar processors.
++
++	  Enables -march=btver2
++
++config MBULLDOZER
++	bool "AMD Bulldozer"
++	help
++	  Select this for AMD Family 15h Bulldozer processors.
++
++	  Enables -march=bdver1
++
++config MPILEDRIVER
++	bool "AMD Piledriver"
++	help
++	  Select this for AMD Family 15h Piledriver processors.
++
++	  Enables -march=bdver2
++
++config MSTEAMROLLER
++	bool "AMD Steamroller"
++	help
++	  Select this for AMD Family 15h Steamroller processors.
++
++	  Enables -march=bdver3
++
++config MEXCAVATOR
++	bool "AMD Excavator"
++	help
++	  Select this for AMD Family 15h Excavator processors.
++
++	  Enables -march=bdver4
++
++config MZEN
++	bool "AMD Zen"
++	help
++	  Select this for AMD Family 17h Zen processors.
++
++	  Enables -march=znver1
++
++config MZEN2
++	bool "AMD Zen 2"
++	help
++	  Select this for AMD Family 17h Zen 2 processors.
++
++	  Enables -march=znver2
++
++config MZEN3
++	bool "AMD Zen 3"
++	depends on (CC_IS_GCC && GCC_VERSION >= 100300) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
++	help
++	  Select this for AMD Family 19h Zen 3 processors.
++
++	  Enables -march=znver3
++
++config MZEN4
++	bool "AMD Zen 4"
++	depends on (CC_IS_GCC && GCC_VERSION >= 130000) || (CC_IS_CLANG && CLANG_VERSION >= 160000)
++	help
++	  Select this for AMD Family 19h Zen 4 processors.
++
++	  Enables -march=znver4
++
+ config MCRUSOE
+ 	bool "Crusoe"
+ 	depends on X86_32
+@@ -270,7 +364,7 @@ config MPSC
+ 	  in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
+ 
+ config MCORE2
+-	bool "Core 2/newer Xeon"
++	bool "Intel Core 2"
+ 	help
+ 
+ 	  Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
+@@ -278,6 +372,8 @@ config MCORE2
+ 	  family in /proc/cpuinfo. Newer ones have 6 and older ones 15
+ 	  (not a typo)
+ 
++	  Enables -march=core2
++
+ config MATOM
+ 	bool "Intel Atom"
+ 	help
+@@ -287,6 +383,212 @@ config MATOM
+ 	  accordingly optimized code. Use a recent GCC with specific Atom
+ 	  support in order to fully benefit from selecting this option.
+ 
++config MNEHALEM
++	bool "Intel Nehalem"
++	select X86_P6_NOP
++	help
++
++	  Select this for 1st Gen Core processors in the Nehalem family.
++
++	  Enables -march=nehalem
++
++config MWESTMERE
++	bool "Intel Westmere"
++	select X86_P6_NOP
++	help
++
++	  Select this for the Intel Westmere formerly Nehalem-C family.
++
++	  Enables -march=westmere
++
++config MSILVERMONT
++	bool "Intel Silvermont"
++	select X86_P6_NOP
++	help
++
++	  Select this for the Intel Silvermont platform.
++
++	  Enables -march=silvermont
++
++config MGOLDMONT
++	bool "Intel Goldmont"
++	select X86_P6_NOP
++	help
++
++	  Select this for the Intel Goldmont platform including Apollo Lake and Denverton.
++
++	  Enables -march=goldmont
++
++config MGOLDMONTPLUS
++	bool "Intel Goldmont Plus"
++	select X86_P6_NOP
++	help
++
++	  Select this for the Intel Goldmont Plus platform including Gemini Lake.
++
++	  Enables -march=goldmont-plus
++
++config MSANDYBRIDGE
++	bool "Intel Sandy Bridge"
++	select X86_P6_NOP
++	help
++
++	  Select this for 2nd Gen Core processors in the Sandy Bridge family.
++
++	  Enables -march=sandybridge
++
++config MIVYBRIDGE
++	bool "Intel Ivy Bridge"
++	select X86_P6_NOP
++	help
++
++	  Select this for 3rd Gen Core processors in the Ivy Bridge family.
++
++	  Enables -march=ivybridge
++
++config MHASWELL
++	bool "Intel Haswell"
++	select X86_P6_NOP
++	help
++
++	  Select this for 4th Gen Core processors in the Haswell family.
++
++	  Enables -march=haswell
++
++config MBROADWELL
++	bool "Intel Broadwell"
++	select X86_P6_NOP
++	help
++
++	  Select this for 5th Gen Core processors in the Broadwell family.
++
++	  Enables -march=broadwell
++
++config MSKYLAKE
++	bool "Intel Skylake"
++	select X86_P6_NOP
++	help
++
++	  Select this for 6th Gen Core processors in the Skylake family.
++
++	  Enables -march=skylake
++
++config MSKYLAKEX
++	bool "Intel Skylake X"
++	select X86_P6_NOP
++	help
++
++	  Select this for 6th Gen Core processors in the Skylake X family.
++
++	  Enables -march=skylake-avx512
++
++config MCANNONLAKE
++	bool "Intel Cannon Lake"
++	select X86_P6_NOP
++	help
++
++	  Select this for 8th Gen Core processors
++
++	  Enables -march=cannonlake
++
++config MICELAKE
++	bool "Intel Ice Lake"
++	select X86_P6_NOP
++	help
++
++	  Select this for 10th Gen Core processors in the Ice Lake family.
++
++	  Enables -march=icelake-client
++
++config MCASCADELAKE
++	bool "Intel Cascade Lake"
++	select X86_P6_NOP
++	help
++
++	  Select this for Xeon processors in the Cascade Lake family.
++
++	  Enables -march=cascadelake
++
++config MCOOPERLAKE
++	bool "Intel Cooper Lake"
++	depends on (CC_IS_GCC && GCC_VERSION > 100100) || (CC_IS_CLANG && CLANG_VERSION >= 100000)
++	select X86_P6_NOP
++	help
++
++	  Select this for Xeon processors in the Cooper Lake family.
++
++	  Enables -march=cooperlake
++
++config MTIGERLAKE
++	bool "Intel Tiger Lake"
++	depends on  (CC_IS_GCC && GCC_VERSION > 100100) || (CC_IS_CLANG && CLANG_VERSION >= 100000)
++	select X86_P6_NOP
++	help
++
++	  Select this for third-generation 10 nm process processors in the Tiger Lake family.
++
++	  Enables -march=tigerlake
++
++config MSAPPHIRERAPIDS
++	bool "Intel Sapphire Rapids"
++	depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
++	select X86_P6_NOP
++	help
++
++	  Select this for fourth-generation 10 nm process processors in the Sapphire Rapids family.
++
++	  Enables -march=sapphirerapids
++
++config MROCKETLAKE
++	bool "Intel Rocket Lake"
++	depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
++	select X86_P6_NOP
++	help
++
++	  Select this for eleventh-generation processors in the Rocket Lake family.
++
++	  Enables -march=rocketlake
++
++config MALDERLAKE
++	bool "Intel Alder Lake"
++	depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
++	select X86_P6_NOP
++	help
++
++	  Select this for twelfth-generation processors in the Alder Lake family.
++
++	  Enables -march=alderlake
++
++config MRAPTORLAKE
++	bool "Intel Raptor Lake"
++	depends on (CC_IS_GCC && GCC_VERSION >= 130000) || (CC_IS_CLANG && CLANG_VERSION >= 150500)
++	select X86_P6_NOP
++	help
++
++	  Select this for thirteenth-generation processors in the Raptor Lake family.
++
++	  Enables -march=raptorlake
++
++config MMETEORLAKE
++	bool "Intel Meteor Lake"
++	depends on (CC_IS_GCC && GCC_VERSION >= 130000) || (CC_IS_CLANG && CLANG_VERSION >= 150500)
++	select X86_P6_NOP
++	help
++
++	  Select this for fourteenth-generation processors in the Meteor Lake family.
++
++	  Enables -march=meteorlake
++
++config MEMERALDRAPIDS
++	bool "Intel Emerald Rapids"
++	depends on (CC_IS_GCC && GCC_VERSION > 130000) || (CC_IS_CLANG && CLANG_VERSION >= 150500)
++	select X86_P6_NOP
++	help
++
++	  Select this for fifth-generation 10 nm process processors in the Emerald Rapids family.
++
++	  Enables -march=emeraldrapids
++
+ config GENERIC_CPU
+ 	bool "Generic-x86-64"
+ 	depends on X86_64
+@@ -294,6 +596,50 @@ config GENERIC_CPU
+ 	  Generic x86-64 CPU.
+ 	  Run equally well on all x86-64 CPUs.
+ 
++config GENERIC_CPU2
++	bool "Generic-x86-64-v2"
++	depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
++	depends on X86_64
++	help
++	  Generic x86-64 CPU.
++	  Run equally well on all x86-64 CPUs with min support of x86-64-v2.
++
++config GENERIC_CPU3
++	bool "Generic-x86-64-v3"
++	depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
++	depends on X86_64
++	help
++	  Generic x86-64-v3 CPU with v3 instructions.
++	  Run equally well on all x86-64 CPUs with min support of x86-64-v3.
++
++config GENERIC_CPU4
++	bool "Generic-x86-64-v4"
++	depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000)
++	depends on X86_64
++	help
++	  Generic x86-64 CPU with v4 instructions.
++	  Run equally well on all x86-64 CPUs with min support of x86-64-v4.
++
++config MNATIVE_INTEL
++	bool "Intel-Native optimizations autodetected by the compiler"
++	help
++
++	  Clang 3.8, GCC 4.2 and above support -march=native, which automatically detects
++	  the optimum settings to use based on your processor. Do NOT use this
++	  for AMD CPUs.  Intel Only!
++
++	  Enables -march=native
++
++config MNATIVE_AMD
++	bool "AMD-Native optimizations autodetected by the compiler"
++	help
++
++	  Clang 3.8, GCC 4.2 and above support -march=native, which automatically detects
++	  the optimum settings to use based on your processor. Do NOT use this
++	  for Intel CPUs.  AMD Only!
++
++	  Enables -march=native
++
+ endchoice
+ 
+ config X86_GENERIC
+@@ -318,9 +664,17 @@ config X86_INTERNODE_CACHE_SHIFT
+ config X86_L1_CACHE_SHIFT
+ 	int
+ 	default "7" if MPENTIUM4 || MPSC
+-	default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
++	default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || MK8SSE3 || MK10 \
++	|| MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER \
++	|| MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MZEN4 || MNEHALEM || MWESTMERE || MSILVERMONT \
++	|| MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL \
++	|| MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE \
++	|| MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MMETEORLAKE \
++	|| MEMERALDRAPIDS || MNATIVE_INTEL || MNATIVE_AMD || X86_GENERIC || GENERIC_CPU || GENERIC_CPU2 \
++	|| GENERIC_CPU3 || GENERIC_CPU4
+ 	default "4" if MELAN || M486SX || M486 || MGEODEGX1
+-	default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
++	default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII \
++	|| MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
+ 
+ config X86_F00F_BUG
+ 	def_bool y
+@@ -332,15 +686,27 @@ config X86_INVD_BUG
+ 
+ config X86_ALIGNMENT_16
+ 	def_bool y
+-	depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MELAN || MK6 || M586MMX || M586TSC || M586 || M486SX || M486 || MVIAC3_2 || MGEODEGX1
++	depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MELAN || MK6 || M586MMX || M586TSC \
++	|| M586 || M486SX || M486 || MVIAC3_2 || MGEODEGX1
+ 
+ config X86_INTEL_USERCOPY
+ 	def_bool y
+-	depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
++	depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC \
++	|| MK8 || MK7 || MEFFICEON || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT \
++	|| MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX \
++	|| MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS \
++	|| MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS || MNATIVE_INTEL
+ 
+ config X86_USE_PPRO_CHECKSUM
+ 	def_bool y
+-	depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM
++	depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM \
++	|| MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX \
++	|| MCORE2 || MATOM || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER \
++	|| MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MZEN4 || MNEHALEM \
++	|| MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE \
++	|| MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE \
++	|| MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE \
++	|| MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS || MNATIVE_INTEL || MNATIVE_AMD
+ 
+ #
+ # P6_NOPs are a relatively minor optimization that require a family >=
+@@ -356,11 +722,22 @@ config X86_USE_PPRO_CHECKSUM
+ config X86_P6_NOP
+ 	def_bool y
+ 	depends on X86_64
+-	depends on (MCORE2 || MPENTIUM4 || MPSC)
++	depends on (MCORE2 || MPENTIUM4 || MPSC || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT \
++	|| MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE \
++	|| MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE \
++	|| MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS \
++	|| MNATIVE_INTEL)
+ 
+ config X86_TSC
+ 	def_bool y
+-	depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64
++	depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM \
++	|| MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 \
++	|| MGEODE_LX || MCORE2 || MATOM || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER \
++	|| MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MZEN4 || MNEHALEM \
++	|| MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL \
++	|| MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE \
++	|| MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS \
++	|| MNATIVE_INTEL || MNATIVE_AMD) || X86_64
+ 
+ config X86_HAVE_PAE
+ 	def_bool y
+@@ -368,24 +745,44 @@ config X86_HAVE_PAE
+ 
+ config X86_CMPXCHG64
+ 	def_bool y
+-	depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7
++	depends on X86_HAVE_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 \
++	|| M586TSC || M586MMX || MATOM || MGEODE_LX || MGEODEGX1 || MK6 || MK7 || MK8 || MK8SSE3 || MK10 \
++	|| MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN \
++	|| MZEN2 || MZEN3 || MZEN4 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS \
++	|| MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE \
++	|| MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE \
++	|| MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS || MNATIVE_INTEL || MNATIVE_AMD
+ 
+ # this should be set for all -march=.. options where the compiler
+ # generates cmov.
+ config X86_CMOV
+ 	def_bool y
+-	depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX)
++	depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 \
++	|| MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX || MK8SSE3 || MK10 \
++	|| MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR \
++	|| MZEN || MZEN2 || MZEN3 || MZEN4 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT \
++	|| MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX \
++	|| MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS \
++	|| MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS || MNATIVE_INTEL || MNATIVE_AMD)
+ 
+ config X86_MINIMUM_CPU_FAMILY
+ 	int
+ 	default "64" if X86_64
+-	default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCORE2 || MK7 || MK8)
++	default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 \
++	|| MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCORE2 || MK7 || MK8 ||  MK8SSE3 \
++	|| MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER \
++	|| MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MZEN4 || MNEHALEM || MWESTMERE || MSILVERMONT \
++	|| MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL \
++	|| MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MCASCADELAKE || MCOOPERLAKE \
++	|| MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MRAPTORLAKE \
++	|| MNATIVE_INTEL || MNATIVE_AMD)
+ 	default "5" if X86_32 && X86_CMPXCHG64
+ 	default "4"
+ 
+ config X86_DEBUGCTLMSR
+ 	def_bool y
+-	depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486SX || M486) && !UML
++	depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 \
++	|| M486SX || M486) && !UML
+ 
+ config IA32_FEAT_CTL
+ 	def_bool y
+diff -up linux-6.8-rc7/arch/x86/Makefile.1~ linux-6.8-rc7/arch/x86/Makefile
+--- linux-6.8-rc7/arch/x86/Makefile.1~	2024-03-03 22:02:52.000000000 +0100
++++ linux-6.8-rc7/arch/x86/Makefile	2024-03-04 17:50:40.497606626 +0100
+@@ -152,8 +152,48 @@ else
+         # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu)
+         cflags-$(CONFIG_MK8)		+= -march=k8
+         cflags-$(CONFIG_MPSC)		+= -march=nocona
+-        cflags-$(CONFIG_MCORE2)		+= -march=core2
+-        cflags-$(CONFIG_MATOM)		+= -march=atom
++        cflags-$(CONFIG_MK8SSE3)	+= -march=k8-sse3
++        cflags-$(CONFIG_MK10) 		+= -march=amdfam10
++        cflags-$(CONFIG_MBARCELONA) 	+= -march=barcelona
++        cflags-$(CONFIG_MBOBCAT) 	+= -march=btver1
++        cflags-$(CONFIG_MJAGUAR) 	+= -march=btver2
++        cflags-$(CONFIG_MBULLDOZER) 	+= -march=bdver1
++        cflags-$(CONFIG_MPILEDRIVER)	+= -march=bdver2 -mno-tbm
++        cflags-$(CONFIG_MSTEAMROLLER) 	+= -march=bdver3 -mno-tbm
++        cflags-$(CONFIG_MEXCAVATOR) 	+= -march=bdver4 -mno-tbm
++        cflags-$(CONFIG_MZEN) 		+= -march=znver1
++        cflags-$(CONFIG_MZEN2) 	+= -march=znver2
++        cflags-$(CONFIG_MZEN3) 	+= -march=znver3
++        cflags-$(CONFIG_MZEN4) 	+= -march=znver4
++        cflags-$(CONFIG_MNATIVE_INTEL) += -march=native
++        cflags-$(CONFIG_MNATIVE_AMD) 	+= -march=native
++        cflags-$(CONFIG_MATOM) 	+= -march=bonnell
++        cflags-$(CONFIG_MCORE2) 	+= -march=core2
++        cflags-$(CONFIG_MNEHALEM) 	+= -march=nehalem
++        cflags-$(CONFIG_MWESTMERE) 	+= -march=westmere
++        cflags-$(CONFIG_MSILVERMONT) 	+= -march=silvermont
++        cflags-$(CONFIG_MGOLDMONT) 	+= -march=goldmont
++        cflags-$(CONFIG_MGOLDMONTPLUS) += -march=goldmont-plus
++        cflags-$(CONFIG_MSANDYBRIDGE) 	+= -march=sandybridge
++        cflags-$(CONFIG_MIVYBRIDGE) 	+= -march=ivybridge
++        cflags-$(CONFIG_MHASWELL) 	+= -march=haswell
++        cflags-$(CONFIG_MBROADWELL) 	+= -march=broadwell
++        cflags-$(CONFIG_MSKYLAKE) 	+= -march=skylake
++        cflags-$(CONFIG_MSKYLAKEX) 	+= -march=skylake-avx512
++        cflags-$(CONFIG_MCANNONLAKE) 	+= -march=cannonlake
++        cflags-$(CONFIG_MICELAKE) 	+= -march=icelake-client
++        cflags-$(CONFIG_MCASCADELAKE) 	+= -march=cascadelake
++        cflags-$(CONFIG_MCOOPERLAKE) 	+= -march=cooperlake
++        cflags-$(CONFIG_MTIGERLAKE) 	+= -march=tigerlake
++        cflags-$(CONFIG_MSAPPHIRERAPIDS) += -march=sapphirerapids
++        cflags-$(CONFIG_MROCKETLAKE) 	+= -march=rocketlake
++        cflags-$(CONFIG_MALDERLAKE) 	+= -march=alderlake
++        cflags-$(CONFIG_MRAPTORLAKE) 	+= -march=raptorlake
++        cflags-$(CONFIG_MMETEORLAKE) 	+= -march=meteorlake
++        cflags-$(CONFIG_MEMERALDRAPIDS)	+= -march=emeraldrapids
++        cflags-$(CONFIG_GENERIC_CPU2) 	+= -march=x86-64-v2
++        cflags-$(CONFIG_GENERIC_CPU3) 	+= -march=x86-64-v3
++        cflags-$(CONFIG_GENERIC_CPU4) 	+= -march=x86-64-v4
+         cflags-$(CONFIG_GENERIC_CPU)	+= -mtune=generic
+         KBUILD_CFLAGS += $(cflags-y)
+ 
+diff -up linux-6.8-rc7/arch/x86/include/asm/vermagic.h.1~ linux-6.8-rc7/arch/x86/include/asm/vermagic.h
+--- linux-6.8-rc7/arch/x86/include/asm/vermagic.h.1~	2024-03-03 22:02:52.000000000 +0100
++++ linux-6.8-rc7/arch/x86/include/asm/vermagic.h	2024-03-04 17:50:40.497606626 +0100
+@@ -17,6 +17,54 @@
+ #define MODULE_PROC_FAMILY "586MMX "
+ #elif defined CONFIG_MCORE2
+ #define MODULE_PROC_FAMILY "CORE2 "
++#elif defined CONFIG_MNATIVE_INTEL
++#define MODULE_PROC_FAMILY "NATIVE_INTEL "
++#elif defined CONFIG_MNATIVE_AMD
++#define MODULE_PROC_FAMILY "NATIVE_AMD "
++#elif defined CONFIG_MNEHALEM
++#define MODULE_PROC_FAMILY "NEHALEM "
++#elif defined CONFIG_MWESTMERE
++#define MODULE_PROC_FAMILY "WESTMERE "
++#elif defined CONFIG_MSILVERMONT
++#define MODULE_PROC_FAMILY "SILVERMONT "
++#elif defined CONFIG_MGOLDMONT
++#define MODULE_PROC_FAMILY "GOLDMONT "
++#elif defined CONFIG_MGOLDMONTPLUS
++#define MODULE_PROC_FAMILY "GOLDMONTPLUS "
++#elif defined CONFIG_MSANDYBRIDGE
++#define MODULE_PROC_FAMILY "SANDYBRIDGE "
++#elif defined CONFIG_MIVYBRIDGE
++#define MODULE_PROC_FAMILY "IVYBRIDGE "
++#elif defined CONFIG_MHASWELL
++#define MODULE_PROC_FAMILY "HASWELL "
++#elif defined CONFIG_MBROADWELL
++#define MODULE_PROC_FAMILY "BROADWELL "
++#elif defined CONFIG_MSKYLAKE
++#define MODULE_PROC_FAMILY "SKYLAKE "
++#elif defined CONFIG_MSKYLAKEX
++#define MODULE_PROC_FAMILY "SKYLAKEX "
++#elif defined CONFIG_MCANNONLAKE
++#define MODULE_PROC_FAMILY "CANNONLAKE "
++#elif defined CONFIG_MICELAKE
++#define MODULE_PROC_FAMILY "ICELAKE "
++#elif defined CONFIG_MCASCADELAKE
++#define MODULE_PROC_FAMILY "CASCADELAKE "
++#elif defined CONFIG_MCOOPERLAKE
++#define MODULE_PROC_FAMILY "COOPERLAKE "
++#elif defined CONFIG_MTIGERLAKE
++#define MODULE_PROC_FAMILY "TIGERLAKE "
++#elif defined CONFIG_MSAPPHIRERAPIDS
++#define MODULE_PROC_FAMILY "SAPPHIRERAPIDS "
++#elif defined CONFIG_ROCKETLAKE
++#define MODULE_PROC_FAMILY "ROCKETLAKE "
++#elif defined CONFIG_MALDERLAKE
++#define MODULE_PROC_FAMILY "ALDERLAKE "
++#elif defined CONFIG_MRAPTORLAKE
++#define MODULE_PROC_FAMILY "RAPTORLAKE "
++#elif defined CONFIG_MMETEORLAKE
++#define MODULE_PROC_FAMILY "METEORLAKE "
++#elif defined CONFIG_MEMERALDRAPIDS
++#define MODULE_PROC_FAMILY "EMERALDRAPIDS "
+ #elif defined CONFIG_MATOM
+ #define MODULE_PROC_FAMILY "ATOM "
+ #elif defined CONFIG_M686
+@@ -35,6 +83,32 @@
+ #define MODULE_PROC_FAMILY "K7 "
+ #elif defined CONFIG_MK8
+ #define MODULE_PROC_FAMILY "K8 "
++#elif defined CONFIG_MK8SSE3
++#define MODULE_PROC_FAMILY "K8SSE3 "
++#elif defined CONFIG_MK10
++#define MODULE_PROC_FAMILY "K10 "
++#elif defined CONFIG_MBARCELONA
++#define MODULE_PROC_FAMILY "BARCELONA "
++#elif defined CONFIG_MBOBCAT
++#define MODULE_PROC_FAMILY "BOBCAT "
++#elif defined CONFIG_MBULLDOZER
++#define MODULE_PROC_FAMILY "BULLDOZER "
++#elif defined CONFIG_MPILEDRIVER
++#define MODULE_PROC_FAMILY "PILEDRIVER "
++#elif defined CONFIG_MSTEAMROLLER
++#define MODULE_PROC_FAMILY "STEAMROLLER "
++#elif defined CONFIG_MJAGUAR
++#define MODULE_PROC_FAMILY "JAGUAR "
++#elif defined CONFIG_MEXCAVATOR
++#define MODULE_PROC_FAMILY "EXCAVATOR "
++#elif defined CONFIG_MZEN
++#define MODULE_PROC_FAMILY "ZEN "
++#elif defined CONFIG_MZEN2
++#define MODULE_PROC_FAMILY "ZEN2 "
++#elif defined CONFIG_MZEN3
++#define MODULE_PROC_FAMILY "ZEN3 "
++#elif defined CONFIG_MZEN4
++#define MODULE_PROC_FAMILY "ZEN4 "
+ #elif defined CONFIG_MELAN
+ #define MODULE_PROC_FAMILY "ELAN "
+ #elif defined CONFIG_MCRUSOE
diff --git a/d6aa52f8a15e56737de5e73f4f2acbb2632f43c0.patch b/d6aa52f8a15e56737de5e73f4f2acbb2632f43c0.patch
new file mode 100644
index 0000000..bf37709
--- /dev/null
+++ b/d6aa52f8a15e56737de5e73f4f2acbb2632f43c0.patch
@@ -0,0 +1,23 @@
+From d6aa52f8a15e56737de5e73f4f2acbb2632f43c0 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Sat, 13 Apr 2024 16:05:38 +0800
+Subject: [PATCH] arm64: rockchip_defconfig: Enable panthor GPU
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm64/configs/rockchip_defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig
+index 8d1c26296a1e2a..1a4d1c6fa8f81f 100644
+--- a/arch/arm64/configs/rockchip_defconfig
++++ b/arch/arm64/configs/rockchip_defconfig
+@@ -756,6 +756,8 @@ CONFIG_DRM_I2C_ADV7511=m
+ CONFIG_DRM_CDNS_DSI=m
+ CONFIG_DRM_DW_HDMI_CEC=m
+ CONFIG_DRM_PANFROST=y
++CONFIG_DRM_PANTHOR=m
++CONFIG_DRM_POWERVR=y
+ CONFIG_FB=y
+ CONFIG_FB_UVESA=m
+ CONFIG_FIRMWARE_EDID=y
diff --git a/dad4c5aac3a74cf3593fad9f7c7d0e83ae96bfa5.patch b/dad4c5aac3a74cf3593fad9f7c7d0e83ae96bfa5.patch
new file mode 100644
index 0000000..80bc4cc
--- /dev/null
+++ b/dad4c5aac3a74cf3593fad9f7c7d0e83ae96bfa5.patch
@@ -0,0 +1,22 @@
+From dad4c5aac3a74cf3593fad9f7c7d0e83ae96bfa5 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Fri, 27 Oct 2023 15:30:32 +0800
+Subject: [PATCH] arm64: defconfig: Enable ROCKCHIP_SAMSUNG_HDPTX phy for hdmi
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm64/configs/rockchip_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig
+index 39702bc5bc7092..e6d71cb298e87e 100644
+--- a/arch/arm64/configs/rockchip_defconfig
++++ b/arch/arm64/configs/rockchip_defconfig
+@@ -967,6 +967,7 @@ CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
+ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+ CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+ CONFIG_PHY_ROCKCHIP_PCIE=y
++CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
+ CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+ CONFIG_PHY_ROCKCHIP_TYPEC=y
+ CONFIG_PHY_ROCKCHIP_USB=y
diff --git a/dd3ada12c3f671e92f67416ba9c267e1b12ed29d.patch b/dd3ada12c3f671e92f67416ba9c267e1b12ed29d.patch
new file mode 100644
index 0000000..a99104d
--- /dev/null
+++ b/dd3ada12c3f671e92f67416ba9c267e1b12ed29d.patch
@@ -0,0 +1,45 @@
+From dd3ada12c3f671e92f67416ba9c267e1b12ed29d Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Wed, 20 Dec 2023 15:19:35 +0800
+Subject: [PATCH] arm: dts: rockchip: Fix emac on rk3036 kylin board
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm/boot/dts/rockchip/rk3036-kylin.dts | 20 ++++++++++++++++++--
+ 1 file changed, 18 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts
+index b66b9a981d71ae..1d4313f371fe4f 100644
+--- a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts
++++ b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts
+@@ -94,12 +94,28 @@
+ 	status = "okay";
+ };
+ 
++&cpu0 {
++        operating-points = <
++                /* KHz    uV */
++                 1000000 1225000
++        >;
++};
++
++&cru {
++	assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_APLL>;
++	assigned-clock-rates = <594000000>, <1000000000> ;
++};
++
+ &emac {
++	assigned-clocks = <&cru SCLK_MACPLL>;
++	assigned-clock-rates = <50000000>;
++	assigned-clock-parents = <&cru PLL_APLL>;
++	phy = <&phy0>;
++	phy-reset-duration = <10>; /* millisecond */
++	phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
+ 	phy = <&phy0>;
+-	phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
+-	phy-reset-duration = <10>; /* millisecond */
+ 
+ 	status = "okay";
+ 
diff --git a/debug.fragment b/debug.fragment
new file mode 100644
index 0000000..3536768
--- /dev/null
+++ b/debug.fragment
@@ -0,0 +1,46 @@
+# Always leave CONFIG_DEBUG_INFO and friends enabled even for
+# non-debug builds -- they're required for BTF, which in turn
+# is needed for BPF
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_BTF=y
+CONFIG_DEBUG_INFO_BTF_MODULES=y
+# CONFIG_DEBUG_INFO_SPLIT is not set
+# CONFIG_DEBUG_INFO_REDUCED is not set
+# CONFIG_DEBUG_INFO_NONE is not set
+# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
+# CONFIG_DEBUG_INFO_DWARF4 is not set
+CONFIG_DEBUG_INFO_DWARF5=y
+# CONFIG_DEBUG_INFO_COMPRESSED_NONE is not set
+# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set
+CONFIG_DEBUG_INFO_COMPRESSED_ZSTD=y
+CONFIG_MODULE_ALLOW_BTF_MISMATCH=y
+CONFIG_GDB_SCRIPTS=y
+CONFIG_FRAME_WARN=2048
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_HEADERS_INSTALL=y
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+CONFIG_VMLINUX_MAP=y
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
+# CONFIG_UAPI_HEADER_TEST is not set
+# CONFIG_COMPILE_TEST is not set
+# CONFIG_VIRTIO_DEBUG is not set
+# CONFIG_MEM_ALLOC_PROFILING is not set
+CONFIG_DEBUG_CGROUP_REF=y
+# CONFIG_FUNCTION_ERROR_INJECTION is not set
+# CONFIG_DEBUG_VFS is not set
+# CONFIG_FORTIFY_SOURCE is not set
+# CONFIG_OBJTOOL_WERROR is not set
+CONFIG_UNICODE_NORMALIZATION_KUNIT_TEST=m
+CONFIG_PRINTF_KUNIT_TEST=m
+CONFIG_SCANF_KUNIT_TEST=m
+CONFIG_SEQ_BUF_KUNIT_TEST=m
+CONFIG_KFIFO_KUNIT_TEST=m
+CONFIG_RATIONAL_KUNIT_TEST=m
+CONFIG_LONGEST_SYM_KUNIT_TEST=m
+CONFIG_BLACKHOLE_DEV_KUNIT_TEST=m
+CONFIG_INT_POW_KUNIT_TEST=m
+CONFIG_INT_LOG_KUNIT_TEST=m
+CONFIG_GCD_KUNIT_TEST=m
+CONFIG_PRIME_NUMBERS_KUNIT_TEST=m
+CONFIG_RATELIMIT_KUNIT_TEST=m
diff --git a/dfb6b6ac7b8403a37c94e5afb0b990643409cbed.patch b/dfb6b6ac7b8403a37c94e5afb0b990643409cbed.patch
new file mode 100644
index 0000000..bd3444b
--- /dev/null
+++ b/dfb6b6ac7b8403a37c94e5afb0b990643409cbed.patch
@@ -0,0 +1,49 @@
+From dfb6b6ac7b8403a37c94e5afb0b990643409cbed Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Thu, 5 Dec 2024 14:35:48 +0800
+Subject: [PATCH] arm64: rockchip_defconfig: Enable DSI2 display
+
+Enable:
+CONFIG_ROCKCHIP_DW_MIPI_DSI2=y
+CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY=y
+CONFIG_DRM_PANEL_RAYDIUM_RM67200=y
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm64/configs/rockchip_defconfig | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig
+index ae949f0148f874..c79513dfe79eb4 100644
+--- a/arch/arm64/configs/rockchip_defconfig
++++ b/arch/arm64/configs/rockchip_defconfig
+@@ -295,7 +295,6 @@ CONFIG_NVME_TARGET_FC=m
+ CONFIG_SRAM=y
+ CONFIG_EEPROM_AT24=m
+ CONFIG_EEPROM_AT25=m
+-CONFIG_EEPROM_93CX6=m
+ CONFIG_EEPROM_EE1004=m
+ # CONFIG_SCSI_PROC_FS is not set
+ CONFIG_BLK_DEV_SD=y
+@@ -721,11 +720,13 @@ CONFIG_ROCKCHIP_CDN_DP=y
+ CONFIG_ROCKCHIP_DW_HDMI=y
+ CONFIG_ROCKCHIP_DW_HDMI_QP=y
+ CONFIG_ROCKCHIP_DW_MIPI_DSI=y
++CONFIG_ROCKCHIP_DW_MIPI_DSI2=y
+ CONFIG_ROCKCHIP_INNO_HDMI=y
+ CONFIG_ROCKCHIP_LVDS=y
+ CONFIG_ROCKCHIP_RGB=y
+ CONFIG_ROCKCHIP_RK3066_HDMI=y
+ CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
++CONFIG_DRM_PANEL_RAYDIUM_RM67200=y
+ CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
+ CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
+ CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
+@@ -965,6 +966,7 @@ CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
+ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+ CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+ CONFIG_PHY_ROCKCHIP_PCIE=y
++CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY=y
+ CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
+ CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+ CONFIG_PHY_ROCKCHIP_TYPEC=y
diff --git a/disabled/0001-MultiQueue-Skiplist-Scheduler-v0.196.patch b/disabled/0001-MultiQueue-Skiplist-Scheduler-v0.196.patch
deleted file mode 100644
index c01a0cb..0000000
--- a/disabled/0001-MultiQueue-Skiplist-Scheduler-v0.196.patch
+++ /dev/null
@@ -1,10873 +0,0 @@
-From 7acac2e4000e75f3349106a8847cf1021651446b Mon Sep 17 00:00:00 2001
-From: Con Kolivas <kernel@kolivas.org>
-Date: Fri, 25 Oct 2019 14:00:52 +1100
-Subject: [PATCH 01/16] MultiQueue Skiplist Scheduler v0.196.
-
----
- .../admin-guide/kernel-parameters.txt         |    8 +
- Documentation/admin-guide/sysctl/kernel.rst   |   37 +
- Documentation/scheduler/sched-BFS.txt         |  351 +
- Documentation/scheduler/sched-MuQSS.txt       |  373 +
- arch/alpha/Kconfig                            |    2 +
- arch/arm/Kconfig                              |    2 +
- arch/arm64/Kconfig                            |    2 +
- arch/powerpc/Kconfig                          |    2 +
- arch/powerpc/platforms/cell/spufs/sched.c     |    5 -
- arch/x86/Kconfig                              |   18 +
- fs/proc/base.c                                |    2 +-
- include/linux/init_task.h                     |    4 +
- include/linux/ioprio.h                        |    2 +
- include/linux/sched.h                         |   60 +-
- include/linux/sched/deadline.h                |    9 +
- include/linux/sched/nohz.h                    |    2 +-
- include/linux/sched/prio.h                    |   12 +
- include/linux/sched/rt.h                      |    2 +
- include/linux/sched/task.h                    |    2 +-
- include/linux/skip_list.h                     |   33 +
- include/uapi/linux/sched.h                    |    9 +-
- init/Kconfig                                  |   23 +-
- init/init_task.c                              |   10 +
- init/main.c                                   |    2 +
- kernel/Kconfig.MuQSS                          |  105 +
- kernel/Makefile                               |    2 +-
- kernel/delayacct.c                            |    2 +-
- kernel/exit.c                                 |    4 +-
- kernel/kthread.c                              |   30 +-
- kernel/livepatch/transition.c                 |    6 +-
- kernel/sched/Makefile                         |   10 +-
- kernel/sched/MuQSS.c                          | 7606 +++++++++++++++++
- kernel/sched/MuQSS.h                          | 1005 +++
- kernel/sched/cpufreq_schedutil.c              |   12 +-
- kernel/sched/cpupri.h                         |    2 +
- kernel/sched/cputime.c                        |   22 +-
- kernel/sched/idle.c                           |   12 +-
- kernel/sched/sched.h                          |   40 +
- kernel/sched/topology.c                       |    9 +
- kernel/skip_list.c                            |  148 +
- kernel/sysctl.c                               |   54 +-
- kernel/time/clockevents.c                     |    5 +
- kernel/time/posix-cpu-timers.c                |    4 +-
- kernel/time/timer.c                           |    7 +-
- kernel/trace/trace_selftest.c                 |    5 +
- 45 files changed, 10010 insertions(+), 52 deletions(-)
- create mode 100644 Documentation/scheduler/sched-BFS.txt
- create mode 100644 Documentation/scheduler/sched-MuQSS.txt
- create mode 100644 include/linux/skip_list.h
- create mode 100644 kernel/Kconfig.MuQSS
- create mode 100644 kernel/sched/MuQSS.c
- create mode 100644 kernel/sched/MuQSS.h
- create mode 100644 kernel/skip_list.c
-
-diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
-index 8dee8f68fe15..e56fb275f607 100644
---- a/Documentation/admin-guide/kernel-parameters.txt
-+++ b/Documentation/admin-guide/kernel-parameters.txt
-@@ -4277,6 +4277,14 @@
- 			Memory area to be used by remote processor image,
- 			managed by CMA.
- 
-+	rqshare=	[X86] Select the MuQSS scheduler runqueue sharing type.
-+			Format: <string>
-+			smt -- Share SMT (hyperthread) sibling runqueues
-+			mc -- Share MC (multicore) sibling runqueues
-+			smp -- Share SMP runqueues
-+			none -- So not share any runqueues
-+			Default value is mc
-+
- 	rw		[KNL] Mount root device read-write on boot
- 
- 	S		[KNL] Run init in single mode
-diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst
-index 032c7cd3cede..ff41dfacb34b 100644
---- a/Documentation/admin-guide/sysctl/kernel.rst
-+++ b/Documentation/admin-guide/sysctl/kernel.rst
-@@ -46,6 +46,7 @@ show up in /proc/sys/kernel:
- - hung_task_check_interval_secs
- - hung_task_warnings
- - hyperv_record_panic_msg
-+- iso_cpu
- - kexec_load_disabled
- - kptr_restrict
- - l2cr                        [ PPC only ]
-@@ -82,6 +83,7 @@ show up in /proc/sys/kernel:
- - randomize_va_space
- - real-root-dev               ==> Documentation/admin-guide/initrd.rst
- - reboot-cmd                  [ SPARC only ]
-+- rr_interval
- - rtsig-max
- - rtsig-nr
- - sched_energy_aware
-@@ -105,6 +107,7 @@ show up in /proc/sys/kernel:
- - unknown_nmi_panic
- - watchdog
- - watchdog_thresh
-+- yield_type
- - version
- 
- 
-@@ -438,6 +441,16 @@ When kptr_restrict is set to (2), kernel pointers printed using
- %pK will be replaced with 0's regardless of privileges.
- 
- 
-+iso_cpu: (MuQSS CPU scheduler only)
-+===================================
-+
-+This sets the percentage cpu that the unprivileged SCHED_ISO tasks can
-+run effectively at realtime priority, averaged over a rolling five
-+seconds over the -whole- system, meaning all cpus.
-+
-+Set to 70 (percent) by default.
-+
-+
- l2cr: (PPC only)
- ================
- 
-@@ -905,6 +918,20 @@ ROM/Flash boot loader. Maybe to tell it what to do after
- rebooting. ???
- 
- 
-+rr_interval: (MuQSS CPU scheduler only)
-+=======================================
-+
-+This is the smallest duration that any cpu process scheduling unit
-+will run for. Increasing this value can increase throughput of cpu
-+bound tasks substantially but at the expense of increased latencies
-+overall. Conversely decreasing it will decrease average and maximum
-+latencies but at the expense of throughput. This value is in
-+milliseconds and the default value chosen depends on the number of
-+cpus available at scheduler initialisation with a minimum of 6.
-+
-+Valid values are from 1-1000.
-+
-+
- rtsig-max & rtsig-nr:
- =====================
- 
-@@ -1175,3 +1202,13 @@ is 10 seconds.
- 
- The softlockup threshold is (2 * watchdog_thresh). Setting this
- tunable to zero will disable lockup detection altogether.
-+
-+
-+yield_type: (MuQSS CPU scheduler only)
-+======================================
-+
-+This determines what type of yield calls to sched_yield will perform.
-+
-+ 0: No yield.
-+ 1: Yield only to better priority/deadline tasks. (default)
-+ 2: Expire timeslice and recalculate deadline.
-diff --git a/Documentation/scheduler/sched-BFS.txt b/Documentation/scheduler/sched-BFS.txt
-new file mode 100644
-index 000000000000..c0282002a079
---- /dev/null
-+++ b/Documentation/scheduler/sched-BFS.txt
-@@ -0,0 +1,351 @@
-+BFS - The Brain Fuck Scheduler by Con Kolivas.
-+
-+Goals.
-+
-+The goal of the Brain Fuck Scheduler, referred to as BFS from here on, is to
-+completely do away with the complex designs of the past for the cpu process
-+scheduler and instead implement one that is very simple in basic design.
-+The main focus of BFS is to achieve excellent desktop interactivity and
-+responsiveness without heuristics and tuning knobs that are difficult to
-+understand, impossible to model and predict the effect of, and when tuned to
-+one workload cause massive detriment to another.
-+
-+
-+Design summary.
-+
-+BFS is best described as a single runqueue, O(n) lookup, earliest effective
-+virtual deadline first design, loosely based on EEVDF (earliest eligible virtual
-+deadline first) and my previous Staircase Deadline scheduler. Each component
-+shall be described in order to understand the significance of, and reasoning for
-+it. The codebase when the first stable version was released was approximately
-+9000 lines less code than the existing mainline linux kernel scheduler (in
-+2.6.31). This does not even take into account the removal of documentation and
-+the cgroups code that is not used.
-+
-+Design reasoning.
-+
-+The single runqueue refers to the queued but not running processes for the
-+entire system, regardless of the number of CPUs. The reason for going back to
-+a single runqueue design is that once multiple runqueues are introduced,
-+per-CPU or otherwise, there will be complex interactions as each runqueue will
-+be responsible for the scheduling latency and fairness of the tasks only on its
-+own runqueue, and to achieve fairness and low latency across multiple CPUs, any
-+advantage in throughput of having CPU local tasks causes other disadvantages.
-+This is due to requiring a very complex balancing system to at best achieve some
-+semblance of fairness across CPUs and can only maintain relatively low latency
-+for tasks bound to the same CPUs, not across them. To increase said fairness
-+and latency across CPUs, the advantage of local runqueue locking, which makes
-+for better scalability, is lost due to having to grab multiple locks.
-+
-+A significant feature of BFS is that all accounting is done purely based on CPU
-+used and nowhere is sleep time used in any way to determine entitlement or
-+interactivity. Interactivity "estimators" that use some kind of sleep/run
-+algorithm are doomed to fail to detect all interactive tasks, and to falsely tag
-+tasks that aren't interactive as being so. The reason for this is that it is
-+close to impossible to determine that when a task is sleeping, whether it is
-+doing it voluntarily, as in a userspace application waiting for input in the
-+form of a mouse click or otherwise, or involuntarily, because it is waiting for
-+another thread, process, I/O, kernel activity or whatever. Thus, such an
-+estimator will introduce corner cases, and more heuristics will be required to
-+cope with those corner cases, introducing more corner cases and failed
-+interactivity detection and so on. Interactivity in BFS is built into the design
-+by virtue of the fact that tasks that are waking up have not used up their quota
-+of CPU time, and have earlier effective deadlines, thereby making it very likely
-+they will preempt any CPU bound task of equivalent nice level. See below for
-+more information on the virtual deadline mechanism. Even if they do not preempt
-+a running task, because the rr interval is guaranteed to have a bound upper
-+limit on how long a task will wait for, it will be scheduled within a timeframe
-+that will not cause visible interface jitter.
-+
-+
-+Design details.
-+
-+Task insertion.
-+
-+BFS inserts tasks into each relevant queue as an O(1) insertion into a double
-+linked list. On insertion, *every* running queue is checked to see if the newly
-+queued task can run on any idle queue, or preempt the lowest running task on the
-+system. This is how the cross-CPU scheduling of BFS achieves significantly lower
-+latency per extra CPU the system has. In this case the lookup is, in the worst
-+case scenario, O(n) where n is the number of CPUs on the system.
-+
-+Data protection.
-+
-+BFS has one single lock protecting the process local data of every task in the
-+global queue. Thus every insertion, removal and modification of task data in the
-+global runqueue needs to grab the global lock. However, once a task is taken by
-+a CPU, the CPU has its own local data copy of the running process' accounting
-+information which only that CPU accesses and modifies (such as during a
-+timer tick) thus allowing the accounting data to be updated lockless. Once a
-+CPU has taken a task to run, it removes it from the global queue. Thus the
-+global queue only ever has, at most,
-+
-+	(number of tasks requesting cpu time) - (number of logical CPUs) + 1
-+
-+tasks in the global queue. This value is relevant for the time taken to look up
-+tasks during scheduling. This will increase if many tasks with CPU affinity set
-+in their policy to limit which CPUs they're allowed to run on if they outnumber
-+the number of CPUs. The +1 is because when rescheduling a task, the CPU's
-+currently running task is put back on the queue. Lookup will be described after
-+the virtual deadline mechanism is explained.
-+
-+Virtual deadline.
-+
-+The key to achieving low latency, scheduling fairness, and "nice level"
-+distribution in BFS is entirely in the virtual deadline mechanism. The one
-+tunable in BFS is the rr_interval, or "round robin interval". This is the
-+maximum time two SCHED_OTHER (or SCHED_NORMAL, the common scheduling policy)
-+tasks of the same nice level will be running for, or looking at it the other
-+way around, the longest duration two tasks of the same nice level will be
-+delayed for. When a task requests cpu time, it is given a quota (time_slice)
-+equal to the rr_interval and a virtual deadline. The virtual deadline is
-+offset from the current time in jiffies by this equation:
-+
-+	jiffies + (prio_ratio * rr_interval)
-+
-+The prio_ratio is determined as a ratio compared to the baseline of nice -20
-+and increases by 10% per nice level. The deadline is a virtual one only in that
-+no guarantee is placed that a task will actually be scheduled by this time, but
-+it is used to compare which task should go next. There are three components to
-+how a task is next chosen. First is time_slice expiration. If a task runs out
-+of its time_slice, it is descheduled, the time_slice is refilled, and the
-+deadline reset to that formula above. Second is sleep, where a task no longer
-+is requesting CPU for whatever reason. The time_slice and deadline are _not_
-+adjusted in this case and are just carried over for when the task is next
-+scheduled. Third is preemption, and that is when a newly waking task is deemed
-+higher priority than a currently running task on any cpu by virtue of the fact
-+that it has an earlier virtual deadline than the currently running task. The
-+earlier deadline is the key to which task is next chosen for the first and
-+second cases. Once a task is descheduled, it is put back on the queue, and an
-+O(n) lookup of all queued-but-not-running tasks is done to determine which has
-+the earliest deadline and that task is chosen to receive CPU next.
-+
-+The CPU proportion of different nice tasks works out to be approximately the
-+
-+	(prio_ratio difference)^2
-+
-+The reason it is squared is that a task's deadline does not change while it is
-+running unless it runs out of time_slice. Thus, even if the time actually
-+passes the deadline of another task that is queued, it will not get CPU time
-+unless the current running task deschedules, and the time "base" (jiffies) is
-+constantly moving.
-+
-+Task lookup.
-+
-+BFS has 103 priority queues. 100 of these are dedicated to the static priority
-+of realtime tasks, and the remaining 3 are, in order of best to worst priority,
-+SCHED_ISO (isochronous), SCHED_NORMAL, and SCHED_IDLEPRIO (idle priority
-+scheduling). When a task of these priorities is queued, a bitmap of running
-+priorities is set showing which of these priorities has tasks waiting for CPU
-+time. When a CPU is made to reschedule, the lookup for the next task to get
-+CPU time is performed in the following way:
-+
-+First the bitmap is checked to see what static priority tasks are queued. If
-+any realtime priorities are found, the corresponding queue is checked and the
-+first task listed there is taken (provided CPU affinity is suitable) and lookup
-+is complete. If the priority corresponds to a SCHED_ISO task, they are also
-+taken in FIFO order (as they behave like SCHED_RR). If the priority corresponds
-+to either SCHED_NORMAL or SCHED_IDLEPRIO, then the lookup becomes O(n). At this
-+stage, every task in the runlist that corresponds to that priority is checked
-+to see which has the earliest set deadline, and (provided it has suitable CPU
-+affinity) it is taken off the runqueue and given the CPU. If a task has an
-+expired deadline, it is taken and the rest of the lookup aborted (as they are
-+chosen in FIFO order).
-+
-+Thus, the lookup is O(n) in the worst case only, where n is as described
-+earlier, as tasks may be chosen before the whole task list is looked over.
-+
-+
-+Scalability.
-+
-+The major limitations of BFS will be that of scalability, as the separate
-+runqueue designs will have less lock contention as the number of CPUs rises.
-+However they do not scale linearly even with separate runqueues as multiple
-+runqueues will need to be locked concurrently on such designs to be able to
-+achieve fair CPU balancing, to try and achieve some sort of nice-level fairness
-+across CPUs, and to achieve low enough latency for tasks on a busy CPU when
-+other CPUs would be more suited. BFS has the advantage that it requires no
-+balancing algorithm whatsoever, as balancing occurs by proxy simply because
-+all CPUs draw off the global runqueue, in priority and deadline order. Despite
-+the fact that scalability is _not_ the prime concern of BFS, it both shows very
-+good scalability to smaller numbers of CPUs and is likely a more scalable design
-+at these numbers of CPUs.
-+
-+It also has some very low overhead scalability features built into the design
-+when it has been deemed their overhead is so marginal that they're worth adding.
-+The first is the local copy of the running process' data to the CPU it's running
-+on to allow that data to be updated lockless where possible. Then there is
-+deference paid to the last CPU a task was running on, by trying that CPU first
-+when looking for an idle CPU to use the next time it's scheduled. Finally there
-+is the notion of cache locality beyond the last running CPU. The sched_domains
-+information is used to determine the relative virtual "cache distance" that
-+other CPUs have from the last CPU a task was running on. CPUs with shared
-+caches, such as SMT siblings, or multicore CPUs with shared caches, are treated
-+as cache local. CPUs without shared caches are treated as not cache local, and
-+CPUs on different NUMA nodes are treated as very distant. This "relative cache
-+distance" is used by modifying the virtual deadline value when doing lookups.
-+Effectively, the deadline is unaltered between "cache local" CPUs, doubled for
-+"cache distant" CPUs, and quadrupled for "very distant" CPUs. The reasoning
-+behind the doubling of deadlines is as follows. The real cost of migrating a
-+task from one CPU to another is entirely dependant on the cache footprint of
-+the task, how cache intensive the task is, how long it's been running on that
-+CPU to take up the bulk of its cache, how big the CPU cache is, how fast and
-+how layered the CPU cache is, how fast a context switch is... and so on. In
-+other words, it's close to random in the real world where we do more than just
-+one sole workload. The only thing we can be sure of is that it's not free. So
-+BFS uses the principle that an idle CPU is a wasted CPU and utilising idle CPUs
-+is more important than cache locality, and cache locality only plays a part
-+after that. Doubling the effective deadline is based on the premise that the
-+"cache local" CPUs will tend to work on the same tasks up to double the number
-+of cache local CPUs, and once the workload is beyond that amount, it is likely
-+that none of the tasks are cache warm anywhere anyway. The quadrupling for NUMA
-+is a value I pulled out of my arse.
-+
-+When choosing an idle CPU for a waking task, the cache locality is determined
-+according to where the task last ran and then idle CPUs are ranked from best
-+to worst to choose the most suitable idle CPU based on cache locality, NUMA
-+node locality and hyperthread sibling business. They are chosen in the
-+following preference (if idle):
-+
-+* Same core, idle or busy cache, idle threads
-+* Other core, same cache, idle or busy cache, idle threads.
-+* Same node, other CPU, idle cache, idle threads.
-+* Same node, other CPU, busy cache, idle threads.
-+* Same core, busy threads.
-+* Other core, same cache, busy threads.
-+* Same node, other CPU, busy threads.
-+* Other node, other CPU, idle cache, idle threads.
-+* Other node, other CPU, busy cache, idle threads.
-+* Other node, other CPU, busy threads.
-+
-+This shows the SMT or "hyperthread" awareness in the design as well which will
-+choose a real idle core first before a logical SMT sibling which already has
-+tasks on the physical CPU.
-+
-+Early benchmarking of BFS suggested scalability dropped off at the 16 CPU mark.
-+However this benchmarking was performed on an earlier design that was far less
-+scalable than the current one so it's hard to know how scalable it is in terms
-+of both CPUs (due to the global runqueue) and heavily loaded machines (due to
-+O(n) lookup) at this stage. Note that in terms of scalability, the number of
-+_logical_ CPUs matters, not the number of _physical_ CPUs. Thus, a dual (2x)
-+quad core (4X) hyperthreaded (2X) machine is effectively a 16X. Newer benchmark
-+results are very promising indeed, without needing to tweak any knobs, features
-+or options. Benchmark contributions are most welcome.
-+
-+
-+Features
-+
-+As the initial prime target audience for BFS was the average desktop user, it
-+was designed to not need tweaking, tuning or have features set to obtain benefit
-+from it. Thus the number of knobs and features has been kept to an absolute
-+minimum and should not require extra user input for the vast majority of cases.
-+There are precisely 2 tunables, and 2 extra scheduling policies. The rr_interval
-+and iso_cpu tunables, and the SCHED_ISO and SCHED_IDLEPRIO policies. In addition
-+to this, BFS also uses sub-tick accounting. What BFS does _not_ now feature is
-+support for CGROUPS. The average user should neither need to know what these
-+are, nor should they need to be using them to have good desktop behaviour.
-+
-+rr_interval
-+
-+There is only one "scheduler" tunable, the round robin interval. This can be
-+accessed in
-+
-+	/proc/sys/kernel/rr_interval
-+
-+The value is in milliseconds, and the default value is set to 6 on a
-+uniprocessor machine, and automatically set to a progressively higher value on
-+multiprocessor machines. The reasoning behind increasing the value on more CPUs
-+is that the effective latency is decreased by virtue of there being more CPUs on
-+BFS (for reasons explained above), and increasing the value allows for less
-+cache contention and more throughput. Valid values are from 1 to 1000
-+Decreasing the value will decrease latencies at the cost of decreasing
-+throughput, while increasing it will improve throughput, but at the cost of
-+worsening latencies. The accuracy of the rr interval is limited by HZ resolution
-+of the kernel configuration. Thus, the worst case latencies are usually slightly
-+higher than this actual value. The default value of 6 is not an arbitrary one.
-+It is based on the fact that humans can detect jitter at approximately 7ms, so
-+aiming for much lower latencies is pointless under most circumstances. It is
-+worth noting this fact when comparing the latency performance of BFS to other
-+schedulers. Worst case latencies being higher than 7ms are far worse than
-+average latencies not being in the microsecond range.
-+
-+Isochronous scheduling.
-+
-+Isochronous scheduling is a unique scheduling policy designed to provide
-+near-real-time performance to unprivileged (ie non-root) users without the
-+ability to starve the machine indefinitely. Isochronous tasks (which means
-+"same time") are set using, for example, the schedtool application like so:
-+
-+	schedtool -I -e amarok
-+
-+This will start the audio application "amarok" as SCHED_ISO. How SCHED_ISO works
-+is that it has a priority level between true realtime tasks and SCHED_NORMAL
-+which would allow them to preempt all normal tasks, in a SCHED_RR fashion (ie,
-+if multiple SCHED_ISO tasks are running, they purely round robin at rr_interval
-+rate). However if ISO tasks run for more than a tunable finite amount of time,
-+they are then demoted back to SCHED_NORMAL scheduling. This finite amount of
-+time is the percentage of _total CPU_ available across the machine, configurable
-+as a percentage in the following "resource handling" tunable (as opposed to a
-+scheduler tunable):
-+
-+	/proc/sys/kernel/iso_cpu
-+
-+and is set to 70% by default. It is calculated over a rolling 5 second average
-+Because it is the total CPU available, it means that on a multi CPU machine, it
-+is possible to have an ISO task running as realtime scheduling indefinitely on
-+just one CPU, as the other CPUs will be available. Setting this to 100 is the
-+equivalent of giving all users SCHED_RR access and setting it to 0 removes the
-+ability to run any pseudo-realtime tasks.
-+
-+A feature of BFS is that it detects when an application tries to obtain a
-+realtime policy (SCHED_RR or SCHED_FIFO) and the caller does not have the
-+appropriate privileges to use those policies. When it detects this, it will
-+give the task SCHED_ISO policy instead. Thus it is transparent to the user.
-+Because some applications constantly set their policy as well as their nice
-+level, there is potential for them to undo the override specified by the user
-+on the command line of setting the policy to SCHED_ISO. To counter this, once
-+a task has been set to SCHED_ISO policy, it needs superuser privileges to set
-+it back to SCHED_NORMAL. This will ensure the task remains ISO and all child
-+processes and threads will also inherit the ISO policy.
-+
-+Idleprio scheduling.
-+
-+Idleprio scheduling is a scheduling policy designed to give out CPU to a task
-+_only_ when the CPU would be otherwise idle. The idea behind this is to allow
-+ultra low priority tasks to be run in the background that have virtually no
-+effect on the foreground tasks. This is ideally suited to distributed computing
-+clients (like setiathome, folding, mprime etc) but can also be used to start
-+a video encode or so on without any slowdown of other tasks. To avoid this
-+policy from grabbing shared resources and holding them indefinitely, if it
-+detects a state where the task is waiting on I/O, the machine is about to
-+suspend to ram and so on, it will transiently schedule them as SCHED_NORMAL. As
-+per the Isochronous task management, once a task has been scheduled as IDLEPRIO,
-+it cannot be put back to SCHED_NORMAL without superuser privileges. Tasks can
-+be set to start as SCHED_IDLEPRIO with the schedtool command like so:
-+
-+	schedtool -D -e ./mprime
-+
-+Subtick accounting.
-+
-+It is surprisingly difficult to get accurate CPU accounting, and in many cases,
-+the accounting is done by simply determining what is happening at the precise
-+moment a timer tick fires off. This becomes increasingly inaccurate as the
-+timer tick frequency (HZ) is lowered. It is possible to create an application
-+which uses almost 100% CPU, yet by being descheduled at the right time, records
-+zero CPU usage. While the main problem with this is that there are possible
-+security implications, it is also difficult to determine how much CPU a task
-+really does use. BFS tries to use the sub-tick accounting from the TSC clock,
-+where possible, to determine real CPU usage. This is not entirely reliable, but
-+is far more likely to produce accurate CPU usage data than the existing designs
-+and will not show tasks as consuming no CPU usage when they actually are. Thus,
-+the amount of CPU reported as being used by BFS will more accurately represent
-+how much CPU the task itself is using (as is shown for example by the 'time'
-+application), so the reported values may be quite different to other schedulers.
-+Values reported as the 'load' are more prone to problems with this design, but
-+per process values are closer to real usage. When comparing throughput of BFS
-+to other designs, it is important to compare the actual completed work in terms
-+of total wall clock time taken and total work done, rather than the reported
-+"cpu usage".
-+
-+
-+Con Kolivas <kernel@kolivas.org> Fri Aug 27 2010
-diff --git a/Documentation/scheduler/sched-MuQSS.txt b/Documentation/scheduler/sched-MuQSS.txt
-new file mode 100644
-index 000000000000..ae28b85c9995
---- /dev/null
-+++ b/Documentation/scheduler/sched-MuQSS.txt
-@@ -0,0 +1,373 @@
-+MuQSS - The Multiple Queue Skiplist Scheduler by Con Kolivas.
-+
-+MuQSS is a per-cpu runqueue variant of the original BFS scheduler with
-+one 8 level skiplist per runqueue, and fine grained locking for much more
-+scalability.
-+
-+
-+Goals.
-+
-+The goal of the Multiple Queue Skiplist Scheduler, referred to as MuQSS from
-+here on (pronounced mux) is to completely do away with the complex designs of
-+the past for the cpu process scheduler and instead implement one that is very
-+simple in basic design. The main focus of MuQSS is to achieve excellent desktop
-+interactivity and responsiveness without heuristics and tuning knobs that are
-+difficult to understand, impossible to model and predict the effect of, and when
-+tuned to one workload cause massive detriment to another, while still being
-+scalable to many CPUs and processes.
-+
-+
-+Design summary.
-+
-+MuQSS is best described as per-cpu multiple runqueue, O(log n) insertion, O(1)
-+lookup, earliest effective virtual deadline first tickless design, loosely based
-+on EEVDF (earliest eligible virtual deadline first) and my previous Staircase
-+Deadline scheduler, and evolved from the single runqueue O(n) BFS scheduler.
-+Each component shall be described in order to understand the significance of,
-+and reasoning for it.
-+
-+
-+Design reasoning.
-+
-+In BFS, the use of a single runqueue across all CPUs meant that each CPU would
-+need to scan the entire runqueue looking for the process with the earliest
-+deadline and schedule that next, regardless of which CPU it originally came
-+from. This made BFS deterministic with respect to latency and provided
-+guaranteed latencies dependent on number of processes and CPUs. The single
-+runqueue, however, meant that all CPUs would compete for the single lock
-+protecting it, which would lead to increasing lock contention as the number of
-+CPUs rose and appeared to limit scalability of common workloads beyond 16
-+logical CPUs. Additionally, the O(n) lookup of the runqueue list obviously
-+increased overhead proportionate to the number of queued proecesses and led to
-+cache thrashing while iterating over the linked list.
-+
-+MuQSS is an evolution of BFS, designed to maintain the same scheduling
-+decision mechanism and be virtually deterministic without relying on the
-+constrained design of the single runqueue by splitting out the single runqueue
-+to be per-CPU and use skiplists instead of linked lists.
-+
-+The original reason for going back to a single runqueue design for BFS was that
-+once multiple runqueues are introduced, per-CPU or otherwise, there will be
-+complex interactions as each runqueue will be responsible for the scheduling
-+latency and fairness of the tasks only on its own runqueue, and to achieve
-+fairness and low latency across multiple CPUs, any advantage in throughput of
-+having CPU local tasks causes other disadvantages. This is due to requiring a
-+very complex balancing system to at best achieve some semblance of fairness
-+across CPUs and can only maintain relatively low latency for tasks bound to the
-+same CPUs, not across them. To increase said fairness and latency across CPUs,
-+the advantage of local runqueue locking, which makes for better scalability, is
-+lost due to having to grab multiple locks.
-+
-+MuQSS works around the problems inherent in multiple runqueue designs by
-+making its skip lists priority ordered and through novel use of lockless
-+examination of each other runqueue it can decide if it should take the earliest
-+deadline task from another runqueue for latency reasons, or for CPU balancing
-+reasons. It still does not have a balancing system, choosing to allow the
-+next task scheduling decision and task wakeup CPU choice to allow balancing to
-+happen by virtue of its choices.
-+
-+As a further evolution of the design, MuQSS normally configures sharing of
-+runqueues in a logical fashion for when CPU resources are shared for improved
-+latency and throughput. By default it shares runqueues and locks between
-+multicore siblings. Optionally it can be configured to run with sharing of
-+SMT siblings only, all SMP packages or no sharing at all. Additionally it can
-+be selected at boot time.
-+
-+
-+Design details.
-+
-+Custom skip list implementation:
-+
-+To avoid the overhead of building up and tearing down skip list structures,
-+the variant used by MuQSS has a number of optimisations making it specific for
-+its use case in the scheduler. It uses static arrays of 8 'levels' instead of
-+building up and tearing down structures dynamically. This makes each runqueue
-+only scale O(log N) up to 64k tasks. However as there is one runqueue per CPU
-+it means that it scales O(log N) up to 64k x number of logical CPUs which is
-+far beyond the realistic task limits each CPU could handle. By being 8 levels
-+it also makes the array exactly one cacheline in size. Additionally, each
-+skip list node is bidirectional making insertion and removal amortised O(1),
-+being O(k) where k is 1-8. Uniquely, we are only ever interested in the very
-+first entry in each list at all times with MuQSS, so there is never a need to
-+do a search and thus look up is always O(1). In interactive mode, the queues
-+will be searched beyond their first entry if the first task is not suitable
-+for affinity or SMT nice reasons.
-+
-+Task insertion:
-+
-+MuQSS inserts tasks into a per CPU runqueue as an O(log N) insertion into
-+a custom skip list as described above (based on the original design by William
-+Pugh). Insertion is ordered in such a way that there is never a need to do a
-+search by ordering tasks according to static priority primarily, and then
-+virtual deadline at the time of insertion.
-+
-+Niffies:
-+
-+Niffies are a monotonic forward moving timer not unlike the "jiffies" but are
-+of nanosecond resolution. Niffies are calculated per-runqueue from the high
-+resolution TSC timers, and in order to maintain fairness are synchronised
-+between CPUs whenever both runqueues are locked concurrently.
-+
-+Virtual deadline:
-+
-+The key to achieving low latency, scheduling fairness, and "nice level"
-+distribution in MuQSS is entirely in the virtual deadline mechanism. The one
-+tunable in MuQSS is the rr_interval, or "round robin interval". This is the
-+maximum time two SCHED_OTHER (or SCHED_NORMAL, the common scheduling policy)
-+tasks of the same nice level will be running for, or looking at it the other
-+way around, the longest duration two tasks of the same nice level will be
-+delayed for. When a task requests cpu time, it is given a quota (time_slice)
-+equal to the rr_interval and a virtual deadline. The virtual deadline is
-+offset from the current time in niffies by this equation:
-+
-+	niffies + (prio_ratio * rr_interval)
-+
-+The prio_ratio is determined as a ratio compared to the baseline of nice -20
-+and increases by 10% per nice level. The deadline is a virtual one only in that
-+no guarantee is placed that a task will actually be scheduled by this time, but
-+it is used to compare which task should go next. There are three components to
-+how a task is next chosen. First is time_slice expiration. If a task runs out
-+of its time_slice, it is descheduled, the time_slice is refilled, and the
-+deadline reset to that formula above. Second is sleep, where a task no longer
-+is requesting CPU for whatever reason. The time_slice and deadline are _not_
-+adjusted in this case and are just carried over for when the task is next
-+scheduled. Third is preemption, and that is when a newly waking task is deemed
-+higher priority than a currently running task on any cpu by virtue of the fact
-+that it has an earlier virtual deadline than the currently running task. The
-+earlier deadline is the key to which task is next chosen for the first and
-+second cases.
-+
-+The CPU proportion of different nice tasks works out to be approximately the
-+
-+	(prio_ratio difference)^2
-+
-+The reason it is squared is that a task's deadline does not change while it is
-+running unless it runs out of time_slice. Thus, even if the time actually
-+passes the deadline of another task that is queued, it will not get CPU time
-+unless the current running task deschedules, and the time "base" (niffies) is
-+constantly moving.
-+
-+Task lookup:
-+
-+As tasks are already pre-ordered according to anticipated scheduling order in
-+the skip lists, lookup for the next suitable task per-runqueue is always a
-+matter of simply selecting the first task in the 0th level skip list entry.
-+In order to maintain optimal latency and fairness across CPUs, MuQSS does a
-+novel examination of every other runqueue in cache locality order, choosing the
-+best task across all runqueues. This provides near-determinism of how long any
-+task across the entire system may wait before receiving CPU time. The other
-+runqueues are first examine lockless and then trylocked to minimise the
-+potential lock contention if they are likely to have a suitable better task.
-+Each other runqueue lock is only held for as long as it takes to examine the
-+entry for suitability. In "interactive" mode, the default setting, MuQSS will
-+look for the best deadline task across all CPUs, while in !interactive mode,
-+it will only select a better deadline task from another CPU if it is more
-+heavily laden than the current one.
-+
-+Lookup is therefore O(k) where k is number of CPUs.
-+
-+
-+Latency.
-+
-+Through the use of virtual deadlines to govern the scheduling order of normal
-+tasks, queue-to-activation latency per runqueue is guaranteed to be bound by
-+the rr_interval tunable which is set to 6ms by default. This means that the
-+longest a CPU bound task will wait for more CPU is proportional to the number
-+of running tasks and in the common case of 0-2 running tasks per CPU, will be
-+under the 7ms threshold for human perception of jitter. Additionally, as newly
-+woken tasks will have an early deadline from their previous runtime, the very
-+tasks that are usually latency sensitive will have the shortest interval for
-+activation, usually preempting any existing CPU bound tasks.
-+
-+Tickless expiry:
-+
-+A feature of MuQSS is that it is not tied to the resolution of the chosen tick
-+rate in Hz, instead depending entirely on the high resolution timers where
-+possible for sub-millisecond accuracy on timeouts regarless of the underlying
-+tick rate. This allows MuQSS to be run with the low overhead of low Hz rates
-+such as 100 by default, benefiting from the improved throughput and lower
-+power usage it provides. Another advantage of this approach is that in
-+combination with the Full No HZ option, which disables ticks on running task
-+CPUs instead of just idle CPUs, the tick can be disabled at all times
-+regardless of how many tasks are running instead of being limited to just one
-+running task. Note that this option is NOT recommended for regular desktop
-+users.
-+
-+
-+Scalability and balancing.
-+
-+Unlike traditional approaches where balancing is a combination of CPU selection
-+at task wakeup and intermittent balancing based on a vast array of rules set
-+according to architecture, busyness calculations and special case management,
-+MuQSS indirectly balances on the fly at task wakeup and next task selection.
-+During initialisation, MuQSS creates a cache coherency ordered list of CPUs for
-+each logical CPU and uses this to aid task/CPU selection when CPUs are busy.
-+Additionally it selects any idle CPUs, if they are available, at any time over
-+busy CPUs according to the following preference:
-+
-+ * Same thread, idle or busy cache, idle or busy threads
-+ * Other core, same cache, idle or busy cache, idle threads.
-+ * Same node, other CPU, idle cache, idle threads.
-+ * Same node, other CPU, busy cache, idle threads.
-+ * Other core, same cache, busy threads.
-+ * Same node, other CPU, busy threads.
-+ * Other node, other CPU, idle cache, idle threads.
-+ * Other node, other CPU, busy cache, idle threads.
-+ * Other node, other CPU, busy threads.
-+
-+Mux is therefore SMT, MC and Numa aware without the need for extra
-+intermittent balancing to maintain CPUs busy and make the most of cache
-+coherency.
-+
-+
-+Features
-+
-+As the initial prime target audience for MuQSS was the average desktop user, it
-+was designed to not need tweaking, tuning or have features set to obtain benefit
-+from it. Thus the number of knobs and features has been kept to an absolute
-+minimum and should not require extra user input for the vast majority of cases.
-+There are 3 optional tunables, and 2 extra scheduling policies. The rr_interval,
-+interactive, and iso_cpu tunables, and the SCHED_ISO and SCHED_IDLEPRIO
-+policies. In addition to this, MuQSS also uses sub-tick accounting. What MuQSS
-+does _not_ now feature is support for CGROUPS. The average user should neither
-+need to know what these are, nor should they need to be using them to have good
-+desktop behaviour. However since some applications refuse to work without
-+cgroups, one can enable them with MuQSS as a stub and the filesystem will be
-+created which will allow the applications to work.
-+
-+rr_interval:
-+
-+	/proc/sys/kernel/rr_interval
-+
-+The value is in milliseconds, and the default value is set to 6. Valid values
-+are from 1 to 1000 Decreasing the value will decrease latencies at the cost of
-+decreasing throughput, while increasing it will improve throughput, but at the
-+cost of worsening latencies. It is based on the fact that humans can detect
-+jitter at approximately 7ms, so aiming for much lower latencies is pointless
-+under most circumstances. It is worth noting this fact when comparing the
-+latency performance of MuQSS to other schedulers. Worst case latencies being
-+higher than 7ms are far worse than average latencies not being in the
-+microsecond range.
-+
-+interactive:
-+
-+	/proc/sys/kernel/interactive
-+
-+The value is a simple boolean of 1 for on and 0 for off and is set to on by
-+default. Disabling this will disable the near-determinism of MuQSS when
-+selecting the next task by not examining all CPUs for the earliest deadline
-+task, or which CPU to wake to, instead prioritising CPU balancing for improved
-+throughput. Latency will still be bound by rr_interval, but on a per-CPU basis
-+instead of across the whole system.
-+
-+Runqueue sharing.
-+
-+By default MuQSS chooses to share runqueue resources (specifically the skip
-+list and locking) between multicore siblings. It is configurable at build time
-+to select between None, SMT, MC and SMP, corresponding to no sharing, sharing
-+only between simultaneous mulithreading siblings, multicore siblings, or
-+symmetric multiprocessing physical packages. Additionally it can be se at
-+bootime with the use of the rqshare parameter. The reason for configurability
-+is that some architectures have CPUs with many multicore siblings (>= 16)
-+where it may be detrimental to throughput to share runqueues and another
-+sharing option may be desirable. Additionally, more sharing than usual can
-+improve latency on a system-wide level at the expense of throughput if desired.
-+
-+The options are:
-+none, smt, mc, smp
-+
-+eg:
-+	rqshare=mc
-+
-+Isochronous scheduling:
-+
-+Isochronous scheduling is a unique scheduling policy designed to provide
-+near-real-time performance to unprivileged (ie non-root) users without the
-+ability to starve the machine indefinitely. Isochronous tasks (which means
-+"same time") are set using, for example, the schedtool application like so:
-+
-+	schedtool -I -e amarok
-+
-+This will start the audio application "amarok" as SCHED_ISO. How SCHED_ISO works
-+is that it has a priority level between true realtime tasks and SCHED_NORMAL
-+which would allow them to preempt all normal tasks, in a SCHED_RR fashion (ie,
-+if multiple SCHED_ISO tasks are running, they purely round robin at rr_interval
-+rate). However if ISO tasks run for more than a tunable finite amount of time,
-+they are then demoted back to SCHED_NORMAL scheduling. This finite amount of
-+time is the percentage of CPU available per CPU, configurable as a percentage in
-+the following "resource handling" tunable (as opposed to a scheduler tunable):
-+
-+iso_cpu:
-+
-+	/proc/sys/kernel/iso_cpu
-+
-+and is set to 70% by default. It is calculated over a rolling 5 second average
-+Because it is the total CPU available, it means that on a multi CPU machine, it
-+is possible to have an ISO task running as realtime scheduling indefinitely on
-+just one CPU, as the other CPUs will be available. Setting this to 100 is the
-+equivalent of giving all users SCHED_RR access and setting it to 0 removes the
-+ability to run any pseudo-realtime tasks.
-+
-+A feature of MuQSS is that it detects when an application tries to obtain a
-+realtime policy (SCHED_RR or SCHED_FIFO) and the caller does not have the
-+appropriate privileges to use those policies. When it detects this, it will
-+give the task SCHED_ISO policy instead. Thus it is transparent to the user.
-+
-+
-+Idleprio scheduling:
-+
-+Idleprio scheduling is a scheduling policy designed to give out CPU to a task
-+_only_ when the CPU would be otherwise idle. The idea behind this is to allow
-+ultra low priority tasks to be run in the background that have virtually no
-+effect on the foreground tasks. This is ideally suited to distributed computing
-+clients (like setiathome, folding, mprime etc) but can also be used to start a
-+video encode or so on without any slowdown of other tasks. To avoid this policy
-+from grabbing shared resources and holding them indefinitely, if it detects a
-+state where the task is waiting on I/O, the machine is about to suspend to ram
-+and so on, it will transiently schedule them as SCHED_NORMAL. Once a task has
-+been scheduled as IDLEPRIO, it cannot be put back to SCHED_NORMAL without
-+superuser privileges since it is effectively a lower scheduling policy. Tasks
-+can be set to start as SCHED_IDLEPRIO with the schedtool command like so:
-+
-+schedtool -D -e ./mprime
-+
-+Subtick accounting:
-+
-+It is surprisingly difficult to get accurate CPU accounting, and in many cases,
-+the accounting is done by simply determining what is happening at the precise
-+moment a timer tick fires off. This becomes increasingly inaccurate as the timer
-+tick frequency (HZ) is lowered. It is possible to create an application which
-+uses almost 100% CPU, yet by being descheduled at the right time, records zero
-+CPU usage. While the main problem with this is that there are possible security
-+implications, it is also difficult to determine how much CPU a task really does
-+use. Mux uses sub-tick accounting from the TSC clock to determine real CPU
-+usage. Thus, the amount of CPU reported as being used by MuQSS will more
-+accurately represent how much CPU the task itself is using (as is shown for
-+example by the 'time' application), so the reported values may be quite
-+different to other schedulers. When comparing throughput of MuQSS to other
-+designs, it is important to compare the actual completed work in terms of total
-+wall clock time taken and total work done, rather than the reported "cpu usage".
-+
-+Symmetric MultiThreading (SMT) aware nice:
-+
-+SMT, a.k.a. hyperthreading, is a very common feature on modern CPUs. While the
-+logical CPU count rises by adding thread units to each CPU core, allowing more
-+than one task to be run simultaneously on the same core, the disadvantage of it
-+is that the CPU power is shared between the tasks, not summating to the power
-+of two CPUs. The practical upshot of this is that two tasks running on
-+separate threads of the same core run significantly slower than if they had one
-+core each to run on. While smart CPU selection allows each task to have a core
-+to itself whenever available (as is done on MuQSS), it cannot offset the
-+slowdown that occurs when the cores are all loaded and only a thread is left.
-+Most of the time this is harmless as the CPU is effectively overloaded at this
-+point and the extra thread is of benefit. However when running a niced task in
-+the presence of an un-niced task (say nice 19 v nice 0), the nice task gets
-+precisely the same amount of CPU power as the unniced one. MuQSS has an
-+optional configuration feature known as SMT-NICE which selectively idles the
-+secondary niced thread for a period proportional to the nice difference,
-+allowing CPU distribution according to nice level to be maintained, at the
-+expense of a small amount of extra overhead. If this is configured in on a
-+machine without SMT threads, the overhead is minimal.
-+
-+
-+Con Kolivas <kernel@kolivas.org> Sat, 29th October 2016
-diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
-index ef179033a7c2..14b576a531ad 100644
---- a/arch/alpha/Kconfig
-+++ b/arch/alpha/Kconfig
-@@ -665,6 +665,8 @@ config HZ
- 	default 1200 if HZ_1200
- 	default 1024
- 
-+source "kernel/Kconfig.MuQSS"
-+
- config SRM_ENV
- 	tristate "SRM environment through procfs"
- 	depends on PROC_FS
-diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
-index 8a50efb559f3..d8507d20c258 100644
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1238,6 +1238,8 @@ config SCHED_SMT
- 	  MultiThreading at a cost of slightly increased overhead in some
- 	  places. If unsure say N here.
- 
-+source "kernel/Kconfig.MuQSS"
-+
- config HAVE_ARM_SCU
- 	bool
- 	help
-diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
-index 3f047afb982c..d35eae0a5c7d 100644
---- a/arch/arm64/Kconfig
-+++ b/arch/arm64/Kconfig
-@@ -864,6 +864,8 @@ config SCHED_SMT
- 	  MultiThreading at a cost of slightly increased overhead in some
- 	  places. If unsure say N here.
- 
-+source "kernel/Kconfig.MuQSS"
-+
- config NR_CPUS
- 	int "Maximum number of CPUs (2-4096)"
- 	range 2 4096
-diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
-index 3e56c9c2f16e..ecee9c2a0062 100644
---- a/arch/powerpc/Kconfig
-+++ b/arch/powerpc/Kconfig
-@@ -853,6 +853,8 @@ config SCHED_SMT
- 	  when dealing with POWER5 cpus at a cost of slightly increased
- 	  overhead in some places. If unsure say N here.
- 
-+source "kernel/Kconfig.MuQSS"
-+
- config PPC_DENORMALISATION
- 	bool "PowerPC denormalisation exception handling"
- 	depends on PPC_BOOK3S_64
-diff --git a/arch/powerpc/platforms/cell/spufs/sched.c b/arch/powerpc/platforms/cell/spufs/sched.c
-index f18d5067cd0f..fe489fc01c73 100644
---- a/arch/powerpc/platforms/cell/spufs/sched.c
-+++ b/arch/powerpc/platforms/cell/spufs/sched.c
-@@ -51,11 +51,6 @@ static struct task_struct *spusched_task;
- static struct timer_list spusched_timer;
- static struct timer_list spuloadavg_timer;
- 
--/*
-- * Priority of a normal, non-rt, non-niced'd process (aka nice level 0).
-- */
--#define NORMAL_PRIO		120
--
- /*
-  * Frequency of the spu scheduler tick.  By default we do one SPU scheduler
-  * tick for every 10 CPU scheduler ticks.
-diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
-index 8ef85139553f..7299015f6252 100644
---- a/arch/x86/Kconfig
-+++ b/arch/x86/Kconfig
-@@ -1034,6 +1034,22 @@ config NR_CPUS
- config SCHED_SMT
- 	def_bool y if SMP
- 
-+config SMT_NICE
-+	bool "SMT (Hyperthreading) aware nice priority and policy support"
-+	depends on SCHED_MUQSS && SCHED_SMT
-+	default y
-+	---help---
-+	  Enabling Hyperthreading on Intel CPUs decreases the effectiveness
-+	  of the use of 'nice' levels and different scheduling policies
-+	  (e.g. realtime) due to sharing of CPU power between hyperthreads.
-+	  SMT nice support makes each logical CPU aware of what is running on
-+	  its hyperthread siblings, maintaining appropriate distribution of
-+	  CPU according to nice levels and scheduling policies at the expense
-+	  of slightly increased overhead.
-+
-+	  If unsure say Y here.
-+
-+
- config SCHED_MC
- 	def_bool y
- 	prompt "Multi-core scheduler support"
-@@ -1064,6 +1080,8 @@ config SCHED_MC_PRIO
- 
- 	  If unsure say Y here.
- 
-+source "kernel/Kconfig.MuQSS"
-+
- config UP_LATE_INIT
-        def_bool y
-        depends on !SMP && X86_LOCAL_APIC
-diff --git a/fs/proc/base.c b/fs/proc/base.c
-index ebea9501afb8..51c9346a69fe 100644
---- a/fs/proc/base.c
-+++ b/fs/proc/base.c
-@@ -477,7 +477,7 @@ static int proc_pid_schedstat(struct seq_file *m, struct pid_namespace *ns,
- 		seq_puts(m, "0 0 0\n");
- 	else
- 		seq_printf(m, "%llu %llu %lu\n",
--		   (unsigned long long)task->se.sum_exec_runtime,
-+		   (unsigned long long)tsk_seruntime(task),
- 		   (unsigned long long)task->sched_info.run_delay,
- 		   task->sched_info.pcount);
- 
-diff --git a/include/linux/init_task.h b/include/linux/init_task.h
-index 2c620d7ac432..73417df5daa2 100644
---- a/include/linux/init_task.h
-+++ b/include/linux/init_task.h
-@@ -36,7 +36,11 @@ extern struct cred init_cred;
- #define INIT_PREV_CPUTIME(x)
- #endif
- 
-+#ifdef CONFIG_SCHED_MUQSS
-+#define INIT_TASK_COMM "MuQSS"
-+#else
- #define INIT_TASK_COMM "swapper"
-+#endif
- 
- /* Attach to the init_task data structure for proper alignment */
- #ifdef CONFIG_ARCH_TASK_STRUCT_ON_STACK
-diff --git a/include/linux/ioprio.h b/include/linux/ioprio.h
-index e9bfe6972aed..16ba1c7e5bde 100644
---- a/include/linux/ioprio.h
-+++ b/include/linux/ioprio.h
-@@ -53,6 +53,8 @@ enum {
-  */
- static inline int task_nice_ioprio(struct task_struct *task)
- {
-+	if (iso_task(task))
-+		return 0;
- 	return (task_nice(task) + 20) / 5;
- }
- 
-diff --git a/include/linux/sched.h b/include/linux/sched.h
-index 67a1d86981a9..0849781f069b 100644
---- a/include/linux/sched.h
-+++ b/include/linux/sched.h
-@@ -31,6 +31,9 @@
- #include <linux/task_io_accounting.h>
- #include <linux/posix-timers.h>
- #include <linux/rseq.h>
-+#ifdef CONFIG_SCHED_MUQSS
-+#include <linux/skip_list.h>
-+#endif
- 
- /* task_struct member predeclarations (sorted alphabetically): */
- struct audit_context;
-@@ -644,9 +647,11 @@ struct task_struct {
- 	unsigned int			flags;
- 	unsigned int			ptrace;
- 
-+#if defined(CONFIG_SMP) || defined(CONFIG_SCHED_MUQSS)
-+	int on_cpu;
-+#endif
- #ifdef CONFIG_SMP
- 	struct llist_node		wake_entry;
--	int				on_cpu;
- #ifdef CONFIG_THREAD_INFO_IN_TASK
- 	/* Current CPU: */
- 	unsigned int			cpu;
-@@ -671,10 +676,25 @@ struct task_struct {
- 	int				static_prio;
- 	int				normal_prio;
- 	unsigned int			rt_priority;
-+#ifdef CONFIG_SCHED_MUQSS
-+	int time_slice;
-+	u64 deadline;
-+	skiplist_node node; /* Skip list node */
-+	u64 last_ran;
-+	u64 sched_time; /* sched_clock time spent running */
-+#ifdef CONFIG_SMT_NICE
-+	int smt_bias; /* Policy/nice level bias across smt siblings */
-+#endif
-+#ifdef CONFIG_HOTPLUG_CPU
-+	bool zerobound; /* Bound to CPU0 for hotplug */
-+#endif
-+	unsigned long rt_timeout;
-+#else /* CONFIG_SCHED_MUQSS */
- 
- 	const struct sched_class	*sched_class;
- 	struct sched_entity		se;
- 	struct sched_rt_entity		rt;
-+#endif
- #ifdef CONFIG_CGROUP_SCHED
- 	struct task_group		*sched_task_group;
- #endif
-@@ -839,6 +859,10 @@ struct task_struct {
- #ifdef CONFIG_ARCH_HAS_SCALED_CPUTIME
- 	u64				utimescaled;
- 	u64				stimescaled;
-+#endif
-+#ifdef CONFIG_SCHED_MUQSS
-+	/* Unbanked cpu time */
-+	unsigned long utime_ns, stime_ns;
- #endif
- 	u64				gtime;
- 	struct prev_cputime		prev_cputime;
-@@ -1283,6 +1307,40 @@ struct task_struct {
- 	 */
- };
- 
-+#ifdef CONFIG_SCHED_MUQSS
-+#define tsk_seruntime(t)		((t)->sched_time)
-+#define tsk_rttimeout(t)		((t)->rt_timeout)
-+
-+static inline void tsk_cpus_current(struct task_struct *p)
-+{
-+}
-+
-+void print_scheduler_version(void);
-+
-+static inline bool iso_task(struct task_struct *p)
-+{
-+	return (p->policy == SCHED_ISO);
-+}
-+#else /* CFS */
-+#define tsk_seruntime(t)	((t)->se.sum_exec_runtime)
-+#define tsk_rttimeout(t)	((t)->rt.timeout)
-+
-+static inline void tsk_cpus_current(struct task_struct *p)
-+{
-+	p->nr_cpus_allowed = current->nr_cpus_allowed;
-+}
-+
-+static inline void print_scheduler_version(void)
-+{
-+	printk(KERN_INFO "CFS CPU scheduler.\n");
-+}
-+
-+static inline bool iso_task(struct task_struct *p)
-+{
-+	return false;
-+}
-+#endif /* CONFIG_SCHED_MUQSS */
-+
- static inline struct pid *task_pid(struct task_struct *task)
- {
- 	return task->thread_pid;
-diff --git a/include/linux/sched/deadline.h b/include/linux/sched/deadline.h
-index 1aff00b65f3c..73d6319a856a 100644
---- a/include/linux/sched/deadline.h
-+++ b/include/linux/sched/deadline.h
-@@ -28,7 +28,16 @@ static inline bool dl_time_before(u64 a, u64 b)
- #ifdef CONFIG_SMP
- 
- struct root_domain;
-+#ifdef CONFIG_SCHED_MUQSS
-+static inline void dl_clear_root_domain(struct root_domain *rd)
-+{
-+}
-+static inline void dl_add_task_root_domain(struct task_struct *p)
-+{
-+}
-+#else /* CONFIG_SCHED_MUQSS */
- extern void dl_add_task_root_domain(struct task_struct *p);
- extern void dl_clear_root_domain(struct root_domain *rd);
-+#endif /* CONFIG_SCHED_MUQSS */
- 
- #endif /* CONFIG_SMP */
-diff --git a/include/linux/sched/nohz.h b/include/linux/sched/nohz.h
-index 1abe91ff6e4a..20ba383562b0 100644
---- a/include/linux/sched/nohz.h
-+++ b/include/linux/sched/nohz.h
-@@ -13,7 +13,7 @@ extern int get_nohz_timer_target(void);
- static inline void nohz_balance_enter_idle(int cpu) { }
- #endif
- 
--#ifdef CONFIG_NO_HZ_COMMON
-+#if defined(CONFIG_NO_HZ_COMMON) && !defined(CONFIG_SCHED_MUQSS)
- void calc_load_nohz_start(void);
- void calc_load_nohz_stop(void);
- #else
-diff --git a/include/linux/sched/prio.h b/include/linux/sched/prio.h
-index 7d64feafc408..43c9d9e50c09 100644
---- a/include/linux/sched/prio.h
-+++ b/include/linux/sched/prio.h
-@@ -20,8 +20,20 @@
-  */
- 
- #define MAX_USER_RT_PRIO	100
-+
-+#ifdef CONFIG_SCHED_MUQSS
-+/* Note different MAX_RT_PRIO */
-+#define MAX_RT_PRIO		(MAX_USER_RT_PRIO + 1)
-+
-+#define ISO_PRIO		(MAX_RT_PRIO)
-+#define NORMAL_PRIO		(MAX_RT_PRIO + 1)
-+#define IDLE_PRIO		(MAX_RT_PRIO + 2)
-+#define PRIO_LIMIT		((IDLE_PRIO) + 1)
-+#else /* CONFIG_SCHED_MUQSS */
- #define MAX_RT_PRIO		MAX_USER_RT_PRIO
- 
-+#endif /* CONFIG_SCHED_MUQSS */
-+
- #define MAX_PRIO		(MAX_RT_PRIO + NICE_WIDTH)
- #define DEFAULT_PRIO		(MAX_RT_PRIO + NICE_WIDTH / 2)
- 
-diff --git a/include/linux/sched/rt.h b/include/linux/sched/rt.h
-index e5af028c08b4..010b2244e0b6 100644
---- a/include/linux/sched/rt.h
-+++ b/include/linux/sched/rt.h
-@@ -24,8 +24,10 @@ static inline bool task_is_realtime(struct task_struct *tsk)
- 
- 	if (policy == SCHED_FIFO || policy == SCHED_RR)
- 		return true;
-+#ifndef CONFIG_SCHED_MUQSS
- 	if (policy == SCHED_DEADLINE)
- 		return true;
-+#endif
- 	return false;
- }
- 
-diff --git a/include/linux/sched/task.h b/include/linux/sched/task.h
-index 4b1c3b664f51..a9671b48799c 100644
---- a/include/linux/sched/task.h
-+++ b/include/linux/sched/task.h
-@@ -99,7 +99,7 @@ extern long kernel_wait4(pid_t, int __user *, int, struct rusage *);
- extern void free_task(struct task_struct *tsk);
- 
- /* sched_exec is called by processes performing an exec */
--#ifdef CONFIG_SMP
-+#if defined(CONFIG_SMP) && !defined(CONFIG_SCHED_MUQSS)
- extern void sched_exec(void);
- #else
- #define sched_exec()   {}
-diff --git a/include/linux/skip_list.h b/include/linux/skip_list.h
-new file mode 100644
-index 000000000000..d4be84ba273b
---- /dev/null
-+++ b/include/linux/skip_list.h
-@@ -0,0 +1,33 @@
-+#ifndef _LINUX_SKIP_LISTS_H
-+#define _LINUX_SKIP_LISTS_H
-+typedef u64 keyType;
-+typedef void *valueType;
-+
-+typedef struct nodeStructure skiplist_node;
-+
-+struct nodeStructure {
-+	int level;	/* Levels in this structure */
-+	keyType key;
-+	valueType value;
-+	skiplist_node *next[8];
-+	skiplist_node *prev[8];
-+};
-+
-+typedef struct listStructure {
-+	int entries;
-+	int level;	/* Maximum level of the list
-+			(1 more than the number of levels in the list) */
-+	skiplist_node *header; /* pointer to header */
-+} skiplist;
-+
-+void skiplist_init(skiplist_node *slnode);
-+skiplist *new_skiplist(skiplist_node *slnode);
-+void free_skiplist(skiplist *l);
-+void skiplist_node_init(skiplist_node *node);
-+void skiplist_insert(skiplist *l, skiplist_node *node, keyType key, valueType value, unsigned int randseed);
-+void skiplist_delete(skiplist *l, skiplist_node *node);
-+
-+static inline bool skiplist_node_empty(skiplist_node *node) {
-+	return (!node->next[0]);
-+}
-+#endif /* _LINUX_SKIP_LISTS_H */
-diff --git a/include/uapi/linux/sched.h b/include/uapi/linux/sched.h
-index 25b4fa00bad1..c2503cd28025 100644
---- a/include/uapi/linux/sched.h
-+++ b/include/uapi/linux/sched.h
-@@ -84,9 +84,16 @@ struct clone_args {
- #define SCHED_FIFO		1
- #define SCHED_RR		2
- #define SCHED_BATCH		3
--/* SCHED_ISO: reserved but not implemented yet */
-+/* SCHED_ISO: Implemented on MuQSS only */
- #define SCHED_IDLE		5
-+#ifdef CONFIG_SCHED_MUQSS
-+#define SCHED_ISO		4
-+#define SCHED_IDLEPRIO		SCHED_IDLE
-+#define SCHED_MAX		(SCHED_IDLEPRIO)
-+#define SCHED_RANGE(policy)	((policy) <= SCHED_MAX)
-+#else /* CONFIG_SCHED_MUQSS */
- #define SCHED_DEADLINE		6
-+#endif /* CONFIG_SCHED_MUQSS */
- 
- /* Can be ORed in to make sure the process is reverted back to SCHED_NORMAL on fork */
- #define SCHED_RESET_ON_FORK     0x40000000
-diff --git a/init/Kconfig b/init/Kconfig
-index b4daad2bac23..da90d33ba4b3 100644
---- a/init/Kconfig
-+++ b/init/Kconfig
-@@ -73,6 +73,18 @@ config THREAD_INFO_IN_TASK
- 
- menu "General setup"
- 
-+config SCHED_MUQSS
-+	bool "MuQSS cpu scheduler"
-+	select HIGH_RES_TIMERS
-+	---help---
-+	  The Multiple Queue Skiplist Scheduler for excellent interactivity and
-+	  responsiveness on the desktop and highly scalable deterministic
-+	  low latency on any hardware.
-+
-+          Say Y here.
-+	default y
-+
-+
- config BROKEN
- 	bool
- 
-@@ -802,6 +814,7 @@ config NUMA_BALANCING
- 	depends on ARCH_SUPPORTS_NUMA_BALANCING
- 	depends on !ARCH_WANT_NUMA_VARIABLE_LOCALITY
- 	depends on SMP && NUMA && MIGRATION
-+	depends on !SCHED_MUQSS
- 	help
- 	  This option adds support for automatic NUMA aware memory/task placement.
- 	  The mechanism is quite primitive and is based on migrating memory when
-@@ -901,9 +914,13 @@ menuconfig CGROUP_SCHED
- 	help
- 	  This feature lets CPU scheduler recognize task groups and control CPU
- 	  bandwidth allocation to such task groups. It uses cgroups to group
--	  tasks.
-+	  tasks. In combination with MuQSS this is purely a STUB to create the
-+	  files associated with the CPU controller cgroup but most of the
-+	  controls do nothing. This is useful for working in environments and
-+	  with applications that will only work if this control group is
-+	  present.
- 
--if CGROUP_SCHED
-+if CGROUP_SCHED && !SCHED_MUQSS
- config FAIR_GROUP_SCHED
- 	bool "Group scheduling for SCHED_OTHER"
- 	depends on CGROUP_SCHED
-@@ -1032,6 +1049,7 @@ config CGROUP_DEVICE
- 
- config CGROUP_CPUACCT
- 	bool "Simple CPU accounting controller"
-+	depends on !SCHED_MUQSS
- 	help
- 	  Provides a simple controller for monitoring the
- 	  total CPU consumed by the tasks in a cgroup.
-@@ -1150,6 +1168,7 @@ config CHECKPOINT_RESTORE
- 
- config SCHED_AUTOGROUP
- 	bool "Automatic process group scheduling"
-+	depends on !SCHED_MUQSS
- 	select CGROUPS
- 	select CGROUP_SCHED
- 	select FAIR_GROUP_SCHED
-diff --git a/init/init_task.c b/init/init_task.c
-index 9e5cbe5eab7b..5c2bcbf25add 100644
---- a/init/init_task.c
-+++ b/init/init_task.c
-@@ -66,9 +66,17 @@ struct task_struct init_task
- 	.stack		= init_stack,
- 	.usage		= REFCOUNT_INIT(2),
- 	.flags		= PF_KTHREAD,
-+#ifdef CONFIG_SCHED_MUQSS
-+	.prio		= NORMAL_PRIO,
-+	.static_prio	= MAX_PRIO - 20,
-+	.normal_prio	= NORMAL_PRIO,
-+	.deadline	= 0,
-+	.time_slice	= 1000000,
-+#else
- 	.prio		= MAX_PRIO - 20,
- 	.static_prio	= MAX_PRIO - 20,
- 	.normal_prio	= MAX_PRIO - 20,
-+#endif
- 	.policy		= SCHED_NORMAL,
- 	.cpus_ptr	= &init_task.cpus_mask,
- 	.cpus_mask	= CPU_MASK_ALL,
-@@ -78,6 +86,7 @@ struct task_struct init_task
- 	.restart_block	= {
- 		.fn = do_no_restart_syscall,
- 	},
-+#ifndef CONFIG_SCHED_MUQSS
- 	.se		= {
- 		.group_node 	= LIST_HEAD_INIT(init_task.se.group_node),
- 	},
-@@ -85,6 +94,7 @@ struct task_struct init_task
- 		.run_list	= LIST_HEAD_INIT(init_task.rt.run_list),
- 		.time_slice	= RR_TIMESLICE,
- 	},
-+#endif
- 	.tasks		= LIST_HEAD_INIT(init_task.tasks),
- #ifdef CONFIG_SMP
- 	.pushable_tasks	= PLIST_NODE_INIT(init_task.pushable_tasks, MAX_PRIO),
-diff --git a/init/main.c b/init/main.c
-index 91f6ebb30ef0..22792032de64 100644
---- a/init/main.c
-+++ b/init/main.c
-@@ -1124,6 +1124,8 @@ static int __ref kernel_init(void *unused)
- 
- 	rcu_end_inkernel_boot();
- 
-+	print_scheduler_version();
-+
- 	if (ramdisk_execute_command) {
- 		ret = run_init_process(ramdisk_execute_command);
- 		if (!ret)
-diff --git a/kernel/Kconfig.MuQSS b/kernel/Kconfig.MuQSS
-new file mode 100644
-index 000000000000..a6a58781ef91
---- /dev/null
-+++ b/kernel/Kconfig.MuQSS
-@@ -0,0 +1,105 @@
-+choice
-+	prompt "CPU scheduler runqueue sharing"
-+	default RQ_MC if SCHED_MUQSS
-+	default RQ_NONE
-+
-+config RQ_NONE
-+	bool "No sharing"
-+	help
-+	  This is the default behaviour where the CPU scheduler has one runqueue
-+	  per CPU, whether it is a physical or logical CPU (hyperthread).
-+
-+	  This can still be enabled runtime with the boot parameter
-+	  rqshare=none
-+
-+	  If unsure, say N.
-+
-+config RQ_SMT
-+	bool "SMT (hyperthread) siblings"
-+	depends on SCHED_SMT && SCHED_MUQSS
-+
-+	help
-+	  With this option enabled, the CPU scheduler will have one runqueue
-+	  shared by SMT (hyperthread) siblings. As these logical cores share
-+	  one physical core, sharing the runqueue resource can lead to decreased
-+	  overhead, lower latency and higher throughput.
-+
-+	  This can still be enabled runtime with the boot parameter
-+	  rqshare=smt
-+
-+	  If unsure, say N.
-+
-+config RQ_MC
-+	bool "Multicore siblings"
-+	depends on SCHED_MC && SCHED_MUQSS
-+	help
-+	  With this option enabled, the CPU scheduler will have one runqueue
-+	  shared by multicore siblings in addition to any SMT siblings.
-+	  As these physical cores share caches, sharing the runqueue resource
-+	  will lead to lower latency, but its effects on overhead and throughput
-+	  are less predictable. As a general rule, 6 or fewer cores will likely
-+	  benefit from this, while larger CPUs will only derive a latency
-+	  benefit. If your workloads are primarily single threaded, this will
-+	  possibly worsen throughput. If you are only concerned about latency
-+	  then enable this regardless of how many cores you have.
-+
-+	  This can still be enabled runtime with the boot parameter
-+	  rqshare=mc
-+
-+	  If unsure, say Y.
-+
-+config RQ_MC_LLC
-+	bool "Multicore siblings (LLC)"
-+	depends on SCHED_MC && SCHED_MUQSS
-+	help
-+	  With this option enabled, the CPU scheduler will behave similarly as
-+	  with "Multicore siblings".
-+	  This option takes LLC cache into account when scheduling tasks.
-+	  Option may benefit CPUs with multiple LLC caches, such as Ryzen
-+	  and Xeon CPUs.
-+
-+	  This can still be enabled runtime with the boot parameter
-+	  rqshare=llc
-+
-+	  If unsure, say N.
-+
-+config RQ_SMP
-+	bool "Symmetric Multi-Processing"
-+	depends on SMP && SCHED_MUQSS
-+	help
-+	  With this option enabled, the CPU scheduler will have one runqueue
-+	  shared by all physical CPUs unless they are on separate NUMA nodes.
-+	  As physical CPUs usually do not share resources, sharing the runqueue
-+	  will normally worsen throughput but improve latency. If you only
-+	  care about latency enable this.
-+
-+	  This can still be enabled runtime with the boot parameter
-+	  rqshare=smp
-+
-+	  If unsure, say N.
-+
-+config RQ_ALL
-+	bool "NUMA"
-+	depends on SMP && SCHED_MUQSS
-+	help
-+	  With this option enabled, the CPU scheduler will have one runqueue
-+	  regardless of the architecture configuration, including across NUMA
-+	  nodes. This can substantially decrease throughput in NUMA
-+	  configurations, but light NUMA designs will not be dramatically
-+	  affected. This option should only be chosen if latency is the prime
-+	  concern.
-+
-+	  This can still be enabled runtime with the boot parameter
-+	  rqshare=all
-+
-+	  If unsure, say N.
-+endchoice
-+
-+config SHARERQ
-+	int
-+	default 0 if RQ_NONE
-+	default 1 if RQ_SMT
-+	default 2 if RQ_MC
-+	default 3 if RQ_MC_LLC
-+	default 4 if RQ_SMP
-+	default 5 if RQ_ALL
-diff --git a/kernel/Makefile b/kernel/Makefile
-index daad787fb795..9bb44fc4ef5b 100644
---- a/kernel/Makefile
-+++ b/kernel/Makefile
-@@ -10,7 +10,7 @@ obj-y     = fork.o exec_domain.o panic.o \
- 	    extable.o params.o \
- 	    kthread.o sys_ni.o nsproxy.o \
- 	    notifier.o ksysfs.o cred.o reboot.o \
--	    async.o range.o smpboot.o ucount.o
-+	    async.o range.o smpboot.o ucount.o skip_list.o
- 
- obj-$(CONFIG_MODULES) += kmod.o
- obj-$(CONFIG_MULTIUSER) += groups.o
-diff --git a/kernel/delayacct.c b/kernel/delayacct.c
-index 27725754ac99..769d773c7182 100644
---- a/kernel/delayacct.c
-+++ b/kernel/delayacct.c
-@@ -106,7 +106,7 @@ int __delayacct_add_tsk(struct taskstats *d, struct task_struct *tsk)
- 	 */
- 	t1 = tsk->sched_info.pcount;
- 	t2 = tsk->sched_info.run_delay;
--	t3 = tsk->se.sum_exec_runtime;
-+	t3 = tsk_seruntime(tsk);
- 
- 	d->cpu_count += t1;
- 
-diff --git a/kernel/exit.c b/kernel/exit.c
-index a46a50d67002..58043176b285 100644
---- a/kernel/exit.c
-+++ b/kernel/exit.c
-@@ -131,7 +131,7 @@ static void __exit_signal(struct task_struct *tsk)
- 			sig->curr_target = next_thread(tsk);
- 	}
- 
--	add_device_randomness((const void*) &tsk->se.sum_exec_runtime,
-+	add_device_randomness((const void*) &tsk_seruntime(tsk),
- 			      sizeof(unsigned long long));
- 
- 	/*
-@@ -152,7 +152,7 @@ static void __exit_signal(struct task_struct *tsk)
- 	sig->inblock += task_io_get_inblock(tsk);
- 	sig->oublock += task_io_get_oublock(tsk);
- 	task_io_accounting_add(&sig->ioac, &tsk->ioac);
--	sig->sum_sched_runtime += tsk->se.sum_exec_runtime;
-+	sig->sum_sched_runtime += tsk_seruntime(tsk);
- 	sig->nr_threads--;
- 	__unhash_process(tsk, group_dead);
- 	write_sequnlock(&sig->stats_lock);
-diff --git a/kernel/kthread.c b/kernel/kthread.c
-index b262f47046ca..9797ad652268 100644
---- a/kernel/kthread.c
-+++ b/kernel/kthread.c
-@@ -433,6 +433,34 @@ void kthread_bind(struct task_struct *p, unsigned int cpu)
- }
- EXPORT_SYMBOL(kthread_bind);
- 
-+#if defined(CONFIG_SCHED_MUQSS) && defined(CONFIG_SMP)
-+extern void __do_set_cpus_allowed(struct task_struct *p, const struct cpumask *new_mask);
-+
-+/*
-+ * new_kthread_bind is a special variant of __kthread_bind_mask.
-+ * For new threads to work on muqss we want to call do_set_cpus_allowed
-+ * without the task_cpu being set and the task rescheduled until they're
-+ * rescheduled on their own so we call __do_set_cpus_allowed directly which
-+ * only changes the cpumask. This is particularly important for smpboot threads
-+ * to work.
-+ */
-+static void new_kthread_bind(struct task_struct *p, unsigned int cpu)
-+{
-+	unsigned long flags;
-+
-+	if (WARN_ON(!wait_task_inactive(p, TASK_UNINTERRUPTIBLE)))
-+		return;
-+
-+	/* It's safe because the task is inactive. */
-+	raw_spin_lock_irqsave(&p->pi_lock, flags);
-+	__do_set_cpus_allowed(p, cpumask_of(cpu));
-+	p->flags |= PF_NO_SETAFFINITY;
-+	raw_spin_unlock_irqrestore(&p->pi_lock, flags);
-+}
-+#else
-+#define new_kthread_bind(p, cpu) kthread_bind(p, cpu)
-+#endif
-+
- /**
-  * kthread_create_on_cpu - Create a cpu bound kthread
-  * @threadfn: the function to run until signal_pending(current).
-@@ -454,7 +482,7 @@ struct task_struct *kthread_create_on_cpu(int (*threadfn)(void *data),
- 				   cpu);
- 	if (IS_ERR(p))
- 		return p;
--	kthread_bind(p, cpu);
-+	new_kthread_bind(p, cpu);
- 	/* CPU hotplug need to bind once again when unparking the thread. */
- 	set_bit(KTHREAD_IS_PER_CPU, &to_kthread(p)->flags);
- 	to_kthread(p)->cpu = cpu;
-diff --git a/kernel/livepatch/transition.c b/kernel/livepatch/transition.c
-index cdf318d86dd6..304c0c8c2bea 100644
---- a/kernel/livepatch/transition.c
-+++ b/kernel/livepatch/transition.c
-@@ -282,7 +282,7 @@ static bool klp_try_switch_task(struct task_struct *task)
- {
- 	static char err_buf[STACK_ERR_BUF_SIZE];
- 	struct rq *rq;
--	struct rq_flags flags;
-+	struct rq_flags rf;
- 	int ret;
- 	bool success = false;
- 
-@@ -304,7 +304,7 @@ static bool klp_try_switch_task(struct task_struct *task)
- 	 * functions.  If all goes well, switch the task to the target patch
- 	 * state.
- 	 */
--	rq = task_rq_lock(task, &flags);
-+	rq = task_rq_lock(task, &rf);
- 
- 	if (task_running(rq, task) && task != current) {
- 		snprintf(err_buf, STACK_ERR_BUF_SIZE,
-@@ -323,7 +323,7 @@ static bool klp_try_switch_task(struct task_struct *task)
- 	task->patch_state = klp_target_state;
- 
- done:
--	task_rq_unlock(rq, task, &flags);
-+	task_rq_unlock(rq, task, &rf);
- 
- 	/*
- 	 * Due to console deadlock issues, pr_debug() can't be used while
-diff --git a/kernel/sched/Makefile b/kernel/sched/Makefile
-index 21fb5a5662b5..a04ffebc6b7a 100644
---- a/kernel/sched/Makefile
-+++ b/kernel/sched/Makefile
-@@ -16,15 +16,23 @@ ifneq ($(CONFIG_SCHED_OMIT_FRAME_POINTER),y)
- CFLAGS_core.o := $(PROFILING) -fno-omit-frame-pointer
- endif
- 
-+ifdef CONFIG_SCHED_MUQSS
-+obj-y += MuQSS.o clock.o cputime.o
-+obj-y += idle.o
-+obj-y += wait.o wait_bit.o swait.o completion.o
-+
-+obj-$(CONFIG_SMP) += topology.o
-+else
- obj-y += core.o loadavg.o clock.o cputime.o
- obj-y += idle.o fair.o rt.o deadline.o
- obj-y += wait.o wait_bit.o swait.o completion.o
- 
- obj-$(CONFIG_SMP) += cpupri.o cpudeadline.o topology.o stop_task.o pelt.o
- obj-$(CONFIG_SCHED_AUTOGROUP) += autogroup.o
--obj-$(CONFIG_SCHEDSTATS) += stats.o
- obj-$(CONFIG_SCHED_DEBUG) += debug.o
- obj-$(CONFIG_CGROUP_CPUACCT) += cpuacct.o
-+endif
-+obj-$(CONFIG_SCHEDSTATS) += stats.o
- obj-$(CONFIG_CPU_FREQ) += cpufreq.o
- obj-$(CONFIG_CPU_FREQ_GOV_SCHEDUTIL) += cpufreq_schedutil.o
- obj-$(CONFIG_MEMBARRIER) += membarrier.o
-diff --git a/kernel/sched/MuQSS.c b/kernel/sched/MuQSS.c
-new file mode 100644
-index 000000000000..fafb5a790cf1
---- /dev/null
-+++ b/kernel/sched/MuQSS.c
-@@ -0,0 +1,7606 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ *  kernel/sched/MuQSS.c, was kernel/sched.c
-+ *
-+ *  Kernel scheduler and related syscalls
-+ *
-+ *  Copyright (C) 1991-2002  Linus Torvalds
-+ *
-+ *  1996-12-23  Modified by Dave Grothe to fix bugs in semaphores and
-+ *		make semaphores SMP safe
-+ *  1998-11-19	Implemented schedule_timeout() and related stuff
-+ *		by Andrea Arcangeli
-+ *  2002-01-04	New ultra-scalable O(1) scheduler by Ingo Molnar:
-+ *		hybrid priority-list and round-robin design with
-+ *		an array-switch method of distributing timeslices
-+ *		and per-CPU runqueues.  Cleanups and useful suggestions
-+ *		by Davide Libenzi, preemptible kernel bits by Robert Love.
-+ *  2003-09-03	Interactivity tuning by Con Kolivas.
-+ *  2004-04-02	Scheduler domains code by Nick Piggin
-+ *  2007-04-15  Work begun on replacing all interactivity tuning with a
-+ *              fair scheduling design by Con Kolivas.
-+ *  2007-05-05  Load balancing (smp-nice) and other improvements
-+ *              by Peter Williams
-+ *  2007-05-06  Interactivity improvements to CFS by Mike Galbraith
-+ *  2007-07-01  Group scheduling enhancements by Srivatsa Vaddagiri
-+ *  2007-11-29  RT balancing improvements by Steven Rostedt, Gregory Haskins,
-+ *              Thomas Gleixner, Mike Kravetz
-+ *  2009-08-13	Brainfuck deadline scheduling policy by Con Kolivas deletes
-+ *              a whole lot of those previous things.
-+ *  2016-10-01  Multiple Queue Skiplist Scheduler scalable evolution of BFS
-+ * 		scheduler by Con Kolivas.
-+ *  2019-08-31  LLC bits by Eduards Bezverhijs
-+ */
-+
-+#include <linux/sched/isolation.h>
-+#include <linux/sched/loadavg.h>
-+
-+#include <linux/binfmts.h>
-+#include <linux/blkdev.h>
-+#include <linux/compat.h>
-+#include <linux/context_tracking.h>
-+#include <linux/cpuset.h>
-+#include <linux/delayacct.h>
-+#include <linux/init_task.h>
-+#include <linux/kcov.h>
-+#include <linux/kprobes.h>
-+#include <linux/mmu_context.h>
-+#include <linux/module.h>
-+#include <linux/nmi.h>
-+#include <linux/prefetch.h>
-+#include <linux/profile.h>
-+#include <linux/rcupdate_wait.h>
-+#include <linux/sched.h>
-+#include <linux/security.h>
-+#include <linux/skip_list.h>
-+#include <linux/syscalls.h>
-+#include <linux/tick.h>
-+#include <linux/wait_bit.h>
-+
-+#include <asm/irq_regs.h>
-+#include <asm/switch_to.h>
-+#include <asm/tlb.h>
-+
-+#include "../workqueue_internal.h"
-+#include "../smpboot.h"
-+
-+#define CREATE_TRACE_POINTS
-+#include <trace/events/sched.h>
-+
-+#include "MuQSS.h"
-+
-+#define rt_prio(prio)		unlikely((prio) < MAX_RT_PRIO)
-+#define rt_task(p)		rt_prio((p)->prio)
-+#define batch_task(p)		(unlikely((p)->policy == SCHED_BATCH))
-+#define is_rt_policy(policy)	((policy) == SCHED_FIFO || \
-+					(policy) == SCHED_RR)
-+#define has_rt_policy(p)	unlikely(is_rt_policy((p)->policy))
-+
-+#define is_idle_policy(policy)	((policy) == SCHED_IDLEPRIO)
-+#define idleprio_task(p)	unlikely(is_idle_policy((p)->policy))
-+#define task_running_idle(p)	unlikely((p)->prio == IDLE_PRIO)
-+
-+#define is_iso_policy(policy)	((policy) == SCHED_ISO)
-+#define iso_task(p)		unlikely(is_iso_policy((p)->policy))
-+#define task_running_iso(p)	unlikely((p)->prio == ISO_PRIO)
-+
-+#define rq_idle(rq)		((rq)->rq_prio == PRIO_LIMIT)
-+
-+#define ISO_PERIOD		(5 * HZ)
-+
-+#define STOP_PRIO		(MAX_RT_PRIO - 1)
-+
-+/*
-+ * Some helpers for converting to/from various scales. Use shifts to get
-+ * approximate multiples of ten for less overhead.
-+ */
-+#define APPROX_NS_PS		(1073741824) /* Approximate ns per second */
-+#define JIFFIES_TO_NS(TIME)	((TIME) * (APPROX_NS_PS / HZ))
-+#define JIFFY_NS		(APPROX_NS_PS / HZ)
-+#define JIFFY_US		(1048576 / HZ)
-+#define NS_TO_JIFFIES(TIME)	((TIME) / JIFFY_NS)
-+#define HALF_JIFFY_NS		(APPROX_NS_PS / HZ / 2)
-+#define HALF_JIFFY_US		(1048576 / HZ / 2)
-+#define MS_TO_NS(TIME)		((TIME) << 20)
-+#define MS_TO_US(TIME)		((TIME) << 10)
-+#define NS_TO_MS(TIME)		((TIME) >> 20)
-+#define NS_TO_US(TIME)		((TIME) >> 10)
-+#define US_TO_NS(TIME)		((TIME) << 10)
-+#define TICK_APPROX_NS		((APPROX_NS_PS+HZ/2)/HZ)
-+
-+#define RESCHED_US	(100) /* Reschedule if less than this many μs left */
-+
-+void print_scheduler_version(void)
-+{
-+	printk(KERN_INFO "MuQSS CPU scheduler v0.196 by Con Kolivas.\n");
-+}
-+
-+/* Define RQ share levels */
-+#define RQSHARE_NONE 0
-+#define RQSHARE_SMT 1
-+#define RQSHARE_MC 2
-+#define RQSHARE_MC_LLC 3
-+#define RQSHARE_SMP 4
-+#define RQSHARE_ALL 5
-+
-+/* Define locality levels */
-+#define LOCALITY_SAME 0
-+#define LOCALITY_SMT 1
-+#define LOCALITY_MC_LLC 2
-+#define LOCALITY_MC 3
-+#define LOCALITY_SMP 4
-+#define LOCALITY_DISTANT 5
-+
-+/*
-+ * This determines what level of runqueue sharing will be done and is
-+ * configurable at boot time with the bootparam rqshare =
-+ */
-+static int rqshare __read_mostly = CONFIG_SHARERQ; /* Default RQSHARE_MC */
-+
-+static int __init set_rqshare(char *str)
-+{
-+	if (!strncmp(str, "none", 4)) {
-+		rqshare = RQSHARE_NONE;
-+		return 0;
-+	}
-+	if (!strncmp(str, "smt", 3)) {
-+		rqshare = RQSHARE_SMT;
-+		return 0;
-+	}
-+	if (!strncmp(str, "mc", 2)) {
-+		rqshare = RQSHARE_MC;
-+		return 0;
-+	}
-+	if (!strncmp(str, "llc", 3)) {
-+		rqshare = RQSHARE_MC_LLC;
-+		return 0;
-+	}
-+	if (!strncmp(str, "smp", 3)) {
-+		rqshare = RQSHARE_SMP;
-+		return 0;
-+	}
-+	if (!strncmp(str, "all", 3)) {
-+		rqshare = RQSHARE_ALL;
-+		return 0;
-+	}
-+	return 1;
-+}
-+__setup("rqshare=", set_rqshare);
-+
-+/*
-+ * This is the time all tasks within the same priority round robin.
-+ * Value is in ms and set to a minimum of 6ms.
-+ * Tunable via /proc interface.
-+ */
-+int rr_interval __read_mostly = 6;
-+
-+/*
-+ * Tunable to choose whether to prioritise latency or throughput, simple
-+ * binary yes or no
-+ */
-+int sched_interactive __read_mostly = 1;
-+
-+/*
-+ * sched_iso_cpu - sysctl which determines the cpu percentage SCHED_ISO tasks
-+ * are allowed to run five seconds as real time tasks. This is the total over
-+ * all online cpus.
-+ */
-+int sched_iso_cpu __read_mostly = 70;
-+
-+/*
-+ * sched_yield_type - Choose what sort of yield sched_yield will perform.
-+ * 0: No yield.
-+ * 1: Yield only to better priority/deadline tasks. (default)
-+ * 2: Expire timeslice and recalculate deadline.
-+ */
-+int sched_yield_type __read_mostly = 1;
-+
-+/*
-+ * The relative length of deadline for each priority(nice) level.
-+ */
-+static int prio_ratios[NICE_WIDTH] __read_mostly;
-+
-+
-+/*
-+ * The quota handed out to tasks of all priority levels when refilling their
-+ * time_slice.
-+ */
-+static inline int timeslice(void)
-+{
-+	return MS_TO_US(rr_interval);
-+}
-+
-+DEFINE_PER_CPU_SHARED_ALIGNED(struct rq, runqueues);
-+
-+#ifdef CONFIG_SMP
-+/*
-+ * Total number of runqueues. Equals number of CPUs when there is no runqueue
-+ * sharing but is usually less with SMT/MC sharing of runqueues.
-+ */
-+static int total_runqueues __read_mostly = 1;
-+
-+static cpumask_t cpu_idle_map ____cacheline_aligned_in_smp;
-+
-+struct rq *cpu_rq(int cpu)
-+{
-+	return &per_cpu(runqueues, (cpu));
-+}
-+#define cpu_curr(cpu)		(cpu_rq(cpu)->curr)
-+
-+/*
-+ * For asym packing, by default the lower numbered cpu has higher priority.
-+ */
-+int __weak arch_asym_cpu_priority(int cpu)
-+{
-+	return -cpu;
-+}
-+
-+int __weak arch_sd_sibling_asym_packing(void)
-+{
-+       return 0*SD_ASYM_PACKING;
-+}
-+
-+#ifdef CONFIG_SCHED_SMT
-+DEFINE_STATIC_KEY_FALSE(sched_smt_present);
-+EXPORT_SYMBOL_GPL(sched_smt_present);
-+#endif
-+
-+#else
-+struct rq *uprq;
-+#endif /* CONFIG_SMP */
-+
-+#include "stats.h"
-+
-+/*
-+ * All common locking functions performed on rq->lock. rq->clock is local to
-+ * the CPU accessing it so it can be modified just with interrupts disabled
-+ * when we're not updating niffies.
-+ * Looking up task_rq must be done under rq->lock to be safe.
-+ */
-+
-+/*
-+ * RQ-clock updating methods:
-+ */
-+
-+#ifdef HAVE_SCHED_AVG_IRQ
-+static void update_irq_load_avg(struct rq *rq, long delta);
-+#else
-+static inline void update_irq_load_avg(struct rq *rq, long delta) {}
-+#endif
-+
-+static void update_rq_clock_task(struct rq *rq, s64 delta)
-+{
-+/*
-+ * In theory, the compile should just see 0 here, and optimize out the call
-+ * to sched_rt_avg_update. But I don't trust it...
-+ */
-+	s64 __maybe_unused steal = 0, irq_delta = 0;
-+#ifdef CONFIG_IRQ_TIME_ACCOUNTING
-+	irq_delta = irq_time_read(cpu_of(rq)) - rq->prev_irq_time;
-+
-+	/*
-+	 * Since irq_time is only updated on {soft,}irq_exit, we might run into
-+	 * this case when a previous update_rq_clock() happened inside a
-+	 * {soft,}irq region.
-+	 *
-+	 * When this happens, we stop ->clock_task and only update the
-+	 * prev_irq_time stamp to account for the part that fit, so that a next
-+	 * update will consume the rest. This ensures ->clock_task is
-+	 * monotonic.
-+	 *
-+	 * It does however cause some slight miss-attribution of {soft,}irq
-+	 * time, a more accurate solution would be to update the irq_time using
-+	 * the current rq->clock timestamp, except that would require using
-+	 * atomic ops.
-+	 */
-+	if (irq_delta > delta)
-+		irq_delta = delta;
-+
-+	rq->prev_irq_time += irq_delta;
-+	delta -= irq_delta;
-+#endif
-+#ifdef CONFIG_PARAVIRT_TIME_ACCOUNTING
-+	if (static_key_false((&paravirt_steal_rq_enabled))) {
-+		steal = paravirt_steal_clock(cpu_of(rq));
-+		steal -= rq->prev_steal_time_rq;
-+
-+		if (unlikely(steal > delta))
-+			steal = delta;
-+
-+		rq->prev_steal_time_rq += steal;
-+		delta -= steal;
-+	}
-+#endif
-+	rq->clock_task += delta;
-+
-+#ifdef CONFIG_HAVE_SCHED_AVG_IRQ
-+	if (irq_delta + steal)
-+		update_irq_load_avg(rq, irq_delta + steal);
-+#endif
-+}
-+
-+static inline void update_rq_clock(struct rq *rq)
-+{
-+	s64 delta = sched_clock_cpu(cpu_of(rq)) - rq->clock;
-+
-+	if (unlikely(delta < 0))
-+		return;
-+	rq->clock += delta;
-+	update_rq_clock_task(rq, delta);
-+}
-+
-+/*
-+ * Niffies are a globally increasing nanosecond counter. They're only used by
-+ * update_load_avg and time_slice_expired, however deadlines are based on them
-+ * across CPUs. Update them whenever we will call one of those functions, and
-+ * synchronise them across CPUs whenever we hold both runqueue locks.
-+ */
-+static inline void update_clocks(struct rq *rq)
-+{
-+	s64 ndiff, minndiff;
-+	long jdiff;
-+
-+	update_rq_clock(rq);
-+	ndiff = rq->clock - rq->old_clock;
-+	rq->old_clock = rq->clock;
-+	jdiff = jiffies - rq->last_jiffy;
-+
-+	/* Subtract any niffies added by balancing with other rqs */
-+	ndiff -= rq->niffies - rq->last_niffy;
-+	minndiff = JIFFIES_TO_NS(jdiff) - rq->niffies + rq->last_jiffy_niffies;
-+	if (minndiff < 0)
-+		minndiff = 0;
-+	ndiff = max(ndiff, minndiff);
-+	rq->niffies += ndiff;
-+	rq->last_niffy = rq->niffies;
-+	if (jdiff) {
-+		rq->last_jiffy += jdiff;
-+		rq->last_jiffy_niffies = rq->niffies;
-+	}
-+}
-+
-+/*
-+ * Any time we have two runqueues locked we use that as an opportunity to
-+ * synchronise niffies to the highest value as idle ticks may have artificially
-+ * kept niffies low on one CPU and the truth can only be later.
-+ */
-+static inline void synchronise_niffies(struct rq *rq1, struct rq *rq2)
-+{
-+	if (rq1->niffies > rq2->niffies)
-+		rq2->niffies = rq1->niffies;
-+	else
-+		rq1->niffies = rq2->niffies;
-+}
-+
-+/*
-+ * double_rq_lock - safely lock two runqueues
-+ *
-+ * Note this does not disable interrupts like task_rq_lock,
-+ * you need to do so manually before calling.
-+ */
-+
-+/* For when we know rq1 != rq2 */
-+static inline void __double_rq_lock(struct rq *rq1, struct rq *rq2)
-+	__acquires(rq1->lock)
-+	__acquires(rq2->lock)
-+{
-+	if (rq1 < rq2) {
-+		raw_spin_lock(rq1->lock);
-+		raw_spin_lock_nested(rq2->lock, SINGLE_DEPTH_NESTING);
-+	} else {
-+		raw_spin_lock(rq2->lock);
-+		raw_spin_lock_nested(rq1->lock, SINGLE_DEPTH_NESTING);
-+	}
-+}
-+
-+static inline void double_rq_lock(struct rq *rq1, struct rq *rq2)
-+	__acquires(rq1->lock)
-+	__acquires(rq2->lock)
-+{
-+	BUG_ON(!irqs_disabled());
-+	if (rq1->lock == rq2->lock) {
-+		raw_spin_lock(rq1->lock);
-+		__acquire(rq2->lock);	/* Fake it out ;) */
-+	} else
-+		__double_rq_lock(rq1, rq2);
-+	synchronise_niffies(rq1, rq2);
-+}
-+
-+/*
-+ * double_rq_unlock - safely unlock two runqueues
-+ *
-+ * Note this does not restore interrupts like task_rq_unlock,
-+ * you need to do so manually after calling.
-+ */
-+static inline void double_rq_unlock(struct rq *rq1, struct rq *rq2)
-+	__releases(rq1->lock)
-+	__releases(rq2->lock)
-+{
-+	raw_spin_unlock(rq1->lock);
-+	if (rq1->lock != rq2->lock)
-+		raw_spin_unlock(rq2->lock);
-+	else
-+		__release(rq2->lock);
-+}
-+
-+static inline void lock_all_rqs(void)
-+{
-+	int cpu;
-+
-+	preempt_disable();
-+	for_each_possible_cpu(cpu) {
-+		struct rq *rq = cpu_rq(cpu);
-+
-+		do_raw_spin_lock(rq->lock);
-+	}
-+}
-+
-+static inline void unlock_all_rqs(void)
-+{
-+	int cpu;
-+
-+	for_each_possible_cpu(cpu) {
-+		struct rq *rq = cpu_rq(cpu);
-+
-+		do_raw_spin_unlock(rq->lock);
-+	}
-+	preempt_enable();
-+}
-+
-+/* Specially nest trylock an rq */
-+static inline bool trylock_rq(struct rq *this_rq, struct rq *rq)
-+{
-+	if (unlikely(!do_raw_spin_trylock(rq->lock)))
-+		return false;
-+	spin_acquire(&rq->lock->dep_map, SINGLE_DEPTH_NESTING, 1, _RET_IP_);
-+	synchronise_niffies(this_rq, rq);
-+	return true;
-+}
-+
-+/* Unlock a specially nested trylocked rq */
-+static inline void unlock_rq(struct rq *rq)
-+{
-+	spin_release(&rq->lock->dep_map, 1, _RET_IP_);
-+	do_raw_spin_unlock(rq->lock);
-+}
-+
-+/*
-+ * cmpxchg based fetch_or, macro so it works for different integer types
-+ */
-+#define fetch_or(ptr, mask)						\
-+	({								\
-+		typeof(ptr) _ptr = (ptr);				\
-+		typeof(mask) _mask = (mask);				\
-+		typeof(*_ptr) _old, _val = *_ptr;			\
-+									\
-+		for (;;) {						\
-+			_old = cmpxchg(_ptr, _val, _val | _mask);	\
-+			if (_old == _val)				\
-+				break;					\
-+			_val = _old;					\
-+		}							\
-+	_old;								\
-+})
-+
-+#if defined(CONFIG_SMP) && defined(TIF_POLLING_NRFLAG)
-+/*
-+ * Atomically set TIF_NEED_RESCHED and test for TIF_POLLING_NRFLAG,
-+ * this avoids any races wrt polling state changes and thereby avoids
-+ * spurious IPIs.
-+ */
-+static bool set_nr_and_not_polling(struct task_struct *p)
-+{
-+	struct thread_info *ti = task_thread_info(p);
-+	return !(fetch_or(&ti->flags, _TIF_NEED_RESCHED) & _TIF_POLLING_NRFLAG);
-+}
-+
-+/*
-+ * Atomically set TIF_NEED_RESCHED if TIF_POLLING_NRFLAG is set.
-+ *
-+ * If this returns true, then the idle task promises to call
-+ * sched_ttwu_pending() and reschedule soon.
-+ */
-+static bool set_nr_if_polling(struct task_struct *p)
-+{
-+	struct thread_info *ti = task_thread_info(p);
-+	typeof(ti->flags) old, val = READ_ONCE(ti->flags);
-+
-+	for (;;) {
-+		if (!(val & _TIF_POLLING_NRFLAG))
-+			return false;
-+		if (val & _TIF_NEED_RESCHED)
-+			return true;
-+		old = cmpxchg(&ti->flags, val, val | _TIF_NEED_RESCHED);
-+		if (old == val)
-+			break;
-+		val = old;
-+	}
-+	return true;
-+}
-+
-+#else
-+static bool set_nr_and_not_polling(struct task_struct *p)
-+{
-+	set_tsk_need_resched(p);
-+	return true;
-+}
-+
-+#ifdef CONFIG_SMP
-+static bool set_nr_if_polling(struct task_struct *p)
-+{
-+	return false;
-+}
-+#endif
-+#endif
-+
-+static bool __wake_q_add(struct wake_q_head *head, struct task_struct *task)
-+{
-+	struct wake_q_node *node = &task->wake_q;
-+
-+	/*
-+	 * Atomically grab the task, if ->wake_q is !nil already it means
-+	 * its already queued (either by us or someone else) and will get the
-+	 * wakeup due to that.
-+	 *
-+	 * In order to ensure that a pending wakeup will observe our pending
-+	 * state, even in the failed case, an explicit smp_mb() must be used.
-+	 */
-+	smp_mb__before_atomic();
-+	if (unlikely(cmpxchg_relaxed(&node->next, NULL, WAKE_Q_TAIL)))
-+		return false;
-+
-+	/*
-+	 * The head is context local, there can be no concurrency.
-+	 */
-+	*head->lastp = node;
-+	head->lastp = &node->next;
-+	return true;
-+}
-+
-+/**
-+ * wake_q_add() - queue a wakeup for 'later' waking.
-+ * @head: the wake_q_head to add @task to
-+ * @task: the task to queue for 'later' wakeup
-+ *
-+ * Queue a task for later wakeup, most likely by the wake_up_q() call in the
-+ * same context, _HOWEVER_ this is not guaranteed, the wakeup can come
-+ * instantly.
-+ *
-+ * This function must be used as-if it were wake_up_process(); IOW the task
-+ * must be ready to be woken at this location.
-+ */
-+void wake_q_add(struct wake_q_head *head, struct task_struct *task)
-+{
-+	if (__wake_q_add(head, task))
-+		get_task_struct(task);
-+}
-+
-+/**
-+ * wake_q_add_safe() - safely queue a wakeup for 'later' waking.
-+ * @head: the wake_q_head to add @task to
-+ * @task: the task to queue for 'later' wakeup
-+ *
-+ * Queue a task for later wakeup, most likely by the wake_up_q() call in the
-+ * same context, _HOWEVER_ this is not guaranteed, the wakeup can come
-+ * instantly.
-+ *
-+ * This function must be used as-if it were wake_up_process(); IOW the task
-+ * must be ready to be woken at this location.
-+ *
-+ * This function is essentially a task-safe equivalent to wake_q_add(). Callers
-+ * that already hold reference to @task can call the 'safe' version and trust
-+ * wake_q to do the right thing depending whether or not the @task is already
-+ * queued for wakeup.
-+ */
-+void wake_q_add_safe(struct wake_q_head *head, struct task_struct *task)
-+{
-+	if (!__wake_q_add(head, task))
-+		put_task_struct(task);
-+}
-+
-+void wake_up_q(struct wake_q_head *head)
-+{
-+	struct wake_q_node *node = head->first;
-+
-+	while (node != WAKE_Q_TAIL) {
-+		struct task_struct *task;
-+
-+		task = container_of(node, struct task_struct, wake_q);
-+		BUG_ON(!task);
-+		/* Task can safely be re-inserted now */
-+		node = node->next;
-+		task->wake_q.next = NULL;
-+
-+		/*
-+		 * wake_up_process() executes a full barrier, which pairs with
-+		 * the queueing in wake_q_add() so as not to miss wakeups.
-+		 */
-+		wake_up_process(task);
-+		put_task_struct(task);
-+	}
-+}
-+
-+static inline void smp_sched_reschedule(int cpu)
-+{
-+	if (likely(cpu_online(cpu)))
-+		smp_send_reschedule(cpu);
-+}
-+
-+/*
-+ * resched_task - mark a task 'to be rescheduled now'.
-+ *
-+ * On UP this means the setting of the need_resched flag, on SMP it
-+ * might also involve a cross-CPU call to trigger the scheduler on
-+ * the target CPU.
-+ */
-+void resched_task(struct task_struct *p)
-+{
-+	int cpu;
-+#ifdef CONFIG_LOCKDEP
-+	/* Kernel threads call this when creating workqueues while still
-+	 * inactive from __kthread_bind_mask, holding only the pi_lock */
-+	if (!(p->flags & PF_KTHREAD)) {
-+		struct rq *rq = task_rq(p);
-+
-+		lockdep_assert_held(rq->lock);
-+	}
-+#endif
-+	if (test_tsk_need_resched(p))
-+		return;
-+
-+	cpu = task_cpu(p);
-+	if (cpu == smp_processor_id()) {
-+		set_tsk_need_resched(p);
-+		set_preempt_need_resched();
-+		return;
-+	}
-+
-+	if (set_nr_and_not_polling(p))
-+		smp_sched_reschedule(cpu);
-+	else
-+		trace_sched_wake_idle_without_ipi(cpu);
-+}
-+
-+/*
-+ * A task that is not running or queued will not have a node set.
-+ * A task that is queued but not running will have a node set.
-+ * A task that is currently running will have ->on_cpu set but no node set.
-+ */
-+static inline bool task_queued(struct task_struct *p)
-+{
-+	return !skiplist_node_empty(&p->node);
-+}
-+
-+static void enqueue_task(struct rq *rq, struct task_struct *p, int flags);
-+static inline void resched_if_idle(struct rq *rq);
-+
-+/* Dodgy workaround till we figure out where the softirqs are going */
-+static inline void do_pending_softirq(struct rq *rq, struct task_struct *next)
-+{
-+	if (unlikely(next == rq->idle && local_softirq_pending() && !in_interrupt()))
-+		do_softirq_own_stack();
-+}
-+
-+static inline bool deadline_before(u64 deadline, u64 time)
-+{
-+	return (deadline < time);
-+}
-+
-+/*
-+ * Deadline is "now" in niffies + (offset by priority). Setting the deadline
-+ * is the key to everything. It distributes cpu fairly amongst tasks of the
-+ * same nice value, it proportions cpu according to nice level, it means the
-+ * task that last woke up the longest ago has the earliest deadline, thus
-+ * ensuring that interactive tasks get low latency on wake up. The CPU
-+ * proportion works out to the square of the virtual deadline difference, so
-+ * this equation will give nice 19 3% CPU compared to nice 0.
-+ */
-+static inline u64 prio_deadline_diff(int user_prio)
-+{
-+	return (prio_ratios[user_prio] * rr_interval * (MS_TO_NS(1) / 128));
-+}
-+
-+static inline u64 task_deadline_diff(struct task_struct *p)
-+{
-+	return prio_deadline_diff(TASK_USER_PRIO(p));
-+}
-+
-+static inline u64 static_deadline_diff(int static_prio)
-+{
-+	return prio_deadline_diff(USER_PRIO(static_prio));
-+}
-+
-+static inline int longest_deadline_diff(void)
-+{
-+	return prio_deadline_diff(39);
-+}
-+
-+static inline int ms_longest_deadline_diff(void)
-+{
-+	return NS_TO_MS(longest_deadline_diff());
-+}
-+
-+static inline bool rq_local(struct rq *rq);
-+
-+#ifndef SCHED_CAPACITY_SCALE
-+#define SCHED_CAPACITY_SCALE 1024
-+#endif
-+
-+static inline int rq_load(struct rq *rq)
-+{
-+	return rq->nr_running;
-+}
-+
-+/*
-+ * Update the load average for feeding into cpu frequency governors. Use a
-+ * rough estimate of a rolling average with ~ time constant of 32ms.
-+ * 80/128 ~ 0.63. * 80 / 32768 / 128 == * 5 / 262144
-+ * Make sure a call to update_clocks has been made before calling this to get
-+ * an updated rq->niffies.
-+ */
-+static void update_load_avg(struct rq *rq, unsigned int flags)
-+{
-+	long us_interval, load;
-+	unsigned long curload;
-+
-+	us_interval = NS_TO_US(rq->niffies - rq->load_update);
-+	if (unlikely(us_interval <= 0))
-+		return;
-+
-+	curload = rq_load(rq);
-+	load = rq->load_avg - (rq->load_avg * us_interval * 5 / 262144);
-+	if (unlikely(load < 0))
-+		load = 0;
-+	load += curload * curload * SCHED_CAPACITY_SCALE * us_interval * 5 / 262144;
-+	rq->load_avg = load;
-+
-+	rq->load_update = rq->niffies;
-+	update_irq_load_avg(rq, 0);
-+	if (likely(rq_local(rq)))
-+		cpufreq_trigger(rq, flags);
-+}
-+
-+#ifdef HAVE_SCHED_AVG_IRQ
-+/*
-+ * IRQ variant of update_load_avg below. delta is actually time in nanoseconds
-+ * here so we scale curload to how long it's been since the last update.
-+ */
-+static void update_irq_load_avg(struct rq *rq, long delta)
-+{
-+	long us_interval, load;
-+	unsigned long curload;
-+
-+	us_interval = NS_TO_US(rq->niffies - rq->irq_load_update);
-+	if (unlikely(us_interval <= 0))
-+		return;
-+
-+	curload = NS_TO_US(delta) / us_interval;
-+	load = rq->irq_load_avg - (rq->irq_load_avg * us_interval * 5 / 262144);
-+	if (unlikely(load < 0))
-+		load = 0;
-+	load += curload * curload * SCHED_CAPACITY_SCALE * us_interval * 5 / 262144;
-+	rq->irq_load_avg = load;
-+
-+	rq->irq_load_update = rq->niffies;
-+}
-+#endif
-+
-+/*
-+ * Removing from the runqueue. Enter with rq locked. Deleting a task
-+ * from the skip list is done via the stored node reference in the task struct
-+ * and does not require a full look up. Thus it occurs in O(k) time where k
-+ * is the "level" of the list the task was stored at - usually < 4, max 8.
-+ */
-+static void dequeue_task(struct rq *rq, struct task_struct *p, int flags)
-+{
-+	skiplist_delete(rq->sl, &p->node);
-+	rq->best_key = rq->node->next[0]->key;
-+	update_clocks(rq);
-+
-+	if (!(flags & DEQUEUE_SAVE)) {
-+		sched_info_dequeued(rq, p);
-+		psi_dequeue(p, flags & DEQUEUE_SLEEP);
-+	}
-+	rq->nr_running--;
-+	if (rt_task(p))
-+		rq->rt_nr_running--;
-+	update_load_avg(rq, flags);
-+}
-+
-+#ifdef CONFIG_PREEMPT_RCU
-+static bool rcu_read_critical(struct task_struct *p)
-+{
-+	return p->rcu_read_unlock_special.b.blocked;
-+}
-+#else /* CONFIG_PREEMPT_RCU */
-+#define rcu_read_critical(p) (false)
-+#endif /* CONFIG_PREEMPT_RCU */
-+
-+/*
-+ * To determine if it's safe for a task of SCHED_IDLEPRIO to actually run as
-+ * an idle task, we ensure none of the following conditions are met.
-+ */
-+static bool idleprio_suitable(struct task_struct *p)
-+{
-+	return (!(task_contributes_to_load(p)) && !(p->flags & (PF_EXITING)) &&
-+		!signal_pending(p) && !rcu_read_critical(p) && !freezing(p));
-+}
-+
-+/*
-+ * To determine if a task of SCHED_ISO can run in pseudo-realtime, we check
-+ * that the iso_refractory flag is not set.
-+ */
-+static inline bool isoprio_suitable(struct rq *rq)
-+{
-+	return !rq->iso_refractory;
-+}
-+
-+/*
-+ * Adding to the runqueue. Enter with rq locked.
-+ */
-+static void enqueue_task(struct rq *rq, struct task_struct *p, int flags)
-+{
-+	unsigned int randseed, cflags = 0;
-+	u64 sl_id;
-+
-+	if (!rt_task(p)) {
-+		/* Check it hasn't gotten rt from PI */
-+		if ((idleprio_task(p) && idleprio_suitable(p)) ||
-+		   (iso_task(p) && isoprio_suitable(rq)))
-+			p->prio = p->normal_prio;
-+		else
-+			p->prio = NORMAL_PRIO;
-+	} else
-+		rq->rt_nr_running++;
-+	/*
-+	 * The sl_id key passed to the skiplist generates a sorted list.
-+	 * Realtime and sched iso tasks run FIFO so they only need be sorted
-+	 * according to priority. The skiplist will put tasks of the same
-+	 * key inserted later in FIFO order. Tasks of sched normal, batch
-+	 * and idleprio are sorted according to their deadlines. Idleprio
-+	 * tasks are offset by an impossibly large deadline value ensuring
-+	 * they get sorted into last positions, but still according to their
-+	 * own deadlines. This creates a "landscape" of skiplists running
-+	 * from priority 0 realtime in first place to the lowest priority
-+	 * idleprio tasks last. Skiplist insertion is an O(log n) process.
-+	 */
-+	if (p->prio <= ISO_PRIO) {
-+		sl_id = p->prio;
-+	} else {
-+		sl_id = p->deadline;
-+		if (idleprio_task(p)) {
-+			if (p->prio == IDLE_PRIO)
-+				sl_id |= 0xF000000000000000;
-+			else
-+				sl_id += longest_deadline_diff();
-+		}
-+	}
-+	/*
-+	 * Some architectures don't have better than microsecond resolution
-+	 * so mask out ~microseconds as the random seed for skiplist insertion.
-+	 */
-+	update_clocks(rq);
-+	if (!(flags & ENQUEUE_RESTORE)) {
-+		sched_info_queued(rq, p);
-+		psi_enqueue(p, flags & ENQUEUE_WAKEUP);
-+	}
-+
-+	randseed = (rq->niffies >> 10) & 0xFFFFFFFF;
-+	skiplist_insert(rq->sl, &p->node, sl_id, p, randseed);
-+	rq->best_key = rq->node->next[0]->key;
-+	if (p->in_iowait)
-+		cflags |= SCHED_CPUFREQ_IOWAIT;
-+	rq->nr_running++;
-+	update_load_avg(rq, cflags);
-+}
-+
-+/*
-+ * Returns the relative length of deadline all compared to the shortest
-+ * deadline which is that of nice -20.
-+ */
-+static inline int task_prio_ratio(struct task_struct *p)
-+{
-+	return prio_ratios[TASK_USER_PRIO(p)];
-+}
-+
-+/*
-+ * task_timeslice - all tasks of all priorities get the exact same timeslice
-+ * length. CPU distribution is handled by giving different deadlines to
-+ * tasks of different priorities. Use 128 as the base value for fast shifts.
-+ */
-+static inline int task_timeslice(struct task_struct *p)
-+{
-+	return (rr_interval * task_prio_ratio(p) / 128);
-+}
-+
-+#ifdef CONFIG_SMP
-+/* Entered with rq locked */
-+static inline void resched_if_idle(struct rq *rq)
-+{
-+	if (rq_idle(rq))
-+		resched_task(rq->curr);
-+}
-+
-+static inline bool rq_local(struct rq *rq)
-+{
-+	return (rq->cpu == smp_processor_id());
-+}
-+#ifdef CONFIG_SMT_NICE
-+static const cpumask_t *thread_cpumask(int cpu);
-+
-+/* Find the best real time priority running on any SMT siblings of cpu and if
-+ * none are running, the static priority of the best deadline task running.
-+ * The lookups to the other runqueues is done lockless as the occasional wrong
-+ * value would be harmless. */
-+static int best_smt_bias(struct rq *this_rq)
-+{
-+	int other_cpu, best_bias = 0;
-+
-+	for_each_cpu(other_cpu, &this_rq->thread_mask) {
-+		struct rq *rq = cpu_rq(other_cpu);
-+
-+		if (rq_idle(rq))
-+			continue;
-+		if (unlikely(!rq->online))
-+			continue;
-+		if (!rq->rq_mm)
-+			continue;
-+		if (likely(rq->rq_smt_bias > best_bias))
-+			best_bias = rq->rq_smt_bias;
-+	}
-+	return best_bias;
-+}
-+
-+static int task_prio_bias(struct task_struct *p)
-+{
-+	if (rt_task(p))
-+		return 1 << 30;
-+	else if (task_running_iso(p))
-+		return 1 << 29;
-+	else if (task_running_idle(p))
-+		return 0;
-+	return MAX_PRIO - p->static_prio;
-+}
-+
-+static bool smt_always_schedule(struct task_struct __maybe_unused *p, struct rq __maybe_unused *this_rq)
-+{
-+	return true;
-+}
-+
-+static bool (*smt_schedule)(struct task_struct *p, struct rq *this_rq) = &smt_always_schedule;
-+
-+/* We've already decided p can run on CPU, now test if it shouldn't for SMT
-+ * nice reasons. */
-+static bool smt_should_schedule(struct task_struct *p, struct rq *this_rq)
-+{
-+	int best_bias, task_bias;
-+
-+	/* Kernel threads always run */
-+	if (unlikely(!p->mm))
-+		return true;
-+	if (rt_task(p))
-+		return true;
-+	if (!idleprio_suitable(p))
-+		return true;
-+	best_bias = best_smt_bias(this_rq);
-+	/* The smt siblings are all idle or running IDLEPRIO */
-+	if (best_bias < 1)
-+		return true;
-+	task_bias = task_prio_bias(p);
-+	if (task_bias < 1)
-+		return false;
-+	if (task_bias >= best_bias)
-+		return true;
-+	/* Dither 25% cpu of normal tasks regardless of nice difference */
-+	if (best_bias % 4 == 1)
-+		return true;
-+	/* Sorry, you lose */
-+	return false;
-+}
-+#else /* CONFIG_SMT_NICE */
-+#define smt_schedule(p, this_rq) (true)
-+#endif /* CONFIG_SMT_NICE */
-+
-+static inline void atomic_set_cpu(int cpu, cpumask_t *cpumask)
-+{
-+	set_bit(cpu, (volatile unsigned long *)cpumask);
-+}
-+
-+/*
-+ * The cpu_idle_map stores a bitmap of all the CPUs currently idle to
-+ * allow easy lookup of whether any suitable idle CPUs are available.
-+ * It's cheaper to maintain a binary yes/no if there are any idle CPUs on the
-+ * idle_cpus variable than to do a full bitmask check when we are busy. The
-+ * bits are set atomically but read locklessly as occasional false positive /
-+ * negative is harmless.
-+ */
-+static inline void set_cpuidle_map(int cpu)
-+{
-+	if (likely(cpu_online(cpu)))
-+		atomic_set_cpu(cpu, &cpu_idle_map);
-+}
-+
-+static inline void atomic_clear_cpu(int cpu, cpumask_t *cpumask)
-+{
-+	clear_bit(cpu, (volatile unsigned long *)cpumask);
-+}
-+
-+static inline void clear_cpuidle_map(int cpu)
-+{
-+	atomic_clear_cpu(cpu, &cpu_idle_map);
-+}
-+
-+static bool suitable_idle_cpus(struct task_struct *p)
-+{
-+	return (cpumask_intersects(p->cpus_ptr, &cpu_idle_map));
-+}
-+
-+/*
-+ * Resched current on rq. We don't know if rq is local to this CPU nor if it
-+ * is locked so we do not use an intermediate variable for the task to avoid
-+ * having it dereferenced.
-+ */
-+static void resched_curr(struct rq *rq)
-+{
-+	int cpu;
-+
-+	if (test_tsk_need_resched(rq->curr))
-+		return;
-+
-+	rq->preempt = rq->curr;
-+	cpu = rq->cpu;
-+
-+	/* We're doing this without holding the rq lock if it's not task_rq */
-+
-+	if (cpu == smp_processor_id()) {
-+		set_tsk_need_resched(rq->curr);
-+		set_preempt_need_resched();
-+		return;
-+	}
-+
-+	if (set_nr_and_not_polling(rq->curr))
-+		smp_sched_reschedule(cpu);
-+	else
-+		trace_sched_wake_idle_without_ipi(cpu);
-+}
-+
-+#define CPUIDLE_DIFF_THREAD     (1)
-+#define CPUIDLE_DIFF_CORE_LLC   (2)
-+#define CPUIDLE_DIFF_CORE       (4)
-+#define CPUIDLE_CACHE_BUSY      (8)
-+#define CPUIDLE_DIFF_CPU        (16)
-+#define CPUIDLE_THREAD_BUSY     (32)
-+#define CPUIDLE_DIFF_NODE       (64)
-+
-+/*
-+ * The best idle CPU is chosen according to the CPUIDLE ranking above where the
-+ * lowest value would give the most suitable CPU to schedule p onto next. The
-+ * order works out to be the following:
-+ *
-+ * Same thread, idle or busy cache, idle or busy threads
-+ * Other core, same cache, idle or busy cache, idle threads.
-+ * Same node, other CPU, idle cache, idle threads.
-+ * Same node, other CPU, busy cache, idle threads.
-+ * Other core, same cache, busy threads.
-+ * Same node, other CPU, busy threads.
-+ * Other node, other CPU, idle cache, idle threads.
-+ * Other node, other CPU, busy cache, idle threads.
-+ * Other node, other CPU, busy threads.
-+ */
-+static int best_mask_cpu(int best_cpu, struct rq *rq, cpumask_t *tmpmask)
-+{
-+	int best_ranking = CPUIDLE_DIFF_NODE | CPUIDLE_THREAD_BUSY |
-+		CPUIDLE_DIFF_CPU | CPUIDLE_CACHE_BUSY | CPUIDLE_DIFF_CORE |
-+		CPUIDLE_DIFF_CORE_LLC | CPUIDLE_DIFF_THREAD;
-+	int cpu_tmp;
-+
-+	if (cpumask_test_cpu(best_cpu, tmpmask))
-+		goto out;
-+
-+	for_each_cpu(cpu_tmp, tmpmask) {
-+		int ranking, locality;
-+		struct rq *tmp_rq;
-+
-+		ranking = 0;
-+		tmp_rq = cpu_rq(cpu_tmp);
-+
-+		locality = rq->cpu_locality[cpu_tmp];
-+#ifdef CONFIG_NUMA
-+		if (locality > LOCALITY_SMP)
-+			ranking |= CPUIDLE_DIFF_NODE;
-+		else
-+#endif
-+			if (locality > LOCALITY_MC)
-+				ranking |= CPUIDLE_DIFF_CPU;
-+#ifdef CONFIG_SCHED_MC
-+			else if (locality == LOCALITY_MC_LLC)
-+				ranking |= CPUIDLE_DIFF_CORE_LLC;
-+			else if (locality == LOCALITY_MC)
-+				ranking |= CPUIDLE_DIFF_CORE;
-+		if (!(tmp_rq->cache_idle(tmp_rq)))
-+			ranking |= CPUIDLE_CACHE_BUSY;
-+#endif
-+#ifdef CONFIG_SCHED_SMT
-+		if (locality == LOCALITY_SMT)
-+			ranking |= CPUIDLE_DIFF_THREAD;
-+#endif
-+		if (ranking < best_ranking
-+#ifdef CONFIG_SCHED_SMT
-+			|| (ranking == best_ranking && (tmp_rq->siblings_idle(tmp_rq)))
-+#endif
-+		) {
-+			best_cpu = cpu_tmp;
-+			best_ranking = ranking;
-+		}
-+	}
-+out:
-+	return best_cpu;
-+}
-+
-+bool cpus_share_cache(int this_cpu, int that_cpu)
-+{
-+	struct rq *this_rq = cpu_rq(this_cpu);
-+
-+	return (this_rq->cpu_locality[that_cpu] < LOCALITY_SMP);
-+}
-+
-+/* As per resched_curr but only will resched idle task */
-+static inline void resched_idle(struct rq *rq)
-+{
-+	if (test_tsk_need_resched(rq->idle))
-+		return;
-+
-+	rq->preempt = rq->idle;
-+
-+	set_tsk_need_resched(rq->idle);
-+
-+	if (rq_local(rq)) {
-+		set_preempt_need_resched();
-+		return;
-+	}
-+
-+	smp_sched_reschedule(rq->cpu);
-+}
-+
-+static struct rq *resched_best_idle(struct task_struct *p, int cpu)
-+{
-+	cpumask_t tmpmask;
-+	struct rq *rq;
-+	int best_cpu;
-+
-+	cpumask_and(&tmpmask, p->cpus_ptr, &cpu_idle_map);
-+	best_cpu = best_mask_cpu(cpu, task_rq(p), &tmpmask);
-+	rq = cpu_rq(best_cpu);
-+	if (!smt_schedule(p, rq))
-+		return NULL;
-+	rq->preempt = p;
-+	resched_idle(rq);
-+	return rq;
-+}
-+
-+static inline void resched_suitable_idle(struct task_struct *p)
-+{
-+	if (suitable_idle_cpus(p))
-+		resched_best_idle(p, task_cpu(p));
-+}
-+
-+static inline struct rq *rq_order(struct rq *rq, int cpu)
-+{
-+	return rq->rq_order[cpu];
-+}
-+#else /* CONFIG_SMP */
-+static inline void set_cpuidle_map(int cpu)
-+{
-+}
-+
-+static inline void clear_cpuidle_map(int cpu)
-+{
-+}
-+
-+static inline bool suitable_idle_cpus(struct task_struct *p)
-+{
-+	return uprq->curr == uprq->idle;
-+}
-+
-+static inline void resched_suitable_idle(struct task_struct *p)
-+{
-+}
-+
-+static inline void resched_curr(struct rq *rq)
-+{
-+	resched_task(rq->curr);
-+}
-+
-+static inline void resched_if_idle(struct rq *rq)
-+{
-+}
-+
-+static inline bool rq_local(struct rq *rq)
-+{
-+	return true;
-+}
-+
-+static inline struct rq *rq_order(struct rq *rq, int cpu)
-+{
-+	return rq;
-+}
-+
-+static inline bool smt_schedule(struct task_struct *p, struct rq *rq)
-+{
-+	return true;
-+}
-+#endif /* CONFIG_SMP */
-+
-+static inline int normal_prio(struct task_struct *p)
-+{
-+	if (has_rt_policy(p))
-+		return MAX_RT_PRIO - 1 - p->rt_priority;
-+	if (idleprio_task(p))
-+		return IDLE_PRIO;
-+	if (iso_task(p))
-+		return ISO_PRIO;
-+	return NORMAL_PRIO;
-+}
-+
-+/*
-+ * Calculate the current priority, i.e. the priority
-+ * taken into account by the scheduler. This value might
-+ * be boosted by RT tasks as it will be RT if the task got
-+ * RT-boosted. If not then it returns p->normal_prio.
-+ */
-+static int effective_prio(struct task_struct *p)
-+{
-+	p->normal_prio = normal_prio(p);
-+	/*
-+	 * If we are RT tasks or we were boosted to RT priority,
-+	 * keep the priority unchanged. Otherwise, update priority
-+	 * to the normal priority:
-+	 */
-+	if (!rt_prio(p->prio))
-+		return p->normal_prio;
-+	return p->prio;
-+}
-+
-+/*
-+ * activate_task - move a task to the runqueue. Enter with rq locked.
-+ */
-+static void activate_task(struct rq *rq, struct task_struct *p, int flags)
-+{
-+	resched_if_idle(rq);
-+
-+	/*
-+	 * Sleep time is in units of nanosecs, so shift by 20 to get a
-+	 * milliseconds-range estimation of the amount of time that the task
-+	 * spent sleeping:
-+	 */
-+	if (unlikely(prof_on == SLEEP_PROFILING)) {
-+		if (p->state == TASK_UNINTERRUPTIBLE)
-+			profile_hits(SLEEP_PROFILING, (void *)get_wchan(p),
-+				     (rq->niffies - p->last_ran) >> 20);
-+	}
-+
-+	p->prio = effective_prio(p);
-+	if (task_contributes_to_load(p))
-+		rq->nr_uninterruptible--;
-+
-+	enqueue_task(rq, p, flags);
-+	p->on_rq = TASK_ON_RQ_QUEUED;
-+}
-+
-+/*
-+ * deactivate_task - If it's running, it's not on the runqueue and we can just
-+ * decrement the nr_running. Enter with rq locked.
-+ */
-+static inline void deactivate_task(struct task_struct *p, struct rq *rq)
-+{
-+	if (task_contributes_to_load(p))
-+		rq->nr_uninterruptible++;
-+
-+	p->on_rq = 0;
-+	sched_info_dequeued(rq, p);
-+	/* deactivate_task is always DEQUEUE_SLEEP in muqss */
-+	psi_dequeue(p, DEQUEUE_SLEEP);
-+}
-+
-+#ifdef CONFIG_SMP
-+void set_task_cpu(struct task_struct *p, unsigned int new_cpu)
-+{
-+	struct rq *rq;
-+
-+	if (task_cpu(p) == new_cpu)
-+		return;
-+
-+	/* Do NOT call set_task_cpu on a currently queued task as we will not
-+	 * be reliably holding the rq lock after changing CPU. */
-+	BUG_ON(task_queued(p));
-+	rq = task_rq(p);
-+
-+#ifdef CONFIG_LOCKDEP
-+	/*
-+	 * The caller should hold either p->pi_lock or rq->lock, when changing
-+	 * a task's CPU. ->pi_lock for waking tasks, rq->lock for runnable tasks.
-+	 *
-+	 * Furthermore, all task_rq users should acquire both locks, see
-+	 * task_rq_lock().
-+	 */
-+	WARN_ON_ONCE(debug_locks && !(lockdep_is_held(&p->pi_lock) ||
-+				      lockdep_is_held(rq->lock)));
-+#endif
-+
-+	trace_sched_migrate_task(p, new_cpu);
-+	rseq_migrate(p);
-+	perf_event_task_migrate(p);
-+
-+	/*
-+	 * After ->cpu is set up to a new value, task_rq_lock(p, ...) can be
-+	 * successfully executed on another CPU. We must ensure that updates of
-+	 * per-task data have been completed by this moment.
-+	 */
-+	smp_wmb();
-+
-+	p->wake_cpu = new_cpu;
-+
-+	if (task_running(rq, p)) {
-+		/*
-+		 * We should only be calling this on a running task if we're
-+		 * holding rq lock.
-+		 */
-+		lockdep_assert_held(rq->lock);
-+
-+		/*
-+		 * We can't change the task_thread_info CPU on a running task
-+		 * as p will still be protected by the rq lock of the CPU it
-+		 * is still running on so we only set the wake_cpu for it to be
-+		 * lazily updated once off the CPU.
-+		 */
-+		return;
-+	}
-+
-+#ifdef CONFIG_THREAD_INFO_IN_TASK
-+	WRITE_ONCE(p->cpu, new_cpu);
-+#else
-+	WRITE_ONCE(task_thread_info(p)->cpu, new_cpu);
-+#endif
-+	/* We're no longer protecting p after this point since we're holding
-+	 * the wrong runqueue lock. */
-+}
-+#endif /* CONFIG_SMP */
-+
-+/*
-+ * Move a task off the runqueue and take it to a cpu for it will
-+ * become the running task.
-+ */
-+static inline void take_task(struct rq *rq, int cpu, struct task_struct *p)
-+{
-+	struct rq *p_rq = task_rq(p);
-+
-+	dequeue_task(p_rq, p, DEQUEUE_SAVE);
-+	if (p_rq != rq) {
-+		sched_info_dequeued(p_rq, p);
-+		sched_info_queued(rq, p);
-+	}
-+	set_task_cpu(p, cpu);
-+}
-+
-+/*
-+ * Returns a descheduling task to the runqueue unless it is being
-+ * deactivated.
-+ */
-+static inline void return_task(struct task_struct *p, struct rq *rq,
-+			       int cpu, bool deactivate)
-+{
-+	if (deactivate)
-+		deactivate_task(p, rq);
-+	else {
-+#ifdef CONFIG_SMP
-+		/*
-+		 * set_task_cpu was called on the running task that doesn't
-+		 * want to deactivate so it has to be enqueued to a different
-+		 * CPU and we need its lock. Tag it to be moved with as the
-+		 * lock is dropped in finish_lock_switch.
-+		 */
-+		if (unlikely(p->wake_cpu != cpu))
-+			WRITE_ONCE(p->on_rq, TASK_ON_RQ_MIGRATING);
-+		else
-+#endif
-+			enqueue_task(rq, p, ENQUEUE_RESTORE);
-+	}
-+}
-+
-+/* Enter with rq lock held. We know p is on the local cpu */
-+static inline void __set_tsk_resched(struct task_struct *p)
-+{
-+	set_tsk_need_resched(p);
-+	set_preempt_need_resched();
-+}
-+
-+/**
-+ * task_curr - is this task currently executing on a CPU?
-+ * @p: the task in question.
-+ *
-+ * Return: 1 if the task is currently executing. 0 otherwise.
-+ */
-+inline int task_curr(const struct task_struct *p)
-+{
-+	return cpu_curr(task_cpu(p)) == p;
-+}
-+
-+#ifdef CONFIG_SMP
-+/*
-+ * wait_task_inactive - wait for a thread to unschedule.
-+ *
-+ * If @match_state is nonzero, it's the @p->state value just checked and
-+ * not expected to change.  If it changes, i.e. @p might have woken up,
-+ * then return zero.  When we succeed in waiting for @p to be off its CPU,
-+ * we return a positive number (its total switch count).  If a second call
-+ * a short while later returns the same number, the caller can be sure that
-+ * @p has remained unscheduled the whole time.
-+ *
-+ * The caller must ensure that the task *will* unschedule sometime soon,
-+ * else this function might spin for a *long* time. This function can't
-+ * be called with interrupts off, or it may introduce deadlock with
-+ * smp_call_function() if an IPI is sent by the same process we are
-+ * waiting to become inactive.
-+ */
-+unsigned long wait_task_inactive(struct task_struct *p, long match_state)
-+{
-+	int running, queued;
-+	struct rq_flags rf;
-+	unsigned long ncsw;
-+	struct rq *rq;
-+
-+	for (;;) {
-+		rq = task_rq(p);
-+
-+		/*
-+		 * If the task is actively running on another CPU
-+		 * still, just relax and busy-wait without holding
-+		 * any locks.
-+		 *
-+		 * NOTE! Since we don't hold any locks, it's not
-+		 * even sure that "rq" stays as the right runqueue!
-+		 * But we don't care, since this will return false
-+		 * if the runqueue has changed and p is actually now
-+		 * running somewhere else!
-+		 */
-+		while (task_running(rq, p)) {
-+			if (match_state && unlikely(p->state != match_state))
-+				return 0;
-+			cpu_relax();
-+		}
-+
-+		/*
-+		 * Ok, time to look more closely! We need the rq
-+		 * lock now, to be *sure*. If we're wrong, we'll
-+		 * just go back and repeat.
-+		 */
-+		rq = task_rq_lock(p, &rf);
-+		trace_sched_wait_task(p);
-+		running = task_running(rq, p);
-+		queued = task_on_rq_queued(p);
-+		ncsw = 0;
-+		if (!match_state || p->state == match_state)
-+			ncsw = p->nvcsw | LONG_MIN; /* sets MSB */
-+		task_rq_unlock(rq, p, &rf);
-+
-+		/*
-+		 * If it changed from the expected state, bail out now.
-+		 */
-+		if (unlikely(!ncsw))
-+			break;
-+
-+		/*
-+		 * Was it really running after all now that we
-+		 * checked with the proper locks actually held?
-+		 *
-+		 * Oops. Go back and try again..
-+		 */
-+		if (unlikely(running)) {
-+			cpu_relax();
-+			continue;
-+		}
-+
-+		/*
-+		 * It's not enough that it's not actively running,
-+		 * it must be off the runqueue _entirely_, and not
-+		 * preempted!
-+		 *
-+		 * So if it was still runnable (but just not actively
-+		 * running right now), it's preempted, and we should
-+		 * yield - it could be a while.
-+		 */
-+		if (unlikely(queued)) {
-+			ktime_t to = NSEC_PER_SEC / HZ;
-+
-+			set_current_state(TASK_UNINTERRUPTIBLE);
-+			schedule_hrtimeout(&to, HRTIMER_MODE_REL);
-+			continue;
-+		}
-+
-+		/*
-+		 * Ahh, all good. It wasn't running, and it wasn't
-+		 * runnable, which means that it will never become
-+		 * running in the future either. We're all done!
-+		 */
-+		break;
-+	}
-+
-+	return ncsw;
-+}
-+
-+/***
-+ * kick_process - kick a running thread to enter/exit the kernel
-+ * @p: the to-be-kicked thread
-+ *
-+ * Cause a process which is running on another CPU to enter
-+ * kernel-mode, without any delay. (to get signals handled.)
-+ *
-+ * NOTE: this function doesn't have to take the runqueue lock,
-+ * because all it wants to ensure is that the remote task enters
-+ * the kernel. If the IPI races and the task has been migrated
-+ * to another CPU then no harm is done and the purpose has been
-+ * achieved as well.
-+ */
-+void kick_process(struct task_struct *p)
-+{
-+	int cpu;
-+
-+	preempt_disable();
-+	cpu = task_cpu(p);
-+	if ((cpu != smp_processor_id()) && task_curr(p))
-+		smp_sched_reschedule(cpu);
-+	preempt_enable();
-+}
-+EXPORT_SYMBOL_GPL(kick_process);
-+#endif
-+
-+/*
-+ * RT tasks preempt purely on priority. SCHED_NORMAL tasks preempt on the
-+ * basis of earlier deadlines. SCHED_IDLEPRIO don't preempt anything else or
-+ * between themselves, they cooperatively multitask. An idle rq scores as
-+ * prio PRIO_LIMIT so it is always preempted.
-+ */
-+static inline bool
-+can_preempt(struct task_struct *p, int prio, u64 deadline)
-+{
-+	/* Better static priority RT task or better policy preemption */
-+	if (p->prio < prio)
-+		return true;
-+	if (p->prio > prio)
-+		return false;
-+	if (p->policy == SCHED_BATCH)
-+		return false;
-+	/* SCHED_NORMAL and ISO will preempt based on deadline */
-+	if (!deadline_before(p->deadline, deadline))
-+		return false;
-+	return true;
-+}
-+
-+#ifdef CONFIG_SMP
-+
-+static inline bool is_per_cpu_kthread(struct task_struct *p)
-+{
-+	if (!(p->flags & PF_KTHREAD))
-+		return false;
-+
-+	if (p->nr_cpus_allowed != 1)
-+		return false;
-+
-+	return true;
-+}
-+
-+/*
-+ * Per-CPU kthreads are allowed to run on !active && online CPUs, see
-+ * __set_cpus_allowed_ptr().
-+ */
-+static inline bool is_cpu_allowed(struct task_struct *p, int cpu)
-+{
-+	if (!cpumask_test_cpu(cpu, p->cpus_ptr))
-+		return false;
-+
-+	if (is_per_cpu_kthread(p))
-+		return cpu_online(cpu);
-+
-+	return cpu_active(cpu);
-+}
-+
-+/*
-+ * Check to see if p can run on cpu, and if not, whether there are any online
-+ * CPUs it can run on instead. This only happens with the hotplug threads that
-+ * bring up the CPUs.
-+ */
-+static inline bool sched_other_cpu(struct task_struct *p, int cpu)
-+{
-+	if (likely(cpumask_test_cpu(cpu, p->cpus_ptr)))
-+		return false;
-+	if (p->nr_cpus_allowed == 1) {
-+		cpumask_t valid_mask;
-+
-+		cpumask_and(&valid_mask, p->cpus_ptr, cpu_online_mask);
-+		if (unlikely(cpumask_empty(&valid_mask)))
-+			return false;
-+	}
-+	return true;
-+}
-+
-+static inline bool needs_other_cpu(struct task_struct *p, int cpu)
-+{
-+	if (cpumask_test_cpu(cpu, p->cpus_ptr))
-+		return false;
-+	return true;
-+}
-+
-+#define cpu_online_map		(*(cpumask_t *)cpu_online_mask)
-+
-+static void try_preempt(struct task_struct *p, struct rq *this_rq)
-+{
-+	int i, this_entries = rq_load(this_rq);
-+	cpumask_t tmp;
-+
-+	if (suitable_idle_cpus(p) && resched_best_idle(p, task_cpu(p)))
-+		return;
-+
-+	/* IDLEPRIO tasks never preempt anything but idle */
-+	if (p->policy == SCHED_IDLEPRIO)
-+		return;
-+
-+	cpumask_and(&tmp, &cpu_online_map, p->cpus_ptr);
-+
-+	for (i = 0; i < num_online_cpus(); i++) {
-+		struct rq *rq = this_rq->cpu_order[i];
-+
-+		if (!cpumask_test_cpu(rq->cpu, &tmp))
-+			continue;
-+
-+		if (!sched_interactive && rq != this_rq && rq_load(rq) <= this_entries)
-+			continue;
-+		if (smt_schedule(p, rq) && can_preempt(p, rq->rq_prio, rq->rq_deadline)) {
-+			/* We set rq->preempting lockless, it's a hint only */
-+			rq->preempting = p;
-+			resched_curr(rq);
-+			return;
-+		}
-+	}
-+}
-+
-+static int __set_cpus_allowed_ptr(struct task_struct *p,
-+				  const struct cpumask *new_mask, bool check);
-+#else /* CONFIG_SMP */
-+static inline bool needs_other_cpu(struct task_struct *p, int cpu)
-+{
-+	return false;
-+}
-+
-+static void try_preempt(struct task_struct *p, struct rq *this_rq)
-+{
-+	if (p->policy == SCHED_IDLEPRIO)
-+		return;
-+	if (can_preempt(p, uprq->rq_prio, uprq->rq_deadline))
-+		resched_curr(uprq);
-+}
-+
-+static inline int __set_cpus_allowed_ptr(struct task_struct *p,
-+					 const struct cpumask *new_mask, bool check)
-+{
-+	return set_cpus_allowed_ptr(p, new_mask);
-+}
-+#endif /* CONFIG_SMP */
-+
-+/*
-+ * wake flags
-+ */
-+#define WF_SYNC		0x01		/* waker goes to sleep after wakeup */
-+#define WF_FORK		0x02		/* child wakeup after fork */
-+#define WF_MIGRATED	0x04		/* internal use, task got migrated */
-+
-+static void
-+ttwu_stat(struct task_struct *p, int cpu, int wake_flags)
-+{
-+	struct rq *rq;
-+
-+	if (!schedstat_enabled())
-+		return;
-+
-+	rq = this_rq();
-+
-+#ifdef CONFIG_SMP
-+	if (cpu == rq->cpu) {
-+		__schedstat_inc(rq->ttwu_local);
-+	} else {
-+		struct sched_domain *sd;
-+
-+		rcu_read_lock();
-+		for_each_domain(rq->cpu, sd) {
-+			if (cpumask_test_cpu(cpu, sched_domain_span(sd))) {
-+				__schedstat_inc(sd->ttwu_wake_remote);
-+				break;
-+			}
-+		}
-+		rcu_read_unlock();
-+	}
-+
-+#endif /* CONFIG_SMP */
-+
-+	__schedstat_inc(rq->ttwu_count);
-+}
-+
-+/*
-+ * Mark the task runnable and perform wakeup-preemption.
-+ */
-+static void ttwu_do_wakeup(struct rq *rq, struct task_struct *p, int wake_flags)
-+{
-+	/*
-+	 * Sync wakeups (i.e. those types of wakeups where the waker
-+	 * has indicated that it will leave the CPU in short order)
-+	 * don't trigger a preemption if there are no idle cpus,
-+	 * instead waiting for current to deschedule.
-+	 */
-+	if (wake_flags & WF_SYNC)
-+		resched_suitable_idle(p);
-+	else
-+		try_preempt(p, rq);
-+	p->state = TASK_RUNNING;
-+	trace_sched_wakeup(p);
-+}
-+
-+static void
-+ttwu_do_activate(struct rq *rq, struct task_struct *p, int wake_flags)
-+{
-+	int en_flags = ENQUEUE_WAKEUP;
-+
-+	lockdep_assert_held(rq->lock);
-+
-+#ifdef CONFIG_SMP
-+	if (p->sched_contributes_to_load)
-+		rq->nr_uninterruptible--;
-+
-+	if (wake_flags & WF_MIGRATED)
-+		en_flags |= ENQUEUE_MIGRATED;
-+#endif
-+
-+	activate_task(rq, p, en_flags);
-+	ttwu_do_wakeup(rq, p, wake_flags);
-+}
-+
-+/*
-+ * Called in case the task @p isn't fully descheduled from its runqueue,
-+ * in this case we must do a remote wakeup. Its a 'light' wakeup though,
-+ * since all we need to do is flip p->state to TASK_RUNNING, since
-+ * the task is still ->on_rq.
-+ */
-+static int ttwu_remote(struct task_struct *p, int wake_flags)
-+{
-+	struct rq *rq;
-+	int ret = 0;
-+
-+	rq = __task_rq_lock(p, NULL);
-+	if (likely(task_on_rq_queued(p))) {
-+		ttwu_do_wakeup(rq, p, wake_flags);
-+		ret = 1;
-+	}
-+	__task_rq_unlock(rq, NULL);
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_SMP
-+void sched_ttwu_pending(void)
-+{
-+	struct rq *rq = this_rq();
-+	struct llist_node *llist = llist_del_all(&rq->wake_list);
-+	struct task_struct *p, *t;
-+	struct rq_flags rf;
-+
-+	if (!llist)
-+		return;
-+
-+	rq_lock_irqsave(rq, &rf);
-+
-+	llist_for_each_entry_safe(p, t, llist, wake_entry)
-+		ttwu_do_activate(rq, p, 0);
-+
-+	rq_unlock_irqrestore(rq, &rf);
-+}
-+
-+void scheduler_ipi(void)
-+{
-+	/*
-+	 * Fold TIF_NEED_RESCHED into the preempt_count; anybody setting
-+	 * TIF_NEED_RESCHED remotely (for the first time) will also send
-+	 * this IPI.
-+	 */
-+	preempt_fold_need_resched();
-+
-+	if (llist_empty(&this_rq()->wake_list) && (!idle_cpu(smp_processor_id()) || need_resched()))
-+		return;
-+
-+	/*
-+	 * Not all reschedule IPI handlers call irq_enter/irq_exit, since
-+	 * traditionally all their work was done from the interrupt return
-+	 * path. Now that we actually do some work, we need to make sure
-+	 * we do call them.
-+	 *
-+	 * Some archs already do call them, luckily irq_enter/exit nest
-+	 * properly.
-+	 *
-+	 * Arguably we should visit all archs and update all handlers,
-+	 * however a fair share of IPIs are still resched only so this would
-+	 * somewhat pessimize the simple resched case.
-+	 */
-+	irq_enter();
-+	sched_ttwu_pending();
-+	irq_exit();
-+}
-+
-+static void ttwu_queue_remote(struct task_struct *p, int cpu, int wake_flags)
-+{
-+	struct rq *rq = cpu_rq(cpu);
-+
-+	if (llist_add(&p->wake_entry, &cpu_rq(cpu)->wake_list)) {
-+		if (!set_nr_if_polling(rq->idle))
-+			smp_sched_reschedule(cpu);
-+		else
-+			trace_sched_wake_idle_without_ipi(cpu);
-+	}
-+}
-+
-+void wake_up_if_idle(int cpu)
-+{
-+	struct rq *rq = cpu_rq(cpu);
-+	struct rq_flags rf;
-+
-+	rcu_read_lock();
-+
-+	if (!is_idle_task(rcu_dereference(rq->curr)))
-+		goto out;
-+
-+	if (set_nr_if_polling(rq->idle)) {
-+		trace_sched_wake_idle_without_ipi(cpu);
-+	} else {
-+		rq_lock_irqsave(rq, &rf);
-+		if (likely(is_idle_task(rq->curr)))
-+			smp_sched_reschedule(cpu);
-+		/* Else cpu is not in idle, do nothing here */
-+		rq_unlock_irqrestore(rq, &rf);
-+	}
-+
-+out:
-+	rcu_read_unlock();
-+}
-+
-+static int valid_task_cpu(struct task_struct *p)
-+{
-+	cpumask_t valid_mask;
-+
-+	if (p->flags & PF_KTHREAD)
-+		cpumask_and(&valid_mask, p->cpus_ptr, cpu_all_mask);
-+	else
-+		cpumask_and(&valid_mask, p->cpus_ptr, cpu_active_mask);
-+
-+	if (unlikely(!cpumask_weight(&valid_mask))) {
-+		/* We shouldn't be hitting this any more */
-+		printk(KERN_WARNING "SCHED: No cpumask for %s/%d weight %d\n", p->comm,
-+		       p->pid, cpumask_weight(p->cpus_ptr));
-+		return cpumask_any(p->cpus_ptr);
-+	}
-+	return cpumask_any(&valid_mask);
-+}
-+
-+/*
-+ * For a task that's just being woken up we have a valuable balancing
-+ * opportunity so choose the nearest cache most lightly loaded runqueue.
-+ * Entered with rq locked and returns with the chosen runqueue locked.
-+ */
-+static inline int select_best_cpu(struct task_struct *p)
-+{
-+	unsigned int idlest = ~0U;
-+	struct rq *rq = NULL;
-+	int i;
-+
-+	if (suitable_idle_cpus(p)) {
-+		int cpu = task_cpu(p);
-+
-+		if (unlikely(needs_other_cpu(p, cpu)))
-+			cpu = valid_task_cpu(p);
-+		rq = resched_best_idle(p, cpu);
-+		if (likely(rq))
-+			return rq->cpu;
-+	}
-+
-+	for (i = 0; i < num_online_cpus(); i++) {
-+		struct rq *other_rq = task_rq(p)->cpu_order[i];
-+		int entries;
-+
-+		if (!other_rq->online)
-+			continue;
-+		if (needs_other_cpu(p, other_rq->cpu))
-+			continue;
-+		entries = rq_load(other_rq);
-+		if (entries >= idlest)
-+			continue;
-+		idlest = entries;
-+		rq = other_rq;
-+	}
-+	if (unlikely(!rq))
-+		return task_cpu(p);
-+	return rq->cpu;
-+}
-+#else /* CONFIG_SMP */
-+static int valid_task_cpu(struct task_struct *p)
-+{
-+	return 0;
-+}
-+
-+static inline int select_best_cpu(struct task_struct *p)
-+{
-+	return 0;
-+}
-+
-+static struct rq *resched_best_idle(struct task_struct *p, int cpu)
-+{
-+	return NULL;
-+}
-+#endif /* CONFIG_SMP */
-+
-+static void ttwu_queue(struct task_struct *p, int cpu, int wake_flags)
-+{
-+	struct rq *rq = cpu_rq(cpu);
-+
-+#if defined(CONFIG_SMP)
-+	if (!cpus_share_cache(smp_processor_id(), cpu)) {
-+		sched_clock_cpu(cpu); /* Sync clocks across CPUs */
-+		ttwu_queue_remote(p, cpu, wake_flags);
-+		return;
-+	}
-+#endif
-+	rq_lock(rq);
-+	ttwu_do_activate(rq, p, wake_flags);
-+	rq_unlock(rq);
-+}
-+
-+/***
-+ * try_to_wake_up - wake up a thread
-+ * @p: the thread to be awakened
-+ * @state: the mask of task states that can be woken
-+ * @wake_flags: wake modifier flags (WF_*)
-+ *
-+ * Put it on the run-queue if it's not already there. The "current"
-+ * thread is always on the run-queue (except when the actual
-+ * re-schedule is in progress), and as such you're allowed to do
-+ * the simpler "current->state = TASK_RUNNING" to mark yourself
-+ * runnable without the overhead of this.
-+ *
-+ * Return: %true if @p was woken up, %false if it was already running.
-+ * or @state didn't match @p's state.
-+ */
-+static int
-+try_to_wake_up(struct task_struct *p, unsigned int state, int wake_flags)
-+{
-+	unsigned long flags;
-+	int cpu, success = 0;
-+
-+	preempt_disable();
-+	if (p == current) {
-+		/*
-+		 * We're waking current, this means 'p->on_rq' and 'task_cpu(p)
-+		 * == smp_processor_id()'. Together this means we can special
-+		 * case the whole 'p->on_rq && ttwu_remote()' case below
-+		 * without taking any locks.
-+		 *
-+		 * In particular:
-+		 *  - we rely on Program-Order guarantees for all the ordering,
-+		 *  - we're serialized against set_special_state() by virtue of
-+		 *    it disabling IRQs (this allows not taking ->pi_lock).
-+		 */
-+		if (!(p->state & state))
-+			goto out;
-+
-+		success = 1;
-+		cpu = task_cpu(p);
-+		trace_sched_waking(p);
-+		p->state = TASK_RUNNING;
-+		trace_sched_wakeup(p);
-+		goto out;
-+	}
-+
-+	/*
-+	 * If we are going to wake up a thread waiting for CONDITION we
-+	 * need to ensure that CONDITION=1 done by the caller can not be
-+	 * reordered with p->state check below. This pairs with mb() in
-+	 * set_current_state() the waiting thread does.
-+	 */
-+	raw_spin_lock_irqsave(&p->pi_lock, flags);
-+	smp_mb__after_spinlock();
-+	if (!(p->state & state))
-+		goto unlock;
-+
-+	trace_sched_waking(p);
-+
-+	/* We're going to change ->state: */
-+	success = 1;
-+	cpu = task_cpu(p);
-+
-+	/*
-+	 * Ensure we load p->on_rq _after_ p->state, otherwise it would
-+	 * be possible to, falsely, observe p->on_rq == 0 and get stuck
-+	 * in smp_cond_load_acquire() below.
-+	 *
-+	 * sched_ttwu_pending()			try_to_wake_up()
-+	 *   STORE p->on_rq = 1			  LOAD p->state
-+	 *   UNLOCK rq->lock
-+	 *
-+	 * __schedule() (switch to task 'p')
-+	 *   LOCK rq->lock			  smp_rmb();
-+	 *   smp_mb__after_spinlock();
-+	 *   UNLOCK rq->lock
-+	 *
-+	 * [task p]
-+	 *   STORE p->state = UNINTERRUPTIBLE	  LOAD p->on_rq
-+	 *
-+	 * Pairs with the LOCK+smp_mb__after_spinlock() on rq->lock in
-+	 * __schedule().  See the comment for smp_mb__after_spinlock().
-+	 */
-+	smp_rmb();
-+	if (p->on_rq && ttwu_remote(p, wake_flags))
-+		goto unlock;
-+
-+#ifdef CONFIG_SMP
-+	/*
-+	 * Ensure we load p->on_cpu _after_ p->on_rq, otherwise it would be
-+	 * possible to, falsely, observe p->on_cpu == 0.
-+	 *
-+	 * One must be running (->on_cpu == 1) in order to remove oneself
-+	 * from the runqueue.
-+	 *
-+	 * __schedule() (switch to task 'p')	try_to_wake_up()
-+	 *   STORE p->on_cpu = 1		  LOAD p->on_rq
-+	 *   UNLOCK rq->lock
-+	 *
-+	 * __schedule() (put 'p' to sleep)
-+	 *   LOCK rq->lock			  smp_rmb();
-+	 *   smp_mb__after_spinlock();
-+	 *   STORE p->on_rq = 0			  LOAD p->on_cpu
-+	 *
-+	 * Pairs with the LOCK+smp_mb__after_spinlock() on rq->lock in
-+	 * __schedule().  See the comment for smp_mb__after_spinlock().
-+	 */
-+	smp_rmb();
-+
-+	/*
-+	 * If the owning (remote) CPU is still in the middle of schedule() with
-+	 * this task as prev, wait until its done referencing the task.
-+	 *
-+	 * Pairs with the smp_store_release() in finish_task().
-+	 *
-+	 * This ensures that tasks getting woken will be fully ordered against
-+	 * their previous state and preserve Program Order.
-+	 */
-+	smp_cond_load_acquire(&p->on_cpu, !VAL);
-+
-+	p->sched_contributes_to_load = !!task_contributes_to_load(p);
-+	p->state = TASK_WAKING;
-+
-+	if (p->in_iowait) {
-+		delayacct_blkio_end(p);
-+		atomic_dec(&task_rq(p)->nr_iowait);
-+	}
-+
-+	cpu = select_best_cpu(p);
-+	if (task_cpu(p) != cpu) {
-+		wake_flags |= WF_MIGRATED;
-+		psi_ttwu_dequeue(p);
-+		set_task_cpu(p, cpu);
-+	}
-+
-+#else /* CONFIG_SMP */
-+
-+	if (p->in_iowait) {
-+		delayacct_blkio_end(p);
-+		atomic_dec(&task_rq(p)->nr_iowait);
-+	}
-+
-+#endif /* CONFIG_SMP */
-+
-+	ttwu_queue(p, cpu, wake_flags);
-+unlock:
-+	raw_spin_unlock_irqrestore(&p->pi_lock, flags);
-+out:
-+	if (success)
-+		ttwu_stat(p, cpu, wake_flags);
-+	preempt_enable();
-+
-+	return success;
-+}
-+
-+/**
-+ * wake_up_process - Wake up a specific process
-+ * @p: The process to be woken up.
-+ *
-+ * Attempt to wake up the nominated process and move it to the set of runnable
-+ * processes.
-+ *
-+ * Return: 1 if the process was woken up, 0 if it was already running.
-+ *
-+ * This function executes a full memory barrier before accessing the task state.
-+ */
-+int wake_up_process(struct task_struct *p)
-+{
-+	return try_to_wake_up(p, TASK_NORMAL, 0);
-+}
-+EXPORT_SYMBOL(wake_up_process);
-+
-+int wake_up_state(struct task_struct *p, unsigned int state)
-+{
-+	return try_to_wake_up(p, state, 0);
-+}
-+
-+static void time_slice_expired(struct task_struct *p, struct rq *rq);
-+
-+/*
-+ * Perform scheduler related setup for a newly forked process p.
-+ * p is forked by current.
-+ */
-+int sched_fork(unsigned long __maybe_unused clone_flags, struct task_struct *p)
-+{
-+	unsigned long flags;
-+
-+#ifdef CONFIG_PREEMPT_NOTIFIERS
-+	INIT_HLIST_HEAD(&p->preempt_notifiers);
-+#endif
-+
-+#ifdef CONFIG_COMPACTION
-+	p->capture_control = NULL;
-+#endif
-+
-+	/*
-+	 * We mark the process as NEW here. This guarantees that
-+	 * nobody will actually run it, and a signal or other external
-+	 * event cannot wake it up and insert it on the runqueue either.
-+	 */
-+	p->state = TASK_NEW;
-+
-+	/*
-+	 * The process state is set to the same value of the process executing
-+	 * do_fork() code. That is running. This guarantees that nobody will
-+	 * actually run it, and a signal or other external event cannot wake
-+	 * it up and insert it on the runqueue either.
-+	 */
-+
-+	/* Should be reset in fork.c but done here for ease of MuQSS patching */
-+	p->on_cpu =
-+	p->on_rq =
-+	p->utime =
-+	p->stime =
-+	p->sched_time =
-+	p->stime_ns =
-+	p->utime_ns = 0;
-+	skiplist_node_init(&p->node);
-+
-+	/*
-+	 * Revert to default priority/policy on fork if requested.
-+	 */
-+	if (unlikely(p->sched_reset_on_fork)) {
-+		if (p->policy == SCHED_FIFO || p->policy == SCHED_RR) {
-+			p->policy = SCHED_NORMAL;
-+			p->normal_prio = normal_prio(p);
-+		}
-+
-+		if (PRIO_TO_NICE(p->static_prio) < 0) {
-+			p->static_prio = NICE_TO_PRIO(0);
-+			p->normal_prio = p->static_prio;
-+		}
-+
-+		/*
-+		 * We don't need the reset flag anymore after the fork. It has
-+		 * fulfilled its duty:
-+		 */
-+		p->sched_reset_on_fork = 0;
-+	}
-+
-+	/*
-+	 * Silence PROVE_RCU.
-+	 */
-+	raw_spin_lock_irqsave(&p->pi_lock, flags);
-+	set_task_cpu(p, smp_processor_id());
-+	raw_spin_unlock_irqrestore(&p->pi_lock, flags);
-+
-+#ifdef CONFIG_SCHED_INFO
-+	if (unlikely(sched_info_on()))
-+		memset(&p->sched_info, 0, sizeof(p->sched_info));
-+#endif
-+	init_task_preempt_count(p);
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_SCHEDSTATS
-+
-+DEFINE_STATIC_KEY_FALSE(sched_schedstats);
-+static bool __initdata __sched_schedstats = false;
-+
-+static void set_schedstats(bool enabled)
-+{
-+	if (enabled)
-+		static_branch_enable(&sched_schedstats);
-+	else
-+		static_branch_disable(&sched_schedstats);
-+}
-+
-+void force_schedstat_enabled(void)
-+{
-+	if (!schedstat_enabled()) {
-+		pr_info("kernel profiling enabled schedstats, disable via kernel.sched_schedstats.\n");
-+		static_branch_enable(&sched_schedstats);
-+	}
-+}
-+
-+static int __init setup_schedstats(char *str)
-+{
-+	int ret = 0;
-+	if (!str)
-+		goto out;
-+
-+	/*
-+	 * This code is called before jump labels have been set up, so we can't
-+	 * change the static branch directly just yet.  Instead set a temporary
-+	 * variable so init_schedstats() can do it later.
-+	 */
-+	if (!strcmp(str, "enable")) {
-+		__sched_schedstats = true;
-+		ret = 1;
-+	} else if (!strcmp(str, "disable")) {
-+		__sched_schedstats = false;
-+		ret = 1;
-+	}
-+out:
-+	if (!ret)
-+		pr_warn("Unable to parse schedstats=\n");
-+
-+	return ret;
-+}
-+__setup("schedstats=", setup_schedstats);
-+
-+static void __init init_schedstats(void)
-+{
-+	set_schedstats(__sched_schedstats);
-+}
-+
-+#ifdef CONFIG_PROC_SYSCTL
-+int sysctl_schedstats(struct ctl_table *table, int write,
-+			 void __user *buffer, size_t *lenp, loff_t *ppos)
-+{
-+	struct ctl_table t;
-+	int err;
-+	int state = static_branch_likely(&sched_schedstats);
-+
-+	if (write && !capable(CAP_SYS_ADMIN))
-+		return -EPERM;
-+
-+	t = *table;
-+	t.data = &state;
-+	err = proc_dointvec_minmax(&t, write, buffer, lenp, ppos);
-+	if (err < 0)
-+		return err;
-+	if (write)
-+		set_schedstats(state);
-+	return err;
-+}
-+#endif /* CONFIG_PROC_SYSCTL */
-+#else  /* !CONFIG_SCHEDSTATS */
-+static inline void init_schedstats(void) {}
-+#endif /* CONFIG_SCHEDSTATS */
-+
-+static void update_cpu_clock_switch(struct rq *rq, struct task_struct *p);
-+
-+static void account_task_cpu(struct rq *rq, struct task_struct *p)
-+{
-+	update_clocks(rq);
-+	/* This isn't really a context switch but accounting is the same */
-+	update_cpu_clock_switch(rq, p);
-+	p->last_ran = rq->niffies;
-+}
-+
-+bool sched_smp_initialized __read_mostly;
-+
-+static inline int hrexpiry_enabled(struct rq *rq)
-+{
-+	if (unlikely(!cpu_active(cpu_of(rq)) || !sched_smp_initialized))
-+		return 0;
-+	return hrtimer_is_hres_active(&rq->hrexpiry_timer);
-+}
-+
-+/*
-+ * Use HR-timers to deliver accurate preemption points.
-+ */
-+static inline void hrexpiry_clear(struct rq *rq)
-+{
-+	if (!hrexpiry_enabled(rq))
-+		return;
-+	if (hrtimer_active(&rq->hrexpiry_timer))
-+		hrtimer_cancel(&rq->hrexpiry_timer);
-+}
-+
-+/*
-+ * High-resolution time_slice expiry.
-+ * Runs from hardirq context with interrupts disabled.
-+ */
-+static enum hrtimer_restart hrexpiry(struct hrtimer *timer)
-+{
-+	struct rq *rq = container_of(timer, struct rq, hrexpiry_timer);
-+	struct task_struct *p;
-+
-+	/* This can happen during CPU hotplug / resume */
-+	if (unlikely(cpu_of(rq) != smp_processor_id()))
-+		goto out;
-+
-+	/*
-+	 * We're doing this without the runqueue lock but this should always
-+	 * be run on the local CPU. Time slice should run out in __schedule
-+	 * but we set it to zero here in case niffies is slightly less.
-+	 */
-+	p = rq->curr;
-+	p->time_slice = 0;
-+	__set_tsk_resched(p);
-+out:
-+	return HRTIMER_NORESTART;
-+}
-+
-+/*
-+ * Called to set the hrexpiry timer state.
-+ *
-+ * called with irqs disabled from the local CPU only
-+ */
-+static void hrexpiry_start(struct rq *rq, u64 delay)
-+{
-+	if (!hrexpiry_enabled(rq))
-+		return;
-+
-+	hrtimer_start(&rq->hrexpiry_timer, ns_to_ktime(delay),
-+		      HRTIMER_MODE_REL_PINNED);
-+}
-+
-+static void init_rq_hrexpiry(struct rq *rq)
-+{
-+	hrtimer_init(&rq->hrexpiry_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
-+	rq->hrexpiry_timer.function = hrexpiry;
-+}
-+
-+static inline int rq_dither(struct rq *rq)
-+{
-+	if (!hrexpiry_enabled(rq))
-+		return HALF_JIFFY_US;
-+	return 0;
-+}
-+
-+/*
-+ * wake_up_new_task - wake up a newly created task for the first time.
-+ *
-+ * This function will do some initial scheduler statistics housekeeping
-+ * that must be done for every newly created context, then puts the task
-+ * on the runqueue and wakes it.
-+ */
-+void wake_up_new_task(struct task_struct *p)
-+{
-+	struct task_struct *parent, *rq_curr;
-+	struct rq *rq, *new_rq;
-+	unsigned long flags;
-+
-+	parent = p->parent;
-+
-+	raw_spin_lock_irqsave(&p->pi_lock, flags);
-+	p->state = TASK_RUNNING;
-+	/* Task_rq can't change yet on a new task */
-+	new_rq = rq = task_rq(p);
-+	if (unlikely(needs_other_cpu(p, task_cpu(p)))) {
-+		set_task_cpu(p, valid_task_cpu(p));
-+		new_rq = task_rq(p);
-+	}
-+
-+	double_rq_lock(rq, new_rq);
-+	rq_curr = rq->curr;
-+
-+	/*
-+	 * Make sure we do not leak PI boosting priority to the child.
-+	 */
-+	p->prio = rq_curr->normal_prio;
-+
-+	trace_sched_wakeup_new(p);
-+
-+	/*
-+	 * Share the timeslice between parent and child, thus the
-+	 * total amount of pending timeslices in the system doesn't change,
-+	 * resulting in more scheduling fairness. If it's negative, it won't
-+	 * matter since that's the same as being 0. rq->rq_deadline is only
-+	 * modified within schedule() so it is always equal to
-+	 * current->deadline.
-+	 */
-+	account_task_cpu(rq, rq_curr);
-+	p->last_ran = rq_curr->last_ran;
-+	if (likely(rq_curr->policy != SCHED_FIFO)) {
-+		rq_curr->time_slice /= 2;
-+		if (rq_curr->time_slice < RESCHED_US) {
-+			/*
-+			 * Forking task has run out of timeslice. Reschedule it and
-+			 * start its child with a new time slice and deadline. The
-+			 * child will end up running first because its deadline will
-+			 * be slightly earlier.
-+			 */
-+			__set_tsk_resched(rq_curr);
-+			time_slice_expired(p, new_rq);
-+			if (suitable_idle_cpus(p))
-+				resched_best_idle(p, task_cpu(p));
-+			else if (unlikely(rq != new_rq))
-+				try_preempt(p, new_rq);
-+		} else {
-+			p->time_slice = rq_curr->time_slice;
-+			if (rq_curr == parent && rq == new_rq && !suitable_idle_cpus(p)) {
-+				/*
-+				 * The VM isn't cloned, so we're in a good position to
-+				 * do child-runs-first in anticipation of an exec. This
-+				 * usually avoids a lot of COW overhead.
-+				 */
-+				__set_tsk_resched(rq_curr);
-+			} else {
-+				/*
-+				 * Adjust the hrexpiry since rq_curr will keep
-+				 * running and its timeslice has been shortened.
-+				 */
-+				hrexpiry_start(rq, US_TO_NS(rq_curr->time_slice));
-+				try_preempt(p, new_rq);
-+			}
-+		}
-+	} else {
-+		time_slice_expired(p, new_rq);
-+		try_preempt(p, new_rq);
-+	}
-+	activate_task(new_rq, p, 0);
-+	double_rq_unlock(rq, new_rq);
-+	raw_spin_unlock_irqrestore(&p->pi_lock, flags);
-+}
-+
-+#ifdef CONFIG_PREEMPT_NOTIFIERS
-+
-+static DEFINE_STATIC_KEY_FALSE(preempt_notifier_key);
-+
-+void preempt_notifier_inc(void)
-+{
-+	static_branch_inc(&preempt_notifier_key);
-+}
-+EXPORT_SYMBOL_GPL(preempt_notifier_inc);
-+
-+void preempt_notifier_dec(void)
-+{
-+	static_branch_dec(&preempt_notifier_key);
-+}
-+EXPORT_SYMBOL_GPL(preempt_notifier_dec);
-+
-+/**
-+ * preempt_notifier_register - tell me when current is being preempted & rescheduled
-+ * @notifier: notifier struct to register
-+ */
-+void preempt_notifier_register(struct preempt_notifier *notifier)
-+{
-+	if (!static_branch_unlikely(&preempt_notifier_key))
-+		WARN(1, "registering preempt_notifier while notifiers disabled\n");
-+
-+	hlist_add_head(&notifier->link, &current->preempt_notifiers);
-+}
-+EXPORT_SYMBOL_GPL(preempt_notifier_register);
-+
-+/**
-+ * preempt_notifier_unregister - no longer interested in preemption notifications
-+ * @notifier: notifier struct to unregister
-+ *
-+ * This is *not* safe to call from within a preemption notifier.
-+ */
-+void preempt_notifier_unregister(struct preempt_notifier *notifier)
-+{
-+	hlist_del(&notifier->link);
-+}
-+EXPORT_SYMBOL_GPL(preempt_notifier_unregister);
-+
-+static void __fire_sched_in_preempt_notifiers(struct task_struct *curr)
-+{
-+	struct preempt_notifier *notifier;
-+
-+	hlist_for_each_entry(notifier, &curr->preempt_notifiers, link)
-+		notifier->ops->sched_in(notifier, raw_smp_processor_id());
-+}
-+
-+static __always_inline void fire_sched_in_preempt_notifiers(struct task_struct *curr)
-+{
-+	if (static_branch_unlikely(&preempt_notifier_key))
-+		__fire_sched_in_preempt_notifiers(curr);
-+}
-+
-+static void
-+__fire_sched_out_preempt_notifiers(struct task_struct *curr,
-+				 struct task_struct *next)
-+{
-+	struct preempt_notifier *notifier;
-+
-+	hlist_for_each_entry(notifier, &curr->preempt_notifiers, link)
-+		notifier->ops->sched_out(notifier, next);
-+}
-+
-+static __always_inline void
-+fire_sched_out_preempt_notifiers(struct task_struct *curr,
-+				 struct task_struct *next)
-+{
-+	if (static_branch_unlikely(&preempt_notifier_key))
-+		__fire_sched_out_preempt_notifiers(curr, next);
-+}
-+
-+#else /* !CONFIG_PREEMPT_NOTIFIERS */
-+
-+static inline void fire_sched_in_preempt_notifiers(struct task_struct *curr)
-+{
-+}
-+
-+static inline void
-+fire_sched_out_preempt_notifiers(struct task_struct *curr,
-+				 struct task_struct *next)
-+{
-+}
-+
-+#endif /* CONFIG_PREEMPT_NOTIFIERS */
-+
-+static inline void prepare_task(struct task_struct *next)
-+{
-+	/*
-+	 * Claim the task as running, we do this before switching to it
-+	 * such that any running task will have this set.
-+	 */
-+	next->on_cpu = 1;
-+}
-+
-+static inline void finish_task(struct task_struct *prev)
-+{
-+#ifdef CONFIG_SMP
-+	/*
-+	 * After ->on_cpu is cleared, the task can be moved to a different CPU.
-+	 * We must ensure this doesn't happen until the switch is completely
-+	 * finished.
-+	 *
-+	 * In particular, the load of prev->state in finish_task_switch() must
-+	 * happen before this.
-+	 *
-+	 * Pairs with the smp_cond_load_acquire() in try_to_wake_up().
-+	 */
-+	smp_store_release(&prev->on_cpu, 0);
-+#endif
-+}
-+
-+static inline void
-+prepare_lock_switch(struct rq *rq, struct task_struct *next)
-+{
-+	/*
-+	 * Since the runqueue lock will be released by the next
-+	 * task (which is an invalid locking op but in the case
-+	 * of the scheduler it's an obvious special-case), so we
-+	 * do an early lockdep release here:
-+	 */
-+	spin_release(&rq->lock->dep_map, 1, _THIS_IP_);
-+#ifdef CONFIG_DEBUG_SPINLOCK
-+	/* this is a valid case when another task releases the spinlock */
-+	rq->lock->owner = next;
-+#endif
-+}
-+
-+static inline void finish_lock_switch(struct rq *rq, struct task_struct *prev)
-+{
-+	/*
-+	 * If we are tracking spinlock dependencies then we have to
-+	 * fix up the runqueue lock - which gets 'carried over' from
-+	 * prev into current:
-+	 */
-+	spin_acquire(&rq->lock->dep_map, 0, 0, _THIS_IP_);
-+
-+#ifdef CONFIG_SMP
-+	/*
-+	 * If prev was marked as migrating to another CPU in return_task, drop
-+	 * the local runqueue lock but leave interrupts disabled and grab the
-+	 * remote lock we're migrating it to before enabling them.
-+	 */
-+	if (unlikely(task_on_rq_migrating(prev))) {
-+		sched_info_dequeued(rq, prev);
-+		/*
-+		 * We move the ownership of prev to the new cpu now. ttwu can't
-+		 * activate prev to the wrong cpu since it has to grab this
-+		 * runqueue in ttwu_remote.
-+		 */
-+#ifdef CONFIG_THREAD_INFO_IN_TASK
-+		prev->cpu = prev->wake_cpu;
-+#else
-+		task_thread_info(prev)->cpu = prev->wake_cpu;
-+#endif
-+		raw_spin_unlock(rq->lock);
-+
-+		raw_spin_lock(&prev->pi_lock);
-+		rq = __task_rq_lock(prev, NULL);
-+		/* Check that someone else hasn't already queued prev */
-+		if (likely(!task_queued(prev))) {
-+			enqueue_task(rq, prev, 0);
-+			prev->on_rq = TASK_ON_RQ_QUEUED;
-+			/* Wake up the CPU if it's not already running */
-+			resched_if_idle(rq);
-+		}
-+		raw_spin_unlock(&prev->pi_lock);
-+	}
-+#endif
-+	rq_unlock(rq);
-+
-+	do_pending_softirq(rq, current);
-+
-+	local_irq_enable();
-+}
-+
-+#ifndef prepare_arch_switch
-+# define prepare_arch_switch(next)	do { } while (0)
-+#endif
-+#ifndef finish_arch_switch
-+# define finish_arch_switch(prev)	do { } while (0)
-+#endif
-+#ifndef finish_arch_post_lock_switch
-+# define finish_arch_post_lock_switch()	do { } while (0)
-+#endif
-+
-+/**
-+ * prepare_task_switch - prepare to switch tasks
-+ * @rq: the runqueue preparing to switch
-+ * @next: the task we are going to switch to.
-+ *
-+ * This is called with the rq lock held and interrupts off. It must
-+ * be paired with a subsequent finish_task_switch after the context
-+ * switch.
-+ *
-+ * prepare_task_switch sets up locking and calls architecture specific
-+ * hooks.
-+ */
-+static inline void
-+prepare_task_switch(struct rq *rq, struct task_struct *prev,
-+		    struct task_struct *next)
-+{
-+	kcov_prepare_switch(prev);
-+	sched_info_switch(rq, prev, next);
-+	perf_event_task_sched_out(prev, next);
-+	rseq_preempt(prev);
-+	fire_sched_out_preempt_notifiers(prev, next);
-+	prepare_task(next);
-+	prepare_arch_switch(next);
-+}
-+
-+/**
-+ * finish_task_switch - clean up after a task-switch
-+ * @rq: runqueue associated with task-switch
-+ * @prev: the thread we just switched away from.
-+ *
-+ * finish_task_switch must be called after the context switch, paired
-+ * with a prepare_task_switch call before the context switch.
-+ * finish_task_switch will reconcile locking set up by prepare_task_switch,
-+ * and do any other architecture-specific cleanup actions.
-+ *
-+ * Note that we may have delayed dropping an mm in context_switch(). If
-+ * so, we finish that here outside of the runqueue lock.  (Doing it
-+ * with the lock held can cause deadlocks; see schedule() for
-+ * details.)
-+ *
-+ * The context switch have flipped the stack from under us and restored the
-+ * local variables which were saved when this task called schedule() in the
-+ * past. prev == current is still correct but we need to recalculate this_rq
-+ * because prev may have moved to another CPU.
-+ */
-+static void finish_task_switch(struct task_struct *prev)
-+	__releases(rq->lock)
-+{
-+	struct rq *rq = this_rq();
-+	struct mm_struct *mm = rq->prev_mm;
-+	long prev_state;
-+
-+	/*
-+	 * The previous task will have left us with a preempt_count of 2
-+	 * because it left us after:
-+	 *
-+	 *	schedule()
-+	 *	  preempt_disable();			// 1
-+	 *	  __schedule()
-+	 *	    raw_spin_lock_irq(rq->lock)	// 2
-+	 *
-+	 * Also, see FORK_PREEMPT_COUNT.
-+	 */
-+	if (WARN_ONCE(preempt_count() != 2*PREEMPT_DISABLE_OFFSET,
-+		      "corrupted preempt_count: %s/%d/0x%x\n",
-+		      current->comm, current->pid, preempt_count()))
-+		preempt_count_set(FORK_PREEMPT_COUNT);
-+
-+	rq->prev_mm = NULL;
-+
-+	/*
-+	 * A task struct has one reference for the use as "current".
-+	 * If a task dies, then it sets TASK_DEAD in tsk->state and calls
-+	 * schedule one last time. The schedule call will never return, and
-+	 * the scheduled task must drop that reference.
-+	 *
-+	 * We must observe prev->state before clearing prev->on_cpu (in
-+	 * finish_task), otherwise a concurrent wakeup can get prev
-+	 * running on another CPU and we could rave with its RUNNING -> DEAD
-+	 * transition, resulting in a double drop.
-+	 */
-+	prev_state = prev->state;
-+	vtime_task_switch(prev);
-+	perf_event_task_sched_in(prev, current);
-+	finish_task(prev);
-+	finish_lock_switch(rq, prev);
-+	finish_arch_post_lock_switch();
-+	kcov_finish_switch(current);
-+
-+	fire_sched_in_preempt_notifiers(current);
-+	/*
-+	 * When switching through a kernel thread, the loop in
-+	 * membarrier_{private,global}_expedited() may have observed that
-+	 * kernel thread and not issued an IPI. It is therefore possible to
-+	 * schedule between user->kernel->user threads without passing though
-+	 * switch_mm(). Membarrier requires a barrier after storing to
-+	 * rq->curr, before returning to userspace, so provide them here:
-+	 *
-+	 * - a full memory barrier for {PRIVATE,GLOBAL}_EXPEDITED, implicitly
-+	 *   provided by mmdrop(),
-+	 * - a sync_core for SYNC_CORE.
-+	 */
-+	if (mm) {
-+		membarrier_mm_sync_core_before_usermode(mm);
-+		mmdrop(mm);
-+	}
-+	if (unlikely(prev_state == TASK_DEAD)) {
-+		/*
-+		 * Remove function-return probe instances associated with this
-+		 * task and put them back on the free list.
-+		 */
-+		kprobe_flush_task(prev);
-+
-+		/* Task is done with its stack. */
-+		put_task_stack(prev);
-+
-+		put_task_struct_rcu_user(prev);
-+	}
-+}
-+
-+/**
-+ * schedule_tail - first thing a freshly forked thread must call.
-+ * @prev: the thread we just switched away from.
-+ */
-+asmlinkage __visible void schedule_tail(struct task_struct *prev)
-+{
-+	/*
-+	 * New tasks start with FORK_PREEMPT_COUNT, see there and
-+	 * finish_task_switch() for details.
-+	 *
-+	 * finish_task_switch() will drop rq->lock() and lower preempt_count
-+	 * and the preempt_enable() will end up enabling preemption (on
-+	 * PREEMPT_COUNT kernels).
-+	 */
-+
-+	finish_task_switch(prev);
-+	preempt_enable();
-+
-+	if (current->set_child_tid)
-+		put_user(task_pid_vnr(current), current->set_child_tid);
-+
-+	calculate_sigpending();
-+}
-+
-+/*
-+ * context_switch - switch to the new MM and the new thread's register state.
-+ */
-+static __always_inline void
-+context_switch(struct rq *rq, struct task_struct *prev,
-+	       struct task_struct *next)
-+{
-+	prepare_task_switch(rq, prev, next);
-+
-+	/*
-+	 * For paravirt, this is coupled with an exit in switch_to to
-+	 * combine the page table reload and the switch backend into
-+	 * one hypercall.
-+	 */
-+	arch_start_context_switch(prev);
-+
-+	/*
-+	 * kernel -> kernel   lazy + transfer active
-+	 *   user -> kernel   lazy + mmgrab() active
-+	 *
-+	 * kernel ->   user   switch + mmdrop() active
-+	 *   user ->   user   switch
-+	 */
-+	if (!next->mm) {                                // to kernel
-+		enter_lazy_tlb(prev->active_mm, next);
-+
-+		next->active_mm = prev->active_mm;
-+		if (prev->mm)                           // from user
-+			mmgrab(prev->active_mm);
-+		else
-+			prev->active_mm = NULL;
-+	} else {                                        // to user
-+		membarrier_switch_mm(rq, prev->active_mm, next->mm);
-+		/*
-+		 * sys_membarrier() requires an smp_mb() between setting
-+		 * rq->curr / membarrier_switch_mm() and returning to userspace.
-+		 *
-+		 * The below provides this either through switch_mm(), or in
-+		 * case 'prev->active_mm == next->mm' through
-+		 * finish_task_switch()'s mmdrop().
-+		 */
-+		switch_mm_irqs_off(prev->active_mm, next->mm, next);
-+
-+		if (!prev->mm) {                        // from kernel
-+			/* will mmdrop() in finish_task_switch(). */
-+			rq->prev_mm = prev->active_mm;
-+			prev->active_mm = NULL;
-+		}
-+	}
-+	prepare_lock_switch(rq, next);
-+
-+	/* Here we just switch the register state and the stack. */
-+	switch_to(prev, next, prev);
-+	barrier();
-+
-+	finish_task_switch(prev);
-+}
-+
-+/*
-+ * nr_running, nr_uninterruptible and nr_context_switches:
-+ *
-+ * externally visible scheduler statistics: current number of runnable
-+ * threads, total number of context switches performed since bootup.
-+ */
-+unsigned long nr_running(void)
-+{
-+	unsigned long i, sum = 0;
-+
-+	for_each_online_cpu(i)
-+		sum += cpu_rq(i)->nr_running;
-+
-+	return sum;
-+}
-+
-+static unsigned long nr_uninterruptible(void)
-+{
-+	unsigned long i, sum = 0;
-+
-+	for_each_online_cpu(i)
-+		sum += cpu_rq(i)->nr_uninterruptible;
-+
-+	return sum;
-+}
-+
-+/*
-+ * Check if only the current task is running on the CPU.
-+ *
-+ * Caution: this function does not check that the caller has disabled
-+ * preemption, thus the result might have a time-of-check-to-time-of-use
-+ * race.  The caller is responsible to use it correctly, for example:
-+ *
-+ * - from a non-preemptible section (of course)
-+ *
-+ * - from a thread that is bound to a single CPU
-+ *
-+ * - in a loop with very short iterations (e.g. a polling loop)
-+ */
-+bool single_task_running(void)
-+{
-+	if (rq_load(raw_rq()) == 1)
-+		return true;
-+	else
-+		return false;
-+}
-+EXPORT_SYMBOL(single_task_running);
-+
-+unsigned long long nr_context_switches(void)
-+{
-+	int cpu;
-+	unsigned long long sum = 0;
-+
-+	for_each_possible_cpu(cpu)
-+		sum += cpu_rq(cpu)->nr_switches;
-+
-+	return sum;
-+}
-+
-+/*
-+ * Consumers of these two interfaces, like for example the cpufreq menu
-+ * governor are using nonsensical data. Boosting frequency for a CPU that has
-+ * IO-wait which might not even end up running the task when it does become
-+ * runnable.
-+ */
-+
-+unsigned long nr_iowait_cpu(int cpu)
-+{
-+	return atomic_read(&cpu_rq(cpu)->nr_iowait);
-+}
-+
-+/*
-+ * IO-wait accounting, and how its mostly bollocks (on SMP).
-+ *
-+ * The idea behind IO-wait account is to account the idle time that we could
-+ * have spend running if it were not for IO. That is, if we were to improve the
-+ * storage performance, we'd have a proportional reduction in IO-wait time.
-+ *
-+ * This all works nicely on UP, where, when a task blocks on IO, we account
-+ * idle time as IO-wait, because if the storage were faster, it could've been
-+ * running and we'd not be idle.
-+ *
-+ * This has been extended to SMP, by doing the same for each CPU. This however
-+ * is broken.
-+ *
-+ * Imagine for instance the case where two tasks block on one CPU, only the one
-+ * CPU will have IO-wait accounted, while the other has regular idle. Even
-+ * though, if the storage were faster, both could've ran at the same time,
-+ * utilising both CPUs.
-+ *
-+ * This means, that when looking globally, the current IO-wait accounting on
-+ * SMP is a lower bound, by reason of under accounting.
-+ *
-+ * Worse, since the numbers are provided per CPU, they are sometimes
-+ * interpreted per CPU, and that is nonsensical. A blocked task isn't strictly
-+ * associated with any one particular CPU, it can wake to another CPU than it
-+ * blocked on. This means the per CPU IO-wait number is meaningless.
-+ *
-+ * Task CPU affinities can make all that even more 'interesting'.
-+ */
-+
-+unsigned long nr_iowait(void)
-+{
-+	unsigned long cpu, sum = 0;
-+
-+	for_each_possible_cpu(cpu)
-+		sum += nr_iowait_cpu(cpu);
-+
-+	return sum;
-+}
-+
-+unsigned long nr_active(void)
-+{
-+	return nr_running() + nr_uninterruptible();
-+}
-+
-+/* Variables and functions for calc_load */
-+static unsigned long calc_load_update;
-+unsigned long avenrun[3];
-+EXPORT_SYMBOL(avenrun);
-+
-+/**
-+ * get_avenrun - get the load average array
-+ * @loads:	pointer to dest load array
-+ * @offset:	offset to add
-+ * @shift:	shift count to shift the result left
-+ *
-+ * These values are estimates at best, so no need for locking.
-+ */
-+void get_avenrun(unsigned long *loads, unsigned long offset, int shift)
-+{
-+	loads[0] = (avenrun[0] + offset) << shift;
-+	loads[1] = (avenrun[1] + offset) << shift;
-+	loads[2] = (avenrun[2] + offset) << shift;
-+}
-+
-+/*
-+ * calc_load - update the avenrun load estimates every LOAD_FREQ seconds.
-+ */
-+void calc_global_load(unsigned long ticks)
-+{
-+	long active;
-+
-+	if (time_before(jiffies, READ_ONCE(calc_load_update)))
-+		return;
-+	active = nr_active() * FIXED_1;
-+
-+	avenrun[0] = calc_load(avenrun[0], EXP_1, active);
-+	avenrun[1] = calc_load(avenrun[1], EXP_5, active);
-+	avenrun[2] = calc_load(avenrun[2], EXP_15, active);
-+
-+	calc_load_update = jiffies + LOAD_FREQ;
-+}
-+
-+/**
-+ * fixed_power_int - compute: x^n, in O(log n) time
-+ *
-+ * @x:         base of the power
-+ * @frac_bits: fractional bits of @x
-+ * @n:         power to raise @x to.
-+ *
-+ * By exploiting the relation between the definition of the natural power
-+ * function: x^n := x*x*...*x (x multiplied by itself for n times), and
-+ * the binary encoding of numbers used by computers: n := \Sum n_i * 2^i,
-+ * (where: n_i \elem {0, 1}, the binary vector representing n),
-+ * we find: x^n := x^(\Sum n_i * 2^i) := \Prod x^(n_i * 2^i), which is
-+ * of course trivially computable in O(log_2 n), the length of our binary
-+ * vector.
-+ */
-+static unsigned long
-+fixed_power_int(unsigned long x, unsigned int frac_bits, unsigned int n)
-+{
-+	unsigned long result = 1UL << frac_bits;
-+
-+	if (n) {
-+		for (;;) {
-+			if (n & 1) {
-+				result *= x;
-+				result += 1UL << (frac_bits - 1);
-+				result >>= frac_bits;
-+			}
-+			n >>= 1;
-+			if (!n)
-+				break;
-+			x *= x;
-+			x += 1UL << (frac_bits - 1);
-+			x >>= frac_bits;
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+/*
-+ * a1 = a0 * e + a * (1 - e)
-+ *
-+ * a2 = a1 * e + a * (1 - e)
-+ *    = (a0 * e + a * (1 - e)) * e + a * (1 - e)
-+ *    = a0 * e^2 + a * (1 - e) * (1 + e)
-+ *
-+ * a3 = a2 * e + a * (1 - e)
-+ *    = (a0 * e^2 + a * (1 - e) * (1 + e)) * e + a * (1 - e)
-+ *    = a0 * e^3 + a * (1 - e) * (1 + e + e^2)
-+ *
-+ *  ...
-+ *
-+ * an = a0 * e^n + a * (1 - e) * (1 + e + ... + e^n-1) [1]
-+ *    = a0 * e^n + a * (1 - e) * (1 - e^n)/(1 - e)
-+ *    = a0 * e^n + a * (1 - e^n)
-+ *
-+ * [1] application of the geometric series:
-+ *
-+ *              n         1 - x^(n+1)
-+ *     S_n := \Sum x^i = -------------
-+ *             i=0          1 - x
-+ */
-+unsigned long
-+calc_load_n(unsigned long load, unsigned long exp,
-+	    unsigned long active, unsigned int n)
-+{
-+	return calc_load(load, fixed_power_int(exp, FSHIFT, n), active);
-+}
-+
-+DEFINE_PER_CPU(struct kernel_stat, kstat);
-+DEFINE_PER_CPU(struct kernel_cpustat, kernel_cpustat);
-+
-+EXPORT_PER_CPU_SYMBOL(kstat);
-+EXPORT_PER_CPU_SYMBOL(kernel_cpustat);
-+
-+#ifdef CONFIG_PARAVIRT
-+static inline u64 steal_ticks(u64 steal)
-+{
-+	if (unlikely(steal > NSEC_PER_SEC))
-+		return div_u64(steal, TICK_NSEC);
-+
-+	return __iter_div_u64_rem(steal, TICK_NSEC, &steal);
-+}
-+#endif
-+
-+#ifndef nsecs_to_cputime
-+# define nsecs_to_cputime(__nsecs)	nsecs_to_jiffies(__nsecs)
-+#endif
-+
-+/*
-+ * On each tick, add the number of nanoseconds to the unbanked variables and
-+ * once one tick's worth has accumulated, account it allowing for accurate
-+ * sub-tick accounting and totals. Use the TICK_APPROX_NS to match the way we
-+ * deduct nanoseconds.
-+ */
-+static void pc_idle_time(struct rq *rq, struct task_struct *idle, unsigned long ns)
-+{
-+	u64 *cpustat = kcpustat_this_cpu->cpustat;
-+	unsigned long ticks;
-+
-+	if (atomic_read(&rq->nr_iowait) > 0) {
-+		rq->iowait_ns += ns;
-+		if (rq->iowait_ns >= JIFFY_NS) {
-+			ticks = NS_TO_JIFFIES(rq->iowait_ns);
-+			cpustat[CPUTIME_IOWAIT] += (__force u64)TICK_APPROX_NS * ticks;
-+			rq->iowait_ns %= JIFFY_NS;
-+		}
-+	} else {
-+		rq->idle_ns += ns;
-+		if (rq->idle_ns >= JIFFY_NS) {
-+			ticks = NS_TO_JIFFIES(rq->idle_ns);
-+			cpustat[CPUTIME_IDLE] += (__force u64)TICK_APPROX_NS * ticks;
-+			rq->idle_ns %= JIFFY_NS;
-+		}
-+	}
-+	acct_update_integrals(idle);
-+}
-+
-+static void pc_system_time(struct rq *rq, struct task_struct *p,
-+			   int hardirq_offset, unsigned long ns)
-+{
-+	u64 *cpustat = kcpustat_this_cpu->cpustat;
-+	unsigned long ticks;
-+
-+	p->stime_ns += ns;
-+	if (p->stime_ns >= JIFFY_NS) {
-+		ticks = NS_TO_JIFFIES(p->stime_ns);
-+		p->stime_ns %= JIFFY_NS;
-+		p->stime += (__force u64)TICK_APPROX_NS * ticks;
-+		account_group_system_time(p, TICK_APPROX_NS * ticks);
-+	}
-+	p->sched_time += ns;
-+	account_group_exec_runtime(p, ns);
-+
-+	if (hardirq_count() - hardirq_offset) {
-+		rq->irq_ns += ns;
-+		if (rq->irq_ns >= JIFFY_NS) {
-+			ticks = NS_TO_JIFFIES(rq->irq_ns);
-+			cpustat[CPUTIME_IRQ] += (__force u64)TICK_APPROX_NS * ticks;
-+			rq->irq_ns %= JIFFY_NS;
-+		}
-+	} else if (in_serving_softirq()) {
-+		rq->softirq_ns += ns;
-+		if (rq->softirq_ns >= JIFFY_NS) {
-+			ticks = NS_TO_JIFFIES(rq->softirq_ns);
-+			cpustat[CPUTIME_SOFTIRQ] += (__force u64)TICK_APPROX_NS * ticks;
-+			rq->softirq_ns %= JIFFY_NS;
-+		}
-+	} else {
-+		rq->system_ns += ns;
-+		if (rq->system_ns >= JIFFY_NS) {
-+			ticks = NS_TO_JIFFIES(rq->system_ns);
-+			cpustat[CPUTIME_SYSTEM] += (__force u64)TICK_APPROX_NS * ticks;
-+			rq->system_ns %= JIFFY_NS;
-+		}
-+	}
-+	acct_update_integrals(p);
-+}
-+
-+static void pc_user_time(struct rq *rq, struct task_struct *p, unsigned long ns)
-+{
-+	u64 *cpustat = kcpustat_this_cpu->cpustat;
-+	unsigned long ticks;
-+
-+	p->utime_ns += ns;
-+	if (p->utime_ns >= JIFFY_NS) {
-+		ticks = NS_TO_JIFFIES(p->utime_ns);
-+		p->utime_ns %= JIFFY_NS;
-+		p->utime += (__force u64)TICK_APPROX_NS * ticks;
-+		account_group_user_time(p, TICK_APPROX_NS * ticks);
-+	}
-+	p->sched_time += ns;
-+	account_group_exec_runtime(p, ns);
-+
-+	if (this_cpu_ksoftirqd() == p) {
-+		/*
-+		 * ksoftirqd time do not get accounted in cpu_softirq_time.
-+		 * So, we have to handle it separately here.
-+		 */
-+		rq->softirq_ns += ns;
-+		if (rq->softirq_ns >= JIFFY_NS) {
-+			ticks = NS_TO_JIFFIES(rq->softirq_ns);
-+			cpustat[CPUTIME_SOFTIRQ] += (__force u64)TICK_APPROX_NS * ticks;
-+			rq->softirq_ns %= JIFFY_NS;
-+		}
-+	}
-+
-+	if (task_nice(p) > 0 || idleprio_task(p)) {
-+		rq->nice_ns += ns;
-+		if (rq->nice_ns >= JIFFY_NS) {
-+			ticks = NS_TO_JIFFIES(rq->nice_ns);
-+			cpustat[CPUTIME_NICE] += (__force u64)TICK_APPROX_NS * ticks;
-+			rq->nice_ns %= JIFFY_NS;
-+		}
-+	} else {
-+		rq->user_ns += ns;
-+		if (rq->user_ns >= JIFFY_NS) {
-+			ticks = NS_TO_JIFFIES(rq->user_ns);
-+			cpustat[CPUTIME_USER] += (__force u64)TICK_APPROX_NS * ticks;
-+			rq->user_ns %= JIFFY_NS;
-+		}
-+	}
-+	acct_update_integrals(p);
-+}
-+
-+/*
-+ * This is called on clock ticks.
-+ * Bank in p->sched_time the ns elapsed since the last tick or switch.
-+ * CPU scheduler quota accounting is also performed here in microseconds.
-+ */
-+static void update_cpu_clock_tick(struct rq *rq, struct task_struct *p)
-+{
-+	s64 account_ns = rq->niffies - p->last_ran;
-+	struct task_struct *idle = rq->idle;
-+
-+	/* Accurate tick timekeeping */
-+	if (user_mode(get_irq_regs()))
-+		pc_user_time(rq, p, account_ns);
-+	else if (p != idle || (irq_count() != HARDIRQ_OFFSET)) {
-+		pc_system_time(rq, p, HARDIRQ_OFFSET, account_ns);
-+	} else
-+		pc_idle_time(rq, idle, account_ns);
-+
-+	/* time_slice accounting is done in usecs to avoid overflow on 32bit */
-+	if (p->policy != SCHED_FIFO && p != idle)
-+		p->time_slice -= NS_TO_US(account_ns);
-+
-+	p->last_ran = rq->niffies;
-+}
-+
-+/*
-+ * This is called on context switches.
-+ * Bank in p->sched_time the ns elapsed since the last tick or switch.
-+ * CPU scheduler quota accounting is also performed here in microseconds.
-+ */
-+static void update_cpu_clock_switch(struct rq *rq, struct task_struct *p)
-+{
-+	s64 account_ns = rq->niffies - p->last_ran;
-+	struct task_struct *idle = rq->idle;
-+
-+	/* Accurate subtick timekeeping */
-+	if (p != idle)
-+		pc_user_time(rq, p, account_ns);
-+	else
-+		pc_idle_time(rq, idle, account_ns);
-+
-+	/* time_slice accounting is done in usecs to avoid overflow on 32bit */
-+	if (p->policy != SCHED_FIFO && p != idle)
-+		p->time_slice -= NS_TO_US(account_ns);
-+}
-+
-+/*
-+ * Return any ns on the sched_clock that have not yet been accounted in
-+ * @p in case that task is currently running.
-+ *
-+ * Called with task_rq_lock(p) held.
-+ */
-+static inline u64 do_task_delta_exec(struct task_struct *p, struct rq *rq)
-+{
-+	u64 ns = 0;
-+
-+	/*
-+	 * Must be ->curr _and_ ->on_rq.  If dequeued, we would
-+	 * project cycles that may never be accounted to this
-+	 * thread, breaking clock_gettime().
-+	 */
-+	if (p == rq->curr && task_on_rq_queued(p)) {
-+		update_clocks(rq);
-+		ns = rq->niffies - p->last_ran;
-+	}
-+
-+	return ns;
-+}
-+
-+/*
-+ * Return accounted runtime for the task.
-+ * Return separately the current's pending runtime that have not been
-+ * accounted yet.
-+ *
-+ */
-+unsigned long long task_sched_runtime(struct task_struct *p)
-+{
-+	struct rq_flags rf;
-+	struct rq *rq;
-+	u64 ns;
-+
-+#if defined(CONFIG_64BIT) && defined(CONFIG_SMP)
-+	/*
-+	 * 64-bit doesn't need locks to atomically read a 64-bit value.
-+	 * So we have a optimisation chance when the task's delta_exec is 0.
-+	 * Reading ->on_cpu is racy, but this is ok.
-+	 *
-+	 * If we race with it leaving CPU, we'll take a lock. So we're correct.
-+	 * If we race with it entering CPU, unaccounted time is 0. This is
-+	 * indistinguishable from the read occurring a few cycles earlier.
-+	 * If we see ->on_cpu without ->on_rq, the task is leaving, and has
-+	 * been accounted, so we're correct here as well.
-+	 */
-+	if (!p->on_cpu || !task_on_rq_queued(p))
-+		return tsk_seruntime(p);
-+#endif
-+
-+	rq = task_rq_lock(p, &rf);
-+	ns = p->sched_time + do_task_delta_exec(p, rq);
-+	task_rq_unlock(rq, p, &rf);
-+
-+	return ns;
-+}
-+
-+/*
-+ * Functions to test for when SCHED_ISO tasks have used their allocated
-+ * quota as real time scheduling and convert them back to SCHED_NORMAL. All
-+ * data is modified only by the local runqueue during scheduler_tick with
-+ * interrupts disabled.
-+ */
-+
-+/*
-+ * Test if SCHED_ISO tasks have run longer than their alloted period as RT
-+ * tasks and set the refractory flag if necessary. There is 10% hysteresis
-+ * for unsetting the flag. 115/128 is ~90/100 as a fast shift instead of a
-+ * slow division.
-+ */
-+static inline void iso_tick(struct rq *rq)
-+{
-+	rq->iso_ticks = rq->iso_ticks * (ISO_PERIOD - 1) / ISO_PERIOD;
-+	rq->iso_ticks += 100;
-+	if (rq->iso_ticks > ISO_PERIOD * sched_iso_cpu) {
-+		rq->iso_refractory = true;
-+		if (unlikely(rq->iso_ticks > ISO_PERIOD * 100))
-+			rq->iso_ticks = ISO_PERIOD * 100;
-+	}
-+}
-+
-+/* No SCHED_ISO task was running so decrease rq->iso_ticks */
-+static inline void no_iso_tick(struct rq *rq, int ticks)
-+{
-+	if (rq->iso_ticks > 0 || rq->iso_refractory) {
-+		rq->iso_ticks = rq->iso_ticks * (ISO_PERIOD - ticks) / ISO_PERIOD;
-+		if (rq->iso_ticks < ISO_PERIOD * (sched_iso_cpu * 115 / 128)) {
-+			rq->iso_refractory = false;
-+			if (unlikely(rq->iso_ticks < 0))
-+				rq->iso_ticks = 0;
-+		}
-+	}
-+}
-+
-+/* This manages tasks that have run out of timeslice during a scheduler_tick */
-+static void task_running_tick(struct rq *rq)
-+{
-+	struct task_struct *p = rq->curr;
-+
-+	/*
-+	 * If a SCHED_ISO task is running we increment the iso_ticks. In
-+	 * order to prevent SCHED_ISO tasks from causing starvation in the
-+	 * presence of true RT tasks we account those as iso_ticks as well.
-+	 */
-+	if (rt_task(p) || task_running_iso(p))
-+		iso_tick(rq);
-+	else
-+		no_iso_tick(rq, 1);
-+
-+	/* SCHED_FIFO tasks never run out of timeslice. */
-+	if (p->policy == SCHED_FIFO)
-+		return;
-+
-+	if (iso_task(p)) {
-+		if (task_running_iso(p)) {
-+			if (rq->iso_refractory) {
-+				/*
-+				 * SCHED_ISO task is running as RT and limit
-+				 * has been hit. Force it to reschedule as
-+				 * SCHED_NORMAL by zeroing its time_slice
-+				 */
-+				p->time_slice = 0;
-+			}
-+		} else if (!rq->iso_refractory) {
-+			/* Can now run again ISO. Reschedule to pick up prio */
-+			goto out_resched;
-+		}
-+	}
-+
-+	/*
-+	 * Tasks that were scheduled in the first half of a tick are not
-+	 * allowed to run into the 2nd half of the next tick if they will
-+	 * run out of time slice in the interim. Otherwise, if they have
-+	 * less than RESCHED_US μs of time slice left they will be rescheduled.
-+	 * Dither is used as a backup for when hrexpiry is disabled or high res
-+	 * timers not configured in.
-+	 */
-+	if (p->time_slice - rq->dither >= RESCHED_US)
-+		return;
-+out_resched:
-+	rq_lock(rq);
-+	__set_tsk_resched(p);
-+	rq_unlock(rq);
-+}
-+
-+static inline void task_tick(struct rq *rq)
-+{
-+	if (!rq_idle(rq))
-+		task_running_tick(rq);
-+	else if (rq->last_jiffy > rq->last_scheduler_tick)
-+		no_iso_tick(rq, rq->last_jiffy - rq->last_scheduler_tick);
-+}
-+
-+#ifdef CONFIG_NO_HZ_FULL
-+/*
-+ * We can stop the timer tick any time highres timers are active since
-+ * we rely entirely on highres timeouts for task expiry rescheduling.
-+ */
-+static void sched_stop_tick(struct rq *rq, int cpu)
-+{
-+	if (!hrexpiry_enabled(rq))
-+		return;
-+	if (!tick_nohz_full_enabled())
-+		return;
-+	if (!tick_nohz_full_cpu(cpu))
-+		return;
-+	tick_nohz_dep_clear_cpu(cpu, TICK_DEP_BIT_SCHED);
-+}
-+
-+static inline void sched_start_tick(struct rq *rq, int cpu)
-+{
-+	tick_nohz_dep_set_cpu(cpu, TICK_DEP_BIT_SCHED);
-+}
-+
-+struct tick_work {
-+	int			cpu;
-+	atomic_t		state;
-+	struct delayed_work	work;
-+};
-+/* Values for ->state, see diagram below. */
-+#define TICK_SCHED_REMOTE_OFFLINE	0
-+#define TICK_SCHED_REMOTE_OFFLINING	1
-+#define TICK_SCHED_REMOTE_RUNNING	2
-+
-+/*
-+ * State diagram for ->state:
-+ *
-+ *
-+ *          TICK_SCHED_REMOTE_OFFLINE
-+ *                    |   ^
-+ *                    |   |
-+ *                    |   | sched_tick_remote()
-+ *                    |   |
-+ *                    |   |
-+ *                    +--TICK_SCHED_REMOTE_OFFLINING
-+ *                    |   ^
-+ *                    |   |
-+ * sched_tick_start() |   | sched_tick_stop()
-+ *                    |   |
-+ *                    V   |
-+ *          TICK_SCHED_REMOTE_RUNNING
-+ *
-+ *
-+ * Other transitions get WARN_ON_ONCE(), except that sched_tick_remote()
-+ * and sched_tick_start() are happy to leave the state in RUNNING.
-+ */
-+
-+static struct tick_work __percpu *tick_work_cpu;
-+
-+static void sched_tick_remote(struct work_struct *work)
-+{
-+	struct delayed_work *dwork = to_delayed_work(work);
-+	struct tick_work *twork = container_of(dwork, struct tick_work, work);
-+	int cpu = twork->cpu;
-+	struct rq *rq = cpu_rq(cpu);
-+	struct task_struct *curr;
-+	u64 delta;
-+	int os;
-+
-+	/*
-+	 * Handle the tick only if it appears the remote CPU is running in full
-+	 * dynticks mode. The check is racy by nature, but missing a tick or
-+	 * having one too much is no big deal because the scheduler tick updates
-+	 * statistics and checks timeslices in a time-independent way, regardless
-+	 * of when exactly it is running.
-+	 */
-+	if (idle_cpu(cpu) || !tick_nohz_tick_stopped_cpu(cpu))
-+		goto out_requeue;
-+
-+	rq_lock_irq(rq);
-+	curr = rq->curr;
-+	if (is_idle_task(curr) || cpu_is_offline(cpu))
-+		goto out_unlock;
-+
-+	update_rq_clock(rq);
-+	delta = rq_clock_task(rq) - curr->last_ran;
-+
-+	/*
-+	 * Make sure the next tick runs within a reasonable
-+	 * amount of time.
-+	 */
-+	WARN_ON_ONCE(delta > (u64)NSEC_PER_SEC * 3);
-+	task_tick(rq);
-+
-+out_unlock:
-+	rq_unlock_irq(rq, NULL);
-+
-+out_requeue:
-+	/*
-+	 * Run the remote tick once per second (1Hz). This arbitrary
-+	 * frequency is large enough to avoid overload but short enough
-+	 * to keep scheduler internal stats reasonably up to date.  But
-+	 * first update state to reflect hotplug activity if required.
-+	 */
-+	os = atomic_fetch_add_unless(&twork->state, -1, TICK_SCHED_REMOTE_RUNNING);
-+	WARN_ON_ONCE(os == TICK_SCHED_REMOTE_OFFLINE);
-+	if (os == TICK_SCHED_REMOTE_RUNNING)
-+		queue_delayed_work(system_unbound_wq, dwork, HZ);
-+}
-+
-+static void sched_tick_start(int cpu)
-+{
-+	struct tick_work *twork;
-+	int os;
-+
-+	if (housekeeping_cpu(cpu, HK_FLAG_TICK))
-+		return;
-+
-+	WARN_ON_ONCE(!tick_work_cpu);
-+
-+	twork = per_cpu_ptr(tick_work_cpu, cpu);
-+	os = atomic_xchg(&twork->state, TICK_SCHED_REMOTE_RUNNING);
-+	WARN_ON_ONCE(os == TICK_SCHED_REMOTE_RUNNING);
-+	if (os == TICK_SCHED_REMOTE_OFFLINE) {
-+		twork->cpu = cpu;
-+		INIT_DELAYED_WORK(&twork->work, sched_tick_remote);
-+		queue_delayed_work(system_unbound_wq, &twork->work, HZ);
-+	}
-+}
-+
-+#ifdef CONFIG_HOTPLUG_CPU
-+static void sched_tick_stop(int cpu)
-+{
-+	struct tick_work *twork;
-+	int os;
-+
-+	if (housekeeping_cpu(cpu, HK_FLAG_TICK))
-+		return;
-+
-+	WARN_ON_ONCE(!tick_work_cpu);
-+
-+	twork = per_cpu_ptr(tick_work_cpu, cpu);
-+	/* There cannot be competing actions, but don't rely on stop-machine. */
-+	os = atomic_xchg(&twork->state, TICK_SCHED_REMOTE_OFFLINING);
-+	WARN_ON_ONCE(os != TICK_SCHED_REMOTE_RUNNING);
-+	/* Don't cancel, as this would mess up the state machine. */
-+}
-+#endif /* CONFIG_HOTPLUG_CPU */
-+
-+int __init sched_tick_offload_init(void)
-+{
-+	tick_work_cpu = alloc_percpu(struct tick_work);
-+	BUG_ON(!tick_work_cpu);
-+	return 0;
-+}
-+
-+#else /* !CONFIG_NO_HZ_FULL */
-+static inline void sched_stop_tick(struct rq *rq, int cpu) {}
-+static inline void sched_start_tick(struct rq *rq, int cpu) {}
-+static inline void sched_tick_start(int cpu) { }
-+static inline void sched_tick_stop(int cpu) { }
-+#endif
-+
-+/*
-+ * This function gets called by the timer code, with HZ frequency.
-+ * We call it with interrupts disabled.
-+ */
-+void scheduler_tick(void)
-+{
-+	int cpu __maybe_unused = smp_processor_id();
-+	struct rq *rq = cpu_rq(cpu);
-+
-+	sched_clock_tick();
-+	update_clocks(rq);
-+	update_load_avg(rq, 0);
-+	update_cpu_clock_tick(rq, rq->curr);
-+	task_tick(rq);
-+	rq->last_scheduler_tick = rq->last_jiffy;
-+	rq->last_tick = rq->clock;
-+	psi_task_tick(rq);
-+	perf_event_task_tick();
-+	sched_stop_tick(rq, cpu);
-+}
-+
-+#if defined(CONFIG_PREEMPTION) && (defined(CONFIG_DEBUG_PREEMPT) || \
-+				defined(CONFIG_TRACE_PREEMPT_TOGGLE))
-+/*
-+ * If the value passed in is equal to the current preempt count
-+ * then we just disabled preemption. Start timing the latency.
-+ */
-+static inline void preempt_latency_start(int val)
-+{
-+	if (preempt_count() == val) {
-+		unsigned long ip = get_lock_parent_ip();
-+#ifdef CONFIG_DEBUG_PREEMPT
-+		current->preempt_disable_ip = ip;
-+#endif
-+		trace_preempt_off(CALLER_ADDR0, ip);
-+	}
-+}
-+
-+void preempt_count_add(int val)
-+{
-+#ifdef CONFIG_DEBUG_PREEMPT
-+	/*
-+	 * Underflow?
-+	 */
-+	if (DEBUG_LOCKS_WARN_ON((preempt_count() < 0)))
-+		return;
-+#endif
-+	__preempt_count_add(val);
-+#ifdef CONFIG_DEBUG_PREEMPT
-+	/*
-+	 * Spinlock count overflowing soon?
-+	 */
-+	DEBUG_LOCKS_WARN_ON((preempt_count() & PREEMPT_MASK) >=
-+				PREEMPT_MASK - 10);
-+#endif
-+	preempt_latency_start(val);
-+}
-+EXPORT_SYMBOL(preempt_count_add);
-+NOKPROBE_SYMBOL(preempt_count_add);
-+
-+/*
-+ * If the value passed in equals to the current preempt count
-+ * then we just enabled preemption. Stop timing the latency.
-+ */
-+static inline void preempt_latency_stop(int val)
-+{
-+	if (preempt_count() == val)
-+		trace_preempt_on(CALLER_ADDR0, get_lock_parent_ip());
-+}
-+
-+void preempt_count_sub(int val)
-+{
-+#ifdef CONFIG_DEBUG_PREEMPT
-+	/*
-+	 * Underflow?
-+	 */
-+	if (DEBUG_LOCKS_WARN_ON(val > preempt_count()))
-+		return;
-+	/*
-+	 * Is the spinlock portion underflowing?
-+	 */
-+	if (DEBUG_LOCKS_WARN_ON((val < PREEMPT_MASK) &&
-+			!(preempt_count() & PREEMPT_MASK)))
-+		return;
-+#endif
-+
-+	preempt_latency_stop(val);
-+	__preempt_count_sub(val);
-+}
-+EXPORT_SYMBOL(preempt_count_sub);
-+NOKPROBE_SYMBOL(preempt_count_sub);
-+
-+#else
-+static inline void preempt_latency_start(int val) { }
-+static inline void preempt_latency_stop(int val) { }
-+#endif
-+
-+static inline unsigned long get_preempt_disable_ip(struct task_struct *p)
-+{
-+#ifdef CONFIG_DEBUG_PREEMPT
-+	return p->preempt_disable_ip;
-+#else
-+	return 0;
-+#endif
-+}
-+
-+/*
-+ * The time_slice is only refilled when it is empty and that is when we set a
-+ * new deadline. Make sure update_clocks has been called recently to update
-+ * rq->niffies.
-+ */
-+static void time_slice_expired(struct task_struct *p, struct rq *rq)
-+{
-+	p->time_slice = timeslice();
-+	p->deadline = rq->niffies + task_deadline_diff(p);
-+#ifdef CONFIG_SMT_NICE
-+	if (!p->mm)
-+		p->smt_bias = 0;
-+	else if (rt_task(p))
-+		p->smt_bias = 1 << 30;
-+	else if (task_running_iso(p))
-+		p->smt_bias = 1 << 29;
-+	else if (idleprio_task(p)) {
-+		if (task_running_idle(p))
-+			p->smt_bias = 0;
-+		else
-+			p->smt_bias = 1;
-+	} else if (--p->smt_bias < 1)
-+		p->smt_bias = MAX_PRIO - p->static_prio;
-+#endif
-+}
-+
-+/*
-+ * Timeslices below RESCHED_US are considered as good as expired as there's no
-+ * point rescheduling when there's so little time left. SCHED_BATCH tasks
-+ * have been flagged be not latency sensitive and likely to be fully CPU
-+ * bound so every time they're rescheduled they have their time_slice
-+ * refilled, but get a new later deadline to have little effect on
-+ * SCHED_NORMAL tasks.
-+
-+ */
-+static inline void check_deadline(struct task_struct *p, struct rq *rq)
-+{
-+	if (p->time_slice < RESCHED_US || batch_task(p))
-+		time_slice_expired(p, rq);
-+}
-+
-+/*
-+ * Task selection with skiplists is a simple matter of picking off the first
-+ * task in the sorted list, an O(1) operation. The lookup is amortised O(1)
-+ * being bound to the number of processors.
-+ *
-+ * Runqueues are selectively locked based on their unlocked data and then
-+ * unlocked if not needed. At most 3 locks will be held at any time and are
-+ * released as soon as they're no longer needed. All balancing between CPUs
-+ * is thus done here in an extremely simple first come best fit manner.
-+ *
-+ * This iterates over runqueues in cache locality order. In interactive mode
-+ * it iterates over all CPUs and finds the task with the best key/deadline.
-+ * In non-interactive mode it will only take a task if it's from the current
-+ * runqueue or a runqueue with more tasks than the current one with a better
-+ * key/deadline.
-+ */
-+#ifdef CONFIG_SMP
-+static inline struct task_struct
-+*earliest_deadline_task(struct rq *rq, int cpu, struct task_struct *idle)
-+{
-+	struct rq *locked = NULL, *chosen = NULL;
-+	struct task_struct *edt = idle;
-+	int i, best_entries = 0;
-+	u64 best_key = ~0ULL;
-+
-+	for (i = 0; i < total_runqueues; i++) {
-+		struct rq *other_rq = rq_order(rq, i);
-+		skiplist_node *next;
-+		int entries;
-+
-+		entries = other_rq->sl->entries;
-+		/*
-+		 * Check for queued entres lockless first. The local runqueue
-+		 * is locked so entries will always be accurate.
-+		 */
-+		if (!sched_interactive) {
-+			/*
-+			 * Don't reschedule balance across nodes unless the CPU
-+			 * is idle.
-+			 */
-+			if (edt != idle && rq->cpu_locality[other_rq->cpu] > LOCALITY_SMP)
-+				break;
-+			if (entries <= best_entries)
-+				continue;
-+		} else if (!entries)
-+			continue;
-+
-+		/* if (i) implies other_rq != rq */
-+		if (i) {
-+			/* Check for best id queued lockless first */
-+			if (other_rq->best_key >= best_key)
-+				continue;
-+
-+			if (unlikely(!trylock_rq(rq, other_rq)))
-+				continue;
-+
-+			/* Need to reevaluate entries after locking */
-+			entries = other_rq->sl->entries;
-+			if (unlikely(!entries)) {
-+				unlock_rq(other_rq);
-+				continue;
-+			}
-+		}
-+
-+		next = other_rq->node;
-+		/*
-+		 * In interactive mode we check beyond the best entry on other
-+		 * runqueues if we can't get the best for smt or affinity
-+		 * reasons.
-+		 */
-+		while ((next = next->next[0]) != other_rq->node) {
-+			struct task_struct *p;
-+			u64 key = next->key;
-+
-+			/* Reevaluate key after locking */
-+			if (key >= best_key)
-+				break;
-+
-+			p = next->value;
-+			if (!smt_schedule(p, rq)) {
-+				if (i && !sched_interactive)
-+					break;
-+				continue;
-+			}
-+
-+			if (sched_other_cpu(p, cpu)) {
-+				if (sched_interactive || !i)
-+					continue;
-+				break;
-+			}
-+			/* Make sure affinity is ok */
-+			if (i) {
-+				/* From this point on p is the best so far */
-+				if (locked)
-+					unlock_rq(locked);
-+				chosen = locked = other_rq;
-+			}
-+			best_entries = entries;
-+			best_key = key;
-+			edt = p;
-+			break;
-+		}
-+		/* rq->preempting is a hint only as the state may have changed
-+		 * since it was set with the resched call but if we have met
-+		 * the condition we can break out here. */
-+		if (edt == rq->preempting)
-+			break;
-+		if (i && other_rq != chosen)
-+			unlock_rq(other_rq);
-+	}
-+
-+	if (likely(edt != idle))
-+		take_task(rq, cpu, edt);
-+
-+	if (locked)
-+		unlock_rq(locked);
-+
-+	rq->preempting = NULL;
-+
-+	return edt;
-+}
-+#else /* CONFIG_SMP */
-+static inline struct task_struct
-+*earliest_deadline_task(struct rq *rq, int cpu, struct task_struct *idle)
-+{
-+	struct task_struct *edt;
-+
-+	if (unlikely(!rq->sl->entries))
-+		return idle;
-+	edt = rq->node->next[0]->value;
-+	take_task(rq, cpu, edt);
-+	return edt;
-+}
-+#endif /* CONFIG_SMP */
-+
-+/*
-+ * Print scheduling while atomic bug:
-+ */
-+static noinline void __schedule_bug(struct task_struct *prev)
-+{
-+	/* Save this before calling printk(), since that will clobber it */
-+	unsigned long preempt_disable_ip = get_preempt_disable_ip(current);
-+
-+	if (oops_in_progress)
-+		return;
-+
-+	printk(KERN_ERR "BUG: scheduling while atomic: %s/%d/0x%08x\n",
-+		prev->comm, prev->pid, preempt_count());
-+
-+	debug_show_held_locks(prev);
-+	print_modules();
-+	if (irqs_disabled())
-+		print_irqtrace_events(prev);
-+	if (IS_ENABLED(CONFIG_DEBUG_PREEMPT)
-+	    && in_atomic_preempt_off()) {
-+		pr_err("Preemption disabled at:");
-+		print_ip_sym(preempt_disable_ip);
-+		pr_cont("\n");
-+	}
-+	dump_stack();
-+	add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
-+}
-+
-+/*
-+ * Various schedule()-time debugging checks and statistics:
-+ */
-+static inline void schedule_debug(struct task_struct *prev, bool preempt)
-+{
-+#ifdef CONFIG_SCHED_STACK_END_CHECK
-+	if (task_stack_end_corrupted(prev))
-+		panic("corrupted stack end detected inside scheduler\n");
-+#endif
-+
-+#ifdef CONFIG_DEBUG_ATOMIC_SLEEP
-+	if (!preempt && prev->state && prev->non_block_count) {
-+		printk(KERN_ERR "BUG: scheduling in a non-blocking section: %s/%d/%i\n",
-+			prev->comm, prev->pid, prev->non_block_count);
-+		dump_stack();
-+		add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
-+	}
-+#endif
-+
-+	if (unlikely(in_atomic_preempt_off())) {
-+		__schedule_bug(prev);
-+		preempt_count_set(PREEMPT_DISABLED);
-+	}
-+	rcu_sleep_check();
-+
-+	profile_hit(SCHED_PROFILING, __builtin_return_address(0));
-+
-+	schedstat_inc(this_rq()->sched_count);
-+}
-+
-+/*
-+ * The currently running task's information is all stored in rq local data
-+ * which is only modified by the local CPU.
-+ */
-+static inline void set_rq_task(struct rq *rq, struct task_struct *p)
-+{
-+	if (p == rq->idle || p->policy == SCHED_FIFO)
-+		hrexpiry_clear(rq);
-+	else
-+		hrexpiry_start(rq, US_TO_NS(p->time_slice));
-+	if (rq->clock - rq->last_tick > HALF_JIFFY_NS)
-+		rq->dither = 0;
-+	else
-+		rq->dither = rq_dither(rq);
-+
-+	rq->rq_deadline = p->deadline;
-+	rq->rq_prio = p->prio;
-+#ifdef CONFIG_SMT_NICE
-+	rq->rq_mm = p->mm;
-+	rq->rq_smt_bias = p->smt_bias;
-+#endif
-+}
-+
-+#ifdef CONFIG_SMT_NICE
-+static void check_no_siblings(struct rq __maybe_unused *this_rq) {}
-+static void wake_no_siblings(struct rq __maybe_unused *this_rq) {}
-+static void (*check_siblings)(struct rq *this_rq) = &check_no_siblings;
-+static void (*wake_siblings)(struct rq *this_rq) = &wake_no_siblings;
-+
-+/* Iterate over smt siblings when we've scheduled a process on cpu and decide
-+ * whether they should continue running or be descheduled. */
-+static void check_smt_siblings(struct rq *this_rq)
-+{
-+	int other_cpu;
-+
-+	for_each_cpu(other_cpu, &this_rq->thread_mask) {
-+		struct task_struct *p;
-+		struct rq *rq;
-+
-+		rq = cpu_rq(other_cpu);
-+		if (rq_idle(rq))
-+			continue;
-+		p = rq->curr;
-+		if (!smt_schedule(p, this_rq))
-+			resched_curr(rq);
-+	}
-+}
-+
-+static void wake_smt_siblings(struct rq *this_rq)
-+{
-+	int other_cpu;
-+
-+	for_each_cpu(other_cpu, &this_rq->thread_mask) {
-+		struct rq *rq;
-+
-+		rq = cpu_rq(other_cpu);
-+		if (rq_idle(rq))
-+			resched_idle(rq);
-+	}
-+}
-+#else
-+static void check_siblings(struct rq __maybe_unused *this_rq) {}
-+static void wake_siblings(struct rq __maybe_unused *this_rq) {}
-+#endif
-+
-+/*
-+ * schedule() is the main scheduler function.
-+ *
-+ * The main means of driving the scheduler and thus entering this function are:
-+ *
-+ *   1. Explicit blocking: mutex, semaphore, waitqueue, etc.
-+ *
-+ *   2. TIF_NEED_RESCHED flag is checked on interrupt and userspace return
-+ *      paths. For example, see arch/x86/entry_64.S.
-+ *
-+ *      To drive preemption between tasks, the scheduler sets the flag in timer
-+ *      interrupt handler scheduler_tick().
-+ *
-+ *   3. Wakeups don't really cause entry into schedule(). They add a
-+ *      task to the run-queue and that's it.
-+ *
-+ *      Now, if the new task added to the run-queue preempts the current
-+ *      task, then the wakeup sets TIF_NEED_RESCHED and schedule() gets
-+ *      called on the nearest possible occasion:
-+ *
-+ *       - If the kernel is preemptible (CONFIG_PREEMPTION=y):
-+ *
-+ *         - in syscall or exception context, at the next outmost
-+ *           preempt_enable(). (this might be as soon as the wake_up()'s
-+ *           spin_unlock()!)
-+ *
-+ *         - in IRQ context, return from interrupt-handler to
-+ *           preemptible context
-+ *
-+ *       - If the kernel is not preemptible (CONFIG_PREEMPTION is not set)
-+ *         then at the next:
-+ *
-+ *          - cond_resched() call
-+ *          - explicit schedule() call
-+ *          - return from syscall or exception to user-space
-+ *          - return from interrupt-handler to user-space
-+ *
-+ * WARNING: must be called with preemption disabled!
-+ */
-+static void __sched notrace __schedule(bool preempt)
-+{
-+	struct task_struct *prev, *next, *idle;
-+	unsigned long *switch_count;
-+	bool deactivate = false;
-+	struct rq *rq;
-+	u64 niffies;
-+	int cpu;
-+
-+	cpu = smp_processor_id();
-+	rq = cpu_rq(cpu);
-+	prev = rq->curr;
-+	idle = rq->idle;
-+
-+	schedule_debug(prev, preempt);
-+
-+	local_irq_disable();
-+	rcu_note_context_switch(preempt);
-+
-+	/*
-+	 * Make sure that signal_pending_state()->signal_pending() below
-+	 * can't be reordered with __set_current_state(TASK_INTERRUPTIBLE)
-+	 * done by the caller to avoid the race with signal_wake_up().
-+	 *
-+	 * The membarrier system call requires a full memory barrier
-+	 * after coming from user-space, before storing to rq->curr.
-+	 */
-+	rq_lock(rq);
-+	smp_mb__after_spinlock();
-+#ifdef CONFIG_SMP
-+	if (rq->preempt) {
-+		/*
-+		 * Make sure resched_curr hasn't triggered a preemption
-+		 * locklessly on a task that has since scheduled away. Spurious
-+		 * wakeup of idle is okay though.
-+		 */
-+		if (unlikely(preempt && prev != idle && !test_tsk_need_resched(prev))) {
-+			rq->preempt = NULL;
-+			clear_preempt_need_resched();
-+			rq_unlock_irq(rq, NULL);
-+			return;
-+		}
-+		rq->preempt = NULL;
-+	}
-+#endif
-+
-+	switch_count = &prev->nivcsw;
-+	if (!preempt && prev->state) {
-+		if (signal_pending_state(prev->state, prev)) {
-+			prev->state = TASK_RUNNING;
-+		} else {
-+			deactivate = true;
-+
-+			if (prev->in_iowait) {
-+				atomic_inc(&rq->nr_iowait);
-+				delayacct_blkio_start();
-+			}
-+		}
-+		switch_count = &prev->nvcsw;
-+	}
-+
-+	/*
-+	 * Store the niffy value here for use by the next task's last_ran
-+	 * below to avoid losing niffies due to update_clocks being called
-+	 * again after this point.
-+	 */
-+	update_clocks(rq);
-+	niffies = rq->niffies;
-+	update_cpu_clock_switch(rq, prev);
-+
-+	clear_tsk_need_resched(prev);
-+	clear_preempt_need_resched();
-+
-+	if (idle != prev) {
-+		check_deadline(prev, rq);
-+		return_task(prev, rq, cpu, deactivate);
-+	}
-+
-+	next = earliest_deadline_task(rq, cpu, idle);
-+	if (likely(next->prio != PRIO_LIMIT))
-+		clear_cpuidle_map(cpu);
-+	else {
-+		set_cpuidle_map(cpu);
-+		update_load_avg(rq, 0);
-+	}
-+
-+	set_rq_task(rq, next);
-+	next->last_ran = niffies;
-+
-+	if (likely(prev != next)) {
-+		/*
-+		 * Don't reschedule an idle task or deactivated tasks
-+		 */
-+		if (prev == idle) {
-+			rq->nr_running++;
-+			if (rt_task(next))
-+				rq->rt_nr_running++;
-+		} else if (!deactivate)
-+			resched_suitable_idle(prev);
-+		if (unlikely(next == idle)) {
-+			rq->nr_running--;
-+			if (rt_task(prev))
-+				rq->rt_nr_running--;
-+			wake_siblings(rq);
-+		} else
-+			check_siblings(rq);
-+		rq->nr_switches++;
-+		/*
-+		 * RCU users of rcu_dereference(rq->curr) may not see
-+		 * changes to task_struct made by pick_next_task().
-+		 */
-+		RCU_INIT_POINTER(rq->curr, next);
-+		/*
-+		 * The membarrier system call requires each architecture
-+		 * to have a full memory barrier after updating
-+		 * rq->curr, before returning to user-space.
-+		 *
-+		 * Here are the schemes providing that barrier on the
-+		 * various architectures:
-+		 * - mm ? switch_mm() : mmdrop() for x86, s390, sparc, PowerPC.
-+		 *   switch_mm() rely on membarrier_arch_switch_mm() on PowerPC.
-+		 * - finish_lock_switch() for weakly-ordered
-+		 *   architectures where spin_unlock is a full barrier,
-+		 * - switch_to() for arm64 (weakly-ordered, spin_unlock
-+		 *   is a RELEASE barrier),
-+		 */
-+		++*switch_count;
-+
-+		trace_sched_switch(preempt, prev, next);
-+		context_switch(rq, prev, next); /* unlocks the rq */
-+	} else {
-+		check_siblings(rq);
-+		rq_unlock(rq);
-+		do_pending_softirq(rq, next);
-+		local_irq_enable();
-+	}
-+}
-+
-+void __noreturn do_task_dead(void)
-+{
-+	/* Causes final put_task_struct in finish_task_switch(). */
-+	set_special_state(TASK_DEAD);
-+
-+	/* Tell freezer to ignore us: */
-+	current->flags |= PF_NOFREEZE;
-+	__schedule(false);
-+	BUG();
-+
-+	/* Avoid "noreturn function does return" - but don't continue if BUG() is a NOP: */
-+	for (;;)
-+		cpu_relax();
-+}
-+
-+static inline void sched_submit_work(struct task_struct *tsk)
-+{
-+	if (!tsk->state)
-+		return;
-+
-+	/*
-+	 * If a worker went to sleep, notify and ask workqueue whether
-+	 * it wants to wake up a task to maintain concurrency.
-+	 * As this function is called inside the schedule() context,
-+	 * we disable preemption to avoid it calling schedule() again
-+	 * in the possible wakeup of a kworker.
-+	 */
-+	if (tsk->flags & PF_WQ_WORKER) {
-+		preempt_disable();
-+		wq_worker_sleeping(tsk);
-+		preempt_enable_no_resched();
-+	}
-+
-+	if (tsk_is_pi_blocked(tsk))
-+		return;
-+
-+	/*
-+	 * If we are going to sleep and we have plugged IO queued,
-+	 * make sure to submit it to avoid deadlocks.
-+	 */
-+	if (blk_needs_flush_plug(tsk))
-+		blk_schedule_flush_plug(tsk);
-+}
-+
-+static inline void sched_update_worker(struct task_struct *tsk)
-+{
-+	if (tsk->flags & PF_WQ_WORKER)
-+		wq_worker_running(tsk);
-+}
-+
-+asmlinkage __visible void __sched schedule(void)
-+{
-+	struct task_struct *tsk = current;
-+
-+	sched_submit_work(tsk);
-+	do {
-+		preempt_disable();
-+		__schedule(false);
-+		sched_preempt_enable_no_resched();
-+	} while (need_resched());
-+	sched_update_worker(tsk);
-+}
-+
-+EXPORT_SYMBOL(schedule);
-+
-+/*
-+ * synchronize_rcu_tasks() makes sure that no task is stuck in preempted
-+ * state (have scheduled out non-voluntarily) by making sure that all
-+ * tasks have either left the run queue or have gone into user space.
-+ * As idle tasks do not do either, they must not ever be preempted
-+ * (schedule out non-voluntarily).
-+ *
-+ * schedule_idle() is similar to schedule_preempt_disable() except that it
-+ * never enables preemption because it does not call sched_submit_work().
-+ */
-+void __sched schedule_idle(void)
-+{
-+	/*
-+	 * As this skips calling sched_submit_work(), which the idle task does
-+	 * regardless because that function is a nop when the task is in a
-+	 * TASK_RUNNING state, make sure this isn't used someplace that the
-+	 * current task can be in any other state. Note, idle is always in the
-+	 * TASK_RUNNING state.
-+	 */
-+	WARN_ON_ONCE(current->state);
-+	do {
-+		__schedule(false);
-+	} while (need_resched());
-+}
-+
-+#ifdef CONFIG_CONTEXT_TRACKING
-+asmlinkage __visible void __sched schedule_user(void)
-+{
-+	/*
-+	 * If we come here after a random call to set_need_resched(),
-+	 * or we have been woken up remotely but the IPI has not yet arrived,
-+	 * we haven't yet exited the RCU idle mode. Do it here manually until
-+	 * we find a better solution.
-+	 *
-+	 * NB: There are buggy callers of this function.  Ideally we
-+	 * should warn if prev_state != IN_USER, but that will trigger
-+	 * too frequently to make sense yet.
-+	 */
-+	enum ctx_state prev_state = exception_enter();
-+	schedule();
-+	exception_exit(prev_state);
-+}
-+#endif
-+
-+/**
-+ * schedule_preempt_disabled - called with preemption disabled
-+ *
-+ * Returns with preemption disabled. Note: preempt_count must be 1
-+ */
-+void __sched schedule_preempt_disabled(void)
-+{
-+	sched_preempt_enable_no_resched();
-+	schedule();
-+	preempt_disable();
-+}
-+
-+static void __sched notrace preempt_schedule_common(void)
-+{
-+	do {
-+		/*
-+		 * Because the function tracer can trace preempt_count_sub()
-+		 * and it also uses preempt_enable/disable_notrace(), if
-+		 * NEED_RESCHED is set, the preempt_enable_notrace() called
-+		 * by the function tracer will call this function again and
-+		 * cause infinite recursion.
-+		 *
-+		 * Preemption must be disabled here before the function
-+		 * tracer can trace. Break up preempt_disable() into two
-+		 * calls. One to disable preemption without fear of being
-+		 * traced. The other to still record the preemption latency,
-+		 * which can also be traced by the function tracer.
-+		 */
-+		preempt_disable_notrace();
-+		preempt_latency_start(1);
-+		__schedule(true);
-+		preempt_latency_stop(1);
-+		preempt_enable_no_resched_notrace();
-+
-+		/*
-+		 * Check again in case we missed a preemption opportunity
-+		 * between schedule and now.
-+		 */
-+	} while (need_resched());
-+}
-+
-+#ifdef CONFIG_PREEMPTION
-+/*
-+ * This is the entry point to schedule() from in-kernel preemption
-+ * off of preempt_enable.
-+ */
-+asmlinkage __visible void __sched notrace preempt_schedule(void)
-+{
-+	/*
-+	 * If there is a non-zero preempt_count or interrupts are disabled,
-+	 * we do not want to preempt the current task. Just return..
-+	 */
-+	if (likely(!preemptible()))
-+		return;
-+
-+	preempt_schedule_common();
-+}
-+NOKPROBE_SYMBOL(preempt_schedule);
-+EXPORT_SYMBOL(preempt_schedule);
-+
-+/**
-+ * preempt_schedule_notrace - preempt_schedule called by tracing
-+ *
-+ * The tracing infrastructure uses preempt_enable_notrace to prevent
-+ * recursion and tracing preempt enabling caused by the tracing
-+ * infrastructure itself. But as tracing can happen in areas coming
-+ * from userspace or just about to enter userspace, a preempt enable
-+ * can occur before user_exit() is called. This will cause the scheduler
-+ * to be called when the system is still in usermode.
-+ *
-+ * To prevent this, the preempt_enable_notrace will use this function
-+ * instead of preempt_schedule() to exit user context if needed before
-+ * calling the scheduler.
-+ */
-+asmlinkage __visible void __sched notrace preempt_schedule_notrace(void)
-+{
-+	enum ctx_state prev_ctx;
-+
-+	if (likely(!preemptible()))
-+		return;
-+
-+	do {
-+		/*
-+		 * Because the function tracer can trace preempt_count_sub()
-+		 * and it also uses preempt_enable/disable_notrace(), if
-+		 * NEED_RESCHED is set, the preempt_enable_notrace() called
-+		 * by the function tracer will call this function again and
-+		 * cause infinite recursion.
-+		 *
-+		 * Preemption must be disabled here before the function
-+		 * tracer can trace. Break up preempt_disable() into two
-+		 * calls. One to disable preemption without fear of being
-+		 * traced. The other to still record the preemption latency,
-+		 * which can also be traced by the function tracer.
-+		 */
-+		preempt_disable_notrace();
-+		preempt_latency_start(1);
-+		/*
-+		 * Needs preempt disabled in case user_exit() is traced
-+		 * and the tracer calls preempt_enable_notrace() causing
-+		 * an infinite recursion.
-+		 */
-+		prev_ctx = exception_enter();
-+		__schedule(true);
-+		exception_exit(prev_ctx);
-+
-+		preempt_latency_stop(1);
-+		preempt_enable_no_resched_notrace();
-+	} while (need_resched());
-+}
-+EXPORT_SYMBOL_GPL(preempt_schedule_notrace);
-+
-+#endif /* CONFIG_PREEMPTION */
-+
-+/*
-+ * This is the entry point to schedule() from kernel preemption
-+ * off of irq context.
-+ * Note, that this is called and return with irqs disabled. This will
-+ * protect us against recursive calling from irq.
-+ */
-+asmlinkage __visible void __sched preempt_schedule_irq(void)
-+{
-+	enum ctx_state prev_state;
-+
-+	/* Catch callers which need to be fixed */
-+	BUG_ON(preempt_count() || !irqs_disabled());
-+
-+	prev_state = exception_enter();
-+
-+	do {
-+		preempt_disable();
-+		local_irq_enable();
-+		__schedule(true);
-+		local_irq_disable();
-+		sched_preempt_enable_no_resched();
-+	} while (need_resched());
-+
-+	exception_exit(prev_state);
-+}
-+
-+int default_wake_function(wait_queue_entry_t *curr, unsigned mode, int wake_flags,
-+			  void *key)
-+{
-+	return try_to_wake_up(curr->private, mode, wake_flags);
-+}
-+EXPORT_SYMBOL(default_wake_function);
-+
-+#ifdef CONFIG_RT_MUTEXES
-+
-+static inline int __rt_effective_prio(struct task_struct *pi_task, int prio)
-+{
-+	if (pi_task)
-+		prio = min(prio, pi_task->prio);
-+
-+	return prio;
-+}
-+
-+static inline int rt_effective_prio(struct task_struct *p, int prio)
-+{
-+	struct task_struct *pi_task = rt_mutex_get_top_task(p);
-+
-+	return __rt_effective_prio(pi_task, prio);
-+}
-+
-+/*
-+ * rt_mutex_setprio - set the current priority of a task
-+ * @p: task to boost
-+ * @pi_task: donor task
-+ *
-+ * This function changes the 'effective' priority of a task. It does
-+ * not touch ->normal_prio like __setscheduler().
-+ *
-+ * Used by the rt_mutex code to implement priority inheritance
-+ * logic. Call site only calls if the priority of the task changed.
-+ */
-+void rt_mutex_setprio(struct task_struct *p, struct task_struct *pi_task)
-+{
-+	int prio, oldprio;
-+	struct rq *rq;
-+
-+	/* XXX used to be waiter->prio, not waiter->task->prio */
-+	prio = __rt_effective_prio(pi_task, p->normal_prio);
-+
-+	/*
-+	 * If nothing changed; bail early.
-+	 */
-+	if (p->pi_top_task == pi_task && prio == p->prio)
-+		return;
-+
-+	rq = __task_rq_lock(p, NULL);
-+	update_rq_clock(rq);
-+	/*
-+	 * Set under pi_lock && rq->lock, such that the value can be used under
-+	 * either lock.
-+	 *
-+	 * Note that there is loads of tricky to make this pointer cache work
-+	 * right. rt_mutex_slowunlock()+rt_mutex_postunlock() work together to
-+	 * ensure a task is de-boosted (pi_task is set to NULL) before the
-+	 * task is allowed to run again (and can exit). This ensures the pointer
-+	 * points to a blocked task -- which guaratees the task is present.
-+	 */
-+	p->pi_top_task = pi_task;
-+
-+	/*
-+	 * For FIFO/RR we only need to set prio, if that matches we're done.
-+	 */
-+	if (prio == p->prio)
-+		goto out_unlock;
-+
-+	/*
-+	 * Idle task boosting is a nono in general. There is one
-+	 * exception, when PREEMPT_RT and NOHZ is active:
-+	 *
-+	 * The idle task calls get_next_timer_interrupt() and holds
-+	 * the timer wheel base->lock on the CPU and another CPU wants
-+	 * to access the timer (probably to cancel it). We can safely
-+	 * ignore the boosting request, as the idle CPU runs this code
-+	 * with interrupts disabled and will complete the lock
-+	 * protected section without being interrupted. So there is no
-+	 * real need to boost.
-+	 */
-+	if (unlikely(p == rq->idle)) {
-+		WARN_ON(p != rq->curr);
-+		WARN_ON(p->pi_blocked_on);
-+		goto out_unlock;
-+	}
-+
-+	trace_sched_pi_setprio(p, pi_task);
-+	oldprio = p->prio;
-+	p->prio = prio;
-+	if (task_running(rq, p)){
-+		if (prio > oldprio)
-+			resched_task(p);
-+	} else if (task_queued(p)) {
-+		dequeue_task(rq, p, DEQUEUE_SAVE);
-+		enqueue_task(rq, p, ENQUEUE_RESTORE);
-+		if (prio < oldprio)
-+			try_preempt(p, rq);
-+	}
-+out_unlock:
-+	__task_rq_unlock(rq, NULL);
-+}
-+#else
-+static inline int rt_effective_prio(struct task_struct *p, int prio)
-+{
-+	return prio;
-+}
-+#endif
-+
-+/*
-+ * Adjust the deadline for when the priority is to change, before it's
-+ * changed.
-+ */
-+static inline void adjust_deadline(struct task_struct *p, int new_prio)
-+{
-+	p->deadline += static_deadline_diff(new_prio) - task_deadline_diff(p);
-+}
-+
-+void set_user_nice(struct task_struct *p, long nice)
-+{
-+	int new_static, old_static;
-+	struct rq_flags rf;
-+	struct rq *rq;
-+
-+	if (task_nice(p) == nice || nice < MIN_NICE || nice > MAX_NICE)
-+		return;
-+	new_static = NICE_TO_PRIO(nice);
-+	/*
-+	 * We have to be careful, if called from sys_setpriority(),
-+	 * the task might be in the middle of scheduling on another CPU.
-+	 */
-+	rq = task_rq_lock(p, &rf);
-+	update_rq_clock(rq);
-+
-+	/*
-+	 * The RT priorities are set via sched_setscheduler(), but we still
-+	 * allow the 'normal' nice value to be set - but as expected
-+	 * it wont have any effect on scheduling until the task is
-+	 * not SCHED_NORMAL/SCHED_BATCH:
-+	 */
-+	if (has_rt_policy(p)) {
-+		p->static_prio = new_static;
-+		goto out_unlock;
-+	}
-+
-+	adjust_deadline(p, new_static);
-+	old_static = p->static_prio;
-+	p->static_prio = new_static;
-+	p->prio = effective_prio(p);
-+
-+	if (task_queued(p)) {
-+		dequeue_task(rq, p, DEQUEUE_SAVE);
-+		enqueue_task(rq, p, ENQUEUE_RESTORE);
-+		if (new_static < old_static)
-+			try_preempt(p, rq);
-+	} else if (task_running(rq, p)) {
-+		set_rq_task(rq, p);
-+		if (old_static < new_static)
-+			resched_task(p);
-+	}
-+out_unlock:
-+	task_rq_unlock(rq, p, &rf);
-+}
-+EXPORT_SYMBOL(set_user_nice);
-+
-+/*
-+ * can_nice - check if a task can reduce its nice value
-+ * @p: task
-+ * @nice: nice value
-+ */
-+int can_nice(const struct task_struct *p, const int nice)
-+{
-+	/* Convert nice value [19,-20] to rlimit style value [1,40] */
-+	int nice_rlim = nice_to_rlimit(nice);
-+
-+	return (nice_rlim <= task_rlimit(p, RLIMIT_NICE) ||
-+		capable(CAP_SYS_NICE));
-+}
-+
-+#ifdef __ARCH_WANT_SYS_NICE
-+
-+/*
-+ * sys_nice - change the priority of the current process.
-+ * @increment: priority increment
-+ *
-+ * sys_setpriority is a more generic, but much slower function that
-+ * does similar things.
-+ */
-+SYSCALL_DEFINE1(nice, int, increment)
-+{
-+	long nice, retval;
-+
-+	/*
-+	 * Setpriority might change our priority at the same moment.
-+	 * We don't have to worry. Conceptually one call occurs first
-+	 * and we have a single winner.
-+	 */
-+
-+	increment = clamp(increment, -NICE_WIDTH, NICE_WIDTH);
-+	nice = task_nice(current) + increment;
-+
-+	nice = clamp_val(nice, MIN_NICE, MAX_NICE);
-+	if (increment < 0 && !can_nice(current, nice))
-+		return -EPERM;
-+
-+	retval = security_task_setnice(current, nice);
-+	if (retval)
-+		return retval;
-+
-+	set_user_nice(current, nice);
-+	return 0;
-+}
-+
-+#endif
-+
-+/**
-+ * task_prio - return the priority value of a given task.
-+ * @p: the task in question.
-+ *
-+ * Return: The priority value as seen by users in /proc.
-+ * RT tasks are offset by -100. Normal tasks are centered around 1, value goes
-+ * from 0 (SCHED_ISO) up to 82 (nice +19 SCHED_IDLEPRIO).
-+ */
-+int task_prio(const struct task_struct *p)
-+{
-+	int delta, prio = p->prio - MAX_RT_PRIO;
-+
-+	/* rt tasks and iso tasks */
-+	if (prio <= 0)
-+		goto out;
-+
-+	/* Convert to ms to avoid overflows */
-+	delta = NS_TO_MS(p->deadline - task_rq(p)->niffies);
-+	if (unlikely(delta < 0))
-+		delta = 0;
-+	delta = delta * 40 / ms_longest_deadline_diff();
-+	if (delta <= 80)
-+		prio += delta;
-+	if (idleprio_task(p))
-+		prio += 40;
-+out:
-+	return prio;
-+}
-+
-+/**
-+ * idle_cpu - is a given CPU idle currently?
-+ * @cpu: the processor in question.
-+ *
-+ * Return: 1 if the CPU is currently idle. 0 otherwise.
-+ */
-+int idle_cpu(int cpu)
-+{
-+	return cpu_curr(cpu) == cpu_rq(cpu)->idle;
-+}
-+
-+/**
-+ * available_idle_cpu - is a given CPU idle for enqueuing work.
-+ * @cpu: the CPU in question.
-+ *
-+ * Return: 1 if the CPU is currently idle. 0 otherwise.
-+ */
-+int available_idle_cpu(int cpu)
-+{
-+	if (!idle_cpu(cpu))
-+		return 0;
-+
-+	if (vcpu_is_preempted(cpu))
-+		return 0;
-+
-+	return 1;
-+}
-+
-+/**
-+ * idle_task - return the idle task for a given CPU.
-+ * @cpu: the processor in question.
-+ *
-+ * Return: The idle task for the CPU @cpu.
-+ */
-+struct task_struct *idle_task(int cpu)
-+{
-+	return cpu_rq(cpu)->idle;
-+}
-+
-+/**
-+ * find_process_by_pid - find a process with a matching PID value.
-+ * @pid: the pid in question.
-+ *
-+ * The task of @pid, if found. %NULL otherwise.
-+ */
-+static inline struct task_struct *find_process_by_pid(pid_t pid)
-+{
-+	return pid ? find_task_by_vpid(pid) : current;
-+}
-+
-+/* Actually do priority change: must hold rq lock. */
-+static void __setscheduler(struct task_struct *p, struct rq *rq, int policy,
-+			   int prio, const struct sched_attr *attr,
-+			   bool keep_boost)
-+{
-+	int oldrtprio, oldprio;
-+
-+	/*
-+	 * If params can't change scheduling class changes aren't allowed
-+	 * either.
-+	 */
-+	if (attr->sched_flags & SCHED_FLAG_KEEP_PARAMS)
-+		return;
-+
-+	p->policy = policy;
-+	oldrtprio = p->rt_priority;
-+	p->rt_priority = prio;
-+	p->normal_prio = normal_prio(p);
-+	oldprio = p->prio;
-+	/*
-+	 * Keep a potential priority boosting if called from
-+	 * sched_setscheduler().
-+	 */
-+	p->prio = normal_prio(p);
-+	if (keep_boost)
-+		p->prio = rt_effective_prio(p, p->prio);
-+
-+	if (task_running(rq, p)) {
-+		set_rq_task(rq, p);
-+		resched_task(p);
-+	} else if (task_queued(p)) {
-+		dequeue_task(rq, p, DEQUEUE_SAVE);
-+		enqueue_task(rq, p, ENQUEUE_RESTORE);
-+		if (p->prio < oldprio || p->rt_priority > oldrtprio)
-+			try_preempt(p, rq);
-+	}
-+}
-+
-+/*
-+ * Check the target process has a UID that matches the current process's
-+ */
-+static bool check_same_owner(struct task_struct *p)
-+{
-+	const struct cred *cred = current_cred(), *pcred;
-+	bool match;
-+
-+	rcu_read_lock();
-+	pcred = __task_cred(p);
-+	match = (uid_eq(cred->euid, pcred->euid) ||
-+		 uid_eq(cred->euid, pcred->uid));
-+	rcu_read_unlock();
-+	return match;
-+}
-+
-+static int __sched_setscheduler(struct task_struct *p,
-+				const struct sched_attr *attr,
-+				bool user, bool pi)
-+{
-+	int retval, policy = attr->sched_policy, oldpolicy = -1, priority = attr->sched_priority;
-+	unsigned long rlim_rtprio = 0;
-+	struct rq_flags rf;
-+	int reset_on_fork;
-+	struct rq *rq;
-+
-+	/* The pi code expects interrupts enabled */
-+	BUG_ON(pi && in_interrupt());
-+
-+	if (is_rt_policy(policy) && !capable(CAP_SYS_NICE)) {
-+		unsigned long lflags;
-+
-+		if (!lock_task_sighand(p, &lflags))
-+			return -ESRCH;
-+		rlim_rtprio = task_rlimit(p, RLIMIT_RTPRIO);
-+		unlock_task_sighand(p, &lflags);
-+		if (rlim_rtprio)
-+			goto recheck;
-+		/*
-+		 * If the caller requested an RT policy without having the
-+		 * necessary rights, we downgrade the policy to SCHED_ISO.
-+		 * We also set the parameter to zero to pass the checks.
-+		 */
-+		policy = SCHED_ISO;
-+		priority = 0;
-+	}
-+recheck:
-+	/* Double check policy once rq lock held */
-+	if (policy < 0) {
-+		reset_on_fork = p->sched_reset_on_fork;
-+		policy = oldpolicy = p->policy;
-+	} else {
-+		reset_on_fork = !!(policy & SCHED_RESET_ON_FORK);
-+		policy &= ~SCHED_RESET_ON_FORK;
-+
-+		if (!SCHED_RANGE(policy))
-+			return -EINVAL;
-+	}
-+
-+	if (attr->sched_flags & ~(SCHED_FLAG_ALL | SCHED_FLAG_SUGOV))
-+		return -EINVAL;
-+
-+	/*
-+	 * Valid priorities for SCHED_FIFO and SCHED_RR are
-+	 * 1..MAX_USER_RT_PRIO-1, valid priority for SCHED_NORMAL and
-+	 * SCHED_BATCH is 0.
-+	 */
-+	if (priority < 0 ||
-+	    (p->mm && priority > MAX_USER_RT_PRIO - 1) ||
-+	    (!p->mm && priority > MAX_RT_PRIO - 1))
-+		return -EINVAL;
-+	if (is_rt_policy(policy) != (priority != 0))
-+		return -EINVAL;
-+
-+	/*
-+	 * Allow unprivileged RT tasks to decrease priority:
-+	 */
-+	if (user && !capable(CAP_SYS_NICE)) {
-+		if (is_rt_policy(policy)) {
-+			unsigned long rlim_rtprio =
-+					task_rlimit(p, RLIMIT_RTPRIO);
-+
-+			/* Can't set/change the rt policy */
-+			if (policy != p->policy && !rlim_rtprio)
-+				return -EPERM;
-+
-+			/* Can't increase priority */
-+			if (priority > p->rt_priority &&
-+			    priority > rlim_rtprio)
-+				return -EPERM;
-+		} else {
-+			switch (p->policy) {
-+				/*
-+				 * Can only downgrade policies but not back to
-+				 * SCHED_NORMAL
-+				 */
-+				case SCHED_ISO:
-+					if (policy == SCHED_ISO)
-+						goto out;
-+					if (policy != SCHED_NORMAL)
-+						return -EPERM;
-+					break;
-+				case SCHED_BATCH:
-+					if (policy == SCHED_BATCH)
-+						goto out;
-+					if (policy != SCHED_IDLEPRIO)
-+						return -EPERM;
-+					break;
-+				case SCHED_IDLEPRIO:
-+					if (policy == SCHED_IDLEPRIO)
-+						goto out;
-+					return -EPERM;
-+				default:
-+					break;
-+			}
-+		}
-+
-+		/* Can't change other user's priorities */
-+		if (!check_same_owner(p))
-+			return -EPERM;
-+
-+		/* Normal users shall not reset the sched_reset_on_fork flag: */
-+		if (p->sched_reset_on_fork && !reset_on_fork)
-+			return -EPERM;
-+	}
-+
-+	if (user) {
-+		retval = security_task_setscheduler(p);
-+		if (retval)
-+			return retval;
-+	}
-+
-+	if (pi)
-+		cpuset_read_lock();
-+
-+	/*
-+	 * Make sure no PI-waiters arrive (or leave) while we are
-+	 * changing the priority of the task:
-+	 *
-+	 * To be able to change p->policy safely, the runqueue lock must be
-+	 * held.
-+	 */
-+	rq = task_rq_lock(p, &rf);
-+	update_rq_clock(rq);
-+
-+	/*
-+	 * Changing the policy of the stop threads its a very bad idea:
-+	 */
-+	if (p == rq->stop) {
-+		retval = -EINVAL;
-+		goto unlock;
-+	}
-+
-+	/*
-+	 * If not changing anything there's no need to proceed further:
-+	 */
-+	if (unlikely(policy == p->policy && (!is_rt_policy(policy) ||
-+	    priority == p->rt_priority))) {
-+		retval = 0;
-+		goto unlock;
-+	}
-+
-+	/* Re-check policy now with rq lock held */
-+	if (unlikely(oldpolicy != -1 && oldpolicy != p->policy)) {
-+		policy = oldpolicy = -1;
-+		task_rq_unlock(rq, p, &rf);
-+		if (pi)
-+			cpuset_read_unlock();
-+		goto recheck;
-+	}
-+	p->sched_reset_on_fork = reset_on_fork;
-+
-+	__setscheduler(p, rq, policy, priority, attr, pi);
-+
-+	/* Avoid rq from going away on us: */
-+	preempt_disable();
-+	task_rq_unlock(rq, p, &rf);
-+
-+	if (pi) {
-+		cpuset_read_unlock();
-+		rt_mutex_adjust_pi(p);
-+	}
-+	preempt_enable();
-+out:
-+	return 0;
-+
-+unlock:
-+	task_rq_unlock(rq, p, &rf);
-+	if (pi)
-+		cpuset_read_unlock();
-+	return retval;
-+}
-+
-+static int _sched_setscheduler(struct task_struct *p, int policy,
-+			       const struct sched_param *param, bool check)
-+{
-+	struct sched_attr attr = {
-+		.sched_policy   = policy,
-+		.sched_priority = param->sched_priority,
-+		.sched_nice	= PRIO_TO_NICE(p->static_prio),
-+	};
-+
-+	return __sched_setscheduler(p, &attr, check, true);
-+}
-+/**
-+ * sched_setscheduler - change the scheduling policy and/or RT priority of a thread.
-+ * @p: the task in question.
-+ * @policy: new policy.
-+ * @param: structure containing the new RT priority.
-+ *
-+ * Return: 0 on success. An error code otherwise.
-+ *
-+ * NOTE that the task may be already dead.
-+ */
-+int sched_setscheduler(struct task_struct *p, int policy,
-+		       const struct sched_param *param)
-+{
-+	return _sched_setscheduler(p, policy, param, true);
-+}
-+
-+EXPORT_SYMBOL_GPL(sched_setscheduler);
-+
-+int sched_setattr(struct task_struct *p, const struct sched_attr *attr)
-+{
-+	return __sched_setscheduler(p, attr, true, true);
-+}
-+EXPORT_SYMBOL_GPL(sched_setattr);
-+
-+int sched_setattr_nocheck(struct task_struct *p, const struct sched_attr *attr)
-+{
-+	return __sched_setscheduler(p, attr, false, true);
-+}
-+
-+/**
-+ * sched_setscheduler_nocheck - change the scheduling policy and/or RT priority of a thread from kernelspace.
-+ * @p: the task in question.
-+ * @policy: new policy.
-+ * @param: structure containing the new RT priority.
-+ *
-+ * Just like sched_setscheduler, only don't bother checking if the
-+ * current context has permission.  For example, this is needed in
-+ * stop_machine(): we create temporary high priority worker threads,
-+ * but our caller might not have that capability.
-+ *
-+ * Return: 0 on success. An error code otherwise.
-+ */
-+int sched_setscheduler_nocheck(struct task_struct *p, int policy,
-+			       const struct sched_param *param)
-+{
-+	return _sched_setscheduler(p, policy, param, false);
-+}
-+EXPORT_SYMBOL_GPL(sched_setscheduler_nocheck);
-+
-+static int
-+do_sched_setscheduler(pid_t pid, int policy, struct sched_param __user *param)
-+{
-+	struct sched_param lparam;
-+	struct task_struct *p;
-+	int retval;
-+
-+	if (!param || pid < 0)
-+		return -EINVAL;
-+	if (copy_from_user(&lparam, param, sizeof(struct sched_param)))
-+		return -EFAULT;
-+
-+	rcu_read_lock();
-+	retval = -ESRCH;
-+	p = find_process_by_pid(pid);
-+	if (likely(p))
-+		get_task_struct(p);
-+	rcu_read_unlock();
-+
-+	if (likely(p)) {
-+		retval = sched_setscheduler(p, policy, &lparam);
-+		put_task_struct(p);
-+	}
-+
-+	return retval;
-+}
-+
-+/*
-+ * Mimics kernel/events/core.c perf_copy_attr().
-+ */
-+static int sched_copy_attr(struct sched_attr __user *uattr,
-+			   struct sched_attr *attr)
-+{
-+	u32 size;
-+	int ret;
-+
-+	/* Zero the full structure, so that a short copy will be nice: */
-+	memset(attr, 0, sizeof(*attr));
-+
-+	ret = get_user(size, &uattr->size);
-+	if (ret)
-+		return ret;
-+
-+	/* ABI compatibility quirk: */
-+	if (!size)
-+		size = SCHED_ATTR_SIZE_VER0;
-+
-+	if (size < SCHED_ATTR_SIZE_VER0 || size > PAGE_SIZE)
-+		goto err_size;
-+
-+	ret = copy_struct_from_user(attr, sizeof(*attr), uattr, size);
-+	if (ret) {
-+		if (ret == -E2BIG)
-+			goto err_size;
-+		return ret;
-+	}
-+
-+	/*
-+	 * XXX: Do we want to be lenient like existing syscalls; or do we want
-+	 * to be strict and return an error on out-of-bounds values?
-+	 */
-+	attr->sched_nice = clamp(attr->sched_nice, -20, 19);
-+
-+	/* sched/core.c uses zero here but we already know ret is zero */
-+	return 0;
-+
-+err_size:
-+	put_user(sizeof(*attr), &uattr->size);
-+	return -E2BIG;
-+}
-+
-+/*
-+ * sched_setparam() passes in -1 for its policy, to let the functions
-+ * it calls know not to change it.
-+ */
-+#define SETPARAM_POLICY	-1
-+
-+/**
-+ * sys_sched_setscheduler - set/change the scheduler policy and RT priority
-+ * @pid: the pid in question.
-+ * @policy: new policy.
-+ * @param: structure containing the new RT priority.
-+ *
-+ * Return: 0 on success. An error code otherwise.
-+ */
-+SYSCALL_DEFINE3(sched_setscheduler, pid_t, pid, int, policy, struct sched_param __user *, param)
-+{
-+	if (policy < 0)
-+		return -EINVAL;
-+
-+	return do_sched_setscheduler(pid, policy, param);
-+}
-+
-+/**
-+ * sys_sched_setparam - set/change the RT priority of a thread
-+ * @pid: the pid in question.
-+ * @param: structure containing the new RT priority.
-+ *
-+ * Return: 0 on success. An error code otherwise.
-+ */
-+SYSCALL_DEFINE2(sched_setparam, pid_t, pid, struct sched_param __user *, param)
-+{
-+	return do_sched_setscheduler(pid, SETPARAM_POLICY, param);
-+}
-+
-+/**
-+ * sys_sched_setattr - same as above, but with extended sched_attr
-+ * @pid: the pid in question.
-+ * @uattr: structure containing the extended parameters.
-+ */
-+SYSCALL_DEFINE3(sched_setattr, pid_t, pid, struct sched_attr __user *, uattr,
-+			       unsigned int, flags)
-+{
-+	struct sched_attr attr;
-+	struct task_struct *p;
-+	int retval;
-+
-+	if (!uattr || pid < 0 || flags)
-+		return -EINVAL;
-+
-+	retval = sched_copy_attr(uattr, &attr);
-+	if (retval)
-+		return retval;
-+
-+	if ((int)attr.sched_policy < 0)
-+		return -EINVAL;
-+	if (attr.sched_flags & SCHED_FLAG_KEEP_POLICY)
-+		attr.sched_policy = SETPARAM_POLICY;
-+
-+	rcu_read_lock();
-+	retval = -ESRCH;
-+	p = find_process_by_pid(pid);
-+	if (likely(p))
-+		get_task_struct(p);
-+	rcu_read_unlock();
-+
-+	if (likely(p)) {
-+		retval = sched_setattr(p, &attr);
-+		put_task_struct(p);
-+	}
-+
-+	return retval;
-+}
-+
-+/**
-+ * sys_sched_getscheduler - get the policy (scheduling class) of a thread
-+ * @pid: the pid in question.
-+ *
-+ * Return: On success, the policy of the thread. Otherwise, a negative error
-+ * code.
-+ */
-+SYSCALL_DEFINE1(sched_getscheduler, pid_t, pid)
-+{
-+	struct task_struct *p;
-+	int retval = -EINVAL;
-+
-+	if (pid < 0)
-+		goto out_nounlock;
-+
-+	retval = -ESRCH;
-+	rcu_read_lock();
-+	p = find_process_by_pid(pid);
-+	if (p) {
-+		retval = security_task_getscheduler(p);
-+		if (!retval)
-+			retval = p->policy;
-+	}
-+	rcu_read_unlock();
-+
-+out_nounlock:
-+	return retval;
-+}
-+
-+/**
-+ * sys_sched_getscheduler - get the RT priority of a thread
-+ * @pid: the pid in question.
-+ * @param: structure containing the RT priority.
-+ *
-+ * Return: On success, 0 and the RT priority is in @param. Otherwise, an error
-+ * code.
-+ */
-+SYSCALL_DEFINE2(sched_getparam, pid_t, pid, struct sched_param __user *, param)
-+{
-+	struct sched_param lp = { .sched_priority = 0 };
-+	struct task_struct *p;
-+	int retval = -EINVAL;
-+
-+	if (!param || pid < 0)
-+		goto out_nounlock;
-+
-+	rcu_read_lock();
-+	p = find_process_by_pid(pid);
-+	retval = -ESRCH;
-+	if (!p)
-+		goto out_unlock;
-+
-+	retval = security_task_getscheduler(p);
-+	if (retval)
-+		goto out_unlock;
-+
-+	if (has_rt_policy(p))
-+		lp.sched_priority = p->rt_priority;
-+	rcu_read_unlock();
-+
-+	/*
-+	 * This one might sleep, we cannot do it with a spinlock held ...
-+	 */
-+	retval = copy_to_user(param, &lp, sizeof(*param)) ? -EFAULT : 0;
-+
-+out_nounlock:
-+	return retval;
-+
-+out_unlock:
-+	rcu_read_unlock();
-+	return retval;
-+}
-+
-+/*
-+ * Copy the kernel size attribute structure (which might be larger
-+ * than what user-space knows about) to user-space.
-+ *
-+ * Note that all cases are valid: user-space buffer can be larger or
-+ * smaller than the kernel-space buffer. The usual case is that both
-+ * have the same size.
-+ */
-+static int
-+sched_attr_copy_to_user(struct sched_attr __user *uattr,
-+			struct sched_attr *kattr,
-+			unsigned int usize)
-+{
-+	unsigned int ksize = sizeof(*kattr);
-+
-+	if (!access_ok(uattr, usize))
-+		return -EFAULT;
-+
-+	/*
-+	 * sched_getattr() ABI forwards and backwards compatibility:
-+	 *
-+	 * If usize == ksize then we just copy everything to user-space and all is good.
-+	 *
-+	 * If usize < ksize then we only copy as much as user-space has space for,
-+	 * this keeps ABI compatibility as well. We skip the rest.
-+	 *
-+	 * If usize > ksize then user-space is using a newer version of the ABI,
-+	 * which part the kernel doesn't know about. Just ignore it - tooling can
-+	 * detect the kernel's knowledge of attributes from the attr->size value
-+	 * which is set to ksize in this case.
-+	 */
-+	kattr->size = min(usize, ksize);
-+
-+	if (copy_to_user(uattr, kattr, kattr->size))
-+		return -EFAULT;
-+
-+	return 0;
-+}
-+
-+/**
-+ * sys_sched_getattr - similar to sched_getparam, but with sched_attr
-+ * @pid: the pid in question.
-+ * @uattr: structure containing the extended parameters.
-+ * @usize: sizeof(attr) for fwd/bwd comp.
-+ * @flags: for future extension.
-+ */
-+SYSCALL_DEFINE4(sched_getattr, pid_t, pid, struct sched_attr __user *, uattr,
-+		unsigned int, usize, unsigned int, flags)
-+{
-+	struct sched_attr kattr = { };
-+	struct task_struct *p;
-+	int retval;
-+
-+	if (!uattr || pid < 0 || usize > PAGE_SIZE ||
-+	    usize < SCHED_ATTR_SIZE_VER0 || flags)
-+		return -EINVAL;
-+
-+	rcu_read_lock();
-+	p = find_process_by_pid(pid);
-+	retval = -ESRCH;
-+	if (!p)
-+		goto out_unlock;
-+
-+	retval = security_task_getscheduler(p);
-+	if (retval)
-+		goto out_unlock;
-+
-+	kattr.sched_policy = p->policy;
-+	if (rt_task(p))
-+		kattr.sched_priority = p->rt_priority;
-+	else
-+		kattr.sched_nice = task_nice(p);
-+
-+	rcu_read_unlock();
-+
-+	return sched_attr_copy_to_user(uattr, &kattr, usize);
-+
-+out_unlock:
-+	rcu_read_unlock();
-+	return retval;
-+}
-+
-+long sched_setaffinity(pid_t pid, const struct cpumask *in_mask)
-+{
-+	cpumask_var_t cpus_allowed, new_mask;
-+	struct task_struct *p;
-+	int retval;
-+
-+	rcu_read_lock();
-+
-+	p = find_process_by_pid(pid);
-+	if (!p) {
-+		rcu_read_unlock();
-+		return -ESRCH;
-+	}
-+
-+	/* Prevent p going away */
-+	get_task_struct(p);
-+	rcu_read_unlock();
-+
-+	if (p->flags & PF_NO_SETAFFINITY) {
-+		retval = -EINVAL;
-+		goto out_put_task;
-+	}
-+	if (!alloc_cpumask_var(&cpus_allowed, GFP_KERNEL)) {
-+		retval = -ENOMEM;
-+		goto out_put_task;
-+	}
-+	if (!alloc_cpumask_var(&new_mask, GFP_KERNEL)) {
-+		retval = -ENOMEM;
-+		goto out_free_cpus_allowed;
-+	}
-+	retval = -EPERM;
-+	if (!check_same_owner(p)) {
-+		rcu_read_lock();
-+		if (!ns_capable(__task_cred(p)->user_ns, CAP_SYS_NICE)) {
-+			rcu_read_unlock();
-+			goto out_unlock;
-+		}
-+		rcu_read_unlock();
-+	}
-+
-+	retval = security_task_setscheduler(p);
-+	if (retval)
-+		goto out_unlock;
-+
-+	cpuset_cpus_allowed(p, cpus_allowed);
-+	cpumask_and(new_mask, in_mask, cpus_allowed);
-+again:
-+	retval = __set_cpus_allowed_ptr(p, new_mask, true);
-+
-+	if (!retval) {
-+		cpuset_cpus_allowed(p, cpus_allowed);
-+		if (!cpumask_subset(new_mask, cpus_allowed)) {
-+			/*
-+			 * We must have raced with a concurrent cpuset
-+			 * update. Just reset the cpus_allowed to the
-+			 * cpuset's cpus_allowed
-+			 */
-+			cpumask_copy(new_mask, cpus_allowed);
-+			goto again;
-+		}
-+	}
-+out_unlock:
-+	free_cpumask_var(new_mask);
-+out_free_cpus_allowed:
-+	free_cpumask_var(cpus_allowed);
-+out_put_task:
-+	put_task_struct(p);
-+	return retval;
-+}
-+
-+static int get_user_cpu_mask(unsigned long __user *user_mask_ptr, unsigned len,
-+			     cpumask_t *new_mask)
-+{
-+	if (len < cpumask_size())
-+		cpumask_clear(new_mask);
-+	else if (len > cpumask_size())
-+		len = cpumask_size();
-+
-+	return copy_from_user(new_mask, user_mask_ptr, len) ? -EFAULT : 0;
-+}
-+
-+
-+/**
-+ * sys_sched_setaffinity - set the CPU affinity of a process
-+ * @pid: pid of the process
-+ * @len: length in bytes of the bitmask pointed to by user_mask_ptr
-+ * @user_mask_ptr: user-space pointer to the new CPU mask
-+ *
-+ * Return: 0 on success. An error code otherwise.
-+ */
-+SYSCALL_DEFINE3(sched_setaffinity, pid_t, pid, unsigned int, len,
-+		unsigned long __user *, user_mask_ptr)
-+{
-+	cpumask_var_t new_mask;
-+	int retval;
-+
-+	if (!alloc_cpumask_var(&new_mask, GFP_KERNEL))
-+		return -ENOMEM;
-+
-+	retval = get_user_cpu_mask(user_mask_ptr, len, new_mask);
-+	if (retval == 0)
-+		retval = sched_setaffinity(pid, new_mask);
-+	free_cpumask_var(new_mask);
-+	return retval;
-+}
-+
-+long sched_getaffinity(pid_t pid, cpumask_t *mask)
-+{
-+	struct task_struct *p;
-+	unsigned long flags;
-+	int retval;
-+
-+	get_online_cpus();
-+	rcu_read_lock();
-+
-+	retval = -ESRCH;
-+	p = find_process_by_pid(pid);
-+	if (!p)
-+		goto out_unlock;
-+
-+	retval = security_task_getscheduler(p);
-+	if (retval)
-+		goto out_unlock;
-+
-+	raw_spin_lock_irqsave(&p->pi_lock, flags);
-+	cpumask_and(mask, &p->cpus_mask, cpu_active_mask);
-+	raw_spin_unlock_irqrestore(&p->pi_lock, flags);
-+
-+out_unlock:
-+	rcu_read_unlock();
-+	put_online_cpus();
-+
-+	return retval;
-+}
-+
-+/**
-+ * sys_sched_getaffinity - get the CPU affinity of a process
-+ * @pid: pid of the process
-+ * @len: length in bytes of the bitmask pointed to by user_mask_ptr
-+ * @user_mask_ptr: user-space pointer to hold the current CPU mask
-+ *
-+ * Return: 0 on success. An error code otherwise.
-+ */
-+SYSCALL_DEFINE3(sched_getaffinity, pid_t, pid, unsigned int, len,
-+		unsigned long __user *, user_mask_ptr)
-+{
-+	int ret;
-+	cpumask_var_t mask;
-+
-+	if ((len * BITS_PER_BYTE) < nr_cpu_ids)
-+		return -EINVAL;
-+	if (len & (sizeof(unsigned long)-1))
-+		return -EINVAL;
-+
-+	if (!alloc_cpumask_var(&mask, GFP_KERNEL))
-+		return -ENOMEM;
-+
-+	ret = sched_getaffinity(pid, mask);
-+	if (ret == 0) {
-+		unsigned int retlen = min(len, cpumask_size());
-+
-+		if (copy_to_user(user_mask_ptr, mask, retlen))
-+			ret = -EFAULT;
-+		else
-+			ret = retlen;
-+	}
-+	free_cpumask_var(mask);
-+
-+	return ret;
-+}
-+
-+/**
-+ * sys_sched_yield - yield the current processor to other threads.
-+ *
-+ * This function yields the current CPU to other tasks. It does this by
-+ * scheduling away the current task. If it still has the earliest deadline
-+ * it will be scheduled again as the next task.
-+ *
-+ * Return: 0.
-+ */
-+static void do_sched_yield(void)
-+{
-+	struct rq *rq;
-+
-+	if (!sched_yield_type)
-+		return;
-+
-+	local_irq_disable();
-+	rq = this_rq();
-+	rq_lock(rq);
-+
-+	if (sched_yield_type > 1)
-+		time_slice_expired(current, rq);
-+	schedstat_inc(rq->yld_count);
-+
-+	/*
-+	 * Since we are going to call schedule() anyway, there's
-+	 * no need to preempt or enable interrupts:
-+	 */
-+	preempt_disable();
-+	rq_unlock(rq);
-+	sched_preempt_enable_no_resched();
-+
-+	schedule();
-+}
-+
-+SYSCALL_DEFINE0(sched_yield)
-+{
-+	do_sched_yield();
-+	return 0;
-+}
-+
-+#ifndef CONFIG_PREEMPTION
-+int __sched _cond_resched(void)
-+{
-+	if (should_resched(0)) {
-+		preempt_schedule_common();
-+		return 1;
-+	}
-+	rcu_all_qs();
-+	return 0;
-+}
-+EXPORT_SYMBOL(_cond_resched);
-+#endif
-+
-+/*
-+ * __cond_resched_lock() - if a reschedule is pending, drop the given lock,
-+ * call schedule, and on return reacquire the lock.
-+ *
-+ * This works OK both with and without CONFIG_PREEMPTION.  We do strange low-level
-+ * operations here to prevent schedule() from being called twice (once via
-+ * spin_unlock(), once by hand).
-+ */
-+int __cond_resched_lock(spinlock_t *lock)
-+{
-+	int resched = should_resched(PREEMPT_LOCK_OFFSET);
-+	int ret = 0;
-+
-+	lockdep_assert_held(lock);
-+
-+	if (spin_needbreak(lock) || resched) {
-+		spin_unlock(lock);
-+		if (resched)
-+			preempt_schedule_common();
-+		else
-+			cpu_relax();
-+		ret = 1;
-+		spin_lock(lock);
-+	}
-+	return ret;
-+}
-+EXPORT_SYMBOL(__cond_resched_lock);
-+
-+/**
-+ * yield - yield the current processor to other threads.
-+ *
-+ * Do not ever use this function, there's a 99% chance you're doing it wrong.
-+ *
-+ * The scheduler is at all times free to pick the calling task as the most
-+ * eligible task to run, if removing the yield() call from your code breaks
-+ * it, its already broken.
-+ *
-+ * Typical broken usage is:
-+ *
-+ * while (!event)
-+ *	yield();
-+ *
-+ * where one assumes that yield() will let 'the other' process run that will
-+ * make event true. If the current task is a SCHED_FIFO task that will never
-+ * happen. Never use yield() as a progress guarantee!!
-+ *
-+ * If you want to use yield() to wait for something, use wait_event().
-+ * If you want to use yield() to be 'nice' for others, use cond_resched().
-+ * If you still want to use yield(), do not!
-+ */
-+void __sched yield(void)
-+{
-+	set_current_state(TASK_RUNNING);
-+	do_sched_yield();
-+}
-+EXPORT_SYMBOL(yield);
-+
-+/**
-+ * yield_to - yield the current processor to another thread in
-+ * your thread group, or accelerate that thread toward the
-+ * processor it's on.
-+ * @p: target task
-+ * @preempt: whether task preemption is allowed or not
-+ *
-+ * It's the caller's job to ensure that the target task struct
-+ * can't go away on us before we can do any checks.
-+ *
-+ * Return:
-+ *	true (>0) if we indeed boosted the target task.
-+ *	false (0) if we failed to boost the target.
-+ *	-ESRCH if there's no task to yield to.
-+ */
-+int __sched yield_to(struct task_struct *p, bool preempt)
-+{
-+	struct task_struct *rq_p;
-+	struct rq *rq, *p_rq;
-+	unsigned long flags;
-+	int yielded = 0;
-+
-+	local_irq_save(flags);
-+	rq = this_rq();
-+
-+again:
-+	p_rq = task_rq(p);
-+	/*
-+	 * If we're the only runnable task on the rq and target rq also
-+	 * has only one task, there's absolutely no point in yielding.
-+	 */
-+	if (task_running(p_rq, p) || p->state) {
-+		yielded = -ESRCH;
-+		goto out_irq;
-+	}
-+
-+	double_rq_lock(rq, p_rq);
-+	if (unlikely(task_rq(p) != p_rq)) {
-+		double_rq_unlock(rq, p_rq);
-+		goto again;
-+	}
-+
-+	yielded = 1;
-+	schedstat_inc(rq->yld_count);
-+	rq_p = rq->curr;
-+	if (p->deadline > rq_p->deadline)
-+		p->deadline = rq_p->deadline;
-+	p->time_slice += rq_p->time_slice;
-+	if (p->time_slice > timeslice())
-+		p->time_slice = timeslice();
-+	time_slice_expired(rq_p, rq);
-+	if (preempt && rq != p_rq)
-+		resched_task(p_rq->curr);
-+	double_rq_unlock(rq, p_rq);
-+out_irq:
-+	local_irq_restore(flags);
-+
-+	if (yielded > 0)
-+		schedule();
-+	return yielded;
-+}
-+EXPORT_SYMBOL_GPL(yield_to);
-+
-+int io_schedule_prepare(void)
-+{
-+	int old_iowait = current->in_iowait;
-+
-+	current->in_iowait = 1;
-+	blk_schedule_flush_plug(current);
-+
-+	return old_iowait;
-+}
-+
-+void io_schedule_finish(int token)
-+{
-+	current->in_iowait = token;
-+}
-+
-+/*
-+ * This task is about to go to sleep on IO.  Increment rq->nr_iowait so
-+ * that process accounting knows that this is a task in IO wait state.
-+ *
-+ * But don't do that if it is a deliberate, throttling IO wait (this task
-+ * has set its backing_dev_info: the queue against which it should throttle)
-+ */
-+
-+long __sched io_schedule_timeout(long timeout)
-+{
-+	int token;
-+	long ret;
-+
-+	token = io_schedule_prepare();
-+	ret = schedule_timeout(timeout);
-+	io_schedule_finish(token);
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL(io_schedule_timeout);
-+
-+void __sched io_schedule(void)
-+{
-+	int token;
-+
-+	token = io_schedule_prepare();
-+	schedule();
-+	io_schedule_finish(token);
-+}
-+EXPORT_SYMBOL(io_schedule);
-+
-+/**
-+ * sys_sched_get_priority_max - return maximum RT priority.
-+ * @policy: scheduling class.
-+ *
-+ * Return: On success, this syscall returns the maximum
-+ * rt_priority that can be used by a given scheduling class.
-+ * On failure, a negative error code is returned.
-+ */
-+SYSCALL_DEFINE1(sched_get_priority_max, int, policy)
-+{
-+	int ret = -EINVAL;
-+
-+	switch (policy) {
-+	case SCHED_FIFO:
-+	case SCHED_RR:
-+		ret = MAX_USER_RT_PRIO-1;
-+		break;
-+	case SCHED_NORMAL:
-+	case SCHED_BATCH:
-+	case SCHED_ISO:
-+	case SCHED_IDLEPRIO:
-+		ret = 0;
-+		break;
-+	}
-+	return ret;
-+}
-+
-+/**
-+ * sys_sched_get_priority_min - return minimum RT priority.
-+ * @policy: scheduling class.
-+ *
-+ * Return: On success, this syscall returns the minimum
-+ * rt_priority that can be used by a given scheduling class.
-+ * On failure, a negative error code is returned.
-+ */
-+SYSCALL_DEFINE1(sched_get_priority_min, int, policy)
-+{
-+	int ret = -EINVAL;
-+
-+	switch (policy) {
-+	case SCHED_FIFO:
-+	case SCHED_RR:
-+		ret = 1;
-+		break;
-+	case SCHED_NORMAL:
-+	case SCHED_BATCH:
-+	case SCHED_ISO:
-+	case SCHED_IDLEPRIO:
-+		ret = 0;
-+		break;
-+	}
-+	return ret;
-+}
-+
-+static int sched_rr_get_interval(pid_t pid, struct timespec64 *t)
-+{
-+	struct task_struct *p;
-+	unsigned int time_slice;
-+	struct rq_flags rf;
-+	struct rq *rq;
-+	int retval;
-+
-+	if (pid < 0)
-+		return -EINVAL;
-+
-+	retval = -ESRCH;
-+	rcu_read_lock();
-+	p = find_process_by_pid(pid);
-+	if (!p)
-+		goto out_unlock;
-+
-+	retval = security_task_getscheduler(p);
-+	if (retval)
-+		goto out_unlock;
-+
-+	rq = task_rq_lock(p, &rf);
-+	time_slice = p->policy == SCHED_FIFO ? 0 : MS_TO_NS(task_timeslice(p));
-+	task_rq_unlock(rq, p, &rf);
-+
-+	rcu_read_unlock();
-+	*t = ns_to_timespec64(time_slice);
-+	return 0;
-+
-+out_unlock:
-+	rcu_read_unlock();
-+	return retval;
-+}
-+
-+/**
-+ * sys_sched_rr_get_interval - return the default timeslice of a process.
-+ * @pid: pid of the process.
-+ * @interval: userspace pointer to the timeslice value.
-+ *
-+ * this syscall writes the default timeslice value of a given process
-+ * into the user-space timespec buffer. A value of '0' means infinity.
-+ *
-+ * Return: On success, 0 and the timeslice is in @interval. Otherwise,
-+ * an error code.
-+ */
-+SYSCALL_DEFINE2(sched_rr_get_interval, pid_t, pid,
-+		struct __kernel_timespec __user *, interval)
-+{
-+	struct timespec64 t;
-+	int retval = sched_rr_get_interval(pid, &t);
-+
-+	if (retval == 0)
-+		retval = put_timespec64(&t, interval);
-+
-+	return retval;
-+}
-+
-+#ifdef CONFIG_COMPAT_32BIT_TIME
-+SYSCALL_DEFINE2(sched_rr_get_interval_time32, pid_t, pid,
-+		struct old_timespec32 __user *, interval)
-+{
-+	struct timespec64 t;
-+	int retval = sched_rr_get_interval(pid, &t);
-+
-+	if (retval == 0)
-+		retval = put_old_timespec32(&t, interval);
-+	return retval;
-+}
-+#endif
-+
-+void sched_show_task(struct task_struct *p)
-+{
-+	unsigned long free = 0;
-+	int ppid;
-+
-+	if (!try_get_task_stack(p))
-+		return;
-+
-+	printk(KERN_INFO "%-15.15s %c", p->comm, task_state_to_char(p));
-+
-+	if (p->state == TASK_RUNNING)
-+		printk(KERN_CONT "  running task    ");
-+#ifdef CONFIG_DEBUG_STACK_USAGE
-+	free = stack_not_used(p);
-+#endif
-+	ppid = 0;
-+	rcu_read_lock();
-+	if (pid_alive(p))
-+		ppid = task_pid_nr(rcu_dereference(p->real_parent));
-+	rcu_read_unlock();
-+	printk(KERN_CONT "%5lu %5d %6d 0x%08lx\n", free,
-+		task_pid_nr(p), ppid,
-+		(unsigned long)task_thread_info(p)->flags);
-+
-+	print_worker_info(KERN_INFO, p);
-+	show_stack(p, NULL);
-+	put_task_stack(p);
-+}
-+EXPORT_SYMBOL_GPL(sched_show_task);
-+
-+static inline bool
-+state_filter_match(unsigned long state_filter, struct task_struct *p)
-+{
-+	/* no filter, everything matches */
-+	if (!state_filter)
-+		return true;
-+
-+	/* filter, but doesn't match */
-+	if (!(p->state & state_filter))
-+		return false;
-+
-+	/*
-+	 * When looking for TASK_UNINTERRUPTIBLE skip TASK_IDLE (allows
-+	 * TASK_KILLABLE).
-+	 */
-+	if (state_filter == TASK_UNINTERRUPTIBLE && p->state == TASK_IDLE)
-+		return false;
-+
-+	return true;
-+}
-+
-+void show_state_filter(unsigned long state_filter)
-+{
-+	struct task_struct *g, *p;
-+
-+#if BITS_PER_LONG == 32
-+	printk(KERN_INFO
-+		"  task                PC stack   pid father\n");
-+#else
-+	printk(KERN_INFO
-+		"  task                        PC stack   pid father\n");
-+#endif
-+	rcu_read_lock();
-+	for_each_process_thread(g, p) {
-+		/*
-+		 * reset the NMI-timeout, listing all files on a slow
-+		 * console might take a lot of time:
-+		 * Also, reset softlockup watchdogs on all CPUs, because
-+		 * another CPU might be blocked waiting for us to process
-+		 * an IPI.
-+		 */
-+		touch_nmi_watchdog();
-+		touch_all_softlockup_watchdogs();
-+		if (state_filter_match(state_filter, p))
-+			sched_show_task(p);
-+	}
-+
-+	rcu_read_unlock();
-+	/*
-+	 * Only show locks if all tasks are dumped:
-+	 */
-+	if (!state_filter)
-+		debug_show_all_locks();
-+}
-+
-+void dump_cpu_task(int cpu)
-+{
-+	pr_info("Task dump for CPU %d:\n", cpu);
-+	sched_show_task(cpu_curr(cpu));
-+}
-+
-+#ifdef CONFIG_SMP
-+void set_cpus_allowed_common(struct task_struct *p, const struct cpumask *new_mask)
-+{
-+	cpumask_copy(&p->cpus_mask, new_mask);
-+	p->nr_cpus_allowed = cpumask_weight(new_mask);
-+}
-+
-+void __do_set_cpus_allowed(struct task_struct *p, const struct cpumask *new_mask)
-+{
-+	struct rq *rq = task_rq(p);
-+
-+	lockdep_assert_held(&p->pi_lock);
-+
-+	cpumask_copy(&p->cpus_mask, new_mask);
-+
-+	if (task_queued(p)) {
-+		/*
-+		 * Because __kthread_bind() calls this on blocked tasks without
-+		 * holding rq->lock.
-+		 */
-+		lockdep_assert_held(rq->lock);
-+	}
-+}
-+
-+/*
-+ * Calling do_set_cpus_allowed from outside the scheduler code should not be
-+ * called on a running or queued task. We should be holding pi_lock.
-+ */
-+void do_set_cpus_allowed(struct task_struct *p, const struct cpumask *new_mask)
-+{
-+	__do_set_cpus_allowed(p, new_mask);
-+	if (needs_other_cpu(p, task_cpu(p))) {
-+		struct rq *rq;
-+
-+		rq = __task_rq_lock(p, NULL);
-+		set_task_cpu(p, valid_task_cpu(p));
-+		resched_task(p);
-+		__task_rq_unlock(rq, NULL);
-+	}
-+}
-+#endif
-+
-+/**
-+ * init_idle - set up an idle thread for a given CPU
-+ * @idle: task in question
-+ * @cpu: cpu the idle task belongs to
-+ *
-+ * NOTE: this function does not set the idle thread's NEED_RESCHED
-+ * flag, to make booting more robust.
-+ */
-+void init_idle(struct task_struct *idle, int cpu)
-+{
-+	struct rq *rq = cpu_rq(cpu);
-+	unsigned long flags;
-+
-+	raw_spin_lock_irqsave(&idle->pi_lock, flags);
-+	raw_spin_lock(rq->lock);
-+	idle->last_ran = rq->niffies;
-+	time_slice_expired(idle, rq);
-+	idle->state = TASK_RUNNING;
-+	/* Setting prio to illegal value shouldn't matter when never queued */
-+	idle->prio = PRIO_LIMIT;
-+
-+	kasan_unpoison_task_stack(idle);
-+
-+#ifdef CONFIG_SMP
-+	/*
-+	 * It's possible that init_idle() gets called multiple times on a task,
-+	 * in that case do_set_cpus_allowed() will not do the right thing.
-+	 *
-+	 * And since this is boot we can forgo the serialisation.
-+	 */
-+	set_cpus_allowed_common(idle, cpumask_of(cpu));
-+#ifdef CONFIG_SMT_NICE
-+	idle->smt_bias = 0;
-+#endif
-+#endif
-+	set_rq_task(rq, idle);
-+
-+	/* Silence PROVE_RCU */
-+	rcu_read_lock();
-+	set_task_cpu(idle, cpu);
-+	rcu_read_unlock();
-+
-+	rq->idle = idle;
-+	rcu_assign_pointer(rq->curr, idle);
-+	idle->on_rq = TASK_ON_RQ_QUEUED;
-+	raw_spin_unlock(rq->lock);
-+	raw_spin_unlock_irqrestore(&idle->pi_lock, flags);
-+
-+	/* Set the preempt count _outside_ the spinlocks! */
-+	init_idle_preempt_count(idle, cpu);
-+
-+	ftrace_graph_init_idle_task(idle, cpu);
-+	vtime_init_idle(idle, cpu);
-+#ifdef CONFIG_SMP
-+	sprintf(idle->comm, "%s/%d", INIT_TASK_COMM, cpu);
-+#endif
-+}
-+
-+int cpuset_cpumask_can_shrink(const struct cpumask __maybe_unused *cur,
-+			      const struct cpumask __maybe_unused *trial)
-+{
-+	return 1;
-+}
-+
-+int task_can_attach(struct task_struct *p,
-+		    const struct cpumask *cs_cpus_allowed)
-+{
-+	int ret = 0;
-+
-+	/*
-+	 * Kthreads which disallow setaffinity shouldn't be moved
-+	 * to a new cpuset; we don't want to change their CPU
-+	 * affinity and isolating such threads by their set of
-+	 * allowed nodes is unnecessary.  Thus, cpusets are not
-+	 * applicable for such threads.  This prevents checking for
-+	 * success of set_cpus_allowed_ptr() on all attached tasks
-+	 * before cpus_mask may be changed.
-+	 */
-+	if (p->flags & PF_NO_SETAFFINITY)
-+		ret = -EINVAL;
-+
-+	return ret;
-+}
-+
-+void resched_cpu(int cpu)
-+{
-+	struct rq *rq = cpu_rq(cpu);
-+	struct rq_flags rf;
-+
-+	rq_lock_irqsave(rq, &rf);
-+	if (cpu_online(cpu) || cpu == smp_processor_id())
-+		resched_curr(rq);
-+	rq_unlock_irqrestore(rq, &rf);
-+}
-+
-+#ifdef CONFIG_SMP
-+#ifdef CONFIG_NO_HZ_COMMON
-+void select_nohz_load_balancer(int stop_tick)
-+{
-+}
-+
-+void set_cpu_sd_state_idle(void) {}
-+void nohz_balance_enter_idle(int cpu) {}
-+
-+/*
-+ * In the semi idle case, use the nearest busy CPU for migrating timers
-+ * from an idle CPU.  This is good for power-savings.
-+ *
-+ * We don't do similar optimization for completely idle system, as
-+ * selecting an idle CPU will add more delays to the timers than intended
-+ * (as that CPU's timer base may not be uptodate wrt jiffies etc).
-+ */
-+int get_nohz_timer_target(void)
-+{
-+	int i, cpu = smp_processor_id();
-+	struct sched_domain *sd;
-+
-+	if (!idle_cpu(cpu) && housekeeping_cpu(cpu, HK_FLAG_TIMER))
-+		return cpu;
-+
-+	rcu_read_lock();
-+	for_each_domain(cpu, sd) {
-+		for_each_cpu(i, sched_domain_span(sd)) {
-+			if (cpu == i)
-+				continue;
-+
-+			if (!idle_cpu(i) && housekeeping_cpu(i, HK_FLAG_TIMER)) {
-+ 				cpu = i;
-+				cpu = i;
-+				goto unlock;
-+			}
-+		}
-+	}
-+
-+	if (!housekeeping_cpu(cpu, HK_FLAG_TIMER))
-+		cpu = housekeeping_any_cpu(HK_FLAG_TIMER);
-+unlock:
-+	rcu_read_unlock();
-+	return cpu;
-+}
-+
-+/*
-+ * When add_timer_on() enqueues a timer into the timer wheel of an
-+ * idle CPU then this timer might expire before the next timer event
-+ * which is scheduled to wake up that CPU. In case of a completely
-+ * idle system the next event might even be infinite time into the
-+ * future. wake_up_idle_cpu() ensures that the CPU is woken up and
-+ * leaves the inner idle loop so the newly added timer is taken into
-+ * account when the CPU goes back to idle and evaluates the timer
-+ * wheel for the next timer event.
-+ */
-+void wake_up_idle_cpu(int cpu)
-+{
-+	if (cpu == smp_processor_id())
-+		return;
-+
-+	if (set_nr_and_not_polling(cpu_rq(cpu)->idle))
-+		smp_sched_reschedule(cpu);
-+	else
-+		trace_sched_wake_idle_without_ipi(cpu);
-+}
-+
-+static bool wake_up_full_nohz_cpu(int cpu)
-+{
-+	/*
-+	 * We just need the target to call irq_exit() and re-evaluate
-+	 * the next tick. The nohz full kick at least implies that.
-+	 * If needed we can still optimize that later with an
-+	 * empty IRQ.
-+	 */
-+	if (cpu_is_offline(cpu))
-+		return true;  /* Don't try to wake offline CPUs. */
-+	if (tick_nohz_full_cpu(cpu)) {
-+		if (cpu != smp_processor_id() ||
-+		    tick_nohz_tick_stopped())
-+			tick_nohz_full_kick_cpu(cpu);
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+/*
-+ * Wake up the specified CPU.  If the CPU is going offline, it is the
-+ * caller's responsibility to deal with the lost wakeup, for example,
-+ * by hooking into the CPU_DEAD notifier like timers and hrtimers do.
-+ */
-+void wake_up_nohz_cpu(int cpu)
-+{
-+	if (!wake_up_full_nohz_cpu(cpu))
-+		wake_up_idle_cpu(cpu);
-+}
-+#endif /* CONFIG_NO_HZ_COMMON */
-+
-+/*
-+ * Change a given task's CPU affinity. Migrate the thread to a
-+ * proper CPU and schedule it away if the CPU it's executing on
-+ * is removed from the allowed bitmask.
-+ *
-+ * NOTE: the caller must have a valid reference to the task, the
-+ * task must not exit() & deallocate itself prematurely. The
-+ * call is not atomic; no spinlocks may be held.
-+ */
-+static int __set_cpus_allowed_ptr(struct task_struct *p,
-+				  const struct cpumask *new_mask, bool check)
-+{
-+	const struct cpumask *cpu_valid_mask = cpu_active_mask;
-+	bool queued = false, running_wrong = false, kthread;
-+	struct cpumask old_mask;
-+	unsigned int dest_cpu;
-+	struct rq_flags rf;
-+	struct rq *rq;
-+	int ret = 0;
-+
-+	rq = task_rq_lock(p, &rf);
-+	update_rq_clock(rq);
-+
-+	kthread = !!(p->flags & PF_KTHREAD);
-+	if (kthread) {
-+		/*
-+		 * Kernel threads are allowed on online && !active CPUs
-+		 */
-+		cpu_valid_mask = cpu_online_mask;
-+	}
-+
-+	/*
-+	 * Must re-check here, to close a race against __kthread_bind(),
-+	 * sched_setaffinity() is not guaranteed to observe the flag.
-+	 */
-+	if (check && (p->flags & PF_NO_SETAFFINITY)) {
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
-+	cpumask_copy(&old_mask, p->cpus_ptr);
-+	if (cpumask_equal(&old_mask, new_mask))
-+		goto out;
-+
-+	dest_cpu = cpumask_any_and(cpu_valid_mask, new_mask);
-+	if (dest_cpu >= nr_cpu_ids) {
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
-+	queued = task_queued(p);
-+	__do_set_cpus_allowed(p, new_mask);
-+
-+	if (kthread) {
-+		/*
-+		 * For kernel threads that do indeed end up on online &&
-+		 * !active we want to ensure they are strict per-CPU threads.
-+		 */
-+		WARN_ON(cpumask_intersects(new_mask, cpu_online_mask) &&
-+			!cpumask_intersects(new_mask, cpu_active_mask) &&
-+			p->nr_cpus_allowed != 1);
-+	}
-+
-+	/* Can the task run on the task's current CPU? If so, we're done */
-+	if (cpumask_test_cpu(task_cpu(p), new_mask))
-+		goto out;
-+
-+	if (task_running(rq, p)) {
-+		/* Task is running on the wrong cpu now, reschedule it. */
-+		if (rq == this_rq()) {
-+			set_task_cpu(p, dest_cpu);
-+			set_tsk_need_resched(p);
-+			running_wrong = true;
-+		} else
-+			resched_task(p);
-+	} else {
-+		if (queued) {
-+			/*
-+			 * Switch runqueue locks after dequeueing the task
-+			 * here while still holding the pi_lock to be holding
-+			 * the correct lock for enqueueing.
-+			 */
-+			dequeue_task(rq, p, 0);
-+			rq_unlock(rq);
-+
-+			rq = cpu_rq(dest_cpu);
-+			rq_lock(rq);
-+		}
-+		set_task_cpu(p, dest_cpu);
-+		if (queued)
-+			enqueue_task(rq, p, 0);
-+	}
-+	if (queued)
-+		try_preempt(p, rq);
-+	if (running_wrong)
-+		preempt_disable();
-+out:
-+	task_rq_unlock(rq, p, &rf);
-+
-+	if (running_wrong) {
-+		__schedule(true);
-+		preempt_enable();
-+	}
-+
-+	return ret;
-+}
-+
-+int set_cpus_allowed_ptr(struct task_struct *p, const struct cpumask *new_mask)
-+{
-+	return __set_cpus_allowed_ptr(p, new_mask, false);
-+}
-+EXPORT_SYMBOL_GPL(set_cpus_allowed_ptr);
-+
-+#ifdef CONFIG_HOTPLUG_CPU
-+/*
-+ * Run through task list and find tasks affined to the dead cpu, then remove
-+ * that cpu from the list, enable cpu0 and set the zerobound flag. Must hold
-+ * cpu 0 and src_cpu's runqueue locks. We should be holding both rq lock and
-+ * pi_lock to change cpus_mask but it's not going to matter here.
-+ */
-+static void bind_zero(int src_cpu)
-+{
-+	struct task_struct *p, *t;
-+	struct rq *rq0;
-+	int bound = 0;
-+
-+	if (src_cpu == 0)
-+		return;
-+
-+	rq0 = cpu_rq(0);
-+
-+	do_each_thread(t, p) {
-+		if (cpumask_test_cpu(src_cpu, p->cpus_ptr)) {
-+			bool local = (task_cpu(p) == src_cpu);
-+			struct rq *rq = task_rq(p);
-+
-+			/* task_running is the cpu stopper thread */
-+			if (local && task_running(rq, p))
-+				continue;
-+			atomic_clear_cpu(src_cpu, &p->cpus_mask);
-+			atomic_set_cpu(0, &p->cpus_mask);
-+			p->zerobound = true;
-+			bound++;
-+			if (local) {
-+				bool queued = task_queued(p);
-+
-+				if (queued)
-+					dequeue_task(rq, p, 0);
-+				set_task_cpu(p, 0);
-+				if (queued)
-+					enqueue_task(rq0, p, 0);
-+			}
-+		}
-+	} while_each_thread(t, p);
-+
-+	if (bound) {
-+		printk(KERN_INFO "MuQSS removed affinity for %d processes to cpu %d\n",
-+		       bound, src_cpu);
-+	}
-+}
-+
-+/* Find processes with the zerobound flag and reenable their affinity for the
-+ * CPU coming alive. */
-+static void unbind_zero(int src_cpu)
-+{
-+	int unbound = 0, zerobound = 0;
-+	struct task_struct *p, *t;
-+
-+	if (src_cpu == 0)
-+		return;
-+
-+	do_each_thread(t, p) {
-+		if (!p->mm)
-+			p->zerobound = false;
-+		if (p->zerobound) {
-+			unbound++;
-+			cpumask_set_cpu(src_cpu, &p->cpus_mask);
-+			/* Once every CPU affinity has been re-enabled, remove
-+			 * the zerobound flag */
-+			if (cpumask_subset(cpu_possible_mask, p->cpus_ptr)) {
-+				p->zerobound = false;
-+				zerobound++;
-+			}
-+		}
-+	} while_each_thread(t, p);
-+
-+	if (unbound) {
-+		printk(KERN_INFO "MuQSS added affinity for %d processes to cpu %d\n",
-+		       unbound, src_cpu);
-+	}
-+	if (zerobound) {
-+		printk(KERN_INFO "MuQSS released forced binding to cpu0 for %d processes\n",
-+		       zerobound);
-+	}
-+}
-+
-+/*
-+ * Ensure that the idle task is using init_mm right before its cpu goes
-+ * offline.
-+ */
-+void idle_task_exit(void)
-+{
-+	struct mm_struct *mm = current->active_mm;
-+
-+	BUG_ON(cpu_online(smp_processor_id()));
-+
-+	if (mm != &init_mm) {
-+		switch_mm(mm, &init_mm, current);
-+		current->active_mm = &init_mm;
-+		finish_arch_post_lock_switch();
-+	}
-+	mmdrop(mm);
-+}
-+#else /* CONFIG_HOTPLUG_CPU */
-+static void unbind_zero(int src_cpu) {}
-+#endif /* CONFIG_HOTPLUG_CPU */
-+
-+void sched_set_stop_task(int cpu, struct task_struct *stop)
-+{
-+	struct sched_param stop_param = { .sched_priority = STOP_PRIO };
-+	struct sched_param start_param = { .sched_priority = 0 };
-+	struct task_struct *old_stop = cpu_rq(cpu)->stop;
-+
-+	if (stop) {
-+		/*
-+		 * Make it appear like a SCHED_FIFO task, its something
-+		 * userspace knows about and won't get confused about.
-+		 *
-+		 * Also, it will make PI more or less work without too
-+		 * much confusion -- but then, stop work should not
-+		 * rely on PI working anyway.
-+		 */
-+		sched_setscheduler_nocheck(stop, SCHED_FIFO, &stop_param);
-+	}
-+
-+	cpu_rq(cpu)->stop = stop;
-+
-+	if (old_stop) {
-+		/*
-+		 * Reset it back to a normal scheduling policy so that
-+		 * it can die in pieces.
-+		 */
-+		sched_setscheduler_nocheck(old_stop, SCHED_NORMAL, &start_param);
-+	}
-+}
-+
-+#if defined(CONFIG_SCHED_DEBUG) && defined(CONFIG_SYSCTL)
-+
-+static struct ctl_table sd_ctl_dir[] = {
-+	{
-+		.procname	= "sched_domain",
-+		.mode		= 0555,
-+	},
-+	{}
-+};
-+
-+static struct ctl_table sd_ctl_root[] = {
-+	{
-+		.procname	= "kernel",
-+		.mode		= 0555,
-+		.child		= sd_ctl_dir,
-+	},
-+	{}
-+};
-+
-+static struct ctl_table *sd_alloc_ctl_entry(int n)
-+{
-+	struct ctl_table *entry =
-+		kcalloc(n, sizeof(struct ctl_table), GFP_KERNEL);
-+
-+	return entry;
-+}
-+
-+static void sd_free_ctl_entry(struct ctl_table **tablep)
-+{
-+	struct ctl_table *entry;
-+
-+	/*
-+	 * In the intermediate directories, both the child directory and
-+	 * procname are dynamically allocated and could fail but the mode
-+	 * will always be set. In the lowest directory the names are
-+	 * static strings and all have proc handlers.
-+	 */
-+	for (entry = *tablep; entry->mode; entry++) {
-+		if (entry->child)
-+			sd_free_ctl_entry(&entry->child);
-+		if (entry->proc_handler == NULL)
-+			kfree(entry->procname);
-+	}
-+
-+	kfree(*tablep);
-+	*tablep = NULL;
-+}
-+
-+static void
-+set_table_entry(struct ctl_table *entry,
-+		const char *procname, void *data, int maxlen,
-+		umode_t mode, proc_handler *proc_handler)
-+{
-+	entry->procname = procname;
-+	entry->data = data;
-+	entry->maxlen = maxlen;
-+	entry->mode = mode;
-+	entry->proc_handler = proc_handler;
-+}
-+
-+static struct ctl_table *
-+sd_alloc_ctl_domain_table(struct sched_domain *sd)
-+{
-+	struct ctl_table *table = sd_alloc_ctl_entry(9);
-+
-+	if (table == NULL)
-+		return NULL;
-+
-+	set_table_entry(&table[0], "min_interval",	  &sd->min_interval,	    sizeof(long), 0644, proc_doulongvec_minmax);
-+	set_table_entry(&table[1], "max_interval",	  &sd->max_interval,	    sizeof(long), 0644, proc_doulongvec_minmax);
-+	set_table_entry(&table[2], "busy_factor",	  &sd->busy_factor,	    sizeof(int),  0644, proc_dointvec_minmax);
-+	set_table_entry(&table[3], "imbalance_pct",	  &sd->imbalance_pct,	    sizeof(int),  0644, proc_dointvec_minmax);
-+	set_table_entry(&table[4], "cache_nice_tries",	  &sd->cache_nice_tries,    sizeof(int),  0644, proc_dointvec_minmax);
-+	set_table_entry(&table[5], "flags",		  &sd->flags,		    sizeof(int),  0644, proc_dointvec_minmax);
-+	set_table_entry(&table[6], "max_newidle_lb_cost", &sd->max_newidle_lb_cost, sizeof(long), 0644, proc_doulongvec_minmax);
-+	set_table_entry(&table[7], "name",		  sd->name,	       CORENAME_MAX_SIZE, 0444, proc_dostring);
-+	/* &table[8] is terminator */
-+
-+	return table;
-+}
-+
-+static struct ctl_table *sd_alloc_ctl_cpu_table(int cpu)
-+{
-+	struct ctl_table *entry, *table;
-+	struct sched_domain *sd;
-+	int domain_num = 0, i;
-+	char buf[32];
-+
-+	for_each_domain(cpu, sd)
-+		domain_num++;
-+	entry = table = sd_alloc_ctl_entry(domain_num + 1);
-+	if (table == NULL)
-+		return NULL;
-+
-+	i = 0;
-+	for_each_domain(cpu, sd) {
-+		snprintf(buf, 32, "domain%d", i);
-+		entry->procname = kstrdup(buf, GFP_KERNEL);
-+		entry->mode = 0555;
-+		entry->child = sd_alloc_ctl_domain_table(sd);
-+		entry++;
-+		i++;
-+	}
-+	return table;
-+}
-+
-+static cpumask_var_t sd_sysctl_cpus;
-+static struct ctl_table_header *sd_sysctl_header;
-+
-+void register_sched_domain_sysctl(void)
-+{
-+	static struct ctl_table *cpu_entries;
-+	static struct ctl_table **cpu_idx;
-+	char buf[32];
-+	int i;
-+
-+	if (!cpu_entries) {
-+		cpu_entries = sd_alloc_ctl_entry(num_possible_cpus() + 1);
-+		if (!cpu_entries)
-+			return;
-+
-+		WARN_ON(sd_ctl_dir[0].child);
-+		sd_ctl_dir[0].child = cpu_entries;
-+	}
-+
-+	if (!cpu_idx) {
-+		struct ctl_table *e = cpu_entries;
-+
-+		cpu_idx = kcalloc(nr_cpu_ids, sizeof(struct ctl_table*), GFP_KERNEL);
-+		if (!cpu_idx)
-+			return;
-+
-+		/* deal with sparse possible map */
-+		for_each_possible_cpu(i) {
-+			cpu_idx[i] = e;
-+			e++;
-+		}
-+	}
-+
-+	if (!cpumask_available(sd_sysctl_cpus)) {
-+		if (!alloc_cpumask_var(&sd_sysctl_cpus, GFP_KERNEL))
-+			return;
-+
-+		/* init to possible to not have holes in @cpu_entries */
-+		cpumask_copy(sd_sysctl_cpus, cpu_possible_mask);
-+	}
-+
-+	for_each_cpu(i, sd_sysctl_cpus) {
-+		struct ctl_table *e = cpu_idx[i];
-+
-+		if (e->child)
-+			sd_free_ctl_entry(&e->child);
-+
-+		if (!e->procname) {
-+			snprintf(buf, 32, "cpu%d", i);
-+			e->procname = kstrdup(buf, GFP_KERNEL);
-+		}
-+		e->mode = 0555;
-+		e->child = sd_alloc_ctl_cpu_table(i);
-+
-+		__cpumask_clear_cpu(i, sd_sysctl_cpus);
-+	}
-+
-+	WARN_ON(sd_sysctl_header);
-+	sd_sysctl_header = register_sysctl_table(sd_ctl_root);
-+}
-+
-+void dirty_sched_domain_sysctl(int cpu)
-+{
-+	if (cpumask_available(sd_sysctl_cpus))
-+		__cpumask_set_cpu(cpu, sd_sysctl_cpus);
-+}
-+
-+/* may be called multiple times per register */
-+void unregister_sched_domain_sysctl(void)
-+{
-+	unregister_sysctl_table(sd_sysctl_header);
-+	sd_sysctl_header = NULL;
-+}
-+#endif /* CONFIG_SYSCTL */
-+
-+void set_rq_online(struct rq *rq)
-+{
-+	if (!rq->online) {
-+		cpumask_set_cpu(cpu_of(rq), rq->rd->online);
-+		rq->online = true;
-+	}
-+}
-+
-+void set_rq_offline(struct rq *rq)
-+{
-+	if (rq->online) {
-+		int cpu = cpu_of(rq);
-+
-+		cpumask_clear_cpu(cpu, rq->rd->online);
-+		rq->online = false;
-+		clear_cpuidle_map(cpu);
-+	}
-+}
-+
-+/*
-+ * used to mark begin/end of suspend/resume:
-+ */
-+static int num_cpus_frozen;
-+
-+/*
-+ * Update cpusets according to cpu_active mask.  If cpusets are
-+ * disabled, cpuset_update_active_cpus() becomes a simple wrapper
-+ * around partition_sched_domains().
-+ *
-+ * If we come here as part of a suspend/resume, don't touch cpusets because we
-+ * want to restore it back to its original state upon resume anyway.
-+ */
-+static void cpuset_cpu_active(void)
-+{
-+	if (cpuhp_tasks_frozen) {
-+		/*
-+		 * num_cpus_frozen tracks how many CPUs are involved in suspend
-+		 * resume sequence. As long as this is not the last online
-+		 * operation in the resume sequence, just build a single sched
-+		 * domain, ignoring cpusets.
-+		 */
-+		partition_sched_domains(1, NULL, NULL);
-+		if (--num_cpus_frozen)
-+			return;
-+		/*
-+		 * This is the last CPU online operation. So fall through and
-+		 * restore the original sched domains by considering the
-+		 * cpuset configurations.
-+		 */
-+		cpuset_force_rebuild();
-+	}
-+
-+	cpuset_update_active_cpus();
-+}
-+
-+static int cpuset_cpu_inactive(unsigned int cpu)
-+{
-+	if (!cpuhp_tasks_frozen) {
-+		cpuset_update_active_cpus();
-+	} else {
-+		num_cpus_frozen++;
-+		partition_sched_domains(1, NULL, NULL);
-+	}
-+	return 0;
-+}
-+
-+int sched_cpu_activate(unsigned int cpu)
-+{
-+	struct rq *rq = cpu_rq(cpu);
-+	struct rq_flags rf;
-+
-+#ifdef CONFIG_SCHED_SMT
-+	/*
-+	 * When going up, increment the number of cores with SMT present.
-+	 */
-+	if (cpumask_weight(cpu_smt_mask(cpu)) == 2)
-+		static_branch_inc_cpuslocked(&sched_smt_present);
-+#endif
-+	set_cpu_active(cpu, true);
-+
-+	if (sched_smp_initialized) {
-+		sched_domains_numa_masks_set(cpu);
-+		cpuset_cpu_active();
-+	}
-+
-+	/*
-+	 * Put the rq online, if not already. This happens:
-+	 *
-+	 * 1) In the early boot process, because we build the real domains
-+	 *    after all CPUs have been brought up.
-+	 *
-+	 * 2) At runtime, if cpuset_cpu_active() fails to rebuild the
-+	 *    domains.
-+	 */
-+	rq_lock_irqsave(rq, &rf);
-+	if (rq->rd) {
-+		BUG_ON(!cpumask_test_cpu(cpu, rq->rd->span));
-+		set_rq_online(rq);
-+	}
-+	unbind_zero(cpu);
-+	rq_unlock_irqrestore(rq, &rf);
-+
-+	return 0;
-+}
-+
-+int sched_cpu_deactivate(unsigned int cpu)
-+{
-+	int ret;
-+
-+	set_cpu_active(cpu, false);
-+	/*
-+	 * We've cleared cpu_active_mask, wait for all preempt-disabled and RCU
-+	 * users of this state to go away such that all new such users will
-+	 * observe it.
-+	 *
-+	 * Do sync before park smpboot threads to take care the rcu boost case.
-+	 */
-+	synchronize_rcu();
-+
-+#ifdef CONFIG_SCHED_SMT
-+	/*
-+	 * When going down, decrement the number of cores with SMT present.
-+	 */
-+	if (cpumask_weight(cpu_smt_mask(cpu)) == 2)
-+		static_branch_dec_cpuslocked(&sched_smt_present);
-+#endif
-+
-+	if (!sched_smp_initialized)
-+		return 0;
-+
-+	ret = cpuset_cpu_inactive(cpu);
-+	if (ret) {
-+		set_cpu_active(cpu, true);
-+		return ret;
-+	}
-+	sched_domains_numa_masks_clear(cpu);
-+	return 0;
-+}
-+
-+int sched_cpu_starting(unsigned int cpu)
-+{
-+	sched_tick_start(cpu);
-+	return 0;
-+}
-+
-+#ifdef CONFIG_HOTPLUG_CPU
-+int sched_cpu_dying(unsigned int cpu)
-+{
-+	struct rq *rq = cpu_rq(cpu);
-+	unsigned long flags;
-+
-+	/* Handle pending wakeups and then migrate everything off */
-+	sched_ttwu_pending();
-+	sched_tick_stop(cpu);
-+
-+	local_irq_save(flags);
-+	double_rq_lock(rq, cpu_rq(0));
-+	if (rq->rd) {
-+		BUG_ON(!cpumask_test_cpu(cpu, rq->rd->span));
-+		set_rq_offline(rq);
-+	}
-+	bind_zero(cpu);
-+	double_rq_unlock(rq, cpu_rq(0));
-+	sched_start_tick(rq, cpu);
-+	hrexpiry_clear(rq);
-+	local_irq_restore(flags);
-+
-+	return 0;
-+}
-+#endif
-+
-+#if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
-+/*
-+ * Cheaper version of the below functions in case support for SMT and MC is
-+ * compiled in but CPUs have no siblings.
-+ */
-+static bool sole_cpu_idle(struct rq *rq)
-+{
-+	return rq_idle(rq);
-+}
-+#endif
-+#ifdef CONFIG_SCHED_SMT
-+static const cpumask_t *thread_cpumask(int cpu)
-+{
-+	return topology_sibling_cpumask(cpu);
-+}
-+/* All this CPU's SMT siblings are idle */
-+static bool siblings_cpu_idle(struct rq *rq)
-+{
-+	return cpumask_subset(&rq->thread_mask, &cpu_idle_map);
-+}
-+#endif
-+#ifdef CONFIG_SCHED_MC
-+static const cpumask_t *core_cpumask(int cpu)
-+{
-+	return topology_core_cpumask(cpu);
-+}
-+/* All this CPU's shared cache siblings are idle */
-+static bool cache_cpu_idle(struct rq *rq)
-+{
-+	return cpumask_subset(&rq->core_mask, &cpu_idle_map);
-+}
-+/* MC siblings CPU mask which share the same LLC */
-+static const cpumask_t *llc_core_cpumask(int cpu)
-+{
-+	return per_cpu(cpu_llc_shared_map, cpu);
-+}
-+#endif
-+
-+enum sched_domain_level {
-+	SD_LV_NONE = 0,
-+	SD_LV_SIBLING,
-+	SD_LV_MC,
-+	SD_LV_BOOK,
-+	SD_LV_CPU,
-+	SD_LV_NODE,
-+	SD_LV_ALLNODES,
-+	SD_LV_MAX
-+};
-+
-+void __init sched_init_smp(void)
-+{
-+	struct rq *rq, *other_rq, *leader = cpu_rq(0);
-+	struct sched_domain *sd;
-+	int cpu, other_cpu, i;
-+#ifdef CONFIG_SCHED_SMT
-+	bool smt_threads = false;
-+#endif
-+	sched_init_numa();
-+
-+	/*
-+	 * There's no userspace yet to cause hotplug operations; hence all the
-+	 * cpu masks are stable and all blatant races in the below code cannot
-+	 * happen.
-+	 */
-+	mutex_lock(&sched_domains_mutex);
-+	sched_init_domains(cpu_active_mask);
-+	mutex_unlock(&sched_domains_mutex);
-+
-+	/* Move init over to a non-isolated CPU */
-+	if (set_cpus_allowed_ptr(current, housekeeping_cpumask(HK_FLAG_DOMAIN)) < 0)
-+		BUG();
-+
-+	local_irq_disable();
-+	mutex_lock(&sched_domains_mutex);
-+	lock_all_rqs();
-+
-+	printk(KERN_INFO "MuQSS possible/present/online CPUs: %d/%d/%d\n",
-+		num_possible_cpus(), num_present_cpus(), num_online_cpus());
-+
-+	/*
-+	 * Set up the relative cache distance of each online cpu from each
-+	 * other in a simple array for quick lookup. Locality is determined
-+	 * by the closest sched_domain that CPUs are separated by. CPUs with
-+	 * shared cache in SMT and MC are treated as local. Separate CPUs
-+	 * (within the same package or physically) within the same node are
-+	 * treated as not local. CPUs not even in the same domain (different
-+	 * nodes) are treated as very distant.
-+	 */
-+	for (cpu = num_online_cpus() - 1; cpu >= 0; cpu--) {
-+		rq = cpu_rq(cpu);
-+		leader = NULL;
-+		/* First check if this cpu is in the same node */
-+		for_each_domain(cpu, sd) {
-+			if (sd->level > SD_LV_MC)
-+				continue;
-+			if (rqshare != RQSHARE_ALL)
-+				leader = NULL;
-+			/* Set locality to local node if not already found lower */
-+			for_each_cpu(other_cpu, sched_domain_span(sd)) {
-+				if (rqshare >= RQSHARE_SMP) {
-+					other_rq = cpu_rq(other_cpu);
-+
-+					/* Set the smp_leader to the first CPU */
-+					if (!leader)
-+						leader = rq;
-+					other_rq->smp_leader = leader;
-+				}
-+				if (rq->cpu_locality[other_cpu] > LOCALITY_SMP)
-+					rq->cpu_locality[other_cpu] = LOCALITY_SMP;
-+			}
-+		}
-+
-+		/*
-+		 * Each runqueue has its own function in case it doesn't have
-+		 * siblings of its own allowing mixed topologies.
-+		 */
-+#ifdef CONFIG_SCHED_MC
-+		leader = NULL;
-+		if (cpumask_weight(core_cpumask(cpu)) > 1) {
-+			cpumask_copy(&rq->core_mask, llc_core_cpumask(cpu));
-+			cpumask_clear_cpu(cpu, &rq->core_mask);
-+			for_each_cpu(other_cpu, core_cpumask(cpu)) {
-+				if (rqshare == RQSHARE_MC ||
-+					(rqshare == RQSHARE_MC_LLC && cpumask_test_cpu(other_cpu, llc_core_cpumask(cpu)))) {
-+					other_rq = cpu_rq(other_cpu);
-+
-+					/* Set the mc_leader to the first CPU */
-+					if (!leader)
-+						leader = rq;
-+					other_rq->mc_leader = leader;
-+				}
-+				if (rq->cpu_locality[other_cpu] > LOCALITY_MC) {
-+					/* this is to get LLC into play even in case LLC sharing is not used */
-+					if (cpumask_test_cpu(other_cpu, llc_core_cpumask(cpu)))
-+						rq->cpu_locality[other_cpu] = LOCALITY_MC_LLC;
-+					else
-+						rq->cpu_locality[other_cpu] = LOCALITY_MC;
-+				}
-+			}
-+			rq->cache_idle = cache_cpu_idle;
-+		}
-+#endif
-+#ifdef CONFIG_SCHED_SMT
-+		leader = NULL;
-+		if (cpumask_weight(thread_cpumask(cpu)) > 1) {
-+			cpumask_copy(&rq->thread_mask, thread_cpumask(cpu));
-+			cpumask_clear_cpu(cpu, &rq->thread_mask);
-+			for_each_cpu(other_cpu, thread_cpumask(cpu)) {
-+				if (rqshare == RQSHARE_SMT) {
-+					other_rq = cpu_rq(other_cpu);
-+
-+					/* Set the smt_leader to the first CPU */
-+					if (!leader)
-+						leader = rq;
-+					other_rq->smt_leader = leader;
-+				}
-+				if (rq->cpu_locality[other_cpu] > LOCALITY_SMT)
-+					rq->cpu_locality[other_cpu] = LOCALITY_SMT;
-+			}
-+			rq->siblings_idle = siblings_cpu_idle;
-+			smt_threads = true;
-+		}
-+#endif
-+	}
-+
-+#ifdef CONFIG_SMT_NICE
-+	if (smt_threads) {
-+		check_siblings = &check_smt_siblings;
-+		wake_siblings = &wake_smt_siblings;
-+		smt_schedule = &smt_should_schedule;
-+	}
-+#endif
-+	unlock_all_rqs();
-+	mutex_unlock(&sched_domains_mutex);
-+
-+	for_each_online_cpu(cpu) {
-+		rq = cpu_rq(cpu);
-+		for_each_online_cpu(other_cpu) {
-+			printk(KERN_DEBUG "MuQSS locality CPU %d to %d: %d\n", cpu, other_cpu, rq->cpu_locality[other_cpu]);
-+		}
-+	}
-+
-+	for_each_online_cpu(cpu) {
-+		rq = cpu_rq(cpu);
-+		leader = rq->smp_leader;
-+
-+		rq_lock(rq);
-+		if (leader && rq != leader) {
-+			printk(KERN_INFO "MuQSS sharing SMP runqueue from CPU %d to CPU %d\n",
-+			       leader->cpu, rq->cpu);
-+			kfree(rq->node);
-+			kfree(rq->sl);
-+			kfree(rq->lock);
-+			rq->node = leader->node;
-+			rq->sl = leader->sl;
-+			rq->lock = leader->lock;
-+			barrier();
-+			/* To make up for not unlocking the freed runlock */
-+			preempt_enable();
-+		} else
-+			rq_unlock(rq);
-+	}
-+
-+#ifdef CONFIG_SCHED_MC
-+	for_each_online_cpu(cpu) {
-+		rq = cpu_rq(cpu);
-+		leader = rq->mc_leader;
-+
-+		rq_lock(rq);
-+		if (leader && rq != leader) {
-+			printk(KERN_INFO "MuQSS sharing MC runqueue from CPU %d to CPU %d\n",
-+			       leader->cpu, rq->cpu);
-+			kfree(rq->node);
-+			kfree(rq->sl);
-+			kfree(rq->lock);
-+			rq->node = leader->node;
-+			rq->sl = leader->sl;
-+			rq->lock = leader->lock;
-+			barrier();
-+			/* To make up for not unlocking the freed runlock */
-+			preempt_enable();
-+		} else
-+			rq_unlock(rq);
-+	}
-+#endif /* CONFIG_SCHED_MC */
-+
-+#ifdef CONFIG_SCHED_SMT
-+	for_each_online_cpu(cpu) {
-+		rq = cpu_rq(cpu);
-+
-+		leader = rq->smt_leader;
-+
-+		rq_lock(rq);
-+		if (leader && rq != leader) {
-+			printk(KERN_INFO "MuQSS sharing SMT runqueue from CPU %d to CPU %d\n",
-+			       leader->cpu, rq->cpu);
-+			kfree(rq->node);
-+			kfree(rq->sl);
-+			kfree(rq->lock);
-+			rq->node = leader->node;
-+			rq->sl = leader->sl;
-+			rq->lock = leader->lock;
-+			barrier();
-+			/* To make up for not unlocking the freed runlock */
-+			preempt_enable();
-+		} else
-+			rq_unlock(rq);
-+	}
-+#endif /* CONFIG_SCHED_SMT */
-+
-+	local_irq_enable();
-+
-+	total_runqueues = 0;
-+	for_each_online_cpu(cpu) {
-+		int locality, total_rqs = 0, total_cpus = 0;
-+
-+		rq = cpu_rq(cpu);
-+		if (
-+#ifdef CONFIG_SCHED_MC
-+		    (rq->mc_leader == rq) &&
-+#endif
-+#ifdef CONFIG_SCHED_SMT
-+		    (rq->smt_leader == rq) &&
-+#endif
-+		    (rq->smp_leader == rq)) {
-+			total_runqueues++;
-+		}
-+
-+		for (locality = LOCALITY_SAME; locality <= LOCALITY_DISTANT; locality++) {
-+			int selected_cpus[NR_CPUS], selected_cpu_cnt, selected_cpu_idx, test_cpu_idx, cpu_idx, best_locality, test_cpu;
-+			int ordered_cpus[NR_CPUS], ordered_cpus_idx;
-+
-+			ordered_cpus_idx = -1;
-+			selected_cpu_cnt = 0;
-+
-+			for_each_online_cpu(test_cpu) {
-+				if (cpu < num_online_cpus() / 2)
-+					other_cpu = cpu + test_cpu;
-+				else
-+					other_cpu = cpu - test_cpu;
-+				if (other_cpu < 0)
-+					other_cpu += num_online_cpus();
-+				else
-+					other_cpu %= num_online_cpus();
-+				/* gather CPUs of the same locality */
-+				if (rq->cpu_locality[other_cpu] == locality) {
-+					selected_cpus[selected_cpu_cnt] = other_cpu;
-+					selected_cpu_cnt++;
-+				}
-+			}
-+
-+			/* reserve first CPU as starting point */
-+			if (selected_cpu_cnt > 0) {
-+				ordered_cpus_idx++;
-+				ordered_cpus[ordered_cpus_idx] = selected_cpus[ordered_cpus_idx];
-+				selected_cpus[ordered_cpus_idx] = -1;
-+			}
-+
-+			/* take each CPU and sort it within the same locality based on each inter-CPU localities */
-+			for(test_cpu_idx = 1; test_cpu_idx < selected_cpu_cnt; test_cpu_idx++) {
-+				/* starting point with worst locality and current CPU */
-+				best_locality = LOCALITY_DISTANT;
-+				selected_cpu_idx = test_cpu_idx;
-+
-+				/* try to find the best locality within group */
-+				for(cpu_idx = 1; cpu_idx < selected_cpu_cnt; cpu_idx++) {
-+					/* if CPU has not been used and locality is better */
-+					if (selected_cpus[cpu_idx] > -1) {
-+						other_rq = cpu_rq(ordered_cpus[ordered_cpus_idx]);
-+						if (best_locality > other_rq->cpu_locality[selected_cpus[cpu_idx]]) {
-+							/* assign best locality and best CPU idx in array */
-+							best_locality = other_rq->cpu_locality[selected_cpus[cpu_idx]];
-+							selected_cpu_idx = cpu_idx;
-+						}
-+					}
-+				}
-+
-+				/* add our next best CPU to ordered list */
-+				ordered_cpus_idx++;
-+				ordered_cpus[ordered_cpus_idx] = selected_cpus[selected_cpu_idx];
-+				/* mark this CPU as used */
-+				selected_cpus[selected_cpu_idx] =  -1;
-+			}
-+
-+			/* set up RQ and CPU orders */
-+			for (test_cpu = 0; test_cpu <= ordered_cpus_idx; test_cpu++) {
-+				other_rq = cpu_rq(ordered_cpus[test_cpu]);
-+				/* set up cpu orders */
-+				rq->cpu_order[total_cpus++] = other_rq;
-+				if (
-+#ifdef CONFIG_SCHED_MC
-+				    (other_rq->mc_leader == other_rq) &&
-+#endif
-+#ifdef CONFIG_SCHED_SMT
-+				    (other_rq->smt_leader == other_rq) &&
-+#endif
-+				    (other_rq->smp_leader == other_rq)) {
-+					/* set up RQ orders */
-+					rq->rq_order[total_rqs++] = other_rq;
-+				}
-+			}
-+		}
-+	}
-+
-+	for_each_online_cpu(cpu) {
-+		rq = cpu_rq(cpu);
-+		for (i = 0; i < total_runqueues; i++) {
-+			printk(KERN_DEBUG "MuQSS CPU %d llc %d RQ order %d RQ %d llc %d\n", cpu, per_cpu(cpu_llc_id, cpu), i,
-+			       rq->rq_order[i]->cpu, per_cpu(cpu_llc_id, rq->rq_order[i]->cpu));
-+		}
-+	}
-+
-+	for_each_online_cpu(cpu) {
-+		rq = cpu_rq(cpu);
-+		for (i = 0; i < num_online_cpus(); i++) {
-+			printk(KERN_DEBUG "MuQSS CPU %d llc %d CPU order %d RQ %d llc %d\n", cpu, per_cpu(cpu_llc_id, cpu), i,
-+			       rq->cpu_order[i]->cpu, per_cpu(cpu_llc_id, rq->cpu_order[i]->cpu));
-+		}
-+	}
-+
-+	switch (rqshare) {
-+		case RQSHARE_ALL:
-+			/* This should only ever read 1 */
-+			printk(KERN_INFO "MuQSS runqueue share type ALL total runqueues: %d\n",
-+			       total_runqueues);
-+			break;
-+		case RQSHARE_SMP:
-+			printk(KERN_INFO "MuQSS runqueue share type SMP total runqueues: %d\n",
-+			       total_runqueues);
-+			break;
-+		case RQSHARE_MC:
-+			printk(KERN_INFO "MuQSS runqueue share type MC total runqueues: %d\n",
-+			       total_runqueues);
-+			break;
-+		case RQSHARE_MC_LLC:
-+			printk(KERN_INFO "MuQSS runqueue share type LLC total runqueues: %d\n",
-+			       total_runqueues);
-+			break;
-+		case RQSHARE_SMT:
-+			printk(KERN_INFO "MuQSS runqueue share type SMT total runqueues: %d\n",
-+			       total_runqueues);
-+			break;
-+		case RQSHARE_NONE:
-+			printk(KERN_INFO "MuQSS runqueue share type NONE total runqueues: %d\n",
-+			       total_runqueues);
-+			break;
-+	}
-+
-+	sched_smp_initialized = true;
-+}
-+#else
-+void __init sched_init_smp(void)
-+{
-+	sched_smp_initialized = true;
-+}
-+#endif /* CONFIG_SMP */
-+
-+int in_sched_functions(unsigned long addr)
-+{
-+	return in_lock_functions(addr) ||
-+		(addr >= (unsigned long)__sched_text_start
-+		&& addr < (unsigned long)__sched_text_end);
-+}
-+
-+#ifdef CONFIG_CGROUP_SCHED
-+/* task group related information */
-+struct task_group {
-+	struct cgroup_subsys_state css;
-+
-+	struct rcu_head rcu;
-+	struct list_head list;
-+
-+	struct task_group *parent;
-+	struct list_head siblings;
-+	struct list_head children;
-+};
-+
-+/*
-+ * Default task group.
-+ * Every task in system belongs to this group at bootup.
-+ */
-+struct task_group root_task_group;
-+LIST_HEAD(task_groups);
-+
-+/* Cacheline aligned slab cache for task_group */
-+static struct kmem_cache *task_group_cache __read_mostly;
-+#endif /* CONFIG_CGROUP_SCHED */
-+
-+void __init sched_init(void)
-+{
-+#ifdef CONFIG_SMP
-+	int cpu_ids;
-+#endif
-+	int i;
-+	struct rq *rq;
-+
-+	wait_bit_init();
-+
-+	prio_ratios[0] = 128;
-+	for (i = 1 ; i < NICE_WIDTH ; i++)
-+		prio_ratios[i] = prio_ratios[i - 1] * 11 / 10;
-+
-+	skiplist_node_init(&init_task.node);
-+
-+#ifdef CONFIG_SMP
-+	init_defrootdomain();
-+	cpumask_clear(&cpu_idle_map);
-+#else
-+	uprq = &per_cpu(runqueues, 0);
-+#endif
-+
-+#ifdef CONFIG_CGROUP_SCHED
-+	task_group_cache = KMEM_CACHE(task_group, 0);
-+
-+	list_add(&root_task_group.list, &task_groups);
-+	INIT_LIST_HEAD(&root_task_group.children);
-+	INIT_LIST_HEAD(&root_task_group.siblings);
-+#endif /* CONFIG_CGROUP_SCHED */
-+	for_each_possible_cpu(i) {
-+		rq = cpu_rq(i);
-+		rq->node = kmalloc(sizeof(skiplist_node), GFP_ATOMIC);
-+		skiplist_init(rq->node);
-+		rq->sl = new_skiplist(rq->node);
-+		rq->lock = kmalloc(sizeof(raw_spinlock_t), GFP_ATOMIC);
-+		raw_spin_lock_init(rq->lock);
-+		rq->nr_running = 0;
-+		rq->nr_uninterruptible = 0;
-+		rq->nr_switches = 0;
-+		rq->clock = rq->old_clock = rq->last_niffy = rq->niffies = 0;
-+		rq->last_jiffy = jiffies;
-+		rq->user_ns = rq->nice_ns = rq->softirq_ns = rq->system_ns =
-+			      rq->iowait_ns = rq->idle_ns = 0;
-+		rq->dither = 0;
-+		set_rq_task(rq, &init_task);
-+		rq->iso_ticks = 0;
-+		rq->iso_refractory = false;
-+#ifdef CONFIG_SMP
-+		rq->smp_leader = rq;
-+#ifdef CONFIG_SCHED_MC
-+		rq->mc_leader = rq;
-+#endif
-+#ifdef CONFIG_SCHED_SMT
-+		rq->smt_leader = rq;
-+#endif
-+		rq->sd = NULL;
-+		rq->rd = NULL;
-+		rq->online = false;
-+		rq->cpu = i;
-+		rq_attach_root(rq, &def_root_domain);
-+#endif
-+		init_rq_hrexpiry(rq);
-+		atomic_set(&rq->nr_iowait, 0);
-+	}
-+
-+#ifdef CONFIG_SMP
-+	cpu_ids = i;
-+	/*
-+	 * Set the base locality for cpu cache distance calculation to
-+	 * "distant" (3). Make sure the distance from a CPU to itself is 0.
-+	 */
-+	for_each_possible_cpu(i) {
-+		int j;
-+
-+		rq = cpu_rq(i);
-+#ifdef CONFIG_SCHED_SMT
-+		rq->siblings_idle = sole_cpu_idle;
-+#endif
-+#ifdef CONFIG_SCHED_MC
-+		rq->cache_idle = sole_cpu_idle;
-+#endif
-+		rq->cpu_locality = kmalloc(cpu_ids * sizeof(int *), GFP_ATOMIC);
-+		for_each_possible_cpu(j) {
-+			if (i == j)
-+				rq->cpu_locality[j] = LOCALITY_SAME;
-+			else
-+				rq->cpu_locality[j] = LOCALITY_DISTANT;
-+		}
-+		rq->rq_order = kmalloc(cpu_ids * sizeof(struct rq *), GFP_ATOMIC);
-+		rq->cpu_order = kmalloc(cpu_ids * sizeof(struct rq *), GFP_ATOMIC);
-+		rq->rq_order[0] = rq->cpu_order[0] = rq;
-+		for (j = 1; j < cpu_ids; j++)
-+			rq->rq_order[j] = rq->cpu_order[j] = cpu_rq(j);
-+	}
-+#endif
-+
-+	/*
-+	 * The boot idle thread does lazy MMU switching as well:
-+	 */
-+	mmgrab(&init_mm);
-+	enter_lazy_tlb(&init_mm, current);
-+
-+	/*
-+	 * Make us the idle thread. Technically, schedule() should not be
-+	 * called from this thread, however somewhere below it might be,
-+	 * but because we are the idle thread, we just pick up running again
-+	 * when this runqueue becomes "idle".
-+	 */
-+	init_idle(current, smp_processor_id());
-+
-+#ifdef CONFIG_SMP
-+	idle_thread_set_boot_cpu();
-+#endif /* SMP */
-+
-+	init_schedstats();
-+
-+	psi_init();
-+}
-+
-+#ifdef CONFIG_DEBUG_ATOMIC_SLEEP
-+static inline int preempt_count_equals(int preempt_offset)
-+{
-+	int nested = preempt_count() + rcu_preempt_depth();
-+
-+	return (nested == preempt_offset);
-+}
-+
-+void __might_sleep(const char *file, int line, int preempt_offset)
-+{
-+	/*
-+	 * Blocking primitives will set (and therefore destroy) current->state,
-+	 * since we will exit with TASK_RUNNING make sure we enter with it,
-+	 * otherwise we will destroy state.
-+	 */
-+	WARN_ONCE(current->state != TASK_RUNNING && current->task_state_change,
-+			"do not call blocking ops when !TASK_RUNNING; "
-+			"state=%lx set at [<%p>] %pS\n",
-+			current->state,
-+			(void *)current->task_state_change,
-+			(void *)current->task_state_change);
-+
-+	___might_sleep(file, line, preempt_offset);
-+}
-+EXPORT_SYMBOL(__might_sleep);
-+
-+void __cant_sleep(const char *file, int line, int preempt_offset)
-+{
-+	static unsigned long prev_jiffy;
-+
-+	if (irqs_disabled())
-+		return;
-+
-+	if (!IS_ENABLED(CONFIG_PREEMPT_COUNT))
-+		return;
-+
-+	if (preempt_count() > preempt_offset)
-+		return;
-+
-+	if (time_before(jiffies, prev_jiffy + HZ) && prev_jiffy)
-+		return;
-+	prev_jiffy = jiffies;
-+
-+	printk(KERN_ERR "BUG: assuming atomic context at %s:%d\n", file, line);
-+	printk(KERN_ERR "in_atomic(): %d, irqs_disabled(): %d, pid: %d, name: %s\n",
-+			in_atomic(), irqs_disabled(),
-+			current->pid, current->comm);
-+
-+	debug_show_held_locks(current);
-+	dump_stack();
-+	add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
-+}
-+EXPORT_SYMBOL_GPL(__cant_sleep);
-+
-+void ___might_sleep(const char *file, int line, int preempt_offset)
-+{
-+	/* Ratelimiting timestamp: */
-+	static unsigned long prev_jiffy;
-+
-+	unsigned long preempt_disable_ip;
-+
-+	/* WARN_ON_ONCE() by default, no rate limit required: */
-+	rcu_sleep_check();
-+
-+	if ((preempt_count_equals(preempt_offset) && !irqs_disabled() &&
-+	     !is_idle_task(current) && !current->non_block_count) ||
-+	    system_state == SYSTEM_BOOTING || system_state > SYSTEM_RUNNING ||
-+	    oops_in_progress)
-+		return;
-+
-+	if (time_before(jiffies, prev_jiffy + HZ) && prev_jiffy)
-+		return;
-+	prev_jiffy = jiffies;
-+
-+	/* Save this before calling printk(), since that will clobber it: */
-+	preempt_disable_ip = get_preempt_disable_ip(current);
-+
-+	printk(KERN_ERR
-+		"BUG: sleeping function called from invalid context at %s:%d\n",
-+			file, line);
-+	printk(KERN_ERR
-+		"in_atomic(): %d, irqs_disabled(): %d, non_block: %d, pid: %d, name: %s\n",
-+			in_atomic(), irqs_disabled(), current->non_block_count,
-+			current->pid, current->comm);
-+
-+	if (task_stack_end_corrupted(current))
-+		printk(KERN_EMERG "Thread overran stack, or stack corrupted\n");
-+
-+	debug_show_held_locks(current);
-+	if (irqs_disabled())
-+		print_irqtrace_events(current);
-+	if (IS_ENABLED(CONFIG_DEBUG_PREEMPT)
-+	    && !preempt_count_equals(preempt_offset)) {
-+		pr_err("Preemption disabled at:");
-+		print_ip_sym(preempt_disable_ip);
-+		pr_cont("\n");
-+	}
-+	dump_stack();
-+	add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
-+}
-+EXPORT_SYMBOL(___might_sleep);
-+#endif
-+
-+#ifdef CONFIG_MAGIC_SYSRQ
-+static inline void normalise_rt_tasks(void)
-+{
-+	struct sched_attr attr = {};
-+	struct task_struct *g, *p;
-+	struct rq_flags rf;
-+	struct rq *rq;
-+
-+	read_lock(&tasklist_lock);
-+	for_each_process_thread(g, p) {
-+		/*
-+		 * Only normalize user tasks:
-+		 */
-+		if (p->flags & PF_KTHREAD)
-+			continue;
-+
-+		if (!rt_task(p) && !iso_task(p))
-+			continue;
-+
-+		rq = task_rq_lock(p, &rf);
-+		__setscheduler(p, rq, SCHED_NORMAL, 0, &attr, false);
-+		task_rq_unlock(rq, p, &rf);
-+	}
-+	read_unlock(&tasklist_lock);
-+}
-+
-+void normalize_rt_tasks(void)
-+{
-+	normalise_rt_tasks();
-+}
-+#endif /* CONFIG_MAGIC_SYSRQ */
-+
-+#if defined(CONFIG_IA64) || defined(CONFIG_KGDB_KDB)
-+/*
-+ * These functions are only useful for the IA64 MCA handling, or kdb.
-+ *
-+ * They can only be called when the whole system has been
-+ * stopped - every CPU needs to be quiescent, and no scheduling
-+ * activity can take place. Using them for anything else would
-+ * be a serious bug, and as a result, they aren't even visible
-+ * under any other configuration.
-+ */
-+
-+/**
-+ * curr_task - return the current task for a given CPU.
-+ * @cpu: the processor in question.
-+ *
-+ * ONLY VALID WHEN THE WHOLE SYSTEM IS STOPPED!
-+ *
-+ * Return: The current task for @cpu.
-+ */
-+struct task_struct *curr_task(int cpu)
-+{
-+	return cpu_curr(cpu);
-+}
-+
-+#endif /* defined(CONFIG_IA64) || defined(CONFIG_KGDB_KDB) */
-+
-+#ifdef CONFIG_IA64
-+/**
-+ * ia64_set_curr_task - set the current task for a given CPU.
-+ * @cpu: the processor in question.
-+ * @p: the task pointer to set.
-+ *
-+ * Description: This function must only be used when non-maskable interrupts
-+ * are serviced on a separate stack.  It allows the architecture to switch the
-+ * notion of the current task on a CPU in a non-blocking manner.  This function
-+ * must be called with all CPU's synchronised, and interrupts disabled, the
-+ * and caller must save the original value of the current task (see
-+ * curr_task() above) and restore that value before reenabling interrupts and
-+ * re-starting the system.
-+ *
-+ * ONLY VALID WHEN THE WHOLE SYSTEM IS STOPPED!
-+ */
-+void ia64_set_curr_task(int cpu, struct task_struct *p)
-+{
-+	cpu_curr(cpu) = p;
-+}
-+
-+#endif
-+
-+void init_idle_bootup_task(struct task_struct *idle)
-+{}
-+
-+#ifdef CONFIG_SCHED_DEBUG
-+__read_mostly bool sched_debug_enabled;
-+
-+void proc_sched_show_task(struct task_struct *p, struct pid_namespace *ns,
-+			  struct seq_file *m)
-+{
-+	seq_printf(m, "%s (%d, #threads: %d)\n", p->comm, task_pid_nr_ns(p, ns),
-+		   get_nr_threads(p));
-+}
-+
-+void proc_sched_set_task(struct task_struct *p)
-+{}
-+#endif
-+
-+#ifdef CONFIG_CGROUP_SCHED
-+static void sched_free_group(struct task_group *tg)
-+{
-+	kmem_cache_free(task_group_cache, tg);
-+}
-+
-+/* allocate runqueue etc for a new task group */
-+struct task_group *sched_create_group(struct task_group *parent)
-+{
-+	struct task_group *tg;
-+
-+	tg = kmem_cache_alloc(task_group_cache, GFP_KERNEL | __GFP_ZERO);
-+	if (!tg)
-+		return ERR_PTR(-ENOMEM);
-+
-+	return tg;
-+}
-+
-+void sched_online_group(struct task_group *tg, struct task_group *parent)
-+{
-+}
-+
-+/* rcu callback to free various structures associated with a task group */
-+static void sched_free_group_rcu(struct rcu_head *rhp)
-+{
-+	/* Now it should be safe to free those cfs_rqs */
-+	sched_free_group(container_of(rhp, struct task_group, rcu));
-+}
-+
-+void sched_destroy_group(struct task_group *tg)
-+{
-+	/* Wait for possible concurrent references to cfs_rqs complete */
-+	call_rcu(&tg->rcu, sched_free_group_rcu);
-+}
-+
-+void sched_offline_group(struct task_group *tg)
-+{
-+}
-+
-+static inline struct task_group *css_tg(struct cgroup_subsys_state *css)
-+{
-+	return css ? container_of(css, struct task_group, css) : NULL;
-+}
-+
-+static struct cgroup_subsys_state *
-+cpu_cgroup_css_alloc(struct cgroup_subsys_state *parent_css)
-+{
-+	struct task_group *parent = css_tg(parent_css);
-+	struct task_group *tg;
-+
-+	if (!parent) {
-+		/* This is early initialization for the top cgroup */
-+		return &root_task_group.css;
-+	}
-+
-+	tg = sched_create_group(parent);
-+	if (IS_ERR(tg))
-+		return ERR_PTR(-ENOMEM);
-+	return &tg->css;
-+}
-+
-+/* Expose task group only after completing cgroup initialization */
-+static int cpu_cgroup_css_online(struct cgroup_subsys_state *css)
-+{
-+	struct task_group *tg = css_tg(css);
-+	struct task_group *parent = css_tg(css->parent);
-+
-+	if (parent)
-+		sched_online_group(tg, parent);
-+	return 0;
-+}
-+
-+static void cpu_cgroup_css_released(struct cgroup_subsys_state *css)
-+{
-+	struct task_group *tg = css_tg(css);
-+
-+	sched_offline_group(tg);
-+}
-+
-+static void cpu_cgroup_css_free(struct cgroup_subsys_state *css)
-+{
-+	struct task_group *tg = css_tg(css);
-+
-+	/*
-+	 * Relies on the RCU grace period between css_released() and this.
-+	 */
-+	sched_free_group(tg);
-+}
-+
-+static void cpu_cgroup_fork(struct task_struct *task)
-+{
-+}
-+
-+static int cpu_cgroup_can_attach(struct cgroup_taskset *tset)
-+{
-+	return 0;
-+}
-+
-+static void cpu_cgroup_attach(struct cgroup_taskset *tset)
-+{
-+}
-+
-+static struct cftype cpu_legacy_files[] = {
-+	{ }	/* Terminate */
-+};
-+
-+static struct cftype cpu_files[] = {
-+	{ }	/* terminate */
-+};
-+
-+static int cpu_extra_stat_show(struct seq_file *sf,
-+			       struct cgroup_subsys_state *css)
-+{
-+	return 0;
-+}
-+
-+struct cgroup_subsys cpu_cgrp_subsys = {
-+	.css_alloc	= cpu_cgroup_css_alloc,
-+	.css_online	= cpu_cgroup_css_online,
-+	.css_released	= cpu_cgroup_css_released,
-+	.css_free	= cpu_cgroup_css_free,
-+	.css_extra_stat_show = cpu_extra_stat_show,
-+	.fork		= cpu_cgroup_fork,
-+	.can_attach	= cpu_cgroup_can_attach,
-+	.attach		= cpu_cgroup_attach,
-+	.legacy_cftypes	= cpu_files,
-+	.legacy_cftypes	= cpu_legacy_files,
-+	.dfl_cftypes	= cpu_files,
-+	.early_init	= true,
-+	.threaded	= true,
-+};
-+#endif	/* CONFIG_CGROUP_SCHED */
-+
-+#undef CREATE_TRACE_POINTS
-diff --git a/kernel/sched/MuQSS.h b/kernel/sched/MuQSS.h
-new file mode 100644
-index 000000000000..5214b158d82f
---- /dev/null
-+++ b/kernel/sched/MuQSS.h
-@@ -0,0 +1,1005 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+#ifndef MUQSS_SCHED_H
-+#define MUQSS_SCHED_H
-+
-+#include <linux/sched/clock.h>
-+#include <linux/sched/cpufreq.h>
-+#include <linux/sched/cputime.h>
-+#include <linux/sched/debug.h>
-+#include <linux/sched/hotplug.h>
-+#include <linux/sched/init.h>
-+#include <linux/sched/isolation.h>
-+#include <linux/sched/mm.h>
-+#include <linux/sched/nohz.h>
-+#include <linux/sched/signal.h>
-+#include <linux/sched/smt.h>
-+#include <linux/sched/stat.h>
-+#include <linux/sched/task.h>
-+#include <linux/sched/task_stack.h>
-+#include <linux/sched/topology.h>
-+#include <linux/sched/wake_q.h>
-+
-+#include <uapi/linux/sched/types.h>
-+
-+#include <linux/cgroup.h>
-+#include <linux/cpufreq.h>
-+#include <linux/cpuidle.h>
-+#include <linux/cpuset.h>
-+#include <linux/ctype.h>
-+#include <linux/energy_model.h>
-+#include <linux/freezer.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel_stat.h>
-+#include <linux/kthread.h>
-+#include <linux/membarrier.h>
-+#include <linux/livepatch.h>
-+#include <linux/proc_fs.h>
-+#include <linux/psi.h>
-+#include <linux/sched.h>
-+#include <linux/slab.h>
-+#include <linux/skip_list.h>
-+#include <linux/stop_machine.h>
-+#include <linux/suspend.h>
-+#include <linux/swait.h>
-+#include <linux/syscalls.h>
-+#include <linux/tick.h>
-+#include <linux/tsacct_kern.h>
-+#include <linux/u64_stats_sync.h>
-+
-+#ifdef CONFIG_PARAVIRT
-+#include <asm/paravirt.h>
-+#endif
-+
-+#include "cpupri.h"
-+
-+#ifdef CONFIG_SCHED_DEBUG
-+# define SCHED_WARN_ON(x)	WARN_ONCE(x, #x)
-+#else
-+# define SCHED_WARN_ON(x)	((void)(x))
-+#endif
-+
-+/* task_struct::on_rq states: */
-+#define TASK_ON_RQ_QUEUED	1
-+#define TASK_ON_RQ_MIGRATING	2
-+
-+struct rq;
-+
-+#ifdef CONFIG_SMP
-+
-+static inline bool sched_asym_prefer(int a, int b)
-+{
-+	return arch_asym_cpu_priority(a) > arch_asym_cpu_priority(b);
-+}
-+
-+struct perf_domain {
-+	struct em_perf_domain *em_pd;
-+	struct perf_domain *next;
-+	struct rcu_head rcu;
-+};
-+
-+/* Scheduling group status flags */
-+#define SG_OVERLOAD		0x1 /* More than one runnable task on a CPU. */
-+#define SG_OVERUTILIZED		0x2 /* One or more CPUs are over-utilized. */
-+
-+/*
-+ * We add the notion of a root-domain which will be used to define per-domain
-+ * variables. Each exclusive cpuset essentially defines an island domain by
-+ * fully partitioning the member cpus from any other cpuset. Whenever a new
-+ * exclusive cpuset is created, we also create and attach a new root-domain
-+ * object.
-+ *
-+ */
-+struct root_domain {
-+	atomic_t refcount;
-+	atomic_t rto_count;
-+	struct rcu_head rcu;
-+	cpumask_var_t span;
-+	cpumask_var_t online;
-+
-+	/*
-+	 * Indicate pullable load on at least one CPU, e.g:
-+	 * - More than one runnable task
-+	 * - Running task is misfit
-+	 */
-+	int			overload;
-+
-+	/* Indicate one or more cpus over-utilized (tipping point) */
-+	int			overutilized;
-+
-+	/*
-+	 * The bit corresponding to a CPU gets set here if such CPU has more
-+	 * than one runnable -deadline task (as it is below for RT tasks).
-+	 */
-+	cpumask_var_t dlo_mask;
-+	atomic_t dlo_count;
-+	/* Replace unused CFS structures with void */
-+	//struct dl_bw dl_bw;
-+	//struct cpudl cpudl;
-+	void *dl_bw;
-+	void *cpudl;
-+
-+	/*
-+	 * The "RT overload" flag: it gets set if a CPU has more than
-+	 * one runnable RT task.
-+	 */
-+	cpumask_var_t rto_mask;
-+	//struct cpupri cpupri;
-+	void *cpupri;
-+
-+	unsigned long max_cpu_capacity;
-+
-+	/*
-+	 * NULL-terminated list of performance domains intersecting with the
-+	 * CPUs of the rd. Protected by RCU.
-+	 */
-+	struct perf_domain	*pd;
-+};
-+
-+extern void init_defrootdomain(void);
-+extern int sched_init_domains(const struct cpumask *cpu_map);
-+extern void rq_attach_root(struct rq *rq, struct root_domain *rd);
-+
-+static inline void cpupri_cleanup(void __maybe_unused *cpupri)
-+{
-+}
-+
-+static inline void cpudl_cleanup(void __maybe_unused *cpudl)
-+{
-+}
-+
-+static inline void init_dl_bw(void __maybe_unused *dl_bw)
-+{
-+}
-+
-+static inline int cpudl_init(void __maybe_unused *dl_bw)
-+{
-+	return 0;
-+}
-+
-+static inline int cpupri_init(void __maybe_unused *cpupri)
-+{
-+	return 0;
-+}
-+#endif /* CONFIG_SMP */
-+
-+/*
-+ * This is the main, per-CPU runqueue data structure.
-+ * This data should only be modified by the local cpu.
-+ */
-+struct rq {
-+	raw_spinlock_t *lock;
-+	raw_spinlock_t *orig_lock;
-+
-+	struct task_struct *curr, *idle, *stop;
-+	struct mm_struct *prev_mm;
-+
-+	unsigned int nr_running;
-+	/*
-+	 * This is part of a global counter where only the total sum
-+	 * over all CPUs matters. A task can increase this counter on
-+	 * one CPU and if it got migrated afterwards it may decrease
-+	 * it on another CPU. Always updated under the runqueue lock:
-+	 */
-+	unsigned long nr_uninterruptible;
-+	u64 nr_switches;
-+
-+	/* Stored data about rq->curr to work outside rq lock */
-+	u64 rq_deadline;
-+	int rq_prio;
-+
-+	/* Best queued id for use outside lock */
-+	u64 best_key;
-+
-+	unsigned long last_scheduler_tick; /* Last jiffy this RQ ticked */
-+	unsigned long last_jiffy; /* Last jiffy this RQ updated rq clock */
-+	u64 niffies; /* Last time this RQ updated rq clock */
-+	u64 last_niffy; /* Last niffies as updated by local clock */
-+	u64 last_jiffy_niffies; /* Niffies @ last_jiffy */
-+
-+	u64 load_update; /* When we last updated load */
-+	unsigned long load_avg; /* Rolling load average */
-+#ifdef CONFIG_HAVE_SCHED_AVG_IRQ
-+	u64 irq_load_update; /* When we last updated IRQ load */
-+	unsigned long irq_load_avg; /* Rolling IRQ load average */
-+#endif
-+#ifdef CONFIG_SMT_NICE
-+	struct mm_struct *rq_mm;
-+	int rq_smt_bias; /* Policy/nice level bias across smt siblings */
-+#endif
-+	/* Accurate timekeeping data */
-+	unsigned long user_ns, nice_ns, irq_ns, softirq_ns, system_ns,
-+		iowait_ns, idle_ns;
-+	atomic_t nr_iowait;
-+
-+#ifdef CONFIG_MEMBARRIER
-+	int membarrier_state;
-+#endif
-+
-+	skiplist_node *node;
-+	skiplist *sl;
-+#ifdef CONFIG_SMP
-+	struct task_struct *preempt; /* Preempt triggered on this task */
-+	struct task_struct *preempting; /* Hint only, what task is preempting */
-+
-+	int cpu;		/* cpu of this runqueue */
-+	bool online;
-+
-+	struct root_domain *rd;
-+	struct sched_domain *sd;
-+
-+	unsigned long cpu_capacity_orig;
-+
-+	int *cpu_locality; /* CPU relative cache distance */
-+	struct rq **rq_order; /* Shared RQs ordered by relative cache distance */
-+	struct rq **cpu_order; /* RQs of discrete CPUs ordered by distance */
-+
-+	struct rq *smp_leader; /* First physical CPU per node */
-+#ifdef CONFIG_SCHED_SMT
-+	struct rq *smt_leader; /* First logical CPU in SMT siblings */
-+	cpumask_t thread_mask;
-+	bool (*siblings_idle)(struct rq *rq);
-+	/* See if all smt siblings are idle */
-+#endif /* CONFIG_SCHED_SMT */
-+#ifdef CONFIG_SCHED_MC
-+	struct rq *mc_leader; /* First logical CPU in MC siblings */
-+	cpumask_t core_mask;
-+	bool (*cache_idle)(struct rq *rq);
-+	/* See if all cache siblings are idle */
-+#endif /* CONFIG_SCHED_MC */
-+#endif /* CONFIG_SMP */
-+#ifdef CONFIG_IRQ_TIME_ACCOUNTING
-+	u64 prev_irq_time;
-+#endif /* CONFIG_IRQ_TIME_ACCOUNTING */
-+#ifdef CONFIG_PARAVIRT
-+	u64 prev_steal_time;
-+#endif /* CONFIG_PARAVIRT */
-+#ifdef CONFIG_PARAVIRT_TIME_ACCOUNTING
-+	u64 prev_steal_time_rq;
-+#endif /* CONFIG_PARAVIRT_TIME_ACCOUNTING */
-+
-+	u64 clock, old_clock, last_tick;
-+	/* Ensure that all clocks are in the same cache line */
-+	u64 clock_task ____cacheline_aligned;
-+	int dither;
-+
-+	int iso_ticks;
-+	bool iso_refractory;
-+
-+#ifdef CONFIG_HIGH_RES_TIMERS
-+	struct hrtimer hrexpiry_timer;
-+#endif
-+
-+	int rt_nr_running; /* Number real time tasks running */
-+#ifdef CONFIG_SCHEDSTATS
-+
-+	/* latency stats */
-+	struct sched_info rq_sched_info;
-+	unsigned long long rq_cpu_time;
-+	/* could above be rq->cfs_rq.exec_clock + rq->rt_rq.rt_runtime ? */
-+
-+	/* sys_sched_yield() stats */
-+	unsigned int yld_count;
-+
-+	/* schedule() stats */
-+	unsigned int sched_switch;
-+	unsigned int sched_count;
-+	unsigned int sched_goidle;
-+
-+	/* try_to_wake_up() stats */
-+	unsigned int ttwu_count;
-+	unsigned int ttwu_local;
-+#endif /* CONFIG_SCHEDSTATS */
-+
-+#ifdef CONFIG_SMP
-+	struct llist_head wake_list;
-+#endif
-+
-+#ifdef CONFIG_CPU_IDLE
-+	/* Must be inspected within a rcu lock section */
-+	struct cpuidle_state *idle_state;
-+#endif
-+};
-+
-+struct rq_flags {
-+	unsigned long flags;
-+};
-+
-+#ifdef CONFIG_SMP
-+struct rq *cpu_rq(int cpu);
-+#endif
-+
-+#ifndef CONFIG_SMP
-+extern struct rq *uprq;
-+#define cpu_rq(cpu)	(uprq)
-+#define this_rq()	(uprq)
-+#define raw_rq()	(uprq)
-+#define task_rq(p)	(uprq)
-+#define cpu_curr(cpu)	((uprq)->curr)
-+#else /* CONFIG_SMP */
-+DECLARE_PER_CPU_SHARED_ALIGNED(struct rq, runqueues);
-+#define this_rq()		this_cpu_ptr(&runqueues)
-+#define raw_rq()		raw_cpu_ptr(&runqueues)
-+#define task_rq(p)		cpu_rq(task_cpu(p))
-+#endif /* CONFIG_SMP */
-+
-+static inline int task_current(struct rq *rq, struct task_struct *p)
-+{
-+	return rq->curr == p;
-+}
-+
-+static inline int task_running(struct rq *rq, struct task_struct *p)
-+{
-+#ifdef CONFIG_SMP
-+	return p->on_cpu;
-+#else
-+	return task_current(rq, p);
-+#endif
-+}
-+
-+static inline int task_on_rq_queued(struct task_struct *p)
-+{
-+	return p->on_rq == TASK_ON_RQ_QUEUED;
-+}
-+
-+static inline int task_on_rq_migrating(struct task_struct *p)
-+{
-+	return READ_ONCE(p->on_rq) == TASK_ON_RQ_MIGRATING;
-+}
-+
-+static inline void rq_lock(struct rq *rq)
-+	__acquires(rq->lock)
-+{
-+	raw_spin_lock(rq->lock);
-+}
-+
-+static inline void rq_unlock(struct rq *rq)
-+	__releases(rq->lock)
-+{
-+	raw_spin_unlock(rq->lock);
-+}
-+
-+static inline void rq_lock_irq(struct rq *rq)
-+	__acquires(rq->lock)
-+{
-+	raw_spin_lock_irq(rq->lock);
-+}
-+
-+static inline void rq_unlock_irq(struct rq *rq, struct rq_flags __always_unused *rf)
-+	__releases(rq->lock)
-+{
-+	raw_spin_unlock_irq(rq->lock);
-+}
-+
-+static inline void rq_lock_irqsave(struct rq *rq, struct rq_flags *rf)
-+	__acquires(rq->lock)
-+{
-+	raw_spin_lock_irqsave(rq->lock, rf->flags);
-+}
-+
-+static inline void rq_unlock_irqrestore(struct rq *rq, struct rq_flags *rf)
-+	__releases(rq->lock)
-+{
-+	raw_spin_unlock_irqrestore(rq->lock, rf->flags);
-+}
-+
-+static inline struct rq *task_rq_lock(struct task_struct *p, struct rq_flags *rf)
-+	__acquires(p->pi_lock)
-+	__acquires(rq->lock)
-+{
-+	struct rq *rq;
-+
-+	while (42) {
-+		raw_spin_lock_irqsave(&p->pi_lock, rf->flags);
-+		rq = task_rq(p);
-+		raw_spin_lock(rq->lock);
-+		if (likely(rq == task_rq(p)))
-+			break;
-+		raw_spin_unlock(rq->lock);
-+		raw_spin_unlock_irqrestore(&p->pi_lock, rf->flags);
-+	}
-+	return rq;
-+}
-+
-+static inline void task_rq_unlock(struct rq *rq, struct task_struct *p, struct rq_flags *rf)
-+	__releases(rq->lock)
-+	__releases(p->pi_lock)
-+{
-+	rq_unlock(rq);
-+	raw_spin_unlock_irqrestore(&p->pi_lock, rf->flags);
-+}
-+
-+static inline struct rq *__task_rq_lock(struct task_struct *p, struct rq_flags __always_unused *rf)
-+	__acquires(rq->lock)
-+{
-+	struct rq *rq;
-+
-+	lockdep_assert_held(&p->pi_lock);
-+
-+	while (42) {
-+		rq = task_rq(p);
-+		raw_spin_lock(rq->lock);
-+		if (likely(rq == task_rq(p)))
-+			break;
-+		raw_spin_unlock(rq->lock);
-+	}
-+	return rq;
-+}
-+
-+static inline void __task_rq_unlock(struct rq *rq, struct rq_flags __always_unused *rf)
-+{
-+	rq_unlock(rq);
-+}
-+
-+static inline struct rq *
-+this_rq_lock_irq(struct rq_flags *rf)
-+	__acquires(rq->lock)
-+{
-+	struct rq *rq;
-+
-+	local_irq_disable();
-+	rq = this_rq();
-+	rq_lock(rq);
-+	return rq;
-+}
-+
-+/*
-+ * {de,en}queue flags: Most not used on MuQSS.
-+ *
-+ * DEQUEUE_SLEEP  - task is no longer runnable
-+ * ENQUEUE_WAKEUP - task just became runnable
-+ *
-+ * SAVE/RESTORE - an otherwise spurious dequeue/enqueue, done to ensure tasks
-+ *                are in a known state which allows modification. Such pairs
-+ *                should preserve as much state as possible.
-+ *
-+ * MOVE - paired with SAVE/RESTORE, explicitly does not preserve the location
-+ *        in the runqueue.
-+ *
-+ * ENQUEUE_HEAD      - place at front of runqueue (tail if not specified)
-+ * ENQUEUE_REPLENISH - CBS (replenish runtime and postpone deadline)
-+ * ENQUEUE_MIGRATED  - the task was migrated during wakeup
-+ *
-+ */
-+
-+#define DEQUEUE_SLEEP		0x01
-+#define DEQUEUE_SAVE		0x02 /* matches ENQUEUE_RESTORE */
-+
-+#define ENQUEUE_WAKEUP		0x01
-+#define ENQUEUE_RESTORE		0x02
-+
-+#ifdef CONFIG_SMP
-+#define ENQUEUE_MIGRATED	0x40
-+#else
-+#define ENQUEUE_MIGRATED	0x00
-+#endif
-+
-+static inline u64 __rq_clock_broken(struct rq *rq)
-+{
-+	return READ_ONCE(rq->clock);
-+}
-+
-+static inline u64 rq_clock(struct rq *rq)
-+{
-+	lockdep_assert_held(rq->lock);
-+
-+	return rq->clock;
-+}
-+
-+static inline u64 rq_clock_task(struct rq *rq)
-+{
-+	lockdep_assert_held(rq->lock);
-+
-+	return rq->clock_task;
-+}
-+
-+#ifdef CONFIG_NUMA
-+enum numa_topology_type {
-+	NUMA_DIRECT,
-+	NUMA_GLUELESS_MESH,
-+	NUMA_BACKPLANE,
-+};
-+extern enum numa_topology_type sched_numa_topology_type;
-+extern int sched_max_numa_distance;
-+extern bool find_numa_distance(int distance);
-+extern void sched_init_numa(void);
-+extern void sched_domains_numa_masks_set(unsigned int cpu);
-+extern void sched_domains_numa_masks_clear(unsigned int cpu);
-+extern int sched_numa_find_closest(const struct cpumask *cpus, int cpu);
-+#else
-+static inline void sched_init_numa(void) { }
-+static inline void sched_domains_numa_masks_set(unsigned int cpu) { }
-+static inline void sched_domains_numa_masks_clear(unsigned int cpu) { }
-+static inline int sched_numa_find_closest(const struct cpumask *cpus, int cpu)
-+{
-+	return nr_cpu_ids;
-+}
-+#endif
-+
-+extern struct mutex sched_domains_mutex;
-+extern struct static_key_false sched_schedstats;
-+
-+#define rcu_dereference_check_sched_domain(p) \
-+	rcu_dereference_check((p), \
-+			      lockdep_is_held(&sched_domains_mutex))
-+
-+#ifdef CONFIG_SMP
-+
-+/*
-+ * The domain tree (rq->sd) is protected by RCU's quiescent state transition.
-+ * See destroy_sched_domains: call_rcu for details.
-+ *
-+ * The domain tree of any CPU may only be accessed from within
-+ * preempt-disabled sections.
-+ */
-+#define for_each_domain(cpu, __sd) \
-+	for (__sd = rcu_dereference_check_sched_domain(cpu_rq(cpu)->sd); \
-+			__sd; __sd = __sd->parent)
-+
-+#define for_each_lower_domain(sd) for (; sd; sd = sd->child)
-+
-+/**
-+ * highest_flag_domain - Return highest sched_domain containing flag.
-+ * @cpu:	The cpu whose highest level of sched domain is to
-+ *		be returned.
-+ * @flag:	The flag to check for the highest sched_domain
-+ *		for the given cpu.
-+ *
-+ * Returns the highest sched_domain of a cpu which contains the given flag.
-+ */
-+static inline struct sched_domain *highest_flag_domain(int cpu, int flag)
-+{
-+	struct sched_domain *sd, *hsd = NULL;
-+
-+	for_each_domain(cpu, sd) {
-+		if (!(sd->flags & flag))
-+			break;
-+		hsd = sd;
-+	}
-+
-+	return hsd;
-+}
-+
-+static inline struct sched_domain *lowest_flag_domain(int cpu, int flag)
-+{
-+	struct sched_domain *sd;
-+
-+	for_each_domain(cpu, sd) {
-+		if (sd->flags & flag)
-+			break;
-+	}
-+
-+	return sd;
-+}
-+
-+DECLARE_PER_CPU(struct sched_domain *, sd_llc);
-+DECLARE_PER_CPU(int, sd_llc_size);
-+DECLARE_PER_CPU(int, sd_llc_id);
-+DECLARE_PER_CPU(struct sched_domain_shared *, sd_llc_shared);
-+DECLARE_PER_CPU(struct sched_domain *, sd_numa);
-+DECLARE_PER_CPU(struct sched_domain *, sd_asym_packing);
-+DECLARE_PER_CPU(struct sched_domain *, sd_asym_cpucapacity);
-+
-+struct sched_group_capacity {
-+	atomic_t ref;
-+	/*
-+	 * CPU capacity of this group, SCHED_CAPACITY_SCALE being max capacity
-+	 * for a single CPU.
-+	 */
-+	unsigned long		capacity;
-+	unsigned long		min_capacity;		/* Min per-CPU capacity in group */
-+	unsigned long		max_capacity;		/* Max per-CPU capacity in group */
-+	unsigned long		next_update;
-+	int			imbalance;		/* XXX unrelated to capacity but shared group state */
-+
-+#ifdef CONFIG_SCHED_DEBUG
-+	int id;
-+#endif
-+
-+	unsigned long cpumask[0]; /* balance mask */
-+};
-+
-+struct sched_group {
-+	struct sched_group *next;	/* Must be a circular list */
-+	atomic_t ref;
-+
-+	unsigned int group_weight;
-+	struct sched_group_capacity *sgc;
-+	int asym_prefer_cpu;		/* cpu of highest priority in group */
-+
-+	/*
-+	 * The CPUs this group covers.
-+	 *
-+	 * NOTE: this field is variable length. (Allocated dynamically
-+	 * by attaching extra space to the end of the structure,
-+	 * depending on how many CPUs the kernel has booted up with)
-+	 */
-+	unsigned long cpumask[0];
-+};
-+
-+static inline struct cpumask *sched_group_span(struct sched_group *sg)
-+{
-+	return to_cpumask(sg->cpumask);
-+}
-+
-+/*
-+ * See build_balance_mask().
-+ */
-+static inline struct cpumask *group_balance_mask(struct sched_group *sg)
-+{
-+	return to_cpumask(sg->sgc->cpumask);
-+}
-+
-+/**
-+ * group_first_cpu - Returns the first cpu in the cpumask of a sched_group.
-+ * @group: The group whose first cpu is to be returned.
-+ */
-+static inline unsigned int group_first_cpu(struct sched_group *group)
-+{
-+	return cpumask_first(sched_group_span(group));
-+}
-+
-+
-+#if defined(CONFIG_SCHED_DEBUG) && defined(CONFIG_SYSCTL)
-+void register_sched_domain_sysctl(void);
-+void dirty_sched_domain_sysctl(int cpu);
-+void unregister_sched_domain_sysctl(void);
-+#else
-+static inline void register_sched_domain_sysctl(void)
-+{
-+}
-+static inline void dirty_sched_domain_sysctl(int cpu)
-+{
-+}
-+static inline void unregister_sched_domain_sysctl(void)
-+{
-+}
-+#endif
-+
-+extern void sched_ttwu_pending(void);
-+extern void set_cpus_allowed_common(struct task_struct *p, const struct cpumask *new_mask);
-+extern void set_rq_online (struct rq *rq);
-+extern void set_rq_offline(struct rq *rq);
-+extern bool sched_smp_initialized;
-+
-+static inline void update_group_capacity(struct sched_domain *sd, int cpu)
-+{
-+}
-+
-+static inline void trigger_load_balance(struct rq *rq)
-+{
-+}
-+
-+#define sched_feat(x) 0
-+
-+#else /* CONFIG_SMP */
-+
-+static inline void sched_ttwu_pending(void) { }
-+
-+#endif /* CONFIG_SMP */
-+
-+#ifdef CONFIG_CPU_IDLE
-+static inline void idle_set_state(struct rq *rq,
-+				  struct cpuidle_state *idle_state)
-+{
-+	rq->idle_state = idle_state;
-+}
-+
-+static inline struct cpuidle_state *idle_get_state(struct rq *rq)
-+{
-+	SCHED_WARN_ON(!rcu_read_lock_held());
-+	return rq->idle_state;
-+}
-+#else
-+static inline void idle_set_state(struct rq *rq,
-+				  struct cpuidle_state *idle_state)
-+{
-+}
-+
-+static inline struct cpuidle_state *idle_get_state(struct rq *rq)
-+{
-+	return NULL;
-+}
-+#endif
-+
-+#ifdef CONFIG_SCHED_DEBUG
-+extern bool sched_debug_enabled;
-+#endif
-+
-+extern void schedule_idle(void);
-+
-+#ifdef CONFIG_IRQ_TIME_ACCOUNTING
-+struct irqtime {
-+	u64			total;
-+	u64			tick_delta;
-+	u64			irq_start_time;
-+	struct u64_stats_sync	sync;
-+};
-+
-+DECLARE_PER_CPU(struct irqtime, cpu_irqtime);
-+
-+/*
-+ * Returns the irqtime minus the softirq time computed by ksoftirqd.
-+ * Otherwise ksoftirqd's sum_exec_runtime is substracted its own runtime
-+ * and never move forward.
-+ */
-+static inline u64 irq_time_read(int cpu)
-+{
-+	struct irqtime *irqtime = &per_cpu(cpu_irqtime, cpu);
-+	unsigned int seq;
-+	u64 total;
-+
-+	do {
-+		seq = __u64_stats_fetch_begin(&irqtime->sync);
-+		total = irqtime->total;
-+	} while (__u64_stats_fetch_retry(&irqtime->sync, seq));
-+
-+	return total;
-+}
-+#endif /* CONFIG_IRQ_TIME_ACCOUNTING */
-+
-+static inline bool sched_stop_runnable(struct rq *rq)
-+{
-+	return rq->stop && task_on_rq_queued(rq->stop);
-+}
-+
-+#ifdef CONFIG_SMP
-+static inline int cpu_of(struct rq *rq)
-+{
-+	return rq->cpu;
-+}
-+#else /* CONFIG_SMP */
-+static inline int cpu_of(struct rq *rq)
-+{
-+	return 0;
-+}
-+#endif
-+
-+#ifdef CONFIG_CPU_FREQ
-+DECLARE_PER_CPU(struct update_util_data *, cpufreq_update_util_data);
-+
-+static inline void cpufreq_trigger(struct rq *rq, unsigned int flags)
-+{
-+	struct update_util_data *data;
-+
-+	data = rcu_dereference_sched(*per_cpu_ptr(&cpufreq_update_util_data,
-+						  cpu_of(rq)));
-+
-+	if (data)
-+		data->func(data, rq->niffies, flags);
-+}
-+#else
-+static inline void cpufreq_trigger(struct rq *rq, unsigned int flag)
-+{
-+}
-+#endif /* CONFIG_CPU_FREQ */
-+
-+static __always_inline
-+unsigned int uclamp_util_with(struct rq __maybe_unused *rq, unsigned int util,
-+			      struct task_struct __maybe_unused *p)
-+{
-+	return util;
-+}
-+
-+static inline unsigned int uclamp_util(struct rq *rq, unsigned int util)
-+{
-+	return util;
-+}
-+
-+#ifdef arch_scale_freq_capacity
-+#ifndef arch_scale_freq_invariant
-+#define arch_scale_freq_invariant()	(true)
-+#endif
-+#else /* arch_scale_freq_capacity */
-+#define arch_scale_freq_invariant()	(false)
-+#endif
-+
-+/*
-+ * This should only be called when current == rq->idle. Dodgy workaround for
-+ * when softirqs are pending and we are in the idle loop. Setting current to
-+ * resched will kick us out of the idle loop and the softirqs will be serviced
-+ * on our next pass through schedule().
-+ */
-+static inline bool softirq_pending(int cpu)
-+{
-+	if (likely(!local_softirq_pending()))
-+		return false;
-+	set_tsk_need_resched(current);
-+	return true;
-+}
-+
-+#ifdef CONFIG_64BIT
-+static inline u64 read_sum_exec_runtime(struct task_struct *t)
-+{
-+	return tsk_seruntime(t);
-+}
-+#else
-+static inline u64 read_sum_exec_runtime(struct task_struct *t)
-+{
-+	struct rq_flags rf;
-+	u64 ns;
-+	struct rq *rq;
-+
-+	rq = task_rq_lock(t, &rf);
-+	ns = tsk_seruntime(t);
-+	task_rq_unlock(rq, t, &rf);
-+
-+	return ns;
-+}
-+#endif
-+
-+#ifndef arch_scale_freq_capacity
-+static __always_inline
-+unsigned long arch_scale_freq_capacity(int cpu)
-+{
-+	return SCHED_CAPACITY_SCALE;
-+}
-+#endif
-+
-+#ifdef CONFIG_NO_HZ_FULL
-+extern bool sched_can_stop_tick(struct rq *rq);
-+extern int __init sched_tick_offload_init(void);
-+
-+/*
-+ * Tick may be needed by tasks in the runqueue depending on their policy and
-+ * requirements. If tick is needed, lets send the target an IPI to kick it out of
-+ * nohz mode if necessary.
-+ */
-+static inline void sched_update_tick_dependency(struct rq *rq)
-+{
-+	int cpu;
-+
-+	if (!tick_nohz_full_enabled())
-+		return;
-+
-+	cpu = cpu_of(rq);
-+
-+	if (!tick_nohz_full_cpu(cpu))
-+		return;
-+
-+	if (sched_can_stop_tick(rq))
-+		tick_nohz_dep_clear_cpu(cpu, TICK_DEP_BIT_SCHED);
-+	else
-+		tick_nohz_dep_set_cpu(cpu, TICK_DEP_BIT_SCHED);
-+}
-+#else
-+static inline int sched_tick_offload_init(void) { return 0; }
-+static inline void sched_update_tick_dependency(struct rq *rq) { }
-+#endif
-+
-+#define SCHED_FLAG_SUGOV	0x10000000
-+
-+static inline bool rt_rq_is_runnable(struct rq *rt_rq)
-+{
-+	return rt_rq->rt_nr_running;
-+}
-+
-+/**
-+ * enum schedutil_type - CPU utilization type
-+ * @FREQUENCY_UTIL:	Utilization used to select frequency
-+ * @ENERGY_UTIL:	Utilization used during energy calculation
-+ *
-+ * The utilization signals of all scheduling classes (CFS/RT/DL) and IRQ time
-+ * need to be aggregated differently depending on the usage made of them. This
-+ * enum is used within schedutil_freq_util() to differentiate the types of
-+ * utilization expected by the callers, and adjust the aggregation accordingly.
-+ */
-+enum schedutil_type {
-+	FREQUENCY_UTIL,
-+	ENERGY_UTIL,
-+};
-+
-+#ifdef CONFIG_CPU_FREQ_GOV_SCHEDUTIL
-+
-+unsigned long schedutil_cpu_util(int cpu, unsigned long util_cfs,
-+				 unsigned long max, enum schedutil_type type,
-+				 struct task_struct *p);
-+
-+static inline unsigned long cpu_bw_dl(struct rq *rq)
-+{
-+	return 0;
-+}
-+
-+static inline unsigned long cpu_util_dl(struct rq *rq)
-+{
-+	return 0;
-+}
-+
-+static inline unsigned long cpu_util_cfs(struct rq *rq)
-+{
-+	unsigned long ret = READ_ONCE(rq->load_avg);
-+
-+	if (ret > SCHED_CAPACITY_SCALE)
-+		ret = SCHED_CAPACITY_SCALE;
-+	return ret;
-+}
-+
-+static inline unsigned long cpu_util_rt(struct rq *rq)
-+{
-+	unsigned long ret = READ_ONCE(rq->rt_nr_running);
-+
-+	if (ret > SCHED_CAPACITY_SCALE)
-+		ret = SCHED_CAPACITY_SCALE;
-+	return ret;
-+}
-+
-+#ifdef CONFIG_HAVE_SCHED_AVG_IRQ
-+static inline unsigned long cpu_util_irq(struct rq *rq)
-+{
-+	unsigned long ret = READ_ONCE(rq->irq_load_avg);
-+
-+	if (ret > SCHED_CAPACITY_SCALE)
-+		ret = SCHED_CAPACITY_SCALE;
-+	return ret;
-+}
-+
-+static inline
-+unsigned long scale_irq_capacity(unsigned long util, unsigned long irq, unsigned long max)
-+{
-+	util *= (max - irq);
-+	util /= max;
-+
-+	return util;
-+
-+}
-+#else
-+static inline unsigned long cpu_util_irq(struct rq *rq)
-+{
-+	return 0;
-+}
-+
-+static inline
-+unsigned long scale_irq_capacity(unsigned long util, unsigned long irq, unsigned long max)
-+{
-+	return util;
-+}
-+#endif
-+#endif
-+
-+#if defined(CONFIG_ENERGY_MODEL) && defined(CONFIG_CPU_FREQ_GOV_SCHEDUTIL)
-+#define perf_domain_span(pd) (to_cpumask(((pd)->em_pd->cpus)))
-+
-+DECLARE_STATIC_KEY_FALSE(sched_energy_present);
-+
-+static inline bool sched_energy_enabled(void)
-+{
-+	return static_branch_unlikely(&sched_energy_present);
-+}
-+
-+#else /* ! (CONFIG_ENERGY_MODEL && CONFIG_CPU_FREQ_GOV_SCHEDUTIL) */
-+
-+#define perf_domain_span(pd) NULL
-+static inline bool sched_energy_enabled(void) { return false; }
-+
-+#endif /* CONFIG_ENERGY_MODEL && CONFIG_CPU_FREQ_GOV_SCHEDUTIL */
-+
-+#ifdef CONFIG_MEMBARRIER
-+/*
-+ * The scheduler provides memory barriers required by membarrier between:
-+ * - prior user-space memory accesses and store to rq->membarrier_state,
-+ * - store to rq->membarrier_state and following user-space memory accesses.
-+ * In the same way it provides those guarantees around store to rq->curr.
-+ */
-+static inline void membarrier_switch_mm(struct rq *rq,
-+					struct mm_struct *prev_mm,
-+					struct mm_struct *next_mm)
-+{
-+	int membarrier_state;
-+
-+	if (prev_mm == next_mm)
-+		return;
-+
-+	membarrier_state = atomic_read(&next_mm->membarrier_state);
-+	if (READ_ONCE(rq->membarrier_state) == membarrier_state)
-+		return;
-+
-+	WRITE_ONCE(rq->membarrier_state, membarrier_state);
-+}
-+#else
-+static inline void membarrier_switch_mm(struct rq *rq,
-+					struct mm_struct *prev_mm,
-+					struct mm_struct *next_mm)
-+{
-+}
-+#endif
-+
-+#endif /* MUQSS_SCHED_H */
-diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c
-index 86800b4d5453..f3d8dca0538a 100644
---- a/kernel/sched/cpufreq_schedutil.c
-+++ b/kernel/sched/cpufreq_schedutil.c
-@@ -185,6 +185,12 @@ static unsigned int get_next_freq(struct sugov_policy *sg_policy,
- 	return cpufreq_driver_resolve_freq(policy, freq);
- }
- 
-+#ifdef CONFIG_SCHED_MUQSS
-+#define rt_rq_runnable(rq_rt) rt_rq_is_runnable(rq)
-+#else
-+#define rt_rq_runnable(rq_rt) rt_rq_is_runnable(&rq->rt)
-+#endif
-+
- /*
-  * This function computes an effective utilization for the given CPU, to be
-  * used for frequency selection given the linear relation: f = u * f_max.
-@@ -213,7 +219,7 @@ unsigned long schedutil_cpu_util(int cpu, unsigned long util_cfs,
- 	struct rq *rq = cpu_rq(cpu);
- 
- 	if (!IS_BUILTIN(CONFIG_UCLAMP_TASK) &&
--	    type == FREQUENCY_UTIL && rt_rq_is_runnable(&rq->rt)) {
-+	    type == FREQUENCY_UTIL && rt_rq_runnable(rq)) {
- 		return max;
- 	}
- 
-@@ -658,7 +664,11 @@ static int sugov_kthread_create(struct sugov_policy *sg_policy)
- 	struct task_struct *thread;
- 	struct sched_attr attr = {
- 		.size		= sizeof(struct sched_attr),
-+#ifdef CONFIG_SCHED_MUQSS
-+		.sched_policy	= SCHED_RR,
-+#else
- 		.sched_policy	= SCHED_DEADLINE,
-+#endif
- 		.sched_flags	= SCHED_FLAG_SUGOV,
- 		.sched_nice	= 0,
- 		.sched_priority	= 0,
-diff --git a/kernel/sched/cpupri.h b/kernel/sched/cpupri.h
-index 7dc20a3232e7..e733a0a53b0a 100644
---- a/kernel/sched/cpupri.h
-+++ b/kernel/sched/cpupri.h
-@@ -17,9 +17,11 @@ struct cpupri {
- 	int			*cpu_to_pri;
- };
- 
-+#ifndef CONFIG_SCHED_MUQSS
- #ifdef CONFIG_SMP
- int  cpupri_find(struct cpupri *cp, struct task_struct *p, struct cpumask *lowest_mask);
- void cpupri_set(struct cpupri *cp, int cpu, int pri);
- int  cpupri_init(struct cpupri *cp);
- void cpupri_cleanup(struct cpupri *cp);
- #endif
-+#endif
-diff --git a/kernel/sched/cputime.c b/kernel/sched/cputime.c
-index 46ed4e1383e2..f077fcd22d2b 100644
---- a/kernel/sched/cputime.c
-+++ b/kernel/sched/cputime.c
-@@ -266,26 +266,6 @@ static inline u64 account_other_time(u64 max)
- 	return accounted;
- }
- 
--#ifdef CONFIG_64BIT
--static inline u64 read_sum_exec_runtime(struct task_struct *t)
--{
--	return t->se.sum_exec_runtime;
--}
--#else
--static u64 read_sum_exec_runtime(struct task_struct *t)
--{
--	u64 ns;
--	struct rq_flags rf;
--	struct rq *rq;
--
--	rq = task_rq_lock(t, &rf);
--	ns = t->se.sum_exec_runtime;
--	task_rq_unlock(rq, t, &rf);
--
--	return ns;
--}
--#endif
--
- /*
-  * Accumulate raw cputime values of dead tasks (sig->[us]time) and live
-  * tasks (sum on group iteration) belonging to @tsk's group.
-@@ -663,7 +643,7 @@ void cputime_adjust(struct task_cputime *curr, struct prev_cputime *prev,
- void task_cputime_adjusted(struct task_struct *p, u64 *ut, u64 *st)
- {
- 	struct task_cputime cputime = {
--		.sum_exec_runtime = p->se.sum_exec_runtime,
-+		.sum_exec_runtime = tsk_seruntime(p),
- 	};
- 
- 	task_cputime(p, &cputime.utime, &cputime.stime);
-diff --git a/kernel/sched/idle.c b/kernel/sched/idle.c
-index f65ef1e2f204..e0aa6c73a5fa 100644
---- a/kernel/sched/idle.c
-+++ b/kernel/sched/idle.c
-@@ -225,6 +225,8 @@ static void cpuidle_idle_call(void)
- static void do_idle(void)
- {
- 	int cpu = smp_processor_id();
-+	bool pending = false;
-+
- 	/*
- 	 * If the arch has a polling bit, we maintain an invariant:
- 	 *
-@@ -235,7 +237,10 @@ static void do_idle(void)
- 	 */
- 
- 	__current_set_polling();
--	tick_nohz_idle_enter();
-+	if (unlikely(softirq_pending(cpu)))
-+		pending = true;
-+	else
-+		tick_nohz_idle_enter();
- 
- 	while (!need_resched()) {
- 		rmb();
-@@ -273,7 +278,8 @@ static void do_idle(void)
- 	 * an IPI to fold the state for us.
- 	 */
- 	preempt_set_need_resched();
--	tick_nohz_idle_exit();
-+	if (!pending)
-+		tick_nohz_idle_exit();
- 	__current_clr_polling();
- 
- 	/*
-@@ -355,6 +361,7 @@ void cpu_startup_entry(enum cpuhp_state state)
- 		do_idle();
- }
- 
-+#ifndef CONFIG_SCHED_MUQSS
- /*
-  * idle-task scheduling class.
-  */
-@@ -479,3 +486,4 @@ const struct sched_class idle_sched_class = {
- 	.switched_to		= switched_to_idle,
- 	.update_curr		= update_curr_idle,
- };
-+#endif /* CONFIG_SCHED_MUQSS */
-diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h
-index c8870c5bd7df..add1d74c2e91 100644
---- a/kernel/sched/sched.h
-+++ b/kernel/sched/sched.h
-@@ -2,6 +2,19 @@
- /*
-  * Scheduler internal types and methods:
-  */
-+#ifdef CONFIG_SCHED_MUQSS
-+#include "MuQSS.h"
-+
-+/* Begin compatibility wrappers for MuQSS/CFS differences */
-+#define rq_rt_nr_running(rq) ((rq)->rt_nr_running)
-+#define rq_h_nr_running(rq) ((rq)->nr_running)
-+
-+#else /* CONFIG_SCHED_MUQSS */
-+
-+#define rq_rt_nr_running(rq) ((rq)->rt.rt_nr_running)
-+#define rq_h_nr_running(rq) ((rq)->cfs.h_nr_running)
-+
-+
- #include <linux/sched.h>
- 
- #include <linux/sched/autogroup.h>
-@@ -2496,3 +2509,30 @@ static inline void membarrier_switch_mm(struct rq *rq,
- {
- }
- #endif
-+
-+/* MuQSS compatibility functions */
-+static inline bool softirq_pending(int cpu)
-+{
-+	return false;
-+}
-+
-+#ifdef CONFIG_64BIT
-+static inline u64 read_sum_exec_runtime(struct task_struct *t)
-+{
-+	return t->se.sum_exec_runtime;
-+}
-+#else
-+static inline u64 read_sum_exec_runtime(struct task_struct *t)
-+{
-+	u64 ns;
-+	struct rq_flags rf;
-+	struct rq *rq;
-+
-+	rq = task_rq_lock(t, &rf);
-+	ns = t->se.sum_exec_runtime;
-+	task_rq_unlock(rq, t, &rf);
-+
-+	return ns;
-+}
-+#endif
-+#endif /* CONFIG_SCHED_MUQSS */
-diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c
-index 49b835f1305f..0253ea846c0d 100644
---- a/kernel/sched/topology.c
-+++ b/kernel/sched/topology.c
-@@ -3,6 +3,7 @@
-  * Scheduler topology setup/handling methods
-  */
- #include "sched.h"
-+#include "linux/sched/deadline.h"
- 
- DEFINE_MUTEX(sched_domains_mutex);
- 
-@@ -442,7 +443,11 @@ void rq_attach_root(struct rq *rq, struct root_domain *rd)
- 	struct root_domain *old_rd = NULL;
- 	unsigned long flags;
- 
-+#ifdef CONFIG_SCHED_MUQSS
-+	raw_spin_lock_irqsave(rq->lock, flags);
-+#else
- 	raw_spin_lock_irqsave(&rq->lock, flags);
-+#endif
- 
- 	if (rq->rd) {
- 		old_rd = rq->rd;
-@@ -468,7 +473,11 @@ void rq_attach_root(struct rq *rq, struct root_domain *rd)
- 	if (cpumask_test_cpu(rq->cpu, cpu_active_mask))
- 		set_rq_online(rq);
- 
-+#ifdef CONFIG_SCHED_MUQSS
-+	raw_spin_unlock_irqrestore(rq->lock, flags);
-+#else
- 	raw_spin_unlock_irqrestore(&rq->lock, flags);
-+#endif
- 
- 	if (old_rd)
- 		call_rcu(&old_rd->rcu, free_rootdomain);
-diff --git a/kernel/skip_list.c b/kernel/skip_list.c
-new file mode 100644
-index 000000000000..bf5c6e97e139
---- /dev/null
-+++ b/kernel/skip_list.c
-@@ -0,0 +1,148 @@
-+/*
-+  Copyright (C) 2011,2016 Con Kolivas.
-+
-+  Code based on example originally by William Pugh.
-+
-+Skip Lists are a probabilistic alternative to balanced trees, as
-+described in the June 1990 issue of CACM and were invented by
-+William Pugh in 1987.
-+
-+A couple of comments about this implementation:
-+The routine randomLevel has been hard-coded to generate random
-+levels using p=0.25. It can be easily changed.
-+
-+The insertion routine has been implemented so as to use the
-+dirty hack described in the CACM paper: if a random level is
-+generated that is more than the current maximum level, the
-+current maximum level plus one is used instead.
-+
-+Levels start at zero and go up to MaxLevel (which is equal to
-+MaxNumberOfLevels-1).
-+
-+The routines defined in this file are:
-+
-+init: defines slnode
-+
-+new_skiplist: returns a new, empty list
-+
-+randomLevel: Returns a random level based on a u64 random seed passed to it.
-+In MuQSS, the "niffy" time is used for this purpose.
-+
-+insert(l,key, value): inserts the binding (key, value) into l. This operation
-+occurs in O(log n) time.
-+
-+delnode(slnode, l, node): deletes any binding of key from the l based on the
-+actual node value. This operation occurs in O(k) time where k is the
-+number of levels of the node in question (max 8). The original delete
-+function occurred in O(log n) time and involved a search.
-+
-+MuQSS Notes: In this implementation of skiplists, there are bidirectional
-+next/prev pointers and the insert function returns a pointer to the actual
-+node the value is stored. The key here is chosen by the scheduler so as to
-+sort tasks according to the priority list requirements and is no longer used
-+by the scheduler after insertion. The scheduler lookup, however, occurs in
-+O(1) time because it is always the first item in the level 0 linked list.
-+Since the task struct stores a copy of the node pointer upon skiplist_insert,
-+it can also remove it much faster than the original implementation with the
-+aid of prev<->next pointer manipulation and no searching.
-+
-+*/
-+
-+#include <linux/slab.h>
-+#include <linux/skip_list.h>
-+
-+#define MaxNumberOfLevels 8
-+#define MaxLevel (MaxNumberOfLevels - 1)
-+
-+void skiplist_init(skiplist_node *slnode)
-+{
-+	int i;
-+
-+	slnode->key = 0xFFFFFFFFFFFFFFFF;
-+	slnode->level = 0;
-+	slnode->value = NULL;
-+	for (i = 0; i < MaxNumberOfLevels; i++)
-+		slnode->next[i] = slnode->prev[i] = slnode;
-+}
-+
-+skiplist *new_skiplist(skiplist_node *slnode)
-+{
-+	skiplist *l = kzalloc(sizeof(skiplist), GFP_ATOMIC);
-+
-+	BUG_ON(!l);
-+	l->header = slnode;
-+	return l;
-+}
-+
-+void free_skiplist(skiplist *l)
-+{
-+	skiplist_node *p, *q;
-+
-+	p = l->header;
-+	do {
-+		q = p->next[0];
-+		p->next[0]->prev[0] = q->prev[0];
-+		skiplist_node_init(p);
-+		p = q;
-+	} while (p != l->header);
-+	kfree(l);
-+}
-+
-+void skiplist_node_init(skiplist_node *node)
-+{
-+	memset(node, 0, sizeof(skiplist_node));
-+}
-+
-+static inline unsigned int randomLevel(const long unsigned int randseed)
-+{
-+	return find_first_bit(&randseed, MaxLevel) / 2;
-+}
-+
-+void skiplist_insert(skiplist *l, skiplist_node *node, keyType key, valueType value, unsigned int randseed)
-+{
-+	skiplist_node *update[MaxNumberOfLevels];
-+	skiplist_node *p, *q;
-+	int k = l->level;
-+
-+	p = l->header;
-+	do {
-+		while (q = p->next[k], q->key <= key)
-+			p = q;
-+		update[k] = p;
-+	} while (--k >= 0);
-+
-+	++l->entries;
-+	k = randomLevel(randseed);
-+	if (k > l->level) {
-+		k = ++l->level;
-+		update[k] = l->header;
-+	}
-+
-+	node->level = k;
-+	node->key = key;
-+	node->value = value;
-+	do {
-+		p = update[k];
-+		node->next[k] = p->next[k];
-+		p->next[k] = node;
-+		node->prev[k] = p;
-+		node->next[k]->prev[k] = node;
-+	} while (--k >= 0);
-+}
-+
-+void skiplist_delete(skiplist *l, skiplist_node *node)
-+{
-+	int k, m = node->level;
-+
-+	for (k = 0; k <= m; k++) {
-+		node->prev[k]->next[k] = node->next[k];
-+		node->next[k]->prev[k] = node->prev[k];
-+	}
-+	skiplist_node_init(node);
-+	if (m == l->level) {
-+		while (l->header->next[m] == l->header && l->header->prev[m] == l->header && m > 0)
-+			m--;
-+		l->level = m;
-+	}
-+	l->entries--;
-+}
-diff --git a/kernel/sysctl.c b/kernel/sysctl.c
-index b6f2f35d0bcf..72065ca9a8e2 100644
---- a/kernel/sysctl.c
-+++ b/kernel/sysctl.c
-@@ -130,8 +130,16 @@ static int __maybe_unused four = 4;
- static unsigned long zero_ul;
- static unsigned long one_ul = 1;
- static unsigned long long_max = LONG_MAX;
--static int one_hundred = 100;
--static int one_thousand = 1000;
-+static int __read_mostly one_hundred = 100;
-+static int __read_mostly one_thousand = 1000;
-+#ifdef CONFIG_SCHED_MUQSS
-+static int zero = 0;
-+static int one = 1;
-+extern int rr_interval;
-+extern int sched_interactive;
-+extern int sched_iso_cpu;
-+extern int sched_yield_type;
-+#endif
- #ifdef CONFIG_PRINTK
- static int ten_thousand = 10000;
- #endif
-@@ -300,7 +308,7 @@ static struct ctl_table sysctl_base_table[] = {
- 	{ }
- };
- 
--#ifdef CONFIG_SCHED_DEBUG
-+#if defined(CONFIG_SCHED_DEBUG) && !defined(CONFIG_SCHED_MUQSS)
- static int min_sched_granularity_ns = 100000;		/* 100 usecs */
- static int max_sched_granularity_ns = NSEC_PER_SEC;	/* 1 second */
- static int min_wakeup_granularity_ns;			/* 0 usecs */
-@@ -317,6 +325,7 @@ static int max_extfrag_threshold = 1000;
- #endif
- 
- static struct ctl_table kern_table[] = {
-+#ifndef CONFIG_SCHED_MUQSS
- 	{
- 		.procname	= "sched_child_runs_first",
- 		.data		= &sysctl_sched_child_runs_first,
-@@ -498,6 +507,7 @@ static struct ctl_table kern_table[] = {
- 		.extra2		= SYSCTL_ONE,
- 	},
- #endif
-+#endif /* !CONFIG_SCHED_MUQSS */
- #ifdef CONFIG_PROVE_LOCKING
- 	{
- 		.procname	= "prove_locking",
-@@ -1070,6 +1080,44 @@ static struct ctl_table kern_table[] = {
- 		.proc_handler	= proc_dointvec,
- 	},
- #endif
-+#ifdef CONFIG_SCHED_MUQSS
-+	{
-+		.procname	= "rr_interval",
-+		.data		= &rr_interval,
-+		.maxlen		= sizeof (int),
-+		.mode		= 0644,
-+		.proc_handler	= &proc_dointvec_minmax,
-+		.extra1		= &one,
-+		.extra2		= &one_thousand,
-+	},
-+	{
-+		.procname	= "interactive",
-+		.data		= &sched_interactive,
-+		.maxlen		= sizeof(int),
-+		.mode		= 0644,
-+		.proc_handler	= &proc_dointvec_minmax,
-+		.extra1		= &zero,
-+		.extra2		= &one,
-+	},
-+	{
-+		.procname	= "iso_cpu",
-+		.data		= &sched_iso_cpu,
-+		.maxlen		= sizeof (int),
-+		.mode		= 0644,
-+		.proc_handler	= &proc_dointvec_minmax,
-+		.extra1		= &zero,
-+		.extra2		= &one_hundred,
-+	},
-+	{
-+		.procname	= "yield_type",
-+		.data		= &sched_yield_type,
-+		.maxlen		= sizeof (int),
-+		.mode		= 0644,
-+		.proc_handler	= &proc_dointvec_minmax,
-+		.extra1		= &zero,
-+		.extra2		= &two,
-+	},
-+#endif
- #if defined(CONFIG_S390) && defined(CONFIG_SMP)
- 	{
- 		.procname	= "spin_retry",
-diff --git a/kernel/time/clockevents.c b/kernel/time/clockevents.c
-index f5490222e134..7a61971cca74 100644
---- a/kernel/time/clockevents.c
-+++ b/kernel/time/clockevents.c
-@@ -190,8 +190,13 @@ int clockevents_tick_resume(struct clock_event_device *dev)
- 
- #ifdef CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST
- 
-+#ifdef CONFIG_SCHED_MUQSS
-+/* Limit min_delta to 100us */
-+#define MIN_DELTA_LIMIT		(NSEC_PER_SEC / 10000)
-+#else
- /* Limit min_delta to a jiffie */
- #define MIN_DELTA_LIMIT		(NSEC_PER_SEC / HZ)
-+#endif
- 
- /**
-  * clockevents_increase_min_delta - raise minimum delta of a clock event device
-diff --git a/kernel/time/posix-cpu-timers.c b/kernel/time/posix-cpu-timers.c
-index 42d512fcfda2..0db83bdf7f39 100644
---- a/kernel/time/posix-cpu-timers.c
-+++ b/kernel/time/posix-cpu-timers.c
-@@ -226,7 +226,7 @@ static void task_sample_cputime(struct task_struct *p, u64 *samples)
- 	u64 stime, utime;
- 
- 	task_cputime(p, &utime, &stime);
--	store_samples(samples, stime, utime, p->se.sum_exec_runtime);
-+	store_samples(samples, stime, utime, tsk_seruntime(p));
- }
- 
- static void proc_sample_cputime_atomic(struct task_cputime_atomic *at,
-@@ -845,7 +845,7 @@ static void check_thread_timers(struct task_struct *tsk,
- 	soft = task_rlimit(tsk, RLIMIT_RTTIME);
- 	if (soft != RLIM_INFINITY) {
- 		/* Task RT timeout is accounted in jiffies. RTTIME is usec */
--		unsigned long rttime = tsk->rt.timeout * (USEC_PER_SEC / HZ);
-+		unsigned long rttime = tsk_rttimeout(tsk) * (USEC_PER_SEC / HZ);
- 		unsigned long hard = task_rlimit_max(tsk, RLIMIT_RTTIME);
- 
- 		/* At the hard limit, send SIGKILL. No further action. */
-diff --git a/kernel/time/timer.c b/kernel/time/timer.c
-index 4820823515e9..7dcadf9cd865 100644
---- a/kernel/time/timer.c
-+++ b/kernel/time/timer.c
-@@ -1567,7 +1567,7 @@ static unsigned long __next_timer_interrupt(struct timer_base *base)
-  * Check, if the next hrtimer event is before the next timer wheel
-  * event:
-  */
--static u64 cmp_next_hrtimer_event(u64 basem, u64 expires)
-+static u64 cmp_next_hrtimer_event(struct timer_base *base, u64 basem, u64 expires)
- {
- 	u64 nextevt = hrtimer_get_next_event();
- 
-@@ -1585,6 +1585,9 @@ static u64 cmp_next_hrtimer_event(u64 basem, u64 expires)
- 	if (nextevt <= basem)
- 		return basem;
- 
-+	if (nextevt < expires && nextevt - basem <= TICK_NSEC)
-+		base->is_idle = false;
-+
- 	/*
- 	 * Round up to the next jiffie. High resolution timers are
- 	 * off, so the hrtimers are expired in the tick and we need to
-@@ -1654,7 +1657,7 @@ u64 get_next_timer_interrupt(unsigned long basej, u64 basem)
- 	}
- 	raw_spin_unlock(&base->lock);
- 
--	return cmp_next_hrtimer_event(basem, expires);
-+	return cmp_next_hrtimer_event(base, basem, expires);
- }
- 
- /**
-diff --git a/kernel/trace/trace_selftest.c b/kernel/trace/trace_selftest.c
-index 69ee8ef12cee..6edb01f2fd81 100644
---- a/kernel/trace/trace_selftest.c
-+++ b/kernel/trace/trace_selftest.c
-@@ -1048,10 +1048,15 @@ static int trace_wakeup_test_thread(void *data)
- {
- 	/* Make this a -deadline thread */
- 	static const struct sched_attr attr = {
-+#ifdef CONFIG_SCHED_MUQSS
-+		/* No deadline on MuQSS, use RR */
-+		.sched_policy = SCHED_RR,
-+#else
- 		.sched_policy = SCHED_DEADLINE,
- 		.sched_runtime = 100000ULL,
- 		.sched_deadline = 10000000ULL,
- 		.sched_period = 10000000ULL
-+#endif
- 	};
- 	struct wakeup_test_data *x = data;
- 
--- 
-2.20.1
-
diff --git a/disabled/0001-futex.patch b/disabled/0001-futex.patch
deleted file mode 100644
index 72bf55a..0000000
--- a/disabled/0001-futex.patch
+++ /dev/null
@@ -1,1028 +0,0 @@
-From 3c0db5afb3180941bf51dd7c12541514d774a250 Mon Sep 17 00:00:00 2001
-From: Gabriel Krisman Bertazi <krisman@collabora.com>
-Date: Thu, 13 Feb 2020 18:45:22 -0300
-Subject: [PATCH 1/4] futex: Implement mechanism to wait on any of several
- futexes
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This is a new futex operation, called FUTEX_WAIT_MULTIPLE, which allows
-a thread to wait on several futexes at the same time, and be awoken by
-any of them.  In a sense, it implements one of the features that was
-supported by pooling on the old FUTEX_FD interface.
-
-The use case lies in the Wine implementation of the Windows NT interface
-WaitMultipleObjects. This Windows API function allows a thread to sleep
-waiting on the first of a set of event sources (mutexes, timers, signal,
-console input, etc) to signal.  Considering this is a primitive
-synchronization operation for Windows applications, being able to quickly
-signal events on the producer side, and quickly go to sleep on the
-consumer side is essential for good performance of those running over Wine.
-
-Wine developers have an implementation that uses eventfd, but it suffers
-from FD exhaustion (there is applications that go to the order of
-multi-milion FDs), and higher CPU utilization than this new operation.
-
-The futex list is passed as an array of `struct futex_wait_block`
-(pointer, value, bitset) to the kernel, which will enqueue all of them
-and sleep if none was already triggered. It returns a hint of which
-futex caused the wake up event to userspace, but the hint doesn't
-guarantee that is the only futex triggered.  Before calling the syscall
-again, userspace should traverse the list, trying to re-acquire any of
-the other futexes, to prevent an immediate -EWOULDBLOCK return code from
-the kernel.
-
-This was tested using three mechanisms:
-
-1) By reimplementing FUTEX_WAIT in terms of FUTEX_WAIT_MULTIPLE and
-running the unmodified tools/testing/selftests/futex and a full linux
-distro on top of this kernel.
-
-2) By an example code that exercises the FUTEX_WAIT_MULTIPLE path on a
-multi-threaded, event-handling setup.
-
-3) By running the Wine fsync with Valve's Proton compatibility code
-implementation and executing multi-threaded applications, in particular
-modern games, on top of this implementation.
-
-Changes were tested for the following ABIs: x86_64, i386 and x32.
-Support for x32 applications is not implemented since it would
-take a major rework adding a new entry point and splitting the current
-futex 64 entry point in two and we can't change the current x32 syscall
-number without breaking user space compatibility.
-
-CC: Steven Rostedt <rostedt@goodmis.org>
-Cc: Richard Yao <ryao@gentoo.org>
-Cc: Thomas Gleixner <tglx@linutronix.de>
-Cc: Peter Zijlstra <peterz@infradead.org>
-Co-developed-by: Zebediah Figura <z.figura12@gmail.com>
-Signed-off-by: Zebediah Figura <z.figura12@gmail.com>
-Co-developed-by: Steven Noonan <steven@valvesoftware.com>
-Signed-off-by: Steven Noonan <steven@valvesoftware.com>
-Co-developed-by: Pierre-Loup A. Griffais <pgriffais@valvesoftware.com>
-Signed-off-by: Pierre-Loup A. Griffais <pgriffais@valvesoftware.com>
-Signed-off-by: Gabriel Krisman Bertazi <krisman@collabora.com>
-[Added compatibility code]
-Co-developed-by: André Almeida <andrealmeid@collabora.com>
-Signed-off-by: André Almeida <andrealmeid@collabora.com>
----
- include/uapi/linux/futex.h |  20 ++
- kernel/futex.c             | 363 ++++++++++++++++++++++++++++++++++++-
- 2 files changed, 379 insertions(+), 4 deletions(-)
-
-diff --git a/include/uapi/linux/futex.h b/include/uapi/linux/futex.h
-index a89eb0acc..a3e760886 100644
---- a/include/uapi/linux/futex.h
-+++ b/include/uapi/linux/futex.h
-@@ -21,6 +21,7 @@
- #define FUTEX_WAKE_BITSET	10
- #define FUTEX_WAIT_REQUEUE_PI	11
- #define FUTEX_CMP_REQUEUE_PI	12
-+#define FUTEX_WAIT_MULTIPLE	31
- 
- #define FUTEX_PRIVATE_FLAG	128
- #define FUTEX_CLOCK_REALTIME	256
-@@ -40,6 +41,8 @@
- 					 FUTEX_PRIVATE_FLAG)
- #define FUTEX_CMP_REQUEUE_PI_PRIVATE	(FUTEX_CMP_REQUEUE_PI | \
- 					 FUTEX_PRIVATE_FLAG)
-+#define FUTEX_WAIT_MULTIPLE_PRIVATE	(FUTEX_WAIT_MULTIPLE | \
-+					 FUTEX_PRIVATE_FLAG)
- 
- /*
-  * Support for robust futexes: the kernel cleans up held futexes at
-@@ -150,4 +153,21 @@ struct robust_list_head {
-   (((op & 0xf) << 28) | ((cmp & 0xf) << 24)		\
-    | ((oparg & 0xfff) << 12) | (cmparg & 0xfff))
- 
-+/*
-+ * Maximum number of multiple futexes to wait for
-+ */
-+#define FUTEX_MULTIPLE_MAX_COUNT	128
-+
-+/**
-+ * struct futex_wait_block - Block of futexes to be waited for
-+ * @uaddr:	User address of the futex
-+ * @val:	Futex value expected by userspace
-+ * @bitset:	Bitset for the optional bitmasked wakeup
-+ */
-+struct futex_wait_block {
-+	__u32 __user *uaddr;
-+	__u32 val;
-+	__u32 bitset;
-+};
-+
- #endif /* _UAPI_LINUX_FUTEX_H */
-diff --git a/kernel/futex.c b/kernel/futex.c
-index b59532862..2fbfb0b80 100644
---- a/kernel/futex.c
-+++ b/kernel/futex.c
-@@ -214,6 +214,8 @@ struct futex_pi_state {
-  * @rt_waiter:		rt_waiter storage for use with requeue_pi
-  * @requeue_pi_key:	the requeue_pi target futex key
-  * @bitset:		bitset for the optional bitmasked wakeup
-+ * @uaddr:             userspace address of futex
-+ * @uval:              expected futex's value
-  *
-  * We use this hashed waitqueue, instead of a normal wait_queue_entry_t, so
-  * we can wake only the relevant ones (hashed queues may be shared).
-@@ -236,6 +238,8 @@ struct futex_q {
- 	struct rt_mutex_waiter *rt_waiter;
- 	union futex_key *requeue_pi_key;
- 	u32 bitset;
-+	u32 __user *uaddr;
-+	u32 uval;
- } __randomize_layout;
- 
- static const struct futex_q futex_q_init = {
-@@ -2346,6 +2350,29 @@ static int unqueue_me(struct futex_q *q)
- 	return ret;
- }
- 
-+/**
-+ * unqueue_multiple() - Remove several futexes from their futex_hash_bucket
-+ * @q:	The list of futexes to unqueue
-+ * @count: Number of futexes in the list
-+ *
-+ * Helper to unqueue a list of futexes. This can't fail.
-+ *
-+ * Return:
-+ *  - >=0 - Index of the last futex that was awoken;
-+ *  - -1  - If no futex was awoken
-+ */
-+static int unqueue_multiple(struct futex_q *q, int count)
-+{
-+	int ret = -1;
-+	int i;
-+
-+	for (i = 0; i < count; i++) {
-+		if (!unqueue_me(&q[i]))
-+			ret = i;
-+	}
-+	return ret;
-+}
-+
- /*
-  * PI futexes can not be requeued and must remove themself from the
-  * hash bucket. The hash bucket lock (i.e. lock_ptr) is held on entry
-@@ -2709,6 +2736,211 @@ static int futex_wait_setup(u32 __user *uaddr, u32 val, unsigned int flags,
- 	return ret;
- }
- 
-+/**
-+ * futex_wait_multiple_setup() - Prepare to wait and enqueue multiple futexes
-+ * @qs:		The corresponding futex list
-+ * @count:	The size of the lists
-+ * @flags:	Futex flags (FLAGS_SHARED, etc.)
-+ * @awaken:	Index of the last awoken futex
-+ *
-+ * Prepare multiple futexes in a single step and enqueue them. This may fail if
-+ * the futex list is invalid or if any futex was already awoken. On success the
-+ * task is ready to interruptible sleep.
-+ *
-+ * Return:
-+ *  -  1 - One of the futexes was awaken by another thread
-+ *  -  0 - Success
-+ *  - <0 - -EFAULT, -EWOULDBLOCK or -EINVAL
-+ */
-+static int futex_wait_multiple_setup(struct futex_q *qs, int count,
-+				     unsigned int flags, int *awaken)
-+{
-+	struct futex_hash_bucket *hb;
-+	int ret, i;
-+	u32 uval;
-+
-+	/*
-+	 * Enqueuing multiple futexes is tricky, because we need to
-+	 * enqueue each futex in the list before dealing with the next
-+	 * one to avoid deadlocking on the hash bucket.  But, before
-+	 * enqueuing, we need to make sure that current->state is
-+	 * TASK_INTERRUPTIBLE, so we don't absorb any awake events, which
-+	 * cannot be done before the get_futex_key of the next key,
-+	 * because it calls get_user_pages, which can sleep.  Thus, we
-+	 * fetch the list of futexes keys in two steps, by first pinning
-+	 * all the memory keys in the futex key, and only then we read
-+	 * each key and queue the corresponding futex.
-+	 */
-+retry:
-+	for (i = 0; i < count; i++) {
-+		qs[i].key = FUTEX_KEY_INIT;
-+		ret = get_futex_key(qs[i].uaddr, flags & FLAGS_SHARED,
-+				    &qs[i].key, FUTEX_READ);
-+		if (unlikely(ret)) {
-+			for (--i; i >= 0; i--)
-+				put_futex_key(&qs[i].key);
-+			return ret;
-+		}
-+	}
-+
-+	set_current_state(TASK_INTERRUPTIBLE);
-+
-+	for (i = 0; i < count; i++) {
-+		struct futex_q *q = &qs[i];
-+
-+		hb = queue_lock(q);
-+
-+		ret = get_futex_value_locked(&uval, q->uaddr);
-+		if (ret) {
-+			/*
-+			 * We need to try to handle the fault, which
-+			 * cannot be done without sleep, so we need to
-+			 * undo all the work already done, to make sure
-+			 * we don't miss any wake ups.  Therefore, clean
-+			 * up, handle the fault and retry from the
-+			 * beginning.
-+			 */
-+			queue_unlock(hb);
-+
-+			/*
-+			 * Keys 0..(i-1) are implicitly put
-+			 * on unqueue_multiple.
-+			 */
-+			put_futex_key(&q->key);
-+
-+			*awaken = unqueue_multiple(qs, i);
-+
-+			__set_current_state(TASK_RUNNING);
-+
-+			/*
-+			 * On a real fault, prioritize the error even if
-+			 * some other futex was awoken.  Userspace gave
-+			 * us a bad address, -EFAULT them.
-+			 */
-+			ret = get_user(uval, q->uaddr);
-+			if (ret)
-+				return ret;
-+
-+			/*
-+			 * Even if the page fault was handled, If
-+			 * something was already awaken, we can safely
-+			 * give up and succeed to give a hint for userspace to
-+			 * acquire the right futex faster.
-+			 */
-+			if (*awaken >= 0)
-+				return 1;
-+
-+			goto retry;
-+		}
-+
-+		if (uval != q->uval) {
-+			queue_unlock(hb);
-+
-+			put_futex_key(&qs[i].key);
-+
-+			/*
-+			 * If something was already awaken, we can
-+			 * safely ignore the error and succeed.
-+			 */
-+			*awaken = unqueue_multiple(qs, i);
-+			__set_current_state(TASK_RUNNING);
-+			if (*awaken >= 0)
-+				return 1;
-+
-+			return -EWOULDBLOCK;
-+		}
-+
-+		/*
-+		 * The bucket lock can't be held while dealing with the
-+		 * next futex. Queue each futex at this moment so hb can
-+		 * be unlocked.
-+		 */
-+		queue_me(&qs[i], hb);
-+	}
-+	return 0;
-+}
-+
-+/**
-+ * futex_wait_multiple() - Prepare to wait on and enqueue several futexes
-+ * @qs:		The list of futexes to wait on
-+ * @op:		Operation code from futex's syscall
-+ * @count:	The number of objects
-+ * @abs_time:	Timeout before giving up and returning to userspace
-+ *
-+ * Entry point for the FUTEX_WAIT_MULTIPLE futex operation, this function
-+ * sleeps on a group of futexes and returns on the first futex that
-+ * triggered, or after the timeout has elapsed.
-+ *
-+ * Return:
-+ *  - >=0 - Hint to the futex that was awoken
-+ *  - <0  - On error
-+ */
-+static int futex_wait_multiple(struct futex_q *qs, int op,
-+			       u32 count, ktime_t *abs_time)
-+{
-+	struct hrtimer_sleeper timeout, *to;
-+	int ret, flags = 0, hint = 0;
-+	unsigned int i;
-+
-+	if (!(op & FUTEX_PRIVATE_FLAG))
-+		flags |= FLAGS_SHARED;
-+
-+	if (op & FUTEX_CLOCK_REALTIME)
-+		flags |= FLAGS_CLOCKRT;
-+
-+	to = futex_setup_timer(abs_time, &timeout, flags, 0);
-+	while (1) {
-+		ret = futex_wait_multiple_setup(qs, count, flags, &hint);
-+		if (ret) {
-+			if (ret > 0) {
-+				/* A futex was awaken during setup */
-+				ret = hint;
-+			}
-+			break;
-+		}
-+
-+		if (to)
-+			hrtimer_start_expires(&to->timer, HRTIMER_MODE_ABS);
-+
-+		/*
-+		 * Avoid sleeping if another thread already tried to
-+		 * wake us.
-+		 */
-+		for (i = 0; i < count; i++) {
-+			if (plist_node_empty(&qs[i].list))
-+				break;
-+		}
-+
-+		if (i == count && (!to || to->task))
-+			freezable_schedule();
-+
-+		ret = unqueue_multiple(qs, count);
-+
-+		__set_current_state(TASK_RUNNING);
-+
-+		if (ret >= 0)
-+			break;
-+		if (to && !to->task) {
-+			ret = -ETIMEDOUT;
-+			break;
-+		} else if (signal_pending(current)) {
-+			ret = -ERESTARTSYS;
-+			break;
-+		}
-+		/*
-+		 * The final case is a spurious wakeup, for
-+		 * which just retry.
-+		 */
-+	}
-+
-+	if (to) {
-+		hrtimer_cancel(&to->timer);
-+		destroy_hrtimer_on_stack(&to->timer);
-+	}
-+
-+	return ret;
-+}
-+
- static int futex_wait(u32 __user *uaddr, unsigned int flags, u32 val,
- 		      ktime_t *abs_time, u32 bitset)
- {
-@@ -3833,6 +4065,43 @@ long do_futex(u32 __user *uaddr, int op, u32 val, ktime_t *timeout,
- 	return -ENOSYS;
- }
- 
-+/**
-+ * futex_read_wait_block - Read an array of futex_wait_block from userspace
-+ * @uaddr:	Userspace address of the block
-+ * @count:	Number of blocks to be read
-+ *
-+ * This function creates and allocate an array of futex_q (we zero it to
-+ * initialize the fields) and then, for each futex_wait_block element from
-+ * userspace, fill a futex_q element with proper values.
-+ */
-+inline struct futex_q *futex_read_wait_block(u32 __user *uaddr, u32 count)
-+{
-+	unsigned int i;
-+	struct futex_q *qs;
-+	struct futex_wait_block fwb;
-+	struct futex_wait_block __user *entry =
-+		(struct futex_wait_block __user *)uaddr;
-+
-+	if (!count || count > FUTEX_MULTIPLE_MAX_COUNT)
-+		return ERR_PTR(-EINVAL);
-+
-+	qs = kcalloc(count, sizeof(*qs), GFP_KERNEL);
-+	if (!qs)
-+		return ERR_PTR(-ENOMEM);
-+
-+	for (i = 0; i < count; i++) {
-+		if (copy_from_user(&fwb, &entry[i], sizeof(fwb))) {
-+			kfree(qs);
-+			return ERR_PTR(-EFAULT);
-+		}
-+
-+		qs[i].uaddr = fwb.uaddr;
-+		qs[i].uval = fwb.val;
-+		qs[i].bitset = fwb.bitset;
-+	}
-+
-+	return qs;
-+}
- 
- SYSCALL_DEFINE6(futex, u32 __user *, uaddr, int, op, u32, val,
- 		struct __kernel_timespec __user *, utime, u32 __user *, uaddr2,
-@@ -3845,7 +4114,8 @@ SYSCALL_DEFINE6(futex, u32 __user *, uaddr, int, op, u32, val,
- 
- 	if (utime && (cmd == FUTEX_WAIT || cmd == FUTEX_LOCK_PI ||
- 		      cmd == FUTEX_WAIT_BITSET ||
--		      cmd == FUTEX_WAIT_REQUEUE_PI)) {
-+		      cmd == FUTEX_WAIT_REQUEUE_PI ||
-+		      cmd == FUTEX_WAIT_MULTIPLE)) {
- 		if (unlikely(should_fail_futex(!(op & FUTEX_PRIVATE_FLAG))))
- 			return -EFAULT;
- 		if (get_timespec64(&ts, utime))
-@@ -3854,7 +4124,7 @@ SYSCALL_DEFINE6(futex, u32 __user *, uaddr, int, op, u32, val,
- 			return -EINVAL;
- 
- 		t = timespec64_to_ktime(ts);
--		if (cmd == FUTEX_WAIT)
-+		if (cmd == FUTEX_WAIT || cmd == FUTEX_WAIT_MULTIPLE)
- 			t = ktime_add_safe(ktime_get(), t);
- 		tp = &t;
- 	}
-@@ -3866,6 +4136,25 @@ SYSCALL_DEFINE6(futex, u32 __user *, uaddr, int, op, u32, val,
- 	    cmd == FUTEX_CMP_REQUEUE_PI || cmd == FUTEX_WAKE_OP)
- 		val2 = (u32) (unsigned long) utime;
- 
-+	if (cmd == FUTEX_WAIT_MULTIPLE) {
-+		int ret;
-+		struct futex_q *qs;
-+
-+#ifdef CONFIG_X86_X32
-+		if (unlikely(in_x32_syscall()))
-+			return -ENOSYS;
-+#endif
-+		qs = futex_read_wait_block(uaddr, val);
-+
-+		if (IS_ERR(qs))
-+			return PTR_ERR(qs);
-+
-+		ret = futex_wait_multiple(qs, op, val, tp);
-+		kfree(qs);
-+
-+		return ret;
-+	}
-+
- 	return do_futex(uaddr, op, val, tp, uaddr2, val2, val3);
- }
- 
-@@ -4028,6 +4317,58 @@ COMPAT_SYSCALL_DEFINE3(get_robust_list, int, pid,
- #endif /* CONFIG_COMPAT */
- 
- #ifdef CONFIG_COMPAT_32BIT_TIME
-+/**
-+ * struct compat_futex_wait_block - Block of futexes to be waited for
-+ * @uaddr:	User address of the futex (compatible pointer)
-+ * @val:	Futex value expected by userspace
-+ * @bitset:	Bitset for the optional bitmasked wakeup
-+ */
-+struct compat_futex_wait_block {
-+	compat_uptr_t	uaddr;
-+	__u32 pad;
-+	__u32 val;
-+	__u32 bitset;
-+};
-+
-+/**
-+ * compat_futex_read_wait_block - Read an array of futex_wait_block from
-+ * userspace
-+ * @uaddr:	Userspace address of the block
-+ * @count:	Number of blocks to be read
-+ *
-+ * This function does the same as futex_read_wait_block(), except that it
-+ * converts the pointer to the futex from the compat version to the regular one.
-+ */
-+inline struct futex_q *compat_futex_read_wait_block(u32 __user *uaddr,
-+						    u32 count)
-+{
-+	unsigned int i;
-+	struct futex_q *qs;
-+	struct compat_futex_wait_block fwb;
-+	struct compat_futex_wait_block __user *entry =
-+		(struct compat_futex_wait_block __user *)uaddr;
-+
-+	if (!count || count > FUTEX_MULTIPLE_MAX_COUNT)
-+		return ERR_PTR(-EINVAL);
-+
-+	qs = kcalloc(count, sizeof(*qs), GFP_KERNEL);
-+	if (!qs)
-+		return ERR_PTR(-ENOMEM);
-+
-+	for (i = 0; i < count; i++) {
-+		if (copy_from_user(&fwb, &entry[i], sizeof(fwb))) {
-+			kfree(qs);
-+			return ERR_PTR(-EFAULT);
-+		}
-+
-+		qs[i].uaddr = compat_ptr(fwb.uaddr);
-+		qs[i].uval = fwb.val;
-+		qs[i].bitset = fwb.bitset;
-+	}
-+
-+	return qs;
-+}
-+
- SYSCALL_DEFINE6(futex_time32, u32 __user *, uaddr, int, op, u32, val,
- 		struct old_timespec32 __user *, utime, u32 __user *, uaddr2,
- 		u32, val3)
-@@ -4039,14 +4380,15 @@ SYSCALL_DEFINE6(futex_time32, u32 __user *, uaddr, int, op, u32, val,
- 
- 	if (utime && (cmd == FUTEX_WAIT || cmd == FUTEX_LOCK_PI ||
- 		      cmd == FUTEX_WAIT_BITSET ||
--		      cmd == FUTEX_WAIT_REQUEUE_PI)) {
-+		      cmd == FUTEX_WAIT_REQUEUE_PI ||
-+		      cmd == FUTEX_WAIT_MULTIPLE)) {
- 		if (get_old_timespec32(&ts, utime))
- 			return -EFAULT;
- 		if (!timespec64_valid(&ts))
- 			return -EINVAL;
- 
- 		t = timespec64_to_ktime(ts);
--		if (cmd == FUTEX_WAIT)
-+		if (cmd == FUTEX_WAIT || cmd == FUTEX_WAIT_MULTIPLE)
- 			t = ktime_add_safe(ktime_get(), t);
- 		tp = &t;
- 	}
-@@ -4054,6 +4396,19 @@ SYSCALL_DEFINE6(futex_time32, u32 __user *, uaddr, int, op, u32, val,
- 	    cmd == FUTEX_CMP_REQUEUE_PI || cmd == FUTEX_WAKE_OP)
- 		val2 = (int) (unsigned long) utime;
- 
-+	if (cmd == FUTEX_WAIT_MULTIPLE) {
-+		int ret;
-+		struct futex_q *qs = compat_futex_read_wait_block(uaddr, val);
-+
-+		if (IS_ERR(qs))
-+			return PTR_ERR(qs);
-+
-+		ret = futex_wait_multiple(qs, op, val, tp);
-+		kfree(qs);
-+
-+		return ret;
-+	}
-+
- 	return do_futex(uaddr, op, val, tp, uaddr2, val2, val3);
- }
- #endif /* CONFIG_COMPAT_32BIT_TIME */
--- 
-2.27.0.rc2
-
-
-From 3b2db8473486da199622782b28a9de69c4446323 Mon Sep 17 00:00:00 2001
-From: Gabriel Krisman Bertazi <krisman@collabora.com>
-Date: Thu, 13 Feb 2020 18:45:23 -0300
-Subject: [PATCH 2/4] selftests: futex: Add FUTEX_WAIT_MULTIPLE timeout test
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add test for timeout when waiting for multiple futexes. Skip the test if
-it's a x32 application and the kernel returned the approtiaded error,
-since this ABI is not supported for this operation.
-
-Signed-off-by: Gabriel Krisman Bertazi <krisman@collabora.com>
-Co-developed-by: André Almeida <andrealmeid@collabora.com>
-Signed-off-by: André Almeida <andrealmeid@collabora.com>
----
- .../futex/functional/futex_wait_timeout.c     | 38 ++++++++++++++++++-
- .../selftests/futex/include/futextest.h       | 22 +++++++++++
- 2 files changed, 58 insertions(+), 2 deletions(-)
-
-diff --git a/tools/testing/selftests/futex/functional/futex_wait_timeout.c b/tools/testing/selftests/futex/functional/futex_wait_timeout.c
-index ee55e6d38..2a63e1c2c 100644
---- a/tools/testing/selftests/futex/functional/futex_wait_timeout.c
-+++ b/tools/testing/selftests/futex/functional/futex_wait_timeout.c
-@@ -11,6 +11,7 @@
-  *
-  * HISTORY
-  *      2009-Nov-6: Initial version by Darren Hart <dvhart@linux.intel.com>
-+ *      2019-Dec-13: Add WAIT_MULTIPLE test by Krisman <krisman@collabora.com>
-  *
-  *****************************************************************************/
- 
-@@ -41,6 +42,8 @@ int main(int argc, char *argv[])
- {
- 	futex_t f1 = FUTEX_INITIALIZER;
- 	struct timespec to;
-+	time_t secs;
-+	struct futex_wait_block fwb = {&f1, f1, 0};
- 	int res, ret = RET_PASS;
- 	int c;
- 
-@@ -65,7 +68,7 @@ int main(int argc, char *argv[])
- 	}
- 
- 	ksft_print_header();
--	ksft_set_plan(1);
-+	ksft_set_plan(2);
- 	ksft_print_msg("%s: Block on a futex and wait for timeout\n",
- 	       basename(argv[0]));
- 	ksft_print_msg("\tArguments: timeout=%ldns\n", timeout_ns);
-@@ -79,8 +82,39 @@ int main(int argc, char *argv[])
- 	if (!res || errno != ETIMEDOUT) {
- 		fail("futex_wait returned %d\n", ret < 0 ? errno : ret);
- 		ret = RET_FAIL;
-+	} else
-+		ksft_test_result_pass("futex_wait timeout succeeds\n");
-+
-+	info("Calling futex_wait_multiple on f1: %u @ %p\n", f1, &f1);
-+
-+	/* Setup absolute time */
-+	ret = clock_gettime(CLOCK_REALTIME, &to);
-+	secs = (to.tv_nsec + timeout_ns) / 1000000000;
-+	to.tv_nsec = ((int64_t)to.tv_nsec + timeout_ns) % 1000000000;
-+	to.tv_sec += secs;
-+	info("to.tv_sec  = %ld\n", to.tv_sec);
-+	info("to.tv_nsec = %ld\n", to.tv_nsec);
-+
-+	res = futex_wait_multiple(&fwb, 1, &to,
-+				  FUTEX_PRIVATE_FLAG | FUTEX_CLOCK_REALTIME);
-+
-+#ifdef __ILP32__
-+	if (res == -1 && errno == ENOSYS) {
-+		ksft_test_result_skip("futex_wait_multiple not supported at x32\n");
-+	} else {
-+		ksft_test_result_fail("futex_wait_multiple returned %d\n",
-+				      res < 0 ? errno : res);
-+		ret = RET_FAIL;
- 	}
-+#else
-+	if (!res || errno != ETIMEDOUT) {
-+		ksft_test_result_fail("futex_wait_multiple returned %d\n",
-+				      res < 0 ? errno : res);
-+		ret = RET_FAIL;
-+	} else
-+		ksft_test_result_pass("futex_wait_multiple timeout succeeds\n");
-+#endif /* __ILP32__ */
- 
--	print_result(TEST_NAME, ret);
-+	ksft_print_cnts();
- 	return ret;
- }
-diff --git a/tools/testing/selftests/futex/include/futextest.h b/tools/testing/selftests/futex/include/futextest.h
-index ddbcfc9b7..bb103bef4 100644
---- a/tools/testing/selftests/futex/include/futextest.h
-+++ b/tools/testing/selftests/futex/include/futextest.h
-@@ -38,6 +38,14 @@ typedef volatile u_int32_t futex_t;
- #ifndef FUTEX_CMP_REQUEUE_PI
- #define FUTEX_CMP_REQUEUE_PI		12
- #endif
-+#ifndef FUTEX_WAIT_MULTIPLE
-+#define FUTEX_WAIT_MULTIPLE		13
-+struct futex_wait_block {
-+	futex_t *uaddr;
-+	futex_t val;
-+	__u32 bitset;
-+};
-+#endif
- #ifndef FUTEX_WAIT_REQUEUE_PI_PRIVATE
- #define FUTEX_WAIT_REQUEUE_PI_PRIVATE	(FUTEX_WAIT_REQUEUE_PI | \
- 					 FUTEX_PRIVATE_FLAG)
-@@ -80,6 +88,20 @@ futex_wait(futex_t *uaddr, futex_t val, struct timespec *timeout, int opflags)
- 	return futex(uaddr, FUTEX_WAIT, val, timeout, NULL, 0, opflags);
- }
- 
-+/**
-+ * futex_wait_multiple() - block on several futexes with optional timeout
-+ * @fwb:	wait block user space address
-+ * @count:	number of entities at fwb
-+ * @timeout:	absolute timeout
-+ */
-+static inline int
-+futex_wait_multiple(struct futex_wait_block *fwb, int count,
-+		    struct timespec *timeout, int opflags)
-+{
-+	return futex(fwb, FUTEX_WAIT_MULTIPLE, count, timeout, NULL, 0,
-+		     opflags);
-+}
-+
- /**
-  * futex_wake() - wake one or more tasks blocked on uaddr
-  * @nr_wake:	wake up to this many tasks
--- 
-2.27.0.rc2
-
-
-From b285216bc7b31eeba9b0e8081fe312bac7514931 Mon Sep 17 00:00:00 2001
-From: Gabriel Krisman Bertazi <krisman@collabora.com>
-Date: Thu, 13 Feb 2020 18:45:24 -0300
-Subject: [PATCH 3/4] selftests: futex: Add FUTEX_WAIT_MULTIPLE wouldblock test
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add test for wouldblock return when waiting for multiple futexes. Skip
-the test if it's a x32 application and the kernel returned the approtiaded
-error, since this ABI is not supported for this operation.
-
-Signed-off-by: Gabriel Krisman Bertazi <krisman@collabora.com>
-Co-developed-by: André Almeida <andrealmeid@collabora.com>
-Signed-off-by: André Almeida <andrealmeid@collabora.com>
----
- .../futex/functional/futex_wait_wouldblock.c  | 28 +++++++++++++++++--
- 1 file changed, 26 insertions(+), 2 deletions(-)
-
-diff --git a/tools/testing/selftests/futex/functional/futex_wait_wouldblock.c b/tools/testing/selftests/futex/functional/futex_wait_wouldblock.c
-index 0ae390ff8..bcbac0429 100644
---- a/tools/testing/selftests/futex/functional/futex_wait_wouldblock.c
-+++ b/tools/testing/selftests/futex/functional/futex_wait_wouldblock.c
-@@ -12,6 +12,7 @@
-  *
-  * HISTORY
-  *      2009-Nov-14: Initial version by Gowrishankar <gowrishankar.m@in.ibm.com>
-+ *      2019-Dec-13: Add WAIT_MULTIPLE test by Krisman <krisman@collabora.com>
-  *
-  *****************************************************************************/
- 
-@@ -40,6 +41,7 @@ int main(int argc, char *argv[])
- {
- 	struct timespec to = {.tv_sec = 0, .tv_nsec = timeout_ns};
- 	futex_t f1 = FUTEX_INITIALIZER;
-+	struct futex_wait_block fwb = {&f1, f1+1, 0};
- 	int res, ret = RET_PASS;
- 	int c;
- 
-@@ -61,7 +63,7 @@ int main(int argc, char *argv[])
- 	}
- 
- 	ksft_print_header();
--	ksft_set_plan(1);
-+	ksft_set_plan(2);
- 	ksft_print_msg("%s: Test the unexpected futex value in FUTEX_WAIT\n",
- 	       basename(argv[0]));
- 
-@@ -71,8 +73,30 @@ int main(int argc, char *argv[])
- 		fail("futex_wait returned: %d %s\n",
- 		     res ? errno : res, res ? strerror(errno) : "");
- 		ret = RET_FAIL;
-+	} else
-+		ksft_test_result_pass("futex_wait wouldblock succeeds\n");
-+
-+	info("Calling futex_wait_multiple on f1: %u @ %p with val=%u\n",
-+	     f1, &f1, f1+1);
-+	res = futex_wait_multiple(&fwb, 1, NULL, FUTEX_PRIVATE_FLAG);
-+
-+#ifdef __ILP32__
-+	if (res != -1 || errno != ENOSYS) {
-+		ksft_test_result_fail("futex_wait_multiple returned %d\n",
-+				      res < 0 ? errno : res);
-+		ret = RET_FAIL;
-+	} else {
-+		ksft_test_result_skip("futex_wait_multiple not supported at x32\n");
-+	}
-+#else
-+	if (!res || errno != EWOULDBLOCK) {
-+		ksft_test_result_fail("futex_wait_multiple returned %d\n",
-+				      res < 0 ? errno : res);
-+		ret = RET_FAIL;
- 	}
-+	ksft_test_result_pass("futex_wait_multiple wouldblock succeeds\n");
-+#endif /* __ILP32__ */
- 
--	print_result(TEST_NAME, ret);
-+	ksft_print_cnts();
- 	return ret;
- }
--- 
-2.27.0.rc2
-
-
-From c2a6902699480877846a07e7567fbce94b370cce Mon Sep 17 00:00:00 2001
-From: Gabriel Krisman Bertazi <krisman@collabora.com>
-Date: Thu, 13 Feb 2020 18:45:25 -0300
-Subject: [PATCH 4/4] selftests: futex: Add FUTEX_WAIT_MULTIPLE wake up test
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add test for wait at multiple futexes mechanism. Skip the test if it's a
-x32 application and the kernel returned the approtiaded error, since this
-ABI is not supported for this operation.
-
-Signed-off-by: Gabriel Krisman Bertazi <krisman@collabora.com>
-Co-developed-by: André Almeida <andrealmeid@collabora.com>
-Signed-off-by: André Almeida <andrealmeid@collabora.com>
----
- .../selftests/futex/functional/.gitignore     |   1 +
- .../selftests/futex/functional/Makefile       |   3 +-
- .../futex/functional/futex_wait_multiple.c    | 173 ++++++++++++++++++
- .../testing/selftests/futex/functional/run.sh |   3 +
- 4 files changed, 179 insertions(+), 1 deletion(-)
- create mode 100644 tools/testing/selftests/futex/functional/futex_wait_multiple.c
-
-diff --git a/tools/testing/selftests/futex/functional/.gitignore b/tools/testing/selftests/futex/functional/.gitignore
-index 0efcd494d..03a4bedce 100644
---- a/tools/testing/selftests/futex/functional/.gitignore
-+++ b/tools/testing/selftests/futex/functional/.gitignore
-@@ -6,3 +6,4 @@ futex_wait_private_mapped_file
- futex_wait_timeout
- futex_wait_uninitialized_heap
- futex_wait_wouldblock
-+futex_wait_multiple
-diff --git a/tools/testing/selftests/futex/functional/Makefile b/tools/testing/selftests/futex/functional/Makefile
-index 23207829e..26562f2d7 100644
---- a/tools/testing/selftests/futex/functional/Makefile
-+++ b/tools/testing/selftests/futex/functional/Makefile
-@@ -14,7 +14,8 @@ TEST_GEN_FILES := \
- 	futex_requeue_pi_signal_restart \
- 	futex_requeue_pi_mismatched_ops \
- 	futex_wait_uninitialized_heap \
--	futex_wait_private_mapped_file
-+	futex_wait_private_mapped_file \
-+	futex_wait_multiple
- 
- TEST_PROGS := run.sh
- 
-diff --git a/tools/testing/selftests/futex/functional/futex_wait_multiple.c b/tools/testing/selftests/futex/functional/futex_wait_multiple.c
-new file mode 100644
-index 000000000..b48422e79
---- /dev/null
-+++ b/tools/testing/selftests/futex/functional/futex_wait_multiple.c
-@@ -0,0 +1,173 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later
-+/******************************************************************************
-+ *
-+ *   Copyright © Collabora, Ltd., 2019
-+ *
-+ * DESCRIPTION
-+ *      Test basic semantics of FUTEX_WAIT_MULTIPLE
-+ *
-+ * AUTHOR
-+ *      Gabriel Krisman Bertazi <krisman@collabora.com>
-+ *
-+ * HISTORY
-+ *      2019-Dec-13: Initial version by Krisman <krisman@collabora.com>
-+ *
-+ *****************************************************************************/
-+
-+#include <errno.h>
-+#include <getopt.h>
-+#include <stdio.h>
-+#include <stdlib.h>
-+#include <string.h>
-+#include <time.h>
-+#include <pthread.h>
-+#include "futextest.h"
-+#include "logging.h"
-+
-+#define TEST_NAME "futex-wait-multiple"
-+#define timeout_ns 100000
-+#define MAX_COUNT 128
-+#define WAKE_WAIT_US 3000000
-+
-+int ret = RET_PASS;
-+char *progname;
-+futex_t f[MAX_COUNT] = {0};
-+struct futex_wait_block fwb[MAX_COUNT];
-+
-+void usage(char *prog)
-+{
-+	printf("Usage: %s\n", prog);
-+	printf("  -c	Use color\n");
-+	printf("  -h	Display this help message\n");
-+	printf("  -v L	Verbosity level: %d=QUIET %d=CRITICAL %d=INFO\n",
-+	       VQUIET, VCRITICAL, VINFO);
-+}
-+
-+void test_count_overflow(void)
-+{
-+	futex_t f = FUTEX_INITIALIZER;
-+	struct futex_wait_block fwb[MAX_COUNT+1];
-+	int res, i;
-+
-+	ksft_print_msg("%s: Test a too big number of futexes\n", progname);
-+
-+	for (i = 0; i < MAX_COUNT+1; i++) {
-+		fwb[i].uaddr = &f;
-+		fwb[i].val = f;
-+		fwb[i].bitset = 0;
-+	}
-+
-+	res = futex_wait_multiple(fwb, MAX_COUNT+1, NULL, FUTEX_PRIVATE_FLAG);
-+
-+#ifdef __ILP32__
-+	if (res != -1 || errno != ENOSYS) {
-+		ksft_test_result_fail("futex_wait_multiple returned %d\n",
-+				      res < 0 ? errno : res);
-+		ret = RET_FAIL;
-+	} else {
-+		ksft_test_result_skip("futex_wait_multiple not supported at x32\n");
-+	}
-+#else
-+	if (res != -1 || errno != EINVAL) {
-+		ksft_test_result_fail("futex_wait_multiple returned %d\n",
-+				      res < 0 ? errno : res);
-+		ret = RET_FAIL;
-+	} else {
-+		ksft_test_result_pass("futex_wait_multiple count overflow succeed\n");
-+	}
-+
-+#endif /* __ILP32__ */
-+}
-+
-+void *waiterfn(void *arg)
-+{
-+	int res;
-+
-+	res = futex_wait_multiple(fwb, MAX_COUNT, NULL, FUTEX_PRIVATE_FLAG);
-+
-+#ifdef __ILP32__
-+	if (res != -1 || errno != ENOSYS) {
-+		ksft_test_result_fail("futex_wait_multiple returned %d\n",
-+				      res < 0 ? errno : res);
-+		ret = RET_FAIL;
-+	} else {
-+		ksft_test_result_skip("futex_wait_multiple not supported at x32\n");
-+	}
-+#else
-+	if (res < 0)
-+		ksft_print_msg("waiter failed %d\n", res);
-+
-+	info("futex_wait_multiple: Got hint futex %d was freed\n", res);
-+#endif /* __ILP32__ */
-+
-+	return NULL;
-+}
-+
-+void test_fwb_wakeup(void)
-+{
-+	int res, i;
-+	pthread_t waiter;
-+
-+	ksft_print_msg("%s: Test wake up in a list of futex\n", progname);
-+
-+	for (i = 0; i < MAX_COUNT; i++) {
-+		fwb[i].uaddr = &f[i];
-+		fwb[i].val = f[i];
-+		fwb[i].bitset = 0xffffffff;
-+	}
-+
-+	res = pthread_create(&waiter, NULL, waiterfn, NULL);
-+	if (res) {
-+		ksft_test_result_fail("Creating waiting thread failed");
-+		ksft_exit_fail();
-+	}
-+
-+	usleep(WAKE_WAIT_US);
-+	res = futex_wake(&(f[MAX_COUNT-1]), 1, FUTEX_PRIVATE_FLAG);
-+	if (res != 1) {
-+		ksft_test_result_fail("Failed to wake thread res=%d\n", res);
-+		ksft_exit_fail();
-+	}
-+
-+	pthread_join(waiter, NULL);
-+	ksft_test_result_pass("%s succeed\n", __func__);
-+}
-+
-+int main(int argc, char *argv[])
-+{
-+	int c;
-+
-+	while ((c = getopt(argc, argv, "cht:v:")) != -1) {
-+		switch (c) {
-+		case 'c':
-+			log_color(1);
-+			break;
-+		case 'h':
-+			usage(basename(argv[0]));
-+			exit(0);
-+		case 'v':
-+			log_verbosity(atoi(optarg));
-+			break;
-+		default:
-+			usage(basename(argv[0]));
-+			exit(1);
-+		}
-+	}
-+
-+	progname = basename(argv[0]);
-+
-+	ksft_print_header();
-+	ksft_set_plan(2);
-+
-+	test_count_overflow();
-+
-+#ifdef __ILP32__
-+	// if it's a 32x binary, there's no futex to wakeup
-+	ksft_test_result_skip("futex_wait_multiple not supported at x32\n");
-+#else
-+	test_fwb_wakeup();
-+#endif /* __ILP32__ */
-+
-+	ksft_print_cnts();
-+	return ret;
-+}
-diff --git a/tools/testing/selftests/futex/functional/run.sh b/tools/testing/selftests/futex/functional/run.sh
-index 1acb6ace1..a8be94f28 100755
---- a/tools/testing/selftests/futex/functional/run.sh
-+++ b/tools/testing/selftests/futex/functional/run.sh
-@@ -73,3 +73,6 @@ echo
- echo
- ./futex_wait_uninitialized_heap $COLOR
- ./futex_wait_private_mapped_file $COLOR
-+
-+echo
-+./futex_wait_multiple $COLOR
--- 
-2.27.0.rc2
-
diff --git a/disabled/0001-gcctunes-4.18-merge-graysky-s-patchset.patch b/disabled/0001-gcctunes-4.18-merge-graysky-s-patchset.patch
deleted file mode 100644
index 1ebb108..0000000
--- a/disabled/0001-gcctunes-4.18-merge-graysky-s-patchset.patch
+++ /dev/null
@@ -1,528 +0,0 @@
-From 2fd89b906088beac499b95ae43a081b9450e5195 Mon Sep 17 00:00:00 2001
-From: Oleksandr Natalenko <oleksandr@natalenko.name>
-Date: Sat, 2 Jun 2018 12:47:40 +0200
-Subject: [PATCH] gcctunes-4.18: merge graysky's patchset
-
-Signed-off-by: Oleksandr Natalenko <oleksandr@natalenko.name>
----
- arch/x86/Kconfig.cpu          | 249 ++++++++++++++++++++++++++++++----
- arch/x86/Makefile             |  39 +++++-
- arch/x86/Makefile_32.cpu      |  26 +++-
- arch/x86/include/asm/module.h |  44 ++++++
- 4 files changed, 323 insertions(+), 35 deletions(-)
-
-diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
-index 638411f22267..160924412d6a 100644
---- a/arch/x86/Kconfig.cpu
-+++ b/arch/x86/Kconfig.cpu
-@@ -116,6 +116,7 @@ config MPENTIUMM
- config MPENTIUM4
- 	bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
- 	depends on X86_32
-+	select X86_P6_NOP
- 	---help---
- 	  Select this for Intel Pentium 4 chips.  This includes the
- 	  Pentium 4, Pentium D, P4-based Celeron and Xeon, and
-@@ -148,9 +149,8 @@ config MPENTIUM4
- 		-Paxville
- 		-Dempsey
- 
--
- config MK6
--	bool "K6/K6-II/K6-III"
-+	bool "AMD K6/K6-II/K6-III"
- 	depends on X86_32
- 	---help---
- 	  Select this for an AMD K6-family processor.  Enables use of
-@@ -158,7 +158,7 @@ config MK6
- 	  flags to GCC.
- 
- config MK7
--	bool "Athlon/Duron/K7"
-+	bool "AMD Athlon/Duron/K7"
- 	depends on X86_32
- 	---help---
- 	  Select this for an AMD Athlon K7-family processor.  Enables use of
-@@ -166,12 +166,83 @@ config MK7
- 	  flags to GCC.
- 
- config MK8
--	bool "Opteron/Athlon64/Hammer/K8"
-+	bool "AMD Opteron/Athlon64/Hammer/K8"
- 	---help---
- 	  Select this for an AMD Opteron or Athlon64 Hammer-family processor.
- 	  Enables use of some extended instructions, and passes appropriate
- 	  optimization flags to GCC.
- 
-+config MK8SSE3
-+	bool "AMD Opteron/Athlon64/Hammer/K8 with SSE3"
-+	---help---
-+	  Select this for improved AMD Opteron or Athlon64 Hammer-family processors.
-+	  Enables use of some extended instructions, and passes appropriate
-+	  optimization flags to GCC.
-+
-+config MK10
-+	bool "AMD 61xx/7x50/PhenomX3/X4/II/K10"
-+	---help---
-+	  Select this for an AMD 61xx Eight-Core Magny-Cours, Athlon X2 7x50,
-+		Phenom X3/X4/II, Athlon II X2/X3/X4, or Turion II-family processor.
-+	  Enables use of some extended instructions, and passes appropriate
-+	  optimization flags to GCC.
-+
-+config MBARCELONA
-+	bool "AMD Barcelona"
-+	---help---
-+	  Select this for AMD Family 10h Barcelona processors.
-+
-+	  Enables -march=barcelona
-+
-+config MBOBCAT
-+	bool "AMD Bobcat"
-+	---help---
-+	  Select this for AMD Family 14h Bobcat processors.
-+
-+	  Enables -march=btver1
-+
-+config MJAGUAR
-+	bool "AMD Jaguar"
-+	---help---
-+	  Select this for AMD Family 16h Jaguar processors.
-+
-+	  Enables -march=btver2
-+
-+config MBULLDOZER
-+	bool "AMD Bulldozer"
-+	---help---
-+	  Select this for AMD Family 15h Bulldozer processors.
-+
-+	  Enables -march=bdver1
-+
-+config MPILEDRIVER
-+	bool "AMD Piledriver"
-+	---help---
-+	  Select this for AMD Family 15h Piledriver processors.
-+
-+	  Enables -march=bdver2
-+
-+config MSTEAMROLLER
-+	bool "AMD Steamroller"
-+	---help---
-+	  Select this for AMD Family 15h Steamroller processors.
-+
-+	  Enables -march=bdver3
-+
-+config MEXCAVATOR
-+	bool "AMD Excavator"
-+	---help---
-+	  Select this for AMD Family 15h Excavator processors.
-+
-+	  Enables -march=bdver4
-+
-+config MZEN
-+	bool "AMD Zen"
-+	---help---
-+	  Select this for AMD Family 17h Zen processors.
-+
-+	  Enables -march=znver1
-+
- config MCRUSOE
- 	bool "Crusoe"
- 	depends on X86_32
-@@ -253,6 +324,7 @@ config MVIAC7
- 
- config MPSC
- 	bool "Intel P4 / older Netburst based Xeon"
-+	select X86_P6_NOP
- 	depends on X86_64
- 	---help---
- 	  Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
-@@ -262,8 +334,19 @@ config MPSC
- 	  using the cpu family field
- 	  in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
- 
-+config MATOM
-+	bool "Intel Atom"
-+	select X86_P6_NOP
-+	---help---
-+
-+	  Select this for the Intel Atom platform. Intel Atom CPUs have an
-+	  in-order pipelining architecture and thus can benefit from
-+	  accordingly optimized code. Use a recent GCC with specific Atom
-+	  support in order to fully benefit from selecting this option.
-+
- config MCORE2
--	bool "Core 2/newer Xeon"
-+	bool "Intel Core 2"
-+	select X86_P6_NOP
- 	---help---
- 
- 	  Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
-@@ -271,14 +354,106 @@ config MCORE2
- 	  family in /proc/cpuinfo. Newer ones have 6 and older ones 15
- 	  (not a typo)
- 
--config MATOM
--	bool "Intel Atom"
-+	  Enables -march=core2
-+
-+config MNEHALEM
-+	bool "Intel Nehalem"
-+	select X86_P6_NOP
- 	---help---
- 
--	  Select this for the Intel Atom platform. Intel Atom CPUs have an
--	  in-order pipelining architecture and thus can benefit from
--	  accordingly optimized code. Use a recent GCC with specific Atom
--	  support in order to fully benefit from selecting this option.
-+	  Select this for 1st Gen Core processors in the Nehalem family.
-+
-+	  Enables -march=nehalem
-+
-+config MWESTMERE
-+	bool "Intel Westmere"
-+	select X86_P6_NOP
-+	---help---
-+
-+	  Select this for the Intel Westmere formerly Nehalem-C family.
-+
-+	  Enables -march=westmere
-+
-+config MSILVERMONT
-+	bool "Intel Silvermont"
-+	select X86_P6_NOP
-+	---help---
-+
-+	  Select this for the Intel Silvermont platform.
-+
-+	  Enables -march=silvermont
-+
-+config MSANDYBRIDGE
-+	bool "Intel Sandy Bridge"
-+	select X86_P6_NOP
-+	---help---
-+
-+	  Select this for 2nd Gen Core processors in the Sandy Bridge family.
-+
-+	  Enables -march=sandybridge
-+
-+config MIVYBRIDGE
-+	bool "Intel Ivy Bridge"
-+	select X86_P6_NOP
-+	---help---
-+
-+	  Select this for 3rd Gen Core processors in the Ivy Bridge family.
-+
-+	  Enables -march=ivybridge
-+
-+config MHASWELL
-+	bool "Intel Haswell"
-+	select X86_P6_NOP
-+	---help---
-+
-+	  Select this for 4th Gen Core processors in the Haswell family.
-+
-+	  Enables -march=haswell
-+
-+config MBROADWELL
-+	bool "Intel Broadwell"
-+	select X86_P6_NOP
-+	---help---
-+
-+	  Select this for 5th Gen Core processors in the Broadwell family.
-+
-+	  Enables -march=broadwell
-+
-+config MSKYLAKE
-+	bool "Intel Skylake"
-+	select X86_P6_NOP
-+	---help---
-+
-+	  Select this for 6th Gen Core processors in the Skylake family.
-+
-+	  Enables -march=skylake
-+
-+config MSKYLAKEX
-+	bool "Intel Skylake X"
-+	select X86_P6_NOP
-+	---help---
-+
-+	  Select this for 6th Gen Core processors in the Skylake X family.
-+
-+	  Enables -march=skylake-avx512
-+
-+config MCANNONLAKE
-+	bool "Intel Cannon Lake"
-+	select X86_P6_NOP
-+	---help---
-+
-+	  Select this for 8th Gen Core processors.
-+
-+	  Enables -march=cannonlake
-+
-+config MICELAKE
-+	bool "Intel Ice Lake"
-+	select X86_P6_NOP
-+	---help---
-+
-+	  Select this for 8th Gen Core processors in the Ice Lake family.
-+
-+	  Enables -march=icelake
- 
- config GENERIC_CPU
- 	bool "Generic-x86-64"
-@@ -287,6 +462,19 @@ config GENERIC_CPU
- 	  Generic x86-64 CPU.
- 	  Run equally well on all x86-64 CPUs.
- 
-+config MNATIVE
-+ bool "Native optimizations autodetected by GCC"
-+ ---help---
-+
-+   GCC 4.2 and above support -march=native, which automatically detects
-+   the optimum settings to use based on your processor. -march=native
-+   also detects and applies additional settings beyond -march specific
-+   to your CPU, (eg. -msse4). Unless you have a specific reason not to
-+   (e.g. distcc cross-compiling), you should probably be using
-+   -march=native rather than anything listed below.
-+
-+   Enables -march=native
-+
- endchoice
- 
- config X86_GENERIC
-@@ -311,7 +499,7 @@ config X86_INTERNODE_CACHE_SHIFT
- config X86_L1_CACHE_SHIFT
- 	int
- 	default "7" if MPENTIUM4 || MPSC
--	default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
-+	default "6" if MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MJAGUAR || MPENTIUMM || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
- 	default "4" if MELAN || M486 || MGEODEGX1
- 	default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
- 
-@@ -329,35 +517,36 @@ config X86_ALIGNMENT_16
- 
- config X86_INTEL_USERCOPY
- 	def_bool y
--	depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
-+	depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK8SSE3 || MK7 || MEFFICEON || MCORE2 || MK10 || MBARCELONA || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE
- 
- config X86_USE_PPRO_CHECKSUM
- 	def_bool y
--	depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM
-+	depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MK10 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MATOM || MNATIVE
- 
- config X86_USE_3DNOW
- 	def_bool y
- 	depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
- 
--#
--# P6_NOPs are a relatively minor optimization that require a family >=
--# 6 processor, except that it is broken on certain VIA chips.
--# Furthermore, AMD chips prefer a totally different sequence of NOPs
--# (which work on all CPUs).  In addition, it looks like Virtual PC
--# does not understand them.
--#
--# As a result, disallow these if we're not compiling for X86_64 (these
--# NOPs do work on all x86-64 capable chips); the list of processors in
--# the right-hand clause are the cores that benefit from this optimization.
--#
- config X86_P6_NOP
--	def_bool y
--	depends on X86_64
--	depends on (MCORE2 || MPENTIUM4 || MPSC)
-+	default n
-+	bool "Support for P6_NOPs on Intel chips"
-+	depends on (MCORE2 || MPENTIUM4 || MPSC || MATOM || MNEHALEM || MWESTMERE || MSILVERMONT  || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE)
-+	---help---
-+	P6_NOPs are a relatively minor optimization that require a family >=
-+	6 processor, except that it is broken on certain VIA chips.
-+	Furthermore, AMD chips prefer a totally different sequence of NOPs
-+	(which work on all CPUs).  In addition, it looks like Virtual PC
-+	does not understand them.
-+
-+	As a result, disallow these if we're not compiling for X86_64 (these
-+	NOPs do work on all x86-64 capable chips); the list of processors in
-+	the right-hand clause are the cores that benefit from this optimization.
-+
-+	Say Y if you have Intel CPU newer than Pentium Pro, N otherwise.
- 
- config X86_TSC
- 	def_bool y
--	depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64
-+	depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MNATIVE || MATOM) || X86_64
- 
- config X86_CMPXCHG64
- 	def_bool y
-@@ -367,7 +556,7 @@ config X86_CMPXCHG64
- # generates cmov.
- config X86_CMOV
- 	def_bool y
--	depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX)
-+	depends on (MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MJAGUAR || MK7 || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MNATIVE || MATOM || MGEODE_LX)
- 
- config X86_MINIMUM_CPU_FAMILY
- 	int
-diff --git a/arch/x86/Makefile b/arch/x86/Makefile
-index a08e82856563..e1f48961d67b 100644
---- a/arch/x86/Makefile
-+++ b/arch/x86/Makefile
-@@ -123,13 +123,46 @@ else
- 	KBUILD_CFLAGS += $(call cc-option,-mskip-rax-setup)
- 
-         # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu)
-+        cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native)
-         cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8)
-+        cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-mtune=k8)
-+        cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10)
-+        cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona)
-+        cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1)
-+        cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2)
-+        cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1)
-+        cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2)
-+        cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3)
-+        cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4)
-+        cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1)
-         cflags-$(CONFIG_MPSC) += $(call cc-option,-march=nocona)
- 
-         cflags-$(CONFIG_MCORE2) += \
--                $(call cc-option,-march=core2,$(call cc-option,-mtune=generic))
--	cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom) \
--		$(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))
-+                $(call cc-option,-march=core2,$(call cc-option,-mtune=core2))
-+        cflags-$(CONFIG_MNEHALEM) += \
-+                $(call cc-option,-march=nehalem,$(call cc-option,-mtune=nehalem))
-+        cflags-$(CONFIG_MWESTMERE) += \
-+                $(call cc-option,-march=westmere,$(call cc-option,-mtune=westmere))
-+        cflags-$(CONFIG_MSILVERMONT) += \
-+                $(call cc-option,-march=silvermont,$(call cc-option,-mtune=silvermont))
-+        cflags-$(CONFIG_MSANDYBRIDGE) += \
-+                $(call cc-option,-march=sandybridge,$(call cc-option,-mtune=sandybridge))
-+        cflags-$(CONFIG_MIVYBRIDGE) += \
-+                $(call cc-option,-march=ivybridge,$(call cc-option,-mtune=ivybridge))
-+        cflags-$(CONFIG_MHASWELL) += \
-+                $(call cc-option,-march=haswell,$(call cc-option,-mtune=haswell))
-+        cflags-$(CONFIG_MBROADWELL) += \
-+                $(call cc-option,-march=broadwell,$(call cc-option,-mtune=broadwell))
-+        cflags-$(CONFIG_MSKYLAKE) += \
-+                $(call cc-option,-march=skylake,$(call cc-option,-mtune=skylake))
-+        cflags-$(CONFIG_MSKYLAKEX) += \
-+                $(call cc-option,-march=skylake-avx512,$(call cc-option,-mtune=skylake-avx512))
-+        cflags-$(CONFIG_MCANNONLAKE) += \
-+                $(call cc-option,-march=cannonlake,$(call cc-option,-mtune=cannonlake))
-+        cflags-$(CONFIG_MICELAKE) += \
-+                $(call cc-option,-march=icelake,$(call cc-option,-mtune=icelake))
-+        cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell) \
-+                $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic))
-         cflags-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=generic)
-         KBUILD_CFLAGS += $(cflags-y)
- 
-diff --git a/arch/x86/Makefile_32.cpu b/arch/x86/Makefile_32.cpu
-index 1f5faf8606b4..14a6d19995cc 100644
---- a/arch/x86/Makefile_32.cpu
-+++ b/arch/x86/Makefile_32.cpu
-@@ -23,7 +23,18 @@ cflags-$(CONFIG_MK6)		+= -march=k6
- # Please note, that patches that add -march=athlon-xp and friends are pointless.
- # They make zero difference whatsosever to performance at this time.
- cflags-$(CONFIG_MK7)		+= -march=athlon
-+cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native)
- cflags-$(CONFIG_MK8)		+= $(call cc-option,-march=k8,-march=athlon)
-+cflags-$(CONFIG_MK8SSE3)		+= $(call cc-option,-march=k8-sse3,-march=athlon)
-+cflags-$(CONFIG_MK10)	+= $(call cc-option,-march=amdfam10,-march=athlon)
-+cflags-$(CONFIG_MBARCELONA)	+= $(call cc-option,-march=barcelona,-march=athlon)
-+cflags-$(CONFIG_MBOBCAT)	+= $(call cc-option,-march=btver1,-march=athlon)
-+cflags-$(CONFIG_MJAGUAR)	+= $(call cc-option,-march=btver2,-march=athlon)
-+cflags-$(CONFIG_MBULLDOZER)	+= $(call cc-option,-march=bdver1,-march=athlon)
-+cflags-$(CONFIG_MPILEDRIVER)	+= $(call cc-option,-march=bdver2,-march=athlon)
-+cflags-$(CONFIG_MSTEAMROLLER)	+= $(call cc-option,-march=bdver3,-march=athlon)
-+cflags-$(CONFIG_MEXCAVATOR)	+= $(call cc-option,-march=bdver4,-march=athlon)
-+cflags-$(CONFIG_MZEN)	+= $(call cc-option,-march=znver1,-march=athlon)
- cflags-$(CONFIG_MCRUSOE)	+= -march=i686 -falign-functions=0 -falign-jumps=0 -falign-loops=0
- cflags-$(CONFIG_MEFFICEON)	+= -march=i686 $(call tune,pentium3) -falign-functions=0 -falign-jumps=0 -falign-loops=0
- cflags-$(CONFIG_MWINCHIPC6)	+= $(call cc-option,-march=winchip-c6,-march=i586)
-@@ -32,8 +43,19 @@ cflags-$(CONFIG_MCYRIXIII)	+= $(call cc-option,-march=c3,-march=i486) -falign-fu
- cflags-$(CONFIG_MVIAC3_2)	+= $(call cc-option,-march=c3-2,-march=i686)
- cflags-$(CONFIG_MVIAC7)		+= -march=i686
- cflags-$(CONFIG_MCORE2)		+= -march=i686 $(call tune,core2)
--cflags-$(CONFIG_MATOM)		+= $(call cc-option,-march=atom,$(call cc-option,-march=core2,-march=i686)) \
--	$(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))
-+cflags-$(CONFIG_MNEHALEM)	+= -march=i686 $(call tune,nehalem)
-+cflags-$(CONFIG_MWESTMERE)	+= -march=i686 $(call tune,westmere)
-+cflags-$(CONFIG_MSILVERMONT)	+= -march=i686 $(call tune,silvermont)
-+cflags-$(CONFIG_MSANDYBRIDGE)	+= -march=i686 $(call tune,sandybridge)
-+cflags-$(CONFIG_MIVYBRIDGE)	+= -march=i686 $(call tune,ivybridge)
-+cflags-$(CONFIG_MHASWELL)	+= -march=i686 $(call tune,haswell)
-+cflags-$(CONFIG_MBROADWELL)	+= -march=i686 $(call tune,broadwell)
-+cflags-$(CONFIG_MSKYLAKE)	+= -march=i686 $(call tune,skylake)
-+cflags-$(CONFIG_MSKYLAKEX)	+= -march=i686 $(call tune,skylake-avx512)
-+cflags-$(CONFIG_MCANNONLAKE)	+= -march=i686 $(call tune,cannonlake)
-+cflags-$(CONFIG_MICELAKE)	+= -march=i686 $(call tune,icelake)
-+cflags-$(CONFIG_MATOM)		+= $(call cc-option,-march=bonnell,$(call cc-option,-march=core2,-march=i686)) \
-+	$(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic))
- 
- # AMD Elan support
- cflags-$(CONFIG_MELAN)		+= -march=i486
-diff --git a/arch/x86/include/asm/module.h b/arch/x86/include/asm/module.h
-index 7948a17febb4..44b776297dc3 100644
---- a/arch/x86/include/asm/module.h
-+++ b/arch/x86/include/asm/module.h
-@@ -25,6 +25,30 @@ struct mod_arch_specific {
- #define MODULE_PROC_FAMILY "586MMX "
- #elif defined CONFIG_MCORE2
- #define MODULE_PROC_FAMILY "CORE2 "
-+#elif defined CONFIG_MNATIVE
-+#define MODULE_PROC_FAMILY "NATIVE "
-+#elif defined CONFIG_MNEHALEM
-+#define MODULE_PROC_FAMILY "NEHALEM "
-+#elif defined CONFIG_MWESTMERE
-+#define MODULE_PROC_FAMILY "WESTMERE "
-+#elif defined CONFIG_MSILVERMONT
-+#define MODULE_PROC_FAMILY "SILVERMONT "
-+#elif defined CONFIG_MSANDYBRIDGE
-+#define MODULE_PROC_FAMILY "SANDYBRIDGE "
-+#elif defined CONFIG_MIVYBRIDGE
-+#define MODULE_PROC_FAMILY "IVYBRIDGE "
-+#elif defined CONFIG_MHASWELL
-+#define MODULE_PROC_FAMILY "HASWELL "
-+#elif defined CONFIG_MBROADWELL
-+#define MODULE_PROC_FAMILY "BROADWELL "
-+#elif defined CONFIG_MSKYLAKE
-+#define MODULE_PROC_FAMILY "SKYLAKE "
-+#elif defined CONFIG_MSKYLAKEX
-+#define MODULE_PROC_FAMILY "SKYLAKEX "
-+#elif defined CONFIG_MCANNONLAKE
-+#define MODULE_PROC_FAMILY "CANNONLAKE "
-+#elif defined CONFIG_MICELAKE
-+#define MODULE_PROC_FAMILY "ICELAKE "
- #elif defined CONFIG_MATOM
- #define MODULE_PROC_FAMILY "ATOM "
- #elif defined CONFIG_M686
-@@ -43,6 +67,26 @@ struct mod_arch_specific {
- #define MODULE_PROC_FAMILY "K7 "
- #elif defined CONFIG_MK8
- #define MODULE_PROC_FAMILY "K8 "
-+#elif defined CONFIG_MK8SSE3
-+#define MODULE_PROC_FAMILY "K8SSE3 "
-+#elif defined CONFIG_MK10
-+#define MODULE_PROC_FAMILY "K10 "
-+#elif defined CONFIG_MBARCELONA
-+#define MODULE_PROC_FAMILY "BARCELONA "
-+#elif defined CONFIG_MBOBCAT
-+#define MODULE_PROC_FAMILY "BOBCAT "
-+#elif defined CONFIG_MBULLDOZER
-+#define MODULE_PROC_FAMILY "BULLDOZER "
-+#elif defined CONFIG_MPILEDRIVER
-+#define MODULE_PROC_FAMILY "PILEDRIVER "
-+#elif defined CONFIG_MSTEAMROLLER
-+#define MODULE_PROC_FAMILY "STEAMROLLER "
-+#elif defined CONFIG_MJAGUAR
-+#define MODULE_PROC_FAMILY "JAGUAR "
-+#elif defined CONFIG_MEXCAVATOR
-+#define MODULE_PROC_FAMILY "EXCAVATOR "
-+#elif defined CONFIG_MZEN
-+#define MODULE_PROC_FAMILY "ZEN "
- #elif defined CONFIG_MELAN
- #define MODULE_PROC_FAMILY "ELAN "
- #elif defined CONFIG_MCRUSOE
--- 
-2.18.0.547.g1d89318c4
-
diff --git a/disabled/0001-ipc-namespace-a-generic-per-ipc-pointer-and-peripc_o.patch b/disabled/0001-ipc-namespace-a-generic-per-ipc-pointer-and-peripc_o.patch
deleted file mode 100644
index a07dc3f..0000000
--- a/disabled/0001-ipc-namespace-a-generic-per-ipc-pointer-and-peripc_o.patch
+++ /dev/null
@@ -1,162 +0,0 @@
---- linux-4.11/include/linux/ipc_namespace.h.omv~	2017-05-04 18:43:48.771124069 +0200
-+++ linux-4.11/include/linux/ipc_namespace.h	2017-05-04 18:46:51.166983693 +0200
-@@ -60,9 +60,42 @@ struct ipc_namespace {
- 	struct user_namespace *user_ns;
- 	struct ucounts *ucounts;
- 
-+	/* allow others to piggyback on ipc_namesspaces */
-+	void *gen;			/* for others' private stuff */
-+
- 	struct ns_common ns;
- };
- 
-+/*
-+ * To access to the per-ipc generic data:
-+ * 1. (un)register ops with (un)register_peripc_operations()
-+ * 2. call ipc_assign_generic() to put private data on the ipc_namespace
-+ * 3. call ipc_access_generic() to access the private data
-+ * 4. do not change the pointer during the lifetime of ipc_namespace
-+ *
-+ * Modeled after generic net-ns pointers (commit dec827d), simplified for
-+ * a single user case for now:
-+ * 5. only one caller can register at a time
-+ * 6. caller must register at boot time (not to be used by modules)
-+ */
-+struct peripc_operations {
-+	int (*init)(struct ipc_namespace *);
-+	void (*exit)(struct ipc_namespace *);
-+};
-+
-+static inline void ipc_assign_generic(struct ipc_namespace *ns, void *data)
-+{
-+	ns->gen = data;
-+}
-+
-+static inline void *ipc_access_generic(struct ipc_namespace *ns)
-+{
-+	return ns->gen;
-+}
-+
-+extern int register_peripc_ops(struct peripc_operations *ops);
-+extern void unregister_peripc_ops(struct peripc_operations *ops);
-+
- extern struct ipc_namespace init_ipc_ns;
- extern spinlock_t mq_lock;
- 
---- linux-4.11/ipc/namespace.c.omv~	2017-05-04 18:47:05.891133643 +0200
-+++ linux-4.11/ipc/namespace.c	2017-05-04 18:49:07.837374749 +0200
-@@ -54,16 +54,22 @@ static struct ipc_namespace *create_ipc_
- 	ns->user_ns = get_user_ns(user_ns);
- 	ns->ucounts = ucounts;
- 
--	err = mq_init_ns(ns);
-+	err = init_peripc_ns(ns);
- 	if (err)
- 		goto fail_put;
- 
-+	err = mq_init_ns(ns);
-+	if (err)
-+		goto fail_peripc;
-+
- 	sem_init_ns(ns);
- 	msg_init_ns(ns);
- 	shm_init_ns(ns);
- 
- 	return ns;
- 
-+fail_peripc:
-+	exit_peripc_ns(ns);
- fail_put:
- 	put_user_ns(ns->user_ns);
- 	ns_free_inum(&ns->ns);
-@@ -119,6 +125,7 @@ static void free_ipc_ns(struct ipc_names
- 	sem_exit_ns(ns);
- 	msg_exit_ns(ns);
- 	shm_exit_ns(ns);
-+	exit_peripc_ns(ns);
- 
- 	dec_ipc_namespaces(ns->ucounts);
- 	put_user_ns(ns->user_ns);
---- linux-4.11/ipc/util.c.omv~	2017-05-04 18:49:23.571534790 +0200
-+++ linux-4.11/ipc/util.c	2017-05-04 18:50:14.493052612 +0200
-@@ -71,6 +71,68 @@ struct ipc_proc_iface {
- 	int (*show)(struct seq_file *, void *);
- };
- 
-+
-+/* allow others to piggyback on ipc_namespace */
-+static DEFINE_MUTEX(peripc_mutex);
-+static struct peripc_operations *peripc_ops;
-+
-+/*
-+ * peripc_operations is a simplified pernet_operations:
-+ * - allow only one entity to register
-+ * - allow to register only at boot time (no modules)
-+ * (these assumptions make the code much simpler)
-+ */
-+
-+static int init_peripc_count;
-+
-+/* caller hold peripc_mutex */
-+int init_peripc_ns(struct ipc_namespace *ns)
-+{
-+	int ret = 0;
-+
-+	if (peripc_ops && peripc_ops->init)
-+		ret = peripc_ops->init(ns);
-+	if (ret == 0)
-+		init_peripc_count++;
-+	return ret;
-+}
-+
-+/* caller hold peripc_mutex */
-+void exit_peripc_ns(struct ipc_namespace *ns)
-+{
-+	if (peripc_ops && peripc_ops->exit)
-+		peripc_ops->exit(ns);
-+	init_peripc_count--;
-+}
-+
-+int register_peripc_ops(struct peripc_operations *ops)
-+{
-+	int ret = -EBUSY;
-+
-+	mutex_lock(&peripc_mutex);
-+	/* must be first register, and only init ipc_namespace exists */
-+	if (peripc_ops == NULL && init_peripc_count == 0) {
-+		peripc_ops = ops;
-+		ret = init_peripc_ns(&init_ipc_ns);
-+		if (ret < 0)
-+			peripc_ops = NULL;
-+	}
-+	mutex_unlock(&peripc_mutex);
-+	return ret;
-+}
-+
-+void unregister_peripc_ops(struct peripc_operations *ops)
-+{
-+	mutex_lock(&peripc_mutex);
-+	/* sanity:  be same as registered, and no other ipc ns (beyond init) */
-+	BUG_ON(peripc_ops != ops);
-+	BUG_ON(init_peripc_count != 1);
-+	if (ops->exit)
-+		exit_peripc_ns(&init_ipc_ns);
-+	peripc_ops = NULL;
-+	mutex_unlock(&peripc_mutex);
-+}
-+
- /**
-  * ipc_init - initialise ipc subsystem
-  *
---- linux-4.11/ipc/util.h.omv~	2017-05-04 18:50:16.419072194 +0200
-+++ linux-4.11/ipc/util.h	2017-05-04 18:50:36.390275228 +0200
-@@ -47,6 +47,9 @@ static inline void msg_exit_ns(struct ip
- static inline void shm_exit_ns(struct ipc_namespace *ns) { }
- #endif
- 
-+int init_peripc_ns(struct ipc_namespace *ns);
-+void exit_peripc_ns(struct ipc_namespace *ns);
-+
- struct ipc_rcu {
- 	struct rcu_head rcu;
- 	atomic_t refcount;
diff --git a/disabled/0001-lib-Add-xxhash-module.patch b/disabled/0001-lib-Add-xxhash-module.patch
deleted file mode 100644
index 83f0992..0000000
--- a/disabled/0001-lib-Add-xxhash-module.patch
+++ /dev/null
@@ -1,862 +0,0 @@
-From a4b1ffb6e89bbccd519f9afa0910635668436105 Mon Sep 17 00:00:00 2001
-From: Nick Terrell <terrelln@fb.com>
-Date: Mon, 17 Jul 2017 17:07:18 -0700
-Subject: [PATCH v5 1/5] lib: Add xxhash module
-
-Adds xxhash kernel module with xxh32 and xxh64 hashes. xxhash is an
-extremely fast non-cryptographic hash algorithm for checksumming.
-The zstd compression and decompression modules added in the next patch
-require xxhash. I extracted it out from zstd since it is useful on its
-own. I copied the code from the upstream XXHash source repository and
-translated it into kernel style. I ran benchmarks and tests in the kernel
-and tests in userland.
-
-I benchmarked xxhash as a special character device. I ran in four modes,
-no-op, xxh32, xxh64, and crc32. The no-op mode simply copies the data to
-kernel space and ignores it. The xxh32, xxh64, and crc32 modes compute
-hashes on the copied data. I also ran it with four different buffer sizes.
-The benchmark file is located in the upstream zstd source repository under
-`contrib/linux-kernel/xxhash_test.c` [1].
-
-I ran the benchmarks on a Ubuntu 14.04 VM with 2 cores and 4 GiB of RAM.
-The VM is running on a MacBook Pro with a 3.1 GHz Intel Core i7 processor,
-16 GB of RAM, and a SSD. I benchmarked using the file `filesystem.squashfs`
-from `ubuntu-16.10-desktop-amd64.iso`, which is 1,536,217,088 B large.
-Run the following commands for the benchmark:
-
-    modprobe xxhash_test
-    mknod xxhash_test c 245 0
-    time cp filesystem.squashfs xxhash_test
-
-The time is reported by the time of the userland `cp`.
-The GB/s is computed with
-
-    1,536,217,008 B / time(buffer size, hash)
-
-which includes the time to copy from userland.
-The Normalized GB/s is computed with
-
-    1,536,217,088 B / (time(buffer size, hash) - time(buffer size, none)).
-
-
-| Buffer Size (B) | Hash  | Time (s) | GB/s | Adjusted GB/s |
-|-----------------|-------|----------|------|---------------|
-|            1024 | none  |    0.408 | 3.77 |             - |
-|            1024 | xxh32 |    0.649 | 2.37 |          6.37 |
-|            1024 | xxh64 |    0.542 | 2.83 |         11.46 |
-|            1024 | crc32 |    1.290 | 1.19 |          1.74 |
-|            4096 | none  |    0.380 | 4.04 |             - |
-|            4096 | xxh32 |    0.645 | 2.38 |          5.79 |
-|            4096 | xxh64 |    0.500 | 3.07 |         12.80 |
-|            4096 | crc32 |    1.168 | 1.32 |          1.95 |
-|            8192 | none  |    0.351 | 4.38 |             - |
-|            8192 | xxh32 |    0.614 | 2.50 |          5.84 |
-|            8192 | xxh64 |    0.464 | 3.31 |         13.60 |
-|            8192 | crc32 |    1.163 | 1.32 |          1.89 |
-|           16384 | none  |    0.346 | 4.43 |             - |
-|           16384 | xxh32 |    0.590 | 2.60 |          6.30 |
-|           16384 | xxh64 |    0.466 | 3.30 |         12.80 |
-|           16384 | crc32 |    1.183 | 1.30 |          1.84 |
-
-Tested in userland using the test-suite in the zstd repo under
-`contrib/linux-kernel/test/XXHashUserlandTest.cpp` [2] by mocking the
-kernel functions. A line in each branch of every function in `xxhash.c`
-was commented out to ensure that the test-suite fails. Additionally
-tested while testing zstd and with SMHasher [3].
-
-[1] https://phabricator.intern.facebook.com/P57526246
-[2] https://github.com/facebook/zstd/blob/dev/contrib/linux-kernel/test/XXHashUserlandTest.cpp
-[3] https://github.com/aappleby/smhasher
-
-zstd source repository: https://github.com/facebook/zstd
-XXHash source repository: https://github.com/cyan4973/xxhash
-
-Signed-off-by: Nick Terrell <terrelln@fb.com>
----
-v1 -> v2:
-- Make pointer in lib/xxhash.c:394 non-const
-
- include/linux/xxhash.h | 236 +++++++++++++++++++++++
- lib/Kconfig            |   3 +
- lib/Makefile           |   1 +
- lib/xxhash.c           | 500 +++++++++++++++++++++++++++++++++++++++++++++++++
- 4 files changed, 740 insertions(+)
- create mode 100644 include/linux/xxhash.h
- create mode 100644 lib/xxhash.c
-
-diff --git a/include/linux/xxhash.h b/include/linux/xxhash.h
-new file mode 100644
-index 0000000..9e1f42c
---- /dev/null
-+++ b/include/linux/xxhash.h
-@@ -0,0 +1,236 @@
-+/*
-+ * xxHash - Extremely Fast Hash algorithm
-+ * Copyright (C) 2012-2016, Yann Collet.
-+ *
-+ * BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php)
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are
-+ * met:
-+ *
-+ *   * Redistributions of source code must retain the above copyright
-+ *     notice, this list of conditions and the following disclaimer.
-+ *   * Redistributions in binary form must reproduce the above
-+ *     copyright notice, this list of conditions and the following disclaimer
-+ *     in the documentation and/or other materials provided with the
-+ *     distribution.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it under
-+ * the terms of the GNU General Public License version 2 as published by the
-+ * Free Software Foundation. This program is dual-licensed; you may select
-+ * either version 2 of the GNU General Public License ("GPL") or BSD license
-+ * ("BSD").
-+ *
-+ * You can contact the author at:
-+ * - xxHash homepage: http://cyan4973.github.io/xxHash/
-+ * - xxHash source repository: https://github.com/Cyan4973/xxHash
-+ */
-+
-+/*
-+ * Notice extracted from xxHash homepage:
-+ *
-+ * xxHash is an extremely fast Hash algorithm, running at RAM speed limits.
-+ * It also successfully passes all tests from the SMHasher suite.
-+ *
-+ * Comparison (single thread, Windows Seven 32 bits, using SMHasher on a Core 2
-+ * Duo @3GHz)
-+ *
-+ * Name            Speed       Q.Score   Author
-+ * xxHash          5.4 GB/s     10
-+ * CrapWow         3.2 GB/s      2       Andrew
-+ * MumurHash 3a    2.7 GB/s     10       Austin Appleby
-+ * SpookyHash      2.0 GB/s     10       Bob Jenkins
-+ * SBox            1.4 GB/s      9       Bret Mulvey
-+ * Lookup3         1.2 GB/s      9       Bob Jenkins
-+ * SuperFastHash   1.2 GB/s      1       Paul Hsieh
-+ * CityHash64      1.05 GB/s    10       Pike & Alakuijala
-+ * FNV             0.55 GB/s     5       Fowler, Noll, Vo
-+ * CRC32           0.43 GB/s     9
-+ * MD5-32          0.33 GB/s    10       Ronald L. Rivest
-+ * SHA1-32         0.28 GB/s    10
-+ *
-+ * Q.Score is a measure of quality of the hash function.
-+ * It depends on successfully passing SMHasher test set.
-+ * 10 is a perfect score.
-+ *
-+ * A 64-bits version, named xxh64 offers much better speed,
-+ * but for 64-bits applications only.
-+ * Name     Speed on 64 bits    Speed on 32 bits
-+ * xxh64       13.8 GB/s            1.9 GB/s
-+ * xxh32        6.8 GB/s            6.0 GB/s
-+ */
-+
-+#ifndef XXHASH_H
-+#define XXHASH_H
-+
-+#include <linux/types.h>
-+
-+/*-****************************
-+ * Simple Hash Functions
-+ *****************************/
-+
-+/**
-+ * xxh32() - calculate the 32-bit hash of the input with a given seed.
-+ *
-+ * @input:  The data to hash.
-+ * @length: The length of the data to hash.
-+ * @seed:   The seed can be used to alter the result predictably.
-+ *
-+ * Speed on Core 2 Duo @ 3 GHz (single thread, SMHasher benchmark) : 5.4 GB/s
-+ *
-+ * Return:  The 32-bit hash of the data.
-+ */
-+uint32_t xxh32(const void *input, size_t length, uint32_t seed);
-+
-+/**
-+ * xxh64() - calculate the 64-bit hash of the input with a given seed.
-+ *
-+ * @input:  The data to hash.
-+ * @length: The length of the data to hash.
-+ * @seed:   The seed can be used to alter the result predictably.
-+ *
-+ * This function runs 2x faster on 64-bit systems, but slower on 32-bit systems.
-+ *
-+ * Return:  The 64-bit hash of the data.
-+ */
-+uint64_t xxh64(const void *input, size_t length, uint64_t seed);
-+
-+/*-****************************
-+ * Streaming Hash Functions
-+ *****************************/
-+
-+/*
-+ * These definitions are only meant to allow allocation of XXH state
-+ * statically, on stack, or in a struct for example.
-+ * Do not use members directly.
-+ */
-+
-+/**
-+ * struct xxh32_state - private xxh32 state, do not use members directly
-+ */
-+struct xxh32_state {
-+	uint32_t total_len_32;
-+	uint32_t large_len;
-+	uint32_t v1;
-+	uint32_t v2;
-+	uint32_t v3;
-+	uint32_t v4;
-+	uint32_t mem32[4];
-+	uint32_t memsize;
-+};
-+
-+/**
-+ * struct xxh32_state - private xxh64 state, do not use members directly
-+ */
-+struct xxh64_state {
-+	uint64_t total_len;
-+	uint64_t v1;
-+	uint64_t v2;
-+	uint64_t v3;
-+	uint64_t v4;
-+	uint64_t mem64[4];
-+	uint32_t memsize;
-+};
-+
-+/**
-+ * xxh32_reset() - reset the xxh32 state to start a new hashing operation
-+ *
-+ * @state: The xxh32 state to reset.
-+ * @seed:  Initialize the hash state with this seed.
-+ *
-+ * Call this function on any xxh32_state to prepare for a new hashing operation.
-+ */
-+void xxh32_reset(struct xxh32_state *state, uint32_t seed);
-+
-+/**
-+ * xxh32_update() - hash the data given and update the xxh32 state
-+ *
-+ * @state:  The xxh32 state to update.
-+ * @input:  The data to hash.
-+ * @length: The length of the data to hash.
-+ *
-+ * After calling xxh32_reset() call xxh32_update() as many times as necessary.
-+ *
-+ * Return:  Zero on success, otherwise an error code.
-+ */
-+int xxh32_update(struct xxh32_state *state, const void *input, size_t length);
-+
-+/**
-+ * xxh32_digest() - produce the current xxh32 hash
-+ *
-+ * @state: Produce the current xxh32 hash of this state.
-+ *
-+ * A hash value can be produced at any time. It is still possible to continue
-+ * inserting input into the hash state after a call to xxh32_digest(), and
-+ * generate new hashes later on, by calling xxh32_digest() again.
-+ *
-+ * Return: The xxh32 hash stored in the state.
-+ */
-+uint32_t xxh32_digest(const struct xxh32_state *state);
-+
-+/**
-+ * xxh64_reset() - reset the xxh64 state to start a new hashing operation
-+ *
-+ * @state: The xxh64 state to reset.
-+ * @seed:  Initialize the hash state with this seed.
-+ */
-+void xxh64_reset(struct xxh64_state *state, uint64_t seed);
-+
-+/**
-+ * xxh64_update() - hash the data given and update the xxh64 state
-+ * @state:  The xxh64 state to update.
-+ * @input:  The data to hash.
-+ * @length: The length of the data to hash.
-+ *
-+ * After calling xxh64_reset() call xxh64_update() as many times as necessary.
-+ *
-+ * Return:  Zero on success, otherwise an error code.
-+ */
-+int xxh64_update(struct xxh64_state *state, const void *input, size_t length);
-+
-+/**
-+ * xxh64_digest() - produce the current xxh64 hash
-+ *
-+ * @state: Produce the current xxh64 hash of this state.
-+ *
-+ * A hash value can be produced at any time. It is still possible to continue
-+ * inserting input into the hash state after a call to xxh64_digest(), and
-+ * generate new hashes later on, by calling xxh64_digest() again.
-+ *
-+ * Return: The xxh64 hash stored in the state.
-+ */
-+uint64_t xxh64_digest(const struct xxh64_state *state);
-+
-+/*-**************************
-+ * Utils
-+ ***************************/
-+
-+/**
-+ * xxh32_copy_state() - copy the source state into the destination state
-+ *
-+ * @src: The source xxh32 state.
-+ * @dst: The destination xxh32 state.
-+ */
-+void xxh32_copy_state(struct xxh32_state *dst, const struct xxh32_state *src);
-+
-+/**
-+ * xxh64_copy_state() - copy the source state into the destination state
-+ *
-+ * @src: The source xxh64 state.
-+ * @dst: The destination xxh64 state.
-+ */
-+void xxh64_copy_state(struct xxh64_state *dst, const struct xxh64_state *src);
-+
-+#endif /* XXHASH_H */
-diff --git a/lib/Kconfig b/lib/Kconfig
-index 6762529..5e7541f 100644
---- a/lib/Kconfig
-+++ b/lib/Kconfig
-@@ -192,6 +192,9 @@ config CRC8
- 	  when they need to do cyclic redundancy check according CRC8
- 	  algorithm. Module will be called crc8.
-
-+config XXHASH
-+	tristate
-+
- config AUDIT_GENERIC
- 	bool
- 	depends on AUDIT && !AUDIT_ARCH
-diff --git a/lib/Makefile b/lib/Makefile
-index 40c1837..d06b68a 100644
---- a/lib/Makefile
-+++ b/lib/Makefile
-@@ -102,6 +102,7 @@ obj-$(CONFIG_CRC4)	+= crc4.o
- obj-$(CONFIG_CRC7)	+= crc7.o
- obj-$(CONFIG_LIBCRC32C)	+= libcrc32c.o
- obj-$(CONFIG_CRC8)	+= crc8.o
-+obj-$(CONFIG_XXHASH)	+= xxhash.o
- obj-$(CONFIG_GENERIC_ALLOCATOR) += genalloc.o
-
- obj-$(CONFIG_842_COMPRESS) += 842/
-diff --git a/lib/xxhash.c b/lib/xxhash.c
-new file mode 100644
-index 0000000..aa61e2a
---- /dev/null
-+++ b/lib/xxhash.c
-@@ -0,0 +1,500 @@
-+/*
-+ * xxHash - Extremely Fast Hash algorithm
-+ * Copyright (C) 2012-2016, Yann Collet.
-+ *
-+ * BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php)
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are
-+ * met:
-+ *
-+ *   * Redistributions of source code must retain the above copyright
-+ *     notice, this list of conditions and the following disclaimer.
-+ *   * Redistributions in binary form must reproduce the above
-+ *     copyright notice, this list of conditions and the following disclaimer
-+ *     in the documentation and/or other materials provided with the
-+ *     distribution.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it under
-+ * the terms of the GNU General Public License version 2 as published by the
-+ * Free Software Foundation. This program is dual-licensed; you may select
-+ * either version 2 of the GNU General Public License ("GPL") or BSD license
-+ * ("BSD").
-+ *
-+ * You can contact the author at:
-+ * - xxHash homepage: http://cyan4973.github.io/xxHash/
-+ * - xxHash source repository: https://github.com/Cyan4973/xxHash
-+ */
-+
-+#include <asm/unaligned.h>
-+#include <linux/errno.h>
-+#include <linux/compiler.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/string.h>
-+#include <linux/xxhash.h>
-+
-+/*-*************************************
-+ * Macros
-+ **************************************/
-+#define xxh_rotl32(x, r) ((x << r) | (x >> (32 - r)))
-+#define xxh_rotl64(x, r) ((x << r) | (x >> (64 - r)))
-+
-+#ifdef __LITTLE_ENDIAN
-+# define XXH_CPU_LITTLE_ENDIAN 1
-+#else
-+# define XXH_CPU_LITTLE_ENDIAN 0
-+#endif
-+
-+/*-*************************************
-+ * Constants
-+ **************************************/
-+static const uint32_t PRIME32_1 = 2654435761U;
-+static const uint32_t PRIME32_2 = 2246822519U;
-+static const uint32_t PRIME32_3 = 3266489917U;
-+static const uint32_t PRIME32_4 =  668265263U;
-+static const uint32_t PRIME32_5 =  374761393U;
-+
-+static const uint64_t PRIME64_1 = 11400714785074694791ULL;
-+static const uint64_t PRIME64_2 = 14029467366897019727ULL;
-+static const uint64_t PRIME64_3 =  1609587929392839161ULL;
-+static const uint64_t PRIME64_4 =  9650029242287828579ULL;
-+static const uint64_t PRIME64_5 =  2870177450012600261ULL;
-+
-+/*-**************************
-+ *  Utils
-+ ***************************/
-+void xxh32_copy_state(struct xxh32_state *dst, const struct xxh32_state *src)
-+{
-+	memcpy(dst, src, sizeof(*dst));
-+}
-+EXPORT_SYMBOL(xxh32_copy_state);
-+
-+void xxh64_copy_state(struct xxh64_state *dst, const struct xxh64_state *src)
-+{
-+	memcpy(dst, src, sizeof(*dst));
-+}
-+EXPORT_SYMBOL(xxh64_copy_state);
-+
-+/*-***************************
-+ * Simple Hash Functions
-+ ****************************/
-+static uint32_t xxh32_round(uint32_t seed, const uint32_t input)
-+{
-+	seed += input * PRIME32_2;
-+	seed = xxh_rotl32(seed, 13);
-+	seed *= PRIME32_1;
-+	return seed;
-+}
-+
-+uint32_t xxh32(const void *input, const size_t len, const uint32_t seed)
-+{
-+	const uint8_t *p = (const uint8_t *)input;
-+	const uint8_t *b_end = p + len;
-+	uint32_t h32;
-+
-+	if (len >= 16) {
-+		const uint8_t *const limit = b_end - 16;
-+		uint32_t v1 = seed + PRIME32_1 + PRIME32_2;
-+		uint32_t v2 = seed + PRIME32_2;
-+		uint32_t v3 = seed + 0;
-+		uint32_t v4 = seed - PRIME32_1;
-+
-+		do {
-+			v1 = xxh32_round(v1, get_unaligned_le32(p));
-+			p += 4;
-+			v2 = xxh32_round(v2, get_unaligned_le32(p));
-+			p += 4;
-+			v3 = xxh32_round(v3, get_unaligned_le32(p));
-+			p += 4;
-+			v4 = xxh32_round(v4, get_unaligned_le32(p));
-+			p += 4;
-+		} while (p <= limit);
-+
-+		h32 = xxh_rotl32(v1, 1) + xxh_rotl32(v2, 7) +
-+			xxh_rotl32(v3, 12) + xxh_rotl32(v4, 18);
-+	} else {
-+		h32 = seed + PRIME32_5;
-+	}
-+
-+	h32 += (uint32_t)len;
-+
-+	while (p + 4 <= b_end) {
-+		h32 += get_unaligned_le32(p) * PRIME32_3;
-+		h32 = xxh_rotl32(h32, 17) * PRIME32_4;
-+		p += 4;
-+	}
-+
-+	while (p < b_end) {
-+		h32 += (*p) * PRIME32_5;
-+		h32 = xxh_rotl32(h32, 11) * PRIME32_1;
-+		p++;
-+	}
-+
-+	h32 ^= h32 >> 15;
-+	h32 *= PRIME32_2;
-+	h32 ^= h32 >> 13;
-+	h32 *= PRIME32_3;
-+	h32 ^= h32 >> 16;
-+
-+	return h32;
-+}
-+EXPORT_SYMBOL(xxh32);
-+
-+static uint64_t xxh64_round(uint64_t acc, const uint64_t input)
-+{
-+	acc += input * PRIME64_2;
-+	acc = xxh_rotl64(acc, 31);
-+	acc *= PRIME64_1;
-+	return acc;
-+}
-+
-+static uint64_t xxh64_merge_round(uint64_t acc, uint64_t val)
-+{
-+	val = xxh64_round(0, val);
-+	acc ^= val;
-+	acc = acc * PRIME64_1 + PRIME64_4;
-+	return acc;
-+}
-+
-+uint64_t xxh64(const void *input, const size_t len, const uint64_t seed)
-+{
-+	const uint8_t *p = (const uint8_t *)input;
-+	const uint8_t *const b_end = p + len;
-+	uint64_t h64;
-+
-+	if (len >= 32) {
-+		const uint8_t *const limit = b_end - 32;
-+		uint64_t v1 = seed + PRIME64_1 + PRIME64_2;
-+		uint64_t v2 = seed + PRIME64_2;
-+		uint64_t v3 = seed + 0;
-+		uint64_t v4 = seed - PRIME64_1;
-+
-+		do {
-+			v1 = xxh64_round(v1, get_unaligned_le64(p));
-+			p += 8;
-+			v2 = xxh64_round(v2, get_unaligned_le64(p));
-+			p += 8;
-+			v3 = xxh64_round(v3, get_unaligned_le64(p));
-+			p += 8;
-+			v4 = xxh64_round(v4, get_unaligned_le64(p));
-+			p += 8;
-+		} while (p <= limit);
-+
-+		h64 = xxh_rotl64(v1, 1) + xxh_rotl64(v2, 7) +
-+			xxh_rotl64(v3, 12) + xxh_rotl64(v4, 18);
-+		h64 = xxh64_merge_round(h64, v1);
-+		h64 = xxh64_merge_round(h64, v2);
-+		h64 = xxh64_merge_round(h64, v3);
-+		h64 = xxh64_merge_round(h64, v4);
-+
-+	} else {
-+		h64  = seed + PRIME64_5;
-+	}
-+
-+	h64 += (uint64_t)len;
-+
-+	while (p + 8 <= b_end) {
-+		const uint64_t k1 = xxh64_round(0, get_unaligned_le64(p));
-+
-+		h64 ^= k1;
-+		h64 = xxh_rotl64(h64, 27) * PRIME64_1 + PRIME64_4;
-+		p += 8;
-+	}
-+
-+	if (p + 4 <= b_end) {
-+		h64 ^= (uint64_t)(get_unaligned_le32(p)) * PRIME64_1;
-+		h64 = xxh_rotl64(h64, 23) * PRIME64_2 + PRIME64_3;
-+		p += 4;
-+	}
-+
-+	while (p < b_end) {
-+		h64 ^= (*p) * PRIME64_5;
-+		h64 = xxh_rotl64(h64, 11) * PRIME64_1;
-+		p++;
-+	}
-+
-+	h64 ^= h64 >> 33;
-+	h64 *= PRIME64_2;
-+	h64 ^= h64 >> 29;
-+	h64 *= PRIME64_3;
-+	h64 ^= h64 >> 32;
-+
-+	return h64;
-+}
-+EXPORT_SYMBOL(xxh64);
-+
-+/*-**************************************************
-+ * Advanced Hash Functions
-+ ***************************************************/
-+void xxh32_reset(struct xxh32_state *statePtr, const uint32_t seed)
-+{
-+	/* use a local state for memcpy() to avoid strict-aliasing warnings */
-+	struct xxh32_state state;
-+
-+	memset(&state, 0, sizeof(state));
-+	state.v1 = seed + PRIME32_1 + PRIME32_2;
-+	state.v2 = seed + PRIME32_2;
-+	state.v3 = seed + 0;
-+	state.v4 = seed - PRIME32_1;
-+	memcpy(statePtr, &state, sizeof(state));
-+}
-+EXPORT_SYMBOL(xxh32_reset);
-+
-+void xxh64_reset(struct xxh64_state *statePtr, const uint64_t seed)
-+{
-+	/* use a local state for memcpy() to avoid strict-aliasing warnings */
-+	struct xxh64_state state;
-+
-+	memset(&state, 0, sizeof(state));
-+	state.v1 = seed + PRIME64_1 + PRIME64_2;
-+	state.v2 = seed + PRIME64_2;
-+	state.v3 = seed + 0;
-+	state.v4 = seed - PRIME64_1;
-+	memcpy(statePtr, &state, sizeof(state));
-+}
-+EXPORT_SYMBOL(xxh64_reset);
-+
-+int xxh32_update(struct xxh32_state *state, const void *input, const size_t len)
-+{
-+	const uint8_t *p = (const uint8_t *)input;
-+	const uint8_t *const b_end = p + len;
-+
-+	if (input == NULL)
-+		return -EINVAL;
-+
-+	state->total_len_32 += (uint32_t)len;
-+	state->large_len |= (len >= 16) | (state->total_len_32 >= 16);
-+
-+	if (state->memsize + len < 16) { /* fill in tmp buffer */
-+		memcpy((uint8_t *)(state->mem32) + state->memsize, input, len);
-+		state->memsize += (uint32_t)len;
-+		return 0;
-+	}
-+
-+	if (state->memsize) { /* some data left from previous update */
-+		const uint32_t *p32 = state->mem32;
-+
-+		memcpy((uint8_t *)(state->mem32) + state->memsize, input,
-+			16 - state->memsize);
-+
-+		state->v1 = xxh32_round(state->v1, get_unaligned_le32(p32));
-+		p32++;
-+		state->v2 = xxh32_round(state->v2, get_unaligned_le32(p32));
-+		p32++;
-+		state->v3 = xxh32_round(state->v3, get_unaligned_le32(p32));
-+		p32++;
-+		state->v4 = xxh32_round(state->v4, get_unaligned_le32(p32));
-+		p32++;
-+
-+		p += 16-state->memsize;
-+		state->memsize = 0;
-+	}
-+
-+	if (p <= b_end - 16) {
-+		const uint8_t *const limit = b_end - 16;
-+		uint32_t v1 = state->v1;
-+		uint32_t v2 = state->v2;
-+		uint32_t v3 = state->v3;
-+		uint32_t v4 = state->v4;
-+
-+		do {
-+			v1 = xxh32_round(v1, get_unaligned_le32(p));
-+			p += 4;
-+			v2 = xxh32_round(v2, get_unaligned_le32(p));
-+			p += 4;
-+			v3 = xxh32_round(v3, get_unaligned_le32(p));
-+			p += 4;
-+			v4 = xxh32_round(v4, get_unaligned_le32(p));
-+			p += 4;
-+		} while (p <= limit);
-+
-+		state->v1 = v1;
-+		state->v2 = v2;
-+		state->v3 = v3;
-+		state->v4 = v4;
-+	}
-+
-+	if (p < b_end) {
-+		memcpy(state->mem32, p, (size_t)(b_end-p));
-+		state->memsize = (uint32_t)(b_end-p);
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(xxh32_update);
-+
-+uint32_t xxh32_digest(const struct xxh32_state *state)
-+{
-+	const uint8_t *p = (const uint8_t *)state->mem32;
-+	const uint8_t *const b_end = (const uint8_t *)(state->mem32) +
-+		state->memsize;
-+	uint32_t h32;
-+
-+	if (state->large_len) {
-+		h32 = xxh_rotl32(state->v1, 1) + xxh_rotl32(state->v2, 7) +
-+			xxh_rotl32(state->v3, 12) + xxh_rotl32(state->v4, 18);
-+	} else {
-+		h32 = state->v3 /* == seed */ + PRIME32_5;
-+	}
-+
-+	h32 += state->total_len_32;
-+
-+	while (p + 4 <= b_end) {
-+		h32 += get_unaligned_le32(p) * PRIME32_3;
-+		h32 = xxh_rotl32(h32, 17) * PRIME32_4;
-+		p += 4;
-+	}
-+
-+	while (p < b_end) {
-+		h32 += (*p) * PRIME32_5;
-+		h32 = xxh_rotl32(h32, 11) * PRIME32_1;
-+		p++;
-+	}
-+
-+	h32 ^= h32 >> 15;
-+	h32 *= PRIME32_2;
-+	h32 ^= h32 >> 13;
-+	h32 *= PRIME32_3;
-+	h32 ^= h32 >> 16;
-+
-+	return h32;
-+}
-+EXPORT_SYMBOL(xxh32_digest);
-+
-+int xxh64_update(struct xxh64_state *state, const void *input, const size_t len)
-+{
-+	const uint8_t *p = (const uint8_t *)input;
-+	const uint8_t *const b_end = p + len;
-+
-+	if (input == NULL)
-+		return -EINVAL;
-+
-+	state->total_len += len;
-+
-+	if (state->memsize + len < 32) { /* fill in tmp buffer */
-+		memcpy(((uint8_t *)state->mem64) + state->memsize, input, len);
-+		state->memsize += (uint32_t)len;
-+		return 0;
-+	}
-+
-+	if (state->memsize) { /* tmp buffer is full */
-+		uint64_t *p64 = state->mem64;
-+
-+		memcpy(((uint8_t *)p64) + state->memsize, input,
-+			32 - state->memsize);
-+
-+		state->v1 = xxh64_round(state->v1, get_unaligned_le64(p64));
-+		p64++;
-+		state->v2 = xxh64_round(state->v2, get_unaligned_le64(p64));
-+		p64++;
-+		state->v3 = xxh64_round(state->v3, get_unaligned_le64(p64));
-+		p64++;
-+		state->v4 = xxh64_round(state->v4, get_unaligned_le64(p64));
-+
-+		p += 32 - state->memsize;
-+		state->memsize = 0;
-+	}
-+
-+	if (p + 32 <= b_end) {
-+		const uint8_t *const limit = b_end - 32;
-+		uint64_t v1 = state->v1;
-+		uint64_t v2 = state->v2;
-+		uint64_t v3 = state->v3;
-+		uint64_t v4 = state->v4;
-+
-+		do {
-+			v1 = xxh64_round(v1, get_unaligned_le64(p));
-+			p += 8;
-+			v2 = xxh64_round(v2, get_unaligned_le64(p));
-+			p += 8;
-+			v3 = xxh64_round(v3, get_unaligned_le64(p));
-+			p += 8;
-+			v4 = xxh64_round(v4, get_unaligned_le64(p));
-+			p += 8;
-+		} while (p <= limit);
-+
-+		state->v1 = v1;
-+		state->v2 = v2;
-+		state->v3 = v3;
-+		state->v4 = v4;
-+	}
-+
-+	if (p < b_end) {
-+		memcpy(state->mem64, p, (size_t)(b_end-p));
-+		state->memsize = (uint32_t)(b_end - p);
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(xxh64_update);
-+
-+uint64_t xxh64_digest(const struct xxh64_state *state)
-+{
-+	const uint8_t *p = (const uint8_t *)state->mem64;
-+	const uint8_t *const b_end = (const uint8_t *)state->mem64 +
-+		state->memsize;
-+	uint64_t h64;
-+
-+	if (state->total_len >= 32) {
-+		const uint64_t v1 = state->v1;
-+		const uint64_t v2 = state->v2;
-+		const uint64_t v3 = state->v3;
-+		const uint64_t v4 = state->v4;
-+
-+		h64 = xxh_rotl64(v1, 1) + xxh_rotl64(v2, 7) +
-+			xxh_rotl64(v3, 12) + xxh_rotl64(v4, 18);
-+		h64 = xxh64_merge_round(h64, v1);
-+		h64 = xxh64_merge_round(h64, v2);
-+		h64 = xxh64_merge_round(h64, v3);
-+		h64 = xxh64_merge_round(h64, v4);
-+	} else {
-+		h64  = state->v3 + PRIME64_5;
-+	}
-+
-+	h64 += (uint64_t)state->total_len;
-+
-+	while (p + 8 <= b_end) {
-+		const uint64_t k1 = xxh64_round(0, get_unaligned_le64(p));
-+
-+		h64 ^= k1;
-+		h64 = xxh_rotl64(h64, 27) * PRIME64_1 + PRIME64_4;
-+		p += 8;
-+	}
-+
-+	if (p + 4 <= b_end) {
-+		h64 ^= (uint64_t)(get_unaligned_le32(p)) * PRIME64_1;
-+		h64 = xxh_rotl64(h64, 23) * PRIME64_2 + PRIME64_3;
-+		p += 4;
-+	}
-+
-+	while (p < b_end) {
-+		h64 ^= (*p) * PRIME64_5;
-+		h64 = xxh_rotl64(h64, 11) * PRIME64_1;
-+		p++;
-+	}
-+
-+	h64 ^= h64 >> 33;
-+	h64 *= PRIME64_2;
-+	h64 ^= h64 >> 29;
-+	h64 *= PRIME64_3;
-+	h64 ^= h64 >> 32;
-+
-+	return h64;
-+}
-+EXPORT_SYMBOL(xxh64_digest);
-+
-+MODULE_LICENSE("Dual BSD/GPL");
-+MODULE_DESCRIPTION("xxHash");
---
-2.9.3
diff --git a/disabled/0001-nfp-make-friends-with-O3.patch b/disabled/0001-nfp-make-friends-with-O3.patch
deleted file mode 100644
index 2239600..0000000
--- a/disabled/0001-nfp-make-friends-with-O3.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 0d3e093c4d4cb2e003814e790b5dc6877a844eaa Mon Sep 17 00:00:00 2001
-From: Oleksandr Natalenko <oleksandr@natalenko.name>
-Date: Tue, 7 May 2019 07:07:05 +0200
-Subject: [PATCH] nfp: make friends with -O3
-
-Signed-off-by: Oleksandr Natalenko <oleksandr@natalenko.name>
----
- drivers/net/ethernet/netronome/nfp/bpf/jit.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/net/ethernet/netronome/nfp/bpf/jit.c b/drivers/net/ethernet/netronome/nfp/bpf/jit.c
-index f272247d1708..6c9665622a61 100644
---- a/drivers/net/ethernet/netronome/nfp/bpf/jit.c
-+++ b/drivers/net/ethernet/netronome/nfp/bpf/jit.c
-@@ -328,7 +328,7 @@ __emit_shf(struct nfp_prog *nfp_prog, u16 dst, enum alu_dst_ab dst_ab,
- 		return;
- 	}
- 
--	if (sc == SHF_SC_L_SHF)
-+	if (sc == SHF_SC_L_SHF && shift)
- 		shift = 32 - shift;
- 
- 	insn = OP_SHF_BASE |
--- 
-2.21.0.777.g83232e3864
-
diff --git a/disabled/0007-irqchip-GICv3-ITS-Refator-ITS-dt-init-code-to-prepar.patch b/disabled/0007-irqchip-GICv3-ITS-Refator-ITS-dt-init-code-to-prepar.patch
deleted file mode 100644
index dab7750..0000000
--- a/disabled/0007-irqchip-GICv3-ITS-Refator-ITS-dt-init-code-to-prepar.patch
+++ /dev/null
@@ -1,249 +0,0 @@
-From b91b2762b6c86bff0cefe6168f7a4ae948dded32 Mon Sep 17 00:00:00 2001
-From: Tomasz Nowicki <tn@semihalf.com>
-Date: Tue, 19 Jan 2016 13:50:20 +0100
-Subject: [PATCH 07/26] irqchip, GICv3, ITS: Refator ITS dt init code to
- prepare for ACPI.
-
-Similarly to GICv3 core, we need to extract common code before adding
-ACPI support. No functional changes.
-
-Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
-Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
----
- drivers/irqchip/irq-gic-v3-its.c   | 82 +++++++++++++++++++++++---------------
- drivers/irqchip/irq-gic-v3.c       |  6 +--
- include/linux/irqchip/arm-gic-v3.h |  2 +-
- 3 files changed, 52 insertions(+), 38 deletions(-)
-
-diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
-index 0e8dfac..81c3179 100644
---- a/drivers/irqchip/irq-gic-v3-its.c
-+++ b/drivers/irqchip/irq-gic-v3-its.c
-@@ -813,7 +813,7 @@ static void its_free_tables(struct its_node *its)
- 	}
- }
- 
--static int its_alloc_tables(const char *node_name, struct its_node *its)
-+static int its_alloc_tables(struct its_node *its)
- {
- 	int err;
- 	int i;
-@@ -868,8 +868,8 @@ static int its_alloc_tables(const char *node_name, struct its_node *its)
- 				    order);
- 			if (order >= MAX_ORDER) {
- 				order = MAX_ORDER - 1;
--				pr_warn("%s: Device Table too large, reduce its page order to %u\n",
--					node_name, order);
-+				pr_warn("ITS@0x%lx: Device Table too large, reduce its page order to %u\n",
-+					its->phys_base, order);
- 			}
- 		}
- 
-@@ -879,8 +879,8 @@ retry_alloc_baser:
- 		if (alloc_pages > GITS_BASER_PAGES_MAX) {
- 			alloc_pages = GITS_BASER_PAGES_MAX;
- 			order = get_order(GITS_BASER_PAGES_MAX * psz);
--			pr_warn("%s: Device Table too large, reduce its page order to %u (%u pages)\n",
--				node_name, order, alloc_pages);
-+			pr_warn("ITS@0x%lx: Device Table too large, reduce its page order to %u (%u pages)\n",
-+				its->phys_base, order, alloc_pages);
- 		}
- 
- 		base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
-@@ -952,8 +952,8 @@ retry_baser:
- 		}
- 
- 		if (val != tmp) {
--			pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n",
--			       node_name, i,
-+			pr_err("ITS@0x%lx: GITS_BASER%d doesn't stick: %lx %lx\n",
-+			       its->phys_base, i,
- 			       (unsigned long) val, (unsigned long) tmp);
- 			err = -ENXIO;
- 			goto out_free;
-@@ -1428,10 +1428,11 @@ static void its_enable_quirks(struct its_node *its)
- 	gic_enable_quirks(iidr, its_quirks, its);
- }
- 
--static int __init its_probe(struct device_node *node,
--			    struct irq_domain *parent)
-+static int __init its_probe_one(phys_addr_t phys_base, unsigned long size,
-+				struct irq_domain *parent,
-+				bool is_msi_controller,
-+				struct fwnode_handle *handler)
- {
--	struct resource res;
- 	struct its_node *its;
- 	void __iomem *its_base;
- 	struct irq_domain *inner_domain;
-@@ -1439,33 +1440,26 @@ static int __init its_probe(struct device_node *node,
- 	u64 baser, tmp;
- 	int err;
- 
--	err = of_address_to_resource(node, 0, &res);
--	if (err) {
--		pr_warn("%s: no regs?\n", node->full_name);
--		return -ENXIO;
--	}
--
--	its_base = ioremap(res.start, resource_size(&res));
-+	its_base = ioremap(phys_base, size);
- 	if (!its_base) {
--		pr_warn("%s: unable to map registers\n", node->full_name);
-+		pr_warn("Unable to map ITS registers\n");
- 		return -ENOMEM;
- 	}
- 
- 	val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
- 	if (val != 0x30 && val != 0x40) {
--		pr_warn("%s: no ITS detected, giving up\n", node->full_name);
-+		pr_warn("No ITS detected, giving up\n");
- 		err = -ENODEV;
- 		goto out_unmap;
- 	}
- 
- 	err = its_force_quiescent(its_base);
- 	if (err) {
--		pr_warn("%s: failed to quiesce, giving up\n",
--			node->full_name);
-+		pr_warn("Failed to quiesce, giving up\n");
- 		goto out_unmap;
- 	}
- 
--	pr_info("ITS: %s\n", node->full_name);
-+	pr_info("ITS@0x%lx\n", (long)phys_base);
- 
- 	its = kzalloc(sizeof(*its), GFP_KERNEL);
- 	if (!its) {
-@@ -1477,7 +1471,7 @@ static int __init its_probe(struct device_node *node,
- 	INIT_LIST_HEAD(&its->entry);
- 	INIT_LIST_HEAD(&its->its_device_list);
- 	its->base = its_base;
--	its->phys_base = res.start;
-+	its->phys_base = phys_base;
- 	its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
- 
- 	its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
-@@ -1489,7 +1483,7 @@ static int __init its_probe(struct device_node *node,
- 
- 	its_enable_quirks(its);
- 
--	err = its_alloc_tables(node->full_name, its);
-+	err = its_alloc_tables(its);
- 	if (err)
- 		goto out_free_cmd;
- 
-@@ -1525,7 +1519,7 @@ static int __init its_probe(struct device_node *node,
- 	writeq_relaxed(0, its->base + GITS_CWRITER);
- 	writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
- 
--	if (of_property_read_bool(node, "msi-controller")) {
-+	if (is_msi_controller) {
- 		struct msi_domain_info *info;
- 
- 		info = kzalloc(sizeof(*info), GFP_KERNEL);
-@@ -1534,7 +1528,8 @@ static int __init its_probe(struct device_node *node,
- 			goto out_free_tables;
- 		}
- 
--		inner_domain = irq_domain_add_tree(node, &its_domain_ops, its);
-+		inner_domain = irq_domain_create_tree(handler, &its_domain_ops,
-+						      its);
- 		if (!inner_domain) {
- 			err = -ENOMEM;
- 			kfree(info);
-@@ -1562,10 +1557,28 @@ out_free_its:
- 	kfree(its);
- out_unmap:
- 	iounmap(its_base);
--	pr_err("ITS: failed probing %s (%d)\n", node->full_name, err);
-+	pr_err("ITS@0x%lx: failed probing (%d)\n", (long)phys_base, err);
- 	return err;
- }
- 
-+static int __init
-+its_of_probe(struct device_node *node, struct irq_domain *parent)
-+{
-+	struct resource res;
-+	bool is_msi_controller = false;
-+
-+	if (of_address_to_resource(node, 0, &res)) {
-+		pr_warn("%s: no regs?\n", node->full_name);
-+		return -ENXIO;
-+	}
-+
-+	if (of_property_read_bool(node, "msi-controller"))
-+		is_msi_controller = true;
-+
-+	return its_probe_one(res.start, resource_size(&res), parent,
-+			    is_msi_controller, &node->fwnode);
-+}
-+
- static bool gic_rdists_supports_plpis(void)
- {
- 	return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
-@@ -1590,14 +1603,17 @@ static struct of_device_id its_device_id[] = {
- 	{},
- };
- 
--int __init its_init(struct device_node *node, struct rdists *rdists,
--	     struct irq_domain *parent_domain)
-+int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
-+		    struct irq_domain *parent_domain)
- {
--	struct device_node *np;
-+	struct device_node *np, *of_node;
- 
--	for (np = of_find_matching_node(node, its_device_id); np;
--	     np = of_find_matching_node(np, its_device_id)) {
--		its_probe(np, parent_domain);
-+	of_node = to_of_node(handle);
-+	if (of_node) {
-+		for (np = of_find_matching_node(of_node, its_device_id); np;
-+		     np = of_find_matching_node(np, its_device_id)) {
-+			its_of_probe(np, parent_domain);
-+		}
- 	}
- 
- 	if (list_empty(&its_nodes)) {
-diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
-index dd16a60..995b7251 100644
---- a/drivers/irqchip/irq-gic-v3.c
-+++ b/drivers/irqchip/irq-gic-v3.c
-@@ -832,7 +832,6 @@ static int __init gic_init_bases(void __iomem *dist_base,
- 				 u64 redist_stride,
- 				 struct fwnode_handle *handle)
- {
--	struct device_node *node;
- 	u32 typer;
- 	int gic_irqs;
- 	int err;
-@@ -872,10 +871,9 @@ static int __init gic_init_bases(void __iomem *dist_base,
- 
- 	set_handle_irq(gic_handle_irq);
- 
--	node = to_of_node(handle);
- 	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&
--	    node) /* Temp hack to prevent ITS init for ACPI */
--		its_init(node, &gic_data.rdists, gic_data.domain);
-+	    to_of_node(handle)) /* Temp hack to prevent ITS init for ACPI */
-+		its_init(handle, &gic_data.rdists, gic_data.domain);
- 
- 	gic_smp_init();
- 	gic_dist_init();
-diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
-index d5d798b..a40ed7d 100644
---- a/include/linux/irqchip/arm-gic-v3.h
-+++ b/include/linux/irqchip/arm-gic-v3.h
-@@ -332,7 +332,7 @@ struct rdists {
- struct irq_domain;
- struct device_node;
- int its_cpu_init(void);
--int its_init(struct device_node *node, struct rdists *rdists,
-+int its_init(struct fwnode_handle *handle, struct rdists *rdists,
- 	     struct irq_domain *domain);
- 
- static inline bool gic_enable_sre(void)
--- 
-2.7.2
-
diff --git a/disabled/0008-md-raid10-LLVMLinux-Remove-VLAIS-from-raid10-driver.patch b/disabled/0008-md-raid10-LLVMLinux-Remove-VLAIS-from-raid10-driver.patch
deleted file mode 100644
index f6d04c5..0000000
--- a/disabled/0008-md-raid10-LLVMLinux-Remove-VLAIS-from-raid10-driver.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 3e8d39cf8c7295e00c45d071f5aa02ca30bcd12b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= <bero@linaro.org>
-Date: Thu, 23 Feb 2017 00:26:19 +0100
-Subject: [PATCH 08/30] md, raid10, LLVMLinux: Remove VLAIS from raid10 driver
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Behan Webster <behanw@converseincode.com>
-Suggested-by: Arnd Bergmann <arnd@arndb.de>
-Cc: Arnd Bergmann <arnd@arndb.de>
-Forward-ported-by: Bernhard Rosenkränzer <bero@linaro.org>
-Signed-off-by: Bernhard Rosenkränzer <bero@linaro.org>
----
- drivers/md/raid10.c | 13 ++++++++-----
- 1 file changed, 8 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c
-index 6bc5c2a85160..5d3bda466795 100644
---- a/drivers/md/raid10.c
-+++ b/drivers/md/raid10.c
-@@ -4655,15 +4655,16 @@ static int handle_reshape_read_error(struct mddev *mddev,
- 	/* Use sync reads to get the blocks from somewhere else */
- 	int sectors = r10_bio->sectors;
- 	struct r10conf *conf = mddev->private;
--	struct {
--		struct r10bio r10_bio;
--		struct r10dev devs[conf->copies];
--	} on_stack;
--	struct r10bio *r10b = &on_stack.r10_bio;
-+	struct r10bio *r10b;
-+
- 	int slot = 0;
- 	int idx = 0;
- 	struct bio_vec *bvec = r10_bio->master_bio->bi_io_vec;
- 
-+	r10b = kmalloc(sizeof *r10b + conf->copies * sizeof(struct r10dev),
-+		       GFP_NOIO);
-+	if (!r10b)
-+		return -ENOMEM;
- 	r10b->sector = r10_bio->sector;
- 	__raid10_find_phys(&conf->prev, r10b);
- 
-@@ -4709,11 +4710,13 @@ static int handle_reshape_read_error(struct mddev *mddev,
- 			/* couldn't read this block, must give up */
- 			set_bit(MD_RECOVERY_INTR,
- 				&mddev->recovery);
-+			kfree(r10b);
- 			return -EIO;
- 		}
- 		sectors -= s;
- 		idx++;
- 	}
-+	kfree(r10b);
- 	return 0;
- }
- 
--- 
-2.11.0
-
diff --git a/disabled/0009-fs-nfs-LLVMLinux-Remove-VLAIS-from-nfs.patch b/disabled/0009-fs-nfs-LLVMLinux-Remove-VLAIS-from-nfs.patch
deleted file mode 100644
index 9c0bd71..0000000
--- a/disabled/0009-fs-nfs-LLVMLinux-Remove-VLAIS-from-nfs.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From 153e6af02a2e67b7c6eb6022d24aba65c8089fbd Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= <bero@linaro.org>
-Date: Thu, 23 Feb 2017 00:29:09 +0100
-Subject: [PATCH 09/30] fs, nfs, LLVMLinux: Remove VLAIS from nfs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Behan Webster <behanw@converseincode.com>
-Suggested-by: Arnd Bergmann <arnd@arndb.de>
-Cc: Arnd Bergmann <arnd@arndb.de>
-Forward-ported-by: Bernhard Rosenkränzer <bero@linaro.org>
-Signed-off-by: Bernhard Rosenkränzer <bero@linaro.org>
----
- fs/nfs/Kconfig               | 2 +-
- fs/nfs/objlayout/objio_osd.c | 5 +++--
- 2 files changed, 4 insertions(+), 3 deletions(-)
-
-diff --git a/fs/nfs/Kconfig b/fs/nfs/Kconfig
-index f31fd0dd92c6..e6ef7b3725db 100644
---- a/fs/nfs/Kconfig
-+++ b/fs/nfs/Kconfig
-@@ -125,7 +125,7 @@ config PNFS_BLOCK
- 
- config PNFS_OBJLAYOUT
- 	tristate
--	depends on NFS_V4_1 && SCSI_OSD_ULD
-+	depends on NFS_V4_1 && SCSI_OSD_ULD && BROKEN
- 	default NFS_V4
- 
- config PNFS_FLEXFILE_LAYOUT
-diff --git a/fs/nfs/objlayout/objio_osd.c b/fs/nfs/objlayout/objio_osd.c
-index 049c1b1f2932..5963c1c83c8c 100644
---- a/fs/nfs/objlayout/objio_osd.c
-+++ b/fs/nfs/objlayout/objio_osd.c
-@@ -301,10 +301,11 @@ objio_alloc_io_state(struct pnfs_layout_hdr *pnfs_layout_type, bool is_reading,
- 	int ret;
- 	struct __alloc_objio_state {
- 		struct objio_state objios;
--		struct pnfs_osd_ioerr ioerrs[objio_seg->oc.numdevs];
-+		struct pnfs_osd_ioerr ioerrs[];
- 	} *aos;
- 
--	aos = kzalloc(sizeof(*aos), gfp_flags);
-+	aos = kzalloc(sizeof(*aos) + objio_seg->oc.numdevs *
-+		      sizeof(struct pnfs_osd_ioerr), gfp_flags);
- 	if (unlikely(!aos))
- 		return -ENOMEM;
- 
--- 
-2.11.0
-
diff --git a/disabled/0009-irqchip-gicv3-its-Probe-ITS-in-the-ACPI-way.patch b/disabled/0009-irqchip-gicv3-its-Probe-ITS-in-the-ACPI-way.patch
deleted file mode 100644
index d6e4f20..0000000
--- a/disabled/0009-irqchip-gicv3-its-Probe-ITS-in-the-ACPI-way.patch
+++ /dev/null
@@ -1,115 +0,0 @@
-From e76fafe8cb5eaed86bd460e8b5ebe40ad3ed7c13 Mon Sep 17 00:00:00 2001
-From: Tomasz Nowicki <tn@semihalf.com>
-Date: Fri, 9 Oct 2015 13:29:22 +0200
-Subject: [PATCH 09/26] irqchip, gicv3, its: Probe ITS in the ACPI way.
-
-Since we prepared ITS for being initialized different that via DT,
-it is now possible to parse MADT and pass mandatory info to
-firmware-agnostic ITS init call.
-
-Note that we are using here IORT lib to keep track of allocated
-domain handler which will be used to build PCI MSI domain on top
-in the later patches.
-
-Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
-Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
----
- drivers/irqchip/irq-gic-v3-its.c | 57 +++++++++++++++++++++++++++++++++++++++-
- 1 file changed, 56 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
-index 81c3179..155fa24 100644
---- a/drivers/irqchip/irq-gic-v3-its.c
-+++ b/drivers/irqchip/irq-gic-v3-its.c
-@@ -15,10 +15,13 @@
-  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-  */
- 
-+#include <linux/acpi.h>
- #include <linux/bitmap.h>
- #include <linux/cpu.h>
- #include <linux/delay.h>
- #include <linux/interrupt.h>
-+#include <linux/irqdomain.h>
-+#include <linux/iort.h>
- #include <linux/log2.h>
- #include <linux/mm.h>
- #include <linux/msi.h>
-@@ -1276,6 +1279,11 @@ static int its_irq_gic_domain_alloc(struct irq_domain *domain,
- 		fwspec.param[0] = GIC_IRQ_TYPE_LPI;
- 		fwspec.param[1] = hwirq;
- 		fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
-+	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {
-+		fwspec.fwnode = domain->parent->fwnode;
-+		fwspec.param_count = 2;
-+		fwspec.param[0] = hwirq;
-+		fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
- 	} else {
- 		return -EINVAL;
- 	}
-@@ -1598,6 +1606,52 @@ int its_cpu_init(void)
- 	return 0;
- }
- 
-+#ifdef CONFIG_ACPI
-+
-+#define ACPI_GICV3_ITS_MEM_SIZE (2 * SZ_64K)
-+
-+static struct irq_domain *its_parent __initdata;
-+
-+static int __init
-+gic_acpi_parse_madt_its(struct acpi_subtable_header *header,
-+			const unsigned long end)
-+{
-+	struct acpi_madt_generic_translator *its_entry;
-+	struct fwnode_handle *domain_handle;
-+	int err;
-+
-+	its_entry = (struct acpi_madt_generic_translator *)header;
-+	domain_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address);
-+	if (!domain_handle) {
-+		pr_err("Unable to allocate GICv2m domain token\n");
-+		return -ENOMEM;
-+	}
-+
-+	/* ITS works as msi controller in ACPI case */
-+	err = its_probe_one(its_entry->base_address, ACPI_GICV3_ITS_MEM_SIZE,
-+			    its_parent, true, domain_handle);
-+	if (err) {
-+		irq_domain_free_fwnode(domain_handle);
-+		return err;
-+	}
-+	iort_register_domain_token(its_entry->translation_id, domain_handle);
-+	return 0;
-+}
-+
-+void __init its_acpi_probe(struct irq_domain *parent_domain)
-+{
-+	int count;
-+
-+	its_parent = parent_domain;
-+	count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
-+				      gic_acpi_parse_madt_its, 0);
-+	if (count <= 0)
-+		pr_info("No valid GIC ITS entries exist\n");
-+}
-+#else
-+static inline void __init its_acpi_probe(struct irq_domain *parent_domain) { }
-+#endif
-+
- static struct of_device_id its_device_id[] = {
- 	{	.compatible	= "arm,gic-v3-its",	},
- 	{},
-@@ -1614,7 +1668,8 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
- 		     np = of_find_matching_node(np, its_device_id)) {
- 			its_of_probe(np, parent_domain);
- 		}
--	}
-+	} else
-+		its_acpi_probe(parent_domain);
- 
- 	if (list_empty(&its_nodes)) {
- 		pr_warn("ITS: No ITS available, not enabling LPIs\n");
--- 
-2.7.2
-
diff --git a/disabled/0010-net-wimax-i2400-LLVMLinux-Remove-VLAIS-from-wimax-i2.patch b/disabled/0010-net-wimax-i2400-LLVMLinux-Remove-VLAIS-from-wimax-i2.patch
deleted file mode 100644
index a47e049..0000000
--- a/disabled/0010-net-wimax-i2400-LLVMLinux-Remove-VLAIS-from-wimax-i2.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From cd38685e0a463234cc4a25ffe1cce639563779f8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= <bero@linaro.org>
-Date: Thu, 23 Feb 2017 00:30:32 +0100
-Subject: [PATCH 10/30] net, wimax, i2400, LLVMLinux: Remove VLAIS from wimax
- i2400m driver
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Convert Variable Length Array in Struct (VLAIS) to valid C by converting
-local struct definition to use a flexible array. The structure is only
-used to define a cast of a buffer so the size of the struct is not used
-to allocate storage.
-
-Signed-off-by: Behan Webster <behanw@converseincode.com>
-Signed-off-by: Mark Charebois <charlebm@gmail.com>
-Suggested-by: Arnd Bergmann <arnd@arndb.de>
-Cc: Arnd Bergmann <arnd@arndb.de>
-Forward-ported-by: Bernhard Rosenkränzer <bero@linaro.org>
-Signed-off-by: Bernhard Rosenkränzer <bero@linaro.org>
----
- drivers/net/wimax/i2400m/fw.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/net/wimax/i2400m/fw.c b/drivers/net/wimax/i2400m/fw.c
-index c9c711dcd0e6..a89b5685e68b 100644
---- a/drivers/net/wimax/i2400m/fw.c
-+++ b/drivers/net/wimax/i2400m/fw.c
-@@ -652,7 +652,7 @@ static int i2400m_download_chunk(struct i2400m *i2400m, const void *chunk,
- 	struct device *dev = i2400m_dev(i2400m);
- 	struct {
- 		struct i2400m_bootrom_header cmd;
--		u8 cmd_payload[chunk_len];
-+		u8 cmd_payload[];
- 	} __packed *buf;
- 	struct i2400m_bootrom_header ack;
- 
--- 
-2.11.0
-
diff --git a/disabled/0011-acpi-gicv3-its-Use-MADT-ITS-subtable-to-do-PCI-MSI-d.patch b/disabled/0011-acpi-gicv3-its-Use-MADT-ITS-subtable-to-do-PCI-MSI-d.patch
deleted file mode 100644
index 3dcb540..0000000
--- a/disabled/0011-acpi-gicv3-its-Use-MADT-ITS-subtable-to-do-PCI-MSI-d.patch
+++ /dev/null
@@ -1,122 +0,0 @@
-From 11530b6253c121e49ae7bdad6d356b6d7aca2cff Mon Sep 17 00:00:00 2001
-From: Tomasz Nowicki <tn@semihalf.com>
-Date: Fri, 9 Oct 2015 13:35:49 +0200
-Subject: [PATCH 11/26] acpi, gicv3, its: Use MADT ITS subtable to do PCI/MSI
- domain initialization.
-
-After refactoring DT code, we let ACPI to build ITS PCI MSI domain
-and do requester ID to device ID translation using IORT table.
-
-We have now full PCI MSI domain stack, thus we can enable ITS initialization
-from GICv3 core driver for ACPI scenario.
-
-Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
----
- drivers/irqchip/irq-gic-v3-its-pci-msi.c | 44 +++++++++++++++++++++++++++++++-
- drivers/irqchip/irq-gic-v3.c             |  3 +--
- drivers/pci/msi.c                        |  3 +++
- 3 files changed, 47 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/irqchip/irq-gic-v3-its-pci-msi.c b/drivers/irqchip/irq-gic-v3-its-pci-msi.c
-index 06165cb..7f0a958 100644
---- a/drivers/irqchip/irq-gic-v3-its-pci-msi.c
-+++ b/drivers/irqchip/irq-gic-v3-its-pci-msi.c
-@@ -15,6 +15,8 @@
-  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-  */
- 
-+#include <linux/acpi.h>
-+#include <linux/iort.h>
- #include <linux/msi.h>
- #include <linux/of.h>
- #include <linux/of_irq.h>
-@@ -143,10 +145,50 @@ static int __init its_pci_of_msi_init(void)
- 	return 0;
- }
- 
-+#ifdef CONFIG_ACPI
-+
-+static int __init
-+its_pci_msi_parse_madt(struct acpi_subtable_header *header,
-+		    const unsigned long end)
-+{
-+	struct acpi_madt_generic_translator *its_entry;
-+	struct fwnode_handle *domain_handle;
-+
-+	its_entry = (struct acpi_madt_generic_translator *)header;
-+	domain_handle = iort_find_its_domain_token(its_entry->translation_id);
-+	if (!domain_handle) {
-+		pr_err("ITS@0x%lx: Unable to locate ITS domain handle\n",
-+		       (long)its_entry->base_address);
-+		return 0;
-+	}
-+
-+	if (its_pci_msi_init_one(domain_handle))
-+		return 0;
-+
-+	pci_msi_register_fwnode_provider(&iort_find_pci_domain_token);
-+	pr_info("PCI/MSI: ITS@0x%lx domain created\n",
-+		(long)its_entry->base_address);
-+	return 0;
-+}
-+
-+static int __init its_pci_acpi_msi_init(void)
-+{
-+	acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
-+			      its_pci_msi_parse_madt, 0);
-+	return 0;
-+}
-+#else
-+inline static int __init its_pci_acpi_msi_init(void)
-+{
-+	return 0;
-+}
-+#endif
-+
- static int __init its_pci_msi_init(void)
- {
- 	its_pci_of_msi_init();
-+	its_pci_acpi_msi_init();
-+
- 	return 0;
- }
--
- early_initcall(its_pci_msi_init);
-diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
-index 995b7251..fee635e 100644
---- a/drivers/irqchip/irq-gic-v3.c
-+++ b/drivers/irqchip/irq-gic-v3.c
-@@ -871,8 +871,7 @@ static int __init gic_init_bases(void __iomem *dist_base,
- 
- 	set_handle_irq(gic_handle_irq);
- 
--	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&
--	    to_of_node(handle)) /* Temp hack to prevent ITS init for ACPI */
-+	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
- 		its_init(handle, &gic_data.rdists, gic_data.domain);
- 
- 	gic_smp_init();
-diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
-index a080f44..222d6d5 100644
---- a/drivers/pci/msi.c
-+++ b/drivers/pci/msi.c
-@@ -18,6 +18,7 @@
- #include <linux/smp.h>
- #include <linux/errno.h>
- #include <linux/io.h>
-+#include <linux/iort.h>
- #include <linux/slab.h>
- #include <linux/irqdomain.h>
- #include <linux/of_irq.h>
-@@ -1366,6 +1367,8 @@ u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
- 	of_node = irq_domain_get_of_node(domain);
- 	if (of_node)
- 		rid = of_msi_map_rid(&pdev->dev, of_node, rid);
-+	else
-+		iort_find_pci_id(pdev, rid, &rid);
- 
- 	return rid;
- }
--- 
-2.7.2
-
diff --git a/disabled/0021-pci-of-Move-the-PCI-I-O-space-management-to-PCI-core.patch b/disabled/0021-pci-of-Move-the-PCI-I-O-space-management-to-PCI-core.patch
deleted file mode 100644
index 1c011fa..0000000
--- a/disabled/0021-pci-of-Move-the-PCI-I-O-space-management-to-PCI-core.patch
+++ /dev/null
@@ -1,337 +0,0 @@
-From 66d1835d844bc3ff8f90f585d195f4911d036ddc Mon Sep 17 00:00:00 2001
-From: Tomasz Nowicki <tn@semihalf.com>
-Date: Sat, 23 Jan 2016 19:41:41 +0100
-Subject: [PATCH 21/26] pci, of: Move the PCI I/O space management to PCI core
- code.
-
-No functional changes in this patch.
-
-PCI I/O space mapping code does not depend on OF, therefore it can be
-moved to PCI core code. This way we will be able to use it
-e.g. in ACPI PCI code.
-
-Suggested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
-CC: Arnd Bergmann <arnd@arndb.de>
-CC: Liviu Dudau <Liviu.Dudau@arm.com>
-CC: Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>
----
- drivers/of/address.c       | 116 +--------------------------------------------
- drivers/pci/pci.c          | 115 ++++++++++++++++++++++++++++++++++++++++++++
- include/linux/of_address.h |   9 ----
- include/linux/pci.h        |   5 ++
- 4 files changed, 121 insertions(+), 124 deletions(-)
-
-diff --git a/drivers/of/address.c b/drivers/of/address.c
-index 91a469d..0a553c0 100644
---- a/drivers/of/address.c
-+++ b/drivers/of/address.c
-@@ -4,6 +4,7 @@
- #include <linux/ioport.h>
- #include <linux/module.h>
- #include <linux/of_address.h>
-+#include <linux/pci.h>
- #include <linux/pci_regs.h>
- #include <linux/sizes.h>
- #include <linux/slab.h>
-@@ -673,121 +674,6 @@ const __be32 *of_get_address(struct device_node *dev, int index, u64 *size,
- }
- EXPORT_SYMBOL(of_get_address);
- 
--#ifdef PCI_IOBASE
--struct io_range {
--	struct list_head list;
--	phys_addr_t start;
--	resource_size_t size;
--};
--
--static LIST_HEAD(io_range_list);
--static DEFINE_SPINLOCK(io_range_lock);
--#endif
--
--/*
-- * Record the PCI IO range (expressed as CPU physical address + size).
-- * Return a negative value if an error has occured, zero otherwise
-- */
--int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
--{
--	int err = 0;
--
--#ifdef PCI_IOBASE
--	struct io_range *range;
--	resource_size_t allocated_size = 0;
--
--	/* check if the range hasn't been previously recorded */
--	spin_lock(&io_range_lock);
--	list_for_each_entry(range, &io_range_list, list) {
--		if (addr >= range->start && addr + size <= range->start + size) {
--			/* range already registered, bail out */
--			goto end_register;
--		}
--		allocated_size += range->size;
--	}
--
--	/* range not registed yet, check for available space */
--	if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
--		/* if it's too big check if 64K space can be reserved */
--		if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
--			err = -E2BIG;
--			goto end_register;
--		}
--
--		size = SZ_64K;
--		pr_warn("Requested IO range too big, new size set to 64K\n");
--	}
--
--	/* add the range to the list */
--	range = kzalloc(sizeof(*range), GFP_ATOMIC);
--	if (!range) {
--		err = -ENOMEM;
--		goto end_register;
--	}
--
--	range->start = addr;
--	range->size = size;
--
--	list_add_tail(&range->list, &io_range_list);
--
--end_register:
--	spin_unlock(&io_range_lock);
--#endif
--
--	return err;
--}
--
--phys_addr_t pci_pio_to_address(unsigned long pio)
--{
--	phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
--
--#ifdef PCI_IOBASE
--	struct io_range *range;
--	resource_size_t allocated_size = 0;
--
--	if (pio > IO_SPACE_LIMIT)
--		return address;
--
--	spin_lock(&io_range_lock);
--	list_for_each_entry(range, &io_range_list, list) {
--		if (pio >= allocated_size && pio < allocated_size + range->size) {
--			address = range->start + pio - allocated_size;
--			break;
--		}
--		allocated_size += range->size;
--	}
--	spin_unlock(&io_range_lock);
--#endif
--
--	return address;
--}
--
--unsigned long __weak pci_address_to_pio(phys_addr_t address)
--{
--#ifdef PCI_IOBASE
--	struct io_range *res;
--	resource_size_t offset = 0;
--	unsigned long addr = -1;
--
--	spin_lock(&io_range_lock);
--	list_for_each_entry(res, &io_range_list, list) {
--		if (address >= res->start && address < res->start + res->size) {
--			addr = address - res->start + offset;
--			break;
--		}
--		offset += res->size;
--	}
--	spin_unlock(&io_range_lock);
--
--	return addr;
--#else
--	if (address > IO_SPACE_LIMIT)
--		return (unsigned long)-1;
--
--	return (unsigned long) address;
--#endif
--}
--
- static int __of_address_to_resource(struct device_node *dev,
- 		const __be32 *addrp, u64 size, unsigned int flags,
- 		const char *name, struct resource *r)
-diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
-index d6c768e..3a516c0 100644
---- a/drivers/pci/pci.c
-+++ b/drivers/pci/pci.c
-@@ -3023,6 +3023,121 @@ int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
- }
- EXPORT_SYMBOL(pci_request_regions_exclusive);
- 
-+#ifdef PCI_IOBASE
-+struct io_range {
-+	struct list_head list;
-+	phys_addr_t start;
-+	resource_size_t size;
-+};
-+
-+static LIST_HEAD(io_range_list);
-+static DEFINE_SPINLOCK(io_range_lock);
-+#endif
-+
-+/*
-+ * Record the PCI IO range (expressed as CPU physical address + size).
-+ * Return a negative value if an error has occured, zero otherwise
-+ */
-+int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
-+{
-+	int err = 0;
-+
-+#ifdef PCI_IOBASE
-+	struct io_range *range;
-+	resource_size_t allocated_size = 0;
-+
-+	/* check if the range hasn't been previously recorded */
-+	spin_lock(&io_range_lock);
-+	list_for_each_entry(range, &io_range_list, list) {
-+		if (addr >= range->start && addr + size <= range->start + size) {
-+			/* range already registered, bail out */
-+			goto end_register;
-+		}
-+		allocated_size += range->size;
-+	}
-+
-+	/* range not registed yet, check for available space */
-+	if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
-+		/* if it's too big check if 64K space can be reserved */
-+		if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
-+			err = -E2BIG;
-+			goto end_register;
-+		}
-+
-+		size = SZ_64K;
-+		pr_warn("Requested IO range too big, new size set to 64K\n");
-+	}
-+
-+	/* add the range to the list */
-+	range = kzalloc(sizeof(*range), GFP_ATOMIC);
-+	if (!range) {
-+		err = -ENOMEM;
-+		goto end_register;
-+	}
-+
-+	range->start = addr;
-+	range->size = size;
-+
-+	list_add_tail(&range->list, &io_range_list);
-+
-+end_register:
-+	spin_unlock(&io_range_lock);
-+#endif
-+
-+	return err;
-+}
-+
-+phys_addr_t pci_pio_to_address(unsigned long pio)
-+{
-+	phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
-+
-+#ifdef PCI_IOBASE
-+	struct io_range *range;
-+	resource_size_t allocated_size = 0;
-+
-+	if (pio > IO_SPACE_LIMIT)
-+		return address;
-+
-+	spin_lock(&io_range_lock);
-+	list_for_each_entry(range, &io_range_list, list) {
-+		if (pio >= allocated_size && pio < allocated_size + range->size) {
-+			address = range->start + pio - allocated_size;
-+			break;
-+		}
-+		allocated_size += range->size;
-+	}
-+	spin_unlock(&io_range_lock);
-+#endif
-+
-+	return address;
-+}
-+
-+unsigned long __weak pci_address_to_pio(phys_addr_t address)
-+{
-+#ifdef PCI_IOBASE
-+	struct io_range *res;
-+	resource_size_t offset = 0;
-+	unsigned long addr = -1;
-+
-+	spin_lock(&io_range_lock);
-+	list_for_each_entry(res, &io_range_list, list) {
-+		if (address >= res->start && address < res->start + res->size) {
-+			addr = address - res->start + offset;
-+			break;
-+		}
-+		offset += res->size;
-+	}
-+	spin_unlock(&io_range_lock);
-+
-+	return addr;
-+#else
-+	if (address > IO_SPACE_LIMIT)
-+		return (unsigned long)-1;
-+
-+	return (unsigned long) address;
-+#endif
-+}
-+
- /**
-  *	pci_remap_iospace - Remap the memory mapped I/O space
-  *	@res: Resource describing the I/O space
-diff --git a/include/linux/of_address.h b/include/linux/of_address.h
-index 01c0a55..3786473 100644
---- a/include/linux/of_address.h
-+++ b/include/linux/of_address.h
-@@ -47,10 +47,6 @@ void __iomem *of_io_request_and_map(struct device_node *device,
- extern const __be32 *of_get_address(struct device_node *dev, int index,
- 			   u64 *size, unsigned int *flags);
- 
--extern int pci_register_io_range(phys_addr_t addr, resource_size_t size);
--extern unsigned long pci_address_to_pio(phys_addr_t addr);
--extern phys_addr_t pci_pio_to_address(unsigned long pio);
--
- extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
- 			struct device_node *node);
- extern struct of_pci_range *of_pci_range_parser_one(
-@@ -86,11 +82,6 @@ static inline const __be32 *of_get_address(struct device_node *dev, int index,
- 	return NULL;
- }
- 
--static inline phys_addr_t pci_pio_to_address(unsigned long pio)
--{
--	return 0;
--}
--
- static inline int of_pci_range_parser_init(struct of_pci_range_parser *parser,
- 			struct device_node *node)
- {
-diff --git a/include/linux/pci.h b/include/linux/pci.h
-index 27df4a6..dac677c 100644
---- a/include/linux/pci.h
-+++ b/include/linux/pci.h
-@@ -1168,6 +1168,9 @@ int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
- 			void *alignf_data);
- 
- 
-+int pci_register_io_range(phys_addr_t addr, resource_size_t size);
-+unsigned long pci_address_to_pio(phys_addr_t addr);
-+phys_addr_t pci_pio_to_address(unsigned long pio);
- int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
- 
- static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
-@@ -1488,6 +1491,8 @@ static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
- { return -EIO; }
- static inline void pci_release_regions(struct pci_dev *dev) { }
- 
-+static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
-+
- static inline void pci_block_cfg_access(struct pci_dev *dev) { }
- static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
- { return 0; }
--- 
-2.7.2
-
diff --git a/disabled/0031-x86-cmpxchg-break.patch b/disabled/0031-x86-cmpxchg-break.patch
deleted file mode 100644
index 896d5b3..0000000
--- a/disabled/0031-x86-cmpxchg-break.patch
+++ /dev/null
@@ -1,54 +0,0 @@
---- linux-4.10/arch/x86/include/asm/cmpxchg.h.omv~	2017-03-03 14:46:55.958170641 +0100
-+++ linux-4.10/arch/x86/include/asm/cmpxchg.h	2017-03-03 14:51:56.894376770 +0100
-@@ -86,46 +86,33 @@ extern void __add_wrong_size(void)
- 	__typeof__(*(ptr)) __ret;					\
- 	__typeof__(*(ptr)) __old = (old);				\
- 	__typeof__(*(ptr)) __new = (new);				\
--	switch (size) {							\
--	case __X86_CASE_B:						\
-+	if (size == __X86_CASE_B) {					\
- 	{								\
- 		volatile u8 *__ptr = (volatile u8 *)(ptr);		\
- 		asm volatile(lock "cmpxchgb %2,%1"			\
- 			     : "=a" (__ret), "+m" (*__ptr)		\
- 			     : "q" (__new), "0" (__old)			\
- 			     : "memory");				\
--		break;							\
--	}								\
--	case __X86_CASE_W:						\
--	{								\
-+	} else if(size == __X86_CASE_W) {				\
- 		volatile u16 *__ptr = (volatile u16 *)(ptr);		\
- 		asm volatile(lock "cmpxchgw %2,%1"			\
- 			     : "=a" (__ret), "+m" (*__ptr)		\
- 			     : "r" (__new), "0" (__old)			\
- 			     : "memory");				\
--		break;							\
--	}								\
--	case __X86_CASE_L:						\
--	{								\
-+	} else if(size == __X86_CASE_L) {				\
- 		volatile u32 *__ptr = (volatile u32 *)(ptr);		\
- 		asm volatile(lock "cmpxchgl %2,%1"			\
- 			     : "=a" (__ret), "+m" (*__ptr)		\
- 			     : "r" (__new), "0" (__old)			\
- 			     : "memory");				\
--		break;							\
--	}								\
--	case __X86_CASE_Q:						\
--	{								\
-+	} else if(size == __X86_CASE_Q) {				\
- 		volatile u64 *__ptr = (volatile u64 *)(ptr);		\
- 		asm volatile(lock "cmpxchgq %2,%1"			\
- 			     : "=a" (__ret), "+m" (*__ptr)		\
- 			     : "r" (__new), "0" (__old)			\
- 			     : "memory");				\
--		break;							\
--	}								\
--	default:							\
-+	} else								\
- 		__cmpxchg_wrong_size();					\
--	}								\
- 	__ret;								\
- })
- 
diff --git a/disabled/0050-f2fs-fix-to-return-0-if-err.patch b/disabled/0050-f2fs-fix-to-return-0-if-err.patch
deleted file mode 100644
index ded4024..0000000
--- a/disabled/0050-f2fs-fix-to-return-0-if-err.patch
+++ /dev/null
@@ -1,11 +0,0 @@
-diff -Naur linux-4.6.3/fs/f2fs/dir.c linux-4.6.3.tpg/fs/f2fs/dir.c
---- linux-4.6.3/fs/f2fs/dir.c	2016-06-24 17:22:27.000000000 +0000
-+++ linux-4.6.3.tpg/fs/f2fs/dir.c	2016-07-02 19:18:44.199858506 +0000
-@@ -887,6 +887,7 @@
- 		kunmap(dentry_page);
- 		f2fs_put_page(dentry_page, 1);
- 	}
-+	err = 0;
- out:
- 	fscrypt_fname_free_buffer(&fstr);
- 	return err;
diff --git a/disabled/01-revert-6602f080cb28745259e2fab1a4cf55eeb5894f93.patch b/disabled/01-revert-6602f080cb28745259e2fab1a4cf55eeb5894f93.patch
deleted file mode 100644
index d527b7c..0000000
--- a/disabled/01-revert-6602f080cb28745259e2fab1a4cf55eeb5894f93.patch
+++ /dev/null
@@ -1,166 +0,0 @@
-diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c
-index 4ed21dad6a8e..6049d3766c64 100644
---- a/drivers/net/wireless/ath/ath9k/hif_usb.c
-+++ b/drivers/net/wireless/ath/ath9k/hif_usb.c
-@@ -643,9 +643,9 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev,
- 
- static void ath9k_hif_usb_rx_cb(struct urb *urb)
- {
--	struct rx_buf *rx_buf = (struct rx_buf *)urb->context;
--	struct hif_device_usb *hif_dev = rx_buf->hif_dev;
--	struct sk_buff *skb = rx_buf->skb;
-+	struct sk_buff *skb = (struct sk_buff *) urb->context;
-+	struct hif_device_usb *hif_dev =
-+		usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
- 	int ret;
- 
- 	if (!skb)
-@@ -685,15 +685,14 @@ static void ath9k_hif_usb_rx_cb(struct urb *urb)
- 	return;
- free:
- 	kfree_skb(skb);
--	kfree(rx_buf);
- }
- 
- static void ath9k_hif_usb_reg_in_cb(struct urb *urb)
- {
--	struct rx_buf *rx_buf = (struct rx_buf *)urb->context;
--	struct hif_device_usb *hif_dev = rx_buf->hif_dev;
--	struct sk_buff *skb = rx_buf->skb;
-+	struct sk_buff *skb = (struct sk_buff *) urb->context;
- 	struct sk_buff *nskb;
-+	struct hif_device_usb *hif_dev =
-+		usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
- 	int ret;
- 
- 	if (!skb)
-@@ -751,7 +750,6 @@ static void ath9k_hif_usb_reg_in_cb(struct urb *urb)
- 	return;
- free:
- 	kfree_skb(skb);
--	kfree(rx_buf);
- 	urb->context = NULL;
- }
- 
-@@ -797,7 +795,7 @@ static int ath9k_hif_usb_alloc_tx_urbs(struct hif_device_usb *hif_dev)
- 	init_usb_anchor(&hif_dev->mgmt_submitted);
- 
- 	for (i = 0; i < MAX_TX_URB_NUM; i++) {
--		tx_buf = kzalloc(sizeof(*tx_buf), GFP_KERNEL);
-+		tx_buf = kzalloc(sizeof(struct tx_buf), GFP_KERNEL);
- 		if (!tx_buf)
- 			goto err;
- 
-@@ -834,9 +832,8 @@ static void ath9k_hif_usb_dealloc_rx_urbs(struct hif_device_usb *hif_dev)
- 
- static int ath9k_hif_usb_alloc_rx_urbs(struct hif_device_usb *hif_dev)
- {
--	struct rx_buf *rx_buf = NULL;
--	struct sk_buff *skb = NULL;
- 	struct urb *urb = NULL;
-+	struct sk_buff *skb = NULL;
- 	int i, ret;
- 
- 	init_usb_anchor(&hif_dev->rx_submitted);
-@@ -844,12 +841,6 @@ static int ath9k_hif_usb_alloc_rx_urbs(struct hif_device_usb *hif_dev)
- 
- 	for (i = 0; i < MAX_RX_URB_NUM; i++) {
- 
--		rx_buf = kzalloc(sizeof(*rx_buf), GFP_KERNEL);
--		if (!rx_buf) {
--			ret = -ENOMEM;
--			goto err_rxb;
--		}
--
- 		/* Allocate URB */
- 		urb = usb_alloc_urb(0, GFP_KERNEL);
- 		if (urb == NULL) {
-@@ -864,14 +855,11 @@ static int ath9k_hif_usb_alloc_rx_urbs(struct hif_device_usb *hif_dev)
- 			goto err_skb;
- 		}
- 
--		rx_buf->hif_dev = hif_dev;
--		rx_buf->skb = skb;
--
- 		usb_fill_bulk_urb(urb, hif_dev->udev,
- 				  usb_rcvbulkpipe(hif_dev->udev,
- 						  USB_WLAN_RX_PIPE),
- 				  skb->data, MAX_RX_BUF_SIZE,
--				  ath9k_hif_usb_rx_cb, rx_buf);
-+				  ath9k_hif_usb_rx_cb, skb);
- 
- 		/* Anchor URB */
- 		usb_anchor_urb(urb, &hif_dev->rx_submitted);
-@@ -897,8 +885,6 @@ static int ath9k_hif_usb_alloc_rx_urbs(struct hif_device_usb *hif_dev)
- err_skb:
- 	usb_free_urb(urb);
- err_urb:
--	kfree(rx_buf);
--err_rxb:
- 	ath9k_hif_usb_dealloc_rx_urbs(hif_dev);
- 	return ret;
- }
-@@ -910,21 +896,14 @@ static void ath9k_hif_usb_dealloc_reg_in_urbs(struct hif_device_usb *hif_dev)
- 
- static int ath9k_hif_usb_alloc_reg_in_urbs(struct hif_device_usb *hif_dev)
- {
--	struct rx_buf *rx_buf = NULL;
--	struct sk_buff *skb = NULL;
- 	struct urb *urb = NULL;
-+	struct sk_buff *skb = NULL;
- 	int i, ret;
- 
- 	init_usb_anchor(&hif_dev->reg_in_submitted);
- 
- 	for (i = 0; i < MAX_REG_IN_URB_NUM; i++) {
- 
--		rx_buf = kzalloc(sizeof(*rx_buf), GFP_KERNEL);
--		if (!rx_buf) {
--			ret = -ENOMEM;
--			goto err_rxb;
--		}
--
- 		/* Allocate URB */
- 		urb = usb_alloc_urb(0, GFP_KERNEL);
- 		if (urb == NULL) {
-@@ -939,14 +918,11 @@ static int ath9k_hif_usb_alloc_reg_in_urbs(struct hif_device_usb *hif_dev)
- 			goto err_skb;
- 		}
- 
--		rx_buf->hif_dev = hif_dev;
--		rx_buf->skb = skb;
--
- 		usb_fill_int_urb(urb, hif_dev->udev,
- 				  usb_rcvintpipe(hif_dev->udev,
- 						  USB_REG_IN_PIPE),
- 				  skb->data, MAX_REG_IN_BUF_SIZE,
--				  ath9k_hif_usb_reg_in_cb, rx_buf, 1);
-+				  ath9k_hif_usb_reg_in_cb, skb, 1);
- 
- 		/* Anchor URB */
- 		usb_anchor_urb(urb, &hif_dev->reg_in_submitted);
-@@ -972,8 +948,6 @@ static int ath9k_hif_usb_alloc_reg_in_urbs(struct hif_device_usb *hif_dev)
- err_skb:
- 	usb_free_urb(urb);
- err_urb:
--	kfree(rx_buf);
--err_rxb:
- 	ath9k_hif_usb_dealloc_reg_in_urbs(hif_dev);
- 	return ret;
- }
-diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.h b/drivers/net/wireless/ath/ath9k/hif_usb.h
-index 5985aa15ca93..a94e7e1c86e9 100644
---- a/drivers/net/wireless/ath/ath9k/hif_usb.h
-+++ b/drivers/net/wireless/ath/ath9k/hif_usb.h
-@@ -86,11 +86,6 @@ struct tx_buf {
- 	struct list_head list;
- };
- 
--struct rx_buf {
--	struct sk_buff *skb;
--	struct hif_device_usb *hif_dev;
--};
--
- #define HIF_USB_TX_STOP  BIT(0)
- #define HIF_USB_TX_FLUSH BIT(1)
- 
diff --git a/disabled/0109-init_task-faster-timerslack.patch b/disabled/0109-init_task-faster-timerslack.patch
deleted file mode 100644
index b73ab1b..0000000
--- a/disabled/0109-init_task-faster-timerslack.patch
+++ /dev/null
@@ -1,12 +0,0 @@
-diff -up linux-4.18/init/init_task.c.0405~ linux-4.18/init/init_task.c
---- linux-4.18/init/init_task.c.0405~	2018-08-27 10:43:34.987345891 +0200
-+++ linux-4.18/init/init_task.c	2018-08-27 10:44:16.064471970 +0200
-@@ -117,7 +117,7 @@ struct task_struct init_task
- 	.journal_info	= NULL,
- 	INIT_CPU_TIMERS(init_task)
- 	.pi_lock	= __RAW_SPIN_LOCK_UNLOCKED(init_task.pi_lock),
--	.timer_slack_ns = 50000, /* 50 usec default slack */
-+	.timer_slack_ns = 1000, /* 1 usec default slack */
- 	.thread_pid	= &init_struct_pid,
- 	.thread_group	= LIST_HEAD_INIT(init_task.thread_group),
- 	.thread_node	= LIST_HEAD_INIT(init_signals.thread_head),
diff --git a/disabled/0111-overload-on-wakeup.patch b/disabled/0111-overload-on-wakeup.patch
deleted file mode 100644
index d5125be..0000000
--- a/disabled/0111-overload-on-wakeup.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From cc7c761946c6b9fa820acc90d7514795af3f42f5 Mon Sep 17 00:00:00 2001
-From: jplozi <jplozi@unice.fr>
-Date: Fri, 11 Mar 2016 15:18:06 +0100
-Subject: [PATCH 111/126] overload on wakeup
-
-source https://github.com/jplozi/wastedcores
-
-as an experiment, apply the learnings from the wasted-cores paper
-and see how the performance works out. With the data from this we should
-be able to work with Peter and the rest of the scheduler folks on
-a more permanent/elegant solution.
----
- kernel/sched/fair.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- linux-4.14/kernel/sched/fair.c.org	2017-11-18 23:01:57.353611850 +0000
-+++ linux-4.14/kernel/sched/fair.c	2017-11-19 15:24:38.093637926 +0000
-@@ -5925,6 +5925,8 @@
- 	return min_cap * 1024 < task_util(p) * capacity_margin;
- }
- 
-+
-+static unsigned int once_in_a_while;
- /*
-  * select_task_rq_fair: Select target runqueue for the waking task in domains
-  * that have the 'sd_flag' flag set. In practice, this is SD_BALANCE_WAKE,
-@@ -5953,6 +5955,30 @@
- 	}
- 
- 	rcu_read_lock();
-+	
-+	once_in_a_while++;
-+
-+	if (cpu_rq(prev_cpu)->nr_running || (once_in_a_while & 15) == 0) {
-+		int _cpu;
-+		int bestprio = -5000;
-+		int bestcpu = -1;
-+
-+		for_each_online_cpu(_cpu) {
-+			if (!cpumask_test_cpu(_cpu, &p->cpus_allowed) ||
-+				cpu_rq(_cpu)->nr_running)
-+				continue;
-+			if (arch_asym_cpu_priority(_cpu) > bestprio || (prev_cpu == _cpu && bestprio == arch_asym_cpu_priority(_cpu))) {
-+				bestcpu = _cpu;
-+				bestprio = arch_asym_cpu_priority(_cpu);
-+			}
-+		}
-+		
-+		if (bestcpu > 0) {
-+			rcu_read_unlock();
-+			return bestcpu;
-+		}
-+	}
-+
- 	for_each_domain(cpu, tmp) {
- 		if (!(tmp->flags & SD_LOAD_BALANCE))
- 			break;
diff --git a/disabled/0113-fix-initcall-timestamps.patch b/disabled/0113-fix-initcall-timestamps.patch
deleted file mode 100644
index 45fbe0e..0000000
--- a/disabled/0113-fix-initcall-timestamps.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 2d08a233a1dd6eef3979f6d09b03cfcb66db7b0e Mon Sep 17 00:00:00 2001
-From: Arjan van de Ven <arjan@linux.intel.com>
-Date: Thu, 2 Jun 2016 23:36:32 -0500
-Subject: [PATCH 113/126] fix initcall timestamps
-
-Print more finegrained initcall timings
-
-use the tsc instead of the jiffies clock for initcall_debug
----
- init/main.c | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/init/main.c b/init/main.c
-index 7da935ad2d12..d1ba883d3382 100644
---- a/init/main.c
-+++ b/init/main.c
-@@ -795,16 +795,16 @@ __setup("initcall_blacklist=", initcall_blacklist);
- 
- static int __init_or_module do_one_initcall_debug(initcall_t fn)
- {
--	ktime_t calltime, delta, rettime;
-+	unsigned long long calltime, delta, rettime;
- 	unsigned long long duration;
- 	int ret;
- 
--	printk(KERN_DEBUG "calling  %pF @ %i\n", fn, raw_smp_processor_id());
--	calltime = ktime_get();
-+	printk(KERN_DEBUG "calling  %pF @ %i\n", fn, task_pid_nr(current));
-+	calltime = local_clock();
- 	ret = fn();
--	rettime = ktime_get();
--	delta = ktime_sub(rettime, calltime);
--	duration = (unsigned long long) ktime_to_ns(delta) >> 10;
-+	rettime = local_clock();
-+	delta = rettime - calltime;
-+	duration = delta >> 10;
- 	printk(KERN_DEBUG "initcall %pF returned %d after %lld usecs\n",
- 		 fn, ret, duration);
- 
--- 
-2.15.0
diff --git a/disabled/0114-smpboot-reuse-timer-calibration.patch b/disabled/0114-smpboot-reuse-timer-calibration.patch
deleted file mode 100644
index 4df91e5..0000000
--- a/disabled/0114-smpboot-reuse-timer-calibration.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Arjan van de Ven <arjan@linux.intel.com>
-Date: Wed, 11 Feb 2015 17:28:14 -0600
-Subject: [PATCH] smpboot: reuse timer calibration
-
-NO point recalibrating for known-constant tsc ...
-saves 200ms+ of boot time.
----
- arch/x86/kernel/tsc.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
-index 0b29e58f288e..7d565350d8fe 100644
---- a/arch/x86/kernel/tsc.c
-+++ b/arch/x86/kernel/tsc.c
-@@ -1508,6 +1508,9 @@ unsigned long calibrate_delay_is_known(void)
- 	if (!constant_tsc || !mask)
- 		return 0;
- 
-+	if (cpu != 0)
-+		return cpu_data(0).loops_per_jiffy;
-+
- 	sibling = cpumask_any_but(mask, cpu);
- 	if (sibling < nr_cpu_ids)
- 		return cpu_data(sibling).loops_per_jiffy;
--- 
-https://clearlinux.org
-
diff --git a/disabled/0121-igb-no-runtime-pm-to-fix-reboot-oops.patch b/disabled/0121-igb-no-runtime-pm-to-fix-reboot-oops.patch
deleted file mode 100644
index 6bc6f2e..0000000
--- a/disabled/0121-igb-no-runtime-pm-to-fix-reboot-oops.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From 3600f0a90ddea2a2a8c4a157a0bb70913ae4e640 Mon Sep 17 00:00:00 2001
-From: Arjan van de Ven <arjan@linux.intel.com>
-Date: Thu, 12 Jan 2017 18:17:14 +0000
-Subject: [PATCH 121/126] disable PM on some NICs
-
-igb: no runtime pm to fix reboot oops
-
-Causes oops on reboot due to a race between runtime resume and shutdown
-
-e1000e: disable PM as it disconects from some NICs
-
-e1000: disable PM just in case
-
----
- drivers/net/ethernet/intel/igb/igb_main.c | 3 ---
- 1 file changed, 3 deletions(-)
-
-diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
-index ea69af267d63..1107b74225b0 100644
---- a/drivers/net/ethernet/intel/igb/igb_main.c
-+++ b/drivers/net/ethernet/intel/igb/igb_main.c
-@@ -239,9 +239,6 @@ static struct pci_driver igb_driver = {
- 	.id_table = igb_pci_tbl,
- 	.probe    = igb_probe,
- 	.remove   = igb_remove,
--#ifdef CONFIG_PM
--	.driver.pm = &igb_pm_ops,
--#endif
- 	.shutdown = igb_shutdown,
- 	.sriov_configure = igb_pci_sriov_configure,
- 	.err_handler = &igb_err_handler
-diff --git a/drivers/net/ethernet/intel/e1000/e1000_main.c b/drivers/net/ethernet/intel/e1000/e1000_main.c
-index 1982f7917a8d..6e8e8919f9b9 100644
---- a/drivers/net/ethernet/intel/e1000/e1000_main.c
-+++ b/drivers/net/ethernet/intel/e1000/e1000_main.c
-@@ -209,11 +209,6 @@ static struct pci_driver e1000_driver = {
- 	.id_table = e1000_pci_tbl,
- 	.probe    = e1000_probe,
- 	.remove   = e1000_remove,
--#ifdef CONFIG_PM
--	/* Power Management Hooks */
--	.suspend  = e1000_suspend,
--	.resume   = e1000_resume,
--#endif
- 	.shutdown = e1000_shutdown,
- 	.err_handler = &e1000_err_handler
- };
-diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
-index 327dfe5bedc0..4f66a91b4026 100644
---- a/drivers/net/ethernet/intel/e1000e/netdev.c
-+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
-@@ -7572,9 +7572,6 @@ static struct pci_driver e1000_driver = {
- 	.id_table = e1000_pci_tbl,
- 	.probe    = e1000_probe,
- 	.remove   = e1000_remove,
--	.driver   = {
--		.pm = &e1000_pm_ops,
--	},
- 	.shutdown = e1000_shutdown,
- 	.err_handler = &e1000_err_handler
- };
--- 
-2.15.0
diff --git a/disabled/0122-tweak-perfbias.patch b/disabled/0122-tweak-perfbias.patch
deleted file mode 100644
index d3a1335..0000000
--- a/disabled/0122-tweak-perfbias.patch
+++ /dev/null
@@ -1,19 +0,0 @@
-diff -up linux-5.1/arch/x86/kernel/cpu/intel.c.49~ linux-5.1/arch/x86/kernel/cpu/intel.c
---- linux-5.1/arch/x86/kernel/cpu/intel.c.49~	2019-05-07 17:36:54.729087361 +0200
-+++ linux-5.1/arch/x86/kernel/cpu/intel.c	2019-05-07 17:39:10.005775786 +0200
-@@ -608,12 +608,12 @@ static void init_intel_energy_perf(struc
- 		return;
- 
- 	rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
--	if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE)
-+	if ((epb & 0xF) >= ENERGY_PERF_BIAS_NORMAL)
- 		return;
- 
--	pr_info_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
-+	pr_info_once("ENERGY_PERF_BIAS: Set to 'performance', was 'normal'\n");
- 	pr_info_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n");
--	epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
-+	epb = (epb & ~0xF) | ENERGY_PERF_BIAS_PERFORMANCE;
- 	wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
- }
- 
diff --git a/disabled/0151-mm-Export-do_madvise.patch b/disabled/0151-mm-Export-do_madvise.patch
deleted file mode 100644
index 0871dc1..0000000
--- a/disabled/0151-mm-Export-do_madvise.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From fc4ee73f68d0e9da4ba61112416849c18d933882 Mon Sep 17 00:00:00 2001
-From: Sebastien Boeuf <sebastien.boeuf@intel.com>
-Date: Mon, 23 Jan 2017 15:03:52 -0800
-Subject: [PATCH 151/154] mm: Export do_madvise()
-
-Combined with some interesting flags madvise() system call
-allows to free memory more smartly and more efficiently than
-we could do with a simple free(). The issue is that is not
-available for kernel modules that could need it.
-
-In order to solve this lack of support, this patch exports
-do_madvise() so as to make it available to the entire kernel.
-The already existing madvise() system call is unchanged and
-now relies on this new do_madvise() function.
-
-Suggested-by: Arjan van de Ven <arjan.van.de.ven@intel.com>
-Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
----
- include/linux/mm.h |  2 ++
- mm/madvise.c       | 25 +++++++++++++++++++++----
- 2 files changed, 23 insertions(+), 4 deletions(-)
-
-diff --git a/include/linux/mm.h b/include/linux/mm.h
-index 43edf659453b..c3153e9ee7ea 100644
---- a/include/linux/mm.h
-+++ b/include/linux/mm.h
-@@ -2603,5 +2603,7 @@ void __init setup_nr_node_ids(void);
- static inline void setup_nr_node_ids(void) {}
- #endif
- 
-+extern int do_madvise(unsigned long start, size_t len_in, int behavior);
-+
- #endif /* __KERNEL__ */
- #endif /* _LINUX_MM_H */
-diff --git a/mm/madvise.c b/mm/madvise.c
-index 375cf32087e4..3798dd68692e 100644
---- a/mm/madvise.c
-+++ b/mm/madvise.c
-@@ -730,9 +730,7 @@ madvise_behavior_valid(int behavior)
- }
- 
- /*
-- * The madvise(2) system call.
-- *
-- * Applications can use madvise() to advise the kernel how it should
-+ * Kernel modules can use do_madvise() to advise the kernel how it should
-  * handle paging I/O in this VM area.  The idea is to help the kernel
-  * use appropriate read-ahead and caching techniques.  The information
-  * provided is advisory only, and can be safely disregarded by the
-@@ -790,7 +788,7 @@ madvise_behavior_valid(int behavior)
-  *  -EBADF  - map exists, but area maps something that isn't a file.
-  *  -EAGAIN - a kernel resource was temporarily unavailable.
-  */
--SYSCALL_DEFINE3(madvise, unsigned long, start, size_t, len_in, int, behavior)
-+int do_madvise(unsigned long start, size_t len_in, int behavior)
- {
- 	unsigned long end, tmp;
- 	struct vm_area_struct *vma, *prev;
-@@ -885,3 +883,22 @@ SYSCALL_DEFINE3(madvise, unsigned long, start, size_t, len_in, int, behavior)
- 
- 	return error;
- }
-+EXPORT_SYMBOL_GPL(do_madvise);
-+
-+/*
-+ * The madvise(2) system call.
-+ *
-+ * Applications can use madvise() system call to advise the kernel how
-+ * it should handle paging I/O in this VM area.  The idea is to help
-+ * the kernel use appropriate read-ahead and caching techniques.  The
-+ * information provided is advisory only, and can be safely disregarded
-+ * by the kernel without affecting the correct operation of the application.
-+ *
-+ * behavior values are the same than the ones defined in madvise()
-+ *
-+ * return values are the same than the ones defined in madvise()
-+ */
-+SYSCALL_DEFINE3(madvise, unsigned long, start, size_t, len_in, int, behavior)
-+{
-+	return do_madvise(start, len_in, behavior);
-+}
--- 
-2.15.0
diff --git a/disabled/0152-x86-kvm-Notify-host-to-release-pages.patch b/disabled/0152-x86-kvm-Notify-host-to-release-pages.patch
deleted file mode 100644
index 89b4afc..0000000
--- a/disabled/0152-x86-kvm-Notify-host-to-release-pages.patch
+++ /dev/null
@@ -1,128 +0,0 @@
-diff -up linux-4.18/arch/x86/kvm/x86.c.0420~ linux-4.18/arch/x86/kvm/x86.c
---- linux-4.18/arch/x86/kvm/x86.c.0420~	2018-08-27 10:47:39.111073764 +0200
-+++ linux-4.18/arch/x86/kvm/x86.c	2018-08-27 10:48:29.916219740 +0200
-@@ -45,6 +45,7 @@
- #include <linux/user-return-notifier.h>
- #include <linux/srcu.h>
- #include <linux/slab.h>
-+#include <linux/mm.h>
- #include <linux/perf_event.h>
- #include <linux/uaccess.h>
- #include <linux/hash.h>
-@@ -6786,6 +6787,19 @@ static void kvm_pv_kick_cpu_op(struct kv
- 	kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
- }
- 
-+static int kvm_pv_return_mem_op(struct kvm *kvm, gpa_t gpa, size_t len)
-+{
-+	unsigned long start = gfn_to_hva(kvm, gpa_to_gfn(gpa));
-+
-+	if (len > KVM_MAX_RET_MEM_SIZE)
-+		return KVM_EPERM;
-+
-+	if (kvm_is_error_hva(start + len))
-+		return KVM_EFAULT;
-+
-+	return do_madvise(start, len, kvm_ret_mem_advice);
-+}
-+
- void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
- {
- 	vcpu->arch.apicv_active = false;
-@@ -6838,6 +6852,9 @@ int kvm_emulate_hypercall(struct kvm_vcp
- 		ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
- 		break;
- #endif
-+	case KVM_HC_RETURN_MEM:
-+		ret = kvm_pv_return_mem_op(vcpu->kvm, a0, a1);
-+		break;
- 	default:
- 		ret = -KVM_ENOSYS;
- 		break;
-diff -up linux-4.18/include/linux/mm.h.0420~ linux-4.18/include/linux/mm.h
---- linux-4.18/include/linux/mm.h.0420~	2018-08-27 10:47:39.311074342 +0200
-+++ linux-4.18/include/linux/mm.h	2018-08-27 10:47:39.312074345 +0200
-@@ -2643,6 +2643,11 @@ extern bool process_shares_mm(struct tas
- extern int sysctl_drop_caches;
- int drop_caches_sysctl_handler(struct ctl_table *, int,
- 					void __user *, size_t *, loff_t *);
-+extern int sysctl_kvm_madv_instant_free;
-+extern int kvm_ret_mem_advice;
-+int kvm_madv_instant_free_sysctl_handler(struct ctl_table *table, int write,
-+					 void __user *buffer, size_t *length,
-+					 loff_t *ppos);
- #endif
- 
- void drop_slab(void);
-diff -up linux-4.18/include/uapi/linux/kvm_para.h.0420~ linux-4.18/include/uapi/linux/kvm_para.h
---- linux-4.18/include/uapi/linux/kvm_para.h.0420~	2018-08-27 10:47:39.312074345 +0200
-+++ linux-4.18/include/uapi/linux/kvm_para.h	2018-08-27 10:48:57.961299671 +0200
-@@ -28,6 +28,9 @@
- #define KVM_HC_MIPS_CONSOLE_OUTPUT	8
- #define KVM_HC_CLOCK_PAIRING		9
- #define KVM_HC_SEND_IPI		10
-+#define KVM_HC_RETURN_MEM		11
-+
-+#define KVM_MAX_RET_MEM_SIZE		(1 << 22) // 4MiB
- 
- /*
-  * hypercalls use architecture specific
-diff -up linux-4.18/kernel/sysctl.c.0420~ linux-4.18/kernel/sysctl.c
---- linux-4.18/kernel/sysctl.c.0420~	2018-08-27 10:47:39.191073996 +0200
-+++ linux-4.18/kernel/sysctl.c	2018-08-27 10:47:39.313074348 +0200
-@@ -1414,6 +1414,13 @@ static struct ctl_table vm_table[] = {
- 		.extra1		= &one,
- 		.extra2		= &four,
- 	},
-+	{
-+		.procname	= "kvm_madv_instant_free",
-+		.data		= &sysctl_kvm_madv_instant_free,
-+		.maxlen		= sizeof(int),
-+		.mode		= 0644,
-+		.proc_handler	= kvm_madv_instant_free_sysctl_handler,
-+	},
- #ifdef CONFIG_COMPACTION
- 	{
- 		.procname	= "compact_memory",
-diff -up linux-4.18/mm/kvm.c.0420~ linux-4.18/mm/kvm.c
---- linux-4.18/mm/kvm.c.0420~	2018-08-27 10:47:39.313074348 +0200
-+++ linux-4.18/mm/kvm.c	2018-08-27 10:47:39.313074348 +0200
-@@ -0,0 +1,26 @@
-+#include <linux/mman.h>
-+#include <linux/sysctl.h>
-+
-+int sysctl_kvm_madv_instant_free;
-+
-+int kvm_ret_mem_advice = MADV_DONTNEED;
-+EXPORT_SYMBOL_GPL(kvm_ret_mem_advice);
-+
-+int kvm_madv_instant_free_sysctl_handler(struct ctl_table *table, int write,
-+	void __user *buffer, size_t *length, loff_t *ppos)
-+{
-+	int ret;
-+
-+	ret = proc_dointvec(table, write, buffer, length, ppos);
-+	if (ret)
-+		return ret;
-+
-+#ifdef MADV_FREE
-+	if (sysctl_kvm_madv_instant_free > 0)
-+		kvm_ret_mem_advice = MADV_FREE;
-+	else
-+		kvm_ret_mem_advice = MADV_DONTNEED;
-+#endif
-+
-+	return 0;
-+}
-diff -up linux-4.18/mm/Makefile.0420~ linux-4.18/mm/Makefile
---- linux-4.18/mm/Makefile.0420~	2018-08-27 10:47:39.254074177 +0200
-+++ linux-4.18/mm/Makefile	2018-08-27 10:47:39.313074348 +0200
-@@ -39,7 +39,7 @@ obj-y			:= filemap.o mempool.o oom_kill.
- 			   mm_init.o mmu_context.o percpu.o slab_common.o \
- 			   compaction.o vmacache.o \
- 			   interval_tree.o list_lru.o workingset.o \
--			   debug.o $(mmu-y)
-+			   debug.o kvm.o $(mmu-y)
- 
- obj-y += init-mm.o
- 
diff --git a/disabled/0153-x86-Return-memory-from-guest-to-host-kernel.patch b/disabled/0153-x86-Return-memory-from-guest-to-host-kernel.patch
deleted file mode 100644
index 9409ded..0000000
--- a/disabled/0153-x86-Return-memory-from-guest-to-host-kernel.patch
+++ /dev/null
@@ -1,90 +0,0 @@
---- linux-4.15/arch/x86/include/asm/kvm_para.h.0421~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/arch/x86/include/asm/kvm_para.h	2018-02-12 12:34:24.909687261 +0100
-@@ -92,6 +92,28 @@ void kvm_async_pf_task_wait(u32 token, i
- void kvm_async_pf_task_wake(u32 token);
- u32 kvm_read_and_reset_pf_reason(void);
- extern void kvm_disable_steal_time(void);
-+void kvm_arch_return_memory(struct page *page, unsigned int order);
-+
-+/*
-+ * This order has been found in an empirical way, running memory tests
-+ * through many iterations to assess the number of hypercalls issued
-+ * and the amount of memory returned. In case you change this order to
-+ * 6 or 8, it should not impact your performances significantly.
-+ *
-+ * Smaller values lead to less memory waste, but consume more CPU on
-+ * hypercalls. Larger values use less CPU, but do not as precisely
-+ * inform the hypervisor of which memory is free.
-+ */
-+#define RET_MEM_BUDDY_ORDER 7
-+
-+static inline void arch_buddy_merge(struct page *page, unsigned int order)
-+{
-+	if (order < RET_MEM_BUDDY_ORDER)
-+		return;
-+
-+	kvm_arch_return_memory(page, order);
-+}
-+#define arch_buddy_merge arch_buddy_merge
- 
- #ifdef CONFIG_PARAVIRT_SPINLOCKS
- void __init kvm_spinlock_init(void);
---- linux-4.15/arch/x86/kernel/kvm.c.0421~	2018-02-12 12:34:24.909687261 +0100
-+++ linux-4.15/arch/x86/kernel/kvm.c	2018-02-12 13:19:43.422948592 +0100
-@@ -645,6 +645,16 @@ static __init int kvm_setup_pv_tlb_flush
- }
- arch_initcall(kvm_setup_pv_tlb_flush);
- 
-+void kvm_arch_return_memory(struct page *page, unsigned int order)
-+{
-+	if (!kvm_para_available())
-+		return;
-+
-+	kvm_hypercall2(KVM_HC_RETURN_MEM,
-+		       page_to_phys(page),
-+		       PAGE_SIZE << order);
-+}
-+
- #ifdef CONFIG_PARAVIRT_SPINLOCKS
- 
- /* Kick a cpu by its apicid. Used to wake up a halted vcpu */
---- linux-4.15/include/linux/mm-arch-hooks.h.0421~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/include/linux/mm-arch-hooks.h	2018-02-12 12:34:24.909687261 +0100
-@@ -12,6 +12,7 @@
- #define _LINUX_MM_ARCH_HOOKS_H
- 
- #include <asm/mm-arch-hooks.h>
-+#include <asm/kvm_para.h>
- 
- #ifndef arch_remap
- static inline void arch_remap(struct mm_struct *mm,
-@@ -22,4 +23,11 @@ static inline void arch_remap(struct mm_
- #define arch_remap arch_remap
- #endif
- 
-+#ifndef arch_buddy_merge
-+static inline void arch_buddy_merge(struct page *page, unsigned int order)
-+{
-+}
-+#define arch_buddy_merge arch_buddy_merge
-+#endif
-+
- #endif /* _LINUX_MM_ARCH_HOOKS_H */
---- linux-4.15/mm/page_alloc.c.0421~	2018-02-12 12:34:24.721686723 +0100
-+++ linux-4.15/mm/page_alloc.c	2018-02-12 12:34:24.910687264 +0100
-@@ -64,6 +64,7 @@
- #include <linux/page_owner.h>
- #include <linux/kthread.h>
- #include <linux/memcontrol.h>
-+#include <linux/mm-arch-hooks.h>
- #include <linux/ftrace.h>
- #include <linux/lockdep.h>
- #include <linux/nmi.h>
-@@ -879,6 +880,7 @@ continue_merging:
- 	}
- 
- done_merging:
-+	arch_buddy_merge(page, order);
- 	set_page_order(page, order);
- 
- 	/*
diff --git a/disabled/0154-sysctl-vm-Fine-grained-cache-shrinking.patch b/disabled/0154-sysctl-vm-Fine-grained-cache-shrinking.patch
deleted file mode 100644
index 5c2990a..0000000
--- a/disabled/0154-sysctl-vm-Fine-grained-cache-shrinking.patch
+++ /dev/null
@@ -1,136 +0,0 @@
-From 130d5d976b920aec243e0fa63273f3143660054b Mon Sep 17 00:00:00 2001
-From: Sebastien Boeuf <sebastien.boeuf@intel.com>
-Date: Mon, 23 Jan 2017 15:32:39 -0800
-Subject: [PATCH 154/154] sysctl: vm: Fine-grained cache shrinking
-
-Lots of virtual machines are let in idle state for days until they
-are terminated, and they can keep a large amount of memory in their
-cache, meaning this memory cannot be used by other processes.
-
-We tried to release this memory using existing drop_caches sysctl,
-but it led to the complete cache loss while it could have been used
-whether the idle process wakes up. Indeed, the process can't find any
-available cached data and it directly affects performances to rebuild
-it from scratch.
-
-Instead, the solution we want is based on shrinking gradually system
-cache over time. This patch adds a new sysctl shrink_caches_mb so as
-to allow userspace applications indicating the kernel it should shrink
-system cache up to the amount (in MiB) specified.
-
-There is an application called "memshrinker" which uses this new
-mechanism. It runs in the background and periodically releases a
-specified amount of cache. This amount is based on the remaining
-cache on the system, and period is computed to follow a shrinking
-model. It results in saving a lot of memory for other processes
-running on the system.
-
-Suggested-by: Arjan van de Ven <arjan.van.de.ven@intel.com>
-Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
----
- fs/drop_caches.c   | 25 +++++++++++++++++++++++++
- include/linux/mm.h |  4 ++++
- kernel/sysctl.c    |  8 ++++++++
- mm/vmscan.c        |  2 --
- 4 files changed, 37 insertions(+), 2 deletions(-)
-
-diff --git a/fs/drop_caches.c b/fs/drop_caches.c
-index 82377017130f..f8de1383498b 100644
---- a/fs/drop_caches.c
-+++ b/fs/drop_caches.c
-@@ -9,10 +9,12 @@
- #include <linux/writeback.h>
- #include <linux/sysctl.h>
- #include <linux/gfp.h>
-+#include <linux/swap.h>
- #include "internal.h"
- 
- /* A global variable is a bit ugly, but it keeps the code simple */
- int sysctl_drop_caches;
-+int sysctl_shrink_caches_mb;
- 
- static void drop_pagecache_sb(struct super_block *sb, void *unused)
- {
-@@ -68,3 +70,26 @@ int drop_caches_sysctl_handler(struct ctl_table *table, int write,
- 	}
- 	return 0;
- }
-+
-+int shrink_caches_sysctl_handler(struct ctl_table *table, int write,
-+	void __user *buffer, size_t *length, loff_t *ppos)
-+{
-+	int ret;
-+	unsigned long nr_to_reclaim, page_reclaimed;
-+
-+	ret = proc_dointvec_minmax(table, write, buffer, length, ppos);
-+	if (ret)
-+		return ret;
-+
-+	nr_to_reclaim = sysctl_shrink_caches_mb * (1 << 20) / PAGE_SIZE;
-+	if (write) {
-+		page_reclaimed = shrink_all_memory(nr_to_reclaim);
-+		if (page_reclaimed > 0)
-+			lru_add_drain_all();
-+
-+		if (page_reclaimed != nr_to_reclaim)
-+			return page_reclaimed;
-+	}
-+
-+	return 0;
-+}
-diff --git a/include/linux/mm.h b/include/linux/mm.h
-index 15e02bf3a6b3..9f9b967ad2c9 100644
---- a/include/linux/mm.h
-+++ b/include/linux/mm.h
-@@ -2457,6 +2457,10 @@ extern int kvm_ret_mem_advice;
- int kvm_madv_instant_free_sysctl_handler(struct ctl_table *table, int write,
- 					 void __user *buffer, size_t *length,
- 					 loff_t *ppos);
-+extern int sysctl_shrink_caches_mb;
-+int shrink_caches_sysctl_handler(struct ctl_table *table, int write,
-+				 void __user *buffer, size_t *length,
-+				 loff_t *ppos);
- #endif
- 
- void drop_slab(void);
-diff --git a/kernel/sysctl.c b/kernel/sysctl.c
-index 9a1611f92a2a..9b74b4f0251d 100644
---- a/kernel/sysctl.c
-+++ b/kernel/sysctl.c
-@@ -1417,6 +1417,14 @@ static struct ctl_table vm_table[] = {
- 		.mode		= 0644,
- 		.proc_handler	= kvm_madv_instant_free_sysctl_handler,
- 	},
-+	{
-+		.procname       = "shrink_caches_mb",
-+		.data           = &sysctl_shrink_caches_mb,
-+		.maxlen         = sizeof(int),
-+		.mode           = 0644,
-+		.proc_handler   = shrink_caches_sysctl_handler,
-+		.extra1         = &one,
-+	},
- #ifdef CONFIG_COMPACTION
- 	{
- 		.procname	= "compact_memory",
-diff --git a/mm/vmscan.c b/mm/vmscan.c
-index eb2f0315b8c0..b16f327b0211 100644
---- a/mm/vmscan.c
-+++ b/mm/vmscan.c
-@@ -3646,7 +3646,6 @@ void wakeup_kswapd(struct zone *zone, int order, enum zone_type classzone_idx)
- 	wake_up_interruptible(&pgdat->kswapd_wait);
- }
- 
--#ifdef CONFIG_HIBERNATION
- /*
-  * Try to free `nr_to_reclaim' of memory, system-wide, and return the number of
-  * freed pages.
-@@ -3686,7 +3685,6 @@ unsigned long shrink_all_memory(unsigned long nr_to_reclaim)
- 
- 	return nr_reclaimed;
- }
--#endif /* CONFIG_HIBERNATION */
- 
- /* It's optimal to keep kswapds on the same CPUs as their memory, but
-    not required for correctness.  So if the last cpu in a node goes
--- 
-2.15.0
diff --git a/disabled/2-0001-x86-Don-t-declare-__force_order-in-kaslr_64.c.patch b/disabled/2-0001-x86-Don-t-declare-__force_order-in-kaslr_64.c.patch
deleted file mode 100644
index b809432..0000000
--- a/disabled/2-0001-x86-Don-t-declare-__force_order-in-kaslr_64.c.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From c8c26194cf5a344cd53763eaaf16c3ab609736f4 Mon Sep 17 00:00:00 2001
-From: "H.J. Lu" <hjl.tools@gmail.com>
-Date: Thu, 16 Jan 2020 12:46:51 -0800
-Subject: [PATCH] x86: Don't declare __force_order in kaslr_64.c
-
-GCC 10 changed the default to -fno-common, which leads to
-
-  LD      arch/x86/boot/compressed/vmlinux
-ld: arch/x86/boot/compressed/pgtable_64.o:(.bss+0x0): multiple definition of `__force_order'; arch/x86/boot/compressed/kaslr_64.o:(.bss+0x0): first defined here
-make[2]: *** [arch/x86/boot/compressed/Makefile:119: arch/x86/boot/compressed/vmlinux] Error 1
-
-Since __force_order is already provided in pgtable_64.c, there is no
-need to declare __force_order in kaslr_64.c.
-
-Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
-Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
----
- arch/x86/boot/compressed/kaslr_64.c | 3 ---
- 1 file changed, 3 deletions(-)
-
-diff --git a/arch/x86/boot/compressed/kaslr_64.c b/arch/x86/boot/compressed/kaslr_64.c
-index 748456c365f4..9557c5a15b91 100644
---- a/arch/x86/boot/compressed/kaslr_64.c
-+++ b/arch/x86/boot/compressed/kaslr_64.c
-@@ -29,9 +29,6 @@
- #define __PAGE_OFFSET __PAGE_OFFSET_BASE
- #include "../../mm/ident_map.c"
- 
--/* Used by pgtable.h asm code to force instruction serialization. */
--unsigned long __force_order;
--
- /* Used to track our page table allocation area. */
- struct alloc_pgt_data {
- 	unsigned char *pgt_buf;
--- 
-2.24.1
-
diff --git a/disabled/4.12.10-C11.patch b/disabled/4.12.10-C11.patch
deleted file mode 100644
index 96119a2..0000000
--- a/disabled/4.12.10-C11.patch
+++ /dev/null
@@ -1,104 +0,0 @@
---- linux-4.13/arch/x86/entry/common.c.0250~	2017-09-03 22:56:17.000000000 +0200
-+++ linux-4.13/arch/x86/entry/common.c	2017-09-04 14:48:56.658723194 +0200
-@@ -178,7 +178,7 @@ static void exit_to_usermode_loop(struct
- }
- 
- /* Called with IRQs disabled. */
--__visible inline void prepare_exit_to_usermode(struct pt_regs *regs)
-+__visible extern inline void prepare_exit_to_usermode(struct pt_regs *regs)
- {
- 	struct thread_info *ti = current_thread_info();
- 	u32 cached_flags;
-@@ -241,7 +241,7 @@ static void syscall_slow_exit_work(struc
-  * Called with IRQs on and fully valid regs.  Returns with IRQs off in a
-  * state such that we can immediately switch to user mode.
-  */
--__visible inline void syscall_return_slowpath(struct pt_regs *regs)
-+__visible extern inline void syscall_return_slowpath(struct pt_regs *regs)
- {
- 	struct thread_info *ti = current_thread_info();
- 	u32 cached_flags = READ_ONCE(ti->flags);
---- linux-4.13/drivers/staging/rtl8192u/Makefile.0250~	2017-09-03 22:56:17.000000000 +0200
-+++ linux-4.13/drivers/staging/rtl8192u/Makefile	2017-09-04 14:48:56.658723194 +0200
-@@ -1,6 +1,6 @@
- NIC_SELECT = RTL8192U
- 
--ccflags-y := -std=gnu89
-+ccflags-y := -std=gnu11
- ccflags-y += -O2
- 
- ccflags-y += -DCONFIG_FORCE_HARD_FLOAT=y
---- linux-4.13/drivers/staging/rtl8723bs/include/ieee80211.h.0250~	2017-09-04 14:48:56.659723191 +0200
-+++ linux-4.13/drivers/staging/rtl8723bs/include/ieee80211.h	2017-09-04 14:50:35.319423023 +0200
-@@ -1008,18 +1008,18 @@ enum ieee80211_state {
- #define IP_FMT "%pI4"
- #define IP_ARG(x) (x)
- 
--extern __inline int is_multicast_mac_addr(const u8 *addr)
-+static inline int is_multicast_mac_addr(const u8 *addr)
- {
-         return ((addr[0] != 0xff) && (0x01 & addr[0]));
- }
- 
--extern __inline int is_broadcast_mac_addr(const u8 *addr)
-+static inline int is_broadcast_mac_addr(const u8 *addr)
- {
- 	return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) &&   \
- 		(addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff));
- }
- 
--extern __inline int is_zero_mac_addr(const u8 *addr)
-+static inline int is_zero_mac_addr(const u8 *addr)
- {
- 	return ((addr[0] == 0x00) && (addr[1] == 0x00) && (addr[2] == 0x00) &&   \
- 		(addr[3] == 0x00) && (addr[4] == 0x00) && (addr[5] == 0x00));
---- linux-4.13/lib/decompress_unlzo.c.0250~	2017-09-03 22:56:17.000000000 +0200
-+++ linux-4.13/lib/decompress_unlzo.c	2017-09-04 14:48:56.659723191 +0200
-@@ -52,7 +52,7 @@ static const unsigned char lzop_magic[]
- #define HEADER_SIZE_MIN       (9 + 7     + 4 + 8     + 1       + 4)
- #define HEADER_SIZE_MAX       (9 + 7 + 1 + 8 + 8 + 4 + 1 + 255 + 4)
- 
--STATIC inline long INIT parse_header(u8 *input, long *skip, long in_len)
-+static inline long INIT parse_header(u8 *input, long *skip, long in_len)
- {
- 	int l;
- 	u8 *parse = input;
---- linux-4.13/Makefile.0250~	2017-09-04 14:48:56.659723191 +0200
-+++ linux-4.13/Makefile	2017-09-04 14:51:00.831345374 +0200
-@@ -301,7 +301,7 @@ HOST_LFS_LIBS := $(shell getconf LFS_LIB
- HOSTCC       = gcc
- HOSTCXX      = g++
- HOSTCFLAGS   := -Wall -Wmissing-prototypes -Wstrict-prototypes -O2 \
--		-fomit-frame-pointer -std=gnu89 $(HOST_LFS_CFLAGS)
-+		-fomit-frame-pointer -std=gnu11 $(HOST_LFS_CFLAGS)
- HOSTCXXFLAGS := -O2 $(HOST_LFS_CFLAGS)
- HOSTLDFLAGS  := $(HOST_LFS_LDFLAGS)
- HOST_LOADLIBES := $(HOST_LFS_LIBS)
-@@ -399,7 +399,7 @@ KBUILD_CFLAGS   := -Wall -Wundef -Wstric
- 		   -fno-strict-aliasing -fno-common -fshort-wchar \
- 		   -Werror-implicit-function-declaration \
- 		   -Wno-format-security \
--		   -std=gnu89 $(call cc-option,-fno-PIE)
-+		   -std=gnu11 $(call cc-option,-fno-PIE)
- 
- 
- KBUILD_AFLAGS_KERNEL :=
---- linux-4.13/tools/testing/selftests/sync/Makefile.0250~	2017-09-03 22:56:17.000000000 +0200
-+++ linux-4.13/tools/testing/selftests/sync/Makefile	2017-09-04 14:48:56.659723191 +0200
-@@ -1,4 +1,4 @@
--CFLAGS += -O2 -g -std=gnu89 -pthread -Wall -Wextra
-+CFLAGS += -O2 -g -std=gnu11 -pthread -Wall -Wextra
- CFLAGS += -I../../../../usr/include/
- LDFLAGS += -pthread
- 
---- linux-4.13/drivers/video/fbdev/i810/i810_dvt.c.omv~	2017-09-04 15:52:19.146422533 +0200
-+++ linux-4.13/drivers/video/fbdev/i810/i810_dvt.c	2017-09-04 15:53:17.307284532 +0200
-@@ -207,7 +207,7 @@ void round_off_xres(u32 *xres)
- 		*xres = 1600;
- }
- 
--inline void round_off_yres(u32 *xres, u32 *yres)
-+void round_off_yres(u32 *xres, u32 *yres)
- {
- 	*yres = (*xres * 3) >> 2;
- }
diff --git a/disabled/4.14-C11.patch b/disabled/4.14-C11.patch
deleted file mode 100644
index f020a7d..0000000
--- a/disabled/4.14-C11.patch
+++ /dev/null
@@ -1,102 +0,0 @@
---- linux-4.14/drivers/staging/rtl8192u/Makefile.0250~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/staging/rtl8192u/Makefile	2017-12-25 17:45:17.803635299 +0100
-@@ -1,7 +1,7 @@
- # SPDX-License-Identifier: GPL-2.0
- NIC_SELECT = RTL8192U
- 
--ccflags-y := -std=gnu89
-+ccflags-y := -std=gnu11
- ccflags-y += -O2
- 
- ccflags-y += -DCONFIG_FORCE_HARD_FLOAT=y
---- linux-4.14/drivers/staging/rtl8723bs/include/ieee80211.h.0250~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/staging/rtl8723bs/include/ieee80211.h	2017-12-25 17:45:17.803635299 +0100
-@@ -1008,18 +1008,18 @@ enum ieee80211_state {
- #define IP_FMT "%pI4"
- #define IP_ARG(x) (x)
- 
--extern __inline int is_multicast_mac_addr(const u8 *addr)
-+static inline int is_multicast_mac_addr(const u8 *addr)
- {
-         return ((addr[0] != 0xff) && (0x01 & addr[0]));
- }
- 
--extern __inline int is_broadcast_mac_addr(const u8 *addr)
-+static inline int is_broadcast_mac_addr(const u8 *addr)
- {
- 	return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) &&   \
- 		(addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff));
- }
- 
--extern __inline int is_zero_mac_addr(const u8 *addr)
-+static inline int is_zero_mac_addr(const u8 *addr)
- {
- 	return ((addr[0] == 0x00) && (addr[1] == 0x00) && (addr[2] == 0x00) &&   \
- 		(addr[3] == 0x00) && (addr[4] == 0x00) && (addr[5] == 0x00));
---- linux-4.14/drivers/video/fbdev/i810/i810_dvt.c.0250~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/video/fbdev/i810/i810_dvt.c	2017-12-25 17:45:17.803635299 +0100
-@@ -207,7 +207,7 @@ void round_off_xres(u32 *xres)
- 		*xres = 1600;
- }
- 
--inline void round_off_yres(u32 *xres, u32 *yres)
-+void round_off_yres(u32 *xres, u32 *yres)
- {
- 	*yres = (*xres * 3) >> 2;
- }
---- linux-4.14/lib/decompress_unlzo.c.0250~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/lib/decompress_unlzo.c	2017-12-25 17:45:17.803635299 +0100
-@@ -52,7 +52,7 @@ static const unsigned char lzop_magic[]
- #define HEADER_SIZE_MIN       (9 + 7     + 4 + 8     + 1       + 4)
- #define HEADER_SIZE_MAX       (9 + 7 + 1 + 8 + 8 + 4 + 1 + 255 + 4)
- 
--STATIC inline long INIT parse_header(u8 *input, long *skip, long in_len)
-+static inline long INIT parse_header(u8 *input, long *skip, long in_len)
- {
- 	int l;
- 	u8 *parse = input;
---- linux-4.14/Makefile.0250~	2017-12-25 17:45:17.567633653 +0100
-+++ linux-4.14/Makefile	2017-12-25 17:47:27.841791582 +0100
-@@ -362,7 +362,7 @@ HOST_LFS_LIBS := $(shell getconf LFS_LIB
- HOSTCC       = gcc
- HOSTCXX      = g++
- HOSTCFLAGS   := -Wall -Wmissing-prototypes -Wstrict-prototypes -O2 \
--		-fomit-frame-pointer -std=gnu89 $(HOST_LFS_CFLAGS)
-+		-fomit-frame-pointer -std=gnu11 $(HOST_LFS_CFLAGS)
- HOSTCXXFLAGS := -O2 $(HOST_LFS_CFLAGS)
- HOSTLDFLAGS  := $(HOST_LFS_LDFLAGS)
- HOST_LOADLIBES := $(HOST_LFS_LIBS)
-@@ -417,7 +417,7 @@ KBUILD_CFLAGS   := -Wall -Wundef -Wstric
- 		   -fno-strict-aliasing -fno-common -fshort-wchar \
- 		   -Werror-implicit-function-declaration \
- 		   -Wno-format-security \
--		   -std=gnu89
-+		   -std=gnu11
- KBUILD_CPPFLAGS := -D__KERNEL__
- KBUILD_AFLAGS_KERNEL :=
- KBUILD_CFLAGS_KERNEL :=
---- linux-4.14/tools/testing/selftests/sync/Makefile.0250~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/tools/testing/selftests/sync/Makefile	2017-12-25 17:45:17.803635299 +0100
-@@ -1,5 +1,5 @@
- # SPDX-License-Identifier: GPL-2.0
--CFLAGS += -O2 -g -std=gnu89 -pthread -Wall -Wextra
-+CFLAGS += -O2 -g -std=gnu11 -pthread -Wall -Wextra
- CFLAGS += -I../../../../usr/include/
- LDFLAGS += -pthread
- 
-diff -up linux-4.17/drivers/scsi/lpfc/lpfc_sli4.h.omv~ linux-4.17/drivers/scsi/lpfc/lpfc_sli4.h
---- linux-4.17/drivers/scsi/lpfc/lpfc_sli4.h.omv~	2018-06-06 21:40:30.150363628 +0200
-+++ linux-4.17/drivers/scsi/lpfc/lpfc_sli4.h	2018-06-06 21:40:41.153364231 +0200
-@@ -866,10 +866,10 @@ void lpfc_sli_remove_dflt_fcf(struct lpf
- int lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *);
- int lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba);
- int lpfc_sli4_init_vpi(struct lpfc_vport *);
--inline void lpfc_sli4_eq_clr_intr(struct lpfc_queue *);
-+void lpfc_sli4_eq_clr_intr(struct lpfc_queue *);
- uint32_t lpfc_sli4_cq_release(struct lpfc_queue *, bool);
- uint32_t lpfc_sli4_eq_release(struct lpfc_queue *, bool);
--inline void lpfc_sli4_if6_eq_clr_intr(struct lpfc_queue *q);
-+void lpfc_sli4_if6_eq_clr_intr(struct lpfc_queue *q);
- uint32_t lpfc_sli4_if6_cq_release(struct lpfc_queue *q, bool arm);
- uint32_t lpfc_sli4_if6_eq_release(struct lpfc_queue *q, bool arm);
- void lpfc_sli4_fcfi_unreg(struct lpfc_hba *, uint16_t);
diff --git a/disabled/4.14-objtool-fix-seg-fault-with-gold-linker.patch b/disabled/4.14-objtool-fix-seg-fault-with-gold-linker.patch
deleted file mode 100644
index 31e30cb..0000000
--- a/disabled/4.14-objtool-fix-seg-fault-with-gold-linker.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 2a0098d70640dda192a79966c14d449e7a34d675 Mon Sep 17 00:00:00 2001
-From: Josh Poimboeuf <jpoimboe@redhat.com>
-Date: Mon, 15 Jan 2018 08:17:07 -0600
-Subject: [PATCH] objtool: Fix seg fault with gold linker
-
-Objtool segfaults when the gold linker is used with
-CONFIG_MODVERSIONS=y and CONFIG_UNWINDER_ORC=y.
-
-With CONFIG_MODVERSIONS=y, the .o file gets passed to the linker before
-being passed to objtool.  The gold linker seems to strip unused ELF
-symbols by default, which confuses objtool and causes the seg fault when
-it's trying to generate ORC metadata.
-
-Objtool should really be running immediately after GCC anyway, without a
-linker call in between.  Change the makefile ordering so that objtool is
-called before the linker.
-
-Reported-and-tested-by: Markus <M4rkusXXL@web.de>
-Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
-Cc: Linus Torvalds <torvalds@linux-foundation.org>
-Cc: Peter Zijlstra <peterz@infradead.org>
-Cc: Thomas Gleixner <tglx@linutronix.de>
-Fixes: ee9f8fce9964 ("x86/unwind: Add the ORC unwinder")
-Link: http://lkml.kernel.org/r/355f04da33581f4a3bf82e5b512973624a1e23a2.1516025651.git.jpoimboe@redhat.com
-Signed-off-by: Ingo Molnar <mingo@kernel.org>
----
- scripts/Makefile.build | 14 ++++++++++----
- 1 file changed, 10 insertions(+), 4 deletions(-)
-
-diff --git a/scripts/Makefile.build b/scripts/Makefile.build
-index e63af4e19382a..6bed45dc2cb1b 100644
---- a/scripts/Makefile.build
-+++ b/scripts/Makefile.build
-@@ -270,12 +270,18 @@ else
- objtool_args += $(call cc-ifversion, -lt, 0405, --no-unreachable)
- endif
- 
-+ifdef CONFIG_MODVERSIONS
-+objtool_o = $(@D)/.tmp_$(@F)
-+else
-+objtool_o = $(@)
-+endif
-+
- # 'OBJECT_FILES_NON_STANDARD := y': skip objtool checking for a directory
- # 'OBJECT_FILES_NON_STANDARD_foo.o := 'y': skip objtool checking for a file
- # 'OBJECT_FILES_NON_STANDARD_foo.o := 'n': override directory skip for a file
- cmd_objtool = $(if $(patsubst y%,, \
- 	$(OBJECT_FILES_NON_STANDARD_$(basetarget).o)$(OBJECT_FILES_NON_STANDARD)n), \
--	$(__objtool_obj) $(objtool_args) "$(@)";)
-+	$(__objtool_obj) $(objtool_args) "$(objtool_o)";)
- objtool_obj = $(if $(patsubst y%,, \
- 	$(OBJECT_FILES_NON_STANDARD_$(basetarget).o)$(OBJECT_FILES_NON_STANDARD)n), \
- 	$(__objtool_obj))
-@@ -291,15 +297,15 @@ objtool_dep = $(objtool_obj)					\
- define rule_cc_o_c
- 	$(call echo-cmd,checksrc) $(cmd_checksrc)			  \
- 	$(call cmd_and_fixdep,cc_o_c)					  \
--	$(cmd_modversions_c)						  \
- 	$(call echo-cmd,objtool) $(cmd_objtool)				  \
-+	$(cmd_modversions_c)						  \
- 	$(call echo-cmd,record_mcount) $(cmd_record_mcount)
- endef
- 
- define rule_as_o_S
- 	$(call cmd_and_fixdep,as_o_S)					  \
--	$(cmd_modversions_S)						  \
--	$(call echo-cmd,objtool) $(cmd_objtool)
-+	$(call echo-cmd,objtool) $(cmd_objtool)				  \
-+	$(cmd_modversions_S)
- endef
- 
- # List module undefined symbols (or empty line if not enabled)
diff --git a/disabled/4.14-rc3-drm-amdgpu.patch b/disabled/4.14-rc3-drm-amdgpu.patch
deleted file mode 100644
index 93bc186..0000000
--- a/disabled/4.14-rc3-drm-amdgpu.patch
+++ /dev/null
@@ -1,240029 +0,0 @@
---- linux-4.14/arch/x86/pci/fixup.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/arch/x86/pci/fixup.c	2017-12-14 06:39:58.373903538 +0100
-@@ -636,3 +636,83 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IN
- DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
- DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
- DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);
-+
-+#ifdef CONFIG_PHYS_ADDR_T_64BIT
-+
-+#define AMD_141b_MMIO_BASE(x)	(0x80 + (x) * 0x8)
-+#define AMD_141b_MMIO_BASE_RE_MASK		BIT(0)
-+#define AMD_141b_MMIO_BASE_WE_MASK		BIT(1)
-+#define AMD_141b_MMIO_BASE_MMIOBASE_MASK	GENMASK(31,8)
-+
-+#define AMD_141b_MMIO_LIMIT(x)	(0x84 + (x) * 0x8)
-+#define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK	GENMASK(31,8)
-+
-+#define AMD_141b_MMIO_HIGH(x)	(0x180 + (x) * 0x4)
-+#define AMD_141b_MMIO_HIGH_MMIOBASE_MASK	GENMASK(7,0)
-+#define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT	16
-+#define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK	GENMASK(23,16)
-+
-+/*
-+ * The PCI Firmware Spec, rev 3.2 notes that ACPI should optionally allow
-+ * configuring host bridge windows using the _PRS and _SRS methods.
-+ *
-+ * But this is rarely implemented, so we manually enable a large 64bit BAR for
-+ * PCIe device on AMD Family 15h (Models 30h-3fh) Processors here.
-+ */
-+static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
-+{
-+	unsigned i;
-+	u32 base, limit, high;
-+	struct resource *res, *conflict;
-+
-+	for (i = 0; i < 8; i++) {
-+		pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base);
-+		pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high);
-+
-+		/* Is this slot free? */
-+		if (!(base & (AMD_141b_MMIO_BASE_RE_MASK |
-+			      AMD_141b_MMIO_BASE_WE_MASK)))
-+			break;
-+
-+		base >>= 8;
-+		base |= high << 24;
-+
-+		/* Abort if a slot already configures a 64bit BAR. */
-+		if (base > 0x10000)
-+			return;
-+	}
-+	if (i == 8)
-+		return;
-+
-+	res = kzalloc(sizeof(*res), GFP_KERNEL);
-+	if (!res)
-+		return;
-+
-+	res->name = "PCI Bus 0000:00";
-+	res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM |
-+		IORESOURCE_MEM_64 | IORESOURCE_WINDOW;
-+	res->start = 0x100000000ull;
-+	res->end = 0xfd00000000ull - 1;
-+
-+	/* Just grab the free area behind system memory for this */
-+	while ((conflict = request_resource_conflict(&iomem_resource, res)))
-+		res->start = conflict->end + 1;
-+
-+	dev_info(&dev->dev, "adding root bus resource %pR\n", res);
-+
-+	base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) |
-+		AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK;
-+	limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK;
-+	high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) |
-+		((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT)
-+		 & AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK);
-+
-+	pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high);
-+	pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit);
-+	pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base);
-+
-+	pci_bus_add_resource(dev->bus, res, 0);
-+}
-+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
-+
-+#endif
---- linux-4.14/Documentation/admin-guide/kernel-parameters.txt.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/Documentation/admin-guide/kernel-parameters.txt	2017-12-14 06:39:58.374903539 +0100
-@@ -854,7 +854,7 @@
- 			The filter can be disabled or changed to another
- 			driver later using sysfs.
- 
--	drm_kms_helper.edid_firmware=[<connector>:]<file>[,[<connector>:]<file>]
-+	drm.edid_firmware=[<connector>:]<file>[,[<connector>:]<file>]
- 			Broken monitors, graphic adapters, KVMs and EDIDless
- 			panels may send no or incorrect EDID data sets.
- 			This parameter allows to specify an EDID data sets
---- linux-4.14/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt	2017-12-14 06:39:58.374903539 +0100
-@@ -68,6 +68,8 @@ Optional properties:
- - adi,disable-timing-generator: Only for ADV7533. Disables the internal timing
-   generator. The chip will rely on the sync signals in the DSI data lanes,
-   rather than generate its own timings for HDMI output.
-+- clocks: from common clock binding: reference to the CEC clock.
-+- clock-names: from common clock binding: must be "cec".
- 
- Required nodes:
- 
-@@ -89,6 +91,8 @@ Example
- 		reg = <39>;
- 		interrupt-parent = <&gpio3>;
- 		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
-+		clocks = <&cec_clock>;
-+		clock-names = "cec";
- 
- 		adi,input-depth = <8>;
- 		adi,input-colorspace = "rgb";
---- linux-4.14/Documentation/devicetree/bindings/display/bridge/sii9234.txt.0130~	2017-12-14 06:39:58.374903539 +0100
-+++ linux-4.14/Documentation/devicetree/bindings/display/bridge/sii9234.txt	2017-12-14 06:39:58.374903539 +0100
-@@ -0,0 +1,49 @@
-+Silicon Image SiI9234 HDMI/MHL bridge bindings
-+
-+Required properties:
-+	- compatible : "sil,sii9234".
-+	- reg : I2C address for TPI interface, use 0x39
-+	- avcc33-supply : MHL/USB Switch Supply Voltage (3.3V)
-+	- iovcc18-supply : I/O Supply Voltage (1.8V)
-+	- avcc12-supply : TMDS Analog Supply Voltage (1.2V)
-+	- cvcc12-supply : Digital Core Supply Voltage (1.2V)
-+	- interrupts, interrupt-parent: interrupt specifier of INT pin
-+	- reset-gpios: gpio specifier of RESET pin (active low)
-+	- video interfaces: Device node can contain two video interface port
-+			    nodes for HDMI encoder and connector according to [1].
-+			    - port@0 - MHL to HDMI
-+			    - port@1 - MHL to connector
-+
-+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
-+
-+
-+Example:
-+	sii9234@39 {
-+		compatible = "sil,sii9234";
-+		reg = <0x39>;
-+		avcc33-supply = <&vcc33mhl>;
-+		iovcc18-supply = <&vcc18mhl>;
-+		avcc12-supply = <&vsil12>;
-+		cvcc12-supply = <&vsil12>;
-+		reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>;
-+		interrupt-parent = <&gpf3>;
-+		interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
-+
-+		ports {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			port@0 {
-+				reg = <0>;
-+				mhl_to_hdmi: endpoint {
-+					remote-endpoint = <&hdmi_to_mhl>;
-+				};
-+			};
-+			port@1 {
-+				reg = <1>;
-+				mhl_to_connector: endpoint {
-+					remote-endpoint = <&connector_to_mhl>;
-+				};
-+			};
-+		};
-+	};
---- linux-4.14/Documentation/devicetree/bindings/display/faraday,tve200.txt.0130~	2017-12-14 06:39:58.374903539 +0100
-+++ linux-4.14/Documentation/devicetree/bindings/display/faraday,tve200.txt	2017-12-14 06:39:58.374903539 +0100
-@@ -0,0 +1,54 @@
-+* Faraday TV Encoder TVE200
-+
-+Required properties:
-+
-+- compatible: must be one of:
-+	"faraday,tve200"
-+	"cortina,gemini-tvc", "faraday,tve200"
-+
-+- reg: base address and size of the control registers block
-+
-+- interrupts: contains an interrupt specifier for the interrupt
-+	line from the TVE200
-+
-+- clock-names: should contain "PCLK" for the clock line clocking the
-+	silicon and "TVE" for the 27MHz clock to the video driver
-+
-+- clocks: contains phandle and clock specifier pairs for the entries
-+	in the clock-names property. See
-+	Documentation/devicetree/bindings/clock/clock-bindings.txt
-+
-+Optional properties:
-+
-+- resets: contains the reset line phandle for the block
-+
-+Required sub-nodes:
-+
-+- port: describes LCD panel signals, following the common binding
-+	for video transmitter interfaces; see
-+	Documentation/devicetree/bindings/media/video-interfaces.txt
-+	This port should have the properties:
-+	reg = <0>;
-+	It should have one endpoint connected to a remote endpoint where
-+	the display is connected.
-+
-+Example:
-+
-+display-controller@6a000000 {
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	compatible = "faraday,tve200";
-+	reg = <0x6a000000 0x1000>;
-+	interrupts = <13 IRQ_TYPE_EDGE_RISING>;
-+	resets = <&syscon GEMINI_RESET_TVC>;
-+	clocks = <&syscon GEMINI_CLK_GATE_TVC>,
-+		 <&syscon GEMINI_CLK_TVC>;
-+	clock-names = "PCLK", "TVE";
-+
-+	port@0 {
-+		reg = <0>;
-+		display_out: endpoint {
-+			remote-endpoint = <&panel_in>;
-+		};
-+	};
-+};
---- linux-4.14/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt.0130~	2017-12-14 06:39:58.374903539 +0100
-+++ linux-4.14/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt	2017-12-14 06:39:58.374903539 +0100
-@@ -0,0 +1,21 @@
-+Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode)
-+
-+The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using
-+a MIPI-DSI video interface. Its backlight is managed through the DSI link.
-+
-+Required properties:
-+  - compatible: "orisetech,otm8009a"
-+  - reg: the virtual channel number of a DSI peripheral
-+
-+Optional properties:
-+  - reset-gpios: a GPIO spec for the reset pin (active low).
-+
-+Example:
-+&dsi {
-+	...
-+	panel@0 {
-+		compatible = "orisetech,otm8009a";
-+		reg = <0>;
-+		reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
-+	};
-+};
---- linux-4.14/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt.0130~	2017-12-14 06:39:58.374903539 +0100
-+++ linux-4.14/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt	2017-12-14 06:39:58.374903539 +0100
-@@ -0,0 +1,49 @@
-+This binding covers the official 7" (800x480) Raspberry Pi touchscreen
-+panel.
-+
-+This DSI panel contains:
-+
-+- TC358762 DSI->DPI bridge
-+- Atmel microcontroller on I2C for power sequencing the DSI bridge and
-+  controlling backlight
-+- Touchscreen controller on I2C for touch input
-+
-+and this binding covers the DSI display parts but not its touch input.
-+
-+Required properties:
-+- compatible:	Must be "raspberrypi,7inch-touchscreen-panel"
-+- reg:		Must be "45"
-+- port:		See panel-common.txt
-+
-+Example:
-+
-+dsi1: dsi@7e700000 {
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	<...>
-+
-+	port {
-+		dsi_out_port: endpoint {
-+			remote-endpoint = <&panel_dsi_port>;
-+		};
-+	};
-+};
-+
-+i2c_dsi: i2c {
-+	compatible = "i2c-gpio";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	gpios = <&gpio 28 0
-+		 &gpio 29 0>;
-+
-+	lcd@45 {
-+		compatible = "raspberrypi,7inch-touchscreen-panel";
-+		reg = <0x45>;
-+
-+		port {
-+			panel_dsi_port: endpoint {
-+				remote-endpoint = <&dsi_out_port>;
-+			};
-+		};
-+	};
-+};
---- linux-4.14/Documentation/devicetree/bindings/display/panel/samsung,s6e63j0x03.txt.0130~	2017-12-14 06:39:58.374903539 +0100
-+++ linux-4.14/Documentation/devicetree/bindings/display/panel/samsung,s6e63j0x03.txt	2017-12-14 06:39:58.374903539 +0100
-@@ -0,0 +1,24 @@
-+Samsung S6E63J0X03 1.63" 320x320 AMOLED panel (interface: MIPI-DSI command mode)
-+
-+Required properties:
-+  - compatible: "samsung,s6e63j0x03"
-+  - reg: the virtual channel number of a DSI peripheral
-+  - vdd3-supply: I/O voltage supply
-+  - vci-supply: voltage supply for analog circuits
-+  - reset-gpios: a GPIO spec for the reset pin (active low)
-+  - te-gpios: a GPIO spec for the tearing effect synchronization signal
-+    gpio pin (active high)
-+
-+Example:
-+&dsi {
-+	...
-+
-+	panel@0 {
-+		compatible = "samsung,s6e63j0x03";
-+		reg = <0>;
-+		vdd3-supply = <&ldo16_reg>;
-+		vci-supply = <&ldo20_reg>;
-+		reset-gpios = <&gpe0 1 GPIO_ACTIVE_LOW>;
-+		te-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
-+	};
-+};
---- linux-4.14/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.txt.0130~	2017-12-14 06:39:58.374903539 +0100
-+++ linux-4.14/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.txt	2017-12-14 06:39:58.374903539 +0100
-@@ -0,0 +1,23 @@
-+Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480) TFT with Touch-Panel
-+
-+Required properties:
-+- compatible: should be "sii,43wvf1g".
-+- "dvdd-supply": 3v3 digital regulator.
-+- "avdd-supply": 5v analog regulator.
-+
-+Optional properties:
-+- backlight: phandle for the backlight control.
-+
-+Example:
-+
-+	panel {
-+		compatible = "sii,43wvf1g";
-+		backlight = <&backlight_display>;
-+		dvdd-supply = <&reg_lcd_3v3>;
-+		avdd-supply = <&reg_lcd_5v>;
-+		port {
-+			panel_in: endpoint {
-+				remote-endpoint = <&display_out>;
-+			};
-+		};
-+	};
---- linux-4.14/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt.0130~	2017-12-14 06:39:58.374903539 +0100
-+++ linux-4.14/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt	2017-12-14 06:39:58.374903539 +0100
-@@ -0,0 +1,99 @@
-+Rockchip RK3288 LVDS interface
-+================================
-+
-+Required properties:
-+- compatible: matching the soc type, one of
-+	- "rockchip,rk3288-lvds";
-+
-+- reg: physical base address of the controller and length
-+	of memory mapped region.
-+- clocks: must include clock specifiers corresponding to entries in the
-+	clock-names property.
-+- clock-names: must contain "pclk_lvds"
-+
-+- avdd1v0-supply: regulator phandle for 1.0V analog power
-+- avdd1v8-supply: regulator phandle for 1.8V analog power
-+- avdd3v3-supply: regulator phandle for 3.3V analog power
-+
-+- rockchip,grf: phandle to the general register files syscon
-+- rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface
-+
-+Optional properties:
-+- pinctrl-names: must contain a "lcdc" entry.
-+- pinctrl-0: pin control group to be used for this controller.
-+
-+Required nodes:
-+
-+The lvds has two video ports as described by
-+	Documentation/devicetree/bindings/media/video-interfaces.txt
-+Their connections are modeled using the OF graph bindings specified in
-+	Documentation/devicetree/bindings/graph.txt.
-+
-+- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
-+- video port 1 for either a panel or subsequent encoder
-+
-+the lvds panel described by
-+	Documentation/devicetree/bindings/display/panel/simple-panel.txt
-+
-+Panel required properties:
-+- ports for remote LVDS output
-+
-+Panel optional properties:
-+- data-mapping: should be "vesa-24","jeida-24" or "jeida-18".
-+This describes decribed by:
-+	Documentation/devicetree/bindings/display/panel/panel-lvds.txt
-+
-+Example:
-+
-+lvds_panel: lvds-panel {
-+	compatible = "auo,b101ean01";
-+	enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
-+	data-mapping = "jeida-24";
-+
-+	ports {
-+		panel_in_lvds: endpoint {
-+			remote-endpoint = <&lvds_out_panel>;
-+		};
-+	};
-+};
-+
-+For Rockchip RK3288:
-+
-+	lvds: lvds@ff96c000 {
-+		compatible = "rockchip,rk3288-lvds";
-+		rockchip,grf = <&grf>;
-+		reg = <0xff96c000 0x4000>;
-+		clocks = <&cru PCLK_LVDS_PHY>;
-+		clock-names = "pclk_lvds";
-+		pinctrl-names = "lcdc";
-+		pinctrl-0 = <&lcdc_ctl>;
-+		avdd1v0-supply = <&vdd10_lcd>;
-+		avdd1v8-supply = <&vcc18_lcd>;
-+		avdd3v3-supply = <&vcca_33>;
-+		rockchip,output = "rgb";
-+		ports {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			lvds_in: port@0 {
-+				reg = <0>;
-+
-+				lvds_in_vopb: endpoint@0 {
-+					reg = <0>;
-+					remote-endpoint = <&vopb_out_lvds>;
-+				};
-+				lvds_in_vopl: endpoint@1 {
-+					reg = <1>;
-+					remote-endpoint = <&vopl_out_lvds>;
-+				};
-+			};
-+
-+			lvds_out: port@1 {
-+				reg = <1>;
-+
-+				lvds_out_panel: endpoint {
-+					remote-endpoint = <&panel_in_lvds>;
-+				};
-+			};
-+		};
-+	};
---- linux-4.14/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt	2017-12-14 06:39:58.374903539 +0100
-@@ -41,14 +41,17 @@ CEC. It is one end of the pipeline.
- Required properties:
-   - compatible: value must be one of:
-     * allwinner,sun5i-a10s-hdmi
-+    * allwinner,sun6i-a31-hdmi
-   - reg: base address and size of memory-mapped region
-   - interrupts: interrupt associated to this IP
-   - clocks: phandles to the clocks feeding the HDMI encoder
-     * ahb: the HDMI interface clock
-     * mod: the HDMI module clock
-+    * ddc: the HDMI ddc clock (A31 only)
-     * pll-0: the first video PLL
-     * pll-1: the second video PLL
-   - clock-names: the clock names mentioned above
-+  - resets: phandle to the reset control for the HDMI encoder (A31 only)
-   - dmas: phandles to the DMA channels used by the HDMI encoder
-     * ddc-tx: The channel for DDC transmission
-     * ddc-rx: The channel for DDC reception
---- linux-4.14/Documentation/devicetree/bindings/vendor-prefixes.txt.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/Documentation/devicetree/bindings/vendor-prefixes.txt	2017-12-14 06:39:58.375903540 +0100
-@@ -248,6 +248,7 @@ ontat	On Tat Industrial Company
- opencores	OpenCores.org
- option	Option NV
- ORCL	Oracle Corporation
-+orisetech	Orise Technology
- ortustech	Ortus Technology Co., Ltd.
- ovti	OmniVision Technologies
- oxsemi	Oxford Semiconductor, Ltd.
---- linux-4.14/Documentation/gpu/drm-uapi.rst.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/Documentation/gpu/drm-uapi.rst	2017-12-14 06:39:58.375903540 +0100
-@@ -168,6 +168,61 @@ IOCTL Support on Device Nodes
- .. kernel-doc:: drivers/gpu/drm/drm_ioctl.c
-    :doc: driver specific ioctls
- 
-+Recommended IOCTL Return Values
-+-------------------------------
-+
-+In theory a driver's IOCTL callback is only allowed to return very few error
-+codes. In practice it's good to abuse a few more. This section documents common
-+practice within the DRM subsystem:
-+
-+ENOENT:
-+        Strictly this should only be used when a file doesn't exist e.g. when
-+        calling the open() syscall. We reuse that to signal any kind of object
-+        lookup failure, e.g. for unknown GEM buffer object handles, unknown KMS
-+        object handles and similar cases.
-+
-+ENOSPC:
-+        Some drivers use this to differentiate "out of kernel memory" from "out
-+        of VRAM". Sometimes also applies to other limited gpu resources used for
-+        rendering (e.g. when you have a special limited compression buffer).
-+        Sometimes resource allocation/reservation issues in command submission
-+        IOCTLs are also signalled through EDEADLK.
-+
-+        Simply running out of kernel/system memory is signalled through ENOMEM.
-+
-+EPERM/EACCESS:
-+        Returned for an operation that is valid, but needs more privileges.
-+        E.g. root-only or much more common, DRM master-only operations return
-+        this when when called by unpriviledged clients. There's no clear
-+        difference between EACCESS and EPERM.
-+
-+ENODEV:
-+        Feature (like PRIME, modesetting, GEM) is not supported by the driver.
-+
-+ENXIO:
-+        Remote failure, either a hardware transaction (like i2c), but also used
-+        when the exporting driver of a shared dma-buf or fence doesn't support a
-+        feature needed.
-+
-+EINTR:
-+        DRM drivers assume that userspace restarts all IOCTLs. Any DRM IOCTL can
-+        return EINTR and in such a case should be restarted with the IOCTL
-+        parameters left unchanged.
-+
-+EIO:
-+        The GPU died and couldn't be resurrected through a reset. Modesetting
-+        hardware failures are signalled through the "link status" connector
-+        property.
-+
-+EINVAL:
-+        Catch-all for anything that is an invalid argument combination which
-+        cannot work.
-+
-+IOCTL also use other error codes like ETIME, EFAULT, EBUSY, ENOTTY but their
-+usage is in line with the common meanings. The above list tries to just document
-+DRM specific patterns. Note that ENOTTY has the slightly unintuitive meaning of
-+"this IOCTL does not exist", and is used exactly as such in DRM.
-+
- .. kernel-doc:: include/drm/drm_ioctl.h
-    :internal:
- 
---- linux-4.14/Documentation/gpu/index.rst.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/Documentation/gpu/index.rst	2017-12-14 06:39:58.375903540 +0100
-@@ -15,6 +15,7 @@ Linux GPU Driver Developer's Guide
-    pl111
-    tegra
-    tinydrm
-+   tve200
-    vc4
-    vga-switcheroo
-    vgaarbiter
---- linux-4.14/Documentation/gpu/todo.rst.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/Documentation/gpu/todo.rst	2017-12-14 06:39:58.375903540 +0100
-@@ -75,17 +75,6 @@ helpers.
- 
- Contact: Ville Syrjälä, Daniel Vetter, driver maintainers
- 
--Implement deferred fbdev setup in the helper
----------------------------------------------
--
--Many (especially embedded drivers) want to delay fbdev setup until there's a
--real screen plugged in. This is to avoid the dreaded fallback to the low-res
--fbdev default. Many drivers have a hacked-up (and often broken) version of this,
--better to do it once in the shared helpers. Thierry has a patch series, but that
--one needs to be rebased and final polish applied.
--
--Contact: Thierry Reding, Daniel Vetter, driver maintainers
--
- Convert early atomic drivers to async commit helpers
- ----------------------------------------------------
- 
-@@ -138,6 +127,8 @@ interfaces to fix these issues:
-   the acquire context explicitly on stack and then also pass it down into
-   drivers explicitly so that the legacy-on-atomic functions can use them.
- 
-+  Except for some driver code this is done.
-+
- * A bunch of the vtable hooks are now in the wrong place: DRM has a split
-   between core vfunc tables (named ``drm_foo_funcs``), which are used to
-   implement the userspace ABI. And then there's the optional hooks for the
-@@ -151,6 +142,8 @@ interfaces to fix these issues:
-   connector at runtime. That's almost all of them, and would allow us to get
-   rid of a lot of ``best_encoder`` boilerplate in drivers.
- 
-+  This was almost done, but new drivers added a few more cases again.
-+
- Contact: Daniel Vetter
- 
- Get rid of dev->struct_mutex from GEM drivers
-@@ -177,14 +170,19 @@ following drivers still use ``struct_mut
- 
- Contact: Daniel Vetter, respective driver maintainers
- 
--Core refactorings
--=================
-+Convert instances of dev_info/dev_err/dev_warn to their DRM_DEV_* equivalent
-+----------------------------------------------------------------------------
- 
--Use new IDR deletion interface to clean up drm_gem_handle_delete()
--------------------------------------------------------------------
-+For drivers which could have multiple instances, it is necessary to
-+differentiate between which is which in the logs. Since DRM_INFO/WARN/ERROR
-+don't do this, drivers used dev_info/warn/err to make this differentiation. We
-+now have DRM_DEV_* variants of the drm print macros, so we can start to convert
-+those drivers back to using drm-formwatted specific log messages.
- 
--See the "This is gross" comment -- apparently the IDR system now can return an
--error code instead of oopsing.
-+Contact: Sean Paul, Maintainer of the driver you plan to convert
-+
-+Core refactorings
-+=================
- 
- Clean up the DRM header mess
- ----------------------------
-@@ -353,7 +351,16 @@ those drivers as simple as possible, so
- - backlight helpers, probably best to put them into a new drm_backlight.c.
-   This is because drivers/video is de-facto unmaintained. We could also
-   move drivers/video/backlight to drivers/gpu/backlight and take it all
--  over within drm-misc, but that's more work.
-+  over within drm-misc, but that's more work. Backlight helpers require a fair
-+  bit of reworking and refactoring. A simple example is the enabling of a backlight.
-+  Tinydrm has helpers for this. It would be good if other drivers can also use the
-+  helper. However, there are various cases we need to consider i.e different
-+  drivers seem to have different ways of enabling/disabling a backlight.
-+  We also need to consider the backlight drivers (like gpio_backlight). The situation
-+  is further complicated by the fact that the backlight is tied to fbdev
-+  via fb_notifier_callback() which has complicated logic. For further details, refer
-+  to the following discussion thread:
-+  https://groups.google.com/forum/#!topic/outreachy-kernel/8rBe30lwtdA
- 
- - spi helpers, probably best put into spi core/helper code. Thierry said
-   the spi maintainer is fast&reactive, so shouldn't be a big issue.
-@@ -390,5 +397,15 @@ those drivers as simple as possible, so
- 
- Contact: Noralf Trønnes, Daniel Vetter
- 
-+AMD DC Display Driver
-+---------------------
-+
-+AMD DC is the display driver for AMD devices starting with Vega. There has been
-+a bunch of progress cleaning it up but there's still plenty of work to be done.
-+
-+See drivers/gpu/drm/amd/display/TODO for tasks.
-+
-+Contact: Harry Wentland, Alex Deucher
-+
- Outside DRM
- ===========
---- linux-4.14/Documentation/gpu/tve200.rst.0130~	2017-12-14 06:39:58.375903540 +0100
-+++ linux-4.14/Documentation/gpu/tve200.rst	2017-12-14 06:39:58.375903540 +0100
-@@ -0,0 +1,6 @@
-+==================================
-+ drm/tve200 Faraday TV Encoder 200
-+==================================
-+
-+.. kernel-doc:: drivers/gpu/drm/tve200/tve200_drv.c
-+   :doc: Faraday TV Encoder 200
---- linux-4.14/drivers/dma-buf/dma-buf.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/dma-buf/dma-buf.c	2017-12-14 06:39:58.375903540 +0100
-@@ -625,7 +625,7 @@ EXPORT_SYMBOL_GPL(dma_buf_detach);
- struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *attach,
- 					enum dma_data_direction direction)
- {
--	struct sg_table *sg_table = ERR_PTR(-EINVAL);
-+	struct sg_table *sg_table;
- 
- 	might_sleep();
- 
---- linux-4.14/drivers/dma-buf/reservation.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/dma-buf/reservation.c	2017-12-14 06:39:58.375903540 +0100
-@@ -104,7 +104,8 @@ reservation_object_add_shared_inplace(st
- 				      struct reservation_object_list *fobj,
- 				      struct dma_fence *fence)
- {
--	u32 i;
-+	struct dma_fence *signaled = NULL;
-+	u32 i, signaled_idx;
- 
- 	dma_fence_get(fence);
- 
-@@ -126,17 +127,28 @@ reservation_object_add_shared_inplace(st
- 			dma_fence_put(old_fence);
- 			return;
- 		}
-+
-+		if (!signaled && dma_fence_is_signaled(old_fence)) {
-+			signaled = old_fence;
-+			signaled_idx = i;
-+		}
- 	}
- 
- 	/*
- 	 * memory barrier is added by write_seqcount_begin,
- 	 * fobj->shared_count is protected by this lock too
- 	 */
--	RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence);
--	fobj->shared_count++;
-+	if (signaled) {
-+		RCU_INIT_POINTER(fobj->shared[signaled_idx], fence);
-+	} else {
-+		RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence);
-+		fobj->shared_count++;
-+	}
- 
- 	write_seqcount_end(&obj->seq);
- 	preempt_enable();
-+
-+	dma_fence_put(signaled);
- }
- 
- static void
-@@ -145,8 +157,7 @@ reservation_object_add_shared_replace(st
- 				      struct reservation_object_list *fobj,
- 				      struct dma_fence *fence)
- {
--	unsigned i;
--	struct dma_fence *old_fence = NULL;
-+	unsigned i, j, k;
- 
- 	dma_fence_get(fence);
- 
-@@ -162,24 +173,20 @@ reservation_object_add_shared_replace(st
- 	 * references from the old struct are carried over to
- 	 * the new.
- 	 */
--	fobj->shared_count = old->shared_count;
--
--	for (i = 0; i < old->shared_count; ++i) {
-+	for (i = 0, j = 0, k = fobj->shared_max; i < old->shared_count; ++i) {
- 		struct dma_fence *check;
- 
- 		check = rcu_dereference_protected(old->shared[i],
- 						reservation_object_held(obj));
- 
--		if (!old_fence && check->context == fence->context) {
--			old_fence = check;
--			RCU_INIT_POINTER(fobj->shared[i], fence);
--		} else
--			RCU_INIT_POINTER(fobj->shared[i], check);
--	}
--	if (!old_fence) {
--		RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence);
--		fobj->shared_count++;
-+		if (check->context == fence->context ||
-+		    dma_fence_is_signaled(check))
-+			RCU_INIT_POINTER(fobj->shared[--k], check);
-+		else
-+			RCU_INIT_POINTER(fobj->shared[j++], check);
- 	}
-+	RCU_INIT_POINTER(fobj->shared[j++], fence);
-+	fobj->shared_count = j;
- 
- done:
- 	preempt_disable();
-@@ -192,10 +199,18 @@ done:
- 	write_seqcount_end(&obj->seq);
- 	preempt_enable();
- 
--	if (old)
--		kfree_rcu(old, rcu);
-+	if (!old)
-+		return;
- 
--	dma_fence_put(old_fence);
-+	/* Drop the references to the signaled fences */
-+	for (i = k; i < fobj->shared_max; ++i) {
-+		struct dma_fence *f;
-+
-+		f = rcu_dereference_protected(fobj->shared[i],
-+					      reservation_object_held(obj));
-+		dma_fence_put(f);
-+	}
-+	kfree_rcu(old, rcu);
- }
- 
- /**
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c	2017-12-14 06:39:58.375903540 +0100
-@@ -35,41 +35,50 @@
- 
- #include "acp_gfx_if.h"
- 
--#define ACP_TILE_ON_MASK                0x03
--#define ACP_TILE_OFF_MASK               0x02
--#define ACP_TILE_ON_RETAIN_REG_MASK     0x1f
--#define ACP_TILE_OFF_RETAIN_REG_MASK    0x20
--
--#define ACP_TILE_P1_MASK                0x3e
--#define ACP_TILE_P2_MASK                0x3d
--#define ACP_TILE_DSP0_MASK              0x3b
--#define ACP_TILE_DSP1_MASK              0x37
--
--#define ACP_TILE_DSP2_MASK              0x2f
--
--#define ACP_DMA_REGS_END		0x146c0
--#define ACP_I2S_PLAY_REGS_START		0x14840
--#define ACP_I2S_PLAY_REGS_END		0x148b4
--#define ACP_I2S_CAP_REGS_START		0x148b8
--#define ACP_I2S_CAP_REGS_END		0x1496c
--
--#define ACP_I2S_COMP1_CAP_REG_OFFSET	0xac
--#define ACP_I2S_COMP2_CAP_REG_OFFSET	0xa8
--#define ACP_I2S_COMP1_PLAY_REG_OFFSET	0x6c
--#define ACP_I2S_COMP2_PLAY_REG_OFFSET	0x68
--
--#define mmACP_PGFSM_RETAIN_REG		0x51c9
--#define mmACP_PGFSM_CONFIG_REG		0x51ca
--#define mmACP_PGFSM_READ_REG_0		0x51cc
--
--#define mmACP_MEM_SHUT_DOWN_REQ_LO	0x51f8
--#define mmACP_MEM_SHUT_DOWN_REQ_HI	0x51f9
--#define mmACP_MEM_SHUT_DOWN_STS_LO	0x51fa
--#define mmACP_MEM_SHUT_DOWN_STS_HI	0x51fb
--
--#define ACP_TIMEOUT_LOOP		0x000000FF
--#define ACP_DEVS			3
--#define ACP_SRC_ID			162
-+#define ACP_TILE_ON_MASK                	0x03
-+#define ACP_TILE_OFF_MASK               	0x02
-+#define ACP_TILE_ON_RETAIN_REG_MASK     	0x1f
-+#define ACP_TILE_OFF_RETAIN_REG_MASK    	0x20
-+
-+#define ACP_TILE_P1_MASK                	0x3e
-+#define ACP_TILE_P2_MASK                	0x3d
-+#define ACP_TILE_DSP0_MASK              	0x3b
-+#define ACP_TILE_DSP1_MASK              	0x37
-+
-+#define ACP_TILE_DSP2_MASK              	0x2f
-+
-+#define ACP_DMA_REGS_END			0x146c0
-+#define ACP_I2S_PLAY_REGS_START			0x14840
-+#define ACP_I2S_PLAY_REGS_END			0x148b4
-+#define ACP_I2S_CAP_REGS_START			0x148b8
-+#define ACP_I2S_CAP_REGS_END			0x1496c
-+
-+#define ACP_I2S_COMP1_CAP_REG_OFFSET		0xac
-+#define ACP_I2S_COMP2_CAP_REG_OFFSET		0xa8
-+#define ACP_I2S_COMP1_PLAY_REG_OFFSET		0x6c
-+#define ACP_I2S_COMP2_PLAY_REG_OFFSET		0x68
-+
-+#define mmACP_PGFSM_RETAIN_REG			0x51c9
-+#define mmACP_PGFSM_CONFIG_REG			0x51ca
-+#define mmACP_PGFSM_READ_REG_0			0x51cc
-+
-+#define mmACP_MEM_SHUT_DOWN_REQ_LO		0x51f8
-+#define mmACP_MEM_SHUT_DOWN_REQ_HI		0x51f9
-+#define mmACP_MEM_SHUT_DOWN_STS_LO		0x51fa
-+#define mmACP_MEM_SHUT_DOWN_STS_HI		0x51fb
-+
-+#define mmACP_CONTROL				0x5131
-+#define mmACP_STATUS				0x5133
-+#define mmACP_SOFT_RESET			0x5134
-+#define ACP_CONTROL__ClkEn_MASK 		0x1
-+#define ACP_SOFT_RESET__SoftResetAud_MASK 	0x100
-+#define ACP_SOFT_RESET__SoftResetAudDone_MASK	0x1000000
-+#define ACP_CLOCK_EN_TIME_OUT_VALUE		0x000000FF
-+#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE	0x000000FF
-+
-+#define ACP_TIMEOUT_LOOP			0x000000FF
-+#define ACP_DEVS				3
-+#define ACP_SRC_ID				162
- 
- enum {
- 	ACP_TILE_P1 = 0,
-@@ -260,6 +269,8 @@ static int acp_hw_init(void *handle)
- {
- 	int r, i;
- 	uint64_t acp_base;
-+	u32 val = 0;
-+	u32 count = 0;
- 	struct device *dev;
- 	struct i2s_platform_data *i2s_pdata;
- 
-@@ -371,6 +382,8 @@ static int acp_hw_init(void *handle)
- 	adev->acp.acp_cell[0].name = "acp_audio_dma";
- 	adev->acp.acp_cell[0].num_resources = 4;
- 	adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
-+	adev->acp.acp_cell[0].platform_data = &adev->asic_type;
-+	adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
- 
- 	adev->acp.acp_cell[1].name = "designware-i2s";
- 	adev->acp.acp_cell[1].num_resources = 1;
-@@ -400,6 +413,46 @@ static int acp_hw_init(void *handle)
- 		}
- 	}
- 
-+	/* Assert Soft reset of ACP */
-+	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
-+
-+	val |= ACP_SOFT_RESET__SoftResetAud_MASK;
-+	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
-+
-+	count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
-+	while (true) {
-+		val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
-+		if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
-+		    (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
-+			break;
-+		if (--count == 0) {
-+			dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
-+			return -ETIMEDOUT;
-+		}
-+		udelay(100);
-+	}
-+	/* Enable clock to ACP and wait until the clock is enabled */
-+	val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
-+	val = val | ACP_CONTROL__ClkEn_MASK;
-+	cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
-+
-+	count = ACP_CLOCK_EN_TIME_OUT_VALUE;
-+
-+	while (true) {
-+		val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
-+		if (val & (u32) 0x1)
-+			break;
-+		if (--count == 0) {
-+			dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
-+			return -ETIMEDOUT;
-+		}
-+		udelay(100);
-+	}
-+	/* Deassert the SOFT RESET flags */
-+	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
-+	val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
-+	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
-+
- 	return 0;
- }
- 
-@@ -412,6 +465,8 @@ static int acp_hw_init(void *handle)
- static int acp_hw_fini(void *handle)
- {
- 	int i, ret;
-+	u32 val = 0;
-+	u32 count = 0;
- 	struct device *dev;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-@@ -419,6 +474,42 @@ static int acp_hw_fini(void *handle)
- 	if (!adev->acp.acp_cell)
- 		return 0;
- 
-+	/* Assert Soft reset of ACP */
-+	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
-+
-+	val |= ACP_SOFT_RESET__SoftResetAud_MASK;
-+	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
-+
-+	count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
-+	while (true) {
-+		val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
-+		if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
-+		    (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
-+			break;
-+		if (--count == 0) {
-+			dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
-+			return -ETIMEDOUT;
-+		}
-+		udelay(100);
-+	}
-+	/* Disable ACP clock */
-+	val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL);
-+	val &= ~ACP_CONTROL__ClkEn_MASK;
-+	cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val);
-+
-+	count = ACP_CLOCK_EN_TIME_OUT_VALUE;
-+
-+	while (true) {
-+		val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS);
-+		if (val & (u32) 0x1)
-+			break;
-+		if (--count == 0) {
-+			dev_err(&adev->pdev->dev, "Failed to reset ACP\n");
-+			return -ETIMEDOUT;
-+		}
-+		udelay(100);
-+	}
-+
- 	if (adev->acp.acp_genpd) {
- 		for (i = 0; i < ACP_DEVS ; i++) {
- 			dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c	2017-12-14 06:39:58.375903540 +0100
-@@ -85,7 +85,7 @@ void amdgpu_amdkfd_device_probe(struct a
- 		kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
- 		break;
- 	default:
--		dev_info(adev->dev, "kfd not supported on this ASIC\n");
-+		dev_dbg(adev->dev, "kfd not supported on this ASIC\n");
- 		return;
- 	}
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c	2017-12-14 06:39:58.375903540 +0100
-@@ -169,6 +169,8 @@ static const struct kfd2kgd_calls kfd2kg
- 	.get_vmem_size = get_vmem_size,
- 	.get_gpu_clock_counter = get_gpu_clock_counter,
- 	.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
-+	.alloc_pasid = amdgpu_vm_alloc_pasid,
-+	.free_pasid = amdgpu_vm_free_pasid,
- 	.program_sh_mem_settings = kgd_program_sh_mem_settings,
- 	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
- 	.init_pipeline = kgd_init_pipeline,
-@@ -336,6 +338,7 @@ static int kgd_hqd_load(struct kgd_dev *
- 	struct cik_mqd *m;
- 	uint32_t *mqd_hqd;
- 	uint32_t reg, wptr_val, data;
-+	bool valid_wptr = false;
- 
- 	m = get_mqd(mqd);
- 
-@@ -354,7 +357,14 @@ static int kgd_hqd_load(struct kgd_dev *
- 			     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
- 	WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
- 
--	if (read_user_wptr(mm, wptr, wptr_val))
-+	/* read_user_ptr may take the mm->mmap_sem.
-+	 * release srbm_mutex to avoid circular dependency between
-+	 * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
-+	 */
-+	release_queue(kgd);
-+	valid_wptr = read_user_wptr(mm, wptr, wptr_val);
-+	acquire_queue(kgd, pipe_id, queue_id);
-+	if (valid_wptr)
- 		WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
- 
- 	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c	2017-12-14 06:39:58.375903540 +0100
-@@ -128,6 +128,8 @@ static const struct kfd2kgd_calls kfd2kg
- 	.get_vmem_size = get_vmem_size,
- 	.get_gpu_clock_counter = get_gpu_clock_counter,
- 	.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
-+	.alloc_pasid = amdgpu_vm_alloc_pasid,
-+	.free_pasid = amdgpu_vm_free_pasid,
- 	.program_sh_mem_settings = kgd_program_sh_mem_settings,
- 	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
- 	.init_pipeline = kgd_init_pipeline,
-@@ -290,6 +292,7 @@ static int kgd_hqd_load(struct kgd_dev *
- 	struct vi_mqd *m;
- 	uint32_t *mqd_hqd;
- 	uint32_t reg, wptr_val, data;
-+	bool valid_wptr = false;
- 
- 	m = get_mqd(mqd);
- 
-@@ -337,7 +340,14 @@ static int kgd_hqd_load(struct kgd_dev *
- 			     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
- 	WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
- 
--	if (read_user_wptr(mm, wptr, wptr_val))
-+	/* read_user_ptr may take the mm->mmap_sem.
-+	 * release srbm_mutex to avoid circular dependency between
-+	 * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
-+	 */
-+	release_queue(kgd);
-+	valid_wptr = read_user_wptr(mm, wptr, wptr_val);
-+	acquire_queue(kgd, pipe_id, queue_id);
-+	if (valid_wptr)
- 		WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
- 
- 	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c	2017-12-14 06:39:58.376903540 +0100
-@@ -690,12 +690,12 @@ int amdgpu_atombios_get_clock_info(struc
- 			le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
- 		/* set a reasonable default for DP */
- 		if (adev->clock.default_dispclk < 53900) {
--			DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
--				 adev->clock.default_dispclk / 100);
-+			DRM_DEBUG("Changing default dispclk from %dMhz to 600Mhz\n",
-+				  adev->clock.default_dispclk / 100);
- 			adev->clock.default_dispclk = 60000;
- 		} else if (adev->clock.default_dispclk <= 60000) {
--			DRM_INFO("Changing default dispclk from %dMhz to 625Mhz\n",
--				 adev->clock.default_dispclk / 100);
-+			DRM_DEBUG("Changing default dispclk from %dMhz to 625Mhz\n",
-+				  adev->clock.default_dispclk / 100);
- 			adev->clock.default_dispclk = 62500;
- 		}
- 		adev->clock.dp_extclk =
-@@ -1805,6 +1805,8 @@ int amdgpu_atombios_allocate_fb_scratch(
- 	uint16_t data_offset;
- 	int usage_bytes = 0;
- 	struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
-+	u64 start_addr;
-+	u64 size;
- 
- 	if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
- 		firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
-@@ -1813,7 +1815,21 @@ int amdgpu_atombios_allocate_fb_scratch(
- 			  le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
- 			  le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
- 
--		usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
-+		start_addr = firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
-+		size = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb;
-+
-+		if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
-+			(uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
-+			ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
-+			/* Firmware request VRAM reservation for SR-IOV */
-+			adev->fw_vram_usage.start_offset = (start_addr &
-+				(~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
-+			adev->fw_vram_usage.size = size << 10;
-+			/* Use the default scratch size */
-+			usage_bytes = 0;
-+		} else {
-+			usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
-+		}
- 	}
- 	ctx->scratch_size_bytes = 0;
- 	if (usage_bytes == 0)
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c	2017-12-14 06:39:58.376903540 +0100
-@@ -71,19 +71,33 @@ int amdgpu_atomfirmware_allocate_fb_scra
- 	struct atom_context *ctx = adev->mode_info.atom_context;
- 	int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
- 						vram_usagebyfirmware);
-+	struct vram_usagebyfirmware_v2_1 *	firmware_usage;
-+	uint32_t start_addr, size;
- 	uint16_t data_offset;
- 	int usage_bytes = 0;
- 
- 	if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
--		struct vram_usagebyfirmware_v2_1 *firmware_usage =
--			(struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
--
-+		firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
- 		DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
- 			  le32_to_cpu(firmware_usage->start_address_in_kb),
- 			  le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
- 			  le16_to_cpu(firmware_usage->used_by_driver_in_kb));
- 
--		usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) * 1024;
-+		start_addr = le32_to_cpu(firmware_usage->start_address_in_kb);
-+		size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb);
-+
-+		if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
-+			(uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
-+			ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
-+			/* Firmware request VRAM reservation for SR-IOV */
-+			adev->fw_vram_usage.start_offset = (start_addr &
-+				(~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
-+			adev->fw_vram_usage.size = size << 10;
-+			/* Use the default scratch size */
-+			usage_bytes = 0;
-+		} else {
-+			usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10;
-+		}
- 	}
- 	ctx->scratch_size_bytes = 0;
- 	if (usage_bytes == 0)
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c	2017-12-14 06:39:58.376903540 +0100
-@@ -42,10 +42,31 @@ struct amdgpu_cgs_device {
- 	struct amdgpu_device *adev =					\
- 		((struct amdgpu_cgs_device *)cgs_device)->adev
- 
-+static void *amdgpu_cgs_register_pp_handle(struct cgs_device *cgs_device,
-+			int (*call_back_func)(struct amd_pp_init *, void **))
-+{
-+	CGS_FUNC_ADEV;
-+	struct amd_pp_init pp_init;
-+	struct amd_powerplay *amd_pp;
-+
-+	if (call_back_func == NULL)
-+		return NULL;
-+
-+	amd_pp = &(adev->powerplay);
-+	pp_init.chip_family = adev->family;
-+	pp_init.chip_id = adev->asic_type;
-+	pp_init.pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
-+	pp_init.feature_mask = amdgpu_pp_feature_mask;
-+	pp_init.device = cgs_device;
-+	if (call_back_func(&pp_init, &(amd_pp->pp_handle)))
-+		return NULL;
-+
-+	return adev->powerplay.pp_handle;
-+}
-+
- static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
- 				    enum cgs_gpu_mem_type type,
- 				    uint64_t size, uint64_t align,
--				    uint64_t min_offset, uint64_t max_offset,
- 				    cgs_handle_t *handle)
- {
- 	CGS_FUNC_ADEV;
-@@ -53,13 +74,6 @@ static int amdgpu_cgs_alloc_gpu_mem(stru
- 	int ret = 0;
- 	uint32_t domain = 0;
- 	struct amdgpu_bo *obj;
--	struct ttm_placement placement;
--	struct ttm_place place;
--
--	if (min_offset > max_offset) {
--		BUG_ON(1);
--		return -EINVAL;
--	}
- 
- 	/* fail if the alignment is not a power of 2 */
- 	if (((align != 1) && (align & (align - 1)))
-@@ -73,41 +87,19 @@ static int amdgpu_cgs_alloc_gpu_mem(stru
- 		flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
- 			AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
- 		domain = AMDGPU_GEM_DOMAIN_VRAM;
--		if (max_offset > adev->mc.real_vram_size)
--			return -EINVAL;
--		place.fpfn = min_offset >> PAGE_SHIFT;
--		place.lpfn = max_offset >> PAGE_SHIFT;
--		place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
--			TTM_PL_FLAG_VRAM;
- 		break;
- 	case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
- 	case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
- 		flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
- 			AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
- 		domain = AMDGPU_GEM_DOMAIN_VRAM;
--		if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
--			place.fpfn =
--				max(min_offset, adev->mc.visible_vram_size) >> PAGE_SHIFT;
--			place.lpfn =
--				min(max_offset, adev->mc.real_vram_size) >> PAGE_SHIFT;
--			place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
--				TTM_PL_FLAG_VRAM;
--		}
--
- 		break;
- 	case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
- 		domain = AMDGPU_GEM_DOMAIN_GTT;
--		place.fpfn = min_offset >> PAGE_SHIFT;
--		place.lpfn = max_offset >> PAGE_SHIFT;
--		place.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
- 		break;
- 	case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
- 		flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
- 		domain = AMDGPU_GEM_DOMAIN_GTT;
--		place.fpfn = min_offset >> PAGE_SHIFT;
--		place.lpfn = max_offset >> PAGE_SHIFT;
--		place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
--			TTM_PL_FLAG_UNCACHED;
- 		break;
- 	default:
- 		return -EINVAL;
-@@ -116,15 +108,8 @@ static int amdgpu_cgs_alloc_gpu_mem(stru
- 
- 	*handle = 0;
- 
--	placement.placement = &place;
--	placement.num_placement = 1;
--	placement.busy_placement = &place;
--	placement.num_busy_placement = 1;
--
--	ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE,
--					  true, domain, flags,
--					  NULL, &placement, NULL,
--					  0, &obj);
-+	ret = amdgpu_bo_create(adev, size, align, true, domain, flags,
-+			       NULL, NULL, 0, &obj);
- 	if (ret) {
- 		DRM_ERROR("(%d) bo create failed\n", ret);
- 		return ret;
-@@ -155,19 +140,14 @@ static int amdgpu_cgs_gmap_gpu_mem(struc
- 				   uint64_t *mcaddr)
- {
- 	int r;
--	u64 min_offset, max_offset;
- 	struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
- 
- 	WARN_ON_ONCE(obj->placement.num_placement > 1);
- 
--	min_offset = obj->placements[0].fpfn << PAGE_SHIFT;
--	max_offset = obj->placements[0].lpfn << PAGE_SHIFT;
--
- 	r = amdgpu_bo_reserve(obj, true);
- 	if (unlikely(r != 0))
- 		return r;
--	r = amdgpu_bo_pin_restricted(obj, obj->preferred_domains,
--				     min_offset, max_offset, mcaddr);
-+	r = amdgpu_bo_pin(obj, obj->preferred_domains, mcaddr);
- 	amdgpu_bo_unreserve(obj);
- 	return r;
- }
-@@ -675,6 +655,85 @@ static int amdgpu_cgs_get_firmware_info(
- 
- 		if (!adev->pm.fw) {
- 			switch (adev->asic_type) {
-+			case CHIP_TAHITI:
-+				strcpy(fw_name, "radeon/tahiti_smc.bin");
-+				break;
-+			case CHIP_PITCAIRN:
-+				if ((adev->pdev->revision == 0x81) &&
-+				    ((adev->pdev->device == 0x6810) ||
-+				    (adev->pdev->device == 0x6811))) {
-+					info->is_kicker = true;
-+					strcpy(fw_name, "radeon/pitcairn_k_smc.bin");
-+				} else {
-+					strcpy(fw_name, "radeon/pitcairn_smc.bin");
-+				}
-+				break;
-+			case CHIP_VERDE:
-+				if (((adev->pdev->device == 0x6820) &&
-+					((adev->pdev->revision == 0x81) ||
-+					(adev->pdev->revision == 0x83))) ||
-+				    ((adev->pdev->device == 0x6821) &&
-+					((adev->pdev->revision == 0x83) ||
-+					(adev->pdev->revision == 0x87))) ||
-+				    ((adev->pdev->revision == 0x87) &&
-+					((adev->pdev->device == 0x6823) ||
-+					(adev->pdev->device == 0x682b)))) {
-+					info->is_kicker = true;
-+					strcpy(fw_name, "radeon/verde_k_smc.bin");
-+				} else {
-+					strcpy(fw_name, "radeon/verde_smc.bin");
-+				}
-+				break;
-+			case CHIP_OLAND:
-+				if (((adev->pdev->revision == 0x81) &&
-+					((adev->pdev->device == 0x6600) ||
-+					(adev->pdev->device == 0x6604) ||
-+					(adev->pdev->device == 0x6605) ||
-+					(adev->pdev->device == 0x6610))) ||
-+				    ((adev->pdev->revision == 0x83) &&
-+					(adev->pdev->device == 0x6610))) {
-+					info->is_kicker = true;
-+					strcpy(fw_name, "radeon/oland_k_smc.bin");
-+				} else {
-+					strcpy(fw_name, "radeon/oland_smc.bin");
-+				}
-+				break;
-+			case CHIP_HAINAN:
-+				if (((adev->pdev->revision == 0x81) &&
-+					(adev->pdev->device == 0x6660)) ||
-+				    ((adev->pdev->revision == 0x83) &&
-+					((adev->pdev->device == 0x6660) ||
-+					(adev->pdev->device == 0x6663) ||
-+					(adev->pdev->device == 0x6665) ||
-+					 (adev->pdev->device == 0x6667)))) {
-+					info->is_kicker = true;
-+					strcpy(fw_name, "radeon/hainan_k_smc.bin");
-+				} else if ((adev->pdev->revision == 0xc3) &&
-+					 (adev->pdev->device == 0x6665)) {
-+					info->is_kicker = true;
-+					strcpy(fw_name, "radeon/banks_k_2_smc.bin");
-+				} else {
-+					strcpy(fw_name, "radeon/hainan_smc.bin");
-+				}
-+				break;
-+			case CHIP_BONAIRE:
-+				if ((adev->pdev->revision == 0x80) ||
-+					(adev->pdev->revision == 0x81) ||
-+					(adev->pdev->device == 0x665f)) {
-+					info->is_kicker = true;
-+					strcpy(fw_name, "radeon/bonaire_k_smc.bin");
-+				} else {
-+					strcpy(fw_name, "radeon/bonaire_smc.bin");
-+				}
-+				break;
-+			case CHIP_HAWAII:
-+				if (adev->pdev->revision == 0x80) {
-+					info->is_kicker = true;
-+					strcpy(fw_name, "radeon/hawaii_k_smc.bin");
-+				} else {
-+					strcpy(fw_name, "radeon/hawaii_smc.bin");
-+				}
-+				break;
- 			case CHIP_TOPAZ:
- 				if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
- 				    ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
-@@ -838,6 +897,9 @@ static int amdgpu_cgs_query_system_info(
- 	case CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID:
- 		sys_info->value = adev->pdev->subsystem_vendor;
- 		break;
-+	case CGS_SYSTEM_INFO_PCIE_BUS_DEVFN:
-+		sys_info->value = adev->pdev->devfn;
-+		break;
- 	default:
- 		return -ENODEV;
- 	}
-@@ -849,10 +911,6 @@ static int amdgpu_cgs_get_active_display
- 					  struct cgs_display_info *info)
- {
- 	CGS_FUNC_ADEV;
--	struct amdgpu_crtc *amdgpu_crtc;
--	struct drm_device *ddev = adev->ddev;
--	struct drm_crtc *crtc;
--	uint32_t line_time_us, vblank_lines;
- 	struct cgs_mode_info *mode_info;
- 
- 	if (info == NULL)
-@@ -866,30 +924,41 @@ static int amdgpu_cgs_get_active_display
- 		mode_info->ref_clock = adev->clock.spll.reference_freq;
- 	}
- 
--	if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
--		list_for_each_entry(crtc,
--				&ddev->mode_config.crtc_list, head) {
--			amdgpu_crtc = to_amdgpu_crtc(crtc);
--			if (crtc->enabled) {
--				info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
--				info->display_count++;
--			}
--			if (mode_info != NULL &&
--				crtc->enabled && amdgpu_crtc->enabled &&
--				amdgpu_crtc->hw_mode.clock) {
--				line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
--							amdgpu_crtc->hw_mode.clock;
--				vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
--							amdgpu_crtc->hw_mode.crtc_vdisplay +
--							(amdgpu_crtc->v_border * 2);
--				mode_info->vblank_time_us = vblank_lines * line_time_us;
--				mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
--				mode_info->ref_clock = adev->clock.spll.reference_freq;
--				mode_info = NULL;
-+	if (!amdgpu_device_has_dc_support(adev)) {
-+		struct amdgpu_crtc *amdgpu_crtc;
-+		struct drm_device *ddev = adev->ddev;
-+		struct drm_crtc *crtc;
-+		uint32_t line_time_us, vblank_lines;
-+
-+		if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
-+			list_for_each_entry(crtc,
-+					&ddev->mode_config.crtc_list, head) {
-+				amdgpu_crtc = to_amdgpu_crtc(crtc);
-+				if (crtc->enabled) {
-+					info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
-+					info->display_count++;
-+				}
-+				if (mode_info != NULL &&
-+					crtc->enabled && amdgpu_crtc->enabled &&
-+					amdgpu_crtc->hw_mode.clock) {
-+					line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
-+								amdgpu_crtc->hw_mode.clock;
-+					vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
-+								amdgpu_crtc->hw_mode.crtc_vdisplay +
-+								(amdgpu_crtc->v_border * 2);
-+					mode_info->vblank_time_us = vblank_lines * line_time_us;
-+					mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
-+					mode_info = NULL;
-+				}
- 			}
- 		}
-+	} else {
-+		info->display_count = adev->pm.pm_display_cfg.num_display;
-+		if (mode_info != NULL) {
-+			mode_info->vblank_time_us = adev->pm.pm_display_cfg.min_vblank_time;
-+			mode_info->refresh_rate = adev->pm.pm_display_cfg.vrefresh;
-+		}
- 	}
--
- 	return 0;
- }
- 
-@@ -1139,6 +1208,7 @@ static const struct cgs_ops amdgpu_cgs_o
- 	.is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
- 	.enter_safe_mode = amdgpu_cgs_enter_safe_mode,
- 	.lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
-+	.register_pp_handle = amdgpu_cgs_register_pp_handle,
- };
- 
- static const struct cgs_os_ops amdgpu_cgs_os_ops = {
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c	2017-12-14 06:39:58.376903540 +0100
-@@ -231,7 +231,7 @@ amdgpu_connector_update_scratch_regs(str
- 		if (connector->encoder_ids[i] == 0)
- 			break;
- 
--		encoder = drm_encoder_find(connector->dev,
-+		encoder = drm_encoder_find(connector->dev, NULL,
- 					connector->encoder_ids[i]);
- 		if (!encoder)
- 			continue;
-@@ -256,7 +256,7 @@ amdgpu_connector_find_encoder(struct drm
- 	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
- 		if (connector->encoder_ids[i] == 0)
- 			break;
--		encoder = drm_encoder_find(connector->dev,
-+		encoder = drm_encoder_find(connector->dev, NULL,
- 					connector->encoder_ids[i]);
- 		if (!encoder)
- 			continue;
-@@ -346,10 +346,8 @@ static void amdgpu_connector_free_edid(s
- {
- 	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
- 
--	if (amdgpu_connector->edid) {
--		kfree(amdgpu_connector->edid);
--		amdgpu_connector->edid = NULL;
--	}
-+	kfree(amdgpu_connector->edid);
-+	amdgpu_connector->edid = NULL;
- }
- 
- static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
-@@ -374,7 +372,7 @@ amdgpu_connector_best_single_encoder(str
- 
- 	/* pick the encoder ids */
- 	if (enc_id)
--		return drm_encoder_find(connector->dev, enc_id);
-+		return drm_encoder_find(connector->dev, NULL, enc_id);
- 	return NULL;
- }
- 
-@@ -1079,7 +1077,7 @@ amdgpu_connector_dvi_detect(struct drm_c
- 			if (connector->encoder_ids[i] == 0)
- 				break;
- 
--			encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
-+			encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
- 			if (!encoder)
- 				continue;
- 
-@@ -1136,7 +1134,7 @@ amdgpu_connector_dvi_encoder(struct drm_
- 		if (connector->encoder_ids[i] == 0)
- 			break;
- 
--		encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
-+		encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
- 		if (!encoder)
- 			continue;
- 
-@@ -1155,7 +1153,7 @@ amdgpu_connector_dvi_encoder(struct drm_
- 	/* then check use digitial */
- 	/* pick the first one */
- 	if (enc_id)
--		return drm_encoder_find(connector->dev, enc_id);
-+		return drm_encoder_find(connector->dev, NULL, enc_id);
- 	return NULL;
- }
- 
-@@ -1296,7 +1294,7 @@ u16 amdgpu_connector_encoder_get_dp_brid
- 		if (connector->encoder_ids[i] == 0)
- 			break;
- 
--		encoder = drm_encoder_find(connector->dev,
-+		encoder = drm_encoder_find(connector->dev, NULL,
- 					connector->encoder_ids[i]);
- 		if (!encoder)
- 			continue;
-@@ -1325,7 +1323,7 @@ static bool amdgpu_connector_encoder_is_
- 	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
- 		if (connector->encoder_ids[i] == 0)
- 			break;
--		encoder = drm_encoder_find(connector->dev,
-+		encoder = drm_encoder_find(connector->dev, NULL,
- 					connector->encoder_ids[i]);
- 		if (!encoder)
- 			continue;
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c	2017-12-14 06:39:58.376903540 +0100
-@@ -25,6 +25,7 @@
-  *    Jerome Glisse <glisse@freedesktop.org>
-  */
- #include <linux/pagemap.h>
-+#include <linux/sync_file.h>
- #include <drm/drmP.h>
- #include <drm/amdgpu_drm.h>
- #include <drm/drm_syncobj.h>
-@@ -89,12 +90,20 @@ static int amdgpu_cs_parser_init(struct
- 		goto free_chunk;
- 	}
- 
-+	/* skip guilty context job */
-+	if (atomic_read(&p->ctx->guilty) == 1) {
-+		ret = -ECANCELED;
-+		goto free_chunk;
-+	}
-+
-+	mutex_lock(&p->ctx->lock);
-+
- 	/* get chunks */
- 	chunk_array_user = u64_to_user_ptr(cs->in.chunks);
- 	if (copy_from_user(chunk_array, chunk_array_user,
- 			   sizeof(uint64_t)*cs->in.num_chunks)) {
- 		ret = -EFAULT;
--		goto put_ctx;
-+		goto free_chunk;
- 	}
- 
- 	p->nchunks = cs->in.num_chunks;
-@@ -102,7 +111,7 @@ static int amdgpu_cs_parser_init(struct
- 			    GFP_KERNEL);
- 	if (!p->chunks) {
- 		ret = -ENOMEM;
--		goto put_ctx;
-+		goto free_chunk;
- 	}
- 
- 	for (i = 0; i < p->nchunks; i++) {
-@@ -169,6 +178,11 @@ static int amdgpu_cs_parser_init(struct
- 	if (ret)
- 		goto free_all_kdata;
- 
-+	if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
-+		ret = -ECANCELED;
-+		goto free_all_kdata;
-+	}
-+
- 	if (p->uf_entry.robj)
- 		p->job->uf_addr = uf_offset;
- 	kfree(chunk_array);
-@@ -182,8 +196,6 @@ free_partial_kdata:
- 	kfree(p->chunks);
- 	p->chunks = NULL;
- 	p->nchunks = 0;
--put_ctx:
--	amdgpu_ctx_put(p->ctx);
- free_chunk:
- 	kfree(chunk_array);
- 
-@@ -473,11 +485,16 @@ static int amdgpu_cs_list_validate(struc
- 			return -EPERM;
- 
- 		/* Check if we have user pages and nobody bound the BO already */
--		if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
--			size_t size = sizeof(struct page *);
--
--			size *= bo->tbo.ttm->num_pages;
--			memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
-+		if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
-+		    lobj->user_pages) {
-+			amdgpu_ttm_placement_from_domain(bo,
-+							 AMDGPU_GEM_DOMAIN_CPU);
-+			r = ttm_bo_validate(&bo->tbo, &bo->placement, true,
-+					    false);
-+			if (r)
-+				return r;
-+			amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
-+						     lobj->user_pages);
- 			binding_userptr = true;
- 		}
- 
-@@ -502,7 +519,6 @@ static int amdgpu_cs_parser_bos(struct a
- 	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
- 	struct amdgpu_bo_list_entry *e;
- 	struct list_head duplicates;
--	bool need_mmap_lock = false;
- 	unsigned i, tries = 10;
- 	int r;
- 
-@@ -510,9 +526,9 @@ static int amdgpu_cs_parser_bos(struct a
- 
- 	p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
- 	if (p->bo_list) {
--		need_mmap_lock = p->bo_list->first_userptr !=
--			p->bo_list->num_entries;
- 		amdgpu_bo_list_get_list(p->bo_list, &p->validated);
-+		if (p->bo_list->first_userptr != p->bo_list->num_entries)
-+			p->mn = amdgpu_mn_get(p->adev);
- 	}
- 
- 	INIT_LIST_HEAD(&duplicates);
-@@ -521,9 +537,6 @@ static int amdgpu_cs_parser_bos(struct a
- 	if (p->uf_entry.robj)
- 		list_add(&p->uf_entry.tv.head, &p->validated);
- 
--	if (need_mmap_lock)
--		down_read(&current->mm->mmap_sem);
--
- 	while (1) {
- 		struct list_head need_pages;
- 		unsigned i;
-@@ -543,23 +556,25 @@ static int amdgpu_cs_parser_bos(struct a
- 		INIT_LIST_HEAD(&need_pages);
- 		for (i = p->bo_list->first_userptr;
- 		     i < p->bo_list->num_entries; ++i) {
-+			struct amdgpu_bo *bo;
- 
- 			e = &p->bo_list->array[i];
-+			bo = e->robj;
- 
--			if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
-+			if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm,
- 				 &e->user_invalidated) && e->user_pages) {
- 
- 				/* We acquired a page array, but somebody
- 				 * invalidated it. Free it and try again
- 				 */
- 				release_pages(e->user_pages,
--					      e->robj->tbo.ttm->num_pages,
-+					      bo->tbo.ttm->num_pages,
- 					      false);
- 				kvfree(e->user_pages);
- 				e->user_pages = NULL;
- 			}
- 
--			if (e->robj->tbo.ttm->state != tt_bound &&
-+			if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
- 			    !e->user_pages) {
- 				list_del(&e->tv.head);
- 				list_add(&e->tv.head, &need_pages);
-@@ -636,9 +651,6 @@ static int amdgpu_cs_parser_bos(struct a
- 
- 	amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
- 				     p->bytes_moved_vis);
--	fpriv->vm.last_eviction_counter =
--		atomic64_read(&p->adev->num_evictions);
--
- 	if (p->bo_list) {
- 		struct amdgpu_bo *gds = p->bo_list->gds_obj;
- 		struct amdgpu_bo *gws = p->bo_list->gws_obj;
-@@ -669,7 +681,7 @@ static int amdgpu_cs_parser_bos(struct a
- 	if (!r && p->uf_entry.robj) {
- 		struct amdgpu_bo *uf = p->uf_entry.robj;
- 
--		r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem);
-+		r = amdgpu_ttm_alloc_gart(&uf->tbo);
- 		p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
- 	}
- 
-@@ -679,9 +691,6 @@ error_validate:
- 
- error_free_pages:
- 
--	if (need_mmap_lock)
--		up_read(&current->mm->mmap_sem);
--
- 	if (p->bo_list) {
- 		for (i = p->bo_list->first_userptr;
- 		     i < p->bo_list->num_entries; ++i) {
-@@ -707,7 +716,8 @@ static int amdgpu_cs_sync_rings(struct a
- 
- 	list_for_each_entry(e, &p->validated, tv.head) {
- 		struct reservation_object *resv = e->robj->tbo.resv;
--		r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
-+		r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
-+				     amdgpu_bo_explicit_sync(e->robj));
- 
- 		if (r)
- 			return r;
-@@ -728,11 +738,7 @@ static void amdgpu_cs_parser_fini(struct
- {
- 	unsigned i;
- 
--	if (!error)
--		ttm_eu_fence_buffer_objects(&parser->ticket,
--					    &parser->validated,
--					    parser->fence);
--	else if (backoff)
-+	if (error && backoff)
- 		ttm_eu_backoff_reservation(&parser->ticket,
- 					   &parser->validated);
- 
-@@ -742,8 +748,10 @@ static void amdgpu_cs_parser_fini(struct
- 
- 	dma_fence_put(parser->fence);
- 
--	if (parser->ctx)
-+	if (parser->ctx) {
-+		mutex_unlock(&parser->ctx->lock);
- 		amdgpu_ctx_put(parser->ctx);
-+	}
- 	if (parser->bo_list)
- 		amdgpu_bo_list_put(parser->bo_list);
- 
-@@ -768,10 +776,6 @@ static int amdgpu_bo_vm_update_pte(struc
- 	if (r)
- 		return r;
- 
--	r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_dir_update);
--	if (r)
--		return r;
--
- 	r = amdgpu_vm_clear_freed(adev, vm, NULL);
- 	if (r)
- 		return r;
-@@ -825,7 +829,13 @@ static int amdgpu_bo_vm_update_pte(struc
- 
- 	}
- 
--	r = amdgpu_vm_clear_moved(adev, vm, &p->job->sync);
-+	r = amdgpu_vm_handle_moved(adev, vm);
-+	if (r)
-+		return r;
-+
-+	r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update);
-+	if (r)
-+		return r;
- 
- 	if (amdgpu_vm_debug && p->bo_list) {
- 		/* Invalidate all BOs to test for userspace bugs */
-@@ -835,7 +845,7 @@ static int amdgpu_bo_vm_update_pte(struc
- 			if (!bo)
- 				continue;
- 
--			amdgpu_vm_bo_invalidate(adev, bo);
-+			amdgpu_vm_bo_invalidate(adev, bo, false);
- 		}
- 	}
- 
-@@ -848,19 +858,63 @@ static int amdgpu_cs_ib_vm_chunk(struct
- 	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
- 	struct amdgpu_vm *vm = &fpriv->vm;
- 	struct amdgpu_ring *ring = p->job->ring;
--	int i, r;
-+	int r;
- 
- 	/* Only for UVD/VCE VM emulation */
--	if (ring->funcs->parse_cs) {
--		for (i = 0; i < p->job->num_ibs; i++) {
--			r = amdgpu_ring_parse_cs(ring, p, i);
-+	if (p->job->ring->funcs->parse_cs) {
-+		unsigned i, j;
-+
-+		for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
-+			struct drm_amdgpu_cs_chunk_ib *chunk_ib;
-+			struct amdgpu_bo_va_mapping *m;
-+			struct amdgpu_bo *aobj = NULL;
-+			struct amdgpu_cs_chunk *chunk;
-+			struct amdgpu_ib *ib;
-+			uint64_t offset;
-+			uint8_t *kptr;
-+
-+			chunk = &p->chunks[i];
-+			ib = &p->job->ibs[j];
-+			chunk_ib = chunk->kdata;
-+
-+			if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
-+				continue;
-+
-+			r = amdgpu_cs_find_mapping(p, chunk_ib->va_start,
-+						   &aobj, &m);
-+			if (r) {
-+				DRM_ERROR("IB va_start is invalid\n");
-+				return r;
-+			}
-+
-+			if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
-+			    (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
-+				DRM_ERROR("IB va_start+ib_bytes is invalid\n");
-+				return -EINVAL;
-+			}
-+
-+			/* the IB should be reserved at this point */
-+			r = amdgpu_bo_kmap(aobj, (void **)&kptr);
-+			if (r) {
-+				return r;
-+			}
-+
-+			offset = m->start * AMDGPU_GPU_PAGE_SIZE;
-+			kptr += chunk_ib->va_start - offset;
-+
-+			memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
-+			amdgpu_bo_kunmap(aobj);
-+
-+			r = amdgpu_ring_parse_cs(ring, p, j);
- 			if (r)
- 				return r;
-+
-+			j++;
- 		}
- 	}
- 
- 	if (p->job->vm) {
--		p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.bo);
-+		p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
- 
- 		r = amdgpu_bo_vm_update_pte(p);
- 		if (r)
-@@ -922,54 +976,18 @@ static int amdgpu_cs_ib_fill(struct amdg
- 
- 		parser->job->ring = ring;
- 
--		if (ring->funcs->parse_cs) {
--			struct amdgpu_bo_va_mapping *m;
--			struct amdgpu_bo *aobj = NULL;
--			uint64_t offset;
--			uint8_t *kptr;
--
--			m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
--						   &aobj);
--			if (!aobj) {
--				DRM_ERROR("IB va_start is invalid\n");
--				return -EINVAL;
--			}
--
--			if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
--			    (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
--				DRM_ERROR("IB va_start+ib_bytes is invalid\n");
--				return -EINVAL;
--			}
--
--			/* the IB should be reserved at this point */
--			r = amdgpu_bo_kmap(aobj, (void **)&kptr);
--			if (r) {
--				return r;
--			}
--
--			offset = m->start * AMDGPU_GPU_PAGE_SIZE;
--			kptr += chunk_ib->va_start - offset;
--
--			r =  amdgpu_ib_get(adev, vm, chunk_ib->ib_bytes, ib);
--			if (r) {
--				DRM_ERROR("Failed to get ib !\n");
--				return r;
--			}
--
--			memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
--			amdgpu_bo_kunmap(aobj);
--		} else {
--			r =  amdgpu_ib_get(adev, vm, 0, ib);
--			if (r) {
--				DRM_ERROR("Failed to get ib !\n");
--				return r;
--			}
--
-+		r =  amdgpu_ib_get(adev, vm,
-+					ring->funcs->parse_cs ? chunk_ib->ib_bytes : 0,
-+					ib);
-+		if (r) {
-+			DRM_ERROR("Failed to get ib !\n");
-+			return r;
- 		}
- 
- 		ib->gpu_addr = chunk_ib->va_start;
- 		ib->length_dw = chunk_ib->ib_bytes / 4;
- 		ib->flags = chunk_ib->flags;
-+
- 		j++;
- 	}
- 
-@@ -979,7 +997,7 @@ static int amdgpu_cs_ib_fill(struct amdg
- 	    parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
- 		return -EINVAL;
- 
--	return 0;
-+	return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->job->ring->idx);
- }
- 
- static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
-@@ -1019,7 +1037,7 @@ static int amdgpu_cs_process_fence_dep(s
- 			amdgpu_ctx_put(ctx);
- 			return r;
- 		} else if (fence) {
--			r = amdgpu_sync_fence(p->adev, &p->job->sync,
-+			r = amdgpu_sync_fence(p->adev, &p->job->dep_sync,
- 					      fence);
- 			dma_fence_put(fence);
- 			amdgpu_ctx_put(ctx);
-@@ -1039,7 +1057,7 @@ static int amdgpu_syncobj_lookup_and_add
- 	if (r)
- 		return r;
- 
--	r = amdgpu_sync_fence(p->adev, &p->job->sync, fence);
-+	r = amdgpu_sync_fence(p->adev, &p->job->dep_sync, fence);
- 	dma_fence_put(fence);
- 
- 	return r;
-@@ -1133,14 +1151,31 @@ static int amdgpu_cs_submit(struct amdgp
- 	struct amdgpu_ring *ring = p->job->ring;
- 	struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
- 	struct amdgpu_job *job;
-+	unsigned i;
-+	uint64_t seq;
-+
- 	int r;
- 
-+	amdgpu_mn_lock(p->mn);
-+	if (p->bo_list) {
-+		for (i = p->bo_list->first_userptr;
-+		     i < p->bo_list->num_entries; ++i) {
-+			struct amdgpu_bo *bo = p->bo_list->array[i].robj;
-+
-+			if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) {
-+				amdgpu_mn_unlock(p->mn);
-+				return -ERESTARTSYS;
-+			}
-+		}
-+	}
-+
- 	job = p->job;
- 	p->job = NULL;
- 
- 	r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
- 	if (r) {
- 		amdgpu_job_free(job);
-+		amdgpu_mn_unlock(p->mn);
- 		return r;
- 	}
- 
-@@ -1148,21 +1183,35 @@ static int amdgpu_cs_submit(struct amdgp
- 	job->fence_ctx = entity->fence_context;
- 	p->fence = dma_fence_get(&job->base.s_fence->finished);
- 
-+	r = amdgpu_ctx_add_fence(p->ctx, ring, p->fence, &seq);
-+	if (r) {
-+		dma_fence_put(p->fence);
-+		dma_fence_put(&job->base.s_fence->finished);
-+		amdgpu_job_free(job);
-+		amdgpu_mn_unlock(p->mn);
-+		return r;
-+	}
-+
- 	amdgpu_cs_post_dependencies(p);
- 
--	cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
--	job->uf_sequence = cs->out.handle;
-+	cs->out.handle = seq;
-+	job->uf_sequence = seq;
-+
- 	amdgpu_job_free_resources(job);
-+	amdgpu_ring_priority_get(job->ring, job->base.s_priority);
- 
- 	trace_amdgpu_cs_ioctl(job);
--	amd_sched_entity_push_job(&job->base);
-+	amd_sched_entity_push_job(&job->base, entity);
-+
-+	ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
-+	amdgpu_mn_unlock(p->mn);
-+
- 	return 0;
- }
- 
- int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
- {
- 	struct amdgpu_device *adev = dev->dev_private;
--	struct amdgpu_fpriv *fpriv = filp->driver_priv;
- 	union drm_amdgpu_cs *cs = data;
- 	struct amdgpu_cs_parser parser = {};
- 	bool reserved_buffers = false;
-@@ -1170,8 +1219,6 @@ int amdgpu_cs_ioctl(struct drm_device *d
- 
- 	if (!adev->accel_working)
- 		return -EBUSY;
--	if (amdgpu_kms_vram_lost(adev, fpriv))
--		return -ENODEV;
- 
- 	parser.adev = adev;
- 	parser.filp = filp;
-@@ -1182,6 +1229,10 @@ int amdgpu_cs_ioctl(struct drm_device *d
- 		goto out;
- 	}
- 
-+	r = amdgpu_cs_ib_fill(adev, &parser);
-+	if (r)
-+		goto out;
-+
- 	r = amdgpu_cs_parser_bos(&parser, data);
- 	if (r) {
- 		if (r == -ENOMEM)
-@@ -1192,9 +1243,6 @@ int amdgpu_cs_ioctl(struct drm_device *d
- 	}
- 
- 	reserved_buffers = true;
--	r = amdgpu_cs_ib_fill(adev, &parser);
--	if (r)
--		goto out;
- 
- 	r = amdgpu_cs_dependencies(adev, &parser);
- 	if (r) {
-@@ -1230,16 +1278,12 @@ int amdgpu_cs_wait_ioctl(struct drm_devi
- {
- 	union drm_amdgpu_wait_cs *wait = data;
- 	struct amdgpu_device *adev = dev->dev_private;
--	struct amdgpu_fpriv *fpriv = filp->driver_priv;
- 	unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
- 	struct amdgpu_ring *ring = NULL;
- 	struct amdgpu_ctx *ctx;
- 	struct dma_fence *fence;
- 	long r;
- 
--	if (amdgpu_kms_vram_lost(adev, fpriv))
--		return -ENODEV;
--
- 	ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
- 	if (ctx == NULL)
- 		return -EINVAL;
-@@ -1257,6 +1301,8 @@ int amdgpu_cs_wait_ioctl(struct drm_devi
- 		r = PTR_ERR(fence);
- 	else if (fence) {
- 		r = dma_fence_wait_timeout(fence, true, timeout);
-+		if (r > 0 && fence->error)
-+			r = fence->error;
- 		dma_fence_put(fence);
- 	} else
- 		r = 1;
-@@ -1304,6 +1350,62 @@ static struct dma_fence *amdgpu_cs_get_f
- 	return fence;
- }
- 
-+int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
-+				    struct drm_file *filp)
-+{
-+	struct amdgpu_device *adev = dev->dev_private;
-+	union drm_amdgpu_fence_to_handle *info = data;
-+	struct dma_fence *fence;
-+	struct drm_syncobj *syncobj;
-+	struct sync_file *sync_file;
-+	int fd, r;
-+
-+	fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
-+	if (IS_ERR(fence))
-+		return PTR_ERR(fence);
-+
-+	switch (info->in.what) {
-+	case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
-+		r = drm_syncobj_create(&syncobj, 0, fence);
-+		dma_fence_put(fence);
-+		if (r)
-+			return r;
-+		r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
-+		drm_syncobj_put(syncobj);
-+		return r;
-+
-+	case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
-+		r = drm_syncobj_create(&syncobj, 0, fence);
-+		dma_fence_put(fence);
-+		if (r)
-+			return r;
-+		r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
-+		drm_syncobj_put(syncobj);
-+		return r;
-+
-+	case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
-+		fd = get_unused_fd_flags(O_CLOEXEC);
-+		if (fd < 0) {
-+			dma_fence_put(fence);
-+			return fd;
-+		}
-+
-+		sync_file = sync_file_create(fence);
-+		dma_fence_put(fence);
-+		if (!sync_file) {
-+			put_unused_fd(fd);
-+			return -ENOMEM;
-+		}
-+
-+		fd_install(fd, sync_file->file);
-+		info->out.handle = fd;
-+		return 0;
-+
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
- /**
-  * amdgpu_cs_wait_all_fence - wait on all fences to signal
-  *
-@@ -1338,6 +1440,9 @@ static int amdgpu_cs_wait_all_fences(str
- 
- 		if (r == 0)
- 			break;
-+
-+		if (fence->error)
-+			return fence->error;
- 	}
- 
- 	memset(wait, 0, sizeof(*wait));
-@@ -1383,6 +1488,7 @@ static int amdgpu_cs_wait_any_fence(stru
- 			array[i] = fence;
- 		} else { /* NULL, the fence has been already signaled */
- 			r = 1;
-+			first = i;
- 			goto out;
- 		}
- 	}
-@@ -1396,8 +1502,11 @@ out:
- 	memset(wait, 0, sizeof(*wait));
- 	wait->out.status = (r > 0);
- 	wait->out.first_signaled = first;
--	/* set return value 0 to indicate success */
--	r = 0;
-+
-+	if (first < fence_count && array[first])
-+		r = array[first]->error;
-+	else
-+		r = 0;
- 
- err_free_fence_array:
- 	for (i = 0; i < fence_count; i++)
-@@ -1418,15 +1527,12 @@ int amdgpu_cs_wait_fences_ioctl(struct d
- 				struct drm_file *filp)
- {
- 	struct amdgpu_device *adev = dev->dev_private;
--	struct amdgpu_fpriv *fpriv = filp->driver_priv;
- 	union drm_amdgpu_wait_fences *wait = data;
- 	uint32_t fence_count = wait->in.fence_count;
- 	struct drm_amdgpu_fence *fences_user;
- 	struct drm_amdgpu_fence *fences;
- 	int r;
- 
--	if (amdgpu_kms_vram_lost(adev, fpriv))
--		return -ENODEV;
- 	/* Get the fences from userspace */
- 	fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
- 			GFP_KERNEL);
-@@ -1462,78 +1568,36 @@ err_free_fences:
-  * virtual memory address. Returns allocation structure when found, NULL
-  * otherwise.
-  */
--struct amdgpu_bo_va_mapping *
--amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
--		       uint64_t addr, struct amdgpu_bo **bo)
-+int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
-+			   uint64_t addr, struct amdgpu_bo **bo,
-+			   struct amdgpu_bo_va_mapping **map)
- {
-+	struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
-+	struct amdgpu_vm *vm = &fpriv->vm;
- 	struct amdgpu_bo_va_mapping *mapping;
--	unsigned i;
--
--	if (!parser->bo_list)
--		return NULL;
--
--	addr /= AMDGPU_GPU_PAGE_SIZE;
--
--	for (i = 0; i < parser->bo_list->num_entries; i++) {
--		struct amdgpu_bo_list_entry *lobj;
--
--		lobj = &parser->bo_list->array[i];
--		if (!lobj->bo_va)
--			continue;
--
--		list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
--			if (mapping->start > addr ||
--			    addr > mapping->last)
--				continue;
--
--			*bo = lobj->bo_va->base.bo;
--			return mapping;
--		}
--
--		list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
--			if (mapping->start > addr ||
--			    addr > mapping->last)
--				continue;
--
--			*bo = lobj->bo_va->base.bo;
--			return mapping;
--		}
--	}
--
--	return NULL;
--}
--
--/**
-- * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM
-- *
-- * @parser: command submission parser context
-- *
-- * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM.
-- */
--int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser)
--{
--	unsigned i;
- 	int r;
- 
--	if (!parser->bo_list)
--		return 0;
-+	addr /= AMDGPU_GPU_PAGE_SIZE;
- 
--	for (i = 0; i < parser->bo_list->num_entries; i++) {
--		struct amdgpu_bo *bo = parser->bo_list->array[i].robj;
-+	mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
-+	if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
-+		return -EINVAL;
- 
--		r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
--		if (unlikely(r))
--			return r;
-+	*bo = mapping->bo_va->base.bo;
-+	*map = mapping;
- 
--		if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
--			continue;
-+	/* Double check that the BO is reserved by this CS */
-+	if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
-+		return -EINVAL;
- 
--		bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
--		amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains);
--		r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
--		if (unlikely(r))
-+	if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
-+		(*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
-+		amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains);
-+		r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, false,
-+				    false);
-+		if (r)
- 			return r;
- 	}
- 
--	return 0;
-+	return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
- }
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c	2017-12-14 06:39:58.377903541 +0100
-@@ -23,13 +23,41 @@
-  */
- 
- #include <drm/drmP.h>
-+#include <drm/drm_auth.h>
- #include "amdgpu.h"
-+#include "amdgpu_sched.h"
- 
--static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx)
-+static int amdgpu_ctx_priority_permit(struct drm_file *filp,
-+				      enum amd_sched_priority priority)
-+{
-+	/* NORMAL and below are accessible by everyone */
-+	if (priority <= AMD_SCHED_PRIORITY_NORMAL)
-+		return 0;
-+
-+	if (capable(CAP_SYS_NICE))
-+		return 0;
-+
-+	if (drm_is_current_master(filp))
-+		return 0;
-+
-+	return -EACCES;
-+}
-+
-+static int amdgpu_ctx_init(struct amdgpu_device *adev,
-+			   enum amd_sched_priority priority,
-+			   struct drm_file *filp,
-+			   struct amdgpu_ctx *ctx)
- {
- 	unsigned i, j;
- 	int r;
- 
-+	if (priority < 0 || priority >= AMD_SCHED_PRIORITY_MAX)
-+		return -EINVAL;
-+
-+	r = amdgpu_ctx_priority_permit(filp, priority);
-+	if (r)
-+		return r;
-+
- 	memset(ctx, 0, sizeof(*ctx));
- 	ctx->adev = adev;
- 	kref_init(&ctx->refcount);
-@@ -39,25 +67,31 @@ static int amdgpu_ctx_init(struct amdgpu
- 	if (!ctx->fences)
- 		return -ENOMEM;
- 
-+	mutex_init(&ctx->lock);
-+
- 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
- 		ctx->rings[i].sequence = 1;
- 		ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i];
- 	}
- 
- 	ctx->reset_counter = atomic_read(&adev->gpu_reset_counter);
-+	ctx->reset_counter_query = ctx->reset_counter;
-+	ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
-+	ctx->init_priority = priority;
-+	ctx->override_priority = AMD_SCHED_PRIORITY_UNSET;
- 
- 	/* create context entity for each ring */
- 	for (i = 0; i < adev->num_rings; i++) {
- 		struct amdgpu_ring *ring = adev->rings[i];
- 		struct amd_sched_rq *rq;
- 
--		rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
-+		rq = &ring->sched.sched_rq[priority];
- 
- 		if (ring == &adev->gfx.kiq.ring)
- 			continue;
- 
- 		r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity,
--					  rq, amdgpu_sched_jobs);
-+					  rq, amdgpu_sched_jobs, &ctx->guilty);
- 		if (r)
- 			goto failed;
- 	}
-@@ -96,10 +130,14 @@ static void amdgpu_ctx_fini(struct amdgp
- 				      &ctx->rings[i].entity);
- 
- 	amdgpu_queue_mgr_fini(adev, &ctx->queue_mgr);
-+
-+	mutex_destroy(&ctx->lock);
- }
- 
- static int amdgpu_ctx_alloc(struct amdgpu_device *adev,
- 			    struct amdgpu_fpriv *fpriv,
-+			    struct drm_file *filp,
-+			    enum amd_sched_priority priority,
- 			    uint32_t *id)
- {
- 	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
-@@ -117,8 +155,9 @@ static int amdgpu_ctx_alloc(struct amdgp
- 		kfree(ctx);
- 		return r;
- 	}
-+
- 	*id = (uint32_t)r;
--	r = amdgpu_ctx_init(adev, ctx);
-+	r = amdgpu_ctx_init(adev, priority, filp, ctx);
- 	if (r) {
- 		idr_remove(&mgr->ctx_handles, *id);
- 		*id = 0;
-@@ -178,11 +217,45 @@ static int amdgpu_ctx_query(struct amdgp
- 	/* determine if a GPU reset has occured since the last call */
- 	reset_counter = atomic_read(&adev->gpu_reset_counter);
- 	/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
--	if (ctx->reset_counter == reset_counter)
-+	if (ctx->reset_counter_query == reset_counter)
- 		out->state.reset_status = AMDGPU_CTX_NO_RESET;
- 	else
- 		out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
--	ctx->reset_counter = reset_counter;
-+	ctx->reset_counter_query = reset_counter;
-+
-+	mutex_unlock(&mgr->lock);
-+	return 0;
-+}
-+
-+static int amdgpu_ctx_query2(struct amdgpu_device *adev,
-+	struct amdgpu_fpriv *fpriv, uint32_t id,
-+	union drm_amdgpu_ctx_out *out)
-+{
-+	struct amdgpu_ctx *ctx;
-+	struct amdgpu_ctx_mgr *mgr;
-+
-+	if (!fpriv)
-+		return -EINVAL;
-+
-+	mgr = &fpriv->ctx_mgr;
-+	mutex_lock(&mgr->lock);
-+	ctx = idr_find(&mgr->ctx_handles, id);
-+	if (!ctx) {
-+		mutex_unlock(&mgr->lock);
-+		return -EINVAL;
-+	}
-+
-+	out->state.flags = 0x0;
-+	out->state.hangs = 0x0;
-+
-+	if (ctx->reset_counter != atomic_read(&adev->gpu_reset_counter))
-+		out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET;
-+
-+	if (ctx->vram_lost_counter != atomic_read(&adev->vram_lost_counter))
-+		out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST;
-+
-+	if (atomic_read(&ctx->guilty))
-+		out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
- 
- 	mutex_unlock(&mgr->lock);
- 	return 0;
-@@ -193,6 +266,7 @@ int amdgpu_ctx_ioctl(struct drm_device *
- {
- 	int r;
- 	uint32_t id;
-+	enum amd_sched_priority priority;
- 
- 	union drm_amdgpu_ctx *args = data;
- 	struct amdgpu_device *adev = dev->dev_private;
-@@ -200,10 +274,16 @@ int amdgpu_ctx_ioctl(struct drm_device *
- 
- 	r = 0;
- 	id = args->in.ctx_id;
-+	priority = amdgpu_to_sched_priority(args->in.priority);
-+
-+	/* For backwards compatibility reasons, we need to accept
-+	 * ioctls with garbage in the priority field */
-+	if (priority == AMD_SCHED_PRIORITY_INVALID)
-+		priority = AMD_SCHED_PRIORITY_NORMAL;
- 
- 	switch (args->in.op) {
- 	case AMDGPU_CTX_OP_ALLOC_CTX:
--		r = amdgpu_ctx_alloc(adev, fpriv, &id);
-+		r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id);
- 		args->out.alloc.ctx_id = id;
- 		break;
- 	case AMDGPU_CTX_OP_FREE_CTX:
-@@ -212,6 +292,9 @@ int amdgpu_ctx_ioctl(struct drm_device *
- 	case AMDGPU_CTX_OP_QUERY_STATE:
- 		r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
- 		break;
-+	case AMDGPU_CTX_OP_QUERY_STATE2:
-+		r = amdgpu_ctx_query2(adev, fpriv, id, &args->out);
-+		break;
- 	default:
- 		return -EINVAL;
- 	}
-@@ -246,8 +329,8 @@ int amdgpu_ctx_put(struct amdgpu_ctx *ct
- 	return 0;
- }
- 
--uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
--			      struct dma_fence *fence)
-+int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
-+			      struct dma_fence *fence, uint64_t* handler)
- {
- 	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
- 	uint64_t seq = cring->sequence;
-@@ -256,12 +339,8 @@ uint64_t amdgpu_ctx_add_fence(struct amd
- 
- 	idx = seq & (amdgpu_sched_jobs - 1);
- 	other = cring->fences[idx];
--	if (other) {
--		signed long r;
--		r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
--		if (r < 0)
--			DRM_ERROR("Error (%ld) waiting for fence!\n", r);
--	}
-+	if (other)
-+		BUG_ON(!dma_fence_is_signaled(other));
- 
- 	dma_fence_get(fence);
- 
-@@ -271,8 +350,10 @@ uint64_t amdgpu_ctx_add_fence(struct amd
- 	spin_unlock(&ctx->ring_lock);
- 
- 	dma_fence_put(other);
-+	if (handler)
-+		*handler = seq;
- 
--	return seq;
-+	return 0;
- }
- 
- struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
-@@ -303,6 +384,51 @@ struct dma_fence *amdgpu_ctx_get_fence(s
- 	return fence;
- }
- 
-+void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
-+				  enum amd_sched_priority priority)
-+{
-+	int i;
-+	struct amdgpu_device *adev = ctx->adev;
-+	struct amd_sched_rq *rq;
-+	struct amd_sched_entity *entity;
-+	struct amdgpu_ring *ring;
-+	enum amd_sched_priority ctx_prio;
-+
-+	ctx->override_priority = priority;
-+
-+	ctx_prio = (ctx->override_priority == AMD_SCHED_PRIORITY_UNSET) ?
-+			ctx->init_priority : ctx->override_priority;
-+
-+	for (i = 0; i < adev->num_rings; i++) {
-+		ring = adev->rings[i];
-+		entity = &ctx->rings[i].entity;
-+		rq = &ring->sched.sched_rq[ctx_prio];
-+
-+		if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
-+			continue;
-+
-+		amd_sched_entity_set_rq(entity, rq);
-+	}
-+}
-+
-+int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id)
-+{
-+	struct amdgpu_ctx_ring *cring = &ctx->rings[ring_id];
-+	unsigned idx = cring->sequence & (amdgpu_sched_jobs - 1);
-+	struct dma_fence *other = cring->fences[idx];
-+
-+	if (other) {
-+		signed long r;
-+		r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
-+		if (r < 0) {
-+			DRM_ERROR("Error (%ld) waiting for fence!\n", r);
-+			return r;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
- void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
- {
- 	mutex_init(&mgr->lock);
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c	2017-12-14 06:39:58.377903541 +0100
-@@ -31,6 +31,7 @@
- #include <linux/debugfs.h>
- #include <drm/drmP.h>
- #include <drm/drm_crtc_helper.h>
-+#include <drm/drm_atomic_helper.h>
- #include <drm/amdgpu_drm.h>
- #include <linux/vgaarb.h>
- #include <linux/vga_switcheroo.h>
-@@ -56,6 +57,7 @@
- #include "amdgpu_vf_error.h"
- 
- #include "amdgpu_amdkfd.h"
-+#include "amdgpu_pm.h"
- 
- MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
- MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
-@@ -65,6 +67,7 @@ MODULE_FIRMWARE("amdgpu/raven_gpu_info.b
- static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
- static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
- static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev);
-+static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev);
- 
- static const char *amdgpu_asic_name[] = {
- 	"TAHITI",
-@@ -107,10 +110,8 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_de
- {
- 	uint32_t ret;
- 
--	if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
--		BUG_ON(in_interrupt());
-+	if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
- 		return amdgpu_virt_kiq_rreg(adev, reg);
--	}
- 
- 	if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
- 		ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
-@@ -135,10 +136,8 @@ void amdgpu_mm_wreg(struct amdgpu_device
- 		adev->last_mm_index = v;
- 	}
- 
--	if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
--		BUG_ON(in_interrupt());
-+	if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
- 		return amdgpu_virt_kiq_wreg(adev, reg, v);
--	}
- 
- 	if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
- 		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
-@@ -402,6 +401,18 @@ void amdgpu_pci_config_reset(struct amdg
-  */
- static int amdgpu_doorbell_init(struct amdgpu_device *adev)
- {
-+	/* No doorbell on SI hardware generation */
-+	if (adev->asic_type < CHIP_BONAIRE) {
-+		adev->doorbell.base = 0;
-+		adev->doorbell.size = 0;
-+		adev->doorbell.num_doorbells = 0;
-+		adev->doorbell.ptr = NULL;
-+		return 0;
-+	}
-+
-+	if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
-+		return -EINVAL;
-+
- 	/* doorbell bar mapping */
- 	adev->doorbell.base = pci_resource_start(adev->pdev, 2);
- 	adev->doorbell.size = pci_resource_len(adev->pdev, 2);
-@@ -539,7 +550,7 @@ int amdgpu_wb_get(struct amdgpu_device *
- 
- 	if (offset < adev->wb.num_wb) {
- 		__set_bit(offset, adev->wb.used);
--		*wb = offset * 8; /* convert to dw offset */
-+		*wb = offset << 3; /* convert to dw offset */
- 		return 0;
- 	} else {
- 		return -EINVAL;
-@@ -557,7 +568,7 @@ int amdgpu_wb_get(struct amdgpu_device *
- void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
- {
- 	if (wb < adev->wb.num_wb)
--		__clear_bit(wb, adev->wb.used);
-+		__clear_bit(wb >> 3, adev->wb.used);
- }
- 
- /**
-@@ -567,41 +578,13 @@ void amdgpu_wb_free(struct amdgpu_device
-  * @base: base address at which to put VRAM
-  *
-  * Function will try to place VRAM at base address provided
-- * as parameter (which is so far either PCI aperture address or
-- * for IGP TOM base address).
-- *
-- * If there is not enough space to fit the unvisible VRAM in the 32bits
-- * address space then we limit the VRAM size to the aperture.
-- *
-- * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
-- * this shouldn't be a problem as we are using the PCI aperture as a reference.
-- * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
-- * not IGP.
-- *
-- * Note: we use mc_vram_size as on some board we need to program the mc to
-- * cover the whole aperture even if VRAM size is inferior to aperture size
-- * Novell bug 204882 + along with lots of ubuntu ones
-- *
-- * Note: when limiting vram it's safe to overwritte real_vram_size because
-- * we are not in case where real_vram_size is inferior to mc_vram_size (ie
-- * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
-- * ones)
-- *
-- * Note: IGP TOM addr should be the same as the aperture addr, we don't
-- * explicitly check for that though.
-- *
-- * FIXME: when reducing VRAM size align new size on power of 2.
-+ * as parameter.
-  */
- void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
- {
- 	uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
- 
- 	mc->vram_start = base;
--	if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
--		dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
--		mc->real_vram_size = mc->aper_size;
--		mc->mc_vram_size = mc->aper_size;
--	}
- 	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
- 	if (limit && limit < mc->real_vram_size)
- 		mc->real_vram_size = limit;
-@@ -639,7 +622,10 @@ void amdgpu_gart_location(struct amdgpu_
- 			dev_warn(adev->dev, "limiting GTT\n");
- 			mc->gart_size = size_af;
- 		}
--		mc->gart_start = mc->vram_end + 1;
-+		/* VCE doesn't like it when BOs cross a 4GB segment, so align
-+		 * the GART base on a 4GB boundary as well.
-+		 */
-+		mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
- 	}
- 	mc->gart_end = mc->gart_start + mc->gart_size - 1;
- 	dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
-@@ -647,42 +633,185 @@ void amdgpu_gart_location(struct amdgpu_
- }
- 
- /*
-- * GPU helpers function.
-+ * Firmware Reservation functions
-  */
- /**
-- * amdgpu_need_post - check if the hw need post or not
-+ * amdgpu_fw_reserve_vram_fini - free fw reserved vram
-  *
-  * @adev: amdgpu_device pointer
-  *
-- * Check if the asic has been initialized (all asics) at driver startup
-- * or post is needed if  hw reset is performed.
-- * Returns true if need or false if not.
-+ * free fw reserved vram if it has been reserved.
-  */
--bool amdgpu_need_post(struct amdgpu_device *adev)
-+void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev)
- {
--	uint32_t reg;
-+	amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
-+		NULL, &adev->fw_vram_usage.va);
-+}
- 
--	if (adev->has_hw_reset) {
--		adev->has_hw_reset = false;
--		return true;
-+/**
-+ * amdgpu_fw_reserve_vram_init - create bo vram reservation from fw
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * create bo vram reservation from fw.
-+ */
-+int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev)
-+{
-+	int r = 0;
-+	int i;
-+	u64 vram_size = adev->mc.visible_vram_size;
-+	u64 offset = adev->fw_vram_usage.start_offset;
-+	u64 size = adev->fw_vram_usage.size;
-+	struct amdgpu_bo *bo;
-+
-+	adev->fw_vram_usage.va = NULL;
-+	adev->fw_vram_usage.reserved_bo = NULL;
-+
-+	if (adev->fw_vram_usage.size > 0 &&
-+		adev->fw_vram_usage.size <= vram_size) {
-+
-+		r = amdgpu_bo_create(adev, adev->fw_vram_usage.size,
-+			PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
-+			AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
-+			AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0,
-+			&adev->fw_vram_usage.reserved_bo);
-+		if (r)
-+			goto error_create;
-+
-+		r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
-+		if (r)
-+			goto error_reserve;
-+
-+		/* remove the original mem node and create a new one at the
-+		 * request position
-+		 */
-+		bo = adev->fw_vram_usage.reserved_bo;
-+		offset = ALIGN(offset, PAGE_SIZE);
-+		for (i = 0; i < bo->placement.num_placement; ++i) {
-+			bo->placements[i].fpfn = offset >> PAGE_SHIFT;
-+			bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
-+		}
-+
-+		ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
-+		r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem,
-+				     false, false);
-+		if (r)
-+			goto error_pin;
-+
-+		r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
-+			AMDGPU_GEM_DOMAIN_VRAM,
-+			adev->fw_vram_usage.start_offset,
-+			(adev->fw_vram_usage.start_offset +
-+			adev->fw_vram_usage.size), NULL);
-+		if (r)
-+			goto error_pin;
-+		r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
-+			&adev->fw_vram_usage.va);
-+		if (r)
-+			goto error_kmap;
-+
-+		amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
- 	}
-+	return r;
- 
--	/* bios scratch used on CIK+ */
-+error_kmap:
-+	amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
-+error_pin:
-+	amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
-+error_reserve:
-+	amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
-+error_create:
-+	adev->fw_vram_usage.va = NULL;
-+	adev->fw_vram_usage.reserved_bo = NULL;
-+	return r;
-+}
-+
-+/**
-+ * amdgpu_device_resize_fb_bar - try to resize FB BAR
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
-+ * to fail, but if any of the BARs is not accessible after the size we abort
-+ * driver loading by returning -ENODEV.
-+ */
-+int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
-+{
-+	u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size);
-+	u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
-+	struct pci_bus *root;
-+	struct resource *res;
-+	unsigned i;
-+	u16 cmd;
-+	int r;
-+
-+	/* Bypass for VF */
-+	if (amdgpu_sriov_vf(adev))
-+		return 0;
-+
-+	/* Check if the root BUS has 64bit memory resources */
-+	root = adev->pdev->bus;
-+	while (root->parent)
-+		root = root->parent;
-+
-+	pci_bus_for_each_resource(root, res, i) {
-+		if (res && res->flags & IORESOURCE_MEM_64 &&
-+		    res->start > 0x100000000ull)
-+			break;
-+	}
-+
-+	/* Trying to resize is pointless without a root hub window above 4GB */
-+	if (!res)
-+		return 0;
-+
-+	/* Disable memory decoding while we change the BAR addresses and size */
-+	pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
-+	pci_write_config_word(adev->pdev, PCI_COMMAND,
-+			      cmd & ~PCI_COMMAND_MEMORY);
-+
-+	/* Free the VRAM and doorbell BAR, we most likely need to move both. */
-+	amdgpu_doorbell_fini(adev);
- 	if (adev->asic_type >= CHIP_BONAIRE)
--		return amdgpu_atombios_scratch_need_asic_init(adev);
-+		pci_release_resource(adev->pdev, 2);
- 
--	/* check MEM_SIZE for older asics */
--	reg = amdgpu_asic_get_config_memsize(adev);
-+	pci_release_resource(adev->pdev, 0);
- 
--	if ((reg != 0) && (reg != 0xffffffff))
--		return false;
-+	r = pci_resize_resource(adev->pdev, 0, rbar_size);
-+	if (r == -ENOSPC)
-+		DRM_INFO("Not enough PCI address space for a large BAR.");
-+	else if (r && r != -ENOTSUPP)
-+		DRM_ERROR("Problem resizing BAR0 (%d).", r);
- 
--	return true;
-+	pci_assign_unassigned_bus_resources(adev->pdev->bus);
-+
-+	/* When the doorbell or fb BAR isn't available we have no chance of
-+	 * using the device.
-+	 */
-+	r = amdgpu_doorbell_init(adev);
-+	if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
-+		return -ENODEV;
- 
-+	pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
-+
-+	return 0;
- }
- 
--static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
-+/*
-+ * GPU helpers function.
-+ */
-+/**
-+ * amdgpu_need_post - check if the hw need post or not
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Check if the asic has been initialized (all asics) at driver startup
-+ * or post is needed if  hw reset is performed.
-+ * Returns true if need or false if not.
-+ */
-+bool amdgpu_need_post(struct amdgpu_device *adev)
- {
-+	uint32_t reg;
-+
- 	if (amdgpu_sriov_vf(adev))
- 		return false;
- 
-@@ -705,7 +834,23 @@ static bool amdgpu_vpost_needed(struct a
- 				return true;
- 		}
- 	}
--	return amdgpu_need_post(adev);
-+
-+	if (adev->has_hw_reset) {
-+		adev->has_hw_reset = false;
-+		return true;
-+	}
-+
-+	/* bios scratch used on CIK+ */
-+	if (adev->asic_type >= CHIP_BONAIRE)
-+		return amdgpu_atombios_scratch_need_asic_init(adev);
-+
-+	/* check MEM_SIZE for older asics */
-+	reg = amdgpu_asic_get_config_memsize(adev);
-+
-+	if ((reg != 0) && (reg != 0xffffffff))
-+		return false;
-+
-+	return true;
- }
- 
- /**
-@@ -887,6 +1032,20 @@ static uint32_t cail_ioreg_read(struct c
- 	return r;
- }
- 
-+static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
-+						 struct device_attribute *attr,
-+						 char *buf)
-+{
-+	struct drm_device *ddev = dev_get_drvdata(dev);
-+	struct amdgpu_device *adev = ddev->dev_private;
-+	struct atom_context *ctx = adev->mode_info.atom_context;
-+
-+	return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version);
-+}
-+
-+static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
-+		   NULL);
-+
- /**
-  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
-  *
-@@ -906,6 +1065,7 @@ static void amdgpu_atombios_fini(struct
- 	adev->mode_info.atom_context = NULL;
- 	kfree(adev->mode_info.atom_card_info);
- 	adev->mode_info.atom_card_info = NULL;
-+	device_remove_file(adev->dev, &dev_attr_vbios_version);
- }
- 
- /**
-@@ -922,6 +1082,7 @@ static int amdgpu_atombios_init(struct a
- {
- 	struct card_info *atom_card_info =
- 	    kzalloc(sizeof(struct card_info), GFP_KERNEL);
-+	int ret;
- 
- 	if (!atom_card_info)
- 		return -ENOMEM;
-@@ -935,7 +1096,7 @@ static int amdgpu_atombios_init(struct a
- 		atom_card_info->ioreg_read = cail_ioreg_read;
- 		atom_card_info->ioreg_write = cail_ioreg_write;
- 	} else {
--		DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
-+		DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
- 		atom_card_info->ioreg_read = cail_reg_read;
- 		atom_card_info->ioreg_write = cail_reg_write;
- 	}
-@@ -958,6 +1119,13 @@ static int amdgpu_atombios_init(struct a
- 		amdgpu_atombios_scratch_regs_init(adev);
- 		amdgpu_atombios_allocate_fb_scratch(adev);
- 	}
-+
-+	ret = device_create_file(adev->dev, &dev_attr_vbios_version);
-+	if (ret) {
-+		DRM_ERROR("Failed to create device file for VBIOS version\n");
-+		return ret;
-+	}
-+
- 	return 0;
- }
- 
-@@ -1521,10 +1689,12 @@ static int amdgpu_early_init(struct amdg
- 	if (r)
- 		return r;
- 
-+	amdgpu_amdkfd_device_probe(adev);
-+
- 	if (amdgpu_sriov_vf(adev)) {
- 		r = amdgpu_virt_request_full_gpu(adev, true);
- 		if (r)
--			return r;
-+			return -EAGAIN;
- 	}
- 
- 	for (i = 0; i < adev->num_ip_blocks; i++) {
-@@ -1615,6 +1785,11 @@ static int amdgpu_init(struct amdgpu_dev
- 		adev->ip_blocks[i].status.hw = true;
- 	}
- 
-+	amdgpu_amdkfd_device_init(adev);
-+
-+	if (amdgpu_sriov_vf(adev))
-+		amdgpu_virt_release_full_gpu(adev, true);
-+
- 	return 0;
- }
- 
-@@ -1682,6 +1857,7 @@ static int amdgpu_fini(struct amdgpu_dev
- {
- 	int i, r;
- 
-+	amdgpu_amdkfd_device_fini(adev);
- 	/* need to disable SMC first */
- 	for (i = 0; i < adev->num_ip_blocks; i++) {
- 		if (!adev->ip_blocks[i].status.hw)
-@@ -1710,6 +1886,7 @@ static int amdgpu_fini(struct amdgpu_dev
- 		if (!adev->ip_blocks[i].status.hw)
- 			continue;
- 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
-+			amdgpu_free_static_csa(adev);
- 			amdgpu_wb_fini(adev);
- 			amdgpu_vram_scratch_fini(adev);
- 		}
-@@ -1757,10 +1934,9 @@ static int amdgpu_fini(struct amdgpu_dev
- 		adev->ip_blocks[i].status.late_initialized = false;
- 	}
- 
--	if (amdgpu_sriov_vf(adev)) {
--		amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
--		amdgpu_virt_release_full_gpu(adev, false);
--	}
-+	if (amdgpu_sriov_vf(adev))
-+		if (amdgpu_virt_release_full_gpu(adev, false))
-+			DRM_ERROR("failed to release exclusive mode on fini\n");
- 
- 	return 0;
- }
-@@ -1848,6 +2024,7 @@ static int amdgpu_sriov_reinit_late(stru
- 
- 	static enum amd_ip_block_type ip_order[] = {
- 		AMD_IP_BLOCK_TYPE_SMC,
-+		AMD_IP_BLOCK_TYPE_PSP,
- 		AMD_IP_BLOCK_TYPE_DCE,
- 		AMD_IP_BLOCK_TYPE_GFX,
- 		AMD_IP_BLOCK_TYPE_SDMA,
-@@ -1933,16 +2110,67 @@ static int amdgpu_resume(struct amdgpu_d
- 
- static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
- {
--	if (adev->is_atom_fw) {
--		if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
--			adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
--	} else {
--		if (amdgpu_atombios_has_gpu_virtualization_table(adev))
--			adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
-+	if (amdgpu_sriov_vf(adev)) {
-+		if (adev->is_atom_fw) {
-+			if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
-+				adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
-+		} else {
-+			if (amdgpu_atombios_has_gpu_virtualization_table(adev))
-+				adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
-+		}
-+
-+		if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
-+			amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
-+	}
-+}
-+
-+bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
-+{
-+	switch (asic_type) {
-+#if defined(CONFIG_DRM_AMD_DC)
-+	case CHIP_BONAIRE:
-+	case CHIP_HAWAII:
-+	case CHIP_KAVERI:
-+	case CHIP_CARRIZO:
-+	case CHIP_STONEY:
-+	case CHIP_POLARIS11:
-+	case CHIP_POLARIS10:
-+	case CHIP_POLARIS12:
-+	case CHIP_TONGA:
-+	case CHIP_FIJI:
-+#if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
-+		return amdgpu_dc != 0;
-+#endif
-+	case CHIP_KABINI:
-+	case CHIP_MULLINS:
-+		return amdgpu_dc > 0;
-+	case CHIP_VEGA10:
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	case CHIP_RAVEN:
-+#endif
-+		return amdgpu_dc != 0;
-+#endif
-+	default:
-+		return false;
- 	}
- }
- 
- /**
-+ * amdgpu_device_has_dc_support - check if dc is supported
-+ *
-+ * @adev: amdgpu_device_pointer
-+ *
-+ * Returns true for supported, false for not supported
-+ */
-+bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
-+{
-+	if (amdgpu_sriov_vf(adev))
-+		return false;
-+
-+	return amdgpu_device_asic_has_dc_support(adev->asic_type);
-+}
-+
-+/**
-  * amdgpu_device_init - initialize the driver
-  *
-  * @adev: amdgpu_device pointer
-@@ -1979,6 +2207,7 @@ int amdgpu_device_init(struct amdgpu_dev
- 	adev->vm_manager.vm_pte_num_rings = 0;
- 	adev->gart.gart_funcs = NULL;
- 	adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
-+	bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
- 
- 	adev->smc_rreg = &amdgpu_invalid_rreg;
- 	adev->smc_wreg = &amdgpu_invalid_wreg;
-@@ -1995,7 +2224,6 @@ int amdgpu_device_init(struct amdgpu_dev
- 	adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
- 	adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
- 
--
- 	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
- 		 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
- 		 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
-@@ -2007,9 +2235,12 @@ int amdgpu_device_init(struct amdgpu_dev
- 	mutex_init(&adev->pm.mutex);
- 	mutex_init(&adev->gfx.gpu_clock_mutex);
- 	mutex_init(&adev->srbm_mutex);
-+	mutex_init(&adev->gfx.pipe_reserve_mutex);
- 	mutex_init(&adev->grbm_idx_mutex);
- 	mutex_init(&adev->mn_lock);
-+	mutex_init(&adev->virt.vf_errors.lock);
- 	hash_init(adev->mn_hash);
-+	mutex_init(&adev->lock_reset);
- 
- 	amdgpu_check_arguments(adev);
- 
-@@ -2026,9 +2257,6 @@ int amdgpu_device_init(struct amdgpu_dev
- 	INIT_LIST_HEAD(&adev->shadow_list);
- 	mutex_init(&adev->shadow_list_lock);
- 
--	INIT_LIST_HEAD(&adev->gtt_list);
--	spin_lock_init(&adev->gtt_list_lock);
--
- 	INIT_LIST_HEAD(&adev->ring_lru_list);
- 	spin_lock_init(&adev->ring_lru_list_lock);
- 
-@@ -2051,9 +2279,8 @@ int amdgpu_device_init(struct amdgpu_dev
- 	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
- 	DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
- 
--	if (adev->asic_type >= CHIP_BONAIRE)
--		/* doorbell bar mapping */
--		amdgpu_doorbell_init(adev);
-+	/* doorbell bar mapping */
-+	amdgpu_doorbell_init(adev);
- 
- 	/* io port mapping */
- 	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
-@@ -2095,7 +2322,7 @@ int amdgpu_device_init(struct amdgpu_dev
- 	r = amdgpu_atombios_init(adev);
- 	if (r) {
- 		dev_err(adev->dev, "amdgpu_atombios_init failed\n");
--		amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
-+		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
- 		goto failed;
- 	}
- 
-@@ -2103,10 +2330,9 @@ int amdgpu_device_init(struct amdgpu_dev
- 	amdgpu_device_detect_sriov_bios(adev);
- 
- 	/* Post card if necessary */
--	if (amdgpu_vpost_needed(adev)) {
-+	if (amdgpu_need_post(adev)) {
- 		if (!adev->bios) {
- 			dev_err(adev->dev, "no vBIOS found\n");
--			amdgpu_vf_error_put(AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
- 			r = -EINVAL;
- 			goto failed;
- 		}
-@@ -2114,11 +2340,8 @@ int amdgpu_device_init(struct amdgpu_dev
- 		r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
- 		if (r) {
- 			dev_err(adev->dev, "gpu post error!\n");
--			amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_POST_ERROR, 0, 0);
- 			goto failed;
- 		}
--	} else {
--		DRM_INFO("GPU post is not needed\n");
- 	}
- 
- 	if (adev->is_atom_fw) {
-@@ -2126,7 +2349,7 @@ int amdgpu_device_init(struct amdgpu_dev
- 		r = amdgpu_atomfirmware_get_clock_info(adev);
- 		if (r) {
- 			dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
--			amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
-+			amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
- 			goto failed;
- 		}
- 	} else {
-@@ -2134,18 +2357,19 @@ int amdgpu_device_init(struct amdgpu_dev
- 		r = amdgpu_atombios_get_clock_info(adev);
- 		if (r) {
- 			dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
--			amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
-+			amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
- 			goto failed;
- 		}
- 		/* init i2c buses */
--		amdgpu_atombios_i2c_init(adev);
-+		if (!amdgpu_device_has_dc_support(adev))
-+			amdgpu_atombios_i2c_init(adev);
- 	}
- 
- 	/* Fence driver */
- 	r = amdgpu_fence_driver_init(adev);
- 	if (r) {
- 		dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
--		amdgpu_vf_error_put(AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
-+		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
- 		goto failed;
- 	}
- 
-@@ -2154,8 +2378,20 @@ int amdgpu_device_init(struct amdgpu_dev
- 
- 	r = amdgpu_init(adev);
- 	if (r) {
-+		/* failed in exclusive mode due to timeout */
-+		if (amdgpu_sriov_vf(adev) &&
-+		    !amdgpu_sriov_runtime(adev) &&
-+		    amdgpu_virt_mmio_blocked(adev) &&
-+		    !amdgpu_virt_wait_reset(adev)) {
-+			dev_err(adev->dev, "VF exclusive mode timeout\n");
-+			/* Don't send request since VF is inactive. */
-+			adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
-+			adev->virt.ops = NULL;
-+			r = -EAGAIN;
-+			goto failed;
-+		}
- 		dev_err(adev->dev, "amdgpu_init failed\n");
--		amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
-+		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
- 		amdgpu_fini(adev);
- 		goto failed;
- 	}
-@@ -2175,7 +2411,7 @@ int amdgpu_device_init(struct amdgpu_dev
- 	r = amdgpu_ib_pool_init(adev);
- 	if (r) {
- 		dev_err(adev->dev, "IB initialization failed (%d).\n", r);
--		amdgpu_vf_error_put(AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
-+		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
- 		goto failed;
- 	}
- 
-@@ -2183,8 +2419,15 @@ int amdgpu_device_init(struct amdgpu_dev
- 	if (r)
- 		DRM_ERROR("ib ring test failed (%d).\n", r);
- 
-+	if (amdgpu_sriov_vf(adev))
-+		amdgpu_virt_init_data_exchange(adev);
-+
- 	amdgpu_fbdev_init(adev);
- 
-+	r = amdgpu_pm_sysfs_init(adev);
-+	if (r)
-+		DRM_ERROR("registering pm debugfs failed (%d).\n", r);
-+
- 	r = amdgpu_gem_debugfs_init(adev);
- 	if (r)
- 		DRM_ERROR("registering gem debugfs failed (%d).\n", r);
-@@ -2201,6 +2444,10 @@ int amdgpu_device_init(struct amdgpu_dev
- 	if (r)
- 		DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
- 
-+	r = amdgpu_debugfs_vbios_dump_init(adev);
-+	if (r)
-+		DRM_ERROR("Creating vbios dump debugfs failed (%d).\n", r);
-+
- 	if ((amdgpu_testing & 1)) {
- 		if (adev->accel_working)
- 			amdgpu_test_moves(adev);
-@@ -2220,7 +2467,7 @@ int amdgpu_device_init(struct amdgpu_dev
- 	r = amdgpu_late_init(adev);
- 	if (r) {
- 		dev_err(adev->dev, "amdgpu_late_init failed\n");
--		amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
-+		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
- 		goto failed;
- 	}
- 
-@@ -2230,6 +2477,7 @@ failed:
- 	amdgpu_vf_error_trans_all(adev);
- 	if (runtime)
- 		vga_switcheroo_fini_domain_pm_ops(adev->dev);
-+
- 	return r;
- }
- 
-@@ -2262,7 +2510,8 @@ void amdgpu_device_fini(struct amdgpu_de
- 	adev->accel_working = false;
- 	cancel_delayed_work_sync(&adev->late_init_work);
- 	/* free i2c buses */
--	amdgpu_i2c_fini(adev);
-+	if (!amdgpu_device_has_dc_support(adev))
-+		amdgpu_i2c_fini(adev);
- 	amdgpu_atombios_fini(adev);
- 	kfree(adev->bios);
- 	adev->bios = NULL;
-@@ -2276,8 +2525,8 @@ void amdgpu_device_fini(struct amdgpu_de
- 	adev->rio_mem = NULL;
- 	iounmap(adev->rmmio);
- 	adev->rmmio = NULL;
--	if (adev->asic_type >= CHIP_BONAIRE)
--		amdgpu_doorbell_fini(adev);
-+	amdgpu_doorbell_fini(adev);
-+	amdgpu_pm_sysfs_fini(adev);
- 	amdgpu_debugfs_regs_cleanup(adev);
- }
- 
-@@ -2313,12 +2562,14 @@ int amdgpu_device_suspend(struct drm_dev
- 
- 	drm_kms_helper_poll_disable(dev);
- 
--	/* turn off display hw */
--	drm_modeset_lock_all(dev);
--	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
--		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
-+	if (!amdgpu_device_has_dc_support(adev)) {
-+		/* turn off display hw */
-+		drm_modeset_lock_all(dev);
-+		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
-+		}
-+		drm_modeset_unlock_all(dev);
- 	}
--	drm_modeset_unlock_all(dev);
- 
- 	amdgpu_amdkfd_suspend(adev);
- 
-@@ -2426,6 +2677,7 @@ int amdgpu_device_resume(struct drm_devi
- 		DRM_ERROR("amdgpu_resume failed (%d).\n", r);
- 		goto unlock;
- 	}
-+
- 	amdgpu_fence_driver_resume(adev);
- 
- 	if (resume) {
-@@ -2461,13 +2713,25 @@ int amdgpu_device_resume(struct drm_devi
- 
- 	/* blat the mode back in */
- 	if (fbcon) {
--		drm_helper_resume_force_mode(dev);
--		/* turn on display hw */
--		drm_modeset_lock_all(dev);
--		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
--			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
-+		if (!amdgpu_device_has_dc_support(adev)) {
-+			/* pre DCE11 */
-+			drm_helper_resume_force_mode(dev);
-+
-+			/* turn on display hw */
-+			drm_modeset_lock_all(dev);
-+			list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+				drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
-+			}
-+			drm_modeset_unlock_all(dev);
-+		} else {
-+			/*
-+			 * There is no equivalent atomic helper to turn on
-+			 * display, so we defined our own function for this,
-+			 * once suspend resume is supported by the atomic
-+			 * framework this will be reworked
-+			 */
-+			amdgpu_dm_display_resume(adev);
- 		}
--		drm_modeset_unlock_all(dev);
- 	}
- 
- 	drm_kms_helper_poll_enable(dev);
-@@ -2484,7 +2748,10 @@ int amdgpu_device_resume(struct drm_devi
- #ifdef CONFIG_PM
- 	dev->dev->power.disable_depth++;
- #endif
--	drm_helper_hpd_irq_event(dev);
-+	if (!amdgpu_device_has_dc_support(adev))
-+		drm_helper_hpd_irq_event(dev);
-+	else
-+		drm_kms_helper_hotplug_event(dev);
- #ifdef CONFIG_PM
- 	dev->dev->power.disable_depth--;
- #endif
-@@ -2504,6 +2771,9 @@ static bool amdgpu_check_soft_reset(stru
- 	int i;
- 	bool asic_hang = false;
- 
-+	if (amdgpu_sriov_vf(adev))
-+		return true;
-+
- 	for (i = 0; i < adev->num_ip_blocks; i++) {
- 		if (!adev->ip_blocks[i].status.valid)
- 			continue;
-@@ -2546,7 +2816,8 @@ static bool amdgpu_need_full_reset(struc
- 		if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
- 		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
- 		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
--		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) {
-+		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
-+		     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
- 			if (adev->ip_blocks[i].status.hang) {
- 				DRM_INFO("Some block need full reset!\n");
- 				return true;
-@@ -2634,165 +2905,178 @@ err:
- 	return r;
- }
- 
--/**
-- * amdgpu_sriov_gpu_reset - reset the asic
-+/*
-+ * amdgpu_reset - reset ASIC/GPU for bare-metal or passthrough
-  *
-  * @adev: amdgpu device pointer
-- * @job: which job trigger hang
-+ * @reset_flags: output param tells caller the reset result
-  *
-- * Attempt the reset the GPU if it has hung (all asics).
-- * for SRIOV case.
-- * Returns 0 for success or an error on failure.
-- */
--int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job)
-+ * attempt to do soft-reset or full-reset and reinitialize Asic
-+ * return 0 means successed otherwise failed
-+*/
-+static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags)
- {
--	int i, j, r = 0;
--	int resched;
--	struct amdgpu_bo *bo, *tmp;
--	struct amdgpu_ring *ring;
--	struct dma_fence *fence = NULL, *next = NULL;
-+	bool need_full_reset, vram_lost = 0;
-+	int r;
- 
--	mutex_lock(&adev->virt.lock_reset);
--	atomic_inc(&adev->gpu_reset_counter);
--	adev->gfx.in_reset = true;
-+	need_full_reset = amdgpu_need_full_reset(adev);
- 
--	/* block TTM */
--	resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
-+	if (!need_full_reset) {
-+		amdgpu_pre_soft_reset(adev);
-+		r = amdgpu_soft_reset(adev);
-+		amdgpu_post_soft_reset(adev);
-+		if (r || amdgpu_check_soft_reset(adev)) {
-+			DRM_INFO("soft reset failed, will fallback to full reset!\n");
-+			need_full_reset = true;
-+		}
- 
--	/* we start from the ring trigger GPU hang */
--	j = job ? job->ring->idx : 0;
-+	}
- 
--	/* block scheduler */
--	for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) {
--		ring = adev->rings[i % AMDGPU_MAX_RINGS];
--		if (!ring || !ring->sched.thread)
--			continue;
-+	if (need_full_reset) {
-+		r = amdgpu_suspend(adev);
- 
--		kthread_park(ring->sched.thread);
-+retry:
-+		amdgpu_atombios_scratch_regs_save(adev);
-+		r = amdgpu_asic_reset(adev);
-+		amdgpu_atombios_scratch_regs_restore(adev);
-+		/* post card */
-+		amdgpu_atom_asic_init(adev->mode_info.atom_context);
- 
--		if (job && j != i)
--			continue;
-+		if (!r) {
-+			dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
-+			r = amdgpu_resume_phase1(adev);
-+			if (r)
-+				goto out;
- 
--		/* here give the last chance to check if job removed from mirror-list
--		 * since we already pay some time on kthread_park */
--		if (job && list_empty(&job->base.node)) {
--			kthread_unpark(ring->sched.thread);
--			goto give_up_reset;
-+			vram_lost = amdgpu_check_vram_lost(adev);
-+			if (vram_lost) {
-+				DRM_ERROR("VRAM is lost!\n");
-+				atomic_inc(&adev->vram_lost_counter);
-+			}
-+
-+			r = amdgpu_gtt_mgr_recover(
-+				&adev->mman.bdev.man[TTM_PL_TT]);
-+			if (r)
-+				goto out;
-+
-+			r = amdgpu_resume_phase2(adev);
-+			if (r)
-+				goto out;
-+
-+			if (vram_lost)
-+				amdgpu_fill_reset_magic(adev);
- 		}
-+	}
- 
--		if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit))
--			amd_sched_job_kickout(&job->base);
-+out:
-+	if (!r) {
-+		amdgpu_irq_gpu_reset_resume_helper(adev);
-+		r = amdgpu_ib_ring_tests(adev);
-+		if (r) {
-+			dev_err(adev->dev, "ib ring test failed (%d).\n", r);
-+			r = amdgpu_suspend(adev);
-+			need_full_reset = true;
-+			goto retry;
-+		}
-+	}
- 
--		/* only do job_reset on the hang ring if @job not NULL */
--		amd_sched_hw_job_reset(&ring->sched);
-+	if (reset_flags) {
-+		if (vram_lost)
-+			(*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
- 
--		/* after all hw jobs are reset, hw fence is meaningless, so force_completion */
--		amdgpu_fence_driver_force_completion_ring(ring);
-+		if (need_full_reset)
-+			(*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
- 	}
- 
--	/* request to take full control of GPU before re-initialization  */
--	if (job)
--		amdgpu_virt_reset_gpu(adev);
--	else
--		amdgpu_virt_request_full_gpu(adev, true);
-+	return r;
-+}
-+
-+/*
-+ * amdgpu_reset_sriov - reset ASIC for SR-IOV vf
-+ *
-+ * @adev: amdgpu device pointer
-+ * @reset_flags: output param tells caller the reset result
-+ *
-+ * do VF FLR and reinitialize Asic
-+ * return 0 means successed otherwise failed
-+*/
-+static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, bool from_hypervisor)
-+{
-+	int r;
- 
-+	if (from_hypervisor)
-+		r = amdgpu_virt_request_full_gpu(adev, true);
-+	else
-+		r = amdgpu_virt_reset_gpu(adev);
-+	if (r)
-+		return r;
- 
- 	/* Resume IP prior to SMC */
--	amdgpu_sriov_reinit_early(adev);
-+	r = amdgpu_sriov_reinit_early(adev);
-+	if (r)
-+		goto error;
- 
- 	/* we need recover gart prior to run SMC/CP/SDMA resume */
--	amdgpu_ttm_recover_gart(adev);
-+	amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
- 
- 	/* now we are okay to resume SMC/CP/SDMA */
--	amdgpu_sriov_reinit_late(adev);
-+	r = amdgpu_sriov_reinit_late(adev);
-+	if (r)
-+		goto error;
- 
- 	amdgpu_irq_gpu_reset_resume_helper(adev);
--
--	if (amdgpu_ib_ring_tests(adev))
-+	r = amdgpu_ib_ring_tests(adev);
-+	if (r)
- 		dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);
- 
-+error:
- 	/* release full control of GPU after ib test */
- 	amdgpu_virt_release_full_gpu(adev, true);
- 
--	DRM_INFO("recover vram bo from shadow\n");
--
--	ring = adev->mman.buffer_funcs_ring;
--	mutex_lock(&adev->shadow_list_lock);
--	list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
--		next = NULL;
--		amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
--		if (fence) {
--			r = dma_fence_wait(fence, false);
--			if (r) {
--				WARN(r, "recovery from shadow isn't completed\n");
--				break;
--			}
--		}
--
--		dma_fence_put(fence);
--		fence = next;
--	}
--	mutex_unlock(&adev->shadow_list_lock);
--
--	if (fence) {
--		r = dma_fence_wait(fence, false);
--		if (r)
--			WARN(r, "recovery from shadow isn't completed\n");
--	}
--	dma_fence_put(fence);
--
--	for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) {
--		ring = adev->rings[i % AMDGPU_MAX_RINGS];
--		if (!ring || !ring->sched.thread)
--			continue;
--
--		if (job && j != i) {
--			kthread_unpark(ring->sched.thread);
--			continue;
-+	if (reset_flags) {
-+		if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
-+			(*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
-+			atomic_inc(&adev->vram_lost_counter);
- 		}
- 
--		amd_sched_job_recovery(&ring->sched);
--		kthread_unpark(ring->sched.thread);
-+		/* VF FLR or hotlink reset is always full-reset */
-+		(*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
- 	}
- 
--	drm_helper_resume_force_mode(adev->ddev);
--give_up_reset:
--	ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
--	if (r) {
--		/* bad news, how to tell it to userspace ? */
--		dev_info(adev->dev, "GPU reset failed\n");
--	} else {
--		dev_info(adev->dev, "GPU reset successed!\n");
--	}
--
--	adev->gfx.in_reset = false;
--	mutex_unlock(&adev->virt.lock_reset);
- 	return r;
- }
- 
- /**
-- * amdgpu_gpu_reset - reset the asic
-+ * amdgpu_gpu_recover - reset the asic and recover scheduler
-  *
-  * @adev: amdgpu device pointer
-+ * @job: which job trigger hang
-  *
-- * Attempt the reset the GPU if it has hung (all asics).
-+ * Attempt to reset the GPU if it has hung (all asics).
-  * Returns 0 for success or an error on failure.
-  */
--int amdgpu_gpu_reset(struct amdgpu_device *adev)
-+int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job)
- {
--	int i, r;
--	int resched;
--	bool need_full_reset, vram_lost = false;
-+	struct drm_atomic_state *state = NULL;
-+	uint64_t reset_flags = 0;
-+	int i, r, resched;
- 
- 	if (!amdgpu_check_soft_reset(adev)) {
- 		DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
- 		return 0;
- 	}
- 
-+	dev_info(adev->dev, "GPU reset begin!\n");
-+
-+	mutex_lock(&adev->lock_reset);
- 	atomic_inc(&adev->gpu_reset_counter);
-+	adev->in_gpu_reset = 1;
- 
- 	/* block TTM */
- 	resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
-+	/* store modesetting */
-+	if (amdgpu_device_has_dc_support(adev))
-+		state = drm_atomic_helper_suspend(adev->ddev);
- 
- 	/* block scheduler */
- 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
-@@ -2800,69 +3084,26 @@ int amdgpu_gpu_reset(struct amdgpu_devic
- 
- 		if (!ring || !ring->sched.thread)
- 			continue;
--		kthread_park(ring->sched.thread);
--		amd_sched_hw_job_reset(&ring->sched);
--	}
--	/* after all hw jobs are reset, hw fence is meaningless, so force_completion */
--	amdgpu_fence_driver_force_completion(adev);
- 
--	need_full_reset = amdgpu_need_full_reset(adev);
-+		/* only focus on the ring hit timeout if &job not NULL */
-+		if (job && job->ring->idx != i)
-+			continue;
- 
--	if (!need_full_reset) {
--		amdgpu_pre_soft_reset(adev);
--		r = amdgpu_soft_reset(adev);
--		amdgpu_post_soft_reset(adev);
--		if (r || amdgpu_check_soft_reset(adev)) {
--			DRM_INFO("soft reset failed, will fallback to full reset!\n");
--			need_full_reset = true;
--		}
--	}
-+		kthread_park(ring->sched.thread);
-+		amd_sched_hw_job_reset(&ring->sched, &job->base);
- 
--	if (need_full_reset) {
--		r = amdgpu_suspend(adev);
-+		/* after all hw jobs are reset, hw fence is meaningless, so force_completion */
-+		amdgpu_fence_driver_force_completion(ring);
-+	}
- 
--retry:
--		amdgpu_atombios_scratch_regs_save(adev);
--		r = amdgpu_asic_reset(adev);
--		amdgpu_atombios_scratch_regs_restore(adev);
--		/* post card */
--		amdgpu_atom_asic_init(adev->mode_info.atom_context);
-+	if (amdgpu_sriov_vf(adev))
-+		r = amdgpu_reset_sriov(adev, &reset_flags, job ? false : true);
-+	else
-+		r = amdgpu_reset(adev, &reset_flags);
- 
--		if (!r) {
--			dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
--			r = amdgpu_resume_phase1(adev);
--			if (r)
--				goto out;
--			vram_lost = amdgpu_check_vram_lost(adev);
--			if (vram_lost) {
--				DRM_ERROR("VRAM is lost!\n");
--				atomic_inc(&adev->vram_lost_counter);
--			}
--			r = amdgpu_ttm_recover_gart(adev);
--			if (r)
--				goto out;
--			r = amdgpu_resume_phase2(adev);
--			if (r)
--				goto out;
--			if (vram_lost)
--				amdgpu_fill_reset_magic(adev);
--		}
--	}
--out:
- 	if (!r) {
--		amdgpu_irq_gpu_reset_resume_helper(adev);
--		r = amdgpu_ib_ring_tests(adev);
--		if (r) {
--			dev_err(adev->dev, "ib ring test failed (%d).\n", r);
--			r = amdgpu_suspend(adev);
--			need_full_reset = true;
--			goto retry;
--		}
--		/**
--		 * recovery vm page tables, since we cannot depend on VRAM is
--		 * consistent after gpu full reset.
--		 */
--		if (need_full_reset && amdgpu_need_backup(adev)) {
-+		if (((reset_flags & AMDGPU_RESET_INFO_FULLRESET) && !(adev->flags & AMD_IS_APU)) ||
-+			(reset_flags & AMDGPU_RESET_INFO_VRAM_LOST)) {
- 			struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
- 			struct amdgpu_bo *bo, *tmp;
- 			struct dma_fence *fence = NULL, *next = NULL;
-@@ -2891,38 +3132,56 @@ out:
- 			}
- 			dma_fence_put(fence);
- 		}
-+
- 		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
- 			struct amdgpu_ring *ring = adev->rings[i];
- 
- 			if (!ring || !ring->sched.thread)
- 				continue;
- 
-+			/* only focus on the ring hit timeout if &job not NULL */
-+			if (job && job->ring->idx != i)
-+				continue;
-+
- 			amd_sched_job_recovery(&ring->sched);
- 			kthread_unpark(ring->sched.thread);
- 		}
- 	} else {
--		dev_err(adev->dev, "asic resume failed (%d).\n", r);
--		amdgpu_vf_error_put(AMDGIM_ERROR_VF_ASIC_RESUME_FAIL, 0, r);
- 		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
--			if (adev->rings[i] && adev->rings[i]->sched.thread) {
--				kthread_unpark(adev->rings[i]->sched.thread);
--			}
-+			struct amdgpu_ring *ring = adev->rings[i];
-+
-+			if (!ring || !ring->sched.thread)
-+				continue;
-+
-+			/* only focus on the ring hit timeout if &job not NULL */
-+			if (job && job->ring->idx != i)
-+				continue;
-+
-+			kthread_unpark(adev->rings[i]->sched.thread);
- 		}
- 	}
- 
--	drm_helper_resume_force_mode(adev->ddev);
-+	if (amdgpu_device_has_dc_support(adev)) {
-+		if (drm_atomic_helper_resume(adev->ddev, state))
-+			dev_info(adev->dev, "drm resume failed:%d\n", r);
-+		amdgpu_dm_display_resume(adev);
-+	} else {
-+		drm_helper_resume_force_mode(adev->ddev);
-+	}
- 
- 	ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
-+
- 	if (r) {
- 		/* bad news, how to tell it to userspace ? */
--		dev_info(adev->dev, "GPU reset failed\n");
--		amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
--	}
--	else {
--		dev_info(adev->dev, "GPU reset successed!\n");
-+		dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
-+		amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
-+	} else {
-+		dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter));
- 	}
- 
- 	amdgpu_vf_error_trans_all(adev);
-+	adev->in_gpu_reset = 0;
-+	mutex_unlock(&adev->lock_reset);
- 	return r;
- }
- 
-@@ -3070,9 +3329,9 @@ static ssize_t amdgpu_debugfs_regs_read(
- 	pm_pg_lock = (*pos >> 23) & 1;
- 
- 	if (*pos & (1ULL << 62)) {
--		se_bank = (*pos >> 24) & 0x3FF;
--		sh_bank = (*pos >> 34) & 0x3FF;
--		instance_bank = (*pos >> 44) & 0x3FF;
-+		se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
-+		sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
-+		instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
- 
- 		if (se_bank == 0x3FF)
- 			se_bank = 0xFFFFFFFF;
-@@ -3146,9 +3405,9 @@ static ssize_t amdgpu_debugfs_regs_write
- 	pm_pg_lock = (*pos >> 23) & 1;
- 
- 	if (*pos & (1ULL << 62)) {
--		se_bank = (*pos >> 24) & 0x3FF;
--		sh_bank = (*pos >> 34) & 0x3FF;
--		instance_bank = (*pos >> 44) & 0x3FF;
-+		se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
-+		sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
-+		instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
- 
- 		if (se_bank == 0x3FF)
- 			se_bank = 0xFFFFFFFF;
-@@ -3463,10 +3722,7 @@ static ssize_t amdgpu_debugfs_sensor_rea
- 
- 	valuesize = sizeof(values);
- 	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
--		r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize);
--	else if (adev->pm.funcs && adev->pm.funcs->read_sensor)
--		r = adev->pm.funcs->read_sensor(adev, idx, &values[0],
--						&valuesize);
-+		r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
- 	else
- 		return -EINVAL;
- 
-@@ -3499,12 +3755,12 @@ static ssize_t amdgpu_debugfs_wave_read(
- 		return -EINVAL;
- 
- 	/* decode offset */
--	offset = (*pos & 0x7F);
--	se = ((*pos >> 7) & 0xFF);
--	sh = ((*pos >> 15) & 0xFF);
--	cu = ((*pos >> 23) & 0xFF);
--	wave = ((*pos >> 31) & 0xFF);
--	simd = ((*pos >> 37) & 0xFF);
-+	offset = (*pos & GENMASK_ULL(6, 0));
-+	se = (*pos & GENMASK_ULL(14, 7)) >> 7;
-+	sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
-+	cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
-+	wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
-+	simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
- 
- 	/* switch to the specific se/sh/cu */
- 	mutex_lock(&adev->grbm_idx_mutex);
-@@ -3549,14 +3805,14 @@ static ssize_t amdgpu_debugfs_gpr_read(s
- 		return -EINVAL;
- 
- 	/* decode offset */
--	offset = (*pos & 0xFFF);       /* in dwords */
--	se = ((*pos >> 12) & 0xFF);
--	sh = ((*pos >> 20) & 0xFF);
--	cu = ((*pos >> 28) & 0xFF);
--	wave = ((*pos >> 36) & 0xFF);
--	simd = ((*pos >> 44) & 0xFF);
--	thread = ((*pos >> 52) & 0xFF);
--	bank = ((*pos >> 60) & 1);
-+	offset = *pos & GENMASK_ULL(11, 0);
-+	se = (*pos & GENMASK_ULL(19, 12)) >> 12;
-+	sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
-+	cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
-+	wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
-+	simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
-+	thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
-+	bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
- 
- 	data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
- 	if (!data)
-@@ -3754,6 +4010,28 @@ int amdgpu_debugfs_init(struct drm_minor
- {
- 	return 0;
- }
-+
-+static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data)
-+{
-+	struct drm_info_node *node = (struct drm_info_node *) m->private;
-+	struct drm_device *dev = node->minor->dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+
-+	seq_write(m, adev->bios, adev->bios_size);
-+	return 0;
-+}
-+
-+static const struct drm_info_list amdgpu_vbios_dump_list[] = {
-+		{"amdgpu_vbios",
-+		 amdgpu_debugfs_get_vbios_dump,
-+		 0, NULL},
-+};
-+
-+static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
-+{
-+	return amdgpu_debugfs_add_files(adev,
-+					amdgpu_vbios_dump_list, 1);
-+}
- #else
- static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
- {
-@@ -3763,5 +4041,9 @@ static int amdgpu_debugfs_regs_init(stru
- {
- 	return 0;
- }
-+static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
-+{
-+	return 0;
-+}
- static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
- #endif
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c	2017-12-14 06:39:58.377903541 +0100
-@@ -518,7 +518,7 @@ amdgpu_framebuffer_init(struct drm_devic
- 	return 0;
- }
- 
--static struct drm_framebuffer *
-+struct drm_framebuffer *
- amdgpu_user_framebuffer_create(struct drm_device *dev,
- 			       struct drm_file *file_priv,
- 			       const struct drm_mode_fb_cmd2 *mode_cmd)
-@@ -556,7 +556,7 @@ amdgpu_user_framebuffer_create(struct dr
- 	return &amdgpu_fb->base;
- }
- 
--static void amdgpu_output_poll_changed(struct drm_device *dev)
-+void amdgpu_output_poll_changed(struct drm_device *dev)
- {
- 	struct amdgpu_device *adev = dev->dev_private;
- 	amdgpu_fb_output_poll_changed(adev);
-@@ -631,6 +631,19 @@ int amdgpu_modeset_create_props(struct a
- 					 "dither",
- 					 amdgpu_dither_enum_list, sz);
- 
-+	if (amdgpu_device_has_dc_support(adev)) {
-+		adev->mode_info.freesync_property =
-+			drm_property_create_bool(adev->ddev, 0, "freesync");
-+		if (!adev->mode_info.freesync_property)
-+			return -ENOMEM;
-+		adev->mode_info.freesync_capable_property =
-+			drm_property_create_bool(adev->ddev,
-+						 0,
-+						 "freesync_capable");
-+		if (!adev->mode_info.freesync_capable_property)
-+			return -ENOMEM;
-+	}
-+
- 	return 0;
- }
- 
-@@ -886,3 +899,18 @@ int amdgpu_crtc_idx_to_irq_type(struct a
- 		return AMDGPU_CRTC_IRQ_NONE;
- 	}
- }
-+
-+int amdgpu_freesync_ioctl(struct drm_device *dev, void *data,
-+			    struct drm_file *filp)
-+{
-+	int ret = -EPERM;
-+	struct amdgpu_device *adev = dev->dev_private;
-+
-+	if (adev->mode_info.funcs->notify_freesync)
-+		ret = adev->mode_info.funcs->notify_freesync(dev,data,filp);
-+	else
-+		DRM_DEBUG("amdgpu no notify_freesync ioctl\n");
-+
-+	return ret;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h.0130~	2017-12-14 06:39:58.377903541 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h	2017-12-14 06:39:58.377903541 +0100
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef __AMDGPU_DISPLAY_H__
-+#define __AMDGPU_DISPLAY_H__
-+
-+struct drm_framebuffer *
-+amdgpu_user_framebuffer_create(struct drm_device *dev,
-+			       struct drm_file *file_priv,
-+			       const struct drm_mode_fb_cmd2 *mode_cmd);
-+void amdgpu_output_poll_changed(struct drm_device *dev);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c	2017-12-14 06:39:58.378903542 +0100
-@@ -960,8 +960,10 @@ u8 amdgpu_encode_pci_lane_width(u32 lane
- }
- 
- struct amd_vce_state*
--amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx)
-+amdgpu_get_vce_clock_state(void *handle, u32 idx)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
- 	if (idx < adev->pm.dpm.num_of_vce_states)
- 		return &adev->pm.dpm.vce_states[idx];
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h	2017-12-14 06:39:58.378903542 +0100
-@@ -241,179 +241,131 @@ enum amdgpu_pcie_gen {
- 	AMDGPU_PCIE_GEN_INVALID = 0xffff
- };
- 
--struct amdgpu_dpm_funcs {
--	int (*get_temperature)(struct amdgpu_device *adev);
--	int (*pre_set_power_state)(struct amdgpu_device *adev);
--	int (*set_power_state)(struct amdgpu_device *adev);
--	void (*post_set_power_state)(struct amdgpu_device *adev);
--	void (*display_configuration_changed)(struct amdgpu_device *adev);
--	u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
--	u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
--	void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
--	void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
--	int (*force_performance_level)(struct amdgpu_device *adev, enum amd_dpm_forced_level level);
--	bool (*vblank_too_short)(struct amdgpu_device *adev);
--	void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
--	void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
--	void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
--	void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
--	u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
--	int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
--	int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
--	int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);
--	int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);
--	int (*get_sclk_od)(struct amdgpu_device *adev);
--	int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value);
--	int (*get_mclk_od)(struct amdgpu_device *adev);
--	int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value);
--	int (*check_state_equal)(struct amdgpu_device *adev,
--				struct amdgpu_ps *cps,
--				struct amdgpu_ps *rps,
--				bool *equal);
--	int (*read_sensor)(struct amdgpu_device *adev, int idx, void *value,
--			   int *size);
--
--	struct amd_vce_state* (*get_vce_clock_state)(struct amdgpu_device *adev, unsigned idx);
--	int (*reset_power_profile_state)(struct amdgpu_device *adev,
--			struct amd_pp_profile *request);
--	int (*get_power_profile_state)(struct amdgpu_device *adev,
--			struct amd_pp_profile *query);
--	int (*set_power_profile_state)(struct amdgpu_device *adev,
--			struct amd_pp_profile *request);
--	int (*switch_power_profile)(struct amdgpu_device *adev,
--			enum amd_pp_profile_type type);
--};
-+#define amdgpu_dpm_pre_set_power_state(adev) \
-+		((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
-+
-+#define amdgpu_dpm_set_power_state(adev) \
-+		((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
-+
-+#define amdgpu_dpm_post_set_power_state(adev) \
-+		((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
-+
-+#define amdgpu_dpm_display_configuration_changed(adev) \
-+		((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))
-+
-+#define amdgpu_dpm_print_power_state(adev, ps) \
-+		((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))
- 
--#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
--#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
--#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
--#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
--#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
--#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
--#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
-+#define amdgpu_dpm_vblank_too_short(adev) \
-+		((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle))
-+
-+#define amdgpu_dpm_enable_bapm(adev, e) \
-+		((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
- 
- #define amdgpu_dpm_read_sensor(adev, idx, value, size) \
--	((adev)->pp_enabled ? \
--		(adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value), (size)) : \
--		(adev)->pm.funcs->read_sensor((adev), (idx), (value), (size)))
-+		((adev)->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle, (idx), (value), (size)))
- 
- #define amdgpu_dpm_get_temperature(adev) \
--	((adev)->pp_enabled ?						\
--	      (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
--	      (adev)->pm.funcs->get_temperature((adev)))
-+		((adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle))
- 
- #define amdgpu_dpm_set_fan_control_mode(adev, m) \
--	((adev)->pp_enabled ?						\
--	      (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
--	      (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
-+		((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)))
- 
- #define amdgpu_dpm_get_fan_control_mode(adev) \
--	((adev)->pp_enabled ?						\
--	      (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
--	      (adev)->pm.funcs->get_fan_control_mode((adev)))
-+		((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle))
- 
- #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
--	((adev)->pp_enabled ?						\
--	      (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
--	      (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
-+		((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
- 
- #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
--	((adev)->pp_enabled ?						\
--	      (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
--	      (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
-+		((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
- 
- #define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
--	((adev)->pp_enabled ?						\
--	      (adev)->powerplay.pp_funcs->get_fan_speed_rpm((adev)->powerplay.pp_handle, (s)) : \
--	      -EINVAL)
-+		((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))
- 
- #define amdgpu_dpm_get_sclk(adev, l) \
--	((adev)->pp_enabled ?						\
--	      (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
--		(adev)->pm.funcs->get_sclk((adev), (l)))
-+		((adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)))
- 
- #define amdgpu_dpm_get_mclk(adev, l)  \
--	((adev)->pp_enabled ?						\
--	      (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
--	      (adev)->pm.funcs->get_mclk((adev), (l)))
--
-+		((adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)))
- 
- #define amdgpu_dpm_force_performance_level(adev, l) \
--	((adev)->pp_enabled ?						\
--	      (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
--	      (adev)->pm.funcs->force_performance_level((adev), (l)))
-+		((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
- 
- #define amdgpu_dpm_powergate_uvd(adev, g) \
--	((adev)->pp_enabled ?						\
--	      (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
--	      (adev)->pm.funcs->powergate_uvd((adev), (g)))
-+		((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)))
- 
- #define amdgpu_dpm_powergate_vce(adev, g) \
--	((adev)->pp_enabled ?						\
--	      (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
--	      (adev)->pm.funcs->powergate_vce((adev), (g)))
-+		((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)))
- 
- #define amdgpu_dpm_get_current_power_state(adev) \
--	(adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
-+		((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
- 
- #define amdgpu_dpm_get_pp_num_states(adev, data) \
--	(adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
-+		((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
- 
- #define amdgpu_dpm_get_pp_table(adev, table) \
--	(adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
-+		((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table))
- 
- #define amdgpu_dpm_set_pp_table(adev, buf, size) \
--	(adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
-+		((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size))
- 
- #define amdgpu_dpm_print_clock_levels(adev, type, buf) \
--	(adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
-+		((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf))
- 
- #define amdgpu_dpm_force_clock_level(adev, type, level) \
--		(adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
-+		((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level))
- 
- #define amdgpu_dpm_get_sclk_od(adev) \
--	(adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
-+		((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle))
- 
- #define amdgpu_dpm_set_sclk_od(adev, value) \
--	(adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
-+		((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value))
- 
- #define amdgpu_dpm_get_mclk_od(adev) \
--	((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
-+		((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
- 
- #define amdgpu_dpm_set_mclk_od(adev, value) \
--	((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
-+		((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
- 
--#define amdgpu_dpm_dispatch_task(adev, event_id, input, output)		\
--	(adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
-+#define amdgpu_dpm_dispatch_task(adev, task_id, input, output)		\
-+		((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (input), (output))
- 
--#define amgdpu_dpm_check_state_equal(adev, cps, rps, equal) (adev)->pm.funcs->check_state_equal((adev), (cps),(rps),(equal))
-+#define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \
-+		((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))
- 
- #define amdgpu_dpm_get_vce_clock_state(adev, i)				\
--	((adev)->pp_enabled ?						\
--	 (adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)) : \
--	 (adev)->pm.funcs->get_vce_clock_state((adev), (i)))
--
--#define amdgpu_dpm_get_performance_level(adev) \
--	((adev)->pp_enabled ?						\
--	(adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) : \
--	(adev)->pm.dpm.forced_level)
-+		((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)))
-+
-+#define amdgpu_dpm_get_performance_level(adev)				\
-+		((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle))
- 
- #define amdgpu_dpm_reset_power_profile_state(adev, request) \
--	((adev)->powerplay.pp_funcs->reset_power_profile_state(\
-+		((adev)->powerplay.pp_funcs->reset_power_profile_state(\
- 			(adev)->powerplay.pp_handle, request))
- 
- #define amdgpu_dpm_get_power_profile_state(adev, query) \
--	((adev)->powerplay.pp_funcs->get_power_profile_state(\
-+		((adev)->powerplay.pp_funcs->get_power_profile_state(\
- 			(adev)->powerplay.pp_handle, query))
- 
- #define amdgpu_dpm_set_power_profile_state(adev, request) \
--	((adev)->powerplay.pp_funcs->set_power_profile_state(\
-+		((adev)->powerplay.pp_funcs->set_power_profile_state(\
- 			(adev)->powerplay.pp_handle, request))
- 
- #define amdgpu_dpm_switch_power_profile(adev, type) \
--	((adev)->powerplay.pp_funcs->switch_power_profile(\
-+		((adev)->powerplay.pp_funcs->switch_power_profile(\
- 			(adev)->powerplay.pp_handle, type))
- 
-+#define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
-+		((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
-+			(adev)->powerplay.pp_handle, msg_id))
-+
-+#define amdgpu_dpm_notify_smu_memory_info(adev, virtual_addr_low, \
-+			virtual_addr_hi, mc_addr_low, mc_addr_hi, size) \
-+		((adev)->powerplay.pp_funcs->notify_smu_memory_info)( \
-+			(adev)->powerplay.pp_handle, virtual_addr_low, \
-+			virtual_addr_hi, mc_addr_low, mc_addr_hi, size)
-+
- struct amdgpu_dpm {
- 	struct amdgpu_ps        *ps;
- 	/* number of valid power states */
-@@ -485,10 +437,9 @@ struct amdgpu_pm {
- 	struct amdgpu_dpm       dpm;
- 	const struct firmware	*fw;	/* SMC firmware */
- 	uint32_t                fw_version;
--	const struct amdgpu_dpm_funcs *funcs;
- 	uint32_t                pcie_gen_mask;
- 	uint32_t                pcie_mlw_mask;
--	struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
-+	struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
- };
- 
- #define R600_SSTU_DFLT                               0
-@@ -551,6 +502,6 @@ u16 amdgpu_get_pcie_lane_support(struct
- u8 amdgpu_encode_pci_lane_width(u32 lanes);
- 
- struct amd_vce_state*
--amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx);
-+amdgpu_get_vce_clock_state(void *handle, u32 idx);
- 
- #endif
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c	2017-12-14 06:39:58.378903542 +0100
-@@ -69,9 +69,13 @@
-  * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
-  * - 3.18.0 - Export gpu always on cu bitmap
-  * - 3.19.0 - Add support for UVD MJPEG decode
-+ * - 3.20.0 - Add support for local BOs
-+ * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
-+ * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
-+ * - 3.23.0 - Add query for VRAM lost counter
-  */
- #define KMS_DRIVER_MAJOR	3
--#define KMS_DRIVER_MINOR	19
-+#define KMS_DRIVER_MINOR	23
- #define KMS_DRIVER_PATCHLEVEL	0
- 
- int amdgpu_vram_limit = 0;
-@@ -91,7 +95,7 @@ int amdgpu_dpm = -1;
- int amdgpu_fw_load_type = -1;
- int amdgpu_aspm = -1;
- int amdgpu_runtime_pm = -1;
--unsigned amdgpu_ip_block_mask = 0xffffffff;
-+uint amdgpu_ip_block_mask = 0xffffffff;
- int amdgpu_bapm = -1;
- int amdgpu_deep_color = 0;
- int amdgpu_vm_size = -1;
-@@ -102,18 +106,20 @@ int amdgpu_vm_debug = 0;
- int amdgpu_vram_page_split = 512;
- int amdgpu_vm_update_mode = -1;
- int amdgpu_exp_hw_support = 0;
-+int amdgpu_dc = -1;
-+int amdgpu_dc_log = 0;
- int amdgpu_sched_jobs = 32;
- int amdgpu_sched_hw_submission = 2;
- int amdgpu_no_evict = 0;
- int amdgpu_direct_gma_size = 0;
--unsigned amdgpu_pcie_gen_cap = 0;
--unsigned amdgpu_pcie_lane_cap = 0;
--unsigned amdgpu_cg_mask = 0xffffffff;
--unsigned amdgpu_pg_mask = 0xffffffff;
--unsigned amdgpu_sdma_phase_quantum = 32;
-+uint amdgpu_pcie_gen_cap = 0;
-+uint amdgpu_pcie_lane_cap = 0;
-+uint amdgpu_cg_mask = 0xffffffff;
-+uint amdgpu_pg_mask = 0xffffffff;
-+uint amdgpu_sdma_phase_quantum = 32;
- char *amdgpu_disable_cu = NULL;
- char *amdgpu_virtual_display = NULL;
--unsigned amdgpu_pp_feature_mask = 0xffffffff;
-+uint amdgpu_pp_feature_mask = 0xffffffff;
- int amdgpu_ngg = 0;
- int amdgpu_prim_buf_per_se = 0;
- int amdgpu_pos_buf_per_se = 0;
-@@ -121,6 +127,7 @@ int amdgpu_cntl_sb_buf_per_se = 0;
- int amdgpu_param_buf_per_se = 0;
- int amdgpu_job_hang_limit = 0;
- int amdgpu_lbpw = -1;
-+int amdgpu_compute_multipipe = -1;
- 
- MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
- module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
-@@ -206,6 +213,12 @@ module_param_named(vram_page_split, amdg
- MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
- module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
- 
-+MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
-+module_param_named(dc, amdgpu_dc, int, 0444);
-+
-+MODULE_PARM_DESC(dc, "Display Core Log Level (0 = minimal (default), 1 = chatty");
-+module_param_named(dc_log, amdgpu_dc_log, int, 0444);
-+
- MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
- module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
- 
-@@ -264,6 +277,9 @@ module_param_named(job_hang_limit, amdgp
- MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
- module_param_named(lbpw, amdgpu_lbpw, int, 0444);
- 
-+MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
-+module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
-+
- #ifdef CONFIG_DRM_AMDGPU_SI
- 
- #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
-@@ -290,7 +306,6 @@ MODULE_PARM_DESC(cik_support, "CIK suppo
- module_param_named(cik_support, amdgpu_cik_support, int, 0444);
- #endif
- 
--
- static const struct pci_device_id pciidlist[] = {
- #ifdef  CONFIG_DRM_AMDGPU_SI
- 	{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
-@@ -510,17 +525,17 @@ static const struct pci_device_id pciidl
- 	{0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
- 	{0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
- 	/* Vega 10 */
--	{0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
--	{0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
--	{0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
--	{0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
--	{0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
--	{0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
--	{0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
--	{0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
--	{0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT},
-+	{0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
-+	{0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
-+	{0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
-+	{0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
-+	{0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
-+	{0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
-+	{0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
-+	{0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
-+	{0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
- 	/* Raven */
--	{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
-+	{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
- 
- 	{0, 0, 0}
- };
-@@ -550,12 +565,13 @@ static int amdgpu_kick_out_firmware_fb(s
- 	return 0;
- }
- 
-+
- static int amdgpu_pci_probe(struct pci_dev *pdev,
- 			    const struct pci_device_id *ent)
- {
- 	struct drm_device *dev;
- 	unsigned long flags = ent->driver_data;
--	int ret;
-+	int ret, retry = 0;
- 
- 	if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
- 		DRM_INFO("This hardware requires experimental hardware support.\n"
-@@ -588,8 +604,14 @@ static int amdgpu_pci_probe(struct pci_d
- 
- 	pci_set_drvdata(pdev, dev);
- 
-+retry_init:
- 	ret = drm_dev_register(dev, ent->driver_data);
--	if (ret)
-+	if (ret == -EAGAIN && ++retry <= 3) {
-+		DRM_INFO("retry init %d\n", retry);
-+		/* Don't request EX mode too frequently which is attacking */
-+		msleep(5000);
-+		goto retry_init;
-+	} else if (ret)
- 		goto err_pci;
- 
- 	return 0;
-@@ -608,6 +630,8 @@ amdgpu_pci_remove(struct pci_dev *pdev)
- 
- 	drm_dev_unregister(dev);
- 	drm_dev_unref(dev);
-+	pci_disable_device(pdev);
-+	pci_set_drvdata(pdev, NULL);
- }
- 
- static void
-@@ -852,6 +876,7 @@ static struct drm_driver kms_driver = {
- 	.gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
- 	.gem_prime_vmap = amdgpu_gem_prime_vmap,
- 	.gem_prime_vunmap = amdgpu_gem_prime_vunmap,
-+	.gem_prime_mmap = amdgpu_gem_prime_mmap,
- 
- 	.name = DRIVER_NAME,
- 	.desc = DRIVER_DESC,
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c	2017-12-14 06:39:58.378903542 +0100
-@@ -42,11 +42,6 @@
-    this contains a helper + a amdgpu fb
-    the helper contains a pointer to amdgpu framebuffer baseclass.
- */
--struct amdgpu_fbdev {
--	struct drm_fb_helper helper;
--	struct amdgpu_framebuffer rfb;
--	struct amdgpu_device *adev;
--};
- 
- static int
- amdgpufb_open(struct fb_info *info, int user)
-@@ -149,7 +144,7 @@ static int amdgpufb_create_pinned_object
- 				       AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
- 				       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
- 				       AMDGPU_GEM_CREATE_VRAM_CLEARED,
--				       true, &gobj);
-+				       true, NULL, &gobj);
- 	if (ret) {
- 		pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
- 		return -ENOMEM;
-@@ -303,10 +298,10 @@ static int amdgpu_fbdev_destroy(struct d
- 	if (rfb->obj) {
- 		amdgpufb_destroy_pinned_object(rfb->obj);
- 		rfb->obj = NULL;
-+		drm_framebuffer_unregister_private(&rfb->base);
-+		drm_framebuffer_cleanup(&rfb->base);
- 	}
- 	drm_fb_helper_fini(&rfbdev->helper);
--	drm_framebuffer_unregister_private(&rfb->base);
--	drm_framebuffer_cleanup(&rfb->base);
- 
- 	return 0;
- }
-@@ -353,7 +348,8 @@ int amdgpu_fbdev_init(struct amdgpu_devi
- 	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
- 
- 	/* disable all the possible outputs/crtcs before entering KMS mode */
--	drm_helper_disable_unused_functions(adev->ddev);
-+	if (!amdgpu_device_has_dc_support(adev))
-+		drm_helper_disable_unused_functions(adev->ddev);
- 
- 	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
- 	return 0;
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c	2017-12-14 06:39:58.378903542 +0100
-@@ -169,6 +169,32 @@ int amdgpu_fence_emit(struct amdgpu_ring
- }
- 
- /**
-+ * amdgpu_fence_emit_polling - emit a fence on the requeste ring
-+ *
-+ * @ring: ring the fence is associated with
-+ * @s: resulting sequence number
-+ *
-+ * Emits a fence command on the requested ring (all asics).
-+ * Used For polling fence.
-+ * Returns 0 on success, -ENOMEM on failure.
-+ */
-+int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s)
-+{
-+	uint32_t seq;
-+
-+	if (!s)
-+		return -EINVAL;
-+
-+	seq = ++ring->fence_drv.sync_seq;
-+	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
-+			       seq, AMDGPU_FENCE_FLAG_INT);
-+
-+	*s = seq;
-+
-+	return 0;
-+}
-+
-+/**
-  * amdgpu_fence_schedule_fallback - schedule fallback check
-  *
-  * @ring: pointer to struct amdgpu_ring
-@@ -282,6 +308,30 @@ int amdgpu_fence_wait_empty(struct amdgp
- }
- 
- /**
-+ * amdgpu_fence_wait_polling - busy wait for givn sequence number
-+ *
-+ * @ring: ring index the fence is associated with
-+ * @wait_seq: sequence number to wait
-+ * @timeout: the timeout for waiting in usecs
-+ *
-+ * Wait for all fences on the requested ring to signal (all asics).
-+ * Returns left time if no timeout, 0 or minus if timeout.
-+ */
-+signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
-+				      uint32_t wait_seq,
-+				      signed long timeout)
-+{
-+	uint32_t seq;
-+
-+	do {
-+		seq = amdgpu_fence_read(ring);
-+		udelay(5);
-+		timeout -= 5;
-+	} while ((int32_t)(wait_seq - seq) > 0 && timeout > 0);
-+
-+	return timeout > 0 ? timeout : 0;
-+}
-+/**
-  * amdgpu_fence_count_emitted - get the count of emitted fences
-  *
-  * @ring: ring the fence is associated with
-@@ -340,9 +390,9 @@ int amdgpu_fence_driver_start_ring(struc
- 	ring->fence_drv.irq_type = irq_type;
- 	ring->fence_drv.initialized = true;
- 
--	dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
--		 "cpu addr 0x%p\n", ring->idx,
--		 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
-+	dev_dbg(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
-+		"cpu addr 0x%p\n", ring->idx,
-+		ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
- 	return 0;
- }
- 
-@@ -396,7 +446,7 @@ int amdgpu_fence_driver_init_ring(struct
- 			timeout = MAX_SCHEDULE_TIMEOUT;
- 		}
- 		r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
--				   num_hw_submission,
-+				   num_hw_submission, amdgpu_job_hang_limit,
- 				   timeout, ring->name);
- 		if (r) {
- 			DRM_ERROR("Failed to create scheduler on ring %s.\n",
-@@ -449,7 +499,7 @@ void amdgpu_fence_driver_fini(struct amd
- 		r = amdgpu_fence_wait_empty(ring);
- 		if (r) {
- 			/* no need to trigger GPU reset as we are unloading */
--			amdgpu_fence_driver_force_completion(adev);
-+			amdgpu_fence_driver_force_completion(ring);
- 		}
- 		amdgpu_irq_put(adev, ring->fence_drv.irq_src,
- 			       ring->fence_drv.irq_type);
-@@ -484,7 +534,7 @@ void amdgpu_fence_driver_suspend(struct
- 		r = amdgpu_fence_wait_empty(ring);
- 		if (r) {
- 			/* delay GPU reset to resume */
--			amdgpu_fence_driver_force_completion(adev);
-+			amdgpu_fence_driver_force_completion(ring);
- 		}
- 
- 		/* disable the interrupt */
-@@ -521,30 +571,15 @@ void amdgpu_fence_driver_resume(struct a
- }
- 
- /**
-- * amdgpu_fence_driver_force_completion - force all fence waiter to complete
-+ * amdgpu_fence_driver_force_completion - force signal latest fence of ring
-  *
-- * @adev: amdgpu device pointer
-+ * @ring: fence of the ring to signal
-  *
-- * In case of GPU reset failure make sure no process keep waiting on fence
-- * that will never complete.
-  */
--void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
-+void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
- {
--	int i;
--
--	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
--		struct amdgpu_ring *ring = adev->rings[i];
--		if (!ring || !ring->fence_drv.initialized)
--			continue;
--
--		amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
--	}
--}
--
--void amdgpu_fence_driver_force_completion_ring(struct amdgpu_ring *ring)
--{
--	if (ring)
--		amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
-+	amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
-+	amdgpu_fence_process(ring);
- }
- 
- /*
-@@ -641,30 +676,43 @@ static int amdgpu_debugfs_fence_info(str
- 			   atomic_read(&ring->fence_drv.last_seq));
- 		seq_printf(m, "Last emitted        0x%08x\n",
- 			   ring->fence_drv.sync_seq);
-+
-+		if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
-+			continue;
-+
-+		/* set in CP_VMID_PREEMPT and preemption occurred */
-+		seq_printf(m, "Last preempted      0x%08x\n",
-+			   le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
-+		/* set in CP_VMID_RESET and reset occurred */
-+		seq_printf(m, "Last reset          0x%08x\n",
-+			   le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
-+		/* Both preemption and reset occurred */
-+		seq_printf(m, "Last both           0x%08x\n",
-+			   le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
- 	}
- 	return 0;
- }
- 
- /**
-- * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset
-+ * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover
-  *
-  * Manually trigger a gpu reset at the next fence wait.
-  */
--static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data)
-+static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data)
- {
- 	struct drm_info_node *node = (struct drm_info_node *) m->private;
- 	struct drm_device *dev = node->minor->dev;
- 	struct amdgpu_device *adev = dev->dev_private;
- 
--	seq_printf(m, "gpu reset\n");
--	amdgpu_gpu_reset(adev);
-+	seq_printf(m, "gpu recover\n");
-+	amdgpu_gpu_recover(adev, NULL);
- 
- 	return 0;
- }
- 
- static const struct drm_info_list amdgpu_debugfs_fence_list[] = {
- 	{"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
--	{"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL}
-+	{"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL}
- };
- 
- static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = {
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c	2017-12-14 06:39:58.378903542 +0100
-@@ -57,63 +57,6 @@
-  */
- 
- /**
-- * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
-- *
-- * @adev: amdgpu_device pointer
-- *
-- * Allocate system memory for GART page table
-- * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
-- * gart table to be in system memory.
-- * Returns 0 for success, -ENOMEM for failure.
-- */
--int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
--{
--	void *ptr;
--
--	ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size,
--				   &adev->gart.table_addr);
--	if (ptr == NULL) {
--		return -ENOMEM;
--	}
--#ifdef CONFIG_X86
--	if (0) {
--		set_memory_uc((unsigned long)ptr,
--			      adev->gart.table_size >> PAGE_SHIFT);
--	}
--#endif
--	adev->gart.ptr = ptr;
--	memset((void *)adev->gart.ptr, 0, adev->gart.table_size);
--	return 0;
--}
--
--/**
-- * amdgpu_gart_table_ram_free - free system ram for gart page table
-- *
-- * @adev: amdgpu_device pointer
-- *
-- * Free system memory for GART page table
-- * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
-- * gart table to be in system memory.
-- */
--void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
--{
--	if (adev->gart.ptr == NULL) {
--		return;
--	}
--#ifdef CONFIG_X86
--	if (0) {
--		set_memory_wb((unsigned long)adev->gart.ptr,
--			      adev->gart.table_size >> PAGE_SHIFT);
--	}
--#endif
--	pci_free_consistent(adev->pdev, adev->gart.table_size,
--			    (void *)adev->gart.ptr,
--			    adev->gart.table_addr);
--	adev->gart.ptr = NULL;
--	adev->gart.table_addr = 0;
--}
--
--/**
-  * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
-  *
-  * @adev: amdgpu_device pointer
-@@ -125,75 +68,9 @@ void amdgpu_gart_table_ram_free(struct a
-  */
- int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
- {
--	int r;
--
--	if (adev->gart.robj == NULL) {
--		r = amdgpu_bo_create(adev, adev->gart.table_size,
--				     PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
--				     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
--				     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
--				     NULL, NULL, 0, &adev->gart.robj);
--		if (r) {
--			return r;
--		}
--	}
--	return 0;
--}
--
--/**
-- * amdgpu_gart_table_vram_pin - pin gart page table in vram
-- *
-- * @adev: amdgpu_device pointer
-- *
-- * Pin the GART page table in vram so it will not be moved
-- * by the memory manager (pcie r4xx, r5xx+).  These asics require the
-- * gart table to be in video memory.
-- * Returns 0 for success, error for failure.
-- */
--int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
--{
--	uint64_t gpu_addr;
--	int r;
--
--	r = amdgpu_bo_reserve(adev->gart.robj, false);
--	if (unlikely(r != 0))
--		return r;
--	r = amdgpu_bo_pin(adev->gart.robj,
--				AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
--	if (r) {
--		amdgpu_bo_unreserve(adev->gart.robj);
--		return r;
--	}
--	r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
--	if (r)
--		amdgpu_bo_unpin(adev->gart.robj);
--	amdgpu_bo_unreserve(adev->gart.robj);
--	adev->gart.table_addr = gpu_addr;
--	return r;
--}
--
--/**
-- * amdgpu_gart_table_vram_unpin - unpin gart page table in vram
-- *
-- * @adev: amdgpu_device pointer
-- *
-- * Unpin the GART page table in vram (pcie r4xx, r5xx+).
-- * These asics require the gart table to be in video memory.
-- */
--void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
--{
--	int r;
--
--	if (adev->gart.robj == NULL) {
--		return;
--	}
--	r = amdgpu_bo_reserve(adev->gart.robj, true);
--	if (likely(r == 0)) {
--		amdgpu_bo_kunmap(adev->gart.robj);
--		amdgpu_bo_unpin(adev->gart.robj);
--		amdgpu_bo_unreserve(adev->gart.robj);
--		adev->gart.ptr = NULL;
--	}
-+	return amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE,
-+					AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.robj,
-+					&adev->gart.table_addr, &adev->gart.ptr);
- }
- 
- /**
-@@ -207,10 +84,9 @@ void amdgpu_gart_table_vram_unpin(struct
-  */
- void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
- {
--	if (adev->gart.robj == NULL) {
--		return;
--	}
--	amdgpu_bo_unref(&adev->gart.robj);
-+	amdgpu_bo_free_kernel(&adev->gart.robj,
-+				&adev->gart.table_addr,
-+				&adev->gart.ptr);
- }
- 
- /*
-@@ -332,12 +208,13 @@ int amdgpu_gart_bind(struct amdgpu_devic
- 		adev->gart.pages[p] = pagelist[i];
- #endif
- 
--	if (adev->gart.ptr) {
--		r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
--			    adev->gart.ptr);
--		if (r)
--			return r;
--	}
-+	if (!adev->gart.ptr)
-+		return 0;
-+
-+	r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
-+		    adev->gart.ptr);
-+	if (r)
-+		return r;
- 
- 	mb();
- 	amdgpu_gart_flush_gpu_tlb(adev, 0);
-@@ -376,10 +253,8 @@ int amdgpu_gart_init(struct amdgpu_devic
- #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
- 	/* Allocate pages table */
- 	adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages);
--	if (adev->gart.pages == NULL) {
--		amdgpu_gart_fini(adev);
-+	if (adev->gart.pages == NULL)
- 		return -ENOMEM;
--	}
- #endif
- 
- 	return 0;
-@@ -394,11 +269,6 @@ int amdgpu_gart_init(struct amdgpu_devic
-  */
- void amdgpu_gart_fini(struct amdgpu_device *adev)
- {
--	if (adev->gart.ready) {
--		/* unbind pages */
--		amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages);
--	}
--	adev->gart.ready = false;
- #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
- 	vfree(adev->gart.pages);
- 	adev->gart.pages = NULL;
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h	2017-12-14 06:39:58.378903542 +0100
-@@ -39,7 +39,7 @@ struct amdgpu_gart_funcs;
- #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
- 
- struct amdgpu_gart {
--	dma_addr_t			table_addr;
-+	u64				table_addr;
- 	struct amdgpu_bo		*robj;
- 	void				*ptr;
- 	unsigned			num_gpu_pages;
-@@ -56,12 +56,8 @@ struct amdgpu_gart {
- 	const struct amdgpu_gart_funcs *gart_funcs;
- };
- 
--int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
--void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
- int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
- void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
--int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
--void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
- int amdgpu_gart_init(struct amdgpu_device *adev);
- void amdgpu_gart_fini(struct amdgpu_device *adev);
- int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c	2017-12-14 06:39:58.378903542 +0100
-@@ -44,11 +44,12 @@ void amdgpu_gem_object_free(struct drm_g
- }
- 
- int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
--				int alignment, u32 initial_domain,
--				u64 flags, bool kernel,
--				struct drm_gem_object **obj)
-+			     int alignment, u32 initial_domain,
-+			     u64 flags, bool kernel,
-+			     struct reservation_object *resv,
-+			     struct drm_gem_object **obj)
- {
--	struct amdgpu_bo *robj;
-+	struct amdgpu_bo *bo;
- 	int r;
- 
- 	*obj = NULL;
-@@ -59,19 +60,24 @@ int amdgpu_gem_object_create(struct amdg
- 
- retry:
- 	r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
--			     flags, NULL, NULL, 0, &robj);
-+			     flags, NULL, resv, 0, &bo);
- 	if (r) {
- 		if (r != -ERESTARTSYS) {
-+			if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
-+				flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
-+				goto retry;
-+			}
-+
- 			if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
- 				initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
- 				goto retry;
- 			}
--			DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
-+			DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
- 				  size, initial_domain, alignment, r);
- 		}
- 		return r;
- 	}
--	*obj = &robj->gem_base;
-+	*obj = &bo->gem_base;
- 
- 	return 0;
- }
-@@ -112,7 +118,17 @@ int amdgpu_gem_object_open(struct drm_ge
- 	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
- 	struct amdgpu_vm *vm = &fpriv->vm;
- 	struct amdgpu_bo_va *bo_va;
-+	struct mm_struct *mm;
- 	int r;
-+
-+	mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
-+	if (mm && mm != current->mm)
-+		return -EPERM;
-+
-+	if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
-+	    abo->tbo.resv != vm->root.base.bo->tbo.resv)
-+		return -EPERM;
-+
- 	r = amdgpu_bo_reserve(abo, false);
- 	if (r)
- 		return r;
-@@ -127,35 +143,6 @@ int amdgpu_gem_object_open(struct drm_ge
- 	return 0;
- }
- 
--static int amdgpu_gem_vm_check(void *param, struct amdgpu_bo *bo)
--{
--	/* if anything is swapped out don't swap it in here,
--	   just abort and wait for the next CS */
--	if (!amdgpu_bo_gpu_accessible(bo))
--		return -ERESTARTSYS;
--
--	if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow))
--		return -ERESTARTSYS;
--
--	return 0;
--}
--
--static bool amdgpu_gem_vm_ready(struct amdgpu_device *adev,
--				struct amdgpu_vm *vm,
--				struct list_head *list)
--{
--	struct ttm_validate_buffer *entry;
--
--	list_for_each_entry(entry, list, head) {
--		struct amdgpu_bo *bo =
--			container_of(entry->bo, struct amdgpu_bo, tbo);
--		if (amdgpu_gem_vm_check(NULL, bo))
--			return false;
--	}
--
--	return !amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_gem_vm_check, NULL);
--}
--
- void amdgpu_gem_object_close(struct drm_gem_object *obj,
- 			     struct drm_file *file_priv)
- {
-@@ -165,13 +152,14 @@ void amdgpu_gem_object_close(struct drm_
- 	struct amdgpu_vm *vm = &fpriv->vm;
- 
- 	struct amdgpu_bo_list_entry vm_pd;
--	struct list_head list;
-+	struct list_head list, duplicates;
- 	struct ttm_validate_buffer tv;
- 	struct ww_acquire_ctx ticket;
- 	struct amdgpu_bo_va *bo_va;
- 	int r;
- 
- 	INIT_LIST_HEAD(&list);
-+	INIT_LIST_HEAD(&duplicates);
- 
- 	tv.bo = &bo->tbo;
- 	tv.shared = true;
-@@ -179,7 +167,7 @@ void amdgpu_gem_object_close(struct drm_
- 
- 	amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
- 
--	r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
-+	r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
- 	if (r) {
- 		dev_err(adev->dev, "leaking bo va because "
- 			"we fail to reserve bo (%d)\n", r);
-@@ -189,7 +177,7 @@ void amdgpu_gem_object_close(struct drm_
- 	if (bo_va && --bo_va->ref_count == 0) {
- 		amdgpu_vm_bo_rmv(adev, bo_va);
- 
--		if (amdgpu_gem_vm_ready(adev, vm, &list)) {
-+		if (amdgpu_vm_ready(vm)) {
- 			struct dma_fence *fence = NULL;
- 
- 			r = amdgpu_vm_clear_freed(adev, vm, &fence);
-@@ -214,18 +202,24 @@ int amdgpu_gem_create_ioctl(struct drm_d
- 			    struct drm_file *filp)
- {
- 	struct amdgpu_device *adev = dev->dev_private;
-+	struct amdgpu_fpriv *fpriv = filp->driver_priv;
-+	struct amdgpu_vm *vm = &fpriv->vm;
- 	union drm_amdgpu_gem_create *args = data;
-+	uint64_t flags = args->in.domain_flags;
- 	uint64_t size = args->in.bo_size;
-+	struct reservation_object *resv = NULL;
- 	struct drm_gem_object *gobj;
- 	uint32_t handle;
--	bool kernel = false;
- 	int r;
- 
- 	/* reject invalid gem flags */
--	if (args->in.domain_flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
--				      AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
--				      AMDGPU_GEM_CREATE_CPU_GTT_USWC |
--				      AMDGPU_GEM_CREATE_VRAM_CLEARED))
-+	if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
-+		      AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
-+		      AMDGPU_GEM_CREATE_CPU_GTT_USWC |
-+		      AMDGPU_GEM_CREATE_VRAM_CLEARED |
-+		      AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
-+		      AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
-+
- 		return -EINVAL;
- 
- 	/* reject invalid gem domains */
-@@ -240,7 +234,7 @@ int amdgpu_gem_create_ioctl(struct drm_d
- 	/* create a gem object to contain this object in */
- 	if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
- 	    AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
--		kernel = true;
-+		flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
- 		if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
- 			size = size << AMDGPU_GDS_SHIFT;
- 		else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
-@@ -252,10 +246,25 @@ int amdgpu_gem_create_ioctl(struct drm_d
- 	}
- 	size = roundup(size, PAGE_SIZE);
- 
-+	if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
-+		r = amdgpu_bo_reserve(vm->root.base.bo, false);
-+		if (r)
-+			return r;
-+
-+		resv = vm->root.base.bo->tbo.resv;
-+	}
-+
- 	r = amdgpu_gem_object_create(adev, size, args->in.alignment,
- 				     (u32)(0xffffffff & args->in.domains),
--				     args->in.domain_flags,
--				     kernel, &gobj);
-+				     flags, false, resv, &gobj);
-+	if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
-+		if (!r) {
-+			struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
-+
-+			abo->parent = amdgpu_bo_ref(vm->root.base.bo);
-+		}
-+		amdgpu_bo_unreserve(vm->root.base.bo);
-+	}
- 	if (r)
- 		return r;
- 
-@@ -297,9 +306,8 @@ int amdgpu_gem_userptr_ioctl(struct drm_
- 	}
- 
- 	/* create a gem object to contain this object in */
--	r = amdgpu_gem_object_create(adev, args->size, 0,
--				     AMDGPU_GEM_DOMAIN_CPU, 0,
--				     0, &gobj);
-+	r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
-+				     0, 0, NULL, &gobj);
- 	if (r)
- 		return r;
- 
-@@ -317,8 +325,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_
- 	}
- 
- 	if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
--		down_read(&current->mm->mmap_sem);
--
- 		r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
- 						 bo->tbo.ttm->pages);
- 		if (r)
-@@ -333,8 +339,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_
- 		amdgpu_bo_unreserve(bo);
- 		if (r)
- 			goto free_pages;
--
--		up_read(&current->mm->mmap_sem);
- 	}
- 
- 	r = drm_gem_handle_create(filp, gobj, &handle);
-@@ -511,10 +515,10 @@ static void amdgpu_gem_va_update_vm(stru
- 				    struct list_head *list,
- 				    uint32_t operation)
- {
--	int r = -ERESTARTSYS;
-+	int r;
- 
--	if (!amdgpu_gem_vm_ready(adev, vm, list))
--		goto error;
-+	if (!amdgpu_vm_ready(vm))
-+		return;
- 
- 	r = amdgpu_vm_update_directories(adev, vm);
- 	if (r)
-@@ -551,15 +555,14 @@ int amdgpu_gem_va_ioctl(struct drm_devic
- 	struct amdgpu_bo_list_entry vm_pd;
- 	struct ttm_validate_buffer tv;
- 	struct ww_acquire_ctx ticket;
--	struct list_head list;
-+	struct list_head list, duplicates;
- 	uint64_t va_flags;
- 	int r = 0;
- 
- 	if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
- 		dev_err(&dev->pdev->dev,
--			"va_address 0x%lX is in reserved area 0x%X\n",
--			(unsigned long)args->va_address,
--			AMDGPU_VA_RESERVED_SIZE);
-+			"va_address 0x%LX is in reserved area 0x%LX\n",
-+			args->va_address, AMDGPU_VA_RESERVED_SIZE);
- 		return -EINVAL;
- 	}
- 
-@@ -580,13 +583,9 @@ int amdgpu_gem_va_ioctl(struct drm_devic
- 			args->operation);
- 		return -EINVAL;
- 	}
--	if ((args->operation == AMDGPU_VA_OP_MAP) ||
--	    (args->operation == AMDGPU_VA_OP_REPLACE)) {
--		if (amdgpu_kms_vram_lost(adev, fpriv))
--			return -ENODEV;
--	}
- 
- 	INIT_LIST_HEAD(&list);
-+	INIT_LIST_HEAD(&duplicates);
- 	if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
- 	    !(args->flags & AMDGPU_VM_PAGE_PRT)) {
- 		gobj = drm_gem_object_lookup(filp, args->handle);
-@@ -603,7 +602,7 @@ int amdgpu_gem_va_ioctl(struct drm_devic
- 
- 	amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
- 
--	r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
-+	r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
- 	if (r)
- 		goto error_unref;
- 
-@@ -669,6 +668,7 @@ error_unref:
- int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
- 			struct drm_file *filp)
- {
-+	struct amdgpu_device *adev = dev->dev_private;
- 	struct drm_amdgpu_gem_op *args = data;
- 	struct drm_gem_object *gobj;
- 	struct amdgpu_bo *robj;
-@@ -716,6 +716,9 @@ int amdgpu_gem_op_ioctl(struct drm_devic
- 		if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
- 			robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
- 
-+		if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
-+			amdgpu_vm_bo_invalidate(adev, robj, true);
-+
- 		amdgpu_bo_unreserve(robj);
- 		break;
- 	default:
-@@ -745,8 +748,7 @@ int amdgpu_mode_dumb_create(struct drm_f
- 	r = amdgpu_gem_object_create(adev, args->size, 0,
- 				     AMDGPU_GEM_DOMAIN_VRAM,
- 				     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
--				     ttm_bo_type_device,
--				     &gobj);
-+				     false, NULL, &gobj);
- 	if (r)
- 		return -ENOMEM;
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c	2017-12-14 06:39:58.379903542 +0100
-@@ -109,9 +109,26 @@ void amdgpu_gfx_parse_disable_cu(unsigne
- 	}
- }
- 
-+static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
-+{
-+	if (amdgpu_compute_multipipe != -1) {
-+		DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
-+			 amdgpu_compute_multipipe);
-+		return amdgpu_compute_multipipe == 1;
-+	}
-+
-+	/* FIXME: spreading the queues across pipes causes perf regressions
-+	 * on POLARIS11 compute workloads */
-+	if (adev->asic_type == CHIP_POLARIS11)
-+		return false;
-+
-+	return adev->gfx.mec.num_mec > 1;
-+}
-+
- void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
- {
- 	int i, queue, pipe, mec;
-+	bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
- 
- 	/* policy for amdgpu compute queue ownership */
- 	for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
-@@ -125,8 +142,7 @@ void amdgpu_gfx_compute_queue_acquire(st
- 		if (mec >= adev->gfx.mec.num_mec)
- 			break;
- 
--		/* FIXME: spreading the queues across pipes causes perf regressions */
--		if (0) {
-+		if (multipipe_policy) {
- 			/* policy: amdgpu owns the first two queues of the first MEC */
- 			if (mec == 0 && queue < 2)
- 				set_bit(i, adev->gfx.mec.queue_bitmap);
-@@ -185,7 +201,7 @@ int amdgpu_gfx_kiq_init_ring(struct amdg
- 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
- 	int r = 0;
- 
--	mutex_init(&kiq->ring_mutex);
-+	spin_lock_init(&kiq->ring_lock);
- 
- 	r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
- 	if (r)
-@@ -260,8 +276,13 @@ int amdgpu_gfx_compute_mqd_sw_init(struc
- 	/* create MQD for KIQ */
- 	ring = &adev->gfx.kiq.ring;
- 	if (!ring->mqd_obj) {
-+		/* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
-+		 * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
-+		 * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
-+		 * KIQ MQD no matter SRIOV or Bare-metal
-+		 */
- 		r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
--					    AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
-+					    AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
- 					    &ring->mqd_gpu_addr, &ring->mqd_ptr);
- 		if (r) {
- 			dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c	2017-12-14 06:39:58.379903542 +0100
-@@ -31,6 +31,11 @@ struct amdgpu_gtt_mgr {
- 	atomic64_t available;
- };
- 
-+struct amdgpu_gtt_node {
-+	struct drm_mm_node node;
-+	struct ttm_buffer_object *tbo;
-+};
-+
- /**
-  * amdgpu_gtt_mgr_init - init GTT manager and DRM MM
-  *
-@@ -71,12 +76,6 @@ static int amdgpu_gtt_mgr_fini(struct tt
- {
- 	struct amdgpu_gtt_mgr *mgr = man->priv;
- 
--	spin_lock(&mgr->lock);
--	if (!drm_mm_clean(&mgr->mm)) {
--		spin_unlock(&mgr->lock);
--		return -EBUSY;
--	}
--
- 	drm_mm_takedown(&mgr->mm);
- 	spin_unlock(&mgr->lock);
- 	kfree(mgr);
-@@ -85,17 +84,17 @@ static int amdgpu_gtt_mgr_fini(struct tt
- }
- 
- /**
-- * amdgpu_gtt_mgr_is_allocated - Check if mem has address space
-+ * amdgpu_gtt_mgr_has_gart_addr - Check if mem has address space
-  *
-  * @mem: the mem object to check
-  *
-  * Check if a mem object has already address space allocated.
-  */
--bool amdgpu_gtt_mgr_is_allocated(struct ttm_mem_reg *mem)
-+bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem)
- {
--	struct drm_mm_node *node = mem->mm_node;
-+	struct amdgpu_gtt_node *node = mem->mm_node;
- 
--	return (node->start != AMDGPU_BO_INVALID_OFFSET);
-+	return (node->node.start != AMDGPU_BO_INVALID_OFFSET);
- }
- 
- /**
-@@ -115,12 +114,12 @@ static int amdgpu_gtt_mgr_alloc(struct t
- {
- 	struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
- 	struct amdgpu_gtt_mgr *mgr = man->priv;
--	struct drm_mm_node *node = mem->mm_node;
-+	struct amdgpu_gtt_node *node = mem->mm_node;
- 	enum drm_mm_insert_mode mode;
- 	unsigned long fpfn, lpfn;
- 	int r;
- 
--	if (amdgpu_gtt_mgr_is_allocated(mem))
-+	if (amdgpu_gtt_mgr_has_gart_addr(mem))
- 		return 0;
- 
- 	if (place)
-@@ -138,13 +137,13 @@ static int amdgpu_gtt_mgr_alloc(struct t
- 		mode = DRM_MM_INSERT_HIGH;
- 
- 	spin_lock(&mgr->lock);
--	r = drm_mm_insert_node_in_range(&mgr->mm, node,
--					mem->num_pages, mem->page_alignment, 0,
--					fpfn, lpfn, mode);
-+	r = drm_mm_insert_node_in_range(&mgr->mm, &node->node, mem->num_pages,
-+					mem->page_alignment, 0, fpfn, lpfn,
-+					mode);
- 	spin_unlock(&mgr->lock);
- 
- 	if (!r)
--		mem->start = node->start;
-+		mem->start = node->node.start;
- 
- 	return r;
- }
-@@ -165,11 +164,12 @@ static int amdgpu_gtt_mgr_new(struct ttm
- 			      struct ttm_mem_reg *mem)
- {
- 	struct amdgpu_gtt_mgr *mgr = man->priv;
--	struct drm_mm_node *node;
-+	struct amdgpu_gtt_node *node;
- 	int r;
- 
- 	spin_lock(&mgr->lock);
--	if (atomic64_read(&mgr->available) < mem->num_pages) {
-+	if ((&tbo->mem == mem || tbo->mem.mem_type != TTM_PL_TT) &&
-+	    atomic64_read(&mgr->available) < mem->num_pages) {
- 		spin_unlock(&mgr->lock);
- 		return 0;
- 	}
-@@ -182,8 +182,9 @@ static int amdgpu_gtt_mgr_new(struct ttm
- 		goto err_out;
- 	}
- 
--	node->start = AMDGPU_BO_INVALID_OFFSET;
--	node->size = mem->num_pages;
-+	node->node.start = AMDGPU_BO_INVALID_OFFSET;
-+	node->node.size = mem->num_pages;
-+	node->tbo = tbo;
- 	mem->mm_node = node;
- 
- 	if (place->fpfn || place->lpfn || place->flags & TTM_PL_FLAG_TOPDOWN) {
-@@ -195,7 +196,7 @@ static int amdgpu_gtt_mgr_new(struct ttm
- 			goto err_out;
- 		}
- 	} else {
--		mem->start = node->start;
-+		mem->start = node->node.start;
- 	}
- 
- 	return 0;
-@@ -219,14 +220,14 @@ static void amdgpu_gtt_mgr_del(struct tt
- 			       struct ttm_mem_reg *mem)
- {
- 	struct amdgpu_gtt_mgr *mgr = man->priv;
--	struct drm_mm_node *node = mem->mm_node;
-+	struct amdgpu_gtt_node *node = mem->mm_node;
- 
- 	if (!node)
- 		return;
- 
- 	spin_lock(&mgr->lock);
--	if (node->start != AMDGPU_BO_INVALID_OFFSET)
--		drm_mm_remove_node(node);
-+	if (node->node.start != AMDGPU_BO_INVALID_OFFSET)
-+		drm_mm_remove_node(&node->node);
- 	spin_unlock(&mgr->lock);
- 	atomic64_add(mem->num_pages, &mgr->available);
- 
-@@ -244,8 +245,28 @@ static void amdgpu_gtt_mgr_del(struct tt
- uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man)
- {
- 	struct amdgpu_gtt_mgr *mgr = man->priv;
-+	s64 result = man->size - atomic64_read(&mgr->available);
-+
-+	return (result > 0 ? result : 0) * PAGE_SIZE;
-+}
-+
-+int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man)
-+{
-+	struct amdgpu_gtt_mgr *mgr = man->priv;
-+	struct amdgpu_gtt_node *node;
-+	struct drm_mm_node *mm_node;
-+	int r = 0;
-+
-+	spin_lock(&mgr->lock);
-+	drm_mm_for_each_node(mm_node, &mgr->mm) {
-+		node = container_of(mm_node, struct amdgpu_gtt_node, node);
-+		r = amdgpu_ttm_recover_gart(node->tbo);
-+		if (r)
-+			break;
-+	}
-+	spin_unlock(&mgr->lock);
- 
--	return (u64)(man->size - atomic64_read(&mgr->available)) * PAGE_SIZE;
-+	return r;
- }
- 
- /**
-@@ -265,7 +286,7 @@ static void amdgpu_gtt_mgr_debug(struct
- 	drm_mm_print(&mgr->mm, printer);
- 	spin_unlock(&mgr->lock);
- 
--	drm_printf(printer, "man size:%llu pages, gtt available:%llu pages, usage:%lluMB\n",
-+	drm_printf(printer, "man size:%llu pages, gtt available:%lld pages, usage:%lluMB\n",
- 		   man->size, (u64)atomic64_read(&mgr->available),
- 		   amdgpu_gtt_mgr_usage(man) >> 20);
- }
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu.h.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu.h	2017-12-14 06:39:58.379903542 +0100
-@@ -47,6 +47,8 @@
- #include <drm/amdgpu_drm.h>
- 
- #include <kgd_kfd_interface.h>
-+#include "dm_pp_interface.h"
-+#include "kgd_pp_interface.h"
- 
- #include "amd_shared.h"
- #include "amdgpu_mode.h"
-@@ -59,17 +61,18 @@
- #include "amdgpu_sync.h"
- #include "amdgpu_ring.h"
- #include "amdgpu_vm.h"
--#include "amd_powerplay.h"
- #include "amdgpu_dpm.h"
- #include "amdgpu_acp.h"
- #include "amdgpu_uvd.h"
- #include "amdgpu_vce.h"
- #include "amdgpu_vcn.h"
--
-+#include "amdgpu_mn.h"
-+#include "amdgpu_dm.h"
- #include "gpu_scheduler.h"
- #include "amdgpu_virt.h"
- #include "amdgpu_gart.h"
- 
-+
- /*
-  * Modules parameters.
-  */
-@@ -91,7 +94,7 @@ extern int amdgpu_dpm;
- extern int amdgpu_fw_load_type;
- extern int amdgpu_aspm;
- extern int amdgpu_runtime_pm;
--extern unsigned amdgpu_ip_block_mask;
-+extern uint amdgpu_ip_block_mask;
- extern int amdgpu_bapm;
- extern int amdgpu_deep_color;
- extern int amdgpu_vm_size;
-@@ -100,18 +103,20 @@ extern int amdgpu_vm_fragment_size;
- extern int amdgpu_vm_fault_stop;
- extern int amdgpu_vm_debug;
- extern int amdgpu_vm_update_mode;
-+extern int amdgpu_dc;
-+extern int amdgpu_dc_log;
- extern int amdgpu_sched_jobs;
- extern int amdgpu_sched_hw_submission;
- extern int amdgpu_no_evict;
- extern int amdgpu_direct_gma_size;
--extern unsigned amdgpu_pcie_gen_cap;
--extern unsigned amdgpu_pcie_lane_cap;
--extern unsigned amdgpu_cg_mask;
--extern unsigned amdgpu_pg_mask;
--extern unsigned amdgpu_sdma_phase_quantum;
-+extern uint amdgpu_pcie_gen_cap;
-+extern uint amdgpu_pcie_lane_cap;
-+extern uint amdgpu_cg_mask;
-+extern uint amdgpu_pg_mask;
-+extern uint amdgpu_sdma_phase_quantum;
- extern char *amdgpu_disable_cu;
- extern char *amdgpu_virtual_display;
--extern unsigned amdgpu_pp_feature_mask;
-+extern uint amdgpu_pp_feature_mask;
- extern int amdgpu_vram_page_split;
- extern int amdgpu_ngg;
- extern int amdgpu_prim_buf_per_se;
-@@ -120,6 +125,7 @@ extern int amdgpu_cntl_sb_buf_per_se;
- extern int amdgpu_param_buf_per_se;
- extern int amdgpu_job_hang_limit;
- extern int amdgpu_lbpw;
-+extern int amdgpu_compute_multipipe;
- 
- #ifdef CONFIG_DRM_AMDGPU_SI
- extern int amdgpu_si_support;
-@@ -172,12 +178,17 @@ extern int amdgpu_cik_support;
- #define CIK_CURSOR_WIDTH 128
- #define CIK_CURSOR_HEIGHT 128
- 
-+/* GPU RESET flags */
-+#define AMDGPU_RESET_INFO_VRAM_LOST  (1 << 0)
-+#define AMDGPU_RESET_INFO_FULLRESET  (1 << 1)
-+
- struct amdgpu_device;
- struct amdgpu_ib;
- struct amdgpu_cs_parser;
- struct amdgpu_job;
- struct amdgpu_irq_src;
- struct amdgpu_fpriv;
-+struct amdgpu_bo_va_mapping;
- 
- enum amdgpu_cp_irq {
- 	AMDGPU_CP_IRQ_GFX_EOP = 0,
-@@ -292,14 +303,25 @@ struct amdgpu_buffer_funcs {
- 
- /* provided by hw blocks that can write ptes, e.g., sdma */
- struct amdgpu_vm_pte_funcs {
-+	/* number of dw to reserve per operation */
-+	unsigned	copy_pte_num_dw;
-+
- 	/* copy pte entries from GART */
- 	void (*copy_pte)(struct amdgpu_ib *ib,
- 			 uint64_t pe, uint64_t src,
- 			 unsigned count);
-+
- 	/* write pte one entry at a time with addr mapping */
- 	void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
- 			  uint64_t value, unsigned count,
- 			  uint32_t incr);
-+
-+	/* maximum nums of PTEs/PDEs in a single operation */
-+	uint32_t	set_max_nums_pte_pde;
-+
-+	/* number of dw to reserve per operation */
-+	unsigned	set_pte_pde_num_dw;
-+
- 	/* for linear pte/pde updates without addr mapping */
- 	void (*set_pte_pde)(struct amdgpu_ib *ib,
- 			    uint64_t pe,
-@@ -332,6 +354,7 @@ struct amdgpu_gart_funcs {
- struct amdgpu_ih_funcs {
- 	/* ring read/write ptr handling, called from interrupt context */
- 	u32 (*get_wptr)(struct amdgpu_device *adev);
-+	bool (*prescreen_iv)(struct amdgpu_device *adev);
- 	void (*decode_iv)(struct amdgpu_device *adev,
- 			  struct amdgpu_iv_entry *entry);
- 	void (*set_rptr)(struct amdgpu_device *adev);
-@@ -399,6 +422,7 @@ void amdgpu_gem_prime_unpin(struct drm_g
- struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
- void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
- void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
-+int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
- int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
- 
- /* sub-allocation manager, it has to be protected by another lock.
-@@ -455,9 +479,10 @@ struct amdgpu_sa_bo {
-  */
- void amdgpu_gem_force_release(struct amdgpu_device *adev);
- int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
--				int alignment, u32 initial_domain,
--				u64 flags, bool kernel,
--				struct drm_gem_object **obj);
-+			     int alignment, u32 initial_domain,
-+			     u64 flags, bool kernel,
-+			     struct reservation_object *resv,
-+			     struct drm_gem_object **obj);
- 
- int amdgpu_mode_dumb_create(struct drm_file *file_priv,
- 			    struct drm_device *dev,
-@@ -715,10 +740,16 @@ struct amdgpu_ctx {
- 	struct amdgpu_device    *adev;
- 	struct amdgpu_queue_mgr queue_mgr;
- 	unsigned		reset_counter;
-+	unsigned        reset_counter_query;
-+	uint32_t		vram_lost_counter;
- 	spinlock_t		ring_lock;
- 	struct dma_fence	**fences;
- 	struct amdgpu_ctx_ring	rings[AMDGPU_MAX_RINGS];
--	bool preamble_presented;
-+	bool			preamble_presented;
-+	enum amd_sched_priority init_priority;
-+	enum amd_sched_priority override_priority;
-+	struct mutex            lock;
-+	atomic_t	guilty;
- };
- 
- struct amdgpu_ctx_mgr {
-@@ -731,17 +762,22 @@ struct amdgpu_ctx_mgr {
- struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
- int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
- 
--uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
--			      struct dma_fence *fence);
-+int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
-+			      struct dma_fence *fence, uint64_t *seq);
- struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
- 				   struct amdgpu_ring *ring, uint64_t seq);
-+void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
-+				  enum amd_sched_priority priority);
- 
- int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
- 		     struct drm_file *filp);
- 
-+int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
-+
- void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
- void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
- 
-+
- /*
-  * file private structure
-  */
-@@ -753,7 +789,6 @@ struct amdgpu_fpriv {
- 	struct mutex		bo_list_lock;
- 	struct idr		bo_list_handles;
- 	struct amdgpu_ctx_mgr	ctx_mgr;
--	u32			vram_lost_counter;
- };
- 
- /*
-@@ -854,7 +889,7 @@ struct amdgpu_mec {
- struct amdgpu_kiq {
- 	u64			eop_gpu_addr;
- 	struct amdgpu_bo	*eop_obj;
--	struct mutex		ring_mutex;
-+	spinlock_t              ring_lock;
- 	struct amdgpu_ring	ring;
- 	struct amdgpu_irq_src	irq;
- };
-@@ -1014,11 +1049,14 @@ struct amdgpu_gfx {
- 	/* reset mask */
- 	uint32_t                        grbm_soft_reset;
- 	uint32_t                        srbm_soft_reset;
--	bool                            in_reset;
- 	/* s3/s4 mask */
- 	bool                            in_suspend;
- 	/* NGG */
- 	struct amdgpu_ngg		ngg;
-+
-+	/* pipe reservation */
-+	struct mutex			pipe_reserve_mutex;
-+	DECLARE_BITMAP			(pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
- };
- 
- int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
-@@ -1056,6 +1094,7 @@ struct amdgpu_cs_parser {
- 	/* buffer objects */
- 	struct ww_acquire_ctx		ticket;
- 	struct amdgpu_bo_list		*bo_list;
-+	struct amdgpu_mn		*mn;
- 	struct amdgpu_bo_list_entry	vm_pd;
- 	struct list_head		validated;
- 	struct dma_fence		*fence;
-@@ -1096,6 +1135,7 @@ struct amdgpu_job {
- 	uint32_t		gds_base, gds_size;
- 	uint32_t		gws_base, gws_size;
- 	uint32_t		oa_base, oa_size;
-+	uint32_t		vram_lost_counter;
- 
- 	/* user fence handling */
- 	uint64_t		uf_addr;
-@@ -1121,7 +1161,7 @@ static inline void amdgpu_set_ib_value(s
- /*
-  * Writeback
-  */
--#define AMDGPU_MAX_WB 1024	/* Reserve at most 1024 WB slots for amdgpu-owned rings. */
-+#define AMDGPU_MAX_WB 512	/* Reserve at most 512 WB slots for amdgpu-owned rings. */
- 
- struct amdgpu_wb {
- 	struct amdgpu_bo	*wb_obj;
-@@ -1183,6 +1223,9 @@ struct amdgpu_firmware {
- 
- 	/* gpu info firmware data pointer */
- 	const struct firmware *gpu_info_fw;
-+
-+	void *fw_buf_ptr;
-+	uint64_t fw_buf_mc;
- };
- 
- /*
-@@ -1197,20 +1240,6 @@ void amdgpu_benchmark(struct amdgpu_devi
- void amdgpu_test_moves(struct amdgpu_device *adev);
- 
- /*
-- * MMU Notifier
-- */
--#if defined(CONFIG_MMU_NOTIFIER)
--int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
--void amdgpu_mn_unregister(struct amdgpu_bo *bo);
--#else
--static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
--{
--	return -ENODEV;
--}
--static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
--#endif
--
--/*
-  * Debugfs
-  */
- struct amdgpu_debugfs {
-@@ -1305,6 +1334,8 @@ int amdgpu_gem_va_ioctl(struct drm_devic
- int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
- 			struct drm_file *filp);
- int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
-+int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
-+				    struct drm_file *filp);
- int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
- int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
- 				struct drm_file *filp);
-@@ -1312,6 +1343,9 @@ int amdgpu_cs_wait_fences_ioctl(struct d
- int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
- 				struct drm_file *filp);
- 
-+int amdgpu_freesync_ioctl(struct drm_device *dev, void *data,
-+			    struct drm_file *filp);
-+
- /* VRAM scratch page for HDP bug, default vram page */
- struct amdgpu_vram_scratch {
- 	struct amdgpu_bo		*robj;
-@@ -1371,6 +1405,19 @@ struct amdgpu_atcs {
- };
- 
- /*
-+ * Firmware VRAM reservation
-+ */
-+struct amdgpu_fw_vram_usage {
-+	u64 start_offset;
-+	u64 size;
-+	struct amdgpu_bo *reserved_bo;
-+	void *va;
-+};
-+
-+int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);
-+void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev);
-+
-+/*
-  * CGS
-  */
- struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
-@@ -1385,6 +1432,13 @@ typedef void (*amdgpu_wreg_t)(struct amd
- typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
- typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
- 
-+struct amd_powerplay {
-+	struct cgs_device *cgs_device;
-+	void *pp_handle;
-+	const struct amd_ip_funcs *ip_funcs;
-+	const struct amd_pm_funcs *pp_funcs;
-+};
-+
- #define AMDGPU_RESET_MAGIC_NUM 64
- struct amdgpu_device {
- 	struct device			*dev;
-@@ -1502,6 +1556,7 @@ struct amdgpu_device {
- 	/* display */
- 	bool				enable_virtual_display;
- 	struct amdgpu_mode_info		mode_info;
-+	/* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
- 	struct work_struct		hotplug_work;
- 	struct amdgpu_irq_src		crtc_irq;
- 	struct amdgpu_irq_src		pageflip_irq;
-@@ -1519,7 +1574,6 @@ struct amdgpu_device {
- 
- 	/* powerplay */
- 	struct amd_powerplay		powerplay;
--	bool				pp_enabled;
- 	bool				pp_force_state_enabled;
- 
- 	/* dpm */
-@@ -1554,6 +1608,9 @@ struct amdgpu_device {
- 	/* GDS */
- 	struct amdgpu_gds		gds;
- 
-+	/* display related functionality */
-+	struct amdgpu_display_manager dm;
-+
- 	struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];
- 	int				num_ip_blocks;
- 	struct mutex	mn_lock;
-@@ -1571,13 +1628,12 @@ struct amdgpu_device {
- 	struct delayed_work     late_init_work;
- 
- 	struct amdgpu_virt	virt;
-+	/* firmware VRAM reservation */
-+	struct amdgpu_fw_vram_usage fw_vram_usage;
- 
- 	/* link all shadow bo */
- 	struct list_head                shadow_list;
- 	struct mutex                    shadow_list_lock;
--	/* link all gtt */
--	spinlock_t			gtt_list_lock;
--	struct list_head                gtt_list;
- 	/* keep an lru list of rings by HW IP */
- 	struct list_head		ring_lru_list;
- 	spinlock_t			ring_lru_list_lock;
-@@ -1588,6 +1644,8 @@ struct amdgpu_device {
- 
- 	/* record last mm index being written through WREG32*/
- 	unsigned long last_mm_index;
-+	bool                            in_gpu_reset;
-+	struct mutex  lock_reset;
- };
- 
- static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
-@@ -1614,6 +1672,9 @@ void amdgpu_mm_wdoorbell(struct amdgpu_d
- u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
- void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
- 
-+bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
-+bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
-+
- /*
-  * Registers read & write functions.
-  */
-@@ -1755,6 +1816,7 @@ amdgpu_get_sdma_instance(struct amdgpu_r
- #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
- #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
- #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
-+#define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev))
- #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
- #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
- #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
-@@ -1777,7 +1839,7 @@ amdgpu_get_sdma_instance(struct amdgpu_r
- #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
- 
- /* Common functions */
--int amdgpu_gpu_reset(struct amdgpu_device *adev);
-+int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job);
- bool amdgpu_need_backup(struct amdgpu_device *adev);
- void amdgpu_pci_config_reset(struct amdgpu_device *adev);
- bool amdgpu_need_post(struct amdgpu_device *adev);
-@@ -1787,20 +1849,9 @@ void amdgpu_cs_report_moved_bytes(struct
- 				  u64 num_vis_bytes);
- void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
- bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
--int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
--int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
--				     uint32_t flags);
--bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
--struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
--bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
--				  unsigned long end);
--bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
--				       int *last_invalidated);
--bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
--uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
--				 struct ttm_mem_reg *mem);
- void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
- void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
-+int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
- void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
- int amdgpu_ttm_init(struct amdgpu_device *adev);
- void amdgpu_ttm_fini(struct amdgpu_device *adev);
-@@ -1832,8 +1883,6 @@ static inline bool amdgpu_has_atpx(void)
- extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
- extern const int amdgpu_max_kms_ioctl;
- 
--bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
--			  struct amdgpu_fpriv *fpriv);
- int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
- void amdgpu_driver_unload_kms(struct drm_device *dev);
- void amdgpu_driver_lastclose_kms(struct drm_device *dev);
-@@ -1881,10 +1930,15 @@ static inline int amdgpu_acpi_init(struc
- static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
- #endif
- 
--struct amdgpu_bo_va_mapping *
--amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
--		       uint64_t addr, struct amdgpu_bo **bo);
--int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
-+int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
-+			   uint64_t addr, struct amdgpu_bo **bo,
-+			   struct amdgpu_bo_va_mapping **mapping);
-+
-+#if defined(CONFIG_DRM_AMD_DC)
-+int amdgpu_dm_display_resume(struct amdgpu_device *adev );
-+#else
-+static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
-+#endif
- 
- #include "amdgpu_object.h"
- #endif
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c	2017-12-14 06:39:58.379903542 +0100
-@@ -169,6 +169,12 @@ restart_ih:
- 	while (adev->irq.ih.rptr != wptr) {
- 		u32 ring_index = adev->irq.ih.rptr >> 2;
- 
-+		/* Prescreening of high-frequency interrupts */
-+		if (!amdgpu_ih_prescreen_iv(adev)) {
-+			adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
-+			continue;
-+		}
-+
- 		/* Before dispatching irq to IP blocks, send it to amdkfd */
- 		amdgpu_amdkfd_interrupt(adev,
- 				(const void *) &adev->irq.ih.ring[ring_index]);
-@@ -190,3 +196,79 @@ restart_ih:
- 
- 	return IRQ_HANDLED;
- }
-+
-+/**
-+ * amdgpu_ih_add_fault - Add a page fault record
-+ *
-+ * @adev: amdgpu device pointer
-+ * @key: 64-bit encoding of PASID and address
-+ *
-+ * This should be called when a retry page fault interrupt is
-+ * received. If this is a new page fault, it will be added to a hash
-+ * table. The return value indicates whether this is a new fault, or
-+ * a fault that was already known and is already being handled.
-+ *
-+ * If there are too many pending page faults, this will fail. Retry
-+ * interrupts should be ignored in this case until there is enough
-+ * free space.
-+ *
-+ * Returns 0 if the fault was added, 1 if the fault was already known,
-+ * -ENOSPC if there are too many pending faults.
-+ */
-+int amdgpu_ih_add_fault(struct amdgpu_device *adev, u64 key)
-+{
-+	unsigned long flags;
-+	int r = -ENOSPC;
-+
-+	if (WARN_ON_ONCE(!adev->irq.ih.faults))
-+		/* Should be allocated in <IP>_ih_sw_init on GPUs that
-+		 * support retry faults and require retry filtering.
-+		 */
-+		return r;
-+
-+	spin_lock_irqsave(&adev->irq.ih.faults->lock, flags);
-+
-+	/* Only let the hash table fill up to 50% for best performance */
-+	if (adev->irq.ih.faults->count >= (1 << (AMDGPU_PAGEFAULT_HASH_BITS-1)))
-+		goto unlock_out;
-+
-+	r = chash_table_copy_in(&adev->irq.ih.faults->hash, key, NULL);
-+	if (!r)
-+		adev->irq.ih.faults->count++;
-+
-+	/* chash_table_copy_in should never fail unless we're losing count */
-+	WARN_ON_ONCE(r < 0);
-+
-+unlock_out:
-+	spin_unlock_irqrestore(&adev->irq.ih.faults->lock, flags);
-+	return r;
-+}
-+
-+/**
-+ * amdgpu_ih_clear_fault - Remove a page fault record
-+ *
-+ * @adev: amdgpu device pointer
-+ * @key: 64-bit encoding of PASID and address
-+ *
-+ * This should be called when a page fault has been handled. Any
-+ * future interrupt with this key will be processed as a new
-+ * page fault.
-+ */
-+void amdgpu_ih_clear_fault(struct amdgpu_device *adev, u64 key)
-+{
-+	unsigned long flags;
-+	int r;
-+
-+	if (!adev->irq.ih.faults)
-+		return;
-+
-+	spin_lock_irqsave(&adev->irq.ih.faults->lock, flags);
-+
-+	r = chash_table_remove(&adev->irq.ih.faults->hash, key, NULL);
-+	if (!WARN_ON_ONCE(r < 0)) {
-+		adev->irq.ih.faults->count--;
-+		WARN_ON_ONCE(adev->irq.ih.faults->count < 0);
-+	}
-+
-+	spin_unlock_irqrestore(&adev->irq.ih.faults->lock, flags);
-+}
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h	2017-12-14 06:39:58.379903542 +0100
-@@ -24,6 +24,8 @@
- #ifndef __AMDGPU_IH_H__
- #define __AMDGPU_IH_H__
- 
-+#include <linux/chash.h>
-+
- struct amdgpu_device;
-  /*
-   * vega10+ IH clients
-@@ -69,6 +71,13 @@ enum amdgpu_ih_clientid
- 
- #define AMDGPU_IH_CLIENTID_LEGACY 0
- 
-+#define AMDGPU_PAGEFAULT_HASH_BITS 8
-+struct amdgpu_retryfault_hashtable {
-+	DECLARE_CHASH_TABLE(hash, AMDGPU_PAGEFAULT_HASH_BITS, 8, 0);
-+	spinlock_t	lock;
-+	int		count;
-+};
-+
- /*
-  * R6xx+ IH ring
-  */
-@@ -87,6 +96,7 @@ struct amdgpu_ih_ring {
- 	bool			use_doorbell;
- 	bool			use_bus_addr;
- 	dma_addr_t		rb_dma_addr; /* only used when use_bus_addr = true */
-+	struct amdgpu_retryfault_hashtable *faults;
- };
- 
- #define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4
-@@ -109,5 +119,7 @@ int amdgpu_ih_ring_init(struct amdgpu_de
- 			bool use_bus_addr);
- void amdgpu_ih_ring_fini(struct amdgpu_device *adev);
- int amdgpu_ih_process(struct amdgpu_device *adev);
-+int amdgpu_ih_add_fault(struct amdgpu_device *adev, u64 key);
-+void amdgpu_ih_clear_fault(struct amdgpu_device *adev, u64 key);
- 
- #endif
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c	2017-12-14 06:39:58.379903542 +0100
-@@ -37,6 +37,10 @@
- 
- #include <linux/pm_runtime.h>
- 
-+#ifdef CONFIG_DRM_AMD_DC
-+#include "amdgpu_dm_irq.h"
-+#endif
-+
- #define AMDGPU_WAIT_IDLE_TIMEOUT 200
- 
- /*
-@@ -84,7 +88,7 @@ static void amdgpu_irq_reset_work_func(s
- 						  reset_work);
- 
- 	if (!amdgpu_sriov_vf(adev))
--		amdgpu_gpu_reset(adev);
-+		amdgpu_gpu_recover(adev, NULL);
- }
- 
- /* Disable *all* interrupts */
-@@ -221,15 +225,6 @@ int amdgpu_irq_init(struct amdgpu_device
- 
- 	spin_lock_init(&adev->irq.lock);
- 
--	if (!adev->enable_virtual_display)
--		/* Disable vblank irqs aggressively for power-saving */
--		adev->ddev->vblank_disable_immediate = true;
--
--	r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
--	if (r) {
--		return r;
--	}
--
- 	/* enable msi */
- 	adev->irq.msi_enabled = false;
- 
-@@ -237,11 +232,25 @@ int amdgpu_irq_init(struct amdgpu_device
- 		int ret = pci_enable_msi(adev->pdev);
- 		if (!ret) {
- 			adev->irq.msi_enabled = true;
--			dev_info(adev->dev, "amdgpu: using MSI.\n");
-+			dev_dbg(adev->dev, "amdgpu: using MSI.\n");
- 		}
- 	}
- 
--	INIT_WORK(&adev->hotplug_work, amdgpu_hotplug_work_func);
-+	if (!amdgpu_device_has_dc_support(adev)) {
-+		if (!adev->enable_virtual_display)
-+			/* Disable vblank irqs aggressively for power-saving */
-+			/* XXX: can this be enabled for DC? */
-+			adev->ddev->vblank_disable_immediate = true;
-+
-+		r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
-+		if (r)
-+			return r;
-+
-+		/* pre DCE11 */
-+		INIT_WORK(&adev->hotplug_work,
-+				amdgpu_hotplug_work_func);
-+	}
-+
- 	INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
- 
- 	adev->irq.installed = true;
-@@ -253,7 +262,7 @@ int amdgpu_irq_init(struct amdgpu_device
- 		return r;
- 	}
- 
--	DRM_INFO("amdgpu: irq initialized.\n");
-+	DRM_DEBUG("amdgpu: irq initialized.\n");
- 	return 0;
- }
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c	2017-12-14 06:39:58.379903542 +0100
-@@ -37,10 +37,7 @@ static void amdgpu_job_timedout(struct a
- 		  atomic_read(&job->ring->fence_drv.last_seq),
- 		  job->ring->fence_drv.sync_seq);
- 
--	if (amdgpu_sriov_vf(job->adev))
--		amdgpu_sriov_gpu_reset(job->adev, job);
--	else
--		amdgpu_gpu_reset(job->adev);
-+	amdgpu_gpu_recover(job->adev, job);
- }
- 
- int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
-@@ -65,6 +62,7 @@ int amdgpu_job_alloc(struct amdgpu_devic
- 	amdgpu_sync_create(&(*job)->sync);
- 	amdgpu_sync_create(&(*job)->dep_sync);
- 	amdgpu_sync_create(&(*job)->sched_sync);
-+	(*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
- 
- 	return 0;
- }
-@@ -103,6 +101,7 @@ static void amdgpu_job_free_cb(struct am
- {
- 	struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base);
- 
-+	amdgpu_ring_priority_put(job->ring, s_job->s_priority);
- 	dma_fence_put(job->fence);
- 	amdgpu_sync_free(&job->sync);
- 	amdgpu_sync_free(&job->dep_sync);
-@@ -139,12 +138,14 @@ int amdgpu_job_submit(struct amdgpu_job
- 	job->fence_ctx = entity->fence_context;
- 	*f = dma_fence_get(&job->base.s_fence->finished);
- 	amdgpu_job_free_resources(job);
--	amd_sched_entity_push_job(&job->base);
-+	amdgpu_ring_priority_get(job->ring, job->base.s_priority);
-+	amd_sched_entity_push_job(&job->base, entity);
- 
- 	return 0;
- }
- 
--static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job)
-+static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job,
-+					       struct amd_sched_entity *s_entity)
- {
- 	struct amdgpu_job *job = to_amdgpu_job(sched_job);
- 	struct amdgpu_vm *vm = job->vm;
-@@ -152,7 +153,7 @@ static struct dma_fence *amdgpu_job_depe
- 	struct dma_fence *fence = amdgpu_sync_get_fence(&job->dep_sync);
- 	int r;
- 
--	if (amd_sched_dependency_optimized(fence, sched_job->s_entity)) {
-+	if (amd_sched_dependency_optimized(fence, s_entity)) {
- 		r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence);
- 		if (r)
- 			DRM_ERROR("Error adding fence to sync (%d)\n", r);
-@@ -176,9 +177,9 @@ static struct dma_fence *amdgpu_job_depe
- 
- static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job)
- {
--	struct dma_fence *fence = NULL;
-+	struct dma_fence *fence = NULL, *finished;
-+	struct amdgpu_device *adev;
- 	struct amdgpu_job *job;
--	struct amdgpu_fpriv *fpriv = NULL;
- 	int r;
- 
- 	if (!sched_job) {
-@@ -186,23 +187,28 @@ static struct dma_fence *amdgpu_job_run(
- 		return NULL;
- 	}
- 	job = to_amdgpu_job(sched_job);
-+	finished = &job->base.s_fence->finished;
-+	adev = job->adev;
- 
- 	BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
- 
- 	trace_amdgpu_sched_run_job(job);
--	if (job->vm)
--		fpriv = container_of(job->vm, struct amdgpu_fpriv, vm);
--	/* skip ib schedule when vram is lost */
--	if (fpriv && amdgpu_kms_vram_lost(job->adev, fpriv))
--		DRM_ERROR("Skip scheduling IBs!\n");
--	else {
--		r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job, &fence);
-+
-+	if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter))
-+		dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */
-+
-+	if (finished->error < 0) {
-+		DRM_INFO("Skip scheduling IBs!\n");
-+	} else {
-+		r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job,
-+				       &fence);
- 		if (r)
- 			DRM_ERROR("Error scheduling IBs (%d)\n", r);
- 	}
- 	/* if gpu reset, hw fence will be replaced here */
- 	dma_fence_put(job->fence);
- 	job->fence = dma_fence_get(fence);
-+
- 	amdgpu_job_free_resources(job);
- 	return fence;
- }
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c	2017-12-14 06:39:58.379903542 +0100
-@@ -28,6 +28,7 @@
- #include <drm/drmP.h>
- #include "amdgpu.h"
- #include <drm/amdgpu_drm.h>
-+#include "amdgpu_sched.h"
- #include "amdgpu_uvd.h"
- #include "amdgpu_vce.h"
- 
-@@ -62,8 +63,6 @@ void amdgpu_driver_unload_kms(struct drm
- 		pm_runtime_forbid(dev->dev);
- 	}
- 
--	amdgpu_amdkfd_device_fini(adev);
--
- 	amdgpu_acpi_fini(adev);
- 
- 	amdgpu_device_fini(adev);
-@@ -158,9 +157,6 @@ int amdgpu_driver_load_kms(struct drm_de
- 				"Error during ACPI methods call\n");
- 	}
- 
--	amdgpu_amdkfd_device_probe(adev);
--	amdgpu_amdkfd_device_init(adev);
--
- 	if (amdgpu_device_is_px(dev)) {
- 		pm_runtime_use_autosuspend(dev->dev);
- 		pm_runtime_set_autosuspend_delay(dev->dev, 5000);
-@@ -170,9 +166,6 @@ int amdgpu_driver_load_kms(struct drm_de
- 		pm_runtime_put_autosuspend(dev->dev);
- 	}
- 
--	if (amdgpu_sriov_vf(adev))
--		amdgpu_virt_release_full_gpu(adev, true);
--
- out:
- 	if (r) {
- 		/* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
-@@ -269,7 +262,6 @@ static int amdgpu_firmware_info(struct d
- static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
- {
- 	struct amdgpu_device *adev = dev->dev_private;
--	struct amdgpu_fpriv *fpriv = filp->driver_priv;
- 	struct drm_amdgpu_info *info = data;
- 	struct amdgpu_mode_info *minfo = &adev->mode_info;
- 	void __user *out = (void __user *)(uintptr_t)info->return_pointer;
-@@ -282,8 +274,6 @@ static int amdgpu_info_ioctl(struct drm_
- 
- 	if (!info->return_size || !info->return_pointer)
- 		return -EINVAL;
--	if (amdgpu_kms_vram_lost(adev, fpriv))
--		return -ENODEV;
- 
- 	switch (info->query) {
- 	case AMDGPU_INFO_ACCEL_WORKING:
-@@ -765,6 +755,9 @@ static int amdgpu_info_ioctl(struct drm_
- 		}
- 		return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
- 	}
-+	case AMDGPU_INFO_VRAM_LOST_COUNTER:
-+		ui32 = atomic_read(&adev->vram_lost_counter);
-+		return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
- 	default:
- 		DRM_DEBUG_KMS("Invalid request %d\n", info->query);
- 		return -EINVAL;
-@@ -791,12 +784,6 @@ void amdgpu_driver_lastclose_kms(struct
- 	vga_switcheroo_process_delayed_switch();
- }
- 
--bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
--			  struct amdgpu_fpriv *fpriv)
--{
--	return fpriv->vram_lost_counter != atomic_read(&adev->vram_lost_counter);
--}
--
- /**
-  * amdgpu_driver_open_kms - drm callback for open
-  *
-@@ -825,7 +812,7 @@ int amdgpu_driver_open_kms(struct drm_de
- 	}
- 
- 	r = amdgpu_vm_init(adev, &fpriv->vm,
--			   AMDGPU_VM_CONTEXT_GFX);
-+			   AMDGPU_VM_CONTEXT_GFX, 0);
- 	if (r) {
- 		kfree(fpriv);
- 		goto out_suspend;
-@@ -841,8 +828,11 @@ int amdgpu_driver_open_kms(struct drm_de
- 
- 	if (amdgpu_sriov_vf(adev)) {
- 		r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
--		if (r)
-+		if (r) {
-+			amdgpu_vm_fini(adev, &fpriv->vm);
-+			kfree(fpriv);
- 			goto out_suspend;
-+		}
- 	}
- 
- 	mutex_init(&fpriv->bo_list_lock);
-@@ -850,7 +840,6 @@ int amdgpu_driver_open_kms(struct drm_de
- 
- 	amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
- 
--	fpriv->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
- 	file_priv->driver_priv = fpriv;
- 
- out_suspend:
-@@ -1020,7 +1009,9 @@ const struct drm_ioctl_desc amdgpu_ioctl
- 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
- 	DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
- 	DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
-+	DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
- 	DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
-+	DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
- 	/* KMS */
- 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
- 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
-@@ -1032,6 +1023,7 @@ const struct drm_ioctl_desc amdgpu_ioctl
- 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
- 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
- 	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
-+	DRM_IOCTL_DEF_DRV(AMDGPU_FREESYNC, amdgpu_freesync_ioctl, DRM_MASTER)
- };
- const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c	2017-12-14 06:39:58.380903543 +0100
-@@ -50,8 +50,10 @@ struct amdgpu_mn {
- 	struct hlist_node	node;
- 
- 	/* objects protected by lock */
--	struct mutex		lock;
-+	struct rw_semaphore	lock;
- 	struct rb_root_cached	objects;
-+	struct mutex		read_lock;
-+	atomic_t		recursion;
- };
- 
- struct amdgpu_mn_node {
-@@ -74,7 +76,7 @@ static void amdgpu_mn_destroy(struct wor
- 	struct amdgpu_bo *bo, *next_bo;
- 
- 	mutex_lock(&adev->mn_lock);
--	mutex_lock(&rmn->lock);
-+	down_write(&rmn->lock);
- 	hash_del(&rmn->node);
- 	rbtree_postorder_for_each_entry_safe(node, next_node,
- 					     &rmn->objects.rb_root, it.rb) {
-@@ -84,7 +86,7 @@ static void amdgpu_mn_destroy(struct wor
- 		}
- 		kfree(node);
- 	}
--	mutex_unlock(&rmn->lock);
-+	up_write(&rmn->lock);
- 	mutex_unlock(&adev->mn_lock);
- 	mmu_notifier_unregister_no_release(&rmn->mn, rmn->mm);
- 	kfree(rmn);
-@@ -106,6 +108,53 @@ static void amdgpu_mn_release(struct mmu
- 	schedule_work(&rmn->work);
- }
- 
-+
-+/**
-+ * amdgpu_mn_lock - take the write side lock for this mn
-+ */
-+void amdgpu_mn_lock(struct amdgpu_mn *mn)
-+{
-+	if (mn)
-+		down_write(&mn->lock);
-+}
-+
-+/**
-+ * amdgpu_mn_unlock - drop the write side lock for this mn
-+ */
-+void amdgpu_mn_unlock(struct amdgpu_mn *mn)
-+{
-+	if (mn)
-+		up_write(&mn->lock);
-+}
-+
-+/**
-+ * amdgpu_mn_read_lock - take the rmn read lock
-+ *
-+ * @rmn: our notifier
-+ *
-+ * Take the rmn read side lock.
-+ */
-+static void amdgpu_mn_read_lock(struct amdgpu_mn *rmn)
-+{
-+	mutex_lock(&rmn->read_lock);
-+	if (atomic_inc_return(&rmn->recursion) == 1)
-+		down_read_non_owner(&rmn->lock);
-+	mutex_unlock(&rmn->read_lock);
-+}
-+
-+/**
-+ * amdgpu_mn_read_unlock - drop the rmn read lock
-+ *
-+ * @rmn: our notifier
-+ *
-+ * Drop the rmn read side lock.
-+ */
-+static void amdgpu_mn_read_unlock(struct amdgpu_mn *rmn)
-+{
-+	if (atomic_dec_return(&rmn->recursion) == 0)
-+		up_read_non_owner(&rmn->lock);
-+}
-+
- /**
-  * amdgpu_mn_invalidate_node - unmap all BOs of a node
-  *
-@@ -126,23 +175,12 @@ static void amdgpu_mn_invalidate_node(st
- 		if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end))
- 			continue;
- 
--		r = amdgpu_bo_reserve(bo, true);
--		if (r) {
--			DRM_ERROR("(%ld) failed to reserve user bo\n", r);
--			continue;
--		}
--
- 		r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
- 			true, false, MAX_SCHEDULE_TIMEOUT);
- 		if (r <= 0)
- 			DRM_ERROR("(%ld) failed to wait for user bo\n", r);
- 
--		amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
--		r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
--		if (r)
--			DRM_ERROR("(%ld) failed to validate user bo\n", r);
--
--		amdgpu_bo_unreserve(bo);
-+		amdgpu_ttm_tt_mark_user_pages(bo->tbo.ttm);
- 	}
- }
- 
-@@ -168,7 +206,7 @@ static void amdgpu_mn_invalidate_range_s
- 	/* notification is exclusive, but interval is inclusive */
- 	end -= 1;
- 
--	mutex_lock(&rmn->lock);
-+	amdgpu_mn_read_lock(rmn);
- 
- 	it = interval_tree_iter_first(&rmn->objects, start, end);
- 	while (it) {
-@@ -179,13 +217,32 @@ static void amdgpu_mn_invalidate_range_s
- 
- 		amdgpu_mn_invalidate_node(node, start, end);
- 	}
-+}
- 
--	mutex_unlock(&rmn->lock);
-+/**
-+ * amdgpu_mn_invalidate_range_end - callback to notify about mm change
-+ *
-+ * @mn: our notifier
-+ * @mn: the mm this callback is about
-+ * @start: start of updated range
-+ * @end: end of updated range
-+ *
-+ * Release the lock again to allow new command submissions.
-+ */
-+static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn,
-+					   struct mm_struct *mm,
-+					   unsigned long start,
-+					   unsigned long end)
-+{
-+	struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn);
-+
-+	amdgpu_mn_read_unlock(rmn);
- }
- 
- static const struct mmu_notifier_ops amdgpu_mn_ops = {
- 	.release = amdgpu_mn_release,
- 	.invalidate_range_start = amdgpu_mn_invalidate_range_start,
-+	.invalidate_range_end = amdgpu_mn_invalidate_range_end,
- };
- 
- /**
-@@ -195,7 +252,7 @@ static const struct mmu_notifier_ops amd
-  *
-  * Creates a notifier context for current->mm.
-  */
--static struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
-+struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
- {
- 	struct mm_struct *mm = current->mm;
- 	struct amdgpu_mn *rmn;
-@@ -220,8 +277,10 @@ static struct amdgpu_mn *amdgpu_mn_get(s
- 	rmn->adev = adev;
- 	rmn->mm = mm;
- 	rmn->mn.ops = &amdgpu_mn_ops;
--	mutex_init(&rmn->lock);
-+	init_rwsem(&rmn->lock);
- 	rmn->objects = RB_ROOT_CACHED;
-+	mutex_init(&rmn->read_lock);
-+	atomic_set(&rmn->recursion, 0);
- 
- 	r = __mmu_notifier_register(&rmn->mn, mm);
- 	if (r)
-@@ -267,7 +326,7 @@ int amdgpu_mn_register(struct amdgpu_bo
- 
- 	INIT_LIST_HEAD(&bos);
- 
--	mutex_lock(&rmn->lock);
-+	down_write(&rmn->lock);
- 
- 	while ((it = interval_tree_iter_first(&rmn->objects, addr, end))) {
- 		kfree(node);
-@@ -281,7 +340,7 @@ int amdgpu_mn_register(struct amdgpu_bo
- 	if (!node) {
- 		node = kmalloc(sizeof(struct amdgpu_mn_node), GFP_KERNEL);
- 		if (!node) {
--			mutex_unlock(&rmn->lock);
-+			up_write(&rmn->lock);
- 			return -ENOMEM;
- 		}
- 	}
-@@ -296,7 +355,7 @@ int amdgpu_mn_register(struct amdgpu_bo
- 
- 	interval_tree_insert(&node->it, &rmn->objects);
- 
--	mutex_unlock(&rmn->lock);
-+	up_write(&rmn->lock);
- 
- 	return 0;
- }
-@@ -322,7 +381,7 @@ void amdgpu_mn_unregister(struct amdgpu_
- 		return;
- 	}
- 
--	mutex_lock(&rmn->lock);
-+	down_write(&rmn->lock);
- 
- 	/* save the next list entry for later */
- 	head = bo->mn_list.next;
-@@ -337,6 +396,7 @@ void amdgpu_mn_unregister(struct amdgpu_
- 		kfree(node);
- 	}
- 
--	mutex_unlock(&rmn->lock);
-+	up_write(&rmn->lock);
- 	mutex_unlock(&adev->mn_lock);
- }
-+
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h.0130~	2017-12-14 06:39:58.380903543 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h	2017-12-14 06:39:58.380903543 +0100
-@@ -0,0 +1,52 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: Christian König
-+ */
-+#ifndef __AMDGPU_MN_H__
-+#define __AMDGPU_MN_H__
-+
-+/*
-+ * MMU Notifier
-+ */
-+struct amdgpu_mn;
-+
-+#if defined(CONFIG_MMU_NOTIFIER)
-+void amdgpu_mn_lock(struct amdgpu_mn *mn);
-+void amdgpu_mn_unlock(struct amdgpu_mn *mn);
-+struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev);
-+int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
-+void amdgpu_mn_unregister(struct amdgpu_bo *bo);
-+#else
-+static inline void amdgpu_mn_lock(struct amdgpu_mn *mn) {}
-+static inline void amdgpu_mn_unlock(struct amdgpu_mn *mn) {}
-+static inline struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
-+{
-+	return NULL;
-+}
-+static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
-+{
-+	return -ENODEV;
-+}
-+static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
-+#endif
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h	2017-12-14 06:39:58.380903543 +0100
-@@ -38,11 +38,15 @@
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_fb_helper.h>
- #include <drm/drm_plane_helper.h>
-+#include <drm/drm_fb_helper.h>
- #include <linux/i2c.h>
- #include <linux/i2c-algo-bit.h>
- #include <linux/hrtimer.h>
- #include "amdgpu_irq.h"
- 
-+#include <drm/drm_dp_mst_helper.h>
-+#include "modules/inc/mod_freesync.h"
-+
- struct amdgpu_bo;
- struct amdgpu_device;
- struct amdgpu_encoder;
-@@ -53,9 +57,13 @@ struct amdgpu_hpd;
- #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
- #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
- #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
-+#define to_amdgpu_plane(x)	container_of(x, struct amdgpu_plane, base)
-+
-+#define to_dm_plane_state(x)	container_of(x, struct dm_plane_state, base);
- 
- #define AMDGPU_MAX_HPD_PINS 6
- #define AMDGPU_MAX_CRTCS 6
-+#define AMDGPU_MAX_PLANES 6
- #define AMDGPU_MAX_AFMT_BLOCKS 9
- 
- enum amdgpu_rmx_type {
-@@ -81,7 +89,6 @@ enum amdgpu_hpd_id {
- 	AMDGPU_HPD_4,
- 	AMDGPU_HPD_5,
- 	AMDGPU_HPD_6,
--	AMDGPU_HPD_LAST,
- 	AMDGPU_HPD_NONE = 0xff,
- };
- 
-@@ -98,7 +105,6 @@ enum amdgpu_crtc_irq {
- 	AMDGPU_CRTC_IRQ_VLINE4,
- 	AMDGPU_CRTC_IRQ_VLINE5,
- 	AMDGPU_CRTC_IRQ_VLINE6,
--	AMDGPU_CRTC_IRQ_LAST,
- 	AMDGPU_CRTC_IRQ_NONE = 0xff
- };
- 
-@@ -109,7 +115,6 @@ enum amdgpu_pageflip_irq {
- 	AMDGPU_PAGEFLIP_IRQ_D4,
- 	AMDGPU_PAGEFLIP_IRQ_D5,
- 	AMDGPU_PAGEFLIP_IRQ_D6,
--	AMDGPU_PAGEFLIP_IRQ_LAST,
- 	AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
- };
- 
-@@ -292,6 +297,30 @@ struct amdgpu_display_funcs {
- 			      uint16_t connector_object_id,
- 			      struct amdgpu_hpd *hpd,
- 			      struct amdgpu_router *router);
-+	/* it is used to enter or exit into free sync mode */
-+	int (*notify_freesync)(struct drm_device *dev, void *data,
-+			       struct drm_file *filp);
-+	/* it is used to allow enablement of freesync mode */
-+	int (*set_freesync_property)(struct drm_connector *connector,
-+				     struct drm_property *property,
-+				     uint64_t val);
-+
-+
-+};
-+
-+struct amdgpu_framebuffer {
-+	struct drm_framebuffer base;
-+	struct drm_gem_object *obj;
-+
-+	/* caching for later use */
-+	uint64_t address;
-+};
-+
-+struct amdgpu_fbdev {
-+	struct drm_fb_helper helper;
-+	struct amdgpu_framebuffer rfb;
-+	struct list_head fbdev_list;
-+	struct amdgpu_device *adev;
- };
- 
- struct amdgpu_mode_info {
-@@ -299,6 +328,7 @@ struct amdgpu_mode_info {
- 	struct card_info *atom_card_info;
- 	bool mode_config_initialized;
- 	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
-+	struct amdgpu_plane *planes[AMDGPU_MAX_PLANES];
- 	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
- 	/* DVI-I properties */
- 	struct drm_property *coherent_mode_property;
-@@ -312,6 +342,10 @@ struct amdgpu_mode_info {
- 	struct drm_property *audio_property;
- 	/* FMT dithering */
- 	struct drm_property *dither_property;
-+	/* it is used to allow enablement of freesync mode */
-+	struct drm_property *freesync_property;
-+	/* it is used to know about display capability of freesync mode */
-+	struct drm_property *freesync_capable_property;
- 	/* hardcoded DFP edid from BIOS */
- 	struct edid *bios_hardcoded_edid;
- 	int bios_hardcoded_edid_size;
-@@ -328,6 +362,7 @@ struct amdgpu_mode_info {
- 	int			num_dig; /* number of dig blocks */
- 	int			disp_priority;
- 	const struct amdgpu_display_funcs *funcs;
-+	const enum drm_plane_type *plane_type;
- };
- 
- #define AMDGPU_MAX_BL_LEVEL 0xFF
-@@ -400,6 +435,14 @@ struct amdgpu_crtc {
- 	/* for virtual dce */
- 	struct hrtimer vblank_timer;
- 	enum amdgpu_interrupt_state vsync_timer_enabled;
-+
-+	int otg_inst;
-+	struct drm_pending_vblank_event *event;
-+};
-+
-+struct amdgpu_plane {
-+	struct drm_plane base;
-+	enum drm_plane_type plane_type;
- };
- 
- struct amdgpu_encoder_atom_dig {
-@@ -489,6 +532,19 @@ enum amdgpu_connector_dither {
- 	AMDGPU_FMT_DITHER_ENABLE = 1,
- };
- 
-+struct amdgpu_dm_dp_aux {
-+	struct drm_dp_aux aux;
-+	struct ddc_service *ddc_service;
-+};
-+
-+struct amdgpu_i2c_adapter {
-+	struct i2c_adapter base;
-+
-+	struct ddc_service *ddc_service;
-+};
-+
-+#define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
-+
- struct amdgpu_connector {
- 	struct drm_connector base;
- 	uint32_t connector_id;
-@@ -500,6 +556,14 @@ struct amdgpu_connector {
- 	/* we need to mind the EDID between detect
- 	   and get modes due to analog/digital/tvencoder */
- 	struct edid *edid;
-+	/* number of modes generated from EDID at 'dc_sink' */
-+	int num_modes;
-+	/* The 'old' sink - before an HPD.
-+	 * The 'current' sink is in dc_link->sink. */
-+	struct dc_sink *dc_sink;
-+	struct dc_link *dc_link;
-+	struct dc_sink *dc_em_sink;
-+	const struct dc_stream *stream;
- 	void *con_priv;
- 	bool dac_load_detect;
- 	bool detected_by_load; /* if the connection status was determined by load */
-@@ -510,11 +574,39 @@ struct amdgpu_connector {
- 	enum amdgpu_connector_audio audio;
- 	enum amdgpu_connector_dither dither;
- 	unsigned pixelclock_for_modeset;
-+
-+	struct drm_dp_mst_topology_mgr mst_mgr;
-+	struct amdgpu_dm_dp_aux dm_dp_aux;
-+	struct drm_dp_mst_port *port;
-+	struct amdgpu_connector *mst_port;
-+	struct amdgpu_encoder *mst_encoder;
-+	struct semaphore mst_sem;
-+
-+	/* TODO see if we can merge with ddc_bus or make a dm_connector */
-+	struct amdgpu_i2c_adapter *i2c;
-+
-+	/* Monitor range limits */
-+	int min_vfreq ;
-+	int max_vfreq ;
-+	int pixel_clock_mhz;
-+
-+	/*freesync caps*/
-+	struct mod_freesync_caps caps;
-+
-+	struct mutex hpd_lock;
-+
- };
- 
--struct amdgpu_framebuffer {
--	struct drm_framebuffer base;
--	struct drm_gem_object *obj;
-+/* TODO: start to use this struct and remove same field from base one */
-+struct amdgpu_mst_connector {
-+	struct amdgpu_connector base;
-+
-+	struct drm_dp_mst_topology_mgr mst_mgr;
-+	struct amdgpu_dm_dp_aux dm_dp_aux;
-+	struct drm_dp_mst_port *port;
-+	struct amdgpu_connector *mst_port;
-+	bool is_mst_connector;
-+	struct amdgpu_encoder *mst_encoder;
- };
- 
- #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c	2017-12-14 06:39:58.380903543 +0100
-@@ -40,9 +40,7 @@
- static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
- {
- 	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
--	struct amdgpu_bo *bo;
--
--	bo = container_of(tbo, struct amdgpu_bo, tbo);
-+	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
- 
- 	amdgpu_bo_kunmap(bo);
- 
-@@ -64,11 +62,12 @@ bool amdgpu_ttm_bo_is_amdgpu_bo(struct t
- 	return false;
- }
- 
--static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
--				      struct ttm_placement *placement,
--				      struct ttm_place *places,
--				      u32 domain, u64 flags)
-+void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
- {
-+	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
-+	struct ttm_placement *placement = &abo->placement;
-+	struct ttm_place *places = abo->placements;
-+	u64 flags = abo->flags;
- 	u32 c = 0;
- 
- 	if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
-@@ -151,27 +150,6 @@ static void amdgpu_ttm_placement_init(st
- 	placement->busy_placement = places;
- }
- 
--void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
--{
--	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
--
--	amdgpu_ttm_placement_init(adev, &abo->placement, abo->placements,
--				  domain, abo->flags);
--}
--
--static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
--					struct ttm_placement *placement)
--{
--	BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1));
--
--	memcpy(bo->placements, placement->placement,
--	       placement->num_placement * sizeof(struct ttm_place));
--	bo->placement.num_placement = placement->num_placement;
--	bo->placement.num_busy_placement = placement->num_busy_placement;
--	bo->placement.placement = bo->placements;
--	bo->placement.busy_placement = bo->placements;
--}
--
- /**
-  * amdgpu_bo_create_reserved - create reserved BO for kernel use
-  *
-@@ -303,14 +281,51 @@ void amdgpu_bo_free_kernel(struct amdgpu
- 		*cpu_addr = NULL;
- }
- 
--int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
--				unsigned long size, int byte_align,
--				bool kernel, u32 domain, u64 flags,
--				struct sg_table *sg,
--				struct ttm_placement *placement,
--				struct reservation_object *resv,
--				uint64_t init_value,
--				struct amdgpu_bo **bo_ptr)
-+/* Validate bo size is bit bigger then the request domain */
-+static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
-+					  unsigned long size, u32 domain)
-+{
-+	struct ttm_mem_type_manager *man = NULL;
-+
-+	/*
-+	 * If GTT is part of requested domains the check must succeed to
-+	 * allow fall back to GTT
-+	 */
-+	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
-+		man = &adev->mman.bdev.man[TTM_PL_TT];
-+
-+		if (size < (man->size << PAGE_SHIFT))
-+			return true;
-+		else
-+			goto fail;
-+	}
-+
-+	if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
-+		man = &adev->mman.bdev.man[TTM_PL_VRAM];
-+
-+		if (size < (man->size << PAGE_SHIFT))
-+			return true;
-+		else
-+			goto fail;
-+	}
-+
-+
-+	/* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
-+	return true;
-+
-+fail:
-+	DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
-+		  man->size << PAGE_SHIFT);
-+	return false;
-+}
-+
-+static int amdgpu_bo_do_create(struct amdgpu_device *adev,
-+			       unsigned long size, int byte_align,
-+			       bool kernel, u32 domain, u64 flags,
-+			       struct sg_table *sg,
-+			       struct reservation_object *resv,
-+			       uint64_t init_value,
-+			       struct amdgpu_bo **bo_ptr)
- {
- 	struct amdgpu_bo *bo;
- 	enum ttm_bo_type type;
-@@ -322,6 +337,9 @@ int amdgpu_bo_create_restricted(struct a
- 	page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
- 	size = ALIGN(size, PAGE_SIZE);
- 
-+	if (!amdgpu_bo_validate_size(adev, size, domain))
-+		return -ENOMEM;
-+
- 	if (kernel) {
- 		type = ttm_bo_type_kernel;
- 	} else if (sg) {
-@@ -384,10 +402,11 @@ int amdgpu_bo_create_restricted(struct a
- 		bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
- #endif
- 
--	amdgpu_fill_placement_to_bo(bo, placement);
--	/* Kernel allocation are uninterruptible */
-+	bo->tbo.bdev = &adev->mman.bdev;
-+	amdgpu_ttm_placement_from_domain(bo, domain);
- 
- 	initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
-+	/* Kernel allocation are uninterruptible */
- 	r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
- 				 &bo->placement, page_align, !kernel, NULL,
- 				 acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
-@@ -442,27 +461,17 @@ static int amdgpu_bo_create_shadow(struc
- 				   unsigned long size, int byte_align,
- 				   struct amdgpu_bo *bo)
- {
--	struct ttm_placement placement = {0};
--	struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
- 	int r;
- 
- 	if (bo->shadow)
- 		return 0;
- 
--	memset(&placements, 0, sizeof(placements));
--	amdgpu_ttm_placement_init(adev, &placement, placements,
--				  AMDGPU_GEM_DOMAIN_GTT,
--				  AMDGPU_GEM_CREATE_CPU_GTT_USWC |
--				  AMDGPU_GEM_CREATE_SHADOW);
--
--	r = amdgpu_bo_create_restricted(adev, size, byte_align, true,
--					AMDGPU_GEM_DOMAIN_GTT,
--					AMDGPU_GEM_CREATE_CPU_GTT_USWC |
--					AMDGPU_GEM_CREATE_SHADOW,
--					NULL, &placement,
--					bo->tbo.resv,
--					0,
--					&bo->shadow);
-+	r = amdgpu_bo_do_create(adev, size, byte_align, true,
-+				AMDGPU_GEM_DOMAIN_GTT,
-+				AMDGPU_GEM_CREATE_CPU_GTT_USWC |
-+				AMDGPU_GEM_CREATE_SHADOW,
-+				NULL, bo->tbo.resv, 0,
-+				&bo->shadow);
- 	if (!r) {
- 		bo->shadow->parent = amdgpu_bo_ref(bo);
- 		mutex_lock(&adev->shadow_list_lock);
-@@ -484,18 +493,11 @@ int amdgpu_bo_create(struct amdgpu_devic
- 		     uint64_t init_value,
- 		     struct amdgpu_bo **bo_ptr)
- {
--	struct ttm_placement placement = {0};
--	struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
- 	uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
- 	int r;
- 
--	memset(&placements, 0, sizeof(placements));
--	amdgpu_ttm_placement_init(adev, &placement, placements,
--				  domain, parent_flags);
--
--	r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel, domain,
--					parent_flags, sg, &placement, resv,
--					init_value, bo_ptr);
-+	r = amdgpu_bo_do_create(adev, size, byte_align, kernel, domain,
-+				parent_flags, sg, resv, init_value, bo_ptr);
- 	if (r)
- 		return r;
- 
-@@ -672,7 +674,6 @@ int amdgpu_bo_pin_restricted(struct amdg
- {
- 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
- 	int r, i;
--	unsigned fpfn, lpfn;
- 
- 	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
- 		return -EPERM;
-@@ -687,7 +688,7 @@ int amdgpu_bo_pin_restricted(struct amdg
- 	if (bo->pin_count) {
- 		uint32_t mem_type = bo->tbo.mem.mem_type;
- 
--		if (domain != amdgpu_mem_type_to_domain(mem_type))
-+		if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
- 			return -EINVAL;
- 
- 		bo->pin_count++;
-@@ -704,22 +705,16 @@ int amdgpu_bo_pin_restricted(struct amdg
- 	}
- 
- 	bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
-+	/* force to pin into visible video ram */
-+	if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
-+		bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
- 	amdgpu_ttm_placement_from_domain(bo, domain);
- 	for (i = 0; i < bo->placement.num_placement; i++) {
--		/* force to pin into visible video ram */
--		if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
--		    !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
--		    (!max_offset || max_offset >
--		     adev->mc.visible_vram_size)) {
--			if (WARN_ON_ONCE(min_offset >
--					 adev->mc.visible_vram_size))
--				return -EINVAL;
--			fpfn = min_offset >> PAGE_SHIFT;
--			lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
--		} else {
--			fpfn = min_offset >> PAGE_SHIFT;
--			lpfn = max_offset >> PAGE_SHIFT;
--		}
-+		unsigned fpfn, lpfn;
-+
-+		fpfn = min_offset >> PAGE_SHIFT;
-+		lpfn = max_offset >> PAGE_SHIFT;
-+
- 		if (fpfn > bo->placements[i].fpfn)
- 			bo->placements[i].fpfn = fpfn;
- 		if (!bo->placements[i].lpfn ||
-@@ -734,15 +729,17 @@ int amdgpu_bo_pin_restricted(struct amdg
- 		goto error;
- 	}
- 
-+	r = amdgpu_ttm_alloc_gart(&bo->tbo);
-+	if (unlikely(r)) {
-+		dev_err(adev->dev, "%p bind failed\n", bo);
-+		goto error;
-+	}
-+
- 	bo->pin_count = 1;
--	if (gpu_addr != NULL) {
--		r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
--		if (unlikely(r)) {
--			dev_err(adev->dev, "%p bind failed\n", bo);
--			goto error;
--		}
-+	if (gpu_addr != NULL)
- 		*gpu_addr = amdgpu_bo_gpu_offset(bo);
--	}
-+
-+	domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
- 	if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
- 		adev->vram_pin_size += amdgpu_bo_size(bo);
- 		if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
-@@ -825,8 +822,8 @@ int amdgpu_bo_init(struct amdgpu_device
- 	adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
- 					      adev->mc.aper_size);
- 	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
--		adev->mc.mc_vram_size >> 20,
--		(unsigned long long)adev->mc.aper_size >> 20);
-+		 adev->mc.mc_vram_size >> 20,
-+		 (unsigned long long)adev->mc.aper_size >> 20);
- 	DRM_INFO("RAM width %dbits %s\n",
- 		 adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
- 	return amdgpu_ttm_init(adev);
-@@ -928,8 +925,8 @@ void amdgpu_bo_move_notify(struct ttm_bu
- 	if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
- 		return;
- 
--	abo = container_of(bo, struct amdgpu_bo, tbo);
--	amdgpu_vm_bo_invalidate(adev, abo);
-+	abo = ttm_to_amdgpu_bo(bo);
-+	amdgpu_vm_bo_invalidate(adev, abo, evict);
- 
- 	amdgpu_bo_kunmap(abo);
- 
-@@ -955,7 +952,7 @@ int amdgpu_bo_fault_reserve_notify(struc
- 	if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
- 		return 0;
- 
--	abo = container_of(bo, struct amdgpu_bo, tbo);
-+	abo = ttm_to_amdgpu_bo(bo);
- 
- 	/* Remember that this BO was accessed by the CPU */
- 	abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
-@@ -1026,7 +1023,7 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_b
- {
- 	WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
- 	WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
--		     !amdgpu_ttm_is_bound(bo->tbo.ttm));
-+		     !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
- 	WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
- 		     !bo->pin_count);
- 	WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h	2017-12-14 06:39:58.380903543 +0100
-@@ -35,6 +35,7 @@
- 
- /* bo virtual addresses in a vm */
- struct amdgpu_bo_va_mapping {
-+	struct amdgpu_bo_va		*bo_va;
- 	struct list_head		list;
- 	struct rb_node			rb;
- 	uint64_t			start;
-@@ -49,12 +50,17 @@ struct amdgpu_bo_va {
- 	struct amdgpu_vm_bo_base	base;
- 
- 	/* protected by bo being reserved */
--	struct dma_fence	        *last_pt_update;
- 	unsigned			ref_count;
- 
-+	/* all other members protected by the VM PD being reserved */
-+	struct dma_fence	        *last_pt_update;
-+
- 	/* mappings for this bo_va */
- 	struct list_head		invalids;
- 	struct list_head		valids;
-+
-+	/* If the mappings are cleared or filled */
-+	bool				cleared;
- };
- 
- struct amdgpu_bo {
-@@ -88,6 +94,11 @@ struct amdgpu_bo {
- 	};
- };
- 
-+static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
-+{
-+	return container_of(tbo, struct amdgpu_bo, tbo);
-+}
-+
- /**
-  * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
-  * @mem_type:	ttm memory type
-@@ -176,12 +187,20 @@ static inline u64 amdgpu_bo_mmap_offset(
- static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
- {
- 	switch (bo->tbo.mem.mem_type) {
--	case TTM_PL_TT: return amdgpu_ttm_is_bound(bo->tbo.ttm);
-+	case TTM_PL_TT: return amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem);
- 	case TTM_PL_VRAM: return true;
- 	default: return false;
- 	}
- }
- 
-+/**
-+ * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
-+ */
-+static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
-+{
-+	return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
-+}
-+
- int amdgpu_bo_create(struct amdgpu_device *adev,
- 			    unsigned long size, int byte_align,
- 			    bool kernel, u32 domain, u64 flags,
-@@ -189,14 +208,6 @@ int amdgpu_bo_create(struct amdgpu_devic
- 			    struct reservation_object *resv,
- 			    uint64_t init_value,
- 			    struct amdgpu_bo **bo_ptr);
--int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
--				unsigned long size, int byte_align,
--				bool kernel, u32 domain, u64 flags,
--				struct sg_table *sg,
--				struct ttm_placement *placement,
--			        struct reservation_object *resv,
--				uint64_t init_value,
--				struct amdgpu_bo **bo_ptr);
- int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
- 			      unsigned long size, int align,
- 			      u32 domain, struct amdgpu_bo **bo_ptr,
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c	2017-12-14 06:39:58.380903543 +0100
-@@ -30,7 +30,6 @@
- #include <linux/hwmon.h>
- #include <linux/hwmon-sysfs.h>
- 
--#include "amd_powerplay.h"
- 
- static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
- 
-@@ -64,17 +63,13 @@ static const struct cg_flag_name clocks[
- 
- void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
- {
--	if (adev->pp_enabled)
--		/* TODO */
--		return;
--
- 	if (adev->pm.dpm_enabled) {
- 		mutex_lock(&adev->pm.mutex);
- 		if (power_supply_is_system_supplied() > 0)
- 			adev->pm.dpm.ac_power = true;
- 		else
- 			adev->pm.dpm.ac_power = false;
--		if (adev->pm.funcs->enable_bapm)
-+		if (adev->powerplay.pp_funcs->enable_bapm)
- 			amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
- 		mutex_unlock(&adev->pm.mutex);
- 	}
-@@ -88,9 +83,9 @@ static ssize_t amdgpu_get_dpm_state(stru
- 	struct amdgpu_device *adev = ddev->dev_private;
- 	enum amd_pm_state_type pm;
- 
--	if (adev->pp_enabled) {
-+	if (adev->powerplay.pp_funcs->get_current_power_state)
- 		pm = amdgpu_dpm_get_current_power_state(adev);
--	} else
-+	else
- 		pm = adev->pm.dpm.user_state;
- 
- 	return snprintf(buf, PAGE_SIZE, "%s\n",
-@@ -118,8 +113,8 @@ static ssize_t amdgpu_set_dpm_state(stru
- 		goto fail;
- 	}
- 
--	if (adev->pp_enabled) {
--		amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
-+	if (adev->powerplay.pp_funcs->dispatch_tasks) {
-+		amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL);
- 	} else {
- 		mutex_lock(&adev->pm.mutex);
- 		adev->pm.dpm.user_state = state;
-@@ -140,13 +135,17 @@ static ssize_t amdgpu_get_dpm_forced_per
- {
- 	struct drm_device *ddev = dev_get_drvdata(dev);
- 	struct amdgpu_device *adev = ddev->dev_private;
--	enum amd_dpm_forced_level level;
-+	enum amd_dpm_forced_level level = 0xff;
- 
- 	if  ((adev->flags & AMD_IS_PX) &&
- 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
- 		return snprintf(buf, PAGE_SIZE, "off\n");
- 
--	level = amdgpu_dpm_get_performance_level(adev);
-+	if (adev->powerplay.pp_funcs->get_performance_level)
-+		level = amdgpu_dpm_get_performance_level(adev);
-+	else
-+		level = adev->pm.dpm.forced_level;
-+
- 	return snprintf(buf, PAGE_SIZE, "%s\n",
- 			(level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
- 			(level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
-@@ -167,7 +166,7 @@ static ssize_t amdgpu_set_dpm_forced_per
- 	struct drm_device *ddev = dev_get_drvdata(dev);
- 	struct amdgpu_device *adev = ddev->dev_private;
- 	enum amd_dpm_forced_level level;
--	enum amd_dpm_forced_level current_level;
-+	enum amd_dpm_forced_level current_level = 0xff;
- 	int ret = 0;
- 
- 	/* Can't force performance level when the card is off */
-@@ -175,7 +174,8 @@ static ssize_t amdgpu_set_dpm_forced_per
- 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
- 		return -EINVAL;
- 
--	current_level = amdgpu_dpm_get_performance_level(adev);
-+	if (adev->powerplay.pp_funcs->get_performance_level)
-+		current_level = amdgpu_dpm_get_performance_level(adev);
- 
- 	if (strncmp("low", buf, strlen("low")) == 0) {
- 		level = AMD_DPM_FORCED_LEVEL_LOW;
-@@ -203,9 +203,7 @@ static ssize_t amdgpu_set_dpm_forced_per
- 	if (current_level == level)
- 		return count;
- 
--	if (adev->pp_enabled)
--		amdgpu_dpm_force_performance_level(adev, level);
--	else {
-+	if (adev->powerplay.pp_funcs->force_performance_level) {
- 		mutex_lock(&adev->pm.mutex);
- 		if (adev->pm.dpm.thermal_active) {
- 			count = -EINVAL;
-@@ -233,7 +231,7 @@ static ssize_t amdgpu_get_pp_num_states(
- 	struct pp_states_info data;
- 	int i, buf_len;
- 
--	if (adev->pp_enabled)
-+	if (adev->powerplay.pp_funcs->get_pp_num_states)
- 		amdgpu_dpm_get_pp_num_states(adev, &data);
- 
- 	buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
-@@ -257,8 +255,8 @@ static ssize_t amdgpu_get_pp_cur_state(s
- 	enum amd_pm_state_type pm = 0;
- 	int i = 0;
- 
--	if (adev->pp_enabled) {
--
-+	if (adev->powerplay.pp_funcs->get_current_power_state
-+		 && adev->powerplay.pp_funcs->get_pp_num_states) {
- 		pm = amdgpu_dpm_get_current_power_state(adev);
- 		amdgpu_dpm_get_pp_num_states(adev, &data);
- 
-@@ -280,25 +278,10 @@ static ssize_t amdgpu_get_pp_force_state
- {
- 	struct drm_device *ddev = dev_get_drvdata(dev);
- 	struct amdgpu_device *adev = ddev->dev_private;
--	struct pp_states_info data;
--	enum amd_pm_state_type pm = 0;
--	int i;
- 
--	if (adev->pp_force_state_enabled && adev->pp_enabled) {
--		pm = amdgpu_dpm_get_current_power_state(adev);
--		amdgpu_dpm_get_pp_num_states(adev, &data);
--
--		for (i = 0; i < data.nums; i++) {
--			if (pm == data.states[i])
--				break;
--		}
--
--		if (i == data.nums)
--			i = -EINVAL;
--
--		return snprintf(buf, PAGE_SIZE, "%d\n", i);
--
--	} else
-+	if (adev->pp_force_state_enabled)
-+		return amdgpu_get_pp_cur_state(dev, attr, buf);
-+	else
- 		return snprintf(buf, PAGE_SIZE, "\n");
- }
- 
-@@ -315,7 +298,8 @@ static ssize_t amdgpu_set_pp_force_state
- 
- 	if (strlen(buf) == 1)
- 		adev->pp_force_state_enabled = false;
--	else if (adev->pp_enabled) {
-+	else if (adev->powerplay.pp_funcs->dispatch_tasks &&
-+			adev->powerplay.pp_funcs->get_pp_num_states) {
- 		struct pp_states_info data;
- 
- 		ret = kstrtoul(buf, 0, &idx);
-@@ -330,7 +314,7 @@ static ssize_t amdgpu_set_pp_force_state
- 		if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
- 		    state != POWER_STATE_TYPE_DEFAULT) {
- 			amdgpu_dpm_dispatch_task(adev,
--					AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
-+					AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL);
- 			adev->pp_force_state_enabled = true;
- 		}
- 	}
-@@ -347,7 +331,7 @@ static ssize_t amdgpu_get_pp_table(struc
- 	char *table = NULL;
- 	int size;
- 
--	if (adev->pp_enabled)
-+	if (adev->powerplay.pp_funcs->get_pp_table)
- 		size = amdgpu_dpm_get_pp_table(adev, &table);
- 	else
- 		return 0;
-@@ -368,7 +352,7 @@ static ssize_t amdgpu_set_pp_table(struc
- 	struct drm_device *ddev = dev_get_drvdata(dev);
- 	struct amdgpu_device *adev = ddev->dev_private;
- 
--	if (adev->pp_enabled)
-+	if (adev->powerplay.pp_funcs->set_pp_table)
- 		amdgpu_dpm_set_pp_table(adev, buf, count);
- 
- 	return count;
-@@ -380,14 +364,11 @@ static ssize_t amdgpu_get_pp_dpm_sclk(st
- {
- 	struct drm_device *ddev = dev_get_drvdata(dev);
- 	struct amdgpu_device *adev = ddev->dev_private;
--	ssize_t size = 0;
--
--	if (adev->pp_enabled)
--		size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
--	else if (adev->pm.funcs->print_clock_levels)
--		size = adev->pm.funcs->print_clock_levels(adev, PP_SCLK, buf);
- 
--	return size;
-+	if (adev->powerplay.pp_funcs->print_clock_levels)
-+		return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
-+	else
-+		return snprintf(buf, PAGE_SIZE, "\n");
- }
- 
- static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
-@@ -416,10 +397,9 @@ static ssize_t amdgpu_set_pp_dpm_sclk(st
- 		mask |= 1 << level;
- 	}
- 
--	if (adev->pp_enabled)
-+	if (adev->powerplay.pp_funcs->force_clock_level)
- 		amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
--	else if (adev->pm.funcs->force_clock_level)
--		adev->pm.funcs->force_clock_level(adev, PP_SCLK, mask);
-+
- fail:
- 	return count;
- }
-@@ -430,14 +410,11 @@ static ssize_t amdgpu_get_pp_dpm_mclk(st
- {
- 	struct drm_device *ddev = dev_get_drvdata(dev);
- 	struct amdgpu_device *adev = ddev->dev_private;
--	ssize_t size = 0;
- 
--	if (adev->pp_enabled)
--		size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
--	else if (adev->pm.funcs->print_clock_levels)
--		size = adev->pm.funcs->print_clock_levels(adev, PP_MCLK, buf);
--
--	return size;
-+	if (adev->powerplay.pp_funcs->print_clock_levels)
-+		return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
-+	else
-+		return snprintf(buf, PAGE_SIZE, "\n");
- }
- 
- static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
-@@ -465,11 +442,9 @@ static ssize_t amdgpu_set_pp_dpm_mclk(st
- 		}
- 		mask |= 1 << level;
- 	}
--
--	if (adev->pp_enabled)
-+	if (adev->powerplay.pp_funcs->force_clock_level)
- 		amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
--	else if (adev->pm.funcs->force_clock_level)
--		adev->pm.funcs->force_clock_level(adev, PP_MCLK, mask);
-+
- fail:
- 	return count;
- }
-@@ -480,14 +455,11 @@ static ssize_t amdgpu_get_pp_dpm_pcie(st
- {
- 	struct drm_device *ddev = dev_get_drvdata(dev);
- 	struct amdgpu_device *adev = ddev->dev_private;
--	ssize_t size = 0;
- 
--	if (adev->pp_enabled)
--		size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
--	else if (adev->pm.funcs->print_clock_levels)
--		size = adev->pm.funcs->print_clock_levels(adev, PP_PCIE, buf);
--
--	return size;
-+	if (adev->powerplay.pp_funcs->print_clock_levels)
-+		return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
-+	else
-+		return snprintf(buf, PAGE_SIZE, "\n");
- }
- 
- static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
-@@ -515,11 +487,9 @@ static ssize_t amdgpu_set_pp_dpm_pcie(st
- 		}
- 		mask |= 1 << level;
- 	}
--
--	if (adev->pp_enabled)
-+	if (adev->powerplay.pp_funcs->force_clock_level)
- 		amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
--	else if (adev->pm.funcs->force_clock_level)
--		adev->pm.funcs->force_clock_level(adev, PP_PCIE, mask);
-+
- fail:
- 	return count;
- }
-@@ -532,10 +502,8 @@ static ssize_t amdgpu_get_pp_sclk_od(str
- 	struct amdgpu_device *adev = ddev->dev_private;
- 	uint32_t value = 0;
- 
--	if (adev->pp_enabled)
-+	if (adev->powerplay.pp_funcs->get_sclk_od)
- 		value = amdgpu_dpm_get_sclk_od(adev);
--	else if (adev->pm.funcs->get_sclk_od)
--		value = adev->pm.funcs->get_sclk_od(adev);
- 
- 	return snprintf(buf, PAGE_SIZE, "%d\n", value);
- }
-@@ -556,12 +524,12 @@ static ssize_t amdgpu_set_pp_sclk_od(str
- 		count = -EINVAL;
- 		goto fail;
- 	}
--
--	if (adev->pp_enabled) {
-+	if (adev->powerplay.pp_funcs->set_sclk_od)
- 		amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
--		amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
--	} else if (adev->pm.funcs->set_sclk_od) {
--		adev->pm.funcs->set_sclk_od(adev, (uint32_t)value);
-+
-+	if (adev->powerplay.pp_funcs->dispatch_tasks) {
-+		amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
-+	} else {
- 		adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
- 		amdgpu_pm_compute_clocks(adev);
- 	}
-@@ -578,10 +546,8 @@ static ssize_t amdgpu_get_pp_mclk_od(str
- 	struct amdgpu_device *adev = ddev->dev_private;
- 	uint32_t value = 0;
- 
--	if (adev->pp_enabled)
-+	if (adev->powerplay.pp_funcs->get_mclk_od)
- 		value = amdgpu_dpm_get_mclk_od(adev);
--	else if (adev->pm.funcs->get_mclk_od)
--		value = adev->pm.funcs->get_mclk_od(adev);
- 
- 	return snprintf(buf, PAGE_SIZE, "%d\n", value);
- }
-@@ -602,12 +568,12 @@ static ssize_t amdgpu_set_pp_mclk_od(str
- 		count = -EINVAL;
- 		goto fail;
- 	}
--
--	if (adev->pp_enabled) {
-+	if (adev->powerplay.pp_funcs->set_mclk_od)
- 		amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
--		amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
--	} else if (adev->pm.funcs->set_mclk_od) {
--		adev->pm.funcs->set_mclk_od(adev, (uint32_t)value);
-+
-+	if (adev->powerplay.pp_funcs->dispatch_tasks) {
-+		amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
-+	} else {
- 		adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
- 		amdgpu_pm_compute_clocks(adev);
- 	}
-@@ -621,14 +587,11 @@ static ssize_t amdgpu_get_pp_power_profi
- {
- 	struct drm_device *ddev = dev_get_drvdata(dev);
- 	struct amdgpu_device *adev = ddev->dev_private;
--	int ret = 0;
-+	int ret = 0xff;
- 
--	if (adev->pp_enabled)
-+	if (adev->powerplay.pp_funcs->get_power_profile_state)
- 		ret = amdgpu_dpm_get_power_profile_state(
- 				adev, query);
--	else if (adev->pm.funcs->get_power_profile_state)
--		ret = adev->pm.funcs->get_power_profile_state(
--				adev, query);
- 
- 	if (ret)
- 		return ret;
-@@ -675,15 +638,12 @@ static ssize_t amdgpu_set_pp_power_profi
- 	char *sub_str, buf_cpy[128], *tmp_str;
- 	const char delimiter[3] = {' ', '\n', '\0'};
- 	long int value;
--	int ret = 0;
-+	int ret = 0xff;
- 
- 	if (strncmp("reset", buf, strlen("reset")) == 0) {
--		if (adev->pp_enabled)
-+		if (adev->powerplay.pp_funcs->reset_power_profile_state)
- 			ret = amdgpu_dpm_reset_power_profile_state(
- 					adev, request);
--		else if (adev->pm.funcs->reset_power_profile_state)
--			ret = adev->pm.funcs->reset_power_profile_state(
--					adev, request);
- 		if (ret) {
- 			count = -EINVAL;
- 			goto fail;
-@@ -692,12 +652,10 @@ static ssize_t amdgpu_set_pp_power_profi
- 	}
- 
- 	if (strncmp("set", buf, strlen("set")) == 0) {
--		if (adev->pp_enabled)
-+		if (adev->powerplay.pp_funcs->set_power_profile_state)
- 			ret = amdgpu_dpm_set_power_profile_state(
- 					adev, request);
--		else if (adev->pm.funcs->set_power_profile_state)
--			ret = adev->pm.funcs->set_power_profile_state(
--					adev, request);
-+
- 		if (ret) {
- 			count = -EINVAL;
- 			goto fail;
-@@ -745,13 +703,8 @@ static ssize_t amdgpu_set_pp_power_profi
- 
- 		loop++;
- 	}
--
--	if (adev->pp_enabled)
--		ret = amdgpu_dpm_set_power_profile_state(
--				adev, request);
--	else if (adev->pm.funcs->set_power_profile_state)
--		ret = adev->pm.funcs->set_power_profile_state(
--				adev, request);
-+	if (adev->powerplay.pp_funcs->set_power_profile_state)
-+		ret = amdgpu_dpm_set_power_profile_state(adev, request);
- 
- 	if (ret)
- 		count = -EINVAL;
-@@ -831,7 +784,7 @@ static ssize_t amdgpu_hwmon_show_temp(st
- 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
- 		return -EINVAL;
- 
--	if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
-+	if (!adev->powerplay.pp_funcs->get_temperature)
- 		temp = 0;
- 	else
- 		temp = amdgpu_dpm_get_temperature(adev);
-@@ -862,7 +815,7 @@ static ssize_t amdgpu_hwmon_get_pwm1_ena
- 	struct amdgpu_device *adev = dev_get_drvdata(dev);
- 	u32 pwm_mode = 0;
- 
--	if (!adev->pp_enabled && !adev->pm.funcs->get_fan_control_mode)
-+	if (!adev->powerplay.pp_funcs->get_fan_control_mode)
- 		return -EINVAL;
- 
- 	pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
-@@ -879,7 +832,7 @@ static ssize_t amdgpu_hwmon_set_pwm1_ena
- 	int err;
- 	int value;
- 
--	if (!adev->pp_enabled && !adev->pm.funcs->set_fan_control_mode)
-+	if (!adev->powerplay.pp_funcs->set_fan_control_mode)
- 		return -EINVAL;
- 
- 	err = kstrtoint(buf, 10, &value);
-@@ -919,9 +872,11 @@ static ssize_t amdgpu_hwmon_set_pwm1(str
- 
- 	value = (value * 100) / 255;
- 
--	err = amdgpu_dpm_set_fan_speed_percent(adev, value);
--	if (err)
--		return err;
-+	if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
-+		err = amdgpu_dpm_set_fan_speed_percent(adev, value);
-+		if (err)
-+			return err;
-+	}
- 
- 	return count;
- }
-@@ -932,11 +887,13 @@ static ssize_t amdgpu_hwmon_get_pwm1(str
- {
- 	struct amdgpu_device *adev = dev_get_drvdata(dev);
- 	int err;
--	u32 speed;
-+	u32 speed = 0;
- 
--	err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
--	if (err)
--		return err;
-+	if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
-+		err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
-+		if (err)
-+			return err;
-+	}
- 
- 	speed = (speed * 255) / 100;
- 
-@@ -949,11 +906,13 @@ static ssize_t amdgpu_hwmon_get_fan1_inp
- {
- 	struct amdgpu_device *adev = dev_get_drvdata(dev);
- 	int err;
--	u32 speed;
-+	u32 speed = 0;
- 
--	err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
--	if (err)
--		return err;
-+	if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
-+		err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
-+		if (err)
-+			return err;
-+	}
- 
- 	return sprintf(buf, "%i\n", speed);
- }
-@@ -996,9 +955,6 @@ static umode_t hwmon_attributes_visible(
- 	     attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
- 		return 0;
- 
--	if (adev->pp_enabled)
--		return effective_mode;
--
- 	/* Skip fan attributes if fan is not present */
- 	if (adev->pm.no_fan &&
- 	    (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
-@@ -1008,21 +964,21 @@ static umode_t hwmon_attributes_visible(
- 		return 0;
- 
- 	/* mask fan attributes if we have no bindings for this asic to expose */
--	if ((!adev->pm.funcs->get_fan_speed_percent &&
-+	if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
- 	     attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
--	    (!adev->pm.funcs->get_fan_control_mode &&
-+	    (!adev->powerplay.pp_funcs->get_fan_control_mode &&
- 	     attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
- 		effective_mode &= ~S_IRUGO;
- 
--	if ((!adev->pm.funcs->set_fan_speed_percent &&
-+	if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
- 	     attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
--	    (!adev->pm.funcs->set_fan_control_mode &&
-+	    (!adev->powerplay.pp_funcs->set_fan_control_mode &&
- 	     attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
- 		effective_mode &= ~S_IWUSR;
- 
- 	/* hide max/min values if we can't both query and manage the fan */
--	if ((!adev->pm.funcs->set_fan_speed_percent &&
--	     !adev->pm.funcs->get_fan_speed_percent) &&
-+	if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
-+	     !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
- 	    (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
- 	     attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
- 		return 0;
-@@ -1055,7 +1011,7 @@ void amdgpu_dpm_thermal_work_handler(str
- 	if (!adev->pm.dpm_enabled)
- 		return;
- 
--	if (adev->pm.funcs->get_temperature) {
-+	if (adev->powerplay.pp_funcs->get_temperature) {
- 		int temp = amdgpu_dpm_get_temperature(adev);
- 
- 		if (temp < adev->pm.dpm.thermal.min_temp)
-@@ -1087,7 +1043,7 @@ static struct amdgpu_ps *amdgpu_dpm_pick
- 		true : false;
- 
- 	/* check if the vblank period is too short to adjust the mclk */
--	if (single_display && adev->pm.funcs->vblank_too_short) {
-+	if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
- 		if (amdgpu_dpm_vblank_too_short(adev))
- 			single_display = false;
- 	}
-@@ -1216,7 +1172,7 @@ static void amdgpu_dpm_change_power_stat
- 	struct amdgpu_ps *ps;
- 	enum amd_pm_state_type dpm_state;
- 	int ret;
--	bool equal;
-+	bool equal = false;
- 
- 	/* if dpm init failed */
- 	if (!adev->pm.dpm_enabled)
-@@ -1236,7 +1192,7 @@ static void amdgpu_dpm_change_power_stat
- 	else
- 		return;
- 
--	if (amdgpu_dpm == 1) {
-+	if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
- 		printk("switching from power state:\n");
- 		amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
- 		printk("switching to power state:\n");
-@@ -1245,15 +1201,17 @@ static void amdgpu_dpm_change_power_stat
- 
- 	/* update whether vce is active */
- 	ps->vce_active = adev->pm.dpm.vce_active;
--
--	amdgpu_dpm_display_configuration_changed(adev);
-+	if (adev->powerplay.pp_funcs->display_configuration_changed)
-+		amdgpu_dpm_display_configuration_changed(adev);
- 
- 	ret = amdgpu_dpm_pre_set_power_state(adev);
- 	if (ret)
- 		return;
- 
--	if ((0 != amgdpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal)))
--		equal = false;
-+	if (adev->powerplay.pp_funcs->check_state_equal) {
-+		if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
-+			equal = false;
-+	}
- 
- 	if (equal)
- 		return;
-@@ -1264,7 +1222,7 @@ static void amdgpu_dpm_change_power_stat
- 	adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
- 	adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
- 
--	if (adev->pm.funcs->force_performance_level) {
-+	if (adev->powerplay.pp_funcs->force_performance_level) {
- 		if (adev->pm.dpm.thermal_active) {
- 			enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
- 			/* force low perf level for thermal */
-@@ -1280,7 +1238,7 @@ static void amdgpu_dpm_change_power_stat
- 
- void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
- {
--	if (adev->pp_enabled || adev->pm.funcs->powergate_uvd) {
-+	if (adev->powerplay.pp_funcs->powergate_uvd) {
- 		/* enable/disable UVD */
- 		mutex_lock(&adev->pm.mutex);
- 		amdgpu_dpm_powergate_uvd(adev, !enable);
-@@ -1302,7 +1260,7 @@ void amdgpu_dpm_enable_uvd(struct amdgpu
- 
- void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
- {
--	if (adev->pp_enabled || adev->pm.funcs->powergate_vce) {
-+	if (adev->powerplay.pp_funcs->powergate_vce) {
- 		/* enable/disable VCE */
- 		mutex_lock(&adev->pm.mutex);
- 		amdgpu_dpm_powergate_vce(adev, !enable);
-@@ -1337,8 +1295,7 @@ void amdgpu_pm_print_power_states(struct
- {
- 	int i;
- 
--	if (adev->pp_enabled)
--		/* TO DO */
-+	if (adev->powerplay.pp_funcs->print_power_state == NULL)
- 		return;
- 
- 	for (i = 0; i < adev->pm.dpm.num_ps; i++)
-@@ -1353,10 +1310,11 @@ int amdgpu_pm_sysfs_init(struct amdgpu_d
- 	if (adev->pm.sysfs_initialized)
- 		return 0;
- 
--	if (!adev->pp_enabled) {
--		if (adev->pm.funcs->get_temperature == NULL)
--			return 0;
--	}
-+	if (adev->pm.dpm_enabled == 0)
-+		return 0;
-+
-+	if (adev->powerplay.pp_funcs->get_temperature == NULL)
-+		return 0;
- 
- 	adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
- 								   DRIVER_NAME, adev,
-@@ -1379,27 +1337,26 @@ int amdgpu_pm_sysfs_init(struct amdgpu_d
- 		return ret;
- 	}
- 
--	if (adev->pp_enabled) {
--		ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
--		if (ret) {
--			DRM_ERROR("failed to create device file pp_num_states\n");
--			return ret;
--		}
--		ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
--		if (ret) {
--			DRM_ERROR("failed to create device file pp_cur_state\n");
--			return ret;
--		}
--		ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
--		if (ret) {
--			DRM_ERROR("failed to create device file pp_force_state\n");
--			return ret;
--		}
--		ret = device_create_file(adev->dev, &dev_attr_pp_table);
--		if (ret) {
--			DRM_ERROR("failed to create device file pp_table\n");
--			return ret;
--		}
-+
-+	ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
-+	if (ret) {
-+		DRM_ERROR("failed to create device file pp_num_states\n");
-+		return ret;
-+	}
-+	ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
-+	if (ret) {
-+		DRM_ERROR("failed to create device file pp_cur_state\n");
-+		return ret;
-+	}
-+	ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
-+	if (ret) {
-+		DRM_ERROR("failed to create device file pp_force_state\n");
-+		return ret;
-+	}
-+	ret = device_create_file(adev->dev, &dev_attr_pp_table);
-+	if (ret) {
-+		DRM_ERROR("failed to create device file pp_table\n");
-+		return ret;
- 	}
- 
- 	ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
-@@ -1455,16 +1412,19 @@ int amdgpu_pm_sysfs_init(struct amdgpu_d
- 
- void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
- {
-+	if (adev->pm.dpm_enabled == 0)
-+		return;
-+
- 	if (adev->pm.int_hwmon_dev)
- 		hwmon_device_unregister(adev->pm.int_hwmon_dev);
- 	device_remove_file(adev->dev, &dev_attr_power_dpm_state);
- 	device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
--	if (adev->pp_enabled) {
--		device_remove_file(adev->dev, &dev_attr_pp_num_states);
--		device_remove_file(adev->dev, &dev_attr_pp_cur_state);
--		device_remove_file(adev->dev, &dev_attr_pp_force_state);
--		device_remove_file(adev->dev, &dev_attr_pp_table);
--	}
-+
-+	device_remove_file(adev->dev, &dev_attr_pp_num_states);
-+	device_remove_file(adev->dev, &dev_attr_pp_cur_state);
-+	device_remove_file(adev->dev, &dev_attr_pp_force_state);
-+	device_remove_file(adev->dev, &dev_attr_pp_table);
-+
- 	device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
- 	device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
- 	device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
-@@ -1495,8 +1455,8 @@ void amdgpu_pm_compute_clocks(struct amd
- 			amdgpu_fence_wait_empty(ring);
- 	}
- 
--	if (adev->pp_enabled) {
--		amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL);
-+	if (adev->powerplay.pp_funcs->dispatch_tasks) {
-+		amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL, NULL);
- 	} else {
- 		mutex_lock(&adev->pm.mutex);
- 		adev->pm.dpm.new_active_crtcs = 0;
-@@ -1505,7 +1465,7 @@ void amdgpu_pm_compute_clocks(struct amd
- 			list_for_each_entry(crtc,
- 					    &ddev->mode_config.crtc_list, head) {
- 				amdgpu_crtc = to_amdgpu_crtc(crtc);
--				if (crtc->enabled) {
-+				if (amdgpu_crtc->enabled) {
- 					adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
- 					adev->pm.dpm.new_active_crtc_count++;
- 				}
-@@ -1630,15 +1590,15 @@ static int amdgpu_debugfs_pm_info(struct
- 	if  ((adev->flags & AMD_IS_PX) &&
- 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
- 		seq_printf(m, "PX asic powered off\n");
--	} else if (adev->pp_enabled) {
--		return amdgpu_debugfs_pm_info_pp(m, adev);
--	} else {
-+	} else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
- 		mutex_lock(&adev->pm.mutex);
--		if (adev->pm.funcs->debugfs_print_current_performance_level)
--			adev->pm.funcs->debugfs_print_current_performance_level(adev, m);
-+		if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
-+			adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
- 		else
- 			seq_printf(m, "Debugfs support not implemented for this asic\n");
- 		mutex_unlock(&adev->pm.mutex);
-+	} else {
-+		return amdgpu_debugfs_pm_info_pp(m, adev);
- 	}
- 
- 	return 0;
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c	2017-12-14 06:39:58.381903544 +0100
-@@ -34,24 +34,6 @@
- #include "cik_dpm.h"
- #include "vi_dpm.h"
- 
--static int amdgpu_create_pp_handle(struct amdgpu_device *adev)
--{
--	struct amd_pp_init pp_init;
--	struct amd_powerplay *amd_pp;
--	int ret;
--
--	amd_pp = &(adev->powerplay);
--	pp_init.chip_family = adev->family;
--	pp_init.chip_id = adev->asic_type;
--	pp_init.pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
--	pp_init.feature_mask = amdgpu_pp_feature_mask;
--	pp_init.device = amdgpu_cgs_create_device(adev);
--	ret = amd_powerplay_create(&pp_init, &(amd_pp->pp_handle));
--	if (ret)
--		return -EINVAL;
--	return 0;
--}
--
- static int amdgpu_pp_early_init(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-@@ -59,7 +41,6 @@ static int amdgpu_pp_early_init(void *ha
- 	int ret = 0;
- 
- 	amd_pp = &(adev->powerplay);
--	adev->pp_enabled = false;
- 	amd_pp->pp_handle = (void *)adev;
- 
- 	switch (adev->asic_type) {
-@@ -73,9 +54,7 @@ static int amdgpu_pp_early_init(void *ha
- 	case CHIP_STONEY:
- 	case CHIP_VEGA10:
- 	case CHIP_RAVEN:
--		adev->pp_enabled = true;
--		if (amdgpu_create_pp_handle(adev))
--			return -EINVAL;
-+		amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
- 		amd_pp->ip_funcs = &pp_ip_funcs;
- 		amd_pp->pp_funcs = &pp_dpm_funcs;
- 		break;
-@@ -87,17 +66,26 @@ static int amdgpu_pp_early_init(void *ha
- 	case CHIP_OLAND:
- 	case CHIP_HAINAN:
- 		amd_pp->ip_funcs = &si_dpm_ip_funcs;
-+		amd_pp->pp_funcs = &si_dpm_funcs;
- 	break;
- #endif
- #ifdef CONFIG_DRM_AMDGPU_CIK
- 	case CHIP_BONAIRE:
- 	case CHIP_HAWAII:
--		amd_pp->ip_funcs = &ci_dpm_ip_funcs;
-+		if (amdgpu_dpm == -1) {
-+			amd_pp->ip_funcs = &ci_dpm_ip_funcs;
-+			amd_pp->pp_funcs = &ci_dpm_funcs;
-+		} else {
-+			amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
-+			amd_pp->ip_funcs = &pp_ip_funcs;
-+			amd_pp->pp_funcs = &pp_dpm_funcs;
-+		}
- 		break;
- 	case CHIP_KABINI:
- 	case CHIP_MULLINS:
- 	case CHIP_KAVERI:
- 		amd_pp->ip_funcs = &kv_dpm_ip_funcs;
-+		amd_pp->pp_funcs = &kv_dpm_funcs;
- 		break;
- #endif
- 	default:
-@@ -107,12 +95,9 @@ static int amdgpu_pp_early_init(void *ha
- 
- 	if (adev->powerplay.ip_funcs->early_init)
- 		ret = adev->powerplay.ip_funcs->early_init(
--					adev->powerplay.pp_handle);
-+					amd_pp->cgs_device ? amd_pp->cgs_device :
-+					amd_pp->pp_handle);
- 
--	if (ret == PP_DPM_DISABLED) {
--		adev->pm.dpm_enabled = false;
--		return 0;
--	}
- 	return ret;
- }
- 
-@@ -126,11 +111,6 @@ static int amdgpu_pp_late_init(void *han
- 		ret = adev->powerplay.ip_funcs->late_init(
- 					adev->powerplay.pp_handle);
- 
--	if (adev->pp_enabled && adev->pm.dpm_enabled) {
--		amdgpu_pm_sysfs_init(adev);
--		amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
--	}
--
- 	return ret;
- }
- 
-@@ -165,21 +145,13 @@ static int amdgpu_pp_hw_init(void *handl
- 	int ret = 0;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
-+	if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
- 		amdgpu_ucode_init_bo(adev);
- 
- 	if (adev->powerplay.ip_funcs->hw_init)
- 		ret = adev->powerplay.ip_funcs->hw_init(
- 					adev->powerplay.pp_handle);
- 
--	if (ret == PP_DPM_DISABLED) {
--		adev->pm.dpm_enabled = false;
--		return 0;
--	}
--
--	if ((amdgpu_dpm != 0) && !amdgpu_sriov_vf(adev))
--		adev->pm.dpm_enabled = true;
--
- 	return ret;
- }
- 
-@@ -188,14 +160,11 @@ static int amdgpu_pp_hw_fini(void *handl
- 	int ret = 0;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	if (adev->pp_enabled && adev->pm.dpm_enabled)
--		amdgpu_pm_sysfs_fini(adev);
--
- 	if (adev->powerplay.ip_funcs->hw_fini)
- 		ret = adev->powerplay.ip_funcs->hw_fini(
- 					adev->powerplay.pp_handle);
- 
--	if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
-+	if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
- 		amdgpu_ucode_fini_bo(adev);
- 
- 	return ret;
-@@ -209,9 +178,8 @@ static void amdgpu_pp_late_fini(void *ha
- 		adev->powerplay.ip_funcs->late_fini(
- 			  adev->powerplay.pp_handle);
- 
--
--	if (adev->pp_enabled)
--		amd_powerplay_destroy(adev->powerplay.pp_handle);
-+	if (adev->powerplay.cgs_device)
-+		amdgpu_cgs_destroy_device(adev->powerplay.cgs_device);
- }
- 
- static int amdgpu_pp_suspend(void *handle)
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c	2017-12-14 06:39:58.381903544 +0100
-@@ -57,6 +57,40 @@ void amdgpu_gem_prime_vunmap(struct drm_
- 	ttm_bo_kunmap(&bo->dma_buf_vmap);
- }
- 
-+int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
-+{
-+	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
-+	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
-+	unsigned asize = amdgpu_bo_size(bo);
-+	int ret;
-+
-+	if (!vma->vm_file)
-+		return -ENODEV;
-+
-+	if (adev == NULL)
-+		return -ENODEV;
-+
-+	/* Check for valid size. */
-+	if (asize < vma->vm_end - vma->vm_start)
-+		return -EINVAL;
-+
-+	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
-+	    (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
-+		return -EPERM;
-+	}
-+	vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT;
-+
-+	/* prime mmap does not need to check access, so allow here */
-+	ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data);
-+	if (ret)
-+		return ret;
-+
-+	ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev);
-+	drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data);
-+
-+	return ret;
-+}
-+
- struct drm_gem_object *
- amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
- 				 struct dma_buf_attachment *attach,
-@@ -135,9 +169,14 @@ struct dma_buf *amdgpu_gem_prime_export(
- 					int flags)
- {
- 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
-+	struct dma_buf *buf;
- 
--	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
-+	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
-+	    bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
- 		return ERR_PTR(-EPERM);
- 
--	return drm_gem_prime_export(dev, gobj, flags);
-+	buf = drm_gem_prime_export(dev, gobj, flags);
-+	if (!IS_ERR(buf))
-+		buf->file->f_mapping = dev->anon_inode->i_mapping;
-+	return buf;
- }
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c	2017-12-14 06:39:58.381903544 +0100
-@@ -57,21 +57,23 @@ static int psp_sw_init(void *handle)
- 		psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
- 		psp->ring_init = psp_v3_1_ring_init;
- 		psp->ring_create = psp_v3_1_ring_create;
-+		psp->ring_stop = psp_v3_1_ring_stop;
- 		psp->ring_destroy = psp_v3_1_ring_destroy;
- 		psp->cmd_submit = psp_v3_1_cmd_submit;
- 		psp->compare_sram_data = psp_v3_1_compare_sram_data;
- 		psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
-+		psp->mode1_reset = psp_v3_1_mode1_reset;
- 		break;
- 	case CHIP_RAVEN:
--#if 0
- 		psp->init_microcode = psp_v10_0_init_microcode;
--#endif
- 		psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
- 		psp->ring_init = psp_v10_0_ring_init;
- 		psp->ring_create = psp_v10_0_ring_create;
-+		psp->ring_stop = psp_v10_0_ring_stop;
- 		psp->ring_destroy = psp_v10_0_ring_destroy;
- 		psp->cmd_submit = psp_v10_0_cmd_submit;
- 		psp->compare_sram_data = psp_v10_0_compare_sram_data;
-+		psp->mode1_reset = psp_v10_0_mode1_reset;
- 		break;
- 	default:
- 		return -EINVAL;
-@@ -90,6 +92,12 @@ static int psp_sw_init(void *handle)
- 
- static int psp_sw_fini(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	release_firmware(adev->psp.sos_fw);
-+	adev->psp.sos_fw = NULL;
-+	release_firmware(adev->psp.asd_fw);
-+	adev->psp.asd_fw = NULL;
- 	return 0;
- }
- 
-@@ -253,15 +261,18 @@ static int psp_asd_load(struct psp_conte
- 
- static int psp_hw_start(struct psp_context *psp)
- {
-+	struct amdgpu_device *adev = psp->adev;
- 	int ret;
- 
--	ret = psp_bootloader_load_sysdrv(psp);
--	if (ret)
--		return ret;
-+	if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
-+		ret = psp_bootloader_load_sysdrv(psp);
-+		if (ret)
-+			return ret;
- 
--	ret = psp_bootloader_load_sos(psp);
--	if (ret)
--		return ret;
-+		ret = psp_bootloader_load_sos(psp);
-+		if (ret)
-+			return ret;
-+	}
- 
- 	ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
- 	if (ret)
-@@ -323,23 +334,26 @@ static int psp_load_fw(struct amdgpu_dev
- 	int ret;
- 	struct psp_context *psp = &adev->psp;
- 
-+	if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset != 0)
-+		goto skip_memalloc;
-+
- 	psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
- 	if (!psp->cmd)
- 		return -ENOMEM;
- 
- 	ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
--				      AMDGPU_GEM_DOMAIN_GTT,
--				      &psp->fw_pri_bo,
--				      &psp->fw_pri_mc_addr,
--				      &psp->fw_pri_buf);
-+					AMDGPU_GEM_DOMAIN_GTT,
-+					&psp->fw_pri_bo,
-+					&psp->fw_pri_mc_addr,
-+					&psp->fw_pri_buf);
- 	if (ret)
- 		goto failed;
- 
- 	ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
--				      AMDGPU_GEM_DOMAIN_VRAM,
--				      &psp->fence_buf_bo,
--				      &psp->fence_buf_mc_addr,
--				      &psp->fence_buf);
-+					AMDGPU_GEM_DOMAIN_VRAM,
-+					&psp->fence_buf_bo,
-+					&psp->fence_buf_mc_addr,
-+					&psp->fence_buf);
- 	if (ret)
- 		goto failed_mem2;
- 
-@@ -364,6 +378,7 @@ static int psp_load_fw(struct amdgpu_dev
- 	if (ret)
- 		goto failed_mem;
- 
-+skip_memalloc:
- 	ret = psp_hw_start(psp);
- 	if (ret)
- 		goto failed_mem;
-@@ -453,6 +468,16 @@ static int psp_hw_fini(void *handle)
- 
- static int psp_suspend(void *handle)
- {
-+	int ret;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	struct psp_context *psp = &adev->psp;
-+
-+	ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
-+	if (ret) {
-+		DRM_ERROR("PSP ring stop failed\n");
-+		return ret;
-+	}
-+
- 	return 0;
- }
- 
-@@ -487,6 +512,22 @@ failed:
- 	return ret;
- }
- 
-+static bool psp_check_reset(void* handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	if (adev->flags & AMD_IS_APU)
-+		return true;
-+
-+	return false;
-+}
-+
-+static int psp_reset(void* handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	return psp_mode1_reset(&adev->psp);
-+}
-+
- static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
- 					enum AMDGPU_UCODE_ID ucode_type)
- {
-@@ -530,8 +571,9 @@ const struct amd_ip_funcs psp_ip_funcs =
- 	.suspend = psp_suspend,
- 	.resume = psp_resume,
- 	.is_idle = NULL,
-+	.check_soft_reset = psp_check_reset,
- 	.wait_for_idle = NULL,
--	.soft_reset = NULL,
-+	.soft_reset = psp_reset,
- 	.set_clockgating_state = psp_set_clockgating_state,
- 	.set_powergating_state = psp_set_powergating_state,
- };
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h	2017-12-14 06:39:58.381903544 +0100
-@@ -66,6 +66,8 @@ struct psp_context
- 			    struct psp_gfx_cmd_resp *cmd);
- 	int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
- 	int (*ring_create)(struct psp_context *psp, enum psp_ring_type ring_type);
-+	int (*ring_stop)(struct psp_context *psp,
-+			    enum psp_ring_type ring_type);
- 	int (*ring_destroy)(struct psp_context *psp,
- 			    enum psp_ring_type ring_type);
- 	int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode,
-@@ -74,6 +76,7 @@ struct psp_context
- 				  struct amdgpu_firmware_info *ucode,
- 				  enum AMDGPU_UCODE_ID ucode_type);
- 	bool (*smu_reload_quirk)(struct psp_context *psp);
-+	int (*mode1_reset)(struct psp_context *psp);
- 
- 	/* fence buffer */
- 	struct amdgpu_bo 		*fw_pri_bo;
-@@ -123,6 +126,7 @@ struct amdgpu_psp_funcs {
- #define psp_prep_cmd_buf(ucode, type) (psp)->prep_cmd_buf((ucode), (type))
- #define psp_ring_init(psp, type) (psp)->ring_init((psp), (type))
- #define psp_ring_create(psp, type) (psp)->ring_create((psp), (type))
-+#define psp_ring_stop(psp, type) (psp)->ring_stop((psp), (type))
- #define psp_ring_destroy(psp, type) ((psp)->ring_destroy((psp), (type)))
- #define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
- 		(psp)->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
-@@ -136,6 +140,8 @@ struct amdgpu_psp_funcs {
- 		((psp)->bootloader_load_sos ? (psp)->bootloader_load_sos((psp)) : 0)
- #define psp_smu_reload_quirk(psp) \
- 		((psp)->smu_reload_quirk ? (psp)->smu_reload_quirk((psp)) : false)
-+#define psp_mode1_reset(psp) \
-+		((psp)->mode1_reset ? (psp)->mode1_reset((psp)) : false)
- 
- extern const struct amd_ip_funcs psp_ip_funcs;
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c	2017-12-14 06:39:58.381903544 +0100
-@@ -121,7 +121,7 @@ static enum amdgpu_ring_type amdgpu_hw_i
- 
- static int amdgpu_lru_map(struct amdgpu_device *adev,
- 			  struct amdgpu_queue_mapper *mapper,
--			  u32 user_ring,
-+			  u32 user_ring, bool lru_pipe_order,
- 			  struct amdgpu_ring **out_ring)
- {
- 	int r, i, j;
-@@ -139,7 +139,7 @@ static int amdgpu_lru_map(struct amdgpu_
- 	}
- 
- 	r = amdgpu_ring_lru_get(adev, ring_type, ring_blacklist,
--				j, out_ring);
-+				j, lru_pipe_order, out_ring);
- 	if (r)
- 		return r;
- 
-@@ -284,8 +284,10 @@ int amdgpu_queue_mgr_map(struct amdgpu_d
- 		r = amdgpu_identity_map(adev, mapper, ring, out_ring);
- 		break;
- 	case AMDGPU_HW_IP_DMA:
-+		r = amdgpu_lru_map(adev, mapper, ring, false, out_ring);
-+		break;
- 	case AMDGPU_HW_IP_COMPUTE:
--		r = amdgpu_lru_map(adev, mapper, ring, out_ring);
-+		r = amdgpu_lru_map(adev, mapper, ring, true, out_ring);
- 		break;
- 	default:
- 		*out_ring = NULL;
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c	2017-12-14 06:39:58.381903544 +0100
-@@ -136,7 +136,8 @@ void amdgpu_ring_commit(struct amdgpu_ri
- 	if (ring->funcs->end_use)
- 		ring->funcs->end_use(ring);
- 
--	amdgpu_ring_lru_touch(ring->adev, ring);
-+	if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ)
-+		amdgpu_ring_lru_touch(ring->adev, ring);
- }
- 
- /**
-@@ -155,6 +156,75 @@ void amdgpu_ring_undo(struct amdgpu_ring
- }
- 
- /**
-+ * amdgpu_ring_priority_put - restore a ring's priority
-+ *
-+ * @ring: amdgpu_ring structure holding the information
-+ * @priority: target priority
-+ *
-+ * Release a request for executing at @priority
-+ */
-+void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
-+			      enum amd_sched_priority priority)
-+{
-+	int i;
-+
-+	if (!ring->funcs->set_priority)
-+		return;
-+
-+	if (atomic_dec_return(&ring->num_jobs[priority]) > 0)
-+		return;
-+
-+	/* no need to restore if the job is already at the lowest priority */
-+	if (priority == AMD_SCHED_PRIORITY_NORMAL)
-+		return;
-+
-+	mutex_lock(&ring->priority_mutex);
-+	/* something higher prio is executing, no need to decay */
-+	if (ring->priority > priority)
-+		goto out_unlock;
-+
-+	/* decay priority to the next level with a job available */
-+	for (i = priority; i >= AMD_SCHED_PRIORITY_MIN; i--) {
-+		if (i == AMD_SCHED_PRIORITY_NORMAL
-+				|| atomic_read(&ring->num_jobs[i])) {
-+			ring->priority = i;
-+			ring->funcs->set_priority(ring, i);
-+			break;
-+		}
-+	}
-+
-+out_unlock:
-+	mutex_unlock(&ring->priority_mutex);
-+}
-+
-+/**
-+ * amdgpu_ring_priority_get - change the ring's priority
-+ *
-+ * @ring: amdgpu_ring structure holding the information
-+ * @priority: target priority
-+ *
-+ * Request a ring's priority to be raised to @priority (refcounted).
-+ */
-+void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
-+			      enum amd_sched_priority priority)
-+{
-+	if (!ring->funcs->set_priority)
-+		return;
-+
-+	atomic_inc(&ring->num_jobs[priority]);
-+
-+	mutex_lock(&ring->priority_mutex);
-+	if (priority <= ring->priority)
-+		goto out_unlock;
-+
-+	ring->priority = priority;
-+	ring->funcs->set_priority(ring, priority);
-+
-+out_unlock:
-+	mutex_unlock(&ring->priority_mutex);
-+}
-+
-+/**
-  * amdgpu_ring_init - init driver ring struct.
-  *
-  * @adev: amdgpu_device pointer
-@@ -169,7 +239,7 @@ int amdgpu_ring_init(struct amdgpu_devic
- 		     unsigned max_dw, struct amdgpu_irq_src *irq_src,
- 		     unsigned irq_type)
- {
--	int r;
-+	int r, i;
- 	int sched_hw_submission = amdgpu_sched_hw_submission;
- 
- 	/* Set the hw submission limit higher for KIQ because
-@@ -247,9 +317,14 @@ int amdgpu_ring_init(struct amdgpu_devic
- 	}
- 
- 	ring->max_dw = max_dw;
-+	ring->priority = AMD_SCHED_PRIORITY_NORMAL;
-+	mutex_init(&ring->priority_mutex);
- 	INIT_LIST_HEAD(&ring->lru_list);
- 	amdgpu_ring_lru_touch(adev, ring);
- 
-+	for (i = 0; i < AMD_SCHED_PRIORITY_MAX; ++i)
-+		atomic_set(&ring->num_jobs[i], 0);
-+
- 	if (amdgpu_debugfs_ring_init(adev, ring)) {
- 		DRM_ERROR("Failed to register debugfs file for rings !\n");
- 	}
-@@ -315,14 +390,16 @@ static bool amdgpu_ring_is_blacklisted(s
-  * @type: amdgpu_ring_type enum
-  * @blacklist: blacklisted ring ids array
-  * @num_blacklist: number of entries in @blacklist
-+ * @lru_pipe_order: find a ring from the least recently used pipe
-  * @ring: output ring
-  *
-  * Retrieve the amdgpu_ring structure for the least recently used ring of
-  * a specific IP block (all asics).
-  * Returns 0 on success, error on failure.
-  */
--int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, int *blacklist,
--			int num_blacklist, struct amdgpu_ring **ring)
-+int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
-+			int *blacklist,	int num_blacklist,
-+			bool lru_pipe_order, struct amdgpu_ring **ring)
- {
- 	struct amdgpu_ring *entry;
- 
-@@ -337,10 +414,23 @@ int amdgpu_ring_lru_get(struct amdgpu_de
- 		if (amdgpu_ring_is_blacklisted(entry, blacklist, num_blacklist))
- 			continue;
- 
--		*ring = entry;
--		amdgpu_ring_lru_touch_locked(adev, *ring);
--		break;
-+		if (!*ring) {
-+			*ring = entry;
-+
-+			/* We are done for ring LRU */
-+			if (!lru_pipe_order)
-+				break;
-+		}
-+
-+		/* Move all rings on the same pipe to the end of the list */
-+		if (entry->pipe == (*ring)->pipe)
-+			amdgpu_ring_lru_touch_locked(adev, entry);
- 	}
-+
-+	/* Move the ring we found to the end of the list */
-+	if (*ring)
-+		amdgpu_ring_lru_touch_locked(adev, *ring);
-+
- 	spin_unlock(&adev->ring_lru_list_lock);
- 
- 	if (!*ring) {
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h	2017-12-14 06:39:58.381903544 +0100
-@@ -24,6 +24,7 @@
- #ifndef __AMDGPU_RING_H__
- #define __AMDGPU_RING_H__
- 
-+#include <drm/amdgpu_drm.h>
- #include "gpu_scheduler.h"
- 
- /* max number of rings */
-@@ -56,6 +57,7 @@ struct amdgpu_device;
- struct amdgpu_ring;
- struct amdgpu_ib;
- struct amdgpu_cs_parser;
-+struct amdgpu_job;
- 
- /*
-  * Fences.
-@@ -77,8 +79,7 @@ struct amdgpu_fence_driver {
- 
- int amdgpu_fence_driver_init(struct amdgpu_device *adev);
- void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
--void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
--void amdgpu_fence_driver_force_completion_ring(struct amdgpu_ring *ring);
-+void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
- 
- int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
- 				  unsigned num_hw_submission);
-@@ -88,8 +89,12 @@ int amdgpu_fence_driver_start_ring(struc
- void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
- void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
- int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence);
-+int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s);
- void amdgpu_fence_process(struct amdgpu_ring *ring);
- int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
-+signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
-+				      uint32_t wait_seq,
-+				      signed long timeout);
- unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
- 
- /*
-@@ -147,6 +152,9 @@ struct amdgpu_ring_funcs {
- 	void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
- 	void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
- 	void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
-+	/* priority functions */
-+	void (*set_priority) (struct amdgpu_ring *ring,
-+			      enum amd_sched_priority priority);
- };
- 
- struct amdgpu_ring {
-@@ -187,6 +195,12 @@ struct amdgpu_ring {
- 	volatile u32		*cond_exe_cpu_addr;
- 	unsigned		vm_inv_eng;
- 	bool			has_compute_vm_bug;
-+
-+	atomic_t		num_jobs[AMD_SCHED_PRIORITY_MAX];
-+	struct mutex		priority_mutex;
-+	/* protected by priority_mutex */
-+	int			priority;
-+
- #if defined(CONFIG_DEBUG_FS)
- 	struct dentry *ent;
- #endif
-@@ -197,12 +211,17 @@ void amdgpu_ring_insert_nop(struct amdgp
- void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
- void amdgpu_ring_commit(struct amdgpu_ring *ring);
- void amdgpu_ring_undo(struct amdgpu_ring *ring);
-+void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
-+			      enum amd_sched_priority priority);
-+void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
-+			      enum amd_sched_priority priority);
- int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
- 		     unsigned ring_size, struct amdgpu_irq_src *irq_src,
- 		     unsigned irq_type);
- void amdgpu_ring_fini(struct amdgpu_ring *ring);
--int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, int *blacklist,
--			int num_blacklist, struct amdgpu_ring **ring);
-+int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
-+			int *blacklist, int num_blacklist,
-+			bool lru_pipe_order, struct amdgpu_ring **ring);
- void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring);
- static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
- {
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c.0130~	2017-12-14 06:39:58.381903544 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c	2017-12-14 06:39:58.381903544 +0100
-@@ -0,0 +1,109 @@
-+/*
-+ * Copyright 2017 Valve Corporation
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: Andres Rodriguez <andresx7@gmail.com>
-+ */
-+
-+#include <linux/fdtable.h>
-+#include <linux/pid.h>
-+#include <drm/amdgpu_drm.h>
-+#include "amdgpu.h"
-+
-+#include "amdgpu_vm.h"
-+
-+enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority)
-+{
-+	switch (amdgpu_priority) {
-+	case AMDGPU_CTX_PRIORITY_VERY_HIGH:
-+		return AMD_SCHED_PRIORITY_HIGH_HW;
-+	case AMDGPU_CTX_PRIORITY_HIGH:
-+		return AMD_SCHED_PRIORITY_HIGH_SW;
-+	case AMDGPU_CTX_PRIORITY_NORMAL:
-+		return AMD_SCHED_PRIORITY_NORMAL;
-+	case AMDGPU_CTX_PRIORITY_LOW:
-+	case AMDGPU_CTX_PRIORITY_VERY_LOW:
-+		return AMD_SCHED_PRIORITY_LOW;
-+	case AMDGPU_CTX_PRIORITY_UNSET:
-+		return AMD_SCHED_PRIORITY_UNSET;
-+	default:
-+		WARN(1, "Invalid context priority %d\n", amdgpu_priority);
-+		return AMD_SCHED_PRIORITY_INVALID;
-+	}
-+}
-+
-+static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,
-+						  int fd,
-+						  enum amd_sched_priority priority)
-+{
-+	struct file *filp = fcheck(fd);
-+	struct drm_file *file;
-+	struct pid *pid;
-+	struct amdgpu_fpriv *fpriv;
-+	struct amdgpu_ctx *ctx;
-+	uint32_t id;
-+
-+	if (!filp)
-+		return -EINVAL;
-+
-+	pid = get_pid(((struct drm_file *)filp->private_data)->pid);
-+
-+	mutex_lock(&adev->ddev->filelist_mutex);
-+	list_for_each_entry(file, &adev->ddev->filelist, lhead) {
-+		if (file->pid != pid)
-+			continue;
-+
-+		fpriv = file->driver_priv;
-+		idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id)
-+				amdgpu_ctx_priority_override(ctx, priority);
-+	}
-+	mutex_unlock(&adev->ddev->filelist_mutex);
-+
-+	put_pid(pid);
-+
-+	return 0;
-+}
-+
-+int amdgpu_sched_ioctl(struct drm_device *dev, void *data,
-+		       struct drm_file *filp)
-+{
-+	union drm_amdgpu_sched *args = data;
-+	struct amdgpu_device *adev = dev->dev_private;
-+	enum amd_sched_priority priority;
-+	int r;
-+
-+	priority = amdgpu_to_sched_priority(args->in.priority);
-+	if (args->in.flags || priority == AMD_SCHED_PRIORITY_INVALID)
-+		return -EINVAL;
-+
-+	switch (args->in.op) {
-+	case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE:
-+		r = amdgpu_sched_process_priority_override(adev,
-+							   args->in.fd,
-+							   priority);
-+		break;
-+	default:
-+		DRM_ERROR("Invalid sched op specified: %d\n", args->in.op);
-+		r = -EINVAL;
-+		break;
-+	}
-+
-+	return r;
-+}
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h.0130~	2017-12-14 06:39:58.381903544 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h	2017-12-14 06:39:58.381903544 +0100
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2017 Valve Corporation
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: Andres Rodriguez <andresx7@gmail.com>
-+ */
-+
-+#ifndef __AMDGPU_SCHED_H__
-+#define __AMDGPU_SCHED_H__
-+
-+#include <drm/drmP.h>
-+
-+enum amd_sched_priority amdgpu_to_sched_priority(int amdgpu_priority);
-+int amdgpu_sched_ioctl(struct drm_device *dev, void *data,
-+		       struct drm_file *filp);
-+
-+#endif // __AMDGPU_SCHED_H__
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c	2017-12-14 06:39:58.381903544 +0100
-@@ -169,14 +169,14 @@ int amdgpu_sync_fence(struct amdgpu_devi
-  *
-  * @sync: sync object to add fences from reservation object to
-  * @resv: reservation object with embedded fence
-- * @shared: true if we should only sync to the exclusive fence
-+ * @explicit_sync: true if we should only sync to the exclusive fence
-  *
-  * Sync to the fence
-  */
- int amdgpu_sync_resv(struct amdgpu_device *adev,
- 		     struct amdgpu_sync *sync,
- 		     struct reservation_object *resv,
--		     void *owner)
-+		     void *owner, bool explicit_sync)
- {
- 	struct reservation_object_list *flist;
- 	struct dma_fence *f;
-@@ -191,6 +191,9 @@ int amdgpu_sync_resv(struct amdgpu_devic
- 	f = reservation_object_get_excl(resv);
- 	r = amdgpu_sync_fence(adev, sync, f);
- 
-+	if (explicit_sync)
-+		return r;
-+
- 	flist = reservation_object_get_list(resv);
- 	if (!flist || r)
- 		return r;
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h	2017-12-14 06:39:58.381903544 +0100
-@@ -45,7 +45,8 @@ int amdgpu_sync_fence(struct amdgpu_devi
- int amdgpu_sync_resv(struct amdgpu_device *adev,
- 		     struct amdgpu_sync *sync,
- 		     struct reservation_object *resv,
--		     void *owner);
-+		     void *owner,
-+		     bool explicit_sync);
- struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
- 				     struct amdgpu_ring *ring);
- struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h	2017-12-14 06:39:58.381903544 +0100
-@@ -15,62 +15,6 @@
- #define AMDGPU_JOB_GET_TIMELINE_NAME(job) \
- 	 job->base.s_fence->finished.ops->get_timeline_name(&job->base.s_fence->finished)
- 
--TRACE_EVENT(amdgpu_ttm_tt_populate,
--	    TP_PROTO(struct amdgpu_device *adev, uint64_t dma_address, uint64_t phys_address),
--	    TP_ARGS(adev, dma_address, phys_address),
--	    TP_STRUCT__entry(
--				__field(uint16_t, domain)
--				__field(uint8_t, bus)
--				__field(uint8_t, slot)
--				__field(uint8_t, func)
--				__field(uint64_t, dma)
--				__field(uint64_t, phys)
--			    ),
--	    TP_fast_assign(
--			   __entry->domain = pci_domain_nr(adev->pdev->bus);
--			   __entry->bus = adev->pdev->bus->number;
--			   __entry->slot = PCI_SLOT(adev->pdev->devfn);
--			   __entry->func = PCI_FUNC(adev->pdev->devfn);
--			   __entry->dma = dma_address;
--			   __entry->phys = phys_address;
--			   ),
--	    TP_printk("%04x:%02x:%02x.%x: 0x%llx => 0x%llx",
--		      (unsigned)__entry->domain,
--		      (unsigned)__entry->bus,
--		      (unsigned)__entry->slot,
--		      (unsigned)__entry->func,
--		      (unsigned long long)__entry->dma,
--		      (unsigned long long)__entry->phys)
--);
--
--TRACE_EVENT(amdgpu_ttm_tt_unpopulate,
--	    TP_PROTO(struct amdgpu_device *adev, uint64_t dma_address, uint64_t phys_address),
--	    TP_ARGS(adev, dma_address, phys_address),
--	    TP_STRUCT__entry(
--				__field(uint16_t, domain)
--				__field(uint8_t, bus)
--				__field(uint8_t, slot)
--				__field(uint8_t, func)
--				__field(uint64_t, dma)
--				__field(uint64_t, phys)
--			    ),
--	    TP_fast_assign(
--			   __entry->domain = pci_domain_nr(adev->pdev->bus);
--			   __entry->bus = adev->pdev->bus->number;
--			   __entry->slot = PCI_SLOT(adev->pdev->devfn);
--			   __entry->func = PCI_FUNC(adev->pdev->devfn);
--			   __entry->dma = dma_address;
--			   __entry->phys = phys_address;
--			   ),
--	    TP_printk("%04x:%02x:%02x.%x: 0x%llx => 0x%llx",
--		      (unsigned)__entry->domain,
--		      (unsigned)__entry->bus,
--		      (unsigned)__entry->slot,
--		      (unsigned)__entry->func,
--		      (unsigned long long)__entry->dma,
--		      (unsigned long long)__entry->phys)
--);
--
- TRACE_EVENT(amdgpu_mm_rreg,
- 	    TP_PROTO(unsigned did, uint32_t reg, uint32_t value),
- 	    TP_ARGS(did, reg, value),
-@@ -474,5 +418,5 @@ TRACE_EVENT(amdgpu_ttm_bo_move,
- 
- /* This part must be outside protection */
- #undef TRACE_INCLUDE_PATH
--#define TRACE_INCLUDE_PATH .
-+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/amd/amdgpu
- #include <trace/define_trace.h>
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c	2017-12-14 06:39:58.382903544 +0100
-@@ -42,7 +42,9 @@
- #include <linux/swap.h>
- #include <linux/pagemap.h>
- #include <linux/debugfs.h>
-+#include <linux/iommu.h>
- #include "amdgpu.h"
-+#include "amdgpu_object.h"
- #include "amdgpu_trace.h"
- #include "bif/bif_4_1_d.h"
- 
-@@ -108,7 +110,7 @@ static int amdgpu_ttm_global_init(struct
- 	ring = adev->mman.buffer_funcs_ring;
- 	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
- 	r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
--				  rq, amdgpu_sched_jobs);
-+				  rq, amdgpu_sched_jobs, NULL);
- 	if (r) {
- 		DRM_ERROR("Failed setting up TTM BO move run queue.\n");
- 		goto error_entity;
-@@ -208,7 +210,7 @@ static void amdgpu_evict_flags(struct tt
- 		placement->num_busy_placement = 1;
- 		return;
- 	}
--	abo = container_of(bo, struct amdgpu_bo, tbo);
-+	abo = ttm_to_amdgpu_bo(bo);
- 	switch (bo->mem.mem_type) {
- 	case TTM_PL_VRAM:
- 		if (adev->mman.buffer_funcs &&
-@@ -256,7 +258,7 @@ gtt:
- 
- static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
- {
--	struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
-+	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
- 
- 	if (amdgpu_ttm_tt_get_usermm(bo->ttm))
- 		return -EPERM;
-@@ -280,105 +282,184 @@ static uint64_t amdgpu_mm_node_addr(stru
- {
- 	uint64_t addr = 0;
- 
--	if (mem->mem_type != TTM_PL_TT ||
--	    amdgpu_gtt_mgr_is_allocated(mem)) {
-+	if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) {
- 		addr = mm_node->start << PAGE_SHIFT;
- 		addr += bo->bdev->man[mem->mem_type].gpu_offset;
- 	}
- 	return addr;
- }
- 
--static int amdgpu_move_blit(struct ttm_buffer_object *bo,
--			    bool evict, bool no_wait_gpu,
--			    struct ttm_mem_reg *new_mem,
--			    struct ttm_mem_reg *old_mem)
-+/**
-+ * amdgpu_find_mm_node - Helper function finds the drm_mm_node
-+ *  corresponding to @offset. It also modifies the offset to be
-+ *  within the drm_mm_node returned
-+ */
-+static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
-+					       unsigned long *offset)
- {
--	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
--	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
-+	struct drm_mm_node *mm_node = mem->mm_node;
- 
--	struct drm_mm_node *old_mm, *new_mm;
--	uint64_t old_start, old_size, new_start, new_size;
--	unsigned long num_pages;
--	struct dma_fence *fence = NULL;
--	int r;
-+	while (*offset >= (mm_node->size << PAGE_SHIFT)) {
-+		*offset -= (mm_node->size << PAGE_SHIFT);
-+		++mm_node;
-+	}
-+	return mm_node;
-+}
- 
--	BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
-+/**
-+ * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
-+ *
-+ * The function copies @size bytes from {src->mem + src->offset} to
-+ * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
-+ * move and different for a BO to BO copy.
-+ *
-+ * @f: Returns the last fence if multiple jobs are submitted.
-+ */
-+int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
-+			       struct amdgpu_copy_mem *src,
-+			       struct amdgpu_copy_mem *dst,
-+			       uint64_t size,
-+			       struct reservation_object *resv,
-+			       struct dma_fence **f)
-+{
-+	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
-+	struct drm_mm_node *src_mm, *dst_mm;
-+	uint64_t src_node_start, dst_node_start, src_node_size,
-+		 dst_node_size, src_page_offset, dst_page_offset;
-+	struct dma_fence *fence = NULL;
-+	int r = 0;
-+	const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
-+					AMDGPU_GPU_PAGE_SIZE);
- 
- 	if (!ring->ready) {
- 		DRM_ERROR("Trying to move memory with ring turned off.\n");
- 		return -EINVAL;
- 	}
- 
--	old_mm = old_mem->mm_node;
--	old_size = old_mm->size;
--	old_start = amdgpu_mm_node_addr(bo, old_mm, old_mem);
--
--	new_mm = new_mem->mm_node;
--	new_size = new_mm->size;
--	new_start = amdgpu_mm_node_addr(bo, new_mm, new_mem);
-+	src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
-+	src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
-+					     src->offset;
-+	src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
-+	src_page_offset = src_node_start & (PAGE_SIZE - 1);
-+
-+	dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
-+	dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
-+					     dst->offset;
-+	dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
-+	dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
- 
--	num_pages = new_mem->num_pages;
- 	mutex_lock(&adev->mman.gtt_window_lock);
--	while (num_pages) {
--		unsigned long cur_pages = min(min(old_size, new_size),
--					      (u64)AMDGPU_GTT_MAX_TRANSFER_SIZE);
--		uint64_t from = old_start, to = new_start;
-+
-+	while (size) {
-+		unsigned long cur_size;
-+		uint64_t from = src_node_start, to = dst_node_start;
- 		struct dma_fence *next;
- 
--		if (old_mem->mem_type == TTM_PL_TT &&
--		    !amdgpu_gtt_mgr_is_allocated(old_mem)) {
--			r = amdgpu_map_buffer(bo, old_mem, cur_pages,
--					      old_start, 0, ring, &from);
-+		/* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
-+		 * begins at an offset, then adjust the size accordingly
-+		 */
-+		cur_size = min3(min(src_node_size, dst_node_size), size,
-+				GTT_MAX_BYTES);
-+		if (cur_size + src_page_offset > GTT_MAX_BYTES ||
-+		    cur_size + dst_page_offset > GTT_MAX_BYTES)
-+			cur_size -= max(src_page_offset, dst_page_offset);
-+
-+		/* Map only what needs to be accessed. Map src to window 0 and
-+		 * dst to window 1
-+		 */
-+		if (src->mem->mem_type == TTM_PL_TT &&
-+		    !amdgpu_gtt_mgr_has_gart_addr(src->mem)) {
-+			r = amdgpu_map_buffer(src->bo, src->mem,
-+					PFN_UP(cur_size + src_page_offset),
-+					src_node_start, 0, ring,
-+					&from);
- 			if (r)
- 				goto error;
-+			/* Adjust the offset because amdgpu_map_buffer returns
-+			 * start of mapped page
-+			 */
-+			from += src_page_offset;
- 		}
- 
--		if (new_mem->mem_type == TTM_PL_TT &&
--		    !amdgpu_gtt_mgr_is_allocated(new_mem)) {
--			r = amdgpu_map_buffer(bo, new_mem, cur_pages,
--					      new_start, 1, ring, &to);
-+		if (dst->mem->mem_type == TTM_PL_TT &&
-+		    !amdgpu_gtt_mgr_has_gart_addr(dst->mem)) {
-+			r = amdgpu_map_buffer(dst->bo, dst->mem,
-+					PFN_UP(cur_size + dst_page_offset),
-+					dst_node_start, 1, ring,
-+					&to);
- 			if (r)
- 				goto error;
-+			to += dst_page_offset;
- 		}
- 
--		r = amdgpu_copy_buffer(ring, from, to,
--				       cur_pages * PAGE_SIZE,
--				       bo->resv, &next, false, true);
-+		r = amdgpu_copy_buffer(ring, from, to, cur_size,
-+				       resv, &next, false, true);
- 		if (r)
- 			goto error;
- 
- 		dma_fence_put(fence);
- 		fence = next;
- 
--		num_pages -= cur_pages;
--		if (!num_pages)
-+		size -= cur_size;
-+		if (!size)
- 			break;
- 
--		old_size -= cur_pages;
--		if (!old_size) {
--			old_start = amdgpu_mm_node_addr(bo, ++old_mm, old_mem);
--			old_size = old_mm->size;
-+		src_node_size -= cur_size;
-+		if (!src_node_size) {
-+			src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
-+							     src->mem);
-+			src_node_size = (src_mm->size << PAGE_SHIFT);
- 		} else {
--			old_start += cur_pages * PAGE_SIZE;
-+			src_node_start += cur_size;
-+			src_page_offset = src_node_start & (PAGE_SIZE - 1);
- 		}
--
--		new_size -= cur_pages;
--		if (!new_size) {
--			new_start = amdgpu_mm_node_addr(bo, ++new_mm, new_mem);
--			new_size = new_mm->size;
-+		dst_node_size -= cur_size;
-+		if (!dst_node_size) {
-+			dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
-+							     dst->mem);
-+			dst_node_size = (dst_mm->size << PAGE_SHIFT);
- 		} else {
--			new_start += cur_pages * PAGE_SIZE;
-+			dst_node_start += cur_size;
-+			dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
- 		}
- 	}
-+error:
- 	mutex_unlock(&adev->mman.gtt_window_lock);
-+	if (f)
-+		*f = dma_fence_get(fence);
-+	dma_fence_put(fence);
-+	return r;
-+}
-+
-+
-+static int amdgpu_move_blit(struct ttm_buffer_object *bo,
-+			    bool evict, bool no_wait_gpu,
-+			    struct ttm_mem_reg *new_mem,
-+			    struct ttm_mem_reg *old_mem)
-+{
-+	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
-+	struct amdgpu_copy_mem src, dst;
-+	struct dma_fence *fence = NULL;
-+	int r;
-+
-+	src.bo = bo;
-+	dst.bo = bo;
-+	src.mem = old_mem;
-+	dst.mem = new_mem;
-+	src.offset = 0;
-+	dst.offset = 0;
-+
-+	r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
-+				       new_mem->num_pages << PAGE_SHIFT,
-+				       bo->resv, &fence);
-+	if (r)
-+		goto error;
- 
- 	r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
- 	dma_fence_put(fence);
- 	return r;
- 
- error:
--	mutex_unlock(&adev->mman.gtt_window_lock);
--
- 	if (fence)
- 		dma_fence_wait(fence, false);
- 	dma_fence_put(fence);
-@@ -483,7 +564,7 @@ static int amdgpu_bo_move(struct ttm_buf
- 	int r;
- 
- 	/* Can't move a pinned BO */
--	abo = container_of(bo, struct amdgpu_bo, tbo);
-+	abo = ttm_to_amdgpu_bo(bo);
- 	if (WARN_ON_ONCE(abo->pin_count > 0))
- 		return -EINVAL;
- 
-@@ -581,13 +662,12 @@ static void amdgpu_ttm_io_mem_free(struc
- static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
- 					   unsigned long page_offset)
- {
--	struct drm_mm_node *mm = bo->mem.mm_node;
--	uint64_t size = mm->size;
--	uint64_t offset = page_offset;
--
--	page_offset = do_div(offset, size);
--	mm += offset;
--	return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset;
-+	struct drm_mm_node *mm;
-+	unsigned long offset = (page_offset << PAGE_SHIFT);
-+
-+	mm = amdgpu_find_mm_node(&bo->mem, &offset);
-+	return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
-+		(offset >> PAGE_SHIFT);
- }
- 
- /*
-@@ -608,7 +688,7 @@ struct amdgpu_ttm_tt {
- 	spinlock_t              guptasklock;
- 	struct list_head        guptasks;
- 	atomic_t		mmu_invalidations;
--	struct list_head        list;
-+	uint32_t		last_set_pages;
- };
- 
- int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
-@@ -621,6 +701,8 @@ int amdgpu_ttm_tt_get_user_pages(struct
- 	if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
- 		flags |= FOLL_WRITE;
- 
-+	down_read(&current->mm->mmap_sem);
-+
- 	if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
- 		/* check that we only use anonymous memory
- 		   to prevent problems with writeback */
-@@ -628,8 +710,10 @@ int amdgpu_ttm_tt_get_user_pages(struct
- 		struct vm_area_struct *vma;
- 
- 		vma = find_vma(gtt->usermm, gtt->userptr);
--		if (!vma || vma->vm_file || vma->vm_end < end)
-+		if (!vma || vma->vm_file || vma->vm_end < end) {
-+			up_read(&current->mm->mmap_sem);
- 			return -EPERM;
-+		}
- 	}
- 
- 	do {
-@@ -656,42 +740,44 @@ int amdgpu_ttm_tt_get_user_pages(struct
- 
- 	} while (pinned < ttm->num_pages);
- 
-+	up_read(&current->mm->mmap_sem);
- 	return 0;
- 
- release_pages:
- 	release_pages(pages, pinned, 0);
-+	up_read(&current->mm->mmap_sem);
- 	return r;
- }
- 
--static void amdgpu_trace_dma_map(struct ttm_tt *ttm)
-+void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
- {
--	struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
- 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
- 	unsigned i;
- 
--	if (unlikely(trace_amdgpu_ttm_tt_populate_enabled())) {
--		for (i = 0; i < ttm->num_pages; i++) {
--			trace_amdgpu_ttm_tt_populate(
--				adev,
--				gtt->ttm.dma_address[i],
--				page_to_phys(ttm->pages[i]));
--		}
-+	gtt->last_set_pages = atomic_read(&gtt->mmu_invalidations);
-+	for (i = 0; i < ttm->num_pages; ++i) {
-+		if (ttm->pages[i])
-+			put_page(ttm->pages[i]);
-+
-+		ttm->pages[i] = pages ? pages[i] : NULL;
- 	}
- }
- 
--static void amdgpu_trace_dma_unmap(struct ttm_tt *ttm)
-+void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
- {
--	struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
- 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
- 	unsigned i;
- 
--	if (unlikely(trace_amdgpu_ttm_tt_unpopulate_enabled())) {
--		for (i = 0; i < ttm->num_pages; i++) {
--			trace_amdgpu_ttm_tt_unpopulate(
--				adev,
--				gtt->ttm.dma_address[i],
--				page_to_phys(ttm->pages[i]));
--		}
-+	for (i = 0; i < ttm->num_pages; ++i) {
-+		struct page *page = ttm->pages[i];
-+
-+		if (!page)
-+			continue;
-+
-+		if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
-+			set_page_dirty(page);
-+
-+		mark_page_accessed(page);
- 	}
- }
- 
-@@ -721,8 +807,6 @@ static int amdgpu_ttm_tt_pin_userptr(str
- 	drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
- 					 gtt->ttm.dma_address, ttm->num_pages);
- 
--	amdgpu_trace_dma_map(ttm);
--
- 	return 0;
- 
- release_sg:
-@@ -734,7 +818,6 @@ static void amdgpu_ttm_tt_unpin_userptr(
- {
- 	struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
- 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
--	struct sg_page_iter sg_iter;
- 
- 	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
- 	enum dma_data_direction direction = write ?
-@@ -747,16 +830,7 @@ static void amdgpu_ttm_tt_unpin_userptr(
- 	/* free the sg table and pages again */
- 	dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
- 
--	for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
--		struct page *page = sg_page_iter_page(&sg_iter);
--		if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
--			set_page_dirty(page);
--
--		mark_page_accessed(page);
--		put_page(page);
--	}
--
--	amdgpu_trace_dma_unmap(ttm);
-+	amdgpu_ttm_tt_mark_user_pages(ttm);
- 
- 	sg_free_table(ttm->sg);
- }
-@@ -785,45 +859,34 @@ static int amdgpu_ttm_backend_bind(struc
- 	    bo_mem->mem_type == AMDGPU_PL_OA)
- 		return -EINVAL;
- 
--	if (!amdgpu_gtt_mgr_is_allocated(bo_mem))
-+	if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
-+		gtt->offset = AMDGPU_BO_INVALID_OFFSET;
- 		return 0;
-+	}
- 
--	spin_lock(&gtt->adev->gtt_list_lock);
- 	flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
- 	gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
- 	r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
- 		ttm->pages, gtt->ttm.dma_address, flags);
- 
--	if (r) {
-+	if (r)
- 		DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
- 			  ttm->num_pages, gtt->offset);
--		goto error_gart_bind;
--	}
--
--	list_add_tail(&gtt->list, &gtt->adev->gtt_list);
--error_gart_bind:
--	spin_unlock(&gtt->adev->gtt_list_lock);
- 	return r;
- }
- 
--bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
--{
--	struct amdgpu_ttm_tt *gtt = (void *)ttm;
--
--	return gtt && !list_empty(&gtt->list);
--}
--
--int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
-+int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
- {
- 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
--	struct ttm_tt *ttm = bo->ttm;
-+	struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
- 	struct ttm_mem_reg tmp;
--
- 	struct ttm_placement placement;
- 	struct ttm_place placements;
-+	uint64_t flags;
- 	int r;
- 
--	if (!ttm || amdgpu_ttm_is_bound(ttm))
-+	if (bo->mem.mem_type != TTM_PL_TT ||
-+	    amdgpu_gtt_mgr_has_gart_addr(&bo->mem))
- 		return 0;
- 
- 	tmp = bo->mem;
-@@ -834,45 +897,47 @@ int amdgpu_ttm_bind(struct ttm_buffer_ob
- 	placement.busy_placement = &placements;
- 	placements.fpfn = 0;
- 	placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT;
--	placements.flags = bo->mem.placement | TTM_PL_FLAG_TT;
-+	placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
-+		TTM_PL_FLAG_TT;
- 
--	r = ttm_bo_mem_space(bo, &placement, &tmp, true, false);
-+	r = ttm_bo_mem_space(bo, &placement, &tmp, false, false);
- 	if (unlikely(r))
- 		return r;
- 
--	r = ttm_bo_move_ttm(bo, true, false, &tmp);
--	if (unlikely(r))
-+	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
-+	gtt->offset = (u64)tmp.start << PAGE_SHIFT;
-+	r = amdgpu_gart_bind(adev, gtt->offset, bo->ttm->num_pages,
-+			     bo->ttm->pages, gtt->ttm.dma_address, flags);
-+	if (unlikely(r)) {
- 		ttm_bo_mem_put(bo, &tmp);
--	else
--		bo->offset = (bo->mem.start << PAGE_SHIFT) +
--			bo->bdev->man[bo->mem.mem_type].gpu_offset;
-+		return r;
-+	}
- 
--	return r;
-+	ttm_bo_mem_put(bo, &bo->mem);
-+	bo->mem = tmp;
-+	bo->offset = (bo->mem.start << PAGE_SHIFT) +
-+		bo->bdev->man[bo->mem.mem_type].gpu_offset;
-+
-+	return 0;
- }
- 
--int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
-+int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
- {
--	struct amdgpu_ttm_tt *gtt, *tmp;
--	struct ttm_mem_reg bo_mem;
-+	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
-+	struct amdgpu_ttm_tt *gtt = (void *)tbo->ttm;
- 	uint64_t flags;
- 	int r;
- 
--	bo_mem.mem_type = TTM_PL_TT;
--	spin_lock(&adev->gtt_list_lock);
--	list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
--		flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
--		r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
--				     gtt->ttm.ttm.pages, gtt->ttm.dma_address,
--				     flags);
--		if (r) {
--			spin_unlock(&adev->gtt_list_lock);
--			DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
--				  gtt->ttm.ttm.num_pages, gtt->offset);
--			return r;
--		}
--	}
--	spin_unlock(&adev->gtt_list_lock);
--	return 0;
-+	if (!gtt)
-+		return 0;
-+
-+	flags = amdgpu_ttm_tt_pte_flags(adev, &gtt->ttm.ttm, &tbo->mem);
-+	r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
-+			     gtt->ttm.ttm.pages, gtt->ttm.dma_address, flags);
-+	if (r)
-+		DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
-+			  gtt->ttm.ttm.num_pages, gtt->offset);
-+	return r;
- }
- 
- static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
-@@ -883,20 +948,14 @@ static int amdgpu_ttm_backend_unbind(str
- 	if (gtt->userptr)
- 		amdgpu_ttm_tt_unpin_userptr(ttm);
- 
--	if (!amdgpu_ttm_is_bound(ttm))
-+	if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
- 		return 0;
- 
- 	/* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
--	spin_lock(&gtt->adev->gtt_list_lock);
- 	r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
--	if (r) {
-+	if (r)
- 		DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
- 			  gtt->ttm.ttm.num_pages, gtt->offset);
--		goto error_unbind;
--	}
--	list_del_init(&gtt->list);
--error_unbind:
--	spin_unlock(&gtt->adev->gtt_list_lock);
- 	return r;
- }
- 
-@@ -933,7 +992,6 @@ static struct ttm_tt *amdgpu_ttm_tt_crea
- 		kfree(gtt);
- 		return NULL;
- 	}
--	INIT_LIST_HEAD(&gtt->list);
- 	return &gtt->ttm.ttm;
- }
- 
-@@ -941,8 +999,6 @@ static int amdgpu_ttm_tt_populate(struct
- {
- 	struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
- 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
--	unsigned i;
--	int r;
- 	bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
- 
- 	if (ttm->state != tt_unpopulated)
-@@ -962,52 +1018,26 @@ static int amdgpu_ttm_tt_populate(struct
- 		drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
- 						 gtt->ttm.dma_address, ttm->num_pages);
- 		ttm->state = tt_unbound;
--		r = 0;
--		goto trace_mappings;
-+		return 0;
- 	}
- 
- #ifdef CONFIG_SWIOTLB
- 	if (swiotlb_nr_tbl()) {
--		r = ttm_dma_populate(&gtt->ttm, adev->dev);
--		goto trace_mappings;
-+		return ttm_dma_populate(&gtt->ttm, adev->dev);
- 	}
- #endif
- 
--	r = ttm_pool_populate(ttm);
--	if (r) {
--		return r;
--	}
--
--	for (i = 0; i < ttm->num_pages; i++) {
--		gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
--						       0, PAGE_SIZE,
--						       PCI_DMA_BIDIRECTIONAL);
--		if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
--			while (i--) {
--				pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
--					       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
--				gtt->ttm.dma_address[i] = 0;
--			}
--			ttm_pool_unpopulate(ttm);
--			return -EFAULT;
--		}
--	}
--
--	r = 0;
--trace_mappings:
--	if (likely(!r))
--		amdgpu_trace_dma_map(ttm);
--	return r;
-+	return ttm_populate_and_map_pages(adev->dev, &gtt->ttm);
- }
- 
- static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
- {
- 	struct amdgpu_device *adev;
- 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
--	unsigned i;
- 	bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
- 
- 	if (gtt && gtt->userptr) {
-+		amdgpu_ttm_tt_set_user_pages(ttm, NULL);
- 		kfree(ttm->sg);
- 		ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
- 		return;
-@@ -1018,8 +1048,6 @@ static void amdgpu_ttm_tt_unpopulate(str
- 
- 	adev = amdgpu_ttm_adev(ttm->bdev);
- 
--	amdgpu_trace_dma_unmap(ttm);
--
- #ifdef CONFIG_SWIOTLB
- 	if (swiotlb_nr_tbl()) {
- 		ttm_dma_unpopulate(&gtt->ttm, adev->dev);
-@@ -1027,14 +1055,7 @@ static void amdgpu_ttm_tt_unpopulate(str
- 	}
- #endif
- 
--	for (i = 0; i < ttm->num_pages; i++) {
--		if (gtt->ttm.dma_address[i]) {
--			pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
--				       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
--		}
--	}
--
--	ttm_pool_unpopulate(ttm);
-+	ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
- }
- 
- int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
-@@ -1051,6 +1072,7 @@ int amdgpu_ttm_tt_set_userptr(struct ttm
- 	spin_lock_init(&gtt->guptasklock);
- 	INIT_LIST_HEAD(&gtt->guptasks);
- 	atomic_set(&gtt->mmu_invalidations, 0);
-+	gtt->last_set_pages = 0;
- 
- 	return 0;
- }
-@@ -1103,6 +1125,16 @@ bool amdgpu_ttm_tt_userptr_invalidated(s
- 	return prev_invalidated != *last_invalidated;
- }
- 
-+bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
-+{
-+	struct amdgpu_ttm_tt *gtt = (void *)ttm;
-+
-+	if (gtt == NULL || !gtt->userptr)
-+		return false;
-+
-+	return atomic_read(&gtt->mmu_invalidations) != gtt->last_set_pages;
-+}
-+
- bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
- {
- 	struct amdgpu_ttm_tt *gtt = (void *)ttm;
-@@ -1143,9 +1175,6 @@ static bool amdgpu_ttm_bo_eviction_valua
- 	unsigned long num_pages = bo->mem.num_pages;
- 	struct drm_mm_node *node = bo->mem.mm_node;
- 
--	if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
--		return ttm_bo_eviction_valuable(bo, place);
--
- 	switch (bo->mem.mem_type) {
- 	case TTM_PL_TT:
- 		return true;
-@@ -1160,7 +1189,7 @@ static bool amdgpu_ttm_bo_eviction_valua
- 			num_pages -= node->size;
- 			++node;
- 		}
--		break;
-+		return false;
- 
- 	default:
- 		break;
-@@ -1173,9 +1202,9 @@ static int amdgpu_ttm_access_memory(stru
- 				    unsigned long offset,
- 				    void *buf, int len, int write)
- {
--	struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
-+	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
- 	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
--	struct drm_mm_node *nodes = abo->tbo.mem.mm_node;
-+	struct drm_mm_node *nodes;
- 	uint32_t value = 0;
- 	int ret = 0;
- 	uint64_t pos;
-@@ -1184,10 +1213,7 @@ static int amdgpu_ttm_access_memory(stru
- 	if (bo->mem.mem_type != TTM_PL_VRAM)
- 		return -EIO;
- 
--	while (offset >= (nodes->size << PAGE_SHIFT)) {
--		offset -= nodes->size << PAGE_SHIFT;
--		++nodes;
--	}
-+	nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
- 	pos = (nodes->start << PAGE_SHIFT) + offset;
- 
- 	while (len && pos < adev->mc.mc_vram_size) {
-@@ -1202,14 +1228,14 @@ static int amdgpu_ttm_access_memory(stru
- 		}
- 
- 		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
--		WREG32(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
--		WREG32(mmMM_INDEX_HI, aligned_pos >> 31);
-+		WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
-+		WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
- 		if (!write || mask != 0xffffffff)
--			value = RREG32(mmMM_DATA);
-+			value = RREG32_NO_KIQ(mmMM_DATA);
- 		if (write) {
- 			value &= ~mask;
- 			value |= (*(uint32_t *)buf << shift) & mask;
--			WREG32(mmMM_DATA, value);
-+			WREG32_NO_KIQ(mmMM_DATA, value);
- 		}
- 		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
- 		if (!write) {
-@@ -1286,6 +1312,15 @@ int amdgpu_ttm_init(struct amdgpu_device
- 	/* Change the size here instead of the init above so only lpfn is affected */
- 	amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
- 
-+	/*
-+	 *The reserved vram for firmware must be pinned to the specified
-+	 *place on the VRAM, so reserve it early.
-+	 */
-+	r = amdgpu_fw_reserve_vram_init(adev);
-+	if (r) {
-+		return r;
-+	}
-+
- 	r = amdgpu_bo_create_kernel(adev, adev->mc.stolen_size, PAGE_SIZE,
- 				    AMDGPU_GEM_DOMAIN_VRAM,
- 				    &adev->stolen_vga_memory,
-@@ -1295,9 +1330,14 @@ int amdgpu_ttm_init(struct amdgpu_device
- 	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
- 		 (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
- 
--	if (amdgpu_gtt_size == -1)
--		gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
--			       adev->mc.mc_vram_size);
-+	if (amdgpu_gtt_size == -1) {
-+		struct sysinfo si;
-+
-+		si_meminfo(&si);
-+		gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
-+			       adev->mc.mc_vram_size),
-+			       ((uint64_t)si.totalram * si.mem_unit * 3/4));
-+	}
- 	else
- 		gtt_size = (uint64_t)amdgpu_gtt_size << 20;
- 	r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
-@@ -1357,19 +1397,13 @@ int amdgpu_ttm_init(struct amdgpu_device
- 
- void amdgpu_ttm_fini(struct amdgpu_device *adev)
- {
--	int r;
--
- 	if (!adev->mman.initialized)
- 		return;
-+
- 	amdgpu_ttm_debugfs_fini(adev);
--	if (adev->stolen_vga_memory) {
--		r = amdgpu_bo_reserve(adev->stolen_vga_memory, true);
--		if (r == 0) {
--			amdgpu_bo_unpin(adev->stolen_vga_memory);
--			amdgpu_bo_unreserve(adev->stolen_vga_memory);
--		}
--		amdgpu_bo_unref(&adev->stolen_vga_memory);
--	}
-+	amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
-+	amdgpu_fw_reserve_vram_fini(adev);
-+
- 	ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
- 	ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
- 	if (adev->gds.mem.total_size)
-@@ -1379,7 +1413,6 @@ void amdgpu_ttm_fini(struct amdgpu_devic
- 	if (adev->gds.oa.total_size)
- 		ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
- 	ttm_bo_device_release(&adev->mman.bdev);
--	amdgpu_gart_fini(adev);
- 	amdgpu_ttm_global_fini(adev);
- 	adev->mman.initialized = false;
- 	DRM_INFO("amdgpu: ttm finalized\n");
-@@ -1510,7 +1543,8 @@ int amdgpu_copy_buffer(struct amdgpu_rin
- 	job->vm_needs_flush = vm_needs_flush;
- 	if (resv) {
- 		r = amdgpu_sync_resv(adev, &job->sync, resv,
--				     AMDGPU_FENCE_OWNER_UNDEFINED);
-+				     AMDGPU_FENCE_OWNER_UNDEFINED,
-+				     false);
- 		if (r) {
- 			DRM_ERROR("sync failed (%d).\n", r);
- 			goto error_free;
-@@ -1557,8 +1591,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo
- 		       struct dma_fence **fence)
- {
- 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
--	/* max_bytes applies to SDMA_OP_PTEPDE as well as SDMA_OP_CONST_FILL*/
--	uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
-+	uint32_t max_bytes = 8 *
-+			adev->vm_manager.vm_pte_funcs->set_max_nums_pte_pde;
- 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
- 
- 	struct drm_mm_node *mm_node;
-@@ -1574,7 +1608,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo
- 	}
- 
- 	if (bo->tbo.mem.mem_type == TTM_PL_TT) {
--		r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
-+		r = amdgpu_ttm_alloc_gart(&bo->tbo);
- 		if (r)
- 			return r;
- 	}
-@@ -1590,8 +1624,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo
- 		++mm_node;
- 	}
- 
--	/* 10 double words for each SDMA_OP_PTEPDE cmd */
--	num_dw = num_loops * 10;
-+	/* num of dwords for each SDMA_OP_PTEPDE cmd */
-+	num_dw = num_loops * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;
- 
- 	/* for IB padding */
- 	num_dw += 64;
-@@ -1602,7 +1636,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo
- 
- 	if (resv) {
- 		r = amdgpu_sync_resv(adev, &job->sync, resv,
--				     AMDGPU_FENCE_OWNER_UNDEFINED);
-+				     AMDGPU_FENCE_OWNER_UNDEFINED, false);
- 		if (r) {
- 			DRM_ERROR("sync failed (%d).\n", r);
- 			goto error_free;
-@@ -1697,9 +1731,9 @@ static ssize_t amdgpu_ttm_vram_read(stru
- 			return result;
- 
- 		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
--		WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
--		WREG32(mmMM_INDEX_HI, *pos >> 31);
--		value = RREG32(mmMM_DATA);
-+		WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
-+		WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
-+		value = RREG32_NO_KIQ(mmMM_DATA);
- 		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
- 
- 		r = put_user(value, (uint32_t *)buf);
-@@ -1715,10 +1749,50 @@ static ssize_t amdgpu_ttm_vram_read(stru
- 	return result;
- }
- 
-+static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
-+				    size_t size, loff_t *pos)
-+{
-+	struct amdgpu_device *adev = file_inode(f)->i_private;
-+	ssize_t result = 0;
-+	int r;
-+
-+	if (size & 0x3 || *pos & 0x3)
-+		return -EINVAL;
-+
-+	if (*pos >= adev->mc.mc_vram_size)
-+		return -ENXIO;
-+
-+	while (size) {
-+		unsigned long flags;
-+		uint32_t value;
-+
-+		if (*pos >= adev->mc.mc_vram_size)
-+			return result;
-+
-+		r = get_user(value, (uint32_t *)buf);
-+		if (r)
-+			return r;
-+
-+		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
-+		WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
-+		WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
-+		WREG32_NO_KIQ(mmMM_DATA, value);
-+		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
-+
-+		result += 4;
-+		buf += 4;
-+		*pos += 4;
-+		size -= 4;
-+	}
-+
-+	return result;
-+}
-+
- static const struct file_operations amdgpu_ttm_vram_fops = {
- 	.owner = THIS_MODULE,
- 	.read = amdgpu_ttm_vram_read,
--	.llseek = default_llseek
-+	.write = amdgpu_ttm_vram_write,
-+	.llseek = default_llseek,
- };
- 
- #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
-@@ -1770,6 +1844,53 @@ static const struct file_operations amdg
- 
- #endif
- 
-+static ssize_t amdgpu_iova_to_phys_read(struct file *f, char __user *buf,
-+				   size_t size, loff_t *pos)
-+{
-+	struct amdgpu_device *adev = file_inode(f)->i_private;
-+	int r;
-+	uint64_t phys;
-+	struct iommu_domain *dom;
-+
-+	// always return 8 bytes
-+	if (size != 8)
-+		return -EINVAL;
-+
-+	// only accept page addresses
-+	if (*pos & 0xFFF)
-+		return -EINVAL;
-+
-+	dom = iommu_get_domain_for_dev(adev->dev);
-+	if (dom)
-+		phys = iommu_iova_to_phys(dom, *pos);
-+	else
-+		phys = *pos;
-+
-+	r = copy_to_user(buf, &phys, 8);
-+	if (r)
-+		return -EFAULT;
-+
-+	return 8;
-+}
-+
-+static const struct file_operations amdgpu_ttm_iova_fops = {
-+	.owner = THIS_MODULE,
-+	.read = amdgpu_iova_to_phys_read,
-+	.llseek = default_llseek
-+};
-+
-+static const struct {
-+	char *name;
-+	const struct file_operations *fops;
-+	int domain;
-+} ttm_debugfs_entries[] = {
-+	{ "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
-+#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
-+	{ "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
-+#endif
-+	{ "amdgpu_iova", &amdgpu_ttm_iova_fops, TTM_PL_SYSTEM },
-+};
-+
- #endif
- 
- static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
-@@ -1780,22 +1901,21 @@ static int amdgpu_ttm_debugfs_init(struc
- 	struct drm_minor *minor = adev->ddev->primary;
- 	struct dentry *ent, *root = minor->debugfs_root;
- 
--	ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
--				  adev, &amdgpu_ttm_vram_fops);
--	if (IS_ERR(ent))
--		return PTR_ERR(ent);
--	i_size_write(ent->d_inode, adev->mc.mc_vram_size);
--	adev->mman.vram = ent;
--
--#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
--	ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
--				  adev, &amdgpu_ttm_gtt_fops);
--	if (IS_ERR(ent))
--		return PTR_ERR(ent);
--	i_size_write(ent->d_inode, adev->mc.gart_size);
--	adev->mman.gtt = ent;
-+	for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
-+		ent = debugfs_create_file(
-+				ttm_debugfs_entries[count].name,
-+				S_IFREG | S_IRUGO, root,
-+				adev,
-+				ttm_debugfs_entries[count].fops);
-+		if (IS_ERR(ent))
-+			return PTR_ERR(ent);
-+		if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
-+			i_size_write(ent->d_inode, adev->mc.mc_vram_size);
-+		else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
-+			i_size_write(ent->d_inode, adev->mc.gart_size);
-+		adev->mman.debugfs_entries[count] = ent;
-+	}
- 
--#endif
- 	count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
- 
- #ifdef CONFIG_SWIOTLB
-@@ -1805,7 +1925,6 @@ static int amdgpu_ttm_debugfs_init(struc
- 
- 	return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
- #else
--
- 	return 0;
- #endif
- }
-@@ -1813,14 +1932,9 @@ static int amdgpu_ttm_debugfs_init(struc
- static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
- {
- #if defined(CONFIG_DEBUG_FS)
-+	unsigned i;
- 
--	debugfs_remove(adev->mman.vram);
--	adev->mman.vram = NULL;
--
--#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
--	debugfs_remove(adev->mman.gtt);
--	adev->mman.gtt = NULL;
--#endif
--
-+	for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
-+		debugfs_remove(adev->mman.debugfs_entries[i]);
- #endif
- }
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h	2017-12-14 06:39:58.382903544 +0100
-@@ -24,6 +24,7 @@
- #ifndef __AMDGPU_TTM_H__
- #define __AMDGPU_TTM_H__
- 
-+#include "amdgpu.h"
- #include "gpu_scheduler.h"
- 
- #define AMDGPU_PL_GDS		(TTM_PL_PRIV + 0)
-@@ -45,8 +46,7 @@ struct amdgpu_mman {
- 	bool				initialized;
- 
- #if defined(CONFIG_DEBUG_FS)
--	struct dentry			*vram;
--	struct dentry			*gtt;
-+	struct dentry			*debugfs_entries[8];
- #endif
- 
- 	/* buffer handling */
-@@ -58,11 +58,18 @@ struct amdgpu_mman {
- 	struct amd_sched_entity			entity;
- };
- 
-+struct amdgpu_copy_mem {
-+	struct ttm_buffer_object	*bo;
-+	struct ttm_mem_reg		*mem;
-+	unsigned long			offset;
-+};
-+
- extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
- extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;
- 
--bool amdgpu_gtt_mgr_is_allocated(struct ttm_mem_reg *mem);
-+bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem);
- uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man);
-+int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);
- 
- uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);
- uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);
-@@ -72,14 +79,35 @@ int amdgpu_copy_buffer(struct amdgpu_rin
- 		       struct reservation_object *resv,
- 		       struct dma_fence **fence, bool direct_submit,
- 		       bool vm_needs_flush);
-+int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
-+			       struct amdgpu_copy_mem *src,
-+			       struct amdgpu_copy_mem *dst,
-+			       uint64_t size,
-+			       struct reservation_object *resv,
-+			       struct dma_fence **f);
- int amdgpu_fill_buffer(struct amdgpu_bo *bo,
- 			uint64_t src_data,
- 			struct reservation_object *resv,
- 			struct dma_fence **fence);
- 
- int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
--bool amdgpu_ttm_is_bound(struct ttm_tt *ttm);
--int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem);
--int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
-+int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
-+int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
-+
-+int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
-+void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
-+void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm);
-+int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
-+				     uint32_t flags);
-+bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
-+struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
-+bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
-+				  unsigned long end);
-+bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
-+				       int *last_invalidated);
-+bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm);
-+bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
-+uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
-+				 struct ttm_mem_reg *mem);
- 
- #endif
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c	2017-12-14 06:39:58.382903544 +0100
-@@ -270,12 +270,8 @@ amdgpu_ucode_get_load_type(struct amdgpu
- 		else
- 			return AMDGPU_FW_LOAD_SMU;
- 	case CHIP_VEGA10:
--		if (!load_type)
--			return AMDGPU_FW_LOAD_DIRECT;
--		else
--			return AMDGPU_FW_LOAD_PSP;
- 	case CHIP_RAVEN:
--		if (load_type != 2)
-+		if (!load_type)
- 			return AMDGPU_FW_LOAD_DIRECT;
- 		else
- 			return AMDGPU_FW_LOAD_PSP;
-@@ -363,9 +359,6 @@ static int amdgpu_ucode_patch_jt(struct
- 
- int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
- {
--	struct amdgpu_bo **bo = &adev->firmware.fw_buf;
--	uint64_t fw_mc_addr;
--	void *fw_buf_ptr = NULL;
- 	uint64_t fw_offset = 0;
- 	int i, err;
- 	struct amdgpu_firmware_info *ucode = NULL;
-@@ -376,37 +369,19 @@ int amdgpu_ucode_init_bo(struct amdgpu_d
- 		return 0;
- 	}
- 
--	err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true,
--				amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
--				AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
--				NULL, NULL, 0, bo);
--	if (err) {
--		dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err);
--		goto failed;
--	}
--
--	err = amdgpu_bo_reserve(*bo, false);
--	if (err) {
--		dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err);
--		goto failed_reserve;
--	}
--
--	err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
--				&fw_mc_addr);
--	if (err) {
--		dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err);
--		goto failed_pin;
--	}
--
--	err = amdgpu_bo_kmap(*bo, &fw_buf_ptr);
--	if (err) {
--		dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err);
--		goto failed_kmap;
-+	if (!adev->in_gpu_reset) {
-+		err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
-+					amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
-+					&adev->firmware.fw_buf,
-+					&adev->firmware.fw_buf_mc,
-+					&adev->firmware.fw_buf_ptr);
-+		if (err) {
-+			dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
-+			goto failed;
-+		}
- 	}
- 
--	amdgpu_bo_unreserve(*bo);
--
--	memset(fw_buf_ptr, 0, adev->firmware.fw_size);
-+	memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
- 
- 	/*
- 	 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
-@@ -425,14 +400,14 @@ int amdgpu_ucode_init_bo(struct amdgpu_d
- 		ucode = &adev->firmware.ucode[i];
- 		if (ucode->fw) {
- 			header = (const struct common_firmware_header *)ucode->fw->data;
--			amdgpu_ucode_init_single_fw(adev, ucode, fw_mc_addr + fw_offset,
--						    (void *)((uint8_t *)fw_buf_ptr + fw_offset));
-+			amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
-+						    adev->firmware.fw_buf_ptr + fw_offset);
- 			if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
- 			    adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
- 				const struct gfx_firmware_header_v1_0 *cp_hdr;
- 				cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
--				amdgpu_ucode_patch_jt(ucode, fw_mc_addr + fw_offset,
--						    fw_buf_ptr + fw_offset);
-+				amdgpu_ucode_patch_jt(ucode,  adev->firmware.fw_buf_mc + fw_offset,
-+						    adev->firmware.fw_buf_ptr + fw_offset);
- 				fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
- 			}
- 			fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
-@@ -440,12 +415,6 @@ int amdgpu_ucode_init_bo(struct amdgpu_d
- 	}
- 	return 0;
- 
--failed_kmap:
--	amdgpu_bo_unpin(*bo);
--failed_pin:
--	amdgpu_bo_unreserve(*bo);
--failed_reserve:
--	amdgpu_bo_unref(bo);
- failed:
- 	if (err)
- 		adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
-@@ -468,8 +437,10 @@ int amdgpu_ucode_fini_bo(struct amdgpu_d
- 			ucode->kaddr = NULL;
- 		}
- 	}
--	amdgpu_bo_unref(&adev->firmware.fw_buf);
--	adev->firmware.fw_buf = NULL;
-+
-+	amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
-+				&adev->firmware.fw_buf_mc,
-+				&adev->firmware.fw_buf_ptr);
- 
- 	return 0;
- }
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c	2017-12-14 06:39:58.382903544 +0100
-@@ -232,7 +232,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_dev
- 	ring = &adev->uvd.ring;
- 	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
- 	r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity,
--				  rq, amdgpu_sched_jobs);
-+				  rq, amdgpu_sched_jobs, NULL);
- 	if (r != 0) {
- 		DRM_ERROR("Failed setting up UVD run queue.\n");
- 		return r;
-@@ -269,6 +269,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_dev
- 
- int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
- {
-+	int i;
- 	kfree(adev->uvd.saved_bo);
- 
- 	amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
-@@ -279,6 +280,9 @@ int amdgpu_uvd_sw_fini(struct amdgpu_dev
- 
- 	amdgpu_ring_fini(&adev->uvd.ring);
- 
-+	for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
-+		amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
-+
- 	release_firmware(adev->uvd.fw);
- 
- 	return 0;
-@@ -410,10 +414,10 @@ static int amdgpu_uvd_cs_pass1(struct am
- 	uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
- 	int r = 0;
- 
--	mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
--	if (mapping == NULL) {
-+	r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
-+	if (r) {
- 		DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
--		return -EINVAL;
-+		return r;
- 	}
- 
- 	if (!ctx->parser->adev->uvd.address_64_bit) {
-@@ -737,10 +741,10 @@ static int amdgpu_uvd_cs_pass2(struct am
- 	uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
- 	int r;
- 
--	mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
--	if (mapping == NULL) {
-+	r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
-+	if (r) {
- 		DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
--		return -EINVAL;
-+		return r;
- 	}
- 
- 	start = amdgpu_bo_gpu_offset(bo);
-@@ -917,10 +921,6 @@ int amdgpu_uvd_ring_parse_cs(struct amdg
- 		return -EINVAL;
- 	}
- 
--	r = amdgpu_cs_sysvm_access_required(parser);
--	if (r)
--		return r;
--
- 	ctx.parser = parser;
- 	ctx.buf_sizes = buf_sizes;
- 	ctx.ib_idx = ib_idx;
-@@ -1218,7 +1218,7 @@ int amdgpu_uvd_ring_test_ib(struct amdgp
- 	} else if (r < 0) {
- 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
- 	} else {
--		DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);
-+		DRM_DEBUG("ib test on ring %d succeeded\n",  ring->idx);
- 		r = 0;
- 	}
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h	2017-12-14 06:39:58.382903544 +0100
-@@ -31,6 +31,10 @@
- #define AMDGPU_UVD_SESSION_SIZE		(50*1024)
- #define AMDGPU_UVD_FIRMWARE_OFFSET	256
- 
-+#define AMDGPU_UVD_FIRMWARE_SIZE(adev)    \
-+	(AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \
-+			       8) - AMDGPU_UVD_FIRMWARE_OFFSET)
-+
- struct amdgpu_uvd {
- 	struct amdgpu_bo	*vcpu_bo;
- 	void			*cpu_addr;
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c	2017-12-14 06:39:58.382903544 +0100
-@@ -176,7 +176,7 @@ int amdgpu_vce_sw_init(struct amdgpu_dev
- 	ring = &adev->vce.ring[0];
- 	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
- 	r = amd_sched_entity_init(&ring->sched, &adev->vce.entity,
--				  rq, amdgpu_sched_jobs);
-+				  rq, amdgpu_sched_jobs, NULL);
- 	if (r != 0) {
- 		DRM_ERROR("Failed setting up VCE run queue.\n");
- 		return r;
-@@ -544,6 +544,54 @@ err:
- }
- 
- /**
-+ * amdgpu_vce_cs_validate_bo - make sure not to cross 4GB boundary
-+ *
-+ * @p: parser context
-+ * @lo: address of lower dword
-+ * @hi: address of higher dword
-+ * @size: minimum size
-+ * @index: bs/fb index
-+ *
-+ * Make sure that no BO cross a 4GB boundary.
-+ */
-+static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx,
-+				  int lo, int hi, unsigned size, int32_t index)
-+{
-+	int64_t offset = ((uint64_t)size) * ((int64_t)index);
-+	struct amdgpu_bo_va_mapping *mapping;
-+	unsigned i, fpfn, lpfn;
-+	struct amdgpu_bo *bo;
-+	uint64_t addr;
-+	int r;
-+
-+	addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
-+	       ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
-+	if (index >= 0) {
-+		addr += offset;
-+		fpfn = PAGE_ALIGN(offset) >> PAGE_SHIFT;
-+		lpfn = 0x100000000ULL >> PAGE_SHIFT;
-+	} else {
-+		fpfn = 0;
-+		lpfn = (0x100000000ULL - PAGE_ALIGN(offset)) >> PAGE_SHIFT;
-+	}
-+
-+	r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
-+	if (r) {
-+		DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
-+			  addr, lo, hi, size, index);
-+		return r;
-+	}
-+
-+	for (i = 0; i < bo->placement.num_placement; ++i) {
-+		bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
-+		bo->placements[i].lpfn = bo->placements[i].fpfn ?
-+			min(bo->placements[i].fpfn, lpfn) : lpfn;
-+	}
-+	return ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
-+}
-+
-+
-+/**
-  * amdgpu_vce_cs_reloc - command submission relocation
-  *
-  * @p: parser context
-@@ -559,6 +607,7 @@ static int amdgpu_vce_cs_reloc(struct am
- 	struct amdgpu_bo_va_mapping *mapping;
- 	struct amdgpu_bo *bo;
- 	uint64_t addr;
-+	int r;
- 
- 	if (index == 0xffffffff)
- 		index = 0;
-@@ -567,11 +616,11 @@ static int amdgpu_vce_cs_reloc(struct am
- 	       ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
- 	addr += ((uint64_t)size) * ((uint64_t)index);
- 
--	mapping = amdgpu_cs_find_mapping(p, addr, &bo);
--	if (mapping == NULL) {
-+	r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
-+	if (r) {
- 		DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
- 			  addr, lo, hi, size, index);
--		return -EINVAL;
-+		return r;
- 	}
- 
- 	if ((addr + (uint64_t)size) >
-@@ -647,16 +696,13 @@ int amdgpu_vce_ring_parse_cs(struct amdg
- 	uint32_t allocated = 0;
- 	uint32_t tmp, handle = 0;
- 	uint32_t *size = &tmp;
--	int i, r = 0, idx = 0;
-+	unsigned idx;
-+	int i, r = 0;
- 
- 	p->job->vm = NULL;
- 	ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
- 
--	r = amdgpu_cs_sysvm_access_required(p);
--	if (r)
--		return r;
--
--	while (idx < ib->length_dw) {
-+	for (idx = 0; idx < ib->length_dw;) {
- 		uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
- 		uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
- 
-@@ -667,6 +713,54 @@ int amdgpu_vce_ring_parse_cs(struct amdg
- 		}
- 
- 		switch (cmd) {
-+		case 0x00000002: /* task info */
-+			fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
-+			bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
-+			break;
-+
-+		case 0x03000001: /* encode */
-+			r = amdgpu_vce_validate_bo(p, ib_idx, idx + 10,
-+						   idx + 9, 0, 0);
-+			if (r)
-+				goto out;
-+
-+			r = amdgpu_vce_validate_bo(p, ib_idx, idx + 12,
-+						   idx + 11, 0, 0);
-+			if (r)
-+				goto out;
-+			break;
-+
-+		case 0x05000001: /* context buffer */
-+			r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
-+						   idx + 2, 0, 0);
-+			if (r)
-+				goto out;
-+			break;
-+
-+		case 0x05000004: /* video bitstream buffer */
-+			tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
-+			r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
-+						   tmp, bs_idx);
-+			if (r)
-+				goto out;
-+			break;
-+
-+		case 0x05000005: /* feedback buffer */
-+			r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
-+						   4096, fb_idx);
-+			if (r)
-+				goto out;
-+			break;
-+		}
-+
-+		idx += len / 4;
-+	}
-+
-+	for (idx = 0; idx < ib->length_dw;) {
-+		uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
-+		uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
-+
-+		switch (cmd) {
- 		case 0x00000001: /* session */
- 			handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
- 			session_idx = amdgpu_vce_validate_handle(p, handle,
-@@ -957,7 +1051,7 @@ int amdgpu_vce_ring_test_ring(struct amd
- 	}
- 
- 	if (i < timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n",
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
- 			 ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed\n",
-@@ -1002,7 +1096,7 @@ int amdgpu_vce_ring_test_ib(struct amdgp
- 	} else if (r < 0) {
- 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
- 	} else {
--		DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
-+		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
- 		r = 0;
- 	}
- error:
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c	2017-12-14 06:39:58.382903544 +0100
-@@ -106,7 +106,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_dev
- 	ring = &adev->vcn.ring_dec;
- 	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
- 	r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_dec,
--				  rq, amdgpu_sched_jobs);
-+				  rq, amdgpu_sched_jobs, NULL);
- 	if (r != 0) {
- 		DRM_ERROR("Failed setting up VCN dec run queue.\n");
- 		return r;
-@@ -115,7 +115,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_dev
- 	ring = &adev->vcn.ring_enc[0];
- 	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
- 	r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_enc,
--				  rq, amdgpu_sched_jobs);
-+				  rq, amdgpu_sched_jobs, NULL);
- 	if (r != 0) {
- 		DRM_ERROR("Failed setting up VCN enc run queue.\n");
- 		return r;
-@@ -261,7 +261,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct
- 	}
- 
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n",
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
- 			 ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
-@@ -467,7 +467,7 @@ int amdgpu_vcn_dec_ring_test_ib(struct a
- 	} else if (r < 0) {
- 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
- 	} else {
--		DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);
-+		DRM_DEBUG("ib test on ring %d succeeded\n",  ring->idx);
- 		r = 0;
- 	}
- 
-@@ -500,7 +500,7 @@ int amdgpu_vcn_enc_ring_test_ring(struct
- 	}
- 
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n",
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
- 			 ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed\n",
-@@ -643,7 +643,7 @@ int amdgpu_vcn_enc_ring_test_ib(struct a
- 	} else if (r < 0) {
- 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
- 	} else {
--		DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
-+		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
- 		r = 0;
- 	}
- error:
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c	2017-12-14 06:39:58.383903545 +0100
-@@ -25,30 +25,26 @@
- #include "amdgpu_vf_error.h"
- #include "mxgpu_ai.h"
- 
--#define AMDGPU_VF_ERROR_ENTRY_SIZE    16 
--
--/* struct error_entry - amdgpu VF error information. */
--struct amdgpu_vf_error_buffer {
--	int read_count;
--	int write_count;
--	uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
--	uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
--	uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
--};
--
--struct amdgpu_vf_error_buffer admgpu_vf_errors;
--
--
--void amdgpu_vf_error_put(uint16_t sub_error_code, uint16_t error_flags, uint64_t error_data)
-+void amdgpu_vf_error_put(struct amdgpu_device *adev,
-+			 uint16_t sub_error_code,
-+			 uint16_t error_flags,
-+			 uint64_t error_data)
- {
- 	int index;
--	uint16_t error_code = AMDGIM_ERROR_CODE(AMDGIM_ERROR_CATEGORY_VF, sub_error_code);
-+	uint16_t error_code;
- 
--	index = admgpu_vf_errors.write_count % AMDGPU_VF_ERROR_ENTRY_SIZE;
--	admgpu_vf_errors.code [index] = error_code;
--	admgpu_vf_errors.flags [index] = error_flags;
--	admgpu_vf_errors.data [index] = error_data;
--	admgpu_vf_errors.write_count ++;
-+	if (!amdgpu_sriov_vf(adev))
-+		return;
-+
-+	error_code = AMDGIM_ERROR_CODE(AMDGIM_ERROR_CATEGORY_VF, sub_error_code);
-+
-+	mutex_lock(&adev->virt.vf_errors.lock);
-+	index = adev->virt.vf_errors.write_count % AMDGPU_VF_ERROR_ENTRY_SIZE;
-+	adev->virt.vf_errors.code [index] = error_code;
-+	adev->virt.vf_errors.flags [index] = error_flags;
-+	adev->virt.vf_errors.data [index] = error_data;
-+	adev->virt.vf_errors.write_count ++;
-+	mutex_unlock(&adev->virt.vf_errors.lock);
- }
- 
- 
-@@ -58,7 +54,8 @@ void amdgpu_vf_error_trans_all(struct am
- 	u32 data1, data2, data3;
- 	int index;
- 
--	if ((NULL == adev) || (!amdgpu_sriov_vf(adev)) || (!adev->virt.ops) || (!adev->virt.ops->trans_msg)) {
-+	if ((NULL == adev) || (!amdgpu_sriov_vf(adev)) ||
-+	    (!adev->virt.ops) || (!adev->virt.ops->trans_msg)) {
- 		return;
- 	}
- /*
-@@ -68,18 +65,22 @@ void amdgpu_vf_error_trans_all(struct am
- 		return;
- 	}
- */
-+
-+	mutex_lock(&adev->virt.vf_errors.lock);
- 	/* The errors are overlay of array, correct read_count as full. */
--	if (admgpu_vf_errors.write_count - admgpu_vf_errors.read_count > AMDGPU_VF_ERROR_ENTRY_SIZE) {
--		admgpu_vf_errors.read_count = admgpu_vf_errors.write_count - AMDGPU_VF_ERROR_ENTRY_SIZE;
-+	if (adev->virt.vf_errors.write_count - adev->virt.vf_errors.read_count > AMDGPU_VF_ERROR_ENTRY_SIZE) {
-+		adev->virt.vf_errors.read_count = adev->virt.vf_errors.write_count - AMDGPU_VF_ERROR_ENTRY_SIZE;
- 	}
- 
--	while (admgpu_vf_errors.read_count < admgpu_vf_errors.write_count) {
--		index =admgpu_vf_errors.read_count % AMDGPU_VF_ERROR_ENTRY_SIZE;
--		data1 = AMDGIM_ERROR_CODE_FLAGS_TO_MAILBOX (admgpu_vf_errors.code[index], admgpu_vf_errors.flags[index]);
--		data2 = admgpu_vf_errors.data[index] & 0xFFFFFFFF;
--		data3 = (admgpu_vf_errors.data[index] >> 32) & 0xFFFFFFFF;
-+	while (adev->virt.vf_errors.read_count < adev->virt.vf_errors.write_count) {
-+		index =adev->virt.vf_errors.read_count % AMDGPU_VF_ERROR_ENTRY_SIZE;
-+		data1 = AMDGIM_ERROR_CODE_FLAGS_TO_MAILBOX(adev->virt.vf_errors.code[index],
-+							   adev->virt.vf_errors.flags[index]);
-+		data2 = adev->virt.vf_errors.data[index] & 0xFFFFFFFF;
-+		data3 = (adev->virt.vf_errors.data[index] >> 32) & 0xFFFFFFFF;
- 
- 		adev->virt.ops->trans_msg(adev, IDH_LOG_VF_ERROR, data1, data2, data3);
--		admgpu_vf_errors.read_count ++;
-+		adev->virt.vf_errors.read_count ++;
- 	}
-+	mutex_unlock(&adev->virt.vf_errors.lock);
- }
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.h	2017-12-14 06:39:58.383903545 +0100
-@@ -56,7 +56,10 @@ enum AMDGIM_ERROR_CATEGORY {
- 	AMDGIM_ERROR_CATEGORY_MAX
- };
- 
--void amdgpu_vf_error_put(uint16_t sub_error_code, uint16_t error_flags, uint64_t error_data);
-+void amdgpu_vf_error_put(struct amdgpu_device *adev,
-+			 uint16_t sub_error_code,
-+			 uint16_t error_flags,
-+			 uint64_t error_data);
- void amdgpu_vf_error_trans_all (struct amdgpu_device *adev);
- 
- #endif /* __VF_ERROR_H__ */
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c	2017-12-14 06:39:58.383903545 +0100
-@@ -22,7 +22,15 @@
-  */
- 
- #include "amdgpu.h"
--#define MAX_KIQ_REG_WAIT	100000
-+#define MAX_KIQ_REG_WAIT	100000000 /* in usecs */
-+
-+bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
-+{
-+	/* By now all MMIO pages except mailbox are blocked */
-+	/* if blocking is enabled in hypervisor. Choose the */
-+	/* SCRATCH_REG0 to test. */
-+	return RREG32_NO_KIQ(0xc040) == 0xffffffff;
-+}
- 
- int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
- {
-@@ -39,6 +47,12 @@ int amdgpu_allocate_static_csa(struct am
- 	return 0;
- }
- 
-+void amdgpu_free_static_csa(struct amdgpu_device *adev) {
-+	amdgpu_bo_free_kernel(&adev->virt.csa_obj,
-+						&adev->virt.csa_vmid0_addr,
-+						NULL);
-+}
-+
- /*
-  * amdgpu_map_static_csa should be called during amdgpu_vm_init
-  * it maps virtual address "AMDGPU_VA_RESERVED_SIZE - AMDGPU_CSA_SIZE"
-@@ -107,34 +121,30 @@ void amdgpu_virt_init_setting(struct amd
- 	adev->enable_virtual_display = true;
- 	adev->cg_flags = 0;
- 	adev->pg_flags = 0;
--
--	mutex_init(&adev->virt.lock_reset);
- }
- 
- uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
- {
- 	signed long r;
--	uint32_t val;
--	struct dma_fence *f;
-+	unsigned long flags;
-+	uint32_t val, seq;
- 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
- 	struct amdgpu_ring *ring = &kiq->ring;
- 
- 	BUG_ON(!ring->funcs->emit_rreg);
- 
--	mutex_lock(&kiq->ring_mutex);
-+	spin_lock_irqsave(&kiq->ring_lock, flags);
- 	amdgpu_ring_alloc(ring, 32);
- 	amdgpu_ring_emit_rreg(ring, reg);
--	amdgpu_fence_emit(ring, &f);
-+	amdgpu_fence_emit_polling(ring, &seq);
- 	amdgpu_ring_commit(ring);
--	mutex_unlock(&kiq->ring_mutex);
-+	spin_unlock_irqrestore(&kiq->ring_lock, flags);
- 
--	r = dma_fence_wait_timeout(f, false, msecs_to_jiffies(MAX_KIQ_REG_WAIT));
--	dma_fence_put(f);
-+	r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
- 	if (r < 1) {
--		DRM_ERROR("wait for kiq fence error: %ld.\n", r);
-+		DRM_ERROR("wait for kiq fence error: %ld\n", r);
- 		return ~0;
- 	}
--
- 	val = adev->wb.wb[adev->virt.reg_val_offs];
- 
- 	return val;
-@@ -143,23 +153,23 @@ uint32_t amdgpu_virt_kiq_rreg(struct amd
- void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
- {
- 	signed long r;
--	struct dma_fence *f;
-+	unsigned long flags;
-+	uint32_t seq;
- 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
- 	struct amdgpu_ring *ring = &kiq->ring;
- 
- 	BUG_ON(!ring->funcs->emit_wreg);
- 
--	mutex_lock(&kiq->ring_mutex);
-+	spin_lock_irqsave(&kiq->ring_lock, flags);
- 	amdgpu_ring_alloc(ring, 32);
- 	amdgpu_ring_emit_wreg(ring, reg, v);
--	amdgpu_fence_emit(ring, &f);
-+	amdgpu_fence_emit_polling(ring, &seq);
- 	amdgpu_ring_commit(ring);
--	mutex_unlock(&kiq->ring_mutex);
-+	spin_unlock_irqrestore(&kiq->ring_lock, flags);
- 
--	r = dma_fence_wait_timeout(f, false, msecs_to_jiffies(MAX_KIQ_REG_WAIT));
-+	r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
- 	if (r < 1)
--		DRM_ERROR("wait for kiq fence error: %ld.\n", r);
--	dma_fence_put(f);
-+		DRM_ERROR("wait for kiq fence error: %ld\n", r);
- }
- 
- /**
-@@ -230,6 +240,22 @@ int amdgpu_virt_reset_gpu(struct amdgpu_
- }
- 
- /**
-+ * amdgpu_virt_wait_reset() - wait for reset gpu completed
-+ * @amdgpu:	amdgpu device.
-+ * Wait for GPU reset completed.
-+ * Return: Zero if reset success, otherwise will return error.
-+ */
-+int amdgpu_virt_wait_reset(struct amdgpu_device *adev)
-+{
-+	struct amdgpu_virt *virt = &adev->virt;
-+
-+	if (!virt->ops || !virt->ops->wait_reset)
-+		return -EINVAL;
-+
-+	return virt->ops->wait_reset(adev);
-+}
-+
-+/**
-  * amdgpu_virt_alloc_mm_table() - alloc memory for mm table
-  * @amdgpu:	amdgpu device.
-  * MM table is used by UVD and VCE for its initialization
-@@ -274,3 +300,79 @@ void amdgpu_virt_free_mm_table(struct am
- 			      (void *)&adev->virt.mm_table.cpu_addr);
- 	adev->virt.mm_table.gpu_addr = 0;
- }
-+
-+
-+int amdgpu_virt_fw_reserve_get_checksum(void *obj,
-+					unsigned long obj_size,
-+					unsigned int key,
-+					unsigned int chksum)
-+{
-+	unsigned int ret = key;
-+	unsigned long i = 0;
-+	unsigned char *pos;
-+
-+	pos = (char *)obj;
-+	/* calculate checksum */
-+	for (i = 0; i < obj_size; ++i)
-+		ret += *(pos + i);
-+	/* minus the chksum itself */
-+	pos = (char *)&chksum;
-+	for (i = 0; i < sizeof(chksum); ++i)
-+		ret -= *(pos + i);
-+	return ret;
-+}
-+
-+void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
-+{
-+	uint32_t pf2vf_size = 0;
-+	uint32_t checksum = 0;
-+	uint32_t checkval;
-+	char *str;
-+
-+	adev->virt.fw_reserve.p_pf2vf = NULL;
-+	adev->virt.fw_reserve.p_vf2pf = NULL;
-+
-+	if (adev->fw_vram_usage.va != NULL) {
-+		adev->virt.fw_reserve.p_pf2vf =
-+			(struct amdgim_pf2vf_info_header *)(
-+			adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET);
-+		AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size);
-+		AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum);
-+		AMDGPU_FW_VRAM_PF2VF_READ(adev, feature_flags, &adev->virt.gim_feature);
-+
-+		/* pf2vf message must be in 4K */
-+		if (pf2vf_size > 0 && pf2vf_size < 4096) {
-+			checkval = amdgpu_virt_fw_reserve_get_checksum(
-+				adev->virt.fw_reserve.p_pf2vf, pf2vf_size,
-+				adev->virt.fw_reserve.checksum_key, checksum);
-+			if (checkval == checksum) {
-+				adev->virt.fw_reserve.p_vf2pf =
-+					((void *)adev->virt.fw_reserve.p_pf2vf +
-+					pf2vf_size);
-+				memset((void *)adev->virt.fw_reserve.p_vf2pf, 0,
-+					sizeof(amdgim_vf2pf_info));
-+				AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.version,
-+					AMDGPU_FW_VRAM_VF2PF_VER);
-+				AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.size,
-+					sizeof(amdgim_vf2pf_info));
-+				AMDGPU_FW_VRAM_VF2PF_READ(adev, driver_version,
-+					&str);
-+#ifdef MODULE
-+				if (THIS_MODULE->version != NULL)
-+					strcpy(str, THIS_MODULE->version);
-+				else
-+#endif
-+					strcpy(str, "N/A");
-+				AMDGPU_FW_VRAM_VF2PF_WRITE(adev, driver_cert,
-+					0);
-+				AMDGPU_FW_VRAM_VF2PF_WRITE(adev, checksum,
-+					amdgpu_virt_fw_reserve_get_checksum(
-+					adev->virt.fw_reserve.p_vf2pf,
-+					pf2vf_size,
-+					adev->virt.fw_reserve.checksum_key, 0));
-+			}
-+		}
-+	}
-+}
-+
-+
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h	2017-12-14 06:39:58.383903545 +0100
-@@ -36,6 +36,18 @@ struct amdgpu_mm_table {
- 	uint64_t		gpu_addr;
- };
- 
-+#define AMDGPU_VF_ERROR_ENTRY_SIZE    16
-+
-+/* struct error_entry - amdgpu VF error information. */
-+struct amdgpu_vf_error_buffer {
-+	struct mutex lock;
-+	int read_count;
-+	int write_count;
-+	uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
-+	uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
-+	uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
-+};
-+
- /**
-  * struct amdgpu_virt_ops - amdgpu device virt operations
-  */
-@@ -43,9 +55,185 @@ struct amdgpu_virt_ops {
- 	int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
- 	int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
- 	int (*reset_gpu)(struct amdgpu_device *adev);
-+	int (*wait_reset)(struct amdgpu_device *adev);
- 	void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
- };
- 
-+/*
-+ * Firmware Reserve Frame buffer
-+ */
-+struct amdgpu_virt_fw_reserve {
-+	struct amdgim_pf2vf_info_header *p_pf2vf;
-+	struct amdgim_vf2pf_info_header *p_vf2pf;
-+	unsigned int checksum_key;
-+};
-+/*
-+ * Defination between PF and VF
-+ * Structures forcibly aligned to 4 to keep the same style as PF.
-+ */
-+#define AMDGIM_DATAEXCHANGE_OFFSET		(64 * 1024)
-+
-+#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
-+		(total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
-+
-+enum AMDGIM_FEATURE_FLAG {
-+	/* GIM supports feature of Error log collecting */
-+	AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
-+	/* GIM supports feature of loading uCodes */
-+	AMDGIM_FEATURE_GIM_LOAD_UCODES   = 0x2,
-+	/* VRAM LOST by GIM */
-+	AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
-+};
-+
-+struct amdgim_pf2vf_info_header {
-+	/* the total structure size in byte. */
-+	uint32_t size;
-+	/* version of this structure, written by the GIM */
-+	uint32_t version;
-+} __aligned(4);
-+struct  amdgim_pf2vf_info_v1 {
-+	/* header contains size and version */
-+	struct amdgim_pf2vf_info_header header;
-+	/* max_width * max_height */
-+	unsigned int uvd_enc_max_pixels_count;
-+	/* 16x16 pixels/sec, codec independent */
-+	unsigned int uvd_enc_max_bandwidth;
-+	/* max_width * max_height */
-+	unsigned int vce_enc_max_pixels_count;
-+	/* 16x16 pixels/sec, codec independent */
-+	unsigned int vce_enc_max_bandwidth;
-+	/* MEC FW position in kb from the start of visible frame buffer */
-+	unsigned int mecfw_kboffset;
-+	/* The features flags of the GIM driver supports. */
-+	unsigned int feature_flags;
-+	/* use private key from mailbox 2 to create chueksum */
-+	unsigned int checksum;
-+} __aligned(4);
-+
-+struct  amdgim_pf2vf_info_v2 {
-+	/* header contains size and version */
-+	struct amdgim_pf2vf_info_header header;
-+	/* use private key from mailbox 2 to create chueksum */
-+	uint32_t checksum;
-+	/* The features flags of the GIM driver supports. */
-+	uint32_t feature_flags;
-+	/* max_width * max_height */
-+	uint32_t uvd_enc_max_pixels_count;
-+	/* 16x16 pixels/sec, codec independent */
-+	uint32_t uvd_enc_max_bandwidth;
-+	/* max_width * max_height */
-+	uint32_t vce_enc_max_pixels_count;
-+	/* 16x16 pixels/sec, codec independent */
-+	uint32_t vce_enc_max_bandwidth;
-+	/* MEC FW position in kb from the start of VF visible frame buffer */
-+	uint64_t mecfw_kboffset;
-+	/* MEC FW size in KB */
-+	uint32_t mecfw_ksize;
-+	/* UVD FW position in kb from the start of VF visible frame buffer */
-+	uint64_t uvdfw_kboffset;
-+	/* UVD FW size in KB */
-+	uint32_t uvdfw_ksize;
-+	/* VCE FW position in kb from the start of VF visible frame buffer */
-+	uint64_t vcefw_kboffset;
-+	/* VCE FW size in KB */
-+	uint32_t vcefw_ksize;
-+	uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (9 + sizeof(struct amdgim_pf2vf_info_header)/sizeof(uint32_t)), 3)];
-+} __aligned(4);
-+
-+
-+struct amdgim_vf2pf_info_header {
-+	/* the total structure size in byte. */
-+	uint32_t size;
-+	/*version of this structure, written by the guest */
-+	uint32_t version;
-+} __aligned(4);
-+
-+struct amdgim_vf2pf_info_v1 {
-+	/* header contains size and version */
-+	struct amdgim_vf2pf_info_header header;
-+	/* driver version */
-+	char driver_version[64];
-+	/* driver certification, 1=WHQL, 0=None */
-+	unsigned int driver_cert;
-+	/* guest OS type and version: need a define */
-+	unsigned int os_info;
-+	/* in the unit of 1M */
-+	unsigned int fb_usage;
-+	/* guest gfx engine usage percentage */
-+	unsigned int gfx_usage;
-+	/* guest gfx engine health percentage */
-+	unsigned int gfx_health;
-+	/* guest compute engine usage percentage */
-+	unsigned int compute_usage;
-+	/* guest compute engine health percentage */
-+	unsigned int compute_health;
-+	/* guest vce engine usage percentage. 0xffff means N/A. */
-+	unsigned int vce_enc_usage;
-+	/* guest vce engine health percentage. 0xffff means N/A. */
-+	unsigned int vce_enc_health;
-+	/* guest uvd engine usage percentage. 0xffff means N/A. */
-+	unsigned int uvd_enc_usage;
-+	/* guest uvd engine usage percentage. 0xffff means N/A. */
-+	unsigned int uvd_enc_health;
-+	unsigned int checksum;
-+} __aligned(4);
-+
-+struct amdgim_vf2pf_info_v2 {
-+	/* header contains size and version */
-+	struct amdgim_vf2pf_info_header header;
-+	uint32_t checksum;
-+	/* driver version */
-+	uint8_t driver_version[64];
-+	/* driver certification, 1=WHQL, 0=None */
-+	uint32_t driver_cert;
-+	/* guest OS type and version: need a define */
-+	uint32_t os_info;
-+	/* in the unit of 1M */
-+	uint32_t fb_usage;
-+	/* guest gfx engine usage percentage */
-+	uint32_t gfx_usage;
-+	/* guest gfx engine health percentage */
-+	uint32_t gfx_health;
-+	/* guest compute engine usage percentage */
-+	uint32_t compute_usage;
-+	/* guest compute engine health percentage */
-+	uint32_t compute_health;
-+	/* guest vce engine usage percentage. 0xffff means N/A. */
-+	uint32_t vce_enc_usage;
-+	/* guest vce engine health percentage. 0xffff means N/A. */
-+	uint32_t vce_enc_health;
-+	/* guest uvd engine usage percentage. 0xffff means N/A. */
-+	uint32_t uvd_enc_usage;
-+	/* guest uvd engine usage percentage. 0xffff means N/A. */
-+	uint32_t uvd_enc_health;
-+	uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amdgim_vf2pf_info_header)/sizeof(uint32_t)), 0)];
-+} __aligned(4);
-+
-+#define AMDGPU_FW_VRAM_VF2PF_VER 2
-+typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ;
-+
-+#define AMDGPU_FW_VRAM_VF2PF_WRITE(adev, field, val) \
-+	do { \
-+		((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field = (val); \
-+	} while (0)
-+
-+#define AMDGPU_FW_VRAM_VF2PF_READ(adev, field, val) \
-+	do { \
-+		(*val) = ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field; \
-+	} while (0)
-+
-+#define AMDGPU_FW_VRAM_PF2VF_READ(adev, field, val) \
-+	do { \
-+		if (!adev->virt.fw_reserve.p_pf2vf) \
-+			*(val) = 0; \
-+		else { \
-+			if (adev->virt.fw_reserve.p_pf2vf->version == 1) \
-+				*(val) = ((struct amdgim_pf2vf_info_v1 *)adev->virt.fw_reserve.p_pf2vf)->field; \
-+			if (adev->virt.fw_reserve.p_pf2vf->version == 2) \
-+				*(val) = ((struct amdgim_pf2vf_info_v2 *)adev->virt.fw_reserve.p_pf2vf)->field; \
-+		} \
-+	} while (0)
-+
- /* GPU virtualization */
- struct amdgpu_virt {
- 	uint32_t			caps;
-@@ -53,12 +241,14 @@ struct amdgpu_virt {
- 	uint64_t			csa_vmid0_addr;
- 	bool chained_ib_support;
- 	uint32_t			reg_val_offs;
--	struct mutex                    lock_reset;
- 	struct amdgpu_irq_src		ack_irq;
- 	struct amdgpu_irq_src		rcv_irq;
- 	struct work_struct		flr_work;
- 	struct amdgpu_mm_table		mm_table;
- 	const struct amdgpu_virt_ops	*ops;
-+	struct amdgpu_vf_error_buffer   vf_errors;
-+	struct amdgpu_virt_fw_reserve	fw_reserve;
-+	uint32_t gim_feature;
- };
- 
- #define AMDGPU_CSA_SIZE    (8 * 1024)
-@@ -89,17 +279,23 @@ static inline bool is_virtual_machine(vo
- }
- 
- struct amdgpu_vm;
-+bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
- int amdgpu_allocate_static_csa(struct amdgpu_device *adev);
- int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- 			  struct amdgpu_bo_va **bo_va);
-+void amdgpu_free_static_csa(struct amdgpu_device *adev);
- void amdgpu_virt_init_setting(struct amdgpu_device *adev);
- uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
- void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
- int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
- int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
- int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
--int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job);
-+int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
- int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
- void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
-+int amdgpu_virt_fw_reserve_get_checksum(void *obj, unsigned long obj_size,
-+					unsigned int key,
-+					unsigned int chksum);
-+void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
- 
- #endif
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c	2017-12-14 06:41:25.923962985 +0100
-@@ -27,12 +27,59 @@
-  */
- #include <linux/dma-fence-array.h>
- #include <linux/interval_tree_generic.h>
-+#include <linux/idr.h>
- #include <drm/drmP.h>
- #include <drm/amdgpu_drm.h>
- #include "amdgpu.h"
- #include "amdgpu_trace.h"
- 
- /*
-+ * PASID manager
-+ *
-+ * PASIDs are global address space identifiers that can be shared
-+ * between the GPU, an IOMMU and the driver. VMs on different devices
-+ * may use the same PASID if they share the same address
-+ * space. Therefore PASIDs are allocated using a global IDA. VMs are
-+ * looked up from the PASID per amdgpu_device.
-+ */
-+static DEFINE_IDA(amdgpu_vm_pasid_ida);
-+
-+/**
-+ * amdgpu_vm_alloc_pasid - Allocate a PASID
-+ * @bits: Maximum width of the PASID in bits, must be at least 1
-+ *
-+ * Allocates a PASID of the given width while keeping smaller PASIDs
-+ * available if possible.
-+ *
-+ * Returns a positive integer on success. Returns %-EINVAL if bits==0.
-+ * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on
-+ * memory allocation failure.
-+ */
-+int amdgpu_vm_alloc_pasid(unsigned int bits)
-+{
-+	int pasid = -EINVAL;
-+
-+	for (bits = min(bits, 31U); bits > 0; bits--) {
-+		pasid = ida_simple_get(&amdgpu_vm_pasid_ida,
-+				       1U << (bits - 1), 1U << bits,
-+				       GFP_KERNEL);
-+		if (pasid != -ENOSPC)
-+			break;
-+	}
-+
-+	return pasid;
-+}
-+
-+/**
-+ * amdgpu_vm_free_pasid - Free a PASID
-+ * @pasid: PASID to free
-+ */
-+void amdgpu_vm_free_pasid(unsigned int pasid)
-+{
-+	ida_simple_remove(&amdgpu_vm_pasid_ida, pasid);
-+}
-+
-+/*
-  * GPUVM
-  * GPUVM is similar to the legacy gart on older asics, however
-  * rather than there being a single global gart table
-@@ -140,7 +187,7 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_v
- 			 struct list_head *validated,
- 			 struct amdgpu_bo_list_entry *entry)
- {
--	entry->robj = vm->root.bo;
-+	entry->robj = vm->root.base.bo;
- 	entry->priority = 0;
- 	entry->tv.bo = &entry->robj->tbo;
- 	entry->tv.shared = true;
-@@ -149,86 +196,80 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_v
- }
- 
- /**
-- * amdgpu_vm_validate_layer - validate a single page table level
-+ * amdgpu_vm_validate_pt_bos - validate the page table BOs
-  *
-- * @parent: parent page table level
-+ * @adev: amdgpu device pointer
-+ * @vm: vm providing the BOs
-  * @validate: callback to do the validation
-  * @param: parameter for the validation callback
-  *
-  * Validate the page table BOs on command submission if neccessary.
-  */
--static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent,
--				    int (*validate)(void *, struct amdgpu_bo *),
--				    void *param, bool use_cpu_for_update,
--				    struct ttm_bo_global *glob)
-+int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
-+			      int (*validate)(void *p, struct amdgpu_bo *bo),
-+			      void *param)
- {
--	unsigned i;
-+	struct ttm_bo_global *glob = adev->mman.bdev.glob;
- 	int r;
- 
--	if (use_cpu_for_update) {
--		r = amdgpu_bo_kmap(parent->bo, NULL);
--		if (r)
--			return r;
--	}
--
--	if (!parent->entries)
--		return 0;
-+	spin_lock(&vm->status_lock);
-+	while (!list_empty(&vm->evicted)) {
-+		struct amdgpu_vm_bo_base *bo_base;
-+		struct amdgpu_bo *bo;
-+
-+		bo_base = list_first_entry(&vm->evicted,
-+					   struct amdgpu_vm_bo_base,
-+					   vm_status);
-+		spin_unlock(&vm->status_lock);
- 
--	for (i = 0; i <= parent->last_entry_used; ++i) {
--		struct amdgpu_vm_pt *entry = &parent->entries[i];
-+		bo = bo_base->bo;
-+		BUG_ON(!bo);
-+		if (bo->parent) {
-+			r = validate(param, bo);
-+			if (r)
-+				return r;
- 
--		if (!entry->bo)
--			continue;
-+			spin_lock(&glob->lru_lock);
-+			ttm_bo_move_to_lru_tail(&bo->tbo);
-+			if (bo->shadow)
-+				ttm_bo_move_to_lru_tail(&bo->shadow->tbo);
-+			spin_unlock(&glob->lru_lock);
-+		}
- 
--		r = validate(param, entry->bo);
--		if (r)
--			return r;
-+		if (bo->tbo.type == ttm_bo_type_kernel &&
-+		    vm->use_cpu_for_update) {
-+			r = amdgpu_bo_kmap(bo, NULL);
-+			if (r)
-+				return r;
-+		}
- 
--		spin_lock(&glob->lru_lock);
--		ttm_bo_move_to_lru_tail(&entry->bo->tbo);
--		if (entry->bo->shadow)
--			ttm_bo_move_to_lru_tail(&entry->bo->shadow->tbo);
--		spin_unlock(&glob->lru_lock);
--
--		/*
--		 * Recurse into the sub directory. This is harmless because we
--		 * have only a maximum of 5 layers.
--		 */
--		r = amdgpu_vm_validate_level(entry, validate, param,
--					     use_cpu_for_update, glob);
--		if (r)
--			return r;
-+		spin_lock(&vm->status_lock);
-+		if (bo->tbo.type != ttm_bo_type_kernel)
-+			list_move(&bo_base->vm_status, &vm->moved);
-+		else
-+			list_move(&bo_base->vm_status, &vm->relocated);
- 	}
-+	spin_unlock(&vm->status_lock);
- 
--	return r;
-+	return 0;
- }
- 
- /**
-- * amdgpu_vm_validate_pt_bos - validate the page table BOs
-+ * amdgpu_vm_ready - check VM is ready for updates
-  *
-- * @adev: amdgpu device pointer
-- * @vm: vm providing the BOs
-- * @validate: callback to do the validation
-- * @param: parameter for the validation callback
-+ * @vm: VM to check
-  *
-- * Validate the page table BOs on command submission if neccessary.
-+ * Check if all VM PDs/PTs are ready for updates
-  */
--int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
--			      int (*validate)(void *p, struct amdgpu_bo *bo),
--			      void *param)
-+bool amdgpu_vm_ready(struct amdgpu_vm *vm)
- {
--	uint64_t num_evictions;
-+	bool ready;
- 
--	/* We only need to validate the page tables
--	 * if they aren't already valid.
--	 */
--	num_evictions = atomic64_read(&adev->num_evictions);
--	if (num_evictions == vm->last_eviction_counter)
--		return 0;
-+	spin_lock(&vm->status_lock);
-+	ready = list_empty(&vm->evicted);
-+	spin_unlock(&vm->status_lock);
- 
--	return amdgpu_vm_validate_level(&vm->root, validate, param,
--					vm->use_cpu_for_update,
--					adev->mman.bdev.glob);
-+	return ready;
- }
- 
- /**
-@@ -287,18 +328,19 @@ static int amdgpu_vm_alloc_levels(struct
- 				AMDGPU_GEM_CREATE_SHADOW);
- 
- 	if (vm->pte_support_ats) {
--		init_value = AMDGPU_PTE_SYSTEM;
-+		init_value = AMDGPU_PTE_DEFAULT_ATC;
- 		if (level != adev->vm_manager.num_level - 1)
- 			init_value |= AMDGPU_PDE_PTE;
-+
- 	}
- 
- 	/* walk over the address space and allocate the page tables */
- 	for (pt_idx = from; pt_idx <= to; ++pt_idx) {
--		struct reservation_object *resv = vm->root.bo->tbo.resv;
-+		struct reservation_object *resv = vm->root.base.bo->tbo.resv;
- 		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
- 		struct amdgpu_bo *pt;
- 
--		if (!entry->bo) {
-+		if (!entry->base.bo) {
- 			r = amdgpu_bo_create(adev,
- 					     amdgpu_vm_bo_size(adev, level),
- 					     AMDGPU_GPU_PAGE_SIZE, true,
-@@ -319,9 +361,14 @@ static int amdgpu_vm_alloc_levels(struct
- 			/* Keep a reference to the root directory to avoid
- 			* freeing them up in the wrong order.
- 			*/
--			pt->parent = amdgpu_bo_ref(vm->root.bo);
-+			pt->parent = amdgpu_bo_ref(parent->base.bo);
- 
--			entry->bo = pt;
-+			entry->base.vm = vm;
-+			entry->base.bo = pt;
-+			list_add_tail(&entry->base.bo_list, &pt->va);
-+			spin_lock(&vm->status_lock);
-+			list_add(&entry->base.vm_status, &vm->relocated);
-+			spin_unlock(&vm->status_lock);
- 			entry->addr = 0;
- 		}
- 
-@@ -988,7 +1035,7 @@ static int amdgpu_vm_wait_pd(struct amdg
- 	int r;
- 
- 	amdgpu_sync_create(&sync);
--	amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.resv, owner);
-+	amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false);
- 	r = amdgpu_sync_wait(&sync, true);
- 	amdgpu_sync_free(&sync);
- 
-@@ -1007,18 +1054,17 @@ static int amdgpu_vm_wait_pd(struct amdg
-  */
- static int amdgpu_vm_update_level(struct amdgpu_device *adev,
- 				  struct amdgpu_vm *vm,
--				  struct amdgpu_vm_pt *parent,
--				  unsigned level)
-+				  struct amdgpu_vm_pt *parent)
- {
- 	struct amdgpu_bo *shadow;
- 	struct amdgpu_ring *ring = NULL;
- 	uint64_t pd_addr, shadow_addr = 0;
--	uint32_t incr = amdgpu_vm_bo_size(adev, level + 1);
- 	uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0;
- 	unsigned count = 0, pt_idx, ndw = 0;
- 	struct amdgpu_job *job;
- 	struct amdgpu_pte_update_params params;
- 	struct dma_fence *fence = NULL;
-+	uint32_t incr;
- 
- 	int r;
- 
-@@ -1027,10 +1073,10 @@ static int amdgpu_vm_update_level(struct
- 
- 	memset(&params, 0, sizeof(params));
- 	params.adev = adev;
--	shadow = parent->bo->shadow;
-+	shadow = parent->base.bo->shadow;
- 
- 	if (vm->use_cpu_for_update) {
--		pd_addr = (unsigned long)amdgpu_bo_kptr(parent->bo);
-+		pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
- 		r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
- 		if (unlikely(r))
- 			return r;
-@@ -1046,7 +1092,7 @@ static int amdgpu_vm_update_level(struct
- 		/* assume the worst case */
- 		ndw += parent->last_entry_used * 6;
- 
--		pd_addr = amdgpu_bo_gpu_offset(parent->bo);
-+		pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
- 
- 		if (shadow) {
- 			shadow_addr = amdgpu_bo_gpu_offset(shadow);
-@@ -1066,12 +1112,17 @@ static int amdgpu_vm_update_level(struct
- 
- 	/* walk over the address space and update the directory */
- 	for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
--		struct amdgpu_bo *bo = parent->entries[pt_idx].bo;
-+		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
-+		struct amdgpu_bo *bo = entry->base.bo;
- 		uint64_t pde, pt;
- 
- 		if (bo == NULL)
- 			continue;
- 
-+		spin_lock(&vm->status_lock);
-+		list_del_init(&entry->base.vm_status);
-+		spin_unlock(&vm->status_lock);
-+
- 		pt = amdgpu_bo_gpu_offset(bo);
- 		pt = amdgpu_gart_get_vm_pde(adev, pt);
- 		/* Don't update huge pages here */
-@@ -1082,6 +1133,7 @@ static int amdgpu_vm_update_level(struct
- 		parent->entries[pt_idx].addr = pt | AMDGPU_PTE_VALID;
- 
- 		pde = pd_addr + pt_idx * 8;
-+		incr = amdgpu_bo_size(bo);
- 		if (((last_pde + 8 * count) != pde) ||
- 		    ((last_pt + incr * count) != pt) ||
- 		    (count == AMDGPU_VM_MAX_UPDATE_SIZE)) {
-@@ -1109,7 +1161,7 @@ static int amdgpu_vm_update_level(struct
- 	}
- 
- 	if (count) {
--		if (vm->root.bo->shadow)
-+		if (vm->root.base.bo->shadow)
- 			params.func(&params, last_shadow, last_pt,
- 				    count, incr, AMDGPU_PTE_VALID);
- 
-@@ -1122,12 +1174,13 @@ static int amdgpu_vm_update_level(struct
- 			amdgpu_job_free(job);
- 		} else {
- 			amdgpu_ring_pad_ib(ring, params.ib);
--			amdgpu_sync_resv(adev, &job->sync, parent->bo->tbo.resv,
--					 AMDGPU_FENCE_OWNER_VM);
-+			amdgpu_sync_resv(adev, &job->sync,
-+					 parent->base.bo->tbo.resv,
-+					 AMDGPU_FENCE_OWNER_VM, false);
- 			if (shadow)
- 				amdgpu_sync_resv(adev, &job->sync,
- 						 shadow->tbo.resv,
--						 AMDGPU_FENCE_OWNER_VM);
-+						 AMDGPU_FENCE_OWNER_VM, false);
- 
- 			WARN_ON(params.ib->length_dw > ndw);
- 			r = amdgpu_job_submit(job, ring, &vm->entity,
-@@ -1135,26 +1188,11 @@ static int amdgpu_vm_update_level(struct
- 			if (r)
- 				goto error_free;
- 
--			amdgpu_bo_fence(parent->bo, fence, true);
--			dma_fence_put(vm->last_dir_update);
--			vm->last_dir_update = dma_fence_get(fence);
--			dma_fence_put(fence);
-+			amdgpu_bo_fence(parent->base.bo, fence, true);
-+			dma_fence_put(vm->last_update);
-+			vm->last_update = fence;
- 		}
- 	}
--	/*
--	 * Recurse into the subdirectories. This recursion is harmless because
--	 * we only have a maximum of 5 layers.
--	 */
--	for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
--		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
--
--		if (!entry->bo)
--			continue;
--
--		r = amdgpu_vm_update_level(adev, vm, entry, level + 1);
--		if (r)
--			return r;
--	}
- 
- 	return 0;
- 
-@@ -1170,7 +1208,8 @@ error_free:
-  *
-  * Mark all PD level as invalid after an error.
-  */
--static void amdgpu_vm_invalidate_level(struct amdgpu_vm_pt *parent)
-+static void amdgpu_vm_invalidate_level(struct amdgpu_vm *vm,
-+				       struct amdgpu_vm_pt *parent)
- {
- 	unsigned pt_idx;
- 
-@@ -1181,11 +1220,15 @@ static void amdgpu_vm_invalidate_level(s
- 	for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
- 		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
- 
--		if (!entry->bo)
-+		if (!entry->base.bo)
- 			continue;
- 
- 		entry->addr = ~0ULL;
--		amdgpu_vm_invalidate_level(entry);
-+		spin_lock(&vm->status_lock);
-+		if (list_empty(&entry->base.vm_status))
-+			list_add(&entry->base.vm_status, &vm->relocated);
-+		spin_unlock(&vm->status_lock);
-+		amdgpu_vm_invalidate_level(vm, entry);
- 	}
- }
- 
-@@ -1203,9 +1246,38 @@ int amdgpu_vm_update_directories(struct
- {
- 	int r = 0;
- 
--	r = amdgpu_vm_update_level(adev, vm, &vm->root, 0);
--	if (r)
--		amdgpu_vm_invalidate_level(&vm->root);
-+	spin_lock(&vm->status_lock);
-+	while (!list_empty(&vm->relocated)) {
-+		struct amdgpu_vm_bo_base *bo_base;
-+		struct amdgpu_bo *bo;
-+
-+		bo_base = list_first_entry(&vm->relocated,
-+					   struct amdgpu_vm_bo_base,
-+					   vm_status);
-+		spin_unlock(&vm->status_lock);
-+
-+		bo = bo_base->bo->parent;
-+		if (bo) {
-+			struct amdgpu_vm_bo_base *parent;
-+			struct amdgpu_vm_pt *pt;
-+
-+			parent = list_first_entry(&bo->va,
-+						  struct amdgpu_vm_bo_base,
-+						  bo_list);
-+			pt = container_of(parent, struct amdgpu_vm_pt, base);
-+
-+			r = amdgpu_vm_update_level(adev, vm, pt);
-+			if (r) {
-+				amdgpu_vm_invalidate_level(vm, &vm->root);
-+				return r;
-+			}
-+			spin_lock(&vm->status_lock);
-+		} else {
-+			spin_lock(&vm->status_lock);
-+			list_del_init(&bo_base->vm_status);
-+		}
-+	}
-+	spin_unlock(&vm->status_lock);
- 
- 	if (vm->use_cpu_for_update) {
- 		/* Flush HDP */
-@@ -1236,7 +1308,7 @@ void amdgpu_vm_get_entry(struct amdgpu_p
- 	*entry = &p->vm->root;
- 	while ((*entry)->entries) {
- 		idx = addr >> (p->adev->vm_manager.block_size * level--);
--		idx %= amdgpu_bo_size((*entry)->bo) / 8;
-+		idx %= amdgpu_bo_size((*entry)->base.bo) / 8;
- 		*parent = *entry;
- 		*entry = &(*entry)->entries[idx];
- 	}
-@@ -1272,7 +1344,7 @@ static void amdgpu_vm_handle_huge_pages(
- 	    p->src ||
- 	    !(flags & AMDGPU_PTE_VALID)) {
- 
--		dst = amdgpu_bo_gpu_offset(entry->bo);
-+		dst = amdgpu_bo_gpu_offset(entry->base.bo);
- 		dst = amdgpu_gart_get_vm_pde(p->adev, dst);
- 		flags = AMDGPU_PTE_VALID;
- 	} else {
-@@ -1298,18 +1370,18 @@ static void amdgpu_vm_handle_huge_pages(
- 		tmp = p->pages_addr;
- 		p->pages_addr = NULL;
- 
--		pd_addr = (unsigned long)amdgpu_bo_kptr(parent->bo);
-+		pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
- 		pde = pd_addr + (entry - parent->entries) * 8;
- 		amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags);
- 
- 		p->pages_addr = tmp;
- 	} else {
--		if (parent->bo->shadow) {
--			pd_addr = amdgpu_bo_gpu_offset(parent->bo->shadow);
-+		if (parent->base.bo->shadow) {
-+			pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
- 			pde = pd_addr + (entry - parent->entries) * 8;
- 			amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
- 		}
--		pd_addr = amdgpu_bo_gpu_offset(parent->bo);
-+		pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
- 		pde = pd_addr + (entry - parent->entries) * 8;
- 		amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
- 	}
-@@ -1360,7 +1432,7 @@ static int amdgpu_vm_update_ptes(struct
- 		if (entry->addr & AMDGPU_PDE_PTE)
- 			continue;
- 
--		pt = entry->bo;
-+		pt = entry->base.bo;
- 		if (use_cpu_update) {
- 			pe_start = (unsigned long)amdgpu_bo_kptr(pt);
- 		} else {
-@@ -1396,8 +1468,6 @@ static int amdgpu_vm_frag_ptes(struct am
- 				uint64_t start, uint64_t end,
- 				uint64_t dst, uint64_t flags)
- {
--	int r;
--
- 	/**
- 	 * The MC L1 TLB supports variable sized pages, based on a fragment
- 	 * field in the PTE. When this field is set to a non-zero value, page
-@@ -1416,39 +1486,38 @@ static int amdgpu_vm_frag_ptes(struct am
- 	 * Userspace can support this by aligning virtual base address and
- 	 * allocation size to the fragment size.
- 	 */
--	unsigned pages_per_frag = params->adev->vm_manager.fragment_size;
--	uint64_t frag_flags = AMDGPU_PTE_FRAG(pages_per_frag);
--	uint64_t frag_align = 1 << pages_per_frag;
--
--	uint64_t frag_start = ALIGN(start, frag_align);
--	uint64_t frag_end = end & ~(frag_align - 1);
-+	unsigned max_frag = params->adev->vm_manager.fragment_size;
-+	int r;
- 
- 	/* system pages are non continuously */
--	if (params->src || !(flags & AMDGPU_PTE_VALID) ||
--	    (frag_start >= frag_end))
-+	if (params->src || !(flags & AMDGPU_PTE_VALID))
- 		return amdgpu_vm_update_ptes(params, start, end, dst, flags);
- 
--	/* handle the 4K area at the beginning */
--	if (start != frag_start) {
--		r = amdgpu_vm_update_ptes(params, start, frag_start,
--					  dst, flags);
-+	while (start != end) {
-+		uint64_t frag_flags, frag_end;
-+		unsigned frag;
-+
-+		/* This intentionally wraps around if no bit is set */
-+		frag = min((unsigned)ffs(start) - 1,
-+			   (unsigned)fls64(end - start) - 1);
-+		if (frag >= max_frag) {
-+			frag_flags = AMDGPU_PTE_FRAG(max_frag);
-+			frag_end = end & ~((1ULL << max_frag) - 1);
-+		} else {
-+			frag_flags = AMDGPU_PTE_FRAG(frag);
-+			frag_end = start + (1 << frag);
-+		}
-+
-+		r = amdgpu_vm_update_ptes(params, start, frag_end, dst,
-+					  flags | frag_flags);
- 		if (r)
- 			return r;
--		dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE;
--	}
--
--	/* handle the area in the middle */
--	r = amdgpu_vm_update_ptes(params, frag_start, frag_end, dst,
--				  flags | frag_flags);
--	if (r)
--		return r;
- 
--	/* handle the 4K area at the end */
--	if (frag_end != end) {
--		dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE;
--		r = amdgpu_vm_update_ptes(params, frag_end, end, dst, flags);
-+		dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE;
-+		start = frag_end;
- 	}
--	return r;
-+
-+	return 0;
- }
- 
- /**
-@@ -1456,7 +1525,6 @@ static int amdgpu_vm_frag_ptes(struct am
-  *
-  * @adev: amdgpu_device pointer
-  * @exclusive: fence we need to sync to
-- * @src: address where to copy page table entries from
-  * @pages_addr: DMA addresses to use for mapping
-  * @vm: requested vm
-  * @start: start of mapped range
-@@ -1470,7 +1538,6 @@ static int amdgpu_vm_frag_ptes(struct am
-  */
- static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
- 				       struct dma_fence *exclusive,
--				       uint64_t src,
- 				       dma_addr_t *pages_addr,
- 				       struct amdgpu_vm *vm,
- 				       uint64_t start, uint64_t last,
-@@ -1488,7 +1555,6 @@ static int amdgpu_vm_bo_update_mapping(s
- 	memset(&params, 0, sizeof(params));
- 	params.adev = adev;
- 	params.vm = vm;
--	params.src = src;
- 
- 	/* sync to everything on unmapping */
- 	if (!(flags & AMDGPU_PTE_VALID))
-@@ -1517,10 +1583,12 @@ static int amdgpu_vm_bo_update_mapping(s
- 	nptes = last - start + 1;
- 
- 	/*
--	 * reserve space for one command every (1 << BLOCK_SIZE)
-+	 * reserve space for two commands every (1 << BLOCK_SIZE)
- 	 *  entries or 2k dwords (whatever is smaller)
-+         *
-+         * The second command is for the shadow pagetables.
- 	 */
--	ncmds = (nptes >> min(adev->vm_manager.block_size, 11u)) + 1;
-+	ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2;
- 
- 	/* padding, etc. */
- 	ndw = 64;
-@@ -1528,15 +1596,9 @@ static int amdgpu_vm_bo_update_mapping(s
- 	/* one PDE write for each huge page */
- 	ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 6;
- 
--	if (src) {
--		/* only copy commands needed */
--		ndw += ncmds * 7;
--
--		params.func = amdgpu_vm_do_copy_ptes;
--
--	} else if (pages_addr) {
-+	if (pages_addr) {
- 		/* copy commands needed */
--		ndw += ncmds * 7;
-+		ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw;
- 
- 		/* and also PTEs */
- 		ndw += nptes * 2;
-@@ -1545,10 +1607,11 @@ static int amdgpu_vm_bo_update_mapping(s
- 
- 	} else {
- 		/* set page commands needed */
--		ndw += ncmds * 10;
-+		ndw += ncmds * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;
- 
--		/* two extra commands for begin/end of fragment */
--		ndw += 2 * 10;
-+		/* extra commands for begin/end fragments */
-+		ndw += 2 * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw
-+				* adev->vm_manager.fragment_size;
- 
- 		params.func = amdgpu_vm_do_set_ptes;
- 	}
-@@ -1559,7 +1622,7 @@ static int amdgpu_vm_bo_update_mapping(s
- 
- 	params.ib = &job->ibs[0];
- 
--	if (!src && pages_addr) {
-+	if (pages_addr) {
- 		uint64_t *pte;
- 		unsigned i;
- 
-@@ -1580,12 +1643,12 @@ static int amdgpu_vm_bo_update_mapping(s
- 	if (r)
- 		goto error_free;
- 
--	r = amdgpu_sync_resv(adev, &job->sync, vm->root.bo->tbo.resv,
--			     owner);
-+	r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
-+			     owner, false);
- 	if (r)
- 		goto error_free;
- 
--	r = reservation_object_reserve_shared(vm->root.bo->tbo.resv);
-+	r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
- 	if (r)
- 		goto error_free;
- 
-@@ -1600,14 +1663,14 @@ static int amdgpu_vm_bo_update_mapping(s
- 	if (r)
- 		goto error_free;
- 
--	amdgpu_bo_fence(vm->root.bo, f, true);
-+	amdgpu_bo_fence(vm->root.base.bo, f, true);
- 	dma_fence_put(*fence);
- 	*fence = f;
- 	return 0;
- 
- error_free:
- 	amdgpu_job_free(job);
--	amdgpu_vm_invalidate_level(&vm->root);
-+	amdgpu_vm_invalidate_level(vm, &vm->root);
- 	return r;
- }
- 
-@@ -1636,7 +1699,8 @@ static int amdgpu_vm_bo_split_mapping(st
- 				      struct drm_mm_node *nodes,
- 				      struct dma_fence **fence)
- {
--	uint64_t pfn, src = 0, start = mapping->start;
-+	unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
-+	uint64_t pfn, start = mapping->start;
- 	int r;
- 
- 	/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
-@@ -1670,6 +1734,7 @@ static int amdgpu_vm_bo_split_mapping(st
- 	}
- 
- 	do {
-+		dma_addr_t *dma_addr = NULL;
- 		uint64_t max_entries;
- 		uint64_t addr, last;
- 
-@@ -1683,16 +1748,32 @@ static int amdgpu_vm_bo_split_mapping(st
- 		}
- 
- 		if (pages_addr) {
-+			uint64_t count;
-+
- 			max_entries = min(max_entries, 16ull * 1024ull);
--			addr = 0;
-+			for (count = 1; count < max_entries; ++count) {
-+				uint64_t idx = pfn + count;
-+
-+				if (pages_addr[idx] !=
-+				    (pages_addr[idx - 1] + PAGE_SIZE))
-+					break;
-+			}
-+
-+			if (count < min_linear_pages) {
-+				addr = pfn << PAGE_SHIFT;
-+				dma_addr = pages_addr;
-+			} else {
-+				addr = pages_addr[pfn];
-+				max_entries = count;
-+			}
-+
- 		} else if (flags & AMDGPU_PTE_VALID) {
- 			addr += adev->vm_manager.vram_base_offset;
-+			addr += pfn << PAGE_SHIFT;
- 		}
--		addr += pfn << PAGE_SHIFT;
- 
- 		last = min((uint64_t)mapping->last, start + max_entries - 1);
--		r = amdgpu_vm_bo_update_mapping(adev, exclusive,
--						src, pages_addr, vm,
-+		r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm,
- 						start, last, flags, addr,
- 						fence);
- 		if (r)
-@@ -1730,7 +1811,7 @@ int amdgpu_vm_bo_update(struct amdgpu_de
- 	dma_addr_t *pages_addr = NULL;
- 	struct ttm_mem_reg *mem;
- 	struct drm_mm_node *nodes;
--	struct dma_fence *exclusive;
-+	struct dma_fence *exclusive, **last_update;
- 	uint64_t flags;
- 	int r;
- 
-@@ -1756,38 +1837,43 @@ int amdgpu_vm_bo_update(struct amdgpu_de
- 	else
- 		flags = 0x0;
- 
--	spin_lock(&vm->status_lock);
--	if (!list_empty(&bo_va->base.vm_status))
-+	if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
-+		last_update = &vm->last_update;
-+	else
-+		last_update = &bo_va->last_pt_update;
-+
-+	if (!clear && bo_va->base.moved) {
-+		bo_va->base.moved = false;
- 		list_splice_init(&bo_va->valids, &bo_va->invalids);
--	spin_unlock(&vm->status_lock);
-+
-+	} else if (bo_va->cleared != clear) {
-+		list_splice_init(&bo_va->valids, &bo_va->invalids);
-+	}
- 
- 	list_for_each_entry(mapping, &bo_va->invalids, list) {
- 		r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
- 					       mapping, flags, nodes,
--					       &bo_va->last_pt_update);
-+					       last_update);
- 		if (r)
- 			return r;
- 	}
- 
--	if (trace_amdgpu_vm_bo_mapping_enabled()) {
--		list_for_each_entry(mapping, &bo_va->valids, list)
--			trace_amdgpu_vm_bo_mapping(mapping);
--
--		list_for_each_entry(mapping, &bo_va->invalids, list)
--			trace_amdgpu_vm_bo_mapping(mapping);
-+	if (vm->use_cpu_for_update) {
-+		/* Flush HDP */
-+		mb();
-+		amdgpu_gart_flush_gpu_tlb(adev, 0);
- 	}
- 
- 	spin_lock(&vm->status_lock);
--	list_splice_init(&bo_va->invalids, &bo_va->valids);
- 	list_del_init(&bo_va->base.vm_status);
--	if (clear)
--		list_add(&bo_va->base.vm_status, &vm->cleared);
- 	spin_unlock(&vm->status_lock);
- 
--	if (vm->use_cpu_for_update) {
--		/* Flush HDP */
--		mb();
--		amdgpu_gart_flush_gpu_tlb(adev, 0);
-+	list_splice_init(&bo_va->invalids, &bo_va->valids);
-+	bo_va->cleared = clear;
-+
-+	if (trace_amdgpu_vm_bo_mapping_enabled()) {
-+		list_for_each_entry(mapping, &bo_va->valids, list)
-+			trace_amdgpu_vm_bo_mapping(mapping);
- 	}
- 
- 	return 0;
-@@ -1895,7 +1981,7 @@ static void amdgpu_vm_free_mapping(struc
-  */
- static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
- {
--	struct reservation_object *resv = vm->root.bo->tbo.resv;
-+	struct reservation_object *resv = vm->root.base.bo->tbo.resv;
- 	struct dma_fence *excl, **shared;
- 	unsigned i, shared_count;
- 	int r;
-@@ -1951,9 +2037,9 @@ int amdgpu_vm_clear_freed(struct amdgpu_
- 		list_del(&mapping->list);
- 
- 		if (vm->pte_support_ats)
--			init_pte_value = AMDGPU_PTE_SYSTEM;
-+			init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
- 
--		r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, NULL, vm,
-+		r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
- 						mapping->start, mapping->last,
- 						init_pte_value, 0, &f);
- 		amdgpu_vm_free_mapping(adev, vm, mapping, f);
-@@ -1975,29 +2061,35 @@ int amdgpu_vm_clear_freed(struct amdgpu_
- }
- 
- /**
-- * amdgpu_vm_clear_moved - clear moved BOs in the PT
-+ * amdgpu_vm_handle_moved - handle moved BOs in the PT
-  *
-  * @adev: amdgpu_device pointer
-  * @vm: requested vm
-+ * @sync: sync object to add fences to
-  *
-- * Make sure all moved BOs are cleared in the PT.
-+ * Make sure all BOs which are moved are updated in the PTs.
-  * Returns 0 for success.
-  *
-- * PTs have to be reserved and mutex must be locked!
-+ * PTs have to be reserved!
-  */
--int amdgpu_vm_clear_moved(struct amdgpu_device *adev, struct amdgpu_vm *vm,
--			    struct amdgpu_sync *sync)
-+int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
-+			   struct amdgpu_vm *vm)
- {
--	struct amdgpu_bo_va *bo_va = NULL;
-+	bool clear;
- 	int r = 0;
- 
- 	spin_lock(&vm->status_lock);
- 	while (!list_empty(&vm->moved)) {
-+		struct amdgpu_bo_va *bo_va;
-+
- 		bo_va = list_first_entry(&vm->moved,
- 			struct amdgpu_bo_va, base.vm_status);
- 		spin_unlock(&vm->status_lock);
- 
--		r = amdgpu_vm_bo_update(adev, bo_va, true);
-+		/* Per VM BOs never need to bo cleared in the page tables */
-+		clear = bo_va->base.bo->tbo.resv != vm->root.base.bo->tbo.resv;
-+
-+		r = amdgpu_vm_bo_update(adev, bo_va, clear);
- 		if (r)
- 			return r;
- 
-@@ -2005,9 +2097,6 @@ int amdgpu_vm_clear_moved(struct amdgpu_
- 	}
- 	spin_unlock(&vm->status_lock);
- 
--	if (bo_va)
--		r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
--
- 	return r;
- }
- 
-@@ -2049,6 +2138,39 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(st
- 	return bo_va;
- }
- 
-+
-+/**
-+ * amdgpu_vm_bo_insert_mapping - insert a new mapping
-+ *
-+ * @adev: amdgpu_device pointer
-+ * @bo_va: bo_va to store the address
-+ * @mapping: the mapping to insert
-+ *
-+ * Insert a new mapping into all structures.
-+ */
-+static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
-+				    struct amdgpu_bo_va *bo_va,
-+				    struct amdgpu_bo_va_mapping *mapping)
-+{
-+	struct amdgpu_vm *vm = bo_va->base.vm;
-+	struct amdgpu_bo *bo = bo_va->base.bo;
-+
-+	mapping->bo_va = bo_va;
-+	list_add(&mapping->list, &bo_va->invalids);
-+	amdgpu_vm_it_insert(mapping, &vm->va);
-+
-+	if (mapping->flags & AMDGPU_PTE_PRT)
-+		amdgpu_vm_prt_get(adev);
-+
-+	if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
-+		spin_lock(&vm->status_lock);
-+		if (list_empty(&bo_va->base.vm_status))
-+			list_add(&bo_va->base.vm_status, &vm->moved);
-+		spin_unlock(&vm->status_lock);
-+	}
-+	trace_amdgpu_vm_bo_map(bo_va, mapping);
-+}
-+
- /**
-  * amdgpu_vm_bo_map - map bo inside a vm
-  *
-@@ -2100,17 +2222,12 @@ int amdgpu_vm_bo_map(struct amdgpu_devic
- 	if (!mapping)
- 		return -ENOMEM;
- 
--	INIT_LIST_HEAD(&mapping->list);
- 	mapping->start = saddr;
- 	mapping->last = eaddr;
- 	mapping->offset = offset;
- 	mapping->flags = flags;
- 
--	list_add(&mapping->list, &bo_va->invalids);
--	amdgpu_vm_it_insert(mapping, &vm->va);
--
--	if (flags & AMDGPU_PTE_PRT)
--		amdgpu_vm_prt_get(adev);
-+	amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
- 
- 	return 0;
- }
-@@ -2137,7 +2254,6 @@ int amdgpu_vm_bo_replace_map(struct amdg
- {
- 	struct amdgpu_bo_va_mapping *mapping;
- 	struct amdgpu_bo *bo = bo_va->base.bo;
--	struct amdgpu_vm *vm = bo_va->base.vm;
- 	uint64_t eaddr;
- 	int r;
- 
-@@ -2171,11 +2287,7 @@ int amdgpu_vm_bo_replace_map(struct amdg
- 	mapping->offset = offset;
- 	mapping->flags = flags;
- 
--	list_add(&mapping->list, &bo_va->invalids);
--	amdgpu_vm_it_insert(mapping, &vm->va);
--
--	if (flags & AMDGPU_PTE_PRT)
--		amdgpu_vm_prt_get(adev);
-+	amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
- 
- 	return 0;
- }
-@@ -2221,6 +2333,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_dev
- 
- 	list_del(&mapping->list);
- 	amdgpu_vm_it_remove(mapping, &vm->va);
-+	mapping->bo_va = NULL;
- 	trace_amdgpu_vm_bo_unmap(bo_va, mapping);
- 
- 	if (valid)
-@@ -2306,6 +2419,7 @@ int amdgpu_vm_bo_clear_mappings(struct a
- 		if (tmp->last > eaddr)
- 		    tmp->last = eaddr;
- 
-+		tmp->bo_va = NULL;
- 		list_add(&tmp->list, &vm->freed);
- 		trace_amdgpu_vm_bo_unmap(NULL, tmp);
- 	}
-@@ -2332,6 +2446,19 @@ int amdgpu_vm_bo_clear_mappings(struct a
- }
- 
- /**
-+ * amdgpu_vm_bo_lookup_mapping - find mapping by address
-+ *
-+ * @vm: the requested VM
-+ *
-+ * Find a mapping by it's address.
-+ */
-+struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
-+							 uint64_t addr)
-+{
-+	return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
-+}
-+
-+/**
-  * amdgpu_vm_bo_rmv - remove a bo to a specific vm
-  *
-  * @adev: amdgpu_device pointer
-@@ -2356,6 +2483,7 @@ void amdgpu_vm_bo_rmv(struct amdgpu_devi
- 	list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
- 		list_del(&mapping->list);
- 		amdgpu_vm_it_remove(mapping, &vm->va);
-+		mapping->bo_va = NULL;
- 		trace_amdgpu_vm_bo_unmap(bo_va, mapping);
- 		list_add(&mapping->list, &vm->freed);
- 	}
-@@ -2380,15 +2508,36 @@ void amdgpu_vm_bo_rmv(struct amdgpu_devi
-  * Mark @bo as invalid.
-  */
- void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
--			     struct amdgpu_bo *bo)
-+			     struct amdgpu_bo *bo, bool evicted)
- {
- 	struct amdgpu_vm_bo_base *bo_base;
- 
- 	list_for_each_entry(bo_base, &bo->va, bo_list) {
-+		struct amdgpu_vm *vm = bo_base->vm;
-+
-+		bo_base->moved = true;
-+		if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
-+			spin_lock(&bo_base->vm->status_lock);
-+			if (bo->tbo.type == ttm_bo_type_kernel)
-+				list_move(&bo_base->vm_status, &vm->evicted);
-+			else
-+				list_move_tail(&bo_base->vm_status,
-+					       &vm->evicted);
-+			spin_unlock(&bo_base->vm->status_lock);
-+			continue;
-+		}
-+
-+		if (bo->tbo.type == ttm_bo_type_kernel) {
-+			spin_lock(&bo_base->vm->status_lock);
-+			if (list_empty(&bo_base->vm_status))
-+				list_add(&bo_base->vm_status, &vm->relocated);
-+			spin_unlock(&bo_base->vm->status_lock);
-+			continue;
-+		}
-+
- 		spin_lock(&bo_base->vm->status_lock);
- 		if (list_empty(&bo_base->vm_status))
--			list_add(&bo_base->vm_status,
--				 &bo_base->vm->moved);
-+			list_add(&bo_base->vm_status, &vm->moved);
- 		spin_unlock(&bo_base->vm->status_lock);
- 	}
- }
-@@ -2412,7 +2561,8 @@ static uint32_t amdgpu_vm_get_block_size
-  * @adev: amdgpu_device pointer
-  * @fragment_size_default: the default fragment size if it's set auto
-  */
--void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, uint32_t fragment_size_default)
-+void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
-+				 uint32_t fragment_size_default)
- {
- 	if (amdgpu_vm_fragment_size == -1)
- 		adev->vm_manager.fragment_size = fragment_size_default;
-@@ -2426,26 +2576,27 @@ void amdgpu_vm_set_fragment_size(struct
-  * @adev: amdgpu_device pointer
-  * @vm_size: the default vm size if it's set auto
-  */
--void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, uint32_t fragment_size_default)
-+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
-+			   uint32_t fragment_size_default)
- {
- 	/* adjust vm size firstly */
--	if (amdgpu_vm_size == -1)
--		adev->vm_manager.vm_size = vm_size;
--	else
--		adev->vm_manager.vm_size = amdgpu_vm_size;
-+	if (amdgpu_vm_size != -1)
-+		vm_size = amdgpu_vm_size;
-+
-+	adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
- 
- 	/* block size depends on vm size */
- 	if (amdgpu_vm_block_size == -1)
- 		adev->vm_manager.block_size =
--			amdgpu_vm_get_block_size(adev->vm_manager.vm_size);
-+			amdgpu_vm_get_block_size(vm_size);
- 	else
- 		adev->vm_manager.block_size = amdgpu_vm_block_size;
- 
- 	amdgpu_vm_set_fragment_size(adev, fragment_size_default);
- 
--	DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
--		adev->vm_manager.vm_size, adev->vm_manager.block_size,
--		adev->vm_manager.fragment_size);
-+	DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is %u-bit\n",
-+		 vm_size, adev->vm_manager.block_size,
-+		 adev->vm_manager.fragment_size);
- }
- 
- /**
-@@ -2458,7 +2609,7 @@ void amdgpu_vm_adjust_size(struct amdgpu
-  * Init @vm fields.
-  */
- int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
--		   int vm_context)
-+		   int vm_context, unsigned int pasid)
- {
- 	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
- 		AMDGPU_VM_PTE_COUNT(adev) * 8);
-@@ -2474,8 +2625,9 @@ int amdgpu_vm_init(struct amdgpu_device
- 	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
- 		vm->reserved_vmid[i] = NULL;
- 	spin_lock_init(&vm->status_lock);
-+	INIT_LIST_HEAD(&vm->evicted);
-+	INIT_LIST_HEAD(&vm->relocated);
- 	INIT_LIST_HEAD(&vm->moved);
--	INIT_LIST_HEAD(&vm->cleared);
- 	INIT_LIST_HEAD(&vm->freed);
- 
- 	/* create scheduler entity for page table updates */
-@@ -2485,7 +2637,7 @@ int amdgpu_vm_init(struct amdgpu_device
- 	ring = adev->vm_manager.vm_pte_rings[ring_instance];
- 	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
- 	r = amd_sched_entity_init(&ring->sched, &vm->entity,
--				  rq, amdgpu_sched_jobs);
-+				  rq, amdgpu_sched_jobs, NULL);
- 	if (r)
- 		return r;
- 
-@@ -2497,7 +2649,9 @@ int amdgpu_vm_init(struct amdgpu_device
- 
- 		if (adev->asic_type == CHIP_RAVEN) {
- 			vm->pte_support_ats = true;
--			init_pde_value = AMDGPU_PTE_SYSTEM | AMDGPU_PDE_PTE;
-+			init_pde_value = AMDGPU_PTE_DEFAULT_ATC
-+					| AMDGPU_PDE_PTE;
-+
- 		}
- 	} else
- 		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
-@@ -2506,7 +2660,7 @@ int amdgpu_vm_init(struct amdgpu_device
- 			 vm->use_cpu_for_update ? "CPU" : "SDMA");
- 	WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)),
- 		  "CPU update of VM recommended only for large BAR system\n");
--	vm->last_dir_update = NULL;
-+	vm->last_update = NULL;
- 
- 	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
- 			AMDGPU_GEM_CREATE_VRAM_CLEARED;
-@@ -2519,30 +2673,47 @@ int amdgpu_vm_init(struct amdgpu_device
- 	r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true,
- 			     AMDGPU_GEM_DOMAIN_VRAM,
- 			     flags,
--			     NULL, NULL, init_pde_value, &vm->root.bo);
-+			     NULL, NULL, init_pde_value, &vm->root.base.bo);
- 	if (r)
- 		goto error_free_sched_entity;
- 
--	r = amdgpu_bo_reserve(vm->root.bo, false);
--	if (r)
--		goto error_free_root;
--
--	vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
-+	vm->root.base.vm = vm;
-+	list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va);
-+	INIT_LIST_HEAD(&vm->root.base.vm_status);
- 
- 	if (vm->use_cpu_for_update) {
--		r = amdgpu_bo_kmap(vm->root.bo, NULL);
-+		r = amdgpu_bo_reserve(vm->root.base.bo, false);
- 		if (r)
- 			goto error_free_root;
-+
-+		r = amdgpu_bo_kmap(vm->root.base.bo, NULL);
-+		amdgpu_bo_unreserve(vm->root.base.bo);
-+		if (r)
-+			goto error_free_root;
-+	}
-+
-+	if (pasid) {
-+		unsigned long flags;
-+
-+		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
-+		r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
-+			      GFP_ATOMIC);
-+		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
-+		if (r < 0)
-+			goto error_free_root;
-+
-+		vm->pasid = pasid;
- 	}
- 
--	amdgpu_bo_unreserve(vm->root.bo);
-+	INIT_KFIFO(vm->faults);
-+	vm->fault_credit = 16;
- 
- 	return 0;
- 
- error_free_root:
--	amdgpu_bo_unref(&vm->root.bo->shadow);
--	amdgpu_bo_unref(&vm->root.bo);
--	vm->root.bo = NULL;
-+	amdgpu_bo_unref(&vm->root.base.bo->shadow);
-+	amdgpu_bo_unref(&vm->root.base.bo);
-+	vm->root.base.bo = NULL;
- 
- error_free_sched_entity:
- 	amd_sched_entity_fini(&ring->sched, &vm->entity);
-@@ -2561,9 +2732,11 @@ static void amdgpu_vm_free_levels(struct
- {
- 	unsigned i;
- 
--	if (level->bo) {
--		amdgpu_bo_unref(&level->bo->shadow);
--		amdgpu_bo_unref(&level->bo);
-+	if (level->base.bo) {
-+		list_del(&level->base.bo_list);
-+		list_del(&level->base.vm_status);
-+		amdgpu_bo_unref(&level->base.bo->shadow);
-+		amdgpu_bo_unref(&level->base.bo);
- 	}
- 
- 	if (level->entries)
-@@ -2587,8 +2760,21 @@ void amdgpu_vm_fini(struct amdgpu_device
- 	struct amdgpu_bo_va_mapping *mapping, *tmp;
- 	bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt;
- 	struct amdgpu_bo *root;
-+	u64 fault;
- 	int i, r;
- 
-+	/* Clear pending page faults from IH when the VM is destroyed */
-+	while (kfifo_get(&vm->faults, &fault))
-+		amdgpu_ih_clear_fault(adev, fault);
-+
-+	if (vm->pasid) {
-+		unsigned long flags;
-+
-+		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
-+		idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
-+		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
-+	}
-+
- 	amd_sched_entity_fini(vm->entity.sched, &vm->entity);
- 
- 	if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
-@@ -2610,7 +2796,7 @@ void amdgpu_vm_fini(struct amdgpu_device
- 		amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
- 	}
- 
--	root = amdgpu_bo_ref(vm->root.bo);
-+	root = amdgpu_bo_ref(vm->root.base.bo);
- 	r = amdgpu_bo_reserve(root, true);
- 	if (r) {
- 		dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
-@@ -2619,12 +2805,42 @@ void amdgpu_vm_fini(struct amdgpu_device
- 		amdgpu_bo_unreserve(root);
- 	}
- 	amdgpu_bo_unref(&root);
--	dma_fence_put(vm->last_dir_update);
-+	dma_fence_put(vm->last_update);
- 	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
- 		amdgpu_vm_free_reserved_vmid(adev, vm, i);
- }
- 
- /**
-+ * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID
-+ *
-+ * @adev: amdgpu_device pointer
-+ * @pasid: PASID do identify the VM
-+ *
-+ * This function is expected to be called in interrupt context. Returns
-+ * true if there was fault credit, false otherwise
-+ */
-+bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
-+				  unsigned int pasid)
-+{
-+	struct amdgpu_vm *vm;
-+
-+	spin_lock(&adev->vm_manager.pasid_lock);
-+	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
-+	spin_unlock(&adev->vm_manager.pasid_lock);
-+	if (!vm)
-+		/* VM not found, can't track fault credit */
-+		return true;
-+
-+	/* No lock needed. only accessed by IRQ handler */
-+	if (!vm->fault_credit)
-+		/* Too many faults in this VM */
-+		return false;
-+
-+	vm->fault_credit--;
-+	return true;
-+}
-+
-+/**
-  * amdgpu_vm_manager_init - init the VM manager
-  *
-  * @adev: amdgpu_device pointer
-@@ -2677,6 +2893,8 @@ void amdgpu_vm_manager_init(struct amdgp
- 	adev->vm_manager.vm_update_mode = 0;
- #endif
- 
-+	idr_init(&adev->vm_manager.pasid_idr);
-+	spin_lock_init(&adev->vm_manager.pasid_lock);
- }
- 
- /**
-@@ -2690,6 +2908,9 @@ void amdgpu_vm_manager_fini(struct amdgp
- {
- 	unsigned i, j;
- 
-+	WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
-+	idr_destroy(&adev->vm_manager.pasid_idr);
-+
- 	for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
- 		struct amdgpu_vm_id_manager *id_mgr =
- 			&adev->vm_manager.id_mgr[i];
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h	2017-12-14 06:39:58.383903545 +0100
-@@ -25,6 +25,7 @@
- #define __AMDGPU_VM_H__
- 
- #include <linux/rbtree.h>
-+#include <linux/idr.h>
- 
- #include "gpu_scheduler.h"
- #include "amdgpu_sync.h"
-@@ -72,6 +73,16 @@ struct amdgpu_bo_list_entry;
- #define AMDGPU_PTE_MTYPE(a)    ((uint64_t)a << 57)
- #define AMDGPU_PTE_MTYPE_MASK	AMDGPU_PTE_MTYPE(3ULL)
- 
-+/* For Raven */
-+#define AMDGPU_MTYPE_CC 2
-+
-+#define AMDGPU_PTE_DEFAULT_ATC  (AMDGPU_PTE_SYSTEM      \
-+                                | AMDGPU_PTE_SNOOPED    \
-+                                | AMDGPU_PTE_EXECUTABLE \
-+                                | AMDGPU_PTE_READABLE   \
-+                                | AMDGPU_PTE_WRITEABLE  \
-+                                | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC))
-+
- /* How to programm VM fault handling */
- #define AMDGPU_VM_FAULT_STOP_NEVER	0
- #define AMDGPU_VM_FAULT_STOP_FIRST	1
-@@ -83,7 +94,8 @@ struct amdgpu_bo_list_entry;
- #define AMDGPU_MMHUB				1
- 
- /* hardcode that limit for now */
--#define AMDGPU_VA_RESERVED_SIZE			(8 << 20)
-+#define AMDGPU_VA_RESERVED_SIZE			(8ULL << 20)
-+
- /* max vmids dedicated for process */
- #define AMDGPU_VM_MAX_RESERVED_VMID	1
- 
-@@ -105,17 +117,24 @@ struct amdgpu_vm_bo_base {
- 
- 	/* protected by spinlock */
- 	struct list_head		vm_status;
-+
-+	/* protected by the BO being reserved */
-+	bool				moved;
- };
- 
- struct amdgpu_vm_pt {
--	struct amdgpu_bo	*bo;
--	uint64_t		addr;
-+	struct amdgpu_vm_bo_base	base;
-+	uint64_t			addr;
- 
- 	/* array of page tables, one for each directory entry */
--	struct amdgpu_vm_pt	*entries;
--	unsigned		last_entry_used;
-+	struct amdgpu_vm_pt		*entries;
-+	unsigned			last_entry_used;
- };
- 
-+#define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr))
-+#define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
-+#define AMDGPU_VM_FAULT_ADDR(fault)  ((u64)(fault) & 0xfffffffff000ULL)
-+
- struct amdgpu_vm {
- 	/* tree of virtual addresses mapped */
- 	struct rb_root_cached	va;
-@@ -123,19 +142,21 @@ struct amdgpu_vm {
- 	/* protecting invalidated */
- 	spinlock_t		status_lock;
- 
-+	/* BOs who needs a validation */
-+	struct list_head	evicted;
-+
-+	/* PT BOs which relocated and their parent need an update */
-+	struct list_head	relocated;
-+
- 	/* BOs moved, but not yet updated in the PT */
- 	struct list_head	moved;
- 
--	/* BOs cleared in the PT because of a move */
--	struct list_head	cleared;
--
- 	/* BO mappings freed, but not yet updated in the PT */
- 	struct list_head	freed;
- 
- 	/* contains the page directory */
- 	struct amdgpu_vm_pt     root;
--	struct dma_fence	*last_dir_update;
--	uint64_t		last_eviction_counter;
-+	struct dma_fence	*last_update;
- 
- 	/* protecting freed */
- 	spinlock_t		freed_lock;
-@@ -143,8 +164,9 @@ struct amdgpu_vm {
- 	/* Scheduler entity for page table updates */
- 	struct amd_sched_entity	entity;
- 
--	/* client id */
-+	/* client id and PASID (TODO: replace client_id with PASID) */
- 	u64                     client_id;
-+	unsigned int		pasid;
- 	/* dedicated to vm */
- 	struct amdgpu_vm_id	*reserved_vmid[AMDGPU_MAX_VMHUBS];
- 
-@@ -153,6 +175,12 @@ struct amdgpu_vm {
- 
- 	/* Flag to indicate ATS support from PTE for GFX9 */
- 	bool			pte_support_ats;
-+
-+	/* Up to 128 pending retry page faults */
-+	DECLARE_KFIFO(faults, u64, 128);
-+
-+	/* Limit non-retry fault storms */
-+	unsigned int		fault_credit;
- };
- 
- struct amdgpu_vm_id {
-@@ -193,7 +221,6 @@ struct amdgpu_vm_manager {
- 
- 	uint64_t				max_pfn;
- 	uint32_t				num_level;
--	uint64_t				vm_size;
- 	uint32_t				block_size;
- 	uint32_t				fragment_size;
- 	/* vram base address for page table entry  */
-@@ -215,16 +242,27 @@ struct amdgpu_vm_manager {
- 	 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
- 	 */
- 	int					vm_update_mode;
-+
-+	/* PASID to VM mapping, will be used in interrupt context to
-+	 * look up VM of a page fault
-+	 */
-+	struct idr				pasid_idr;
-+	spinlock_t				pasid_lock;
- };
- 
-+int amdgpu_vm_alloc_pasid(unsigned int bits);
-+void amdgpu_vm_free_pasid(unsigned int pasid);
- void amdgpu_vm_manager_init(struct amdgpu_device *adev);
- void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
- int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
--		   int vm_context);
-+		   int vm_context, unsigned int pasid);
- void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
-+bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
-+				  unsigned int pasid);
- void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
- 			 struct list_head *validated,
- 			 struct amdgpu_bo_list_entry *entry);
-+bool amdgpu_vm_ready(struct amdgpu_vm *vm);
- int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
- 			      int (*callback)(void *p, struct amdgpu_bo *bo),
- 			      void *param);
-@@ -243,13 +281,13 @@ int amdgpu_vm_update_directories(struct
- int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
- 			  struct amdgpu_vm *vm,
- 			  struct dma_fence **fence);
--int amdgpu_vm_clear_moved(struct amdgpu_device *adev, struct amdgpu_vm *vm,
--			  struct amdgpu_sync *sync);
-+int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
-+			   struct amdgpu_vm *vm);
- int amdgpu_vm_bo_update(struct amdgpu_device *adev,
- 			struct amdgpu_bo_va *bo_va,
- 			bool clear);
- void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
--			     struct amdgpu_bo *bo);
-+			     struct amdgpu_bo *bo, bool evicted);
- struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
- 				       struct amdgpu_bo *bo);
- struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
-@@ -269,12 +307,14 @@ int amdgpu_vm_bo_unmap(struct amdgpu_dev
- int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
- 				struct amdgpu_vm *vm,
- 				uint64_t saddr, uint64_t size);
-+struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
-+							 uint64_t addr);
- void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
- 		      struct amdgpu_bo_va *bo_va);
- void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
--				uint32_t fragment_size_default);
--void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
--				uint32_t fragment_size_default);
-+				 uint32_t fragment_size_default);
-+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
-+			   uint32_t fragment_size_default);
- int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
- bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
- 				  struct amdgpu_job *job);
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c	2017-12-14 06:39:58.384903546 +0100
-@@ -68,11 +68,6 @@ static int amdgpu_vram_mgr_fini(struct t
- 	struct amdgpu_vram_mgr *mgr = man->priv;
- 
- 	spin_lock(&mgr->lock);
--	if (!drm_mm_clean(&mgr->mm)) {
--		spin_unlock(&mgr->lock);
--		return -EBUSY;
--	}
--
- 	drm_mm_takedown(&mgr->mm);
- 	spin_unlock(&mgr->lock);
- 	kfree(mgr);
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/atom.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/atom.c	2017-12-14 06:39:58.384903546 +0100
-@@ -1343,8 +1343,11 @@ struct atom_context *amdgpu_atom_parse(s
- 		idx = 0x80;
- 
- 	str = CSTR(idx);
--	if (*str != '\0')
-+	if (*str != '\0') {
- 		pr_info("ATOM BIOS: %s\n", str);
-+		strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version));
-+	}
-+
- 
- 	return ctx;
- }
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/atom.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/atom.h	2017-12-14 06:39:58.384903546 +0100
-@@ -140,6 +140,7 @@ struct atom_context {
- 	int io_mode;
- 	uint32_t *scratch;
- 	int scratch_size_bytes;
-+	char vbios_version[20];
- };
- 
- extern int amdgpu_atom_debug;
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/ci_dpm.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/ci_dpm.c	2017-12-14 06:39:58.384903546 +0100
-@@ -307,7 +307,6 @@ static int ci_set_power_limit(struct amd
- static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
- 				       u32 target_tdp);
- static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
--static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
- static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
- 
- static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
-@@ -883,8 +882,9 @@ static int ci_power_control_set_level(st
- 	return ret;
- }
- 
--static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
-+static void ci_dpm_powergate_uvd(void *handle, bool gate)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 
- 	pi->uvd_power_gated = gate;
-@@ -901,8 +901,9 @@ static void ci_dpm_powergate_uvd(struct
- 	}
- }
- 
--static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
-+static bool ci_dpm_vblank_too_short(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
- 	u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
- 
-@@ -1210,11 +1211,12 @@ static int ci_fan_ctrl_stop_smc_fan_cont
- 	}
- }
- 
--static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
-+static int ci_dpm_get_fan_speed_percent(void *handle,
- 					u32 *speed)
- {
- 	u32 duty, duty100;
- 	u64 tmp64;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	if (adev->pm.no_fan)
- 		return -ENOENT;
-@@ -1237,12 +1239,13 @@ static int ci_dpm_get_fan_speed_percent(
- 	return 0;
- }
- 
--static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
-+static int ci_dpm_set_fan_speed_percent(void *handle,
- 					u32 speed)
- {
- 	u32 tmp;
- 	u32 duty, duty100;
- 	u64 tmp64;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 
- 	if (adev->pm.no_fan)
-@@ -1271,8 +1274,10 @@ static int ci_dpm_set_fan_speed_percent(
- 	return 0;
- }
- 
--static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
-+static void ci_dpm_set_fan_control_mode(void *handle, u32 mode)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
- 	switch (mode) {
- 	case AMD_FAN_CTRL_NONE:
- 		if (adev->pm.dpm.fan.ucode_fan_control)
-@@ -1292,8 +1297,9 @@ static void ci_dpm_set_fan_control_mode(
- 	}
- }
- 
--static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev)
-+static u32 ci_dpm_get_fan_control_mode(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 
- 	if (pi->fan_is_controlled_by_smc)
-@@ -4378,9 +4384,10 @@ static u32 ci_get_lowest_enabled_level(s
- }
- 
- 
--static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
-+static int ci_dpm_force_performance_level(void *handle,
- 					  enum amd_dpm_forced_level level)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 	u32 tmp, levels, i;
- 	int ret;
-@@ -5291,8 +5298,9 @@ static void ci_update_requested_ps(struc
- 	adev->pm.dpm.requested_ps = &pi->requested_rps;
- }
- 
--static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev)
-+static int ci_dpm_pre_set_power_state(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 	struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
- 	struct amdgpu_ps *new_ps = &requested_ps;
-@@ -5304,8 +5312,9 @@ static int ci_dpm_pre_set_power_state(st
- 	return 0;
- }
- 
--static void ci_dpm_post_set_power_state(struct amdgpu_device *adev)
-+static void ci_dpm_post_set_power_state(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 	struct amdgpu_ps *new_ps = &pi->requested_rps;
- 
-@@ -5479,8 +5488,9 @@ static void ci_dpm_disable(struct amdgpu
- 	ci_update_current_ps(adev, boot_ps);
- }
- 
--static int ci_dpm_set_power_state(struct amdgpu_device *adev)
-+static int ci_dpm_set_power_state(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 	struct amdgpu_ps *new_ps = &pi->requested_rps;
- 	struct amdgpu_ps *old_ps = &pi->current_rps;
-@@ -5551,8 +5561,10 @@ static void ci_dpm_reset_asic(struct amd
- }
- #endif
- 
--static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev)
-+static void ci_dpm_display_configuration_changed(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
- 	ci_program_display_gap(adev);
- }
- 
-@@ -6105,9 +6117,10 @@ static int ci_dpm_init(struct amdgpu_dev
- }
- 
- static void
--ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
-+ci_dpm_debugfs_print_current_performance_level(void *handle,
- 					       struct seq_file *m)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 	struct amdgpu_ps *rps = &pi->current_rps;
- 	u32 sclk = ci_get_average_sclk_freq(adev);
-@@ -6131,12 +6144,13 @@ ci_dpm_debugfs_print_current_performance
- 	seq_printf(m, "GPU load: %u %%\n", activity_percent);
- }
- 
--static void ci_dpm_print_power_state(struct amdgpu_device *adev,
--				     struct amdgpu_ps *rps)
-+static void ci_dpm_print_power_state(void *handle, void *current_ps)
- {
-+	struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
- 	struct ci_ps *ps = ci_get_ps(rps);
- 	struct ci_pl *pl;
- 	int i;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	amdgpu_dpm_print_class_info(rps->class, rps->class2);
- 	amdgpu_dpm_print_cap_info(rps->caps);
-@@ -6158,20 +6172,23 @@ static inline bool ci_are_power_levels_e
- 		  (ci_cpl1->pcie_lane == ci_cpl2->pcie_lane));
- }
- 
--static int ci_check_state_equal(struct amdgpu_device *adev,
--				struct amdgpu_ps *cps,
--				struct amdgpu_ps *rps,
-+static int ci_check_state_equal(void *handle,
-+				void *current_ps,
-+				void *request_ps,
- 				bool *equal)
- {
- 	struct ci_ps *ci_cps;
- 	struct ci_ps *ci_rps;
- 	int i;
-+	struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
-+	struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
- 		return -EINVAL;
- 
--	ci_cps = ci_get_ps(cps);
--	ci_rps = ci_get_ps(rps);
-+	ci_cps = ci_get_ps((struct amdgpu_ps *)cps);
-+	ci_rps = ci_get_ps((struct amdgpu_ps *)rps);
- 
- 	if (ci_cps == NULL) {
- 		*equal = false;
-@@ -6199,8 +6216,9 @@ static int ci_check_state_equal(struct a
- 	return 0;
- }
- 
--static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low)
-+static u32 ci_dpm_get_sclk(void *handle, bool low)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 	struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
- 
-@@ -6210,8 +6228,9 @@ static u32 ci_dpm_get_sclk(struct amdgpu
- 		return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
- }
- 
--static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low)
-+static u32 ci_dpm_get_mclk(void *handle, bool low)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 	struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
- 
-@@ -6222,10 +6241,11 @@ static u32 ci_dpm_get_mclk(struct amdgpu
- }
- 
- /* get temperature in millidegrees */
--static int ci_dpm_get_temp(struct amdgpu_device *adev)
-+static int ci_dpm_get_temp(void *handle)
- {
- 	u32 temp;
- 	int actual_temp = 0;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
- 		CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
-@@ -6261,7 +6281,6 @@ static int ci_dpm_early_init(void *handl
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	ci_dpm_set_dpm_funcs(adev);
- 	ci_dpm_set_irq_funcs(adev);
- 
- 	return 0;
-@@ -6346,7 +6365,6 @@ static int ci_dpm_sw_fini(void *handle)
- 	flush_work(&adev->pm.dpm.thermal.work);
- 
- 	mutex_lock(&adev->pm.mutex);
--	amdgpu_pm_sysfs_fini(adev);
- 	ci_dpm_fini(adev);
- 	mutex_unlock(&adev->pm.mutex);
- 
-@@ -6551,9 +6569,10 @@ static int ci_dpm_set_powergating_state(
- 	return 0;
- }
- 
--static int ci_dpm_print_clock_levels(struct amdgpu_device *adev,
-+static int ci_dpm_print_clock_levels(void *handle,
- 		enum pp_clock_type type, char *buf)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 	struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
- 	struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
-@@ -6606,9 +6625,9 @@ static int ci_dpm_print_clock_levels(str
- 
- 		for (i = 0; i < pcie_table->count; i++)
- 			size += sprintf(buf + size, "%d: %s %s\n", i,
--					(pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" :
--					(pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
--					(pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
-+					(pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x1" :
-+					(pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
-+					(pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
- 					(i == now) ? "*" : "");
- 		break;
- 	default:
-@@ -6618,9 +6637,10 @@ static int ci_dpm_print_clock_levels(str
- 	return size;
- }
- 
--static int ci_dpm_force_clock_level(struct amdgpu_device *adev,
-+static int ci_dpm_force_clock_level(void *handle,
- 		enum pp_clock_type type, uint32_t mask)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 
- 	if (adev->pm.dpm.forced_level & (AMD_DPM_FORCED_LEVEL_AUTO |
-@@ -6664,8 +6684,9 @@ static int ci_dpm_force_clock_level(stru
- 	return 0;
- }
- 
--static int ci_dpm_get_sclk_od(struct amdgpu_device *adev)
-+static int ci_dpm_get_sclk_od(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 	struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table);
- 	struct ci_single_dpm_table *golden_sclk_table =
-@@ -6680,8 +6701,9 @@ static int ci_dpm_get_sclk_od(struct amd
- 	return value;
- }
- 
--static int ci_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value)
-+static int ci_dpm_set_sclk_od(void *handle, uint32_t value)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 	struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
- 	struct ci_single_dpm_table *golden_sclk_table =
-@@ -6698,8 +6720,9 @@ static int ci_dpm_set_sclk_od(struct amd
- 	return 0;
- }
- 
--static int ci_dpm_get_mclk_od(struct amdgpu_device *adev)
-+static int ci_dpm_get_mclk_od(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 	struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table);
- 	struct ci_single_dpm_table *golden_mclk_table =
-@@ -6714,8 +6737,9 @@ static int ci_dpm_get_mclk_od(struct amd
- 	return value;
- }
- 
--static int ci_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value)
-+static int ci_dpm_set_mclk_od(void *handle, uint32_t value)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 	struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
- 	struct ci_single_dpm_table *golden_mclk_table =
-@@ -6732,9 +6756,10 @@ static int ci_dpm_set_mclk_od(struct amd
- 	return 0;
- }
- 
--static int ci_dpm_get_power_profile_state(struct amdgpu_device *adev,
-+static int ci_dpm_get_power_profile_state(void *handle,
- 		struct amd_pp_profile *query)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 
- 	if (!pi || !query)
-@@ -6851,9 +6876,10 @@ static int ci_set_power_profile_state(st
- 	return result;
- }
- 
--static int ci_dpm_set_power_profile_state(struct amdgpu_device *adev,
-+static int ci_dpm_set_power_profile_state(void *handle,
- 		struct amd_pp_profile *request)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 	int ret = -1;
- 
-@@ -6906,9 +6932,10 @@ static int ci_dpm_set_power_profile_stat
- 	return 0;
- }
- 
--static int ci_dpm_reset_power_profile_state(struct amdgpu_device *adev,
-+static int ci_dpm_reset_power_profile_state(void *handle,
- 		struct amd_pp_profile *request)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 
- 	if (!pi || !request)
-@@ -6927,9 +6954,10 @@ static int ci_dpm_reset_power_profile_st
- 		return -EINVAL;
- }
- 
--static int ci_dpm_switch_power_profile(struct amdgpu_device *adev,
-+static int ci_dpm_switch_power_profile(void *handle,
- 		enum amd_pp_profile_type type)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct ci_power_info *pi = ci_get_pi(adev);
- 	struct amd_pp_profile request = {0};
- 
-@@ -6944,11 +6972,12 @@ static int ci_dpm_switch_power_profile(s
- 	return 0;
- }
- 
--static int ci_dpm_read_sensor(struct amdgpu_device *adev, int idx,
-+static int ci_dpm_read_sensor(void *handle, int idx,
- 			      void *value, int *size)
- {
- 	u32 activity_percent = 50;
- 	int ret;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	/* size must be at least 4 bytes for all sensors */
- 	if (*size < 4)
-@@ -7003,7 +7032,7 @@ const struct amd_ip_funcs ci_dpm_ip_func
- 	.set_powergating_state = ci_dpm_set_powergating_state,
- };
- 
--static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
-+const struct amd_pm_funcs ci_dpm_funcs = {
- 	.get_temperature = &ci_dpm_get_temp,
- 	.pre_set_power_state = &ci_dpm_pre_set_power_state,
- 	.set_power_state = &ci_dpm_set_power_state,
-@@ -7035,12 +7064,6 @@ static const struct amdgpu_dpm_funcs ci_
- 	.read_sensor = ci_dpm_read_sensor,
- };
- 
--static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
--{
--	if (adev->pm.funcs == NULL)
--		adev->pm.funcs = &ci_dpm_funcs;
--}
--
- static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
- 	.set = ci_dpm_set_interrupt_state,
- 	.process = ci_dpm_process_interrupt,
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/cik.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/cik.c	2017-12-14 06:39:58.385903546 +0100
-@@ -65,6 +65,7 @@
- #include "oss/oss_2_0_d.h"
- #include "oss/oss_2_0_sh_mask.h"
- 
-+#include "amdgpu_dm.h"
- #include "amdgpu_amdkfd.h"
- #include "amdgpu_powerplay.h"
- #include "dce_virtual.h"
-@@ -756,72 +757,72 @@ static void cik_init_golden_registers(st
- 	case CHIP_BONAIRE:
- 		amdgpu_program_register_sequence(adev,
- 						 bonaire_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
-+						 ARRAY_SIZE(bonaire_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 bonaire_golden_registers,
--						 (const u32)ARRAY_SIZE(bonaire_golden_registers));
-+						 ARRAY_SIZE(bonaire_golden_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 bonaire_golden_common_registers,
--						 (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
-+						 ARRAY_SIZE(bonaire_golden_common_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 bonaire_golden_spm_registers,
--						 (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
-+						 ARRAY_SIZE(bonaire_golden_spm_registers));
- 		break;
- 	case CHIP_KABINI:
- 		amdgpu_program_register_sequence(adev,
- 						 kalindi_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
-+						 ARRAY_SIZE(kalindi_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 kalindi_golden_registers,
--						 (const u32)ARRAY_SIZE(kalindi_golden_registers));
-+						 ARRAY_SIZE(kalindi_golden_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 kalindi_golden_common_registers,
--						 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
-+						 ARRAY_SIZE(kalindi_golden_common_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 kalindi_golden_spm_registers,
--						 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
-+						 ARRAY_SIZE(kalindi_golden_spm_registers));
- 		break;
- 	case CHIP_MULLINS:
- 		amdgpu_program_register_sequence(adev,
- 						 kalindi_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
-+						 ARRAY_SIZE(kalindi_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 godavari_golden_registers,
--						 (const u32)ARRAY_SIZE(godavari_golden_registers));
-+						 ARRAY_SIZE(godavari_golden_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 kalindi_golden_common_registers,
--						 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
-+						 ARRAY_SIZE(kalindi_golden_common_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 kalindi_golden_spm_registers,
--						 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
-+						 ARRAY_SIZE(kalindi_golden_spm_registers));
- 		break;
- 	case CHIP_KAVERI:
- 		amdgpu_program_register_sequence(adev,
- 						 spectre_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
-+						 ARRAY_SIZE(spectre_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 spectre_golden_registers,
--						 (const u32)ARRAY_SIZE(spectre_golden_registers));
-+						 ARRAY_SIZE(spectre_golden_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 spectre_golden_common_registers,
--						 (const u32)ARRAY_SIZE(spectre_golden_common_registers));
-+						 ARRAY_SIZE(spectre_golden_common_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 spectre_golden_spm_registers,
--						 (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
-+						 ARRAY_SIZE(spectre_golden_spm_registers));
- 		break;
- 	case CHIP_HAWAII:
- 		amdgpu_program_register_sequence(adev,
- 						 hawaii_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
-+						 ARRAY_SIZE(hawaii_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 hawaii_golden_registers,
--						 (const u32)ARRAY_SIZE(hawaii_golden_registers));
-+						 ARRAY_SIZE(hawaii_golden_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 hawaii_golden_common_registers,
--						 (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
-+						 ARRAY_SIZE(hawaii_golden_common_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 hawaii_golden_spm_registers,
--						 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
-+						 ARRAY_SIZE(hawaii_golden_spm_registers));
- 		break;
- 	default:
- 		break;
-@@ -1900,6 +1901,10 @@ int cik_set_ip_blocks(struct amdgpu_devi
- 		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
- 		if (adev->enable_virtual_display)
- 			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
-+#if defined(CONFIG_DRM_AMD_DC)
-+		else if (amdgpu_device_has_dc_support(adev))
-+			amdgpu_ip_block_add(adev, &dm_ip_block);
-+#endif
- 		else
- 			amdgpu_ip_block_add(adev, &dce_v8_2_ip_block);
- 		amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
-@@ -1914,6 +1919,10 @@ int cik_set_ip_blocks(struct amdgpu_devi
- 		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
- 		if (adev->enable_virtual_display)
- 			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
-+#if defined(CONFIG_DRM_AMD_DC)
-+		else if (amdgpu_device_has_dc_support(adev))
-+			amdgpu_ip_block_add(adev, &dm_ip_block);
-+#endif
- 		else
- 			amdgpu_ip_block_add(adev, &dce_v8_5_ip_block);
- 		amdgpu_ip_block_add(adev, &gfx_v7_3_ip_block);
-@@ -1928,6 +1937,10 @@ int cik_set_ip_blocks(struct amdgpu_devi
- 		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
- 		if (adev->enable_virtual_display)
- 			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
-+#if defined(CONFIG_DRM_AMD_DC)
-+		else if (amdgpu_device_has_dc_support(adev))
-+			amdgpu_ip_block_add(adev, &dm_ip_block);
-+#endif
- 		else
- 			amdgpu_ip_block_add(adev, &dce_v8_1_ip_block);
- 		amdgpu_ip_block_add(adev, &gfx_v7_1_ip_block);
-@@ -1943,6 +1956,10 @@ int cik_set_ip_blocks(struct amdgpu_devi
- 		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
- 		if (adev->enable_virtual_display)
- 			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
-+#if defined(CONFIG_DRM_AMD_DC)
-+		else if (amdgpu_device_has_dc_support(adev))
-+			amdgpu_ip_block_add(adev, &dm_ip_block);
-+#endif
- 		else
- 			amdgpu_ip_block_add(adev, &dce_v8_3_ip_block);
- 		amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/cik_dpm.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/cik_dpm.h	2017-12-14 06:39:58.385903546 +0100
-@@ -26,5 +26,6 @@
- 
- extern const struct amd_ip_funcs ci_dpm_ip_funcs;
- extern const struct amd_ip_funcs kv_dpm_ip_funcs;
--
-+extern const struct amd_pm_funcs ci_dpm_funcs;
-+extern const struct amd_pm_funcs kv_dpm_funcs;
- #endif
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/cik_ih.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/cik_ih.c	2017-12-14 06:39:58.385903546 +0100
-@@ -228,6 +228,34 @@ static u32 cik_ih_get_wptr(struct amdgpu
-  * [127:96] - reserved
-  */
- 
-+/**
-+ * cik_ih_prescreen_iv - prescreen an interrupt vector
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Returns true if the interrupt vector should be further processed.
-+ */
-+static bool cik_ih_prescreen_iv(struct amdgpu_device *adev)
-+{
-+	u32 ring_index = adev->irq.ih.rptr >> 2;
-+	u16 pasid;
-+
-+	switch (le32_to_cpu(adev->irq.ih.ring[ring_index]) & 0xff) {
-+	case 146:
-+	case 147:
-+		pasid = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]) >> 16;
-+		if (!pasid || amdgpu_vm_pasid_fault_credit(adev, pasid))
-+			return true;
-+		break;
-+	default:
-+		/* Not a VM fault */
-+		return true;
-+	}
-+
-+	adev->irq.ih.rptr += 16;
-+	return false;
-+}
-+
-  /**
-  * cik_ih_decode_iv - decode an interrupt vector
-  *
-@@ -433,6 +461,7 @@ static const struct amd_ip_funcs cik_ih_
- 
- static const struct amdgpu_ih_funcs cik_ih_funcs = {
- 	.get_wptr = cik_ih_get_wptr,
-+	.prescreen_iv = cik_ih_prescreen_iv,
- 	.decode_iv = cik_ih_decode_iv,
- 	.set_rptr = cik_ih_set_rptr
- };
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/cik_sdma.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/cik_sdma.c	2017-12-14 06:39:58.385903546 +0100
-@@ -657,7 +657,7 @@ static int cik_sdma_ring_test_ring(struc
- 	}
- 
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
- 			  ring->idx, tmp);
-@@ -724,7 +724,7 @@ static int cik_sdma_ring_test_ib(struct
- 	}
- 	tmp = le32_to_cpu(adev->wb.wb[index]);
- 	if (tmp == 0xDEADBEEF) {
--		DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
-+		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
- 		r = 0;
- 	} else {
- 		DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
-@@ -1387,8 +1387,13 @@ static void cik_sdma_set_buffer_funcs(st
- }
- 
- static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
-+	.copy_pte_num_dw = 7,
- 	.copy_pte = cik_sdma_vm_copy_pte,
-+
- 	.write_pte = cik_sdma_vm_write_pte,
-+
-+	.set_max_nums_pte_pde = 0x1fffff >> 3,
-+	.set_pte_pde_num_dw = 10,
- 	.set_pte_pde = cik_sdma_vm_set_pte_pde,
- };
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/cz_ih.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/cz_ih.c	2017-12-14 06:39:58.385903546 +0100
-@@ -208,6 +208,34 @@ static u32 cz_ih_get_wptr(struct amdgpu_
- }
- 
- /**
-+ * cz_ih_prescreen_iv - prescreen an interrupt vector
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Returns true if the interrupt vector should be further processed.
-+ */
-+static bool cz_ih_prescreen_iv(struct amdgpu_device *adev)
-+{
-+	u32 ring_index = adev->irq.ih.rptr >> 2;
-+	u16 pasid;
-+
-+	switch (le32_to_cpu(adev->irq.ih.ring[ring_index]) & 0xff) {
-+	case 146:
-+	case 147:
-+		pasid = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]) >> 16;
-+		if (!pasid || amdgpu_vm_pasid_fault_credit(adev, pasid))
-+			return true;
-+		break;
-+	default:
-+		/* Not a VM fault */
-+		return true;
-+	}
-+
-+	adev->irq.ih.rptr += 16;
-+	return false;
-+}
-+
-+/**
-  * cz_ih_decode_iv - decode an interrupt vector
-  *
-  * @adev: amdgpu_device pointer
-@@ -414,6 +442,7 @@ static const struct amd_ip_funcs cz_ih_i
- 
- static const struct amdgpu_ih_funcs cz_ih_funcs = {
- 	.get_wptr = cz_ih_get_wptr,
-+	.prescreen_iv = cz_ih_prescreen_iv,
- 	.decode_iv = cz_ih_decode_iv,
- 	.set_rptr = cz_ih_set_rptr
- };
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c	2017-12-14 06:39:58.385903546 +0100
-@@ -147,18 +147,18 @@ static void dce_v10_0_init_golden_regist
- 	case CHIP_FIJI:
- 		amdgpu_program_register_sequence(adev,
- 						 fiji_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
-+						 ARRAY_SIZE(fiji_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_fiji_a10,
--						 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
-+						 ARRAY_SIZE(golden_settings_fiji_a10));
- 		break;
- 	case CHIP_TONGA:
- 		amdgpu_program_register_sequence(adev,
- 						 tonga_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
-+						 ARRAY_SIZE(tonga_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_tonga_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
-+						 ARRAY_SIZE(golden_settings_tonga_a11));
- 		break;
- 	default:
- 		break;
-@@ -2773,7 +2773,6 @@ static int dce_v10_0_early_init(void *ha
- 	adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
- 
- 	dce_v10_0_set_display_funcs(adev);
--	dce_v10_0_set_irq_funcs(adev);
- 
- 	adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
- 
-@@ -2788,6 +2787,8 @@ static int dce_v10_0_early_init(void *ha
- 		return -EINVAL;
- 	}
- 
-+	dce_v10_0_set_irq_funcs(adev);
-+
- 	return 0;
- }
- 
-@@ -3635,13 +3636,16 @@ static const struct amdgpu_irq_src_funcs
- 
- static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
- {
--	adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
-+	if (adev->mode_info.num_crtc > 0)
-+		adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
-+	else
-+		adev->crtc_irq.num_types = 0;
- 	adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
- 
--	adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
-+	adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
- 	adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
- 
--	adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
-+	adev->hpd_irq.num_types = adev->mode_info.num_hpd;
- 	adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
- }
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c	2017-12-14 06:39:58.386903547 +0100
-@@ -156,26 +156,26 @@ static void dce_v11_0_init_golden_regist
- 	case CHIP_CARRIZO:
- 		amdgpu_program_register_sequence(adev,
- 						 cz_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
-+						 ARRAY_SIZE(cz_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 cz_golden_settings_a11,
--						 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
-+						 ARRAY_SIZE(cz_golden_settings_a11));
- 		break;
- 	case CHIP_STONEY:
- 		amdgpu_program_register_sequence(adev,
- 						 stoney_golden_settings_a11,
--						 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
-+						 ARRAY_SIZE(stoney_golden_settings_a11));
- 		break;
- 	case CHIP_POLARIS11:
- 	case CHIP_POLARIS12:
- 		amdgpu_program_register_sequence(adev,
- 						 polaris11_golden_settings_a11,
--						 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
-+						 ARRAY_SIZE(polaris11_golden_settings_a11));
- 		break;
- 	case CHIP_POLARIS10:
- 		amdgpu_program_register_sequence(adev,
- 						 polaris10_golden_settings_a11,
--						 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
-+						 ARRAY_SIZE(polaris10_golden_settings_a11));
- 		break;
- 	default:
- 		break;
-@@ -2876,7 +2876,6 @@ static int dce_v11_0_early_init(void *ha
- 	adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
- 
- 	dce_v11_0_set_display_funcs(adev);
--	dce_v11_0_set_irq_funcs(adev);
- 
- 	adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
- 
-@@ -2903,6 +2902,8 @@ static int dce_v11_0_early_init(void *ha
- 		return -EINVAL;
- 	}
- 
-+	dce_v11_0_set_irq_funcs(adev);
-+
- 	return 0;
- }
- 
-@@ -3759,13 +3760,16 @@ static const struct amdgpu_irq_src_funcs
- 
- static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
- {
--	adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
-+	if (adev->mode_info.num_crtc > 0)
-+		adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
-+	else
-+		adev->crtc_irq.num_types = 0;
- 	adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
- 
--	adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
-+	adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
- 	adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
- 
--	adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
-+	adev->hpd_irq.num_types = adev->mode_info.num_hpd;
- 	adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
- }
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c	2017-12-14 06:39:58.386903547 +0100
-@@ -2639,7 +2639,6 @@ static int dce_v6_0_early_init(void *han
- 	adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg;
- 
- 	dce_v6_0_set_display_funcs(adev);
--	dce_v6_0_set_irq_funcs(adev);
- 
- 	adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
- 
-@@ -2658,6 +2657,8 @@ static int dce_v6_0_early_init(void *han
- 		return -EINVAL;
- 	}
- 
-+	dce_v6_0_set_irq_funcs(adev);
-+
- 	return 0;
- }
- 
-@@ -3441,13 +3442,16 @@ static const struct amdgpu_irq_src_funcs
- 
- static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
- {
--	adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
-+	if (adev->mode_info.num_crtc > 0)
-+		adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
-+	else
-+		adev->crtc_irq.num_types = 0;
- 	adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs;
- 
--	adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
-+	adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
- 	adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs;
- 
--	adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
-+	adev->hpd_irq.num_types = adev->mode_info.num_hpd;
- 	adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;
- }
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c	2017-12-14 06:39:58.386903547 +0100
-@@ -2664,7 +2664,6 @@ static int dce_v8_0_early_init(void *han
- 	adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
- 
- 	dce_v8_0_set_display_funcs(adev);
--	dce_v8_0_set_irq_funcs(adev);
- 
- 	adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev);
- 
-@@ -2688,6 +2687,8 @@ static int dce_v8_0_early_init(void *han
- 		return -EINVAL;
- 	}
- 
-+	dce_v8_0_set_irq_funcs(adev);
-+
- 	return 0;
- }
- 
-@@ -3525,13 +3526,16 @@ static const struct amdgpu_irq_src_funcs
- 
- static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
- {
--	adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
-+	if (adev->mode_info.num_crtc > 0)
-+		adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
-+	else
-+		adev->crtc_irq.num_types = 0;
- 	adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
- 
--	adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
-+	adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
- 	adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
- 
--	adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
-+	adev->hpd_irq.num_types = adev->mode_info.num_hpd;
- 	adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
- }
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/dce_virtual.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/dce_virtual.c	2017-12-14 06:39:58.386903547 +0100
-@@ -44,6 +44,9 @@ static void dce_virtual_set_display_func
- static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
- static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
- 					      int index);
-+static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
-+							int crtc,
-+							enum amdgpu_interrupt_state state);
- 
- /**
-  * dce_virtual_vblank_wait - vblank wait asic callback.
-@@ -288,7 +291,7 @@ dce_virtual_encoder(struct drm_connector
- 		if (connector->encoder_ids[i] == 0)
- 			break;
- 
--		encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
-+		encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
- 		if (!encoder)
- 			continue;
- 
-@@ -298,7 +301,7 @@ dce_virtual_encoder(struct drm_connector
- 
- 	/* pick the first one */
- 	if (enc_id)
--		return drm_encoder_find(connector->dev, enc_id);
-+		return drm_encoder_find(connector->dev, NULL, enc_id);
- 	return NULL;
- }
- 
-@@ -437,6 +440,8 @@ static int dce_virtual_sw_fini(void *han
- 	drm_kms_helper_poll_fini(adev->ddev);
- 
- 	drm_mode_config_cleanup(adev->ddev);
-+	/* clear crtcs pointer to avoid dce irq finish routine access freed data */
-+	memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS);
- 	adev->mode_info.mode_config_initialized = false;
- 	return 0;
- }
-@@ -489,6 +494,13 @@ static int dce_virtual_hw_init(void *han
- 
- static int dce_virtual_hw_fini(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	int i = 0;
-+
-+	for (i = 0; i<adev->mode_info.num_crtc; i++)
-+		if (adev->mode_info.crtcs[i])
-+			dce_virtual_set_crtc_vblank_interrupt_state(adev, i, AMDGPU_IRQ_STATE_DISABLE);
-+
- 	return 0;
- }
- 
-@@ -723,7 +735,7 @@ static void dce_virtual_set_crtc_vblank_
- 							int crtc,
- 							enum amdgpu_interrupt_state state)
- {
--	if (crtc >= adev->mode_info.num_crtc) {
-+	if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) {
- 		DRM_DEBUG("invalid crtc %d\n", crtc);
- 		return;
- 	}
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c	2017-12-14 06:39:58.386903547 +0100
-@@ -319,6 +319,12 @@ void gfxhub_v1_0_set_fault_enable_defaul
- 			WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
- 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
- 			EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
-+	if (!value) {
-+		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
-+				CRASH_ON_NO_RETRY_FAULT, 1);
-+		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
-+				CRASH_ON_RETRY_FAULT, 1);
-+    }
- 	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
- }
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c	2017-12-14 06:39:58.387903548 +0100
-@@ -1798,7 +1798,7 @@ static int gfx_v6_0_ring_test_ring(struc
- 		DRM_UDELAY(1);
- 	}
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
- 			  ring->idx, scratch, tmp);
-@@ -1951,7 +1951,7 @@ static int gfx_v6_0_ring_test_ib(struct
- 	}
- 	tmp = RREG32(scratch);
- 	if (tmp == 0xDEADBEEF) {
--		DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
-+		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
- 		r = 0;
- 	} else {
- 		DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
-@@ -2962,25 +2962,7 @@ static void gfx_v6_0_get_csb_buffer(stru
- 
- 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
- 	buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
--
--	switch (adev->asic_type) {
--	case CHIP_TAHITI:
--	case CHIP_PITCAIRN:
--		buffer[count++] = cpu_to_le32(0x2a00126a);
--		break;
--	case CHIP_VERDE:
--		buffer[count++] = cpu_to_le32(0x0000124a);
--		break;
--	case CHIP_OLAND:
--		buffer[count++] = cpu_to_le32(0x00000082);
--		break;
--	case CHIP_HAINAN:
--		buffer[count++] = cpu_to_le32(0x00000000);
--		break;
--	default:
--		buffer[count++] = cpu_to_le32(0x00000000);
--		break;
--	}
-+	buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
- 
- 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
- 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c	2017-12-14 06:39:58.387903548 +0100
-@@ -1819,6 +1819,22 @@ static void gfx_v7_0_setup_rb(struct amd
- 							adev->gfx.config.backend_enable_mask,
- 							num_rb_pipes);
- 	}
-+
-+	/* cache the values for userspace */
-+	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
-+		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
-+			gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
-+			adev->gfx.config.rb_config[i][j].rb_backend_disable =
-+				RREG32(mmCC_RB_BACKEND_DISABLE);
-+			adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
-+				RREG32(mmGC_USER_RB_BACKEND_DISABLE);
-+			adev->gfx.config.rb_config[i][j].raster_config =
-+				RREG32(mmPA_SC_RASTER_CONFIG);
-+			adev->gfx.config.rb_config[i][j].raster_config_1 =
-+				RREG32(mmPA_SC_RASTER_CONFIG_1);
-+		}
-+	}
-+	gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
- 	mutex_unlock(&adev->grbm_idx_mutex);
- }
- 
-@@ -2069,7 +2085,7 @@ static int gfx_v7_0_ring_test_ring(struc
- 		DRM_UDELAY(1);
- 	}
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
- 			  ring->idx, scratch, tmp);
-@@ -2349,7 +2365,7 @@ static int gfx_v7_0_ring_test_ib(struct
- 	}
- 	tmp = RREG32(scratch);
- 	if (tmp == 0xDEADBEEF) {
--		DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
-+		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
- 		r = 0;
- 	} else {
- 		DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
-@@ -2535,29 +2551,8 @@ static int gfx_v7_0_cp_gfx_start(struct
- 
- 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
- 	amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
--	switch (adev->asic_type) {
--	case CHIP_BONAIRE:
--		amdgpu_ring_write(ring, 0x16000012);
--		amdgpu_ring_write(ring, 0x00000000);
--		break;
--	case CHIP_KAVERI:
--		amdgpu_ring_write(ring, 0x00000000); /* XXX */
--		amdgpu_ring_write(ring, 0x00000000);
--		break;
--	case CHIP_KABINI:
--	case CHIP_MULLINS:
--		amdgpu_ring_write(ring, 0x00000000); /* XXX */
--		amdgpu_ring_write(ring, 0x00000000);
--		break;
--	case CHIP_HAWAII:
--		amdgpu_ring_write(ring, 0x3a00161a);
--		amdgpu_ring_write(ring, 0x0000002e);
--		break;
--	default:
--		amdgpu_ring_write(ring, 0x00000000);
--		amdgpu_ring_write(ring, 0x00000000);
--		break;
--	}
-+	amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
-+	amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
- 
- 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
- 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
-@@ -4670,6 +4665,14 @@ static int gfx_v7_0_sw_fini(void *handle
- 	gfx_v7_0_cp_compute_fini(adev);
- 	gfx_v7_0_rlc_fini(adev);
- 	gfx_v7_0_mec_fini(adev);
-+	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
-+				&adev->gfx.rlc.clear_state_gpu_addr,
-+				(void **)&adev->gfx.rlc.cs_ptr);
-+	if (adev->gfx.rlc.cp_table_size) {
-+		amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
-+				&adev->gfx.rlc.cp_table_gpu_addr,
-+				(void **)&adev->gfx.rlc.cp_table_ptr);
-+	}
- 	gfx_v7_0_free_microcode(adev);
- 
- 	return 0;
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c	2017-12-14 06:39:58.388903549 +0100
-@@ -20,6 +20,7 @@
-  * OTHER DEALINGS IN THE SOFTWARE.
-  *
-  */
-+#include <linux/kernel.h>
- #include <linux/firmware.h>
- #include <drm/drmP.h>
- #include "amdgpu.h"
-@@ -125,24 +126,39 @@ MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
- MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
- 
- MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
-+MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
- 
- MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
-+MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
- 
- MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
-+MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
-+MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
-+MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
-+MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
-+MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
- MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
- 
- static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
-@@ -665,53 +681,53 @@ static void gfx_v8_0_init_golden_registe
- 	case CHIP_TOPAZ:
- 		amdgpu_program_register_sequence(adev,
- 						 iceland_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
-+						 ARRAY_SIZE(iceland_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_iceland_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
-+						 ARRAY_SIZE(golden_settings_iceland_a11));
- 		amdgpu_program_register_sequence(adev,
- 						 iceland_golden_common_all,
--						 (const u32)ARRAY_SIZE(iceland_golden_common_all));
-+						 ARRAY_SIZE(iceland_golden_common_all));
- 		break;
- 	case CHIP_FIJI:
- 		amdgpu_program_register_sequence(adev,
- 						 fiji_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
-+						 ARRAY_SIZE(fiji_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_fiji_a10,
--						 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
-+						 ARRAY_SIZE(golden_settings_fiji_a10));
- 		amdgpu_program_register_sequence(adev,
- 						 fiji_golden_common_all,
--						 (const u32)ARRAY_SIZE(fiji_golden_common_all));
-+						 ARRAY_SIZE(fiji_golden_common_all));
- 		break;
- 
- 	case CHIP_TONGA:
- 		amdgpu_program_register_sequence(adev,
- 						 tonga_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
-+						 ARRAY_SIZE(tonga_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_tonga_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
-+						 ARRAY_SIZE(golden_settings_tonga_a11));
- 		amdgpu_program_register_sequence(adev,
- 						 tonga_golden_common_all,
--						 (const u32)ARRAY_SIZE(tonga_golden_common_all));
-+						 ARRAY_SIZE(tonga_golden_common_all));
- 		break;
- 	case CHIP_POLARIS11:
- 	case CHIP_POLARIS12:
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_polaris11_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
-+						 ARRAY_SIZE(golden_settings_polaris11_a11));
- 		amdgpu_program_register_sequence(adev,
- 						 polaris11_golden_common_all,
--						 (const u32)ARRAY_SIZE(polaris11_golden_common_all));
-+						 ARRAY_SIZE(polaris11_golden_common_all));
- 		break;
- 	case CHIP_POLARIS10:
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_polaris10_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
-+						 ARRAY_SIZE(golden_settings_polaris10_a11));
- 		amdgpu_program_register_sequence(adev,
- 						 polaris10_golden_common_all,
--						 (const u32)ARRAY_SIZE(polaris10_golden_common_all));
-+						 ARRAY_SIZE(polaris10_golden_common_all));
- 		WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
- 		if (adev->pdev->revision == 0xc7 &&
- 		    ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
-@@ -724,24 +740,24 @@ static void gfx_v8_0_init_golden_registe
- 	case CHIP_CARRIZO:
- 		amdgpu_program_register_sequence(adev,
- 						 cz_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
-+						 ARRAY_SIZE(cz_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 cz_golden_settings_a11,
--						 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
-+						 ARRAY_SIZE(cz_golden_settings_a11));
- 		amdgpu_program_register_sequence(adev,
- 						 cz_golden_common_all,
--						 (const u32)ARRAY_SIZE(cz_golden_common_all));
-+						 ARRAY_SIZE(cz_golden_common_all));
- 		break;
- 	case CHIP_STONEY:
- 		amdgpu_program_register_sequence(adev,
- 						 stoney_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
-+						 ARRAY_SIZE(stoney_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 stoney_golden_settings_a11,
--						 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
-+						 ARRAY_SIZE(stoney_golden_settings_a11));
- 		amdgpu_program_register_sequence(adev,
- 						 stoney_golden_common_all,
--						 (const u32)ARRAY_SIZE(stoney_golden_common_all));
-+						 ARRAY_SIZE(stoney_golden_common_all));
- 		break;
- 	default:
- 		break;
-@@ -788,7 +804,7 @@ static int gfx_v8_0_ring_test_ring(struc
- 		DRM_UDELAY(1);
- 	}
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n",
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
- 			 ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
-@@ -840,7 +856,7 @@ static int gfx_v8_0_ring_test_ib(struct
- 	}
- 	tmp = RREG32(scratch);
- 	if (tmp == 0xDEADBEEF) {
--		DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
-+		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
- 		r = 0;
- 	} else {
- 		DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
-@@ -918,8 +934,17 @@ static int gfx_v8_0_init_microcode(struc
- 		BUG();
- 	}
- 
--	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
--	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
-+	if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
-+		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);
-+		err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
-+		if (err == -ENOENT) {
-+			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
-+			err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
-+		}
-+	} else {
-+		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
-+		err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
-+	}
- 	if (err)
- 		goto out;
- 	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
-@@ -929,8 +954,17 @@ static int gfx_v8_0_init_microcode(struc
- 	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
- 	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
- 
--	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
--	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
-+	if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
-+		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);
-+		err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
-+		if (err == -ENOENT) {
-+			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
-+			err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
-+		}
-+	} else {
-+		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
-+		err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
-+	}
- 	if (err)
- 		goto out;
- 	err = amdgpu_ucode_validate(adev->gfx.me_fw);
-@@ -941,8 +975,17 @@ static int gfx_v8_0_init_microcode(struc
- 
- 	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
- 
--	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
--	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
-+	if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
-+		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);
-+		err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
-+		if (err == -ENOENT) {
-+			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
-+			err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
-+		}
-+	} else {
-+		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
-+		err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
-+	}
- 	if (err)
- 		goto out;
- 	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
-@@ -1012,8 +1055,17 @@ static int gfx_v8_0_init_microcode(struc
- 	for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
- 		adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
- 
--	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
--	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
-+	if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
-+		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);
-+		err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
-+		if (err == -ENOENT) {
-+			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
-+			err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
-+		}
-+	} else {
-+		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
-+		err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
-+	}
- 	if (err)
- 		goto out;
- 	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
-@@ -1025,8 +1077,17 @@ static int gfx_v8_0_init_microcode(struc
- 
- 	if ((adev->asic_type != CHIP_STONEY) &&
- 	    (adev->asic_type != CHIP_TOPAZ)) {
--		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
--		err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
-+		if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
-+			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);
-+			err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
-+			if (err == -ENOENT) {
-+				snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
-+				err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
-+			}
-+		} else {
-+			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
-+			err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
-+		}
- 		if (!err) {
- 			err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
- 			if (err)
-@@ -2056,6 +2117,15 @@ static int gfx_v8_0_sw_fini(void *handle
- 
- 	gfx_v8_0_mec_fini(adev);
- 	gfx_v8_0_rlc_fini(adev);
-+	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
-+				&adev->gfx.rlc.clear_state_gpu_addr,
-+				(void **)&adev->gfx.rlc.cs_ptr);
-+	if ((adev->asic_type == CHIP_CARRIZO) ||
-+	    (adev->asic_type == CHIP_STONEY)) {
-+		amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
-+				&adev->gfx.rlc.cp_table_gpu_addr,
-+				(void **)&adev->gfx.rlc.cp_table_ptr);
-+	}
- 	gfx_v8_0_free_microcode(adev);
- 
- 	return 0;
-@@ -3780,6 +3850,14 @@ static void gfx_v8_0_wait_for_rlc_serdes
- 					break;
- 				udelay(1);
- 			}
-+			if (k == adev->usec_timeout) {
-+				gfx_v8_0_select_se_sh(adev, 0xffffffff,
-+						      0xffffffff, 0xffffffff);
-+				mutex_unlock(&adev->grbm_idx_mutex);
-+				DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
-+					 i, j);
-+				return;
-+			}
- 		}
- 	}
- 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
-@@ -3891,10 +3969,10 @@ static int gfx_v8_0_init_save_restore_li
- 				adev->gfx.rlc.reg_list_format_size_bytes >> 2,
- 				unique_indices,
- 				&indices_count,
--				sizeof(unique_indices) / sizeof(int),
-+				ARRAY_SIZE(unique_indices),
- 				indirect_start_offsets,
- 				&offset_count,
--				sizeof(indirect_start_offsets)/sizeof(int));
-+				ARRAY_SIZE(indirect_start_offsets));
- 
- 	/* save and restore list */
- 	WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
-@@ -3916,14 +3994,14 @@ static int gfx_v8_0_init_save_restore_li
- 	/* starting offsets starts */
- 	WREG32(mmRLC_GPM_SCRATCH_ADDR,
- 		adev->gfx.rlc.starting_offsets_start);
--	for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
-+	for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
- 		WREG32(mmRLC_GPM_SCRATCH_DATA,
- 				indirect_start_offsets[i]);
- 
- 	/* unique indices */
- 	temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
- 	data = mmRLC_SRM_INDEX_CNTL_DATA_0;
--	for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
-+	for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {
- 		if (unique_indices[i] != 0) {
- 			WREG32(temp + i, unique_indices[i] & 0x3FFFF);
- 			WREG32(data + i, unique_indices[i] >> 20);
-@@ -4071,18 +4149,12 @@ static int gfx_v8_0_rlc_resume(struct am
- 	gfx_v8_0_rlc_reset(adev);
- 	gfx_v8_0_init_pg(adev);
- 
--	if (!adev->pp_enabled) {
--		if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
--			/* legacy rlc firmware loading */
--			r = gfx_v8_0_rlc_load_microcode(adev);
--			if (r)
--				return r;
--		} else {
--			r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--							AMDGPU_UCODE_ID_RLC_G);
--			if (r)
--				return -EINVAL;
--		}
-+
-+	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
-+		/* legacy rlc firmware loading */
-+		r = gfx_v8_0_rlc_load_microcode(adev);
-+		if (r)
-+			return r;
- 	}
- 
- 	gfx_v8_0_rlc_start(adev);
-@@ -4240,37 +4312,8 @@ static int gfx_v8_0_cp_gfx_start(struct
- 
- 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
- 	amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
--	switch (adev->asic_type) {
--	case CHIP_TONGA:
--	case CHIP_POLARIS10:
--		amdgpu_ring_write(ring, 0x16000012);
--		amdgpu_ring_write(ring, 0x0000002A);
--		break;
--	case CHIP_POLARIS11:
--	case CHIP_POLARIS12:
--		amdgpu_ring_write(ring, 0x16000012);
--		amdgpu_ring_write(ring, 0x00000000);
--		break;
--	case CHIP_FIJI:
--		amdgpu_ring_write(ring, 0x3a00161a);
--		amdgpu_ring_write(ring, 0x0000002e);
--		break;
--	case CHIP_CARRIZO:
--		amdgpu_ring_write(ring, 0x00000002);
--		amdgpu_ring_write(ring, 0x00000000);
--		break;
--	case CHIP_TOPAZ:
--		amdgpu_ring_write(ring, adev->gfx.config.num_rbs == 1 ?
--				0x00000000 : 0x00000002);
--		amdgpu_ring_write(ring, 0x00000000);
--		break;
--	case CHIP_STONEY:
--		amdgpu_ring_write(ring, 0x00000000);
--		amdgpu_ring_write(ring, 0x00000000);
--		break;
--	default:
--		BUG();
--	}
-+	amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
-+	amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
- 
- 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
- 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
-@@ -4577,12 +4620,10 @@ static int gfx_v8_0_mqd_init(struct amdg
- 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
- 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
- 	mqd->compute_misc_reserved = 0x00000003;
--	if (!(adev->flags & AMD_IS_APU)) {
--		mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
--					     + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
--		mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
--					     + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
--	}
-+	mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
-+						     + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
-+	mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
-+						     + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
- 	eop_base_addr = ring->eop_gpu_addr >> 8;
- 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
- 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
-@@ -4753,7 +4794,7 @@ static int gfx_v8_0_kiq_init_queue(struc
- 
- 	gfx_v8_0_kiq_setting(ring);
- 
--	if (adev->gfx.in_reset) { /* for GPU_RESET case */
-+	if (adev->in_gpu_reset) { /* for GPU_RESET case */
- 		/* reset MQD to a clean status */
- 		if (adev->gfx.mec.mqd_backup[mqd_idx])
- 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
-@@ -4790,7 +4831,7 @@ static int gfx_v8_0_kcq_init_queue(struc
- 	struct vi_mqd *mqd = ring->mqd_ptr;
- 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
- 
--	if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
-+	if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
- 		memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
- 		((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
- 		((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
-@@ -4802,13 +4843,10 @@ static int gfx_v8_0_kcq_init_queue(struc
- 
- 		if (adev->gfx.mec.mqd_backup[mqd_idx])
- 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
--	} else if (adev->gfx.in_reset) { /* for GPU_RESET case */
-+	} else if (adev->in_gpu_reset) { /* for GPU_RESET case */
- 		/* reset MQD to a clean status */
- 		if (adev->gfx.mec.mqd_backup[mqd_idx])
- 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
--		/* reset ring buffer */
--		ring->wptr = 0;
--		amdgpu_ring_clear_ring(ring);
- 	} else {
- 		amdgpu_ring_clear_ring(ring);
- 	}
-@@ -4883,6 +4921,13 @@ static int gfx_v8_0_kiq_resume(struct am
- 	/* Test KCQs */
- 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
- 		ring = &adev->gfx.compute_ring[i];
-+		if (adev->in_gpu_reset) {
-+			/* move reset ring buffer to here to workaround
-+			 * compute ring test failed
-+			 */
-+			ring->wptr = 0;
-+			amdgpu_ring_clear_ring(ring);
-+		}
- 		ring->ready = true;
- 		r = amdgpu_ring_test_ring(ring);
- 		if (r)
-@@ -4900,43 +4945,15 @@ static int gfx_v8_0_cp_resume(struct amd
- 	if (!(adev->flags & AMD_IS_APU))
- 		gfx_v8_0_enable_gui_idle_interrupt(adev, false);
- 
--	if (!adev->pp_enabled) {
--		if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
-+	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
- 			/* legacy firmware loading */
--			r = gfx_v8_0_cp_gfx_load_microcode(adev);
--			if (r)
--				return r;
--
--			r = gfx_v8_0_cp_compute_load_microcode(adev);
--			if (r)
--				return r;
--		} else {
--			r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--							AMDGPU_UCODE_ID_CP_CE);
--			if (r)
--				return -EINVAL;
--
--			r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--							AMDGPU_UCODE_ID_CP_PFP);
--			if (r)
--				return -EINVAL;
--
--			r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--							AMDGPU_UCODE_ID_CP_ME);
--			if (r)
--				return -EINVAL;
-+		r = gfx_v8_0_cp_gfx_load_microcode(adev);
-+		if (r)
-+			return r;
- 
--			if (adev->asic_type == CHIP_TOPAZ) {
--				r = gfx_v8_0_cp_compute_load_microcode(adev);
--				if (r)
--					return r;
--			} else {
--				r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--										 AMDGPU_UCODE_ID_CP_MEC1);
--				if (r)
--					return -EINVAL;
--			}
--		}
-+		r = gfx_v8_0_cp_compute_load_microcode(adev);
-+		if (r)
-+			return r;
- 	}
- 
- 	r = gfx_v8_0_cp_gfx_resume(adev);
-@@ -4975,12 +4992,69 @@ static int gfx_v8_0_hw_init(void *handle
- 	return r;
- }
- 
-+static int gfx_v8_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
-+{
-+	struct amdgpu_device *adev = kiq_ring->adev;
-+	uint32_t scratch, tmp = 0;
-+	int r, i;
-+
-+	r = amdgpu_gfx_scratch_get(adev, &scratch);
-+	if (r) {
-+		DRM_ERROR("Failed to get scratch reg (%d).\n", r);
-+		return r;
-+	}
-+	WREG32(scratch, 0xCAFEDEAD);
-+
-+	r = amdgpu_ring_alloc(kiq_ring, 10);
-+	if (r) {
-+		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
-+		amdgpu_gfx_scratch_free(adev, scratch);
-+		return r;
-+	}
-+
-+	/* unmap queues */
-+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
-+	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
-+						PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
-+						PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
-+						PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
-+						PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
-+	amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
-+	amdgpu_ring_write(kiq_ring, 0);
-+	amdgpu_ring_write(kiq_ring, 0);
-+	amdgpu_ring_write(kiq_ring, 0);
-+	/* write to scratch for completion */
-+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
-+	amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
-+	amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
-+	amdgpu_ring_commit(kiq_ring);
-+
-+	for (i = 0; i < adev->usec_timeout; i++) {
-+		tmp = RREG32(scratch);
-+		if (tmp == 0xDEADBEEF)
-+			break;
-+		DRM_UDELAY(1);
-+	}
-+	if (i >= adev->usec_timeout) {
-+		DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
-+		r = -EINVAL;
-+	}
-+	amdgpu_gfx_scratch_free(adev, scratch);
-+	return r;
-+}
-+
- static int gfx_v8_0_hw_fini(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	int i;
- 
- 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
- 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
-+
-+	/* disable KCQ to avoid CPC touch memory not valid anymore */
-+	for (i = 0; i < adev->gfx.num_compute_rings; i++)
-+		gfx_v8_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
-+
- 	if (amdgpu_sriov_vf(adev)) {
- 		pr_debug("For SRIOV client, shouldn't do anything.\n");
- 		return 0;
-@@ -5902,7 +5976,6 @@ static int gfx_v8_0_tonga_update_gfx_clo
- {
- 	uint32_t msg_id, pp_state = 0;
- 	uint32_t pp_support_state = 0;
--	void *pp_handle = adev->powerplay.pp_handle;
- 
- 	if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
- 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
-@@ -5920,7 +5993,8 @@ static int gfx_v8_0_tonga_update_gfx_clo
- 				PP_BLOCK_GFX_CG,
- 				pp_support_state,
- 				pp_state);
--		amd_set_clockgating_by_smu(pp_handle, msg_id);
-+		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
-+			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
- 	}
- 
- 	if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
-@@ -5941,7 +6015,8 @@ static int gfx_v8_0_tonga_update_gfx_clo
- 				PP_BLOCK_GFX_MG,
- 				pp_support_state,
- 				pp_state);
--		amd_set_clockgating_by_smu(pp_handle, msg_id);
-+		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
-+			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
- 	}
- 
- 	return 0;
-@@ -5953,7 +6028,6 @@ static int gfx_v8_0_polaris_update_gfx_c
- 
- 	uint32_t msg_id, pp_state = 0;
- 	uint32_t pp_support_state = 0;
--	void *pp_handle = adev->powerplay.pp_handle;
- 
- 	if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
- 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
-@@ -5971,7 +6045,8 @@ static int gfx_v8_0_polaris_update_gfx_c
- 				PP_BLOCK_GFX_CG,
- 				pp_support_state,
- 				pp_state);
--		amd_set_clockgating_by_smu(pp_handle, msg_id);
-+		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
-+			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
- 	}
- 
- 	if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
-@@ -5990,7 +6065,8 @@ static int gfx_v8_0_polaris_update_gfx_c
- 				PP_BLOCK_GFX_3D,
- 				pp_support_state,
- 				pp_state);
--		amd_set_clockgating_by_smu(pp_handle, msg_id);
-+		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
-+			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
- 	}
- 
- 	if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
-@@ -6011,7 +6087,8 @@ static int gfx_v8_0_polaris_update_gfx_c
- 				PP_BLOCK_GFX_MG,
- 				pp_support_state,
- 				pp_state);
--		amd_set_clockgating_by_smu(pp_handle, msg_id);
-+		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
-+			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
- 	}
- 
- 	if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
-@@ -6026,7 +6103,8 @@ static int gfx_v8_0_polaris_update_gfx_c
- 				PP_BLOCK_GFX_RLC,
- 				pp_support_state,
- 				pp_state);
--		amd_set_clockgating_by_smu(pp_handle, msg_id);
-+		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
-+			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
- 	}
- 
- 	if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
-@@ -6040,7 +6118,8 @@ static int gfx_v8_0_polaris_update_gfx_c
- 			PP_BLOCK_GFX_CP,
- 			pp_support_state,
- 			pp_state);
--		amd_set_clockgating_by_smu(pp_handle, msg_id);
-+		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
-+			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
- 	}
- 
- 	return 0;
-@@ -6307,6 +6386,104 @@ static void gfx_v8_0_ring_set_wptr_compu
- 	WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
- }
- 
-+static void gfx_v8_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
-+					   bool acquire)
-+{
-+	struct amdgpu_device *adev = ring->adev;
-+	int pipe_num, tmp, reg;
-+	int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
-+
-+	pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
-+
-+	/* first me only has 2 entries, GFX and HP3D */
-+	if (ring->me > 0)
-+		pipe_num -= 2;
-+
-+	reg = mmSPI_WCL_PIPE_PERCENT_GFX + pipe_num;
-+	tmp = RREG32(reg);
-+	tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
-+	WREG32(reg, tmp);
-+}
-+
-+static void gfx_v8_0_pipe_reserve_resources(struct amdgpu_device *adev,
-+					    struct amdgpu_ring *ring,
-+					    bool acquire)
-+{
-+	int i, pipe;
-+	bool reserve;
-+	struct amdgpu_ring *iring;
-+
-+	mutex_lock(&adev->gfx.pipe_reserve_mutex);
-+	pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
-+	if (acquire)
-+		set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
-+	else
-+		clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
-+
-+	if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
-+		/* Clear all reservations - everyone reacquires all resources */
-+		for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
-+			gfx_v8_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
-+						       true);
-+
-+		for (i = 0; i < adev->gfx.num_compute_rings; ++i)
-+			gfx_v8_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
-+						       true);
-+	} else {
-+		/* Lower all pipes without a current reservation */
-+		for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
-+			iring = &adev->gfx.gfx_ring[i];
-+			pipe = amdgpu_gfx_queue_to_bit(adev,
-+						       iring->me,
-+						       iring->pipe,
-+						       0);
-+			reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
-+			gfx_v8_0_ring_set_pipe_percent(iring, reserve);
-+		}
-+
-+		for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
-+			iring = &adev->gfx.compute_ring[i];
-+			pipe = amdgpu_gfx_queue_to_bit(adev,
-+						       iring->me,
-+						       iring->pipe,
-+						       0);
-+			reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
-+			gfx_v8_0_ring_set_pipe_percent(iring, reserve);
-+		}
-+	}
-+
-+	mutex_unlock(&adev->gfx.pipe_reserve_mutex);
-+}
-+
-+static void gfx_v8_0_hqd_set_priority(struct amdgpu_device *adev,
-+				      struct amdgpu_ring *ring,
-+				      bool acquire)
-+{
-+	uint32_t pipe_priority = acquire ? 0x2 : 0x0;
-+	uint32_t queue_priority = acquire ? 0xf : 0x0;
-+
-+	mutex_lock(&adev->srbm_mutex);
-+	vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
-+
-+	WREG32(mmCP_HQD_PIPE_PRIORITY, pipe_priority);
-+	WREG32(mmCP_HQD_QUEUE_PRIORITY, queue_priority);
-+
-+	vi_srbm_select(adev, 0, 0, 0, 0);
-+	mutex_unlock(&adev->srbm_mutex);
-+}
-+static void gfx_v8_0_ring_set_priority_compute(struct amdgpu_ring *ring,
-+					       enum amd_sched_priority priority)
-+{
-+	struct amdgpu_device *adev = ring->adev;
-+	bool acquire = priority == AMD_SCHED_PRIORITY_HIGH_HW;
-+
-+	if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
-+		return;
-+
-+	gfx_v8_0_hqd_set_priority(adev, ring, acquire);
-+	gfx_v8_0_pipe_reserve_resources(adev, ring, acquire);
-+}
-+
- static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
- 					     u64 addr, u64 seq,
- 					     unsigned flags)
-@@ -6752,6 +6929,7 @@ static const struct amdgpu_ring_funcs gf
- 	.test_ib = gfx_v8_0_ring_test_ib,
- 	.insert_nop = amdgpu_ring_insert_nop,
- 	.pad_ib = amdgpu_ring_generic_pad_ib,
-+	.set_priority = gfx_v8_0_ring_set_priority_compute,
- };
- 
- static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
-@@ -6960,7 +7138,7 @@ static void gfx_v8_0_ring_emit_ce_meta(s
- {
- 	uint64_t ce_payload_addr;
- 	int cnt_ce;
--	static union {
-+	union {
- 		struct vi_ce_ib_state regular;
- 		struct vi_ce_ib_state_chained_ib chained;
- 	} ce_payload = {};
-@@ -6989,7 +7167,7 @@ static void gfx_v8_0_ring_emit_de_meta(s
- {
- 	uint64_t de_payload_addr, gds_addr, csa_addr;
- 	int cnt_de;
--	static union {
-+	union {
- 		struct vi_de_ib_state regular;
- 		struct vi_de_ib_state_chained_ib chained;
- 	} de_payload = {};
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c	2017-12-14 06:39:58.389903549 +0100
-@@ -20,6 +20,7 @@
-  * OTHER DEALINGS IN THE SOFTWARE.
-  *
-  */
-+#include <linux/kernel.h>
- #include <linux/firmware.h>
- #include <drm/drmP.h>
- #include "amdgpu.h"
-@@ -66,38 +67,70 @@ MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
- 
- static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
- {
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
--	       	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
--	{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
--		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
-+	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),
-+	  SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }
- };
- 
- static const u32 golden_settings_gc_9_0[] =
-@@ -174,6 +207,12 @@ static const u32 golden_settings_gc_9_1_
- 	SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
- };
- 
-+static const u32 golden_settings_gc_9_x_common[] =
-+{
-+	SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_INDEX), 0xffffffff, 0x00000000,
-+	SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_DATA), 0xffffffff, 0x2544c382
-+};
-+
- #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
- #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
- 
-@@ -193,22 +232,25 @@ static void gfx_v9_0_init_golden_registe
- 	case CHIP_VEGA10:
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_gc_9_0,
--						 (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
-+						 ARRAY_SIZE(golden_settings_gc_9_0));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_gc_9_0_vg10,
--						 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
-+						 ARRAY_SIZE(golden_settings_gc_9_0_vg10));
- 		break;
- 	case CHIP_RAVEN:
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_gc_9_1,
--						 (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
-+						 ARRAY_SIZE(golden_settings_gc_9_1));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_gc_9_1_rv1,
--						 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
-+						 ARRAY_SIZE(golden_settings_gc_9_1_rv1));
- 		break;
- 	default:
- 		break;
- 	}
-+
-+	amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common,
-+					(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
- }
- 
- static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
-@@ -285,7 +327,7 @@ static int gfx_v9_0_ring_test_ring(struc
- 		DRM_UDELAY(1);
- 	}
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n",
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
- 			 ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
-@@ -337,7 +379,7 @@ static int gfx_v9_0_ring_test_ib(struct
-         }
-         tmp = RREG32(scratch);
-         if (tmp == 0xDEADBEEF) {
--                DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
-+                DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
-                 r = 0;
-         } else {
-                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
-@@ -352,6 +394,25 @@ err1:
-         return r;
- }
- 
-+
-+static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
-+{
-+	release_firmware(adev->gfx.pfp_fw);
-+	adev->gfx.pfp_fw = NULL;
-+	release_firmware(adev->gfx.me_fw);
-+	adev->gfx.me_fw = NULL;
-+	release_firmware(adev->gfx.ce_fw);
-+	adev->gfx.ce_fw = NULL;
-+	release_firmware(adev->gfx.rlc_fw);
-+	adev->gfx.rlc_fw = NULL;
-+	release_firmware(adev->gfx.mec_fw);
-+	adev->gfx.mec_fw = NULL;
-+	release_firmware(adev->gfx.mec2_fw);
-+	adev->gfx.mec2_fw = NULL;
-+
-+	kfree(adev->gfx.rlc.register_list_format);
-+}
-+
- static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
- {
- 	const char *chip_name;
-@@ -936,12 +997,22 @@ static void gfx_v9_0_read_wave_sgprs(str
- 		start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
- }
- 
-+static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
-+				     uint32_t wave, uint32_t thread,
-+				     uint32_t start, uint32_t size,
-+				     uint32_t *dst)
-+{
-+	wave_read_regs(
-+		adev, simd, wave, thread,
-+		start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
-+}
- 
- static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
- 	.get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
- 	.select_se_sh = &gfx_v9_0_select_se_sh,
- 	.read_wave_data = &gfx_v9_0_read_wave_data,
- 	.read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
-+	.read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
- };
- 
- static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
-@@ -1120,30 +1191,22 @@ static int gfx_v9_0_ngg_en(struct amdgpu
- {
- 	struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
- 	int r;
--	u32 data;
--	u32 size;
--	u32 base;
-+	u32 data, base;
- 
- 	if (!amdgpu_ngg)
- 		return 0;
- 
- 	/* Program buffer size */
--	data = 0;
--	size = adev->gfx.ngg.buf[NGG_PRIM].size / 256;
--	data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
--
--	size = adev->gfx.ngg.buf[NGG_POS].size / 256;
--	data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
--
-+	data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
-+			     adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
-+	data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
-+			     adev->gfx.ngg.buf[NGG_POS].size >> 8);
- 	WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
- 
--	data = 0;
--	size = adev->gfx.ngg.buf[NGG_CNTL].size / 256;
--	data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
--
--	size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024;
--	data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
--
-+	data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
-+			     adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
-+	data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
-+			     adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
- 	WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
- 
- 	/* Program buffer base address */
-@@ -1306,7 +1369,10 @@ static int gfx_v9_0_sw_init(void *handle
- 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
- 		ring = &adev->gfx.gfx_ring[i];
- 		ring->ring_obj = NULL;
--		sprintf(ring->name, "gfx");
-+		if (!i)
-+			sprintf(ring->name, "gfx");
-+		else
-+			sprintf(ring->name, "gfx_%d", i);
- 		ring->use_doorbell = true;
- 		ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
- 		r = amdgpu_ring_init(adev, ring, 1024,
-@@ -1346,7 +1412,7 @@ static int gfx_v9_0_sw_init(void *handle
- 		return r;
- 
- 	/* create MQD for all compute queues as wel as KIQ for SRIOV case */
--	r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd));
-+	r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
- 	if (r)
- 		return r;
- 
-@@ -1401,6 +1467,15 @@ static int gfx_v9_0_sw_fini(void *handle
- 
- 	gfx_v9_0_mec_fini(adev);
- 	gfx_v9_0_ngg_fini(adev);
-+	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
-+				&adev->gfx.rlc.clear_state_gpu_addr,
-+				(void **)&adev->gfx.rlc.cs_ptr);
-+	if (adev->asic_type == CHIP_RAVEN) {
-+		amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
-+				&adev->gfx.rlc.cp_table_gpu_addr,
-+				(void **)&adev->gfx.rlc.cp_table_ptr);
-+	}
-+	gfx_v9_0_free_microcode(adev);
- 
- 	return 0;
- }
-@@ -1569,6 +1644,14 @@ static void gfx_v9_0_wait_for_rlc_serdes
- 					break;
- 				udelay(1);
- 			}
-+			if (k == adev->usec_timeout) {
-+				gfx_v9_0_select_se_sh(adev, 0xffffffff,
-+						      0xffffffff, 0xffffffff);
-+				mutex_unlock(&adev->grbm_idx_mutex);
-+				DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
-+					 i, j);
-+				return;
-+			}
- 		}
- 	}
- 	gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
-@@ -1682,10 +1765,10 @@ static int gfx_v9_0_init_rlc_save_restor
- 				adev->gfx.rlc.reg_list_format_size_bytes >> 2,
- 				unique_indirect_regs,
- 				&unique_indirect_reg_count,
--				sizeof(unique_indirect_regs)/sizeof(int),
-+				ARRAY_SIZE(unique_indirect_regs),
- 				indirect_start_offsets,
- 				&indirect_start_offsets_count,
--				sizeof(indirect_start_offsets)/sizeof(int));
-+				ARRAY_SIZE(indirect_start_offsets));
- 
- 	/* enable auto inc in case it is disabled */
- 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
-@@ -1722,12 +1805,12 @@ static int gfx_v9_0_init_rlc_save_restor
- 	/* write the starting offsets to RLC scratch ram */
- 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
- 		adev->gfx.rlc.starting_offsets_start);
--	for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
-+	for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
- 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
- 			indirect_start_offsets[i]);
- 
- 	/* load unique indirect regs*/
--	for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
-+	for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
- 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
- 			unique_indirect_regs[i] & 0x3FFFF);
- 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
-@@ -1740,11 +1823,7 @@ static int gfx_v9_0_init_rlc_save_restor
- 
- static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
- {
--	u32 tmp = 0;
--
--	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
--	tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
--	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
-+	WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
- }
- 
- static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
-@@ -1822,16 +1901,11 @@ static void gfx_v9_0_enable_sck_slow_dow
- 	uint32_t default_data = 0;
- 
- 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
--
--	if (enable == true) {
--		data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
--		if (default_data != data)
--			WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
--	} else {
--		data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
--		if(default_data != data)
--			WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
--	}
-+	data = REG_SET_FIELD(data, RLC_PG_CNTL,
-+			     SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
-+			     enable ? 1 : 0);
-+	if (default_data != data)
-+		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
- }
- 
- static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
-@@ -1841,16 +1915,11 @@ static void gfx_v9_0_enable_sck_slow_dow
- 	uint32_t default_data = 0;
- 
- 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
--
--	if (enable == true) {
--		data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
--		if(default_data != data)
--			WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
--	} else {
--		data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
--		if(default_data != data)
--			WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
--	}
-+	data = REG_SET_FIELD(data, RLC_PG_CNTL,
-+			     SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
-+			     enable ? 1 : 0);
-+	if(default_data != data)
-+		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
- }
- 
- static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
-@@ -1860,16 +1929,11 @@ static void gfx_v9_0_enable_cp_power_gat
- 	uint32_t default_data = 0;
- 
- 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
--
--	if (enable == true) {
--		data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
--		if(default_data != data)
--			WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
--	} else {
--		data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
--		if(default_data != data)
--			WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
--	}
-+	data = REG_SET_FIELD(data, RLC_PG_CNTL,
-+			     CP_PG_DISABLE,
-+			     enable ? 0 : 1);
-+	if(default_data != data)
-+		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
- }
- 
- static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
-@@ -1878,10 +1942,9 @@ static void gfx_v9_0_enable_gfx_cg_power
- 	uint32_t data, default_data;
- 
- 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
--	if (enable == true)
--		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
--	else
--		data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
-+	data = REG_SET_FIELD(data, RLC_PG_CNTL,
-+			     GFX_POWER_GATING_ENABLE,
-+			     enable ? 1 : 0);
- 	if(default_data != data)
- 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
- }
-@@ -1892,10 +1955,9 @@ static void gfx_v9_0_enable_gfx_pipeline
- 	uint32_t data, default_data;
- 
- 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
--	if (enable == true)
--		data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
--	else
--		data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
-+	data = REG_SET_FIELD(data, RLC_PG_CNTL,
-+			     GFX_PIPELINE_PG_ENABLE,
-+			     enable ? 1 : 0);
- 	if(default_data != data)
- 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
- 
-@@ -1910,10 +1972,9 @@ static void gfx_v9_0_enable_gfx_static_m
- 	uint32_t data, default_data;
- 
- 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
--	if (enable == true)
--		data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
--	else
--		data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
-+	data = REG_SET_FIELD(data, RLC_PG_CNTL,
-+			     STATIC_PER_CU_PG_ENABLE,
-+			     enable ? 1 : 0);
- 	if(default_data != data)
- 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
- }
-@@ -1924,10 +1985,9 @@ static void gfx_v9_0_enable_gfx_dynamic_
- 	uint32_t data, default_data;
- 
- 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
--	if (enable == true)
--		data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
--	else
--		data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
-+	data = REG_SET_FIELD(data, RLC_PG_CNTL,
-+			     DYN_PER_CU_PG_ENABLE,
-+			     enable ? 1 : 0);
- 	if(default_data != data)
- 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
- }
-@@ -1967,13 +2027,8 @@ static void gfx_v9_0_init_pg(struct amdg
- 
- void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
- {
--	u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
--
--	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
--	WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
--
-+	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
- 	gfx_v9_0_enable_gui_idle_interrupt(adev, false);
--
- 	gfx_v9_0_wait_for_rlc_serdes(adev);
- }
- 
-@@ -2045,8 +2100,10 @@ static int gfx_v9_0_rlc_resume(struct am
- {
- 	int r;
- 
--	if (amdgpu_sriov_vf(adev))
-+	if (amdgpu_sriov_vf(adev)) {
-+		gfx_v9_0_init_csb(adev);
- 		return 0;
-+	}
- 
- 	gfx_v9_0_rlc_stop(adev);
- 
-@@ -2463,6 +2520,13 @@ static int gfx_v9_0_mqd_init(struct amdg
- 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
- 	mqd->compute_misc_reserved = 0x00000003;
- 
-+	mqd->dynamic_cu_mask_addr_lo =
-+		lower_32_bits(ring->mqd_gpu_addr
-+			      + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
-+	mqd->dynamic_cu_mask_addr_hi =
-+		upper_32_bits(ring->mqd_gpu_addr
-+			      + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
-+
- 	eop_base_addr = ring->eop_gpu_addr >> 8;
- 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
- 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
-@@ -2486,10 +2550,10 @@ static int gfx_v9_0_mqd_init(struct amdg
- 				    DOORBELL_SOURCE, 0);
- 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
- 				    DOORBELL_HIT, 0);
--	}
--	else
-+	} else {
- 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
- 					 DOORBELL_EN, 0);
-+	}
- 
- 	mqd->cp_hqd_pq_doorbell_control = tmp;
- 
-@@ -2692,10 +2756,10 @@ static int gfx_v9_0_kiq_init_queue(struc
- 
- 	gfx_v9_0_kiq_setting(ring);
- 
--	if (adev->gfx.in_reset) { /* for GPU_RESET case */
-+	if (adev->in_gpu_reset) { /* for GPU_RESET case */
- 		/* reset MQD to a clean status */
- 		if (adev->gfx.mec.mqd_backup[mqd_idx])
--			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
-+			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
- 
- 		/* reset ring buffer */
- 		ring->wptr = 0;
-@@ -2707,7 +2771,9 @@ static int gfx_v9_0_kiq_init_queue(struc
- 		soc15_grbm_select(adev, 0, 0, 0, 0);
- 		mutex_unlock(&adev->srbm_mutex);
- 	} else {
--		memset((void *)mqd, 0, sizeof(*mqd));
-+		memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
-+		((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
-+		((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
- 		mutex_lock(&adev->srbm_mutex);
- 		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
- 		gfx_v9_0_mqd_init(ring);
-@@ -2716,7 +2782,7 @@ static int gfx_v9_0_kiq_init_queue(struc
- 		mutex_unlock(&adev->srbm_mutex);
- 
- 		if (adev->gfx.mec.mqd_backup[mqd_idx])
--			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
-+			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
- 	}
- 
- 	return 0;
-@@ -2728,8 +2794,10 @@ static int gfx_v9_0_kcq_init_queue(struc
- 	struct v9_mqd *mqd = ring->mqd_ptr;
- 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
- 
--	if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
--		memset((void *)mqd, 0, sizeof(*mqd));
-+	if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
-+		memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
-+		((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
-+		((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
- 		mutex_lock(&adev->srbm_mutex);
- 		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
- 		gfx_v9_0_mqd_init(ring);
-@@ -2737,11 +2805,11 @@ static int gfx_v9_0_kcq_init_queue(struc
- 		mutex_unlock(&adev->srbm_mutex);
- 
- 		if (adev->gfx.mec.mqd_backup[mqd_idx])
--			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
--	} else if (adev->gfx.in_reset) { /* for GPU_RESET case */
-+			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
-+	} else if (adev->in_gpu_reset) { /* for GPU_RESET case */
- 		/* reset MQD to a clean status */
- 		if (adev->gfx.mec.mqd_backup[mqd_idx])
--			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
-+			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
- 
- 		/* reset ring buffer */
- 		ring->wptr = 0;
-@@ -2882,12 +2950,70 @@ static int gfx_v9_0_hw_init(void *handle
- 	return r;
- }
- 
-+static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
-+{
-+	struct amdgpu_device *adev = kiq_ring->adev;
-+	uint32_t scratch, tmp = 0;
-+	int r, i;
-+
-+	r = amdgpu_gfx_scratch_get(adev, &scratch);
-+	if (r) {
-+		DRM_ERROR("Failed to get scratch reg (%d).\n", r);
-+		return r;
-+	}
-+	WREG32(scratch, 0xCAFEDEAD);
-+
-+	r = amdgpu_ring_alloc(kiq_ring, 10);
-+	if (r) {
-+		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
-+		amdgpu_gfx_scratch_free(adev, scratch);
-+		return r;
-+	}
-+
-+	/* unmap queues */
-+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
-+	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
-+						PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
-+						PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
-+						PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
-+						PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
-+	amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
-+	amdgpu_ring_write(kiq_ring, 0);
-+	amdgpu_ring_write(kiq_ring, 0);
-+	amdgpu_ring_write(kiq_ring, 0);
-+	/* write to scratch for completion */
-+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
-+	amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
-+	amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
-+	amdgpu_ring_commit(kiq_ring);
-+
-+	for (i = 0; i < adev->usec_timeout; i++) {
-+		tmp = RREG32(scratch);
-+		if (tmp == 0xDEADBEEF)
-+			break;
-+		DRM_UDELAY(1);
-+	}
-+	if (i >= adev->usec_timeout) {
-+		DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
-+		r = -EINVAL;
-+	}
-+	amdgpu_gfx_scratch_free(adev, scratch);
-+	return r;
-+}
-+
-+
- static int gfx_v9_0_hw_fini(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	int i;
- 
- 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
- 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
-+
-+	/* disable KCQ to avoid CPC touch memory not valid anymore */
-+	for (i = 0; i < adev->gfx.num_compute_rings; i++)
-+		gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
-+
- 	if (amdgpu_sriov_vf(adev)) {
- 		pr_debug("For SRIOV client, shouldn't do anything.\n");
- 		return 0;
-@@ -2930,15 +3056,10 @@ static bool gfx_v9_0_is_idle(void *handl
- static int gfx_v9_0_wait_for_idle(void *handle)
- {
- 	unsigned i;
--	u32 tmp;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	for (i = 0; i < adev->usec_timeout; i++) {
--		/* read MC_STATUS */
--		tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
--			GRBM_STATUS__GUI_ACTIVE_MASK;
--
--		if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
-+		if (gfx_v9_0_is_idle(handle))
- 			return 0;
- 		udelay(1);
- 	}
-@@ -3497,9 +3618,11 @@ static void gfx_v9_0_ring_set_wptr_gfx(s
- static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
- {
- 	u32 ref_and_mask, reg_mem_engine;
--	struct nbio_hdp_flush_reg *nbio_hf_reg;
-+	const struct nbio_hdp_flush_reg *nbio_hf_reg;
- 
--	if (ring->adev->asic_type == CHIP_VEGA10)
-+	if (ring->adev->flags & AMD_IS_APU)
-+		nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
-+	else
- 		nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
- 
- 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
-@@ -3528,7 +3651,7 @@ static void gfx_v9_0_ring_emit_hdp_flush
- static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
- {
- 	gfx_v9_0_write_data_to_reg(ring, 0, true,
--				   SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
-+				   SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
- }
- 
- static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
-@@ -3718,7 +3841,7 @@ static void gfx_v9_ring_emit_sb(struct a
- 
- static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
- {
--	static struct v9_ce_ib_state ce_payload = {0};
-+	struct v9_ce_ib_state ce_payload = {0};
- 	uint64_t csa_addr;
- 	int cnt;
- 
-@@ -3737,7 +3860,7 @@ static void gfx_v9_0_ring_emit_ce_meta(s
- 
- static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
- {
--	static struct v9_de_ib_state de_payload = {0};
-+	struct v9_de_ib_state de_payload = {0};
- 	uint64_t csa_addr, gds_addr;
- 	int cnt;
- 
-@@ -3757,6 +3880,12 @@ static void gfx_v9_0_ring_emit_de_meta(s
- 	amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
- }
- 
-+static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
-+{
-+	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
-+	amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
-+}
-+
- static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
- {
- 	uint32_t dw2 = 0;
-@@ -3764,6 +3893,8 @@ static void gfx_v9_ring_emit_cntxcntl(st
- 	if (amdgpu_sriov_vf(ring->adev))
- 		gfx_v9_0_ring_emit_ce_meta(ring);
- 
-+	gfx_v9_0_ring_emit_tmz(ring, true);
-+
- 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
- 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
- 		/* set load_global_config & load_global_uconfig */
-@@ -3814,12 +3945,6 @@ static void gfx_v9_0_ring_emit_patch_con
- 		ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
- }
- 
--static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
--{
--	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
--	amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
--}
--
- static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
- {
- 	struct amdgpu_device *adev = ring->adev;
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c	2017-12-14 06:39:58.389903549 +0100
-@@ -222,11 +222,6 @@ static void gmc_v6_0_vram_gtt_location(s
- 	u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
- 	base <<= 24;
- 
--	if (mc->mc_vram_size > 0xFFC0000000ULL) {
--		dev_warn(adev->dev, "limiting VRAM\n");
--		mc->real_vram_size = 0xFFC0000000ULL;
--		mc->mc_vram_size = 0xFFC0000000ULL;
--	}
- 	amdgpu_vram_location(adev, &adev->mc, base);
- 	amdgpu_gart_location(adev, mc);
- }
-@@ -283,6 +278,7 @@ static int gmc_v6_0_mc_init(struct amdgp
- 
- 	u32 tmp;
- 	int chansize, numchan;
-+	int r;
- 
- 	tmp = RREG32(mmMC_ARB_RAMCFG);
- 	if (tmp & (1 << 11)) {
-@@ -324,12 +320,17 @@ static int gmc_v6_0_mc_init(struct amdgp
- 		break;
- 	}
- 	adev->mc.vram_width = numchan * chansize;
--	/* Could aper size report 0 ? */
--	adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
--	adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
- 	/* size in MB on si */
- 	adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
- 	adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
-+
-+	if (!(adev->flags & AMD_IS_APU)) {
-+		r = amdgpu_device_resize_fb_bar(adev);
-+		if (r)
-+			return r;
-+	}
-+	adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
-+	adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
- 	adev->mc.visible_vram_size = adev->mc.aper_size;
- 
- 	/* set the gart size */
-@@ -477,16 +478,14 @@ static void gmc_v6_0_set_prt(struct amdg
- 
- static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
- {
--	int r, i;
-+	int i;
- 	u32 field;
- 
- 	if (adev->gart.robj == NULL) {
- 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
- 		return -EINVAL;
- 	}
--	r = amdgpu_gart_table_vram_pin(adev);
--	if (r)
--		return r;
-+
- 	/* Setup TLB control */
- 	WREG32(mmMC_VM_MX_L1_TLB_CNTL,
- 	       (0xA << 7) |
-@@ -613,7 +612,6 @@ static void gmc_v6_0_gart_disable(struct
- 	WREG32(mmVM_L2_CNTL3,
- 	       VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
- 	       (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
--	amdgpu_gart_table_vram_unpin(adev);
- }
- 
- static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
-@@ -831,8 +829,7 @@ static int gmc_v6_0_sw_init(void *handle
- 	if (r)
- 		return r;
- 
--	amdgpu_vm_adjust_size(adev, 64, 4);
--	adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
-+	amdgpu_vm_adjust_size(adev, 64, 9);
- 
- 	adev->mc.mc_mask = 0xffffffffffULL;
- 
-@@ -897,10 +894,12 @@ static int gmc_v6_0_sw_fini(void *handle
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-+	amdgpu_gem_force_release(adev);
- 	amdgpu_vm_manager_fini(adev);
- 	gmc_v6_0_gart_fini(adev);
--	amdgpu_gem_force_release(adev);
- 	amdgpu_bo_fini(adev);
-+	release_firmware(adev->mc.fw);
-+	adev->mc.fw = NULL;
- 
- 	return 0;
- }
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c	2017-12-14 06:39:58.389903549 +0100
-@@ -69,10 +69,10 @@ static void gmc_v7_0_init_golden_registe
- 	case CHIP_TOPAZ:
- 		amdgpu_program_register_sequence(adev,
- 						 iceland_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
-+						 ARRAY_SIZE(iceland_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_iceland_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
-+						 ARRAY_SIZE(golden_settings_iceland_a11));
- 		break;
- 	default:
- 		break;
-@@ -240,12 +240,6 @@ static void gmc_v7_0_vram_gtt_location(s
- 	u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
- 	base <<= 24;
- 
--	if (mc->mc_vram_size > 0xFFC0000000ULL) {
--		/* leave room for at least 1024M GTT */
--		dev_warn(adev->dev, "limiting VRAM\n");
--		mc->real_vram_size = 0xFFC0000000ULL;
--		mc->mc_vram_size = 0xFFC0000000ULL;
--	}
- 	amdgpu_vram_location(adev, &adev->mc, base);
- 	amdgpu_gart_location(adev, mc);
- }
-@@ -322,6 +316,8 @@ static void gmc_v7_0_mc_program(struct a
-  */
- static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
- {
-+	int r;
-+
- 	adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
- 	if (!adev->mc.vram_width) {
- 		u32 tmp;
-@@ -367,13 +363,18 @@ static int gmc_v7_0_mc_init(struct amdgp
- 		}
- 		adev->mc.vram_width = numchan * chansize;
- 	}
--	/* Could aper size report 0 ? */
--	adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
--	adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
- 	/* size in MB on si */
- 	adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
- 	adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
- 
-+	if (!(adev->flags & AMD_IS_APU)) {
-+		r = amdgpu_device_resize_fb_bar(adev);
-+		if (r)
-+			return r;
-+	}
-+	adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
-+	adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
-+
- #ifdef CONFIG_X86_64
- 	if (adev->flags & AMD_IS_APU) {
- 		adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
-@@ -581,16 +582,14 @@ static void gmc_v7_0_set_prt(struct amdg
-  */
- static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
- {
--	int r, i;
-+	int i;
- 	u32 tmp, field;
- 
- 	if (adev->gart.robj == NULL) {
- 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
- 		return -EINVAL;
- 	}
--	r = amdgpu_gart_table_vram_pin(adev);
--	if (r)
--		return r;
-+
- 	/* Setup TLB control */
- 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
- 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
-@@ -723,7 +722,6 @@ static void gmc_v7_0_gart_disable(struct
- 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
- 	WREG32(mmVM_L2_CNTL, tmp);
- 	WREG32(mmVM_L2_CNTL2, 0);
--	amdgpu_gart_table_vram_unpin(adev);
- }
- 
- /**
-@@ -970,8 +968,7 @@ static int gmc_v7_0_sw_init(void *handle
- 	 * Currently set to 4GB ((1 << 20) 4k pages).
- 	 * Max GPUVM size for cayman and SI is 40 bits.
- 	 */
--	amdgpu_vm_adjust_size(adev, 64, 4);
--	adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
-+	amdgpu_vm_adjust_size(adev, 64, 9);
- 
- 	/* Set the internal MC address mask
- 	 * This is the max address of the GPU's
-@@ -1046,10 +1043,12 @@ static int gmc_v7_0_sw_fini(void *handle
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-+	amdgpu_gem_force_release(adev);
- 	amdgpu_vm_manager_fini(adev);
- 	gmc_v7_0_gart_fini(adev);
--	amdgpu_gem_force_release(adev);
- 	amdgpu_bo_fini(adev);
-+	release_firmware(adev->mc.fw);
-+	adev->mc.fw = NULL;
- 
- 	return 0;
- }
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c	2017-12-14 06:39:58.389903549 +0100
-@@ -122,42 +122,42 @@ static void gmc_v8_0_init_golden_registe
- 	case CHIP_FIJI:
- 		amdgpu_program_register_sequence(adev,
- 						 fiji_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
-+						 ARRAY_SIZE(fiji_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_fiji_a10,
--						 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
-+						 ARRAY_SIZE(golden_settings_fiji_a10));
- 		break;
- 	case CHIP_TONGA:
- 		amdgpu_program_register_sequence(adev,
- 						 tonga_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
-+						 ARRAY_SIZE(tonga_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_tonga_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
-+						 ARRAY_SIZE(golden_settings_tonga_a11));
- 		break;
- 	case CHIP_POLARIS11:
- 	case CHIP_POLARIS12:
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_polaris11_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
-+						 ARRAY_SIZE(golden_settings_polaris11_a11));
- 		break;
- 	case CHIP_POLARIS10:
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_polaris10_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
-+						 ARRAY_SIZE(golden_settings_polaris10_a11));
- 		break;
- 	case CHIP_CARRIZO:
- 		amdgpu_program_register_sequence(adev,
- 						 cz_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
-+						 ARRAY_SIZE(cz_mgcg_cgcg_init));
- 		break;
- 	case CHIP_STONEY:
- 		amdgpu_program_register_sequence(adev,
- 						 stoney_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
-+						 ARRAY_SIZE(stoney_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_stoney_common,
--						 (const u32)ARRAY_SIZE(golden_settings_stoney_common));
-+						 ARRAY_SIZE(golden_settings_stoney_common));
- 		break;
- 	default:
- 		break;
-@@ -405,12 +405,6 @@ static void gmc_v8_0_vram_gtt_location(s
- 		base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
- 	base <<= 24;
- 
--	if (mc->mc_vram_size > 0xFFC0000000ULL) {
--		/* leave room for at least 1024M GTT */
--		dev_warn(adev->dev, "limiting VRAM\n");
--		mc->real_vram_size = 0xFFC0000000ULL;
--		mc->mc_vram_size = 0xFFC0000000ULL;
--	}
- 	amdgpu_vram_location(adev, &adev->mc, base);
- 	amdgpu_gart_location(adev, mc);
- }
-@@ -498,6 +492,8 @@ static void gmc_v8_0_mc_program(struct a
-  */
- static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
- {
-+	int r;
-+
- 	adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
- 	if (!adev->mc.vram_width) {
- 		u32 tmp;
-@@ -543,13 +539,18 @@ static int gmc_v8_0_mc_init(struct amdgp
- 		}
- 		adev->mc.vram_width = numchan * chansize;
- 	}
--	/* Could aper size report 0 ? */
--	adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
--	adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
- 	/* size in MB on si */
- 	adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
- 	adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
- 
-+	if (!(adev->flags & AMD_IS_APU)) {
-+		r = amdgpu_device_resize_fb_bar(adev);
-+		if (r)
-+			return r;
-+	}
-+	adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
-+	adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
-+
- #ifdef CONFIG_X86_64
- 	if (adev->flags & AMD_IS_APU) {
- 		adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
-@@ -780,16 +781,14 @@ static void gmc_v8_0_set_prt(struct amdg
-  */
- static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
- {
--	int r, i;
-+	int i;
- 	u32 tmp, field;
- 
- 	if (adev->gart.robj == NULL) {
- 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
- 		return -EINVAL;
- 	}
--	r = amdgpu_gart_table_vram_pin(adev);
--	if (r)
--		return r;
-+
- 	/* Setup TLB control */
- 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
- 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
-@@ -939,7 +938,6 @@ static void gmc_v8_0_gart_disable(struct
- 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
- 	WREG32(mmVM_L2_CNTL, tmp);
- 	WREG32(mmVM_L2_CNTL2, 0);
--	amdgpu_gart_table_vram_unpin(adev);
- }
- 
- /**
-@@ -1067,8 +1065,7 @@ static int gmc_v8_0_sw_init(void *handle
- 	 * Currently set to 4GB ((1 << 20) 4k pages).
- 	 * Max GPUVM size for cayman and SI is 40 bits.
- 	 */
--	amdgpu_vm_adjust_size(adev, 64, 4);
--	adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
-+	amdgpu_vm_adjust_size(adev, 64, 9);
- 
- 	/* Set the internal MC address mask
- 	 * This is the max address of the GPU's
-@@ -1143,10 +1140,12 @@ static int gmc_v8_0_sw_fini(void *handle
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-+	amdgpu_gem_force_release(adev);
- 	amdgpu_vm_manager_fini(adev);
- 	gmc_v8_0_gart_fini(adev);
--	amdgpu_gem_force_release(adev);
- 	amdgpu_bo_fini(adev);
-+	release_firmware(adev->mc.fw);
-+	adev->mc.fw = NULL;
- 
- 	return 0;
- }
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c	2017-12-14 06:39:58.389903549 +0100
-@@ -32,8 +32,11 @@
- #include "vega10/DC/dce_12_0_offset.h"
- #include "vega10/DC/dce_12_0_sh_mask.h"
- #include "vega10/vega10_enum.h"
-+#include "vega10/MMHUB/mmhub_1_0_offset.h"
-+#include "vega10/ATHUB/athub_1_0_offset.h"
- 
- #include "soc15_common.h"
-+#include "vega10/UMC/umc_6_0_sh_mask.h"
- 
- #include "nbio_v6_1.h"
- #include "nbio_v7_0.h"
-@@ -71,13 +74,140 @@ static const u32 golden_settings_vega10_
- 	0xf6e, 0x0fffffff, 0x00000000,
- };
- 
-+static const u32 golden_settings_mmhub_1_0_0[] =
-+{
-+	SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa,
-+	SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565
-+};
-+
-+static const u32 golden_settings_athub_1_0_0[] =
-+{
-+	SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800,
-+	SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008
-+};
-+
-+/* Ecc related register addresses, (BASE + reg offset) */
-+/* Universal Memory Controller caps (may be fused). */
-+/* UMCCH:UmcLocalCap */
-+#define UMCLOCALCAPS_ADDR0	(0x00014306 + 0x00000000)
-+#define UMCLOCALCAPS_ADDR1	(0x00014306 + 0x00000800)
-+#define UMCLOCALCAPS_ADDR2	(0x00014306 + 0x00001000)
-+#define UMCLOCALCAPS_ADDR3	(0x00014306 + 0x00001800)
-+#define UMCLOCALCAPS_ADDR4	(0x00054306 + 0x00000000)
-+#define UMCLOCALCAPS_ADDR5	(0x00054306 + 0x00000800)
-+#define UMCLOCALCAPS_ADDR6	(0x00054306 + 0x00001000)
-+#define UMCLOCALCAPS_ADDR7	(0x00054306 + 0x00001800)
-+#define UMCLOCALCAPS_ADDR8	(0x00094306 + 0x00000000)
-+#define UMCLOCALCAPS_ADDR9	(0x00094306 + 0x00000800)
-+#define UMCLOCALCAPS_ADDR10	(0x00094306 + 0x00001000)
-+#define UMCLOCALCAPS_ADDR11	(0x00094306 + 0x00001800)
-+#define UMCLOCALCAPS_ADDR12	(0x000d4306 + 0x00000000)
-+#define UMCLOCALCAPS_ADDR13	(0x000d4306 + 0x00000800)
-+#define UMCLOCALCAPS_ADDR14	(0x000d4306 + 0x00001000)
-+#define UMCLOCALCAPS_ADDR15	(0x000d4306 + 0x00001800)
-+
-+/* Universal Memory Controller Channel config. */
-+/* UMCCH:UMC_CONFIG */
-+#define UMCCH_UMC_CONFIG_ADDR0	(0x00014040 + 0x00000000)
-+#define UMCCH_UMC_CONFIG_ADDR1	(0x00014040 + 0x00000800)
-+#define UMCCH_UMC_CONFIG_ADDR2	(0x00014040 + 0x00001000)
-+#define UMCCH_UMC_CONFIG_ADDR3	(0x00014040 + 0x00001800)
-+#define UMCCH_UMC_CONFIG_ADDR4	(0x00054040 + 0x00000000)
-+#define UMCCH_UMC_CONFIG_ADDR5	(0x00054040 + 0x00000800)
-+#define UMCCH_UMC_CONFIG_ADDR6	(0x00054040 + 0x00001000)
-+#define UMCCH_UMC_CONFIG_ADDR7	(0x00054040 + 0x00001800)
-+#define UMCCH_UMC_CONFIG_ADDR8	(0x00094040 + 0x00000000)
-+#define UMCCH_UMC_CONFIG_ADDR9	(0x00094040 + 0x00000800)
-+#define UMCCH_UMC_CONFIG_ADDR10	(0x00094040 + 0x00001000)
-+#define UMCCH_UMC_CONFIG_ADDR11	(0x00094040 + 0x00001800)
-+#define UMCCH_UMC_CONFIG_ADDR12	(0x000d4040 + 0x00000000)
-+#define UMCCH_UMC_CONFIG_ADDR13	(0x000d4040 + 0x00000800)
-+#define UMCCH_UMC_CONFIG_ADDR14	(0x000d4040 + 0x00001000)
-+#define UMCCH_UMC_CONFIG_ADDR15	(0x000d4040 + 0x00001800)
-+
-+/* Universal Memory Controller Channel Ecc config. */
-+/* UMCCH:EccCtrl */
-+#define UMCCH_ECCCTRL_ADDR0	(0x00014053 + 0x00000000)
-+#define UMCCH_ECCCTRL_ADDR1	(0x00014053 + 0x00000800)
-+#define UMCCH_ECCCTRL_ADDR2	(0x00014053 + 0x00001000)
-+#define UMCCH_ECCCTRL_ADDR3	(0x00014053 + 0x00001800)
-+#define UMCCH_ECCCTRL_ADDR4	(0x00054053 + 0x00000000)
-+#define UMCCH_ECCCTRL_ADDR5	(0x00054053 + 0x00000800)
-+#define UMCCH_ECCCTRL_ADDR6	(0x00054053 + 0x00001000)
-+#define UMCCH_ECCCTRL_ADDR7	(0x00054053 + 0x00001800)
-+#define UMCCH_ECCCTRL_ADDR8	(0x00094053 + 0x00000000)
-+#define UMCCH_ECCCTRL_ADDR9	(0x00094053 + 0x00000800)
-+#define UMCCH_ECCCTRL_ADDR10	(0x00094053 + 0x00001000)
-+#define UMCCH_ECCCTRL_ADDR11	(0x00094053 + 0x00001800)
-+#define UMCCH_ECCCTRL_ADDR12	(0x000d4053 + 0x00000000)
-+#define UMCCH_ECCCTRL_ADDR13	(0x000d4053 + 0x00000800)
-+#define UMCCH_ECCCTRL_ADDR14	(0x000d4053 + 0x00001000)
-+#define UMCCH_ECCCTRL_ADDR15	(0x000d4053 + 0x00001800)
-+
-+static const uint32_t ecc_umclocalcap_addrs[] = {
-+	UMCLOCALCAPS_ADDR0,
-+	UMCLOCALCAPS_ADDR1,
-+	UMCLOCALCAPS_ADDR2,
-+	UMCLOCALCAPS_ADDR3,
-+	UMCLOCALCAPS_ADDR4,
-+	UMCLOCALCAPS_ADDR5,
-+	UMCLOCALCAPS_ADDR6,
-+	UMCLOCALCAPS_ADDR7,
-+	UMCLOCALCAPS_ADDR8,
-+	UMCLOCALCAPS_ADDR9,
-+	UMCLOCALCAPS_ADDR10,
-+	UMCLOCALCAPS_ADDR11,
-+	UMCLOCALCAPS_ADDR12,
-+	UMCLOCALCAPS_ADDR13,
-+	UMCLOCALCAPS_ADDR14,
-+	UMCLOCALCAPS_ADDR15,
-+};
-+
-+static const uint32_t ecc_umcch_umc_config_addrs[] = {
-+	UMCCH_UMC_CONFIG_ADDR0,
-+	UMCCH_UMC_CONFIG_ADDR1,
-+	UMCCH_UMC_CONFIG_ADDR2,
-+	UMCCH_UMC_CONFIG_ADDR3,
-+	UMCCH_UMC_CONFIG_ADDR4,
-+	UMCCH_UMC_CONFIG_ADDR5,
-+	UMCCH_UMC_CONFIG_ADDR6,
-+	UMCCH_UMC_CONFIG_ADDR7,
-+	UMCCH_UMC_CONFIG_ADDR8,
-+	UMCCH_UMC_CONFIG_ADDR9,
-+	UMCCH_UMC_CONFIG_ADDR10,
-+	UMCCH_UMC_CONFIG_ADDR11,
-+	UMCCH_UMC_CONFIG_ADDR12,
-+	UMCCH_UMC_CONFIG_ADDR13,
-+	UMCCH_UMC_CONFIG_ADDR14,
-+	UMCCH_UMC_CONFIG_ADDR15,
-+};
-+
-+static const uint32_t ecc_umcch_eccctrl_addrs[] = {
-+	UMCCH_ECCCTRL_ADDR0,
-+	UMCCH_ECCCTRL_ADDR1,
-+	UMCCH_ECCCTRL_ADDR2,
-+	UMCCH_ECCCTRL_ADDR3,
-+	UMCCH_ECCCTRL_ADDR4,
-+	UMCCH_ECCCTRL_ADDR5,
-+	UMCCH_ECCCTRL_ADDR6,
-+	UMCCH_ECCCTRL_ADDR7,
-+	UMCCH_ECCCTRL_ADDR8,
-+	UMCCH_ECCCTRL_ADDR9,
-+	UMCCH_ECCCTRL_ADDR10,
-+	UMCCH_ECCCTRL_ADDR11,
-+	UMCCH_ECCCTRL_ADDR12,
-+	UMCCH_ECCCTRL_ADDR13,
-+	UMCCH_ECCCTRL_ADDR14,
-+	UMCCH_ECCCTRL_ADDR15,
-+};
-+
- static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
- 					struct amdgpu_irq_src *src,
- 					unsigned type,
- 					enum amdgpu_interrupt_state state)
- {
- 	struct amdgpu_vmhub *hub;
--	u32 tmp, reg, bits, i;
-+	u32 tmp, reg, bits, i, j;
- 
- 	bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
- 		VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
-@@ -89,43 +219,26 @@ static int gmc_v9_0_vm_fault_interrupt_s
- 
- 	switch (state) {
- 	case AMDGPU_IRQ_STATE_DISABLE:
--		/* MM HUB */
--		hub = &adev->vmhub[AMDGPU_MMHUB];
--		for (i = 0; i< 16; i++) {
--			reg = hub->vm_context0_cntl + i;
--			tmp = RREG32(reg);
--			tmp &= ~bits;
--			WREG32(reg, tmp);
--		}
--
--		/* GFX HUB */
--		hub = &adev->vmhub[AMDGPU_GFXHUB];
--		for (i = 0; i < 16; i++) {
--			reg = hub->vm_context0_cntl + i;
--			tmp = RREG32(reg);
--			tmp &= ~bits;
--			WREG32(reg, tmp);
-+		for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
-+			hub = &adev->vmhub[j];
-+			for (i = 0; i < 16; i++) {
-+				reg = hub->vm_context0_cntl + i;
-+				tmp = RREG32(reg);
-+				tmp &= ~bits;
-+				WREG32(reg, tmp);
-+			}
- 		}
- 		break;
- 	case AMDGPU_IRQ_STATE_ENABLE:
--		/* MM HUB */
--		hub = &adev->vmhub[AMDGPU_MMHUB];
--		for (i = 0; i< 16; i++) {
--			reg = hub->vm_context0_cntl + i;
--			tmp = RREG32(reg);
--			tmp |= bits;
--			WREG32(reg, tmp);
--		}
--
--		/* GFX HUB */
--		hub = &adev->vmhub[AMDGPU_GFXHUB];
--		for (i = 0; i < 16; i++) {
--			reg = hub->vm_context0_cntl + i;
--			tmp = RREG32(reg);
--			tmp |= bits;
--			WREG32(reg, tmp);
-+		for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
-+			hub = &adev->vmhub[j];
-+			for (i = 0; i < 16; i++) {
-+				reg = hub->vm_context0_cntl + i;
-+				tmp = RREG32(reg);
-+				tmp |= bits;
-+				WREG32(reg, tmp);
-+			}
- 		}
--		break;
- 	default:
- 		break;
- 	}
-@@ -392,6 +505,85 @@ static int gmc_v9_0_early_init(void *han
- 	return 0;
- }
- 
-+static int gmc_v9_0_ecc_available(struct amdgpu_device *adev)
-+{
-+	uint32_t reg_val;
-+	uint32_t reg_addr;
-+	uint32_t field_val;
-+	size_t i;
-+	uint32_t fv2;
-+	size_t lost_sheep;
-+
-+	DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n");
-+
-+	lost_sheep = 0;
-+	for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {
-+		reg_addr = ecc_umclocalcap_addrs[i];
-+		DRM_DEBUG("ecc: "
-+			  "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n",
-+			  i, reg_addr);
-+		reg_val = RREG32(reg_addr);
-+		field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap,
-+					  EccDis);
-+		DRM_DEBUG("ecc: "
-+			  "reg_val: 0x%08x, "
-+			  "EccDis: 0x%08x, ",
-+			  reg_val, field_val);
-+		if (field_val) {
-+			DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n");
-+			++lost_sheep;
-+		}
-+	}
-+
-+	for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) {
-+		reg_addr = ecc_umcch_umc_config_addrs[i];
-+		DRM_DEBUG("ecc: "
-+			  "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x",
-+			  i, reg_addr);
-+		reg_val = RREG32(reg_addr);
-+		field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG,
-+					  DramReady);
-+		DRM_DEBUG("ecc: "
-+			  "reg_val: 0x%08x, "
-+			  "DramReady: 0x%08x\n",
-+			  reg_val, field_val);
-+
-+		if (!field_val) {
-+			DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n");
-+			++lost_sheep;
-+		}
-+	}
-+
-+	for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) {
-+		reg_addr = ecc_umcch_eccctrl_addrs[i];
-+		DRM_DEBUG("ecc: "
-+			  "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ",
-+			  i, reg_addr);
-+		reg_val = RREG32(reg_addr);
-+		field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
-+					  WrEccEn);
-+		fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
-+				    RdEccEn);
-+		DRM_DEBUG("ecc: "
-+			  "reg_val: 0x%08x, "
-+			  "WrEccEn: 0x%08x, "
-+			  "RdEccEn: 0x%08x\n",
-+			  reg_val, field_val, fv2);
-+
-+		if (!field_val) {
-+			DRM_DEBUG("ecc: WrEccEn is not set\n");
-+			++lost_sheep;
-+		}
-+		if (!fv2) {
-+			DRM_DEBUG("ecc: RdEccEn is not set\n");
-+			++lost_sheep;
-+		}
-+	}
-+
-+	DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep);
-+	return lost_sheep == 0;
-+}
-+
- static int gmc_v9_0_late_init(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-@@ -406,6 +598,7 @@ static int gmc_v9_0_late_init(void *hand
- 	 */
- 	unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
- 	unsigned i;
-+	int r;
- 
- 	for(i = 0; i < adev->num_rings; ++i) {
- 		struct amdgpu_ring *ring = adev->rings[i];
-@@ -421,6 +614,16 @@ static int gmc_v9_0_late_init(void *hand
- 	for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
- 		BUG_ON(vm_inv_eng[i] > 16);
- 
-+	r = gmc_v9_0_ecc_available(adev);
-+	if (r == 1) {
-+		DRM_INFO("ECC is active.\n");
-+	} else if (r == 0) {
-+		DRM_INFO("ECC is not present.\n");
-+	} else {
-+		DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
-+		return r;
-+	}
-+
- 	return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
- }
- 
-@@ -452,6 +655,7 @@ static int gmc_v9_0_mc_init(struct amdgp
- {
- 	u32 tmp;
- 	int chansize, numchan;
-+	int r;
- 
- 	adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
- 	if (!adev->mc.vram_width) {
-@@ -494,17 +698,22 @@ static int gmc_v9_0_mc_init(struct amdgp
- 		adev->mc.vram_width = numchan * chansize;
- 	}
- 
--	/* Could aper size report 0 ? */
--	adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
--	adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
- 	/* size in MB on si */
- 	adev->mc.mc_vram_size =
- 		((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) :
- 		 nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL;
- 	adev->mc.real_vram_size = adev->mc.mc_vram_size;
--	adev->mc.visible_vram_size = adev->mc.aper_size;
-+
-+	if (!(adev->flags & AMD_IS_APU)) {
-+		r = amdgpu_device_resize_fb_bar(adev);
-+		if (r)
-+			return r;
-+	}
-+	adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
-+	adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
- 
- 	/* In case the PCI BAR is larger than the actual amount of vram */
-+	adev->mc.visible_vram_size = adev->mc.aper_size;
- 	if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
- 		adev->mc.visible_vram_size = adev->mc.real_vram_size;
- 
-@@ -561,7 +770,7 @@ static int gmc_v9_0_sw_init(void *handle
- 	case CHIP_RAVEN:
- 		adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
- 		if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
--			adev->vm_manager.vm_size = 1U << 18;
-+			adev->vm_manager.max_pfn = 1ULL << 36;
- 			adev->vm_manager.block_size = 9;
- 			adev->vm_manager.num_level = 3;
- 			amdgpu_vm_set_fragment_size(adev, 9);
-@@ -579,7 +788,7 @@ static int gmc_v9_0_sw_init(void *handle
- 		 * vm size is 256TB (48bit), maximum size of Vega10,
- 		 * block size 512 (9bit)
- 		 */
--		adev->vm_manager.vm_size = 1U << 18;
-+		adev->vm_manager.max_pfn = 1ULL << 36;
- 		adev->vm_manager.block_size = 9;
- 		adev->vm_manager.num_level = 3;
- 		amdgpu_vm_set_fragment_size(adev, 9);
-@@ -588,10 +797,9 @@ static int gmc_v9_0_sw_init(void *handle
- 		break;
- 	}
- 
--	DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n",
--			adev->vm_manager.vm_size,
--			adev->vm_manager.block_size,
--			adev->vm_manager.fragment_size);
-+	DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
-+		 adev->vm_manager.max_pfn >> 18, adev->vm_manager.block_size,
-+		 adev->vm_manager.fragment_size);
- 
- 	/* This interrupt is VMC page fault.*/
- 	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
-@@ -602,8 +810,6 @@ static int gmc_v9_0_sw_init(void *handle
- 	if (r)
- 		return r;
- 
--	adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
--
- 	/* Set the internal MC address mask
- 	 * This is the max address of the GPU's
- 	 * internal address space.
-@@ -663,7 +869,7 @@ static int gmc_v9_0_sw_init(void *handle
- }
- 
- /**
-- * gmc_v8_0_gart_fini - vm fini callback
-+ * gmc_v9_0_gart_fini - vm fini callback
-  *
-  * @adev: amdgpu_device pointer
-  *
-@@ -679,9 +885,9 @@ static int gmc_v9_0_sw_fini(void *handle
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
-+	amdgpu_gem_force_release(adev);
- 	amdgpu_vm_manager_fini(adev);
- 	gmc_v9_0_gart_fini(adev);
--	amdgpu_gem_force_release(adev);
- 	amdgpu_bo_fini(adev);
- 
- 	return 0;
-@@ -691,8 +897,17 @@ static void gmc_v9_0_init_golden_registe
- {
- 	switch (adev->asic_type) {
- 	case CHIP_VEGA10:
-+		amdgpu_program_register_sequence(adev,
-+						golden_settings_mmhub_1_0_0,
-+						ARRAY_SIZE(golden_settings_mmhub_1_0_0));
-+		amdgpu_program_register_sequence(adev,
-+						golden_settings_athub_1_0_0,
-+						ARRAY_SIZE(golden_settings_athub_1_0_0));
- 		break;
- 	case CHIP_RAVEN:
-+		amdgpu_program_register_sequence(adev,
-+						golden_settings_athub_1_0_0,
-+						ARRAY_SIZE(golden_settings_athub_1_0_0));
- 		break;
- 	default:
- 		break;
-@@ -712,21 +927,12 @@ static int gmc_v9_0_gart_enable(struct a
- 
- 	amdgpu_program_register_sequence(adev,
- 		golden_settings_vega10_hdp,
--		(const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
-+		ARRAY_SIZE(golden_settings_vega10_hdp));
- 
- 	if (adev->gart.robj == NULL) {
- 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
- 		return -EINVAL;
- 	}
--	r = amdgpu_gart_table_vram_pin(adev);
--	if (r)
--		return r;
--
--	/* After HDP is initialized, flush HDP.*/
--	if (adev->flags & AMD_IS_APU)
--		nbio_v7_0_hdp_flush(adev);
--	else
--		nbio_v6_1_hdp_flush(adev);
- 
- 	switch (adev->asic_type) {
- 	case CHIP_RAVEN:
-@@ -745,13 +951,16 @@ static int gmc_v9_0_gart_enable(struct a
- 	if (r)
- 		return r;
- 
--	tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
--	tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
--	WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
-+	WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
- 
- 	tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
- 	WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
- 
-+	/* After HDP is initialized, flush HDP.*/
-+	if (adev->flags & AMD_IS_APU)
-+		nbio_v7_0_hdp_flush(adev);
-+	else
-+		nbio_v6_1_hdp_flush(adev);
- 
- 	if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
- 		value = false;
-@@ -760,7 +969,6 @@ static int gmc_v9_0_gart_enable(struct a
- 
- 	gfxhub_v1_0_set_fault_enable_default(adev, value);
- 	mmhub_v1_0_set_fault_enable_default(adev, value);
--
- 	gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
- 
- 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
-@@ -779,17 +987,11 @@ static int gmc_v9_0_hw_init(void *handle
- 	gmc_v9_0_init_golden_registers(adev);
- 
- 	if (adev->mode_info.num_crtc) {
--		u32 tmp;
--
- 		/* Lockout access through VGA aperture*/
--		tmp = RREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL);
--		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
--		WREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL, tmp);
-+		WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
- 
- 		/* disable VGA render */
--		tmp = RREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL);
--		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
--		WREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL, tmp);
-+		WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
- 	}
- 
- 	r = gmc_v9_0_gart_enable(adev);
-@@ -808,7 +1010,6 @@ static void gmc_v9_0_gart_disable(struct
- {
- 	gfxhub_v1_0_gart_disable(adev);
- 	mmhub_v1_0_gart_disable(adev);
--	amdgpu_gart_table_vram_unpin(adev);
- }
- 
- static int gmc_v9_0_hw_fini(void *handle)
-@@ -831,9 +1032,7 @@ static int gmc_v9_0_suspend(void *handle
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	gmc_v9_0_hw_fini(adev);
--
--	return 0;
-+	return gmc_v9_0_hw_fini(adev);
- }
- 
- static int gmc_v9_0_resume(void *handle)
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/iceland_ih.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/iceland_ih.c	2017-12-14 06:39:58.389903549 +0100
-@@ -208,6 +208,34 @@ static u32 iceland_ih_get_wptr(struct am
- }
- 
- /**
-+ * iceland_ih_prescreen_iv - prescreen an interrupt vector
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Returns true if the interrupt vector should be further processed.
-+ */
-+static bool iceland_ih_prescreen_iv(struct amdgpu_device *adev)
-+{
-+	u32 ring_index = adev->irq.ih.rptr >> 2;
-+	u16 pasid;
-+
-+	switch (le32_to_cpu(adev->irq.ih.ring[ring_index]) & 0xff) {
-+	case 146:
-+	case 147:
-+		pasid = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]) >> 16;
-+		if (!pasid || amdgpu_vm_pasid_fault_credit(adev, pasid))
-+			return true;
-+		break;
-+	default:
-+		/* Not a VM fault */
-+		return true;
-+	}
-+
-+	adev->irq.ih.rptr += 16;
-+	return false;
-+}
-+
-+/**
-  * iceland_ih_decode_iv - decode an interrupt vector
-  *
-  * @adev: amdgpu_device pointer
-@@ -412,6 +440,7 @@ static const struct amd_ip_funcs iceland
- 
- static const struct amdgpu_ih_funcs iceland_ih_funcs = {
- 	.get_wptr = iceland_ih_get_wptr,
-+	.prescreen_iv = iceland_ih_prescreen_iv,
- 	.decode_iv = iceland_ih_decode_iv,
- 	.set_rptr = iceland_ih_set_rptr
- };
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/Kconfig.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/Kconfig	2017-12-14 06:39:58.389903549 +0100
-@@ -41,3 +41,4 @@ config DRM_AMDGPU_GART_DEBUGFS
- 	  pages. Uses more memory for housekeeping, enable only for debugging.
- 
- source "drivers/gpu/drm/amd/acp/Kconfig"
-+source "drivers/gpu/drm/amd/display/Kconfig"
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/kv_dpm.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/kv_dpm.c	2017-12-14 06:39:58.390903550 +0100
-@@ -42,7 +42,6 @@
- #define KV_MINIMUM_ENGINE_CLOCK         800
- #define SMC_RAM_END                     0x40000
- 
--static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev);
- static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
- static int kv_enable_nb_dpm(struct amdgpu_device *adev,
- 			    bool enable);
-@@ -64,7 +63,7 @@ static int kv_set_thermal_temperature_ra
- 					    int min_temp, int max_temp);
- static int kv_init_fps_limits(struct amdgpu_device *adev);
- 
--static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
-+static void kv_dpm_powergate_uvd(void *handle, bool gate);
- static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
- static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
- static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
-@@ -1245,8 +1244,9 @@ static void kv_update_requested_ps(struc
- 	adev->pm.dpm.requested_ps = &pi->requested_rps;
- }
- 
--static void kv_dpm_enable_bapm(struct amdgpu_device *adev, bool enable)
-+static void kv_dpm_enable_bapm(void *handle, bool enable)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct kv_power_info *pi = kv_get_pi(adev);
- 	int ret;
- 
-@@ -1672,8 +1672,9 @@ static int kv_update_acp_dpm(struct amdg
- 	return kv_enable_acp_dpm(adev, !gate);
- }
- 
--static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
-+static void kv_dpm_powergate_uvd(void *handle, bool gate)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct kv_power_info *pi = kv_get_pi(adev);
- 	int ret;
- 
-@@ -1868,10 +1869,11 @@ static int kv_enable_nb_dpm(struct amdgp
- 	return ret;
- }
- 
--static int kv_dpm_force_performance_level(struct amdgpu_device *adev,
-+static int kv_dpm_force_performance_level(void *handle,
- 					  enum amd_dpm_forced_level level)
- {
- 	int ret;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
- 		ret = kv_force_dpm_highest(adev);
-@@ -1892,8 +1894,9 @@ static int kv_dpm_force_performance_leve
- 	return 0;
- }
- 
--static int kv_dpm_pre_set_power_state(struct amdgpu_device *adev)
-+static int kv_dpm_pre_set_power_state(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct kv_power_info *pi = kv_get_pi(adev);
- 	struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
- 	struct amdgpu_ps *new_ps = &requested_ps;
-@@ -1907,8 +1910,9 @@ static int kv_dpm_pre_set_power_state(st
- 	return 0;
- }
- 
--static int kv_dpm_set_power_state(struct amdgpu_device *adev)
-+static int kv_dpm_set_power_state(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct kv_power_info *pi = kv_get_pi(adev);
- 	struct amdgpu_ps *new_ps = &pi->requested_rps;
- 	struct amdgpu_ps *old_ps = &pi->current_rps;
-@@ -1981,8 +1985,9 @@ static int kv_dpm_set_power_state(struct
- 	return 0;
- }
- 
--static void kv_dpm_post_set_power_state(struct amdgpu_device *adev)
-+static void kv_dpm_post_set_power_state(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct kv_power_info *pi = kv_get_pi(adev);
- 	struct amdgpu_ps *new_ps = &pi->requested_rps;
- 
-@@ -2848,9 +2853,10 @@ static int kv_dpm_init(struct amdgpu_dev
- }
- 
- static void
--kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
-+kv_dpm_debugfs_print_current_performance_level(void *handle,
- 					       struct seq_file *m)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct kv_power_info *pi = kv_get_pi(adev);
- 	u32 current_index =
- 		(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
-@@ -2875,11 +2881,12 @@ kv_dpm_debugfs_print_current_performance
- }
- 
- static void
--kv_dpm_print_power_state(struct amdgpu_device *adev,
--			 struct amdgpu_ps *rps)
-+kv_dpm_print_power_state(void *handle, void *request_ps)
- {
- 	int i;
-+	struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
- 	struct kv_ps *ps = kv_get_ps(rps);
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	amdgpu_dpm_print_class_info(rps->class, rps->class2);
- 	amdgpu_dpm_print_cap_info(rps->caps);
-@@ -2905,13 +2912,14 @@ static void kv_dpm_fini(struct amdgpu_de
- 	amdgpu_free_extended_power_table(adev);
- }
- 
--static void kv_dpm_display_configuration_changed(struct amdgpu_device *adev)
-+static void kv_dpm_display_configuration_changed(void *handle)
- {
- 
- }
- 
--static u32 kv_dpm_get_sclk(struct amdgpu_device *adev, bool low)
-+static u32 kv_dpm_get_sclk(void *handle, bool low)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct kv_power_info *pi = kv_get_pi(adev);
- 	struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
- 
-@@ -2921,18 +2929,20 @@ static u32 kv_dpm_get_sclk(struct amdgpu
- 		return requested_state->levels[requested_state->num_levels - 1].sclk;
- }
- 
--static u32 kv_dpm_get_mclk(struct amdgpu_device *adev, bool low)
-+static u32 kv_dpm_get_mclk(void *handle, bool low)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct kv_power_info *pi = kv_get_pi(adev);
- 
- 	return pi->sys_info.bootup_uma_clk;
- }
- 
- /* get temperature in millidegrees */
--static int kv_dpm_get_temp(struct amdgpu_device *adev)
-+static int kv_dpm_get_temp(void *handle)
- {
- 	u32 temp;
- 	int actual_temp = 0;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	temp = RREG32_SMC(0xC0300E0C);
- 
-@@ -2950,7 +2960,6 @@ static int kv_dpm_early_init(void *handl
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	kv_dpm_set_dpm_funcs(adev);
- 	kv_dpm_set_irq_funcs(adev);
- 
- 	return 0;
-@@ -2960,16 +2969,10 @@ static int kv_dpm_late_init(void *handle
- {
- 	/* powerdown unused blocks for now */
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--	int ret;
- 
- 	if (!amdgpu_dpm)
- 		return 0;
- 
--	/* init the sysfs and debugfs files late */
--	ret = amdgpu_pm_sysfs_init(adev);
--	if (ret)
--		return ret;
--
- 	kv_dpm_powergate_acp(adev, true);
- 	kv_dpm_powergate_samu(adev, true);
- 
-@@ -3031,7 +3034,6 @@ static int kv_dpm_sw_fini(void *handle)
- 	flush_work(&adev->pm.dpm.thermal.work);
- 
- 	mutex_lock(&adev->pm.mutex);
--	amdgpu_pm_sysfs_fini(adev);
- 	kv_dpm_fini(adev);
- 	mutex_unlock(&adev->pm.mutex);
- 
-@@ -3222,14 +3224,17 @@ static inline bool kv_are_power_levels_e
- 		  (kv_cpl1->force_nbp_state == kv_cpl2->force_nbp_state));
- }
- 
--static int kv_check_state_equal(struct amdgpu_device *adev,
--				struct amdgpu_ps *cps,
--				struct amdgpu_ps *rps,
-+static int kv_check_state_equal(void *handle,
-+				void *current_ps,
-+				void *request_ps,
- 				bool *equal)
- {
- 	struct kv_ps *kv_cps;
- 	struct kv_ps *kv_rps;
- 	int i;
-+	struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
-+	struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
- 		return -EINVAL;
-@@ -3262,9 +3267,10 @@ static int kv_check_state_equal(struct a
- 	return 0;
- }
- 
--static int kv_dpm_read_sensor(struct amdgpu_device *adev, int idx,
-+static int kv_dpm_read_sensor(void *handle, int idx,
- 			      void *value, int *size)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct kv_power_info *pi = kv_get_pi(adev);
- 	uint32_t sclk;
- 	u32 pl_index =
-@@ -3312,7 +3318,7 @@ const struct amd_ip_funcs kv_dpm_ip_func
- 	.set_powergating_state = kv_dpm_set_powergating_state,
- };
- 
--static const struct amdgpu_dpm_funcs kv_dpm_funcs = {
-+const struct amd_pm_funcs kv_dpm_funcs = {
- 	.get_temperature = &kv_dpm_get_temp,
- 	.pre_set_power_state = &kv_dpm_pre_set_power_state,
- 	.set_power_state = &kv_dpm_set_power_state,
-@@ -3330,12 +3336,6 @@ static const struct amdgpu_dpm_funcs kv_
- 	.read_sensor = &kv_dpm_read_sensor,
- };
- 
--static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev)
--{
--	if (adev->pm.funcs == NULL)
--		adev->pm.funcs = &kv_dpm_funcs;
--}
--
- static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = {
- 	.set = kv_dpm_set_interrupt_state,
- 	.process = kv_dpm_process_interrupt,
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/Makefile	2017-12-14 06:39:58.390903550 +0100
-@@ -4,13 +4,19 @@
- # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
- 
- FULL_AMD_PATH=$(src)/..
-+DISPLAY_FOLDER_NAME=display
-+FULL_AMD_DISPLAY_PATH = $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME)
- 
- ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \
- 	-I$(FULL_AMD_PATH)/include \
- 	-I$(FULL_AMD_PATH)/amdgpu \
- 	-I$(FULL_AMD_PATH)/scheduler \
- 	-I$(FULL_AMD_PATH)/powerplay/inc \
--	-I$(FULL_AMD_PATH)/acp/include
-+	-I$(FULL_AMD_PATH)/acp/include \
-+	-I$(FULL_AMD_DISPLAY_PATH) \
-+	-I$(FULL_AMD_DISPLAY_PATH)/include \
-+	-I$(FULL_AMD_DISPLAY_PATH)/dc \
-+	-I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm
- 
- amdgpu-y := amdgpu_drv.o
- 
-@@ -26,7 +32,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o
- 	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
- 	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
- 	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
--	amdgpu_queue_mgr.o amdgpu_vf_error.o
-+	amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o
- 
- # add asic specific block
- amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
-@@ -133,6 +139,13 @@ include $(FULL_AMD_PATH)/powerplay/Makef
- 
- amdgpu-y += $(AMD_POWERPLAY_FILES)
- 
--obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o
-+ifneq ($(CONFIG_DRM_AMD_DC),)
-+
-+RELATIVE_AMD_DISPLAY_PATH = ../$(DISPLAY_FOLDER_NAME)
-+include $(FULL_AMD_DISPLAY_PATH)/Makefile
-+
-+amdgpu-y += $(AMD_DISPLAY_FILES)
- 
--CFLAGS_amdgpu_trace_points.o := -I$(src)
-+endif
-+
-+obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c	2017-12-14 06:39:58.390903550 +0100
-@@ -273,7 +273,7 @@ static const struct pctl_data pctl0_data
- 	{0x135, 0x12a810},
- 	{0x149, 0x7a82c}
- };
--#define PCTL0_DATA_LEN (sizeof(pctl0_data)/sizeof(pctl0_data[0]))
-+#define PCTL0_DATA_LEN (ARRAY_SIZE(pctl0_data))
- 
- #define PCTL0_RENG_EXEC_END_PTR 0x151
- #define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE  0xa640
-@@ -309,7 +309,7 @@ static const struct pctl_data pctl1_data
- 	{0x1f0, 0x5000a7f6},
- 	{0x1f1, 0x5000a7e4}
- };
--#define PCTL1_DATA_LEN (sizeof(pctl1_data)/sizeof(pctl1_data[0]))
-+#define PCTL1_DATA_LEN (ARRAY_SIZE(pctl1_data))
- 
- #define PCTL1_RENG_EXEC_END_PTR 0x1f1
- #define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE  0xa000
-@@ -561,6 +561,13 @@ void mmhub_v1_0_set_fault_enable_default
- 			WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
- 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
- 			EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
-+	if (!value) {
-+		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
-+				CRASH_ON_NO_RETRY_FAULT, 1);
-+		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
-+				CRASH_ON_RETRY_FAULT, 1);
-+    }
-+
- 	WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
- }
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c	2017-12-14 06:39:58.390903550 +0100
-@@ -183,6 +183,12 @@ static int xgpu_ai_send_access_requests(
- 			pr_err("Doesn't get READY_TO_ACCESS_GPU from pf, give up\n");
- 			return r;
- 		}
-+		/* Retrieve checksum from mailbox2 */
-+		if (req == IDH_REQ_GPU_INIT_ACCESS) {
-+			adev->virt.fw_reserve.checksum_key =
-+				RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
-+					mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2));
-+		}
- 	}
- 
- 	return 0;
-@@ -248,7 +254,7 @@ static void xgpu_ai_mailbox_flr_work(str
- 	}
- 
- 	/* Trigger recovery due to world switch failure */
--	amdgpu_sriov_gpu_reset(adev, NULL);
-+	amdgpu_gpu_recover(adev, NULL);
- }
- 
- static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,
-@@ -276,9 +282,17 @@ static int xgpu_ai_mailbox_rcv_irq(struc
- 		/* see what event we get */
- 		r = xgpu_ai_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
- 
--		/* only handle FLR_NOTIFY now */
--		if (!r)
--			schedule_work(&adev->virt.flr_work);
-+		/* sometimes the interrupt is delayed to inject to VM, so under such case
-+		 * the IDH_FLR_NOTIFICATION is overwritten by VF FLR from GIM side, thus
-+		 * above recieve message could be failed, we should schedule the flr_work
-+		 * anyway
-+		 */
-+		if (r) {
-+			DRM_ERROR("FLR_NOTIFICATION is missed\n");
-+			xgpu_ai_mailbox_send_ack(adev);
-+		}
-+
-+		schedule_work(&adev->virt.flr_work);
- 	}
- 
- 	return 0;
-@@ -347,5 +361,6 @@ const struct amdgpu_virt_ops xgpu_ai_vir
- 	.req_full_gpu	= xgpu_ai_request_full_gpu_access,
- 	.rel_full_gpu	= xgpu_ai_release_full_gpu_access,
- 	.reset_gpu = xgpu_ai_request_reset,
-+	.wait_reset = NULL,
- 	.trans_msg = xgpu_ai_mailbox_trans_msg,
- };
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h	2017-12-14 06:39:58.390903550 +0100
-@@ -24,7 +24,7 @@
- #ifndef __MXGPU_AI_H__
- #define __MXGPU_AI_H__
- 
--#define AI_MAILBOX_TIMEDOUT	5000
-+#define AI_MAILBOX_TIMEDOUT	12000
- 
- enum idh_request {
- 	IDH_REQ_GPU_INIT_ACCESS = 1,
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c	2017-12-14 06:39:58.390903550 +0100
-@@ -281,29 +281,29 @@ void xgpu_vi_init_golden_registers(struc
- 	case CHIP_FIJI:
- 		amdgpu_program_register_sequence(adev,
- 						 xgpu_fiji_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(
-+						 ARRAY_SIZE(
- 						 xgpu_fiji_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 xgpu_fiji_golden_settings_a10,
--						 (const u32)ARRAY_SIZE(
-+						 ARRAY_SIZE(
- 						 xgpu_fiji_golden_settings_a10));
- 		amdgpu_program_register_sequence(adev,
- 						 xgpu_fiji_golden_common_all,
--						 (const u32)ARRAY_SIZE(
-+						 ARRAY_SIZE(
- 						 xgpu_fiji_golden_common_all));
- 		break;
- 	case CHIP_TONGA:
- 		amdgpu_program_register_sequence(adev,
- 						 xgpu_tonga_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(
-+						 ARRAY_SIZE(
- 						 xgpu_tonga_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 xgpu_tonga_golden_settings_a11,
--						 (const u32)ARRAY_SIZE(
-+						 ARRAY_SIZE(
- 						 xgpu_tonga_golden_settings_a11));
- 		amdgpu_program_register_sequence(adev,
- 						 xgpu_tonga_golden_common_all,
--						 (const u32)ARRAY_SIZE(
-+						 ARRAY_SIZE(
- 						 xgpu_tonga_golden_common_all));
- 		break;
- 	default:
-@@ -446,8 +446,10 @@ static int xgpu_vi_send_access_requests(
- 		request == IDH_REQ_GPU_FINI_ACCESS ||
- 		request == IDH_REQ_GPU_RESET_ACCESS) {
- 		r = xgpu_vi_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);
--		if (r)
--			pr_err("Doesn't get ack from pf, continue\n");
-+		if (r) {
-+			pr_err("Doesn't get ack from pf, give up\n");
-+			return r;
-+		}
- 	}
- 
- 	return 0;
-@@ -458,6 +460,11 @@ static int xgpu_vi_request_reset(struct
- 	return xgpu_vi_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
- }
- 
-+static int xgpu_vi_wait_reset_cmpl(struct amdgpu_device *adev)
-+{
-+	return xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL);
-+}
-+
- static int xgpu_vi_request_full_gpu_access(struct amdgpu_device *adev,
- 					   bool init)
- {
-@@ -514,7 +521,7 @@ static void xgpu_vi_mailbox_flr_work(str
- 	}
- 
- 	/* Trigger recovery due to world switch failure */
--	amdgpu_sriov_gpu_reset(adev, NULL);
-+	amdgpu_gpu_recover(adev, NULL);
- }
- 
- static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev,
-@@ -613,5 +620,6 @@ const struct amdgpu_virt_ops xgpu_vi_vir
- 	.req_full_gpu		= xgpu_vi_request_full_gpu_access,
- 	.rel_full_gpu		= xgpu_vi_release_full_gpu_access,
- 	.reset_gpu		= xgpu_vi_request_reset,
-+	.wait_reset             = xgpu_vi_wait_reset_cmpl,
- 	.trans_msg		= NULL, /* Does not need to trans VF errors to host. */
- };
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h	2017-12-14 06:39:58.390903550 +0100
-@@ -23,7 +23,7 @@
- #ifndef __MXGPU_VI_H__
- #define __MXGPU_VI_H__
- 
--#define VI_MAILBOX_TIMEDOUT	5000
-+#define VI_MAILBOX_TIMEDOUT	12000
- #define VI_MAILBOX_RESET_TIME	12
- 
- /* VI mailbox messages request */
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c	2017-12-14 06:39:58.390903550 +0100
-@@ -215,31 +215,27 @@ void nbio_v6_1_get_clockgating_state(str
- 		*flags |= AMD_CG_SUPPORT_BIF_LS;
- }
- 
--struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
--struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
-+const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
-+	.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ),
-+	.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE),
-+	.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
-+	.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
-+	.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
-+	.ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
-+	.ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
-+	.ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
-+	.ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
-+	.ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
-+	.ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
-+	.ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
-+	.ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
-+	.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
-+};
- 
--int nbio_v6_1_init(struct amdgpu_device *adev)
--{
--	nbio_v6_1_hdp_flush_reg.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
--	nbio_v6_1_hdp_flush_reg.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
--	nbio_v6_1_hdp_flush_reg.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK;
--	nbio_v6_1_hdp_flush_reg.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK;
--	nbio_v6_1_hdp_flush_reg.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK;
--	nbio_v6_1_hdp_flush_reg.ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK;
--	nbio_v6_1_hdp_flush_reg.ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK;
--	nbio_v6_1_hdp_flush_reg.ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK;
--	nbio_v6_1_hdp_flush_reg.ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK;
--	nbio_v6_1_hdp_flush_reg.ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK;
--	nbio_v6_1_hdp_flush_reg.ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK;
--	nbio_v6_1_hdp_flush_reg.ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK;
--	nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK;
--	nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK;
--
--	nbio_v6_1_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX);
--	nbio_v6_1_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA);
--
--	return 0;
--}
-+const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data = {
-+	.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX),
-+	.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA),
-+};
- 
- void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
- {
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h	2017-12-14 06:39:58.390903550 +0100
-@@ -26,8 +26,8 @@
- 
- #include "soc15_common.h"
- 
--extern struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
--extern struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
-+extern const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
-+extern const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
- int nbio_v6_1_init(struct amdgpu_device *adev);
- u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,
-                                         uint32_t idx);
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c	2017-12-14 06:39:58.390903550 +0100
-@@ -185,28 +185,24 @@ void nbio_v7_0_ih_control(struct amdgpu_
- 	WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
- }
- 
--struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
--struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
-+const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
-+	.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ),
-+	.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE),
-+	.ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
-+	.ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
-+	.ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
-+	.ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
-+	.ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
-+	.ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
-+	.ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
-+	.ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
-+	.ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
-+	.ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
-+	.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
-+	.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
-+};
- 
--int nbio_v7_0_init(struct amdgpu_device *adev)
--{
--	nbio_v7_0_hdp_flush_reg.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
--	nbio_v7_0_hdp_flush_reg.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
--	nbio_v7_0_hdp_flush_reg.ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK;
--	nbio_v7_0_hdp_flush_reg.ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK;
--	nbio_v7_0_hdp_flush_reg.ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK;
--	nbio_v7_0_hdp_flush_reg.ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK;
--	nbio_v7_0_hdp_flush_reg.ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK;
--	nbio_v7_0_hdp_flush_reg.ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK;
--	nbio_v7_0_hdp_flush_reg.ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK;
--	nbio_v7_0_hdp_flush_reg.ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK;
--	nbio_v7_0_hdp_flush_reg.ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK;
--	nbio_v7_0_hdp_flush_reg.ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK;
--	nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
--	nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
--
--	nbio_v7_0_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
--	nbio_v7_0_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
--
--	return 0;
--}
-+const struct nbio_pcie_index_data nbio_v7_0_pcie_index_data = {
-+	.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2),
-+	.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2)
-+};
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h	2017-12-14 06:39:58.391903551 +0100
-@@ -26,8 +26,8 @@
- 
- #include "soc15_common.h"
- 
--extern struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
--extern struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
-+extern const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
-+extern const struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
- int nbio_v7_0_init(struct amdgpu_device *adev);
- u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev,
-                                         uint32_t idx);
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c	2017-12-14 06:39:58.391903551 +0100
-@@ -35,6 +35,8 @@
- #include "raven1/GC/gc_9_1_offset.h"
- #include "raven1/SDMA0/sdma0_4_1_offset.h"
- 
-+MODULE_FIRMWARE("amdgpu/raven_asd.bin");
-+
- static int
- psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
- {
-@@ -136,15 +138,13 @@ int psp_v10_0_prep_cmd_buf(struct amdgpu
- {
- 	int ret;
- 	uint64_t fw_mem_mc_addr = ucode->mc_addr;
--	struct  common_firmware_header *header;
- 
- 	memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
--	header = (struct common_firmware_header *)ucode->fw;
- 
- 	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
- 	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
- 	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
--	cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes);
-+	cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
- 
- 	ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
- 	if (ret)
-@@ -209,7 +209,7 @@ int psp_v10_0_ring_create(struct psp_con
- 	return ret;
- }
- 
--int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
-+int psp_v10_0_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
- {
- 	int ret = 0;
- 	struct psp_ring *ring;
-@@ -229,6 +229,19 @@ int psp_v10_0_ring_destroy(struct psp_co
- 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
- 			   0x80000000, 0x80000000, false);
- 
-+	return ret;
-+}
-+
-+int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
-+{
-+	int ret = 0;
-+	struct psp_ring *ring = &psp->km_ring;
-+	struct amdgpu_device *adev = psp->adev;
-+
-+	ret = psp_v10_0_ring_stop(psp, ring_type);
-+	if (ret)
-+		DRM_ERROR("Fail to stop psp ring\n");
-+
- 	amdgpu_bo_free_kernel(&adev->firmware.rbuf,
- 			      &ring->ring_mem_mc_addr,
- 			      (void **)&ring->ring_mem);
-@@ -244,16 +257,31 @@ int psp_v10_0_cmd_submit(struct psp_cont
- 	unsigned int psp_write_ptr_reg = 0;
- 	struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
- 	struct psp_ring *ring = &psp->km_ring;
-+	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
-+	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
-+		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
- 	struct amdgpu_device *adev = psp->adev;
-+	uint32_t ring_size_dw = ring->ring_size / 4;
-+	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
- 
- 	/* KM (GPCOM) prepare write pointer */
- 	psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
- 
- 	/* Update KM RB frame pointer to new frame */
--	if ((psp_write_ptr_reg % ring->ring_size) == 0)
--		write_frame = ring->ring_mem;
-+	if ((psp_write_ptr_reg % ring_size_dw) == 0)
-+		write_frame = ring_buffer_start;
- 	else
--		write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4));
-+		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
-+	/* Check invalid write_frame ptr address */
-+	if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
-+		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
-+			  ring_buffer_start, ring_buffer_end, write_frame);
-+		DRM_ERROR("write_frame is pointing to address out of bounds\n");
-+		return -EINVAL;
-+	}
-+
-+	/* Initialize KM RB frame */
-+	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
- 
- 	/* Update KM RB frame */
- 	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
-@@ -263,8 +291,7 @@ int psp_v10_0_cmd_submit(struct psp_cont
- 	write_frame->fence_value = index;
- 
- 	/* Update the write Pointer in DWORDs */
--	psp_write_ptr_reg += sizeof(struct psp_gfx_rb_frame) / 4;
--	psp_write_ptr_reg = (psp_write_ptr_reg >= ring->ring_size) ? 0 : psp_write_ptr_reg;
-+	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
- 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
- 
- 	return 0;
-@@ -390,3 +417,10 @@ bool psp_v10_0_compare_sram_data(struct
- 
- 	return true;
- }
-+
-+
-+int psp_v10_0_mode1_reset(struct psp_context *psp)
-+{
-+	DRM_INFO("psp mode 1 reset not supported now! \n");
-+	return -EINVAL;
-+}
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h	2017-12-14 06:39:58.391903551 +0100
-@@ -34,6 +34,8 @@ extern int psp_v10_0_ring_init(struct ps
- 			      enum psp_ring_type ring_type);
- extern int psp_v10_0_ring_create(struct psp_context *psp,
- 				 enum psp_ring_type ring_type);
-+extern int psp_v10_0_ring_stop(struct psp_context *psp,
-+				  enum psp_ring_type ring_type);
- extern int psp_v10_0_ring_destroy(struct psp_context *psp,
- 				  enum psp_ring_type ring_type);
- extern int psp_v10_0_cmd_submit(struct psp_context *psp,
-@@ -43,4 +45,6 @@ extern int psp_v10_0_cmd_submit(struct p
- extern bool psp_v10_0_compare_sram_data(struct psp_context *psp,
- 				       struct amdgpu_firmware_info *ucode,
- 				       enum AMDGPU_UCODE_ID ucode_type);
-+
-+extern int psp_v10_0_mode1_reset(struct psp_context *psp);
- #endif
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c	2017-12-14 06:39:58.391903551 +0100
-@@ -319,7 +319,7 @@ int psp_v3_1_ring_create(struct psp_cont
- 	return ret;
- }
- 
--int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
-+int psp_v3_1_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
- {
- 	int ret = 0;
- 	struct psp_ring *ring;
-@@ -339,6 +339,19 @@ int psp_v3_1_ring_destroy(struct psp_con
- 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
- 			   0x80000000, 0x80000000, false);
- 
-+	return ret;
-+}
-+
-+int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
-+{
-+	int ret = 0;
-+	struct psp_ring *ring = &psp->km_ring;
-+	struct amdgpu_device *adev = psp->adev;
-+
-+	ret = psp_v3_1_ring_stop(psp, ring_type);
-+	if (ret)
-+		DRM_ERROR("Fail to stop psp ring\n");
-+
- 	amdgpu_bo_free_kernel(&adev->firmware.rbuf,
- 			      &ring->ring_mem_mc_addr,
- 			      (void **)&ring->ring_mem);
-@@ -354,6 +367,9 @@ int psp_v3_1_cmd_submit(struct psp_conte
- 	unsigned int psp_write_ptr_reg = 0;
- 	struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
- 	struct psp_ring *ring = &psp->km_ring;
-+	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
-+	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
-+		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
- 	struct amdgpu_device *adev = psp->adev;
- 	uint32_t ring_size_dw = ring->ring_size / 4;
- 	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
-@@ -365,9 +381,16 @@ int psp_v3_1_cmd_submit(struct psp_conte
- 	/* write_frame ptr increments by size of rb_frame in bytes */
- 	/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
- 	if ((psp_write_ptr_reg % ring_size_dw) == 0)
--		write_frame = ring->ring_mem;
-+		write_frame = ring_buffer_start;
- 	else
--		write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw);
-+		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
-+	/* Check invalid write_frame ptr address */
-+	if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
-+		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
-+			  ring_buffer_start, ring_buffer_end, write_frame);
-+		DRM_ERROR("write_frame is pointing to address out of bounds\n");
-+		return -EINVAL;
-+	}
- 
- 	/* Initialize KM RB frame */
- 	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
-@@ -517,3 +540,37 @@ bool psp_v3_1_smu_reload_quirk(struct ps
- 	reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2);
- 	return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
- }
-+
-+int psp_v3_1_mode1_reset(struct psp_context *psp)
-+{
-+	int ret;
-+	uint32_t offset;
-+	struct amdgpu_device *adev = psp->adev;
-+
-+	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
-+
-+	ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
-+
-+	if (ret) {
-+		DRM_INFO("psp is not working correctly before mode1 reset!\n");
-+		return -EINVAL;
-+	}
-+
-+	/*send the mode 1 reset command*/
-+	WREG32(offset, 0x70000);
-+
-+	mdelay(1000);
-+
-+	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
-+
-+	ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
-+
-+	if (ret) {
-+		DRM_INFO("psp mode 1 reset failed!\n");
-+		return -EINVAL;
-+	}
-+
-+	DRM_INFO("psp mode1 reset succeed \n");
-+
-+	return 0;
-+}
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h	2017-12-14 06:39:58.391903551 +0100
-@@ -41,6 +41,8 @@ extern int psp_v3_1_ring_init(struct psp
- 			      enum psp_ring_type ring_type);
- extern int psp_v3_1_ring_create(struct psp_context *psp,
- 				enum psp_ring_type ring_type);
-+extern int psp_v3_1_ring_stop(struct psp_context *psp,
-+				enum psp_ring_type ring_type);
- extern int psp_v3_1_ring_destroy(struct psp_context *psp,
- 				enum psp_ring_type ring_type);
- extern int psp_v3_1_cmd_submit(struct psp_context *psp,
-@@ -51,4 +53,5 @@ extern bool psp_v3_1_compare_sram_data(s
- 				       struct amdgpu_firmware_info *ucode,
- 				       enum AMDGPU_UCODE_ID ucode_type);
- extern bool psp_v3_1_smu_reload_quirk(struct psp_context *psp);
-+extern int psp_v3_1_mode1_reset(struct psp_context *psp);
- #endif
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c	2017-12-14 06:39:58.391903551 +0100
-@@ -95,10 +95,10 @@ static void sdma_v2_4_init_golden_regist
- 	case CHIP_TOPAZ:
- 		amdgpu_program_register_sequence(adev,
- 						 iceland_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
-+						 ARRAY_SIZE(iceland_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_iceland_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
-+						 ARRAY_SIZE(golden_settings_iceland_a11));
- 		break;
- 	default:
- 		break;
-@@ -561,21 +561,11 @@ static int sdma_v2_4_start(struct amdgpu
- {
- 	int r;
- 
--	if (!adev->pp_enabled) {
--		if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
--			r = sdma_v2_4_load_microcode(adev);
--			if (r)
--				return r;
--		} else {
--			r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--							AMDGPU_UCODE_ID_SDMA0);
--			if (r)
--				return -EINVAL;
--			r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--							AMDGPU_UCODE_ID_SDMA1);
--			if (r)
--				return -EINVAL;
--		}
-+
-+	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
-+		r = sdma_v2_4_load_microcode(adev);
-+		if (r)
-+			return r;
- 	}
- 
- 	/* halt the engine before programing */
-@@ -643,7 +633,7 @@ static int sdma_v2_4_ring_test_ring(stru
- 	}
- 
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
- 			  ring->idx, tmp);
-@@ -714,7 +704,7 @@ static int sdma_v2_4_ring_test_ib(struct
- 	}
- 	tmp = le32_to_cpu(adev->wb.wb[index]);
- 	if (tmp == 0xDEADBEEF) {
--		DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
-+		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
- 		r = 0;
- 	} else {
- 		DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
-@@ -1324,8 +1314,13 @@ static void sdma_v2_4_set_buffer_funcs(s
- }
- 
- static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
-+	.copy_pte_num_dw = 7,
- 	.copy_pte = sdma_v2_4_vm_copy_pte,
-+
- 	.write_pte = sdma_v2_4_vm_write_pte,
-+
-+	.set_max_nums_pte_pde = 0x1fffff >> 3,
-+	.set_pte_pde_num_dw = 10,
- 	.set_pte_pde = sdma_v2_4_vm_set_pte_pde,
- };
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c	2017-12-14 06:39:58.391903551 +0100
-@@ -194,45 +194,45 @@ static void sdma_v3_0_init_golden_regist
- 	case CHIP_FIJI:
- 		amdgpu_program_register_sequence(adev,
- 						 fiji_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
-+						 ARRAY_SIZE(fiji_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_fiji_a10,
--						 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
-+						 ARRAY_SIZE(golden_settings_fiji_a10));
- 		break;
- 	case CHIP_TONGA:
- 		amdgpu_program_register_sequence(adev,
- 						 tonga_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
-+						 ARRAY_SIZE(tonga_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_tonga_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
-+						 ARRAY_SIZE(golden_settings_tonga_a11));
- 		break;
- 	case CHIP_POLARIS11:
- 	case CHIP_POLARIS12:
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_polaris11_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
-+						 ARRAY_SIZE(golden_settings_polaris11_a11));
- 		break;
- 	case CHIP_POLARIS10:
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_polaris10_a11,
--						 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
-+						 ARRAY_SIZE(golden_settings_polaris10_a11));
- 		break;
- 	case CHIP_CARRIZO:
- 		amdgpu_program_register_sequence(adev,
- 						 cz_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
-+						 ARRAY_SIZE(cz_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 cz_golden_settings_a11,
--						 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
-+						 ARRAY_SIZE(cz_golden_settings_a11));
- 		break;
- 	case CHIP_STONEY:
- 		amdgpu_program_register_sequence(adev,
- 						 stoney_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
-+						 ARRAY_SIZE(stoney_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 stoney_golden_settings_a11,
--						 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
-+						 ARRAY_SIZE(stoney_golden_settings_a11));
- 		break;
- 	default:
- 		break;
-@@ -379,8 +379,10 @@ static void sdma_v3_0_ring_set_wptr(stru
- 	struct amdgpu_device *adev = ring->adev;
- 
- 	if (ring->use_doorbell) {
-+		u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
-+
- 		/* XXX check if swapping is necessary on BE */
--		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr) << 2;
-+		WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
- 		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
- 	} else {
- 		int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
-@@ -641,10 +643,11 @@ static void sdma_v3_0_enable(struct amdg
- static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
- {
- 	struct amdgpu_ring *ring;
--	u32 rb_cntl, ib_cntl;
-+	u32 rb_cntl, ib_cntl, wptr_poll_cntl;
- 	u32 rb_bufsz;
- 	u32 wb_offset;
- 	u32 doorbell;
-+	u64 wptr_gpu_addr;
- 	int i, j, r;
- 
- 	for (i = 0; i < adev->sdma.num_instances; i++) {
-@@ -707,6 +710,20 @@ static int sdma_v3_0_gfx_resume(struct a
- 		}
- 		WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
- 
-+		/* setup the wptr shadow polling */
-+		wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
-+
-+		WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
-+		       lower_32_bits(wptr_gpu_addr));
-+		WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
-+		       upper_32_bits(wptr_gpu_addr));
-+		wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
-+		if (amdgpu_sriov_vf(adev))
-+			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
-+		else
-+			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
-+		WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
-+
- 		/* enable DMA RB */
- 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
- 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
-@@ -802,23 +819,12 @@ static int sdma_v3_0_load_microcode(stru
-  */
- static int sdma_v3_0_start(struct amdgpu_device *adev)
- {
--	int r, i;
-+	int r;
- 
--	if (!adev->pp_enabled) {
--		if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) {
--			r = sdma_v3_0_load_microcode(adev);
--			if (r)
--				return r;
--		} else {
--			for (i = 0; i < adev->sdma.num_instances; i++) {
--				r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
--										 (i == 0) ?
--										 AMDGPU_UCODE_ID_SDMA0 :
--										 AMDGPU_UCODE_ID_SDMA1);
--				if (r)
--					return -EINVAL;
--			}
--		}
-+	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
-+		r = sdma_v3_0_load_microcode(adev);
-+		if (r)
-+			return r;
- 	}
- 
- 	/* disable sdma engine before programing it */
-@@ -887,7 +893,7 @@ static int sdma_v3_0_ring_test_ring(stru
- 	}
- 
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
- 			  ring->idx, tmp);
-@@ -958,7 +964,7 @@ static int sdma_v3_0_ring_test_ib(struct
- 	}
- 	tmp = le32_to_cpu(adev->wb.wb[index]);
- 	if (tmp == 0xDEADBEEF) {
--		DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
-+		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
- 		r = 0;
- 	} else {
- 		DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
-@@ -1713,11 +1719,11 @@ static void sdma_v3_0_emit_fill_buffer(s
- }
- 
- static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
--	.copy_max_bytes = 0x1fffff,
-+	.copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
- 	.copy_num_dw = 7,
- 	.emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
- 
--	.fill_max_bytes = 0x1fffff,
-+	.fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
- 	.fill_num_dw = 5,
- 	.emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
- };
-@@ -1731,8 +1737,14 @@ static void sdma_v3_0_set_buffer_funcs(s
- }
- 
- static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
-+	.copy_pte_num_dw = 7,
- 	.copy_pte = sdma_v3_0_vm_copy_pte,
-+
- 	.write_pte = sdma_v3_0_vm_write_pte,
-+
-+	/* not 0x3fffff due to HW limitation */
-+	.set_max_nums_pte_pde = 0x3fffe0 >> 3,
-+	.set_pte_pde_num_dw = 10,
- 	.set_pte_pde = sdma_v3_0_vm_set_pte_pde,
- };
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c	2017-12-14 06:39:58.391903551 +0100
-@@ -54,7 +54,7 @@ static void sdma_v4_0_set_vm_pte_funcs(s
- static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
- 
- static const u32 golden_settings_sdma_4[] = {
--	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
-+	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07,
- 	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100,
- 	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100,
- 	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
-@@ -89,7 +89,7 @@ static const u32 golden_settings_sdma_vg
- 
- static const u32 golden_settings_sdma_4_1[] =
- {
--	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
-+	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07,
- 	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xffffffff, 0x3f000100,
- 	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0111, 0x00000100,
- 	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
-@@ -132,18 +132,18 @@ static void sdma_v4_0_init_golden_regist
- 	case CHIP_VEGA10:
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_sdma_4,
--						 (const u32)ARRAY_SIZE(golden_settings_sdma_4));
-+						 ARRAY_SIZE(golden_settings_sdma_4));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_sdma_vg10,
--						 (const u32)ARRAY_SIZE(golden_settings_sdma_vg10));
-+						 ARRAY_SIZE(golden_settings_sdma_vg10));
- 		break;
- 	case CHIP_RAVEN:
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_sdma_4_1,
--						 (const u32)ARRAY_SIZE(golden_settings_sdma_4_1));
-+						 ARRAY_SIZE(golden_settings_sdma_4_1));
- 		amdgpu_program_register_sequence(adev,
- 						 golden_settings_sdma_rv1,
--						 (const u32)ARRAY_SIZE(golden_settings_sdma_rv1));
-+						 ARRAY_SIZE(golden_settings_sdma_rv1));
- 		break;
- 	default:
- 		break;
-@@ -371,7 +371,7 @@ static void sdma_v4_0_ring_emit_ib(struc
- static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
- {
- 	u32 ref_and_mask = 0;
--	struct nbio_hdp_flush_reg *nbio_hf_reg;
-+	const struct nbio_hdp_flush_reg *nbio_hf_reg;
- 
- 	if (ring->adev->flags & AMD_IS_APU)
- 		nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
-@@ -398,7 +398,7 @@ static void sdma_v4_0_ring_emit_hdp_inva
- {
- 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
- 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
--	amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0));
-+	amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE));
- 	amdgpu_ring_write(ring, 1);
- }
- 
-@@ -919,7 +919,7 @@ static int sdma_v4_0_ring_test_ring(stru
- 	}
- 
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
- 			  ring->idx, tmp);
-@@ -990,7 +990,7 @@ static int sdma_v4_0_ring_test_ib(struct
- 	}
- 	tmp = le32_to_cpu(adev->wb.wb[index]);
- 	if (tmp == 0xDEADBEEF) {
--		DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
-+		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
- 		r = 0;
- 	} else {
- 		DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
-@@ -1264,6 +1264,11 @@ static int sdma_v4_0_sw_fini(void *handl
- 	for (i = 0; i < adev->sdma.num_instances; i++)
- 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
- 
-+	for (i = 0; i < adev->sdma.num_instances; i++) {
-+		release_firmware(adev->sdma.instance[i].fw);
-+		adev->sdma.instance[i].fw = NULL;
-+	}
-+
- 	return 0;
- }
- 
-@@ -1714,8 +1719,13 @@ static void sdma_v4_0_set_buffer_funcs(s
- }
- 
- static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
-+	.copy_pte_num_dw = 7,
- 	.copy_pte = sdma_v4_0_vm_copy_pte,
-+
- 	.write_pte = sdma_v4_0_vm_write_pte,
-+
-+	.set_max_nums_pte_pde = 0x400000 >> 3,
-+	.set_pte_pde_num_dw = 10,
- 	.set_pte_pde = sdma_v4_0_vm_set_pte_pde,
- };
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/si.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/si.c	2017-12-14 06:39:58.392903551 +0100
-@@ -1392,63 +1392,63 @@ static void si_init_golden_registers(str
- 	case CHIP_TAHITI:
- 		amdgpu_program_register_sequence(adev,
- 						 tahiti_golden_registers,
--						 (const u32)ARRAY_SIZE(tahiti_golden_registers));
-+						 ARRAY_SIZE(tahiti_golden_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 tahiti_golden_rlc_registers,
--						 (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
-+						 ARRAY_SIZE(tahiti_golden_rlc_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 tahiti_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
-+						 ARRAY_SIZE(tahiti_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 tahiti_golden_registers2,
--						 (const u32)ARRAY_SIZE(tahiti_golden_registers2));
-+						 ARRAY_SIZE(tahiti_golden_registers2));
- 		break;
- 	case CHIP_PITCAIRN:
- 		amdgpu_program_register_sequence(adev,
- 						 pitcairn_golden_registers,
--						 (const u32)ARRAY_SIZE(pitcairn_golden_registers));
-+						 ARRAY_SIZE(pitcairn_golden_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 pitcairn_golden_rlc_registers,
--						 (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
-+						 ARRAY_SIZE(pitcairn_golden_rlc_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 pitcairn_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
-+						 ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
- 		break;
- 	case CHIP_VERDE:
- 		amdgpu_program_register_sequence(adev,
- 						 verde_golden_registers,
--						 (const u32)ARRAY_SIZE(verde_golden_registers));
-+						 ARRAY_SIZE(verde_golden_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 verde_golden_rlc_registers,
--						 (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
-+						 ARRAY_SIZE(verde_golden_rlc_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 verde_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
-+						 ARRAY_SIZE(verde_mgcg_cgcg_init));
- 		amdgpu_program_register_sequence(adev,
- 						 verde_pg_init,
--						 (const u32)ARRAY_SIZE(verde_pg_init));
-+						 ARRAY_SIZE(verde_pg_init));
- 		break;
- 	case CHIP_OLAND:
- 		amdgpu_program_register_sequence(adev,
- 						 oland_golden_registers,
--						 (const u32)ARRAY_SIZE(oland_golden_registers));
-+						 ARRAY_SIZE(oland_golden_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 oland_golden_rlc_registers,
--						 (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
-+						 ARRAY_SIZE(oland_golden_rlc_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 oland_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
-+						 ARRAY_SIZE(oland_mgcg_cgcg_init));
- 		break;
- 	case CHIP_HAINAN:
- 		amdgpu_program_register_sequence(adev,
- 						 hainan_golden_registers,
--						 (const u32)ARRAY_SIZE(hainan_golden_registers));
-+						 ARRAY_SIZE(hainan_golden_registers));
- 		amdgpu_program_register_sequence(adev,
- 						 hainan_golden_registers2,
--						 (const u32)ARRAY_SIZE(hainan_golden_registers2));
-+						 ARRAY_SIZE(hainan_golden_registers2));
- 		amdgpu_program_register_sequence(adev,
- 						 hainan_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
-+						 ARRAY_SIZE(hainan_mgcg_cgcg_init));
- 		break;
- 
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/si_dma.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/si_dma.c	2017-12-14 06:39:58.392903551 +0100
-@@ -252,7 +252,7 @@ static int si_dma_ring_test_ring(struct
- 	}
- 
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
- 			  ring->idx, tmp);
-@@ -317,7 +317,7 @@ static int si_dma_ring_test_ib(struct am
- 	}
- 	tmp = le32_to_cpu(adev->wb.wb[index]);
- 	if (tmp == 0xDEADBEEF) {
--		DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
-+		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
- 		r = 0;
- 	} else {
- 		DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
-@@ -887,8 +887,13 @@ static void si_dma_set_buffer_funcs(stru
- }
- 
- static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = {
-+	.copy_pte_num_dw = 5,
- 	.copy_pte = si_dma_vm_copy_pte,
-+
- 	.write_pte = si_dma_vm_write_pte,
-+
-+	.set_max_nums_pte_pde = 0xffff8 >> 3,
-+	.set_pte_pde_num_dw = 9,
- 	.set_pte_pde = si_dma_vm_set_pte_pde,
- };
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/si_dpm.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/si_dpm.c	2017-12-14 06:39:58.392903551 +0100
-@@ -1847,7 +1847,6 @@ static int si_calculate_sclk_params(stru
- 
- static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
- static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
--static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
- static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
- 
- static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
-@@ -3060,9 +3059,9 @@ static int si_get_vce_clock_voltage(stru
- 	return ret;
- }
- 
--static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
-+static bool si_dpm_vblank_too_short(void *handle)
- {
--
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
- 	/* we never hit the non-gddr5 limit so disable it */
- 	u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
-@@ -3871,9 +3870,10 @@ static int si_restrict_performance_level
- 		0 : -EINVAL;
- }
- 
--static int si_dpm_force_performance_level(struct amdgpu_device *adev,
-+static int si_dpm_force_performance_level(void *handle,
- 				   enum amd_dpm_forced_level level)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
- 	struct  si_ps *ps = si_get_ps(rps);
- 	u32 levels = ps->performance_level_count;
-@@ -6575,11 +6575,12 @@ static int si_fan_ctrl_stop_smc_fan_cont
- 	}
- }
- 
--static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
-+static int si_dpm_get_fan_speed_percent(void *handle,
- 				      u32 *speed)
- {
- 	u32 duty, duty100;
- 	u64 tmp64;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	if (adev->pm.no_fan)
- 		return -ENOENT;
-@@ -6600,9 +6601,10 @@ static int si_dpm_get_fan_speed_percent(
- 	return 0;
- }
- 
--static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
-+static int si_dpm_set_fan_speed_percent(void *handle,
- 				      u32 speed)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct si_power_info *si_pi = si_get_pi(adev);
- 	u32 tmp;
- 	u32 duty, duty100;
-@@ -6633,8 +6635,10 @@ static int si_dpm_set_fan_speed_percent(
- 	return 0;
- }
- 
--static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
-+static void si_dpm_set_fan_control_mode(void *handle, u32 mode)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
- 	if (mode) {
- 		/* stop auto-manage */
- 		if (adev->pm.dpm.fan.ucode_fan_control)
-@@ -6649,8 +6653,9 @@ static void si_dpm_set_fan_control_mode(
- 	}
- }
- 
--static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
-+static u32 si_dpm_get_fan_control_mode(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct si_power_info *si_pi = si_get_pi(adev);
- 	u32 tmp;
- 
-@@ -6946,8 +6951,9 @@ static void si_dpm_disable(struct amdgpu
- 	ni_update_current_ps(adev, boot_ps);
- }
- 
--static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
-+static int si_dpm_pre_set_power_state(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
- 	struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
- 	struct amdgpu_ps *new_ps = &requested_ps;
-@@ -6984,8 +6990,9 @@ static int si_power_control_set_level(st
- 	return 0;
- }
- 
--static int si_dpm_set_power_state(struct amdgpu_device *adev)
-+static int si_dpm_set_power_state(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
- 	struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
- 	struct amdgpu_ps *old_ps = &eg_pi->current_rps;
-@@ -7086,8 +7093,9 @@ static int si_dpm_set_power_state(struct
- 	return 0;
- }
- 
--static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
-+static void si_dpm_post_set_power_state(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
- 	struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
- 
-@@ -7103,8 +7111,10 @@ void si_dpm_reset_asic(struct amdgpu_dev
- }
- #endif
- 
--static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
-+static void si_dpm_display_configuration_changed(void *handle)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
- 	si_program_display_gap(adev);
- }
- 
-@@ -7486,9 +7496,10 @@ static void si_dpm_fini(struct amdgpu_de
- 	amdgpu_free_extended_power_table(adev);
- }
- 
--static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
-+static void si_dpm_debugfs_print_current_performance_level(void *handle,
- 						    struct seq_file *m)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
- 	struct amdgpu_ps *rps = &eg_pi->current_rps;
- 	struct  si_ps *ps = si_get_ps(rps);
-@@ -7593,11 +7604,6 @@ static int si_dpm_late_init(void *handle
- 	if (!amdgpu_dpm)
- 		return 0;
- 
--	/* init the sysfs and debugfs files late */
--	ret = amdgpu_pm_sysfs_init(adev);
--	if (ret)
--		return ret;
--
- 	ret = si_set_temperature_range(adev);
- 	if (ret)
- 		return ret;
-@@ -7753,7 +7759,6 @@ static int si_dpm_sw_fini(void *handle)
- 	flush_work(&adev->pm.dpm.thermal.work);
- 
- 	mutex_lock(&adev->pm.mutex);
--	amdgpu_pm_sysfs_fini(adev);
- 	si_dpm_fini(adev);
- 	mutex_unlock(&adev->pm.mutex);
- 
-@@ -7860,10 +7865,11 @@ static int si_dpm_set_powergating_state(
- }
- 
- /* get temperature in millidegrees */
--static int si_dpm_get_temp(struct amdgpu_device *adev)
-+static int si_dpm_get_temp(void *handle)
- {
- 	u32 temp;
- 	int actual_temp = 0;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
- 		CTF_TEMP_SHIFT;
-@@ -7878,8 +7884,9 @@ static int si_dpm_get_temp(struct amdgpu
- 	return actual_temp;
- }
- 
--static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
-+static u32 si_dpm_get_sclk(void *handle, bool low)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
- 	struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
- 
-@@ -7889,8 +7896,9 @@ static u32 si_dpm_get_sclk(struct amdgpu
- 		return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
- }
- 
--static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
-+static u32 si_dpm_get_mclk(void *handle, bool low)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
- 	struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
- 
-@@ -7900,9 +7908,11 @@ static u32 si_dpm_get_mclk(struct amdgpu
- 		return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
- }
- 
--static void si_dpm_print_power_state(struct amdgpu_device *adev,
--				     struct amdgpu_ps *rps)
-+static void si_dpm_print_power_state(void *handle,
-+				     void *current_ps)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
- 	struct  si_ps *ps = si_get_ps(rps);
- 	struct rv7xx_pl *pl;
- 	int i;
-@@ -7927,7 +7937,6 @@ static int si_dpm_early_init(void *handl
- 
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	si_dpm_set_dpm_funcs(adev);
- 	si_dpm_set_irq_funcs(adev);
- 	return 0;
- }
-@@ -7942,20 +7951,23 @@ static inline bool si_are_power_levels_e
- 		  (si_cpl1->vddci == si_cpl2->vddci));
- }
- 
--static int si_check_state_equal(struct amdgpu_device *adev,
--				struct amdgpu_ps *cps,
--				struct amdgpu_ps *rps,
-+static int si_check_state_equal(void *handle,
-+				void *current_ps,
-+				void *request_ps,
- 				bool *equal)
- {
- 	struct si_ps *si_cps;
- 	struct si_ps *si_rps;
- 	int i;
-+	struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
-+	struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
- 		return -EINVAL;
- 
--	si_cps = si_get_ps(cps);
--	si_rps = si_get_ps(rps);
-+	si_cps = si_get_ps((struct amdgpu_ps *)cps);
-+	si_rps = si_get_ps((struct amdgpu_ps *)rps);
- 
- 	if (si_cps == NULL) {
- 		printk("si_cps is NULL\n");
-@@ -7983,9 +7995,10 @@ static int si_check_state_equal(struct a
- 	return 0;
- }
- 
--static int si_dpm_read_sensor(struct amdgpu_device *adev, int idx,
-+static int si_dpm_read_sensor(void *handle, int idx,
- 			      void *value, int *size)
- {
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
- 	struct amdgpu_ps *rps = &eg_pi->current_rps;
- 	struct  si_ps *ps = si_get_ps(rps);
-@@ -8041,7 +8054,7 @@ const struct amd_ip_funcs si_dpm_ip_func
- 	.set_powergating_state = si_dpm_set_powergating_state,
- };
- 
--static const struct amdgpu_dpm_funcs si_dpm_funcs = {
-+const struct amd_pm_funcs si_dpm_funcs = {
- 	.get_temperature = &si_dpm_get_temp,
- 	.pre_set_power_state = &si_dpm_pre_set_power_state,
- 	.set_power_state = &si_dpm_set_power_state,
-@@ -8062,12 +8075,6 @@ static const struct amdgpu_dpm_funcs si_
- 	.read_sensor = &si_dpm_read_sensor,
- };
- 
--static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
--{
--	if (adev->pm.funcs == NULL)
--		adev->pm.funcs = &si_dpm_funcs;
--}
--
- static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
- 	.set = si_dpm_set_interrupt_state,
- 	.process = si_dpm_process_interrupt,
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/si_dpm.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/si_dpm.h	2017-12-14 06:39:58.393903552 +0100
-@@ -246,6 +246,7 @@ enum si_display_gap
- };
- 
- extern const struct amd_ip_funcs si_dpm_ip_funcs;
-+extern const struct amd_pm_funcs si_dpm_funcs;
- 
- struct ni_leakage_coeffients
- {
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/si_ih.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/si_ih.c	2017-12-14 06:39:58.393903552 +0100
-@@ -118,6 +118,19 @@ static u32 si_ih_get_wptr(struct amdgpu_
- 	return (wptr & adev->irq.ih.ptr_mask);
- }
- 
-+/**
-+ * si_ih_prescreen_iv - prescreen an interrupt vector
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Returns true if the interrupt vector should be further processed.
-+ */
-+static bool si_ih_prescreen_iv(struct amdgpu_device *adev)
-+{
-+	/* Process all interrupts */
-+	return true;
-+}
-+
- static void si_ih_decode_iv(struct amdgpu_device *adev,
- 			     struct amdgpu_iv_entry *entry)
- {
-@@ -288,6 +301,7 @@ static const struct amd_ip_funcs si_ih_i
- 
- static const struct amdgpu_ih_funcs si_ih_funcs = {
- 	.get_wptr = si_ih_get_wptr,
-+	.prescreen_iv = si_ih_prescreen_iv,
- 	.decode_iv = si_ih_decode_iv,
- 	.set_rptr = si_ih_set_rptr
- };
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/soc15.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/soc15.c	2017-12-14 06:39:58.393903552 +0100
-@@ -101,7 +101,7 @@ static u32 soc15_pcie_rreg(struct amdgpu
- {
- 	unsigned long flags, address, data;
- 	u32 r;
--	struct nbio_pcie_index_data *nbio_pcie_id;
-+	const struct nbio_pcie_index_data *nbio_pcie_id;
- 
- 	if (adev->flags & AMD_IS_APU)
- 		nbio_pcie_id = &nbio_v7_0_pcie_index_data;
-@@ -122,7 +122,7 @@ static u32 soc15_pcie_rreg(struct amdgpu
- static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
- {
- 	unsigned long flags, address, data;
--	struct nbio_pcie_index_data *nbio_pcie_id;
-+	const struct nbio_pcie_index_data *nbio_pcie_id;
- 
- 	if (adev->flags & AMD_IS_APU)
- 		nbio_pcie_id = &nbio_v7_0_pcie_index_data;
-@@ -265,12 +265,12 @@ static void soc15_init_golden_registers(
- 	case CHIP_VEGA10:
- 		amdgpu_program_register_sequence(adev,
- 						 vega10_golden_init,
--						 (const u32)ARRAY_SIZE(vega10_golden_init));
-+						 ARRAY_SIZE(vega10_golden_init));
- 		break;
- 	case CHIP_RAVEN:
- 		amdgpu_program_register_sequence(adev,
- 						 raven_golden_init,
--						 (const u32)ARRAY_SIZE(raven_golden_init));
-+						 ARRAY_SIZE(raven_golden_init));
- 		break;
- 	default:
- 		break;
-@@ -404,18 +404,27 @@ static int soc15_read_register(struct am
- 	return -EINVAL;
- }
- 
--static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
-+static int soc15_asic_reset(struct amdgpu_device *adev)
- {
- 	u32 i;
- 
--	dev_info(adev->dev, "GPU pci config reset\n");
-+	amdgpu_atombios_scratch_regs_engine_hung(adev, true);
-+
-+	dev_info(adev->dev, "GPU reset\n");
- 
- 	/* disable BM */
- 	pci_clear_master(adev->pdev);
--	/* reset */
--	amdgpu_pci_config_reset(adev);
- 
--	udelay(100);
-+	pci_save_state(adev->pdev);
-+
-+	for (i = 0; i < AMDGPU_MAX_IP_NUM; i++) {
-+		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP){
-+			adev->ip_blocks[i].version->funcs->soft_reset((void *)adev);
-+			break;
-+		}
-+	}
-+
-+	pci_restore_state(adev->pdev);
- 
- 	/* wait for asic to come out of reset */
- 	for (i = 0; i < adev->usec_timeout; i++) {
-@@ -427,14 +436,6 @@ static void soc15_gpu_pci_config_reset(s
- 		udelay(1);
- 	}
- 
--}
--
--static int soc15_asic_reset(struct amdgpu_device *adev)
--{
--	amdgpu_atombios_scratch_regs_engine_hung(adev, true);
--
--	soc15_gpu_pci_config_reset(adev);
--
- 	amdgpu_atombios_scratch_regs_engine_hung(adev, false);
- 
- 	return 0;
-@@ -531,6 +532,12 @@ int soc15_set_ip_blocks(struct amdgpu_de
- 			amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
- 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
- 			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
-+#if defined(CONFIG_DRM_AMD_DC)
-+		else if (amdgpu_device_has_dc_support(adev))
-+			amdgpu_ip_block_add(adev, &dm_ip_block);
-+#else
-+#	warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
-+#endif
- 		amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
- 		amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
- 		amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
-@@ -544,6 +551,12 @@ int soc15_set_ip_blocks(struct amdgpu_de
- 		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
- 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
- 			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
-+#if defined(CONFIG_DRM_AMD_DC)
-+		else if (amdgpu_device_has_dc_support(adev))
-+			amdgpu_ip_block_add(adev, &dm_ip_block);
-+#else
-+#	warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
-+#endif
- 		amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
- 		amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
- 		amdgpu_ip_block_add(adev, &vcn_v1_0_ip_block);
-@@ -600,21 +613,6 @@ static int soc15_common_early_init(void
- 		(amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
- 		psp_enabled = true;
- 
--	/*
--	 * nbio need be used for both sdma and gfx9, but only
--	 * initializes once
--	 */
--	switch(adev->asic_type) {
--	case CHIP_VEGA10:
--		nbio_v6_1_init(adev);
--		break;
--	case CHIP_RAVEN:
--		nbio_v7_0_init(adev);
--		break;
--	default:
--		return -EINVAL;
--	}
--
- 	adev->rev_id = soc15_get_rev_id(adev);
- 	adev->external_rev_id = 0xFF;
- 	switch (adev->asic_type) {
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/tonga_ih.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/tonga_ih.c	2017-12-14 06:39:58.393903552 +0100
-@@ -219,6 +219,34 @@ static u32 tonga_ih_get_wptr(struct amdg
- }
- 
- /**
-+ * tonga_ih_prescreen_iv - prescreen an interrupt vector
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Returns true if the interrupt vector should be further processed.
-+ */
-+static bool tonga_ih_prescreen_iv(struct amdgpu_device *adev)
-+{
-+	u32 ring_index = adev->irq.ih.rptr >> 2;
-+	u16 pasid;
-+
-+	switch (le32_to_cpu(adev->irq.ih.ring[ring_index]) & 0xff) {
-+	case 146:
-+	case 147:
-+		pasid = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]) >> 16;
-+		if (!pasid || amdgpu_vm_pasid_fault_credit(adev, pasid))
-+			return true;
-+		break;
-+	default:
-+		/* Not a VM fault */
-+		return true;
-+	}
-+
-+	adev->irq.ih.rptr += 16;
-+	return false;
-+}
-+
-+/**
-  * tonga_ih_decode_iv - decode an interrupt vector
-  *
-  * @adev: amdgpu_device pointer
-@@ -478,6 +506,7 @@ static const struct amd_ip_funcs tonga_i
- 
- static const struct amdgpu_ih_funcs tonga_ih_funcs = {
- 	.get_wptr = tonga_ih_get_wptr,
-+	.prescreen_iv = tonga_ih_prescreen_iv,
- 	.decode_iv = tonga_ih_decode_iv,
- 	.set_rptr = tonga_ih_set_rptr
- };
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c	2017-12-14 06:39:58.393903552 +0100
-@@ -521,7 +521,7 @@ static int uvd_v4_2_ring_test_ring(struc
- 	}
- 
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n",
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
- 			 ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
-@@ -563,7 +563,7 @@ static void uvd_v4_2_mc_resume(struct am
- 
- 	/* programm the VCPU memory controller bits 0-27 */
- 	addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
--	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3;
-+	size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3;
- 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
- 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c	2017-12-14 06:39:58.393903552 +0100
-@@ -258,7 +258,7 @@ static void uvd_v5_0_mc_resume(struct am
- 			upper_32_bits(adev->uvd.gpu_addr));
- 
- 	offset = AMDGPU_UVD_FIRMWARE_OFFSET;
--	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
-+	size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
- 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
- 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
- 
-@@ -536,7 +536,7 @@ static int uvd_v5_0_ring_test_ring(struc
- 	}
- 
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n",
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
- 			 ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c	2017-12-14 06:39:58.393903552 +0100
-@@ -38,6 +38,8 @@
- #include "vi.h"
- 
- static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
-+static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
-+
- static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
- static int uvd_v6_0_start(struct amdgpu_device *adev);
- static void uvd_v6_0_stop(struct amdgpu_device *adev);
-@@ -48,6 +50,18 @@ static void uvd_v6_0_enable_mgcg(struct
- 				 bool enable);
- 
- /**
-+* uvd_v6_0_enc_support - get encode support status
-+*
-+* @adev: amdgpu_device pointer
-+*
-+* Returns the current hardware encode support status
-+*/
-+static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
-+{
-+	return ((adev->asic_type >= CHIP_POLARIS10) && (adev->asic_type <= CHIP_POLARIS12));
-+}
-+
-+/**
-  * uvd_v6_0_ring_get_rptr - get read pointer
-  *
-  * @ring: amdgpu_ring pointer
-@@ -62,6 +76,22 @@ static uint64_t uvd_v6_0_ring_get_rptr(s
- }
- 
- /**
-+ * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
-+ *
-+ * @ring: amdgpu_ring pointer
-+ *
-+ * Returns the current hardware enc read pointer
-+ */
-+static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
-+{
-+	struct amdgpu_device *adev = ring->adev;
-+
-+	if (ring == &adev->uvd.ring_enc[0])
-+		return RREG32(mmUVD_RB_RPTR);
-+	else
-+		return RREG32(mmUVD_RB_RPTR2);
-+}
-+/**
-  * uvd_v6_0_ring_get_wptr - get write pointer
-  *
-  * @ring: amdgpu_ring pointer
-@@ -76,6 +106,23 @@ static uint64_t uvd_v6_0_ring_get_wptr(s
- }
- 
- /**
-+ * uvd_v6_0_enc_ring_get_wptr - get enc write pointer
-+ *
-+ * @ring: amdgpu_ring pointer
-+ *
-+ * Returns the current hardware enc write pointer
-+ */
-+static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
-+{
-+	struct amdgpu_device *adev = ring->adev;
-+
-+	if (ring == &adev->uvd.ring_enc[0])
-+		return RREG32(mmUVD_RB_WPTR);
-+	else
-+		return RREG32(mmUVD_RB_WPTR2);
-+}
-+
-+/**
-  * uvd_v6_0_ring_set_wptr - set write pointer
-  *
-  * @ring: amdgpu_ring pointer
-@@ -89,6 +136,238 @@ static void uvd_v6_0_ring_set_wptr(struc
- 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
- }
- 
-+/**
-+ * uvd_v6_0_enc_ring_set_wptr - set enc write pointer
-+ *
-+ * @ring: amdgpu_ring pointer
-+ *
-+ * Commits the enc write pointer to the hardware
-+ */
-+static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
-+{
-+	struct amdgpu_device *adev = ring->adev;
-+
-+	if (ring == &adev->uvd.ring_enc[0])
-+		WREG32(mmUVD_RB_WPTR,
-+			lower_32_bits(ring->wptr));
-+	else
-+		WREG32(mmUVD_RB_WPTR2,
-+			lower_32_bits(ring->wptr));
-+}
-+
-+/**
-+ * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working
-+ *
-+ * @ring: the engine to test on
-+ *
-+ */
-+static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
-+{
-+	struct amdgpu_device *adev = ring->adev;
-+	uint32_t rptr = amdgpu_ring_get_rptr(ring);
-+	unsigned i;
-+	int r;
-+
-+	r = amdgpu_ring_alloc(ring, 16);
-+	if (r) {
-+		DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
-+			  ring->idx, r);
-+		return r;
-+	}
-+	amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
-+	amdgpu_ring_commit(ring);
-+
-+	for (i = 0; i < adev->usec_timeout; i++) {
-+		if (amdgpu_ring_get_rptr(ring) != rptr)
-+			break;
-+		DRM_UDELAY(1);
-+	}
-+
-+	if (i < adev->usec_timeout) {
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
-+			 ring->idx, i);
-+	} else {
-+		DRM_ERROR("amdgpu: ring %d test failed\n",
-+			  ring->idx);
-+		r = -ETIMEDOUT;
-+	}
-+
-+	return r;
-+}
-+
-+/**
-+ * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg
-+ *
-+ * @adev: amdgpu_device pointer
-+ * @ring: ring we should submit the msg to
-+ * @handle: session handle to use
-+ * @fence: optional fence to return
-+ *
-+ * Open up a stream for HW test
-+ */
-+static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
-+				       struct dma_fence **fence)
-+{
-+	const unsigned ib_size_dw = 16;
-+	struct amdgpu_job *job;
-+	struct amdgpu_ib *ib;
-+	struct dma_fence *f = NULL;
-+	uint64_t dummy;
-+	int i, r;
-+
-+	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
-+	if (r)
-+		return r;
-+
-+	ib = &job->ibs[0];
-+	dummy = ib->gpu_addr + 1024;
-+
-+	ib->length_dw = 0;
-+	ib->ptr[ib->length_dw++] = 0x00000018;
-+	ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
-+	ib->ptr[ib->length_dw++] = handle;
-+	ib->ptr[ib->length_dw++] = 0x00010000;
-+	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
-+	ib->ptr[ib->length_dw++] = dummy;
-+
-+	ib->ptr[ib->length_dw++] = 0x00000014;
-+	ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
-+	ib->ptr[ib->length_dw++] = 0x0000001c;
-+	ib->ptr[ib->length_dw++] = 0x00000001;
-+	ib->ptr[ib->length_dw++] = 0x00000000;
-+
-+	ib->ptr[ib->length_dw++] = 0x00000008;
-+	ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
-+
-+	for (i = ib->length_dw; i < ib_size_dw; ++i)
-+		ib->ptr[i] = 0x0;
-+
-+	r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
-+	job->fence = dma_fence_get(f);
-+	if (r)
-+		goto err;
-+
-+	amdgpu_job_free(job);
-+	if (fence)
-+		*fence = dma_fence_get(f);
-+	dma_fence_put(f);
-+	return 0;
-+
-+err:
-+	amdgpu_job_free(job);
-+	return r;
-+}
-+
-+/**
-+ * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
-+ *
-+ * @adev: amdgpu_device pointer
-+ * @ring: ring we should submit the msg to
-+ * @handle: session handle to use
-+ * @fence: optional fence to return
-+ *
-+ * Close up a stream for HW test or if userspace failed to do so
-+ */
-+static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
-+					uint32_t handle,
-+					bool direct, struct dma_fence **fence)
-+{
-+	const unsigned ib_size_dw = 16;
-+	struct amdgpu_job *job;
-+	struct amdgpu_ib *ib;
-+	struct dma_fence *f = NULL;
-+	uint64_t dummy;
-+	int i, r;
-+
-+	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
-+	if (r)
-+		return r;
-+
-+	ib = &job->ibs[0];
-+	dummy = ib->gpu_addr + 1024;
-+
-+	ib->length_dw = 0;
-+	ib->ptr[ib->length_dw++] = 0x00000018;
-+	ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
-+	ib->ptr[ib->length_dw++] = handle;
-+	ib->ptr[ib->length_dw++] = 0x00010000;
-+	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
-+	ib->ptr[ib->length_dw++] = dummy;
-+
-+	ib->ptr[ib->length_dw++] = 0x00000014;
-+	ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
-+	ib->ptr[ib->length_dw++] = 0x0000001c;
-+	ib->ptr[ib->length_dw++] = 0x00000001;
-+	ib->ptr[ib->length_dw++] = 0x00000000;
-+
-+	ib->ptr[ib->length_dw++] = 0x00000008;
-+	ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
-+
-+	for (i = ib->length_dw; i < ib_size_dw; ++i)
-+		ib->ptr[i] = 0x0;
-+
-+	if (direct) {
-+		r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
-+		job->fence = dma_fence_get(f);
-+		if (r)
-+			goto err;
-+
-+		amdgpu_job_free(job);
-+	} else {
-+		r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
-+				      AMDGPU_FENCE_OWNER_UNDEFINED, &f);
-+		if (r)
-+			goto err;
-+	}
-+
-+	if (fence)
-+		*fence = dma_fence_get(f);
-+	dma_fence_put(f);
-+	return 0;
-+
-+err:
-+	amdgpu_job_free(job);
-+	return r;
-+}
-+
-+/**
-+ * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working
-+ *
-+ * @ring: the engine to test on
-+ *
-+ */
-+static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
-+{
-+	struct dma_fence *fence = NULL;
-+	long r;
-+
-+	r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL);
-+	if (r) {
-+		DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
-+		goto error;
-+	}
-+
-+	r = uvd_v6_0_enc_get_destroy_msg(ring, 1, true, &fence);
-+	if (r) {
-+		DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
-+		goto error;
-+	}
-+
-+	r = dma_fence_wait_timeout(fence, false, timeout);
-+	if (r == 0) {
-+		DRM_ERROR("amdgpu: IB test timed out.\n");
-+		r = -ETIMEDOUT;
-+	} else if (r < 0) {
-+		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
-+	} else {
-+		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
-+		r = 0;
-+	}
-+error:
-+	dma_fence_put(fence);
-+	return r;
-+}
-+
- static int uvd_v6_0_early_init(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-@@ -98,6 +377,12 @@ static int uvd_v6_0_early_init(void *han
- 		return -ENOENT;
- 
- 	uvd_v6_0_set_ring_funcs(adev);
-+
-+	if (uvd_v6_0_enc_support(adev)) {
-+		adev->uvd.num_enc_rings = 2;
-+		uvd_v6_0_set_enc_ring_funcs(adev);
-+	}
-+
- 	uvd_v6_0_set_irq_funcs(adev);
- 
- 	return 0;
-@@ -106,7 +391,7 @@ static int uvd_v6_0_early_init(void *han
- static int uvd_v6_0_sw_init(void *handle)
- {
- 	struct amdgpu_ring *ring;
--	int r;
-+	int i, r;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	/* UVD TRAP */
-@@ -114,10 +399,31 @@ static int uvd_v6_0_sw_init(void *handle
- 	if (r)
- 		return r;
- 
-+	/* UVD ENC TRAP */
-+	if (uvd_v6_0_enc_support(adev)) {
-+		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-+			r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 119, &adev->uvd.irq);
-+			if (r)
-+				return r;
-+		}
-+	}
-+
- 	r = amdgpu_uvd_sw_init(adev);
- 	if (r)
- 		return r;
- 
-+	if (uvd_v6_0_enc_support(adev)) {
-+		struct amd_sched_rq *rq;
-+		ring = &adev->uvd.ring_enc[0];
-+		rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
-+		r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
-+					  rq, amdgpu_sched_jobs, NULL);
-+		if (r) {
-+			DRM_ERROR("Failed setting up UVD ENC run queue.\n");
-+			return r;
-+		}
-+	}
-+
- 	r = amdgpu_uvd_resume(adev);
- 	if (r)
- 		return r;
-@@ -125,19 +431,38 @@ static int uvd_v6_0_sw_init(void *handle
- 	ring = &adev->uvd.ring;
- 	sprintf(ring->name, "uvd");
- 	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
-+	if (r)
-+		return r;
-+
-+	if (uvd_v6_0_enc_support(adev)) {
-+		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-+			ring = &adev->uvd.ring_enc[i];
-+			sprintf(ring->name, "uvd_enc%d", i);
-+			r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
-+			if (r)
-+				return r;
-+		}
-+	}
- 
- 	return r;
- }
- 
- static int uvd_v6_0_sw_fini(void *handle)
- {
--	int r;
-+	int i, r;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
- 	r = amdgpu_uvd_suspend(adev);
- 	if (r)
- 		return r;
- 
-+	if (uvd_v6_0_enc_support(adev)) {
-+		amd_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
-+
-+		for (i = 0; i < adev->uvd.num_enc_rings; ++i)
-+			amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
-+	}
-+
- 	return amdgpu_uvd_sw_fini(adev);
- }
- 
-@@ -153,7 +478,7 @@ static int uvd_v6_0_hw_init(void *handle
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 	struct amdgpu_ring *ring = &adev->uvd.ring;
- 	uint32_t tmp;
--	int r;
-+	int i, r;
- 
- 	amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
- 	uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
-@@ -193,9 +518,25 @@ static int uvd_v6_0_hw_init(void *handle
- 
- 	amdgpu_ring_commit(ring);
- 
-+	if (uvd_v6_0_enc_support(adev)) {
-+		for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-+			ring = &adev->uvd.ring_enc[i];
-+			ring->ready = true;
-+			r = amdgpu_ring_test_ring(ring);
-+			if (r) {
-+				ring->ready = false;
-+				goto done;
-+			}
-+		}
-+	}
-+
- done:
--	if (!r)
--		DRM_INFO("UVD initialized successfully.\n");
-+	if (!r) {
-+		if (uvd_v6_0_enc_support(adev))
-+			DRM_INFO("UVD and UVD ENC initialized successfully.\n");
-+		else
-+			DRM_INFO("UVD initialized successfully.\n");
-+	}
- 
- 	return r;
- }
-@@ -263,7 +604,7 @@ static void uvd_v6_0_mc_resume(struct am
- 			upper_32_bits(adev->uvd.gpu_addr));
- 
- 	offset = AMDGPU_UVD_FIRMWARE_OFFSET;
--	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
-+	size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
- 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
- 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
- 
-@@ -512,6 +853,22 @@ static int uvd_v6_0_start(struct amdgpu_
- 
- 	WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
- 
-+	if (uvd_v6_0_enc_support(adev)) {
-+		ring = &adev->uvd.ring_enc[0];
-+		WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
-+		WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
-+		WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
-+		WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
-+		WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
-+
-+		ring = &adev->uvd.ring_enc[1];
-+		WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
-+		WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
-+		WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
-+		WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
-+		WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
-+	}
-+
- 	return 0;
- }
- 
-@@ -575,6 +932,26 @@ static void uvd_v6_0_ring_emit_fence(str
- }
- 
- /**
-+ * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command
-+ *
-+ * @ring: amdgpu_ring pointer
-+ * @fence: fence to emit
-+ *
-+ * Write enc a fence and a trap command to the ring.
-+ */
-+static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
-+			u64 seq, unsigned flags)
-+{
-+	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
-+
-+	amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
-+	amdgpu_ring_write(ring, addr);
-+	amdgpu_ring_write(ring, upper_32_bits(addr));
-+	amdgpu_ring_write(ring, seq);
-+	amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
-+}
-+
-+/**
-  * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
-  *
-  * @ring: amdgpu_ring pointer
-@@ -632,7 +1009,7 @@ static int uvd_v6_0_ring_test_ring(struc
- 	}
- 
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n",
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
- 			 ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
-@@ -665,6 +1042,24 @@ static void uvd_v6_0_ring_emit_ib(struct
- 	amdgpu_ring_write(ring, ib->length_dw);
- }
- 
-+/**
-+ * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer
-+ *
-+ * @ring: amdgpu_ring pointer
-+ * @ib: indirect buffer to execute
-+ *
-+ * Write enc ring commands to execute the indirect buffer
-+ */
-+static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
-+		struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
-+{
-+	amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
-+	amdgpu_ring_write(ring, vm_id);
-+	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
-+	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
-+	amdgpu_ring_write(ring, ib->length_dw);
-+}
-+
- static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
- 					 unsigned vm_id, uint64_t pd_addr)
- {
-@@ -716,6 +1111,33 @@ static void uvd_v6_0_ring_emit_pipeline_
- 	amdgpu_ring_write(ring, 0xE);
- }
- 
-+static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
-+{
-+	uint32_t seq = ring->fence_drv.sync_seq;
-+	uint64_t addr = ring->fence_drv.gpu_addr;
-+
-+	amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE);
-+	amdgpu_ring_write(ring, lower_32_bits(addr));
-+	amdgpu_ring_write(ring, upper_32_bits(addr));
-+	amdgpu_ring_write(ring, seq);
-+}
-+
-+static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
-+{
-+	amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
-+}
-+
-+static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
-+        unsigned int vm_id, uint64_t pd_addr)
-+{
-+	amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
-+	amdgpu_ring_write(ring, vm_id);
-+	amdgpu_ring_write(ring, pd_addr >> 12);
-+
-+	amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
-+	amdgpu_ring_write(ring, vm_id);
-+}
-+
- static bool uvd_v6_0_is_idle(void *handle)
- {
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-@@ -823,8 +1245,31 @@ static int uvd_v6_0_process_interrupt(st
- 				      struct amdgpu_irq_src *source,
- 				      struct amdgpu_iv_entry *entry)
- {
-+	bool int_handled = true;
- 	DRM_DEBUG("IH: UVD TRAP\n");
--	amdgpu_fence_process(&adev->uvd.ring);
-+
-+	switch (entry->src_id) {
-+	case 124:
-+		amdgpu_fence_process(&adev->uvd.ring);
-+		break;
-+	case 119:
-+		if (likely(uvd_v6_0_enc_support(adev)))
-+			amdgpu_fence_process(&adev->uvd.ring_enc[0]);
-+		else
-+			int_handled = false;
-+		break;
-+	case 120:
-+		if (likely(uvd_v6_0_enc_support(adev)))
-+			amdgpu_fence_process(&adev->uvd.ring_enc[1]);
-+		else
-+			int_handled = false;
-+		break;
-+	}
-+
-+	if (false == int_handled)
-+			DRM_ERROR("Unhandled interrupt: %d %d\n",
-+			  entry->src_id, entry->src_data[0]);
-+
- 	return 0;
- }
- 
-@@ -1151,6 +1596,33 @@ static const struct amdgpu_ring_funcs uv
- 	.end_use = amdgpu_uvd_ring_end_use,
- };
- 
-+static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
-+	.type = AMDGPU_RING_TYPE_UVD_ENC,
-+	.align_mask = 0x3f,
-+	.nop = HEVC_ENC_CMD_NO_OP,
-+	.support_64bit_ptrs = false,
-+	.get_rptr = uvd_v6_0_enc_ring_get_rptr,
-+	.get_wptr = uvd_v6_0_enc_ring_get_wptr,
-+	.set_wptr = uvd_v6_0_enc_ring_set_wptr,
-+	.emit_frame_size =
-+		4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
-+		6 + /* uvd_v6_0_enc_ring_emit_vm_flush */
-+		5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
-+		1, /* uvd_v6_0_enc_ring_insert_end */
-+	.emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
-+	.emit_ib = uvd_v6_0_enc_ring_emit_ib,
-+	.emit_fence = uvd_v6_0_enc_ring_emit_fence,
-+	.emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush,
-+	.emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync,
-+	.test_ring = uvd_v6_0_enc_ring_test_ring,
-+	.test_ib = uvd_v6_0_enc_ring_test_ib,
-+	.insert_nop = amdgpu_ring_insert_nop,
-+	.insert_end = uvd_v6_0_enc_ring_insert_end,
-+	.pad_ib = amdgpu_ring_generic_pad_ib,
-+	.begin_use = amdgpu_uvd_ring_begin_use,
-+	.end_use = amdgpu_uvd_ring_end_use,
-+};
-+
- static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
- {
- 	if (adev->asic_type >= CHIP_POLARIS10) {
-@@ -1162,6 +1634,16 @@ static void uvd_v6_0_set_ring_funcs(stru
- 	}
- }
- 
-+static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
-+{
-+	int i;
-+
-+	for (i = 0; i < adev->uvd.num_enc_rings; ++i)
-+		adev->uvd.ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
-+
-+	DRM_INFO("UVD ENC is enabled in VM mode\n");
-+}
-+
- static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
- 	.set = uvd_v6_0_set_interrupt_state,
- 	.process = uvd_v6_0_process_interrupt,
-@@ -1169,7 +1651,11 @@ static const struct amdgpu_irq_src_funcs
- 
- static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
- {
--	adev->uvd.irq.num_types = 1;
-+	if (uvd_v6_0_enc_support(adev))
-+		adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
-+	else
-+		adev->uvd.irq.num_types = 1;
-+
- 	adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
- }
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c	2017-12-14 06:39:58.394903553 +0100
-@@ -184,7 +184,7 @@ static int uvd_v7_0_enc_ring_test_ring(s
- 	}
- 
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n",
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
- 			 ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed\n",
-@@ -359,7 +359,7 @@ static int uvd_v7_0_enc_ring_test_ib(str
- 	} else if (r < 0) {
- 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
- 	} else {
--		DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
-+		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
- 		r = 0;
- 	}
- error:
-@@ -418,7 +418,7 @@ static int uvd_v7_0_sw_init(void *handle
- 	ring = &adev->uvd.ring_enc[0];
- 	rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
- 	r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
--				  rq, amdgpu_sched_jobs);
-+				  rq, amdgpu_sched_jobs, NULL);
- 	if (r) {
- 		DRM_ERROR("Failed setting up UVD ENC run queue.\n");
- 		return r;
-@@ -592,11 +592,7 @@ static int uvd_v7_0_suspend(void *handle
- 	if (r)
- 		return r;
- 
--	/* Skip this for APU for now */
--	if (!(adev->flags & AMD_IS_APU))
--		r = amdgpu_uvd_suspend(adev);
--
--	return r;
-+	return amdgpu_uvd_suspend(adev);
- }
- 
- static int uvd_v7_0_resume(void *handle)
-@@ -604,12 +600,10 @@ static int uvd_v7_0_resume(void *handle)
- 	int r;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- 
--	/* Skip this for APU for now */
--	if (!(adev->flags & AMD_IS_APU)) {
--		r = amdgpu_uvd_resume(adev);
--		if (r)
--			return r;
--	}
-+	r = amdgpu_uvd_resume(adev);
-+	if (r)
-+		return r;
-+
- 	return uvd_v7_0_hw_init(adev);
- }
- 
-@@ -622,7 +616,7 @@ static int uvd_v7_0_resume(void *handle)
-  */
- static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
- {
--	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
-+	uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
- 	uint32_t offset;
- 
- 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
-@@ -1161,7 +1155,7 @@ static void uvd_v7_0_ring_emit_hdp_flush
-  */
- static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
- {
--	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0));
-+	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0));
- 	amdgpu_ring_write(ring, 1);
- }
- 
-@@ -1198,7 +1192,7 @@ static int uvd_v7_0_ring_test_ring(struc
- 	}
- 
- 	if (i < adev->usec_timeout) {
--		DRM_INFO("ring test on %d succeeded in %d usecs\n",
-+		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
- 			 ring->idx, i);
- 	} else {
- 		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c	2017-12-14 06:39:58.394903553 +0100
-@@ -1011,10 +1011,6 @@ static int vce_v4_0_process_interrupt(st
- {
- 	DRM_DEBUG("IH: VCE\n");
- 
--	WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_STATUS),
--			VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK,
--			~VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK);
--
- 	switch (entry->src_data[0]) {
- 	case 0:
- 	case 1:
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c	2017-12-14 06:39:58.394903553 +0100
-@@ -812,7 +812,7 @@ static void vcn_v1_0_dec_ring_emit_fence
-  */
- static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
- {
--	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0));
-+	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0));
- 	amdgpu_ring_write(ring, 1);
- }
- 
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/vega10_ih.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/vega10_ih.c	2017-12-14 06:39:58.394903553 +0100
-@@ -46,11 +46,11 @@ static void vega10_ih_set_interrupt_func
-  */
- static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
- {
--	u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
-+	u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
- 
- 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
- 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
--	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl);
-+	WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
- 	adev->irq.ih.enabled = true;
- }
- 
-@@ -63,14 +63,14 @@ static void vega10_ih_enable_interrupts(
-  */
- static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
- {
--	u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
-+	u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
- 
- 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
- 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
--	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl);
-+	WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
- 	/* set rptr, wptr to 0 */
--	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0);
--	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0);
-+	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
-+	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
- 	adev->irq.ih.enabled = false;
- 	adev->irq.ih.rptr = 0;
- }
-@@ -102,15 +102,15 @@ static int vega10_ih_irq_init(struct amd
- 	else
- 		nbio_v6_1_ih_control(adev);
- 
--	ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
-+	ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
- 	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
- 	if (adev->irq.ih.use_bus_addr) {
--		WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.rb_dma_addr >> 8);
--		WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff);
-+		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
-+		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff);
- 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1);
- 	} else {
--		WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.gpu_addr >> 8);
--		WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), (adev->irq.ih.gpu_addr >> 40) & 0xff);
-+		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
-+		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev->irq.ih.gpu_addr >> 40) & 0xff);
- 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4);
- 	}
- 	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
-@@ -126,21 +126,21 @@ static int vega10_ih_irq_init(struct amd
- 	if (adev->irq.msi_enabled)
- 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
- 
--	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl);
-+	WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
- 
- 	/* set the writeback address whether it's enabled or not */
- 	if (adev->irq.ih.use_bus_addr)
- 		wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
- 	else
- 		wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
--	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO), lower_32_bits(wptr_off));
--	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI), upper_32_bits(wptr_off) & 0xFF);
-+	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
-+	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
- 
- 	/* set rptr, wptr to 0 */
--	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0);
--	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0);
-+	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
-+	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
- 
--	ih_doorbell_rtpr = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR));
-+	ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR);
- 	if (adev->irq.ih.use_doorbell) {
- 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
- 						 OFFSET, adev->irq.ih.doorbell_index);
-@@ -150,20 +150,20 @@ static int vega10_ih_irq_init(struct amd
- 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
- 						 ENABLE, 0);
- 	}
--	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR), ih_doorbell_rtpr);
-+	WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
- 	if (adev->flags & AMD_IS_APU)
- 		nbio_v7_0_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index);
- 	else
- 		nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index);
- 
--	tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL));
-+	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
- 	tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
- 			    CLIENT18_IS_STORM_CLIENT, 1);
--	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL), tmp);
-+	WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp);
- 
--	tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_INT_FLOOD_CNTL));
-+	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL);
- 	tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
--	WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_INT_FLOOD_CNTL), tmp);
-+	WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp);
- 
- 	pci_set_master(adev->pdev);
- 
-@@ -219,14 +219,95 @@ static u32 vega10_ih_get_wptr(struct amd
- 			wptr, adev->irq.ih.rptr, tmp);
- 		adev->irq.ih.rptr = tmp;
- 
--		tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
-+		tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
- 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
--		WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);
-+		WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);
- 	}
- 	return (wptr & adev->irq.ih.ptr_mask);
- }
- 
- /**
-+ * vega10_ih_prescreen_iv - prescreen an interrupt vector
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Returns true if the interrupt vector should be further processed.
-+ */
-+static bool vega10_ih_prescreen_iv(struct amdgpu_device *adev)
-+{
-+	u32 ring_index = adev->irq.ih.rptr >> 2;
-+	u32 dw0, dw3, dw4, dw5;
-+	u16 pasid;
-+	u64 addr, key;
-+	struct amdgpu_vm *vm;
-+	int r;
-+
-+	dw0 = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
-+	dw3 = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
-+	dw4 = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]);
-+	dw5 = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]);
-+
-+	/* Filter retry page faults, let only the first one pass. If
-+	 * there are too many outstanding faults, ignore them until
-+	 * some faults get cleared.
-+	 */
-+	switch (dw0 & 0xff) {
-+	case AMDGPU_IH_CLIENTID_VMC:
-+	case AMDGPU_IH_CLIENTID_UTCL2:
-+		break;
-+	default:
-+		/* Not a VM fault */
-+		return true;
-+	}
-+
-+	pasid = dw3 & 0xffff;
-+	/* No PASID, can't identify faulting process */
-+	if (!pasid)
-+		return true;
-+
-+	/* Not a retry fault, check fault credit */
-+	if (!(dw5 & 0x80)) {
-+		if (!amdgpu_vm_pasid_fault_credit(adev, pasid))
-+			goto ignore_iv;
-+		return true;
-+	}
-+
-+	addr = ((u64)(dw5 & 0xf) << 44) | ((u64)dw4 << 12);
-+	key = AMDGPU_VM_FAULT(pasid, addr);
-+	r = amdgpu_ih_add_fault(adev, key);
-+
-+	/* Hash table is full or the fault is already being processed,
-+	 * ignore further page faults
-+	 */
-+	if (r != 0)
-+		goto ignore_iv;
-+
-+	/* Track retry faults in per-VM fault FIFO. */
-+	spin_lock(&adev->vm_manager.pasid_lock);
-+	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
-+	spin_unlock(&adev->vm_manager.pasid_lock);
-+	if (WARN_ON_ONCE(!vm)) {
-+		/* VM not found, process it normally */
-+		amdgpu_ih_clear_fault(adev, key);
-+		return true;
-+	}
-+	/* No locking required with single writer and single reader */
-+	r = kfifo_put(&vm->faults, key);
-+	if (!r) {
-+		/* FIFO is full. Ignore it until there is space */
-+		amdgpu_ih_clear_fault(adev, key);
-+		goto ignore_iv;
-+	}
-+
-+	/* It's the first fault for this address, process it normally */
-+	return true;
-+
-+ignore_iv:
-+	adev->irq.ih.rptr += 32;
-+	return false;
-+}
-+
-+/**
-  * vega10_ih_decode_iv - decode an interrupt vector
-  *
-  * @adev: amdgpu_device pointer
-@@ -286,7 +367,7 @@ static void vega10_ih_set_rptr(struct am
- 			adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
- 		WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
- 	} else {
--		WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), adev->irq.ih.rptr);
-+		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, adev->irq.ih.rptr);
- 	}
- }
- 
-@@ -310,6 +391,14 @@ static int vega10_ih_sw_init(void *handl
- 	adev->irq.ih.use_doorbell = true;
- 	adev->irq.ih.doorbell_index = AMDGPU_DOORBELL64_IH << 1;
- 
-+	adev->irq.ih.faults = kmalloc(sizeof(*adev->irq.ih.faults), GFP_KERNEL);
-+	if (!adev->irq.ih.faults)
-+		return -ENOMEM;
-+	INIT_CHASH_TABLE(adev->irq.ih.faults->hash,
-+			 AMDGPU_PAGEFAULT_HASH_BITS, 8, 0);
-+	spin_lock_init(&adev->irq.ih.faults->lock);
-+	adev->irq.ih.faults->count = 0;
-+
- 	r = amdgpu_irq_init(adev);
- 
- 	return r;
-@@ -322,6 +411,9 @@ static int vega10_ih_sw_fini(void *handl
- 	amdgpu_irq_fini(adev);
- 	amdgpu_ih_ring_fini(adev);
- 
-+	kfree(adev->irq.ih.faults);
-+	adev->irq.ih.faults = NULL;
-+
- 	return 0;
- }
- 
-@@ -410,6 +502,7 @@ const struct amd_ip_funcs vega10_ih_ip_f
- 
- static const struct amdgpu_ih_funcs vega10_ih_funcs = {
- 	.get_wptr = vega10_ih_get_wptr,
-+	.prescreen_iv = vega10_ih_prescreen_iv,
- 	.decode_iv = vega10_ih_decode_iv,
- 	.set_rptr = vega10_ih_set_rptr
- };
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/vi.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/vi.c	2017-12-14 06:39:58.394903553 +0100
-@@ -77,6 +77,7 @@
- #endif
- #include "dce_virtual.h"
- #include "mxgpu_vi.h"
-+#include "amdgpu_dm.h"
- 
- /*
-  * Indirect registers accessor
-@@ -283,27 +284,27 @@ static void vi_init_golden_registers(str
- 	case CHIP_TOPAZ:
- 		amdgpu_program_register_sequence(adev,
- 						 iceland_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
-+						 ARRAY_SIZE(iceland_mgcg_cgcg_init));
- 		break;
- 	case CHIP_FIJI:
- 		amdgpu_program_register_sequence(adev,
- 						 fiji_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
-+						 ARRAY_SIZE(fiji_mgcg_cgcg_init));
- 		break;
- 	case CHIP_TONGA:
- 		amdgpu_program_register_sequence(adev,
- 						 tonga_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
-+						 ARRAY_SIZE(tonga_mgcg_cgcg_init));
- 		break;
- 	case CHIP_CARRIZO:
- 		amdgpu_program_register_sequence(adev,
- 						 cz_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
-+						 ARRAY_SIZE(cz_mgcg_cgcg_init));
- 		break;
- 	case CHIP_STONEY:
- 		amdgpu_program_register_sequence(adev,
- 						 stoney_mgcg_cgcg_init,
--						 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
-+						 ARRAY_SIZE(stoney_mgcg_cgcg_init));
- 		break;
- 	case CHIP_POLARIS11:
- 	case CHIP_POLARIS10:
-@@ -1254,7 +1255,6 @@ static int vi_common_set_clockgating_sta
- 	uint32_t msg_id, pp_state = 0;
- 	uint32_t pp_support_state = 0;
- 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--	void *pp_handle = adev->powerplay.pp_handle;
- 
- 	if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
- 		if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
-@@ -1271,7 +1271,8 @@ static int vi_common_set_clockgating_sta
- 			       PP_BLOCK_SYS_MC,
- 			       pp_support_state,
- 			       pp_state);
--		amd_set_clockgating_by_smu(pp_handle, msg_id);
-+		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
-+			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
- 	}
- 
- 	if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
-@@ -1289,7 +1290,8 @@ static int vi_common_set_clockgating_sta
- 			       PP_BLOCK_SYS_SDMA,
- 			       pp_support_state,
- 			       pp_state);
--		amd_set_clockgating_by_smu(pp_handle, msg_id);
-+		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
-+			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
- 	}
- 
- 	if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
-@@ -1307,7 +1309,8 @@ static int vi_common_set_clockgating_sta
- 			       PP_BLOCK_SYS_HDP,
- 			       pp_support_state,
- 			       pp_state);
--		amd_set_clockgating_by_smu(pp_handle, msg_id);
-+		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
-+			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
- 	}
- 
- 
-@@ -1321,7 +1324,8 @@ static int vi_common_set_clockgating_sta
- 			       PP_BLOCK_SYS_BIF,
- 			       PP_STATE_SUPPORT_LS,
- 			        pp_state);
--		amd_set_clockgating_by_smu(pp_handle, msg_id);
-+		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
-+			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
- 	}
- 	if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
- 		if (state == AMD_CG_STATE_UNGATE)
-@@ -1333,7 +1337,8 @@ static int vi_common_set_clockgating_sta
- 			       PP_BLOCK_SYS_BIF,
- 			       PP_STATE_SUPPORT_CG,
- 			       pp_state);
--		amd_set_clockgating_by_smu(pp_handle, msg_id);
-+		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
-+			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
- 	}
- 
- 	if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
-@@ -1347,7 +1352,8 @@ static int vi_common_set_clockgating_sta
- 			       PP_BLOCK_SYS_DRM,
- 			       PP_STATE_SUPPORT_LS,
- 			       pp_state);
--		amd_set_clockgating_by_smu(pp_handle, msg_id);
-+		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
-+			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
- 	}
- 
- 	if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
-@@ -1361,7 +1367,8 @@ static int vi_common_set_clockgating_sta
- 			       PP_BLOCK_SYS_ROM,
- 			       PP_STATE_SUPPORT_CG,
- 			       pp_state);
--		amd_set_clockgating_by_smu(pp_handle, msg_id);
-+		if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
-+			amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
- 	}
- 	return 0;
- }
-@@ -1496,6 +1503,10 @@ int vi_set_ip_blocks(struct amdgpu_devic
- 		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
- 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
- 			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
-+#if defined(CONFIG_DRM_AMD_DC)
-+		else if (amdgpu_device_has_dc_support(adev))
-+			amdgpu_ip_block_add(adev, &dm_ip_block);
-+#endif
- 		else
- 			amdgpu_ip_block_add(adev, &dce_v10_1_ip_block);
- 		amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
-@@ -1512,6 +1523,10 @@ int vi_set_ip_blocks(struct amdgpu_devic
- 		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
- 		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
- 			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
-+#if defined(CONFIG_DRM_AMD_DC)
-+		else if (amdgpu_device_has_dc_support(adev))
-+			amdgpu_ip_block_add(adev, &dm_ip_block);
-+#endif
- 		else
- 			amdgpu_ip_block_add(adev, &dce_v10_0_ip_block);
- 		amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
-@@ -1530,6 +1545,10 @@ int vi_set_ip_blocks(struct amdgpu_devic
- 		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
- 		if (adev->enable_virtual_display)
- 			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
-+#if defined(CONFIG_DRM_AMD_DC)
-+		else if (amdgpu_device_has_dc_support(adev))
-+			amdgpu_ip_block_add(adev, &dm_ip_block);
-+#endif
- 		else
- 			amdgpu_ip_block_add(adev, &dce_v11_2_ip_block);
- 		amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
-@@ -1544,6 +1563,10 @@ int vi_set_ip_blocks(struct amdgpu_devic
- 		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
- 		if (adev->enable_virtual_display)
- 			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
-+#if defined(CONFIG_DRM_AMD_DC)
-+		else if (amdgpu_device_has_dc_support(adev))
-+			amdgpu_ip_block_add(adev, &dm_ip_block);
-+#endif
- 		else
- 			amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
- 		amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
-@@ -1561,6 +1584,10 @@ int vi_set_ip_blocks(struct amdgpu_devic
- 		amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
- 		if (adev->enable_virtual_display)
- 			amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
-+#if defined(CONFIG_DRM_AMD_DC)
-+		else if (amdgpu_device_has_dc_support(adev))
-+			amdgpu_ip_block_add(adev, &dm_ip_block);
-+#endif
- 		else
- 			amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
- 		amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block);
---- linux-4.14/drivers/gpu/drm/amd/amdgpu/vid.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdgpu/vid.h	2017-12-14 06:39:58.394903553 +0100
-@@ -465,6 +465,16 @@
- #define VCE_CMD_UPDATE_PTB      0x00000107
- #define VCE_CMD_FLUSH_TLB       0x00000108
- 
-+/* HEVC ENC */
-+#define HEVC_ENC_CMD_NO_OP         0x00000000
-+#define HEVC_ENC_CMD_END           0x00000001
-+#define HEVC_ENC_CMD_FENCE         0x00000003
-+#define HEVC_ENC_CMD_TRAP          0x00000004
-+#define HEVC_ENC_CMD_IB_VM         0x00000102
-+#define HEVC_ENC_CMD_WAIT_GE       0x00000106
-+#define HEVC_ENC_CMD_UPDATE_PTB    0x00000107
-+#define HEVC_ENC_CMD_FLUSH_TLB     0x00000108
-+
- /* mmPA_SC_RASTER_CONFIG mask */
- #define RB_MAP_PKR0(x)				((x) << 0)
- #define RB_MAP_PKR0_MASK			(0x3 << 0)
---- linux-4.14/drivers/gpu/drm/amd/amdkfd/kfd_device.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdkfd/kfd_device.c	2017-12-14 06:39:58.394903553 +0100
-@@ -168,13 +168,6 @@ static bool device_iommu_pasid_init(stru
- 	pasid_limit = min_t(unsigned int,
- 			(unsigned int)(1 << kfd->device_info->max_pasid_bits),
- 			iommu_info.max_pasids);
--	/*
--	 * last pasid is used for kernel queues doorbells
--	 * in the future the last pasid might be used for a kernel thread.
--	 */
--	pasid_limit = min_t(unsigned int,
--				pasid_limit,
--				kfd->doorbell_process_limit - 1);
- 
- 	err = amd_iommu_init_device(kfd->pdev, pasid_limit);
- 	if (err < 0) {
---- linux-4.14/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c	2017-12-14 06:39:58.394903553 +0100
-@@ -24,16 +24,15 @@
- #include <linux/mman.h>
- #include <linux/slab.h>
- #include <linux/io.h>
-+#include <linux/idr.h>
- 
- /*
-- * This extension supports a kernel level doorbells management for
-- * the kernel queues.
-- * Basically the last doorbells page is devoted to kernel queues
-- * and that's assures that any user process won't get access to the
-- * kernel doorbells page
-+ * This extension supports a kernel level doorbells management for the
-+ * kernel queues using the first doorbell page reserved for the kernel.
-  */
- 
--#define KERNEL_DOORBELL_PASID 1
-+static DEFINE_IDA(doorbell_ida);
-+static unsigned int max_doorbell_slices;
- #define KFD_SIZE_OF_DOORBELL_IN_BYTES 4
- 
- /*
-@@ -84,13 +83,16 @@ int kfd_doorbell_init(struct kfd_dev *kf
- 			(doorbell_aperture_size - doorbell_start_offset) /
- 						doorbell_process_allocation();
- 	else
--		doorbell_process_limit = 0;
-+		return -ENOSPC;
-+
-+	if (!max_doorbell_slices ||
-+	    doorbell_process_limit < max_doorbell_slices)
-+		max_doorbell_slices = doorbell_process_limit;
- 
- 	kfd->doorbell_base = kfd->shared_resources.doorbell_physical_address +
- 				doorbell_start_offset;
- 
- 	kfd->doorbell_id_offset = doorbell_start_offset / sizeof(u32);
--	kfd->doorbell_process_limit = doorbell_process_limit - 1;
- 
- 	kfd->doorbell_kernel_ptr = ioremap(kfd->doorbell_base,
- 						doorbell_process_allocation());
-@@ -185,11 +187,10 @@ u32 __iomem *kfd_get_kernel_doorbell(str
- 		return NULL;
- 
- 	/*
--	 * Calculating the kernel doorbell offset using "faked" kernel
--	 * pasid that allocated for kernel queues only
-+	 * Calculating the kernel doorbell offset using the first
-+	 * doorbell page.
- 	 */
--	*doorbell_off = KERNEL_DOORBELL_PASID * (doorbell_process_allocation() /
--							sizeof(u32)) + inx;
-+	*doorbell_off = kfd->doorbell_id_offset + inx;
- 
- 	pr_debug("Get kernel queue doorbell\n"
- 			 "     doorbell offset   == 0x%08X\n"
-@@ -228,11 +229,12 @@ unsigned int kfd_queue_id_to_doorbell(st
- {
- 	/*
- 	 * doorbell_id_offset accounts for doorbells taken by KGD.
--	 * pasid * doorbell_process_allocation/sizeof(u32) adjusts
--	 * to the process's doorbells
-+	 * index * doorbell_process_allocation/sizeof(u32) adjusts to
-+	 * the process's doorbells.
- 	 */
- 	return kfd->doorbell_id_offset +
--		process->pasid * (doorbell_process_allocation()/sizeof(u32)) +
-+		process->doorbell_index
-+		* doorbell_process_allocation() / sizeof(u32) +
- 		queue_id;
- }
- 
-@@ -250,5 +252,21 @@ phys_addr_t kfd_get_process_doorbells(st
- 					struct kfd_process *process)
- {
- 	return dev->doorbell_base +
--		process->pasid * doorbell_process_allocation();
-+		process->doorbell_index * doorbell_process_allocation();
-+}
-+
-+int kfd_alloc_process_doorbells(struct kfd_process *process)
-+{
-+	int r = ida_simple_get(&doorbell_ida, 1, max_doorbell_slices,
-+				GFP_KERNEL);
-+	if (r > 0)
-+		process->doorbell_index = r;
-+
-+	return r;
-+}
-+
-+void kfd_free_process_doorbells(struct kfd_process *process)
-+{
-+	if (process->doorbell_index)
-+		ida_simple_remove(&doorbell_ida, process->doorbell_index);
- }
---- linux-4.14/drivers/gpu/drm/amd/amdkfd/kfd_module.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdkfd/kfd_module.c	2017-12-14 06:39:58.394903553 +0100
-@@ -103,10 +103,6 @@ static int __init kfd_module_init(void)
- 		return -1;
- 	}
- 
--	err = kfd_pasid_init();
--	if (err < 0)
--		return err;
--
- 	err = kfd_chardev_init();
- 	if (err < 0)
- 		goto err_ioctl;
-@@ -126,7 +122,6 @@ static int __init kfd_module_init(void)
- err_topology:
- 	kfd_chardev_exit();
- err_ioctl:
--	kfd_pasid_exit();
- 	return err;
- }
- 
-@@ -137,7 +132,6 @@ static void __exit kfd_module_exit(void)
- 	kfd_process_destroy_wq();
- 	kfd_topology_shutdown();
- 	kfd_chardev_exit();
--	kfd_pasid_exit();
- 	dev_info(kfd_device, "Removed module\n");
- }
- 
---- linux-4.14/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c	2017-12-14 06:39:58.394903553 +0100
-@@ -20,78 +20,64 @@
-  * OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
--#include <linux/slab.h>
- #include <linux/types.h>
- #include "kfd_priv.h"
- 
--static unsigned long *pasid_bitmap;
--static unsigned int pasid_limit;
--static DEFINE_MUTEX(pasid_mutex);
--
--int kfd_pasid_init(void)
--{
--	pasid_limit = KFD_MAX_NUM_OF_PROCESSES;
--
--	pasid_bitmap = kcalloc(BITS_TO_LONGS(pasid_limit), sizeof(long),
--				GFP_KERNEL);
--	if (!pasid_bitmap)
--		return -ENOMEM;
--
--	set_bit(0, pasid_bitmap); /* PASID 0 is reserved. */
--
--	return 0;
--}
--
--void kfd_pasid_exit(void)
--{
--	kfree(pasid_bitmap);
--}
-+static unsigned int pasid_bits = 16;
-+static const struct kfd2kgd_calls *kfd2kgd;
- 
- bool kfd_set_pasid_limit(unsigned int new_limit)
- {
--	if (new_limit < pasid_limit) {
--		bool ok;
-+	if (new_limit < 2)
-+		return false;
- 
--		mutex_lock(&pasid_mutex);
-+	if (new_limit < (1U << pasid_bits)) {
-+		if (kfd2kgd)
-+			/* We've already allocated user PASIDs, too late to
-+			 * change the limit
-+			 */
-+			return false;
- 
--		/* ensure that no pasids >= new_limit are in-use */
--		ok = (find_next_bit(pasid_bitmap, pasid_limit, new_limit) ==
--								pasid_limit);
--		if (ok)
--			pasid_limit = new_limit;
--
--		mutex_unlock(&pasid_mutex);
--
--		return ok;
-+		while (new_limit < (1U << pasid_bits))
-+			pasid_bits--;
- 	}
- 
- 	return true;
- }
- 
--inline unsigned int kfd_get_pasid_limit(void)
-+unsigned int kfd_get_pasid_limit(void)
- {
--	return pasid_limit;
-+	return 1U << pasid_bits;
- }
- 
- unsigned int kfd_pasid_alloc(void)
- {
--	unsigned int found;
-+	int r;
- 
--	mutex_lock(&pasid_mutex);
-+	/* Find the first best KFD device for calling KGD */
-+	if (!kfd2kgd) {
-+		struct kfd_dev *dev = NULL;
-+		unsigned int i = 0;
-+
-+		while ((dev = kfd_topology_enum_kfd_devices(i)) != NULL) {
-+			if (dev && dev->kfd2kgd) {
-+				kfd2kgd = dev->kfd2kgd;
-+				break;
-+			}
-+			i++;
-+		}
- 
--	found = find_first_zero_bit(pasid_bitmap, pasid_limit);
--	if (found == pasid_limit)
--		found = 0;
--	else
--		set_bit(found, pasid_bitmap);
-+		if (!kfd2kgd)
-+			return false;
-+	}
- 
--	mutex_unlock(&pasid_mutex);
-+	r = kfd2kgd->alloc_pasid(pasid_bits);
- 
--	return found;
-+	return r > 0 ? r : 0;
- }
- 
- void kfd_pasid_free(unsigned int pasid)
- {
--	if (!WARN_ON(pasid == 0 || pasid >= pasid_limit))
--		clear_bit(pasid, pasid_bitmap);
-+	if (kfd2kgd)
-+		kfd2kgd->free_pasid(pasid);
- }
---- linux-4.14/drivers/gpu/drm/amd/amdkfd/kfd_priv.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdkfd/kfd_priv.h	2017-12-14 06:39:58.395903553 +0100
-@@ -157,9 +157,6 @@ struct kfd_dev {
- 					 * to HW doorbell, GFX reserved some
- 					 * at the start)
- 					 */
--	size_t doorbell_process_limit;	/* Number of processes we have doorbell
--					 * space for.
--					 */
- 	u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells
- 					   * page used by kernel queue
- 					   */
-@@ -495,6 +492,7 @@ struct kfd_process {
- 	struct rcu_head	rcu;
- 
- 	unsigned int pasid;
-+	unsigned int doorbell_index;
- 
- 	/*
- 	 * List of kfd_process_device structures,
-@@ -584,6 +582,10 @@ void write_kernel_doorbell(u32 __iomem *
- unsigned int kfd_queue_id_to_doorbell(struct kfd_dev *kfd,
- 					struct kfd_process *process,
- 					unsigned int queue_id);
-+phys_addr_t kfd_get_process_doorbells(struct kfd_dev *dev,
-+					struct kfd_process *process);
-+int kfd_alloc_process_doorbells(struct kfd_process *process);
-+void kfd_free_process_doorbells(struct kfd_process *process);
- 
- /* GTT Sub-Allocator */
- 
-@@ -695,8 +697,6 @@ int pm_send_unmap_queue(struct packet_ma
- void pm_release_ib(struct packet_manager *pm);
- 
- uint64_t kfd_get_number_elems(struct kfd_dev *kfd);
--phys_addr_t kfd_get_process_doorbells(struct kfd_dev *dev,
--					struct kfd_process *process);
- 
- /* Events */
- extern const struct kfd_event_interrupt_class event_interrupt_class_cik;
---- linux-4.14/drivers/gpu/drm/amd/amdkfd/kfd_process.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/amdkfd/kfd_process.c	2017-12-14 06:39:58.395903553 +0100
-@@ -183,6 +183,7 @@ static void kfd_process_wq_release(struc
- 	kfd_event_free_process(p);
- 
- 	kfd_pasid_free(p->pasid);
-+	kfd_free_process_doorbells(p);
- 
- 	mutex_unlock(&p->mutex);
- 
-@@ -288,6 +289,9 @@ static struct kfd_process *create_proces
- 	if (process->pasid == 0)
- 		goto err_alloc_pasid;
- 
-+	if (kfd_alloc_process_doorbells(process) < 0)
-+		goto err_alloc_doorbells;
-+
- 	mutex_init(&process->mutex);
- 
- 	process->mm = thread->mm;
-@@ -329,6 +333,8 @@ err_process_pqm_init:
- 	mmu_notifier_unregister_no_release(&process->mmu_notifier, process->mm);
- err_mmu_notifier:
- 	mutex_destroy(&process->mutex);
-+	kfd_free_process_doorbells(process);
-+err_alloc_doorbells:
- 	kfd_pasid_free(process->pasid);
- err_alloc_pasid:
- 	kfree(process->queues);
---- linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c.0130~	2017-12-14 06:39:58.396903554 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c	2017-12-14 06:39:58.396903554 +0100
-@@ -0,0 +1,5033 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services_types.h"
-+#include "dc.h"
-+#include "dc/inc/core_types.h"
-+
-+#include "vid.h"
-+#include "amdgpu.h"
-+#include "amdgpu_display.h"
-+#include "atom.h"
-+#include "amdgpu_dm.h"
-+#include "amdgpu_pm.h"
-+
-+#include "amd_shared.h"
-+#include "amdgpu_dm_irq.h"
-+#include "dm_helpers.h"
-+#include "dm_services_types.h"
-+#include "amdgpu_dm_mst_types.h"
-+
-+#include "ivsrcid/ivsrcid_vislands30.h"
-+
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/version.h>
-+#include <linux/types.h>
-+
-+#include <drm/drmP.h>
-+#include <drm/drm_atomic.h>
-+#include <drm/drm_atomic_helper.h>
-+#include <drm/drm_dp_mst_helper.h>
-+#include <drm/drm_fb_helper.h>
-+#include <drm/drm_edid.h>
-+
-+#include "modules/inc/mod_freesync.h"
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+#include "ivsrcid/irqsrcs_dcn_1_0.h"
-+
-+#include "raven1/DCN/dcn_1_0_offset.h"
-+#include "raven1/DCN/dcn_1_0_sh_mask.h"
-+#include "vega10/soc15ip.h"
-+
-+#include "soc15_common.h"
-+#endif
-+
-+#include "modules/inc/mod_freesync.h"
-+
-+#include "i2caux_interface.h"
-+
-+/* basic init/fini API */
-+static int amdgpu_dm_init(struct amdgpu_device *adev);
-+static void amdgpu_dm_fini(struct amdgpu_device *adev);
-+
-+/* initializes drm_device display related structures, based on the information
-+ * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
-+ * drm_encoder, drm_mode_config
-+ *
-+ * Returns 0 on success
-+ */
-+static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
-+/* removes and deallocates the drm structures, created by the above function */
-+static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
-+
-+static void
-+amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
-+
-+static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
-+				struct amdgpu_plane *aplane,
-+				unsigned long possible_crtcs);
-+static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
-+			       struct drm_plane *plane,
-+			       uint32_t link_index);
-+static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
-+				    struct amdgpu_dm_connector *amdgpu_dm_connector,
-+				    uint32_t link_index,
-+				    struct amdgpu_encoder *amdgpu_encoder);
-+static int amdgpu_dm_encoder_init(struct drm_device *dev,
-+				  struct amdgpu_encoder *aencoder,
-+				  uint32_t link_index);
-+
-+static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
-+
-+static int amdgpu_dm_atomic_commit(struct drm_device *dev,
-+				   struct drm_atomic_state *state,
-+				   bool nonblock);
-+
-+static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
-+
-+static int amdgpu_dm_atomic_check(struct drm_device *dev,
-+				  struct drm_atomic_state *state);
-+
-+
-+
-+
-+static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
-+	DRM_PLANE_TYPE_PRIMARY,
-+	DRM_PLANE_TYPE_PRIMARY,
-+	DRM_PLANE_TYPE_PRIMARY,
-+	DRM_PLANE_TYPE_PRIMARY,
-+	DRM_PLANE_TYPE_PRIMARY,
-+	DRM_PLANE_TYPE_PRIMARY,
-+};
-+
-+static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
-+	DRM_PLANE_TYPE_PRIMARY,
-+	DRM_PLANE_TYPE_PRIMARY,
-+	DRM_PLANE_TYPE_PRIMARY,
-+	DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
-+};
-+
-+static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
-+	DRM_PLANE_TYPE_PRIMARY,
-+	DRM_PLANE_TYPE_PRIMARY,
-+	DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
-+};
-+
-+/*
-+ * dm_vblank_get_counter
-+ *
-+ * @brief
-+ * Get counter for number of vertical blanks
-+ *
-+ * @param
-+ * struct amdgpu_device *adev - [in] desired amdgpu device
-+ * int disp_idx - [in] which CRTC to get the counter from
-+ *
-+ * @return
-+ * Counter for vertical blanks
-+ */
-+static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
-+{
-+	if (crtc >= adev->mode_info.num_crtc)
-+		return 0;
-+	else {
-+		struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
-+		struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
-+				acrtc->base.state);
-+
-+
-+		if (acrtc_state->stream == NULL) {
-+			DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
-+				  crtc);
-+			return 0;
-+		}
-+
-+		return dc_stream_get_vblank_counter(acrtc_state->stream);
-+	}
-+}
-+
-+static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
-+				  u32 *vbl, u32 *position)
-+{
-+	uint32_t v_blank_start, v_blank_end, h_position, v_position;
-+
-+	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
-+		return -EINVAL;
-+	else {
-+		struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
-+		struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
-+						acrtc->base.state);
-+
-+		if (acrtc_state->stream ==  NULL) {
-+			DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
-+				  crtc);
-+			return 0;
-+		}
-+
-+		/*
-+		 * TODO rework base driver to use values directly.
-+		 * for now parse it back into reg-format
-+		 */
-+		dc_stream_get_scanoutpos(acrtc_state->stream,
-+					 &v_blank_start,
-+					 &v_blank_end,
-+					 &h_position,
-+					 &v_position);
-+
-+		*position = v_position | (h_position << 16);
-+		*vbl = v_blank_start | (v_blank_end << 16);
-+	}
-+
-+	return 0;
-+}
-+
-+static bool dm_is_idle(void *handle)
-+{
-+	/* XXX todo */
-+	return true;
-+}
-+
-+static int dm_wait_for_idle(void *handle)
-+{
-+	/* XXX todo */
-+	return 0;
-+}
-+
-+static bool dm_check_soft_reset(void *handle)
-+{
-+	return false;
-+}
-+
-+static int dm_soft_reset(void *handle)
-+{
-+	/* XXX todo */
-+	return 0;
-+}
-+
-+static struct amdgpu_crtc *
-+get_crtc_by_otg_inst(struct amdgpu_device *adev,
-+		     int otg_inst)
-+{
-+	struct drm_device *dev = adev->ddev;
-+	struct drm_crtc *crtc;
-+	struct amdgpu_crtc *amdgpu_crtc;
-+
-+	/*
-+	 * following if is check inherited from both functions where this one is
-+	 * used now. Need to be checked why it could happen.
-+	 */
-+	if (otg_inst == -1) {
-+		WARN_ON(1);
-+		return adev->mode_info.crtcs[0];
-+	}
-+
-+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-+		amdgpu_crtc = to_amdgpu_crtc(crtc);
-+
-+		if (amdgpu_crtc->otg_inst == otg_inst)
-+			return amdgpu_crtc;
-+	}
-+
-+	return NULL;
-+}
-+
-+static void dm_pflip_high_irq(void *interrupt_params)
-+{
-+	struct amdgpu_crtc *amdgpu_crtc;
-+	struct common_irq_params *irq_params = interrupt_params;
-+	struct amdgpu_device *adev = irq_params->adev;
-+	unsigned long flags;
-+
-+	amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
-+
-+	/* IRQ could occur when in initial stage */
-+	/*TODO work and BO cleanup */
-+	if (amdgpu_crtc == NULL) {
-+		DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
-+		return;
-+	}
-+
-+	spin_lock_irqsave(&adev->ddev->event_lock, flags);
-+
-+	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
-+		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
-+						 amdgpu_crtc->pflip_status,
-+						 AMDGPU_FLIP_SUBMITTED,
-+						 amdgpu_crtc->crtc_id,
-+						 amdgpu_crtc);
-+		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
-+		return;
-+	}
-+
-+
-+	/* wakeup usersapce */
-+	if (amdgpu_crtc->event) {
-+		/* Update to correct count/ts if racing with vblank irq */
-+		drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
-+
-+		drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
-+
-+		/* page flip completed. clean up */
-+		amdgpu_crtc->event = NULL;
-+
-+	} else
-+		WARN_ON(1);
-+
-+	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
-+	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
-+
-+	DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
-+					__func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
-+
-+	drm_crtc_vblank_put(&amdgpu_crtc->base);
-+}
-+
-+static void dm_crtc_high_irq(void *interrupt_params)
-+{
-+	struct common_irq_params *irq_params = interrupt_params;
-+	struct amdgpu_device *adev = irq_params->adev;
-+	uint8_t crtc_index = 0;
-+	struct amdgpu_crtc *acrtc;
-+
-+	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
-+
-+	if (acrtc)
-+		crtc_index = acrtc->crtc_id;
-+
-+	drm_handle_vblank(adev->ddev, crtc_index);
-+}
-+
-+static int dm_set_clockgating_state(void *handle,
-+		  enum amd_clockgating_state state)
-+{
-+	return 0;
-+}
-+
-+static int dm_set_powergating_state(void *handle,
-+		  enum amd_powergating_state state)
-+{
-+	return 0;
-+}
-+
-+/* Prototypes of private functions */
-+static int dm_early_init(void* handle);
-+
-+static void hotplug_notify_work_func(struct work_struct *work)
-+{
-+	struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
-+	struct drm_device *dev = dm->ddev;
-+
-+	drm_kms_helper_hotplug_event(dev);
-+}
-+
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+#include "dal_asic_id.h"
-+/* Allocate memory for FBC compressed data  */
-+/* TODO: Dynamic allocation */
-+#define AMDGPU_FBC_SIZE    (3840 * 2160 * 4)
-+
-+static void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev)
-+{
-+	int r;
-+	struct dm_comressor_info *compressor = &adev->dm.compressor;
-+
-+	if (!compressor->bo_ptr) {
-+		r = amdgpu_bo_create_kernel(adev, AMDGPU_FBC_SIZE, PAGE_SIZE,
-+				AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr,
-+				&compressor->gpu_addr, &compressor->cpu_addr);
-+
-+		if (r)
-+			DRM_ERROR("DM: Failed to initialize fbc\n");
-+	}
-+
-+}
-+#endif
-+
-+
-+/* Init display KMS
-+ *
-+ * Returns 0 on success
-+ */
-+static int amdgpu_dm_init(struct amdgpu_device *adev)
-+{
-+	struct dc_init_data init_data;
-+	adev->dm.ddev = adev->ddev;
-+	adev->dm.adev = adev;
-+
-+	/* Zero all the fields */
-+	memset(&init_data, 0, sizeof(init_data));
-+
-+	/* initialize DAL's lock (for SYNC context use) */
-+	spin_lock_init(&adev->dm.dal_lock);
-+
-+	/* initialize DAL's mutex */
-+	mutex_init(&adev->dm.dal_mutex);
-+
-+	if(amdgpu_dm_irq_init(adev)) {
-+		DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
-+		goto error;
-+	}
-+
-+	init_data.asic_id.chip_family = adev->family;
-+
-+	init_data.asic_id.pci_revision_id = adev->rev_id;
-+	init_data.asic_id.hw_internal_rev = adev->external_rev_id;
-+
-+	init_data.asic_id.vram_width = adev->mc.vram_width;
-+	/* TODO: initialize init_data.asic_id.vram_type here!!!! */
-+	init_data.asic_id.atombios_base_address =
-+		adev->mode_info.atom_context->bios;
-+
-+	init_data.driver = adev;
-+
-+	adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
-+
-+	if (!adev->dm.cgs_device) {
-+		DRM_ERROR("amdgpu: failed to create cgs device.\n");
-+		goto error;
-+	}
-+
-+	init_data.cgs_device = adev->dm.cgs_device;
-+
-+	adev->dm.dal = NULL;
-+
-+	init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
-+
-+	if (amdgpu_dc_log)
-+		init_data.log_mask = DC_DEFAULT_LOG_MASK;
-+	else
-+		init_data.log_mask = DC_MIN_LOG_MASK;
-+
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+	if (adev->family == FAMILY_CZ)
-+		amdgpu_dm_initialize_fbc(adev);
-+	init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr;
-+#endif
-+	/* Display Core create. */
-+	adev->dm.dc = dc_create(&init_data);
-+
-+	if (adev->dm.dc) {
-+		DRM_INFO("Display Core initialized!\n");
-+	} else {
-+		DRM_INFO("Display Core failed to initialize!\n");
-+		goto error;
-+	}
-+
-+	INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
-+
-+	adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
-+	if (!adev->dm.freesync_module) {
-+		DRM_ERROR(
-+		"amdgpu: failed to initialize freesync_module.\n");
-+	} else
-+		DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
-+				adev->dm.freesync_module);
-+
-+	if (amdgpu_dm_initialize_drm_device(adev)) {
-+		DRM_ERROR(
-+		"amdgpu: failed to initialize sw for display support.\n");
-+		goto error;
-+	}
-+
-+	/* Update the actual used number of crtc */
-+	adev->mode_info.num_crtc = adev->dm.display_indexes_num;
-+
-+	/* TODO: Add_display_info? */
-+
-+	/* TODO use dynamic cursor width */
-+	adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
-+	adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
-+
-+	if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
-+		DRM_ERROR(
-+		"amdgpu: failed to initialize sw for display support.\n");
-+		goto error;
-+	}
-+
-+	DRM_DEBUG_DRIVER("KMS initialized.\n");
-+
-+	return 0;
-+error:
-+	amdgpu_dm_fini(adev);
-+
-+	return -1;
-+}
-+
-+static void amdgpu_dm_fini(struct amdgpu_device *adev)
-+{
-+	amdgpu_dm_destroy_drm_device(&adev->dm);
-+	/*
-+	 * TODO: pageflip, vlank interrupt
-+	 *
-+	 * amdgpu_dm_irq_fini(adev);
-+	 */
-+
-+	if (adev->dm.cgs_device) {
-+		amdgpu_cgs_destroy_device(adev->dm.cgs_device);
-+		adev->dm.cgs_device = NULL;
-+	}
-+	if (adev->dm.freesync_module) {
-+		mod_freesync_destroy(adev->dm.freesync_module);
-+		adev->dm.freesync_module = NULL;
-+	}
-+	/* DC Destroy TODO: Replace destroy DAL */
-+	if (adev->dm.dc)
-+		dc_destroy(&adev->dm.dc);
-+	return;
-+}
-+
-+static int dm_sw_init(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int dm_sw_fini(void *handle)
-+{
-+	return 0;
-+}
-+
-+static int detect_mst_link_for_all_connectors(struct drm_device *dev)
-+{
-+	struct amdgpu_dm_connector *aconnector;
-+	struct drm_connector *connector;
-+	int ret = 0;
-+
-+	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
-+
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+		aconnector = to_amdgpu_dm_connector(connector);
-+		if (aconnector->dc_link->type == dc_connection_mst_branch &&
-+		    aconnector->mst_mgr.aux) {
-+			DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
-+					aconnector, aconnector->base.base.id);
-+
-+			ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
-+			if (ret < 0) {
-+				DRM_ERROR("DM_MST: Failed to start MST\n");
-+				((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
-+				return ret;
-+				}
-+			}
-+	}
-+
-+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
-+	return ret;
-+}
-+
-+static int dm_late_init(void *handle)
-+{
-+	struct drm_device *dev = ((struct amdgpu_device *)handle)->ddev;
-+
-+	return detect_mst_link_for_all_connectors(dev);
-+}
-+
-+static void s3_handle_mst(struct drm_device *dev, bool suspend)
-+{
-+	struct amdgpu_dm_connector *aconnector;
-+	struct drm_connector *connector;
-+
-+	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
-+
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+		   aconnector = to_amdgpu_dm_connector(connector);
-+		   if (aconnector->dc_link->type == dc_connection_mst_branch &&
-+				   !aconnector->mst_port) {
-+
-+			   if (suspend)
-+				   drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
-+			   else
-+				   drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
-+		   }
-+	}
-+
-+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
-+}
-+
-+static int dm_hw_init(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+	/* Create DAL display manager */
-+	amdgpu_dm_init(adev);
-+	amdgpu_dm_hpd_init(adev);
-+
-+	return 0;
-+}
-+
-+static int dm_hw_fini(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	amdgpu_dm_hpd_fini(adev);
-+
-+	amdgpu_dm_irq_fini(adev);
-+	amdgpu_dm_fini(adev);
-+	return 0;
-+}
-+
-+static int dm_suspend(void *handle)
-+{
-+	struct amdgpu_device *adev = handle;
-+	struct amdgpu_display_manager *dm = &adev->dm;
-+	int ret = 0;
-+
-+	s3_handle_mst(adev->ddev, true);
-+
-+	amdgpu_dm_irq_suspend(adev);
-+
-+	WARN_ON(adev->dm.cached_state);
-+	adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
-+
-+	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
-+
-+	return ret;
-+}
-+
-+static struct amdgpu_dm_connector *
-+amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
-+					     struct drm_crtc *crtc)
-+{
-+	uint32_t i;
-+	struct drm_connector_state *new_con_state;
-+	struct drm_connector *connector;
-+	struct drm_crtc *crtc_from_state;
-+
-+	for_each_new_connector_in_state(state, connector, new_con_state, i) {
-+		crtc_from_state = new_con_state->crtc;
-+
-+		if (crtc_from_state == crtc)
-+			return to_amdgpu_dm_connector(connector);
-+	}
-+
-+	return NULL;
-+}
-+
-+static int dm_resume(void *handle)
-+{
-+	struct amdgpu_device *adev = handle;
-+	struct amdgpu_display_manager *dm = &adev->dm;
-+
-+	/* power on hardware */
-+	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
-+
-+	return 0;
-+}
-+
-+int amdgpu_dm_display_resume(struct amdgpu_device *adev)
-+{
-+	struct drm_device *ddev = adev->ddev;
-+	struct amdgpu_display_manager *dm = &adev->dm;
-+	struct amdgpu_dm_connector *aconnector;
-+	struct drm_connector *connector;
-+	struct drm_crtc *crtc;
-+	struct drm_crtc_state *new_crtc_state;
-+	struct dm_crtc_state *dm_new_crtc_state;
-+	struct drm_plane *plane;
-+	struct drm_plane_state *new_plane_state;
-+	struct dm_plane_state *dm_new_plane_state;
-+
-+	int ret = 0;
-+	int i;
-+
-+	/* program HPD filter */
-+	dc_resume(dm->dc);
-+
-+	/* On resume we need to  rewrite the MSTM control bits to enamble MST*/
-+	s3_handle_mst(ddev, false);
-+
-+	/*
-+	 * early enable HPD Rx IRQ, should be done before set mode as short
-+	 * pulse interrupts are used for MST
-+	 */
-+	amdgpu_dm_irq_resume_early(adev);
-+
-+	/* Do detection*/
-+	list_for_each_entry(connector,
-+			&ddev->mode_config.connector_list, head) {
-+		aconnector = to_amdgpu_dm_connector(connector);
-+
-+		/*
-+		 * this is the case when traversing through already created
-+		 * MST connectors, should be skipped
-+		 */
-+		if (aconnector->mst_port)
-+			continue;
-+
-+		mutex_lock(&aconnector->hpd_lock);
-+		dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
-+
-+		if (aconnector->fake_enable && aconnector->dc_link->local_sink)
-+			aconnector->fake_enable = false;
-+
-+		aconnector->dc_sink = NULL;
-+		amdgpu_dm_update_connector_after_detect(aconnector);
-+		mutex_unlock(&aconnector->hpd_lock);
-+	}
-+
-+	/* Force mode set in atomic comit */
-+	for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
-+		new_crtc_state->active_changed = true;
-+
-+	/*
-+	 * atomic_check is expected to create the dc states. We need to release
-+	 * them here, since they were duplicated as part of the suspend
-+	 * procedure.
-+	 */
-+	for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
-+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
-+		if (dm_new_crtc_state->stream) {
-+			WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
-+			dc_stream_release(dm_new_crtc_state->stream);
-+			dm_new_crtc_state->stream = NULL;
-+		}
-+	}
-+
-+	for_each_new_plane_in_state(adev->dm.cached_state, plane, new_plane_state, i) {
-+		dm_new_plane_state = to_dm_plane_state(new_plane_state);
-+		if (dm_new_plane_state->dc_state) {
-+			WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
-+			dc_plane_state_release(dm_new_plane_state->dc_state);
-+			dm_new_plane_state->dc_state = NULL;
-+		}
-+	}
-+
-+	ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
-+
-+	drm_atomic_state_put(adev->dm.cached_state);
-+	adev->dm.cached_state = NULL;
-+
-+	amdgpu_dm_irq_resume_late(adev);
-+
-+	return ret;
-+}
-+
-+static const struct amd_ip_funcs amdgpu_dm_funcs = {
-+	.name = "dm",
-+	.early_init = dm_early_init,
-+	.late_init = dm_late_init,
-+	.sw_init = dm_sw_init,
-+	.sw_fini = dm_sw_fini,
-+	.hw_init = dm_hw_init,
-+	.hw_fini = dm_hw_fini,
-+	.suspend = dm_suspend,
-+	.resume = dm_resume,
-+	.is_idle = dm_is_idle,
-+	.wait_for_idle = dm_wait_for_idle,
-+	.check_soft_reset = dm_check_soft_reset,
-+	.soft_reset = dm_soft_reset,
-+	.set_clockgating_state = dm_set_clockgating_state,
-+	.set_powergating_state = dm_set_powergating_state,
-+};
-+
-+const struct amdgpu_ip_block_version dm_ip_block =
-+{
-+	.type = AMD_IP_BLOCK_TYPE_DCE,
-+	.major = 1,
-+	.minor = 0,
-+	.rev = 0,
-+	.funcs = &amdgpu_dm_funcs,
-+};
-+
-+
-+static struct drm_atomic_state *
-+dm_atomic_state_alloc(struct drm_device *dev)
-+{
-+	struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
-+
-+	if (!state)
-+		return NULL;
-+
-+	if (drm_atomic_state_init(dev, &state->base) < 0)
-+		goto fail;
-+
-+	return &state->base;
-+
-+fail:
-+	kfree(state);
-+	return NULL;
-+}
-+
-+static void
-+dm_atomic_state_clear(struct drm_atomic_state *state)
-+{
-+	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
-+
-+	if (dm_state->context) {
-+		dc_release_state(dm_state->context);
-+		dm_state->context = NULL;
-+	}
-+
-+	drm_atomic_state_default_clear(state);
-+}
-+
-+static void
-+dm_atomic_state_alloc_free(struct drm_atomic_state *state)
-+{
-+	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
-+	drm_atomic_state_default_release(state);
-+	kfree(dm_state);
-+}
-+
-+static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
-+	.fb_create = amdgpu_user_framebuffer_create,
-+	.output_poll_changed = amdgpu_output_poll_changed,
-+	.atomic_check = amdgpu_dm_atomic_check,
-+	.atomic_commit = amdgpu_dm_atomic_commit,
-+	.atomic_state_alloc = dm_atomic_state_alloc,
-+	.atomic_state_clear = dm_atomic_state_clear,
-+	.atomic_state_free = dm_atomic_state_alloc_free
-+};
-+
-+static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
-+	.atomic_commit_tail = amdgpu_dm_atomic_commit_tail
-+};
-+
-+static void
-+amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
-+{
-+	struct drm_connector *connector = &aconnector->base;
-+	struct drm_device *dev = connector->dev;
-+	struct dc_sink *sink;
-+
-+	/* MST handled by drm_mst framework */
-+	if (aconnector->mst_mgr.mst_state == true)
-+		return;
-+
-+
-+	sink = aconnector->dc_link->local_sink;
-+
-+	/* Edid mgmt connector gets first update only in mode_valid hook and then
-+	 * the connector sink is set to either fake or physical sink depends on link status.
-+	 * don't do it here if u are during boot
-+	 */
-+	if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
-+			&& aconnector->dc_em_sink) {
-+
-+		/* For S3 resume with headless use eml_sink to fake stream
-+		 * because on resume connecotr->sink is set ti NULL
-+		 */
-+		mutex_lock(&dev->mode_config.mutex);
-+
-+		if (sink) {
-+			if (aconnector->dc_sink) {
-+				amdgpu_dm_remove_sink_from_freesync_module(
-+								connector);
-+				/* retain and release bellow are used for
-+				 * bump up refcount for sink because the link don't point
-+				 * to it anymore after disconnect so on next crtc to connector
-+				 * reshuffle by UMD we will get into unwanted dc_sink release
-+				 */
-+				if (aconnector->dc_sink != aconnector->dc_em_sink)
-+					dc_sink_release(aconnector->dc_sink);
-+			}
-+			aconnector->dc_sink = sink;
-+			amdgpu_dm_add_sink_to_freesync_module(
-+						connector, aconnector->edid);
-+		} else {
-+			amdgpu_dm_remove_sink_from_freesync_module(connector);
-+			if (!aconnector->dc_sink)
-+				aconnector->dc_sink = aconnector->dc_em_sink;
-+			else if (aconnector->dc_sink != aconnector->dc_em_sink)
-+				dc_sink_retain(aconnector->dc_sink);
-+		}
-+
-+		mutex_unlock(&dev->mode_config.mutex);
-+		return;
-+	}
-+
-+	/*
-+	 * TODO: temporary guard to look for proper fix
-+	 * if this sink is MST sink, we should not do anything
-+	 */
-+	if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
-+		return;
-+
-+	if (aconnector->dc_sink == sink) {
-+		/* We got a DP short pulse (Link Loss, DP CTS, etc...).
-+		 * Do nothing!! */
-+		DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
-+				aconnector->connector_id);
-+		return;
-+	}
-+
-+	DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
-+		aconnector->connector_id, aconnector->dc_sink, sink);
-+
-+	mutex_lock(&dev->mode_config.mutex);
-+
-+	/* 1. Update status of the drm connector
-+	 * 2. Send an event and let userspace tell us what to do */
-+	if (sink) {
-+		/* TODO: check if we still need the S3 mode update workaround.
-+		 * If yes, put it here. */
-+		if (aconnector->dc_sink)
-+			amdgpu_dm_remove_sink_from_freesync_module(
-+							connector);
-+
-+		aconnector->dc_sink = sink;
-+		if (sink->dc_edid.length == 0) {
-+			aconnector->edid = NULL;
-+		} else {
-+			aconnector->edid =
-+				(struct edid *) sink->dc_edid.raw_edid;
-+
-+
-+			drm_mode_connector_update_edid_property(connector,
-+					aconnector->edid);
-+		}
-+		amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
-+
-+	} else {
-+		amdgpu_dm_remove_sink_from_freesync_module(connector);
-+		drm_mode_connector_update_edid_property(connector, NULL);
-+		aconnector->num_modes = 0;
-+		aconnector->dc_sink = NULL;
-+	}
-+
-+	mutex_unlock(&dev->mode_config.mutex);
-+}
-+
-+static void handle_hpd_irq(void *param)
-+{
-+	struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
-+	struct drm_connector *connector = &aconnector->base;
-+	struct drm_device *dev = connector->dev;
-+
-+	/* In case of failure or MST no need to update connector status or notify the OS
-+	 * since (for MST case) MST does this in it's own context.
-+	 */
-+	mutex_lock(&aconnector->hpd_lock);
-+
-+	if (aconnector->fake_enable)
-+		aconnector->fake_enable = false;
-+
-+	if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
-+		amdgpu_dm_update_connector_after_detect(aconnector);
-+
-+
-+		drm_modeset_lock_all(dev);
-+		dm_restore_drm_connector_state(dev, connector);
-+		drm_modeset_unlock_all(dev);
-+
-+		if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
-+			drm_kms_helper_hotplug_event(dev);
-+	}
-+	mutex_unlock(&aconnector->hpd_lock);
-+
-+}
-+
-+static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
-+{
-+	uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
-+	uint8_t dret;
-+	bool new_irq_handled = false;
-+	int dpcd_addr;
-+	int dpcd_bytes_to_read;
-+
-+	const int max_process_count = 30;
-+	int process_count = 0;
-+
-+	const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
-+
-+	if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
-+		dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
-+		/* DPCD 0x200 - 0x201 for downstream IRQ */
-+		dpcd_addr = DP_SINK_COUNT;
-+	} else {
-+		dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
-+		/* DPCD 0x2002 - 0x2005 for downstream IRQ */
-+		dpcd_addr = DP_SINK_COUNT_ESI;
-+	}
-+
-+	dret = drm_dp_dpcd_read(
-+		&aconnector->dm_dp_aux.aux,
-+		dpcd_addr,
-+		esi,
-+		dpcd_bytes_to_read);
-+
-+	while (dret == dpcd_bytes_to_read &&
-+		process_count < max_process_count) {
-+		uint8_t retry;
-+		dret = 0;
-+
-+		process_count++;
-+
-+		DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
-+		/* handle HPD short pulse irq */
-+		if (aconnector->mst_mgr.mst_state)
-+			drm_dp_mst_hpd_irq(
-+				&aconnector->mst_mgr,
-+				esi,
-+				&new_irq_handled);
-+
-+		if (new_irq_handled) {
-+			/* ACK at DPCD to notify down stream */
-+			const int ack_dpcd_bytes_to_write =
-+				dpcd_bytes_to_read - 1;
-+
-+			for (retry = 0; retry < 3; retry++) {
-+				uint8_t wret;
-+
-+				wret = drm_dp_dpcd_write(
-+					&aconnector->dm_dp_aux.aux,
-+					dpcd_addr + 1,
-+					&esi[1],
-+					ack_dpcd_bytes_to_write);
-+				if (wret == ack_dpcd_bytes_to_write)
-+					break;
-+			}
-+
-+			/* check if there is new irq to be handle */
-+			dret = drm_dp_dpcd_read(
-+				&aconnector->dm_dp_aux.aux,
-+				dpcd_addr,
-+				esi,
-+				dpcd_bytes_to_read);
-+
-+			new_irq_handled = false;
-+		} else {
-+			break;
-+		}
-+	}
-+
-+	if (process_count == max_process_count)
-+		DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
-+}
-+
-+static void handle_hpd_rx_irq(void *param)
-+{
-+	struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
-+	struct drm_connector *connector = &aconnector->base;
-+	struct drm_device *dev = connector->dev;
-+	struct dc_link *dc_link = aconnector->dc_link;
-+	bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
-+
-+	/* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
-+	 * conflict, after implement i2c helper, this mutex should be
-+	 * retired.
-+	 */
-+	if (dc_link->type != dc_connection_mst_branch)
-+		mutex_lock(&aconnector->hpd_lock);
-+
-+	if (dc_link_handle_hpd_rx_irq(dc_link, NULL) &&
-+			!is_mst_root_connector) {
-+		/* Downstream Port status changed. */
-+		if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
-+			amdgpu_dm_update_connector_after_detect(aconnector);
-+
-+
-+			drm_modeset_lock_all(dev);
-+			dm_restore_drm_connector_state(dev, connector);
-+			drm_modeset_unlock_all(dev);
-+
-+			drm_kms_helper_hotplug_event(dev);
-+		}
-+	}
-+	if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
-+	    (dc_link->type == dc_connection_mst_branch))
-+		dm_handle_hpd_rx_irq(aconnector);
-+
-+	if (dc_link->type != dc_connection_mst_branch)
-+		mutex_unlock(&aconnector->hpd_lock);
-+}
-+
-+static void register_hpd_handlers(struct amdgpu_device *adev)
-+{
-+	struct drm_device *dev = adev->ddev;
-+	struct drm_connector *connector;
-+	struct amdgpu_dm_connector *aconnector;
-+	const struct dc_link *dc_link;
-+	struct dc_interrupt_params int_params = {0};
-+
-+	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
-+	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
-+
-+	list_for_each_entry(connector,
-+			&dev->mode_config.connector_list, head)	{
-+
-+		aconnector = to_amdgpu_dm_connector(connector);
-+		dc_link = aconnector->dc_link;
-+
-+		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
-+			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
-+			int_params.irq_source = dc_link->irq_source_hpd;
-+
-+			amdgpu_dm_irq_register_interrupt(adev, &int_params,
-+					handle_hpd_irq,
-+					(void *) aconnector);
-+		}
-+
-+		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
-+
-+			/* Also register for DP short pulse (hpd_rx). */
-+			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
-+			int_params.irq_source =	dc_link->irq_source_hpd_rx;
-+
-+			amdgpu_dm_irq_register_interrupt(adev, &int_params,
-+					handle_hpd_rx_irq,
-+					(void *) aconnector);
-+		}
-+	}
-+}
-+
-+/* Register IRQ sources and initialize IRQ callbacks */
-+static int dce110_register_irq_handlers(struct amdgpu_device *adev)
-+{
-+	struct dc *dc = adev->dm.dc;
-+	struct common_irq_params *c_irq_params;
-+	struct dc_interrupt_params int_params = {0};
-+	int r;
-+	int i;
-+	unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
-+
-+	if (adev->asic_type == CHIP_VEGA10 ||
-+	    adev->asic_type == CHIP_RAVEN)
-+		client_id = AMDGPU_IH_CLIENTID_DCE;
-+
-+	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
-+	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
-+
-+	/* Actions of amdgpu_irq_add_id():
-+	 * 1. Register a set() function with base driver.
-+	 *    Base driver will call set() function to enable/disable an
-+	 *    interrupt in DC hardware.
-+	 * 2. Register amdgpu_dm_irq_handler().
-+	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
-+	 *    coming from DC hardware.
-+	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
-+	 *    for acknowledging and handling. */
-+
-+	/* Use VBLANK interrupt */
-+	for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
-+		r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
-+		if (r) {
-+			DRM_ERROR("Failed to add crtc irq id!\n");
-+			return r;
-+		}
-+
-+		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
-+		int_params.irq_source =
-+			dc_interrupt_to_irq_source(dc, i, 0);
-+
-+		c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
-+
-+		c_irq_params->adev = adev;
-+		c_irq_params->irq_src = int_params.irq_source;
-+
-+		amdgpu_dm_irq_register_interrupt(adev, &int_params,
-+				dm_crtc_high_irq, c_irq_params);
-+	}
-+
-+	/* Use GRPH_PFLIP interrupt */
-+	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
-+			i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
-+		r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
-+		if (r) {
-+			DRM_ERROR("Failed to add page flip irq id!\n");
-+			return r;
-+		}
-+
-+		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
-+		int_params.irq_source =
-+			dc_interrupt_to_irq_source(dc, i, 0);
-+
-+		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
-+
-+		c_irq_params->adev = adev;
-+		c_irq_params->irq_src = int_params.irq_source;
-+
-+		amdgpu_dm_irq_register_interrupt(adev, &int_params,
-+				dm_pflip_high_irq, c_irq_params);
-+
-+	}
-+
-+	/* HPD */
-+	r = amdgpu_irq_add_id(adev, client_id,
-+			VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
-+	if (r) {
-+		DRM_ERROR("Failed to add hpd irq id!\n");
-+		return r;
-+	}
-+
-+	register_hpd_handlers(adev);
-+
-+	return 0;
-+}
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+/* Register IRQ sources and initialize IRQ callbacks */
-+static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
-+{
-+	struct dc *dc = adev->dm.dc;
-+	struct common_irq_params *c_irq_params;
-+	struct dc_interrupt_params int_params = {0};
-+	int r;
-+	int i;
-+
-+	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
-+	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
-+
-+	/* Actions of amdgpu_irq_add_id():
-+	 * 1. Register a set() function with base driver.
-+	 *    Base driver will call set() function to enable/disable an
-+	 *    interrupt in DC hardware.
-+	 * 2. Register amdgpu_dm_irq_handler().
-+	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
-+	 *    coming from DC hardware.
-+	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
-+	 *    for acknowledging and handling.
-+	 * */
-+
-+	/* Use VSTARTUP interrupt */
-+	for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
-+			i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
-+			i++) {
-+		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
-+
-+		if (r) {
-+			DRM_ERROR("Failed to add crtc irq id!\n");
-+			return r;
-+		}
-+
-+		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
-+		int_params.irq_source =
-+			dc_interrupt_to_irq_source(dc, i, 0);
-+
-+		c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
-+
-+		c_irq_params->adev = adev;
-+		c_irq_params->irq_src = int_params.irq_source;
-+
-+		amdgpu_dm_irq_register_interrupt(adev, &int_params,
-+				dm_crtc_high_irq, c_irq_params);
-+	}
-+
-+	/* Use GRPH_PFLIP interrupt */
-+	for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
-+			i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
-+			i++) {
-+		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
-+		if (r) {
-+			DRM_ERROR("Failed to add page flip irq id!\n");
-+			return r;
-+		}
-+
-+		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
-+		int_params.irq_source =
-+			dc_interrupt_to_irq_source(dc, i, 0);
-+
-+		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
-+
-+		c_irq_params->adev = adev;
-+		c_irq_params->irq_src = int_params.irq_source;
-+
-+		amdgpu_dm_irq_register_interrupt(adev, &int_params,
-+				dm_pflip_high_irq, c_irq_params);
-+
-+	}
-+
-+	/* HPD */
-+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
-+			&adev->hpd_irq);
-+	if (r) {
-+		DRM_ERROR("Failed to add hpd irq id!\n");
-+		return r;
-+	}
-+
-+	register_hpd_handlers(adev);
-+
-+	return 0;
-+}
-+#endif
-+
-+static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
-+{
-+	int r;
-+
-+	adev->mode_info.mode_config_initialized = true;
-+
-+	adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
-+	adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
-+
-+	adev->ddev->mode_config.max_width = 16384;
-+	adev->ddev->mode_config.max_height = 16384;
-+
-+	adev->ddev->mode_config.preferred_depth = 24;
-+	adev->ddev->mode_config.prefer_shadow = 1;
-+	/* indicate support of immediate flip */
-+	adev->ddev->mode_config.async_page_flip = true;
-+
-+	adev->ddev->mode_config.fb_base = adev->mc.aper_base;
-+
-+	r = amdgpu_modeset_create_props(adev);
-+	if (r)
-+		return r;
-+
-+	return 0;
-+}
-+
-+#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
-+	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-+
-+static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
-+{
-+	struct amdgpu_display_manager *dm = bl_get_data(bd);
-+
-+	if (dc_link_set_backlight_level(dm->backlight_link,
-+			bd->props.brightness, 0, 0))
-+		return 0;
-+	else
-+		return 1;
-+}
-+
-+static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
-+{
-+	return bd->props.brightness;
-+}
-+
-+static const struct backlight_ops amdgpu_dm_backlight_ops = {
-+	.get_brightness = amdgpu_dm_backlight_get_brightness,
-+	.update_status	= amdgpu_dm_backlight_update_status,
-+};
-+
-+static void
-+amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
-+{
-+	char bl_name[16];
-+	struct backlight_properties props = { 0 };
-+
-+	props.max_brightness = AMDGPU_MAX_BL_LEVEL;
-+	props.type = BACKLIGHT_RAW;
-+
-+	snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
-+			dm->adev->ddev->primary->index);
-+
-+	dm->backlight_dev = backlight_device_register(bl_name,
-+			dm->adev->ddev->dev,
-+			dm,
-+			&amdgpu_dm_backlight_ops,
-+			&props);
-+
-+	if (IS_ERR(dm->backlight_dev))
-+		DRM_ERROR("DM: Backlight registration failed!\n");
-+	else
-+		DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
-+}
-+
-+#endif
-+
-+/* In this architecture, the association
-+ * connector -> encoder -> crtc
-+ * id not really requried. The crtc and connector will hold the
-+ * display_index as an abstraction to use with DAL component
-+ *
-+ * Returns 0 on success
-+ */
-+static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
-+{
-+	struct amdgpu_display_manager *dm = &adev->dm;
-+	uint32_t i;
-+	struct amdgpu_dm_connector *aconnector = NULL;
-+	struct amdgpu_encoder *aencoder = NULL;
-+	struct amdgpu_mode_info *mode_info = &adev->mode_info;
-+	uint32_t link_cnt;
-+	unsigned long possible_crtcs;
-+
-+	link_cnt = dm->dc->caps.max_links;
-+	if (amdgpu_dm_mode_config_init(dm->adev)) {
-+		DRM_ERROR("DM: Failed to initialize mode config\n");
-+		return -1;
-+	}
-+
-+	for (i = 0; i < dm->dc->caps.max_planes; i++) {
-+		struct amdgpu_plane *plane;
-+
-+		plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
-+		mode_info->planes[i] = plane;
-+
-+		if (!plane) {
-+			DRM_ERROR("KMS: Failed to allocate plane\n");
-+			goto fail;
-+		}
-+		plane->base.type = mode_info->plane_type[i];
-+
-+		/*
-+		 * HACK: IGT tests expect that each plane can only have one
-+		 * one possible CRTC. For now, set one CRTC for each
-+		 * plane that is not an underlay, but still allow multiple
-+		 * CRTCs for underlay planes.
-+		 */
-+		possible_crtcs = 1 << i;
-+		if (i >= dm->dc->caps.max_streams)
-+			possible_crtcs = 0xff;
-+
-+		if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
-+			DRM_ERROR("KMS: Failed to initialize plane\n");
-+			goto fail;
-+		}
-+	}
-+
-+	for (i = 0; i < dm->dc->caps.max_streams; i++)
-+		if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
-+			DRM_ERROR("KMS: Failed to initialize crtc\n");
-+			goto fail;
-+		}
-+
-+	dm->display_indexes_num = dm->dc->caps.max_streams;
-+
-+	/* loops over all connectors on the board */
-+	for (i = 0; i < link_cnt; i++) {
-+
-+		if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
-+			DRM_ERROR(
-+				"KMS: Cannot support more than %d display indexes\n",
-+					AMDGPU_DM_MAX_DISPLAY_INDEX);
-+			continue;
-+		}
-+
-+		aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
-+		if (!aconnector)
-+			goto fail;
-+
-+		aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
-+		if (!aencoder)
-+			goto fail;
-+
-+		if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
-+			DRM_ERROR("KMS: Failed to initialize encoder\n");
-+			goto fail;
-+		}
-+
-+		if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
-+			DRM_ERROR("KMS: Failed to initialize connector\n");
-+			goto fail;
-+		}
-+
-+		if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
-+				DETECT_REASON_BOOT))
-+			amdgpu_dm_update_connector_after_detect(aconnector);
-+	}
-+
-+	/* Software is initialized. Now we can register interrupt handlers. */
-+	switch (adev->asic_type) {
-+	case CHIP_BONAIRE:
-+	case CHIP_HAWAII:
-+	case CHIP_KAVERI:
-+	case CHIP_KABINI:
-+	case CHIP_MULLINS:
-+	case CHIP_TONGA:
-+	case CHIP_FIJI:
-+	case CHIP_CARRIZO:
-+	case CHIP_STONEY:
-+	case CHIP_POLARIS11:
-+	case CHIP_POLARIS10:
-+	case CHIP_POLARIS12:
-+	case CHIP_VEGA10:
-+		if (dce110_register_irq_handlers(dm->adev)) {
-+			DRM_ERROR("DM: Failed to initialize IRQ\n");
-+			goto fail;
-+		}
-+		break;
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	case CHIP_RAVEN:
-+		if (dcn10_register_irq_handlers(dm->adev)) {
-+			DRM_ERROR("DM: Failed to initialize IRQ\n");
-+			goto fail;
-+		}
-+		/*
-+		 * Temporary disable until pplib/smu interaction is implemented
-+		 */
-+		dm->dc->debug.disable_stutter = true;
-+		break;
-+#endif
-+	default:
-+		DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
-+		goto fail;
-+	}
-+
-+	return 0;
-+fail:
-+	kfree(aencoder);
-+	kfree(aconnector);
-+	for (i = 0; i < dm->dc->caps.max_planes; i++)
-+		kfree(mode_info->planes[i]);
-+	return -1;
-+}
-+
-+static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
-+{
-+	drm_mode_config_cleanup(dm->ddev);
-+	return;
-+}
-+
-+/******************************************************************************
-+ * amdgpu_display_funcs functions
-+ *****************************************************************************/
-+
-+/**
-+ * dm_bandwidth_update - program display watermarks
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Calculate and program the display watermarks and line buffer allocation.
-+ */
-+static void dm_bandwidth_update(struct amdgpu_device *adev)
-+{
-+	/* TODO: implement later */
-+}
-+
-+static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
-+				     u8 level)
-+{
-+	/* TODO: translate amdgpu_encoder to display_index and call DAL */
-+}
-+
-+static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
-+{
-+	/* TODO: translate amdgpu_encoder to display_index and call DAL */
-+	return 0;
-+}
-+
-+static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
-+				struct drm_file *filp)
-+{
-+	struct mod_freesync_params freesync_params;
-+	uint8_t num_streams;
-+	uint8_t i;
-+
-+	struct amdgpu_device *adev = dev->dev_private;
-+	struct drm_amdgpu_freesync *args = data;
-+	int r = 0;
-+
-+	freesync_params.state  = FREESYNC_STATE_FULLSCREEN;
-+	if (args->op == AMDGPU_FREESYNC_FULLSCREEN_ENTER)
-+		freesync_params.enable = true;
-+	else
-+		freesync_params.enable = false;
-+
-+	num_streams = dc_get_current_stream_count(adev->dm.dc);
-+
-+	for (i = 0; i < num_streams; i++) {
-+		struct dc_stream_state *stream;
-+		stream = dc_get_stream_at_index(adev->dm.dc, i);
-+
-+		mod_freesync_update_state(adev->dm.freesync_module,
-+					  &stream, 1, &freesync_params);
-+	}
-+
-+	return r;
-+}
-+
-+static const struct amdgpu_display_funcs dm_display_funcs = {
-+	.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
-+	.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
-+	.vblank_wait = NULL,
-+	.backlight_set_level =
-+		dm_set_backlight_level,/* called unconditionally */
-+	.backlight_get_level =
-+		dm_get_backlight_level,/* called unconditionally */
-+	.hpd_sense = NULL,/* called unconditionally */
-+	.hpd_set_polarity = NULL, /* called unconditionally */
-+	.hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
-+	.page_flip_get_scanoutpos =
-+		dm_crtc_get_scanoutpos,/* called unconditionally */
-+	.add_encoder = NULL, /* VBIOS parsing. DAL does it. */
-+	.add_connector = NULL, /* VBIOS parsing. DAL does it. */
-+	.notify_freesync = amdgpu_notify_freesync,
-+
-+};
-+
-+#if defined(CONFIG_DEBUG_KERNEL_DC)
-+
-+static ssize_t s3_debug_store(struct device *device,
-+			      struct device_attribute *attr,
-+			      const char *buf,
-+			      size_t count)
-+{
-+	int ret;
-+	int s3_state;
-+	struct pci_dev *pdev = to_pci_dev(device);
-+	struct drm_device *drm_dev = pci_get_drvdata(pdev);
-+	struct amdgpu_device *adev = drm_dev->dev_private;
-+
-+	ret = kstrtoint(buf, 0, &s3_state);
-+
-+	if (ret == 0) {
-+		if (s3_state) {
-+			dm_resume(adev);
-+			amdgpu_dm_display_resume(adev);
-+			drm_kms_helper_hotplug_event(adev->ddev);
-+		} else
-+			dm_suspend(adev);
-+	}
-+
-+	return ret == 0 ? count : 0;
-+}
-+
-+DEVICE_ATTR_WO(s3_debug);
-+
-+#endif
-+
-+static int dm_early_init(void *handle)
-+{
-+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-+
-+	adev->ddev->driver->driver_features |= DRIVER_ATOMIC;
-+
-+	switch (adev->asic_type) {
-+	case CHIP_BONAIRE:
-+	case CHIP_HAWAII:
-+		adev->mode_info.num_crtc = 6;
-+		adev->mode_info.num_hpd = 6;
-+		adev->mode_info.num_dig = 6;
-+		adev->mode_info.plane_type = dm_plane_type_default;
-+		break;
-+	case CHIP_KAVERI:
-+		adev->mode_info.num_crtc = 4;
-+		adev->mode_info.num_hpd = 6;
-+		adev->mode_info.num_dig = 7;
-+		adev->mode_info.plane_type = dm_plane_type_default;
-+		break;
-+	case CHIP_KABINI:
-+	case CHIP_MULLINS:
-+		adev->mode_info.num_crtc = 2;
-+		adev->mode_info.num_hpd = 6;
-+		adev->mode_info.num_dig = 6;
-+		adev->mode_info.plane_type = dm_plane_type_default;
-+		break;
-+	case CHIP_FIJI:
-+	case CHIP_TONGA:
-+		adev->mode_info.num_crtc = 6;
-+		adev->mode_info.num_hpd = 6;
-+		adev->mode_info.num_dig = 7;
-+		adev->mode_info.plane_type = dm_plane_type_default;
-+		break;
-+	case CHIP_CARRIZO:
-+		adev->mode_info.num_crtc = 3;
-+		adev->mode_info.num_hpd = 6;
-+		adev->mode_info.num_dig = 9;
-+		adev->mode_info.plane_type = dm_plane_type_carizzo;
-+		break;
-+	case CHIP_STONEY:
-+		adev->mode_info.num_crtc = 2;
-+		adev->mode_info.num_hpd = 6;
-+		adev->mode_info.num_dig = 9;
-+		adev->mode_info.plane_type = dm_plane_type_stoney;
-+		break;
-+	case CHIP_POLARIS11:
-+	case CHIP_POLARIS12:
-+		adev->mode_info.num_crtc = 5;
-+		adev->mode_info.num_hpd = 5;
-+		adev->mode_info.num_dig = 5;
-+		adev->mode_info.plane_type = dm_plane_type_default;
-+		break;
-+	case CHIP_POLARIS10:
-+		adev->mode_info.num_crtc = 6;
-+		adev->mode_info.num_hpd = 6;
-+		adev->mode_info.num_dig = 6;
-+		adev->mode_info.plane_type = dm_plane_type_default;
-+		break;
-+	case CHIP_VEGA10:
-+		adev->mode_info.num_crtc = 6;
-+		adev->mode_info.num_hpd = 6;
-+		adev->mode_info.num_dig = 6;
-+		adev->mode_info.plane_type = dm_plane_type_default;
-+		break;
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	case CHIP_RAVEN:
-+		adev->mode_info.num_crtc = 4;
-+		adev->mode_info.num_hpd = 4;
-+		adev->mode_info.num_dig = 4;
-+		adev->mode_info.plane_type = dm_plane_type_default;
-+		break;
-+#endif
-+	default:
-+		DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
-+		return -EINVAL;
-+	}
-+
-+	amdgpu_dm_set_irq_funcs(adev);
-+
-+	if (adev->mode_info.funcs == NULL)
-+		adev->mode_info.funcs = &dm_display_funcs;
-+
-+	/* Note: Do NOT change adev->audio_endpt_rreg and
-+	 * adev->audio_endpt_wreg because they are initialised in
-+	 * amdgpu_device_init() */
-+#if defined(CONFIG_DEBUG_KERNEL_DC)
-+	device_create_file(
-+		adev->ddev->dev,
-+		&dev_attr_s3_debug);
-+#endif
-+
-+	return 0;
-+}
-+
-+static bool modeset_required(struct drm_crtc_state *crtc_state,
-+			     struct dc_stream_state *new_stream,
-+			     struct dc_stream_state *old_stream)
-+{
-+	if (!drm_atomic_crtc_needs_modeset(crtc_state))
-+		return false;
-+
-+	if (!crtc_state->enable)
-+		return false;
-+
-+	return crtc_state->active;
-+}
-+
-+static bool modereset_required(struct drm_crtc_state *crtc_state)
-+{
-+	if (!drm_atomic_crtc_needs_modeset(crtc_state))
-+		return false;
-+
-+	return !crtc_state->enable || !crtc_state->active;
-+}
-+
-+static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
-+{
-+	drm_encoder_cleanup(encoder);
-+	kfree(encoder);
-+}
-+
-+static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
-+	.destroy = amdgpu_dm_encoder_destroy,
-+};
-+
-+static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
-+					struct dc_plane_state *plane_state)
-+{
-+	plane_state->src_rect.x = state->src_x >> 16;
-+	plane_state->src_rect.y = state->src_y >> 16;
-+	/*we ignore for now mantissa and do not to deal with floating pixels :(*/
-+	plane_state->src_rect.width = state->src_w >> 16;
-+
-+	if (plane_state->src_rect.width == 0)
-+		return false;
-+
-+	plane_state->src_rect.height = state->src_h >> 16;
-+	if (plane_state->src_rect.height == 0)
-+		return false;
-+
-+	plane_state->dst_rect.x = state->crtc_x;
-+	plane_state->dst_rect.y = state->crtc_y;
-+
-+	if (state->crtc_w == 0)
-+		return false;
-+
-+	plane_state->dst_rect.width = state->crtc_w;
-+
-+	if (state->crtc_h == 0)
-+		return false;
-+
-+	plane_state->dst_rect.height = state->crtc_h;
-+
-+	plane_state->clip_rect = plane_state->dst_rect;
-+
-+	switch (state->rotation & DRM_MODE_ROTATE_MASK) {
-+	case DRM_MODE_ROTATE_0:
-+		plane_state->rotation = ROTATION_ANGLE_0;
-+		break;
-+	case DRM_MODE_ROTATE_90:
-+		plane_state->rotation = ROTATION_ANGLE_90;
-+		break;
-+	case DRM_MODE_ROTATE_180:
-+		plane_state->rotation = ROTATION_ANGLE_180;
-+		break;
-+	case DRM_MODE_ROTATE_270:
-+		plane_state->rotation = ROTATION_ANGLE_270;
-+		break;
-+	default:
-+		plane_state->rotation = ROTATION_ANGLE_0;
-+		break;
-+	}
-+
-+	return true;
-+}
-+static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
-+		       uint64_t *tiling_flags)
-+{
-+	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
-+	int r = amdgpu_bo_reserve(rbo, false);
-+
-+	if (unlikely(r)) {
-+		// Don't show error msg. when return -ERESTARTSYS
-+		if (r != -ERESTARTSYS)
-+			DRM_ERROR("Unable to reserve buffer: %d\n", r);
-+		return r;
-+	}
-+
-+	if (tiling_flags)
-+		amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
-+
-+	amdgpu_bo_unreserve(rbo);
-+
-+	return r;
-+}
-+
-+static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
-+					 struct dc_plane_state *plane_state,
-+					 const struct amdgpu_framebuffer *amdgpu_fb)
-+{
-+	uint64_t tiling_flags;
-+	unsigned int awidth;
-+	const struct drm_framebuffer *fb = &amdgpu_fb->base;
-+	int ret = 0;
-+	struct drm_format_name_buf format_name;
-+
-+	ret = get_fb_info(
-+		amdgpu_fb,
-+		&tiling_flags);
-+
-+	if (ret)
-+		return ret;
-+
-+	switch (fb->format->format) {
-+	case DRM_FORMAT_C8:
-+		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
-+		break;
-+	case DRM_FORMAT_RGB565:
-+		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
-+		break;
-+	case DRM_FORMAT_XRGB8888:
-+	case DRM_FORMAT_ARGB8888:
-+		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
-+		break;
-+	case DRM_FORMAT_XRGB2101010:
-+	case DRM_FORMAT_ARGB2101010:
-+		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
-+		break;
-+	case DRM_FORMAT_XBGR2101010:
-+	case DRM_FORMAT_ABGR2101010:
-+		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
-+		break;
-+	case DRM_FORMAT_NV21:
-+		plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
-+		break;
-+	case DRM_FORMAT_NV12:
-+		plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
-+		break;
-+	default:
-+		DRM_ERROR("Unsupported screen format %s\n",
-+			  drm_get_format_name(fb->format->format, &format_name));
-+		return -EINVAL;
-+	}
-+
-+	if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-+		plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
-+		plane_state->plane_size.grph.surface_size.x = 0;
-+		plane_state->plane_size.grph.surface_size.y = 0;
-+		plane_state->plane_size.grph.surface_size.width = fb->width;
-+		plane_state->plane_size.grph.surface_size.height = fb->height;
-+		plane_state->plane_size.grph.surface_pitch =
-+				fb->pitches[0] / fb->format->cpp[0];
-+		/* TODO: unhardcode */
-+		plane_state->color_space = COLOR_SPACE_SRGB;
-+
-+	} else {
-+		awidth = ALIGN(fb->width, 64);
-+		plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
-+		plane_state->plane_size.video.luma_size.x = 0;
-+		plane_state->plane_size.video.luma_size.y = 0;
-+		plane_state->plane_size.video.luma_size.width = awidth;
-+		plane_state->plane_size.video.luma_size.height = fb->height;
-+		/* TODO: unhardcode */
-+		plane_state->plane_size.video.luma_pitch = awidth;
-+
-+		plane_state->plane_size.video.chroma_size.x = 0;
-+		plane_state->plane_size.video.chroma_size.y = 0;
-+		plane_state->plane_size.video.chroma_size.width = awidth;
-+		plane_state->plane_size.video.chroma_size.height = fb->height;
-+		plane_state->plane_size.video.chroma_pitch = awidth / 2;
-+
-+		/* TODO: unhardcode */
-+		plane_state->color_space = COLOR_SPACE_YCBCR709;
-+	}
-+
-+	memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
-+
-+	/* Fill GFX8 params */
-+	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
-+		unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
-+
-+		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
-+		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
-+		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
-+		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
-+		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
-+
-+		/* XXX fix me for VI */
-+		plane_state->tiling_info.gfx8.num_banks = num_banks;
-+		plane_state->tiling_info.gfx8.array_mode =
-+				DC_ARRAY_2D_TILED_THIN1;
-+		plane_state->tiling_info.gfx8.tile_split = tile_split;
-+		plane_state->tiling_info.gfx8.bank_width = bankw;
-+		plane_state->tiling_info.gfx8.bank_height = bankh;
-+		plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
-+		plane_state->tiling_info.gfx8.tile_mode =
-+				DC_ADDR_SURF_MICRO_TILING_DISPLAY;
-+	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
-+			== DC_ARRAY_1D_TILED_THIN1) {
-+		plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
-+	}
-+
-+	plane_state->tiling_info.gfx8.pipe_config =
-+			AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
-+
-+	if (adev->asic_type == CHIP_VEGA10 ||
-+	    adev->asic_type == CHIP_RAVEN) {
-+		/* Fill GFX9 params */
-+		plane_state->tiling_info.gfx9.num_pipes =
-+			adev->gfx.config.gb_addr_config_fields.num_pipes;
-+		plane_state->tiling_info.gfx9.num_banks =
-+			adev->gfx.config.gb_addr_config_fields.num_banks;
-+		plane_state->tiling_info.gfx9.pipe_interleave =
-+			adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
-+		plane_state->tiling_info.gfx9.num_shader_engines =
-+			adev->gfx.config.gb_addr_config_fields.num_se;
-+		plane_state->tiling_info.gfx9.max_compressed_frags =
-+			adev->gfx.config.gb_addr_config_fields.max_compress_frags;
-+		plane_state->tiling_info.gfx9.num_rb_per_se =
-+			adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
-+		plane_state->tiling_info.gfx9.swizzle =
-+			AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
-+		plane_state->tiling_info.gfx9.shaderEnable = 1;
-+	}
-+
-+	plane_state->visible = true;
-+	plane_state->scaling_quality.h_taps_c = 0;
-+	plane_state->scaling_quality.v_taps_c = 0;
-+
-+	/* is this needed? is plane_state zeroed at allocation? */
-+	plane_state->scaling_quality.h_taps = 0;
-+	plane_state->scaling_quality.v_taps = 0;
-+	plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
-+
-+	return ret;
-+
-+}
-+
-+static void fill_gamma_from_crtc_state(const struct drm_crtc_state *crtc_state,
-+				       struct dc_plane_state *plane_state)
-+{
-+	int i;
-+	struct dc_gamma *gamma;
-+	struct drm_color_lut *lut =
-+			(struct drm_color_lut *) crtc_state->gamma_lut->data;
-+
-+	gamma = dc_create_gamma();
-+
-+	if (gamma == NULL) {
-+		WARN_ON(1);
-+		return;
-+	}
-+
-+	gamma->type = GAMMA_RGB_256;
-+	gamma->num_entries = GAMMA_RGB_256_ENTRIES;
-+	for (i = 0; i < GAMMA_RGB_256_ENTRIES; i++) {
-+		gamma->entries.red[i] = dal_fixed31_32_from_int(lut[i].red);
-+		gamma->entries.green[i] = dal_fixed31_32_from_int(lut[i].green);
-+		gamma->entries.blue[i] = dal_fixed31_32_from_int(lut[i].blue);
-+	}
-+
-+	plane_state->gamma_correction = gamma;
-+}
-+
-+static int fill_plane_attributes(struct amdgpu_device *adev,
-+				 struct dc_plane_state *dc_plane_state,
-+				 struct drm_plane_state *plane_state,
-+				 struct drm_crtc_state *crtc_state)
-+{
-+	const struct amdgpu_framebuffer *amdgpu_fb =
-+		to_amdgpu_framebuffer(plane_state->fb);
-+	const struct drm_crtc *crtc = plane_state->crtc;
-+	struct dc_transfer_func *input_tf;
-+	int ret = 0;
-+
-+	if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
-+		return -EINVAL;
-+
-+	ret = fill_plane_attributes_from_fb(
-+		crtc->dev->dev_private,
-+		dc_plane_state,
-+		amdgpu_fb);
-+
-+	if (ret)
-+		return ret;
-+
-+	input_tf = dc_create_transfer_func();
-+
-+	if (input_tf == NULL)
-+		return -ENOMEM;
-+
-+	input_tf->type = TF_TYPE_PREDEFINED;
-+	input_tf->tf = TRANSFER_FUNCTION_SRGB;
-+
-+	dc_plane_state->in_transfer_func = input_tf;
-+
-+	/* In case of gamma set, update gamma value */
-+	if (crtc_state->gamma_lut)
-+		fill_gamma_from_crtc_state(crtc_state, dc_plane_state);
-+
-+	return ret;
-+}
-+
-+/*****************************************************************************/
-+
-+static void update_stream_scaling_settings(const struct drm_display_mode *mode,
-+					   const struct dm_connector_state *dm_state,
-+					   struct dc_stream_state *stream)
-+{
-+	enum amdgpu_rmx_type rmx_type;
-+
-+	struct rect src = { 0 }; /* viewport in composition space*/
-+	struct rect dst = { 0 }; /* stream addressable area */
-+
-+	/* no mode. nothing to be done */
-+	if (!mode)
-+		return;
-+
-+	/* Full screen scaling by default */
-+	src.width = mode->hdisplay;
-+	src.height = mode->vdisplay;
-+	dst.width = stream->timing.h_addressable;
-+	dst.height = stream->timing.v_addressable;
-+
-+	rmx_type = dm_state->scaling;
-+	if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
-+		if (src.width * dst.height <
-+				src.height * dst.width) {
-+			/* height needs less upscaling/more downscaling */
-+			dst.width = src.width *
-+					dst.height / src.height;
-+		} else {
-+			/* width needs less upscaling/more downscaling */
-+			dst.height = src.height *
-+					dst.width / src.width;
-+		}
-+	} else if (rmx_type == RMX_CENTER) {
-+		dst = src;
-+	}
-+
-+	dst.x = (stream->timing.h_addressable - dst.width) / 2;
-+	dst.y = (stream->timing.v_addressable - dst.height) / 2;
-+
-+	if (dm_state->underscan_enable) {
-+		dst.x += dm_state->underscan_hborder / 2;
-+		dst.y += dm_state->underscan_vborder / 2;
-+		dst.width -= dm_state->underscan_hborder;
-+		dst.height -= dm_state->underscan_vborder;
-+	}
-+
-+	stream->src = src;
-+	stream->dst = dst;
-+
-+	DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
-+			dst.x, dst.y, dst.width, dst.height);
-+
-+}
-+
-+static enum dc_color_depth
-+convert_color_depth_from_display_info(const struct drm_connector *connector)
-+{
-+	uint32_t bpc = connector->display_info.bpc;
-+
-+	/* Limited color depth to 8bit
-+	 * TODO: Still need to handle deep color
-+	 */
-+	if (bpc > 8)
-+		bpc = 8;
-+
-+	switch (bpc) {
-+	case 0:
-+		/* Temporary Work around, DRM don't parse color depth for
-+		 * EDID revision before 1.4
-+		 * TODO: Fix edid parsing
-+		 */
-+		return COLOR_DEPTH_888;
-+	case 6:
-+		return COLOR_DEPTH_666;
-+	case 8:
-+		return COLOR_DEPTH_888;
-+	case 10:
-+		return COLOR_DEPTH_101010;
-+	case 12:
-+		return COLOR_DEPTH_121212;
-+	case 14:
-+		return COLOR_DEPTH_141414;
-+	case 16:
-+		return COLOR_DEPTH_161616;
-+	default:
-+		return COLOR_DEPTH_UNDEFINED;
-+	}
-+}
-+
-+static enum dc_aspect_ratio
-+get_aspect_ratio(const struct drm_display_mode *mode_in)
-+{
-+	int32_t width = mode_in->crtc_hdisplay * 9;
-+	int32_t height = mode_in->crtc_vdisplay * 16;
-+
-+	if ((width - height) < 10 && (width - height) > -10)
-+		return ASPECT_RATIO_16_9;
-+	else
-+		return ASPECT_RATIO_4_3;
-+}
-+
-+static enum dc_color_space
-+get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
-+{
-+	enum dc_color_space color_space = COLOR_SPACE_SRGB;
-+
-+	switch (dc_crtc_timing->pixel_encoding)	{
-+	case PIXEL_ENCODING_YCBCR422:
-+	case PIXEL_ENCODING_YCBCR444:
-+	case PIXEL_ENCODING_YCBCR420:
-+	{
-+		/*
-+		 * 27030khz is the separation point between HDTV and SDTV
-+		 * according to HDMI spec, we use YCbCr709 and YCbCr601
-+		 * respectively
-+		 */
-+		if (dc_crtc_timing->pix_clk_khz > 27030) {
-+			if (dc_crtc_timing->flags.Y_ONLY)
-+				color_space =
-+					COLOR_SPACE_YCBCR709_LIMITED;
-+			else
-+				color_space = COLOR_SPACE_YCBCR709;
-+		} else {
-+			if (dc_crtc_timing->flags.Y_ONLY)
-+				color_space =
-+					COLOR_SPACE_YCBCR601_LIMITED;
-+			else
-+				color_space = COLOR_SPACE_YCBCR601;
-+		}
-+
-+	}
-+	break;
-+	case PIXEL_ENCODING_RGB:
-+		color_space = COLOR_SPACE_SRGB;
-+		break;
-+
-+	default:
-+		WARN_ON(1);
-+		break;
-+	}
-+
-+	return color_space;
-+}
-+
-+/*****************************************************************************/
-+
-+static void
-+fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
-+					     const struct drm_display_mode *mode_in,
-+					     const struct drm_connector *connector)
-+{
-+	struct dc_crtc_timing *timing_out = &stream->timing;
-+	struct dc_transfer_func *tf = dc_create_transfer_func();
-+
-+	memset(timing_out, 0, sizeof(struct dc_crtc_timing));
-+
-+	timing_out->h_border_left = 0;
-+	timing_out->h_border_right = 0;
-+	timing_out->v_border_top = 0;
-+	timing_out->v_border_bottom = 0;
-+	/* TODO: un-hardcode */
-+
-+	if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
-+			&& stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
-+	else
-+		timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
-+
-+	timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
-+	timing_out->display_color_depth = convert_color_depth_from_display_info(
-+			connector);
-+	timing_out->scan_type = SCANNING_TYPE_NODATA;
-+	timing_out->hdmi_vic = 0;
-+	timing_out->vic = drm_match_cea_mode(mode_in);
-+
-+	timing_out->h_addressable = mode_in->crtc_hdisplay;
-+	timing_out->h_total = mode_in->crtc_htotal;
-+	timing_out->h_sync_width =
-+		mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
-+	timing_out->h_front_porch =
-+		mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
-+	timing_out->v_total = mode_in->crtc_vtotal;
-+	timing_out->v_addressable = mode_in->crtc_vdisplay;
-+	timing_out->v_front_porch =
-+		mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
-+	timing_out->v_sync_width =
-+		mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
-+	timing_out->pix_clk_khz = mode_in->crtc_clock;
-+	timing_out->aspect_ratio = get_aspect_ratio(mode_in);
-+	if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
-+		timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
-+	if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
-+		timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
-+
-+	stream->output_color_space = get_output_color_space(timing_out);
-+
-+	tf->type = TF_TYPE_PREDEFINED;
-+	tf->tf = TRANSFER_FUNCTION_SRGB;
-+	stream->out_transfer_func = tf;
-+}
-+
-+static void fill_audio_info(struct audio_info *audio_info,
-+			    const struct drm_connector *drm_connector,
-+			    const struct dc_sink *dc_sink)
-+{
-+	int i = 0;
-+	int cea_revision = 0;
-+	const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
-+
-+	audio_info->manufacture_id = edid_caps->manufacturer_id;
-+	audio_info->product_id = edid_caps->product_id;
-+
-+	cea_revision = drm_connector->display_info.cea_rev;
-+
-+	strncpy(audio_info->display_name,
-+		edid_caps->display_name,
-+		AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
-+
-+	if (cea_revision >= 3) {
-+		audio_info->mode_count = edid_caps->audio_mode_count;
-+
-+		for (i = 0; i < audio_info->mode_count; ++i) {
-+			audio_info->modes[i].format_code =
-+					(enum audio_format_code)
-+					(edid_caps->audio_modes[i].format_code);
-+			audio_info->modes[i].channel_count =
-+					edid_caps->audio_modes[i].channel_count;
-+			audio_info->modes[i].sample_rates.all =
-+					edid_caps->audio_modes[i].sample_rate;
-+			audio_info->modes[i].sample_size =
-+					edid_caps->audio_modes[i].sample_size;
-+		}
-+	}
-+
-+	audio_info->flags.all = edid_caps->speaker_flags;
-+
-+	/* TODO: We only check for the progressive mode, check for interlace mode too */
-+	if (drm_connector->latency_present[0]) {
-+		audio_info->video_latency = drm_connector->video_latency[0];
-+		audio_info->audio_latency = drm_connector->audio_latency[0];
-+	}
-+
-+	/* TODO: For DP, video and audio latency should be calculated from DPCD caps */
-+
-+}
-+
-+static void
-+copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
-+				      struct drm_display_mode *dst_mode)
-+{
-+	dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
-+	dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
-+	dst_mode->crtc_clock = src_mode->crtc_clock;
-+	dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
-+	dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
-+	dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
-+	dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
-+	dst_mode->crtc_htotal = src_mode->crtc_htotal;
-+	dst_mode->crtc_hskew = src_mode->crtc_hskew;
-+	dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
-+	dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
-+	dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
-+	dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
-+	dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
-+}
-+
-+static void
-+decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
-+					const struct drm_display_mode *native_mode,
-+					bool scale_enabled)
-+{
-+	if (scale_enabled) {
-+		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
-+	} else if (native_mode->clock == drm_mode->clock &&
-+			native_mode->htotal == drm_mode->htotal &&
-+			native_mode->vtotal == drm_mode->vtotal) {
-+		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
-+	} else {
-+		/* no scaling nor amdgpu inserted, no need to patch */
-+	}
-+}
-+
-+static int create_fake_sink(struct amdgpu_dm_connector *aconnector)
-+{
-+	struct dc_sink *sink = NULL;
-+	struct dc_sink_init_data sink_init_data = { 0 };
-+
-+	sink_init_data.link = aconnector->dc_link;
-+	sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
-+
-+	sink = dc_sink_create(&sink_init_data);
-+	if (!sink) {
-+		DRM_ERROR("Failed to create sink!\n");
-+		return -ENOMEM;
-+	}
-+
-+	sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
-+	aconnector->fake_enable = true;
-+
-+	aconnector->dc_sink = sink;
-+	aconnector->dc_link->local_sink = sink;
-+
-+	return 0;
-+}
-+
-+static void set_multisync_trigger_params(
-+		struct dc_stream_state *stream)
-+{
-+	if (stream->triggered_crtc_reset.enabled) {
-+		stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
-+		stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
-+	}
-+}
-+
-+static void set_master_stream(struct dc_stream_state *stream_set[],
-+			      int stream_count)
-+{
-+	int j, highest_rfr = 0, master_stream = 0;
-+
-+	for (j = 0;  j < stream_count; j++) {
-+		if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
-+			int refresh_rate = 0;
-+
-+			refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
-+				(stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
-+			if (refresh_rate > highest_rfr) {
-+				highest_rfr = refresh_rate;
-+				master_stream = j;
-+			}
-+		}
-+	}
-+	for (j = 0;  j < stream_count; j++) {
-+		if (stream_set[j] && j != master_stream)
-+			stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
-+	}
-+}
-+
-+static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
-+{
-+	int i = 0;
-+
-+	if (context->stream_count < 2)
-+		return;
-+	for (i = 0; i < context->stream_count ; i++) {
-+		if (!context->streams[i])
-+			continue;
-+		/* TODO: add a function to read AMD VSDB bits and will set
-+		 * crtc_sync_master.multi_sync_enabled flag
-+		 * For now its set to false
-+		 */
-+		set_multisync_trigger_params(context->streams[i]);
-+	}
-+	set_master_stream(context->streams, context->stream_count);
-+}
-+
-+static struct dc_stream_state *
-+create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
-+		       const struct drm_display_mode *drm_mode,
-+		       const struct dm_connector_state *dm_state)
-+{
-+	struct drm_display_mode *preferred_mode = NULL;
-+	const struct drm_connector *drm_connector;
-+	struct dc_stream_state *stream = NULL;
-+	struct drm_display_mode mode = *drm_mode;
-+	bool native_mode_found = false;
-+
-+	if (aconnector == NULL) {
-+		DRM_ERROR("aconnector is NULL!\n");
-+		goto drm_connector_null;
-+	}
-+
-+	if (dm_state == NULL) {
-+		DRM_ERROR("dm_state is NULL!\n");
-+		goto dm_state_null;
-+	}
-+
-+	drm_connector = &aconnector->base;
-+
-+	if (!aconnector->dc_sink) {
-+		/*
-+		 * Exclude MST from creating fake_sink
-+		 * TODO: need to enable MST into fake_sink feature
-+		 */
-+		if (aconnector->mst_port)
-+			goto stream_create_fail;
-+
-+		if (create_fake_sink(aconnector))
-+			goto stream_create_fail;
-+	}
-+
-+	stream = dc_create_stream_for_sink(aconnector->dc_sink);
-+
-+	if (stream == NULL) {
-+		DRM_ERROR("Failed to create stream for sink!\n");
-+		goto stream_create_fail;
-+	}
-+
-+	list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
-+		/* Search for preferred mode */
-+		if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
-+			native_mode_found = true;
-+			break;
-+		}
-+	}
-+	if (!native_mode_found)
-+		preferred_mode = list_first_entry_or_null(
-+				&aconnector->base.modes,
-+				struct drm_display_mode,
-+				head);
-+
-+	if (preferred_mode == NULL) {
-+		/* This may not be an error, the use case is when we we have no
-+		 * usermode calls to reset and set mode upon hotplug. In this
-+		 * case, we call set mode ourselves to restore the previous mode
-+		 * and the modelist may not be filled in in time.
-+		 */
-+		DRM_DEBUG_DRIVER("No preferred mode found\n");
-+	} else {
-+		decide_crtc_timing_for_drm_display_mode(
-+				&mode, preferred_mode,
-+				dm_state->scaling != RMX_OFF);
-+	}
-+
-+	fill_stream_properties_from_drm_display_mode(stream,
-+			&mode, &aconnector->base);
-+	update_stream_scaling_settings(&mode, dm_state, stream);
-+
-+	fill_audio_info(
-+		&stream->audio_info,
-+		drm_connector,
-+		aconnector->dc_sink);
-+
-+stream_create_fail:
-+dm_state_null:
-+drm_connector_null:
-+	return stream;
-+}
-+
-+static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
-+{
-+	drm_crtc_cleanup(crtc);
-+	kfree(crtc);
-+}
-+
-+static void dm_crtc_destroy_state(struct drm_crtc *crtc,
-+				  struct drm_crtc_state *state)
-+{
-+	struct dm_crtc_state *cur = to_dm_crtc_state(state);
-+
-+	/* TODO Destroy dc_stream objects are stream object is flattened */
-+	if (cur->stream)
-+		dc_stream_release(cur->stream);
-+
-+
-+	__drm_atomic_helper_crtc_destroy_state(state);
-+
-+
-+	kfree(state);
-+}
-+
-+static void dm_crtc_reset_state(struct drm_crtc *crtc)
-+{
-+	struct dm_crtc_state *state;
-+
-+	if (crtc->state)
-+		dm_crtc_destroy_state(crtc, crtc->state);
-+
-+	state = kzalloc(sizeof(*state), GFP_KERNEL);
-+	if (WARN_ON(!state))
-+		return;
-+
-+	crtc->state = &state->base;
-+	crtc->state->crtc = crtc;
-+
-+}
-+
-+static struct drm_crtc_state *
-+dm_crtc_duplicate_state(struct drm_crtc *crtc)
-+{
-+	struct dm_crtc_state *state, *cur;
-+
-+	cur = to_dm_crtc_state(crtc->state);
-+
-+	if (WARN_ON(!crtc->state))
-+		return NULL;
-+
-+	state = kzalloc(sizeof(*state), GFP_KERNEL);
-+	if (!state)
-+		return NULL;
-+
-+	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
-+
-+	if (cur->stream) {
-+		state->stream = cur->stream;
-+		dc_stream_retain(state->stream);
-+	}
-+
-+	/* TODO Duplicate dc_stream after objects are stream object is flattened */
-+
-+	return &state->base;
-+}
-+
-+/* Implemented only the options currently availible for the driver */
-+static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
-+	.reset = dm_crtc_reset_state,
-+	.destroy = amdgpu_dm_crtc_destroy,
-+	.gamma_set = drm_atomic_helper_legacy_gamma_set,
-+	.set_config = drm_atomic_helper_set_config,
-+	.page_flip = drm_atomic_helper_page_flip,
-+	.atomic_duplicate_state = dm_crtc_duplicate_state,
-+	.atomic_destroy_state = dm_crtc_destroy_state,
-+};
-+
-+static enum drm_connector_status
-+amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
-+{
-+	bool connected;
-+	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
-+
-+	/* Notes:
-+	 * 1. This interface is NOT called in context of HPD irq.
-+	 * 2. This interface *is called* in context of user-mode ioctl. Which
-+	 * makes it a bad place for *any* MST-related activit. */
-+
-+	if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
-+	    !aconnector->fake_enable)
-+		connected = (aconnector->dc_sink != NULL);
-+	else
-+		connected = (aconnector->base.force == DRM_FORCE_ON);
-+
-+	return (connected ? connector_status_connected :
-+			connector_status_disconnected);
-+}
-+
-+int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
-+					    struct drm_connector_state *connector_state,
-+					    struct drm_property *property,
-+					    uint64_t val)
-+{
-+	struct drm_device *dev = connector->dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+	struct dm_connector_state *dm_old_state =
-+		to_dm_connector_state(connector->state);
-+	struct dm_connector_state *dm_new_state =
-+		to_dm_connector_state(connector_state);
-+
-+	int ret = -EINVAL;
-+
-+	if (property == dev->mode_config.scaling_mode_property) {
-+		enum amdgpu_rmx_type rmx_type;
-+
-+		switch (val) {
-+		case DRM_MODE_SCALE_CENTER:
-+			rmx_type = RMX_CENTER;
-+			break;
-+		case DRM_MODE_SCALE_ASPECT:
-+			rmx_type = RMX_ASPECT;
-+			break;
-+		case DRM_MODE_SCALE_FULLSCREEN:
-+			rmx_type = RMX_FULL;
-+			break;
-+		case DRM_MODE_SCALE_NONE:
-+		default:
-+			rmx_type = RMX_OFF;
-+			break;
-+		}
-+
-+		if (dm_old_state->scaling == rmx_type)
-+			return 0;
-+
-+		dm_new_state->scaling = rmx_type;
-+		ret = 0;
-+	} else if (property == adev->mode_info.underscan_hborder_property) {
-+		dm_new_state->underscan_hborder = val;
-+		ret = 0;
-+	} else if (property == adev->mode_info.underscan_vborder_property) {
-+		dm_new_state->underscan_vborder = val;
-+		ret = 0;
-+	} else if (property == adev->mode_info.underscan_property) {
-+		dm_new_state->underscan_enable = val;
-+		ret = 0;
-+	} else if (property == adev->mode_info.freesync_property) {
-+		struct amdgpu_crtc *acrtc;
-+		struct dm_crtc_state *acrtc_state;
-+
-+		dm_new_state->user_enable.enable_for_gaming = val;
-+		dm_new_state->user_enable.enable_for_static = val;
-+		dm_new_state->user_enable.enable_for_video = val;
-+
-+		if (adev->dm.freesync_module && connector_state->crtc) {
-+			acrtc = to_amdgpu_crtc(connector_state->crtc);
-+			acrtc_state = to_dm_crtc_state(connector_state->crtc->state);
-+			mod_freesync_set_user_enable(adev->dm.freesync_module,
-+						     &acrtc_state->stream, 1,
-+						     &dm_new_state->user_enable);
-+		}
-+
-+		ret = 0;
-+	} else if (property == adev->mode_info.freesync_capable_property) {
-+		dm_new_state->freesync_capable = val;
-+		ret = 0;
-+	}
-+
-+	return ret;
-+}
-+
-+int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
-+					    const struct drm_connector_state *state,
-+					    struct drm_property *property,
-+					    uint64_t *val)
-+{
-+	struct drm_device *dev = connector->dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+	struct dm_connector_state *dm_state =
-+		to_dm_connector_state(state);
-+	int ret = -EINVAL;
-+
-+	if (property == dev->mode_config.scaling_mode_property) {
-+		switch (dm_state->scaling) {
-+		case RMX_CENTER:
-+			*val = DRM_MODE_SCALE_CENTER;
-+			break;
-+		case RMX_ASPECT:
-+			*val = DRM_MODE_SCALE_ASPECT;
-+			break;
-+		case RMX_FULL:
-+			*val = DRM_MODE_SCALE_FULLSCREEN;
-+			break;
-+		case RMX_OFF:
-+		default:
-+			*val = DRM_MODE_SCALE_NONE;
-+			break;
-+		}
-+		ret = 0;
-+	} else if (property == adev->mode_info.underscan_hborder_property) {
-+		*val = dm_state->underscan_hborder;
-+		ret = 0;
-+	} else if (property == adev->mode_info.underscan_vborder_property) {
-+		*val = dm_state->underscan_vborder;
-+		ret = 0;
-+	} else if (property == adev->mode_info.underscan_property) {
-+		*val = dm_state->underscan_enable;
-+		ret = 0;
-+	} else if (property == adev->mode_info.freesync_property) {
-+		*val = dm_state->user_enable.enable_for_gaming;
-+		ret = 0;
-+	} else if (property == adev->mode_info.freesync_capable_property) {
-+		*val = dm_state->freesync_capable;
-+		ret = 0;
-+	}
-+	return ret;
-+}
-+
-+static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
-+{
-+	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
-+	const struct dc_link *link = aconnector->dc_link;
-+	struct amdgpu_device *adev = connector->dev->dev_private;
-+	struct amdgpu_display_manager *dm = &adev->dm;
-+#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
-+	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-+
-+	if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
-+		amdgpu_dm_register_backlight_device(dm);
-+
-+		if (dm->backlight_dev) {
-+			backlight_device_unregister(dm->backlight_dev);
-+			dm->backlight_dev = NULL;
-+		}
-+
-+	}
-+#endif
-+	drm_connector_unregister(connector);
-+	drm_connector_cleanup(connector);
-+	kfree(connector);
-+}
-+
-+void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
-+{
-+	struct dm_connector_state *state =
-+		to_dm_connector_state(connector->state);
-+
-+	kfree(state);
-+
-+	state = kzalloc(sizeof(*state), GFP_KERNEL);
-+
-+	if (state) {
-+		state->scaling = RMX_OFF;
-+		state->underscan_enable = false;
-+		state->underscan_hborder = 0;
-+		state->underscan_vborder = 0;
-+
-+		connector->state = &state->base;
-+		connector->state->connector = connector;
-+	}
-+}
-+
-+struct drm_connector_state *
-+amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
-+{
-+	struct dm_connector_state *state =
-+		to_dm_connector_state(connector->state);
-+
-+	struct dm_connector_state *new_state =
-+			kmemdup(state, sizeof(*state), GFP_KERNEL);
-+
-+	if (new_state) {
-+		__drm_atomic_helper_connector_duplicate_state(connector,
-+							      &new_state->base);
-+		return &new_state->base;
-+	}
-+
-+	return NULL;
-+}
-+
-+static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
-+	.reset = amdgpu_dm_connector_funcs_reset,
-+	.detect = amdgpu_dm_connector_detect,
-+	.fill_modes = drm_helper_probe_single_connector_modes,
-+	.destroy = amdgpu_dm_connector_destroy,
-+	.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
-+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-+	.atomic_set_property = amdgpu_dm_connector_atomic_set_property,
-+	.atomic_get_property = amdgpu_dm_connector_atomic_get_property
-+};
-+
-+static struct drm_encoder *best_encoder(struct drm_connector *connector)
-+{
-+	int enc_id = connector->encoder_ids[0];
-+	struct drm_mode_object *obj;
-+	struct drm_encoder *encoder;
-+
-+	DRM_DEBUG_DRIVER("Finding the best encoder\n");
-+
-+	/* pick the encoder ids */
-+	if (enc_id) {
-+		obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
-+		if (!obj) {
-+			DRM_ERROR("Couldn't find a matching encoder for our connector\n");
-+			return NULL;
-+		}
-+		encoder = obj_to_encoder(obj);
-+		return encoder;
-+	}
-+	DRM_ERROR("No encoder id\n");
-+	return NULL;
-+}
-+
-+static int get_modes(struct drm_connector *connector)
-+{
-+	return amdgpu_dm_connector_get_modes(connector);
-+}
-+
-+static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
-+{
-+	struct dc_sink_init_data init_params = {
-+			.link = aconnector->dc_link,
-+			.sink_signal = SIGNAL_TYPE_VIRTUAL
-+	};
-+	struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
-+
-+	if (!aconnector->base.edid_blob_ptr ||
-+		!aconnector->base.edid_blob_ptr->data) {
-+		DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
-+				aconnector->base.name);
-+
-+		aconnector->base.force = DRM_FORCE_OFF;
-+		aconnector->base.override_edid = false;
-+		return;
-+	}
-+
-+	aconnector->edid = edid;
-+
-+	aconnector->dc_em_sink = dc_link_add_remote_sink(
-+		aconnector->dc_link,
-+		(uint8_t *)edid,
-+		(edid->extensions + 1) * EDID_LENGTH,
-+		&init_params);
-+
-+	if (aconnector->base.force == DRM_FORCE_ON)
-+		aconnector->dc_sink = aconnector->dc_link->local_sink ?
-+		aconnector->dc_link->local_sink :
-+		aconnector->dc_em_sink;
-+}
-+
-+static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
-+{
-+	struct dc_link *link = (struct dc_link *)aconnector->dc_link;
-+
-+	/* In case of headless boot with force on for DP managed connector
-+	 * Those settings have to be != 0 to get initial modeset
-+	 */
-+	if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
-+		link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
-+		link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
-+	}
-+
-+
-+	aconnector->base.override_edid = true;
-+	create_eml_sink(aconnector);
-+}
-+
-+int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
-+				   struct drm_display_mode *mode)
-+{
-+	int result = MODE_ERROR;
-+	struct dc_sink *dc_sink;
-+	struct amdgpu_device *adev = connector->dev->dev_private;
-+	/* TODO: Unhardcode stream count */
-+	struct dc_stream_state *stream;
-+	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
-+
-+	if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
-+			(mode->flags & DRM_MODE_FLAG_DBLSCAN))
-+		return result;
-+
-+	/* Only run this the first time mode_valid is called to initilialize
-+	 * EDID mgmt
-+	 */
-+	if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
-+		!aconnector->dc_em_sink)
-+		handle_edid_mgmt(aconnector);
-+
-+	dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
-+
-+	if (dc_sink == NULL) {
-+		DRM_ERROR("dc_sink is NULL!\n");
-+		goto fail;
-+	}
-+
-+	stream = dc_create_stream_for_sink(dc_sink);
-+	if (stream == NULL) {
-+		DRM_ERROR("Failed to create stream for sink!\n");
-+		goto fail;
-+	}
-+
-+	drm_mode_set_crtcinfo(mode, 0);
-+	fill_stream_properties_from_drm_display_mode(stream, mode, connector);
-+
-+	stream->src.width = mode->hdisplay;
-+	stream->src.height = mode->vdisplay;
-+	stream->dst = stream->src;
-+
-+	if (dc_validate_stream(adev->dm.dc, stream) == DC_OK)
-+		result = MODE_OK;
-+
-+	dc_stream_release(stream);
-+
-+fail:
-+	/* TODO: error handling*/
-+	return result;
-+}
-+
-+static const struct drm_connector_helper_funcs
-+amdgpu_dm_connector_helper_funcs = {
-+	/*
-+	 * If hotplug a second bigger display in FB Con mode, bigger resolution
-+	 * modes will be filtered by drm_mode_validate_size(), and those modes
-+	 * is missing after user start lightdm. So we need to renew modes list.
-+	 * in get_modes call back, not just return the modes count
-+	 */
-+	.get_modes = get_modes,
-+	.mode_valid = amdgpu_dm_connector_mode_valid,
-+	.best_encoder = best_encoder
-+};
-+
-+static void dm_crtc_helper_disable(struct drm_crtc *crtc)
-+{
-+}
-+
-+static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
-+				       struct drm_crtc_state *state)
-+{
-+	struct amdgpu_device *adev = crtc->dev->dev_private;
-+	struct dc *dc = adev->dm.dc;
-+	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
-+	int ret = -EINVAL;
-+
-+	if (unlikely(!dm_crtc_state->stream &&
-+		     modeset_required(state, NULL, dm_crtc_state->stream))) {
-+		WARN_ON(1);
-+		return ret;
-+	}
-+
-+	/* In some use cases, like reset, no stream  is attached */
-+	if (!dm_crtc_state->stream)
-+		return 0;
-+
-+	if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
-+		return 0;
-+
-+	return ret;
-+}
-+
-+static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
-+				      const struct drm_display_mode *mode,
-+				      struct drm_display_mode *adjusted_mode)
-+{
-+	return true;
-+}
-+
-+static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
-+	.disable = dm_crtc_helper_disable,
-+	.atomic_check = dm_crtc_helper_atomic_check,
-+	.mode_fixup = dm_crtc_helper_mode_fixup
-+};
-+
-+static void dm_encoder_helper_disable(struct drm_encoder *encoder)
-+{
-+
-+}
-+
-+static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
-+					  struct drm_crtc_state *crtc_state,
-+					  struct drm_connector_state *conn_state)
-+{
-+	return 0;
-+}
-+
-+const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
-+	.disable = dm_encoder_helper_disable,
-+	.atomic_check = dm_encoder_helper_atomic_check
-+};
-+
-+static void dm_drm_plane_reset(struct drm_plane *plane)
-+{
-+	struct dm_plane_state *amdgpu_state = NULL;
-+
-+	if (plane->state)
-+		plane->funcs->atomic_destroy_state(plane, plane->state);
-+
-+	amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
-+	WARN_ON(amdgpu_state == NULL);
-+	
-+	if (amdgpu_state) {
-+		plane->state = &amdgpu_state->base;
-+		plane->state->plane = plane;
-+		plane->state->rotation = DRM_MODE_ROTATE_0;
-+	}
-+}
-+
-+static struct drm_plane_state *
-+dm_drm_plane_duplicate_state(struct drm_plane *plane)
-+{
-+	struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
-+
-+	old_dm_plane_state = to_dm_plane_state(plane->state);
-+	dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
-+	if (!dm_plane_state)
-+		return NULL;
-+
-+	__drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
-+
-+	if (old_dm_plane_state->dc_state) {
-+		dm_plane_state->dc_state = old_dm_plane_state->dc_state;
-+		dc_plane_state_retain(dm_plane_state->dc_state);
-+	}
-+
-+	return &dm_plane_state->base;
-+}
-+
-+void dm_drm_plane_destroy_state(struct drm_plane *plane,
-+				struct drm_plane_state *state)
-+{
-+	struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
-+
-+	if (dm_plane_state->dc_state)
-+		dc_plane_state_release(dm_plane_state->dc_state);
-+
-+	drm_atomic_helper_plane_destroy_state(plane, state);
-+}
-+
-+static const struct drm_plane_funcs dm_plane_funcs = {
-+	.update_plane	= drm_atomic_helper_update_plane,
-+	.disable_plane	= drm_atomic_helper_disable_plane,
-+	.destroy	= drm_plane_cleanup,
-+	.reset = dm_drm_plane_reset,
-+	.atomic_duplicate_state = dm_drm_plane_duplicate_state,
-+	.atomic_destroy_state = dm_drm_plane_destroy_state,
-+};
-+
-+static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
-+				      struct drm_plane_state *new_state)
-+{
-+	struct amdgpu_framebuffer *afb;
-+	struct drm_gem_object *obj;
-+	struct amdgpu_bo *rbo;
-+	uint64_t chroma_addr = 0;
-+	int r;
-+	struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
-+	unsigned int awidth;
-+
-+	dm_plane_state_old = to_dm_plane_state(plane->state);
-+	dm_plane_state_new = to_dm_plane_state(new_state);
-+
-+	if (!new_state->fb) {
-+		DRM_DEBUG_DRIVER("No FB bound\n");
-+		return 0;
-+	}
-+
-+	afb = to_amdgpu_framebuffer(new_state->fb);
-+
-+	obj = afb->obj;
-+	rbo = gem_to_amdgpu_bo(obj);
-+	r = amdgpu_bo_reserve(rbo, false);
-+	if (unlikely(r != 0))
-+		return r;
-+
-+	r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
-+
-+
-+	amdgpu_bo_unreserve(rbo);
-+
-+	if (unlikely(r != 0)) {
-+		if (r != -ERESTARTSYS)
-+			DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
-+		return r;
-+	}
-+
-+	amdgpu_bo_ref(rbo);
-+
-+	if (dm_plane_state_new->dc_state &&
-+			dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
-+		struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
-+
-+		if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-+			plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
-+			plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
-+		} else {
-+			awidth = ALIGN(new_state->fb->width, 64);
-+			plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
-+			plane_state->address.video_progressive.luma_addr.low_part
-+							= lower_32_bits(afb->address);
-+			plane_state->address.video_progressive.luma_addr.high_part
-+							= upper_32_bits(afb->address);
-+			chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
-+			plane_state->address.video_progressive.chroma_addr.low_part
-+							= lower_32_bits(chroma_addr);
-+			plane_state->address.video_progressive.chroma_addr.high_part
-+							= upper_32_bits(chroma_addr);
-+		}
-+	}
-+
-+	/* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
-+	 * prepare and cleanup in drm_atomic_helper_prepare_planes
-+	 * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
-+	 * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
-+	 * code touching fram buffers should be avoided for DC.
-+	 */
-+	if (plane->type == DRM_PLANE_TYPE_CURSOR) {
-+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
-+
-+		acrtc->cursor_bo = obj;
-+	}
-+	return 0;
-+}
-+
-+static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
-+				       struct drm_plane_state *old_state)
-+{
-+	struct amdgpu_bo *rbo;
-+	struct amdgpu_framebuffer *afb;
-+	int r;
-+
-+	if (!old_state->fb)
-+		return;
-+
-+	afb = to_amdgpu_framebuffer(old_state->fb);
-+	rbo = gem_to_amdgpu_bo(afb->obj);
-+	r = amdgpu_bo_reserve(rbo, false);
-+	if (unlikely(r)) {
-+		DRM_ERROR("failed to reserve rbo before unpin\n");
-+		return;
-+	}
-+
-+	amdgpu_bo_unpin(rbo);
-+	amdgpu_bo_unreserve(rbo);
-+	amdgpu_bo_unref(&rbo);
-+}
-+
-+static int dm_plane_atomic_check(struct drm_plane *plane,
-+				 struct drm_plane_state *state)
-+{
-+	struct amdgpu_device *adev = plane->dev->dev_private;
-+	struct dc *dc = adev->dm.dc;
-+	struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
-+
-+	if (!dm_plane_state->dc_state)
-+		return 0;
-+
-+	if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
-+		return 0;
-+
-+	return -EINVAL;
-+}
-+
-+static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
-+	.prepare_fb = dm_plane_helper_prepare_fb,
-+	.cleanup_fb = dm_plane_helper_cleanup_fb,
-+	.atomic_check = dm_plane_atomic_check,
-+};
-+
-+/*
-+ * TODO: these are currently initialized to rgb formats only.
-+ * For future use cases we should either initialize them dynamically based on
-+ * plane capabilities, or initialize this array to all formats, so internal drm
-+ * check will succeed, and let DC to implement proper check
-+ */
-+static const uint32_t rgb_formats[] = {
-+	DRM_FORMAT_RGB888,
-+	DRM_FORMAT_XRGB8888,
-+	DRM_FORMAT_ARGB8888,
-+	DRM_FORMAT_RGBA8888,
-+	DRM_FORMAT_XRGB2101010,
-+	DRM_FORMAT_XBGR2101010,
-+	DRM_FORMAT_ARGB2101010,
-+	DRM_FORMAT_ABGR2101010,
-+};
-+
-+static const uint32_t yuv_formats[] = {
-+	DRM_FORMAT_NV12,
-+	DRM_FORMAT_NV21,
-+};
-+
-+static const u32 cursor_formats[] = {
-+	DRM_FORMAT_ARGB8888
-+};
-+
-+static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
-+				struct amdgpu_plane *aplane,
-+				unsigned long possible_crtcs)
-+{
-+	int res = -EPERM;
-+
-+	switch (aplane->base.type) {
-+	case DRM_PLANE_TYPE_PRIMARY:
-+		aplane->base.format_default = true;
-+
-+		res = drm_universal_plane_init(
-+				dm->adev->ddev,
-+				&aplane->base,
-+				possible_crtcs,
-+				&dm_plane_funcs,
-+				rgb_formats,
-+				ARRAY_SIZE(rgb_formats),
-+				NULL, aplane->base.type, NULL);
-+		break;
-+	case DRM_PLANE_TYPE_OVERLAY:
-+		res = drm_universal_plane_init(
-+				dm->adev->ddev,
-+				&aplane->base,
-+				possible_crtcs,
-+				&dm_plane_funcs,
-+				yuv_formats,
-+				ARRAY_SIZE(yuv_formats),
-+				NULL, aplane->base.type, NULL);
-+		break;
-+	case DRM_PLANE_TYPE_CURSOR:
-+		res = drm_universal_plane_init(
-+				dm->adev->ddev,
-+				&aplane->base,
-+				possible_crtcs,
-+				&dm_plane_funcs,
-+				cursor_formats,
-+				ARRAY_SIZE(cursor_formats),
-+				NULL, aplane->base.type, NULL);
-+		break;
-+	}
-+
-+	drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
-+
-+	/* Create (reset) the plane state */
-+	if (aplane->base.funcs->reset)
-+		aplane->base.funcs->reset(&aplane->base);
-+
-+
-+	return res;
-+}
-+
-+static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
-+			       struct drm_plane *plane,
-+			       uint32_t crtc_index)
-+{
-+	struct amdgpu_crtc *acrtc = NULL;
-+	struct amdgpu_plane *cursor_plane;
-+
-+	int res = -ENOMEM;
-+
-+	cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
-+	if (!cursor_plane)
-+		goto fail;
-+
-+	cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
-+	res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
-+
-+	acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
-+	if (!acrtc)
-+		goto fail;
-+
-+	res = drm_crtc_init_with_planes(
-+			dm->ddev,
-+			&acrtc->base,
-+			plane,
-+			&cursor_plane->base,
-+			&amdgpu_dm_crtc_funcs, NULL);
-+
-+	if (res)
-+		goto fail;
-+
-+	drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
-+
-+	/* Create (reset) the plane state */
-+	if (acrtc->base.funcs->reset)
-+		acrtc->base.funcs->reset(&acrtc->base);
-+
-+	acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
-+	acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
-+
-+	acrtc->crtc_id = crtc_index;
-+	acrtc->base.enabled = false;
-+
-+	dm->adev->mode_info.crtcs[crtc_index] = acrtc;
-+	drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
-+
-+	return 0;
-+
-+fail:
-+	kfree(acrtc);
-+	kfree(cursor_plane);
-+	return res;
-+}
-+
-+
-+static int to_drm_connector_type(enum signal_type st)
-+{
-+	switch (st) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		return DRM_MODE_CONNECTOR_HDMIA;
-+	case SIGNAL_TYPE_EDP:
-+		return DRM_MODE_CONNECTOR_eDP;
-+	case SIGNAL_TYPE_RGB:
-+		return DRM_MODE_CONNECTOR_VGA;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		return DRM_MODE_CONNECTOR_DisplayPort;
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+		return DRM_MODE_CONNECTOR_DVID;
-+	case SIGNAL_TYPE_VIRTUAL:
-+		return DRM_MODE_CONNECTOR_VIRTUAL;
-+
-+	default:
-+		return DRM_MODE_CONNECTOR_Unknown;
-+	}
-+}
-+
-+static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
-+{
-+	const struct drm_connector_helper_funcs *helper =
-+		connector->helper_private;
-+	struct drm_encoder *encoder;
-+	struct amdgpu_encoder *amdgpu_encoder;
-+
-+	encoder = helper->best_encoder(connector);
-+
-+	if (encoder == NULL)
-+		return;
-+
-+	amdgpu_encoder = to_amdgpu_encoder(encoder);
-+
-+	amdgpu_encoder->native_mode.clock = 0;
-+
-+	if (!list_empty(&connector->probed_modes)) {
-+		struct drm_display_mode *preferred_mode = NULL;
-+
-+		list_for_each_entry(preferred_mode,
-+				    &connector->probed_modes,
-+				    head) {
-+			if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
-+				amdgpu_encoder->native_mode = *preferred_mode;
-+
-+			break;
-+		}
-+
-+	}
-+}
-+
-+static struct drm_display_mode *
-+amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
-+			     char *name,
-+			     int hdisplay, int vdisplay)
-+{
-+	struct drm_device *dev = encoder->dev;
-+	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
-+	struct drm_display_mode *mode = NULL;
-+	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
-+
-+	mode = drm_mode_duplicate(dev, native_mode);
-+
-+	if (mode == NULL)
-+		return NULL;
-+
-+	mode->hdisplay = hdisplay;
-+	mode->vdisplay = vdisplay;
-+	mode->type &= ~DRM_MODE_TYPE_PREFERRED;
-+	strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
-+
-+	return mode;
-+
-+}
-+
-+static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
-+						 struct drm_connector *connector)
-+{
-+	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
-+	struct drm_display_mode *mode = NULL;
-+	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
-+	struct amdgpu_dm_connector *amdgpu_dm_connector =
-+				to_amdgpu_dm_connector(connector);
-+	int i;
-+	int n;
-+	struct mode_size {
-+		char name[DRM_DISPLAY_MODE_LEN];
-+		int w;
-+		int h;
-+	} common_modes[] = {
-+		{  "640x480",  640,  480},
-+		{  "800x600",  800,  600},
-+		{ "1024x768", 1024,  768},
-+		{ "1280x720", 1280,  720},
-+		{ "1280x800", 1280,  800},
-+		{"1280x1024", 1280, 1024},
-+		{ "1440x900", 1440,  900},
-+		{"1680x1050", 1680, 1050},
-+		{"1600x1200", 1600, 1200},
-+		{"1920x1080", 1920, 1080},
-+		{"1920x1200", 1920, 1200}
-+	};
-+
-+	n = ARRAY_SIZE(common_modes);
-+
-+	for (i = 0; i < n; i++) {
-+		struct drm_display_mode *curmode = NULL;
-+		bool mode_existed = false;
-+
-+		if (common_modes[i].w > native_mode->hdisplay ||
-+		    common_modes[i].h > native_mode->vdisplay ||
-+		   (common_modes[i].w == native_mode->hdisplay &&
-+		    common_modes[i].h == native_mode->vdisplay))
-+			continue;
-+
-+		list_for_each_entry(curmode, &connector->probed_modes, head) {
-+			if (common_modes[i].w == curmode->hdisplay &&
-+			    common_modes[i].h == curmode->vdisplay) {
-+				mode_existed = true;
-+				break;
-+			}
-+		}
-+
-+		if (mode_existed)
-+			continue;
-+
-+		mode = amdgpu_dm_create_common_mode(encoder,
-+				common_modes[i].name, common_modes[i].w,
-+				common_modes[i].h);
-+		drm_mode_probed_add(connector, mode);
-+		amdgpu_dm_connector->num_modes++;
-+	}
-+}
-+
-+static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
-+					      struct edid *edid)
-+{
-+	struct amdgpu_dm_connector *amdgpu_dm_connector =
-+			to_amdgpu_dm_connector(connector);
-+
-+	if (edid) {
-+		/* empty probed_modes */
-+		INIT_LIST_HEAD(&connector->probed_modes);
-+		amdgpu_dm_connector->num_modes =
-+				drm_add_edid_modes(connector, edid);
-+
-+		drm_edid_to_eld(connector, edid);
-+
-+		amdgpu_dm_get_native_mode(connector);
-+	} else {
-+		amdgpu_dm_connector->num_modes = 0;
-+	}
-+}
-+
-+static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
-+{
-+	const struct drm_connector_helper_funcs *helper =
-+			connector->helper_private;
-+	struct amdgpu_dm_connector *amdgpu_dm_connector =
-+			to_amdgpu_dm_connector(connector);
-+	struct drm_encoder *encoder;
-+	struct edid *edid = amdgpu_dm_connector->edid;
-+
-+	encoder = helper->best_encoder(connector);
-+
-+	amdgpu_dm_connector_ddc_get_modes(connector, edid);
-+	amdgpu_dm_connector_add_common_modes(encoder, connector);
-+	return amdgpu_dm_connector->num_modes;
-+}
-+
-+void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
-+				     struct amdgpu_dm_connector *aconnector,
-+				     int connector_type,
-+				     struct dc_link *link,
-+				     int link_index)
-+{
-+	struct amdgpu_device *adev = dm->ddev->dev_private;
-+
-+	aconnector->connector_id = link_index;
-+	aconnector->dc_link = link;
-+	aconnector->base.interlace_allowed = false;
-+	aconnector->base.doublescan_allowed = false;
-+	aconnector->base.stereo_allowed = false;
-+	aconnector->base.dpms = DRM_MODE_DPMS_OFF;
-+	aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
-+
-+	mutex_init(&aconnector->hpd_lock);
-+
-+	/* configure support HPD hot plug connector_>polled default value is 0
-+	 * which means HPD hot plug not supported
-+	 */
-+	switch (connector_type) {
-+	case DRM_MODE_CONNECTOR_HDMIA:
-+		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
-+		break;
-+	case DRM_MODE_CONNECTOR_DisplayPort:
-+		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
-+		break;
-+	case DRM_MODE_CONNECTOR_DVID:
-+		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	drm_object_attach_property(&aconnector->base.base,
-+				dm->ddev->mode_config.scaling_mode_property,
-+				DRM_MODE_SCALE_NONE);
-+
-+	drm_object_attach_property(&aconnector->base.base,
-+				adev->mode_info.underscan_property,
-+				UNDERSCAN_OFF);
-+	drm_object_attach_property(&aconnector->base.base,
-+				adev->mode_info.underscan_hborder_property,
-+				0);
-+	drm_object_attach_property(&aconnector->base.base,
-+				adev->mode_info.underscan_vborder_property,
-+				0);
-+
-+	if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
-+	    connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
-+		drm_object_attach_property(&aconnector->base.base,
-+					  adev->mode_info.freesync_property, 0);
-+		drm_object_attach_property(&aconnector->base.base,
-+				      adev->mode_info.freesync_capable_property,
-+					   0);
-+	}
-+}
-+
-+static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
-+			      struct i2c_msg *msgs, int num)
-+{
-+	struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
-+	struct ddc_service *ddc_service = i2c->ddc_service;
-+	struct i2c_command cmd;
-+	int i;
-+	int result = -EIO;
-+
-+	cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
-+
-+	if (!cmd.payloads)
-+		return result;
-+
-+	cmd.number_of_payloads = num;
-+	cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
-+	cmd.speed = 100;
-+
-+	for (i = 0; i < num; i++) {
-+		cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
-+		cmd.payloads[i].address = msgs[i].addr;
-+		cmd.payloads[i].length = msgs[i].len;
-+		cmd.payloads[i].data = msgs[i].buf;
-+	}
-+
-+	if (dal_i2caux_submit_i2c_command(
-+			ddc_service->ctx->i2caux,
-+			ddc_service->ddc_pin,
-+			&cmd))
-+		result = num;
-+
-+	kfree(cmd.payloads);
-+	return result;
-+}
-+
-+static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
-+{
-+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
-+}
-+
-+static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
-+	.master_xfer = amdgpu_dm_i2c_xfer,
-+	.functionality = amdgpu_dm_i2c_func,
-+};
-+
-+static struct amdgpu_i2c_adapter *
-+create_i2c(struct ddc_service *ddc_service,
-+	   int link_index,
-+	   int *res)
-+{
-+	struct amdgpu_device *adev = ddc_service->ctx->driver_context;
-+	struct amdgpu_i2c_adapter *i2c;
-+
-+	i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
-+	if (!i2c)
-+		return NULL;
-+	i2c->base.owner = THIS_MODULE;
-+	i2c->base.class = I2C_CLASS_DDC;
-+	i2c->base.dev.parent = &adev->pdev->dev;
-+	i2c->base.algo = &amdgpu_dm_i2c_algo;
-+	snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
-+	i2c_set_adapdata(&i2c->base, i2c);
-+	i2c->ddc_service = ddc_service;
-+
-+	return i2c;
-+}
-+
-+/* Note: this function assumes that dc_link_detect() was called for the
-+ * dc_link which will be represented by this aconnector.
-+ */
-+static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
-+				    struct amdgpu_dm_connector *aconnector,
-+				    uint32_t link_index,
-+				    struct amdgpu_encoder *aencoder)
-+{
-+	int res = 0;
-+	int connector_type;
-+	struct dc *dc = dm->dc;
-+	struct dc_link *link = dc_get_link_at_index(dc, link_index);
-+	struct amdgpu_i2c_adapter *i2c;
-+
-+	link->priv = aconnector;
-+
-+	DRM_DEBUG_DRIVER("%s()\n", __func__);
-+
-+	i2c = create_i2c(link->ddc, link->link_index, &res);
-+	if (!i2c) {
-+		DRM_ERROR("Failed to create i2c adapter data\n");
-+		return -ENOMEM;
-+	}
-+
-+	aconnector->i2c = i2c;
-+	res = i2c_add_adapter(&i2c->base);
-+
-+	if (res) {
-+		DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
-+		goto out_free;
-+	}
-+
-+	connector_type = to_drm_connector_type(link->connector_signal);
-+
-+	res = drm_connector_init(
-+			dm->ddev,
-+			&aconnector->base,
-+			&amdgpu_dm_connector_funcs,
-+			connector_type);
-+
-+	if (res) {
-+		DRM_ERROR("connector_init failed\n");
-+		aconnector->connector_id = -1;
-+		goto out_free;
-+	}
-+
-+	drm_connector_helper_add(
-+			&aconnector->base,
-+			&amdgpu_dm_connector_helper_funcs);
-+
-+	if (aconnector->base.funcs->reset)
-+		aconnector->base.funcs->reset(&aconnector->base);
-+
-+	amdgpu_dm_connector_init_helper(
-+		dm,
-+		aconnector,
-+		connector_type,
-+		link,
-+		link_index);
-+
-+	drm_mode_connector_attach_encoder(
-+		&aconnector->base, &aencoder->base);
-+
-+	drm_connector_register(&aconnector->base);
-+
-+	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
-+		|| connector_type == DRM_MODE_CONNECTOR_eDP)
-+		amdgpu_dm_initialize_dp_connector(dm, aconnector);
-+
-+#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
-+	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-+
-+	/* NOTE: this currently will create backlight device even if a panel
-+	 * is not connected to the eDP/LVDS connector.
-+	 *
-+	 * This is less than ideal but we don't have sink information at this
-+	 * stage since detection happens after. We can't do detection earlier
-+	 * since MST detection needs connectors to be created first.
-+	 */
-+	if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
-+		/* Event if registration failed, we should continue with
-+		 * DM initialization because not having a backlight control
-+		 * is better then a black screen.
-+		 */
-+		amdgpu_dm_register_backlight_device(dm);
-+
-+		if (dm->backlight_dev)
-+			dm->backlight_link = link;
-+	}
-+#endif
-+
-+out_free:
-+	if (res) {
-+		kfree(i2c);
-+		aconnector->i2c = NULL;
-+	}
-+	return res;
-+}
-+
-+int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
-+{
-+	switch (adev->mode_info.num_crtc) {
-+	case 1:
-+		return 0x1;
-+	case 2:
-+		return 0x3;
-+	case 3:
-+		return 0x7;
-+	case 4:
-+		return 0xf;
-+	case 5:
-+		return 0x1f;
-+	case 6:
-+	default:
-+		return 0x3f;
-+	}
-+}
-+
-+static int amdgpu_dm_encoder_init(struct drm_device *dev,
-+				  struct amdgpu_encoder *aencoder,
-+				  uint32_t link_index)
-+{
-+	struct amdgpu_device *adev = dev->dev_private;
-+
-+	int res = drm_encoder_init(dev,
-+				   &aencoder->base,
-+				   &amdgpu_dm_encoder_funcs,
-+				   DRM_MODE_ENCODER_TMDS,
-+				   NULL);
-+
-+	aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
-+
-+	if (!res)
-+		aencoder->encoder_id = link_index;
-+	else
-+		aencoder->encoder_id = -1;
-+
-+	drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
-+
-+	return res;
-+}
-+
-+static void manage_dm_interrupts(struct amdgpu_device *adev,
-+				 struct amdgpu_crtc *acrtc,
-+				 bool enable)
-+{
-+	/*
-+	 * this is not correct translation but will work as soon as VBLANK
-+	 * constant is the same as PFLIP
-+	 */
-+	int irq_type =
-+		amdgpu_crtc_idx_to_irq_type(
-+			adev,
-+			acrtc->crtc_id);
-+
-+	if (enable) {
-+		drm_crtc_vblank_on(&acrtc->base);
-+		amdgpu_irq_get(
-+			adev,
-+			&adev->pageflip_irq,
-+			irq_type);
-+	} else {
-+
-+		amdgpu_irq_put(
-+			adev,
-+			&adev->pageflip_irq,
-+			irq_type);
-+		drm_crtc_vblank_off(&acrtc->base);
-+	}
-+}
-+
-+static bool
-+is_scaling_state_different(const struct dm_connector_state *dm_state,
-+			   const struct dm_connector_state *old_dm_state)
-+{
-+	if (dm_state->scaling != old_dm_state->scaling)
-+		return true;
-+	if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
-+		if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
-+			return true;
-+	} else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
-+		if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
-+			return true;
-+	} else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
-+		   dm_state->underscan_vborder != old_dm_state->underscan_vborder)
-+		return true;
-+	return false;
-+}
-+
-+static void remove_stream(struct amdgpu_device *adev,
-+			  struct amdgpu_crtc *acrtc,
-+			  struct dc_stream_state *stream)
-+{
-+	/* this is the update mode case */
-+	if (adev->dm.freesync_module)
-+		mod_freesync_remove_stream(adev->dm.freesync_module, stream);
-+
-+	acrtc->otg_inst = -1;
-+	acrtc->enabled = false;
-+}
-+
-+static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
-+			       struct dc_cursor_position *position)
-+{
-+	struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
-+	int x, y;
-+	int xorigin = 0, yorigin = 0;
-+
-+	if (!crtc || !plane->state->fb) {
-+		position->enable = false;
-+		position->x = 0;
-+		position->y = 0;
-+		return 0;
-+	}
-+
-+	if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
-+	    (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
-+		DRM_ERROR("%s: bad cursor width or height %d x %d\n",
-+			  __func__,
-+			  plane->state->crtc_w,
-+			  plane->state->crtc_h);
-+		return -EINVAL;
-+	}
-+
-+	x = plane->state->crtc_x;
-+	y = plane->state->crtc_y;
-+	/* avivo cursor are offset into the total surface */
-+	x += crtc->primary->state->src_x >> 16;
-+	y += crtc->primary->state->src_y >> 16;
-+	if (x < 0) {
-+		xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
-+		x = 0;
-+	}
-+	if (y < 0) {
-+		yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
-+		y = 0;
-+	}
-+	position->enable = true;
-+	position->x = x;
-+	position->y = y;
-+	position->x_hotspot = xorigin;
-+	position->y_hotspot = yorigin;
-+
-+	return 0;
-+}
-+
-+static void handle_cursor_update(struct drm_plane *plane,
-+				 struct drm_plane_state *old_plane_state)
-+{
-+	struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
-+	struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
-+	struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
-+	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-+	uint64_t address = afb ? afb->address : 0;
-+	struct dc_cursor_position position;
-+	struct dc_cursor_attributes attributes;
-+	int ret;
-+
-+	if (!plane->state->fb && !old_plane_state->fb)
-+		return;
-+
-+	DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
-+			 __func__,
-+			 amdgpu_crtc->crtc_id,
-+			 plane->state->crtc_w,
-+			 plane->state->crtc_h);
-+
-+	ret = get_cursor_position(plane, crtc, &position);
-+	if (ret)
-+		return;
-+
-+	if (!position.enable) {
-+		/* turn off cursor */
-+		if (crtc_state && crtc_state->stream)
-+			dc_stream_set_cursor_position(crtc_state->stream,
-+						      &position);
-+		return;
-+	}
-+
-+	amdgpu_crtc->cursor_width = plane->state->crtc_w;
-+	amdgpu_crtc->cursor_height = plane->state->crtc_h;
-+
-+	attributes.address.high_part = upper_32_bits(address);
-+	attributes.address.low_part  = lower_32_bits(address);
-+	attributes.width             = plane->state->crtc_w;
-+	attributes.height            = plane->state->crtc_h;
-+	attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
-+	attributes.rotation_angle    = 0;
-+	attributes.attribute_flags.value = 0;
-+
-+	attributes.pitch = attributes.width;
-+
-+	if (crtc_state->stream) {
-+		if (!dc_stream_set_cursor_attributes(crtc_state->stream,
-+							 &attributes))
-+			DRM_ERROR("DC failed to set cursor attributes\n");
-+
-+		if (!dc_stream_set_cursor_position(crtc_state->stream,
-+						   &position))
-+			DRM_ERROR("DC failed to set cursor position\n");
-+	}
-+}
-+
-+static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
-+{
-+
-+	assert_spin_locked(&acrtc->base.dev->event_lock);
-+	WARN_ON(acrtc->event);
-+
-+	acrtc->event = acrtc->base.state->event;
-+
-+	/* Set the flip status */
-+	acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
-+
-+	/* Mark this event as consumed */
-+	acrtc->base.state->event = NULL;
-+
-+	DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
-+						 acrtc->crtc_id);
-+}
-+
-+/*
-+ * Executes flip
-+ *
-+ * Waits on all BO's fences and for proper vblank count
-+ */
-+static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
-+			      struct drm_framebuffer *fb,
-+			      uint32_t target,
-+			      struct dc_state *state)
-+{
-+	unsigned long flags;
-+	uint32_t target_vblank;
-+	int r, vpos, hpos;
-+	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-+	struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
-+	struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
-+	struct amdgpu_device *adev = crtc->dev->dev_private;
-+	bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
-+	struct dc_flip_addrs addr = { {0} };
-+	/* TODO eliminate or rename surface_update */
-+	struct dc_surface_update surface_updates[1] = { {0} };
-+	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
-+
-+
-+	/* Prepare wait for target vblank early - before the fence-waits */
-+	target_vblank = target - drm_crtc_vblank_count(crtc) +
-+			amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
-+
-+	/* TODO This might fail and hence better not used, wait
-+	 * explicitly on fences instead
-+	 * and in general should be called for
-+	 * blocking commit to as per framework helpers
-+	 */
-+	r = amdgpu_bo_reserve(abo, true);
-+	if (unlikely(r != 0)) {
-+		DRM_ERROR("failed to reserve buffer before flip\n");
-+		WARN_ON(1);
-+	}
-+
-+	/* Wait for all fences on this FB */
-+	WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
-+								    MAX_SCHEDULE_TIMEOUT) < 0);
-+
-+	amdgpu_bo_unreserve(abo);
-+
-+	/* Wait until we're out of the vertical blank period before the one
-+	 * targeted by the flip
-+	 */
-+	while ((acrtc->enabled &&
-+		(amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
-+					&vpos, &hpos, NULL, NULL,
-+					&crtc->hwmode)
-+		 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
-+		(DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
-+		(int)(target_vblank -
-+		  amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
-+		usleep_range(1000, 1100);
-+	}
-+
-+	/* Flip */
-+	spin_lock_irqsave(&crtc->dev->event_lock, flags);
-+	/* update crtc fb */
-+	crtc->primary->fb = fb;
-+
-+	WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
-+	WARN_ON(!acrtc_state->stream);
-+
-+	addr.address.grph.addr.low_part = lower_32_bits(afb->address);
-+	addr.address.grph.addr.high_part = upper_32_bits(afb->address);
-+	addr.flip_immediate = async_flip;
-+
-+
-+	if (acrtc->base.state->event)
-+		prepare_flip_isr(acrtc);
-+
-+	surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
-+	surface_updates->flip_addr = &addr;
-+
-+
-+	dc_commit_updates_for_stream(adev->dm.dc,
-+					     surface_updates,
-+					     1,
-+					     acrtc_state->stream,
-+					     NULL,
-+					     &surface_updates->surface,
-+					     state);
-+
-+	DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
-+			 __func__,
-+			 addr.address.grph.addr.high_part,
-+			 addr.address.grph.addr.low_part);
-+
-+
-+	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
-+}
-+
-+static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
-+				    struct drm_device *dev,
-+				    struct amdgpu_display_manager *dm,
-+				    struct drm_crtc *pcrtc,
-+				    bool *wait_for_vblank)
-+{
-+	uint32_t i;
-+	struct drm_plane *plane;
-+	struct drm_plane_state *old_plane_state, *new_plane_state;
-+	struct dc_stream_state *dc_stream_attach;
-+	struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
-+	struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
-+	struct drm_crtc_state *new_pcrtc_state =
-+			drm_atomic_get_new_crtc_state(state, pcrtc);
-+	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
-+	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
-+	int planes_count = 0;
-+	unsigned long flags;
-+
-+	/* update planes when needed */
-+	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
-+		struct drm_crtc *crtc = new_plane_state->crtc;
-+		struct drm_crtc_state *new_crtc_state;
-+		struct drm_framebuffer *fb = new_plane_state->fb;
-+		bool pflip_needed;
-+		struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
-+
-+		if (plane->type == DRM_PLANE_TYPE_CURSOR) {
-+			handle_cursor_update(plane, old_plane_state);
-+			continue;
-+		}
-+
-+		if (!fb || !crtc || pcrtc != crtc)
-+			continue;
-+
-+		new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
-+		if (!new_crtc_state->active)
-+			continue;
-+
-+		pflip_needed = !state->allow_modeset;
-+
-+		spin_lock_irqsave(&crtc->dev->event_lock, flags);
-+		if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
-+			DRM_ERROR("%s: acrtc %d, already busy\n",
-+				  __func__,
-+				  acrtc_attach->crtc_id);
-+			/* In commit tail framework this cannot happen */
-+			WARN_ON(1);
-+		}
-+		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
-+
-+		if (!pflip_needed) {
-+			WARN_ON(!dm_new_plane_state->dc_state);
-+
-+			plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
-+
-+			dc_stream_attach = acrtc_state->stream;
-+			planes_count++;
-+
-+		} else if (new_crtc_state->planes_changed) {
-+			/* Assume even ONE crtc with immediate flip means
-+			 * entire can't wait for VBLANK
-+			 * TODO Check if it's correct
-+			 */
-+			*wait_for_vblank =
-+					new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
-+				false : true;
-+
-+			/* TODO: Needs rework for multiplane flip */
-+			if (plane->type == DRM_PLANE_TYPE_PRIMARY)
-+				drm_crtc_vblank_get(crtc);
-+
-+			amdgpu_dm_do_flip(
-+				crtc,
-+				fb,
-+				drm_crtc_vblank_count(crtc) + *wait_for_vblank,
-+				dm_state->context);
-+		}
-+
-+	}
-+
-+	if (planes_count) {
-+		unsigned long flags;
-+
-+		if (new_pcrtc_state->event) {
-+
-+			drm_crtc_vblank_get(pcrtc);
-+
-+			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
-+			prepare_flip_isr(acrtc_attach);
-+			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
-+		}
-+
-+		if (false == dc_commit_planes_to_stream(dm->dc,
-+							plane_states_constructed,
-+							planes_count,
-+							dc_stream_attach,
-+							dm_state->context))
-+			dm_error("%s: Failed to attach plane!\n", __func__);
-+	} else {
-+		/*TODO BUG Here should go disable planes on CRTC. */
-+	}
-+}
-+
-+
-+static int amdgpu_dm_atomic_commit(struct drm_device *dev,
-+				   struct drm_atomic_state *state,
-+				   bool nonblock)
-+{
-+	struct drm_crtc *crtc;
-+	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
-+	struct amdgpu_device *adev = dev->dev_private;
-+	int i;
-+
-+	/*
-+	 * We evade vblanks and pflips on crtc that
-+	 * should be changed. We do it here to flush & disable
-+	 * interrupts before drm_swap_state is called in drm_atomic_helper_commit
-+	 * it will update crtc->dm_crtc_state->stream pointer which is used in
-+	 * the ISRs.
-+	 */
-+	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
-+		struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
-+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-+
-+		if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
-+			manage_dm_interrupts(adev, acrtc, false);
-+	}
-+	/* Add check here for SoC's that support hardware cursor plane, to
-+	 * unset legacy_cursor_update */
-+
-+	return drm_atomic_helper_commit(dev, state, nonblock);
-+
-+	/*TODO Handle EINTR, reenable IRQ*/
-+}
-+
-+static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
-+{
-+	struct drm_device *dev = state->dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+	struct amdgpu_display_manager *dm = &adev->dm;
-+	struct dm_atomic_state *dm_state;
-+	uint32_t i, j;
-+	struct drm_crtc *crtc;
-+	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
-+	unsigned long flags;
-+	bool wait_for_vblank = true;
-+	struct drm_connector *connector;
-+	struct drm_connector_state *old_con_state, *new_con_state;
-+	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
-+
-+	drm_atomic_helper_update_legacy_modeset_state(dev, state);
-+
-+	dm_state = to_dm_atomic_state(state);
-+
-+	/* update changed items */
-+	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
-+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-+
-+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
-+		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
-+
-+		DRM_DEBUG_DRIVER(
-+			"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
-+			"planes_changed:%d, mode_changed:%d,active_changed:%d,"
-+			"connectors_changed:%d\n",
-+			acrtc->crtc_id,
-+			new_crtc_state->enable,
-+			new_crtc_state->active,
-+			new_crtc_state->planes_changed,
-+			new_crtc_state->mode_changed,
-+			new_crtc_state->active_changed,
-+			new_crtc_state->connectors_changed);
-+
-+		/* handles headless hotplug case, updating new_state and
-+		 * aconnector as needed
-+		 */
-+
-+		if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
-+
-+			DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
-+
-+			if (!dm_new_crtc_state->stream) {
-+				/*
-+				 * this could happen because of issues with
-+				 * userspace notifications delivery.
-+				 * In this case userspace tries to set mode on
-+				 * display which is disconnect in fact.
-+				 * dc_sink in NULL in this case on aconnector.
-+				 * We expect reset mode will come soon.
-+				 *
-+				 * This can also happen when unplug is done
-+				 * during resume sequence ended
-+				 *
-+				 * In this case, we want to pretend we still
-+				 * have a sink to keep the pipe running so that
-+				 * hw state is consistent with the sw state
-+				 */
-+				DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
-+						__func__, acrtc->base.base.id);
-+				continue;
-+			}
-+
-+			if (dm_old_crtc_state->stream)
-+				remove_stream(adev, acrtc, dm_old_crtc_state->stream);
-+
-+			acrtc->enabled = true;
-+			acrtc->hw_mode = new_crtc_state->mode;
-+			crtc->hwmode = new_crtc_state->mode;
-+		} else if (modereset_required(new_crtc_state)) {
-+			DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
-+
-+			/* i.e. reset mode */
-+			if (dm_old_crtc_state->stream)
-+				remove_stream(adev, acrtc, dm_old_crtc_state->stream);
-+		}
-+	} /* for_each_crtc_in_state() */
-+
-+	/*
-+	 * Add streams after required streams from new and replaced streams
-+	 * are removed from freesync module
-+	 */
-+	if (adev->dm.freesync_module) {
-+		for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
-+					      new_crtc_state, i) {
-+			struct amdgpu_dm_connector *aconnector = NULL;
-+			struct dm_connector_state *dm_new_con_state = NULL;
-+			struct amdgpu_crtc *acrtc = NULL;
-+			bool modeset_needed;
-+
-+			dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
-+			dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
-+			modeset_needed = modeset_required(
-+					new_crtc_state,
-+					dm_new_crtc_state->stream,
-+					dm_old_crtc_state->stream);
-+			/* We add stream to freesync if:
-+			 * 1. Said stream is not null, and
-+			 * 2. A modeset is requested. This means that the
-+			 *    stream was removed previously, and needs to be
-+			 *    replaced.
-+			 */
-+			if (dm_new_crtc_state->stream == NULL ||
-+					!modeset_needed)
-+				continue;
-+
-+			acrtc = to_amdgpu_crtc(crtc);
-+
-+			aconnector =
-+				amdgpu_dm_find_first_crtc_matching_connector(
-+					state, crtc);
-+			if (!aconnector) {
-+				DRM_DEBUG_DRIVER("Atomic commit: Failed to "
-+						 "find connector for acrtc "
-+						 "id:%d skipping freesync "
-+						 "init\n",
-+						 acrtc->crtc_id);
-+				continue;
-+			}
-+
-+			mod_freesync_add_stream(adev->dm.freesync_module,
-+						dm_new_crtc_state->stream,
-+						&aconnector->caps);
-+			new_con_state = drm_atomic_get_new_connector_state(
-+					state, &aconnector->base);
-+			dm_new_con_state = to_dm_connector_state(new_con_state);
-+
-+			mod_freesync_set_user_enable(adev->dm.freesync_module,
-+						     &dm_new_crtc_state->stream,
-+						     1,
-+						     &dm_new_con_state->user_enable);
-+		}
-+	}
-+
-+	if (dm_state->context) {
-+		dm_enable_per_frame_crtc_master_sync(dm_state->context);
-+		WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
-+	}
-+
-+	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
-+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-+
-+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
-+
-+		if (dm_new_crtc_state->stream != NULL) {
-+			const struct dc_stream_status *status =
-+					dc_stream_get_status(dm_new_crtc_state->stream);
-+
-+			if (!status)
-+				DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
-+			else
-+				acrtc->otg_inst = status->primary_otg_inst;
-+		}
-+	}
-+
-+	/* Handle scaling and underscan changes*/
-+	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
-+		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
-+		struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
-+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
-+		struct dc_stream_status *status = NULL;
-+
-+		if (acrtc)
-+			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
-+
-+		/* Skip any modesets/resets */
-+		if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
-+			continue;
-+
-+		/* Skip any thing not scale or underscan changes */
-+		if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
-+			continue;
-+
-+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
-+
-+		update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
-+				dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
-+
-+		status = dc_stream_get_status(dm_new_crtc_state->stream);
-+		WARN_ON(!status);
-+		WARN_ON(!status->plane_count);
-+
-+		if (!dm_new_crtc_state->stream)
-+			continue;
-+
-+		/*TODO How it works with MPO ?*/
-+		if (!dc_commit_planes_to_stream(
-+				dm->dc,
-+				status->plane_states,
-+				status->plane_count,
-+				dm_new_crtc_state->stream,
-+				dm_state->context))
-+			dm_error("%s: Failed to update stream scaling!\n", __func__);
-+	}
-+
-+	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
-+			new_crtc_state, i) {
-+		/*
-+		 * loop to enable interrupts on newly arrived crtc
-+		 */
-+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-+		bool modeset_needed;
-+
-+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
-+		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
-+		modeset_needed = modeset_required(
-+				new_crtc_state,
-+				dm_new_crtc_state->stream,
-+				dm_old_crtc_state->stream);
-+
-+		if (dm_new_crtc_state->stream == NULL || !modeset_needed)
-+			continue;
-+
-+		if (adev->dm.freesync_module)
-+			mod_freesync_notify_mode_change(
-+				adev->dm.freesync_module,
-+				&dm_new_crtc_state->stream, 1);
-+
-+		manage_dm_interrupts(adev, acrtc, true);
-+	}
-+
-+	/* update planes when needed per crtc*/
-+	for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
-+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
-+
-+		if (dm_new_crtc_state->stream)
-+			amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
-+	}
-+
-+
-+	/*
-+	 * send vblank event on all events not handled in flip and
-+	 * mark consumed event for drm_atomic_helper_commit_hw_done
-+	 */
-+	spin_lock_irqsave(&adev->ddev->event_lock, flags);
-+	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
-+
-+		if (new_crtc_state->event)
-+			drm_send_event_locked(dev, &new_crtc_state->event->base);
-+
-+		new_crtc_state->event = NULL;
-+	}
-+	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
-+
-+	/* Signal HW programming completion */
-+	drm_atomic_helper_commit_hw_done(state);
-+
-+	if (wait_for_vblank)
-+		drm_atomic_helper_wait_for_vblanks(dev, state);
-+
-+	drm_atomic_helper_cleanup_planes(dev, state);
-+}
-+
-+
-+static int dm_force_atomic_commit(struct drm_connector *connector)
-+{
-+	int ret = 0;
-+	struct drm_device *ddev = connector->dev;
-+	struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
-+	struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
-+	struct drm_plane *plane = disconnected_acrtc->base.primary;
-+	struct drm_connector_state *conn_state;
-+	struct drm_crtc_state *crtc_state;
-+	struct drm_plane_state *plane_state;
-+
-+	if (!state)
-+		return -ENOMEM;
-+
-+	state->acquire_ctx = ddev->mode_config.acquire_ctx;
-+
-+	/* Construct an atomic state to restore previous display setting */
-+
-+	/*
-+	 * Attach connectors to drm_atomic_state
-+	 */
-+	conn_state = drm_atomic_get_connector_state(state, connector);
-+
-+	ret = PTR_ERR_OR_ZERO(conn_state);
-+	if (ret)
-+		goto err;
-+
-+	/* Attach crtc to drm_atomic_state*/
-+	crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
-+
-+	ret = PTR_ERR_OR_ZERO(crtc_state);
-+	if (ret)
-+		goto err;
-+
-+	/* force a restore */
-+	crtc_state->mode_changed = true;
-+
-+	/* Attach plane to drm_atomic_state */
-+	plane_state = drm_atomic_get_plane_state(state, plane);
-+
-+	ret = PTR_ERR_OR_ZERO(plane_state);
-+	if (ret)
-+		goto err;
-+
-+
-+	/* Call commit internally with the state we just constructed */
-+	ret = drm_atomic_commit(state);
-+	if (!ret)
-+		return 0;
-+
-+err:
-+	DRM_ERROR("Restoring old state failed with %i\n", ret);
-+	drm_atomic_state_put(state);
-+
-+	return ret;
-+}
-+
-+/*
-+ * This functions handle all cases when set mode does not come upon hotplug.
-+ * This include when the same display is unplugged then plugged back into the
-+ * same port and when we are running without usermode desktop manager supprot
-+ */
-+void dm_restore_drm_connector_state(struct drm_device *dev,
-+				    struct drm_connector *connector)
-+{
-+	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
-+	struct amdgpu_crtc *disconnected_acrtc;
-+	struct dm_crtc_state *acrtc_state;
-+
-+	if (!aconnector->dc_sink || !connector->state || !connector->encoder)
-+		return;
-+
-+	disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
-+	acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
-+
-+	if (!disconnected_acrtc || !acrtc_state->stream)
-+		return;
-+
-+	/*
-+	 * If the previous sink is not released and different from the current,
-+	 * we deduce we are in a state where we can not rely on usermode call
-+	 * to turn on the display, so we do it here
-+	 */
-+	if (acrtc_state->stream->sink != aconnector->dc_sink)
-+		dm_force_atomic_commit(&aconnector->base);
-+}
-+
-+/*`
-+ * Grabs all modesetting locks to serialize against any blocking commits,
-+ * Waits for completion of all non blocking commits.
-+ */
-+static int do_aquire_global_lock(struct drm_device *dev,
-+				 struct drm_atomic_state *state)
-+{
-+	struct drm_crtc *crtc;
-+	struct drm_crtc_commit *commit;
-+	long ret;
-+
-+	/* Adding all modeset locks to aquire_ctx will
-+	 * ensure that when the framework release it the
-+	 * extra locks we are locking here will get released to
-+	 */
-+	ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
-+	if (ret)
-+		return ret;
-+
-+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-+		spin_lock(&crtc->commit_lock);
-+		commit = list_first_entry_or_null(&crtc->commit_list,
-+				struct drm_crtc_commit, commit_entry);
-+		if (commit)
-+			drm_crtc_commit_get(commit);
-+		spin_unlock(&crtc->commit_lock);
-+
-+		if (!commit)
-+			continue;
-+
-+		/* Make sure all pending HW programming completed and
-+		 * page flips done
-+		 */
-+		ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
-+
-+		if (ret > 0)
-+			ret = wait_for_completion_interruptible_timeout(
-+					&commit->flip_done, 10*HZ);
-+
-+		if (ret == 0)
-+			DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
-+				  "timed out\n", crtc->base.id, crtc->name);
-+
-+		drm_crtc_commit_put(commit);
-+	}
-+
-+	return ret < 0 ? ret : 0;
-+}
-+
-+static int dm_update_crtcs_state(struct dc *dc,
-+				 struct drm_atomic_state *state,
-+				 bool enable,
-+				 bool *lock_and_validation_needed)
-+{
-+	struct drm_crtc *crtc;
-+	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
-+	int i;
-+	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
-+	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
-+	struct dc_stream_state *new_stream;
-+	int ret = 0;
-+
-+	/*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
-+	/* update changed items */
-+	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
-+		struct amdgpu_crtc *acrtc = NULL;
-+		struct amdgpu_dm_connector *aconnector = NULL;
-+		struct drm_connector_state *new_con_state = NULL;
-+		struct dm_connector_state *dm_conn_state = NULL;
-+
-+		new_stream = NULL;
-+
-+		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
-+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
-+		acrtc = to_amdgpu_crtc(crtc);
-+
-+		aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
-+
-+		/* TODO This hack should go away */
-+		if (aconnector && enable) {
-+			// Make sure fake sink is created in plug-in scenario
-+			new_con_state = drm_atomic_get_connector_state(state,
-+ 								    &aconnector->base);
-+
-+			if (IS_ERR(new_con_state)) {
-+				ret = PTR_ERR_OR_ZERO(new_con_state);
-+				break;
-+			}
-+
-+			dm_conn_state = to_dm_connector_state(new_con_state);
-+
-+			new_stream = create_stream_for_sink(aconnector,
-+							     &new_crtc_state->mode,
-+							    dm_conn_state);
-+
-+			/*
-+			 * we can have no stream on ACTION_SET if a display
-+			 * was disconnected during S3, in this case it not and
-+			 * error, the OS will be updated after detection, and
-+			 * do the right thing on next atomic commit
-+			 */
-+
-+			if (!new_stream) {
-+				DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
-+						__func__, acrtc->base.base.id);
-+				break;
-+			}
-+		}
-+
-+		if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
-+				dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
-+
-+			new_crtc_state->mode_changed = false;
-+
-+			DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
-+				         new_crtc_state->mode_changed);
-+		}
-+
-+
-+		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
-+			goto next_crtc;
-+
-+		DRM_DEBUG_DRIVER(
-+			"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
-+			"planes_changed:%d, mode_changed:%d,active_changed:%d,"
-+			"connectors_changed:%d\n",
-+			acrtc->crtc_id,
-+			new_crtc_state->enable,
-+			new_crtc_state->active,
-+			new_crtc_state->planes_changed,
-+			new_crtc_state->mode_changed,
-+			new_crtc_state->active_changed,
-+			new_crtc_state->connectors_changed);
-+
-+		/* Remove stream for any changed/disabled CRTC */
-+		if (!enable) {
-+
-+			if (!dm_old_crtc_state->stream)
-+				goto next_crtc;
-+
-+			DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
-+					crtc->base.id);
-+
-+			/* i.e. reset mode */
-+			if (dc_remove_stream_from_ctx(
-+					dc,
-+					dm_state->context,
-+					dm_old_crtc_state->stream) != DC_OK) {
-+				ret = -EINVAL;
-+				goto fail;
-+			}
-+
-+			dc_stream_release(dm_old_crtc_state->stream);
-+			dm_new_crtc_state->stream = NULL;
-+
-+			*lock_and_validation_needed = true;
-+
-+		} else {/* Add stream for any updated/enabled CRTC */
-+			/*
-+			 * Quick fix to prevent NULL pointer on new_stream when
-+			 * added MST connectors not found in existing crtc_state in the chained mode
-+			 * TODO: need to dig out the root cause of that
-+			 */
-+			if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
-+				goto next_crtc;
-+
-+			if (modereset_required(new_crtc_state))
-+				goto next_crtc;
-+
-+			if (modeset_required(new_crtc_state, new_stream,
-+					     dm_old_crtc_state->stream)) {
-+
-+				WARN_ON(dm_new_crtc_state->stream);
-+
-+				dm_new_crtc_state->stream = new_stream;
-+				dc_stream_retain(new_stream);
-+
-+				DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
-+							crtc->base.id);
-+
-+				if (dc_add_stream_to_ctx(
-+						dc,
-+						dm_state->context,
-+						dm_new_crtc_state->stream) != DC_OK) {
-+					ret = -EINVAL;
-+					goto fail;
-+				}
-+
-+				*lock_and_validation_needed = true;
-+			}
-+		}
-+
-+next_crtc:
-+		/* Release extra reference */
-+		if (new_stream)
-+			 dc_stream_release(new_stream);
-+	}
-+
-+	return ret;
-+
-+fail:
-+	if (new_stream)
-+		dc_stream_release(new_stream);
-+	return ret;
-+}
-+
-+static int dm_update_planes_state(struct dc *dc,
-+				  struct drm_atomic_state *state,
-+				  bool enable,
-+				  bool *lock_and_validation_needed)
-+{
-+	struct drm_crtc *new_plane_crtc, *old_plane_crtc;
-+	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
-+	struct drm_plane *plane;
-+	struct drm_plane_state *old_plane_state, *new_plane_state;
-+	struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
-+	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
-+	struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
-+	int i ;
-+	/* TODO return page_flip_needed() function */
-+	bool pflip_needed  = !state->allow_modeset;
-+	int ret = 0;
-+
-+	if (pflip_needed)
-+		return ret;
-+
-+	/* Add new planes */
-+	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
-+		new_plane_crtc = new_plane_state->crtc;
-+		old_plane_crtc = old_plane_state->crtc;
-+		dm_new_plane_state = to_dm_plane_state(new_plane_state);
-+		dm_old_plane_state = to_dm_plane_state(old_plane_state);
-+
-+		/*TODO Implement atomic check for cursor plane */
-+		if (plane->type == DRM_PLANE_TYPE_CURSOR)
-+			continue;
-+
-+		/* Remove any changed/removed planes */
-+		if (!enable) {
-+
-+			if (!old_plane_crtc)
-+				continue;
-+
-+			old_crtc_state = drm_atomic_get_old_crtc_state(
-+					state, old_plane_crtc);
-+			dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
-+
-+			if (!dm_old_crtc_state->stream)
-+				continue;
-+
-+			DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
-+					plane->base.id, old_plane_crtc->base.id);
-+
-+			if (!dc_remove_plane_from_context(
-+					dc,
-+					dm_old_crtc_state->stream,
-+					dm_old_plane_state->dc_state,
-+					dm_state->context)) {
-+
-+				ret = EINVAL;
-+				return ret;
-+			}
-+
-+
-+			dc_plane_state_release(dm_old_plane_state->dc_state);
-+			dm_new_plane_state->dc_state = NULL;
-+
-+			*lock_and_validation_needed = true;
-+
-+		} else { /* Add new planes */
-+
-+			if (drm_atomic_plane_disabling(plane->state, new_plane_state))
-+				continue;
-+
-+			if (!new_plane_crtc)
-+				continue;
-+
-+			new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
-+			dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
-+
-+			if (!dm_new_crtc_state->stream)
-+				continue;
-+
-+
-+			WARN_ON(dm_new_plane_state->dc_state);
-+
-+			dm_new_plane_state->dc_state = dc_create_plane_state(dc);
-+
-+			DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
-+					plane->base.id, new_plane_crtc->base.id);
-+
-+			if (!dm_new_plane_state->dc_state) {
-+				ret = -EINVAL;
-+				return ret;
-+			}
-+
-+			ret = fill_plane_attributes(
-+				new_plane_crtc->dev->dev_private,
-+				dm_new_plane_state->dc_state,
-+				new_plane_state,
-+				new_crtc_state);
-+			if (ret)
-+				return ret;
-+
-+
-+			if (!dc_add_plane_to_context(
-+					dc,
-+					dm_new_crtc_state->stream,
-+					dm_new_plane_state->dc_state,
-+					dm_state->context)) {
-+
-+				ret = -EINVAL;
-+				return ret;
-+			}
-+
-+			*lock_and_validation_needed = true;
-+		}
-+	}
-+
-+
-+	return ret;
-+}
-+
-+static int amdgpu_dm_atomic_check(struct drm_device *dev,
-+				  struct drm_atomic_state *state)
-+{
-+	int i;
-+	int ret;
-+	struct amdgpu_device *adev = dev->dev_private;
-+	struct dc *dc = adev->dm.dc;
-+	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
-+	struct drm_connector *connector;
-+	struct drm_connector_state *old_con_state, *new_con_state;
-+	struct drm_crtc *crtc;
-+	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
-+
-+	/*
-+	 * This bool will be set for true for any modeset/reset
-+	 * or plane update which implies non fast surface update.
-+	 */
-+	bool lock_and_validation_needed = false;
-+
-+	ret = drm_atomic_helper_check_modeset(dev, state);
-+	if (ret)
-+		goto fail;
-+
-+	/*
-+	 * legacy_cursor_update should be made false for SoC's having
-+	 * a dedicated hardware plane for cursor in amdgpu_dm_atomic_commit(),
-+	 * otherwise for software cursor plane,
-+	 * we should not add it to list of affected planes.
-+	 */
-+	if (state->legacy_cursor_update) {
-+		for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
-+			if (new_crtc_state->color_mgmt_changed) {
-+				ret = drm_atomic_add_affected_planes(state, crtc);
-+				if (ret)
-+					goto fail;
-+			}
-+		}
-+	} else {
-+		for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
-+			if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
-+				continue;
-+
-+			if (!new_crtc_state->enable)
-+				continue;
-+
-+			ret = drm_atomic_add_affected_connectors(state, crtc);
-+			if (ret)
-+				return ret;
-+
-+			ret = drm_atomic_add_affected_planes(state, crtc);
-+			if (ret)
-+				goto fail;
-+		}
-+	}
-+
-+	dm_state->context = dc_create_state();
-+	ASSERT(dm_state->context);
-+	dc_resource_state_copy_construct_current(dc, dm_state->context);
-+
-+	/* Remove exiting planes if they are modified */
-+	ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
-+	if (ret) {
-+		goto fail;
-+	}
-+
-+	/* Disable all crtcs which require disable */
-+	ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
-+	if (ret) {
-+		goto fail;
-+	}
-+
-+	/* Enable all crtcs which require enable */
-+	ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
-+	if (ret) {
-+		goto fail;
-+	}
-+
-+	/* Add new/modified planes */
-+	ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
-+	if (ret) {
-+		goto fail;
-+	}
-+
-+	/* Run this here since we want to validate the streams we created */
-+	ret = drm_atomic_helper_check_planes(dev, state);
-+	if (ret)
-+		goto fail;
-+
-+	/* Check scaling and underscan changes*/
-+	/*TODO Removed scaling changes validation due to inability to commit
-+	 * new stream into context w\o causing full reset. Need to
-+	 * decide how to handle.
-+	 */
-+	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
-+		struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
-+		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
-+		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
-+
-+		/* Skip any modesets/resets */
-+		if (!acrtc || drm_atomic_crtc_needs_modeset(
-+				drm_atomic_get_new_crtc_state(state, &acrtc->base)))
-+			continue;
-+
-+		/* Skip any thing not scale or underscan changes */
-+		if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
-+			continue;
-+
-+		lock_and_validation_needed = true;
-+	}
-+
-+	/*
-+	 * For full updates case when
-+	 * removing/adding/updating  streams on once CRTC while flipping
-+	 * on another CRTC,
-+	 * acquiring global lock  will guarantee that any such full
-+	 * update commit
-+	 * will wait for completion of any outstanding flip using DRMs
-+	 * synchronization events.
-+	 */
-+
-+	if (lock_and_validation_needed) {
-+
-+		ret = do_aquire_global_lock(dev, state);
-+		if (ret)
-+			goto fail;
-+
-+		if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
-+			ret = -EINVAL;
-+			goto fail;
-+		}
-+	}
-+
-+	/* Must be success */
-+	WARN_ON(ret);
-+	return ret;
-+
-+fail:
-+	if (ret == -EDEADLK)
-+		DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
-+	else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
-+		DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
-+	else
-+		DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
-+
-+	return ret;
-+}
-+
-+static bool is_dp_capable_without_timing_msa(struct dc *dc,
-+					     struct amdgpu_dm_connector *amdgpu_dm_connector)
-+{
-+	uint8_t dpcd_data;
-+	bool capable = false;
-+
-+	if (amdgpu_dm_connector->dc_link &&
-+		dm_helpers_dp_read_dpcd(
-+				NULL,
-+				amdgpu_dm_connector->dc_link,
-+				DP_DOWN_STREAM_PORT_COUNT,
-+				&dpcd_data,
-+				sizeof(dpcd_data))) {
-+		capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
-+	}
-+
-+	return capable;
-+}
-+void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
-+					   struct edid *edid)
-+{
-+	int i;
-+	bool edid_check_required;
-+	struct detailed_timing *timing;
-+	struct detailed_non_pixel *data;
-+	struct detailed_data_monitor_range *range;
-+	struct amdgpu_dm_connector *amdgpu_dm_connector =
-+			to_amdgpu_dm_connector(connector);
-+	struct dm_connector_state *dm_con_state;
-+
-+	struct drm_device *dev = connector->dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+
-+	if (!connector->state) {
-+		DRM_ERROR("%s - Connector has no state", __func__);
-+		return;
-+	}
-+
-+	dm_con_state = to_dm_connector_state(connector->state);
-+
-+	edid_check_required = false;
-+	if (!amdgpu_dm_connector->dc_sink) {
-+		DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
-+		return;
-+	}
-+	if (!adev->dm.freesync_module)
-+		return;
-+	/*
-+	 * if edid non zero restrict freesync only for dp and edp
-+	 */
-+	if (edid) {
-+		if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
-+			|| amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
-+			edid_check_required = is_dp_capable_without_timing_msa(
-+						adev->dm.dc,
-+						amdgpu_dm_connector);
-+		}
-+	}
-+	dm_con_state->freesync_capable = false;
-+	if (edid_check_required == true && (edid->version > 1 ||
-+	   (edid->version == 1 && edid->revision > 1))) {
-+		for (i = 0; i < 4; i++) {
-+
-+			timing	= &edid->detailed_timings[i];
-+			data	= &timing->data.other_data;
-+			range	= &data->data.range;
-+			/*
-+			 * Check if monitor has continuous frequency mode
-+			 */
-+			if (data->type != EDID_DETAIL_MONITOR_RANGE)
-+				continue;
-+			/*
-+			 * Check for flag range limits only. If flag == 1 then
-+			 * no additional timing information provided.
-+			 * Default GTF, GTF Secondary curve and CVT are not
-+			 * supported
-+			 */
-+			if (range->flags != 1)
-+				continue;
-+
-+			amdgpu_dm_connector->min_vfreq = range->min_vfreq;
-+			amdgpu_dm_connector->max_vfreq = range->max_vfreq;
-+			amdgpu_dm_connector->pixel_clock_mhz =
-+				range->pixel_clock_mhz * 10;
-+			break;
-+		}
-+
-+		if (amdgpu_dm_connector->max_vfreq -
-+				amdgpu_dm_connector->min_vfreq > 10) {
-+			amdgpu_dm_connector->caps.supported = true;
-+			amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
-+					amdgpu_dm_connector->min_vfreq * 1000000;
-+			amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
-+					amdgpu_dm_connector->max_vfreq * 1000000;
-+			dm_con_state->freesync_capable = true;
-+		}
-+	}
-+
-+	dm_con_state->user_enable.enable_for_gaming = dm_con_state->freesync_capable;
-+	dm_con_state->user_enable.enable_for_static = dm_con_state->freesync_capable;
-+	dm_con_state->user_enable.enable_for_video = dm_con_state->freesync_capable;
-+}
-+
-+void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
-+{
-+	struct amdgpu_dm_connector *amdgpu_dm_connector =
-+			to_amdgpu_dm_connector(connector);
-+	struct dm_connector_state *dm_con_state;
-+	struct drm_device *dev = connector->dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+
-+	if (!amdgpu_dm_connector->dc_sink || !adev->dm.freesync_module) {
-+		DRM_ERROR("dc_sink NULL or no free_sync module.\n");
-+		return;
-+	}
-+
-+	if (!connector->state) {
-+		DRM_ERROR("%s - Connector has no state", __func__);
-+		return;
-+	}
-+
-+	dm_con_state = to_dm_connector_state(connector->state);
-+
-+	amdgpu_dm_connector->min_vfreq = 0;
-+	amdgpu_dm_connector->max_vfreq = 0;
-+	amdgpu_dm_connector->pixel_clock_mhz = 0;
-+
-+	memset(&amdgpu_dm_connector->caps, 0, sizeof(amdgpu_dm_connector->caps));
-+
-+	dm_con_state->freesync_capable = false;
-+
-+	dm_con_state->user_enable.enable_for_gaming = false;
-+	dm_con_state->user_enable.enable_for_static = false;
-+	dm_con_state->user_enable.enable_for_video = false;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h.0130~	2017-12-14 06:39:58.396903554 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h	2017-12-14 06:39:58.396903554 +0100
-@@ -0,0 +1,272 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __AMDGPU_DM_H__
-+#define __AMDGPU_DM_H__
-+
-+#include <drm/drmP.h>
-+#include <drm/drm_atomic.h>
-+#include "dc.h"
-+
-+/*
-+ * This file contains the definition for amdgpu_display_manager
-+ * and its API for amdgpu driver's use.
-+ * This component provides all the display related functionality
-+ * and this is the only component that calls DAL API.
-+ * The API contained here intended for amdgpu driver use.
-+ * The API that is called directly from KMS framework is located
-+ * in amdgpu_dm_kms.h file
-+ */
-+
-+#define AMDGPU_DM_MAX_DISPLAY_INDEX 31
-+/*
-+#include "include/amdgpu_dal_power_if.h"
-+#include "amdgpu_dm_irq.h"
-+*/
-+
-+#include "irq_types.h"
-+#include "signal_types.h"
-+
-+/* Forward declarations */
-+struct amdgpu_device;
-+struct drm_device;
-+struct amdgpu_dm_irq_handler_data;
-+
-+struct amdgpu_dm_prev_state {
-+	struct drm_framebuffer *fb;
-+	int32_t x;
-+	int32_t y;
-+	struct drm_display_mode mode;
-+};
-+
-+struct common_irq_params {
-+	struct amdgpu_device *adev;
-+	enum dc_irq_source irq_src;
-+};
-+
-+struct irq_list_head {
-+	struct list_head head;
-+	/* In case this interrupt needs post-processing, 'work' will be queued*/
-+	struct work_struct work;
-+};
-+
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+struct dm_comressor_info {
-+	void *cpu_addr;
-+	struct amdgpu_bo *bo_ptr;
-+	uint64_t gpu_addr;
-+};
-+#endif
-+
-+
-+struct amdgpu_display_manager {
-+	struct dal *dal;
-+	struct dc *dc;
-+	struct cgs_device *cgs_device;
-+	/* lock to be used when DAL is called from SYNC IRQ context */
-+	spinlock_t dal_lock;
-+
-+	struct amdgpu_device *adev;	/*AMD base driver*/
-+	struct drm_device *ddev;	/*DRM base driver*/
-+	u16 display_indexes_num;
-+
-+	struct amdgpu_dm_prev_state prev_state;
-+
-+	/*
-+	 * 'irq_source_handler_table' holds a list of handlers
-+	 * per (DAL) IRQ source.
-+	 *
-+	 * Each IRQ source may need to be handled at different contexts.
-+	 * By 'context' we mean, for example:
-+	 * - The ISR context, which is the direct interrupt handler.
-+	 * - The 'deferred' context - this is the post-processing of the
-+	 *	interrupt, but at a lower priority.
-+	 *
-+	 * Note that handlers are called in the same order as they were
-+	 * registered (FIFO).
-+	 */
-+	struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
-+	struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
-+
-+	struct common_irq_params
-+	pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
-+
-+	struct common_irq_params
-+	vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
-+
-+	/* this spin lock synchronizes access to 'irq_handler_list_table' */
-+	spinlock_t irq_handler_list_table_lock;
-+
-+	/* Timer-related data. */
-+	struct list_head timer_handler_list;
-+	struct workqueue_struct *timer_workqueue;
-+
-+	/* Use dal_mutex for any activity which is NOT syncronized by
-+	 * DRM mode setting locks.
-+	 * For example: amdgpu_dm_hpd_low_irq() calls into DAL *without*
-+	 * DRM mode setting locks being acquired. This is where dal_mutex
-+	 * is acquired before calling into DAL. */
-+	struct mutex dal_mutex;
-+
-+	struct backlight_device *backlight_dev;
-+
-+	const struct dc_link *backlight_link;
-+
-+	struct work_struct mst_hotplug_work;
-+
-+	struct mod_freesync *freesync_module;
-+
-+	/**
-+	 * Caches device atomic state for suspend/resume
-+	 */
-+	struct drm_atomic_state *cached_state;
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+	struct dm_comressor_info compressor;
-+#endif
-+};
-+
-+struct amdgpu_dm_connector {
-+
-+	struct drm_connector base;
-+	uint32_t connector_id;
-+
-+	/* we need to mind the EDID between detect
-+	   and get modes due to analog/digital/tvencoder */
-+	struct edid *edid;
-+
-+	/* shared with amdgpu */
-+	struct amdgpu_hpd hpd;
-+
-+	/* number of modes generated from EDID at 'dc_sink' */
-+	int num_modes;
-+
-+	/* The 'old' sink - before an HPD.
-+	 * The 'current' sink is in dc_link->sink. */
-+	struct dc_sink *dc_sink;
-+	struct dc_link *dc_link;
-+	struct dc_sink *dc_em_sink;
-+
-+	/* DM only */
-+	struct drm_dp_mst_topology_mgr mst_mgr;
-+	struct amdgpu_dm_dp_aux dm_dp_aux;
-+	struct drm_dp_mst_port *port;
-+	struct amdgpu_dm_connector *mst_port;
-+	struct amdgpu_encoder *mst_encoder;
-+
-+	/* TODO see if we can merge with ddc_bus or make a dm_connector */
-+	struct amdgpu_i2c_adapter *i2c;
-+
-+	/* Monitor range limits */
-+	int min_vfreq ;
-+	int max_vfreq ;
-+	int pixel_clock_mhz;
-+
-+	/*freesync caps*/
-+	struct mod_freesync_caps caps;
-+
-+	struct mutex hpd_lock;
-+
-+	bool fake_enable;
-+};
-+
-+#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
-+
-+extern const struct amdgpu_ip_block_version dm_ip_block;
-+
-+struct amdgpu_framebuffer;
-+struct amdgpu_display_manager;
-+struct dc_validation_set;
-+struct dc_plane_state;
-+
-+struct dm_plane_state {
-+	struct drm_plane_state base;
-+	struct dc_plane_state *dc_state;
-+};
-+
-+struct dm_crtc_state {
-+	struct drm_crtc_state base;
-+	struct dc_stream_state *stream;
-+};
-+
-+#define to_dm_crtc_state(x)    container_of(x, struct dm_crtc_state, base)
-+
-+struct dm_atomic_state {
-+	struct drm_atomic_state base;
-+
-+	struct dc_state *context;
-+};
-+
-+#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
-+
-+struct dm_connector_state {
-+	struct drm_connector_state base;
-+
-+	enum amdgpu_rmx_type scaling;
-+	uint8_t underscan_vborder;
-+	uint8_t underscan_hborder;
-+	bool underscan_enable;
-+	struct mod_freesync_user_enable user_enable;
-+	bool freesync_capable;
-+};
-+
-+#define to_dm_connector_state(x)\
-+	container_of((x), struct dm_connector_state, base)
-+
-+void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
-+struct drm_connector_state *
-+amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
-+int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
-+					    struct drm_connector_state *state,
-+					    struct drm_property *property,
-+					    uint64_t val);
-+
-+int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
-+					    const struct drm_connector_state *state,
-+					    struct drm_property *property,
-+					    uint64_t *val);
-+
-+int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
-+
-+void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
-+				     struct amdgpu_dm_connector *aconnector,
-+				     int connector_type,
-+				     struct dc_link *link,
-+				     int link_index);
-+
-+int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
-+				   struct drm_display_mode *mode);
-+
-+void dm_restore_drm_connector_state(struct drm_device *dev,
-+				    struct drm_connector *connector);
-+
-+void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
-+					   struct edid *edid);
-+
-+void
-+amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector);
-+
-+extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
-+
-+#endif /* __AMDGPU_DM_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c.0130~	2017-12-14 06:39:58.396903554 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c	2017-12-14 06:39:58.396903554 +0100
-@@ -0,0 +1,498 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include <linux/string.h>
-+#include <linux/acpi.h>
-+#include <linux/version.h>
-+#include <linux/i2c.h>
-+
-+#include <drm/drmP.h>
-+#include <drm/drm_crtc_helper.h>
-+#include <drm/amdgpu_drm.h>
-+#include <drm/drm_edid.h>
-+
-+#include "dm_services.h"
-+#include "amdgpu.h"
-+#include "dc.h"
-+#include "amdgpu_dm.h"
-+#include "amdgpu_dm_irq.h"
-+
-+#include "dm_helpers.h"
-+
-+/* dm_helpers_parse_edid_caps
-+ *
-+ * Parse edid caps
-+ *
-+ * @edid:	[in] pointer to edid
-+ *  edid_caps:	[in] pointer to edid caps
-+ * @return
-+ *	void
-+ * */
-+enum dc_edid_status dm_helpers_parse_edid_caps(
-+		struct dc_context *ctx,
-+		const struct dc_edid *edid,
-+		struct dc_edid_caps *edid_caps)
-+{
-+	struct edid *edid_buf = (struct edid *) edid->raw_edid;
-+	struct cea_sad *sads;
-+	int sad_count = -1;
-+	int sadb_count = -1;
-+	int i = 0;
-+	int j = 0;
-+	uint8_t *sadb = NULL;
-+
-+	enum dc_edid_status result = EDID_OK;
-+
-+	if (!edid_caps || !edid)
-+		return EDID_BAD_INPUT;
-+
-+	if (!drm_edid_is_valid(edid_buf))
-+		result = EDID_BAD_CHECKSUM;
-+
-+	edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
-+					((uint16_t) edid_buf->mfg_id[1])<<8;
-+	edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
-+					((uint16_t) edid_buf->prod_code[1])<<8;
-+	edid_caps->serial_number = edid_buf->serial;
-+	edid_caps->manufacture_week = edid_buf->mfg_week;
-+	edid_caps->manufacture_year = edid_buf->mfg_year;
-+
-+	/* One of the four detailed_timings stores the monitor name. It's
-+	 * stored in an array of length 13. */
-+	for (i = 0; i < 4; i++) {
-+		if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) {
-+			while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) {
-+				if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n')
-+					break;
-+
-+				edid_caps->display_name[j] =
-+					edid_buf->detailed_timings[i].data.other_data.data.str.str[j];
-+				j++;
-+			}
-+		}
-+	}
-+
-+	edid_caps->edid_hdmi = drm_detect_hdmi_monitor(
-+			(struct edid *) edid->raw_edid);
-+
-+	sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
-+	if (sad_count <= 0) {
-+		DRM_INFO("SADs count is: %d, don't need to read it\n",
-+				sad_count);
-+		return result;
-+	}
-+
-+	edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;
-+	for (i = 0; i < edid_caps->audio_mode_count; ++i) {
-+		struct cea_sad *sad = &sads[i];
-+
-+		edid_caps->audio_modes[i].format_code = sad->format;
-+		edid_caps->audio_modes[i].channel_count = sad->channels;
-+		edid_caps->audio_modes[i].sample_rate = sad->freq;
-+		edid_caps->audio_modes[i].sample_size = sad->byte2;
-+	}
-+
-+	sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
-+
-+	if (sadb_count < 0) {
-+		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
-+		sadb_count = 0;
-+	}
-+
-+	if (sadb_count)
-+		edid_caps->speaker_flags = sadb[0];
-+	else
-+		edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
-+
-+	kfree(sads);
-+	kfree(sadb);
-+
-+	return result;
-+}
-+
-+static void get_payload_table(
-+		struct amdgpu_dm_connector *aconnector,
-+		struct dp_mst_stream_allocation_table *proposed_table)
-+{
-+	int i;
-+	struct drm_dp_mst_topology_mgr *mst_mgr =
-+			&aconnector->mst_port->mst_mgr;
-+
-+	mutex_lock(&mst_mgr->payload_lock);
-+
-+	proposed_table->stream_count = 0;
-+
-+	/* number of active streams */
-+	for (i = 0; i < mst_mgr->max_payloads; i++) {
-+		if (mst_mgr->payloads[i].num_slots == 0)
-+			break; /* end of vcp_id table */
-+
-+		ASSERT(mst_mgr->payloads[i].payload_state !=
-+				DP_PAYLOAD_DELETE_LOCAL);
-+
-+		if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL ||
-+			mst_mgr->payloads[i].payload_state ==
-+					DP_PAYLOAD_REMOTE) {
-+
-+			struct dp_mst_stream_allocation *sa =
-+					&proposed_table->stream_allocations[
-+						proposed_table->stream_count];
-+
-+			sa->slot_count = mst_mgr->payloads[i].num_slots;
-+			sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi;
-+			proposed_table->stream_count++;
-+		}
-+	}
-+
-+	mutex_unlock(&mst_mgr->payload_lock);
-+}
-+
-+/*
-+ * Writes payload allocation table in immediate downstream device.
-+ */
-+bool dm_helpers_dp_mst_write_payload_allocation_table(
-+		struct dc_context *ctx,
-+		const struct dc_stream_state *stream,
-+		struct dp_mst_stream_allocation_table *proposed_table,
-+		bool enable)
-+{
-+	struct amdgpu_dm_connector *aconnector;
-+	struct drm_dp_mst_topology_mgr *mst_mgr;
-+	struct drm_dp_mst_port *mst_port;
-+	int slots = 0;
-+	bool ret;
-+	int clock;
-+	int bpp = 0;
-+	int pbn = 0;
-+
-+	aconnector = stream->sink->priv;
-+
-+	if (!aconnector || !aconnector->mst_port)
-+		return false;
-+
-+	mst_mgr = &aconnector->mst_port->mst_mgr;
-+
-+	if (!mst_mgr->mst_state)
-+		return false;
-+
-+	mst_port = aconnector->port;
-+
-+	if (enable) {
-+		clock = stream->timing.pix_clk_khz;
-+
-+		switch (stream->timing.display_color_depth) {
-+
-+		case COLOR_DEPTH_666:
-+			bpp = 6;
-+			break;
-+		case COLOR_DEPTH_888:
-+			bpp = 8;
-+			break;
-+		case COLOR_DEPTH_101010:
-+			bpp = 10;
-+			break;
-+		case COLOR_DEPTH_121212:
-+			bpp = 12;
-+			break;
-+		case COLOR_DEPTH_141414:
-+			bpp = 14;
-+			break;
-+		case COLOR_DEPTH_161616:
-+			bpp = 16;
-+			break;
-+		default:
-+			ASSERT(bpp != 0);
-+			break;
-+		}
-+
-+		bpp = bpp * 3;
-+
-+		/* TODO need to know link rate */
-+
-+		pbn = drm_dp_calc_pbn_mode(clock, bpp);
-+
-+		slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
-+		ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
-+
-+		if (!ret)
-+			return false;
-+
-+	} else {
-+		drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port);
-+	}
-+
-+	ret = drm_dp_update_payload_part1(mst_mgr);
-+
-+	/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
-+	 * AUX message. The sequence is slot 1-63 allocated sequence for each
-+	 * stream. AMD ASIC stream slot allocation should follow the same
-+	 * sequence. copy DRM MST allocation to dc */
-+
-+	get_payload_table(aconnector, proposed_table);
-+
-+	if (ret)
-+		return false;
-+
-+	return true;
-+}
-+
-+/*
-+ * Polls for ACT (allocation change trigger) handled and sends
-+ * ALLOCATE_PAYLOAD message.
-+ */
-+bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
-+		struct dc_context *ctx,
-+		const struct dc_stream_state *stream)
-+{
-+	struct amdgpu_dm_connector *aconnector;
-+	struct drm_dp_mst_topology_mgr *mst_mgr;
-+	int ret;
-+
-+	aconnector = stream->sink->priv;
-+
-+	if (!aconnector || !aconnector->mst_port)
-+		return false;
-+
-+	mst_mgr = &aconnector->mst_port->mst_mgr;
-+
-+	if (!mst_mgr->mst_state)
-+		return false;
-+
-+	ret = drm_dp_check_act_status(mst_mgr);
-+
-+	if (ret)
-+		return false;
-+
-+	return true;
-+}
-+
-+bool dm_helpers_dp_mst_send_payload_allocation(
-+		struct dc_context *ctx,
-+		const struct dc_stream_state *stream,
-+		bool enable)
-+{
-+	struct amdgpu_dm_connector *aconnector;
-+	struct drm_dp_mst_topology_mgr *mst_mgr;
-+	struct drm_dp_mst_port *mst_port;
-+	int ret;
-+
-+	aconnector = stream->sink->priv;
-+
-+	if (!aconnector || !aconnector->mst_port)
-+		return false;
-+
-+	mst_port = aconnector->port;
-+
-+	mst_mgr = &aconnector->mst_port->mst_mgr;
-+
-+	if (!mst_mgr->mst_state)
-+		return false;
-+
-+	ret = drm_dp_update_payload_part2(mst_mgr);
-+
-+	if (ret)
-+		return false;
-+
-+	if (!enable)
-+		drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
-+
-+	return true;
-+}
-+
-+bool dm_helpers_dc_conn_log(struct dc_context *ctx, struct log_entry *entry, enum dc_log_type event)
-+{
-+	return true;
-+}
-+
-+void dm_dtn_log_begin(struct dc_context *ctx)
-+{}
-+
-+void dm_dtn_log_append_v(struct dc_context *ctx,
-+		const char *pMsg, ...)
-+{}
-+
-+void dm_dtn_log_end(struct dc_context *ctx)
-+{}
-+
-+bool dm_helpers_dp_mst_start_top_mgr(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		bool boot)
-+{
-+	struct amdgpu_dm_connector *aconnector = link->priv;
-+
-+	if (!aconnector) {
-+			DRM_ERROR("Failed to found connector for link!");
-+			return false;
-+	}
-+
-+	if (boot) {
-+		DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
-+					aconnector, aconnector->base.base.id);
-+		return true;
-+	}
-+
-+	DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
-+			aconnector, aconnector->base.base.id);
-+
-+	return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0);
-+}
-+
-+void dm_helpers_dp_mst_stop_top_mgr(
-+		struct dc_context *ctx,
-+		const struct dc_link *link)
-+{
-+	struct amdgpu_dm_connector *aconnector = link->priv;
-+
-+	if (!aconnector) {
-+			DRM_ERROR("Failed to found connector for link!");
-+			return;
-+	}
-+
-+	DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
-+			aconnector, aconnector->base.base.id);
-+
-+	if (aconnector->mst_mgr.mst_state == true)
-+		drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
-+}
-+
-+bool dm_helpers_dp_read_dpcd(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint32_t address,
-+		uint8_t *data,
-+		uint32_t size)
-+{
-+
-+	struct amdgpu_dm_connector *aconnector = link->priv;
-+
-+	if (!aconnector) {
-+		DRM_ERROR("Failed to found connector for link!");
-+		return false;
-+	}
-+
-+	return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address,
-+			data, size) > 0;
-+}
-+
-+bool dm_helpers_dp_write_dpcd(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint32_t address,
-+		const uint8_t *data,
-+		uint32_t size)
-+{
-+	struct amdgpu_dm_connector *aconnector = link->priv;
-+
-+	if (!aconnector) {
-+		DRM_ERROR("Failed to found connector for link!");
-+		return false;
-+	}
-+
-+	return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
-+			address, (uint8_t *)data, size) > 0;
-+}
-+
-+bool dm_helpers_submit_i2c(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		struct i2c_command *cmd)
-+{
-+	struct amdgpu_dm_connector *aconnector = link->priv;
-+	struct i2c_msg *msgs;
-+	int i = 0;
-+	int num = cmd->number_of_payloads;
-+	bool result;
-+
-+	if (!aconnector) {
-+		DRM_ERROR("Failed to found connector for link!");
-+		return false;
-+	}
-+
-+	msgs = kzalloc(num * sizeof(struct i2c_msg), GFP_KERNEL);
-+
-+	if (!msgs)
-+		return false;
-+
-+	for (i = 0; i < num; i++) {
-+		msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
-+		msgs[i].addr = cmd->payloads[i].address;
-+		msgs[i].len = cmd->payloads[i].length;
-+		msgs[i].buf = cmd->payloads[i].data;
-+	}
-+
-+	result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
-+
-+	kfree(msgs);
-+
-+	return result;
-+}
-+
-+enum dc_edid_status dm_helpers_read_local_edid(
-+		struct dc_context *ctx,
-+		struct dc_link *link,
-+		struct dc_sink *sink)
-+{
-+	struct amdgpu_dm_connector *aconnector = link->priv;
-+	struct i2c_adapter *ddc;
-+	int retry = 3;
-+	enum dc_edid_status edid_status;
-+	struct edid *edid;
-+
-+	if (link->aux_mode)
-+		ddc = &aconnector->dm_dp_aux.aux.ddc;
-+	else
-+		ddc = &aconnector->i2c->base;
-+
-+	/* some dongles read edid incorrectly the first time,
-+	 * do check sum and retry to make sure read correct edid.
-+	 */
-+	do {
-+
-+		edid = drm_get_edid(&aconnector->base, ddc);
-+
-+		if (!edid)
-+			return EDID_NO_RESPONSE;
-+
-+		sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
-+		memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
-+
-+		/* We don't need the original edid anymore */
-+		kfree(edid);
-+
-+		edid_status = dm_helpers_parse_edid_caps(
-+						ctx,
-+						&sink->dc_edid,
-+						&sink->edid_caps);
-+
-+	} while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
-+
-+	if (edid_status != EDID_OK)
-+		DRM_ERROR("EDID err: %d, on connector: %s",
-+				edid_status,
-+				aconnector->base.name);
-+
-+	return edid_status;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c.0130~	2017-12-14 06:39:58.396903554 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c	2017-12-14 06:39:58.396903554 +0100
-@@ -0,0 +1,758 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include <drm/drmP.h>
-+
-+#include "dm_services_types.h"
-+#include "dc.h"
-+
-+#include "amdgpu.h"
-+#include "amdgpu_dm.h"
-+#include "amdgpu_dm_irq.h"
-+
-+/******************************************************************************
-+ * Private declarations.
-+ *****************************************************************************/
-+
-+struct handler_common_data {
-+	struct list_head list;
-+	interrupt_handler handler;
-+	void *handler_arg;
-+
-+	/* DM which this handler belongs to */
-+	struct amdgpu_display_manager *dm;
-+};
-+
-+struct amdgpu_dm_irq_handler_data {
-+	struct handler_common_data hcd;
-+	/* DAL irq source which registered for this interrupt. */
-+	enum dc_irq_source irq_source;
-+};
-+
-+struct amdgpu_dm_timer_handler_data {
-+	struct handler_common_data hcd;
-+	struct delayed_work d_work;
-+};
-+
-+#define DM_IRQ_TABLE_LOCK(adev, flags) \
-+	spin_lock_irqsave(&adev->dm.irq_handler_list_table_lock, flags)
-+
-+#define DM_IRQ_TABLE_UNLOCK(adev, flags) \
-+	spin_unlock_irqrestore(&adev->dm.irq_handler_list_table_lock, flags)
-+
-+/******************************************************************************
-+ * Private functions.
-+ *****************************************************************************/
-+
-+static void init_handler_common_data(struct handler_common_data *hcd,
-+				     void (*ih)(void *),
-+				     void *args,
-+				     struct amdgpu_display_manager *dm)
-+{
-+	hcd->handler = ih;
-+	hcd->handler_arg = args;
-+	hcd->dm = dm;
-+}
-+
-+/**
-+ * dm_irq_work_func - Handle an IRQ outside of the interrupt handler proper.
-+ *
-+ * @work: work struct
-+ */
-+static void dm_irq_work_func(struct work_struct *work)
-+{
-+	struct list_head *entry;
-+	struct irq_list_head *irq_list_head =
-+		container_of(work, struct irq_list_head, work);
-+	struct list_head *handler_list = &irq_list_head->head;
-+	struct amdgpu_dm_irq_handler_data *handler_data;
-+
-+	list_for_each(entry, handler_list) {
-+		handler_data =
-+			list_entry(
-+				entry,
-+				struct amdgpu_dm_irq_handler_data,
-+				hcd.list);
-+
-+		DRM_DEBUG_KMS("DM_IRQ: work_func: for dal_src=%d\n",
-+				handler_data->irq_source);
-+
-+		DRM_DEBUG_KMS("DM_IRQ: schedule_work: for dal_src=%d\n",
-+			handler_data->irq_source);
-+
-+		handler_data->hcd.handler(handler_data->hcd.handler_arg);
-+	}
-+
-+	/* Call a DAL subcomponent which registered for interrupt notification
-+	 * at INTERRUPT_LOW_IRQ_CONTEXT.
-+	 * (The most common use is HPD interrupt) */
-+}
-+
-+/**
-+ * Remove a handler and return a pointer to hander list from which the
-+ * handler was removed.
-+ */
-+static struct list_head *remove_irq_handler(struct amdgpu_device *adev,
-+					    void *ih,
-+					    const struct dc_interrupt_params *int_params)
-+{
-+	struct list_head *hnd_list;
-+	struct list_head *entry, *tmp;
-+	struct amdgpu_dm_irq_handler_data *handler;
-+	unsigned long irq_table_flags;
-+	bool handler_removed = false;
-+	enum dc_irq_source irq_source;
-+
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	irq_source = int_params->irq_source;
-+
-+	switch (int_params->int_context) {
-+	case INTERRUPT_HIGH_IRQ_CONTEXT:
-+		hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
-+		break;
-+	case INTERRUPT_LOW_IRQ_CONTEXT:
-+	default:
-+		hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head;
-+		break;
-+	}
-+
-+	list_for_each_safe(entry, tmp, hnd_list) {
-+
-+		handler = list_entry(entry, struct amdgpu_dm_irq_handler_data,
-+				hcd.list);
-+
-+		if (ih == handler) {
-+			/* Found our handler. Remove it from the list. */
-+			list_del(&handler->hcd.list);
-+			handler_removed = true;
-+			break;
-+		}
-+	}
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+	if (handler_removed == false) {
-+		/* Not necessarily an error - caller may not
-+		 * know the context. */
-+		return NULL;
-+	}
-+
-+	kfree(handler);
-+
-+	DRM_DEBUG_KMS(
-+	"DM_IRQ: removed irq handler: %p for: dal_src=%d, irq context=%d\n",
-+		ih, int_params->irq_source, int_params->int_context);
-+
-+	return hnd_list;
-+}
-+
-+/* If 'handler_in == NULL' then remove ALL handlers. */
-+static void remove_timer_handler(struct amdgpu_device *adev,
-+				 struct amdgpu_dm_timer_handler_data *handler_in)
-+{
-+	struct amdgpu_dm_timer_handler_data *handler_temp;
-+	struct list_head *handler_list;
-+	struct list_head *entry, *tmp;
-+	unsigned long irq_table_flags;
-+	bool handler_removed = false;
-+
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	handler_list = &adev->dm.timer_handler_list;
-+
-+	list_for_each_safe(entry, tmp, handler_list) {
-+		/* Note that list_for_each_safe() guarantees that
-+		 * handler_temp is NOT null. */
-+		handler_temp = list_entry(entry,
-+				struct amdgpu_dm_timer_handler_data, hcd.list);
-+
-+		if (handler_in == NULL || handler_in == handler_temp) {
-+			list_del(&handler_temp->hcd.list);
-+			DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+			DRM_DEBUG_KMS("DM_IRQ: removing timer handler: %p\n",
-+					handler_temp);
-+
-+			if (handler_in == NULL) {
-+				/* Since it is still in the queue, it must
-+				 * be cancelled. */
-+				cancel_delayed_work_sync(&handler_temp->d_work);
-+			}
-+
-+			kfree(handler_temp);
-+			handler_removed = true;
-+
-+			DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+		}
-+
-+		/* Remove ALL handlers. */
-+		if (handler_in == NULL)
-+			continue;
-+
-+		/* Remove a SPECIFIC handler.
-+		 * Found our handler - we can stop here. */
-+		if (handler_in == handler_temp)
-+			break;
-+	}
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+	if (handler_in != NULL && handler_removed == false)
-+		DRM_ERROR("DM_IRQ: handler: %p is not in the list!\n",
-+				handler_in);
-+}
-+
-+static bool
-+validate_irq_registration_params(struct dc_interrupt_params *int_params,
-+				 void (*ih)(void *))
-+{
-+	if (NULL == int_params || NULL == ih) {
-+		DRM_ERROR("DM_IRQ: invalid input!\n");
-+		return false;
-+	}
-+
-+	if (int_params->int_context >= INTERRUPT_CONTEXT_NUMBER) {
-+		DRM_ERROR("DM_IRQ: invalid context: %d!\n",
-+				int_params->int_context);
-+		return false;
-+	}
-+
-+	if (!DAL_VALID_IRQ_SRC_NUM(int_params->irq_source)) {
-+		DRM_ERROR("DM_IRQ: invalid irq_source: %d!\n",
-+				int_params->irq_source);
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+static bool validate_irq_unregistration_params(enum dc_irq_source irq_source,
-+					       irq_handler_idx handler_idx)
-+{
-+	if (DAL_INVALID_IRQ_HANDLER_IDX == handler_idx) {
-+		DRM_ERROR("DM_IRQ: invalid handler_idx==NULL!\n");
-+		return false;
-+	}
-+
-+	if (!DAL_VALID_IRQ_SRC_NUM(irq_source)) {
-+		DRM_ERROR("DM_IRQ: invalid irq_source:%d!\n", irq_source);
-+		return false;
-+	}
-+
-+	return true;
-+}
-+/******************************************************************************
-+ * Public functions.
-+ *
-+ * Note: caller is responsible for input validation.
-+ *****************************************************************************/
-+
-+void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
-+				       struct dc_interrupt_params *int_params,
-+				       void (*ih)(void *),
-+				       void *handler_args)
-+{
-+	struct list_head *hnd_list;
-+	struct amdgpu_dm_irq_handler_data *handler_data;
-+	unsigned long irq_table_flags;
-+	enum dc_irq_source irq_source;
-+
-+	if (false == validate_irq_registration_params(int_params, ih))
-+		return DAL_INVALID_IRQ_HANDLER_IDX;
-+
-+	handler_data = kzalloc(sizeof(*handler_data), GFP_KERNEL);
-+	if (!handler_data) {
-+		DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n");
-+		return DAL_INVALID_IRQ_HANDLER_IDX;
-+	}
-+
-+	memset(handler_data, 0, sizeof(*handler_data));
-+
-+	init_handler_common_data(&handler_data->hcd, ih, handler_args,
-+			&adev->dm);
-+
-+	irq_source = int_params->irq_source;
-+
-+	handler_data->irq_source = irq_source;
-+
-+	/* Lock the list, add the handler. */
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	switch (int_params->int_context) {
-+	case INTERRUPT_HIGH_IRQ_CONTEXT:
-+		hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
-+		break;
-+	case INTERRUPT_LOW_IRQ_CONTEXT:
-+	default:
-+		hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head;
-+		break;
-+	}
-+
-+	list_add_tail(&handler_data->hcd.list, hnd_list);
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+	/* This pointer will be stored by code which requested interrupt
-+	 * registration.
-+	 * The same pointer will be needed in order to unregister the
-+	 * interrupt. */
-+
-+	DRM_DEBUG_KMS(
-+		"DM_IRQ: added irq handler: %p for: dal_src=%d, irq context=%d\n",
-+		handler_data,
-+		irq_source,
-+		int_params->int_context);
-+
-+	return handler_data;
-+}
-+
-+void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
-+					enum dc_irq_source irq_source,
-+					void *ih)
-+{
-+	struct list_head *handler_list;
-+	struct dc_interrupt_params int_params;
-+	int i;
-+
-+	if (false == validate_irq_unregistration_params(irq_source, ih))
-+		return;
-+
-+	memset(&int_params, 0, sizeof(int_params));
-+
-+	int_params.irq_source = irq_source;
-+
-+	for (i = 0; i < INTERRUPT_CONTEXT_NUMBER; i++) {
-+
-+		int_params.int_context = i;
-+
-+		handler_list = remove_irq_handler(adev, ih, &int_params);
-+
-+		if (handler_list != NULL)
-+			break;
-+	}
-+
-+	if (handler_list == NULL) {
-+		/* If we got here, it means we searched all irq contexts
-+		 * for this irq source, but the handler was not found. */
-+		DRM_ERROR(
-+		"DM_IRQ: failed to find irq handler:%p for irq_source:%d!\n",
-+			ih, irq_source);
-+	}
-+}
-+
-+int amdgpu_dm_irq_init(struct amdgpu_device *adev)
-+{
-+	int src;
-+	struct irq_list_head *lh;
-+
-+	DRM_DEBUG_KMS("DM_IRQ\n");
-+
-+	spin_lock_init(&adev->dm.irq_handler_list_table_lock);
-+
-+	for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
-+		/* low context handler list init */
-+		lh = &adev->dm.irq_handler_list_low_tab[src];
-+		INIT_LIST_HEAD(&lh->head);
-+		INIT_WORK(&lh->work, dm_irq_work_func);
-+
-+		/* high context handler init */
-+		INIT_LIST_HEAD(&adev->dm.irq_handler_list_high_tab[src]);
-+	}
-+
-+	INIT_LIST_HEAD(&adev->dm.timer_handler_list);
-+
-+	/* allocate and initialize the workqueue for DM timer */
-+	adev->dm.timer_workqueue = create_singlethread_workqueue(
-+			"dm_timer_queue");
-+	if (adev->dm.timer_workqueue == NULL) {
-+		DRM_ERROR("DM_IRQ: unable to create timer queue!\n");
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+/* DM IRQ and timer resource release */
-+void amdgpu_dm_irq_fini(struct amdgpu_device *adev)
-+{
-+	int src;
-+	struct irq_list_head *lh;
-+	DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n");
-+
-+	for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
-+
-+		/* The handler was removed from the table,
-+		 * it means it is safe to flush all the 'work'
-+		 * (because no code can schedule a new one). */
-+		lh = &adev->dm.irq_handler_list_low_tab[src];
-+		flush_work(&lh->work);
-+	}
-+
-+	/* Cancel ALL timers and release handlers (if any). */
-+	remove_timer_handler(adev, NULL);
-+	/* Release the queue itself. */
-+	destroy_workqueue(adev->dm.timer_workqueue);
-+}
-+
-+int amdgpu_dm_irq_suspend(struct amdgpu_device *adev)
-+{
-+	int src;
-+	struct list_head *hnd_list_h;
-+	struct list_head *hnd_list_l;
-+	unsigned long irq_table_flags;
-+
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	DRM_DEBUG_KMS("DM_IRQ: suspend\n");
-+
-+	/**
-+	 * Disable HW interrupt  for HPD and HPDRX only since FLIP and VBLANK
-+	 * will be disabled from manage_dm_interrupts on disable CRTC.
-+	 */
-+	for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
-+		hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
-+		hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
-+		if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
-+			dc_interrupt_set(adev->dm.dc, src, false);
-+
-+		DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+		flush_work(&adev->dm.irq_handler_list_low_tab[src].work);
-+
-+		DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+	}
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+	return 0;
-+}
-+
-+int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)
-+{
-+	int src;
-+	struct list_head *hnd_list_h, *hnd_list_l;
-+	unsigned long irq_table_flags;
-+
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	DRM_DEBUG_KMS("DM_IRQ: early resume\n");
-+
-+	/* re-enable short pulse interrupts HW interrupt */
-+	for (src = DC_IRQ_SOURCE_HPD1RX; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
-+		hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
-+		hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
-+		if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
-+			dc_interrupt_set(adev->dm.dc, src, true);
-+	}
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+	return 0;
-+}
-+
-+int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)
-+{
-+	int src;
-+	struct list_head *hnd_list_h, *hnd_list_l;
-+	unsigned long irq_table_flags;
-+
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	DRM_DEBUG_KMS("DM_IRQ: resume\n");
-+
-+	/**
-+	 * Renable HW interrupt  for HPD and only since FLIP and VBLANK
-+	 * will be enabled from manage_dm_interrupts on enable CRTC.
-+	 */
-+	for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6; src++) {
-+		hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
-+		hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
-+		if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
-+			dc_interrupt_set(adev->dm.dc, src, true);
-+	}
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+	return 0;
-+}
-+
-+/**
-+ * amdgpu_dm_irq_schedule_work - schedule all work items registered for the
-+ * "irq_source".
-+ */
-+static void amdgpu_dm_irq_schedule_work(struct amdgpu_device *adev,
-+					enum dc_irq_source irq_source)
-+{
-+	unsigned long irq_table_flags;
-+	struct work_struct *work = NULL;
-+
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	if (!list_empty(&adev->dm.irq_handler_list_low_tab[irq_source].head))
-+		work = &adev->dm.irq_handler_list_low_tab[irq_source].work;
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+
-+	if (work) {
-+		if (!schedule_work(work))
-+			DRM_INFO("amdgpu_dm_irq_schedule_work FAILED src %d\n",
-+						irq_source);
-+	}
-+
-+}
-+
-+/** amdgpu_dm_irq_immediate_work
-+ *  Callback high irq work immediately, don't send to work queue
-+ */
-+static void amdgpu_dm_irq_immediate_work(struct amdgpu_device *adev,
-+					 enum dc_irq_source irq_source)
-+{
-+	struct amdgpu_dm_irq_handler_data *handler_data;
-+	struct list_head *entry;
-+	unsigned long irq_table_flags;
-+
-+	DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
-+
-+	list_for_each(
-+		entry,
-+		&adev->dm.irq_handler_list_high_tab[irq_source]) {
-+
-+		handler_data =
-+			list_entry(
-+				entry,
-+				struct amdgpu_dm_irq_handler_data,
-+				hcd.list);
-+
-+		/* Call a subcomponent which registered for immediate
-+		 * interrupt notification */
-+		handler_data->hcd.handler(handler_data->hcd.handler_arg);
-+	}
-+
-+	DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
-+}
-+
-+/*
-+ * amdgpu_dm_irq_handler
-+ *
-+ * Generic IRQ handler, calls all registered high irq work immediately, and
-+ * schedules work for low irq
-+ */
-+static int amdgpu_dm_irq_handler(struct amdgpu_device *adev,
-+				 struct amdgpu_irq_src *source,
-+				 struct amdgpu_iv_entry *entry)
-+{
-+
-+	enum dc_irq_source src =
-+		dc_interrupt_to_irq_source(
-+			adev->dm.dc,
-+			entry->src_id,
-+			entry->src_data[0]);
-+
-+	dc_interrupt_ack(adev->dm.dc, src);
-+
-+	/* Call high irq work immediately */
-+	amdgpu_dm_irq_immediate_work(adev, src);
-+	/*Schedule low_irq work */
-+	amdgpu_dm_irq_schedule_work(adev, src);
-+
-+	return 0;
-+}
-+
-+static enum dc_irq_source amdgpu_dm_hpd_to_dal_irq_source(unsigned type)
-+{
-+	switch (type) {
-+	case AMDGPU_HPD_1:
-+		return DC_IRQ_SOURCE_HPD1;
-+	case AMDGPU_HPD_2:
-+		return DC_IRQ_SOURCE_HPD2;
-+	case AMDGPU_HPD_3:
-+		return DC_IRQ_SOURCE_HPD3;
-+	case AMDGPU_HPD_4:
-+		return DC_IRQ_SOURCE_HPD4;
-+	case AMDGPU_HPD_5:
-+		return DC_IRQ_SOURCE_HPD5;
-+	case AMDGPU_HPD_6:
-+		return DC_IRQ_SOURCE_HPD6;
-+	default:
-+		return DC_IRQ_SOURCE_INVALID;
-+	}
-+}
-+
-+static int amdgpu_dm_set_hpd_irq_state(struct amdgpu_device *adev,
-+				       struct amdgpu_irq_src *source,
-+				       unsigned type,
-+				       enum amdgpu_interrupt_state state)
-+{
-+	enum dc_irq_source src = amdgpu_dm_hpd_to_dal_irq_source(type);
-+	bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
-+
-+	dc_interrupt_set(adev->dm.dc, src, st);
-+	return 0;
-+}
-+
-+static inline int dm_irq_state(struct amdgpu_device *adev,
-+			       struct amdgpu_irq_src *source,
-+			       unsigned crtc_id,
-+			       enum amdgpu_interrupt_state state,
-+			       const enum irq_type dal_irq_type,
-+			       const char *func)
-+{
-+	bool st;
-+	enum dc_irq_source irq_source;
-+
-+	struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
-+
-+	if (!acrtc) {
-+		DRM_ERROR(
-+			"%s: crtc is NULL at id :%d\n",
-+			func,
-+			crtc_id);
-+		return 0;
-+	}
-+
-+	irq_source = dal_irq_type + acrtc->otg_inst;
-+
-+	st = (state == AMDGPU_IRQ_STATE_ENABLE);
-+
-+	dc_interrupt_set(adev->dm.dc, irq_source, st);
-+	return 0;
-+}
-+
-+static int amdgpu_dm_set_pflip_irq_state(struct amdgpu_device *adev,
-+					 struct amdgpu_irq_src *source,
-+					 unsigned crtc_id,
-+					 enum amdgpu_interrupt_state state)
-+{
-+	return dm_irq_state(
-+		adev,
-+		source,
-+		crtc_id,
-+		state,
-+		IRQ_TYPE_PFLIP,
-+		__func__);
-+}
-+
-+static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev,
-+					struct amdgpu_irq_src *source,
-+					unsigned crtc_id,
-+					enum amdgpu_interrupt_state state)
-+{
-+	return dm_irq_state(
-+		adev,
-+		source,
-+		crtc_id,
-+		state,
-+		IRQ_TYPE_VBLANK,
-+		__func__);
-+}
-+
-+static const struct amdgpu_irq_src_funcs dm_crtc_irq_funcs = {
-+	.set = amdgpu_dm_set_crtc_irq_state,
-+	.process = amdgpu_dm_irq_handler,
-+};
-+
-+static const struct amdgpu_irq_src_funcs dm_pageflip_irq_funcs = {
-+	.set = amdgpu_dm_set_pflip_irq_state,
-+	.process = amdgpu_dm_irq_handler,
-+};
-+
-+static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = {
-+	.set = amdgpu_dm_set_hpd_irq_state,
-+	.process = amdgpu_dm_irq_handler,
-+};
-+
-+void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
-+{
-+	if (adev->mode_info.num_crtc > 0)
-+		adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
-+	else
-+		adev->crtc_irq.num_types = 0;
-+	adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
-+
-+	adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
-+	adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs;
-+
-+	adev->hpd_irq.num_types = adev->mode_info.num_hpd;
-+	adev->hpd_irq.funcs = &dm_hpd_irq_funcs;
-+}
-+
-+/*
-+ * amdgpu_dm_hpd_init - hpd setup callback.
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Setup the hpd pins used by the card (evergreen+).
-+ * Enable the pin, set the polarity, and enable the hpd interrupts.
-+ */
-+void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
-+{
-+	struct drm_device *dev = adev->ddev;
-+	struct drm_connector *connector;
-+
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+		struct amdgpu_dm_connector *amdgpu_dm_connector =
-+				to_amdgpu_dm_connector(connector);
-+
-+		const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
-+
-+		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
-+			dc_interrupt_set(adev->dm.dc,
-+					dc_link->irq_source_hpd,
-+					true);
-+		}
-+
-+		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
-+			dc_interrupt_set(adev->dm.dc,
-+					dc_link->irq_source_hpd_rx,
-+					true);
-+		}
-+	}
-+}
-+
-+/**
-+ * amdgpu_dm_hpd_fini - hpd tear down callback.
-+ *
-+ * @adev: amdgpu_device pointer
-+ *
-+ * Tear down the hpd pins used by the card (evergreen+).
-+ * Disable the hpd interrupts.
-+ */
-+void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)
-+{
-+	struct drm_device *dev = adev->ddev;
-+	struct drm_connector *connector;
-+
-+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-+		struct amdgpu_dm_connector *amdgpu_dm_connector =
-+				to_amdgpu_dm_connector(connector);
-+		const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
-+
-+		dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, false);
-+
-+		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
-+			dc_interrupt_set(adev->dm.dc,
-+					dc_link->irq_source_hpd_rx,
-+					false);
-+		}
-+	}
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h.0130~	2017-12-14 06:39:58.396903554 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h	2017-12-14 06:39:58.396903554 +0100
-@@ -0,0 +1,102 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef __AMDGPU_DM_IRQ_H__
-+#define __AMDGPU_DM_IRQ_H__
-+
-+#include "irq_types.h" /* DAL irq definitions */
-+
-+/*
-+ * Display Manager IRQ-related interfaces (for use by DAL).
-+ */
-+
-+/**
-+ * amdgpu_dm_irq_init - Initialize internal structures of 'amdgpu_dm_irq'.
-+ *
-+ * This function should be called exactly once - during DM initialization.
-+ *
-+ * Returns:
-+ *	0 - success
-+ *	non-zero - error
-+ */
-+int amdgpu_dm_irq_init(struct amdgpu_device *adev);
-+
-+/**
-+ * amdgpu_dm_irq_fini - deallocate internal structures of 'amdgpu_dm_irq'.
-+ *
-+ * This function should be called exactly once - during DM destruction.
-+ *
-+ */
-+void amdgpu_dm_irq_fini(struct amdgpu_device *adev);
-+
-+/**
-+ * amdgpu_dm_irq_register_interrupt - register irq handler for Display block.
-+ *
-+ * @adev: AMD DRM device
-+ * @int_params: parameters for the irq
-+ * @ih: pointer to the irq hander function
-+ * @handler_args: arguments which will be passed to ih
-+ *
-+ * Returns:
-+ * 	IRQ Handler Index on success.
-+ * 	NULL on failure.
-+ *
-+ * Cannot be called from an interrupt handler.
-+ */
-+void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
-+				       struct dc_interrupt_params *int_params,
-+				       void (*ih)(void *),
-+				       void *handler_args);
-+
-+/**
-+ * amdgpu_dm_irq_unregister_interrupt - unregister handler which was registered
-+ *	by amdgpu_dm_irq_register_interrupt().
-+ *
-+ * @adev: AMD DRM device.
-+ * @ih_index: irq handler index which was returned by
-+ *	amdgpu_dm_irq_register_interrupt
-+ */
-+void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
-+					enum dc_irq_source irq_source,
-+					void *ih_index);
-+
-+void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev);
-+
-+void amdgpu_dm_hpd_init(struct amdgpu_device *adev);
-+void amdgpu_dm_hpd_fini(struct amdgpu_device *adev);
-+
-+/**
-+ * amdgpu_dm_irq_suspend - disable ASIC interrupt during suspend.
-+ *
-+ */
-+int amdgpu_dm_irq_suspend(struct amdgpu_device *adev);
-+
-+/**
-+ * amdgpu_dm_irq_resume_early - enable HPDRX ASIC interrupts during resume.
-+ * amdgpu_dm_irq_resume - enable ASIC interrupt during resume.
-+ *
-+ */
-+int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev);
-+int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev);
-+
-+#endif /* __AMDGPU_DM_IRQ_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c.0130~	2017-12-14 06:39:58.397903555 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c	2017-12-14 06:39:58.397903555 +0100
-@@ -0,0 +1,446 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include <linux/version.h>
-+#include <drm/drm_atomic_helper.h>
-+#include "dm_services.h"
-+#include "amdgpu.h"
-+#include "amdgpu_dm.h"
-+#include "amdgpu_dm_mst_types.h"
-+
-+#include "dc.h"
-+#include "dm_helpers.h"
-+
-+#include "dc_link_ddc.h"
-+
-+/* #define TRACE_DPCD */
-+
-+#ifdef TRACE_DPCD
-+#define SIDE_BAND_MSG(address) (address >= DP_SIDEBAND_MSG_DOWN_REQ_BASE && address < DP_SINK_COUNT_ESI)
-+
-+static inline char *side_band_msg_type_to_str(uint32_t address)
-+{
-+	static char str[10] = {0};
-+
-+	if (address < DP_SIDEBAND_MSG_UP_REP_BASE)
-+		strcpy(str, "DOWN_REQ");
-+	else if (address < DP_SIDEBAND_MSG_DOWN_REP_BASE)
-+		strcpy(str, "UP_REP");
-+	else if (address < DP_SIDEBAND_MSG_UP_REQ_BASE)
-+		strcpy(str, "DOWN_REP");
-+	else
-+		strcpy(str, "UP_REQ");
-+
-+	return str;
-+}
-+
-+static void log_dpcd(uint8_t type,
-+		     uint32_t address,
-+		     uint8_t *data,
-+		     uint32_t size,
-+		     bool res)
-+{
-+	DRM_DEBUG_KMS("Op: %s, addr: %04x, SideBand Msg: %s, Op res: %s\n",
-+			(type == DP_AUX_NATIVE_READ) ||
-+			(type == DP_AUX_I2C_READ) ?
-+					"Read" : "Write",
-+			address,
-+			SIDE_BAND_MSG(address) ?
-+					side_band_msg_type_to_str(address) : "Nop",
-+			res ? "OK" : "Fail");
-+
-+	if (res) {
-+		print_hex_dump(KERN_INFO, "Body: ", DUMP_PREFIX_NONE, 16, 1, data, size, false);
-+	}
-+}
-+#endif
-+
-+static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
-+				  struct drm_dp_aux_msg *msg)
-+{
-+	enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ?
-+		I2C_MOT_TRUE : I2C_MOT_FALSE;
-+	enum ddc_result res;
-+
-+	switch (msg->request & ~DP_AUX_I2C_MOT) {
-+	case DP_AUX_NATIVE_READ:
-+		res = dal_ddc_service_read_dpcd_data(
-+				TO_DM_AUX(aux)->ddc_service,
-+				false,
-+				I2C_MOT_UNDEF,
-+				msg->address,
-+				msg->buffer,
-+				msg->size);
-+		break;
-+	case DP_AUX_NATIVE_WRITE:
-+		res = dal_ddc_service_write_dpcd_data(
-+				TO_DM_AUX(aux)->ddc_service,
-+				false,
-+				I2C_MOT_UNDEF,
-+				msg->address,
-+				msg->buffer,
-+				msg->size);
-+		break;
-+	case DP_AUX_I2C_READ:
-+		res = dal_ddc_service_read_dpcd_data(
-+				TO_DM_AUX(aux)->ddc_service,
-+				true,
-+				mot,
-+				msg->address,
-+				msg->buffer,
-+				msg->size);
-+		break;
-+	case DP_AUX_I2C_WRITE:
-+		res = dal_ddc_service_write_dpcd_data(
-+				TO_DM_AUX(aux)->ddc_service,
-+				true,
-+				mot,
-+				msg->address,
-+				msg->buffer,
-+				msg->size);
-+		break;
-+	default:
-+		return 0;
-+	}
-+
-+#ifdef TRACE_DPCD
-+	log_dpcd(msg->request,
-+		 msg->address,
-+		 msg->buffer,
-+		 msg->size,
-+		 r == DDC_RESULT_SUCESSFULL);
-+#endif
-+
-+	return msg->size;
-+}
-+
-+static enum drm_connector_status
-+dm_dp_mst_detect(struct drm_connector *connector, bool force)
-+{
-+	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
-+	struct amdgpu_dm_connector *master = aconnector->mst_port;
-+
-+	enum drm_connector_status status =
-+		drm_dp_mst_detect_port(
-+			connector,
-+			&master->mst_mgr,
-+			aconnector->port);
-+
-+	return status;
-+}
-+
-+static void
-+dm_dp_mst_connector_destroy(struct drm_connector *connector)
-+{
-+	struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
-+	struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder;
-+
-+	drm_encoder_cleanup(&amdgpu_encoder->base);
-+	kfree(amdgpu_encoder);
-+	drm_connector_cleanup(connector);
-+	kfree(amdgpu_dm_connector);
-+}
-+
-+static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
-+	.detect = dm_dp_mst_detect,
-+	.fill_modes = drm_helper_probe_single_connector_modes,
-+	.destroy = dm_dp_mst_connector_destroy,
-+	.reset = amdgpu_dm_connector_funcs_reset,
-+	.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
-+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-+	.atomic_set_property = amdgpu_dm_connector_atomic_set_property,
-+	.atomic_get_property = amdgpu_dm_connector_atomic_get_property
-+};
-+
-+static int dm_connector_update_modes(struct drm_connector *connector,
-+				struct edid *edid)
-+{
-+	int ret;
-+
-+	ret = drm_add_edid_modes(connector, edid);
-+	drm_edid_to_eld(connector, edid);
-+
-+	return ret;
-+}
-+
-+static int dm_dp_mst_get_modes(struct drm_connector *connector)
-+{
-+	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
-+	int ret = 0;
-+
-+	if (!aconnector)
-+		return dm_connector_update_modes(connector, NULL);
-+
-+	if (!aconnector->edid) {
-+		struct edid *edid;
-+		struct dc_sink *dc_sink;
-+		struct dc_sink_init_data init_params = {
-+				.link = aconnector->dc_link,
-+				.sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
-+		edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
-+
-+		if (!edid) {
-+			drm_mode_connector_update_edid_property(
-+				&aconnector->base,
-+				NULL);
-+			return ret;
-+		}
-+
-+		aconnector->edid = edid;
-+
-+		dc_sink = dc_link_add_remote_sink(
-+			aconnector->dc_link,
-+			(uint8_t *)edid,
-+			(edid->extensions + 1) * EDID_LENGTH,
-+			&init_params);
-+
-+		dc_sink->priv = aconnector;
-+		aconnector->dc_sink = dc_sink;
-+
-+		if (aconnector->dc_sink)
-+			amdgpu_dm_add_sink_to_freesync_module(
-+					connector, edid);
-+
-+		drm_mode_connector_update_edid_property(
-+						&aconnector->base, edid);
-+	}
-+
-+	ret = dm_connector_update_modes(connector, aconnector->edid);
-+
-+	return ret;
-+}
-+
-+static struct drm_encoder *dm_mst_best_encoder(struct drm_connector *connector)
-+{
-+	struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
-+
-+	return &amdgpu_dm_connector->mst_encoder->base;
-+}
-+
-+static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
-+	.get_modes = dm_dp_mst_get_modes,
-+	.mode_valid = amdgpu_dm_connector_mode_valid,
-+	.best_encoder = dm_mst_best_encoder,
-+};
-+
-+static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
-+{
-+	drm_encoder_cleanup(encoder);
-+	kfree(encoder);
-+}
-+
-+static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
-+	.destroy = amdgpu_dm_encoder_destroy,
-+};
-+
-+static struct amdgpu_encoder *
-+dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector)
-+{
-+	struct drm_device *dev = connector->base.dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+	struct amdgpu_encoder *amdgpu_encoder;
-+	struct drm_encoder *encoder;
-+	const struct drm_connector_helper_funcs *connector_funcs =
-+		connector->base.helper_private;
-+	struct drm_encoder *enc_master =
-+		connector_funcs->best_encoder(&connector->base);
-+
-+	DRM_DEBUG_KMS("enc master is %p\n", enc_master);
-+	amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL);
-+	if (!amdgpu_encoder)
-+		return NULL;
-+
-+	encoder = &amdgpu_encoder->base;
-+	encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
-+
-+	drm_encoder_init(
-+		dev,
-+		&amdgpu_encoder->base,
-+		&amdgpu_dm_encoder_funcs,
-+		DRM_MODE_ENCODER_DPMST,
-+		NULL);
-+
-+	drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
-+
-+	return amdgpu_encoder;
-+}
-+
-+static struct drm_connector *
-+dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
-+			struct drm_dp_mst_port *port,
-+			const char *pathprop)
-+{
-+	struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
-+	struct drm_device *dev = master->base.dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+	struct amdgpu_dm_connector *aconnector;
-+	struct drm_connector *connector;
-+	struct drm_connector_list_iter conn_iter;
-+
-+	drm_connector_list_iter_begin(dev, &conn_iter);
-+	drm_for_each_connector_iter(connector, &conn_iter) {
-+		aconnector = to_amdgpu_dm_connector(connector);
-+		if (aconnector->mst_port == master
-+				&& !aconnector->port) {
-+			DRM_INFO("DM_MST: reusing connector: %p [id: %d] [master: %p]\n",
-+						aconnector, connector->base.id, aconnector->mst_port);
-+
-+			aconnector->port = port;
-+			drm_mode_connector_set_path_property(connector, pathprop);
-+
-+			drm_connector_list_iter_end(&conn_iter);
-+			return &aconnector->base;
-+		}
-+	}
-+	drm_connector_list_iter_end(&conn_iter);
-+
-+	aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
-+	if (!aconnector)
-+		return NULL;
-+
-+	connector = &aconnector->base;
-+	aconnector->port = port;
-+	aconnector->mst_port = master;
-+
-+	if (drm_connector_init(
-+		dev,
-+		connector,
-+		&dm_dp_mst_connector_funcs,
-+		DRM_MODE_CONNECTOR_DisplayPort)) {
-+		kfree(aconnector);
-+		return NULL;
-+	}
-+	drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
-+
-+	amdgpu_dm_connector_init_helper(
-+		&adev->dm,
-+		aconnector,
-+		DRM_MODE_CONNECTOR_DisplayPort,
-+		master->dc_link,
-+		master->connector_id);
-+
-+	aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);
-+
-+	/*
-+	 * TODO: understand why this one is needed
-+	 */
-+	drm_object_attach_property(
-+		&connector->base,
-+		dev->mode_config.path_property,
-+		0);
-+	drm_object_attach_property(
-+		&connector->base,
-+		dev->mode_config.tile_property,
-+		0);
-+
-+	drm_mode_connector_set_path_property(connector, pathprop);
-+
-+	/*
-+	 * Initialize connector state before adding the connectror to drm and
-+	 * framebuffer lists
-+	 */
-+	amdgpu_dm_connector_funcs_reset(connector);
-+
-+	DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n",
-+			aconnector, connector->base.id, aconnector->mst_port);
-+
-+	DRM_DEBUG_KMS(":%d\n", connector->base.id);
-+
-+	return connector;
-+}
-+
-+static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
-+					struct drm_connector *connector)
-+{
-+	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
-+
-+	DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n",
-+				aconnector, connector->base.id, aconnector->mst_port);
-+
-+	aconnector->port = NULL;
-+	if (aconnector->dc_sink) {
-+		amdgpu_dm_remove_sink_from_freesync_module(connector);
-+		dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
-+		dc_sink_release(aconnector->dc_sink);
-+		aconnector->dc_sink = NULL;
-+	}
-+	if (aconnector->edid) {
-+		kfree(aconnector->edid);
-+		aconnector->edid = NULL;
-+	}
-+
-+	drm_mode_connector_update_edid_property(
-+			&aconnector->base,
-+			NULL);
-+}
-+
-+static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
-+{
-+	struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
-+	struct drm_device *dev = master->base.dev;
-+
-+	drm_kms_helper_hotplug_event(dev);
-+}
-+
-+static void dm_dp_mst_register_connector(struct drm_connector *connector)
-+{
-+	struct drm_device *dev = connector->dev;
-+	struct amdgpu_device *adev = dev->dev_private;
-+
-+	if (adev->mode_info.rfbdev)
-+		drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector);
-+	else
-+		DRM_ERROR("adev->mode_info.rfbdev is NULL\n");
-+
-+	drm_connector_register(connector);
-+
-+}
-+
-+static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
-+	.add_connector = dm_dp_add_mst_connector,
-+	.destroy_connector = dm_dp_destroy_mst_connector,
-+	.hotplug = dm_dp_mst_hotplug,
-+	.register_connector = dm_dp_mst_register_connector
-+};
-+
-+void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
-+				       struct amdgpu_dm_connector *aconnector)
-+{
-+	aconnector->dm_dp_aux.aux.name = "dmdc";
-+	aconnector->dm_dp_aux.aux.dev = dm->adev->dev;
-+	aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
-+	aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
-+
-+	drm_dp_aux_register(&aconnector->dm_dp_aux.aux);
-+	aconnector->mst_mgr.cbs = &dm_mst_cbs;
-+	drm_dp_mst_topology_mgr_init(
-+		&aconnector->mst_mgr,
-+		dm->adev->ddev,
-+		&aconnector->dm_dp_aux.aux,
-+		16,
-+		4,
-+		aconnector->connector_id);
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h.0130~	2017-12-14 06:39:58.397903555 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h	2017-12-14 06:39:58.397903555 +0100
-@@ -0,0 +1,35 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_AMDGPU_DM_MST_TYPES_H__
-+#define __DAL_AMDGPU_DM_MST_TYPES_H__
-+
-+struct amdgpu_display_manager;
-+struct amdgpu_dm_connector;
-+
-+void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
-+				       struct amdgpu_dm_connector *aconnector);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c.0130~	2017-12-14 06:39:58.397903555 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c	2017-12-14 06:39:58.397903555 +0100
-@@ -0,0 +1,384 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include <linux/string.h>
-+#include <linux/acpi.h>
-+
-+#include <drm/drmP.h>
-+#include <drm/drm_crtc_helper.h>
-+#include <drm/amdgpu_drm.h>
-+#include "dm_services.h"
-+#include "amdgpu.h"
-+#include "amdgpu_dm.h"
-+#include "amdgpu_dm_irq.h"
-+#include "amdgpu_pm.h"
-+
-+unsigned long long dm_get_timestamp(struct dc_context *ctx)
-+{
-+	/* TODO: return actual timestamp */
-+	return 0;
-+}
-+
-+bool dm_write_persistent_data(struct dc_context *ctx,
-+		const struct dc_sink *sink,
-+		const char *module_name,
-+		const char *key_name,
-+		void *params,
-+		unsigned int size,
-+		struct persistent_data_flag *flag)
-+{
-+	/*TODO implement*/
-+	return false;
-+}
-+
-+bool dm_read_persistent_data(struct dc_context *ctx,
-+				const struct dc_sink *sink,
-+				const char *module_name,
-+				const char *key_name,
-+				void *params,
-+				unsigned int size,
-+				struct persistent_data_flag *flag)
-+{
-+	/*TODO implement*/
-+	return false;
-+}
-+
-+/**** power component interfaces ****/
-+
-+bool dm_pp_pre_dce_clock_change(
-+		struct dc_context *ctx,
-+		struct dm_pp_gpu_clock_range *requested_state,
-+		struct dm_pp_gpu_clock_range *actual_state)
-+{
-+	/*TODO*/
-+	return false;
-+}
-+
-+bool dm_pp_apply_display_requirements(
-+		const struct dc_context *ctx,
-+		const struct dm_pp_display_configuration *pp_display_cfg)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+
-+	if (adev->pm.dpm_enabled) {
-+
-+		memset(&adev->pm.pm_display_cfg, 0,
-+				sizeof(adev->pm.pm_display_cfg));
-+
-+		adev->pm.pm_display_cfg.cpu_cc6_disable =
-+			pp_display_cfg->cpu_cc6_disable;
-+
-+		adev->pm.pm_display_cfg.cpu_pstate_disable =
-+			pp_display_cfg->cpu_pstate_disable;
-+
-+		adev->pm.pm_display_cfg.cpu_pstate_separation_time =
-+			pp_display_cfg->cpu_pstate_separation_time;
-+
-+		adev->pm.pm_display_cfg.nb_pstate_switch_disable =
-+			pp_display_cfg->nb_pstate_switch_disable;
-+
-+		adev->pm.pm_display_cfg.num_display =
-+				pp_display_cfg->display_count;
-+		adev->pm.pm_display_cfg.num_path_including_non_display =
-+				pp_display_cfg->display_count;
-+
-+		adev->pm.pm_display_cfg.min_core_set_clock =
-+				pp_display_cfg->min_engine_clock_khz/10;
-+		adev->pm.pm_display_cfg.min_core_set_clock_in_sr =
-+				pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
-+		adev->pm.pm_display_cfg.min_mem_set_clock =
-+				pp_display_cfg->min_memory_clock_khz/10;
-+
-+		adev->pm.pm_display_cfg.multi_monitor_in_sync =
-+				pp_display_cfg->all_displays_in_sync;
-+		adev->pm.pm_display_cfg.min_vblank_time =
-+				pp_display_cfg->avail_mclk_switch_time_us;
-+
-+		adev->pm.pm_display_cfg.display_clk =
-+				pp_display_cfg->disp_clk_khz/10;
-+
-+		adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency =
-+				pp_display_cfg->avail_mclk_switch_time_in_disp_active_us;
-+
-+		adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index;
-+		adev->pm.pm_display_cfg.line_time_in_us =
-+				pp_display_cfg->line_time_in_us;
-+
-+		adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh;
-+		adev->pm.pm_display_cfg.crossfire_display_index = -1;
-+		adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
-+
-+		/* TODO: complete implementation of
-+		 * pp_display_configuration_change().
-+		 * Follow example of:
-+		 * PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c
-+		 * PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */
-+		if (adev->powerplay.pp_funcs->display_configuration_change)
-+			adev->powerplay.pp_funcs->display_configuration_change(
-+				adev->powerplay.pp_handle,
-+				&adev->pm.pm_display_cfg);
-+
-+		/* TODO: replace by a separate call to 'apply display cfg'? */
-+		amdgpu_pm_compute_clocks(adev);
-+	}
-+
-+	return true;
-+}
-+
-+bool dc_service_get_system_clocks_range(
-+		const struct dc_context *ctx,
-+		struct dm_pp_gpu_clock_range *sys_clks)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+
-+	/* Default values, in case PPLib is not compiled-in. */
-+	sys_clks->mclk.max_khz = 800000;
-+	sys_clks->mclk.min_khz = 800000;
-+
-+	sys_clks->sclk.max_khz = 600000;
-+	sys_clks->sclk.min_khz = 300000;
-+
-+	if (adev->pm.dpm_enabled) {
-+		sys_clks->mclk.max_khz = amdgpu_dpm_get_mclk(adev, false);
-+		sys_clks->mclk.min_khz = amdgpu_dpm_get_mclk(adev, true);
-+
-+		sys_clks->sclk.max_khz = amdgpu_dpm_get_sclk(adev, false);
-+		sys_clks->sclk.min_khz = amdgpu_dpm_get_sclk(adev, true);
-+	}
-+
-+	return true;
-+}
-+
-+static void get_default_clock_levels(
-+		enum dm_pp_clock_type clk_type,
-+		struct dm_pp_clock_levels *clks)
-+{
-+	uint32_t disp_clks_in_khz[6] = {
-+			300000, 400000, 496560, 626090, 685720, 757900 };
-+	uint32_t sclks_in_khz[6] = {
-+			300000, 360000, 423530, 514290, 626090, 720000 };
-+	uint32_t mclks_in_khz[2] = { 333000, 800000 };
-+
-+	switch (clk_type) {
-+	case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
-+		clks->num_levels = 6;
-+		memmove(clks->clocks_in_khz, disp_clks_in_khz,
-+				sizeof(disp_clks_in_khz));
-+		break;
-+	case DM_PP_CLOCK_TYPE_ENGINE_CLK:
-+		clks->num_levels = 6;
-+		memmove(clks->clocks_in_khz, sclks_in_khz,
-+				sizeof(sclks_in_khz));
-+		break;
-+	case DM_PP_CLOCK_TYPE_MEMORY_CLK:
-+		clks->num_levels = 2;
-+		memmove(clks->clocks_in_khz, mclks_in_khz,
-+				sizeof(mclks_in_khz));
-+		break;
-+	default:
-+		clks->num_levels = 0;
-+		break;
-+	}
-+}
-+
-+static enum amd_pp_clock_type dc_to_pp_clock_type(
-+		enum dm_pp_clock_type dm_pp_clk_type)
-+{
-+	enum amd_pp_clock_type amd_pp_clk_type = 0;
-+
-+	switch (dm_pp_clk_type) {
-+	case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
-+		amd_pp_clk_type = amd_pp_disp_clock;
-+		break;
-+	case DM_PP_CLOCK_TYPE_ENGINE_CLK:
-+		amd_pp_clk_type = amd_pp_sys_clock;
-+		break;
-+	case DM_PP_CLOCK_TYPE_MEMORY_CLK:
-+		amd_pp_clk_type = amd_pp_mem_clock;
-+		break;
-+	default:
-+		DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
-+				dm_pp_clk_type);
-+		break;
-+	}
-+
-+	return amd_pp_clk_type;
-+}
-+
-+static void pp_to_dc_clock_levels(
-+		const struct amd_pp_clocks *pp_clks,
-+		struct dm_pp_clock_levels *dc_clks,
-+		enum dm_pp_clock_type dc_clk_type)
-+{
-+	uint32_t i;
-+
-+	if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
-+		DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
-+				DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
-+				pp_clks->count,
-+				DM_PP_MAX_CLOCK_LEVELS);
-+
-+		dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
-+	} else
-+		dc_clks->num_levels = pp_clks->count;
-+
-+	DRM_INFO("DM_PPLIB: values for %s clock\n",
-+			DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
-+
-+	for (i = 0; i < dc_clks->num_levels; i++) {
-+		DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
-+		/* translate 10kHz to kHz */
-+		dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10;
-+	}
-+}
-+
-+bool dm_pp_get_clock_levels_by_type(
-+		const struct dc_context *ctx,
-+		enum dm_pp_clock_type clk_type,
-+		struct dm_pp_clock_levels *dc_clks)
-+{
-+	struct amdgpu_device *adev = ctx->driver_context;
-+	void *pp_handle = adev->powerplay.pp_handle;
-+	struct amd_pp_clocks pp_clks = { 0 };
-+	struct amd_pp_simple_clock_info validation_clks = { 0 };
-+	uint32_t i;
-+
-+	if (adev->powerplay.pp_funcs->get_clock_by_type) {
-+		if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
-+			dc_to_pp_clock_type(clk_type), &pp_clks)) {
-+		/* Error in pplib. Provide default values. */
-+			get_default_clock_levels(clk_type, dc_clks);
-+			return true;
-+		}
-+	}
-+
-+	pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
-+
-+	if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
-+		if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks(
-+						pp_handle, &validation_clks)) {
-+			/* Error in pplib. Provide default values. */
-+			DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
-+			validation_clks.engine_max_clock = 72000;
-+			validation_clks.memory_max_clock = 80000;
-+			validation_clks.level = 0;
-+		}
-+	}
-+
-+	DRM_INFO("DM_PPLIB: Validation clocks:\n");
-+	DRM_INFO("DM_PPLIB:    engine_max_clock: %d\n",
-+			validation_clks.engine_max_clock);
-+	DRM_INFO("DM_PPLIB:    memory_max_clock: %d\n",
-+			validation_clks.memory_max_clock);
-+	DRM_INFO("DM_PPLIB:    level           : %d\n",
-+			validation_clks.level);
-+
-+	/* Translate 10 kHz to kHz. */
-+	validation_clks.engine_max_clock *= 10;
-+	validation_clks.memory_max_clock *= 10;
-+
-+	/* Determine the highest non-boosted level from the Validation Clocks */
-+	if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
-+		for (i = 0; i < dc_clks->num_levels; i++) {
-+			if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
-+				/* This clock is higher the validation clock.
-+				 * Than means the previous one is the highest
-+				 * non-boosted one. */
-+				DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
-+						dc_clks->num_levels, i);
-+				dc_clks->num_levels = i > 0 ? i : 1;
-+				break;
-+			}
-+		}
-+	} else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {
-+		for (i = 0; i < dc_clks->num_levels; i++) {
-+			if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
-+				DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
-+						dc_clks->num_levels, i);
-+				dc_clks->num_levels = i > 0 ? i : 1;
-+				break;
-+			}
-+		}
-+	}
-+
-+	return true;
-+}
-+
-+bool dm_pp_get_clock_levels_by_type_with_latency(
-+	const struct dc_context *ctx,
-+	enum dm_pp_clock_type clk_type,
-+	struct dm_pp_clock_levels_with_latency *clk_level_info)
-+{
-+	/* TODO: to be implemented */
-+	return false;
-+}
-+
-+bool dm_pp_get_clock_levels_by_type_with_voltage(
-+	const struct dc_context *ctx,
-+	enum dm_pp_clock_type clk_type,
-+	struct dm_pp_clock_levels_with_voltage *clk_level_info)
-+{
-+	/* TODO: to be implemented */
-+	return false;
-+}
-+
-+bool dm_pp_notify_wm_clock_changes(
-+	const struct dc_context *ctx,
-+	struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
-+{
-+	/* TODO: to be implemented */
-+	return false;
-+}
-+
-+bool dm_pp_apply_power_level_change_request(
-+	const struct dc_context *ctx,
-+	struct dm_pp_power_level_change_request *level_change_req)
-+{
-+	/* TODO: to be implemented */
-+	return false;
-+}
-+
-+bool dm_pp_apply_clock_for_voltage_request(
-+	const struct dc_context *ctx,
-+	struct dm_pp_clock_for_voltage_req *clock_for_voltage_req)
-+{
-+	/* TODO: to be implemented */
-+	return false;
-+}
-+
-+bool dm_pp_get_static_clocks(
-+	const struct dc_context *ctx,
-+	struct dm_pp_static_clock_info *static_clk_info)
-+{
-+	/* TODO: to be implemented */
-+	return false;
-+}
-+
-+void dm_pp_get_funcs_rv(
-+		struct dc_context *ctx,
-+		struct pp_smu_funcs_rv *funcs)
-+{}
-+
-+/**** end of power component interfaces ****/
---- linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile.0130~	2017-12-14 06:39:58.397903555 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile	2017-12-14 06:39:58.397903555 +0100
-@@ -0,0 +1,17 @@
-+#
-+# Makefile for the 'dm' sub-component of DAL.
-+# It provides the control and status of dm blocks.
-+
-+
-+
-+AMDGPUDM = amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o
-+
-+ifneq ($(CONFIG_DRM_AMD_DC),)
-+AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o
-+endif
-+
-+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc
-+
-+AMDGPU_DM = $(addprefix $(AMDDALPATH)/amdgpu_dm/,$(AMDGPUDM))
-+
-+AMD_DISPLAY_FILES += $(AMDGPU_DM)
---- linux-4.14/drivers/gpu/drm/amd/display/dc/basics/conversion.c.0130~	2017-12-14 06:39:58.397903555 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/basics/conversion.c	2017-12-14 06:39:58.397903555 +0100
-@@ -0,0 +1,104 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#define DIVIDER 10000
-+
-+/* S2D13 value in [-3.00...0.9999] */
-+#define S2D13_MIN (-3 * DIVIDER)
-+#define S2D13_MAX (3 * DIVIDER)
-+
-+uint16_t fixed_point_to_int_frac(
-+	struct fixed31_32 arg,
-+	uint8_t integer_bits,
-+	uint8_t fractional_bits)
-+{
-+	int32_t numerator;
-+	int32_t divisor = 1 << fractional_bits;
-+
-+	uint16_t result;
-+
-+	uint16_t d = (uint16_t)dal_fixed31_32_floor(
-+		dal_fixed31_32_abs(
-+			arg));
-+
-+	if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
-+		numerator = (uint16_t)dal_fixed31_32_floor(
-+			dal_fixed31_32_mul_int(
-+				arg,
-+				divisor));
-+	else {
-+		numerator = dal_fixed31_32_floor(
-+			dal_fixed31_32_sub(
-+				dal_fixed31_32_from_int(
-+					1LL << integer_bits),
-+				dal_fixed31_32_recip(
-+					dal_fixed31_32_from_int(
-+						divisor))));
-+	}
-+
-+	if (numerator >= 0)
-+		result = (uint16_t)numerator;
-+	else
-+		result = (uint16_t)(
-+		(1 << (integer_bits + fractional_bits + 1)) + numerator);
-+
-+	if ((result != 0) && dal_fixed31_32_lt(
-+		arg, dal_fixed31_32_zero))
-+		result |= 1 << (integer_bits + fractional_bits);
-+
-+	return result;
-+}
-+/**
-+* convert_float_matrix
-+* This converts a double into HW register spec defined format S2D13.
-+* @param :
-+* @return None
-+*/
-+void convert_float_matrix(
-+	uint16_t *matrix,
-+	struct fixed31_32 *flt,
-+	uint32_t buffer_size)
-+{
-+	const struct fixed31_32 min_2_13 =
-+		dal_fixed31_32_from_fraction(S2D13_MIN, DIVIDER);
-+	const struct fixed31_32 max_2_13 =
-+		dal_fixed31_32_from_fraction(S2D13_MAX, DIVIDER);
-+	uint32_t i;
-+
-+	for (i = 0; i < buffer_size; ++i) {
-+		uint32_t reg_value =
-+				fixed_point_to_int_frac(
-+					dal_fixed31_32_clamp(
-+						flt[i],
-+						min_2_13,
-+						max_2_13),
-+						2,
-+						13);
-+
-+		matrix[i] = (uint16_t)reg_value;
-+	}
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/basics/conversion.h.0130~	2017-12-14 06:39:58.397903555 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/basics/conversion.h	2017-12-14 06:39:58.397903555 +0100
-@@ -0,0 +1,46 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_CONVERSION_H__
-+#define __DAL_CONVERSION_H__
-+
-+#include "include/fixed31_32.h"
-+
-+uint16_t fixed_point_to_int_frac(
-+	struct fixed31_32 arg,
-+	uint8_t integer_bits,
-+	uint8_t fractional_bits);
-+
-+void convert_float_matrix(
-+	uint16_t *matrix,
-+	struct fixed31_32 *flt,
-+	uint32_t buffer_size);
-+
-+static inline unsigned int log_2(unsigned int num)
-+{
-+	return ilog2(num);
-+}
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c.0130~	2017-12-14 06:39:58.397903555 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c	2017-12-14 06:39:58.397903555 +0100
-@@ -0,0 +1,567 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "include/fixed31_32.h"
-+
-+static inline uint64_t abs_i64(
-+	int64_t arg)
-+{
-+	if (arg > 0)
-+		return (uint64_t)arg;
-+	else
-+		return (uint64_t)(-arg);
-+}
-+
-+/*
-+ * @brief
-+ * result = dividend / divisor
-+ * *remainder = dividend % divisor
-+ */
-+static inline uint64_t complete_integer_division_u64(
-+	uint64_t dividend,
-+	uint64_t divisor,
-+	uint64_t *remainder)
-+{
-+	uint64_t result;
-+
-+	ASSERT(divisor);
-+
-+	result = div64_u64_rem(dividend, divisor, remainder);
-+
-+	return result;
-+}
-+
-+
-+#define FRACTIONAL_PART_MASK \
-+	((1ULL << FIXED31_32_BITS_PER_FRACTIONAL_PART) - 1)
-+
-+#define GET_INTEGER_PART(x) \
-+	((x) >> FIXED31_32_BITS_PER_FRACTIONAL_PART)
-+
-+#define GET_FRACTIONAL_PART(x) \
-+	(FRACTIONAL_PART_MASK & (x))
-+
-+struct fixed31_32 dal_fixed31_32_from_fraction(
-+	int64_t numerator,
-+	int64_t denominator)
-+{
-+	struct fixed31_32 res;
-+
-+	bool arg1_negative = numerator < 0;
-+	bool arg2_negative = denominator < 0;
-+
-+	uint64_t arg1_value = arg1_negative ? -numerator : numerator;
-+	uint64_t arg2_value = arg2_negative ? -denominator : denominator;
-+
-+	uint64_t remainder;
-+
-+	/* determine integer part */
-+
-+	uint64_t res_value = complete_integer_division_u64(
-+		arg1_value, arg2_value, &remainder);
-+
-+	ASSERT(res_value <= LONG_MAX);
-+
-+	/* determine fractional part */
-+	{
-+		uint32_t i = FIXED31_32_BITS_PER_FRACTIONAL_PART;
-+
-+		do {
-+			remainder <<= 1;
-+
-+			res_value <<= 1;
-+
-+			if (remainder >= arg2_value) {
-+				res_value |= 1;
-+				remainder -= arg2_value;
-+			}
-+		} while (--i != 0);
-+	}
-+
-+	/* round up LSB */
-+	{
-+		uint64_t summand = (remainder << 1) >= arg2_value;
-+
-+		ASSERT(res_value <= LLONG_MAX - summand);
-+
-+		res_value += summand;
-+	}
-+
-+	res.value = (int64_t)res_value;
-+
-+	if (arg1_negative ^ arg2_negative)
-+		res.value = -res.value;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_from_int_nonconst(
-+	int64_t arg)
-+{
-+	struct fixed31_32 res;
-+
-+	ASSERT((LONG_MIN <= arg) && (arg <= LONG_MAX));
-+
-+	res.value = arg << FIXED31_32_BITS_PER_FRACTIONAL_PART;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_shl(
-+	struct fixed31_32 arg,
-+	uint8_t shift)
-+{
-+	struct fixed31_32 res;
-+
-+	ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) ||
-+		((arg.value < 0) && (arg.value >= LLONG_MIN >> shift)));
-+
-+	res.value = arg.value << shift;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_add(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2)
-+{
-+	struct fixed31_32 res;
-+
-+	ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) ||
-+		((arg1.value < 0) && (LLONG_MIN - arg1.value <= arg2.value)));
-+
-+	res.value = arg1.value + arg2.value;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_sub(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2)
-+{
-+	struct fixed31_32 res;
-+
-+	ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) ||
-+		((arg2.value < 0) && (LLONG_MAX + arg2.value >= arg1.value)));
-+
-+	res.value = arg1.value - arg2.value;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_mul(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2)
-+{
-+	struct fixed31_32 res;
-+
-+	bool arg1_negative = arg1.value < 0;
-+	bool arg2_negative = arg2.value < 0;
-+
-+	uint64_t arg1_value = arg1_negative ? -arg1.value : arg1.value;
-+	uint64_t arg2_value = arg2_negative ? -arg2.value : arg2.value;
-+
-+	uint64_t arg1_int = GET_INTEGER_PART(arg1_value);
-+	uint64_t arg2_int = GET_INTEGER_PART(arg2_value);
-+
-+	uint64_t arg1_fra = GET_FRACTIONAL_PART(arg1_value);
-+	uint64_t arg2_fra = GET_FRACTIONAL_PART(arg2_value);
-+
-+	uint64_t tmp;
-+
-+	res.value = arg1_int * arg2_int;
-+
-+	ASSERT(res.value <= LONG_MAX);
-+
-+	res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART;
-+
-+	tmp = arg1_int * arg2_fra;
-+
-+	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+	res.value += tmp;
-+
-+	tmp = arg2_int * arg1_fra;
-+
-+	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+	res.value += tmp;
-+
-+	tmp = arg1_fra * arg2_fra;
-+
-+	tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
-+		(tmp >= (uint64_t)dal_fixed31_32_half.value);
-+
-+	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+	res.value += tmp;
-+
-+	if (arg1_negative ^ arg2_negative)
-+		res.value = -res.value;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_sqr(
-+	struct fixed31_32 arg)
-+{
-+	struct fixed31_32 res;
-+
-+	uint64_t arg_value = abs_i64(arg.value);
-+
-+	uint64_t arg_int = GET_INTEGER_PART(arg_value);
-+
-+	uint64_t arg_fra = GET_FRACTIONAL_PART(arg_value);
-+
-+	uint64_t tmp;
-+
-+	res.value = arg_int * arg_int;
-+
-+	ASSERT(res.value <= LONG_MAX);
-+
-+	res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART;
-+
-+	tmp = arg_int * arg_fra;
-+
-+	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+	res.value += tmp;
-+
-+	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+	res.value += tmp;
-+
-+	tmp = arg_fra * arg_fra;
-+
-+	tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
-+		(tmp >= (uint64_t)dal_fixed31_32_half.value);
-+
-+	ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
-+
-+	res.value += tmp;
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_recip(
-+	struct fixed31_32 arg)
-+{
-+	/*
-+	 * @note
-+	 * Good idea to use Newton's method
-+	 */
-+
-+	ASSERT(arg.value);
-+
-+	return dal_fixed31_32_from_fraction(
-+		dal_fixed31_32_one.value,
-+		arg.value);
-+}
-+
-+struct fixed31_32 dal_fixed31_32_sinc(
-+	struct fixed31_32 arg)
-+{
-+	struct fixed31_32 square;
-+
-+	struct fixed31_32 res = dal_fixed31_32_one;
-+
-+	int32_t n = 27;
-+
-+	struct fixed31_32 arg_norm = arg;
-+
-+	if (dal_fixed31_32_le(
-+		dal_fixed31_32_two_pi,
-+		dal_fixed31_32_abs(arg))) {
-+		arg_norm = dal_fixed31_32_sub(
-+			arg_norm,
-+			dal_fixed31_32_mul_int(
-+				dal_fixed31_32_two_pi,
-+				(int32_t)div64_s64(
-+					arg_norm.value,
-+					dal_fixed31_32_two_pi.value)));
-+	}
-+
-+	square = dal_fixed31_32_sqr(arg_norm);
-+
-+	do {
-+		res = dal_fixed31_32_sub(
-+			dal_fixed31_32_one,
-+			dal_fixed31_32_div_int(
-+				dal_fixed31_32_mul(
-+					square,
-+					res),
-+				n * (n - 1)));
-+
-+		n -= 2;
-+	} while (n > 2);
-+
-+	if (arg.value != arg_norm.value)
-+		res = dal_fixed31_32_div(
-+			dal_fixed31_32_mul(res, arg_norm),
-+			arg);
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_sin(
-+	struct fixed31_32 arg)
-+{
-+	return dal_fixed31_32_mul(
-+		arg,
-+		dal_fixed31_32_sinc(arg));
-+}
-+
-+struct fixed31_32 dal_fixed31_32_cos(
-+	struct fixed31_32 arg)
-+{
-+	/* TODO implement argument normalization */
-+
-+	const struct fixed31_32 square = dal_fixed31_32_sqr(arg);
-+
-+	struct fixed31_32 res = dal_fixed31_32_one;
-+
-+	int32_t n = 26;
-+
-+	do {
-+		res = dal_fixed31_32_sub(
-+			dal_fixed31_32_one,
-+			dal_fixed31_32_div_int(
-+				dal_fixed31_32_mul(
-+					square,
-+					res),
-+				n * (n - 1)));
-+
-+		n -= 2;
-+	} while (n != 0);
-+
-+	return res;
-+}
-+
-+/*
-+ * @brief
-+ * result = exp(arg),
-+ * where abs(arg) < 1
-+ *
-+ * Calculated as Taylor series.
-+ */
-+static struct fixed31_32 fixed31_32_exp_from_taylor_series(
-+	struct fixed31_32 arg)
-+{
-+	uint32_t n = 9;
-+
-+	struct fixed31_32 res = dal_fixed31_32_from_fraction(
-+		n + 2,
-+		n + 1);
-+	/* TODO find correct res */
-+
-+	ASSERT(dal_fixed31_32_lt(arg, dal_fixed31_32_one));
-+
-+	do
-+		res = dal_fixed31_32_add(
-+			dal_fixed31_32_one,
-+			dal_fixed31_32_div_int(
-+				dal_fixed31_32_mul(
-+					arg,
-+					res),
-+				n));
-+	while (--n != 1);
-+
-+	return dal_fixed31_32_add(
-+		dal_fixed31_32_one,
-+		dal_fixed31_32_mul(
-+			arg,
-+			res));
-+}
-+
-+struct fixed31_32 dal_fixed31_32_exp(
-+	struct fixed31_32 arg)
-+{
-+	/*
-+	 * @brief
-+	 * Main equation is:
-+	 * exp(x) = exp(r + m * ln(2)) = (1 << m) * exp(r),
-+	 * where m = round(x / ln(2)), r = x - m * ln(2)
-+	 */
-+
-+	if (dal_fixed31_32_le(
-+		dal_fixed31_32_ln2_div_2,
-+		dal_fixed31_32_abs(arg))) {
-+		int32_t m = dal_fixed31_32_round(
-+			dal_fixed31_32_div(
-+				arg,
-+				dal_fixed31_32_ln2));
-+
-+		struct fixed31_32 r = dal_fixed31_32_sub(
-+			arg,
-+			dal_fixed31_32_mul_int(
-+				dal_fixed31_32_ln2,
-+				m));
-+
-+		ASSERT(m != 0);
-+
-+		ASSERT(dal_fixed31_32_lt(
-+			dal_fixed31_32_abs(r),
-+			dal_fixed31_32_one));
-+
-+		if (m > 0)
-+			return dal_fixed31_32_shl(
-+				fixed31_32_exp_from_taylor_series(r),
-+				(uint8_t)m);
-+		else
-+			return dal_fixed31_32_div_int(
-+				fixed31_32_exp_from_taylor_series(r),
-+				1LL << -m);
-+	} else if (arg.value != 0)
-+		return fixed31_32_exp_from_taylor_series(arg);
-+	else
-+		return dal_fixed31_32_one;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_log(
-+	struct fixed31_32 arg)
-+{
-+	struct fixed31_32 res = dal_fixed31_32_neg(dal_fixed31_32_one);
-+	/* TODO improve 1st estimation */
-+
-+	struct fixed31_32 error;
-+
-+	ASSERT(arg.value > 0);
-+	/* TODO if arg is negative, return NaN */
-+	/* TODO if arg is zero, return -INF */
-+
-+	do {
-+		struct fixed31_32 res1 = dal_fixed31_32_add(
-+			dal_fixed31_32_sub(
-+				res,
-+				dal_fixed31_32_one),
-+			dal_fixed31_32_div(
-+				arg,
-+				dal_fixed31_32_exp(res)));
-+
-+		error = dal_fixed31_32_sub(
-+			res,
-+			res1);
-+
-+		res = res1;
-+		/* TODO determine max_allowed_error based on quality of exp() */
-+	} while (abs_i64(error.value) > 100ULL);
-+
-+	return res;
-+}
-+
-+struct fixed31_32 dal_fixed31_32_pow(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2)
-+{
-+	return dal_fixed31_32_exp(
-+		dal_fixed31_32_mul(
-+			dal_fixed31_32_log(arg1),
-+			arg2));
-+}
-+
-+int32_t dal_fixed31_32_floor(
-+	struct fixed31_32 arg)
-+{
-+	uint64_t arg_value = abs_i64(arg.value);
-+
-+	if (arg.value >= 0)
-+		return (int32_t)GET_INTEGER_PART(arg_value);
-+	else
-+		return -(int32_t)GET_INTEGER_PART(arg_value);
-+}
-+
-+int32_t dal_fixed31_32_round(
-+	struct fixed31_32 arg)
-+{
-+	uint64_t arg_value = abs_i64(arg.value);
-+
-+	const int64_t summand = dal_fixed31_32_half.value;
-+
-+	ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);
-+
-+	arg_value += summand;
-+
-+	if (arg.value >= 0)
-+		return (int32_t)GET_INTEGER_PART(arg_value);
-+	else
-+		return -(int32_t)GET_INTEGER_PART(arg_value);
-+}
-+
-+int32_t dal_fixed31_32_ceil(
-+	struct fixed31_32 arg)
-+{
-+	uint64_t arg_value = abs_i64(arg.value);
-+
-+	const int64_t summand = dal_fixed31_32_one.value -
-+		dal_fixed31_32_epsilon.value;
-+
-+	ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);
-+
-+	arg_value += summand;
-+
-+	if (arg.value >= 0)
-+		return (int32_t)GET_INTEGER_PART(arg_value);
-+	else
-+		return -(int32_t)GET_INTEGER_PART(arg_value);
-+}
-+
-+/* this function is a generic helper to translate fixed point value to
-+ * specified integer format that will consist of integer_bits integer part and
-+ * fractional_bits fractional part. For example it is used in
-+ * dal_fixed31_32_u2d19 to receive 2 bits integer part and 19 bits fractional
-+ * part in 32 bits. It is used in hw programming (scaler)
-+ */
-+
-+static inline uint32_t ux_dy(
-+	int64_t value,
-+	uint32_t integer_bits,
-+	uint32_t fractional_bits)
-+{
-+	/* 1. create mask of integer part */
-+	uint32_t result = (1 << integer_bits) - 1;
-+	/* 2. mask out fractional part */
-+	uint32_t fractional_part = FRACTIONAL_PART_MASK & value;
-+	/* 3. shrink fixed point integer part to be of integer_bits width*/
-+	result &= GET_INTEGER_PART(value);
-+	/* 4. make space for fractional part to be filled in after integer */
-+	result <<= fractional_bits;
-+	/* 5. shrink fixed point fractional part to of fractional_bits width*/
-+	fractional_part >>= FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits;
-+	/* 6. merge the result */
-+	return result | fractional_part;
-+}
-+
-+uint32_t dal_fixed31_32_u2d19(
-+	struct fixed31_32 arg)
-+{
-+	return ux_dy(arg.value, 2, 19);
-+}
-+
-+uint32_t dal_fixed31_32_u0d19(
-+	struct fixed31_32 arg)
-+{
-+	return ux_dy(arg.value, 0, 19);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/basics/fixpt32_32.c.0130~	2017-12-14 06:39:58.397903555 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/basics/fixpt32_32.c	2017-12-14 06:39:58.397903555 +0100
-@@ -0,0 +1,161 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "include/fixed32_32.h"
-+
-+static uint64_t u64_div(uint64_t n, uint64_t d)
-+{
-+	uint32_t i = 0;
-+	uint64_t r;
-+	uint64_t q = div64_u64_rem(n, d, &r);
-+
-+	for (i = 0; i < 32; ++i) {
-+		uint64_t sbit = q & (1ULL<<63);
-+
-+		r <<= 1;
-+		r |= sbit ? 1 : 0;
-+		q <<= 1;
-+		if (r >= d) {
-+			r -= d;
-+			q |= 1;
-+		}
-+	}
-+
-+	if (2*r >= d)
-+		q += 1;
-+	return q;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_from_fraction(uint32_t n, uint32_t d)
-+{
-+	struct fixed32_32 fx;
-+
-+	fx.value = u64_div((uint64_t)n << 32, (uint64_t)d << 32);
-+	return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_add(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs)
-+{
-+	struct fixed32_32 fx = {lhs.value + rhs.value};
-+
-+	ASSERT(fx.value >= rhs.value);
-+	return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_add_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+	struct fixed32_32 fx = {lhs.value + ((uint64_t)rhs << 32)};
-+
-+	ASSERT(fx.value >= (uint64_t)rhs << 32);
-+	return fx;
-+
-+}
-+struct fixed32_32 dal_fixed32_32_sub(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs)
-+{
-+	struct fixed32_32 fx;
-+
-+	ASSERT(lhs.value >= rhs.value);
-+	fx.value = lhs.value - rhs.value;
-+	return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_sub_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+	struct fixed32_32 fx;
-+
-+	ASSERT(lhs.value >= ((uint64_t)rhs<<32));
-+	fx.value = lhs.value - ((uint64_t)rhs<<32);
-+	return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_mul(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs)
-+{
-+	struct fixed32_32 fx;
-+	uint64_t lhs_int = lhs.value>>32;
-+	uint64_t lhs_frac = (uint32_t)lhs.value;
-+	uint64_t rhs_int = rhs.value>>32;
-+	uint64_t rhs_frac = (uint32_t)rhs.value;
-+	uint64_t ahbh = lhs_int * rhs_int;
-+	uint64_t ahbl = lhs_int * rhs_frac;
-+	uint64_t albh = lhs_frac * rhs_int;
-+	uint64_t albl = lhs_frac * rhs_frac;
-+
-+	ASSERT((ahbh>>32) == 0);
-+
-+	fx.value = (ahbh<<32) + ahbl + albh + (albl>>32);
-+	return fx;
-+
-+}
-+
-+struct fixed32_32 dal_fixed32_32_mul_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+	struct fixed32_32 fx;
-+	uint64_t lhsi = (lhs.value>>32) * (uint64_t)rhs;
-+	uint64_t lhsf;
-+
-+	ASSERT((lhsi>>32) == 0);
-+	lhsf = ((uint32_t)lhs.value) * (uint64_t)rhs;
-+	ASSERT((lhsi<<32) + lhsf >= lhsf);
-+	fx.value = (lhsi<<32) + lhsf;
-+	return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_div(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs)
-+{
-+	struct fixed32_32 fx;
-+
-+	fx.value = u64_div(lhs.value, rhs.value);
-+	return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_div_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+	struct fixed32_32 fx;
-+
-+	fx.value = u64_div(lhs.value, (uint64_t)rhs << 32);
-+	return fx;
-+}
-+
-+uint32_t dal_fixed32_32_ceil(struct fixed32_32 v)
-+{
-+	ASSERT((uint32_t)v.value ? (v.value >> 32) + 1 >= 1 : true);
-+	return (v.value>>32) + ((uint32_t)v.value ? 1 : 0);
-+}
-+
-+uint32_t dal_fixed32_32_round(struct fixed32_32 v)
-+{
-+	ASSERT(v.value + (1ULL<<31) >= (1ULL<<31));
-+	return (v.value + (1ULL<<31))>>32;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c.0130~	2017-12-14 06:39:58.397903555 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c	2017-12-14 06:39:58.397903555 +0100
-@@ -0,0 +1,75 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "include/grph_object_id.h"
-+
-+static bool dal_graphics_object_id_is_valid(struct graphics_object_id id)
-+{
-+	bool rc = true;
-+
-+	switch (id.type) {
-+	case OBJECT_TYPE_UNKNOWN:
-+		rc = false;
-+		break;
-+	case OBJECT_TYPE_GPU:
-+	case OBJECT_TYPE_ENGINE:
-+		/* do NOT check for id.id == 0 */
-+		if (id.enum_id == ENUM_ID_UNKNOWN)
-+			rc = false;
-+		break;
-+	default:
-+		if (id.id == 0 || id.enum_id == ENUM_ID_UNKNOWN)
-+			rc = false;
-+		break;
-+	}
-+
-+	return rc;
-+}
-+
-+bool dal_graphics_object_id_is_equal(
-+	struct graphics_object_id id1,
-+	struct graphics_object_id id2)
-+{
-+	if (false == dal_graphics_object_id_is_valid(id1)) {
-+		dm_output_to_console(
-+		"%s: Warning: comparing invalid object 'id1'!\n", __func__);
-+		return false;
-+	}
-+
-+	if (false == dal_graphics_object_id_is_valid(id2)) {
-+		dm_output_to_console(
-+		"%s: Warning: comparing invalid object 'id2'!\n", __func__);
-+		return false;
-+	}
-+
-+	if (id1.id == id2.id && id1.enum_id == id2.enum_id
-+		&& id1.type == id2.type)
-+		return true;
-+
-+	return false;
-+}
-+
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/basics/logger.c.0130~	2017-12-14 06:39:58.397903555 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/basics/logger.c	2017-12-14 06:39:58.397903555 +0100
-@@ -0,0 +1,396 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dm_services.h"
-+#include "include/logger_interface.h"
-+#include "logger.h"
-+
-+
-+#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
-+
-+static const struct dc_log_type_info log_type_info_tbl[] = {
-+		{LOG_ERROR,                 "Error"},
-+		{LOG_WARNING,               "Warning"},
-+		{LOG_DEBUG,		    "Debug"},
-+		{LOG_DC,                    "DC_Interface"},
-+		{LOG_SURFACE,               "Surface"},
-+		{LOG_HW_HOTPLUG,            "HW_Hotplug"},
-+		{LOG_HW_LINK_TRAINING,      "HW_LKTN"},
-+		{LOG_HW_SET_MODE,           "HW_Mode"},
-+		{LOG_HW_RESUME_S3,          "HW_Resume"},
-+		{LOG_HW_AUDIO,              "HW_Audio"},
-+		{LOG_HW_HPD_IRQ,            "HW_HPDIRQ"},
-+		{LOG_MST,                   "MST"},
-+		{LOG_SCALER,                "Scaler"},
-+		{LOG_BIOS,                  "BIOS"},
-+		{LOG_BANDWIDTH_CALCS,       "BWCalcs"},
-+		{LOG_BANDWIDTH_VALIDATION,  "BWValidation"},
-+		{LOG_I2C_AUX,               "I2C_AUX"},
-+		{LOG_SYNC,                  "Sync"},
-+		{LOG_BACKLIGHT,             "Backlight"},
-+		{LOG_FEATURE_OVERRIDE,      "Override"},
-+		{LOG_DETECTION_EDID_PARSER, "Edid"},
-+		{LOG_DETECTION_DP_CAPS,     "DP_Caps"},
-+		{LOG_RESOURCE,              "Resource"},
-+		{LOG_DML,                   "DML"},
-+		{LOG_EVENT_MODE_SET,        "Mode"},
-+		{LOG_EVENT_DETECTION,       "Detect"},
-+		{LOG_EVENT_LINK_TRAINING,   "LKTN"},
-+		{LOG_EVENT_LINK_LOSS,       "LinkLoss"},
-+		{LOG_EVENT_UNDERFLOW,       "Underflow"},
-+		{LOG_IF_TRACE,              "InterfaceTrace"},
-+		{LOG_DTN,                   "DTN"}
-+};
-+
-+
-+/* ----------- Object init and destruction ----------- */
-+static bool construct(struct dc_context *ctx, struct dal_logger *logger,
-+		      uint32_t log_mask)
-+{
-+	/* malloc buffer and init offsets */
-+	logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE;
-+	logger->log_buffer = kcalloc(logger->log_buffer_size, sizeof(char),
-+				     GFP_KERNEL);
-+	if (!logger->log_buffer)
-+		return false;
-+
-+	/* Initialize both offsets to start of buffer (empty) */
-+	logger->buffer_read_offset = 0;
-+	logger->buffer_write_offset = 0;
-+
-+	logger->open_count = 0;
-+
-+	logger->flags.bits.ENABLE_CONSOLE = 1;
-+	logger->flags.bits.ENABLE_BUFFER = 0;
-+
-+	logger->ctx = ctx;
-+
-+	logger->mask = log_mask;
-+
-+	return true;
-+}
-+
-+static void destruct(struct dal_logger *logger)
-+{
-+	if (logger->log_buffer) {
-+		kfree(logger->log_buffer);
-+		logger->log_buffer = NULL;
-+	}
-+}
-+
-+struct dal_logger *dal_logger_create(struct dc_context *ctx, uint32_t log_mask)
-+{
-+	/* malloc struct */
-+	struct dal_logger *logger = kzalloc(sizeof(struct dal_logger),
-+					    GFP_KERNEL);
-+
-+	if (!logger)
-+		return NULL;
-+	if (!construct(ctx, logger, log_mask)) {
-+		kfree(logger);
-+		return NULL;
-+	}
-+
-+	return logger;
-+}
-+
-+uint32_t dal_logger_destroy(struct dal_logger **logger)
-+{
-+	if (logger == NULL || *logger == NULL)
-+		return 1;
-+	destruct(*logger);
-+	kfree(*logger);
-+	*logger = NULL;
-+
-+	return 0;
-+}
-+
-+/* ------------------------------------------------------------------------ */
-+
-+
-+static bool dal_logger_should_log(
-+	struct dal_logger *logger,
-+	enum dc_log_type log_type)
-+{
-+	if (logger->mask & (1 << log_type))
-+		return true;
-+
-+	return false;
-+}
-+
-+static void log_to_debug_console(struct log_entry *entry)
-+{
-+	struct dal_logger *logger = entry->logger;
-+
-+	if (logger->flags.bits.ENABLE_CONSOLE == 0)
-+		return;
-+
-+	if (entry->buf_offset) {
-+		switch (entry->type) {
-+		case LOG_ERROR:
-+			dm_error("%s", entry->buf);
-+			break;
-+		default:
-+			dm_output_to_console("%s", entry->buf);
-+			break;
-+		}
-+	}
-+}
-+
-+/* Print everything unread existing in log_buffer to debug console*/
-+void dm_logger_flush_buffer(struct dal_logger *logger, bool should_warn)
-+{
-+	char *string_start = &logger->log_buffer[logger->buffer_read_offset];
-+
-+	if (should_warn)
-+		dm_output_to_console(
-+			"---------------- FLUSHING LOG BUFFER ----------------\n");
-+	while (logger->buffer_read_offset < logger->buffer_write_offset) {
-+
-+		if (logger->log_buffer[logger->buffer_read_offset] == '\0') {
-+			dm_output_to_console("%s", string_start);
-+			string_start = logger->log_buffer + logger->buffer_read_offset + 1;
-+		}
-+		logger->buffer_read_offset++;
-+	}
-+	if (should_warn)
-+		dm_output_to_console(
-+			"-------------- END FLUSHING LOG BUFFER --------------\n\n");
-+}
-+
-+static void log_to_internal_buffer(struct log_entry *entry)
-+{
-+
-+	uint32_t size = entry->buf_offset;
-+	struct dal_logger *logger = entry->logger;
-+
-+	if (logger->flags.bits.ENABLE_BUFFER == 0)
-+		return;
-+
-+	if (logger->log_buffer == NULL)
-+		return;
-+
-+	if (size > 0 && size < logger->log_buffer_size) {
-+
-+		int buffer_space = logger->log_buffer_size -
-+				logger->buffer_write_offset;
-+
-+		if (logger->buffer_write_offset == logger->buffer_read_offset) {
-+			/* Buffer is empty, start writing at beginning */
-+			buffer_space = logger->log_buffer_size;
-+			logger->buffer_write_offset = 0;
-+			logger->buffer_read_offset = 0;
-+		}
-+
-+		if (buffer_space > size) {
-+			/* No wrap around, copy 'size' bytes
-+			 * from 'entry->buf' to 'log_buffer'
-+			 */
-+			memmove(logger->log_buffer +
-+					logger->buffer_write_offset,
-+					entry->buf, size);
-+			logger->buffer_write_offset += size;
-+
-+		} else {
-+			/* Not enough room remaining, we should flush
-+			 * existing logs */
-+
-+			/* Flush existing unread logs to console */
-+			dm_logger_flush_buffer(logger, true);
-+
-+			/* Start writing to beginning of buffer */
-+			memmove(logger->log_buffer, entry->buf, size);
-+			logger->buffer_write_offset = size;
-+			logger->buffer_read_offset = 0;
-+		}
-+
-+	}
-+}
-+
-+static void log_heading(struct log_entry *entry)
-+{
-+	int j;
-+
-+	for (j = 0; j < NUM_ELEMENTS(log_type_info_tbl); j++) {
-+
-+		const struct dc_log_type_info *info = &log_type_info_tbl[j];
-+
-+		if (info->type == entry->type)
-+			dm_logger_append(entry, "[%s]\t", info->name);
-+	}
-+}
-+
-+static void append_entry(
-+		struct log_entry *entry,
-+		char *buffer,
-+		uint32_t buf_size)
-+{
-+	if (!entry->buf ||
-+		entry->buf_offset + buf_size > entry->max_buf_bytes
-+	) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	/* Todo: check if off by 1 byte due to \0 anywhere */
-+	memmove(entry->buf + entry->buf_offset, buffer, buf_size);
-+	entry->buf_offset += buf_size;
-+}
-+
-+/* ------------------------------------------------------------------------ */
-+
-+/* Warning: Be careful that 'msg' is null terminated and the total size is
-+ * less than DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE (256) including '\0'
-+ */
-+void dm_logger_write(
-+	struct dal_logger *logger,
-+	enum dc_log_type log_type,
-+	const char *msg,
-+	...)
-+{
-+	if (logger && dal_logger_should_log(logger, log_type)) {
-+		uint32_t size;
-+		va_list args;
-+		char buffer[LOG_MAX_LINE_SIZE];
-+		struct log_entry entry;
-+
-+		va_start(args, msg);
-+
-+		entry.logger = logger;
-+
-+		entry.buf = buffer;
-+
-+		entry.buf_offset = 0;
-+		entry.max_buf_bytes = DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char);
-+
-+		entry.type = log_type;
-+
-+		log_heading(&entry);
-+
-+		size = dm_log_to_buffer(
-+			buffer, LOG_MAX_LINE_SIZE - 1, msg, args);
-+
-+		buffer[entry.buf_offset + size] = '\0';
-+		entry.buf_offset += size + 1;
-+
-+		/* --Flush log_entry buffer-- */
-+		/* print to kernel console */
-+		log_to_debug_console(&entry);
-+		/* log internally for dsat */
-+		log_to_internal_buffer(&entry);
-+
-+		va_end(args);
-+	}
-+}
-+
-+/* Same as dm_logger_write, except without open() and close(), which must
-+ * be done separately.
-+ */
-+void dm_logger_append(
-+	struct log_entry *entry,
-+	const char *msg,
-+	...)
-+{
-+	struct dal_logger *logger;
-+
-+	if (!entry) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	logger = entry->logger;
-+
-+	if (logger && logger->open_count > 0 &&
-+		dal_logger_should_log(logger, entry->type)) {
-+
-+		uint32_t size;
-+		va_list args;
-+		char buffer[LOG_MAX_LINE_SIZE];
-+
-+		va_start(args, msg);
-+
-+		size = dm_log_to_buffer(
-+			buffer, LOG_MAX_LINE_SIZE, msg, args);
-+
-+		if (size < LOG_MAX_LINE_SIZE - 1) {
-+			append_entry(entry, buffer, size);
-+		} else {
-+			append_entry(entry, "LOG_ERROR, line too long\n", 27);
-+		}
-+
-+		va_end(args);
-+	}
-+}
-+
-+void dm_logger_open(
-+		struct dal_logger *logger,
-+		struct log_entry *entry, /* out */
-+		enum dc_log_type log_type)
-+{
-+	if (!entry) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	entry->type = log_type;
-+	entry->logger = logger;
-+
-+	entry->buf = kzalloc(DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char),
-+			     GFP_KERNEL);
-+
-+	entry->buf_offset = 0;
-+	entry->max_buf_bytes = DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char);
-+
-+	logger->open_count++;
-+
-+	log_heading(entry);
-+}
-+
-+void dm_logger_close(struct log_entry *entry)
-+{
-+	struct dal_logger *logger = entry->logger;
-+
-+	if (logger && logger->open_count > 0) {
-+		logger->open_count--;
-+	} else {
-+		BREAK_TO_DEBUGGER();
-+		goto cleanup;
-+	}
-+
-+	/* --Flush log_entry buffer-- */
-+	/* print to kernel console */
-+	log_to_debug_console(entry);
-+	/* log internally for dsat */
-+	log_to_internal_buffer(entry);
-+
-+	/* TODO: Write end heading */
-+
-+cleanup:
-+	if (entry->buf) {
-+		kfree(entry->buf);
-+		entry->buf = NULL;
-+		entry->buf_offset = 0;
-+		entry->max_buf_bytes = 0;
-+	}
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/basics/logger.h.0130~	2017-12-14 06:39:58.397903555 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/basics/logger.h	2017-12-14 06:39:58.397903555 +0100
-@@ -0,0 +1,30 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_LOGGER_H__
-+#define __DAL_LOGGER_H__
-+
-+
-+#endif /* __DAL_LOGGER_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c.0130~	2017-12-14 06:39:58.397903555 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c	2017-12-14 06:39:58.397903555 +0100
-@@ -0,0 +1,102 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "core_types.h"
-+#include "logger.h"
-+#include "include/logger_interface.h"
-+#include "dm_helpers.h"
-+
-+#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
-+
-+struct dc_signal_type_info {
-+	enum signal_type type;
-+	char name[MAX_NAME_LEN];
-+};
-+
-+static const struct dc_signal_type_info signal_type_info_tbl[] = {
-+		{SIGNAL_TYPE_NONE,             "NC"},
-+		{SIGNAL_TYPE_DVI_SINGLE_LINK,  "DVI"},
-+		{SIGNAL_TYPE_DVI_DUAL_LINK,    "DDVI"},
-+		{SIGNAL_TYPE_HDMI_TYPE_A,      "HDMIA"},
-+		{SIGNAL_TYPE_LVDS,             "LVDS"},
-+		{SIGNAL_TYPE_RGB,              "VGA"},
-+		{SIGNAL_TYPE_DISPLAY_PORT,     "DP"},
-+		{SIGNAL_TYPE_DISPLAY_PORT_MST, "MST"},
-+		{SIGNAL_TYPE_EDP,              "eDP"},
-+		{SIGNAL_TYPE_VIRTUAL,          "Virtual"}
-+};
-+
-+void dc_conn_log(struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint8_t *hex_data,
-+		int hex_data_count,
-+		enum dc_log_type event,
-+		const char *msg,
-+		...)
-+{
-+	int i;
-+	va_list args;
-+	struct log_entry entry = { 0 };
-+	enum signal_type signal;
-+
-+	if (link->local_sink)
-+		signal = link->local_sink->sink_signal;
-+	else
-+		signal = link->connector_signal;
-+
-+	if (link->type == dc_connection_mst_branch)
-+		signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
-+
-+	dm_logger_open(ctx->logger, &entry, event);
-+
-+	for (i = 0; i < NUM_ELEMENTS(signal_type_info_tbl); i++)
-+		if (signal == signal_type_info_tbl[i].type)
-+			break;
-+
-+	dm_logger_append(&entry, "[%s][ConnIdx:%d] ",
-+			signal_type_info_tbl[i].name,
-+			link->link_index);
-+
-+	va_start(args, msg);
-+	entry.buf_offset += dm_log_to_buffer(
-+		&entry.buf[entry.buf_offset],
-+		LOG_MAX_LINE_SIZE - entry.buf_offset,
-+		msg, args);
-+
-+	if (entry.buf[strlen(entry.buf) - 1] == '\n') {
-+		entry.buf[strlen(entry.buf) - 1] = '\0';
-+		entry.buf_offset--;
-+	}
-+
-+	if (hex_data)
-+		for (i = 0; i < hex_data_count; i++)
-+			dm_logger_append(&entry, "%2.2X ", hex_data[i]);
-+
-+	dm_logger_append(&entry, "^\n");
-+	dm_helpers_dc_conn_log(ctx, &entry, event);
-+	dm_logger_close(&entry);
-+
-+	va_end(args);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/basics/Makefile.0130~	2017-12-14 06:39:58.398903556 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/basics/Makefile	2017-12-14 06:39:58.397903555 +0100
-@@ -0,0 +1,11 @@
-+#
-+# Makefile for the 'utils' sub-component of DAL.
-+# It provides the general basic services required by other DAL
-+# subcomponents.
-+
-+BASICS = conversion.o fixpt31_32.o fixpt32_32.o grph_object_id.o \
-+	logger.o log_helpers.o vector.o
-+
-+AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_BASICS)
---- linux-4.14/drivers/gpu/drm/amd/display/dc/basics/vector.c.0130~	2017-12-14 06:39:58.398903556 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/basics/vector.c	2017-12-14 06:39:58.398903556 +0100
-@@ -0,0 +1,307 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "include/vector.h"
-+
-+bool dal_vector_construct(
-+	struct vector *vector,
-+	struct dc_context *ctx,
-+	uint32_t capacity,
-+	uint32_t struct_size)
-+{
-+	vector->container = NULL;
-+
-+	if (!struct_size || !capacity) {
-+		/* Container must be non-zero size*/
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	vector->container = kzalloc(struct_size * capacity, GFP_KERNEL);
-+	if (vector->container == NULL)
-+		return false;
-+	vector->capacity = capacity;
-+	vector->struct_size = struct_size;
-+	vector->count = 0;
-+	vector->ctx = ctx;
-+	return true;
-+}
-+
-+bool dal_vector_presized_costruct(
-+	struct vector *vector,
-+	struct dc_context *ctx,
-+	uint32_t count,
-+	void *initial_value,
-+	uint32_t struct_size)
-+{
-+	uint32_t i;
-+
-+	vector->container = NULL;
-+
-+	if (!struct_size || !count) {
-+		/* Container must be non-zero size*/
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	vector->container = kzalloc(struct_size * count, GFP_KERNEL);
-+
-+	if (vector->container == NULL)
-+		return false;
-+
-+	/* If caller didn't supply initial value then the default
-+	 * of all zeros is expected, which is exactly what dal_alloc()
-+	 * initialises the memory to. */
-+	if (NULL != initial_value) {
-+		for (i = 0; i < count; ++i)
-+			memmove(
-+				vector->container + i * struct_size,
-+				initial_value,
-+				struct_size);
-+	}
-+
-+	vector->capacity = count;
-+	vector->struct_size = struct_size;
-+	vector->count = count;
-+	return true;
-+}
-+
-+struct vector *dal_vector_presized_create(
-+	struct dc_context *ctx,
-+	uint32_t size,
-+	void *initial_value,
-+	uint32_t struct_size)
-+{
-+	struct vector *vector = kzalloc(sizeof(struct vector), GFP_KERNEL);
-+
-+	if (vector == NULL)
-+		return NULL;
-+
-+	if (dal_vector_presized_costruct(
-+		vector, ctx, size, initial_value, struct_size))
-+		return vector;
-+
-+	BREAK_TO_DEBUGGER();
-+	kfree(vector);
-+	return NULL;
-+}
-+
-+struct vector *dal_vector_create(
-+	struct dc_context *ctx,
-+	uint32_t capacity,
-+	uint32_t struct_size)
-+{
-+	struct vector *vector = kzalloc(sizeof(struct vector), GFP_KERNEL);
-+
-+	if (vector == NULL)
-+		return NULL;
-+
-+	if (dal_vector_construct(vector, ctx, capacity, struct_size))
-+		return vector;
-+
-+	BREAK_TO_DEBUGGER();
-+	kfree(vector);
-+	return NULL;
-+}
-+
-+void dal_vector_destruct(
-+	struct vector *vector)
-+{
-+	kfree(vector->container);
-+	vector->count = 0;
-+	vector->capacity = 0;
-+}
-+
-+void dal_vector_destroy(
-+	struct vector **vector)
-+{
-+	if (vector == NULL || *vector == NULL)
-+		return;
-+	dal_vector_destruct(*vector);
-+	kfree(*vector);
-+	*vector = NULL;
-+}
-+
-+uint32_t dal_vector_get_count(
-+	const struct vector *vector)
-+{
-+	return vector->count;
-+}
-+
-+void *dal_vector_at_index(
-+	const struct vector *vector,
-+	uint32_t index)
-+{
-+	if (vector->container == NULL || index >= vector->count)
-+		return NULL;
-+	return vector->container + (index * vector->struct_size);
-+}
-+
-+bool dal_vector_remove_at_index(
-+	struct vector *vector,
-+	uint32_t index)
-+{
-+	if (index >= vector->count)
-+		return false;
-+
-+	if (index != vector->count - 1)
-+		memmove(
-+			vector->container + (index * vector->struct_size),
-+			vector->container + ((index + 1) * vector->struct_size),
-+			(vector->count - index - 1) * vector->struct_size);
-+	vector->count -= 1;
-+
-+	return true;
-+}
-+
-+void dal_vector_set_at_index(
-+	const struct vector *vector,
-+	const void *what,
-+	uint32_t index)
-+{
-+	void *where = dal_vector_at_index(vector, index);
-+
-+	if (!where) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+	memmove(
-+		where,
-+		what,
-+		vector->struct_size);
-+}
-+
-+static inline uint32_t calc_increased_capacity(
-+	uint32_t old_capacity)
-+{
-+	return old_capacity * 2;
-+}
-+
-+bool dal_vector_insert_at(
-+	struct vector *vector,
-+	const void *what,
-+	uint32_t position)
-+{
-+	uint8_t *insert_address;
-+
-+	if (vector->count == vector->capacity) {
-+		if (!dal_vector_reserve(
-+			vector,
-+			calc_increased_capacity(vector->capacity)))
-+			return false;
-+	}
-+
-+	insert_address = vector->container + (vector->struct_size * position);
-+
-+	if (vector->count && position < vector->count)
-+		memmove(
-+			insert_address + vector->struct_size,
-+			insert_address,
-+			vector->struct_size * (vector->count - position));
-+
-+	memmove(
-+		insert_address,
-+		what,
-+		vector->struct_size);
-+
-+	vector->count++;
-+
-+	return true;
-+}
-+
-+bool dal_vector_append(
-+	struct vector *vector,
-+	const void *item)
-+{
-+	return dal_vector_insert_at(vector, item, vector->count);
-+}
-+
-+struct vector *dal_vector_clone(
-+	const struct vector *vector)
-+{
-+	struct vector *vec_cloned;
-+	uint32_t count;
-+
-+	/* create new vector */
-+	count = dal_vector_get_count(vector);
-+
-+	if (count == 0)
-+		/* when count is 0 we still want to create clone of the vector
-+		 */
-+		vec_cloned = dal_vector_create(
-+			vector->ctx,
-+			vector->capacity,
-+			vector->struct_size);
-+	else
-+		/* Call "presized create" version, independently of how the
-+		 * original vector was created.
-+		 * The owner of original vector must know how to treat the new
-+		 * vector - as "presized" or as "regular".
-+		 * But from vector point of view it doesn't matter. */
-+		vec_cloned = dal_vector_presized_create(vector->ctx, count,
-+			NULL,/* no initial value */
-+			vector->struct_size);
-+
-+	if (NULL == vec_cloned) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	/* copy vector's data */
-+	memmove(vec_cloned->container, vector->container,
-+			vec_cloned->struct_size * vec_cloned->capacity);
-+
-+	return vec_cloned;
-+}
-+
-+uint32_t dal_vector_capacity(const struct vector *vector)
-+{
-+	return vector->capacity;
-+}
-+
-+bool dal_vector_reserve(struct vector *vector, uint32_t capacity)
-+{
-+	void *new_container;
-+
-+	if (capacity <= vector->capacity)
-+		return true;
-+
-+	new_container = krealloc(vector->container,
-+				 capacity * vector->struct_size, GFP_KERNEL);
-+
-+	if (new_container) {
-+		vector->container = new_container;
-+		vector->capacity = capacity;
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+void dal_vector_clear(struct vector *vector)
-+{
-+	vector->count = 0;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c.0130~	2017-12-14 06:39:58.398903556 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c	2017-12-14 06:39:58.398903556 +0100
-@@ -0,0 +1,1934 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "ObjectID.h"
-+#include "atomfirmware.h"
-+
-+#include "dc_bios_types.h"
-+#include "include/grph_object_ctrl_defs.h"
-+#include "include/bios_parser_interface.h"
-+#include "include/i2caux_interface.h"
-+#include "include/logger_interface.h"
-+
-+#include "command_table2.h"
-+
-+#include "bios_parser_helper.h"
-+#include "command_table_helper2.h"
-+#include "bios_parser2.h"
-+#include "bios_parser_types_internal2.h"
-+#include "bios_parser_interface.h"
-+
-+#include "bios_parser_common.h"
-+#define LAST_RECORD_TYPE 0xff
-+
-+
-+struct i2c_id_config_access {
-+	uint8_t bfI2C_LineMux:4;
-+	uint8_t bfHW_EngineID:3;
-+	uint8_t bfHW_Capable:1;
-+	uint8_t ucAccess;
-+};
-+
-+static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
-+	struct atom_i2c_record *record,
-+	struct graphics_object_i2c_info *info);
-+
-+static enum bp_result bios_parser_get_firmware_info(
-+	struct dc_bios *dcb,
-+	struct dc_firmware_info *info);
-+
-+static enum bp_result bios_parser_get_encoder_cap_info(
-+	struct dc_bios *dcb,
-+	struct graphics_object_id object_id,
-+	struct bp_encoder_cap_info *info);
-+
-+static enum bp_result get_firmware_info_v3_1(
-+	struct bios_parser *bp,
-+	struct dc_firmware_info *info);
-+
-+static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
-+		struct atom_display_object_path_v2 *object);
-+
-+static struct atom_encoder_caps_record *get_encoder_cap_record(
-+	struct bios_parser *bp,
-+	struct atom_display_object_path_v2 *object);
-+
-+#define BIOS_IMAGE_SIZE_OFFSET 2
-+#define BIOS_IMAGE_SIZE_UNIT 512
-+
-+#define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
-+
-+
-+static void destruct(struct bios_parser *bp)
-+{
-+	kfree(bp->base.bios_local_image);
-+	kfree(bp->base.integrated_info);
-+}
-+
-+static void firmware_parser_destroy(struct dc_bios **dcb)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(*dcb);
-+
-+	if (!bp) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	destruct(bp);
-+
-+	kfree(bp);
-+	*dcb = NULL;
-+}
-+
-+static void get_atom_data_table_revision(
-+	struct atom_common_table_header *atom_data_tbl,
-+	struct atom_data_revision *tbl_revision)
-+{
-+	if (!tbl_revision)
-+		return;
-+
-+	/* initialize the revision to 0 which is invalid revision */
-+	tbl_revision->major = 0;
-+	tbl_revision->minor = 0;
-+
-+	if (!atom_data_tbl)
-+		return;
-+
-+	tbl_revision->major =
-+			(uint32_t) atom_data_tbl->format_revision & 0x3f;
-+	tbl_revision->minor =
-+			(uint32_t) atom_data_tbl->content_revision & 0x3f;
-+}
-+
-+/* BIOS oject table displaypath is per connector.
-+ * There is extra path not for connector. BIOS fill its encoderid as 0
-+ */
-+static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	unsigned int count = 0;
-+	unsigned int i;
-+
-+	for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
-+		if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
-+			count++;
-+	}
-+	return count;
-+}
-+
-+static struct graphics_object_id bios_parser_get_encoder_id(
-+	struct dc_bios *dcb,
-+	uint32_t i)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	struct graphics_object_id object_id = dal_graphics_object_id_init(
-+		0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
-+
-+	if (bp->object_info_tbl.v1_4->number_of_path > i)
-+		object_id = object_id_from_bios_object_id(
-+		bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
-+
-+	return object_id;
-+}
-+
-+static struct graphics_object_id bios_parser_get_connector_id(
-+	struct dc_bios *dcb,
-+	uint8_t i)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	struct graphics_object_id object_id = dal_graphics_object_id_init(
-+		0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
-+	struct object_info_table *tbl = &bp->object_info_tbl;
-+	struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
-+
-+	if (v1_4->number_of_path > i) {
-+		/* If display_objid is generic object id,  the encoderObj
-+		 * /extencoderobjId should be 0
-+		 */
-+		if (v1_4->display_path[i].encoderobjid != 0 &&
-+				v1_4->display_path[i].display_objid != 0)
-+			object_id = object_id_from_bios_object_id(
-+					v1_4->display_path[i].display_objid);
-+	}
-+
-+	return object_id;
-+}
-+
-+
-+/*  TODO:  GetNumberOfSrc*/
-+
-+static uint32_t bios_parser_get_dst_number(struct dc_bios *dcb,
-+	struct graphics_object_id id)
-+{
-+	/* connector has 1 Dest, encoder has 0 Dest */
-+	switch (id.type) {
-+	case OBJECT_TYPE_ENCODER:
-+		return 0;
-+	case OBJECT_TYPE_CONNECTOR:
-+		return 1;
-+	default:
-+		return 0;
-+	}
-+}
-+
-+/*  removed getSrcObjList, getDestObjList*/
-+
-+
-+static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
-+	struct graphics_object_id object_id, uint32_t index,
-+	struct graphics_object_id *src_object_id)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	unsigned int i;
-+	enum bp_result  bp_result = BP_RESULT_BADINPUT;
-+	struct graphics_object_id obj_id = {0};
-+	struct object_info_table *tbl = &bp->object_info_tbl;
-+
-+	if (!src_object_id)
-+		return bp_result;
-+
-+	switch (object_id.type) {
-+	/* Encoder's Source is GPU.  BIOS does not provide GPU, since all
-+	 * displaypaths point to same GPU (0x1100).  Hardcode GPU object type
-+	 */
-+	case OBJECT_TYPE_ENCODER:
-+		/* TODO: since num of src must be less than 2.
-+		 * If found in for loop, should break.
-+		 * DAL2 implementation may be changed too
-+		 */
-+		for (i = 0; i < tbl->v1_4->number_of_path; i++) {
-+			obj_id = object_id_from_bios_object_id(
-+			tbl->v1_4->display_path[i].encoderobjid);
-+			if (object_id.type == obj_id.type &&
-+					object_id.id == obj_id.id &&
-+						object_id.enum_id ==
-+							obj_id.enum_id) {
-+				*src_object_id =
-+				object_id_from_bios_object_id(0x1100);
-+				/* break; */
-+			}
-+		}
-+		bp_result = BP_RESULT_OK;
-+		break;
-+	case OBJECT_TYPE_CONNECTOR:
-+		for (i = 0; i < tbl->v1_4->number_of_path; i++) {
-+			obj_id = object_id_from_bios_object_id(
-+				tbl->v1_4->display_path[i].display_objid);
-+
-+			if (object_id.type == obj_id.type &&
-+				object_id.id == obj_id.id &&
-+					object_id.enum_id == obj_id.enum_id) {
-+				*src_object_id =
-+				object_id_from_bios_object_id(
-+				tbl->v1_4->display_path[i].encoderobjid);
-+				/* break; */
-+			}
-+		}
-+		bp_result = BP_RESULT_OK;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return bp_result;
-+}
-+
-+static enum bp_result bios_parser_get_dst_obj(struct dc_bios *dcb,
-+	struct graphics_object_id object_id, uint32_t index,
-+	struct graphics_object_id *dest_object_id)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	unsigned int i;
-+	enum bp_result  bp_result = BP_RESULT_BADINPUT;
-+	struct graphics_object_id obj_id = {0};
-+	struct object_info_table *tbl = &bp->object_info_tbl;
-+
-+	if (!dest_object_id)
-+		return BP_RESULT_BADINPUT;
-+
-+	switch (object_id.type) {
-+	case OBJECT_TYPE_ENCODER:
-+		/* TODO: since num of src must be less than 2.
-+		 * If found in for loop, should break.
-+		 * DAL2 implementation may be changed too
-+		 */
-+		for (i = 0; i < tbl->v1_4->number_of_path; i++) {
-+			obj_id = object_id_from_bios_object_id(
-+				tbl->v1_4->display_path[i].encoderobjid);
-+			if (object_id.type == obj_id.type &&
-+					object_id.id == obj_id.id &&
-+						object_id.enum_id ==
-+							obj_id.enum_id) {
-+				*dest_object_id =
-+					object_id_from_bios_object_id(
-+				tbl->v1_4->display_path[i].display_objid);
-+				/* break; */
-+			}
-+		}
-+		bp_result = BP_RESULT_OK;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return bp_result;
-+}
-+
-+
-+/* from graphics_object_id, find display path which includes the object_id */
-+static struct atom_display_object_path_v2 *get_bios_object(
-+	struct bios_parser *bp,
-+	struct graphics_object_id id)
-+{
-+	unsigned int i;
-+	struct graphics_object_id obj_id = {0};
-+
-+	switch (id.type) {
-+	case OBJECT_TYPE_ENCODER:
-+		for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
-+			obj_id = object_id_from_bios_object_id(
-+			bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
-+			if (id.type == obj_id.type &&
-+					id.id == obj_id.id &&
-+						id.enum_id == obj_id.enum_id)
-+				return
-+				&bp->object_info_tbl.v1_4->display_path[i];
-+		}
-+	case OBJECT_TYPE_CONNECTOR:
-+	case OBJECT_TYPE_GENERIC:
-+		/* Both Generic and Connector Object ID
-+		 * will be stored on display_objid
-+		*/
-+		for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
-+			obj_id = object_id_from_bios_object_id(
-+			bp->object_info_tbl.v1_4->display_path[i].display_objid
-+			);
-+			if (id.type == obj_id.type &&
-+					id.id == obj_id.id &&
-+						id.enum_id == obj_id.enum_id)
-+				return
-+				&bp->object_info_tbl.v1_4->display_path[i];
-+		}
-+	default:
-+		return NULL;
-+	}
-+}
-+
-+static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
-+	struct graphics_object_id id,
-+	struct graphics_object_i2c_info *info)
-+{
-+	uint32_t offset;
-+	struct atom_display_object_path_v2 *object;
-+	struct atom_common_record_header *header;
-+	struct atom_i2c_record *record;
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	object = get_bios_object(bp, id);
-+
-+	if (!object)
-+		return BP_RESULT_BADINPUT;
-+
-+	offset = object->disp_recordoffset + bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(struct atom_common_record_header, offset);
-+
-+		if (!header)
-+			return BP_RESULT_BADBIOSTABLE;
-+
-+		if (header->record_type == LAST_RECORD_TYPE ||
-+			!header->record_size)
-+			break;
-+
-+		if (header->record_type == ATOM_I2C_RECORD_TYPE
-+			&& sizeof(struct atom_i2c_record) <=
-+							header->record_size) {
-+			/* get the I2C info */
-+			record = (struct atom_i2c_record *) header;
-+
-+			if (get_gpio_i2c_info(bp, record, info) ==
-+								BP_RESULT_OK)
-+				return BP_RESULT_OK;
-+		}
-+
-+		offset += header->record_size;
-+	}
-+
-+	return BP_RESULT_NORECORD;
-+}
-+
-+static enum bp_result get_gpio_i2c_info(
-+	struct bios_parser *bp,
-+	struct atom_i2c_record *record,
-+	struct graphics_object_i2c_info *info)
-+{
-+	struct atom_gpio_pin_lut_v2_1 *header;
-+	uint32_t count = 0;
-+	unsigned int table_index = 0;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	/* get the GPIO_I2C info */
-+	if (!DATA_TABLES(gpio_pin_lut))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
-+					DATA_TABLES(gpio_pin_lut));
-+	if (!header)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (sizeof(struct atom_common_table_header) +
-+			sizeof(struct atom_gpio_pin_assignment)	>
-+			le16_to_cpu(header->table_header.structuresize))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	/* TODO: is version change? */
-+	if (header->table_header.content_revision != 1)
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	/* get data count */
-+	count = (le16_to_cpu(header->table_header.structuresize)
-+			- sizeof(struct atom_common_table_header))
-+				/ sizeof(struct atom_gpio_pin_assignment);
-+
-+	table_index = record->i2c_id  & I2C_HW_LANE_MUX;
-+
-+	if (count < table_index) {
-+		bool find_valid = false;
-+
-+		for (table_index = 0; table_index < count; table_index++) {
-+			if (((record->i2c_id & I2C_HW_CAP) == (
-+			header->gpio_pin[table_index].gpio_id &
-+							I2C_HW_CAP)) &&
-+			((record->i2c_id & I2C_HW_ENGINE_ID_MASK)  ==
-+			(header->gpio_pin[table_index].gpio_id &
-+						I2C_HW_ENGINE_ID_MASK)) &&
-+			((record->i2c_id & I2C_HW_LANE_MUX) ==
-+			(header->gpio_pin[table_index].gpio_id &
-+							I2C_HW_LANE_MUX))) {
-+				/* still valid */
-+				find_valid = true;
-+				break;
-+			}
-+		}
-+		/* If we don't find the entry that we are looking for then
-+		 *  we will return BP_Result_BadBiosTable.
-+		 */
-+		if (find_valid == false)
-+			return BP_RESULT_BADBIOSTABLE;
-+	}
-+
-+	/* get the GPIO_I2C_INFO */
-+	info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
-+	info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
-+	info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
-+	info->i2c_slave_address = record->i2c_slave_addr;
-+
-+	/* TODO: check how to get register offset for en, Y, etc. */
-+	info->gpio_info.clk_a_register_index =
-+			le16_to_cpu(
-+			header->gpio_pin[table_index].data_a_reg_index);
-+	info->gpio_info.clk_a_shift =
-+			header->gpio_pin[table_index].gpio_bitshift;
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_voltage_ddc_info_v4(
-+	uint8_t *i2c_line,
-+	uint32_t index,
-+	struct atom_common_table_header *header,
-+	uint8_t *address)
-+{
-+	enum bp_result result = BP_RESULT_NORECORD;
-+	struct atom_voltage_objects_info_v4_1 *info =
-+		(struct atom_voltage_objects_info_v4_1 *) address;
-+
-+	uint8_t *voltage_current_object =
-+		(uint8_t *) (&(info->voltage_object[0]));
-+
-+	while ((address + le16_to_cpu(header->structuresize)) >
-+						voltage_current_object) {
-+		struct atom_i2c_voltage_object_v4 *object =
-+			(struct atom_i2c_voltage_object_v4 *)
-+						voltage_current_object;
-+
-+		if (object->header.voltage_mode ==
-+			ATOM_INIT_VOLTAGE_REGULATOR) {
-+			if (object->header.voltage_type == index) {
-+				*i2c_line = object->i2c_id ^ 0x90;
-+				result = BP_RESULT_OK;
-+				break;
-+			}
-+		}
-+
-+		voltage_current_object +=
-+				le16_to_cpu(object->header.object_size);
-+	}
-+	return result;
-+}
-+
-+static enum bp_result bios_parser_get_thermal_ddc_info(
-+	struct dc_bios *dcb,
-+	uint32_t i2c_channel_id,
-+	struct graphics_object_i2c_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	struct i2c_id_config_access *config;
-+	struct atom_i2c_record record;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	config = (struct i2c_id_config_access *) &i2c_channel_id;
-+
-+	record.i2c_id = config->bfHW_Capable;
-+	record.i2c_id |= config->bfI2C_LineMux;
-+	record.i2c_id |= config->bfHW_EngineID;
-+
-+	return get_gpio_i2c_info(bp, &record, info);
-+}
-+
-+static enum bp_result bios_parser_get_voltage_ddc_info(struct dc_bios *dcb,
-+	uint32_t index,
-+	struct graphics_object_i2c_info *info)
-+{
-+	uint8_t i2c_line = 0;
-+	enum bp_result result = BP_RESULT_NORECORD;
-+	uint8_t *voltage_info_address;
-+	struct atom_common_table_header *header;
-+	struct atom_data_revision revision = {0};
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!DATA_TABLES(voltageobject_info))
-+		return result;
-+
-+	voltage_info_address = bios_get_image(&bp->base,
-+			DATA_TABLES(voltageobject_info),
-+			sizeof(struct atom_common_table_header));
-+
-+	header = (struct atom_common_table_header *) voltage_info_address;
-+
-+	get_atom_data_table_revision(header, &revision);
-+
-+	switch (revision.major) {
-+	case 4:
-+		if (revision.minor != 1)
-+			break;
-+		result = get_voltage_ddc_info_v4(&i2c_line, index, header,
-+			voltage_info_address);
-+		break;
-+	}
-+
-+	if (result == BP_RESULT_OK)
-+		result = bios_parser_get_thermal_ddc_info(dcb,
-+			i2c_line, info);
-+
-+	return result;
-+}
-+
-+static enum bp_result bios_parser_get_hpd_info(
-+	struct dc_bios *dcb,
-+	struct graphics_object_id id,
-+	struct graphics_object_hpd_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	struct atom_display_object_path_v2 *object;
-+	struct atom_hpd_int_record *record = NULL;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	object = get_bios_object(bp, id);
-+
-+	if (!object)
-+		return BP_RESULT_BADINPUT;
-+
-+	record = get_hpd_record(bp, object);
-+
-+	if (record != NULL) {
-+		info->hpd_int_gpio_uid = record->pin_id;
-+		info->hpd_active = record->plugin_pin_state;
-+		return BP_RESULT_OK;
-+	}
-+
-+	return BP_RESULT_NORECORD;
-+}
-+
-+static struct atom_hpd_int_record *get_hpd_record(
-+	struct bios_parser *bp,
-+	struct atom_display_object_path_v2 *object)
-+{
-+	struct atom_common_record_header *header;
-+	uint32_t offset;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object */
-+		return NULL;
-+	}
-+
-+	offset = le16_to_cpu(object->disp_recordoffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(struct atom_common_record_header, offset);
-+
-+		if (!header)
-+			return NULL;
-+
-+		if (header->record_type == LAST_RECORD_TYPE ||
-+			!header->record_size)
-+			break;
-+
-+		if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
-+			&& sizeof(struct atom_hpd_int_record) <=
-+							header->record_size)
-+			return (struct atom_hpd_int_record *) header;
-+
-+		offset += header->record_size;
-+	}
-+
-+	return NULL;
-+}
-+
-+/**
-+ * bios_parser_get_gpio_pin_info
-+ * Get GpioPin information of input gpio id
-+ *
-+ * @param gpio_id, GPIO ID
-+ * @param info, GpioPin information structure
-+ * @return Bios parser result code
-+ * @note
-+ *  to get the GPIO PIN INFO, we need:
-+ *  1. get the GPIO_ID from other object table, see GetHPDInfo()
-+ *  2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
-+ *	to get the registerA  offset/mask
-+ */
-+static enum bp_result bios_parser_get_gpio_pin_info(
-+	struct dc_bios *dcb,
-+	uint32_t gpio_id,
-+	struct gpio_pin_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	struct atom_gpio_pin_lut_v2_1 *header;
-+	uint32_t count = 0;
-+	uint32_t i = 0;
-+
-+	if (!DATA_TABLES(gpio_pin_lut))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
-+						DATA_TABLES(gpio_pin_lut));
-+	if (!header)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (sizeof(struct atom_common_table_header) +
-+			sizeof(struct atom_gpio_pin_lut_v2_1)
-+			> le16_to_cpu(header->table_header.structuresize))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (header->table_header.content_revision != 1)
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	/* Temporary hard code gpio pin info */
-+#if defined(FOR_SIMNOW_BOOT)
-+	{
-+		struct  atom_gpio_pin_assignment  gpio_pin[8] = {
-+				{0x5db5, 0, 0, 1, 0},
-+				{0x5db5, 8, 8, 2, 0},
-+				{0x5db5, 0x10, 0x10, 3, 0},
-+				{0x5db5, 0x18, 0x14, 4, 0},
-+				{0x5db5, 0x1A, 0x18, 5, 0},
-+				{0x5db5, 0x1C, 0x1C, 6, 0},
-+		};
-+
-+		count = 6;
-+		memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin));
-+	}
-+#else
-+	count = (le16_to_cpu(header->table_header.structuresize)
-+			- sizeof(struct atom_common_table_header))
-+				/ sizeof(struct atom_gpio_pin_assignment);
-+#endif
-+	for (i = 0; i < count; ++i) {
-+		if (header->gpio_pin[i].gpio_id != gpio_id)
-+			continue;
-+
-+		info->offset =
-+			(uint32_t) le16_to_cpu(
-+					header->gpio_pin[i].data_a_reg_index);
-+		info->offset_y = info->offset + 2;
-+		info->offset_en = info->offset + 1;
-+		info->offset_mask = info->offset - 1;
-+
-+		info->mask = (uint32_t) (1 <<
-+			header->gpio_pin[i].gpio_bitshift);
-+		info->mask_y = info->mask + 2;
-+		info->mask_en = info->mask + 1;
-+		info->mask_mask = info->mask - 1;
-+
-+		return BP_RESULT_OK;
-+	}
-+
-+	return BP_RESULT_NORECORD;
-+}
-+
-+static struct device_id device_type_from_device_id(uint16_t device_id)
-+{
-+
-+	struct device_id result_device_id;
-+
-+	result_device_id.raw_device_tag = device_id;
-+
-+	switch (device_id) {
-+	case ATOM_DISPLAY_LCD1_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_LCD;
-+		result_device_id.enum_id = 1;
-+		break;
-+
-+	case ATOM_DISPLAY_DFP1_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 1;
-+		break;
-+
-+	case ATOM_DISPLAY_DFP2_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 2;
-+		break;
-+
-+	case ATOM_DISPLAY_DFP3_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 3;
-+		break;
-+
-+	case ATOM_DISPLAY_DFP4_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 4;
-+		break;
-+
-+	case ATOM_DISPLAY_DFP5_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 5;
-+		break;
-+
-+	case ATOM_DISPLAY_DFP6_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 6;
-+		break;
-+
-+	default:
-+		BREAK_TO_DEBUGGER(); /* Invalid device Id */
-+		result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
-+		result_device_id.enum_id = 0;
-+	}
-+	return result_device_id;
-+}
-+
-+static enum bp_result bios_parser_get_device_tag(
-+	struct dc_bios *dcb,
-+	struct graphics_object_id connector_object_id,
-+	uint32_t device_tag_index,
-+	struct connector_device_tag_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	struct atom_display_object_path_v2 *object;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	/* getBiosObject will return MXM object */
-+	object = get_bios_object(bp, connector_object_id);
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object id */
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	info->acpi_device = 0; /* BIOS no longer provides this */
-+	info->dev_id = device_type_from_device_id(object->device_tag);
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_ss_info_v4_1(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	uint32_t index,
-+	struct spread_spectrum_info *ss_info)
-+{
-+	enum bp_result result = BP_RESULT_OK;
-+	struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
-+
-+	if (!ss_info)
-+		return BP_RESULT_BADINPUT;
-+
-+	if (!DATA_TABLES(dce_info))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	disp_cntl_tbl =  GET_IMAGE(struct atom_display_controller_info_v4_1,
-+							DATA_TABLES(dce_info));
-+	if (!disp_cntl_tbl)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	ss_info->type.STEP_AND_DELAY_INFO = false;
-+	ss_info->spread_percentage_divider = 1000;
-+	/* BIOS no longer uses target clock.  Always enable for now */
-+	ss_info->target_clock_range = 0xffffffff;
-+
-+	switch (id) {
-+	case AS_SIGNAL_TYPE_DVI:
-+		ss_info->spread_spectrum_percentage =
-+				disp_cntl_tbl->dvi_ss_percentage;
-+		ss_info->spread_spectrum_range =
-+				disp_cntl_tbl->dvi_ss_rate_10hz * 10;
-+		if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
-+			ss_info->type.CENTER_MODE = true;
-+		break;
-+	case AS_SIGNAL_TYPE_HDMI:
-+		ss_info->spread_spectrum_percentage =
-+				disp_cntl_tbl->hdmi_ss_percentage;
-+		ss_info->spread_spectrum_range =
-+				disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
-+		if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
-+			ss_info->type.CENTER_MODE = true;
-+		break;
-+	/* TODO LVDS not support anymore? */
-+	case AS_SIGNAL_TYPE_DISPLAY_PORT:
-+		ss_info->spread_spectrum_percentage =
-+				disp_cntl_tbl->dp_ss_percentage;
-+		ss_info->spread_spectrum_range =
-+				disp_cntl_tbl->dp_ss_rate_10hz * 10;
-+		if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
-+			ss_info->type.CENTER_MODE = true;
-+		break;
-+	case AS_SIGNAL_TYPE_GPU_PLL:
-+		/* atom_firmware: DAL only get data from dce_info table.
-+		 * if data within smu_info is needed for DAL, VBIOS should
-+		 * copy it into dce_info
-+		 */
-+		result = BP_RESULT_UNSUPPORTED;
-+		break;
-+	default:
-+		result = BP_RESULT_UNSUPPORTED;
-+	}
-+
-+	return result;
-+}
-+
-+static enum bp_result get_ss_info_v4_2(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	uint32_t index,
-+	struct spread_spectrum_info *ss_info)
-+{
-+	enum bp_result result = BP_RESULT_OK;
-+	struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
-+	struct atom_smu_info_v3_1 *smu_info = NULL;
-+
-+	if (!ss_info)
-+		return BP_RESULT_BADINPUT;
-+
-+	if (!DATA_TABLES(dce_info))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (!DATA_TABLES(smu_info))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	disp_cntl_tbl =  GET_IMAGE(struct atom_display_controller_info_v4_2,
-+							DATA_TABLES(dce_info));
-+	if (!disp_cntl_tbl)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	smu_info =  GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
-+	if (!smu_info)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	ss_info->type.STEP_AND_DELAY_INFO = false;
-+	ss_info->spread_percentage_divider = 1000;
-+	/* BIOS no longer uses target clock.  Always enable for now */
-+	ss_info->target_clock_range = 0xffffffff;
-+
-+	switch (id) {
-+	case AS_SIGNAL_TYPE_DVI:
-+		ss_info->spread_spectrum_percentage =
-+				disp_cntl_tbl->dvi_ss_percentage;
-+		ss_info->spread_spectrum_range =
-+				disp_cntl_tbl->dvi_ss_rate_10hz * 10;
-+		if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
-+			ss_info->type.CENTER_MODE = true;
-+		break;
-+	case AS_SIGNAL_TYPE_HDMI:
-+		ss_info->spread_spectrum_percentage =
-+				disp_cntl_tbl->hdmi_ss_percentage;
-+		ss_info->spread_spectrum_range =
-+				disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
-+		if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
-+			ss_info->type.CENTER_MODE = true;
-+		break;
-+	/* TODO LVDS not support anymore? */
-+	case AS_SIGNAL_TYPE_DISPLAY_PORT:
-+		ss_info->spread_spectrum_percentage =
-+				smu_info->gpuclk_ss_percentage;
-+		ss_info->spread_spectrum_range =
-+				smu_info->gpuclk_ss_rate_10hz * 10;
-+		if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
-+			ss_info->type.CENTER_MODE = true;
-+		break;
-+	case AS_SIGNAL_TYPE_GPU_PLL:
-+		/* atom_firmware: DAL only get data from dce_info table.
-+		 * if data within smu_info is needed for DAL, VBIOS should
-+		 * copy it into dce_info
-+		 */
-+		result = BP_RESULT_UNSUPPORTED;
-+		break;
-+	default:
-+		result = BP_RESULT_UNSUPPORTED;
-+	}
-+
-+	return result;
-+}
-+
-+/**
-+ * bios_parser_get_spread_spectrum_info
-+ * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
-+ * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
-+ * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
-+ * ver 3.1,
-+ * there is only one entry for each signal /ss id.  However, there is
-+ * no planning of supporting multiple spread Sprectum entry for EverGreen
-+ * @param [in] this
-+ * @param [in] signal, ASSignalType to be converted to info index
-+ * @param [in] index, number of entries that match the converted info index
-+ * @param [out] ss_info, sprectrum information structure,
-+ * @return Bios parser result code
-+ */
-+static enum bp_result bios_parser_get_spread_spectrum_info(
-+	struct dc_bios *dcb,
-+	enum as_signal_type signal,
-+	uint32_t index,
-+	struct spread_spectrum_info *ss_info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	enum bp_result result = BP_RESULT_UNSUPPORTED;
-+	struct atom_common_table_header *header;
-+	struct atom_data_revision tbl_revision;
-+
-+	if (!ss_info) /* check for bad input */
-+		return BP_RESULT_BADINPUT;
-+
-+	if (!DATA_TABLES(dce_info))
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	header = GET_IMAGE(struct atom_common_table_header,
-+						DATA_TABLES(dce_info));
-+	get_atom_data_table_revision(header, &tbl_revision);
-+
-+	switch (tbl_revision.major) {
-+	case 4:
-+		switch (tbl_revision.minor) {
-+		case 1:
-+			return get_ss_info_v4_1(bp, signal, index, ss_info);
-+		case 2:
-+			return get_ss_info_v4_2(bp, signal, index, ss_info);
-+		default:
-+			break;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+	/* there can not be more then one entry for SS Info table */
-+	return result;
-+}
-+
-+static enum bp_result get_embedded_panel_info_v2_1(
-+	struct bios_parser *bp,
-+	struct embedded_panel_info *info)
-+{
-+	struct lcd_info_v2_1 *lvds;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	if (!DATA_TABLES(lcd_info))
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
-+
-+	if (!lvds)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	/* TODO: previous vv1_3, should v2_1 */
-+	if (!((lvds->table_header.format_revision == 2)
-+			&& (lvds->table_header.content_revision >= 1)))
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	memset(info, 0, sizeof(struct embedded_panel_info));
-+
-+	/* We need to convert from 10KHz units into KHz units */
-+	info->lcd_timing.pixel_clk =
-+			le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
-+	/* usHActive does not include borders, according to VBIOS team */
-+	info->lcd_timing.horizontal_addressable =
-+			le16_to_cpu(lvds->lcd_timing.h_active);
-+	/* usHBlanking_Time includes borders, so we should really be
-+	 * subtractingborders duing this translation, but LVDS generally
-+	 * doesn't have borders, so we should be okay leaving this as is for
-+	 * now.  May need to revisit if we ever have LVDS with borders
-+	 */
-+	info->lcd_timing.horizontal_blanking_time =
-+		le16_to_cpu(lvds->lcd_timing.h_blanking_time);
-+	/* usVActive does not include borders, according to VBIOS team*/
-+	info->lcd_timing.vertical_addressable =
-+		le16_to_cpu(lvds->lcd_timing.v_active);
-+	/* usVBlanking_Time includes borders, so we should really be
-+	 * subtracting borders duing this translation, but LVDS generally
-+	 * doesn't have borders, so we should be okay leaving this as is for
-+	 * now. May need to revisit if we ever have LVDS with borders
-+	 */
-+	info->lcd_timing.vertical_blanking_time =
-+		le16_to_cpu(lvds->lcd_timing.v_blanking_time);
-+	info->lcd_timing.horizontal_sync_offset =
-+		le16_to_cpu(lvds->lcd_timing.h_sync_offset);
-+	info->lcd_timing.horizontal_sync_width =
-+		le16_to_cpu(lvds->lcd_timing.h_sync_width);
-+	info->lcd_timing.vertical_sync_offset =
-+		le16_to_cpu(lvds->lcd_timing.v_sync_offset);
-+	info->lcd_timing.vertical_sync_width =
-+		le16_to_cpu(lvds->lcd_timing.v_syncwidth);
-+	info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
-+	info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
-+
-+	/* not provided by VBIOS */
-+	info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
-+
-+	info->lcd_timing.misc_info.H_SYNC_POLARITY =
-+		~(uint32_t)
-+		(lvds->lcd_timing.miscinfo & ATOM_HSYNC_POLARITY);
-+	info->lcd_timing.misc_info.V_SYNC_POLARITY =
-+		~(uint32_t)
-+		(lvds->lcd_timing.miscinfo & ATOM_VSYNC_POLARITY);
-+
-+	/* not provided by VBIOS */
-+	info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
-+
-+	info->lcd_timing.misc_info.H_REPLICATION_BY2 =
-+		!!(lvds->lcd_timing.miscinfo & ATOM_H_REPLICATIONBY2);
-+	info->lcd_timing.misc_info.V_REPLICATION_BY2 =
-+		!!(lvds->lcd_timing.miscinfo & ATOM_V_REPLICATIONBY2);
-+	info->lcd_timing.misc_info.COMPOSITE_SYNC =
-+		!!(lvds->lcd_timing.miscinfo & ATOM_COMPOSITESYNC);
-+	info->lcd_timing.misc_info.INTERLACE =
-+		!!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
-+
-+	/* not provided by VBIOS*/
-+	info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
-+	/* not provided by VBIOS*/
-+	info->ss_id = 0;
-+
-+	info->realtek_eDPToLVDS =
-+			!!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result bios_parser_get_embedded_panel_info(
-+	struct dc_bios *dcb,
-+	struct embedded_panel_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	struct atom_common_table_header *header;
-+	struct atom_data_revision tbl_revision;
-+
-+	if (!DATA_TABLES(lcd_info))
-+		return BP_RESULT_FAILURE;
-+
-+	header = GET_IMAGE(struct atom_common_table_header,
-+					DATA_TABLES(lcd_info));
-+
-+	if (!header)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	get_atom_data_table_revision(header, &tbl_revision);
-+
-+
-+	switch (tbl_revision.major) {
-+	case 2:
-+		switch (tbl_revision.minor) {
-+		case 1:
-+			return get_embedded_panel_info_v2_1(bp, info);
-+		default:
-+			break;
-+		}
-+	default:
-+		break;
-+	}
-+
-+	return BP_RESULT_FAILURE;
-+}
-+
-+static uint32_t get_support_mask_for_device_id(struct device_id device_id)
-+{
-+	enum dal_device_type device_type = device_id.device_type;
-+	uint32_t enum_id = device_id.enum_id;
-+
-+	switch (device_type) {
-+	case DEVICE_TYPE_LCD:
-+		switch (enum_id) {
-+		case 1:
-+			return ATOM_DISPLAY_LCD1_SUPPORT;
-+		default:
-+			break;
-+		}
-+		break;
-+	case DEVICE_TYPE_DFP:
-+		switch (enum_id) {
-+		case 1:
-+			return ATOM_DISPLAY_DFP1_SUPPORT;
-+		case 2:
-+			return ATOM_DISPLAY_DFP2_SUPPORT;
-+		case 3:
-+			return ATOM_DISPLAY_DFP3_SUPPORT;
-+		case 4:
-+			return ATOM_DISPLAY_DFP4_SUPPORT;
-+		case 5:
-+			return ATOM_DISPLAY_DFP5_SUPPORT;
-+		case 6:
-+			return ATOM_DISPLAY_DFP6_SUPPORT;
-+		default:
-+			break;
-+		}
-+		break;
-+	default:
-+		break;
-+	};
-+
-+	/* Unidentified device ID, return empty support mask. */
-+	return 0;
-+}
-+
-+static bool bios_parser_is_device_id_supported(
-+	struct dc_bios *dcb,
-+	struct device_id id)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	uint32_t mask = get_support_mask_for_device_id(id);
-+
-+	return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) &
-+								mask) != 0;
-+}
-+
-+static void bios_parser_post_init(
-+	struct dc_bios *dcb)
-+{
-+	/* TODO for OPM module. Need implement later */
-+}
-+
-+static uint32_t bios_parser_get_ss_entry_number(
-+	struct dc_bios *dcb,
-+	enum as_signal_type signal)
-+{
-+	/* TODO: DAL2 atomfirmware implementation does not need this.
-+	 * why DAL3 need this?
-+	 */
-+	return 1;
-+}
-+
-+static enum bp_result bios_parser_transmitter_control(
-+	struct dc_bios *dcb,
-+	struct bp_transmitter_control *cntl)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.transmitter_control)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.transmitter_control(bp, cntl);
-+}
-+
-+static enum bp_result bios_parser_encoder_control(
-+	struct dc_bios *dcb,
-+	struct bp_encoder_control *cntl)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.dig_encoder_control)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.dig_encoder_control(bp, cntl);
-+}
-+
-+static enum bp_result bios_parser_set_pixel_clock(
-+	struct dc_bios *dcb,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.set_pixel_clock)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
-+}
-+
-+static enum bp_result bios_parser_set_dce_clock(
-+	struct dc_bios *dcb,
-+	struct bp_set_dce_clock_parameters *bp_params)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.set_dce_clock)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.set_dce_clock(bp, bp_params);
-+}
-+
-+static unsigned int bios_parser_get_smu_clock_info(
-+	struct dc_bios *dcb)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.get_smu_clock_info)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.get_smu_clock_info(bp);
-+}
-+
-+static enum bp_result bios_parser_program_crtc_timing(
-+	struct dc_bios *dcb,
-+	struct bp_hw_crtc_timing_parameters *bp_params)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.set_crtc_timing)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
-+}
-+
-+static enum bp_result bios_parser_enable_crtc(
-+	struct dc_bios *dcb,
-+	enum controller_id id,
-+	bool enable)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.enable_crtc)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.enable_crtc(bp, id, enable);
-+}
-+
-+static enum bp_result bios_parser_crtc_source_select(
-+	struct dc_bios *dcb,
-+	struct bp_crtc_source_select *bp_params)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.select_crtc_source)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.select_crtc_source(bp, bp_params);
-+}
-+
-+static enum bp_result bios_parser_enable_disp_power_gating(
-+	struct dc_bios *dcb,
-+	enum controller_id controller_id,
-+	enum bp_pipe_control_action action)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.enable_disp_power_gating)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
-+		action);
-+}
-+
-+static bool bios_parser_is_accelerated_mode(
-+	struct dc_bios *dcb)
-+{
-+	return bios_is_accelerated_mode(dcb);
-+}
-+
-+
-+/**
-+ * bios_parser_set_scratch_critical_state
-+ *
-+ * @brief
-+ *  update critical state bit in VBIOS scratch register
-+ *
-+ * @param
-+ *  bool - to set or reset state
-+ */
-+static void bios_parser_set_scratch_critical_state(
-+	struct dc_bios *dcb,
-+	bool state)
-+{
-+	bios_set_scratch_critical_state(dcb, state);
-+}
-+
-+static enum bp_result bios_parser_get_firmware_info(
-+	struct dc_bios *dcb,
-+	struct dc_firmware_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	enum bp_result result = BP_RESULT_BADBIOSTABLE;
-+	struct atom_common_table_header *header;
-+
-+	struct atom_data_revision revision;
-+
-+	if (info && DATA_TABLES(firmwareinfo)) {
-+		header = GET_IMAGE(struct atom_common_table_header,
-+				DATA_TABLES(firmwareinfo));
-+		get_atom_data_table_revision(header, &revision);
-+		switch (revision.major) {
-+		case 3:
-+			switch (revision.minor) {
-+			case 1:
-+				result = get_firmware_info_v3_1(bp, info);
-+				break;
-+			default:
-+				break;
-+			}
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+static enum bp_result get_firmware_info_v3_1(
-+	struct bios_parser *bp,
-+	struct dc_firmware_info *info)
-+{
-+	struct atom_firmware_info_v3_1 *firmware_info;
-+	struct atom_display_controller_info_v4_1 *dce_info = NULL;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
-+			DATA_TABLES(firmwareinfo));
-+
-+	dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
-+			DATA_TABLES(dce_info));
-+
-+	if (!firmware_info || !dce_info)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	memset(info, 0, sizeof(*info));
-+
-+	/* Pixel clock pll information. */
-+	 /* We need to convert from 10KHz units into KHz units */
-+	info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
-+	info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
-+
-+	 /* 27MHz for Vega10: */
-+	info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
-+
-+	/* Hardcode frequency if BIOS gives no DCE Ref Clk */
-+	if (info->pll_info.crystal_frequency == 0)
-+		info->pll_info.crystal_frequency = 27000;
-+	/*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
-+	info->dp_phy_ref_clk     = dce_info->dpphy_refclk_10khz * 10;
-+	info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
-+
-+	/* Get GPU PLL VCO Clock */
-+
-+	if (bp->cmd_tbl.get_smu_clock_info != NULL) {
-+		/* VBIOS gives in 10KHz */
-+		info->smu_gpu_pll_output_freq =
-+				bp->cmd_tbl.get_smu_clock_info(bp) * 10;
-+	}
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result bios_parser_get_encoder_cap_info(
-+	struct dc_bios *dcb,
-+	struct graphics_object_id object_id,
-+	struct bp_encoder_cap_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	struct atom_display_object_path_v2 *object;
-+	struct atom_encoder_caps_record *record = NULL;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	object = get_bios_object(bp, object_id);
-+
-+	if (!object)
-+		return BP_RESULT_BADINPUT;
-+
-+	record = get_encoder_cap_record(bp, object);
-+	if (!record)
-+		return BP_RESULT_NORECORD;
-+
-+	info->DP_HBR2_CAP = (record->encodercaps &
-+			ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
-+	info->DP_HBR2_EN = (record->encodercaps &
-+			ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
-+	info->DP_HBR3_EN = (record->encodercaps &
-+			ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
-+	info->HDMI_6GB_EN = (record->encodercaps &
-+			ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
-+
-+	return BP_RESULT_OK;
-+}
-+
-+
-+static struct atom_encoder_caps_record *get_encoder_cap_record(
-+	struct bios_parser *bp,
-+	struct atom_display_object_path_v2 *object)
-+{
-+	struct atom_common_record_header *header;
-+	uint32_t offset;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object */
-+		return NULL;
-+	}
-+
-+	offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(struct atom_common_record_header, offset);
-+
-+		if (!header)
-+			return NULL;
-+
-+		offset += header->record_size;
-+
-+		if (header->record_type == LAST_RECORD_TYPE ||
-+				!header->record_size)
-+			break;
-+
-+		if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
-+			continue;
-+
-+		if (sizeof(struct atom_encoder_caps_record) <=
-+							header->record_size)
-+			return (struct atom_encoder_caps_record *)header;
-+	}
-+
-+	return NULL;
-+}
-+
-+/*
-+ * get_integrated_info_v11
-+ *
-+ * @brief
-+ * Get V8 integrated BIOS information
-+ *
-+ * @param
-+ * bios_parser *bp - [in]BIOS parser handler to get master data table
-+ * integrated_info *info - [out] store and output integrated info
-+ *
-+ * @return
-+ * enum bp_result - BP_RESULT_OK if information is available,
-+ *                  BP_RESULT_BADBIOSTABLE otherwise.
-+ */
-+static enum bp_result get_integrated_info_v11(
-+	struct bios_parser *bp,
-+	struct integrated_info *info)
-+{
-+	struct atom_integrated_system_info_v1_11 *info_v11;
-+	uint32_t i;
-+
-+	info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
-+					DATA_TABLES(integratedsysteminfo));
-+
-+	if (info_v11 == NULL)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	info->gpu_cap_info =
-+	le32_to_cpu(info_v11->gpucapinfo);
-+	/*
-+	* system_config: Bit[0] = 0 : PCIE power gating disabled
-+	*                       = 1 : PCIE power gating enabled
-+	*                Bit[1] = 0 : DDR-PLL shut down disabled
-+	*                       = 1 : DDR-PLL shut down enabled
-+	*                Bit[2] = 0 : DDR-PLL power down disabled
-+	*                       = 1 : DDR-PLL power down enabled
-+	*/
-+	info->system_config = le32_to_cpu(info_v11->system_config);
-+	info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
-+	info->memory_type = info_v11->memorytype;
-+	info->ma_channel_number = info_v11->umachannelnumber;
-+	info->lvds_ss_percentage =
-+	le16_to_cpu(info_v11->lvds_ss_percentage);
-+	info->lvds_sspread_rate_in_10hz =
-+	le16_to_cpu(info_v11->lvds_ss_rate_10hz);
-+	info->hdmi_ss_percentage =
-+	le16_to_cpu(info_v11->hdmi_ss_percentage);
-+	info->hdmi_sspread_rate_in_10hz =
-+	le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
-+	info->dvi_ss_percentage =
-+	le16_to_cpu(info_v11->dvi_ss_percentage);
-+	info->dvi_sspread_rate_in_10_hz =
-+	le16_to_cpu(info_v11->dvi_ss_rate_10hz);
-+	info->lvds_misc = info_v11->lvds_misc;
-+	for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
-+		info->ext_disp_conn_info.gu_id[i] =
-+				info_v11->extdispconninfo.guid[i];
-+	}
-+
-+	for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
-+		info->ext_disp_conn_info.path[i].device_connector_id =
-+		object_id_from_bios_object_id(
-+		le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
-+
-+		info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
-+		object_id_from_bios_object_id(
-+			le16_to_cpu(
-+			info_v11->extdispconninfo.path[i].ext_encoder_objid));
-+
-+		info->ext_disp_conn_info.path[i].device_tag =
-+			le16_to_cpu(
-+				info_v11->extdispconninfo.path[i].device_tag);
-+		info->ext_disp_conn_info.path[i].device_acpi_enum =
-+		le16_to_cpu(
-+			info_v11->extdispconninfo.path[i].device_acpi_enum);
-+		info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
-+			info_v11->extdispconninfo.path[i].auxddclut_index;
-+		info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
-+			info_v11->extdispconninfo.path[i].hpdlut_index;
-+		info->ext_disp_conn_info.path[i].channel_mapping.raw =
-+			info_v11->extdispconninfo.path[i].channelmapping;
-+		info->ext_disp_conn_info.path[i].caps =
-+				le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
-+	}
-+	info->ext_disp_conn_info.checksum =
-+	info_v11->extdispconninfo.checksum;
-+
-+	info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
-+	info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
-+	for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
-+		info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
-+				info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
-+		info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
-+				info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
-+	}
-+	info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
-+	for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
-+		info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
-+				info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
-+		info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
-+				info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
-+	}
-+
-+	info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
-+	info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
-+	for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
-+		info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
-+				info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
-+		info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
-+				info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
-+	}
-+	info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
-+	for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
-+		info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
-+				info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
-+		info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
-+				info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
-+	}
-+
-+	info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
-+	info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
-+	for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
-+		info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
-+				info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
-+		info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
-+				info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
-+	}
-+	info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
-+	for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
-+		info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
-+				info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
-+		info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
-+				info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
-+	}
-+
-+	info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
-+	info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
-+	for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
-+		info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
-+				info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
-+		info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
-+				info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
-+	}
-+	info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
-+	for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
-+		info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
-+				info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
-+		info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
-+				info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
-+	}
-+
-+
-+	/** TODO - review **/
-+	#if 0
-+	info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
-+									* 10;
-+	info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
-+	info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
-+
-+	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+		/* Convert [10KHz] into [KHz] */
-+		info->disp_clk_voltage[i].max_supported_clk =
-+		le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
-+			ulMaximumSupportedCLK) * 10;
-+		info->disp_clk_voltage[i].voltage_index =
-+		le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
-+	}
-+
-+	info->boot_up_req_display_vector =
-+			le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
-+	info->boot_up_nb_voltage =
-+			le16_to_cpu(info_v11->usBootUpNBVoltage);
-+	info->ext_disp_conn_info_offset =
-+			le16_to_cpu(info_v11->usExtDispConnInfoOffset);
-+	info->gmc_restore_reset_time =
-+			le32_to_cpu(info_v11->ulGMCRestoreResetTime);
-+	info->minimum_n_clk =
-+			le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
-+	for (i = 1; i < 4; ++i)
-+		info->minimum_n_clk =
-+				info->minimum_n_clk <
-+				le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
-+				info->minimum_n_clk : le32_to_cpu(
-+					info_v11->ulNbpStateNClkFreq[i]);
-+
-+	info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
-+	info->ddr_dll_power_up_time =
-+	    le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
-+	info->ddr_pll_power_up_time =
-+		le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
-+	info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
-+	info->max_lvds_pclk_freq_in_single_link =
-+		le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
-+	info->max_lvds_pclk_freq_in_single_link =
-+		le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
-+	info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
-+		info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
-+	info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
-+		info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
-+	info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
-+		info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
-+	info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
-+		info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
-+	info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
-+		info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
-+	info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
-+		info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
-+	info->lvds_off_to_on_delay_in_4ms =
-+		info_v11->ucLVDSOffToOnDelay_in4Ms;
-+	info->lvds_bit_depth_control_val =
-+		le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
-+
-+	for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
-+		/* Convert [10KHz] into [KHz] */
-+		info->avail_s_clk[i].supported_s_clk =
-+			le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
-+									* 10;
-+		info->avail_s_clk[i].voltage_index =
-+			le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
-+		info->avail_s_clk[i].voltage_id =
-+			le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
-+	}
-+	#endif /* TODO*/
-+
-+	return BP_RESULT_OK;
-+}
-+
-+
-+/*
-+ * construct_integrated_info
-+ *
-+ * @brief
-+ * Get integrated BIOS information based on table revision
-+ *
-+ * @param
-+ * bios_parser *bp - [in]BIOS parser handler to get master data table
-+ * integrated_info *info - [out] store and output integrated info
-+ *
-+ * @return
-+ * enum bp_result - BP_RESULT_OK if information is available,
-+ *                  BP_RESULT_BADBIOSTABLE otherwise.
-+ */
-+static enum bp_result construct_integrated_info(
-+	struct bios_parser *bp,
-+	struct integrated_info *info)
-+{
-+	enum bp_result result = BP_RESULT_BADBIOSTABLE;
-+
-+	struct atom_common_table_header *header;
-+	struct atom_data_revision revision;
-+
-+	struct clock_voltage_caps temp = {0, 0};
-+	uint32_t i;
-+	uint32_t j;
-+
-+	if (info && DATA_TABLES(integratedsysteminfo)) {
-+		header = GET_IMAGE(struct atom_common_table_header,
-+					DATA_TABLES(integratedsysteminfo));
-+
-+		get_atom_data_table_revision(header, &revision);
-+
-+		/* Don't need to check major revision as they are all 1 */
-+		switch (revision.minor) {
-+		case 11:
-+			result = get_integrated_info_v11(bp, info);
-+			break;
-+		default:
-+			return result;
-+		}
-+	}
-+
-+	if (result != BP_RESULT_OK)
-+		return result;
-+
-+	/* Sort voltage table from low to high*/
-+	for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+		for (j = i; j > 0; --j) {
-+			if (info->disp_clk_voltage[j].max_supported_clk <
-+				info->disp_clk_voltage[j-1].max_supported_clk
-+				) {
-+				/* swap j and j - 1*/
-+				temp = info->disp_clk_voltage[j-1];
-+				info->disp_clk_voltage[j-1] =
-+					info->disp_clk_voltage[j];
-+				info->disp_clk_voltage[j] = temp;
-+			}
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+static struct integrated_info *bios_parser_create_integrated_info(
-+	struct dc_bios *dcb)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	struct integrated_info *info = NULL;
-+
-+	info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
-+
-+	if (info == NULL) {
-+		ASSERT_CRITICAL(0);
-+		return NULL;
-+	}
-+
-+	if (construct_integrated_info(bp, info) == BP_RESULT_OK)
-+		return info;
-+
-+	kfree(info);
-+
-+	return NULL;
-+}
-+
-+static const struct dc_vbios_funcs vbios_funcs = {
-+	.get_connectors_number = bios_parser_get_connectors_number,
-+
-+	.get_encoder_id = bios_parser_get_encoder_id,
-+
-+	.get_connector_id = bios_parser_get_connector_id,
-+
-+	.get_dst_number = bios_parser_get_dst_number,
-+
-+	.get_src_obj = bios_parser_get_src_obj,
-+
-+	.get_dst_obj = bios_parser_get_dst_obj,
-+
-+	.get_i2c_info = bios_parser_get_i2c_info,
-+
-+	.get_voltage_ddc_info = bios_parser_get_voltage_ddc_info,
-+
-+	.get_thermal_ddc_info = bios_parser_get_thermal_ddc_info,
-+
-+	.get_hpd_info = bios_parser_get_hpd_info,
-+
-+	.get_device_tag = bios_parser_get_device_tag,
-+
-+	.get_firmware_info = bios_parser_get_firmware_info,
-+
-+	.get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
-+
-+	.get_ss_entry_number = bios_parser_get_ss_entry_number,
-+
-+	.get_embedded_panel_info = bios_parser_get_embedded_panel_info,
-+
-+	.get_gpio_pin_info = bios_parser_get_gpio_pin_info,
-+
-+	.get_encoder_cap_info = bios_parser_get_encoder_cap_info,
-+
-+	.is_device_id_supported = bios_parser_is_device_id_supported,
-+
-+
-+
-+	.is_accelerated_mode = bios_parser_is_accelerated_mode,
-+
-+	.set_scratch_critical_state = bios_parser_set_scratch_critical_state,
-+
-+
-+/*	 COMMANDS */
-+	.encoder_control = bios_parser_encoder_control,
-+
-+	.transmitter_control = bios_parser_transmitter_control,
-+
-+	.enable_crtc = bios_parser_enable_crtc,
-+
-+	.set_pixel_clock = bios_parser_set_pixel_clock,
-+
-+	.set_dce_clock = bios_parser_set_dce_clock,
-+
-+	.program_crtc_timing = bios_parser_program_crtc_timing,
-+
-+	/* .blank_crtc = bios_parser_blank_crtc, */
-+
-+	.crtc_source_select = bios_parser_crtc_source_select,
-+
-+	/* .external_encoder_control = bios_parser_external_encoder_control, */
-+
-+	.enable_disp_power_gating = bios_parser_enable_disp_power_gating,
-+
-+	.post_init = bios_parser_post_init,
-+
-+	.bios_parser_destroy = firmware_parser_destroy,
-+
-+	.get_smu_clock_info = bios_parser_get_smu_clock_info,
-+};
-+
-+static bool bios_parser_construct(
-+	struct bios_parser *bp,
-+	struct bp_init_data *init,
-+	enum dce_version dce_version)
-+{
-+	uint16_t *rom_header_offset = NULL;
-+	struct atom_rom_header_v2_2 *rom_header = NULL;
-+	struct display_object_info_table_v1_4 *object_info_tbl;
-+	struct atom_data_revision tbl_rev = {0};
-+
-+	if (!init)
-+		return false;
-+
-+	if (!init->bios)
-+		return false;
-+
-+	bp->base.funcs = &vbios_funcs;
-+	bp->base.bios = init->bios;
-+	bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
-+
-+	bp->base.ctx = init->ctx;
-+
-+	bp->base.bios_local_image = NULL;
-+
-+	rom_header_offset =
-+			GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
-+
-+	if (!rom_header_offset)
-+		return false;
-+
-+	rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
-+
-+	if (!rom_header)
-+		return false;
-+
-+	get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
-+	if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
-+		return false;
-+
-+	bp->master_data_tbl =
-+		GET_IMAGE(struct atom_master_data_table_v2_1,
-+				rom_header->masterdatatable_offset);
-+
-+	if (!bp->master_data_tbl)
-+		return false;
-+
-+	bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
-+
-+	if (!bp->object_info_tbl_offset)
-+		return false;
-+
-+	object_info_tbl =
-+			GET_IMAGE(struct display_object_info_table_v1_4,
-+						bp->object_info_tbl_offset);
-+
-+	if (!object_info_tbl)
-+		return false;
-+
-+	get_atom_data_table_revision(&object_info_tbl->table_header,
-+		&bp->object_info_tbl.revision);
-+
-+	if (bp->object_info_tbl.revision.major == 1
-+		&& bp->object_info_tbl.revision.minor >= 4) {
-+		struct display_object_info_table_v1_4 *tbl_v1_4;
-+
-+		tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
-+			bp->object_info_tbl_offset);
-+		if (!tbl_v1_4)
-+			return false;
-+
-+		bp->object_info_tbl.v1_4 = tbl_v1_4;
-+	} else
-+		return false;
-+
-+	dal_firmware_parser_init_cmd_tbl(bp);
-+	dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
-+
-+	bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
-+
-+	return true;
-+}
-+
-+struct dc_bios *firmware_parser_create(
-+	struct bp_init_data *init,
-+	enum dce_version dce_version)
-+{
-+	struct bios_parser *bp = NULL;
-+
-+	bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
-+	if (!bp)
-+		return NULL;
-+
-+	if (bios_parser_construct(bp, init, dce_version))
-+		return &bp->base;
-+
-+	kfree(bp);
-+	return NULL;
-+}
-+
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.h.0130~	2017-12-14 06:39:58.398903556 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.h	2017-12-14 06:39:58.398903556 +0100
-@@ -0,0 +1,33 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER2_H__
-+#define __DAL_BIOS_PARSER2_H__
-+
-+struct dc_bios *firmware_parser_create(
-+	struct bp_init_data *init,
-+	enum dce_version dce_version);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c.0130~	2017-12-14 06:39:58.399903556 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c	2017-12-14 06:39:58.399903556 +0100
-@@ -0,0 +1,3871 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "atom.h"
-+
-+#include "dc_bios_types.h"
-+#include "include/gpio_service_interface.h"
-+#include "include/grph_object_ctrl_defs.h"
-+#include "include/bios_parser_interface.h"
-+#include "include/i2caux_interface.h"
-+#include "include/logger_interface.h"
-+
-+#include "command_table.h"
-+#include "bios_parser_helper.h"
-+#include "command_table_helper.h"
-+#include "bios_parser.h"
-+#include "bios_parser_types_internal.h"
-+#include "bios_parser_interface.h"
-+
-+#include "bios_parser_common.h"
-+/* TODO remove - only needed for default i2c speed */
-+#include "dc.h"
-+
-+#define THREE_PERCENT_OF_10000 300
-+
-+#define LAST_RECORD_TYPE 0xff
-+
-+/* GUID to validate external display connection info table (aka OPM module) */
-+static const uint8_t ext_display_connection_guid[NUMBER_OF_UCHAR_FOR_GUID] = {
-+	0x91, 0x6E, 0x57, 0x09,
-+	0x3F, 0x6D, 0xD2, 0x11,
-+	0x39, 0x8E, 0x00, 0xA0,
-+	0xC9, 0x69, 0x72, 0x3B};
-+
-+#define DATA_TABLES(table) (bp->master_data_tbl->ListOfDataTables.table)
-+
-+static void get_atom_data_table_revision(
-+	ATOM_COMMON_TABLE_HEADER *atom_data_tbl,
-+	struct atom_data_revision *tbl_revision);
-+static uint32_t get_dst_number_from_object(struct bios_parser *bp,
-+	ATOM_OBJECT *object);
-+static uint32_t get_src_obj_list(struct bios_parser *bp, ATOM_OBJECT *object,
-+	uint16_t **id_list);
-+static uint32_t get_dest_obj_list(struct bios_parser *bp,
-+	ATOM_OBJECT *object, uint16_t **id_list);
-+static ATOM_OBJECT *get_bios_object(struct bios_parser *bp,
-+	struct graphics_object_id id);
-+static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
-+	ATOM_I2C_RECORD *record,
-+	struct graphics_object_i2c_info *info);
-+static ATOM_HPD_INT_RECORD *get_hpd_record(struct bios_parser *bp,
-+	ATOM_OBJECT *object);
-+static struct device_id device_type_from_device_id(uint16_t device_id);
-+static uint32_t signal_to_ss_id(enum as_signal_type signal);
-+static uint32_t get_support_mask_for_device_id(struct device_id device_id);
-+static ATOM_ENCODER_CAP_RECORD_V2 *get_encoder_cap_record(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *object);
-+
-+#define BIOS_IMAGE_SIZE_OFFSET 2
-+#define BIOS_IMAGE_SIZE_UNIT 512
-+
-+/*****************************************************************************/
-+static bool bios_parser_construct(
-+	struct bios_parser *bp,
-+	struct bp_init_data *init,
-+	enum dce_version dce_version);
-+
-+static uint8_t bios_parser_get_connectors_number(
-+	struct dc_bios *dcb);
-+
-+static enum bp_result bios_parser_get_embedded_panel_info(
-+	struct dc_bios *dcb,
-+	struct embedded_panel_info *info);
-+
-+/*****************************************************************************/
-+
-+struct dc_bios *bios_parser_create(
-+	struct bp_init_data *init,
-+	enum dce_version dce_version)
-+{
-+	struct bios_parser *bp = NULL;
-+
-+	bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
-+	if (!bp)
-+		return NULL;
-+
-+	if (bios_parser_construct(bp, init, dce_version))
-+		return &bp->base;
-+
-+	kfree(bp);
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
-+static void destruct(struct bios_parser *bp)
-+{
-+	kfree(bp->base.bios_local_image);
-+	kfree(bp->base.integrated_info);
-+}
-+
-+static void bios_parser_destroy(struct dc_bios **dcb)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(*dcb);
-+
-+	if (!bp) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	destruct(bp);
-+
-+	kfree(bp);
-+	*dcb = NULL;
-+}
-+
-+static uint8_t get_number_of_objects(struct bios_parser *bp, uint32_t offset)
-+{
-+	ATOM_OBJECT_TABLE *table;
-+
-+	uint32_t object_table_offset = bp->object_info_tbl_offset + offset;
-+
-+	table = GET_IMAGE(ATOM_OBJECT_TABLE, object_table_offset);
-+
-+	if (!table)
-+		return 0;
-+	else
-+		return table->ucNumberOfObjects;
-+}
-+
-+static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	return get_number_of_objects(bp,
-+		le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset));
-+}
-+
-+static struct graphics_object_id bios_parser_get_encoder_id(
-+	struct dc_bios *dcb,
-+	uint32_t i)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	struct graphics_object_id object_id = dal_graphics_object_id_init(
-+		0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
-+
-+	uint32_t encoder_table_offset = bp->object_info_tbl_offset
-+		+ le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset);
-+
-+	ATOM_OBJECT_TABLE *tbl =
-+		GET_IMAGE(ATOM_OBJECT_TABLE, encoder_table_offset);
-+
-+	if (tbl && tbl->ucNumberOfObjects > i) {
-+		const uint16_t id = le16_to_cpu(tbl->asObjects[i].usObjectID);
-+
-+		object_id = object_id_from_bios_object_id(id);
-+	}
-+
-+	return object_id;
-+}
-+
-+static struct graphics_object_id bios_parser_get_connector_id(
-+	struct dc_bios *dcb,
-+	uint8_t i)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	struct graphics_object_id object_id = dal_graphics_object_id_init(
-+		0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
-+
-+	uint32_t connector_table_offset = bp->object_info_tbl_offset
-+		+ le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+
-+	ATOM_OBJECT_TABLE *tbl =
-+		GET_IMAGE(ATOM_OBJECT_TABLE, connector_table_offset);
-+
-+	if (tbl && tbl->ucNumberOfObjects > i) {
-+		const uint16_t id = le16_to_cpu(tbl->asObjects[i].usObjectID);
-+
-+		object_id = object_id_from_bios_object_id(id);
-+	}
-+
-+	return object_id;
-+}
-+
-+static uint32_t bios_parser_get_dst_number(struct dc_bios *dcb,
-+	struct graphics_object_id id)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	ATOM_OBJECT *object = get_bios_object(bp, id);
-+
-+	return get_dst_number_from_object(bp, object);
-+}
-+
-+static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
-+	struct graphics_object_id object_id, uint32_t index,
-+	struct graphics_object_id *src_object_id)
-+{
-+	uint32_t number;
-+	uint16_t *id;
-+	ATOM_OBJECT *object;
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!src_object_id)
-+		return BP_RESULT_BADINPUT;
-+
-+	object = get_bios_object(bp, object_id);
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object id */
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	number = get_src_obj_list(bp, object, &id);
-+
-+	if (number <= index)
-+		return BP_RESULT_BADINPUT;
-+
-+	*src_object_id = object_id_from_bios_object_id(id[index]);
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result bios_parser_get_dst_obj(struct dc_bios *dcb,
-+	struct graphics_object_id object_id, uint32_t index,
-+	struct graphics_object_id *dest_object_id)
-+{
-+	uint32_t number;
-+	uint16_t *id;
-+	ATOM_OBJECT *object;
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!dest_object_id)
-+		return BP_RESULT_BADINPUT;
-+
-+	object = get_bios_object(bp, object_id);
-+
-+	number = get_dest_obj_list(bp, object, &id);
-+
-+	if (number <= index)
-+		return BP_RESULT_BADINPUT;
-+
-+	*dest_object_id = object_id_from_bios_object_id(id[index]);
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
-+	struct graphics_object_id id,
-+	struct graphics_object_i2c_info *info)
-+{
-+	uint32_t offset;
-+	ATOM_OBJECT *object;
-+	ATOM_COMMON_RECORD_HEADER *header;
-+	ATOM_I2C_RECORD *record;
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	object = get_bios_object(bp, id);
-+
-+	if (!object)
-+		return BP_RESULT_BADINPUT;
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!header)
-+			return BP_RESULT_BADBIOSTABLE;
-+
-+		if (LAST_RECORD_TYPE == header->ucRecordType ||
-+			!header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_I2C_RECORD_TYPE == header->ucRecordType
-+			&& sizeof(ATOM_I2C_RECORD) <= header->ucRecordSize) {
-+			/* get the I2C info */
-+			record = (ATOM_I2C_RECORD *) header;
-+
-+			if (get_gpio_i2c_info(bp, record, info) == BP_RESULT_OK)
-+				return BP_RESULT_OK;
-+		}
-+
-+		offset += header->ucRecordSize;
-+	}
-+
-+	return BP_RESULT_NORECORD;
-+}
-+
-+static enum bp_result get_voltage_ddc_info_v1(uint8_t *i2c_line,
-+	ATOM_COMMON_TABLE_HEADER *header,
-+	uint8_t *address)
-+{
-+	enum bp_result result = BP_RESULT_NORECORD;
-+	ATOM_VOLTAGE_OBJECT_INFO *info =
-+		(ATOM_VOLTAGE_OBJECT_INFO *) address;
-+
-+	uint8_t *voltage_current_object = (uint8_t *) &info->asVoltageObj[0];
-+
-+	while ((address + le16_to_cpu(header->usStructureSize)) > voltage_current_object) {
-+		ATOM_VOLTAGE_OBJECT *object =
-+			(ATOM_VOLTAGE_OBJECT *) voltage_current_object;
-+
-+		if ((object->ucVoltageType == SET_VOLTAGE_INIT_MODE) &&
-+			(object->ucVoltageType &
-+				VOLTAGE_CONTROLLED_BY_I2C_MASK)) {
-+
-+			*i2c_line = object->asControl.ucVoltageControlI2cLine
-+					^ 0x90;
-+			result = BP_RESULT_OK;
-+			break;
-+		}
-+
-+		voltage_current_object += object->ucSize;
-+	}
-+	return result;
-+}
-+
-+static enum bp_result get_voltage_ddc_info_v3(uint8_t *i2c_line,
-+	uint32_t index,
-+	ATOM_COMMON_TABLE_HEADER *header,
-+	uint8_t *address)
-+{
-+	enum bp_result result = BP_RESULT_NORECORD;
-+	ATOM_VOLTAGE_OBJECT_INFO_V3_1 *info =
-+		(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *) address;
-+
-+	uint8_t *voltage_current_object =
-+		(uint8_t *) (&(info->asVoltageObj[0]));
-+
-+	while ((address + le16_to_cpu(header->usStructureSize)) > voltage_current_object) {
-+		ATOM_I2C_VOLTAGE_OBJECT_V3 *object =
-+			(ATOM_I2C_VOLTAGE_OBJECT_V3 *) voltage_current_object;
-+
-+		if (object->sHeader.ucVoltageMode ==
-+			ATOM_INIT_VOLTAGE_REGULATOR) {
-+			if (object->sHeader.ucVoltageType == index) {
-+				*i2c_line = object->ucVoltageControlI2cLine
-+						^ 0x90;
-+				result = BP_RESULT_OK;
-+				break;
-+			}
-+		}
-+
-+		voltage_current_object += le16_to_cpu(object->sHeader.usSize);
-+	}
-+	return result;
-+}
-+
-+static enum bp_result bios_parser_get_thermal_ddc_info(
-+	struct dc_bios *dcb,
-+	uint32_t i2c_channel_id,
-+	struct graphics_object_i2c_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	ATOM_I2C_ID_CONFIG_ACCESS *config;
-+	ATOM_I2C_RECORD record;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	config = (ATOM_I2C_ID_CONFIG_ACCESS *) &i2c_channel_id;
-+
-+	record.sucI2cId.bfHW_Capable = config->sbfAccess.bfHW_Capable;
-+	record.sucI2cId.bfI2C_LineMux = config->sbfAccess.bfI2C_LineMux;
-+	record.sucI2cId.bfHW_EngineID = config->sbfAccess.bfHW_EngineID;
-+
-+	return get_gpio_i2c_info(bp, &record, info);
-+}
-+
-+static enum bp_result bios_parser_get_voltage_ddc_info(struct dc_bios *dcb,
-+	uint32_t index,
-+	struct graphics_object_i2c_info *info)
-+{
-+	uint8_t i2c_line = 0;
-+	enum bp_result result = BP_RESULT_NORECORD;
-+	uint8_t *voltage_info_address;
-+	ATOM_COMMON_TABLE_HEADER *header;
-+	struct atom_data_revision revision = {0};
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!DATA_TABLES(VoltageObjectInfo))
-+		return result;
-+
-+	voltage_info_address = bios_get_image(&bp->base, DATA_TABLES(VoltageObjectInfo), sizeof(ATOM_COMMON_TABLE_HEADER));
-+
-+	header = (ATOM_COMMON_TABLE_HEADER *) voltage_info_address;
-+
-+	get_atom_data_table_revision(header, &revision);
-+
-+	switch (revision.major) {
-+	case 1:
-+	case 2:
-+		result = get_voltage_ddc_info_v1(&i2c_line, header,
-+			voltage_info_address);
-+		break;
-+	case 3:
-+		if (revision.minor != 1)
-+			break;
-+		result = get_voltage_ddc_info_v3(&i2c_line, index, header,
-+			voltage_info_address);
-+		break;
-+	}
-+
-+	if (result == BP_RESULT_OK)
-+		result = bios_parser_get_thermal_ddc_info(dcb,
-+			i2c_line, info);
-+
-+	return result;
-+}
-+
-+/* TODO: temporary commented out to suppress 'defined but not used' warning */
-+#if 0
-+static enum bp_result bios_parser_get_ddc_info_for_i2c_line(
-+	struct bios_parser *bp,
-+	uint8_t i2c_line, struct graphics_object_i2c_info *info)
-+{
-+	uint32_t offset;
-+	ATOM_OBJECT *object;
-+	ATOM_OBJECT_TABLE *table;
-+	uint32_t i;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	offset = le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+
-+	offset += bp->object_info_tbl_offset;
-+
-+	table = GET_IMAGE(ATOM_OBJECT_TABLE, offset);
-+
-+	if (!table)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	for (i = 0; i < table->ucNumberOfObjects; i++) {
-+		object = &table->asObjects[i];
-+
-+		if (!object) {
-+			BREAK_TO_DEBUGGER(); /* Invalid object id */
-+			return BP_RESULT_BADINPUT;
-+		}
-+
-+		offset = le16_to_cpu(object->usRecordOffset)
-+				+ bp->object_info_tbl_offset;
-+
-+		for (;;) {
-+			ATOM_COMMON_RECORD_HEADER *header =
-+				GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+			if (!header)
-+				return BP_RESULT_BADBIOSTABLE;
-+
-+			offset += header->ucRecordSize;
-+
-+			if (LAST_RECORD_TYPE == header->ucRecordType ||
-+				!header->ucRecordSize)
-+				break;
-+
-+			if (ATOM_I2C_RECORD_TYPE == header->ucRecordType
-+				&& sizeof(ATOM_I2C_RECORD) <=
-+				header->ucRecordSize) {
-+				ATOM_I2C_RECORD *record =
-+					(ATOM_I2C_RECORD *) header;
-+
-+				if (i2c_line != record->sucI2cId.bfI2C_LineMux)
-+					continue;
-+
-+				/* get the I2C info */
-+				if (get_gpio_i2c_info(bp, record, info) ==
-+					BP_RESULT_OK)
-+					return BP_RESULT_OK;
-+			}
-+		}
-+	}
-+
-+	return BP_RESULT_NORECORD;
-+}
-+#endif
-+
-+static enum bp_result bios_parser_get_hpd_info(struct dc_bios *dcb,
-+	struct graphics_object_id id,
-+	struct graphics_object_hpd_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	ATOM_OBJECT *object;
-+	ATOM_HPD_INT_RECORD *record = NULL;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	object = get_bios_object(bp, id);
-+
-+	if (!object)
-+		return BP_RESULT_BADINPUT;
-+
-+	record = get_hpd_record(bp, object);
-+
-+	if (record != NULL) {
-+		info->hpd_int_gpio_uid = record->ucHPDIntGPIOID;
-+		info->hpd_active = record->ucPlugged_PinState;
-+		return BP_RESULT_OK;
-+	}
-+
-+	return BP_RESULT_NORECORD;
-+}
-+
-+static enum bp_result bios_parser_get_device_tag_record(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *object,
-+	ATOM_CONNECTOR_DEVICE_TAG_RECORD **record)
-+{
-+	ATOM_COMMON_RECORD_HEADER *header;
-+	uint32_t offset;
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!header)
-+			return BP_RESULT_BADBIOSTABLE;
-+
-+		offset += header->ucRecordSize;
-+
-+		if (LAST_RECORD_TYPE == header->ucRecordType ||
-+			!header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE !=
-+			header->ucRecordType)
-+			continue;
-+
-+		if (sizeof(ATOM_CONNECTOR_DEVICE_TAG) > header->ucRecordSize)
-+			continue;
-+
-+		*record = (ATOM_CONNECTOR_DEVICE_TAG_RECORD *) header;
-+		return BP_RESULT_OK;
-+	}
-+
-+	return BP_RESULT_NORECORD;
-+}
-+
-+static enum bp_result bios_parser_get_device_tag(
-+	struct dc_bios *dcb,
-+	struct graphics_object_id connector_object_id,
-+	uint32_t device_tag_index,
-+	struct connector_device_tag_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	ATOM_OBJECT *object;
-+	ATOM_CONNECTOR_DEVICE_TAG_RECORD *record = NULL;
-+	ATOM_CONNECTOR_DEVICE_TAG *device_tag;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	/* getBiosObject will return MXM object */
-+	object = get_bios_object(bp, connector_object_id);
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object id */
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	if (bios_parser_get_device_tag_record(bp, object, &record)
-+		!= BP_RESULT_OK)
-+		return BP_RESULT_NORECORD;
-+
-+	if (device_tag_index >= record->ucNumberOfDevice)
-+		return BP_RESULT_NORECORD;
-+
-+	device_tag = &record->asDeviceTag[device_tag_index];
-+
-+	info->acpi_device = le32_to_cpu(device_tag->ulACPIDeviceEnum);
-+	info->dev_id =
-+		device_type_from_device_id(le16_to_cpu(device_tag->usDeviceID));
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_firmware_info_v1_4(
-+	struct bios_parser *bp,
-+	struct dc_firmware_info *info);
-+static enum bp_result get_firmware_info_v2_1(
-+	struct bios_parser *bp,
-+	struct dc_firmware_info *info);
-+static enum bp_result get_firmware_info_v2_2(
-+	struct bios_parser *bp,
-+	struct dc_firmware_info *info);
-+
-+static enum bp_result bios_parser_get_firmware_info(
-+	struct dc_bios *dcb,
-+	struct dc_firmware_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	enum bp_result result = BP_RESULT_BADBIOSTABLE;
-+	ATOM_COMMON_TABLE_HEADER *header;
-+	struct atom_data_revision revision;
-+
-+	if (info && DATA_TABLES(FirmwareInfo)) {
-+		header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+			DATA_TABLES(FirmwareInfo));
-+		get_atom_data_table_revision(header, &revision);
-+		switch (revision.major) {
-+		case 1:
-+			switch (revision.minor) {
-+			case 4:
-+				result = get_firmware_info_v1_4(bp, info);
-+				break;
-+			default:
-+				break;
-+			}
-+			break;
-+
-+		case 2:
-+			switch (revision.minor) {
-+			case 1:
-+				result = get_firmware_info_v2_1(bp, info);
-+				break;
-+			case 2:
-+				result = get_firmware_info_v2_2(bp, info);
-+				break;
-+			default:
-+				break;
-+			}
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+static enum bp_result get_firmware_info_v1_4(
-+	struct bios_parser *bp,
-+	struct dc_firmware_info *info)
-+{
-+	ATOM_FIRMWARE_INFO_V1_4 *firmware_info =
-+		GET_IMAGE(ATOM_FIRMWARE_INFO_V1_4,
-+			DATA_TABLES(FirmwareInfo));
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	if (!firmware_info)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	memset(info, 0, sizeof(*info));
-+
-+	/* Pixel clock pll information. We need to convert from 10KHz units into
-+	 * KHz units */
-+	info->pll_info.crystal_frequency =
-+		le16_to_cpu(firmware_info->usReferenceClock) * 10;
-+	info->pll_info.min_input_pxl_clk_pll_frequency =
-+		le16_to_cpu(firmware_info->usMinPixelClockPLL_Input) * 10;
-+	info->pll_info.max_input_pxl_clk_pll_frequency =
-+		le16_to_cpu(firmware_info->usMaxPixelClockPLL_Input) * 10;
-+	info->pll_info.min_output_pxl_clk_pll_frequency =
-+		le32_to_cpu(firmware_info->ulMinPixelClockPLL_Output) * 10;
-+	info->pll_info.max_output_pxl_clk_pll_frequency =
-+		le32_to_cpu(firmware_info->ulMaxPixelClockPLL_Output) * 10;
-+
-+	if (firmware_info->usFirmwareCapability.sbfAccess.MemoryClockSS_Support)
-+		/* Since there is no information on the SS, report conservative
-+		 * value 3% for bandwidth calculation */
-+		/* unit of 0.01% */
-+		info->feature.memory_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+
-+	if (firmware_info->usFirmwareCapability.sbfAccess.EngineClockSS_Support)
-+		/* Since there is no information on the SS,report conservative
-+		 * value 3% for bandwidth calculation */
-+		/* unit of 0.01% */
-+		info->feature.engine_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_ss_info_v3_1(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	uint32_t index,
-+	struct spread_spectrum_info *ss_info);
-+
-+static enum bp_result get_firmware_info_v2_1(
-+	struct bios_parser *bp,
-+	struct dc_firmware_info *info)
-+{
-+	ATOM_FIRMWARE_INFO_V2_1 *firmwareInfo =
-+		GET_IMAGE(ATOM_FIRMWARE_INFO_V2_1, DATA_TABLES(FirmwareInfo));
-+	struct spread_spectrum_info internalSS;
-+	uint32_t index;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	if (!firmwareInfo)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	memset(info, 0, sizeof(*info));
-+
-+	/* Pixel clock pll information. We need to convert from 10KHz units into
-+	 * KHz units */
-+	info->pll_info.crystal_frequency =
-+		le16_to_cpu(firmwareInfo->usCoreReferenceClock) * 10;
-+	info->pll_info.min_input_pxl_clk_pll_frequency =
-+		le16_to_cpu(firmwareInfo->usMinPixelClockPLL_Input) * 10;
-+	info->pll_info.max_input_pxl_clk_pll_frequency =
-+		le16_to_cpu(firmwareInfo->usMaxPixelClockPLL_Input) * 10;
-+	info->pll_info.min_output_pxl_clk_pll_frequency =
-+		le32_to_cpu(firmwareInfo->ulMinPixelClockPLL_Output) * 10;
-+	info->pll_info.max_output_pxl_clk_pll_frequency =
-+		le32_to_cpu(firmwareInfo->ulMaxPixelClockPLL_Output) * 10;
-+	info->default_display_engine_pll_frequency =
-+		le32_to_cpu(firmwareInfo->ulDefaultDispEngineClkFreq) * 10;
-+	info->external_clock_source_frequency_for_dp =
-+		le16_to_cpu(firmwareInfo->usUniphyDPModeExtClkFreq) * 10;
-+	info->min_allowed_bl_level = firmwareInfo->ucMinAllowedBL_Level;
-+
-+	/* There should be only one entry in the SS info table for Memory Clock
-+	 */
-+	index = 0;
-+	if (firmwareInfo->usFirmwareCapability.sbfAccess.MemoryClockSS_Support)
-+		/* Since there is no information for external SS, report
-+		 *  conservative value 3% for bandwidth calculation */
-+		/* unit of 0.01% */
-+		info->feature.memory_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+	else if (get_ss_info_v3_1(bp,
-+		ASIC_INTERNAL_MEMORY_SS, index, &internalSS) == BP_RESULT_OK) {
-+		if (internalSS.spread_spectrum_percentage) {
-+			info->feature.memory_clk_ss_percentage =
-+				internalSS.spread_spectrum_percentage;
-+			if (internalSS.type.CENTER_MODE) {
-+				/* if it is centermode, the exact SS Percentage
-+				 * will be round up of half of the percentage
-+				 * reported in the SS table */
-+				++info->feature.memory_clk_ss_percentage;
-+				info->feature.memory_clk_ss_percentage /= 2;
-+			}
-+		}
-+	}
-+
-+	/* There should be only one entry in the SS info table for Engine Clock
-+	 */
-+	index = 1;
-+	if (firmwareInfo->usFirmwareCapability.sbfAccess.EngineClockSS_Support)
-+		/* Since there is no information for external SS, report
-+		 * conservative value 3% for bandwidth calculation */
-+		/* unit of 0.01% */
-+		info->feature.engine_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+	else if (get_ss_info_v3_1(bp,
-+		ASIC_INTERNAL_ENGINE_SS, index, &internalSS) == BP_RESULT_OK) {
-+		if (internalSS.spread_spectrum_percentage) {
-+			info->feature.engine_clk_ss_percentage =
-+				internalSS.spread_spectrum_percentage;
-+			if (internalSS.type.CENTER_MODE) {
-+				/* if it is centermode, the exact SS Percentage
-+				 * will be round up of half of the percentage
-+				 * reported in the SS table */
-+				++info->feature.engine_clk_ss_percentage;
-+				info->feature.engine_clk_ss_percentage /= 2;
-+			}
-+		}
-+	}
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_firmware_info_v2_2(
-+	struct bios_parser *bp,
-+	struct dc_firmware_info *info)
-+{
-+	ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
-+	struct spread_spectrum_info internal_ss;
-+	uint32_t index;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	firmware_info = GET_IMAGE(ATOM_FIRMWARE_INFO_V2_2,
-+		DATA_TABLES(FirmwareInfo));
-+
-+	if (!firmware_info)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	memset(info, 0, sizeof(*info));
-+
-+	/* Pixel clock pll information. We need to convert from 10KHz units into
-+	 * KHz units */
-+	info->pll_info.crystal_frequency =
-+		le16_to_cpu(firmware_info->usCoreReferenceClock) * 10;
-+	info->pll_info.min_input_pxl_clk_pll_frequency =
-+		le16_to_cpu(firmware_info->usMinPixelClockPLL_Input) * 10;
-+	info->pll_info.max_input_pxl_clk_pll_frequency =
-+		le16_to_cpu(firmware_info->usMaxPixelClockPLL_Input) * 10;
-+	info->pll_info.min_output_pxl_clk_pll_frequency =
-+		le32_to_cpu(firmware_info->ulMinPixelClockPLL_Output) * 10;
-+	info->pll_info.max_output_pxl_clk_pll_frequency =
-+		le32_to_cpu(firmware_info->ulMaxPixelClockPLL_Output) * 10;
-+	info->default_display_engine_pll_frequency =
-+		le32_to_cpu(firmware_info->ulDefaultDispEngineClkFreq) * 10;
-+	info->external_clock_source_frequency_for_dp =
-+		le16_to_cpu(firmware_info->usUniphyDPModeExtClkFreq) * 10;
-+
-+	/* There should be only one entry in the SS info table for Memory Clock
-+	 */
-+	index = 0;
-+	if (firmware_info->usFirmwareCapability.sbfAccess.MemoryClockSS_Support)
-+		/* Since there is no information for external SS, report
-+		 *  conservative value 3% for bandwidth calculation */
-+		/* unit of 0.01% */
-+		info->feature.memory_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+	else if (get_ss_info_v3_1(bp,
-+			ASIC_INTERNAL_MEMORY_SS, index, &internal_ss) == BP_RESULT_OK) {
-+		if (internal_ss.spread_spectrum_percentage) {
-+			info->feature.memory_clk_ss_percentage =
-+					internal_ss.spread_spectrum_percentage;
-+			if (internal_ss.type.CENTER_MODE) {
-+				/* if it is centermode, the exact SS Percentage
-+				 * will be round up of half of the percentage
-+				 * reported in the SS table */
-+				++info->feature.memory_clk_ss_percentage;
-+				info->feature.memory_clk_ss_percentage /= 2;
-+			}
-+		}
-+	}
-+
-+	/* There should be only one entry in the SS info table for Engine Clock
-+	 */
-+	index = 1;
-+	if (firmware_info->usFirmwareCapability.sbfAccess.EngineClockSS_Support)
-+		/* Since there is no information for external SS, report
-+		 * conservative value 3% for bandwidth calculation */
-+		/* unit of 0.01% */
-+		info->feature.engine_clk_ss_percentage = THREE_PERCENT_OF_10000;
-+	else if (get_ss_info_v3_1(bp,
-+			ASIC_INTERNAL_ENGINE_SS, index, &internal_ss) == BP_RESULT_OK) {
-+		if (internal_ss.spread_spectrum_percentage) {
-+			info->feature.engine_clk_ss_percentage =
-+					internal_ss.spread_spectrum_percentage;
-+			if (internal_ss.type.CENTER_MODE) {
-+				/* if it is centermode, the exact SS Percentage
-+				 * will be round up of half of the percentage
-+				 * reported in the SS table */
-+				++info->feature.engine_clk_ss_percentage;
-+				info->feature.engine_clk_ss_percentage /= 2;
-+			}
-+		}
-+	}
-+
-+	/* Remote Display */
-+	info->remote_display_config = firmware_info->ucRemoteDisplayConfig;
-+
-+	/* Is allowed minimum BL level */
-+	info->min_allowed_bl_level = firmware_info->ucMinAllowedBL_Level;
-+	/* Used starting from CI */
-+	info->smu_gpu_pll_output_freq =
-+			(uint32_t) (le32_to_cpu(firmware_info->ulGPUPLL_OutputFreq) * 10);
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_ss_info_v3_1(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	uint32_t index,
-+	struct spread_spectrum_info *ss_info)
-+{
-+	ATOM_ASIC_INTERNAL_SS_INFO_V3 *ss_table_header_include;
-+	ATOM_ASIC_SS_ASSIGNMENT_V3 *tbl;
-+	uint32_t table_size;
-+	uint32_t i;
-+	uint32_t table_index = 0;
-+
-+	if (!ss_info)
-+		return BP_RESULT_BADINPUT;
-+
-+	if (!DATA_TABLES(ASIC_InternalSS_Info))
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	ss_table_header_include = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V3,
-+		DATA_TABLES(ASIC_InternalSS_Info));
-+	table_size =
-+		(le16_to_cpu(ss_table_header_include->sHeader.usStructureSize)
-+				- sizeof(ATOM_COMMON_TABLE_HEADER))
-+				/ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
-+
-+	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V3 *)
-+				&ss_table_header_include->asSpreadSpectrum[0];
-+
-+	memset(ss_info, 0, sizeof(struct spread_spectrum_info));
-+
-+	for (i = 0; i < table_size; i++) {
-+		if (tbl[i].ucClockIndication != (uint8_t) id)
-+			continue;
-+
-+		if (table_index != index) {
-+			table_index++;
-+			continue;
-+		}
-+		/* VBIOS introduced new defines for Version 3, same values as
-+		 *  before, so now use these new ones for Version 3.
-+		 * Shouldn't affect field VBIOS's V3 as define values are still
-+		 *  same.
-+		 * #define SS_MODE_V3_CENTRE_SPREAD_MASK                0x01
-+		 * #define SS_MODE_V3_EXTERNAL_SS_MASK                  0x02
-+
-+		 * Old VBIOS defines:
-+		 * #define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
-+		 * #define ATOM_EXTERNAL_SS_MASK                  0x00000002
-+		 */
-+
-+		if (SS_MODE_V3_EXTERNAL_SS_MASK & tbl[i].ucSpreadSpectrumMode)
-+			ss_info->type.EXTERNAL = true;
-+
-+		if (SS_MODE_V3_CENTRE_SPREAD_MASK & tbl[i].ucSpreadSpectrumMode)
-+			ss_info->type.CENTER_MODE = true;
-+
-+		/* Older VBIOS (in field) always provides SS percentage in 0.01%
-+		 * units set Divider to 100 */
-+		ss_info->spread_percentage_divider = 100;
-+
-+		/* #define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 */
-+		if (SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK
-+				& tbl[i].ucSpreadSpectrumMode)
-+			ss_info->spread_percentage_divider = 1000;
-+
-+		ss_info->type.STEP_AND_DELAY_INFO = false;
-+		/* convert [10KHz] into [KHz] */
-+		ss_info->target_clock_range =
-+				le32_to_cpu(tbl[i].ulTargetClockRange) * 10;
-+		ss_info->spread_spectrum_percentage =
-+				(uint32_t)le16_to_cpu(tbl[i].usSpreadSpectrumPercentage);
-+		ss_info->spread_spectrum_range =
-+				(uint32_t)(le16_to_cpu(tbl[i].usSpreadRateIn10Hz) * 10);
-+
-+		return BP_RESULT_OK;
-+	}
-+	return BP_RESULT_NORECORD;
-+}
-+
-+static enum bp_result bios_parser_transmitter_control(
-+	struct dc_bios *dcb,
-+	struct bp_transmitter_control *cntl)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.transmitter_control)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.transmitter_control(bp, cntl);
-+}
-+
-+static enum bp_result bios_parser_encoder_control(
-+	struct dc_bios *dcb,
-+	struct bp_encoder_control *cntl)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.dig_encoder_control)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.dig_encoder_control(bp, cntl);
-+}
-+
-+static enum bp_result bios_parser_adjust_pixel_clock(
-+	struct dc_bios *dcb,
-+	struct bp_adjust_pixel_clock_parameters *bp_params)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.adjust_display_pll)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.adjust_display_pll(bp, bp_params);
-+}
-+
-+static enum bp_result bios_parser_set_pixel_clock(
-+	struct dc_bios *dcb,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.set_pixel_clock)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
-+}
-+
-+static enum bp_result bios_parser_set_dce_clock(
-+	struct dc_bios *dcb,
-+	struct bp_set_dce_clock_parameters *bp_params)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.set_dce_clock)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.set_dce_clock(bp, bp_params);
-+}
-+
-+static enum bp_result bios_parser_enable_spread_spectrum_on_ppll(
-+	struct dc_bios *dcb,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.enable_spread_spectrum_on_ppll)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.enable_spread_spectrum_on_ppll(
-+			bp, bp_params, enable);
-+
-+}
-+
-+static enum bp_result bios_parser_program_crtc_timing(
-+	struct dc_bios *dcb,
-+	struct bp_hw_crtc_timing_parameters *bp_params)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.set_crtc_timing)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
-+}
-+
-+static enum bp_result bios_parser_program_display_engine_pll(
-+	struct dc_bios *dcb,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.program_clock)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.program_clock(bp, bp_params);
-+
-+}
-+
-+
-+static enum bp_result bios_parser_enable_crtc(
-+	struct dc_bios *dcb,
-+	enum controller_id id,
-+	bool enable)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.enable_crtc)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.enable_crtc(bp, id, enable);
-+}
-+
-+static enum bp_result bios_parser_crtc_source_select(
-+	struct dc_bios *dcb,
-+	struct bp_crtc_source_select *bp_params)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.select_crtc_source)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.select_crtc_source(bp, bp_params);
-+}
-+
-+static enum bp_result bios_parser_enable_disp_power_gating(
-+	struct dc_bios *dcb,
-+	enum controller_id controller_id,
-+	enum bp_pipe_control_action action)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	if (!bp->cmd_tbl.enable_disp_power_gating)
-+		return BP_RESULT_FAILURE;
-+
-+	return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
-+		action);
-+}
-+
-+static bool bios_parser_is_device_id_supported(
-+	struct dc_bios *dcb,
-+	struct device_id id)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	uint32_t mask = get_support_mask_for_device_id(id);
-+
-+	return (le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport) & mask) != 0;
-+}
-+
-+static enum bp_result bios_parser_crt_control(
-+	struct dc_bios *dcb,
-+	enum engine_id engine_id,
-+	bool enable,
-+	uint32_t pixel_clock)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	uint8_t standard;
-+
-+	if (!bp->cmd_tbl.dac1_encoder_control &&
-+		engine_id == ENGINE_ID_DACA)
-+		return BP_RESULT_FAILURE;
-+	if (!bp->cmd_tbl.dac2_encoder_control &&
-+		engine_id == ENGINE_ID_DACB)
-+		return BP_RESULT_FAILURE;
-+	/* validate params */
-+	switch (engine_id) {
-+	case ENGINE_ID_DACA:
-+	case ENGINE_ID_DACB:
-+		break;
-+	default:
-+		/* unsupported engine */
-+		return BP_RESULT_FAILURE;
-+	}
-+
-+	standard = ATOM_DAC1_PS2; /* == ATOM_DAC2_PS2 */
-+
-+	if (enable) {
-+		if (engine_id == ENGINE_ID_DACA) {
-+			bp->cmd_tbl.dac1_encoder_control(bp, enable,
-+				pixel_clock, standard);
-+			if (bp->cmd_tbl.dac1_output_control != NULL)
-+				bp->cmd_tbl.dac1_output_control(bp, enable);
-+		} else {
-+			bp->cmd_tbl.dac2_encoder_control(bp, enable,
-+				pixel_clock, standard);
-+			if (bp->cmd_tbl.dac2_output_control != NULL)
-+				bp->cmd_tbl.dac2_output_control(bp, enable);
-+		}
-+	} else {
-+		if (engine_id == ENGINE_ID_DACA) {
-+			if (bp->cmd_tbl.dac1_output_control != NULL)
-+				bp->cmd_tbl.dac1_output_control(bp, enable);
-+			bp->cmd_tbl.dac1_encoder_control(bp, enable,
-+				pixel_clock, standard);
-+		} else {
-+			if (bp->cmd_tbl.dac2_output_control != NULL)
-+				bp->cmd_tbl.dac2_output_control(bp, enable);
-+			bp->cmd_tbl.dac2_encoder_control(bp, enable,
-+				pixel_clock, standard);
-+		}
-+	}
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static ATOM_HPD_INT_RECORD *get_hpd_record(struct bios_parser *bp,
-+	ATOM_OBJECT *object)
-+{
-+	ATOM_COMMON_RECORD_HEADER *header;
-+	uint32_t offset;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object */
-+		return NULL;
-+	}
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!header)
-+			return NULL;
-+
-+		if (LAST_RECORD_TYPE == header->ucRecordType ||
-+			!header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_HPD_INT_RECORD_TYPE == header->ucRecordType
-+			&& sizeof(ATOM_HPD_INT_RECORD) <= header->ucRecordSize)
-+			return (ATOM_HPD_INT_RECORD *) header;
-+
-+		offset += header->ucRecordSize;
-+	}
-+
-+	return NULL;
-+}
-+
-+/**
-+ * Get I2C information of input object id
-+ *
-+ * search all records to find the ATOM_I2C_RECORD_TYPE record IR
-+ */
-+static ATOM_I2C_RECORD *get_i2c_record(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *object)
-+{
-+	uint32_t offset;
-+	ATOM_COMMON_RECORD_HEADER *record_header;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER();
-+		/* Invalid object */
-+		return NULL;
-+	}
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+			+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		record_header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!record_header)
-+			return NULL;
-+
-+		if (LAST_RECORD_TYPE == record_header->ucRecordType ||
-+			0 == record_header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_I2C_RECORD_TYPE == record_header->ucRecordType &&
-+			sizeof(ATOM_I2C_RECORD) <=
-+			record_header->ucRecordSize) {
-+			return (ATOM_I2C_RECORD *)record_header;
-+		}
-+
-+		offset += record_header->ucRecordSize;
-+	}
-+
-+	return NULL;
-+}
-+
-+static enum bp_result get_ss_info_from_ss_info_table(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	struct spread_spectrum_info *ss_info);
-+static enum bp_result get_ss_info_from_tbl(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	struct spread_spectrum_info *ss_info);
-+/**
-+ * bios_parser_get_spread_spectrum_info
-+ * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
-+ * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
-+ * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info ver 3.1,
-+ * there is only one entry for each signal /ss id.  However, there is
-+ * no planning of supporting multiple spread Sprectum entry for EverGreen
-+ * @param [in] this
-+ * @param [in] signal, ASSignalType to be converted to info index
-+ * @param [in] index, number of entries that match the converted info index
-+ * @param [out] ss_info, sprectrum information structure,
-+ * @return Bios parser result code
-+ */
-+static enum bp_result bios_parser_get_spread_spectrum_info(
-+	struct dc_bios *dcb,
-+	enum as_signal_type signal,
-+	uint32_t index,
-+	struct spread_spectrum_info *ss_info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	enum bp_result result = BP_RESULT_UNSUPPORTED;
-+	uint32_t clk_id_ss = 0;
-+	ATOM_COMMON_TABLE_HEADER *header;
-+	struct atom_data_revision tbl_revision;
-+
-+	if (!ss_info) /* check for bad input */
-+		return BP_RESULT_BADINPUT;
-+	/* signal translation */
-+	clk_id_ss = signal_to_ss_id(signal);
-+
-+	if (!DATA_TABLES(ASIC_InternalSS_Info))
-+		if (!index)
-+			return get_ss_info_from_ss_info_table(bp, clk_id_ss,
-+				ss_info);
-+
-+	header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+		DATA_TABLES(ASIC_InternalSS_Info));
-+	get_atom_data_table_revision(header, &tbl_revision);
-+
-+	switch (tbl_revision.major) {
-+	case 2:
-+		switch (tbl_revision.minor) {
-+		case 1:
-+			/* there can not be more then one entry for Internal
-+			 * SS Info table version 2.1 */
-+			if (!index)
-+				return get_ss_info_from_tbl(bp, clk_id_ss,
-+						ss_info);
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+
-+	case 3:
-+		switch (tbl_revision.minor) {
-+		case 1:
-+			return get_ss_info_v3_1(bp, clk_id_ss, index, ss_info);
-+		default:
-+			break;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+	/* there can not be more then one entry for SS Info table */
-+	return result;
-+}
-+
-+static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	struct spread_spectrum_info *info);
-+
-+/**
-+ * get_ss_info_from_table
-+ * Get spread sprectrum information from the ASIC_InternalSS_Info Ver 2.1 or
-+ * SS_Info table from the VBIOS
-+ * There can not be more than 1 entry for  ASIC_InternalSS_Info Ver 2.1 or
-+ * SS_Info.
-+ *
-+ * @param this
-+ * @param id, spread sprectrum info index
-+ * @param pSSinfo, sprectrum information structure,
-+ * @return Bios parser result code
-+ */
-+static enum bp_result get_ss_info_from_tbl(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	struct spread_spectrum_info *ss_info)
-+{
-+	if (!ss_info) /* check for bad input, if ss_info is not NULL */
-+		return BP_RESULT_BADINPUT;
-+	/* for SS_Info table only support DP and LVDS */
-+	if (id == ASIC_INTERNAL_SS_ON_DP || id == ASIC_INTERNAL_SS_ON_LVDS)
-+		return get_ss_info_from_ss_info_table(bp, id, ss_info);
-+	else
-+		return get_ss_info_from_internal_ss_info_tbl_V2_1(bp, id,
-+			ss_info);
-+}
-+
-+/**
-+ * get_ss_info_from_internal_ss_info_tbl_V2_1
-+ * Get spread sprectrum information from the ASIC_InternalSS_Info table Ver 2.1
-+ * from the VBIOS
-+ * There will not be multiple entry for Ver 2.1
-+ *
-+ * @param id, spread sprectrum info index
-+ * @param pSSinfo, sprectrum information structure,
-+ * @return Bios parser result code
-+ */
-+static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	struct spread_spectrum_info *info)
-+{
-+	enum bp_result result = BP_RESULT_UNSUPPORTED;
-+	ATOM_ASIC_INTERNAL_SS_INFO_V2 *header;
-+	ATOM_ASIC_SS_ASSIGNMENT_V2 *tbl;
-+	uint32_t tbl_size, i;
-+
-+	if (!DATA_TABLES(ASIC_InternalSS_Info))
-+		return result;
-+
-+	header = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V2,
-+		DATA_TABLES(ASIC_InternalSS_Info));
-+
-+	memset(info, 0, sizeof(struct spread_spectrum_info));
-+
-+	tbl_size = (le16_to_cpu(header->sHeader.usStructureSize)
-+			- sizeof(ATOM_COMMON_TABLE_HEADER))
-+					/ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
-+
-+	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V2 *)
-+					&(header->asSpreadSpectrum[0]);
-+	for (i = 0; i < tbl_size; i++) {
-+		result = BP_RESULT_NORECORD;
-+
-+		if (tbl[i].ucClockIndication != (uint8_t)id)
-+			continue;
-+
-+		if (ATOM_EXTERNAL_SS_MASK
-+			& tbl[i].ucSpreadSpectrumMode) {
-+			info->type.EXTERNAL = true;
-+		}
-+		if (ATOM_SS_CENTRE_SPREAD_MODE_MASK
-+			& tbl[i].ucSpreadSpectrumMode) {
-+			info->type.CENTER_MODE = true;
-+		}
-+		info->type.STEP_AND_DELAY_INFO = false;
-+		/* convert [10KHz] into [KHz] */
-+		info->target_clock_range =
-+			le32_to_cpu(tbl[i].ulTargetClockRange) * 10;
-+		info->spread_spectrum_percentage =
-+			(uint32_t)le16_to_cpu(tbl[i].usSpreadSpectrumPercentage);
-+		info->spread_spectrum_range =
-+			(uint32_t)(le16_to_cpu(tbl[i].usSpreadRateIn10Hz) * 10);
-+		result = BP_RESULT_OK;
-+		break;
-+	}
-+
-+	return result;
-+
-+}
-+
-+/**
-+ * get_ss_info_from_ss_info_table
-+ * Get spread sprectrum information from the SS_Info table from the VBIOS
-+ * if the pointer to info is NULL, indicate the caller what to know the number
-+ * of entries that matches the id
-+ * for, the SS_Info table, there should not be more than 1 entry match.
-+ *
-+ * @param [in] id, spread sprectrum id
-+ * @param [out] pSSinfo, sprectrum information structure,
-+ * @return Bios parser result code
-+ */
-+static enum bp_result get_ss_info_from_ss_info_table(
-+	struct bios_parser *bp,
-+	uint32_t id,
-+	struct spread_spectrum_info *ss_info)
-+{
-+	enum bp_result result = BP_RESULT_UNSUPPORTED;
-+	ATOM_SPREAD_SPECTRUM_INFO *tbl;
-+	ATOM_COMMON_TABLE_HEADER *header;
-+	uint32_t table_size;
-+	uint32_t i;
-+	uint32_t id_local = SS_ID_UNKNOWN;
-+	struct atom_data_revision revision;
-+
-+	/* exist of the SS_Info table */
-+	/* check for bad input, pSSinfo can not be NULL */
-+	if (!DATA_TABLES(SS_Info) || !ss_info)
-+		return result;
-+
-+	header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER, DATA_TABLES(SS_Info));
-+	get_atom_data_table_revision(header, &revision);
-+
-+	tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO, DATA_TABLES(SS_Info));
-+
-+	if (1 != revision.major || 2 > revision.minor)
-+		return result;
-+
-+	/* have to convert from Internal_SS format to SS_Info format */
-+	switch (id) {
-+	case ASIC_INTERNAL_SS_ON_DP:
-+		id_local = SS_ID_DP1;
-+		break;
-+	case ASIC_INTERNAL_SS_ON_LVDS:
-+	{
-+		struct embedded_panel_info panel_info;
-+
-+		if (bios_parser_get_embedded_panel_info(&bp->base, &panel_info)
-+				== BP_RESULT_OK)
-+			id_local = panel_info.ss_id;
-+		break;
-+	}
-+	default:
-+		break;
-+	}
-+
-+	if (id_local == SS_ID_UNKNOWN)
-+		return result;
-+
-+	table_size = (le16_to_cpu(tbl->sHeader.usStructureSize) -
-+			sizeof(ATOM_COMMON_TABLE_HEADER)) /
-+					sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
-+
-+	for (i = 0; i < table_size; i++) {
-+		if (id_local != (uint32_t)tbl->asSS_Info[i].ucSS_Id)
-+			continue;
-+
-+		memset(ss_info, 0, sizeof(struct spread_spectrum_info));
-+
-+		if (ATOM_EXTERNAL_SS_MASK &
-+				tbl->asSS_Info[i].ucSpreadSpectrumType)
-+			ss_info->type.EXTERNAL = true;
-+
-+		if (ATOM_SS_CENTRE_SPREAD_MODE_MASK &
-+				tbl->asSS_Info[i].ucSpreadSpectrumType)
-+			ss_info->type.CENTER_MODE = true;
-+
-+		ss_info->type.STEP_AND_DELAY_INFO = true;
-+		ss_info->spread_spectrum_percentage =
-+			(uint32_t)le16_to_cpu(tbl->asSS_Info[i].usSpreadSpectrumPercentage);
-+		ss_info->step_and_delay_info.step = tbl->asSS_Info[i].ucSS_Step;
-+		ss_info->step_and_delay_info.delay =
-+			tbl->asSS_Info[i].ucSS_Delay;
-+		ss_info->step_and_delay_info.recommended_ref_div =
-+			tbl->asSS_Info[i].ucRecommendedRef_Div;
-+		ss_info->spread_spectrum_range =
-+			(uint32_t)tbl->asSS_Info[i].ucSS_Range * 10000;
-+
-+		/* there will be only one entry for each display type in SS_info
-+		 * table */
-+		result = BP_RESULT_OK;
-+		break;
-+	}
-+
-+	return result;
-+}
-+static enum bp_result get_embedded_panel_info_v1_2(
-+	struct bios_parser *bp,
-+	struct embedded_panel_info *info);
-+static enum bp_result get_embedded_panel_info_v1_3(
-+	struct bios_parser *bp,
-+	struct embedded_panel_info *info);
-+
-+static enum bp_result bios_parser_get_embedded_panel_info(
-+	struct dc_bios *dcb,
-+	struct embedded_panel_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	ATOM_COMMON_TABLE_HEADER *hdr;
-+
-+	if (!DATA_TABLES(LCD_Info))
-+		return BP_RESULT_FAILURE;
-+
-+	hdr = GET_IMAGE(ATOM_COMMON_TABLE_HEADER, DATA_TABLES(LCD_Info));
-+
-+	if (!hdr)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	switch (hdr->ucTableFormatRevision) {
-+	case 1:
-+		switch (hdr->ucTableContentRevision) {
-+		case 0:
-+		case 1:
-+		case 2:
-+			return get_embedded_panel_info_v1_2(bp, info);
-+		case 3:
-+			return get_embedded_panel_info_v1_3(bp, info);
-+		default:
-+			break;
-+		}
-+	default:
-+		break;
-+	}
-+
-+	return BP_RESULT_FAILURE;
-+}
-+
-+static enum bp_result get_embedded_panel_info_v1_2(
-+	struct bios_parser *bp,
-+	struct embedded_panel_info *info)
-+{
-+	ATOM_LVDS_INFO_V12 *lvds;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	if (!DATA_TABLES(LVDS_Info))
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	lvds =
-+		GET_IMAGE(ATOM_LVDS_INFO_V12, DATA_TABLES(LVDS_Info));
-+
-+	if (!lvds)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (1 != lvds->sHeader.ucTableFormatRevision
-+		|| 2 > lvds->sHeader.ucTableContentRevision)
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	memset(info, 0, sizeof(struct embedded_panel_info));
-+
-+	/* We need to convert from 10KHz units into KHz units*/
-+	info->lcd_timing.pixel_clk =
-+		le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10;
-+	/* usHActive does not include borders, according to VBIOS team*/
-+	info->lcd_timing.horizontal_addressable =
-+		le16_to_cpu(lvds->sLCDTiming.usHActive);
-+	/* usHBlanking_Time includes borders, so we should really be subtracting
-+	 * borders duing this translation, but LVDS generally*/
-+	/* doesn't have borders, so we should be okay leaving this as is for
-+	 * now.  May need to revisit if we ever have LVDS with borders*/
-+	info->lcd_timing.horizontal_blanking_time =
-+			le16_to_cpu(lvds->sLCDTiming.usHBlanking_Time);
-+	/* usVActive does not include borders, according to VBIOS team*/
-+	info->lcd_timing.vertical_addressable =
-+			le16_to_cpu(lvds->sLCDTiming.usVActive);
-+	/* usVBlanking_Time includes borders, so we should really be subtracting
-+	 * borders duing this translation, but LVDS generally*/
-+	/* doesn't have borders, so we should be okay leaving this as is for
-+	 * now. May need to revisit if we ever have LVDS with borders*/
-+	info->lcd_timing.vertical_blanking_time =
-+		le16_to_cpu(lvds->sLCDTiming.usVBlanking_Time);
-+	info->lcd_timing.horizontal_sync_offset =
-+		le16_to_cpu(lvds->sLCDTiming.usHSyncOffset);
-+	info->lcd_timing.horizontal_sync_width =
-+		le16_to_cpu(lvds->sLCDTiming.usHSyncWidth);
-+	info->lcd_timing.vertical_sync_offset =
-+		le16_to_cpu(lvds->sLCDTiming.usVSyncOffset);
-+	info->lcd_timing.vertical_sync_width =
-+		le16_to_cpu(lvds->sLCDTiming.usVSyncWidth);
-+	info->lcd_timing.horizontal_border = lvds->sLCDTiming.ucHBorder;
-+	info->lcd_timing.vertical_border = lvds->sLCDTiming.ucVBorder;
-+	info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HorizontalCutOff;
-+	info->lcd_timing.misc_info.H_SYNC_POLARITY =
-+		~(uint32_t)
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HSyncPolarity;
-+	info->lcd_timing.misc_info.V_SYNC_POLARITY =
-+		~(uint32_t)
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VSyncPolarity;
-+	info->lcd_timing.misc_info.VERTICAL_CUT_OFF =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VerticalCutOff;
-+	info->lcd_timing.misc_info.H_REPLICATION_BY2 =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.H_ReplicationBy2;
-+	info->lcd_timing.misc_info.V_REPLICATION_BY2 =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.V_ReplicationBy2;
-+	info->lcd_timing.misc_info.COMPOSITE_SYNC =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.CompositeSync;
-+	info->lcd_timing.misc_info.INTERLACE =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace;
-+	info->lcd_timing.misc_info.DOUBLE_CLOCK =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.DoubleClock;
-+	info->ss_id = lvds->ucSS_Id;
-+
-+	{
-+		uint8_t rr = le16_to_cpu(lvds->usSupportedRefreshRate);
-+		/* Get minimum supported refresh rate*/
-+		if (SUPPORTED_LCD_REFRESHRATE_30Hz & rr)
-+			info->supported_rr.REFRESH_RATE_30HZ = 1;
-+		else if (SUPPORTED_LCD_REFRESHRATE_40Hz & rr)
-+			info->supported_rr.REFRESH_RATE_40HZ = 1;
-+		else if (SUPPORTED_LCD_REFRESHRATE_48Hz & rr)
-+			info->supported_rr.REFRESH_RATE_48HZ = 1;
-+		else if (SUPPORTED_LCD_REFRESHRATE_50Hz & rr)
-+			info->supported_rr.REFRESH_RATE_50HZ = 1;
-+		else if (SUPPORTED_LCD_REFRESHRATE_60Hz & rr)
-+			info->supported_rr.REFRESH_RATE_60HZ = 1;
-+	}
-+
-+	/*Drr panel support can be reported by VBIOS*/
-+	if (LCDPANEL_CAP_DRR_SUPPORTED
-+			& lvds->ucLCDPanel_SpecialHandlingCap)
-+		info->drr_enabled = 1;
-+
-+	if (ATOM_PANEL_MISC_DUAL & lvds->ucLVDS_Misc)
-+		info->lcd_timing.misc_info.DOUBLE_CLOCK = true;
-+
-+	if (ATOM_PANEL_MISC_888RGB & lvds->ucLVDS_Misc)
-+		info->lcd_timing.misc_info.RGB888 = true;
-+
-+	info->lcd_timing.misc_info.GREY_LEVEL =
-+		(uint32_t) (ATOM_PANEL_MISC_GREY_LEVEL &
-+			lvds->ucLVDS_Misc) >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT;
-+
-+	if (ATOM_PANEL_MISC_SPATIAL & lvds->ucLVDS_Misc)
-+		info->lcd_timing.misc_info.SPATIAL = true;
-+
-+	if (ATOM_PANEL_MISC_TEMPORAL & lvds->ucLVDS_Misc)
-+		info->lcd_timing.misc_info.TEMPORAL = true;
-+
-+	if (ATOM_PANEL_MISC_API_ENABLED & lvds->ucLVDS_Misc)
-+		info->lcd_timing.misc_info.API_ENABLED = true;
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static enum bp_result get_embedded_panel_info_v1_3(
-+	struct bios_parser *bp,
-+	struct embedded_panel_info *info)
-+{
-+	ATOM_LCD_INFO_V13 *lvds;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	if (!DATA_TABLES(LCD_Info))
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	lvds = GET_IMAGE(ATOM_LCD_INFO_V13, DATA_TABLES(LCD_Info));
-+
-+	if (!lvds)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (!((1 == lvds->sHeader.ucTableFormatRevision)
-+			&& (3 <= lvds->sHeader.ucTableContentRevision)))
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	memset(info, 0, sizeof(struct embedded_panel_info));
-+
-+	/* We need to convert from 10KHz units into KHz units */
-+	info->lcd_timing.pixel_clk =
-+			le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10;
-+	/* usHActive does not include borders, according to VBIOS team */
-+	info->lcd_timing.horizontal_addressable =
-+			le16_to_cpu(lvds->sLCDTiming.usHActive);
-+	/* usHBlanking_Time includes borders, so we should really be subtracting
-+	 * borders duing this translation, but LVDS generally*/
-+	/* doesn't have borders, so we should be okay leaving this as is for
-+	 * now.  May need to revisit if we ever have LVDS with borders*/
-+	info->lcd_timing.horizontal_blanking_time =
-+		le16_to_cpu(lvds->sLCDTiming.usHBlanking_Time);
-+	/* usVActive does not include borders, according to VBIOS team*/
-+	info->lcd_timing.vertical_addressable =
-+		le16_to_cpu(lvds->sLCDTiming.usVActive);
-+	/* usVBlanking_Time includes borders, so we should really be subtracting
-+	 * borders duing this translation, but LVDS generally*/
-+	/* doesn't have borders, so we should be okay leaving this as is for
-+	 * now. May need to revisit if we ever have LVDS with borders*/
-+	info->lcd_timing.vertical_blanking_time =
-+		le16_to_cpu(lvds->sLCDTiming.usVBlanking_Time);
-+	info->lcd_timing.horizontal_sync_offset =
-+		le16_to_cpu(lvds->sLCDTiming.usHSyncOffset);
-+	info->lcd_timing.horizontal_sync_width =
-+		le16_to_cpu(lvds->sLCDTiming.usHSyncWidth);
-+	info->lcd_timing.vertical_sync_offset =
-+		le16_to_cpu(lvds->sLCDTiming.usVSyncOffset);
-+	info->lcd_timing.vertical_sync_width =
-+		le16_to_cpu(lvds->sLCDTiming.usVSyncWidth);
-+	info->lcd_timing.horizontal_border = lvds->sLCDTiming.ucHBorder;
-+	info->lcd_timing.vertical_border = lvds->sLCDTiming.ucVBorder;
-+	info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HorizontalCutOff;
-+	info->lcd_timing.misc_info.H_SYNC_POLARITY =
-+		~(uint32_t)
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HSyncPolarity;
-+	info->lcd_timing.misc_info.V_SYNC_POLARITY =
-+		~(uint32_t)
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VSyncPolarity;
-+	info->lcd_timing.misc_info.VERTICAL_CUT_OFF =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VerticalCutOff;
-+	info->lcd_timing.misc_info.H_REPLICATION_BY2 =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.H_ReplicationBy2;
-+	info->lcd_timing.misc_info.V_REPLICATION_BY2 =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.V_ReplicationBy2;
-+	info->lcd_timing.misc_info.COMPOSITE_SYNC =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.CompositeSync;
-+	info->lcd_timing.misc_info.INTERLACE =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace;
-+	info->lcd_timing.misc_info.DOUBLE_CLOCK =
-+		lvds->sLCDTiming.susModeMiscInfo.sbfAccess.DoubleClock;
-+	info->ss_id = lvds->ucSS_Id;
-+
-+	/* Drr panel support can be reported by VBIOS*/
-+	if (LCDPANEL_CAP_V13_DRR_SUPPORTED
-+			& lvds->ucLCDPanel_SpecialHandlingCap)
-+		info->drr_enabled = 1;
-+
-+	/* Get supported refresh rate*/
-+	if (info->drr_enabled == 1) {
-+		uint8_t min_rr =
-+				lvds->sRefreshRateSupport.ucMinRefreshRateForDRR;
-+		uint8_t rr = lvds->sRefreshRateSupport.ucSupportedRefreshRate;
-+
-+		if (min_rr != 0) {
-+			if (SUPPORTED_LCD_REFRESHRATE_30Hz & min_rr)
-+				info->supported_rr.REFRESH_RATE_30HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_40Hz & min_rr)
-+				info->supported_rr.REFRESH_RATE_40HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_48Hz & min_rr)
-+				info->supported_rr.REFRESH_RATE_48HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_50Hz & min_rr)
-+				info->supported_rr.REFRESH_RATE_50HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_60Hz & min_rr)
-+				info->supported_rr.REFRESH_RATE_60HZ = 1;
-+		} else {
-+			if (SUPPORTED_LCD_REFRESHRATE_30Hz & rr)
-+				info->supported_rr.REFRESH_RATE_30HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_40Hz & rr)
-+				info->supported_rr.REFRESH_RATE_40HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_48Hz & rr)
-+				info->supported_rr.REFRESH_RATE_48HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_50Hz & rr)
-+				info->supported_rr.REFRESH_RATE_50HZ = 1;
-+			else if (SUPPORTED_LCD_REFRESHRATE_60Hz & rr)
-+				info->supported_rr.REFRESH_RATE_60HZ = 1;
-+		}
-+	}
-+
-+	if (ATOM_PANEL_MISC_V13_DUAL & lvds->ucLCD_Misc)
-+		info->lcd_timing.misc_info.DOUBLE_CLOCK = true;
-+
-+	if (ATOM_PANEL_MISC_V13_8BIT_PER_COLOR & lvds->ucLCD_Misc)
-+		info->lcd_timing.misc_info.RGB888 = true;
-+
-+	info->lcd_timing.misc_info.GREY_LEVEL =
-+			(uint32_t) (ATOM_PANEL_MISC_V13_GREY_LEVEL &
-+				lvds->ucLCD_Misc) >> ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT;
-+
-+	return BP_RESULT_OK;
-+}
-+
-+/**
-+ * bios_parser_get_encoder_cap_info
-+ *
-+ * @brief
-+ *  Get encoder capability information of input object id
-+ *
-+ * @param object_id, Object id
-+ * @param object_id, encoder cap information structure
-+ *
-+ * @return Bios parser result code
-+ *
-+ */
-+static enum bp_result bios_parser_get_encoder_cap_info(
-+	struct dc_bios *dcb,
-+	struct graphics_object_id object_id,
-+	struct bp_encoder_cap_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	ATOM_OBJECT *object;
-+	ATOM_ENCODER_CAP_RECORD_V2 *record = NULL;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	object = get_bios_object(bp, object_id);
-+
-+	if (!object)
-+		return BP_RESULT_BADINPUT;
-+
-+	record = get_encoder_cap_record(bp, object);
-+	if (!record)
-+		return BP_RESULT_NORECORD;
-+
-+	info->DP_HBR2_EN = record->usHBR2En;
-+	info->DP_HBR3_EN = record->usHBR3En;
-+	info->HDMI_6GB_EN = record->usHDMI6GEn;
-+	return BP_RESULT_OK;
-+}
-+
-+/**
-+ * get_encoder_cap_record
-+ *
-+ * @brief
-+ *  Get encoder cap record for the object
-+ *
-+ * @param object, ATOM object
-+ *
-+ * @return atom encoder cap record
-+ *
-+ * @note
-+ *  search all records to find the ATOM_ENCODER_CAP_RECORD_V2 record
-+ */
-+static ATOM_ENCODER_CAP_RECORD_V2 *get_encoder_cap_record(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *object)
-+{
-+	ATOM_COMMON_RECORD_HEADER *header;
-+	uint32_t offset;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object */
-+		return NULL;
-+	}
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+					+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!header)
-+			return NULL;
-+
-+		offset += header->ucRecordSize;
-+
-+		if (LAST_RECORD_TYPE == header->ucRecordType ||
-+				!header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_ENCODER_CAP_RECORD_TYPE != header->ucRecordType)
-+			continue;
-+
-+		if (sizeof(ATOM_ENCODER_CAP_RECORD_V2) <= header->ucRecordSize)
-+			return (ATOM_ENCODER_CAP_RECORD_V2 *)header;
-+	}
-+
-+	return NULL;
-+}
-+
-+static uint32_t get_ss_entry_number(
-+	struct bios_parser *bp,
-+	uint32_t id);
-+static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(
-+	struct bios_parser *bp,
-+	uint32_t id);
-+static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
-+	struct bios_parser *bp,
-+	uint32_t id);
-+static uint32_t get_ss_entry_number_from_ss_info_tbl(
-+	struct bios_parser *bp,
-+	uint32_t id);
-+
-+/**
-+ * BiosParserObject::GetNumberofSpreadSpectrumEntry
-+ * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table from
-+ * the VBIOS that match the SSid (to be converted from signal)
-+ *
-+ * @param[in] signal, ASSignalType to be converted to SSid
-+ * @return number of SS Entry that match the signal
-+ */
-+static uint32_t bios_parser_get_ss_entry_number(
-+	struct dc_bios *dcb,
-+	enum as_signal_type signal)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	uint32_t ss_id = 0;
-+	ATOM_COMMON_TABLE_HEADER *header;
-+	struct atom_data_revision revision;
-+
-+	ss_id = signal_to_ss_id(signal);
-+
-+	if (!DATA_TABLES(ASIC_InternalSS_Info))
-+		return get_ss_entry_number_from_ss_info_tbl(bp, ss_id);
-+
-+	header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+			DATA_TABLES(ASIC_InternalSS_Info));
-+	get_atom_data_table_revision(header, &revision);
-+
-+	switch (revision.major) {
-+	case 2:
-+		switch (revision.minor) {
-+		case 1:
-+			return get_ss_entry_number(bp, ss_id);
-+		default:
-+			break;
-+		}
-+		break;
-+	case 3:
-+		switch (revision.minor) {
-+		case 1:
-+			return
-+				get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
-+						bp, ss_id);
-+		default:
-+			break;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * get_ss_entry_number_from_ss_info_tbl
-+ * Get Number of spread spectrum entry from the SS_Info table from the VBIOS.
-+ *
-+ * @note There can only be one entry for each id for SS_Info Table
-+ *
-+ * @param [in] id, spread spectrum id
-+ * @return number of SS Entry that match the id
-+ */
-+static uint32_t get_ss_entry_number_from_ss_info_tbl(
-+	struct bios_parser *bp,
-+	uint32_t id)
-+{
-+	ATOM_SPREAD_SPECTRUM_INFO *tbl;
-+	ATOM_COMMON_TABLE_HEADER *header;
-+	uint32_t table_size;
-+	uint32_t i;
-+	uint32_t number = 0;
-+	uint32_t id_local = SS_ID_UNKNOWN;
-+	struct atom_data_revision revision;
-+
-+	/* SS_Info table exist */
-+	if (!DATA_TABLES(SS_Info))
-+		return number;
-+
-+	header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+			DATA_TABLES(SS_Info));
-+	get_atom_data_table_revision(header, &revision);
-+
-+	tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO,
-+			DATA_TABLES(SS_Info));
-+
-+	if (1 != revision.major || 2 > revision.minor)
-+		return number;
-+
-+	/* have to convert from Internal_SS format to SS_Info format */
-+	switch (id) {
-+	case ASIC_INTERNAL_SS_ON_DP:
-+		id_local = SS_ID_DP1;
-+		break;
-+	case ASIC_INTERNAL_SS_ON_LVDS: {
-+		struct embedded_panel_info panel_info;
-+
-+		if (bios_parser_get_embedded_panel_info(&bp->base, &panel_info)
-+				== BP_RESULT_OK)
-+			id_local = panel_info.ss_id;
-+		break;
-+	}
-+	default:
-+		break;
-+	}
-+
-+	if (id_local == SS_ID_UNKNOWN)
-+		return number;
-+
-+	table_size = (le16_to_cpu(tbl->sHeader.usStructureSize) -
-+			sizeof(ATOM_COMMON_TABLE_HEADER)) /
-+					sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
-+
-+	for (i = 0; i < table_size; i++)
-+		if (id_local == (uint32_t)tbl->asSS_Info[i].ucSS_Id) {
-+			number = 1;
-+			break;
-+		}
-+
-+	return number;
-+}
-+
-+/**
-+ * get_ss_entry_number
-+ * Get spread sprectrum information from the ASIC_InternalSS_Info Ver 2.1 or
-+ * SS_Info table from the VBIOS
-+ * There can not be more than 1 entry for  ASIC_InternalSS_Info Ver 2.1 or
-+ * SS_Info.
-+ *
-+ * @param id, spread sprectrum info index
-+ * @return Bios parser result code
-+ */
-+static uint32_t get_ss_entry_number(struct bios_parser *bp, uint32_t id)
-+{
-+	if (id == ASIC_INTERNAL_SS_ON_DP || id == ASIC_INTERNAL_SS_ON_LVDS)
-+		return get_ss_entry_number_from_ss_info_tbl(bp, id);
-+
-+	return get_ss_entry_number_from_internal_ss_info_tbl_v2_1(bp, id);
-+}
-+
-+/**
-+ * get_ss_entry_number_from_internal_ss_info_tbl_v2_1
-+ * Get NUmber of spread sprectrum entry from the ASIC_InternalSS_Info table
-+ * Ver 2.1 from the VBIOS
-+ * There will not be multiple entry for Ver 2.1
-+ *
-+ * @param id, spread sprectrum info index
-+ * @return number of SS Entry that match the id
-+ */
-+static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1(
-+	struct bios_parser *bp,
-+	uint32_t id)
-+{
-+	ATOM_ASIC_INTERNAL_SS_INFO_V2 *header_include;
-+	ATOM_ASIC_SS_ASSIGNMENT_V2 *tbl;
-+	uint32_t size;
-+	uint32_t i;
-+
-+	if (!DATA_TABLES(ASIC_InternalSS_Info))
-+		return 0;
-+
-+	header_include = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V2,
-+			DATA_TABLES(ASIC_InternalSS_Info));
-+
-+	size = (le16_to_cpu(header_include->sHeader.usStructureSize)
-+			- sizeof(ATOM_COMMON_TABLE_HEADER))
-+						/ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
-+
-+	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V2 *)
-+				&header_include->asSpreadSpectrum[0];
-+	for (i = 0; i < size; i++)
-+		if (tbl[i].ucClockIndication == (uint8_t)id)
-+			return 1;
-+
-+	return 0;
-+}
-+/**
-+ * get_ss_entry_number_from_internal_ss_info_table_V3_1
-+ * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table of
-+ * the VBIOS that matches id
-+ *
-+ * @param[in]  id, spread sprectrum id
-+ * @return number of SS Entry that match the id
-+ */
-+static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1(
-+	struct bios_parser *bp,
-+	uint32_t id)
-+{
-+	uint32_t number = 0;
-+	ATOM_ASIC_INTERNAL_SS_INFO_V3 *header_include;
-+	ATOM_ASIC_SS_ASSIGNMENT_V3 *tbl;
-+	uint32_t size;
-+	uint32_t i;
-+
-+	if (!DATA_TABLES(ASIC_InternalSS_Info))
-+		return number;
-+
-+	header_include = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V3,
-+			DATA_TABLES(ASIC_InternalSS_Info));
-+	size = (le16_to_cpu(header_include->sHeader.usStructureSize) -
-+			sizeof(ATOM_COMMON_TABLE_HEADER)) /
-+					sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
-+
-+	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V3 *)
-+				&header_include->asSpreadSpectrum[0];
-+
-+	for (i = 0; i < size; i++)
-+		if (tbl[i].ucClockIndication == (uint8_t)id)
-+			number++;
-+
-+	return number;
-+}
-+
-+/**
-+ * bios_parser_get_gpio_pin_info
-+ * Get GpioPin information of input gpio id
-+ *
-+ * @param gpio_id, GPIO ID
-+ * @param info, GpioPin information structure
-+ * @return Bios parser result code
-+ * @note
-+ *  to get the GPIO PIN INFO, we need:
-+ *  1. get the GPIO_ID from other object table, see GetHPDInfo()
-+ *  2. in DATA_TABLE.GPIO_Pin_LUT, search all records, to get the registerA
-+ *  offset/mask
-+ */
-+static enum bp_result bios_parser_get_gpio_pin_info(
-+	struct dc_bios *dcb,
-+	uint32_t gpio_id,
-+	struct gpio_pin_info *info)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	ATOM_GPIO_PIN_LUT *header;
-+	uint32_t count = 0;
-+	uint32_t i = 0;
-+
-+	if (!DATA_TABLES(GPIO_Pin_LUT))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	header = GET_IMAGE(ATOM_GPIO_PIN_LUT, DATA_TABLES(GPIO_Pin_LUT));
-+	if (!header)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (sizeof(ATOM_COMMON_TABLE_HEADER) + sizeof(ATOM_GPIO_PIN_LUT)
-+			> le16_to_cpu(header->sHeader.usStructureSize))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (1 != header->sHeader.ucTableContentRevision)
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	count = (le16_to_cpu(header->sHeader.usStructureSize)
-+			- sizeof(ATOM_COMMON_TABLE_HEADER))
-+				/ sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
-+	for (i = 0; i < count; ++i) {
-+		if (header->asGPIO_Pin[i].ucGPIO_ID != gpio_id)
-+			continue;
-+
-+		info->offset =
-+			(uint32_t) le16_to_cpu(header->asGPIO_Pin[i].usGpioPin_AIndex);
-+		info->offset_y = info->offset + 2;
-+		info->offset_en = info->offset + 1;
-+		info->offset_mask = info->offset - 1;
-+
-+		info->mask = (uint32_t) (1 <<
-+			header->asGPIO_Pin[i].ucGpioPinBitShift);
-+		info->mask_y = info->mask + 2;
-+		info->mask_en = info->mask + 1;
-+		info->mask_mask = info->mask - 1;
-+
-+		return BP_RESULT_OK;
-+	}
-+
-+	return BP_RESULT_NORECORD;
-+}
-+
-+static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
-+	ATOM_I2C_RECORD *record,
-+	struct graphics_object_i2c_info *info)
-+{
-+	ATOM_GPIO_I2C_INFO *header;
-+	uint32_t count = 0;
-+
-+	if (!info)
-+		return BP_RESULT_BADINPUT;
-+
-+	/* get the GPIO_I2C info */
-+	if (!DATA_TABLES(GPIO_I2C_Info))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	header = GET_IMAGE(ATOM_GPIO_I2C_INFO, DATA_TABLES(GPIO_I2C_Info));
-+	if (!header)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (sizeof(ATOM_COMMON_TABLE_HEADER) + sizeof(ATOM_GPIO_I2C_ASSIGMENT)
-+			> le16_to_cpu(header->sHeader.usStructureSize))
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	if (1 != header->sHeader.ucTableContentRevision)
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	/* get data count */
-+	count = (le16_to_cpu(header->sHeader.usStructureSize)
-+			- sizeof(ATOM_COMMON_TABLE_HEADER))
-+				/ sizeof(ATOM_GPIO_I2C_ASSIGMENT);
-+	if (count < record->sucI2cId.bfI2C_LineMux)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	/* get the GPIO_I2C_INFO */
-+	info->i2c_hw_assist = record->sucI2cId.bfHW_Capable;
-+	info->i2c_line = record->sucI2cId.bfI2C_LineMux;
-+	info->i2c_engine_id = record->sucI2cId.bfHW_EngineID;
-+	info->i2c_slave_address = record->ucI2CAddr;
-+
-+	info->gpio_info.clk_mask_register_index =
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkMaskRegisterIndex);
-+	info->gpio_info.clk_en_register_index =
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkEnRegisterIndex);
-+	info->gpio_info.clk_y_register_index =
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkY_RegisterIndex);
-+	info->gpio_info.clk_a_register_index =
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkA_RegisterIndex);
-+	info->gpio_info.data_mask_register_index =
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataMaskRegisterIndex);
-+	info->gpio_info.data_en_register_index =
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataEnRegisterIndex);
-+	info->gpio_info.data_y_register_index =
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataY_RegisterIndex);
-+	info->gpio_info.data_a_register_index =
-+			le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataA_RegisterIndex);
-+
-+	info->gpio_info.clk_mask_shift =
-+			header->asGPIO_Info[info->i2c_line].ucClkMaskShift;
-+	info->gpio_info.clk_en_shift =
-+			header->asGPIO_Info[info->i2c_line].ucClkEnShift;
-+	info->gpio_info.clk_y_shift =
-+			header->asGPIO_Info[info->i2c_line].ucClkY_Shift;
-+	info->gpio_info.clk_a_shift =
-+			header->asGPIO_Info[info->i2c_line].ucClkA_Shift;
-+	info->gpio_info.data_mask_shift =
-+			header->asGPIO_Info[info->i2c_line].ucDataMaskShift;
-+	info->gpio_info.data_en_shift =
-+			header->asGPIO_Info[info->i2c_line].ucDataEnShift;
-+	info->gpio_info.data_y_shift =
-+			header->asGPIO_Info[info->i2c_line].ucDataY_Shift;
-+	info->gpio_info.data_a_shift =
-+			header->asGPIO_Info[info->i2c_line].ucDataA_Shift;
-+
-+	return BP_RESULT_OK;
-+}
-+
-+static ATOM_OBJECT *get_bios_object(struct bios_parser *bp,
-+	struct graphics_object_id id)
-+{
-+	uint32_t offset;
-+	ATOM_OBJECT_TABLE *tbl;
-+	uint32_t i;
-+
-+	switch (id.type) {
-+	case OBJECT_TYPE_ENCODER:
-+		offset = le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset);
-+		break;
-+
-+	case OBJECT_TYPE_CONNECTOR:
-+		offset = le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+		break;
-+
-+	case OBJECT_TYPE_ROUTER:
-+		offset = le16_to_cpu(bp->object_info_tbl.v1_1->usRouterObjectTableOffset);
-+		break;
-+
-+	case OBJECT_TYPE_GENERIC:
-+		if (bp->object_info_tbl.revision.minor < 3)
-+			return NULL;
-+		offset = le16_to_cpu(bp->object_info_tbl.v1_3->usMiscObjectTableOffset);
-+		break;
-+
-+	default:
-+		return NULL;
-+	}
-+
-+	offset += bp->object_info_tbl_offset;
-+
-+	tbl = GET_IMAGE(ATOM_OBJECT_TABLE, offset);
-+	if (!tbl)
-+		return NULL;
-+
-+	for (i = 0; i < tbl->ucNumberOfObjects; i++)
-+		if (dal_graphics_object_id_is_equal(id,
-+				object_id_from_bios_object_id(
-+						le16_to_cpu(tbl->asObjects[i].usObjectID))))
-+			return &tbl->asObjects[i];
-+
-+	return NULL;
-+}
-+
-+static uint32_t get_dest_obj_list(struct bios_parser *bp,
-+	ATOM_OBJECT *object, uint16_t **id_list)
-+{
-+	uint32_t offset;
-+	uint8_t *number;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object id */
-+		return 0;
-+	}
-+
-+	offset = le16_to_cpu(object->usSrcDstTableOffset)
-+						+ bp->object_info_tbl_offset;
-+
-+	number = GET_IMAGE(uint8_t, offset);
-+	if (!number)
-+		return 0;
-+
-+	offset += sizeof(uint8_t);
-+	offset += sizeof(uint16_t) * (*number);
-+
-+	number = GET_IMAGE(uint8_t, offset);
-+	if ((!number) || (!*number))
-+		return 0;
-+
-+	offset += sizeof(uint8_t);
-+	*id_list = (uint16_t *)bios_get_image(&bp->base, offset, *number * sizeof(uint16_t));
-+
-+	if (!*id_list)
-+		return 0;
-+
-+	return *number;
-+}
-+
-+static uint32_t get_src_obj_list(struct bios_parser *bp, ATOM_OBJECT *object,
-+	uint16_t **id_list)
-+{
-+	uint32_t offset;
-+	uint8_t *number;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid object id */
-+		return 0;
-+	}
-+
-+	offset = le16_to_cpu(object->usSrcDstTableOffset)
-+					+ bp->object_info_tbl_offset;
-+
-+	number = GET_IMAGE(uint8_t, offset);
-+	if (!number)
-+		return 0;
-+
-+	offset += sizeof(uint8_t);
-+	*id_list = (uint16_t *)bios_get_image(&bp->base, offset, *number * sizeof(uint16_t));
-+
-+	if (!*id_list)
-+		return 0;
-+
-+	return *number;
-+}
-+
-+static uint32_t get_dst_number_from_object(struct bios_parser *bp,
-+	ATOM_OBJECT *object)
-+{
-+	uint32_t offset;
-+	uint8_t *number;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER(); /* Invalid encoder object id*/
-+		return 0;
-+	}
-+
-+	offset = le16_to_cpu(object->usSrcDstTableOffset)
-+					+ bp->object_info_tbl_offset;
-+
-+	number = GET_IMAGE(uint8_t, offset);
-+	if (!number)
-+		return 0;
-+
-+	offset += sizeof(uint8_t);
-+	offset += sizeof(uint16_t) * (*number);
-+
-+	number = GET_IMAGE(uint8_t, offset);
-+
-+	if (!number)
-+		return 0;
-+
-+	return *number;
-+}
-+
-+static struct device_id device_type_from_device_id(uint16_t device_id)
-+{
-+
-+	struct device_id result_device_id;
-+
-+	switch (device_id) {
-+	case ATOM_DEVICE_LCD1_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_LCD;
-+		result_device_id.enum_id = 1;
-+		break;
-+
-+	case ATOM_DEVICE_LCD2_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_LCD;
-+		result_device_id.enum_id = 2;
-+		break;
-+
-+	case ATOM_DEVICE_CRT1_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_CRT;
-+		result_device_id.enum_id = 1;
-+		break;
-+
-+	case ATOM_DEVICE_CRT2_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_CRT;
-+		result_device_id.enum_id = 2;
-+		break;
-+
-+	case ATOM_DEVICE_DFP1_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 1;
-+		break;
-+
-+	case ATOM_DEVICE_DFP2_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 2;
-+		break;
-+
-+	case ATOM_DEVICE_DFP3_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 3;
-+		break;
-+
-+	case ATOM_DEVICE_DFP4_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 4;
-+		break;
-+
-+	case ATOM_DEVICE_DFP5_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 5;
-+		break;
-+
-+	case ATOM_DEVICE_DFP6_SUPPORT:
-+		result_device_id.device_type = DEVICE_TYPE_DFP;
-+		result_device_id.enum_id = 6;
-+		break;
-+
-+	default:
-+		BREAK_TO_DEBUGGER(); /* Invalid device Id */
-+		result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
-+		result_device_id.enum_id = 0;
-+	}
-+	return result_device_id;
-+}
-+
-+static void get_atom_data_table_revision(
-+	ATOM_COMMON_TABLE_HEADER *atom_data_tbl,
-+	struct atom_data_revision *tbl_revision)
-+{
-+	if (!tbl_revision)
-+		return;
-+
-+	/* initialize the revision to 0 which is invalid revision */
-+	tbl_revision->major = 0;
-+	tbl_revision->minor = 0;
-+
-+	if (!atom_data_tbl)
-+		return;
-+
-+	tbl_revision->major =
-+			(uint32_t) GET_DATA_TABLE_MAJOR_REVISION(atom_data_tbl);
-+	tbl_revision->minor =
-+			(uint32_t) GET_DATA_TABLE_MINOR_REVISION(atom_data_tbl);
-+}
-+
-+static uint32_t signal_to_ss_id(enum as_signal_type signal)
-+{
-+	uint32_t clk_id_ss = 0;
-+
-+	switch (signal) {
-+	case AS_SIGNAL_TYPE_DVI:
-+		clk_id_ss = ASIC_INTERNAL_SS_ON_TMDS;
-+		break;
-+	case AS_SIGNAL_TYPE_HDMI:
-+		clk_id_ss = ASIC_INTERNAL_SS_ON_HDMI;
-+		break;
-+	case AS_SIGNAL_TYPE_LVDS:
-+		clk_id_ss = ASIC_INTERNAL_SS_ON_LVDS;
-+		break;
-+	case AS_SIGNAL_TYPE_DISPLAY_PORT:
-+		clk_id_ss = ASIC_INTERNAL_SS_ON_DP;
-+		break;
-+	case AS_SIGNAL_TYPE_GPU_PLL:
-+		clk_id_ss = ASIC_INTERNAL_GPUPLL_SS;
-+		break;
-+	default:
-+		break;
-+	}
-+	return clk_id_ss;
-+}
-+
-+static uint32_t get_support_mask_for_device_id(struct device_id device_id)
-+{
-+	enum dal_device_type device_type = device_id.device_type;
-+	uint32_t enum_id = device_id.enum_id;
-+
-+	switch (device_type) {
-+	case DEVICE_TYPE_LCD:
-+		switch (enum_id) {
-+		case 1:
-+			return ATOM_DEVICE_LCD1_SUPPORT;
-+		case 2:
-+			return ATOM_DEVICE_LCD2_SUPPORT;
-+		default:
-+			break;
-+		}
-+		break;
-+	case DEVICE_TYPE_CRT:
-+		switch (enum_id) {
-+		case 1:
-+			return ATOM_DEVICE_CRT1_SUPPORT;
-+		case 2:
-+			return ATOM_DEVICE_CRT2_SUPPORT;
-+		default:
-+			break;
-+		}
-+		break;
-+	case DEVICE_TYPE_DFP:
-+		switch (enum_id) {
-+		case 1:
-+			return ATOM_DEVICE_DFP1_SUPPORT;
-+		case 2:
-+			return ATOM_DEVICE_DFP2_SUPPORT;
-+		case 3:
-+			return ATOM_DEVICE_DFP3_SUPPORT;
-+		case 4:
-+			return ATOM_DEVICE_DFP4_SUPPORT;
-+		case 5:
-+			return ATOM_DEVICE_DFP5_SUPPORT;
-+		case 6:
-+			return ATOM_DEVICE_DFP6_SUPPORT;
-+		default:
-+			break;
-+		}
-+		break;
-+	case DEVICE_TYPE_CV:
-+		switch (enum_id) {
-+		case 1:
-+			return ATOM_DEVICE_CV_SUPPORT;
-+		default:
-+			break;
-+		}
-+		break;
-+	case DEVICE_TYPE_TV:
-+		switch (enum_id) {
-+		case 1:
-+			return ATOM_DEVICE_TV1_SUPPORT;
-+		default:
-+			break;
-+		}
-+		break;
-+	default:
-+		break;
-+	};
-+
-+	/* Unidentified device ID, return empty support mask. */
-+	return 0;
-+}
-+
-+/**
-+ *  HwContext interface for writing MM registers
-+ */
-+
-+static bool i2c_read(
-+	struct bios_parser *bp,
-+	struct graphics_object_i2c_info *i2c_info,
-+	uint8_t *buffer,
-+	uint32_t length)
-+{
-+	struct ddc *ddc;
-+	uint8_t offset[2] = { 0, 0 };
-+	bool result = false;
-+	struct i2c_command cmd;
-+	struct gpio_ddc_hw_info hw_info = {
-+		i2c_info->i2c_hw_assist,
-+		i2c_info->i2c_line };
-+
-+	ddc = dal_gpio_create_ddc(bp->base.ctx->gpio_service,
-+		i2c_info->gpio_info.clk_a_register_index,
-+		(1 << i2c_info->gpio_info.clk_a_shift), &hw_info);
-+
-+	if (!ddc)
-+		return result;
-+
-+	/*Using SW engine */
-+	cmd.engine = I2C_COMMAND_ENGINE_SW;
-+	cmd.speed = ddc->ctx->dc->caps.i2c_speed_in_khz;
-+
-+	{
-+		struct i2c_payload payloads[] = {
-+				{
-+						.address = i2c_info->i2c_slave_address >> 1,
-+						.data = offset,
-+						.length = sizeof(offset),
-+						.write = true
-+				},
-+				{
-+						.address = i2c_info->i2c_slave_address >> 1,
-+						.data = buffer,
-+						.length = length,
-+						.write = false
-+				}
-+		};
-+
-+		cmd.payloads = payloads;
-+		cmd.number_of_payloads = ARRAY_SIZE(payloads);
-+
-+		/* TODO route this through drm i2c_adapter */
-+		result = dal_i2caux_submit_i2c_command(
-+				ddc->ctx->i2caux,
-+				ddc,
-+				&cmd);
-+	}
-+
-+	dal_gpio_destroy_ddc(&ddc);
-+
-+	return result;
-+}
-+
-+/**
-+ * Read external display connection info table through i2c.
-+ * validate the GUID and checksum.
-+ *
-+ * @return enum bp_result whether all data was sucessfully read
-+ */
-+static enum bp_result get_ext_display_connection_info(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *opm_object,
-+	ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO *ext_display_connection_info_tbl)
-+{
-+	bool config_tbl_present = false;
-+	ATOM_I2C_RECORD *i2c_record = NULL;
-+	uint32_t i = 0;
-+
-+	if (opm_object == NULL)
-+		return BP_RESULT_BADINPUT;
-+
-+	i2c_record = get_i2c_record(bp, opm_object);
-+
-+	if (i2c_record != NULL) {
-+		ATOM_GPIO_I2C_INFO *gpio_i2c_header;
-+		struct graphics_object_i2c_info i2c_info;
-+
-+		gpio_i2c_header = GET_IMAGE(ATOM_GPIO_I2C_INFO,
-+				bp->master_data_tbl->ListOfDataTables.GPIO_I2C_Info);
-+
-+		if (NULL == gpio_i2c_header)
-+			return BP_RESULT_BADBIOSTABLE;
-+
-+		if (get_gpio_i2c_info(bp, i2c_record, &i2c_info) !=
-+				BP_RESULT_OK)
-+			return BP_RESULT_BADBIOSTABLE;
-+
-+		if (i2c_read(bp,
-+			     &i2c_info,
-+			     (uint8_t *)ext_display_connection_info_tbl,
-+			     sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO))) {
-+			config_tbl_present = true;
-+		}
-+	}
-+
-+	/* Validate GUID */
-+	if (config_tbl_present)
-+		for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; i++) {
-+			if (ext_display_connection_info_tbl->ucGuid[i]
-+			    != ext_display_connection_guid[i]) {
-+				config_tbl_present = false;
-+				break;
-+			}
-+		}
-+
-+	/* Validate checksum */
-+	if (config_tbl_present) {
-+		uint8_t check_sum = 0;
-+		uint8_t *buf =
-+				(uint8_t *)ext_display_connection_info_tbl;
-+
-+		for (i = 0; i < sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
-+				i++) {
-+			check_sum += buf[i];
-+		}
-+
-+		if (check_sum != 0)
-+			config_tbl_present = false;
-+	}
-+
-+	if (config_tbl_present)
-+		return BP_RESULT_OK;
-+	else
-+		return BP_RESULT_FAILURE;
-+}
-+
-+/*
-+ * Gets the first device ID in the same group as the given ID for enumerating.
-+ * For instance, if any DFP device ID is passed, returns the device ID for DFP1.
-+ *
-+ * The first device ID in the same group as the passed device ID, or 0 if no
-+ * matching device group found.
-+ */
-+static uint32_t enum_first_device_id(uint32_t dev_id)
-+{
-+	/* Return the first in the group that this ID belongs to. */
-+	if (dev_id & ATOM_DEVICE_CRT_SUPPORT)
-+		return ATOM_DEVICE_CRT1_SUPPORT;
-+	else if (dev_id & ATOM_DEVICE_DFP_SUPPORT)
-+		return ATOM_DEVICE_DFP1_SUPPORT;
-+	else if (dev_id & ATOM_DEVICE_LCD_SUPPORT)
-+		return ATOM_DEVICE_LCD1_SUPPORT;
-+	else if (dev_id & ATOM_DEVICE_TV_SUPPORT)
-+		return ATOM_DEVICE_TV1_SUPPORT;
-+	else if (dev_id & ATOM_DEVICE_CV_SUPPORT)
-+		return ATOM_DEVICE_CV_SUPPORT;
-+
-+	/* No group found for this device ID. */
-+
-+	dm_error("%s: incorrect input %d\n", __func__, dev_id);
-+	/* No matching support flag for given device ID */
-+	return 0;
-+}
-+
-+/*
-+ * Gets the next device ID in the group for a given device ID.
-+ *
-+ * The current device ID being enumerated on.
-+ *
-+ * The next device ID in the group, or 0 if no device exists.
-+ */
-+static uint32_t enum_next_dev_id(uint32_t dev_id)
-+{
-+	/* Get next device ID in the group. */
-+	switch (dev_id) {
-+	case ATOM_DEVICE_CRT1_SUPPORT:
-+		return ATOM_DEVICE_CRT2_SUPPORT;
-+	case ATOM_DEVICE_LCD1_SUPPORT:
-+		return ATOM_DEVICE_LCD2_SUPPORT;
-+	case ATOM_DEVICE_DFP1_SUPPORT:
-+		return ATOM_DEVICE_DFP2_SUPPORT;
-+	case ATOM_DEVICE_DFP2_SUPPORT:
-+		return ATOM_DEVICE_DFP3_SUPPORT;
-+	case ATOM_DEVICE_DFP3_SUPPORT:
-+		return ATOM_DEVICE_DFP4_SUPPORT;
-+	case ATOM_DEVICE_DFP4_SUPPORT:
-+		return ATOM_DEVICE_DFP5_SUPPORT;
-+	case ATOM_DEVICE_DFP5_SUPPORT:
-+		return ATOM_DEVICE_DFP6_SUPPORT;
-+	}
-+
-+	/* Done enumerating through devices. */
-+	return 0;
-+}
-+
-+/*
-+ * Returns the new device tag record for patched BIOS object.
-+ *
-+ * [IN] pExtDisplayPath - External display path to copy device tag from.
-+ * [IN] deviceSupport - Bit vector for device ID support flags.
-+ * [OUT] pDeviceTag - Device tag structure to fill with patched data.
-+ *
-+ * True if a compatible device ID was found, false otherwise.
-+ */
-+static bool get_patched_device_tag(
-+	struct bios_parser *bp,
-+	EXT_DISPLAY_PATH *ext_display_path,
-+	uint32_t device_support,
-+	ATOM_CONNECTOR_DEVICE_TAG *device_tag)
-+{
-+	uint32_t dev_id;
-+	/* Use fallback behaviour if not supported. */
-+	if (!bp->remap_device_tags) {
-+		device_tag->ulACPIDeviceEnum =
-+				cpu_to_le32((uint32_t) le16_to_cpu(ext_display_path->usDeviceACPIEnum));
-+		device_tag->usDeviceID =
-+				cpu_to_le16(le16_to_cpu(ext_display_path->usDeviceTag));
-+		return true;
-+	}
-+
-+	/* Find the first unused in the same group. */
-+	dev_id = enum_first_device_id(le16_to_cpu(ext_display_path->usDeviceTag));
-+	while (dev_id != 0) {
-+		/* Assign this device ID if supported. */
-+		if ((device_support & dev_id) != 0) {
-+			device_tag->ulACPIDeviceEnum =
-+					cpu_to_le32((uint32_t) le16_to_cpu(ext_display_path->usDeviceACPIEnum));
-+			device_tag->usDeviceID = cpu_to_le16((USHORT) dev_id);
-+			return true;
-+		}
-+
-+		dev_id = enum_next_dev_id(dev_id);
-+	}
-+
-+	/* No compatible device ID found. */
-+	return false;
-+}
-+
-+/*
-+ * Adds a device tag to a BIOS object's device tag record if there is
-+ * matching device ID supported.
-+ *
-+ * pObject - Pointer to the BIOS object to add the device tag to.
-+ * pExtDisplayPath - Display path to retrieve base device ID from.
-+ * pDeviceSupport - Pointer to bit vector for supported device IDs.
-+ */
-+static void add_device_tag_from_ext_display_path(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *object,
-+	EXT_DISPLAY_PATH *ext_display_path,
-+	uint32_t *device_support)
-+{
-+	/* Get device tag record for object. */
-+	ATOM_CONNECTOR_DEVICE_TAG *device_tag = NULL;
-+	ATOM_CONNECTOR_DEVICE_TAG_RECORD *device_tag_record = NULL;
-+	enum bp_result result =
-+			bios_parser_get_device_tag_record(
-+					bp, object, &device_tag_record);
-+
-+	if ((le16_to_cpu(ext_display_path->usDeviceTag) != CONNECTOR_OBJECT_ID_NONE)
-+			&& (result == BP_RESULT_OK)) {
-+		uint8_t index;
-+
-+		if ((device_tag_record->ucNumberOfDevice == 1) &&
-+				(le16_to_cpu(device_tag_record->asDeviceTag[0].usDeviceID) == 0)) {
-+			/*Workaround bug in current VBIOS releases where
-+			 * ucNumberOfDevice = 1 but there is no actual device
-+			 * tag data. This w/a is temporary until the updated
-+			 * VBIOS is distributed. */
-+			device_tag_record->ucNumberOfDevice =
-+					device_tag_record->ucNumberOfDevice - 1;
-+		}
-+
-+		/* Attempt to find a matching device ID. */
-+		index = device_tag_record->ucNumberOfDevice;
-+		device_tag = &device_tag_record->asDeviceTag[index];
-+		if (get_patched_device_tag(
-+				bp,
-+				ext_display_path,
-+				*device_support,
-+				device_tag)) {
-+			/* Update cached device support to remove assigned ID.
-+			 */
-+			*device_support &= ~le16_to_cpu(device_tag->usDeviceID);
-+			device_tag_record->ucNumberOfDevice++;
-+		}
-+	}
-+}
-+
-+/*
-+ * Read out a single EXT_DISPLAY_PATH from the external display connection info
-+ * table. The specific entry in the table is determined by the enum_id passed
-+ * in.
-+ *
-+ * EXT_DISPLAY_PATH describing a single Configuration table entry
-+ */
-+
-+#define INVALID_CONNECTOR 0xffff
-+
-+static EXT_DISPLAY_PATH *get_ext_display_path_entry(
-+	ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO *config_table,
-+	uint32_t bios_object_id)
-+{
-+	EXT_DISPLAY_PATH *ext_display_path;
-+	uint32_t ext_display_path_index =
-+			((bios_object_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT) - 1;
-+
-+	if (ext_display_path_index >= MAX_NUMBER_OF_EXT_DISPLAY_PATH)
-+		return NULL;
-+
-+	ext_display_path = &config_table->sPath[ext_display_path_index];
-+
-+	if (le16_to_cpu(ext_display_path->usDeviceConnector) == INVALID_CONNECTOR)
-+		ext_display_path->usDeviceConnector = cpu_to_le16(0);
-+
-+	return ext_display_path;
-+}
-+
-+/*
-+ * Get AUX/DDC information of input object id
-+ *
-+ * search all records to find the ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE record
-+ * IR
-+ */
-+static ATOM_CONNECTOR_AUXDDC_LUT_RECORD *get_ext_connector_aux_ddc_lut_record(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *object)
-+{
-+	uint32_t offset;
-+	ATOM_COMMON_RECORD_HEADER *header;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER();
-+		/* Invalid object */
-+		return NULL;
-+	}
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+					+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!header)
-+			return NULL;
-+
-+		if (LAST_RECORD_TYPE == header->ucRecordType ||
-+				0 == header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE ==
-+				header->ucRecordType &&
-+				sizeof(ATOM_CONNECTOR_AUXDDC_LUT_RECORD) <=
-+				header->ucRecordSize)
-+			return (ATOM_CONNECTOR_AUXDDC_LUT_RECORD *)(header);
-+
-+		offset += header->ucRecordSize;
-+	}
-+
-+	return NULL;
-+}
-+
-+/*
-+ * Get AUX/DDC information of input object id
-+ *
-+ * search all records to find the ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE record
-+ * IR
-+ */
-+static ATOM_CONNECTOR_HPDPIN_LUT_RECORD *get_ext_connector_hpd_pin_lut_record(
-+	struct bios_parser *bp,
-+	ATOM_OBJECT *object)
-+{
-+	uint32_t offset;
-+	ATOM_COMMON_RECORD_HEADER *header;
-+
-+	if (!object) {
-+		BREAK_TO_DEBUGGER();
-+		/* Invalid object */
-+		return NULL;
-+	}
-+
-+	offset = le16_to_cpu(object->usRecordOffset)
-+					+ bp->object_info_tbl_offset;
-+
-+	for (;;) {
-+		header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset);
-+
-+		if (!header)
-+			return NULL;
-+
-+		if (LAST_RECORD_TYPE == header->ucRecordType ||
-+				0 == header->ucRecordSize)
-+			break;
-+
-+		if (ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE ==
-+				header->ucRecordType &&
-+				sizeof(ATOM_CONNECTOR_HPDPIN_LUT_RECORD) <=
-+				header->ucRecordSize)
-+			return (ATOM_CONNECTOR_HPDPIN_LUT_RECORD *)header;
-+
-+		offset += header->ucRecordSize;
-+	}
-+
-+	return NULL;
-+}
-+
-+/*
-+ * Check whether we need to patch the VBIOS connector info table with
-+ * data from an external display connection info table.  This is
-+ * necessary to support MXM boards with an OPM (output personality
-+ * module).  With these designs, the VBIOS connector info table
-+ * specifies an MXM_CONNECTOR with a unique ID.  The driver retrieves
-+ * the external connection info table through i2c and then looks up the
-+ * connector ID to find the real connector type (e.g. DFP1).
-+ *
-+ */
-+static enum bp_result patch_bios_image_from_ext_display_connection_info(
-+	struct bios_parser *bp)
-+{
-+	ATOM_OBJECT_TABLE *connector_tbl;
-+	uint32_t connector_tbl_offset;
-+	struct graphics_object_id object_id;
-+	ATOM_OBJECT *object;
-+	ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO ext_display_connection_info_tbl;
-+	EXT_DISPLAY_PATH *ext_display_path;
-+	ATOM_CONNECTOR_AUXDDC_LUT_RECORD *aux_ddc_lut_record = NULL;
-+	ATOM_I2C_RECORD *i2c_record = NULL;
-+	ATOM_CONNECTOR_HPDPIN_LUT_RECORD *hpd_pin_lut_record = NULL;
-+	ATOM_HPD_INT_RECORD *hpd_record = NULL;
-+	ATOM_OBJECT_TABLE *encoder_table;
-+	uint32_t encoder_table_offset;
-+	ATOM_OBJECT *opm_object = NULL;
-+	uint32_t i = 0;
-+	struct graphics_object_id opm_object_id =
-+			dal_graphics_object_id_init(
-+					GENERIC_ID_MXM_OPM,
-+					ENUM_ID_1,
-+					OBJECT_TYPE_GENERIC);
-+	ATOM_CONNECTOR_DEVICE_TAG_RECORD *dev_tag_record;
-+	uint32_t cached_device_support =
-+			le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport);
-+
-+	uint32_t dst_number;
-+	uint16_t *dst_object_id_list;
-+
-+	opm_object = get_bios_object(bp, opm_object_id);
-+	if (!opm_object)
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	memset(&ext_display_connection_info_tbl, 0,
-+			sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO));
-+
-+	connector_tbl_offset = bp->object_info_tbl_offset
-+			+ le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+	connector_tbl = GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
-+
-+	/* Read Connector info table from EEPROM through i2c */
-+	if (get_ext_display_connection_info(bp,
-+					    opm_object,
-+					    &ext_display_connection_info_tbl) != BP_RESULT_OK) {
-+
-+		dm_logger_write(bp->base.ctx->logger, LOG_WARNING,
-+				"%s: Failed to read Connection Info Table", __func__);
-+		return BP_RESULT_UNSUPPORTED;
-+	}
-+
-+	/* Get pointer to AUX/DDC and HPD LUTs */
-+	aux_ddc_lut_record =
-+			get_ext_connector_aux_ddc_lut_record(bp, opm_object);
-+	hpd_pin_lut_record =
-+			get_ext_connector_hpd_pin_lut_record(bp, opm_object);
-+
-+	if ((aux_ddc_lut_record == NULL) || (hpd_pin_lut_record == NULL))
-+		return BP_RESULT_UNSUPPORTED;
-+
-+	/* Cache support bits for currently unmapped device types. */
-+	if (bp->remap_device_tags) {
-+		for (i = 0; i < connector_tbl->ucNumberOfObjects; ++i) {
-+			uint32_t j;
-+			/* Remove support for all non-MXM connectors. */
-+			object = &connector_tbl->asObjects[i];
-+			object_id = object_id_from_bios_object_id(
-+					le16_to_cpu(object->usObjectID));
-+			if ((OBJECT_TYPE_CONNECTOR != object_id.type) ||
-+					(CONNECTOR_ID_MXM == object_id.id))
-+				continue;
-+
-+			/* Remove support for all device tags. */
-+			if (bios_parser_get_device_tag_record(
-+					bp, object, &dev_tag_record) != BP_RESULT_OK)
-+				continue;
-+
-+			for (j = 0; j < dev_tag_record->ucNumberOfDevice; ++j) {
-+				ATOM_CONNECTOR_DEVICE_TAG *device_tag =
-+						&dev_tag_record->asDeviceTag[j];
-+				cached_device_support &=
-+						~le16_to_cpu(device_tag->usDeviceID);
-+			}
-+		}
-+	}
-+
-+	/* Find all MXM connector objects and patch them with connector info
-+	 * from the external display connection info table. */
-+	for (i = 0; i < connector_tbl->ucNumberOfObjects; i++) {
-+		uint32_t j;
-+
-+		object = &connector_tbl->asObjects[i];
-+		object_id = object_id_from_bios_object_id(le16_to_cpu(object->usObjectID));
-+		if ((OBJECT_TYPE_CONNECTOR != object_id.type) ||
-+				(CONNECTOR_ID_MXM != object_id.id))
-+			continue;
-+
-+		/* Get the correct connection info table entry based on the enum
-+		 * id. */
-+		ext_display_path = get_ext_display_path_entry(
-+				&ext_display_connection_info_tbl,
-+				le16_to_cpu(object->usObjectID));
-+		if (!ext_display_path)
-+			return BP_RESULT_FAILURE;
-+
-+		/* Patch device connector ID */
-+		object->usObjectID =
-+				cpu_to_le16(le16_to_cpu(ext_display_path->usDeviceConnector));
-+
-+		/* Patch device tag, ulACPIDeviceEnum. */
-+		add_device_tag_from_ext_display_path(
-+				bp,
-+				object,
-+				ext_display_path,
-+				&cached_device_support);
-+
-+		/* Patch HPD info */
-+		if (ext_display_path->ucExtHPDPINLutIndex <
-+				MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES) {
-+			hpd_record = get_hpd_record(bp, object);
-+			if (hpd_record) {
-+				uint8_t index =
-+						ext_display_path->ucExtHPDPINLutIndex;
-+				hpd_record->ucHPDIntGPIOID =
-+						hpd_pin_lut_record->ucHPDPINMap[index];
-+			} else {
-+				BREAK_TO_DEBUGGER();
-+				/* Invalid hpd record */
-+				return BP_RESULT_FAILURE;
-+			}
-+		}
-+
-+		/* Patch I2C/AUX info */
-+		if (ext_display_path->ucExtHPDPINLutIndex <
-+				MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES) {
-+			i2c_record = get_i2c_record(bp, object);
-+			if (i2c_record) {
-+				uint8_t index =
-+						ext_display_path->ucExtAUXDDCLutIndex;
-+				i2c_record->sucI2cId =
-+						aux_ddc_lut_record->ucAUXDDCMap[index];
-+			} else {
-+				BREAK_TO_DEBUGGER();
-+				/* Invalid I2C record */
-+				return BP_RESULT_FAILURE;
-+			}
-+		}
-+
-+		/* Merge with other MXM connectors that map to the same physical
-+		 * connector. */
-+		for (j = i + 1;
-+				j < connector_tbl->ucNumberOfObjects; j++) {
-+			ATOM_OBJECT *next_object;
-+			struct graphics_object_id next_object_id;
-+			EXT_DISPLAY_PATH *next_ext_display_path;
-+
-+			next_object = &connector_tbl->asObjects[j];
-+			next_object_id = object_id_from_bios_object_id(
-+					le16_to_cpu(next_object->usObjectID));
-+
-+			if ((OBJECT_TYPE_CONNECTOR != next_object_id.type) &&
-+					(CONNECTOR_ID_MXM == next_object_id.id))
-+				continue;
-+
-+			next_ext_display_path = get_ext_display_path_entry(
-+					&ext_display_connection_info_tbl,
-+					le16_to_cpu(next_object->usObjectID));
-+
-+			if (next_ext_display_path == NULL)
-+				return BP_RESULT_FAILURE;
-+
-+			/* Merge if using same connector. */
-+			if ((le16_to_cpu(next_ext_display_path->usDeviceConnector) ==
-+					le16_to_cpu(ext_display_path->usDeviceConnector)) &&
-+					(le16_to_cpu(ext_display_path->usDeviceConnector) != 0)) {
-+				/* Clear duplicate connector from table. */
-+				next_object->usObjectID = cpu_to_le16(0);
-+				add_device_tag_from_ext_display_path(
-+						bp,
-+						object,
-+						ext_display_path,
-+						&cached_device_support);
-+			}
-+		}
-+	}
-+
-+	/* Find all encoders which have an MXM object as their destination.
-+	 *  Replace the MXM object with the real connector Id from the external
-+	 *  display connection info table */
-+
-+	encoder_table_offset = bp->object_info_tbl_offset
-+			+ le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset);
-+	encoder_table = GET_IMAGE(ATOM_OBJECT_TABLE, encoder_table_offset);
-+
-+	for (i = 0; i < encoder_table->ucNumberOfObjects; i++) {
-+		uint32_t j;
-+
-+		object = &encoder_table->asObjects[i];
-+
-+		dst_number = get_dest_obj_list(bp, object, &dst_object_id_list);
-+
-+		for (j = 0; j < dst_number; j++) {
-+			object_id = object_id_from_bios_object_id(
-+					dst_object_id_list[j]);
-+
-+			if ((OBJECT_TYPE_CONNECTOR != object_id.type) ||
-+					(CONNECTOR_ID_MXM != object_id.id))
-+				continue;
-+
-+			/* Get the correct connection info table entry based on
-+			 * the enum id. */
-+			ext_display_path =
-+					get_ext_display_path_entry(
-+							&ext_display_connection_info_tbl,
-+							dst_object_id_list[j]);
-+
-+			if (ext_display_path == NULL)
-+				return BP_RESULT_FAILURE;
-+
-+			dst_object_id_list[j] =
-+					le16_to_cpu(ext_display_path->usDeviceConnector);
-+		}
-+	}
-+
-+	return BP_RESULT_OK;
-+}
-+
-+/*
-+ * Check whether we need to patch the VBIOS connector info table with
-+ * data from an external display connection info table.  This is
-+ * necessary to support MXM boards with an OPM (output personality
-+ * module).  With these designs, the VBIOS connector info table
-+ * specifies an MXM_CONNECTOR with a unique ID.  The driver retrieves
-+ * the external connection info table through i2c and then looks up the
-+ * connector ID to find the real connector type (e.g. DFP1).
-+ *
-+ */
-+
-+static void process_ext_display_connection_info(struct bios_parser *bp)
-+{
-+	ATOM_OBJECT_TABLE *connector_tbl;
-+	uint32_t connector_tbl_offset;
-+	struct graphics_object_id object_id;
-+	ATOM_OBJECT *object;
-+	bool mxm_connector_found = false;
-+	bool null_entry_found = false;
-+	uint32_t i = 0;
-+
-+	connector_tbl_offset = bp->object_info_tbl_offset +
-+			le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
-+	connector_tbl = GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
-+
-+	/* Look for MXM connectors to determine whether we need patch the VBIOS
-+	 * connector info table. Look for null entries to determine whether we
-+	 * need to compact connector table. */
-+	for (i = 0; i < connector_tbl->ucNumberOfObjects; i++) {
-+		object = &connector_tbl->asObjects[i];
-+		object_id = object_id_from_bios_object_id(le16_to_cpu(object->usObjectID));
-+
-+		if ((OBJECT_TYPE_CONNECTOR == object_id.type) &&
-+				(CONNECTOR_ID_MXM == object_id.id)) {
-+			/* Once we found MXM connector - we can break */
-+			mxm_connector_found = true;
-+			break;
-+		} else if (OBJECT_TYPE_CONNECTOR != object_id.type) {
-+			/* We need to continue looping - to check if MXM
-+			 * connector present */
-+			null_entry_found = true;
-+		}
-+	}
-+
-+	/* Patch BIOS image */
-+	if (mxm_connector_found || null_entry_found) {
-+		uint32_t connectors_num = 0;
-+		uint8_t *original_bios;
-+		/* Step 1: Replace bios image with the new copy which will be
-+		 * patched */
-+		bp->base.bios_local_image = kzalloc(bp->base.bios_size,
-+						    GFP_KERNEL);
-+		if (bp->base.bios_local_image == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			/* Failed to alloc bp->base.bios_local_image */
-+			return;
-+		}
-+
-+		memmove(bp->base.bios_local_image, bp->base.bios, bp->base.bios_size);
-+		original_bios = bp->base.bios;
-+		bp->base.bios = bp->base.bios_local_image;
-+		connector_tbl =
-+				GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
-+
-+		/* Step 2: (only if MXM connector found) Patch BIOS image with
-+		 * info from external module */
-+		if (mxm_connector_found &&
-+		    patch_bios_image_from_ext_display_connection_info(bp) !=
-+						BP_RESULT_OK) {
-+			/* Patching the bios image has failed. We will copy
-+			 * again original image provided and afterwards
-+			 * only remove null entries */
-+			memmove(
-+					bp->base.bios_local_image,
-+					original_bios,
-+					bp->base.bios_size);
-+		}
-+
-+		/* Step 3: Compact connector table (remove null entries, valid
-+		 * entries moved to beginning) */
-+		for (i = 0; i < connector_tbl->ucNumberOfObjects; i++) {
-+			object = &connector_tbl->asObjects[i];
-+			object_id = object_id_from_bios_object_id(
-+					le16_to_cpu(object->usObjectID));
-+
-+			if (OBJECT_TYPE_CONNECTOR != object_id.type)
-+				continue;
-+
-+			if (i != connectors_num) {
-+				memmove(
-+						&connector_tbl->
-+						asObjects[connectors_num],
-+						object,
-+						sizeof(ATOM_OBJECT));
-+			}
-+			++connectors_num;
-+		}
-+		connector_tbl->ucNumberOfObjects = (uint8_t)connectors_num;
-+	}
-+}
-+
-+static void bios_parser_post_init(struct dc_bios *dcb)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+
-+	process_ext_display_connection_info(bp);
-+}
-+
-+/**
-+ * bios_parser_set_scratch_critical_state
-+ *
-+ * @brief
-+ *  update critical state bit in VBIOS scratch register
-+ *
-+ * @param
-+ *  bool - to set or reset state
-+ */
-+static void bios_parser_set_scratch_critical_state(
-+	struct dc_bios *dcb,
-+	bool state)
-+{
-+	bios_set_scratch_critical_state(dcb, state);
-+}
-+
-+/*
-+ * get_integrated_info_v8
-+ *
-+ * @brief
-+ * Get V8 integrated BIOS information
-+ *
-+ * @param
-+ * bios_parser *bp - [in]BIOS parser handler to get master data table
-+ * integrated_info *info - [out] store and output integrated info
-+ *
-+ * @return
-+ * enum bp_result - BP_RESULT_OK if information is available,
-+ *                  BP_RESULT_BADBIOSTABLE otherwise.
-+ */
-+static enum bp_result get_integrated_info_v8(
-+	struct bios_parser *bp,
-+	struct integrated_info *info)
-+{
-+	ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *info_v8;
-+	uint32_t i;
-+
-+	info_v8 = GET_IMAGE(ATOM_INTEGRATED_SYSTEM_INFO_V1_8,
-+			bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
-+
-+	if (info_v8 == NULL)
-+		return BP_RESULT_BADBIOSTABLE;
-+	info->boot_up_engine_clock = le32_to_cpu(info_v8->ulBootUpEngineClock) * 10;
-+	info->dentist_vco_freq = le32_to_cpu(info_v8->ulDentistVCOFreq) * 10;
-+	info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
-+
-+	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+		/* Convert [10KHz] into [KHz] */
-+		info->disp_clk_voltage[i].max_supported_clk =
-+			le32_to_cpu(info_v8->sDISPCLK_Voltage[i].
-+				    ulMaximumSupportedCLK) * 10;
-+		info->disp_clk_voltage[i].voltage_index =
-+			le32_to_cpu(info_v8->sDISPCLK_Voltage[i].ulVoltageIndex);
-+	}
-+
-+	info->boot_up_req_display_vector =
-+		le32_to_cpu(info_v8->ulBootUpReqDisplayVector);
-+	info->gpu_cap_info =
-+		le32_to_cpu(info_v8->ulGPUCapInfo);
-+
-+	/*
-+	 * system_config: Bit[0] = 0 : PCIE power gating disabled
-+	 *                       = 1 : PCIE power gating enabled
-+	 *                Bit[1] = 0 : DDR-PLL shut down disabled
-+	 *                       = 1 : DDR-PLL shut down enabled
-+	 *                Bit[2] = 0 : DDR-PLL power down disabled
-+	 *                       = 1 : DDR-PLL power down enabled
-+	 */
-+	info->system_config = le32_to_cpu(info_v8->ulSystemConfig);
-+	info->cpu_cap_info = le32_to_cpu(info_v8->ulCPUCapInfo);
-+	info->boot_up_nb_voltage =
-+		le16_to_cpu(info_v8->usBootUpNBVoltage);
-+	info->ext_disp_conn_info_offset =
-+		le16_to_cpu(info_v8->usExtDispConnInfoOffset);
-+	info->memory_type = info_v8->ucMemoryType;
-+	info->ma_channel_number = info_v8->ucUMAChannelNumber;
-+	info->gmc_restore_reset_time =
-+		le32_to_cpu(info_v8->ulGMCRestoreResetTime);
-+
-+	info->minimum_n_clk =
-+		le32_to_cpu(info_v8->ulNbpStateNClkFreq[0]);
-+	for (i = 1; i < 4; ++i)
-+		info->minimum_n_clk =
-+			info->minimum_n_clk < le32_to_cpu(info_v8->ulNbpStateNClkFreq[i]) ?
-+			info->minimum_n_clk : le32_to_cpu(info_v8->ulNbpStateNClkFreq[i]);
-+
-+	info->idle_n_clk = le32_to_cpu(info_v8->ulIdleNClk);
-+	info->ddr_dll_power_up_time =
-+		le32_to_cpu(info_v8->ulDDR_DLL_PowerUpTime);
-+	info->ddr_pll_power_up_time =
-+		le32_to_cpu(info_v8->ulDDR_PLL_PowerUpTime);
-+	info->pcie_clk_ss_type = le16_to_cpu(info_v8->usPCIEClkSSType);
-+	info->lvds_ss_percentage =
-+		le16_to_cpu(info_v8->usLvdsSSPercentage);
-+	info->lvds_sspread_rate_in_10hz =
-+		le16_to_cpu(info_v8->usLvdsSSpreadRateIn10Hz);
-+	info->hdmi_ss_percentage =
-+		le16_to_cpu(info_v8->usHDMISSPercentage);
-+	info->hdmi_sspread_rate_in_10hz =
-+		le16_to_cpu(info_v8->usHDMISSpreadRateIn10Hz);
-+	info->dvi_ss_percentage =
-+		le16_to_cpu(info_v8->usDVISSPercentage);
-+	info->dvi_sspread_rate_in_10_hz =
-+		le16_to_cpu(info_v8->usDVISSpreadRateIn10Hz);
-+
-+	info->max_lvds_pclk_freq_in_single_link =
-+		le16_to_cpu(info_v8->usMaxLVDSPclkFreqInSingleLink);
-+	info->lvds_misc = info_v8->ucLvdsMisc;
-+	info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
-+		info_v8->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
-+	info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
-+		info_v8->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
-+	info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
-+		info_v8->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
-+	info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
-+		info_v8->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
-+	info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
-+		info_v8->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
-+	info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
-+		info_v8->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
-+	info->lvds_off_to_on_delay_in_4ms =
-+		info_v8->ucLVDSOffToOnDelay_in4Ms;
-+	info->lvds_bit_depth_control_val =
-+		le32_to_cpu(info_v8->ulLCDBitDepthControlVal);
-+
-+	for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
-+		/* Convert [10KHz] into [KHz] */
-+		info->avail_s_clk[i].supported_s_clk =
-+			le32_to_cpu(info_v8->sAvail_SCLK[i].ulSupportedSCLK) * 10;
-+		info->avail_s_clk[i].voltage_index =
-+			le16_to_cpu(info_v8->sAvail_SCLK[i].usVoltageIndex);
-+		info->avail_s_clk[i].voltage_id =
-+			le16_to_cpu(info_v8->sAvail_SCLK[i].usVoltageID);
-+	}
-+
-+	for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
-+		info->ext_disp_conn_info.gu_id[i] =
-+			info_v8->sExtDispConnInfo.ucGuid[i];
-+	}
-+
-+	for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
-+		info->ext_disp_conn_info.path[i].device_connector_id =
-+			object_id_from_bios_object_id(
-+				le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceConnector));
-+
-+		info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
-+			object_id_from_bios_object_id(
-+				le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usExtEncoderObjId));
-+
-+		info->ext_disp_conn_info.path[i].device_tag =
-+			le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceTag);
-+		info->ext_disp_conn_info.path[i].device_acpi_enum =
-+			le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceACPIEnum);
-+		info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
-+			info_v8->sExtDispConnInfo.sPath[i].ucExtAUXDDCLutIndex;
-+		info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
-+			info_v8->sExtDispConnInfo.sPath[i].ucExtHPDPINLutIndex;
-+		info->ext_disp_conn_info.path[i].channel_mapping.raw =
-+			info_v8->sExtDispConnInfo.sPath[i].ucChannelMapping;
-+	}
-+	info->ext_disp_conn_info.checksum =
-+		info_v8->sExtDispConnInfo.ucChecksum;
-+
-+	return BP_RESULT_OK;
-+}
-+
-+/*
-+ * get_integrated_info_v8
-+ *
-+ * @brief
-+ * Get V8 integrated BIOS information
-+ *
-+ * @param
-+ * bios_parser *bp - [in]BIOS parser handler to get master data table
-+ * integrated_info *info - [out] store and output integrated info
-+ *
-+ * @return
-+ * enum bp_result - BP_RESULT_OK if information is available,
-+ *                  BP_RESULT_BADBIOSTABLE otherwise.
-+ */
-+static enum bp_result get_integrated_info_v9(
-+	struct bios_parser *bp,
-+	struct integrated_info *info)
-+{
-+	ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info_v9;
-+	uint32_t i;
-+
-+	info_v9 = GET_IMAGE(ATOM_INTEGRATED_SYSTEM_INFO_V1_9,
-+			bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
-+
-+	if (!info_v9)
-+		return BP_RESULT_BADBIOSTABLE;
-+
-+	info->boot_up_engine_clock = le32_to_cpu(info_v9->ulBootUpEngineClock) * 10;
-+	info->dentist_vco_freq = le32_to_cpu(info_v9->ulDentistVCOFreq) * 10;
-+	info->boot_up_uma_clock = le32_to_cpu(info_v9->ulBootUpUMAClock) * 10;
-+
-+	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+		/* Convert [10KHz] into [KHz] */
-+		info->disp_clk_voltage[i].max_supported_clk =
-+			le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulMaximumSupportedCLK) * 10;
-+		info->disp_clk_voltage[i].voltage_index =
-+			le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulVoltageIndex);
-+	}
-+
-+	info->boot_up_req_display_vector =
-+		le32_to_cpu(info_v9->ulBootUpReqDisplayVector);
-+	info->gpu_cap_info = le32_to_cpu(info_v9->ulGPUCapInfo);
-+
-+	/*
-+	 * system_config: Bit[0] = 0 : PCIE power gating disabled
-+	 *                       = 1 : PCIE power gating enabled
-+	 *                Bit[1] = 0 : DDR-PLL shut down disabled
-+	 *                       = 1 : DDR-PLL shut down enabled
-+	 *                Bit[2] = 0 : DDR-PLL power down disabled
-+	 *                       = 1 : DDR-PLL power down enabled
-+	 */
-+	info->system_config = le32_to_cpu(info_v9->ulSystemConfig);
-+	info->cpu_cap_info = le32_to_cpu(info_v9->ulCPUCapInfo);
-+	info->boot_up_nb_voltage = le16_to_cpu(info_v9->usBootUpNBVoltage);
-+	info->ext_disp_conn_info_offset = le16_to_cpu(info_v9->usExtDispConnInfoOffset);
-+	info->memory_type = info_v9->ucMemoryType;
-+	info->ma_channel_number = info_v9->ucUMAChannelNumber;
-+	info->gmc_restore_reset_time = le32_to_cpu(info_v9->ulGMCRestoreResetTime);
-+
-+	info->minimum_n_clk = le32_to_cpu(info_v9->ulNbpStateNClkFreq[0]);
-+	for (i = 1; i < 4; ++i)
-+		info->minimum_n_clk =
-+			info->minimum_n_clk < le32_to_cpu(info_v9->ulNbpStateNClkFreq[i]) ?
-+			info->minimum_n_clk : le32_to_cpu(info_v9->ulNbpStateNClkFreq[i]);
-+
-+	info->idle_n_clk = le32_to_cpu(info_v9->ulIdleNClk);
-+	info->ddr_dll_power_up_time = le32_to_cpu(info_v9->ulDDR_DLL_PowerUpTime);
-+	info->ddr_pll_power_up_time = le32_to_cpu(info_v9->ulDDR_PLL_PowerUpTime);
-+	info->pcie_clk_ss_type = le16_to_cpu(info_v9->usPCIEClkSSType);
-+	info->lvds_ss_percentage = le16_to_cpu(info_v9->usLvdsSSPercentage);
-+	info->lvds_sspread_rate_in_10hz = le16_to_cpu(info_v9->usLvdsSSpreadRateIn10Hz);
-+	info->hdmi_ss_percentage = le16_to_cpu(info_v9->usHDMISSPercentage);
-+	info->hdmi_sspread_rate_in_10hz = le16_to_cpu(info_v9->usHDMISSpreadRateIn10Hz);
-+	info->dvi_ss_percentage = le16_to_cpu(info_v9->usDVISSPercentage);
-+	info->dvi_sspread_rate_in_10_hz = le16_to_cpu(info_v9->usDVISSpreadRateIn10Hz);
-+
-+	info->max_lvds_pclk_freq_in_single_link =
-+		le16_to_cpu(info_v9->usMaxLVDSPclkFreqInSingleLink);
-+	info->lvds_misc = info_v9->ucLvdsMisc;
-+	info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
-+		info_v9->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
-+	info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
-+		info_v9->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
-+	info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
-+		info_v9->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
-+	info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
-+		info_v9->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
-+	info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
-+		info_v9->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
-+	info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
-+		info_v9->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
-+	info->lvds_off_to_on_delay_in_4ms =
-+		info_v9->ucLVDSOffToOnDelay_in4Ms;
-+	info->lvds_bit_depth_control_val =
-+		le32_to_cpu(info_v9->ulLCDBitDepthControlVal);
-+
-+	for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
-+		/* Convert [10KHz] into [KHz] */
-+		info->avail_s_clk[i].supported_s_clk =
-+			le32_to_cpu(info_v9->sAvail_SCLK[i].ulSupportedSCLK) * 10;
-+		info->avail_s_clk[i].voltage_index =
-+			le16_to_cpu(info_v9->sAvail_SCLK[i].usVoltageIndex);
-+		info->avail_s_clk[i].voltage_id =
-+			le16_to_cpu(info_v9->sAvail_SCLK[i].usVoltageID);
-+	}
-+
-+	for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
-+		info->ext_disp_conn_info.gu_id[i] =
-+			info_v9->sExtDispConnInfo.ucGuid[i];
-+	}
-+
-+	for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
-+		info->ext_disp_conn_info.path[i].device_connector_id =
-+			object_id_from_bios_object_id(
-+				le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceConnector));
-+
-+		info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
-+			object_id_from_bios_object_id(
-+				le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usExtEncoderObjId));
-+
-+		info->ext_disp_conn_info.path[i].device_tag =
-+			le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceTag);
-+		info->ext_disp_conn_info.path[i].device_acpi_enum =
-+			le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceACPIEnum);
-+		info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
-+			info_v9->sExtDispConnInfo.sPath[i].ucExtAUXDDCLutIndex;
-+		info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
-+			info_v9->sExtDispConnInfo.sPath[i].ucExtHPDPINLutIndex;
-+		info->ext_disp_conn_info.path[i].channel_mapping.raw =
-+			info_v9->sExtDispConnInfo.sPath[i].ucChannelMapping;
-+	}
-+	info->ext_disp_conn_info.checksum =
-+		info_v9->sExtDispConnInfo.ucChecksum;
-+
-+	return BP_RESULT_OK;
-+}
-+
-+/*
-+ * construct_integrated_info
-+ *
-+ * @brief
-+ * Get integrated BIOS information based on table revision
-+ *
-+ * @param
-+ * bios_parser *bp - [in]BIOS parser handler to get master data table
-+ * integrated_info *info - [out] store and output integrated info
-+ *
-+ * @return
-+ * enum bp_result - BP_RESULT_OK if information is available,
-+ *                  BP_RESULT_BADBIOSTABLE otherwise.
-+ */
-+static enum bp_result construct_integrated_info(
-+	struct bios_parser *bp,
-+	struct integrated_info *info)
-+{
-+	enum bp_result result = BP_RESULT_BADBIOSTABLE;
-+
-+	ATOM_COMMON_TABLE_HEADER *header;
-+	struct atom_data_revision revision;
-+
-+	if (bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo) {
-+		header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER,
-+				bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo);
-+
-+		get_atom_data_table_revision(header, &revision);
-+
-+		/* Don't need to check major revision as they are all 1 */
-+		switch (revision.minor) {
-+		case 8:
-+			result = get_integrated_info_v8(bp, info);
-+			break;
-+		case 9:
-+			result = get_integrated_info_v9(bp, info);
-+			break;
-+		default:
-+			return result;
-+
-+		}
-+	}
-+
-+	/* Sort voltage table from low to high*/
-+	if (result == BP_RESULT_OK) {
-+		struct clock_voltage_caps temp = {0, 0};
-+		uint32_t i;
-+		uint32_t j;
-+
-+		for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+			for (j = i; j > 0; --j) {
-+				if (
-+						info->disp_clk_voltage[j].max_supported_clk <
-+						info->disp_clk_voltage[j-1].max_supported_clk) {
-+					/* swap j and j - 1*/
-+					temp = info->disp_clk_voltage[j-1];
-+					info->disp_clk_voltage[j-1] =
-+							info->disp_clk_voltage[j];
-+					info->disp_clk_voltage[j] = temp;
-+				}
-+			}
-+		}
-+
-+	}
-+
-+	return result;
-+}
-+
-+static struct integrated_info *bios_parser_create_integrated_info(
-+	struct dc_bios *dcb)
-+{
-+	struct bios_parser *bp = BP_FROM_DCB(dcb);
-+	struct integrated_info *info = NULL;
-+
-+	info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
-+
-+	if (info == NULL) {
-+		ASSERT_CRITICAL(0);
-+		return NULL;
-+	}
-+
-+	if (construct_integrated_info(bp, info) == BP_RESULT_OK)
-+		return info;
-+
-+	kfree(info);
-+
-+	return NULL;
-+}
-+
-+/******************************************************************************/
-+
-+static const struct dc_vbios_funcs vbios_funcs = {
-+	.get_connectors_number = bios_parser_get_connectors_number,
-+
-+	.get_encoder_id = bios_parser_get_encoder_id,
-+
-+	.get_connector_id = bios_parser_get_connector_id,
-+
-+	.get_dst_number = bios_parser_get_dst_number,
-+
-+	.get_src_obj = bios_parser_get_src_obj,
-+
-+	.get_dst_obj = bios_parser_get_dst_obj,
-+
-+	.get_i2c_info = bios_parser_get_i2c_info,
-+
-+	.get_voltage_ddc_info = bios_parser_get_voltage_ddc_info,
-+
-+	.get_thermal_ddc_info = bios_parser_get_thermal_ddc_info,
-+
-+	.get_hpd_info = bios_parser_get_hpd_info,
-+
-+	.get_device_tag = bios_parser_get_device_tag,
-+
-+	.get_firmware_info = bios_parser_get_firmware_info,
-+
-+	.get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
-+
-+	.get_ss_entry_number = bios_parser_get_ss_entry_number,
-+
-+	.get_embedded_panel_info = bios_parser_get_embedded_panel_info,
-+
-+	.get_gpio_pin_info = bios_parser_get_gpio_pin_info,
-+
-+	.get_embedded_panel_info = bios_parser_get_embedded_panel_info,
-+
-+	.get_gpio_pin_info = bios_parser_get_gpio_pin_info,
-+
-+	.get_encoder_cap_info = bios_parser_get_encoder_cap_info,
-+
-+	/* bios scratch register communication */
-+	.is_accelerated_mode = bios_is_accelerated_mode,
-+
-+	.set_scratch_critical_state = bios_parser_set_scratch_critical_state,
-+
-+	.is_device_id_supported = bios_parser_is_device_id_supported,
-+
-+	/* COMMANDS */
-+	.encoder_control = bios_parser_encoder_control,
-+
-+	.transmitter_control = bios_parser_transmitter_control,
-+
-+	.crt_control = bios_parser_crt_control,  /* not used in DAL3.  keep for now in case we need to support VGA on Bonaire */
-+
-+	.enable_crtc = bios_parser_enable_crtc,
-+
-+	.adjust_pixel_clock = bios_parser_adjust_pixel_clock,
-+
-+	.set_pixel_clock = bios_parser_set_pixel_clock,
-+
-+	.set_dce_clock = bios_parser_set_dce_clock,
-+
-+	.enable_spread_spectrum_on_ppll = bios_parser_enable_spread_spectrum_on_ppll,
-+
-+	.program_crtc_timing = bios_parser_program_crtc_timing, /* still use.  should probably retire and program directly */
-+
-+	.crtc_source_select = bios_parser_crtc_source_select,  /* still use.  should probably retire and program directly */
-+
-+	.program_display_engine_pll = bios_parser_program_display_engine_pll,
-+
-+	.enable_disp_power_gating = bios_parser_enable_disp_power_gating,
-+
-+	/* SW init and patch */
-+	.post_init = bios_parser_post_init,  /* patch vbios table for mxm module by reading i2c */
-+
-+	.bios_parser_destroy = bios_parser_destroy,
-+};
-+
-+static bool bios_parser_construct(
-+	struct bios_parser *bp,
-+	struct bp_init_data *init,
-+	enum dce_version dce_version)
-+{
-+	uint16_t *rom_header_offset = NULL;
-+	ATOM_ROM_HEADER *rom_header = NULL;
-+	ATOM_OBJECT_HEADER *object_info_tbl;
-+	struct atom_data_revision tbl_rev = {0};
-+
-+	if (!init)
-+		return false;
-+
-+	if (!init->bios)
-+		return false;
-+
-+	bp->base.funcs = &vbios_funcs;
-+	bp->base.bios = init->bios;
-+	bp->base.bios_size = bp->base.bios[BIOS_IMAGE_SIZE_OFFSET] * BIOS_IMAGE_SIZE_UNIT;
-+
-+	bp->base.ctx = init->ctx;
-+	bp->base.bios_local_image = NULL;
-+
-+	rom_header_offset =
-+	GET_IMAGE(uint16_t, OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER);
-+
-+	if (!rom_header_offset)
-+		return false;
-+
-+	rom_header = GET_IMAGE(ATOM_ROM_HEADER, *rom_header_offset);
-+
-+	if (!rom_header)
-+		return false;
-+
-+	get_atom_data_table_revision(&rom_header->sHeader, &tbl_rev);
-+	if (tbl_rev.major >= 2 && tbl_rev.minor >= 2)
-+		return false;
-+
-+	bp->master_data_tbl =
-+	GET_IMAGE(ATOM_MASTER_DATA_TABLE,
-+		rom_header->usMasterDataTableOffset);
-+
-+	if (!bp->master_data_tbl)
-+		return false;
-+
-+	bp->object_info_tbl_offset = DATA_TABLES(Object_Header);
-+
-+	if (!bp->object_info_tbl_offset)
-+		return false;
-+
-+	object_info_tbl =
-+	GET_IMAGE(ATOM_OBJECT_HEADER, bp->object_info_tbl_offset);
-+
-+	if (!object_info_tbl)
-+		return false;
-+
-+	get_atom_data_table_revision(&object_info_tbl->sHeader,
-+		&bp->object_info_tbl.revision);
-+
-+	if (bp->object_info_tbl.revision.major == 1
-+		&& bp->object_info_tbl.revision.minor >= 3) {
-+		ATOM_OBJECT_HEADER_V3 *tbl_v3;
-+
-+		tbl_v3 = GET_IMAGE(ATOM_OBJECT_HEADER_V3,
-+			bp->object_info_tbl_offset);
-+		if (!tbl_v3)
-+			return false;
-+
-+		bp->object_info_tbl.v1_3 = tbl_v3;
-+	} else if (bp->object_info_tbl.revision.major == 1
-+		&& bp->object_info_tbl.revision.minor >= 1)
-+		bp->object_info_tbl.v1_1 = object_info_tbl;
-+	else
-+		return false;
-+
-+	dal_bios_parser_init_cmd_tbl(bp);
-+	dal_bios_parser_init_cmd_tbl_helper(&bp->cmd_helper, dce_version);
-+
-+	bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
-+
-+	return true;
-+}
-+
-+/******************************************************************************/
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c.0130~	2017-12-14 06:39:58.399903556 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.c	2017-12-14 06:39:58.399903556 +0100
-@@ -0,0 +1,288 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "bios_parser_common.h"
-+#include "include/grph_object_ctrl_defs.h"
-+
-+static enum object_type object_type_from_bios_object_id(uint32_t bios_object_id)
-+{
-+	uint32_t bios_object_type = (bios_object_id & OBJECT_TYPE_MASK)
-+				>> OBJECT_TYPE_SHIFT;
-+	enum object_type object_type;
-+
-+	switch (bios_object_type) {
-+	case GRAPH_OBJECT_TYPE_GPU:
-+		object_type = OBJECT_TYPE_GPU;
-+		break;
-+	case GRAPH_OBJECT_TYPE_ENCODER:
-+		object_type = OBJECT_TYPE_ENCODER;
-+		break;
-+	case GRAPH_OBJECT_TYPE_CONNECTOR:
-+		object_type = OBJECT_TYPE_CONNECTOR;
-+		break;
-+	case GRAPH_OBJECT_TYPE_ROUTER:
-+		object_type = OBJECT_TYPE_ROUTER;
-+		break;
-+	case GRAPH_OBJECT_TYPE_GENERIC:
-+		object_type = OBJECT_TYPE_GENERIC;
-+		break;
-+	default:
-+		object_type = OBJECT_TYPE_UNKNOWN;
-+		break;
-+	}
-+
-+	return object_type;
-+}
-+
-+static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id)
-+{
-+	uint32_t bios_enum_id =
-+			(bios_object_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
-+	enum object_enum_id id;
-+
-+	switch (bios_enum_id) {
-+	case GRAPH_OBJECT_ENUM_ID1:
-+		id = ENUM_ID_1;
-+		break;
-+	case GRAPH_OBJECT_ENUM_ID2:
-+		id = ENUM_ID_2;
-+		break;
-+	case GRAPH_OBJECT_ENUM_ID3:
-+		id = ENUM_ID_3;
-+		break;
-+	case GRAPH_OBJECT_ENUM_ID4:
-+		id = ENUM_ID_4;
-+		break;
-+	case GRAPH_OBJECT_ENUM_ID5:
-+		id = ENUM_ID_5;
-+		break;
-+	case GRAPH_OBJECT_ENUM_ID6:
-+		id = ENUM_ID_6;
-+		break;
-+	case GRAPH_OBJECT_ENUM_ID7:
-+		id = ENUM_ID_7;
-+		break;
-+	default:
-+		id = ENUM_ID_UNKNOWN;
-+		break;
-+	}
-+
-+	return id;
-+}
-+
-+static uint32_t gpu_id_from_bios_object_id(uint32_t bios_object_id)
-+{
-+	return (bios_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
-+}
-+
-+static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id)
-+{
-+	uint32_t bios_encoder_id = gpu_id_from_bios_object_id(bios_object_id);
-+	enum encoder_id id;
-+
-+	switch (bios_encoder_id) {
-+	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
-+		id = ENCODER_ID_INTERNAL_LVDS;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
-+		id = ENCODER_ID_INTERNAL_TMDS1;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_TMDS2:
-+		id = ENCODER_ID_INTERNAL_TMDS2;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
-+		id = ENCODER_ID_INTERNAL_DAC1;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
-+		id = ENCODER_ID_INTERNAL_DAC2;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
-+		id = ENCODER_ID_INTERNAL_LVTM1;
-+		break;
-+	case ENCODER_OBJECT_ID_HDMI_INTERNAL:
-+		id = ENCODER_ID_INTERNAL_HDMI;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
-+		id = ENCODER_ID_INTERNAL_KLDSCP_TMDS1;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
-+		id = ENCODER_ID_INTERNAL_KLDSCP_DAC1;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
-+		id = ENCODER_ID_INTERNAL_KLDSCP_DAC2;
-+		break;
-+	case ENCODER_OBJECT_ID_MVPU_FPGA:
-+		id = ENCODER_ID_EXTERNAL_MVPU_FPGA;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_DDI:
-+		id = ENCODER_ID_INTERNAL_DDI;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
-+		id = ENCODER_ID_INTERNAL_UNIPHY;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
-+		id = ENCODER_ID_INTERNAL_KLDSCP_LVTMA;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
-+		id = ENCODER_ID_INTERNAL_UNIPHY1;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
-+		id = ENCODER_ID_INTERNAL_UNIPHY2;
-+		break;
-+	case ENCODER_OBJECT_ID_ALMOND: /* ENCODER_OBJECT_ID_NUTMEG */
-+		id = ENCODER_ID_EXTERNAL_NUTMEG;
-+		break;
-+	case ENCODER_OBJECT_ID_TRAVIS:
-+		id = ENCODER_ID_EXTERNAL_TRAVIS;
-+		break;
-+	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
-+		id = ENCODER_ID_INTERNAL_UNIPHY3;
-+		break;
-+	default:
-+		id = ENCODER_ID_UNKNOWN;
-+		ASSERT(0);
-+		break;
-+	}
-+
-+	return id;
-+}
-+
-+static enum connector_id connector_id_from_bios_object_id(
-+	uint32_t bios_object_id)
-+{
-+	uint32_t bios_connector_id = gpu_id_from_bios_object_id(bios_object_id);
-+
-+	enum connector_id id;
-+
-+	switch (bios_connector_id) {
-+	case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I:
-+		id = CONNECTOR_ID_SINGLE_LINK_DVII;
-+		break;
-+	case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I:
-+		id = CONNECTOR_ID_DUAL_LINK_DVII;
-+		break;
-+	case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D:
-+		id = CONNECTOR_ID_SINGLE_LINK_DVID;
-+		break;
-+	case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D:
-+		id = CONNECTOR_ID_DUAL_LINK_DVID;
-+		break;
-+	case CONNECTOR_OBJECT_ID_VGA:
-+		id = CONNECTOR_ID_VGA;
-+		break;
-+	case CONNECTOR_OBJECT_ID_HDMI_TYPE_A:
-+		id = CONNECTOR_ID_HDMI_TYPE_A;
-+		break;
-+	case CONNECTOR_OBJECT_ID_LVDS:
-+		id = CONNECTOR_ID_LVDS;
-+		break;
-+	case CONNECTOR_OBJECT_ID_PCIE_CONNECTOR:
-+		id = CONNECTOR_ID_PCIE;
-+		break;
-+	case CONNECTOR_OBJECT_ID_HARDCODE_DVI:
-+		id = CONNECTOR_ID_HARDCODE_DVI;
-+		break;
-+	case CONNECTOR_OBJECT_ID_DISPLAYPORT:
-+		id = CONNECTOR_ID_DISPLAY_PORT;
-+		break;
-+	case CONNECTOR_OBJECT_ID_eDP:
-+		id = CONNECTOR_ID_EDP;
-+		break;
-+	case CONNECTOR_OBJECT_ID_MXM:
-+		id = CONNECTOR_ID_MXM;
-+		break;
-+	default:
-+		id = CONNECTOR_ID_UNKNOWN;
-+		break;
-+	}
-+
-+	return id;
-+}
-+
-+static enum generic_id generic_id_from_bios_object_id(uint32_t bios_object_id)
-+{
-+	uint32_t bios_generic_id = gpu_id_from_bios_object_id(bios_object_id);
-+
-+	enum generic_id id;
-+
-+	switch (bios_generic_id) {
-+	case GENERIC_OBJECT_ID_MXM_OPM:
-+		id = GENERIC_ID_MXM_OPM;
-+		break;
-+	case GENERIC_OBJECT_ID_GLSYNC:
-+		id = GENERIC_ID_GLSYNC;
-+		break;
-+	case GENERIC_OBJECT_ID_STEREO_PIN:
-+		id = GENERIC_ID_STEREO;
-+		break;
-+	default:
-+		id = GENERIC_ID_UNKNOWN;
-+		break;
-+	}
-+
-+	return id;
-+}
-+
-+static uint32_t id_from_bios_object_id(enum object_type type,
-+	uint32_t bios_object_id)
-+{
-+	switch (type) {
-+	case OBJECT_TYPE_GPU:
-+		return gpu_id_from_bios_object_id(bios_object_id);
-+	case OBJECT_TYPE_ENCODER:
-+		return (uint32_t)encoder_id_from_bios_object_id(bios_object_id);
-+	case OBJECT_TYPE_CONNECTOR:
-+		return (uint32_t)connector_id_from_bios_object_id(
-+				bios_object_id);
-+	case OBJECT_TYPE_GENERIC:
-+		return generic_id_from_bios_object_id(bios_object_id);
-+	default:
-+		return 0;
-+	}
-+}
-+
-+struct graphics_object_id object_id_from_bios_object_id(uint32_t bios_object_id)
-+{
-+	enum object_type type;
-+	enum object_enum_id enum_id;
-+	struct graphics_object_id go_id = { 0 };
-+
-+	type = object_type_from_bios_object_id(bios_object_id);
-+
-+	if (OBJECT_TYPE_UNKNOWN == type)
-+		return go_id;
-+
-+	enum_id = enum_id_from_bios_object_id(bios_object_id);
-+
-+	if (ENUM_ID_UNKNOWN == enum_id)
-+		return go_id;
-+
-+	go_id = dal_graphics_object_id_init(
-+			id_from_bios_object_id(type, bios_object_id), enum_id, type);
-+
-+	return go_id;
-+}
-+
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.h.0130~	2017-12-14 06:39:58.399903556 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser_common.h	2017-12-14 06:39:58.399903556 +0100
-@@ -0,0 +1,33 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __BIOS_PARSER_COMMON_H__
-+#define __BIOS_PARSER_COMMON_H__
-+
-+#include "dm_services.h"
-+#include "ObjectID.h"
-+
-+struct graphics_object_id object_id_from_bios_object_id(uint32_t bios_object_id);
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser.h.0130~	2017-12-14 06:39:58.399903556 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser.h	2017-12-14 06:39:58.399903556 +0100
-@@ -0,0 +1,33 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_H__
-+#define __DAL_BIOS_PARSER_H__
-+
-+struct dc_bios *bios_parser_create(
-+	struct bp_init_data *init,
-+	enum dce_version dce_version);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c.0130~	2017-12-14 06:39:58.399903556 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c	2017-12-14 06:39:58.399903556 +0100
-@@ -0,0 +1,82 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/bios_parser_types.h"
-+#include "bios_parser_helper.h"
-+#include "command_table_helper.h"
-+#include "command_table.h"
-+#include "bios_parser_types_internal.h"
-+
-+uint8_t *bios_get_image(struct dc_bios *bp,
-+	uint32_t offset,
-+	uint32_t size)
-+{
-+	if (bp->bios && offset + size < bp->bios_size)
-+		return bp->bios + offset;
-+	else
-+		return NULL;
-+}
-+
-+#include "reg_helper.h"
-+
-+#define CTX \
-+	bios->ctx
-+#define REG(reg)\
-+	(bios->regs->reg)
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+		ATOM_ ## field_name ## _SHIFT, ATOM_ ## field_name
-+
-+bool bios_is_accelerated_mode(
-+	struct dc_bios *bios)
-+{
-+	uint32_t acc_mode;
-+	REG_GET(BIOS_SCRATCH_6, S6_ACC_MODE, &acc_mode);
-+	return (acc_mode == 1);
-+}
-+
-+
-+void bios_set_scratch_acc_mode_change(
-+	struct dc_bios *bios)
-+{
-+	REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, 1);
-+}
-+
-+
-+void bios_set_scratch_critical_state(
-+	struct dc_bios *bios,
-+	bool state)
-+{
-+	uint32_t critial_state = state ? 1 : 0;
-+	REG_UPDATE(BIOS_SCRATCH_6, S6_CRITICAL_STATE, critial_state);
-+}
-+
-+
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h.0130~	2017-12-14 06:39:58.399903556 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h	2017-12-14 06:39:58.399903556 +0100
-@@ -0,0 +1,40 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_HELPER_H__
-+#define __DAL_BIOS_PARSER_HELPER_H__
-+
-+struct bios_parser;
-+
-+uint8_t *bios_get_image(struct dc_bios *bp, uint32_t offset,
-+	uint32_t size);
-+
-+bool bios_is_accelerated_mode(struct dc_bios *bios);
-+void bios_set_scratch_acc_mode_change(struct dc_bios *bios);
-+void bios_set_scratch_critical_state(struct dc_bios *bios, bool state);
-+
-+#define GET_IMAGE(type, offset) ((type *) bios_get_image(&bp->base, offset, sizeof(type)))
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c.0130~	2017-12-14 06:39:58.399903556 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c	2017-12-14 06:39:58.399903556 +0100
-@@ -0,0 +1,56 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "include/logger_interface.h"
-+
-+#include "bios_parser_interface.h"
-+#include "bios_parser.h"
-+
-+#include "bios_parser2.h"
-+
-+
-+struct dc_bios *dal_bios_parser_create(
-+	struct bp_init_data *init,
-+	enum dce_version dce_version)
-+{
-+	struct dc_bios *bios = NULL;
-+
-+	bios = firmware_parser_create(init, dce_version);
-+
-+	/* Fall back to old bios parser for older asics */
-+	if (bios == NULL)
-+		bios = bios_parser_create(init, dce_version);
-+
-+	return bios;
-+}
-+
-+void dal_bios_parser_destroy(struct dc_bios **dcb)
-+{
-+	struct dc_bios *bios = *dcb;
-+
-+	bios->funcs->bios_parser_destroy(dcb);
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h.0130~	2017-12-14 06:39:58.400903557 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h	2017-12-14 06:39:58.400903557 +0100
-@@ -0,0 +1,74 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_TYPES_BIOS2_H__
-+#define __DAL_BIOS_PARSER_TYPES_BIOS2_H__
-+
-+#include "dc_bios_types.h"
-+#include "bios_parser_helper.h"
-+
-+/* use atomfirmware_bringup.h only. Not atombios.h anymore */
-+
-+struct atom_data_revision {
-+	uint32_t major;
-+	uint32_t minor;
-+};
-+
-+struct object_info_table {
-+	struct atom_data_revision revision;
-+	union {
-+		struct display_object_info_table_v1_4 *v1_4;
-+	};
-+};
-+
-+enum spread_spectrum_id {
-+	SS_ID_UNKNOWN = 0,
-+	SS_ID_DP1 = 0xf1,
-+	SS_ID_DP2 = 0xf2,
-+	SS_ID_LVLINK_2700MHZ = 0xf3,
-+	SS_ID_LVLINK_1620MHZ = 0xf4
-+};
-+
-+struct bios_parser {
-+	struct dc_bios base;
-+
-+	struct object_info_table object_info_tbl;
-+	uint32_t object_info_tbl_offset;
-+	struct atom_master_data_table_v2_1 *master_data_tbl;
-+
-+
-+	const struct bios_parser_helper *bios_helper;
-+
-+	const struct command_table_helper *cmd_helper;
-+	struct cmd_tbl cmd_tbl;
-+
-+	bool remap_device_tags;
-+};
-+
-+/* Bios Parser from DC Bios */
-+#define BP_FROM_DCB(dc_bios) \
-+	container_of(dc_bios, struct bios_parser, base)
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal.h.0130~	2017-12-14 06:39:58.400903557 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal.h	2017-12-14 06:39:58.400903557 +0100
-@@ -0,0 +1,72 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_TYPES_BIOS_H__
-+#define __DAL_BIOS_PARSER_TYPES_BIOS_H__
-+
-+#include "dc_bios_types.h"
-+#include "bios_parser_helper.h"
-+
-+struct atom_data_revision {
-+	uint32_t major;
-+	uint32_t minor;
-+};
-+
-+struct object_info_table {
-+	struct atom_data_revision revision;
-+	union {
-+		ATOM_OBJECT_HEADER *v1_1;
-+		ATOM_OBJECT_HEADER_V3 *v1_3;
-+	};
-+};
-+
-+enum spread_spectrum_id {
-+	SS_ID_UNKNOWN = 0,
-+	SS_ID_DP1 = 0xf1,
-+	SS_ID_DP2 = 0xf2,
-+	SS_ID_LVLINK_2700MHZ = 0xf3,
-+	SS_ID_LVLINK_1620MHZ = 0xf4
-+};
-+
-+struct bios_parser {
-+	struct dc_bios base;
-+
-+	struct object_info_table object_info_tbl;
-+	uint32_t object_info_tbl_offset;
-+	ATOM_MASTER_DATA_TABLE *master_data_tbl;
-+
-+	const struct bios_parser_helper *bios_helper;
-+
-+	const struct command_table_helper *cmd_helper;
-+	struct cmd_tbl cmd_tbl;
-+
-+	bool remap_device_tags;
-+};
-+
-+/* Bios Parser from DC Bios */
-+#define BP_FROM_DCB(dc_bios) \
-+	container_of(dc_bios, struct bios_parser, base)
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table2.c.0130~	2017-12-14 06:39:58.400903557 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table2.c	2017-12-14 06:39:58.400903557 +0100
-@@ -0,0 +1,812 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "ObjectID.h"
-+#include "atomfirmware.h"
-+
-+#include "include/bios_parser_interface.h"
-+
-+#include "command_table2.h"
-+#include "command_table_helper2.h"
-+#include "bios_parser_helper.h"
-+#include "bios_parser_types_internal2.h"
-+
-+#define GET_INDEX_INTO_MASTER_TABLE(MasterOrData, FieldName)\
-+	(((char *)(&((\
-+		struct atom_master_list_of_##MasterOrData##_functions_v2_1 *)0)\
-+		->FieldName)-(char *)0)/sizeof(uint16_t))
-+
-+#define EXEC_BIOS_CMD_TABLE(fname, params)\
-+	(cgs_atom_exec_cmd_table(bp->base.ctx->cgs_device, \
-+		GET_INDEX_INTO_MASTER_TABLE(command, fname), \
-+		&params) == 0)
-+
-+#define BIOS_CMD_TABLE_REVISION(fname, frev, crev)\
-+	cgs_atom_get_cmd_table_revs(bp->base.ctx->cgs_device, \
-+		GET_INDEX_INTO_MASTER_TABLE(command, fname), &frev, &crev)
-+
-+#define BIOS_CMD_TABLE_PARA_REVISION(fname)\
-+	bios_cmd_table_para_revision(bp->base.ctx->cgs_device, \
-+			GET_INDEX_INTO_MASTER_TABLE(command, fname))
-+
-+static void init_dig_encoder_control(struct bios_parser *bp);
-+static void init_transmitter_control(struct bios_parser *bp);
-+static void init_set_pixel_clock(struct bios_parser *bp);
-+
-+static void init_set_crtc_timing(struct bios_parser *bp);
-+
-+static void init_select_crtc_source(struct bios_parser *bp);
-+static void init_enable_crtc(struct bios_parser *bp);
-+
-+static void init_external_encoder_control(struct bios_parser *bp);
-+static void init_enable_disp_power_gating(struct bios_parser *bp);
-+static void init_set_dce_clock(struct bios_parser *bp);
-+static void init_get_smu_clock_info(struct bios_parser *bp);
-+
-+void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
-+{
-+	init_dig_encoder_control(bp);
-+	init_transmitter_control(bp);
-+	init_set_pixel_clock(bp);
-+
-+	init_set_crtc_timing(bp);
-+
-+	init_select_crtc_source(bp);
-+	init_enable_crtc(bp);
-+
-+	init_external_encoder_control(bp);
-+	init_enable_disp_power_gating(bp);
-+	init_set_dce_clock(bp);
-+	init_get_smu_clock_info(bp);
-+}
-+
-+static uint32_t bios_cmd_table_para_revision(void *cgs_device,
-+					     uint32_t index)
-+{
-+	uint8_t frev, crev;
-+
-+	if (cgs_atom_get_cmd_table_revs(cgs_device,
-+					index,
-+					&frev, &crev) != 0)
-+		return 0;
-+	return crev;
-+}
-+
-+/******************************************************************************
-+ ******************************************************************************
-+ **
-+ **                  D I G E N C O D E R C O N T R O L
-+ **
-+ ******************************************************************************
-+ *****************************************************************************/
-+
-+static enum bp_result encoder_control_digx_v1_5(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl);
-+
-+static void init_dig_encoder_control(struct bios_parser *bp)
-+{
-+	uint32_t version =
-+		BIOS_CMD_TABLE_PARA_REVISION(digxencodercontrol);
-+
-+	switch (version) {
-+	case 5:
-+		bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v1_5;
-+		break;
-+	default:
-+		bp->cmd_tbl.dig_encoder_control = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result encoder_control_digx_v1_5(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	struct dig_encoder_stream_setup_parameters_v1_5 params = {0};
-+
-+	params.digid = (uint8_t)(cntl->engine_id);
-+	params.action = bp->cmd_helper->encoder_action_to_atom(cntl->action);
-+
-+	params.pclk_10khz = cntl->pixel_clock / 10;
-+	params.digmode =
-+			(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
-+					cntl->signal,
-+					cntl->enable_dp_audio));
-+	params.lanenum = (uint8_t)(cntl->lanes_number);
-+
-+	switch (cntl->color_depth) {
-+	case COLOR_DEPTH_888:
-+		params.bitpercolor = PANEL_8BIT_PER_COLOR;
-+		break;
-+	case COLOR_DEPTH_101010:
-+		params.bitpercolor = PANEL_10BIT_PER_COLOR;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		params.bitpercolor = PANEL_12BIT_PER_COLOR;
-+		break;
-+	case COLOR_DEPTH_161616:
-+		params.bitpercolor = PANEL_16BIT_PER_COLOR;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+		switch (cntl->color_depth) {
-+		case COLOR_DEPTH_101010:
-+			params.pclk_10khz =
-+				(params.pclk_10khz * 30) / 24;
-+			break;
-+		case COLOR_DEPTH_121212:
-+			params.pclk_10khz =
-+				(params.pclk_10khz * 36) / 24;
-+			break;
-+		case COLOR_DEPTH_161616:
-+			params.pclk_10khz =
-+				(params.pclk_10khz * 48) / 24;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+	if (EXEC_BIOS_CMD_TABLE(digxencodercontrol, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*****************************************************************************
-+ ******************************************************************************
-+ **
-+ **                  TRANSMITTER CONTROL
-+ **
-+ ******************************************************************************
-+ *****************************************************************************/
-+
-+static enum bp_result transmitter_control_v1_6(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl);
-+
-+static void init_transmitter_control(struct bios_parser *bp)
-+{
-+	uint8_t frev;
-+	uint8_t crev;
-+
-+	if (BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) != 0)
-+		BREAK_TO_DEBUGGER();
-+	switch (crev) {
-+	case 6:
-+		bp->cmd_tbl.transmitter_control = transmitter_control_v1_6;
-+		break;
-+	default:
-+		bp->cmd_tbl.transmitter_control = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result transmitter_control_v1_6(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	const struct command_table_helper *cmd = bp->cmd_helper;
-+	struct dig_transmitter_control_ps_allocation_v1_6 ps = { { 0 } };
-+
-+	ps.param.phyid = cmd->phy_id_to_atom(cntl->transmitter);
-+	ps.param.action = (uint8_t)cntl->action;
-+
-+	if (cntl->action == TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS)
-+		ps.param.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings;
-+	else
-+		ps.param.mode_laneset.digmode =
-+				cmd->signal_type_to_atom_dig_mode(cntl->signal);
-+
-+	ps.param.lanenum = (uint8_t)cntl->lanes_number;
-+	ps.param.hpdsel = cmd->hpd_sel_to_atom(cntl->hpd_sel);
-+	ps.param.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id);
-+	ps.param.connobj_id = (uint8_t)cntl->connector_obj_id.id;
-+	ps.param.symclk_10khz = cntl->pixel_clock/10;
-+
-+
-+	if (cntl->action == TRANSMITTER_CONTROL_ENABLE ||
-+		cntl->action == TRANSMITTER_CONTROL_ACTIAVATE ||
-+		cntl->action == TRANSMITTER_CONTROL_DEACTIVATE) {
-+		dm_logger_write(bp->base.ctx->logger, LOG_BIOS,\
-+		"%s:ps.param.symclk_10khz = %d\n",\
-+		__func__, ps.param.symclk_10khz);
-+	}
-+
-+
-+/*color_depth not used any more, driver has deep color factor in the Phyclk*/
-+	if (EXEC_BIOS_CMD_TABLE(dig1transmittercontrol, ps))
-+		result = BP_RESULT_OK;
-+	return result;
-+}
-+
-+/******************************************************************************
-+ ******************************************************************************
-+ **
-+ **                  SET PIXEL CLOCK
-+ **
-+ ******************************************************************************
-+ *****************************************************************************/
-+
-+static enum bp_result set_pixel_clock_v7(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
-+
-+static void init_set_pixel_clock(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(setpixelclock)) {
-+	case 7:
-+		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v7;
-+		break;
-+	default:
-+		bp->cmd_tbl.set_pixel_clock = NULL;
-+		break;
-+	}
-+}
-+
-+
-+
-+static enum bp_result set_pixel_clock_v7(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	struct set_pixel_clock_parameter_v1_7 clk;
-+	uint8_t controller_id;
-+	uint32_t pll_id;
-+
-+	memset(&clk, 0, sizeof(clk));
-+
-+	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
-+			&& bp->cmd_helper->controller_id_to_atom(bp_params->
-+					controller_id, &controller_id)) {
-+		/* Note: VBIOS still wants to use ucCRTC name which is now
-+		 * 1 byte in ULONG
-+		 *typedef struct _CRTC_PIXEL_CLOCK_FREQ
-+		 *{
-+		 * target the pixel clock to drive the CRTC timing.
-+		 * ULONG ulPixelClock:24;
-+		 * 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to
-+		 * previous version.
-+		 * ATOM_CRTC1~6, indicate the CRTC controller to
-+		 * ULONG ucCRTC:8;
-+		 * drive the pixel clock. not used for DCPLL case.
-+		 *}CRTC_PIXEL_CLOCK_FREQ;
-+		 *union
-+		 *{
-+		 * pixel clock and CRTC id frequency
-+		 * CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;
-+		 * ULONG ulDispEngClkFreq; dispclk frequency
-+		 *};
-+		 */
-+		clk.crtc_id = controller_id;
-+		clk.pll_id = (uint8_t) pll_id;
-+		clk.encoderobjid =
-+			bp->cmd_helper->encoder_id_to_atom(
-+				dal_graphics_object_id_get_encoder_id(
-+					bp_params->encoder_object_id));
-+
-+		clk.encoder_mode = (uint8_t) bp->
-+			cmd_helper->encoder_mode_bp_to_atom(
-+				bp_params->signal_type, false);
-+
-+		/* We need to convert from KHz units into 10KHz units */
-+		clk.pixclk_100hz = cpu_to_le32(bp_params->target_pixel_clock *
-+				10);
-+
-+		clk.deep_color_ratio =
-+			(uint8_t) bp->cmd_helper->
-+				transmitter_color_depth_to_atom(
-+					bp_params->color_depth);
-+		dm_logger_write(bp->base.ctx->logger, LOG_BIOS,\
-+				"%s:program display clock = %d"\
-+				"colorDepth = %d\n", __func__,\
-+				bp_params->target_pixel_clock, bp_params->color_depth);
-+
-+		if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
-+			clk.miscinfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL;
-+
-+		if (bp_params->flags.PROGRAM_PHY_PLL_ONLY)
-+			clk.miscinfo |= PIXEL_CLOCK_V7_MISC_PROG_PHYPLL;
-+
-+		if (bp_params->flags.SUPPORT_YUV_420)
-+			clk.miscinfo |= PIXEL_CLOCK_V7_MISC_YUV420_MODE;
-+
-+		if (bp_params->flags.SET_XTALIN_REF_SRC)
-+			clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN;
-+
-+		if (bp_params->flags.SET_GENLOCK_REF_DIV_SRC)
-+			clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK;
-+
-+		if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
-+			clk.miscinfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
-+
-+		if (EXEC_BIOS_CMD_TABLE(setpixelclock, clk))
-+			result = BP_RESULT_OK;
-+	}
-+	return result;
-+}
-+
-+/******************************************************************************
-+ ******************************************************************************
-+ **
-+ **                  SET CRTC TIMING
-+ **
-+ ******************************************************************************
-+ *****************************************************************************/
-+
-+static enum bp_result set_crtc_using_dtd_timing_v3(
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_timing_parameters *bp_params);
-+
-+static void init_set_crtc_timing(struct bios_parser *bp)
-+{
-+	uint32_t dtd_version =
-+			BIOS_CMD_TABLE_PARA_REVISION(setcrtc_usingdtdtiming);
-+
-+	switch (dtd_version) {
-+	case 3:
-+		bp->cmd_tbl.set_crtc_timing =
-+			set_crtc_using_dtd_timing_v3;
-+		break;
-+	default:
-+		bp->cmd_tbl.set_crtc_timing = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result set_crtc_using_dtd_timing_v3(
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_timing_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	struct set_crtc_using_dtd_timing_parameters params = {0};
-+	uint8_t atom_controller_id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(
-+			bp_params->controller_id, &atom_controller_id))
-+		params.crtc_id = atom_controller_id;
-+
-+	/* bios usH_Size wants h addressable size */
-+	params.h_size = cpu_to_le16((uint16_t)bp_params->h_addressable);
-+	/* bios usH_Blanking_Time wants borders included in blanking */
-+	params.h_blanking_time =
-+			cpu_to_le16((uint16_t)(bp_params->h_total -
-+					bp_params->h_addressable));
-+	/* bios usV_Size wants v addressable size */
-+	params.v_size = cpu_to_le16((uint16_t)bp_params->v_addressable);
-+	/* bios usV_Blanking_Time wants borders included in blanking */
-+	params.v_blanking_time =
-+			cpu_to_le16((uint16_t)(bp_params->v_total -
-+					bp_params->v_addressable));
-+	/* bios usHSyncOffset is the offset from the end of h addressable,
-+	 * our horizontalSyncStart is the offset from the beginning
-+	 * of h addressable
-+	 */
-+	params.h_syncoffset =
-+			cpu_to_le16((uint16_t)(bp_params->h_sync_start -
-+					bp_params->h_addressable));
-+	params.h_syncwidth = cpu_to_le16((uint16_t)bp_params->h_sync_width);
-+	/* bios usHSyncOffset is the offset from the end of v addressable,
-+	 * our verticalSyncStart is the offset from the beginning of
-+	 * v addressable
-+	 */
-+	params.v_syncoffset =
-+			cpu_to_le16((uint16_t)(bp_params->v_sync_start -
-+					bp_params->v_addressable));
-+	params.v_syncwidth = cpu_to_le16((uint16_t)bp_params->v_sync_width);
-+
-+	/* we assume that overscan from original timing does not get bigger
-+	 * than 255
-+	 * we will program all the borders in the Set CRTC Overscan call below
-+	 */
-+
-+	if (bp_params->flags.HSYNC_POSITIVE_POLARITY == 0)
-+		params.modemiscinfo =
-+				cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
-+						ATOM_HSYNC_POLARITY);
-+
-+	if (bp_params->flags.VSYNC_POSITIVE_POLARITY == 0)
-+		params.modemiscinfo =
-+				cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
-+						ATOM_VSYNC_POLARITY);
-+
-+	if (bp_params->flags.INTERLACE)	{
-+		params.modemiscinfo =
-+				cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
-+						ATOM_INTERLACE);
-+
-+		/* original DAL code has this condition to apply this
-+		 * for non-TV/CV only
-+		 * due to complex MV testing for possible impact
-+		 * if ( pACParameters->signal != SignalType_YPbPr &&
-+		 *  pACParameters->signal != SignalType_Composite &&
-+		 *  pACParameters->signal != SignalType_SVideo)
-+		 */
-+		{
-+			/* HW will deduct 0.5 line from 2nd feild.
-+			 * i.e. for 1080i, it is 2 lines for 1st field,
-+			 * 2.5 lines for the 2nd feild. we need input as 5
-+			 * instead of 4.
-+			 * but it is 4 either from Edid data (spec CEA 861)
-+			 * or CEA timing table.
-+			 */
-+			params.v_syncoffset =
-+				cpu_to_le16(le16_to_cpu(params.v_syncoffset) +
-+						1);
-+
-+		}
-+	}
-+
-+	if (bp_params->flags.HORZ_COUNT_BY_TWO)
-+		params.modemiscinfo =
-+			cpu_to_le16(le16_to_cpu(params.modemiscinfo) |
-+					0x100); /* ATOM_DOUBLE_CLOCK_MODE */
-+
-+	if (EXEC_BIOS_CMD_TABLE(setcrtc_usingdtdtiming, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/******************************************************************************
-+ ******************************************************************************
-+ **
-+ **                  SELECT CRTC SOURCE
-+ **
-+ ******************************************************************************
-+ *****************************************************************************/
-+
-+
-+static enum bp_result select_crtc_source_v3(
-+	struct bios_parser *bp,
-+	struct bp_crtc_source_select *bp_params);
-+
-+static void init_select_crtc_source(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(selectcrtc_source)) {
-+	case 3:
-+		bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
-+		break;
-+	default:
-+		bp->cmd_tbl.select_crtc_source = NULL;
-+		break;
-+	}
-+}
-+
-+
-+static enum bp_result select_crtc_source_v3(
-+	struct bios_parser *bp,
-+	struct bp_crtc_source_select *bp_params)
-+{
-+	bool result = BP_RESULT_FAILURE;
-+	struct select_crtc_source_parameters_v2_3 params;
-+	uint8_t atom_controller_id;
-+	uint32_t atom_engine_id;
-+	enum signal_type s = bp_params->signal;
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
-+			&atom_controller_id))
-+		params.crtc_id = atom_controller_id;
-+	else
-+		return result;
-+
-+	if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id,
-+			&atom_engine_id))
-+		params.encoder_id = (uint8_t)atom_engine_id;
-+	else
-+		return result;
-+
-+	if (s == SIGNAL_TYPE_EDP ||
-+		(s == SIGNAL_TYPE_DISPLAY_PORT && bp_params->sink_signal ==
-+							SIGNAL_TYPE_LVDS))
-+		s = SIGNAL_TYPE_LVDS;
-+
-+	params.encode_mode =
-+			bp->cmd_helper->encoder_mode_bp_to_atom(
-+					s, bp_params->enable_dp_audio);
-+	/* Needed for VBIOS Random Spatial Dithering feature */
-+	params.dst_bpc = (uint8_t)(bp_params->display_output_bit_depth);
-+
-+	if (EXEC_BIOS_CMD_TABLE(selectcrtc_source, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/******************************************************************************
-+ ******************************************************************************
-+ **
-+ **                  ENABLE CRTC
-+ **
-+ ******************************************************************************
-+ *****************************************************************************/
-+
-+static enum bp_result enable_crtc_v1(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	bool enable);
-+
-+static void init_enable_crtc(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(enablecrtc)) {
-+	case 1:
-+		bp->cmd_tbl.enable_crtc = enable_crtc_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.enable_crtc = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result enable_crtc_v1(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	bool enable)
-+{
-+	bool result = BP_RESULT_FAILURE;
-+	struct enable_crtc_parameters params = {0};
-+	uint8_t id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(controller_id, &id))
-+		params.crtc_id = id;
-+	else
-+		return BP_RESULT_BADINPUT;
-+
-+	if (enable)
-+		params.enable = ATOM_ENABLE;
-+	else
-+		params.enable = ATOM_DISABLE;
-+
-+	if (EXEC_BIOS_CMD_TABLE(enablecrtc, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/******************************************************************************
-+ ******************************************************************************
-+ **
-+ **                  DISPLAY PLL
-+ **
-+ ******************************************************************************
-+ *****************************************************************************/
-+
-+
-+
-+/******************************************************************************
-+ ******************************************************************************
-+ **
-+ **                  EXTERNAL ENCODER CONTROL
-+ **
-+ ******************************************************************************
-+ *****************************************************************************/
-+
-+static enum bp_result external_encoder_control_v3(
-+	struct bios_parser *bp,
-+	struct bp_external_encoder_control *cntl);
-+
-+static void init_external_encoder_control(
-+	struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(externalencodercontrol)) {
-+	case 3:
-+		bp->cmd_tbl.external_encoder_control =
-+				external_encoder_control_v3;
-+		break;
-+	default:
-+		bp->cmd_tbl.external_encoder_control = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result external_encoder_control_v3(
-+	struct bios_parser *bp,
-+	struct bp_external_encoder_control *cntl)
-+{
-+	/* TODO */
-+	return BP_RESULT_OK;
-+}
-+
-+/******************************************************************************
-+ ******************************************************************************
-+ **
-+ **                  ENABLE DISPLAY POWER GATING
-+ **
-+ ******************************************************************************
-+ *****************************************************************************/
-+
-+static enum bp_result enable_disp_power_gating_v2_1(
-+	struct bios_parser *bp,
-+	enum controller_id crtc_id,
-+	enum bp_pipe_control_action action);
-+
-+static void init_enable_disp_power_gating(
-+	struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating)) {
-+	case 1:
-+		bp->cmd_tbl.enable_disp_power_gating =
-+				enable_disp_power_gating_v2_1;
-+		break;
-+	default:
-+		bp->cmd_tbl.enable_disp_power_gating = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result enable_disp_power_gating_v2_1(
-+	struct bios_parser *bp,
-+	enum controller_id crtc_id,
-+	enum bp_pipe_control_action action)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+
-+
-+	struct enable_disp_power_gating_ps_allocation ps = { { 0 } };
-+	uint8_t atom_crtc_id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(crtc_id, &atom_crtc_id))
-+		ps.param.disp_pipe_id = atom_crtc_id;
-+	else
-+		return BP_RESULT_BADINPUT;
-+
-+	ps.param.enable =
-+		bp->cmd_helper->disp_power_gating_action_to_atom(action);
-+
-+	if (EXEC_BIOS_CMD_TABLE(enabledisppowergating, ps.param))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/******************************************************************************
-+*******************************************************************************
-+ **
-+ **                  SET DCE CLOCK
-+ **
-+*******************************************************************************
-+*******************************************************************************/
-+
-+static enum bp_result set_dce_clock_v2_1(
-+	struct bios_parser *bp,
-+	struct bp_set_dce_clock_parameters *bp_params);
-+
-+static void init_set_dce_clock(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(setdceclock)) {
-+	case 1:
-+		bp->cmd_tbl.set_dce_clock = set_dce_clock_v2_1;
-+		break;
-+	default:
-+		bp->cmd_tbl.set_dce_clock = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result set_dce_clock_v2_1(
-+	struct bios_parser *bp,
-+	struct bp_set_dce_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+
-+	struct set_dce_clock_ps_allocation_v2_1 params;
-+	uint32_t atom_pll_id;
-+	uint32_t atom_clock_type;
-+	const struct command_table_helper *cmd = bp->cmd_helper;
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	if (!cmd->clock_source_id_to_atom(bp_params->pll_id, &atom_pll_id) ||
-+			!cmd->dc_clock_type_to_atom(bp_params->clock_type,
-+					&atom_clock_type))
-+		return BP_RESULT_BADINPUT;
-+
-+	params.param.dceclksrc  = atom_pll_id;
-+	params.param.dceclktype = atom_clock_type;
-+
-+	if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) {
-+		if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK)
-+			params.param.dceclkflag |=
-+					DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK;
-+
-+		if (bp_params->flags.USE_PCIE_AS_SOURCE_FOR_DPREFCLK)
-+			params.param.dceclkflag |=
-+					DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE;
-+
-+		if (bp_params->flags.USE_XTALIN_AS_SOURCE_FOR_DPREFCLK)
-+			params.param.dceclkflag |=
-+					DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN;
-+
-+		if (bp_params->flags.USE_GENERICA_AS_SOURCE_FOR_DPREFCLK)
-+			params.param.dceclkflag |=
-+					DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA;
-+	} else
-+		/* only program clock frequency if display clock is used;
-+		 * VBIOS will program DPREFCLK
-+		 * We need to convert from KHz units into 10KHz units
-+		 */
-+		params.param.dceclk_10khz = cpu_to_le32(
-+				bp_params->target_clock_frequency / 10);
-+	dm_logger_write(bp->base.ctx->logger, LOG_BIOS,
-+			"%s:target_clock_frequency = %d"\
-+			"clock_type = %d \n", __func__,\
-+			bp_params->target_clock_frequency,\
-+			bp_params->clock_type);
-+
-+	if (EXEC_BIOS_CMD_TABLE(setdceclock, params)) {
-+		/* Convert from 10KHz units back to KHz */
-+		bp_params->target_clock_frequency = le32_to_cpu(
-+				params.param.dceclk_10khz) * 10;
-+		result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
-+
-+
-+/******************************************************************************
-+ ******************************************************************************
-+ **
-+ **                  GET SMU CLOCK INFO
-+ **
-+ ******************************************************************************
-+ *****************************************************************************/
-+
-+static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp);
-+
-+static void init_get_smu_clock_info(struct bios_parser *bp)
-+{
-+	/* TODO add switch for table vrsion */
-+	bp->cmd_tbl.get_smu_clock_info = get_smu_clock_info_v3_1;
-+
-+}
-+
-+static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp)
-+{
-+	struct atom_get_smu_clock_info_parameters_v3_1 smu_input = {0};
-+	struct atom_get_smu_clock_info_output_parameters_v3_1 smu_output;
-+
-+	smu_input.command = GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ;
-+
-+	/* Get Specific Clock */
-+	if (EXEC_BIOS_CMD_TABLE(getsmuclockinfo, smu_input)) {
-+		memmove(&smu_output, &smu_input, sizeof(
-+			struct atom_get_smu_clock_info_parameters_v3_1));
-+		return smu_output.atom_smu_outputclkfreq.syspllvcofreq_10khz;
-+	}
-+
-+	return 0;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table2.h.0130~	2017-12-14 06:39:58.400903557 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table2.h	2017-12-14 06:39:58.400903557 +0100
-@@ -0,0 +1,105 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMMAND_TABLE2_H__
-+#define __DAL_COMMAND_TABLE2_H__
-+
-+struct bios_parser;
-+struct bp_encoder_control;
-+
-+struct cmd_tbl {
-+	enum bp_result (*dig_encoder_control)(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *control);
-+	enum bp_result (*encoder_control_dig1)(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *control);
-+	enum bp_result (*encoder_control_dig2)(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *control);
-+	enum bp_result (*transmitter_control)(
-+		struct bios_parser *bp,
-+		struct bp_transmitter_control *control);
-+	enum bp_result (*set_pixel_clock)(
-+		struct bios_parser *bp,
-+		struct bp_pixel_clock_parameters *bp_params);
-+	enum bp_result (*enable_spread_spectrum_on_ppll)(
-+		struct bios_parser *bp,
-+		struct bp_spread_spectrum_parameters *bp_params,
-+		bool enable);
-+	enum bp_result (*adjust_display_pll)(
-+		struct bios_parser *bp,
-+		struct bp_adjust_pixel_clock_parameters *bp_params);
-+	enum bp_result (*dac1_encoder_control)(
-+		struct bios_parser *bp,
-+		bool enable,
-+		uint32_t pixel_clock,
-+		uint8_t dac_standard);
-+	enum bp_result (*dac2_encoder_control)(
-+		struct bios_parser *bp,
-+		bool enable,
-+		uint32_t pixel_clock,
-+		uint8_t dac_standard);
-+	enum bp_result (*dac1_output_control)(
-+		struct bios_parser *bp,
-+		bool enable);
-+	enum bp_result (*dac2_output_control)(
-+		struct bios_parser *bp,
-+		bool enable);
-+	enum bp_result (*set_crtc_timing)(
-+		struct bios_parser *bp,
-+		struct bp_hw_crtc_timing_parameters *bp_params);
-+	enum bp_result (*select_crtc_source)(
-+		struct bios_parser *bp,
-+		struct bp_crtc_source_select *bp_params);
-+	enum bp_result (*enable_crtc)(
-+		struct bios_parser *bp,
-+		enum controller_id controller_id,
-+		bool enable);
-+	enum bp_result (*enable_crtc_mem_req)(
-+		struct bios_parser *bp,
-+		enum controller_id controller_id,
-+		bool enable);
-+	enum bp_result (*program_clock)(
-+		struct bios_parser *bp,
-+		struct bp_pixel_clock_parameters *bp_params);
-+	enum bp_result (*external_encoder_control)(
-+			struct bios_parser *bp,
-+			struct bp_external_encoder_control *cntl);
-+	enum bp_result (*enable_disp_power_gating)(
-+		struct bios_parser *bp,
-+		enum controller_id crtc_id,
-+		enum bp_pipe_control_action action);
-+	enum bp_result (*set_dce_clock)(
-+		struct bios_parser *bp,
-+		struct bp_set_dce_clock_parameters *bp_params);
-+	unsigned int (*get_smu_clock_info)(
-+			struct bios_parser *bp);
-+
-+};
-+
-+void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table.c.0130~	2017-12-14 06:39:58.401903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table.c	2017-12-14 06:39:58.401903558 +0100
-@@ -0,0 +1,2424 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/bios_parser_interface.h"
-+
-+#include "command_table.h"
-+#include "command_table_helper.h"
-+#include "bios_parser_helper.h"
-+#include "bios_parser_types_internal.h"
-+
-+#define EXEC_BIOS_CMD_TABLE(command, params)\
-+	(cgs_atom_exec_cmd_table(bp->base.ctx->cgs_device, \
-+		GetIndexIntoMasterTable(COMMAND, command), \
-+		&params) == 0)
-+
-+#define BIOS_CMD_TABLE_REVISION(command, frev, crev)\
-+	cgs_atom_get_cmd_table_revs(bp->base.ctx->cgs_device, \
-+		GetIndexIntoMasterTable(COMMAND, command), &frev, &crev)
-+
-+#define BIOS_CMD_TABLE_PARA_REVISION(command)\
-+	bios_cmd_table_para_revision(bp->base.ctx->cgs_device, \
-+		GetIndexIntoMasterTable(COMMAND, command))
-+
-+static void init_dig_encoder_control(struct bios_parser *bp);
-+static void init_transmitter_control(struct bios_parser *bp);
-+static void init_set_pixel_clock(struct bios_parser *bp);
-+static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp);
-+static void init_adjust_display_pll(struct bios_parser *bp);
-+static void init_dac_encoder_control(struct bios_parser *bp);
-+static void init_dac_output_control(struct bios_parser *bp);
-+static void init_set_crtc_timing(struct bios_parser *bp);
-+static void init_select_crtc_source(struct bios_parser *bp);
-+static void init_enable_crtc(struct bios_parser *bp);
-+static void init_enable_crtc_mem_req(struct bios_parser *bp);
-+static void init_external_encoder_control(struct bios_parser *bp);
-+static void init_enable_disp_power_gating(struct bios_parser *bp);
-+static void init_program_clock(struct bios_parser *bp);
-+static void init_set_dce_clock(struct bios_parser *bp);
-+
-+void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
-+{
-+	init_dig_encoder_control(bp);
-+	init_transmitter_control(bp);
-+	init_set_pixel_clock(bp);
-+	init_enable_spread_spectrum_on_ppll(bp);
-+	init_adjust_display_pll(bp);
-+	init_dac_encoder_control(bp);
-+	init_dac_output_control(bp);
-+	init_set_crtc_timing(bp);
-+	init_select_crtc_source(bp);
-+	init_enable_crtc(bp);
-+	init_enable_crtc_mem_req(bp);
-+	init_program_clock(bp);
-+	init_external_encoder_control(bp);
-+	init_enable_disp_power_gating(bp);
-+	init_set_dce_clock(bp);
-+}
-+
-+static uint32_t bios_cmd_table_para_revision(void *cgs_device,
-+					     uint32_t index)
-+{
-+	uint8_t frev, crev;
-+
-+	if (cgs_atom_get_cmd_table_revs(cgs_device,
-+					index,
-+					&frev, &crev) != 0)
-+		return 0;
-+	return crev;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  D I G E N C O D E R C O N T R O L
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+static enum bp_result encoder_control_digx_v3(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl);
-+
-+static enum bp_result encoder_control_digx_v4(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl);
-+
-+static enum bp_result encoder_control_digx_v5(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl);
-+
-+static void init_encoder_control_dig_v1(struct bios_parser *bp);
-+
-+static void init_dig_encoder_control(struct bios_parser *bp)
-+{
-+	uint32_t version =
-+		BIOS_CMD_TABLE_PARA_REVISION(DIGxEncoderControl);
-+
-+	switch (version) {
-+	case 2:
-+		bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v3;
-+		break;
-+	case 4:
-+		bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v4;
-+		break;
-+
-+	case 5:
-+		bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v5;
-+		break;
-+
-+	default:
-+		init_encoder_control_dig_v1(bp);
-+		break;
-+	}
-+}
-+
-+static enum bp_result encoder_control_dig_v1(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl);
-+static enum bp_result encoder_control_dig1_v1(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl);
-+static enum bp_result encoder_control_dig2_v1(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl);
-+
-+static void init_encoder_control_dig_v1(struct bios_parser *bp)
-+{
-+	struct cmd_tbl *cmd_tbl = &bp->cmd_tbl;
-+
-+	if (1 == BIOS_CMD_TABLE_PARA_REVISION(DIG1EncoderControl))
-+		cmd_tbl->encoder_control_dig1 = encoder_control_dig1_v1;
-+	else
-+		cmd_tbl->encoder_control_dig1 = NULL;
-+
-+	if (1 == BIOS_CMD_TABLE_PARA_REVISION(DIG2EncoderControl))
-+		cmd_tbl->encoder_control_dig2 = encoder_control_dig2_v1;
-+	else
-+		cmd_tbl->encoder_control_dig2 = NULL;
-+
-+	cmd_tbl->dig_encoder_control = encoder_control_dig_v1;
-+}
-+
-+static enum bp_result encoder_control_dig_v1(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	struct cmd_tbl *cmd_tbl = &bp->cmd_tbl;
-+
-+	if (cntl != NULL)
-+		switch (cntl->engine_id) {
-+		case ENGINE_ID_DIGA:
-+			if (cmd_tbl->encoder_control_dig1 != NULL)
-+				result =
-+					cmd_tbl->encoder_control_dig1(bp, cntl);
-+			break;
-+		case ENGINE_ID_DIGB:
-+			if (cmd_tbl->encoder_control_dig2 != NULL)
-+				result =
-+					cmd_tbl->encoder_control_dig2(bp, cntl);
-+			break;
-+
-+		default:
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static enum bp_result encoder_control_dig1_v1(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DIG_ENCODER_CONTROL_PARAMETERS_V2 params = {0};
-+
-+	bp->cmd_helper->assign_control_parameter(bp->cmd_helper, cntl, &params);
-+
-+	if (EXEC_BIOS_CMD_TABLE(DIG1EncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result encoder_control_dig2_v1(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DIG_ENCODER_CONTROL_PARAMETERS_V2 params = {0};
-+
-+	bp->cmd_helper->assign_control_parameter(bp->cmd_helper, cntl, &params);
-+
-+	if (EXEC_BIOS_CMD_TABLE(DIG2EncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result encoder_control_digx_v3(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DIG_ENCODER_CONTROL_PARAMETERS_V3 params = {0};
-+
-+	if (LANE_COUNT_FOUR < cntl->lanes_number)
-+		params.acConfig.ucDPLinkRate = 1; /* dual link 2.7GHz */
-+	else
-+		params.acConfig.ucDPLinkRate = 0; /* single link 1.62GHz */
-+
-+	params.acConfig.ucDigSel = (uint8_t)(cntl->engine_id);
-+
-+	/* We need to convert from KHz units into 10KHz units */
-+	params.ucAction = bp->cmd_helper->encoder_action_to_atom(cntl->action);
-+	params.usPixelClock = cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+	params.ucEncoderMode =
-+			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+					cntl->signal,
-+					cntl->enable_dp_audio);
-+	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
-+
-+	if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result encoder_control_digx_v4(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DIG_ENCODER_CONTROL_PARAMETERS_V4 params = {0};
-+
-+	if (LANE_COUNT_FOUR < cntl->lanes_number)
-+		params.acConfig.ucDPLinkRate = 1; /* dual link 2.7GHz */
-+	else
-+		params.acConfig.ucDPLinkRate = 0; /* single link 1.62GHz */
-+
-+	params.acConfig.ucDigSel = (uint8_t)(cntl->engine_id);
-+
-+	/* We need to convert from KHz units into 10KHz units */
-+	params.ucAction = bp->cmd_helper->encoder_action_to_atom(cntl->action);
-+	params.usPixelClock = cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+	params.ucEncoderMode =
-+			(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
-+					cntl->signal,
-+					cntl->enable_dp_audio));
-+	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
-+
-+	if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result encoder_control_digx_v5(
-+	struct bios_parser *bp,
-+	struct bp_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	ENCODER_STREAM_SETUP_PARAMETERS_V5 params = {0};
-+
-+	params.ucDigId = (uint8_t)(cntl->engine_id);
-+	params.ucAction = bp->cmd_helper->encoder_action_to_atom(cntl->action);
-+
-+	params.ulPixelClock = cntl->pixel_clock / 10;
-+	params.ucDigMode =
-+			(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
-+					cntl->signal,
-+					cntl->enable_dp_audio));
-+	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
-+
-+	switch (cntl->color_depth) {
-+	case COLOR_DEPTH_888:
-+		params.ucBitPerColor = PANEL_8BIT_PER_COLOR;
-+		break;
-+	case COLOR_DEPTH_101010:
-+		params.ucBitPerColor = PANEL_10BIT_PER_COLOR;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		params.ucBitPerColor = PANEL_12BIT_PER_COLOR;
-+		break;
-+	case COLOR_DEPTH_161616:
-+		params.ucBitPerColor = PANEL_16BIT_PER_COLOR;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+		switch (cntl->color_depth) {
-+		case COLOR_DEPTH_101010:
-+			params.ulPixelClock =
-+				(params.ulPixelClock * 30) / 24;
-+			break;
-+		case COLOR_DEPTH_121212:
-+			params.ulPixelClock =
-+				(params.ulPixelClock * 36) / 24;
-+			break;
-+		case COLOR_DEPTH_161616:
-+			params.ulPixelClock =
-+				(params.ulPixelClock * 48) / 24;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+	if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  TRANSMITTER CONTROL
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+
-+static enum bp_result transmitter_control_v2(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl);
-+static enum bp_result transmitter_control_v3(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl);
-+static enum bp_result transmitter_control_v4(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl);
-+static enum bp_result transmitter_control_v1_5(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl);
-+static enum bp_result transmitter_control_v1_6(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl);
-+
-+static void init_transmitter_control(struct bios_parser *bp)
-+{
-+	uint8_t frev;
-+	uint8_t crev;
-+
-+	if (BIOS_CMD_TABLE_REVISION(UNIPHYTransmitterControl,
-+			frev, crev) != 0)
-+		BREAK_TO_DEBUGGER();
-+	switch (crev) {
-+	case 2:
-+		bp->cmd_tbl.transmitter_control = transmitter_control_v2;
-+		break;
-+	case 3:
-+		bp->cmd_tbl.transmitter_control = transmitter_control_v3;
-+		break;
-+	case 4:
-+		bp->cmd_tbl.transmitter_control = transmitter_control_v4;
-+		break;
-+	case 5:
-+		bp->cmd_tbl.transmitter_control = transmitter_control_v1_5;
-+		break;
-+	case 6:
-+		bp->cmd_tbl.transmitter_control = transmitter_control_v1_6;
-+		break;
-+	default:
-+		bp->cmd_tbl.transmitter_control = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result transmitter_control_v2(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 params;
-+	enum connector_id connector_id =
-+		dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	switch (cntl->transmitter) {
-+	case TRANSMITTER_UNIPHY_A:
-+	case TRANSMITTER_UNIPHY_B:
-+	case TRANSMITTER_UNIPHY_C:
-+	case TRANSMITTER_UNIPHY_D:
-+	case TRANSMITTER_UNIPHY_E:
-+	case TRANSMITTER_UNIPHY_F:
-+	case TRANSMITTER_TRAVIS_LCD:
-+		break;
-+	default:
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	switch (cntl->action) {
-+	case TRANSMITTER_CONTROL_INIT:
-+		if ((CONNECTOR_ID_DUAL_LINK_DVII == connector_id) ||
-+				(CONNECTOR_ID_DUAL_LINK_DVID == connector_id))
-+			/* on INIT this bit should be set according to the
-+			 * phisycal connector
-+			 * Bit0: dual link connector flag
-+			 * =0 connector is single link connector
-+			 * =1 connector is dual link connector
-+			 */
-+			params.acConfig.fDualLinkConnector = 1;
-+
-+		/* connector object id */
-+		params.usInitInfo =
-+				cpu_to_le16((uint8_t)cntl->connector_obj_id.id);
-+		break;
-+	case TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS:
-+		/* votage swing and pre-emphsis */
-+		params.asMode.ucLaneSel = (uint8_t)cntl->lane_select;
-+		params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings;
-+		break;
-+	default:
-+		/* if dual-link */
-+		if (LANE_COUNT_FOUR < cntl->lanes_number) {
-+			/* on ENABLE/DISABLE this bit should be set according to
-+			 * actual timing (number of lanes)
-+			 * Bit0: dual link connector flag
-+			 * =0 connector is single link connector
-+			 * =1 connector is dual link connector
-+			 */
-+			params.acConfig.fDualLinkConnector = 1;
-+
-+			/* link rate, half for dual link
-+			 * We need to convert from KHz units into 20KHz units
-+			 */
-+			params.usPixelClock =
-+					cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
-+		} else
-+			/* link rate, half for dual link
-+			 * We need to convert from KHz units into 10KHz units
-+			 */
-+			params.usPixelClock =
-+					cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+		break;
-+	}
-+
-+	/* 00 - coherent mode
-+	 * 01 - incoherent mode
-+	 */
-+
-+	params.acConfig.fCoherentMode = cntl->coherent;
-+
-+	if ((TRANSMITTER_UNIPHY_B == cntl->transmitter)
-+			|| (TRANSMITTER_UNIPHY_D == cntl->transmitter)
-+			|| (TRANSMITTER_UNIPHY_F == cntl->transmitter))
-+		/* Bit2: Transmitter Link selection
-+		 * =0 when bit0=0, single link A/C/E, when bit0=1,
-+		 * master link A/C/E
-+		 * =1 when bit0=0, single link B/D/F, when bit0=1,
-+		 * master link B/D/F
-+		 */
-+		params.acConfig.ucLinkSel = 1;
-+
-+	if (ENGINE_ID_DIGB == cntl->engine_id)
-+		/* Bit3: Transmitter data source selection
-+		 * =0 DIGA is data source.
-+		 * =1 DIGB is data source.
-+		 * This bit is only useful when ucAction= ATOM_ENABLE
-+		 */
-+		params.acConfig.ucEncoderSel = 1;
-+
-+	if (CONNECTOR_ID_DISPLAY_PORT == connector_id)
-+		/* Bit4: DP connector flag
-+		 * =0 connector is none-DP connector
-+		 * =1 connector is DP connector
-+		 */
-+		params.acConfig.fDPConnector = 1;
-+
-+	/* Bit[7:6]: Transmitter selection
-+	 * =0 UNIPHY_ENCODER: UNIPHYA/B
-+	 * =1 UNIPHY1_ENCODER: UNIPHYC/D
-+	 * =2 UNIPHY2_ENCODER: UNIPHYE/F
-+	 * =3 reserved
-+	 */
-+	params.acConfig.ucTransmitterSel =
-+			(uint8_t)bp->cmd_helper->transmitter_bp_to_atom(
-+					cntl->transmitter);
-+
-+	params.ucAction = (uint8_t)cntl->action;
-+
-+	if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result transmitter_control_v3(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 params;
-+	uint32_t pll_id;
-+	enum connector_id conn_id =
-+			dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
-+	const struct command_table_helper *cmd = bp->cmd_helper;
-+	bool dual_link_conn = (CONNECTOR_ID_DUAL_LINK_DVII == conn_id)
-+					|| (CONNECTOR_ID_DUAL_LINK_DVID == conn_id);
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	switch (cntl->transmitter) {
-+	case TRANSMITTER_UNIPHY_A:
-+	case TRANSMITTER_UNIPHY_B:
-+	case TRANSMITTER_UNIPHY_C:
-+	case TRANSMITTER_UNIPHY_D:
-+	case TRANSMITTER_UNIPHY_E:
-+	case TRANSMITTER_UNIPHY_F:
-+	case TRANSMITTER_TRAVIS_LCD:
-+		break;
-+	default:
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	if (!cmd->clock_source_id_to_atom(cntl->pll_id, &pll_id))
-+		return BP_RESULT_BADINPUT;
-+
-+	/* fill information based on the action */
-+	switch (cntl->action) {
-+	case TRANSMITTER_CONTROL_INIT:
-+		if (dual_link_conn) {
-+			/* on INIT this bit should be set according to the
-+			 * phisycal connector
-+			 * Bit0: dual link connector flag
-+			 * =0 connector is single link connector
-+			 * =1 connector is dual link connector
-+			 */
-+			params.acConfig.fDualLinkConnector = 1;
-+		}
-+
-+		/* connector object id */
-+		params.usInitInfo =
-+				cpu_to_le16((uint8_t)(cntl->connector_obj_id.id));
-+		break;
-+	case TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS:
-+		/* votage swing and pre-emphsis */
-+		params.asMode.ucLaneSel = (uint8_t)cntl->lane_select;
-+		params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings;
-+		break;
-+	default:
-+		if (dual_link_conn && cntl->multi_path)
-+			/* on ENABLE/DISABLE this bit should be set according to
-+			 * actual timing (number of lanes)
-+			 * Bit0: dual link connector flag
-+			 * =0 connector is single link connector
-+			 * =1 connector is dual link connector
-+			 */
-+			params.acConfig.fDualLinkConnector = 1;
-+
-+		/* if dual-link */
-+		if (LANE_COUNT_FOUR < cntl->lanes_number) {
-+			/* on ENABLE/DISABLE this bit should be set according to
-+			 * actual timing (number of lanes)
-+			 * Bit0: dual link connector flag
-+			 * =0 connector is single link connector
-+			 * =1 connector is dual link connector
-+			 */
-+			params.acConfig.fDualLinkConnector = 1;
-+
-+			/* link rate, half for dual link
-+			 * We need to convert from KHz units into 20KHz units
-+			 */
-+			params.usPixelClock =
-+					cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
-+		} else {
-+			/* link rate, half for dual link
-+			 * We need to convert from KHz units into 10KHz units
-+			 */
-+			params.usPixelClock =
-+					cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+		}
-+		break;
-+	}
-+
-+	/* 00 - coherent mode
-+	 * 01 - incoherent mode
-+	 */
-+
-+	params.acConfig.fCoherentMode = cntl->coherent;
-+
-+	if ((TRANSMITTER_UNIPHY_B == cntl->transmitter)
-+		|| (TRANSMITTER_UNIPHY_D == cntl->transmitter)
-+		|| (TRANSMITTER_UNIPHY_F == cntl->transmitter))
-+		/* Bit2: Transmitter Link selection
-+		 * =0 when bit0=0, single link A/C/E, when bit0=1,
-+		 * master link A/C/E
-+		 * =1 when bit0=0, single link B/D/F, when bit0=1,
-+		 * master link B/D/F
-+		 */
-+		params.acConfig.ucLinkSel = 1;
-+
-+	if (ENGINE_ID_DIGB == cntl->engine_id)
-+		/* Bit3: Transmitter data source selection
-+		 * =0 DIGA is data source.
-+		 * =1 DIGB is data source.
-+		 * This bit is only useful when ucAction= ATOM_ENABLE
-+		 */
-+		params.acConfig.ucEncoderSel = 1;
-+
-+	/* Bit[7:6]: Transmitter selection
-+	 * =0 UNIPHY_ENCODER: UNIPHYA/B
-+	 * =1 UNIPHY1_ENCODER: UNIPHYC/D
-+	 * =2 UNIPHY2_ENCODER: UNIPHYE/F
-+	 * =3 reserved
-+	 */
-+	params.acConfig.ucTransmitterSel =
-+			(uint8_t)cmd->transmitter_bp_to_atom(cntl->transmitter);
-+
-+	params.ucLaneNum = (uint8_t)cntl->lanes_number;
-+
-+	params.acConfig.ucRefClkSource = (uint8_t)pll_id;
-+
-+	params.ucAction = (uint8_t)cntl->action;
-+
-+	if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result transmitter_control_v4(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 params;
-+	uint32_t ref_clk_src_id;
-+	enum connector_id conn_id =
-+			dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
-+	const struct command_table_helper *cmd = bp->cmd_helper;
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	switch (cntl->transmitter) {
-+	case TRANSMITTER_UNIPHY_A:
-+	case TRANSMITTER_UNIPHY_B:
-+	case TRANSMITTER_UNIPHY_C:
-+	case TRANSMITTER_UNIPHY_D:
-+	case TRANSMITTER_UNIPHY_E:
-+	case TRANSMITTER_UNIPHY_F:
-+	case TRANSMITTER_TRAVIS_LCD:
-+		break;
-+	default:
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	if (!cmd->clock_source_id_to_ref_clk_src(cntl->pll_id, &ref_clk_src_id))
-+		return BP_RESULT_BADINPUT;
-+
-+	switch (cntl->action) {
-+	case TRANSMITTER_CONTROL_INIT:
-+	{
-+		if ((CONNECTOR_ID_DUAL_LINK_DVII == conn_id) ||
-+				(CONNECTOR_ID_DUAL_LINK_DVID == conn_id))
-+			/* on INIT this bit should be set according to the
-+			 * phisycal connector
-+			 * Bit0: dual link connector flag
-+			 * =0 connector is single link connector
-+			 * =1 connector is dual link connector
-+			 */
-+			params.acConfig.fDualLinkConnector = 1;
-+
-+		/* connector object id */
-+		params.usInitInfo =
-+				cpu_to_le16((uint8_t)(cntl->connector_obj_id.id));
-+	}
-+	break;
-+	case TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS:
-+		/* votage swing and pre-emphsis */
-+		params.asMode.ucLaneSel = (uint8_t)(cntl->lane_select);
-+		params.asMode.ucLaneSet = (uint8_t)(cntl->lane_settings);
-+		break;
-+	default:
-+		if ((CONNECTOR_ID_DUAL_LINK_DVII == conn_id) ||
-+				(CONNECTOR_ID_DUAL_LINK_DVID == conn_id))
-+			/* on ENABLE/DISABLE this bit should be set according to
-+			 * actual timing (number of lanes)
-+			 * Bit0: dual link connector flag
-+			 * =0 connector is single link connector
-+			 * =1 connector is dual link connector
-+			 */
-+			params.acConfig.fDualLinkConnector = 1;
-+
-+		/* if dual-link */
-+		if (LANE_COUNT_FOUR < cntl->lanes_number)
-+			/* link rate, half for dual link
-+			 * We need to convert from KHz units into 20KHz units
-+			 */
-+			params.usPixelClock =
-+					cpu_to_le16((uint16_t)(cntl->pixel_clock / 20));
-+		else {
-+			/* link rate, half for dual link
-+			 * We need to convert from KHz units into 10KHz units
-+			 */
-+			params.usPixelClock =
-+					cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+		}
-+		break;
-+	}
-+
-+	/* 00 - coherent mode
-+	 * 01 - incoherent mode
-+	 */
-+
-+	params.acConfig.fCoherentMode = cntl->coherent;
-+
-+	if ((TRANSMITTER_UNIPHY_B == cntl->transmitter)
-+		|| (TRANSMITTER_UNIPHY_D == cntl->transmitter)
-+		|| (TRANSMITTER_UNIPHY_F == cntl->transmitter))
-+		/* Bit2: Transmitter Link selection
-+		 * =0 when bit0=0, single link A/C/E, when bit0=1,
-+		 * master link A/C/E
-+		 * =1 when bit0=0, single link B/D/F, when bit0=1,
-+		 * master link B/D/F
-+		 */
-+		params.acConfig.ucLinkSel = 1;
-+
-+	if (ENGINE_ID_DIGB == cntl->engine_id)
-+		/* Bit3: Transmitter data source selection
-+		 * =0 DIGA is data source.
-+		 * =1 DIGB is data source.
-+		 * This bit is only useful when ucAction= ATOM_ENABLE
-+		 */
-+		params.acConfig.ucEncoderSel = 1;
-+
-+	/* Bit[7:6]: Transmitter selection
-+	 * =0 UNIPHY_ENCODER: UNIPHYA/B
-+	 * =1 UNIPHY1_ENCODER: UNIPHYC/D
-+	 * =2 UNIPHY2_ENCODER: UNIPHYE/F
-+	 * =3 reserved
-+	 */
-+	params.acConfig.ucTransmitterSel =
-+		(uint8_t)(cmd->transmitter_bp_to_atom(cntl->transmitter));
-+	params.ucLaneNum = (uint8_t)(cntl->lanes_number);
-+	params.acConfig.ucRefClkSource = (uint8_t)(ref_clk_src_id);
-+	params.ucAction = (uint8_t)(cntl->action);
-+
-+	if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result transmitter_control_v1_5(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	const struct command_table_helper *cmd = bp->cmd_helper;
-+	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 params;
-+
-+	memset(&params, 0, sizeof(params));
-+	params.ucPhyId = cmd->phy_id_to_atom(cntl->transmitter);
-+	params.ucAction = (uint8_t)cntl->action;
-+	params.ucLaneNum = (uint8_t)cntl->lanes_number;
-+	params.ucConnObjId = (uint8_t)cntl->connector_obj_id.id;
-+
-+	params.ucDigMode =
-+		cmd->signal_type_to_atom_dig_mode(cntl->signal);
-+	params.asConfig.ucPhyClkSrcId =
-+		cmd->clock_source_id_to_atom_phy_clk_src_id(cntl->pll_id);
-+	/* 00 - coherent mode */
-+	params.asConfig.ucCoherentMode = cntl->coherent;
-+	params.asConfig.ucHPDSel =
-+		cmd->hpd_sel_to_atom(cntl->hpd_sel);
-+	params.ucDigEncoderSel =
-+		cmd->dig_encoder_sel_to_atom(cntl->engine_id);
-+	params.ucDPLaneSet = (uint8_t) cntl->lane_settings;
-+	params.usSymClock = cpu_to_le16((uint16_t) (cntl->pixel_clock / 10));
-+	/*
-+	 * In SI/TN case, caller have to set usPixelClock as following:
-+	 * DP mode: usPixelClock = DP_LINK_CLOCK/10
-+	 * (DP_LINK_CLOCK = 1.62GHz, 2.7GHz, 5.4GHz)
-+	 * DVI single link mode: usPixelClock = pixel clock
-+	 * DVI dual link mode: usPixelClock = pixel clock
-+	 * HDMI mode: usPixelClock = pixel clock * deep_color_ratio
-+	 * (=1: 8bpp, =1.25: 10bpp, =1.5:12bpp, =2: 16bpp)
-+	 * LVDS mode: usPixelClock = pixel clock
-+	 */
-+
-+	if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result transmitter_control_v1_6(
-+	struct bios_parser *bp,
-+	struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	const struct command_table_helper *cmd = bp->cmd_helper;
-+	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 params;
-+
-+	memset(&params, 0, sizeof(params));
-+	params.ucPhyId = cmd->phy_id_to_atom(cntl->transmitter);
-+	params.ucAction = (uint8_t)cntl->action;
-+
-+	if (cntl->action == TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS)
-+		params.ucDPLaneSet = (uint8_t)cntl->lane_settings;
-+	else
-+		params.ucDigMode = cmd->signal_type_to_atom_dig_mode(cntl->signal);
-+
-+	params.ucLaneNum = (uint8_t)cntl->lanes_number;
-+	params.ucHPDSel = cmd->hpd_sel_to_atom(cntl->hpd_sel);
-+	params.ucDigEncoderSel = cmd->dig_encoder_sel_to_atom(cntl->engine_id);
-+	params.ucConnObjId = (uint8_t)cntl->connector_obj_id.id;
-+	params.ulSymClock = cntl->pixel_clock/10;
-+
-+	/*
-+	 * In SI/TN case, caller have to set usPixelClock as following:
-+	 * DP mode: usPixelClock = DP_LINK_CLOCK/10
-+	 * (DP_LINK_CLOCK = 1.62GHz, 2.7GHz, 5.4GHz)
-+	 * DVI single link mode: usPixelClock = pixel clock
-+	 * DVI dual link mode: usPixelClock = pixel clock
-+	 * HDMI mode: usPixelClock = pixel clock * deep_color_ratio
-+	 * (=1: 8bpp, =1.25: 10bpp, =1.5:12bpp, =2: 16bpp)
-+	 * LVDS mode: usPixelClock = pixel clock
-+	 */
-+	switch (cntl->signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		switch (cntl->color_depth) {
-+		case COLOR_DEPTH_101010:
-+			params.ulSymClock =
-+				cpu_to_le16((le16_to_cpu(params.ulSymClock) * 30) / 24);
-+			break;
-+		case COLOR_DEPTH_121212:
-+			params.ulSymClock =
-+				cpu_to_le16((le16_to_cpu(params.ulSymClock) * 36) / 24);
-+			break;
-+		case COLOR_DEPTH_161616:
-+			params.ulSymClock =
-+				cpu_to_le16((le16_to_cpu(params.ulSymClock) * 48) / 24);
-+			break;
-+		default:
-+			break;
-+		}
-+		break;
-+		default:
-+			break;
-+	}
-+
-+	if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
-+		result = BP_RESULT_OK;
-+	return result;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  SET PIXEL CLOCK
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+
-+static enum bp_result set_pixel_clock_v3(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
-+static enum bp_result set_pixel_clock_v5(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
-+static enum bp_result set_pixel_clock_v6(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
-+static enum bp_result set_pixel_clock_v7(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
-+
-+static void init_set_pixel_clock(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock)) {
-+	case 3:
-+		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v3;
-+		break;
-+	case 5:
-+		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v5;
-+		break;
-+	case 6:
-+		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v6;
-+		break;
-+	case 7:
-+		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v7;
-+		break;
-+	default:
-+		bp->cmd_tbl.set_pixel_clock = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result set_pixel_clock_v3(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	PIXEL_CLOCK_PARAMETERS_V3 *params;
-+	SET_PIXEL_CLOCK_PS_ALLOCATION allocation;
-+
-+	memset(&allocation, 0, sizeof(allocation));
-+
-+	if (CLOCK_SOURCE_ID_PLL1 == bp_params->pll_id)
-+		allocation.sPCLKInput.ucPpll = ATOM_PPLL1;
-+	else if (CLOCK_SOURCE_ID_PLL2 == bp_params->pll_id)
-+		allocation.sPCLKInput.ucPpll = ATOM_PPLL2;
-+	else
-+		return BP_RESULT_BADINPUT;
-+
-+	allocation.sPCLKInput.usRefDiv =
-+			cpu_to_le16((uint16_t)bp_params->reference_divider);
-+	allocation.sPCLKInput.usFbDiv =
-+			cpu_to_le16((uint16_t)bp_params->feedback_divider);
-+	allocation.sPCLKInput.ucFracFbDiv =
-+			(uint8_t)bp_params->fractional_feedback_divider;
-+	allocation.sPCLKInput.ucPostDiv =
-+			(uint8_t)bp_params->pixel_clock_post_divider;
-+
-+	/* We need to convert from KHz units into 10KHz units */
-+	allocation.sPCLKInput.usPixelClock =
-+			cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
-+
-+	params = (PIXEL_CLOCK_PARAMETERS_V3 *)&allocation.sPCLKInput;
-+	params->ucTransmitterId =
-+			bp->cmd_helper->encoder_id_to_atom(
-+					dal_graphics_object_id_get_encoder_id(
-+							bp_params->encoder_object_id));
-+	params->ucEncoderMode =
-+			(uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom(
-+					bp_params->signal_type, false));
-+
-+	if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
-+		params->ucMiscInfo |= PIXEL_CLOCK_MISC_FORCE_PROG_PPLL;
-+
-+	if (bp_params->flags.USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK)
-+		params->ucMiscInfo |= PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK;
-+
-+	if (CONTROLLER_ID_D1 != bp_params->controller_id)
-+		params->ucMiscInfo |= PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
-+
-+	if (EXEC_BIOS_CMD_TABLE(SetPixelClock, allocation))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+#ifndef SET_PIXEL_CLOCK_PS_ALLOCATION_V5
-+/* video bios did not define this: */
-+typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION_V5 {
-+	PIXEL_CLOCK_PARAMETERS_V5 sPCLKInput;
-+	/* Caller doesn't need to init this portion */
-+	ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;
-+} SET_PIXEL_CLOCK_PS_ALLOCATION_V5;
-+#endif
-+
-+#ifndef SET_PIXEL_CLOCK_PS_ALLOCATION_V6
-+/* video bios did not define this: */
-+typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION_V6 {
-+	PIXEL_CLOCK_PARAMETERS_V6 sPCLKInput;
-+	/* Caller doesn't need to init this portion */
-+	ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;
-+} SET_PIXEL_CLOCK_PS_ALLOCATION_V6;
-+#endif
-+
-+static enum bp_result set_pixel_clock_v5(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	SET_PIXEL_CLOCK_PS_ALLOCATION_V5 clk;
-+	uint8_t controller_id;
-+	uint32_t pll_id;
-+
-+	memset(&clk, 0, sizeof(clk));
-+
-+	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
-+			&& bp->cmd_helper->controller_id_to_atom(
-+					bp_params->controller_id, &controller_id)) {
-+		clk.sPCLKInput.ucCRTC = controller_id;
-+		clk.sPCLKInput.ucPpll = (uint8_t)pll_id;
-+		clk.sPCLKInput.ucRefDiv =
-+				(uint8_t)(bp_params->reference_divider);
-+		clk.sPCLKInput.usFbDiv =
-+				cpu_to_le16((uint16_t)(bp_params->feedback_divider));
-+		clk.sPCLKInput.ulFbDivDecFrac =
-+				cpu_to_le32(bp_params->fractional_feedback_divider);
-+		clk.sPCLKInput.ucPostDiv =
-+				(uint8_t)(bp_params->pixel_clock_post_divider);
-+		clk.sPCLKInput.ucTransmitterID =
-+				bp->cmd_helper->encoder_id_to_atom(
-+						dal_graphics_object_id_get_encoder_id(
-+								bp_params->encoder_object_id));
-+		clk.sPCLKInput.ucEncoderMode =
-+				(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+						bp_params->signal_type, false);
-+
-+		/* We need to convert from KHz units into 10KHz units */
-+		clk.sPCLKInput.usPixelClock =
-+				cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
-+
-+		if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
-+			clk.sPCLKInput.ucMiscInfo |=
-+					PIXEL_CLOCK_MISC_FORCE_PROG_PPLL;
-+
-+		if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
-+			clk.sPCLKInput.ucMiscInfo |=
-+					PIXEL_CLOCK_MISC_REF_DIV_SRC;
-+
-+		/* clkV5.ucMiscInfo bit[3:2]= HDMI panel bit depth: =0: 24bpp
-+		 * =1:30bpp, =2:32bpp
-+		 * driver choose program it itself, i.e. here we program it
-+		 * to 888 by default.
-+		 */
-+
-+		if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
-+			result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
-+
-+static enum bp_result set_pixel_clock_v6(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	SET_PIXEL_CLOCK_PS_ALLOCATION_V6 clk;
-+	uint8_t controller_id;
-+	uint32_t pll_id;
-+
-+	memset(&clk, 0, sizeof(clk));
-+
-+	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
-+			&& bp->cmd_helper->controller_id_to_atom(
-+					bp_params->controller_id, &controller_id)) {
-+		/* Note: VBIOS still wants to use ucCRTC name which is now
-+		 * 1 byte in ULONG
-+		 *typedef struct _CRTC_PIXEL_CLOCK_FREQ
-+		 *{
-+		 * target the pixel clock to drive the CRTC timing.
-+		 * ULONG ulPixelClock:24;
-+		 * 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to
-+		 * previous version.
-+		 * ATOM_CRTC1~6, indicate the CRTC controller to
-+		 * ULONG ucCRTC:8;
-+		 * drive the pixel clock. not used for DCPLL case.
-+		 *}CRTC_PIXEL_CLOCK_FREQ;
-+		 *union
-+		 *{
-+		 * pixel clock and CRTC id frequency
-+		 * CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;
-+		 * ULONG ulDispEngClkFreq; dispclk frequency
-+		 *};
-+		 */
-+		clk.sPCLKInput.ulCrtcPclkFreq.ucCRTC = controller_id;
-+		clk.sPCLKInput.ucPpll = (uint8_t) pll_id;
-+		clk.sPCLKInput.ucRefDiv =
-+				(uint8_t) bp_params->reference_divider;
-+		clk.sPCLKInput.usFbDiv =
-+				cpu_to_le16((uint16_t) bp_params->feedback_divider);
-+		clk.sPCLKInput.ulFbDivDecFrac =
-+				cpu_to_le32(bp_params->fractional_feedback_divider);
-+		clk.sPCLKInput.ucPostDiv =
-+				(uint8_t) bp_params->pixel_clock_post_divider;
-+		clk.sPCLKInput.ucTransmitterID =
-+				bp->cmd_helper->encoder_id_to_atom(
-+						dal_graphics_object_id_get_encoder_id(
-+								bp_params->encoder_object_id));
-+		clk.sPCLKInput.ucEncoderMode =
-+				(uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(
-+						bp_params->signal_type, false);
-+
-+		/* We need to convert from KHz units into 10KHz units */
-+		clk.sPCLKInput.ulCrtcPclkFreq.ulPixelClock =
-+				cpu_to_le32(bp_params->target_pixel_clock / 10);
-+
-+		if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL) {
-+			clk.sPCLKInput.ucMiscInfo |=
-+					PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL;
-+		}
-+
-+		if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC) {
-+			clk.sPCLKInput.ucMiscInfo |=
-+					PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
-+		}
-+
-+		/* clkV6.ucMiscInfo bit[3:2]= HDMI panel bit depth: =0:
-+		 * 24bpp =1:30bpp, =2:32bpp
-+		 * driver choose program it itself, i.e. here we pass required
-+		 * target rate that includes deep color.
-+		 */
-+
-+		if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
-+			result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
-+
-+static enum bp_result set_pixel_clock_v7(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	PIXEL_CLOCK_PARAMETERS_V7 clk;
-+	uint8_t controller_id;
-+	uint32_t pll_id;
-+
-+	memset(&clk, 0, sizeof(clk));
-+
-+	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
-+			&& bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &controller_id)) {
-+		/* Note: VBIOS still wants to use ucCRTC name which is now
-+		 * 1 byte in ULONG
-+		 *typedef struct _CRTC_PIXEL_CLOCK_FREQ
-+		 *{
-+		 * target the pixel clock to drive the CRTC timing.
-+		 * ULONG ulPixelClock:24;
-+		 * 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to
-+		 * previous version.
-+		 * ATOM_CRTC1~6, indicate the CRTC controller to
-+		 * ULONG ucCRTC:8;
-+		 * drive the pixel clock. not used for DCPLL case.
-+		 *}CRTC_PIXEL_CLOCK_FREQ;
-+		 *union
-+		 *{
-+		 * pixel clock and CRTC id frequency
-+		 * CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;
-+		 * ULONG ulDispEngClkFreq; dispclk frequency
-+		 *};
-+		 */
-+		clk.ucCRTC = controller_id;
-+		clk.ucPpll = (uint8_t) pll_id;
-+		clk.ucTransmitterID = bp->cmd_helper->encoder_id_to_atom(dal_graphics_object_id_get_encoder_id(bp_params->encoder_object_id));
-+		clk.ucEncoderMode = (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, false);
-+
-+		/* We need to convert from KHz units into 10KHz units */
-+		clk.ulPixelClock = cpu_to_le32(bp_params->target_pixel_clock * 10);
-+
-+		clk.ucDeepColorRatio = (uint8_t) bp->cmd_helper->transmitter_color_depth_to_atom(bp_params->color_depth);
-+
-+		if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
-+			clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL;
-+
-+		if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
-+			clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC;
-+
-+		if (bp_params->flags.PROGRAM_PHY_PLL_ONLY)
-+			clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_PROG_PHYPLL;
-+
-+		if (bp_params->flags.SUPPORT_YUV_420)
-+			clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_YUV420_MODE;
-+
-+		if (bp_params->flags.SET_XTALIN_REF_SRC)
-+			clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN;
-+
-+		if (bp_params->flags.SET_GENLOCK_REF_DIV_SRC)
-+			clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK;
-+
-+		if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
-+			clk.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
-+
-+		if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
-+			result = BP_RESULT_OK;
-+	}
-+	return result;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  ENABLE PIXEL CLOCK SS
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+static enum bp_result enable_spread_spectrum_on_ppll_v1(
-+	struct bios_parser *bp,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable);
-+static enum bp_result enable_spread_spectrum_on_ppll_v2(
-+	struct bios_parser *bp,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable);
-+static enum bp_result enable_spread_spectrum_on_ppll_v3(
-+	struct bios_parser *bp,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable);
-+
-+static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(EnableSpreadSpectrumOnPPLL)) {
-+	case 1:
-+		bp->cmd_tbl.enable_spread_spectrum_on_ppll =
-+				enable_spread_spectrum_on_ppll_v1;
-+		break;
-+	case 2:
-+		bp->cmd_tbl.enable_spread_spectrum_on_ppll =
-+				enable_spread_spectrum_on_ppll_v2;
-+		break;
-+	case 3:
-+		bp->cmd_tbl.enable_spread_spectrum_on_ppll =
-+				enable_spread_spectrum_on_ppll_v3;
-+		break;
-+	default:
-+		bp->cmd_tbl.enable_spread_spectrum_on_ppll = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result enable_spread_spectrum_on_ppll_v1(
-+	struct bios_parser *bp,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	ENABLE_SPREAD_SPECTRUM_ON_PPLL params;
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	if ((enable == true) && (bp_params->percentage > 0))
-+		params.ucEnable = ATOM_ENABLE;
-+	else
-+		params.ucEnable = ATOM_DISABLE;
-+
-+	params.usSpreadSpectrumPercentage =
-+			cpu_to_le16((uint16_t)bp_params->percentage);
-+	params.ucSpreadSpectrumStep =
-+			(uint8_t)bp_params->ver1.step;
-+	params.ucSpreadSpectrumDelay =
-+			(uint8_t)bp_params->ver1.delay;
-+	/* convert back to unit of 10KHz */
-+	params.ucSpreadSpectrumRange =
-+			(uint8_t)(bp_params->ver1.range / 10000);
-+
-+	if (bp_params->flags.EXTERNAL_SS)
-+		params.ucSpreadSpectrumType |= ATOM_EXTERNAL_SS_MASK;
-+
-+	if (bp_params->flags.CENTER_SPREAD)
-+		params.ucSpreadSpectrumType |= ATOM_SS_CENTRE_SPREAD_MODE;
-+
-+	if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL1)
-+		params.ucPpll = ATOM_PPLL1;
-+	else if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL2)
-+		params.ucPpll = ATOM_PPLL2;
-+	else
-+		BREAK_TO_DEBUGGER(); /* Unexpected PLL value!! */
-+
-+	if (EXEC_BIOS_CMD_TABLE(EnableSpreadSpectrumOnPPLL, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result enable_spread_spectrum_on_ppll_v2(
-+	struct bios_parser *bp,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 params;
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL1)
-+		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V2_P1PLL;
-+	else if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL2)
-+		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V2_P2PLL;
-+	else
-+		BREAK_TO_DEBUGGER(); /* Unexpected PLL value!! */
-+
-+	if ((enable == true) && (bp_params->percentage > 0)) {
-+		params.ucEnable = ATOM_ENABLE;
-+
-+		params.usSpreadSpectrumPercentage =
-+				cpu_to_le16((uint16_t)(bp_params->percentage));
-+		params.usSpreadSpectrumStep =
-+				cpu_to_le16((uint16_t)(bp_params->ds.ds_frac_size));
-+
-+		if (bp_params->flags.EXTERNAL_SS)
-+			params.ucSpreadSpectrumType |=
-+					ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD;
-+
-+		if (bp_params->flags.CENTER_SPREAD)
-+			params.ucSpreadSpectrumType |=
-+					ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD;
-+
-+		/* Both amounts need to be left shifted first before bit
-+		 * comparison. Otherwise, the result will always be zero here
-+		 */
-+		params.usSpreadSpectrumAmount = cpu_to_le16((uint16_t)(
-+				((bp_params->ds.feedback_amount <<
-+						ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT) &
-+						ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK) |
-+						((bp_params->ds.nfrac_amount <<
-+								ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
-+								ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK)));
-+	} else
-+		params.ucEnable = ATOM_DISABLE;
-+
-+	if (EXEC_BIOS_CMD_TABLE(EnableSpreadSpectrumOnPPLL, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result enable_spread_spectrum_on_ppll_v3(
-+	struct bios_parser *bp,
-+	struct bp_spread_spectrum_parameters *bp_params,
-+	bool enable)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 params;
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	switch (bp_params->pll_id) {
-+	case CLOCK_SOURCE_ID_PLL0:
-+		/* ATOM_PPLL_SS_TYPE_V3_P0PLL; this is pixel clock only,
-+		 * not for SI display clock.
-+		 */
-+		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V3_DCPLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL1:
-+		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V3_P1PLL;
-+		break;
-+
-+	case CLOCK_SOURCE_ID_PLL2:
-+		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V3_P2PLL;
-+		break;
-+
-+	case CLOCK_SOURCE_ID_DCPLL:
-+		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V3_DCPLL;
-+		break;
-+
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		/* Unexpected PLL value!! */
-+		return result;
-+	}
-+
-+	if (enable == true) {
-+		params.ucEnable = ATOM_ENABLE;
-+
-+		params.usSpreadSpectrumAmountFrac =
-+				cpu_to_le16((uint16_t)(bp_params->ds_frac_amount));
-+		params.usSpreadSpectrumStep =
-+				cpu_to_le16((uint16_t)(bp_params->ds.ds_frac_size));
-+
-+		if (bp_params->flags.EXTERNAL_SS)
-+			params.ucSpreadSpectrumType |=
-+					ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD;
-+		if (bp_params->flags.CENTER_SPREAD)
-+			params.ucSpreadSpectrumType |=
-+					ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD;
-+
-+		/* Both amounts need to be left shifted first before bit
-+		 * comparison. Otherwise, the result will always be zero here
-+		 */
-+		params.usSpreadSpectrumAmount = cpu_to_le16((uint16_t)(
-+				((bp_params->ds.feedback_amount <<
-+						ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT) &
-+						ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK) |
-+						((bp_params->ds.nfrac_amount <<
-+								ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT) &
-+								ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK)));
-+	} else
-+		params.ucEnable = ATOM_DISABLE;
-+
-+	if (EXEC_BIOS_CMD_TABLE(EnableSpreadSpectrumOnPPLL, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  ADJUST DISPLAY PLL
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+
-+static enum bp_result adjust_display_pll_v2(
-+	struct bios_parser *bp,
-+	struct bp_adjust_pixel_clock_parameters *bp_params);
-+static enum bp_result adjust_display_pll_v3(
-+	struct bios_parser *bp,
-+	struct bp_adjust_pixel_clock_parameters *bp_params);
-+
-+static void init_adjust_display_pll(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(AdjustDisplayPll)) {
-+	case 2:
-+		bp->cmd_tbl.adjust_display_pll = adjust_display_pll_v2;
-+		break;
-+	case 3:
-+		bp->cmd_tbl.adjust_display_pll = adjust_display_pll_v3;
-+		break;
-+	default:
-+		bp->cmd_tbl.adjust_display_pll = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result adjust_display_pll_v2(
-+	struct bios_parser *bp,
-+	struct bp_adjust_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	ADJUST_DISPLAY_PLL_PS_ALLOCATION params = { 0 };
-+
-+	/* We need to convert from KHz units into 10KHz units and then convert
-+	 * output pixel clock back 10KHz-->KHz */
-+	uint32_t pixel_clock_10KHz_in = bp_params->pixel_clock / 10;
-+
-+	params.usPixelClock = cpu_to_le16((uint16_t)(pixel_clock_10KHz_in));
-+	params.ucTransmitterID =
-+			bp->cmd_helper->encoder_id_to_atom(
-+					dal_graphics_object_id_get_encoder_id(
-+							bp_params->encoder_object_id));
-+	params.ucEncodeMode =
-+			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+					bp_params->signal_type, false);
-+	return result;
-+}
-+
-+static enum bp_result adjust_display_pll_v3(
-+	struct bios_parser *bp,
-+	struct bp_adjust_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 params;
-+	uint32_t pixel_clk_10_kHz_in = bp_params->pixel_clock / 10;
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	/* We need to convert from KHz units into 10KHz units and then convert
-+	 * output pixel clock back 10KHz-->KHz */
-+	params.sInput.usPixelClock = cpu_to_le16((uint16_t)pixel_clk_10_kHz_in);
-+	params.sInput.ucTransmitterID =
-+			bp->cmd_helper->encoder_id_to_atom(
-+					dal_graphics_object_id_get_encoder_id(
-+							bp_params->encoder_object_id));
-+	params.sInput.ucEncodeMode =
-+			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+					bp_params->signal_type, false);
-+
-+	if (bp_params->ss_enable == true)
-+		params.sInput.ucDispPllConfig |= DISPPLL_CONFIG_SS_ENABLE;
-+
-+	if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
-+		params.sInput.ucDispPllConfig |= DISPPLL_CONFIG_DUAL_LINK;
-+
-+	if (EXEC_BIOS_CMD_TABLE(AdjustDisplayPll, params)) {
-+		/* Convert output pixel clock back 10KHz-->KHz: multiply
-+		 * original pixel clock in KHz by ratio
-+		 * [output pxlClk/input pxlClk] */
-+		uint64_t pixel_clk_10_khz_out =
-+				(uint64_t)le32_to_cpu(params.sOutput.ulDispPllFreq);
-+		uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock;
-+
-+		if (pixel_clk_10_kHz_in != 0) {
-+			bp_params->adjusted_pixel_clock =
-+					div_u64(pixel_clk * pixel_clk_10_khz_out,
-+							pixel_clk_10_kHz_in);
-+		} else {
-+			bp_params->adjusted_pixel_clock = 0;
-+			BREAK_TO_DEBUGGER();
-+		}
-+
-+		bp_params->reference_divider = params.sOutput.ucRefDiv;
-+		bp_params->pixel_clock_post_divider = params.sOutput.ucPostDiv;
-+
-+		result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  DAC ENCODER CONTROL
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+
-+static enum bp_result dac1_encoder_control_v1(
-+	struct bios_parser *bp,
-+	bool enable,
-+	uint32_t pixel_clock,
-+	uint8_t dac_standard);
-+static enum bp_result dac2_encoder_control_v1(
-+	struct bios_parser *bp,
-+	bool enable,
-+	uint32_t pixel_clock,
-+	uint8_t dac_standard);
-+
-+static void init_dac_encoder_control(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(DAC1EncoderControl)) {
-+	case 1:
-+		bp->cmd_tbl.dac1_encoder_control = dac1_encoder_control_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.dac1_encoder_control = NULL;
-+		break;
-+	}
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(DAC2EncoderControl)) {
-+	case 1:
-+		bp->cmd_tbl.dac2_encoder_control = dac2_encoder_control_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.dac2_encoder_control = NULL;
-+		break;
-+	}
-+}
-+
-+static void dac_encoder_control_prepare_params(
-+	DAC_ENCODER_CONTROL_PS_ALLOCATION *params,
-+	bool enable,
-+	uint32_t pixel_clock,
-+	uint8_t dac_standard)
-+{
-+	params->ucDacStandard = dac_standard;
-+	if (enable)
-+		params->ucAction = ATOM_ENABLE;
-+	else
-+		params->ucAction = ATOM_DISABLE;
-+
-+	/* We need to convert from KHz units into 10KHz units
-+	 * it looks as if the TvControl do not care about pixel clock
-+	 */
-+	params->usPixelClock = cpu_to_le16((uint16_t)(pixel_clock / 10));
-+}
-+
-+static enum bp_result dac1_encoder_control_v1(
-+	struct bios_parser *bp,
-+	bool enable,
-+	uint32_t pixel_clock,
-+	uint8_t dac_standard)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DAC_ENCODER_CONTROL_PS_ALLOCATION params;
-+
-+	dac_encoder_control_prepare_params(
-+		&params,
-+		enable,
-+		pixel_clock,
-+		dac_standard);
-+
-+	if (EXEC_BIOS_CMD_TABLE(DAC1EncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result dac2_encoder_control_v1(
-+	struct bios_parser *bp,
-+	bool enable,
-+	uint32_t pixel_clock,
-+	uint8_t dac_standard)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DAC_ENCODER_CONTROL_PS_ALLOCATION params;
-+
-+	dac_encoder_control_prepare_params(
-+		&params,
-+		enable,
-+		pixel_clock,
-+		dac_standard);
-+
-+	if (EXEC_BIOS_CMD_TABLE(DAC2EncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  DAC OUTPUT CONTROL
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+static enum bp_result dac1_output_control_v1(
-+	struct bios_parser *bp,
-+	bool enable);
-+static enum bp_result dac2_output_control_v1(
-+	struct bios_parser *bp,
-+	bool enable);
-+
-+static void init_dac_output_control(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(DAC1OutputControl)) {
-+	case 1:
-+		bp->cmd_tbl.dac1_output_control = dac1_output_control_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.dac1_output_control = NULL;
-+		break;
-+	}
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(DAC2OutputControl)) {
-+	case 1:
-+		bp->cmd_tbl.dac2_output_control = dac2_output_control_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.dac2_output_control = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result dac1_output_control_v1(
-+	struct bios_parser *bp, bool enable)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION params;
-+
-+	if (enable)
-+		params.ucAction = ATOM_ENABLE;
-+	else
-+		params.ucAction = ATOM_DISABLE;
-+
-+	if (EXEC_BIOS_CMD_TABLE(DAC1OutputControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result dac2_output_control_v1(
-+	struct bios_parser *bp, bool enable)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION params;
-+
-+	if (enable)
-+		params.ucAction = ATOM_ENABLE;
-+	else
-+		params.ucAction = ATOM_DISABLE;
-+
-+	if (EXEC_BIOS_CMD_TABLE(DAC2OutputControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  SET CRTC TIMING
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+
-+static enum bp_result set_crtc_using_dtd_timing_v3(
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_timing_parameters *bp_params);
-+static enum bp_result set_crtc_timing_v1(
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_timing_parameters *bp_params);
-+
-+static void init_set_crtc_timing(struct bios_parser *bp)
-+{
-+	uint32_t dtd_version =
-+			BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_UsingDTDTiming);
-+	if (dtd_version > 2)
-+		switch (dtd_version) {
-+		case 3:
-+			bp->cmd_tbl.set_crtc_timing =
-+					set_crtc_using_dtd_timing_v3;
-+			break;
-+		default:
-+			bp->cmd_tbl.set_crtc_timing = NULL;
-+			break;
-+		}
-+	else
-+		switch (BIOS_CMD_TABLE_PARA_REVISION(SetCRTC_Timing)) {
-+		case 1:
-+			bp->cmd_tbl.set_crtc_timing = set_crtc_timing_v1;
-+			break;
-+		default:
-+			bp->cmd_tbl.set_crtc_timing = NULL;
-+			break;
-+		}
-+}
-+
-+static enum bp_result set_crtc_timing_v1(
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_timing_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION params = {0};
-+	uint8_t atom_controller_id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(
-+			bp_params->controller_id, &atom_controller_id))
-+		params.ucCRTC = atom_controller_id;
-+
-+	params.usH_Total = cpu_to_le16((uint16_t)(bp_params->h_total));
-+	params.usH_Disp = cpu_to_le16((uint16_t)(bp_params->h_addressable));
-+	params.usH_SyncStart = cpu_to_le16((uint16_t)(bp_params->h_sync_start));
-+	params.usH_SyncWidth = cpu_to_le16((uint16_t)(bp_params->h_sync_width));
-+	params.usV_Total = cpu_to_le16((uint16_t)(bp_params->v_total));
-+	params.usV_Disp = cpu_to_le16((uint16_t)(bp_params->v_addressable));
-+	params.usV_SyncStart =
-+			cpu_to_le16((uint16_t)(bp_params->v_sync_start));
-+	params.usV_SyncWidth =
-+			cpu_to_le16((uint16_t)(bp_params->v_sync_width));
-+
-+	/* VBIOS does not expect any value except zero into this call, for
-+	 * underscan use another entry ProgramOverscan call but when mode
-+	 * 1776x1000 with the overscan 72x44 .e.i. 1920x1080 @30 DAL2 is ok,
-+	 * but when same ,but 60 Hz there is corruption
-+	 * DAL1 does not allow the mode 1776x1000@60
-+	 */
-+	params.ucOverscanRight = (uint8_t)bp_params->h_overscan_right;
-+	params.ucOverscanLeft = (uint8_t)bp_params->h_overscan_left;
-+	params.ucOverscanBottom = (uint8_t)bp_params->v_overscan_bottom;
-+	params.ucOverscanTop = (uint8_t)bp_params->v_overscan_top;
-+
-+	if (0 == bp_params->flags.HSYNC_POSITIVE_POLARITY)
-+		params.susModeMiscInfo.usAccess =
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_HSYNC_POLARITY);
-+
-+	if (0 == bp_params->flags.VSYNC_POSITIVE_POLARITY)
-+		params.susModeMiscInfo.usAccess =
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_VSYNC_POLARITY);
-+
-+	if (bp_params->flags.INTERLACE) {
-+		params.susModeMiscInfo.usAccess =
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_INTERLACE);
-+
-+		/* original DAL code has this condition to apply tis for
-+		 * non-TV/CV only due to complex MV testing for possible
-+		 * impact
-+		 * if (pACParameters->signal != SignalType_YPbPr &&
-+		 *  pACParameters->signal != SignalType_Composite &&
-+		 *  pACParameters->signal != SignalType_SVideo)
-+		 */
-+		/* HW will deduct 0.5 line from 2nd feild.
-+		 * i.e. for 1080i, it is 2 lines for 1st field, 2.5
-+		 * lines for the 2nd feild. we need input as 5 instead
-+		 * of 4, but it is 4 either from Edid data
-+		 * (spec CEA 861) or CEA timing table.
-+		 */
-+		params.usV_SyncStart =
-+				cpu_to_le16((uint16_t)(bp_params->v_sync_start + 1));
-+	}
-+
-+	if (bp_params->flags.HORZ_COUNT_BY_TWO)
-+		params.susModeMiscInfo.usAccess =
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_DOUBLE_CLOCK_MODE);
-+
-+	if (EXEC_BIOS_CMD_TABLE(SetCRTC_Timing, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result set_crtc_using_dtd_timing_v3(
-+	struct bios_parser *bp,
-+	struct bp_hw_crtc_timing_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	SET_CRTC_USING_DTD_TIMING_PARAMETERS params = {0};
-+	uint8_t atom_controller_id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(
-+			bp_params->controller_id, &atom_controller_id))
-+		params.ucCRTC = atom_controller_id;
-+
-+	/* bios usH_Size wants h addressable size */
-+	params.usH_Size = cpu_to_le16((uint16_t)bp_params->h_addressable);
-+	/* bios usH_Blanking_Time wants borders included in blanking */
-+	params.usH_Blanking_Time =
-+			cpu_to_le16((uint16_t)(bp_params->h_total - bp_params->h_addressable));
-+	/* bios usV_Size wants v addressable size */
-+	params.usV_Size = cpu_to_le16((uint16_t)bp_params->v_addressable);
-+	/* bios usV_Blanking_Time wants borders included in blanking */
-+	params.usV_Blanking_Time =
-+			cpu_to_le16((uint16_t)(bp_params->v_total - bp_params->v_addressable));
-+	/* bios usHSyncOffset is the offset from the end of h addressable,
-+	 * our horizontalSyncStart is the offset from the beginning
-+	 * of h addressable */
-+	params.usH_SyncOffset =
-+			cpu_to_le16((uint16_t)(bp_params->h_sync_start - bp_params->h_addressable));
-+	params.usH_SyncWidth = cpu_to_le16((uint16_t)bp_params->h_sync_width);
-+	/* bios usHSyncOffset is the offset from the end of v addressable,
-+	 * our verticalSyncStart is the offset from the beginning of
-+	 * v addressable */
-+	params.usV_SyncOffset =
-+			cpu_to_le16((uint16_t)(bp_params->v_sync_start - bp_params->v_addressable));
-+	params.usV_SyncWidth = cpu_to_le16((uint16_t)bp_params->v_sync_width);
-+
-+	/* we assume that overscan from original timing does not get bigger
-+	 * than 255
-+	 * we will program all the borders in the Set CRTC Overscan call below
-+	 */
-+
-+	if (0 == bp_params->flags.HSYNC_POSITIVE_POLARITY)
-+		params.susModeMiscInfo.usAccess =
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_HSYNC_POLARITY);
-+
-+	if (0 == bp_params->flags.VSYNC_POSITIVE_POLARITY)
-+		params.susModeMiscInfo.usAccess =
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_VSYNC_POLARITY);
-+
-+	if (bp_params->flags.INTERLACE)	{
-+		params.susModeMiscInfo.usAccess =
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_INTERLACE);
-+
-+		/* original DAL code has this condition to apply this
-+		 * for non-TV/CV only
-+		 * due to complex MV testing for possible impact
-+		 * if ( pACParameters->signal != SignalType_YPbPr &&
-+		 *  pACParameters->signal != SignalType_Composite &&
-+		 *  pACParameters->signal != SignalType_SVideo)
-+		 */
-+		{
-+			/* HW will deduct 0.5 line from 2nd feild.
-+			 * i.e. for 1080i, it is 2 lines for 1st field,
-+			 * 2.5 lines for the 2nd feild. we need input as 5
-+			 * instead of 4.
-+			 * but it is 4 either from Edid data (spec CEA 861)
-+			 * or CEA timing table.
-+			 */
-+			params.usV_SyncOffset =
-+					cpu_to_le16(le16_to_cpu(params.usV_SyncOffset) + 1);
-+
-+		}
-+	}
-+
-+	if (bp_params->flags.HORZ_COUNT_BY_TWO)
-+		params.susModeMiscInfo.usAccess =
-+				cpu_to_le16(le16_to_cpu(params.susModeMiscInfo.usAccess) | ATOM_DOUBLE_CLOCK_MODE);
-+
-+	if (EXEC_BIOS_CMD_TABLE(SetCRTC_UsingDTDTiming, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  SELECT CRTC SOURCE
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+
-+static enum bp_result select_crtc_source_v2(
-+	struct bios_parser *bp,
-+	struct bp_crtc_source_select *bp_params);
-+static enum bp_result select_crtc_source_v3(
-+	struct bios_parser *bp,
-+	struct bp_crtc_source_select *bp_params);
-+
-+static void init_select_crtc_source(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source)) {
-+	case 2:
-+		bp->cmd_tbl.select_crtc_source = select_crtc_source_v2;
-+		break;
-+	case 3:
-+		bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
-+		break;
-+	default:
-+		bp->cmd_tbl.select_crtc_source = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result select_crtc_source_v2(
-+	struct bios_parser *bp,
-+	struct bp_crtc_source_select *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+	SELECT_CRTC_SOURCE_PARAMETERS_V2 params;
-+	uint8_t atom_controller_id;
-+	uint32_t atom_engine_id;
-+	enum signal_type s = bp_params->signal;
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	/* set controller id */
-+	if (bp->cmd_helper->controller_id_to_atom(
-+			bp_params->controller_id, &atom_controller_id))
-+		params.ucCRTC = atom_controller_id;
-+	else
-+		return BP_RESULT_FAILURE;
-+
-+	/* set encoder id */
-+	if (bp->cmd_helper->engine_bp_to_atom(
-+			bp_params->engine_id, &atom_engine_id))
-+		params.ucEncoderID = (uint8_t)atom_engine_id;
-+	else
-+		return BP_RESULT_FAILURE;
-+
-+	if (SIGNAL_TYPE_EDP == s ||
-+			(SIGNAL_TYPE_DISPLAY_PORT == s &&
-+					SIGNAL_TYPE_LVDS == bp_params->sink_signal))
-+		s = SIGNAL_TYPE_LVDS;
-+
-+	params.ucEncodeMode =
-+			(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+					s, bp_params->enable_dp_audio);
-+
-+	if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result select_crtc_source_v3(
-+	struct bios_parser *bp,
-+	struct bp_crtc_source_select *bp_params)
-+{
-+	bool result = BP_RESULT_FAILURE;
-+	SELECT_CRTC_SOURCE_PARAMETERS_V3 params;
-+	uint8_t atom_controller_id;
-+	uint32_t atom_engine_id;
-+	enum signal_type s = bp_params->signal;
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
-+			&atom_controller_id))
-+		params.ucCRTC = atom_controller_id;
-+	else
-+		return result;
-+
-+	if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id,
-+			&atom_engine_id))
-+		params.ucEncoderID = (uint8_t)atom_engine_id;
-+	else
-+		return result;
-+
-+	if (SIGNAL_TYPE_EDP == s ||
-+			(SIGNAL_TYPE_DISPLAY_PORT == s &&
-+					SIGNAL_TYPE_LVDS == bp_params->sink_signal))
-+		s = SIGNAL_TYPE_LVDS;
-+
-+	params.ucEncodeMode =
-+			bp->cmd_helper->encoder_mode_bp_to_atom(
-+					s, bp_params->enable_dp_audio);
-+	/* Needed for VBIOS Random Spatial Dithering feature */
-+	params.ucDstBpc = (uint8_t)(bp_params->display_output_bit_depth);
-+
-+	if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  ENABLE CRTC
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+
-+static enum bp_result enable_crtc_v1(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	bool enable);
-+
-+static void init_enable_crtc(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(EnableCRTC)) {
-+	case 1:
-+		bp->cmd_tbl.enable_crtc = enable_crtc_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.enable_crtc = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result enable_crtc_v1(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	bool enable)
-+{
-+	bool result = BP_RESULT_FAILURE;
-+	ENABLE_CRTC_PARAMETERS params = {0};
-+	uint8_t id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(controller_id, &id))
-+		params.ucCRTC = id;
-+	else
-+		return BP_RESULT_BADINPUT;
-+
-+	if (enable)
-+		params.ucEnable = ATOM_ENABLE;
-+	else
-+		params.ucEnable = ATOM_DISABLE;
-+
-+	if (EXEC_BIOS_CMD_TABLE(EnableCRTC, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  ENABLE CRTC MEM REQ
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+
-+static enum bp_result enable_crtc_mem_req_v1(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	bool enable);
-+
-+static void init_enable_crtc_mem_req(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(EnableCRTCMemReq)) {
-+	case 1:
-+		bp->cmd_tbl.enable_crtc_mem_req = enable_crtc_mem_req_v1;
-+		break;
-+	default:
-+		bp->cmd_tbl.enable_crtc_mem_req = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result enable_crtc_mem_req_v1(
-+	struct bios_parser *bp,
-+	enum controller_id controller_id,
-+	bool enable)
-+{
-+	bool result = BP_RESULT_BADINPUT;
-+	ENABLE_CRTC_PARAMETERS params = {0};
-+	uint8_t id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(controller_id, &id)) {
-+		params.ucCRTC = id;
-+
-+		if (enable)
-+			params.ucEnable = ATOM_ENABLE;
-+		else
-+			params.ucEnable = ATOM_DISABLE;
-+
-+		if (EXEC_BIOS_CMD_TABLE(EnableCRTCMemReq, params))
-+			result = BP_RESULT_OK;
-+		else
-+			result = BP_RESULT_FAILURE;
-+	}
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  DISPLAY PLL
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+
-+static enum bp_result program_clock_v5(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
-+static enum bp_result program_clock_v6(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params);
-+
-+static void init_program_clock(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock)) {
-+	case 5:
-+		bp->cmd_tbl.program_clock = program_clock_v5;
-+		break;
-+	case 6:
-+		bp->cmd_tbl.program_clock = program_clock_v6;
-+		break;
-+	default:
-+		bp->cmd_tbl.program_clock = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result program_clock_v5(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+
-+	SET_PIXEL_CLOCK_PS_ALLOCATION_V5 params;
-+	uint32_t atom_pll_id;
-+
-+	memset(&params, 0, sizeof(params));
-+	if (!bp->cmd_helper->clock_source_id_to_atom(
-+			bp_params->pll_id, &atom_pll_id)) {
-+		BREAK_TO_DEBUGGER(); /* Invalid Inpute!! */
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	/* We need to convert from KHz units into 10KHz units */
-+	params.sPCLKInput.ucPpll = (uint8_t) atom_pll_id;
-+	params.sPCLKInput.usPixelClock =
-+			cpu_to_le16((uint16_t) (bp_params->target_pixel_clock / 10));
-+	params.sPCLKInput.ucCRTC = (uint8_t) ATOM_CRTC_INVALID;
-+
-+	if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
-+		params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
-+
-+	if (EXEC_BIOS_CMD_TABLE(SetPixelClock, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+static enum bp_result program_clock_v6(
-+	struct bios_parser *bp,
-+	struct bp_pixel_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+
-+	SET_PIXEL_CLOCK_PS_ALLOCATION_V6 params;
-+	uint32_t atom_pll_id;
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	if (!bp->cmd_helper->clock_source_id_to_atom(
-+			bp_params->pll_id, &atom_pll_id)) {
-+		BREAK_TO_DEBUGGER(); /*Invalid Input!!*/
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	/* We need to convert from KHz units into 10KHz units */
-+	params.sPCLKInput.ucPpll = (uint8_t)atom_pll_id;
-+	params.sPCLKInput.ulDispEngClkFreq =
-+			cpu_to_le32(bp_params->target_pixel_clock / 10);
-+
-+	if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
-+		params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
-+
-+	if (EXEC_BIOS_CMD_TABLE(SetPixelClock, params)) {
-+		/* True display clock is returned by VBIOS if DFS bypass
-+		 * is enabled. */
-+		bp_params->dfs_bypass_display_clock =
-+				(uint32_t)(le32_to_cpu(params.sPCLKInput.ulDispEngClkFreq) * 10);
-+		result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  EXTERNAL ENCODER CONTROL
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+
-+static enum bp_result external_encoder_control_v3(
-+	struct bios_parser *bp,
-+	struct bp_external_encoder_control *cntl);
-+
-+static void init_external_encoder_control(
-+	struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(ExternalEncoderControl)) {
-+	case 3:
-+		bp->cmd_tbl.external_encoder_control =
-+				external_encoder_control_v3;
-+		break;
-+	default:
-+		bp->cmd_tbl.external_encoder_control = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result external_encoder_control_v3(
-+	struct bios_parser *bp,
-+	struct bp_external_encoder_control *cntl)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+
-+	/* we need use _PS_Alloc struct */
-+	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 params;
-+	EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 *cntl_params;
-+	struct graphics_object_id encoder;
-+	bool is_input_signal_dp = false;
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	cntl_params = &params.sExtEncoder;
-+
-+	encoder = cntl->encoder_id;
-+
-+	/* check if encoder supports external encoder control table */
-+	switch (dal_graphics_object_id_get_encoder_id(encoder)) {
-+	case ENCODER_ID_EXTERNAL_NUTMEG:
-+	case ENCODER_ID_EXTERNAL_TRAVIS:
-+		is_input_signal_dp = true;
-+		break;
-+
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		return BP_RESULT_BADINPUT;
-+	}
-+
-+	/* Fill information based on the action
-+	 *
-+	 * Bit[6:4]: indicate external encoder, applied to all functions.
-+	 * =0: external encoder1, mapped to external encoder enum id1
-+	 * =1: external encoder2, mapped to external encoder enum id2
-+	 *
-+	 * enum ObjectEnumId
-+	 * {
-+	 *  EnumId_Unknown = 0,
-+	 *  EnumId_1,
-+	 *  EnumId_2,
-+	 * };
-+	 */
-+	cntl_params->ucConfig = (uint8_t)((encoder.enum_id - 1) << 4);
-+
-+	switch (cntl->action) {
-+	case EXTERNAL_ENCODER_CONTROL_INIT:
-+		/* output display connector type. Only valid in encoder
-+		 * initialization */
-+		cntl_params->usConnectorId =
-+				cpu_to_le16((uint16_t)cntl->connector_obj_id.id);
-+		break;
-+	case EXTERNAL_ENCODER_CONTROL_SETUP:
-+		/* EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 pixel clock unit in
-+		 * 10KHz
-+		 * output display device pixel clock frequency in unit of 10KHz.
-+		 * Only valid in setup and enableoutput
-+		 */
-+		cntl_params->usPixelClock =
-+				cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+		/* Indicate display output signal type drive by external
-+		 * encoder, only valid in setup and enableoutput */
-+		cntl_params->ucEncoderMode =
-+				(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+						cntl->signal, false);
-+
-+		if (is_input_signal_dp) {
-+			/* Bit[0]: indicate link rate, =1: 2.7Ghz, =0: 1.62Ghz,
-+			 * only valid in encoder setup with DP mode. */
-+			if (LINK_RATE_HIGH == cntl->link_rate)
-+				cntl_params->ucConfig |= 1;
-+			/* output color depth Indicate encoder data bpc format
-+			 * in DP mode, only valid in encoder setup in DP mode.
-+			 */
-+			cntl_params->ucBitPerColor =
-+					(uint8_t)(cntl->color_depth);
-+		}
-+		/* Indicate how many lanes used by external encoder, only valid
-+		 * in encoder setup and enableoutput. */
-+		cntl_params->ucLaneNum = (uint8_t)(cntl->lanes_number);
-+		break;
-+	case EXTERNAL_ENCODER_CONTROL_ENABLE:
-+		cntl_params->usPixelClock =
-+				cpu_to_le16((uint16_t)(cntl->pixel_clock / 10));
-+		cntl_params->ucEncoderMode =
-+				(uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-+						cntl->signal, false);
-+		cntl_params->ucLaneNum = (uint8_t)cntl->lanes_number;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	cntl_params->ucAction = (uint8_t)cntl->action;
-+
-+	if (EXEC_BIOS_CMD_TABLE(ExternalEncoderControl, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  ENABLE DISPLAY POWER GATING
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+
-+static enum bp_result enable_disp_power_gating_v2_1(
-+	struct bios_parser *bp,
-+	enum controller_id crtc_id,
-+	enum bp_pipe_control_action action);
-+
-+static void init_enable_disp_power_gating(
-+	struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(EnableDispPowerGating)) {
-+	case 1:
-+		bp->cmd_tbl.enable_disp_power_gating =
-+				enable_disp_power_gating_v2_1;
-+		break;
-+	default:
-+		bp->cmd_tbl.enable_disp_power_gating = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result enable_disp_power_gating_v2_1(
-+	struct bios_parser *bp,
-+	enum controller_id crtc_id,
-+	enum bp_pipe_control_action action)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+
-+	ENABLE_DISP_POWER_GATING_PS_ALLOCATION params = {0};
-+	uint8_t atom_crtc_id;
-+
-+	if (bp->cmd_helper->controller_id_to_atom(crtc_id, &atom_crtc_id))
-+		params.ucDispPipeId = atom_crtc_id;
-+	else
-+		return BP_RESULT_BADINPUT;
-+
-+	params.ucEnable =
-+			bp->cmd_helper->disp_power_gating_action_to_atom(action);
-+
-+	if (EXEC_BIOS_CMD_TABLE(EnableDispPowerGating, params))
-+		result = BP_RESULT_OK;
-+
-+	return result;
-+}
-+
-+/*******************************************************************************
-+ ********************************************************************************
-+ **
-+ **                  SET DCE CLOCK
-+ **
-+ ********************************************************************************
-+ *******************************************************************************/
-+static enum bp_result set_dce_clock_v2_1(
-+	struct bios_parser *bp,
-+	struct bp_set_dce_clock_parameters *bp_params);
-+
-+static void init_set_dce_clock(struct bios_parser *bp)
-+{
-+	switch (BIOS_CMD_TABLE_PARA_REVISION(SetDCEClock)) {
-+	case 1:
-+		bp->cmd_tbl.set_dce_clock = set_dce_clock_v2_1;
-+		break;
-+	default:
-+		bp->cmd_tbl.set_dce_clock = NULL;
-+		break;
-+	}
-+}
-+
-+static enum bp_result set_dce_clock_v2_1(
-+	struct bios_parser *bp,
-+	struct bp_set_dce_clock_parameters *bp_params)
-+{
-+	enum bp_result result = BP_RESULT_FAILURE;
-+
-+	SET_DCE_CLOCK_PS_ALLOCATION_V2_1 params;
-+	uint32_t atom_pll_id;
-+	uint32_t atom_clock_type;
-+	const struct command_table_helper *cmd = bp->cmd_helper;
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	if (!cmd->clock_source_id_to_atom(bp_params->pll_id, &atom_pll_id) ||
-+			!cmd->dc_clock_type_to_atom(bp_params->clock_type, &atom_clock_type))
-+		return BP_RESULT_BADINPUT;
-+
-+	params.asParam.ucDCEClkSrc  = atom_pll_id;
-+	params.asParam.ucDCEClkType = atom_clock_type;
-+
-+	if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) {
-+		if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK)
-+			params.asParam.ucDCEClkFlag |= DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK;
-+
-+		if (bp_params->flags.USE_PCIE_AS_SOURCE_FOR_DPREFCLK)
-+			params.asParam.ucDCEClkFlag |= DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE;
-+
-+		if (bp_params->flags.USE_XTALIN_AS_SOURCE_FOR_DPREFCLK)
-+			params.asParam.ucDCEClkFlag |= DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN;
-+
-+		if (bp_params->flags.USE_GENERICA_AS_SOURCE_FOR_DPREFCLK)
-+			params.asParam.ucDCEClkFlag |= DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA;
-+	}
-+	else
-+		/* only program clock frequency if display clock is used; VBIOS will program DPREFCLK */
-+		/* We need to convert from KHz units into 10KHz units */
-+		params.asParam.ulDCEClkFreq = cpu_to_le32(bp_params->target_clock_frequency / 10);
-+
-+	if (EXEC_BIOS_CMD_TABLE(SetDCEClock, params)) {
-+		/* Convert from 10KHz units back to KHz */
-+		bp_params->target_clock_frequency = le32_to_cpu(params.asParam.ulDCEClkFreq) * 10;
-+		result = BP_RESULT_OK;
-+	}
-+
-+	return result;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table.h.0130~	2017-12-14 06:39:58.401903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table.h	2017-12-14 06:39:58.401903558 +0100
-@@ -0,0 +1,102 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMMAND_TABLE_H__
-+#define __DAL_COMMAND_TABLE_H__
-+
-+struct bios_parser;
-+struct bp_encoder_control;
-+
-+struct cmd_tbl {
-+	enum bp_result (*dig_encoder_control)(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *control);
-+	enum bp_result (*encoder_control_dig1)(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *control);
-+	enum bp_result (*encoder_control_dig2)(
-+		struct bios_parser *bp,
-+		struct bp_encoder_control *control);
-+	enum bp_result (*transmitter_control)(
-+		struct bios_parser *bp,
-+		struct bp_transmitter_control *control);
-+	enum bp_result (*set_pixel_clock)(
-+		struct bios_parser *bp,
-+		struct bp_pixel_clock_parameters *bp_params);
-+	enum bp_result (*enable_spread_spectrum_on_ppll)(
-+		struct bios_parser *bp,
-+		struct bp_spread_spectrum_parameters *bp_params,
-+		bool enable);
-+	enum bp_result (*adjust_display_pll)(
-+		struct bios_parser *bp,
-+		struct bp_adjust_pixel_clock_parameters *bp_params);
-+	enum bp_result (*dac1_encoder_control)(
-+		struct bios_parser *bp,
-+		bool enable,
-+		uint32_t pixel_clock,
-+		uint8_t dac_standard);
-+	enum bp_result (*dac2_encoder_control)(
-+		struct bios_parser *bp,
-+		bool enable,
-+		uint32_t pixel_clock,
-+		uint8_t dac_standard);
-+	enum bp_result (*dac1_output_control)(
-+		struct bios_parser *bp,
-+		bool enable);
-+	enum bp_result (*dac2_output_control)(
-+		struct bios_parser *bp,
-+		bool enable);
-+	enum bp_result (*set_crtc_timing)(
-+		struct bios_parser *bp,
-+		struct bp_hw_crtc_timing_parameters *bp_params);
-+	enum bp_result (*select_crtc_source)(
-+		struct bios_parser *bp,
-+		struct bp_crtc_source_select *bp_params);
-+	enum bp_result (*enable_crtc)(
-+		struct bios_parser *bp,
-+		enum controller_id controller_id,
-+		bool enable);
-+	enum bp_result (*enable_crtc_mem_req)(
-+		struct bios_parser *bp,
-+		enum controller_id controller_id,
-+		bool enable);
-+	enum bp_result (*program_clock)(
-+		struct bios_parser *bp,
-+		struct bp_pixel_clock_parameters *bp_params);
-+	enum bp_result (*external_encoder_control)(
-+			struct bios_parser *bp,
-+			struct bp_external_encoder_control *cntl);
-+	enum bp_result (*enable_disp_power_gating)(
-+		struct bios_parser *bp,
-+		enum controller_id crtc_id,
-+		enum bp_pipe_control_action action);
-+	enum bp_result (*set_dce_clock)(
-+		struct bios_parser *bp,
-+		struct bp_set_dce_clock_parameters *bp_params);
-+};
-+
-+void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c.0130~	2017-12-14 06:39:58.401903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c	2017-12-14 06:39:58.401903558 +0100
-@@ -0,0 +1,265 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "ObjectID.h"
-+#include "atomfirmware.h"
-+
-+#include "include/bios_parser_types.h"
-+
-+#include "command_table_helper2.h"
-+
-+bool dal_bios_parser_init_cmd_tbl_helper2(
-+	const struct command_table_helper **h,
-+	enum dce_version dce)
-+{
-+	switch (dce) {
-+	case DCE_VERSION_8_0:
-+	case DCE_VERSION_8_1:
-+	case DCE_VERSION_8_3:
-+		*h = dal_cmd_tbl_helper_dce80_get_table();
-+		return true;
-+
-+	case DCE_VERSION_10_0:
-+		*h = dal_cmd_tbl_helper_dce110_get_table();
-+		return true;
-+
-+	case DCE_VERSION_11_0:
-+		*h = dal_cmd_tbl_helper_dce110_get_table();
-+		return true;
-+
-+	case DCE_VERSION_11_2:
-+		*h = dal_cmd_tbl_helper_dce112_get_table2();
-+		return true;
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	case DCN_VERSION_1_0:
-+		*h = dal_cmd_tbl_helper_dce112_get_table2();
-+		return true;
-+#endif
-+
-+	case DCE_VERSION_12_0:
-+		*h = dal_cmd_tbl_helper_dce112_get_table2();
-+		return true;
-+
-+	default:
-+		/* Unsupported DCE */
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
-+
-+/* real implementations */
-+
-+bool dal_cmd_table_helper_controller_id_to_atom2(
-+	enum controller_id id,
-+	uint8_t *atom_id)
-+{
-+	if (atom_id == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	switch (id) {
-+	case CONTROLLER_ID_D0:
-+		*atom_id = ATOM_CRTC1;
-+		return true;
-+	case CONTROLLER_ID_D1:
-+		*atom_id = ATOM_CRTC2;
-+		return true;
-+	case CONTROLLER_ID_D2:
-+		*atom_id = ATOM_CRTC3;
-+		return true;
-+	case CONTROLLER_ID_D3:
-+		*atom_id = ATOM_CRTC4;
-+		return true;
-+	case CONTROLLER_ID_D4:
-+		*atom_id = ATOM_CRTC5;
-+		return true;
-+	case CONTROLLER_ID_D5:
-+		*atom_id = ATOM_CRTC6;
-+		return true;
-+	/* TODO :case CONTROLLER_ID_UNDERLAY0:
-+		*atom_id = ATOM_UNDERLAY_PIPE0;
-+		return true;
-+	*/
-+	case CONTROLLER_ID_UNDEFINED:
-+		*atom_id = ATOM_CRTC_INVALID;
-+		return true;
-+	default:
-+		/* Wrong controller id */
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
-+
-+/**
-+* translate_transmitter_bp_to_atom
-+*
-+* @brief
-+*  Translate the Transmitter to the corresponding ATOM BIOS value
-+*
-+* @param
-+*   input transmitter
-+*   output digitalTransmitter
-+*    // =00: Digital Transmitter1 ( UNIPHY linkAB )
-+*    // =01: Digital Transmitter2 ( UNIPHY linkCD )
-+*    // =02: Digital Transmitter3 ( UNIPHY linkEF )
-+*/
-+uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2(
-+	enum transmitter t)
-+{
-+	switch (t) {
-+	case TRANSMITTER_UNIPHY_A:
-+	case TRANSMITTER_UNIPHY_B:
-+	case TRANSMITTER_TRAVIS_LCD:
-+		return 0;
-+	case TRANSMITTER_UNIPHY_C:
-+	case TRANSMITTER_UNIPHY_D:
-+		return 1;
-+	case TRANSMITTER_UNIPHY_E:
-+	case TRANSMITTER_UNIPHY_F:
-+		return 2;
-+	default:
-+		/* Invalid Transmitter Type! */
-+		BREAK_TO_DEBUGGER();
-+		return 0;
-+	}
-+}
-+
-+uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2(
-+	enum signal_type s,
-+	bool enable_dp_audio)
-+{
-+	switch (s) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		return ATOM_ENCODER_MODE_DVI;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		return ATOM_ENCODER_MODE_HDMI;
-+	case SIGNAL_TYPE_LVDS:
-+		return ATOM_ENCODER_MODE_LVDS;
-+	case SIGNAL_TYPE_EDP:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_VIRTUAL:
-+		if (enable_dp_audio)
-+			return ATOM_ENCODER_MODE_DP_AUDIO;
-+		else
-+			return ATOM_ENCODER_MODE_DP;
-+	case SIGNAL_TYPE_RGB:
-+		return ATOM_ENCODER_MODE_CRT;
-+	default:
-+		return ATOM_ENCODER_MODE_CRT;
-+	}
-+}
-+
-+bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2(
-+	enum clock_source_id id,
-+	uint32_t *ref_clk_src_id)
-+{
-+	if (ref_clk_src_id == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	switch (id) {
-+	case CLOCK_SOURCE_ID_PLL1:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL;
-+		return true;
-+	case CLOCK_SOURCE_ID_PLL2:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL;
-+		return true;
-+	/*TODO:case CLOCK_SOURCE_ID_DCPLL:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL;
-+		return true;
-+	*/
-+	case CLOCK_SOURCE_ID_EXTERNAL:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK;
-+		return true;
-+	case CLOCK_SOURCE_ID_UNDEFINED:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID;
-+		return true;
-+	default:
-+		/* Unsupported clock source id */
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
-+
-+uint8_t dal_cmd_table_helper_encoder_id_to_atom2(
-+	enum encoder_id id)
-+{
-+	switch (id) {
-+	case ENCODER_ID_INTERNAL_LVDS:
-+		return ENCODER_OBJECT_ID_INTERNAL_LVDS;
-+	case ENCODER_ID_INTERNAL_TMDS1:
-+		return ENCODER_OBJECT_ID_INTERNAL_TMDS1;
-+	case ENCODER_ID_INTERNAL_TMDS2:
-+		return ENCODER_OBJECT_ID_INTERNAL_TMDS2;
-+	case ENCODER_ID_INTERNAL_DAC1:
-+		return ENCODER_OBJECT_ID_INTERNAL_DAC1;
-+	case ENCODER_ID_INTERNAL_DAC2:
-+		return ENCODER_OBJECT_ID_INTERNAL_DAC2;
-+	case ENCODER_ID_INTERNAL_LVTM1:
-+		return ENCODER_OBJECT_ID_INTERNAL_LVTM1;
-+	case ENCODER_ID_INTERNAL_HDMI:
-+		return ENCODER_OBJECT_ID_HDMI_INTERNAL;
-+	case ENCODER_ID_EXTERNAL_TRAVIS:
-+		return ENCODER_OBJECT_ID_TRAVIS;
-+	case ENCODER_ID_EXTERNAL_NUTMEG:
-+		return ENCODER_OBJECT_ID_NUTMEG;
-+	case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
-+		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
-+	case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
-+		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
-+	case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
-+		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
-+	case ENCODER_ID_EXTERNAL_MVPU_FPGA:
-+		return ENCODER_OBJECT_ID_MVPU_FPGA;
-+	case ENCODER_ID_INTERNAL_DDI:
-+		return ENCODER_OBJECT_ID_INTERNAL_DDI;
-+	case ENCODER_ID_INTERNAL_UNIPHY:
-+		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY;
-+	case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
-+		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA;
-+	case ENCODER_ID_INTERNAL_UNIPHY1:
-+		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1;
-+	case ENCODER_ID_INTERNAL_UNIPHY2:
-+		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2;
-+	case ENCODER_ID_INTERNAL_UNIPHY3:
-+		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3;
-+	case ENCODER_ID_INTERNAL_WIRELESS:
-+		return ENCODER_OBJECT_ID_INTERNAL_VCE;
-+	case ENCODER_ID_INTERNAL_VIRTUAL:
-+		return ENCODER_OBJECT_ID_NONE;
-+	case ENCODER_ID_UNKNOWN:
-+		return ENCODER_OBJECT_ID_NONE;
-+	default:
-+		/* Invalid encoder id */
-+		BREAK_TO_DEBUGGER();
-+		return ENCODER_OBJECT_ID_NONE;
-+	}
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h.0130~	2017-12-14 06:39:58.401903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h	2017-12-14 06:39:58.401903558 +0100
-@@ -0,0 +1,82 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMMAND_TABLE_HELPER2_H__
-+#define __DAL_COMMAND_TABLE_HELPER2_H__
-+
-+#include "dce80/command_table_helper_dce80.h"
-+#include "dce110/command_table_helper_dce110.h"
-+#include "dce112/command_table_helper2_dce112.h"
-+
-+struct command_table_helper {
-+	bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);
-+	uint8_t (*encoder_action_to_atom)(
-+			enum bp_encoder_control_action action);
-+	uint32_t (*encoder_mode_bp_to_atom)(enum signal_type s,
-+			bool enable_dp_audio);
-+	bool (*engine_bp_to_atom)(enum engine_id engine_id,
-+			uint32_t *atom_engine_id);
-+	bool (*clock_source_id_to_atom)(enum clock_source_id id,
-+			uint32_t *atom_pll_id);
-+	bool (*clock_source_id_to_ref_clk_src)(
-+			enum clock_source_id id,
-+			uint32_t *ref_clk_src_id);
-+	uint8_t (*transmitter_bp_to_atom)(enum transmitter t);
-+	uint8_t (*encoder_id_to_atom)(enum encoder_id id);
-+	uint8_t (*clock_source_id_to_atom_phy_clk_src_id)(
-+			enum clock_source_id id);
-+	uint8_t (*signal_type_to_atom_dig_mode)(enum signal_type s);
-+	uint8_t (*hpd_sel_to_atom)(enum hpd_source_id id);
-+	uint8_t (*dig_encoder_sel_to_atom)(enum engine_id engine_id);
-+	uint8_t (*phy_id_to_atom)(enum transmitter t);
-+	uint8_t (*disp_power_gating_action_to_atom)(
-+			enum bp_pipe_control_action action);
-+	bool (*dc_clock_type_to_atom)(enum bp_dce_clock_type id,
-+			uint32_t *atom_clock_type);
-+	uint8_t (*transmitter_color_depth_to_atom)(
-+			enum transmitter_color_depth id);
-+};
-+
-+bool dal_bios_parser_init_cmd_tbl_helper2(const struct command_table_helper **h,
-+	enum dce_version dce);
-+
-+bool dal_cmd_table_helper_controller_id_to_atom2(
-+	enum controller_id id,
-+	uint8_t *atom_id);
-+
-+uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2(
-+	enum signal_type s,
-+	bool enable_dp_audio);
-+
-+bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2(
-+	enum clock_source_id id,
-+	uint32_t *ref_clk_src_id);
-+
-+uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2(
-+	enum transmitter t);
-+
-+uint8_t dal_cmd_table_helper_encoder_id_to_atom2(
-+	enum encoder_id id);
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c.0130~	2017-12-14 06:39:58.401903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c	2017-12-14 06:39:58.401903558 +0100
-@@ -0,0 +1,290 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/bios_parser_types.h"
-+
-+#include "command_table_helper.h"
-+
-+bool dal_bios_parser_init_cmd_tbl_helper(
-+	const struct command_table_helper **h,
-+	enum dce_version dce)
-+{
-+	switch (dce) {
-+	case DCE_VERSION_8_0:
-+	case DCE_VERSION_8_1:
-+	case DCE_VERSION_8_3:
-+		*h = dal_cmd_tbl_helper_dce80_get_table();
-+		return true;
-+
-+	case DCE_VERSION_10_0:
-+		*h = dal_cmd_tbl_helper_dce110_get_table();
-+		return true;
-+
-+	case DCE_VERSION_11_0:
-+		*h = dal_cmd_tbl_helper_dce110_get_table();
-+		return true;
-+
-+	case DCE_VERSION_11_2:
-+		*h = dal_cmd_tbl_helper_dce112_get_table();
-+		return true;
-+
-+	default:
-+		/* Unsupported DCE */
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
-+
-+/* real implementations */
-+
-+bool dal_cmd_table_helper_controller_id_to_atom(
-+	enum controller_id id,
-+	uint8_t *atom_id)
-+{
-+	if (atom_id == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	switch (id) {
-+	case CONTROLLER_ID_D0:
-+		*atom_id = ATOM_CRTC1;
-+		return true;
-+	case CONTROLLER_ID_D1:
-+		*atom_id = ATOM_CRTC2;
-+		return true;
-+	case CONTROLLER_ID_D2:
-+		*atom_id = ATOM_CRTC3;
-+		return true;
-+	case CONTROLLER_ID_D3:
-+		*atom_id = ATOM_CRTC4;
-+		return true;
-+	case CONTROLLER_ID_D4:
-+		*atom_id = ATOM_CRTC5;
-+		return true;
-+	case CONTROLLER_ID_D5:
-+		*atom_id = ATOM_CRTC6;
-+		return true;
-+	case CONTROLLER_ID_UNDERLAY0:
-+		*atom_id = ATOM_UNDERLAY_PIPE0;
-+		return true;
-+	case CONTROLLER_ID_UNDEFINED:
-+		*atom_id = ATOM_CRTC_INVALID;
-+		return true;
-+	default:
-+		/* Wrong controller id */
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
-+
-+/**
-+* translate_transmitter_bp_to_atom
-+*
-+* @brief
-+*  Translate the Transmitter to the corresponding ATOM BIOS value
-+*
-+* @param
-+*   input transmitter
-+*   output digitalTransmitter
-+*    // =00: Digital Transmitter1 ( UNIPHY linkAB )
-+*    // =01: Digital Transmitter2 ( UNIPHY linkCD )
-+*    // =02: Digital Transmitter3 ( UNIPHY linkEF )
-+*/
-+uint8_t dal_cmd_table_helper_transmitter_bp_to_atom(
-+	enum transmitter t)
-+{
-+	switch (t) {
-+	case TRANSMITTER_UNIPHY_A:
-+	case TRANSMITTER_UNIPHY_B:
-+	case TRANSMITTER_TRAVIS_LCD:
-+		return 0;
-+	case TRANSMITTER_UNIPHY_C:
-+	case TRANSMITTER_UNIPHY_D:
-+		return 1;
-+	case TRANSMITTER_UNIPHY_E:
-+	case TRANSMITTER_UNIPHY_F:
-+		return 2;
-+	default:
-+		/* Invalid Transmitter Type! */
-+		BREAK_TO_DEBUGGER();
-+		return 0;
-+	}
-+}
-+
-+uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom(
-+	enum signal_type s,
-+	bool enable_dp_audio)
-+{
-+	switch (s) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		return ATOM_ENCODER_MODE_DVI;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		return ATOM_ENCODER_MODE_HDMI;
-+	case SIGNAL_TYPE_LVDS:
-+		return ATOM_ENCODER_MODE_LVDS;
-+	case SIGNAL_TYPE_EDP:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_VIRTUAL:
-+		if (enable_dp_audio)
-+			return ATOM_ENCODER_MODE_DP_AUDIO;
-+		else
-+			return ATOM_ENCODER_MODE_DP;
-+	case SIGNAL_TYPE_RGB:
-+		return ATOM_ENCODER_MODE_CRT;
-+	default:
-+		return ATOM_ENCODER_MODE_CRT;
-+	}
-+}
-+
-+void dal_cmd_table_helper_assign_control_parameter(
-+	const struct command_table_helper *h,
-+	struct bp_encoder_control *control,
-+	DIG_ENCODER_CONTROL_PARAMETERS_V2 *ctrl_param)
-+{
-+	/* there are three transmitter blocks, each one has two links 4-lanes
-+	 * each, A+B, C+D, E+F, Uniphy A, C and E are enumerated as link 0 in
-+	 * each transmitter block B, D and F as link 1, third transmitter block
-+	 * has non splitable links (UniphyE and UniphyF can not be configured
-+	 * separately to drive two different streams)
-+	 */
-+	if ((control->transmitter == TRANSMITTER_UNIPHY_B) ||
-+		(control->transmitter == TRANSMITTER_UNIPHY_D) ||
-+		(control->transmitter == TRANSMITTER_UNIPHY_F)) {
-+		/* Bit2: Link Select
-+		 * =0: PHY linkA/C/E
-+		 * =1: PHY linkB/D/F
-+		 */
-+		ctrl_param->acConfig.ucLinkSel = 1;
-+	}
-+
-+	/* Bit[4:3]: Transmitter Selection
-+	 * =00: Digital Transmitter1 ( UNIPHY linkAB )
-+	 * =01: Digital Transmitter2 ( UNIPHY linkCD )
-+	 * =02: Digital Transmitter3 ( UNIPHY linkEF )
-+	 * =03: Reserved
-+	 */
-+	ctrl_param->acConfig.ucTransmitterSel =
-+		(uint8_t)(h->transmitter_bp_to_atom(control->transmitter));
-+
-+	/* We need to convert from KHz units into 10KHz units */
-+	ctrl_param->ucAction = h->encoder_action_to_atom(control->action);
-+	ctrl_param->usPixelClock = cpu_to_le16((uint16_t)(control->pixel_clock / 10));
-+	ctrl_param->ucEncoderMode =
-+		(uint8_t)(h->encoder_mode_bp_to_atom(
-+			control->signal, control->enable_dp_audio));
-+	ctrl_param->ucLaneNum = (uint8_t)(control->lanes_number);
-+}
-+
-+bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src(
-+	enum clock_source_id id,
-+	uint32_t *ref_clk_src_id)
-+{
-+	if (ref_clk_src_id == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	switch (id) {
-+	case CLOCK_SOURCE_ID_PLL1:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL;
-+		return true;
-+	case CLOCK_SOURCE_ID_PLL2:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL;
-+		return true;
-+	case CLOCK_SOURCE_ID_DCPLL:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL;
-+		return true;
-+	case CLOCK_SOURCE_ID_EXTERNAL:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK;
-+		return true;
-+	case CLOCK_SOURCE_ID_UNDEFINED:
-+		*ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID;
-+		return true;
-+	default:
-+		/* Unsupported clock source id */
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
-+
-+uint8_t dal_cmd_table_helper_encoder_id_to_atom(
-+	enum encoder_id id)
-+{
-+	switch (id) {
-+	case ENCODER_ID_INTERNAL_LVDS:
-+		return ENCODER_OBJECT_ID_INTERNAL_LVDS;
-+	case ENCODER_ID_INTERNAL_TMDS1:
-+		return ENCODER_OBJECT_ID_INTERNAL_TMDS1;
-+	case ENCODER_ID_INTERNAL_TMDS2:
-+		return ENCODER_OBJECT_ID_INTERNAL_TMDS2;
-+	case ENCODER_ID_INTERNAL_DAC1:
-+		return ENCODER_OBJECT_ID_INTERNAL_DAC1;
-+	case ENCODER_ID_INTERNAL_DAC2:
-+		return ENCODER_OBJECT_ID_INTERNAL_DAC2;
-+	case ENCODER_ID_INTERNAL_LVTM1:
-+		return ENCODER_OBJECT_ID_INTERNAL_LVTM1;
-+	case ENCODER_ID_INTERNAL_HDMI:
-+		return ENCODER_OBJECT_ID_HDMI_INTERNAL;
-+	case ENCODER_ID_EXTERNAL_TRAVIS:
-+		return ENCODER_OBJECT_ID_TRAVIS;
-+	case ENCODER_ID_EXTERNAL_NUTMEG:
-+		return ENCODER_OBJECT_ID_NUTMEG;
-+	case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
-+		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
-+	case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
-+		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
-+	case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
-+		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
-+	case ENCODER_ID_EXTERNAL_MVPU_FPGA:
-+		return ENCODER_OBJECT_ID_MVPU_FPGA;
-+	case ENCODER_ID_INTERNAL_DDI:
-+		return ENCODER_OBJECT_ID_INTERNAL_DDI;
-+	case ENCODER_ID_INTERNAL_UNIPHY:
-+		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY;
-+	case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
-+		return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA;
-+	case ENCODER_ID_INTERNAL_UNIPHY1:
-+		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1;
-+	case ENCODER_ID_INTERNAL_UNIPHY2:
-+		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2;
-+	case ENCODER_ID_INTERNAL_UNIPHY3:
-+		return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3;
-+	case ENCODER_ID_INTERNAL_WIRELESS:
-+		return ENCODER_OBJECT_ID_INTERNAL_VCE;
-+	case ENCODER_ID_UNKNOWN:
-+		return ENCODER_OBJECT_ID_NONE;
-+	default:
-+		/* Invalid encoder id */
-+		BREAK_TO_DEBUGGER();
-+		return ENCODER_OBJECT_ID_NONE;
-+	}
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h.0130~	2017-12-14 06:39:58.401903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.h	2017-12-14 06:39:58.401903558 +0100
-@@ -0,0 +1,90 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMMAND_TABLE_HELPER_H__
-+#define __DAL_COMMAND_TABLE_HELPER_H__
-+
-+#include "dce80/command_table_helper_dce80.h"
-+#include "dce110/command_table_helper_dce110.h"
-+#include "dce112/command_table_helper_dce112.h"
-+
-+struct command_table_helper {
-+	bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);
-+	uint8_t (*encoder_action_to_atom)(
-+			enum bp_encoder_control_action action);
-+	uint32_t (*encoder_mode_bp_to_atom)(enum signal_type s,
-+			bool enable_dp_audio);
-+	bool (*engine_bp_to_atom)(enum engine_id engine_id,
-+			uint32_t *atom_engine_id);
-+	void (*assign_control_parameter)(
-+			const struct command_table_helper *h,
-+			struct bp_encoder_control *control,
-+			DIG_ENCODER_CONTROL_PARAMETERS_V2 *ctrl_param);
-+	bool (*clock_source_id_to_atom)(enum clock_source_id id,
-+			uint32_t *atom_pll_id);
-+	bool (*clock_source_id_to_ref_clk_src)(
-+			enum clock_source_id id,
-+			uint32_t *ref_clk_src_id);
-+	uint8_t (*transmitter_bp_to_atom)(enum transmitter t);
-+	uint8_t (*encoder_id_to_atom)(enum encoder_id id);
-+	uint8_t (*clock_source_id_to_atom_phy_clk_src_id)(
-+			enum clock_source_id id);
-+	uint8_t (*signal_type_to_atom_dig_mode)(enum signal_type s);
-+	uint8_t (*hpd_sel_to_atom)(enum hpd_source_id id);
-+	uint8_t (*dig_encoder_sel_to_atom)(enum engine_id engine_id);
-+	uint8_t (*phy_id_to_atom)(enum transmitter t);
-+	uint8_t (*disp_power_gating_action_to_atom)(
-+			enum bp_pipe_control_action action);
-+	bool (*dc_clock_type_to_atom)(enum bp_dce_clock_type id,
-+			uint32_t *atom_clock_type);
-+    uint8_t (*transmitter_color_depth_to_atom)(enum transmitter_color_depth id);
-+};
-+
-+bool dal_bios_parser_init_cmd_tbl_helper(const struct command_table_helper **h,
-+	enum dce_version dce);
-+
-+bool dal_cmd_table_helper_controller_id_to_atom(
-+	enum controller_id id,
-+	uint8_t *atom_id);
-+
-+uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom(
-+	enum signal_type s,
-+	bool enable_dp_audio);
-+
-+void dal_cmd_table_helper_assign_control_parameter(
-+	const struct command_table_helper *h,
-+	struct bp_encoder_control *control,
-+DIG_ENCODER_CONTROL_PARAMETERS_V2 *ctrl_param);
-+
-+bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src(
-+	enum clock_source_id id,
-+	uint32_t *ref_clk_src_id);
-+
-+uint8_t dal_cmd_table_helper_transmitter_bp_to_atom(
-+	enum transmitter t);
-+
-+uint8_t dal_cmd_table_helper_encoder_id_to_atom(
-+	enum encoder_id id);
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c.0130~	2017-12-14 06:39:58.401903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c	2017-12-14 06:39:58.401903558 +0100
-@@ -0,0 +1,364 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/bios_parser_types.h"
-+
-+#include "../command_table_helper.h"
-+
-+static uint8_t phy_id_to_atom(enum transmitter t)
-+{
-+	uint8_t atom_phy_id;
-+
-+	switch (t) {
-+	case TRANSMITTER_UNIPHY_A:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
-+		break;
-+	case TRANSMITTER_UNIPHY_B:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYB;
-+		break;
-+	case TRANSMITTER_UNIPHY_C:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYC;
-+		break;
-+	case TRANSMITTER_UNIPHY_D:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYD;
-+		break;
-+	case TRANSMITTER_UNIPHY_E:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYE;
-+		break;
-+	case TRANSMITTER_UNIPHY_F:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYF;
-+		break;
-+	case TRANSMITTER_UNIPHY_G:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYG;
-+		break;
-+	default:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
-+		break;
-+	}
-+	return atom_phy_id;
-+}
-+
-+static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
-+{
-+	uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
-+
-+	switch (s) {
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_EDP:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
-+		break;
-+	case SIGNAL_TYPE_LVDS:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
-+		break;
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
-+		break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
-+		break;
-+	default:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
-+		break;
-+	}
-+
-+	return atom_dig_mode;
-+}
-+
-+static uint8_t clock_source_id_to_atom_phy_clk_src_id(
-+		enum clock_source_id id)
-+{
-+	uint8_t atom_phy_clk_src_id = 0;
-+
-+	switch (id) {
-+	case CLOCK_SOURCE_ID_PLL0:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL1:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL2:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_EXTERNAL:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
-+		break;
-+	default:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
-+		break;
-+	}
-+
-+	return atom_phy_clk_src_id >> 2;
-+}
-+
-+static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
-+{
-+	uint8_t atom_hpd_sel = 0;
-+
-+	switch (id) {
-+	case HPD_SOURCEID1:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
-+		break;
-+	case HPD_SOURCEID2:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
-+		break;
-+	case HPD_SOURCEID3:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
-+		break;
-+	case HPD_SOURCEID4:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
-+		break;
-+	case HPD_SOURCEID5:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
-+		break;
-+	case HPD_SOURCEID6:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL;
-+		break;
-+	case HPD_SOURCEID_UNKNOWN:
-+	default:
-+		atom_hpd_sel = 0;
-+		break;
-+	}
-+	return atom_hpd_sel >> 4;
-+}
-+
-+static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
-+{
-+	uint8_t atom_dig_encoder_sel = 0;
-+
-+	switch (id) {
-+	case ENGINE_ID_DIGA:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
-+		break;
-+	case ENGINE_ID_DIGB:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
-+		break;
-+	case ENGINE_ID_DIGC:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
-+		break;
-+	case ENGINE_ID_DIGD:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
-+		break;
-+	case ENGINE_ID_DIGE:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
-+		break;
-+	case ENGINE_ID_DIGF:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
-+		break;
-+	case ENGINE_ID_DIGG:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
-+		break;
-+	case ENGINE_ID_UNKNOWN:
-+		 /* No DIG_FRONT is associated to DIG_BACKEND */
-+		atom_dig_encoder_sel = 0;
-+		break;
-+	default:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static bool clock_source_id_to_atom(
-+	enum clock_source_id id,
-+	uint32_t *atom_pll_id)
-+{
-+	bool result = true;
-+
-+	if (atom_pll_id != NULL)
-+		switch (id) {
-+		case CLOCK_SOURCE_ID_PLL0:
-+			*atom_pll_id = ATOM_PPLL0;
-+			break;
-+		case CLOCK_SOURCE_ID_PLL1:
-+			*atom_pll_id = ATOM_PPLL1;
-+			break;
-+		case CLOCK_SOURCE_ID_PLL2:
-+			*atom_pll_id = ATOM_PPLL2;
-+			break;
-+		case CLOCK_SOURCE_ID_EXTERNAL:
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			break;
-+		case CLOCK_SOURCE_ID_DFS:
-+			*atom_pll_id = ATOM_EXT_PLL1;
-+			break;
-+		case CLOCK_SOURCE_ID_VCE:
-+			/* for VCE encoding,
-+			 * we need to pass in ATOM_PPLL_INVALID
-+			 */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			break;
-+		case CLOCK_SOURCE_ID_DP_DTO:
-+			/* When programming DP DTO PLL ID should be invalid */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			break;
-+		case CLOCK_SOURCE_ID_UNDEFINED:
-+			/* Should not happen */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			result = false;
-+			break;
-+		default:
-+			result = false;
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
-+{
-+	bool result = false;
-+
-+	if (atom_engine_id != NULL)
-+		switch (id) {
-+		case ENGINE_ID_DIGA:
-+			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGB:
-+			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGC:
-+			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGD:
-+			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGE:
-+			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGF:
-+			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGG:
-+			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DACA:
-+			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
-+			result = true;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
-+{
-+	uint8_t atom_action = 0;
-+
-+	switch (action) {
-+	case ENCODER_CONTROL_ENABLE:
-+		atom_action = ATOM_ENABLE;
-+		break;
-+	case ENCODER_CONTROL_DISABLE:
-+		atom_action = ATOM_DISABLE;
-+		break;
-+	case ENCODER_CONTROL_SETUP:
-+		atom_action = ATOM_ENCODER_CMD_SETUP;
-+		break;
-+	case ENCODER_CONTROL_INIT:
-+		atom_action = ATOM_ENCODER_INIT;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
-+		break;
-+	}
-+
-+	return atom_action;
-+}
-+
-+static uint8_t disp_power_gating_action_to_atom(
-+	enum bp_pipe_control_action action)
-+{
-+	uint8_t atom_pipe_action = 0;
-+
-+	switch (action) {
-+	case ASIC_PIPE_DISABLE:
-+		atom_pipe_action = ATOM_DISABLE;
-+		break;
-+	case ASIC_PIPE_ENABLE:
-+		atom_pipe_action = ATOM_ENABLE;
-+		break;
-+	case ASIC_PIPE_INIT:
-+		atom_pipe_action = ATOM_INIT;
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false); /* Unhandle action in driver! */
-+		break;
-+	}
-+
-+	return atom_pipe_action;
-+}
-+
-+/* function table */
-+static const struct command_table_helper command_table_helper_funcs = {
-+	.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
-+	.encoder_action_to_atom = encoder_action_to_atom,
-+	.engine_bp_to_atom = engine_bp_to_atom,
-+	.clock_source_id_to_atom = clock_source_id_to_atom,
-+	.clock_source_id_to_atom_phy_clk_src_id =
-+			clock_source_id_to_atom_phy_clk_src_id,
-+	.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
-+	.hpd_sel_to_atom = hpd_sel_to_atom,
-+	.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
-+	.phy_id_to_atom = phy_id_to_atom,
-+	.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
-+	.assign_control_parameter = NULL,
-+	.clock_source_id_to_ref_clk_src = NULL,
-+	.transmitter_bp_to_atom = NULL,
-+	.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
-+	.encoder_mode_bp_to_atom = dal_cmd_table_helper_encoder_mode_bp_to_atom,
-+};
-+
-+/*
-+ * dal_cmd_tbl_helper_dce110_get_table
-+ *
-+ * @brief
-+ * Initialize command table helper functions
-+ *
-+ * @param
-+ * const struct command_table_helper **h - [out] struct of functions
-+ *
-+ */
-+const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void)
-+{
-+	return &command_table_helper_funcs;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.h.0130~	2017-12-14 06:39:58.401903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.h	2017-12-14 06:39:58.401903558 +0100
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMMAND_TABLE_HELPER_DCE110_H__
-+#define __DAL_COMMAND_TABLE_HELPER_DCE110_H__
-+
-+struct command_table_helper;
-+
-+/* Initialize command table helper functions */
-+const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void);
-+
-+#endif /* __DAL_COMMAND_TABLE_HELPER_DCE110_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c.0130~	2017-12-14 06:39:58.401903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c	2017-12-14 06:39:58.401903558 +0100
-@@ -0,0 +1,418 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/bios_parser_types.h"
-+
-+#include "../command_table_helper2.h"
-+
-+static uint8_t phy_id_to_atom(enum transmitter t)
-+{
-+	uint8_t atom_phy_id;
-+
-+	switch (t) {
-+	case TRANSMITTER_UNIPHY_A:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
-+		break;
-+	case TRANSMITTER_UNIPHY_B:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYB;
-+		break;
-+	case TRANSMITTER_UNIPHY_C:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYC;
-+		break;
-+	case TRANSMITTER_UNIPHY_D:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYD;
-+		break;
-+	case TRANSMITTER_UNIPHY_E:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYE;
-+		break;
-+	case TRANSMITTER_UNIPHY_F:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYF;
-+		break;
-+	case TRANSMITTER_UNIPHY_G:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYG;
-+		break;
-+	default:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
-+		break;
-+	}
-+	return atom_phy_id;
-+}
-+
-+static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
-+{
-+	uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;
-+
-+	switch (s) {
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_EDP:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;
-+		break;
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DVI;
-+		break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_HDMI;
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP_MST;
-+		break;
-+	default:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DVI;
-+		break;
-+	}
-+
-+	return atom_dig_mode;
-+}
-+
-+static uint8_t clock_source_id_to_atom_phy_clk_src_id(
-+		enum clock_source_id id)
-+{
-+	uint8_t atom_phy_clk_src_id = 0;
-+
-+	switch (id) {
-+	case CLOCK_SOURCE_ID_PLL0:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL1:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL2:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_EXTERNAL:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
-+		break;
-+	default:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
-+		break;
-+	}
-+
-+	return atom_phy_clk_src_id >> 2;
-+}
-+
-+static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
-+{
-+	uint8_t atom_hpd_sel = 0;
-+
-+	switch (id) {
-+	case HPD_SOURCEID1:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD1_SEL;
-+		break;
-+	case HPD_SOURCEID2:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD2_SEL;
-+		break;
-+	case HPD_SOURCEID3:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD3_SEL;
-+		break;
-+	case HPD_SOURCEID4:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD4_SEL;
-+		break;
-+	case HPD_SOURCEID5:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD5_SEL;
-+		break;
-+	case HPD_SOURCEID6:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD6_SEL;
-+		break;
-+	case HPD_SOURCEID_UNKNOWN:
-+	default:
-+		atom_hpd_sel = 0;
-+		break;
-+	}
-+	return atom_hpd_sel;
-+}
-+
-+static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
-+{
-+	uint8_t atom_dig_encoder_sel = 0;
-+
-+	switch (id) {
-+	case ENGINE_ID_DIGA:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
-+		break;
-+	case ENGINE_ID_DIGB:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL;
-+		break;
-+	case ENGINE_ID_DIGC:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL;
-+		break;
-+	case ENGINE_ID_DIGD:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL;
-+		break;
-+	case ENGINE_ID_DIGE:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL;
-+		break;
-+	case ENGINE_ID_DIGF:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL;
-+		break;
-+	case ENGINE_ID_DIGG:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL;
-+		break;
-+	case ENGINE_ID_UNKNOWN:
-+		/* No DIG_FRONT is associated to DIG_BACKEND */
-+		atom_dig_encoder_sel = 0;
-+		break;
-+	default:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static bool clock_source_id_to_atom(
-+	enum clock_source_id id,
-+	uint32_t *atom_pll_id)
-+{
-+	bool result = true;
-+
-+	if (atom_pll_id != NULL)
-+		switch (id) {
-+		case CLOCK_SOURCE_COMBO_PHY_PLL0:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL0;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL1:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL1;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL2:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL2;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL3:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL3;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL4:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL4;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL5:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL5;
-+			break;
-+		case CLOCK_SOURCE_COMBO_DISPLAY_PLL0:
-+			*atom_pll_id = ATOM_PPLL0;
-+			break;
-+		case CLOCK_SOURCE_ID_DFS:
-+			*atom_pll_id = ATOM_GCK_DFS;
-+			break;
-+		case CLOCK_SOURCE_ID_VCE:
-+			*atom_pll_id = ATOM_DP_DTO;
-+			break;
-+		case CLOCK_SOURCE_ID_DP_DTO:
-+			*atom_pll_id = ATOM_DP_DTO;
-+			break;
-+		case CLOCK_SOURCE_ID_UNDEFINED:
-+			/* Should not happen */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			result = false;
-+			break;
-+		default:
-+			result = false;
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
-+{
-+	bool result = false;
-+
-+	if (atom_engine_id != NULL)
-+		switch (id) {
-+		case ENGINE_ID_DIGA:
-+			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGB:
-+			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGC:
-+			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGD:
-+			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGE:
-+			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGF:
-+			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGG:
-+			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DACA:
-+			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
-+			result = true;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
-+{
-+	uint8_t atom_action = 0;
-+
-+	switch (action) {
-+	case ENCODER_CONTROL_ENABLE:
-+		atom_action = ATOM_ENABLE;
-+		break;
-+	case ENCODER_CONTROL_DISABLE:
-+		atom_action = ATOM_DISABLE;
-+		break;
-+	case ENCODER_CONTROL_SETUP:
-+		atom_action = ATOM_ENCODER_CMD_STREAM_SETUP;
-+		break;
-+	case ENCODER_CONTROL_INIT:
-+		atom_action = ATOM_ENCODER_INIT;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
-+		break;
-+	}
-+
-+	return atom_action;
-+}
-+
-+static uint8_t disp_power_gating_action_to_atom(
-+	enum bp_pipe_control_action action)
-+{
-+	uint8_t atom_pipe_action = 0;
-+
-+	switch (action) {
-+	case ASIC_PIPE_DISABLE:
-+		atom_pipe_action = ATOM_DISABLE;
-+		break;
-+	case ASIC_PIPE_ENABLE:
-+		atom_pipe_action = ATOM_ENABLE;
-+		break;
-+	case ASIC_PIPE_INIT:
-+		atom_pipe_action = ATOM_INIT;
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false); /* Unhandle action in driver! */
-+		break;
-+	}
-+
-+	return atom_pipe_action;
-+}
-+
-+static bool dc_clock_type_to_atom(
-+		enum bp_dce_clock_type id,
-+		uint32_t *atom_clock_type)
-+{
-+	bool retCode = true;
-+
-+	if (atom_clock_type != NULL) {
-+		switch (id) {
-+		case DCECLOCK_TYPE_DISPLAY_CLOCK:
-+			*atom_clock_type = DCE_CLOCK_TYPE_DISPCLK;
-+			break;
-+
-+		case DCECLOCK_TYPE_DPREFCLK:
-+			*atom_clock_type = DCE_CLOCK_TYPE_DPREFCLK;
-+			break;
-+
-+		default:
-+			ASSERT_CRITICAL(false); /* Unhandle action in driver! */
-+			break;
-+		}
-+	}
-+
-+	return retCode;
-+}
-+
-+static uint8_t transmitter_color_depth_to_atom(enum transmitter_color_depth id)
-+{
-+	uint8_t atomColorDepth = 0;
-+
-+	switch (id) {
-+	case TRANSMITTER_COLOR_DEPTH_24:
-+		atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS;
-+		break;
-+	case TRANSMITTER_COLOR_DEPTH_30:
-+		atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4;
-+		break;
-+	case TRANSMITTER_COLOR_DEPTH_36:
-+		atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2;
-+		break;
-+	case TRANSMITTER_COLOR_DEPTH_48:
-+		atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1;
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false); /* Unhandle action in driver! */
-+		break;
-+	}
-+
-+	return atomColorDepth;
-+}
-+
-+/* function table */
-+static const struct command_table_helper command_table_helper_funcs = {
-+	.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom2,
-+	.encoder_action_to_atom = encoder_action_to_atom,
-+	.engine_bp_to_atom = engine_bp_to_atom,
-+	.clock_source_id_to_atom = clock_source_id_to_atom,
-+	.clock_source_id_to_atom_phy_clk_src_id =
-+			clock_source_id_to_atom_phy_clk_src_id,
-+	.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
-+	.hpd_sel_to_atom = hpd_sel_to_atom,
-+	.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
-+	.phy_id_to_atom = phy_id_to_atom,
-+	.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
-+	.clock_source_id_to_ref_clk_src = NULL,
-+	.transmitter_bp_to_atom = NULL,
-+	.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom2,
-+	.encoder_mode_bp_to_atom =
-+			dal_cmd_table_helper_encoder_mode_bp_to_atom2,
-+	.dc_clock_type_to_atom = dc_clock_type_to_atom,
-+	.transmitter_color_depth_to_atom = transmitter_color_depth_to_atom,
-+};
-+
-+/*
-+ * dal_cmd_tbl_helper_dce110_get_table
-+ *
-+ * @brief
-+ * Initialize command table helper functions
-+ *
-+ * @param
-+ * const struct command_table_helper **h - [out] struct of functions
-+ *
-+ */
-+const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table2(void)
-+{
-+	return &command_table_helper_funcs;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h.0130~	2017-12-14 06:39:58.401903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h	2017-12-14 06:39:58.401903558 +0100
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMMAND_TABLE_HELPER2_DCE112_H__
-+#define __DAL_COMMAND_TABLE_HELPER2_DCE112_H__
-+
-+struct command_table_helper;
-+
-+/* Initialize command table helper functions */
-+const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table2(void);
-+
-+#endif /* __DAL_COMMAND_TABLE_HELPER_DCE110_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c.0130~	2017-12-14 06:39:58.401903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c	2017-12-14 06:39:58.401903558 +0100
-@@ -0,0 +1,418 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/bios_parser_types.h"
-+
-+#include "../command_table_helper.h"
-+
-+static uint8_t phy_id_to_atom(enum transmitter t)
-+{
-+	uint8_t atom_phy_id;
-+
-+	switch (t) {
-+	case TRANSMITTER_UNIPHY_A:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
-+		break;
-+	case TRANSMITTER_UNIPHY_B:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYB;
-+		break;
-+	case TRANSMITTER_UNIPHY_C:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYC;
-+		break;
-+	case TRANSMITTER_UNIPHY_D:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYD;
-+		break;
-+	case TRANSMITTER_UNIPHY_E:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYE;
-+		break;
-+	case TRANSMITTER_UNIPHY_F:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYF;
-+		break;
-+	case TRANSMITTER_UNIPHY_G:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYG;
-+		break;
-+	default:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
-+		break;
-+	}
-+	return atom_phy_id;
-+}
-+
-+static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
-+{
-+	uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;
-+
-+	switch (s) {
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_EDP:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP;
-+		break;
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DVI;
-+		break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_HDMI;
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DP_MST;
-+		break;
-+	default:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V6_DVI;
-+		break;
-+	}
-+
-+	return atom_dig_mode;
-+}
-+
-+static uint8_t clock_source_id_to_atom_phy_clk_src_id(
-+		enum clock_source_id id)
-+{
-+	uint8_t atom_phy_clk_src_id = 0;
-+
-+	switch (id) {
-+	case CLOCK_SOURCE_ID_PLL0:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL1:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL2:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_EXTERNAL:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
-+		break;
-+	default:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
-+		break;
-+	}
-+
-+	return atom_phy_clk_src_id >> 2;
-+}
-+
-+static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
-+{
-+	uint8_t atom_hpd_sel = 0;
-+
-+	switch (id) {
-+	case HPD_SOURCEID1:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD1_SEL;
-+		break;
-+	case HPD_SOURCEID2:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD2_SEL;
-+		break;
-+	case HPD_SOURCEID3:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD3_SEL;
-+		break;
-+	case HPD_SOURCEID4:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD4_SEL;
-+		break;
-+	case HPD_SOURCEID5:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD5_SEL;
-+		break;
-+	case HPD_SOURCEID6:
-+		atom_hpd_sel = ATOM_TRANSMITTER_V6_HPD6_SEL;
-+		break;
-+	case HPD_SOURCEID_UNKNOWN:
-+	default:
-+		atom_hpd_sel = 0;
-+		break;
-+	}
-+	return atom_hpd_sel;
-+}
-+
-+static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
-+{
-+	uint8_t atom_dig_encoder_sel = 0;
-+
-+	switch (id) {
-+	case ENGINE_ID_DIGA:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
-+		break;
-+	case ENGINE_ID_DIGB:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL;
-+		break;
-+	case ENGINE_ID_DIGC:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL;
-+		break;
-+	case ENGINE_ID_DIGD:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL;
-+		break;
-+	case ENGINE_ID_DIGE:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL;
-+		break;
-+	case ENGINE_ID_DIGF:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL;
-+		break;
-+	case ENGINE_ID_DIGG:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL;
-+		break;
-+	case ENGINE_ID_UNKNOWN:
-+		/* No DIG_FRONT is associated to DIG_BACKEND */
-+		atom_dig_encoder_sel = 0;
-+		break;
-+	default:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static bool clock_source_id_to_atom(
-+	enum clock_source_id id,
-+	uint32_t *atom_pll_id)
-+{
-+	bool result = true;
-+
-+	if (atom_pll_id != NULL)
-+		switch (id) {
-+		case CLOCK_SOURCE_COMBO_PHY_PLL0:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL0;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL1:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL1;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL2:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL2;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL3:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL3;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL4:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL4;
-+			break;
-+		case CLOCK_SOURCE_COMBO_PHY_PLL5:
-+			*atom_pll_id = ATOM_COMBOPHY_PLL5;
-+			break;
-+		case CLOCK_SOURCE_COMBO_DISPLAY_PLL0:
-+			*atom_pll_id = ATOM_PPLL0;
-+			break;
-+		case CLOCK_SOURCE_ID_DFS:
-+			*atom_pll_id = ATOM_GCK_DFS;
-+			break;
-+		case CLOCK_SOURCE_ID_VCE:
-+			*atom_pll_id = ATOM_DP_DTO;
-+			break;
-+		case CLOCK_SOURCE_ID_DP_DTO:
-+			*atom_pll_id = ATOM_DP_DTO;
-+			break;
-+		case CLOCK_SOURCE_ID_UNDEFINED:
-+			/* Should not happen */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			result = false;
-+			break;
-+		default:
-+			result = false;
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
-+{
-+	bool result = false;
-+
-+	if (atom_engine_id != NULL)
-+		switch (id) {
-+		case ENGINE_ID_DIGA:
-+			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGB:
-+			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGC:
-+			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGD:
-+			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGE:
-+			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGF:
-+			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGG:
-+			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DACA:
-+			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
-+			result = true;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
-+{
-+	uint8_t atom_action = 0;
-+
-+	switch (action) {
-+	case ENCODER_CONTROL_ENABLE:
-+		atom_action = ATOM_ENABLE;
-+		break;
-+	case ENCODER_CONTROL_DISABLE:
-+		atom_action = ATOM_DISABLE;
-+		break;
-+	case ENCODER_CONTROL_SETUP:
-+		atom_action = ATOM_ENCODER_CMD_STREAM_SETUP;
-+		break;
-+	case ENCODER_CONTROL_INIT:
-+		atom_action = ATOM_ENCODER_INIT;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
-+		break;
-+	}
-+
-+	return atom_action;
-+}
-+
-+static uint8_t disp_power_gating_action_to_atom(
-+	enum bp_pipe_control_action action)
-+{
-+	uint8_t atom_pipe_action = 0;
-+
-+	switch (action) {
-+	case ASIC_PIPE_DISABLE:
-+		atom_pipe_action = ATOM_DISABLE;
-+		break;
-+	case ASIC_PIPE_ENABLE:
-+		atom_pipe_action = ATOM_ENABLE;
-+		break;
-+	case ASIC_PIPE_INIT:
-+		atom_pipe_action = ATOM_INIT;
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false); /* Unhandle action in driver! */
-+		break;
-+	}
-+
-+	return atom_pipe_action;
-+}
-+
-+static bool dc_clock_type_to_atom(
-+		enum bp_dce_clock_type id,
-+		uint32_t *atom_clock_type)
-+{
-+	bool retCode = true;
-+
-+	if (atom_clock_type != NULL) {
-+		switch (id) {
-+		case DCECLOCK_TYPE_DISPLAY_CLOCK:
-+			*atom_clock_type = DCE_CLOCK_TYPE_DISPCLK;
-+			break;
-+
-+		case DCECLOCK_TYPE_DPREFCLK:
-+			*atom_clock_type = DCE_CLOCK_TYPE_DPREFCLK;
-+			break;
-+
-+		default:
-+			ASSERT_CRITICAL(false); /* Unhandle action in driver! */
-+			break;
-+		}
-+	}
-+
-+	return retCode;
-+}
-+
-+static uint8_t transmitter_color_depth_to_atom(enum transmitter_color_depth id)
-+{
-+	uint8_t atomColorDepth = 0;
-+
-+	switch (id) {
-+	case TRANSMITTER_COLOR_DEPTH_24:
-+		atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS;
-+		break;
-+	case TRANSMITTER_COLOR_DEPTH_30:
-+		atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4;
-+		break;
-+	case TRANSMITTER_COLOR_DEPTH_36:
-+		atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2;
-+		break;
-+	case TRANSMITTER_COLOR_DEPTH_48:
-+		atomColorDepth = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1;
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false); /* Unhandle action in driver! */
-+		break;
-+	}
-+
-+	return atomColorDepth;
-+}
-+
-+/* function table */
-+static const struct command_table_helper command_table_helper_funcs = {
-+	.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
-+	.encoder_action_to_atom = encoder_action_to_atom,
-+	.engine_bp_to_atom = engine_bp_to_atom,
-+	.clock_source_id_to_atom = clock_source_id_to_atom,
-+	.clock_source_id_to_atom_phy_clk_src_id =
-+			clock_source_id_to_atom_phy_clk_src_id,
-+	.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
-+	.hpd_sel_to_atom = hpd_sel_to_atom,
-+	.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
-+	.phy_id_to_atom = phy_id_to_atom,
-+	.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
-+	.assign_control_parameter = NULL,
-+	.clock_source_id_to_ref_clk_src = NULL,
-+	.transmitter_bp_to_atom = NULL,
-+	.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
-+	.encoder_mode_bp_to_atom = dal_cmd_table_helper_encoder_mode_bp_to_atom,
-+	.dc_clock_type_to_atom = dc_clock_type_to_atom,
-+	.transmitter_color_depth_to_atom = transmitter_color_depth_to_atom,
-+};
-+
-+/*
-+ * dal_cmd_tbl_helper_dce110_get_table
-+ *
-+ * @brief
-+ * Initialize command table helper functions
-+ *
-+ * @param
-+ * const struct command_table_helper **h - [out] struct of functions
-+ *
-+ */
-+const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table(void)
-+{
-+	return &command_table_helper_funcs;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.h.0130~	2017-12-14 06:39:58.402903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.h	2017-12-14 06:39:58.402903558 +0100
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMMAND_TABLE_HELPER_DCE112_H__
-+#define __DAL_COMMAND_TABLE_HELPER_DCE112_H__
-+
-+struct command_table_helper;
-+
-+/* Initialize command table helper functions */
-+const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table(void);
-+
-+#endif /* __DAL_COMMAND_TABLE_HELPER_DCE110_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c.0130~	2017-12-14 06:39:58.402903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c	2017-12-14 06:39:58.402903558 +0100
-@@ -0,0 +1,354 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "atom.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/grph_object_defs.h"
-+#include "include/bios_parser_types.h"
-+
-+#include "../command_table_helper.h"
-+
-+static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
-+{
-+	uint8_t atom_action = 0;
-+
-+	switch (action) {
-+	case ENCODER_CONTROL_ENABLE:
-+		atom_action = ATOM_ENABLE;
-+		break;
-+	case ENCODER_CONTROL_DISABLE:
-+		atom_action = ATOM_DISABLE;
-+		break;
-+	case ENCODER_CONTROL_SETUP:
-+		atom_action = ATOM_ENCODER_CMD_SETUP;
-+		break;
-+	case ENCODER_CONTROL_INIT:
-+		atom_action = ATOM_ENCODER_INIT;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
-+		break;
-+	}
-+
-+	return atom_action;
-+}
-+
-+static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
-+{
-+	bool result = false;
-+
-+	if (atom_engine_id != NULL)
-+		switch (id) {
-+		case ENGINE_ID_DIGA:
-+			*atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGB:
-+			*atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGC:
-+			*atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGD:
-+			*atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGE:
-+			*atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGF:
-+			*atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGG:
-+			*atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
-+			result = true;
-+			break;
-+		case ENGINE_ID_DACA:
-+			*atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
-+			result = true;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static bool clock_source_id_to_atom(
-+	enum clock_source_id id,
-+	uint32_t *atom_pll_id)
-+{
-+	bool result = true;
-+
-+	if (atom_pll_id != NULL)
-+		switch (id) {
-+		case CLOCK_SOURCE_ID_PLL0:
-+			*atom_pll_id = ATOM_PPLL0;
-+			break;
-+		case CLOCK_SOURCE_ID_PLL1:
-+			*atom_pll_id = ATOM_PPLL1;
-+			break;
-+		case CLOCK_SOURCE_ID_PLL2:
-+			*atom_pll_id = ATOM_PPLL2;
-+			break;
-+		case CLOCK_SOURCE_ID_EXTERNAL:
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			break;
-+		case CLOCK_SOURCE_ID_DFS:
-+			*atom_pll_id = ATOM_EXT_PLL1;
-+			break;
-+		case CLOCK_SOURCE_ID_VCE:
-+			/* for VCE encoding,
-+			 * we need to pass in ATOM_PPLL_INVALID
-+			 */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			break;
-+		case CLOCK_SOURCE_ID_DP_DTO:
-+			/* When programming DP DTO PLL ID should be invalid */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			break;
-+		case CLOCK_SOURCE_ID_UNDEFINED:
-+			BREAK_TO_DEBUGGER(); /* check when this will happen! */
-+			*atom_pll_id = ATOM_PPLL_INVALID;
-+			result = false;
-+			break;
-+		default:
-+			result = false;
-+			break;
-+		}
-+
-+	return result;
-+}
-+
-+static uint8_t clock_source_id_to_atom_phy_clk_src_id(
-+		enum clock_source_id id)
-+{
-+	uint8_t atom_phy_clk_src_id = 0;
-+
-+	switch (id) {
-+	case CLOCK_SOURCE_ID_PLL0:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL1:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_PLL2:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
-+		break;
-+	case CLOCK_SOURCE_ID_EXTERNAL:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
-+		break;
-+	default:
-+		atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
-+		break;
-+	}
-+
-+	return atom_phy_clk_src_id >> 2;
-+}
-+
-+static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
-+{
-+	uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
-+
-+	switch (s) {
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_EDP:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
-+		break;
-+	case SIGNAL_TYPE_LVDS:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
-+		break;
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
-+		break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
-+		break;
-+	default:
-+		atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
-+		break;
-+	}
-+
-+	return atom_dig_mode;
-+}
-+
-+static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
-+{
-+	uint8_t atom_hpd_sel = 0;
-+
-+	switch (id) {
-+	case HPD_SOURCEID1:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
-+		break;
-+	case HPD_SOURCEID2:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
-+		break;
-+	case HPD_SOURCEID3:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
-+		break;
-+	case HPD_SOURCEID4:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
-+		break;
-+	case HPD_SOURCEID5:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
-+		break;
-+	case HPD_SOURCEID6:
-+		atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL;
-+		break;
-+	case HPD_SOURCEID_UNKNOWN:
-+	default:
-+		atom_hpd_sel = 0;
-+		break;
-+	}
-+	return atom_hpd_sel >> 4;
-+}
-+
-+static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
-+{
-+	uint8_t atom_dig_encoder_sel = 0;
-+
-+	switch (id) {
-+	case ENGINE_ID_DIGA:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
-+		break;
-+	case ENGINE_ID_DIGB:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
-+		break;
-+	case ENGINE_ID_DIGC:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
-+		break;
-+	case ENGINE_ID_DIGD:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
-+		break;
-+	case ENGINE_ID_DIGE:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
-+		break;
-+	case ENGINE_ID_DIGF:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
-+		break;
-+	case ENGINE_ID_DIGG:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
-+		break;
-+	default:
-+		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
-+		break;
-+	}
-+
-+	return atom_dig_encoder_sel;
-+}
-+
-+static uint8_t phy_id_to_atom(enum transmitter t)
-+{
-+	uint8_t atom_phy_id;
-+
-+	switch (t) {
-+	case TRANSMITTER_UNIPHY_A:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
-+		break;
-+	case TRANSMITTER_UNIPHY_B:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYB;
-+		break;
-+	case TRANSMITTER_UNIPHY_C:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYC;
-+		break;
-+	case TRANSMITTER_UNIPHY_D:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYD;
-+		break;
-+	case TRANSMITTER_UNIPHY_E:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYE;
-+		break;
-+	case TRANSMITTER_UNIPHY_F:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYF;
-+		break;
-+	case TRANSMITTER_UNIPHY_G:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYG;
-+		break;
-+	default:
-+		atom_phy_id = ATOM_PHY_ID_UNIPHYA;
-+		break;
-+	}
-+	return atom_phy_id;
-+}
-+
-+static uint8_t disp_power_gating_action_to_atom(
-+	enum bp_pipe_control_action action)
-+{
-+	uint8_t atom_pipe_action = 0;
-+
-+	switch (action) {
-+	case ASIC_PIPE_DISABLE:
-+		atom_pipe_action = ATOM_DISABLE;
-+		break;
-+	case ASIC_PIPE_ENABLE:
-+		atom_pipe_action = ATOM_ENABLE;
-+		break;
-+	case ASIC_PIPE_INIT:
-+		atom_pipe_action = ATOM_INIT;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER(); /* Unhandle action in driver! */
-+		break;
-+	}
-+
-+	return atom_pipe_action;
-+}
-+
-+static const struct command_table_helper command_table_helper_funcs = {
-+	.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
-+	.encoder_action_to_atom = encoder_action_to_atom,
-+	.engine_bp_to_atom = engine_bp_to_atom,
-+	.clock_source_id_to_atom = clock_source_id_to_atom,
-+	.clock_source_id_to_atom_phy_clk_src_id =
-+		clock_source_id_to_atom_phy_clk_src_id,
-+	.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
-+	.hpd_sel_to_atom = hpd_sel_to_atom,
-+	.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
-+	.phy_id_to_atom = phy_id_to_atom,
-+	.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
-+	.assign_control_parameter =
-+		dal_cmd_table_helper_assign_control_parameter,
-+	.clock_source_id_to_ref_clk_src =
-+		dal_cmd_table_helper_clock_source_id_to_ref_clk_src,
-+	.transmitter_bp_to_atom = dal_cmd_table_helper_transmitter_bp_to_atom,
-+	.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
-+	.encoder_mode_bp_to_atom =
-+		dal_cmd_table_helper_encoder_mode_bp_to_atom,
-+};
-+
-+const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void)
-+{
-+	return &command_table_helper_funcs;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.h.0130~	2017-12-14 06:39:58.402903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.h	2017-12-14 06:39:58.402903558 +0100
-@@ -0,0 +1,33 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMMAND_TABLE_HELPER_DCE80_H__
-+#define __DAL_COMMAND_TABLE_HELPER_DCE80_H__
-+
-+struct command_table_helper;
-+
-+const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/bios/Makefile.0130~	2017-12-14 06:39:58.402903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/bios/Makefile	2017-12-14 06:39:58.402903558 +0100
-@@ -0,0 +1,27 @@
-+#
-+# Makefile for the 'bios' sub-component of DAL.
-+# It provides the parsing and executing controls for atom bios image.
-+
-+BIOS = bios_parser.o bios_parser_interface.o  bios_parser_helper.o command_table.o command_table_helper.o bios_parser_common.o
-+
-+BIOS += command_table2.o command_table_helper2.o bios_parser2.o
-+
-+AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_BIOS)
-+
-+###############################################################################
-+# DCE 8x
-+###############################################################################
-+# All DCE8.x are derived from DCE8.0, so 8.0 MUST be defined if ANY of
-+# DCE8.x is compiled.
-+AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce80/command_table_helper_dce80.o
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o
-+
-+AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper_dce112.o
-+
-+AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper2_dce112.o
---- linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c.0130~	2017-12-14 06:39:58.402903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c	2017-12-14 06:39:58.402903558 +0100
-@@ -0,0 +1,191 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dm_services.h"
-+#include "bw_fixed.h"
-+
-+
-+#define MIN_I64 \
-+	(int64_t)(-(1LL << 63))
-+
-+#define MAX_I64 \
-+	(int64_t)((1ULL << 63) - 1)
-+
-+#define FRACTIONAL_PART_MASK \
-+	((1ULL << BW_FIXED_BITS_PER_FRACTIONAL_PART) - 1)
-+
-+#define GET_FRACTIONAL_PART(x) \
-+	(FRACTIONAL_PART_MASK & (x))
-+
-+static uint64_t abs_i64(int64_t arg)
-+{
-+	if (arg >= 0)
-+		return (uint64_t)(arg);
-+	else
-+		return (uint64_t)(-arg);
-+}
-+
-+struct bw_fixed bw_int_to_fixed_nonconst(int64_t value)
-+{
-+	struct bw_fixed res;
-+	ASSERT(value < BW_FIXED_MAX_I32 && value > BW_FIXED_MIN_I32);
-+	res.value = value << BW_FIXED_BITS_PER_FRACTIONAL_PART;
-+	return res;
-+}
-+
-+struct bw_fixed bw_frc_to_fixed(int64_t numerator, int64_t denominator)
-+{
-+	struct bw_fixed res;
-+	bool arg1_negative = numerator < 0;
-+	bool arg2_negative = denominator < 0;
-+	uint64_t arg1_value;
-+	uint64_t arg2_value;
-+	uint64_t remainder;
-+
-+	/* determine integer part */
-+	uint64_t res_value;
-+
-+	ASSERT(denominator != 0);
-+
-+	arg1_value = abs_i64(numerator);
-+	arg2_value = abs_i64(denominator);
-+	res_value = div64_u64_rem(arg1_value, arg2_value, &remainder);
-+
-+	ASSERT(res_value <= BW_FIXED_MAX_I32);
-+
-+	/* determine fractional part */
-+	{
-+		uint32_t i = BW_FIXED_BITS_PER_FRACTIONAL_PART;
-+
-+		do
-+		{
-+			remainder <<= 1;
-+
-+			res_value <<= 1;
-+
-+			if (remainder >= arg2_value)
-+			{
-+				res_value |= 1;
-+				remainder -= arg2_value;
-+			}
-+		} while (--i != 0);
-+	}
-+
-+	/* round up LSB */
-+	{
-+		uint64_t summand = (remainder << 1) >= arg2_value;
-+
-+		ASSERT(res_value <= MAX_I64 - summand);
-+
-+		res_value += summand;
-+	}
-+
-+	res.value = (int64_t)(res_value);
-+
-+	if (arg1_negative ^ arg2_negative)
-+		res.value = -res.value;
-+	return res;
-+}
-+
-+struct bw_fixed bw_floor2(
-+	const struct bw_fixed arg,
-+	const struct bw_fixed significance)
-+{
-+	struct bw_fixed result;
-+	int64_t multiplicand;
-+
-+	multiplicand = div64_s64(arg.value, abs_i64(significance.value));
-+	result.value = abs_i64(significance.value) * multiplicand;
-+	ASSERT(abs_i64(result.value) <= abs_i64(arg.value));
-+	return result;
-+}
-+
-+struct bw_fixed bw_ceil2(
-+	const struct bw_fixed arg,
-+	const struct bw_fixed significance)
-+{
-+	struct bw_fixed result;
-+	int64_t multiplicand;
-+
-+	multiplicand = div64_s64(arg.value, abs_i64(significance.value));
-+	result.value = abs_i64(significance.value) * multiplicand;
-+	if (abs_i64(result.value) < abs_i64(arg.value)) {
-+		if (arg.value < 0)
-+			result.value -= abs_i64(significance.value);
-+		else
-+			result.value += abs_i64(significance.value);
-+	}
-+	return result;
-+}
-+
-+struct bw_fixed bw_mul(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	struct bw_fixed res;
-+
-+	bool arg1_negative = arg1.value < 0;
-+	bool arg2_negative = arg2.value < 0;
-+
-+	uint64_t arg1_value = abs_i64(arg1.value);
-+	uint64_t arg2_value = abs_i64(arg2.value);
-+
-+	uint64_t arg1_int = BW_FIXED_GET_INTEGER_PART(arg1_value);
-+	uint64_t arg2_int = BW_FIXED_GET_INTEGER_PART(arg2_value);
-+
-+	uint64_t arg1_fra = GET_FRACTIONAL_PART(arg1_value);
-+	uint64_t arg2_fra = GET_FRACTIONAL_PART(arg2_value);
-+
-+	uint64_t tmp;
-+
-+	res.value = arg1_int * arg2_int;
-+
-+	ASSERT(res.value <= BW_FIXED_MAX_I32);
-+
-+	res.value <<= BW_FIXED_BITS_PER_FRACTIONAL_PART;
-+
-+	tmp = arg1_int * arg2_fra;
-+
-+	ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
-+
-+	res.value += tmp;
-+
-+	tmp = arg2_int * arg1_fra;
-+
-+	ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
-+
-+	res.value += tmp;
-+
-+	tmp = arg1_fra * arg2_fra;
-+
-+	tmp = (tmp >> BW_FIXED_BITS_PER_FRACTIONAL_PART) +
-+		(tmp >= (uint64_t)(bw_frc_to_fixed(1, 2).value));
-+
-+	ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));
-+
-+	res.value += tmp;
-+
-+	if (arg1_negative ^ arg2_negative)
-+		res.value = -res.value;
-+	return res;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/custom_float.c.0130~	2017-12-14 06:39:58.402903558 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/custom_float.c	2017-12-14 06:39:58.402903558 +0100
-@@ -0,0 +1,197 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dm_services.h"
-+#include "custom_float.h"
-+
-+
-+static bool build_custom_float(
-+	struct fixed31_32 value,
-+	const struct custom_float_format *format,
-+	bool *negative,
-+	uint32_t *mantissa,
-+	uint32_t *exponenta)
-+{
-+	uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1;
-+
-+	const struct fixed31_32 mantissa_constant_plus_max_fraction =
-+		dal_fixed31_32_from_fraction(
-+			(1LL << (format->mantissa_bits + 1)) - 1,
-+			1LL << format->mantissa_bits);
-+
-+	struct fixed31_32 mantiss;
-+
-+	if (dal_fixed31_32_eq(
-+		value,
-+		dal_fixed31_32_zero)) {
-+		*negative = false;
-+		*mantissa = 0;
-+		*exponenta = 0;
-+		return true;
-+	}
-+
-+	if (dal_fixed31_32_lt(
-+		value,
-+		dal_fixed31_32_zero)) {
-+		*negative = format->sign;
-+		value = dal_fixed31_32_neg(value);
-+	} else {
-+		*negative = false;
-+	}
-+
-+	if (dal_fixed31_32_lt(
-+		value,
-+		dal_fixed31_32_one)) {
-+		uint32_t i = 1;
-+
-+		do {
-+			value = dal_fixed31_32_shl(value, 1);
-+			++i;
-+		} while (dal_fixed31_32_lt(
-+			value,
-+			dal_fixed31_32_one));
-+
-+		--i;
-+
-+		if (exp_offset <= i) {
-+			*mantissa = 0;
-+			*exponenta = 0;
-+			return true;
-+		}
-+
-+		*exponenta = exp_offset - i;
-+	} else if (dal_fixed31_32_le(
-+		mantissa_constant_plus_max_fraction,
-+		value)) {
-+		uint32_t i = 1;
-+
-+		do {
-+			value = dal_fixed31_32_shr(value, 1);
-+			++i;
-+		} while (dal_fixed31_32_lt(
-+			mantissa_constant_plus_max_fraction,
-+			value));
-+
-+		*exponenta = exp_offset + i - 1;
-+	} else {
-+		*exponenta = exp_offset;
-+	}
-+
-+	mantiss = dal_fixed31_32_sub(
-+		value,
-+		dal_fixed31_32_one);
-+
-+	if (dal_fixed31_32_lt(
-+			mantiss,
-+			dal_fixed31_32_zero) ||
-+		dal_fixed31_32_lt(
-+			dal_fixed31_32_one,
-+			mantiss))
-+		mantiss = dal_fixed31_32_zero;
-+	else
-+		mantiss = dal_fixed31_32_shl(
-+			mantiss,
-+			format->mantissa_bits);
-+
-+	*mantissa = dal_fixed31_32_floor(mantiss);
-+
-+	return true;
-+}
-+
-+static bool setup_custom_float(
-+	const struct custom_float_format *format,
-+	bool negative,
-+	uint32_t mantissa,
-+	uint32_t exponenta,
-+	uint32_t *result)
-+{
-+	uint32_t i = 0;
-+	uint32_t j = 0;
-+
-+	uint32_t value = 0;
-+
-+	/* verification code:
-+	 * once calculation is ok we can remove it
-+	 */
-+
-+	const uint32_t mantissa_mask =
-+		(1 << (format->mantissa_bits + 1)) - 1;
-+
-+	const uint32_t exponenta_mask =
-+		(1 << (format->exponenta_bits + 1)) - 1;
-+
-+	if (mantissa & ~mantissa_mask) {
-+		BREAK_TO_DEBUGGER();
-+		mantissa = mantissa_mask;
-+	}
-+
-+	if (exponenta & ~exponenta_mask) {
-+		BREAK_TO_DEBUGGER();
-+		exponenta = exponenta_mask;
-+	}
-+
-+	/* end of verification code */
-+
-+	while (i < format->mantissa_bits) {
-+		uint32_t mask = 1 << i;
-+
-+		if (mantissa & mask)
-+			value |= mask;
-+
-+		++i;
-+	}
-+
-+	while (j < format->exponenta_bits) {
-+		uint32_t mask = 1 << j;
-+
-+		if (exponenta & mask)
-+			value |= mask << i;
-+
-+		++j;
-+	}
-+
-+	if (negative && format->sign)
-+		value |= 1 << (i + j);
-+
-+	*result = value;
-+
-+	return true;
-+}
-+
-+bool convert_to_custom_float_format(
-+	struct fixed31_32 value,
-+	const struct custom_float_format *format,
-+	uint32_t *result)
-+{
-+	uint32_t mantissa;
-+	uint32_t exponenta;
-+	bool negative;
-+
-+	return build_custom_float(
-+		value, format, &negative, &mantissa, &exponenta) &&
-+	setup_custom_float(
-+		format, negative, mantissa, exponenta, result);
-+}
-+
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c.0130~	2017-12-14 06:39:58.403903559 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c	2017-12-14 06:39:58.403903559 +0100
-@@ -0,0 +1,3257 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dce_calcs.h"
-+#include "dc.h"
-+#include "core_types.h"
-+#include "dal_asic_id.h"
-+
-+/*******************************************************************************
-+ * Private Functions
-+ ******************************************************************************/
-+
-+static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asic_id)
-+{
-+	switch (asic_id.chip_family) {
-+
-+	case FAMILY_CZ:
-+		if (ASIC_REV_IS_STONEY(asic_id.hw_internal_rev))
-+			return BW_CALCS_VERSION_STONEY;
-+		return BW_CALCS_VERSION_CARRIZO;
-+
-+	case FAMILY_VI:
-+		if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))
-+			return BW_CALCS_VERSION_POLARIS10;
-+		if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
-+				ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
-+			return BW_CALCS_VERSION_POLARIS11;
-+		return BW_CALCS_VERSION_INVALID;
-+
-+	case FAMILY_AI:
-+		return BW_CALCS_VERSION_VEGA10;
-+
-+	default:
-+		return BW_CALCS_VERSION_INVALID;
-+	}
-+}
-+
-+static void calculate_bandwidth(
-+	const struct bw_calcs_dceip *dceip,
-+	const struct bw_calcs_vbios *vbios,
-+	struct bw_calcs_data *data)
-+
-+{
-+	const int32_t pixels_per_chunk = 512;
-+	const int32_t high = 2;
-+	const int32_t mid = 1;
-+	const int32_t low = 0;
-+	const uint32_t s_low = 0;
-+	const uint32_t s_mid1 = 1;
-+	const uint32_t s_mid2 = 2;
-+	const uint32_t s_mid3 = 3;
-+	const uint32_t s_mid4 = 4;
-+	const uint32_t s_mid5 = 5;
-+	const uint32_t s_mid6 = 6;
-+	const uint32_t s_high = 7;
-+	const uint32_t bus_efficiency = 1;
-+	const uint32_t dmif_chunk_buff_margin = 1;
-+
-+	uint32_t max_chunks_fbc_mode;
-+	int32_t num_cursor_lines;
-+
-+	int32_t i, j, k;
-+	struct bw_fixed yclk[3];
-+	struct bw_fixed sclk[8];
-+	bool d0_underlay_enable;
-+	bool d1_underlay_enable;
-+	bool fbc_enabled;
-+	bool lpt_enabled;
-+	enum bw_defines sclk_message;
-+	enum bw_defines yclk_message;
-+	enum bw_defines v_filter_init_mode[maximum_number_of_surfaces];
-+	enum bw_defines tiling_mode[maximum_number_of_surfaces];
-+	enum bw_defines surface_type[maximum_number_of_surfaces];
-+	enum bw_defines voltage;
-+	enum bw_defines pipe_check;
-+	enum bw_defines hsr_check;
-+	enum bw_defines vsr_check;
-+	enum bw_defines lb_size_check;
-+	enum bw_defines fbc_check;
-+	enum bw_defines rotation_check;
-+	enum bw_defines mode_check;
-+	enum bw_defines nbp_state_change_enable_blank;
-+	/*initialize variables*/
-+	int32_t number_of_displays_enabled = 0;
-+	int32_t number_of_displays_enabled_with_margin = 0;
-+	int32_t number_of_aligned_displays_with_no_margin = 0;
-+
-+	yclk[low] = vbios->low_yclk;
-+	yclk[mid] = vbios->mid_yclk;
-+	yclk[high] = vbios->high_yclk;
-+	sclk[s_low] = vbios->low_sclk;
-+	sclk[s_mid1] = vbios->mid1_sclk;
-+	sclk[s_mid2] = vbios->mid2_sclk;
-+	sclk[s_mid3] = vbios->mid3_sclk;
-+	sclk[s_mid4] = vbios->mid4_sclk;
-+	sclk[s_mid5] = vbios->mid5_sclk;
-+	sclk[s_mid6] = vbios->mid6_sclk;
-+	sclk[s_high] = vbios->high_sclk;
-+	/*''''''''''''''''''*/
-+	/* surface assignment:*/
-+	/* 0: d0 underlay or underlay luma*/
-+	/* 1: d0 underlay chroma*/
-+	/* 2: d1 underlay or underlay luma*/
-+	/* 3: d1 underlay chroma*/
-+	/* 4: d0 graphics*/
-+	/* 5: d1 graphics*/
-+	/* 6: d2 graphics*/
-+	/* 7: d3 graphics, same mode as d2*/
-+	/* 8: d4 graphics, same mode as d2*/
-+	/* 9: d5 graphics, same mode as d2*/
-+	/* ...*/
-+	/* maximum_number_of_surfaces-2: d1 display_write_back420 luma*/
-+	/* maximum_number_of_surfaces-1: d1 display_write_back420 chroma*/
-+	/* underlay luma and chroma surface parameters from spreadsheet*/
-+
-+
-+
-+
-+	if (data->d0_underlay_mode == bw_def_none) { d0_underlay_enable = 0; }
-+	else {
-+		d0_underlay_enable = 1;
-+	}
-+	if (data->d1_underlay_mode == bw_def_none) { d1_underlay_enable = 0; }
-+	else {
-+		d1_underlay_enable = 1;
-+	}
-+	data->number_of_underlay_surfaces = d0_underlay_enable + d1_underlay_enable;
-+	switch (data->underlay_surface_type) {
-+	case bw_def_420:
-+		surface_type[0] = bw_def_underlay420_luma;
-+		surface_type[2] = bw_def_underlay420_luma;
-+		data->bytes_per_pixel[0] = 1;
-+		data->bytes_per_pixel[2] = 1;
-+		surface_type[1] = bw_def_underlay420_chroma;
-+		surface_type[3] = bw_def_underlay420_chroma;
-+		data->bytes_per_pixel[1] = 2;
-+		data->bytes_per_pixel[3] = 2;
-+		data->lb_size_per_component[0] = dceip->underlay420_luma_lb_size_per_component;
-+		data->lb_size_per_component[1] = dceip->underlay420_chroma_lb_size_per_component;
-+		data->lb_size_per_component[2] = dceip->underlay420_luma_lb_size_per_component;
-+		data->lb_size_per_component[3] = dceip->underlay420_chroma_lb_size_per_component;
-+		break;
-+	case bw_def_422:
-+		surface_type[0] = bw_def_underlay422;
-+		surface_type[2] = bw_def_underlay422;
-+		data->bytes_per_pixel[0] = 2;
-+		data->bytes_per_pixel[2] = 2;
-+		data->lb_size_per_component[0] = dceip->underlay422_lb_size_per_component;
-+		data->lb_size_per_component[2] = dceip->underlay422_lb_size_per_component;
-+		break;
-+	default:
-+		surface_type[0] = bw_def_underlay444;
-+		surface_type[2] = bw_def_underlay444;
-+		data->bytes_per_pixel[0] = 4;
-+		data->bytes_per_pixel[2] = 4;
-+		data->lb_size_per_component[0] = dceip->lb_size_per_component444;
-+		data->lb_size_per_component[2] = dceip->lb_size_per_component444;
-+		break;
-+	}
-+	if (d0_underlay_enable) {
-+		switch (data->underlay_surface_type) {
-+		case bw_def_420:
-+			data->enable[0] = 1;
-+			data->enable[1] = 1;
-+			break;
-+		default:
-+			data->enable[0] = 1;
-+			data->enable[1] = 0;
-+			break;
-+		}
-+	}
-+	else {
-+		data->enable[0] = 0;
-+		data->enable[1] = 0;
-+	}
-+	if (d1_underlay_enable) {
-+		switch (data->underlay_surface_type) {
-+		case bw_def_420:
-+			data->enable[2] = 1;
-+			data->enable[3] = 1;
-+			break;
-+		default:
-+			data->enable[2] = 1;
-+			data->enable[3] = 0;
-+			break;
-+		}
-+	}
-+	else {
-+		data->enable[2] = 0;
-+		data->enable[3] = 0;
-+	}
-+	data->use_alpha[0] = 0;
-+	data->use_alpha[1] = 0;
-+	data->use_alpha[2] = 0;
-+	data->use_alpha[3] = 0;
-+	data->scatter_gather_enable_for_pipe[0] = vbios->scatter_gather_enable;
-+	data->scatter_gather_enable_for_pipe[1] = vbios->scatter_gather_enable;
-+	data->scatter_gather_enable_for_pipe[2] = vbios->scatter_gather_enable;
-+	data->scatter_gather_enable_for_pipe[3] = vbios->scatter_gather_enable;
-+	/*underlay0 same and graphics display pipe0*/
-+	data->interlace_mode[0] = data->interlace_mode[4];
-+	data->interlace_mode[1] = data->interlace_mode[4];
-+	/*underlay1 same and graphics display pipe1*/
-+	data->interlace_mode[2] = data->interlace_mode[5];
-+	data->interlace_mode[3] = data->interlace_mode[5];
-+	/*underlay0 same and graphics display pipe0*/
-+	data->h_total[0] = data->h_total[4];
-+	data->v_total[0] = data->v_total[4];
-+	data->h_total[1] = data->h_total[4];
-+	data->v_total[1] = data->v_total[4];
-+	/*underlay1 same and graphics display pipe1*/
-+	data->h_total[2] = data->h_total[5];
-+	data->v_total[2] = data->v_total[5];
-+	data->h_total[3] = data->h_total[5];
-+	data->v_total[3] = data->v_total[5];
-+	/*underlay0 same and graphics display pipe0*/
-+	data->pixel_rate[0] = data->pixel_rate[4];
-+	data->pixel_rate[1] = data->pixel_rate[4];
-+	/*underlay1 same and graphics display pipe1*/
-+	data->pixel_rate[2] = data->pixel_rate[5];
-+	data->pixel_rate[3] = data->pixel_rate[5];
-+	if ((data->underlay_tiling_mode == bw_def_array_linear_general || data->underlay_tiling_mode == bw_def_array_linear_aligned)) {
-+		tiling_mode[0] = bw_def_linear;
-+		tiling_mode[1] = bw_def_linear;
-+		tiling_mode[2] = bw_def_linear;
-+		tiling_mode[3] = bw_def_linear;
-+	}
-+	else {
-+		tiling_mode[0] = bw_def_landscape;
-+		tiling_mode[1] = bw_def_landscape;
-+		tiling_mode[2] = bw_def_landscape;
-+		tiling_mode[3] = bw_def_landscape;
-+	}
-+	data->lb_bpc[0] = data->underlay_lb_bpc;
-+	data->lb_bpc[1] = data->underlay_lb_bpc;
-+	data->lb_bpc[2] = data->underlay_lb_bpc;
-+	data->lb_bpc[3] = data->underlay_lb_bpc;
-+	data->compression_rate[0] = bw_int_to_fixed(1);
-+	data->compression_rate[1] = bw_int_to_fixed(1);
-+	data->compression_rate[2] = bw_int_to_fixed(1);
-+	data->compression_rate[3] = bw_int_to_fixed(1);
-+	data->access_one_channel_only[0] = 0;
-+	data->access_one_channel_only[1] = 0;
-+	data->access_one_channel_only[2] = 0;
-+	data->access_one_channel_only[3] = 0;
-+	data->cursor_width_pixels[0] = bw_int_to_fixed(0);
-+	data->cursor_width_pixels[1] = bw_int_to_fixed(0);
-+	data->cursor_width_pixels[2] = bw_int_to_fixed(0);
-+	data->cursor_width_pixels[3] = bw_int_to_fixed(0);
-+	/* graphics surface parameters from spreadsheet*/
-+	fbc_enabled = 0;
-+	lpt_enabled = 0;
-+	for (i = 4; i <= maximum_number_of_surfaces - 3; i++) {
-+		if (i < data->number_of_displays + 4) {
-+			if (i == 4 && data->d0_underlay_mode == bw_def_underlay_only) {
-+				data->enable[i] = 0;
-+				data->use_alpha[i] = 0;
-+			}
-+			else if (i == 4 && data->d0_underlay_mode == bw_def_blend) {
-+				data->enable[i] = 1;
-+				data->use_alpha[i] = 1;
-+			}
-+			else if (i == 4) {
-+				data->enable[i] = 1;
-+				data->use_alpha[i] = 0;
-+			}
-+			else if (i == 5 && data->d1_underlay_mode == bw_def_underlay_only) {
-+				data->enable[i] = 0;
-+				data->use_alpha[i] = 0;
-+			}
-+			else if (i == 5 && data->d1_underlay_mode == bw_def_blend) {
-+				data->enable[i] = 1;
-+				data->use_alpha[i] = 1;
-+			}
-+			else {
-+				data->enable[i] = 1;
-+				data->use_alpha[i] = 0;
-+			}
-+		}
-+		else {
-+			data->enable[i] = 0;
-+			data->use_alpha[i] = 0;
-+		}
-+		data->scatter_gather_enable_for_pipe[i] = vbios->scatter_gather_enable;
-+		surface_type[i] = bw_def_graphics;
-+		data->lb_size_per_component[i] = dceip->lb_size_per_component444;
-+		if (data->graphics_tiling_mode == bw_def_array_linear_general || data->graphics_tiling_mode == bw_def_array_linear_aligned) {
-+			tiling_mode[i] = bw_def_linear;
-+		}
-+		else {
-+			tiling_mode[i] = bw_def_tiled;
-+		}
-+		data->lb_bpc[i] = data->graphics_lb_bpc;
-+		if ((data->fbc_en[i] == 1 && (dceip->argb_compression_support || data->d0_underlay_mode != bw_def_blended))) {
-+			data->compression_rate[i] = bw_int_to_fixed(vbios->average_compression_rate);
-+			data->access_one_channel_only[i] = data->lpt_en[i];
-+		}
-+		else {
-+			data->compression_rate[i] = bw_int_to_fixed(1);
-+			data->access_one_channel_only[i] = 0;
-+		}
-+		if (data->fbc_en[i] == 1) {
-+			fbc_enabled = 1;
-+			if (data->lpt_en[i] == 1) {
-+				lpt_enabled = 1;
-+			}
-+		}
-+		data->cursor_width_pixels[i] = bw_int_to_fixed(vbios->cursor_width);
-+	}
-+	/* display_write_back420*/
-+	data->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 2] = 0;
-+	data->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 1] = 0;
-+	if (data->d1_display_write_back_dwb_enable == 1) {
-+		data->enable[maximum_number_of_surfaces - 2] = 1;
-+		data->enable[maximum_number_of_surfaces - 1] = 1;
-+	}
-+	else {
-+		data->enable[maximum_number_of_surfaces - 2] = 0;
-+		data->enable[maximum_number_of_surfaces - 1] = 0;
-+	}
-+	surface_type[maximum_number_of_surfaces - 2] = bw_def_display_write_back420_luma;
-+	surface_type[maximum_number_of_surfaces - 1] = bw_def_display_write_back420_chroma;
-+	data->lb_size_per_component[maximum_number_of_surfaces - 2] = dceip->underlay420_luma_lb_size_per_component;
-+	data->lb_size_per_component[maximum_number_of_surfaces - 1] = dceip->underlay420_chroma_lb_size_per_component;
-+	data->bytes_per_pixel[maximum_number_of_surfaces - 2] = 1;
-+	data->bytes_per_pixel[maximum_number_of_surfaces - 1] = 2;
-+	data->interlace_mode[maximum_number_of_surfaces - 2] = data->interlace_mode[5];
-+	data->interlace_mode[maximum_number_of_surfaces - 1] = data->interlace_mode[5];
-+	data->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
-+	data->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
-+	data->v_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
-+	data->v_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
-+	data->rotation_angle[maximum_number_of_surfaces - 2] = bw_int_to_fixed(0);
-+	data->rotation_angle[maximum_number_of_surfaces - 1] = bw_int_to_fixed(0);
-+	tiling_mode[maximum_number_of_surfaces - 2] = bw_def_linear;
-+	tiling_mode[maximum_number_of_surfaces - 1] = bw_def_linear;
-+	data->lb_bpc[maximum_number_of_surfaces - 2] = 8;
-+	data->lb_bpc[maximum_number_of_surfaces - 1] = 8;
-+	data->compression_rate[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
-+	data->compression_rate[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
-+	data->access_one_channel_only[maximum_number_of_surfaces - 2] = 0;
-+	data->access_one_channel_only[maximum_number_of_surfaces - 1] = 0;
-+	/*assume display pipe1 has dwb enabled*/
-+	data->h_total[maximum_number_of_surfaces - 2] = data->h_total[5];
-+	data->h_total[maximum_number_of_surfaces - 1] = data->h_total[5];
-+	data->v_total[maximum_number_of_surfaces - 2] = data->v_total[5];
-+	data->v_total[maximum_number_of_surfaces - 1] = data->v_total[5];
-+	data->pixel_rate[maximum_number_of_surfaces - 2] = data->pixel_rate[5];
-+	data->pixel_rate[maximum_number_of_surfaces - 1] = data->pixel_rate[5];
-+	data->src_width[maximum_number_of_surfaces - 2] = data->src_width[5];
-+	data->src_width[maximum_number_of_surfaces - 1] = data->src_width[5];
-+	data->src_height[maximum_number_of_surfaces - 2] = data->src_height[5];
-+	data->src_height[maximum_number_of_surfaces - 1] = data->src_height[5];
-+	data->pitch_in_pixels[maximum_number_of_surfaces - 2] = data->src_width[5];
-+	data->pitch_in_pixels[maximum_number_of_surfaces - 1] = data->src_width[5];
-+	data->h_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
-+	data->h_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
-+	data->v_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
-+	data->v_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
-+	data->stereo_mode[maximum_number_of_surfaces - 2] = bw_def_mono;
-+	data->stereo_mode[maximum_number_of_surfaces - 1] = bw_def_mono;
-+	data->cursor_width_pixels[maximum_number_of_surfaces - 2] = bw_int_to_fixed(0);
-+	data->cursor_width_pixels[maximum_number_of_surfaces - 1] = bw_int_to_fixed(0);
-+	data->use_alpha[maximum_number_of_surfaces - 2] = 0;
-+	data->use_alpha[maximum_number_of_surfaces - 1] = 0;
-+	/*mode check calculations:*/
-+	/* mode within dce ip capabilities*/
-+	/* fbc*/
-+	/* hsr*/
-+	/* vsr*/
-+	/* lb size*/
-+	/*effective scaling source and ratios:*/
-+	/*for graphics, non-stereo, non-interlace surfaces when the size of the source and destination are the same, only one tap is used*/
-+	/*420 chroma has half the width, height, horizontal and vertical scaling ratios than luma*/
-+	/*rotating a graphic or underlay surface swaps the width, height, horizontal and vertical scaling ratios*/
-+	/*in top-bottom stereo mode there is 2:1 vertical downscaling for each eye*/
-+	/*in side-by-side stereo mode there is 2:1 horizontal downscaling for each eye*/
-+	/*in interlace mode there is 2:1 vertical downscaling for each field*/
-+	/*in panning or bezel adjustment mode the source width has an extra 128 pixels*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (bw_equ(data->h_scale_ratio[i], bw_int_to_fixed(1)) && bw_equ(data->v_scale_ratio[i], bw_int_to_fixed(1)) && surface_type[i] == bw_def_graphics && data->stereo_mode[i] == bw_def_mono && data->interlace_mode[i] == 0) {
-+				data->h_taps[i] = bw_int_to_fixed(1);
-+				data->v_taps[i] = bw_int_to_fixed(1);
-+			}
-+			if (surface_type[i] == bw_def_display_write_back420_chroma || surface_type[i] == bw_def_underlay420_chroma) {
-+				data->pitch_in_pixels_after_surface_type[i] = bw_div(data->pitch_in_pixels[i], bw_int_to_fixed(2));
-+				data->src_width_after_surface_type = bw_div(data->src_width[i], bw_int_to_fixed(2));
-+				data->src_height_after_surface_type = bw_div(data->src_height[i], bw_int_to_fixed(2));
-+				data->hsr_after_surface_type = bw_div(data->h_scale_ratio[i], bw_int_to_fixed(2));
-+				data->vsr_after_surface_type = bw_div(data->v_scale_ratio[i], bw_int_to_fixed(2));
-+			}
-+			else {
-+				data->pitch_in_pixels_after_surface_type[i] = data->pitch_in_pixels[i];
-+				data->src_width_after_surface_type = data->src_width[i];
-+				data->src_height_after_surface_type = data->src_height[i];
-+				data->hsr_after_surface_type = data->h_scale_ratio[i];
-+				data->vsr_after_surface_type = data->v_scale_ratio[i];
-+			}
-+			if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
-+				data->src_width_after_rotation = data->src_height_after_surface_type;
-+				data->src_height_after_rotation = data->src_width_after_surface_type;
-+				data->hsr_after_rotation = data->vsr_after_surface_type;
-+				data->vsr_after_rotation = data->hsr_after_surface_type;
-+			}
-+			else {
-+				data->src_width_after_rotation = data->src_width_after_surface_type;
-+				data->src_height_after_rotation = data->src_height_after_surface_type;
-+				data->hsr_after_rotation = data->hsr_after_surface_type;
-+				data->vsr_after_rotation = data->vsr_after_surface_type;
-+			}
-+			switch (data->stereo_mode[i]) {
-+			case bw_def_top_bottom:
-+				data->source_width_pixels[i] = data->src_width_after_rotation;
-+				data->source_height_pixels = bw_mul(bw_int_to_fixed(2), data->src_height_after_rotation);
-+				data->hsr_after_stereo = data->hsr_after_rotation;
-+				data->vsr_after_stereo = bw_mul(bw_int_to_fixed(1), data->vsr_after_rotation);
-+				break;
-+			case bw_def_side_by_side:
-+				data->source_width_pixels[i] = bw_mul(bw_int_to_fixed(2), data->src_width_after_rotation);
-+				data->source_height_pixels = data->src_height_after_rotation;
-+				data->hsr_after_stereo = bw_mul(bw_int_to_fixed(1), data->hsr_after_rotation);
-+				data->vsr_after_stereo = data->vsr_after_rotation;
-+				break;
-+			default:
-+				data->source_width_pixels[i] = data->src_width_after_rotation;
-+				data->source_height_pixels = data->src_height_after_rotation;
-+				data->hsr_after_stereo = data->hsr_after_rotation;
-+				data->vsr_after_stereo = data->vsr_after_rotation;
-+				break;
-+			}
-+			data->hsr[i] = data->hsr_after_stereo;
-+			if (data->interlace_mode[i]) {
-+				data->vsr[i] = bw_mul(data->vsr_after_stereo, bw_int_to_fixed(2));
-+			}
-+			else {
-+				data->vsr[i] = data->vsr_after_stereo;
-+			}
-+			if (data->panning_and_bezel_adjustment != bw_def_none) {
-+				data->source_width_rounded_up_to_chunks[i] = bw_add(bw_floor2(bw_sub(data->source_width_pixels[i], bw_int_to_fixed(1)), bw_int_to_fixed(128)), bw_int_to_fixed(256));
-+			}
-+			else {
-+				data->source_width_rounded_up_to_chunks[i] = bw_ceil2(data->source_width_pixels[i], bw_int_to_fixed(128));
-+			}
-+			data->source_height_rounded_up_to_chunks[i] = data->source_height_pixels;
-+		}
-+	}
-+	/*mode support checks:*/
-+	/*the number of graphics and underlay pipes is limited by the ip support*/
-+	/*maximum horizontal and vertical scale ratio is 4, and should not exceed the number of taps*/
-+	/*for downscaling with the pre-downscaler, the horizontal scale ratio must be more than the ceiling of one quarter of the number of taps*/
-+	/*the pre-downscaler reduces the line buffer source by the horizontal scale ratio*/
-+	/*the number of lines in the line buffer has to exceed the number of vertical taps*/
-+	/*the size of the line in the line buffer is the product of the source width and the bits per component, rounded up to a multiple of 48*/
-+	/*the size of the line in the line buffer in the case of 10 bit per component is the product of the source width rounded up to multiple of 8 and 30.023438 / 3, rounded up to a multiple of 48*/
-+	/*the size of the line in the line buffer in the case of 8 bit per component is the product of the source width rounded up to multiple of 8 and 30.023438 / 3, rounded up to a multiple of 48*/
-+	/*frame buffer compression is not supported with stereo mode, rotation, or non- 888 formats*/
-+	/*rotation is not supported with linear of stereo modes*/
-+	if (dceip->number_of_graphics_pipes >= data->number_of_displays && dceip->number_of_underlay_pipes >= data->number_of_underlay_surfaces && !(dceip->display_write_back_supported == 0 && data->d1_display_write_back_dwb_enable == 1)) {
-+		pipe_check = bw_def_ok;
-+	}
-+	else {
-+		pipe_check = bw_def_notok;
-+	}
-+	hsr_check = bw_def_ok;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (bw_neq(data->hsr[i], bw_int_to_fixed(1))) {
-+				if (bw_mtn(data->hsr[i], bw_int_to_fixed(4))) {
-+					hsr_check = bw_def_hsr_mtn_4;
-+				}
-+				else {
-+					if (bw_mtn(data->hsr[i], data->h_taps[i])) {
-+						hsr_check = bw_def_hsr_mtn_h_taps;
-+					}
-+					else {
-+						if (dceip->pre_downscaler_enabled == 1 && bw_mtn(data->hsr[i], bw_int_to_fixed(1)) && bw_leq(data->hsr[i], bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)))) {
-+							hsr_check = bw_def_ceiling__h_taps_div_4___meq_hsr;
-+						}
-+					}
-+				}
-+			}
-+		}
-+	}
-+	vsr_check = bw_def_ok;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (bw_neq(data->vsr[i], bw_int_to_fixed(1))) {
-+				if (bw_mtn(data->vsr[i], bw_int_to_fixed(4))) {
-+					vsr_check = bw_def_vsr_mtn_4;
-+				}
-+				else {
-+					if (bw_mtn(data->vsr[i], data->v_taps[i])) {
-+						vsr_check = bw_def_vsr_mtn_v_taps;
-+					}
-+				}
-+			}
-+		}
-+	}
-+	lb_size_check = bw_def_ok;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if ((dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1)))) {
-+				data->source_width_in_lb = bw_div(data->source_width_pixels[i], data->hsr[i]);
-+			}
-+			else {
-+				data->source_width_in_lb = data->source_width_pixels[i];
-+			}
-+			switch (data->lb_bpc[i]) {
-+			case 8:
-+				data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(2401171875ul, 100000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48));
-+				break;
-+			case 10:
-+				data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(300234375, 10000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48));
-+				break;
-+			default:
-+				data->lb_line_pitch = bw_ceil2(bw_mul(bw_int_to_fixed(data->lb_bpc[i]), data->source_width_in_lb), bw_int_to_fixed(48));
-+				break;
-+			}
-+			data->lb_partitions[i] = bw_floor2(bw_div(data->lb_size_per_component[i], data->lb_line_pitch), bw_int_to_fixed(1));
-+			/*clamp the partitions to the maxium number supported by the lb*/
-+			if ((surface_type[i] != bw_def_graphics || dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1)) {
-+				data->lb_partitions_max[i] = bw_int_to_fixed(10);
-+			}
-+			else {
-+				data->lb_partitions_max[i] = bw_int_to_fixed(7);
-+			}
-+			data->lb_partitions[i] = bw_min2(data->lb_partitions_max[i], data->lb_partitions[i]);
-+			if (bw_mtn(bw_add(data->v_taps[i], bw_int_to_fixed(1)), data->lb_partitions[i])) {
-+				lb_size_check = bw_def_notok;
-+			}
-+		}
-+	}
-+	fbc_check = bw_def_ok;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i] && data->fbc_en[i] == 1 && (bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270)) || data->stereo_mode[i] != bw_def_mono || data->bytes_per_pixel[i] != 4)) {
-+			fbc_check = bw_def_invalid_rotation_or_bpp_or_stereo;
-+		}
-+	}
-+	rotation_check = bw_def_ok;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && (tiling_mode[i] == bw_def_linear || data->stereo_mode[i] != bw_def_mono)) {
-+				rotation_check = bw_def_invalid_linear_or_stereo_mode;
-+			}
-+		}
-+	}
-+	if (pipe_check == bw_def_ok && hsr_check == bw_def_ok && vsr_check == bw_def_ok && lb_size_check == bw_def_ok && fbc_check == bw_def_ok && rotation_check == bw_def_ok) {
-+		mode_check = bw_def_ok;
-+	}
-+	else {
-+		mode_check = bw_def_notok;
-+	}
-+	/*number of memory channels for write-back client*/
-+	data->number_of_dram_wrchannels = vbios->number_of_dram_channels;
-+	data->number_of_dram_channels = vbios->number_of_dram_channels;
-+	/*modify number of memory channels if lpt mode is enabled*/
-+	/* low power tiling mode register*/
-+	/* 0 = use channel 0*/
-+	/* 1 = use channel 0 and 1*/
-+	/* 2 = use channel 0,1,2,3*/
-+	if ((fbc_enabled == 1 && lpt_enabled == 1)) {
-+		data->dram_efficiency = bw_int_to_fixed(1);
-+		if (dceip->low_power_tiling_mode == 0) {
-+			data->number_of_dram_channels = 1;
-+		}
-+		else if (dceip->low_power_tiling_mode == 1) {
-+			data->number_of_dram_channels = 2;
-+		}
-+		else if (dceip->low_power_tiling_mode == 2) {
-+			data->number_of_dram_channels = 4;
-+		}
-+		else {
-+			data->number_of_dram_channels = 1;
-+		}
-+	}
-+	else {
-+		data->dram_efficiency = bw_frc_to_fixed(8, 10);
-+	}
-+	/*memory request size and latency hiding:*/
-+	/*request size is normally 64 byte, 2-line interleaved, with full latency hiding*/
-+	/*the display write-back requests are single line*/
-+	/*for tiled graphics surfaces, or undelay surfaces with width higher than the maximum size for full efficiency, request size is 32 byte in 8 and 16 bpp or if the rotation is orthogonal to the tiling grain. only half is useful of the bytes in the request size in 8 bpp or in 32 bpp if the rotation is orthogonal to the tiling grain.*/
-+	/*for undelay surfaces with width lower than the maximum size for full efficiency, requests are 4-line interleaved in 16bpp if the rotation is parallel to the tiling grain, and 8-line interleaved with 4-line latency hiding in 8bpp or if the rotation is orthogonal to the tiling grain.*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270)))) {
-+				if ((i < 4)) {
-+					/*underlay portrait tiling mode is not supported*/
-+					data->orthogonal_rotation[i] = 1;
-+				}
-+				else {
-+					/*graphics portrait tiling mode*/
-+					if ((data->graphics_micro_tile_mode == bw_def_rotated_micro_tiling)) {
-+						data->orthogonal_rotation[i] = 0;
-+					}
-+					else {
-+						data->orthogonal_rotation[i] = 1;
-+					}
-+				}
-+			}
-+			else {
-+				if ((i < 4)) {
-+					/*underlay landscape tiling mode is only supported*/
-+					if ((data->underlay_micro_tile_mode == bw_def_display_micro_tiling)) {
-+						data->orthogonal_rotation[i] = 0;
-+					}
-+					else {
-+						data->orthogonal_rotation[i] = 1;
-+					}
-+				}
-+				else {
-+					/*graphics landscape tiling mode*/
-+					if ((data->graphics_micro_tile_mode == bw_def_display_micro_tiling)) {
-+						data->orthogonal_rotation[i] = 0;
-+					}
-+					else {
-+						data->orthogonal_rotation[i] = 1;
-+					}
-+				}
-+			}
-+			if (bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) {
-+				data->underlay_maximum_source_efficient_for_tiling = dceip->underlay_maximum_height_efficient_for_tiling;
-+			}
-+			else {
-+				data->underlay_maximum_source_efficient_for_tiling = dceip->underlay_maximum_width_efficient_for_tiling;
-+			}
-+			if (surface_type[i] == bw_def_display_write_back420_luma || surface_type[i] == bw_def_display_write_back420_chroma) {
-+				data->bytes_per_request[i] = bw_int_to_fixed(64);
-+				data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
-+				data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(1);
-+				data->latency_hiding_lines[i] = bw_int_to_fixed(1);
-+			}
-+			else if (tiling_mode[i] == bw_def_linear) {
-+				data->bytes_per_request[i] = bw_int_to_fixed(64);
-+				data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
-+				data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
-+				data->latency_hiding_lines[i] = bw_int_to_fixed(2);
-+			}
-+			else {
-+				if (surface_type[i] == bw_def_graphics || (bw_mtn(data->source_width_rounded_up_to_chunks[i], bw_ceil2(data->underlay_maximum_source_efficient_for_tiling, bw_int_to_fixed(256))))) {
-+					switch (data->bytes_per_pixel[i]) {
-+					case 8:
-+						data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
-+						data->latency_hiding_lines[i] = bw_int_to_fixed(2);
-+						if (data->orthogonal_rotation[i]) {
-+							data->bytes_per_request[i] = bw_int_to_fixed(32);
-+							data->useful_bytes_per_request[i] = bw_int_to_fixed(32);
-+						}
-+						else {
-+							data->bytes_per_request[i] = bw_int_to_fixed(64);
-+							data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
-+						}
-+						break;
-+					case 4:
-+						if (data->orthogonal_rotation[i]) {
-+							data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
-+							data->latency_hiding_lines[i] = bw_int_to_fixed(2);
-+							data->bytes_per_request[i] = bw_int_to_fixed(32);
-+							data->useful_bytes_per_request[i] = bw_int_to_fixed(16);
-+						}
-+						else {
-+							data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
-+							data->latency_hiding_lines[i] = bw_int_to_fixed(2);
-+							data->bytes_per_request[i] = bw_int_to_fixed(64);
-+							data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
-+						}
-+						break;
-+					case 2:
-+						data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
-+						data->latency_hiding_lines[i] = bw_int_to_fixed(2);
-+						data->bytes_per_request[i] = bw_int_to_fixed(32);
-+						data->useful_bytes_per_request[i] = bw_int_to_fixed(32);
-+						break;
-+					default:
-+						data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
-+						data->latency_hiding_lines[i] = bw_int_to_fixed(2);
-+						data->bytes_per_request[i] = bw_int_to_fixed(32);
-+						data->useful_bytes_per_request[i] = bw_int_to_fixed(16);
-+						break;
-+					}
-+				}
-+				else {
-+					data->bytes_per_request[i] = bw_int_to_fixed(64);
-+					data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
-+					if (data->orthogonal_rotation[i]) {
-+						data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(8);
-+						data->latency_hiding_lines[i] = bw_int_to_fixed(4);
-+					}
-+					else {
-+						switch (data->bytes_per_pixel[i]) {
-+						case 4:
-+							data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
-+							data->latency_hiding_lines[i] = bw_int_to_fixed(2);
-+							break;
-+						case 2:
-+							data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(4);
-+							data->latency_hiding_lines[i] = bw_int_to_fixed(4);
-+							break;
-+						default:
-+							data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(8);
-+							data->latency_hiding_lines[i] = bw_int_to_fixed(4);
-+							break;
-+						}
-+					}
-+				}
-+			}
-+		}
-+	}
-+	/*requested peak bandwidth:*/
-+	/*the peak request-per-second bandwidth is the product of the maximum source lines in per line out in the beginning*/
-+	/*and in the middle of the frame, the ratio of the source width to the line time, the ratio of line interleaving*/
-+	/*in memory to lines of latency hiding, and the ratio of bytes per pixel to useful bytes per request.*/
-+	/**/
-+	/*if the dmif data buffer size holds more than vta_ps worth of source lines, then only vsr is used.*/
-+	/*the peak bandwidth is the peak request-per-second bandwidth times the request size.*/
-+	/**/
-+	/*the line buffer lines in per line out in the beginning of the frame is the vertical filter initialization value*/
-+	/*rounded up to even and divided by the line times for initialization, which is normally three.*/
-+	/*the line buffer lines in per line out in the middle of the frame is at least one, or the vertical scale ratio,*/
-+	/*rounded up to line pairs if not doing line buffer prefetching.*/
-+	/**/
-+	/*the non-prefetching rounding up of the vertical scale ratio can also be done up to 1 (for a 0,2 pattern), 4/3 (for a 0,2,2 pattern),*/
-+	/*6/4 (for a 0,2,2,2 pattern), or 3 (for a 2,4 pattern).*/
-+	/**/
-+	/*the scaler vertical filter initialization value is calculated by the hardware as the floor of the average of the*/
-+	/*vertical scale ratio and the number of vertical taps increased by one.  add one more for possible odd line*/
-+	/*panning/bezel adjustment mode.*/
-+	/**/
-+	/*for the bottom interlace field an extra 50% of the vertical scale ratio is considered for this calculation.*/
-+	/*in top-bottom stereo mode software has to set the filter initialization value manually and explicitly limit it to 4.*/
-+	/*furthermore, there is only one line time for initialization.*/
-+	/**/
-+	/*line buffer prefetching is done when the number of lines in the line buffer exceeds the number of taps plus*/
-+	/*the ceiling of the vertical scale ratio.*/
-+	/**/
-+	/*multi-line buffer prefetching is only done in the graphics pipe when the scaler is disabled or when upscaling and the vsr <= 0.8.'*/
-+	/**/
-+	/*the horizontal blank and chunk granularity factor is indirectly used indicate the interval of time required to transfer the source pixels.*/
-+	/*the denominator of this term represents the total number of destination output pixels required for the input source pixels.*/
-+	/*it applies when the lines in per line out is not 2 or 4.  it does not apply when there is a line buffer between the scl and blnd.*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			data->v_filter_init[i] = bw_floor2(bw_div((bw_add(bw_add(bw_add(bw_int_to_fixed(1), data->v_taps[i]), data->vsr[i]), bw_mul(bw_mul(bw_int_to_fixed(data->interlace_mode[i]), bw_frc_to_fixed(5, 10)), data->vsr[i]))), bw_int_to_fixed(2)), bw_int_to_fixed(1));
-+			if (data->panning_and_bezel_adjustment == bw_def_any_lines) {
-+				data->v_filter_init[i] = bw_add(data->v_filter_init[i], bw_int_to_fixed(1));
-+			}
-+			if (data->stereo_mode[i] == bw_def_top_bottom) {
-+				v_filter_init_mode[i] = bw_def_manual;
-+				data->v_filter_init[i] = bw_min2(data->v_filter_init[i], bw_int_to_fixed(4));
-+			}
-+			else {
-+				v_filter_init_mode[i] = bw_def_auto;
-+			}
-+			if (data->stereo_mode[i] == bw_def_top_bottom) {
-+				data->num_lines_at_frame_start = bw_int_to_fixed(1);
-+			}
-+			else {
-+				data->num_lines_at_frame_start = bw_int_to_fixed(3);
-+			}
-+			if ((bw_mtn(data->vsr[i], bw_int_to_fixed(1)) && surface_type[i] == bw_def_graphics) || data->panning_and_bezel_adjustment == bw_def_any_lines) {
-+				data->line_buffer_prefetch[i] = 0;
-+			}
-+			else if ((((dceip->underlay_downscale_prefetch_enabled == 1 && surface_type[i] != bw_def_graphics) || surface_type[i] == bw_def_graphics) && (bw_mtn(data->lb_partitions[i], bw_add(data->v_taps[i], bw_ceil2(data->vsr[i], bw_int_to_fixed(1))))))) {
-+				data->line_buffer_prefetch[i] = 1;
-+			}
-+			else {
-+				data->line_buffer_prefetch[i] = 0;
-+			}
-+			data->lb_lines_in_per_line_out_in_beginning_of_frame[i] = bw_div(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->num_lines_at_frame_start);
-+			if (data->line_buffer_prefetch[i] == 1) {
-+				data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_max2(bw_int_to_fixed(1), data->vsr[i]);
-+			}
-+			else if (bw_leq(data->vsr[i], bw_int_to_fixed(1))) {
-+				data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(1);
-+			} else if (bw_leq(data->vsr[i],
-+					bw_frc_to_fixed(4, 3))) {
-+				data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_div(bw_int_to_fixed(4), bw_int_to_fixed(3));
-+			} else if (bw_leq(data->vsr[i],
-+					bw_frc_to_fixed(6, 4))) {
-+				data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_div(bw_int_to_fixed(6), bw_int_to_fixed(4));
-+			}
-+			else if (bw_leq(data->vsr[i], bw_int_to_fixed(2))) {
-+				data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(2);
-+			}
-+			else if (bw_leq(data->vsr[i], bw_int_to_fixed(3))) {
-+				data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(3);
-+			}
-+			else {
-+				data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(4);
-+			}
-+			if (data->line_buffer_prefetch[i] == 1 || bw_equ(data->lb_lines_in_per_line_out_in_middle_of_frame[i], bw_int_to_fixed(2)) || bw_equ(data->lb_lines_in_per_line_out_in_middle_of_frame[i], bw_int_to_fixed(4))) {
-+				data->horizontal_blank_and_chunk_granularity_factor[i] = bw_int_to_fixed(1);
-+			}
-+			else {
-+				data->horizontal_blank_and_chunk_granularity_factor[i] = bw_div(data->h_total[i], (bw_div((bw_add(data->h_total[i], bw_div((bw_sub(data->source_width_pixels[i], bw_int_to_fixed(dceip->chunk_width))), data->hsr[i]))), bw_int_to_fixed(2))));
-+			}
-+			data->request_bandwidth[i] = bw_div(bw_mul(bw_div(bw_mul(bw_div(bw_mul(bw_max2(data->lb_lines_in_per_line_out_in_beginning_of_frame[i], data->lb_lines_in_per_line_out_in_middle_of_frame[i]), data->source_width_rounded_up_to_chunks[i]), (bw_div(data->h_total[i], data->pixel_rate[i]))), bw_int_to_fixed(data->bytes_per_pixel[i])), data->useful_bytes_per_request[i]), data->lines_interleaved_in_mem_access[i]), data->latency_hiding_lines[i]);
-+			data->display_bandwidth[i] = bw_mul(data->request_bandwidth[i], data->bytes_per_request[i]);
-+		}
-+	}
-+	/*outstanding chunk request limit*/
-+	/*if underlay buffer sharing is enabled, the data buffer size for underlay in 422 or 444 is the sum of the luma and chroma data buffer sizes.*/
-+	/*underlay buffer sharing mode is only permitted in orthogonal rotation modes.*/
-+	/**/
-+	/*if there is only one display enabled, the dmif data buffer size for the graphics surface is increased by concatenating the adjacent buffers.*/
-+	/**/
-+	/*the memory chunk size in bytes is 1024 for the writeback, and 256 times the memory line interleaving and the bytes per pixel for graphics*/
-+	/*and underlay.*/
-+	/**/
-+	/*the pipe chunk size uses 2 for line interleaving, except for the write back, in which case it is 1.*/
-+	/*graphics and underlay data buffer size is adjusted (limited) using the outstanding chunk request limit if there is more than one*/
-+	/*display enabled or if the dmif request buffer is not large enough for the total data buffer size.*/
-+	/*the outstanding chunk request limit is the ceiling of the adjusted data buffer size divided by the chunk size in bytes*/
-+	/*the adjusted data buffer size is the product of the display bandwidth and the minimum effective data buffer size in terms of time,*/
-+	/*rounded up to the chunk size in bytes, but should not exceed the original data buffer size*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if ((dceip->dmif_pipe_en_fbc_chunk_tracker + 3 == i && fbc_enabled == 0 && tiling_mode[i] != bw_def_linear)) {
-+				data->max_chunks_non_fbc_mode[i] = 128 - dmif_chunk_buff_margin;
-+			}
-+			else {
-+				data->max_chunks_non_fbc_mode[i] = 16 - dmif_chunk_buff_margin;
-+			}
-+		}
-+		if (data->fbc_en[i] == 1) {
-+			max_chunks_fbc_mode = 128 - dmif_chunk_buff_margin;
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			switch (surface_type[i]) {
-+			case bw_def_display_write_back420_luma:
-+				data->data_buffer_size[i] = bw_int_to_fixed(dceip->display_write_back420_luma_mcifwr_buffer_size);
-+				break;
-+			case bw_def_display_write_back420_chroma:
-+				data->data_buffer_size[i] = bw_int_to_fixed(dceip->display_write_back420_chroma_mcifwr_buffer_size);
-+				break;
-+			case bw_def_underlay420_luma:
-+				data->data_buffer_size[i] = bw_int_to_fixed(dceip->underlay_luma_dmif_size);
-+				break;
-+			case bw_def_underlay420_chroma:
-+				data->data_buffer_size[i] = bw_div(bw_int_to_fixed(dceip->underlay_chroma_dmif_size), bw_int_to_fixed(2));
-+				break;
-+			case bw_def_underlay422:case bw_def_underlay444:
-+				if (data->orthogonal_rotation[i] == 0) {
-+					data->data_buffer_size[i] = bw_int_to_fixed(dceip->underlay_luma_dmif_size);
-+				}
-+				else {
-+					data->data_buffer_size[i] = bw_add(bw_int_to_fixed(dceip->underlay_luma_dmif_size), bw_int_to_fixed(dceip->underlay_chroma_dmif_size));
-+				}
-+				break;
-+			default:
-+				if (data->fbc_en[i] == 1) {
-+					/*data_buffer_size(i) = max_dmif_buffer_allocated * graphics_dmif_size*/
-+					if (data->number_of_displays == 1) {
-+						data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(max_chunks_fbc_mode), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_mul(bw_int_to_fixed(dceip->max_dmif_buffer_allocated), bw_int_to_fixed(dceip->graphics_dmif_size)));
-+					}
-+					else {
-+						data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(max_chunks_fbc_mode), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_int_to_fixed(dceip->graphics_dmif_size));
-+					}
-+				}
-+				else {
-+					/*the effective dmif buffer size in non-fbc mode is limited by the 16 entry chunk tracker*/
-+					if (data->number_of_displays == 1) {
-+						data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(data->max_chunks_non_fbc_mode[i]), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_mul(bw_int_to_fixed(dceip->max_dmif_buffer_allocated), bw_int_to_fixed(dceip->graphics_dmif_size)));
-+					}
-+					else {
-+						data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(data->max_chunks_non_fbc_mode[i]), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_int_to_fixed(dceip->graphics_dmif_size));
-+					}
-+				}
-+				break;
-+			}
-+			if (surface_type[i] == bw_def_display_write_back420_luma || surface_type[i] == bw_def_display_write_back420_chroma) {
-+				data->memory_chunk_size_in_bytes[i] = bw_int_to_fixed(1024);
-+				data->pipe_chunk_size_in_bytes[i] = bw_int_to_fixed(1024);
-+			}
-+			else {
-+				data->memory_chunk_size_in_bytes[i] = bw_mul(bw_mul(bw_int_to_fixed(dceip->chunk_width), data->lines_interleaved_in_mem_access[i]), bw_int_to_fixed(data->bytes_per_pixel[i]));
-+				data->pipe_chunk_size_in_bytes[i] = bw_mul(bw_mul(bw_int_to_fixed(dceip->chunk_width), bw_int_to_fixed(dceip->lines_interleaved_into_lb)), bw_int_to_fixed(data->bytes_per_pixel[i]));
-+			}
-+		}
-+	}
-+	data->min_dmif_size_in_time = bw_int_to_fixed(9999);
-+	data->min_mcifwr_size_in_time = bw_int_to_fixed(9999);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
-+				if (bw_ltn(bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]), data->min_dmif_size_in_time)) {
-+					data->min_dmif_size_in_time = bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]);
-+				}
-+			}
-+			else {
-+				if (bw_ltn(bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]), data->min_mcifwr_size_in_time)) {
-+					data->min_mcifwr_size_in_time = bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]);
-+				}
-+			}
-+		}
-+	}
-+	data->total_requests_for_dmif_size = bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i] && surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
-+			data->total_requests_for_dmif_size = bw_add(data->total_requests_for_dmif_size, bw_div(data->data_buffer_size[i], data->useful_bytes_per_request[i]));
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma && dceip->limit_excessive_outstanding_dmif_requests && (data->number_of_displays > 1 || bw_mtn(data->total_requests_for_dmif_size, dceip->dmif_request_buffer_size))) {
-+				data->adjusted_data_buffer_size[i] = bw_min2(data->data_buffer_size[i], bw_ceil2(bw_mul(data->min_dmif_size_in_time, data->display_bandwidth[i]), data->memory_chunk_size_in_bytes[i]));
-+			}
-+			else {
-+				data->adjusted_data_buffer_size[i] = data->data_buffer_size[i];
-+			}
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if ((data->number_of_displays == 1 && data->number_of_underlay_surfaces == 0)) {
-+				/*set maximum chunk limit if only one graphic pipe is enabled*/
-+				data->outstanding_chunk_request_limit[i] = bw_int_to_fixed(127);
-+			}
-+			else {
-+				data->outstanding_chunk_request_limit[i] = bw_ceil2(bw_div(data->adjusted_data_buffer_size[i], data->pipe_chunk_size_in_bytes[i]), bw_int_to_fixed(1));
-+				/*clamp maximum chunk limit in the graphic display pipe*/
-+				if ((i >= 4)) {
-+					data->outstanding_chunk_request_limit[i] = bw_max2(bw_int_to_fixed(127), data->outstanding_chunk_request_limit[i]);
-+				}
-+			}
-+		}
-+	}
-+	/*outstanding pte request limit*/
-+	/*in tiling mode with no rotation the sg pte requests are 8 useful pt_es, the sg row height is the page height and the sg page width x height is 64x64 for 8bpp, 64x32 for 16 bpp, 32x32 for 32 bpp*/
-+	/*in tiling mode with rotation the sg pte requests are only one useful pte, and the sg row height is also the page height, but the sg page width and height are swapped*/
-+	/*in linear mode the pte requests are 8 useful pt_es, the sg page width is 4096 divided by the bytes per pixel, the sg page height is 1, but there is just one row whose height is the lines of pte prefetching*/
-+	/*the outstanding pte request limit is obtained by multiplying the outstanding chunk request limit by the peak pte request to eviction limiting ratio, rounding up to integer, multiplying by the pte requests per chunk, and rounding up to integer again*/
-+	/*if not using peak pte request to eviction limiting, the outstanding pte request limit is the pte requests in the vblank*/
-+	/*the pte requests in the vblank is the product of the number of pte request rows times the number of pte requests in a row*/
-+	/*the number of pte requests in a row is the quotient of the source width divided by 256, multiplied by the pte requests per chunk, rounded up to even, multiplied by the scatter-gather row height and divided by the scatter-gather page height*/
-+	/*the pte requests per chunk is 256 divided by the scatter-gather page width and the useful pt_es per pte request*/
-+	if (data->number_of_displays > 1 || (bw_neq(data->rotation_angle[4], bw_int_to_fixed(0)) && bw_neq(data->rotation_angle[4], bw_int_to_fixed(180)))) {
-+		data->peak_pte_request_to_eviction_ratio_limiting = dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display;
-+	}
-+	else {
-+		data->peak_pte_request_to_eviction_ratio_limiting = dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation;
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i] && data->scatter_gather_enable_for_pipe[i] == 1) {
-+			if (tiling_mode[i] == bw_def_linear) {
-+				data->useful_pte_per_pte_request = bw_int_to_fixed(8);
-+				data->scatter_gather_page_width[i] = bw_div(bw_int_to_fixed(4096), bw_int_to_fixed(data->bytes_per_pixel[i]));
-+				data->scatter_gather_page_height[i] = bw_int_to_fixed(1);
-+				data->scatter_gather_pte_request_rows = bw_int_to_fixed(1);
-+				data->scatter_gather_row_height = bw_int_to_fixed(dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode);
-+			}
-+			else if (bw_equ(data->rotation_angle[i], bw_int_to_fixed(0)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(180))) {
-+				data->useful_pte_per_pte_request = bw_int_to_fixed(8);
-+				switch (data->bytes_per_pixel[i]) {
-+				case 4:
-+					data->scatter_gather_page_width[i] = bw_int_to_fixed(32);
-+					data->scatter_gather_page_height[i] = bw_int_to_fixed(32);
-+					break;
-+				case 2:
-+					data->scatter_gather_page_width[i] = bw_int_to_fixed(64);
-+					data->scatter_gather_page_height[i] = bw_int_to_fixed(32);
-+					break;
-+				default:
-+					data->scatter_gather_page_width[i] = bw_int_to_fixed(64);
-+					data->scatter_gather_page_height[i] = bw_int_to_fixed(64);
-+					break;
-+				}
-+				data->scatter_gather_pte_request_rows = bw_int_to_fixed(dceip->scatter_gather_pte_request_rows_in_tiling_mode);
-+				data->scatter_gather_row_height = data->scatter_gather_page_height[i];
-+			}
-+			else {
-+				data->useful_pte_per_pte_request = bw_int_to_fixed(1);
-+				switch (data->bytes_per_pixel[i]) {
-+				case 4:
-+					data->scatter_gather_page_width[i] = bw_int_to_fixed(32);
-+					data->scatter_gather_page_height[i] = bw_int_to_fixed(32);
-+					break;
-+				case 2:
-+					data->scatter_gather_page_width[i] = bw_int_to_fixed(32);
-+					data->scatter_gather_page_height[i] = bw_int_to_fixed(64);
-+					break;
-+				default:
-+					data->scatter_gather_page_width[i] = bw_int_to_fixed(64);
-+					data->scatter_gather_page_height[i] = bw_int_to_fixed(64);
-+					break;
-+				}
-+				data->scatter_gather_pte_request_rows = bw_int_to_fixed(dceip->scatter_gather_pte_request_rows_in_tiling_mode);
-+				data->scatter_gather_row_height = data->scatter_gather_page_height[i];
-+			}
-+			data->pte_request_per_chunk[i] = bw_div(bw_div(bw_int_to_fixed(dceip->chunk_width), data->scatter_gather_page_width[i]), data->useful_pte_per_pte_request);
-+			data->scatter_gather_pte_requests_in_row[i] = bw_div(bw_mul(bw_ceil2(bw_mul(bw_div(data->source_width_rounded_up_to_chunks[i], bw_int_to_fixed(dceip->chunk_width)), data->pte_request_per_chunk[i]), bw_int_to_fixed(1)), data->scatter_gather_row_height), data->scatter_gather_page_height[i]);
-+			data->scatter_gather_pte_requests_in_vblank = bw_mul(data->scatter_gather_pte_request_rows, data->scatter_gather_pte_requests_in_row[i]);
-+			if (bw_equ(data->peak_pte_request_to_eviction_ratio_limiting, bw_int_to_fixed(0))) {
-+				data->scatter_gather_pte_request_limit[i] = data->scatter_gather_pte_requests_in_vblank;
-+			}
-+			else {
-+				data->scatter_gather_pte_request_limit[i] = bw_max2(dceip->minimum_outstanding_pte_request_limit, bw_min2(data->scatter_gather_pte_requests_in_vblank, bw_ceil2(bw_mul(bw_mul(bw_div(bw_ceil2(data->adjusted_data_buffer_size[i], data->memory_chunk_size_in_bytes[i]), data->memory_chunk_size_in_bytes[i]), data->pte_request_per_chunk[i]), data->peak_pte_request_to_eviction_ratio_limiting), bw_int_to_fixed(1))));
-+			}
-+		}
-+	}
-+	/*pitch padding recommended for efficiency in linear mode*/
-+	/*in linear mode graphics or underlay with scatter gather, a pitch that is a multiple of the channel interleave (256 bytes) times the channel-bank rotation is not efficient*/
-+	/*if that is the case it is recommended to pad the pitch by at least 256 pixels*/
-+	data->inefficient_linear_pitch_in_bytes = bw_mul(bw_mul(bw_int_to_fixed(256), bw_int_to_fixed(vbios->number_of_dram_banks)), bw_int_to_fixed(data->number_of_dram_channels));
-+
-+	/*pixel transfer time*/
-+	/*the dmif and mcifwr yclk(pclk) required is the one that allows the transfer of all pipe's data buffer size in memory in the time for data transfer*/
-+	/*for dmif, pte and cursor requests have to be included.*/
-+	/*the dram data requirement is doubled when the data request size in bytes is less than the dram channel width times the burst size (8)*/
-+	/*the dram data requirement is also multiplied by the number of channels in the case of low power tiling*/
-+	/*the page close-open time is determined by trc and the number of page close-opens*/
-+	/*in tiled mode graphics or underlay with scatter-gather enabled the bytes per page close-open is the product of the memory line interleave times the maximum of the scatter-gather page width and the product of the tile width (8 pixels) times the number of channels times the number of banks.*/
-+	/*in linear mode graphics or underlay with scatter-gather enabled and inefficient pitch, the bytes per page close-open is the line request alternation slice, because different lines are in completely different 4k address bases.*/
-+	/*otherwise, the bytes page close-open is the chunk size because that is the arbitration slice.*/
-+	/*pte requests are grouped by pte requests per chunk if that is more than 1. each group costs a page close-open time for dmif reads*/
-+	/*cursor requests outstanding are limited to a group of two source lines. each group costs a page close-open time for dmif reads*/
-+	/*the display reads and writes time for data transfer is the minimum data or cursor buffer size in time minus the mc urgent latency*/
-+	/*the mc urgent latency is experienced more than one time if the number of dmif requests in the data buffer exceeds the request buffer size plus the request slots reserved for dmif in the dram channel arbiter queues*/
-+	/*the dispclk required is the maximum for all surfaces of the maximum of the source pixels for first output pixel times the throughput factor, divided by the pixels per dispclk, and divided by the minimum latency hiding minus the dram speed/p-state change latency minus the burst time, and the source pixels for last output pixel, times the throughput factor, divided by the pixels per dispclk, and divided by the minimum latency hiding minus the dram speed/p-state change latency minus the burst time, plus the active time.*/
-+	/*the data burst time is the maximum of the total page close-open time, total dmif/mcifwr buffer size in memory divided by the dram bandwidth, and the total dmif/mcifwr buffer size in memory divided by the 32 byte sclk data bus bandwidth, each multiplied by its efficiency.*/
-+	/*the source line transfer time is the maximum for all surfaces of the maximum of the burst time plus the urgent latency times the floor of the data required divided by the buffer size for the fist pixel, and the burst time plus the urgent latency times the floor of the data required divided by the buffer size for the last pixel plus the active time.*/
-+	/*the source pixels for the first output pixel is 512 if the scaler vertical filter initialization value is greater than 2, and it is 4 times the source width if it is greater than 4.*/
-+	/*the source pixels for the last output pixel is the source width times the scaler vertical filter initialization value rounded up to even*/
-+	/*the source data for these pixels is the number of pixels times the bytes per pixel times the bytes per request divided by the useful bytes per request.*/
-+	data->cursor_total_data = bw_int_to_fixed(0);
-+	data->cursor_total_request_groups = bw_int_to_fixed(0);
-+	data->scatter_gather_total_pte_requests = bw_int_to_fixed(0);
-+	data->scatter_gather_total_pte_request_groups = bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			data->cursor_total_data = bw_add(data->cursor_total_data, bw_mul(bw_mul(bw_int_to_fixed(2), data->cursor_width_pixels[i]), bw_int_to_fixed(4)));
-+			if (dceip->large_cursor == 1) {
-+				data->cursor_total_request_groups = bw_add(data->cursor_total_request_groups, bw_int_to_fixed((dceip->cursor_max_outstanding_group_num + 1)));
-+			}
-+			else {
-+				data->cursor_total_request_groups = bw_add(data->cursor_total_request_groups, bw_ceil2(bw_div(data->cursor_width_pixels[i], dceip->cursor_chunk_width), bw_int_to_fixed(1)));
-+			}
-+			if (data->scatter_gather_enable_for_pipe[i]) {
-+				data->scatter_gather_total_pte_requests = bw_add(data->scatter_gather_total_pte_requests, data->scatter_gather_pte_request_limit[i]);
-+				data->scatter_gather_total_pte_request_groups = bw_add(data->scatter_gather_total_pte_request_groups, bw_ceil2(bw_div(data->scatter_gather_pte_request_limit[i], bw_ceil2(data->pte_request_per_chunk[i], bw_int_to_fixed(1))), bw_int_to_fixed(1)));
-+			}
-+		}
-+	}
-+	data->tile_width_in_pixels = bw_int_to_fixed(8);
-+	data->dmif_total_number_of_data_request_page_close_open = bw_int_to_fixed(0);
-+	data->mcifwr_total_number_of_data_request_page_close_open = bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] != bw_def_linear) {
-+				data->bytes_per_page_close_open = bw_mul(data->lines_interleaved_in_mem_access[i], bw_max2(bw_mul(bw_mul(bw_mul(bw_int_to_fixed(data->bytes_per_pixel[i]), data->tile_width_in_pixels), bw_int_to_fixed(vbios->number_of_dram_banks)), bw_int_to_fixed(data->number_of_dram_channels)), bw_mul(bw_int_to_fixed(data->bytes_per_pixel[i]), data->scatter_gather_page_width[i])));
-+			}
-+			else if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] == bw_def_linear && bw_equ(bw_mod((bw_mul(data->pitch_in_pixels_after_surface_type[i], bw_int_to_fixed(data->bytes_per_pixel[i]))), data->inefficient_linear_pitch_in_bytes), bw_int_to_fixed(0))) {
-+				data->bytes_per_page_close_open = dceip->linear_mode_line_request_alternation_slice;
-+			}
-+			else {
-+				data->bytes_per_page_close_open = data->memory_chunk_size_in_bytes[i];
-+			}
-+			if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
-+				data->dmif_total_number_of_data_request_page_close_open = bw_add(data->dmif_total_number_of_data_request_page_close_open, bw_div(bw_ceil2(data->adjusted_data_buffer_size[i], data->memory_chunk_size_in_bytes[i]), data->bytes_per_page_close_open));
-+			}
-+			else {
-+				data->mcifwr_total_number_of_data_request_page_close_open = bw_add(data->mcifwr_total_number_of_data_request_page_close_open, bw_div(bw_ceil2(data->adjusted_data_buffer_size[i], data->memory_chunk_size_in_bytes[i]), data->bytes_per_page_close_open));
-+			}
-+		}
-+	}
-+	data->dmif_total_page_close_open_time = bw_div(bw_mul((bw_add(bw_add(data->dmif_total_number_of_data_request_page_close_open, data->scatter_gather_total_pte_request_groups), data->cursor_total_request_groups)), vbios->trc), bw_int_to_fixed(1000));
-+	data->mcifwr_total_page_close_open_time = bw_div(bw_mul(data->mcifwr_total_number_of_data_request_page_close_open, vbios->trc), bw_int_to_fixed(1000));
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			data->adjusted_data_buffer_size_in_memory[i] = bw_div(bw_mul(data->adjusted_data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
-+		}
-+	}
-+	data->total_requests_for_adjusted_dmif_size = bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
-+				data->total_requests_for_adjusted_dmif_size = bw_add(data->total_requests_for_adjusted_dmif_size, bw_div(data->adjusted_data_buffer_size[i], data->useful_bytes_per_request[i]));
-+			}
-+		}
-+	}
-+	data->total_dmifmc_urgent_trips = bw_ceil2(bw_div(data->total_requests_for_adjusted_dmif_size, (bw_add(dceip->dmif_request_buffer_size, bw_int_to_fixed(vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel * data->number_of_dram_channels)))), bw_int_to_fixed(1));
-+	data->total_dmifmc_urgent_latency = bw_mul(vbios->dmifmc_urgent_latency, data->total_dmifmc_urgent_trips);
-+	data->total_display_reads_required_data = bw_int_to_fixed(0);
-+	data->total_display_reads_required_dram_access_data = bw_int_to_fixed(0);
-+	data->total_display_writes_required_data = bw_int_to_fixed(0);
-+	data->total_display_writes_required_dram_access_data = bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
-+				data->display_reads_required_data = data->adjusted_data_buffer_size_in_memory[i];
-+				/*for hbm memories, each channel is split into 2 pseudo-channels that are each 64 bits in width.  each*/
-+				/*pseudo-channel may be read independently of one another.*/
-+				/*the read burst length (bl) for hbm memories is 4, so each read command will access 32 bytes of data.*/
-+				/*the 64 or 32 byte sized data is stored in one pseudo-channel.*/
-+				/*it will take 4 memclk cycles or 8 yclk cycles to fetch 64 bytes of data from the hbm memory (2 read commands).*/
-+				/*it will take 2 memclk cycles or 4 yclk cycles to fetch 32 bytes of data from the hbm memory (1 read command).*/
-+				/*for gddr5/ddr4 memories, there is additional overhead if the size of the request is smaller than 64 bytes.*/
-+				/*the read burst length (bl) for gddr5/ddr4 memories is 8, regardless of the size of the data request.*/
-+				/*therefore it will require 8 cycles to fetch 64 or 32 bytes of data from the memory.*/
-+				/*the memory efficiency will be 50% for the 32 byte sized data.*/
-+				if (vbios->memory_type == bw_def_hbm) {
-+					data->display_reads_required_dram_access_data = data->adjusted_data_buffer_size_in_memory[i];
-+				}
-+				else {
-+					data->display_reads_required_dram_access_data = bw_mul(data->adjusted_data_buffer_size_in_memory[i], bw_ceil2(bw_div(bw_int_to_fixed((8 * vbios->dram_channel_width_in_bits / 8)), data->bytes_per_request[i]), bw_int_to_fixed(1)));
-+				}
-+				data->total_display_reads_required_data = bw_add(data->total_display_reads_required_data, data->display_reads_required_data);
-+				data->total_display_reads_required_dram_access_data = bw_add(data->total_display_reads_required_dram_access_data, data->display_reads_required_dram_access_data);
-+			}
-+			else {
-+				data->total_display_writes_required_data = bw_add(data->total_display_writes_required_data, data->adjusted_data_buffer_size_in_memory[i]);
-+				data->total_display_writes_required_dram_access_data = bw_add(data->total_display_writes_required_dram_access_data, bw_mul(data->adjusted_data_buffer_size_in_memory[i], bw_ceil2(bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits), data->bytes_per_request[i]), bw_int_to_fixed(1))));
-+			}
-+		}
-+	}
-+	data->total_display_reads_required_data = bw_add(bw_add(data->total_display_reads_required_data, data->cursor_total_data), bw_mul(data->scatter_gather_total_pte_requests, bw_int_to_fixed(64)));
-+	data->total_display_reads_required_dram_access_data = bw_add(bw_add(data->total_display_reads_required_dram_access_data, data->cursor_total_data), bw_mul(data->scatter_gather_total_pte_requests, bw_int_to_fixed(64)));
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (bw_mtn(data->v_filter_init[i], bw_int_to_fixed(4))) {
-+				data->src_pixels_for_first_output_pixel[i] = bw_mul(bw_int_to_fixed(4), data->source_width_rounded_up_to_chunks[i]);
-+			}
-+			else {
-+				if (bw_mtn(data->v_filter_init[i], bw_int_to_fixed(2))) {
-+					data->src_pixels_for_first_output_pixel[i] = bw_int_to_fixed(512);
-+				}
-+				else {
-+					data->src_pixels_for_first_output_pixel[i] = bw_int_to_fixed(0);
-+				}
-+			}
-+			data->src_data_for_first_output_pixel[i] = bw_div(bw_mul(bw_mul(data->src_pixels_for_first_output_pixel[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
-+			data->src_pixels_for_last_output_pixel[i] = bw_mul(data->source_width_rounded_up_to_chunks[i], bw_max2(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), bw_mul(bw_ceil2(data->vsr[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->horizontal_blank_and_chunk_granularity_factor[i])));
-+			data->src_data_for_last_output_pixel[i] = bw_div(bw_mul(bw_mul(bw_mul(data->source_width_rounded_up_to_chunks[i], bw_max2(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->lines_interleaved_in_mem_access[i])), bw_int_to_fixed(data->bytes_per_pixel[i])), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
-+			data->active_time[i] = bw_div(bw_div(data->source_width_rounded_up_to_chunks[i], data->hsr[i]), data->pixel_rate[i]);
-+		}
-+	}
-+	for (i = 0; i <= 2; i++) {
-+		for (j = 0; j <= 7; j++) {
-+			data->dmif_burst_time[i][j] = bw_max3(data->dmif_total_page_close_open_time, bw_div(data->total_display_reads_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels)))), bw_div(data->total_display_reads_required_data, (bw_mul(bw_mul(sclk[j], vbios->data_return_bus_width), bw_int_to_fixed(bus_efficiency)))));
-+			if (data->d1_display_write_back_dwb_enable == 1) {
-+				data->mcifwr_burst_time[i][j] = bw_max3(data->mcifwr_total_page_close_open_time, bw_div(data->total_display_writes_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_wrchannels)))), bw_div(data->total_display_writes_required_data, (bw_mul(bw_mul(sclk[j], vbios->data_return_bus_width), bw_int_to_fixed(bus_efficiency)))));
-+			}
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		for (j = 0; j <= 2; j++) {
-+			for (k = 0; k <= 7; k++) {
-+				if (data->enable[i]) {
-+					if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
-+						/*time to transfer data from the dmif buffer to the lb.  since the mc to dmif transfer time overlaps*/
-+						/*with the dmif to lb transfer time, only time to transfer the last chunk  is considered.*/
-+						data->dmif_buffer_transfer_time[i] = bw_mul(data->source_width_rounded_up_to_chunks[i], (bw_div(dceip->lb_write_pixels_per_dispclk, (bw_div(vbios->low_voltage_max_dispclk, dceip->display_pipe_throughput_factor)))));
-+						data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_add(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->dmif_buffer_transfer_time[i]), data->active_time[i]));
-+						/*during an mclk switch the requests from the dce ip are stored in the gmc/arb.  these requests should be serviced immediately*/
-+						/*after the mclk switch sequence and not incur an urgent latency penalty.  it is assumed that the gmc/arb can hold up to 256 requests*/
-+						/*per memory channel.  if the dce ip is urgent after the mclk switch sequence, all pending requests and subsequent requests should be*/
-+						/*immediately serviced without a gap in the urgent requests.*/
-+						/*the latency incurred would be the time to issue the requests and return the data for the first or last output pixel.*/
-+						if (surface_type[i] == bw_def_graphics) {
-+							switch (data->lb_bpc[i]) {
-+							case 6:
-+								data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency6_bit_per_component;
-+								break;
-+							case 8:
-+								data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency8_bit_per_component;
-+								break;
-+							case 10:
-+								data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency10_bit_per_component;
-+								break;
-+							default:
-+								data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency12_bit_per_component;
-+								break;
-+							}
-+							if (data->use_alpha[i] == 1) {
-+								data->v_scaler_efficiency = bw_min2(data->v_scaler_efficiency, dceip->alpha_vscaler_efficiency);
-+							}
-+						}
-+						else {
-+							switch (data->lb_bpc[i]) {
-+							case 6:
-+								data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency6_bit_per_component;
-+								break;
-+							case 8:
-+								data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency8_bit_per_component;
-+								break;
-+							case 10:
-+								data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency10_bit_per_component;
-+								break;
-+							default:
-+								data->v_scaler_efficiency = bw_int_to_fixed(3);
-+								break;
-+							}
-+						}
-+						if (dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1))) {
-+							data->scaler_limits_factor = bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_div(data->source_width_rounded_up_to_chunks[i], data->h_total[i]));
-+						}
-+						else {
-+							data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1))));
-+						}
-+						data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_mul(bw_int_to_fixed(2), bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]))))));
-+					}
-+					else {
-+						data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]));
-+						/*during an mclk switch the requests from the dce ip are stored in the gmc/arb.  these requests should be serviced immediately*/
-+						/*after the mclk switch sequence and not incur an urgent latency penalty.  it is assumed that the gmc/arb can hold up to 256 requests*/
-+						/*per memory channel.  if the dce ip is urgent after the mclk switch sequence, all pending requests and subsequent requests should be*/
-+						/*immediately serviced without a gap in the urgent requests.*/
-+						/*the latency incurred would be the time to issue the requests and return the data for the first or last output pixel.*/
-+						data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i])))));
-+					}
-+				}
-+			}
-+		}
-+	}
-+	/*cpu c-state and p-state change enable*/
-+	/*for cpu p-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration*/
-+	/*for cpu c-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration and recovery*/
-+	/*condition for the blackout duration:*/
-+	/* minimum latency hiding > blackout duration + dmif burst time + line source transfer time*/
-+	/*condition for the blackout recovery:*/
-+	/* recovery time >  dmif burst time + 2 * urgent latency*/
-+	/* recovery time > (display bw * blackout duration  + (2 * urgent latency + dmif burst time)*dispclk - dmif size )*/
-+	/*                  / (dispclk - display bw)*/
-+	/*the minimum latency hiding is the minimum for all pipes of one screen line time, plus one more line time if doing lb prefetch, plus the dmif data buffer size equivalent in time, minus the urgent latency.*/
-+	/*the minimum latency hiding is  further limited by the cursor.  the cursor latency hiding is the number of lines of the cursor buffer, minus one if the downscaling is less than two, or minus three if it is more*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if ((bw_equ(dceip->stutter_and_dram_clock_state_change_gated_before_cursor, bw_int_to_fixed(0)) && bw_mtn(data->cursor_width_pixels[i], bw_int_to_fixed(0)))) {
-+				if (bw_ltn(data->vsr[i], bw_int_to_fixed(2))) {
-+					data->cursor_latency_hiding[i] = bw_div(bw_div(bw_mul((bw_sub(dceip->cursor_dcp_buffer_lines, bw_int_to_fixed(1))), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]);
-+				}
-+				else {
-+					data->cursor_latency_hiding[i] = bw_div(bw_div(bw_mul((bw_sub(dceip->cursor_dcp_buffer_lines, bw_int_to_fixed(3))), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]);
-+				}
-+			}
-+			else {
-+				data->cursor_latency_hiding[i] = bw_int_to_fixed(9999);
-+			}
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1 && (bw_equ(data->vsr[i], bw_int_to_fixed(1)) || (bw_leq(data->vsr[i], bw_frc_to_fixed(8, 10)) && bw_leq(data->v_taps[i], bw_int_to_fixed(2)) && data->lb_bpc[i] == 8)) && surface_type[i] == bw_def_graphics) {
-+				data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_sub(data->lb_partitions[i], bw_int_to_fixed(1)), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);
-+			}
-+			else {
-+				data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_int_to_fixed(1 + data->line_buffer_prefetch[i]), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);
-+			}
-+			data->minimum_latency_hiding_with_cursor[i] = bw_min2(data->minimum_latency_hiding[i], data->cursor_latency_hiding[i]);
-+		}
-+	}
-+	for (i = 0; i <= 2; i++) {
-+		for (j = 0; j <= 7; j++) {
-+			data->blackout_duration_margin[i][j] = bw_int_to_fixed(9999);
-+			data->dispclk_required_for_blackout_duration[i][j] = bw_int_to_fixed(0);
-+			data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(0);
-+			for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
-+				if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0))) {
-+					if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
-+						data->blackout_duration_margin[i][j] = bw_min2(data->blackout_duration_margin[i][j], bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->line_source_transfer_time[k][i][j]));
-+						data->dispclk_required_for_blackout_duration[i][j] = bw_max3(data->dispclk_required_for_blackout_duration[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->active_time[k]))));
-+						if (bw_leq(vbios->maximum_blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j]))) {
-+							data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(9999);
-+						}
-+						else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) {
-+							data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, bw_sub(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k]));
-+						}
-+					}
-+					else {
-+						data->blackout_duration_margin[i][j] = bw_min2(data->blackout_duration_margin[i][j], bw_sub(bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->line_source_transfer_time[k][i][j]));
-+						data->dispclk_required_for_blackout_duration[i][j] = bw_max3(data->dispclk_required_for_blackout_duration[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->active_time[k]))));
-+						if (bw_ltn(vbios->maximum_blackout_recovery_time, bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]))) {
-+							data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(9999);
-+						}
-+						else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) {
-+							data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, (bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j]))))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k]));
-+						}
-+					}
-+				}
-+			}
-+		}
-+	}
-+	if (bw_mtn(data->blackout_duration_margin[high][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[high][s_high], vbios->high_voltage_max_dispclk)) {
-+		data->cpup_state_change_enable = bw_def_yes;
-+		if (bw_ltn(data->dispclk_required_for_blackout_recovery[high][s_high], vbios->high_voltage_max_dispclk)) {
-+			data->cpuc_state_change_enable = bw_def_yes;
-+		}
-+		else {
-+			data->cpuc_state_change_enable = bw_def_no;
-+		}
-+	}
-+	else {
-+		data->cpup_state_change_enable = bw_def_no;
-+		data->cpuc_state_change_enable = bw_def_no;
-+	}
-+	/*nb p-state change enable*/
-+	/*for dram speed/p-state change to be possible for a yclk(pclk) and sclk level there has to be positive margin and the dispclk required has to be*/
-+	/*below the maximum.*/
-+	/*the dram speed/p-state change margin is the minimum for all surfaces of the maximum latency hiding minus the dram speed/p-state change latency,*/
-+	/*minus the dmif burst time, minus the source line transfer time*/
-+	/*the maximum latency hiding is the minimum latency hiding plus one source line used for de-tiling in the line buffer, plus half the urgent latency*/
-+	/*if stutter and dram clock state change are gated before cursor then the cursor latency hiding does not limit stutter or dram clock state change*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if ((dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1)) {
-+				data->maximum_latency_hiding[i] = bw_add(data->minimum_latency_hiding[i], bw_mul(bw_frc_to_fixed(8, 10), data->total_dmifmc_urgent_latency));
-+			}
-+			else {
-+				/*maximum_latency_hiding(i) = minimum_latency_hiding(i) + 1 / vsr(i) * h_total(i) / pixel_rate(i) + 0.5 * total_dmifmc_urgent_latency*/
-+				data->maximum_latency_hiding[i] = bw_add(data->minimum_latency_hiding[i], bw_mul(bw_frc_to_fixed(8, 10), data->total_dmifmc_urgent_latency));
-+			}
-+			data->maximum_latency_hiding_with_cursor[i] = bw_min2(data->maximum_latency_hiding[i], data->cursor_latency_hiding[i]);
-+		}
-+	}
-+	/*initialize variables*/
-+	number_of_displays_enabled = 0;
-+	number_of_displays_enabled_with_margin = 0;
-+	for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
-+		if (data->enable[k]) {
-+			number_of_displays_enabled = number_of_displays_enabled + 1;
-+		}
-+		data->display_pstate_change_enable[k] = 0;
-+	}
-+	for (i = 0; i <= 2; i++) {
-+		for (j = 0; j <= 7; j++) {
-+			data->min_dram_speed_change_margin[i][j] = bw_int_to_fixed(9999);
-+			data->dram_speed_change_margin = bw_int_to_fixed(9999);
-+			data->dispclk_required_for_dram_speed_change[i][j] = bw_int_to_fixed(0);
-+			data->num_displays_with_margin[i][j] = 0;
-+			for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
-+				if (data->enable[k]) {
-+					if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
-+						data->dram_speed_change_margin = bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]);
-+						if ((bw_mtn(data->dram_speed_change_margin, bw_int_to_fixed(0)) && bw_ltn(data->dram_speed_change_margin, bw_int_to_fixed(9999)))) {
-+							/*determine the minimum dram clock change margin for each set of clock frequencies*/
-+							data->min_dram_speed_change_margin[i][j] = bw_min2(data->min_dram_speed_change_margin[i][j], data->dram_speed_change_margin);
-+							/*compute the maximum clock frequuency required for the dram clock change at each set of clock frequencies*/
-+							data->dispclk_required_for_dram_speed_change[i][j] = bw_max3(data->dispclk_required_for_dram_speed_change[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->active_time[k]))));
-+							if ((bw_ltn(data->dispclk_required_for_dram_speed_change[i][j], vbios->high_voltage_max_dispclk))) {
-+								data->display_pstate_change_enable[k] = 1;
-+								data->num_displays_with_margin[i][j] = data->num_displays_with_margin[i][j] + 1;
-+							}
-+						}
-+					}
-+					else {
-+						data->dram_speed_change_margin = bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]);
-+						if ((bw_mtn(data->dram_speed_change_margin, bw_int_to_fixed(0)) && bw_ltn(data->dram_speed_change_margin, bw_int_to_fixed(9999)))) {
-+							/*determine the minimum dram clock change margin for each display pipe*/
-+							data->min_dram_speed_change_margin[i][j] = bw_min2(data->min_dram_speed_change_margin[i][j], data->dram_speed_change_margin);
-+							/*compute the maximum clock frequuency required for the dram clock change at each set of clock frequencies*/
-+							data->dispclk_required_for_dram_speed_change[i][j] = bw_max3(data->dispclk_required_for_dram_speed_change[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]), data->active_time[k]))));
-+							if ((bw_ltn(data->dispclk_required_for_dram_speed_change[i][j], vbios->high_voltage_max_dispclk))) {
-+								data->display_pstate_change_enable[k] = 1;
-+								data->num_displays_with_margin[i][j] = data->num_displays_with_margin[i][j] + 1;
-+							}
-+						}
-+					}
-+				}
-+			}
-+		}
-+	}
-+	/*determine the number of displays with margin to switch in the v_active region*/
-+	for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
-+		if ((data->enable[k] == 1 && data->display_pstate_change_enable[k] == 1)) {
-+			number_of_displays_enabled_with_margin = number_of_displays_enabled_with_margin + 1;
-+		}
-+	}
-+	/*determine the number of displays that don't have any dram clock change margin, but*/
-+	/*have the same resolution.  these displays can switch in a common vblank region if*/
-+	/*their frames are aligned.*/
-+	data->min_vblank_dram_speed_change_margin = bw_int_to_fixed(9999);
-+	for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
-+		if (data->enable[k]) {
-+			if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
-+				data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
-+				data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]);
-+			}
-+			else {
-+				data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->mcifwr_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
-+				data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]);
-+			}
-+		}
-+	}
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		data->displays_with_same_mode[i] = bw_int_to_fixed(0);
-+		if (data->enable[i] == 1 && data->display_pstate_change_enable[i] == 0 && bw_mtn(data->v_blank_dram_speed_change_margin[i], bw_int_to_fixed(0))) {
-+			for (j = 0; j <= maximum_number_of_surfaces - 1; j++) {
-+				if ((data->enable[j] == 1 && bw_equ(data->source_width_rounded_up_to_chunks[i], data->source_width_rounded_up_to_chunks[j]) && bw_equ(data->source_height_rounded_up_to_chunks[i], data->source_height_rounded_up_to_chunks[j]) && bw_equ(data->vsr[i], data->vsr[j]) && bw_equ(data->hsr[i], data->hsr[j]) && bw_equ(data->pixel_rate[i], data->pixel_rate[j]))) {
-+					data->displays_with_same_mode[i] = bw_add(data->displays_with_same_mode[i], bw_int_to_fixed(1));
-+				}
-+			}
-+		}
-+	}
-+	/*compute the maximum number of aligned displays with no margin*/
-+	number_of_aligned_displays_with_no_margin = 0;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		number_of_aligned_displays_with_no_margin = bw_fixed_to_int(bw_max2(bw_int_to_fixed(number_of_aligned_displays_with_no_margin), data->displays_with_same_mode[i]));
-+	}
-+	/*dram clock change is possible, if all displays have positive margin except for one display or a group of*/
-+	/*aligned displays with the same timing.*/
-+	/*the display(s) with the negative margin can be switched in the v_blank region while the other*/
-+	/*displays are in v_blank or v_active.*/
-+	if ((number_of_displays_enabled_with_margin + number_of_aligned_displays_with_no_margin == number_of_displays_enabled && bw_mtn(data->min_dram_speed_change_margin[high][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[high][s_high], bw_int_to_fixed(9999)) && bw_ltn(data->dispclk_required_for_dram_speed_change[high][s_high], vbios->high_voltage_max_dispclk))) {
-+		data->nbp_state_change_enable = bw_def_yes;
-+	}
-+	else {
-+		data->nbp_state_change_enable = bw_def_no;
-+	}
-+	/*dram clock change is possible only in vblank if all displays are aligned and have no margin*/
-+	if ((number_of_aligned_displays_with_no_margin == number_of_displays_enabled)) {
-+		nbp_state_change_enable_blank = bw_def_yes;
-+	}
-+	else {
-+		nbp_state_change_enable_blank = bw_def_no;
-+	}
-+	/*required yclk(pclk)*/
-+	/*yclk requirement only makes sense if the dmif and mcifwr data total page close-open time is less than the time for data transfer and the total pte requests fit in the scatter-gather saw queque size*/
-+	/*if that is the case, the yclk requirement is the maximum of the ones required by dmif and mcifwr, and the high/low yclk(pclk) is chosen accordingly*/
-+	/*high yclk(pclk) has to be selected when dram speed/p-state change is not possible.*/
-+	data->min_cursor_memory_interface_buffer_size_in_time = bw_int_to_fixed(9999);
-+	/* number of cursor lines stored in the cursor data return buffer*/
-+	num_cursor_lines = 0;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (bw_mtn(data->cursor_width_pixels[i], bw_int_to_fixed(0))) {
-+				/*compute number of cursor lines stored in data return buffer*/
-+				if (bw_leq(data->cursor_width_pixels[i], bw_int_to_fixed(64)) && dceip->large_cursor == 1) {
-+					num_cursor_lines = 4;
-+				}
-+				else {
-+					num_cursor_lines = 2;
-+				}
-+				data->min_cursor_memory_interface_buffer_size_in_time = bw_min2(data->min_cursor_memory_interface_buffer_size_in_time, bw_div(bw_mul(bw_div(bw_int_to_fixed(num_cursor_lines), data->vsr[i]), data->h_total[i]), data->pixel_rate[i]));
-+			}
-+		}
-+	}
-+	/*compute minimum time to read one chunk from the dmif buffer*/
-+	if ((number_of_displays_enabled > 2)) {
-+		data->chunk_request_delay = 0;
-+	}
-+	else {
-+		data->chunk_request_delay = bw_fixed_to_int(bw_div(bw_int_to_fixed(512), vbios->high_voltage_max_dispclk));
-+	}
-+	data->min_read_buffer_size_in_time = bw_min2(data->min_cursor_memory_interface_buffer_size_in_time, data->min_dmif_size_in_time);
-+	data->display_reads_time_for_data_transfer = bw_sub(bw_sub(data->min_read_buffer_size_in_time, data->total_dmifmc_urgent_latency), bw_int_to_fixed(data->chunk_request_delay));
-+	data->display_writes_time_for_data_transfer = bw_sub(data->min_mcifwr_size_in_time, vbios->mcifwrmc_urgent_latency);
-+	data->dmif_required_dram_bandwidth = bw_div(data->total_display_reads_required_dram_access_data, data->display_reads_time_for_data_transfer);
-+	data->mcifwr_required_dram_bandwidth = bw_div(data->total_display_writes_required_dram_access_data, data->display_writes_time_for_data_transfer);
-+	data->required_dmifmc_urgent_latency_for_page_close_open = bw_div((bw_sub(data->min_read_buffer_size_in_time, data->dmif_total_page_close_open_time)), data->total_dmifmc_urgent_trips);
-+	data->required_mcifmcwr_urgent_latency = bw_sub(data->min_mcifwr_size_in_time, data->mcifwr_total_page_close_open_time);
-+	if (bw_mtn(data->scatter_gather_total_pte_requests, dceip->maximum_total_outstanding_pte_requests_allowed_by_saw)) {
-+		data->required_dram_bandwidth_gbyte_per_second = bw_int_to_fixed(9999);
-+		yclk_message = bw_def_exceeded_allowed_outstanding_pte_req_queue_size;
-+		data->y_clk_level = high;
-+		data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
-+	}
-+	else if (bw_mtn(vbios->dmifmc_urgent_latency, data->required_dmifmc_urgent_latency_for_page_close_open) || bw_mtn(vbios->mcifwrmc_urgent_latency, data->required_mcifmcwr_urgent_latency)) {
-+		data->required_dram_bandwidth_gbyte_per_second = bw_int_to_fixed(9999);
-+		yclk_message = bw_def_exceeded_allowed_page_close_open;
-+		data->y_clk_level = high;
-+		data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
-+	}
-+	else {
-+		data->required_dram_bandwidth_gbyte_per_second = bw_div(bw_max2(data->dmif_required_dram_bandwidth, data->mcifwr_required_dram_bandwidth), bw_int_to_fixed(1000));
-+		if (bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[low]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels))) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[low][s_high], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[low][s_high], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[low][s_high], vbios->high_voltage_max_dispclk))) && (data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[low][s_high], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[low][s_high], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[low][s_high] == number_of_displays_enabled_with_margin))) {
-+			yclk_message = bw_fixed_to_int(vbios->low_yclk);
-+			data->y_clk_level = low;
-+			data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[low]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
-+		}
-+		else if (bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[mid]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels))) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[mid][s_high], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[mid][s_high], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[mid][s_high], vbios->high_voltage_max_dispclk))) && (data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[mid][s_high], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[mid][s_high], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[mid][s_high] == number_of_displays_enabled_with_margin))) {
-+			yclk_message = bw_fixed_to_int(vbios->mid_yclk);
-+			data->y_clk_level = mid;
-+			data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[mid]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
-+		}
-+		else if (bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels)))) {
-+			yclk_message = bw_fixed_to_int(vbios->high_yclk);
-+			data->y_clk_level = high;
-+			data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
-+		}
-+		else {
-+			yclk_message = bw_def_exceeded_allowed_maximum_bw;
-+			data->y_clk_level = high;
-+			data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
-+		}
-+	}
-+	/*required sclk*/
-+	/*sclk requirement only makes sense if the total pte requests fit in the scatter-gather saw queque size*/
-+	/*if that is the case, the sclk requirement is the maximum of the ones required by dmif and mcifwr, and the high/mid/low sclk is chosen accordingly, unless that choice results in foresaking dram speed/nb p-state change.*/
-+	/*the dmif and mcifwr sclk required is the one that allows the transfer of all pipe's data buffer size through the sclk bus in the time for data transfer*/
-+	/*for dmif, pte and cursor requests have to be included.*/
-+	data->dmif_required_sclk = bw_div(bw_div(data->total_display_reads_required_data, data->display_reads_time_for_data_transfer), (bw_mul(vbios->data_return_bus_width, bw_int_to_fixed(bus_efficiency))));
-+	data->mcifwr_required_sclk = bw_div(bw_div(data->total_display_writes_required_data, data->display_writes_time_for_data_transfer), (bw_mul(vbios->data_return_bus_width, bw_int_to_fixed(bus_efficiency))));
-+	if (bw_mtn(data->scatter_gather_total_pte_requests, dceip->maximum_total_outstanding_pte_requests_allowed_by_saw)) {
-+		data->required_sclk = bw_int_to_fixed(9999);
-+		sclk_message = bw_def_exceeded_allowed_outstanding_pte_req_queue_size;
-+		data->sclk_level = s_high;
-+	}
-+	else if (bw_mtn(vbios->dmifmc_urgent_latency, data->required_dmifmc_urgent_latency_for_page_close_open) || bw_mtn(vbios->mcifwrmc_urgent_latency, data->required_mcifmcwr_urgent_latency)) {
-+		data->required_sclk = bw_int_to_fixed(9999);
-+		sclk_message = bw_def_exceeded_allowed_page_close_open;
-+		data->sclk_level = s_high;
-+	}
-+	else {
-+		data->required_sclk = bw_max2(data->dmif_required_sclk, data->mcifwr_required_sclk);
-+		if (bw_ltn(data->required_sclk, sclk[s_low]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk))) && (data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_low], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_low], vbios->low_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_low] == number_of_displays_enabled_with_margin))) {
-+			sclk_message = bw_def_low;
-+			data->sclk_level = s_low;
-+			data->required_sclk = vbios->low_sclk;
-+		}
-+		else if (bw_ltn(data->required_sclk, sclk[s_mid1]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk))) && (data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid1], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid1] == number_of_displays_enabled_with_margin))) {
-+			sclk_message = bw_def_mid;
-+			data->sclk_level = s_mid1;
-+			data->required_sclk = vbios->mid1_sclk;
-+		}
-+		else if (bw_ltn(data->required_sclk, sclk[s_mid2]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk))) && (data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid2], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid2] == number_of_displays_enabled_with_margin))) {
-+			sclk_message = bw_def_mid;
-+			data->sclk_level = s_mid2;
-+			data->required_sclk = vbios->mid2_sclk;
-+		}
-+		else if (bw_ltn(data->required_sclk, sclk[s_mid3]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk))) && (data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid3], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid3] == number_of_displays_enabled_with_margin))) {
-+			sclk_message = bw_def_mid;
-+			data->sclk_level = s_mid3;
-+			data->required_sclk = vbios->mid3_sclk;
-+		}
-+		else if (bw_ltn(data->required_sclk, sclk[s_mid4]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk))) && (data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid4], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid4] == number_of_displays_enabled_with_margin))) {
-+			sclk_message = bw_def_mid;
-+			data->sclk_level = s_mid4;
-+			data->required_sclk = vbios->mid4_sclk;
-+		}
-+		else if (bw_ltn(data->required_sclk, sclk[s_mid5]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk))) && (data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid5], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid5] == number_of_displays_enabled_with_margin))) {
-+			sclk_message = bw_def_mid;
-+			data->sclk_level = s_mid5;
-+			data->required_sclk = vbios->mid5_sclk;
-+		}
-+		else if (bw_ltn(data->required_sclk, sclk[s_mid6]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk))) && (data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid6] == number_of_displays_enabled_with_margin))) {
-+			sclk_message = bw_def_mid;
-+			data->sclk_level = s_mid6;
-+			data->required_sclk = vbios->mid6_sclk;
-+		}
-+		else if (bw_ltn(data->required_sclk, sclk[s_high])) {
-+			sclk_message = bw_def_high;
-+			data->sclk_level = s_high;
-+			data->required_sclk = vbios->high_sclk;
-+		}
-+		else {
-+			sclk_message = bw_def_exceeded_allowed_maximum_sclk;
-+			data->sclk_level = s_high;
-+			/*required_sclk = high_sclk*/
-+		}
-+	}
-+	/*dispclk*/
-+	/*if dispclk is set to the maximum, ramping is not required.  dispclk required without ramping is less than the dispclk required with ramping.*/
-+	/*if dispclk required without ramping is more than the maximum dispclk, that is the dispclk required, and the mode is not supported*/
-+	/*if that does not happen, but dispclk required with ramping is more than the maximum dispclk, dispclk required is just the maximum dispclk*/
-+	/*if that does not happen either, dispclk required is the dispclk required with ramping.*/
-+	/*dispclk required without ramping is the maximum of the one required for display pipe pixel throughput, for scaler throughput, for total read request thrrougput and for dram/np p-state change if enabled.*/
-+	/*the display pipe pixel throughput is the maximum of lines in per line out in the beginning of the frame and lines in per line out in the middle of the frame multiplied by the horizontal blank and chunk granularity factor, altogether multiplied by the ratio of the source width to the line time, divided by the line buffer pixels per dispclk throughput, and multiplied by the display pipe throughput factor.*/
-+	/*the horizontal blank and chunk granularity factor is the ratio of the line time divided by the line time minus half the horizontal blank and chunk time.  it applies when the lines in per line out is not 2 or 4.*/
-+	/*the dispclk required for scaler throughput is the product of the pixel rate and the scaling limits factor.*/
-+	/*the dispclk required for total read request throughput is the product of the peak request-per-second bandwidth and the dispclk cycles per request, divided by the request efficiency.*/
-+	/*for the dispclk required with ramping, instead of multiplying just the pipe throughput by the display pipe throughput factor, we multiply the scaler and pipe throughput by the ramping factor.*/
-+	/*the scaling limits factor is the product of the horizontal scale ratio, and the ratio of the vertical taps divided by the scaler efficiency clamped to at least 1.*/
-+	/*the scaling limits factor itself it also clamped to at least 1*/
-+	/*if doing downscaling with the pre-downscaler enabled, the horizontal scale ratio should not be considered above (use "1")*/
-+	data->downspread_factor = bw_add(bw_int_to_fixed(1), bw_div(vbios->down_spread_percentage, bw_int_to_fixed(100)));
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (surface_type[i] == bw_def_graphics) {
-+				switch (data->lb_bpc[i]) {
-+				case 6:
-+					data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency6_bit_per_component;
-+					break;
-+				case 8:
-+					data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency8_bit_per_component;
-+					break;
-+				case 10:
-+					data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency10_bit_per_component;
-+					break;
-+				default:
-+					data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency12_bit_per_component;
-+					break;
-+				}
-+				if (data->use_alpha[i] == 1) {
-+					data->v_scaler_efficiency = bw_min2(data->v_scaler_efficiency, dceip->alpha_vscaler_efficiency);
-+				}
-+			}
-+			else {
-+				switch (data->lb_bpc[i]) {
-+				case 6:
-+					data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency6_bit_per_component;
-+					break;
-+				case 8:
-+					data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency8_bit_per_component;
-+					break;
-+				case 10:
-+					data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency10_bit_per_component;
-+					break;
-+				default:
-+					data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency12_bit_per_component;
-+					break;
-+				}
-+			}
-+			if (dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1))) {
-+				data->scaler_limits_factor = bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_div(data->source_width_rounded_up_to_chunks[i], data->h_total[i]));
-+			}
-+			else {
-+				data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1))));
-+			}
-+			data->display_pipe_pixel_throughput = bw_div(bw_div(bw_mul(bw_max2(data->lb_lines_in_per_line_out_in_beginning_of_frame[i], bw_mul(data->lb_lines_in_per_line_out_in_middle_of_frame[i], data->horizontal_blank_and_chunk_granularity_factor[i])), data->source_width_rounded_up_to_chunks[i]), (bw_div(data->h_total[i], data->pixel_rate[i]))), dceip->lb_write_pixels_per_dispclk);
-+			data->dispclk_required_without_ramping[i] = bw_mul(data->downspread_factor, bw_max2(bw_mul(data->pixel_rate[i], data->scaler_limits_factor), bw_mul(dceip->display_pipe_throughput_factor, data->display_pipe_pixel_throughput)));
-+			data->dispclk_required_with_ramping[i] = bw_mul(dceip->dispclk_ramping_factor, bw_max2(bw_mul(data->pixel_rate[i], data->scaler_limits_factor), data->display_pipe_pixel_throughput));
-+		}
-+	}
-+	data->total_dispclk_required_with_ramping = bw_int_to_fixed(0);
-+	data->total_dispclk_required_without_ramping = bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (bw_ltn(data->total_dispclk_required_with_ramping, data->dispclk_required_with_ramping[i])) {
-+				data->total_dispclk_required_with_ramping = data->dispclk_required_with_ramping[i];
-+			}
-+			if (bw_ltn(data->total_dispclk_required_without_ramping, data->dispclk_required_without_ramping[i])) {
-+				data->total_dispclk_required_without_ramping = data->dispclk_required_without_ramping[i];
-+			}
-+		}
-+	}
-+	data->total_read_request_bandwidth = bw_int_to_fixed(0);
-+	data->total_write_request_bandwidth = bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
-+				data->total_read_request_bandwidth = bw_add(data->total_read_request_bandwidth, data->request_bandwidth[i]);
-+			}
-+			else {
-+				data->total_write_request_bandwidth = bw_add(data->total_write_request_bandwidth, data->request_bandwidth[i]);
-+			}
-+		}
-+	}
-+	data->dispclk_required_for_total_read_request_bandwidth = bw_div(bw_mul(data->total_read_request_bandwidth, dceip->dispclk_per_request), dceip->request_efficiency);
-+	data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_with_ramping, data->dispclk_required_for_total_read_request_bandwidth);
-+	data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_without_ramping, data->dispclk_required_for_total_read_request_bandwidth);
-+	if (data->cpuc_state_change_enable == bw_def_yes) {
-+		data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max3(data->total_dispclk_required_with_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level], data->dispclk_required_for_blackout_recovery[data->y_clk_level][data->sclk_level]);
-+		data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max3(data->total_dispclk_required_without_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level], data->dispclk_required_for_blackout_recovery[data->y_clk_level][data->sclk_level]);
-+	}
-+	if (data->cpup_state_change_enable == bw_def_yes) {
-+		data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_with_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level]);
-+		data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_without_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level]);
-+	}
-+	if (data->nbp_state_change_enable == bw_def_yes) {
-+		data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_with_ramping_with_request_bandwidth, data->dispclk_required_for_dram_speed_change[data->y_clk_level][data->sclk_level]);
-+		data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_without_ramping_with_request_bandwidth, data->dispclk_required_for_dram_speed_change[data->y_clk_level][data->sclk_level]);
-+	}
-+	if (bw_ltn(data->total_dispclk_required_with_ramping_with_request_bandwidth, vbios->high_voltage_max_dispclk)) {
-+		data->dispclk = data->total_dispclk_required_with_ramping_with_request_bandwidth;
-+	}
-+	else if (bw_ltn(data->total_dispclk_required_without_ramping_with_request_bandwidth, vbios->high_voltage_max_dispclk)) {
-+		data->dispclk = vbios->high_voltage_max_dispclk;
-+	}
-+	else {
-+		data->dispclk = data->total_dispclk_required_without_ramping_with_request_bandwidth;
-+	}
-+	/* required core voltage*/
-+	/* the core voltage required is low if sclk, yclk(pclk)and dispclk are within the low limits*/
-+	/* otherwise, the core voltage required is medium if yclk (pclk) is within the low limit and sclk and dispclk are within the medium limit*/
-+	/* otherwise, the core voltage required is high if the three clocks are within the high limits*/
-+	/* otherwise, or if the mode is not supported, core voltage requirement is not applicable*/
-+	if (pipe_check == bw_def_notok) {
-+		voltage = bw_def_na;
-+	}
-+	else if (mode_check == bw_def_notok) {
-+		voltage = bw_def_notok;
-+	}
-+	else if (bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) && sclk_message == bw_def_low && bw_ltn(data->dispclk, vbios->low_voltage_max_dispclk)) {
-+		voltage = bw_def_0_72;
-+	}
-+	else if ((bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->mid_yclk)) && (sclk_message == bw_def_low || sclk_message == bw_def_mid) && bw_ltn(data->dispclk, vbios->mid_voltage_max_dispclk)) {
-+		voltage = bw_def_0_8;
-+	}
-+	else if ((bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->mid_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->high_yclk)) && (sclk_message == bw_def_low || sclk_message == bw_def_mid || sclk_message == bw_def_high) && bw_leq(data->dispclk, vbios->high_voltage_max_dispclk)) {
-+		if ((data->nbp_state_change_enable == bw_def_no && nbp_state_change_enable_blank == bw_def_no)) {
-+			voltage = bw_def_high_no_nbp_state_change;
-+		}
-+		else {
-+			voltage = bw_def_0_9;
-+		}
-+	}
-+	else {
-+		voltage = bw_def_notok;
-+	}
-+	if (voltage == bw_def_0_72) {
-+		data->max_phyclk = vbios->low_voltage_max_phyclk;
-+	}
-+	else if (voltage == bw_def_0_8) {
-+		data->max_phyclk = vbios->mid_voltage_max_phyclk;
-+	}
-+	else {
-+		data->max_phyclk = vbios->high_voltage_max_phyclk;
-+	}
-+	/*required blackout recovery time*/
-+	data->blackout_recovery_time = bw_int_to_fixed(0);
-+	for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
-+		if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0)) && data->cpup_state_change_enable == bw_def_yes) {
-+			if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
-+				data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level]));
-+				if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])))))) {
-+					data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k])))));
-+				}
-+			}
-+			else {
-+				data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level]));
-+				if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])))))) {
-+					data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level]), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k])))));
-+				}
-+			}
-+		}
-+	}
-+	/*sclk deep sleep*/
-+	/*during self-refresh, sclk can be reduced to dispclk divided by the minimum pixels in the data fifo entry, with 15% margin, but shoudl not be set to less than the request bandwidth.*/
-+	/*the data fifo entry is 16 pixels for the writeback, 64 bytes/bytes_per_pixel for the graphics, 16 pixels for the parallel rotation underlay,*/
-+	/*and 16 bytes/bytes_per_pixel for the orthogonal rotation underlay.*/
-+	/*in parallel mode (underlay pipe), the data read from the dmifv buffer is variable and based on the pixel depth (8bbp - 16 bytes, 16 bpp - 32 bytes, 32 bpp - 64 bytes)*/
-+	/*in orthogonal mode (underlay pipe), the data read from the dmifv buffer is fixed at 16 bytes.*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (surface_type[i] == bw_def_display_write_back420_luma || surface_type[i] == bw_def_display_write_back420_chroma) {
-+				data->pixels_per_data_fifo_entry[i] = bw_int_to_fixed(16);
-+			}
-+			else if (surface_type[i] == bw_def_graphics) {
-+				data->pixels_per_data_fifo_entry[i] = bw_div(bw_int_to_fixed(64), bw_int_to_fixed(data->bytes_per_pixel[i]));
-+			}
-+			else if (data->orthogonal_rotation[i] == 0) {
-+				data->pixels_per_data_fifo_entry[i] = bw_int_to_fixed(16);
-+			}
-+			else {
-+				data->pixels_per_data_fifo_entry[i] = bw_div(bw_int_to_fixed(16), bw_int_to_fixed(data->bytes_per_pixel[i]));
-+			}
-+		}
-+	}
-+	data->min_pixels_per_data_fifo_entry = bw_int_to_fixed(9999);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (bw_mtn(data->min_pixels_per_data_fifo_entry, data->pixels_per_data_fifo_entry[i])) {
-+				data->min_pixels_per_data_fifo_entry = data->pixels_per_data_fifo_entry[i];
-+			}
-+		}
-+	}
-+	data->sclk_deep_sleep = bw_max2(bw_div(bw_mul(data->dispclk, bw_frc_to_fixed(115, 100)), data->min_pixels_per_data_fifo_entry), data->total_read_request_bandwidth);
-+	/*urgent, stutter and nb-p_state watermark*/
-+	/*the urgent watermark is the maximum of the urgent trip time plus the pixel transfer time, the urgent trip times to get data for the first pixel, and the urgent trip times to get data for the last pixel.*/
-+	/*the stutter exit watermark is the self refresh exit time plus the maximum of the data burst time plus the pixel transfer time, the data burst times to get data for the first pixel, and the data burst times to get data for the last pixel.  it does not apply to the writeback.*/
-+	/*the nb p-state change watermark is the dram speed/p-state change time plus the maximum of the data burst time plus the pixel transfer time, the data burst times to get data for the first pixel, and the data burst times to get data for the last pixel.*/
-+	/*the pixel transfer time is the maximum of the time to transfer the source pixels required for the first output pixel, and the time to transfer the pixels for the last output pixel minus the active line time.*/
-+	/*blackout_duration is added to the urgent watermark*/
-+	data->chunk_request_time = bw_int_to_fixed(0);
-+	data->cursor_request_time = bw_int_to_fixed(0);
-+	/*compute total time to request one chunk from each active display pipe*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			data->chunk_request_time = bw_add(data->chunk_request_time, (bw_div((bw_div(bw_int_to_fixed(pixels_per_chunk * data->bytes_per_pixel[i]), data->useful_bytes_per_request[i])), bw_min2(sclk[data->sclk_level], bw_div(data->dispclk, bw_int_to_fixed(2))))));
-+		}
-+	}
-+	/*compute total time to request cursor data*/
-+	data->cursor_request_time = (bw_div(data->cursor_total_data, (bw_mul(bw_int_to_fixed(32), sclk[data->sclk_level]))));
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			data->line_source_pixels_transfer_time = bw_max2(bw_div(bw_div(data->src_pixels_for_first_output_pixel[i], dceip->lb_write_pixels_per_dispclk), (bw_div(data->dispclk, dceip->display_pipe_throughput_factor))), bw_sub(bw_div(bw_div(data->src_pixels_for_last_output_pixel[i], dceip->lb_write_pixels_per_dispclk), (bw_div(data->dispclk, dceip->display_pipe_throughput_factor))), data->active_time[i]));
-+			if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
-+				data->urgent_watermark[i] = bw_add(bw_add(bw_add(bw_add(bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->line_source_transfer_time[i][data->y_clk_level][data->sclk_level])), vbios->blackout_duration), data->chunk_request_time), data->cursor_request_time);
-+				data->stutter_exit_watermark[i] = bw_add(bw_sub(vbios->stutter_self_refresh_exit_latency, data->total_dmifmc_urgent_latency), data->urgent_watermark[i]);
-+				data->stutter_entry_watermark[i] = bw_add(bw_sub(bw_add(vbios->stutter_self_refresh_exit_latency, vbios->stutter_self_refresh_entry_latency), data->total_dmifmc_urgent_latency), data->urgent_watermark[i]);
-+				/*unconditionally remove black out time from the nb p_state watermark*/
-+				if ((data->display_pstate_change_enable[i] == 1)) {
-+					data->nbp_state_change_watermark[i] = bw_add(bw_add(vbios->nbp_state_change_latency, data->dmif_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->dram_speed_change_line_source_transfer_time[i][data->y_clk_level][data->sclk_level]));
-+				}
-+				else {
-+					/*maximize the watermark to force the switch in the vb_lank region of the frame*/
-+					data->nbp_state_change_watermark[i] = bw_int_to_fixed(131000);
-+				}
-+			}
-+			else {
-+				data->urgent_watermark[i] = bw_add(bw_add(bw_add(bw_add(bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->line_source_transfer_time[i][data->y_clk_level][data->sclk_level])), vbios->blackout_duration), data->chunk_request_time), data->cursor_request_time);
-+				data->stutter_exit_watermark[i] = bw_int_to_fixed(0);
-+				data->stutter_entry_watermark[i] = bw_int_to_fixed(0);
-+				if ((data->display_pstate_change_enable[i] == 1)) {
-+					data->nbp_state_change_watermark[i] = bw_add(bw_add(vbios->nbp_state_change_latency, data->mcifwr_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->dram_speed_change_line_source_transfer_time[i][data->y_clk_level][data->sclk_level]));
-+				}
-+				else {
-+					/*maximize the watermark to force the switch in the vb_lank region of the frame*/
-+					data->nbp_state_change_watermark[i] = bw_int_to_fixed(131000);
-+				}
-+			}
-+		}
-+	}
-+	/*stutter mode enable*/
-+	/*in the multi-display case the stutter exit or entry watermark cannot exceed the minimum latency hiding capabilities of the*/
-+	/*display pipe.*/
-+	data->stutter_mode_enable = data->cpuc_state_change_enable;
-+	if (data->number_of_displays > 1) {
-+		for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+			if (data->enable[i]) {
-+				if ((bw_mtn(data->stutter_exit_watermark[i], data->minimum_latency_hiding[i]) || bw_mtn(data->stutter_entry_watermark[i], data->minimum_latency_hiding[i]))) {
-+					data->stutter_mode_enable = bw_def_no;
-+				}
-+			}
-+		}
-+	}
-+	/*performance metrics*/
-+	/* display read access efficiency (%)*/
-+	/* display write back access efficiency (%)*/
-+	/* stutter efficiency (%)*/
-+	/* extra underlay pitch recommended for efficiency (pixels)*/
-+	/* immediate flip time (us)*/
-+	/* latency for other clients due to urgent display read (us)*/
-+	/* latency for other clients due to urgent display write (us)*/
-+	/* average bandwidth consumed by display (no compression) (gb/s)*/
-+	/* required dram  bandwidth (gb/s)*/
-+	/* required sclk (m_hz)*/
-+	/* required rd urgent latency (us)*/
-+	/* nb p-state change margin (us)*/
-+	/*dmif and mcifwr dram access efficiency*/
-+	/*is the ratio between the ideal dram access time (which is the data buffer size in memory divided by the dram bandwidth), and the actual time which is the total page close-open time.  but it cannot exceed the dram efficiency provided by the memory subsystem*/
-+	data->dmifdram_access_efficiency = bw_min2(bw_div(bw_div(data->total_display_reads_required_dram_access_data, data->dram_bandwidth), data->dmif_total_page_close_open_time), bw_int_to_fixed(1));
-+	if (bw_mtn(data->total_display_writes_required_dram_access_data, bw_int_to_fixed(0))) {
-+		data->mcifwrdram_access_efficiency = bw_min2(bw_div(bw_div(data->total_display_writes_required_dram_access_data, data->dram_bandwidth), data->mcifwr_total_page_close_open_time), bw_int_to_fixed(1));
-+	}
-+	else {
-+		data->mcifwrdram_access_efficiency = bw_int_to_fixed(0);
-+	}
-+	/*average bandwidth*/
-+	/*the average bandwidth with no compression is the vertical active time is the source width times the bytes per pixel divided by the line time, multiplied by the vertical scale ratio and the ratio of bytes per request divided by the useful bytes per request.*/
-+	/*the average bandwidth with compression is the same, divided by the compression ratio*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			data->average_bandwidth_no_compression[i] = bw_div(bw_mul(bw_mul(bw_div(bw_mul(data->source_width_rounded_up_to_chunks[i], bw_int_to_fixed(data->bytes_per_pixel[i])), (bw_div(data->h_total[i], data->pixel_rate[i]))), data->vsr[i]), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
-+			data->average_bandwidth[i] = bw_div(data->average_bandwidth_no_compression[i], data->compression_rate[i]);
-+		}
-+	}
-+	data->total_average_bandwidth_no_compression = bw_int_to_fixed(0);
-+	data->total_average_bandwidth = bw_int_to_fixed(0);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			data->total_average_bandwidth_no_compression = bw_add(data->total_average_bandwidth_no_compression, data->average_bandwidth_no_compression[i]);
-+			data->total_average_bandwidth = bw_add(data->total_average_bandwidth, data->average_bandwidth[i]);
-+		}
-+	}
-+	/*stutter efficiency*/
-+	/*the stutter efficiency is the frame-average time in self-refresh divided by the frame-average stutter cycle duration.  only applies if the display write-back is not enabled.*/
-+	/*the frame-average stutter cycle used is the minimum for all pipes of the frame-average data buffer size in time, times the compression rate*/
-+	/*the frame-average time in self-refresh is the stutter cycle minus the self refresh exit latency and the burst time*/
-+	/*the stutter cycle is the dmif buffer size reduced by the excess of the stutter exit watermark over the lb size in time.*/
-+	/*the burst time is the data needed during the stutter cycle divided by the available bandwidth*/
-+	/*compute the time read all the data from the dmif buffer to the lb (dram refresh period)*/
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			data->stutter_refresh_duration[i] = bw_sub(bw_mul(bw_div(bw_div(bw_mul(bw_div(bw_div(data->adjusted_data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_rounded_up_to_chunks[i]), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]), data->compression_rate[i]), bw_max2(bw_int_to_fixed(0), bw_sub(data->stutter_exit_watermark[i], bw_div(bw_mul((bw_sub(data->lb_partitions[i], bw_int_to_fixed(1))), data->h_total[i]), data->pixel_rate[i]))));
-+			data->stutter_dmif_buffer_size[i] = bw_div(bw_mul(bw_mul(bw_div(bw_mul(bw_mul(data->stutter_refresh_duration[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_rounded_up_to_chunks[i]), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]), data->compression_rate[i]);
-+		}
-+	}
-+	data->min_stutter_refresh_duration = bw_int_to_fixed(9999);
-+	data->total_stutter_dmif_buffer_size = 0;
-+	data->total_bytes_requested = 0;
-+	data->min_stutter_dmif_buffer_size = 9999;
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			if (bw_mtn(data->min_stutter_refresh_duration, data->stutter_refresh_duration[i])) {
-+				data->min_stutter_refresh_duration = data->stutter_refresh_duration[i];
-+				data->total_bytes_requested = bw_fixed_to_int(bw_add(bw_int_to_fixed(data->total_bytes_requested), (bw_mul(bw_mul(data->source_height_rounded_up_to_chunks[i], data->source_width_rounded_up_to_chunks[i]), bw_int_to_fixed(data->bytes_per_pixel[i])))));
-+				data->min_stutter_dmif_buffer_size = bw_fixed_to_int(data->stutter_dmif_buffer_size[i]);
-+			}
-+			data->total_stutter_dmif_buffer_size = bw_fixed_to_int(bw_add(data->stutter_dmif_buffer_size[i], bw_int_to_fixed(data->total_stutter_dmif_buffer_size)));
-+		}
-+	}
-+	data->stutter_burst_time = bw_div(bw_int_to_fixed(data->total_stutter_dmif_buffer_size), bw_min2(bw_mul(data->dram_bandwidth, data->dmifdram_access_efficiency), bw_mul(sclk[data->sclk_level], bw_int_to_fixed(32))));
-+	data->num_stutter_bursts = data->total_bytes_requested / data->min_stutter_dmif_buffer_size;
-+	data->total_stutter_cycle_duration = bw_add(bw_add(data->min_stutter_refresh_duration, vbios->stutter_self_refresh_exit_latency), data->stutter_burst_time);
-+	data->time_in_self_refresh = data->min_stutter_refresh_duration;
-+	if (data->d1_display_write_back_dwb_enable == 1) {
-+		data->stutter_efficiency = bw_int_to_fixed(0);
-+	}
-+	else if (bw_ltn(data->time_in_self_refresh, bw_int_to_fixed(0))) {
-+		data->stutter_efficiency = bw_int_to_fixed(0);
-+	}
-+	else {
-+		/*compute stutter efficiency assuming 60 hz refresh rate*/
-+		data->stutter_efficiency = bw_max2(bw_int_to_fixed(0), bw_mul((bw_sub(bw_int_to_fixed(1), (bw_div(bw_mul((bw_add(vbios->stutter_self_refresh_exit_latency, data->stutter_burst_time)), bw_int_to_fixed(data->num_stutter_bursts)), bw_frc_to_fixed(166666667, 10000))))), bw_int_to_fixed(100)));
-+	}
-+	/*immediate flip time*/
-+	/*if scatter gather is enabled, the immediate flip takes a number of urgent memory trips equivalent to the pte requests in a row divided by the pte request limit.*/
-+	/*otherwise, it may take just one urgenr memory trip*/
-+	data->worst_number_of_trips_to_memory = bw_int_to_fixed(1);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i] && data->scatter_gather_enable_for_pipe[i] == 1) {
-+			data->number_of_trips_to_memory_for_getting_apte_row[i] = bw_ceil2(bw_div(data->scatter_gather_pte_requests_in_row[i], data->scatter_gather_pte_request_limit[i]), bw_int_to_fixed(1));
-+			if (bw_ltn(data->worst_number_of_trips_to_memory, data->number_of_trips_to_memory_for_getting_apte_row[i])) {
-+				data->worst_number_of_trips_to_memory = data->number_of_trips_to_memory_for_getting_apte_row[i];
-+			}
-+		}
-+	}
-+	data->immediate_flip_time = bw_mul(data->worst_number_of_trips_to_memory, data->total_dmifmc_urgent_latency);
-+	/*worst latency for other clients*/
-+	/*it is the urgent latency plus the urgent burst time*/
-+	data->latency_for_non_dmif_clients = bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[data->y_clk_level][data->sclk_level]);
-+	if (data->d1_display_write_back_dwb_enable == 1) {
-+		data->latency_for_non_mcifwr_clients = bw_add(vbios->mcifwrmc_urgent_latency, dceip->mcifwr_all_surfaces_burst_time);
-+	}
-+	else {
-+		data->latency_for_non_mcifwr_clients = bw_int_to_fixed(0);
-+	}
-+	/*dmif mc urgent latency suppported in high sclk and yclk*/
-+	data->dmifmc_urgent_latency_supported_in_high_sclk_and_yclk = bw_div((bw_sub(data->min_read_buffer_size_in_time, data->dmif_burst_time[high][s_high])), data->total_dmifmc_urgent_trips);
-+	/*dram speed/p-state change margin*/
-+	/*in the multi-display case the nb p-state change watermark cannot exceed the average lb size plus the dmif size or the cursor dcp buffer size*/
-+	data->v_blank_nbp_state_dram_speed_change_latency_supported = bw_int_to_fixed(99999);
-+	data->nbp_state_dram_speed_change_latency_supported = bw_int_to_fixed(99999);
-+	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
-+		if (data->enable[i]) {
-+			data->nbp_state_dram_speed_change_latency_supported = bw_min2(data->nbp_state_dram_speed_change_latency_supported, bw_add(bw_sub(data->maximum_latency_hiding_with_cursor[i], data->nbp_state_change_watermark[i]), vbios->nbp_state_change_latency));
-+			data->v_blank_nbp_state_dram_speed_change_latency_supported = bw_min2(data->v_blank_nbp_state_dram_speed_change_latency_supported, bw_add(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[i], bw_sub(bw_div(data->src_height[i], data->v_scale_ratio[i]), bw_int_to_fixed(4)))), data->h_total[i]), data->pixel_rate[i]), data->nbp_state_change_watermark[i]), vbios->nbp_state_change_latency));
-+		}
-+	}
-+	/*sclk required vs urgent latency*/
-+	for (i = 1; i <= 5; i++) {
-+		data->display_reads_time_for_data_transfer_and_urgent_latency = bw_sub(data->min_read_buffer_size_in_time, bw_mul(data->total_dmifmc_urgent_trips, bw_int_to_fixed(i)));
-+		if (pipe_check == bw_def_ok && (bw_mtn(data->display_reads_time_for_data_transfer_and_urgent_latency, data->dmif_total_page_close_open_time))) {
-+			data->dmif_required_sclk_for_urgent_latency[i] = bw_div(bw_div(data->total_display_reads_required_data, data->display_reads_time_for_data_transfer_and_urgent_latency), (bw_mul(vbios->data_return_bus_width, bw_int_to_fixed(bus_efficiency))));
-+		}
-+		else {
-+			data->dmif_required_sclk_for_urgent_latency[i] = bw_int_to_fixed(bw_def_na);
-+		}
-+	}
-+	/*output link bit per pixel supported*/
-+	for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
-+		data->output_bpphdmi[k] = bw_def_na;
-+		data->output_bppdp4_lane_hbr[k] = bw_def_na;
-+		data->output_bppdp4_lane_hbr2[k] = bw_def_na;
-+		data->output_bppdp4_lane_hbr3[k] = bw_def_na;
-+		if (data->enable[k]) {
-+			data->output_bpphdmi[k] = bw_fixed_to_int(bw_mul(bw_div(bw_min2(bw_int_to_fixed(600), data->max_phyclk), data->pixel_rate[k]), bw_int_to_fixed(24)));
-+			if (bw_meq(data->max_phyclk, bw_int_to_fixed(270))) {
-+				data->output_bppdp4_lane_hbr[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(270), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
-+			}
-+			if (bw_meq(data->max_phyclk, bw_int_to_fixed(540))) {
-+				data->output_bppdp4_lane_hbr2[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(540), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
-+			}
-+			if (bw_meq(data->max_phyclk, bw_int_to_fixed(810))) {
-+				data->output_bppdp4_lane_hbr3[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(810), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
-+			}
-+		}
-+	}
-+}
-+
-+/*******************************************************************************
-+ * Public functions
-+ ******************************************************************************/
-+void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
-+	struct bw_calcs_vbios *bw_vbios,
-+	struct hw_asic_id asic_id)
-+{
-+	struct bw_calcs_dceip dceip = { 0 };
-+	struct bw_calcs_vbios vbios = { 0 };
-+
-+	enum bw_calcs_version version = bw_calcs_version_from_asic_id(asic_id);
-+
-+	dceip.version = version;
-+
-+	switch (version) {
-+	case BW_CALCS_VERSION_CARRIZO:
-+		vbios.memory_type = bw_def_gddr5;
-+		vbios.dram_channel_width_in_bits = 64;
-+		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
-+		vbios.number_of_dram_banks = 8;
-+		vbios.high_yclk = bw_int_to_fixed(1600);
-+		vbios.mid_yclk = bw_int_to_fixed(1600);
-+		vbios.low_yclk = bw_frc_to_fixed(66666, 100);
-+		vbios.low_sclk = bw_int_to_fixed(200);
-+		vbios.mid1_sclk = bw_int_to_fixed(300);
-+		vbios.mid2_sclk = bw_int_to_fixed(300);
-+		vbios.mid3_sclk = bw_int_to_fixed(300);
-+		vbios.mid4_sclk = bw_int_to_fixed(300);
-+		vbios.mid5_sclk = bw_int_to_fixed(300);
-+		vbios.mid6_sclk = bw_int_to_fixed(300);
-+		vbios.high_sclk = bw_frc_to_fixed(62609, 100);
-+		vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);
-+		vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);
-+		vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);
-+		vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
-+		vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
-+		vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
-+		vbios.data_return_bus_width = bw_int_to_fixed(32);
-+		vbios.trc = bw_int_to_fixed(50);
-+		vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
-+		vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(153, 10);
-+		vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
-+		vbios.nbp_state_change_latency = bw_frc_to_fixed(19649, 1000);
-+		vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
-+		vbios.scatter_gather_enable = true;
-+		vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
-+		vbios.cursor_width = 32;
-+		vbios.average_compression_rate = 4;
-+		vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
-+		vbios.blackout_duration = bw_int_to_fixed(18); /* us */
-+		vbios.maximum_blackout_recovery_time = bw_int_to_fixed(20);
-+
-+		dceip.large_cursor = false;
-+		dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
-+		dceip.dmif_pipe_en_fbc_chunk_tracker = false;
-+		dceip.cursor_max_outstanding_group_num = 1;
-+		dceip.lines_interleaved_into_lb = 2;
-+		dceip.chunk_width = 256;
-+		dceip.number_of_graphics_pipes = 3;
-+		dceip.number_of_underlay_pipes = 1;
-+		dceip.low_power_tiling_mode = 0;
-+		dceip.display_write_back_supported = false;
-+		dceip.argb_compression_support = false;
-+		dceip.underlay_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35556, 10000);
-+		dceip.underlay_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.underlay_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.underlay_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.graphics_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35, 10);
-+		dceip.graphics_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.graphics_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.graphics_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
-+		dceip.max_dmif_buffer_allocated = 2;
-+		dceip.graphics_dmif_size = 12288;
-+		dceip.underlay_luma_dmif_size = 19456;
-+		dceip.underlay_chroma_dmif_size = 23552;
-+		dceip.pre_downscaler_enabled = true;
-+		dceip.underlay_downscale_prefetch_enabled = true;
-+		dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
-+		dceip.lb_size_per_component444 = bw_int_to_fixed(82176);
-+		dceip.graphics_lb_nodownscaling_multi_line_prefetching = false;
-+		dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
-+			bw_int_to_fixed(0);
-+		dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.underlay420_chroma_lb_size_per_component =
-+			bw_int_to_fixed(164352);
-+		dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.cursor_chunk_width = bw_int_to_fixed(64);
-+		dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
-+		dceip.underlay_maximum_width_efficient_for_tiling =
-+			bw_int_to_fixed(1920);
-+		dceip.underlay_maximum_height_efficient_for_tiling =
-+			bw_int_to_fixed(1080);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
-+			bw_frc_to_fixed(3, 10);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
-+			bw_int_to_fixed(25);
-+		dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
-+			2);
-+		dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
-+			bw_int_to_fixed(128);
-+		dceip.limit_excessive_outstanding_dmif_requests = true;
-+		dceip.linear_mode_line_request_alternation_slice =
-+			bw_int_to_fixed(64);
-+		dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
-+			32;
-+		dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
-+		dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
-+		dceip.request_efficiency = bw_frc_to_fixed(8, 10);
-+		dceip.dispclk_per_request = bw_int_to_fixed(2);
-+		dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
-+		dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
-+		dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
-+		dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/
-+		break;
-+	case BW_CALCS_VERSION_POLARIS10:
-+		vbios.memory_type = bw_def_gddr5;
-+		vbios.dram_channel_width_in_bits = 32;
-+		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
-+		vbios.number_of_dram_banks = 8;
-+		vbios.high_yclk = bw_int_to_fixed(6000);
-+		vbios.mid_yclk = bw_int_to_fixed(3200);
-+		vbios.low_yclk = bw_int_to_fixed(1000);
-+		vbios.low_sclk = bw_int_to_fixed(300);
-+		vbios.mid1_sclk = bw_int_to_fixed(400);
-+		vbios.mid2_sclk = bw_int_to_fixed(500);
-+		vbios.mid3_sclk = bw_int_to_fixed(600);
-+		vbios.mid4_sclk = bw_int_to_fixed(700);
-+		vbios.mid5_sclk = bw_int_to_fixed(800);
-+		vbios.mid6_sclk = bw_int_to_fixed(974);
-+		vbios.high_sclk = bw_int_to_fixed(1154);
-+		vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
-+		vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
-+		vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);
-+		vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
-+		vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
-+		vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
-+		vbios.data_return_bus_width = bw_int_to_fixed(32);
-+		vbios.trc = bw_int_to_fixed(48);
-+		vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
-+		vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
-+		vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
-+		vbios.nbp_state_change_latency = bw_int_to_fixed(45);
-+		vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
-+		vbios.scatter_gather_enable = true;
-+		vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
-+		vbios.cursor_width = 32;
-+		vbios.average_compression_rate = 4;
-+		vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
-+		vbios.blackout_duration = bw_int_to_fixed(0); /* us */
-+		vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
-+
-+		dceip.large_cursor = false;
-+		dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
-+		dceip.dmif_pipe_en_fbc_chunk_tracker = false;
-+		dceip.cursor_max_outstanding_group_num = 1;
-+		dceip.lines_interleaved_into_lb = 2;
-+		dceip.chunk_width = 256;
-+		dceip.number_of_graphics_pipes = 6;
-+		dceip.number_of_underlay_pipes = 0;
-+		dceip.low_power_tiling_mode = 0;
-+		dceip.display_write_back_supported = false;
-+		dceip.argb_compression_support = true;
-+		dceip.underlay_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35556, 10000);
-+		dceip.underlay_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.underlay_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.underlay_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.graphics_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35, 10);
-+		dceip.graphics_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.graphics_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.graphics_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
-+		dceip.max_dmif_buffer_allocated = 4;
-+		dceip.graphics_dmif_size = 12288;
-+		dceip.underlay_luma_dmif_size = 19456;
-+		dceip.underlay_chroma_dmif_size = 23552;
-+		dceip.pre_downscaler_enabled = true;
-+		dceip.underlay_downscale_prefetch_enabled = true;
-+		dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
-+		dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
-+		dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
-+		dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
-+			bw_int_to_fixed(1);
-+		dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.underlay420_chroma_lb_size_per_component =
-+			bw_int_to_fixed(164352);
-+		dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.cursor_chunk_width = bw_int_to_fixed(64);
-+		dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
-+		dceip.underlay_maximum_width_efficient_for_tiling =
-+			bw_int_to_fixed(1920);
-+		dceip.underlay_maximum_height_efficient_for_tiling =
-+			bw_int_to_fixed(1080);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
-+			bw_frc_to_fixed(3, 10);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
-+			bw_int_to_fixed(25);
-+		dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
-+			2);
-+		dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
-+			bw_int_to_fixed(128);
-+		dceip.limit_excessive_outstanding_dmif_requests = true;
-+		dceip.linear_mode_line_request_alternation_slice =
-+			bw_int_to_fixed(64);
-+		dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
-+			32;
-+		dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
-+		dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
-+		dceip.request_efficiency = bw_frc_to_fixed(8, 10);
-+		dceip.dispclk_per_request = bw_int_to_fixed(2);
-+		dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
-+		dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
-+		dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
-+		dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
-+		break;
-+	case BW_CALCS_VERSION_POLARIS11:
-+		vbios.memory_type = bw_def_gddr5;
-+		vbios.dram_channel_width_in_bits = 32;
-+		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
-+		vbios.number_of_dram_banks = 8;
-+		vbios.high_yclk = bw_int_to_fixed(6000);
-+		vbios.mid_yclk = bw_int_to_fixed(3200);
-+		vbios.low_yclk = bw_int_to_fixed(1000);
-+		vbios.low_sclk = bw_int_to_fixed(300);
-+		vbios.mid1_sclk = bw_int_to_fixed(400);
-+		vbios.mid2_sclk = bw_int_to_fixed(500);
-+		vbios.mid3_sclk = bw_int_to_fixed(600);
-+		vbios.mid4_sclk = bw_int_to_fixed(700);
-+		vbios.mid5_sclk = bw_int_to_fixed(800);
-+		vbios.mid6_sclk = bw_int_to_fixed(974);
-+		vbios.high_sclk = bw_int_to_fixed(1154);
-+		vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
-+		vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
-+		vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);
-+		vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
-+		vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
-+		vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
-+		vbios.data_return_bus_width = bw_int_to_fixed(32);
-+		vbios.trc = bw_int_to_fixed(48);
-+		if (vbios.number_of_dram_channels == 2) // 64-bit
-+			vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
-+		else
-+			vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
-+		vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
-+		vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
-+		vbios.nbp_state_change_latency = bw_int_to_fixed(45);
-+		vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
-+		vbios.scatter_gather_enable = true;
-+		vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
-+		vbios.cursor_width = 32;
-+		vbios.average_compression_rate = 4;
-+		vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
-+		vbios.blackout_duration = bw_int_to_fixed(0); /* us */
-+		vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
-+
-+		dceip.large_cursor = false;
-+		dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
-+		dceip.dmif_pipe_en_fbc_chunk_tracker = false;
-+		dceip.cursor_max_outstanding_group_num = 1;
-+		dceip.lines_interleaved_into_lb = 2;
-+		dceip.chunk_width = 256;
-+		dceip.number_of_graphics_pipes = 5;
-+		dceip.number_of_underlay_pipes = 0;
-+		dceip.low_power_tiling_mode = 0;
-+		dceip.display_write_back_supported = false;
-+		dceip.argb_compression_support = true;
-+		dceip.underlay_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35556, 10000);
-+		dceip.underlay_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.underlay_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.underlay_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.graphics_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35, 10);
-+		dceip.graphics_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.graphics_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.graphics_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
-+		dceip.max_dmif_buffer_allocated = 4;
-+		dceip.graphics_dmif_size = 12288;
-+		dceip.underlay_luma_dmif_size = 19456;
-+		dceip.underlay_chroma_dmif_size = 23552;
-+		dceip.pre_downscaler_enabled = true;
-+		dceip.underlay_downscale_prefetch_enabled = true;
-+		dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
-+		dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
-+		dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
-+		dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
-+			bw_int_to_fixed(1);
-+		dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.underlay420_chroma_lb_size_per_component =
-+			bw_int_to_fixed(164352);
-+		dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.cursor_chunk_width = bw_int_to_fixed(64);
-+		dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
-+		dceip.underlay_maximum_width_efficient_for_tiling =
-+			bw_int_to_fixed(1920);
-+		dceip.underlay_maximum_height_efficient_for_tiling =
-+			bw_int_to_fixed(1080);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
-+			bw_frc_to_fixed(3, 10);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
-+			bw_int_to_fixed(25);
-+		dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
-+			2);
-+		dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
-+			bw_int_to_fixed(128);
-+		dceip.limit_excessive_outstanding_dmif_requests = true;
-+		dceip.linear_mode_line_request_alternation_slice =
-+			bw_int_to_fixed(64);
-+		dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
-+			32;
-+		dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
-+		dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
-+		dceip.request_efficiency = bw_frc_to_fixed(8, 10);
-+		dceip.dispclk_per_request = bw_int_to_fixed(2);
-+		dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
-+		dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
-+		dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
-+		dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
-+		break;
-+	case BW_CALCS_VERSION_STONEY:
-+		vbios.memory_type = bw_def_gddr5;
-+		vbios.dram_channel_width_in_bits = 64;
-+		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
-+		vbios.number_of_dram_banks = 8;
-+		vbios.high_yclk = bw_int_to_fixed(1866);
-+		vbios.mid_yclk = bw_int_to_fixed(1866);
-+		vbios.low_yclk = bw_int_to_fixed(1333);
-+		vbios.low_sclk = bw_int_to_fixed(200);
-+		vbios.mid1_sclk = bw_int_to_fixed(600);
-+		vbios.mid2_sclk = bw_int_to_fixed(600);
-+		vbios.mid3_sclk = bw_int_to_fixed(600);
-+		vbios.mid4_sclk = bw_int_to_fixed(600);
-+		vbios.mid5_sclk = bw_int_to_fixed(600);
-+		vbios.mid6_sclk = bw_int_to_fixed(600);
-+		vbios.high_sclk = bw_int_to_fixed(800);
-+		vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);
-+		vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);
-+		vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);
-+		vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
-+		vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
-+		vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
-+		vbios.data_return_bus_width = bw_int_to_fixed(32);
-+		vbios.trc = bw_int_to_fixed(50);
-+		vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
-+		vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(158, 10);
-+		vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
-+		vbios.nbp_state_change_latency = bw_frc_to_fixed(2008, 100);
-+		vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
-+		vbios.scatter_gather_enable = true;
-+		vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
-+		vbios.cursor_width = 32;
-+		vbios.average_compression_rate = 4;
-+		vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
-+		vbios.blackout_duration = bw_int_to_fixed(18); /* us */
-+		vbios.maximum_blackout_recovery_time = bw_int_to_fixed(20);
-+
-+		dceip.large_cursor = false;
-+		dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
-+		dceip.dmif_pipe_en_fbc_chunk_tracker = false;
-+		dceip.cursor_max_outstanding_group_num = 1;
-+		dceip.lines_interleaved_into_lb = 2;
-+		dceip.chunk_width = 256;
-+		dceip.number_of_graphics_pipes = 2;
-+		dceip.number_of_underlay_pipes = 1;
-+		dceip.low_power_tiling_mode = 0;
-+		dceip.display_write_back_supported = false;
-+		dceip.argb_compression_support = true;
-+		dceip.underlay_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35556, 10000);
-+		dceip.underlay_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.underlay_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.underlay_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.graphics_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35, 10);
-+		dceip.graphics_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.graphics_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.graphics_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
-+		dceip.max_dmif_buffer_allocated = 2;
-+		dceip.graphics_dmif_size = 12288;
-+		dceip.underlay_luma_dmif_size = 19456;
-+		dceip.underlay_chroma_dmif_size = 23552;
-+		dceip.pre_downscaler_enabled = true;
-+		dceip.underlay_downscale_prefetch_enabled = true;
-+		dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
-+		dceip.lb_size_per_component444 = bw_int_to_fixed(82176);
-+		dceip.graphics_lb_nodownscaling_multi_line_prefetching = false;
-+		dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
-+			bw_int_to_fixed(0);
-+		dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.underlay420_chroma_lb_size_per_component =
-+			bw_int_to_fixed(164352);
-+		dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.cursor_chunk_width = bw_int_to_fixed(64);
-+		dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
-+		dceip.underlay_maximum_width_efficient_for_tiling =
-+			bw_int_to_fixed(1920);
-+		dceip.underlay_maximum_height_efficient_for_tiling =
-+			bw_int_to_fixed(1080);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
-+			bw_frc_to_fixed(3, 10);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
-+			bw_int_to_fixed(25);
-+		dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
-+			2);
-+		dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
-+			bw_int_to_fixed(128);
-+		dceip.limit_excessive_outstanding_dmif_requests = true;
-+		dceip.linear_mode_line_request_alternation_slice =
-+			bw_int_to_fixed(64);
-+		dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
-+			32;
-+		dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
-+		dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
-+		dceip.request_efficiency = bw_frc_to_fixed(8, 10);
-+		dceip.dispclk_per_request = bw_int_to_fixed(2);
-+		dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
-+		dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
-+		dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
-+		dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
-+		break;
-+	case BW_CALCS_VERSION_VEGA10:
-+		vbios.memory_type = bw_def_hbm;
-+		vbios.dram_channel_width_in_bits = 128;
-+		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
-+		vbios.number_of_dram_banks = 16;
-+		vbios.high_yclk = bw_int_to_fixed(2400);
-+		vbios.mid_yclk = bw_int_to_fixed(1700);
-+		vbios.low_yclk = bw_int_to_fixed(1000);
-+		vbios.low_sclk = bw_int_to_fixed(300);
-+		vbios.mid1_sclk = bw_int_to_fixed(350);
-+		vbios.mid2_sclk = bw_int_to_fixed(400);
-+		vbios.mid3_sclk = bw_int_to_fixed(500);
-+		vbios.mid4_sclk = bw_int_to_fixed(600);
-+		vbios.mid5_sclk = bw_int_to_fixed(700);
-+		vbios.mid6_sclk = bw_int_to_fixed(760);
-+		vbios.high_sclk = bw_int_to_fixed(776);
-+		vbios.low_voltage_max_dispclk = bw_int_to_fixed(460);
-+		vbios.mid_voltage_max_dispclk = bw_int_to_fixed(670);
-+		vbios.high_voltage_max_dispclk = bw_int_to_fixed(1133);
-+		vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
-+		vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
-+		vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
-+		vbios.data_return_bus_width = bw_int_to_fixed(32);
-+		vbios.trc = bw_int_to_fixed(48);
-+		vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
-+		vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(75, 10);
-+		vbios.stutter_self_refresh_entry_latency = bw_frc_to_fixed(19, 10);
-+		vbios.nbp_state_change_latency = bw_int_to_fixed(39);
-+		vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
-+		vbios.scatter_gather_enable = false;
-+		vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
-+		vbios.cursor_width = 32;
-+		vbios.average_compression_rate = 4;
-+		vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 8;
-+		vbios.blackout_duration = bw_int_to_fixed(0); /* us */
-+		vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
-+
-+		dceip.large_cursor = false;
-+		dceip.dmif_request_buffer_size = bw_int_to_fixed(2304);
-+		dceip.dmif_pipe_en_fbc_chunk_tracker = true;
-+		dceip.cursor_max_outstanding_group_num = 1;
-+		dceip.lines_interleaved_into_lb = 2;
-+		dceip.chunk_width = 256;
-+		dceip.number_of_graphics_pipes = 6;
-+		dceip.number_of_underlay_pipes = 0;
-+		dceip.low_power_tiling_mode = 0;
-+		dceip.display_write_back_supported = true;
-+		dceip.argb_compression_support = true;
-+		dceip.underlay_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35556, 10000);
-+		dceip.underlay_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.underlay_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.underlay_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.graphics_vscaler_efficiency6_bit_per_component =
-+			bw_frc_to_fixed(35, 10);
-+		dceip.graphics_vscaler_efficiency8_bit_per_component =
-+			bw_frc_to_fixed(34286, 10000);
-+		dceip.graphics_vscaler_efficiency10_bit_per_component =
-+			bw_frc_to_fixed(32, 10);
-+		dceip.graphics_vscaler_efficiency12_bit_per_component =
-+			bw_int_to_fixed(3);
-+		dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
-+		dceip.max_dmif_buffer_allocated = 4;
-+		dceip.graphics_dmif_size = 24576;
-+		dceip.underlay_luma_dmif_size = 19456;
-+		dceip.underlay_chroma_dmif_size = 23552;
-+		dceip.pre_downscaler_enabled = true;
-+		dceip.underlay_downscale_prefetch_enabled = false;
-+		dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
-+		dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
-+		dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
-+		dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
-+			bw_int_to_fixed(1);
-+		dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.underlay420_chroma_lb_size_per_component =
-+			bw_int_to_fixed(164352);
-+		dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
-+			82176);
-+		dceip.cursor_chunk_width = bw_int_to_fixed(64);
-+		dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
-+		dceip.underlay_maximum_width_efficient_for_tiling =
-+			bw_int_to_fixed(1920);
-+		dceip.underlay_maximum_height_efficient_for_tiling =
-+			bw_int_to_fixed(1080);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
-+			bw_frc_to_fixed(3, 10);
-+		dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
-+			bw_int_to_fixed(25);
-+		dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
-+			2);
-+		dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
-+			bw_int_to_fixed(128);
-+		dceip.limit_excessive_outstanding_dmif_requests = true;
-+		dceip.linear_mode_line_request_alternation_slice =
-+			bw_int_to_fixed(64);
-+		dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
-+			32;
-+		dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
-+		dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
-+		dceip.request_efficiency = bw_frc_to_fixed(8, 10);
-+		dceip.dispclk_per_request = bw_int_to_fixed(2);
-+		dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
-+		dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
-+		dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
-+		dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
-+		break;
-+	default:
-+		break;
-+	}
-+	*bw_dceip = dceip;
-+	*bw_vbios = vbios;
-+
-+}
-+
-+/**
-+ * Compare calculated (required) clocks against the clocks available at
-+ * maximum voltage (max Performance Level).
-+ */
-+static bool is_display_configuration_supported(
-+	const struct bw_calcs_vbios *vbios,
-+	const struct dce_bw_output *calcs_output)
-+{
-+	uint32_t int_max_clk;
-+
-+	int_max_clk = bw_fixed_to_int(vbios->high_voltage_max_dispclk);
-+	int_max_clk *= 1000; /* MHz to kHz */
-+	if (calcs_output->dispclk_khz > int_max_clk)
-+		return false;
-+
-+	int_max_clk = bw_fixed_to_int(vbios->high_sclk);
-+	int_max_clk *= 1000; /* MHz to kHz */
-+	if (calcs_output->sclk_khz > int_max_clk)
-+		return false;
-+
-+	return true;
-+}
-+
-+static void populate_initial_data(
-+	const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data)
-+{
-+	int i, j;
-+	int num_displays = 0;
-+
-+	data->underlay_surface_type = bw_def_420;
-+	data->panning_and_bezel_adjustment = bw_def_none;
-+	data->graphics_lb_bpc = 10;
-+	data->underlay_lb_bpc = 8;
-+	data->underlay_tiling_mode = bw_def_tiled;
-+	data->graphics_tiling_mode = bw_def_tiled;
-+	data->underlay_micro_tile_mode = bw_def_display_micro_tiling;
-+	data->graphics_micro_tile_mode = bw_def_display_micro_tiling;
-+
-+	/* Pipes with underlay first */
-+	for (i = 0; i < pipe_count; i++) {
-+		if (!pipe[i].stream || !pipe[i].bottom_pipe)
-+			continue;
-+
-+		ASSERT(pipe[i].plane_state);
-+
-+		if (num_displays == 0) {
-+			if (!pipe[i].plane_state->visible)
-+				data->d0_underlay_mode = bw_def_underlay_only;
-+			else
-+				data->d0_underlay_mode = bw_def_blend;
-+		} else {
-+			if (!pipe[i].plane_state->visible)
-+				data->d1_underlay_mode = bw_def_underlay_only;
-+			else
-+				data->d1_underlay_mode = bw_def_blend;
-+		}
-+
-+		data->fbc_en[num_displays + 4] = false;
-+		data->lpt_en[num_displays + 4] = false;
-+		data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
-+		data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
-+		data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000);
-+		data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
-+		data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
-+		data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);
-+		data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);
-+		data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);
-+		data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);
-+		data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);
-+		switch (pipe[i].plane_state->rotation) {
-+		case ROTATION_ANGLE_0:
-+			data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
-+			break;
-+		case ROTATION_ANGLE_90:
-+			data->rotation_angle[num_displays + 4] = bw_int_to_fixed(90);
-+			break;
-+		case ROTATION_ANGLE_180:
-+			data->rotation_angle[num_displays + 4] = bw_int_to_fixed(180);
-+			break;
-+		case ROTATION_ANGLE_270:
-+			data->rotation_angle[num_displays + 4] = bw_int_to_fixed(270);
-+			break;
-+		default:
-+			break;
-+		}
-+		switch (pipe[i].plane_state->format) {
-+		case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
-+		case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
-+			data->bytes_per_pixel[num_displays + 4] = 2;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
-+		case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
-+		case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
-+			data->bytes_per_pixel[num_displays + 4] = 4;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+			data->bytes_per_pixel[num_displays + 4] = 8;
-+			break;
-+		default:
-+			data->bytes_per_pixel[num_displays + 4] = 4;
-+			break;
-+		}
-+		data->interlace_mode[num_displays + 4] = false;
-+		data->stereo_mode[num_displays + 4] = bw_def_mono;
-+
-+
-+		for (j = 0; j < 2; j++) {
-+			data->fbc_en[num_displays * 2 + j] = false;
-+			data->lpt_en[num_displays * 2 + j] = false;
-+
-+			data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height);
-+			data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width);
-+			data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed(
-+					pipe[i].bottom_pipe->plane_state->plane_size.grph.surface_pitch);
-+			data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);
-+			data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps);
-+			data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed(
-+					pipe[i].bottom_pipe->plane_res.scl_data.ratios.horz.value);
-+			data->v_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed(
-+					pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value);
-+			switch (pipe[i].bottom_pipe->plane_state->rotation) {
-+			case ROTATION_ANGLE_0:
-+				data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(0);
-+				break;
-+			case ROTATION_ANGLE_90:
-+				data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(90);
-+				break;
-+			case ROTATION_ANGLE_180:
-+				data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(180);
-+				break;
-+			case ROTATION_ANGLE_270:
-+				data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(270);
-+				break;
-+			default:
-+				break;
-+			}
-+			data->stereo_mode[num_displays * 2 + j] = bw_def_mono;
-+		}
-+
-+		num_displays++;
-+	}
-+
-+	/* Pipes without underlay after */
-+	for (i = 0; i < pipe_count; i++) {
-+		if (!pipe[i].stream || pipe[i].bottom_pipe)
-+			continue;
-+
-+
-+		data->fbc_en[num_displays + 4] = false;
-+		data->lpt_en[num_displays + 4] = false;
-+		data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
-+		data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
-+		data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000);
-+		if (pipe[i].plane_state) {
-+			data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
-+			data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
-+			data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);
-+			data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);
-+			data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);
-+			data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);
-+			data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);
-+			switch (pipe[i].plane_state->rotation) {
-+			case ROTATION_ANGLE_0:
-+				data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
-+				break;
-+			case ROTATION_ANGLE_90:
-+				data->rotation_angle[num_displays + 4] = bw_int_to_fixed(90);
-+				break;
-+			case ROTATION_ANGLE_180:
-+				data->rotation_angle[num_displays + 4] = bw_int_to_fixed(180);
-+				break;
-+			case ROTATION_ANGLE_270:
-+				data->rotation_angle[num_displays + 4] = bw_int_to_fixed(270);
-+				break;
-+			default:
-+				break;
-+			}
-+			switch (pipe[i].plane_state->format) {
-+			case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
-+			case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
-+			case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
-+			case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
-+				data->bytes_per_pixel[num_displays + 4] = 2;
-+				break;
-+			case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+			case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
-+			case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+			case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+			case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
-+			case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
-+			case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
-+				data->bytes_per_pixel[num_displays + 4] = 4;
-+				break;
-+			case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+			case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+				data->bytes_per_pixel[num_displays + 4] = 8;
-+				break;
-+			default:
-+				data->bytes_per_pixel[num_displays + 4] = 4;
-+				break;
-+			}
-+		} else {
-+			data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);
-+			data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
-+			data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable);
-+			data->h_taps[num_displays + 4] = bw_int_to_fixed(1);
-+			data->v_taps[num_displays + 4] = bw_int_to_fixed(1);
-+			data->h_scale_ratio[num_displays + 4] = bw_int_to_fixed(1);
-+			data->v_scale_ratio[num_displays + 4] = bw_int_to_fixed(1);
-+			data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
-+			data->bytes_per_pixel[num_displays + 4] = 4;
-+		}
-+
-+		data->interlace_mode[num_displays + 4] = false;
-+		data->stereo_mode[num_displays + 4] = bw_def_mono;
-+		num_displays++;
-+	}
-+
-+	data->number_of_displays = num_displays;
-+}
-+
-+/**
-+ * Return:
-+ *	true -	Display(s) configuration supported.
-+ *		In this case 'calcs_output' contains data for HW programming
-+ *	false - Display(s) configuration not supported (not enough bandwidth).
-+ */
-+
-+bool bw_calcs(struct dc_context *ctx,
-+	const struct bw_calcs_dceip *dceip,
-+	const struct bw_calcs_vbios *vbios,
-+	const struct pipe_ctx pipe[],
-+	int pipe_count,
-+	struct dce_bw_output *calcs_output)
-+{
-+	struct bw_calcs_data *data = kzalloc(sizeof(struct bw_calcs_data),
-+					     GFP_KERNEL);
-+	if (!data)
-+		return false;
-+
-+	populate_initial_data(pipe, pipe_count, data);
-+
-+	/*TODO: this should be taken out calcs output and assigned during timing sync for pplib use*/
-+	calcs_output->all_displays_in_sync = false;
-+
-+	if (data->number_of_displays != 0) {
-+		uint8_t yclk_lvl, sclk_lvl;
-+		struct bw_fixed high_sclk = vbios->high_sclk;
-+		struct bw_fixed mid1_sclk = vbios->mid1_sclk;
-+		struct bw_fixed mid2_sclk = vbios->mid2_sclk;
-+		struct bw_fixed mid3_sclk = vbios->mid3_sclk;
-+		struct bw_fixed mid4_sclk = vbios->mid4_sclk;
-+		struct bw_fixed mid5_sclk = vbios->mid5_sclk;
-+		struct bw_fixed mid6_sclk = vbios->mid6_sclk;
-+		struct bw_fixed low_sclk = vbios->low_sclk;
-+		struct bw_fixed high_yclk = vbios->high_yclk;
-+		struct bw_fixed mid_yclk = vbios->mid_yclk;
-+		struct bw_fixed low_yclk = vbios->low_yclk;
-+
-+		calculate_bandwidth(dceip, vbios, data);
-+
-+		yclk_lvl = data->y_clk_level;
-+		sclk_lvl = data->sclk_level;
-+
-+		calcs_output->nbp_state_change_enable =
-+			data->nbp_state_change_enable;
-+		calcs_output->cpuc_state_change_enable =
-+				data->cpuc_state_change_enable;
-+		calcs_output->cpup_state_change_enable =
-+				data->cpup_state_change_enable;
-+		calcs_output->stutter_mode_enable =
-+				data->stutter_mode_enable;
-+		calcs_output->dispclk_khz =
-+			bw_fixed_to_int(bw_mul(data->dispclk,
-+					bw_int_to_fixed(1000)));
-+		calcs_output->blackout_recovery_time_us =
-+			bw_fixed_to_int(data->blackout_recovery_time);
-+		calcs_output->sclk_khz =
-+			bw_fixed_to_int(bw_mul(data->required_sclk,
-+					bw_int_to_fixed(1000)));
-+		calcs_output->sclk_deep_sleep_khz =
-+			bw_fixed_to_int(bw_mul(data->sclk_deep_sleep,
-+					bw_int_to_fixed(1000)));
-+		if (yclk_lvl == 0)
-+			calcs_output->yclk_khz = bw_fixed_to_int(
-+				bw_mul(low_yclk, bw_int_to_fixed(1000)));
-+		else if (yclk_lvl == 1)
-+			calcs_output->yclk_khz = bw_fixed_to_int(
-+				bw_mul(mid_yclk, bw_int_to_fixed(1000)));
-+		else
-+			calcs_output->yclk_khz = bw_fixed_to_int(
-+				bw_mul(high_yclk, bw_int_to_fixed(1000)));
-+
-+		/* units: nanosecond, 16bit storage. */
-+
-+		calcs_output->nbp_state_change_wm_ns[0].a_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[1].a_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[2].a_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
-+
-+		if (ctx->dc->caps.max_slave_planes) {
-+			calcs_output->nbp_state_change_wm_ns[3].a_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
-+			calcs_output->nbp_state_change_wm_ns[4].a_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+							nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
-+		} else {
-+			calcs_output->nbp_state_change_wm_ns[3].a_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
-+			calcs_output->nbp_state_change_wm_ns[4].a_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
-+		}
-+		calcs_output->nbp_state_change_wm_ns[5].a_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
-+
-+
-+
-+		calcs_output->stutter_exit_wm_ns[0].a_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				stutter_exit_watermark[4], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[1].a_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				stutter_exit_watermark[5], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[2].a_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				stutter_exit_watermark[6], bw_int_to_fixed(1000)));
-+		if (ctx->dc->caps.max_slave_planes) {
-+			calcs_output->stutter_exit_wm_ns[3].a_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[0], bw_int_to_fixed(1000)));
-+			calcs_output->stutter_exit_wm_ns[4].a_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[1], bw_int_to_fixed(1000)));
-+		} else {
-+			calcs_output->stutter_exit_wm_ns[3].a_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[7], bw_int_to_fixed(1000)));
-+			calcs_output->stutter_exit_wm_ns[4].a_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[8], bw_int_to_fixed(1000)));
-+		}
-+		calcs_output->stutter_exit_wm_ns[5].a_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				stutter_exit_watermark[9], bw_int_to_fixed(1000)));
-+
-+
-+
-+		calcs_output->urgent_wm_ns[0].a_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				urgent_watermark[4], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[1].a_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				urgent_watermark[5], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[2].a_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				urgent_watermark[6], bw_int_to_fixed(1000)));
-+		if (ctx->dc->caps.max_slave_planes) {
-+			calcs_output->urgent_wm_ns[3].a_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[0], bw_int_to_fixed(1000)));
-+			calcs_output->urgent_wm_ns[4].a_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[1], bw_int_to_fixed(1000)));
-+		} else {
-+			calcs_output->urgent_wm_ns[3].a_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[7], bw_int_to_fixed(1000)));
-+			calcs_output->urgent_wm_ns[4].a_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[8], bw_int_to_fixed(1000)));
-+		}
-+		calcs_output->urgent_wm_ns[5].a_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				urgent_watermark[9], bw_int_to_fixed(1000)));
-+
-+		if (dceip->version != BW_CALCS_VERSION_CARRIZO) {
-+			((struct bw_calcs_vbios *)vbios)->low_sclk = mid3_sclk;
-+			((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid3_sclk;
-+			((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid3_sclk;
-+			calculate_bandwidth(dceip, vbios, data);
-+
-+			calcs_output->nbp_state_change_wm_ns[0].b_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[4],bw_int_to_fixed(1000)));
-+			calcs_output->nbp_state_change_wm_ns[1].b_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
-+			calcs_output->nbp_state_change_wm_ns[2].b_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
-+
-+			if (ctx->dc->caps.max_slave_planes) {
-+				calcs_output->nbp_state_change_wm_ns[3].b_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
-+				calcs_output->nbp_state_change_wm_ns[4].b_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
-+			} else {
-+				calcs_output->nbp_state_change_wm_ns[3].b_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
-+				calcs_output->nbp_state_change_wm_ns[4].b_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
-+			}
-+			calcs_output->nbp_state_change_wm_ns[5].b_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
-+
-+
-+
-+			calcs_output->stutter_exit_wm_ns[0].b_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[4], bw_int_to_fixed(1000)));
-+			calcs_output->stutter_exit_wm_ns[1].b_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[5], bw_int_to_fixed(1000)));
-+			calcs_output->stutter_exit_wm_ns[2].b_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[6], bw_int_to_fixed(1000)));
-+			if (ctx->dc->caps.max_slave_planes) {
-+				calcs_output->stutter_exit_wm_ns[3].b_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						stutter_exit_watermark[0], bw_int_to_fixed(1000)));
-+				calcs_output->stutter_exit_wm_ns[4].b_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						stutter_exit_watermark[1], bw_int_to_fixed(1000)));
-+			} else {
-+				calcs_output->stutter_exit_wm_ns[3].b_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						stutter_exit_watermark[7], bw_int_to_fixed(1000)));
-+				calcs_output->stutter_exit_wm_ns[4].b_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						stutter_exit_watermark[8], bw_int_to_fixed(1000)));
-+			}
-+			calcs_output->stutter_exit_wm_ns[5].b_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[9], bw_int_to_fixed(1000)));
-+
-+
-+
-+			calcs_output->urgent_wm_ns[0].b_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[4], bw_int_to_fixed(1000)));
-+			calcs_output->urgent_wm_ns[1].b_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[5], bw_int_to_fixed(1000)));
-+			calcs_output->urgent_wm_ns[2].b_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[6], bw_int_to_fixed(1000)));
-+			if (ctx->dc->caps.max_slave_planes) {
-+				calcs_output->urgent_wm_ns[3].b_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						urgent_watermark[0], bw_int_to_fixed(1000)));
-+				calcs_output->urgent_wm_ns[4].b_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						urgent_watermark[1], bw_int_to_fixed(1000)));
-+			} else {
-+				calcs_output->urgent_wm_ns[3].b_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						urgent_watermark[7], bw_int_to_fixed(1000)));
-+				calcs_output->urgent_wm_ns[4].b_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						urgent_watermark[8], bw_int_to_fixed(1000)));
-+			}
-+			calcs_output->urgent_wm_ns[5].b_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[9], bw_int_to_fixed(1000)));
-+
-+			((struct bw_calcs_vbios *)vbios)->low_sclk = low_sclk;
-+			((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid1_sclk;
-+			((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid2_sclk;
-+			((struct bw_calcs_vbios *)vbios)->low_yclk = mid_yclk;
-+			calculate_bandwidth(dceip, vbios, data);
-+
-+			calcs_output->nbp_state_change_wm_ns[0].c_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
-+			calcs_output->nbp_state_change_wm_ns[1].c_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
-+			calcs_output->nbp_state_change_wm_ns[2].c_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
-+			if (ctx->dc->caps.max_slave_planes) {
-+				calcs_output->nbp_state_change_wm_ns[3].c_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
-+				calcs_output->nbp_state_change_wm_ns[4].c_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
-+			} else {
-+				calcs_output->nbp_state_change_wm_ns[3].c_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
-+				calcs_output->nbp_state_change_wm_ns[4].c_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
-+			}
-+			calcs_output->nbp_state_change_wm_ns[5].c_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
-+
-+
-+			calcs_output->stutter_exit_wm_ns[0].c_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[4], bw_int_to_fixed(1000)));
-+			calcs_output->stutter_exit_wm_ns[1].c_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[5], bw_int_to_fixed(1000)));
-+			calcs_output->stutter_exit_wm_ns[2].c_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[6], bw_int_to_fixed(1000)));
-+			if (ctx->dc->caps.max_slave_planes) {
-+				calcs_output->stutter_exit_wm_ns[3].c_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						stutter_exit_watermark[0], bw_int_to_fixed(1000)));
-+				calcs_output->stutter_exit_wm_ns[4].c_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						stutter_exit_watermark[1], bw_int_to_fixed(1000)));
-+			} else {
-+				calcs_output->stutter_exit_wm_ns[3].c_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						stutter_exit_watermark[7], bw_int_to_fixed(1000)));
-+				calcs_output->stutter_exit_wm_ns[4].c_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						stutter_exit_watermark[8], bw_int_to_fixed(1000)));
-+			}
-+			calcs_output->stutter_exit_wm_ns[5].c_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[9], bw_int_to_fixed(1000)));
-+
-+			calcs_output->urgent_wm_ns[0].c_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[4], bw_int_to_fixed(1000)));
-+			calcs_output->urgent_wm_ns[1].c_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[5], bw_int_to_fixed(1000)));
-+			calcs_output->urgent_wm_ns[2].c_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[6], bw_int_to_fixed(1000)));
-+			if (ctx->dc->caps.max_slave_planes) {
-+				calcs_output->urgent_wm_ns[3].c_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						urgent_watermark[0], bw_int_to_fixed(1000)));
-+				calcs_output->urgent_wm_ns[4].c_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						urgent_watermark[1], bw_int_to_fixed(1000)));
-+			} else {
-+				calcs_output->urgent_wm_ns[3].c_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						urgent_watermark[7], bw_int_to_fixed(1000)));
-+				calcs_output->urgent_wm_ns[4].c_mark =
-+					bw_fixed_to_int(bw_mul(data->
-+						urgent_watermark[8], bw_int_to_fixed(1000)));
-+			}
-+			calcs_output->urgent_wm_ns[5].c_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[9], bw_int_to_fixed(1000)));
-+		}
-+
-+		if (dceip->version == BW_CALCS_VERSION_CARRIZO) {
-+			((struct bw_calcs_vbios *)vbios)->low_yclk = high_yclk;
-+			((struct bw_calcs_vbios *)vbios)->mid_yclk = high_yclk;
-+			((struct bw_calcs_vbios *)vbios)->low_sclk = high_sclk;
-+			((struct bw_calcs_vbios *)vbios)->mid1_sclk = high_sclk;
-+			((struct bw_calcs_vbios *)vbios)->mid2_sclk = high_sclk;
-+			((struct bw_calcs_vbios *)vbios)->mid3_sclk = high_sclk;
-+			((struct bw_calcs_vbios *)vbios)->mid4_sclk = high_sclk;
-+			((struct bw_calcs_vbios *)vbios)->mid5_sclk = high_sclk;
-+			((struct bw_calcs_vbios *)vbios)->mid6_sclk = high_sclk;
-+		} else {
-+			((struct bw_calcs_vbios *)vbios)->low_yclk = mid_yclk;
-+			((struct bw_calcs_vbios *)vbios)->low_sclk = mid3_sclk;
-+			((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid3_sclk;
-+			((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid3_sclk;
-+		}
-+
-+		calculate_bandwidth(dceip, vbios, data);
-+
-+		calcs_output->nbp_state_change_wm_ns[0].d_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[1].d_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
-+		calcs_output->nbp_state_change_wm_ns[2].d_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
-+		if (ctx->dc->caps.max_slave_planes) {
-+			calcs_output->nbp_state_change_wm_ns[3].d_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
-+			calcs_output->nbp_state_change_wm_ns[4].d_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
-+		} else {
-+			calcs_output->nbp_state_change_wm_ns[3].d_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
-+			calcs_output->nbp_state_change_wm_ns[4].d_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
-+		}
-+		calcs_output->nbp_state_change_wm_ns[5].d_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
-+
-+		calcs_output->stutter_exit_wm_ns[0].d_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				stutter_exit_watermark[4], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[1].d_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				stutter_exit_watermark[5], bw_int_to_fixed(1000)));
-+		calcs_output->stutter_exit_wm_ns[2].d_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				stutter_exit_watermark[6], bw_int_to_fixed(1000)));
-+		if (ctx->dc->caps.max_slave_planes) {
-+			calcs_output->stutter_exit_wm_ns[3].d_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[0], bw_int_to_fixed(1000)));
-+			calcs_output->stutter_exit_wm_ns[4].d_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[1], bw_int_to_fixed(1000)));
-+		} else {
-+			calcs_output->stutter_exit_wm_ns[3].d_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[7], bw_int_to_fixed(1000)));
-+			calcs_output->stutter_exit_wm_ns[4].d_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					stutter_exit_watermark[8], bw_int_to_fixed(1000)));
-+		}
-+		calcs_output->stutter_exit_wm_ns[5].d_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				stutter_exit_watermark[9], bw_int_to_fixed(1000)));
-+
-+
-+		calcs_output->urgent_wm_ns[0].d_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				urgent_watermark[4], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[1].d_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				urgent_watermark[5], bw_int_to_fixed(1000)));
-+		calcs_output->urgent_wm_ns[2].d_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				urgent_watermark[6], bw_int_to_fixed(1000)));
-+		if (ctx->dc->caps.max_slave_planes) {
-+			calcs_output->urgent_wm_ns[3].d_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[0], bw_int_to_fixed(1000)));
-+			calcs_output->urgent_wm_ns[4].d_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[1], bw_int_to_fixed(1000)));
-+		} else {
-+			calcs_output->urgent_wm_ns[3].d_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[7], bw_int_to_fixed(1000)));
-+			calcs_output->urgent_wm_ns[4].d_mark =
-+				bw_fixed_to_int(bw_mul(data->
-+					urgent_watermark[8], bw_int_to_fixed(1000)));
-+		}
-+		calcs_output->urgent_wm_ns[5].d_mark =
-+			bw_fixed_to_int(bw_mul(data->
-+				urgent_watermark[9], bw_int_to_fixed(1000)));
-+
-+		((struct bw_calcs_vbios *)vbios)->low_yclk = low_yclk;
-+		((struct bw_calcs_vbios *)vbios)->mid_yclk = mid_yclk;
-+		((struct bw_calcs_vbios *)vbios)->low_sclk = low_sclk;
-+		((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid1_sclk;
-+		((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid2_sclk;
-+		((struct bw_calcs_vbios *)vbios)->mid3_sclk = mid3_sclk;
-+		((struct bw_calcs_vbios *)vbios)->mid4_sclk = mid4_sclk;
-+		((struct bw_calcs_vbios *)vbios)->mid5_sclk = mid5_sclk;
-+		((struct bw_calcs_vbios *)vbios)->mid6_sclk = mid6_sclk;
-+		((struct bw_calcs_vbios *)vbios)->high_sclk = high_sclk;
-+	} else {
-+		calcs_output->nbp_state_change_enable = true;
-+		calcs_output->cpuc_state_change_enable = true;
-+		calcs_output->cpup_state_change_enable = true;
-+		calcs_output->stutter_mode_enable = true;
-+		calcs_output->dispclk_khz = 0;
-+		calcs_output->sclk_khz = 0;
-+	}
-+
-+	kfree(data);
-+
-+	return is_display_configuration_supported(vbios, calcs_output);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c.0130~	2017-12-14 06:39:58.404903560 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c	2017-12-14 06:39:58.404903560 +0100
-@@ -0,0 +1,1899 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dcn_calc_auto.h"
-+#include "dcn_calc_math.h"
-+
-+/*REVISION#250*/
-+void scaler_settings_calculation(struct dcn_bw_internal_vars *v)
-+{
-+	int k;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->allow_different_hratio_vratio == dcn_bw_yes) {
-+			if (v->source_scan[k] == dcn_bw_hor) {
-+				v->h_ratio[k] = v->viewport_width[k] / v->scaler_rec_out_width[k];
-+				v->v_ratio[k] = v->viewport_height[k] / v->scaler_recout_height[k];
-+			}
-+			else {
-+				v->h_ratio[k] = v->viewport_height[k] / v->scaler_rec_out_width[k];
-+				v->v_ratio[k] = v->viewport_width[k] / v->scaler_recout_height[k];
-+			}
-+		}
-+		else {
-+			if (v->source_scan[k] == dcn_bw_hor) {
-+				v->h_ratio[k] =dcn_bw_max2(v->viewport_width[k] / v->scaler_rec_out_width[k], v->viewport_height[k] / v->scaler_recout_height[k]);
-+			}
-+			else {
-+				v->h_ratio[k] =dcn_bw_max2(v->viewport_height[k] / v->scaler_rec_out_width[k], v->viewport_width[k] / v->scaler_recout_height[k]);
-+			}
-+			v->v_ratio[k] = v->h_ratio[k];
-+		}
-+		if (v->interlace_output[k] == 1.0) {
-+			v->v_ratio[k] = 2.0 * v->v_ratio[k];
-+		}
-+		if ((v->underscan_output[k] == 1.0)) {
-+			v->h_ratio[k] = v->h_ratio[k] * v->under_scan_factor;
-+			v->v_ratio[k] = v->v_ratio[k] * v->under_scan_factor;
-+		}
-+	}
-+	/*scaler taps calculation*/
-+
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->h_ratio[k] > 1.0) {
-+			v->acceptable_quality_hta_ps =dcn_bw_min2(v->max_hscl_taps, 2.0 *dcn_bw_ceil2(v->h_ratio[k], 1.0));
-+		}
-+		else if (v->h_ratio[k] < 1.0) {
-+			v->acceptable_quality_hta_ps = 4.0;
-+		}
-+		else {
-+			v->acceptable_quality_hta_ps = 1.0;
-+		}
-+		if (v->ta_pscalculation == dcn_bw_override) {
-+			v->htaps[k] = v->override_hta_ps[k];
-+		}
-+		else {
-+			v->htaps[k] = v->acceptable_quality_hta_ps;
-+		}
-+		if (v->v_ratio[k] > 1.0) {
-+			v->acceptable_quality_vta_ps =dcn_bw_min2(v->max_vscl_taps, 2.0 *dcn_bw_ceil2(v->v_ratio[k], 1.0));
-+		}
-+		else if (v->v_ratio[k] < 1.0) {
-+			v->acceptable_quality_vta_ps = 4.0;
-+		}
-+		else {
-+			v->acceptable_quality_vta_ps = 1.0;
-+		}
-+		if (v->ta_pscalculation == dcn_bw_override) {
-+			v->vtaps[k] = v->override_vta_ps[k];
-+		}
-+		else {
-+			v->vtaps[k] = v->acceptable_quality_vta_ps;
-+		}
-+		if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
-+			v->vta_pschroma[k] = 0.0;
-+			v->hta_pschroma[k] = 0.0;
-+		}
-+		else {
-+			if (v->ta_pscalculation == dcn_bw_override) {
-+				v->vta_pschroma[k] = v->override_vta_pschroma[k];
-+				v->hta_pschroma[k] = v->override_hta_pschroma[k];
-+			}
-+			else {
-+				v->vta_pschroma[k] = v->acceptable_quality_vta_ps;
-+				v->hta_pschroma[k] = v->acceptable_quality_hta_ps;
-+			}
-+		}
-+	}
-+}
-+
-+void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v)
-+{
-+	int i;
-+	int j;
-+	int k;
-+	/*mode support, voltage state and soc configuration*/
-+
-+	/*scale ratio support check*/
-+
-+	v->scale_ratio_support = dcn_bw_yes;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio || v->h_ratio[k] > v->htaps[k] || v->v_ratio[k] > v->vtaps[k] || (v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16 && (v->h_ratio[k] / 2.0 > v->hta_pschroma[k] || v->v_ratio[k] / 2.0 > v->vta_pschroma[k]))) {
-+			v->scale_ratio_support = dcn_bw_no;
-+		}
-+	}
-+	/*source format, pixel format and scan support check*/
-+
-+	v->source_format_pixel_and_scan_support = dcn_bw_yes;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if ((v->source_surface_mode[k] == dcn_bw_sw_linear && v->source_scan[k] != dcn_bw_hor) || ((v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x || v->source_surface_mode[k] == dcn_bw_sw_var_d || v->source_surface_mode[k] == dcn_bw_sw_var_d_x) && v->source_pixel_format[k] != dcn_bw_rgb_sub_64)) {
-+			v->source_format_pixel_and_scan_support = dcn_bw_no;
-+		}
-+	}
-+	/*bandwidth support check*/
-+
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->source_scan[k] == dcn_bw_hor) {
-+			v->swath_width_ysingle_dpp[k] = v->viewport_width[k];
-+		}
-+		else {
-+			v->swath_width_ysingle_dpp[k] = v->viewport_height[k];
-+		}
-+		if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
-+			v->byte_per_pixel_in_dety[k] = 8.0;
-+			v->byte_per_pixel_in_detc[k] = 0.0;
-+		}
-+		else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
-+			v->byte_per_pixel_in_dety[k] = 4.0;
-+			v->byte_per_pixel_in_detc[k] = 0.0;
-+		}
-+		else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
-+			v->byte_per_pixel_in_dety[k] = 2.0;
-+			v->byte_per_pixel_in_detc[k] = 0.0;
-+		}
-+		else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
-+			v->byte_per_pixel_in_dety[k] = 1.0;
-+			v->byte_per_pixel_in_detc[k] = 2.0;
-+		}
-+		else {
-+			v->byte_per_pixel_in_dety[k] = 4.0f / 3.0f;
-+			v->byte_per_pixel_in_detc[k] = 8.0f / 3.0f;
-+		}
-+	}
-+	v->total_read_bandwidth_consumed_gbyte_per_second = 0.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		v->read_bandwidth[k] = v->swath_width_ysingle_dpp[k] * (dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) * v->v_ratio[k] +dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0 * v->v_ratio[k] / 2) / (v->htotal[k] / v->pixel_clock[k]);
-+		if (v->dcc_enable[k] == dcn_bw_yes) {
-+			v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256);
-+		}
-+		if (v->pte_enable == dcn_bw_yes && v->source_scan[k] != dcn_bw_hor && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x)) {
-+			v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 64);
-+		}
-+		else if (v->pte_enable == dcn_bw_yes && v->source_scan[k] == dcn_bw_hor && (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32) && (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x)) {
-+			v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256);
-+		}
-+		else if (v->pte_enable == dcn_bw_yes) {
-+			v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 512);
-+		}
-+		v->total_read_bandwidth_consumed_gbyte_per_second = v->total_read_bandwidth_consumed_gbyte_per_second + v->read_bandwidth[k] / 1000.0;
-+	}
-+	v->total_write_bandwidth_consumed_gbyte_per_second = 0.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) {
-+			v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0;
-+		}
-+		else if (v->output[k] == dcn_bw_writeback) {
-+			v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5;
-+		}
-+		else {
-+			v->write_bandwidth[k] = 0.0;
-+		}
-+		v->total_write_bandwidth_consumed_gbyte_per_second = v->total_write_bandwidth_consumed_gbyte_per_second + v->write_bandwidth[k] / 1000.0;
-+	}
-+	v->total_bandwidth_consumed_gbyte_per_second = v->total_read_bandwidth_consumed_gbyte_per_second + v->total_write_bandwidth_consumed_gbyte_per_second;
-+	v->dcc_enabled_in_any_plane = dcn_bw_no;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->dcc_enable[k] == dcn_bw_yes) {
-+			v->dcc_enabled_in_any_plane = dcn_bw_yes;
-+		}
-+	}
-+	for (i = 0; i <= number_of_states_plus_one; i++) {
-+		v->return_bw_todcn_per_state =dcn_bw_min2(v->return_bus_width * v->dcfclk_per_state[i], v->fabric_and_dram_bandwidth_per_state[i] * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0);
-+		v->return_bw_per_state[i] = v->return_bw_todcn_per_state;
-+		if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0) {
-+			v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], v->return_bw_todcn_per_state * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bw_todcn_per_state - v->dcfclk_per_state[i] * v->return_bus_width / 4.0) + v->urgent_latency)));
-+		}
-+		v->critical_point = 2.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0);
-+		if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0 && v->critical_point < 4.0) {
-+			v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], dcn_bw_pow(4.0 * v->return_bw_todcn_per_state * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2));
-+		}
-+		v->return_bw_todcn_per_state =dcn_bw_min2(v->return_bus_width * v->dcfclk_per_state[i], v->fabric_and_dram_bandwidth_per_state[i] * 1000.0);
-+		if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0) {
-+			v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], v->return_bw_todcn_per_state * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bw_todcn_per_state - v->dcfclk_per_state[i] * v->return_bus_width / 4.0) + v->urgent_latency)));
-+		}
-+		v->critical_point = 2.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0);
-+		if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0 && v->critical_point < 4.0) {
-+			v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], dcn_bw_pow(4.0 * v->return_bw_todcn_per_state * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2));
-+		}
-+	}
-+	for (i = 0; i <= number_of_states_plus_one; i++) {
-+		if ((v->total_read_bandwidth_consumed_gbyte_per_second * 1000.0 <= v->return_bw_per_state[i]) && (v->total_bandwidth_consumed_gbyte_per_second * 1000.0 <= v->fabric_and_dram_bandwidth_per_state[i] * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0)) {
-+			v->bandwidth_support[i] = dcn_bw_yes;
-+		}
-+		else {
-+			v->bandwidth_support[i] = dcn_bw_no;
-+		}
-+	}
-+	/*writeback latency support check*/
-+
-+	v->writeback_latency_support = dcn_bw_yes;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444 && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0 > (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) {
-+			v->writeback_latency_support = dcn_bw_no;
-+		}
-+		else if (v->output[k] == dcn_bw_writeback && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) >dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) {
-+			v->writeback_latency_support = dcn_bw_no;
-+		}
-+	}
-+	/*re-ordering buffer support check*/
-+
-+	for (i = 0; i <= number_of_states_plus_one; i++) {
-+		v->urgent_round_trip_and_out_of_order_latency_per_state[i] = (v->round_trip_ping_latency_cycles + 32.0) / v->dcfclk_per_state[i] + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw_per_state[i];
-+		if ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / v->return_bw_per_state[i] > v->urgent_round_trip_and_out_of_order_latency_per_state[i]) {
-+			v->rob_support[i] = dcn_bw_yes;
-+		}
-+		else {
-+			v->rob_support[i] = dcn_bw_no;
-+		}
-+	}
-+	/*display io support check*/
-+
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->output[k] == dcn_bw_dp && v->dsc_capability == dcn_bw_yes) {
-+			if (v->output_format[k] == dcn_bw_420) {
-+				v->required_output_bw = v->pixel_clock[k] / 2.0;
-+			}
-+			else {
-+				v->required_output_bw = v->pixel_clock[k];
-+			}
-+		}
-+		else if (v->output_format[k] == dcn_bw_420) {
-+			v->required_output_bw = v->pixel_clock[k] * 3.0 / 2.0;
-+		}
-+		else {
-+			v->required_output_bw = v->pixel_clock[k] * 3.0;
-+		}
-+		if (v->output[k] == dcn_bw_hdmi) {
-+			v->required_phyclk[k] = v->required_output_bw;
-+			switch (v->output_deep_color[k]) {
-+			case dcn_bw_encoder_10bpc:
-+				v->required_phyclk[k] =  v->required_phyclk[k] * 5.0 / 4;
-+			break;
-+			case dcn_bw_encoder_12bpc:
-+				v->required_phyclk[k] =  v->required_phyclk[k] * 3.0 / 2;
-+				break;
-+			default:
-+				break;
-+			}
-+			v->required_phyclk[k] = v->required_phyclk[k] / 3.0;
-+		}
-+		else if (v->output[k] == dcn_bw_dp) {
-+			v->required_phyclk[k] = v->required_output_bw / 4.0;
-+		}
-+		else {
-+			v->required_phyclk[k] = 0.0;
-+		}
-+	}
-+	for (i = 0; i <= number_of_states_plus_one; i++) {
-+		v->dio_support[i] = dcn_bw_yes;
-+		for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+			if (v->required_phyclk[k] > v->phyclk_per_state[i] || (v->output[k] == dcn_bw_hdmi && v->required_phyclk[k] > 600.0)) {
-+				v->dio_support[i] = dcn_bw_no;
-+			}
-+		}
-+	}
-+	/*total available writeback support check*/
-+
-+	v->total_number_of_active_writeback = 0.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->output[k] == dcn_bw_writeback) {
-+			v->total_number_of_active_writeback = v->total_number_of_active_writeback + 1.0;
-+		}
-+	}
-+	if (v->total_number_of_active_writeback <= v->max_num_writeback) {
-+		v->total_available_writeback_support = dcn_bw_yes;
-+	}
-+	else {
-+		v->total_available_writeback_support = dcn_bw_no;
-+	}
-+	/*maximum dispclk/dppclk support check*/
-+
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->h_ratio[k] > 1.0) {
-+			v->pscl_factor[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] /dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0));
-+		}
-+		else {
-+			v->pscl_factor[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
-+		}
-+		if (v->byte_per_pixel_in_detc[k] == 0.0) {
-+			v->pscl_factor_chroma[k] = 0.0;
-+			v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], 1.0);
-+		}
-+		else {
-+			if (v->h_ratio[k] / 2.0 > 1.0) {
-+				v->pscl_factor_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0 /dcn_bw_ceil2(v->hta_pschroma[k] / 6.0, 1.0));
-+			}
-+			else {
-+				v->pscl_factor_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
-+			}
-+			v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max5(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_factor_chroma[k], 1.0);
-+		}
-+	}
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
-+			if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+				v->read256_block_height_y[k] = 1.0;
-+			}
-+			else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
-+				v->read256_block_height_y[k] = 4.0;
-+			}
-+			else {
-+				v->read256_block_height_y[k] = 8.0;
-+			}
-+			v->read256_block_width_y[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->read256_block_height_y[k];
-+			v->read256_block_height_c[k] = 0.0;
-+			v->read256_block_width_c[k] = 0.0;
-+		}
-+		else {
-+			if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+				v->read256_block_height_y[k] = 1.0;
-+				v->read256_block_height_c[k] = 1.0;
-+			}
-+			else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
-+				v->read256_block_height_y[k] = 16.0;
-+				v->read256_block_height_c[k] = 8.0;
-+			}
-+			else {
-+				v->read256_block_height_y[k] = 8.0;
-+				v->read256_block_height_c[k] = 8.0;
-+			}
-+			v->read256_block_width_y[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->read256_block_height_y[k];
-+			v->read256_block_width_c[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->read256_block_height_c[k];
-+		}
-+		if (v->source_scan[k] == dcn_bw_hor) {
-+			v->max_swath_height_y[k] = v->read256_block_height_y[k];
-+			v->max_swath_height_c[k] = v->read256_block_height_c[k];
-+		}
-+		else {
-+			v->max_swath_height_y[k] = v->read256_block_width_y[k];
-+			v->max_swath_height_c[k] = v->read256_block_width_c[k];
-+		}
-+		if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
-+			if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) {
-+				v->min_swath_height_y[k] = v->max_swath_height_y[k];
-+			}
-+			else {
-+				v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
-+			}
-+			v->min_swath_height_c[k] = v->max_swath_height_c[k];
-+		}
-+		else {
-+			if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+				v->min_swath_height_y[k] = v->max_swath_height_y[k];
-+				v->min_swath_height_c[k] = v->max_swath_height_c[k];
-+			}
-+			else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) {
-+				v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
-+				if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) {
-+					v->min_swath_height_c[k] = v->max_swath_height_c[k];
-+				}
-+				else {
-+					v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0;
-+				}
-+			}
-+			else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) {
-+				v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0;
-+				if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) {
-+					v->min_swath_height_y[k] = v->max_swath_height_y[k];
-+				}
-+				else {
-+					v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
-+				}
-+			}
-+			else {
-+				v->min_swath_height_y[k] = v->max_swath_height_y[k];
-+				v->min_swath_height_c[k] = v->max_swath_height_c[k];
-+			}
-+		}
-+		if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+			v->maximum_swath_width = 8192.0;
-+		}
-+		else {
-+			v->maximum_swath_width = 5120.0;
-+		}
-+		v->number_of_dpp_required_for_det_size =dcn_bw_ceil2(v->swath_width_ysingle_dpp[k] /dcn_bw_min2(v->maximum_swath_width, v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / (v->byte_per_pixel_in_dety[k] * v->min_swath_height_y[k] + v->byte_per_pixel_in_detc[k] / 2.0 * v->min_swath_height_c[k])), 1.0);
-+		if (v->byte_per_pixel_in_detc[k] == 0.0) {
-+			v->number_of_dpp_required_for_lb_size =dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0);
-+		}
-+		else {
-+			v->number_of_dpp_required_for_lb_size =dcn_bw_max2(dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0),dcn_bw_ceil2((v->vta_pschroma[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k] / 2.0, 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0));
-+		}
-+		v->number_of_dpp_required_for_det_and_lb_size[k] =dcn_bw_max2(v->number_of_dpp_required_for_det_size, v->number_of_dpp_required_for_lb_size);
-+	}
-+	for (i = 0; i <= number_of_states_plus_one; i++) {
-+		for (j = 0; j <= 1; j++) {
-+			v->total_number_of_active_dpp[i][j] = 0.0;
-+			v->required_dispclk[i][j] = 0.0;
-+			v->dispclk_dppclk_support[i][j] = dcn_bw_yes;
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0);
-+				if (v->odm_capability == dcn_bw_yes) {
-+					v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k] / 2.0, v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0);
-+				}
-+				else {
-+					v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0);
-+				}
-+				if (i < number_of_states) {
-+					v->min_dispclk_using_single_dpp = v->min_dispclk_using_single_dpp * (1.0 + v->dispclk_ramping_margin / 100.0);
-+					v->min_dispclk_using_dual_dpp = v->min_dispclk_using_dual_dpp * (1.0 + v->dispclk_ramping_margin / 100.0);
-+				}
-+				if (v->min_dispclk_using_single_dpp <=dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i]) && v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) {
-+					v->no_of_dpp[i][j][k] = 1.0;
-+					v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_single_dpp);
-+				}
-+				else if (v->min_dispclk_using_dual_dpp <=dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) {
-+					v->no_of_dpp[i][j][k] = 2.0;
-+					v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp);
-+				}
-+				else {
-+					v->no_of_dpp[i][j][k] = 2.0;
-+					v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp);
-+					v->dispclk_dppclk_support[i][j] = dcn_bw_no;
-+				}
-+				v->total_number_of_active_dpp[i][j] = v->total_number_of_active_dpp[i][j] + v->no_of_dpp[i][j][k];
-+			}
-+			if (v->total_number_of_active_dpp[i][j] > v->max_num_dpp) {
-+				v->total_number_of_active_dpp[i][j] = 0.0;
-+				v->required_dispclk[i][j] = 0.0;
-+				v->dispclk_dppclk_support[i][j] = dcn_bw_yes;
-+				for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+					v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0);
-+					v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0);
-+					if (i < number_of_states) {
-+						v->min_dispclk_using_single_dpp = v->min_dispclk_using_single_dpp * (1.0 + v->dispclk_ramping_margin / 100.0);
-+						v->min_dispclk_using_dual_dpp = v->min_dispclk_using_dual_dpp * (1.0 + v->dispclk_ramping_margin / 100.0);
-+					}
-+					if (v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) {
-+						v->no_of_dpp[i][j][k] = 1.0;
-+						v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_single_dpp);
-+						if (v->min_dispclk_using_single_dpp >dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) {
-+							v->dispclk_dppclk_support[i][j] = dcn_bw_no;
-+						}
-+					}
-+					else {
-+						v->no_of_dpp[i][j][k] = 2.0;
-+						v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp);
-+						if (v->min_dispclk_using_dual_dpp >dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) {
-+							v->dispclk_dppclk_support[i][j] = dcn_bw_no;
-+						}
-+					}
-+					v->total_number_of_active_dpp[i][j] = v->total_number_of_active_dpp[i][j] + v->no_of_dpp[i][j][k];
-+				}
-+			}
-+		}
-+	}
-+	/*viewport size check*/
-+
-+	v->viewport_size_support = dcn_bw_yes;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->number_of_dpp_required_for_det_and_lb_size[k] > 2.0) {
-+			v->viewport_size_support = dcn_bw_no;
-+		}
-+	}
-+	/*total available pipes support check*/
-+
-+	for (i = 0; i <= number_of_states_plus_one; i++) {
-+		for (j = 0; j <= 1; j++) {
-+			if (v->total_number_of_active_dpp[i][j] <= v->max_num_dpp) {
-+				v->total_available_pipes_support[i][j] = dcn_bw_yes;
-+			}
-+			else {
-+				v->total_available_pipes_support[i][j] = dcn_bw_no;
-+			}
-+		}
-+	}
-+	/*urgent latency support check*/
-+
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		for (i = 0; i <= number_of_states_plus_one; i++) {
-+			for (j = 0; j <= 1; j++) {
-+				v->swath_width_yper_state[i][j][k] = v->swath_width_ysingle_dpp[k] / v->no_of_dpp[i][j][k];
-+				v->swath_width_granularity_y = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->max_swath_height_y[k];
-+				v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] - 1.0, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pixel_in_dety[k] * v->max_swath_height_y[k];
-+				if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
-+					v->rounded_up_max_swath_size_bytes_y =dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_y, 256.0) + 256;
-+				}
-+				if (v->max_swath_height_c[k] > 0.0) {
-+					v->swath_width_granularity_c = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->max_swath_height_c[k];
-+				}
-+				v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] / 2.0 - 1.0, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pixel_in_detc[k] * v->max_swath_height_c[k];
-+				if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
-+					v->rounded_up_max_swath_size_bytes_c =dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_c, 256.0) + 256;
-+				}
-+				if (v->rounded_up_max_swath_size_bytes_y + v->rounded_up_max_swath_size_bytes_c <= v->det_buffer_size_in_kbyte * 1024.0 / 2.0) {
-+					v->swath_height_yper_state[i][j][k] = v->max_swath_height_y[k];
-+					v->swath_height_cper_state[i][j][k] = v->max_swath_height_c[k];
-+				}
-+				else {
-+					v->swath_height_yper_state[i][j][k] = v->min_swath_height_y[k];
-+					v->swath_height_cper_state[i][j][k] = v->min_swath_height_c[k];
-+				}
-+				if (v->byte_per_pixel_in_detc[k] == 0.0) {
-+					v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k];
-+					v->lines_in_det_chroma = 0.0;
-+				}
-+				else if (v->swath_height_yper_state[i][j][k] <= v->swath_height_cper_state[i][j][k]) {
-+					v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k];
-+					v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / v->byte_per_pixel_in_detc[k] / (v->swath_width_yper_state[i][j][k] / 2.0);
-+				}
-+				else {
-+					v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k];
-+					v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0 / 3.0 / v->byte_per_pixel_in_dety[k] / (v->swath_width_yper_state[i][j][k] / 2.0);
-+				}
-+				v->effective_lb_latency_hiding_source_lines_luma =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0);
-+				v->effective_lb_latency_hiding_source_lines_chroma =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0)), 1.0)) - (v->vta_pschroma[k] - 1.0);
-+				v->effective_detlb_lines_luma =dcn_bw_floor2(v->lines_in_det_luma +dcn_bw_min2(v->lines_in_det_luma * v->required_dispclk[i][j] * v->byte_per_pixel_in_dety[k] * v->pscl_factor[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_yper_state[i][j][k]);
-+				v->effective_detlb_lines_chroma =dcn_bw_floor2(v->lines_in_det_chroma +dcn_bw_min2(v->lines_in_det_chroma * v->required_dispclk[i][j] * v->byte_per_pixel_in_detc[k] * v->pscl_factor_chroma[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_cper_state[i][j][k]);
-+				if (v->byte_per_pixel_in_detc[k] == 0.0) {
-+					v->urgent_latency_support_us_per_state[i][j][k] = v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]);
-+				}
-+				else {
-+					v->urgent_latency_support_us_per_state[i][j][k] =dcn_bw_min2(v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]), v->effective_detlb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_detlb_lines_chroma * v->swath_width_yper_state[i][j][k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]));
-+				}
-+			}
-+		}
-+	}
-+	for (i = 0; i <= number_of_states_plus_one; i++) {
-+		for (j = 0; j <= 1; j++) {
-+			v->urgent_latency_support[i][j] = dcn_bw_yes;
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				if (v->urgent_latency_support_us_per_state[i][j][k] < v->urgent_latency / 1.0) {
-+					v->urgent_latency_support[i][j] = dcn_bw_no;
-+				}
-+			}
-+		}
-+	}
-+	/*prefetch check*/
-+
-+	for (i = 0; i <= number_of_states_plus_one; i++) {
-+		for (j = 0; j <= 1; j++) {
-+			v->total_number_of_dcc_active_dpp[i][j] = 0.0;
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				if (v->dcc_enable[k] == dcn_bw_yes) {
-+					v->total_number_of_dcc_active_dpp[i][j] = v->total_number_of_dcc_active_dpp[i][j] + v->no_of_dpp[i][j][k];
-+				}
-+			}
-+		}
-+	}
-+	for (i = 0; i <= number_of_states_plus_one; i++) {
-+		for (j = 0; j <= 1; j++) {
-+			v->projected_dcfclk_deep_sleep = 8.0;
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, v->pixel_clock[k] / 16.0);
-+				if (v->byte_per_pixel_in_detc[k] == 0.0) {
-+					if (v->v_ratio[k] <= 1.0) {
-+						v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 64.0 * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]);
-+					}
-+					else {
-+						v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 64.0 * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j));
-+					}
-+				}
-+				else {
-+					if (v->v_ratio[k] <= 1.0) {
-+						v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 32.0 * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]);
-+					}
-+					else {
-+						v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 32.0 * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j));
-+					}
-+					if (v->v_ratio[k] / 2.0 <= 1.0) {
-+						v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 32.0 * v->h_ratio[k] / 2.0 * v->pixel_clock[k] / v->no_of_dpp[i][j][k]);
-+					}
-+					else {
-+						v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 32.0 * v->pscl_factor_chroma[k] * v->required_dispclk[i][j] / (1 + j));
-+					}
-+				}
-+			}
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				if (v->dcc_enable[k] == dcn_bw_yes) {
-+					v->meta_req_height_y = 8.0 * v->read256_block_height_y[k];
-+					v->meta_req_width_y = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->meta_req_height_y;
-+					v->meta_surface_width_y =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0, v->meta_req_width_y) + v->meta_req_width_y;
-+					v->meta_surface_height_y =dcn_bw_ceil2(v->viewport_height[k] - 1.0, v->meta_req_height_y) + v->meta_req_height_y;
-+					if (v->pte_enable == dcn_bw_yes) {
-+						v->meta_pte_bytes_per_frame_y = (dcn_bw_ceil2((v->meta_surface_width_y * v->meta_surface_height_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
-+					}
-+					else {
-+						v->meta_pte_bytes_per_frame_y = 0.0;
-+					}
-+					if (v->source_scan[k] == dcn_bw_hor) {
-+						v->meta_row_bytes_y = v->meta_surface_width_y * v->meta_req_height_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0;
-+					}
-+					else {
-+						v->meta_row_bytes_y = v->meta_surface_height_y * v->meta_req_width_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0;
-+					}
-+				}
-+				else {
-+					v->meta_pte_bytes_per_frame_y = 0.0;
-+					v->meta_row_bytes_y = 0.0;
-+				}
-+				if (v->pte_enable == dcn_bw_yes) {
-+					if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+						v->macro_tile_block_size_bytes_y = 256.0;
-+						v->macro_tile_block_height_y = 1.0;
-+					}
-+					else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
-+						v->macro_tile_block_size_bytes_y = 4096.0;
-+						v->macro_tile_block_height_y = 4.0 * v->read256_block_height_y[k];
-+					}
-+					else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
-+						v->macro_tile_block_size_bytes_y = 64.0 * 1024;
-+						v->macro_tile_block_height_y = 16.0 * v->read256_block_height_y[k];
-+					}
-+					else {
-+						v->macro_tile_block_size_bytes_y = 256.0 * 1024;
-+						v->macro_tile_block_height_y = 32.0 * v->read256_block_height_y[k];
-+					}
-+					if (v->macro_tile_block_size_bytes_y <= 65536.0) {
-+						v->data_pte_req_height_y = v->macro_tile_block_height_y;
-+					}
-+					else {
-+						v->data_pte_req_height_y = 16.0 * v->read256_block_height_y[k];
-+					}
-+					v->data_pte_req_width_y = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->data_pte_req_height_y * 8;
-+					if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+						v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_y / (v->viewport_width[k] / v->no_of_dpp[i][j][k]), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_y, 1.0) + 1);
-+					}
-+					else if (v->source_scan[k] == dcn_bw_hor) {
-+						v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0) / v->data_pte_req_width_y, 1.0) + 1);
-+					}
-+					else {
-+						v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] - 1.0) / v->data_pte_req_height_y, 1.0) + 1);
-+					}
-+				}
-+				else {
-+					v->dpte_bytes_per_row_y = 0.0;
-+				}
-+				if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
-+					if (v->dcc_enable[k] == dcn_bw_yes) {
-+						v->meta_req_height_c = 8.0 * v->read256_block_height_c[k];
-+						v->meta_req_width_c = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->meta_req_height_c;
-+						v->meta_surface_width_c =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0, v->meta_req_width_c) + v->meta_req_width_c;
-+						v->meta_surface_height_c =dcn_bw_ceil2(v->viewport_height[k] / 2.0 - 1.0, v->meta_req_height_c) + v->meta_req_height_c;
-+						if (v->pte_enable == dcn_bw_yes) {
-+							v->meta_pte_bytes_per_frame_c = (dcn_bw_ceil2((v->meta_surface_width_c * v->meta_surface_height_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
-+						}
-+						else {
-+							v->meta_pte_bytes_per_frame_c = 0.0;
-+						}
-+						if (v->source_scan[k] == dcn_bw_hor) {
-+							v->meta_row_bytes_c = v->meta_surface_width_c * v->meta_req_height_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0;
-+						}
-+						else {
-+							v->meta_row_bytes_c = v->meta_surface_height_c * v->meta_req_width_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0;
-+						}
-+					}
-+					else {
-+						v->meta_pte_bytes_per_frame_c = 0.0;
-+						v->meta_row_bytes_c = 0.0;
-+					}
-+					if (v->pte_enable == dcn_bw_yes) {
-+						if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+							v->macro_tile_block_size_bytes_c = 256.0;
-+							v->macro_tile_block_height_c = 1.0;
-+						}
-+						else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
-+							v->macro_tile_block_size_bytes_c = 4096.0;
-+							v->macro_tile_block_height_c = 4.0 * v->read256_block_height_c[k];
-+						}
-+						else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
-+							v->macro_tile_block_size_bytes_c = 64.0 * 1024;
-+							v->macro_tile_block_height_c = 16.0 * v->read256_block_height_c[k];
-+						}
-+						else {
-+							v->macro_tile_block_size_bytes_c = 256.0 * 1024;
-+							v->macro_tile_block_height_c = 32.0 * v->read256_block_height_c[k];
-+						}
-+						v->macro_tile_block_width_c = v->macro_tile_block_size_bytes_c /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->macro_tile_block_height_c;
-+						if (v->macro_tile_block_size_bytes_c <= 65536.0) {
-+							v->data_pte_req_height_c = v->macro_tile_block_height_c;
-+						}
-+						else {
-+							v->data_pte_req_height_c = 16.0 * v->read256_block_height_c[k];
-+						}
-+						v->data_pte_req_width_c = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->data_pte_req_height_c * 8;
-+						if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+							v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 * dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_c / (v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_c, 1.0) + 1);
-+						}
-+						else if (v->source_scan[k] == dcn_bw_hor) {
-+							v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0) / v->data_pte_req_width_c, 1.0) + 1);
-+						}
-+						else {
-+							v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] / 2.0 - 1.0) / v->data_pte_req_height_c, 1.0) + 1);
-+						}
-+					}
-+					else {
-+						v->dpte_bytes_per_row_c = 0.0;
-+					}
-+				}
-+				else {
-+					v->dpte_bytes_per_row_c = 0.0;
-+					v->meta_pte_bytes_per_frame_c = 0.0;
-+					v->meta_row_bytes_c = 0.0;
-+				}
-+				v->dpte_bytes_per_row[k] = v->dpte_bytes_per_row_y + v->dpte_bytes_per_row_c;
-+				v->meta_pte_bytes_per_frame[k] = v->meta_pte_bytes_per_frame_y + v->meta_pte_bytes_per_frame_c;
-+				v->meta_row_bytes[k] = v->meta_row_bytes_y + v->meta_row_bytes_c;
-+				v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0;
-+				v->prefill_y[k] =dcn_bw_floor2(v->v_init_y, 1.0);
-+				v->max_num_sw_y[k] =dcn_bw_ceil2((v->prefill_y[k] - 1.0) / v->swath_height_yper_state[i][j][k], 1.0) + 1;
-+				if (v->prefill_y[k] > 1.0) {
-+					v->max_partial_sw_y =dcn_bw_mod((v->prefill_y[k] - 2.0), v->swath_height_yper_state[i][j][k]);
-+				}
-+				else {
-+					v->max_partial_sw_y =dcn_bw_mod((v->prefill_y[k] + v->swath_height_yper_state[i][j][k] - 2.0), v->swath_height_yper_state[i][j][k]);
-+				}
-+				v->max_partial_sw_y =dcn_bw_max2(1.0, v->max_partial_sw_y);
-+				v->prefetch_lines_y[k] = v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k] + v->max_partial_sw_y;
-+				if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
-+					v->v_init_c = (v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0;
-+					v->prefill_c[k] =dcn_bw_floor2(v->v_init_c, 1.0);
-+					v->max_num_sw_c[k] =dcn_bw_ceil2((v->prefill_c[k] - 1.0) / v->swath_height_cper_state[i][j][k], 1.0) + 1;
-+					if (v->prefill_c[k] > 1.0) {
-+						v->max_partial_sw_c =dcn_bw_mod((v->prefill_c[k] - 2.0), v->swath_height_cper_state[i][j][k]);
-+					}
-+					else {
-+						v->max_partial_sw_c =dcn_bw_mod((v->prefill_c[k] + v->swath_height_cper_state[i][j][k] - 2.0), v->swath_height_cper_state[i][j][k]);
-+					}
-+					v->max_partial_sw_c =dcn_bw_max2(1.0, v->max_partial_sw_c);
-+					v->prefetch_lines_c[k] = v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k] + v->max_partial_sw_c;
-+				}
-+				else {
-+					v->prefetch_lines_c[k] = 0.0;
-+				}
-+				v->dst_x_after_scaler = 90.0 * v->pixel_clock[k] / (v->required_dispclk[i][j] / (j + 1)) + 42.0 * v->pixel_clock[k] / v->required_dispclk[i][j];
-+				if (v->no_of_dpp[i][j][k] > 1.0) {
-+					v->dst_x_after_scaler = v->dst_x_after_scaler + v->scaler_rec_out_width[k] / 2.0;
-+				}
-+				if (v->output_format[k] == dcn_bw_420) {
-+					v->dst_y_after_scaler = 1.0;
-+				}
-+				else {
-+					v->dst_y_after_scaler = 0.0;
-+				}
-+				v->time_calc = 24.0 / v->projected_dcfclk_deep_sleep;
-+				v->v_update_offset[k] =dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
-+				v->total_repeater_delay = v->max_inter_dcn_tile_repeaters * (2.0 / (v->required_dispclk[i][j] / (j + 1)) + 3.0 / v->required_dispclk[i][j]);
-+				v->v_update_width[k] = (14.0 / v->projected_dcfclk_deep_sleep + 12.0 / (v->required_dispclk[i][j] / (j + 1)) + v->total_repeater_delay) * v->pixel_clock[k];
-+				v->v_ready_offset[k] =dcn_bw_max2(150.0 / (v->required_dispclk[i][j] / (j + 1)), v->total_repeater_delay + 20.0 / v->projected_dcfclk_deep_sleep + 10.0 / (v->required_dispclk[i][j] / (j + 1))) * v->pixel_clock[k];
-+				v->time_setup = (v->v_update_offset[k] + v->v_update_width[k] + v->v_ready_offset[k]) / v->pixel_clock[k];
-+				v->extra_latency = v->urgent_round_trip_and_out_of_order_latency_per_state[i] + (v->total_number_of_active_dpp[i][j] * v->pixel_chunk_size_in_kbyte + v->total_number_of_dcc_active_dpp[i][j] * v->meta_chunk_size) * 1024.0 / v->return_bw_per_state[i];
-+				if (v->pte_enable == dcn_bw_yes) {
-+					v->extra_latency = v->extra_latency + v->total_number_of_active_dpp[i][j] * v->pte_chunk_size * 1024.0 / v->return_bw_per_state[i];
-+				}
-+				if (v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes) {
-+					v->maximum_vstartup = v->vtotal[k] - v->vactive[k] - 1.0;
-+				}
-+				else {
-+					v->maximum_vstartup = v->v_sync_plus_back_porch[k] - 1.0;
-+				}
-+				v->line_times_for_prefetch[k] = v->maximum_vstartup - v->urgent_latency / (v->htotal[k] / v->pixel_clock[k]) - (v->time_calc + v->time_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dst_y_after_scaler + v->dst_x_after_scaler / v->htotal[k]);
-+				v->line_times_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->line_times_for_prefetch[k] + 0.125), 1.0) / 4;
-+				v->prefetch_bw[k] = (v->meta_pte_bytes_per_frame[k] + 2.0 * v->meta_row_bytes[k] + 2.0 * v->dpte_bytes_per_row[k] + v->prefetch_lines_y[k] * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] * v->swath_width_yper_state[i][j][k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0)) / (v->line_times_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]);
-+			}
-+			v->bw_available_for_immediate_flip = v->return_bw_per_state[i];
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				v->bw_available_for_immediate_flip = v->bw_available_for_immediate_flip -dcn_bw_max2(v->read_bandwidth[k], v->prefetch_bw[k]);
-+			}
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				v->total_immediate_flip_bytes[k] = 0.0;
-+				if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
-+					v->total_immediate_flip_bytes[k] = v->total_immediate_flip_bytes[k] + v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k];
-+				}
-+			}
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
-+					v->time_for_meta_pte_with_immediate_flip =dcn_bw_max5(v->meta_pte_bytes_per_frame[k] / v->prefetch_bw[k], v->meta_pte_bytes_per_frame[k] * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
-+					v->time_for_meta_pte_without_immediate_flip =dcn_bw_max3(v->meta_pte_bytes_per_frame[k] / v->prefetch_bw[k], v->extra_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
-+				}
-+				else {
-+					v->time_for_meta_pte_with_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0;
-+					v->time_for_meta_pte_without_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0;
-+				}
-+				if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
-+					v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max5((v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k], (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency, 2.0 * v->urgent_latency);
-+					v->time_for_meta_and_dpte_row_without_immediate_flip =dcn_bw_max3((v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k], v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip, v->extra_latency);
-+				}
-+				else {
-+					v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max2(v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency - v->time_for_meta_pte_with_immediate_flip);
-+					v->time_for_meta_and_dpte_row_without_immediate_flip =dcn_bw_max2(v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip, v->extra_latency - v->time_for_meta_pte_without_immediate_flip);
-+				}
-+				v->lines_for_meta_pte_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
-+				v->lines_for_meta_pte_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
-+				v->lines_for_meta_and_dpte_row_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
-+				v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
-+				v->line_times_to_request_prefetch_pixel_data_with_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_with_immediate_flip[k] - v->lines_for_meta_and_dpte_row_with_immediate_flip[k];
-+				v->line_times_to_request_prefetch_pixel_data_without_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_without_immediate_flip[k] - v->lines_for_meta_and_dpte_row_without_immediate_flip[k];
-+				if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip > 0.0) {
-+					v->v_ratio_pre_ywith_immediate_flip[i][j][k] = v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip;
-+					if ((v->swath_height_yper_state[i][j][k] > 4.0)) {
-+						if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0 > 0.0) {
-+							v->v_ratio_pre_ywith_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_ywith_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0));
-+						}
-+						else {
-+							v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0;
-+						}
-+					}
-+					v->v_ratio_pre_cwith_immediate_flip[i][j][k] = v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip;
-+					if ((v->swath_height_cper_state[i][j][k] > 4.0)) {
-+						if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0 > 0.0) {
-+							v->v_ratio_pre_cwith_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_cwith_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0));
-+						}
-+						else {
-+							v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0;
-+						}
-+					}
-+					v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]);
-+				}
-+				else {
-+					v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0;
-+					v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0;
-+					v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = 999999.0;
-+				}
-+				if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip > 0.0) {
-+					v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip;
-+					if ((v->swath_height_yper_state[i][j][k] > 4.0)) {
-+						if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0 > 0.0) {
-+							v->v_ratio_pre_ywithout_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_ywithout_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0));
-+						}
-+						else {
-+							v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0;
-+						}
-+					}
-+					v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip;
-+					if ((v->swath_height_cper_state[i][j][k] > 4.0)) {
-+						if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0 > 0.0) {
-+							v->v_ratio_pre_cwithout_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_cwithout_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0));
-+						}
-+						else {
-+							v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0;
-+						}
-+					}
-+					v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]);
-+				}
-+				else {
-+					v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0;
-+					v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0;
-+					v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = 999999.0;
-+				}
-+			}
-+			v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = 0.0;
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
-+					v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k]) +dcn_bw_max2(v->meta_pte_bytes_per_frame[k] / (v->lines_for_meta_pte_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / (v->lines_for_meta_and_dpte_row_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k]));
-+				}
-+				else {
-+					v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]);
-+				}
-+			}
-+			v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = 0.0;
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = v->maximum_read_bandwidth_with_prefetch_without_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]);
-+			}
-+			v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_yes;
-+			if (v->maximum_read_bandwidth_with_prefetch_with_immediate_flip > v->return_bw_per_state[i]) {
-+				v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no;
-+			}
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				if (v->line_times_for_prefetch[k] < 2.0 || v->lines_for_meta_pte_with_immediate_flip[k] >= 8.0 || v->lines_for_meta_and_dpte_row_with_immediate_flip[k] >= 16.0) {
-+					v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no;
-+				}
-+			}
-+			v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_yes;
-+			if (v->maximum_read_bandwidth_with_prefetch_without_immediate_flip > v->return_bw_per_state[i]) {
-+				v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no;
-+			}
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				if (v->line_times_for_prefetch[k] < 2.0 || v->lines_for_meta_pte_without_immediate_flip[k] >= 8.0 || v->lines_for_meta_and_dpte_row_without_immediate_flip[k] >= 16.0) {
-+					v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no;
-+				}
-+			}
-+		}
-+	}
-+	for (i = 0; i <= number_of_states_plus_one; i++) {
-+		for (j = 0; j <= 1; j++) {
-+			v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] = dcn_bw_yes;
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				if ((((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywith_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwith_immediate_flip[i][j][k] > 4.0)) || ((v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 || v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0)))) {
-+					v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no;
-+				}
-+			}
-+			v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] = dcn_bw_yes;
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				if ((v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0)) {
-+					v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no;
-+				}
-+			}
-+		}
-+	}
-+	/*mode support, voltage state and soc configuration*/
-+
-+	for (i = number_of_states_plus_one; i >= 0; i--) {
-+		for (j = 0; j <= 1; j++) {
-+			if (v->scale_ratio_support == dcn_bw_yes && v->source_format_pixel_and_scan_support == dcn_bw_yes && v->viewport_size_support == dcn_bw_yes && v->bandwidth_support[i] == dcn_bw_yes && v->dio_support[i] == dcn_bw_yes && v->urgent_latency_support[i][j] == dcn_bw_yes && v->rob_support[i] == dcn_bw_yes && v->dispclk_dppclk_support[i][j] == dcn_bw_yes && v->total_available_pipes_support[i][j] == dcn_bw_yes && v->total_available_writeback_support == dcn_bw_yes && v->writeback_latency_support == dcn_bw_yes) {
-+				if (v->prefetch_supported_with_immediate_flip[i][j] == dcn_bw_yes && v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] == dcn_bw_yes) {
-+					v->mode_support_with_immediate_flip[i][j] = dcn_bw_yes;
-+				}
-+				else {
-+					v->mode_support_with_immediate_flip[i][j] = dcn_bw_no;
-+				}
-+				if (v->prefetch_supported_without_immediate_flip[i][j] == dcn_bw_yes && v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] == dcn_bw_yes) {
-+					v->mode_support_without_immediate_flip[i][j] = dcn_bw_yes;
-+				}
-+				else {
-+					v->mode_support_without_immediate_flip[i][j] = dcn_bw_no;
-+				}
-+			}
-+			else {
-+				v->mode_support_with_immediate_flip[i][j] = dcn_bw_no;
-+				v->mode_support_without_immediate_flip[i][j] = dcn_bw_no;
-+			}
-+		}
-+	}
-+	for (i = number_of_states_plus_one; i >= 0; i--) {
-+		if ((i == number_of_states_plus_one || v->mode_support_with_immediate_flip[i][1] == dcn_bw_yes || v->mode_support_with_immediate_flip[i][0] == dcn_bw_yes) && i >= v->voltage_override_level) {
-+			v->voltage_level_with_immediate_flip = i;
-+		}
-+	}
-+	for (i = number_of_states_plus_one; i >= 0; i--) {
-+		if ((i == number_of_states_plus_one || v->mode_support_without_immediate_flip[i][1] == dcn_bw_yes || v->mode_support_without_immediate_flip[i][0] == dcn_bw_yes) && i >= v->voltage_override_level) {
-+			v->voltage_level_without_immediate_flip = i;
-+		}
-+	}
-+	if (v->voltage_level_with_immediate_flip == number_of_states_plus_one) {
-+		v->immediate_flip_supported = dcn_bw_no;
-+		v->voltage_level = v->voltage_level_without_immediate_flip;
-+	}
-+	else {
-+		v->immediate_flip_supported = dcn_bw_yes;
-+		v->voltage_level = v->voltage_level_with_immediate_flip;
-+	}
-+	v->dcfclk = v->dcfclk_per_state[v->voltage_level];
-+	v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
-+	for (j = 0; j <= 1; j++) {
-+		v->required_dispclk_per_ratio[j] = v->required_dispclk[v->voltage_level][j];
-+		for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+			v->dpp_per_plane_per_ratio[j][k] = v->no_of_dpp[v->voltage_level][j][k];
-+		}
-+		v->dispclk_dppclk_support_per_ratio[j] = v->dispclk_dppclk_support[v->voltage_level][j];
-+	}
-+	v->max_phyclk = v->phyclk_per_state[v->voltage_level];
-+}
-+void display_pipe_configuration(struct dcn_bw_internal_vars *v)
-+{
-+	int j;
-+	int k;
-+	/*display pipe configuration*/
-+
-+	for (j = 0; j <= 1; j++) {
-+		v->total_number_of_active_dpp_per_ratio[j] = 0.0;
-+		for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+			v->total_number_of_active_dpp_per_ratio[j] = v->total_number_of_active_dpp_per_ratio[j] + v->dpp_per_plane_per_ratio[j][k];
-+		}
-+	}
-+	if ((v->dispclk_dppclk_support_per_ratio[0] == dcn_bw_yes && v->dispclk_dppclk_support_per_ratio[1] == dcn_bw_no) || (v->dispclk_dppclk_support_per_ratio[0] == v->dispclk_dppclk_support_per_ratio[1] && (v->total_number_of_active_dpp_per_ratio[0] < v->total_number_of_active_dpp_per_ratio[1] || (((v->total_number_of_active_dpp_per_ratio[0] == v->total_number_of_active_dpp_per_ratio[1]) && v->required_dispclk_per_ratio[0] <= 0.5 * v->required_dispclk_per_ratio[1]))))) {
-+		v->dispclk_dppclk_ratio = 1;
-+		v->final_error_message = v->error_message[0];
-+	}
-+	else {
-+		v->dispclk_dppclk_ratio = 2;
-+		v->final_error_message = v->error_message[1];
-+	}
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		v->dpp_per_plane[k] = v->dpp_per_plane_per_ratio[v->dispclk_dppclk_ratio - 1][k];
-+	}
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
-+			v->byte_per_pix_dety = 8.0;
-+			v->byte_per_pix_detc = 0.0;
-+		}
-+		else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
-+			v->byte_per_pix_dety = 4.0;
-+			v->byte_per_pix_detc = 0.0;
-+		}
-+		else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
-+			v->byte_per_pix_dety = 2.0;
-+			v->byte_per_pix_detc = 0.0;
-+		}
-+		else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
-+			v->byte_per_pix_dety = 1.0;
-+			v->byte_per_pix_detc = 2.0;
-+		}
-+		else {
-+			v->byte_per_pix_dety = 4.0f / 3.0f;
-+			v->byte_per_pix_detc = 8.0f / 3.0f;
-+		}
-+		if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
-+			if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+				v->read256_bytes_block_height_y = 1.0;
-+			}
-+			else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
-+				v->read256_bytes_block_height_y = 4.0;
-+			}
-+			else {
-+				v->read256_bytes_block_height_y = 8.0;
-+			}
-+			v->read256_bytes_block_width_y = 256.0 /dcn_bw_ceil2(v->byte_per_pix_dety, 1.0) / v->read256_bytes_block_height_y;
-+			v->read256_bytes_block_height_c = 0.0;
-+			v->read256_bytes_block_width_c = 0.0;
-+		}
-+		else {
-+			if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+				v->read256_bytes_block_height_y = 1.0;
-+				v->read256_bytes_block_height_c = 1.0;
-+			}
-+			else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
-+				v->read256_bytes_block_height_y = 16.0;
-+				v->read256_bytes_block_height_c = 8.0;
-+			}
-+			else {
-+				v->read256_bytes_block_height_y = 8.0;
-+				v->read256_bytes_block_height_c = 8.0;
-+			}
-+			v->read256_bytes_block_width_y = 256.0 /dcn_bw_ceil2(v->byte_per_pix_dety, 1.0) / v->read256_bytes_block_height_y;
-+			v->read256_bytes_block_width_c = 256.0 /dcn_bw_ceil2(v->byte_per_pix_detc, 2.0) / v->read256_bytes_block_height_c;
-+		}
-+		if (v->source_scan[k] == dcn_bw_hor) {
-+			v->maximum_swath_height_y = v->read256_bytes_block_height_y;
-+			v->maximum_swath_height_c = v->read256_bytes_block_height_c;
-+		}
-+		else {
-+			v->maximum_swath_height_y = v->read256_bytes_block_width_y;
-+			v->maximum_swath_height_c = v->read256_bytes_block_width_c;
-+		}
-+		if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
-+			if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) {
-+				v->minimum_swath_height_y = v->maximum_swath_height_y;
-+			}
-+			else {
-+				v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0;
-+			}
-+			v->minimum_swath_height_c = v->maximum_swath_height_c;
-+		}
-+		else {
-+			if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+				v->minimum_swath_height_y = v->maximum_swath_height_y;
-+				v->minimum_swath_height_c = v->maximum_swath_height_c;
-+			}
-+			else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) {
-+				v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0;
-+				if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) {
-+					v->minimum_swath_height_c = v->maximum_swath_height_c;
-+				}
-+				else {
-+					v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0;
-+				}
-+			}
-+			else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) {
-+				v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0;
-+				if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) {
-+					v->minimum_swath_height_y = v->maximum_swath_height_y;
-+				}
-+				else {
-+					v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0;
-+				}
-+			}
-+			else {
-+				v->minimum_swath_height_y = v->maximum_swath_height_y;
-+				v->minimum_swath_height_c = v->maximum_swath_height_c;
-+			}
-+		}
-+		if (v->source_scan[k] == dcn_bw_hor) {
-+			v->swath_width = v->viewport_width[k] / v->dpp_per_plane[k];
-+		}
-+		else {
-+			v->swath_width = v->viewport_height[k] / v->dpp_per_plane[k];
-+		}
-+		v->swath_width_granularity_y = 256.0 /dcn_bw_ceil2(v->byte_per_pix_dety, 1.0) / v->maximum_swath_height_y;
-+		v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width - 1.0, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pix_dety * v->maximum_swath_height_y;
-+		if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
-+			v->rounded_up_max_swath_size_bytes_y =dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_y, 256.0) + 256;
-+		}
-+		if (v->maximum_swath_height_c > 0.0) {
-+			v->swath_width_granularity_c = 256.0 /dcn_bw_ceil2(v->byte_per_pix_detc, 2.0) / v->maximum_swath_height_c;
-+		}
-+		v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width / 2.0 - 1.0, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pix_detc * v->maximum_swath_height_c;
-+		if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
-+			v->rounded_up_max_swath_size_bytes_c =dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_c, 256.0) + 256;
-+		}
-+		if (v->rounded_up_max_swath_size_bytes_y + v->rounded_up_max_swath_size_bytes_c <= v->det_buffer_size_in_kbyte * 1024.0 / 2.0) {
-+			v->swath_height_y[k] = v->maximum_swath_height_y;
-+			v->swath_height_c[k] = v->maximum_swath_height_c;
-+		}
-+		else {
-+			v->swath_height_y[k] = v->minimum_swath_height_y;
-+			v->swath_height_c[k] = v->minimum_swath_height_c;
-+		}
-+		if (v->swath_height_c[k] == 0.0) {
-+			v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0;
-+			v->det_buffer_size_c[k] = 0.0;
-+		}
-+		else if (v->swath_height_y[k] <= v->swath_height_c[k]) {
-+			v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0;
-+			v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0;
-+		}
-+		else {
-+			v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0;
-+			v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 3.0;
-+		}
-+	}
-+}
-+void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(struct dcn_bw_internal_vars *v)
-+{
-+	int k;
-+	/*dispclk and dppclk calculation*/
-+
-+	v->dispclk_with_ramping = 0.0;
-+	v->dispclk_without_ramping = 0.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->h_ratio[k] > 1.0) {
-+			v->pscl_throughput[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] /dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0));
-+		}
-+		else {
-+			v->pscl_throughput[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
-+		}
-+		v->dppclk_using_single_dpp_luma = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_throughput[k], 1.0);
-+		if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
-+			v->pscl_throughput_chroma[k] = 0.0;
-+			v->dppclk_using_single_dpp = v->dppclk_using_single_dpp_luma;
-+		}
-+		else {
-+			if (v->h_ratio[k] > 1.0) {
-+				v->pscl_throughput_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0 /dcn_bw_ceil2(v->hta_pschroma[k] / 6.0, 1.0));
-+			}
-+			else {
-+				v->pscl_throughput_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
-+			}
-+			v->dppclk_using_single_dpp_chroma = v->pixel_clock[k] *dcn_bw_max3(v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_throughput_chroma[k], 1.0);
-+			v->dppclk_using_single_dpp =dcn_bw_max2(v->dppclk_using_single_dpp_luma, v->dppclk_using_single_dpp_chroma);
-+		}
-+		if (v->odm_capable == dcn_bw_yes) {
-+			v->dispclk_with_ramping =dcn_bw_max2(v->dispclk_with_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0 + v->downspreading / 100.0) * (1.0 + v->dispclk_ramping_margin / 100.0));
-+			v->dispclk_without_ramping =dcn_bw_max2(v->dispclk_without_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0 + v->downspreading / 100.0));
-+		}
-+		else {
-+			v->dispclk_with_ramping =dcn_bw_max2(v->dispclk_with_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0 + v->downspreading / 100.0) * (1.0 + v->dispclk_ramping_margin / 100.0));
-+			v->dispclk_without_ramping =dcn_bw_max2(v->dispclk_without_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0 + v->downspreading / 100.0));
-+		}
-+	}
-+	if (v->dispclk_without_ramping > v->max_dispclk[number_of_states]) {
-+		v->dispclk = v->dispclk_without_ramping;
-+	}
-+	else if (v->dispclk_with_ramping > v->max_dispclk[number_of_states]) {
-+		v->dispclk = v->max_dispclk[number_of_states];
-+	}
-+	else {
-+		v->dispclk = v->dispclk_with_ramping;
-+	}
-+	v->dppclk = v->dispclk / v->dispclk_dppclk_ratio;
-+	/*urgent watermark*/
-+
-+	v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0);
-+	v->dcc_enabled_any_plane = dcn_bw_no;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->dcc_enable[k] == dcn_bw_yes) {
-+			v->dcc_enabled_any_plane = dcn_bw_yes;
-+		}
-+	}
-+	v->return_bw = v->return_bandwidth_to_dcn;
-+	if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) {
-+		v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency)));
-+	}
-+	v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0);
-+	if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0 && v->critical_compression < 4.0) {
-+		v->return_bw =dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0 * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2));
-+	}
-+	v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0);
-+	if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) {
-+		v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency)));
-+	}
-+	v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0);
-+	if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0 && v->critical_compression < 4.0) {
-+		v->return_bw =dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0 * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2));
-+	}
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->source_scan[k] == dcn_bw_hor) {
-+			v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
-+		}
-+		else {
-+			v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
-+		}
-+	}
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
-+			v->byte_per_pixel_dety[k] = 8.0;
-+			v->byte_per_pixel_detc[k] = 0.0;
-+		}
-+		else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
-+			v->byte_per_pixel_dety[k] = 4.0;
-+			v->byte_per_pixel_detc[k] = 0.0;
-+		}
-+		else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
-+			v->byte_per_pixel_dety[k] = 2.0;
-+			v->byte_per_pixel_detc[k] = 0.0;
-+		}
-+		else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
-+			v->byte_per_pixel_dety[k] = 1.0;
-+			v->byte_per_pixel_detc[k] = 2.0;
-+		}
-+		else {
-+			v->byte_per_pixel_dety[k] = 4.0f / 3.0f;
-+			v->byte_per_pixel_detc[k] = 8.0f / 3.0f;
-+		}
-+	}
-+	v->total_data_read_bandwidth = 0.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
-+		v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
-+		v->total_data_read_bandwidth = v->total_data_read_bandwidth + v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k];
-+	}
-+	v->total_active_dpp = 0.0;
-+	v->total_dcc_active_dpp = 0.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		v->total_active_dpp = v->total_active_dpp + v->dpp_per_plane[k];
-+		if (v->dcc_enable[k] == dcn_bw_yes) {
-+			v->total_dcc_active_dpp = v->total_dcc_active_dpp + v->dpp_per_plane[k];
-+		}
-+	}
-+	v->urgent_round_trip_and_out_of_order_latency = (v->round_trip_ping_latency_cycles + 32.0) / v->dcfclk + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw;
-+	v->last_pixel_of_line_extra_watermark = 0.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->v_ratio[k] <= 1.0) {
-+			v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
-+		}
-+		else {
-+			v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk;
-+		}
-+		v->data_fabric_line_delivery_time_luma = v->swath_width_y[k] * v->swath_height_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->return_bw * v->read_bandwidth_plane_luma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth);
-+		v->last_pixel_of_line_extra_watermark =dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_luma - v->display_pipe_line_delivery_time_luma[k]);
-+		if (v->byte_per_pixel_detc[k] == 0.0) {
-+			v->display_pipe_line_delivery_time_chroma[k] = 0.0;
-+		}
-+		else {
-+			if (v->v_ratio[k] / 2.0 <= 1.0) {
-+				v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] / (v->h_ratio[k] / 2.0) / v->pixel_clock[k];
-+			}
-+			else {
-+				v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk;
-+			}
-+			v->data_fabric_line_delivery_time_chroma = v->swath_width_y[k] / 2.0 * v->swath_height_c[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->return_bw * v->read_bandwidth_plane_chroma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth);
-+			v->last_pixel_of_line_extra_watermark =dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_chroma - v->display_pipe_line_delivery_time_chroma[k]);
-+		}
-+	}
-+	v->urgent_extra_latency = v->urgent_round_trip_and_out_of_order_latency + (v->total_active_dpp * v->pixel_chunk_size_in_kbyte + v->total_dcc_active_dpp * v->meta_chunk_size) * 1024.0 / v->return_bw;
-+	if (v->pte_enable == dcn_bw_yes) {
-+		v->urgent_extra_latency = v->urgent_extra_latency + v->total_active_dpp * v->pte_chunk_size * 1024.0 / v->return_bw;
-+	}
-+	v->urgent_watermark = v->urgent_latency + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency;
-+	v->ptemeta_urgent_watermark = v->urgent_watermark + 2.0 * v->urgent_latency;
-+	/*nb p-state/dram clock change watermark*/
-+
-+	v->dram_clock_change_watermark = v->dram_clock_change_latency + v->urgent_watermark;
-+	v->total_active_writeback = 0.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->output[k] == dcn_bw_writeback) {
-+			v->total_active_writeback = v->total_active_writeback + 1.0;
-+		}
-+	}
-+	if (v->total_active_writeback <= 1.0) {
-+		v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency + v->write_back_latency;
-+	}
-+	else {
-+		v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency + v->write_back_latency + v->writeback_chunk_size * 1024.0 / 32.0 / v->socclk;
-+	}
-+	/*stutter efficiency*/
-+
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		v->lines_in_dety[k] = v->det_buffer_size_y[k] / v->byte_per_pixel_dety[k] / v->swath_width_y[k];
-+		v->lines_in_dety_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_dety[k], v->swath_height_y[k]);
-+		v->full_det_buffering_time_y[k] = v->lines_in_dety_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k];
-+		if (v->byte_per_pixel_detc[k] > 0.0) {
-+			v->lines_in_detc[k] = v->det_buffer_size_c[k] / v->byte_per_pixel_detc[k] / (v->swath_width_y[k] / 2.0);
-+			v->lines_in_detc_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_detc[k], v->swath_height_c[k]);
-+			v->full_det_buffering_time_c[k] = v->lines_in_detc_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0);
-+		}
-+		else {
-+			v->lines_in_detc[k] = 0.0;
-+			v->lines_in_detc_rounded_down_to_swath[k] = 0.0;
-+			v->full_det_buffering_time_c[k] = 999999.0;
-+		}
-+	}
-+	v->min_full_det_buffering_time = 999999.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->full_det_buffering_time_y[k] < v->min_full_det_buffering_time) {
-+			v->min_full_det_buffering_time = v->full_det_buffering_time_y[k];
-+			v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k] / v->pixel_clock[k];
-+		}
-+		if (v->full_det_buffering_time_c[k] < v->min_full_det_buffering_time) {
-+			v->min_full_det_buffering_time = v->full_det_buffering_time_c[k];
-+			v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k] / v->pixel_clock[k];
-+		}
-+	}
-+	v->average_read_bandwidth_gbyte_per_second = 0.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->dcc_enable[k] == dcn_bw_yes) {
-+			v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / v->dcc_rate[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] / v->dcc_rate[k] / 1000.0;
-+		}
-+		else {
-+			v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] / 1000.0;
-+		}
-+		if (v->dcc_enable[k] == dcn_bw_yes) {
-+			v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 / 256.0 + v->read_bandwidth_plane_chroma[k] / 1000.0 / 256.0;
-+		}
-+		if (v->pte_enable == dcn_bw_yes) {
-+			v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 / 512.0 + v->read_bandwidth_plane_chroma[k] / 1000.0 / 512.0;
-+		}
-+	}
-+	v->part_of_burst_that_fits_in_rob =dcn_bw_min2(v->min_full_det_buffering_time * v->total_data_read_bandwidth, v->rob_buffer_size_in_kbyte * 1024.0 * v->total_data_read_bandwidth / (v->average_read_bandwidth_gbyte_per_second * 1000.0));
-+	v->stutter_burst_time = v->part_of_burst_that_fits_in_rob * (v->average_read_bandwidth_gbyte_per_second * 1000.0) / v->total_data_read_bandwidth / v->return_bw + (v->min_full_det_buffering_time * v->total_data_read_bandwidth - v->part_of_burst_that_fits_in_rob) / (v->dcfclk * 64.0);
-+	if (v->total_active_writeback == 0.0) {
-+		v->stutter_efficiency_not_including_vblank = (1.0 - (v->sr_exit_time + v->stutter_burst_time) / v->min_full_det_buffering_time) * 100.0;
-+	}
-+	else {
-+		v->stutter_efficiency_not_including_vblank = 0.0;
-+	}
-+	v->smallest_vblank = 999999.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->synchronized_vblank == dcn_bw_yes || v->number_of_active_planes == 1) {
-+			v->v_blank_time = (v->vtotal[k] - v->vactive[k]) * v->htotal[k] / v->pixel_clock[k];
-+		}
-+		else {
-+			v->v_blank_time = 0.0;
-+		}
-+		v->smallest_vblank =dcn_bw_min2(v->smallest_vblank, v->v_blank_time);
-+	}
-+	v->stutter_efficiency = (v->stutter_efficiency_not_including_vblank / 100.0 * (v->frame_time_for_min_full_det_buffering_time - v->smallest_vblank) + v->smallest_vblank) / v->frame_time_for_min_full_det_buffering_time * 100.0;
-+	/*dcfclk deep sleep*/
-+
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->byte_per_pixel_detc[k] > 0.0) {
-+			v->dcfclk_deep_sleep_per_plane[k] =dcn_bw_max2(1.1 * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 32.0 / v->display_pipe_line_delivery_time_luma[k], 1.1 * v->swath_width_y[k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 32.0 / v->display_pipe_line_delivery_time_chroma[k]);
-+		}
-+		else {
-+			v->dcfclk_deep_sleep_per_plane[k] = 1.1 * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 64.0 / v->display_pipe_line_delivery_time_luma[k];
-+		}
-+		v->dcfclk_deep_sleep_per_plane[k] =dcn_bw_max2(v->dcfclk_deep_sleep_per_plane[k], v->pixel_clock[k] / 16.0);
-+	}
-+	v->dcf_clk_deep_sleep = 8.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		v->dcf_clk_deep_sleep =dcn_bw_max2(v->dcf_clk_deep_sleep, v->dcfclk_deep_sleep_per_plane[k]);
-+	}
-+	/*stutter watermark*/
-+
-+	v->stutter_exit_watermark = v->sr_exit_time + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency + 10.0 / v->dcf_clk_deep_sleep;
-+	v->stutter_enter_plus_exit_watermark = v->sr_enter_plus_exit_time + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency;
-+	/*urgent latency supported*/
-+
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		v->effective_det_plus_lb_lines_luma =dcn_bw_floor2(v->lines_in_dety[k] +dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixel_dety[k] * v->pscl_throughput[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_y[k]);
-+		v->urgent_latency_support_us_luma = v->effective_det_plus_lb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_det_plus_lb_lines_luma * v->swath_width_y[k] * v->byte_per_pixel_dety[k] / (v->return_bw / v->dpp_per_plane[k]);
-+		if (v->byte_per_pixel_detc[k] > 0.0) {
-+			v->effective_det_plus_lb_lines_chroma =dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixel_detc[k] * v->pscl_throughput_chroma[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_c[k]);
-+			v->urgent_latency_support_us_chroma = v->effective_det_plus_lb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_det_plus_lb_lines_chroma * (v->swath_width_y[k] / 2.0) * v->byte_per_pixel_detc[k] / (v->return_bw / v->dpp_per_plane[k]);
-+			v->urgent_latency_support_us[k] =dcn_bw_min2(v->urgent_latency_support_us_luma, v->urgent_latency_support_us_chroma);
-+		}
-+		else {
-+			v->urgent_latency_support_us[k] = v->urgent_latency_support_us_luma;
-+		}
-+	}
-+	v->min_urgent_latency_support_us = 999999.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		v->min_urgent_latency_support_us =dcn_bw_min2(v->min_urgent_latency_support_us, v->urgent_latency_support_us[k]);
-+	}
-+	/*non-urgent latency tolerance*/
-+
-+	v->non_urgent_latency_tolerance = v->min_urgent_latency_support_us - v->urgent_watermark;
-+	/*prefetch*/
-+
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
-+			if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+				v->block_height256_bytes_y = 1.0;
-+			}
-+			else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
-+				v->block_height256_bytes_y = 4.0;
-+			}
-+			else {
-+				v->block_height256_bytes_y = 8.0;
-+			}
-+			v->block_height256_bytes_c = 0.0;
-+		}
-+		else {
-+			if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+				v->block_height256_bytes_y = 1.0;
-+				v->block_height256_bytes_c = 1.0;
-+			}
-+			else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
-+				v->block_height256_bytes_y = 16.0;
-+				v->block_height256_bytes_c = 8.0;
-+			}
-+			else {
-+				v->block_height256_bytes_y = 8.0;
-+				v->block_height256_bytes_c = 8.0;
-+			}
-+		}
-+		if (v->dcc_enable[k] == dcn_bw_yes) {
-+			v->meta_request_width_y = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (8.0 * v->block_height256_bytes_y);
-+			v->meta_surf_width_y =dcn_bw_ceil2(v->swath_width_y[k] - 1.0, v->meta_request_width_y) + v->meta_request_width_y;
-+			v->meta_surf_height_y =dcn_bw_ceil2(v->viewport_height[k] - 1.0, 8.0 * v->block_height256_bytes_y) + 8.0 * v->block_height256_bytes_y;
-+			if (v->pte_enable == dcn_bw_yes) {
-+				v->meta_pte_bytes_frame_y = (dcn_bw_ceil2((v->meta_surf_width_y * v->meta_surf_height_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
-+			}
-+			else {
-+				v->meta_pte_bytes_frame_y = 0.0;
-+			}
-+			if (v->source_scan[k] == dcn_bw_hor) {
-+				v->meta_row_byte_y = v->meta_surf_width_y * 8.0 * v->block_height256_bytes_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0;
-+			}
-+			else {
-+				v->meta_row_byte_y = v->meta_surf_height_y * v->meta_request_width_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0;
-+			}
-+		}
-+		else {
-+			v->meta_pte_bytes_frame_y = 0.0;
-+			v->meta_row_byte_y = 0.0;
-+		}
-+		if (v->pte_enable == dcn_bw_yes) {
-+			if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+				v->macro_tile_size_byte_y = 256.0;
-+				v->macro_tile_height_y = 1.0;
-+			}
-+			else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
-+				v->macro_tile_size_byte_y = 4096.0;
-+				v->macro_tile_height_y = 4.0 * v->block_height256_bytes_y;
-+			}
-+			else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
-+				v->macro_tile_size_byte_y = 64.0 * 1024;
-+				v->macro_tile_height_y = 16.0 * v->block_height256_bytes_y;
-+			}
-+			else {
-+				v->macro_tile_size_byte_y = 256.0 * 1024;
-+				v->macro_tile_height_y = 32.0 * v->block_height256_bytes_y;
-+			}
-+			if (v->macro_tile_size_byte_y <= 65536.0) {
-+				v->pixel_pte_req_height_y = v->macro_tile_height_y;
-+			}
-+			else {
-+				v->pixel_pte_req_height_y = 16.0 * v->block_height256_bytes_y;
-+			}
-+			v->pixel_pte_req_width_y = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / v->pixel_pte_req_height_y * 8;
-+			if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+				v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_y / v->swath_width_y[k], 2.0), 1.0))) - 1.0) / v->pixel_pte_req_width_y, 1.0) + 1);
-+			}
-+			else if (v->source_scan[k] == dcn_bw_hor) {
-+				v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] - 1.0) / v->pixel_pte_req_width_y, 1.0) + 1);
-+			}
-+			else {
-+				v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] - 1.0) / v->pixel_pte_req_height_y, 1.0) + 1);
-+			}
-+		}
-+		else {
-+			v->pixel_pte_bytes_per_row_y = 0.0;
-+		}
-+		if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
-+			if (v->dcc_enable[k] == dcn_bw_yes) {
-+				v->meta_request_width_c = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (8.0 * v->block_height256_bytes_c);
-+				v->meta_surf_width_c =dcn_bw_ceil2(v->swath_width_y[k] / 2.0 - 1.0, v->meta_request_width_c) + v->meta_request_width_c;
-+				v->meta_surf_height_c =dcn_bw_ceil2(v->viewport_height[k] / 2.0 - 1.0, 8.0 * v->block_height256_bytes_c) + 8.0 * v->block_height256_bytes_c;
-+				if (v->pte_enable == dcn_bw_yes) {
-+					v->meta_pte_bytes_frame_c = (dcn_bw_ceil2((v->meta_surf_width_c * v->meta_surf_height_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
-+				}
-+				else {
-+					v->meta_pte_bytes_frame_c = 0.0;
-+				}
-+				if (v->source_scan[k] == dcn_bw_hor) {
-+					v->meta_row_byte_c = v->meta_surf_width_c * 8.0 * v->block_height256_bytes_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0;
-+				}
-+				else {
-+					v->meta_row_byte_c = v->meta_surf_height_c * v->meta_request_width_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0;
-+				}
-+			}
-+			else {
-+				v->meta_pte_bytes_frame_c = 0.0;
-+				v->meta_row_byte_c = 0.0;
-+			}
-+			if (v->pte_enable == dcn_bw_yes) {
-+				if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+					v->macro_tile_size_bytes_c = 256.0;
-+					v->macro_tile_height_c = 1.0;
-+				}
-+				else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
-+					v->macro_tile_size_bytes_c = 4096.0;
-+					v->macro_tile_height_c = 4.0 * v->block_height256_bytes_c;
-+				}
-+				else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
-+					v->macro_tile_size_bytes_c = 64.0 * 1024;
-+					v->macro_tile_height_c = 16.0 * v->block_height256_bytes_c;
-+				}
-+				else {
-+					v->macro_tile_size_bytes_c = 256.0 * 1024;
-+					v->macro_tile_height_c = 32.0 * v->block_height256_bytes_c;
-+				}
-+				if (v->macro_tile_size_bytes_c <= 65536.0) {
-+					v->pixel_pte_req_height_c = v->macro_tile_height_c;
-+				}
-+				else {
-+					v->pixel_pte_req_height_c = 16.0 * v->block_height256_bytes_c;
-+				}
-+				v->pixel_pte_req_width_c = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / v->pixel_pte_req_height_c * 8;
-+				if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
-+					v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0 * dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_c / (v->swath_width_y[k] / 2.0), 2.0), 1.0))) - 1.0) / v->pixel_pte_req_width_c, 1.0) + 1);
-+				}
-+				else if (v->source_scan[k] == dcn_bw_hor) {
-+					v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0 - 1.0) / v->pixel_pte_req_width_c, 1.0) + 1);
-+				}
-+				else {
-+					v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] / 2.0 - 1.0) / v->pixel_pte_req_height_c, 1.0) + 1);
-+				}
-+			}
-+			else {
-+				v->pixel_pte_bytes_per_row_c = 0.0;
-+			}
-+		}
-+		else {
-+			v->pixel_pte_bytes_per_row_c = 0.0;
-+			v->meta_pte_bytes_frame_c = 0.0;
-+			v->meta_row_byte_c = 0.0;
-+		}
-+		v->pixel_pte_bytes_per_row[k] = v->pixel_pte_bytes_per_row_y + v->pixel_pte_bytes_per_row_c;
-+		v->meta_pte_bytes_frame[k] = v->meta_pte_bytes_frame_y + v->meta_pte_bytes_frame_c;
-+		v->meta_row_byte[k] = v->meta_row_byte_y + v->meta_row_byte_c;
-+		v->v_init_pre_fill_y[k] =dcn_bw_floor2((v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0, 1.0);
-+		v->max_num_swath_y[k] =dcn_bw_ceil2((v->v_init_pre_fill_y[k] - 1.0) / v->swath_height_y[k], 1.0) + 1;
-+		if (v->v_init_pre_fill_y[k] > 1.0) {
-+			v->max_partial_swath_y =dcn_bw_mod((v->v_init_pre_fill_y[k] - 2.0), v->swath_height_y[k]);
-+		}
-+		else {
-+			v->max_partial_swath_y =dcn_bw_mod((v->v_init_pre_fill_y[k] + v->swath_height_y[k] - 2.0), v->swath_height_y[k]);
-+		}
-+		v->max_partial_swath_y =dcn_bw_max2(1.0, v->max_partial_swath_y);
-+		v->prefetch_source_lines_y[k] = v->max_num_swath_y[k] * v->swath_height_y[k] + v->max_partial_swath_y;
-+		if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
-+			v->v_init_pre_fill_c[k] =dcn_bw_floor2((v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0, 1.0);
-+			v->max_num_swath_c[k] =dcn_bw_ceil2((v->v_init_pre_fill_c[k] - 1.0) / v->swath_height_c[k], 1.0) + 1;
-+			if (v->v_init_pre_fill_c[k] > 1.0) {
-+				v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] - 2.0), v->swath_height_c[k]);
-+			}
-+			else {
-+				v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] + v->swath_height_c[k] - 2.0), v->swath_height_c[k]);
-+			}
-+			v->max_partial_swath_c =dcn_bw_max2(1.0, v->max_partial_swath_c);
-+		}
-+		else {
-+			v->max_num_swath_c[k] = 0.0;
-+			v->max_partial_swath_c = 0.0;
-+		}
-+		v->prefetch_source_lines_c[k] = v->max_num_swath_c[k] * v->swath_height_c[k] + v->max_partial_swath_c;
-+	}
-+	v->t_calc = 24.0 / v->dcf_clk_deep_sleep;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes) {
-+			v->max_vstartup_lines[k] = v->vtotal[k] - v->vactive[k] - 1.0;
-+		}
-+		else {
-+			v->max_vstartup_lines[k] = v->v_sync_plus_back_porch[k] - 1.0;
-+		}
-+	}
-+	v->next_prefetch_mode = 0.0;
-+	do {
-+		v->v_startup_lines = 13.0;
-+		do {
-+			v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw = dcn_bw_yes;
-+			v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 = dcn_bw_no;
-+			v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 = dcn_bw_no;
-+			v->v_ratio_prefetch_more_than4 = dcn_bw_no;
-+			v->destination_line_times_for_prefetch_less_than2 = dcn_bw_no;
-+			v->prefetch_mode = v->next_prefetch_mode;
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk;
-+				if (v->dpp_per_plane[k] > 1.0) {
-+					v->dstx_after_scaler = v->dstx_after_scaler + v->scaler_rec_out_width[k] / 2.0;
-+				}
-+				if (v->output_format[k] == dcn_bw_420) {
-+					v->dsty_after_scaler = 1.0;
-+				}
-+				else {
-+					v->dsty_after_scaler = 0.0;
-+				}
-+				v->v_update_offset_pix =dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
-+				v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispclk);
-+				v->v_update_width_pix = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_delay_time) * v->pixel_clock[k];
-+				v->v_ready_offset_pix =dcn_bw_max2(150.0 / v->dppclk, v->total_repeater_delay_time + 20.0 / v->dcf_clk_deep_sleep + 10.0 / v->dppclk) * v->pixel_clock[k];
-+				v->t_setup = (v->v_update_offset_pix + v->v_update_width_pix + v->v_ready_offset_pix) / v->pixel_clock[k];
-+				v->v_startup[k] =dcn_bw_min2(v->v_startup_lines, v->max_vstartup_lines[k]);
-+				if (v->prefetch_mode == 0.0) {
-+					v->t_wait =dcn_bw_max3(v->dram_clock_change_latency + v->urgent_latency, v->sr_enter_plus_exit_time, v->urgent_latency);
-+				}
-+				else if (v->prefetch_mode == 1.0) {
-+					v->t_wait =dcn_bw_max2(v->sr_enter_plus_exit_time, v->urgent_latency);
-+				}
-+				else {
-+					v->t_wait = v->urgent_latency;
-+				}
-+				v->destination_lines_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->v_startup[k] - v->t_wait / (v->htotal[k] / v->pixel_clock[k]) - (v->t_calc + v->t_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dsty_after_scaler + v->dstx_after_scaler / v->htotal[k]) + 0.125), 1.0) / 4;
-+				if (v->destination_lines_for_prefetch[k] > 0.0) {
-+					v->prefetch_bandwidth[k] = (v->meta_pte_bytes_frame[k] + 2.0 * v->meta_row_byte[k] + 2.0 * v->pixel_pte_bytes_per_row[k] + v->prefetch_source_lines_y[k] * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) + v->prefetch_source_lines_c[k] * v->swath_width_y[k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)) / (v->destination_lines_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]);
-+				}
-+				else {
-+					v->prefetch_bandwidth[k] = 999999.0;
-+				}
-+			}
-+			v->bandwidth_available_for_immediate_flip = v->return_bw;
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				v->bandwidth_available_for_immediate_flip = v->bandwidth_available_for_immediate_flip -dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->prefetch_bandwidth[k]);
-+			}
-+			v->tot_immediate_flip_bytes = 0.0;
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
-+					v->tot_immediate_flip_bytes = v->tot_immediate_flip_bytes + v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k];
-+				}
-+			}
-+			v->max_rd_bandwidth = 0.0;
-+			for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+				if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
-+					if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
-+						v->time_for_fetching_meta_pte =dcn_bw_max5(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->meta_pte_bytes_frame[k] * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
-+					}
-+					else {
-+						v->time_for_fetching_meta_pte =dcn_bw_max3(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
-+					}
-+				}
-+				else {
-+					v->time_for_fetching_meta_pte = v->htotal[k] / v->pixel_clock[k] / 4.0;
-+				}
-+				v->destination_lines_to_request_vm_inv_blank[k] =dcn_bw_floor2(4.0 * (v->time_for_fetching_meta_pte / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
-+				if ((v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes)) {
-+					if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
-+						v->time_for_fetching_row_in_vblank =dcn_bw_max5((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, 2.0 * v->urgent_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte);
-+					}
-+					else {
-+						v->time_for_fetching_row_in_vblank =dcn_bw_max3((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte);
-+					}
-+				}
-+				else {
-+					v->time_for_fetching_row_in_vblank =dcn_bw_max2(v->urgent_extra_latency - v->time_for_fetching_meta_pte, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte);
-+				}
-+				v->destination_lines_to_request_row_in_vblank[k] =dcn_bw_floor2(4.0 * (v->time_for_fetching_row_in_vblank / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
-+				v->lines_to_request_prefetch_pixel_data = v->destination_lines_for_prefetch[k] - v->destination_lines_to_request_vm_inv_blank[k] - v->destination_lines_to_request_row_in_vblank[k];
-+				if (v->lines_to_request_prefetch_pixel_data > 0.0) {
-+					v->v_ratio_prefetch_y[k] = v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data;
-+					if ((v->swath_height_y[k] > 4.0)) {
-+						if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_y[k] - 3.0) / 2.0) {
-+							v->v_ratio_prefetch_y[k] =dcn_bw_max2(v->v_ratio_prefetch_y[k], v->max_num_swath_y[k] * v->swath_height_y[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_y[k] - 3.0) / 2.0));
-+						}
-+						else {
-+							v->v_ratio_prefetch_y[k] = 999999.0;
-+						}
-+					}
-+				}
-+				else {
-+					v->v_ratio_prefetch_y[k] = 999999.0;
-+				}
-+				v->v_ratio_prefetch_y[k] =dcn_bw_max2(v->v_ratio_prefetch_y[k], 1.0);
-+				if (v->lines_to_request_prefetch_pixel_data > 0.0) {
-+					v->v_ratio_prefetch_c[k] = v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data;
-+					if ((v->swath_height_c[k] > 4.0)) {
-+						if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_c[k] - 3.0) / 2.0) {
-+							v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], v->max_num_swath_c[k] * v->swath_height_c[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_c[k] - 3.0) / 2.0));
-+						}
-+						else {
-+							v->v_ratio_prefetch_c[k] = 999999.0;
-+						}
-+					}
-+				}
-+				else {
-+					v->v_ratio_prefetch_c[k] = 999999.0;
-+				}
-+				v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], 1.0);
-+				if (v->lines_to_request_prefetch_pixel_data > 0.0) {
-+					v->required_prefetch_pix_data_bw = v->dpp_per_plane[k] * (v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) + v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 2.0) * v->swath_width_y[k] / (v->htotal[k] / v->pixel_clock[k]);
-+				}
-+				else {
-+					v->required_prefetch_pix_data_bw = 999999.0;
-+				}
-+				v->max_rd_bandwidth = v->max_rd_bandwidth +dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->required_prefetch_pix_data_bw);
-+				if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
-+					v->max_rd_bandwidth = v->max_rd_bandwidth +dcn_bw_max2(v->meta_pte_bytes_frame[k] / (v->destination_lines_to_request_vm_inv_blank[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / (v->destination_lines_to_request_row_in_vblank[k] * v->htotal[k] / v->pixel_clock[k]));
-+				}
-+				if (v->v_ratio_prefetch_y[k] > 4.0 || v->v_ratio_prefetch_c[k] > 4.0) {
-+					v->v_ratio_prefetch_more_than4 = dcn_bw_yes;
-+				}
-+				if (v->destination_lines_for_prefetch[k] < 2.0) {
-+					v->destination_line_times_for_prefetch_less_than2 = dcn_bw_yes;
-+				}
-+				if (v->max_vstartup_lines[k] > v->v_startup_lines) {
-+					if (v->required_prefetch_pix_data_bw > (v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k])) {
-+						v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw = dcn_bw_no;
-+					}
-+					if (v->v_ratio_prefetch_y[k] > 4.0 || v->v_ratio_prefetch_c[k] > 4.0) {
-+						v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 = dcn_bw_yes;
-+					}
-+					if (v->destination_lines_for_prefetch[k] < 2.0) {
-+						v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 = dcn_bw_yes;
-+					}
-+				}
-+			}
-+			if (v->max_rd_bandwidth <= v->return_bw && v->v_ratio_prefetch_more_than4 == dcn_bw_no && v->destination_line_times_for_prefetch_less_than2 == dcn_bw_no) {
-+				v->prefetch_mode_supported = dcn_bw_yes;
-+			}
-+			else {
-+				v->prefetch_mode_supported = dcn_bw_no;
-+			}
-+			v->v_startup_lines = v->v_startup_lines + 1.0;
-+		} while (!(v->prefetch_mode_supported == dcn_bw_yes || (v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw == dcn_bw_yes && v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 == dcn_bw_no && v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 == dcn_bw_no)));
-+		v->next_prefetch_mode = v->next_prefetch_mode + 1.0;
-+	} while (!(v->prefetch_mode_supported == dcn_bw_yes || v->prefetch_mode == 2.0));
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->v_ratio_prefetch_y[k] <= 1.0) {
-+			v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
-+		}
-+		else {
-+			v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk;
-+		}
-+		if (v->byte_per_pixel_detc[k] == 0.0) {
-+			v->display_pipe_line_delivery_time_chroma_prefetch[k] = 0.0;
-+		}
-+		else {
-+			if (v->v_ratio_prefetch_c[k] <= 1.0) {
-+				v->display_pipe_line_delivery_time_chroma_prefetch[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
-+			}
-+			else {
-+				v->display_pipe_line_delivery_time_chroma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk;
-+			}
-+		}
-+	}
-+	/*min ttuv_blank*/
-+
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->prefetch_mode == 0.0) {
-+			v->allow_dram_clock_change_during_vblank[k] = dcn_bw_yes;
-+			v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes;
-+			v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max3(v->dram_clock_change_watermark, v->stutter_enter_plus_exit_watermark, v->urgent_watermark);
-+		}
-+		else if (v->prefetch_mode == 1.0) {
-+			v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no;
-+			v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes;
-+			v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max2(v->stutter_enter_plus_exit_watermark, v->urgent_watermark);
-+		}
-+		else {
-+			v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no;
-+			v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_no;
-+			v->min_ttuv_blank[k] = v->t_calc + v->urgent_watermark;
-+		}
-+	}
-+	/*nb p-state/dram clock change support*/
-+
-+	v->active_dp_ps = 0.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		v->active_dp_ps = v->active_dp_ps + v->dpp_per_plane[k];
-+	}
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		v->lb_latency_hiding_source_lines_y =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0);
-+		v->lb_latency_hiding_source_lines_c =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0)), 1.0)) - (v->vta_pschroma[k] - 1.0);
-+		v->effective_lb_latency_hiding_y = v->lb_latency_hiding_source_lines_y / v->v_ratio[k] * (v->htotal[k] / v->pixel_clock[k]);
-+		v->effective_lb_latency_hiding_c = v->lb_latency_hiding_source_lines_c / (v->v_ratio[k] / 2.0) * (v->htotal[k] / v->pixel_clock[k]);
-+		if (v->swath_width_y[k] > 2.0 * v->dpp_output_buffer_pixels) {
-+			v->dpp_output_buffer_lines_y = v->dpp_output_buffer_pixels / v->swath_width_y[k];
-+		}
-+		else if (v->swath_width_y[k] > v->dpp_output_buffer_pixels) {
-+			v->dpp_output_buffer_lines_y = 0.5;
-+		}
-+		else {
-+			v->dpp_output_buffer_lines_y = 1.0;
-+		}
-+		if (v->swath_width_y[k] / 2.0 > 2.0 * v->dpp_output_buffer_pixels) {
-+			v->dpp_output_buffer_lines_c = v->dpp_output_buffer_pixels / (v->swath_width_y[k] / 2.0);
-+		}
-+		else if (v->swath_width_y[k] / 2.0 > v->dpp_output_buffer_pixels) {
-+			v->dpp_output_buffer_lines_c = 0.5;
-+		}
-+		else {
-+			v->dpp_output_buffer_lines_c = 1.0;
-+		}
-+		v->dppopp_buffering_y = (v->htotal[k] / v->pixel_clock[k]) * (v->dpp_output_buffer_lines_y + v->opp_output_buffer_lines);
-+		v->max_det_buffering_time_y = v->full_det_buffering_time_y[k] + (v->lines_in_dety[k] - v->lines_in_dety_rounded_down_to_swath[k]) / v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]);
-+		v->active_dram_clock_change_latency_margin_y = v->dppopp_buffering_y + v->effective_lb_latency_hiding_y + v->max_det_buffering_time_y - v->dram_clock_change_watermark;
-+		if (v->active_dp_ps > 1.0) {
-+			v->active_dram_clock_change_latency_margin_y = v->active_dram_clock_change_latency_margin_y - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]);
-+		}
-+		if (v->byte_per_pixel_detc[k] > 0.0) {
-+			v->dppopp_buffering_c = (v->htotal[k] / v->pixel_clock[k]) * (v->dpp_output_buffer_lines_c + v->opp_output_buffer_lines);
-+			v->max_det_buffering_time_c = v->full_det_buffering_time_c[k] + (v->lines_in_detc[k] - v->lines_in_detc_rounded_down_to_swath[k]) / v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]);
-+			v->active_dram_clock_change_latency_margin_c = v->dppopp_buffering_c + v->effective_lb_latency_hiding_c + v->max_det_buffering_time_c - v->dram_clock_change_watermark;
-+			if (v->active_dp_ps > 1.0) {
-+				v->active_dram_clock_change_latency_margin_c = v->active_dram_clock_change_latency_margin_c - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]);
-+			}
-+			v->active_dram_clock_change_latency_margin[k] =dcn_bw_min2(v->active_dram_clock_change_latency_margin_y, v->active_dram_clock_change_latency_margin_c);
-+		}
-+		else {
-+			v->active_dram_clock_change_latency_margin[k] = v->active_dram_clock_change_latency_margin_y;
-+		}
-+		if (v->output_format[k] == dcn_bw_444) {
-+			v->writeback_dram_clock_change_latency_margin = (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0) - v->writeback_dram_clock_change_watermark;
-+		}
-+		else {
-+			v->writeback_dram_clock_change_latency_margin =dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k])) - v->writeback_dram_clock_change_watermark;
-+		}
-+		if (v->output[k] == dcn_bw_writeback) {
-+			v->active_dram_clock_change_latency_margin[k] =dcn_bw_min2(v->active_dram_clock_change_latency_margin[k], v->writeback_dram_clock_change_latency_margin);
-+		}
-+	}
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->allow_dram_clock_change_during_vblank[k] == dcn_bw_yes) {
-+			v->v_blank_dram_clock_change_latency_margin[k] = (v->vtotal[k] - v->scaler_recout_height[k]) * (v->htotal[k] / v->pixel_clock[k]) -dcn_bw_max2(v->dram_clock_change_watermark, v->writeback_dram_clock_change_watermark);
-+		}
-+		else {
-+			v->v_blank_dram_clock_change_latency_margin[k] = 0.0;
-+		}
-+	}
-+	v->min_active_dram_clock_change_margin = 999999.0;
-+	v->v_blank_of_min_active_dram_clock_change_margin = 999999.0;
-+	v->second_min_active_dram_clock_change_margin = 999999.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->active_dram_clock_change_latency_margin[k] < v->min_active_dram_clock_change_margin) {
-+			v->second_min_active_dram_clock_change_margin = v->min_active_dram_clock_change_margin;
-+			v->min_active_dram_clock_change_margin = v->active_dram_clock_change_latency_margin[k];
-+			v->v_blank_of_min_active_dram_clock_change_margin = v->v_blank_dram_clock_change_latency_margin[k];
-+		}
-+		else if (v->active_dram_clock_change_latency_margin[k] < v->second_min_active_dram_clock_change_margin) {
-+			v->second_min_active_dram_clock_change_margin = v->active_dram_clock_change_latency_margin[k];
-+		}
-+	}
-+	v->min_vblank_dram_clock_change_margin = 999999.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->min_vblank_dram_clock_change_margin > v->v_blank_dram_clock_change_latency_margin[k]) {
-+			v->min_vblank_dram_clock_change_margin = v->v_blank_dram_clock_change_latency_margin[k];
-+		}
-+	}
-+	if (v->synchronized_vblank == dcn_bw_yes || v->number_of_active_planes == 1) {
-+		v->dram_clock_change_margin =dcn_bw_max2(v->min_active_dram_clock_change_margin, v->min_vblank_dram_clock_change_margin);
-+	}
-+	else if (v->v_blank_of_min_active_dram_clock_change_margin > v->min_active_dram_clock_change_margin) {
-+		v->dram_clock_change_margin =dcn_bw_min2(v->second_min_active_dram_clock_change_margin, v->v_blank_of_min_active_dram_clock_change_margin);
-+	}
-+	else {
-+		v->dram_clock_change_margin = v->min_active_dram_clock_change_margin;
-+	}
-+	if (v->min_active_dram_clock_change_margin > 0.0) {
-+		v->dram_clock_change_support = dcn_bw_supported_in_v_active;
-+	}
-+	else if (v->dram_clock_change_margin > 0.0) {
-+		v->dram_clock_change_support = dcn_bw_supported_in_v_blank;
-+	}
-+	else {
-+		v->dram_clock_change_support = dcn_bw_not_supported;
-+	}
-+	/*maximum bandwidth used*/
-+
-+	v->wr_bandwidth = 0.0;
-+	for (k = 0; k <= v->number_of_active_planes - 1; k++) {
-+		if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) {
-+			v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0;
-+		}
-+		else if (v->output[k] == dcn_bw_writeback) {
-+			v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5;
-+		}
-+	}
-+	v->max_used_bw = v->max_rd_bandwidth + v->wr_bandwidth;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h.0130~	2017-12-14 06:39:58.404903560 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h	2017-12-14 06:39:58.404903560 +0100
-@@ -0,0 +1,37 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef _DCN_CALC_AUTO_H_
-+#define _DCN_CALC_AUTO_H_
-+
-+#include "dcn_calcs.h"
-+
-+void scaler_settings_calculation(struct dcn_bw_internal_vars *v);
-+void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v);
-+void display_pipe_configuration(struct dcn_bw_internal_vars *v);
-+void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(
-+		struct dcn_bw_internal_vars *v);
-+
-+#endif /* _DCN_CALC_AUTO_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c.0130~	2017-12-14 06:39:58.404903560 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c	2017-12-14 06:39:58.404903560 +0100
-@@ -0,0 +1,120 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dcn_calc_math.h"
-+
-+float dcn_bw_mod(const float arg1, const float arg2)
-+{
-+	if (arg1 != arg1)
-+		return arg2;
-+	if (arg2 != arg2)
-+		return arg1;
-+	return arg1 - arg1 * ((int) (arg1 / arg2));
-+}
-+
-+float dcn_bw_min2(const float arg1, const float arg2)
-+{
-+	if (arg1 != arg1)
-+		return arg2;
-+	if (arg2 != arg2)
-+		return arg1;
-+	return arg1 < arg2 ? arg1 : arg2;
-+}
-+
-+unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2)
-+{
-+	if (arg1 != arg1)
-+		return arg2;
-+	if (arg2 != arg2)
-+		return arg1;
-+	return arg1 > arg2 ? arg1 : arg2;
-+}
-+float dcn_bw_max2(const float arg1, const float arg2)
-+{
-+	if (arg1 != arg1)
-+		return arg2;
-+	if (arg2 != arg2)
-+		return arg1;
-+	return arg1 > arg2 ? arg1 : arg2;
-+}
-+
-+float dcn_bw_floor2(const float arg, const float significance)
-+{
-+	if (significance == 0)
-+		return 0;
-+	return ((int) (arg / significance)) * significance;
-+}
-+
-+float dcn_bw_ceil2(const float arg, const float significance)
-+{
-+	float flr = dcn_bw_floor2(arg, significance);
-+	if (significance == 0)
-+		return 0;
-+	return flr + 0.00001 >= arg ? arg : flr + significance;
-+}
-+
-+float dcn_bw_max3(float v1, float v2, float v3)
-+{
-+	return v3 > dcn_bw_max2(v1, v2) ? v3 : dcn_bw_max2(v1, v2);
-+}
-+
-+float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5)
-+{
-+	return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, v2, v3) : dcn_bw_max2(v4, v5);
-+}
-+
-+float dcn_bw_pow(float a, float exp)
-+{
-+	float temp;
-+	/*ASSERT(exp == (int)exp);*/
-+	if ((int)exp == 0)
-+		return 1;
-+	temp = dcn_bw_pow(a, (int)(exp / 2));
-+	if (((int)exp % 2) == 0) {
-+		return temp * temp;
-+	} else {
-+		if ((int)exp > 0)
-+			return a * temp * temp;
-+		else
-+			return (temp * temp) / a;
-+	}
-+}
-+
-+float dcn_bw_log(float a, float b)
-+{
-+	int * const exp_ptr = (int *)(&a);
-+	int x = *exp_ptr;
-+	const int log_2 = ((x >> 23) & 255) - 128;
-+	x &= ~(255 << 23);
-+	x += 127 << 23;
-+	*exp_ptr = x;
-+
-+	a = ((-1.0f / 3) * a + 2) * a - 2.0f / 3;
-+
-+	if (b > 2.00001 || b < 1.99999)
-+		return (a + log_2) / dcn_bw_log(b, 2);
-+	else
-+		return (a + log_2);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h.0130~	2017-12-14 06:39:58.404903560 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h	2017-12-14 06:39:58.404903560 +0100
-@@ -0,0 +1,40 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef _DCN_CALC_MATH_H_
-+#define _DCN_CALC_MATH_H_
-+
-+float dcn_bw_mod(const float arg1, const float arg2);
-+float dcn_bw_min2(const float arg1, const float arg2);
-+unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2);
-+float dcn_bw_max2(const float arg1, const float arg2);
-+float dcn_bw_floor2(const float arg, const float significance);
-+float dcn_bw_ceil2(const float arg, const float significance);
-+float dcn_bw_max3(float v1, float v2, float v3);
-+float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5);
-+float dcn_bw_pow(float a, float exp);
-+float dcn_bw_log(float a, float b);
-+
-+#endif /* _DCN_CALC_MATH_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c.0130~	2017-12-14 06:39:58.405903560 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c	2017-12-14 06:39:58.405903560 +0100
-@@ -0,0 +1,1651 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dcn_calcs.h"
-+#include "dcn_calc_auto.h"
-+#include "dc.h"
-+#include "dal_asic_id.h"
-+
-+#include "resource.h"
-+#include "dcn10/dcn10_resource.h"
-+#include "dcn_calc_math.h"
-+
-+/* Defaults from spreadsheet rev#247 */
-+const struct dcn_soc_bounding_box dcn10_soc_defaults = {
-+		/* latencies */
-+		.sr_exit_time = 17, /*us*/
-+		.sr_enter_plus_exit_time = 19, /*us*/
-+		.urgent_latency = 4, /*us*/
-+		.dram_clock_change_latency = 17, /*us*/
-+		.write_back_latency = 12, /*us*/
-+		.percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/
-+
-+		/* below default clocks derived from STA target base on
-+		 * slow-slow corner + 10% margin with voltages aligned to FCLK.
-+		 *
-+		 * Use these value if fused value doesn't make sense as earlier
-+		 * part don't have correct value fused */
-+		/* default DCF CLK DPM on RV*/
-+		.dcfclkv_max0p9 = 655,	/* MHz, = 3600/5.5 */
-+		.dcfclkv_nom0p8 = 626,	/* MHz, = 3600/5.75 */
-+		.dcfclkv_mid0p72 = 600,	/* MHz, = 3600/6, bypass */
-+		.dcfclkv_min0p65 = 300,	/* MHz, = 3600/12, bypass */
-+
-+		/* default DISP CLK voltage state on RV */
-+		.max_dispclk_vmax0p9 = 1108,	/* MHz, = 3600/3.25 */
-+		.max_dispclk_vnom0p8 = 1029,	/* MHz, = 3600/3.5 */
-+		.max_dispclk_vmid0p72 = 960,	/* MHz, = 3600/3.75 */
-+		.max_dispclk_vmin0p65 = 626,	/* MHz, = 3600/5.75 */
-+
-+		/* default DPP CLK voltage state on RV */
-+		.max_dppclk_vmax0p9 = 720,	/* MHz, = 3600/5 */
-+		.max_dppclk_vnom0p8 = 686,	/* MHz, = 3600/5.25 */
-+		.max_dppclk_vmid0p72 = 626,	/* MHz, = 3600/5.75 */
-+		.max_dppclk_vmin0p65 = 400,	/* MHz, = 3600/9 */
-+
-+		/* default PHY CLK voltage state on RV */
-+		.phyclkv_max0p9 = 900, /*MHz*/
-+		.phyclkv_nom0p8 = 847, /*MHz*/
-+		.phyclkv_mid0p72 = 800, /*MHz*/
-+		.phyclkv_min0p65 = 600, /*MHz*/
-+
-+		/* BW depend on FCLK, MCLK, # of channels */
-+		/* dual channel BW */
-+		.fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/
-+		.fabric_and_dram_bandwidth_vnom0p8 = 34.133f, /*GB/s*/
-+		.fabric_and_dram_bandwidth_vmid0p72 = 29.866f, /*GB/s*/
-+		.fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/
-+		/* single channel BW
-+		.fabric_and_dram_bandwidth_vmax0p9 = 19.2f,
-+		.fabric_and_dram_bandwidth_vnom0p8 = 17.066f,
-+		.fabric_and_dram_bandwidth_vmid0p72 = 14.933f,
-+		.fabric_and_dram_bandwidth_vmin0p65 = 12.8f,
-+		*/
-+
-+		.number_of_channels = 2,
-+
-+		.socclk = 208, /*MHz*/
-+		.downspreading = 0.5f, /*%*/
-+		.round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
-+		.urgent_out_of_order_return_per_channel = 256, /*bytes*/
-+		.vmm_page_size = 4096, /*bytes*/
-+		.return_bus_width = 64, /*bytes*/
-+		.max_request_size = 256, /*bytes*/
-+
-+		/* Depends on user class (client vs embedded, workstation, etc) */
-+		.percent_disp_bw_limit = 0.3f /*%*/
-+};
-+
-+const struct dcn_ip_params dcn10_ip_defaults = {
-+		.rob_buffer_size_in_kbyte = 64,
-+		.det_buffer_size_in_kbyte = 164,
-+		.dpp_output_buffer_pixels = 2560,
-+		.opp_output_buffer_lines = 1,
-+		.pixel_chunk_size_in_kbyte = 8,
-+		.pte_enable = dcn_bw_yes,
-+		.pte_chunk_size = 2, /*kbytes*/
-+		.meta_chunk_size = 2, /*kbytes*/
-+		.writeback_chunk_size = 2, /*kbytes*/
-+		.odm_capability = dcn_bw_no,
-+		.dsc_capability = dcn_bw_no,
-+		.line_buffer_size = 589824, /*bit*/
-+		.max_line_buffer_lines = 12,
-+		.is_line_buffer_bpp_fixed = dcn_bw_no,
-+		.line_buffer_fixed_bpp = dcn_bw_na,
-+		.writeback_luma_buffer_size = 12, /*kbytes*/
-+		.writeback_chroma_buffer_size = 8, /*kbytes*/
-+		.max_num_dpp = 4,
-+		.max_num_writeback = 2,
-+		.max_dchub_topscl_throughput = 4, /*pixels/dppclk*/
-+		.max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
-+		.max_lb_tovscl_throughput = 4, /*pixels/dppclk*/
-+		.max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/
-+		.max_hscl_ratio = 4,
-+		.max_vscl_ratio = 4,
-+		.max_hscl_taps = 8,
-+		.max_vscl_taps = 8,
-+		.pte_buffer_size_in_requests = 42,
-+		.dispclk_ramping_margin = 1, /*%*/
-+		.under_scan_factor = 1.11f,
-+		.max_inter_dcn_tile_repeaters = 8,
-+		.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dcn_bw_no,
-+		.bug_forcing_luma_and_chroma_request_to_same_size_fixed = dcn_bw_no,
-+		.dcfclk_cstate_latency = 10 /*TODO clone of something else? sr_enter_plus_exit_time?*/
-+};
-+
-+static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode)
-+{
-+	switch (sw_mode) {
-+	case DC_SW_LINEAR:
-+		return dcn_bw_sw_linear;
-+	case DC_SW_4KB_S:
-+		return dcn_bw_sw_4_kb_s;
-+	case DC_SW_4KB_D:
-+		return dcn_bw_sw_4_kb_d;
-+	case DC_SW_64KB_S:
-+		return dcn_bw_sw_64_kb_s;
-+	case DC_SW_64KB_D:
-+		return dcn_bw_sw_64_kb_d;
-+	case DC_SW_VAR_S:
-+		return dcn_bw_sw_var_s;
-+	case DC_SW_VAR_D:
-+		return dcn_bw_sw_var_d;
-+	case DC_SW_64KB_S_T:
-+		return dcn_bw_sw_64_kb_s_t;
-+	case DC_SW_64KB_D_T:
-+		return dcn_bw_sw_64_kb_d_t;
-+	case DC_SW_4KB_S_X:
-+		return dcn_bw_sw_4_kb_s_x;
-+	case DC_SW_4KB_D_X:
-+		return dcn_bw_sw_4_kb_d_x;
-+	case DC_SW_64KB_S_X:
-+		return dcn_bw_sw_64_kb_s_x;
-+	case DC_SW_64KB_D_X:
-+		return dcn_bw_sw_64_kb_d_x;
-+	case DC_SW_VAR_S_X:
-+		return dcn_bw_sw_var_s_x;
-+	case DC_SW_VAR_D_X:
-+		return dcn_bw_sw_var_d_x;
-+	case DC_SW_256B_S:
-+	case DC_SW_256_D:
-+	case DC_SW_256_R:
-+	case DC_SW_4KB_R:
-+	case DC_SW_64KB_R:
-+	case DC_SW_VAR_R:
-+	case DC_SW_4KB_R_X:
-+	case DC_SW_64KB_R_X:
-+	case DC_SW_VAR_R_X:
-+	default:
-+		BREAK_TO_DEBUGGER(); /*not in formula*/
-+		return dcn_bw_sw_4_kb_s;
-+	}
-+}
-+
-+static int tl_lb_bpp_to_int(enum lb_pixel_depth depth)
-+{
-+	switch (depth) {
-+	case LB_PIXEL_DEPTH_18BPP:
-+		return 18;
-+	case LB_PIXEL_DEPTH_24BPP:
-+		return 24;
-+	case LB_PIXEL_DEPTH_30BPP:
-+		return 30;
-+	case LB_PIXEL_DEPTH_36BPP:
-+		return 36;
-+	default:
-+		return 30;
-+	}
-+}
-+
-+static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format format)
-+{
-+	switch (format) {
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
-+	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
-+		return dcn_bw_rgb_sub_16;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
-+		return dcn_bw_rgb_sub_32;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+		return dcn_bw_rgb_sub_64;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
-+		return dcn_bw_yuv420_sub_8;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
-+		return dcn_bw_yuv420_sub_10;
-+	default:
-+		return dcn_bw_rgb_sub_32;
-+	}
-+}
-+
-+static void pipe_ctx_to_e2e_pipe_params (
-+		const struct pipe_ctx *pipe,
-+		struct _vcs_dpi_display_pipe_params_st *input)
-+{
-+	input->src.is_hsplit = false;
-+	if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state)
-+		input->src.is_hsplit = true;
-+	else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state)
-+		input->src.is_hsplit = true;
-+
-+	input->src.dcc                 = pipe->plane_state->dcc.enable;
-+	input->src.dcc_rate            = 1;
-+	input->src.meta_pitch          = pipe->plane_state->dcc.grph.meta_pitch;
-+	input->src.source_scan         = dm_horz;
-+	input->src.sw_mode             = pipe->plane_state->tiling_info.gfx9.swizzle;
-+
-+	input->src.viewport_width      = pipe->plane_res.scl_data.viewport.width;
-+	input->src.viewport_height     = pipe->plane_res.scl_data.viewport.height;
-+	input->src.data_pitch          = pipe->plane_res.scl_data.viewport.width;
-+	input->src.data_pitch_c        = pipe->plane_res.scl_data.viewport.width;
-+	input->src.cur0_src_width      = 128; /* TODO: Cursor calcs, not curently stored */
-+	input->src.cur0_bpp            = 32;
-+
-+	switch (pipe->plane_state->tiling_info.gfx9.swizzle) {
-+	/* for 4/8/16 high tiles */
-+	case DC_SW_LINEAR:
-+		input->src.is_display_sw = 1;
-+		input->src.macro_tile_size = dm_4k_tile;
-+		break;
-+	case DC_SW_4KB_S:
-+	case DC_SW_4KB_S_X:
-+		input->src.is_display_sw = 0;
-+		input->src.macro_tile_size = dm_4k_tile;
-+		break;
-+	case DC_SW_64KB_S:
-+	case DC_SW_64KB_S_X:
-+	case DC_SW_64KB_S_T:
-+		input->src.is_display_sw = 0;
-+		input->src.macro_tile_size = dm_64k_tile;
-+		break;
-+	case DC_SW_VAR_S:
-+	case DC_SW_VAR_S_X:
-+		input->src.is_display_sw = 0;
-+		input->src.macro_tile_size = dm_256k_tile;
-+		break;
-+
-+	/* For 64bpp 2 high tiles */
-+	case DC_SW_4KB_D:
-+	case DC_SW_4KB_D_X:
-+		input->src.is_display_sw = 1;
-+		input->src.macro_tile_size = dm_4k_tile;
-+		break;
-+	case DC_SW_64KB_D:
-+	case DC_SW_64KB_D_X:
-+	case DC_SW_64KB_D_T:
-+		input->src.is_display_sw = 1;
-+		input->src.macro_tile_size = dm_64k_tile;
-+		break;
-+	case DC_SW_VAR_D:
-+	case DC_SW_VAR_D_X:
-+		input->src.is_display_sw = 1;
-+		input->src.macro_tile_size = dm_256k_tile;
-+		break;
-+
-+	/* Unsupported swizzle modes for dcn */
-+	case DC_SW_256B_S:
-+	default:
-+		ASSERT(0); /* Not supported */
-+		break;
-+	}
-+
-+	switch (pipe->plane_state->rotation) {
-+	case ROTATION_ANGLE_0:
-+	case ROTATION_ANGLE_180:
-+		input->src.source_scan = dm_horz;
-+		break;
-+	case ROTATION_ANGLE_90:
-+	case ROTATION_ANGLE_270:
-+		input->src.source_scan = dm_vert;
-+		break;
-+	default:
-+		ASSERT(0); /* Not supported */
-+		break;
-+	}
-+
-+	/* TODO: Fix pixel format mappings */
-+	switch (pipe->plane_state->format) {
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
-+		input->src.source_format = dm_420_8;
-+		input->src.viewport_width_c    = input->src.viewport_width / 2;
-+		input->src.viewport_height_c   = input->src.viewport_height / 2;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
-+		input->src.source_format = dm_420_10;
-+		input->src.viewport_width_c    = input->src.viewport_width / 2;
-+		input->src.viewport_height_c   = input->src.viewport_height / 2;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+		input->src.source_format = dm_444_64;
-+		input->src.viewport_width_c    = input->src.viewport_width;
-+		input->src.viewport_height_c   = input->src.viewport_height;
-+		break;
-+	default:
-+		input->src.source_format = dm_444_32;
-+		input->src.viewport_width_c    = input->src.viewport_width;
-+		input->src.viewport_height_c   = input->src.viewport_height;
-+		break;
-+	}
-+
-+	input->scale_taps.htaps                = pipe->plane_res.scl_data.taps.h_taps;
-+	input->scale_ratio_depth.hscl_ratio    = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;
-+	input->scale_ratio_depth.vscl_ratio    = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;
-+	input->scale_ratio_depth.vinit =  pipe->plane_res.scl_data.inits.v.value/4294967296.0;
-+	if (input->scale_ratio_depth.vinit < 1.0)
-+			input->scale_ratio_depth.vinit = 1;
-+	input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
-+	input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;
-+	input->scale_taps.htaps_c              = pipe->plane_res.scl_data.taps.h_taps_c;
-+	input->scale_ratio_depth.hscl_ratio_c  = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0;
-+	input->scale_ratio_depth.vscl_ratio_c  = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0;
-+	input->scale_ratio_depth.vinit_c       = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0;
-+	if (input->scale_ratio_depth.vinit_c < 1.0)
-+			input->scale_ratio_depth.vinit_c = 1;
-+	switch (pipe->plane_res.scl_data.lb_params.depth) {
-+	case LB_PIXEL_DEPTH_30BPP:
-+		input->scale_ratio_depth.lb_depth = 30; break;
-+	case LB_PIXEL_DEPTH_36BPP:
-+		input->scale_ratio_depth.lb_depth = 36; break;
-+	default:
-+		input->scale_ratio_depth.lb_depth = 24; break;
-+	}
-+
-+
-+	input->dest.vactive        = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top
-+			+ pipe->stream->timing.v_border_bottom;
-+
-+	input->dest.recout_width   = pipe->plane_res.scl_data.recout.width;
-+	input->dest.recout_height  = pipe->plane_res.scl_data.recout.height;
-+
-+	input->dest.full_recout_width   = pipe->plane_res.scl_data.recout.width;
-+	input->dest.full_recout_height  = pipe->plane_res.scl_data.recout.height;
-+
-+	input->dest.htotal         = pipe->stream->timing.h_total;
-+	input->dest.hblank_start   = input->dest.htotal - pipe->stream->timing.h_front_porch;
-+	input->dest.hblank_end     = input->dest.hblank_start
-+			- pipe->stream->timing.h_addressable
-+			- pipe->stream->timing.h_border_left
-+			- pipe->stream->timing.h_border_right;
-+
-+	input->dest.vtotal         = pipe->stream->timing.v_total;
-+	input->dest.vblank_start   = input->dest.vtotal - pipe->stream->timing.v_front_porch;
-+	input->dest.vblank_end     = input->dest.vblank_start
-+			- pipe->stream->timing.v_addressable
-+			- pipe->stream->timing.v_border_bottom
-+			- pipe->stream->timing.v_border_top;
-+	input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0;
-+	input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
-+	input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
-+	input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
-+	input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
-+
-+}
-+
-+static void dcn_bw_calc_rq_dlg_ttu(
-+		const struct dc *dc,
-+		const struct dcn_bw_internal_vars *v,
-+		struct pipe_ctx *pipe,
-+		int in_idx)
-+{
-+	struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);
-+	struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
-+	struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
-+	struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
-+	struct _vcs_dpi_display_rq_params_st rq_param = {0};
-+	struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0};
-+	struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } };
-+	float total_active_bw = 0;
-+	float total_prefetch_bw = 0;
-+	int total_flip_bytes = 0;
-+	int i;
-+
-+	for (i = 0; i < number_of_planes; i++) {
-+		total_active_bw += v->read_bandwidth[i];
-+		total_prefetch_bw += v->prefetch_bandwidth[i];
-+		total_flip_bytes += v->total_immediate_flip_bytes[i];
-+	}
-+	dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
-+	if (dlg_sys_param.total_flip_bw < 0.0)
-+		dlg_sys_param.total_flip_bw = 0;
-+
-+	dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark;
-+	dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
-+	dlg_sys_param.t_urg_wm_us = v->urgent_watermark;
-+	dlg_sys_param.t_extra_us = v->urgent_extra_latency;
-+	dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
-+	dlg_sys_param.total_flip_bytes = total_flip_bytes;
-+
-+	pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe);
-+	input.clks_cfg.dcfclk_mhz = v->dcfclk;
-+	input.clks_cfg.dispclk_mhz = v->dispclk;
-+	input.clks_cfg.dppclk_mhz = v->dppclk;
-+	input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz/1000;
-+	input.clks_cfg.socclk_mhz = v->socclk;
-+	input.clks_cfg.voltage = v->voltage_level;
-+//	dc->dml.logger = pool->base.logger;
-+	input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
-+	input.dout.output_type  = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
-+	//input[in_idx].dout.output_standard;
-+	switch (v->output_deep_color[in_idx]) {
-+	case dcn_bw_encoder_12bpc:
-+		input.dout.output_bpc = dm_out_12;
-+	break;
-+	case dcn_bw_encoder_10bpc:
-+		input.dout.output_bpc = dm_out_10;
-+	break;
-+	case dcn_bw_encoder_8bpc:
-+	default:
-+		input.dout.output_bpc = dm_out_8;
-+	break;
-+	}
-+
-+	/*todo: soc->sr_enter_plus_exit_time??*/
-+	dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
-+
-+	dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
-+	dml1_extract_rq_regs(dml, rq_regs, rq_param);
-+	dml1_rq_dlg_get_dlg_params(
-+			dml,
-+			dlg_regs,
-+			ttu_regs,
-+			rq_param.dlg,
-+			dlg_sys_param,
-+			input,
-+			true,
-+			true,
-+			v->pte_enable == dcn_bw_yes,
-+			pipe->plane_state->flip_immediate);
-+}
-+
-+static void split_stream_across_pipes(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool,
-+		struct pipe_ctx *primary_pipe,
-+		struct pipe_ctx *secondary_pipe)
-+{
-+	int pipe_idx = secondary_pipe->pipe_idx;
-+
-+	if (!primary_pipe->plane_state)
-+		return;
-+
-+	*secondary_pipe = *primary_pipe;
-+
-+	secondary_pipe->pipe_idx = pipe_idx;
-+	secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
-+	secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
-+	secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
-+	secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
-+	secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
-+	if (primary_pipe->bottom_pipe) {
-+		ASSERT(primary_pipe->bottom_pipe != secondary_pipe);
-+		secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
-+		secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
-+	}
-+	primary_pipe->bottom_pipe = secondary_pipe;
-+	secondary_pipe->top_pipe = primary_pipe;
-+
-+	resource_build_scaling_params(primary_pipe);
-+	resource_build_scaling_params(secondary_pipe);
-+}
-+
-+static void calc_wm_sets_and_perf_params(
-+		struct dc_state *context,
-+		struct dcn_bw_internal_vars *v)
-+{
-+	/* Calculate set A last to keep internal var state consistent for required config */
-+	if (v->voltage_level < 2) {
-+		v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8;
-+		v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8;
-+		v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
-+		dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
-+
-+		context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
-+			v->stutter_exit_watermark * 1000;
-+		context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
-+				v->stutter_enter_plus_exit_watermark * 1000;
-+		context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
-+				v->dram_clock_change_watermark * 1000;
-+		context->bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
-+		context->bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
-+
-+		v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
-+		v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
-+		v->dcfclk = v->dcfclkv_nom0p8;
-+		dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
-+
-+		context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
-+			v->stutter_exit_watermark * 1000;
-+		context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
-+				v->stutter_enter_plus_exit_watermark * 1000;
-+		context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
-+				v->dram_clock_change_watermark * 1000;
-+		context->bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
-+		context->bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
-+	}
-+
-+	if (v->voltage_level < 3) {
-+		v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9;
-+		v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9;
-+		v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9;
-+		v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9;
-+		v->dcfclk_per_state[2] = v->dcfclkv_max0p9;
-+		v->dcfclk_per_state[1] = v->dcfclkv_max0p9;
-+		v->dcfclk_per_state[0] = v->dcfclkv_max0p9;
-+		v->dcfclk = v->dcfclkv_max0p9;
-+		dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
-+
-+		context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
-+			v->stutter_exit_watermark * 1000;
-+		context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
-+				v->stutter_enter_plus_exit_watermark * 1000;
-+		context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
-+				v->dram_clock_change_watermark * 1000;
-+		context->bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
-+		context->bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
-+	}
-+
-+	v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
-+	v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
-+	v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
-+	v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
-+	v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
-+	v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
-+	v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
-+	v->dcfclk = v->dcfclk_per_state[v->voltage_level];
-+	dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
-+
-+	context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
-+		v->stutter_exit_watermark * 1000;
-+	context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
-+			v->stutter_enter_plus_exit_watermark * 1000;
-+	context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
-+			v->dram_clock_change_watermark * 1000;
-+	context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
-+	context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
-+	if (v->voltage_level >= 2) {
-+		context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
-+		context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
-+	}
-+	if (v->voltage_level >= 3)
-+		context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
-+}
-+
-+static bool dcn_bw_apply_registry_override(struct dc *dc)
-+{
-+	bool updated = false;
-+
-+	kernel_fpu_begin();
-+	if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
-+			&& dc->debug.sr_exit_time_ns) {
-+		updated = true;
-+		dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0;
-+	}
-+
-+	if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)
-+				!= dc->debug.sr_enter_plus_exit_time_ns
-+			&& dc->debug.sr_enter_plus_exit_time_ns) {
-+		updated = true;
-+		dc->dcn_soc->sr_enter_plus_exit_time =
-+				dc->debug.sr_enter_plus_exit_time_ns / 1000.0;
-+	}
-+
-+	if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns
-+			&& dc->debug.urgent_latency_ns) {
-+		updated = true;
-+		dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0;
-+	}
-+
-+	if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)
-+				!= dc->debug.percent_of_ideal_drambw
-+			&& dc->debug.percent_of_ideal_drambw) {
-+		updated = true;
-+		dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =
-+				dc->debug.percent_of_ideal_drambw;
-+	}
-+
-+	if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)
-+				!= dc->debug.dram_clock_change_latency_ns
-+			&& dc->debug.dram_clock_change_latency_ns) {
-+		updated = true;
-+		dc->dcn_soc->dram_clock_change_latency =
-+				dc->debug.dram_clock_change_latency_ns / 1000.0;
-+	}
-+	kernel_fpu_end();
-+
-+	return updated;
-+}
-+
-+void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
-+{
-+	/*
-+	 * disable optional pipe split by lower dispclk bounding box
-+	 * at DPM0
-+	 */
-+	v->max_dispclk[0] = v->max_dppclk_vmin0p65;
-+}
-+
-+void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
-+		unsigned int pixel_rate_khz)
-+{
-+	float pixel_rate_mhz = pixel_rate_khz / 1000;
-+
-+	/*
-+	 * force enabling pipe split by lower dpp clock for DPM0 to just
-+	 * below the specify pixel_rate, so bw calc would split pipe.
-+	 */
-+	if (pixel_rate_mhz < v->max_dppclk[0])
-+		v->max_dppclk[0] = pixel_rate_mhz;
-+}
-+
-+void hack_bounding_box(struct dcn_bw_internal_vars *v,
-+		struct dc_debug *dbg,
-+		struct dc_state *context)
-+{
-+	if (dbg->pipe_split_policy == MPC_SPLIT_AVOID) {
-+		hack_disable_optional_pipe_split(v);
-+	}
-+
-+	if (dbg->pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP &&
-+		context->stream_count >= 2) {
-+		hack_disable_optional_pipe_split(v);
-+	}
-+
-+	if (context->stream_count == 1 &&
-+			dbg->force_single_disp_pipe_split) {
-+		struct dc_stream_state *stream0 = context->streams[0];
-+
-+		hack_force_pipe_split(v, stream0->timing.pix_clk_khz);
-+	}
-+}
-+
-+bool dcn_validate_bandwidth(
-+		struct dc *dc,
-+		struct dc_state *context)
-+{
-+	const struct resource_pool *pool = dc->res_pool;
-+	struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
-+	int i, input_idx;
-+	int vesa_sync_start, asic_blank_end, asic_blank_start;
-+	bool bw_limit_pass;
-+	float bw_limit;
-+
-+	PERFORMANCE_TRACE_START();
-+	if (dcn_bw_apply_registry_override(dc))
-+		dcn_bw_sync_calcs_and_dml(dc);
-+
-+	memset(v, 0, sizeof(*v));
-+	kernel_fpu_begin();
-+	v->sr_exit_time = dc->dcn_soc->sr_exit_time;
-+	v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
-+	v->urgent_latency = dc->dcn_soc->urgent_latency;
-+	v->write_back_latency = dc->dcn_soc->write_back_latency;
-+	v->percent_of_ideal_drambw_received_after_urg_latency =
-+			dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
-+
-+	v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65;
-+	v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72;
-+	v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8;
-+	v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9;
-+
-+	v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65;
-+	v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72;
-+	v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8;
-+	v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9;
-+
-+	v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65;
-+	v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72;
-+	v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8;
-+	v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9;
-+
-+	v->socclk = dc->dcn_soc->socclk;
-+
-+	v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;
-+	v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;
-+	v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;
-+	v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;
-+
-+	v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65;
-+	v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72;
-+	v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8;
-+	v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9;
-+
-+	v->downspreading = dc->dcn_soc->downspreading;
-+	v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles;
-+	v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel;
-+	v->number_of_channels = dc->dcn_soc->number_of_channels;
-+	v->vmm_page_size = dc->dcn_soc->vmm_page_size;
-+	v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency;
-+	v->return_bus_width = dc->dcn_soc->return_bus_width;
-+
-+	v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte;
-+	v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte;
-+	v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
-+	v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
-+	v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte;
-+	v->pte_enable = dc->dcn_ip->pte_enable;
-+	v->pte_chunk_size = dc->dcn_ip->pte_chunk_size;
-+	v->meta_chunk_size = dc->dcn_ip->meta_chunk_size;
-+	v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size;
-+	v->odm_capability = dc->dcn_ip->odm_capability;
-+	v->dsc_capability = dc->dcn_ip->dsc_capability;
-+	v->line_buffer_size = dc->dcn_ip->line_buffer_size;
-+	v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed;
-+	v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp;
-+	v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
-+	v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size;
-+	v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size;
-+	v->max_num_dpp = dc->dcn_ip->max_num_dpp;
-+	v->max_num_writeback = dc->dcn_ip->max_num_writeback;
-+	v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput;
-+	v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput;
-+	v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput;
-+	v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput;
-+	v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
-+	v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
-+	v->max_hscl_taps = dc->dcn_ip->max_hscl_taps;
-+	v->max_vscl_taps = dc->dcn_ip->max_vscl_taps;
-+	v->under_scan_factor = dc->dcn_ip->under_scan_factor;
-+	v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests;
-+	v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin;
-+	v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
-+	v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
-+			dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
-+	v->bug_forcing_luma_and_chroma_request_to_same_size_fixed =
-+			dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed;
-+
-+	v->voltage[5] = dcn_bw_no_support;
-+	v->voltage[4] = dcn_bw_v_max0p9;
-+	v->voltage[3] = dcn_bw_v_max0p9;
-+	v->voltage[2] = dcn_bw_v_nom0p8;
-+	v->voltage[1] = dcn_bw_v_mid0p72;
-+	v->voltage[0] = dcn_bw_v_min0p65;
-+	v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9;
-+	v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9;
-+	v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9;
-+	v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
-+	v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
-+	v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
-+	v->dcfclk_per_state[5] = v->dcfclkv_max0p9;
-+	v->dcfclk_per_state[4] = v->dcfclkv_max0p9;
-+	v->dcfclk_per_state[3] = v->dcfclkv_max0p9;
-+	v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
-+	v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
-+	v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
-+	v->max_dispclk[5] = v->max_dispclk_vmax0p9;
-+	v->max_dispclk[4] = v->max_dispclk_vmax0p9;
-+	v->max_dispclk[3] = v->max_dispclk_vmax0p9;
-+	v->max_dispclk[2] = v->max_dispclk_vnom0p8;
-+	v->max_dispclk[1] = v->max_dispclk_vmid0p72;
-+	v->max_dispclk[0] = v->max_dispclk_vmin0p65;
-+	v->max_dppclk[5] = v->max_dppclk_vmax0p9;
-+	v->max_dppclk[4] = v->max_dppclk_vmax0p9;
-+	v->max_dppclk[3] = v->max_dppclk_vmax0p9;
-+	v->max_dppclk[2] = v->max_dppclk_vnom0p8;
-+	v->max_dppclk[1] = v->max_dppclk_vmid0p72;
-+	v->max_dppclk[0] = v->max_dppclk_vmin0p65;
-+	v->phyclk_per_state[5] = v->phyclkv_max0p9;
-+	v->phyclk_per_state[4] = v->phyclkv_max0p9;
-+	v->phyclk_per_state[3] = v->phyclkv_max0p9;
-+	v->phyclk_per_state[2] = v->phyclkv_nom0p8;
-+	v->phyclk_per_state[1] = v->phyclkv_mid0p72;
-+	v->phyclk_per_state[0] = v->phyclkv_min0p65;
-+
-+	hack_bounding_box(v, &dc->debug, context);
-+
-+	if (v->voltage_override == dcn_bw_v_max0p9) {
-+		v->voltage_override_level = number_of_states - 1;
-+	} else if (v->voltage_override == dcn_bw_v_nom0p8) {
-+		v->voltage_override_level = number_of_states - 2;
-+	} else if (v->voltage_override == dcn_bw_v_mid0p72) {
-+		v->voltage_override_level = number_of_states - 3;
-+	} else {
-+		v->voltage_override_level = 0;
-+	}
-+	v->synchronized_vblank = dcn_bw_no;
-+	v->ta_pscalculation = dcn_bw_override;
-+	v->allow_different_hratio_vratio = dcn_bw_yes;
-+
-+
-+	for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
-+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
-+
-+		if (!pipe->stream)
-+			continue;
-+		/* skip all but first of split pipes */
-+		if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
-+			continue;
-+
-+		v->underscan_output[input_idx] = false; /* taken care of in recout already*/
-+		v->interlace_output[input_idx] = false;
-+
-+		v->htotal[input_idx] = pipe->stream->timing.h_total;
-+		v->vtotal[input_idx] = pipe->stream->timing.v_total;
-+		v->vactive[input_idx] = pipe->stream->timing.v_addressable +
-+				pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom;
-+		v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
-+				- v->vactive[input_idx]
-+				- pipe->stream->timing.v_front_porch;
-+		v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f;
-+
-+		if (!pipe->plane_state) {
-+			v->dcc_enable[input_idx] = dcn_bw_yes;
-+			v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
-+			v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
-+			v->lb_bit_per_pixel[input_idx] = 30;
-+			v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
-+			v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
-+			v->scaler_rec_out_width[input_idx] = pipe->stream->timing.h_addressable;
-+			v->scaler_recout_height[input_idx] = pipe->stream->timing.v_addressable;
-+			v->override_hta_ps[input_idx] = 1;
-+			v->override_vta_ps[input_idx] = 1;
-+			v->override_hta_pschroma[input_idx] = 1;
-+			v->override_vta_pschroma[input_idx] = 1;
-+			v->source_scan[input_idx] = dcn_bw_hor;
-+
-+		} else {
-+			v->viewport_height[input_idx] =  pipe->plane_res.scl_data.viewport.height;
-+			v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width;
-+			v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width;
-+			v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height;
-+			if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
-+				if (pipe->plane_state->rotation % 2 == 0) {
-+					int viewport_end = pipe->plane_res.scl_data.viewport.width
-+							+ pipe->plane_res.scl_data.viewport.x;
-+					int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width
-+							+ pipe->bottom_pipe->plane_res.scl_data.viewport.x;
-+
-+					if (viewport_end > viewport_b_end)
-+						v->viewport_width[input_idx] = viewport_end
-+							- pipe->bottom_pipe->plane_res.scl_data.viewport.x;
-+					else
-+						v->viewport_width[input_idx] = viewport_b_end
-+									- pipe->plane_res.scl_data.viewport.x;
-+				} else  {
-+					int viewport_end = pipe->plane_res.scl_data.viewport.height
-+						+ pipe->plane_res.scl_data.viewport.y;
-+					int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height
-+						+ pipe->bottom_pipe->plane_res.scl_data.viewport.y;
-+
-+					if (viewport_end > viewport_b_end)
-+						v->viewport_height[input_idx] = viewport_end
-+							- pipe->bottom_pipe->plane_res.scl_data.viewport.y;
-+					else
-+						v->viewport_height[input_idx] = viewport_b_end
-+									- pipe->plane_res.scl_data.viewport.y;
-+				}
-+				v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width
-+						+ pipe->bottom_pipe->plane_res.scl_data.recout.width;
-+			}
-+
-+			v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
-+			v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
-+					pipe->plane_state->format);
-+			v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
-+					pipe->plane_state->tiling_info.gfx9.swizzle);
-+			v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);
-+			v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
-+			v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
-+			v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;
-+			v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;
-+			v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
-+		}
-+		if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
-+			v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
-+		v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
-+		v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
-+				PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444;
-+		v->output[input_idx] = pipe->stream->sink->sink_signal ==
-+				SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp;
-+		v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc;
-+		if (v->output[input_idx] == dcn_bw_hdmi) {
-+			switch (pipe->stream->timing.display_color_depth) {
-+			case COLOR_DEPTH_101010:
-+				v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc;
-+				break;
-+			case COLOR_DEPTH_121212:
-+				v->output_deep_color[input_idx]  = dcn_bw_encoder_12bpc;
-+				break;
-+			case COLOR_DEPTH_161616:
-+				v->output_deep_color[input_idx]  = dcn_bw_encoder_16bpc;
-+				break;
-+			default:
-+				break;
-+			}
-+		}
-+
-+		input_idx++;
-+	}
-+	v->number_of_active_planes = input_idx;
-+
-+	scaler_settings_calculation(v);
-+	mode_support_and_system_configuration(v);
-+
-+	if (v->voltage_level == 0 &&
-+			(dc->debug.sr_exit_time_dpm0_ns
-+				|| dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {
-+
-+		if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)
-+			v->sr_enter_plus_exit_time =
-+				dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
-+		if (dc->debug.sr_exit_time_dpm0_ns)
-+			v->sr_exit_time =  dc->debug.sr_exit_time_dpm0_ns / 1000.0f;
-+		dc->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
-+		dc->dml.soc.sr_exit_time_us = v->sr_exit_time;
-+		mode_support_and_system_configuration(v);
-+	}
-+
-+	if (v->voltage_level != 5) {
-+		float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
-+		if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
-+			bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65;
-+		else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72)
-+			bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72;
-+		else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8)
-+			bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8;
-+		else
-+			bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;
-+
-+		if (bw_consumed < v->fabric_and_dram_bandwidth)
-+			if (dc->debug.voltage_align_fclk)
-+				bw_consumed = v->fabric_and_dram_bandwidth;
-+
-+		display_pipe_configuration(v);
-+		calc_wm_sets_and_perf_params(context, v);
-+		context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 /
-+				(ddr4_dram_factor_single_Channel * v->number_of_channels));
-+		if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) {
-+			context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
-+		}
-+
-+		context->bw.dcn.calc_clk.dram_ccm_us = (int)(v->dram_clock_change_margin);
-+		context->bw.dcn.calc_clk.min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin);
-+		context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
-+		context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000);
-+
-+		context->bw.dcn.calc_clk.dispclk_khz = (int)(v->dispclk * 1000);
-+		if (dc->debug.max_disp_clk == true)
-+			context->bw.dcn.calc_clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
-+
-+		if (context->bw.dcn.calc_clk.dispclk_khz <
-+				dc->debug.min_disp_clk_khz) {
-+			context->bw.dcn.calc_clk.dispclk_khz =
-+					dc->debug.min_disp_clk_khz;
-+		}
-+
-+		context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2;
-+
-+		for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
-+			struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
-+
-+			/* skip inactive pipe */
-+			if (!pipe->stream)
-+				continue;
-+			/* skip all but first of split pipes */
-+			if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
-+				continue;
-+
-+			pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
-+			pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx];
-+			pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx];
-+			pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
-+
-+			pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
-+			pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
-+			vesa_sync_start = pipe->stream->timing.v_addressable +
-+						pipe->stream->timing.v_border_bottom +
-+						pipe->stream->timing.v_front_porch;
-+
-+			asic_blank_end = (pipe->stream->timing.v_total -
-+						vesa_sync_start -
-+						pipe->stream->timing.v_border_top)
-+			* (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
-+
-+			asic_blank_start = asic_blank_end +
-+						(pipe->stream->timing.v_border_top +
-+						pipe->stream->timing.v_addressable +
-+						pipe->stream->timing.v_border_bottom)
-+			* (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
-+
-+			pipe->pipe_dlg_param.vblank_start = asic_blank_start;
-+			pipe->pipe_dlg_param.vblank_end = asic_blank_end;
-+
-+			if (pipe->plane_state) {
-+				struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
-+
-+				if (v->dpp_per_plane[input_idx] == 2 ||
-+					((pipe->stream->view_format ==
-+					  VIEW_3D_FORMAT_SIDE_BY_SIDE ||
-+					  pipe->stream->view_format ==
-+					  VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
-+					(pipe->stream->timing.timing_3d_format ==
-+					 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
-+					 pipe->stream->timing.timing_3d_format ==
-+					 TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
-+					if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
-+						/* update previously split pipe */
-+						hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
-+						hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx];
-+						hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx];
-+						hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
-+
-+						hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
-+						hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
-+						hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;
-+						hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
-+					} else {
-+						/* pipe not split previously needs split */
-+						hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool);
-+						ASSERT(hsplit_pipe);
-+						split_stream_across_pipes(
-+							&context->res_ctx, pool,
-+							pipe, hsplit_pipe);
-+					}
-+
-+					dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);
-+				} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
-+					/* merge previously split pipe */
-+					pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
-+					if (hsplit_pipe->bottom_pipe)
-+						hsplit_pipe->bottom_pipe->top_pipe = pipe;
-+					hsplit_pipe->plane_state = NULL;
-+					hsplit_pipe->stream = NULL;
-+					hsplit_pipe->top_pipe = NULL;
-+					hsplit_pipe->bottom_pipe = NULL;
-+					/* Clear plane_res and stream_res */
-+					memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
-+					memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
-+					resource_build_scaling_params(pipe);
-+				}
-+				/* for now important to do this after pipe split for building e2e params */
-+				dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);
-+			}
-+
-+			input_idx++;
-+		}
-+	}
-+
-+	if (v->voltage_level == 0) {
-+
-+		dc->dml.soc.sr_enter_plus_exit_time_us =
-+				dc->dcn_soc->sr_enter_plus_exit_time;
-+		dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
-+	}
-+
-+	/*
-+	 * BW limit is set to prevent display from impacting other system functions
-+	 */
-+
-+	bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
-+	bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
-+
-+	kernel_fpu_end();
-+
-+	PERFORMANCE_TRACE_END();
-+
-+	if (bw_limit_pass && v->voltage_level != 5)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+static unsigned int dcn_find_normalized_clock_vdd_Level(
-+	const struct dc *dc,
-+	enum dm_pp_clock_type clocks_type,
-+	int clocks_in_khz)
-+{
-+	int vdd_level = dcn_bw_v_min0p65;
-+
-+	if (clocks_in_khz == 0)/*todo some clock not in the considerations*/
-+		return vdd_level;
-+
-+	switch (clocks_type) {
-+	case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
-+		if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {
-+			vdd_level = dcn_bw_v_max0p91;
-+			BREAK_TO_DEBUGGER();
-+		} else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {
-+			vdd_level = dcn_bw_v_max0p9;
-+		} else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {
-+			vdd_level = dcn_bw_v_nom0p8;
-+		} else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) {
-+			vdd_level = dcn_bw_v_mid0p72;
-+		} else
-+			vdd_level = dcn_bw_v_min0p65;
-+		break;
-+	case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
-+		if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {
-+			vdd_level = dcn_bw_v_max0p91;
-+			BREAK_TO_DEBUGGER();
-+		} else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {
-+			vdd_level = dcn_bw_v_max0p9;
-+		} else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {
-+			vdd_level = dcn_bw_v_nom0p8;
-+		} else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) {
-+			vdd_level = dcn_bw_v_mid0p72;
-+		} else
-+			vdd_level = dcn_bw_v_min0p65;
-+		break;
-+
-+	case DM_PP_CLOCK_TYPE_DPPCLK:
-+		if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {
-+			vdd_level = dcn_bw_v_max0p91;
-+			BREAK_TO_DEBUGGER();
-+		} else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {
-+			vdd_level = dcn_bw_v_max0p9;
-+		} else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) {
-+			vdd_level = dcn_bw_v_nom0p8;
-+		} else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) {
-+			vdd_level = dcn_bw_v_mid0p72;
-+		} else
-+			vdd_level = dcn_bw_v_min0p65;
-+		break;
-+
-+	case DM_PP_CLOCK_TYPE_MEMORY_CLK:
-+		{
-+			unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
-+
-+			if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
-+				vdd_level = dcn_bw_v_max0p91;
-+				BREAK_TO_DEBUGGER();
-+			} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
-+				vdd_level = dcn_bw_v_max0p9;
-+			} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {
-+				vdd_level = dcn_bw_v_nom0p8;
-+			} else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {
-+				vdd_level = dcn_bw_v_mid0p72;
-+			} else
-+				vdd_level = dcn_bw_v_min0p65;
-+		}
-+		break;
-+
-+	case DM_PP_CLOCK_TYPE_DCFCLK:
-+		if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {
-+			vdd_level = dcn_bw_v_max0p91;
-+			BREAK_TO_DEBUGGER();
-+		} else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {
-+			vdd_level = dcn_bw_v_max0p9;
-+		} else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) {
-+			vdd_level = dcn_bw_v_nom0p8;
-+		} else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) {
-+			vdd_level = dcn_bw_v_mid0p72;
-+		} else
-+			vdd_level = dcn_bw_v_min0p65;
-+		break;
-+
-+	default:
-+		 break;
-+	}
-+	return vdd_level;
-+}
-+
-+unsigned int dcn_find_dcfclk_suits_all(
-+	const struct dc *dc,
-+	struct clocks_value *clocks)
-+{
-+	unsigned vdd_level, vdd_level_temp;
-+	unsigned dcf_clk;
-+
-+	/*find a common supported voltage level*/
-+	vdd_level = dcn_find_normalized_clock_vdd_Level(
-+		dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_in_khz);
-+	vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
-+		dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_in_khz);
-+
-+	vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
-+	vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
-+		dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_in_khz);
-+	vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
-+
-+	vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
-+		dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->dcfclock_in_khz);
-+	vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
-+	vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
-+		dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclock_in_khz);
-+
-+	/*find that level conresponding dcfclk*/
-+	vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
-+	if (vdd_level == dcn_bw_v_max0p91) {
-+		BREAK_TO_DEBUGGER();
-+		dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;
-+	} else if (vdd_level == dcn_bw_v_max0p9)
-+		dcf_clk =  dc->dcn_soc->dcfclkv_max0p9*1000;
-+	else if (vdd_level == dcn_bw_v_nom0p8)
-+		dcf_clk =  dc->dcn_soc->dcfclkv_nom0p8*1000;
-+	else if (vdd_level == dcn_bw_v_mid0p72)
-+		dcf_clk =  dc->dcn_soc->dcfclkv_mid0p72*1000;
-+	else
-+		dcf_clk =  dc->dcn_soc->dcfclkv_min0p65*1000;
-+
-+	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"\tdcf_clk for voltage = %d\n", dcf_clk);
-+	return dcf_clk;
-+}
-+
-+static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
-+{
-+	int i;
-+
-+	if (clks->num_levels == 0)
-+		return false;
-+
-+	for (i = 0; i < clks->num_levels; i++)
-+		/* Ensure that the result is sane */
-+		if (clks->data[i].clocks_in_khz == 0)
-+			return false;
-+
-+	return true;
-+}
-+
-+void dcn_bw_update_from_pplib(struct dc *dc)
-+{
-+	struct dc_context *ctx = dc->ctx;
-+	struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
-+	bool res;
-+
-+	kernel_fpu_begin();
-+
-+	/* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */
-+	res = dm_pp_get_clock_levels_by_type_with_voltage(
-+			ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
-+
-+	if (res)
-+		res = verify_clock_values(&fclks);
-+
-+	if (res) {
-+		ASSERT(fclks.num_levels >= 3);
-+		dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0;
-+		dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels *
-+				(fclks.data[fclks.num_levels - (fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0)
-+				* ddr4_dram_factor_single_Channel / 1000.0;
-+		dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels *
-+				(fclks.data[fclks.num_levels - 2].clocks_in_khz / 1000.0)
-+				* ddr4_dram_factor_single_Channel / 1000.0;
-+		dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels *
-+				(fclks.data[fclks.num_levels - 1].clocks_in_khz / 1000.0)
-+				* ddr4_dram_factor_single_Channel / 1000.0;
-+	} else
-+		BREAK_TO_DEBUGGER();
-+
-+	res = dm_pp_get_clock_levels_by_type_with_voltage(
-+			ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
-+
-+	if (res)
-+		res = verify_clock_values(&dcfclks);
-+
-+	if (res && dcfclks.num_levels >= 3) {
-+		dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0;
-+		dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0;
-+		dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0;
-+		dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0;
-+	} else
-+		BREAK_TO_DEBUGGER();
-+
-+	kernel_fpu_end();
-+}
-+
-+void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
-+{
-+	struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu;
-+	struct pp_smu_wm_range_sets ranges = {0};
-+	int max_fclk_khz, nom_fclk_khz, mid_fclk_khz, min_fclk_khz;
-+	int max_dcfclk_khz, min_dcfclk_khz;
-+	int socclk_khz;
-+	const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
-+	unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
-+
-+	if (!pp->set_wm_ranges)
-+		return;
-+
-+	kernel_fpu_begin();
-+	max_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000000 / factor;
-+	nom_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000000 / factor;
-+	mid_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000000 / factor;
-+	min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
-+	max_dcfclk_khz = dc->dcn_soc->dcfclkv_max0p9 * 1000;
-+	min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
-+	socclk_khz = dc->dcn_soc->socclk * 1000;
-+	kernel_fpu_end();
-+
-+	/* Now notify PPLib/SMU about which Watermarks sets they should select
-+	 * depending on DPM state they are in. And update BW MGR GFX Engine and
-+	 * Memory clock member variables for Watermarks calculations for each
-+	 * Watermark Set
-+	 */
-+	/* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
-+	 * care what the value is, hence min to overdrive level
-+	 */
-+	ranges.num_reader_wm_sets = WM_COUNT;
-+	ranges.num_writer_wm_sets = WM_COUNT;
-+	ranges.reader_wm_sets[0].wm_inst = WM_A;
-+	ranges.reader_wm_sets[0].min_drain_clk_khz = min_dcfclk_khz;
-+	ranges.reader_wm_sets[0].max_drain_clk_khz = max_dcfclk_khz;
-+	ranges.reader_wm_sets[0].min_fill_clk_khz = min_fclk_khz;
-+	ranges.reader_wm_sets[0].max_fill_clk_khz = min_fclk_khz;
-+	ranges.writer_wm_sets[0].wm_inst = WM_A;
-+	ranges.writer_wm_sets[0].min_fill_clk_khz = socclk_khz;
-+	ranges.writer_wm_sets[0].max_fill_clk_khz = overdrive;
-+	ranges.writer_wm_sets[0].min_drain_clk_khz = min_fclk_khz;
-+	ranges.writer_wm_sets[0].max_drain_clk_khz = min_fclk_khz;
-+
-+	ranges.reader_wm_sets[1].wm_inst = WM_B;
-+	ranges.reader_wm_sets[1].min_drain_clk_khz = min_fclk_khz;
-+	ranges.reader_wm_sets[1].max_drain_clk_khz = max_dcfclk_khz;
-+	ranges.reader_wm_sets[1].min_fill_clk_khz = mid_fclk_khz;
-+	ranges.reader_wm_sets[1].max_fill_clk_khz = mid_fclk_khz;
-+	ranges.writer_wm_sets[1].wm_inst = WM_B;
-+	ranges.writer_wm_sets[1].min_fill_clk_khz = socclk_khz;
-+	ranges.writer_wm_sets[1].max_fill_clk_khz = overdrive;
-+	ranges.writer_wm_sets[1].min_drain_clk_khz = mid_fclk_khz;
-+	ranges.writer_wm_sets[1].max_drain_clk_khz = mid_fclk_khz;
-+
-+
-+	ranges.reader_wm_sets[2].wm_inst = WM_C;
-+	ranges.reader_wm_sets[2].min_drain_clk_khz = min_fclk_khz;
-+	ranges.reader_wm_sets[2].max_drain_clk_khz = max_dcfclk_khz;
-+	ranges.reader_wm_sets[2].min_fill_clk_khz = nom_fclk_khz;
-+	ranges.reader_wm_sets[2].max_fill_clk_khz = nom_fclk_khz;
-+	ranges.writer_wm_sets[2].wm_inst = WM_C;
-+	ranges.writer_wm_sets[2].min_fill_clk_khz = socclk_khz;
-+	ranges.writer_wm_sets[2].max_fill_clk_khz = overdrive;
-+	ranges.writer_wm_sets[2].min_drain_clk_khz = nom_fclk_khz;
-+	ranges.writer_wm_sets[2].max_drain_clk_khz = nom_fclk_khz;
-+
-+	ranges.reader_wm_sets[3].wm_inst = WM_D;
-+	ranges.reader_wm_sets[3].min_drain_clk_khz = min_fclk_khz;
-+	ranges.reader_wm_sets[3].max_drain_clk_khz = max_dcfclk_khz;
-+	ranges.reader_wm_sets[3].min_fill_clk_khz = max_fclk_khz;
-+	ranges.reader_wm_sets[3].max_fill_clk_khz = max_fclk_khz;
-+	ranges.writer_wm_sets[3].wm_inst = WM_D;
-+	ranges.writer_wm_sets[3].min_fill_clk_khz = socclk_khz;
-+	ranges.writer_wm_sets[3].max_fill_clk_khz = overdrive;
-+	ranges.writer_wm_sets[3].min_drain_clk_khz = max_fclk_khz;
-+	ranges.writer_wm_sets[3].max_drain_clk_khz = max_fclk_khz;
-+
-+	if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
-+		ranges.reader_wm_sets[0].wm_inst = WM_A;
-+		ranges.reader_wm_sets[0].min_drain_clk_khz = 300000;
-+		ranges.reader_wm_sets[0].max_drain_clk_khz = 654000;
-+		ranges.reader_wm_sets[0].min_fill_clk_khz = 800000;
-+		ranges.reader_wm_sets[0].max_fill_clk_khz = 800000;
-+		ranges.writer_wm_sets[0].wm_inst = WM_A;
-+		ranges.writer_wm_sets[0].min_fill_clk_khz = 200000;
-+		ranges.writer_wm_sets[0].max_fill_clk_khz = 757000;
-+		ranges.writer_wm_sets[0].min_drain_clk_khz = 800000;
-+		ranges.writer_wm_sets[0].max_drain_clk_khz = 800000;
-+
-+		ranges.reader_wm_sets[1].wm_inst = WM_B;
-+		ranges.reader_wm_sets[1].min_drain_clk_khz = 300000;
-+		ranges.reader_wm_sets[1].max_drain_clk_khz = 654000;
-+		ranges.reader_wm_sets[1].min_fill_clk_khz = 933000;
-+		ranges.reader_wm_sets[1].max_fill_clk_khz = 933000;
-+		ranges.writer_wm_sets[1].wm_inst = WM_B;
-+		ranges.writer_wm_sets[1].min_fill_clk_khz = 200000;
-+		ranges.writer_wm_sets[1].max_fill_clk_khz = 757000;
-+		ranges.writer_wm_sets[1].min_drain_clk_khz = 933000;
-+		ranges.writer_wm_sets[1].max_drain_clk_khz = 933000;
-+
-+
-+		ranges.reader_wm_sets[2].wm_inst = WM_C;
-+		ranges.reader_wm_sets[2].min_drain_clk_khz = 300000;
-+		ranges.reader_wm_sets[2].max_drain_clk_khz = 654000;
-+		ranges.reader_wm_sets[2].min_fill_clk_khz = 1067000;
-+		ranges.reader_wm_sets[2].max_fill_clk_khz = 1067000;
-+		ranges.writer_wm_sets[2].wm_inst = WM_C;
-+		ranges.writer_wm_sets[2].min_fill_clk_khz = 200000;
-+		ranges.writer_wm_sets[2].max_fill_clk_khz = 757000;
-+		ranges.writer_wm_sets[2].min_drain_clk_khz = 1067000;
-+		ranges.writer_wm_sets[2].max_drain_clk_khz = 1067000;
-+
-+		ranges.reader_wm_sets[3].wm_inst = WM_D;
-+		ranges.reader_wm_sets[3].min_drain_clk_khz = 300000;
-+		ranges.reader_wm_sets[3].max_drain_clk_khz = 654000;
-+		ranges.reader_wm_sets[3].min_fill_clk_khz = 1200000;
-+		ranges.reader_wm_sets[3].max_fill_clk_khz = 1200000;
-+		ranges.writer_wm_sets[3].wm_inst = WM_D;
-+		ranges.writer_wm_sets[3].min_fill_clk_khz = 200000;
-+		ranges.writer_wm_sets[3].max_fill_clk_khz = 757000;
-+		ranges.writer_wm_sets[3].min_drain_clk_khz = 1200000;
-+		ranges.writer_wm_sets[3].max_drain_clk_khz = 1200000;
-+	}
-+
-+	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
-+	pp->set_wm_ranges(&pp->pp_smu, &ranges);
-+}
-+
-+void dcn_bw_sync_calcs_and_dml(struct dc *dc)
-+{
-+	kernel_fpu_begin();
-+	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"sr_exit_time: %d ns\n"
-+			"sr_enter_plus_exit_time: %d ns\n"
-+			"urgent_latency: %d ns\n"
-+			"write_back_latency: %d ns\n"
-+			"percent_of_ideal_drambw_received_after_urg_latency: %d %\n"
-+			"max_request_size: %d bytes\n"
-+			"dcfclkv_max0p9: %d kHz\n"
-+			"dcfclkv_nom0p8: %d kHz\n"
-+			"dcfclkv_mid0p72: %d kHz\n"
-+			"dcfclkv_min0p65: %d kHz\n"
-+			"max_dispclk_vmax0p9: %d kHz\n"
-+			"max_dispclk_vnom0p8: %d kHz\n"
-+			"max_dispclk_vmid0p72: %d kHz\n"
-+			"max_dispclk_vmin0p65: %d kHz\n"
-+			"max_dppclk_vmax0p9: %d kHz\n"
-+			"max_dppclk_vnom0p8: %d kHz\n"
-+			"max_dppclk_vmid0p72: %d kHz\n"
-+			"max_dppclk_vmin0p65: %d kHz\n"
-+			"socclk: %d kHz\n"
-+			"fabric_and_dram_bandwidth_vmax0p9: %d MB/s\n"
-+			"fabric_and_dram_bandwidth_vnom0p8: %d MB/s\n"
-+			"fabric_and_dram_bandwidth_vmid0p72: %d MB/s\n"
-+			"fabric_and_dram_bandwidth_vmin0p65: %d MB/s\n"
-+			"phyclkv_max0p9: %d kHz\n"
-+			"phyclkv_nom0p8: %d kHz\n"
-+			"phyclkv_mid0p72: %d kHz\n"
-+			"phyclkv_min0p65: %d kHz\n"
-+			"downspreading: %d %\n"
-+			"round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
-+			"urgent_out_of_order_return_per_channel: %d Bytes\n"
-+			"number_of_channels: %d\n"
-+			"vmm_page_size: %d Bytes\n"
-+			"dram_clock_change_latency: %d ns\n"
-+			"return_bus_width: %d Bytes\n",
-+			dc->dcn_soc->sr_exit_time * 1000,
-+			dc->dcn_soc->sr_enter_plus_exit_time * 1000,
-+			dc->dcn_soc->urgent_latency * 1000,
-+			dc->dcn_soc->write_back_latency * 1000,
-+			dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency,
-+			dc->dcn_soc->max_request_size,
-+			dc->dcn_soc->dcfclkv_max0p9 * 1000,
-+			dc->dcn_soc->dcfclkv_nom0p8 * 1000,
-+			dc->dcn_soc->dcfclkv_mid0p72 * 1000,
-+			dc->dcn_soc->dcfclkv_min0p65 * 1000,
-+			dc->dcn_soc->max_dispclk_vmax0p9 * 1000,
-+			dc->dcn_soc->max_dispclk_vnom0p8 * 1000,
-+			dc->dcn_soc->max_dispclk_vmid0p72 * 1000,
-+			dc->dcn_soc->max_dispclk_vmin0p65 * 1000,
-+			dc->dcn_soc->max_dppclk_vmax0p9 * 1000,
-+			dc->dcn_soc->max_dppclk_vnom0p8 * 1000,
-+			dc->dcn_soc->max_dppclk_vmid0p72 * 1000,
-+			dc->dcn_soc->max_dppclk_vmin0p65 * 1000,
-+			dc->dcn_soc->socclk * 1000,
-+			dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000,
-+			dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000,
-+			dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000,
-+			dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000,
-+			dc->dcn_soc->phyclkv_max0p9 * 1000,
-+			dc->dcn_soc->phyclkv_nom0p8 * 1000,
-+			dc->dcn_soc->phyclkv_mid0p72 * 1000,
-+			dc->dcn_soc->phyclkv_min0p65 * 1000,
-+			dc->dcn_soc->downspreading * 100,
-+			dc->dcn_soc->round_trip_ping_latency_cycles,
-+			dc->dcn_soc->urgent_out_of_order_return_per_channel,
-+			dc->dcn_soc->number_of_channels,
-+			dc->dcn_soc->vmm_page_size,
-+			dc->dcn_soc->dram_clock_change_latency * 1000,
-+			dc->dcn_soc->return_bus_width);
-+	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"rob_buffer_size_in_kbyte: %d\n"
-+			"det_buffer_size_in_kbyte: %d\n"
-+			"dpp_output_buffer_pixels: %d\n"
-+			"opp_output_buffer_lines: %d\n"
-+			"pixel_chunk_size_in_kbyte: %d\n"
-+			"pte_enable: %d\n"
-+			"pte_chunk_size: %d kbytes\n"
-+			"meta_chunk_size: %d kbytes\n"
-+			"writeback_chunk_size: %d kbytes\n"
-+			"odm_capability: %d\n"
-+			"dsc_capability: %d\n"
-+			"line_buffer_size: %d bits\n"
-+			"max_line_buffer_lines: %d\n"
-+			"is_line_buffer_bpp_fixed: %d\n"
-+			"line_buffer_fixed_bpp: %d\n"
-+			"writeback_luma_buffer_size: %d kbytes\n"
-+			"writeback_chroma_buffer_size: %d kbytes\n"
-+			"max_num_dpp: %d\n"
-+			"max_num_writeback: %d\n"
-+			"max_dchub_topscl_throughput: %d pixels/dppclk\n"
-+			"max_pscl_tolb_throughput: %d pixels/dppclk\n"
-+			"max_lb_tovscl_throughput: %d pixels/dppclk\n"
-+			"max_vscl_tohscl_throughput: %d pixels/dppclk\n"
-+			"max_hscl_ratio: %d\n"
-+			"max_vscl_ratio: %d\n"
-+			"max_hscl_taps: %d\n"
-+			"max_vscl_taps: %d\n"
-+			"pte_buffer_size_in_requests: %d\n"
-+			"dispclk_ramping_margin: %d %\n"
-+			"under_scan_factor: %d %\n"
-+			"max_inter_dcn_tile_repeaters: %d\n"
-+			"can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
-+			"bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"
-+			"dcfclk_cstate_latency: %d\n",
-+			dc->dcn_ip->rob_buffer_size_in_kbyte,
-+			dc->dcn_ip->det_buffer_size_in_kbyte,
-+			dc->dcn_ip->dpp_output_buffer_pixels,
-+			dc->dcn_ip->opp_output_buffer_lines,
-+			dc->dcn_ip->pixel_chunk_size_in_kbyte,
-+			dc->dcn_ip->pte_enable,
-+			dc->dcn_ip->pte_chunk_size,
-+			dc->dcn_ip->meta_chunk_size,
-+			dc->dcn_ip->writeback_chunk_size,
-+			dc->dcn_ip->odm_capability,
-+			dc->dcn_ip->dsc_capability,
-+			dc->dcn_ip->line_buffer_size,
-+			dc->dcn_ip->max_line_buffer_lines,
-+			dc->dcn_ip->is_line_buffer_bpp_fixed,
-+			dc->dcn_ip->line_buffer_fixed_bpp,
-+			dc->dcn_ip->writeback_luma_buffer_size,
-+			dc->dcn_ip->writeback_chroma_buffer_size,
-+			dc->dcn_ip->max_num_dpp,
-+			dc->dcn_ip->max_num_writeback,
-+			dc->dcn_ip->max_dchub_topscl_throughput,
-+			dc->dcn_ip->max_pscl_tolb_throughput,
-+			dc->dcn_ip->max_lb_tovscl_throughput,
-+			dc->dcn_ip->max_vscl_tohscl_throughput,
-+			dc->dcn_ip->max_hscl_ratio,
-+			dc->dcn_ip->max_vscl_ratio,
-+			dc->dcn_ip->max_hscl_taps,
-+			dc->dcn_ip->max_vscl_taps,
-+			dc->dcn_ip->pte_buffer_size_in_requests,
-+			dc->dcn_ip->dispclk_ramping_margin,
-+			dc->dcn_ip->under_scan_factor * 100,
-+			dc->dcn_ip->max_inter_dcn_tile_repeaters,
-+			dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,
-+			dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,
-+			dc->dcn_ip->dcfclk_cstate_latency);
-+	dc->dml.soc.vmin.socclk_mhz = dc->dcn_soc->socclk;
-+	dc->dml.soc.vmid.socclk_mhz = dc->dcn_soc->socclk;
-+	dc->dml.soc.vnom.socclk_mhz = dc->dcn_soc->socclk;
-+	dc->dml.soc.vmax.socclk_mhz = dc->dcn_soc->socclk;
-+
-+	dc->dml.soc.vmin.dcfclk_mhz = dc->dcn_soc->dcfclkv_min0p65;
-+	dc->dml.soc.vmid.dcfclk_mhz = dc->dcn_soc->dcfclkv_mid0p72;
-+	dc->dml.soc.vnom.dcfclk_mhz = dc->dcn_soc->dcfclkv_nom0p8;
-+	dc->dml.soc.vmax.dcfclk_mhz = dc->dcn_soc->dcfclkv_max0p9;
-+
-+	dc->dml.soc.vmin.dispclk_mhz = dc->dcn_soc->max_dispclk_vmin0p65;
-+	dc->dml.soc.vmid.dispclk_mhz = dc->dcn_soc->max_dispclk_vmid0p72;
-+	dc->dml.soc.vnom.dispclk_mhz = dc->dcn_soc->max_dispclk_vnom0p8;
-+	dc->dml.soc.vmax.dispclk_mhz = dc->dcn_soc->max_dispclk_vmax0p9;
-+
-+	dc->dml.soc.vmin.dppclk_mhz = dc->dcn_soc->max_dppclk_vmin0p65;
-+	dc->dml.soc.vmid.dppclk_mhz = dc->dcn_soc->max_dppclk_vmid0p72;
-+	dc->dml.soc.vnom.dppclk_mhz = dc->dcn_soc->max_dppclk_vnom0p8;
-+	dc->dml.soc.vmax.dppclk_mhz = dc->dcn_soc->max_dppclk_vmax0p9;
-+
-+	dc->dml.soc.vmin.phyclk_mhz = dc->dcn_soc->phyclkv_min0p65;
-+	dc->dml.soc.vmid.phyclk_mhz = dc->dcn_soc->phyclkv_mid0p72;
-+	dc->dml.soc.vnom.phyclk_mhz = dc->dcn_soc->phyclkv_nom0p8;
-+	dc->dml.soc.vmax.phyclk_mhz = dc->dcn_soc->phyclkv_max0p9;
-+
-+	dc->dml.soc.vmin.dram_bw_per_chan_gbps = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;
-+	dc->dml.soc.vmid.dram_bw_per_chan_gbps = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;
-+	dc->dml.soc.vnom.dram_bw_per_chan_gbps = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;
-+	dc->dml.soc.vmax.dram_bw_per_chan_gbps = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;
-+
-+	dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
-+	dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;
-+	dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency;
-+	dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency;
-+	dc->dml.soc.ideal_dram_bw_after_urgent_percent =
-+			dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
-+	dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size;
-+	dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading;
-+	dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =
-+			dc->dcn_soc->round_trip_ping_latency_cycles;
-+	dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =
-+			dc->dcn_soc->urgent_out_of_order_return_per_channel;
-+	dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels;
-+	dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size;
-+	dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency;
-+	dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width;
-+
-+	dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte;
-+	dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte;
-+	dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
-+	dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
-+	dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte;
-+	dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes;
-+	dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size;
-+	dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size;
-+	dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size;
-+	dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size;
-+	dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
-+	dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes;
-+	dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp;
-+	dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size;
-+	dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size;
-+	dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp;
-+	dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback;
-+	dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput;
-+	dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput;
-+	dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput;
-+	dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput;
-+	dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
-+	dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
-+	dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps;
-+	dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps;
-+	/*pte_buffer_size_in_requests missing in dml*/
-+	dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin;
-+	dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor;
-+	dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
-+	dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
-+		dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;
-+	dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
-+		dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
-+	dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
-+	kernel_fpu_end();
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/Makefile.0130~	2017-12-14 06:39:58.405903560 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/calcs/Makefile	2017-12-14 06:39:58.405903560 +0100
-@@ -0,0 +1,18 @@
-+#
-+# Makefile for the 'calcs' sub-component of DAL.
-+# It calculates Bandwidth and Watermarks values for HW programming
-+#
-+
-+CFLAGS_dcn_calcs.o := -mhard-float -msse -mpreferred-stack-boundary=4
-+CFLAGS_dcn_calc_auto.o := -mhard-float -msse -mpreferred-stack-boundary=4
-+CFLAGS_dcn_calc_math.o := -mhard-float -msse -mpreferred-stack-boundary=4 -Wno-tautological-compare
-+
-+BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
-+
-+ifdef CONFIG_DRM_AMD_DC_DCN1_0
-+BW_CALCS += dcn_calcs.o dcn_calc_math.o dcn_calc_auto.o
-+endif
-+
-+AMD_DAL_BW_CALCS = $(addprefix $(AMDDALPATH)/dc/calcs/,$(BW_CALCS))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_BW_CALCS)
---- linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc.c.0130~	2017-12-14 06:39:58.405903560 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc.c	2017-12-14 06:39:58.405903560 +0100
-@@ -0,0 +1,1601 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "dc.h"
-+
-+#include "core_status.h"
-+#include "core_types.h"
-+#include "hw_sequencer.h"
-+
-+#include "resource.h"
-+
-+#include "clock_source.h"
-+#include "dc_bios_types.h"
-+
-+#include "bios_parser_interface.h"
-+#include "include/irq_service_interface.h"
-+#include "transform.h"
-+#include "dpp.h"
-+#include "timing_generator.h"
-+#include "virtual/virtual_link_encoder.h"
-+
-+#include "link_hwss.h"
-+#include "link_encoder.h"
-+
-+#include "dc_link_ddc.h"
-+#include "dm_helpers.h"
-+#include "mem_input.h"
-+#include "hubp.h"
-+
-+
-+/*******************************************************************************
-+ * Private functions
-+ ******************************************************************************/
-+
-+static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
-+{
-+	if (new > *original)
-+		*original = new;
-+}
-+
-+static void destroy_links(struct dc *dc)
-+{
-+	uint32_t i;
-+
-+	for (i = 0; i < dc->link_count; i++) {
-+		if (NULL != dc->links[i])
-+			link_destroy(&dc->links[i]);
-+	}
-+}
-+
-+static bool create_links(
-+		struct dc *dc,
-+		uint32_t num_virtual_links)
-+{
-+	int i;
-+	int connectors_num;
-+	struct dc_bios *bios = dc->ctx->dc_bios;
-+
-+	dc->link_count = 0;
-+
-+	connectors_num = bios->funcs->get_connectors_number(bios);
-+
-+	if (connectors_num > ENUM_ID_COUNT) {
-+		dm_error(
-+			"DC: Number of connectors %d exceeds maximum of %d!\n",
-+			connectors_num,
-+			ENUM_ID_COUNT);
-+		return false;
-+	}
-+
-+	if (connectors_num == 0 && num_virtual_links == 0) {
-+		dm_error("DC: Number of connectors is zero!\n");
-+	}
-+
-+	dm_output_to_console(
-+		"DC: %s: connectors_num: physical:%d, virtual:%d\n",
-+		__func__,
-+		connectors_num,
-+		num_virtual_links);
-+
-+	for (i = 0; i < connectors_num; i++) {
-+		struct link_init_data link_init_params = {0};
-+		struct dc_link *link;
-+
-+		link_init_params.ctx = dc->ctx;
-+		/* next BIOS object table connector */
-+		link_init_params.connector_index = i;
-+		link_init_params.link_index = dc->link_count;
-+		link_init_params.dc = dc;
-+		link = link_create(&link_init_params);
-+
-+		if (link) {
-+			dc->links[dc->link_count] = link;
-+			link->dc = dc;
-+			++dc->link_count;
-+		}
-+	}
-+
-+	for (i = 0; i < num_virtual_links; i++) {
-+		struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
-+		struct encoder_init_data enc_init = {0};
-+
-+		if (link == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			goto failed_alloc;
-+		}
-+
-+		link->ctx = dc->ctx;
-+		link->dc = dc;
-+		link->connector_signal = SIGNAL_TYPE_VIRTUAL;
-+		link->link_id.type = OBJECT_TYPE_CONNECTOR;
-+		link->link_id.id = CONNECTOR_ID_VIRTUAL;
-+		link->link_id.enum_id = ENUM_ID_1;
-+		link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
-+		link->link_status.dpcd_caps = &link->dpcd_caps;
-+
-+		enc_init.ctx = dc->ctx;
-+		enc_init.channel = CHANNEL_ID_UNKNOWN;
-+		enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
-+		enc_init.transmitter = TRANSMITTER_UNKNOWN;
-+		enc_init.connector = link->link_id;
-+		enc_init.encoder.type = OBJECT_TYPE_ENCODER;
-+		enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
-+		enc_init.encoder.enum_id = ENUM_ID_1;
-+		virtual_link_encoder_construct(link->link_enc, &enc_init);
-+
-+		link->link_index = dc->link_count;
-+		dc->links[dc->link_count] = link;
-+		dc->link_count++;
-+	}
-+
-+	return true;
-+
-+failed_alloc:
-+	return false;
-+}
-+
-+bool dc_stream_adjust_vmin_vmax(struct dc *dc,
-+		struct dc_stream_state **streams, int num_streams,
-+		int vmin, int vmax)
-+{
-+	/* TODO: Support multiple streams */
-+	struct dc_stream_state *stream = streams[0];
-+	int i = 0;
-+	bool ret = false;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
-+
-+		if (pipe->stream == stream && pipe->stream_res.stream_enc) {
-+			dc->hwss.set_drr(&pipe, 1, vmin, vmax);
-+
-+			/* build and update the info frame */
-+			resource_build_info_frame(pipe);
-+			dc->hwss.update_info_frame(pipe);
-+
-+			ret = true;
-+		}
-+	}
-+	return ret;
-+}
-+
-+bool dc_stream_get_crtc_position(struct dc *dc,
-+		struct dc_stream_state **streams, int num_streams,
-+		unsigned int *v_pos, unsigned int *nom_v_pos)
-+{
-+	/* TODO: Support multiple streams */
-+	struct dc_stream_state *stream = streams[0];
-+	int i = 0;
-+	bool ret = false;
-+	struct crtc_position position;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe =
-+				&dc->current_state->res_ctx.pipe_ctx[i];
-+
-+		if (pipe->stream == stream && pipe->stream_res.stream_enc) {
-+			dc->hwss.get_position(&pipe, 1, &position);
-+
-+			*v_pos = position.vertical_count;
-+			*nom_v_pos = position.nominal_vcount;
-+			ret = true;
-+		}
-+	}
-+	return ret;
-+}
-+
-+void dc_stream_set_static_screen_events(struct dc *dc,
-+		struct dc_stream_state **streams,
-+		int num_streams,
-+		const struct dc_static_screen_events *events)
-+{
-+	int i = 0;
-+	int j = 0;
-+	struct pipe_ctx *pipes_affected[MAX_PIPES];
-+	int num_pipes_affected = 0;
-+
-+	for (i = 0; i < num_streams; i++) {
-+		struct dc_stream_state *stream = streams[i];
-+
-+		for (j = 0; j < MAX_PIPES; j++) {
-+			if (dc->current_state->res_ctx.pipe_ctx[j].stream
-+					== stream) {
-+				pipes_affected[num_pipes_affected++] =
-+						&dc->current_state->res_ctx.pipe_ctx[j];
-+			}
-+		}
-+	}
-+
-+	dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
-+}
-+
-+static void set_drive_settings(struct dc *dc,
-+		struct link_training_settings *lt_settings,
-+		const struct dc_link *link)
-+{
-+
-+	int i;
-+
-+	for (i = 0; i < dc->link_count; i++) {
-+		if (dc->links[i] == link)
-+			break;
-+	}
-+
-+	if (i >= dc->link_count)
-+		ASSERT_CRITICAL(false);
-+
-+	dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
-+}
-+
-+static void perform_link_training(struct dc *dc,
-+		struct dc_link_settings *link_setting,
-+		bool skip_video_pattern)
-+{
-+	int i;
-+
-+	for (i = 0; i < dc->link_count; i++)
-+		dc_link_dp_perform_link_training(
-+			dc->links[i],
-+			link_setting,
-+			skip_video_pattern);
-+}
-+
-+static void set_preferred_link_settings(struct dc *dc,
-+		struct dc_link_settings *link_setting,
-+		struct dc_link *link)
-+{
-+	link->preferred_link_setting = *link_setting;
-+	dp_retrain_link_dp_test(link, link_setting, false);
-+}
-+
-+static void enable_hpd(const struct dc_link *link)
-+{
-+	dc_link_dp_enable_hpd(link);
-+}
-+
-+static void disable_hpd(const struct dc_link *link)
-+{
-+	dc_link_dp_disable_hpd(link);
-+}
-+
-+
-+static void set_test_pattern(
-+		struct dc_link *link,
-+		enum dp_test_pattern test_pattern,
-+		const struct link_training_settings *p_link_settings,
-+		const unsigned char *p_custom_pattern,
-+		unsigned int cust_pattern_size)
-+{
-+	if (link != NULL)
-+		dc_link_dp_set_test_pattern(
-+			link,
-+			test_pattern,
-+			p_link_settings,
-+			p_custom_pattern,
-+			cust_pattern_size);
-+}
-+
-+static void allocate_dc_stream_funcs(struct dc  *dc)
-+{
-+	dc->link_funcs.set_drive_settings =
-+			set_drive_settings;
-+
-+	dc->link_funcs.perform_link_training =
-+			perform_link_training;
-+
-+	dc->link_funcs.set_preferred_link_settings =
-+			set_preferred_link_settings;
-+
-+	dc->link_funcs.enable_hpd =
-+			enable_hpd;
-+
-+	dc->link_funcs.disable_hpd =
-+			disable_hpd;
-+
-+	dc->link_funcs.set_test_pattern =
-+			set_test_pattern;
-+}
-+
-+static void destruct(struct dc *dc)
-+{
-+	dc_release_state(dc->current_state);
-+	dc->current_state = NULL;
-+
-+	destroy_links(dc);
-+
-+	dc_destroy_resource_pool(dc);
-+
-+	if (dc->ctx->gpio_service)
-+		dal_gpio_service_destroy(&dc->ctx->gpio_service);
-+
-+	if (dc->ctx->i2caux)
-+		dal_i2caux_destroy(&dc->ctx->i2caux);
-+
-+	if (dc->ctx->created_bios)
-+		dal_bios_parser_destroy(&dc->ctx->dc_bios);
-+
-+	if (dc->ctx->logger)
-+		dal_logger_destroy(&dc->ctx->logger);
-+
-+	kfree(dc->ctx);
-+	dc->ctx = NULL;
-+
-+	kfree(dc->bw_vbios);
-+	dc->bw_vbios = NULL;
-+
-+	kfree(dc->bw_dceip);
-+	dc->bw_dceip = NULL;
-+
-+#ifdef CONFIG_DRM_AMD_DC_DCN1_0
-+	kfree(dc->dcn_soc);
-+	dc->dcn_soc = NULL;
-+
-+	kfree(dc->dcn_ip);
-+	dc->dcn_ip = NULL;
-+
-+#endif
-+}
-+
-+static bool construct(struct dc *dc,
-+		const struct dc_init_data *init_params)
-+{
-+	struct dal_logger *logger;
-+	struct dc_context *dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
-+	struct bw_calcs_dceip *dc_dceip = kzalloc(sizeof(*dc_dceip),
-+						  GFP_KERNEL);
-+	struct bw_calcs_vbios *dc_vbios = kzalloc(sizeof(*dc_vbios),
-+						  GFP_KERNEL);
-+#ifdef CONFIG_DRM_AMD_DC_DCN1_0
-+	struct dcn_soc_bounding_box *dcn_soc = kzalloc(sizeof(*dcn_soc),
-+						       GFP_KERNEL);
-+	struct dcn_ip_params *dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
-+#endif
-+
-+	enum dce_version dc_version = DCE_VERSION_UNKNOWN;
-+
-+	if (!dc_dceip) {
-+		dm_error("%s: failed to create dceip\n", __func__);
-+		goto fail;
-+	}
-+
-+	dc->bw_dceip = dc_dceip;
-+
-+	if (!dc_vbios) {
-+		dm_error("%s: failed to create vbios\n", __func__);
-+		goto fail;
-+	}
-+
-+	dc->bw_vbios = dc_vbios;
-+#ifdef CONFIG_DRM_AMD_DC_DCN1_0
-+	if (!dcn_soc) {
-+		dm_error("%s: failed to create dcn_soc\n", __func__);
-+		goto fail;
-+	}
-+
-+	dc->dcn_soc = dcn_soc;
-+
-+	if (!dcn_ip) {
-+		dm_error("%s: failed to create dcn_ip\n", __func__);
-+		goto fail;
-+	}
-+
-+	dc->dcn_ip = dcn_ip;
-+#endif
-+
-+	if (!dc_ctx) {
-+		dm_error("%s: failed to create ctx\n", __func__);
-+		goto fail;
-+	}
-+
-+	dc->current_state = dc_create_state();
-+
-+	if (!dc->current_state) {
-+		dm_error("%s: failed to create validate ctx\n", __func__);
-+		goto fail;
-+	}
-+
-+	dc_ctx->cgs_device = init_params->cgs_device;
-+	dc_ctx->driver_context = init_params->driver;
-+	dc_ctx->dc = dc;
-+	dc_ctx->asic_id = init_params->asic_id;
-+
-+	/* Create logger */
-+	logger = dal_logger_create(dc_ctx, init_params->log_mask);
-+
-+	if (!logger) {
-+		/* can *not* call logger. call base driver 'print error' */
-+		dm_error("%s: failed to create Logger!\n", __func__);
-+		goto fail;
-+	}
-+	dc_ctx->logger = logger;
-+	dc->ctx = dc_ctx;
-+	dc->ctx->dce_environment = init_params->dce_environment;
-+
-+	dc_version = resource_parse_asic_id(init_params->asic_id);
-+	dc->ctx->dce_version = dc_version;
-+
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+	dc->ctx->fbc_gpu_addr = init_params->fbc_gpu_addr;
-+#endif
-+	/* Resource should construct all asic specific resources.
-+	 * This should be the only place where we need to parse the asic id
-+	 */
-+	if (init_params->vbios_override)
-+		dc_ctx->dc_bios = init_params->vbios_override;
-+	else {
-+		/* Create BIOS parser */
-+		struct bp_init_data bp_init_data;
-+
-+		bp_init_data.ctx = dc_ctx;
-+		bp_init_data.bios = init_params->asic_id.atombios_base_address;
-+
-+		dc_ctx->dc_bios = dal_bios_parser_create(
-+				&bp_init_data, dc_version);
-+
-+		if (!dc_ctx->dc_bios) {
-+			ASSERT_CRITICAL(false);
-+			goto fail;
-+		}
-+
-+		dc_ctx->created_bios = true;
-+		}
-+
-+	/* Create I2C AUX */
-+	dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
-+
-+	if (!dc_ctx->i2caux) {
-+		ASSERT_CRITICAL(false);
-+		goto fail;
-+	}
-+
-+	/* Create GPIO service */
-+	dc_ctx->gpio_service = dal_gpio_service_create(
-+			dc_version,
-+			dc_ctx->dce_environment,
-+			dc_ctx);
-+
-+	if (!dc_ctx->gpio_service) {
-+		ASSERT_CRITICAL(false);
-+		goto fail;
-+	}
-+
-+	dc->res_pool = dc_create_resource_pool(
-+			dc,
-+			init_params->num_virtual_links,
-+			dc_version,
-+			init_params->asic_id);
-+	if (!dc->res_pool)
-+		goto fail;
-+
-+	dc_resource_state_construct(dc, dc->current_state);
-+
-+	if (!create_links(dc, init_params->num_virtual_links))
-+		goto fail;
-+
-+	allocate_dc_stream_funcs(dc);
-+
-+	return true;
-+
-+fail:
-+
-+	destruct(dc);
-+	return false;
-+}
-+
-+static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
-+{
-+	int i, j;
-+	struct dc_state *dangling_context = dc_create_state();
-+	struct dc_state *current_ctx;
-+
-+	if (dangling_context == NULL)
-+		return;
-+
-+	dc_resource_state_copy_construct(dc->current_state, dangling_context);
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct dc_stream_state *old_stream =
-+				dc->current_state->res_ctx.pipe_ctx[i].stream;
-+		bool should_disable = true;
-+
-+		for (j = 0; j < context->stream_count; j++) {
-+			if (old_stream == context->streams[j]) {
-+				should_disable = false;
-+				break;
-+			}
-+		}
-+		if (should_disable && old_stream) {
-+			dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
-+			dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
-+		}
-+	}
-+
-+	current_ctx = dc->current_state;
-+	dc->current_state = dangling_context;
-+	dc_release_state(current_ctx);
-+}
-+
-+/*******************************************************************************
-+ * Public functions
-+ ******************************************************************************/
-+
-+struct dc *dc_create(const struct dc_init_data *init_params)
-+ {
-+	struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
-+	unsigned int full_pipe_count;
-+
-+	if (NULL == dc)
-+		goto alloc_fail;
-+
-+	if (false == construct(dc, init_params))
-+		goto construct_fail;
-+
-+	/*TODO: separate HW and SW initialization*/
-+	dc->hwss.init_hw(dc);
-+
-+	full_pipe_count = dc->res_pool->pipe_count;
-+	if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
-+		full_pipe_count--;
-+	dc->caps.max_streams = min(
-+			full_pipe_count,
-+			dc->res_pool->stream_enc_count);
-+
-+	dc->caps.max_links = dc->link_count;
-+	dc->caps.max_audios = dc->res_pool->audio_count;
-+	dc->caps.linear_pitch_alignment = 64;
-+
-+	dc->config = init_params->flags;
-+
-+	dm_logger_write(dc->ctx->logger, LOG_DC,
-+			"Display Core initialized\n");
-+
-+
-+	/* TODO: missing feature to be enabled */
-+	dc->debug.disable_dfs_bypass = true;
-+
-+	return dc;
-+
-+construct_fail:
-+	kfree(dc);
-+
-+alloc_fail:
-+	return NULL;
-+}
-+
-+void dc_destroy(struct dc **dc)
-+{
-+	destruct(*dc);
-+	kfree(*dc);
-+	*dc = NULL;
-+}
-+
-+static void enable_timing_multisync(
-+		struct dc *dc,
-+		struct dc_state *ctx)
-+{
-+	int i = 0, multisync_count = 0;
-+	int pipe_count = dc->res_pool->pipe_count;
-+	struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
-+
-+	for (i = 0; i < pipe_count; i++) {
-+		if (!ctx->res_ctx.pipe_ctx[i].stream ||
-+				!ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
-+			continue;
-+		multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
-+		multisync_count++;
-+	}
-+
-+	if (multisync_count > 1) {
-+		dc->hwss.enable_per_frame_crtc_position_reset(
-+			dc, multisync_count, multisync_pipes);
-+	}
-+}
-+
-+static void program_timing_sync(
-+		struct dc *dc,
-+		struct dc_state *ctx)
-+{
-+	int i, j;
-+	int group_index = 0;
-+	int pipe_count = dc->res_pool->pipe_count;
-+	struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
-+
-+	for (i = 0; i < pipe_count; i++) {
-+		if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
-+			continue;
-+
-+		unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
-+	}
-+
-+	for (i = 0; i < pipe_count; i++) {
-+		int group_size = 1;
-+		struct pipe_ctx *pipe_set[MAX_PIPES];
-+
-+		if (!unsynced_pipes[i])
-+			continue;
-+
-+		pipe_set[0] = unsynced_pipes[i];
-+		unsynced_pipes[i] = NULL;
-+
-+		/* Add tg to the set, search rest of the tg's for ones with
-+		 * same timing, add all tgs with same timing to the group
-+		 */
-+		for (j = i + 1; j < pipe_count; j++) {
-+			if (!unsynced_pipes[j])
-+				continue;
-+
-+			if (resource_are_streams_timing_synchronizable(
-+					unsynced_pipes[j]->stream,
-+					pipe_set[0]->stream)) {
-+				pipe_set[group_size] = unsynced_pipes[j];
-+				unsynced_pipes[j] = NULL;
-+				group_size++;
-+			}
-+		}
-+
-+		/* set first unblanked pipe as master */
-+		for (j = 0; j < group_size; j++) {
-+			struct pipe_ctx *temp;
-+
-+			if (!pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) {
-+				if (j == 0)
-+					break;
-+
-+				temp = pipe_set[0];
-+				pipe_set[0] = pipe_set[j];
-+				pipe_set[j] = temp;
-+				break;
-+			}
-+		}
-+
-+		/* remove any other unblanked pipes as they have already been synced */
-+		for (j = j + 1; j < group_size; j++) {
-+			if (!pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) {
-+				group_size--;
-+				pipe_set[j] = pipe_set[group_size];
-+				j--;
-+			}
-+		}
-+
-+		if (group_size > 1) {
-+			dc->hwss.enable_timing_synchronization(
-+				dc, group_index, group_size, pipe_set);
-+			group_index++;
-+		}
-+	}
-+}
-+
-+static bool context_changed(
-+		struct dc *dc,
-+		struct dc_state *context)
-+{
-+	uint8_t i;
-+
-+	if (context->stream_count != dc->current_state->stream_count)
-+		return true;
-+
-+	for (i = 0; i < dc->current_state->stream_count; i++) {
-+		if (dc->current_state->streams[i] != context->streams[i])
-+			return true;
-+	}
-+
-+	return false;
-+}
-+
-+bool dc_enable_stereo(
-+	struct dc *dc,
-+	struct dc_state *context,
-+	struct dc_stream_state *streams[],
-+	uint8_t stream_count)
-+{
-+	bool ret = true;
-+	int i, j;
-+	struct pipe_ctx *pipe;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (context != NULL)
-+			pipe = &context->res_ctx.pipe_ctx[i];
-+		else
-+			pipe = &dc->current_state->res_ctx.pipe_ctx[i];
-+		for (j = 0 ; pipe && j < stream_count; j++)  {
-+			if (streams[j] && streams[j] == pipe->stream &&
-+				dc->hwss.setup_stereo)
-+				dc->hwss.setup_stereo(pipe, dc);
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+
-+/*
-+ * Applies given context to HW and copy it into current context.
-+ * It's up to the user to release the src context afterwards.
-+ */
-+static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
-+{
-+	struct dc_bios *dcb = dc->ctx->dc_bios;
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+	struct pipe_ctx *pipe;
-+	int i, k, l;
-+	struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
-+
-+	disable_dangling_plane(dc, context);
-+
-+	for (i = 0; i < context->stream_count; i++)
-+		dc_streams[i] =  context->streams[i];
-+
-+	if (!dcb->funcs->is_accelerated_mode(dcb))
-+		dc->hwss.enable_accelerated_mode(dc);
-+
-+	/* re-program planes for existing stream, in case we need to
-+	 * free up plane resource for later use
-+	 */
-+	for (i = 0; i < dc->current_state->stream_count; i++) {
-+		dc->hwss.apply_ctx_for_surface(
-+			dc, dc->current_state->streams[i],
-+			dc->current_state->stream_status[i].plane_count,
-+			context); /* use new pipe config in new context */
-+	}
-+
-+	/* Program hardware */
-+	dc->hwss.ready_shared_resources(dc, context);
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		pipe = &context->res_ctx.pipe_ctx[i];
-+		dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
-+	}
-+
-+	result = dc->hwss.apply_ctx_to_hw(dc, context);
-+
-+	if (result != DC_OK)
-+		return result;
-+
-+	if (context->stream_count > 1) {
-+		enable_timing_multisync(dc, context);
-+		program_timing_sync(dc, context);
-+	}
-+
-+	/* Program all planes within new context*/
-+	for (i = 0; i < context->stream_count; i++) {
-+		const struct dc_sink *sink = context->streams[i]->sink;
-+
-+		dc->hwss.apply_ctx_for_surface(
-+				dc, context->streams[i],
-+				context->stream_status[i].plane_count,
-+				context);
-+
-+		/*
-+		 * enable stereo
-+		 * TODO rework dc_enable_stereo call to work with validation sets?
-+		 */
-+		for (k = 0; k < MAX_PIPES; k++) {
-+			pipe = &context->res_ctx.pipe_ctx[k];
-+
-+			for (l = 0 ; pipe && l < context->stream_count; l++)  {
-+				if (context->streams[l] &&
-+					context->streams[l] == pipe->stream &&
-+					dc->hwss.setup_stereo)
-+					dc->hwss.setup_stereo(pipe, dc);
-+			}
-+		}
-+
-+		CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
-+				context->streams[i]->timing.h_addressable,
-+				context->streams[i]->timing.v_addressable,
-+				context->streams[i]->timing.h_total,
-+				context->streams[i]->timing.v_total,
-+				context->streams[i]->timing.pix_clk_khz);
-+	}
-+
-+	dc_enable_stereo(dc, context, dc_streams, context->stream_count);
-+
-+	dc_release_state(dc->current_state);
-+
-+	dc->current_state = context;
-+
-+	dc_retain_state(dc->current_state);
-+
-+	dc->hwss.optimize_shared_resources(dc);
-+
-+	return result;
-+}
-+
-+bool dc_commit_state(struct dc *dc, struct dc_state *context)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+	int i;
-+
-+	if (false == context_changed(dc, context))
-+		return DC_OK;
-+
-+	dm_logger_write(dc->ctx->logger, LOG_DC, "%s: %d streams\n",
-+				__func__, context->stream_count);
-+
-+	for (i = 0; i < context->stream_count; i++) {
-+		struct dc_stream_state *stream = context->streams[i];
-+
-+		dc_stream_log(stream,
-+				dc->ctx->logger,
-+				LOG_DC);
-+	}
-+
-+	result = dc_commit_state_no_check(dc, context);
-+
-+	return (result == DC_OK);
-+}
-+
-+bool dc_post_update_surfaces_to_stream(struct dc *dc)
-+{
-+	int i;
-+	struct dc_state *context = dc->current_state;
-+
-+	post_surface_trace(dc);
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++)
-+		if (context->res_ctx.pipe_ctx[i].stream == NULL ||
-+		    context->res_ctx.pipe_ctx[i].plane_state == NULL) {
-+			context->res_ctx.pipe_ctx[i].pipe_idx = i;
-+			dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
-+		}
-+
-+	/* 3rd param should be true, temp w/a for RV*/
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	dc->hwss.set_bandwidth(dc, context, dc->ctx->dce_version < DCN_VERSION_1_0);
-+#else
-+	dc->hwss.set_bandwidth(dc, context, true);
-+#endif
-+	return true;
-+}
-+
-+/*
-+ * TODO this whole function needs to go
-+ *
-+ * dc_surface_update is needlessly complex. See if we can just replace this
-+ * with a dc_plane_state and follow the atomic model a bit more closely here.
-+ */
-+bool dc_commit_planes_to_stream(
-+		struct dc *dc,
-+		struct dc_plane_state **plane_states,
-+		uint8_t new_plane_count,
-+		struct dc_stream_state *dc_stream,
-+		struct dc_state *state)
-+{
-+	/* no need to dynamically allocate this. it's pretty small */
-+	struct dc_surface_update updates[MAX_SURFACES];
-+	struct dc_flip_addrs *flip_addr;
-+	struct dc_plane_info *plane_info;
-+	struct dc_scaling_info *scaling_info;
-+	int i;
-+	struct dc_stream_update *stream_update =
-+			kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
-+
-+	if (!stream_update) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
-+			    GFP_KERNEL);
-+	plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
-+			     GFP_KERNEL);
-+	scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
-+			       GFP_KERNEL);
-+
-+	if (!flip_addr || !plane_info || !scaling_info) {
-+		kfree(flip_addr);
-+		kfree(plane_info);
-+		kfree(scaling_info);
-+		kfree(stream_update);
-+		return false;
-+	}
-+
-+	memset(updates, 0, sizeof(updates));
-+
-+	stream_update->src = dc_stream->src;
-+	stream_update->dst = dc_stream->dst;
-+	stream_update->out_transfer_func = dc_stream->out_transfer_func;
-+
-+	for (i = 0; i < new_plane_count; i++) {
-+		updates[i].surface = plane_states[i];
-+		updates[i].gamma =
-+			(struct dc_gamma *)plane_states[i]->gamma_correction;
-+		updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
-+		flip_addr[i].address = plane_states[i]->address;
-+		flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
-+		plane_info[i].color_space = plane_states[i]->color_space;
-+		plane_info[i].input_tf = plane_states[i]->input_tf;
-+		plane_info[i].format = plane_states[i]->format;
-+		plane_info[i].plane_size = plane_states[i]->plane_size;
-+		plane_info[i].rotation = plane_states[i]->rotation;
-+		plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
-+		plane_info[i].stereo_format = plane_states[i]->stereo_format;
-+		plane_info[i].tiling_info = plane_states[i]->tiling_info;
-+		plane_info[i].visible = plane_states[i]->visible;
-+		plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
-+		plane_info[i].dcc = plane_states[i]->dcc;
-+		scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
-+		scaling_info[i].src_rect = plane_states[i]->src_rect;
-+		scaling_info[i].dst_rect = plane_states[i]->dst_rect;
-+		scaling_info[i].clip_rect = plane_states[i]->clip_rect;
-+
-+		updates[i].flip_addr = &flip_addr[i];
-+		updates[i].plane_info = &plane_info[i];
-+		updates[i].scaling_info = &scaling_info[i];
-+	}
-+
-+	dc_commit_updates_for_stream(
-+			dc,
-+			updates,
-+			new_plane_count,
-+			dc_stream, stream_update, plane_states, state);
-+
-+	kfree(flip_addr);
-+	kfree(plane_info);
-+	kfree(scaling_info);
-+	kfree(stream_update);
-+	return true;
-+}
-+
-+struct dc_state *dc_create_state(void)
-+{
-+	struct dc_state *context = kzalloc(sizeof(struct dc_state),
-+					   GFP_KERNEL);
-+
-+	if (!context)
-+		return NULL;
-+
-+	kref_init(&context->refcount);
-+	return context;
-+}
-+
-+void dc_retain_state(struct dc_state *context)
-+{
-+	kref_get(&context->refcount);
-+}
-+
-+static void dc_state_free(struct kref *kref)
-+{
-+	struct dc_state *context = container_of(kref, struct dc_state, refcount);
-+	dc_resource_state_destruct(context);
-+	kfree(context);
-+}
-+
-+void dc_release_state(struct dc_state *context)
-+{
-+	kref_put(&context->refcount, dc_state_free);
-+}
-+
-+static bool is_surface_in_context(
-+		const struct dc_state *context,
-+		const struct dc_plane_state *plane_state)
-+{
-+	int j;
-+
-+	for (j = 0; j < MAX_PIPES; j++) {
-+		const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
-+
-+		if (plane_state == pipe_ctx->plane_state) {
-+			return true;
-+		}
-+	}
-+
-+	return false;
-+}
-+
-+static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
-+{
-+	switch (format) {
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
-+		return 12;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
-+	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
-+		return 16;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+		return 32;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+		return 64;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return -1;
-+	}
-+}
-+
-+static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
-+{
-+	union surface_update_flags *update_flags = &u->surface->update_flags;
-+
-+	if (!u->plane_info)
-+		return UPDATE_TYPE_FAST;
-+
-+	if (u->plane_info->color_space != u->surface->color_space)
-+		update_flags->bits.color_space_change = 1;
-+
-+	if (u->plane_info->input_tf != u->surface->input_tf)
-+		update_flags->bits.input_tf_change = 1;
-+
-+	if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror)
-+		update_flags->bits.horizontal_mirror_change = 1;
-+
-+	if (u->plane_info->rotation != u->surface->rotation)
-+		update_flags->bits.rotation_change = 1;
-+
-+	if (u->plane_info->stereo_format != u->surface->stereo_format)
-+		update_flags->bits.stereo_format_change = 1;
-+
-+	if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha)
-+		update_flags->bits.per_pixel_alpha_change = 1;
-+
-+	if (pixel_format_to_bpp(u->plane_info->format) !=
-+			pixel_format_to_bpp(u->surface->format))
-+		/* different bytes per element will require full bandwidth
-+		 * and DML calculation
-+		 */
-+		update_flags->bits.bpp_change = 1;
-+
-+	if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
-+			sizeof(union dc_tiling_info)) != 0) {
-+		update_flags->bits.swizzle_change = 1;
-+		/* todo: below are HW dependent, we should add a hook to
-+		 * DCE/N resource and validated there.
-+		 */
-+		if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR)
-+			/* swizzled mode requires RQ to be setup properly,
-+			 * thus need to run DML to calculate RQ settings
-+			 */
-+			update_flags->bits.bandwidth_change = 1;
-+	}
-+
-+	if (update_flags->bits.rotation_change
-+			|| update_flags->bits.stereo_format_change
-+			|| update_flags->bits.bpp_change
-+			|| update_flags->bits.bandwidth_change)
-+		return UPDATE_TYPE_FULL;
-+
-+	return UPDATE_TYPE_MED;
-+}
-+
-+static enum surface_update_type get_scaling_info_update_type(
-+		const struct dc_surface_update *u)
-+{
-+	union surface_update_flags *update_flags = &u->surface->update_flags;
-+
-+	if (!u->scaling_info)
-+		return UPDATE_TYPE_FAST;
-+
-+	if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
-+			|| u->scaling_info->clip_rect.height != u->surface->clip_rect.height
-+			|| u->scaling_info->dst_rect.width != u->surface->dst_rect.width
-+			|| u->scaling_info->dst_rect.height != u->surface->dst_rect.height) {
-+		update_flags->bits.scaling_change = 1;
-+
-+		if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
-+			|| u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
-+				&& (u->scaling_info->dst_rect.width < u->surface->src_rect.width
-+					|| u->scaling_info->dst_rect.height < u->surface->src_rect.height))
-+			/* Making dst rect smaller requires a bandwidth change */
-+			update_flags->bits.bandwidth_change = 1;
-+	}
-+
-+	if (u->scaling_info->src_rect.width != u->surface->src_rect.width
-+		|| u->scaling_info->src_rect.height != u->surface->src_rect.height) {
-+
-+		update_flags->bits.scaling_change = 1;
-+		if (u->scaling_info->src_rect.width > u->surface->src_rect.width
-+				&& u->scaling_info->src_rect.height > u->surface->src_rect.height)
-+			/* Making src rect bigger requires a bandwidth change */
-+			update_flags->bits.clock_change = 1;
-+	}
-+
-+	if (u->scaling_info->src_rect.x != u->surface->src_rect.x
-+			|| u->scaling_info->src_rect.y != u->surface->src_rect.y
-+			|| u->scaling_info->clip_rect.x != u->surface->clip_rect.x
-+			|| u->scaling_info->clip_rect.y != u->surface->clip_rect.y
-+			|| u->scaling_info->dst_rect.x != u->surface->dst_rect.x
-+			|| u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
-+		update_flags->bits.position_change = 1;
-+
-+	if (update_flags->bits.clock_change
-+			|| update_flags->bits.bandwidth_change)
-+		return UPDATE_TYPE_FULL;
-+
-+	if (update_flags->bits.scaling_change
-+			|| update_flags->bits.position_change)
-+		return UPDATE_TYPE_MED;
-+
-+	return UPDATE_TYPE_FAST;
-+}
-+
-+static enum surface_update_type det_surface_update(const struct dc *dc,
-+		const struct dc_surface_update *u)
-+{
-+	const struct dc_state *context = dc->current_state;
-+	enum surface_update_type type;
-+	enum surface_update_type overall_type = UPDATE_TYPE_FAST;
-+	union surface_update_flags *update_flags = &u->surface->update_flags;
-+
-+	update_flags->raw = 0; // Reset all flags
-+
-+	if (!is_surface_in_context(context, u->surface)) {
-+		update_flags->bits.new_plane = 1;
-+		return UPDATE_TYPE_FULL;
-+	}
-+
-+	type = get_plane_info_update_type(u);
-+	elevate_update_type(&overall_type, type);
-+
-+	type = get_scaling_info_update_type(u);
-+	elevate_update_type(&overall_type, type);
-+
-+	if (u->in_transfer_func)
-+		update_flags->bits.in_transfer_func = 1;
-+
-+	if (u->input_csc_color_matrix)
-+		update_flags->bits.input_csc_change = 1;
-+
-+	if (update_flags->bits.in_transfer_func
-+			|| update_flags->bits.input_csc_change) {
-+		type = UPDATE_TYPE_MED;
-+		elevate_update_type(&overall_type, type);
-+	}
-+
-+	return overall_type;
-+}
-+
-+static enum surface_update_type check_update_surfaces_for_stream(
-+		struct dc *dc,
-+		struct dc_surface_update *updates,
-+		int surface_count,
-+		struct dc_stream_update *stream_update,
-+		const struct dc_stream_status *stream_status)
-+{
-+	int i;
-+	enum surface_update_type overall_type = UPDATE_TYPE_FAST;
-+
-+	if (stream_status == NULL || stream_status->plane_count != surface_count)
-+		return UPDATE_TYPE_FULL;
-+
-+	if (stream_update)
-+		return UPDATE_TYPE_FULL;
-+
-+	for (i = 0 ; i < surface_count; i++) {
-+		enum surface_update_type type =
-+				det_surface_update(dc, &updates[i]);
-+
-+		if (type == UPDATE_TYPE_FULL)
-+			return type;
-+
-+		elevate_update_type(&overall_type, type);
-+	}
-+
-+	return overall_type;
-+}
-+
-+enum surface_update_type dc_check_update_surfaces_for_stream(
-+		struct dc *dc,
-+		struct dc_surface_update *updates,
-+		int surface_count,
-+		struct dc_stream_update *stream_update,
-+		const struct dc_stream_status *stream_status)
-+{
-+	int i;
-+	enum surface_update_type type;
-+
-+	for (i = 0; i < surface_count; i++)
-+		updates[i].surface->update_flags.raw = 0;
-+
-+	type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
-+	if (type == UPDATE_TYPE_FULL)
-+		for (i = 0; i < surface_count; i++)
-+			updates[i].surface->update_flags.bits.full_update = 1;
-+
-+	return type;
-+}
-+
-+static struct dc_stream_status *stream_get_status(
-+	struct dc_state *ctx,
-+	struct dc_stream_state *stream)
-+{
-+	uint8_t i;
-+
-+	for (i = 0; i < ctx->stream_count; i++) {
-+		if (stream == ctx->streams[i]) {
-+			return &ctx->stream_status[i];
-+		}
-+	}
-+
-+	return NULL;
-+}
-+
-+static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
-+
-+
-+static void commit_planes_for_stream(struct dc *dc,
-+		struct dc_surface_update *srf_updates,
-+		int surface_count,
-+		struct dc_stream_state *stream,
-+		struct dc_stream_update *stream_update,
-+		enum surface_update_type update_type,
-+		struct dc_state *context)
-+{
-+	int i, j;
-+
-+	if (update_type == UPDATE_TYPE_FULL) {
-+		dc->hwss.set_bandwidth(dc, context, false);
-+		context_clock_trace(dc, context);
-+	}
-+
-+	if (update_type > UPDATE_TYPE_FAST) {
-+		for (j = 0; j < dc->res_pool->pipe_count; j++) {
-+			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
-+
-+			dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
-+		}
-+	}
-+
-+	if (surface_count == 0) {
-+		/*
-+		 * In case of turning off screen, no need to program front end a second time.
-+		 * just return after program front end.
-+		 */
-+		dc->hwss.apply_ctx_for_surface(dc, stream, surface_count, context);
-+		return;
-+	}
-+
-+	/* Full fe update*/
-+	for (j = 0; j < dc->res_pool->pipe_count; j++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
-+
-+		if (update_type == UPDATE_TYPE_FAST || !pipe_ctx->plane_state)
-+			continue;
-+
-+		if (!pipe_ctx->top_pipe &&
-+		    pipe_ctx->stream &&
-+		    pipe_ctx->stream == stream) {
-+			struct dc_stream_status *stream_status =
-+					stream_get_status(context, pipe_ctx->stream);
-+
-+			dc->hwss.apply_ctx_for_surface(
-+					dc, pipe_ctx->stream, stream_status->plane_count, context);
-+		}
-+	}
-+
-+	if (update_type > UPDATE_TYPE_FAST)
-+		context_timing_trace(dc, &context->res_ctx);
-+
-+	/* Perform requested Updates */
-+	for (i = 0; i < surface_count; i++) {
-+		struct dc_plane_state *plane_state = srf_updates[i].surface;
-+
-+		for (j = 0; j < dc->res_pool->pipe_count; j++) {
-+			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
-+
-+			if (pipe_ctx->stream != stream)
-+				continue;
-+
-+			if (pipe_ctx->plane_state != plane_state)
-+				continue;
-+
-+			if (srf_updates[i].flip_addr)
-+				dc->hwss.update_plane_addr(dc, pipe_ctx);
-+		}
-+	}
-+
-+	if (stream && stream_update && update_type > UPDATE_TYPE_FAST)
-+		for (j = 0; j < dc->res_pool->pipe_count; j++) {
-+			struct pipe_ctx *pipe_ctx =
-+					&context->res_ctx.pipe_ctx[j];
-+
-+			if (pipe_ctx->stream != stream)
-+				continue;
-+
-+			if (stream_update->hdr_static_metadata) {
-+				resource_build_info_frame(pipe_ctx);
-+				dc->hwss.update_info_frame(pipe_ctx);
-+			}
-+		}
-+}
-+
-+void dc_commit_updates_for_stream(struct dc *dc,
-+		struct dc_surface_update *srf_updates,
-+		int surface_count,
-+		struct dc_stream_state *stream,
-+		struct dc_stream_update *stream_update,
-+		struct dc_plane_state **plane_states,
-+		struct dc_state *state)
-+{
-+	const struct dc_stream_status *stream_status;
-+	enum surface_update_type update_type;
-+	struct dc_state *context;
-+	struct dc_context *dc_ctx = dc->ctx;
-+	int i, j;
-+
-+	stream_status = dc_stream_get_status(stream);
-+	context = dc->current_state;
-+
-+	update_type = dc_check_update_surfaces_for_stream(
-+				dc, srf_updates, surface_count, stream_update, stream_status);
-+
-+	if (update_type >= update_surface_trace_level)
-+		update_surface_trace(dc, srf_updates, surface_count);
-+
-+
-+	if (update_type >= UPDATE_TYPE_FULL) {
-+
-+		/* initialize scratch memory for building context */
-+		context = dc_create_state();
-+		if (context == NULL) {
-+			DC_ERROR("Failed to allocate new validate context!\n");
-+			return;
-+		}
-+
-+		dc_resource_state_copy_construct(state, context);
-+	}
-+
-+
-+	for (i = 0; i < surface_count; i++) {
-+		struct dc_plane_state *surface = srf_updates[i].surface;
-+
-+		/* TODO: On flip we don't build the state, so it still has the
-+		 * old address. Which is why we are updating the address here
-+		 */
-+		if (srf_updates[i].flip_addr) {
-+			surface->address = srf_updates[i].flip_addr->address;
-+			surface->flip_immediate = srf_updates[i].flip_addr->flip_immediate;
-+
-+		}
-+
-+		if (update_type >= UPDATE_TYPE_MED) {
-+			for (j = 0; j < dc->res_pool->pipe_count; j++) {
-+				struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
-+
-+				if (pipe_ctx->plane_state != surface)
-+					continue;
-+
-+				resource_build_scaling_params(pipe_ctx);
-+			}
-+		}
-+	}
-+
-+	commit_planes_for_stream(
-+				dc,
-+				srf_updates,
-+				surface_count,
-+				stream,
-+				stream_update,
-+				update_type,
-+				context);
-+	/*update current_State*/
-+	if (dc->current_state != context) {
-+
-+		struct dc_state *old = dc->current_state;
-+
-+		dc->current_state = context;
-+		dc_release_state(old);
-+
-+	}
-+	/*let's use current_state to update watermark etc*/
-+	if (update_type >= UPDATE_TYPE_FULL)
-+		dc_post_update_surfaces_to_stream(dc);
-+
-+	return;
-+
-+}
-+
-+uint8_t dc_get_current_stream_count(struct dc *dc)
-+{
-+	return dc->current_state->stream_count;
-+}
-+
-+struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
-+{
-+	if (i < dc->current_state->stream_count)
-+		return dc->current_state->streams[i];
-+	return NULL;
-+}
-+
-+enum dc_irq_source dc_interrupt_to_irq_source(
-+		struct dc *dc,
-+		uint32_t src_id,
-+		uint32_t ext_id)
-+{
-+	return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
-+}
-+
-+void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
-+{
-+
-+	if (dc == NULL)
-+		return;
-+
-+	dal_irq_service_set(dc->res_pool->irqs, src, enable);
-+}
-+
-+void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
-+{
-+	dal_irq_service_ack(dc->res_pool->irqs, src);
-+}
-+
-+void dc_set_power_state(
-+	struct dc *dc,
-+	enum dc_acpi_cm_power_state power_state)
-+{
-+	struct kref refcount;
-+
-+	switch (power_state) {
-+	case DC_ACPI_CM_POWER_STATE_D0:
-+		dc_resource_state_construct(dc, dc->current_state);
-+
-+		dc->hwss.init_hw(dc);
-+		break;
-+	default:
-+
-+		dc->hwss.power_down(dc);
-+
-+		/* Zero out the current context so that on resume we start with
-+		 * clean state, and dc hw programming optimizations will not
-+		 * cause any trouble.
-+		 */
-+
-+		/* Preserve refcount */
-+		refcount = dc->current_state->refcount;
-+		dc_resource_state_destruct(dc->current_state);
-+		memset(dc->current_state, 0,
-+				sizeof(*dc->current_state));
-+
-+		dc->current_state->refcount = refcount;
-+
-+		break;
-+	}
-+
-+}
-+
-+void dc_resume(struct dc *dc)
-+{
-+
-+	uint32_t i;
-+
-+	for (i = 0; i < dc->link_count; i++)
-+		core_link_resume(dc->links[i]);
-+}
-+
-+bool dc_submit_i2c(
-+		struct dc *dc,
-+		uint32_t link_index,
-+		struct i2c_command *cmd)
-+{
-+
-+	struct dc_link *link = dc->links[link_index];
-+	struct ddc_service *ddc = link->ddc;
-+
-+	return dal_i2caux_submit_i2c_command(
-+		ddc->ctx->i2caux,
-+		ddc->ddc_pin,
-+		cmd);
-+}
-+
-+static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
-+{
-+	if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	dc_sink_retain(sink);
-+
-+	dc_link->remote_sinks[dc_link->sink_count] = sink;
-+	dc_link->sink_count++;
-+
-+	return true;
-+}
-+
-+struct dc_sink *dc_link_add_remote_sink(
-+		struct dc_link *link,
-+		const uint8_t *edid,
-+		int len,
-+		struct dc_sink_init_data *init_data)
-+{
-+	struct dc_sink *dc_sink;
-+	enum dc_edid_status edid_status;
-+
-+	if (len > MAX_EDID_BUFFER_SIZE) {
-+		dm_error("Max EDID buffer size breached!\n");
-+		return NULL;
-+	}
-+
-+	if (!init_data) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (!init_data->link) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dc_sink = dc_sink_create(init_data);
-+
-+	if (!dc_sink)
-+		return NULL;
-+
-+	memmove(dc_sink->dc_edid.raw_edid, edid, len);
-+	dc_sink->dc_edid.length = len;
-+
-+	if (!link_add_remote_sink_helper(
-+			link,
-+			dc_sink))
-+		goto fail_add_sink;
-+
-+	edid_status = dm_helpers_parse_edid_caps(
-+			link->ctx,
-+			&dc_sink->dc_edid,
-+			&dc_sink->edid_caps);
-+
-+	if (edid_status != EDID_OK)
-+		goto fail;
-+
-+	return dc_sink;
-+fail:
-+	dc_link_remove_remote_sink(link, dc_sink);
-+fail_add_sink:
-+	dc_sink_release(dc_sink);
-+	return NULL;
-+}
-+
-+void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
-+{
-+	int i;
-+
-+	if (!link->sink_count) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	for (i = 0; i < link->sink_count; i++) {
-+		if (link->remote_sinks[i] == sink) {
-+			dc_sink_release(sink);
-+			link->remote_sinks[i] = NULL;
-+
-+			/* shrink array to remove empty place */
-+			while (i < link->sink_count - 1) {
-+				link->remote_sinks[i] = link->remote_sinks[i+1];
-+				i++;
-+			}
-+			link->remote_sinks[i] = NULL;
-+			link->sink_count--;
-+			return;
-+		}
-+	}
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_debug.c.0130~	2017-12-14 06:39:58.405903560 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_debug.c	2017-12-14 06:39:58.405903560 +0100
-@@ -0,0 +1,363 @@
-+/*
-+ * dc_debug.c
-+ *
-+ *  Created on: Nov 3, 2016
-+ *      Author: yonsun
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "dc.h"
-+
-+#include "core_status.h"
-+#include "core_types.h"
-+#include "hw_sequencer.h"
-+
-+#include "resource.h"
-+
-+#define SURFACE_TRACE(...) do {\
-+		if (dc->debug.surface_trace) \
-+			dm_logger_write(logger, \
-+					LOG_IF_TRACE, \
-+					##__VA_ARGS__); \
-+} while (0)
-+
-+#define TIMING_TRACE(...) do {\
-+	if (dc->debug.timing_trace) \
-+		dm_logger_write(logger, \
-+				LOG_SYNC, \
-+				##__VA_ARGS__); \
-+} while (0)
-+
-+#define CLOCK_TRACE(...) do {\
-+	if (dc->debug.clock_trace) \
-+		dm_logger_write(logger, \
-+				LOG_BANDWIDTH_CALCS, \
-+				##__VA_ARGS__); \
-+} while (0)
-+
-+void pre_surface_trace(
-+		struct dc *dc,
-+		const struct dc_plane_state *const *plane_states,
-+		int surface_count)
-+{
-+	int i;
-+	struct dc  *core_dc = dc;
-+	struct dal_logger *logger =  core_dc->ctx->logger;
-+
-+	for (i = 0; i < surface_count; i++) {
-+		const struct dc_plane_state *plane_state = plane_states[i];
-+
-+		SURFACE_TRACE("Planes %d:\n", i);
-+
-+		SURFACE_TRACE(
-+				"plane_state->visible = %d;\n"
-+				"plane_state->flip_immediate = %d;\n"
-+				"plane_state->address.type = %d;\n"
-+				"plane_state->address.grph.addr.quad_part = 0x%X;\n"
-+				"plane_state->address.grph.meta_addr.quad_part = 0x%X;\n"
-+				"plane_state->scaling_quality.h_taps = %d;\n"
-+				"plane_state->scaling_quality.v_taps = %d;\n"
-+				"plane_state->scaling_quality.h_taps_c = %d;\n"
-+				"plane_state->scaling_quality.v_taps_c = %d;\n",
-+				plane_state->visible,
-+				plane_state->flip_immediate,
-+				plane_state->address.type,
-+				plane_state->address.grph.addr.quad_part,
-+				plane_state->address.grph.meta_addr.quad_part,
-+				plane_state->scaling_quality.h_taps,
-+				plane_state->scaling_quality.v_taps,
-+				plane_state->scaling_quality.h_taps_c,
-+				plane_state->scaling_quality.v_taps_c);
-+
-+		SURFACE_TRACE(
-+				"plane_state->src_rect.x = %d;\n"
-+				"plane_state->src_rect.y = %d;\n"
-+				"plane_state->src_rect.width = %d;\n"
-+				"plane_state->src_rect.height = %d;\n"
-+				"plane_state->dst_rect.x = %d;\n"
-+				"plane_state->dst_rect.y = %d;\n"
-+				"plane_state->dst_rect.width = %d;\n"
-+				"plane_state->dst_rect.height = %d;\n"
-+				"plane_state->clip_rect.x = %d;\n"
-+				"plane_state->clip_rect.y = %d;\n"
-+				"plane_state->clip_rect.width = %d;\n"
-+				"plane_state->clip_rect.height = %d;\n",
-+				plane_state->src_rect.x,
-+				plane_state->src_rect.y,
-+				plane_state->src_rect.width,
-+				plane_state->src_rect.height,
-+				plane_state->dst_rect.x,
-+				plane_state->dst_rect.y,
-+				plane_state->dst_rect.width,
-+				plane_state->dst_rect.height,
-+				plane_state->clip_rect.x,
-+				plane_state->clip_rect.y,
-+				plane_state->clip_rect.width,
-+				plane_state->clip_rect.height);
-+
-+		SURFACE_TRACE(
-+				"plane_state->plane_size.grph.surface_size.x = %d;\n"
-+				"plane_state->plane_size.grph.surface_size.y = %d;\n"
-+				"plane_state->plane_size.grph.surface_size.width = %d;\n"
-+				"plane_state->plane_size.grph.surface_size.height = %d;\n"
-+				"plane_state->plane_size.grph.surface_pitch = %d;\n",
-+				plane_state->plane_size.grph.surface_size.x,
-+				plane_state->plane_size.grph.surface_size.y,
-+				plane_state->plane_size.grph.surface_size.width,
-+				plane_state->plane_size.grph.surface_size.height,
-+				plane_state->plane_size.grph.surface_pitch);
-+
-+
-+		SURFACE_TRACE(
-+				"plane_state->tiling_info.gfx8.num_banks = %d;\n"
-+				"plane_state->tiling_info.gfx8.bank_width = %d;\n"
-+				"plane_state->tiling_info.gfx8.bank_width_c = %d;\n"
-+				"plane_state->tiling_info.gfx8.bank_height = %d;\n"
-+				"plane_state->tiling_info.gfx8.bank_height_c = %d;\n"
-+				"plane_state->tiling_info.gfx8.tile_aspect = %d;\n"
-+				"plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n"
-+				"plane_state->tiling_info.gfx8.tile_split = %d;\n"
-+				"plane_state->tiling_info.gfx8.tile_split_c = %d;\n"
-+				"plane_state->tiling_info.gfx8.tile_mode = %d;\n"
-+				"plane_state->tiling_info.gfx8.tile_mode_c = %d;\n",
-+				plane_state->tiling_info.gfx8.num_banks,
-+				plane_state->tiling_info.gfx8.bank_width,
-+				plane_state->tiling_info.gfx8.bank_width_c,
-+				plane_state->tiling_info.gfx8.bank_height,
-+				plane_state->tiling_info.gfx8.bank_height_c,
-+				plane_state->tiling_info.gfx8.tile_aspect,
-+				plane_state->tiling_info.gfx8.tile_aspect_c,
-+				plane_state->tiling_info.gfx8.tile_split,
-+				plane_state->tiling_info.gfx8.tile_split_c,
-+				plane_state->tiling_info.gfx8.tile_mode,
-+				plane_state->tiling_info.gfx8.tile_mode_c);
-+
-+		SURFACE_TRACE(
-+				"plane_state->tiling_info.gfx8.pipe_config = %d;\n"
-+				"plane_state->tiling_info.gfx8.array_mode = %d;\n"
-+				"plane_state->color_space = %d;\n"
-+				"plane_state->input_tf = %d;\n"
-+				"plane_state->dcc.enable = %d;\n"
-+				"plane_state->format = %d;\n"
-+				"plane_state->rotation = %d;\n"
-+				"plane_state->stereo_format = %d;\n",
-+				plane_state->tiling_info.gfx8.pipe_config,
-+				plane_state->tiling_info.gfx8.array_mode,
-+				plane_state->color_space,
-+				plane_state->input_tf,
-+				plane_state->dcc.enable,
-+				plane_state->format,
-+				plane_state->rotation,
-+				plane_state->stereo_format);
-+
-+		SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n",
-+				plane_state->tiling_info.gfx9.swizzle);
-+
-+		SURFACE_TRACE("\n");
-+	}
-+	SURFACE_TRACE("\n");
-+}
-+
-+void update_surface_trace(
-+		struct dc *dc,
-+		const struct dc_surface_update *updates,
-+		int surface_count)
-+{
-+	int i;
-+	struct dc  *core_dc = dc;
-+	struct dal_logger *logger =  core_dc->ctx->logger;
-+
-+	for (i = 0; i < surface_count; i++) {
-+		const struct dc_surface_update *update = &updates[i];
-+
-+		SURFACE_TRACE("Update %d\n", i);
-+		if (update->flip_addr) {
-+			SURFACE_TRACE("flip_addr->address.type = %d;\n"
-+					"flip_addr->address.grph.addr.quad_part = 0x%X;\n"
-+					"flip_addr->address.grph.meta_addr.quad_part = 0x%X;\n"
-+					"flip_addr->flip_immediate = %d;\n",
-+					update->flip_addr->address.type,
-+					update->flip_addr->address.grph.addr.quad_part,
-+					update->flip_addr->address.grph.meta_addr.quad_part,
-+					update->flip_addr->flip_immediate);
-+		}
-+
-+		if (update->plane_info) {
-+			SURFACE_TRACE(
-+					"plane_info->color_space = %d;\n"
-+					"plane_info->input_tf = %d;\n"
-+					"plane_info->format = %d;\n"
-+					"plane_info->plane_size.grph.surface_pitch = %d;\n"
-+					"plane_info->plane_size.grph.surface_size.height = %d;\n"
-+					"plane_info->plane_size.grph.surface_size.width = %d;\n"
-+					"plane_info->plane_size.grph.surface_size.x = %d;\n"
-+					"plane_info->plane_size.grph.surface_size.y = %d;\n"
-+					"plane_info->rotation = %d;\n",
-+					update->plane_info->color_space,
-+					update->plane_info->input_tf,
-+					update->plane_info->format,
-+					update->plane_info->plane_size.grph.surface_pitch,
-+					update->plane_info->plane_size.grph.surface_size.height,
-+					update->plane_info->plane_size.grph.surface_size.width,
-+					update->plane_info->plane_size.grph.surface_size.x,
-+					update->plane_info->plane_size.grph.surface_size.y,
-+					update->plane_info->rotation,
-+					update->plane_info->stereo_format);
-+
-+			SURFACE_TRACE(
-+					"plane_info->tiling_info.gfx8.num_banks = %d;\n"
-+					"plane_info->tiling_info.gfx8.bank_width = %d;\n"
-+					"plane_info->tiling_info.gfx8.bank_width_c = %d;\n"
-+					"plane_info->tiling_info.gfx8.bank_height = %d;\n"
-+					"plane_info->tiling_info.gfx8.bank_height_c = %d;\n"
-+					"plane_info->tiling_info.gfx8.tile_aspect = %d;\n"
-+					"plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n"
-+					"plane_info->tiling_info.gfx8.tile_split = %d;\n"
-+					"plane_info->tiling_info.gfx8.tile_split_c = %d;\n"
-+					"plane_info->tiling_info.gfx8.tile_mode = %d;\n"
-+					"plane_info->tiling_info.gfx8.tile_mode_c = %d;\n",
-+					update->plane_info->tiling_info.gfx8.num_banks,
-+					update->plane_info->tiling_info.gfx8.bank_width,
-+					update->plane_info->tiling_info.gfx8.bank_width_c,
-+					update->plane_info->tiling_info.gfx8.bank_height,
-+					update->plane_info->tiling_info.gfx8.bank_height_c,
-+					update->plane_info->tiling_info.gfx8.tile_aspect,
-+					update->plane_info->tiling_info.gfx8.tile_aspect_c,
-+					update->plane_info->tiling_info.gfx8.tile_split,
-+					update->plane_info->tiling_info.gfx8.tile_split_c,
-+					update->plane_info->tiling_info.gfx8.tile_mode,
-+					update->plane_info->tiling_info.gfx8.tile_mode_c);
-+
-+			SURFACE_TRACE(
-+					"plane_info->tiling_info.gfx8.pipe_config = %d;\n"
-+					"plane_info->tiling_info.gfx8.array_mode = %d;\n"
-+					"plane_info->visible = %d;\n"
-+					"plane_info->per_pixel_alpha = %d;\n",
-+					update->plane_info->tiling_info.gfx8.pipe_config,
-+					update->plane_info->tiling_info.gfx8.array_mode,
-+					update->plane_info->visible,
-+					update->plane_info->per_pixel_alpha);
-+
-+			SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
-+					update->plane_info->tiling_info.gfx9.swizzle);
-+		}
-+
-+		if (update->scaling_info) {
-+			SURFACE_TRACE(
-+					"scaling_info->src_rect.x = %d;\n"
-+					"scaling_info->src_rect.y = %d;\n"
-+					"scaling_info->src_rect.width = %d;\n"
-+					"scaling_info->src_rect.height = %d;\n"
-+					"scaling_info->dst_rect.x = %d;\n"
-+					"scaling_info->dst_rect.y = %d;\n"
-+					"scaling_info->dst_rect.width = %d;\n"
-+					"scaling_info->dst_rect.height = %d;\n"
-+					"scaling_info->clip_rect.x = %d;\n"
-+					"scaling_info->clip_rect.y = %d;\n"
-+					"scaling_info->clip_rect.width = %d;\n"
-+					"scaling_info->clip_rect.height = %d;\n"
-+					"scaling_info->scaling_quality.h_taps = %d;\n"
-+					"scaling_info->scaling_quality.v_taps = %d;\n"
-+					"scaling_info->scaling_quality.h_taps_c = %d;\n"
-+					"scaling_info->scaling_quality.v_taps_c = %d;\n",
-+					update->scaling_info->src_rect.x,
-+					update->scaling_info->src_rect.y,
-+					update->scaling_info->src_rect.width,
-+					update->scaling_info->src_rect.height,
-+					update->scaling_info->dst_rect.x,
-+					update->scaling_info->dst_rect.y,
-+					update->scaling_info->dst_rect.width,
-+					update->scaling_info->dst_rect.height,
-+					update->scaling_info->clip_rect.x,
-+					update->scaling_info->clip_rect.y,
-+					update->scaling_info->clip_rect.width,
-+					update->scaling_info->clip_rect.height,
-+					update->scaling_info->scaling_quality.h_taps,
-+					update->scaling_info->scaling_quality.v_taps,
-+					update->scaling_info->scaling_quality.h_taps_c,
-+					update->scaling_info->scaling_quality.v_taps_c);
-+		}
-+		SURFACE_TRACE("\n");
-+	}
-+	SURFACE_TRACE("\n");
-+}
-+
-+void post_surface_trace(struct dc *dc)
-+{
-+	struct dc  *core_dc = dc;
-+	struct dal_logger *logger =  core_dc->ctx->logger;
-+
-+	SURFACE_TRACE("post surface process.\n");
-+
-+}
-+
-+void context_timing_trace(
-+		struct dc *dc,
-+		struct resource_context *res_ctx)
-+{
-+	int i;
-+	struct dc  *core_dc = dc;
-+	struct dal_logger *logger =  core_dc->ctx->logger;
-+	int h_pos[MAX_PIPES], v_pos[MAX_PIPES];
-+	struct crtc_position position;
-+	unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
-+
-+
-+	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
-+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
-+		/* get_position() returns CRTC vertical/horizontal counter
-+		 * hence not applicable for underlay pipe
-+		 */
-+		if (pipe_ctx->stream == NULL
-+				 || pipe_ctx->pipe_idx == underlay_idx)
-+			continue;
-+
-+		pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);
-+		h_pos[i] = position.horizontal_count;
-+		v_pos[i] = position.vertical_count;
-+	}
-+	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
-+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
-+
-+		if (pipe_ctx->stream == NULL)
-+			continue;
-+
-+		TIMING_TRACE("OTG_%d   H_tot:%d  V_tot:%d   H_pos:%d  V_pos:%d\n",
-+				pipe_ctx->stream_res.tg->inst,
-+				pipe_ctx->stream->timing.h_total,
-+				pipe_ctx->stream->timing.v_total,
-+				h_pos[i], v_pos[i]);
-+	}
-+}
-+
-+void context_clock_trace(
-+		struct dc *dc,
-+		struct dc_state *context)
-+{
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	struct dc  *core_dc = dc;
-+	struct dal_logger *logger =  core_dc->ctx->logger;
-+
-+	CLOCK_TRACE("Current: dispclk_khz:%d  dppclk_div:%d  dcfclk_khz:%d\n"
-+			"dcfclk_deep_sleep_khz:%d  fclk_khz:%d\n"
-+			"dram_ccm_us:%d  min_active_dram_ccm_us:%d\n",
-+			context->bw.dcn.calc_clk.dispclk_khz,
-+			context->bw.dcn.calc_clk.dppclk_div,
-+			context->bw.dcn.calc_clk.dcfclk_khz,
-+			context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
-+			context->bw.dcn.calc_clk.fclk_khz,
-+			context->bw.dcn.calc_clk.dram_ccm_us,
-+			context->bw.dcn.calc_clk.min_active_dram_ccm_us);
-+	CLOCK_TRACE("Calculated: dispclk_khz:%d  dppclk_div:%d  dcfclk_khz:%d\n"
-+			"dcfclk_deep_sleep_khz:%d  fclk_khz:%d\n"
-+			"dram_ccm_us:%d  min_active_dram_ccm_us:%d\n",
-+			context->bw.dcn.calc_clk.dispclk_khz,
-+			context->bw.dcn.calc_clk.dppclk_div,
-+			context->bw.dcn.calc_clk.dcfclk_khz,
-+			context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
-+			context->bw.dcn.calc_clk.fclk_khz,
-+			context->bw.dcn.calc_clk.dram_ccm_us,
-+			context->bw.dcn.calc_clk.min_active_dram_ccm_us);
-+#endif
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c.0130~	2017-12-14 06:39:58.405903560 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c	2017-12-14 06:39:58.405903560 +0100
-@@ -0,0 +1,101 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "core_types.h"
-+#include "timing_generator.h"
-+#include "hw_sequencer.h"
-+
-+/* used as index in array of black_color_format */
-+enum black_color_format {
-+	BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,
-+	BLACK_COLOR_FORMAT_RGB_LIMITED,
-+	BLACK_COLOR_FORMAT_YUV_TV,
-+	BLACK_COLOR_FORMAT_YUV_CV,
-+	BLACK_COLOR_FORMAT_YUV_SUPER_AA,
-+	BLACK_COLOR_FORMAT_DEBUG,
-+};
-+
-+static const struct tg_color black_color_format[] = {
-+	/* BlackColorFormat_RGB_FullRange */
-+	{0, 0, 0},
-+	/* BlackColorFormat_RGB_Limited */
-+	{0x40, 0x40, 0x40},
-+	/* BlackColorFormat_YUV_TV */
-+	{0x200, 0x40, 0x200},
-+	/* BlackColorFormat_YUV_CV */
-+	{0x1f4, 0x40, 0x1f4},
-+	/* BlackColorFormat_YUV_SuperAA */
-+	{0x1a2, 0x20, 0x1a2},
-+	/* visual confirm debug */
-+	{0xff, 0xff, 0},
-+};
-+
-+void color_space_to_black_color(
-+	const struct dc *dc,
-+	enum dc_color_space colorspace,
-+	struct tg_color *black_color)
-+{
-+	switch (colorspace) {
-+	case COLOR_SPACE_YCBCR601:
-+	case COLOR_SPACE_YCBCR709:
-+	case COLOR_SPACE_YCBCR601_LIMITED:
-+	case COLOR_SPACE_YCBCR709_LIMITED:
-+		*black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];
-+		break;
-+
-+	case COLOR_SPACE_SRGB_LIMITED:
-+		*black_color =
-+			black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];
-+		break;
-+
-+	default:
-+		/* fefault is sRGB black (full range). */
-+		*black_color =
-+			black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE];
-+		/* default is sRGB black 0. */
-+		break;
-+	}
-+}
-+
-+bool hwss_wait_for_blank_complete(
-+		struct timing_generator *tg)
-+{
-+	int counter;
-+
-+	for (counter = 0; counter < 100; counter++) {
-+		if (tg->funcs->is_blanked(tg))
-+			break;
-+
-+		msleep(1);
-+	}
-+
-+	if (counter == 100) {
-+		dm_error("DC: failed to blank crtc!\n");
-+		return false;
-+	}
-+
-+	return true;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_link.c.0130~	2017-12-14 06:39:58.406903561 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_link.c	2017-12-14 06:39:58.406903561 +0100
-@@ -0,0 +1,2435 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "atom.h"
-+#include "dm_helpers.h"
-+#include "dc.h"
-+#include "grph_object_id.h"
-+#include "gpio_service_interface.h"
-+#include "core_status.h"
-+#include "dc_link_dp.h"
-+#include "dc_link_ddc.h"
-+#include "link_hwss.h"
-+
-+#include "link_encoder.h"
-+#include "hw_sequencer.h"
-+#include "resource.h"
-+#include "abm.h"
-+#include "fixed31_32.h"
-+#include "dpcd_defs.h"
-+#include "dmcu.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_enum.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#define LINK_INFO(...) \
-+	dm_logger_write(dc_ctx->logger, LOG_HW_HOTPLUG, \
-+		__VA_ARGS__)
-+
-+/*******************************************************************************
-+ * Private structures
-+ ******************************************************************************/
-+
-+enum {
-+	LINK_RATE_REF_FREQ_IN_MHZ = 27,
-+	PEAK_FACTOR_X1000 = 1006
-+};
-+
-+/*******************************************************************************
-+ * Private functions
-+ ******************************************************************************/
-+static void destruct(struct dc_link *link)
-+{
-+	int i;
-+
-+	if (link->ddc)
-+		dal_ddc_service_destroy(&link->ddc);
-+
-+	if(link->link_enc)
-+		link->link_enc->funcs->destroy(&link->link_enc);
-+
-+	if (link->local_sink)
-+		dc_sink_release(link->local_sink);
-+
-+	for (i = 0; i < link->sink_count; ++i)
-+		dc_sink_release(link->remote_sinks[i]);
-+}
-+
-+struct gpio *get_hpd_gpio(struct dc_bios *dcb,
-+		struct graphics_object_id link_id,
-+		struct gpio_service *gpio_service)
-+{
-+	enum bp_result bp_result;
-+	struct graphics_object_hpd_info hpd_info;
-+	struct gpio_pin_info pin_info;
-+
-+	if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
-+		return NULL;
-+
-+	bp_result = dcb->funcs->get_gpio_pin_info(dcb,
-+		hpd_info.hpd_int_gpio_uid, &pin_info);
-+
-+	if (bp_result != BP_RESULT_OK) {
-+		ASSERT(bp_result == BP_RESULT_NORECORD);
-+		return NULL;
-+	}
-+
-+	return dal_gpio_service_create_irq(
-+		gpio_service,
-+		pin_info.offset,
-+		pin_info.mask);
-+}
-+
-+/*
-+ *  Function: program_hpd_filter
-+ *
-+ *  @brief
-+ *     Programs HPD filter on associated HPD line
-+ *
-+ *  @param [in] delay_on_connect_in_ms: Connect filter timeout
-+ *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
-+ *
-+ *  @return
-+ *     true on success, false otherwise
-+ */
-+static bool program_hpd_filter(
-+	const struct dc_link *link)
-+{
-+	bool result = false;
-+
-+	struct gpio *hpd;
-+
-+	int delay_on_connect_in_ms = 0;
-+	int delay_on_disconnect_in_ms = 0;
-+
-+	/* Verify feature is supported */
-+	switch (link->connector_signal) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		/* Program hpd filter */
-+		delay_on_connect_in_ms = 500;
-+		delay_on_disconnect_in_ms = 100;
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		/* Program hpd filter to allow DP signal to settle */
-+		/* 500:	not able to detect MST <-> SST switch as HPD is low for
-+		 * 	only 100ms on DELL U2413
-+		 * 0:	some passive dongle still show aux mode instead of i2c
-+		 * 20-50:not enough to hide bouncing HPD with passive dongle.
-+		 * 	also see intermittent i2c read issues.
-+		 */
-+		delay_on_connect_in_ms = 80;
-+		delay_on_disconnect_in_ms = 0;
-+		break;
-+	case SIGNAL_TYPE_LVDS:
-+	case SIGNAL_TYPE_EDP:
-+	default:
-+		/* Don't program hpd filter */
-+		return false;
-+	}
-+
-+	/* Obtain HPD handle */
-+	hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
-+
-+	if (!hpd)
-+		return result;
-+
-+	/* Setup HPD filtering */
-+	if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
-+		struct gpio_hpd_config config;
-+
-+		config.delay_on_connect = delay_on_connect_in_ms;
-+		config.delay_on_disconnect = delay_on_disconnect_in_ms;
-+
-+		dal_irq_setup_hpd_filter(hpd, &config);
-+
-+		dal_gpio_close(hpd);
-+
-+		result = true;
-+	} else {
-+		ASSERT_CRITICAL(false);
-+	}
-+
-+	/* Release HPD handle */
-+	dal_gpio_destroy_irq(&hpd);
-+
-+	return result;
-+}
-+
-+static bool detect_sink(struct dc_link *link, enum dc_connection_type *type)
-+{
-+	uint32_t is_hpd_high = 0;
-+	struct gpio *hpd_pin;
-+
-+	/* todo: may need to lock gpio access */
-+	hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
-+	if (hpd_pin == NULL)
-+		goto hpd_gpio_failure;
-+
-+	dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
-+	dal_gpio_get_value(hpd_pin, &is_hpd_high);
-+	dal_gpio_close(hpd_pin);
-+	dal_gpio_destroy_irq(&hpd_pin);
-+
-+	if (is_hpd_high) {
-+		*type = dc_connection_single;
-+		/* TODO: need to do the actual detection */
-+	} else {
-+		*type = dc_connection_none;
-+	}
-+
-+	return true;
-+
-+hpd_gpio_failure:
-+	return false;
-+}
-+
-+static enum ddc_transaction_type get_ddc_transaction_type(
-+		enum signal_type sink_signal)
-+{
-+	enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
-+
-+	switch (sink_signal) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+	case SIGNAL_TYPE_LVDS:
-+	case SIGNAL_TYPE_RGB:
-+		transaction_type = DDC_TRANSACTION_TYPE_I2C;
-+		break;
-+
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_EDP:
-+		transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
-+		break;
-+
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		/* MST does not use I2COverAux, but there is the
-+		 * SPECIAL use case for "immediate dwnstrm device
-+		 * access" (EPR#370830). */
-+		transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return transaction_type;
-+}
-+
-+static enum signal_type get_basic_signal_type(
-+	struct graphics_object_id encoder,
-+	struct graphics_object_id downstream)
-+{
-+	if (downstream.type == OBJECT_TYPE_CONNECTOR) {
-+		switch (downstream.id) {
-+		case CONNECTOR_ID_SINGLE_LINK_DVII:
-+			switch (encoder.id) {
-+			case ENCODER_ID_INTERNAL_DAC1:
-+			case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
-+			case ENCODER_ID_INTERNAL_DAC2:
-+			case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
-+				return SIGNAL_TYPE_RGB;
-+			default:
-+				return SIGNAL_TYPE_DVI_SINGLE_LINK;
-+			}
-+		break;
-+		case CONNECTOR_ID_DUAL_LINK_DVII:
-+		{
-+			switch (encoder.id) {
-+			case ENCODER_ID_INTERNAL_DAC1:
-+			case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
-+			case ENCODER_ID_INTERNAL_DAC2:
-+			case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
-+				return SIGNAL_TYPE_RGB;
-+			default:
-+				return SIGNAL_TYPE_DVI_DUAL_LINK;
-+			}
-+		}
-+		break;
-+		case CONNECTOR_ID_SINGLE_LINK_DVID:
-+			return SIGNAL_TYPE_DVI_SINGLE_LINK;
-+		case CONNECTOR_ID_DUAL_LINK_DVID:
-+			return SIGNAL_TYPE_DVI_DUAL_LINK;
-+		case CONNECTOR_ID_VGA:
-+			return SIGNAL_TYPE_RGB;
-+		case CONNECTOR_ID_HDMI_TYPE_A:
-+			return SIGNAL_TYPE_HDMI_TYPE_A;
-+		case CONNECTOR_ID_LVDS:
-+			return SIGNAL_TYPE_LVDS;
-+		case CONNECTOR_ID_DISPLAY_PORT:
-+			return SIGNAL_TYPE_DISPLAY_PORT;
-+		case CONNECTOR_ID_EDP:
-+			return SIGNAL_TYPE_EDP;
-+		default:
-+			return SIGNAL_TYPE_NONE;
-+		}
-+	} else if (downstream.type == OBJECT_TYPE_ENCODER) {
-+		switch (downstream.id) {
-+		case ENCODER_ID_EXTERNAL_NUTMEG:
-+		case ENCODER_ID_EXTERNAL_TRAVIS:
-+			return SIGNAL_TYPE_DISPLAY_PORT;
-+		default:
-+			return SIGNAL_TYPE_NONE;
-+		}
-+	}
-+
-+	return SIGNAL_TYPE_NONE;
-+}
-+
-+/*
-+ * @brief
-+ * Check whether there is a dongle on DP connector
-+ */
-+static bool is_dp_sink_present(struct dc_link *link)
-+{
-+	enum gpio_result gpio_result;
-+	uint32_t clock_pin = 0;
-+
-+	struct ddc *ddc;
-+
-+	enum connector_id connector_id =
-+		dal_graphics_object_id_get_connector_id(link->link_id);
-+
-+	bool present =
-+		((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
-+		(connector_id == CONNECTOR_ID_EDP));
-+
-+	ddc = dal_ddc_service_get_ddc_pin(link->ddc);
-+
-+	if (!ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return present;
-+	}
-+
-+	/* Open GPIO and set it to I2C mode */
-+	/* Note: this GpioMode_Input will be converted
-+	 * to GpioConfigType_I2cAuxDualMode in GPIO component,
-+	 * which indicates we need additional delay */
-+
-+	if (GPIO_RESULT_OK != dal_ddc_open(
-+		ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
-+		dal_gpio_destroy_ddc(&ddc);
-+
-+		return present;
-+	}
-+
-+	/* Read GPIO: DP sink is present if both clock and data pins are zero */
-+	/* [anaumov] in DAL2, there was no check for GPIO failure */
-+
-+	gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
-+	ASSERT(gpio_result == GPIO_RESULT_OK);
-+
-+	present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
-+
-+	dal_ddc_close(ddc);
-+
-+	return present;
-+}
-+
-+/*
-+ * @brief
-+ * Detect output sink type
-+ */
-+static enum signal_type link_detect_sink(
-+	struct dc_link *link,
-+	enum dc_detect_reason reason)
-+{
-+	enum signal_type result = get_basic_signal_type(
-+		link->link_enc->id, link->link_id);
-+
-+	/* Internal digital encoder will detect only dongles
-+	 * that require digital signal */
-+
-+	/* Detection mechanism is different
-+	 * for different native connectors.
-+	 * LVDS connector supports only LVDS signal;
-+	 * PCIE is a bus slot, the actual connector needs to be detected first;
-+	 * eDP connector supports only eDP signal;
-+	 * HDMI should check straps for audio */
-+
-+	/* PCIE detects the actual connector on add-on board */
-+
-+	if (link->link_id.id == CONNECTOR_ID_PCIE) {
-+		/* ZAZTODO implement PCIE add-on card detection */
-+	}
-+
-+	switch (link->link_id.id) {
-+	case CONNECTOR_ID_HDMI_TYPE_A: {
-+		/* check audio support:
-+		 * if native HDMI is not supported, switch to DVI */
-+		struct audio_support *aud_support = &link->dc->res_pool->audio_support;
-+
-+		if (!aud_support->hdmi_audio_native)
-+			if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
-+				result = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+	}
-+	break;
-+	case CONNECTOR_ID_DISPLAY_PORT: {
-+		/* DP HPD short pulse. Passive DP dongle will not
-+		 * have short pulse
-+		 */
-+		if (reason != DETECT_REASON_HPDRX) {
-+			/* Check whether DP signal detected: if not -
-+			 * we assume signal is DVI; it could be corrected
-+			 * to HDMI after dongle detection
-+			 */
-+			if (!is_dp_sink_present(link))
-+				result = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+		}
-+	}
-+	break;
-+	default:
-+	break;
-+	}
-+
-+	return result;
-+}
-+
-+static enum signal_type decide_signal_from_strap_and_dongle_type(
-+		enum display_dongle_type dongle_type,
-+		struct audio_support *audio_support)
-+{
-+	enum signal_type signal = SIGNAL_TYPE_NONE;
-+
-+	switch (dongle_type) {
-+	case DISPLAY_DONGLE_DP_HDMI_DONGLE:
-+		if (audio_support->hdmi_audio_on_dongle)
-+			signal =  SIGNAL_TYPE_HDMI_TYPE_A;
-+		else
-+			signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+		break;
-+	case DISPLAY_DONGLE_DP_DVI_DONGLE:
-+		signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+		break;
-+	case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
-+		if (audio_support->hdmi_audio_native)
-+			signal =  SIGNAL_TYPE_HDMI_TYPE_A;
-+		else
-+			signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+		break;
-+	default:
-+		signal = SIGNAL_TYPE_NONE;
-+		break;
-+	}
-+
-+	return signal;
-+}
-+
-+static enum signal_type dp_passive_dongle_detection(
-+		struct ddc_service *ddc,
-+		struct display_sink_capability *sink_cap,
-+		struct audio_support *audio_support)
-+{
-+	dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
-+						ddc, sink_cap);
-+	return decide_signal_from_strap_and_dongle_type(
-+			sink_cap->dongle_type,
-+			audio_support);
-+}
-+
-+static void link_disconnect_sink(struct dc_link *link)
-+{
-+	if (link->local_sink) {
-+		dc_sink_release(link->local_sink);
-+		link->local_sink = NULL;
-+	}
-+
-+	link->dpcd_sink_count = 0;
-+}
-+
-+static void detect_dp(
-+	struct dc_link *link,
-+	struct display_sink_capability *sink_caps,
-+	bool *converter_disable_audio,
-+	struct audio_support *audio_support,
-+	enum dc_detect_reason reason)
-+{
-+	bool boot = false;
-+	sink_caps->signal = link_detect_sink(link, reason);
-+	sink_caps->transaction_type =
-+		get_ddc_transaction_type(sink_caps->signal);
-+
-+	if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
-+		sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
-+		detect_dp_sink_caps(link);
-+
-+		if (is_mst_supported(link)) {
-+			sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
-+			link->type = dc_connection_mst_branch;
-+
-+			/*
-+			 * This call will initiate MST topology discovery. Which
-+			 * will detect MST ports and add new DRM connector DRM
-+			 * framework. Then read EDID via remote i2c over aux. In
-+			 * the end, will notify DRM detect result and save EDID
-+			 * into DRM framework.
-+			 *
-+			 * .detect is called by .fill_modes.
-+			 * .fill_modes is called by user mode ioctl
-+			 * DRM_IOCTL_MODE_GETCONNECTOR.
-+			 *
-+			 * .get_modes is called by .fill_modes.
-+			 *
-+			 * call .get_modes, AMDGPU DM implementation will create
-+			 * new dc_sink and add to dc_link. For long HPD plug
-+			 * in/out, MST has its own handle.
-+			 *
-+			 * Therefore, just after dc_create, link->sink is not
-+			 * created for MST until user mode app calls
-+			 * DRM_IOCTL_MODE_GETCONNECTOR.
-+			 *
-+			 * Need check ->sink usages in case ->sink = NULL
-+			 * TODO: s3 resume check
-+			 */
-+			if (reason == DETECT_REASON_BOOT)
-+				boot = true;
-+
-+			if (!dm_helpers_dp_mst_start_top_mgr(
-+				link->ctx,
-+				link, boot)) {
-+				/* MST not supported */
-+				link->type = dc_connection_single;
-+				sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
-+			}
-+		}
-+
-+		if (link->type != dc_connection_mst_branch &&
-+			is_dp_active_dongle(link)) {
-+			/* DP active dongles */
-+			link->type = dc_connection_active_dongle;
-+			if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
-+				/*
-+				 * active dongle unplug processing for short irq
-+				 */
-+				link_disconnect_sink(link);
-+				return;
-+			}
-+
-+			if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
-+				*converter_disable_audio = true;
-+		}
-+	} else {
-+		/* DP passive dongles */
-+		sink_caps->signal = dp_passive_dongle_detection(link->ddc,
-+				sink_caps,
-+				audio_support);
-+	}
-+}
-+
-+bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
-+{
-+	struct dc_sink_init_data sink_init_data = { 0 };
-+	struct display_sink_capability sink_caps = { 0 };
-+	uint8_t i;
-+	bool converter_disable_audio = false;
-+	struct audio_support *aud_support = &link->dc->res_pool->audio_support;
-+	enum dc_edid_status edid_status;
-+	struct dc_context *dc_ctx = link->ctx;
-+	struct dc_sink *sink = NULL;
-+	enum dc_connection_type new_connection_type = dc_connection_none;
-+
-+	if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
-+		return false;
-+
-+	if (false == detect_sink(link, &new_connection_type)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (link->connector_signal == SIGNAL_TYPE_EDP &&
-+			link->local_sink)
-+		return true;
-+
-+	link_disconnect_sink(link);
-+
-+	if (new_connection_type != dc_connection_none) {
-+		link->type = new_connection_type;
-+
-+		/* From Disconnected-to-Connected. */
-+		switch (link->connector_signal) {
-+		case SIGNAL_TYPE_HDMI_TYPE_A: {
-+			sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
-+			if (aud_support->hdmi_audio_native)
-+				sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
-+			else
-+				sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+			break;
-+		}
-+
-+		case SIGNAL_TYPE_DVI_SINGLE_LINK: {
-+			sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
-+			sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+			break;
-+		}
-+
-+		case SIGNAL_TYPE_DVI_DUAL_LINK: {
-+			sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
-+			sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
-+			break;
-+		}
-+
-+		case SIGNAL_TYPE_EDP: {
-+			detect_edp_sink_caps(link);
-+			sink_caps.transaction_type =
-+				DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
-+			sink_caps.signal = SIGNAL_TYPE_EDP;
-+			break;
-+		}
-+
-+		case SIGNAL_TYPE_DISPLAY_PORT: {
-+			detect_dp(
-+				link,
-+				&sink_caps,
-+				&converter_disable_audio,
-+				aud_support, reason);
-+
-+			/* Active dongle downstream unplug */
-+			if (link->type == dc_connection_active_dongle
-+					&& link->dpcd_caps.sink_count.
-+					bits.SINK_COUNT == 0)
-+				return true;
-+
-+			if (link->type == dc_connection_mst_branch) {
-+				LINK_INFO("link=%d, mst branch is now Connected\n",
-+					link->link_index);
-+				/* Need to setup mst link_cap struct here
-+				 * otherwise dc_link_detect() will leave mst link_cap
-+				 * empty which leads to allocate_mst_payload() has "0"
-+				 * pbn_per_slot value leading to exception on dal_fixed31_32_div()
-+				 */
-+				link->verified_link_cap = link->reported_link_cap;
-+				return false;
-+			}
-+
-+			break;
-+		}
-+
-+		default:
-+			DC_ERROR("Invalid connector type! signal:%d\n",
-+				link->connector_signal);
-+			return false;
-+		} /* switch() */
-+
-+		if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
-+			link->dpcd_sink_count = link->dpcd_caps.sink_count.
-+					bits.SINK_COUNT;
-+		else
-+			link->dpcd_sink_count = 1;
-+
-+		dal_ddc_service_set_transaction_type(
-+						link->ddc,
-+						sink_caps.transaction_type);
-+
-+		link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
-+				link->ddc);
-+
-+		sink_init_data.link = link;
-+		sink_init_data.sink_signal = sink_caps.signal;
-+
-+		sink = dc_sink_create(&sink_init_data);
-+		if (!sink) {
-+			DC_ERROR("Failed to create sink!\n");
-+			return false;
-+		}
-+
-+		sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
-+		sink->converter_disable_audio = converter_disable_audio;
-+
-+		link->local_sink = sink;
-+
-+		edid_status = dm_helpers_read_local_edid(
-+				link->ctx,
-+				link,
-+				sink);
-+
-+		switch (edid_status) {
-+		case EDID_BAD_CHECKSUM:
-+			dm_logger_write(link->ctx->logger, LOG_ERROR,
-+				"EDID checksum invalid.\n");
-+			break;
-+		case EDID_NO_RESPONSE:
-+			dm_logger_write(link->ctx->logger, LOG_ERROR,
-+				"No EDID read.\n");
-+			return false;
-+
-+		default:
-+			break;
-+		}
-+
-+		if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
-+			sink_caps.transaction_type ==
-+			DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
-+			/*
-+			 * TODO debug why Dell 2413 doesn't like
-+			 *  two link trainings
-+			 */
-+
-+			/* deal with non-mst cases */
-+			dp_hbr_verify_link_cap(link, &link->reported_link_cap);
-+		}
-+
-+		/* HDMI-DVI Dongle */
-+		if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
-+				!sink->edid_caps.edid_hdmi)
-+			sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+
-+		/* Connectivity log: detection */
-+		for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) {
-+			CONN_DATA_DETECT(link,
-+					&sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE],
-+					EDID_BLOCK_SIZE,
-+					"%s: [Block %d] ", sink->edid_caps.display_name, i);
-+		}
-+
-+		dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER,
-+			"%s: "
-+			"manufacturer_id = %X, "
-+			"product_id = %X, "
-+			"serial_number = %X, "
-+			"manufacture_week = %d, "
-+			"manufacture_year = %d, "
-+			"display_name = %s, "
-+			"speaker_flag = %d, "
-+			"audio_mode_count = %d\n",
-+			__func__,
-+			sink->edid_caps.manufacturer_id,
-+			sink->edid_caps.product_id,
-+			sink->edid_caps.serial_number,
-+			sink->edid_caps.manufacture_week,
-+			sink->edid_caps.manufacture_year,
-+			sink->edid_caps.display_name,
-+			sink->edid_caps.speaker_flags,
-+			sink->edid_caps.audio_mode_count);
-+
-+		for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
-+			dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER,
-+				"%s: mode number = %d, "
-+				"format_code = %d, "
-+				"channel_count = %d, "
-+				"sample_rate = %d, "
-+				"sample_size = %d\n",
-+				__func__,
-+				i,
-+				sink->edid_caps.audio_modes[i].format_code,
-+				sink->edid_caps.audio_modes[i].channel_count,
-+				sink->edid_caps.audio_modes[i].sample_rate,
-+				sink->edid_caps.audio_modes[i].sample_size);
-+		}
-+
-+	} else {
-+		/* From Connected-to-Disconnected. */
-+		if (link->type == dc_connection_mst_branch) {
-+			LINK_INFO("link=%d, mst branch is now Disconnected\n",
-+				link->link_index);
-+
-+			dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
-+
-+			link->mst_stream_alloc_table.stream_count = 0;
-+			memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
-+		}
-+
-+		link->type = dc_connection_none;
-+		sink_caps.signal = SIGNAL_TYPE_NONE;
-+	}
-+
-+	LINK_INFO("link=%d, dc_sink_in=%p is now %s\n",
-+		link->link_index, sink,
-+		(sink_caps.signal == SIGNAL_TYPE_NONE ?
-+			"Disconnected":"Connected"));
-+
-+	return true;
-+}
-+
-+static enum hpd_source_id get_hpd_line(
-+		struct dc_link *link)
-+{
-+	struct gpio *hpd;
-+	enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
-+
-+	hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
-+
-+	if (hpd) {
-+		switch (dal_irq_get_source(hpd)) {
-+		case DC_IRQ_SOURCE_HPD1:
-+			hpd_id = HPD_SOURCEID1;
-+		break;
-+		case DC_IRQ_SOURCE_HPD2:
-+			hpd_id = HPD_SOURCEID2;
-+		break;
-+		case DC_IRQ_SOURCE_HPD3:
-+			hpd_id = HPD_SOURCEID3;
-+		break;
-+		case DC_IRQ_SOURCE_HPD4:
-+			hpd_id = HPD_SOURCEID4;
-+		break;
-+		case DC_IRQ_SOURCE_HPD5:
-+			hpd_id = HPD_SOURCEID5;
-+		break;
-+		case DC_IRQ_SOURCE_HPD6:
-+			hpd_id = HPD_SOURCEID6;
-+		break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+		break;
-+		}
-+
-+		dal_gpio_destroy_irq(&hpd);
-+	}
-+
-+	return hpd_id;
-+}
-+
-+static enum channel_id get_ddc_line(struct dc_link *link)
-+{
-+	struct ddc *ddc;
-+	enum channel_id channel = CHANNEL_ID_UNKNOWN;
-+
-+	ddc = dal_ddc_service_get_ddc_pin(link->ddc);
-+
-+	if (ddc) {
-+		switch (dal_ddc_get_line(ddc)) {
-+		case GPIO_DDC_LINE_DDC1:
-+			channel = CHANNEL_ID_DDC1;
-+			break;
-+		case GPIO_DDC_LINE_DDC2:
-+			channel = CHANNEL_ID_DDC2;
-+			break;
-+		case GPIO_DDC_LINE_DDC3:
-+			channel = CHANNEL_ID_DDC3;
-+			break;
-+		case GPIO_DDC_LINE_DDC4:
-+			channel = CHANNEL_ID_DDC4;
-+			break;
-+		case GPIO_DDC_LINE_DDC5:
-+			channel = CHANNEL_ID_DDC5;
-+			break;
-+		case GPIO_DDC_LINE_DDC6:
-+			channel = CHANNEL_ID_DDC6;
-+			break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			channel = CHANNEL_ID_DDC_VGA;
-+			break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			channel = CHANNEL_ID_I2C_PAD;
-+			break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			break;
-+		}
-+	}
-+
-+	return channel;
-+}
-+
-+static enum transmitter translate_encoder_to_transmitter(
-+	struct graphics_object_id encoder)
-+{
-+	switch (encoder.id) {
-+	case ENCODER_ID_INTERNAL_UNIPHY:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_UNIPHY_A;
-+		case ENUM_ID_2:
-+			return TRANSMITTER_UNIPHY_B;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_INTERNAL_UNIPHY1:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_UNIPHY_C;
-+		case ENUM_ID_2:
-+			return TRANSMITTER_UNIPHY_D;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_INTERNAL_UNIPHY2:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_UNIPHY_E;
-+		case ENUM_ID_2:
-+			return TRANSMITTER_UNIPHY_F;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_INTERNAL_UNIPHY3:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_UNIPHY_G;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_EXTERNAL_NUTMEG:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_NUTMEG_CRT;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	case ENCODER_ID_EXTERNAL_TRAVIS:
-+		switch (encoder.enum_id) {
-+		case ENUM_ID_1:
-+			return TRANSMITTER_TRAVIS_CRT;
-+		case ENUM_ID_2:
-+			return TRANSMITTER_TRAVIS_LCD;
-+		default:
-+			return TRANSMITTER_UNKNOWN;
-+		}
-+	break;
-+	default:
-+		return TRANSMITTER_UNKNOWN;
-+	}
-+}
-+
-+static bool construct(
-+	struct dc_link *link,
-+	const struct link_init_data *init_params)
-+{
-+	uint8_t i;
-+	struct gpio *hpd_gpio = NULL;
-+	struct ddc_service_init_data ddc_service_init_data = { { 0 } };
-+	struct dc_context *dc_ctx = init_params->ctx;
-+	struct encoder_init_data enc_init_data = { 0 };
-+	struct integrated_info info = {{{ 0 }}};
-+	struct dc_bios *bios = init_params->dc->ctx->dc_bios;
-+	const struct dc_vbios_funcs *bp_funcs = bios->funcs;
-+
-+	link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
-+	link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
-+
-+	link->link_status.dpcd_caps = &link->dpcd_caps;
-+
-+	link->dc = init_params->dc;
-+	link->ctx = dc_ctx;
-+	link->link_index = init_params->link_index;
-+
-+	link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
-+
-+	if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
-+		dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d!\n",
-+				__func__, init_params->connector_index);
-+		goto create_fail;
-+	}
-+
-+	hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
-+
-+	if (hpd_gpio != NULL)
-+		link->irq_source_hpd = dal_irq_get_source(hpd_gpio);
-+
-+	switch (link->link_id.id) {
-+	case CONNECTOR_ID_HDMI_TYPE_A:
-+		link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
-+
-+		break;
-+	case CONNECTOR_ID_SINGLE_LINK_DVID:
-+	case CONNECTOR_ID_SINGLE_LINK_DVII:
-+		link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+		break;
-+	case CONNECTOR_ID_DUAL_LINK_DVID:
-+	case CONNECTOR_ID_DUAL_LINK_DVII:
-+		link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
-+		break;
-+	case CONNECTOR_ID_DISPLAY_PORT:
-+		link->connector_signal =	SIGNAL_TYPE_DISPLAY_PORT;
-+
-+		if (hpd_gpio != NULL)
-+			link->irq_source_hpd_rx =
-+					dal_irq_get_rx_source(hpd_gpio);
-+
-+		break;
-+	case CONNECTOR_ID_EDP:
-+		link->connector_signal = SIGNAL_TYPE_EDP;
-+
-+		if (hpd_gpio != NULL) {
-+			link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
-+			link->irq_source_hpd_rx =
-+					dal_irq_get_rx_source(hpd_gpio);
-+		}
-+		break;
-+	default:
-+		dm_logger_write(dc_ctx->logger, LOG_WARNING,
-+			"Unsupported Connector type:%d!\n", link->link_id.id);
-+		goto create_fail;
-+	}
-+
-+	if (hpd_gpio != NULL) {
-+		dal_gpio_destroy_irq(&hpd_gpio);
-+		hpd_gpio = NULL;
-+	}
-+
-+	/* TODO: #DAL3 Implement id to str function.*/
-+	LINK_INFO("Connector[%d] description:"
-+			"signal %d\n",
-+			init_params->connector_index,
-+			link->connector_signal);
-+
-+	ddc_service_init_data.ctx = link->ctx;
-+	ddc_service_init_data.id = link->link_id;
-+	ddc_service_init_data.link = link;
-+	link->ddc = dal_ddc_service_create(&ddc_service_init_data);
-+
-+	if (link->ddc == NULL) {
-+		DC_ERROR("Failed to create ddc_service!\n");
-+		goto ddc_create_fail;
-+	}
-+
-+	link->ddc_hw_inst =
-+		dal_ddc_get_line(
-+			dal_ddc_service_get_ddc_pin(link->ddc));
-+
-+	enc_init_data.ctx = dc_ctx;
-+	bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
-+	enc_init_data.connector = link->link_id;
-+	enc_init_data.channel = get_ddc_line(link);
-+	enc_init_data.hpd_source = get_hpd_line(link);
-+
-+	link->hpd_src = enc_init_data.hpd_source;
-+
-+	enc_init_data.transmitter =
-+			translate_encoder_to_transmitter(enc_init_data.encoder);
-+	link->link_enc = link->dc->res_pool->funcs->link_enc_create(
-+								&enc_init_data);
-+
-+	if( link->link_enc == NULL) {
-+		DC_ERROR("Failed to create link encoder!\n");
-+		goto link_enc_create_fail;
-+	}
-+
-+	link->link_enc_hw_inst = link->link_enc->transmitter;
-+
-+	for (i = 0; i < 4; i++) {
-+		if (BP_RESULT_OK !=
-+				bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
-+			DC_ERROR("Failed to find device tag!\n");
-+			goto device_tag_fail;
-+		}
-+
-+		/* Look for device tag that matches connector signal,
-+		 * CRT for rgb, LCD for other supported signal tyes
-+		 */
-+		if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
-+			continue;
-+		if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
-+			&& link->connector_signal != SIGNAL_TYPE_RGB)
-+			continue;
-+		if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
-+			&& link->connector_signal == SIGNAL_TYPE_RGB)
-+			continue;
-+		break;
-+	}
-+
-+	if (bios->integrated_info)
-+		info = *bios->integrated_info;
-+
-+	/* Look for channel mapping corresponding to connector and device tag */
-+	for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
-+		struct external_display_path *path =
-+			&info.ext_disp_conn_info.path[i];
-+		if (path->device_connector_id.enum_id == link->link_id.enum_id
-+			&& path->device_connector_id.id == link->link_id.id
-+			&& path->device_connector_id.type == link->link_id.type) {
-+
-+			if (link->device_tag.acpi_device != 0
-+				&& path->device_acpi_enum == link->device_tag.acpi_device) {
-+				link->ddi_channel_mapping = path->channel_mapping;
-+				link->chip_caps = path->caps;
-+			} else if (path->device_tag ==
-+					link->device_tag.dev_id.raw_device_tag) {
-+				link->ddi_channel_mapping = path->channel_mapping;
-+				link->chip_caps = path->caps;
-+			}
-+			break;
-+		}
-+	}
-+
-+	/*
-+	 * TODO check if GPIO programmed correctly
-+	 *
-+	 * If GPIO isn't programmed correctly HPD might not rise or drain
-+	 * fast enough, leading to bounces.
-+	 */
-+	program_hpd_filter(link);
-+
-+	return true;
-+device_tag_fail:
-+	link->link_enc->funcs->destroy(&link->link_enc);
-+link_enc_create_fail:
-+	dal_ddc_service_destroy(&link->ddc);
-+ddc_create_fail:
-+create_fail:
-+
-+	if (hpd_gpio != NULL) {
-+		dal_gpio_destroy_irq(&hpd_gpio);
-+	}
-+
-+	return false;
-+}
-+
-+/*******************************************************************************
-+ * Public functions
-+ ******************************************************************************/
-+struct dc_link *link_create(const struct link_init_data *init_params)
-+{
-+	struct dc_link *link =
-+			kzalloc(sizeof(*link), GFP_KERNEL);
-+
-+	if (NULL == link)
-+		goto alloc_fail;
-+
-+	if (false == construct(link, init_params))
-+		goto construct_fail;
-+
-+	return link;
-+
-+construct_fail:
-+	kfree(link);
-+
-+alloc_fail:
-+	return NULL;
-+}
-+
-+void link_destroy(struct dc_link **link)
-+{
-+	destruct(*link);
-+	kfree(*link);
-+	*link = NULL;
-+}
-+
-+static void dpcd_configure_panel_mode(
-+	struct dc_link *link,
-+	enum dp_panel_mode panel_mode)
-+{
-+	union dpcd_edp_config edp_config_set;
-+	bool panel_mode_edp = false;
-+
-+	memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
-+
-+	if (DP_PANEL_MODE_DEFAULT != panel_mode) {
-+
-+		switch (panel_mode) {
-+		case DP_PANEL_MODE_EDP:
-+		case DP_PANEL_MODE_SPECIAL:
-+			panel_mode_edp = true;
-+			break;
-+
-+		default:
-+			break;
-+		}
-+
-+		/*set edp panel mode in receiver*/
-+		core_link_read_dpcd(
-+			link,
-+			DP_EDP_CONFIGURATION_SET,
-+			&edp_config_set.raw,
-+			sizeof(edp_config_set.raw));
-+
-+		if (edp_config_set.bits.PANEL_MODE_EDP
-+			!= panel_mode_edp) {
-+			enum ddc_result result = DDC_RESULT_UNKNOWN;
-+
-+			edp_config_set.bits.PANEL_MODE_EDP =
-+			panel_mode_edp;
-+			result = core_link_write_dpcd(
-+				link,
-+				DP_EDP_CONFIGURATION_SET,
-+				&edp_config_set.raw,
-+				sizeof(edp_config_set.raw));
-+
-+			ASSERT(result == DDC_RESULT_SUCESSFULL);
-+		}
-+	}
-+	dm_logger_write(link->ctx->logger, LOG_DETECTION_DP_CAPS,
-+			"Link: %d eDP panel mode supported: %d "
-+			"eDP panel mode enabled: %d \n",
-+			link->link_index,
-+			link->dpcd_caps.panel_mode_edp,
-+			panel_mode_edp);
-+}
-+
-+static void enable_stream_features(struct pipe_ctx *pipe_ctx)
-+{
-+	struct dc_stream_state *stream = pipe_ctx->stream;
-+	struct dc_link *link = stream->sink->link;
-+	union down_spread_ctrl downspread;
-+
-+	core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
-+			&downspread.raw, sizeof(downspread));
-+
-+	downspread.bits.IGNORE_MSA_TIMING_PARAM =
-+			(stream->ignore_msa_timing_param) ? 1 : 0;
-+
-+	core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
-+			&downspread.raw, sizeof(downspread));
-+}
-+
-+static enum dc_status enable_link_dp(
-+		struct dc_state *state,
-+		struct pipe_ctx *pipe_ctx)
-+{
-+	struct dc_stream_state *stream = pipe_ctx->stream;
-+	enum dc_status status;
-+	bool skip_video_pattern;
-+	struct dc_link *link = stream->sink->link;
-+	struct dc_link_settings link_settings = {0};
-+	enum dp_panel_mode panel_mode;
-+	enum dc_link_rate max_link_rate = LINK_RATE_HIGH2;
-+
-+	/* get link settings for video mode timing */
-+	decide_link_settings(stream, &link_settings);
-+
-+	/* raise clock state for HBR3 if required. Confirmed with HW DCE/DPCS
-+	 * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
-+	 */
-+	if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
-+		max_link_rate = LINK_RATE_HIGH3;
-+
-+	if (link_settings.link_rate == max_link_rate) {
-+		if (state->dis_clk->funcs->set_min_clocks_state) {
-+			if (state->dis_clk->cur_min_clks_state < DM_PP_CLOCKS_STATE_NOMINAL)
-+				state->dis_clk->funcs->set_min_clocks_state(
-+					state->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL);
-+		} else {
-+			uint32_t dp_phyclk_in_khz;
-+			const struct clocks_value clocks_value =
-+					state->dis_clk->cur_clocks_value;
-+
-+			/* 27mhz = 27000000hz= 27000khz */
-+			dp_phyclk_in_khz = link_settings.link_rate * 27000;
-+
-+			if (((clocks_value.max_non_dp_phyclk_in_khz != 0) &&
-+				(dp_phyclk_in_khz > clocks_value.max_non_dp_phyclk_in_khz)) ||
-+				(dp_phyclk_in_khz > clocks_value.max_dp_phyclk_in_khz)) {
-+				state->dis_clk->funcs->apply_clock_voltage_request(
-+						state->dis_clk,
-+						DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
-+						dp_phyclk_in_khz,
-+						false,
-+						true);
-+			}
-+		}
-+	}
-+
-+	dp_enable_link_phy(
-+		link,
-+		pipe_ctx->stream->signal,
-+		pipe_ctx->clock_source->id,
-+		&link_settings);
-+
-+	panel_mode = dp_get_panel_mode(link);
-+	dpcd_configure_panel_mode(link, panel_mode);
-+
-+	skip_video_pattern = true;
-+
-+	if (link_settings.link_rate == LINK_RATE_LOW)
-+			skip_video_pattern = false;
-+
-+	if (perform_link_training_with_retries(
-+			link,
-+			&link_settings,
-+			skip_video_pattern,
-+			LINK_TRAINING_ATTEMPTS)) {
-+		link->cur_link_settings = link_settings;
-+		status = DC_OK;
-+	}
-+	else
-+		status = DC_FAIL_DP_LINK_TRAINING;
-+
-+	enable_stream_features(pipe_ctx);
-+
-+	return status;
-+}
-+
-+static enum dc_status enable_link_dp_mst(
-+		struct dc_state *state,
-+		struct pipe_ctx *pipe_ctx)
-+{
-+	struct dc_link *link = pipe_ctx->stream->sink->link;
-+
-+	/* sink signal type after MST branch is MST. Multiple MST sinks
-+	 * share one link. Link DP PHY is enable or training only once.
-+	 */
-+	if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
-+		return DC_OK;
-+
-+	/* set the sink to MST mode before enabling the link */
-+	dp_enable_mst_on_sink(link, true);
-+
-+	return enable_link_dp(state, pipe_ctx);
-+}
-+
-+static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
-+		enum engine_id eng_id,
-+		struct ext_hdmi_settings *settings)
-+{
-+	bool result = false;
-+	int i = 0;
-+	struct integrated_info *integrated_info =
-+			pipe_ctx->stream->ctx->dc_bios->integrated_info;
-+
-+	if (integrated_info == NULL)
-+		return false;
-+
-+	/*
-+	 * Get retimer settings from sbios for passing SI eye test for DCE11
-+	 * The setting values are varied based on board revision and port id
-+	 * Therefore the setting values of each ports is passed by sbios.
-+	 */
-+
-+	// Check if current bios contains ext Hdmi settings
-+	if (integrated_info->gpu_cap_info & 0x20) {
-+		switch (eng_id) {
-+		case ENGINE_ID_DIGA:
-+			settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
-+			settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
-+			settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
-+			memmove(settings->reg_settings,
-+					integrated_info->dp0_ext_hdmi_reg_settings,
-+					sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
-+			memmove(settings->reg_settings_6g,
-+					integrated_info->dp0_ext_hdmi_6g_reg_settings,
-+					sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGB:
-+			settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
-+			settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
-+			settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
-+			memmove(settings->reg_settings,
-+					integrated_info->dp1_ext_hdmi_reg_settings,
-+					sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
-+			memmove(settings->reg_settings_6g,
-+					integrated_info->dp1_ext_hdmi_6g_reg_settings,
-+					sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGC:
-+			settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
-+			settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
-+			settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
-+			memmove(settings->reg_settings,
-+					integrated_info->dp2_ext_hdmi_reg_settings,
-+					sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
-+			memmove(settings->reg_settings_6g,
-+					integrated_info->dp2_ext_hdmi_6g_reg_settings,
-+					sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
-+			result = true;
-+			break;
-+		case ENGINE_ID_DIGD:
-+			settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
-+			settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
-+			settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
-+			memmove(settings->reg_settings,
-+					integrated_info->dp3_ext_hdmi_reg_settings,
-+					sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
-+			memmove(settings->reg_settings_6g,
-+					integrated_info->dp3_ext_hdmi_6g_reg_settings,
-+					sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
-+			result = true;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+		if (result == true) {
-+			// Validate settings from bios integrated info table
-+			if (settings->slv_addr == 0)
-+				return false;
-+			if (settings->reg_num > 9)
-+				return false;
-+			if (settings->reg_num_6g > 3)
-+				return false;
-+
-+			for (i = 0; i < settings->reg_num; i++) {
-+				if (settings->reg_settings[i].i2c_reg_index > 0x20)
-+					return false;
-+			}
-+
-+			for (i = 0; i < settings->reg_num_6g; i++) {
-+				if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
-+					return false;
-+			}
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+static bool i2c_write(struct pipe_ctx *pipe_ctx,
-+		uint8_t address, uint8_t *buffer, uint32_t length)
-+{
-+	struct i2c_command cmd = {0};
-+	struct i2c_payload payload = {0};
-+
-+	memset(&payload, 0, sizeof(payload));
-+	memset(&cmd, 0, sizeof(cmd));
-+
-+	cmd.number_of_payloads = 1;
-+	cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
-+	cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
-+
-+	payload.address = address;
-+	payload.data = buffer;
-+	payload.length = length;
-+	payload.write = true;
-+	cmd.payloads = &payload;
-+
-+	if (dc_submit_i2c(pipe_ctx->stream->ctx->dc,
-+			pipe_ctx->stream->sink->link->link_index, &cmd))
-+		return true;
-+
-+	return false;
-+}
-+
-+static void write_i2c_retimer_setting(
-+		struct pipe_ctx *pipe_ctx,
-+		bool is_vga_mode,
-+		bool is_over_340mhz,
-+		struct ext_hdmi_settings *settings)
-+{
-+	uint8_t slave_address = (settings->slv_addr >> 1);
-+	uint8_t buffer[2];
-+	const uint8_t apply_rx_tx_change = 0x4;
-+	uint8_t offset = 0xA;
-+	uint8_t value = 0;
-+	int i = 0;
-+	bool i2c_success = false;
-+
-+	memset(&buffer, 0, sizeof(buffer));
-+
-+	/* Start Ext-Hdmi programming*/
-+
-+	for (i = 0; i < settings->reg_num; i++) {
-+		/* Apply 3G settings */
-+		if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
-+
-+			buffer[0] = settings->reg_settings[i].i2c_reg_index;
-+			buffer[1] = settings->reg_settings[i].i2c_reg_val;
-+			i2c_success = i2c_write(pipe_ctx, slave_address,
-+						buffer, sizeof(buffer));
-+
-+			if (!i2c_success)
-+				/* Write failure */
-+				ASSERT(i2c_success);
-+
-+			/* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
-+			 * needs to be set to 1 on every 0xA-0xC write.
-+			 */
-+			if (settings->reg_settings[i].i2c_reg_index == 0xA ||
-+				settings->reg_settings[i].i2c_reg_index == 0xB ||
-+				settings->reg_settings[i].i2c_reg_index == 0xC) {
-+
-+				/* Query current value from offset 0xA */
-+				if (settings->reg_settings[i].i2c_reg_index == 0xA)
-+					value = settings->reg_settings[i].i2c_reg_val;
-+				else {
-+					i2c_success =
-+						dal_ddc_service_query_ddc_data(
-+						pipe_ctx->stream->sink->link->ddc,
-+						slave_address, &offset, 1, &value, 1);
-+					if (!i2c_success)
-+						/* Write failure */
-+						ASSERT(i2c_success);
-+				}
-+
-+				buffer[0] = offset;
-+				/* Set APPLY_RX_TX_CHANGE bit to 1 */
-+				buffer[1] = value | apply_rx_tx_change;
-+				i2c_success = i2c_write(pipe_ctx, slave_address,
-+						buffer, sizeof(buffer));
-+				if (!i2c_success)
-+					/* Write failure */
-+					ASSERT(i2c_success);
-+			}
-+		}
-+	}
-+
-+	/* Apply 3G settings */
-+	if (is_over_340mhz) {
-+		for (i = 0; i < settings->reg_num_6g; i++) {
-+			/* Apply 3G settings */
-+			if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
-+
-+				buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
-+				buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
-+				i2c_success = i2c_write(pipe_ctx, slave_address,
-+							buffer, sizeof(buffer));
-+
-+				if (!i2c_success)
-+					/* Write failure */
-+					ASSERT(i2c_success);
-+
-+				/* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
-+				 * needs to be set to 1 on every 0xA-0xC write.
-+				 */
-+				if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
-+					settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
-+					settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
-+
-+					/* Query current value from offset 0xA */
-+					if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
-+						value = settings->reg_settings_6g[i].i2c_reg_val;
-+					else {
-+						i2c_success =
-+								dal_ddc_service_query_ddc_data(
-+								pipe_ctx->stream->sink->link->ddc,
-+								slave_address, &offset, 1, &value, 1);
-+						if (!i2c_success)
-+							/* Write failure */
-+							ASSERT(i2c_success);
-+					}
-+
-+					buffer[0] = offset;
-+					/* Set APPLY_RX_TX_CHANGE bit to 1 */
-+					buffer[1] = value | apply_rx_tx_change;
-+					i2c_success = i2c_write(pipe_ctx, slave_address,
-+							buffer, sizeof(buffer));
-+					if (!i2c_success)
-+						/* Write failure */
-+						ASSERT(i2c_success);
-+				}
-+			}
-+		}
-+	}
-+
-+	if (is_vga_mode) {
-+		/* Program additional settings if using 640x480 resolution */
-+
-+		/* Write offset 0xFF to 0x01 */
-+		buffer[0] = 0xff;
-+		buffer[1] = 0x01;
-+		i2c_success = i2c_write(pipe_ctx, slave_address,
-+				buffer, sizeof(buffer));
-+		if (!i2c_success)
-+			/* Write failure */
-+			ASSERT(i2c_success);
-+
-+		/* Write offset 0x00 to 0x23 */
-+		buffer[0] = 0x00;
-+		buffer[1] = 0x23;
-+		i2c_success = i2c_write(pipe_ctx, slave_address,
-+				buffer, sizeof(buffer));
-+		if (!i2c_success)
-+			/* Write failure */
-+			ASSERT(i2c_success);
-+
-+		/* Write offset 0xff to 0x00 */
-+		buffer[0] = 0xff;
-+		buffer[1] = 0x00;
-+		i2c_success = i2c_write(pipe_ctx, slave_address,
-+				buffer, sizeof(buffer));
-+		if (!i2c_success)
-+			/* Write failure */
-+			ASSERT(i2c_success);
-+
-+	}
-+}
-+
-+static void write_i2c_default_retimer_setting(
-+		struct pipe_ctx *pipe_ctx,
-+		bool is_vga_mode,
-+		bool is_over_340mhz)
-+{
-+	uint8_t slave_address = (0xBA >> 1);
-+	uint8_t buffer[2];
-+	bool i2c_success = false;
-+
-+	memset(&buffer, 0, sizeof(buffer));
-+
-+	/* Program Slave Address for tuning single integrity */
-+	/* Write offset 0x0A to 0x13 */
-+	buffer[0] = 0x0A;
-+	buffer[1] = 0x13;
-+	i2c_success = i2c_write(pipe_ctx, slave_address,
-+			buffer, sizeof(buffer));
-+	if (!i2c_success)
-+		/* Write failure */
-+		ASSERT(i2c_success);
-+
-+	/* Write offset 0x0A to 0x17 */
-+	buffer[0] = 0x0A;
-+	buffer[1] = 0x17;
-+	i2c_success = i2c_write(pipe_ctx, slave_address,
-+			buffer, sizeof(buffer));
-+	if (!i2c_success)
-+		/* Write failure */
-+		ASSERT(i2c_success);
-+
-+	/* Write offset 0x0B to 0xDA or 0xD8 */
-+	buffer[0] = 0x0B;
-+	buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
-+	i2c_success = i2c_write(pipe_ctx, slave_address,
-+			buffer, sizeof(buffer));
-+	if (!i2c_success)
-+		/* Write failure */
-+		ASSERT(i2c_success);
-+
-+	/* Write offset 0x0A to 0x17 */
-+	buffer[0] = 0x0A;
-+	buffer[1] = 0x17;
-+	i2c_success = i2c_write(pipe_ctx, slave_address,
-+			buffer, sizeof(buffer));
-+	if (!i2c_success)
-+		/* Write failure */
-+		ASSERT(i2c_success);
-+
-+	/* Write offset 0x0C to 0x1D or 0x91 */
-+	buffer[0] = 0x0C;
-+	buffer[1] = is_over_340mhz ? 0x1D : 0x91;
-+	i2c_success = i2c_write(pipe_ctx, slave_address,
-+			buffer, sizeof(buffer));
-+	if (!i2c_success)
-+		/* Write failure */
-+		ASSERT(i2c_success);
-+
-+	/* Write offset 0x0A to 0x17 */
-+	buffer[0] = 0x0A;
-+	buffer[1] = 0x17;
-+	i2c_success = i2c_write(pipe_ctx, slave_address,
-+			buffer, sizeof(buffer));
-+	if (!i2c_success)
-+		/* Write failure */
-+		ASSERT(i2c_success);
-+
-+
-+	if (is_vga_mode) {
-+		/* Program additional settings if using 640x480 resolution */
-+
-+		/* Write offset 0xFF to 0x01 */
-+		buffer[0] = 0xff;
-+		buffer[1] = 0x01;
-+		i2c_success = i2c_write(pipe_ctx, slave_address,
-+				buffer, sizeof(buffer));
-+		if (!i2c_success)
-+			/* Write failure */
-+			ASSERT(i2c_success);
-+
-+		/* Write offset 0x00 to 0x23 */
-+		buffer[0] = 0x00;
-+		buffer[1] = 0x23;
-+		i2c_success = i2c_write(pipe_ctx, slave_address,
-+				buffer, sizeof(buffer));
-+		if (!i2c_success)
-+			/* Write failure */
-+			ASSERT(i2c_success);
-+
-+		/* Write offset 0xff to 0x00 */
-+		buffer[0] = 0xff;
-+		buffer[1] = 0x00;
-+		i2c_success = i2c_write(pipe_ctx, slave_address,
-+				buffer, sizeof(buffer));
-+		if (!i2c_success)
-+			/* Write failure */
-+			ASSERT(i2c_success);
-+	}
-+}
-+
-+static void write_i2c_redriver_setting(
-+		struct pipe_ctx *pipe_ctx,
-+		bool is_over_340mhz)
-+{
-+	uint8_t slave_address = (0xF0 >> 1);
-+	uint8_t buffer[16];
-+	bool i2c_success = false;
-+
-+	memset(&buffer, 0, sizeof(buffer));
-+
-+	// Program Slave Address for tuning single integrity
-+	buffer[3] = 0x4E;
-+	buffer[4] = 0x4E;
-+	buffer[5] = 0x4E;
-+	buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
-+
-+	i2c_success = i2c_write(pipe_ctx, slave_address,
-+					buffer, sizeof(buffer));
-+
-+	if (!i2c_success)
-+		/* Write failure */
-+		ASSERT(i2c_success);
-+}
-+
-+static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
-+{
-+	struct dc_stream_state *stream = pipe_ctx->stream;
-+	struct dc_link *link = stream->sink->link;
-+	enum dc_color_depth display_color_depth;
-+	enum engine_id eng_id;
-+	struct ext_hdmi_settings settings = {0};
-+	bool is_over_340mhz = false;
-+	bool is_vga_mode = (stream->timing.h_addressable == 640)
-+			&& (stream->timing.v_addressable == 480);
-+
-+	if (stream->phy_pix_clk > 340000)
-+		is_over_340mhz = true;
-+
-+	if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
-+		unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &
-+				EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
-+		if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
-+			/* DP159, Retimer settings */
-+			eng_id = pipe_ctx->stream_res.stream_enc->id;
-+
-+			if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
-+				write_i2c_retimer_setting(pipe_ctx,
-+						is_vga_mode, is_over_340mhz, &settings);
-+			} else {
-+				write_i2c_default_retimer_setting(pipe_ctx,
-+						is_vga_mode, is_over_340mhz);
-+			}
-+		} else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
-+			/* PI3EQX1204, Redriver settings */
-+			write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
-+		}
-+	}
-+
-+	if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
-+		dal_ddc_service_write_scdc_data(
-+			stream->sink->link->ddc,
-+			stream->phy_pix_clk,
-+			stream->timing.flags.LTE_340MCSC_SCRAMBLE);
-+
-+	memset(&stream->sink->link->cur_link_settings, 0,
-+			sizeof(struct dc_link_settings));
-+
-+	display_color_depth = stream->timing.display_color_depth;
-+	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
-+		display_color_depth = COLOR_DEPTH_888;
-+
-+	link->link_enc->funcs->enable_tmds_output(
-+			link->link_enc,
-+			pipe_ctx->clock_source->id,
-+			display_color_depth,
-+			pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A,
-+			pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK,
-+			stream->phy_pix_clk);
-+
-+	if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
-+		dal_ddc_service_read_scdc_data(link->ddc);
-+}
-+
-+/****************************enable_link***********************************/
-+static enum dc_status enable_link(
-+		struct dc_state *state,
-+		struct pipe_ctx *pipe_ctx)
-+{
-+	enum dc_status status = DC_ERROR_UNEXPECTED;
-+	switch (pipe_ctx->stream->signal) {
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_EDP:
-+		status = enable_link_dp(state, pipe_ctx);
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		status = enable_link_dp_mst(state, pipe_ctx);
-+		msleep(200);
-+		break;
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		enable_link_hdmi(pipe_ctx);
-+		status = DC_OK;
-+		break;
-+	case SIGNAL_TYPE_VIRTUAL:
-+		status = DC_OK;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (pipe_ctx->stream_res.audio && status == DC_OK) {
-+		/* notify audio driver for audio modes of monitor */
-+		pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
-+
-+		/* un-mute audio */
-+		/* TODO: audio should be per stream rather than per link */
-+		pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
-+			pipe_ctx->stream_res.stream_enc, false);
-+	}
-+
-+	return status;
-+}
-+
-+static void disable_link(struct dc_link *link, enum signal_type signal)
-+{
-+	/*
-+	 * TODO: implement call for dp_set_hw_test_pattern
-+	 * it is needed for compliance testing
-+	 */
-+
-+	/* here we need to specify that encoder output settings
-+	 * need to be calculated as for the set mode,
-+	 * it will lead to querying dynamic link capabilities
-+	 * which should be done before enable output */
-+
-+	if (dc_is_dp_signal(signal)) {
-+		/* SST DP, eDP */
-+		if (dc_is_dp_sst_signal(signal))
-+			dp_disable_link_phy(link, signal);
-+		else
-+			dp_disable_link_phy_mst(link, signal);
-+	} else
-+		link->link_enc->funcs->disable_output(link->link_enc, signal);
-+}
-+
-+bool dp_active_dongle_validate_timing(
-+		const struct dc_crtc_timing *timing,
-+		const struct dc_dongle_caps *dongle_caps)
-+{
-+	unsigned int required_pix_clk = timing->pix_clk_khz;
-+
-+	if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
-+		dongle_caps->extendedCapValid == false)
-+		return true;
-+
-+	/* Check Pixel Encoding */
-+	switch (timing->pixel_encoding) {
-+	case PIXEL_ENCODING_RGB:
-+	case PIXEL_ENCODING_YCBCR444:
-+		break;
-+	case PIXEL_ENCODING_YCBCR422:
-+		if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
-+			return false;
-+		break;
-+	case PIXEL_ENCODING_YCBCR420:
-+		if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
-+			return false;
-+		break;
-+	default:
-+		/* Invalid Pixel Encoding*/
-+		return false;
-+	}
-+
-+
-+	/* Check Color Depth and Pixel Clock */
-+	if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
-+		required_pix_clk /= 2;
-+
-+	switch (timing->display_color_depth) {
-+	case COLOR_DEPTH_666:
-+	case COLOR_DEPTH_888:
-+		/*888 and 666 should always be supported*/
-+		break;
-+	case COLOR_DEPTH_101010:
-+		if (dongle_caps->dp_hdmi_max_bpc < 10)
-+			return false;
-+		required_pix_clk = required_pix_clk * 10 / 8;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		if (dongle_caps->dp_hdmi_max_bpc < 12)
-+			return false;
-+		required_pix_clk = required_pix_clk * 12 / 8;
-+		break;
-+
-+	case COLOR_DEPTH_141414:
-+	case COLOR_DEPTH_161616:
-+	default:
-+		/* These color depths are currently not supported */
-+		return false;
-+	}
-+
-+	if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
-+		return false;
-+
-+	return true;
-+}
-+
-+enum dc_status dc_link_validate_mode_timing(
-+		const struct dc_stream_state *stream,
-+		struct dc_link *link,
-+		const struct dc_crtc_timing *timing)
-+{
-+	uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
-+	struct dc_dongle_caps *dongle_caps = &link->dpcd_caps.dongle_caps;
-+
-+	/* A hack to avoid failing any modes for EDID override feature on
-+	 * topology change such as lower quality cable for DP or different dongle
-+	 */
-+	if (link->remote_sinks[0])
-+		return DC_OK;
-+
-+	/* Passive Dongle */
-+	if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
-+		return DC_EXCEED_DONGLE_CAP;
-+
-+	/* Active Dongle*/
-+	if (!dp_active_dongle_validate_timing(timing, dongle_caps))
-+		return DC_EXCEED_DONGLE_CAP;
-+
-+	switch (stream->signal) {
-+	case SIGNAL_TYPE_EDP:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+		if (!dp_validate_mode_timing(
-+				link,
-+				timing))
-+			return DC_NO_DP_LINK_BANDWIDTH;
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return DC_OK;
-+}
-+
-+
-+bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
-+		uint32_t frame_ramp, const struct dc_stream_state *stream)
-+{
-+	struct dc  *core_dc = link->ctx->dc;
-+	struct abm *abm = core_dc->res_pool->abm;
-+	unsigned int controller_id = 0;
-+	int i;
-+
-+	if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL))
-+		return false;
-+
-+	dm_logger_write(link->ctx->logger, LOG_BACKLIGHT,
-+			"New Backlight level: %d (0x%X)\n", level, level);
-+
-+	if (dc_is_embedded_signal(link->connector_signal)) {
-+		if (stream != NULL) {
-+			for (i = 0; i < MAX_PIPES; i++) {
-+				if (core_dc->current_state->res_ctx.
-+						pipe_ctx[i].stream
-+						== stream)
-+					/* DMCU -1 for all controller id values,
-+					 * therefore +1 here
-+					 */
-+					controller_id =
-+						core_dc->current_state->
-+						res_ctx.pipe_ctx[i].stream_res.tg->inst +
-+						1;
-+			}
-+		}
-+		abm->funcs->set_backlight_level(
-+				abm,
-+				level,
-+				frame_ramp,
-+				controller_id);
-+	}
-+
-+	return true;
-+}
-+
-+bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
-+{
-+	struct dc  *core_dc = link->ctx->dc;
-+	struct dmcu *dmcu = core_dc->res_pool->dmcu;
-+
-+	if (dmcu != NULL && link->psr_enabled)
-+		dmcu->funcs->set_psr_enable(dmcu, enable, wait);
-+
-+	return true;
-+}
-+
-+bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
-+{
-+	struct dc  *core_dc = link->ctx->dc;
-+	struct dmcu *dmcu = core_dc->res_pool->dmcu;
-+
-+	if (dmcu != NULL && link->psr_enabled)
-+		dmcu->funcs->get_psr_state(dmcu, psr_state);
-+
-+	return true;
-+}
-+
-+bool dc_link_setup_psr(struct dc_link *link,
-+		const struct dc_stream_state *stream, struct psr_config *psr_config,
-+		struct psr_context *psr_context)
-+{
-+	struct dc  *core_dc = link->ctx->dc;
-+	struct dmcu *dmcu = core_dc->res_pool->dmcu;
-+	int i;
-+
-+	psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
-+
-+	if (link != NULL &&
-+		dmcu != NULL) {
-+		/* updateSinkPsrDpcdConfig*/
-+		union dpcd_psr_configuration psr_configuration;
-+
-+		memset(&psr_configuration, 0, sizeof(psr_configuration));
-+
-+		psr_configuration.bits.ENABLE                    = 1;
-+		psr_configuration.bits.CRC_VERIFICATION          = 1;
-+		psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
-+				psr_config->psr_frame_capture_indication_req;
-+
-+		/* Check for PSR v2*/
-+		if (psr_config->psr_version == 0x2) {
-+			/* For PSR v2 selective update.
-+			 * Indicates whether sink should start capturing
-+			 * immediately following active scan line,
-+			 * or starting with the 2nd active scan line.
-+			 */
-+			psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
-+			/*For PSR v2, determines whether Sink should generate
-+			 * IRQ_HPD when CRC mismatch is detected.
-+			 */
-+			psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
-+		}
-+
-+		dm_helpers_dp_write_dpcd(
-+			link->ctx,
-+			link,
-+			368,
-+			&psr_configuration.raw,
-+			sizeof(psr_configuration.raw));
-+
-+		psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
-+		psr_context->transmitterId = link->link_enc->transmitter;
-+		psr_context->engineId = link->link_enc->preferred_engine;
-+
-+		for (i = 0; i < MAX_PIPES; i++) {
-+			if (core_dc->current_state->res_ctx.pipe_ctx[i].stream
-+					== stream) {
-+				/* dmcu -1 for all controller id values,
-+				 * therefore +1 here
-+				 */
-+				psr_context->controllerId =
-+					core_dc->current_state->res_ctx.
-+					pipe_ctx[i].stream_res.tg->inst + 1;
-+				break;
-+			}
-+		}
-+
-+		/* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
-+		psr_context->phyType = PHY_TYPE_UNIPHY;
-+		/*PhyId is associated with the transmitter id*/
-+		psr_context->smuPhyId = link->link_enc->transmitter;
-+
-+		psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
-+		psr_context->vsyncRateHz = div64_u64(div64_u64((stream->
-+						timing.pix_clk_khz * 1000),
-+						stream->timing.v_total),
-+						stream->timing.h_total);
-+
-+		psr_context->psrSupportedDisplayConfig = true;
-+		psr_context->psrExitLinkTrainingRequired =
-+			psr_config->psr_exit_link_training_required;
-+		psr_context->sdpTransmitLineNumDeadline =
-+			psr_config->psr_sdp_transmit_line_num_deadline;
-+		psr_context->psrFrameCaptureIndicationReq =
-+			psr_config->psr_frame_capture_indication_req;
-+
-+		psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
-+
-+		psr_context->numberOfControllers =
-+				link->dc->res_pool->res_cap->num_timing_generator;
-+
-+		psr_context->rfb_update_auto_en = true;
-+
-+		/* 2 frames before enter PSR. */
-+		psr_context->timehyst_frames = 2;
-+		/* half a frame
-+		 * (units in 100 lines, i.e. a value of 1 represents 100 lines)
-+		 */
-+		psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
-+		psr_context->aux_repeats = 10;
-+
-+		psr_context->psr_level.u32all = 0;
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+		/*skip power down the single pipe since it blocks the cstate*/
-+		if (ASIC_REV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
-+			psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
-+#endif
-+
-+		/* SMU will perform additional powerdown sequence.
-+		 * For unsupported ASICs, set psr_level flag to skip PSR
-+		 *  static screen notification to SMU.
-+		 *  (Always set for DAL2, did not check ASIC)
-+		 */
-+		psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION = 1;
-+
-+		/* Complete PSR entry before aborting to prevent intermittent
-+		 * freezes on certain eDPs
-+		 */
-+		psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
-+
-+		/* Controls additional delay after remote frame capture before
-+		 * continuing power down, default = 0
-+		 */
-+		psr_context->frame_delay = 0;
-+
-+		link->psr_enabled = true;
-+		dmcu->funcs->setup_psr(dmcu, link, psr_context);
-+		return true;
-+	} else
-+		return false;
-+
-+}
-+
-+const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
-+{
-+	return &link->link_status;
-+}
-+
-+void core_link_resume(struct dc_link *link)
-+{
-+	if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
-+		program_hpd_filter(link);
-+}
-+
-+static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
-+{
-+	struct dc_link_settings *link_settings =
-+			&stream->sink->link->cur_link_settings;
-+	uint32_t link_rate_in_mbps =
-+			link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
-+	struct fixed31_32 mbps = dal_fixed31_32_from_int(
-+			link_rate_in_mbps * link_settings->lane_count);
-+
-+	return dal_fixed31_32_div_int(mbps, 54);
-+}
-+
-+static int get_color_depth(enum dc_color_depth color_depth)
-+{
-+	switch (color_depth) {
-+	case COLOR_DEPTH_666: return 6;
-+	case COLOR_DEPTH_888: return 8;
-+	case COLOR_DEPTH_101010: return 10;
-+	case COLOR_DEPTH_121212: return 12;
-+	case COLOR_DEPTH_141414: return 14;
-+	case COLOR_DEPTH_161616: return 16;
-+	default: return 0;
-+	}
-+}
-+
-+static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
-+{
-+	uint32_t bpc;
-+	uint64_t kbps;
-+	struct fixed31_32 peak_kbps;
-+	uint32_t numerator;
-+	uint32_t denominator;
-+
-+	bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
-+	kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;
-+
-+	/*
-+	 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
-+	 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
-+	 * common multiplier to render an integer PBN for all link rate/lane
-+	 * counts combinations
-+	 * calculate
-+	 * peak_kbps *= (1006/1000)
-+	 * peak_kbps *= (64/54)
-+	 * peak_kbps *= 8    convert to bytes
-+	 */
-+
-+	numerator = 64 * PEAK_FACTOR_X1000;
-+	denominator = 54 * 8 * 1000 * 1000;
-+	kbps *= numerator;
-+	peak_kbps = dal_fixed31_32_from_fraction(kbps, denominator);
-+
-+	return peak_kbps;
-+}
-+
-+static void update_mst_stream_alloc_table(
-+	struct dc_link *link,
-+	struct stream_encoder *stream_enc,
-+	const struct dp_mst_stream_allocation_table *proposed_table)
-+{
-+	struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
-+			{ 0 } };
-+	struct link_mst_stream_allocation *dc_alloc;
-+
-+	int i;
-+	int j;
-+
-+	/* if DRM proposed_table has more than one new payload */
-+	ASSERT(proposed_table->stream_count -
-+			link->mst_stream_alloc_table.stream_count < 2);
-+
-+	/* copy proposed_table to link, add stream encoder */
-+	for (i = 0; i < proposed_table->stream_count; i++) {
-+
-+		for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
-+			dc_alloc =
-+			&link->mst_stream_alloc_table.stream_allocations[j];
-+
-+			if (dc_alloc->vcp_id ==
-+				proposed_table->stream_allocations[i].vcp_id) {
-+
-+				work_table[i] = *dc_alloc;
-+				break; /* exit j loop */
-+			}
-+		}
-+
-+		/* new vcp_id */
-+		if (j == link->mst_stream_alloc_table.stream_count) {
-+			work_table[i].vcp_id =
-+				proposed_table->stream_allocations[i].vcp_id;
-+			work_table[i].slot_count =
-+				proposed_table->stream_allocations[i].slot_count;
-+			work_table[i].stream_enc = stream_enc;
-+		}
-+	}
-+
-+	/* update link->mst_stream_alloc_table with work_table */
-+	link->mst_stream_alloc_table.stream_count =
-+			proposed_table->stream_count;
-+	for (i = 0; i < MAX_CONTROLLER_NUM; i++)
-+		link->mst_stream_alloc_table.stream_allocations[i] =
-+				work_table[i];
-+}
-+
-+/* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
-+ * because stream_encoder is not exposed to dm
-+ */
-+static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
-+{
-+	struct dc_stream_state *stream = pipe_ctx->stream;
-+	struct dc_link *link = stream->sink->link;
-+	struct link_encoder *link_encoder = link->link_enc;
-+	struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
-+	struct dp_mst_stream_allocation_table proposed_table = {0};
-+	struct fixed31_32 avg_time_slots_per_mtp;
-+	struct fixed31_32 pbn;
-+	struct fixed31_32 pbn_per_slot;
-+	uint8_t i;
-+
-+	/* enable_link_dp_mst already check link->enabled_stream_count
-+	 * and stream is in link->stream[]. This is called during set mode,
-+	 * stream_enc is available.
-+	 */
-+
-+	/* get calculate VC payload for stream: stream_alloc */
-+	if (dm_helpers_dp_mst_write_payload_allocation_table(
-+		stream->ctx,
-+		stream,
-+		&proposed_table,
-+		true)) {
-+		update_mst_stream_alloc_table(
-+					link, pipe_ctx->stream_res.stream_enc, &proposed_table);
-+	}
-+	else
-+		dm_logger_write(link->ctx->logger, LOG_WARNING,
-+				"Failed to update"
-+				"MST allocation table for"
-+				"pipe idx:%d\n",
-+				pipe_ctx->pipe_idx);
-+
-+	dm_logger_write(link->ctx->logger, LOG_MST,
-+			"%s  "
-+			"stream_count: %d: \n ",
-+			__func__,
-+			link->mst_stream_alloc_table.stream_count);
-+
-+	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
-+		dm_logger_write(link->ctx->logger, LOG_MST,
-+		"stream_enc[%d]: 0x%x      "
-+		"stream[%d].vcp_id: %d      "
-+		"stream[%d].slot_count: %d\n",
-+		i,
-+		link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
-+		i,
-+		link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
-+		i,
-+		link->mst_stream_alloc_table.stream_allocations[i].slot_count);
-+	}
-+
-+	ASSERT(proposed_table.stream_count > 0);
-+
-+	/* program DP source TX for payload */
-+	link_encoder->funcs->update_mst_stream_allocation_table(
-+		link_encoder,
-+		&link->mst_stream_alloc_table);
-+
-+	/* send down message */
-+	dm_helpers_dp_mst_poll_for_allocation_change_trigger(
-+			stream->ctx,
-+			stream);
-+
-+	dm_helpers_dp_mst_send_payload_allocation(
-+			stream->ctx,
-+			stream,
-+			true);
-+
-+	/* slot X.Y for only current stream */
-+	pbn_per_slot = get_pbn_per_slot(stream);
-+	pbn = get_pbn_from_timing(pipe_ctx);
-+	avg_time_slots_per_mtp = dal_fixed31_32_div(pbn, pbn_per_slot);
-+
-+	stream_encoder->funcs->set_mst_bandwidth(
-+		stream_encoder,
-+		avg_time_slots_per_mtp);
-+
-+	return DC_OK;
-+
-+}
-+
-+static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
-+{
-+	struct dc_stream_state *stream = pipe_ctx->stream;
-+	struct dc_link *link = stream->sink->link;
-+	struct link_encoder *link_encoder = link->link_enc;
-+	struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
-+	struct dp_mst_stream_allocation_table proposed_table = {0};
-+	struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
-+	uint8_t i;
-+	bool mst_mode = (link->type == dc_connection_mst_branch);
-+
-+	/* deallocate_mst_payload is called before disable link. When mode or
-+	 * disable/enable monitor, new stream is created which is not in link
-+	 * stream[] yet. For this, payload is not allocated yet, so de-alloc
-+	 * should not done. For new mode set, map_resources will get engine
-+	 * for new stream, so stream_enc->id should be validated until here.
-+	 */
-+
-+	/* slot X.Y */
-+	stream_encoder->funcs->set_mst_bandwidth(
-+		stream_encoder,
-+		avg_time_slots_per_mtp);
-+
-+	/* TODO: which component is responsible for remove payload table? */
-+	if (mst_mode) {
-+		if (dm_helpers_dp_mst_write_payload_allocation_table(
-+				stream->ctx,
-+				stream,
-+				&proposed_table,
-+				false)) {
-+
-+			update_mst_stream_alloc_table(
-+				link, pipe_ctx->stream_res.stream_enc, &proposed_table);
-+		}
-+		else {
-+				dm_logger_write(link->ctx->logger, LOG_WARNING,
-+						"Failed to update"
-+						"MST allocation table for"
-+						"pipe idx:%d\n",
-+						pipe_ctx->pipe_idx);
-+		}
-+	}
-+
-+	dm_logger_write(link->ctx->logger, LOG_MST,
-+			"%s"
-+			"stream_count: %d: ",
-+			__func__,
-+			link->mst_stream_alloc_table.stream_count);
-+
-+	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
-+		dm_logger_write(link->ctx->logger, LOG_MST,
-+		"stream_enc[%d]: 0x%x      "
-+		"stream[%d].vcp_id: %d      "
-+		"stream[%d].slot_count: %d\n",
-+		i,
-+		link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
-+		i,
-+		link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
-+		i,
-+		link->mst_stream_alloc_table.stream_allocations[i].slot_count);
-+	}
-+
-+	link_encoder->funcs->update_mst_stream_allocation_table(
-+		link_encoder,
-+		&link->mst_stream_alloc_table);
-+
-+	if (mst_mode) {
-+		dm_helpers_dp_mst_poll_for_allocation_change_trigger(
-+			stream->ctx,
-+			stream);
-+
-+		dm_helpers_dp_mst_send_payload_allocation(
-+			stream->ctx,
-+			stream,
-+			false);
-+	}
-+
-+	return DC_OK;
-+}
-+
-+void core_link_enable_stream(
-+		struct dc_state *state,
-+		struct pipe_ctx *pipe_ctx)
-+{
-+	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
-+
-+	enum dc_status status = enable_link(state, pipe_ctx);
-+
-+	if (status != DC_OK) {
-+			dm_logger_write(pipe_ctx->stream->ctx->logger,
-+			LOG_WARNING, "enabling link %u failed: %d\n",
-+			pipe_ctx->stream->sink->link->link_index,
-+			status);
-+
-+			/* Abort stream enable *unless* the failure was due to
-+			 * DP link training - some DP monitors will recover and
-+			 * show the stream anyway. But MST displays can't proceed
-+			 * without link training.
-+			 */
-+			if (status != DC_FAIL_DP_LINK_TRAINING ||
-+					pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
-+				BREAK_TO_DEBUGGER();
-+				return;
-+			}
-+	}
-+
-+	/* turn off otg test pattern if enable */
-+	pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
-+			CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
-+			COLOR_DEPTH_UNDEFINED);
-+
-+	core_dc->hwss.enable_stream(pipe_ctx);
-+
-+	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
-+		allocate_mst_payload(pipe_ctx);
-+
-+	if (dc_is_dp_signal(pipe_ctx->stream->signal))
-+		core_dc->hwss.unblank_stream(pipe_ctx,
-+			&pipe_ctx->stream->sink->link->cur_link_settings);
-+}
-+
-+void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
-+{
-+	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
-+
-+	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
-+		deallocate_mst_payload(pipe_ctx);
-+
-+	core_dc->hwss.disable_stream(pipe_ctx, option);
-+
-+	disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
-+}
-+
-+void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
-+{
-+	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
-+
-+	if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
-+		return;
-+
-+	core_dc->hwss.set_avmute(pipe_ctx, enable);
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c.0130~	2017-12-14 06:39:58.406903561 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c	2017-12-14 06:39:58.406903561 +0100
-@@ -0,0 +1,775 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dm_helpers.h"
-+#include "gpio_service_interface.h"
-+#include "include/ddc_service_types.h"
-+#include "include/grph_object_id.h"
-+#include "include/dpcd_defs.h"
-+#include "include/logger_interface.h"
-+#include "include/vector.h"
-+#include "core_types.h"
-+#include "dc_link_ddc.h"
-+
-+#define AUX_POWER_UP_WA_DELAY 500
-+#define I2C_OVER_AUX_DEFER_WA_DELAY 70
-+
-+/* CV smart dongle slave address for retrieving supported HDTV modes*/
-+#define CV_SMART_DONGLE_ADDRESS 0x20
-+/* DVI-HDMI dongle slave address for retrieving dongle signature*/
-+#define DVI_HDMI_DONGLE_ADDRESS 0x68
-+static const int8_t dvi_hdmi_dongle_signature_str[] = "6140063500G";
-+struct dvi_hdmi_dongle_signature_data {
-+	int8_t vendor[3];/* "AMD" */
-+	uint8_t version[2];
-+	uint8_t size;
-+	int8_t id[11];/* "6140063500G"*/
-+};
-+/* DP-HDMI dongle slave address for retrieving dongle signature*/
-+#define DP_HDMI_DONGLE_ADDRESS 0x40
-+static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";
-+#define DP_HDMI_DONGLE_SIGNATURE_EOT 0x04
-+
-+struct dp_hdmi_dongle_signature_data {
-+	int8_t id[15];/* "DP-HDMI ADAPTOR"*/
-+	uint8_t eot;/* end of transmition '\x4' */
-+};
-+
-+/* SCDC Address defines (HDMI 2.0)*/
-+#define HDMI_SCDC_WRITE_UPDATE_0_ARRAY 3
-+#define HDMI_SCDC_ADDRESS  0x54
-+#define HDMI_SCDC_SINK_VERSION 0x01
-+#define HDMI_SCDC_SOURCE_VERSION 0x02
-+#define HDMI_SCDC_UPDATE_0 0x10
-+#define HDMI_SCDC_TMDS_CONFIG 0x20
-+#define HDMI_SCDC_SCRAMBLER_STATUS 0x21
-+#define HDMI_SCDC_CONFIG_0 0x30
-+#define HDMI_SCDC_STATUS_FLAGS 0x40
-+#define HDMI_SCDC_ERR_DETECT 0x50
-+#define HDMI_SCDC_TEST_CONFIG 0xC0
-+
-+union hdmi_scdc_update_read_data {
-+	uint8_t byte[2];
-+	struct {
-+		uint8_t STATUS_UPDATE:1;
-+		uint8_t CED_UPDATE:1;
-+		uint8_t RR_TEST:1;
-+		uint8_t RESERVED:5;
-+		uint8_t RESERVED2:8;
-+	} fields;
-+};
-+
-+union hdmi_scdc_status_flags_data {
-+	uint8_t byte[2];
-+	struct {
-+		uint8_t CLOCK_DETECTED:1;
-+		uint8_t CH0_LOCKED:1;
-+		uint8_t CH1_LOCKED:1;
-+		uint8_t CH2_LOCKED:1;
-+		uint8_t RESERVED:4;
-+		uint8_t RESERVED2:8;
-+	} fields;
-+};
-+
-+union hdmi_scdc_ced_data {
-+	uint8_t byte[7];
-+	struct {
-+		uint8_t CH0_8LOW:8;
-+		uint8_t CH0_7HIGH:7;
-+		uint8_t CH0_VALID:1;
-+		uint8_t CH1_8LOW:8;
-+		uint8_t CH1_7HIGH:7;
-+		uint8_t CH1_VALID:1;
-+		uint8_t CH2_8LOW:8;
-+		uint8_t CH2_7HIGH:7;
-+		uint8_t CH2_VALID:1;
-+		uint8_t CHECKSUM:8;
-+	} fields;
-+};
-+
-+union hdmi_scdc_test_config_Data {
-+	uint8_t byte;
-+	struct {
-+		uint8_t TEST_READ_REQUEST_DELAY:7;
-+		uint8_t TEST_READ_REQUEST: 1;
-+	} fields;
-+};
-+
-+struct i2c_payloads {
-+	struct vector payloads;
-+};
-+
-+struct aux_payloads {
-+	struct vector payloads;
-+};
-+
-+static struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_t count)
-+{
-+	struct i2c_payloads *payloads;
-+
-+	payloads = kzalloc(sizeof(struct i2c_payloads), GFP_KERNEL);
-+
-+	if (!payloads)
-+		return NULL;
-+
-+	if (dal_vector_construct(
-+		&payloads->payloads, ctx, count, sizeof(struct i2c_payload)))
-+		return payloads;
-+
-+	kfree(payloads);
-+	return NULL;
-+
-+}
-+
-+static struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p)
-+{
-+	return (struct i2c_payload *)p->payloads.container;
-+}
-+
-+static uint32_t dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p)
-+{
-+	return p->payloads.count;
-+}
-+
-+static void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p)
-+{
-+	if (!p || !*p)
-+		return;
-+	dal_vector_destruct(&(*p)->payloads);
-+	kfree(*p);
-+	*p = NULL;
-+
-+}
-+
-+static struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_t count)
-+{
-+	struct aux_payloads *payloads;
-+
-+	payloads = kzalloc(sizeof(struct aux_payloads), GFP_KERNEL);
-+
-+	if (!payloads)
-+		return NULL;
-+
-+	if (dal_vector_construct(
-+		&payloads->payloads, ctx, count, sizeof(struct aux_payload)))
-+		return payloads;
-+
-+	kfree(payloads);
-+	return NULL;
-+}
-+
-+static struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p)
-+{
-+	return (struct aux_payload *)p->payloads.container;
-+}
-+
-+static uint32_t  dal_ddc_aux_payloads_get_count(struct aux_payloads *p)
-+{
-+	return p->payloads.count;
-+}
-+
-+static void dal_ddc_aux_payloads_destroy(struct aux_payloads **p)
-+{
-+	if (!p || !*p)
-+		return;
-+
-+	dal_vector_destruct(&(*p)->payloads);
-+	kfree(*p);
-+	*p = NULL;
-+}
-+
-+#define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
-+
-+void dal_ddc_i2c_payloads_add(
-+	struct i2c_payloads *payloads,
-+	uint32_t address,
-+	uint32_t len,
-+	uint8_t *data,
-+	bool write)
-+{
-+	uint32_t payload_size = EDID_SEGMENT_SIZE;
-+	uint32_t pos;
-+
-+	for (pos = 0; pos < len; pos += payload_size) {
-+		struct i2c_payload payload = {
-+			.write = write,
-+			.address = address,
-+			.length = DDC_MIN(payload_size, len - pos),
-+			.data = data + pos };
-+		dal_vector_append(&payloads->payloads, &payload);
-+	}
-+
-+}
-+
-+void dal_ddc_aux_payloads_add(
-+	struct aux_payloads *payloads,
-+	uint32_t address,
-+	uint32_t len,
-+	uint8_t *data,
-+	bool write)
-+{
-+	uint32_t payload_size = DEFAULT_AUX_MAX_DATA_SIZE;
-+	uint32_t pos;
-+
-+	for (pos = 0; pos < len; pos += payload_size) {
-+		struct aux_payload payload = {
-+			.i2c_over_aux = true,
-+			.write = write,
-+			.address = address,
-+			.length = DDC_MIN(payload_size, len - pos),
-+			.data = data + pos };
-+		dal_vector_append(&payloads->payloads, &payload);
-+	}
-+}
-+
-+static void construct(
-+	struct ddc_service *ddc_service,
-+	struct ddc_service_init_data *init_data)
-+{
-+	enum connector_id connector_id =
-+		dal_graphics_object_id_get_connector_id(init_data->id);
-+
-+	struct gpio_service *gpio_service = init_data->ctx->gpio_service;
-+	struct graphics_object_i2c_info i2c_info;
-+	struct gpio_ddc_hw_info hw_info;
-+	struct dc_bios *dcb = init_data->ctx->dc_bios;
-+
-+	ddc_service->link = init_data->link;
-+	ddc_service->ctx = init_data->ctx;
-+
-+	if (BP_RESULT_OK != dcb->funcs->get_i2c_info(dcb, init_data->id, &i2c_info)) {
-+		ddc_service->ddc_pin = NULL;
-+	} else {
-+		hw_info.ddc_channel = i2c_info.i2c_line;
-+		hw_info.hw_supported = i2c_info.i2c_hw_assist;
-+
-+		ddc_service->ddc_pin = dal_gpio_create_ddc(
-+			gpio_service,
-+			i2c_info.gpio_info.clk_a_register_index,
-+			1 << i2c_info.gpio_info.clk_a_shift,
-+			&hw_info);
-+	}
-+
-+	ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
-+	ddc_service->flags.FORCE_READ_REPEATED_START = false;
-+	ddc_service->flags.EDID_STRESS_READ = false;
-+
-+	ddc_service->flags.IS_INTERNAL_DISPLAY =
-+		connector_id == CONNECTOR_ID_EDP ||
-+		connector_id == CONNECTOR_ID_LVDS;
-+
-+	ddc_service->wa.raw = 0;
-+}
-+
-+struct ddc_service *dal_ddc_service_create(
-+	struct ddc_service_init_data *init_data)
-+{
-+	struct ddc_service *ddc_service;
-+
-+	ddc_service = kzalloc(sizeof(struct ddc_service), GFP_KERNEL);
-+
-+	if (!ddc_service)
-+		return NULL;
-+
-+	construct(ddc_service, init_data);
-+	return ddc_service;
-+}
-+
-+static void destruct(struct ddc_service *ddc)
-+{
-+	if (ddc->ddc_pin)
-+		dal_gpio_destroy_ddc(&ddc->ddc_pin);
-+}
-+
-+void dal_ddc_service_destroy(struct ddc_service **ddc)
-+{
-+	if (!ddc || !*ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+	destruct(*ddc);
-+	kfree(*ddc);
-+	*ddc = NULL;
-+}
-+
-+enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc)
-+{
-+	return DDC_SERVICE_TYPE_CONNECTOR;
-+}
-+
-+void dal_ddc_service_set_transaction_type(
-+	struct ddc_service *ddc,
-+	enum ddc_transaction_type type)
-+{
-+	ddc->transaction_type = type;
-+}
-+
-+bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc)
-+{
-+	switch (ddc->transaction_type) {
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER:
-+		return true;
-+	default:
-+		break;
-+	}
-+	return false;
-+}
-+
-+void ddc_service_set_dongle_type(struct ddc_service *ddc,
-+		enum display_dongle_type dongle_type)
-+{
-+	ddc->dongle_type = dongle_type;
-+}
-+
-+static uint32_t defer_delay_converter_wa(
-+	struct ddc_service *ddc,
-+	uint32_t defer_delay)
-+{
-+	struct dc_link *link = ddc->link;
-+
-+	if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_4 &&
-+		!memcmp(link->dpcd_caps.branch_dev_name,
-+			DP_DVI_CONVERTER_ID_4,
-+			sizeof(link->dpcd_caps.branch_dev_name)))
-+		return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
-+			defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY;
-+
-+	return defer_delay;
-+}
-+
-+#define DP_TRANSLATOR_DELAY 5
-+
-+uint32_t get_defer_delay(struct ddc_service *ddc)
-+{
-+	uint32_t defer_delay = 0;
-+
-+	switch (ddc->transaction_type) {
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
-+		if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) ||
-+			(DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) ||
-+			(DISPLAY_DONGLE_DP_HDMI_CONVERTER ==
-+				ddc->dongle_type)) {
-+
-+			defer_delay = DP_TRANSLATOR_DELAY;
-+
-+			defer_delay =
-+				defer_delay_converter_wa(ddc, defer_delay);
-+
-+		} else /*sink has a delay different from an Active Converter*/
-+			defer_delay = 0;
-+		break;
-+	case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
-+		defer_delay = DP_TRANSLATOR_DELAY;
-+		break;
-+	default:
-+		break;
-+	}
-+	return defer_delay;
-+}
-+
-+static bool i2c_read(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	uint8_t *buffer,
-+	uint32_t len)
-+{
-+	uint8_t offs_data = 0;
-+	struct i2c_payload payloads[2] = {
-+		{
-+		.write = true,
-+		.address = address,
-+		.length = 1,
-+		.data = &offs_data },
-+		{
-+		.write = false,
-+		.address = address,
-+		.length = len,
-+		.data = buffer } };
-+
-+	struct i2c_command command = {
-+		.payloads = payloads,
-+		.number_of_payloads = 2,
-+		.engine = DDC_I2C_COMMAND_ENGINE,
-+		.speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
-+
-+	return dm_helpers_submit_i2c(
-+			ddc->ctx,
-+			ddc->link,
-+			&command);
-+}
-+
-+void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
-+	struct ddc_service *ddc,
-+	struct display_sink_capability *sink_cap)
-+{
-+	uint8_t i;
-+	bool is_valid_hdmi_signature;
-+	enum display_dongle_type *dongle = &sink_cap->dongle_type;
-+	uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
-+	bool is_type2_dongle = false;
-+	struct dp_hdmi_dongle_signature_data *dongle_signature;
-+
-+	/* Assume we have no valid DP passive dongle connected */
-+	*dongle = DISPLAY_DONGLE_NONE;
-+	sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
-+
-+	/* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
-+	if (!i2c_read(
-+		ddc,
-+		DP_HDMI_DONGLE_ADDRESS,
-+		type2_dongle_buf,
-+		sizeof(type2_dongle_buf))) {
-+		*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
-+		sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
-+
-+		CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
-+				"DP-DVI passive dongle %dMhz: ",
-+				DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
-+		return;
-+	}
-+
-+	/* Check if Type 2 dongle.*/
-+	if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
-+		is_type2_dongle = true;
-+
-+	dongle_signature =
-+		(struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
-+
-+	is_valid_hdmi_signature = true;
-+
-+	/* Check EOT */
-+	if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
-+		is_valid_hdmi_signature = false;
-+	}
-+
-+	/* Check signature */
-+	for (i = 0; i < sizeof(dongle_signature->id); ++i) {
-+		/* If its not the right signature,
-+		 * skip mismatch in subversion byte.*/
-+		if (dongle_signature->id[i] !=
-+			dp_hdmi_dongle_signature_str[i] && i != 3) {
-+
-+			if (is_type2_dongle) {
-+				is_valid_hdmi_signature = false;
-+				break;
-+			}
-+
-+		}
-+	}
-+
-+	if (is_type2_dongle) {
-+		uint32_t max_tmds_clk =
-+			type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
-+
-+		max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
-+
-+		if (0 == max_tmds_clk ||
-+				max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
-+				max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
-+			*dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
-+
-+			CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
-+					sizeof(type2_dongle_buf),
-+					"DP-DVI passive dongle %dMhz: ",
-+					DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
-+		} else {
-+			if (is_valid_hdmi_signature == true) {
-+				*dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
-+
-+				CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
-+						sizeof(type2_dongle_buf),
-+						"Type 2 DP-HDMI passive dongle %dMhz: ",
-+						max_tmds_clk);
-+			} else {
-+				*dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
-+
-+				CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
-+						sizeof(type2_dongle_buf),
-+						"Type 2 DP-HDMI passive dongle (no signature) %dMhz: ",
-+						max_tmds_clk);
-+
-+			}
-+
-+			/* Multiply by 1000 to convert to kHz. */
-+			sink_cap->max_hdmi_pixel_clock =
-+				max_tmds_clk * 1000;
-+		}
-+
-+	} else {
-+		if (is_valid_hdmi_signature == true) {
-+			*dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
-+
-+			CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
-+					sizeof(type2_dongle_buf),
-+					"Type 1 DP-HDMI passive dongle %dMhz: ",
-+					sink_cap->max_hdmi_pixel_clock / 1000);
-+		} else {
-+			*dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
-+
-+			CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
-+					sizeof(type2_dongle_buf),
-+					"Type 1 DP-HDMI passive dongle (no signature) %dMhz: ",
-+					sink_cap->max_hdmi_pixel_clock / 1000);
-+		}
-+	}
-+
-+	return;
-+}
-+
-+enum {
-+	DP_SINK_CAP_SIZE =
-+		DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
-+};
-+
-+bool dal_ddc_service_query_ddc_data(
-+	struct ddc_service *ddc,
-+	uint32_t address,
-+	uint8_t *write_buf,
-+	uint32_t write_size,
-+	uint8_t *read_buf,
-+	uint32_t read_size)
-+{
-+	bool ret;
-+	uint32_t payload_size =
-+		dal_ddc_service_is_in_aux_transaction_mode(ddc) ?
-+			DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE;
-+
-+	uint32_t write_payloads =
-+		(write_size + payload_size - 1) / payload_size;
-+
-+	uint32_t read_payloads =
-+		(read_size + payload_size - 1) / payload_size;
-+
-+	uint32_t payloads_num = write_payloads + read_payloads;
-+
-+	if (write_size > EDID_SEGMENT_SIZE || read_size > EDID_SEGMENT_SIZE)
-+		return false;
-+
-+	/*TODO: len of payload data for i2c and aux is uint8!!!!,
-+	 *  but we want to read 256 over i2c!!!!*/
-+	if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
-+
-+		struct aux_payloads *payloads =
-+			dal_ddc_aux_payloads_create(ddc->ctx, payloads_num);
-+
-+		struct aux_command command = {
-+			.payloads = dal_ddc_aux_payloads_get(payloads),
-+			.number_of_payloads = 0,
-+			.defer_delay = get_defer_delay(ddc),
-+			.max_defer_write_retry = 0 };
-+
-+		dal_ddc_aux_payloads_add(
-+			payloads, address, write_size, write_buf, true);
-+
-+		dal_ddc_aux_payloads_add(
-+			payloads, address, read_size, read_buf, false);
-+
-+		command.number_of_payloads =
-+			dal_ddc_aux_payloads_get_count(payloads);
-+
-+		ret = dal_i2caux_submit_aux_command(
-+				ddc->ctx->i2caux,
-+				ddc->ddc_pin,
-+				&command);
-+
-+		dal_ddc_aux_payloads_destroy(&payloads);
-+
-+	} else {
-+		struct i2c_payloads *payloads =
-+			dal_ddc_i2c_payloads_create(ddc->ctx, payloads_num);
-+
-+		struct i2c_command command = {
-+			.payloads = dal_ddc_i2c_payloads_get(payloads),
-+			.number_of_payloads = 0,
-+			.engine = DDC_I2C_COMMAND_ENGINE,
-+			.speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
-+
-+		dal_ddc_i2c_payloads_add(
-+			payloads, address, write_size, write_buf, true);
-+
-+		dal_ddc_i2c_payloads_add(
-+			payloads, address, read_size, read_buf, false);
-+
-+		command.number_of_payloads =
-+			dal_ddc_i2c_payloads_get_count(payloads);
-+
-+		ret = dm_helpers_submit_i2c(
-+				ddc->ctx,
-+				ddc->link,
-+				&command);
-+
-+		dal_ddc_i2c_payloads_destroy(&payloads);
-+	}
-+
-+	return ret;
-+}
-+
-+enum ddc_result dal_ddc_service_read_dpcd_data(
-+	struct ddc_service *ddc,
-+	bool i2c,
-+	enum i2c_mot_mode mot,
-+	uint32_t address,
-+	uint8_t *data,
-+	uint32_t len)
-+{
-+	struct aux_payload read_payload = {
-+		.i2c_over_aux = i2c,
-+		.write = false,
-+		.address = address,
-+		.length = len,
-+		.data = data,
-+	};
-+	struct aux_command command = {
-+		.payloads = &read_payload,
-+		.number_of_payloads = 1,
-+		.defer_delay = 0,
-+		.max_defer_write_retry = 0,
-+		.mot = mot
-+	};
-+
-+	if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
-+		BREAK_TO_DEBUGGER();
-+		return DDC_RESULT_FAILED_INVALID_OPERATION;
-+	}
-+
-+	if (dal_i2caux_submit_aux_command(
-+		ddc->ctx->i2caux,
-+		ddc->ddc_pin,
-+		&command))
-+		return DDC_RESULT_SUCESSFULL;
-+
-+	return DDC_RESULT_FAILED_OPERATION;
-+}
-+
-+enum ddc_result dal_ddc_service_write_dpcd_data(
-+	struct ddc_service *ddc,
-+	bool i2c,
-+	enum i2c_mot_mode mot,
-+	uint32_t address,
-+	const uint8_t *data,
-+	uint32_t len)
-+{
-+	struct aux_payload write_payload = {
-+		.i2c_over_aux = i2c,
-+		.write = true,
-+		.address = address,
-+		.length = len,
-+		.data = (uint8_t *)data,
-+	};
-+	struct aux_command command = {
-+		.payloads = &write_payload,
-+		.number_of_payloads = 1,
-+		.defer_delay = 0,
-+		.max_defer_write_retry = 0,
-+		.mot = mot
-+	};
-+
-+	if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
-+		BREAK_TO_DEBUGGER();
-+		return DDC_RESULT_FAILED_INVALID_OPERATION;
-+	}
-+
-+	if (dal_i2caux_submit_aux_command(
-+		ddc->ctx->i2caux,
-+		ddc->ddc_pin,
-+		&command))
-+		return DDC_RESULT_SUCESSFULL;
-+
-+	return DDC_RESULT_FAILED_OPERATION;
-+}
-+
-+/*test only function*/
-+void dal_ddc_service_set_ddc_pin(
-+	struct ddc_service *ddc_service,
-+	struct ddc *ddc)
-+{
-+	ddc_service->ddc_pin = ddc;
-+}
-+
-+struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service)
-+{
-+	return ddc_service->ddc_pin;
-+}
-+
-+void dal_ddc_service_write_scdc_data(struct ddc_service *ddc_service,
-+		uint32_t pix_clk,
-+		bool lte_340_scramble)
-+{
-+	bool over_340_mhz = pix_clk > 340000 ? 1 : 0;
-+	uint8_t slave_address = HDMI_SCDC_ADDRESS;
-+	uint8_t offset = HDMI_SCDC_SINK_VERSION;
-+	uint8_t sink_version = 0;
-+	uint8_t write_buffer[2] = {0};
-+	/*Lower than 340 Scramble bit from SCDC caps*/
-+
-+	dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
-+			sizeof(offset), &sink_version, sizeof(sink_version));
-+	if (sink_version == 1) {
-+		/*Source Version = 1*/
-+		write_buffer[0] = HDMI_SCDC_SOURCE_VERSION;
-+		write_buffer[1] = 1;
-+		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
-+				write_buffer, sizeof(write_buffer), NULL, 0);
-+		/*Read Request from SCDC caps*/
-+	}
-+	write_buffer[0] = HDMI_SCDC_TMDS_CONFIG;
-+
-+	if (over_340_mhz) {
-+		write_buffer[1] = 3;
-+	} else if (lte_340_scramble) {
-+		write_buffer[1] = 1;
-+	} else {
-+		write_buffer[1] = 0;
-+	}
-+	dal_ddc_service_query_ddc_data(ddc_service, slave_address, write_buffer,
-+			sizeof(write_buffer), NULL, 0);
-+}
-+
-+void dal_ddc_service_read_scdc_data(struct ddc_service *ddc_service)
-+{
-+	uint8_t slave_address = HDMI_SCDC_ADDRESS;
-+	uint8_t offset = HDMI_SCDC_TMDS_CONFIG;
-+	uint8_t tmds_config = 0;
-+
-+	dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
-+			sizeof(offset), &tmds_config, sizeof(tmds_config));
-+	if (tmds_config & 0x1) {
-+		union hdmi_scdc_status_flags_data status_data = { {0} };
-+		uint8_t scramble_status = 0;
-+
-+		offset = HDMI_SCDC_SCRAMBLER_STATUS;
-+		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
-+				&offset, sizeof(offset), &scramble_status,
-+				sizeof(scramble_status));
-+		offset = HDMI_SCDC_STATUS_FLAGS;
-+		dal_ddc_service_query_ddc_data(ddc_service, slave_address,
-+				&offset, sizeof(offset), status_data.byte,
-+				sizeof(status_data.byte));
-+	}
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c.0130~	2017-12-14 06:39:58.407903562 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c	2017-12-14 06:39:58.407903562 +0100
-@@ -0,0 +1,2603 @@
-+/* Copyright 2015 Advanced Micro Devices, Inc. */
-+#include "dm_services.h"
-+#include "dc.h"
-+#include "dc_link_dp.h"
-+#include "dm_helpers.h"
-+
-+#include "inc/core_types.h"
-+#include "link_hwss.h"
-+#include "dc_link_ddc.h"
-+#include "core_status.h"
-+#include "dpcd_defs.h"
-+
-+#include "resource.h"
-+
-+/* maximum pre emphasis level allowed for each voltage swing level*/
-+static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
-+		PRE_EMPHASIS_LEVEL3,
-+		PRE_EMPHASIS_LEVEL2,
-+		PRE_EMPHASIS_LEVEL1,
-+		PRE_EMPHASIS_DISABLED };
-+
-+enum {
-+	POST_LT_ADJ_REQ_LIMIT = 6,
-+	POST_LT_ADJ_REQ_TIMEOUT = 200
-+};
-+
-+enum {
-+	LINK_TRAINING_MAX_RETRY_COUNT = 5,
-+	/* to avoid infinite loop where-in the receiver
-+	 * switches between different VS
-+	 */
-+	LINK_TRAINING_MAX_CR_RETRY = 100
-+};
-+
-+static bool decide_fallback_link_setting(
-+		struct dc_link_settings initial_link_settings,
-+		struct dc_link_settings *current_link_setting,
-+		enum link_training_result training_result);
-+static struct dc_link_settings get_common_supported_link_settings (
-+		struct dc_link_settings link_setting_a,
-+		struct dc_link_settings link_setting_b);
-+
-+static void wait_for_training_aux_rd_interval(
-+	struct dc_link *link,
-+	uint32_t default_wait_in_micro_secs)
-+{
-+	union training_aux_rd_interval training_rd_interval;
-+
-+	/* overwrite the delay if rev > 1.1*/
-+	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
-+		/* DP 1.2 or later - retrieve delay through
-+		 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
-+		core_link_read_dpcd(
-+			link,
-+			DP_TRAINING_AUX_RD_INTERVAL,
-+			(uint8_t *)&training_rd_interval,
-+			sizeof(training_rd_interval));
-+
-+		if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
-+			default_wait_in_micro_secs =
-+				training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
-+	}
-+
-+	udelay(default_wait_in_micro_secs);
-+
-+	dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
-+		"%s:\n wait = %d\n",
-+		__func__,
-+		default_wait_in_micro_secs);
-+}
-+
-+static void dpcd_set_training_pattern(
-+	struct dc_link *link,
-+	union dpcd_training_pattern dpcd_pattern)
-+{
-+	core_link_write_dpcd(
-+		link,
-+		DP_TRAINING_PATTERN_SET,
-+		&dpcd_pattern.raw,
-+		1);
-+
-+	dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
-+		"%s\n %x pattern = %x\n",
-+		__func__,
-+		DP_TRAINING_PATTERN_SET,
-+		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
-+}
-+
-+static void dpcd_set_link_settings(
-+	struct dc_link *link,
-+	const struct link_training_settings *lt_settings)
-+{
-+	uint8_t rate = (uint8_t)
-+	(lt_settings->link_settings.link_rate);
-+
-+	union down_spread_ctrl downspread = {{0}};
-+	union lane_count_set lane_count_set = {{0}};
-+	uint8_t link_set_buffer[2];
-+
-+	downspread.raw = (uint8_t)
-+	(lt_settings->link_settings.link_spread);
-+
-+	lane_count_set.bits.LANE_COUNT_SET =
-+	lt_settings->link_settings.lane_count;
-+
-+	lane_count_set.bits.ENHANCED_FRAMING = 1;
-+
-+	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
-+		link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
-+
-+	link_set_buffer[0] = rate;
-+	link_set_buffer[1] = lane_count_set.raw;
-+
-+	core_link_write_dpcd(link, DP_LINK_BW_SET,
-+	link_set_buffer, 2);
-+	core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
-+	&downspread.raw, sizeof(downspread));
-+
-+	dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
-+		"%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
-+		__func__,
-+		DP_LINK_BW_SET,
-+		lt_settings->link_settings.link_rate,
-+		DP_LANE_COUNT_SET,
-+		lt_settings->link_settings.lane_count,
-+		DP_DOWNSPREAD_CTRL,
-+		lt_settings->link_settings.link_spread);
-+
-+}
-+
-+static enum dpcd_training_patterns
-+	hw_training_pattern_to_dpcd_training_pattern(
-+	struct dc_link *link,
-+	enum hw_dp_training_pattern pattern)
-+{
-+	enum dpcd_training_patterns dpcd_tr_pattern =
-+	DPCD_TRAINING_PATTERN_VIDEOIDLE;
-+
-+	switch (pattern) {
-+	case HW_DP_TRAINING_PATTERN_1:
-+		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
-+		break;
-+	case HW_DP_TRAINING_PATTERN_2:
-+		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
-+		break;
-+	case HW_DP_TRAINING_PATTERN_3:
-+		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
-+		break;
-+	case HW_DP_TRAINING_PATTERN_4:
-+		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
-+		break;
-+	default:
-+		ASSERT(0);
-+		dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
-+			"%s: Invalid HW Training pattern: %d\n",
-+			__func__, pattern);
-+		break;
-+	}
-+
-+	return dpcd_tr_pattern;
-+
-+}
-+
-+static void dpcd_set_lt_pattern_and_lane_settings(
-+	struct dc_link *link,
-+	const struct link_training_settings *lt_settings,
-+	enum hw_dp_training_pattern pattern)
-+{
-+	union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
-+	const uint32_t dpcd_base_lt_offset =
-+	DP_TRAINING_PATTERN_SET;
-+	uint8_t dpcd_lt_buffer[5] = {0};
-+	union dpcd_training_pattern dpcd_pattern = {{0}};
-+	uint32_t lane;
-+	uint32_t size_in_bytes;
-+	bool edp_workaround = false; /* TODO link_prop.INTERNAL */
-+
-+	/*****************************************************************
-+	* DpcdAddress_TrainingPatternSet
-+	*****************************************************************/
-+	dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
-+		hw_training_pattern_to_dpcd_training_pattern(link, pattern);
-+
-+	dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
-+		= dpcd_pattern.raw;
-+
-+	dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
-+		"%s\n %x pattern = %x\n",
-+		__func__,
-+		DP_TRAINING_PATTERN_SET,
-+		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
-+
-+	/*****************************************************************
-+	* DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
-+	*****************************************************************/
-+	for (lane = 0; lane <
-+		(uint32_t)(lt_settings->link_settings.lane_count); lane++) {
-+
-+		dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
-+		(uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
-+		dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
-+		(uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
-+
-+		dpcd_lane[lane].bits.MAX_SWING_REACHED =
-+		(lt_settings->lane_settings[lane].VOLTAGE_SWING ==
-+		VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
-+		dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
-+		(lt_settings->lane_settings[lane].PRE_EMPHASIS ==
-+		PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
-+	}
-+
-+	/* concatinate everything into one buffer*/
-+
-+	size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
-+
-+	 // 0x00103 - 0x00102
-+	memmove(
-+		&dpcd_lt_buffer[DP_TRAINING_LANE0_SET - dpcd_base_lt_offset],
-+		dpcd_lane,
-+		size_in_bytes);
-+
-+	dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
-+		"%s:\n %x VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
-+		__func__,
-+		DP_TRAINING_LANE0_SET,
-+		dpcd_lane[0].bits.VOLTAGE_SWING_SET,
-+		dpcd_lane[0].bits.PRE_EMPHASIS_SET,
-+		dpcd_lane[0].bits.MAX_SWING_REACHED,
-+		dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
-+
-+	if (edp_workaround) {
-+		/* for eDP write in 2 parts because the 5-byte burst is
-+		* causing issues on some eDP panels (EPR#366724)
-+		*/
-+		core_link_write_dpcd(
-+			link,
-+			DP_TRAINING_PATTERN_SET,
-+			&dpcd_pattern.raw,
-+			sizeof(dpcd_pattern.raw) );
-+
-+		core_link_write_dpcd(
-+			link,
-+			DP_TRAINING_LANE0_SET,
-+			(uint8_t *)(dpcd_lane),
-+			size_in_bytes);
-+
-+		} else
-+		/* write it all in (1 + number-of-lanes)-byte burst*/
-+			core_link_write_dpcd(
-+				link,
-+				dpcd_base_lt_offset,
-+				dpcd_lt_buffer,
-+				size_in_bytes + sizeof(dpcd_pattern.raw) );
-+
-+	link->cur_lane_setting = lt_settings->lane_settings[0];
-+}
-+
-+static bool is_cr_done(enum dc_lane_count ln_count,
-+	union lane_status *dpcd_lane_status)
-+{
-+	bool done = true;
-+	uint32_t lane;
-+	/*LANEx_CR_DONE bits All 1's?*/
-+	for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
-+		if (!dpcd_lane_status[lane].bits.CR_DONE_0)
-+			done = false;
-+	}
-+	return done;
-+
-+}
-+
-+static bool is_ch_eq_done(enum dc_lane_count ln_count,
-+	union lane_status *dpcd_lane_status,
-+	union lane_align_status_updated *lane_status_updated)
-+{
-+	bool done = true;
-+	uint32_t lane;
-+	if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
-+		done = false;
-+	else {
-+		for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
-+			if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
-+				!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
-+				done = false;
-+		}
-+	}
-+	return done;
-+
-+}
-+
-+static void update_drive_settings(
-+		struct link_training_settings *dest,
-+		struct link_training_settings src)
-+{
-+	uint32_t lane;
-+	for (lane = 0; lane < src.link_settings.lane_count; lane++) {
-+		dest->lane_settings[lane].VOLTAGE_SWING =
-+			src.lane_settings[lane].VOLTAGE_SWING;
-+		dest->lane_settings[lane].PRE_EMPHASIS =
-+			src.lane_settings[lane].PRE_EMPHASIS;
-+		dest->lane_settings[lane].POST_CURSOR2 =
-+			src.lane_settings[lane].POST_CURSOR2;
-+	}
-+}
-+
-+static uint8_t get_nibble_at_index(const uint8_t *buf,
-+	uint32_t index)
-+{
-+	uint8_t nibble;
-+	nibble = buf[index / 2];
-+
-+	if (index % 2)
-+		nibble >>= 4;
-+	else
-+		nibble &= 0x0F;
-+
-+	return nibble;
-+}
-+
-+static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
-+	enum dc_voltage_swing voltage)
-+{
-+	enum dc_pre_emphasis pre_emphasis;
-+	pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
-+
-+	if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
-+		pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
-+
-+	return pre_emphasis;
-+
-+}
-+
-+static void find_max_drive_settings(
-+	const struct link_training_settings *link_training_setting,
-+	struct link_training_settings *max_lt_setting)
-+{
-+	uint32_t lane;
-+	struct dc_lane_settings max_requested;
-+
-+	max_requested.VOLTAGE_SWING =
-+		link_training_setting->
-+		lane_settings[0].VOLTAGE_SWING;
-+	max_requested.PRE_EMPHASIS =
-+		link_training_setting->
-+		lane_settings[0].PRE_EMPHASIS;
-+	/*max_requested.postCursor2 =
-+	 * link_training_setting->laneSettings[0].postCursor2;*/
-+
-+	/* Determine what the maximum of the requested settings are*/
-+	for (lane = 1; lane < link_training_setting->link_settings.lane_count;
-+			lane++) {
-+		if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
-+			max_requested.VOLTAGE_SWING)
-+
-+			max_requested.VOLTAGE_SWING =
-+			link_training_setting->
-+			lane_settings[lane].VOLTAGE_SWING;
-+
-+		if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
-+				max_requested.PRE_EMPHASIS)
-+			max_requested.PRE_EMPHASIS =
-+			link_training_setting->
-+			lane_settings[lane].PRE_EMPHASIS;
-+
-+		/*
-+		if (link_training_setting->laneSettings[lane].postCursor2 >
-+		 max_requested.postCursor2)
-+		{
-+		max_requested.postCursor2 =
-+		link_training_setting->laneSettings[lane].postCursor2;
-+		}
-+		*/
-+	}
-+
-+	/* make sure the requested settings are
-+	 * not higher than maximum settings*/
-+	if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
-+		max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
-+
-+	if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
-+		max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
-+	/*
-+	if (max_requested.postCursor2 > PostCursor2_MaxLevel)
-+	max_requested.postCursor2 = PostCursor2_MaxLevel;
-+	*/
-+
-+	/* make sure the pre-emphasis matches the voltage swing*/
-+	if (max_requested.PRE_EMPHASIS >
-+		get_max_pre_emphasis_for_voltage_swing(
-+			max_requested.VOLTAGE_SWING))
-+		max_requested.PRE_EMPHASIS =
-+		get_max_pre_emphasis_for_voltage_swing(
-+			max_requested.VOLTAGE_SWING);
-+
-+	/*
-+	 * Post Cursor2 levels are completely independent from
-+	 * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
-+	 * can only be applied to each allowable combination of voltage
-+	 * swing and pre-emphasis levels */
-+	 /* if ( max_requested.postCursor2 >
-+	  *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
-+	  *  max_requested.postCursor2 =
-+	  *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
-+	  */
-+
-+	max_lt_setting->link_settings.link_rate =
-+		link_training_setting->link_settings.link_rate;
-+	max_lt_setting->link_settings.lane_count =
-+	link_training_setting->link_settings.lane_count;
-+	max_lt_setting->link_settings.link_spread =
-+		link_training_setting->link_settings.link_spread;
-+
-+	for (lane = 0; lane <
-+		link_training_setting->link_settings.lane_count;
-+		lane++) {
-+		max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
-+			max_requested.VOLTAGE_SWING;
-+		max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
-+			max_requested.PRE_EMPHASIS;
-+		/*max_lt_setting->laneSettings[lane].postCursor2 =
-+		 * max_requested.postCursor2;
-+		 */
-+	}
-+
-+}
-+
-+static void get_lane_status_and_drive_settings(
-+	struct dc_link *link,
-+	const struct link_training_settings *link_training_setting,
-+	union lane_status *ln_status,
-+	union lane_align_status_updated *ln_status_updated,
-+	struct link_training_settings *req_settings)
-+{
-+	uint8_t dpcd_buf[6] = {0};
-+	union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {{{0}}};
-+	struct link_training_settings request_settings = {{0}};
-+	uint32_t lane;
-+
-+	memset(req_settings, '\0', sizeof(struct link_training_settings));
-+
-+	core_link_read_dpcd(
-+		link,
-+		DP_LANE0_1_STATUS,
-+		(uint8_t *)(dpcd_buf),
-+		sizeof(dpcd_buf));
-+
-+	for (lane = 0; lane <
-+		(uint32_t)(link_training_setting->link_settings.lane_count);
-+		lane++) {
-+
-+		ln_status[lane].raw =
-+			get_nibble_at_index(&dpcd_buf[0], lane);
-+		dpcd_lane_adjust[lane].raw =
-+			get_nibble_at_index(&dpcd_buf[4], lane);
-+	}
-+
-+	ln_status_updated->raw = dpcd_buf[2];
-+
-+	dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
-+		"%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
-+		__func__,
-+		DP_LANE0_1_STATUS, dpcd_buf[0],
-+		DP_LANE2_3_STATUS, dpcd_buf[1]);
-+
-+	dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
-+		"%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
-+		__func__,
-+		DP_ADJUST_REQUEST_LANE0_1,
-+		dpcd_buf[4],
-+		DP_ADJUST_REQUEST_LANE2_3,
-+		dpcd_buf[5]);
-+
-+	/*copy to req_settings*/
-+	request_settings.link_settings.lane_count =
-+		link_training_setting->link_settings.lane_count;
-+	request_settings.link_settings.link_rate =
-+		link_training_setting->link_settings.link_rate;
-+	request_settings.link_settings.link_spread =
-+		link_training_setting->link_settings.link_spread;
-+
-+	for (lane = 0; lane <
-+		(uint32_t)(link_training_setting->link_settings.lane_count);
-+		lane++) {
-+
-+		request_settings.lane_settings[lane].VOLTAGE_SWING =
-+			(enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
-+				VOLTAGE_SWING_LANE);
-+		request_settings.lane_settings[lane].PRE_EMPHASIS =
-+			(enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
-+				PRE_EMPHASIS_LANE);
-+	}
-+
-+	/*Note: for postcursor2, read adjusted
-+	 * postcursor2 settings from*/
-+	/*DpcdAddress_AdjustRequestPostCursor2 =
-+	 *0x020C (not implemented yet)*/
-+
-+	/* we find the maximum of the requested settings across all lanes*/
-+	/* and set this maximum for all lanes*/
-+	find_max_drive_settings(&request_settings, req_settings);
-+
-+	/* if post cursor 2 is needed in the future,
-+	 * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
-+	 */
-+
-+}
-+
-+static void dpcd_set_lane_settings(
-+	struct dc_link *link,
-+	const struct link_training_settings *link_training_setting)
-+{
-+	union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
-+	uint32_t lane;
-+
-+	for (lane = 0; lane <
-+		(uint32_t)(link_training_setting->
-+		link_settings.lane_count);
-+		lane++) {
-+		dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
-+			(uint8_t)(link_training_setting->
-+			lane_settings[lane].VOLTAGE_SWING);
-+		dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
-+			(uint8_t)(link_training_setting->
-+			lane_settings[lane].PRE_EMPHASIS);
-+		dpcd_lane[lane].bits.MAX_SWING_REACHED =
-+			(link_training_setting->
-+			lane_settings[lane].VOLTAGE_SWING ==
-+			VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
-+		dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
-+			(link_training_setting->
-+			lane_settings[lane].PRE_EMPHASIS ==
-+			PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
-+	}
-+
-+	core_link_write_dpcd(link,
-+		DP_TRAINING_LANE0_SET,
-+		(uint8_t *)(dpcd_lane),
-+		link_training_setting->link_settings.lane_count);
-+
-+	/*
-+	if (LTSettings.link.rate == LinkRate_High2)
-+	{
-+		DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
-+		for ( uint32_t lane = 0;
-+		lane < lane_count_DPMax; lane++)
-+		{
-+			dpcd_lane2[lane].bits.post_cursor2_set =
-+			static_cast<unsigned char>(
-+			LTSettings.laneSettings[lane].postCursor2);
-+			dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
-+		}
-+		m_pDpcdAccessSrv->WriteDpcdData(
-+		DpcdAddress_Lane0Set2,
-+		reinterpret_cast<unsigned char*>(dpcd_lane2),
-+		LTSettings.link.lanes);
-+	}
-+	*/
-+
-+	dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
-+		"%s\n %x VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
-+		__func__,
-+		DP_TRAINING_LANE0_SET,
-+		dpcd_lane[0].bits.VOLTAGE_SWING_SET,
-+		dpcd_lane[0].bits.PRE_EMPHASIS_SET,
-+		dpcd_lane[0].bits.MAX_SWING_REACHED,
-+		dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
-+
-+	link->cur_lane_setting = link_training_setting->lane_settings[0];
-+
-+}
-+
-+static bool is_max_vs_reached(
-+	const struct link_training_settings *lt_settings)
-+{
-+	uint32_t lane;
-+	for (lane = 0; lane <
-+		(uint32_t)(lt_settings->link_settings.lane_count);
-+		lane++) {
-+		if (lt_settings->lane_settings[lane].VOLTAGE_SWING
-+			== VOLTAGE_SWING_MAX_LEVEL)
-+			return true;
-+	}
-+	return false;
-+
-+}
-+
-+void dc_link_dp_set_drive_settings(
-+	struct dc_link *link,
-+	struct link_training_settings *lt_settings)
-+{
-+	/* program ASIC PHY settings*/
-+	dp_set_hw_lane_settings(link, lt_settings);
-+
-+	/* Notify DP sink the PHY settings from source */
-+	dpcd_set_lane_settings(link, lt_settings);
-+}
-+
-+static bool perform_post_lt_adj_req_sequence(
-+	struct dc_link *link,
-+	struct link_training_settings *lt_settings)
-+{
-+	enum dc_lane_count lane_count =
-+	lt_settings->link_settings.lane_count;
-+
-+	uint32_t adj_req_count;
-+	uint32_t adj_req_timer;
-+	bool req_drv_setting_changed;
-+	uint32_t lane;
-+
-+	req_drv_setting_changed = false;
-+	for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
-+	adj_req_count++) {
-+
-+		req_drv_setting_changed = false;
-+
-+		for (adj_req_timer = 0;
-+			adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
-+			adj_req_timer++) {
-+
-+			struct link_training_settings req_settings;
-+			union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
-+			union lane_align_status_updated
-+				dpcd_lane_status_updated;
-+
-+			get_lane_status_and_drive_settings(
-+			link,
-+			lt_settings,
-+			dpcd_lane_status,
-+			&dpcd_lane_status_updated,
-+			&req_settings);
-+
-+			if (dpcd_lane_status_updated.bits.
-+					POST_LT_ADJ_REQ_IN_PROGRESS == 0)
-+				return true;
-+
-+			if (!is_cr_done(lane_count, dpcd_lane_status))
-+				return false;
-+
-+			if (!is_ch_eq_done(
-+				lane_count,
-+				dpcd_lane_status,
-+				&dpcd_lane_status_updated))
-+				return false;
-+
-+			for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
-+
-+				if (lt_settings->
-+				lane_settings[lane].VOLTAGE_SWING !=
-+				req_settings.lane_settings[lane].
-+				VOLTAGE_SWING ||
-+				lt_settings->lane_settings[lane].PRE_EMPHASIS !=
-+				req_settings.lane_settings[lane].PRE_EMPHASIS) {
-+
-+					req_drv_setting_changed = true;
-+					break;
-+				}
-+			}
-+
-+			if (req_drv_setting_changed) {
-+				update_drive_settings(
-+					lt_settings,req_settings);
-+
-+				dc_link_dp_set_drive_settings(link,
-+						lt_settings);
-+				break;
-+			}
-+
-+			msleep(1);
-+		}
-+
-+		if (!req_drv_setting_changed) {
-+			dm_logger_write(link->ctx->logger, LOG_WARNING,
-+				"%s: Post Link Training Adjust Request Timed out\n",
-+				__func__);
-+
-+			ASSERT(0);
-+			return true;
-+		}
-+	}
-+	dm_logger_write(link->ctx->logger, LOG_WARNING,
-+		"%s: Post Link Training Adjust Request limit reached\n",
-+		__func__);
-+
-+	ASSERT(0);
-+	return true;
-+
-+}
-+
-+static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
-+{
-+	enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
-+	struct encoder_feature_support *features = &link->link_enc->features;
-+	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
-+
-+	if (features->flags.bits.IS_TPS3_CAPABLE)
-+		highest_tp = HW_DP_TRAINING_PATTERN_3;
-+
-+	if (features->flags.bits.IS_TPS4_CAPABLE)
-+		highest_tp = HW_DP_TRAINING_PATTERN_4;
-+
-+	if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
-+		highest_tp >= HW_DP_TRAINING_PATTERN_4)
-+		return HW_DP_TRAINING_PATTERN_4;
-+
-+	if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
-+		highest_tp >= HW_DP_TRAINING_PATTERN_3)
-+		return HW_DP_TRAINING_PATTERN_3;
-+
-+	return HW_DP_TRAINING_PATTERN_2;
-+}
-+
-+static enum link_training_result perform_channel_equalization_sequence(
-+	struct dc_link *link,
-+	struct link_training_settings *lt_settings)
-+{
-+	struct link_training_settings req_settings;
-+	enum hw_dp_training_pattern hw_tr_pattern;
-+	uint32_t retries_ch_eq;
-+	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
-+	union lane_align_status_updated dpcd_lane_status_updated = {{0}};
-+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};;
-+
-+	hw_tr_pattern = get_supported_tp(link);
-+
-+	dp_set_hw_training_pattern(link, hw_tr_pattern);
-+
-+	for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
-+		retries_ch_eq++) {
-+
-+		dp_set_hw_lane_settings(link, lt_settings);
-+
-+		/* 2. update DPCD*/
-+		if (!retries_ch_eq)
-+			/* EPR #361076 - write as a 5-byte burst,
-+			 * but only for the 1-st iteration*/
-+			dpcd_set_lt_pattern_and_lane_settings(
-+				link,
-+				lt_settings,
-+				hw_tr_pattern);
-+		else
-+			dpcd_set_lane_settings(link, lt_settings);
-+
-+		/* 3. wait for receiver to lock-on*/
-+		wait_for_training_aux_rd_interval(link, 400);
-+
-+		/* 4. Read lane status and requested
-+		 * drive settings as set by the sink*/
-+
-+		get_lane_status_and_drive_settings(
-+			link,
-+			lt_settings,
-+			dpcd_lane_status,
-+			&dpcd_lane_status_updated,
-+			&req_settings);
-+
-+		/* 5. check CR done*/
-+		if (!is_cr_done(lane_count, dpcd_lane_status))
-+			return LINK_TRAINING_EQ_FAIL_CR;
-+
-+		/* 6. check CHEQ done*/
-+		if (is_ch_eq_done(lane_count,
-+			dpcd_lane_status,
-+			&dpcd_lane_status_updated))
-+			return LINK_TRAINING_SUCCESS;
-+
-+		/* 7. update VS/PE/PC2 in lt_settings*/
-+		update_drive_settings(lt_settings, req_settings);
-+	}
-+
-+	return LINK_TRAINING_EQ_FAIL_EQ;
-+
-+}
-+
-+static bool perform_clock_recovery_sequence(
-+	struct dc_link *link,
-+	struct link_training_settings *lt_settings)
-+{
-+	uint32_t retries_cr;
-+	uint32_t retry_count;
-+	uint32_t lane;
-+	struct link_training_settings req_settings;
-+	enum dc_lane_count lane_count =
-+	lt_settings->link_settings.lane_count;
-+	enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1;
-+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
-+	union lane_align_status_updated dpcd_lane_status_updated;
-+
-+	retries_cr = 0;
-+	retry_count = 0;
-+	/* initial drive setting (VS/PE/PC2)*/
-+	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
-+		lt_settings->lane_settings[lane].VOLTAGE_SWING =
-+		VOLTAGE_SWING_LEVEL0;
-+		lt_settings->lane_settings[lane].PRE_EMPHASIS =
-+		PRE_EMPHASIS_DISABLED;
-+		lt_settings->lane_settings[lane].POST_CURSOR2 =
-+		POST_CURSOR2_DISABLED;
-+	}
-+
-+	dp_set_hw_training_pattern(link, hw_tr_pattern);
-+
-+	/* najeeb - The synaptics MST hub can put the LT in
-+	* infinite loop by switching the VS
-+	*/
-+	/* between level 0 and level 1 continuously, here
-+	* we try for CR lock for LinkTrainingMaxCRRetry count*/
-+	while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
-+	(retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
-+
-+		memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
-+		memset(&dpcd_lane_status_updated, '\0',
-+		sizeof(dpcd_lane_status_updated));
-+
-+		/* 1. call HWSS to set lane settings*/
-+		dp_set_hw_lane_settings(
-+				link,
-+				lt_settings);
-+
-+		/* 2. update DPCD of the receiver*/
-+		if (!retries_cr)
-+			/* EPR #361076 - write as a 5-byte burst,
-+			 * but only for the 1-st iteration.*/
-+			dpcd_set_lt_pattern_and_lane_settings(
-+					link,
-+					lt_settings,
-+					hw_tr_pattern);
-+		else
-+			dpcd_set_lane_settings(
-+					link,
-+					lt_settings);
-+
-+		/* 3. wait receiver to lock-on*/
-+		wait_for_training_aux_rd_interval(
-+				link,
-+				100);
-+
-+		/* 4. Read lane status and requested drive
-+		* settings as set by the sink
-+		*/
-+		get_lane_status_and_drive_settings(
-+				link,
-+				lt_settings,
-+				dpcd_lane_status,
-+				&dpcd_lane_status_updated,
-+				&req_settings);
-+
-+		/* 5. check CR done*/
-+		if (is_cr_done(lane_count, dpcd_lane_status))
-+			return true;
-+
-+		/* 6. max VS reached*/
-+		if (is_max_vs_reached(lt_settings))
-+			return false;
-+
-+		/* 7. same voltage*/
-+		/* Note: VS same for all lanes,
-+		* so comparing first lane is sufficient*/
-+		if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
-+			req_settings.lane_settings[0].VOLTAGE_SWING)
-+			retries_cr++;
-+		else
-+			retries_cr = 0;
-+
-+		/* 8. update VS/PE/PC2 in lt_settings*/
-+		update_drive_settings(lt_settings, req_settings);
-+
-+		retry_count++;
-+	}
-+
-+	if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
-+		ASSERT(0);
-+		dm_logger_write(link->ctx->logger, LOG_ERROR,
-+			"%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
-+			__func__,
-+			LINK_TRAINING_MAX_CR_RETRY);
-+
-+	}
-+
-+	return false;
-+}
-+
-+static inline bool perform_link_training_int(
-+	struct dc_link *link,
-+	struct link_training_settings *lt_settings,
-+	bool status)
-+{
-+	union lane_count_set lane_count_set = { {0} };
-+	union dpcd_training_pattern dpcd_pattern = { {0} };
-+
-+	/* 3. set training not in progress*/
-+	dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
-+	dpcd_set_training_pattern(link, dpcd_pattern);
-+
-+	/* 4. mainlink output idle pattern*/
-+	dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
-+
-+	/*
-+	 * 5. post training adjust if required
-+	 * If the upstream DPTX and downstream DPRX both support TPS4,
-+	 * TPS4 must be used instead of POST_LT_ADJ_REQ.
-+	 */
-+	if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
-+			get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
-+		return status;
-+
-+	if (status &&
-+		perform_post_lt_adj_req_sequence(link, lt_settings) == false)
-+		status = false;
-+
-+	lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
-+	lane_count_set.bits.ENHANCED_FRAMING = 1;
-+	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
-+
-+	core_link_write_dpcd(
-+		link,
-+		DP_LANE_COUNT_SET,
-+		&lane_count_set.raw,
-+		sizeof(lane_count_set));
-+
-+	return status;
-+}
-+
-+enum link_training_result dc_link_dp_perform_link_training(
-+	struct dc_link *link,
-+	const struct dc_link_settings *link_setting,
-+	bool skip_video_pattern)
-+{
-+	enum link_training_result status = LINK_TRAINING_SUCCESS;
-+
-+	char *link_rate = "Unknown";
-+	struct link_training_settings lt_settings;
-+
-+	memset(&lt_settings, '\0', sizeof(lt_settings));
-+
-+	lt_settings.link_settings.link_rate = link_setting->link_rate;
-+	lt_settings.link_settings.lane_count = link_setting->lane_count;
-+
-+	/*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
-+
-+	/* TODO hard coded to SS for now
-+	 * lt_settings.link_settings.link_spread =
-+	 * dal_display_path_is_ss_supported(
-+	 * path_mode->display_path) ?
-+	 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
-+	 * LINK_SPREAD_DISABLED;
-+	 */
-+	lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
-+
-+	/* 1. set link rate, lane count and spread*/
-+	dpcd_set_link_settings(link, &lt_settings);
-+
-+	/* 2. perform link training (set link training done
-+	 *  to false is done as well)*/
-+	if (!perform_clock_recovery_sequence(link, &lt_settings)) {
-+		status = LINK_TRAINING_CR_FAIL;
-+	} else {
-+		status = perform_channel_equalization_sequence(link,
-+				&lt_settings);
-+	}
-+
-+	if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
-+		if (!perform_link_training_int(link,
-+				&lt_settings,
-+				status == LINK_TRAINING_SUCCESS)) {
-+			/* the next link training setting in this case
-+			 * would be the same as CR failure case.
-+			 */
-+			status = LINK_TRAINING_CR_FAIL;
-+		}
-+	}
-+
-+	/* 6. print status message*/
-+	switch (lt_settings.link_settings.link_rate) {
-+
-+	case LINK_RATE_LOW:
-+		link_rate = "RBR";
-+		break;
-+	case LINK_RATE_HIGH:
-+		link_rate = "HBR";
-+		break;
-+	case LINK_RATE_HIGH2:
-+		link_rate = "HBR2";
-+		break;
-+	case LINK_RATE_RBR2:
-+		link_rate = "RBR2";
-+		break;
-+	case LINK_RATE_HIGH3:
-+		link_rate = "HBR3";
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	/* Connectivity log: link training */
-+	CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d",
-+			link_rate,
-+			lt_settings.link_settings.lane_count,
-+			(status ==  LINK_TRAINING_SUCCESS) ? "pass" :
-+			((status == LINK_TRAINING_CR_FAIL) ? "CR failed" :
-+			"EQ failed"),
-+			lt_settings.lane_settings[0].VOLTAGE_SWING,
-+			lt_settings.lane_settings[0].PRE_EMPHASIS);
-+
-+	return status;
-+}
-+
-+
-+bool perform_link_training_with_retries(
-+	struct dc_link *link,
-+	const struct dc_link_settings *link_setting,
-+	bool skip_video_pattern,
-+	int attempts)
-+{
-+	uint8_t j;
-+	uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
-+
-+	for (j = 0; j < attempts; ++j) {
-+
-+		if (dc_link_dp_perform_link_training(
-+				link,
-+				link_setting,
-+				skip_video_pattern) == LINK_TRAINING_SUCCESS)
-+			return true;
-+
-+		msleep(delay_between_attempts);
-+		delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
-+	}
-+
-+	return false;
-+}
-+
-+static struct dc_link_settings get_max_link_cap(struct dc_link *link)
-+{
-+	/* Set Default link settings */
-+	struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
-+			LINK_SPREAD_05_DOWNSPREAD_30KHZ};
-+
-+	/* Higher link settings based on feature supported */
-+	if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
-+		max_link_cap.link_rate = LINK_RATE_HIGH2;
-+
-+	if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
-+		max_link_cap.link_rate = LINK_RATE_HIGH3;
-+
-+	/* Lower link settings based on sink's link cap */
-+	if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
-+		max_link_cap.lane_count =
-+				link->reported_link_cap.lane_count;
-+	if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
-+		max_link_cap.link_rate =
-+				link->reported_link_cap.link_rate;
-+	if (link->reported_link_cap.link_spread <
-+			max_link_cap.link_spread)
-+		max_link_cap.link_spread =
-+				link->reported_link_cap.link_spread;
-+	return max_link_cap;
-+}
-+
-+bool dp_hbr_verify_link_cap(
-+	struct dc_link *link,
-+	struct dc_link_settings *known_limit_link_setting)
-+{
-+	struct dc_link_settings max_link_cap = {0};
-+	struct dc_link_settings cur_link_setting = {0};
-+	struct dc_link_settings *cur = &cur_link_setting;
-+	struct dc_link_settings initial_link_settings = {0};
-+	bool success;
-+	bool skip_link_training;
-+	bool skip_video_pattern;
-+	struct clock_source *dp_cs;
-+	enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
-+	enum link_training_result status;
-+
-+	success = false;
-+	skip_link_training = false;
-+
-+	max_link_cap = get_max_link_cap(link);
-+
-+	/* TODO implement override and monitor patch later */
-+
-+	/* try to train the link from high to low to
-+	 * find the physical link capability
-+	 */
-+	/* disable PHY done possible by BIOS, will be done by driver itself */
-+	dp_disable_link_phy(link, link->connector_signal);
-+
-+	dp_cs = link->dc->res_pool->dp_clock_source;
-+
-+	if (dp_cs)
-+		dp_cs_id = dp_cs->id;
-+	else {
-+		/*
-+		 * dp clock source is not initialized for some reason.
-+		 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
-+		 */
-+		ASSERT(dp_cs);
-+	}
-+
-+	/* link training starts with the maximum common settings
-+	 * supported by both sink and ASIC.
-+	 */
-+	initial_link_settings = get_common_supported_link_settings(
-+			*known_limit_link_setting,
-+			max_link_cap);
-+	cur_link_setting = initial_link_settings;
-+	do {
-+		skip_video_pattern = true;
-+
-+		if (cur->link_rate == LINK_RATE_LOW)
-+			skip_video_pattern = false;
-+
-+		dp_enable_link_phy(
-+				link,
-+				link->connector_signal,
-+				dp_cs_id,
-+				cur);
-+
-+		if (skip_link_training)
-+			success = true;
-+		else {
-+			status = dc_link_dp_perform_link_training(
-+							link,
-+							cur,
-+							skip_video_pattern);
-+			if (status == LINK_TRAINING_SUCCESS)
-+				success = true;
-+		}
-+
-+		if (success)
-+			link->verified_link_cap = *cur;
-+
-+		/* always disable the link before trying another
-+		 * setting or before returning we'll enable it later
-+		 * based on the actual mode we're driving
-+		 */
-+		dp_disable_link_phy(link, link->connector_signal);
-+	} while (!success && decide_fallback_link_setting(
-+			initial_link_settings, cur, status));
-+
-+	/* Link Training failed for all Link Settings
-+	 *  (Lane Count is still unknown)
-+	 */
-+	if (!success) {
-+		/* If all LT fails for all settings,
-+		 * set verified = failed safe (1 lane low)
-+		 */
-+		link->verified_link_cap.lane_count = LANE_COUNT_ONE;
-+		link->verified_link_cap.link_rate = LINK_RATE_LOW;
-+
-+		link->verified_link_cap.link_spread =
-+		LINK_SPREAD_DISABLED;
-+	}
-+
-+
-+	return success;
-+}
-+
-+static struct dc_link_settings get_common_supported_link_settings (
-+		struct dc_link_settings link_setting_a,
-+		struct dc_link_settings link_setting_b)
-+{
-+	struct dc_link_settings link_settings = {0};
-+
-+	link_settings.lane_count =
-+		(link_setting_a.lane_count <=
-+			link_setting_b.lane_count) ?
-+			link_setting_a.lane_count :
-+			link_setting_b.lane_count;
-+	link_settings.link_rate =
-+		(link_setting_a.link_rate <=
-+			link_setting_b.link_rate) ?
-+			link_setting_a.link_rate :
-+			link_setting_b.link_rate;
-+	link_settings.link_spread = LINK_SPREAD_DISABLED;
-+
-+	/* in DP compliance test, DPR-120 may have
-+	 * a random value in its MAX_LINK_BW dpcd field.
-+	 * We map it to the maximum supported link rate that
-+	 * is smaller than MAX_LINK_BW in this case.
-+	 */
-+	if (link_settings.link_rate > LINK_RATE_HIGH3) {
-+		link_settings.link_rate = LINK_RATE_HIGH3;
-+	} else if (link_settings.link_rate < LINK_RATE_HIGH3
-+			&& link_settings.link_rate > LINK_RATE_HIGH2) {
-+		link_settings.link_rate = LINK_RATE_HIGH2;
-+	} else if (link_settings.link_rate < LINK_RATE_HIGH2
-+			&& link_settings.link_rate > LINK_RATE_HIGH) {
-+		link_settings.link_rate = LINK_RATE_HIGH;
-+	} else if (link_settings.link_rate < LINK_RATE_HIGH
-+			&& link_settings.link_rate > LINK_RATE_LOW) {
-+		link_settings.link_rate = LINK_RATE_LOW;
-+	} else if (link_settings.link_rate < LINK_RATE_LOW) {
-+		link_settings.link_rate = LINK_RATE_UNKNOWN;
-+	}
-+
-+	return link_settings;
-+}
-+
-+static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
-+{
-+	return lane_count <= LANE_COUNT_ONE;
-+}
-+
-+static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
-+{
-+	return link_rate <= LINK_RATE_LOW;
-+}
-+
-+static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
-+{
-+	switch (lane_count) {
-+	case LANE_COUNT_FOUR:
-+		return LANE_COUNT_TWO;
-+	case LANE_COUNT_TWO:
-+		return LANE_COUNT_ONE;
-+	case LANE_COUNT_ONE:
-+		return LANE_COUNT_UNKNOWN;
-+	default:
-+		return LANE_COUNT_UNKNOWN;
-+	}
-+}
-+
-+static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
-+{
-+	switch (link_rate) {
-+	case LINK_RATE_HIGH3:
-+		return LINK_RATE_HIGH2;
-+	case LINK_RATE_HIGH2:
-+		return LINK_RATE_HIGH;
-+	case LINK_RATE_HIGH:
-+		return LINK_RATE_LOW;
-+	case LINK_RATE_LOW:
-+		return LINK_RATE_UNKNOWN;
-+	default:
-+		return LINK_RATE_UNKNOWN;
-+	}
-+}
-+
-+static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
-+{
-+	switch (lane_count) {
-+	case LANE_COUNT_ONE:
-+		return LANE_COUNT_TWO;
-+	case LANE_COUNT_TWO:
-+		return LANE_COUNT_FOUR;
-+	default:
-+		return LANE_COUNT_UNKNOWN;
-+	}
-+}
-+
-+static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
-+{
-+	switch (link_rate) {
-+	case LINK_RATE_LOW:
-+		return LINK_RATE_HIGH;
-+	case LINK_RATE_HIGH:
-+		return LINK_RATE_HIGH2;
-+	case LINK_RATE_HIGH2:
-+		return LINK_RATE_HIGH3;
-+	default:
-+		return LINK_RATE_UNKNOWN;
-+	}
-+}
-+
-+/*
-+ * function: set link rate and lane count fallback based
-+ * on current link setting and last link training result
-+ * return value:
-+ *			true - link setting could be set
-+ *			false - has reached minimum setting
-+ *					and no further fallback could be done
-+ */
-+static bool decide_fallback_link_setting(
-+		struct dc_link_settings initial_link_settings,
-+		struct dc_link_settings *current_link_setting,
-+		enum link_training_result training_result)
-+{
-+	if (!current_link_setting)
-+		return false;
-+
-+	switch (training_result) {
-+	case LINK_TRAINING_CR_FAIL:
-+	{
-+		if (!reached_minimum_link_rate
-+				(current_link_setting->link_rate)) {
-+			current_link_setting->link_rate =
-+				reduce_link_rate(
-+					current_link_setting->link_rate);
-+		} else if (!reached_minimum_lane_count
-+				(current_link_setting->lane_count)) {
-+			current_link_setting->link_rate =
-+				initial_link_settings.link_rate;
-+			current_link_setting->lane_count =
-+				reduce_lane_count(
-+					current_link_setting->lane_count);
-+		} else {
-+			return false;
-+		}
-+		break;
-+	}
-+	case LINK_TRAINING_EQ_FAIL_EQ:
-+	{
-+		if (!reached_minimum_lane_count
-+				(current_link_setting->lane_count)) {
-+			current_link_setting->lane_count =
-+				reduce_lane_count(
-+					current_link_setting->lane_count);
-+		} else if (!reached_minimum_link_rate
-+				(current_link_setting->link_rate)) {
-+			current_link_setting->link_rate =
-+				reduce_link_rate(
-+					current_link_setting->link_rate);
-+		} else {
-+			return false;
-+		}
-+		break;
-+	}
-+	case LINK_TRAINING_EQ_FAIL_CR:
-+	{
-+		if (!reached_minimum_link_rate
-+				(current_link_setting->link_rate)) {
-+			current_link_setting->link_rate =
-+				reduce_link_rate(
-+					current_link_setting->link_rate);
-+		} else {
-+			return false;
-+		}
-+		break;
-+	}
-+	default:
-+		return false;
-+	}
-+	return true;
-+}
-+
-+static uint32_t bandwidth_in_kbps_from_timing(
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t bits_per_channel = 0;
-+	uint32_t kbps;
-+	switch (timing->display_color_depth) {
-+
-+	case COLOR_DEPTH_666:
-+		bits_per_channel = 6;
-+		break;
-+	case COLOR_DEPTH_888:
-+		bits_per_channel = 8;
-+		break;
-+	case COLOR_DEPTH_101010:
-+		bits_per_channel = 10;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		bits_per_channel = 12;
-+		break;
-+	case COLOR_DEPTH_141414:
-+		bits_per_channel = 14;
-+		break;
-+	case COLOR_DEPTH_161616:
-+		bits_per_channel = 16;
-+		break;
-+	default:
-+		break;
-+	}
-+	ASSERT(bits_per_channel != 0);
-+
-+	kbps = timing->pix_clk_khz;
-+	kbps *= bits_per_channel;
-+
-+	if (timing->flags.Y_ONLY != 1)
-+		/*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
-+		kbps *= 3;
-+
-+	return kbps;
-+
-+}
-+
-+static uint32_t bandwidth_in_kbps_from_link_settings(
-+	const struct dc_link_settings *link_setting)
-+{
-+	uint32_t link_rate_in_kbps = link_setting->link_rate *
-+		LINK_RATE_REF_FREQ_IN_KHZ;
-+
-+	uint32_t lane_count  = link_setting->lane_count;
-+	uint32_t kbps = link_rate_in_kbps;
-+	kbps *= lane_count;
-+	kbps *= 8;   /* 8 bits per byte*/
-+
-+	return kbps;
-+
-+}
-+
-+bool dp_validate_mode_timing(
-+	struct dc_link *link,
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t req_bw;
-+	uint32_t max_bw;
-+
-+	const struct dc_link_settings *link_setting;
-+
-+	/*always DP fail safe mode*/
-+	if (timing->pix_clk_khz == (uint32_t)25175 &&
-+		timing->h_addressable == (uint32_t)640 &&
-+		timing->v_addressable == (uint32_t)480)
-+		return true;
-+
-+	/* We always use verified link settings */
-+	link_setting = &link->verified_link_cap;
-+
-+	/* TODO: DYNAMIC_VALIDATION needs to be implemented */
-+	/*if (flags.DYNAMIC_VALIDATION == 1 &&
-+		link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
-+		link_setting = &link->verified_link_cap;
-+	*/
-+
-+	req_bw = bandwidth_in_kbps_from_timing(timing);
-+	max_bw = bandwidth_in_kbps_from_link_settings(link_setting);
-+
-+	if (req_bw <= max_bw) {
-+		/* remember the biggest mode here, during
-+		 * initial link training (to get
-+		 * verified_link_cap), LS sends event about
-+		 * cannot train at reported cap to upper
-+		 * layer and upper layer will re-enumerate modes.
-+		 * this is not necessary if the lower
-+		 * verified_link_cap is enough to drive
-+		 * all the modes */
-+
-+		/* TODO: DYNAMIC_VALIDATION needs to be implemented */
-+		/* if (flags.DYNAMIC_VALIDATION == 1)
-+			dpsst->max_req_bw_for_verified_linkcap = dal_max(
-+				dpsst->max_req_bw_for_verified_linkcap, req_bw); */
-+		return true;
-+	} else
-+		return false;
-+}
-+
-+void decide_link_settings(struct dc_stream_state *stream,
-+	struct dc_link_settings *link_setting)
-+{
-+
-+	struct dc_link_settings initial_link_setting = {
-+		LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED};
-+	struct dc_link_settings current_link_setting =
-+			initial_link_setting;
-+	struct dc_link *link;
-+	uint32_t req_bw;
-+	uint32_t link_bw;
-+
-+	req_bw = bandwidth_in_kbps_from_timing(&stream->timing);
-+
-+	link = stream->sink->link;
-+
-+	/* if preferred is specified through AMDDP, use it, if it's enough
-+	 * to drive the mode
-+	 */
-+	if (link->preferred_link_setting.lane_count !=
-+			LANE_COUNT_UNKNOWN &&
-+			link->preferred_link_setting.link_rate !=
-+					LINK_RATE_UNKNOWN) {
-+		*link_setting =  link->preferred_link_setting;
-+		return;
-+	}
-+
-+	/* MST doesn't perform link training for now
-+	 * TODO: add MST specific link training routine
-+	 */
-+	if (is_mst_supported(link)) {
-+		*link_setting = link->verified_link_cap;
-+		return;
-+	}
-+
-+	/* search for the minimum link setting that:
-+	 * 1. is supported according to the link training result
-+	 * 2. could support the b/w requested by the timing
-+	 */
-+	while (current_link_setting.link_rate <=
-+			link->verified_link_cap.link_rate) {
-+		link_bw = bandwidth_in_kbps_from_link_settings(
-+				&current_link_setting);
-+		if (req_bw <= link_bw) {
-+			*link_setting = current_link_setting;
-+			return;
-+		}
-+
-+		if (current_link_setting.lane_count <
-+				link->verified_link_cap.lane_count) {
-+			current_link_setting.lane_count =
-+					increase_lane_count(
-+							current_link_setting.lane_count);
-+		} else {
-+			current_link_setting.link_rate =
-+					increase_link_rate(
-+							current_link_setting.link_rate);
-+			current_link_setting.lane_count =
-+					initial_link_setting.lane_count;
-+		}
-+	}
-+
-+	BREAK_TO_DEBUGGER();
-+	ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
-+
-+	*link_setting = link->verified_link_cap;
-+}
-+
-+/*************************Short Pulse IRQ***************************/
-+
-+static bool hpd_rx_irq_check_link_loss_status(
-+	struct dc_link *link,
-+	union hpd_irq_data *hpd_irq_dpcd_data)
-+{
-+	uint8_t irq_reg_rx_power_state;
-+	enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
-+	union lane_status lane_status;
-+	uint32_t lane;
-+	bool sink_status_changed;
-+	bool return_code;
-+
-+	sink_status_changed = false;
-+	return_code = false;
-+
-+	if (link->cur_link_settings.lane_count == 0)
-+		return return_code;
-+	/*1. Check that we can handle interrupt: Not in FS DOS,
-+	 *  Not in "Display Timeout" state, Link is trained.
-+	 */
-+
-+	dpcd_result = core_link_read_dpcd(link,
-+		DP_SET_POWER,
-+		&irq_reg_rx_power_state,
-+		sizeof(irq_reg_rx_power_state));
-+
-+	if (dpcd_result != DC_OK) {
-+		irq_reg_rx_power_state = DP_SET_POWER_D0;
-+		dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
-+			"%s: DPCD read failed to obtain power state.\n",
-+			__func__);
-+	}
-+
-+	if (irq_reg_rx_power_state == DP_SET_POWER_D0) {
-+
-+		/*2. Check that Link Status changed, before re-training.*/
-+
-+		/*parse lane status*/
-+		for (lane = 0;
-+			lane < link->cur_link_settings.lane_count;
-+			lane++) {
-+
-+			/* check status of lanes 0,1
-+			 * changed DpcdAddress_Lane01Status (0x202)*/
-+			lane_status.raw = get_nibble_at_index(
-+				&hpd_irq_dpcd_data->bytes.lane01_status.raw,
-+				lane);
-+
-+			if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
-+				!lane_status.bits.CR_DONE_0 ||
-+				!lane_status.bits.SYMBOL_LOCKED_0) {
-+				/* if one of the channel equalization, clock
-+				 * recovery or symbol lock is dropped
-+				 * consider it as (link has been
-+				 * dropped) dp sink status has changed*/
-+				sink_status_changed = true;
-+				break;
-+			}
-+
-+		}
-+
-+		/* Check interlane align.*/
-+		if (sink_status_changed ||
-+			!hpd_irq_dpcd_data->bytes.lane_status_updated.bits.
-+			INTERLANE_ALIGN_DONE) {
-+
-+			dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
-+				"%s: Link Status changed.\n",
-+				__func__);
-+
-+			return_code = true;
-+		}
-+	}
-+
-+	return return_code;
-+}
-+
-+static enum dc_status read_hpd_rx_irq_data(
-+	struct dc_link *link,
-+	union hpd_irq_data *irq_data)
-+{
-+	/* The HW reads 16 bytes from 200h on HPD,
-+	 * but if we get an AUX_DEFER, the HW cannot retry
-+	 * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
-+	 * fail, so we now explicitly read 6 bytes which is
-+	 * the req from the above mentioned test cases.
-+	 */
-+	return core_link_read_dpcd(
-+	link,
-+	DP_SINK_COUNT,
-+	irq_data->raw,
-+	sizeof(union hpd_irq_data));
-+}
-+
-+static bool allow_hpd_rx_irq(const struct dc_link *link)
-+{
-+	/*
-+	 * Don't handle RX IRQ unless one of following is met:
-+	 * 1) The link is established (cur_link_settings != unknown)
-+	 * 2) We kicked off MST detection
-+	 * 3) We know we're dealing with an active dongle
-+	 */
-+
-+	if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
-+		(link->type == dc_connection_mst_branch) ||
-+		is_dp_active_dongle(link))
-+		return true;
-+
-+	return false;
-+}
-+
-+static bool handle_hpd_irq_psr_sink(const struct dc_link *link)
-+{
-+	union dpcd_psr_configuration psr_configuration;
-+
-+	if (!link->psr_enabled)
-+		return false;
-+
-+	dm_helpers_dp_read_dpcd(
-+		link->ctx,
-+		link,
-+		368,/*DpcdAddress_PSR_Enable_Cfg*/
-+		&psr_configuration.raw,
-+		sizeof(psr_configuration.raw));
-+
-+
-+	if (psr_configuration.bits.ENABLE) {
-+		unsigned char dpcdbuf[3] = {0};
-+		union psr_error_status psr_error_status;
-+		union psr_sink_psr_status psr_sink_psr_status;
-+
-+		dm_helpers_dp_read_dpcd(
-+			link->ctx,
-+			link,
-+			0x2006, /*DpcdAddress_PSR_Error_Status*/
-+			(unsigned char *) dpcdbuf,
-+			sizeof(dpcdbuf));
-+
-+		/*DPCD 2006h   ERROR STATUS*/
-+		psr_error_status.raw = dpcdbuf[0];
-+		/*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
-+		psr_sink_psr_status.raw = dpcdbuf[2];
-+
-+		if (psr_error_status.bits.LINK_CRC_ERROR ||
-+				psr_error_status.bits.RFB_STORAGE_ERROR) {
-+			/* Acknowledge and clear error bits */
-+			dm_helpers_dp_write_dpcd(
-+				link->ctx,
-+				link,
-+				8198,/*DpcdAddress_PSR_Error_Status*/
-+				&psr_error_status.raw,
-+				sizeof(psr_error_status.raw));
-+
-+			/* PSR error, disable and re-enable PSR */
-+			dc_link_set_psr_enable(link, false, true);
-+			dc_link_set_psr_enable(link, true, true);
-+
-+			return true;
-+		} else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
-+				PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
-+			/* No error is detect, PSR is active.
-+			 * We should return with IRQ_HPD handled without
-+			 * checking for loss of sync since PSR would have
-+			 * powered down main link.
-+			 */
-+			return true;
-+		}
-+	}
-+	return false;
-+}
-+
-+static void dp_test_send_link_training(struct dc_link *link)
-+{
-+	struct dc_link_settings link_settings = {0};
-+
-+	core_link_read_dpcd(
-+			link,
-+			DP_TEST_LANE_COUNT,
-+			(unsigned char *)(&link_settings.lane_count),
-+			1);
-+	core_link_read_dpcd(
-+			link,
-+			DP_TEST_LINK_RATE,
-+			(unsigned char *)(&link_settings.link_rate),
-+			1);
-+
-+	/* Set preferred link settings */
-+	link->verified_link_cap.lane_count = link_settings.lane_count;
-+	link->verified_link_cap.link_rate = link_settings.link_rate;
-+
-+	dp_retrain_link_dp_test(link, &link_settings, false);
-+}
-+
-+/* TODO hbr2 compliance eye output is unstable
-+ * (toggling on and off) with debugger break
-+ * This caueses intermittent PHY automation failure
-+ * Need to look into the root cause */
-+static uint8_t force_tps4_for_cp2520 = 1;
-+
-+static void dp_test_send_phy_test_pattern(struct dc_link *link)
-+{
-+	union phy_test_pattern dpcd_test_pattern;
-+	union lane_adjust dpcd_lane_adjustment[2];
-+	unsigned char dpcd_post_cursor_2_adjustment = 0;
-+	unsigned char test_80_bit_pattern[
-+			(DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
-+			DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
-+	enum dp_test_pattern test_pattern;
-+	struct dc_link_training_settings link_settings;
-+	union lane_adjust dpcd_lane_adjust;
-+	unsigned int lane;
-+	struct link_training_settings link_training_settings;
-+	int i = 0;
-+
-+	dpcd_test_pattern.raw = 0;
-+	memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
-+	memset(&link_settings, 0, sizeof(link_settings));
-+
-+	/* get phy test pattern and pattern parameters from DP receiver */
-+	core_link_read_dpcd(
-+			link,
-+			DP_TEST_PHY_PATTERN,
-+			&dpcd_test_pattern.raw,
-+			sizeof(dpcd_test_pattern));
-+	core_link_read_dpcd(
-+			link,
-+			DP_ADJUST_REQUEST_LANE0_1,
-+			&dpcd_lane_adjustment[0].raw,
-+			sizeof(dpcd_lane_adjustment));
-+
-+	/*get post cursor 2 parameters
-+	 * For DP 1.1a or eariler, this DPCD register's value is 0
-+	 * For DP 1.2 or later:
-+	 * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
-+	 * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
-+	 */
-+	core_link_read_dpcd(
-+			link,
-+			DP_ADJUST_REQUEST_POST_CURSOR2,
-+			&dpcd_post_cursor_2_adjustment,
-+			sizeof(dpcd_post_cursor_2_adjustment));
-+
-+	/* translate request */
-+	switch (dpcd_test_pattern.bits.PATTERN) {
-+	case PHY_TEST_PATTERN_D10_2:
-+		test_pattern = DP_TEST_PATTERN_D102;
-+		break;
-+	case PHY_TEST_PATTERN_SYMBOL_ERROR:
-+		test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
-+		break;
-+	case PHY_TEST_PATTERN_PRBS7:
-+		test_pattern = DP_TEST_PATTERN_PRBS7;
-+		break;
-+	case PHY_TEST_PATTERN_80BIT_CUSTOM:
-+		test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
-+		break;
-+	case PHY_TEST_PATTERN_CP2520_1:
-+		/* CP2520 pattern is unstable, temporarily use TPS4 instead */
-+		test_pattern = (force_tps4_for_cp2520 == 1) ?
-+				DP_TEST_PATTERN_TRAINING_PATTERN4 :
-+				DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
-+		break;
-+	case PHY_TEST_PATTERN_CP2520_2:
-+		/* CP2520 pattern is unstable, temporarily use TPS4 instead */
-+		test_pattern = (force_tps4_for_cp2520 == 1) ?
-+				DP_TEST_PATTERN_TRAINING_PATTERN4 :
-+				DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
-+		break;
-+	case PHY_TEST_PATTERN_CP2520_3:
-+		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
-+		break;
-+	default:
-+		test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
-+	break;
-+	}
-+
-+	if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
-+		core_link_read_dpcd(
-+				link,
-+				DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
-+				test_80_bit_pattern,
-+				sizeof(test_80_bit_pattern));
-+
-+	/* prepare link training settings */
-+	link_settings.link = link->cur_link_settings;
-+
-+	for (lane = 0; lane <
-+		(unsigned int)(link->cur_link_settings.lane_count);
-+		lane++) {
-+		dpcd_lane_adjust.raw =
-+			get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
-+		link_settings.lane_settings[lane].VOLTAGE_SWING =
-+			(enum dc_voltage_swing)
-+			(dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
-+		link_settings.lane_settings[lane].PRE_EMPHASIS =
-+			(enum dc_pre_emphasis)
-+			(dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
-+		link_settings.lane_settings[lane].POST_CURSOR2 =
-+			(enum dc_post_cursor2)
-+			((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
-+	}
-+
-+	for (i = 0; i < 4; i++)
-+		link_training_settings.lane_settings[i] =
-+				link_settings.lane_settings[i];
-+	link_training_settings.link_settings = link_settings.link;
-+	link_training_settings.allow_invalid_msa_timing_param = false;
-+	/*Usage: Measure DP physical lane signal
-+	 * by DP SI test equipment automatically.
-+	 * PHY test pattern request is generated by equipment via HPD interrupt.
-+	 * HPD needs to be active all the time. HPD should be active
-+	 * all the time. Do not touch it.
-+	 * forward request to DS
-+	 */
-+	dc_link_dp_set_test_pattern(
-+		link,
-+		test_pattern,
-+		&link_training_settings,
-+		test_80_bit_pattern,
-+		(DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
-+		DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
-+}
-+
-+static void dp_test_send_link_test_pattern(struct dc_link *link)
-+{
-+	union link_test_pattern dpcd_test_pattern;
-+	union test_misc dpcd_test_params;
-+	enum dp_test_pattern test_pattern;
-+
-+	memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
-+	memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
-+
-+	/* get link test pattern and pattern parameters */
-+	core_link_read_dpcd(
-+			link,
-+			DP_TEST_PATTERN,
-+			&dpcd_test_pattern.raw,
-+			sizeof(dpcd_test_pattern));
-+	core_link_read_dpcd(
-+			link,
-+			DP_TEST_MISC0,
-+			&dpcd_test_params.raw,
-+			sizeof(dpcd_test_params));
-+
-+	switch (dpcd_test_pattern.bits.PATTERN) {
-+	case LINK_TEST_PATTERN_COLOR_RAMP:
-+		test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
-+	break;
-+	case LINK_TEST_PATTERN_VERTICAL_BARS:
-+		test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
-+	break; /* black and white */
-+	case LINK_TEST_PATTERN_COLOR_SQUARES:
-+		test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
-+				TEST_DYN_RANGE_VESA ?
-+				DP_TEST_PATTERN_COLOR_SQUARES :
-+				DP_TEST_PATTERN_COLOR_SQUARES_CEA);
-+	break;
-+	default:
-+		test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
-+	break;
-+	}
-+
-+	dc_link_dp_set_test_pattern(
-+			link,
-+			test_pattern,
-+			NULL,
-+			NULL,
-+			0);
-+}
-+
-+static void handle_automated_test(struct dc_link *link)
-+{
-+	union test_request test_request;
-+	union test_response test_response;
-+
-+	memset(&test_request, 0, sizeof(test_request));
-+	memset(&test_response, 0, sizeof(test_response));
-+
-+	core_link_read_dpcd(
-+		link,
-+		DP_TEST_REQUEST,
-+		&test_request.raw,
-+		sizeof(union test_request));
-+	if (test_request.bits.LINK_TRAINING) {
-+		/* ACK first to let DP RX test box monitor LT sequence */
-+		test_response.bits.ACK = 1;
-+		core_link_write_dpcd(
-+			link,
-+			DP_TEST_RESPONSE,
-+			&test_response.raw,
-+			sizeof(test_response));
-+		dp_test_send_link_training(link);
-+		/* no acknowledge request is needed again */
-+		test_response.bits.ACK = 0;
-+	}
-+	if (test_request.bits.LINK_TEST_PATTRN) {
-+		dp_test_send_link_test_pattern(link);
-+		test_response.bits.ACK = 1;
-+	}
-+	if (test_request.bits.PHY_TEST_PATTERN) {
-+		dp_test_send_phy_test_pattern(link);
-+		test_response.bits.ACK = 1;
-+	}
-+	if (!test_request.raw)
-+		/* no requests, revert all test signals
-+		 * TODO: revert all test signals
-+		 */
-+		test_response.bits.ACK = 1;
-+	/* send request acknowledgment */
-+	if (test_response.bits.ACK)
-+		core_link_write_dpcd(
-+			link,
-+			DP_TEST_RESPONSE,
-+			&test_response.raw,
-+			sizeof(test_response));
-+}
-+
-+bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data)
-+{
-+	union hpd_irq_data hpd_irq_dpcd_data = {{{{0}}}};
-+	union device_service_irq device_service_clear = { { 0 } };
-+	enum dc_status result = DDC_RESULT_UNKNOWN;
-+	bool status = false;
-+	/* For use cases related to down stream connection status change,
-+	 * PSR and device auto test, refer to function handle_sst_hpd_irq
-+	 * in DAL2.1*/
-+
-+	dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
-+		"%s: Got short pulse HPD on link %d\n",
-+		__func__, link->link_index);
-+
-+
-+	 /* All the "handle_hpd_irq_xxx()" methods
-+		 * should be called only after
-+		 * dal_dpsst_ls_read_hpd_irq_data
-+		 * Order of calls is important too
-+		 */
-+	result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
-+	if (out_hpd_irq_dpcd_data)
-+		*out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
-+
-+	if (result != DC_OK) {
-+		dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
-+			"%s: DPCD read failed to obtain irq data\n",
-+			__func__);
-+		return false;
-+	}
-+
-+	if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
-+		device_service_clear.bits.AUTOMATED_TEST = 1;
-+		core_link_write_dpcd(
-+			link,
-+			DP_DEVICE_SERVICE_IRQ_VECTOR,
-+			&device_service_clear.raw,
-+			sizeof(device_service_clear.raw));
-+		device_service_clear.raw = 0;
-+		handle_automated_test(link);
-+		return false;
-+	}
-+
-+	if (!allow_hpd_rx_irq(link)) {
-+		dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
-+			"%s: skipping HPD handling on %d\n",
-+			__func__, link->link_index);
-+		return false;
-+	}
-+
-+	if (handle_hpd_irq_psr_sink(link))
-+		/* PSR-related error was detected and handled */
-+		return true;
-+
-+	/* If PSR-related error handled, Main link may be off,
-+	 * so do not handle as a normal sink status change interrupt.
-+	 */
-+
-+	if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
-+		return true;
-+
-+	/* check if we have MST msg and return since we poll for it */
-+	if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
-+		return false;
-+
-+	/* For now we only handle 'Downstream port status' case.
-+	 * If we got sink count changed it means
-+	 * Downstream port status changed,
-+	 * then DM should call DC to do the detection. */
-+	if (hpd_rx_irq_check_link_loss_status(
-+		link,
-+		&hpd_irq_dpcd_data)) {
-+		/* Connectivity log: link loss */
-+		CONN_DATA_LINK_LOSS(link,
-+					hpd_irq_dpcd_data.raw,
-+					sizeof(hpd_irq_dpcd_data),
-+					"Status: ");
-+
-+		perform_link_training_with_retries(link,
-+			&link->cur_link_settings,
-+			true, LINK_TRAINING_ATTEMPTS);
-+
-+		status = false;
-+	}
-+
-+	if (link->type == dc_connection_active_dongle &&
-+		hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
-+			!= link->dpcd_sink_count)
-+		status = true;
-+
-+	/* reasons for HPD RX:
-+	 * 1. Link Loss - ie Re-train the Link
-+	 * 2. MST sideband message
-+	 * 3. Automated Test - ie. Internal Commit
-+	 * 4. CP (copy protection) - (not interesting for DM???)
-+	 * 5. DRR
-+	 * 6. Downstream Port status changed
-+	 * -ie. Detect - this the only one
-+	 * which is interesting for DM because
-+	 * it must call dc_link_detect.
-+	 */
-+	return status;
-+}
-+
-+/*query dpcd for version and mst cap addresses*/
-+bool is_mst_supported(struct dc_link *link)
-+{
-+	bool mst          = false;
-+	enum dc_status st = DC_OK;
-+	union dpcd_rev rev;
-+	union mstm_cap cap;
-+
-+	rev.raw  = 0;
-+	cap.raw  = 0;
-+
-+	st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
-+			sizeof(rev));
-+
-+	if (st == DC_OK && rev.raw >= DPCD_REV_12) {
-+
-+		st = core_link_read_dpcd(link, DP_MSTM_CAP,
-+				&cap.raw, sizeof(cap));
-+		if (st == DC_OK && cap.bits.MST_CAP == 1)
-+			mst = true;
-+	}
-+	return mst;
-+
-+}
-+
-+bool is_dp_active_dongle(const struct dc_link *link)
-+{
-+	enum display_dongle_type dongle_type = link->dpcd_caps.dongle_type;
-+
-+	return (dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) ||
-+			(dongle_type == DISPLAY_DONGLE_DP_DVI_CONVERTER) ||
-+			(dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER);
-+}
-+
-+static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
-+{
-+	switch (bpc) {
-+	case DOWN_STREAM_MAX_8BPC:
-+		return 8;
-+	case DOWN_STREAM_MAX_10BPC:
-+		return 10;
-+	case DOWN_STREAM_MAX_12BPC:
-+		return 12;
-+	case DOWN_STREAM_MAX_16BPC:
-+		return 16;
-+	default:
-+		break;
-+	}
-+
-+	return -1;
-+}
-+
-+static void get_active_converter_info(
-+	uint8_t data, struct dc_link *link)
-+{
-+	union dp_downstream_port_present ds_port = { .byte = data };
-+
-+	/* decode converter info*/
-+	if (!ds_port.fields.PORT_PRESENT) {
-+		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
-+		ddc_service_set_dongle_type(link->ddc,
-+				link->dpcd_caps.dongle_type);
-+		return;
-+	}
-+
-+	switch (ds_port.fields.PORT_TYPE) {
-+	case DOWNSTREAM_VGA:
-+		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
-+		break;
-+	case DOWNSTREAM_DVI_HDMI:
-+		/* At this point we don't know is it DVI or HDMI,
-+		 * assume DVI.*/
-+		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
-+		break;
-+	default:
-+		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
-+		break;
-+	}
-+
-+	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
-+		uint8_t det_caps[4];
-+		union dwnstream_port_caps_byte0 *port_caps =
-+			(union dwnstream_port_caps_byte0 *)det_caps;
-+		core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
-+				det_caps, sizeof(det_caps));
-+
-+		switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
-+		case DOWN_STREAM_DETAILED_VGA:
-+			link->dpcd_caps.dongle_type =
-+				DISPLAY_DONGLE_DP_VGA_CONVERTER;
-+			break;
-+		case DOWN_STREAM_DETAILED_DVI:
-+			link->dpcd_caps.dongle_type =
-+				DISPLAY_DONGLE_DP_DVI_CONVERTER;
-+			break;
-+		case DOWN_STREAM_DETAILED_HDMI:
-+			link->dpcd_caps.dongle_type =
-+				DISPLAY_DONGLE_DP_HDMI_CONVERTER;
-+
-+			link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
-+			if (ds_port.fields.DETAILED_CAPS) {
-+
-+				union dwnstream_port_caps_byte3_hdmi
-+					hdmi_caps = {.raw = det_caps[3] };
-+				union dwnstream_port_caps_byte2
-+					hdmi_color_caps = {.raw = det_caps[2] };
-+				link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk =
-+					det_caps[1] * 25000;
-+
-+				link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
-+					hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
-+				link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
-+					hdmi_caps.bits.YCrCr422_PASS_THROUGH;
-+				link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
-+					hdmi_caps.bits.YCrCr420_PASS_THROUGH;
-+				link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
-+					hdmi_caps.bits.YCrCr422_CONVERSION;
-+				link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
-+					hdmi_caps.bits.YCrCr420_CONVERSION;
-+
-+				link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
-+					translate_dpcd_max_bpc(
-+						hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
-+
-+				link->dpcd_caps.dongle_caps.extendedCapValid = true;
-+			}
-+
-+			break;
-+		}
-+	}
-+
-+	ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
-+
-+	{
-+		struct dp_device_vendor_id dp_id;
-+
-+		/* read IEEE branch device id */
-+		core_link_read_dpcd(
-+			link,
-+			DP_BRANCH_OUI,
-+			(uint8_t *)&dp_id,
-+			sizeof(dp_id));
-+
-+		link->dpcd_caps.branch_dev_id =
-+			(dp_id.ieee_oui[0] << 16) +
-+			(dp_id.ieee_oui[1] << 8) +
-+			dp_id.ieee_oui[2];
-+
-+		memmove(
-+			link->dpcd_caps.branch_dev_name,
-+			dp_id.ieee_device_id,
-+			sizeof(dp_id.ieee_device_id));
-+	}
-+
-+	{
-+		struct dp_sink_hw_fw_revision dp_hw_fw_revision;
-+
-+		core_link_read_dpcd(
-+			link,
-+			DP_BRANCH_REVISION_START,
-+			(uint8_t *)&dp_hw_fw_revision,
-+			sizeof(dp_hw_fw_revision));
-+
-+		link->dpcd_caps.branch_hw_revision =
-+			dp_hw_fw_revision.ieee_hw_rev;
-+	}
-+}
-+
-+static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
-+		int length)
-+{
-+	int retry = 0;
-+	union dp_downstream_port_present ds_port = { 0 };
-+
-+	if (!link->dpcd_caps.dpcd_rev.raw) {
-+		do {
-+			dp_receiver_power_ctrl(link, true);
-+			core_link_read_dpcd(link, DP_DPCD_REV,
-+							dpcd_data, length);
-+			link->dpcd_caps.dpcd_rev.raw = dpcd_data[
-+				DP_DPCD_REV -
-+				DP_DPCD_REV];
-+		} while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
-+	}
-+
-+	ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
-+				 DP_DPCD_REV];
-+
-+	if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
-+		switch (link->dpcd_caps.branch_dev_id) {
-+		/* Some active dongles (DP-VGA, DP-DLDVI converters) power down
-+		 * all internal circuits including AUX communication preventing
-+		 * reading DPCD table and EDID (spec violation).
-+		 * Encoder will skip DP RX power down on disable_output to
-+		 * keep receiver powered all the time.*/
-+		case DP_BRANCH_DEVICE_ID_1:
-+		case DP_BRANCH_DEVICE_ID_4:
-+			link->wa_flags.dp_keep_receiver_powered = true;
-+			break;
-+
-+		/* TODO: May need work around for other dongles. */
-+		default:
-+			link->wa_flags.dp_keep_receiver_powered = false;
-+			break;
-+		}
-+	} else
-+		link->wa_flags.dp_keep_receiver_powered = false;
-+}
-+
-+static void retrieve_link_cap(struct dc_link *link)
-+{
-+	uint8_t dpcd_data[DP_TRAINING_AUX_RD_INTERVAL - DP_DPCD_REV + 1];
-+
-+	union down_stream_port_count down_strm_port_count;
-+	union edp_configuration_cap edp_config_cap;
-+	union dp_downstream_port_present ds_port = { 0 };
-+
-+	memset(dpcd_data, '\0', sizeof(dpcd_data));
-+	memset(&down_strm_port_count,
-+		'\0', sizeof(union down_stream_port_count));
-+	memset(&edp_config_cap, '\0',
-+		sizeof(union edp_configuration_cap));
-+
-+	core_link_read_dpcd(
-+		link,
-+		DP_DPCD_REV,
-+		dpcd_data,
-+		sizeof(dpcd_data));
-+
-+	{
-+		union training_aux_rd_interval aux_rd_interval;
-+
-+		aux_rd_interval.raw =
-+			dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
-+
-+		if (aux_rd_interval.bits.EXT_RECIEVER_CAP_FIELD_PRESENT == 1) {
-+			core_link_read_dpcd(
-+				link,
-+				DP_DP13_DPCD_REV,
-+				dpcd_data,
-+				sizeof(dpcd_data));
-+		}
-+	}
-+
-+	link->dpcd_caps.dpcd_rev.raw =
-+		dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
-+
-+	ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
-+				 DP_DPCD_REV];
-+
-+	get_active_converter_info(ds_port.byte, link);
-+
-+	dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
-+
-+	link->dpcd_caps.allow_invalid_MSA_timing_param =
-+		down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
-+
-+	link->dpcd_caps.max_ln_count.raw = dpcd_data[
-+		DP_MAX_LANE_COUNT - DP_DPCD_REV];
-+
-+	link->dpcd_caps.max_down_spread.raw = dpcd_data[
-+		DP_MAX_DOWNSPREAD - DP_DPCD_REV];
-+
-+	link->reported_link_cap.lane_count =
-+		link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
-+	link->reported_link_cap.link_rate = dpcd_data[
-+		DP_MAX_LINK_RATE - DP_DPCD_REV];
-+	link->reported_link_cap.link_spread =
-+		link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
-+		LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
-+
-+	edp_config_cap.raw = dpcd_data[
-+		DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
-+	link->dpcd_caps.panel_mode_edp =
-+		edp_config_cap.bits.ALT_SCRAMBLER_RESET;
-+	link->dpcd_caps.dpcd_display_control_capable =
-+		edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
-+
-+	link->test_pattern_enabled = false;
-+	link->compliance_test_state.raw = 0;
-+
-+	/* read sink count */
-+	core_link_read_dpcd(link,
-+			DP_SINK_COUNT,
-+			&link->dpcd_caps.sink_count.raw,
-+			sizeof(link->dpcd_caps.sink_count.raw));
-+
-+	/* Connectivity log: detection */
-+	CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
-+}
-+
-+void detect_dp_sink_caps(struct dc_link *link)
-+{
-+	retrieve_link_cap(link);
-+
-+	/* dc init_hw has power encoder using default
-+	 * signal for connector. For native DP, no
-+	 * need to power up encoder again. If not native
-+	 * DP, hw_init may need check signal or power up
-+	 * encoder here.
-+	 */
-+	/* TODO save sink caps in link->sink */
-+}
-+
-+void detect_edp_sink_caps(struct dc_link *link)
-+{
-+	retrieve_link_cap(link);
-+	link->verified_link_cap = link->reported_link_cap;
-+}
-+
-+void dc_link_dp_enable_hpd(const struct dc_link *link)
-+{
-+	struct link_encoder *encoder = link->link_enc;
-+
-+	if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
-+		encoder->funcs->enable_hpd(encoder);
-+}
-+
-+void dc_link_dp_disable_hpd(const struct dc_link *link)
-+{
-+	struct link_encoder *encoder = link->link_enc;
-+
-+	if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
-+		encoder->funcs->disable_hpd(encoder);
-+}
-+
-+static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
-+{
-+	if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
-+			test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
-+			test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+static void set_crtc_test_pattern(struct dc_link *link,
-+				struct pipe_ctx *pipe_ctx,
-+				enum dp_test_pattern test_pattern)
-+{
-+	enum controller_dp_test_pattern controller_test_pattern;
-+	enum dc_color_depth color_depth = pipe_ctx->
-+		stream->timing.display_color_depth;
-+	struct bit_depth_reduction_params params;
-+
-+	memset(&params, 0, sizeof(params));
-+
-+	switch (test_pattern) {
-+	case DP_TEST_PATTERN_COLOR_SQUARES:
-+		controller_test_pattern =
-+				CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
-+	break;
-+	case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
-+		controller_test_pattern =
-+				CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
-+	break;
-+	case DP_TEST_PATTERN_VERTICAL_BARS:
-+		controller_test_pattern =
-+				CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
-+	break;
-+	case DP_TEST_PATTERN_HORIZONTAL_BARS:
-+		controller_test_pattern =
-+				CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
-+	break;
-+	case DP_TEST_PATTERN_COLOR_RAMP:
-+		controller_test_pattern =
-+				CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
-+	break;
-+	default:
-+		controller_test_pattern =
-+				CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
-+	break;
-+	}
-+
-+	switch (test_pattern) {
-+	case DP_TEST_PATTERN_COLOR_SQUARES:
-+	case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
-+	case DP_TEST_PATTERN_VERTICAL_BARS:
-+	case DP_TEST_PATTERN_HORIZONTAL_BARS:
-+	case DP_TEST_PATTERN_COLOR_RAMP:
-+	{
-+		/* disable bit depth reduction */
-+		pipe_ctx->stream->bit_depth_params = params;
-+		pipe_ctx->stream_res.opp->funcs->
-+			opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
-+
-+		pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
-+				controller_test_pattern, color_depth);
-+	}
-+	break;
-+	case DP_TEST_PATTERN_VIDEO_MODE:
-+	{
-+		/* restore bitdepth reduction */
-+		resource_build_bit_depth_reduction_params(pipe_ctx->stream,
-+					&params);
-+		pipe_ctx->stream->bit_depth_params = params;
-+		pipe_ctx->stream_res.opp->funcs->
-+			opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
-+
-+		pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
-+				CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
-+				color_depth);
-+	}
-+	break;
-+
-+	default:
-+	break;
-+	}
-+}
-+
-+bool dc_link_dp_set_test_pattern(
-+	struct dc_link *link,
-+	enum dp_test_pattern test_pattern,
-+	const struct link_training_settings *p_link_settings,
-+	const unsigned char *p_custom_pattern,
-+	unsigned int cust_pattern_size)
-+{
-+	struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
-+	struct pipe_ctx *pipe_ctx = &pipes[0];
-+	unsigned int lane;
-+	unsigned int i;
-+	unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
-+	union dpcd_training_pattern training_pattern;
-+	enum dpcd_phy_test_patterns pattern;
-+
-+	memset(&training_pattern, 0, sizeof(training_pattern));
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (pipes[i].stream->sink->link == link) {
-+			pipe_ctx = &pipes[i];
-+			break;
-+		}
-+	}
-+
-+	/* Reset CRTC Test Pattern if it is currently running and request
-+	 * is VideoMode Reset DP Phy Test Pattern if it is currently running
-+	 * and request is VideoMode
-+	 */
-+	if (link->test_pattern_enabled && test_pattern ==
-+			DP_TEST_PATTERN_VIDEO_MODE) {
-+		/* Set CRTC Test Pattern */
-+		set_crtc_test_pattern(link, pipe_ctx, test_pattern);
-+		dp_set_hw_test_pattern(link, test_pattern,
-+				(uint8_t *)p_custom_pattern,
-+				(uint32_t)cust_pattern_size);
-+
-+		/* Unblank Stream */
-+		link->dc->hwss.unblank_stream(
-+			pipe_ctx,
-+			&link->verified_link_cap);
-+		/* TODO:m_pHwss->MuteAudioEndpoint
-+		 * (pPathMode->pDisplayPath, false);
-+		 */
-+
-+		/* Reset Test Pattern state */
-+		link->test_pattern_enabled = false;
-+
-+		return true;
-+	}
-+
-+	/* Check for PHY Test Patterns */
-+	if (is_dp_phy_pattern(test_pattern)) {
-+		/* Set DPCD Lane Settings before running test pattern */
-+		if (p_link_settings != NULL) {
-+			dp_set_hw_lane_settings(link, p_link_settings);
-+			dpcd_set_lane_settings(link, p_link_settings);
-+		}
-+
-+		/* Blank stream if running test pattern */
-+		if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
-+			/*TODO:
-+			 * m_pHwss->
-+			 * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
-+			 */
-+			/* Blank stream */
-+			pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
-+		}
-+
-+		dp_set_hw_test_pattern(link, test_pattern,
-+				(uint8_t *)p_custom_pattern,
-+				(uint32_t)cust_pattern_size);
-+
-+		if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
-+			/* Set Test Pattern state */
-+			link->test_pattern_enabled = true;
-+			if (p_link_settings != NULL)
-+				dpcd_set_link_settings(link,
-+						p_link_settings);
-+		}
-+
-+		switch (test_pattern) {
-+		case DP_TEST_PATTERN_VIDEO_MODE:
-+			pattern = PHY_TEST_PATTERN_NONE;
-+			break;
-+		case DP_TEST_PATTERN_D102:
-+			pattern = PHY_TEST_PATTERN_D10_2;
-+			break;
-+		case DP_TEST_PATTERN_SYMBOL_ERROR:
-+			pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
-+			break;
-+		case DP_TEST_PATTERN_PRBS7:
-+			pattern = PHY_TEST_PATTERN_PRBS7;
-+			break;
-+		case DP_TEST_PATTERN_80BIT_CUSTOM:
-+			pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
-+			break;
-+		case DP_TEST_PATTERN_CP2520_1:
-+			pattern = PHY_TEST_PATTERN_CP2520_1;
-+			break;
-+		case DP_TEST_PATTERN_CP2520_2:
-+			pattern = PHY_TEST_PATTERN_CP2520_2;
-+			break;
-+		case DP_TEST_PATTERN_CP2520_3:
-+			pattern = PHY_TEST_PATTERN_CP2520_3;
-+			break;
-+		default:
-+			return false;
-+		}
-+
-+		if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
-+		/*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
-+			return false;
-+
-+		if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
-+			/* tell receiver that we are sending qualification
-+			 * pattern DP 1.2 or later - DP receiver's link quality
-+			 * pattern is set using DPCD LINK_QUAL_LANEx_SET
-+			 * register (0x10B~0x10E)\
-+			 */
-+			for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
-+				link_qual_pattern[lane] =
-+						(unsigned char)(pattern);
-+
-+			core_link_write_dpcd(link,
-+					DP_LINK_QUAL_LANE0_SET,
-+					link_qual_pattern,
-+					sizeof(link_qual_pattern));
-+		} else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
-+			   link->dpcd_caps.dpcd_rev.raw == 0) {
-+			/* tell receiver that we are sending qualification
-+			 * pattern DP 1.1a or earlier - DP receiver's link
-+			 * quality pattern is set using
-+			 * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
-+			 * register (0x102). We will use v_1.3 when we are
-+			 * setting test pattern for DP 1.1.
-+			 */
-+			core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
-+					    &training_pattern.raw,
-+					    sizeof(training_pattern));
-+			training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
-+			core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
-+					     &training_pattern.raw,
-+					     sizeof(training_pattern));
-+		}
-+	} else {
-+	/* CRTC Patterns */
-+		set_crtc_test_pattern(link, pipe_ctx, test_pattern);
-+		/* Set Test Pattern state */
-+		link->test_pattern_enabled = true;
-+	}
-+
-+	return true;
-+}
-+
-+void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
-+{
-+	unsigned char mstmCntl;
-+
-+	core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
-+	if (enable)
-+		mstmCntl |= DP_MST_EN;
-+	else
-+		mstmCntl &= (~DP_MST_EN);
-+
-+	core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c.0130~	2017-12-14 06:39:58.407903562 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c	2017-12-14 06:39:58.407903562 +0100
-@@ -0,0 +1,330 @@
-+/* Copyright 2015 Advanced Micro Devices, Inc. */
-+
-+
-+#include "dm_services.h"
-+#include "dc.h"
-+#include "inc/core_types.h"
-+#include "include/ddc_service_types.h"
-+#include "include/i2caux_interface.h"
-+#include "link_hwss.h"
-+#include "hw_sequencer.h"
-+#include "dc_link_dp.h"
-+#include "dc_link_ddc.h"
-+#include "dm_helpers.h"
-+#include "dce/dce_link_encoder.h"
-+#include "dce/dce_stream_encoder.h"
-+#include "dpcd_defs.h"
-+
-+enum dc_status core_link_read_dpcd(
-+	struct dc_link *link,
-+	uint32_t address,
-+	uint8_t *data,
-+	uint32_t size)
-+{
-+	if (!dm_helpers_dp_read_dpcd(link->ctx,
-+			link,
-+			address, data, size))
-+			return DC_ERROR_UNEXPECTED;
-+
-+	return DC_OK;
-+}
-+
-+enum dc_status core_link_write_dpcd(
-+	struct dc_link *link,
-+	uint32_t address,
-+	const uint8_t *data,
-+	uint32_t size)
-+{
-+	if (!dm_helpers_dp_write_dpcd(link->ctx,
-+			link,
-+			address, data, size))
-+				return DC_ERROR_UNEXPECTED;
-+
-+	return DC_OK;
-+}
-+
-+void dp_receiver_power_ctrl(struct dc_link *link, bool on)
-+{
-+	uint8_t state;
-+
-+	state = on ? DP_POWER_STATE_D0 : DP_POWER_STATE_D3;
-+
-+	core_link_write_dpcd(link, DP_SET_POWER, &state,
-+			sizeof(state));
-+}
-+
-+void dp_enable_link_phy(
-+	struct dc_link *link,
-+	enum signal_type signal,
-+	enum clock_source_id clock_source,
-+	const struct dc_link_settings *link_settings)
-+{
-+	struct link_encoder *link_enc = link->link_enc;
-+
-+	struct pipe_ctx *pipes =
-+			link->dc->current_state->res_ctx.pipe_ctx;
-+	struct clock_source *dp_cs =
-+			link->dc->res_pool->dp_clock_source;
-+	unsigned int i;
-+	/* If the current pixel clock source is not DTO(happens after
-+	 * switching from HDMI passive dongle to DP on the same connector),
-+	 * switch the pixel clock source to DTO.
-+	 */
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (pipes[i].stream != NULL &&
-+			pipes[i].stream->sink != NULL &&
-+			pipes[i].stream->sink->link == link) {
-+			if (pipes[i].clock_source != NULL &&
-+					pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
-+				pipes[i].clock_source = dp_cs;
-+				pipes[i].stream_res.pix_clk_params.requested_pix_clk =
-+						pipes[i].stream->timing.pix_clk_khz;
-+				pipes[i].clock_source->funcs->program_pix_clk(
-+							pipes[i].clock_source,
-+							&pipes[i].stream_res.pix_clk_params,
-+							&pipes[i].pll_settings);
-+			}
-+		}
-+	}
-+
-+	if (dc_is_dp_sst_signal(signal)) {
-+		if (signal == SIGNAL_TYPE_EDP) {
-+			link->dc->hwss.edp_power_control(link, true);
-+			link_enc->funcs->enable_dp_output(
-+						link_enc,
-+						link_settings,
-+						clock_source);
-+			link->dc->hwss.edp_backlight_control(link, true);
-+		} else
-+			link_enc->funcs->enable_dp_output(
-+						link_enc,
-+						link_settings,
-+						clock_source);
-+	} else {
-+		link_enc->funcs->enable_dp_mst_output(
-+						link_enc,
-+						link_settings,
-+						clock_source);
-+	}
-+
-+	dp_receiver_power_ctrl(link, true);
-+}
-+
-+static bool edp_receiver_ready_T9(struct dc_link *link)
-+{
-+	unsigned int tries = 0;
-+	unsigned char sinkstatus = 0;
-+	unsigned char edpRev = 0;
-+	enum dc_status result = DC_OK;
-+	result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
-+	if (edpRev < DP_EDP_12)
-+		return true;
-+	/* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
-+	do {
-+		sinkstatus = 1;
-+		result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
-+		if (sinkstatus == 0)
-+			break;
-+		if (result != DC_OK)
-+			break;
-+		udelay(100); //MAx T9
-+	} while (++tries < 50);
-+	return result;
-+}
-+
-+void dp_disable_link_phy(struct dc_link *link, enum signal_type signal)
-+{
-+	if (!link->wa_flags.dp_keep_receiver_powered)
-+		dp_receiver_power_ctrl(link, false);
-+
-+	if (signal == SIGNAL_TYPE_EDP) {
-+		link->dc->hwss.edp_backlight_control(link, false);
-+		edp_receiver_ready_T9(link);
-+		link->link_enc->funcs->disable_output(link->link_enc, signal);
-+		link->dc->hwss.edp_power_control(link, false);
-+	} else
-+		link->link_enc->funcs->disable_output(link->link_enc, signal);
-+
-+	/* Clear current link setting.*/
-+	memset(&link->cur_link_settings, 0,
-+			sizeof(link->cur_link_settings));
-+}
-+
-+void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal)
-+{
-+	/* MST disable link only when no stream use the link */
-+	if (link->mst_stream_alloc_table.stream_count > 0)
-+		return;
-+
-+	dp_disable_link_phy(link, signal);
-+
-+	/* set the sink to SST mode after disabling the link */
-+	dp_enable_mst_on_sink(link, false);
-+}
-+
-+bool dp_set_hw_training_pattern(
-+	struct dc_link *link,
-+	enum hw_dp_training_pattern pattern)
-+{
-+	enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
-+
-+	switch (pattern) {
-+	case HW_DP_TRAINING_PATTERN_1:
-+		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN1;
-+		break;
-+	case HW_DP_TRAINING_PATTERN_2:
-+		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN2;
-+		break;
-+	case HW_DP_TRAINING_PATTERN_3:
-+		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3;
-+		break;
-+	case HW_DP_TRAINING_PATTERN_4:
-+		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	dp_set_hw_test_pattern(link, test_pattern, NULL, 0);
-+
-+	return true;
-+}
-+
-+void dp_set_hw_lane_settings(
-+	struct dc_link *link,
-+	const struct link_training_settings *link_settings)
-+{
-+	struct link_encoder *encoder = link->link_enc;
-+
-+	/* call Encoder to set lane settings */
-+	encoder->funcs->dp_set_lane_settings(encoder, link_settings);
-+}
-+
-+enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
-+{
-+	/* We need to explicitly check that connector
-+	 * is not DP. Some Travis_VGA get reported
-+	 * by video bios as DP.
-+	 */
-+	if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
-+
-+		switch (link->dpcd_caps.branch_dev_id) {
-+		case DP_BRANCH_DEVICE_ID_2:
-+			if (strncmp(
-+				link->dpcd_caps.branch_dev_name,
-+				DP_VGA_LVDS_CONVERTER_ID_2,
-+				sizeof(
-+				link->dpcd_caps.
-+				branch_dev_name)) == 0) {
-+				return DP_PANEL_MODE_SPECIAL;
-+			}
-+			break;
-+		case DP_BRANCH_DEVICE_ID_3:
-+			if (strncmp(link->dpcd_caps.branch_dev_name,
-+				DP_VGA_LVDS_CONVERTER_ID_3,
-+				sizeof(
-+				link->dpcd_caps.
-+				branch_dev_name)) == 0) {
-+				return DP_PANEL_MODE_SPECIAL;
-+			}
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	if (link->dpcd_caps.panel_mode_edp) {
-+		return DP_PANEL_MODE_EDP;
-+	}
-+
-+	return DP_PANEL_MODE_DEFAULT;
-+}
-+
-+void dp_set_hw_test_pattern(
-+	struct dc_link *link,
-+	enum dp_test_pattern test_pattern,
-+	uint8_t *custom_pattern,
-+	uint32_t custom_pattern_size)
-+{
-+	struct encoder_set_dp_phy_pattern_param pattern_param = {0};
-+	struct link_encoder *encoder = link->link_enc;
-+
-+	pattern_param.dp_phy_pattern = test_pattern;
-+	pattern_param.custom_pattern = custom_pattern;
-+	pattern_param.custom_pattern_size = custom_pattern_size;
-+	pattern_param.dp_panel_mode = dp_get_panel_mode(link);
-+
-+	encoder->funcs->dp_set_phy_pattern(encoder, &pattern_param);
-+}
-+
-+void dp_retrain_link_dp_test(struct dc_link *link,
-+			struct dc_link_settings *link_setting,
-+			bool skip_video_pattern)
-+{
-+	struct pipe_ctx *pipes =
-+			&link->dc->current_state->res_ctx.pipe_ctx[0];
-+	unsigned int i;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (pipes[i].stream != NULL &&
-+			pipes[i].stream->sink != NULL &&
-+			pipes[i].stream->sink->link != NULL &&
-+			pipes[i].stream_res.stream_enc != NULL &&
-+			pipes[i].stream->sink->link == link) {
-+			udelay(100);
-+
-+			pipes[i].stream_res.stream_enc->funcs->dp_blank(
-+					pipes[i].stream_res.stream_enc);
-+
-+			/* disable any test pattern that might be active */
-+			dp_set_hw_test_pattern(link,
-+					DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
-+
-+			dp_receiver_power_ctrl(link, false);
-+
-+			link->dc->hwss.disable_stream(&pipes[i], KEEP_ACQUIRED_RESOURCE);
-+
-+			link->link_enc->funcs->disable_output(
-+					link->link_enc,
-+					SIGNAL_TYPE_DISPLAY_PORT);
-+
-+			/* Clear current link setting. */
-+			memset(&link->cur_link_settings, 0,
-+				sizeof(link->cur_link_settings));
-+
-+			link->link_enc->funcs->enable_dp_output(
-+						link->link_enc,
-+						link_setting,
-+						pipes[i].clock_source->id);
-+
-+			dp_receiver_power_ctrl(link, true);
-+
-+			perform_link_training_with_retries(
-+					link,
-+					link_setting,
-+					skip_video_pattern,
-+					LINK_TRAINING_ATTEMPTS);
-+
-+			link->cur_link_settings = *link_setting;
-+
-+			link->dc->hwss.enable_stream(&pipes[i]);
-+
-+			link->dc->hwss.unblank_stream(&pipes[i],
-+					link_setting);
-+
-+			if (pipes[i].stream_res.audio) {
-+				/* notify audio driver for
-+				 * audio modes of monitor */
-+				pipes[i].stream_res.audio->funcs->az_enable(
-+						pipes[i].stream_res.audio);
-+
-+				/* un-mute audio */
-+				/* TODO: audio should be per stream rather than
-+				 * per link */
-+				pipes[i].stream_res.stream_enc->funcs->
-+				audio_mute_control(
-+					pipes[i].stream_res.stream_enc, false);
-+			}
-+		}
-+	}
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_resource.c.0130~	2017-12-14 06:39:58.407903562 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_resource.c	2017-12-14 06:39:58.407903562 +0100
-@@ -0,0 +1,2783 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dm_services.h"
-+
-+#include "resource.h"
-+#include "include/irq_service_interface.h"
-+#include "link_encoder.h"
-+#include "stream_encoder.h"
-+#include "opp.h"
-+#include "timing_generator.h"
-+#include "transform.h"
-+#include "dpp.h"
-+#include "core_types.h"
-+#include "set_mode_types.h"
-+#include "virtual/virtual_stream_encoder.h"
-+
-+#include "dce80/dce80_resource.h"
-+#include "dce100/dce100_resource.h"
-+#include "dce110/dce110_resource.h"
-+#include "dce112/dce112_resource.h"
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+#include "dcn10/dcn10_resource.h"
-+#endif
-+#include "dce120/dce120_resource.h"
-+
-+enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
-+{
-+	enum dce_version dc_version = DCE_VERSION_UNKNOWN;
-+	switch (asic_id.chip_family) {
-+
-+	case FAMILY_CI:
-+		dc_version = DCE_VERSION_8_0;
-+		break;
-+	case FAMILY_KV:
-+		if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
-+		    ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
-+		    ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
-+			dc_version = DCE_VERSION_8_3;
-+		else
-+			dc_version = DCE_VERSION_8_1;
-+		break;
-+	case FAMILY_CZ:
-+		dc_version = DCE_VERSION_11_0;
-+		break;
-+
-+	case FAMILY_VI:
-+		if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
-+				ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
-+			dc_version = DCE_VERSION_10_0;
-+			break;
-+		}
-+		if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
-+				ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
-+				ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
-+			dc_version = DCE_VERSION_11_2;
-+		}
-+		break;
-+	case FAMILY_AI:
-+		dc_version = DCE_VERSION_12_0;
-+		break;
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	case FAMILY_RV:
-+		dc_version = DCN_VERSION_1_0;
-+		break;
-+#endif
-+	default:
-+		dc_version = DCE_VERSION_UNKNOWN;
-+		break;
-+	}
-+	return dc_version;
-+}
-+
-+struct resource_pool *dc_create_resource_pool(
-+				struct dc  *dc,
-+				int num_virtual_links,
-+				enum dce_version dc_version,
-+				struct hw_asic_id asic_id)
-+{
-+	struct resource_pool *res_pool = NULL;
-+
-+	switch (dc_version) {
-+	case DCE_VERSION_8_0:
-+		res_pool = dce80_create_resource_pool(
-+			num_virtual_links, dc);
-+		break;
-+	case DCE_VERSION_8_1:
-+		res_pool = dce81_create_resource_pool(
-+			num_virtual_links, dc);
-+		break;
-+	case DCE_VERSION_8_3:
-+		res_pool = dce83_create_resource_pool(
-+			num_virtual_links, dc);
-+		break;
-+	case DCE_VERSION_10_0:
-+		res_pool = dce100_create_resource_pool(
-+				num_virtual_links, dc);
-+		break;
-+	case DCE_VERSION_11_0:
-+		res_pool = dce110_create_resource_pool(
-+			num_virtual_links, dc, asic_id);
-+		break;
-+	case DCE_VERSION_11_2:
-+		res_pool = dce112_create_resource_pool(
-+			num_virtual_links, dc);
-+		break;
-+	case DCE_VERSION_12_0:
-+		res_pool = dce120_create_resource_pool(
-+			num_virtual_links, dc);
-+		break;
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	case DCN_VERSION_1_0:
-+		res_pool = dcn10_create_resource_pool(
-+				num_virtual_links, dc);
-+		break;
-+#endif
-+
-+
-+	default:
-+		break;
-+	}
-+	if (res_pool != NULL) {
-+		struct dc_firmware_info fw_info = { { 0 } };
-+
-+		if (dc->ctx->dc_bios->funcs->get_firmware_info(
-+				dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
-+				res_pool->ref_clock_inKhz = fw_info.pll_info.crystal_frequency;
-+			} else
-+				ASSERT_CRITICAL(false);
-+	}
-+
-+	return res_pool;
-+}
-+
-+void dc_destroy_resource_pool(struct dc  *dc)
-+{
-+	if (dc) {
-+		if (dc->res_pool)
-+			dc->res_pool->funcs->destroy(&dc->res_pool);
-+
-+		kfree(dc->hwseq);
-+	}
-+}
-+
-+static void update_num_audio(
-+	const struct resource_straps *straps,
-+	unsigned int *num_audio,
-+	struct audio_support *aud_support)
-+{
-+	aud_support->dp_audio = true;
-+	aud_support->hdmi_audio_native = false;
-+	aud_support->hdmi_audio_on_dongle = false;
-+
-+	if (straps->hdmi_disable == 0) {
-+		if (straps->dc_pinstraps_audio & 0x2) {
-+			aud_support->hdmi_audio_on_dongle = true;
-+			aud_support->hdmi_audio_native = true;
-+		}
-+	}
-+
-+	switch (straps->audio_stream_number) {
-+	case 0: /* multi streams supported */
-+		break;
-+	case 1: /* multi streams not supported */
-+		*num_audio = 1;
-+		break;
-+	default:
-+		DC_ERR("DC: unexpected audio fuse!\n");
-+	}
-+}
-+
-+bool resource_construct(
-+	unsigned int num_virtual_links,
-+	struct dc  *dc,
-+	struct resource_pool *pool,
-+	const struct resource_create_funcs *create_funcs)
-+{
-+	struct dc_context *ctx = dc->ctx;
-+	const struct resource_caps *caps = pool->res_cap;
-+	int i;
-+	unsigned int num_audio = caps->num_audio;
-+	struct resource_straps straps = {0};
-+
-+	if (create_funcs->read_dce_straps)
-+		create_funcs->read_dce_straps(dc->ctx, &straps);
-+
-+	pool->audio_count = 0;
-+	if (create_funcs->create_audio) {
-+		/* find the total number of streams available via the
-+		 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
-+		 * registers (one for each pin) starting from pin 1
-+		 * up to the max number of audio pins.
-+		 * We stop on the first pin where
-+		 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
-+		 */
-+		update_num_audio(&straps, &num_audio, &pool->audio_support);
-+		for (i = 0; i < pool->pipe_count && i < num_audio; i++) {
-+			struct audio *aud = create_funcs->create_audio(ctx, i);
-+
-+			if (aud == NULL) {
-+				DC_ERR("DC: failed to create audio!\n");
-+				return false;
-+			}
-+
-+			if (!aud->funcs->endpoint_valid(aud)) {
-+				aud->funcs->destroy(&aud);
-+				break;
-+			}
-+
-+			pool->audios[i] = aud;
-+			pool->audio_count++;
-+		}
-+	}
-+
-+	pool->stream_enc_count = 0;
-+	if (create_funcs->create_stream_encoder) {
-+		for (i = 0; i < caps->num_stream_encoder; i++) {
-+			pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
-+			if (pool->stream_enc[i] == NULL)
-+				DC_ERR("DC: failed to create stream_encoder!\n");
-+			pool->stream_enc_count++;
-+		}
-+	}
-+	dc->caps.dynamic_audio = false;
-+	if (pool->audio_count < pool->stream_enc_count) {
-+		dc->caps.dynamic_audio = true;
-+	}
-+	for (i = 0; i < num_virtual_links; i++) {
-+		pool->stream_enc[pool->stream_enc_count] =
-+			virtual_stream_encoder_create(
-+					ctx, ctx->dc_bios);
-+		if (pool->stream_enc[pool->stream_enc_count] == NULL) {
-+			DC_ERR("DC: failed to create stream_encoder!\n");
-+			return false;
-+		}
-+		pool->stream_enc_count++;
-+	}
-+
-+	dc->hwseq = create_funcs->create_hwseq(ctx);
-+
-+	return true;
-+}
-+
-+
-+void resource_unreference_clock_source(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool,
-+		struct clock_source *clock_source)
-+{
-+	int i;
-+
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] != clock_source)
-+			continue;
-+
-+		res_ctx->clock_source_ref_count[i]--;
-+
-+		break;
-+	}
-+
-+	if (pool->dp_clock_source == clock_source)
-+		res_ctx->dp_clock_source_ref_count--;
-+}
-+
-+void resource_reference_clock_source(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool,
-+		struct clock_source *clock_source)
-+{
-+	int i;
-+	for (i = 0; i < pool->clk_src_count; i++) {
-+		if (pool->clock_sources[i] != clock_source)
-+			continue;
-+
-+		res_ctx->clock_source_ref_count[i]++;
-+		break;
-+	}
-+
-+	if (pool->dp_clock_source == clock_source)
-+		res_ctx->dp_clock_source_ref_count++;
-+}
-+
-+bool resource_are_streams_timing_synchronizable(
-+	struct dc_stream_state *stream1,
-+	struct dc_stream_state *stream2)
-+{
-+	if (stream1->timing.h_total != stream2->timing.h_total)
-+		return false;
-+
-+	if (stream1->timing.v_total != stream2->timing.v_total)
-+		return false;
-+
-+	if (stream1->timing.h_addressable
-+				!= stream2->timing.h_addressable)
-+		return false;
-+
-+	if (stream1->timing.v_addressable
-+				!= stream2->timing.v_addressable)
-+		return false;
-+
-+	if (stream1->timing.pix_clk_khz
-+				!= stream2->timing.pix_clk_khz)
-+		return false;
-+
-+	if (stream1->phy_pix_clk != stream2->phy_pix_clk
-+			&& (!dc_is_dp_signal(stream1->signal)
-+			|| !dc_is_dp_signal(stream2->signal)))
-+		return false;
-+
-+	return true;
-+}
-+
-+static bool is_sharable_clk_src(
-+	const struct pipe_ctx *pipe_with_clk_src,
-+	const struct pipe_ctx *pipe)
-+{
-+	if (pipe_with_clk_src->clock_source == NULL)
-+		return false;
-+
-+	if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
-+		return false;
-+
-+	if (dc_is_dp_signal(pipe_with_clk_src->stream->signal))
-+		return false;
-+
-+	if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
-+			&& dc_is_dvi_signal(pipe->stream->signal))
-+		return false;
-+
-+	if (dc_is_hdmi_signal(pipe->stream->signal)
-+			&& dc_is_dvi_signal(pipe_with_clk_src->stream->signal))
-+		return false;
-+
-+	if (!resource_are_streams_timing_synchronizable(
-+			pipe_with_clk_src->stream, pipe->stream))
-+		return false;
-+
-+	return true;
-+}
-+
-+struct clock_source *resource_find_used_clk_src_for_sharing(
-+					struct resource_context *res_ctx,
-+					struct pipe_ctx *pipe_ctx)
-+{
-+	int i;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
-+			return res_ctx->pipe_ctx[i].clock_source;
-+	}
-+
-+	return NULL;
-+}
-+
-+static enum pixel_format convert_pixel_format_to_dalsurface(
-+		enum surface_pixel_format surface_pixel_format)
-+{
-+	enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
-+
-+	switch (surface_pixel_format) {
-+	case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
-+		dal_pixel_format = PIXEL_FORMAT_INDEX8;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
-+		dal_pixel_format = PIXEL_FORMAT_RGB565;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
-+		dal_pixel_format = PIXEL_FORMAT_RGB565;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+		dal_pixel_format = PIXEL_FORMAT_ARGB8888;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
-+		dal_pixel_format = PIXEL_FORMAT_ARGB8888;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+		dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+		dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
-+		dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
-+		dal_pixel_format = PIXEL_FORMAT_FP16;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
-+		dal_pixel_format = PIXEL_FORMAT_420BPP8;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
-+		dal_pixel_format = PIXEL_FORMAT_420BPP10;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+	default:
-+		dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
-+		break;
-+	}
-+	return dal_pixel_format;
-+}
-+
-+static void rect_swap_helper(struct rect *rect)
-+{
-+	swap(rect->height, rect->width);
-+	swap(rect->x, rect->y);
-+}
-+
-+static void calculate_viewport(struct pipe_ctx *pipe_ctx)
-+{
-+	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-+	const struct dc_stream_state *stream = pipe_ctx->stream;
-+	struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
-+	struct rect surf_src = plane_state->src_rect;
-+	struct rect clip = { 0 };
-+	int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
-+			|| data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
-+	bool pri_split = pipe_ctx->bottom_pipe &&
-+			pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
-+	bool sec_split = pipe_ctx->top_pipe &&
-+			pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
-+
-+	if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
-+		stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
-+		pri_split = false;
-+		sec_split = false;
-+	}
-+
-+	if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
-+			pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
-+		rect_swap_helper(&surf_src);
-+
-+	/* The actual clip is an intersection between stream
-+	 * source and surface clip
-+	 */
-+	clip.x = stream->src.x > plane_state->clip_rect.x ?
-+			stream->src.x : plane_state->clip_rect.x;
-+
-+	clip.width = stream->src.x + stream->src.width <
-+			plane_state->clip_rect.x + plane_state->clip_rect.width ?
-+			stream->src.x + stream->src.width - clip.x :
-+			plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
-+
-+	clip.y = stream->src.y > plane_state->clip_rect.y ?
-+			stream->src.y : plane_state->clip_rect.y;
-+
-+	clip.height = stream->src.y + stream->src.height <
-+			plane_state->clip_rect.y + plane_state->clip_rect.height ?
-+			stream->src.y + stream->src.height - clip.y :
-+			plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
-+
-+	/* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
-+	 * num_pixels = clip.num_pix * scl_ratio
-+	 */
-+	data->viewport.x = surf_src.x + (clip.x - plane_state->dst_rect.x) *
-+			surf_src.width / plane_state->dst_rect.width;
-+	data->viewport.width = clip.width *
-+			surf_src.width / plane_state->dst_rect.width;
-+
-+	data->viewport.y = surf_src.y + (clip.y - plane_state->dst_rect.y) *
-+			surf_src.height / plane_state->dst_rect.height;
-+	data->viewport.height = clip.height *
-+			surf_src.height / plane_state->dst_rect.height;
-+
-+	/* Round down, compensate in init */
-+	data->viewport_c.x = data->viewport.x / vpc_div;
-+	data->viewport_c.y = data->viewport.y / vpc_div;
-+	data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
-+			dal_fixed31_32_half : dal_fixed31_32_zero;
-+	data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
-+			dal_fixed31_32_half : dal_fixed31_32_zero;
-+	/* Round up, assume original video size always even dimensions */
-+	data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
-+	data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
-+
-+	/* Handle hsplit */
-+	if (pri_split || sec_split) {
-+		/* HMirror XOR Secondary_pipe XOR Rotation_180 */
-+		bool right_view = (sec_split != plane_state->horizontal_mirror) !=
-+					(plane_state->rotation == ROTATION_ANGLE_180);
-+
-+		if (plane_state->rotation == ROTATION_ANGLE_90
-+				|| plane_state->rotation == ROTATION_ANGLE_270)
-+			/* Secondary_pipe XOR Rotation_270 */
-+			right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split;
-+
-+		if (right_view) {
-+			data->viewport.width /= 2;
-+			data->viewport_c.width /= 2;
-+			data->viewport.x +=  data->viewport.width;
-+			data->viewport_c.x +=  data->viewport_c.width;
-+			/* Ceil offset pipe */
-+			data->viewport.width += data->viewport.width % 2;
-+			data->viewport_c.width += data->viewport_c.width % 2;
-+		} else {
-+			data->viewport.width /= 2;
-+			data->viewport_c.width /= 2;
-+		}
-+	}
-+
-+	if (plane_state->rotation == ROTATION_ANGLE_90 ||
-+			plane_state->rotation == ROTATION_ANGLE_270) {
-+		rect_swap_helper(&data->viewport_c);
-+		rect_swap_helper(&data->viewport);
-+	}
-+}
-+
-+static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
-+{
-+	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-+	const struct dc_stream_state *stream = pipe_ctx->stream;
-+	struct rect surf_src = plane_state->src_rect;
-+	struct rect surf_clip = plane_state->clip_rect;
-+	int recout_full_x, recout_full_y;
-+
-+	if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
-+			pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
-+		rect_swap_helper(&surf_src);
-+
-+	pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
-+	if (stream->src.x < surf_clip.x)
-+		pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
-+			- stream->src.x) * stream->dst.width
-+						/ stream->src.width;
-+
-+	pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
-+			stream->dst.width / stream->src.width;
-+	if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
-+			stream->dst.x + stream->dst.width)
-+		pipe_ctx->plane_res.scl_data.recout.width =
-+			stream->dst.x + stream->dst.width
-+						- pipe_ctx->plane_res.scl_data.recout.x;
-+
-+	pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
-+	if (stream->src.y < surf_clip.y)
-+		pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
-+			- stream->src.y) * stream->dst.height
-+						/ stream->src.height;
-+
-+	pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
-+			stream->dst.height / stream->src.height;
-+	if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
-+			stream->dst.y + stream->dst.height)
-+		pipe_ctx->plane_res.scl_data.recout.height =
-+			stream->dst.y + stream->dst.height
-+						- pipe_ctx->plane_res.scl_data.recout.y;
-+
-+	/* Handle h & vsplit */
-+	if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state ==
-+		pipe_ctx->plane_state) {
-+		if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
-+			pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height / 2;
-+			/* Floor primary pipe, ceil 2ndary pipe */
-+			pipe_ctx->plane_res.scl_data.recout.height = (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
-+		} else {
-+			pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width / 2;
-+			pipe_ctx->plane_res.scl_data.recout.width = (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
-+		}
-+	} else if (pipe_ctx->bottom_pipe &&
-+			pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state) {
-+		if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
-+			pipe_ctx->plane_res.scl_data.recout.height /= 2;
-+		else
-+			pipe_ctx->plane_res.scl_data.recout.width /= 2;
-+	}
-+
-+	/* Unclipped recout offset = stream dst offset + ((surf dst offset - stream surf_src offset)
-+	 * 				* 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl
-+	 * 				ratio)
-+	 */
-+	recout_full_x = stream->dst.x + (plane_state->dst_rect.x -  stream->src.x)
-+					* stream->dst.width / stream->src.width -
-+			surf_src.x * plane_state->dst_rect.width / surf_src.width
-+					* stream->dst.width / stream->src.width;
-+	recout_full_y = stream->dst.y + (plane_state->dst_rect.y -  stream->src.y)
-+					* stream->dst.height / stream->src.height -
-+			surf_src.y * plane_state->dst_rect.height / surf_src.height
-+					* stream->dst.height / stream->src.height;
-+
-+	recout_skip->width = pipe_ctx->plane_res.scl_data.recout.x - recout_full_x;
-+	recout_skip->height = pipe_ctx->plane_res.scl_data.recout.y - recout_full_y;
-+}
-+
-+static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
-+{
-+	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-+	const struct dc_stream_state *stream = pipe_ctx->stream;
-+	struct rect surf_src = plane_state->src_rect;
-+	const int in_w = stream->src.width;
-+	const int in_h = stream->src.height;
-+	const int out_w = stream->dst.width;
-+	const int out_h = stream->dst.height;
-+
-+	if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
-+			pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
-+		rect_swap_helper(&surf_src);
-+
-+	pipe_ctx->plane_res.scl_data.ratios.horz = dal_fixed31_32_from_fraction(
-+					surf_src.width,
-+					plane_state->dst_rect.width);
-+	pipe_ctx->plane_res.scl_data.ratios.vert = dal_fixed31_32_from_fraction(
-+					surf_src.height,
-+					plane_state->dst_rect.height);
-+
-+	if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
-+		pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
-+	else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
-+		pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
-+
-+	pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
-+		pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
-+	pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
-+		pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
-+
-+	pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
-+	pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
-+
-+	if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
-+			|| pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
-+		pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
-+		pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
-+	}
-+}
-+
-+static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
-+{
-+	struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
-+	struct rect src = pipe_ctx->plane_state->src_rect;
-+	int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
-+			|| data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
-+
-+
-+	if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
-+			pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
-+		rect_swap_helper(&src);
-+		rect_swap_helper(&data->viewport_c);
-+		rect_swap_helper(&data->viewport);
-+	}
-+
-+	/*
-+	 * Init calculated according to formula:
-+	 * 	init = (scaling_ratio + number_of_taps + 1) / 2
-+	 * 	init_bot = init + scaling_ratio
-+	 * 	init_c = init + truncated_vp_c_offset(from calculate viewport)
-+	 */
-+	data->inits.h = dal_fixed31_32_div_int(
-+			dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
-+
-+	data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int(
-+			dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
-+
-+	data->inits.v = dal_fixed31_32_div_int(
-+			dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
-+
-+	data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int(
-+			dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
-+
-+
-+	/* Adjust for viewport end clip-off */
-+	if ((data->viewport.x + data->viewport.width) < (src.x + src.width)) {
-+		int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
-+		int int_part = dal_fixed31_32_floor(
-+				dal_fixed31_32_sub(data->inits.h, data->ratios.horz));
-+
-+		int_part = int_part > 0 ? int_part : 0;
-+		data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
-+	}
-+	if ((data->viewport.y + data->viewport.height) < (src.y + src.height)) {
-+		int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
-+		int int_part = dal_fixed31_32_floor(
-+				dal_fixed31_32_sub(data->inits.v, data->ratios.vert));
-+
-+		int_part = int_part > 0 ? int_part : 0;
-+		data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
-+	}
-+	if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div) {
-+		int vp_clip = (src.x + src.width) / vpc_div -
-+				data->viewport_c.width - data->viewport_c.x;
-+		int int_part = dal_fixed31_32_floor(
-+				dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c));
-+
-+		int_part = int_part > 0 ? int_part : 0;
-+		data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
-+	}
-+	if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div) {
-+		int vp_clip = (src.y + src.height) / vpc_div -
-+				data->viewport_c.height - data->viewport_c.y;
-+		int int_part = dal_fixed31_32_floor(
-+				dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c));
-+
-+		int_part = int_part > 0 ? int_part : 0;
-+		data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
-+	}
-+
-+	/* Adjust for non-0 viewport offset */
-+	if (data->viewport.x) {
-+		int int_part;
-+
-+		data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
-+				data->ratios.horz, recout_skip->width));
-+		int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x;
-+		if (int_part < data->taps.h_taps) {
-+			int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
-+						(data->taps.h_taps - int_part) : data->viewport.x;
-+			data->viewport.x -= int_adj;
-+			data->viewport.width += int_adj;
-+			int_part += int_adj;
-+		} else if (int_part > data->taps.h_taps) {
-+			data->viewport.x += int_part - data->taps.h_taps;
-+			data->viewport.width -= int_part - data->taps.h_taps;
-+			int_part = data->taps.h_taps;
-+		}
-+		data->inits.h.value &= 0xffffffff;
-+		data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
-+	}
-+
-+	if (data->viewport_c.x) {
-+		int int_part;
-+
-+		data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
-+				data->ratios.horz_c, recout_skip->width));
-+		int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x;
-+		if (int_part < data->taps.h_taps_c) {
-+			int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
-+					(data->taps.h_taps_c - int_part) : data->viewport_c.x;
-+			data->viewport_c.x -= int_adj;
-+			data->viewport_c.width += int_adj;
-+			int_part += int_adj;
-+		} else if (int_part > data->taps.h_taps_c) {
-+			data->viewport_c.x += int_part - data->taps.h_taps_c;
-+			data->viewport_c.width -= int_part - data->taps.h_taps_c;
-+			int_part = data->taps.h_taps_c;
-+		}
-+		data->inits.h_c.value &= 0xffffffff;
-+		data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
-+	}
-+
-+	if (data->viewport.y) {
-+		int int_part;
-+
-+		data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
-+				data->ratios.vert, recout_skip->height));
-+		int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y;
-+		if (int_part < data->taps.v_taps) {
-+			int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
-+						(data->taps.v_taps - int_part) : data->viewport.y;
-+			data->viewport.y -= int_adj;
-+			data->viewport.height += int_adj;
-+			int_part += int_adj;
-+		} else if (int_part > data->taps.v_taps) {
-+			data->viewport.y += int_part - data->taps.v_taps;
-+			data->viewport.height -= int_part - data->taps.v_taps;
-+			int_part = data->taps.v_taps;
-+		}
-+		data->inits.v.value &= 0xffffffff;
-+		data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
-+	}
-+
-+	if (data->viewport_c.y) {
-+		int int_part;
-+
-+		data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
-+				data->ratios.vert_c, recout_skip->height));
-+		int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y;
-+		if (int_part < data->taps.v_taps_c) {
-+			int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
-+					(data->taps.v_taps_c - int_part) : data->viewport_c.y;
-+			data->viewport_c.y -= int_adj;
-+			data->viewport_c.height += int_adj;
-+			int_part += int_adj;
-+		} else if (int_part > data->taps.v_taps_c) {
-+			data->viewport_c.y += int_part - data->taps.v_taps_c;
-+			data->viewport_c.height -= int_part - data->taps.v_taps_c;
-+			int_part = data->taps.v_taps_c;
-+		}
-+		data->inits.v_c.value &= 0xffffffff;
-+		data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part);
-+	}
-+
-+	/* Interlaced inits based on final vert inits */
-+	data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
-+	data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
-+
-+	if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
-+			pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
-+		rect_swap_helper(&data->viewport_c);
-+		rect_swap_helper(&data->viewport);
-+	}
-+}
-+
-+bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
-+{
-+	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-+	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
-+	struct view recout_skip = { 0 };
-+	bool res = false;
-+
-+	/* Important: scaling ratio calculation requires pixel format,
-+	 * lb depth calculation requires recout and taps require scaling ratios.
-+	 * Inits require viewport, taps, ratios and recout of split pipe
-+	 */
-+	pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
-+			pipe_ctx->plane_state->format);
-+
-+	calculate_scaling_ratios(pipe_ctx);
-+
-+	calculate_viewport(pipe_ctx);
-+
-+	if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
-+		return false;
-+
-+	calculate_recout(pipe_ctx, &recout_skip);
-+
-+	/**
-+	 * Setting line buffer pixel depth to 24bpp yields banding
-+	 * on certain displays, such as the Sharp 4k
-+	 */
-+	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
-+
-+	pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
-+	pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
-+
-+	pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
-+	pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
-+
-+
-+	/* Taps calculations */
-+	if (pipe_ctx->plane_res.xfm != NULL)
-+		res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
-+				pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
-+
-+	if (pipe_ctx->plane_res.dpp != NULL)
-+		res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
-+				pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
-+	if (!res) {
-+		/* Try 24 bpp linebuffer */
-+		pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
-+
-+		if (pipe_ctx->plane_res.xfm != NULL)
-+			res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
-+					pipe_ctx->plane_res.xfm,
-+					&pipe_ctx->plane_res.scl_data,
-+					&plane_state->scaling_quality);
-+
-+		if (pipe_ctx->plane_res.dpp != NULL)
-+			res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
-+					pipe_ctx->plane_res.dpp,
-+					&pipe_ctx->plane_res.scl_data,
-+					&plane_state->scaling_quality);
-+	}
-+
-+	if (res)
-+		/* May need to re-check lb size after this in some obscure scenario */
-+		calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
-+
-+	dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
-+				"%s: Viewport:\nheight:%d width:%d x:%d "
-+				"y:%d\n dst_rect:\nheight:%d width:%d x:%d "
-+				"y:%d\n",
-+				__func__,
-+				pipe_ctx->plane_res.scl_data.viewport.height,
-+				pipe_ctx->plane_res.scl_data.viewport.width,
-+				pipe_ctx->plane_res.scl_data.viewport.x,
-+				pipe_ctx->plane_res.scl_data.viewport.y,
-+				plane_state->dst_rect.height,
-+				plane_state->dst_rect.width,
-+				plane_state->dst_rect.x,
-+				plane_state->dst_rect.y);
-+
-+	return res;
-+}
-+
-+
-+enum dc_status resource_build_scaling_params_for_context(
-+	const struct dc  *dc,
-+	struct dc_state *context)
-+{
-+	int i;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
-+				context->res_ctx.pipe_ctx[i].stream != NULL)
-+			if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
-+				return DC_FAIL_SCALING;
-+	}
-+
-+	return DC_OK;
-+}
-+
-+struct pipe_ctx *find_idle_secondary_pipe(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool)
-+{
-+	int i;
-+	struct pipe_ctx *secondary_pipe = NULL;
-+
-+	/*
-+	 * search backwards for the second pipe to keep pipe
-+	 * assignment more consistent
-+	 */
-+
-+	for (i = pool->pipe_count - 1; i >= 0; i--) {
-+		if (res_ctx->pipe_ctx[i].stream == NULL) {
-+			secondary_pipe = &res_ctx->pipe_ctx[i];
-+			secondary_pipe->pipe_idx = i;
-+			break;
-+		}
-+	}
-+
-+
-+	return secondary_pipe;
-+}
-+
-+struct pipe_ctx *resource_get_head_pipe_for_stream(
-+		struct resource_context *res_ctx,
-+		struct dc_stream_state *stream)
-+{
-+	int i;
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (res_ctx->pipe_ctx[i].stream == stream &&
-+				!res_ctx->pipe_ctx[i].top_pipe) {
-+			return &res_ctx->pipe_ctx[i];
-+			break;
-+		}
-+	}
-+	return NULL;
-+}
-+
-+static struct pipe_ctx *resource_get_tail_pipe_for_stream(
-+		struct resource_context *res_ctx,
-+		struct dc_stream_state *stream)
-+{
-+	struct pipe_ctx *head_pipe, *tail_pipe;
-+	head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
-+
-+	if (!head_pipe)
-+		return NULL;
-+
-+	tail_pipe = head_pipe->bottom_pipe;
-+
-+	while (tail_pipe) {
-+		head_pipe = tail_pipe;
-+		tail_pipe = tail_pipe->bottom_pipe;
-+	}
-+
-+	return head_pipe;
-+}
-+
-+/*
-+ * A free_pipe for a stream is defined here as a pipe
-+ * that has no surface attached yet
-+ */
-+static struct pipe_ctx *acquire_free_pipe_for_stream(
-+		struct dc_state *context,
-+		const struct resource_pool *pool,
-+		struct dc_stream_state *stream)
-+{
-+	int i;
-+	struct resource_context *res_ctx = &context->res_ctx;
-+
-+	struct pipe_ctx *head_pipe = NULL;
-+
-+	/* Find head pipe, which has the back end set up*/
-+
-+	head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
-+
-+	if (!head_pipe)
-+		ASSERT(0);
-+
-+	if (!head_pipe->plane_state)
-+		return head_pipe;
-+
-+	/* Re-use pipe already acquired for this stream if available*/
-+	for (i = pool->pipe_count - 1; i >= 0; i--) {
-+		if (res_ctx->pipe_ctx[i].stream == stream &&
-+				!res_ctx->pipe_ctx[i].plane_state) {
-+			return &res_ctx->pipe_ctx[i];
-+		}
-+	}
-+
-+	/*
-+	 * At this point we have no re-useable pipe for this stream and we need
-+	 * to acquire an idle one to satisfy the request
-+	 */
-+
-+	if (!pool->funcs->acquire_idle_pipe_for_layer)
-+		return NULL;
-+
-+	return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
-+
-+}
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+static int acquire_first_split_pipe(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool,
-+		struct dc_stream_state *stream)
-+{
-+	int i;
-+
-+	for (i = 0; i < pool->pipe_count; i++) {
-+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
-+
-+		if (pipe_ctx->top_pipe &&
-+				pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) {
-+			pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
-+			if (pipe_ctx->bottom_pipe)
-+				pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
-+
-+			memset(pipe_ctx, 0, sizeof(*pipe_ctx));
-+			pipe_ctx->stream_res.tg = pool->timing_generators[i];
-+			pipe_ctx->plane_res.hubp = pool->hubps[i];
-+			pipe_ctx->plane_res.ipp = pool->ipps[i];
-+			pipe_ctx->plane_res.dpp = pool->dpps[i];
-+			pipe_ctx->stream_res.opp = pool->opps[i];
-+			pipe_ctx->pipe_idx = i;
-+
-+			pipe_ctx->stream = stream;
-+			return i;
-+		}
-+	}
-+	return -1;
-+}
-+#endif
-+
-+bool dc_add_plane_to_context(
-+		const struct dc *dc,
-+		struct dc_stream_state *stream,
-+		struct dc_plane_state *plane_state,
-+		struct dc_state *context)
-+{
-+	int i;
-+	struct resource_pool *pool = dc->res_pool;
-+	struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
-+	struct dc_stream_status *stream_status = NULL;
-+
-+	for (i = 0; i < context->stream_count; i++)
-+		if (context->streams[i] == stream) {
-+			stream_status = &context->stream_status[i];
-+			break;
-+		}
-+	if (stream_status == NULL) {
-+		dm_error("Existing stream not found; failed to attach surface!\n");
-+		return false;
-+	}
-+
-+
-+	if (stream_status->plane_count == MAX_SURFACE_NUM) {
-+		dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
-+				plane_state, MAX_SURFACE_NUM);
-+		return false;
-+	}
-+
-+	head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
-+
-+	if (!head_pipe) {
-+		dm_error("Head pipe not found for stream_state %p !\n", stream);
-+		return false;
-+	}
-+
-+	free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	if (!free_pipe) {
-+		int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
-+		if (pipe_idx >= 0)
-+			free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
-+	}
-+#endif
-+	if (!free_pipe)
-+		return false;
-+
-+	/* retain new surfaces */
-+	dc_plane_state_retain(plane_state);
-+	free_pipe->plane_state = plane_state;
-+
-+	if (head_pipe != free_pipe) {
-+
-+		tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
-+		ASSERT(tail_pipe);
-+
-+		free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
-+		free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
-+		free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
-+		free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
-+		free_pipe->clock_source = tail_pipe->clock_source;
-+		free_pipe->top_pipe = tail_pipe;
-+		tail_pipe->bottom_pipe = free_pipe;
-+	}
-+
-+	/* assign new surfaces*/
-+	stream_status->plane_states[stream_status->plane_count] = plane_state;
-+
-+	stream_status->plane_count++;
-+
-+	return true;
-+}
-+
-+bool dc_remove_plane_from_context(
-+		const struct dc *dc,
-+		struct dc_stream_state *stream,
-+		struct dc_plane_state *plane_state,
-+		struct dc_state *context)
-+{
-+	int i;
-+	struct dc_stream_status *stream_status = NULL;
-+	struct resource_pool *pool = dc->res_pool;
-+
-+	for (i = 0; i < context->stream_count; i++)
-+		if (context->streams[i] == stream) {
-+			stream_status = &context->stream_status[i];
-+			break;
-+		}
-+
-+	if (stream_status == NULL) {
-+		dm_error("Existing stream not found; failed to remove plane.\n");
-+		return false;
-+	}
-+
-+	/* release pipe for plane*/
-+	for (i = pool->pipe_count - 1; i >= 0; i--) {
-+		struct pipe_ctx *pipe_ctx;
-+
-+		if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) {
-+			pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+			if (pipe_ctx->top_pipe)
-+				pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
-+
-+			/* Second condition is to avoid setting NULL to top pipe
-+			 * of tail pipe making it look like head pipe in subsequent
-+			 * deletes
-+			 */
-+			if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
-+				pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
-+
-+			/*
-+			 * For head pipe detach surfaces from pipe for tail
-+			 * pipe just zero it out
-+			 */
-+			if (!pipe_ctx->top_pipe) {
-+				pipe_ctx->plane_state = NULL;
-+				pipe_ctx->bottom_pipe = NULL;
-+			} else  {
-+				memset(pipe_ctx, 0, sizeof(*pipe_ctx));
-+			}
-+		}
-+	}
-+
-+
-+	for (i = 0; i < stream_status->plane_count; i++) {
-+		if (stream_status->plane_states[i] == plane_state) {
-+
-+			dc_plane_state_release(stream_status->plane_states[i]);
-+			break;
-+		}
-+	}
-+
-+	if (i == stream_status->plane_count) {
-+		dm_error("Existing plane_state not found; failed to detach it!\n");
-+		return false;
-+	}
-+
-+	stream_status->plane_count--;
-+
-+	/* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
-+	for (; i < stream_status->plane_count; i++)
-+		stream_status->plane_states[i] = stream_status->plane_states[i + 1];
-+
-+	stream_status->plane_states[stream_status->plane_count] = NULL;
-+
-+	return true;
-+}
-+
-+bool dc_rem_all_planes_for_stream(
-+		const struct dc *dc,
-+		struct dc_stream_state *stream,
-+		struct dc_state *context)
-+{
-+	int i, old_plane_count;
-+	struct dc_stream_status *stream_status = NULL;
-+	struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
-+
-+	for (i = 0; i < context->stream_count; i++)
-+			if (context->streams[i] == stream) {
-+				stream_status = &context->stream_status[i];
-+				break;
-+			}
-+
-+	if (stream_status == NULL) {
-+		dm_error("Existing stream %p not found!\n", stream);
-+		return false;
-+	}
-+
-+	old_plane_count = stream_status->plane_count;
-+
-+	for (i = 0; i < old_plane_count; i++)
-+		del_planes[i] = stream_status->plane_states[i];
-+
-+	for (i = 0; i < old_plane_count; i++)
-+		if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
-+			return false;
-+
-+	return true;
-+}
-+
-+static bool add_all_planes_for_stream(
-+		const struct dc *dc,
-+		struct dc_stream_state *stream,
-+		const struct dc_validation_set set[],
-+		int set_count,
-+		struct dc_state *context)
-+{
-+	int i, j;
-+
-+	for (i = 0; i < set_count; i++)
-+		if (set[i].stream == stream)
-+			break;
-+
-+	if (i == set_count) {
-+		dm_error("Stream %p not found in set!\n", stream);
-+		return false;
-+	}
-+
-+	for (j = 0; j < set[i].plane_count; j++)
-+		if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
-+			return false;
-+
-+	return true;
-+}
-+
-+bool dc_add_all_planes_for_stream(
-+		const struct dc *dc,
-+		struct dc_stream_state *stream,
-+		struct dc_plane_state * const *plane_states,
-+		int plane_count,
-+		struct dc_state *context)
-+{
-+	struct dc_validation_set set;
-+	int i;
-+
-+	set.stream = stream;
-+	set.plane_count = plane_count;
-+
-+	for (i = 0; i < plane_count; i++)
-+		set.plane_states[i] = plane_states[i];
-+
-+	return add_all_planes_for_stream(dc, stream, &set, 1, context);
-+}
-+
-+
-+
-+static bool is_timing_changed(struct dc_stream_state *cur_stream,
-+		struct dc_stream_state *new_stream)
-+{
-+	if (cur_stream == NULL)
-+		return true;
-+
-+	/* If sink pointer changed, it means this is a hotplug, we should do
-+	 * full hw setting.
-+	 */
-+	if (cur_stream->sink != new_stream->sink)
-+		return true;
-+
-+	/* If output color space is changed, need to reprogram info frames */
-+	if (cur_stream->output_color_space != new_stream->output_color_space)
-+		return true;
-+
-+	return memcmp(
-+		&cur_stream->timing,
-+		&new_stream->timing,
-+		sizeof(struct dc_crtc_timing)) != 0;
-+}
-+
-+static bool are_stream_backends_same(
-+	struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
-+{
-+	if (stream_a == stream_b)
-+		return true;
-+
-+	if (stream_a == NULL || stream_b == NULL)
-+		return false;
-+
-+	if (is_timing_changed(stream_a, stream_b))
-+		return false;
-+
-+	return true;
-+}
-+
-+bool dc_is_stream_unchanged(
-+	struct dc_stream_state *old_stream, struct dc_stream_state *stream)
-+{
-+
-+	if (!are_stream_backends_same(old_stream, stream))
-+		return false;
-+
-+	return true;
-+}
-+
-+bool dc_is_stream_scaling_unchanged(
-+	struct dc_stream_state *old_stream, struct dc_stream_state *stream)
-+{
-+	if (old_stream == stream)
-+		return true;
-+
-+	if (old_stream == NULL || stream == NULL)
-+		return false;
-+
-+	if (memcmp(&old_stream->src,
-+			&stream->src,
-+			sizeof(struct rect)) != 0)
-+		return false;
-+
-+	if (memcmp(&old_stream->dst,
-+			&stream->dst,
-+			sizeof(struct rect)) != 0)
-+		return false;
-+
-+	return true;
-+}
-+
-+/* Maximum TMDS single link pixel clock 165MHz */
-+#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000
-+
-+static void update_stream_engine_usage(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool,
-+		struct stream_encoder *stream_enc,
-+		bool acquired)
-+{
-+	int i;
-+
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		if (pool->stream_enc[i] == stream_enc)
-+			res_ctx->is_stream_enc_acquired[i] = acquired;
-+	}
-+}
-+
-+/* TODO: release audio object */
-+void update_audio_usage(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool,
-+		struct audio *audio,
-+		bool acquired)
-+{
-+	int i;
-+	for (i = 0; i < pool->audio_count; i++) {
-+		if (pool->audios[i] == audio)
-+			res_ctx->is_audio_acquired[i] = acquired;
-+	}
-+}
-+
-+static int acquire_first_free_pipe(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool,
-+		struct dc_stream_state *stream)
-+{
-+	int i;
-+
-+	for (i = 0; i < pool->pipe_count; i++) {
-+		if (!res_ctx->pipe_ctx[i].stream) {
-+			struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
-+
-+			pipe_ctx->stream_res.tg = pool->timing_generators[i];
-+			pipe_ctx->plane_res.mi = pool->mis[i];
-+			pipe_ctx->plane_res.hubp = pool->hubps[i];
-+			pipe_ctx->plane_res.ipp = pool->ipps[i];
-+			pipe_ctx->plane_res.xfm = pool->transforms[i];
-+			pipe_ctx->plane_res.dpp = pool->dpps[i];
-+			pipe_ctx->stream_res.opp = pool->opps[i];
-+			pipe_ctx->pipe_idx = i;
-+
-+
-+			pipe_ctx->stream = stream;
-+			return i;
-+		}
-+	}
-+	return -1;
-+}
-+
-+static struct stream_encoder *find_first_free_match_stream_enc_for_link(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool,
-+		struct dc_stream_state *stream)
-+{
-+	int i;
-+	int j = -1;
-+	struct dc_link *link = stream->sink->link;
-+
-+	for (i = 0; i < pool->stream_enc_count; i++) {
-+		if (!res_ctx->is_stream_enc_acquired[i] &&
-+				pool->stream_enc[i]) {
-+			/* Store first available for MST second display
-+			 * in daisy chain use case */
-+			j = i;
-+			if (pool->stream_enc[i]->id ==
-+					link->link_enc->preferred_engine)
-+				return pool->stream_enc[i];
-+		}
-+	}
-+
-+	/*
-+	 * below can happen in cases when stream encoder is acquired:
-+	 * 1) for second MST display in chain, so preferred engine already
-+	 * acquired;
-+	 * 2) for another link, which preferred engine already acquired by any
-+	 * MST configuration.
-+	 *
-+	 * If signal is of DP type and preferred engine not found, return last available
-+	 *
-+	 * TODO - This is just a patch up and a generic solution is
-+	 * required for non DP connectors.
-+	 */
-+
-+	if (j >= 0 && dc_is_dp_signal(stream->signal))
-+		return pool->stream_enc[j];
-+
-+	return NULL;
-+}
-+
-+static struct audio *find_first_free_audio(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool)
-+{
-+	int i;
-+	for (i = 0; i < pool->audio_count; i++) {
-+		if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
-+			return pool->audios[i];
-+		}
-+	}
-+	/*not found the matching one, first come first serve*/
-+	for (i = 0; i < pool->audio_count; i++) {
-+		if (res_ctx->is_audio_acquired[i] == false) {
-+			return pool->audios[i];
-+		}
-+	}
-+	return 0;
-+}
-+
-+bool resource_is_stream_unchanged(
-+	struct dc_state *old_context, struct dc_stream_state *stream)
-+{
-+	int i;
-+
-+	for (i = 0; i < old_context->stream_count; i++) {
-+		struct dc_stream_state *old_stream = old_context->streams[i];
-+
-+		if (are_stream_backends_same(old_stream, stream))
-+				return true;
-+	}
-+
-+	return false;
-+}
-+
-+enum dc_status dc_add_stream_to_ctx(
-+		struct dc *dc,
-+		struct dc_state *new_ctx,
-+		struct dc_stream_state *stream)
-+{
-+	struct dc_context *dc_ctx = dc->ctx;
-+	enum dc_status res;
-+
-+	if (new_ctx->stream_count >= dc->res_pool->pipe_count) {
-+		DC_ERROR("Max streams reached, can add stream %p !\n", stream);
-+		return DC_ERROR_UNEXPECTED;
-+	}
-+
-+	new_ctx->streams[new_ctx->stream_count] = stream;
-+	dc_stream_retain(stream);
-+	new_ctx->stream_count++;
-+
-+	res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
-+	if (res != DC_OK)
-+		DC_ERROR("Adding stream %p to context failed with err %d!\n", stream, res);
-+
-+	return res;
-+}
-+
-+enum dc_status dc_remove_stream_from_ctx(
-+			struct dc *dc,
-+			struct dc_state *new_ctx,
-+			struct dc_stream_state *stream)
-+{
-+	int i;
-+	struct dc_context *dc_ctx = dc->ctx;
-+	struct pipe_ctx *del_pipe = NULL;
-+
-+	/* Release primary pipe */
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
-+				!new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
-+			del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
-+
-+			ASSERT(del_pipe->stream_res.stream_enc);
-+			update_stream_engine_usage(
-+					&new_ctx->res_ctx,
-+						dc->res_pool,
-+					del_pipe->stream_res.stream_enc,
-+					false);
-+
-+			if (del_pipe->stream_res.audio)
-+				update_audio_usage(
-+					&new_ctx->res_ctx,
-+					dc->res_pool,
-+					del_pipe->stream_res.audio,
-+					false);
-+
-+			resource_unreference_clock_source(&new_ctx->res_ctx,
-+							  dc->res_pool,
-+							  del_pipe->clock_source);
-+
-+			memset(del_pipe, 0, sizeof(*del_pipe));
-+
-+			break;
-+		}
-+	}
-+
-+	if (!del_pipe) {
-+		DC_ERROR("Pipe not found for stream %p !\n", stream);
-+		return DC_ERROR_UNEXPECTED;
-+	}
-+
-+	for (i = 0; i < new_ctx->stream_count; i++)
-+		if (new_ctx->streams[i] == stream)
-+			break;
-+
-+	if (new_ctx->streams[i] != stream) {
-+		DC_ERROR("Context doesn't have stream %p !\n", stream);
-+		return DC_ERROR_UNEXPECTED;
-+	}
-+
-+	dc_stream_release(new_ctx->streams[i]);
-+	new_ctx->stream_count--;
-+
-+	/* Trim back arrays */
-+	for (; i < new_ctx->stream_count; i++) {
-+		new_ctx->streams[i] = new_ctx->streams[i + 1];
-+		new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
-+	}
-+
-+	new_ctx->streams[new_ctx->stream_count] = NULL;
-+	memset(
-+			&new_ctx->stream_status[new_ctx->stream_count],
-+			0,
-+			sizeof(new_ctx->stream_status[0]));
-+
-+	return DC_OK;
-+}
-+
-+static void copy_pipe_ctx(
-+	const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx)
-+{
-+	struct dc_plane_state *plane_state = to_pipe_ctx->plane_state;
-+	struct dc_stream_state *stream = to_pipe_ctx->stream;
-+
-+	*to_pipe_ctx = *from_pipe_ctx;
-+	to_pipe_ctx->stream = stream;
-+	if (plane_state != NULL)
-+		to_pipe_ctx->plane_state = plane_state;
-+}
-+
-+static struct dc_stream_state *find_pll_sharable_stream(
-+		struct dc_stream_state *stream_needs_pll,
-+		struct dc_state *context)
-+{
-+	int i;
-+
-+	for (i = 0; i < context->stream_count; i++) {
-+		struct dc_stream_state *stream_has_pll = context->streams[i];
-+
-+		/* We are looking for non dp, non virtual stream */
-+		if (resource_are_streams_timing_synchronizable(
-+			stream_needs_pll, stream_has_pll)
-+			&& !dc_is_dp_signal(stream_has_pll->signal)
-+			&& stream_has_pll->sink->link->connector_signal
-+			!= SIGNAL_TYPE_VIRTUAL)
-+			return stream_has_pll;
-+
-+	}
-+
-+	return NULL;
-+}
-+
-+static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
-+{
-+	uint32_t pix_clk = timing->pix_clk_khz;
-+	uint32_t normalized_pix_clk = pix_clk;
-+
-+	if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
-+		pix_clk /= 2;
-+	if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
-+		switch (timing->display_color_depth) {
-+		case COLOR_DEPTH_888:
-+			normalized_pix_clk = pix_clk;
-+			break;
-+		case COLOR_DEPTH_101010:
-+			normalized_pix_clk = (pix_clk * 30) / 24;
-+			break;
-+		case COLOR_DEPTH_121212:
-+			normalized_pix_clk = (pix_clk * 36) / 24;
-+		break;
-+		case COLOR_DEPTH_161616:
-+			normalized_pix_clk = (pix_clk * 48) / 24;
-+		break;
-+		default:
-+			ASSERT(0);
-+		break;
-+		}
-+	}
-+	return normalized_pix_clk;
-+}
-+
-+static void calculate_phy_pix_clks(struct dc_stream_state *stream)
-+{
-+	/* update actual pixel clock on all streams */
-+	if (dc_is_hdmi_signal(stream->signal))
-+		stream->phy_pix_clk = get_norm_pix_clk(
-+			&stream->timing);
-+	else
-+		stream->phy_pix_clk =
-+			stream->timing.pix_clk_khz;
-+}
-+
-+enum dc_status resource_map_pool_resources(
-+		const struct dc  *dc,
-+		struct dc_state *context,
-+		struct dc_stream_state *stream)
-+{
-+	const struct resource_pool *pool = dc->res_pool;
-+	int i;
-+	struct dc_context *dc_ctx = dc->ctx;
-+	struct pipe_ctx *pipe_ctx = NULL;
-+	int pipe_idx = -1;
-+
-+	/* TODO Check if this is needed */
-+	/*if (!resource_is_stream_unchanged(old_context, stream)) {
-+			if (stream != NULL && old_context->streams[i] != NULL) {
-+				stream->bit_depth_params =
-+						old_context->streams[i]->bit_depth_params;
-+				stream->clamping = old_context->streams[i]->clamping;
-+				continue;
-+			}
-+		}
-+	*/
-+
-+	/* acquire new resources */
-+	pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
-+
-+#ifdef CONFIG_DRM_AMD_DC_DCN1_0
-+	if (pipe_idx < 0)
-+		pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
-+#endif
-+
-+	if (pipe_idx < 0)
-+		return DC_NO_CONTROLLER_RESOURCE;
-+
-+	pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
-+
-+	pipe_ctx->stream_res.stream_enc =
-+		find_first_free_match_stream_enc_for_link(
-+			&context->res_ctx, pool, stream);
-+
-+	if (!pipe_ctx->stream_res.stream_enc)
-+		return DC_NO_STREAM_ENG_RESOURCE;
-+
-+	update_stream_engine_usage(
-+		&context->res_ctx, pool,
-+		pipe_ctx->stream_res.stream_enc,
-+		true);
-+
-+	/* TODO: Add check if ASIC support and EDID audio */
-+	if (!stream->sink->converter_disable_audio &&
-+	    dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
-+	    stream->audio_info.mode_count) {
-+		pipe_ctx->stream_res.audio = find_first_free_audio(
-+		&context->res_ctx, pool);
-+
-+		/*
-+		 * Audio assigned in order first come first get.
-+		 * There are asics which has number of audio
-+		 * resources less then number of pipes
-+		 */
-+		if (pipe_ctx->stream_res.audio)
-+			update_audio_usage(&context->res_ctx, pool,
-+					   pipe_ctx->stream_res.audio, true);
-+	}
-+
-+	for (i = 0; i < context->stream_count; i++)
-+		if (context->streams[i] == stream) {
-+			context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
-+			context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->id;
-+			return DC_OK;
-+		}
-+
-+	DC_ERROR("Stream %p not found in new ctx!\n", stream);
-+	return DC_ERROR_UNEXPECTED;
-+}
-+
-+/* first stream in the context is used to populate the rest */
-+void validate_guaranteed_copy_streams(
-+		struct dc_state *context,
-+		int max_streams)
-+{
-+	int i;
-+
-+	for (i = 1; i < max_streams; i++) {
-+		context->streams[i] = context->streams[0];
-+
-+		copy_pipe_ctx(&context->res_ctx.pipe_ctx[0],
-+			      &context->res_ctx.pipe_ctx[i]);
-+		context->res_ctx.pipe_ctx[i].stream =
-+				context->res_ctx.pipe_ctx[0].stream;
-+
-+		dc_stream_retain(context->streams[i]);
-+		context->stream_count++;
-+	}
-+}
-+
-+void dc_resource_state_copy_construct_current(
-+		const struct dc *dc,
-+		struct dc_state *dst_ctx)
-+{
-+	dc_resource_state_copy_construct(dc->current_state, dst_ctx);
-+}
-+
-+
-+void dc_resource_state_construct(
-+		const struct dc *dc,
-+		struct dc_state *dst_ctx)
-+{
-+	dst_ctx->dis_clk = dc->res_pool->display_clock;
-+}
-+
-+enum dc_status dc_validate_global_state(
-+		struct dc *dc,
-+		struct dc_state *new_ctx)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+	int i, j;
-+
-+	if (dc->res_pool->funcs->validate_global) {
-+			result = dc->res_pool->funcs->validate_global(dc, new_ctx);
-+			if (result != DC_OK)
-+				return result;
-+	}
-+
-+	for (i = 0; new_ctx && i < new_ctx->stream_count; i++) {
-+		struct dc_stream_state *stream = new_ctx->streams[i];
-+
-+		for (j = 0; j < dc->res_pool->pipe_count; j++) {
-+			struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
-+
-+			if (pipe_ctx->stream != stream)
-+				continue;
-+
-+			/* Switch to dp clock source only if there is
-+			 * no non dp stream that shares the same timing
-+			 * with the dp stream.
-+			 */
-+			if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
-+				!find_pll_sharable_stream(stream, new_ctx)) {
-+
-+				resource_unreference_clock_source(
-+						&new_ctx->res_ctx,
-+						dc->res_pool,
-+						pipe_ctx->clock_source);
-+
-+				pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
-+				resource_reference_clock_source(
-+						&new_ctx->res_ctx,
-+						dc->res_pool,
-+						 pipe_ctx->clock_source);
-+			}
-+		}
-+	}
-+
-+	result = resource_build_scaling_params_for_context(dc, new_ctx);
-+
-+	if (result == DC_OK)
-+		if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx))
-+			result = DC_FAIL_BANDWIDTH_VALIDATE;
-+
-+	return result;
-+}
-+
-+static void patch_gamut_packet_checksum(
-+		struct encoder_info_packet *gamut_packet)
-+{
-+	/* For gamut we recalc checksum */
-+	if (gamut_packet->valid) {
-+		uint8_t chk_sum = 0;
-+		uint8_t *ptr;
-+		uint8_t i;
-+
-+		/*start of the Gamut data. */
-+		ptr = &gamut_packet->sb[3];
-+
-+		for (i = 0; i <= gamut_packet->sb[1]; i++)
-+			chk_sum += ptr[i];
-+
-+		gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
-+	}
-+}
-+
-+static void set_avi_info_frame(
-+		struct encoder_info_packet *info_packet,
-+		struct pipe_ctx *pipe_ctx)
-+{
-+	struct dc_stream_state *stream = pipe_ctx->stream;
-+	enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
-+	struct info_frame info_frame = { {0} };
-+	uint32_t pixel_encoding = 0;
-+	enum scanning_type scan_type = SCANNING_TYPE_NODATA;
-+	enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
-+	bool itc = false;
-+	uint8_t itc_value = 0;
-+	uint8_t cn0_cn1 = 0;
-+	unsigned int cn0_cn1_value = 0;
-+	uint8_t *check_sum = NULL;
-+	uint8_t byte_index = 0;
-+	union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi;
-+	union display_content_support support = {0};
-+	unsigned int vic = pipe_ctx->stream->timing.vic;
-+	enum dc_timing_3d_format format;
-+
-+	color_space = pipe_ctx->stream->output_color_space;
-+	if (color_space == COLOR_SPACE_UNKNOWN)
-+		color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
-+			COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
-+
-+	/* Initialize header */
-+	hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
-+	/* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
-+	* not be used in HDMI 2.0 (Section 10.1) */
-+	hdmi_info->bits.header.version = 2;
-+	hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
-+
-+	/*
-+	 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
-+	 * according to HDMI 2.0 spec (Section 10.1)
-+	 */
-+
-+	switch (stream->timing.pixel_encoding) {
-+	case PIXEL_ENCODING_YCBCR422:
-+		pixel_encoding = 1;
-+		break;
-+
-+	case PIXEL_ENCODING_YCBCR444:
-+		pixel_encoding = 2;
-+		break;
-+	case PIXEL_ENCODING_YCBCR420:
-+		pixel_encoding = 3;
-+		break;
-+
-+	case PIXEL_ENCODING_RGB:
-+	default:
-+		pixel_encoding = 0;
-+	}
-+
-+	/* Y0_Y1_Y2 : The pixel encoding */
-+	/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
-+	hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding;
-+
-+	/* A0 = 1 Active Format Information valid */
-+	hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID;
-+
-+	/* B0, B1 = 3; Bar info data is valid */
-+	hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID;
-+
-+	hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
-+
-+	/* S0, S1 : Underscan / Overscan */
-+	/* TODO: un-hardcode scan type */
-+	scan_type = SCANNING_TYPE_UNDERSCAN;
-+	hdmi_info->bits.S0_S1 = scan_type;
-+
-+	/* C0, C1 : Colorimetry */
-+	if (color_space == COLOR_SPACE_YCBCR709 ||
-+			color_space == COLOR_SPACE_YCBCR709_LIMITED)
-+		hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
-+	else if (color_space == COLOR_SPACE_YCBCR601 ||
-+			color_space == COLOR_SPACE_YCBCR601_LIMITED)
-+		hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601;
-+	else {
-+		hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA;
-+	}
-+	if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
-+			color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
-+			color_space == COLOR_SPACE_2020_YCBCR) {
-+		hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
-+		hdmi_info->bits.C0_C1   = COLORIMETRY_EXTENDED;
-+	} else if (color_space == COLOR_SPACE_ADOBERGB) {
-+		hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
-+		hdmi_info->bits.C0_C1   = COLORIMETRY_EXTENDED;
-+	}
-+
-+	/* TODO: un-hardcode aspect ratio */
-+	aspect = stream->timing.aspect_ratio;
-+
-+	switch (aspect) {
-+	case ASPECT_RATIO_4_3:
-+	case ASPECT_RATIO_16_9:
-+		hdmi_info->bits.M0_M1 = aspect;
-+		break;
-+
-+	case ASPECT_RATIO_NO_DATA:
-+	case ASPECT_RATIO_64_27:
-+	case ASPECT_RATIO_256_135:
-+	default:
-+		hdmi_info->bits.M0_M1 = 0;
-+	}
-+
-+	/* Active Format Aspect ratio - same as Picture Aspect Ratio. */
-+	hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
-+
-+	/* TODO: un-hardcode cn0_cn1 and itc */
-+
-+	cn0_cn1 = 0;
-+	cn0_cn1_value = 0;
-+
-+	itc = true;
-+	itc_value = 1;
-+
-+	support = stream->sink->edid_caps.content_support;
-+
-+	if (itc) {
-+		if (!support.bits.valid_content_type) {
-+			cn0_cn1_value = 0;
-+		} else {
-+			if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
-+				if (support.bits.graphics_content == 1) {
-+					cn0_cn1_value = 0;
-+				}
-+			} else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
-+				if (support.bits.photo_content == 1) {
-+					cn0_cn1_value = 1;
-+				} else {
-+					cn0_cn1_value = 0;
-+					itc_value = 0;
-+				}
-+			} else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
-+				if (support.bits.cinema_content == 1) {
-+					cn0_cn1_value = 2;
-+				} else {
-+					cn0_cn1_value = 0;
-+					itc_value = 0;
-+				}
-+			} else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
-+				if (support.bits.game_content == 1) {
-+					cn0_cn1_value = 3;
-+				} else {
-+					cn0_cn1_value = 0;
-+					itc_value = 0;
-+				}
-+			}
-+		}
-+		hdmi_info->bits.CN0_CN1 = cn0_cn1_value;
-+		hdmi_info->bits.ITC = itc_value;
-+	}
-+
-+	/* TODO : We should handle YCC quantization */
-+	/* but we do not have matrix calculation */
-+	if (stream->sink->edid_caps.qs_bit == 1 &&
-+			stream->sink->edid_caps.qy_bit == 1) {
-+		if (color_space == COLOR_SPACE_SRGB ||
-+			color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
-+			hdmi_info->bits.Q0_Q1   = RGB_QUANTIZATION_FULL_RANGE;
-+			hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
-+		} else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
-+					color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
-+			hdmi_info->bits.Q0_Q1   = RGB_QUANTIZATION_LIMITED_RANGE;
-+			hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
-+		} else {
-+			hdmi_info->bits.Q0_Q1   = RGB_QUANTIZATION_DEFAULT_RANGE;
-+			hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
-+		}
-+	} else {
-+		hdmi_info->bits.Q0_Q1   = RGB_QUANTIZATION_DEFAULT_RANGE;
-+		hdmi_info->bits.YQ0_YQ1   = YYC_QUANTIZATION_LIMITED_RANGE;
-+	}
-+
-+	///VIC
-+	format = stream->timing.timing_3d_format;
-+	/*todo, add 3DStereo support*/
-+	if (format != TIMING_3D_FORMAT_NONE) {
-+		// Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
-+		switch (pipe_ctx->stream->timing.hdmi_vic) {
-+		case 1:
-+			vic = 95;
-+			break;
-+		case 2:
-+			vic = 94;
-+			break;
-+		case 3:
-+			vic = 93;
-+			break;
-+		case 4:
-+			vic = 98;
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+	hdmi_info->bits.VIC0_VIC7 = vic;
-+
-+	/* pixel repetition
-+	 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
-+	 * repetition start from 1 */
-+	hdmi_info->bits.PR0_PR3 = 0;
-+
-+	/* Bar Info
-+	 * barTop:    Line Number of End of Top Bar.
-+	 * barBottom: Line Number of Start of Bottom Bar.
-+	 * barLeft:   Pixel Number of End of Left Bar.
-+	 * barRight:  Pixel Number of Start of Right Bar. */
-+	hdmi_info->bits.bar_top = stream->timing.v_border_top;
-+	hdmi_info->bits.bar_bottom = (stream->timing.v_total
-+			- stream->timing.v_border_bottom + 1);
-+	hdmi_info->bits.bar_left  = stream->timing.h_border_left;
-+	hdmi_info->bits.bar_right = (stream->timing.h_total
-+			- stream->timing.h_border_right + 1);
-+
-+	/* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
-+	check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
-+
-+	*check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
-+
-+	for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
-+		*check_sum += hdmi_info->packet_raw_data.sb[byte_index];
-+
-+	/* one byte complement */
-+	*check_sum = (uint8_t) (0x100 - *check_sum);
-+
-+	/* Store in hw_path_mode */
-+	info_packet->hb0 = hdmi_info->packet_raw_data.hb0;
-+	info_packet->hb1 = hdmi_info->packet_raw_data.hb1;
-+	info_packet->hb2 = hdmi_info->packet_raw_data.hb2;
-+
-+	for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet.
-+				info_packet_hdmi.packet_raw_data.sb); byte_index++)
-+		info_packet->sb[byte_index] = info_frame.avi_info_packet.
-+				info_packet_hdmi.packet_raw_data.sb[byte_index];
-+
-+	info_packet->valid = true;
-+}
-+
-+static void set_vendor_info_packet(
-+		struct encoder_info_packet *info_packet,
-+		struct dc_stream_state *stream)
-+{
-+	uint32_t length = 0;
-+	bool hdmi_vic_mode = false;
-+	uint8_t checksum = 0;
-+	uint32_t i = 0;
-+	enum dc_timing_3d_format format;
-+	// Can be different depending on packet content /*todo*/
-+	// unsigned int length = pPathMode->dolbyVision ? 24 : 5;
-+
-+	info_packet->valid = false;
-+
-+	format = stream->timing.timing_3d_format;
-+	if (stream->view_format == VIEW_3D_FORMAT_NONE)
-+		format = TIMING_3D_FORMAT_NONE;
-+
-+	/* Can be different depending on packet content */
-+	length = 5;
-+
-+	if (stream->timing.hdmi_vic != 0
-+			&& stream->timing.h_total >= 3840
-+			&& stream->timing.v_total >= 2160)
-+		hdmi_vic_mode = true;
-+
-+	/* According to HDMI 1.4a CTS, VSIF should be sent
-+	 * for both 3D stereo and HDMI VIC modes.
-+	 * For all other modes, there is no VSIF sent.  */
-+
-+	if (format == TIMING_3D_FORMAT_NONE && !hdmi_vic_mode)
-+		return;
-+
-+	/* 24bit IEEE Registration identifier (0x000c03). LSB first. */
-+	info_packet->sb[1] = 0x03;
-+	info_packet->sb[2] = 0x0C;
-+	info_packet->sb[3] = 0x00;
-+
-+	/*PB4: 5 lower bytes = 0 (reserved). 3 higher bits = HDMI_Video_Format.
-+	 * The value for HDMI_Video_Format are:
-+	 * 0x0 (0b000) - No additional HDMI video format is presented in this
-+	 * packet
-+	 * 0x1 (0b001) - Extended resolution format present. 1 byte of HDMI_VIC
-+	 * parameter follows
-+	 * 0x2 (0b010) - 3D format indication present. 3D_Structure and
-+	 * potentially 3D_Ext_Data follows
-+	 * 0x3..0x7 (0b011..0b111) - reserved for future use */
-+	if (format != TIMING_3D_FORMAT_NONE)
-+		info_packet->sb[4] = (2 << 5);
-+	else if (hdmi_vic_mode)
-+		info_packet->sb[4] = (1 << 5);
-+
-+	/* PB5: If PB4 claims 3D timing (HDMI_Video_Format = 0x2):
-+	 * 4 lower bites = 0 (reserved). 4 higher bits = 3D_Structure.
-+	 * The value for 3D_Structure are:
-+	 * 0x0 - Frame Packing
-+	 * 0x1 - Field Alternative
-+	 * 0x2 - Line Alternative
-+	 * 0x3 - Side-by-Side (full)
-+	 * 0x4 - L + depth
-+	 * 0x5 - L + depth + graphics + graphics-depth
-+	 * 0x6 - Top-and-Bottom
-+	 * 0x7 - Reserved for future use
-+	 * 0x8 - Side-by-Side (Half)
-+	 * 0x9..0xE - Reserved for future use
-+	 * 0xF - Not used */
-+	switch (format) {
-+	case TIMING_3D_FORMAT_HW_FRAME_PACKING:
-+	case TIMING_3D_FORMAT_SW_FRAME_PACKING:
-+		info_packet->sb[5] = (0x0 << 4);
-+		break;
-+
-+	case TIMING_3D_FORMAT_SIDE_BY_SIDE:
-+	case TIMING_3D_FORMAT_SBS_SW_PACKED:
-+		info_packet->sb[5] = (0x8 << 4);
-+		length = 6;
-+		break;
-+
-+	case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
-+	case TIMING_3D_FORMAT_TB_SW_PACKED:
-+		info_packet->sb[5] = (0x6 << 4);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	/*PB5: If PB4 is set to 0x1 (extended resolution format)
-+	 * fill PB5 with the correct HDMI VIC code */
-+	if (hdmi_vic_mode)
-+		info_packet->sb[5] = stream->timing.hdmi_vic;
-+
-+	/* Header */
-+	info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */
-+	info_packet->hb1 = 0x01; /* Version */
-+
-+	/* 4 lower bits = Length, 4 higher bits = 0 (reserved) */
-+	info_packet->hb2 = (uint8_t) (length);
-+
-+	/* Calculate checksum */
-+	checksum = 0;
-+	checksum += info_packet->hb0;
-+	checksum += info_packet->hb1;
-+	checksum += info_packet->hb2;
-+
-+	for (i = 1; i <= length; i++)
-+		checksum += info_packet->sb[i];
-+
-+	info_packet->sb[0] = (uint8_t) (0x100 - checksum);
-+
-+	info_packet->valid = true;
-+}
-+
-+static void set_spd_info_packet(
-+		struct encoder_info_packet *info_packet,
-+		struct dc_stream_state *stream)
-+{
-+	/* SPD info packet for FreeSync */
-+
-+	unsigned char checksum = 0;
-+	unsigned int idx, payload_size = 0;
-+
-+	/* Check if Freesync is supported. Return if false. If true,
-+	 * set the corresponding bit in the info packet
-+	 */
-+	if (stream->freesync_ctx.supported == false)
-+		return;
-+
-+	if (dc_is_hdmi_signal(stream->signal)) {
-+
-+		/* HEADER */
-+
-+		/* HB0  = Packet Type = 0x83 (Source Product
-+		 *	  Descriptor InfoFrame)
-+		 */
-+		info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
-+
-+		/* HB1  = Version = 0x01 */
-+		info_packet->hb1 = 0x01;
-+
-+		/* HB2  = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
-+		info_packet->hb2 = 0x08;
-+
-+		payload_size = 0x08;
-+
-+	} else if (dc_is_dp_signal(stream->signal)) {
-+
-+		/* HEADER */
-+
-+		/* HB0  = Secondary-data Packet ID = 0 - Only non-zero
-+		 *	  when used to associate audio related info packets
-+		 */
-+		info_packet->hb0 = 0x00;
-+
-+		/* HB1  = Packet Type = 0x83 (Source Product
-+		 *	  Descriptor InfoFrame)
-+		 */
-+		info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
-+
-+		/* HB2  = [Bits 7:0 = Least significant eight bits -
-+		 *	  For INFOFRAME, the value must be 1Bh]
-+		 */
-+		info_packet->hb2 = 0x1B;
-+
-+		/* HB3  = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
-+		 *	  [Bits 1:0 = Most significant two bits = 0x00]
-+		 */
-+		info_packet->hb3 = 0x04;
-+
-+		payload_size = 0x1B;
-+	}
-+
-+	/* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
-+	info_packet->sb[1] = 0x1A;
-+
-+	/* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
-+	info_packet->sb[2] = 0x00;
-+
-+	/* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
-+	info_packet->sb[3] = 0x00;
-+
-+	/* PB4 = Reserved */
-+	info_packet->sb[4] = 0x00;
-+
-+	/* PB5 = Reserved */
-+	info_packet->sb[5] = 0x00;
-+
-+	/* PB6 = [Bits 7:3 = Reserved] */
-+	info_packet->sb[6] = 0x00;
-+
-+	if (stream->freesync_ctx.supported == true)
-+		/* PB6 = [Bit 0 = FreeSync Supported] */
-+		info_packet->sb[6] |= 0x01;
-+
-+	if (stream->freesync_ctx.enabled == true)
-+		/* PB6 = [Bit 1 = FreeSync Enabled] */
-+		info_packet->sb[6] |= 0x02;
-+
-+	if (stream->freesync_ctx.active == true)
-+		/* PB6 = [Bit 2 = FreeSync Active] */
-+		info_packet->sb[6] |= 0x04;
-+
-+	/* PB7 = FreeSync Minimum refresh rate (Hz) */
-+	info_packet->sb[7] = (unsigned char) (stream->freesync_ctx.
-+			min_refresh_in_micro_hz / 1000000);
-+
-+	/* PB8 = FreeSync Maximum refresh rate (Hz)
-+	 *
-+	 * Note: We do not use the maximum capable refresh rate
-+	 * of the panel, because we should never go above the field
-+	 * rate of the mode timing set.
-+	 */
-+	info_packet->sb[8] = (unsigned char) (stream->freesync_ctx.
-+			nominal_refresh_in_micro_hz / 1000000);
-+
-+	/* PB9 - PB27  = Reserved */
-+	for (idx = 9; idx <= 27; idx++)
-+		info_packet->sb[idx] = 0x00;
-+
-+	/* Calculate checksum */
-+	checksum += info_packet->hb0;
-+	checksum += info_packet->hb1;
-+	checksum += info_packet->hb2;
-+	checksum += info_packet->hb3;
-+
-+	for (idx = 1; idx <= payload_size; idx++)
-+		checksum += info_packet->sb[idx];
-+
-+	/* PB0 = Checksum (one byte complement) */
-+	info_packet->sb[0] = (unsigned char) (0x100 - checksum);
-+
-+	info_packet->valid = true;
-+}
-+
-+static void set_hdr_static_info_packet(
-+		struct encoder_info_packet *info_packet,
-+		struct dc_stream_state *stream)
-+{
-+	uint16_t i = 0;
-+	enum signal_type signal = stream->signal;
-+	uint32_t data;
-+
-+	if (!stream->hdr_static_metadata.hdr_supported)
-+		return;
-+
-+	if (dc_is_hdmi_signal(signal)) {
-+		info_packet->valid = true;
-+
-+		info_packet->hb0 = 0x87;
-+		info_packet->hb1 = 0x01;
-+		info_packet->hb2 = 0x1A;
-+		i = 1;
-+	} else if (dc_is_dp_signal(signal)) {
-+		info_packet->valid = true;
-+
-+		info_packet->hb0 = 0x00;
-+		info_packet->hb1 = 0x87;
-+		info_packet->hb2 = 0x1D;
-+		info_packet->hb3 = (0x13 << 2);
-+		i = 2;
-+	}
-+
-+	data = stream->hdr_static_metadata.is_hdr;
-+	info_packet->sb[i++] = data ? 0x02 : 0x00;
-+	info_packet->sb[i++] = 0x00;
-+
-+	data = stream->hdr_static_metadata.chromaticity_green_x / 2;
-+	info_packet->sb[i++] = data & 0xFF;
-+	info_packet->sb[i++] = (data & 0xFF00) >> 8;
-+
-+	data = stream->hdr_static_metadata.chromaticity_green_y / 2;
-+	info_packet->sb[i++] = data & 0xFF;
-+	info_packet->sb[i++] = (data & 0xFF00) >> 8;
-+
-+	data = stream->hdr_static_metadata.chromaticity_blue_x / 2;
-+	info_packet->sb[i++] = data & 0xFF;
-+	info_packet->sb[i++] = (data & 0xFF00) >> 8;
-+
-+	data = stream->hdr_static_metadata.chromaticity_blue_y / 2;
-+	info_packet->sb[i++] = data & 0xFF;
-+	info_packet->sb[i++] = (data & 0xFF00) >> 8;
-+
-+	data = stream->hdr_static_metadata.chromaticity_red_x / 2;
-+	info_packet->sb[i++] = data & 0xFF;
-+	info_packet->sb[i++] = (data & 0xFF00) >> 8;
-+
-+	data = stream->hdr_static_metadata.chromaticity_red_y / 2;
-+	info_packet->sb[i++] = data & 0xFF;
-+	info_packet->sb[i++] = (data & 0xFF00) >> 8;
-+
-+	data = stream->hdr_static_metadata.chromaticity_white_point_x / 2;
-+	info_packet->sb[i++] = data & 0xFF;
-+	info_packet->sb[i++] = (data & 0xFF00) >> 8;
-+
-+	data = stream->hdr_static_metadata.chromaticity_white_point_y / 2;
-+	info_packet->sb[i++] = data & 0xFF;
-+	info_packet->sb[i++] = (data & 0xFF00) >> 8;
-+
-+	data = stream->hdr_static_metadata.max_luminance;
-+	info_packet->sb[i++] = data & 0xFF;
-+	info_packet->sb[i++] = (data & 0xFF00) >> 8;
-+
-+	data = stream->hdr_static_metadata.min_luminance;
-+	info_packet->sb[i++] = data & 0xFF;
-+	info_packet->sb[i++] = (data & 0xFF00) >> 8;
-+
-+	data = stream->hdr_static_metadata.maximum_content_light_level;
-+	info_packet->sb[i++] = data & 0xFF;
-+	info_packet->sb[i++] = (data & 0xFF00) >> 8;
-+
-+	data = stream->hdr_static_metadata.maximum_frame_average_light_level;
-+	info_packet->sb[i++] = data & 0xFF;
-+	info_packet->sb[i++] = (data & 0xFF00) >> 8;
-+
-+	if (dc_is_hdmi_signal(signal)) {
-+		uint32_t checksum = 0;
-+
-+		checksum += info_packet->hb0;
-+		checksum += info_packet->hb1;
-+		checksum += info_packet->hb2;
-+
-+		for (i = 1; i <= info_packet->hb2; i++)
-+			checksum += info_packet->sb[i];
-+
-+		info_packet->sb[0] = 0x100 - checksum;
-+	} else if (dc_is_dp_signal(signal)) {
-+		info_packet->sb[0] = 0x01;
-+		info_packet->sb[1] = 0x1A;
-+	}
-+}
-+
-+static void set_vsc_info_packet(
-+		struct encoder_info_packet *info_packet,
-+		struct dc_stream_state *stream)
-+{
-+	unsigned int vscPacketRevision = 0;
-+	unsigned int i;
-+
-+	if (stream->sink->link->psr_enabled) {
-+		vscPacketRevision = 2;
-+	}
-+
-+	/* VSC packet not needed based on the features
-+	 * supported by this DP display
-+	 */
-+	if (vscPacketRevision == 0)
-+		return;
-+
-+	if (vscPacketRevision == 0x2) {
-+		/* Secondary-data Packet ID = 0*/
-+		info_packet->hb0 = 0x00;
-+		/* 07h - Packet Type Value indicating Video
-+		 * Stream Configuration packet
-+		 */
-+		info_packet->hb1 = 0x07;
-+		/* 02h = VSC SDP supporting 3D stereo and PSR
-+		 * (applies to eDP v1.3 or higher).
-+		 */
-+		info_packet->hb2 = 0x02;
-+		/* 08h = VSC packet supporting 3D stereo + PSR
-+		 * (HB2 = 02h).
-+		 */
-+		info_packet->hb3 = 0x08;
-+
-+		for (i = 0; i < 28; i++)
-+			info_packet->sb[i] = 0;
-+
-+		info_packet->valid = true;
-+	}
-+
-+	/*TODO: stereo 3D support and extend pixel encoding colorimetry*/
-+}
-+
-+void dc_resource_state_destruct(struct dc_state *context)
-+{
-+	int i, j;
-+
-+	for (i = 0; i < context->stream_count; i++) {
-+		for (j = 0; j < context->stream_status[i].plane_count; j++)
-+			dc_plane_state_release(
-+				context->stream_status[i].plane_states[j]);
-+
-+		context->stream_status[i].plane_count = 0;
-+		dc_stream_release(context->streams[i]);
-+		context->streams[i] = NULL;
-+	}
-+}
-+
-+/*
-+ * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced
-+ * by the src_ctx
-+ */
-+void dc_resource_state_copy_construct(
-+		const struct dc_state *src_ctx,
-+		struct dc_state *dst_ctx)
-+{
-+	int i, j;
-+	struct kref refcount = dst_ctx->refcount;
-+
-+	*dst_ctx = *src_ctx;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
-+
-+		if (cur_pipe->top_pipe)
-+			cur_pipe->top_pipe =  &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
-+
-+		if (cur_pipe->bottom_pipe)
-+			cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
-+
-+	}
-+
-+	for (i = 0; i < dst_ctx->stream_count; i++) {
-+		dc_stream_retain(dst_ctx->streams[i]);
-+		for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
-+			dc_plane_state_retain(
-+				dst_ctx->stream_status[i].plane_states[j]);
-+	}
-+
-+	/* context refcount should not be overridden */
-+	dst_ctx->refcount = refcount;
-+
-+}
-+
-+struct clock_source *dc_resource_find_first_free_pll(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool)
-+{
-+	int i;
-+
-+	for (i = 0; i < pool->clk_src_count; ++i) {
-+		if (res_ctx->clock_source_ref_count[i] == 0)
-+			return pool->clock_sources[i];
-+	}
-+
-+	return NULL;
-+}
-+
-+void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
-+{
-+	enum signal_type signal = SIGNAL_TYPE_NONE;
-+	struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
-+
-+	/* default all packets to invalid */
-+	info->avi.valid = false;
-+	info->gamut.valid = false;
-+	info->vendor.valid = false;
-+	info->spd.valid = false;
-+	info->hdrsmd.valid = false;
-+	info->vsc.valid = false;
-+
-+	signal = pipe_ctx->stream->signal;
-+
-+	/* HDMi and DP have different info packets*/
-+	if (dc_is_hdmi_signal(signal)) {
-+		set_avi_info_frame(&info->avi, pipe_ctx);
-+
-+		set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
-+
-+		set_spd_info_packet(&info->spd, pipe_ctx->stream);
-+
-+		set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
-+
-+	} else if (dc_is_dp_signal(signal)) {
-+		set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
-+
-+		set_spd_info_packet(&info->spd, pipe_ctx->stream);
-+
-+		set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
-+	}
-+
-+	patch_gamut_packet_checksum(&info->gamut);
-+}
-+
-+enum dc_status resource_map_clock_resources(
-+		const struct dc  *dc,
-+		struct dc_state *context,
-+		struct dc_stream_state *stream)
-+{
-+	/* acquire new resources */
-+	const struct resource_pool *pool = dc->res_pool;
-+	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
-+				&context->res_ctx, stream);
-+
-+	if (!pipe_ctx)
-+		return DC_ERROR_UNEXPECTED;
-+
-+	if (dc_is_dp_signal(pipe_ctx->stream->signal)
-+		|| pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
-+		pipe_ctx->clock_source = pool->dp_clock_source;
-+	else {
-+		pipe_ctx->clock_source = NULL;
-+
-+		if (!dc->config.disable_disp_pll_sharing)
-+			pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
-+				&context->res_ctx,
-+				pipe_ctx);
-+
-+		if (pipe_ctx->clock_source == NULL)
-+			pipe_ctx->clock_source =
-+				dc_resource_find_first_free_pll(
-+					&context->res_ctx,
-+					pool);
-+	}
-+
-+	if (pipe_ctx->clock_source == NULL)
-+		return DC_NO_CLOCK_SOURCE_RESOURCE;
-+
-+	resource_reference_clock_source(
-+		&context->res_ctx, pool,
-+		pipe_ctx->clock_source);
-+
-+	return DC_OK;
-+}
-+
-+/*
-+ * Note: We need to disable output if clock sources change,
-+ * since bios does optimization and doesn't apply if changing
-+ * PHY when not already disabled.
-+ */
-+bool pipe_need_reprogram(
-+		struct pipe_ctx *pipe_ctx_old,
-+		struct pipe_ctx *pipe_ctx)
-+{
-+	if (!pipe_ctx_old->stream)
-+		return false;
-+
-+	if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
-+		return true;
-+
-+	if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
-+		return true;
-+
-+	if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
-+		return true;
-+
-+	if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
-+			&& pipe_ctx_old->stream != pipe_ctx->stream)
-+		return true;
-+
-+	if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
-+		return true;
-+
-+	if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
-+		return true;
-+
-+
-+	return false;
-+}
-+
-+void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
-+		struct bit_depth_reduction_params *fmt_bit_depth)
-+{
-+	enum dc_dither_option option = stream->dither_option;
-+	enum dc_pixel_encoding pixel_encoding =
-+			stream->timing.pixel_encoding;
-+
-+	memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
-+
-+	if (option == DITHER_OPTION_DEFAULT) {
-+		switch (stream->timing.display_color_depth) {
-+		case COLOR_DEPTH_666:
-+			option = DITHER_OPTION_SPATIAL6;
-+			break;
-+		case COLOR_DEPTH_888:
-+			option = DITHER_OPTION_SPATIAL8;
-+			break;
-+		case COLOR_DEPTH_101010:
-+			option = DITHER_OPTION_SPATIAL10;
-+			break;
-+		default:
-+			option = DITHER_OPTION_DISABLE;
-+		}
-+	}
-+
-+	if (option == DITHER_OPTION_DISABLE)
-+		return;
-+
-+	if (option == DITHER_OPTION_TRUN6) {
-+		fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
-+		fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
-+	} else if (option == DITHER_OPTION_TRUN8 ||
-+			option == DITHER_OPTION_TRUN8_SPATIAL6 ||
-+			option == DITHER_OPTION_TRUN8_FM6) {
-+		fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
-+		fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
-+	} else if (option == DITHER_OPTION_TRUN10        ||
-+			option == DITHER_OPTION_TRUN10_SPATIAL6   ||
-+			option == DITHER_OPTION_TRUN10_SPATIAL8   ||
-+			option == DITHER_OPTION_TRUN10_FM8     ||
-+			option == DITHER_OPTION_TRUN10_FM6     ||
-+			option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
-+		fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
-+		fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
-+	}
-+
-+	/* special case - Formatter can only reduce by 4 bits at most.
-+	 * When reducing from 12 to 6 bits,
-+	 * HW recommends we use trunc with round mode
-+	 * (if we did nothing, trunc to 10 bits would be used)
-+	 * note that any 12->10 bit reduction is ignored prior to DCE8,
-+	 * as the input was 10 bits.
-+	 */
-+	if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
-+			option == DITHER_OPTION_SPATIAL6 ||
-+			option == DITHER_OPTION_FM6) {
-+		fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
-+		fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
-+		fmt_bit_depth->flags.TRUNCATE_MODE = 1;
-+	}
-+
-+	/* spatial dither
-+	 * note that spatial modes 1-3 are never used
-+	 */
-+	if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM            ||
-+			option == DITHER_OPTION_SPATIAL6 ||
-+			option == DITHER_OPTION_TRUN10_SPATIAL6      ||
-+			option == DITHER_OPTION_TRUN8_SPATIAL6) {
-+		fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
-+		fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
-+		fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
-+		fmt_bit_depth->flags.RGB_RANDOM =
-+				(pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
-+	} else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM            ||
-+			option == DITHER_OPTION_SPATIAL8 ||
-+			option == DITHER_OPTION_SPATIAL8_FM6        ||
-+			option == DITHER_OPTION_TRUN10_SPATIAL8      ||
-+			option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
-+		fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
-+		fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
-+		fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
-+		fmt_bit_depth->flags.RGB_RANDOM =
-+				(pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
-+	} else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
-+			option == DITHER_OPTION_SPATIAL10 ||
-+			option == DITHER_OPTION_SPATIAL10_FM8 ||
-+			option == DITHER_OPTION_SPATIAL10_FM6) {
-+		fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
-+		fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
-+		fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
-+		fmt_bit_depth->flags.RGB_RANDOM =
-+				(pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
-+	}
-+
-+	if (option == DITHER_OPTION_SPATIAL6 ||
-+			option == DITHER_OPTION_SPATIAL8 ||
-+			option == DITHER_OPTION_SPATIAL10) {
-+		fmt_bit_depth->flags.FRAME_RANDOM = 0;
-+	} else {
-+		fmt_bit_depth->flags.FRAME_RANDOM = 1;
-+	}
-+
-+	//////////////////////
-+	//// temporal dither
-+	//////////////////////
-+	if (option == DITHER_OPTION_FM6           ||
-+			option == DITHER_OPTION_SPATIAL8_FM6     ||
-+			option == DITHER_OPTION_SPATIAL10_FM6     ||
-+			option == DITHER_OPTION_TRUN10_FM6     ||
-+			option == DITHER_OPTION_TRUN8_FM6      ||
-+			option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
-+		fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
-+		fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
-+	} else if (option == DITHER_OPTION_FM8        ||
-+			option == DITHER_OPTION_SPATIAL10_FM8  ||
-+			option == DITHER_OPTION_TRUN10_FM8) {
-+		fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
-+		fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
-+	} else if (option == DITHER_OPTION_FM10) {
-+		fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
-+		fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
-+	}
-+
-+	fmt_bit_depth->pixel_encoding = pixel_encoding;
-+}
-+
-+enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
-+{
-+	struct dc  *core_dc = dc;
-+	struct dc_link *link = stream->sink->link;
-+	struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
-+	enum dc_status res = DC_OK;
-+
-+	calculate_phy_pix_clks(stream);
-+
-+	if (!tg->funcs->validate_timing(tg, &stream->timing))
-+		res = DC_FAIL_CONTROLLER_VALIDATE;
-+
-+	if (res == DC_OK)
-+		if (!link->link_enc->funcs->validate_output_with_stream(
-+						link->link_enc, stream))
-+			res = DC_FAIL_ENC_VALIDATE;
-+
-+	/* TODO: validate audio ASIC caps, encoder */
-+
-+	if (res == DC_OK)
-+		res = dc_link_validate_mode_timing(stream,
-+		      link,
-+		      &stream->timing);
-+
-+	return res;
-+}
-+
-+enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
-+{
-+	enum dc_status res = DC_OK;
-+
-+	/* TODO For now validates pixel format only */
-+	if (dc->res_pool->funcs->validate_plane)
-+		return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
-+
-+	return res;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_sink.c.0130~	2017-12-14 06:39:58.407903562 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_sink.c	2017-12-14 06:39:58.407903562 +0100
-@@ -0,0 +1,104 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dm_helpers.h"
-+#include "core_types.h"
-+
-+/*******************************************************************************
-+ * Private functions
-+ ******************************************************************************/
-+
-+static void destruct(struct dc_sink *sink)
-+{
-+	if (sink->dc_container_id) {
-+		kfree(sink->dc_container_id);
-+		sink->dc_container_id = NULL;
-+	}
-+}
-+
-+static bool construct(struct dc_sink *sink, const struct dc_sink_init_data *init_params)
-+{
-+
-+	struct dc_link *link = init_params->link;
-+
-+	if (!link)
-+		return false;
-+
-+	sink->sink_signal = init_params->sink_signal;
-+	sink->link = link;
-+	sink->ctx = link->ctx;
-+	sink->dongle_max_pix_clk = init_params->dongle_max_pix_clk;
-+	sink->converter_disable_audio = init_params->converter_disable_audio;
-+	sink->dc_container_id = NULL;
-+
-+	return true;
-+}
-+
-+/*******************************************************************************
-+ * Public functions
-+ ******************************************************************************/
-+
-+void dc_sink_retain(struct dc_sink *sink)
-+{
-+	kref_get(&sink->refcount);
-+}
-+
-+static void dc_sink_free(struct kref *kref)
-+{
-+	struct dc_sink *sink = container_of(kref, struct dc_sink, refcount);
-+	destruct(sink);
-+	kfree(sink);
-+}
-+
-+void dc_sink_release(struct dc_sink *sink)
-+{
-+	kref_put(&sink->refcount, dc_sink_free);
-+}
-+
-+struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params)
-+{
-+	struct dc_sink *sink = kzalloc(sizeof(*sink), GFP_KERNEL);
-+
-+	if (NULL == sink)
-+		goto alloc_fail;
-+
-+	if (false == construct(sink, init_params))
-+		goto construct_fail;
-+
-+	kref_init(&sink->refcount);
-+
-+	return sink;
-+
-+construct_fail:
-+	kfree(sink);
-+
-+alloc_fail:
-+	return NULL;
-+}
-+
-+/*******************************************************************************
-+ * Protected functions - visible only inside of DC (not visible in DM)
-+ ******************************************************************************/
---- linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_stream.c.0130~	2017-12-14 06:39:58.408903562 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_stream.c	2017-12-14 06:39:58.408903562 +0100
-@@ -0,0 +1,395 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dc.h"
-+#include "core_types.h"
-+#include "resource.h"
-+#include "ipp.h"
-+#include "timing_generator.h"
-+
-+/*******************************************************************************
-+ * Private functions
-+ ******************************************************************************/
-+#define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000
-+static void update_stream_signal(struct dc_stream_state *stream)
-+{
-+
-+	struct dc_sink *dc_sink = stream->sink;
-+
-+	if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
-+		stream->signal = stream->sink->link->connector_signal;
-+	else
-+		stream->signal = dc_sink->sink_signal;
-+
-+	if (dc_is_dvi_signal(stream->signal)) {
-+		if (stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST &&
-+			stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
-+			stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
-+		else
-+			stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+	}
-+}
-+
-+static void construct(struct dc_stream_state *stream,
-+	struct dc_sink *dc_sink_data)
-+{
-+	uint32_t i = 0;
-+
-+	stream->sink = dc_sink_data;
-+	stream->ctx = stream->sink->ctx;
-+
-+	dc_sink_retain(dc_sink_data);
-+
-+	/* Copy audio modes */
-+	/* TODO - Remove this translation */
-+	for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++)
-+	{
-+		stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count;
-+		stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code;
-+		stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate;
-+		stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size;
-+	}
-+	stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count;
-+	stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency;
-+	stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency;
-+	memmove(
-+		stream->audio_info.display_name,
-+		dc_sink_data->edid_caps.display_name,
-+		AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
-+	stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id;
-+	stream->audio_info.product_id = dc_sink_data->edid_caps.product_id;
-+	stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags;
-+
-+	if (dc_sink_data->dc_container_id != NULL) {
-+		struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id;
-+
-+		stream->audio_info.port_id[0] = dc_container_id->portId[0];
-+		stream->audio_info.port_id[1] = dc_container_id->portId[1];
-+	} else {
-+		/* TODO - WindowDM has implemented,
-+		other DMs need Unhardcode port_id */
-+		stream->audio_info.port_id[0] = 0x5558859e;
-+		stream->audio_info.port_id[1] = 0xd989449;
-+	}
-+
-+	/* EDID CAP translation for HDMI 2.0 */
-+	stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
-+
-+	stream->status.link = stream->sink->link;
-+
-+	update_stream_signal(stream);
-+}
-+
-+static void destruct(struct dc_stream_state *stream)
-+{
-+	dc_sink_release(stream->sink);
-+	if (stream->out_transfer_func != NULL) {
-+		dc_transfer_func_release(
-+				stream->out_transfer_func);
-+		stream->out_transfer_func = NULL;
-+	}
-+}
-+
-+void dc_stream_retain(struct dc_stream_state *stream)
-+{
-+	kref_get(&stream->refcount);
-+}
-+
-+static void dc_stream_free(struct kref *kref)
-+{
-+	struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount);
-+
-+	destruct(stream);
-+	kfree(stream);
-+}
-+
-+void dc_stream_release(struct dc_stream_state *stream)
-+{
-+	if (stream != NULL) {
-+		kref_put(&stream->refcount, dc_stream_free);
-+	}
-+}
-+
-+struct dc_stream_state *dc_create_stream_for_sink(
-+		struct dc_sink *sink)
-+{
-+	struct dc_stream_state *stream;
-+
-+	if (sink == NULL)
-+		return NULL;
-+
-+	stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);
-+	if (stream == NULL)
-+		return NULL;
-+
-+	construct(stream, sink);
-+
-+	kref_init(&stream->refcount);
-+
-+	return stream;
-+}
-+
-+struct dc_stream_status *dc_stream_get_status(
-+	struct dc_stream_state *stream)
-+{
-+	uint8_t i;
-+	struct dc  *dc = stream->ctx->dc;
-+
-+	for (i = 0; i < dc->current_state->stream_count; i++) {
-+		if (stream == dc->current_state->streams[i])
-+			return &dc->current_state->stream_status[i];
-+	}
-+
-+	return NULL;
-+}
-+
-+/**
-+ * Update the cursor attributes and set cursor surface address
-+ */
-+bool dc_stream_set_cursor_attributes(
-+	struct dc_stream_state *stream,
-+	const struct dc_cursor_attributes *attributes)
-+{
-+	int i;
-+	struct dc  *core_dc;
-+	struct resource_context *res_ctx;
-+
-+	if (NULL == stream) {
-+		dm_error("DC: dc_stream is NULL!\n");
-+		return false;
-+	}
-+	if (NULL == attributes) {
-+		dm_error("DC: attributes is NULL!\n");
-+		return false;
-+	}
-+
-+	if (attributes->address.quad_part == 0) {
-+		dm_output_to_console("DC: Cursor address is 0!\n");
-+		return false;
-+	}
-+
-+	core_dc = stream->ctx->dc;
-+	res_ctx = &core_dc->current_state->res_ctx;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
-+
-+		if (pipe_ctx->stream != stream || (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp))
-+			continue;
-+		if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
-+			continue;
-+
-+
-+		if (pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes != NULL)
-+			pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
-+						pipe_ctx->plane_res.ipp, attributes);
-+
-+		if (pipe_ctx->plane_res.hubp != NULL &&
-+				pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes != NULL)
-+			pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
-+					pipe_ctx->plane_res.hubp, attributes);
-+
-+		if (pipe_ctx->plane_res.mi != NULL &&
-+				pipe_ctx->plane_res.mi->funcs->set_cursor_attributes != NULL)
-+			pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
-+					pipe_ctx->plane_res.mi, attributes);
-+
-+
-+		if (pipe_ctx->plane_res.xfm != NULL &&
-+				pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes != NULL)
-+			pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
-+				pipe_ctx->plane_res.xfm, attributes);
-+
-+		if (pipe_ctx->plane_res.dpp != NULL &&
-+				pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes != NULL)
-+			pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
-+				pipe_ctx->plane_res.dpp, attributes);
-+	}
-+
-+	stream->cursor_attributes = *attributes;
-+
-+	return true;
-+}
-+
-+bool dc_stream_set_cursor_position(
-+	struct dc_stream_state *stream,
-+	const struct dc_cursor_position *position)
-+{
-+	int i;
-+	struct dc  *core_dc;
-+	struct resource_context *res_ctx;
-+
-+	if (NULL == stream) {
-+		dm_error("DC: dc_stream is NULL!\n");
-+		return false;
-+	}
-+
-+	if (NULL == position) {
-+		dm_error("DC: cursor position is NULL!\n");
-+		return false;
-+	}
-+
-+	core_dc = stream->ctx->dc;
-+	res_ctx = &core_dc->current_state->res_ctx;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
-+		struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
-+		struct mem_input *mi = pipe_ctx->plane_res.mi;
-+		struct hubp *hubp = pipe_ctx->plane_res.hubp;
-+		struct transform *xfm = pipe_ctx->plane_res.xfm;
-+		struct dpp *dpp = pipe_ctx->plane_res.dpp;
-+		struct dc_cursor_position pos_cpy = *position;
-+		struct dc_cursor_mi_param param = {
-+			.pixel_clk_khz = stream->timing.pix_clk_khz,
-+			.ref_clk_khz = core_dc->res_pool->ref_clock_inKhz,
-+			.viewport_x_start = pipe_ctx->plane_res.scl_data.viewport.x,
-+			.viewport_width = pipe_ctx->plane_res.scl_data.viewport.width,
-+			.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz
-+		};
-+
-+		if (pipe_ctx->stream != stream ||
-+				(!pipe_ctx->plane_res.mi  && !pipe_ctx->plane_res.hubp) ||
-+				!pipe_ctx->plane_state ||
-+				(!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp))
-+			continue;
-+
-+		if (pipe_ctx->plane_state->address.type
-+				== PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
-+			pos_cpy.enable = false;
-+
-+		if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
-+			pos_cpy.enable = false;
-+
-+
-+		if (ipp != NULL && ipp->funcs->ipp_cursor_set_position != NULL)
-+			ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
-+
-+		if (mi != NULL && mi->funcs->set_cursor_position != NULL)
-+			mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
-+
-+		if (hubp != NULL && hubp->funcs->set_cursor_position != NULL)
-+			hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
-+
-+		if (xfm != NULL && xfm->funcs->set_cursor_position != NULL)
-+			xfm->funcs->set_cursor_position(xfm, &pos_cpy, &param, hubp->curs_attr.width);
-+
-+		if (dpp != NULL && dpp->funcs->set_cursor_position != NULL)
-+			dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width);
-+
-+	}
-+
-+	return true;
-+}
-+
-+uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
-+{
-+	uint8_t i;
-+	struct dc  *core_dc = stream->ctx->dc;
-+	struct resource_context *res_ctx =
-+		&core_dc->current_state->res_ctx;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
-+
-+		if (res_ctx->pipe_ctx[i].stream != stream)
-+			continue;
-+
-+		return tg->funcs->get_frame_count(tg);
-+	}
-+
-+	return 0;
-+}
-+
-+bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
-+				  uint32_t *v_blank_start,
-+				  uint32_t *v_blank_end,
-+				  uint32_t *h_position,
-+				  uint32_t *v_position)
-+{
-+	uint8_t i;
-+	bool ret = false;
-+	struct dc  *core_dc = stream->ctx->dc;
-+	struct resource_context *res_ctx =
-+		&core_dc->current_state->res_ctx;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
-+
-+		if (res_ctx->pipe_ctx[i].stream != stream)
-+			continue;
-+
-+		tg->funcs->get_scanoutpos(tg,
-+					  v_blank_start,
-+					  v_blank_end,
-+					  h_position,
-+					  v_position);
-+
-+		ret = true;
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+
-+void dc_stream_log(
-+	const struct dc_stream_state *stream,
-+	struct dal_logger *dm_logger,
-+	enum dc_log_type log_type)
-+{
-+
-+	dm_logger_write(dm_logger,
-+			log_type,
-+			"core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n",
-+			stream,
-+			stream->src.x,
-+			stream->src.y,
-+			stream->src.width,
-+			stream->src.height,
-+			stream->dst.x,
-+			stream->dst.y,
-+			stream->dst.width,
-+			stream->dst.height,
-+			stream->output_color_space);
-+	dm_logger_write(dm_logger,
-+			log_type,
-+			"\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
-+			stream->timing.pix_clk_khz,
-+			stream->timing.h_total,
-+			stream->timing.v_total,
-+			stream->timing.pixel_encoding,
-+			stream->timing.display_color_depth);
-+	dm_logger_write(dm_logger,
-+			log_type,
-+			"\tsink name: %s, serial: %d\n",
-+			stream->sink->edid_caps.display_name,
-+			stream->sink->edid_caps.serial_number);
-+	dm_logger_write(dm_logger,
-+			log_type,
-+			"\tlink: %d\n",
-+			stream->sink->link->link_index);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_surface.c.0130~	2017-12-14 06:39:58.408903562 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/core/dc_surface.c	2017-12-14 06:39:58.408903562 +0100
-@@ -0,0 +1,193 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/* DC interface (public) */
-+#include "dm_services.h"
-+#include "dc.h"
-+
-+/* DC core (private) */
-+#include "core_types.h"
-+#include "transform.h"
-+#include "dpp.h"
-+
-+/*******************************************************************************
-+ * Private functions
-+ ******************************************************************************/
-+static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state)
-+{
-+	plane_state->ctx = ctx;
-+}
-+
-+static void destruct(struct dc_plane_state *plane_state)
-+{
-+	if (plane_state->gamma_correction != NULL) {
-+		dc_gamma_release(&plane_state->gamma_correction);
-+	}
-+	if (plane_state->in_transfer_func != NULL) {
-+		dc_transfer_func_release(
-+				plane_state->in_transfer_func);
-+		plane_state->in_transfer_func = NULL;
-+	}
-+}
-+
-+/*******************************************************************************
-+ * Public functions
-+ ******************************************************************************/
-+void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
-+		uint32_t controller_id)
-+{
-+	plane_state->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1;
-+	/*register_flip_interrupt(surface);*/
-+}
-+
-+struct dc_plane_state *dc_create_plane_state(struct dc *dc)
-+{
-+	struct dc *core_dc = dc;
-+
-+	struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state),
-+						     GFP_KERNEL);
-+
-+	if (NULL == plane_state)
-+		return NULL;
-+
-+	kref_init(&plane_state->refcount);
-+	construct(core_dc->ctx, plane_state);
-+
-+	return plane_state;
-+}
-+
-+const struct dc_plane_status *dc_plane_get_status(
-+		const struct dc_plane_state *plane_state)
-+{
-+	const struct dc_plane_status *plane_status;
-+	struct dc  *core_dc;
-+	int i;
-+
-+	if (!plane_state ||
-+		!plane_state->ctx ||
-+		!plane_state->ctx->dc) {
-+		ASSERT(0);
-+		return NULL; /* remove this if above assert never hit */
-+	}
-+
-+	plane_status = &plane_state->status;
-+	core_dc = plane_state->ctx->dc;
-+
-+	if (core_dc->current_state == NULL)
-+		return NULL;
-+
-+	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
-+		struct pipe_ctx *pipe_ctx =
-+				&core_dc->current_state->res_ctx.pipe_ctx[i];
-+
-+		if (pipe_ctx->plane_state != plane_state)
-+			continue;
-+
-+		core_dc->hwss.update_pending_status(pipe_ctx);
-+	}
-+
-+	return plane_status;
-+}
-+
-+void dc_plane_state_retain(struct dc_plane_state *plane_state)
-+{
-+	kref_get(&plane_state->refcount);
-+}
-+
-+static void dc_plane_state_free(struct kref *kref)
-+{
-+	struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);
-+	destruct(plane_state);
-+	kfree(plane_state);
-+}
-+
-+void dc_plane_state_release(struct dc_plane_state *plane_state)
-+{
-+	kref_put(&plane_state->refcount, dc_plane_state_free);
-+}
-+
-+void dc_gamma_retain(struct dc_gamma *gamma)
-+{
-+	kref_get(&gamma->refcount);
-+}
-+
-+static void dc_gamma_free(struct kref *kref)
-+{
-+	struct dc_gamma *gamma = container_of(kref, struct dc_gamma, refcount);
-+	kfree(gamma);
-+}
-+
-+void dc_gamma_release(struct dc_gamma **gamma)
-+{
-+	kref_put(&(*gamma)->refcount, dc_gamma_free);
-+	*gamma = NULL;
-+}
-+
-+struct dc_gamma *dc_create_gamma(void)
-+{
-+	struct dc_gamma *gamma = kzalloc(sizeof(*gamma), GFP_KERNEL);
-+
-+	if (gamma == NULL)
-+		goto alloc_fail;
-+
-+	kref_init(&gamma->refcount);
-+	return gamma;
-+
-+alloc_fail:
-+	return NULL;
-+}
-+
-+void dc_transfer_func_retain(struct dc_transfer_func *tf)
-+{
-+	kref_get(&tf->refcount);
-+}
-+
-+static void dc_transfer_func_free(struct kref *kref)
-+{
-+	struct dc_transfer_func *tf = container_of(kref, struct dc_transfer_func, refcount);
-+	kfree(tf);
-+}
-+
-+void dc_transfer_func_release(struct dc_transfer_func *tf)
-+{
-+	kref_put(&tf->refcount, dc_transfer_func_free);
-+}
-+
-+struct dc_transfer_func *dc_create_transfer_func(void)
-+{
-+	struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL);
-+
-+	if (tf == NULL)
-+		goto alloc_fail;
-+
-+	kref_init(&tf->refcount);
-+
-+	return tf;
-+
-+alloc_fail:
-+	return NULL;
-+}
-+
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dc_bios_types.h.0130~	2017-12-14 06:39:58.408903562 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dc_bios_types.h	2017-12-14 06:39:58.408903562 +0100
-@@ -0,0 +1,218 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef DC_BIOS_TYPES_H
-+#define DC_BIOS_TYPES_H
-+
-+/******************************************************************************
-+ * Interface file for VBIOS implementations.
-+ *
-+ * The default implementation is inside DC.
-+ * Display Manager (which instantiates DC) has the option to supply it's own
-+ * (external to DC) implementation of VBIOS, which will be called by DC, using
-+ * this interface.
-+ * (The intended use is Diagnostics, but other uses may appear.)
-+ *****************************************************************************/
-+
-+#include "include/bios_parser_types.h"
-+
-+struct dc_vbios_funcs {
-+	uint8_t (*get_connectors_number)(struct dc_bios *bios);
-+
-+	struct graphics_object_id (*get_encoder_id)(
-+		struct dc_bios *bios,
-+		uint32_t i);
-+	struct graphics_object_id (*get_connector_id)(
-+		struct dc_bios *bios,
-+		uint8_t connector_index);
-+	uint32_t (*get_dst_number)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id id);
-+
-+	enum bp_result (*get_src_obj)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id object_id, uint32_t index,
-+		struct graphics_object_id *src_object_id);
-+	enum bp_result (*get_dst_obj)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id object_id, uint32_t index,
-+		struct graphics_object_id *dest_object_id);
-+
-+	enum bp_result (*get_i2c_info)(
-+		struct dc_bios *dcb,
-+		struct graphics_object_id id,
-+		struct graphics_object_i2c_info *info);
-+
-+	enum bp_result (*get_voltage_ddc_info)(
-+		struct dc_bios *bios,
-+		uint32_t index,
-+		struct graphics_object_i2c_info *info);
-+	enum bp_result (*get_thermal_ddc_info)(
-+		struct dc_bios *bios,
-+		uint32_t i2c_channel_id,
-+		struct graphics_object_i2c_info *info);
-+	enum bp_result (*get_hpd_info)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id id,
-+		struct graphics_object_hpd_info *info);
-+	enum bp_result (*get_device_tag)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id connector_object_id,
-+		uint32_t device_tag_index,
-+		struct connector_device_tag_info *info);
-+	enum bp_result (*get_firmware_info)(
-+		struct dc_bios *bios,
-+		struct dc_firmware_info *info);
-+	enum bp_result (*get_spread_spectrum_info)(
-+		struct dc_bios *bios,
-+		enum as_signal_type signal,
-+		uint32_t index,
-+		struct spread_spectrum_info *ss_info);
-+	uint32_t (*get_ss_entry_number)(
-+		struct dc_bios *bios,
-+		enum as_signal_type signal);
-+	enum bp_result (*get_embedded_panel_info)(
-+		struct dc_bios *bios,
-+		struct embedded_panel_info *info);
-+	enum bp_result (*get_gpio_pin_info)(
-+		struct dc_bios *bios,
-+		uint32_t gpio_id,
-+		struct gpio_pin_info *info);
-+	enum bp_result (*get_encoder_cap_info)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id object_id,
-+		struct bp_encoder_cap_info *info);
-+
-+	bool (*is_lid_status_changed)(
-+		struct dc_bios *bios);
-+	bool (*is_display_config_changed)(
-+		struct dc_bios *bios);
-+	bool (*is_accelerated_mode)(
-+		struct dc_bios *bios);
-+	void (*get_bios_event_info)(
-+		struct dc_bios *bios,
-+		struct bios_event_info *info);
-+	void (*update_requested_backlight_level)(
-+		struct dc_bios *bios,
-+		uint32_t backlight_8bit);
-+	uint32_t (*get_requested_backlight_level)(
-+		struct dc_bios *bios);
-+	void (*take_backlight_control)(
-+		struct dc_bios *bios,
-+		bool cntl);
-+
-+	bool (*is_active_display)(
-+		struct dc_bios *bios,
-+		enum signal_type signal,
-+		const struct connector_device_tag_info *device_tag);
-+	enum controller_id (*get_embedded_display_controller_id)(
-+		struct dc_bios *bios);
-+	uint32_t (*get_embedded_display_refresh_rate)(
-+		struct dc_bios *bios);
-+
-+	void (*set_scratch_critical_state)(
-+		struct dc_bios *bios,
-+		bool state);
-+	bool (*is_device_id_supported)(
-+		struct dc_bios *bios,
-+		struct device_id id);
-+
-+	/* COMMANDS */
-+
-+	enum bp_result (*encoder_control)(
-+		struct dc_bios *bios,
-+		struct bp_encoder_control *cntl);
-+	enum bp_result (*transmitter_control)(
-+		struct dc_bios *bios,
-+		struct bp_transmitter_control *cntl);
-+	enum bp_result (*crt_control)(
-+		struct dc_bios *bios,
-+		enum engine_id engine_id,
-+		bool enable,
-+		uint32_t pixel_clock);
-+	enum bp_result (*enable_crtc)(
-+		struct dc_bios *bios,
-+		enum controller_id id,
-+		bool enable);
-+	enum bp_result (*adjust_pixel_clock)(
-+		struct dc_bios *bios,
-+		struct bp_adjust_pixel_clock_parameters *bp_params);
-+	enum bp_result (*set_pixel_clock)(
-+		struct dc_bios *bios,
-+		struct bp_pixel_clock_parameters *bp_params);
-+	enum bp_result (*set_dce_clock)(
-+		struct dc_bios *bios,
-+		struct bp_set_dce_clock_parameters *bp_params);
-+	unsigned int (*get_smu_clock_info)(
-+		struct dc_bios *bios);
-+	enum bp_result (*enable_spread_spectrum_on_ppll)(
-+		struct dc_bios *bios,
-+		struct bp_spread_spectrum_parameters *bp_params,
-+		bool enable);
-+	enum bp_result (*program_crtc_timing)(
-+		struct dc_bios *bios,
-+		struct bp_hw_crtc_timing_parameters *bp_params);
-+
-+	enum bp_result (*crtc_source_select)(
-+		struct dc_bios *bios,
-+		struct bp_crtc_source_select *bp_params);
-+	enum bp_result (*program_display_engine_pll)(
-+		struct dc_bios *bios,
-+		struct bp_pixel_clock_parameters *bp_params);
-+
-+	enum signal_type (*dac_load_detect)(
-+		struct dc_bios *bios,
-+		struct graphics_object_id encoder,
-+		struct graphics_object_id connector,
-+		enum signal_type display_signal);
-+
-+	enum bp_result (*enable_disp_power_gating)(
-+		struct dc_bios *bios,
-+		enum controller_id controller_id,
-+		enum bp_pipe_control_action action);
-+
-+	void (*post_init)(struct dc_bios *bios);
-+
-+	void (*bios_parser_destroy)(struct dc_bios **dcb);
-+};
-+
-+struct bios_registers {
-+	uint32_t BIOS_SCRATCH_6;
-+};
-+
-+struct dc_bios {
-+	const struct dc_vbios_funcs *funcs;
-+
-+	uint8_t *bios;
-+	uint32_t bios_size;
-+
-+	uint8_t *bios_local_image;
-+
-+	struct dc_context *ctx;
-+	const struct bios_registers *regs;
-+	struct integrated_info *integrated_info;
-+};
-+
-+#endif /* DC_BIOS_TYPES_H */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h.0130~	2017-12-14 06:39:58.408903562 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h	2017-12-14 06:39:58.408903562 +0100
-@@ -0,0 +1,115 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef DC_DDC_TYPES_H_
-+#define DC_DDC_TYPES_H_
-+
-+struct i2c_payload {
-+	bool write;
-+	uint8_t address;
-+	uint32_t length;
-+	uint8_t *data;
-+};
-+
-+enum i2c_command_engine {
-+	I2C_COMMAND_ENGINE_DEFAULT,
-+	I2C_COMMAND_ENGINE_SW,
-+	I2C_COMMAND_ENGINE_HW
-+};
-+
-+struct i2c_command {
-+	struct i2c_payload *payloads;
-+	uint8_t number_of_payloads;
-+
-+	enum i2c_command_engine engine;
-+
-+	/* expressed in KHz
-+	 * zero means "use default value" */
-+	uint32_t speed;
-+};
-+
-+struct gpio_ddc_hw_info {
-+	bool hw_supported;
-+	uint32_t ddc_channel;
-+};
-+
-+struct ddc {
-+	struct gpio *pin_data;
-+	struct gpio *pin_clock;
-+	struct gpio_ddc_hw_info hw_info;
-+	struct dc_context *ctx;
-+};
-+
-+union ddc_wa {
-+	struct {
-+		uint32_t DP_SKIP_POWER_OFF:1;
-+		uint32_t DP_AUX_POWER_UP_WA_DELAY:1;
-+	} bits;
-+	uint32_t raw;
-+};
-+
-+struct ddc_flags {
-+	uint8_t EDID_QUERY_DONE_ONCE:1;
-+	uint8_t IS_INTERNAL_DISPLAY:1;
-+	uint8_t FORCE_READ_REPEATED_START:1;
-+	uint8_t EDID_STRESS_READ:1;
-+
-+};
-+
-+enum ddc_transaction_type {
-+	DDC_TRANSACTION_TYPE_NONE = 0,
-+	DDC_TRANSACTION_TYPE_I2C,
-+	DDC_TRANSACTION_TYPE_I2C_OVER_AUX,
-+	DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER,
-+	DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER
-+};
-+
-+enum display_dongle_type {
-+	DISPLAY_DONGLE_NONE = 0,
-+	/* Active converter types*/
-+	DISPLAY_DONGLE_DP_VGA_CONVERTER,
-+	DISPLAY_DONGLE_DP_DVI_CONVERTER,
-+	DISPLAY_DONGLE_DP_HDMI_CONVERTER,
-+	/* DP-HDMI/DVI passive dongles (Type 1 and Type 2)*/
-+	DISPLAY_DONGLE_DP_DVI_DONGLE,
-+	DISPLAY_DONGLE_DP_HDMI_DONGLE,
-+	/* Other types of dongle*/
-+	DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE,
-+};
-+
-+struct ddc_service {
-+	struct ddc *ddc_pin;
-+	struct ddc_flags flags;
-+	union ddc_wa wa;
-+	enum ddc_transaction_type transaction_type;
-+	enum display_dongle_type dongle_type;
-+	struct dc_context *ctx;
-+	struct dc_link *link;
-+
-+	uint32_t address;
-+	uint32_t edid_buf_len;
-+	uint8_t edid_buf[MAX_EDID_BUFFER_SIZE];
-+};
-+
-+#endif /* DC_DDC_TYPES_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dc_dp_types.h.0130~	2017-12-14 06:39:58.408903562 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dc_dp_types.h	2017-12-14 06:39:58.408903562 +0100
-@@ -0,0 +1,493 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef DC_DP_TYPES_H
-+#define DC_DP_TYPES_H
-+
-+enum dc_lane_count {
-+	LANE_COUNT_UNKNOWN = 0,
-+	LANE_COUNT_ONE = 1,
-+	LANE_COUNT_TWO = 2,
-+	LANE_COUNT_FOUR = 4,
-+	LANE_COUNT_EIGHT = 8,
-+	LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
-+};
-+
-+/* This is actually a reference clock (27MHz) multiplier
-+ * 162MBps bandwidth for 1.62GHz like rate,
-+ * 270MBps for 2.70GHz,
-+ * 324MBps for 3.24Ghz,
-+ * 540MBps for 5.40GHz
-+ * 810MBps for 8.10GHz
-+ */
-+enum dc_link_rate {
-+	LINK_RATE_UNKNOWN = 0,
-+	LINK_RATE_LOW = 0x06,
-+	LINK_RATE_HIGH = 0x0A,
-+	LINK_RATE_RBR2 = 0x0C,
-+	LINK_RATE_HIGH2 = 0x14,
-+	LINK_RATE_HIGH3 = 0x1E
-+};
-+
-+enum dc_link_spread {
-+	LINK_SPREAD_DISABLED = 0x00,
-+	/* 0.5 % downspread 30 kHz */
-+	LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
-+	/* 0.5 % downspread 33 kHz */
-+	LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
-+};
-+
-+enum dc_voltage_swing {
-+	VOLTAGE_SWING_LEVEL0 = 0,	/* direct HW translation! */
-+	VOLTAGE_SWING_LEVEL1,
-+	VOLTAGE_SWING_LEVEL2,
-+	VOLTAGE_SWING_LEVEL3,
-+	VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
-+};
-+
-+enum dc_pre_emphasis {
-+	PRE_EMPHASIS_DISABLED = 0,	/* direct HW translation! */
-+	PRE_EMPHASIS_LEVEL1,
-+	PRE_EMPHASIS_LEVEL2,
-+	PRE_EMPHASIS_LEVEL3,
-+	PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
-+};
-+/* Post Cursor 2 is optional for transmitter
-+ * and it applies only to the main link operating at HBR2
-+ */
-+enum dc_post_cursor2 {
-+	POST_CURSOR2_DISABLED = 0,	/* direct HW translation! */
-+	POST_CURSOR2_LEVEL1,
-+	POST_CURSOR2_LEVEL2,
-+	POST_CURSOR2_LEVEL3,
-+	POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
-+};
-+
-+struct dc_link_settings {
-+	enum dc_lane_count lane_count;
-+	enum dc_link_rate link_rate;
-+	enum dc_link_spread link_spread;
-+};
-+
-+struct dc_lane_settings {
-+	enum dc_voltage_swing VOLTAGE_SWING;
-+	enum dc_pre_emphasis PRE_EMPHASIS;
-+	enum dc_post_cursor2 POST_CURSOR2;
-+};
-+
-+struct dc_link_training_settings {
-+	struct dc_link_settings link;
-+	struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
-+};
-+
-+
-+union dpcd_rev {
-+	struct {
-+		uint8_t MINOR:4;
-+		uint8_t MAJOR:4;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union max_lane_count {
-+	struct {
-+		uint8_t MAX_LANE_COUNT:5;
-+		uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
-+		uint8_t TPS3_SUPPORTED:1;
-+		uint8_t ENHANCED_FRAME_CAP:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union max_down_spread {
-+	struct {
-+		uint8_t MAX_DOWN_SPREAD:1;
-+		uint8_t RESERVED:5;
-+		uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
-+		uint8_t TPS4_SUPPORTED:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union mstm_cap {
-+	struct {
-+		uint8_t MST_CAP:1;
-+		uint8_t RESERVED:7;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union lane_count_set {
-+	struct {
-+		uint8_t LANE_COUNT_SET:5;
-+		uint8_t POST_LT_ADJ_REQ_GRANTED:1;
-+		uint8_t RESERVED:1;
-+		uint8_t ENHANCED_FRAMING:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union lane_status {
-+	struct {
-+		uint8_t CR_DONE_0:1;
-+		uint8_t CHANNEL_EQ_DONE_0:1;
-+		uint8_t SYMBOL_LOCKED_0:1;
-+		uint8_t RESERVED0:1;
-+		uint8_t CR_DONE_1:1;
-+		uint8_t CHANNEL_EQ_DONE_1:1;
-+		uint8_t SYMBOL_LOCKED_1:1;
-+		uint8_t RESERVED_1:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union device_service_irq {
-+	struct {
-+		uint8_t REMOTE_CONTROL_CMD_PENDING:1;
-+		uint8_t AUTOMATED_TEST:1;
-+		uint8_t CP_IRQ:1;
-+		uint8_t MCCS_IRQ:1;
-+		uint8_t DOWN_REP_MSG_RDY:1;
-+		uint8_t UP_REQ_MSG_RDY:1;
-+		uint8_t SINK_SPECIFIC:1;
-+		uint8_t reserved:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union sink_count {
-+	struct {
-+		uint8_t SINK_COUNT:6;
-+		uint8_t CPREADY:1;
-+		uint8_t RESERVED:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union lane_align_status_updated {
-+	struct {
-+		uint8_t INTERLANE_ALIGN_DONE:1;
-+		uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
-+		uint8_t RESERVED:4;
-+		uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
-+		uint8_t LINK_STATUS_UPDATED:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union lane_adjust {
-+	struct {
-+		uint8_t VOLTAGE_SWING_LANE:2;
-+		uint8_t PRE_EMPHASIS_LANE:2;
-+		uint8_t RESERVED:4;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union dpcd_training_pattern {
-+	struct {
-+		uint8_t TRAINING_PATTERN_SET:4;
-+		uint8_t RECOVERED_CLOCK_OUT_EN:1;
-+		uint8_t SCRAMBLING_DISABLE:1;
-+		uint8_t SYMBOL_ERROR_COUNT_SEL:2;
-+	} v1_4;
-+	struct {
-+		uint8_t TRAINING_PATTERN_SET:2;
-+		uint8_t LINK_QUAL_PATTERN_SET:2;
-+		uint8_t RESERVED:4;
-+	} v1_3;
-+	uint8_t raw;
-+};
-+
-+/* Training Lane is used to configure downstream DP device's voltage swing
-+and pre-emphasis levels*/
-+/* The DPCD addresses are from 0x103 to 0x106*/
-+union dpcd_training_lane {
-+	struct {
-+		uint8_t VOLTAGE_SWING_SET:2;
-+		uint8_t MAX_SWING_REACHED:1;
-+		uint8_t PRE_EMPHASIS_SET:2;
-+		uint8_t MAX_PRE_EMPHASIS_REACHED:1;
-+		uint8_t RESERVED:2;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/* TMDS-converter related */
-+union dwnstream_port_caps_byte0 {
-+	struct {
-+		uint8_t DWN_STRM_PORTX_TYPE:3;
-+		uint8_t DWN_STRM_PORTX_HPD:1;
-+		uint8_t RESERVERD:4;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
-+enum dpcd_downstream_port_detailed_type {
-+	DOWN_STREAM_DETAILED_DP = 0,
-+	DOWN_STREAM_DETAILED_VGA,
-+	DOWN_STREAM_DETAILED_DVI,
-+	DOWN_STREAM_DETAILED_HDMI,
-+	DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
-+	DOWN_STREAM_DETAILED_DP_PLUS_PLUS
-+};
-+
-+union dwnstream_port_caps_byte2 {
-+	struct {
-+		uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
-+		uint8_t RESERVED:6;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union dp_downstream_port_present {
-+	uint8_t byte;
-+	struct {
-+		uint8_t PORT_PRESENT:1;
-+		uint8_t PORT_TYPE:2;
-+		uint8_t FMT_CONVERSION:1;
-+		uint8_t DETAILED_CAPS:1;
-+		uint8_t RESERVED:3;
-+	} fields;
-+};
-+
-+union dwnstream_port_caps_byte3_dvi {
-+	struct {
-+		uint8_t RESERVED1:1;
-+		uint8_t DUAL_LINK:1;
-+		uint8_t HIGH_COLOR_DEPTH:1;
-+		uint8_t RESERVED2:5;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union dwnstream_port_caps_byte3_hdmi {
-+	struct {
-+		uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
-+		uint8_t YCrCr422_PASS_THROUGH:1;
-+		uint8_t YCrCr420_PASS_THROUGH:1;
-+		uint8_t YCrCr422_CONVERSION:1;
-+		uint8_t YCrCr420_CONVERSION:1;
-+		uint8_t RESERVED:3;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/*4-byte structure for detailed capabilities of a down-stream port
-+(DP-to-TMDS converter).*/
-+union dwnstream_portxcaps {
-+	struct {
-+		union dwnstream_port_caps_byte0 byte0;
-+		unsigned char max_TMDS_clock;   //byte1
-+		union dwnstream_port_caps_byte2 byte2;
-+
-+		union {
-+			union dwnstream_port_caps_byte3_dvi byteDVI;
-+			union dwnstream_port_caps_byte3_hdmi byteHDMI;
-+		} byte3;
-+	} bytes;
-+
-+	unsigned char raw[4];
-+};
-+
-+union downstream_port {
-+	struct {
-+		unsigned char   present:1;
-+		unsigned char   type:2;
-+		unsigned char   format_conv:1;
-+		unsigned char   detailed_caps:1;
-+		unsigned char   reserved:3;
-+	} bits;
-+	unsigned char raw;
-+};
-+
-+
-+union sink_status {
-+	struct {
-+		uint8_t RX_PORT0_STATUS:1;
-+		uint8_t RX_PORT1_STATUS:1;
-+		uint8_t RESERVED:6;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/*6-byte structure corresponding to 6 registers (200h-205h)
-+read during handling of HPD-IRQ*/
-+union hpd_irq_data {
-+	struct {
-+		union sink_count sink_cnt;/* 200h */
-+		union device_service_irq device_service_irq;/* 201h */
-+		union lane_status lane01_status;/* 202h */
-+		union lane_status lane23_status;/* 203h */
-+		union lane_align_status_updated lane_status_updated;/* 204h */
-+		union sink_status sink_status;
-+	} bytes;
-+	uint8_t raw[6];
-+};
-+
-+union down_stream_port_count {
-+	struct {
-+		uint8_t DOWN_STR_PORT_COUNT:4;
-+		uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/
-+		/*Bit 6 = MSA_TIMING_PAR_IGNORED
-+		0 = Sink device requires the MSA timing parameters
-+		1 = Sink device is capable of rendering incoming video
-+		 stream without MSA timing parameters*/
-+		uint8_t IGNORE_MSA_TIMING_PARAM:1;
-+		/*Bit 7 = OUI Support
-+		0 = OUI not supported
-+		1 = OUI supported
-+		(OUI and Device Identification mandatory for DP 1.2)*/
-+		uint8_t OUI_SUPPORT:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union down_spread_ctrl {
-+	struct {
-+		uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
-+	/* Bits 4 = SPREAD_AMP. Spreading amplitude
-+	0 = Main link signal is not downspread
-+	1 = Main link signal is downspread <= 0.5%
-+	with frequency in the range of 30kHz ~ 33kHz*/
-+		uint8_t SPREAD_AMP:1;
-+		uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/
-+	/*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
-+	0 = Source device will send valid data for the MSA Timing Params
-+	1 = Source device may send invalid data for these MSA Timing Params*/
-+		uint8_t IGNORE_MSA_TIMING_PARAM:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union dpcd_edp_config {
-+	struct {
-+		uint8_t PANEL_MODE_EDP:1;
-+		uint8_t FRAMING_CHANGE_ENABLE:1;
-+		uint8_t RESERVED:5;
-+		uint8_t PANEL_SELF_TEST_ENABLE:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+struct dp_device_vendor_id {
-+	uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
-+	uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
-+};
-+
-+struct dp_sink_hw_fw_revision {
-+	uint8_t ieee_hw_rev;
-+	uint8_t ieee_fw_rev[2];
-+};
-+
-+/*DPCD register of DP receiver capability field bits-*/
-+union edp_configuration_cap {
-+	struct {
-+		uint8_t ALT_SCRAMBLER_RESET:1;
-+		uint8_t FRAMING_CHANGE:1;
-+		uint8_t RESERVED:1;
-+		uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
-+		uint8_t RESERVED2:4;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union training_aux_rd_interval {
-+	struct {
-+		uint8_t TRAINIG_AUX_RD_INTERVAL:7;
-+		uint8_t EXT_RECIEVER_CAP_FIELD_PRESENT:1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/* Automated test structures */
-+union test_request {
-+	struct {
-+	uint8_t LINK_TRAINING         :1;
-+	uint8_t LINK_TEST_PATTRN      :1;
-+	uint8_t EDID_REAT             :1;
-+	uint8_t PHY_TEST_PATTERN      :1;
-+	uint8_t AUDIO_TEST_PATTERN    :1;
-+	uint8_t RESERVED              :1;
-+	uint8_t TEST_STEREO_3D        :1;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union test_response {
-+	struct {
-+		uint8_t ACK         :1;
-+		uint8_t NO_ACK      :1;
-+		uint8_t RESERVED    :6;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+union phy_test_pattern {
-+	struct {
-+		/* DpcdPhyTestPatterns. This field is 2 bits for DP1.1
-+		 * and 3 bits for DP1.2.
-+		 */
-+		uint8_t PATTERN     :3;
-+		/* BY speci, bit7:2 is 0 for DP1.1. */
-+		uint8_t RESERVED    :5;
-+	} bits;
-+	uint8_t raw;
-+};
-+
-+/* States of Compliance Test Specification (CTS DP1.2). */
-+union compliance_test_state {
-+	struct {
-+		unsigned char STEREO_3D_RUNNING        : 1;
-+		unsigned char RESERVED                 : 7;
-+	} bits;
-+	unsigned char raw;
-+};
-+
-+union link_test_pattern {
-+	struct {
-+		/* dpcd_link_test_patterns */
-+		unsigned char PATTERN :2;
-+		unsigned char RESERVED:6;
-+	} bits;
-+	unsigned char raw;
-+};
-+
-+union test_misc {
-+	struct dpcd_test_misc_bits {
-+		unsigned char SYNC_CLOCK :1;
-+		/* dpcd_test_color_format */
-+		unsigned char CLR_FORMAT :2;
-+		/* dpcd_test_dyn_range */
-+		unsigned char DYN_RANGE  :1;
-+		unsigned char YCBCR      :1;
-+		/* dpcd_test_bit_depth */
-+		unsigned char BPC        :3;
-+	} bits;
-+	unsigned char raw;
-+};
-+
-+#endif /* DC_DP_TYPES_H */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c.0130~	2017-12-14 06:39:58.408903562 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c	2017-12-14 06:39:58.408903562 +0100
-@@ -0,0 +1,154 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dm_services.h"
-+#include "dc.h"
-+#include "core_types.h"
-+#include "hw_sequencer.h"
-+#include "dce100_hw_sequencer.h"
-+#include "resource.h"
-+
-+#include "dce110/dce110_hw_sequencer.h"
-+
-+/* include DCE10 register header files */
-+#include "dce/dce_10_0_d.h"
-+#include "dce/dce_10_0_sh_mask.h"
-+
-+struct dce100_hw_seq_reg_offsets {
-+	uint32_t blnd;
-+	uint32_t crtc;
-+};
-+
-+static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
-+{
-+	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+}
-+};
-+
-+#define HW_REG_CRTC(reg, id)\
-+	(reg + reg_offsets[id].crtc)
-+
-+/*******************************************************************************
-+ * Private definitions
-+ ******************************************************************************/
-+/***************************PIPE_CONTROL***********************************/
-+
-+static bool dce100_enable_display_power_gating(
-+	struct dc *dc,
-+	uint8_t controller_id,
-+	struct dc_bios *dcb,
-+	enum pipe_gating_control power_gating)
-+{
-+	enum bp_result bp_result = BP_RESULT_OK;
-+	enum bp_pipe_control_action cntl;
-+	struct dc_context *ctx = dc->ctx;
-+
-+	if (power_gating == PIPE_GATING_CONTROL_INIT)
-+		cntl = ASIC_PIPE_INIT;
-+	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
-+		cntl = ASIC_PIPE_ENABLE;
-+	else
-+		cntl = ASIC_PIPE_DISABLE;
-+
-+	if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){
-+
-+		bp_result = dcb->funcs->enable_disp_power_gating(
-+						dcb, controller_id + 1, cntl);
-+
-+		/* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
-+		 * by default when command table is called
-+		 */
-+		dm_write_reg(ctx,
-+			HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id),
-+			0);
-+	}
-+
-+	if (bp_result == BP_RESULT_OK)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+static void dce100_pplib_apply_display_requirements(
-+	struct dc *dc,
-+	struct dc_state *context)
-+{
-+	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
-+
-+	pp_display_cfg->avail_mclk_switch_time_us =
-+						dce110_get_min_vblank_time_us(context);
-+	/*pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
-+		/ MEMORY_TYPE_MULTIPLIER;*/
-+
-+	dce110_fill_display_configs(context, pp_display_cfg);
-+
-+	if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
-+			struct dm_pp_display_configuration)) !=  0)
-+		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
-+
-+	dc->prev_display_config = *pp_display_cfg;
-+}
-+
-+void dce100_set_bandwidth(
-+		struct dc *dc,
-+		struct dc_state *context,
-+		bool decrease_allowed)
-+{
-+	if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) {
-+		dc->res_pool->display_clock->funcs->set_clock(
-+				dc->res_pool->display_clock,
-+				context->bw.dce.dispclk_khz * 115 / 100);
-+		dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz;
-+	}
-+	dce100_pplib_apply_display_requirements(dc, context);
-+}
-+
-+
-+/**************************************************************************/
-+
-+void dce100_hw_sequencer_construct(struct dc *dc)
-+{
-+	dce110_hw_sequencer_construct(dc);
-+
-+	dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
-+	dc->hwss.set_bandwidth = dce100_set_bandwidth;
-+	dc->hwss.pplib_apply_display_requirements =
-+			dce100_pplib_apply_display_requirements;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h.0130~	2017-12-14 06:39:58.408903562 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h	2017-12-14 06:39:58.408903562 +0100
-@@ -0,0 +1,42 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_HWSS_DCE100_H__
-+#define __DC_HWSS_DCE100_H__
-+
-+#include "core_types.h"
-+
-+struct dc;
-+struct dc_state;
-+
-+void dce100_hw_sequencer_construct(struct dc *dc);
-+
-+void dce100_set_bandwidth(
-+		struct dc *dc,
-+		struct dc_state *context,
-+		bool decrease_allowed);
-+
-+#endif /* __DC_HWSS_DCE100_H__ */
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c.0130~	2017-12-14 06:39:58.408903562 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c	2017-12-14 06:39:58.408903562 +0100
-@@ -0,0 +1,933 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dm_services.h"
-+
-+#include "link_encoder.h"
-+#include "stream_encoder.h"
-+
-+#include "resource.h"
-+#include "include/irq_service_interface.h"
-+#include "../virtual/virtual_stream_encoder.h"
-+#include "dce110/dce110_resource.h"
-+#include "dce110/dce110_timing_generator.h"
-+#include "irq/dce110/irq_service_dce110.h"
-+#include "dce/dce_link_encoder.h"
-+#include "dce/dce_stream_encoder.h"
-+
-+#include "dce/dce_mem_input.h"
-+#include "dce/dce_ipp.h"
-+#include "dce/dce_transform.h"
-+#include "dce/dce_opp.h"
-+#include "dce/dce_clocks.h"
-+#include "dce/dce_clock_source.h"
-+#include "dce/dce_audio.h"
-+#include "dce/dce_hwseq.h"
-+#include "dce100/dce100_hw_sequencer.h"
-+
-+#include "reg_helper.h"
-+
-+#include "dce/dce_10_0_d.h"
-+#include "dce/dce_10_0_sh_mask.h"
-+
-+#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
-+#include "gmc/gmc_8_2_d.h"
-+#include "gmc/gmc_8_2_sh_mask.h"
-+#endif
-+
-+#ifndef mmDP_DPHY_INTERNAL_CTRL
-+	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
-+	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
-+	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
-+	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
-+	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
-+	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
-+	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
-+	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
-+	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
-+	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
-+#endif
-+
-+#ifndef mmBIOS_SCRATCH_2
-+	#define mmBIOS_SCRATCH_2 0x05CB
-+	#define mmBIOS_SCRATCH_6 0x05CF
-+#endif
-+
-+#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
-+	#define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
-+	#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
-+	#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
-+	#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
-+	#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
-+	#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
-+	#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
-+	#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
-+#endif
-+
-+#ifndef mmDP_DPHY_FAST_TRAINING
-+	#define mmDP_DPHY_FAST_TRAINING                         0x4ABC
-+	#define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
-+	#define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
-+	#define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
-+	#define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
-+	#define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
-+	#define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
-+	#define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
-+#endif
-+
-+static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
-+	{
-+		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp =  (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
-+	}
-+};
-+
-+/* set register offset */
-+#define SR(reg_name)\
-+	.reg_name = mm ## reg_name
-+
-+/* set register offset with instance */
-+#define SRI(reg_name, block, id)\
-+	.reg_name = mm ## block ## id ## _ ## reg_name
-+
-+
-+static const struct dce_disp_clk_registers disp_clk_regs = {
-+		CLK_COMMON_REG_LIST_DCE_BASE()
-+};
-+
-+static const struct dce_disp_clk_shift disp_clk_shift = {
-+		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
-+};
-+
-+static const struct dce_disp_clk_mask disp_clk_mask = {
-+		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
-+};
-+
-+#define ipp_regs(id)\
-+[id] = {\
-+		IPP_DCE100_REG_LIST_DCE_BASE(id)\
-+}
-+
-+static const struct dce_ipp_registers ipp_regs[] = {
-+		ipp_regs(0),
-+		ipp_regs(1),
-+		ipp_regs(2),
-+		ipp_regs(3),
-+		ipp_regs(4),
-+		ipp_regs(5)
-+};
-+
-+static const struct dce_ipp_shift ipp_shift = {
-+		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
-+};
-+
-+static const struct dce_ipp_mask ipp_mask = {
-+		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
-+};
-+
-+#define transform_regs(id)\
-+[id] = {\
-+		XFM_COMMON_REG_LIST_DCE100(id)\
-+}
-+
-+static const struct dce_transform_registers xfm_regs[] = {
-+		transform_regs(0),
-+		transform_regs(1),
-+		transform_regs(2),
-+		transform_regs(3),
-+		transform_regs(4),
-+		transform_regs(5)
-+};
-+
-+static const struct dce_transform_shift xfm_shift = {
-+		XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-+};
-+
-+static const struct dce_transform_mask xfm_mask = {
-+		XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
-+};
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	AUX_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
-+		aux_regs(0),
-+		aux_regs(1),
-+		aux_regs(2),
-+		aux_regs(3),
-+		aux_regs(4),
-+		aux_regs(5)
-+};
-+
-+#define hpd_regs(id)\
-+[id] = {\
-+	HPD_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
-+		hpd_regs(0),
-+		hpd_regs(1),
-+		hpd_regs(2),
-+		hpd_regs(3),
-+		hpd_regs(4),
-+		hpd_regs(5)
-+};
-+
-+#define link_regs(id)\
-+[id] = {\
-+	LE_DCE100_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_registers link_enc_regs[] = {
-+	link_regs(0),
-+	link_regs(1),
-+	link_regs(2),
-+	link_regs(3),
-+	link_regs(4),
-+	link_regs(5),
-+	link_regs(6),
-+};
-+
-+#define stream_enc_regs(id)\
-+[id] = {\
-+	SE_COMMON_REG_LIST_DCE_BASE(id),\
-+	.AFMT_CNTL = 0,\
-+}
-+
-+static const struct dce110_stream_enc_registers stream_enc_regs[] = {
-+	stream_enc_regs(0),
-+	stream_enc_regs(1),
-+	stream_enc_regs(2),
-+	stream_enc_regs(3),
-+	stream_enc_regs(4),
-+	stream_enc_regs(5),
-+	stream_enc_regs(6)
-+};
-+
-+static const struct dce_stream_encoder_shift se_shift = {
-+		SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
-+};
-+
-+static const struct dce_stream_encoder_mask se_mask = {
-+		SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
-+};
-+
-+#define opp_regs(id)\
-+[id] = {\
-+	OPP_DCE_100_REG_LIST(id),\
-+}
-+
-+static const struct dce_opp_registers opp_regs[] = {
-+	opp_regs(0),
-+	opp_regs(1),
-+	opp_regs(2),
-+	opp_regs(3),
-+	opp_regs(4),
-+	opp_regs(5)
-+};
-+
-+static const struct dce_opp_shift opp_shift = {
-+	OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT)
-+};
-+
-+static const struct dce_opp_mask opp_mask = {
-+	OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)
-+};
-+
-+
-+#define audio_regs(id)\
-+[id] = {\
-+	AUD_COMMON_REG_LIST(id)\
-+}
-+
-+static const struct dce_audio_registers audio_regs[] = {
-+	audio_regs(0),
-+	audio_regs(1),
-+	audio_regs(2),
-+	audio_regs(3),
-+	audio_regs(4),
-+	audio_regs(5),
-+	audio_regs(6),
-+};
-+
-+static const struct dce_audio_shift audio_shift = {
-+		AUD_COMMON_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct dce_aduio_mask audio_mask = {
-+		AUD_COMMON_MASK_SH_LIST(_MASK)
-+};
-+
-+#define clk_src_regs(id)\
-+[id] = {\
-+	CS_COMMON_REG_LIST_DCE_100_110(id),\
-+}
-+
-+static const struct dce110_clk_src_regs clk_src_regs[] = {
-+	clk_src_regs(0),
-+	clk_src_regs(1),
-+	clk_src_regs(2)
-+};
-+
-+static const struct dce110_clk_src_shift cs_shift = {
-+		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
-+};
-+
-+static const struct dce110_clk_src_mask cs_mask = {
-+		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
-+};
-+
-+
-+
-+#define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
-+
-+static const struct bios_registers bios_regs = {
-+	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
-+};
-+
-+static const struct resource_caps res_cap = {
-+	.num_timing_generator = 6,
-+	.num_audio = 6,
-+	.num_stream_encoder = 6,
-+	.num_pll = 3
-+};
-+
-+#define CTX  ctx
-+#define REG(reg) mm ## reg
-+
-+#ifndef mmCC_DC_HDMI_STRAPS
-+#define mmCC_DC_HDMI_STRAPS 0x1918
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
-+#endif
-+
-+static void read_dce_straps(
-+	struct dc_context *ctx,
-+	struct resource_straps *straps)
-+{
-+	REG_GET_2(CC_DC_HDMI_STRAPS,
-+			HDMI_DISABLE, &straps->hdmi_disable,
-+			AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
-+
-+	REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
-+}
-+
-+static struct audio *create_audio(
-+		struct dc_context *ctx, unsigned int inst)
-+{
-+	return dce_audio_create(ctx, inst,
-+			&audio_regs[inst], &audio_shift, &audio_mask);
-+}
-+
-+static struct timing_generator *dce100_timing_generator_create(
-+		struct dc_context *ctx,
-+		uint32_t instance,
-+		const struct dce110_timing_generator_offsets *offsets)
-+{
-+	struct dce110_timing_generator *tg110 =
-+		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
-+
-+	if (!tg110)
-+		return NULL;
-+
-+	dce110_timing_generator_construct(tg110, ctx, instance, offsets);
-+	return &tg110->base;
-+}
-+
-+static struct stream_encoder *dce100_stream_encoder_create(
-+	enum engine_id eng_id,
-+	struct dc_context *ctx)
-+{
-+	struct dce110_stream_encoder *enc110 =
-+		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
-+					&stream_enc_regs[eng_id], &se_shift, &se_mask);
-+	return &enc110->base;
-+}
-+
-+#define SRII(reg_name, block, id)\
-+	.reg_name[id] = mm ## block ## id ## _ ## reg_name
-+
-+static const struct dce_hwseq_registers hwseq_reg = {
-+		HWSEQ_DCE10_REG_LIST()
-+};
-+
-+static const struct dce_hwseq_shift hwseq_shift = {
-+		HWSEQ_DCE10_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct dce_hwseq_mask hwseq_mask = {
-+		HWSEQ_DCE10_MASK_SH_LIST(_MASK)
-+};
-+
-+static struct dce_hwseq *dce100_hwseq_create(
-+	struct dc_context *ctx)
-+{
-+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
-+
-+	if (hws) {
-+		hws->ctx = ctx;
-+		hws->regs = &hwseq_reg;
-+		hws->shifts = &hwseq_shift;
-+		hws->masks = &hwseq_mask;
-+	}
-+	return hws;
-+}
-+
-+static const struct resource_create_funcs res_create_funcs = {
-+	.read_dce_straps = read_dce_straps,
-+	.create_audio = create_audio,
-+	.create_stream_encoder = dce100_stream_encoder_create,
-+	.create_hwseq = dce100_hwseq_create,
-+};
-+
-+#define mi_inst_regs(id) { \
-+	MI_DCE8_REG_LIST(id), \
-+	.MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
-+}
-+static const struct dce_mem_input_registers mi_regs[] = {
-+		mi_inst_regs(0),
-+		mi_inst_regs(1),
-+		mi_inst_regs(2),
-+		mi_inst_regs(3),
-+		mi_inst_regs(4),
-+		mi_inst_regs(5),
-+};
-+
-+static const struct dce_mem_input_shift mi_shifts = {
-+		MI_DCE8_MASK_SH_LIST(__SHIFT),
-+		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
-+};
-+
-+static const struct dce_mem_input_mask mi_masks = {
-+		MI_DCE8_MASK_SH_LIST(_MASK),
-+		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
-+};
-+
-+static struct mem_input *dce100_mem_input_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
-+					       GFP_KERNEL);
-+
-+	if (!dce_mi) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
-+	dce_mi->wa.single_head_rdreq_dmif_limit = 2;
-+	return &dce_mi->base;
-+}
-+
-+static void dce100_transform_destroy(struct transform **xfm)
-+{
-+	kfree(TO_DCE_TRANSFORM(*xfm));
-+	*xfm = NULL;
-+}
-+
-+static struct transform *dce100_transform_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce_transform *transform =
-+		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
-+
-+	if (!transform)
-+		return NULL;
-+
-+	dce_transform_construct(transform, ctx, inst,
-+				&xfm_regs[inst], &xfm_shift, &xfm_mask);
-+	return &transform->base;
-+}
-+
-+static struct input_pixel_processor *dce100_ipp_create(
-+	struct dc_context *ctx, uint32_t inst)
-+{
-+	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
-+
-+	if (!ipp) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dce_ipp_construct(ipp, ctx, inst,
-+			&ipp_regs[inst], &ipp_shift, &ipp_mask);
-+	return &ipp->base;
-+}
-+
-+static const struct encoder_feature_support link_enc_feature = {
-+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
-+		.max_hdmi_pixel_clock = 300000,
-+		.flags.bits.IS_HBR2_CAPABLE = true,
-+		.flags.bits.IS_TPS3_CAPABLE = true,
-+		.flags.bits.IS_YCBCR_CAPABLE = true
-+};
-+
-+struct link_encoder *dce100_link_encoder_create(
-+	const struct encoder_init_data *enc_init_data)
-+{
-+	struct dce110_link_encoder *enc110 =
-+		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	dce110_link_encoder_construct(enc110,
-+				      enc_init_data,
-+				      &link_enc_feature,
-+				      &link_enc_regs[enc_init_data->transmitter],
-+				      &link_enc_aux_regs[enc_init_data->channel - 1],
-+				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
-+	return &enc110->base;
-+}
-+
-+struct output_pixel_processor *dce100_opp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce110_opp *opp =
-+		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
-+
-+	if (!opp)
-+		return NULL;
-+
-+	dce110_opp_construct(opp,
-+			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
-+	return &opp->base;
-+}
-+
-+struct clock_source *dce100_clock_source_create(
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id id,
-+	const struct dce110_clk_src_regs *regs,
-+	bool dp_clk_src)
-+{
-+	struct dce110_clk_src *clk_src =
-+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
-+
-+	if (!clk_src)
-+		return NULL;
-+
-+	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
-+			regs, &cs_shift, &cs_mask)) {
-+		clk_src->base.dp_clk_src = dp_clk_src;
-+		return &clk_src->base;
-+	}
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
-+void dce100_clock_source_destroy(struct clock_source **clk_src)
-+{
-+	kfree(TO_DCE110_CLK_SRC(*clk_src));
-+	*clk_src = NULL;
-+}
-+
-+static void destruct(struct dce110_resource_pool *pool)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < pool->base.pipe_count; i++) {
-+		if (pool->base.opps[i] != NULL)
-+			dce110_opp_destroy(&pool->base.opps[i]);
-+
-+		if (pool->base.transforms[i] != NULL)
-+			dce100_transform_destroy(&pool->base.transforms[i]);
-+
-+		if (pool->base.ipps[i] != NULL)
-+			dce_ipp_destroy(&pool->base.ipps[i]);
-+
-+		if (pool->base.mis[i] != NULL) {
-+			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
-+			pool->base.mis[i] = NULL;
-+		}
-+
-+		if (pool->base.timing_generators[i] != NULL)	{
-+			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
-+			pool->base.timing_generators[i] = NULL;
-+		}
-+	}
-+
-+	for (i = 0; i < pool->base.stream_enc_count; i++) {
-+		if (pool->base.stream_enc[i] != NULL)
-+			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
-+	}
-+
-+	for (i = 0; i < pool->base.clk_src_count; i++) {
-+		if (pool->base.clock_sources[i] != NULL)
-+			dce100_clock_source_destroy(&pool->base.clock_sources[i]);
-+	}
-+
-+	if (pool->base.dp_clock_source != NULL)
-+		dce100_clock_source_destroy(&pool->base.dp_clock_source);
-+
-+	for (i = 0; i < pool->base.audio_count; i++)	{
-+		if (pool->base.audios[i] != NULL)
-+			dce_aud_destroy(&pool->base.audios[i]);
-+	}
-+
-+	if (pool->base.display_clock != NULL)
-+		dce_disp_clk_destroy(&pool->base.display_clock);
-+
-+	if (pool->base.irqs != NULL)
-+		dal_irq_service_destroy(&pool->base.irqs);
-+}
-+
-+static enum dc_status build_mapped_resource(
-+		const struct dc  *dc,
-+		struct dc_state *context,
-+		struct dc_stream_state *stream)
-+{
-+	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
-+
-+	if (!pipe_ctx)
-+		return DC_ERROR_UNEXPECTED;
-+
-+	dce110_resource_build_pipe_hw_param(pipe_ctx);
-+
-+	resource_build_info_frame(pipe_ctx);
-+
-+	return DC_OK;
-+}
-+
-+bool dce100_validate_bandwidth(
-+	struct dc  *dc,
-+	struct dc_state *context)
-+{
-+	/* TODO implement when needed but for now hardcode max value*/
-+	context->bw.dce.dispclk_khz = 681000;
-+	context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
-+
-+	return true;
-+}
-+
-+static bool dce100_validate_surface_sets(
-+		struct dc_state *context)
-+{
-+	int i;
-+
-+	for (i = 0; i < context->stream_count; i++) {
-+		if (context->stream_status[i].plane_count == 0)
-+			continue;
-+
-+		if (context->stream_status[i].plane_count > 1)
-+			return false;
-+
-+		if (context->stream_status[i].plane_states[0]->format
-+				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
-+			return false;
-+	}
-+
-+	return true;
-+}
-+
-+enum dc_status dce100_validate_global(
-+		struct dc  *dc,
-+		struct dc_state *context)
-+{
-+	if (!dce100_validate_surface_sets(context))
-+		return DC_FAIL_SURFACE_VALIDATE;
-+
-+	return DC_OK;
-+}
-+
-+enum dc_status dce100_add_stream_to_ctx(
-+		struct dc *dc,
-+		struct dc_state *new_ctx,
-+		struct dc_stream_state *dc_stream)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+
-+	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
-+
-+	if (result == DC_OK)
-+		result = resource_map_clock_resources(dc, new_ctx, dc_stream);
-+
-+	if (result == DC_OK)
-+		result = build_mapped_resource(dc, new_ctx, dc_stream);
-+
-+	return result;
-+}
-+
-+enum dc_status dce100_validate_guaranteed(
-+		struct dc  *dc,
-+		struct dc_stream_state *dc_stream,
-+		struct dc_state *context)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+
-+	context->streams[0] = dc_stream;
-+	dc_stream_retain(context->streams[0]);
-+	context->stream_count++;
-+
-+	result = resource_map_pool_resources(dc, context, dc_stream);
-+
-+	if (result == DC_OK)
-+		result = resource_map_clock_resources(dc, context, dc_stream);
-+
-+	if (result == DC_OK)
-+		result = build_mapped_resource(dc, context, dc_stream);
-+
-+	if (result == DC_OK) {
-+		validate_guaranteed_copy_streams(
-+				context, dc->caps.max_streams);
-+		result = resource_build_scaling_params_for_context(dc, context);
-+	}
-+
-+	if (result == DC_OK)
-+		if (!dce100_validate_bandwidth(dc, context))
-+			result = DC_FAIL_BANDWIDTH_VALIDATE;
-+
-+	return result;
-+}
-+
-+static void dce100_destroy_resource_pool(struct resource_pool **pool)
-+{
-+	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
-+
-+	destruct(dce110_pool);
-+	kfree(dce110_pool);
-+	*pool = NULL;
-+}
-+
-+enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
-+{
-+
-+	if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
-+		return DC_OK;
-+
-+	return DC_FAIL_SURFACE_VALIDATE;
-+}
-+
-+static const struct resource_funcs dce100_res_pool_funcs = {
-+	.destroy = dce100_destroy_resource_pool,
-+	.link_enc_create = dce100_link_encoder_create,
-+	.validate_guaranteed = dce100_validate_guaranteed,
-+	.validate_bandwidth = dce100_validate_bandwidth,
-+	.validate_plane = dce100_validate_plane,
-+	.add_stream_to_ctx = dce100_add_stream_to_ctx,
-+	.validate_global = dce100_validate_global
-+};
-+
-+static bool construct(
-+	uint8_t num_virtual_links,
-+	struct dc  *dc,
-+	struct dce110_resource_pool *pool)
-+{
-+	unsigned int i;
-+	struct dc_context *ctx = dc->ctx;
-+	struct dc_firmware_info info;
-+	struct dc_bios *bp;
-+	struct dm_pp_static_clock_info static_clk_info = {0};
-+
-+	ctx->dc_bios->regs = &bios_regs;
-+
-+	pool->base.res_cap = &res_cap;
-+	pool->base.funcs = &dce100_res_pool_funcs;
-+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
-+
-+	bp = ctx->dc_bios;
-+
-+	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
-+		info.external_clock_source_frequency_for_dp != 0) {
-+		pool->base.dp_clock_source =
-+				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
-+
-+		pool->base.clock_sources[0] =
-+				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
-+		pool->base.clock_sources[1] =
-+				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
-+		pool->base.clock_sources[2] =
-+				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
-+		pool->base.clk_src_count = 3;
-+
-+	} else {
-+		pool->base.dp_clock_source =
-+				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
-+
-+		pool->base.clock_sources[0] =
-+				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
-+		pool->base.clock_sources[1] =
-+				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
-+		pool->base.clk_src_count = 2;
-+	}
-+
-+	if (pool->base.dp_clock_source == NULL) {
-+		dm_error("DC: failed to create dp clock source!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->base.clk_src_count; i++) {
-+		if (pool->base.clock_sources[i] == NULL) {
-+			dm_error("DC: failed to create clock sources!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto res_create_fail;
-+		}
-+	}
-+
-+	pool->base.display_clock = dce_disp_clk_create(ctx,
-+			&disp_clk_regs,
-+			&disp_clk_shift,
-+			&disp_clk_mask);
-+	if (pool->base.display_clock == NULL) {
-+		dm_error("DC: failed to create display clock!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+
-+	/* get static clock information for PPLIB or firmware, save
-+	 * max_clock_state
-+	 */
-+	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
-+		pool->base.display_clock->max_clks_state =
-+					static_clk_info.max_clocks_state;
-+	{
-+		struct irq_service_init_data init_data;
-+		init_data.ctx = dc->ctx;
-+		pool->base.irqs = dal_irq_service_dce110_create(&init_data);
-+		if (!pool->base.irqs)
-+			goto res_create_fail;
-+	}
-+
-+	/*************************************************
-+	*  Resource + asic cap harcoding                *
-+	*************************************************/
-+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
-+	pool->base.pipe_count = res_cap.num_timing_generator;
-+	dc->caps.max_downscale_ratio = 200;
-+	dc->caps.i2c_speed_in_khz = 40;
-+	dc->caps.max_cursor_size = 128;
-+
-+	for (i = 0; i < pool->base.pipe_count; i++) {
-+		pool->base.timing_generators[i] =
-+			dce100_timing_generator_create(
-+				ctx,
-+				i,
-+				&dce100_tg_offsets[i]);
-+		if (pool->base.timing_generators[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create tg!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.mis[i] = dce100_mem_input_create(ctx, i);
-+		if (pool->base.mis[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create memory input!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.ipps[i] = dce100_ipp_create(ctx, i);
-+		if (pool->base.ipps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create input pixel processor!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.transforms[i] = dce100_transform_create(ctx, i);
-+		if (pool->base.transforms[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create transform!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.opps[i] = dce100_opp_create(ctx, i);
-+		if (pool->base.opps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create output pixel processor!\n");
-+			goto res_create_fail;
-+		}
-+	}
-+
-+	dc->caps.max_planes =  pool->base.pipe_count;
-+
-+	if (!resource_construct(num_virtual_links, dc, &pool->base,
-+			&res_create_funcs))
-+		goto res_create_fail;
-+
-+	/* Create hardware sequencer */
-+	dce100_hw_sequencer_construct(dc);
-+	return true;
-+
-+res_create_fail:
-+	destruct(pool);
-+
-+	return false;
-+}
-+
-+struct resource_pool *dce100_create_resource_pool(
-+	uint8_t num_virtual_links,
-+	struct dc  *dc)
-+{
-+	struct dce110_resource_pool *pool =
-+		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
-+
-+	if (!pool)
-+		return NULL;
-+
-+	if (construct(num_virtual_links, dc, pool))
-+		return &pool->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h.0130~	2017-12-14 06:39:58.408903562 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h	2017-12-14 06:39:58.408903562 +0100
-@@ -0,0 +1,26 @@
-+/*
-+ * dce100_resource.h
-+ *
-+ *  Created on: 2016-01-20
-+ *      Author: qyang
-+ */
-+
-+#ifndef DCE100_RESOURCE_H_
-+#define DCE100_RESOURCE_H_
-+
-+struct dc;
-+struct resource_pool;
-+struct dc_validation_set;
-+
-+struct resource_pool *dce100_create_resource_pool(
-+	uint8_t num_virtual_links,
-+	struct dc *dc);
-+
-+enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps);
-+
-+enum dc_status dce100_add_stream_to_ctx(
-+		struct dc *dc,
-+		struct dc_state *new_ctx,
-+		struct dc_stream_state *dc_stream);
-+
-+#endif /* DCE100_RESOURCE_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce100/Makefile.0130~	2017-12-14 06:39:58.408903562 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce100/Makefile	2017-12-14 06:39:58.408903562 +0100
-@@ -0,0 +1,23 @@
-+#
-+# Makefile for the 'controller' sub-component of DAL.
-+# It provides the control and status of HW CRTC block.
-+
-+DCE100 = dce100_resource.o dce100_hw_sequencer.o
-+
-+AMD_DAL_DCE100 = $(addprefix $(AMDDALPATH)/dc/dce100/,$(DCE100))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_DCE100)
-+
-+
-+###############################################################################
-+# DCE 10x
-+###############################################################################
-+ifdef 0#CONFIG_DRM_AMD_DC_DCE11_0
-+TG_DCE100 = dce100_resource.o
-+
-+AMD_DAL_TG_DCE100 = $(addprefix \
-+	$(AMDDALPATH)/dc/dce100/,$(TG_DCE100))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_TG_DCE100)
-+endif
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c.0130~	2017-12-14 06:39:58.409903563 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c	2017-12-14 06:39:58.409903563 +0100
-@@ -0,0 +1,522 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "gmc/gmc_8_2_sh_mask.h"
-+#include "gmc/gmc_8_2_d.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "dce110_compressor.h"
-+
-+#define DCP_REG(reg)\
-+	(reg + cp110->offsets.dcp_offset)
-+#define DMIF_REG(reg)\
-+	(reg + cp110->offsets.dmif_offset)
-+
-+static const struct dce110_compressor_reg_offsets reg_offsets[] = {
-+{
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset =
-+		(mmDMIF_PG0_DPG_PIPE_DPM_CONTROL
-+			- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset =
-+		(mmDMIF_PG1_DPG_PIPE_DPM_CONTROL
-+			- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset =
-+		(mmDMIF_PG2_DPG_PIPE_DPM_CONTROL
-+			- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+}
-+};
-+
-+static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;
-+
-+enum fbc_idle_force {
-+	/* Bit 0 - Display registers updated */
-+	FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001,
-+
-+	/* Bit 2 - FBC_GRPH_COMP_EN register updated */
-+	FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002,
-+	/* Bit 3 - FBC_SRC_SEL register updated */
-+	FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004,
-+	/* Bit 4 - FBC_MIN_COMPRESSION register updated */
-+	FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008,
-+	/* Bit 5 - FBC_ALPHA_COMP_EN register updated */
-+	FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010,
-+	/* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
-+	FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020,
-+	/* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
-+	FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040,
-+
-+	/* Bit 24 - Memory write to region 0 defined by MC registers. */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000,
-+	/* Bit 25 - Memory write to region 1 defined by MC registers */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000,
-+	/* Bit 26 - Memory write to region 2 defined by MC registers */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000,
-+	/* Bit 27 - Memory write to region 3 defined by MC registers. */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000,
-+
-+	/* Bit 28 - Memory write from any client other than MCIF */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000,
-+	/* Bit 29 - CG statics screen signal is inactive */
-+	FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000,
-+};
-+
-+
-+static uint32_t align_to_chunks_number_per_line(uint32_t pixels)
-+{
-+	return 256 * ((pixels + 255) / 256);
-+}
-+
-+static void wait_for_fbc_state_changed(
-+	struct dce110_compressor *cp110,
-+	bool enabled)
-+{
-+	uint8_t counter = 0;
-+	uint32_t addr = mmFBC_STATUS;
-+	uint32_t value;
-+
-+	while (counter < 10) {
-+		value = dm_read_reg(cp110->base.ctx, addr);
-+		if (get_reg_field_value(
-+			value,
-+			FBC_STATUS,
-+			FBC_ENABLE_STATUS) == enabled)
-+			break;
-+		msleep(10);
-+		counter++;
-+	}
-+
-+	if (counter == 10) {
-+		dm_logger_write(
-+			cp110->base.ctx->logger, LOG_WARNING,
-+			"%s: wait counter exceeded, changes to HW not applied",
-+			__func__);
-+	} else {
-+		dm_logger_write(
-+			cp110->base.ctx->logger, LOG_SYNC,
-+			"FBC status changed to %d", enabled);
-+	}
-+
-+
-+}
-+
-+void dce110_compressor_power_up_fbc(struct compressor *compressor)
-+{
-+	uint32_t value;
-+	uint32_t addr;
-+
-+	addr = mmFBC_CNTL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+	set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
-+	set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
-+	if (compressor->options.bits.CLK_GATING_DISABLED == 1) {
-+		/* HW needs to do power measurement comparison. */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			FBC_CNTL,
-+			FBC_COMP_CLK_GATE_EN);
-+	}
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	addr = mmFBC_COMP_MODE;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	addr = mmFBC_COMP_CNTL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN);
-+	dm_write_reg(compressor->ctx, addr, value);
-+	/*FBC_MIN_COMPRESSION 0 ==> 2:1 */
-+	/*                    1 ==> 4:1 */
-+	/*                    2 ==> 8:1 */
-+	/*                  0xF ==> 1:1 */
-+	set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION);
-+	dm_write_reg(compressor->ctx, addr, value);
-+	compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;
-+
-+	value = 0;
-+	dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
-+
-+	value = 0xFFFFFF;
-+	dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
-+}
-+
-+void dce110_compressor_enable_fbc(
-+	struct compressor *compressor,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
-+
-+	if (compressor->options.bits.FBC_SUPPORT &&
-+		(!dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL))) {
-+
-+		uint32_t addr;
-+		uint32_t value, misc_value;
-+
-+
-+		addr = mmFBC_CNTL;
-+		value = dm_read_reg(compressor->ctx, addr);
-+		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		set_reg_field_value(
-+			value,
-+			params->inst,
-+			FBC_CNTL, FBC_SRC_SEL);
-+		dm_write_reg(compressor->ctx, addr, value);
-+
-+		/* Keep track of enum controller_id FBC is attached to */
-+		compressor->is_enabled = true;
-+		compressor->attached_inst = params->inst;
-+		cp110->offsets = reg_offsets[params->inst];
-+
-+		/* Toggle it as there is bug in HW */
-+		set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, addr, value);
-+
-+		/* FBC usage with scatter & gather for dce110 */
-+		misc_value = dm_read_reg(compressor->ctx, mmFBC_MISC);
-+
-+		set_reg_field_value(misc_value, 1,
-+				FBC_MISC, FBC_INVALIDATE_ON_ERROR);
-+		set_reg_field_value(misc_value, 1,
-+				FBC_MISC, FBC_DECOMPRESS_ERROR_CLEAR);
-+		set_reg_field_value(misc_value, 0x14,
-+				FBC_MISC, FBC_SLOW_REQ_INTERVAL);
-+
-+		dm_write_reg(compressor->ctx, mmFBC_MISC, misc_value);
-+
-+		/* Enable FBC */
-+		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, addr, value);
-+
-+		wait_for_fbc_state_changed(cp110, true);
-+	}
-+}
-+
-+void dce110_compressor_disable_fbc(struct compressor *compressor)
-+{
-+	struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
-+
-+	if (compressor->options.bits.FBC_SUPPORT &&
-+		dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
-+		uint32_t reg_data;
-+		/* Turn off compression */
-+		reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
-+		set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
-+
-+		/* Reset enum controller_id to undefined */
-+		compressor->attached_inst = 0;
-+		compressor->is_enabled = false;
-+
-+		wait_for_fbc_state_changed(cp110, false);
-+	}
-+}
-+
-+bool dce110_compressor_is_fbc_enabled_in_hw(
-+	struct compressor *compressor,
-+	uint32_t *inst)
-+{
-+	/* Check the hardware register */
-+	uint32_t value;
-+
-+	value = dm_read_reg(compressor->ctx, mmFBC_STATUS);
-+	if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
-+		if (inst != NULL)
-+			*inst = compressor->attached_inst;
-+		return true;
-+	}
-+
-+	value = dm_read_reg(compressor->ctx, mmFBC_MISC);
-+	if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {
-+		value = dm_read_reg(compressor->ctx, mmFBC_CNTL);
-+
-+		if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
-+			if (inst != NULL)
-+				*inst =
-+					compressor->attached_inst;
-+			return true;
-+		}
-+	}
-+	return false;
-+}
-+
-+
-+void dce110_compressor_program_compressed_surface_address_and_pitch(
-+	struct compressor *compressor,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
-+	uint32_t value = 0;
-+	uint32_t fbc_pitch = 0;
-+	uint32_t compressed_surf_address_low_part =
-+		compressor->compr_surface_address.addr.low_part;
-+
-+	/* Clear content first. */
-+	dm_write_reg(
-+		compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
-+		0);
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0);
-+
-+	/* Write address, HIGH has to be first. */
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
-+		compressor->compr_surface_address.addr.high_part);
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS),
-+		compressed_surf_address_low_part);
-+
-+	fbc_pitch = align_to_chunks_number_per_line(params->source_view_width);
-+
-+	if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
-+		fbc_pitch = fbc_pitch / 8;
-+	else
-+		dm_logger_write(
-+			compressor->ctx->logger, LOG_WARNING,
-+			"%s: Unexpected DCE11 compression ratio",
-+			__func__);
-+
-+	/* Clear content first. */
-+	dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);
-+
-+	/* Write FBC Pitch. */
-+	set_reg_field_value(
-+		value,
-+		fbc_pitch,
-+		GRPH_COMPRESS_PITCH,
-+		GRPH_COMPRESS_PITCH);
-+	dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);
-+
-+}
-+
-+void dce110_compressor_set_fbc_invalidation_triggers(
-+	struct compressor *compressor,
-+	uint32_t fbc_trigger)
-+{
-+	/* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19)
-+	 * for DCE 11 regions cannot be used - does not work with S/G
-+	 */
-+	uint32_t addr = mmFBC_CLIENT_REGION_MASK;
-+	uint32_t value = dm_read_reg(compressor->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		FBC_CLIENT_REGION_MASK,
-+		FBC_MEMORY_REGION_MASK);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Setup events when to clear all CSM entries (effectively marking
-+	 * current compressed data invalid)
-+	 * For DCE 11 CSM metadata 11111 means - "Not Compressed"
-+	 * Used as the initial value of the metadata sent to the compressor
-+	 * after invalidation, to indicate that the compressor should attempt
-+	 * to compress all chunks on the current pass.  Also used when the chunk
-+	 * is not successfully written to memory.
-+	 * When this CSM value is detected, FBC reads from the uncompressed
-+	 * buffer. Set events according to passed in value, these events are
-+	 * valid for DCE11:
-+	 *     - bit  0 - display register updated
-+	 *     - bit 28 - memory write from any client except from MCIF
-+	 *     - bit 29 - CG static screen signal is inactive
-+	 * In addition, DCE11.1 also needs to set new DCE11.1 specific events
-+	 * that are used to trigger invalidation on certain register changes,
-+	 * for example enabling of Alpha Compression may trigger invalidation of
-+	 * FBC once bit is set. These events are as follows:
-+	 *      - Bit 2 - FBC_GRPH_COMP_EN register updated
-+	 *      - Bit 3 - FBC_SRC_SEL register updated
-+	 *      - Bit 4 - FBC_MIN_COMPRESSION register updated
-+	 *      - Bit 5 - FBC_ALPHA_COMP_EN register updated
-+	 *      - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated
-+	 *      - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated
-+	 */
-+	addr = mmFBC_IDLE_FORCE_CLEAR_MASK;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		fbc_trigger |
-+		FBC_IDLE_FORCE_GRPH_COMP_EN |
-+		FBC_IDLE_FORCE_SRC_SEL_CHANGE |
-+		FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE |
-+		FBC_IDLE_FORCE_ALPHA_COMP_EN |
-+		FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN |
-+		FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF,
-+		FBC_IDLE_FORCE_CLEAR_MASK,
-+		FBC_IDLE_FORCE_CLEAR_MASK);
-+	dm_write_reg(compressor->ctx, addr, value);
-+}
-+
-+struct compressor *dce110_compressor_create(struct dc_context *ctx)
-+{
-+	struct dce110_compressor *cp110 =
-+		kzalloc(sizeof(struct dce110_compressor), GFP_KERNEL);
-+
-+	if (!cp110)
-+		return NULL;
-+
-+	dce110_compressor_construct(cp110, ctx);
-+	return &cp110->base;
-+}
-+
-+void dce110_compressor_destroy(struct compressor **compressor)
-+{
-+	kfree(TO_DCE110_COMPRESSOR(*compressor));
-+	*compressor = NULL;
-+}
-+
-+bool dce110_get_required_compressed_surfacesize(struct fbc_input_info fbc_input_info,
-+						struct fbc_requested_compressed_size size)
-+{
-+	bool result = false;
-+
-+	unsigned int max_x = FBC_MAX_X, max_y = FBC_MAX_Y;
-+
-+	get_max_support_fbc_buffersize(&max_x, &max_y);
-+
-+	if (fbc_input_info.dynamic_fbc_buffer_alloc == 0) {
-+		/*
-+		 * For DCE11 here use Max HW supported size:  HW Support up to 3840x2400 resolution
-+		 * or 18000 chunks.
-+		 */
-+		size.preferred_size = size.min_size = align_to_chunks_number_per_line(max_x) * max_y * 4;  /* (For FBC when LPT not supported). */
-+		size.preferred_size_alignment = size.min_size_alignment = 0x100;       /* For FBC when LPT not supported */
-+		size.bits.preferred_must_be_framebuffer_pool = 1;
-+		size.bits.min_must_be_framebuffer_pool = 1;
-+
-+		result = true;
-+	}
-+	/*
-+	 * Maybe to add registry key support with optional size here to override above
-+	 * for debugging purposes
-+	 */
-+
-+	return result;
-+}
-+
-+
-+void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y)
-+{
-+	*max_x = FBC_MAX_X;
-+	*max_y = FBC_MAX_Y;
-+
-+	/* if (m_smallLocalFrameBufferMemory == 1)
-+	 * {
-+	 *	*max_x = FBC_MAX_X_SG;
-+	 *	*max_y = FBC_MAX_Y_SG;
-+	 * }
-+	 */
-+}
-+
-+
-+unsigned int controller_id_to_index(enum controller_id controller_id)
-+{
-+	unsigned int index = 0;
-+
-+	switch (controller_id) {
-+	case CONTROLLER_ID_D0:
-+		index = 0;
-+		break;
-+	case CONTROLLER_ID_D1:
-+		index = 1;
-+		break;
-+	case CONTROLLER_ID_D2:
-+		index = 2;
-+		break;
-+	case CONTROLLER_ID_D3:
-+		index = 3;
-+		break;
-+	default:
-+		break;
-+	}
-+	return index;
-+}
-+
-+
-+static const struct compressor_funcs dce110_compressor_funcs = {
-+	.power_up_fbc = dce110_compressor_power_up_fbc,
-+	.enable_fbc = dce110_compressor_enable_fbc,
-+	.disable_fbc = dce110_compressor_disable_fbc,
-+	.set_fbc_invalidation_triggers = dce110_compressor_set_fbc_invalidation_triggers,
-+	.surface_address_and_pitch = dce110_compressor_program_compressed_surface_address_and_pitch,
-+	.is_fbc_enabled_in_hw = dce110_compressor_is_fbc_enabled_in_hw
-+};
-+
-+
-+void dce110_compressor_construct(struct dce110_compressor *compressor,
-+	struct dc_context *ctx)
-+{
-+
-+	compressor->base.options.raw = 0;
-+	compressor->base.options.bits.FBC_SUPPORT = true;
-+
-+	/* for dce 11 always use one dram channel for lpt */
-+	compressor->base.lpt_channels_num = 1;
-+	compressor->base.options.bits.DUMMY_BACKEND = false;
-+
-+	/*
-+	 * check if this system has more than 1 dram channel; if only 1 then lpt
-+	 * should not be supported
-+	 */
-+
-+
-+	compressor->base.options.bits.CLK_GATING_DISABLED = false;
-+
-+	compressor->base.ctx = ctx;
-+	compressor->base.embedded_panel_h_size = 0;
-+	compressor->base.embedded_panel_v_size = 0;
-+	compressor->base.memory_bus_width = ctx->asic_id.vram_width;
-+	compressor->base.allocated_size = 0;
-+	compressor->base.preferred_requested_size = 0;
-+	compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
-+	compressor->base.banks_num = 0;
-+	compressor->base.raw_size = 0;
-+	compressor->base.channel_interleave_size = 0;
-+	compressor->base.dram_channels_num = 0;
-+	compressor->base.lpt_channels_num = 0;
-+	compressor->base.attached_inst = 0;
-+	compressor->base.is_enabled = false;
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+	compressor->base.funcs = &dce110_compressor_funcs;
-+
-+#endif
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h.0130~	2017-12-14 06:39:58.409903563 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h	2017-12-14 06:39:58.409903563 +0100
-@@ -0,0 +1,81 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_COMPRESSOR_DCE110_H__
-+#define __DC_COMPRESSOR_DCE110_H__
-+
-+#include "../inc/compressor.h"
-+
-+#define TO_DCE110_COMPRESSOR(compressor)\
-+	container_of(compressor, struct dce110_compressor, base)
-+
-+struct dce110_compressor_reg_offsets {
-+	uint32_t dcp_offset;
-+	uint32_t dmif_offset;
-+};
-+
-+struct dce110_compressor {
-+	struct compressor base;
-+	struct dce110_compressor_reg_offsets offsets;
-+};
-+
-+struct compressor *dce110_compressor_create(struct dc_context *ctx);
-+
-+void dce110_compressor_construct(struct dce110_compressor *cp110,
-+	struct dc_context *ctx);
-+
-+void dce110_compressor_destroy(struct compressor **cp);
-+
-+/* FBC RELATED */
-+void dce110_compressor_power_up_fbc(struct compressor *cp);
-+
-+void dce110_compressor_enable_fbc(struct compressor *cp,
-+	struct compr_addr_and_pitch_params *params);
-+
-+void dce110_compressor_disable_fbc(struct compressor *cp);
-+
-+void dce110_compressor_set_fbc_invalidation_triggers(struct compressor *cp,
-+	uint32_t fbc_trigger);
-+
-+void dce110_compressor_program_compressed_surface_address_and_pitch(
-+	struct compressor *cp,
-+	struct compr_addr_and_pitch_params *params);
-+
-+bool dce110_compressor_is_fbc_enabled_in_hw(struct compressor *cp,
-+	uint32_t *fbc_mapped_crtc_id);
-+
-+/* LPT RELATED */
-+void dce110_compressor_enable_lpt(struct compressor *cp);
-+
-+void dce110_compressor_disable_lpt(struct compressor *cp);
-+
-+void dce110_compressor_program_lpt_control(struct compressor *cp,
-+	struct compr_addr_and_pitch_params *params);
-+
-+bool dce110_compressor_is_lpt_enabled_in_hw(struct compressor *cp);
-+
-+void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y);
-+
-+#endif
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c.0130~	2017-12-14 06:39:58.409903563 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c	2017-12-14 06:39:58.409903563 +0100
-@@ -0,0 +1,2989 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dm_services.h"
-+#include "dc.h"
-+#include "dc_bios_types.h"
-+#include "core_types.h"
-+#include "core_status.h"
-+#include "resource.h"
-+#include "dm_helpers.h"
-+#include "dce110_hw_sequencer.h"
-+#include "dce110_timing_generator.h"
-+#include "dce/dce_hwseq.h"
-+#include "gpio_service_interface.h"
-+
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+#include "dce110_compressor.h"
-+#endif
-+
-+#include "bios/bios_parser_helper.h"
-+#include "timing_generator.h"
-+#include "mem_input.h"
-+#include "opp.h"
-+#include "ipp.h"
-+#include "transform.h"
-+#include "stream_encoder.h"
-+#include "link_encoder.h"
-+#include "link_hwss.h"
-+#include "clock_source.h"
-+#include "abm.h"
-+#include "audio.h"
-+#include "reg_helper.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "custom_float.h"
-+
-+/*
-+ * All values are in milliseconds;
-+ * For eDP, after power-up/power/down,
-+ * 300/500 msec max. delay from LCDVCC to black video generation
-+ */
-+#define PANEL_POWER_UP_TIMEOUT 300
-+#define PANEL_POWER_DOWN_TIMEOUT 500
-+#define HPD_CHECK_INTERVAL 10
-+
-+#define CTX \
-+	hws->ctx
-+#define REG(reg)\
-+	hws->regs->reg
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	hws->shifts->field_name, hws->masks->field_name
-+
-+struct dce110_hw_seq_reg_offsets {
-+	uint32_t crtc;
-+};
-+
-+static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
-+{
-+	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+}
-+};
-+
-+#define HW_REG_BLND(reg, id)\
-+	(reg + reg_offsets[id].blnd)
-+
-+#define HW_REG_CRTC(reg, id)\
-+	(reg + reg_offsets[id].crtc)
-+
-+#define MAX_WATERMARK 0xFFFF
-+#define SAFE_NBP_MARK 0x7FFF
-+
-+/*******************************************************************************
-+ * Private definitions
-+ ******************************************************************************/
-+/***************************PIPE_CONTROL***********************************/
-+static void dce110_init_pte(struct dc_context *ctx)
-+{
-+	uint32_t addr;
-+	uint32_t value = 0;
-+	uint32_t chunk_int = 0;
-+	uint32_t chunk_mul = 0;
-+
-+	addr = mmUNP_DVMM_PTE_CONTROL;
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DVMM_PTE_CONTROL,
-+		DVMM_USE_SINGLE_PTE);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DVMM_PTE_CONTROL,
-+		DVMM_PTE_BUFFER_MODE0);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DVMM_PTE_CONTROL,
-+		DVMM_PTE_BUFFER_MODE1);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmDVMM_PTE_REQ;
-+	value = dm_read_reg(ctx, addr);
-+
-+	chunk_int = get_reg_field_value(
-+		value,
-+		DVMM_PTE_REQ,
-+		HFLIP_PTEREQ_PER_CHUNK_INT);
-+
-+	chunk_mul = get_reg_field_value(
-+		value,
-+		DVMM_PTE_REQ,
-+		HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
-+
-+	if (chunk_int != 0x4 || chunk_mul != 0x4) {
-+
-+		set_reg_field_value(
-+			value,
-+			255,
-+			DVMM_PTE_REQ,
-+			MAX_PTEREQ_TO_ISSUE);
-+
-+		set_reg_field_value(
-+			value,
-+			4,
-+			DVMM_PTE_REQ,
-+			HFLIP_PTEREQ_PER_CHUNK_INT);
-+
-+		set_reg_field_value(
-+			value,
-+			4,
-+			DVMM_PTE_REQ,
-+			HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+}
-+/**************************************************************************/
-+
-+static void enable_display_pipe_clock_gating(
-+	struct dc_context *ctx,
-+	bool clock_gating)
-+{
-+	/*TODO*/
-+}
-+
-+static bool dce110_enable_display_power_gating(
-+	struct dc *dc,
-+	uint8_t controller_id,
-+	struct dc_bios *dcb,
-+	enum pipe_gating_control power_gating)
-+{
-+	enum bp_result bp_result = BP_RESULT_OK;
-+	enum bp_pipe_control_action cntl;
-+	struct dc_context *ctx = dc->ctx;
-+	unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
-+
-+	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
-+		return true;
-+
-+	if (power_gating == PIPE_GATING_CONTROL_INIT)
-+		cntl = ASIC_PIPE_INIT;
-+	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
-+		cntl = ASIC_PIPE_ENABLE;
-+	else
-+		cntl = ASIC_PIPE_DISABLE;
-+
-+	if (controller_id == underlay_idx)
-+		controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
-+
-+	if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
-+
-+		bp_result = dcb->funcs->enable_disp_power_gating(
-+						dcb, controller_id + 1, cntl);
-+
-+		/* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
-+		 * by default when command table is called
-+		 *
-+		 * Bios parser accepts controller_id = 6 as indicative of
-+		 * underlay pipe in dce110. But we do not support more
-+		 * than 3.
-+		 */
-+		if (controller_id < CONTROLLER_ID_MAX - 1)
-+			dm_write_reg(ctx,
-+				HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
-+				0);
-+	}
-+
-+	if (power_gating != PIPE_GATING_CONTROL_ENABLE)
-+		dce110_init_pte(ctx);
-+
-+	if (bp_result == BP_RESULT_OK)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+static void build_prescale_params(struct ipp_prescale_params *prescale_params,
-+		const struct dc_plane_state *plane_state)
-+{
-+	prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
-+
-+	switch (plane_state->format) {
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
-+		prescale_params->scale = 0x2020;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+		prescale_params->scale = 0x2008;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+		prescale_params->scale = 0x2000;
-+		break;
-+	default:
-+		ASSERT(false);
-+		break;
-+	}
-+}
-+
-+static bool
-+dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
-+			       const struct dc_plane_state *plane_state)
-+{
-+	struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
-+	const struct dc_transfer_func *tf = NULL;
-+	struct ipp_prescale_params prescale_params = { 0 };
-+	bool result = true;
-+
-+	if (ipp == NULL)
-+		return false;
-+
-+	if (plane_state->in_transfer_func)
-+		tf = plane_state->in_transfer_func;
-+
-+	build_prescale_params(&prescale_params, plane_state);
-+	ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
-+
-+	if (plane_state->gamma_correction && dce_use_lut(plane_state))
-+		ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
-+
-+	if (tf == NULL) {
-+		/* Default case if no input transfer function specified */
-+		ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
-+	} else if (tf->type == TF_TYPE_PREDEFINED) {
-+		switch (tf->tf) {
-+		case TRANSFER_FUNCTION_SRGB:
-+			ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
-+			break;
-+		case TRANSFER_FUNCTION_BT709:
-+			ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
-+			break;
-+		case TRANSFER_FUNCTION_LINEAR:
-+			ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
-+			break;
-+		case TRANSFER_FUNCTION_PQ:
-+		default:
-+			result = false;
-+			break;
-+		}
-+	} else if (tf->type == TF_TYPE_BYPASS) {
-+		ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
-+	} else {
-+		/*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
-+		result = false;
-+	}
-+
-+	return result;
-+}
-+
-+static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
-+				    struct curve_points *arr_points,
-+				    uint32_t hw_points_num)
-+{
-+	struct custom_float_format fmt;
-+
-+	struct pwl_result_data *rgb = rgb_resulted;
-+
-+	uint32_t i = 0;
-+
-+	fmt.exponenta_bits = 6;
-+	fmt.mantissa_bits = 12;
-+	fmt.sign = true;
-+
-+	if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
-+					    &arr_points[0].custom_float_x)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
-+					    &arr_points[0].custom_float_offset)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
-+					    &arr_points[0].custom_float_slope)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	fmt.mantissa_bits = 10;
-+	fmt.sign = false;
-+
-+	if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
-+					    &arr_points[1].custom_float_x)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
-+					    &arr_points[1].custom_float_y)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(arr_points[2].slope, &fmt,
-+					    &arr_points[2].custom_float_slope)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	fmt.mantissa_bits = 12;
-+	fmt.sign = true;
-+
-+	while (i != hw_points_num) {
-+		if (!convert_to_custom_float_format(rgb->red, &fmt,
-+						    &rgb->red_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(rgb->green, &fmt,
-+						    &rgb->green_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(rgb->blue, &fmt,
-+						    &rgb->blue_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
-+						    &rgb->delta_red_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
-+						    &rgb->delta_green_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
-+						    &rgb->delta_blue_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		++rgb;
-+		++i;
-+	}
-+
-+	return true;
-+}
-+
-+static bool
-+dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
-+				      struct pwl_params *regamma_params)
-+{
-+	struct curve_points *arr_points;
-+	struct pwl_result_data *rgb_resulted;
-+	struct pwl_result_data *rgb;
-+	struct pwl_result_data *rgb_plus_1;
-+	struct fixed31_32 y_r;
-+	struct fixed31_32 y_g;
-+	struct fixed31_32 y_b;
-+	struct fixed31_32 y1_min;
-+	struct fixed31_32 y3_max;
-+
-+	int32_t segment_start, segment_end;
-+	uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points;
-+
-+	if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
-+		return false;
-+
-+	arr_points = regamma_params->arr_points;
-+	rgb_resulted = regamma_params->rgb_resulted;
-+	hw_points = 0;
-+
-+	memset(regamma_params, 0, sizeof(struct pwl_params));
-+
-+	if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
-+		/* 16 segments
-+		 * segments are from 2^-11 to 2^5
-+		 */
-+		segment_start = -11;
-+		segment_end = 5;
-+
-+		seg_distr[0] = 2;
-+		seg_distr[1] = 2;
-+		seg_distr[2] = 2;
-+		seg_distr[3] = 2;
-+		seg_distr[4] = 2;
-+		seg_distr[5] = 2;
-+		seg_distr[6] = 3;
-+		seg_distr[7] = 4;
-+		seg_distr[8] = 4;
-+		seg_distr[9] = 4;
-+		seg_distr[10] = 4;
-+		seg_distr[11] = 5;
-+		seg_distr[12] = 5;
-+		seg_distr[13] = 5;
-+		seg_distr[14] = 5;
-+		seg_distr[15] = 5;
-+
-+	} else {
-+		/* 10 segments
-+		 * segment is from 2^-10 to 2^0
-+		 */
-+		segment_start = -10;
-+		segment_end = 0;
-+
-+		seg_distr[0] = 3;
-+		seg_distr[1] = 4;
-+		seg_distr[2] = 4;
-+		seg_distr[3] = 4;
-+		seg_distr[4] = 4;
-+		seg_distr[5] = 4;
-+		seg_distr[6] = 4;
-+		seg_distr[7] = 4;
-+		seg_distr[8] = 5;
-+		seg_distr[9] = 5;
-+		seg_distr[10] = -1;
-+		seg_distr[11] = -1;
-+		seg_distr[12] = -1;
-+		seg_distr[13] = -1;
-+		seg_distr[14] = -1;
-+		seg_distr[15] = -1;
-+	}
-+
-+	for (k = 0; k < 16; k++) {
-+		if (seg_distr[k] != -1)
-+			hw_points += (1 << seg_distr[k]);
-+	}
-+
-+	j = 0;
-+	for (k = 0; k < (segment_end - segment_start); k++) {
-+		increment = 32 / (1 << seg_distr[k]);
-+		start_index = (segment_start + k + 25) * 32;
-+		for (i = start_index; i < start_index + 32; i += increment) {
-+			if (j == hw_points - 1)
-+				break;
-+			rgb_resulted[j].red = output_tf->tf_pts.red[i];
-+			rgb_resulted[j].green = output_tf->tf_pts.green[i];
-+			rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
-+			j++;
-+		}
-+	}
-+
-+	/* last point */
-+	start_index = (segment_end + 25) * 32;
-+	rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
-+	rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
-+	rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
-+
-+	arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-+					     dal_fixed31_32_from_int(segment_start));
-+	arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-+					     dal_fixed31_32_from_int(segment_end));
-+
-+	y_r = rgb_resulted[0].red;
-+	y_g = rgb_resulted[0].green;
-+	y_b = rgb_resulted[0].blue;
-+
-+	y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
-+
-+	arr_points[0].y = y1_min;
-+	arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y,
-+						 arr_points[0].x);
-+
-+	y_r = rgb_resulted[hw_points - 1].red;
-+	y_g = rgb_resulted[hw_points - 1].green;
-+	y_b = rgb_resulted[hw_points - 1].blue;
-+
-+	/* see comment above, m_arrPoints[1].y should be the Y value for the
-+	 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
-+	 */
-+	y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
-+
-+	arr_points[1].y = y3_max;
-+
-+	arr_points[1].slope = dal_fixed31_32_zero;
-+
-+	if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
-+		/* for PQ, we want to have a straight line from last HW X point,
-+		 * and the slope to be such that we hit 1.0 at 10000 nits.
-+		 */
-+		const struct fixed31_32 end_value = dal_fixed31_32_from_int(125);
-+
-+		arr_points[1].slope = dal_fixed31_32_div(
-+				dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
-+				dal_fixed31_32_sub(end_value, arr_points[1].x));
-+	}
-+
-+	regamma_params->hw_points_num = hw_points;
-+
-+	i = 1;
-+	for (k = 0; k < 16 && i < 16; k++) {
-+		if (seg_distr[k] != -1) {
-+			regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
-+			regamma_params->arr_curve_points[i].offset =
-+					regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
-+		}
-+		i++;
-+	}
-+
-+	if (seg_distr[k] != -1)
-+		regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
-+
-+	rgb = rgb_resulted;
-+	rgb_plus_1 = rgb_resulted + 1;
-+
-+	i = 1;
-+
-+	while (i != hw_points + 1) {
-+		if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
-+			rgb_plus_1->red = rgb->red;
-+		if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
-+			rgb_plus_1->green = rgb->green;
-+		if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
-+			rgb_plus_1->blue = rgb->blue;
-+
-+		rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red);
-+		rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green);
-+		rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue);
-+
-+		++rgb_plus_1;
-+		++rgb;
-+		++i;
-+	}
-+
-+	convert_to_custom_float(rgb_resulted, arr_points, hw_points);
-+
-+	return true;
-+}
-+
-+static bool
-+dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
-+				const struct dc_stream_state *stream)
-+{
-+	struct transform *xfm = pipe_ctx->plane_res.xfm;
-+
-+	xfm->funcs->opp_power_on_regamma_lut(xfm, true);
-+	xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
-+
-+	if (stream->out_transfer_func &&
-+	    stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
-+	    stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
-+		xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
-+	} else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
-+							 &xfm->regamma_params)) {
-+		xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
-+		xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
-+	} else {
-+		xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
-+	}
-+
-+	xfm->funcs->opp_power_on_regamma_lut(xfm, false);
-+
-+	return true;
-+}
-+
-+static enum dc_status bios_parser_crtc_source_select(
-+		struct pipe_ctx *pipe_ctx)
-+{
-+	struct dc_bios *dcb;
-+	/* call VBIOS table to set CRTC source for the HW
-+	 * encoder block
-+	 * note: video bios clears all FMT setting here. */
-+	struct bp_crtc_source_select crtc_source_select = {0};
-+	const struct dc_sink *sink = pipe_ctx->stream->sink;
-+
-+	crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;
-+	crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1;
-+	/*TODO: Need to un-hardcode color depth, dp_audio and account for
-+	 * the case where signal and sink signal is different (translator
-+	 * encoder)*/
-+	crtc_source_select.signal = pipe_ctx->stream->signal;
-+	crtc_source_select.enable_dp_audio = false;
-+	crtc_source_select.sink_signal = pipe_ctx->stream->signal;
-+
-+	switch (pipe_ctx->stream->timing.display_color_depth) {
-+	case COLOR_DEPTH_666:
-+		crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR;
-+		break;
-+	case COLOR_DEPTH_888:
-+		crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
-+		break;
-+	case COLOR_DEPTH_101010:
-+		crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
-+		break;
-+	}
-+
-+	dcb = sink->ctx->dc_bios;
-+
-+	if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
-+		dcb,
-+		&crtc_source_select)) {
-+		return DC_ERROR_UNEXPECTED;
-+	}
-+
-+	return DC_OK;
-+}
-+
-+void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
-+{
-+	ASSERT(pipe_ctx->stream);
-+
-+	if (pipe_ctx->stream_res.stream_enc == NULL)
-+		return;  /* this is not root pipe */
-+
-+	if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
-+		pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
-+			pipe_ctx->stream_res.stream_enc,
-+			&pipe_ctx->stream_res.encoder_info_frame);
-+	else if (dc_is_dp_signal(pipe_ctx->stream->signal))
-+		pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
-+			pipe_ctx->stream_res.stream_enc,
-+			&pipe_ctx->stream_res.encoder_info_frame);
-+}
-+
-+void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
-+{
-+	enum dc_lane_count lane_count =
-+		pipe_ctx->stream->sink->link->cur_link_settings.lane_count;
-+
-+	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
-+	struct dc_link *link = pipe_ctx->stream->sink->link;
-+
-+	/* 1. update AVI info frame (HDMI, DP)
-+	 * we always need to update info frame
-+	*/
-+	uint32_t active_total_with_borders;
-+	uint32_t early_control = 0;
-+	struct timing_generator *tg = pipe_ctx->stream_res.tg;
-+
-+	/* TODOFPGA may change to hwss.update_info_frame */
-+	dce110_update_info_frame(pipe_ctx);
-+	/* enable early control to avoid corruption on DP monitor*/
-+	active_total_with_borders =
-+			timing->h_addressable
-+				+ timing->h_border_left
-+				+ timing->h_border_right;
-+
-+	if (lane_count != 0)
-+		early_control = active_total_with_borders % lane_count;
-+
-+	if (early_control == 0)
-+		early_control = lane_count;
-+
-+	tg->funcs->set_early_control(tg, early_control);
-+
-+	/* enable audio only within mode set */
-+	if (pipe_ctx->stream_res.audio != NULL) {
-+		if (dc_is_dp_signal(pipe_ctx->stream->signal))
-+			pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
-+	}
-+
-+	/* For MST, there are multiply stream go to only one link.
-+	 * connect DIG back_end to front_end while enable_stream and
-+	 * disconnect them during disable_stream
-+	 * BY this, it is logic clean to separate stream and link */
-+	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
-+						    pipe_ctx->stream_res.stream_enc->id, true);
-+
-+}
-+
-+/*todo: cloned in stream enc, fix*/
-+static bool is_panel_backlight_on(struct dce_hwseq *hws)
-+{
-+	uint32_t value;
-+
-+	REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
-+
-+	return value;
-+}
-+
-+static bool is_panel_powered_on(struct dce_hwseq *hws)
-+{
-+	uint32_t value;
-+
-+	REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &value);
-+	return value == 1;
-+}
-+
-+static enum bp_result link_transmitter_control(
-+		struct dc_bios *bios,
-+	struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result;
-+
-+	result = bios->funcs->transmitter_control(bios, cntl);
-+
-+	return result;
-+}
-+
-+/*
-+ * @brief
-+ * eDP only.
-+ */
-+void hwss_edp_wait_for_hpd_ready(
-+		struct dc_link *link,
-+		bool power_up)
-+{
-+	struct dc_context *ctx = link->ctx;
-+	struct graphics_object_id connector = link->link_enc->connector;
-+	struct gpio *hpd;
-+	bool edp_hpd_high = false;
-+	uint32_t time_elapsed = 0;
-+	uint32_t timeout = power_up ?
-+		PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
-+
-+	if (dal_graphics_object_id_get_connector_id(connector)
-+			!= CONNECTOR_ID_EDP) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	if (!power_up)
-+		/*
-+		 * From KV, we will not HPD low after turning off VCC -
-+		 * instead, we will check the SW timer in power_up().
-+		 */
-+		return;
-+
-+	/*
-+	 * When we power on/off the eDP panel,
-+	 * we need to wait until SENSE bit is high/low.
-+	 */
-+
-+	/* obtain HPD */
-+	/* TODO what to do with this? */
-+	hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
-+
-+	if (!hpd) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
-+
-+	/* wait until timeout or panel detected */
-+
-+	do {
-+		uint32_t detected = 0;
-+
-+		dal_gpio_get_value(hpd, &detected);
-+
-+		if (!(detected ^ power_up)) {
-+			edp_hpd_high = true;
-+			break;
-+		}
-+
-+		msleep(HPD_CHECK_INTERVAL);
-+
-+		time_elapsed += HPD_CHECK_INTERVAL;
-+	} while (time_elapsed < timeout);
-+
-+	dal_gpio_close(hpd);
-+
-+	dal_gpio_destroy_irq(&hpd);
-+
-+	if (false == edp_hpd_high) {
-+		dm_logger_write(ctx->logger, LOG_ERROR,
-+				"%s: wait timed out!\n", __func__);
-+	}
-+}
-+
-+void hwss_edp_power_control(
-+		struct dc_link *link,
-+		bool power_up)
-+{
-+	struct dc_context *ctx = link->ctx;
-+	struct dce_hwseq *hwseq = ctx->dc->hwseq;
-+	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result bp_result;
-+
-+
-+	if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
-+			!= CONNECTOR_ID_EDP) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	if (power_up != is_panel_powered_on(hwseq)) {
-+		/* Send VBIOS command to prompt eDP panel power */
-+
-+		dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
-+				"%s: Panel Power action: %s\n",
-+				__func__, (power_up ? "On":"Off"));
-+
-+		cntl.action = power_up ?
-+			TRANSMITTER_CONTROL_POWER_ON :
-+			TRANSMITTER_CONTROL_POWER_OFF;
-+		cntl.transmitter = link->link_enc->transmitter;
-+		cntl.connector_obj_id = link->link_enc->connector;
-+		cntl.coherent = false;
-+		cntl.lanes_number = LANE_COUNT_FOUR;
-+		cntl.hpd_sel = link->link_enc->hpd_source;
-+
-+		bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
-+
-+		if (bp_result != BP_RESULT_OK)
-+			dm_logger_write(ctx->logger, LOG_ERROR,
-+					"%s: Panel Power bp_result: %d\n",
-+					__func__, bp_result);
-+	} else {
-+		dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
-+				"%s: Skipping Panel Power action: %s\n",
-+				__func__, (power_up ? "On":"Off"));
-+	}
-+
-+	hwss_edp_wait_for_hpd_ready(link, true);
-+}
-+
-+/*todo: cloned in stream enc, fix*/
-+/*
-+ * @brief
-+ * eDP only. Control the backlight of the eDP panel
-+ */
-+void hwss_edp_backlight_control(
-+		struct dc_link *link,
-+		bool enable)
-+{
-+	struct dc_context *ctx = link->ctx;
-+	struct dce_hwseq *hws = ctx->dc->hwseq;
-+	struct bp_transmitter_control cntl = { 0 };
-+
-+	if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
-+		!= CONNECTOR_ID_EDP) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	if (enable && is_panel_backlight_on(hws)) {
-+		dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
-+				"%s: panel already powered up. Do nothing.\n",
-+				__func__);
-+		return;
-+	}
-+
-+	/* Send VBIOS command to control eDP panel backlight */
-+
-+	dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
-+			"%s: backlight action: %s\n",
-+			__func__, (enable ? "On":"Off"));
-+
-+	cntl.action = enable ?
-+		TRANSMITTER_CONTROL_BACKLIGHT_ON :
-+		TRANSMITTER_CONTROL_BACKLIGHT_OFF;
-+
-+	/*cntl.engine_id = ctx->engine;*/
-+	cntl.transmitter = link->link_enc->transmitter;
-+	cntl.connector_obj_id = link->link_enc->connector;
-+	/*todo: unhardcode*/
-+	cntl.lanes_number = LANE_COUNT_FOUR;
-+	cntl.hpd_sel = link->link_enc->hpd_source;
-+
-+	/* For eDP, the following delays might need to be considered
-+	 * after link training completed:
-+	 * idle period - min. accounts for required BS-Idle pattern,
-+	 * max. allows for source frame synchronization);
-+	 * 50 msec max. delay from valid video data from source
-+	 * to video on dislpay or backlight enable.
-+	 *
-+	 * Disable the delay for now.
-+	 * Enable it in the future if necessary.
-+	 */
-+	/* dc_service_sleep_in_milliseconds(50); */
-+	link_transmitter_control(ctx->dc_bios, &cntl);
-+}
-+
-+void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
-+{
-+	struct dc_stream_state *stream = pipe_ctx->stream;
-+	struct dc_link *link = stream->sink->link;
-+	struct dc *dc = pipe_ctx->stream->ctx->dc;
-+
-+	if (pipe_ctx->stream_res.audio) {
-+		pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
-+
-+		if (dc_is_dp_signal(pipe_ctx->stream->signal))
-+			pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
-+					pipe_ctx->stream_res.stream_enc);
-+		else
-+			pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
-+					pipe_ctx->stream_res.stream_enc);
-+		/*don't free audio if it is from retrain or internal disable stream*/
-+		if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
-+			/*we have to dynamic arbitrate the audio endpoints*/
-+			pipe_ctx->stream_res.audio = NULL;
-+			/*we free the resource, need reset is_audio_acquired*/
-+			update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
-+		}
-+
-+		/* TODO: notify audio driver for if audio modes list changed
-+		 * add audio mode list change flag */
-+		/* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
-+		 * stream->stream_engine_id);
-+		 */
-+	}
-+
-+	if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
-+		pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
-+			pipe_ctx->stream_res.stream_enc);
-+
-+	if (dc_is_dp_signal(pipe_ctx->stream->signal))
-+		pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
-+			pipe_ctx->stream_res.stream_enc);
-+
-+	pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
-+			pipe_ctx->stream_res.stream_enc, true);
-+
-+
-+	/* blank at encoder level */
-+	if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
-+		if (pipe_ctx->stream->sink->link->connector_signal == SIGNAL_TYPE_EDP)
-+			hwss_edp_backlight_control(link, false);
-+		pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
-+	}
-+	link->link_enc->funcs->connect_dig_be_to_fe(
-+			link->link_enc,
-+			pipe_ctx->stream_res.stream_enc->id,
-+			false);
-+
-+}
-+
-+void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
-+		struct dc_link_settings *link_settings)
-+{
-+	struct encoder_unblank_param params = { { 0 } };
-+	struct dc_link *link = pipe_ctx->stream->sink->link;
-+
-+	/* only 3 items below are used by unblank */
-+	params.pixel_clk_khz =
-+		pipe_ctx->stream->timing.pix_clk_khz;
-+	params.link_settings.link_rate = link_settings->link_rate;
-+	pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
-+	if (link->connector_signal == SIGNAL_TYPE_EDP)
-+		hwss_edp_backlight_control(link, true);
-+}
-+
-+
-+void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
-+{
-+	if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
-+		pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
-+}
-+
-+static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
-+{
-+	switch (crtc_id) {
-+	case CONTROLLER_ID_D0:
-+		return DTO_SOURCE_ID0;
-+	case CONTROLLER_ID_D1:
-+		return DTO_SOURCE_ID1;
-+	case CONTROLLER_ID_D2:
-+		return DTO_SOURCE_ID2;
-+	case CONTROLLER_ID_D3:
-+		return DTO_SOURCE_ID3;
-+	case CONTROLLER_ID_D4:
-+		return DTO_SOURCE_ID4;
-+	case CONTROLLER_ID_D5:
-+		return DTO_SOURCE_ID5;
-+	default:
-+		return DTO_SOURCE_UNKNOWN;
-+	}
-+}
-+
-+static void build_audio_output(
-+	struct dc_state *state,
-+	const struct pipe_ctx *pipe_ctx,
-+	struct audio_output *audio_output)
-+{
-+	const struct dc_stream_state *stream = pipe_ctx->stream;
-+	audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
-+
-+	audio_output->signal = pipe_ctx->stream->signal;
-+
-+	/* audio_crtc_info  */
-+
-+	audio_output->crtc_info.h_total =
-+		stream->timing.h_total;
-+
-+	/*
-+	 * Audio packets are sent during actual CRTC blank physical signal, we
-+	 * need to specify actual active signal portion
-+	 */
-+	audio_output->crtc_info.h_active =
-+			stream->timing.h_addressable
-+			+ stream->timing.h_border_left
-+			+ stream->timing.h_border_right;
-+
-+	audio_output->crtc_info.v_active =
-+			stream->timing.v_addressable
-+			+ stream->timing.v_border_top
-+			+ stream->timing.v_border_bottom;
-+
-+	audio_output->crtc_info.pixel_repetition = 1;
-+
-+	audio_output->crtc_info.interlaced =
-+			stream->timing.flags.INTERLACE;
-+
-+	audio_output->crtc_info.refresh_rate =
-+		(stream->timing.pix_clk_khz*1000)/
-+		(stream->timing.h_total*stream->timing.v_total);
-+
-+	audio_output->crtc_info.color_depth =
-+		stream->timing.display_color_depth;
-+
-+	audio_output->crtc_info.requested_pixel_clock =
-+			pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
-+
-+	audio_output->crtc_info.calculated_pixel_clock =
-+			pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
-+
-+/*for HDMI, audio ACR is with deep color ratio factor*/
-+	if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
-+		audio_output->crtc_info.requested_pixel_clock ==
-+				stream->timing.pix_clk_khz) {
-+		if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
-+			audio_output->crtc_info.requested_pixel_clock =
-+					audio_output->crtc_info.requested_pixel_clock/2;
-+			audio_output->crtc_info.calculated_pixel_clock =
-+					pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2;
-+
-+		}
-+	}
-+
-+	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+			pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
-+		audio_output->pll_info.dp_dto_source_clock_in_khz =
-+				state->dis_clk->funcs->get_dp_ref_clk_frequency(
-+						state->dis_clk);
-+	}
-+
-+	audio_output->pll_info.feed_back_divider =
-+			pipe_ctx->pll_settings.feedback_divider;
-+
-+	audio_output->pll_info.dto_source =
-+		translate_to_dto_source(
-+			pipe_ctx->pipe_idx + 1);
-+
-+	/* TODO hard code to enable for now. Need get from stream */
-+	audio_output->pll_info.ss_enabled = true;
-+
-+	audio_output->pll_info.ss_percentage =
-+			pipe_ctx->pll_settings.ss_percentage;
-+}
-+
-+static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
-+		struct tg_color *color)
-+{
-+	uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->pipe_idx) / 4;
-+
-+	switch (pipe_ctx->plane_res.scl_data.format) {
-+	case PIXEL_FORMAT_ARGB8888:
-+		/* set boarder color to red */
-+		color->color_r_cr = color_value;
-+		break;
-+
-+	case PIXEL_FORMAT_ARGB2101010:
-+		/* set boarder color to blue */
-+		color->color_b_cb = color_value;
-+		break;
-+	case PIXEL_FORMAT_420BPP8:
-+		/* set boarder color to green */
-+		color->color_g_y = color_value;
-+		break;
-+	case PIXEL_FORMAT_420BPP10:
-+		/* set boarder color to yellow */
-+		color->color_g_y = color_value;
-+		color->color_r_cr = color_value;
-+		break;
-+	case PIXEL_FORMAT_FP16:
-+		/* set boarder color to white */
-+		color->color_r_cr = color_value;
-+		color->color_b_cb = color_value;
-+		color->color_g_y = color_value;
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+static void program_scaler(const struct dc *dc,
-+		const struct pipe_ctx *pipe_ctx)
-+{
-+	struct tg_color color = {0};
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	/* TOFPGA */
-+	if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
-+		return;
-+#endif
-+
-+	if (dc->debug.surface_visual_confirm)
-+		get_surface_visual_confirm_color(pipe_ctx, &color);
-+	else
-+		color_space_to_black_color(dc,
-+				pipe_ctx->stream->output_color_space,
-+				&color);
-+
-+	pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
-+		pipe_ctx->plane_res.xfm,
-+		pipe_ctx->plane_res.scl_data.lb_params.depth,
-+		&pipe_ctx->stream->bit_depth_params);
-+
-+	if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color)
-+		pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
-+				pipe_ctx->stream_res.tg,
-+				&color);
-+
-+	pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
-+		&pipe_ctx->plane_res.scl_data);
-+}
-+
-+static enum dc_status dce110_prog_pixclk_crtc_otg(
-+		struct pipe_ctx *pipe_ctx,
-+		struct dc_state *context,
-+		struct dc *dc)
-+{
-+	struct dc_stream_state *stream = pipe_ctx->stream;
-+	struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
-+			pipe_ctx[pipe_ctx->pipe_idx];
-+	struct tg_color black_color = {0};
-+
-+	if (!pipe_ctx_old->stream) {
-+
-+		/* program blank color */
-+		color_space_to_black_color(dc,
-+				stream->output_color_space, &black_color);
-+		pipe_ctx->stream_res.tg->funcs->set_blank_color(
-+				pipe_ctx->stream_res.tg,
-+				&black_color);
-+
-+		/*
-+		 * Must blank CRTC after disabling power gating and before any
-+		 * programming, otherwise CRTC will be hung in bad state
-+		 */
-+		pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
-+
-+		if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
-+				pipe_ctx->clock_source,
-+				&pipe_ctx->stream_res.pix_clk_params,
-+				&pipe_ctx->pll_settings)) {
-+			BREAK_TO_DEBUGGER();
-+			return DC_ERROR_UNEXPECTED;
-+		}
-+
-+		pipe_ctx->stream_res.tg->funcs->program_timing(
-+				pipe_ctx->stream_res.tg,
-+				&stream->timing,
-+				true);
-+
-+		pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
-+				pipe_ctx->stream_res.tg,
-+				0x182);
-+	}
-+
-+	if (!pipe_ctx_old->stream) {
-+		if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
-+				pipe_ctx->stream_res.tg)) {
-+			BREAK_TO_DEBUGGER();
-+			return DC_ERROR_UNEXPECTED;
-+		}
-+	}
-+
-+
-+
-+	return DC_OK;
-+}
-+
-+static enum dc_status apply_single_controller_ctx_to_hw(
-+		struct pipe_ctx *pipe_ctx,
-+		struct dc_state *context,
-+		struct dc *dc)
-+{
-+	struct dc_stream_state *stream = pipe_ctx->stream;
-+	struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
-+			pipe_ctx[pipe_ctx->pipe_idx];
-+
-+	/*  */
-+	dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
-+
-+	/* FPGA does not program backend */
-+	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
-+		pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
-+		pipe_ctx->stream_res.opp,
-+		COLOR_SPACE_YCBCR601,
-+		stream->timing.display_color_depth,
-+		pipe_ctx->stream->signal);
-+
-+		pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
-+			pipe_ctx->stream_res.opp,
-+			&stream->bit_depth_params,
-+			&stream->clamping);
-+		return DC_OK;
-+	}
-+	/* TODO: move to stream encoder */
-+	if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
-+		if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
-+			BREAK_TO_DEBUGGER();
-+			return DC_ERROR_UNEXPECTED;
-+		}
-+	pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
-+			pipe_ctx->stream_res.opp,
-+			COLOR_SPACE_YCBCR601,
-+			stream->timing.display_color_depth,
-+			pipe_ctx->stream->signal);
-+
-+	if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
-+		stream->sink->link->link_enc->funcs->setup(
-+			stream->sink->link->link_enc,
-+			pipe_ctx->stream->signal);
-+
-+	if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
-+		pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
-+		pipe_ctx->stream_res.stream_enc,
-+		pipe_ctx->stream_res.tg->inst,
-+		stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
-+
-+
-+	pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
-+		pipe_ctx->stream_res.opp,
-+		&stream->bit_depth_params,
-+		&stream->clamping);
-+
-+	if (dc_is_dp_signal(pipe_ctx->stream->signal))
-+		pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
-+			pipe_ctx->stream_res.stream_enc,
-+			&stream->timing,
-+			stream->output_color_space);
-+
-+	if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
-+		pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
-+			pipe_ctx->stream_res.stream_enc,
-+			&stream->timing,
-+			stream->phy_pix_clk,
-+			pipe_ctx->stream_res.audio != NULL);
-+
-+	if (dc_is_dvi_signal(pipe_ctx->stream->signal))
-+		pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
-+			pipe_ctx->stream_res.stream_enc,
-+			&stream->timing,
-+			(pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
-+			true : false);
-+
-+	resource_build_info_frame(pipe_ctx);
-+	dce110_update_info_frame(pipe_ctx);
-+	if (!pipe_ctx_old->stream) {
-+		if (!pipe_ctx->stream->dpms_off)
-+			core_link_enable_stream(context, pipe_ctx);
-+	}
-+
-+	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
-+
-+	pipe_ctx->stream->sink->link->psr_enabled = false;
-+
-+	return DC_OK;
-+}
-+
-+/******************************************************************************/
-+
-+static void power_down_encoders(struct dc *dc)
-+{
-+	int i;
-+	enum connector_id connector_id;
-+	enum signal_type signal = SIGNAL_TYPE_NONE;
-+
-+	/* do not know BIOS back-front mapping, simply blank all. It will not
-+	 * hurt for non-DP
-+	 */
-+	for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
-+		dc->res_pool->stream_enc[i]->funcs->dp_blank(
-+					dc->res_pool->stream_enc[i]);
-+	}
-+
-+	for (i = 0; i < dc->link_count; i++) {
-+		connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
-+		if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
-+			(connector_id == CONNECTOR_ID_EDP)) {
-+
-+			if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
-+				dp_receiver_power_ctrl(dc->links[i], false);
-+			if (connector_id == CONNECTOR_ID_EDP) {
-+				signal = SIGNAL_TYPE_EDP;
-+				hwss_edp_backlight_control(dc->links[i], false);
-+			}
-+		}
-+
-+		dc->links[i]->link_enc->funcs->disable_output(
-+				dc->links[i]->link_enc, signal);
-+	}
-+}
-+
-+static void power_down_controllers(struct dc *dc)
-+{
-+	int i;
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		dc->res_pool->timing_generators[i]->funcs->disable_crtc(
-+				dc->res_pool->timing_generators[i]);
-+	}
-+}
-+
-+static void power_down_clock_sources(struct dc *dc)
-+{
-+	int i;
-+
-+	if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
-+		dc->res_pool->dp_clock_source) == false)
-+		dm_error("Failed to power down pll! (dp clk src)\n");
-+
-+	for (i = 0; i < dc->res_pool->clk_src_count; i++) {
-+		if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
-+				dc->res_pool->clock_sources[i]) == false)
-+			dm_error("Failed to power down pll! (clk src index=%d)\n", i);
-+	}
-+}
-+
-+static void power_down_all_hw_blocks(struct dc *dc)
-+{
-+	power_down_encoders(dc);
-+
-+	power_down_controllers(dc);
-+
-+	power_down_clock_sources(dc);
-+
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+	if (dc->fbc_compressor)
-+		dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
-+#endif
-+}
-+
-+static void disable_vga_and_power_gate_all_controllers(
-+		struct dc *dc)
-+{
-+	int i;
-+	struct timing_generator *tg;
-+	struct dc_context *ctx = dc->ctx;
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		tg = dc->res_pool->timing_generators[i];
-+
-+		if (tg->funcs->disable_vga)
-+			tg->funcs->disable_vga(tg);
-+
-+		/* Enable CLOCK gating for each pipe BEFORE controller
-+		 * powergating. */
-+		enable_display_pipe_clock_gating(ctx,
-+				true);
-+
-+		dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
-+		dc->hwss.disable_plane(dc,
-+			&dc->current_state->res_ctx.pipe_ctx[i]);
-+	}
-+}
-+
-+/**
-+ * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
-+ *  1. Power down all DC HW blocks
-+ *  2. Disable VGA engine on all controllers
-+ *  3. Enable power gating for controller
-+ *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
-+ */
-+void dce110_enable_accelerated_mode(struct dc *dc)
-+{
-+	power_down_all_hw_blocks(dc);
-+
-+	disable_vga_and_power_gate_all_controllers(dc);
-+	bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
-+}
-+
-+static uint32_t compute_pstate_blackout_duration(
-+	struct bw_fixed blackout_duration,
-+	const struct dc_stream_state *stream)
-+{
-+	uint32_t total_dest_line_time_ns;
-+	uint32_t pstate_blackout_duration_ns;
-+
-+	pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
-+
-+	total_dest_line_time_ns = 1000000UL *
-+		stream->timing.h_total /
-+		stream->timing.pix_clk_khz +
-+		pstate_blackout_duration_ns;
-+
-+	return total_dest_line_time_ns;
-+}
-+
-+void dce110_set_displaymarks(
-+	const struct dc *dc,
-+	struct dc_state *context)
-+{
-+	uint8_t i, num_pipes;
-+	unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
-+
-+	for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+		uint32_t total_dest_line_time_ns;
-+
-+		if (pipe_ctx->stream == NULL)
-+			continue;
-+
-+		total_dest_line_time_ns = compute_pstate_blackout_duration(
-+			dc->bw_vbios->blackout_duration, pipe_ctx->stream);
-+		pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
-+			pipe_ctx->plane_res.mi,
-+			context->bw.dce.nbp_state_change_wm_ns[num_pipes],
-+			context->bw.dce.stutter_exit_wm_ns[num_pipes],
-+			context->bw.dce.urgent_wm_ns[num_pipes],
-+			total_dest_line_time_ns);
-+		if (i == underlay_idx) {
-+			num_pipes++;
-+			pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
-+				pipe_ctx->plane_res.mi,
-+				context->bw.dce.nbp_state_change_wm_ns[num_pipes],
-+				context->bw.dce.stutter_exit_wm_ns[num_pipes],
-+				context->bw.dce.urgent_wm_ns[num_pipes],
-+				total_dest_line_time_ns);
-+		}
-+		num_pipes++;
-+	}
-+}
-+
-+static void set_safe_displaymarks(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool)
-+{
-+	int i;
-+	int underlay_idx = pool->underlay_pipe_index;
-+	struct dce_watermarks max_marks = {
-+		MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
-+	struct dce_watermarks nbp_marks = {
-+		SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
-+			continue;
-+
-+		res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
-+				res_ctx->pipe_ctx[i].plane_res.mi,
-+				nbp_marks,
-+				max_marks,
-+				max_marks,
-+				MAX_WATERMARK);
-+
-+		if (i == underlay_idx)
-+			res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
-+				res_ctx->pipe_ctx[i].plane_res.mi,
-+				nbp_marks,
-+				max_marks,
-+				max_marks,
-+				MAX_WATERMARK);
-+
-+	}
-+}
-+
-+/*******************************************************************************
-+ * Public functions
-+ ******************************************************************************/
-+
-+static void set_drr(struct pipe_ctx **pipe_ctx,
-+		int num_pipes, int vmin, int vmax)
-+{
-+	int i = 0;
-+	struct drr_params params = {0};
-+
-+	params.vertical_total_max = vmax;
-+	params.vertical_total_min = vmin;
-+
-+	/* TODO: If multiple pipes are to be supported, you need
-+	 * some GSL stuff
-+	 */
-+
-+	for (i = 0; i < num_pipes; i++) {
-+		pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
-+	}
-+}
-+
-+static void get_position(struct pipe_ctx **pipe_ctx,
-+		int num_pipes,
-+		struct crtc_position *position)
-+{
-+	int i = 0;
-+
-+	/* TODO: handle pipes > 1
-+	 */
-+	for (i = 0; i < num_pipes; i++)
-+		pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
-+}
-+
-+static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
-+		int num_pipes, const struct dc_static_screen_events *events)
-+{
-+	unsigned int i;
-+	unsigned int value = 0;
-+
-+	if (events->overlay_update)
-+		value |= 0x100;
-+	if (events->surface_update)
-+		value |= 0x80;
-+	if (events->cursor_update)
-+		value |= 0x2;
-+
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+	value |= 0x84;
-+#endif
-+
-+	for (i = 0; i < num_pipes; i++)
-+		pipe_ctx[i]->stream_res.tg->funcs->
-+			set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
-+}
-+
-+/* unit: in_khz before mode set, get pixel clock from context. ASIC register
-+ * may not be programmed yet.
-+ * TODO: after mode set, pre_mode_set = false,
-+ * may read PLL register to get pixel clock
-+ */
-+static uint32_t get_max_pixel_clock_for_all_paths(
-+	struct dc *dc,
-+	struct dc_state *context,
-+	bool pre_mode_set)
-+{
-+	uint32_t max_pix_clk = 0;
-+	int i;
-+
-+	if (!pre_mode_set) {
-+		/* TODO: read ASIC register to get pixel clock */
-+		ASSERT(0);
-+	}
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+		if (pipe_ctx->stream == NULL)
-+			continue;
-+
-+		/* do not check under lay */
-+		if (pipe_ctx->top_pipe)
-+			continue;
-+
-+		if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)
-+			max_pix_clk =
-+				pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
-+	}
-+
-+	if (max_pix_clk == 0)
-+		ASSERT(0);
-+
-+	return max_pix_clk;
-+}
-+
-+/*
-+ * Find clock state based on clock requested. if clock value is 0, simply
-+ * set clock state as requested without finding clock state by clock value
-+ */
-+
-+static void apply_min_clocks(
-+	struct dc *dc,
-+	struct dc_state *context,
-+	enum dm_pp_clocks_state *clocks_state,
-+	bool pre_mode_set)
-+{
-+	struct state_dependent_clocks req_clocks = {0};
-+
-+	if (!pre_mode_set) {
-+		/* set clock_state without verification */
-+		if (context->dis_clk->funcs->set_min_clocks_state) {
-+			context->dis_clk->funcs->set_min_clocks_state(
-+						context->dis_clk, *clocks_state);
-+			return;
-+		}
-+
-+		/* TODO: This is incorrect. Figure out how to fix. */
-+		context->dis_clk->funcs->apply_clock_voltage_request(
-+				context->dis_clk,
-+				DM_PP_CLOCK_TYPE_DISPLAY_CLK,
-+				context->dis_clk->cur_clocks_value.dispclk_in_khz,
-+				pre_mode_set,
-+				false);
-+
-+		context->dis_clk->funcs->apply_clock_voltage_request(
-+				context->dis_clk,
-+				DM_PP_CLOCK_TYPE_PIXELCLK,
-+				context->dis_clk->cur_clocks_value.max_pixelclk_in_khz,
-+				pre_mode_set,
-+				false);
-+
-+		context->dis_clk->funcs->apply_clock_voltage_request(
-+				context->dis_clk,
-+				DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
-+				context->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz,
-+				pre_mode_set,
-+				false);
-+		return;
-+	}
-+
-+	/* get the required state based on state dependent clocks:
-+	 * display clock and pixel clock
-+	 */
-+	req_clocks.display_clk_khz = context->bw.dce.dispclk_khz;
-+
-+	req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths(
-+			dc, context, true);
-+
-+	if (context->dis_clk->funcs->get_required_clocks_state) {
-+		*clocks_state = context->dis_clk->funcs->get_required_clocks_state(
-+				context->dis_clk, &req_clocks);
-+		context->dis_clk->funcs->set_min_clocks_state(
-+			context->dis_clk, *clocks_state);
-+	} else {
-+		context->dis_clk->funcs->apply_clock_voltage_request(
-+				context->dis_clk,
-+				DM_PP_CLOCK_TYPE_DISPLAY_CLK,
-+				req_clocks.display_clk_khz,
-+				pre_mode_set,
-+				false);
-+
-+		context->dis_clk->funcs->apply_clock_voltage_request(
-+				context->dis_clk,
-+				DM_PP_CLOCK_TYPE_PIXELCLK,
-+				req_clocks.pixel_clk_khz,
-+				pre_mode_set,
-+				false);
-+
-+		context->dis_clk->funcs->apply_clock_voltage_request(
-+				context->dis_clk,
-+				DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
-+				req_clocks.pixel_clk_khz,
-+				pre_mode_set,
-+				false);
-+	}
-+}
-+
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+
-+/*
-+ *  Check if FBC can be enabled
-+ */
-+static enum dc_status validate_fbc(struct dc *dc,
-+		struct dc_state *context)
-+{
-+	struct pipe_ctx *pipe_ctx =
-+			      &context->res_ctx.pipe_ctx[0];
-+
-+	ASSERT(dc->fbc_compressor);
-+
-+	/* FBC memory should be allocated */
-+	if (!dc->ctx->fbc_gpu_addr)
-+		return DC_ERROR_UNEXPECTED;
-+
-+	/* Only supports single display */
-+	if (context->stream_count != 1)
-+		return DC_ERROR_UNEXPECTED;
-+
-+	/* Only supports eDP */
-+	if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
-+		return DC_ERROR_UNEXPECTED;
-+
-+	/* PSR should not be enabled */
-+	if (pipe_ctx->stream->sink->link->psr_enabled)
-+		return DC_ERROR_UNEXPECTED;
-+
-+	/* Only for non-linear tiling */
-+	if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
-+		return DC_ERROR_UNEXPECTED;
-+
-+	return DC_OK;
-+}
-+
-+/*
-+ *  Enable FBC
-+ */
-+static enum dc_status enable_fbc(struct dc *dc,
-+		struct dc_state *context)
-+{
-+	enum dc_status status = validate_fbc(dc, context);
-+
-+	if (status == DC_OK) {
-+		/* Program GRPH COMPRESSED ADDRESS and PITCH */
-+		struct compr_addr_and_pitch_params params = {0, 0, 0};
-+		struct compressor *compr = dc->fbc_compressor;
-+		struct pipe_ctx *pipe_ctx =
-+				      &context->res_ctx.pipe_ctx[0];
-+
-+		params.source_view_width =
-+				pipe_ctx->stream->timing.h_addressable;
-+		params.source_view_height =
-+				pipe_ctx->stream->timing.v_addressable;
-+
-+		compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
-+
-+		compr->funcs->surface_address_and_pitch(compr, &params);
-+		compr->funcs->set_fbc_invalidation_triggers(compr, 1);
-+
-+		compr->funcs->enable_fbc(compr, &params);
-+	}
-+	return status;
-+}
-+#endif
-+
-+static enum dc_status apply_ctx_to_hw_fpga(
-+		struct dc *dc,
-+		struct dc_state *context)
-+{
-+	enum dc_status status = DC_ERROR_UNEXPECTED;
-+	int i;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx_old =
-+				&dc->current_state->res_ctx.pipe_ctx[i];
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+		if (pipe_ctx->stream == NULL)
-+			continue;
-+
-+		if (pipe_ctx->stream == pipe_ctx_old->stream)
-+			continue;
-+
-+		status = apply_single_controller_ctx_to_hw(
-+				pipe_ctx,
-+				context,
-+				dc);
-+
-+		if (status != DC_OK)
-+			return status;
-+	}
-+
-+	return DC_OK;
-+}
-+
-+static void dce110_reset_hw_ctx_wrap(
-+		struct dc *dc,
-+		struct dc_state *context)
-+{
-+	int i;
-+
-+	/* Reset old context */
-+	/* look up the targets that have been removed since last commit */
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		struct pipe_ctx *pipe_ctx_old =
-+			&dc->current_state->res_ctx.pipe_ctx[i];
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+		/* Note: We need to disable output if clock sources change,
-+		 * since bios does optimization and doesn't apply if changing
-+		 * PHY when not already disabled.
-+		 */
-+
-+		/* Skip underlay pipe since it will be handled in commit surface*/
-+		if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
-+			continue;
-+
-+		if (!pipe_ctx->stream ||
-+				pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
-+			struct clock_source *old_clk = pipe_ctx_old->clock_source;
-+
-+			/* Disable if new stream is null. O/w, if stream is
-+			 * disabled already, no need to disable again.
-+			 */
-+			if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
-+				core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
-+
-+			pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
-+			if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
-+				dm_error("DC: failed to blank crtc!\n");
-+				BREAK_TO_DEBUGGER();
-+			}
-+			pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
-+			pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
-+					pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
-+
-+			if (old_clk)
-+				old_clk->funcs->cs_power_down(old_clk);
-+
-+			dc->hwss.disable_plane(dc, pipe_ctx_old);
-+
-+			pipe_ctx_old->stream = NULL;
-+		}
-+	}
-+}
-+
-+
-+enum dc_status dce110_apply_ctx_to_hw(
-+		struct dc *dc,
-+		struct dc_state *context)
-+{
-+	struct dc_bios *dcb = dc->ctx->dc_bios;
-+	enum dc_status status;
-+	int i;
-+	enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID;
-+
-+	/* Reset old context */
-+	/* look up the targets that have been removed since last commit */
-+	dc->hwss.reset_hw_ctx_wrap(dc, context);
-+
-+	/* Skip applying if no targets */
-+	if (context->stream_count <= 0)
-+		return DC_OK;
-+
-+	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
-+		apply_ctx_to_hw_fpga(dc, context);
-+		return DC_OK;
-+	}
-+
-+	/* Apply new context */
-+	dcb->funcs->set_scratch_critical_state(dcb, true);
-+
-+	/* below is for real asic only */
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct pipe_ctx *pipe_ctx_old =
-+					&dc->current_state->res_ctx.pipe_ctx[i];
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+		if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
-+			continue;
-+
-+		if (pipe_ctx->stream == pipe_ctx_old->stream) {
-+			if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
-+				dce_crtc_switch_to_clk_src(dc->hwseq,
-+						pipe_ctx->clock_source, i);
-+			continue;
-+		}
-+
-+		dc->hwss.enable_display_power_gating(
-+				dc, i, dc->ctx->dc_bios,
-+				PIPE_GATING_CONTROL_DISABLE);
-+	}
-+
-+	set_safe_displaymarks(&context->res_ctx, dc->res_pool);
-+
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+	if (dc->fbc_compressor)
-+		dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
-+#endif
-+	/*TODO: when pplib works*/
-+	apply_min_clocks(dc, context, &clocks_state, true);
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
-+		if (context->bw.dcn.calc_clk.fclk_khz
-+				> dc->current_state->bw.dcn.cur_clk.fclk_khz) {
-+			struct dm_pp_clock_for_voltage_req clock;
-+
-+			clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
-+			clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
-+			dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
-+			dc->current_state->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
-+			context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
-+		}
-+		if (context->bw.dcn.calc_clk.dcfclk_khz
-+				> dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
-+			struct dm_pp_clock_for_voltage_req clock;
-+
-+			clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
-+			clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
-+			dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
-+			dc->current_state->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
-+			context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
-+		}
-+		if (context->bw.dcn.calc_clk.dispclk_khz
-+				> dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
-+			dc->res_pool->display_clock->funcs->set_clock(
-+					dc->res_pool->display_clock,
-+					context->bw.dcn.calc_clk.dispclk_khz);
-+			dc->current_state->bw.dcn.cur_clk.dispclk_khz =
-+					context->bw.dcn.calc_clk.dispclk_khz;
-+			context->bw.dcn.cur_clk.dispclk_khz =
-+					context->bw.dcn.calc_clk.dispclk_khz;
-+		}
-+	} else
-+#endif
-+	if (context->bw.dce.dispclk_khz
-+			> dc->current_state->bw.dce.dispclk_khz) {
-+		dc->res_pool->display_clock->funcs->set_clock(
-+				dc->res_pool->display_clock,
-+				context->bw.dce.dispclk_khz * 115 / 100);
-+	}
-+	/* program audio wall clock. use HDMI as clock source if HDMI
-+	 * audio active. Otherwise, use DP as clock source
-+	 * first, loop to find any HDMI audio, if not, loop find DP audio
-+	 */
-+	/* Setup audio rate clock source */
-+	/* Issue:
-+	* Audio lag happened on DP monitor when unplug a HDMI monitor
-+	*
-+	* Cause:
-+	* In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
-+	* is set to either dto0 or dto1, audio should work fine.
-+	* In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
-+	* set to dto0 will cause audio lag.
-+	*
-+	* Solution:
-+	* Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
-+	* find first available pipe with audio, setup audio wall DTO per topology
-+	* instead of per pipe.
-+	*/
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+		if (pipe_ctx->stream == NULL)
-+			continue;
-+
-+		if (pipe_ctx->top_pipe)
-+			continue;
-+
-+		if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
-+			continue;
-+
-+		if (pipe_ctx->stream_res.audio != NULL) {
-+			struct audio_output audio_output;
-+
-+			build_audio_output(context, pipe_ctx, &audio_output);
-+
-+			pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
-+				pipe_ctx->stream_res.audio,
-+				pipe_ctx->stream->signal,
-+				&audio_output.crtc_info,
-+				&audio_output.pll_info);
-+			break;
-+		}
-+	}
-+
-+	/* no HDMI audio is found, try DP audio */
-+	if (i == dc->res_pool->pipe_count) {
-+		for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+			if (pipe_ctx->stream == NULL)
-+				continue;
-+
-+			if (pipe_ctx->top_pipe)
-+				continue;
-+
-+			if (!dc_is_dp_signal(pipe_ctx->stream->signal))
-+				continue;
-+
-+			if (pipe_ctx->stream_res.audio != NULL) {
-+				struct audio_output audio_output;
-+
-+				build_audio_output(context, pipe_ctx, &audio_output);
-+
-+				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
-+					pipe_ctx->stream_res.audio,
-+					pipe_ctx->stream->signal,
-+					&audio_output.crtc_info,
-+					&audio_output.pll_info);
-+				break;
-+			}
-+		}
-+	}
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct pipe_ctx *pipe_ctx_old =
-+					&dc->current_state->res_ctx.pipe_ctx[i];
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+		if (pipe_ctx->stream == NULL)
-+			continue;
-+
-+		if (pipe_ctx->stream == pipe_ctx_old->stream)
-+			continue;
-+
-+		if (pipe_ctx->stream && pipe_ctx_old->stream
-+				&& !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
-+			continue;
-+
-+		if (pipe_ctx->top_pipe)
-+			continue;
-+
-+		if (context->res_ctx.pipe_ctx[i].stream_res.audio != NULL) {
-+
-+			struct audio_output audio_output;
-+
-+			build_audio_output(context, pipe_ctx, &audio_output);
-+
-+			if (dc_is_dp_signal(pipe_ctx->stream->signal))
-+				pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
-+						pipe_ctx->stream_res.stream_enc,
-+						pipe_ctx->stream_res.audio->inst,
-+						&pipe_ctx->stream->audio_info);
-+			else
-+				pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
-+						pipe_ctx->stream_res.stream_enc,
-+						pipe_ctx->stream_res.audio->inst,
-+						&pipe_ctx->stream->audio_info,
-+						&audio_output.crtc_info);
-+
-+			pipe_ctx->stream_res.audio->funcs->az_configure(
-+					pipe_ctx->stream_res.audio,
-+					pipe_ctx->stream->signal,
-+					&audio_output.crtc_info,
-+					&pipe_ctx->stream->audio_info);
-+		}
-+
-+		status = apply_single_controller_ctx_to_hw(
-+				pipe_ctx,
-+				context,
-+				dc);
-+
-+		if (dc->hwss.enable_plane)
-+			dc->hwss.enable_plane(dc, pipe_ctx, context);
-+
-+		if (DC_OK != status)
-+			return status;
-+	}
-+
-+	/* pplib is notified if disp_num changed */
-+	dc->hwss.set_bandwidth(dc, context, true);
-+
-+	/* to save power */
-+	apply_min_clocks(dc, context, &clocks_state, false);
-+
-+	dcb->funcs->set_scratch_critical_state(dcb, false);
-+
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+	if (dc->fbc_compressor)
-+		enable_fbc(dc, context);
-+
-+#endif
-+
-+	return DC_OK;
-+}
-+
-+/*******************************************************************************
-+ * Front End programming
-+ ******************************************************************************/
-+static void set_default_colors(struct pipe_ctx *pipe_ctx)
-+{
-+	struct default_adjustment default_adjust = { 0 };
-+
-+	default_adjust.force_hw_default = false;
-+	if (pipe_ctx->plane_state == NULL)
-+		default_adjust.in_color_space = COLOR_SPACE_SRGB;
-+	else
-+		default_adjust.in_color_space =
-+				pipe_ctx->plane_state->color_space;
-+	if (pipe_ctx->stream == NULL)
-+		default_adjust.out_color_space = COLOR_SPACE_SRGB;
-+	else
-+		default_adjust.out_color_space =
-+				pipe_ctx->stream->output_color_space;
-+	default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
-+	default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
-+
-+	/* display color depth */
-+	default_adjust.color_depth =
-+		pipe_ctx->stream->timing.display_color_depth;
-+
-+	/* Lb color depth */
-+	default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
-+
-+	pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
-+					pipe_ctx->plane_res.xfm, &default_adjust);
-+}
-+
-+
-+/*******************************************************************************
-+ * In order to turn on/off specific surface we will program
-+ * Blender + CRTC
-+ *
-+ * In case that we have two surfaces and they have a different visibility
-+ * we can't turn off the CRTC since it will turn off the entire display
-+ *
-+ * |----------------------------------------------- |
-+ * |bottom pipe|curr pipe  |              |         |
-+ * |Surface    |Surface    | Blender      |  CRCT   |
-+ * |visibility |visibility | Configuration|         |
-+ * |------------------------------------------------|
-+ * |   off     |    off    | CURRENT_PIPE | blank   |
-+ * |   off     |    on     | CURRENT_PIPE | unblank |
-+ * |   on      |    off    | OTHER_PIPE   | unblank |
-+ * |   on      |    on     | BLENDING     | unblank |
-+ * -------------------------------------------------|
-+ *
-+ ******************************************************************************/
-+static void program_surface_visibility(const struct dc *dc,
-+		struct pipe_ctx *pipe_ctx)
-+{
-+	enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
-+	bool blank_target = false;
-+
-+	if (pipe_ctx->bottom_pipe) {
-+
-+		/* For now we are supporting only two pipes */
-+		ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
-+
-+		if (pipe_ctx->bottom_pipe->plane_state->visible) {
-+			if (pipe_ctx->plane_state->visible)
-+				blender_mode = BLND_MODE_BLENDING;
-+			else
-+				blender_mode = BLND_MODE_OTHER_PIPE;
-+
-+		} else if (!pipe_ctx->plane_state->visible)
-+			blank_target = true;
-+
-+	} else if (!pipe_ctx->plane_state->visible)
-+		blank_target = true;
-+
-+	dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode);
-+	pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
-+
-+}
-+
-+static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
-+{
-+	struct xfm_grph_csc_adjustment adjust;
-+	memset(&adjust, 0, sizeof(adjust));
-+	adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
-+
-+
-+	if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
-+		adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
-+		adjust.temperature_matrix[0] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[0];
-+		adjust.temperature_matrix[1] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[1];
-+		adjust.temperature_matrix[2] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[2];
-+		adjust.temperature_matrix[3] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[4];
-+		adjust.temperature_matrix[4] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[5];
-+		adjust.temperature_matrix[5] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[6];
-+		adjust.temperature_matrix[6] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[8];
-+		adjust.temperature_matrix[7] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[9];
-+		adjust.temperature_matrix[8] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[10];
-+	}
-+
-+	pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
-+}
-+
-+/**
-+ * TODO REMOVE, USE UPDATE INSTEAD
-+ */
-+static void set_plane_config(
-+	const struct dc *dc,
-+	struct pipe_ctx *pipe_ctx,
-+	struct resource_context *res_ctx)
-+{
-+	struct mem_input *mi = pipe_ctx->plane_res.mi;
-+	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-+	struct xfm_grph_csc_adjustment adjust;
-+	struct out_csc_color_matrix tbl_entry;
-+	unsigned int i;
-+
-+	memset(&adjust, 0, sizeof(adjust));
-+	memset(&tbl_entry, 0, sizeof(tbl_entry));
-+	adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
-+
-+	dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
-+
-+	set_default_colors(pipe_ctx);
-+	if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
-+		tbl_entry.color_space =
-+			pipe_ctx->stream->output_color_space;
-+
-+		for (i = 0; i < 12; i++)
-+			tbl_entry.regval[i] =
-+			pipe_ctx->stream->csc_color_matrix.matrix[i];
-+
-+		pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
-+				(pipe_ctx->plane_res.xfm, &tbl_entry);
-+	}
-+
-+	if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
-+		adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
-+		adjust.temperature_matrix[0] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[0];
-+		adjust.temperature_matrix[1] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[1];
-+		adjust.temperature_matrix[2] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[2];
-+		adjust.temperature_matrix[3] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[4];
-+		adjust.temperature_matrix[4] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[5];
-+		adjust.temperature_matrix[5] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[6];
-+		adjust.temperature_matrix[6] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[8];
-+		adjust.temperature_matrix[7] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[9];
-+		adjust.temperature_matrix[8] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[10];
-+	}
-+
-+	pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
-+
-+	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
-+	program_scaler(dc, pipe_ctx);
-+
-+	program_surface_visibility(dc, pipe_ctx);
-+
-+	mi->funcs->mem_input_program_surface_config(
-+			mi,
-+			plane_state->format,
-+			&plane_state->tiling_info,
-+			&plane_state->plane_size,
-+			plane_state->rotation,
-+			NULL,
-+			false);
-+	if (mi->funcs->set_blank)
-+		mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
-+
-+	if (dc->config.gpu_vm_support)
-+		mi->funcs->mem_input_program_pte_vm(
-+				pipe_ctx->plane_res.mi,
-+				plane_state->format,
-+				&plane_state->tiling_info,
-+				plane_state->rotation);
-+}
-+
-+static void update_plane_addr(const struct dc *dc,
-+		struct pipe_ctx *pipe_ctx)
-+{
-+	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-+
-+	if (plane_state == NULL)
-+		return;
-+
-+	pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
-+			pipe_ctx->plane_res.mi,
-+			&plane_state->address,
-+			plane_state->flip_immediate);
-+
-+	plane_state->status.requested_address = plane_state->address;
-+}
-+
-+void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
-+{
-+	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-+
-+	if (plane_state == NULL)
-+		return;
-+
-+	plane_state->status.is_flip_pending =
-+			pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
-+					pipe_ctx->plane_res.mi);
-+
-+	if (plane_state->status.is_flip_pending && !plane_state->visible)
-+		pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
-+
-+	plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
-+	if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
-+			pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
-+		plane_state->status.is_right_eye =\
-+				!pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
-+	}
-+}
-+
-+void dce110_power_down(struct dc *dc)
-+{
-+	power_down_all_hw_blocks(dc);
-+	disable_vga_and_power_gate_all_controllers(dc);
-+}
-+
-+static bool wait_for_reset_trigger_to_occur(
-+	struct dc_context *dc_ctx,
-+	struct timing_generator *tg)
-+{
-+	bool rc = false;
-+
-+	/* To avoid endless loop we wait at most
-+	 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
-+	const uint32_t frames_to_wait_on_triggered_reset = 10;
-+	uint32_t i;
-+
-+	for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
-+
-+		if (!tg->funcs->is_counter_moving(tg)) {
-+			DC_ERROR("TG counter is not moving!\n");
-+			break;
-+		}
-+
-+		if (tg->funcs->did_triggered_reset_occur(tg)) {
-+			rc = true;
-+			/* usually occurs at i=1 */
-+			DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
-+					i);
-+			break;
-+		}
-+
-+		/* Wait for one frame. */
-+		tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
-+		tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
-+	}
-+
-+	if (false == rc)
-+		DC_ERROR("GSL: Timeout on reset trigger!\n");
-+
-+	return rc;
-+}
-+
-+/* Enable timing synchronization for a group of Timing Generators. */
-+static void dce110_enable_timing_synchronization(
-+		struct dc *dc,
-+		int group_index,
-+		int group_size,
-+		struct pipe_ctx *grouped_pipes[])
-+{
-+	struct dc_context *dc_ctx = dc->ctx;
-+	struct dcp_gsl_params gsl_params = { 0 };
-+	int i;
-+
-+	DC_SYNC_INFO("GSL: Setting-up...\n");
-+
-+	/* Designate a single TG in the group as a master.
-+	 * Since HW doesn't care which one, we always assign
-+	 * the 1st one in the group. */
-+	gsl_params.gsl_group = 0;
-+	gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
-+
-+	for (i = 0; i < group_size; i++)
-+		grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
-+					grouped_pipes[i]->stream_res.tg, &gsl_params);
-+
-+	/* Reset slave controllers on master VSync */
-+	DC_SYNC_INFO("GSL: enabling trigger-reset\n");
-+
-+	for (i = 1 /* skip the master */; i < group_size; i++)
-+		grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
-+				grouped_pipes[i]->stream_res.tg,
-+				gsl_params.gsl_group);
-+
-+	for (i = 1 /* skip the master */; i < group_size; i++) {
-+		DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
-+		wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
-+		grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
-+				grouped_pipes[i]->stream_res.tg);
-+	}
-+
-+	/* GSL Vblank synchronization is a one time sync mechanism, assumption
-+	 * is that the sync'ed displays will not drift out of sync over time*/
-+	DC_SYNC_INFO("GSL: Restoring register states.\n");
-+	for (i = 0; i < group_size; i++)
-+		grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
-+
-+	DC_SYNC_INFO("GSL: Set-up complete.\n");
-+}
-+
-+static void dce110_enable_per_frame_crtc_position_reset(
-+		struct dc *dc,
-+		int group_size,
-+		struct pipe_ctx *grouped_pipes[])
-+{
-+	struct dc_context *dc_ctx = dc->ctx;
-+	struct dcp_gsl_params gsl_params = { 0 };
-+	int i;
-+
-+	gsl_params.gsl_group = 0;
-+	gsl_params.gsl_master = grouped_pipes[0]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst;
-+
-+	for (i = 0; i < group_size; i++)
-+		grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
-+					grouped_pipes[i]->stream_res.tg, &gsl_params);
-+
-+	DC_SYNC_INFO("GSL: enabling trigger-reset\n");
-+
-+	for (i = 1; i < group_size; i++)
-+		grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
-+				grouped_pipes[i]->stream_res.tg,
-+				gsl_params.gsl_master,
-+				&grouped_pipes[i]->stream->triggered_crtc_reset);
-+
-+	DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
-+	for (i = 1; i < group_size; i++)
-+		wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
-+
-+	for (i = 0; i < group_size; i++)
-+		grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
-+
-+}
-+
-+static void init_hw(struct dc *dc)
-+{
-+	int i;
-+	struct dc_bios *bp;
-+	struct transform *xfm;
-+	struct abm *abm;
-+
-+	bp = dc->ctx->dc_bios;
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		xfm = dc->res_pool->transforms[i];
-+		xfm->funcs->transform_reset(xfm);
-+
-+		dc->hwss.enable_display_power_gating(
-+				dc, i, bp,
-+				PIPE_GATING_CONTROL_INIT);
-+		dc->hwss.enable_display_power_gating(
-+				dc, i, bp,
-+				PIPE_GATING_CONTROL_DISABLE);
-+		dc->hwss.enable_display_pipe_clock_gating(
-+			dc->ctx,
-+			true);
-+	}
-+
-+	dce_clock_gating_power_up(dc->hwseq, false);
-+	/***************************************/
-+
-+	for (i = 0; i < dc->link_count; i++) {
-+		/****************************************/
-+		/* Power up AND update implementation according to the
-+		 * required signal (which may be different from the
-+		 * default signal on connector). */
-+		struct dc_link *link = dc->links[i];
-+
-+		if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
-+			dc->hwss.edp_power_control(link, true);
-+
-+		link->link_enc->funcs->hw_init(link->link_enc);
-+	}
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
-+
-+		tg->funcs->disable_vga(tg);
-+
-+		/* Blank controller using driver code instead of
-+		 * command table. */
-+		tg->funcs->set_blank(tg, true);
-+		hwss_wait_for_blank_complete(tg);
-+	}
-+
-+	for (i = 0; i < dc->res_pool->audio_count; i++) {
-+		struct audio *audio = dc->res_pool->audios[i];
-+		audio->funcs->hw_init(audio);
-+	}
-+
-+	abm = dc->res_pool->abm;
-+	if (abm != NULL) {
-+		abm->funcs->init_backlight(abm);
-+		abm->funcs->abm_init(abm);
-+	}
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+	if (dc->fbc_compressor)
-+		dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
-+#endif
-+
-+}
-+
-+void dce110_fill_display_configs(
-+	const struct dc_state *context,
-+	struct dm_pp_display_configuration *pp_display_cfg)
-+{
-+	int j;
-+	int num_cfgs = 0;
-+
-+	for (j = 0; j < context->stream_count; j++) {
-+		int k;
-+
-+		const struct dc_stream_state *stream = context->streams[j];
-+		struct dm_pp_single_disp_config *cfg =
-+			&pp_display_cfg->disp_configs[num_cfgs];
-+		const struct pipe_ctx *pipe_ctx = NULL;
-+
-+		for (k = 0; k < MAX_PIPES; k++)
-+			if (stream == context->res_ctx.pipe_ctx[k].stream) {
-+				pipe_ctx = &context->res_ctx.pipe_ctx[k];
-+				break;
-+			}
-+
-+		ASSERT(pipe_ctx != NULL);
-+
-+		/* only notify active stream */
-+		if (stream->dpms_off)
-+			continue;
-+
-+		num_cfgs++;
-+		cfg->signal = pipe_ctx->stream->signal;
-+		cfg->pipe_idx = pipe_ctx->pipe_idx;
-+		cfg->src_height = stream->src.height;
-+		cfg->src_width = stream->src.width;
-+		cfg->ddi_channel_mapping =
-+			stream->sink->link->ddi_channel_mapping.raw;
-+		cfg->transmitter =
-+			stream->sink->link->link_enc->transmitter;
-+		cfg->link_settings.lane_count =
-+			stream->sink->link->cur_link_settings.lane_count;
-+		cfg->link_settings.link_rate =
-+			stream->sink->link->cur_link_settings.link_rate;
-+		cfg->link_settings.link_spread =
-+			stream->sink->link->cur_link_settings.link_spread;
-+		cfg->sym_clock = stream->phy_pix_clk;
-+		/* Round v_refresh*/
-+		cfg->v_refresh = stream->timing.pix_clk_khz * 1000;
-+		cfg->v_refresh /= stream->timing.h_total;
-+		cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
-+							/ stream->timing.v_total;
-+	}
-+
-+	pp_display_cfg->display_count = num_cfgs;
-+}
-+
-+uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
-+{
-+	uint8_t j;
-+	uint32_t min_vertical_blank_time = -1;
-+
-+	for (j = 0; j < context->stream_count; j++) {
-+		struct dc_stream_state *stream = context->streams[j];
-+		uint32_t vertical_blank_in_pixels = 0;
-+		uint32_t vertical_blank_time = 0;
-+
-+		vertical_blank_in_pixels = stream->timing.h_total *
-+			(stream->timing.v_total
-+			 - stream->timing.v_addressable);
-+
-+		vertical_blank_time = vertical_blank_in_pixels
-+			* 1000 / stream->timing.pix_clk_khz;
-+
-+		if (min_vertical_blank_time > vertical_blank_time)
-+			min_vertical_blank_time = vertical_blank_time;
-+	}
-+
-+	return min_vertical_blank_time;
-+}
-+
-+static int determine_sclk_from_bounding_box(
-+		const struct dc *dc,
-+		int required_sclk)
-+{
-+	int i;
-+
-+	/*
-+	 * Some asics do not give us sclk levels, so we just report the actual
-+	 * required sclk
-+	 */
-+	if (dc->sclk_lvls.num_levels == 0)
-+		return required_sclk;
-+
-+	for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
-+		if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
-+			return dc->sclk_lvls.clocks_in_khz[i];
-+	}
-+	/*
-+	 * even maximum level could not satisfy requirement, this
-+	 * is unexpected at this stage, should have been caught at
-+	 * validation time
-+	 */
-+	ASSERT(0);
-+	return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
-+}
-+
-+static void pplib_apply_display_requirements(
-+	struct dc *dc,
-+	struct dc_state *context)
-+{
-+	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
-+
-+	pp_display_cfg->all_displays_in_sync =
-+		context->bw.dce.all_displays_in_sync;
-+	pp_display_cfg->nb_pstate_switch_disable =
-+			context->bw.dce.nbp_state_change_enable == false;
-+	pp_display_cfg->cpu_cc6_disable =
-+			context->bw.dce.cpuc_state_change_enable == false;
-+	pp_display_cfg->cpu_pstate_disable =
-+			context->bw.dce.cpup_state_change_enable == false;
-+	pp_display_cfg->cpu_pstate_separation_time =
-+			context->bw.dce.blackout_recovery_time_us;
-+
-+	pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
-+		/ MEMORY_TYPE_MULTIPLIER;
-+
-+	pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
-+			dc,
-+			context->bw.dce.sclk_khz);
-+
-+	pp_display_cfg->min_engine_clock_deep_sleep_khz
-+			= context->bw.dce.sclk_deep_sleep_khz;
-+
-+	pp_display_cfg->avail_mclk_switch_time_us =
-+						dce110_get_min_vblank_time_us(context);
-+	/* TODO: dce11.2*/
-+	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
-+
-+	pp_display_cfg->disp_clk_khz = context->bw.dce.dispclk_khz;
-+
-+	dce110_fill_display_configs(context, pp_display_cfg);
-+
-+	/* TODO: is this still applicable?*/
-+	if (pp_display_cfg->display_count == 1) {
-+		const struct dc_crtc_timing *timing =
-+			&context->streams[0]->timing;
-+
-+		pp_display_cfg->crtc_index =
-+			pp_display_cfg->disp_configs[0].pipe_idx;
-+		pp_display_cfg->line_time_in_us = timing->h_total * 1000
-+							/ timing->pix_clk_khz;
-+	}
-+
-+	if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
-+			struct dm_pp_display_configuration)) !=  0)
-+		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
-+
-+	dc->prev_display_config = *pp_display_cfg;
-+}
-+
-+static void dce110_set_bandwidth(
-+		struct dc *dc,
-+		struct dc_state *context,
-+		bool decrease_allowed)
-+{
-+	dce110_set_displaymarks(dc, context);
-+
-+	if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) {
-+		dc->res_pool->display_clock->funcs->set_clock(
-+				dc->res_pool->display_clock,
-+				context->bw.dce.dispclk_khz * 115 / 100);
-+		dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz;
-+	}
-+
-+	pplib_apply_display_requirements(dc, context);
-+}
-+
-+static void dce110_program_front_end_for_pipe(
-+		struct dc *dc, struct pipe_ctx *pipe_ctx)
-+{
-+	struct mem_input *mi = pipe_ctx->plane_res.mi;
-+	struct pipe_ctx *old_pipe = NULL;
-+	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-+	struct xfm_grph_csc_adjustment adjust;
-+	struct out_csc_color_matrix tbl_entry;
-+	struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
-+	unsigned int i;
-+
-+	memset(&tbl_entry, 0, sizeof(tbl_entry));
-+
-+	if (dc->current_state)
-+		old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
-+
-+	memset(&adjust, 0, sizeof(adjust));
-+	adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
-+
-+	dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
-+
-+	set_default_colors(pipe_ctx);
-+	if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
-+			== true) {
-+		tbl_entry.color_space =
-+			pipe_ctx->stream->output_color_space;
-+
-+		for (i = 0; i < 12; i++)
-+			tbl_entry.regval[i] =
-+			pipe_ctx->stream->csc_color_matrix.matrix[i];
-+
-+		pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
-+				(pipe_ctx->plane_res.xfm, &tbl_entry);
-+	}
-+
-+	if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
-+		adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
-+		adjust.temperature_matrix[0] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[0];
-+		adjust.temperature_matrix[1] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[1];
-+		adjust.temperature_matrix[2] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[2];
-+		adjust.temperature_matrix[3] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[4];
-+		adjust.temperature_matrix[4] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[5];
-+		adjust.temperature_matrix[5] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[6];
-+		adjust.temperature_matrix[6] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[8];
-+		adjust.temperature_matrix[7] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[9];
-+		adjust.temperature_matrix[8] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[10];
-+	}
-+
-+	pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
-+
-+	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
-+
-+	program_scaler(dc, pipe_ctx);
-+
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+	if (dc->fbc_compressor && old_pipe->stream) {
-+		if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
-+			dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
-+		else
-+			enable_fbc(dc, dc->current_state);
-+	}
-+#endif
-+
-+	mi->funcs->mem_input_program_surface_config(
-+			mi,
-+			plane_state->format,
-+			&plane_state->tiling_info,
-+			&plane_state->plane_size,
-+			plane_state->rotation,
-+			NULL,
-+			false);
-+	if (mi->funcs->set_blank)
-+		mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
-+
-+	if (dc->config.gpu_vm_support)
-+		mi->funcs->mem_input_program_pte_vm(
-+				pipe_ctx->plane_res.mi,
-+				plane_state->format,
-+				&plane_state->tiling_info,
-+				plane_state->rotation);
-+
-+	/* Moved programming gamma from dc to hwss */
-+	if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
-+		dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
-+		dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
-+	}
-+
-+	dm_logger_write(dc->ctx->logger, LOG_SURFACE,
-+			"Pipe:%d 0x%x: addr hi:0x%x, "
-+			"addr low:0x%x, "
-+			"src: %d, %d, %d,"
-+			" %d; dst: %d, %d, %d, %d;"
-+			"clip: %d, %d, %d, %d\n",
-+			pipe_ctx->pipe_idx,
-+			pipe_ctx->plane_state,
-+			pipe_ctx->plane_state->address.grph.addr.high_part,
-+			pipe_ctx->plane_state->address.grph.addr.low_part,
-+			pipe_ctx->plane_state->src_rect.x,
-+			pipe_ctx->plane_state->src_rect.y,
-+			pipe_ctx->plane_state->src_rect.width,
-+			pipe_ctx->plane_state->src_rect.height,
-+			pipe_ctx->plane_state->dst_rect.x,
-+			pipe_ctx->plane_state->dst_rect.y,
-+			pipe_ctx->plane_state->dst_rect.width,
-+			pipe_ctx->plane_state->dst_rect.height,
-+			pipe_ctx->plane_state->clip_rect.x,
-+			pipe_ctx->plane_state->clip_rect.y,
-+			pipe_ctx->plane_state->clip_rect.width,
-+			pipe_ctx->plane_state->clip_rect.height);
-+
-+	dm_logger_write(dc->ctx->logger, LOG_SURFACE,
-+			"Pipe %d: width, height, x, y\n"
-+			"viewport:%d, %d, %d, %d\n"
-+			"recout:  %d, %d, %d, %d\n",
-+			pipe_ctx->pipe_idx,
-+			pipe_ctx->plane_res.scl_data.viewport.width,
-+			pipe_ctx->plane_res.scl_data.viewport.height,
-+			pipe_ctx->plane_res.scl_data.viewport.x,
-+			pipe_ctx->plane_res.scl_data.viewport.y,
-+			pipe_ctx->plane_res.scl_data.recout.width,
-+			pipe_ctx->plane_res.scl_data.recout.height,
-+			pipe_ctx->plane_res.scl_data.recout.x,
-+			pipe_ctx->plane_res.scl_data.recout.y);
-+}
-+
-+static void dce110_apply_ctx_for_surface(
-+		struct dc *dc,
-+		const struct dc_stream_state *stream,
-+		int num_planes,
-+		struct dc_state *context)
-+{
-+	int i;
-+
-+	if (num_planes == 0)
-+		return;
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+		struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
-+
-+		if (stream == pipe_ctx->stream) {
-+			if (!pipe_ctx->top_pipe &&
-+				(pipe_ctx->plane_state || old_pipe_ctx->plane_state))
-+				dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
-+		}
-+	}
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+		if (pipe_ctx->stream != stream)
-+			continue;
-+
-+		/* Need to allocate mem before program front end for Fiji */
-+		if (pipe_ctx->plane_res.mi != NULL)
-+			pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
-+					pipe_ctx->plane_res.mi,
-+					pipe_ctx->stream->timing.h_total,
-+					pipe_ctx->stream->timing.v_total,
-+					pipe_ctx->stream->timing.pix_clk_khz,
-+					context->stream_count);
-+
-+		dce110_program_front_end_for_pipe(dc, pipe_ctx);
-+		program_surface_visibility(dc, pipe_ctx);
-+
-+	}
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+		struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
-+
-+		if ((stream == pipe_ctx->stream) &&
-+			(!pipe_ctx->top_pipe) &&
-+			(pipe_ctx->plane_state || old_pipe_ctx->plane_state))
-+			dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
-+	}
-+}
-+
-+static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
-+{
-+	int fe_idx = pipe_ctx->pipe_idx;
-+
-+	/* Do not power down fe when stream is active on dce*/
-+	if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
-+		return;
-+
-+	dc->hwss.enable_display_power_gating(
-+		dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
-+
-+	dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
-+				dc->res_pool->transforms[fe_idx]);
-+}
-+
-+static void dce110_wait_for_mpcc_disconnect(
-+		struct dc *dc,
-+		struct resource_pool *res_pool,
-+		struct pipe_ctx *pipe_ctx)
-+{
-+	/* do nothing*/
-+}
-+
-+static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
-+		enum dc_color_space colorspace,
-+		uint16_t *matrix)
-+{
-+	int i;
-+	struct out_csc_color_matrix tbl_entry;
-+
-+	if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
-+				== true) {
-+			enum dc_color_space color_space =
-+				pipe_ctx->stream->output_color_space;
-+
-+			//uint16_t matrix[12];
-+			for (i = 0; i < 12; i++)
-+				tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
-+
-+			tbl_entry.color_space = color_space;
-+			//tbl_entry.regval = matrix;
-+			pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.xfm, &tbl_entry);
-+	}
-+}
-+
-+static void ready_shared_resources(struct dc *dc, struct dc_state *context) {}
-+
-+static void optimize_shared_resources(struct dc *dc) {}
-+
-+static const struct hw_sequencer_funcs dce110_funcs = {
-+	.program_gamut_remap = program_gamut_remap,
-+	.program_csc_matrix = program_csc_matrix,
-+	.init_hw = init_hw,
-+	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
-+	.apply_ctx_for_surface = dce110_apply_ctx_for_surface,
-+	.set_plane_config = set_plane_config,
-+	.update_plane_addr = update_plane_addr,
-+	.update_pending_status = dce110_update_pending_status,
-+	.set_input_transfer_func = dce110_set_input_transfer_func,
-+	.set_output_transfer_func = dce110_set_output_transfer_func,
-+	.power_down = dce110_power_down,
-+	.enable_accelerated_mode = dce110_enable_accelerated_mode,
-+	.enable_timing_synchronization = dce110_enable_timing_synchronization,
-+	.enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
-+	.update_info_frame = dce110_update_info_frame,
-+	.enable_stream = dce110_enable_stream,
-+	.disable_stream = dce110_disable_stream,
-+	.unblank_stream = dce110_unblank_stream,
-+	.enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
-+	.enable_display_power_gating = dce110_enable_display_power_gating,
-+	.disable_plane = dce110_power_down_fe,
-+	.pipe_control_lock = dce_pipe_control_lock,
-+	.set_bandwidth = dce110_set_bandwidth,
-+	.set_drr = set_drr,
-+	.get_position = get_position,
-+	.set_static_screen_control = set_static_screen_control,
-+	.reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
-+	.prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg,
-+	.setup_stereo = NULL,
-+	.set_avmute = dce110_set_avmute,
-+	.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
-+	.ready_shared_resources = ready_shared_resources,
-+	.optimize_shared_resources = optimize_shared_resources,
-+	.pplib_apply_display_requirements = pplib_apply_display_requirements,
-+	.edp_backlight_control = hwss_edp_backlight_control,
-+	.edp_power_control = hwss_edp_power_control,
-+};
-+
-+void dce110_hw_sequencer_construct(struct dc *dc)
-+{
-+	dc->hwss = dce110_funcs;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h.0130~	2017-12-14 06:39:58.409903563 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h	2017-12-14 06:39:58.409903563 +0100
-@@ -0,0 +1,81 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_HWSS_DCE110_H__
-+#define __DC_HWSS_DCE110_H__
-+
-+#include "core_types.h"
-+
-+#define GAMMA_HW_POINTS_NUM 256
-+struct dc;
-+struct dc_state;
-+struct dm_pp_display_configuration;
-+
-+void dce110_hw_sequencer_construct(struct dc *dc);
-+
-+enum dc_status dce110_apply_ctx_to_hw(
-+		struct dc *dc,
-+		struct dc_state *context);
-+
-+void dce110_set_display_clock(struct dc_state *context);
-+
-+void dce110_set_displaymarks(
-+	const struct dc *dc,
-+	struct dc_state *context);
-+
-+void dce110_enable_stream(struct pipe_ctx *pipe_ctx);
-+
-+void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option);
-+
-+void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
-+		struct dc_link_settings *link_settings);
-+
-+void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
-+
-+void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
-+void dce110_enable_accelerated_mode(struct dc *dc);
-+
-+void dce110_power_down(struct dc *dc);
-+
-+void dce110_update_pending_status(struct pipe_ctx *pipe_ctx);
-+
-+void dce110_fill_display_configs(
-+	const struct dc_state *context,
-+	struct dm_pp_display_configuration *pp_display_cfg);
-+
-+uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context);
-+
-+void dp_receiver_power_ctrl(struct dc_link *link, bool on);
-+
-+void hwss_edp_power_control(
-+		struct dc_link *link,
-+		bool power_up);
-+
-+void hwss_edp_backlight_control(
-+	struct dc_link *link,
-+	bool enable);
-+
-+#endif /* __DC_HWSS_DCE110_H__ */
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c.0130~	2017-12-14 06:39:58.410903564 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c	2017-12-14 06:39:58.410903564 +0100
-@@ -0,0 +1,1040 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dm_services.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+/* TODO: this needs to be looked at, used by Stella's workaround*/
-+#include "gmc/gmc_8_2_d.h"
-+#include "gmc/gmc_8_2_sh_mask.h"
-+
-+#include "include/logger_interface.h"
-+#include "inc/dce_calcs.h"
-+
-+#include "dce/dce_mem_input.h"
-+
-+static void set_flip_control(
-+	struct dce_mem_input *mem_input110,
-+	bool immediate)
-+{
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(
-+			mem_input110->base.ctx,
-+			mmUNP_FLIP_CONTROL);
-+
-+	set_reg_field_value(value, 1,
-+			UNP_FLIP_CONTROL,
-+			GRPH_SURFACE_UPDATE_PENDING_MODE);
-+
-+	dm_write_reg(
-+			mem_input110->base.ctx,
-+			mmUNP_FLIP_CONTROL,
-+			value);
-+}
-+
-+/* chroma part */
-+static void program_pri_addr_c(
-+	struct dce_mem_input *mem_input110,
-+	PHYSICAL_ADDRESS_LOC address)
-+{
-+	uint32_t value = 0;
-+	uint32_t temp = 0;
-+	/*high register MUST be programmed first*/
-+	temp = address.high_part &
-+UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK;
-+
-+	set_reg_field_value(value, temp,
-+		UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,
-+		GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C);
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,
-+		value);
-+
-+	temp = 0;
-+	value = 0;
-+	temp = address.low_part >>
-+	UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT;
-+
-+	set_reg_field_value(value, temp,
-+		UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C,
-+		GRPH_PRIMARY_SURFACE_ADDRESS_C);
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C,
-+		value);
-+}
-+
-+/* luma part */
-+static void program_pri_addr_l(
-+	struct dce_mem_input *mem_input110,
-+	PHYSICAL_ADDRESS_LOC address)
-+{
-+	uint32_t value = 0;
-+	uint32_t temp = 0;
-+
-+	/*high register MUST be programmed first*/
-+	temp = address.high_part &
-+UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK;
-+
-+	set_reg_field_value(value, temp,
-+		UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,
-+		GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L);
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,
-+		value);
-+
-+	temp = 0;
-+	value = 0;
-+	temp = address.low_part >>
-+	UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT;
-+
-+	set_reg_field_value(value, temp,
-+		UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L,
-+		GRPH_PRIMARY_SURFACE_ADDRESS_L);
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L,
-+		value);
-+}
-+
-+static void program_addr(
-+	struct dce_mem_input *mem_input110,
-+	const struct dc_plane_address *addr)
-+{
-+	switch (addr->type) {
-+	case PLN_ADDR_TYPE_GRAPHICS:
-+		program_pri_addr_l(
-+			mem_input110,
-+			addr->grph.addr);
-+		break;
-+	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
-+		program_pri_addr_c(
-+			mem_input110,
-+			addr->video_progressive.chroma_addr);
-+		program_pri_addr_l(
-+			mem_input110,
-+			addr->video_progressive.luma_addr);
-+		break;
-+	default:
-+		/* not supported */
-+		BREAK_TO_DEBUGGER();
-+	}
-+}
-+
-+static void enable(struct dce_mem_input *mem_input110)
-+{
-+	uint32_t value = 0;
-+
-+	value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_ENABLE);
-+	set_reg_field_value(value, 1, UNP_GRPH_ENABLE, GRPH_ENABLE);
-+	dm_write_reg(mem_input110->base.ctx,
-+		mmUNP_GRPH_ENABLE,
-+		value);
-+}
-+
-+static void program_tiling(
-+	struct dce_mem_input *mem_input110,
-+	const union dc_tiling_info *info,
-+	const enum surface_pixel_format pixel_format)
-+{
-+	uint32_t value = 0;
-+
-+	set_reg_field_value(value, info->gfx8.num_banks,
-+		UNP_GRPH_CONTROL, GRPH_NUM_BANKS);
-+
-+	set_reg_field_value(value, info->gfx8.bank_width,
-+		UNP_GRPH_CONTROL, GRPH_BANK_WIDTH_L);
-+
-+	set_reg_field_value(value, info->gfx8.bank_height,
-+		UNP_GRPH_CONTROL, GRPH_BANK_HEIGHT_L);
-+
-+	set_reg_field_value(value, info->gfx8.tile_aspect,
-+		UNP_GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT_L);
-+
-+	set_reg_field_value(value, info->gfx8.tile_split,
-+		UNP_GRPH_CONTROL, GRPH_TILE_SPLIT_L);
-+
-+	set_reg_field_value(value, info->gfx8.tile_mode,
-+		UNP_GRPH_CONTROL, GRPH_MICRO_TILE_MODE_L);
-+
-+	set_reg_field_value(value, info->gfx8.pipe_config,
-+		UNP_GRPH_CONTROL, GRPH_PIPE_CONFIG);
-+
-+	set_reg_field_value(value, info->gfx8.array_mode,
-+		UNP_GRPH_CONTROL, GRPH_ARRAY_MODE);
-+
-+	set_reg_field_value(value, 1,
-+		UNP_GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE);
-+
-+	set_reg_field_value(value, 0,
-+		UNP_GRPH_CONTROL, GRPH_Z);
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_CONTROL,
-+		value);
-+
-+	value = 0;
-+
-+	set_reg_field_value(value, info->gfx8.bank_width_c,
-+		UNP_GRPH_CONTROL_C, GRPH_BANK_WIDTH_C);
-+
-+	set_reg_field_value(value, info->gfx8.bank_height_c,
-+		UNP_GRPH_CONTROL_C, GRPH_BANK_HEIGHT_C);
-+
-+	set_reg_field_value(value, info->gfx8.tile_aspect_c,
-+		UNP_GRPH_CONTROL_C, GRPH_MACRO_TILE_ASPECT_C);
-+
-+	set_reg_field_value(value, info->gfx8.tile_split_c,
-+		UNP_GRPH_CONTROL_C, GRPH_TILE_SPLIT_C);
-+
-+	set_reg_field_value(value, info->gfx8.tile_mode_c,
-+		UNP_GRPH_CONTROL_C, GRPH_MICRO_TILE_MODE_C);
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_CONTROL_C,
-+		value);
-+}
-+
-+static void program_size_and_rotation(
-+	struct dce_mem_input *mem_input110,
-+	enum dc_rotation_angle rotation,
-+	const union plane_size *plane_size)
-+{
-+	uint32_t value = 0;
-+	union plane_size local_size = *plane_size;
-+
-+	if (rotation == ROTATION_ANGLE_90 ||
-+		rotation == ROTATION_ANGLE_270) {
-+
-+		swap(local_size.video.luma_size.x,
-+		     local_size.video.luma_size.y);
-+		swap(local_size.video.luma_size.width,
-+		     local_size.video.luma_size.height);
-+		swap(local_size.video.chroma_size.x,
-+		     local_size.video.chroma_size.y);
-+		swap(local_size.video.chroma_size.width,
-+		     local_size.video.chroma_size.height);
-+	}
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.video.luma_pitch,
-+			UNP_GRPH_PITCH_L, GRPH_PITCH_L);
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_PITCH_L,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.video.chroma_pitch,
-+			UNP_GRPH_PITCH_C, GRPH_PITCH_C);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_PITCH_C,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, 0,
-+			UNP_GRPH_X_START_L, GRPH_X_START_L);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_X_START_L,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, 0,
-+			UNP_GRPH_X_START_C, GRPH_X_START_C);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_X_START_C,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, 0,
-+			UNP_GRPH_Y_START_L, GRPH_Y_START_L);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_Y_START_L,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, 0,
-+			UNP_GRPH_Y_START_C, GRPH_Y_START_C);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_Y_START_C,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.video.luma_size.x +
-+			local_size.video.luma_size.width,
-+			UNP_GRPH_X_END_L, GRPH_X_END_L);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_X_END_L,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.video.chroma_size.x +
-+			local_size.video.chroma_size.width,
-+			UNP_GRPH_X_END_C, GRPH_X_END_C);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_X_END_C,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.video.luma_size.y +
-+			local_size.video.luma_size.height,
-+			UNP_GRPH_Y_END_L, GRPH_Y_END_L);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_Y_END_L,
-+		value);
-+
-+	value = 0;
-+	set_reg_field_value(value, local_size.video.chroma_size.y +
-+			local_size.video.chroma_size.height,
-+			UNP_GRPH_Y_END_C, GRPH_Y_END_C);
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_GRPH_Y_END_C,
-+		value);
-+
-+	value = 0;
-+	switch (rotation) {
-+	case ROTATION_ANGLE_90:
-+		set_reg_field_value(value, 3,
-+			UNP_HW_ROTATION, ROTATION_ANGLE);
-+		break;
-+	case ROTATION_ANGLE_180:
-+		set_reg_field_value(value, 2,
-+			UNP_HW_ROTATION, ROTATION_ANGLE);
-+		break;
-+	case ROTATION_ANGLE_270:
-+		set_reg_field_value(value, 1,
-+			UNP_HW_ROTATION, ROTATION_ANGLE);
-+		break;
-+	default:
-+		set_reg_field_value(value, 0,
-+			UNP_HW_ROTATION, ROTATION_ANGLE);
-+		break;
-+	}
-+
-+	dm_write_reg(
-+		mem_input110->base.ctx,
-+		mmUNP_HW_ROTATION,
-+		value);
-+}
-+
-+static void program_pixel_format(
-+	struct dce_mem_input *mem_input110,
-+	enum surface_pixel_format format)
-+{
-+	if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-+		uint32_t value;
-+		uint8_t grph_depth;
-+		uint8_t grph_format;
-+
-+		value =	dm_read_reg(
-+				mem_input110->base.ctx,
-+				mmUNP_GRPH_CONTROL);
-+
-+		switch (format) {
-+		case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
-+			grph_depth = 0;
-+			grph_format = 0;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
-+			grph_depth = 1;
-+			grph_format = 1;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
-+			grph_depth = 2;
-+			grph_format = 0;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
-+			grph_depth = 2;
-+			grph_format = 1;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+		case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
-+			grph_depth = 3;
-+			grph_format = 0;
-+			break;
-+		default:
-+			grph_depth = 2;
-+			grph_format = 0;
-+			break;
-+		}
-+
-+		set_reg_field_value(
-+				value,
-+				grph_depth,
-+				UNP_GRPH_CONTROL,
-+				GRPH_DEPTH);
-+		set_reg_field_value(
-+				value,
-+				grph_format,
-+				UNP_GRPH_CONTROL,
-+				GRPH_FORMAT);
-+
-+		dm_write_reg(
-+				mem_input110->base.ctx,
-+				mmUNP_GRPH_CONTROL,
-+				value);
-+
-+		value =	dm_read_reg(
-+				mem_input110->base.ctx,
-+				mmUNP_GRPH_CONTROL_EXP);
-+
-+		/* VIDEO FORMAT 0 */
-+		set_reg_field_value(
-+				value,
-+				0,
-+				UNP_GRPH_CONTROL_EXP,
-+				VIDEO_FORMAT);
-+		dm_write_reg(
-+				mem_input110->base.ctx,
-+				mmUNP_GRPH_CONTROL_EXP,
-+				value);
-+
-+	} else {
-+		/* Video 422 and 420 needs UNP_GRPH_CONTROL_EXP programmed */
-+		uint32_t value;
-+		uint8_t video_format;
-+
-+		value =	dm_read_reg(
-+				mem_input110->base.ctx,
-+				mmUNP_GRPH_CONTROL_EXP);
-+
-+		switch (format) {
-+		case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
-+			video_format = 2;
-+			break;
-+		case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
-+			video_format = 3;
-+			break;
-+		default:
-+			video_format = 0;
-+			break;
-+		}
-+
-+		set_reg_field_value(
-+			value,
-+			video_format,
-+			UNP_GRPH_CONTROL_EXP,
-+			VIDEO_FORMAT);
-+
-+		dm_write_reg(
-+			mem_input110->base.ctx,
-+			mmUNP_GRPH_CONTROL_EXP,
-+			value);
-+	}
-+}
-+
-+bool dce_mem_input_v_is_surface_pending(struct mem_input *mem_input)
-+{
-+	struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
-+	uint32_t value;
-+
-+	value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_UPDATE);
-+
-+	if (get_reg_field_value(value, UNP_GRPH_UPDATE,
-+			GRPH_SURFACE_UPDATE_PENDING))
-+		return true;
-+
-+	mem_input->current_address = mem_input->request_address;
-+	return false;
-+}
-+
-+bool dce_mem_input_v_program_surface_flip_and_addr(
-+	struct mem_input *mem_input,
-+	const struct dc_plane_address *address,
-+	bool flip_immediate)
-+{
-+	struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
-+
-+	set_flip_control(mem_input110, flip_immediate);
-+	program_addr(mem_input110,
-+		address);
-+
-+	mem_input->request_address = *address;
-+
-+	return true;
-+}
-+
-+/* Scatter Gather param tables */
-+static const unsigned int dvmm_Hw_Setting_2DTiling[4][9] = {
-+		{  8, 64, 64,  8,  8, 1, 4, 0, 0},
-+		{ 16, 64, 32,  8, 16, 1, 8, 0, 0},
-+		{ 32, 32, 32, 16, 16, 1, 8, 0, 0},
-+		{ 64,  8, 32, 16, 16, 1, 8, 0, 0}, /* fake */
-+};
-+
-+static const unsigned int dvmm_Hw_Setting_1DTiling[4][9] = {
-+		{  8, 512, 8, 1, 0, 1, 0, 0, 0},  /* 0 for invalid */
-+		{ 16, 256, 8, 2, 0, 1, 0, 0, 0},
-+		{ 32, 128, 8, 4, 0, 1, 0, 0, 0},
-+		{ 64,  64, 8, 4, 0, 1, 0, 0, 0}, /* fake */
-+};
-+
-+static const unsigned int dvmm_Hw_Setting_Linear[4][9] = {
-+		{  8, 4096, 1, 8, 0, 1, 0, 0, 0},
-+		{ 16, 2048, 1, 8, 0, 1, 0, 0, 0},
-+		{ 32, 1024, 1, 8, 0, 1, 0, 0, 0},
-+		{ 64,  512, 1, 8, 0, 1, 0, 0, 0}, /* new for 64bpp from HW */
-+};
-+
-+/* Helper to get table entry from surface info */
-+static const unsigned int *get_dvmm_hw_setting(
-+		union dc_tiling_info *tiling_info,
-+		enum surface_pixel_format format,
-+		bool chroma)
-+{
-+	enum bits_per_pixel {
-+		bpp_8 = 0,
-+		bpp_16,
-+		bpp_32,
-+		bpp_64
-+	} bpp;
-+
-+	if (format >= SURFACE_PIXEL_FORMAT_INVALID)
-+		bpp = bpp_32;
-+	else if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
-+		bpp = chroma ? bpp_16 : bpp_8;
-+	else
-+		bpp = bpp_8;
-+
-+	switch (tiling_info->gfx8.array_mode) {
-+	case DC_ARRAY_1D_TILED_THIN1:
-+	case DC_ARRAY_1D_TILED_THICK:
-+	case DC_ARRAY_PRT_TILED_THIN1:
-+		return dvmm_Hw_Setting_1DTiling[bpp];
-+	case DC_ARRAY_2D_TILED_THIN1:
-+	case DC_ARRAY_2D_TILED_THICK:
-+	case DC_ARRAY_2D_TILED_X_THICK:
-+	case DC_ARRAY_PRT_2D_TILED_THIN1:
-+	case DC_ARRAY_PRT_2D_TILED_THICK:
-+		return dvmm_Hw_Setting_2DTiling[bpp];
-+	case DC_ARRAY_LINEAR_GENERAL:
-+	case DC_ARRAY_LINEAR_ALLIGNED:
-+		return dvmm_Hw_Setting_Linear[bpp];
-+	default:
-+		return dvmm_Hw_Setting_2DTiling[bpp];
-+	}
-+}
-+
-+void dce_mem_input_v_program_pte_vm(
-+		struct mem_input *mem_input,
-+		enum surface_pixel_format format,
-+		union dc_tiling_info *tiling_info,
-+		enum dc_rotation_angle rotation)
-+{
-+	struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
-+	const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false);
-+	const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true);
-+
-+	unsigned int page_width = 0;
-+	unsigned int page_height = 0;
-+	unsigned int page_width_chroma = 0;
-+	unsigned int page_height_chroma = 0;
-+	unsigned int temp_page_width = pte[1];
-+	unsigned int temp_page_height = pte[2];
-+	unsigned int min_pte_before_flip = 0;
-+	unsigned int min_pte_before_flip_chroma = 0;
-+	uint32_t value = 0;
-+
-+	while ((temp_page_width >>= 1) != 0)
-+		page_width++;
-+	while ((temp_page_height >>= 1) != 0)
-+		page_height++;
-+
-+	temp_page_width = pte_chroma[1];
-+	temp_page_height = pte_chroma[2];
-+	while ((temp_page_width >>= 1) != 0)
-+		page_width_chroma++;
-+	while ((temp_page_height >>= 1) != 0)
-+		page_height_chroma++;
-+
-+	switch (rotation) {
-+	case ROTATION_ANGLE_90:
-+	case ROTATION_ANGLE_270:
-+		min_pte_before_flip = pte[4];
-+		min_pte_before_flip_chroma = pte_chroma[4];
-+		break;
-+	default:
-+		min_pte_before_flip = pte[3];
-+		min_pte_before_flip_chroma = pte_chroma[3];
-+		break;
-+	}
-+
-+	value = dm_read_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT);
-+	/* TODO: un-hardcode requestlimit */
-+	set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L);
-+	set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C);
-+	dm_write_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT, value);
-+
-+	value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL);
-+	set_reg_field_value(value, page_width, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH);
-+	set_reg_field_value(value, page_height, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT);
-+	set_reg_field_value(value, min_pte_before_flip, UNP_DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP);
-+	dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL, value);
-+
-+	value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL);
-+	set_reg_field_value(value, pte[5], UNP_DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK);
-+	set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING);
-+	dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL, value);
-+
-+	value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C);
-+	set_reg_field_value(value, page_width_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_WIDTH_C);
-+	set_reg_field_value(value, page_height_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_HEIGHT_C);
-+	set_reg_field_value(value, min_pte_before_flip_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_MIN_PTE_BEFORE_FLIP_C);
-+	dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C, value);
-+
-+	value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C);
-+	set_reg_field_value(value, pte_chroma[5], UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_PTE_REQ_PER_CHUNK_C);
-+	set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_MAX_PTE_REQ_OUTSTANDING_C);
-+	dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C, value);
-+}
-+
-+void dce_mem_input_v_program_surface_config(
-+	struct mem_input *mem_input,
-+	enum surface_pixel_format format,
-+	union dc_tiling_info *tiling_info,
-+	union plane_size *plane_size,
-+	enum dc_rotation_angle rotation,
-+	struct dc_plane_dcc_param *dcc,
-+	bool horizotal_mirror)
-+{
-+	struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
-+
-+	enable(mem_input110);
-+	program_tiling(mem_input110, tiling_info, format);
-+	program_size_and_rotation(mem_input110, rotation, plane_size);
-+	program_pixel_format(mem_input110, format);
-+}
-+
-+static void program_urgency_watermark(
-+	const struct dc_context *ctx,
-+	const uint32_t urgency_addr,
-+	const uint32_t wm_addr,
-+	struct dce_watermarks marks_low,
-+	uint32_t total_dest_line_time_ns)
-+{
-+	/* register value */
-+	uint32_t urgency_cntl = 0;
-+	uint32_t wm_mask_cntl = 0;
-+
-+	/*Write mask to enable reading/writing of watermark set A*/
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+			1,
-+			DPGV0_WATERMARK_MASK_CONTROL,
-+			URGENCY_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	urgency_cntl = dm_read_reg(ctx, urgency_addr);
-+
-+	set_reg_field_value(
-+		urgency_cntl,
-+		marks_low.a_mark,
-+		DPGV0_PIPE_URGENCY_CONTROL,
-+		URGENCY_LOW_WATERMARK);
-+
-+	set_reg_field_value(
-+		urgency_cntl,
-+		total_dest_line_time_ns,
-+		DPGV0_PIPE_URGENCY_CONTROL,
-+		URGENCY_HIGH_WATERMARK);
-+	dm_write_reg(ctx, urgency_addr, urgency_cntl);
-+
-+	/*Write mask to enable reading/writing of watermark set B*/
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+			2,
-+			DPGV0_WATERMARK_MASK_CONTROL,
-+			URGENCY_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	urgency_cntl = dm_read_reg(ctx, urgency_addr);
-+
-+	set_reg_field_value(urgency_cntl,
-+		marks_low.b_mark,
-+		DPGV0_PIPE_URGENCY_CONTROL,
-+		URGENCY_LOW_WATERMARK);
-+
-+	set_reg_field_value(urgency_cntl,
-+		total_dest_line_time_ns,
-+		DPGV0_PIPE_URGENCY_CONTROL,
-+		URGENCY_HIGH_WATERMARK);
-+
-+	dm_write_reg(ctx, urgency_addr, urgency_cntl);
-+}
-+
-+static void program_urgency_watermark_l(
-+	const struct dc_context *ctx,
-+	struct dce_watermarks marks_low,
-+	uint32_t total_dest_line_time_ns)
-+{
-+	program_urgency_watermark(
-+		ctx,
-+		mmDPGV0_PIPE_URGENCY_CONTROL,
-+		mmDPGV0_WATERMARK_MASK_CONTROL,
-+		marks_low,
-+		total_dest_line_time_ns);
-+}
-+
-+static void program_urgency_watermark_c(
-+	const struct dc_context *ctx,
-+	struct dce_watermarks marks_low,
-+	uint32_t total_dest_line_time_ns)
-+{
-+	program_urgency_watermark(
-+		ctx,
-+		mmDPGV1_PIPE_URGENCY_CONTROL,
-+		mmDPGV1_WATERMARK_MASK_CONTROL,
-+		marks_low,
-+		total_dest_line_time_ns);
-+}
-+
-+static void program_stutter_watermark(
-+	const struct dc_context *ctx,
-+	const uint32_t stutter_addr,
-+	const uint32_t wm_addr,
-+	struct dce_watermarks marks)
-+{
-+	/* register value */
-+	uint32_t stutter_cntl = 0;
-+	uint32_t wm_mask_cntl = 0;
-+
-+	/*Write mask to enable reading/writing of watermark set A*/
-+
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+		1,
-+		DPGV0_WATERMARK_MASK_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	stutter_cntl = dm_read_reg(ctx, stutter_addr);
-+
-+	if (ctx->dc->debug.disable_stutter) {
-+		set_reg_field_value(stutter_cntl,
-+			0,
-+			DPGV0_PIPE_STUTTER_CONTROL,
-+			STUTTER_ENABLE);
-+	} else {
-+		set_reg_field_value(stutter_cntl,
-+			1,
-+			DPGV0_PIPE_STUTTER_CONTROL,
-+			STUTTER_ENABLE);
-+	}
-+
-+	set_reg_field_value(stutter_cntl,
-+		1,
-+		DPGV0_PIPE_STUTTER_CONTROL,
-+		STUTTER_IGNORE_FBC);
-+
-+	/*Write watermark set A*/
-+	set_reg_field_value(stutter_cntl,
-+		marks.a_mark,
-+		DPGV0_PIPE_STUTTER_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK);
-+	dm_write_reg(ctx, stutter_addr, stutter_cntl);
-+
-+	/*Write mask to enable reading/writing of watermark set B*/
-+	wm_mask_cntl = dm_read_reg(ctx, wm_addr);
-+	set_reg_field_value(wm_mask_cntl,
-+		2,
-+		DPGV0_WATERMARK_MASK_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_addr, wm_mask_cntl);
-+
-+	stutter_cntl = dm_read_reg(ctx, stutter_addr);
-+	/*Write watermark set B*/
-+	set_reg_field_value(stutter_cntl,
-+		marks.b_mark,
-+		DPGV0_PIPE_STUTTER_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK);
-+	dm_write_reg(ctx, stutter_addr, stutter_cntl);
-+}
-+
-+static void program_stutter_watermark_l(
-+	const struct dc_context *ctx,
-+	struct dce_watermarks marks)
-+{
-+	program_stutter_watermark(ctx,
-+			mmDPGV0_PIPE_STUTTER_CONTROL,
-+			mmDPGV0_WATERMARK_MASK_CONTROL,
-+			marks);
-+}
-+
-+static void program_stutter_watermark_c(
-+	const struct dc_context *ctx,
-+	struct dce_watermarks marks)
-+{
-+	program_stutter_watermark(ctx,
-+			mmDPGV1_PIPE_STUTTER_CONTROL,
-+			mmDPGV1_WATERMARK_MASK_CONTROL,
-+			marks);
-+}
-+
-+static void program_nbp_watermark(
-+	const struct dc_context *ctx,
-+	const uint32_t wm_mask_ctrl_addr,
-+	const uint32_t nbp_pstate_ctrl_addr,
-+	struct dce_watermarks marks)
-+{
-+	uint32_t value;
-+
-+	/* Write mask to enable reading/writing of watermark set A */
-+
-+	value = dm_read_reg(ctx, wm_mask_ctrl_addr);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_WATERMARK_MASK_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_mask_ctrl_addr, value);
-+
-+	value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_ENABLE);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
-+	dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
-+
-+	/* Write watermark set A */
-+	value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
-+	set_reg_field_value(
-+		value,
-+		marks.a_mark,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK);
-+	dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
-+
-+	/* Write mask to enable reading/writing of watermark set B */
-+	value = dm_read_reg(ctx, wm_mask_ctrl_addr);
-+	set_reg_field_value(
-+		value,
-+		2,
-+		DPGV0_WATERMARK_MASK_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK_MASK);
-+	dm_write_reg(ctx, wm_mask_ctrl_addr, value);
-+
-+	value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_ENABLE);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
-+	dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
-+
-+	/* Write watermark set B */
-+	value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
-+	set_reg_field_value(
-+		value,
-+		marks.b_mark,
-+		DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+		NB_PSTATE_CHANGE_WATERMARK);
-+	dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
-+}
-+
-+static void program_nbp_watermark_l(
-+	const struct dc_context *ctx,
-+	struct dce_watermarks marks)
-+{
-+	program_nbp_watermark(ctx,
-+			mmDPGV0_WATERMARK_MASK_CONTROL,
-+			mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+			marks);
-+}
-+
-+static void program_nbp_watermark_c(
-+	const struct dc_context *ctx,
-+	struct dce_watermarks marks)
-+{
-+	program_nbp_watermark(ctx,
-+			mmDPGV1_WATERMARK_MASK_CONTROL,
-+			mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+			marks);
-+}
-+
-+void dce_mem_input_v_program_display_marks(
-+	struct mem_input *mem_input,
-+	struct dce_watermarks nbp,
-+	struct dce_watermarks stutter,
-+	struct dce_watermarks urgent,
-+	uint32_t total_dest_line_time_ns)
-+{
-+	program_urgency_watermark_l(
-+		mem_input->ctx,
-+		urgent,
-+		total_dest_line_time_ns);
-+
-+	program_nbp_watermark_l(
-+		mem_input->ctx,
-+		nbp);
-+
-+	program_stutter_watermark_l(
-+		mem_input->ctx,
-+		stutter);
-+
-+}
-+
-+void dce_mem_input_program_chroma_display_marks(
-+	struct mem_input *mem_input,
-+	struct dce_watermarks nbp,
-+	struct dce_watermarks stutter,
-+	struct dce_watermarks urgent,
-+	uint32_t total_dest_line_time_ns)
-+{
-+	program_urgency_watermark_c(
-+		mem_input->ctx,
-+		urgent,
-+		total_dest_line_time_ns);
-+
-+	program_nbp_watermark_c(
-+		mem_input->ctx,
-+		nbp);
-+
-+	program_stutter_watermark_c(
-+		mem_input->ctx,
-+		stutter);
-+}
-+
-+void dce110_allocate_mem_input_v(
-+	struct mem_input *mi,
-+	uint32_t h_total,/* for current stream */
-+	uint32_t v_total,/* for current stream */
-+	uint32_t pix_clk_khz,/* for current stream */
-+	uint32_t total_stream_num)
-+{
-+	uint32_t addr;
-+	uint32_t value;
-+	uint32_t pix_dur;
-+	if (pix_clk_khz != 0) {
-+		addr = mmDPGV0_PIPE_ARBITRATION_CONTROL1;
-+		value = dm_read_reg(mi->ctx, addr);
-+		pix_dur = 1000000000ULL / pix_clk_khz;
-+		set_reg_field_value(
-+			value,
-+			pix_dur,
-+			DPGV0_PIPE_ARBITRATION_CONTROL1,
-+			PIXEL_DURATION);
-+		dm_write_reg(mi->ctx, addr, value);
-+
-+		addr = mmDPGV1_PIPE_ARBITRATION_CONTROL1;
-+		value = dm_read_reg(mi->ctx, addr);
-+		pix_dur = 1000000000ULL / pix_clk_khz;
-+		set_reg_field_value(
-+			value,
-+			pix_dur,
-+			DPGV1_PIPE_ARBITRATION_CONTROL1,
-+			PIXEL_DURATION);
-+		dm_write_reg(mi->ctx, addr, value);
-+
-+		addr = mmDPGV0_PIPE_ARBITRATION_CONTROL2;
-+		value = 0x4000800;
-+		dm_write_reg(mi->ctx, addr, value);
-+
-+		addr = mmDPGV1_PIPE_ARBITRATION_CONTROL2;
-+		value = 0x4000800;
-+		dm_write_reg(mi->ctx, addr, value);
-+	}
-+
-+}
-+
-+void dce110_free_mem_input_v(
-+	struct mem_input *mi,
-+	uint32_t total_stream_num)
-+{
-+}
-+
-+static struct mem_input_funcs dce110_mem_input_v_funcs = {
-+	.mem_input_program_display_marks =
-+			dce_mem_input_v_program_display_marks,
-+	.mem_input_program_chroma_display_marks =
-+			dce_mem_input_program_chroma_display_marks,
-+	.allocate_mem_input = dce110_allocate_mem_input_v,
-+	.free_mem_input = dce110_free_mem_input_v,
-+	.mem_input_program_surface_flip_and_addr =
-+			dce_mem_input_v_program_surface_flip_and_addr,
-+	.mem_input_program_pte_vm =
-+			dce_mem_input_v_program_pte_vm,
-+	.mem_input_program_surface_config =
-+			dce_mem_input_v_program_surface_config,
-+	.mem_input_is_flip_pending =
-+			dce_mem_input_v_is_surface_pending
-+};
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+void dce110_mem_input_v_construct(
-+	struct dce_mem_input *dce_mi,
-+	struct dc_context *ctx)
-+{
-+	dce_mi->base.funcs = &dce110_mem_input_v_funcs;
-+	dce_mi->base.ctx = ctx;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h.0130~	2017-12-14 06:39:58.410903564 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.h	2017-12-14 06:39:58.410903564 +0100
-@@ -0,0 +1,35 @@
-+/* Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_MEM_INPUT_V_DCE110_H__
-+#define __DC_MEM_INPUT_V_DCE110_H__
-+
-+#include "mem_input.h"
-+#include "dce/dce_mem_input.h"
-+
-+void dce110_mem_input_v_construct(
-+	struct dce_mem_input *dce_mi,
-+	struct dc_context *ctx);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c.0130~	2017-12-14 06:39:58.410903564 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c	2017-12-14 06:39:58.410903564 +0100
-@@ -0,0 +1,738 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dce110_transform_v.h"
-+#include "basics/conversion.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "dce/dce_11_0_enum.h"
-+
-+enum {
-+	OUTPUT_CSC_MATRIX_SIZE = 12
-+};
-+
-+/* constrast:0 - 2.0, default 1.0 */
-+#define UNDERLAY_CONTRAST_DEFAULT 100
-+#define UNDERLAY_CONTRAST_MAX     200
-+#define UNDERLAY_CONTRAST_MIN       0
-+#define UNDERLAY_CONTRAST_STEP      1
-+#define UNDERLAY_CONTRAST_DIVIDER 100
-+
-+/* Saturation: 0 - 2.0; default 1.0 */
-+#define UNDERLAY_SATURATION_DEFAULT   100 /*1.00*/
-+#define UNDERLAY_SATURATION_MIN         0
-+#define UNDERLAY_SATURATION_MAX       200 /* 2.00 */
-+#define UNDERLAY_SATURATION_STEP        1 /* 0.01 */
-+/*actual max overlay saturation
-+ * value = UNDERLAY_SATURATION_MAX /UNDERLAY_SATURATION_DIVIDER
-+ */
-+
-+/* Hue */
-+#define  UNDERLAY_HUE_DEFAULT      0
-+#define  UNDERLAY_HUE_MIN       -300
-+#define  UNDERLAY_HUE_MAX        300
-+#define  UNDERLAY_HUE_STEP         5
-+#define  UNDERLAY_HUE_DIVIDER   10 /* HW range: -30 ~ +30 */
-+#define UNDERLAY_SATURATION_DIVIDER   100
-+
-+/* Brightness: in DAL usually -.25 ~ .25.
-+ * In MMD is -100 to +100 in 16-235 range; which when scaled to full range is
-+ *  ~-116 to +116. When normalized this is about 0.4566.
-+ * With 100 divider this becomes 46, but we may use another for better precision
-+ * The ideal one is 100/219 ((100/255)*(255/219)),
-+ * i.e. min/max = +-100, divider = 219
-+ * default 0.0
-+ */
-+#define  UNDERLAY_BRIGHTNESS_DEFAULT    0
-+#define  UNDERLAY_BRIGHTNESS_MIN      -46 /* ~116/255 */
-+#define  UNDERLAY_BRIGHTNESS_MAX       46
-+#define  UNDERLAY_BRIGHTNESS_STEP       1 /*  .01 */
-+#define  UNDERLAY_BRIGHTNESS_DIVIDER  100
-+
-+static const struct out_csc_color_matrix global_color_matrix[] = {
-+{ COLOR_SPACE_SRGB,
-+	{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
-+{ COLOR_SPACE_SRGB_LIMITED,
-+	{ 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
-+{ COLOR_SPACE_YCBCR601,
-+	{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
-+		0xF6B9, 0xE00, 0x1000} },
-+{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
-+	0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
-+/* TODO: correct values below */
-+{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
-+	0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
-+{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
-+	0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
-+};
-+
-+enum csc_color_mode {
-+	/* 00 - BITS2:0 Bypass */
-+	CSC_COLOR_MODE_GRAPHICS_BYPASS,
-+	/* 01 - hard coded coefficient TV RGB */
-+	CSC_COLOR_MODE_GRAPHICS_PREDEFINED,
-+	/* 04 - programmable OUTPUT CSC coefficient */
-+	CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC,
-+};
-+
-+enum grph_color_adjust_option {
-+	GRPH_COLOR_MATRIX_HW_DEFAULT = 1,
-+	GRPH_COLOR_MATRIX_SW
-+};
-+
-+static void program_color_matrix_v(
-+	struct dce_transform *xfm_dce,
-+	const struct out_csc_color_matrix *tbl_entry,
-+	enum grph_color_adjust_option options)
-+{
-+	struct dc_context *ctx = xfm_dce->base.ctx;
-+	uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL);
-+	bool use_set_a = (get_reg_field_value(cntl_value,
-+			COL_MAN_OUTPUT_CSC_CONTROL,
-+			OUTPUT_CSC_MODE) != 4);
-+
-+	set_reg_field_value(
-+			cntl_value,
-+		0,
-+		COL_MAN_OUTPUT_CSC_CONTROL,
-+		OUTPUT_CSC_MODE);
-+
-+	if (use_set_a) {
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C11_C12_A;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[0],
-+				OUTPUT_CSC_C11_C12_A,
-+				OUTPUT_CSC_C11_A);
-+
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[1],
-+				OUTPUT_CSC_C11_C12_A,
-+				OUTPUT_CSC_C12_A);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C13_C14_A;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[2],
-+				OUTPUT_CSC_C13_C14_A,
-+				OUTPUT_CSC_C13_A);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[3],
-+				OUTPUT_CSC_C13_C14_A,
-+				OUTPUT_CSC_C14_A);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C21_C22_A;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[4],
-+				OUTPUT_CSC_C21_C22_A,
-+				OUTPUT_CSC_C21_A);
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[5],
-+				OUTPUT_CSC_C21_C22_A,
-+				OUTPUT_CSC_C22_A);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C23_C24_A;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[6],
-+				OUTPUT_CSC_C23_C24_A,
-+				OUTPUT_CSC_C23_A);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[7],
-+				OUTPUT_CSC_C23_C24_A,
-+				OUTPUT_CSC_C24_A);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C31_C32_A;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[8],
-+				OUTPUT_CSC_C31_C32_A,
-+				OUTPUT_CSC_C31_A);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[9],
-+				OUTPUT_CSC_C31_C32_A,
-+				OUTPUT_CSC_C32_A);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C33_C34_A;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[10],
-+				OUTPUT_CSC_C33_C34_A,
-+				OUTPUT_CSC_C33_A);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[11],
-+				OUTPUT_CSC_C33_C34_A,
-+				OUTPUT_CSC_C34_A);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		set_reg_field_value(
-+			cntl_value,
-+			4,
-+			COL_MAN_OUTPUT_CSC_CONTROL,
-+			OUTPUT_CSC_MODE);
-+	} else {
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C11_C12_B;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[0],
-+				OUTPUT_CSC_C11_C12_B,
-+				OUTPUT_CSC_C11_B);
-+
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[1],
-+				OUTPUT_CSC_C11_C12_B,
-+				OUTPUT_CSC_C12_B);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C13_C14_B;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[2],
-+				OUTPUT_CSC_C13_C14_B,
-+				OUTPUT_CSC_C13_B);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[3],
-+				OUTPUT_CSC_C13_C14_B,
-+				OUTPUT_CSC_C14_B);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C21_C22_B;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[4],
-+				OUTPUT_CSC_C21_C22_B,
-+				OUTPUT_CSC_C21_B);
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[5],
-+				OUTPUT_CSC_C21_C22_B,
-+				OUTPUT_CSC_C22_B);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C23_C24_B;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[6],
-+				OUTPUT_CSC_C23_C24_B,
-+				OUTPUT_CSC_C23_B);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[7],
-+				OUTPUT_CSC_C23_C24_B,
-+				OUTPUT_CSC_C24_B);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C31_C32_B;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[8],
-+				OUTPUT_CSC_C31_C32_B,
-+				OUTPUT_CSC_C31_B);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[9],
-+				OUTPUT_CSC_C31_C32_B,
-+				OUTPUT_CSC_C32_B);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		{
-+			uint32_t value = 0;
-+			uint32_t addr = mmOUTPUT_CSC_C33_C34_B;
-+			/* fixed S2.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[10],
-+				OUTPUT_CSC_C33_C34_B,
-+				OUTPUT_CSC_C33_B);
-+			/* fixed S0.13 format */
-+			set_reg_field_value(
-+				value,
-+				tbl_entry->regval[11],
-+				OUTPUT_CSC_C33_C34_B,
-+				OUTPUT_CSC_C34_B);
-+
-+			dm_write_reg(ctx, addr, value);
-+		}
-+		set_reg_field_value(
-+			cntl_value,
-+			5,
-+			COL_MAN_OUTPUT_CSC_CONTROL,
-+			OUTPUT_CSC_MODE);
-+	}
-+
-+	dm_write_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL, cntl_value);
-+}
-+
-+static bool configure_graphics_mode_v(
-+	struct dce_transform *xfm_dce,
-+	enum csc_color_mode config,
-+	enum graphics_csc_adjust_type csc_adjust_type,
-+	enum dc_color_space color_space)
-+{
-+	struct dc_context *ctx = xfm_dce->base.ctx;
-+	uint32_t addr = mmCOL_MAN_OUTPUT_CSC_CONTROL;
-+	uint32_t value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		COL_MAN_OUTPUT_CSC_CONTROL,
-+		OUTPUT_CSC_MODE);
-+
-+	if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) {
-+		if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC)
-+			return true;
-+
-+		switch (color_space) {
-+		case COLOR_SPACE_SRGB:
-+			/* by pass */
-+			set_reg_field_value(
-+				value,
-+				0,
-+				COL_MAN_OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_MODE);
-+			break;
-+		case COLOR_SPACE_SRGB_LIMITED:
-+			/* not supported for underlay on CZ */
-+			return false;
-+
-+		case COLOR_SPACE_YCBCR601_LIMITED:
-+			/* YCbCr601 */
-+			set_reg_field_value(
-+				value,
-+				2,
-+				COL_MAN_OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_MODE);
-+			break;
-+		case COLOR_SPACE_YCBCR709:
-+		case COLOR_SPACE_YCBCR709_LIMITED:
-+			/* YCbCr709 */
-+			set_reg_field_value(
-+				value,
-+				3,
-+				COL_MAN_OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_MODE);
-+			break;
-+		default:
-+			return false;
-+		}
-+
-+	} else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) {
-+		switch (color_space) {
-+		case COLOR_SPACE_SRGB:
-+			/* by pass */
-+			set_reg_field_value(
-+				value,
-+				0,
-+				COL_MAN_OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_MODE);
-+			break;
-+		case COLOR_SPACE_SRGB_LIMITED:
-+			/* not supported for underlay on CZ */
-+			return false;
-+		case COLOR_SPACE_YCBCR601:
-+		case COLOR_SPACE_YCBCR601_LIMITED:
-+			/* YCbCr601 */
-+			set_reg_field_value(
-+				value,
-+				2,
-+				COL_MAN_OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_MODE);
-+			break;
-+		case COLOR_SPACE_YCBCR709:
-+		case COLOR_SPACE_YCBCR709_LIMITED:
-+			 /* YCbCr709 */
-+			set_reg_field_value(
-+				value,
-+				3,
-+				COL_MAN_OUTPUT_CSC_CONTROL,
-+				OUTPUT_CSC_MODE);
-+			break;
-+		default:
-+			return false;
-+		}
-+
-+	} else
-+		/* by pass */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			COL_MAN_OUTPUT_CSC_CONTROL,
-+			OUTPUT_CSC_MODE);
-+
-+	addr = mmCOL_MAN_OUTPUT_CSC_CONTROL;
-+	dm_write_reg(ctx, addr, value);
-+
-+	return true;
-+}
-+
-+/*TODO: color depth is not correct when this is called*/
-+static void set_Denormalization(struct transform *xfm,
-+		enum dc_color_depth color_depth)
-+{
-+	uint32_t value = dm_read_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL);
-+
-+	switch (color_depth) {
-+	case COLOR_DEPTH_888:
-+		/* 255/256 for 8 bit output color depth */
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DENORM_CLAMP_CONTROL,
-+			DENORM_MODE);
-+		break;
-+	case COLOR_DEPTH_101010:
-+		/* 1023/1024 for 10 bit output color depth */
-+		set_reg_field_value(
-+			value,
-+			2,
-+			DENORM_CLAMP_CONTROL,
-+			DENORM_MODE);
-+		break;
-+	case COLOR_DEPTH_121212:
-+		/* 4095/4096 for 12 bit output color depth */
-+		set_reg_field_value(
-+			value,
-+			3,
-+			DENORM_CLAMP_CONTROL,
-+			DENORM_MODE);
-+		break;
-+	default:
-+		/* not valid case */
-+		break;
-+	}
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DENORM_CLAMP_CONTROL,
-+		DENORM_10BIT_OUT);
-+
-+	dm_write_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL, value);
-+}
-+
-+struct input_csc_matrix {
-+	enum dc_color_space color_space;
-+	uint32_t regval[12];
-+};
-+
-+static const struct input_csc_matrix input_csc_matrix[] = {
-+	{COLOR_SPACE_SRGB,
-+/*1_1   1_2   1_3   1_4   2_1   2_2   2_3   2_4   3_1   3_2   3_3   3_4 */
-+		{0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
-+	{COLOR_SPACE_SRGB_LIMITED,
-+		{0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
-+	{COLOR_SPACE_YCBCR601,
-+		{0x2cdd, 0x2000, 0x0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef,
-+						0x0, 0x2000, 0x38b4, 0xe3a6} },
-+	{COLOR_SPACE_YCBCR601_LIMITED,
-+		{0x3353, 0x2568, 0x0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108,
-+						0x0, 0x2568, 0x40de, 0xdd3a} },
-+	{COLOR_SPACE_YCBCR709,
-+		{0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
-+						0x2000, 0x3b61, 0xe24f} },
-+	{COLOR_SPACE_YCBCR709_LIMITED,
-+		{0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0,
-+						0x2568, 0x43ee, 0xdbb2} }
-+};
-+
-+static void program_input_csc(
-+		struct transform *xfm, enum dc_color_space color_space)
-+{
-+	int arr_size = sizeof(input_csc_matrix)/sizeof(struct input_csc_matrix);
-+	struct dc_context *ctx = xfm->ctx;
-+	const uint32_t *regval = NULL;
-+	bool use_set_a;
-+	uint32_t value;
-+	int i;
-+
-+	for (i = 0; i < arr_size; i++)
-+		if (input_csc_matrix[i].color_space == color_space) {
-+			regval = input_csc_matrix[i].regval;
-+			break;
-+		}
-+	if (regval == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	/*
-+	 * 1 == set A, the logic is 'if currently we're not using set A,
-+	 * then use set A, otherwise use set B'
-+	 */
-+	value = dm_read_reg(ctx, mmCOL_MAN_INPUT_CSC_CONTROL);
-+	use_set_a = get_reg_field_value(
-+		value, COL_MAN_INPUT_CSC_CONTROL, INPUT_CSC_MODE) != 1;
-+
-+	if (use_set_a) {
-+		/* fixed S2.13 format */
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[0], INPUT_CSC_C11_C12_A, INPUT_CSC_C11_A);
-+		set_reg_field_value(
-+			value, regval[1], INPUT_CSC_C11_C12_A, INPUT_CSC_C12_A);
-+		dm_write_reg(ctx, mmINPUT_CSC_C11_C12_A, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[2], INPUT_CSC_C13_C14_A, INPUT_CSC_C13_A);
-+		set_reg_field_value(
-+			value, regval[3], INPUT_CSC_C13_C14_A, INPUT_CSC_C14_A);
-+		dm_write_reg(ctx, mmINPUT_CSC_C13_C14_A, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[4], INPUT_CSC_C21_C22_A, INPUT_CSC_C21_A);
-+		set_reg_field_value(
-+			value, regval[5], INPUT_CSC_C21_C22_A, INPUT_CSC_C22_A);
-+		dm_write_reg(ctx, mmINPUT_CSC_C21_C22_A, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[6], INPUT_CSC_C23_C24_A, INPUT_CSC_C23_A);
-+		set_reg_field_value(
-+			value, regval[7], INPUT_CSC_C23_C24_A, INPUT_CSC_C24_A);
-+		dm_write_reg(ctx, mmINPUT_CSC_C23_C24_A, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[8], INPUT_CSC_C31_C32_A, INPUT_CSC_C31_A);
-+		set_reg_field_value(
-+			value, regval[9], INPUT_CSC_C31_C32_A, INPUT_CSC_C32_A);
-+		dm_write_reg(ctx, mmINPUT_CSC_C31_C32_A, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[10], INPUT_CSC_C33_C34_A, INPUT_CSC_C33_A);
-+		set_reg_field_value(
-+			value, regval[11], INPUT_CSC_C33_C34_A, INPUT_CSC_C34_A);
-+		dm_write_reg(ctx, mmINPUT_CSC_C33_C34_A, value);
-+	} else {
-+		/* fixed S2.13 format */
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[0], INPUT_CSC_C11_C12_B, INPUT_CSC_C11_B);
-+		set_reg_field_value(
-+			value, regval[1], INPUT_CSC_C11_C12_B, INPUT_CSC_C12_B);
-+		dm_write_reg(ctx, mmINPUT_CSC_C11_C12_B, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[2], INPUT_CSC_C13_C14_B, INPUT_CSC_C13_B);
-+		set_reg_field_value(
-+			value, regval[3], INPUT_CSC_C13_C14_B, INPUT_CSC_C14_B);
-+		dm_write_reg(ctx, mmINPUT_CSC_C13_C14_B, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[4], INPUT_CSC_C21_C22_B, INPUT_CSC_C21_B);
-+		set_reg_field_value(
-+			value, regval[5], INPUT_CSC_C21_C22_B, INPUT_CSC_C22_B);
-+		dm_write_reg(ctx, mmINPUT_CSC_C21_C22_B, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[6], INPUT_CSC_C23_C24_B, INPUT_CSC_C23_B);
-+		set_reg_field_value(
-+			value, regval[7], INPUT_CSC_C23_C24_B, INPUT_CSC_C24_B);
-+		dm_write_reg(ctx, mmINPUT_CSC_C23_C24_B, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[8], INPUT_CSC_C31_C32_B, INPUT_CSC_C31_B);
-+		set_reg_field_value(
-+			value, regval[9], INPUT_CSC_C31_C32_B, INPUT_CSC_C32_B);
-+		dm_write_reg(ctx, mmINPUT_CSC_C31_C32_B, value);
-+
-+		value = 0;
-+		set_reg_field_value(
-+			value, regval[10], INPUT_CSC_C33_C34_B, INPUT_CSC_C33_B);
-+		set_reg_field_value(
-+			value, regval[11], INPUT_CSC_C33_C34_B, INPUT_CSC_C34_B);
-+		dm_write_reg(ctx, mmINPUT_CSC_C33_C34_B, value);
-+	}
-+
-+	/* KK: leave INPUT_CSC_CONVERSION_MODE at default */
-+	value = 0;
-+	/*
-+	 * select 8.4 input type instead of default 12.0. From the discussion
-+	 * with HW team, this format depends on the UNP surface format, so for
-+	 * 8-bit we should select 8.4 (4 bits truncated). For 10 it should be
-+	 * 10.2. For Carrizo we only support 8-bit surfaces on underlay pipe
-+	 * so we can always keep this at 8.4 (input_type=2). If the later asics
-+	 * start supporting 10+ bits, we will have a problem: surface
-+	 * programming including UNP_GRPH* is being done in DalISR after this,
-+	 * so either we pass surface format to here, or move this logic to ISR
-+	 */
-+
-+	set_reg_field_value(
-+		value, 2, COL_MAN_INPUT_CSC_CONTROL, INPUT_CSC_INPUT_TYPE);
-+	set_reg_field_value(
-+		value,
-+		use_set_a ? 1 : 2,
-+		COL_MAN_INPUT_CSC_CONTROL,
-+		INPUT_CSC_MODE);
-+
-+	dm_write_reg(ctx, mmCOL_MAN_INPUT_CSC_CONTROL, value);
-+}
-+
-+void dce110_opp_v_set_csc_default(
-+	struct transform *xfm,
-+	const struct default_adjustment *default_adjust)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+	enum csc_color_mode config =
-+			CSC_COLOR_MODE_GRAPHICS_PREDEFINED;
-+
-+	if (default_adjust->force_hw_default == false) {
-+		const struct out_csc_color_matrix *elm;
-+		/* currently parameter not in use */
-+		enum grph_color_adjust_option option =
-+			GRPH_COLOR_MATRIX_HW_DEFAULT;
-+		uint32_t i;
-+		/*
-+		 * HW default false we program locally defined matrix
-+		 * HW default true  we use predefined hw matrix and we
-+		 * do not need to program matrix
-+		 * OEM wants the HW default via runtime parameter.
-+		 */
-+		option = GRPH_COLOR_MATRIX_SW;
-+
-+		for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {
-+			elm = &global_color_matrix[i];
-+			if (elm->color_space != default_adjust->out_color_space)
-+				continue;
-+			/* program the matrix with default values from this
-+			 * file
-+			 */
-+			program_color_matrix_v(xfm_dce, elm, option);
-+			config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
-+			break;
-+		}
-+	}
-+
-+	program_input_csc(xfm, default_adjust->in_color_space);
-+
-+	/* configure the what we programmed :
-+	 * 1. Default values from this file
-+	 * 2. Use hardware default from ROM_A and we do not need to program
-+	 * matrix
-+	 */
-+
-+	configure_graphics_mode_v(xfm_dce, config,
-+		default_adjust->csc_adjust_type,
-+		default_adjust->out_color_space);
-+
-+	set_Denormalization(xfm, default_adjust->color_depth);
-+}
-+
-+void dce110_opp_v_set_csc_adjustment(
-+	struct transform *xfm,
-+	const struct out_csc_color_matrix *tbl_entry)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+	enum csc_color_mode config =
-+			CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
-+
-+	program_color_matrix_v(
-+			xfm_dce, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW);
-+
-+	/*  We did everything ,now program DxOUTPUT_CSC_CONTROL */
-+	configure_graphics_mode_v(xfm_dce, config, GRAPHICS_CSC_ADJUST_TYPE_SW,
-+			tbl_entry->color_space);
-+
-+	/*TODO: Check if denormalization is needed*/
-+	/*set_Denormalization(opp, adjust->color_depth);*/
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c.0130~	2017-12-14 06:39:58.410903564 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c	2017-12-14 06:39:58.410903564 +0100
-@@ -0,0 +1,555 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dce110_transform_v.h"
-+
-+static void power_on_lut(struct transform *xfm,
-+	bool power_on, bool inputgamma, bool regamma)
-+{
-+	uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL);
-+	int i;
-+
-+	if (power_on) {
-+		if (inputgamma)
-+			set_reg_field_value(
-+				value,
-+				1,
-+				DCFEV_MEM_PWR_CTRL,
-+				COL_MAN_INPUT_GAMMA_MEM_PWR_DIS);
-+		if (regamma)
-+			set_reg_field_value(
-+				value,
-+				1,
-+				DCFEV_MEM_PWR_CTRL,
-+				COL_MAN_GAMMA_CORR_MEM_PWR_DIS);
-+	} else {
-+		if (inputgamma)
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DCFEV_MEM_PWR_CTRL,
-+				COL_MAN_INPUT_GAMMA_MEM_PWR_DIS);
-+		if (regamma)
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DCFEV_MEM_PWR_CTRL,
-+				COL_MAN_GAMMA_CORR_MEM_PWR_DIS);
-+	}
-+
-+	dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value);
-+
-+	for (i = 0; i < 3; i++) {
-+		value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL);
-+		if (get_reg_field_value(value,
-+				DCFEV_MEM_PWR_CTRL,
-+				COL_MAN_INPUT_GAMMA_MEM_PWR_DIS) &&
-+			get_reg_field_value(value,
-+					DCFEV_MEM_PWR_CTRL,
-+					COL_MAN_GAMMA_CORR_MEM_PWR_DIS))
-+			break;
-+
-+		udelay(2);
-+	}
-+}
-+
-+static void set_bypass_input_gamma(struct dce_transform *xfm_dce)
-+{
-+	uint32_t value;
-+
-+	value = dm_read_reg(xfm_dce->base.ctx,
-+			mmCOL_MAN_INPUT_GAMMA_CONTROL1);
-+
-+	set_reg_field_value(
-+				value,
-+				0,
-+				COL_MAN_INPUT_GAMMA_CONTROL1,
-+				INPUT_GAMMA_MODE);
-+
-+	dm_write_reg(xfm_dce->base.ctx,
-+			mmCOL_MAN_INPUT_GAMMA_CONTROL1, value);
-+}
-+
-+static void configure_regamma_mode(struct dce_transform *xfm_dce, uint32_t mode)
-+{
-+	uint32_t value = 0;
-+
-+	set_reg_field_value(
-+				value,
-+				mode,
-+				GAMMA_CORR_CONTROL,
-+				GAMMA_CORR_MODE);
-+
-+	dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CONTROL, 0);
-+}
-+
-+/*
-+ *****************************************************************************
-+ *  Function: regamma_config_regions_and_segments
-+ *
-+ *     build regamma curve by using predefined hw points
-+ *     uses interface parameters ,like EDID coeff.
-+ *
-+ * @param   : parameters   interface parameters
-+ *  @return void
-+ *
-+ *  @note
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void regamma_config_regions_and_segments(
-+	struct dce_transform *xfm_dce, const struct pwl_params *params)
-+{
-+	const struct gamma_curve *curve;
-+	uint32_t value = 0;
-+
-+	{
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[0].custom_float_x,
-+			GAMMA_CORR_CNTLA_START_CNTL,
-+			GAMMA_CORR_CNTLA_EXP_REGION_START);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			GAMMA_CORR_CNTLA_START_CNTL,
-+			GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT);
-+
-+		dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL,
-+				value);
-+	}
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[0].custom_float_slope,
-+			GAMMA_CORR_CNTLA_SLOPE_CNTL,
-+			GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE);
-+
-+		dm_write_reg(xfm_dce->base.ctx,
-+			mmGAMMA_CORR_CNTLA_SLOPE_CNTL, value);
-+	}
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[1].custom_float_x,
-+			GAMMA_CORR_CNTLA_END_CNTL1,
-+			GAMMA_CORR_CNTLA_EXP_REGION_END);
-+
-+		dm_write_reg(xfm_dce->base.ctx,
-+			mmGAMMA_CORR_CNTLA_END_CNTL1, value);
-+	}
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[1].custom_float_slope,
-+			GAMMA_CORR_CNTLA_END_CNTL2,
-+			GAMMA_CORR_CNTLA_EXP_REGION_END_BASE);
-+
-+		set_reg_field_value(
-+			value,
-+			params->arr_points[1].custom_float_y,
-+			GAMMA_CORR_CNTLA_END_CNTL2,
-+			GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE);
-+
-+		dm_write_reg(xfm_dce->base.ctx,
-+			mmGAMMA_CORR_CNTLA_END_CNTL2, value);
-+	}
-+
-+	curve = params->arr_curve_points;
-+
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_0_1,
-+			GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_0_1,
-+			GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_0_1,
-+			GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_0_1,
-+			GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS);
-+
-+		dm_write_reg(
-+				xfm_dce->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_0_1,
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_2_3,
-+			GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_2_3,
-+			GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_2_3,
-+			GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_2_3,
-+			GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS);
-+
-+		dm_write_reg(xfm_dce->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_2_3,
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_4_5,
-+			GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_4_5,
-+			GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_4_5,
-+			GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_4_5,
-+			GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS);
-+
-+		dm_write_reg(xfm_dce->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_4_5,
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_6_7,
-+			GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_6_7,
-+			GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_6_7,
-+			GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_6_7,
-+			GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS);
-+
-+		dm_write_reg(xfm_dce->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_6_7,
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_8_9,
-+			GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_8_9,
-+			GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_8_9,
-+			GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_8_9,
-+			GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS);
-+
-+		dm_write_reg(xfm_dce->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_8_9,
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_10_11,
-+			GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_10_11,
-+			GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_10_11,
-+			GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_10_11,
-+			GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS);
-+
-+		dm_write_reg(xfm_dce->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_10_11,
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_12_13,
-+			GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_12_13,
-+			GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_12_13,
-+			GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_12_13,
-+			GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS);
-+
-+		dm_write_reg(xfm_dce->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_12_13,
-+			value);
-+	}
-+
-+	curve += 2;
-+	{
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			curve[0].offset,
-+			GAMMA_CORR_CNTLA_REGION_14_15,
-+			GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[0].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_14_15,
-+			GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].offset,
-+			GAMMA_CORR_CNTLA_REGION_14_15,
-+			GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET);
-+
-+		set_reg_field_value(
-+			value,
-+			curve[1].segments_num,
-+			GAMMA_CORR_CNTLA_REGION_14_15,
-+			GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS);
-+
-+		dm_write_reg(xfm_dce->base.ctx,
-+			mmGAMMA_CORR_CNTLA_REGION_14_15,
-+			value);
-+	}
-+}
-+
-+static void program_pwl(struct dce_transform *xfm_dce,
-+		const struct pwl_params *params)
-+{
-+	uint32_t value = 0;
-+
-+	set_reg_field_value(
-+		value,
-+		7,
-+		GAMMA_CORR_LUT_WRITE_EN_MASK,
-+		GAMMA_CORR_LUT_WRITE_EN_MASK);
-+
-+	dm_write_reg(xfm_dce->base.ctx,
-+		mmGAMMA_CORR_LUT_WRITE_EN_MASK, value);
-+
-+	dm_write_reg(xfm_dce->base.ctx,
-+		mmGAMMA_CORR_LUT_INDEX, 0);
-+
-+	/* Program REGAMMA_LUT_DATA */
-+	{
-+		const uint32_t addr = mmGAMMA_CORR_LUT_DATA;
-+		uint32_t i = 0;
-+		const struct pwl_result_data *rgb =
-+				params->rgb_resulted;
-+
-+		while (i != params->hw_points_num) {
-+			dm_write_reg(xfm_dce->base.ctx, addr, rgb->red_reg);
-+			dm_write_reg(xfm_dce->base.ctx, addr, rgb->green_reg);
-+			dm_write_reg(xfm_dce->base.ctx, addr, rgb->blue_reg);
-+
-+			dm_write_reg(xfm_dce->base.ctx, addr,
-+				rgb->delta_red_reg);
-+			dm_write_reg(xfm_dce->base.ctx, addr,
-+				rgb->delta_green_reg);
-+			dm_write_reg(xfm_dce->base.ctx, addr,
-+				rgb->delta_blue_reg);
-+
-+			++rgb;
-+			++i;
-+		}
-+	}
-+}
-+
-+void dce110_opp_program_regamma_pwl_v(
-+	struct transform *xfm,
-+	const struct pwl_params *params)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+
-+	/* Setup regions */
-+	regamma_config_regions_and_segments(xfm_dce, params);
-+
-+	set_bypass_input_gamma(xfm_dce);
-+
-+	/* Power on gamma LUT memory */
-+	power_on_lut(xfm, true, false, true);
-+
-+	/* Program PWL */
-+	program_pwl(xfm_dce, params);
-+
-+	/* program regamma config */
-+	configure_regamma_mode(xfm_dce, 1);
-+
-+	/* Power return to auto back */
-+	power_on_lut(xfm, false, false, true);
-+}
-+
-+void dce110_opp_power_on_regamma_lut_v(
-+	struct transform *xfm,
-+	bool power_on)
-+{
-+	uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DCFEV_MEM_PWR_CTRL,
-+		COL_MAN_GAMMA_CORR_MEM_PWR_FORCE);
-+
-+	set_reg_field_value(
-+		value,
-+		power_on,
-+		DCFEV_MEM_PWR_CTRL,
-+		COL_MAN_GAMMA_CORR_MEM_PWR_DIS);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DCFEV_MEM_PWR_CTRL,
-+		COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE);
-+
-+	set_reg_field_value(
-+		value,
-+		power_on,
-+		DCFEV_MEM_PWR_CTRL,
-+		COL_MAN_INPUT_GAMMA_MEM_PWR_DIS);
-+
-+	dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value);
-+}
-+
-+void dce110_opp_set_regamma_mode_v(
-+	struct transform *xfm,
-+	enum opp_regamma mode)
-+{
-+	// TODO: need to implement the function
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c.0130~	2017-12-14 06:39:58.410903564 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c	2017-12-14 06:39:58.410903564 +0100
-@@ -0,0 +1,54 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dce/dce_opp.h"
-+#include "dce110_opp_v.h"
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+static const struct opp_funcs funcs = {
-+		.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
-+		.opp_destroy = dce110_opp_destroy,
-+		.opp_program_fmt = dce110_opp_program_fmt,
-+		.opp_program_bit_depth_reduction =
-+				dce110_opp_program_bit_depth_reduction
-+};
-+
-+void dce110_opp_v_construct(struct dce110_opp *opp110,
-+	struct dc_context *ctx)
-+{
-+	opp110->base.funcs = &funcs;
-+
-+	opp110->base.ctx = ctx;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h.0130~	2017-12-14 06:39:58.410903564 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h	2017-12-14 06:39:58.410903564 +0100
-@@ -0,0 +1,39 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_OPP_DCE110_V_H__
-+#define __DC_OPP_DCE110_V_H__
-+
-+#include "dc_types.h"
-+#include "opp.h"
-+#include "core_types.h"
-+
-+void dce110_opp_v_construct(struct dce110_opp *opp110,
-+	struct dc_context *ctx);
-+
-+/* underlay callbacks */
-+
-+
-+
-+#endif /* __DC_OPP_DCE110_V_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c.0130~	2017-12-14 06:39:58.411903565 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c	2017-12-14 06:39:58.411903565 +0100
-@@ -0,0 +1,1328 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "link_encoder.h"
-+#include "stream_encoder.h"
-+
-+#include "resource.h"
-+#include "dce110/dce110_resource.h"
-+
-+#include "include/irq_service_interface.h"
-+#include "dce/dce_audio.h"
-+#include "dce110/dce110_timing_generator.h"
-+#include "irq/dce110/irq_service_dce110.h"
-+#include "dce110/dce110_timing_generator_v.h"
-+#include "dce/dce_link_encoder.h"
-+#include "dce/dce_stream_encoder.h"
-+#include "dce/dce_mem_input.h"
-+#include "dce110/dce110_mem_input_v.h"
-+#include "dce/dce_ipp.h"
-+#include "dce/dce_transform.h"
-+#include "dce110/dce110_transform_v.h"
-+#include "dce/dce_opp.h"
-+#include "dce110/dce110_opp_v.h"
-+#include "dce/dce_clocks.h"
-+#include "dce/dce_clock_source.h"
-+#include "dce/dce_hwseq.h"
-+#include "dce110/dce110_hw_sequencer.h"
-+#include "dce/dce_abm.h"
-+#include "dce/dce_dmcu.h"
-+
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+#include "dce110/dce110_compressor.h"
-+#endif
-+
-+#include "reg_helper.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
-+#include "gmc/gmc_8_2_d.h"
-+#include "gmc/gmc_8_2_sh_mask.h"
-+#endif
-+
-+#ifndef mmDP_DPHY_INTERNAL_CTRL
-+	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
-+	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
-+	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
-+	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
-+	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
-+	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
-+	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
-+	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
-+	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
-+	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
-+#endif
-+
-+#ifndef mmBIOS_SCRATCH_2
-+	#define mmBIOS_SCRATCH_2 0x05CB
-+	#define mmBIOS_SCRATCH_6 0x05CF
-+#endif
-+
-+#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
-+	#define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
-+	#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
-+	#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
-+	#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
-+	#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
-+	#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
-+	#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
-+	#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
-+#endif
-+
-+#ifndef mmDP_DPHY_FAST_TRAINING
-+	#define mmDP_DPHY_FAST_TRAINING                         0x4ABC
-+	#define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
-+	#define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
-+	#define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
-+	#define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
-+	#define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
-+	#define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
-+	#define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
-+#endif
-+
-+#ifndef DPHY_RX_FAST_TRAINING_CAPABLE
-+	#define DPHY_RX_FAST_TRAINING_CAPABLE 0x1
-+#endif
-+
-+static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
-+	{
-+		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp =  (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
-+	}
-+};
-+
-+/* set register offset */
-+#define SR(reg_name)\
-+	.reg_name = mm ## reg_name
-+
-+/* set register offset with instance */
-+#define SRI(reg_name, block, id)\
-+	.reg_name = mm ## block ## id ## _ ## reg_name
-+
-+static const struct dce_disp_clk_registers disp_clk_regs = {
-+		CLK_COMMON_REG_LIST_DCE_BASE()
-+};
-+
-+static const struct dce_disp_clk_shift disp_clk_shift = {
-+		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
-+};
-+
-+static const struct dce_disp_clk_mask disp_clk_mask = {
-+		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
-+};
-+
-+static const struct dce_dmcu_registers dmcu_regs = {
-+		DMCU_DCE110_COMMON_REG_LIST()
-+};
-+
-+static const struct dce_dmcu_shift dmcu_shift = {
-+		DMCU_MASK_SH_LIST_DCE110(__SHIFT)
-+};
-+
-+static const struct dce_dmcu_mask dmcu_mask = {
-+		DMCU_MASK_SH_LIST_DCE110(_MASK)
-+};
-+
-+static const struct dce_abm_registers abm_regs = {
-+		ABM_DCE110_COMMON_REG_LIST()
-+};
-+
-+static const struct dce_abm_shift abm_shift = {
-+		ABM_MASK_SH_LIST_DCE110(__SHIFT)
-+};
-+
-+static const struct dce_abm_mask abm_mask = {
-+		ABM_MASK_SH_LIST_DCE110(_MASK)
-+};
-+
-+#define ipp_regs(id)\
-+[id] = {\
-+		IPP_DCE110_REG_LIST_DCE_BASE(id)\
-+}
-+
-+static const struct dce_ipp_registers ipp_regs[] = {
-+		ipp_regs(0),
-+		ipp_regs(1),
-+		ipp_regs(2)
-+};
-+
-+static const struct dce_ipp_shift ipp_shift = {
-+		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
-+};
-+
-+static const struct dce_ipp_mask ipp_mask = {
-+		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
-+};
-+
-+#define transform_regs(id)\
-+[id] = {\
-+		XFM_COMMON_REG_LIST_DCE110(id)\
-+}
-+
-+static const struct dce_transform_registers xfm_regs[] = {
-+		transform_regs(0),
-+		transform_regs(1),
-+		transform_regs(2)
-+};
-+
-+static const struct dce_transform_shift xfm_shift = {
-+		XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-+};
-+
-+static const struct dce_transform_mask xfm_mask = {
-+		XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
-+};
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	AUX_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
-+		aux_regs(0),
-+		aux_regs(1),
-+		aux_regs(2),
-+		aux_regs(3),
-+		aux_regs(4),
-+		aux_regs(5)
-+};
-+
-+#define hpd_regs(id)\
-+[id] = {\
-+	HPD_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
-+		hpd_regs(0),
-+		hpd_regs(1),
-+		hpd_regs(2),
-+		hpd_regs(3),
-+		hpd_regs(4),
-+		hpd_regs(5)
-+};
-+
-+
-+#define link_regs(id)\
-+[id] = {\
-+	LE_DCE110_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_registers link_enc_regs[] = {
-+	link_regs(0),
-+	link_regs(1),
-+	link_regs(2),
-+	link_regs(3),
-+	link_regs(4),
-+	link_regs(5),
-+	link_regs(6),
-+};
-+
-+#define stream_enc_regs(id)\
-+[id] = {\
-+	SE_COMMON_REG_LIST(id),\
-+	.TMDS_CNTL = 0,\
-+}
-+
-+static const struct dce110_stream_enc_registers stream_enc_regs[] = {
-+	stream_enc_regs(0),
-+	stream_enc_regs(1),
-+	stream_enc_regs(2)
-+};
-+
-+static const struct dce_stream_encoder_shift se_shift = {
-+		SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-+};
-+
-+static const struct dce_stream_encoder_mask se_mask = {
-+		SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
-+};
-+
-+#define opp_regs(id)\
-+[id] = {\
-+	OPP_DCE_110_REG_LIST(id),\
-+}
-+
-+static const struct dce_opp_registers opp_regs[] = {
-+	opp_regs(0),
-+	opp_regs(1),
-+	opp_regs(2),
-+	opp_regs(3),
-+	opp_regs(4),
-+	opp_regs(5)
-+};
-+
-+static const struct dce_opp_shift opp_shift = {
-+	OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT)
-+};
-+
-+static const struct dce_opp_mask opp_mask = {
-+	OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK)
-+};
-+
-+#define audio_regs(id)\
-+[id] = {\
-+	AUD_COMMON_REG_LIST(id)\
-+}
-+
-+static const struct dce_audio_registers audio_regs[] = {
-+	audio_regs(0),
-+	audio_regs(1),
-+	audio_regs(2),
-+	audio_regs(3),
-+	audio_regs(4),
-+	audio_regs(5),
-+	audio_regs(6),
-+};
-+
-+static const struct dce_audio_shift audio_shift = {
-+		AUD_COMMON_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct dce_aduio_mask audio_mask = {
-+		AUD_COMMON_MASK_SH_LIST(_MASK)
-+};
-+
-+/* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
-+
-+
-+#define clk_src_regs(id)\
-+[id] = {\
-+	CS_COMMON_REG_LIST_DCE_100_110(id),\
-+}
-+
-+static const struct dce110_clk_src_regs clk_src_regs[] = {
-+	clk_src_regs(0),
-+	clk_src_regs(1),
-+	clk_src_regs(2)
-+};
-+
-+static const struct dce110_clk_src_shift cs_shift = {
-+		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
-+};
-+
-+static const struct dce110_clk_src_mask cs_mask = {
-+		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
-+};
-+
-+static const struct bios_registers bios_regs = {
-+	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
-+};
-+
-+static const struct resource_caps carrizo_resource_cap = {
-+		.num_timing_generator = 3,
-+		.num_video_plane = 1,
-+		.num_audio = 3,
-+		.num_stream_encoder = 3,
-+		.num_pll = 2,
-+};
-+
-+static const struct resource_caps stoney_resource_cap = {
-+		.num_timing_generator = 2,
-+		.num_video_plane = 1,
-+		.num_audio = 3,
-+		.num_stream_encoder = 3,
-+		.num_pll = 2,
-+};
-+
-+#define CTX  ctx
-+#define REG(reg) mm ## reg
-+
-+#ifndef mmCC_DC_HDMI_STRAPS
-+#define mmCC_DC_HDMI_STRAPS 0x4819
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
-+#endif
-+
-+static void read_dce_straps(
-+	struct dc_context *ctx,
-+	struct resource_straps *straps)
-+{
-+	REG_GET_2(CC_DC_HDMI_STRAPS,
-+			HDMI_DISABLE, &straps->hdmi_disable,
-+			AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
-+
-+	REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
-+}
-+
-+static struct audio *create_audio(
-+		struct dc_context *ctx, unsigned int inst)
-+{
-+	return dce_audio_create(ctx, inst,
-+			&audio_regs[inst], &audio_shift, &audio_mask);
-+}
-+
-+static struct timing_generator *dce110_timing_generator_create(
-+		struct dc_context *ctx,
-+		uint32_t instance,
-+		const struct dce110_timing_generator_offsets *offsets)
-+{
-+	struct dce110_timing_generator *tg110 =
-+		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
-+
-+	if (!tg110)
-+		return NULL;
-+
-+	dce110_timing_generator_construct(tg110, ctx, instance, offsets);
-+	return &tg110->base;
-+}
-+
-+static struct stream_encoder *dce110_stream_encoder_create(
-+	enum engine_id eng_id,
-+	struct dc_context *ctx)
-+{
-+	struct dce110_stream_encoder *enc110 =
-+		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
-+					&stream_enc_regs[eng_id],
-+					&se_shift, &se_mask);
-+	return &enc110->base;
-+}
-+
-+#define SRII(reg_name, block, id)\
-+	.reg_name[id] = mm ## block ## id ## _ ## reg_name
-+
-+static const struct dce_hwseq_registers hwseq_stoney_reg = {
-+		HWSEQ_ST_REG_LIST()
-+};
-+
-+static const struct dce_hwseq_registers hwseq_cz_reg = {
-+		HWSEQ_CZ_REG_LIST()
-+};
-+
-+static const struct dce_hwseq_shift hwseq_shift = {
-+		HWSEQ_DCE11_MASK_SH_LIST(__SHIFT),
-+};
-+
-+static const struct dce_hwseq_mask hwseq_mask = {
-+		HWSEQ_DCE11_MASK_SH_LIST(_MASK),
-+};
-+
-+static struct dce_hwseq *dce110_hwseq_create(
-+	struct dc_context *ctx)
-+{
-+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
-+
-+	if (hws) {
-+		hws->ctx = ctx;
-+		hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
-+				&hwseq_stoney_reg : &hwseq_cz_reg;
-+		hws->shifts = &hwseq_shift;
-+		hws->masks = &hwseq_mask;
-+		hws->wa.blnd_crtc_trigger = true;
-+	}
-+	return hws;
-+}
-+
-+static const struct resource_create_funcs res_create_funcs = {
-+	.read_dce_straps = read_dce_straps,
-+	.create_audio = create_audio,
-+	.create_stream_encoder = dce110_stream_encoder_create,
-+	.create_hwseq = dce110_hwseq_create,
-+};
-+
-+#define mi_inst_regs(id) { \
-+	MI_DCE11_REG_LIST(id), \
-+	.MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
-+}
-+static const struct dce_mem_input_registers mi_regs[] = {
-+		mi_inst_regs(0),
-+		mi_inst_regs(1),
-+		mi_inst_regs(2),
-+};
-+
-+static const struct dce_mem_input_shift mi_shifts = {
-+		MI_DCE11_MASK_SH_LIST(__SHIFT),
-+		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
-+};
-+
-+static const struct dce_mem_input_mask mi_masks = {
-+		MI_DCE11_MASK_SH_LIST(_MASK),
-+		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
-+};
-+
-+
-+static struct mem_input *dce110_mem_input_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
-+					       GFP_KERNEL);
-+
-+	if (!dce_mi) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
-+	dce_mi->wa.single_head_rdreq_dmif_limit = 3;
-+	return &dce_mi->base;
-+}
-+
-+static void dce110_transform_destroy(struct transform **xfm)
-+{
-+	kfree(TO_DCE_TRANSFORM(*xfm));
-+	*xfm = NULL;
-+}
-+
-+static struct transform *dce110_transform_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce_transform *transform =
-+		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
-+
-+	if (!transform)
-+		return NULL;
-+
-+	dce_transform_construct(transform, ctx, inst,
-+				&xfm_regs[inst], &xfm_shift, &xfm_mask);
-+	return &transform->base;
-+}
-+
-+static struct input_pixel_processor *dce110_ipp_create(
-+	struct dc_context *ctx, uint32_t inst)
-+{
-+	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
-+
-+	if (!ipp) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dce_ipp_construct(ipp, ctx, inst,
-+			&ipp_regs[inst], &ipp_shift, &ipp_mask);
-+	return &ipp->base;
-+}
-+
-+static const struct encoder_feature_support link_enc_feature = {
-+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
-+		.max_hdmi_pixel_clock = 594000,
-+		.flags.bits.IS_HBR2_CAPABLE = true,
-+		.flags.bits.IS_TPS3_CAPABLE = true,
-+		.flags.bits.IS_YCBCR_CAPABLE = true
-+};
-+
-+static struct link_encoder *dce110_link_encoder_create(
-+	const struct encoder_init_data *enc_init_data)
-+{
-+	struct dce110_link_encoder *enc110 =
-+		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	dce110_link_encoder_construct(enc110,
-+				      enc_init_data,
-+				      &link_enc_feature,
-+				      &link_enc_regs[enc_init_data->transmitter],
-+				      &link_enc_aux_regs[enc_init_data->channel - 1],
-+				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
-+	return &enc110->base;
-+}
-+
-+static struct output_pixel_processor *dce110_opp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce110_opp *opp =
-+		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
-+
-+	if (!opp)
-+		return NULL;
-+
-+	dce110_opp_construct(opp,
-+			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
-+	return &opp->base;
-+}
-+
-+struct clock_source *dce110_clock_source_create(
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id id,
-+	const struct dce110_clk_src_regs *regs,
-+	bool dp_clk_src)
-+{
-+	struct dce110_clk_src *clk_src =
-+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
-+
-+	if (!clk_src)
-+		return NULL;
-+
-+	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
-+			regs, &cs_shift, &cs_mask)) {
-+		clk_src->base.dp_clk_src = dp_clk_src;
-+		return &clk_src->base;
-+	}
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
-+void dce110_clock_source_destroy(struct clock_source **clk_src)
-+{
-+	struct dce110_clk_src *dce110_clk_src;
-+
-+	if (!clk_src)
-+		return;
-+
-+	dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src);
-+
-+	kfree(dce110_clk_src->dp_ss_params);
-+	kfree(dce110_clk_src->hdmi_ss_params);
-+	kfree(dce110_clk_src->dvi_ss_params);
-+
-+	kfree(dce110_clk_src);
-+	*clk_src = NULL;
-+}
-+
-+static void destruct(struct dce110_resource_pool *pool)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < pool->base.pipe_count; i++) {
-+		if (pool->base.opps[i] != NULL)
-+			dce110_opp_destroy(&pool->base.opps[i]);
-+
-+		if (pool->base.transforms[i] != NULL)
-+			dce110_transform_destroy(&pool->base.transforms[i]);
-+
-+		if (pool->base.ipps[i] != NULL)
-+			dce_ipp_destroy(&pool->base.ipps[i]);
-+
-+		if (pool->base.mis[i] != NULL) {
-+			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
-+			pool->base.mis[i] = NULL;
-+		}
-+
-+		if (pool->base.timing_generators[i] != NULL)	{
-+			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
-+			pool->base.timing_generators[i] = NULL;
-+		}
-+	}
-+
-+	for (i = 0; i < pool->base.stream_enc_count; i++) {
-+		if (pool->base.stream_enc[i] != NULL)
-+			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
-+	}
-+
-+	for (i = 0; i < pool->base.clk_src_count; i++) {
-+		if (pool->base.clock_sources[i] != NULL) {
-+			dce110_clock_source_destroy(&pool->base.clock_sources[i]);
-+		}
-+	}
-+
-+	if (pool->base.dp_clock_source != NULL)
-+		dce110_clock_source_destroy(&pool->base.dp_clock_source);
-+
-+	for (i = 0; i < pool->base.audio_count; i++)	{
-+		if (pool->base.audios[i] != NULL) {
-+			dce_aud_destroy(&pool->base.audios[i]);
-+		}
-+	}
-+
-+	if (pool->base.abm != NULL)
-+		dce_abm_destroy(&pool->base.abm);
-+
-+	if (pool->base.dmcu != NULL)
-+		dce_dmcu_destroy(&pool->base.dmcu);
-+
-+	if (pool->base.display_clock != NULL)
-+		dce_disp_clk_destroy(&pool->base.display_clock);
-+
-+	if (pool->base.irqs != NULL) {
-+		dal_irq_service_destroy(&pool->base.irqs);
-+	}
-+}
-+
-+
-+static void get_pixel_clock_parameters(
-+	const struct pipe_ctx *pipe_ctx,
-+	struct pixel_clk_params *pixel_clk_params)
-+{
-+	const struct dc_stream_state *stream = pipe_ctx->stream;
-+
-+	/*TODO: is this halved for YCbCr 420? in that case we might want to move
-+	 * the pixel clock normalization for hdmi up to here instead of doing it
-+	 * in pll_adjust_pix_clk
-+	 */
-+	pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
-+	pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
-+	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
-+	pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
-+	/* TODO: un-hardcode*/
-+	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
-+						LINK_RATE_REF_FREQ_IN_KHZ;
-+	pixel_clk_params->flags.ENABLE_SS = 0;
-+	pixel_clk_params->color_depth =
-+		stream->timing.display_color_depth;
-+	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
-+	pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding ==
-+			PIXEL_ENCODING_YCBCR420);
-+	pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
-+	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
-+		pixel_clk_params->color_depth = COLOR_DEPTH_888;
-+	}
-+	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
-+		pixel_clk_params->requested_pix_clk  = pixel_clk_params->requested_pix_clk / 2;
-+	}
-+}
-+
-+void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
-+{
-+	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
-+	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
-+		pipe_ctx->clock_source,
-+		&pipe_ctx->stream_res.pix_clk_params,
-+		&pipe_ctx->pll_settings);
-+	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
-+			&pipe_ctx->stream->bit_depth_params);
-+	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
-+}
-+
-+static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)
-+{
-+	if (pipe_ctx->pipe_idx != underlay_idx)
-+		return true;
-+	if (!pipe_ctx->plane_state)
-+		return false;
-+	if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
-+		return false;
-+	return true;
-+}
-+
-+static enum dc_status build_mapped_resource(
-+		const struct dc *dc,
-+		struct dc_state *context,
-+		struct dc_stream_state *stream)
-+{
-+	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
-+
-+	if (!pipe_ctx)
-+		return DC_ERROR_UNEXPECTED;
-+
-+	if (!is_surface_pixel_format_supported(pipe_ctx,
-+			dc->res_pool->underlay_pipe_index))
-+		return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
-+
-+	dce110_resource_build_pipe_hw_param(pipe_ctx);
-+
-+	/* TODO: validate audio ASIC caps, encoder */
-+
-+	resource_build_info_frame(pipe_ctx);
-+
-+	return DC_OK;
-+}
-+
-+static bool dce110_validate_bandwidth(
-+	struct dc *dc,
-+	struct dc_state *context)
-+{
-+	bool result = false;
-+
-+	dm_logger_write(
-+		dc->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"%s: start",
-+		__func__);
-+
-+	if (bw_calcs(
-+			dc->ctx,
-+			dc->bw_dceip,
-+			dc->bw_vbios,
-+			context->res_ctx.pipe_ctx,
-+			dc->res_pool->pipe_count,
-+			&context->bw.dce))
-+		result =  true;
-+
-+	if (!result)
-+		dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
-+			"%s: %dx%d@%d Bandwidth validation failed!\n",
-+			__func__,
-+			context->streams[0]->timing.h_addressable,
-+			context->streams[0]->timing.v_addressable,
-+			context->streams[0]->timing.pix_clk_khz);
-+
-+	if (memcmp(&dc->current_state->bw.dce,
-+			&context->bw.dce, sizeof(context->bw.dce))) {
-+		struct log_entry log_entry;
-+		dm_logger_open(
-+			dc->ctx->logger,
-+			&log_entry,
-+			LOG_BANDWIDTH_CALCS);
-+		dm_logger_append(&log_entry, "%s: finish,\n"
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d\n",
-+			__func__,
-+			context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
-+			context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
-+			context->bw.dce.urgent_wm_ns[0].b_mark,
-+			context->bw.dce.urgent_wm_ns[0].a_mark,
-+			context->bw.dce.stutter_exit_wm_ns[0].b_mark,
-+			context->bw.dce.stutter_exit_wm_ns[0].a_mark);
-+		dm_logger_append(&log_entry,
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d\n",
-+			context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
-+			context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
-+			context->bw.dce.urgent_wm_ns[1].b_mark,
-+			context->bw.dce.urgent_wm_ns[1].a_mark,
-+			context->bw.dce.stutter_exit_wm_ns[1].b_mark,
-+			context->bw.dce.stutter_exit_wm_ns[1].a_mark);
-+		dm_logger_append(&log_entry,
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
-+			context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
-+			context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
-+			context->bw.dce.urgent_wm_ns[2].b_mark,
-+			context->bw.dce.urgent_wm_ns[2].a_mark,
-+			context->bw.dce.stutter_exit_wm_ns[2].b_mark,
-+			context->bw.dce.stutter_exit_wm_ns[2].a_mark,
-+			context->bw.dce.stutter_mode_enable);
-+		dm_logger_append(&log_entry,
-+			"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
-+			"sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n",
-+			context->bw.dce.cpuc_state_change_enable,
-+			context->bw.dce.cpup_state_change_enable,
-+			context->bw.dce.nbp_state_change_enable,
-+			context->bw.dce.all_displays_in_sync,
-+			context->bw.dce.dispclk_khz,
-+			context->bw.dce.sclk_khz,
-+			context->bw.dce.sclk_deep_sleep_khz,
-+			context->bw.dce.yclk_khz,
-+			context->bw.dce.blackout_recovery_time_us);
-+		dm_logger_close(&log_entry);
-+	}
-+	return result;
-+}
-+
-+static bool dce110_validate_surface_sets(
-+		struct dc_state *context)
-+{
-+	int i, j;
-+
-+	for (i = 0; i < context->stream_count; i++) {
-+		if (context->stream_status[i].plane_count == 0)
-+			continue;
-+
-+		if (context->stream_status[i].plane_count > 2)
-+			return false;
-+
-+		for (j = 0; j < context->stream_status[i].plane_count; j++) {
-+			struct dc_plane_state *plane =
-+				context->stream_status[i].plane_states[j];
-+
-+			/* underlay validation */
-+			if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-+
-+				if ((plane->src_rect.width > 1920 ||
-+					plane->src_rect.height > 1080))
-+					return false;
-+
-+				/* irrespective of plane format,
-+				 * stream should be RGB encoded
-+				 */
-+				if (context->streams[i]->timing.pixel_encoding
-+						!= PIXEL_ENCODING_RGB)
-+					return false;
-+
-+			}
-+
-+		}
-+	}
-+
-+	return true;
-+}
-+
-+enum dc_status dce110_validate_global(
-+		struct dc *dc,
-+		struct dc_state *context)
-+{
-+	if (!dce110_validate_surface_sets(context))
-+		return DC_FAIL_SURFACE_VALIDATE;
-+
-+	return DC_OK;
-+}
-+
-+static enum dc_status dce110_add_stream_to_ctx(
-+		struct dc *dc,
-+		struct dc_state *new_ctx,
-+		struct dc_stream_state *dc_stream)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+
-+	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
-+
-+	if (result == DC_OK)
-+		result = resource_map_clock_resources(dc, new_ctx, dc_stream);
-+
-+
-+	if (result == DC_OK)
-+		result = build_mapped_resource(dc, new_ctx, dc_stream);
-+
-+	return result;
-+}
-+
-+static enum dc_status dce110_validate_guaranteed(
-+		struct dc *dc,
-+		struct dc_stream_state *dc_stream,
-+		struct dc_state *context)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+
-+	context->streams[0] = dc_stream;
-+	dc_stream_retain(context->streams[0]);
-+	context->stream_count++;
-+
-+	result = resource_map_pool_resources(dc, context, dc_stream);
-+
-+	if (result == DC_OK)
-+		result = resource_map_clock_resources(dc, context, dc_stream);
-+
-+	if (result == DC_OK)
-+		result = build_mapped_resource(dc, context, dc_stream);
-+
-+	if (result == DC_OK) {
-+		validate_guaranteed_copy_streams(
-+				context, dc->caps.max_streams);
-+		result = resource_build_scaling_params_for_context(dc, context);
-+	}
-+
-+	if (result == DC_OK)
-+		if (!dce110_validate_bandwidth(dc, context))
-+			result = DC_FAIL_BANDWIDTH_VALIDATE;
-+
-+	return result;
-+}
-+
-+static struct pipe_ctx *dce110_acquire_underlay(
-+		struct dc_state *context,
-+		const struct resource_pool *pool,
-+		struct dc_stream_state *stream)
-+{
-+	struct dc *dc = stream->ctx->dc;
-+	struct resource_context *res_ctx = &context->res_ctx;
-+	unsigned int underlay_idx = pool->underlay_pipe_index;
-+	struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];
-+
-+	if (res_ctx->pipe_ctx[underlay_idx].stream)
-+		return NULL;
-+
-+	pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];
-+	pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
-+	/*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
-+	pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
-+	pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
-+	pipe_ctx->pipe_idx = underlay_idx;
-+
-+	pipe_ctx->stream = stream;
-+
-+	if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {
-+		struct tg_color black_color = {0};
-+		struct dc_bios *dcb = dc->ctx->dc_bios;
-+
-+		dc->hwss.enable_display_power_gating(
-+				dc,
-+				pipe_ctx->pipe_idx,
-+				dcb, PIPE_GATING_CONTROL_DISABLE);
-+
-+		/*
-+		 * This is for powering on underlay, so crtc does not
-+		 * need to be enabled
-+		 */
-+
-+		pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,
-+				&stream->timing,
-+				false);
-+
-+		pipe_ctx->stream_res.tg->funcs->enable_advanced_request(
-+				pipe_ctx->stream_res.tg,
-+				true,
-+				&stream->timing);
-+
-+		pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
-+				stream->timing.h_total,
-+				stream->timing.v_total,
-+				stream->timing.pix_clk_khz,
-+				context->stream_count);
-+
-+		color_space_to_black_color(dc,
-+				COLOR_SPACE_YCBCR601, &black_color);
-+		pipe_ctx->stream_res.tg->funcs->set_blank_color(
-+				pipe_ctx->stream_res.tg,
-+				&black_color);
-+	}
-+
-+	return pipe_ctx;
-+}
-+
-+static void dce110_destroy_resource_pool(struct resource_pool **pool)
-+{
-+	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
-+
-+	destruct(dce110_pool);
-+	kfree(dce110_pool);
-+	*pool = NULL;
-+}
-+
-+
-+static const struct resource_funcs dce110_res_pool_funcs = {
-+	.destroy = dce110_destroy_resource_pool,
-+	.link_enc_create = dce110_link_encoder_create,
-+	.validate_guaranteed = dce110_validate_guaranteed,
-+	.validate_bandwidth = dce110_validate_bandwidth,
-+	.acquire_idle_pipe_for_layer = dce110_acquire_underlay,
-+	.add_stream_to_ctx = dce110_add_stream_to_ctx,
-+	.validate_global = dce110_validate_global
-+};
-+
-+static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
-+{
-+	struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv),
-+							     GFP_KERNEL);
-+	struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv),
-+						    GFP_KERNEL);
-+	struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv),
-+						   GFP_KERNEL);
-+	struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv),
-+						 GFP_KERNEL);
-+
-+	if ((dce110_tgv == NULL) ||
-+		(dce110_xfmv == NULL) ||
-+		(dce110_miv == NULL) ||
-+		(dce110_oppv == NULL))
-+			return false;
-+
-+	dce110_opp_v_construct(dce110_oppv, ctx);
-+
-+	dce110_timing_generator_v_construct(dce110_tgv, ctx);
-+	dce110_mem_input_v_construct(dce110_miv, ctx);
-+	dce110_transform_v_construct(dce110_xfmv, ctx);
-+
-+	pool->opps[pool->pipe_count] = &dce110_oppv->base;
-+	pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
-+	pool->mis[pool->pipe_count] = &dce110_miv->base;
-+	pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
-+	pool->pipe_count++;
-+
-+	/* update the public caps to indicate an underlay is available */
-+	ctx->dc->caps.max_slave_planes = 1;
-+	ctx->dc->caps.max_slave_planes = 1;
-+
-+	return true;
-+}
-+
-+static void bw_calcs_data_update_from_pplib(struct dc *dc)
-+{
-+	struct dm_pp_clock_levels clks = {0};
-+
-+	/*do system clock*/
-+	dm_pp_get_clock_levels_by_type(
-+			dc->ctx,
-+			DM_PP_CLOCK_TYPE_ENGINE_CLK,
-+			&clks);
-+	/* convert all the clock fro kHz to fix point mHz */
-+	dc->bw_vbios->high_sclk = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels-1], 1000);
-+	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels/8], 1000);
-+	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels*2/8], 1000);
-+	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels*3/8], 1000);
-+	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels*4/8], 1000);
-+	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels*5/8], 1000);
-+	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels*6/8], 1000);
-+	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[0], 1000);
-+	dc->sclk_lvls = clks;
-+
-+	/*do display clock*/
-+	dm_pp_get_clock_levels_by_type(
-+			dc->ctx,
-+			DM_PP_CLOCK_TYPE_DISPLAY_CLK,
-+			&clks);
-+	dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels-1], 1000);
-+	dc->bw_vbios->mid_voltage_max_dispclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels>>1], 1000);
-+	dc->bw_vbios->low_voltage_max_dispclk  = bw_frc_to_fixed(
-+			clks.clocks_in_khz[0], 1000);
-+
-+	/*do memory clock*/
-+	dm_pp_get_clock_levels_by_type(
-+			dc->ctx,
-+			DM_PP_CLOCK_TYPE_MEMORY_CLK,
-+			&clks);
-+
-+	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
-+		clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
-+	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
-+		clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
-+		1000);
-+	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
-+		clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
-+		1000);
-+}
-+
-+const struct resource_caps *dce110_resource_cap(
-+	struct hw_asic_id *asic_id)
-+{
-+	if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
-+		return &stoney_resource_cap;
-+	else
-+		return &carrizo_resource_cap;
-+}
-+
-+static bool construct(
-+	uint8_t num_virtual_links,
-+	struct dc *dc,
-+	struct dce110_resource_pool *pool,
-+	struct hw_asic_id asic_id)
-+{
-+	unsigned int i;
-+	struct dc_context *ctx = dc->ctx;
-+	struct dc_firmware_info info;
-+	struct dc_bios *bp;
-+	struct dm_pp_static_clock_info static_clk_info = {0};
-+
-+	ctx->dc_bios->regs = &bios_regs;
-+
-+	pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
-+	pool->base.funcs = &dce110_res_pool_funcs;
-+
-+	/*************************************************
-+	 *  Resource + asic cap harcoding                *
-+	 *************************************************/
-+
-+	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
-+	pool->base.underlay_pipe_index = pool->base.pipe_count;
-+
-+	dc->caps.max_downscale_ratio = 150;
-+	dc->caps.i2c_speed_in_khz = 100;
-+	dc->caps.max_cursor_size = 128;
-+	dc->caps.is_apu = true;
-+
-+	/*************************************************
-+	 *  Create resources                             *
-+	 *************************************************/
-+
-+	bp = ctx->dc_bios;
-+
-+	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
-+		info.external_clock_source_frequency_for_dp != 0) {
-+		pool->base.dp_clock_source =
-+				dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
-+
-+		pool->base.clock_sources[0] =
-+				dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0,
-+						&clk_src_regs[0], false);
-+		pool->base.clock_sources[1] =
-+				dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1,
-+						&clk_src_regs[1], false);
-+
-+		pool->base.clk_src_count = 2;
-+
-+		/* TODO: find out if CZ support 3 PLLs */
-+	}
-+
-+	if (pool->base.dp_clock_source == NULL) {
-+		dm_error("DC: failed to create dp clock source!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->base.clk_src_count; i++) {
-+		if (pool->base.clock_sources[i] == NULL) {
-+			dm_error("DC: failed to create clock sources!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto res_create_fail;
-+		}
-+	}
-+
-+	pool->base.display_clock = dce110_disp_clk_create(ctx,
-+			&disp_clk_regs,
-+			&disp_clk_shift,
-+			&disp_clk_mask);
-+	if (pool->base.display_clock == NULL) {
-+		dm_error("DC: failed to create display clock!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+	pool->base.dmcu = dce_dmcu_create(ctx,
-+			&dmcu_regs,
-+			&dmcu_shift,
-+			&dmcu_mask);
-+	if (pool->base.dmcu == NULL) {
-+		dm_error("DC: failed to create dmcu!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+	pool->base.abm = dce_abm_create(ctx,
-+			&abm_regs,
-+			&abm_shift,
-+			&abm_mask);
-+	if (pool->base.abm == NULL) {
-+		dm_error("DC: failed to create abm!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+	/* get static clock information for PPLIB or firmware, save
-+	 * max_clock_state
-+	 */
-+	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
-+		pool->base.display_clock->max_clks_state =
-+				static_clk_info.max_clocks_state;
-+
-+	{
-+		struct irq_service_init_data init_data;
-+		init_data.ctx = dc->ctx;
-+		pool->base.irqs = dal_irq_service_dce110_create(&init_data);
-+		if (!pool->base.irqs)
-+			goto res_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->base.pipe_count; i++) {
-+		pool->base.timing_generators[i] = dce110_timing_generator_create(
-+				ctx, i, &dce110_tg_offsets[i]);
-+		if (pool->base.timing_generators[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create tg!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.mis[i] = dce110_mem_input_create(ctx, i);
-+		if (pool->base.mis[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create memory input!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.ipps[i] = dce110_ipp_create(ctx, i);
-+		if (pool->base.ipps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create input pixel processor!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.transforms[i] = dce110_transform_create(ctx, i);
-+		if (pool->base.transforms[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create transform!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.opps[i] = dce110_opp_create(ctx, i);
-+		if (pool->base.opps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create output pixel processor!\n");
-+			goto res_create_fail;
-+		}
-+	}
-+
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+	dc->fbc_compressor = dce110_compressor_create(ctx);
-+
-+
-+
-+#endif
-+	if (!underlay_create(ctx, &pool->base))
-+		goto res_create_fail;
-+
-+	if (!resource_construct(num_virtual_links, dc, &pool->base,
-+			&res_create_funcs))
-+		goto res_create_fail;
-+
-+	/* Create hardware sequencer */
-+	dce110_hw_sequencer_construct(dc);
-+
-+	dc->caps.max_planes =  pool->base.pipe_count;
-+
-+	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
-+
-+	bw_calcs_data_update_from_pplib(dc);
-+
-+	return true;
-+
-+res_create_fail:
-+	destruct(pool);
-+	return false;
-+}
-+
-+struct resource_pool *dce110_create_resource_pool(
-+	uint8_t num_virtual_links,
-+	struct dc *dc,
-+	struct hw_asic_id asic_id)
-+{
-+	struct dce110_resource_pool *pool =
-+		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
-+
-+	if (!pool)
-+		return NULL;
-+
-+	if (construct(num_virtual_links, dc, pool, asic_id))
-+		return &pool->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h.0130~	2017-12-14 06:39:58.411903565 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h	2017-12-14 06:39:58.411903565 +0100
-@@ -0,0 +1,49 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_RESOURCE_DCE110_H__
-+#define __DC_RESOURCE_DCE110_H__
-+
-+#include "core_types.h"
-+
-+struct dc;
-+struct resource_pool;
-+
-+#define TO_DCE110_RES_POOL(pool)\
-+	container_of(pool, struct dce110_resource_pool, base)
-+
-+struct dce110_resource_pool {
-+	struct resource_pool base;
-+};
-+
-+void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx);
-+
-+struct resource_pool *dce110_create_resource_pool(
-+	uint8_t num_virtual_links,
-+	struct dc *dc,
-+	struct hw_asic_id asic_id);
-+
-+#endif /* __DC_RESOURCE_DCE110_H__ */
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c.0130~	2017-12-14 06:39:58.411903565 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c	2017-12-14 06:39:58.411903565 +0100
-@@ -0,0 +1,2139 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dc_types.h"
-+#include "dc_bios_types.h"
-+#include "dc.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/logger_interface.h"
-+#include "dce110_timing_generator.h"
-+
-+#include "timing_generator.h"
-+
-+
-+#define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
-+
-+#define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
-+#define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
-+
-+#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
-+#define DCP_REG(reg) (reg + tg110->offsets.dcp)
-+
-+/* Flowing register offsets are same in files of
-+ * dce/dce_11_0_d.h
-+ * dce/vi_polaris10_p/vi_polaris10_d.h
-+ *
-+ * So we can create dce110 timing generator to use it.
-+ */
-+
-+
-+/*
-+* apply_front_porch_workaround
-+*
-+* This is a workaround for a bug that has existed since R5xx and has not been
-+* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
-+*/
-+static void dce110_timing_generator_apply_front_porch_workaround(
-+	struct timing_generator *tg,
-+	struct dc_crtc_timing *timing)
-+{
-+	if (timing->flags.INTERLACE == 1) {
-+		if (timing->v_front_porch < 2)
-+			timing->v_front_porch = 2;
-+	} else {
-+		if (timing->v_front_porch < 1)
-+			timing->v_front_porch = 1;
-+	}
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: is_in_vertical_blank
-+ *
-+ *  @brief
-+ *     check the current status of CRTC to check if we are in Vertical Blank
-+ *     regioneased" state
-+ *
-+ *  @return
-+ *     true if currently in blank region, false otherwise
-+ *
-+ *****************************************************************************
-+ */
-+static bool dce110_timing_generator_is_in_vertical_blank(
-+		struct timing_generator *tg)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+	uint32_t field = 0;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	addr = CRTC_REG(mmCRTC_STATUS);
-+	value = dm_read_reg(tg->ctx, addr);
-+	field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK);
-+	return field == 1;
-+}
-+
-+void dce110_timing_generator_set_early_control(
-+		struct timing_generator *tg,
-+		uint32_t early_cntl)
-+{
-+	uint32_t regval;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t address = CRTC_REG(mmCRTC_CONTROL);
-+
-+	regval = dm_read_reg(tg->ctx, address);
-+	set_reg_field_value(regval, early_cntl,
-+			CRTC_CONTROL, CRTC_HBLANK_EARLY_CONTROL);
-+	dm_write_reg(tg->ctx, address, regval);
-+}
-+
-+/**
-+ * Enable CRTC
-+ * Enable CRTC - call ASIC Control Object to enable Timing generator.
-+ */
-+bool dce110_timing_generator_enable_crtc(struct timing_generator *tg)
-+{
-+	enum bp_result result;
-+
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t value = 0;
-+
-+	/*
-+	 * 3 is used to make sure V_UPDATE occurs at the beginning of the first
-+	 * line of vertical front porch
-+	 */
-+	set_reg_field_value(
-+		value,
-+		0,
-+		CRTC_MASTER_UPDATE_MODE,
-+		MASTER_UPDATE_MODE);
-+
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
-+
-+	/* TODO: may want this on to catch underflow */
-+	value = 0;
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value);
-+
-+	result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);
-+
-+	return result == BP_RESULT_OK;
-+}
-+
-+void dce110_timing_generator_program_blank_color(
-+		struct timing_generator *tg,
-+		const struct tg_color *black_color)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR);
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		black_color->color_b_cb,
-+		CRTC_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_B_CB);
-+	set_reg_field_value(
-+		value,
-+		black_color->color_g_y,
-+		CRTC_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_G_Y);
-+	set_reg_field_value(
-+		value,
-+		black_color->color_r_cr,
-+		CRTC_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_R_CR);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: disable_stereo
-+ *
-+ *  @brief
-+ *     Disables active stereo on controller
-+ *     Frame Packing need to be disabled in vBlank or when CRTC not running
-+ *****************************************************************************
-+ */
-+#if 0
-+@TODOSTEREO
-+static void disable_stereo(struct timing_generator *tg)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_3D_STRUCTURE_CONTROL);
-+	uint32_t value = 0;
-+	uint32_t test = 0;
-+	uint32_t field = 0;
-+	uint32_t struc_en = 0;
-+	uint32_t struc_stereo_sel_ovr = 0;
-+
-+	value = dm_read_reg(tg->ctx, addr);
-+	struc_en = get_reg_field_value(
-+			value,
-+			CRTC_3D_STRUCTURE_CONTROL,
-+			CRTC_3D_STRUCTURE_EN);
-+
-+	struc_stereo_sel_ovr = get_reg_field_value(
-+			value,
-+			CRTC_3D_STRUCTURE_CONTROL,
-+			CRTC_3D_STRUCTURE_STEREO_SEL_OVR);
-+
-+	/*
-+	 * When disabling Frame Packing in 2 step mode, we need to program both
-+	 * registers at the same frame
-+	 * Programming it in the beginning of VActive makes sure we are ok
-+	 */
-+
-+	if (struc_en != 0 && struc_stereo_sel_ovr == 0) {
-+		tg->funcs->wait_for_vblank(tg);
-+		tg->funcs->wait_for_vactive(tg);
-+	}
-+
-+	value = 0;
-+	dm_write_reg(tg->ctx, addr, value);
-+
-+	addr = tg->regs[IDX_CRTC_STEREO_CONTROL];
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+#endif
-+
-+/**
-+ * disable_crtc - call ASIC Control Object to disable Timing generator.
-+ */
-+bool dce110_timing_generator_disable_crtc(struct timing_generator *tg)
-+{
-+	enum bp_result result;
-+
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, false);
-+
-+	/* Need to make sure stereo is disabled according to the DCE5.0 spec */
-+
-+	/*
-+	 * @TODOSTEREO call this when adding stereo support
-+	 * tg->funcs->disable_stereo(tg);
-+	 */
-+
-+	return result == BP_RESULT_OK;
-+}
-+
-+/**
-+* program_horz_count_by_2
-+* Programs DxCRTC_HORZ_COUNT_BY2_EN - 1 for DVI 30bpp mode, 0 otherwise
-+*
-+*/
-+static void program_horz_count_by_2(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t regval;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	regval = dm_read_reg(tg->ctx,
-+			CRTC_REG(mmCRTC_COUNT_CONTROL));
-+
-+	set_reg_field_value(regval, 0, CRTC_COUNT_CONTROL,
-+			CRTC_HORZ_COUNT_BY2_EN);
-+
-+	if (timing->flags.HORZ_COUNT_BY_TWO)
-+		set_reg_field_value(regval, 1, CRTC_COUNT_CONTROL,
-+					CRTC_HORZ_COUNT_BY2_EN);
-+
-+	dm_write_reg(tg->ctx,
-+			CRTC_REG(mmCRTC_COUNT_CONTROL), regval);
-+}
-+
-+/**
-+ * program_timing_generator
-+ * Program CRTC Timing Registers - DxCRTC_H_*, DxCRTC_V_*, Pixel repetition.
-+ * Call ASIC Control Object to program Timings.
-+ */
-+bool dce110_timing_generator_program_timing_generator(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *dc_crtc_timing)
-+{
-+	enum bp_result result;
-+	struct bp_hw_crtc_timing_parameters bp_params;
-+	struct dc_crtc_timing patched_crtc_timing;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	uint32_t vsync_offset = dc_crtc_timing->v_border_bottom +
-+			dc_crtc_timing->v_front_porch;
-+	uint32_t v_sync_start =dc_crtc_timing->v_addressable + vsync_offset;
-+
-+	uint32_t hsync_offset = dc_crtc_timing->h_border_right +
-+			dc_crtc_timing->h_front_porch;
-+	uint32_t h_sync_start = dc_crtc_timing->h_addressable + hsync_offset;
-+
-+	memset(&bp_params, 0, sizeof(struct bp_hw_crtc_timing_parameters));
-+
-+	/* Due to an asic bug we need to apply the Front Porch workaround prior
-+	 * to programming the timing.
-+	 */
-+
-+	patched_crtc_timing = *dc_crtc_timing;
-+
-+	dce110_timing_generator_apply_front_porch_workaround(tg, &patched_crtc_timing);
-+
-+	bp_params.controller_id = tg110->controller_id;
-+
-+	bp_params.h_total = patched_crtc_timing.h_total;
-+	bp_params.h_addressable =
-+		patched_crtc_timing.h_addressable;
-+	bp_params.v_total = patched_crtc_timing.v_total;
-+	bp_params.v_addressable = patched_crtc_timing.v_addressable;
-+
-+	bp_params.h_sync_start = h_sync_start;
-+	bp_params.h_sync_width = patched_crtc_timing.h_sync_width;
-+	bp_params.v_sync_start = v_sync_start;
-+	bp_params.v_sync_width = patched_crtc_timing.v_sync_width;
-+
-+	/* Set overscan */
-+	bp_params.h_overscan_left =
-+		patched_crtc_timing.h_border_left;
-+	bp_params.h_overscan_right =
-+		patched_crtc_timing.h_border_right;
-+	bp_params.v_overscan_top = patched_crtc_timing.v_border_top;
-+	bp_params.v_overscan_bottom =
-+		patched_crtc_timing.v_border_bottom;
-+
-+	/* Set flags */
-+	if (patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY == 1)
-+		bp_params.flags.HSYNC_POSITIVE_POLARITY = 1;
-+
-+	if (patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY == 1)
-+		bp_params.flags.VSYNC_POSITIVE_POLARITY = 1;
-+
-+	if (patched_crtc_timing.flags.INTERLACE == 1)
-+		bp_params.flags.INTERLACE = 1;
-+
-+	if (patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1)
-+		bp_params.flags.HORZ_COUNT_BY_TWO = 1;
-+
-+	result = tg->bp->funcs->program_crtc_timing(tg->bp, &bp_params);
-+
-+	program_horz_count_by_2(tg, &patched_crtc_timing);
-+
-+	tg110->base.funcs->enable_advanced_request(tg, true, &patched_crtc_timing);
-+
-+	/* Enable stereo - only when we need to pack 3D frame. Other types
-+	 * of stereo handled in explicit call */
-+
-+	return result == BP_RESULT_OK;
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: set_drr
-+ *
-+ *  @brief
-+ *     Program dynamic refresh rate registers m_DxCRTC_V_TOTAL_*.
-+ *
-+ *  @param [in] pHwCrtcTiming: point to H
-+ *  wCrtcTiming struct
-+ *****************************************************************************
-+ */
-+void dce110_timing_generator_set_drr(
-+	struct timing_generator *tg,
-+	const struct drr_params *params)
-+{
-+	/* register values */
-+	uint32_t v_total_min = 0;
-+	uint32_t v_total_max = 0;
-+	uint32_t v_total_cntl = 0;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	uint32_t addr = 0;
-+
-+	addr = CRTC_REG(mmCRTC_V_TOTAL_MIN);
-+	v_total_min = dm_read_reg(tg->ctx, addr);
-+
-+	addr = CRTC_REG(mmCRTC_V_TOTAL_MAX);
-+	v_total_max = dm_read_reg(tg->ctx, addr);
-+
-+	addr = CRTC_REG(mmCRTC_V_TOTAL_CONTROL);
-+	v_total_cntl = dm_read_reg(tg->ctx, addr);
-+
-+	if (params != NULL &&
-+		params->vertical_total_max > 0 &&
-+		params->vertical_total_min > 0) {
-+
-+		set_reg_field_value(v_total_max,
-+				params->vertical_total_max - 1,
-+				CRTC_V_TOTAL_MAX,
-+				CRTC_V_TOTAL_MAX);
-+
-+		set_reg_field_value(v_total_min,
-+				params->vertical_total_min - 1,
-+				CRTC_V_TOTAL_MIN,
-+				CRTC_V_TOTAL_MIN);
-+
-+		set_reg_field_value(v_total_cntl,
-+				1,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_V_TOTAL_MIN_SEL);
-+
-+		set_reg_field_value(v_total_cntl,
-+				1,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_V_TOTAL_MAX_SEL);
-+
-+		set_reg_field_value(v_total_cntl,
-+				0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_FORCE_LOCK_ON_EVENT);
-+		set_reg_field_value(v_total_cntl,
-+				0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_FORCE_LOCK_TO_MASTER_VSYNC);
-+
-+		set_reg_field_value(v_total_cntl,
-+				0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_SET_V_TOTAL_MIN_MASK_EN);
-+
-+		set_reg_field_value(v_total_cntl,
-+				0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_SET_V_TOTAL_MIN_MASK);
-+	} else {
-+		set_reg_field_value(v_total_cntl,
-+			0,
-+			CRTC_V_TOTAL_CONTROL,
-+			CRTC_SET_V_TOTAL_MIN_MASK);
-+		set_reg_field_value(v_total_min,
-+				0,
-+				CRTC_V_TOTAL_MIN,
-+				CRTC_V_TOTAL_MIN);
-+		set_reg_field_value(v_total_max,
-+				0,
-+				CRTC_V_TOTAL_MAX,
-+				CRTC_V_TOTAL_MAX);
-+		set_reg_field_value(v_total_cntl,
-+				0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_V_TOTAL_MIN_SEL);
-+		set_reg_field_value(v_total_cntl,
-+				0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_V_TOTAL_MAX_SEL);
-+		set_reg_field_value(v_total_cntl,
-+				0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_FORCE_LOCK_ON_EVENT);
-+		set_reg_field_value(v_total_cntl,
-+				0,
-+				CRTC_V_TOTAL_CONTROL,
-+				CRTC_FORCE_LOCK_TO_MASTER_VSYNC);
-+	}
-+
-+	addr = CRTC_REG(mmCRTC_V_TOTAL_MIN);
-+	dm_write_reg(tg->ctx, addr, v_total_min);
-+
-+	addr = CRTC_REG(mmCRTC_V_TOTAL_MAX);
-+	dm_write_reg(tg->ctx, addr, v_total_max);
-+
-+	addr = CRTC_REG(mmCRTC_V_TOTAL_CONTROL);
-+	dm_write_reg(tg->ctx, addr, v_total_cntl);
-+}
-+
-+void dce110_timing_generator_set_static_screen_control(
-+	struct timing_generator *tg,
-+	uint32_t value)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t static_screen_cntl = 0;
-+	uint32_t addr = 0;
-+
-+	addr = CRTC_REG(mmCRTC_STATIC_SCREEN_CONTROL);
-+	static_screen_cntl = dm_read_reg(tg->ctx, addr);
-+
-+	set_reg_field_value(static_screen_cntl,
-+				value,
-+				CRTC_STATIC_SCREEN_CONTROL,
-+				CRTC_STATIC_SCREEN_EVENT_MASK);
-+
-+	set_reg_field_value(static_screen_cntl,
-+				2,
-+				CRTC_STATIC_SCREEN_CONTROL,
-+				CRTC_STATIC_SCREEN_FRAME_COUNT);
-+
-+	dm_write_reg(tg->ctx, addr, static_screen_cntl);
-+}
-+
-+/*
-+ * get_vblank_counter
-+ *
-+ * @brief
-+ * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
-+ * holds the counter of frames.
-+ *
-+ * @param
-+ * struct timing_generator *tg - [in] timing generator which controls the
-+ * desired CRTC
-+ *
-+ * @return
-+ * Counter of frames, which should equal to number of vblanks.
-+ */
-+uint32_t dce110_timing_generator_get_vblank_counter(struct timing_generator *tg)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_STATUS_FRAME_COUNT);
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+	uint32_t field = get_reg_field_value(
-+			value, CRTC_STATUS_FRAME_COUNT, CRTC_FRAME_COUNT);
-+
-+	return field;
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dce110_timing_generator_get_position
-+ *
-+ *  @brief
-+ *     Returns CRTC vertical/horizontal counters
-+ *
-+ *  @param [out] position
-+ *****************************************************************************
-+ */
-+void dce110_timing_generator_get_position(struct timing_generator *tg,
-+	struct crtc_position *position)
-+{
-+	uint32_t value;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_STATUS_POSITION));
-+
-+	position->horizontal_count = get_reg_field_value(
-+			value,
-+			CRTC_STATUS_POSITION,
-+			CRTC_HORZ_COUNT);
-+
-+	position->vertical_count = get_reg_field_value(
-+			value,
-+			CRTC_STATUS_POSITION,
-+			CRTC_VERT_COUNT);
-+
-+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_NOM_VERT_POSITION));
-+
-+	position->nominal_vcount = get_reg_field_value(
-+			value,
-+			CRTC_NOM_VERT_POSITION,
-+			CRTC_VERT_COUNT_NOM);
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: get_crtc_scanoutpos
-+ *
-+ *  @brief
-+ *     Returns CRTC vertical/horizontal counters
-+ *
-+ *  @param [out] vpos, hpos
-+ *****************************************************************************
-+ */
-+void dce110_timing_generator_get_crtc_scanoutpos(
-+	struct timing_generator *tg,
-+	uint32_t *v_blank_start,
-+	uint32_t *v_blank_end,
-+	uint32_t *h_position,
-+	uint32_t *v_position)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	struct crtc_position position;
-+
-+	uint32_t value  = dm_read_reg(tg->ctx,
-+			CRTC_REG(mmCRTC_V_BLANK_START_END));
-+
-+	*v_blank_start = get_reg_field_value(value,
-+					     CRTC_V_BLANK_START_END,
-+					     CRTC_V_BLANK_START);
-+	*v_blank_end = get_reg_field_value(value,
-+					   CRTC_V_BLANK_START_END,
-+					   CRTC_V_BLANK_END);
-+
-+	dce110_timing_generator_get_position(
-+			tg, &position);
-+
-+	*h_position = position.horizontal_count;
-+	*v_position = position.vertical_count;
-+}
-+
-+/* TODO: is it safe to assume that mask/shift of Primary and Underlay
-+ * are the same?
-+ * For example: today CRTC_H_TOTAL == CRTCV_H_TOTAL but is it always
-+ * guaranteed? */
-+void dce110_timing_generator_program_blanking(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t vsync_offset = timing->v_border_bottom +
-+			timing->v_front_porch;
-+	uint32_t v_sync_start =timing->v_addressable + vsync_offset;
-+
-+	uint32_t hsync_offset = timing->h_border_right +
-+			timing->h_front_porch;
-+	uint32_t h_sync_start = timing->h_addressable + hsync_offset;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t value = 0;
-+	uint32_t addr = 0;
-+	uint32_t tmp = 0;
-+
-+	addr = CRTC_REG(mmCRTC_H_TOTAL);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		timing->h_total - 1,
-+		CRTC_H_TOTAL,
-+		CRTC_H_TOTAL);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = CRTC_REG(mmCRTC_V_TOTAL);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		timing->v_total - 1,
-+		CRTC_V_TOTAL,
-+		CRTC_V_TOTAL);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* In case of V_TOTAL_CONTROL is on, make sure V_TOTAL_MAX and
-+	 * V_TOTAL_MIN are equal to V_TOTAL.
-+	 */
-+	addr = CRTC_REG(mmCRTC_V_TOTAL_MAX);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		timing->v_total - 1,
-+		CRTC_V_TOTAL_MAX,
-+		CRTC_V_TOTAL_MAX);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = CRTC_REG(mmCRTC_V_TOTAL_MIN);
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		timing->v_total - 1,
-+		CRTC_V_TOTAL_MIN,
-+		CRTC_V_TOTAL_MIN);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = CRTC_REG(mmCRTC_H_BLANK_START_END);
-+	value = dm_read_reg(ctx, addr);
-+
-+	tmp = timing->h_total -
-+		(h_sync_start + timing->h_border_left);
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTC_H_BLANK_START_END,
-+		CRTC_H_BLANK_END);
-+
-+	tmp = tmp + timing->h_addressable +
-+		timing->h_border_left + timing->h_border_right;
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTC_H_BLANK_START_END,
-+		CRTC_H_BLANK_START);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = CRTC_REG(mmCRTC_V_BLANK_START_END);
-+	value = dm_read_reg(ctx, addr);
-+
-+	tmp = timing->v_total - (v_sync_start + timing->v_border_top);
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTC_V_BLANK_START_END,
-+		CRTC_V_BLANK_END);
-+
-+	tmp = tmp + timing->v_addressable + timing->v_border_top +
-+		timing->v_border_bottom;
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTC_V_BLANK_START_END,
-+		CRTC_V_BLANK_START);
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+void dce110_timing_generator_set_test_pattern(
-+	struct timing_generator *tg,
-+	/* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
-+	 * because this is not DP-specific (which is probably somewhere in DP
-+	 * encoder) */
-+	enum controller_dp_test_pattern test_pattern,
-+	enum dc_color_depth color_depth)
-+{
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t value;
-+	uint32_t addr;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	enum test_pattern_color_format bit_depth;
-+	enum test_pattern_dyn_range dyn_range;
-+	enum test_pattern_mode mode;
-+	/* color ramp generator mixes 16-bits color */
-+	uint32_t src_bpc = 16;
-+	/* requested bpc */
-+	uint32_t dst_bpc;
-+	uint32_t index;
-+	/* RGB values of the color bars.
-+	 * Produce two RGB colors: RGB0 - white (all Fs)
-+	 * and RGB1 - black (all 0s)
-+	 * (three RGB components for two colors)
-+	 */
-+	uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
-+						0x0000, 0x0000};
-+	/* dest color (converted to the specified color format) */
-+	uint16_t dst_color[6];
-+	uint32_t inc_base;
-+
-+	/* translate to bit depth */
-+	switch (color_depth) {
-+	case COLOR_DEPTH_666:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
-+	break;
-+	case COLOR_DEPTH_888:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
-+	break;
-+	case COLOR_DEPTH_101010:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
-+	break;
-+	case COLOR_DEPTH_121212:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
-+	break;
-+	default:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
-+	break;
-+	}
-+
-+	switch (test_pattern) {
-+	case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
-+	case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
-+	{
-+		dyn_range = (test_pattern ==
-+				CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
-+				TEST_PATTERN_DYN_RANGE_CEA :
-+				TEST_PATTERN_DYN_RANGE_VESA);
-+		mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
-+		value = 0;
-+		addr = CRTC_REG(mmCRTC_TEST_PATTERN_PARAMETERS);
-+
-+		set_reg_field_value(
-+			value,
-+			6,
-+			CRTC_TEST_PATTERN_PARAMETERS,
-+			CRTC_TEST_PATTERN_VRES);
-+		set_reg_field_value(
-+			value,
-+			6,
-+			CRTC_TEST_PATTERN_PARAMETERS,
-+			CRTC_TEST_PATTERN_HRES);
-+
-+		dm_write_reg(ctx, addr, value);
-+
-+		addr = CRTC_REG(mmCRTC_TEST_PATTERN_CONTROL);
-+		value = 0;
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_EN);
-+
-+		set_reg_field_value(
-+			value,
-+			mode,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_MODE);
-+
-+		set_reg_field_value(
-+			value,
-+			dyn_range,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_DYNAMIC_RANGE);
-+		set_reg_field_value(
-+			value,
-+			bit_depth,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_COLOR_FORMAT);
-+		dm_write_reg(ctx, addr, value);
-+	}
-+	break;
-+
-+	case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
-+	case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
-+	{
-+		mode = (test_pattern ==
-+			CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
-+			TEST_PATTERN_MODE_VERTICALBARS :
-+			TEST_PATTERN_MODE_HORIZONTALBARS);
-+
-+		switch (bit_depth) {
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_6:
-+			dst_bpc = 6;
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_8:
-+			dst_bpc = 8;
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_10:
-+			dst_bpc = 10;
-+		break;
-+		default:
-+			dst_bpc = 8;
-+		break;
-+		}
-+
-+		/* adjust color to the required colorFormat */
-+		for (index = 0; index < 6; index++) {
-+			/* dst = 2^dstBpc * src / 2^srcBpc = src >>
-+			 * (srcBpc - dstBpc);
-+			 */
-+			dst_color[index] =
-+				src_color[index] >> (src_bpc - dst_bpc);
-+		/* CRTC_TEST_PATTERN_DATA has 16 bits,
-+		 * lowest 6 are hardwired to ZERO
-+		 * color bits should be left aligned aligned to MSB
-+		 * XXXXXXXXXX000000 for 10 bit,
-+		 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
-+		 */
-+			dst_color[index] <<= (16 - dst_bpc);
-+		}
-+
-+		value = 0;
-+		addr = CRTC_REG(mmCRTC_TEST_PATTERN_PARAMETERS);
-+		dm_write_reg(ctx, addr, value);
-+
-+		/* We have to write the mask before data, similar to pipeline.
-+		 * For example, for 8 bpc, if we want RGB0 to be magenta,
-+		 * and RGB1 to be cyan,
-+		 * we need to make 7 writes:
-+		 * MASK   DATA
-+		 * 000001 00000000 00000000                     set mask to R0
-+		 * 000010 11111111 00000000     R0 255, 0xFF00, set mask to G0
-+		 * 000100 00000000 00000000     G0 0,   0x0000, set mask to B0
-+		 * 001000 11111111 00000000     B0 255, 0xFF00, set mask to R1
-+		 * 010000 00000000 00000000     R1 0,   0x0000, set mask to G1
-+		 * 100000 11111111 00000000     G1 255, 0xFF00, set mask to B1
-+		 * 100000 11111111 00000000     B1 255, 0xFF00
-+		 *
-+		 * we will make a loop of 6 in which we prepare the mask,
-+		 * then write, then prepare the color for next write.
-+		 * first iteration will write mask only,
-+		 * but each next iteration color prepared in
-+		 * previous iteration will be written within new mask,
-+		 * the last component will written separately,
-+		 * mask is not changing between 6th and 7th write
-+		 * and color will be prepared by last iteration
-+		 */
-+
-+		/* write color, color values mask in CRTC_TEST_PATTERN_MASK
-+		 * is B1, G1, R1, B0, G0, R0
-+		 */
-+		value = 0;
-+		addr = CRTC_REG(mmCRTC_TEST_PATTERN_COLOR);
-+		for (index = 0; index < 6; index++) {
-+			/* prepare color mask, first write PATTERN_DATA
-+			 * will have all zeros
-+			 */
-+			set_reg_field_value(
-+				value,
-+				(1 << index),
-+				CRTC_TEST_PATTERN_COLOR,
-+				CRTC_TEST_PATTERN_MASK);
-+			/* write color component */
-+			dm_write_reg(ctx, addr, value);
-+			/* prepare next color component,
-+			 * will be written in the next iteration
-+			 */
-+			set_reg_field_value(
-+				value,
-+				dst_color[index],
-+				CRTC_TEST_PATTERN_COLOR,
-+				CRTC_TEST_PATTERN_DATA);
-+		}
-+		/* write last color component,
-+		 * it's been already prepared in the loop
-+		 */
-+		dm_write_reg(ctx, addr, value);
-+
-+		/* enable test pattern */
-+		addr = CRTC_REG(mmCRTC_TEST_PATTERN_CONTROL);
-+		value = 0;
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_EN);
-+
-+		set_reg_field_value(
-+			value,
-+			mode,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_MODE);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_DYNAMIC_RANGE);
-+
-+		set_reg_field_value(
-+			value,
-+			bit_depth,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_COLOR_FORMAT);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+	break;
-+
-+	case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
-+	{
-+		mode = (bit_depth ==
-+			TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
-+			TEST_PATTERN_MODE_DUALRAMP_RGB :
-+			TEST_PATTERN_MODE_SINGLERAMP_RGB);
-+
-+		switch (bit_depth) {
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_6:
-+			dst_bpc = 6;
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_8:
-+			dst_bpc = 8;
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_10:
-+			dst_bpc = 10;
-+		break;
-+		default:
-+			dst_bpc = 8;
-+		break;
-+		}
-+
-+		/* increment for the first ramp for one color gradation
-+		 * 1 gradation for 6-bit color is 2^10
-+		 * gradations in 16-bit color
-+		 */
-+		inc_base = (src_bpc - dst_bpc);
-+
-+		value = 0;
-+		addr = CRTC_REG(mmCRTC_TEST_PATTERN_PARAMETERS);
-+
-+		switch (bit_depth) {
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_6:
-+		{
-+			set_reg_field_value(
-+				value,
-+				inc_base,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_INC0);
-+			set_reg_field_value(
-+				value,
-+				0,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_INC1);
-+			set_reg_field_value(
-+				value,
-+				6,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_HRES);
-+			set_reg_field_value(
-+				value,
-+				6,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_VRES);
-+			set_reg_field_value(
-+				value,
-+				0,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_RAMP0_OFFSET);
-+		}
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_8:
-+		{
-+			set_reg_field_value(
-+				value,
-+				inc_base,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_INC0);
-+			set_reg_field_value(
-+				value,
-+				0,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_INC1);
-+			set_reg_field_value(
-+				value,
-+				8,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_HRES);
-+			set_reg_field_value(
-+				value,
-+				6,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_VRES);
-+			set_reg_field_value(
-+				value,
-+				0,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_RAMP0_OFFSET);
-+		}
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_10:
-+		{
-+			set_reg_field_value(
-+				value,
-+				inc_base,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_INC0);
-+			set_reg_field_value(
-+				value,
-+				inc_base + 2,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_INC1);
-+			set_reg_field_value(
-+				value,
-+				8,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_HRES);
-+			set_reg_field_value(
-+				value,
-+				5,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_VRES);
-+			set_reg_field_value(
-+				value,
-+				384 << 6,
-+				CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_RAMP0_OFFSET);
-+		}
-+		break;
-+		default:
-+		break;
-+		}
-+		dm_write_reg(ctx, addr, value);
-+
-+		value = 0;
-+		addr = CRTC_REG(mmCRTC_TEST_PATTERN_COLOR);
-+		dm_write_reg(ctx, addr, value);
-+
-+		/* enable test pattern */
-+		addr = CRTC_REG(mmCRTC_TEST_PATTERN_CONTROL);
-+		value = 0;
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_EN);
-+
-+		set_reg_field_value(
-+			value,
-+			mode,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_MODE);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_DYNAMIC_RANGE);
-+		/* add color depth translation here */
-+		set_reg_field_value(
-+			value,
-+			bit_depth,
-+			CRTC_TEST_PATTERN_CONTROL,
-+			CRTC_TEST_PATTERN_COLOR_FORMAT);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+	break;
-+	case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
-+	{
-+		value = 0;
-+		dm_write_reg(ctx, CRTC_REG(mmCRTC_TEST_PATTERN_CONTROL), value);
-+		dm_write_reg(ctx, CRTC_REG(mmCRTC_TEST_PATTERN_COLOR), value);
-+		dm_write_reg(ctx, CRTC_REG(mmCRTC_TEST_PATTERN_PARAMETERS),
-+				value);
-+	}
-+	break;
-+	default:
-+	break;
-+	}
-+}
-+
-+/**
-+* dce110_timing_generator_validate_timing
-+* The timing generators support a maximum display size of is 8192 x 8192 pixels,
-+* including both active display and blanking periods. Check H Total and V Total.
-+*/
-+bool dce110_timing_generator_validate_timing(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing,
-+	enum signal_type signal)
-+{
-+	uint32_t h_blank;
-+	uint32_t h_back_porch;
-+	uint32_t hsync_offset = timing->h_border_right +
-+			timing->h_front_porch;
-+	uint32_t h_sync_start = timing->h_addressable + hsync_offset;
-+
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	ASSERT(timing != NULL);
-+
-+	if (!timing)
-+		return false;
-+
-+	/* Currently we don't support 3D, so block all 3D timings */
-+	if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE)
-+		return false;
-+
-+	/* Temporarily blocking interlacing mode until it's supported */
-+	if (timing->flags.INTERLACE == 1)
-+		return false;
-+
-+	/* Check maximum number of pixels supported by Timing Generator
-+	 * (Currently will never fail, in order to fail needs display which
-+	 * needs more than 8192 horizontal and
-+	 * more than 8192 vertical total pixels)
-+	 */
-+	if (timing->h_total > tg110->max_h_total ||
-+		timing->v_total > tg110->max_v_total)
-+		return false;
-+
-+	h_blank = (timing->h_total - timing->h_addressable -
-+		timing->h_border_right -
-+		timing->h_border_left);
-+
-+	if (h_blank < tg110->min_h_blank)
-+		return false;
-+
-+	if (timing->h_front_porch < tg110->min_h_front_porch)
-+		return false;
-+
-+	h_back_porch = h_blank - (h_sync_start -
-+		timing->h_addressable -
-+		timing->h_border_right -
-+		timing->h_sync_width);
-+
-+	if (h_back_porch < tg110->min_h_back_porch)
-+		return false;
-+
-+	return true;
-+}
-+
-+/**
-+* Wait till we are at the beginning of VBlank.
-+*/
-+void dce110_timing_generator_wait_for_vblank(struct timing_generator *tg)
-+{
-+	/* We want to catch beginning of VBlank here, so if the first try are
-+	 * in VBlank, we might be very close to Active, in this case wait for
-+	 * another frame
-+	 */
-+	while (dce110_timing_generator_is_in_vertical_blank(tg)) {
-+		if (!dce110_timing_generator_is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+
-+	while (!dce110_timing_generator_is_in_vertical_blank(tg)) {
-+		if (!dce110_timing_generator_is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+}
-+
-+/**
-+* Wait till we are in VActive (anywhere in VActive)
-+*/
-+void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg)
-+{
-+	while (dce110_timing_generator_is_in_vertical_blank(tg)) {
-+		if (!dce110_timing_generator_is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dce110_timing_generator_setup_global_swap_lock
-+ *
-+ *  @brief
-+ *     Setups Global Swap Lock group for current pipe
-+ *     Pipe can join or leave GSL group, become a TimingServer or TimingClient
-+ *
-+ *  @param [in] gsl_params: setup data
-+ *****************************************************************************
-+ */
-+
-+void dce110_timing_generator_setup_global_swap_lock(
-+	struct timing_generator *tg,
-+	const struct dcp_gsl_params *gsl_params)
-+{
-+	uint32_t value;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t address = DCP_REG(mmDCP_GSL_CONTROL);
-+	uint32_t check_point = FLIP_READY_BACK_LOOKUP;
-+
-+	value = dm_read_reg(tg->ctx, address);
-+
-+	/* This pipe will belong to GSL Group zero. */
-+	set_reg_field_value(value,
-+			    1,
-+			    DCP_GSL_CONTROL,
-+			    DCP_GSL0_EN);
-+
-+	set_reg_field_value(value,
-+			    gsl_params->gsl_master == tg->inst,
-+			    DCP_GSL_CONTROL,
-+			    DCP_GSL_MASTER_EN);
-+
-+	set_reg_field_value(value,
-+			    HFLIP_READY_DELAY,
-+			    DCP_GSL_CONTROL,
-+			    DCP_GSL_HSYNC_FLIP_FORCE_DELAY);
-+
-+	/* Keep signal low (pending high) during 6 lines.
-+	 * Also defines minimum interval before re-checking signal. */
-+	set_reg_field_value(value,
-+			    HFLIP_CHECK_DELAY,
-+			    DCP_GSL_CONTROL,
-+			    DCP_GSL_HSYNC_FLIP_CHECK_DELAY);
-+
-+	dm_write_reg(tg->ctx, CRTC_REG(mmDCP_GSL_CONTROL), value);
-+	value = 0;
-+
-+	set_reg_field_value(value,
-+			    gsl_params->gsl_master,
-+			    DCIO_GSL0_CNTL,
-+			    DCIO_GSL0_VSYNC_SEL);
-+
-+	set_reg_field_value(value,
-+			    0,
-+			    DCIO_GSL0_CNTL,
-+			    DCIO_GSL0_TIMING_SYNC_SEL);
-+
-+	set_reg_field_value(value,
-+			    0,
-+			    DCIO_GSL0_CNTL,
-+			    DCIO_GSL0_GLOBAL_UNLOCK_SEL);
-+
-+	dm_write_reg(tg->ctx, CRTC_REG(mmDCIO_GSL0_CNTL), value);
-+
-+
-+	{
-+		uint32_t value_crtc_vtotal;
-+
-+		value_crtc_vtotal = dm_read_reg(tg->ctx,
-+				CRTC_REG(mmCRTC_V_TOTAL));
-+
-+		set_reg_field_value(value,
-+				    0,/* DCP_GSL_PURPOSE_SURFACE_FLIP */
-+				    DCP_GSL_CONTROL,
-+				    DCP_GSL_SYNC_SOURCE);
-+
-+		/* Checkpoint relative to end of frame */
-+		check_point = get_reg_field_value(value_crtc_vtotal,
-+						  CRTC_V_TOTAL,
-+						  CRTC_V_TOTAL);
-+
-+		dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_GSL_WINDOW), 0);
-+	}
-+
-+	set_reg_field_value(value,
-+			    1,
-+			    DCP_GSL_CONTROL,
-+			    DCP_GSL_DELAY_SURFACE_UPDATE_PENDING);
-+
-+	dm_write_reg(tg->ctx, address, value);
-+
-+	/********************************************************************/
-+	address = CRTC_REG(mmCRTC_GSL_CONTROL);
-+
-+	value = dm_read_reg(tg->ctx, address);
-+	set_reg_field_value(value,
-+			    check_point - FLIP_READY_BACK_LOOKUP,
-+			    CRTC_GSL_CONTROL,
-+			    CRTC_GSL_CHECK_LINE_NUM);
-+
-+	set_reg_field_value(value,
-+			    VFLIP_READY_DELAY,
-+			    CRTC_GSL_CONTROL,
-+			    CRTC_GSL_FORCE_DELAY);
-+
-+	dm_write_reg(tg->ctx, address, value);
-+}
-+
-+void dce110_timing_generator_tear_down_global_swap_lock(
-+	struct timing_generator *tg)
-+{
-+	/* Clear all the register writes done by
-+	 * dce110_timing_generator_setup_global_swap_lock
-+	 */
-+
-+	uint32_t value;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t address = DCP_REG(mmDCP_GSL_CONTROL);
-+
-+	value = 0;
-+
-+	/* This pipe will belong to GSL Group zero. */
-+	/* Settig HW default values from reg specs */
-+	set_reg_field_value(value,
-+			0,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL0_EN);
-+
-+	set_reg_field_value(value,
-+			0,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL_MASTER_EN);
-+
-+	set_reg_field_value(value,
-+			0x2,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL_HSYNC_FLIP_FORCE_DELAY);
-+
-+	set_reg_field_value(value,
-+			0x6,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL_HSYNC_FLIP_CHECK_DELAY);
-+
-+	/* Restore DCP_GSL_PURPOSE_SURFACE_FLIP */
-+	{
-+		uint32_t value_crtc_vtotal;
-+
-+		value_crtc_vtotal = dm_read_reg(tg->ctx,
-+				CRTC_REG(mmCRTC_V_TOTAL));
-+
-+		set_reg_field_value(value,
-+				0,
-+				DCP_GSL_CONTROL,
-+				DCP_GSL_SYNC_SOURCE);
-+	}
-+
-+	set_reg_field_value(value,
-+			0,
-+			DCP_GSL_CONTROL,
-+			DCP_GSL_DELAY_SURFACE_UPDATE_PENDING);
-+
-+	dm_write_reg(tg->ctx, address, value);
-+
-+	/********************************************************************/
-+	address = CRTC_REG(mmCRTC_GSL_CONTROL);
-+
-+	value = 0;
-+	set_reg_field_value(value,
-+			0,
-+			CRTC_GSL_CONTROL,
-+			CRTC_GSL_CHECK_LINE_NUM);
-+
-+	set_reg_field_value(value,
-+			0x2,
-+			CRTC_GSL_CONTROL,
-+			CRTC_GSL_FORCE_DELAY);
-+
-+	dm_write_reg(tg->ctx, address, value);
-+}
-+/**
-+ *****************************************************************************
-+ *  Function: is_counter_moving
-+ *
-+ *  @brief
-+ *     check if the timing generator is currently going
-+ *
-+ *  @return
-+ *     true if currently going, false if currently paused or stopped.
-+ *
-+ *****************************************************************************
-+ */
-+bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg)
-+{
-+	struct crtc_position position1, position2;
-+
-+	tg->funcs->get_position(tg, &position1);
-+	tg->funcs->get_position(tg, &position2);
-+
-+	if (position1.horizontal_count == position2.horizontal_count &&
-+		position1.vertical_count == position2.vertical_count)
-+		return false;
-+	else
-+		return true;
-+}
-+
-+void dce110_timing_generator_enable_advanced_request(
-+	struct timing_generator *tg,
-+	bool enable,
-+	const struct dc_crtc_timing *timing)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	if (enable) {
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_LEGACY_REQUESTOR_EN);
-+	} else {
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_LEGACY_REQUESTOR_EN);
-+	}
-+
-+	if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
-+		set_reg_field_value(
-+			value,
-+			3,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_ADVANCED_START_LINE_POSITION);
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_PREFETCH_EN);
-+	} else {
-+		set_reg_field_value(
-+			value,
-+			4,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_ADVANCED_START_LINE_POSITION);
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_PREFETCH_EN);
-+	}
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		CRTC_START_LINE_CONTROL,
-+		CRTC_PROGRESSIVE_START_LINE_EARLY);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		CRTC_START_LINE_CONTROL,
-+		CRTC_INTERLACE_START_LINE_EARLY);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+
-+/*TODO: Figure out if we need this function. */
-+void dce110_timing_generator_set_lock_master(struct timing_generator *tg,
-+		bool lock)
-+{
-+	struct dc_context *ctx = tg->ctx;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK);
-+	uint32_t value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		lock ? 1 : 0,
-+		CRTC_MASTER_UPDATE_LOCK,
-+		MASTER_UPDATE_LOCK);
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+void dce110_timing_generator_enable_reset_trigger(
-+	struct timing_generator *tg,
-+	int source_tg_inst)
-+{
-+	uint32_t value;
-+	uint32_t rising_edge = 0;
-+	uint32_t falling_edge = 0;
-+	enum trigger_source_select trig_src_select = TRIGGER_SOURCE_SELECT_LOGIC_ZERO;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	/* Setup trigger edge */
-+	{
-+		uint32_t pol_value = dm_read_reg(tg->ctx,
-+				CRTC_REG(mmCRTC_V_SYNC_A_CNTL));
-+
-+		/* Register spec has reversed definition:
-+		 *	0 for positive, 1 for negative */
-+		if (get_reg_field_value(pol_value,
-+				CRTC_V_SYNC_A_CNTL,
-+				CRTC_V_SYNC_A_POL) == 0) {
-+			rising_edge = 1;
-+		} else {
-+			falling_edge = 1;
-+		}
-+	}
-+
-+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL));
-+
-+	trig_src_select = TRIGGER_SOURCE_SELECT_GSL_GROUP0;
-+
-+	set_reg_field_value(value,
-+			trig_src_select,
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_SOURCE_SELECT);
-+
-+	set_reg_field_value(value,
-+			TRIGGER_POLARITY_SELECT_LOGIC_ZERO,
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_POLARITY_SELECT);
-+
-+	set_reg_field_value(value,
-+			rising_edge,
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_RISING_EDGE_DETECT_CNTL);
-+
-+	set_reg_field_value(value,
-+			falling_edge,
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL);
-+
-+	set_reg_field_value(value,
-+			0, /* send every signal */
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_FREQUENCY_SELECT);
-+
-+	set_reg_field_value(value,
-+			0, /* no delay */
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_DELAY);
-+
-+	set_reg_field_value(value,
-+			1, /* clear trigger status */
-+			CRTC_TRIGB_CNTL,
-+			CRTC_TRIGB_CLEAR);
-+
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value);
-+
-+	/**************************************************************/
-+
-+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
-+
-+	set_reg_field_value(value,
-+			2, /* force H count to H_TOTAL and V count to V_TOTAL */
-+			CRTC_FORCE_COUNT_NOW_CNTL,
-+			CRTC_FORCE_COUNT_NOW_MODE);
-+
-+	set_reg_field_value(value,
-+			1, /* TriggerB - we never use TriggerA */
-+			CRTC_FORCE_COUNT_NOW_CNTL,
-+			CRTC_FORCE_COUNT_NOW_TRIG_SEL);
-+
-+	set_reg_field_value(value,
-+			1, /* clear trigger status */
-+			CRTC_FORCE_COUNT_NOW_CNTL,
-+			CRTC_FORCE_COUNT_NOW_CLEAR);
-+
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
-+}
-+
-+void dce110_timing_generator_enable_crtc_reset(
-+		struct timing_generator *tg,
-+		int source_tg_inst,
-+		struct crtc_trigger_info *crtc_tp)
-+{
-+	uint32_t value = 0;
-+	uint32_t rising_edge = 0;
-+	uint32_t falling_edge = 0;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	/* Setup trigger edge */
-+	switch (crtc_tp->event) {
-+	case CRTC_EVENT_VSYNC_RISING:
-+			rising_edge = 1;
-+			break;
-+
-+	case CRTC_EVENT_VSYNC_FALLING:
-+		falling_edge = 1;
-+		break;
-+	}
-+
-+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL));
-+
-+	set_reg_field_value(value,
-+			    source_tg_inst,
-+			    CRTC_TRIGB_CNTL,
-+			    CRTC_TRIGB_SOURCE_SELECT);
-+
-+	set_reg_field_value(value,
-+			    TRIGGER_POLARITY_SELECT_LOGIC_ZERO,
-+			    CRTC_TRIGB_CNTL,
-+			    CRTC_TRIGB_POLARITY_SELECT);
-+
-+	set_reg_field_value(value,
-+			    rising_edge,
-+			    CRTC_TRIGB_CNTL,
-+			    CRTC_TRIGB_RISING_EDGE_DETECT_CNTL);
-+
-+	set_reg_field_value(value,
-+			    falling_edge,
-+			    CRTC_TRIGB_CNTL,
-+			    CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL);
-+
-+	set_reg_field_value(value,
-+			    1, /* clear trigger status */
-+			    CRTC_TRIGB_CNTL,
-+			    CRTC_TRIGB_CLEAR);
-+
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value);
-+
-+	/**************************************************************/
-+
-+	switch (crtc_tp->delay) {
-+	case TRIGGER_DELAY_NEXT_LINE:
-+		value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
-+
-+		set_reg_field_value(value,
-+				    0, /* force H count to H_TOTAL and V count to V_TOTAL */
-+				    CRTC_FORCE_COUNT_NOW_CNTL,
-+				    CRTC_FORCE_COUNT_NOW_MODE);
-+
-+		set_reg_field_value(value,
-+				    0, /* TriggerB - we never use TriggerA */
-+				    CRTC_FORCE_COUNT_NOW_CNTL,
-+				    CRTC_FORCE_COUNT_NOW_TRIG_SEL);
-+
-+		set_reg_field_value(value,
-+				    1, /* clear trigger status */
-+				    CRTC_FORCE_COUNT_NOW_CNTL,
-+				    CRTC_FORCE_COUNT_NOW_CLEAR);
-+
-+		dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
-+
-+		value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL));
-+
-+		set_reg_field_value(value,
-+				    1,
-+				    CRTC_VERT_SYNC_CONTROL,
-+				    CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR);
-+
-+		set_reg_field_value(value,
-+				    2,
-+				    CRTC_VERT_SYNC_CONTROL,
-+				    CRTC_AUTO_FORCE_VSYNC_MODE);
-+
-+		break;
-+
-+	case TRIGGER_DELAY_NEXT_PIXEL:
-+		value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL));
-+
-+		set_reg_field_value(value,
-+				    1,
-+				    CRTC_VERT_SYNC_CONTROL,
-+				    CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR);
-+
-+		set_reg_field_value(value,
-+				    0,
-+				    CRTC_VERT_SYNC_CONTROL,
-+				    CRTC_AUTO_FORCE_VSYNC_MODE);
-+
-+		dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL), value);
-+
-+		value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
-+
-+		set_reg_field_value(value,
-+				    2, /* force H count to H_TOTAL and V count to V_TOTAL */
-+				    CRTC_FORCE_COUNT_NOW_CNTL,
-+				    CRTC_FORCE_COUNT_NOW_MODE);
-+
-+		set_reg_field_value(value,
-+				    1, /* TriggerB - we never use TriggerA */
-+				    CRTC_FORCE_COUNT_NOW_CNTL,
-+				    CRTC_FORCE_COUNT_NOW_TRIG_SEL);
-+
-+		set_reg_field_value(value,
-+				    1, /* clear trigger status */
-+				    CRTC_FORCE_COUNT_NOW_CNTL,
-+				    CRTC_FORCE_COUNT_NOW_CLEAR);
-+
-+		dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
-+		break;
-+	}
-+
-+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE));
-+
-+	set_reg_field_value(value,
-+			    2,
-+			    CRTC_MASTER_UPDATE_MODE,
-+			    MASTER_UPDATE_MODE);
-+
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value);
-+}
-+void dce110_timing_generator_disable_reset_trigger(
-+	struct timing_generator *tg)
-+{
-+	uint32_t value;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
-+
-+	set_reg_field_value(value,
-+			    0, /* force counter now mode is disabled */
-+			    CRTC_FORCE_COUNT_NOW_CNTL,
-+			    CRTC_FORCE_COUNT_NOW_MODE);
-+
-+	set_reg_field_value(value,
-+			    1, /* clear trigger status */
-+			    CRTC_FORCE_COUNT_NOW_CNTL,
-+			    CRTC_FORCE_COUNT_NOW_CLEAR);
-+
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value);
-+
-+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL));
-+
-+	set_reg_field_value(value,
-+			    1,
-+			    CRTC_VERT_SYNC_CONTROL,
-+			    CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR);
-+
-+	set_reg_field_value(value,
-+			    0,
-+			    CRTC_VERT_SYNC_CONTROL,
-+			    CRTC_AUTO_FORCE_VSYNC_MODE);
-+
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL), value);
-+
-+	/********************************************************************/
-+	value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL));
-+
-+	set_reg_field_value(value,
-+			    TRIGGER_SOURCE_SELECT_LOGIC_ZERO,
-+			    CRTC_TRIGB_CNTL,
-+			    CRTC_TRIGB_SOURCE_SELECT);
-+
-+	set_reg_field_value(value,
-+			    TRIGGER_POLARITY_SELECT_LOGIC_ZERO,
-+			    CRTC_TRIGB_CNTL,
-+			    CRTC_TRIGB_POLARITY_SELECT);
-+
-+	set_reg_field_value(value,
-+			    1, /* clear trigger status */
-+			    CRTC_TRIGB_CNTL,
-+			    CRTC_TRIGB_CLEAR);
-+
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value);
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  @brief
-+ *     Checks whether CRTC triggered reset occurred
-+ *
-+ *  @return
-+ *     true if triggered reset occurred, false otherwise
-+ *****************************************************************************
-+ */
-+bool dce110_timing_generator_did_triggered_reset_occur(
-+	struct timing_generator *tg)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t value = dm_read_reg(tg->ctx,
-+			CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL));
-+	uint32_t value1 = dm_read_reg(tg->ctx,
-+			CRTC_REG(mmCRTC_VERT_SYNC_CONTROL));
-+	bool force = get_reg_field_value(value,
-+					 CRTC_FORCE_COUNT_NOW_CNTL,
-+					 CRTC_FORCE_COUNT_NOW_OCCURRED) != 0;
-+	bool vert_sync = get_reg_field_value(value1,
-+					     CRTC_VERT_SYNC_CONTROL,
-+					     CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED) != 0;
-+
-+	return (force || vert_sync);
-+}
-+
-+/**
-+ * dce110_timing_generator_disable_vga
-+ * Turn OFF VGA Mode and Timing  - DxVGA_CONTROL
-+ * VGA Mode and VGA Timing is used by VBIOS on CRT Monitors;
-+ */
-+void dce110_timing_generator_disable_vga(
-+	struct timing_generator *tg)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	switch (tg110->controller_id) {
-+	case CONTROLLER_ID_D0:
-+		addr = mmD1VGA_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D1:
-+		addr = mmD2VGA_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D2:
-+		addr = mmD3VGA_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D3:
-+		addr = mmD4VGA_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D4:
-+		addr = mmD5VGA_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D5:
-+		addr = mmD6VGA_CONTROL;
-+		break;
-+	default:
-+		break;
-+	}
-+	value = dm_read_reg(tg->ctx, addr);
-+
-+	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE);
-+	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT);
-+	set_reg_field_value(
-+			value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT);
-+	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+
-+/**
-+* set_overscan_color_black
-+*
-+* @param :black_color is one of the color space
-+*    :this routine will set overscan black color according to the color space.
-+* @return none
-+*/
-+
-+void dce110_timing_generator_set_overscan_color_black(
-+	struct timing_generator *tg,
-+	const struct tg_color *color)
-+{
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t addr;
-+	uint32_t value = 0;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	set_reg_field_value(
-+			value,
-+			color->color_b_cb,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_BLUE);
-+
-+	set_reg_field_value(
-+			value,
-+			color->color_r_cr,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_RED);
-+
-+	set_reg_field_value(
-+			value,
-+			color->color_g_y,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_GREEN);
-+
-+	addr = CRTC_REG(mmCRTC_OVERSCAN_COLOR);
-+	dm_write_reg(ctx, addr, value);
-+	addr = CRTC_REG(mmCRTC_BLACK_COLOR);
-+	dm_write_reg(ctx, addr, value);
-+	/* This is desirable to have a constant DAC output voltage during the
-+	 * blank time that is higher than the 0 volt reference level that the
-+	 * DAC outputs when the NBLANK signal
-+	 * is asserted low, such as for output to an analog TV. */
-+	addr = CRTC_REG(mmCRTC_BLANK_DATA_COLOR);
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* TO DO we have to program EXT registers and we need to know LB DATA
-+	 * format because it is used when more 10 , i.e. 12 bits per color
-+	 *
-+	 * m_mmDxCRTC_OVERSCAN_COLOR_EXT
-+	 * m_mmDxCRTC_BLACK_COLOR_EXT
-+	 * m_mmDxCRTC_BLANK_DATA_COLOR_EXT
-+	 */
-+
-+}
-+
-+void dce110_tg_program_blank_color(struct timing_generator *tg,
-+		const struct tg_color *black_color)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR);
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		black_color->color_b_cb,
-+		CRTC_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_B_CB);
-+	set_reg_field_value(
-+		value,
-+		black_color->color_g_y,
-+		CRTC_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_G_Y);
-+	set_reg_field_value(
-+		value,
-+		black_color->color_r_cr,
-+		CRTC_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_R_CR);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+
-+	addr = CRTC_REG(mmCRTC_BLANK_DATA_COLOR);
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+
-+void dce110_tg_set_overscan_color(struct timing_generator *tg,
-+	const struct tg_color *overscan_color)
-+{
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t value = 0;
-+	uint32_t addr;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	set_reg_field_value(
-+		value,
-+		overscan_color->color_b_cb,
-+		CRTC_OVERSCAN_COLOR,
-+		CRTC_OVERSCAN_COLOR_BLUE);
-+
-+	set_reg_field_value(
-+		value,
-+		overscan_color->color_g_y,
-+		CRTC_OVERSCAN_COLOR,
-+		CRTC_OVERSCAN_COLOR_GREEN);
-+
-+	set_reg_field_value(
-+		value,
-+		overscan_color->color_r_cr,
-+		CRTC_OVERSCAN_COLOR,
-+		CRTC_OVERSCAN_COLOR_RED);
-+
-+	addr = CRTC_REG(mmCRTC_OVERSCAN_COLOR);
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+void dce110_tg_program_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing,
-+	bool use_vbios)
-+{
-+	if (use_vbios)
-+		dce110_timing_generator_program_timing_generator(tg, timing);
-+	else
-+		dce110_timing_generator_program_blanking(tg, timing);
-+}
-+
-+bool dce110_tg_is_blanked(struct timing_generator *tg)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL));
-+
-+	if (get_reg_field_value(
-+			value,
-+			CRTC_BLANK_CONTROL,
-+			CRTC_BLANK_DATA_EN) == 1 &&
-+		get_reg_field_value(
-+			value,
-+			CRTC_BLANK_CONTROL,
-+			CRTC_CURRENT_BLANK_STATE) == 1)
-+		return true;
-+	return false;
-+}
-+
-+void dce110_tg_set_blank(struct timing_generator *tg,
-+		bool enable_blanking)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t value = 0;
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		CRTC_DOUBLE_BUFFER_CONTROL,
-+		CRTC_BLANK_DATA_DOUBLE_BUFFER_EN);
-+
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_DOUBLE_BUFFER_CONTROL), value);
-+	value = 0;
-+
-+	if (enable_blanking) {
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_BLANK_CONTROL,
-+			CRTC_BLANK_DATA_EN);
-+
-+		dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL), value);
-+
-+	} else
-+		dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_BLANK_CONTROL), 0);
-+}
-+
-+bool dce110_tg_validate_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing)
-+{
-+	return dce110_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE);
-+}
-+
-+void dce110_tg_wait_for_state(struct timing_generator *tg,
-+	enum crtc_state state)
-+{
-+	switch (state) {
-+	case CRTC_STATE_VBLANK:
-+		dce110_timing_generator_wait_for_vblank(tg);
-+		break;
-+
-+	case CRTC_STATE_VACTIVE:
-+		dce110_timing_generator_wait_for_vactive(tg);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+void dce110_tg_set_colors(struct timing_generator *tg,
-+	const struct tg_color *blank_color,
-+	const struct tg_color *overscan_color)
-+{
-+	if (blank_color != NULL)
-+		dce110_tg_program_blank_color(tg, blank_color);
-+	if (overscan_color != NULL)
-+		dce110_tg_set_overscan_color(tg, overscan_color);
-+}
-+
-+/* Gets first line of blank region of the display timing for CRTC
-+ * and programms is as a trigger to fire vertical interrupt
-+ */
-+bool dce110_arm_vert_intr(struct timing_generator *tg, uint8_t width)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t v_blank_start = 0;
-+	uint32_t v_blank_end = 0;
-+	uint32_t val = 0;
-+	uint32_t h_position, v_position;
-+
-+	tg->funcs->get_scanoutpos(
-+			tg,
-+			&v_blank_start,
-+			&v_blank_end,
-+			&h_position,
-+			&v_position);
-+
-+	if (v_blank_start == 0 || v_blank_end == 0)
-+		return false;
-+
-+	set_reg_field_value(
-+		val,
-+		v_blank_start,
-+		CRTC_VERTICAL_INTERRUPT0_POSITION,
-+		CRTC_VERTICAL_INTERRUPT0_LINE_START);
-+
-+	/* Set interval width for interrupt to fire to 1 scanline */
-+	set_reg_field_value(
-+		val,
-+		v_blank_start + width,
-+		CRTC_VERTICAL_INTERRUPT0_POSITION,
-+		CRTC_VERTICAL_INTERRUPT0_LINE_END);
-+
-+	dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERTICAL_INTERRUPT0_POSITION), val);
-+
-+	return true;
-+}
-+
-+static const struct timing_generator_funcs dce110_tg_funcs = {
-+		.validate_timing = dce110_tg_validate_timing,
-+		.program_timing = dce110_tg_program_timing,
-+		.enable_crtc = dce110_timing_generator_enable_crtc,
-+		.disable_crtc = dce110_timing_generator_disable_crtc,
-+		.is_counter_moving = dce110_timing_generator_is_counter_moving,
-+		.get_position = dce110_timing_generator_get_position,
-+		.get_frame_count = dce110_timing_generator_get_vblank_counter,
-+		.get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
-+		.set_early_control = dce110_timing_generator_set_early_control,
-+		.wait_for_state = dce110_tg_wait_for_state,
-+		.set_blank = dce110_tg_set_blank,
-+		.is_blanked = dce110_tg_is_blanked,
-+		.set_colors = dce110_tg_set_colors,
-+		.set_overscan_blank_color =
-+				dce110_timing_generator_set_overscan_color_black,
-+		.set_blank_color = dce110_timing_generator_program_blank_color,
-+		.disable_vga = dce110_timing_generator_disable_vga,
-+		.did_triggered_reset_occur =
-+				dce110_timing_generator_did_triggered_reset_occur,
-+		.setup_global_swap_lock =
-+				dce110_timing_generator_setup_global_swap_lock,
-+		.enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
-+		.enable_crtc_reset = dce110_timing_generator_enable_crtc_reset,
-+		.disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
-+		.tear_down_global_swap_lock =
-+				dce110_timing_generator_tear_down_global_swap_lock,
-+		.enable_advanced_request =
-+				dce110_timing_generator_enable_advanced_request,
-+		.set_drr =
-+				dce110_timing_generator_set_drr,
-+		.set_static_screen_control =
-+			dce110_timing_generator_set_static_screen_control,
-+		.set_test_pattern = dce110_timing_generator_set_test_pattern,
-+		.arm_vert_intr = dce110_arm_vert_intr,
-+};
-+
-+void dce110_timing_generator_construct(
-+	struct dce110_timing_generator *tg110,
-+	struct dc_context *ctx,
-+	uint32_t instance,
-+	const struct dce110_timing_generator_offsets *offsets)
-+{
-+	tg110->controller_id = CONTROLLER_ID_D0 + instance;
-+	tg110->base.inst = instance;
-+
-+	tg110->offsets = *offsets;
-+
-+	tg110->base.funcs = &dce110_tg_funcs;
-+
-+	tg110->base.ctx = ctx;
-+	tg110->base.bp = ctx->dc_bios;
-+
-+	tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
-+	tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
-+
-+	tg110->min_h_blank = 56;
-+	tg110->min_h_front_porch = 4;
-+	tg110->min_h_back_porch = 4;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h.0130~	2017-12-14 06:39:58.411903565 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h	2017-12-14 06:39:58.411903565 +0100
-@@ -0,0 +1,279 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_TIMING_GENERATOR_DCE110_H__
-+#define __DC_TIMING_GENERATOR_DCE110_H__
-+
-+#include "timing_generator.h"
-+#include "../include/grph_object_id.h"
-+
-+/* GSL Sync related values */
-+
-+/* In VSync mode, after 4 units of time, master pipe will generate
-+ * flip_ready signal */
-+#define VFLIP_READY_DELAY 4
-+/* In HSync mode, after 2 units of time, master pipe will generate
-+ * flip_ready signal */
-+#define HFLIP_READY_DELAY 2
-+/* 6 lines delay between forcing flip and checking all pipes ready */
-+#define HFLIP_CHECK_DELAY 6
-+/* 3 lines before end of frame */
-+#define FLIP_READY_BACK_LOOKUP 3
-+
-+/* Trigger Source Select - ASIC-defendant, actual values for the
-+ * register programming */
-+enum trigger_source_select {
-+	TRIGGER_SOURCE_SELECT_LOGIC_ZERO = 0,
-+	TRIGGER_SOURCE_SELECT_CRTC_VSYNCA = 1,
-+	TRIGGER_SOURCE_SELECT_CRTC_HSYNCA = 2,
-+	TRIGGER_SOURCE_SELECT_CRTC_VSYNCB = 3,
-+	TRIGGER_SOURCE_SELECT_CRTC_HSYNCB = 4,
-+	TRIGGER_SOURCE_SELECT_GENERICF = 5,
-+	TRIGGER_SOURCE_SELECT_GENERICE = 6,
-+	TRIGGER_SOURCE_SELECT_VSYNCA = 7,
-+	TRIGGER_SOURCE_SELECT_HSYNCA = 8,
-+	TRIGGER_SOURCE_SELECT_VSYNCB = 9,
-+	TRIGGER_SOURCE_SELECT_HSYNCB = 10,
-+	TRIGGER_SOURCE_SELECT_HPD1 = 11,
-+	TRIGGER_SOURCE_SELECT_HPD2 = 12,
-+	TRIGGER_SOURCE_SELECT_GENERICD = 13,
-+	TRIGGER_SOURCE_SELECT_GENERICC = 14,
-+	TRIGGER_SOURCE_SELECT_VIDEO_CAPTURE = 15,
-+	TRIGGER_SOURCE_SELECT_GSL_GROUP0 = 16,
-+	TRIGGER_SOURCE_SELECT_GSL_GROUP1 = 17,
-+	TRIGGER_SOURCE_SELECT_GSL_GROUP2 = 18,
-+	TRIGGER_SOURCE_SELECT_BLONY = 19,
-+	TRIGGER_SOURCE_SELECT_GENERICA = 20,
-+	TRIGGER_SOURCE_SELECT_GENERICB = 21,
-+	TRIGGER_SOURCE_SELECT_GSL_ALLOW_FLIP = 22,
-+	TRIGGER_SOURCE_SELECT_MANUAL_TRIGGER = 23
-+};
-+
-+/* Trigger Source Select - ASIC-dependant, actual values for the
-+ * register programming */
-+enum trigger_polarity_select {
-+	TRIGGER_POLARITY_SELECT_LOGIC_ZERO = 0,
-+	TRIGGER_POLARITY_SELECT_CRTC = 1,
-+	TRIGGER_POLARITY_SELECT_GENERICA = 2,
-+	TRIGGER_POLARITY_SELECT_GENERICB = 3,
-+	TRIGGER_POLARITY_SELECT_HSYNCA = 4,
-+	TRIGGER_POLARITY_SELECT_HSYNCB = 5,
-+	TRIGGER_POLARITY_SELECT_VIDEO_CAPTURE = 6,
-+	TRIGGER_POLARITY_SELECT_GENERICC = 7
-+};
-+
-+
-+struct dce110_timing_generator_offsets {
-+	int32_t crtc;
-+	int32_t dcp;
-+
-+	/* DCE80 use only */
-+	int32_t dmif;
-+};
-+
-+struct dce110_timing_generator {
-+	struct timing_generator base;
-+	struct dce110_timing_generator_offsets offsets;
-+	struct dce110_timing_generator_offsets derived_offsets;
-+
-+	enum controller_id controller_id;
-+
-+	uint32_t max_h_total;
-+	uint32_t max_v_total;
-+
-+	uint32_t min_h_blank;
-+	uint32_t min_h_front_porch;
-+	uint32_t min_h_back_porch;
-+
-+	/* DCE 12 */
-+	uint32_t min_h_sync_width;
-+	uint32_t min_v_sync_width;
-+	uint32_t min_v_blank;
-+
-+};
-+
-+#define DCE110TG_FROM_TG(tg)\
-+	container_of(tg, struct dce110_timing_generator, base)
-+
-+void dce110_timing_generator_construct(
-+	struct dce110_timing_generator *tg,
-+	struct dc_context *ctx,
-+	uint32_t instance,
-+	const struct dce110_timing_generator_offsets *offsets);
-+
-+/* determine if given timing can be supported by TG */
-+bool dce110_timing_generator_validate_timing(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing,
-+	enum signal_type signal);
-+
-+/******** HW programming ************/
-+
-+/* Program timing generator with given timing */
-+bool dce110_timing_generator_program_timing_generator(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *dc_crtc_timing);
-+
-+/* Disable/Enable Timing Generator */
-+bool dce110_timing_generator_enable_crtc(struct timing_generator *tg);
-+bool dce110_timing_generator_disable_crtc(struct timing_generator *tg);
-+
-+void dce110_timing_generator_set_early_control(
-+		struct timing_generator *tg,
-+		uint32_t early_cntl);
-+
-+/**************** TG current status ******************/
-+
-+/* return the current frame counter. Used by Linux kernel DRM */
-+uint32_t dce110_timing_generator_get_vblank_counter(
-+		struct timing_generator *tg);
-+
-+void dce110_timing_generator_get_position(
-+	struct timing_generator *tg,
-+	struct crtc_position *position);
-+
-+/* return true if TG counter is moving. false if TG is stopped */
-+bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg);
-+
-+/* wait until TG is in beginning of vertical blank region */
-+void dce110_timing_generator_wait_for_vblank(struct timing_generator *tg);
-+
-+/* wait until TG is in beginning of active region */
-+void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg);
-+
-+/*********** Timing Generator Synchronization routines ****/
-+
-+/* Setups Global Swap Lock group, TimingServer or TimingClient*/
-+void dce110_timing_generator_setup_global_swap_lock(
-+	struct timing_generator *tg,
-+	const struct dcp_gsl_params *gsl_params);
-+
-+/* Clear all the register writes done by setup_global_swap_lock */
-+void dce110_timing_generator_tear_down_global_swap_lock(
-+	struct timing_generator *tg);
-+
-+/* Reset crtc position on master VSync */
-+void dce110_timing_generator_enable_crtc_reset(
-+	struct timing_generator *tg,
-+	int source,
-+	struct crtc_trigger_info *crtc_tp);
-+
-+/* Reset slave controllers on master VSync */
-+void dce110_timing_generator_enable_reset_trigger(
-+	struct timing_generator *tg,
-+	int source);
-+
-+/* disabling trigger-reset */
-+void dce110_timing_generator_disable_reset_trigger(
-+	struct timing_generator *tg);
-+
-+/* Checks whether CRTC triggered reset occurred */
-+bool dce110_timing_generator_did_triggered_reset_occur(
-+	struct timing_generator *tg);
-+
-+/******** Stuff to move to other virtual HW objects *****************/
-+/* Move to enable accelerated mode */
-+void dce110_timing_generator_disable_vga(struct timing_generator *tg);
-+/* TODO: Should we move it to transform */
-+/* Fully program CRTC timing in timing generator */
-+void dce110_timing_generator_program_blanking(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing);
-+
-+/* TODO: Should we move it to opp? */
-+/* Combine with below and move YUV/RGB color conversion to SW layer */
-+void dce110_timing_generator_program_blank_color(
-+	struct timing_generator *tg,
-+	const struct tg_color *black_color);
-+/* Combine with above and move YUV/RGB color conversion to SW layer */
-+void dce110_timing_generator_set_overscan_color_black(
-+	struct timing_generator *tg,
-+	const struct tg_color *color);
-+void dce110_timing_generator_color_space_to_black_color(
-+		enum dc_color_space colorspace,
-+	struct tg_color *black_color);
-+/*************** End-of-move ********************/
-+
-+/* Not called yet */
-+void dce110_timing_generator_set_test_pattern(
-+	struct timing_generator *tg,
-+	/* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
-+	 * because this is not DP-specific (which is probably somewhere in DP
-+	 * encoder) */
-+	enum controller_dp_test_pattern test_pattern,
-+	enum dc_color_depth color_depth);
-+
-+void dce110_timing_generator_set_drr(
-+	struct timing_generator *tg,
-+	const struct drr_params *params);
-+
-+void dce110_timing_generator_set_static_screen_control(
-+	struct timing_generator *tg,
-+	uint32_t value);
-+
-+void dce110_timing_generator_get_crtc_scanoutpos(
-+	struct timing_generator *tg,
-+	uint32_t *v_blank_start,
-+	uint32_t *v_blank_end,
-+	uint32_t *h_position,
-+	uint32_t *v_position);
-+
-+void dce110_timing_generator_enable_advanced_request(
-+	struct timing_generator *tg,
-+	bool enable,
-+	const struct dc_crtc_timing *timing);
-+
-+void dce110_timing_generator_set_lock_master(struct timing_generator *tg,
-+		bool lock);
-+
-+void dce110_tg_program_blank_color(struct timing_generator *tg,
-+	const struct tg_color *black_color);
-+
-+void dce110_tg_set_overscan_color(struct timing_generator *tg,
-+	const struct tg_color *overscan_color);
-+
-+void dce110_tg_program_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing,
-+	bool use_vbios);
-+
-+bool dce110_tg_is_blanked(struct timing_generator *tg);
-+
-+void dce110_tg_set_blank(struct timing_generator *tg,
-+		bool enable_blanking);
-+
-+bool dce110_tg_validate_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing);
-+
-+void dce110_tg_wait_for_state(struct timing_generator *tg,
-+	enum crtc_state state);
-+
-+void dce110_tg_set_colors(struct timing_generator *tg,
-+	const struct tg_color *blank_color,
-+	const struct tg_color *overscan_color);
-+
-+bool dce110_arm_vert_intr(
-+		struct timing_generator *tg, uint8_t width);
-+
-+#endif /* __DC_TIMING_GENERATOR_DCE110_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c.0130~	2017-12-14 06:39:58.411903565 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c	2017-12-14 06:39:58.411903565 +0100
-@@ -0,0 +1,688 @@
-+#include "dm_services.h"
-+
-+/* include DCE11 register header files */
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "dc_types.h"
-+#include "dc_bios_types.h"
-+#include "dc.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/logger_interface.h"
-+#include "dce110_timing_generator.h"
-+#include "dce110_timing_generator_v.h"
-+
-+#include "timing_generator.h"
-+
-+/** ********************************************************************************
-+ *
-+ * DCE11 Timing Generator Implementation
-+ *
-+ **********************************************************************************/
-+
-+/**
-+* Enable CRTCV
-+*/
-+
-+static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg)
-+{
-+/*
-+* Set MASTER_UPDATE_MODE to 0
-+* This is needed for DRR, and also suggested to be default value by Syed.
-+*/
-+
-+	uint32_t value;
-+
-+	value = 0;
-+	set_reg_field_value(value, 0,
-+			CRTCV_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE);
-+	dm_write_reg(tg->ctx,
-+			mmCRTCV_MASTER_UPDATE_MODE, value);
-+
-+	/* TODO: may want this on for looking for underflow */
-+	value = 0;
-+	dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value);
-+
-+	value = 0;
-+	set_reg_field_value(value, 1,
-+			CRTCV_MASTER_EN, CRTC_MASTER_EN);
-+	dm_write_reg(tg->ctx,
-+			mmCRTCV_MASTER_EN, value);
-+
-+	return true;
-+}
-+
-+static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg)
-+{
-+	uint32_t value;
-+
-+	value = dm_read_reg(tg->ctx,
-+			mmCRTCV_CONTROL);
-+	set_reg_field_value(value, 0,
-+			CRTCV_CONTROL, CRTC_DISABLE_POINT_CNTL);
-+	set_reg_field_value(value, 0,
-+				CRTCV_CONTROL, CRTC_MASTER_EN);
-+	dm_write_reg(tg->ctx,
-+			mmCRTCV_CONTROL, value);
-+	/*
-+	 * TODO: call this when adding stereo support
-+	 * tg->funcs->disable_stereo(tg);
-+	 */
-+	return true;
-+}
-+
-+static void dce110_timing_generator_v_blank_crtc(struct timing_generator *tg)
-+{
-+	uint32_t addr = mmCRTCV_BLANK_CONTROL;
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		CRTCV_BLANK_CONTROL,
-+		CRTC_BLANK_DATA_EN);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		CRTCV_BLANK_CONTROL,
-+		CRTC_BLANK_DE_MODE);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+
-+static void dce110_timing_generator_v_unblank_crtc(struct timing_generator *tg)
-+{
-+	uint32_t addr = mmCRTCV_BLANK_CONTROL;
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		CRTCV_BLANK_CONTROL,
-+		CRTC_BLANK_DATA_EN);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		CRTCV_BLANK_CONTROL,
-+		CRTC_BLANK_DE_MODE);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+
-+static bool dce110_timing_generator_v_is_in_vertical_blank(
-+		struct timing_generator *tg)
-+{
-+	uint32_t addr = 0;
-+	uint32_t value = 0;
-+	uint32_t field = 0;
-+
-+	addr = mmCRTCV_STATUS;
-+	value = dm_read_reg(tg->ctx, addr);
-+	field = get_reg_field_value(value, CRTCV_STATUS, CRTC_V_BLANK);
-+	return field == 1;
-+}
-+
-+static bool dce110_timing_generator_v_is_counter_moving(struct timing_generator *tg)
-+{
-+	uint32_t value;
-+	uint32_t h1 = 0;
-+	uint32_t h2 = 0;
-+	uint32_t v1 = 0;
-+	uint32_t v2 = 0;
-+
-+	value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION);
-+
-+	h1 = get_reg_field_value(
-+			value,
-+			CRTCV_STATUS_POSITION,
-+			CRTC_HORZ_COUNT);
-+
-+	v1 = get_reg_field_value(
-+			value,
-+			CRTCV_STATUS_POSITION,
-+			CRTC_VERT_COUNT);
-+
-+	value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION);
-+
-+	h2 = get_reg_field_value(
-+			value,
-+			CRTCV_STATUS_POSITION,
-+			CRTC_HORZ_COUNT);
-+
-+	v2 = get_reg_field_value(
-+			value,
-+			CRTCV_STATUS_POSITION,
-+			CRTC_VERT_COUNT);
-+
-+	if (h1 == h2 && v1 == v2)
-+		return false;
-+	else
-+		return true;
-+}
-+
-+static void dce110_timing_generator_v_wait_for_vblank(struct timing_generator *tg)
-+{
-+	/* We want to catch beginning of VBlank here, so if the first try are
-+	 * in VBlank, we might be very close to Active, in this case wait for
-+	 * another frame
-+	 */
-+	while (dce110_timing_generator_v_is_in_vertical_blank(tg)) {
-+		if (!dce110_timing_generator_v_is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+
-+	while (!dce110_timing_generator_v_is_in_vertical_blank(tg)) {
-+		if (!dce110_timing_generator_v_is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+}
-+
-+/**
-+* Wait till we are in VActive (anywhere in VActive)
-+*/
-+static void dce110_timing_generator_v_wait_for_vactive(struct timing_generator *tg)
-+{
-+	while (dce110_timing_generator_v_is_in_vertical_blank(tg)) {
-+		if (!dce110_timing_generator_v_is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+}
-+
-+static void dce110_timing_generator_v_wait_for_state(struct timing_generator *tg,
-+	enum crtc_state state)
-+{
-+	switch (state) {
-+	case CRTC_STATE_VBLANK:
-+		dce110_timing_generator_v_wait_for_vblank(tg);
-+		break;
-+
-+	case CRTC_STATE_VACTIVE:
-+		dce110_timing_generator_v_wait_for_vactive(tg);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+static void dce110_timing_generator_v_program_blanking(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t vsync_offset = timing->v_border_bottom +
-+			timing->v_front_porch;
-+	uint32_t v_sync_start = timing->v_addressable + vsync_offset;
-+
-+	uint32_t hsync_offset = timing->h_border_right +
-+			timing->h_front_porch;
-+	uint32_t h_sync_start = timing->h_addressable + hsync_offset;
-+
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t value = 0;
-+	uint32_t addr = 0;
-+	uint32_t tmp = 0;
-+
-+	addr = mmCRTCV_H_TOTAL;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		timing->h_total - 1,
-+		CRTCV_H_TOTAL,
-+		CRTC_H_TOTAL);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmCRTCV_V_TOTAL;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		timing->v_total - 1,
-+		CRTCV_V_TOTAL,
-+		CRTC_V_TOTAL);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmCRTCV_H_BLANK_START_END;
-+	value = dm_read_reg(ctx, addr);
-+
-+	tmp = timing->h_total -
-+		(h_sync_start + timing->h_border_left);
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTCV_H_BLANK_START_END,
-+		CRTC_H_BLANK_END);
-+
-+	tmp = tmp + timing->h_addressable +
-+		timing->h_border_left + timing->h_border_right;
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTCV_H_BLANK_START_END,
-+		CRTC_H_BLANK_START);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmCRTCV_V_BLANK_START_END;
-+	value = dm_read_reg(ctx, addr);
-+
-+	tmp = timing->v_total - (v_sync_start + timing->v_border_top);
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTCV_V_BLANK_START_END,
-+		CRTC_V_BLANK_END);
-+
-+	tmp = tmp + timing->v_addressable + timing->v_border_top +
-+		timing->v_border_bottom;
-+
-+	set_reg_field_value(
-+		value,
-+		tmp,
-+		CRTCV_V_BLANK_START_END,
-+		CRTC_V_BLANK_START);
-+
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmCRTCV_H_SYNC_A;
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		timing->h_sync_width,
-+		CRTCV_H_SYNC_A,
-+		CRTC_H_SYNC_A_END);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmCRTCV_H_SYNC_A_CNTL;
-+	value = dm_read_reg(ctx, addr);
-+	if (timing->flags.HSYNC_POSITIVE_POLARITY) {
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTCV_H_SYNC_A_CNTL,
-+			CRTC_H_SYNC_A_POL);
-+	} else {
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTCV_H_SYNC_A_CNTL,
-+			CRTC_H_SYNC_A_POL);
-+	}
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmCRTCV_V_SYNC_A;
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		timing->v_sync_width,
-+		CRTCV_V_SYNC_A,
-+		CRTC_V_SYNC_A_END);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmCRTCV_V_SYNC_A_CNTL;
-+	value = dm_read_reg(ctx, addr);
-+	if (timing->flags.VSYNC_POSITIVE_POLARITY) {
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTCV_V_SYNC_A_CNTL,
-+			CRTC_V_SYNC_A_POL);
-+	} else {
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTCV_V_SYNC_A_CNTL,
-+			CRTC_V_SYNC_A_POL);
-+	}
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmCRTCV_INTERLACE_CONTROL;
-+	value = dm_read_reg(ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		timing->flags.INTERLACE,
-+		CRTCV_INTERLACE_CONTROL,
-+		CRTC_INTERLACE_ENABLE);
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static void dce110_timing_generator_v_enable_advanced_request(
-+	struct timing_generator *tg,
-+	bool enable,
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t addr = mmCRTCV_START_LINE_CONTROL;
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	if (enable) {
-+		if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
-+			set_reg_field_value(
-+				value,
-+				3,
-+				CRTCV_START_LINE_CONTROL,
-+				CRTC_ADVANCED_START_LINE_POSITION);
-+		} else {
-+			set_reg_field_value(
-+				value,
-+				4,
-+				CRTCV_START_LINE_CONTROL,
-+				CRTC_ADVANCED_START_LINE_POSITION);
-+		}
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTCV_START_LINE_CONTROL,
-+			CRTC_LEGACY_REQUESTOR_EN);
-+	} else {
-+		set_reg_field_value(
-+			value,
-+			2,
-+			CRTCV_START_LINE_CONTROL,
-+			CRTC_ADVANCED_START_LINE_POSITION);
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTCV_START_LINE_CONTROL,
-+			CRTC_LEGACY_REQUESTOR_EN);
-+	}
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+
-+static void dce110_timing_generator_v_set_blank(struct timing_generator *tg,
-+		bool enable_blanking)
-+{
-+	if (enable_blanking)
-+		dce110_timing_generator_v_blank_crtc(tg);
-+	else
-+		dce110_timing_generator_v_unblank_crtc(tg);
-+}
-+
-+static void dce110_timing_generator_v_program_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing,
-+	bool use_vbios)
-+{
-+	if (use_vbios)
-+		dce110_timing_generator_program_timing_generator(tg, timing);
-+	else
-+		dce110_timing_generator_v_program_blanking(tg, timing);
-+}
-+
-+static void dce110_timing_generator_v_program_blank_color(
-+		struct timing_generator *tg,
-+		const struct tg_color *black_color)
-+{
-+	uint32_t addr = mmCRTCV_BLACK_COLOR;
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		black_color->color_b_cb,
-+		CRTCV_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_B_CB);
-+	set_reg_field_value(
-+		value,
-+		black_color->color_g_y,
-+		CRTCV_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_G_Y);
-+	set_reg_field_value(
-+		value,
-+		black_color->color_r_cr,
-+		CRTCV_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_R_CR);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+
-+static void dce110_timing_generator_v_set_overscan_color_black(
-+	struct timing_generator *tg,
-+	const struct tg_color *color)
-+{
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t addr;
-+	uint32_t value = 0;
-+
-+	set_reg_field_value(
-+			value,
-+			color->color_b_cb,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_BLUE);
-+
-+	set_reg_field_value(
-+			value,
-+			color->color_r_cr,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_RED);
-+
-+	set_reg_field_value(
-+			value,
-+			color->color_g_y,
-+			CRTC_OVERSCAN_COLOR,
-+			CRTC_OVERSCAN_COLOR_GREEN);
-+
-+	addr = mmCRTCV_OVERSCAN_COLOR;
-+	dm_write_reg(ctx, addr, value);
-+	addr = mmCRTCV_BLACK_COLOR;
-+	dm_write_reg(ctx, addr, value);
-+	/* This is desirable to have a constant DAC output voltage during the
-+	 * blank time that is higher than the 0 volt reference level that the
-+	 * DAC outputs when the NBLANK signal
-+	 * is asserted low, such as for output to an analog TV. */
-+	addr = mmCRTCV_BLANK_DATA_COLOR;
-+	dm_write_reg(ctx, addr, value);
-+
-+	/* TO DO we have to program EXT registers and we need to know LB DATA
-+	 * format because it is used when more 10 , i.e. 12 bits per color
-+	 *
-+	 * m_mmDxCRTC_OVERSCAN_COLOR_EXT
-+	 * m_mmDxCRTC_BLACK_COLOR_EXT
-+	 * m_mmDxCRTC_BLANK_DATA_COLOR_EXT
-+	 */
-+}
-+
-+static void dce110_tg_v_program_blank_color(struct timing_generator *tg,
-+		const struct tg_color *black_color)
-+{
-+	uint32_t addr = mmCRTCV_BLACK_COLOR;
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		black_color->color_b_cb,
-+		CRTCV_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_B_CB);
-+	set_reg_field_value(
-+		value,
-+		black_color->color_g_y,
-+		CRTCV_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_G_Y);
-+	set_reg_field_value(
-+		value,
-+		black_color->color_r_cr,
-+		CRTCV_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_R_CR);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+
-+	addr = mmCRTCV_BLANK_DATA_COLOR;
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+
-+static void dce110_timing_generator_v_set_overscan_color(struct timing_generator *tg,
-+	const struct tg_color *overscan_color)
-+{
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t value = 0;
-+	uint32_t addr;
-+
-+	set_reg_field_value(
-+		value,
-+		overscan_color->color_b_cb,
-+		CRTCV_OVERSCAN_COLOR,
-+		CRTC_OVERSCAN_COLOR_BLUE);
-+
-+	set_reg_field_value(
-+		value,
-+		overscan_color->color_g_y,
-+		CRTCV_OVERSCAN_COLOR,
-+		CRTC_OVERSCAN_COLOR_GREEN);
-+
-+	set_reg_field_value(
-+		value,
-+		overscan_color->color_r_cr,
-+		CRTCV_OVERSCAN_COLOR,
-+		CRTC_OVERSCAN_COLOR_RED);
-+
-+	addr = mmCRTCV_OVERSCAN_COLOR;
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static void dce110_timing_generator_v_set_colors(struct timing_generator *tg,
-+	const struct tg_color *blank_color,
-+	const struct tg_color *overscan_color)
-+{
-+	if (blank_color != NULL)
-+		dce110_tg_v_program_blank_color(tg, blank_color);
-+	if (overscan_color != NULL)
-+		dce110_timing_generator_v_set_overscan_color(tg, overscan_color);
-+}
-+
-+static void dce110_timing_generator_v_set_early_control(
-+		struct timing_generator *tg,
-+		uint32_t early_cntl)
-+{
-+	uint32_t regval;
-+	uint32_t address = mmCRTC_CONTROL;
-+
-+	regval = dm_read_reg(tg->ctx, address);
-+	set_reg_field_value(regval, early_cntl,
-+			CRTCV_CONTROL, CRTC_HBLANK_EARLY_CONTROL);
-+	dm_write_reg(tg->ctx, address, regval);
-+}
-+
-+static uint32_t dce110_timing_generator_v_get_vblank_counter(struct timing_generator *tg)
-+{
-+	uint32_t addr = mmCRTCV_STATUS_FRAME_COUNT;
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+	uint32_t field = get_reg_field_value(
-+			value, CRTCV_STATUS_FRAME_COUNT, CRTC_FRAME_COUNT);
-+
-+	return field;
-+}
-+
-+static bool dce110_timing_generator_v_did_triggered_reset_occur(
-+	struct timing_generator *tg)
-+{
-+	dm_logger_write(tg->ctx->logger, LOG_ERROR,
-+					"Timing Sync not supported on underlay pipe\n");
-+	return false;
-+}
-+
-+static void dce110_timing_generator_v_setup_global_swap_lock(
-+	struct timing_generator *tg,
-+	const struct dcp_gsl_params *gsl_params)
-+{
-+	dm_logger_write(tg->ctx->logger, LOG_ERROR,
-+					"Timing Sync not supported on underlay pipe\n");
-+	return;
-+}
-+
-+static void dce110_timing_generator_v_enable_reset_trigger(
-+	struct timing_generator *tg,
-+	int source_tg_inst)
-+{
-+	dm_logger_write(tg->ctx->logger, LOG_ERROR,
-+					"Timing Sync not supported on underlay pipe\n");
-+	return;
-+}
-+
-+static void dce110_timing_generator_v_disable_reset_trigger(
-+	struct timing_generator *tg)
-+{
-+	dm_logger_write(tg->ctx->logger, LOG_ERROR,
-+						"Timing Sync not supported on underlay pipe\n");
-+	return;
-+}
-+
-+static void dce110_timing_generator_v_tear_down_global_swap_lock(
-+	struct timing_generator *tg)
-+{
-+	dm_logger_write(tg->ctx->logger, LOG_ERROR,
-+						"Timing Sync not supported on underlay pipe\n");
-+	return;
-+}
-+
-+static void dce110_timing_generator_v_disable_vga(
-+	struct timing_generator *tg)
-+{
-+	return;
-+}
-+
-+static bool dce110_tg_v_is_blanked(struct timing_generator *tg)
-+{
-+	/* Signal comes from the primary pipe, underlay is never blanked. */
-+	return false;
-+}
-+
-+/** ********************************************************************************************
-+ *
-+ * DCE11 Timing Generator Constructor / Destructor
-+ *
-+ *********************************************************************************************/
-+static const struct timing_generator_funcs dce110_tg_v_funcs = {
-+		.validate_timing = dce110_tg_validate_timing,
-+		.program_timing = dce110_timing_generator_v_program_timing,
-+		.enable_crtc = dce110_timing_generator_v_enable_crtc,
-+		.disable_crtc = dce110_timing_generator_v_disable_crtc,
-+		.is_counter_moving = dce110_timing_generator_v_is_counter_moving,
-+		.get_position = NULL, /* Not to be implemented for underlay*/
-+		.get_frame_count = dce110_timing_generator_v_get_vblank_counter,
-+		.set_early_control = dce110_timing_generator_v_set_early_control,
-+		.wait_for_state = dce110_timing_generator_v_wait_for_state,
-+		.set_blank = dce110_timing_generator_v_set_blank,
-+		.is_blanked = dce110_tg_v_is_blanked,
-+		.set_colors = dce110_timing_generator_v_set_colors,
-+		.set_overscan_blank_color =
-+				dce110_timing_generator_v_set_overscan_color_black,
-+		.set_blank_color = dce110_timing_generator_v_program_blank_color,
-+		.disable_vga = dce110_timing_generator_v_disable_vga,
-+		.did_triggered_reset_occur =
-+				dce110_timing_generator_v_did_triggered_reset_occur,
-+		.setup_global_swap_lock =
-+				dce110_timing_generator_v_setup_global_swap_lock,
-+		.enable_reset_trigger = dce110_timing_generator_v_enable_reset_trigger,
-+		.disable_reset_trigger = dce110_timing_generator_v_disable_reset_trigger,
-+		.tear_down_global_swap_lock =
-+				dce110_timing_generator_v_tear_down_global_swap_lock,
-+		.enable_advanced_request =
-+				dce110_timing_generator_v_enable_advanced_request
-+};
-+
-+void dce110_timing_generator_v_construct(
-+	struct dce110_timing_generator *tg110,
-+	struct dc_context *ctx)
-+{
-+	tg110->controller_id = CONTROLLER_ID_UNDERLAY0;
-+
-+	tg110->base.funcs = &dce110_tg_v_funcs;
-+
-+	tg110->base.ctx = ctx;
-+	tg110->base.bp = ctx->dc_bios;
-+
-+	tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
-+	tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
-+
-+	tg110->min_h_blank = 56;
-+	tg110->min_h_front_porch = 4;
-+	tg110->min_h_back_porch = 4;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h.0130~	2017-12-14 06:39:58.411903565 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h	2017-12-14 06:39:58.411903565 +0100
-@@ -0,0 +1,33 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_TIMING_GENERATOR_V_DCE110_H__
-+#define __DC_TIMING_GENERATOR_V_DCE110_H__
-+
-+void dce110_timing_generator_v_construct(
-+	struct dce110_timing_generator *tg110,
-+	struct dc_context *ctx);
-+
-+#endif /* __DC_TIMING_GENERATOR_V_DCE110_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c.0130~	2017-12-14 06:39:58.412903565 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c	2017-12-14 06:39:58.412903565 +0100
-@@ -0,0 +1,716 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dce110_transform_v.h"
-+#include "dm_services.h"
-+#include "dc.h"
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#define SCLV_PHASES 64
-+
-+struct sclv_ratios_inits {
-+	uint32_t h_int_scale_ratio_luma;
-+	uint32_t h_int_scale_ratio_chroma;
-+	uint32_t v_int_scale_ratio_luma;
-+	uint32_t v_int_scale_ratio_chroma;
-+	struct init_int_and_frac h_init_luma;
-+	struct init_int_and_frac h_init_chroma;
-+	struct init_int_and_frac v_init_luma;
-+	struct init_int_and_frac v_init_chroma;
-+};
-+
-+static void calculate_viewport(
-+		const struct scaler_data *scl_data,
-+		struct rect *luma_viewport,
-+		struct rect *chroma_viewport)
-+{
-+	/*Do not set chroma vp for rgb444 pixel format*/
-+	luma_viewport->x = scl_data->viewport.x - scl_data->viewport.x % 2;
-+	luma_viewport->y = scl_data->viewport.y - scl_data->viewport.y % 2;
-+	luma_viewport->width =
-+		scl_data->viewport.width - scl_data->viewport.width % 2;
-+	luma_viewport->height =
-+		scl_data->viewport.height - scl_data->viewport.height % 2;
-+	chroma_viewport->x = luma_viewport->x;
-+	chroma_viewport->y = luma_viewport->y;
-+	chroma_viewport->height = luma_viewport->height;
-+	chroma_viewport->width = luma_viewport->width;
-+
-+	if (scl_data->format == PIXEL_FORMAT_420BPP8) {
-+		luma_viewport->height += luma_viewport->height % 2;
-+		luma_viewport->width += luma_viewport->width % 2;
-+		/*for 420 video chroma is 1/4 the area of luma, scaled
-+		 *vertically and horizontally
-+		 */
-+		chroma_viewport->x = luma_viewport->x / 2;
-+		chroma_viewport->y = luma_viewport->y / 2;
-+		chroma_viewport->height = luma_viewport->height / 2;
-+		chroma_viewport->width = luma_viewport->width / 2;
-+	}
-+}
-+
-+static void program_viewport(
-+	struct dce_transform *xfm_dce,
-+	struct rect *luma_view_port,
-+	struct rect *chroma_view_port)
-+{
-+	struct dc_context *ctx = xfm_dce->base.ctx;
-+	uint32_t value = 0;
-+	uint32_t addr = 0;
-+
-+	if (luma_view_port->width != 0 && luma_view_port->height != 0) {
-+		addr = mmSCLV_VIEWPORT_START;
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			luma_view_port->x,
-+			SCLV_VIEWPORT_START,
-+			VIEWPORT_X_START);
-+		set_reg_field_value(
-+			value,
-+			luma_view_port->y,
-+			SCLV_VIEWPORT_START,
-+			VIEWPORT_Y_START);
-+		dm_write_reg(ctx, addr, value);
-+
-+		addr = mmSCLV_VIEWPORT_SIZE;
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			luma_view_port->height,
-+			SCLV_VIEWPORT_SIZE,
-+			VIEWPORT_HEIGHT);
-+		set_reg_field_value(
-+			value,
-+			luma_view_port->width,
-+			SCLV_VIEWPORT_SIZE,
-+			VIEWPORT_WIDTH);
-+		dm_write_reg(ctx, addr, value);
-+	}
-+
-+	if (chroma_view_port->width != 0 && chroma_view_port->height != 0) {
-+		addr = mmSCLV_VIEWPORT_START_C;
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			chroma_view_port->x,
-+			SCLV_VIEWPORT_START_C,
-+			VIEWPORT_X_START_C);
-+		set_reg_field_value(
-+			value,
-+			chroma_view_port->y,
-+			SCLV_VIEWPORT_START_C,
-+			VIEWPORT_Y_START_C);
-+		dm_write_reg(ctx, addr, value);
-+
-+		addr = mmSCLV_VIEWPORT_SIZE_C;
-+		value = 0;
-+		set_reg_field_value(
-+			value,
-+			chroma_view_port->height,
-+			SCLV_VIEWPORT_SIZE_C,
-+			VIEWPORT_HEIGHT_C);
-+		set_reg_field_value(
-+			value,
-+			chroma_view_port->width,
-+			SCLV_VIEWPORT_SIZE_C,
-+			VIEWPORT_WIDTH_C);
-+		dm_write_reg(ctx, addr, value);
-+	}
-+}
-+
-+/*
-+ * Function:
-+ * void setup_scaling_configuration
-+ *
-+ * Purpose: setup scaling mode : bypass, RGb, YCbCr and nummber of taps
-+ * Input:   data
-+ *
-+ * Output:
-+ *  void
-+ */
-+static bool setup_scaling_configuration(
-+	struct dce_transform *xfm_dce,
-+	const struct scaler_data *data)
-+{
-+	bool is_scaling_needed = false;
-+	struct dc_context *ctx = xfm_dce->base.ctx;
-+	uint32_t value = 0;
-+
-+	set_reg_field_value(value, data->taps.h_taps - 1,
-+			SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS);
-+	set_reg_field_value(value, data->taps.v_taps - 1,
-+			SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS);
-+	set_reg_field_value(value, data->taps.h_taps_c - 1,
-+			SCLV_TAP_CONTROL, SCL_H_NUM_OF_TAPS_C);
-+	set_reg_field_value(value, data->taps.v_taps_c - 1,
-+			SCLV_TAP_CONTROL, SCL_V_NUM_OF_TAPS_C);
-+	dm_write_reg(ctx, mmSCLV_TAP_CONTROL, value);
-+
-+	value = 0;
-+	if (data->taps.h_taps + data->taps.v_taps > 2) {
-+		set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE);
-+		set_reg_field_value(value, 1, SCLV_MODE, SCL_PSCL_EN);
-+		is_scaling_needed = true;
-+	} else {
-+		set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE);
-+		set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN);
-+	}
-+
-+	if (data->taps.h_taps_c + data->taps.v_taps_c > 2) {
-+		set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE_C);
-+		set_reg_field_value(value, 1, SCLV_MODE, SCL_PSCL_EN_C);
-+		is_scaling_needed = true;
-+	} else if (data->format != PIXEL_FORMAT_420BPP8) {
-+		set_reg_field_value(
-+			value,
-+			get_reg_field_value(value, SCLV_MODE, SCL_MODE),
-+			SCLV_MODE,
-+			SCL_MODE_C);
-+		set_reg_field_value(
-+			value,
-+			get_reg_field_value(value, SCLV_MODE, SCL_PSCL_EN),
-+			SCLV_MODE,
-+			SCL_PSCL_EN_C);
-+	} else {
-+		set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE_C);
-+		set_reg_field_value(value, 0, SCLV_MODE, SCL_PSCL_EN_C);
-+	}
-+	dm_write_reg(ctx, mmSCLV_MODE, value);
-+
-+	value = 0;
-+	/*
-+	 * 0 - Replaced out of bound pixels with black pixel
-+	 * (or any other required color)
-+	 * 1 - Replaced out of bound pixels with the edge pixel
-+	 */
-+	set_reg_field_value(value, 1, SCLV_CONTROL, SCL_BOUNDARY_MODE);
-+	dm_write_reg(ctx, mmSCLV_CONTROL, value);
-+
-+	return is_scaling_needed;
-+}
-+
-+/**
-+* Function:
-+* void program_overscan
-+*
-+* Purpose: Programs overscan border
-+* Input:   overscan
-+*
-+* Output:
-+   void
-+*/
-+static void program_overscan(
-+		struct dce_transform *xfm_dce,
-+		const struct scaler_data *data)
-+{
-+	uint32_t overscan_left_right = 0;
-+	uint32_t overscan_top_bottom = 0;
-+
-+	int overscan_right = data->h_active - data->recout.x - data->recout.width;
-+	int overscan_bottom = data->v_active - data->recout.y - data->recout.height;
-+
-+	if (xfm_dce->base.ctx->dc->debug.surface_visual_confirm) {
-+		overscan_bottom += 2;
-+		overscan_right += 2;
-+	}
-+
-+	if (overscan_right < 0) {
-+		BREAK_TO_DEBUGGER();
-+		overscan_right = 0;
-+	}
-+	if (overscan_bottom < 0) {
-+		BREAK_TO_DEBUGGER();
-+		overscan_bottom = 0;
-+	}
-+
-+	set_reg_field_value(overscan_left_right, data->recout.x,
-+			EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT);
-+
-+	set_reg_field_value(overscan_left_right, overscan_right,
-+			EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT);
-+
-+	set_reg_field_value(overscan_top_bottom, data->recout.y,
-+			EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP);
-+
-+	set_reg_field_value(overscan_top_bottom, overscan_bottom,
-+			EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM);
-+
-+	dm_write_reg(xfm_dce->base.ctx,
-+			mmSCLV_EXT_OVERSCAN_LEFT_RIGHT,
-+			overscan_left_right);
-+
-+	dm_write_reg(xfm_dce->base.ctx,
-+			mmSCLV_EXT_OVERSCAN_TOP_BOTTOM,
-+			overscan_top_bottom);
-+}
-+
-+static void set_coeff_update_complete(
-+		struct dce_transform *xfm_dce)
-+{
-+	uint32_t value;
-+
-+	value = dm_read_reg(xfm_dce->base.ctx, mmSCLV_UPDATE);
-+	set_reg_field_value(value, 1, SCLV_UPDATE, SCL_COEF_UPDATE_COMPLETE);
-+	dm_write_reg(xfm_dce->base.ctx, mmSCLV_UPDATE, value);
-+}
-+
-+static void program_multi_taps_filter(
-+	struct dce_transform *xfm_dce,
-+	int taps,
-+	const uint16_t *coeffs,
-+	enum ram_filter_type filter_type)
-+{
-+	struct dc_context *ctx = xfm_dce->base.ctx;
-+	int i, phase, pair;
-+	int array_idx = 0;
-+	int taps_pairs = (taps + 1) / 2;
-+	int phases_to_program = SCLV_PHASES / 2 + 1;
-+
-+	uint32_t select = 0;
-+	uint32_t power_ctl, power_ctl_off;
-+
-+	if (!coeffs)
-+		return;
-+
-+	/*We need to disable power gating on coeff memory to do programming*/
-+	power_ctl = dm_read_reg(ctx, mmDCFEV_MEM_PWR_CTRL);
-+	power_ctl_off = power_ctl;
-+	set_reg_field_value(power_ctl_off, 1, DCFEV_MEM_PWR_CTRL, SCLV_COEFF_MEM_PWR_DIS);
-+	dm_write_reg(ctx, mmDCFEV_MEM_PWR_CTRL, power_ctl_off);
-+
-+	/*Wait to disable gating:*/
-+	for (i = 0; i < 10; i++) {
-+		if (get_reg_field_value(
-+				dm_read_reg(ctx, mmDCFEV_MEM_PWR_STATUS),
-+				DCFEV_MEM_PWR_STATUS,
-+				SCLV_COEFF_MEM_PWR_STATE) == 0)
-+			break;
-+
-+		udelay(1);
-+	}
-+
-+	set_reg_field_value(select, filter_type, SCLV_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE);
-+
-+	for (phase = 0; phase < phases_to_program; phase++) {
-+		/*we always program N/2 + 1 phases, total phases N, but N/2-1 are just mirror
-+		phase 0 is unique and phase N/2 is unique if N is even*/
-+		set_reg_field_value(select, phase, SCLV_COEF_RAM_SELECT, SCL_C_RAM_PHASE);
-+		for (pair = 0; pair < taps_pairs; pair++) {
-+			uint32_t data = 0;
-+
-+			set_reg_field_value(select, pair,
-+					SCLV_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX);
-+
-+			dm_write_reg(ctx, mmSCLV_COEF_RAM_SELECT, select);
-+
-+			set_reg_field_value(
-+					data, 1,
-+					SCLV_COEF_RAM_TAP_DATA,
-+					SCL_C_RAM_EVEN_TAP_COEF_EN);
-+			set_reg_field_value(
-+					data, coeffs[array_idx],
-+					SCLV_COEF_RAM_TAP_DATA,
-+					SCL_C_RAM_EVEN_TAP_COEF);
-+
-+			if (taps % 2 && pair == taps_pairs - 1) {
-+				set_reg_field_value(
-+						data, 0,
-+						SCLV_COEF_RAM_TAP_DATA,
-+						SCL_C_RAM_ODD_TAP_COEF_EN);
-+				array_idx++;
-+			} else {
-+				set_reg_field_value(
-+						data, 1,
-+						SCLV_COEF_RAM_TAP_DATA,
-+						SCL_C_RAM_ODD_TAP_COEF_EN);
-+				set_reg_field_value(
-+						data, coeffs[array_idx + 1],
-+						SCLV_COEF_RAM_TAP_DATA,
-+						SCL_C_RAM_ODD_TAP_COEF);
-+
-+				array_idx += 2;
-+			}
-+
-+			dm_write_reg(ctx, mmSCLV_COEF_RAM_TAP_DATA, data);
-+		}
-+	}
-+
-+	/*We need to restore power gating on coeff memory to initial state*/
-+	dm_write_reg(ctx, mmDCFEV_MEM_PWR_CTRL, power_ctl);
-+}
-+
-+static void calculate_inits(
-+	struct dce_transform *xfm_dce,
-+	const struct scaler_data *data,
-+	struct sclv_ratios_inits *inits,
-+	struct rect *luma_viewport,
-+	struct rect *chroma_viewport)
-+{
-+	inits->h_int_scale_ratio_luma =
-+		dal_fixed31_32_u2d19(data->ratios.horz) << 5;
-+	inits->v_int_scale_ratio_luma =
-+		dal_fixed31_32_u2d19(data->ratios.vert) << 5;
-+	inits->h_int_scale_ratio_chroma =
-+		dal_fixed31_32_u2d19(data->ratios.horz_c) << 5;
-+	inits->v_int_scale_ratio_chroma =
-+		dal_fixed31_32_u2d19(data->ratios.vert_c) << 5;
-+
-+	inits->h_init_luma.integer = 1;
-+	inits->v_init_luma.integer = 1;
-+	inits->h_init_chroma.integer = 1;
-+	inits->v_init_chroma.integer = 1;
-+}
-+
-+static void program_scl_ratios_inits(
-+	struct dce_transform *xfm_dce,
-+	struct sclv_ratios_inits *inits)
-+{
-+	struct dc_context *ctx = xfm_dce->base.ctx;
-+	uint32_t addr = mmSCLV_HORZ_FILTER_SCALE_RATIO;
-+	uint32_t value = 0;
-+
-+	set_reg_field_value(
-+		value,
-+		inits->h_int_scale_ratio_luma,
-+		SCLV_HORZ_FILTER_SCALE_RATIO,
-+		SCL_H_SCALE_RATIO);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_VERT_FILTER_SCALE_RATIO;
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->v_int_scale_ratio_luma,
-+		SCLV_VERT_FILTER_SCALE_RATIO,
-+		SCL_V_SCALE_RATIO);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_HORZ_FILTER_SCALE_RATIO_C;
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->h_int_scale_ratio_chroma,
-+		SCLV_HORZ_FILTER_SCALE_RATIO_C,
-+		SCL_H_SCALE_RATIO_C);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_VERT_FILTER_SCALE_RATIO_C;
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->v_int_scale_ratio_chroma,
-+		SCLV_VERT_FILTER_SCALE_RATIO_C,
-+		SCL_V_SCALE_RATIO_C);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_HORZ_FILTER_INIT;
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->h_init_luma.fraction,
-+		SCLV_HORZ_FILTER_INIT,
-+		SCL_H_INIT_FRAC);
-+	set_reg_field_value(
-+		value,
-+		inits->h_init_luma.integer,
-+		SCLV_HORZ_FILTER_INIT,
-+		SCL_H_INIT_INT);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_VERT_FILTER_INIT;
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->v_init_luma.fraction,
-+		SCLV_VERT_FILTER_INIT,
-+		SCL_V_INIT_FRAC);
-+	set_reg_field_value(
-+		value,
-+		inits->v_init_luma.integer,
-+		SCLV_VERT_FILTER_INIT,
-+		SCL_V_INIT_INT);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_HORZ_FILTER_INIT_C;
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->h_init_chroma.fraction,
-+		SCLV_HORZ_FILTER_INIT_C,
-+		SCL_H_INIT_FRAC_C);
-+	set_reg_field_value(
-+		value,
-+		inits->h_init_chroma.integer,
-+		SCLV_HORZ_FILTER_INIT_C,
-+		SCL_H_INIT_INT_C);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = mmSCLV_VERT_FILTER_INIT_C;
-+	value = 0;
-+	set_reg_field_value(
-+		value,
-+		inits->v_init_chroma.fraction,
-+		SCLV_VERT_FILTER_INIT_C,
-+		SCL_V_INIT_FRAC_C);
-+	set_reg_field_value(
-+		value,
-+		inits->v_init_chroma.integer,
-+		SCLV_VERT_FILTER_INIT_C,
-+		SCL_V_INIT_INT_C);
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static const uint16_t *get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
-+{
-+	if (taps == 4)
-+		return get_filter_4tap_64p(ratio);
-+	else if (taps == 2)
-+		return get_filter_2tap_64p();
-+	else if (taps == 1)
-+		return NULL;
-+	else {
-+		/* should never happen, bug */
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+}
-+
-+static bool dce110_xfmv_power_up_line_buffer(struct transform *xfm)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+	uint32_t value;
-+
-+	value = dm_read_reg(xfm_dce->base.ctx, mmLBV_MEMORY_CTRL);
-+
-+	/*Use all three pieces of memory always*/
-+	set_reg_field_value(value, 0, LBV_MEMORY_CTRL, LB_MEMORY_CONFIG);
-+	/*hard coded number DCE11 1712(0x6B0) Partitions: 720/960/1712*/
-+	set_reg_field_value(value, xfm_dce->lb_memory_size, LBV_MEMORY_CTRL,
-+			LB_MEMORY_SIZE);
-+
-+	dm_write_reg(xfm_dce->base.ctx, mmLBV_MEMORY_CTRL, value);
-+
-+	return true;
-+}
-+
-+static void dce110_xfmv_set_scaler(
-+	struct transform *xfm,
-+	const struct scaler_data *data)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+	bool is_scaling_required = false;
-+	bool filter_updated = false;
-+	const uint16_t *coeffs_v, *coeffs_h, *coeffs_h_c, *coeffs_v_c;
-+	struct rect luma_viewport = {0};
-+	struct rect chroma_viewport = {0};
-+
-+	dce110_xfmv_power_up_line_buffer(xfm);
-+	/* 1. Calculate viewport, viewport programming should happen after init
-+	 * calculations as they may require an adjustment in the viewport.
-+	 */
-+
-+	calculate_viewport(data, &luma_viewport, &chroma_viewport);
-+
-+	/* 2. Program overscan */
-+	program_overscan(xfm_dce, data);
-+
-+	/* 3. Program taps and configuration */
-+	is_scaling_required = setup_scaling_configuration(xfm_dce, data);
-+
-+	if (is_scaling_required) {
-+		/* 4. Calculate and program ratio, filter initialization */
-+
-+		struct sclv_ratios_inits inits = { 0 };
-+
-+		calculate_inits(
-+			xfm_dce,
-+			data,
-+			&inits,
-+			&luma_viewport,
-+			&chroma_viewport);
-+
-+		program_scl_ratios_inits(xfm_dce, &inits);
-+
-+		coeffs_v = get_filter_coeffs_64p(data->taps.v_taps, data->ratios.vert);
-+		coeffs_h = get_filter_coeffs_64p(data->taps.h_taps, data->ratios.horz);
-+		coeffs_v_c = get_filter_coeffs_64p(data->taps.v_taps_c, data->ratios.vert_c);
-+		coeffs_h_c = get_filter_coeffs_64p(data->taps.h_taps_c, data->ratios.horz_c);
-+
-+		if (coeffs_v != xfm_dce->filter_v
-+				|| coeffs_v_c != xfm_dce->filter_v_c
-+				|| coeffs_h != xfm_dce->filter_h
-+				|| coeffs_h_c != xfm_dce->filter_h_c) {
-+		/* 5. Program vertical filters */
-+			program_multi_taps_filter(
-+					xfm_dce,
-+					data->taps.v_taps,
-+					coeffs_v,
-+					FILTER_TYPE_RGB_Y_VERTICAL);
-+			program_multi_taps_filter(
-+					xfm_dce,
-+					data->taps.v_taps_c,
-+					coeffs_v_c,
-+					FILTER_TYPE_CBCR_VERTICAL);
-+
-+		/* 6. Program horizontal filters */
-+			program_multi_taps_filter(
-+					xfm_dce,
-+					data->taps.h_taps,
-+					coeffs_h,
-+					FILTER_TYPE_RGB_Y_HORIZONTAL);
-+			program_multi_taps_filter(
-+					xfm_dce,
-+					data->taps.h_taps_c,
-+					coeffs_h_c,
-+					FILTER_TYPE_CBCR_HORIZONTAL);
-+
-+			xfm_dce->filter_v = coeffs_v;
-+			xfm_dce->filter_v_c = coeffs_v_c;
-+			xfm_dce->filter_h = coeffs_h;
-+			xfm_dce->filter_h_c = coeffs_h_c;
-+			filter_updated = true;
-+		}
-+	}
-+
-+	/* 7. Program the viewport */
-+	program_viewport(xfm_dce, &luma_viewport, &chroma_viewport);
-+
-+	/* 8. Set bit to flip to new coefficient memory */
-+	if (filter_updated)
-+		set_coeff_update_complete(xfm_dce);
-+}
-+
-+static void dce110_xfmv_reset(struct transform *xfm)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+
-+	xfm_dce->filter_h = NULL;
-+	xfm_dce->filter_v = NULL;
-+	xfm_dce->filter_h_c = NULL;
-+	xfm_dce->filter_v_c = NULL;
-+}
-+
-+static void dce110_xfmv_set_gamut_remap(
-+	struct transform *xfm,
-+	const struct xfm_grph_csc_adjustment *adjust)
-+{
-+	/* DO NOTHING*/
-+}
-+
-+static void dce110_xfmv_set_pixel_storage_depth(
-+	struct transform *xfm,
-+	enum lb_pixel_depth depth,
-+	const struct bit_depth_reduction_params *bit_depth_params)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+	int pixel_depth = 0;
-+	int expan_mode = 0;
-+	uint32_t reg_data = 0;
-+
-+	switch (depth) {
-+	case LB_PIXEL_DEPTH_18BPP:
-+		pixel_depth = 2;
-+		expan_mode  = 1;
-+		break;
-+	case LB_PIXEL_DEPTH_24BPP:
-+		pixel_depth = 1;
-+		expan_mode  = 1;
-+		break;
-+	case LB_PIXEL_DEPTH_30BPP:
-+		pixel_depth = 0;
-+		expan_mode  = 1;
-+		break;
-+	case LB_PIXEL_DEPTH_36BPP:
-+		pixel_depth = 3;
-+		expan_mode  = 0;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+
-+	set_reg_field_value(
-+		reg_data,
-+		expan_mode,
-+		LBV_DATA_FORMAT,
-+		PIXEL_EXPAN_MODE);
-+
-+	set_reg_field_value(
-+		reg_data,
-+		pixel_depth,
-+		LBV_DATA_FORMAT,
-+		PIXEL_DEPTH);
-+
-+	dm_write_reg(xfm->ctx, mmLBV_DATA_FORMAT, reg_data);
-+
-+	if (!(xfm_dce->lb_pixel_depth_supported & depth)) {
-+		/*we should use unsupported capabilities
-+		 *  unless it is required by w/a*/
-+		dm_logger_write(xfm->ctx->logger, LOG_WARNING,
-+			"%s: Capability not supported",
-+			__func__);
-+	}
-+}
-+
-+static const struct transform_funcs dce110_xfmv_funcs = {
-+	.transform_reset = dce110_xfmv_reset,
-+	.transform_set_scaler = dce110_xfmv_set_scaler,
-+	.transform_set_gamut_remap =
-+		dce110_xfmv_set_gamut_remap,
-+	.opp_set_csc_default = dce110_opp_v_set_csc_default,
-+	.opp_set_csc_adjustment = dce110_opp_v_set_csc_adjustment,
-+	.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut_v,
-+	.opp_program_regamma_pwl = dce110_opp_program_regamma_pwl_v,
-+	.opp_set_regamma_mode = dce110_opp_set_regamma_mode_v,
-+	.transform_set_pixel_storage_depth =
-+			dce110_xfmv_set_pixel_storage_depth,
-+	.transform_get_optimal_number_of_taps =
-+		dce_transform_get_optimal_number_of_taps
-+};
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+bool dce110_transform_v_construct(
-+	struct dce_transform *xfm_dce,
-+	struct dc_context *ctx)
-+{
-+	xfm_dce->base.ctx = ctx;
-+
-+	xfm_dce->base.funcs = &dce110_xfmv_funcs;
-+
-+	xfm_dce->lb_pixel_depth_supported =
-+			LB_PIXEL_DEPTH_18BPP |
-+			LB_PIXEL_DEPTH_24BPP |
-+			LB_PIXEL_DEPTH_30BPP;
-+
-+	xfm_dce->prescaler_on = true;
-+	xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY;
-+	xfm_dce->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x6B0*/
-+
-+	return true;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h.0130~	2017-12-14 06:39:58.412903565 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h	2017-12-14 06:39:58.412903565 +0100
-@@ -0,0 +1,58 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TRANSFORM_V_DCE110_H__
-+#define __DAL_TRANSFORM_V_DCE110_H__
-+
-+#include "../dce/dce_transform.h"
-+
-+#define LB_TOTAL_NUMBER_OF_ENTRIES 1712
-+#define LB_BITS_PER_ENTRY 144
-+
-+bool dce110_transform_v_construct(
-+	struct dce_transform *xfm110,
-+	struct dc_context *ctx);
-+
-+void dce110_opp_v_set_csc_default(
-+	struct transform *xfm,
-+	const struct default_adjustment *default_adjust);
-+
-+void dce110_opp_v_set_csc_adjustment(
-+		struct transform *xfm,
-+	const struct out_csc_color_matrix *tbl_entry);
-+
-+
-+void dce110_opp_program_regamma_pwl_v(
-+	struct transform *xfm,
-+	const struct pwl_params *params);
-+
-+void dce110_opp_power_on_regamma_lut_v(
-+	struct transform *xfm,
-+	bool power_on);
-+
-+void dce110_opp_set_regamma_mode_v(
-+	struct transform *xfm,
-+	enum opp_regamma mode);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/Makefile.0130~	2017-12-14 06:39:58.412903565 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce110/Makefile	2017-12-14 06:39:58.412903565 +0100
-@@ -0,0 +1,12 @@
-+#
-+# Makefile for the 'controller' sub-component of DAL.
-+# It provides the control and status of HW CRTC block.
-+
-+DCE110 = dce110_timing_generator.o \
-+dce110_compressor.o dce110_hw_sequencer.o dce110_resource.o \
-+dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \
-+dce110_mem_input_v.o dce110_opp_v.o dce110_transform_v.o
-+
-+AMD_DAL_DCE110 = $(addprefix $(AMDDALPATH)/dc/dce110/,$(DCE110))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_DCE110)
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c.0130~	2017-12-14 06:39:58.412903565 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c	2017-12-14 06:39:58.412903565 +0100
-@@ -0,0 +1,854 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "dce/dce_11_2_d.h"
-+#include "dce/dce_11_2_sh_mask.h"
-+#include "gmc/gmc_8_1_sh_mask.h"
-+#include "gmc/gmc_8_1_d.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "dce112_compressor.h"
-+
-+#define DCP_REG(reg)\
-+	(reg + cp110->offsets.dcp_offset)
-+#define DMIF_REG(reg)\
-+	(reg + cp110->offsets.dmif_offset)
-+
-+static const struct dce112_compressor_reg_offsets reg_offsets[] = {
-+{
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset =
-+		(mmDMIF_PG0_DPG_PIPE_DPM_CONTROL
-+			- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset =
-+		(mmDMIF_PG1_DPG_PIPE_DPM_CONTROL
-+			- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset =
-+		(mmDMIF_PG2_DPG_PIPE_DPM_CONTROL
-+			- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+}
-+};
-+
-+static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;
-+
-+enum fbc_idle_force {
-+	/* Bit 0 - Display registers updated */
-+	FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001,
-+
-+	/* Bit 2 - FBC_GRPH_COMP_EN register updated */
-+	FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002,
-+	/* Bit 3 - FBC_SRC_SEL register updated */
-+	FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004,
-+	/* Bit 4 - FBC_MIN_COMPRESSION register updated */
-+	FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008,
-+	/* Bit 5 - FBC_ALPHA_COMP_EN register updated */
-+	FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010,
-+	/* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
-+	FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020,
-+	/* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
-+	FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040,
-+
-+	/* Bit 24 - Memory write to region 0 defined by MC registers. */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000,
-+	/* Bit 25 - Memory write to region 1 defined by MC registers */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000,
-+	/* Bit 26 - Memory write to region 2 defined by MC registers */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000,
-+	/* Bit 27 - Memory write to region 3 defined by MC registers. */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000,
-+
-+	/* Bit 28 - Memory write from any client other than MCIF */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000,
-+	/* Bit 29 - CG statics screen signal is inactive */
-+	FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000,
-+};
-+
-+static uint32_t lpt_size_alignment(struct dce112_compressor *cp110)
-+{
-+	/*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */
-+	return cp110->base.raw_size * cp110->base.banks_num *
-+		cp110->base.dram_channels_num;
-+}
-+
-+static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110,
-+	uint32_t lpt_control)
-+{
-+	/*LPT MC Config */
-+	if (cp110->base.options.bits.LPT_MC_CONFIG == 1) {
-+		/* POSSIBLE VALUES for LPT NUM_PIPES (DRAM CHANNELS):
-+		 * 00 - 1 CHANNEL
-+		 * 01 - 2 CHANNELS
-+		 * 02 - 4 OR 6 CHANNELS
-+		 * (Only for discrete GPU, N/A for CZ)
-+		 * 03 - 8 OR 12 CHANNELS
-+		 * (Only for discrete GPU, N/A for CZ) */
-+		switch (cp110->base.dram_channels_num) {
-+		case 2:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_PIPES);
-+			break;
-+		case 1:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_PIPES);
-+			break;
-+		default:
-+			dm_logger_write(
-+				cp110->base.ctx->logger, LOG_WARNING,
-+				"%s: Invalid LPT NUM_PIPES!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping for LPT NUM_BANKS is in
-+		 * GRPH_CONTROL.GRPH_NUM_BANKS register field
-+		 * Specifies the number of memory banks for tiling
-+		 * purposes. Only applies to 2D and 3D tiling modes.
-+		 * POSSIBLE VALUES:
-+		 * 00 - DCP_GRPH_NUM_BANKS_2BANK: ADDR_SURF_2_BANK
-+		 * 01 - DCP_GRPH_NUM_BANKS_4BANK: ADDR_SURF_4_BANK
-+		 * 02 - DCP_GRPH_NUM_BANKS_8BANK: ADDR_SURF_8_BANK
-+		 * 03 - DCP_GRPH_NUM_BANKS_16BANK: ADDR_SURF_16_BANK */
-+		switch (cp110->base.banks_num) {
-+		case 16:
-+			set_reg_field_value(
-+				lpt_control,
-+				3,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 8:
-+			set_reg_field_value(
-+				lpt_control,
-+				2,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 4:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 2:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		default:
-+			dm_logger_write(
-+				cp110->base.ctx->logger, LOG_WARNING,
-+				"%s: Invalid LPT NUM_BANKS!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping is in DMIF_ADDR_CALC.
-+		 * ADDR_CONFIG_PIPE_INTERLEAVE_SIZE register field for
-+		 * Carrizo specifies the memory interleave per pipe.
-+		 * It effectively specifies the location of pipe bits in
-+		 * the memory address.
-+		 * POSSIBLE VALUES:
-+		 * 00 - ADDR_CONFIG_PIPE_INTERLEAVE_256B: 256 byte
-+		 * interleave
-+		 * 01 - ADDR_CONFIG_PIPE_INTERLEAVE_512B: 512 byte
-+		 * interleave
-+		 */
-+		switch (cp110->base.channel_interleave_size) {
-+		case 256: /*256B */
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
-+			break;
-+		case 512: /*512B */
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
-+			break;
-+		default:
-+			dm_logger_write(
-+				cp110->base.ctx->logger, LOG_WARNING,
-+				"%s: Invalid LPT INTERLEAVE_SIZE!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping for LOW_POWER_TILING_ROW_SIZE is in
-+		 * DMIF_ADDR_CALC.ADDR_CONFIG_ROW_SIZE register field
-+		 * for Carrizo. Specifies the size of dram row in bytes.
-+		 * This should match up with NOOFCOLS field in
-+		 * MC_ARB_RAMCFG (ROW_SIZE = 4 * 2 ^^ columns).
-+		 * This register DMIF_ADDR_CALC is not used by the
-+		 * hardware as it is only used for addrlib assertions.
-+		 * POSSIBLE VALUES:
-+		 * 00 - ADDR_CONFIG_1KB_ROW: Treat 1KB as DRAM row
-+		 * boundary
-+		 * 01 - ADDR_CONFIG_2KB_ROW: Treat 2KB as DRAM row
-+		 * boundary
-+		 * 02 - ADDR_CONFIG_4KB_ROW: Treat 4KB as DRAM row
-+		 * boundary */
-+		switch (cp110->base.raw_size) {
-+		case 4096: /*4 KB */
-+			set_reg_field_value(
-+				lpt_control,
-+				2,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		case 2048:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		case 1024:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		default:
-+			dm_logger_write(
-+				cp110->base.ctx->logger, LOG_WARNING,
-+				"%s: Invalid LPT ROW_SIZE!!!",
-+				__func__);
-+			break;
-+		}
-+	} else {
-+		dm_logger_write(
-+			cp110->base.ctx->logger, LOG_WARNING,
-+			"%s: LPT MC Configuration is not provided",
-+			__func__);
-+	}
-+
-+	return lpt_control;
-+}
-+
-+static bool is_source_bigger_than_epanel_size(
-+	struct dce112_compressor *cp110,
-+	uint32_t source_view_width,
-+	uint32_t source_view_height)
-+{
-+	if (cp110->base.embedded_panel_h_size != 0 &&
-+		cp110->base.embedded_panel_v_size != 0 &&
-+		((source_view_width * source_view_height) >
-+		(cp110->base.embedded_panel_h_size *
-+			cp110->base.embedded_panel_v_size)))
-+		return true;
-+
-+	return false;
-+}
-+
-+static uint32_t align_to_chunks_number_per_line(
-+	struct dce112_compressor *cp110,
-+	uint32_t pixels)
-+{
-+	return 256 * ((pixels + 255) / 256);
-+}
-+
-+static void wait_for_fbc_state_changed(
-+	struct dce112_compressor *cp110,
-+	bool enabled)
-+{
-+	uint8_t counter = 0;
-+	uint32_t addr = mmFBC_STATUS;
-+	uint32_t value;
-+
-+	while (counter < 10) {
-+		value = dm_read_reg(cp110->base.ctx, addr);
-+		if (get_reg_field_value(
-+			value,
-+			FBC_STATUS,
-+			FBC_ENABLE_STATUS) == enabled)
-+			break;
-+		udelay(10);
-+		counter++;
-+	}
-+
-+	if (counter == 10) {
-+		dm_logger_write(
-+			cp110->base.ctx->logger, LOG_WARNING,
-+			"%s: wait counter exceeded, changes to HW not applied",
-+			__func__);
-+	}
-+}
-+
-+void dce112_compressor_power_up_fbc(struct compressor *compressor)
-+{
-+	uint32_t value;
-+	uint32_t addr;
-+
-+	addr = mmFBC_CNTL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+	set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
-+	set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
-+	if (compressor->options.bits.CLK_GATING_DISABLED == 1) {
-+		/* HW needs to do power measurement comparison. */
-+		set_reg_field_value(
-+			value,
-+			0,
-+			FBC_CNTL,
-+			FBC_COMP_CLK_GATE_EN);
-+	}
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	addr = mmFBC_COMP_MODE;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	addr = mmFBC_COMP_CNTL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN);
-+	dm_write_reg(compressor->ctx, addr, value);
-+	/*FBC_MIN_COMPRESSION 0 ==> 2:1 */
-+	/*                    1 ==> 4:1 */
-+	/*                    2 ==> 8:1 */
-+	/*                  0xF ==> 1:1 */
-+	set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION);
-+	dm_write_reg(compressor->ctx, addr, value);
-+	compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;
-+
-+	value = 0;
-+	dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
-+
-+	value = 0xFFFFFF;
-+	dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
-+}
-+
-+void dce112_compressor_enable_fbc(
-+	struct compressor *compressor,
-+	uint32_t paths_num,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
-+
-+	if (compressor->options.bits.FBC_SUPPORT &&
-+		(compressor->options.bits.DUMMY_BACKEND == 0) &&
-+		(!dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) &&
-+		(!is_source_bigger_than_epanel_size(
-+			cp110,
-+			params->source_view_width,
-+			params->source_view_height))) {
-+
-+		uint32_t addr;
-+		uint32_t value;
-+
-+		/* Before enabling FBC first need to enable LPT if applicable
-+		 * LPT state should always be changed (enable/disable) while FBC
-+		 * is disabled */
-+		if (compressor->options.bits.LPT_SUPPORT && (paths_num < 2) &&
-+			(params->source_view_width *
-+				params->source_view_height <=
-+				dce11_one_lpt_channel_max_resolution)) {
-+			dce112_compressor_enable_lpt(compressor);
-+		}
-+
-+		addr = mmFBC_CNTL;
-+		value = dm_read_reg(compressor->ctx, addr);
-+		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		set_reg_field_value(
-+			value,
-+			params->inst,
-+			FBC_CNTL, FBC_SRC_SEL);
-+		dm_write_reg(compressor->ctx, addr, value);
-+
-+		/* Keep track of enum controller_id FBC is attached to */
-+		compressor->is_enabled = true;
-+		compressor->attached_inst = params->inst;
-+		cp110->offsets = reg_offsets[params->inst];
-+
-+		/*Toggle it as there is bug in HW */
-+		set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, addr, value);
-+		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, addr, value);
-+
-+		wait_for_fbc_state_changed(cp110, true);
-+	}
-+}
-+
-+void dce112_compressor_disable_fbc(struct compressor *compressor)
-+{
-+	struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
-+
-+	if (compressor->options.bits.FBC_SUPPORT &&
-+		dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
-+		uint32_t reg_data;
-+		/* Turn off compression */
-+		reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
-+		set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
-+
-+		/* Reset enum controller_id to undefined */
-+		compressor->attached_inst = 0;
-+		compressor->is_enabled = false;
-+
-+		/* Whenever disabling FBC make sure LPT is disabled if LPT
-+		 * supported */
-+		if (compressor->options.bits.LPT_SUPPORT)
-+			dce112_compressor_disable_lpt(compressor);
-+
-+		wait_for_fbc_state_changed(cp110, false);
-+	}
-+}
-+
-+bool dce112_compressor_is_fbc_enabled_in_hw(
-+	struct compressor *compressor,
-+	uint32_t *inst)
-+{
-+	/* Check the hardware register */
-+	uint32_t value;
-+
-+	value = dm_read_reg(compressor->ctx, mmFBC_STATUS);
-+	if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
-+		if (inst != NULL)
-+			*inst = compressor->attached_inst;
-+		return true;
-+	}
-+
-+	value = dm_read_reg(compressor->ctx, mmFBC_MISC);
-+	if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {
-+		value = dm_read_reg(compressor->ctx, mmFBC_CNTL);
-+
-+		if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
-+			if (inst != NULL)
-+				*inst =
-+					compressor->attached_inst;
-+			return true;
-+		}
-+	}
-+	return false;
-+}
-+
-+bool dce112_compressor_is_lpt_enabled_in_hw(struct compressor *compressor)
-+{
-+	/* Check the hardware register */
-+	uint32_t value = dm_read_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL);
-+
-+	return get_reg_field_value(
-+		value,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+}
-+
-+void dce112_compressor_program_compressed_surface_address_and_pitch(
-+	struct compressor *compressor,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
-+	uint32_t value = 0;
-+	uint32_t fbc_pitch = 0;
-+	uint32_t compressed_surf_address_low_part =
-+		compressor->compr_surface_address.addr.low_part;
-+
-+	/* Clear content first. */
-+	dm_write_reg(
-+		compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
-+		0);
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0);
-+
-+	if (compressor->options.bits.LPT_SUPPORT) {
-+		uint32_t lpt_alignment = lpt_size_alignment(cp110);
-+
-+		if (lpt_alignment != 0) {
-+			compressed_surf_address_low_part =
-+				((compressed_surf_address_low_part
-+					+ (lpt_alignment - 1)) / lpt_alignment)
-+					* lpt_alignment;
-+		}
-+	}
-+
-+	/* Write address, HIGH has to be first. */
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
-+		compressor->compr_surface_address.addr.high_part);
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS),
-+		compressed_surf_address_low_part);
-+
-+	fbc_pitch = align_to_chunks_number_per_line(
-+		cp110,
-+		params->source_view_width);
-+
-+	if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
-+		fbc_pitch = fbc_pitch / 8;
-+	else
-+		dm_logger_write(
-+			compressor->ctx->logger, LOG_WARNING,
-+			"%s: Unexpected DCE11 compression ratio",
-+			__func__);
-+
-+	/* Clear content first. */
-+	dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);
-+
-+	/* Write FBC Pitch. */
-+	set_reg_field_value(
-+		value,
-+		fbc_pitch,
-+		GRPH_COMPRESS_PITCH,
-+		GRPH_COMPRESS_PITCH);
-+	dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);
-+
-+}
-+
-+void dce112_compressor_disable_lpt(struct compressor *compressor)
-+{
-+	struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
-+	uint32_t value;
-+	uint32_t addr;
-+	uint32_t inx;
-+
-+	/* Disable all pipes LPT Stutter */
-+	for (inx = 0; inx < 3; inx++) {
-+		value =
-+			dm_read_reg(
-+				compressor->ctx,
-+				DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
-+			STUTTER_ENABLE_NONLPTCH);
-+		dm_write_reg(
-+			compressor->ctx,
-+			DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH),
-+			value);
-+	}
-+	/* Disable Underlay pipe LPT Stutter */
-+	addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH,
-+		STUTTER_ENABLE_NONLPTCH);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Disable LPT */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Clear selection of Channel(s) containing Compressed Surface */
-+	addr = mmGMCON_LPT_TARGET;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0xFFFFFFFF,
-+		GMCON_LPT_TARGET,
-+		STCTRL_LPT_TARGET);
-+	dm_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value);
-+}
-+
-+void dce112_compressor_enable_lpt(struct compressor *compressor)
-+{
-+	struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
-+	uint32_t value;
-+	uint32_t addr;
-+	uint32_t value_control;
-+	uint32_t channels;
-+
-+	/* Enable LPT Stutter from Display pipe */
-+	value = dm_read_reg(compressor->ctx,
-+		DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
-+		STUTTER_ENABLE_NONLPTCH);
-+	dm_write_reg(compressor->ctx,
-+		DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), value);
-+
-+	/* Enable Underlay pipe LPT Stutter */
-+	addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH,
-+		STUTTER_ENABLE_NONLPTCH);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Selection of Channel(s) containing Compressed Surface: 0xfffffff
-+	 * will disable LPT.
-+	 * STCTRL_LPT_TARGETn corresponds to channel n. */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value_control = dm_read_reg(compressor->ctx, addr);
-+	channels = get_reg_field_value(value_control,
-+			LOW_POWER_TILING_CONTROL,
-+			LOW_POWER_TILING_MODE);
-+
-+	addr = mmGMCON_LPT_TARGET;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		channels + 1, /* not mentioned in programming guide,
-+				but follow DCE8.1 */
-+		GMCON_LPT_TARGET,
-+		STCTRL_LPT_TARGET);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Enable LPT */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+	dm_write_reg(compressor->ctx, addr, value);
-+}
-+
-+void dce112_compressor_program_lpt_control(
-+	struct compressor *compressor,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
-+	uint32_t rows_per_channel;
-+	uint32_t lpt_alignment;
-+	uint32_t source_view_width;
-+	uint32_t source_view_height;
-+	uint32_t lpt_control = 0;
-+
-+	if (!compressor->options.bits.LPT_SUPPORT)
-+		return;
-+
-+	lpt_control = dm_read_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL);
-+
-+	/* POSSIBLE VALUES for Low Power Tiling Mode:
-+	 * 00 - Use channel 0
-+	 * 01 - Use Channel 0 and 1
-+	 * 02 - Use Channel 0,1,2,3
-+	 * 03 - reserved */
-+	switch (compressor->lpt_channels_num) {
-+	/* case 2:
-+	 * Use Channel 0 & 1 / Not used for DCE 11 */
-+	case 1:
-+		/*Use Channel 0 for LPT for DCE 11 */
-+		set_reg_field_value(
-+			lpt_control,
-+			0,
-+			LOW_POWER_TILING_CONTROL,
-+			LOW_POWER_TILING_MODE);
-+		break;
-+	default:
-+		dm_logger_write(
-+			compressor->ctx->logger, LOG_WARNING,
-+			"%s: Invalid selected DRAM channels for LPT!!!",
-+			__func__);
-+		break;
-+	}
-+
-+	lpt_control = lpt_memory_control_config(cp110, lpt_control);
-+
-+	/* Program LOW_POWER_TILING_ROWS_PER_CHAN field which depends on
-+	 * FBC compressed surface pitch.
-+	 * LOW_POWER_TILING_ROWS_PER_CHAN = Roundup ((Surface Height *
-+	 * Surface Pitch) / (Row Size * Number of Channels *
-+	 * Number of Banks)). */
-+	rows_per_channel = 0;
-+	lpt_alignment = lpt_size_alignment(cp110);
-+	source_view_width =
-+		align_to_chunks_number_per_line(
-+			cp110,
-+			params->source_view_width);
-+	source_view_height = (params->source_view_height + 1) & (~0x1);
-+
-+	if (lpt_alignment != 0) {
-+		rows_per_channel = source_view_width * source_view_height * 4;
-+		rows_per_channel =
-+			(rows_per_channel % lpt_alignment) ?
-+				(rows_per_channel / lpt_alignment + 1) :
-+				rows_per_channel / lpt_alignment;
-+	}
-+
-+	set_reg_field_value(
-+		lpt_control,
-+		rows_per_channel,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ROWS_PER_CHAN);
-+
-+	dm_write_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL, lpt_control);
-+}
-+
-+/*
-+ * DCE 11 Frame Buffer Compression Implementation
-+ */
-+
-+void dce112_compressor_set_fbc_invalidation_triggers(
-+	struct compressor *compressor,
-+	uint32_t fbc_trigger)
-+{
-+	/* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19)
-+	 * for DCE 11 regions cannot be used - does not work with S/G
-+	 */
-+	uint32_t addr = mmFBC_CLIENT_REGION_MASK;
-+	uint32_t value = dm_read_reg(compressor->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		FBC_CLIENT_REGION_MASK,
-+		FBC_MEMORY_REGION_MASK);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Setup events when to clear all CSM entries (effectively marking
-+	 * current compressed data invalid)
-+	 * For DCE 11 CSM metadata 11111 means - "Not Compressed"
-+	 * Used as the initial value of the metadata sent to the compressor
-+	 * after invalidation, to indicate that the compressor should attempt
-+	 * to compress all chunks on the current pass.  Also used when the chunk
-+	 * is not successfully written to memory.
-+	 * When this CSM value is detected, FBC reads from the uncompressed
-+	 * buffer. Set events according to passed in value, these events are
-+	 * valid for DCE11:
-+	 *     - bit  0 - display register updated
-+	 *     - bit 28 - memory write from any client except from MCIF
-+	 *     - bit 29 - CG static screen signal is inactive
-+	 * In addition, DCE11.1 also needs to set new DCE11.1 specific events
-+	 * that are used to trigger invalidation on certain register changes,
-+	 * for example enabling of Alpha Compression may trigger invalidation of
-+	 * FBC once bit is set. These events are as follows:
-+	 *      - Bit 2 - FBC_GRPH_COMP_EN register updated
-+	 *      - Bit 3 - FBC_SRC_SEL register updated
-+	 *      - Bit 4 - FBC_MIN_COMPRESSION register updated
-+	 *      - Bit 5 - FBC_ALPHA_COMP_EN register updated
-+	 *      - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated
-+	 *      - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated
-+	 */
-+	addr = mmFBC_IDLE_FORCE_CLEAR_MASK;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		fbc_trigger |
-+		FBC_IDLE_FORCE_GRPH_COMP_EN |
-+		FBC_IDLE_FORCE_SRC_SEL_CHANGE |
-+		FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE |
-+		FBC_IDLE_FORCE_ALPHA_COMP_EN |
-+		FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN |
-+		FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF,
-+		FBC_IDLE_FORCE_CLEAR_MASK,
-+		FBC_IDLE_FORCE_CLEAR_MASK);
-+	dm_write_reg(compressor->ctx, addr, value);
-+}
-+
-+void dce112_compressor_construct(struct dce112_compressor *compressor,
-+	struct dc_context *ctx)
-+{
-+	struct dc_bios *bp = ctx->dc_bios;
-+	struct embedded_panel_info panel_info;
-+
-+	compressor->base.options.raw = 0;
-+	compressor->base.options.bits.FBC_SUPPORT = true;
-+	compressor->base.options.bits.LPT_SUPPORT = true;
-+	 /* For DCE 11 always use one DRAM channel for LPT */
-+	compressor->base.lpt_channels_num = 1;
-+	compressor->base.options.bits.DUMMY_BACKEND = false;
-+
-+	/* Check if this system has more than 1 DRAM channel; if only 1 then LPT
-+	 * should not be supported */
-+	if (compressor->base.memory_bus_width == 64)
-+		compressor->base.options.bits.LPT_SUPPORT = false;
-+
-+	compressor->base.options.bits.CLK_GATING_DISABLED = false;
-+
-+	compressor->base.ctx = ctx;
-+	compressor->base.embedded_panel_h_size = 0;
-+	compressor->base.embedded_panel_v_size = 0;
-+	compressor->base.memory_bus_width = ctx->asic_id.vram_width;
-+	compressor->base.allocated_size = 0;
-+	compressor->base.preferred_requested_size = 0;
-+	compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
-+	compressor->base.banks_num = 0;
-+	compressor->base.raw_size = 0;
-+	compressor->base.channel_interleave_size = 0;
-+	compressor->base.dram_channels_num = 0;
-+	compressor->base.lpt_channels_num = 0;
-+	compressor->base.attached_inst = 0;
-+	compressor->base.is_enabled = false;
-+
-+	if (BP_RESULT_OK ==
-+			bp->funcs->get_embedded_panel_info(bp, &panel_info)) {
-+		compressor->base.embedded_panel_h_size =
-+			panel_info.lcd_timing.horizontal_addressable;
-+		compressor->base.embedded_panel_v_size =
-+			panel_info.lcd_timing.vertical_addressable;
-+	}
-+}
-+
-+struct compressor *dce112_compressor_create(struct dc_context *ctx)
-+{
-+	struct dce112_compressor *cp110 =
-+		kzalloc(sizeof(struct dce112_compressor), GFP_KERNEL);
-+
-+	if (!cp110)
-+		return NULL;
-+
-+	dce112_compressor_construct(cp110, ctx);
-+	return &cp110->base;
-+}
-+
-+void dce112_compressor_destroy(struct compressor **compressor)
-+{
-+	kfree(TO_DCE112_COMPRESSOR(*compressor));
-+	*compressor = NULL;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h.0130~	2017-12-14 06:39:58.412903565 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h	2017-12-14 06:39:58.412903565 +0100
-@@ -0,0 +1,78 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_COMPRESSOR_DCE112_H__
-+#define __DC_COMPRESSOR_DCE112_H__
-+
-+#include "../inc/compressor.h"
-+
-+#define TO_DCE112_COMPRESSOR(compressor)\
-+	container_of(compressor, struct dce112_compressor, base)
-+
-+struct dce112_compressor_reg_offsets {
-+	uint32_t dcp_offset;
-+	uint32_t dmif_offset;
-+};
-+
-+struct dce112_compressor {
-+	struct compressor base;
-+	struct dce112_compressor_reg_offsets offsets;
-+};
-+
-+struct compressor *dce112_compressor_create(struct dc_context *ctx);
-+
-+void dce112_compressor_construct(struct dce112_compressor *cp110,
-+	struct dc_context *ctx);
-+
-+void dce112_compressor_destroy(struct compressor **cp);
-+
-+/* FBC RELATED */
-+void dce112_compressor_power_up_fbc(struct compressor *cp);
-+
-+void dce112_compressor_enable_fbc(struct compressor *cp, uint32_t paths_num,
-+	struct compr_addr_and_pitch_params *params);
-+
-+void dce112_compressor_disable_fbc(struct compressor *cp);
-+
-+void dce112_compressor_set_fbc_invalidation_triggers(struct compressor *cp,
-+	uint32_t fbc_trigger);
-+
-+void dce112_compressor_program_compressed_surface_address_and_pitch(
-+	struct compressor *cp,
-+	struct compr_addr_and_pitch_params *params);
-+
-+bool dce112_compressor_is_fbc_enabled_in_hw(struct compressor *cp,
-+	uint32_t *fbc_mapped_crtc_id);
-+
-+/* LPT RELATED */
-+void dce112_compressor_enable_lpt(struct compressor *cp);
-+
-+void dce112_compressor_disable_lpt(struct compressor *cp);
-+
-+void dce112_compressor_program_lpt_control(struct compressor *cp,
-+	struct compr_addr_and_pitch_params *params);
-+
-+bool dce112_compressor_is_lpt_enabled_in_hw(struct compressor *cp);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c.0130~	2017-12-14 06:39:58.412903565 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c	2017-12-14 06:39:58.412903565 +0100
-@@ -0,0 +1,163 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dc.h"
-+#include "core_types.h"
-+#include "dce112_hw_sequencer.h"
-+
-+#include "dce110/dce110_hw_sequencer.h"
-+
-+/* include DCE11.2 register header files */
-+#include "dce/dce_11_2_d.h"
-+#include "dce/dce_11_2_sh_mask.h"
-+
-+struct dce112_hw_seq_reg_offsets {
-+	uint32_t crtc;
-+};
-+
-+
-+static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
-+{
-+	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+}
-+};
-+#define HW_REG_CRTC(reg, id)\
-+	(reg + reg_offsets[id].crtc)
-+
-+/*******************************************************************************
-+ * Private definitions
-+ ******************************************************************************/
-+
-+static void dce112_init_pte(struct dc_context *ctx)
-+{
-+	uint32_t addr;
-+	uint32_t value = 0;
-+	uint32_t chunk_int = 0;
-+	uint32_t chunk_mul = 0;
-+
-+	addr = mmDVMM_PTE_REQ;
-+	value = dm_read_reg(ctx, addr);
-+
-+	chunk_int = get_reg_field_value(
-+		value,
-+		DVMM_PTE_REQ,
-+		HFLIP_PTEREQ_PER_CHUNK_INT);
-+
-+	chunk_mul = get_reg_field_value(
-+		value,
-+		DVMM_PTE_REQ,
-+		HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
-+
-+	if (chunk_int != 0x4 || chunk_mul != 0x4) {
-+
-+		set_reg_field_value(
-+			value,
-+			255,
-+			DVMM_PTE_REQ,
-+			MAX_PTEREQ_TO_ISSUE);
-+
-+		set_reg_field_value(
-+			value,
-+			4,
-+			DVMM_PTE_REQ,
-+			HFLIP_PTEREQ_PER_CHUNK_INT);
-+
-+		set_reg_field_value(
-+			value,
-+			4,
-+			DVMM_PTE_REQ,
-+			HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+}
-+
-+static bool dce112_enable_display_power_gating(
-+	struct dc *dc,
-+	uint8_t controller_id,
-+	struct dc_bios *dcb,
-+	enum pipe_gating_control power_gating)
-+{
-+	enum bp_result bp_result = BP_RESULT_OK;
-+	enum bp_pipe_control_action cntl;
-+	struct dc_context *ctx = dc->ctx;
-+
-+	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
-+		return true;
-+
-+	if (power_gating == PIPE_GATING_CONTROL_INIT)
-+		cntl = ASIC_PIPE_INIT;
-+	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
-+		cntl = ASIC_PIPE_ENABLE;
-+	else
-+		cntl = ASIC_PIPE_DISABLE;
-+
-+	if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
-+
-+		bp_result = dcb->funcs->enable_disp_power_gating(
-+						dcb, controller_id + 1, cntl);
-+
-+		/* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
-+		 * by default when command table is called
-+		 */
-+		dm_write_reg(ctx,
-+			HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
-+			0);
-+	}
-+
-+	if (power_gating != PIPE_GATING_CONTROL_ENABLE)
-+		dce112_init_pte(ctx);
-+
-+	if (bp_result == BP_RESULT_OK)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+void dce112_hw_sequencer_construct(struct dc *dc)
-+{
-+	/* All registers used by dce11.2 match those in dce11 in offset and
-+	 * structure
-+	 */
-+	dce110_hw_sequencer_construct(dc);
-+	dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h.0130~	2017-12-14 06:39:58.412903565 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h	2017-12-14 06:39:58.412903565 +0100
-@@ -0,0 +1,36 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_HWSS_DCE112_H__
-+#define __DC_HWSS_DCE112_H__
-+
-+#include "core_types.h"
-+
-+struct dc;
-+
-+void dce112_hw_sequencer_construct(struct dc *dc);
-+
-+#endif /* __DC_HWSS_DCE112_H__ */
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c.0130~	2017-12-14 06:39:58.412903565 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c	2017-12-14 06:39:58.412903565 +0100
-@@ -0,0 +1,1283 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "link_encoder.h"
-+#include "stream_encoder.h"
-+
-+#include "resource.h"
-+#include "include/irq_service_interface.h"
-+#include "dce110/dce110_resource.h"
-+#include "dce110/dce110_timing_generator.h"
-+
-+#include "irq/dce110/irq_service_dce110.h"
-+
-+#include "dce/dce_mem_input.h"
-+#include "dce/dce_transform.h"
-+#include "dce/dce_link_encoder.h"
-+#include "dce/dce_stream_encoder.h"
-+#include "dce/dce_audio.h"
-+#include "dce/dce_opp.h"
-+#include "dce/dce_ipp.h"
-+#include "dce/dce_clocks.h"
-+#include "dce/dce_clock_source.h"
-+
-+#include "dce/dce_hwseq.h"
-+#include "dce112/dce112_hw_sequencer.h"
-+#include "dce/dce_abm.h"
-+#include "dce/dce_dmcu.h"
-+
-+#include "reg_helper.h"
-+
-+#include "dce/dce_11_2_d.h"
-+#include "dce/dce_11_2_sh_mask.h"
-+
-+#include "dce100/dce100_resource.h"
-+
-+#ifndef mmDP_DPHY_INTERNAL_CTRL
-+	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
-+	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
-+	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
-+	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
-+	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
-+	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
-+	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
-+	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
-+	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
-+	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
-+#endif
-+
-+#ifndef mmBIOS_SCRATCH_2
-+	#define mmBIOS_SCRATCH_2 0x05CB
-+	#define mmBIOS_SCRATCH_6 0x05CF
-+#endif
-+
-+#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
-+	#define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
-+	#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
-+	#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
-+	#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
-+	#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
-+	#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
-+	#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
-+	#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
-+#endif
-+
-+#ifndef mmDP_DPHY_FAST_TRAINING
-+	#define mmDP_DPHY_FAST_TRAINING                         0x4ABC
-+	#define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
-+	#define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
-+	#define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
-+	#define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
-+	#define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
-+	#define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
-+	#define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
-+#endif
-+
-+enum dce112_clk_src_array_id {
-+	DCE112_CLK_SRC_PLL0,
-+	DCE112_CLK_SRC_PLL1,
-+	DCE112_CLK_SRC_PLL2,
-+	DCE112_CLK_SRC_PLL3,
-+	DCE112_CLK_SRC_PLL4,
-+	DCE112_CLK_SRC_PLL5,
-+
-+	DCE112_CLK_SRC_TOTAL
-+};
-+
-+static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
-+	{
-+		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
-+		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
-+	}
-+};
-+
-+/* set register offset */
-+#define SR(reg_name)\
-+	.reg_name = mm ## reg_name
-+
-+/* set register offset with instance */
-+#define SRI(reg_name, block, id)\
-+	.reg_name = mm ## block ## id ## _ ## reg_name
-+
-+
-+static const struct dce_disp_clk_registers disp_clk_regs = {
-+		CLK_COMMON_REG_LIST_DCE_BASE()
-+};
-+
-+static const struct dce_disp_clk_shift disp_clk_shift = {
-+		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
-+};
-+
-+static const struct dce_disp_clk_mask disp_clk_mask = {
-+		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
-+};
-+
-+static const struct dce_dmcu_registers dmcu_regs = {
-+		DMCU_DCE110_COMMON_REG_LIST()
-+};
-+
-+static const struct dce_dmcu_shift dmcu_shift = {
-+		DMCU_MASK_SH_LIST_DCE110(__SHIFT)
-+};
-+
-+static const struct dce_dmcu_mask dmcu_mask = {
-+		DMCU_MASK_SH_LIST_DCE110(_MASK)
-+};
-+
-+static const struct dce_abm_registers abm_regs = {
-+		ABM_DCE110_COMMON_REG_LIST()
-+};
-+
-+static const struct dce_abm_shift abm_shift = {
-+		ABM_MASK_SH_LIST_DCE110(__SHIFT)
-+};
-+
-+static const struct dce_abm_mask abm_mask = {
-+		ABM_MASK_SH_LIST_DCE110(_MASK)
-+};
-+
-+#define ipp_regs(id)\
-+[id] = {\
-+		IPP_DCE110_REG_LIST_DCE_BASE(id)\
-+}
-+
-+static const struct dce_ipp_registers ipp_regs[] = {
-+		ipp_regs(0),
-+		ipp_regs(1),
-+		ipp_regs(2),
-+		ipp_regs(3),
-+		ipp_regs(4),
-+		ipp_regs(5)
-+};
-+
-+static const struct dce_ipp_shift ipp_shift = {
-+		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
-+};
-+
-+static const struct dce_ipp_mask ipp_mask = {
-+		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
-+};
-+
-+#define transform_regs(id)\
-+[id] = {\
-+		XFM_COMMON_REG_LIST_DCE110(id)\
-+}
-+
-+static const struct dce_transform_registers xfm_regs[] = {
-+		transform_regs(0),
-+		transform_regs(1),
-+		transform_regs(2),
-+		transform_regs(3),
-+		transform_regs(4),
-+		transform_regs(5)
-+};
-+
-+static const struct dce_transform_shift xfm_shift = {
-+		XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-+};
-+
-+static const struct dce_transform_mask xfm_mask = {
-+		XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
-+};
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	AUX_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
-+		aux_regs(0),
-+		aux_regs(1),
-+		aux_regs(2),
-+		aux_regs(3),
-+		aux_regs(4),
-+		aux_regs(5)
-+};
-+
-+#define hpd_regs(id)\
-+[id] = {\
-+	HPD_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
-+		hpd_regs(0),
-+		hpd_regs(1),
-+		hpd_regs(2),
-+		hpd_regs(3),
-+		hpd_regs(4),
-+		hpd_regs(5)
-+};
-+
-+#define link_regs(id)\
-+[id] = {\
-+	LE_DCE110_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_registers link_enc_regs[] = {
-+	link_regs(0),
-+	link_regs(1),
-+	link_regs(2),
-+	link_regs(3),
-+	link_regs(4),
-+	link_regs(5),
-+	link_regs(6),
-+};
-+
-+#define stream_enc_regs(id)\
-+[id] = {\
-+	SE_COMMON_REG_LIST(id),\
-+	.TMDS_CNTL = 0,\
-+}
-+
-+static const struct dce110_stream_enc_registers stream_enc_regs[] = {
-+	stream_enc_regs(0),
-+	stream_enc_regs(1),
-+	stream_enc_regs(2),
-+	stream_enc_regs(3),
-+	stream_enc_regs(4),
-+	stream_enc_regs(5)
-+};
-+
-+static const struct dce_stream_encoder_shift se_shift = {
-+		SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
-+};
-+
-+static const struct dce_stream_encoder_mask se_mask = {
-+		SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
-+};
-+
-+#define opp_regs(id)\
-+[id] = {\
-+	OPP_DCE_112_REG_LIST(id),\
-+}
-+
-+static const struct dce_opp_registers opp_regs[] = {
-+	opp_regs(0),
-+	opp_regs(1),
-+	opp_regs(2),
-+	opp_regs(3),
-+	opp_regs(4),
-+	opp_regs(5)
-+};
-+
-+static const struct dce_opp_shift opp_shift = {
-+	OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
-+};
-+
-+static const struct dce_opp_mask opp_mask = {
-+	OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)
-+};
-+
-+#define audio_regs(id)\
-+[id] = {\
-+	AUD_COMMON_REG_LIST(id)\
-+}
-+
-+static const struct dce_audio_registers audio_regs[] = {
-+	audio_regs(0),
-+	audio_regs(1),
-+	audio_regs(2),
-+	audio_regs(3),
-+	audio_regs(4),
-+	audio_regs(5)
-+};
-+
-+static const struct dce_audio_shift audio_shift = {
-+		AUD_COMMON_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct dce_aduio_mask audio_mask = {
-+		AUD_COMMON_MASK_SH_LIST(_MASK)
-+};
-+
-+#define clk_src_regs(index, id)\
-+[index] = {\
-+	CS_COMMON_REG_LIST_DCE_112(id),\
-+}
-+
-+static const struct dce110_clk_src_regs clk_src_regs[] = {
-+	clk_src_regs(0, A),
-+	clk_src_regs(1, B),
-+	clk_src_regs(2, C),
-+	clk_src_regs(3, D),
-+	clk_src_regs(4, E),
-+	clk_src_regs(5, F)
-+};
-+
-+static const struct dce110_clk_src_shift cs_shift = {
-+		CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
-+};
-+
-+static const struct dce110_clk_src_mask cs_mask = {
-+		CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
-+};
-+
-+static const struct bios_registers bios_regs = {
-+	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
-+};
-+
-+static const struct resource_caps polaris_10_resource_cap = {
-+		.num_timing_generator = 6,
-+		.num_audio = 6,
-+		.num_stream_encoder = 6,
-+		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
-+};
-+
-+static const struct resource_caps polaris_11_resource_cap = {
-+		.num_timing_generator = 5,
-+		.num_audio = 5,
-+		.num_stream_encoder = 5,
-+		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
-+};
-+
-+#define CTX  ctx
-+#define REG(reg) mm ## reg
-+
-+#ifndef mmCC_DC_HDMI_STRAPS
-+#define mmCC_DC_HDMI_STRAPS 0x4819
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
-+#endif
-+
-+static void read_dce_straps(
-+	struct dc_context *ctx,
-+	struct resource_straps *straps)
-+{
-+	REG_GET_2(CC_DC_HDMI_STRAPS,
-+			HDMI_DISABLE, &straps->hdmi_disable,
-+			AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
-+
-+	REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
-+}
-+
-+static struct audio *create_audio(
-+		struct dc_context *ctx, unsigned int inst)
-+{
-+	return dce_audio_create(ctx, inst,
-+			&audio_regs[inst], &audio_shift, &audio_mask);
-+}
-+
-+
-+static struct timing_generator *dce112_timing_generator_create(
-+		struct dc_context *ctx,
-+		uint32_t instance,
-+		const struct dce110_timing_generator_offsets *offsets)
-+{
-+	struct dce110_timing_generator *tg110 =
-+		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
-+
-+	if (!tg110)
-+		return NULL;
-+
-+	dce110_timing_generator_construct(tg110, ctx, instance, offsets);
-+	return &tg110->base;
-+}
-+
-+static struct stream_encoder *dce112_stream_encoder_create(
-+	enum engine_id eng_id,
-+	struct dc_context *ctx)
-+{
-+	struct dce110_stream_encoder *enc110 =
-+		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
-+
-+	if (!enc110)
-+		return NULL;
-+	
-+	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
-+					&stream_enc_regs[eng_id],
-+					&se_shift, &se_mask);
-+	return &enc110->base;
-+}
-+
-+#define SRII(reg_name, block, id)\
-+	.reg_name[id] = mm ## block ## id ## _ ## reg_name
-+
-+static const struct dce_hwseq_registers hwseq_reg = {
-+		HWSEQ_DCE112_REG_LIST()
-+};
-+
-+static const struct dce_hwseq_shift hwseq_shift = {
-+		HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct dce_hwseq_mask hwseq_mask = {
-+		HWSEQ_DCE112_MASK_SH_LIST(_MASK)
-+};
-+
-+static struct dce_hwseq *dce112_hwseq_create(
-+	struct dc_context *ctx)
-+{
-+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
-+
-+	if (hws) {
-+		hws->ctx = ctx;
-+		hws->regs = &hwseq_reg;
-+		hws->shifts = &hwseq_shift;
-+		hws->masks = &hwseq_mask;
-+	}
-+	return hws;
-+}
-+
-+static const struct resource_create_funcs res_create_funcs = {
-+	.read_dce_straps = read_dce_straps,
-+	.create_audio = create_audio,
-+	.create_stream_encoder = dce112_stream_encoder_create,
-+	.create_hwseq = dce112_hwseq_create,
-+};
-+
-+#define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
-+static const struct dce_mem_input_registers mi_regs[] = {
-+		mi_inst_regs(0),
-+		mi_inst_regs(1),
-+		mi_inst_regs(2),
-+		mi_inst_regs(3),
-+		mi_inst_regs(4),
-+		mi_inst_regs(5),
-+};
-+
-+static const struct dce_mem_input_shift mi_shifts = {
-+		MI_DCE11_2_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct dce_mem_input_mask mi_masks = {
-+		MI_DCE11_2_MASK_SH_LIST(_MASK)
-+};
-+
-+static struct mem_input *dce112_mem_input_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
-+					       GFP_KERNEL);
-+
-+	if (!dce_mi) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
-+	return &dce_mi->base;
-+}
-+
-+static void dce112_transform_destroy(struct transform **xfm)
-+{
-+	kfree(TO_DCE_TRANSFORM(*xfm));
-+	*xfm = NULL;
-+}
-+
-+static struct transform *dce112_transform_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce_transform *transform =
-+		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
-+
-+	if (!transform)
-+		return NULL;
-+
-+	dce_transform_construct(transform, ctx, inst,
-+				&xfm_regs[inst], &xfm_shift, &xfm_mask);
-+	transform->lb_memory_size = 0x1404; /*5124*/
-+	return &transform->base;
-+}
-+
-+static const struct encoder_feature_support link_enc_feature = {
-+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
-+		.max_hdmi_pixel_clock = 600000,
-+		.ycbcr420_supported = true,
-+		.flags.bits.IS_HBR2_CAPABLE = true,
-+		.flags.bits.IS_HBR3_CAPABLE = true,
-+		.flags.bits.IS_TPS3_CAPABLE = true,
-+		.flags.bits.IS_TPS4_CAPABLE = true,
-+		.flags.bits.IS_YCBCR_CAPABLE = true
-+};
-+
-+struct link_encoder *dce112_link_encoder_create(
-+	const struct encoder_init_data *enc_init_data)
-+{
-+	struct dce110_link_encoder *enc110 =
-+		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	dce110_link_encoder_construct(enc110,
-+				      enc_init_data,
-+				      &link_enc_feature,
-+				      &link_enc_regs[enc_init_data->transmitter],
-+				      &link_enc_aux_regs[enc_init_data->channel - 1],
-+				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
-+	return &enc110->base;
-+}
-+
-+static struct input_pixel_processor *dce112_ipp_create(
-+	struct dc_context *ctx, uint32_t inst)
-+{
-+	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
-+
-+	if (!ipp) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dce_ipp_construct(ipp, ctx, inst,
-+			&ipp_regs[inst], &ipp_shift, &ipp_mask);
-+	return &ipp->base;
-+}
-+
-+struct output_pixel_processor *dce112_opp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce110_opp *opp =
-+		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
-+
-+	if (!opp)
-+		return NULL;
-+
-+	dce110_opp_construct(opp,
-+			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
-+	return &opp->base;
-+}
-+
-+struct clock_source *dce112_clock_source_create(
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id id,
-+	const struct dce110_clk_src_regs *regs,
-+	bool dp_clk_src)
-+{
-+	struct dce110_clk_src *clk_src =
-+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
-+
-+	if (!clk_src)
-+		return NULL;
-+
-+	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
-+			regs, &cs_shift, &cs_mask)) {
-+		clk_src->base.dp_clk_src = dp_clk_src;
-+		return &clk_src->base;
-+	}
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
-+void dce112_clock_source_destroy(struct clock_source **clk_src)
-+{
-+	kfree(TO_DCE110_CLK_SRC(*clk_src));
-+	*clk_src = NULL;
-+}
-+
-+static void destruct(struct dce110_resource_pool *pool)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < pool->base.pipe_count; i++) {
-+		if (pool->base.opps[i] != NULL)
-+			dce110_opp_destroy(&pool->base.opps[i]);
-+
-+		if (pool->base.transforms[i] != NULL)
-+			dce112_transform_destroy(&pool->base.transforms[i]);
-+
-+		if (pool->base.ipps[i] != NULL)
-+			dce_ipp_destroy(&pool->base.ipps[i]);
-+
-+		if (pool->base.mis[i] != NULL) {
-+			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
-+			pool->base.mis[i] = NULL;
-+		}
-+
-+		if (pool->base.timing_generators[i] != NULL) {
-+			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
-+			pool->base.timing_generators[i] = NULL;
-+		}
-+	}
-+
-+	for (i = 0; i < pool->base.stream_enc_count; i++) {
-+		if (pool->base.stream_enc[i] != NULL)
-+			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
-+	}
-+
-+	for (i = 0; i < pool->base.clk_src_count; i++) {
-+		if (pool->base.clock_sources[i] != NULL) {
-+			dce112_clock_source_destroy(&pool->base.clock_sources[i]);
-+		}
-+	}
-+
-+	if (pool->base.dp_clock_source != NULL)
-+		dce112_clock_source_destroy(&pool->base.dp_clock_source);
-+
-+	for (i = 0; i < pool->base.audio_count; i++)	{
-+		if (pool->base.audios[i] != NULL) {
-+			dce_aud_destroy(&pool->base.audios[i]);
-+		}
-+	}
-+
-+	if (pool->base.abm != NULL)
-+		dce_abm_destroy(&pool->base.abm);
-+
-+	if (pool->base.dmcu != NULL)
-+		dce_dmcu_destroy(&pool->base.dmcu);
-+
-+	if (pool->base.display_clock != NULL)
-+		dce_disp_clk_destroy(&pool->base.display_clock);
-+
-+	if (pool->base.irqs != NULL) {
-+		dal_irq_service_destroy(&pool->base.irqs);
-+	}
-+}
-+
-+static struct clock_source *find_matching_pll(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool,
-+		const struct dc_stream_state *const stream)
-+{
-+	switch (stream->sink->link->link_enc->transmitter) {
-+	case TRANSMITTER_UNIPHY_A:
-+		return pool->clock_sources[DCE112_CLK_SRC_PLL0];
-+	case TRANSMITTER_UNIPHY_B:
-+		return pool->clock_sources[DCE112_CLK_SRC_PLL1];
-+	case TRANSMITTER_UNIPHY_C:
-+		return pool->clock_sources[DCE112_CLK_SRC_PLL2];
-+	case TRANSMITTER_UNIPHY_D:
-+		return pool->clock_sources[DCE112_CLK_SRC_PLL3];
-+	case TRANSMITTER_UNIPHY_E:
-+		return pool->clock_sources[DCE112_CLK_SRC_PLL4];
-+	case TRANSMITTER_UNIPHY_F:
-+		return pool->clock_sources[DCE112_CLK_SRC_PLL5];
-+	default:
-+		return NULL;
-+	};
-+
-+	return 0;
-+}
-+
-+static enum dc_status build_mapped_resource(
-+		const struct dc *dc,
-+		struct dc_state *context,
-+		struct dc_stream_state *stream)
-+{
-+	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
-+
-+	if (!pipe_ctx)
-+		return DC_ERROR_UNEXPECTED;
-+
-+	dce110_resource_build_pipe_hw_param(pipe_ctx);
-+
-+	resource_build_info_frame(pipe_ctx);
-+
-+	return DC_OK;
-+}
-+
-+bool dce112_validate_bandwidth(
-+	struct dc *dc,
-+	struct dc_state *context)
-+{
-+	bool result = false;
-+
-+	dm_logger_write(
-+		dc->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"%s: start",
-+		__func__);
-+
-+	if (bw_calcs(
-+			dc->ctx,
-+			dc->bw_dceip,
-+			dc->bw_vbios,
-+			context->res_ctx.pipe_ctx,
-+			dc->res_pool->pipe_count,
-+			&context->bw.dce))
-+		result = true;
-+
-+	if (!result)
-+		dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
-+			"%s: Bandwidth validation failed!",
-+			__func__);
-+
-+	if (memcmp(&dc->current_state->bw.dce,
-+			&context->bw.dce, sizeof(context->bw.dce))) {
-+		struct log_entry log_entry;
-+		dm_logger_open(
-+			dc->ctx->logger,
-+			&log_entry,
-+			LOG_BANDWIDTH_CALCS);
-+		dm_logger_append(&log_entry, "%s: finish,\n"
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d\n",
-+			__func__,
-+			context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
-+			context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
-+			context->bw.dce.urgent_wm_ns[0].b_mark,
-+			context->bw.dce.urgent_wm_ns[0].a_mark,
-+			context->bw.dce.stutter_exit_wm_ns[0].b_mark,
-+			context->bw.dce.stutter_exit_wm_ns[0].a_mark);
-+		dm_logger_append(&log_entry,
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d\n",
-+			context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
-+			context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
-+			context->bw.dce.urgent_wm_ns[1].b_mark,
-+			context->bw.dce.urgent_wm_ns[1].a_mark,
-+			context->bw.dce.stutter_exit_wm_ns[1].b_mark,
-+			context->bw.dce.stutter_exit_wm_ns[1].a_mark);
-+		dm_logger_append(&log_entry,
-+			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
-+			"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
-+			context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
-+			context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
-+			context->bw.dce.urgent_wm_ns[2].b_mark,
-+			context->bw.dce.urgent_wm_ns[2].a_mark,
-+			context->bw.dce.stutter_exit_wm_ns[2].b_mark,
-+			context->bw.dce.stutter_exit_wm_ns[2].a_mark,
-+			context->bw.dce.stutter_mode_enable);
-+		dm_logger_append(&log_entry,
-+			"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
-+			"sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n",
-+			context->bw.dce.cpuc_state_change_enable,
-+			context->bw.dce.cpup_state_change_enable,
-+			context->bw.dce.nbp_state_change_enable,
-+			context->bw.dce.all_displays_in_sync,
-+			context->bw.dce.dispclk_khz,
-+			context->bw.dce.sclk_khz,
-+			context->bw.dce.sclk_deep_sleep_khz,
-+			context->bw.dce.yclk_khz,
-+			context->bw.dce.blackout_recovery_time_us);
-+		dm_logger_close(&log_entry);
-+	}
-+	return result;
-+}
-+
-+enum dc_status resource_map_phy_clock_resources(
-+		const struct dc *dc,
-+		struct dc_state *context,
-+		struct dc_stream_state *stream)
-+{
-+
-+	/* acquire new resources */
-+	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
-+			&context->res_ctx, stream);
-+
-+	if (!pipe_ctx)
-+		return DC_ERROR_UNEXPECTED;
-+
-+	if (dc_is_dp_signal(pipe_ctx->stream->signal)
-+		|| pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
-+		pipe_ctx->clock_source =
-+				dc->res_pool->dp_clock_source;
-+	else
-+		pipe_ctx->clock_source = find_matching_pll(
-+			&context->res_ctx, dc->res_pool,
-+			stream);
-+
-+	if (pipe_ctx->clock_source == NULL)
-+		return DC_NO_CLOCK_SOURCE_RESOURCE;
-+
-+	resource_reference_clock_source(
-+		&context->res_ctx,
-+		dc->res_pool,
-+		pipe_ctx->clock_source);
-+
-+	return DC_OK;
-+}
-+
-+static bool dce112_validate_surface_sets(
-+		struct dc_state *context)
-+{
-+	int i;
-+
-+	for (i = 0; i < context->stream_count; i++) {
-+		if (context->stream_status[i].plane_count == 0)
-+			continue;
-+
-+		if (context->stream_status[i].plane_count > 1)
-+			return false;
-+
-+		if (context->stream_status[i].plane_states[0]->format
-+				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
-+			return false;
-+	}
-+
-+	return true;
-+}
-+
-+enum dc_status dce112_add_stream_to_ctx(
-+		struct dc *dc,
-+		struct dc_state *new_ctx,
-+		struct dc_stream_state *dc_stream)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+
-+	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
-+
-+	if (result == DC_OK)
-+		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
-+
-+
-+	if (result == DC_OK)
-+		result = build_mapped_resource(dc, new_ctx, dc_stream);
-+
-+	return result;
-+}
-+
-+enum dc_status dce112_validate_guaranteed(
-+		struct dc *dc,
-+		struct dc_stream_state *stream,
-+		struct dc_state *context)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+
-+	context->streams[0] = stream;
-+	dc_stream_retain(context->streams[0]);
-+	context->stream_count++;
-+
-+	result = resource_map_pool_resources(dc, context, stream);
-+
-+	if (result == DC_OK)
-+		result = resource_map_phy_clock_resources(dc, context, stream);
-+
-+	if (result == DC_OK)
-+		result = build_mapped_resource(dc, context, stream);
-+
-+	if (result == DC_OK) {
-+		validate_guaranteed_copy_streams(
-+				context, dc->caps.max_streams);
-+		result = resource_build_scaling_params_for_context(dc, context);
-+	}
-+
-+	if (result == DC_OK)
-+		if (!dce112_validate_bandwidth(dc, context))
-+			result = DC_FAIL_BANDWIDTH_VALIDATE;
-+
-+	return result;
-+}
-+
-+enum dc_status dce112_validate_global(
-+		struct dc *dc,
-+		struct dc_state *context)
-+{
-+	if (!dce112_validate_surface_sets(context))
-+		return DC_FAIL_SURFACE_VALIDATE;
-+
-+	return DC_OK;
-+}
-+
-+static void dce112_destroy_resource_pool(struct resource_pool **pool)
-+{
-+	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
-+
-+	destruct(dce110_pool);
-+	kfree(dce110_pool);
-+	*pool = NULL;
-+}
-+
-+static const struct resource_funcs dce112_res_pool_funcs = {
-+	.destroy = dce112_destroy_resource_pool,
-+	.link_enc_create = dce112_link_encoder_create,
-+	.validate_guaranteed = dce112_validate_guaranteed,
-+	.validate_bandwidth = dce112_validate_bandwidth,
-+	.validate_plane = dce100_validate_plane,
-+	.add_stream_to_ctx = dce112_add_stream_to_ctx,
-+	.validate_global = dce112_validate_global
-+};
-+
-+static void bw_calcs_data_update_from_pplib(struct dc *dc)
-+{
-+	struct dm_pp_clock_levels_with_latency eng_clks = {0};
-+	struct dm_pp_clock_levels_with_latency mem_clks = {0};
-+	struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
-+	struct dm_pp_clock_levels clks = {0};
-+
-+	/*do system clock  TODO PPLIB: after PPLIB implement,
-+	 * then remove old way
-+	 */
-+	if (!dm_pp_get_clock_levels_by_type_with_latency(
-+			dc->ctx,
-+			DM_PP_CLOCK_TYPE_ENGINE_CLK,
-+			&eng_clks)) {
-+
-+		/* This is only for temporary */
-+		dm_pp_get_clock_levels_by_type(
-+				dc->ctx,
-+				DM_PP_CLOCK_TYPE_ENGINE_CLK,
-+				&clks);
-+		/* convert all the clock fro kHz to fix point mHz */
-+		dc->bw_vbios->high_sclk = bw_frc_to_fixed(
-+				clks.clocks_in_khz[clks.num_levels-1], 1000);
-+		dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
-+				clks.clocks_in_khz[clks.num_levels/8], 1000);
-+		dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
-+				clks.clocks_in_khz[clks.num_levels*2/8], 1000);
-+		dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
-+				clks.clocks_in_khz[clks.num_levels*3/8], 1000);
-+		dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
-+				clks.clocks_in_khz[clks.num_levels*4/8], 1000);
-+		dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
-+				clks.clocks_in_khz[clks.num_levels*5/8], 1000);
-+		dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
-+				clks.clocks_in_khz[clks.num_levels*6/8], 1000);
-+		dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
-+				clks.clocks_in_khz[0], 1000);
-+
-+		/*do memory clock*/
-+		dm_pp_get_clock_levels_by_type(
-+				dc->ctx,
-+				DM_PP_CLOCK_TYPE_MEMORY_CLK,
-+				&clks);
-+
-+		dc->bw_vbios->low_yclk = bw_frc_to_fixed(
-+			clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
-+		dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
-+			1000);
-+		dc->bw_vbios->high_yclk = bw_frc_to_fixed(
-+			clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
-+			1000);
-+
-+		return;
-+	}
-+
-+	/* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
-+	dc->bw_vbios->high_sclk = bw_frc_to_fixed(
-+		eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
-+	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
-+		eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
-+	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
-+		eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
-+	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
-+		eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
-+	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
-+		eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
-+	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
-+		eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
-+	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
-+		eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
-+	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
-+			eng_clks.data[0].clocks_in_khz, 1000);
-+
-+	/*do memory clock*/
-+	dm_pp_get_clock_levels_by_type_with_latency(
-+			dc->ctx,
-+			DM_PP_CLOCK_TYPE_MEMORY_CLK,
-+			&mem_clks);
-+
-+	/* we don't need to call PPLIB for validation clock since they
-+	 * also give us the highest sclk and highest mclk (UMA clock).
-+	 * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
-+	 * YCLK = UMACLK*m_memoryTypeMultiplier
-+	 */
-+	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
-+		mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
-+	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
-+		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
-+		1000);
-+	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
-+		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
-+		1000);
-+
-+	/* Now notify PPLib/SMU about which Watermarks sets they should select
-+	 * depending on DPM state they are in. And update BW MGR GFX Engine and
-+	 * Memory clock member variables for Watermarks calculations for each
-+	 * Watermark Set
-+	 */
-+	clk_ranges.num_wm_sets = 4;
-+	clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
-+	clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
-+			eng_clks.data[0].clocks_in_khz;
-+	clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
-+			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
-+	clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz =
-+			mem_clks.data[0].clocks_in_khz;
-+	clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
-+			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
-+
-+	clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
-+	clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
-+			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
-+	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
-+	clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
-+	clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz =
-+			mem_clks.data[0].clocks_in_khz;
-+	clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
-+			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
-+
-+	clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
-+	clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
-+			eng_clks.data[0].clocks_in_khz;
-+	clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
-+			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
-+	clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz =
-+			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
-+	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
-+	clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
-+
-+	clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
-+	clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
-+			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
-+	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
-+	clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
-+	clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz =
-+			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
-+	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
-+	clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
-+
-+	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
-+	dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
-+}
-+
-+const struct resource_caps *dce112_resource_cap(
-+	struct hw_asic_id *asic_id)
-+{
-+	if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
-+	    ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
-+		return &polaris_11_resource_cap;
-+	else
-+		return &polaris_10_resource_cap;
-+}
-+
-+static bool construct(
-+	uint8_t num_virtual_links,
-+	struct dc *dc,
-+	struct dce110_resource_pool *pool)
-+{
-+	unsigned int i;
-+	struct dc_context *ctx = dc->ctx;
-+	struct dm_pp_static_clock_info static_clk_info = {0};
-+
-+	ctx->dc_bios->regs = &bios_regs;
-+
-+	pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
-+	pool->base.funcs = &dce112_res_pool_funcs;
-+
-+	/*************************************************
-+	 *  Resource + asic cap harcoding                *
-+	 *************************************************/
-+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
-+	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
-+	dc->caps.max_downscale_ratio = 200;
-+	dc->caps.i2c_speed_in_khz = 100;
-+	dc->caps.max_cursor_size = 128;
-+
-+	/*************************************************
-+	 *  Create resources                             *
-+	 *************************************************/
-+
-+	pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
-+			dce112_clock_source_create(
-+				ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL0,
-+				&clk_src_regs[0], false);
-+	pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
-+			dce112_clock_source_create(
-+				ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL1,
-+				&clk_src_regs[1], false);
-+	pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
-+			dce112_clock_source_create(
-+				ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL2,
-+				&clk_src_regs[2], false);
-+	pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
-+			dce112_clock_source_create(
-+				ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL3,
-+				&clk_src_regs[3], false);
-+	pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
-+			dce112_clock_source_create(
-+				ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL4,
-+				&clk_src_regs[4], false);
-+	pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
-+			dce112_clock_source_create(
-+				ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL5,
-+				&clk_src_regs[5], false);
-+	pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
-+
-+	pool->base.dp_clock_source =  dce112_clock_source_create(
-+		ctx, ctx->dc_bios,
-+		CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);
-+
-+
-+	for (i = 0; i < pool->base.clk_src_count; i++) {
-+		if (pool->base.clock_sources[i] == NULL) {
-+			dm_error("DC: failed to create clock sources!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto res_create_fail;
-+		}
-+	}
-+
-+	pool->base.display_clock = dce112_disp_clk_create(ctx,
-+			&disp_clk_regs,
-+			&disp_clk_shift,
-+			&disp_clk_mask);
-+	if (pool->base.display_clock == NULL) {
-+		dm_error("DC: failed to create display clock!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+	pool->base.dmcu = dce_dmcu_create(ctx,
-+			&dmcu_regs,
-+			&dmcu_shift,
-+			&dmcu_mask);
-+	if (pool->base.dmcu == NULL) {
-+		dm_error("DC: failed to create dmcu!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+	pool->base.abm = dce_abm_create(ctx,
-+			&abm_regs,
-+			&abm_shift,
-+			&abm_mask);
-+	if (pool->base.abm == NULL) {
-+		dm_error("DC: failed to create abm!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+	/* get static clock information for PPLIB or firmware, save
-+	 * max_clock_state
-+	 */
-+	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
-+		pool->base.display_clock->max_clks_state =
-+				static_clk_info.max_clocks_state;
-+
-+	{
-+		struct irq_service_init_data init_data;
-+		init_data.ctx = dc->ctx;
-+		pool->base.irqs = dal_irq_service_dce110_create(&init_data);
-+		if (!pool->base.irqs)
-+			goto res_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->base.pipe_count; i++) {
-+		pool->base.timing_generators[i] =
-+				dce112_timing_generator_create(
-+					ctx,
-+					i,
-+					&dce112_tg_offsets[i]);
-+		if (pool->base.timing_generators[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create tg!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.mis[i] = dce112_mem_input_create(ctx, i);
-+		if (pool->base.mis[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create memory input!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.ipps[i] = dce112_ipp_create(ctx, i);
-+		if (pool->base.ipps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC:failed to create input pixel processor!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.transforms[i] = dce112_transform_create(ctx, i);
-+		if (pool->base.transforms[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create transform!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.opps[i] = dce112_opp_create(
-+			ctx,
-+			i);
-+		if (pool->base.opps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC:failed to create output pixel processor!\n");
-+			goto res_create_fail;
-+		}
-+	}
-+
-+	if (!resource_construct(num_virtual_links, dc, &pool->base,
-+			  &res_create_funcs))
-+		goto res_create_fail;
-+
-+	dc->caps.max_planes =  pool->base.pipe_count;
-+
-+	/* Create hardware sequencer */
-+	dce112_hw_sequencer_construct(dc);
-+
-+	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
-+
-+	bw_calcs_data_update_from_pplib(dc);
-+
-+	return true;
-+
-+res_create_fail:
-+	destruct(pool);
-+	return false;
-+}
-+
-+struct resource_pool *dce112_create_resource_pool(
-+	uint8_t num_virtual_links,
-+	struct dc *dc)
-+{
-+	struct dce110_resource_pool *pool =
-+		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
-+
-+	if (!pool)
-+		return NULL;
-+
-+	if (construct(num_virtual_links, dc, pool))
-+		return &pool->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h.0130~	2017-12-14 06:39:58.413903566 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h	2017-12-14 06:39:58.413903566 +0100
-@@ -0,0 +1,61 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_RESOURCE_DCE112_H__
-+#define __DC_RESOURCE_DCE112_H__
-+
-+#include "core_types.h"
-+
-+struct dc;
-+struct resource_pool;
-+
-+struct resource_pool *dce112_create_resource_pool(
-+	uint8_t num_virtual_links,
-+	struct dc *dc);
-+
-+enum dc_status dce112_validate_with_context(
-+		struct dc *dc,
-+		const struct dc_validation_set set[],
-+		int set_count,
-+		struct dc_state *context,
-+		struct dc_state *old_context);
-+
-+enum dc_status dce112_validate_guaranteed(
-+		struct dc *dc,
-+		struct dc_stream_state *dc_stream,
-+		struct dc_state *context);
-+
-+bool dce112_validate_bandwidth(
-+	struct dc *dc,
-+	struct dc_state *context);
-+
-+enum dc_status dce112_add_stream_to_ctx(
-+		struct dc *dc,
-+		struct dc_state *new_ctx,
-+		struct dc_stream_state *dc_stream);
-+
-+
-+#endif /* __DC_RESOURCE_DCE112_H__ */
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce112/Makefile.0130~	2017-12-14 06:39:58.413903566 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce112/Makefile	2017-12-14 06:39:58.413903566 +0100
-@@ -0,0 +1,10 @@
-+#
-+# Makefile for the 'controller' sub-component of DAL.
-+# It provides the control and status of HW CRTC block.
-+
-+DCE112 = dce112_compressor.o dce112_hw_sequencer.o \
-+dce112_resource.o
-+
-+AMD_DAL_DCE112 = $(addprefix $(AMDDALPATH)/dc/dce112/,$(DCE112))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_DCE112)
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c.0130~	2017-12-14 06:39:58.413903566 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c	2017-12-14 06:39:58.413903566 +0100
-@@ -0,0 +1,257 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dc.h"
-+#include "core_types.h"
-+#include "dce120_hw_sequencer.h"
-+#include "dce/dce_hwseq.h"
-+
-+#include "dce110/dce110_hw_sequencer.h"
-+
-+#include "vega10/DC/dce_12_0_offset.h"
-+#include "vega10/DC/dce_12_0_sh_mask.h"
-+#include "vega10/soc15ip.h"
-+#include "reg_helper.h"
-+
-+#define CTX \
-+	hws->ctx
-+#define REG(reg)\
-+	hws->regs->reg
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	hws->shifts->field_name, hws->masks->field_name
-+
-+struct dce120_hw_seq_reg_offsets {
-+	uint32_t crtc;
-+};
-+
-+static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {
-+{
-+	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
-+}
-+};
-+
-+#define HW_REG_CRTC(reg, id)\
-+	(reg + reg_offsets[id].crtc)
-+
-+#define CNTL_ID(controller_id)\
-+	controller_id
-+/*******************************************************************************
-+ * Private definitions
-+ ******************************************************************************/
-+#if 0
-+static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
-+{
-+	uint32_t addr;
-+	uint32_t value = 0;
-+	uint32_t chunk_int = 0;
-+	uint32_t chunk_mul = 0;
-+/*
-+	addr = mmDCP0_DVMM_PTE_CONTROL + controller_id *
-+			(mmDCP1_DVMM_PTE_CONTROL- mmDCP0_DVMM_PTE_CONTROL);
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+			value, 0, DCP, controller_id,
-+			DVMM_PTE_CONTROL,
-+			DVMM_USE_SINGLE_PTE);
-+
-+	set_reg_field_value_soc15(
-+			value, 1, DCP, controller_id,
-+			DVMM_PTE_CONTROL,
-+			DVMM_PTE_BUFFER_MODE0);
-+
-+	set_reg_field_value_soc15(
-+			value, 1, DCP, controller_id,
-+			DVMM_PTE_CONTROL,
-+			DVMM_PTE_BUFFER_MODE1);
-+
-+	dm_write_reg(ctx, addr, value);*/
-+
-+	addr = mmDVMM_PTE_REQ;
-+	value = dm_read_reg(ctx, addr);
-+
-+	chunk_int = get_reg_field_value(
-+		value,
-+		DVMM_PTE_REQ,
-+		HFLIP_PTEREQ_PER_CHUNK_INT);
-+
-+	chunk_mul = get_reg_field_value(
-+		value,
-+		DVMM_PTE_REQ,
-+		HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
-+
-+	if (chunk_int != 0x4 || chunk_mul != 0x4) {
-+
-+		set_reg_field_value(
-+			value,
-+			255,
-+			DVMM_PTE_REQ,
-+			MAX_PTEREQ_TO_ISSUE);
-+
-+		set_reg_field_value(
-+			value,
-+			4,
-+			DVMM_PTE_REQ,
-+			HFLIP_PTEREQ_PER_CHUNK_INT);
-+
-+		set_reg_field_value(
-+			value,
-+			4,
-+			DVMM_PTE_REQ,
-+			HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+}
-+#endif
-+
-+static bool dce120_enable_display_power_gating(
-+	struct dc *dc,
-+	uint8_t controller_id,
-+	struct dc_bios *dcb,
-+	enum pipe_gating_control power_gating)
-+{
-+	/* disable for bringup */
-+#if 0
-+	enum bp_result bp_result = BP_RESULT_OK;
-+	enum bp_pipe_control_action cntl;
-+	struct dc_context *ctx = dc->ctx;
-+
-+	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
-+		return true;
-+
-+	if (power_gating == PIPE_GATING_CONTROL_INIT)
-+		cntl = ASIC_PIPE_INIT;
-+	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
-+		cntl = ASIC_PIPE_ENABLE;
-+	else
-+		cntl = ASIC_PIPE_DISABLE;
-+
-+	if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
-+
-+		bp_result = dcb->funcs->enable_disp_power_gating(
-+						dcb, controller_id + 1, cntl);
-+
-+		/* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
-+		 * by default when command table is called
-+		 */
-+		dm_write_reg(ctx,
-+			HW_REG_CRTC(mmCRTC0_CRTC_MASTER_UPDATE_MODE, controller_id),
-+			0);
-+	}
-+
-+	if (power_gating != PIPE_GATING_CONTROL_ENABLE)
-+		dce120_init_pte(ctx, controller_id);
-+
-+	if (bp_result == BP_RESULT_OK)
-+		return true;
-+	else
-+		return false;
-+#endif
-+	return false;
-+}
-+
-+static void dce120_update_dchub(
-+	struct dce_hwseq *hws,
-+	struct dchub_init_data *dh_data)
-+{
-+	/* TODO: port code from dal2 */
-+	switch (dh_data->fb_mode) {
-+	case FRAME_BUFFER_MODE_ZFB_ONLY:
-+		/*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
-+		REG_UPDATE_2(DCHUB_FB_LOCATION,
-+				FB_TOP, 0,
-+				FB_BASE, 0x0FFFF);
-+
-+		REG_UPDATE(DCHUB_AGP_BASE,
-+				AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
-+
-+		REG_UPDATE(DCHUB_AGP_BOT,
-+				AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
-+
-+		REG_UPDATE(DCHUB_AGP_TOP,
-+				AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
-+		break;
-+	case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
-+		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
-+		REG_UPDATE(DCHUB_AGP_BASE,
-+				AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
-+
-+		REG_UPDATE(DCHUB_AGP_BOT,
-+				AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
-+
-+		REG_UPDATE(DCHUB_AGP_TOP,
-+				AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
-+		break;
-+	case FRAME_BUFFER_MODE_LOCAL_ONLY:
-+		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
-+		REG_UPDATE(DCHUB_AGP_BASE,
-+				AGP_BASE, 0);
-+
-+		REG_UPDATE(DCHUB_AGP_BOT,
-+				AGP_BOT, 0x03FFFF);
-+
-+		REG_UPDATE(DCHUB_AGP_TOP,
-+				AGP_TOP, 0);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	dh_data->dchub_initialzied = true;
-+	dh_data->dchub_info_valid = false;
-+}
-+
-+
-+
-+void dce120_hw_sequencer_construct(struct dc *dc)
-+{
-+	/* All registers used by dce11.2 match those in dce11 in offset and
-+	 * structure
-+	 */
-+	dce110_hw_sequencer_construct(dc);
-+	dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating;
-+	dc->hwss.update_dchub = dce120_update_dchub;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h.0130~	2017-12-14 06:39:58.413903566 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h	2017-12-14 06:39:58.413903566 +0100
-@@ -0,0 +1,36 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_HWSS_DCE120_H__
-+#define __DC_HWSS_DCE120_H__
-+
-+#include "core_types.h"
-+
-+struct dc;
-+
-+void dce120_hw_sequencer_construct(struct dc *dc);
-+
-+#endif /* __DC_HWSS_DCE112_H__ */
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c.0130~	2017-12-14 06:39:58.413903566 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c	2017-12-14 06:39:58.413903566 +0100
-@@ -0,0 +1,1004 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.cls
-+*
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+
-+#include "stream_encoder.h"
-+#include "resource.h"
-+#include "include/irq_service_interface.h"
-+#include "dce120_resource.h"
-+#include "dce112/dce112_resource.h"
-+
-+#include "dce110/dce110_resource.h"
-+#include "../virtual/virtual_stream_encoder.h"
-+#include "dce120_timing_generator.h"
-+#include "irq/dce120/irq_service_dce120.h"
-+#include "dce/dce_opp.h"
-+#include "dce/dce_clock_source.h"
-+#include "dce/dce_clocks.h"
-+#include "dce/dce_ipp.h"
-+#include "dce/dce_mem_input.h"
-+
-+#include "dce110/dce110_hw_sequencer.h"
-+#include "dce120/dce120_hw_sequencer.h"
-+#include "dce/dce_transform.h"
-+
-+#include "dce/dce_audio.h"
-+#include "dce/dce_link_encoder.h"
-+#include "dce/dce_stream_encoder.h"
-+#include "dce/dce_hwseq.h"
-+#include "dce/dce_abm.h"
-+#include "dce/dce_dmcu.h"
-+
-+#include "vega10/DC/dce_12_0_offset.h"
-+#include "vega10/DC/dce_12_0_sh_mask.h"
-+#include "vega10/soc15ip.h"
-+#include "vega10/NBIO/nbio_6_1_offset.h"
-+#include "reg_helper.h"
-+
-+#include "dce100/dce100_resource.h"
-+
-+#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
-+	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f
-+	#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
-+	#define mmDP1_DP_DPHY_INTERNAL_CTRL		0x220f
-+	#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
-+	#define mmDP2_DP_DPHY_INTERNAL_CTRL		0x230f
-+	#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
-+	#define mmDP3_DP_DPHY_INTERNAL_CTRL		0x240f
-+	#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
-+	#define mmDP4_DP_DPHY_INTERNAL_CTRL		0x250f
-+	#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
-+	#define mmDP5_DP_DPHY_INTERNAL_CTRL		0x260f
-+	#define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
-+	#define mmDP6_DP_DPHY_INTERNAL_CTRL		0x270f
-+	#define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
-+#endif
-+
-+enum dce120_clk_src_array_id {
-+	DCE120_CLK_SRC_PLL0,
-+	DCE120_CLK_SRC_PLL1,
-+	DCE120_CLK_SRC_PLL2,
-+	DCE120_CLK_SRC_PLL3,
-+	DCE120_CLK_SRC_PLL4,
-+	DCE120_CLK_SRC_PLL5,
-+
-+	DCE120_CLK_SRC_TOTAL
-+};
-+
-+static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = {
-+	{
-+		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
-+	},
-+	{
-+		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
-+	}
-+};
-+
-+/* begin *********************
-+ * macros to expend register list macro defined in HW object header file */
-+
-+#define BASE_INNER(seg) \
-+	DCE_BASE__INST0_SEG ## seg
-+
-+#define NBIO_BASE_INNER(seg) \
-+	NBIF_BASE__INST0_SEG ## seg
-+
-+#define NBIO_BASE(seg) \
-+	NBIO_BASE_INNER(seg)
-+
-+/* compile time expand base address. */
-+#define BASE(seg) \
-+	BASE_INNER(seg)
-+
-+#define SR(reg_name)\
-+		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
-+					mm ## reg_name
-+
-+#define SRI(reg_name, block, id)\
-+	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-+					mm ## block ## id ## _ ## reg_name
-+
-+/* macros to expend register list macro defined in HW object header file
-+ * end *********************/
-+
-+
-+static const struct dce_dmcu_registers dmcu_regs = {
-+		DMCU_DCE110_COMMON_REG_LIST()
-+};
-+
-+static const struct dce_dmcu_shift dmcu_shift = {
-+		DMCU_MASK_SH_LIST_DCE110(__SHIFT)
-+};
-+
-+static const struct dce_dmcu_mask dmcu_mask = {
-+		DMCU_MASK_SH_LIST_DCE110(_MASK)
-+};
-+
-+static const struct dce_abm_registers abm_regs = {
-+		ABM_DCE110_COMMON_REG_LIST()
-+};
-+
-+static const struct dce_abm_shift abm_shift = {
-+		ABM_MASK_SH_LIST_DCE110(__SHIFT)
-+};
-+
-+static const struct dce_abm_mask abm_mask = {
-+		ABM_MASK_SH_LIST_DCE110(_MASK)
-+};
-+
-+#define ipp_regs(id)\
-+[id] = {\
-+		IPP_DCE110_REG_LIST_DCE_BASE(id)\
-+}
-+
-+static const struct dce_ipp_registers ipp_regs[] = {
-+		ipp_regs(0),
-+		ipp_regs(1),
-+		ipp_regs(2),
-+		ipp_regs(3),
-+		ipp_regs(4),
-+		ipp_regs(5)
-+};
-+
-+static const struct dce_ipp_shift ipp_shift = {
-+		IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT)
-+};
-+
-+static const struct dce_ipp_mask ipp_mask = {
-+		IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK)
-+};
-+
-+#define transform_regs(id)\
-+[id] = {\
-+		XFM_COMMON_REG_LIST_DCE110(id)\
-+}
-+
-+static const struct dce_transform_registers xfm_regs[] = {
-+		transform_regs(0),
-+		transform_regs(1),
-+		transform_regs(2),
-+		transform_regs(3),
-+		transform_regs(4),
-+		transform_regs(5)
-+};
-+
-+static const struct dce_transform_shift xfm_shift = {
-+		XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT)
-+};
-+
-+static const struct dce_transform_mask xfm_mask = {
-+		XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK)
-+};
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	AUX_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
-+		aux_regs(0),
-+		aux_regs(1),
-+		aux_regs(2),
-+		aux_regs(3),
-+		aux_regs(4),
-+		aux_regs(5)
-+};
-+
-+#define hpd_regs(id)\
-+[id] = {\
-+	HPD_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
-+		hpd_regs(0),
-+		hpd_regs(1),
-+		hpd_regs(2),
-+		hpd_regs(3),
-+		hpd_regs(4),
-+		hpd_regs(5)
-+};
-+
-+#define link_regs(id)\
-+[id] = {\
-+	LE_DCE120_REG_LIST(id), \
-+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
-+}
-+
-+static const struct dce110_link_enc_registers link_enc_regs[] = {
-+	link_regs(0),
-+	link_regs(1),
-+	link_regs(2),
-+	link_regs(3),
-+	link_regs(4),
-+	link_regs(5),
-+	link_regs(6),
-+};
-+
-+
-+#define stream_enc_regs(id)\
-+[id] = {\
-+	SE_COMMON_REG_LIST(id),\
-+	.TMDS_CNTL = 0,\
-+}
-+
-+static const struct dce110_stream_enc_registers stream_enc_regs[] = {
-+	stream_enc_regs(0),
-+	stream_enc_regs(1),
-+	stream_enc_regs(2),
-+	stream_enc_regs(3),
-+	stream_enc_regs(4),
-+	stream_enc_regs(5)
-+};
-+
-+static const struct dce_stream_encoder_shift se_shift = {
-+		SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT)
-+};
-+
-+static const struct dce_stream_encoder_mask se_mask = {
-+		SE_COMMON_MASK_SH_LIST_DCE120(_MASK)
-+};
-+
-+#define opp_regs(id)\
-+[id] = {\
-+	OPP_DCE_120_REG_LIST(id),\
-+}
-+
-+static const struct dce_opp_registers opp_regs[] = {
-+	opp_regs(0),
-+	opp_regs(1),
-+	opp_regs(2),
-+	opp_regs(3),
-+	opp_regs(4),
-+	opp_regs(5)
-+};
-+
-+static const struct dce_opp_shift opp_shift = {
-+	OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT)
-+};
-+
-+static const struct dce_opp_mask opp_mask = {
-+	OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK)
-+};
-+
-+#define audio_regs(id)\
-+[id] = {\
-+	AUD_COMMON_REG_LIST(id)\
-+}
-+
-+static const struct dce_audio_registers audio_regs[] = {
-+	audio_regs(0),
-+	audio_regs(1),
-+	audio_regs(2),
-+	audio_regs(3),
-+	audio_regs(4),
-+	audio_regs(5)
-+};
-+
-+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
-+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
-+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
-+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
-+
-+static const struct dce_audio_shift audio_shift = {
-+		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct dce_aduio_mask audio_mask = {
-+		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
-+};
-+
-+#define clk_src_regs(index, id)\
-+[index] = {\
-+	CS_COMMON_REG_LIST_DCE_112(id),\
-+}
-+
-+static const struct dce110_clk_src_regs clk_src_regs[] = {
-+	clk_src_regs(0, A),
-+	clk_src_regs(1, B),
-+	clk_src_regs(2, C),
-+	clk_src_regs(3, D),
-+	clk_src_regs(4, E),
-+	clk_src_regs(5, F)
-+};
-+
-+static const struct dce110_clk_src_shift cs_shift = {
-+		CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
-+};
-+
-+static const struct dce110_clk_src_mask cs_mask = {
-+		CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
-+};
-+
-+struct output_pixel_processor *dce120_opp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce110_opp *opp =
-+		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
-+
-+	if (!opp)
-+		return NULL;
-+
-+	dce110_opp_construct(opp,
-+			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
-+	return &opp->base;
-+}
-+
-+static const struct bios_registers bios_regs = {
-+	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
-+};
-+
-+static const struct resource_caps res_cap = {
-+		.num_timing_generator = 6,
-+		.num_audio = 7,
-+		.num_stream_encoder = 6,
-+		.num_pll = 6,
-+};
-+
-+static const struct dc_debug debug_defaults = {
-+		.disable_clock_gate = true,
-+};
-+
-+struct clock_source *dce120_clock_source_create(
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id id,
-+	const struct dce110_clk_src_regs *regs,
-+	bool dp_clk_src)
-+{
-+	struct dce110_clk_src *clk_src =
-+		kzalloc(sizeof(*clk_src), GFP_KERNEL);
-+
-+	if (!clk_src)
-+		return NULL;
-+
-+	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
-+				     regs, &cs_shift, &cs_mask)) {
-+		clk_src->base.dp_clk_src = dp_clk_src;
-+		return &clk_src->base;
-+	}
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
-+void dce120_clock_source_destroy(struct clock_source **clk_src)
-+{
-+	kfree(TO_DCE110_CLK_SRC(*clk_src));
-+	*clk_src = NULL;
-+}
-+
-+
-+bool dce120_hw_sequencer_create(struct dc *dc)
-+{
-+	/* All registers used by dce11.2 match those in dce11 in offset and
-+	 * structure
-+	 */
-+	dce120_hw_sequencer_construct(dc);
-+
-+	/*TODO	Move to separate file and Override what is needed */
-+
-+	return true;
-+}
-+
-+static struct timing_generator *dce120_timing_generator_create(
-+		struct dc_context *ctx,
-+		uint32_t instance,
-+		const struct dce110_timing_generator_offsets *offsets)
-+{
-+	struct dce110_timing_generator *tg110 =
-+		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
-+
-+	if (!tg110)
-+		return NULL;
-+
-+	dce120_timing_generator_construct(tg110, ctx, instance, offsets);
-+	return &tg110->base;
-+}
-+
-+static void dce120_transform_destroy(struct transform **xfm)
-+{
-+	kfree(TO_DCE_TRANSFORM(*xfm));
-+	*xfm = NULL;
-+}
-+
-+static void destruct(struct dce110_resource_pool *pool)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < pool->base.pipe_count; i++) {
-+		if (pool->base.opps[i] != NULL)
-+			dce110_opp_destroy(&pool->base.opps[i]);
-+
-+		if (pool->base.transforms[i] != NULL)
-+			dce120_transform_destroy(&pool->base.transforms[i]);
-+
-+		if (pool->base.ipps[i] != NULL)
-+			dce_ipp_destroy(&pool->base.ipps[i]);
-+
-+		if (pool->base.mis[i] != NULL) {
-+			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
-+			pool->base.mis[i] = NULL;
-+		}
-+
-+		if (pool->base.irqs != NULL) {
-+			dal_irq_service_destroy(&pool->base.irqs);
-+		}
-+
-+		if (pool->base.timing_generators[i] != NULL) {
-+			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
-+			pool->base.timing_generators[i] = NULL;
-+		}
-+	}
-+
-+	for (i = 0; i < pool->base.audio_count; i++) {
-+		if (pool->base.audios[i])
-+			dce_aud_destroy(&pool->base.audios[i]);
-+	}
-+
-+	for (i = 0; i < pool->base.stream_enc_count; i++) {
-+		if (pool->base.stream_enc[i] != NULL)
-+			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
-+	}
-+
-+	for (i = 0; i < pool->base.clk_src_count; i++) {
-+		if (pool->base.clock_sources[i] != NULL)
-+			dce120_clock_source_destroy(
-+				&pool->base.clock_sources[i]);
-+	}
-+
-+	if (pool->base.dp_clock_source != NULL)
-+		dce120_clock_source_destroy(&pool->base.dp_clock_source);
-+
-+	if (pool->base.abm != NULL)
-+		dce_abm_destroy(&pool->base.abm);
-+
-+	if (pool->base.dmcu != NULL)
-+		dce_dmcu_destroy(&pool->base.dmcu);
-+
-+	if (pool->base.display_clock != NULL)
-+		dce_disp_clk_destroy(&pool->base.display_clock);
-+}
-+
-+static void read_dce_straps(
-+	struct dc_context *ctx,
-+	struct resource_straps *straps)
-+{
-+	uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);
-+
-+	straps->audio_stream_number = get_reg_field_value(reg_val,
-+							  CC_DC_MISC_STRAPS,
-+							  AUDIO_STREAM_NUMBER);
-+	straps->hdmi_disable = get_reg_field_value(reg_val,
-+						   CC_DC_MISC_STRAPS,
-+						   HDMI_DISABLE);
-+
-+	reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);
-+	straps->dc_pinstraps_audio = get_reg_field_value(reg_val,
-+							 DC_PINSTRAPS,
-+							 DC_PINSTRAPS_AUDIO);
-+}
-+
-+static struct audio *create_audio(
-+		struct dc_context *ctx, unsigned int inst)
-+{
-+	return dce_audio_create(ctx, inst,
-+			&audio_regs[inst], &audio_shift, &audio_mask);
-+}
-+
-+static const struct encoder_feature_support link_enc_feature = {
-+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
-+		.max_hdmi_pixel_clock = 600000,
-+		.ycbcr420_supported = true,
-+		.flags.bits.IS_HBR2_CAPABLE = true,
-+		.flags.bits.IS_HBR3_CAPABLE = true,
-+		.flags.bits.IS_TPS3_CAPABLE = true,
-+		.flags.bits.IS_TPS4_CAPABLE = true,
-+		.flags.bits.IS_YCBCR_CAPABLE = true
-+};
-+
-+static struct link_encoder *dce120_link_encoder_create(
-+	const struct encoder_init_data *enc_init_data)
-+{
-+	struct dce110_link_encoder *enc110 =
-+		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	dce110_link_encoder_construct(enc110,
-+				      enc_init_data,
-+				      &link_enc_feature,
-+				      &link_enc_regs[enc_init_data->transmitter],
-+				      &link_enc_aux_regs[enc_init_data->channel - 1],
-+				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
-+
-+	return &enc110->base;
-+}
-+
-+static struct input_pixel_processor *dce120_ipp_create(
-+	struct dc_context *ctx, uint32_t inst)
-+{
-+	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
-+
-+	if (!ipp) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dce_ipp_construct(ipp, ctx, inst,
-+			&ipp_regs[inst], &ipp_shift, &ipp_mask);
-+	return &ipp->base;
-+}
-+
-+static struct stream_encoder *dce120_stream_encoder_create(
-+	enum engine_id eng_id,
-+	struct dc_context *ctx)
-+{
-+	struct dce110_stream_encoder *enc110 =
-+		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
-+					&stream_enc_regs[eng_id],
-+					&se_shift, &se_mask);
-+	return &enc110->base;
-+}
-+
-+#define SRII(reg_name, block, id)\
-+	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-+					mm ## block ## id ## _ ## reg_name
-+
-+static const struct dce_hwseq_registers hwseq_reg = {
-+		HWSEQ_DCE120_REG_LIST()
-+};
-+
-+static const struct dce_hwseq_shift hwseq_shift = {
-+		HWSEQ_DCE12_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct dce_hwseq_mask hwseq_mask = {
-+		HWSEQ_DCE12_MASK_SH_LIST(_MASK)
-+};
-+
-+static struct dce_hwseq *dce120_hwseq_create(
-+	struct dc_context *ctx)
-+{
-+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
-+
-+	if (hws) {
-+		hws->ctx = ctx;
-+		hws->regs = &hwseq_reg;
-+		hws->shifts = &hwseq_shift;
-+		hws->masks = &hwseq_mask;
-+	}
-+	return hws;
-+}
-+
-+static const struct resource_create_funcs res_create_funcs = {
-+	.read_dce_straps = read_dce_straps,
-+	.create_audio = create_audio,
-+	.create_stream_encoder = dce120_stream_encoder_create,
-+	.create_hwseq = dce120_hwseq_create,
-+};
-+
-+#define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) }
-+static const struct dce_mem_input_registers mi_regs[] = {
-+		mi_inst_regs(0),
-+		mi_inst_regs(1),
-+		mi_inst_regs(2),
-+		mi_inst_regs(3),
-+		mi_inst_regs(4),
-+		mi_inst_regs(5),
-+};
-+
-+static const struct dce_mem_input_shift mi_shifts = {
-+		MI_DCE12_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct dce_mem_input_mask mi_masks = {
-+		MI_DCE12_MASK_SH_LIST(_MASK)
-+};
-+
-+static struct mem_input *dce120_mem_input_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
-+					       GFP_KERNEL);
-+
-+	if (!dce_mi) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
-+	return &dce_mi->base;
-+}
-+
-+static struct transform *dce120_transform_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce_transform *transform =
-+		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
-+
-+	if (!transform)
-+		return NULL;
-+
-+	dce_transform_construct(transform, ctx, inst,
-+				&xfm_regs[inst], &xfm_shift, &xfm_mask);
-+	transform->lb_memory_size = 0x1404; /*5124*/
-+	return &transform->base;
-+}
-+
-+static void dce120_destroy_resource_pool(struct resource_pool **pool)
-+{
-+	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
-+
-+	destruct(dce110_pool);
-+	kfree(dce110_pool);
-+	*pool = NULL;
-+}
-+
-+static const struct resource_funcs dce120_res_pool_funcs = {
-+	.destroy = dce120_destroy_resource_pool,
-+	.link_enc_create = dce120_link_encoder_create,
-+	.validate_guaranteed = dce112_validate_guaranteed,
-+	.validate_bandwidth = dce112_validate_bandwidth,
-+	.validate_plane = dce100_validate_plane,
-+	.add_stream_to_ctx = dce112_add_stream_to_ctx
-+};
-+
-+static void bw_calcs_data_update_from_pplib(struct dc *dc)
-+{
-+	struct dm_pp_clock_levels_with_latency eng_clks = {0};
-+	struct dm_pp_clock_levels_with_latency mem_clks = {0};
-+	struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
-+	int i;
-+	unsigned int clk;
-+	unsigned int latency;
-+
-+	/*do system clock*/
-+	if (!dm_pp_get_clock_levels_by_type_with_latency(
-+				dc->ctx,
-+				DM_PP_CLOCK_TYPE_ENGINE_CLK,
-+				&eng_clks) || eng_clks.num_levels == 0) {
-+
-+		eng_clks.num_levels = 8;
-+		clk = 300000;
-+
-+		for (i = 0; i < eng_clks.num_levels; i++) {
-+			eng_clks.data[i].clocks_in_khz = clk;
-+			clk += 100000;
-+		}
-+	}
-+
-+	/* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
-+	dc->bw_vbios->high_sclk = bw_frc_to_fixed(
-+		eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
-+	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
-+		eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
-+	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
-+		eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
-+	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
-+		eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
-+	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
-+		eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
-+	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
-+		eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
-+	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
-+		eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
-+	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
-+			eng_clks.data[0].clocks_in_khz, 1000);
-+
-+	/*do memory clock*/
-+	if (!dm_pp_get_clock_levels_by_type_with_latency(
-+			dc->ctx,
-+			DM_PP_CLOCK_TYPE_MEMORY_CLK,
-+			&mem_clks) || mem_clks.num_levels == 0) {
-+
-+		mem_clks.num_levels = 3;
-+		clk = 250000;
-+		latency = 45;
-+
-+		for (i = 0; i < eng_clks.num_levels; i++) {
-+			mem_clks.data[i].clocks_in_khz = clk;
-+			mem_clks.data[i].latency_in_us = latency;
-+			clk += 500000;
-+			latency -= 5;
-+		}
-+
-+	}
-+
-+	/* we don't need to call PPLIB for validation clock since they
-+	 * also give us the highest sclk and highest mclk (UMA clock).
-+	 * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
-+	 * YCLK = UMACLK*m_memoryTypeMultiplier
-+	 */
-+	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
-+		mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
-+	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
-+		mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
-+		1000);
-+	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
-+		mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
-+		1000);
-+
-+	/* Now notify PPLib/SMU about which Watermarks sets they should select
-+	 * depending on DPM state they are in. And update BW MGR GFX Engine and
-+	 * Memory clock member variables for Watermarks calculations for each
-+	 * Watermark Set
-+	 */
-+	clk_ranges.num_wm_sets = 4;
-+	clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
-+	clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
-+			eng_clks.data[0].clocks_in_khz;
-+	clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
-+			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
-+	clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz =
-+			mem_clks.data[0].clocks_in_khz;
-+	clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
-+			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
-+
-+	clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
-+	clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
-+			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
-+	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
-+	clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
-+	clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz =
-+			mem_clks.data[0].clocks_in_khz;
-+	clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
-+			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
-+
-+	clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
-+	clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
-+			eng_clks.data[0].clocks_in_khz;
-+	clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
-+			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
-+	clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz =
-+			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
-+	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
-+	clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
-+
-+	clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
-+	clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
-+			eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
-+	/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
-+	clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
-+	clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz =
-+			mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
-+	/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
-+	clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
-+
-+	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
-+	dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
-+}
-+
-+static bool construct(
-+	uint8_t num_virtual_links,
-+	struct dc *dc,
-+	struct dce110_resource_pool *pool)
-+{
-+	unsigned int i;
-+	struct dc_context *ctx = dc->ctx;
-+	struct irq_service_init_data irq_init_data;
-+
-+	ctx->dc_bios->regs = &bios_regs;
-+
-+	pool->base.res_cap = &res_cap;
-+	pool->base.funcs = &dce120_res_pool_funcs;
-+
-+	/* TODO: Fill more data from GreenlandAsicCapability.cpp */
-+	pool->base.pipe_count = res_cap.num_timing_generator;
-+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
-+
-+	dc->caps.max_downscale_ratio = 200;
-+	dc->caps.i2c_speed_in_khz = 100;
-+	dc->caps.max_cursor_size = 128;
-+	dc->debug = debug_defaults;
-+
-+	/*************************************************
-+	 *  Create resources                             *
-+	 *************************************************/
-+
-+	pool->base.clock_sources[DCE120_CLK_SRC_PLL0] =
-+			dce120_clock_source_create(ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL0,
-+				&clk_src_regs[0], false);
-+	pool->base.clock_sources[DCE120_CLK_SRC_PLL1] =
-+			dce120_clock_source_create(ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL1,
-+				&clk_src_regs[1], false);
-+	pool->base.clock_sources[DCE120_CLK_SRC_PLL2] =
-+			dce120_clock_source_create(ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL2,
-+				&clk_src_regs[2], false);
-+	pool->base.clock_sources[DCE120_CLK_SRC_PLL3] =
-+			dce120_clock_source_create(ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL3,
-+				&clk_src_regs[3], false);
-+	pool->base.clock_sources[DCE120_CLK_SRC_PLL4] =
-+			dce120_clock_source_create(ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL4,
-+				&clk_src_regs[4], false);
-+	pool->base.clock_sources[DCE120_CLK_SRC_PLL5] =
-+			dce120_clock_source_create(ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL5,
-+				&clk_src_regs[5], false);
-+	pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL;
-+
-+	pool->base.dp_clock_source =
-+			dce120_clock_source_create(ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_ID_DP_DTO,
-+				&clk_src_regs[0], true);
-+
-+	for (i = 0; i < pool->base.clk_src_count; i++) {
-+		if (pool->base.clock_sources[i] == NULL) {
-+			dm_error("DC: failed to create clock sources!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto clk_src_create_fail;
-+		}
-+	}
-+
-+	pool->base.display_clock = dce120_disp_clk_create(ctx);
-+	if (pool->base.display_clock == NULL) {
-+		dm_error("DC: failed to create display clock!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto disp_clk_create_fail;
-+	}
-+
-+	pool->base.dmcu = dce_dmcu_create(ctx,
-+			&dmcu_regs,
-+			&dmcu_shift,
-+			&dmcu_mask);
-+	if (pool->base.dmcu == NULL) {
-+		dm_error("DC: failed to create dmcu!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+	pool->base.abm = dce_abm_create(ctx,
-+			&abm_regs,
-+			&abm_shift,
-+			&abm_mask);
-+	if (pool->base.abm == NULL) {
-+		dm_error("DC: failed to create abm!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+	irq_init_data.ctx = dc->ctx;
-+	pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data);
-+	if (!pool->base.irqs)
-+		goto irqs_create_fail;
-+
-+	for (i = 0; i < pool->base.pipe_count; i++) {
-+		pool->base.timing_generators[i] =
-+				dce120_timing_generator_create(
-+					ctx,
-+					i,
-+					&dce120_tg_offsets[i]);
-+		if (pool->base.timing_generators[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create tg!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->base.mis[i] = dce120_mem_input_create(ctx, i);
-+
-+		if (pool->base.mis[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create memory input!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->base.ipps[i] = dce120_ipp_create(ctx, i);
-+		if (pool->base.ipps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create input pixel processor!\n");
-+			goto controller_create_fail;
-+		}
-+
-+		pool->base.transforms[i] = dce120_transform_create(ctx, i);
-+		if (pool->base.transforms[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create transform!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.opps[i] = dce120_opp_create(
-+			ctx,
-+			i);
-+		if (pool->base.opps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create output pixel processor!\n");
-+		}
-+	}
-+
-+	if (!resource_construct(num_virtual_links, dc, &pool->base,
-+			 &res_create_funcs))
-+		goto res_create_fail;
-+
-+	/* Create hardware sequencer */
-+	if (!dce120_hw_sequencer_create(dc))
-+		goto controller_create_fail;
-+
-+	dc->caps.max_planes =  pool->base.pipe_count;
-+
-+	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
-+
-+	bw_calcs_data_update_from_pplib(dc);
-+
-+	return true;
-+
-+irqs_create_fail:
-+controller_create_fail:
-+disp_clk_create_fail:
-+clk_src_create_fail:
-+res_create_fail:
-+
-+	destruct(pool);
-+
-+	return false;
-+}
-+
-+struct resource_pool *dce120_create_resource_pool(
-+	uint8_t num_virtual_links,
-+	struct dc *dc)
-+{
-+	struct dce110_resource_pool *pool =
-+		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
-+
-+	if (!pool)
-+		return NULL;
-+
-+	if (construct(num_virtual_links, dc, pool))
-+		return &pool->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h.0130~	2017-12-14 06:39:58.413903566 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h	2017-12-14 06:39:58.413903566 +0100
-@@ -0,0 +1,39 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_RESOURCE_DCE120_H__
-+#define __DC_RESOURCE_DCE120_H__
-+
-+#include "core_types.h"
-+
-+struct dc;
-+struct resource_pool;
-+
-+struct resource_pool *dce120_create_resource_pool(
-+	uint8_t num_virtual_links,
-+	struct dc *dc);
-+
-+#endif /* __DC_RESOURCE_DCE120_H__ */
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c.0130~	2017-12-14 06:39:58.413903566 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c	2017-12-14 06:39:58.413903566 +0100
-@@ -0,0 +1,1174 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "vega10/DC/dce_12_0_offset.h"
-+#include "vega10/DC/dce_12_0_sh_mask.h"
-+#include "vega10/soc15ip.h"
-+
-+#include "dc_types.h"
-+#include "dc_bios_types.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/logger_interface.h"
-+#include "dce120_timing_generator.h"
-+
-+#include "timing_generator.h"
-+
-+#define CRTC_REG_UPDATE_N(reg_name, n, ...)	\
-+		generic_reg_update_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
-+
-+#define CRTC_REG_SET_N(reg_name, n, ...)	\
-+		generic_reg_set_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
-+
-+#define CRTC_REG_UPDATE(reg, field, val)	\
-+		CRTC_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)
-+
-+#define CRTC_REG_UPDATE_2(reg, field1, val1, field2, val2)	\
-+		CRTC_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
-+
-+#define CRTC_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3)	\
-+		CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
-+
-+#define CRTC_REG_UPDATE_4(reg, field1, val1, field2, val2, field3, val3, field4, val4)	\
-+		CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4)
-+
-+#define CRTC_REG_UPDATE_5(reg, field1, val1, field2, val2, field3, val3, field4, val4, field5, val5)	\
-+		CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4, FD(reg##__##field5), val5)
-+
-+#define CRTC_REG_SET(reg, field, val)	\
-+		CRTC_REG_SET_N(reg, 1, FD(reg##__##field), val)
-+
-+#define CRTC_REG_SET_2(reg, field1, val1, field2, val2)	\
-+		CRTC_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
-+
-+#define CRTC_REG_SET_3(reg, field1, val1, field2, val2, field3, val3)	\
-+		CRTC_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
-+
-+/**
-+ *****************************************************************************
-+ *  Function: is_in_vertical_blank
-+ *
-+ *  @brief
-+ *     check the current status of CRTC to check if we are in Vertical Blank
-+ *     regioneased" state
-+ *
-+ *  @return
-+ *     true if currently in blank region, false otherwise
-+ *
-+ *****************************************************************************
-+ */
-+static bool dce120_timing_generator_is_in_vertical_blank(
-+		struct timing_generator *tg)
-+{
-+	uint32_t field = 0;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t value = dm_read_reg_soc15(
-+					tg->ctx,
-+					mmCRTC0_CRTC_STATUS,
-+					tg110->offsets.crtc);
-+
-+	field = get_reg_field_value(value, CRTC0_CRTC_STATUS, CRTC_V_BLANK);
-+	return field == 1;
-+}
-+
-+
-+/* determine if given timing can be supported by TG */
-+bool dce120_timing_generator_validate_timing(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing,
-+	enum signal_type signal)
-+{
-+	uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1;
-+	uint32_t v_blank =
-+					(timing->v_total - timing->v_addressable -
-+					timing->v_border_top - timing->v_border_bottom) *
-+					interlace_factor;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	if (!dce110_timing_generator_validate_timing(
-+					tg,
-+					timing,
-+					signal))
-+		return false;
-+
-+
-+	if (v_blank < tg110->min_v_blank	||
-+		 timing->h_sync_width  < tg110->min_h_sync_width ||
-+		 timing->v_sync_width  < tg110->min_v_sync_width)
-+		return false;
-+
-+	return true;
-+}
-+
-+bool dce120_tg_validate_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing)
-+{
-+	return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE);
-+}
-+
-+/******** HW programming ************/
-+/* Disable/Enable Timing Generator */
-+bool dce120_timing_generator_enable_crtc(struct timing_generator *tg)
-+{
-+	enum bp_result result;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	/* Set MASTER_UPDATE_MODE to 0
-+	 * This is needed for DRR, and also suggested to be default value by Syed.*/
-+
-+	CRTC_REG_UPDATE(CRTC0_CRTC_MASTER_UPDATE_MODE,
-+			MASTER_UPDATE_MODE, 0);
-+
-+	CRTC_REG_UPDATE(CRTC0_CRTC_MASTER_UPDATE_LOCK,
-+			UNDERFLOW_UPDATE_LOCK, 0);
-+
-+	/* TODO API for AtomFirmware didn't change*/
-+	result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);
-+
-+	return result == BP_RESULT_OK;
-+}
-+
-+void dce120_timing_generator_set_early_control(
-+		struct timing_generator *tg,
-+		uint32_t early_cntl)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	CRTC_REG_UPDATE(CRTC0_CRTC_CONTROL,
-+			CRTC_HBLANK_EARLY_CONTROL, early_cntl);
-+}
-+
-+/**************** TG current status ******************/
-+
-+/* return the current frame counter. Used by Linux kernel DRM */
-+uint32_t dce120_timing_generator_get_vblank_counter(
-+		struct timing_generator *tg)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t value = dm_read_reg_soc15(
-+				tg->ctx,
-+				mmCRTC0_CRTC_STATUS_FRAME_COUNT,
-+				tg110->offsets.crtc);
-+	uint32_t field = get_reg_field_value(
-+				value, CRTC0_CRTC_STATUS_FRAME_COUNT, CRTC_FRAME_COUNT);
-+
-+	return field;
-+}
-+
-+/* Get current H and V position */
-+void dce120_timing_generator_get_crtc_position(
-+	struct timing_generator *tg,
-+	struct crtc_position *position)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t value = dm_read_reg_soc15(
-+				tg->ctx,
-+				mmCRTC0_CRTC_STATUS_POSITION,
-+				tg110->offsets.crtc);
-+
-+	position->horizontal_count = get_reg_field_value(value,
-+			CRTC0_CRTC_STATUS_POSITION, CRTC_HORZ_COUNT);
-+
-+	position->vertical_count = get_reg_field_value(value,
-+			CRTC0_CRTC_STATUS_POSITION, CRTC_VERT_COUNT);
-+
-+	value = dm_read_reg_soc15(
-+				tg->ctx,
-+				mmCRTC0_CRTC_NOM_VERT_POSITION,
-+				tg110->offsets.crtc);
-+
-+	position->nominal_vcount = get_reg_field_value(value,
-+			CRTC0_CRTC_NOM_VERT_POSITION, CRTC_VERT_COUNT_NOM);
-+}
-+
-+/* wait until TG is in beginning of vertical blank region */
-+void dce120_timing_generator_wait_for_vblank(struct timing_generator *tg)
-+{
-+	/* We want to catch beginning of VBlank here, so if the first try are
-+	 * in VBlank, we might be very close to Active, in this case wait for
-+	 * another frame
-+	 */
-+	while (dce120_timing_generator_is_in_vertical_blank(tg)) {
-+		if (!tg->funcs->is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+
-+	while (!dce120_timing_generator_is_in_vertical_blank(tg)) {
-+		if (!tg->funcs->is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+}
-+
-+/* wait until TG is in beginning of active region */
-+void dce120_timing_generator_wait_for_vactive(struct timing_generator *tg)
-+{
-+	while (dce120_timing_generator_is_in_vertical_blank(tg)) {
-+		if (!tg->funcs->is_counter_moving(tg)) {
-+			/* error - no point to wait if counter is not moving */
-+			break;
-+		}
-+	}
-+}
-+
-+/*********** Timing Generator Synchronization routines ****/
-+
-+/* Setups Global Swap Lock group, TimingServer or TimingClient*/
-+void dce120_timing_generator_setup_global_swap_lock(
-+	struct timing_generator *tg,
-+	const struct dcp_gsl_params *gsl_params)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t value_crtc_vtotal =
-+							dm_read_reg_soc15(tg->ctx,
-+							mmCRTC0_CRTC_V_TOTAL,
-+							tg110->offsets.crtc);
-+	/* Checkpoint relative to end of frame */
-+	uint32_t check_point =
-+							get_reg_field_value(value_crtc_vtotal,
-+							CRTC0_CRTC_V_TOTAL,
-+							CRTC_V_TOTAL);
-+
-+
-+	dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_GSL_WINDOW, tg110->offsets.crtc, 0);
-+
-+	CRTC_REG_UPDATE_N(DCP0_DCP_GSL_CONTROL, 6,
-+		/* This pipe will belong to GSL Group zero. */
-+		FD(DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN), 1,
-+		FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN), gsl_params->gsl_master == tg->inst,
-+		FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY), HFLIP_READY_DELAY,
-+		/* Keep signal low (pending high) during 6 lines.
-+		 * Also defines minimum interval before re-checking signal. */
-+		FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY), HFLIP_CHECK_DELAY,
-+		/* DCP_GSL_PURPOSE_SURFACE_FLIP */
-+		FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE), 0,
-+		FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING), 1);
-+
-+	CRTC_REG_SET_2(
-+			CRTC0_CRTC_GSL_CONTROL,
-+			CRTC_GSL_CHECK_LINE_NUM, check_point - FLIP_READY_BACK_LOOKUP,
-+			CRTC_GSL_FORCE_DELAY, VFLIP_READY_DELAY);
-+}
-+
-+/* Clear all the register writes done by setup_global_swap_lock */
-+void dce120_timing_generator_tear_down_global_swap_lock(
-+	struct timing_generator *tg)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	/* Settig HW default values from reg specs */
-+	CRTC_REG_SET_N(DCP0_DCP_GSL_CONTROL, 6,
-+			FD(DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN), 0,
-+			FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN), 0,
-+			FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY), HFLIP_READY_DELAY,
-+			FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY), HFLIP_CHECK_DELAY,
-+			/* DCP_GSL_PURPOSE_SURFACE_FLIP */
-+			FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE), 0,
-+			FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING), 0);
-+
-+	CRTC_REG_SET_2(CRTC0_CRTC_GSL_CONTROL,
-+		       CRTC_GSL_CHECK_LINE_NUM, 0,
-+		       CRTC_GSL_FORCE_DELAY, 0x2); /*TODO Why this value here ?*/
-+}
-+
-+/* Reset slave controllers on master VSync */
-+void dce120_timing_generator_enable_reset_trigger(
-+	struct timing_generator *tg,
-+	int source)
-+{
-+	enum trigger_source_select trig_src_select = TRIGGER_SOURCE_SELECT_LOGIC_ZERO;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t rising_edge = 0;
-+	uint32_t falling_edge = 0;
-+	/* Setup trigger edge */
-+	uint32_t pol_value = dm_read_reg_soc15(
-+									tg->ctx,
-+									mmCRTC0_CRTC_V_SYNC_A_CNTL,
-+									tg110->offsets.crtc);
-+
-+	/* Register spec has reversed definition:
-+	 *	0 for positive, 1 for negative */
-+	if (get_reg_field_value(pol_value,
-+			CRTC0_CRTC_V_SYNC_A_CNTL,
-+			CRTC_V_SYNC_A_POL) == 0) {
-+		rising_edge = 1;
-+	} else {
-+		falling_edge = 1;
-+	}
-+
-+	/* TODO What about other sources ?*/
-+	trig_src_select = TRIGGER_SOURCE_SELECT_GSL_GROUP0;
-+
-+	CRTC_REG_UPDATE_N(CRTC0_CRTC_TRIGB_CNTL, 7,
-+		FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT), trig_src_select,
-+		FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT), TRIGGER_POLARITY_SELECT_LOGIC_ZERO,
-+		FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL), rising_edge,
-+		FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL), falling_edge,
-+		/* send every signal */
-+		FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT), 0,
-+		/* no delay */
-+		FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY), 0,
-+		/* clear trigger status */
-+		FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR), 1);
-+
-+	CRTC_REG_UPDATE_3(
-+			CRTC0_CRTC_FORCE_COUNT_NOW_CNTL,
-+			CRTC_FORCE_COUNT_NOW_MODE, 2,
-+			CRTC_FORCE_COUNT_NOW_TRIG_SEL, 1,
-+			CRTC_FORCE_COUNT_NOW_CLEAR, 1);
-+}
-+
-+/* disabling trigger-reset */
-+void dce120_timing_generator_disable_reset_trigger(
-+	struct timing_generator *tg)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	CRTC_REG_UPDATE_2(
-+		CRTC0_CRTC_FORCE_COUNT_NOW_CNTL,
-+		CRTC_FORCE_COUNT_NOW_MODE, 0,
-+		CRTC_FORCE_COUNT_NOW_CLEAR, 1);
-+
-+	CRTC_REG_UPDATE_3(
-+		CRTC0_CRTC_TRIGB_CNTL,
-+		CRTC_TRIGB_SOURCE_SELECT, TRIGGER_SOURCE_SELECT_LOGIC_ZERO,
-+		CRTC_TRIGB_POLARITY_SELECT, TRIGGER_POLARITY_SELECT_LOGIC_ZERO,
-+		/* clear trigger status */
-+		CRTC_TRIGB_CLEAR, 1);
-+
-+}
-+
-+/* Checks whether CRTC triggered reset occurred */
-+bool dce120_timing_generator_did_triggered_reset_occur(
-+	struct timing_generator *tg)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t value = dm_read_reg_soc15(
-+			tg->ctx,
-+			mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL,
-+			tg110->offsets.crtc);
-+
-+	return get_reg_field_value(value,
-+			CRTC0_CRTC_FORCE_COUNT_NOW_CNTL,
-+			CRTC_FORCE_COUNT_NOW_OCCURRED) != 0;
-+}
-+
-+
-+/******** Stuff to move to other virtual HW objects *****************/
-+/* Move to enable accelerated mode */
-+void dce120_timing_generator_disable_vga(struct timing_generator *tg)
-+{
-+	uint32_t offset = 0;
-+	uint32_t value = 0;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	switch (tg110->controller_id) {
-+	case CONTROLLER_ID_D0:
-+		offset = 0;
-+		break;
-+	case CONTROLLER_ID_D1:
-+		offset = mmD2VGA_CONTROL - mmD1VGA_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D2:
-+		offset = mmD3VGA_CONTROL - mmD1VGA_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D3:
-+		offset = mmD4VGA_CONTROL - mmD1VGA_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D4:
-+		offset = mmD5VGA_CONTROL - mmD1VGA_CONTROL;
-+		break;
-+	case CONTROLLER_ID_D5:
-+		offset = mmD6VGA_CONTROL - mmD1VGA_CONTROL;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	value = dm_read_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset);
-+
-+	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE);
-+	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT);
-+	set_reg_field_value(
-+			value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT);
-+	set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN);
-+
-+	dm_write_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset, value);
-+}
-+/* TODO: Should we move it to transform */
-+/* Fully program CRTC timing in timing generator */
-+void dce120_timing_generator_program_blanking(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t tmp1 = 0;
-+	uint32_t tmp2 = 0;
-+	uint32_t vsync_offset = timing->v_border_bottom +
-+			timing->v_front_porch;
-+	uint32_t v_sync_start = timing->v_addressable + vsync_offset;
-+
-+	uint32_t hsync_offset = timing->h_border_right +
-+			timing->h_front_porch;
-+	uint32_t h_sync_start = timing->h_addressable + hsync_offset;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	CRTC_REG_UPDATE(
-+		CRTC0_CRTC_H_TOTAL,
-+		CRTC_H_TOTAL,
-+		timing->h_total - 1);
-+
-+	CRTC_REG_UPDATE(
-+		CRTC0_CRTC_V_TOTAL,
-+		CRTC_V_TOTAL,
-+		timing->v_total - 1);
-+
-+	/* In case of V_TOTAL_CONTROL is on, make sure V_TOTAL_MAX and
-+	 * V_TOTAL_MIN are equal to V_TOTAL.
-+	 */
-+	CRTC_REG_UPDATE(
-+		CRTC0_CRTC_V_TOTAL_MAX,
-+		CRTC_V_TOTAL_MAX,
-+		timing->v_total - 1);
-+
-+	CRTC_REG_UPDATE(
-+		CRTC0_CRTC_V_TOTAL_MIN,
-+		CRTC_V_TOTAL_MIN,
-+		timing->v_total - 1);
-+
-+	tmp1 = timing->h_total -
-+			(h_sync_start + timing->h_border_left);
-+	tmp2 = tmp1 + timing->h_addressable +
-+			timing->h_border_left + timing->h_border_right;
-+
-+	CRTC_REG_UPDATE_2(
-+			CRTC0_CRTC_H_BLANK_START_END,
-+			CRTC_H_BLANK_END, tmp1,
-+			CRTC_H_BLANK_START, tmp2);
-+
-+	tmp1 = timing->v_total - (v_sync_start + timing->v_border_top);
-+	tmp2 = tmp1 + timing->v_addressable + timing->v_border_top +
-+			timing->v_border_bottom;
-+
-+	CRTC_REG_UPDATE_2(
-+		CRTC0_CRTC_V_BLANK_START_END,
-+		CRTC_V_BLANK_END, tmp1,
-+		CRTC_V_BLANK_START, tmp2);
-+}
-+
-+/* TODO: Should we move it to opp? */
-+/* Combine with below and move YUV/RGB color conversion to SW layer */
-+void dce120_timing_generator_program_blank_color(
-+	struct timing_generator *tg,
-+	const struct tg_color *black_color)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	CRTC_REG_UPDATE_3(
-+		CRTC0_CRTC_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_B_CB, black_color->color_b_cb,
-+		CRTC_BLACK_COLOR_G_Y, black_color->color_g_y,
-+		CRTC_BLACK_COLOR_R_CR, black_color->color_r_cr);
-+}
-+/* Combine with above and move YUV/RGB color conversion to SW layer */
-+void dce120_timing_generator_set_overscan_color_black(
-+	struct timing_generator *tg,
-+	const struct tg_color *color)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t value = 0;
-+	CRTC_REG_SET_3(
-+		CRTC0_CRTC_OVERSCAN_COLOR,
-+		CRTC_OVERSCAN_COLOR_BLUE, color->color_b_cb,
-+		CRTC_OVERSCAN_COLOR_GREEN, color->color_g_y,
-+		CRTC_OVERSCAN_COLOR_RED, color->color_r_cr);
-+
-+	value = dm_read_reg_soc15(
-+			tg->ctx,
-+			mmCRTC0_CRTC_OVERSCAN_COLOR,
-+			tg110->offsets.crtc);
-+
-+	dm_write_reg_soc15(
-+			tg->ctx,
-+			mmCRTC0_CRTC_BLACK_COLOR,
-+			tg110->offsets.crtc,
-+			value);
-+
-+	/* This is desirable to have a constant DAC output voltage during the
-+	 * blank time that is higher than the 0 volt reference level that the
-+	 * DAC outputs when the NBLANK signal
-+	 * is asserted low, such as for output to an analog TV. */
-+	dm_write_reg_soc15(
-+		tg->ctx,
-+		mmCRTC0_CRTC_BLANK_DATA_COLOR,
-+		tg110->offsets.crtc,
-+		value);
-+
-+	/* TO DO we have to program EXT registers and we need to know LB DATA
-+	 * format because it is used when more 10 , i.e. 12 bits per color
-+	 *
-+	 * m_mmDxCRTC_OVERSCAN_COLOR_EXT
-+	 * m_mmDxCRTC_BLACK_COLOR_EXT
-+	 * m_mmDxCRTC_BLANK_DATA_COLOR_EXT
-+	 */
-+}
-+
-+void dce120_timing_generator_set_drr(
-+	struct timing_generator *tg,
-+	const struct drr_params *params)
-+{
-+
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	if (params != NULL &&
-+		params->vertical_total_max > 0 &&
-+		params->vertical_total_min > 0) {
-+
-+		CRTC_REG_UPDATE(
-+				CRTC0_CRTC_V_TOTAL_MIN,
-+				CRTC_V_TOTAL_MIN, params->vertical_total_min - 1);
-+		CRTC_REG_UPDATE(
-+				CRTC0_CRTC_V_TOTAL_MAX,
-+				CRTC_V_TOTAL_MAX, params->vertical_total_max - 1);
-+		CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 6,
-+				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 1,
-+				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 1,
-+				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0,
-+				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0,
-+				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN), 0,
-+				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0);
-+		CRTC_REG_UPDATE(
-+				CRTC0_CRTC_STATIC_SCREEN_CONTROL,
-+				CRTC_STATIC_SCREEN_EVENT_MASK,
-+				0x180);
-+
-+	} else {
-+		CRTC_REG_UPDATE(
-+				CRTC0_CRTC_V_TOTAL_MIN,
-+				CRTC_V_TOTAL_MIN, 0);
-+		CRTC_REG_UPDATE(
-+				CRTC0_CRTC_V_TOTAL_MAX,
-+				CRTC_V_TOTAL_MAX, 0);
-+		CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 5,
-+				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 0,
-+				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 0,
-+				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0,
-+				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0,
-+				FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0);
-+		CRTC_REG_UPDATE(
-+				CRTC0_CRTC_STATIC_SCREEN_CONTROL,
-+				CRTC_STATIC_SCREEN_EVENT_MASK,
-+				0);
-+	}
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dce120_timing_generator_get_position
-+ *
-+ *  @brief
-+ *     Returns CRTC vertical/horizontal counters
-+ *
-+ *  @param [out] position
-+ *****************************************************************************
-+ */
-+void dce120_timing_generator_get_position(struct timing_generator *tg,
-+	struct crtc_position *position)
-+{
-+	uint32_t value;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	value = dm_read_reg_soc15(
-+			tg->ctx,
-+			mmCRTC0_CRTC_STATUS_POSITION,
-+			tg110->offsets.crtc);
-+
-+	position->horizontal_count = get_reg_field_value(
-+			value,
-+			CRTC0_CRTC_STATUS_POSITION,
-+			CRTC_HORZ_COUNT);
-+
-+	position->vertical_count = get_reg_field_value(
-+			value,
-+			CRTC0_CRTC_STATUS_POSITION,
-+			CRTC_VERT_COUNT);
-+
-+	value = dm_read_reg_soc15(
-+			tg->ctx,
-+			mmCRTC0_CRTC_NOM_VERT_POSITION,
-+			tg110->offsets.crtc);
-+
-+	position->nominal_vcount = get_reg_field_value(
-+			value,
-+			CRTC0_CRTC_NOM_VERT_POSITION,
-+			CRTC_VERT_COUNT_NOM);
-+}
-+
-+
-+void dce120_timing_generator_get_crtc_scanoutpos(
-+	struct timing_generator *tg,
-+	uint32_t *v_blank_start,
-+	uint32_t *v_blank_end,
-+	uint32_t *h_position,
-+	uint32_t *v_position)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	struct crtc_position position;
-+
-+	uint32_t v_blank_start_end = dm_read_reg_soc15(
-+			tg->ctx,
-+			mmCRTC0_CRTC_V_BLANK_START_END,
-+			tg110->offsets.crtc);
-+
-+	*v_blank_start = get_reg_field_value(v_blank_start_end,
-+					     CRTC0_CRTC_V_BLANK_START_END,
-+					     CRTC_V_BLANK_START);
-+	*v_blank_end = get_reg_field_value(v_blank_start_end,
-+					   CRTC0_CRTC_V_BLANK_START_END,
-+					   CRTC_V_BLANK_END);
-+
-+	dce120_timing_generator_get_crtc_position(
-+			tg, &position);
-+
-+	*h_position = position.horizontal_count;
-+	*v_position = position.vertical_count;
-+}
-+
-+void dce120_timing_generator_enable_advanced_request(
-+	struct timing_generator *tg,
-+	bool enable,
-+	const struct dc_crtc_timing *timing)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t v_sync_width_and_b_porch =
-+				timing->v_total - timing->v_addressable -
-+				timing->v_border_bottom - timing->v_front_porch;
-+	uint32_t value = dm_read_reg_soc15(
-+				tg->ctx,
-+				mmCRTC0_CRTC_START_LINE_CONTROL,
-+				tg110->offsets.crtc);
-+
-+	set_reg_field_value(
-+		value,
-+		enable ? 0 : 1,
-+		CRTC0_CRTC_START_LINE_CONTROL,
-+		CRTC_LEGACY_REQUESTOR_EN);
-+
-+	/* Program advanced line position acc.to the best case from fetching data perspective to hide MC latency
-+	 * and prefilling Line Buffer in V Blank (to 10 lines as LB can store max 10 lines)
-+	 */
-+	if (v_sync_width_and_b_porch > 10)
-+		v_sync_width_and_b_porch = 10;
-+
-+	set_reg_field_value(
-+		value,
-+		v_sync_width_and_b_porch,
-+		CRTC0_CRTC_START_LINE_CONTROL,
-+		CRTC_ADVANCED_START_LINE_POSITION);
-+
-+	dm_write_reg_soc15(tg->ctx,
-+			mmCRTC0_CRTC_START_LINE_CONTROL,
-+			tg110->offsets.crtc,
-+			value);
-+}
-+
-+void dce120_tg_program_blank_color(struct timing_generator *tg,
-+	const struct tg_color *black_color)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t value = 0;
-+
-+	CRTC_REG_UPDATE_3(
-+		CRTC0_CRTC_BLACK_COLOR,
-+		CRTC_BLACK_COLOR_B_CB, black_color->color_b_cb,
-+		CRTC_BLACK_COLOR_G_Y, black_color->color_g_y,
-+		CRTC_BLACK_COLOR_R_CR, black_color->color_r_cr);
-+
-+	value = dm_read_reg_soc15(
-+				tg->ctx,
-+				mmCRTC0_CRTC_BLACK_COLOR,
-+				tg110->offsets.crtc);
-+	dm_write_reg_soc15(
-+		tg->ctx,
-+		mmCRTC0_CRTC_BLANK_DATA_COLOR,
-+		tg110->offsets.crtc,
-+		value);
-+}
-+
-+void dce120_tg_set_overscan_color(struct timing_generator *tg,
-+	const struct tg_color *overscan_color)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	CRTC_REG_SET_3(
-+		CRTC0_CRTC_OVERSCAN_COLOR,
-+		CRTC_OVERSCAN_COLOR_BLUE, overscan_color->color_b_cb,
-+		CRTC_OVERSCAN_COLOR_GREEN, overscan_color->color_g_y,
-+		CRTC_OVERSCAN_COLOR_RED, overscan_color->color_r_cr);
-+}
-+
-+void dce120_tg_program_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing,
-+	bool use_vbios)
-+{
-+	if (use_vbios)
-+		dce110_timing_generator_program_timing_generator(tg, timing);
-+	else
-+		dce120_timing_generator_program_blanking(tg, timing);
-+}
-+
-+bool dce120_tg_is_blanked(struct timing_generator *tg)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t value = dm_read_reg_soc15(
-+			tg->ctx,
-+			mmCRTC0_CRTC_BLANK_CONTROL,
-+			tg110->offsets.crtc);
-+
-+	if (get_reg_field_value(
-+		value,
-+		CRTC0_CRTC_BLANK_CONTROL,
-+		CRTC_BLANK_DATA_EN) == 1 &&
-+	    get_reg_field_value(
-+		value,
-+		CRTC0_CRTC_BLANK_CONTROL,
-+		CRTC_CURRENT_BLANK_STATE) == 1)
-+			return true;
-+
-+	return false;
-+}
-+
-+void dce120_tg_set_blank(struct timing_generator *tg,
-+		bool enable_blanking)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	CRTC_REG_SET(
-+		CRTC0_CRTC_DOUBLE_BUFFER_CONTROL,
-+		CRTC_BLANK_DATA_DOUBLE_BUFFER_EN, 0);
-+
-+	if (enable_blanking)
-+		CRTC_REG_SET(CRTC0_CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
-+	else
-+		dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_BLANK_CONTROL,
-+			tg110->offsets.crtc, 0);
-+}
-+
-+bool dce120_tg_validate_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing);
-+
-+void dce120_tg_wait_for_state(struct timing_generator *tg,
-+	enum crtc_state state)
-+{
-+	switch (state) {
-+	case CRTC_STATE_VBLANK:
-+		dce120_timing_generator_wait_for_vblank(tg);
-+		break;
-+
-+	case CRTC_STATE_VACTIVE:
-+		dce120_timing_generator_wait_for_vactive(tg);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+void dce120_tg_set_colors(struct timing_generator *tg,
-+	const struct tg_color *blank_color,
-+	const struct tg_color *overscan_color)
-+{
-+	if (blank_color != NULL)
-+		dce120_tg_program_blank_color(tg, blank_color);
-+
-+	if (overscan_color != NULL)
-+		dce120_tg_set_overscan_color(tg, overscan_color);
-+}
-+
-+static void dce120_timing_generator_set_static_screen_control(
-+	struct timing_generator *tg,
-+	uint32_t value)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+
-+	CRTC_REG_UPDATE_2(CRTC0_CRTC_STATIC_SCREEN_CONTROL,
-+			CRTC_STATIC_SCREEN_EVENT_MASK, value,
-+			CRTC_STATIC_SCREEN_FRAME_COUNT, 2);
-+}
-+
-+void dce120_timing_generator_set_test_pattern(
-+	struct timing_generator *tg,
-+	/* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
-+	 * because this is not DP-specific (which is probably somewhere in DP
-+	 * encoder) */
-+	enum controller_dp_test_pattern test_pattern,
-+	enum dc_color_depth color_depth)
-+{
-+	struct dc_context *ctx = tg->ctx;
-+	uint32_t value;
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	enum test_pattern_color_format bit_depth;
-+	enum test_pattern_dyn_range dyn_range;
-+	enum test_pattern_mode mode;
-+	/* color ramp generator mixes 16-bits color */
-+	uint32_t src_bpc = 16;
-+	/* requested bpc */
-+	uint32_t dst_bpc;
-+	uint32_t index;
-+	/* RGB values of the color bars.
-+	 * Produce two RGB colors: RGB0 - white (all Fs)
-+	 * and RGB1 - black (all 0s)
-+	 * (three RGB components for two colors)
-+	 */
-+	uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
-+						0x0000, 0x0000};
-+	/* dest color (converted to the specified color format) */
-+	uint16_t dst_color[6];
-+	uint32_t inc_base;
-+
-+	/* translate to bit depth */
-+	switch (color_depth) {
-+	case COLOR_DEPTH_666:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
-+	break;
-+	case COLOR_DEPTH_888:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
-+	break;
-+	case COLOR_DEPTH_101010:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
-+	break;
-+	case COLOR_DEPTH_121212:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
-+	break;
-+	default:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
-+	break;
-+	}
-+
-+	switch (test_pattern) {
-+	case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
-+	case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
-+	{
-+		dyn_range = (test_pattern ==
-+				CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
-+				TEST_PATTERN_DYN_RANGE_CEA :
-+				TEST_PATTERN_DYN_RANGE_VESA);
-+		mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
-+
-+		CRTC_REG_UPDATE_2(CRTC0_CRTC_TEST_PATTERN_PARAMETERS,
-+				CRTC_TEST_PATTERN_VRES, 6,
-+				CRTC_TEST_PATTERN_HRES, 6);
-+
-+		CRTC_REG_UPDATE_4(CRTC0_CRTC_TEST_PATTERN_CONTROL,
-+				CRTC_TEST_PATTERN_EN, 1,
-+				CRTC_TEST_PATTERN_MODE, mode,
-+				CRTC_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
-+				CRTC_TEST_PATTERN_COLOR_FORMAT, bit_depth);
-+	}
-+	break;
-+
-+	case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
-+	case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
-+	{
-+		mode = (test_pattern ==
-+			CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
-+			TEST_PATTERN_MODE_VERTICALBARS :
-+			TEST_PATTERN_MODE_HORIZONTALBARS);
-+
-+		switch (bit_depth) {
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_6:
-+			dst_bpc = 6;
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_8:
-+			dst_bpc = 8;
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_10:
-+			dst_bpc = 10;
-+		break;
-+		default:
-+			dst_bpc = 8;
-+		break;
-+		}
-+
-+		/* adjust color to the required colorFormat */
-+		for (index = 0; index < 6; index++) {
-+			/* dst = 2^dstBpc * src / 2^srcBpc = src >>
-+			 * (srcBpc - dstBpc);
-+			 */
-+			dst_color[index] =
-+				src_color[index] >> (src_bpc - dst_bpc);
-+		/* CRTC_TEST_PATTERN_DATA has 16 bits,
-+		 * lowest 6 are hardwired to ZERO
-+		 * color bits should be left aligned aligned to MSB
-+		 * XXXXXXXXXX000000 for 10 bit,
-+		 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
-+		 */
-+			dst_color[index] <<= (16 - dst_bpc);
-+		}
-+
-+		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, 0);
-+
-+		/* We have to write the mask before data, similar to pipeline.
-+		 * For example, for 8 bpc, if we want RGB0 to be magenta,
-+		 * and RGB1 to be cyan,
-+		 * we need to make 7 writes:
-+		 * MASK   DATA
-+		 * 000001 00000000 00000000                     set mask to R0
-+		 * 000010 11111111 00000000     R0 255, 0xFF00, set mask to G0
-+		 * 000100 00000000 00000000     G0 0,   0x0000, set mask to B0
-+		 * 001000 11111111 00000000     B0 255, 0xFF00, set mask to R1
-+		 * 010000 00000000 00000000     R1 0,   0x0000, set mask to G1
-+		 * 100000 11111111 00000000     G1 255, 0xFF00, set mask to B1
-+		 * 100000 11111111 00000000     B1 255, 0xFF00
-+		 *
-+		 * we will make a loop of 6 in which we prepare the mask,
-+		 * then write, then prepare the color for next write.
-+		 * first iteration will write mask only,
-+		 * but each next iteration color prepared in
-+		 * previous iteration will be written within new mask,
-+		 * the last component will written separately,
-+		 * mask is not changing between 6th and 7th write
-+		 * and color will be prepared by last iteration
-+		 */
-+
-+		/* write color, color values mask in CRTC_TEST_PATTERN_MASK
-+		 * is B1, G1, R1, B0, G0, R0
-+		 */
-+		value = 0;
-+		for (index = 0; index < 6; index++) {
-+			/* prepare color mask, first write PATTERN_DATA
-+			 * will have all zeros
-+			 */
-+			set_reg_field_value(
-+				value,
-+				(1 << index),
-+				CRTC0_CRTC_TEST_PATTERN_COLOR,
-+				CRTC_TEST_PATTERN_MASK);
-+			/* write color component */
-+			dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);
-+			/* prepare next color component,
-+			 * will be written in the next iteration
-+			 */
-+			set_reg_field_value(
-+				value,
-+				dst_color[index],
-+				CRTC0_CRTC_TEST_PATTERN_COLOR,
-+				CRTC_TEST_PATTERN_DATA);
-+		}
-+		/* write last color component,
-+		 * it's been already prepared in the loop
-+		 */
-+		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);
-+
-+		/* enable test pattern */
-+		CRTC_REG_UPDATE_4(CRTC0_CRTC_TEST_PATTERN_CONTROL,
-+				CRTC_TEST_PATTERN_EN, 1,
-+				CRTC_TEST_PATTERN_MODE, mode,
-+				CRTC_TEST_PATTERN_DYNAMIC_RANGE, 0,
-+				CRTC_TEST_PATTERN_COLOR_FORMAT, bit_depth);
-+	}
-+	break;
-+
-+	case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
-+	{
-+		mode = (bit_depth ==
-+			TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
-+			TEST_PATTERN_MODE_DUALRAMP_RGB :
-+			TEST_PATTERN_MODE_SINGLERAMP_RGB);
-+
-+		switch (bit_depth) {
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_6:
-+			dst_bpc = 6;
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_8:
-+			dst_bpc = 8;
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_10:
-+			dst_bpc = 10;
-+		break;
-+		default:
-+			dst_bpc = 8;
-+		break;
-+		}
-+
-+		/* increment for the first ramp for one color gradation
-+		 * 1 gradation for 6-bit color is 2^10
-+		 * gradations in 16-bit color
-+		 */
-+		inc_base = (src_bpc - dst_bpc);
-+
-+		switch (bit_depth) {
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_6:
-+		{
-+			CRTC_REG_UPDATE_5(CRTC0_CRTC_TEST_PATTERN_PARAMETERS,
-+					CRTC_TEST_PATTERN_INC0, inc_base,
-+					CRTC_TEST_PATTERN_INC1, 0,
-+					CRTC_TEST_PATTERN_HRES, 6,
-+					CRTC_TEST_PATTERN_VRES, 6,
-+					CRTC_TEST_PATTERN_RAMP0_OFFSET, 0);
-+		}
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_8:
-+		{
-+			CRTC_REG_UPDATE_5(CRTC0_CRTC_TEST_PATTERN_PARAMETERS,
-+					CRTC_TEST_PATTERN_INC0, inc_base,
-+					CRTC_TEST_PATTERN_INC1, 0,
-+					CRTC_TEST_PATTERN_HRES, 8,
-+					CRTC_TEST_PATTERN_VRES, 6,
-+					CRTC_TEST_PATTERN_RAMP0_OFFSET, 0);
-+		}
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_10:
-+		{
-+			CRTC_REG_UPDATE_5(CRTC0_CRTC_TEST_PATTERN_PARAMETERS,
-+					CRTC_TEST_PATTERN_INC0, inc_base,
-+					CRTC_TEST_PATTERN_INC1, inc_base + 2,
-+					CRTC_TEST_PATTERN_HRES, 8,
-+					CRTC_TEST_PATTERN_VRES, 5,
-+					CRTC_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
-+		}
-+		break;
-+		default:
-+		break;
-+		}
-+
-+		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, 0);
-+
-+		/* enable test pattern */
-+		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, 0);
-+
-+		CRTC_REG_UPDATE_4(CRTC0_CRTC_TEST_PATTERN_CONTROL,
-+				CRTC_TEST_PATTERN_EN, 1,
-+				CRTC_TEST_PATTERN_MODE, mode,
-+				CRTC_TEST_PATTERN_DYNAMIC_RANGE, 0,
-+				CRTC_TEST_PATTERN_COLOR_FORMAT, bit_depth);
-+	}
-+	break;
-+	case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
-+	{
-+		value = 0;
-+		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc,  value);
-+		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);
-+		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, value);
-+	}
-+	break;
-+	default:
-+	break;
-+	}
-+}
-+
-+static bool dce120_arm_vert_intr(
-+		struct timing_generator *tg,
-+		uint8_t width)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t v_blank_start, v_blank_end, h_position, v_position;
-+
-+	tg->funcs->get_scanoutpos(
-+				tg,
-+				&v_blank_start,
-+				&v_blank_end,
-+				&h_position,
-+				&v_position);
-+
-+	if (v_blank_start == 0 || v_blank_end == 0)
-+		return false;
-+
-+	CRTC_REG_SET_2(
-+			CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION,
-+			CRTC_VERTICAL_INTERRUPT0_LINE_START, v_blank_start,
-+			CRTC_VERTICAL_INTERRUPT0_LINE_END, v_blank_start + width);
-+
-+	return true;
-+}
-+
-+static const struct timing_generator_funcs dce120_tg_funcs = {
-+		.validate_timing = dce120_tg_validate_timing,
-+		.program_timing = dce120_tg_program_timing,
-+		.enable_crtc = dce120_timing_generator_enable_crtc,
-+		.disable_crtc = dce110_timing_generator_disable_crtc,
-+		/* used by enable_timing_synchronization. Not need for FPGA */
-+		.is_counter_moving = dce110_timing_generator_is_counter_moving,
-+		/* never be called */
-+		.get_position = dce120_timing_generator_get_crtc_position,
-+		.get_frame_count = dce120_timing_generator_get_vblank_counter,
-+		.get_scanoutpos = dce120_timing_generator_get_crtc_scanoutpos,
-+		.set_early_control = dce120_timing_generator_set_early_control,
-+		/* used by enable_timing_synchronization. Not need for FPGA */
-+		.wait_for_state = dce120_tg_wait_for_state,
-+		.set_blank = dce120_tg_set_blank,
-+		.is_blanked = dce120_tg_is_blanked,
-+		/* never be called */
-+		.set_colors = dce120_tg_set_colors,
-+		.set_overscan_blank_color = dce120_timing_generator_set_overscan_color_black,
-+		.set_blank_color = dce120_timing_generator_program_blank_color,
-+		.disable_vga = dce120_timing_generator_disable_vga,
-+		.did_triggered_reset_occur = dce120_timing_generator_did_triggered_reset_occur,
-+		.setup_global_swap_lock = dce120_timing_generator_setup_global_swap_lock,
-+		.enable_reset_trigger = dce120_timing_generator_enable_reset_trigger,
-+		.disable_reset_trigger = dce120_timing_generator_disable_reset_trigger,
-+		.tear_down_global_swap_lock = dce120_timing_generator_tear_down_global_swap_lock,
-+		.enable_advanced_request = dce120_timing_generator_enable_advanced_request,
-+		.set_drr = dce120_timing_generator_set_drr,
-+		.set_static_screen_control = dce120_timing_generator_set_static_screen_control,
-+		.set_test_pattern = dce120_timing_generator_set_test_pattern,
-+		.arm_vert_intr = dce120_arm_vert_intr,
-+};
-+
-+
-+void dce120_timing_generator_construct(
-+	struct dce110_timing_generator *tg110,
-+	struct dc_context *ctx,
-+	uint32_t instance,
-+	const struct dce110_timing_generator_offsets *offsets)
-+{
-+	tg110->controller_id = CONTROLLER_ID_D0 + instance;
-+	tg110->base.inst = instance;
-+
-+	tg110->offsets = *offsets;
-+
-+	tg110->base.funcs = &dce120_tg_funcs;
-+
-+	tg110->base.ctx = ctx;
-+	tg110->base.bp = ctx->dc_bios;
-+
-+	tg110->max_h_total = CRTC0_CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
-+	tg110->max_v_total = CRTC0_CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
-+
-+	/*//CRTC requires a minimum HBLANK = 32 pixels and o
-+	 * Minimum HSYNC = 8 pixels*/
-+	tg110->min_h_blank = 32;
-+	/*DCE12_CRTC_Block_ARch.doc*/
-+	tg110->min_h_front_porch = 0;
-+	tg110->min_h_back_porch = 0;
-+
-+	tg110->min_h_sync_width = 8;
-+	tg110->min_v_sync_width = 1;
-+	tg110->min_v_blank = 3;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h.0130~	2017-12-14 06:39:58.413903566 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h	2017-12-14 06:39:58.413903566 +0100
-@@ -0,0 +1,40 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_TIMING_GENERATOR_DCE120_H__
-+#define __DC_TIMING_GENERATOR_DCE120_H__
-+
-+#include "timing_generator.h"
-+#include "../include/grph_object_id.h"
-+#include "dce110/dce110_timing_generator.h"
-+
-+
-+void dce120_timing_generator_construct(
-+	struct dce110_timing_generator *tg110,
-+	struct dc_context *ctx,
-+	uint32_t instance,
-+	const struct dce110_timing_generator_offsets *offsets);
-+
-+#endif /* __DC_TIMING_GENERATOR_DCE120_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce120/Makefile.0130~	2017-12-14 06:39:58.414903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce120/Makefile	2017-12-14 06:39:58.413903566 +0100
-@@ -0,0 +1,11 @@
-+#
-+# Makefile for the 'controller' sub-component of DAL.
-+# It provides the control and status of HW CRTC block.
-+
-+
-+DCE120 = dce120_resource.o dce120_timing_generator.o \
-+dce120_hw_sequencer.o
-+
-+AMD_DAL_DCE120 = $(addprefix $(AMDDALPATH)/dc/dce120/,$(DCE120))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_DCE120)
-\ No newline at end of file
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c.0130~	2017-12-14 06:39:58.414903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c	2017-12-14 06:39:58.414903567 +0100
-@@ -0,0 +1,834 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+#include "gmc/gmc_7_1_sh_mask.h"
-+#include "gmc/gmc_7_1_d.h"
-+
-+#include "include/logger_interface.h"
-+#include "dce80_compressor.h"
-+
-+#define DCP_REG(reg)\
-+	(reg + cp80->offsets.dcp_offset)
-+#define DMIF_REG(reg)\
-+	(reg + cp80->offsets.dmif_offset)
-+
-+static const struct dce80_compressor_reg_offsets reg_offsets[] = {
-+{
-+	.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset = (mmDMIF_PG0_DPG_PIPE_DPM_CONTROL
-+					- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset = (mmDMIF_PG1_DPG_PIPE_DPM_CONTROL
-+					- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset = (mmDMIF_PG2_DPG_PIPE_DPM_CONTROL
-+					- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset = (mmDMIF_PG3_DPG_PIPE_DPM_CONTROL
-+					- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset = (mmDMIF_PG4_DPG_PIPE_DPM_CONTROL
-+					- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+},
-+{
-+	.dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+	.dmif_offset = (mmDMIF_PG5_DPG_PIPE_DPM_CONTROL
-+					- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
-+}
-+};
-+
-+static const uint32_t dce8_one_lpt_channel_max_resolution = 2048 * 1200;
-+
-+enum fbc_idle_force {
-+	/* Bit 0 - Display registers updated */
-+	FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001,
-+
-+	/* Bit 2 - FBC_GRPH_COMP_EN register updated */
-+	FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002,
-+	/* Bit 3 - FBC_SRC_SEL register updated */
-+	FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004,
-+	/* Bit 4 - FBC_MIN_COMPRESSION register updated */
-+	FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008,
-+	/* Bit 5 - FBC_ALPHA_COMP_EN register updated */
-+	FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010,
-+	/* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
-+	FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020,
-+	/* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
-+	FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040,
-+
-+	/* Bit 24 - Memory write to region 0 defined by MC registers. */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000,
-+	/* Bit 25 - Memory write to region 1 defined by MC registers */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000,
-+	/* Bit 26 - Memory write to region 2 defined by MC registers */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000,
-+	/* Bit 27 - Memory write to region 3 defined by MC registers. */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000,
-+
-+	/* Bit 28 - Memory write from any client other than MCIF */
-+	FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000,
-+	/* Bit 29 - CG statics screen signal is inactive */
-+	FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000,
-+};
-+
-+static uint32_t lpt_size_alignment(struct dce80_compressor *cp80)
-+{
-+	/*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */
-+	return cp80->base.raw_size * cp80->base.banks_num *
-+		cp80->base.dram_channels_num;
-+}
-+
-+static uint32_t lpt_memory_control_config(struct dce80_compressor *cp80,
-+	uint32_t lpt_control)
-+{
-+	/*LPT MC Config */
-+	if (cp80->base.options.bits.LPT_MC_CONFIG == 1) {
-+		/* POSSIBLE VALUES for LPT NUM_PIPES (DRAM CHANNELS):
-+		 * 00 - 1 CHANNEL
-+		 * 01 - 2 CHANNELS
-+		 * 02 - 4 OR 6 CHANNELS
-+		 * (Only for discrete GPU, N/A for CZ)
-+		 * 03 - 8 OR 12 CHANNELS
-+		 * (Only for discrete GPU, N/A for CZ) */
-+		switch (cp80->base.dram_channels_num) {
-+		case 2:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_PIPES);
-+			break;
-+		case 1:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_PIPES);
-+			break;
-+		default:
-+			dm_logger_write(
-+				cp80->base.ctx->logger, LOG_WARNING,
-+				"%s: Invalid LPT NUM_PIPES!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping for LPT NUM_BANKS is in
-+		 * GRPH_CONTROL.GRPH_NUM_BANKS register field
-+		 * Specifies the number of memory banks for tiling
-+		 * purposes. Only applies to 2D and 3D tiling modes.
-+		 * POSSIBLE VALUES:
-+		 * 00 - DCP_GRPH_NUM_BANKS_2BANK: ADDR_SURF_2_BANK
-+		 * 01 - DCP_GRPH_NUM_BANKS_4BANK: ADDR_SURF_4_BANK
-+		 * 02 - DCP_GRPH_NUM_BANKS_8BANK: ADDR_SURF_8_BANK
-+		 * 03 - DCP_GRPH_NUM_BANKS_16BANK: ADDR_SURF_16_BANK */
-+		switch (cp80->base.banks_num) {
-+		case 16:
-+			set_reg_field_value(
-+				lpt_control,
-+				3,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 8:
-+			set_reg_field_value(
-+				lpt_control,
-+				2,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 4:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		case 2:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_NUM_BANKS);
-+			break;
-+		default:
-+			dm_logger_write(
-+				cp80->base.ctx->logger, LOG_WARNING,
-+				"%s: Invalid LPT NUM_BANKS!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping is in DMIF_ADDR_CALC.
-+		 * ADDR_CONFIG_PIPE_INTERLEAVE_SIZE register field for
-+		 * Carrizo specifies the memory interleave per pipe.
-+		 * It effectively specifies the location of pipe bits in
-+		 * the memory address.
-+		 * POSSIBLE VALUES:
-+		 * 00 - ADDR_CONFIG_PIPE_INTERLEAVE_256B: 256 byte
-+		 * interleave
-+		 * 01 - ADDR_CONFIG_PIPE_INTERLEAVE_512B: 512 byte
-+		 * interleave
-+		 */
-+		switch (cp80->base.channel_interleave_size) {
-+		case 256: /*256B */
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
-+			break;
-+		case 512: /*512B */
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
-+			break;
-+		default:
-+			dm_logger_write(
-+				cp80->base.ctx->logger, LOG_WARNING,
-+				"%s: Invalid LPT INTERLEAVE_SIZE!!!",
-+				__func__);
-+			break;
-+		}
-+
-+		/* The mapping for LOW_POWER_TILING_ROW_SIZE is in
-+		 * DMIF_ADDR_CALC.ADDR_CONFIG_ROW_SIZE register field
-+		 * for Carrizo. Specifies the size of dram row in bytes.
-+		 * This should match up with NOOFCOLS field in
-+		 * MC_ARB_RAMCFG (ROW_SIZE = 4 * 2 ^^ columns).
-+		 * This register DMIF_ADDR_CALC is not used by the
-+		 * hardware as it is only used for addrlib assertions.
-+		 * POSSIBLE VALUES:
-+		 * 00 - ADDR_CONFIG_1KB_ROW: Treat 1KB as DRAM row
-+		 * boundary
-+		 * 01 - ADDR_CONFIG_2KB_ROW: Treat 2KB as DRAM row
-+		 * boundary
-+		 * 02 - ADDR_CONFIG_4KB_ROW: Treat 4KB as DRAM row
-+		 * boundary */
-+		switch (cp80->base.raw_size) {
-+		case 4096: /*4 KB */
-+			set_reg_field_value(
-+				lpt_control,
-+				2,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		case 2048:
-+			set_reg_field_value(
-+				lpt_control,
-+				1,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		case 1024:
-+			set_reg_field_value(
-+				lpt_control,
-+				0,
-+				LOW_POWER_TILING_CONTROL,
-+				LOW_POWER_TILING_ROW_SIZE);
-+			break;
-+		default:
-+			dm_logger_write(
-+				cp80->base.ctx->logger, LOG_WARNING,
-+				"%s: Invalid LPT ROW_SIZE!!!",
-+				__func__);
-+			break;
-+		}
-+	} else {
-+		dm_logger_write(
-+			cp80->base.ctx->logger, LOG_WARNING,
-+			"%s: LPT MC Configuration is not provided",
-+			__func__);
-+	}
-+
-+	return lpt_control;
-+}
-+
-+static bool is_source_bigger_than_epanel_size(
-+	struct dce80_compressor *cp80,
-+	uint32_t source_view_width,
-+	uint32_t source_view_height)
-+{
-+	if (cp80->base.embedded_panel_h_size != 0 &&
-+		cp80->base.embedded_panel_v_size != 0 &&
-+		((source_view_width * source_view_height) >
-+		(cp80->base.embedded_panel_h_size *
-+			cp80->base.embedded_panel_v_size)))
-+		return true;
-+
-+	return false;
-+}
-+
-+static uint32_t align_to_chunks_number_per_line(
-+	struct dce80_compressor *cp80,
-+	uint32_t pixels)
-+{
-+	return 256 * ((pixels + 255) / 256);
-+}
-+
-+static void wait_for_fbc_state_changed(
-+	struct dce80_compressor *cp80,
-+	bool enabled)
-+{
-+	uint8_t counter = 0;
-+	uint32_t addr = mmFBC_STATUS;
-+	uint32_t value;
-+
-+	while (counter < 10) {
-+		value = dm_read_reg(cp80->base.ctx, addr);
-+		if (get_reg_field_value(
-+			value,
-+			FBC_STATUS,
-+			FBC_ENABLE_STATUS) == enabled)
-+			break;
-+		udelay(10);
-+		counter++;
-+	}
-+
-+	if (counter == 10) {
-+		dm_logger_write(
-+			cp80->base.ctx->logger, LOG_WARNING,
-+			"%s: wait counter exceeded, changes to HW not applied",
-+			__func__);
-+	}
-+}
-+
-+void dce80_compressor_power_up_fbc(struct compressor *compressor)
-+{
-+	uint32_t value;
-+	uint32_t addr;
-+
-+	addr = mmFBC_CNTL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+	set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
-+	set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	addr = mmFBC_COMP_MODE;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN);
-+	set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	addr = mmFBC_COMP_CNTL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN);
-+	dm_write_reg(compressor->ctx, addr, value);
-+	/*FBC_MIN_COMPRESSION 0 ==> 2:1 */
-+	/*                    1 ==> 4:1 */
-+	/*                    2 ==> 8:1 */
-+	/*                  0xF ==> 1:1 */
-+	set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION);
-+	dm_write_reg(compressor->ctx, addr, value);
-+	compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;
-+
-+	value = 0;
-+	dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
-+
-+	value = 0xFFFFFF;
-+	dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
-+}
-+
-+void dce80_compressor_enable_fbc(
-+	struct compressor *compressor,
-+	uint32_t paths_num,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce80_compressor *cp80 = TO_DCE80_COMPRESSOR(compressor);
-+
-+	if (compressor->options.bits.FBC_SUPPORT &&
-+		(compressor->options.bits.DUMMY_BACKEND == 0) &&
-+		(!dce80_compressor_is_fbc_enabled_in_hw(compressor, NULL)) &&
-+		(!is_source_bigger_than_epanel_size(
-+			cp80,
-+			params->source_view_width,
-+			params->source_view_height))) {
-+
-+		uint32_t addr;
-+		uint32_t value;
-+
-+		/* Before enabling FBC first need to enable LPT if applicable
-+		 * LPT state should always be changed (enable/disable) while FBC
-+		 * is disabled */
-+		if (compressor->options.bits.LPT_SUPPORT && (paths_num < 2) &&
-+			(params->source_view_width *
-+				params->source_view_height <=
-+				dce8_one_lpt_channel_max_resolution)) {
-+			dce80_compressor_enable_lpt(compressor);
-+		}
-+
-+		addr = mmFBC_CNTL;
-+		value = dm_read_reg(compressor->ctx, addr);
-+		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		set_reg_field_value(
-+			value,
-+			params->inst,
-+			FBC_CNTL, FBC_SRC_SEL);
-+		dm_write_reg(compressor->ctx, addr, value);
-+
-+		/* Keep track of enum controller_id FBC is attached to */
-+		compressor->is_enabled = true;
-+		compressor->attached_inst = params->inst;
-+		cp80->offsets = reg_offsets[params->inst];
-+
-+		/*Toggle it as there is bug in HW */
-+		set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, addr, value);
-+		set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, addr, value);
-+
-+		wait_for_fbc_state_changed(cp80, true);
-+	}
-+}
-+
-+void dce80_compressor_disable_fbc(struct compressor *compressor)
-+{
-+	struct dce80_compressor *cp80 = TO_DCE80_COMPRESSOR(compressor);
-+
-+	if (compressor->options.bits.FBC_SUPPORT &&
-+		dce80_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
-+		uint32_t reg_data;
-+		/* Turn off compression */
-+		reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
-+		set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
-+		dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
-+
-+		/* Reset enum controller_id to undefined */
-+		compressor->attached_inst = 0;
-+		compressor->is_enabled = false;
-+
-+		/* Whenever disabling FBC make sure LPT is disabled if LPT
-+		 * supported */
-+		if (compressor->options.bits.LPT_SUPPORT)
-+			dce80_compressor_disable_lpt(compressor);
-+
-+		wait_for_fbc_state_changed(cp80, false);
-+	}
-+}
-+
-+bool dce80_compressor_is_fbc_enabled_in_hw(
-+	struct compressor *compressor,
-+	uint32_t *inst)
-+{
-+	/* Check the hardware register */
-+	uint32_t value;
-+
-+	value = dm_read_reg(compressor->ctx, mmFBC_STATUS);
-+	if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
-+		if (inst != NULL)
-+			*inst = compressor->attached_inst;
-+		return true;
-+	}
-+
-+	value = dm_read_reg(compressor->ctx, mmFBC_CNTL);
-+	if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
-+		if (inst != NULL)
-+			*inst =	compressor->attached_inst;
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+bool dce80_compressor_is_lpt_enabled_in_hw(struct compressor *compressor)
-+{
-+	/* Check the hardware register */
-+	uint32_t value = dm_read_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL);
-+
-+	return get_reg_field_value(
-+		value,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+}
-+
-+void dce80_compressor_program_compressed_surface_address_and_pitch(
-+	struct compressor *compressor,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce80_compressor *cp80 = TO_DCE80_COMPRESSOR(compressor);
-+	uint32_t value = 0;
-+	uint32_t fbc_pitch = 0;
-+	uint32_t compressed_surf_address_low_part =
-+		compressor->compr_surface_address.addr.low_part;
-+
-+	/* Clear content first. */
-+	dm_write_reg(
-+		compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
-+		0);
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0);
-+
-+	if (compressor->options.bits.LPT_SUPPORT) {
-+		uint32_t lpt_alignment = lpt_size_alignment(cp80);
-+
-+		if (lpt_alignment != 0) {
-+			compressed_surf_address_low_part =
-+				((compressed_surf_address_low_part
-+					+ (lpt_alignment - 1)) / lpt_alignment)
-+					* lpt_alignment;
-+		}
-+	}
-+
-+	/* Write address, HIGH has to be first. */
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
-+		compressor->compr_surface_address.addr.high_part);
-+	dm_write_reg(compressor->ctx,
-+		DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS),
-+		compressed_surf_address_low_part);
-+
-+	fbc_pitch = align_to_chunks_number_per_line(
-+		cp80,
-+		params->source_view_width);
-+
-+	if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
-+		fbc_pitch = fbc_pitch / 8;
-+	else
-+		dm_logger_write(
-+			compressor->ctx->logger, LOG_WARNING,
-+			"%s: Unexpected DCE8 compression ratio",
-+			__func__);
-+
-+	/* Clear content first. */
-+	dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);
-+
-+	/* Write FBC Pitch. */
-+	set_reg_field_value(
-+		value,
-+		fbc_pitch,
-+		GRPH_COMPRESS_PITCH,
-+		GRPH_COMPRESS_PITCH);
-+	dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);
-+
-+}
-+
-+void dce80_compressor_disable_lpt(struct compressor *compressor)
-+{
-+	struct dce80_compressor *cp80 = TO_DCE80_COMPRESSOR(compressor);
-+	uint32_t value;
-+	uint32_t addr;
-+	uint32_t inx;
-+
-+	/* Disable all pipes LPT Stutter */
-+	for (inx = 0; inx < 3; inx++) {
-+		value =
-+			dm_read_reg(
-+				compressor->ctx,
-+				DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
-+			STUTTER_ENABLE_NONLPTCH);
-+		dm_write_reg(
-+			compressor->ctx,
-+			DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH),
-+			value);
-+	}
-+
-+	/* Disable LPT */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Clear selection of Channel(s) containing Compressed Surface */
-+	addr = mmGMCON_LPT_TARGET;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		0xFFFFFFFF,
-+		GMCON_LPT_TARGET,
-+		STCTRL_LPT_TARGET);
-+	dm_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value);
-+}
-+
-+void dce80_compressor_enable_lpt(struct compressor *compressor)
-+{
-+	struct dce80_compressor *cp80 = TO_DCE80_COMPRESSOR(compressor);
-+	uint32_t value;
-+	uint32_t addr;
-+	uint32_t value_control;
-+	uint32_t channels;
-+
-+	/* Enable LPT Stutter from Display pipe */
-+	value = dm_read_reg(compressor->ctx,
-+		DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
-+		STUTTER_ENABLE_NONLPTCH);
-+	dm_write_reg(compressor->ctx,
-+		DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), value);
-+
-+	/* Selection of Channel(s) containing Compressed Surface: 0xfffffff
-+	 * will disable LPT.
-+	 * STCTRL_LPT_TARGETn corresponds to channel n. */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value_control = dm_read_reg(compressor->ctx, addr);
-+	channels = get_reg_field_value(value_control,
-+			LOW_POWER_TILING_CONTROL,
-+			LOW_POWER_TILING_MODE);
-+
-+	addr = mmGMCON_LPT_TARGET;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		channels + 1, /* not mentioned in programming guide,
-+				but follow DCE8.1 */
-+		GMCON_LPT_TARGET,
-+		STCTRL_LPT_TARGET);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Enable LPT */
-+	addr = mmLOW_POWER_TILING_CONTROL;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		1,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ENABLE);
-+	dm_write_reg(compressor->ctx, addr, value);
-+}
-+
-+void dce80_compressor_program_lpt_control(
-+	struct compressor *compressor,
-+	struct compr_addr_and_pitch_params *params)
-+{
-+	struct dce80_compressor *cp80 = TO_DCE80_COMPRESSOR(compressor);
-+	uint32_t rows_per_channel;
-+	uint32_t lpt_alignment;
-+	uint32_t source_view_width;
-+	uint32_t source_view_height;
-+	uint32_t lpt_control = 0;
-+
-+	if (!compressor->options.bits.LPT_SUPPORT)
-+		return;
-+
-+	lpt_control = dm_read_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL);
-+
-+	/* POSSIBLE VALUES for Low Power Tiling Mode:
-+	 * 00 - Use channel 0
-+	 * 01 - Use Channel 0 and 1
-+	 * 02 - Use Channel 0,1,2,3
-+	 * 03 - reserved */
-+	switch (compressor->lpt_channels_num) {
-+	/* case 2:
-+	 * Use Channel 0 & 1 / Not used for DCE 11 */
-+	case 1:
-+		/*Use Channel 0 for LPT for DCE 11 */
-+		set_reg_field_value(
-+			lpt_control,
-+			0,
-+			LOW_POWER_TILING_CONTROL,
-+			LOW_POWER_TILING_MODE);
-+		break;
-+	default:
-+		dm_logger_write(
-+			compressor->ctx->logger, LOG_WARNING,
-+			"%s: Invalid selected DRAM channels for LPT!!!",
-+			__func__);
-+		break;
-+	}
-+
-+	lpt_control = lpt_memory_control_config(cp80, lpt_control);
-+
-+	/* Program LOW_POWER_TILING_ROWS_PER_CHAN field which depends on
-+	 * FBC compressed surface pitch.
-+	 * LOW_POWER_TILING_ROWS_PER_CHAN = Roundup ((Surface Height *
-+	 * Surface Pitch) / (Row Size * Number of Channels *
-+	 * Number of Banks)). */
-+	rows_per_channel = 0;
-+	lpt_alignment = lpt_size_alignment(cp80);
-+	source_view_width =
-+		align_to_chunks_number_per_line(
-+			cp80,
-+			params->source_view_width);
-+	source_view_height = (params->source_view_height + 1) & (~0x1);
-+
-+	if (lpt_alignment != 0) {
-+		rows_per_channel = source_view_width * source_view_height * 4;
-+		rows_per_channel =
-+			(rows_per_channel % lpt_alignment) ?
-+				(rows_per_channel / lpt_alignment + 1) :
-+				rows_per_channel / lpt_alignment;
-+	}
-+
-+	set_reg_field_value(
-+		lpt_control,
-+		rows_per_channel,
-+		LOW_POWER_TILING_CONTROL,
-+		LOW_POWER_TILING_ROWS_PER_CHAN);
-+
-+	dm_write_reg(compressor->ctx,
-+		mmLOW_POWER_TILING_CONTROL, lpt_control);
-+}
-+
-+/*
-+ * DCE 11 Frame Buffer Compression Implementation
-+ */
-+
-+void dce80_compressor_set_fbc_invalidation_triggers(
-+	struct compressor *compressor,
-+	uint32_t fbc_trigger)
-+{
-+	/* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19)
-+	 * for DCE 11 regions cannot be used - does not work with S/G
-+	 */
-+	uint32_t addr = mmFBC_CLIENT_REGION_MASK;
-+	uint32_t value = dm_read_reg(compressor->ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		FBC_CLIENT_REGION_MASK,
-+		FBC_MEMORY_REGION_MASK);
-+	dm_write_reg(compressor->ctx, addr, value);
-+
-+	/* Setup events when to clear all CSM entries (effectively marking
-+	 * current compressed data invalid)
-+	 * For DCE 11 CSM metadata 11111 means - "Not Compressed"
-+	 * Used as the initial value of the metadata sent to the compressor
-+	 * after invalidation, to indicate that the compressor should attempt
-+	 * to compress all chunks on the current pass.  Also used when the chunk
-+	 * is not successfully written to memory.
-+	 * When this CSM value is detected, FBC reads from the uncompressed
-+	 * buffer. Set events according to passed in value, these events are
-+	 * valid for DCE8:
-+	 *     - bit  0 - display register updated
-+	 *     - bit 28 - memory write from any client except from MCIF
-+	 *     - bit 29 - CG static screen signal is inactive
-+	 * In addition, DCE8.1 also needs to set new DCE8.1 specific events
-+	 * that are used to trigger invalidation on certain register changes,
-+	 * for example enabling of Alpha Compression may trigger invalidation of
-+	 * FBC once bit is set. These events are as follows:
-+	 *      - Bit 2 - FBC_GRPH_COMP_EN register updated
-+	 *      - Bit 3 - FBC_SRC_SEL register updated
-+	 *      - Bit 4 - FBC_MIN_COMPRESSION register updated
-+	 *      - Bit 5 - FBC_ALPHA_COMP_EN register updated
-+	 *      - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated
-+	 *      - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated
-+	 */
-+	addr = mmFBC_IDLE_FORCE_CLEAR_MASK;
-+	value = dm_read_reg(compressor->ctx, addr);
-+	set_reg_field_value(
-+		value,
-+		fbc_trigger |
-+		FBC_IDLE_FORCE_GRPH_COMP_EN |
-+		FBC_IDLE_FORCE_SRC_SEL_CHANGE |
-+		FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE |
-+		FBC_IDLE_FORCE_ALPHA_COMP_EN |
-+		FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN |
-+		FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF,
-+		FBC_IDLE_FORCE_CLEAR_MASK,
-+		FBC_IDLE_FORCE_CLEAR_MASK);
-+	dm_write_reg(compressor->ctx, addr, value);
-+}
-+
-+void dce80_compressor_construct(struct dce80_compressor *compressor,
-+	struct dc_context *ctx)
-+{
-+	struct dc_bios *bp = ctx->dc_bios;
-+	struct embedded_panel_info panel_info;
-+
-+	compressor->base.options.raw = 0;
-+	compressor->base.options.bits.FBC_SUPPORT = true;
-+	compressor->base.options.bits.LPT_SUPPORT = true;
-+	 /* For DCE 11 always use one DRAM channel for LPT */
-+	compressor->base.lpt_channels_num = 1;
-+	compressor->base.options.bits.DUMMY_BACKEND = false;
-+
-+	/* Check if this system has more than 1 DRAM channel; if only 1 then LPT
-+	 * should not be supported */
-+	if (compressor->base.memory_bus_width == 64)
-+		compressor->base.options.bits.LPT_SUPPORT = false;
-+
-+	compressor->base.options.bits.CLK_GATING_DISABLED = false;
-+
-+	compressor->base.ctx = ctx;
-+	compressor->base.embedded_panel_h_size = 0;
-+	compressor->base.embedded_panel_v_size = 0;
-+	compressor->base.memory_bus_width = ctx->asic_id.vram_width;
-+	compressor->base.allocated_size = 0;
-+	compressor->base.preferred_requested_size = 0;
-+	compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
-+	compressor->base.banks_num = 0;
-+	compressor->base.raw_size = 0;
-+	compressor->base.channel_interleave_size = 0;
-+	compressor->base.dram_channels_num = 0;
-+	compressor->base.lpt_channels_num = 0;
-+	compressor->base.attached_inst = 0;
-+	compressor->base.is_enabled = false;
-+
-+	if (BP_RESULT_OK ==
-+			bp->funcs->get_embedded_panel_info(bp, &panel_info)) {
-+		compressor->base.embedded_panel_h_size =
-+			panel_info.lcd_timing.horizontal_addressable;
-+		compressor->base.embedded_panel_v_size =
-+			panel_info.lcd_timing.vertical_addressable;
-+	}
-+}
-+
-+struct compressor *dce80_compressor_create(struct dc_context *ctx)
-+{
-+	struct dce80_compressor *cp80 =
-+		kzalloc(sizeof(struct dce80_compressor), GFP_KERNEL);
-+
-+	if (!cp80)
-+		return NULL;
-+
-+	dce80_compressor_construct(cp80, ctx);
-+	return &cp80->base;
-+}
-+
-+void dce80_compressor_destroy(struct compressor **compressor)
-+{
-+	kfree(TO_DCE80_COMPRESSOR(*compressor));
-+	*compressor = NULL;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.h.0130~	2017-12-14 06:39:58.414903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.h	2017-12-14 06:39:58.414903567 +0100
-@@ -0,0 +1,78 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_COMPRESSOR_DCE80_H__
-+#define __DC_COMPRESSOR_DCE80_H__
-+
-+#include "../inc/compressor.h"
-+
-+#define TO_DCE80_COMPRESSOR(compressor)\
-+	container_of(compressor, struct dce80_compressor, base)
-+
-+struct dce80_compressor_reg_offsets {
-+	uint32_t dcp_offset;
-+	uint32_t dmif_offset;
-+};
-+
-+struct dce80_compressor {
-+	struct compressor base;
-+	struct dce80_compressor_reg_offsets offsets;
-+};
-+
-+struct compressor *dce80_compressor_create(struct dc_context *ctx);
-+
-+void dce80_compressor_construct(struct dce80_compressor *cp80,
-+		struct dc_context *ctx);
-+
-+void dce80_compressor_destroy(struct compressor **cp);
-+
-+/* FBC RELATED */
-+void dce80_compressor_power_up_fbc(struct compressor *cp);
-+
-+void dce80_compressor_enable_fbc(struct compressor *cp, uint32_t paths_num,
-+	struct compr_addr_and_pitch_params *params);
-+
-+void dce80_compressor_disable_fbc(struct compressor *cp);
-+
-+void dce80_compressor_set_fbc_invalidation_triggers(struct compressor *cp,
-+	uint32_t fbc_trigger);
-+
-+void dce80_compressor_program_compressed_surface_address_and_pitch(
-+	struct compressor *cp,
-+	struct compr_addr_and_pitch_params *params);
-+
-+bool dce80_compressor_is_fbc_enabled_in_hw(struct compressor *cp,
-+	uint32_t *fbc_mapped_crtc_id);
-+
-+/* LPT RELATED */
-+void dce80_compressor_enable_lpt(struct compressor *cp);
-+
-+void dce80_compressor_disable_lpt(struct compressor *cp);
-+
-+void dce80_compressor_program_lpt_control(struct compressor *cp,
-+	struct compr_addr_and_pitch_params *params);
-+
-+bool dce80_compressor_is_lpt_enabled_in_hw(struct compressor *cp);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c.0130~	2017-12-14 06:39:58.414903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c	2017-12-14 06:39:58.414903567 +0100
-@@ -0,0 +1,117 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dc.h"
-+#include "core_types.h"
-+#include "dce80_hw_sequencer.h"
-+
-+#include "dce/dce_hwseq.h"
-+#include "dce110/dce110_hw_sequencer.h"
-+#include "dce100/dce100_hw_sequencer.h"
-+
-+/* include DCE8 register header files */
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+struct dce80_hw_seq_reg_offsets {
-+	uint32_t crtc;
-+};
-+
-+static const struct dce80_hw_seq_reg_offsets reg_offsets[] = {
-+{
-+	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
-+}
-+};
-+
-+#define HW_REG_CRTC(reg, id)\
-+	(reg + reg_offsets[id].crtc)
-+
-+/*******************************************************************************
-+ * Private definitions
-+ ******************************************************************************/
-+
-+/***************************PIPE_CONTROL***********************************/
-+
-+static bool dce80_enable_display_power_gating(
-+	struct dc *dc,
-+	uint8_t controller_id,
-+	struct dc_bios *dcb,
-+	enum pipe_gating_control power_gating)
-+{
-+	enum bp_result bp_result = BP_RESULT_OK;
-+	enum bp_pipe_control_action cntl;
-+	struct dc_context *ctx = dc->ctx;
-+
-+	if (power_gating == PIPE_GATING_CONTROL_INIT)
-+		cntl = ASIC_PIPE_INIT;
-+	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
-+		cntl = ASIC_PIPE_ENABLE;
-+	else
-+		cntl = ASIC_PIPE_DISABLE;
-+
-+	if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){
-+
-+		bp_result = dcb->funcs->enable_disp_power_gating(
-+						dcb, controller_id + 1, cntl);
-+
-+		/* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
-+		 * by default when command table is called
-+		 */
-+		dm_write_reg(ctx,
-+			HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id),
-+			0);
-+	}
-+
-+	if (bp_result == BP_RESULT_OK)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+void dce80_hw_sequencer_construct(struct dc *dc)
-+{
-+	dce110_hw_sequencer_construct(dc);
-+
-+	dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
-+	dc->hwss.pipe_control_lock = dce_pipe_control_lock;
-+	dc->hwss.set_bandwidth = dce100_set_bandwidth;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h.0130~	2017-12-14 06:39:58.414903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h	2017-12-14 06:39:58.414903567 +0100
-@@ -0,0 +1,36 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_HWSS_DCE80_H__
-+#define __DC_HWSS_DCE80_H__
-+
-+#include "core_types.h"
-+
-+struct dc;
-+
-+void dce80_hw_sequencer_construct(struct dc *dc);
-+
-+#endif /* __DC_HWSS_DCE80_H__ */
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c.0130~	2017-12-14 06:39:58.414903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c	2017-12-14 06:39:58.414903567 +0100
-@@ -0,0 +1,1259 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#include "dm_services.h"
-+
-+#include "link_encoder.h"
-+#include "stream_encoder.h"
-+
-+#include "resource.h"
-+#include "include/irq_service_interface.h"
-+#include "irq/dce80/irq_service_dce80.h"
-+#include "dce110/dce110_timing_generator.h"
-+#include "dce110/dce110_resource.h"
-+#include "dce80/dce80_timing_generator.h"
-+#include "dce/dce_mem_input.h"
-+#include "dce/dce_link_encoder.h"
-+#include "dce/dce_stream_encoder.h"
-+#include "dce/dce_mem_input.h"
-+#include "dce/dce_ipp.h"
-+#include "dce/dce_transform.h"
-+#include "dce/dce_opp.h"
-+#include "dce/dce_clocks.h"
-+#include "dce/dce_clock_source.h"
-+#include "dce/dce_audio.h"
-+#include "dce/dce_hwseq.h"
-+#include "dce80/dce80_hw_sequencer.h"
-+#include "dce100/dce100_resource.h"
-+
-+#include "reg_helper.h"
-+
-+/* TODO remove this include */
-+
-+#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
-+#include "gmc/gmc_7_1_d.h"
-+#include "gmc/gmc_7_1_sh_mask.h"
-+#endif
-+
-+#ifndef mmDP_DPHY_INTERNAL_CTRL
-+#define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
-+#define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
-+#define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
-+#define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
-+#define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
-+#define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
-+#define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
-+#define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE
-+#endif
-+
-+
-+#ifndef mmBIOS_SCRATCH_2
-+	#define mmBIOS_SCRATCH_2 0x05CB
-+	#define mmBIOS_SCRATCH_6 0x05CF
-+#endif
-+
-+#ifndef mmDP_DPHY_FAST_TRAINING
-+	#define mmDP_DPHY_FAST_TRAINING                         0x1CCE
-+	#define mmDP0_DP_DPHY_FAST_TRAINING                     0x1CCE
-+	#define mmDP1_DP_DPHY_FAST_TRAINING                     0x1FCE
-+	#define mmDP2_DP_DPHY_FAST_TRAINING                     0x42CE
-+	#define mmDP3_DP_DPHY_FAST_TRAINING                     0x45CE
-+	#define mmDP4_DP_DPHY_FAST_TRAINING                     0x48CE
-+	#define mmDP5_DP_DPHY_FAST_TRAINING                     0x4BCE
-+	#define mmDP6_DP_DPHY_FAST_TRAINING                     0x4ECE
-+#endif
-+
-+
-+#ifndef mmHPD_DC_HPD_CONTROL
-+	#define mmHPD_DC_HPD_CONTROL                            0x189A
-+	#define mmHPD0_DC_HPD_CONTROL                           0x189A
-+	#define mmHPD1_DC_HPD_CONTROL                           0x18A2
-+	#define mmHPD2_DC_HPD_CONTROL                           0x18AA
-+	#define mmHPD3_DC_HPD_CONTROL                           0x18B2
-+	#define mmHPD4_DC_HPD_CONTROL                           0x18BA
-+	#define mmHPD5_DC_HPD_CONTROL                           0x18C2
-+#endif
-+
-+#define DCE11_DIG_FE_CNTL 0x4a00
-+#define DCE11_DIG_BE_CNTL 0x4a47
-+#define DCE11_DP_SEC 0x4ac3
-+
-+static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
-+		{
-+			.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
-+			.dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
-+					- mmDPG_WATERMARK_MASK_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
-+			.dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
-+					- mmDPG_WATERMARK_MASK_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
-+			.dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
-+					- mmDPG_WATERMARK_MASK_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
-+			.dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
-+					- mmDPG_WATERMARK_MASK_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
-+			.dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
-+					- mmDPG_WATERMARK_MASK_CONTROL),
-+		},
-+		{
-+			.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
-+			.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
-+			.dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
-+					- mmDPG_WATERMARK_MASK_CONTROL),
-+		}
-+};
-+
-+/* set register offset */
-+#define SR(reg_name)\
-+	.reg_name = mm ## reg_name
-+
-+/* set register offset with instance */
-+#define SRI(reg_name, block, id)\
-+	.reg_name = mm ## block ## id ## _ ## reg_name
-+
-+
-+static const struct dce_disp_clk_registers disp_clk_regs = {
-+		CLK_COMMON_REG_LIST_DCE_BASE()
-+};
-+
-+static const struct dce_disp_clk_shift disp_clk_shift = {
-+		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
-+};
-+
-+static const struct dce_disp_clk_mask disp_clk_mask = {
-+		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
-+};
-+
-+#define ipp_regs(id)\
-+[id] = {\
-+		IPP_COMMON_REG_LIST_DCE_BASE(id)\
-+}
-+
-+static const struct dce_ipp_registers ipp_regs[] = {
-+		ipp_regs(0),
-+		ipp_regs(1),
-+		ipp_regs(2),
-+		ipp_regs(3),
-+		ipp_regs(4),
-+		ipp_regs(5)
-+};
-+
-+static const struct dce_ipp_shift ipp_shift = {
-+		IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
-+};
-+
-+static const struct dce_ipp_mask ipp_mask = {
-+		IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
-+};
-+
-+#define transform_regs(id)\
-+[id] = {\
-+		XFM_COMMON_REG_LIST_DCE80(id)\
-+}
-+
-+static const struct dce_transform_registers xfm_regs[] = {
-+		transform_regs(0),
-+		transform_regs(1),
-+		transform_regs(2),
-+		transform_regs(3),
-+		transform_regs(4),
-+		transform_regs(5)
-+};
-+
-+static const struct dce_transform_shift xfm_shift = {
-+		XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
-+};
-+
-+static const struct dce_transform_mask xfm_mask = {
-+		XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
-+};
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	AUX_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
-+	aux_regs(0),
-+	aux_regs(1),
-+	aux_regs(2),
-+	aux_regs(3),
-+	aux_regs(4),
-+	aux_regs(5)
-+};
-+
-+#define hpd_regs(id)\
-+[id] = {\
-+	HPD_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
-+		hpd_regs(0),
-+		hpd_regs(1),
-+		hpd_regs(2),
-+		hpd_regs(3),
-+		hpd_regs(4),
-+		hpd_regs(5)
-+};
-+
-+#define link_regs(id)\
-+[id] = {\
-+	LE_DCE80_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_registers link_enc_regs[] = {
-+	link_regs(0),
-+	link_regs(1),
-+	link_regs(2),
-+	link_regs(3),
-+	link_regs(4),
-+	link_regs(5),
-+	link_regs(6),
-+};
-+
-+#define stream_enc_regs(id)\
-+[id] = {\
-+	SE_COMMON_REG_LIST_DCE_BASE(id),\
-+	.AFMT_CNTL = 0,\
-+}
-+
-+static const struct dce110_stream_enc_registers stream_enc_regs[] = {
-+	stream_enc_regs(0),
-+	stream_enc_regs(1),
-+	stream_enc_regs(2),
-+	stream_enc_regs(3),
-+	stream_enc_regs(4),
-+	stream_enc_regs(5),
-+	stream_enc_regs(6)
-+};
-+
-+static const struct dce_stream_encoder_shift se_shift = {
-+		SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
-+};
-+
-+static const struct dce_stream_encoder_mask se_mask = {
-+		SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
-+};
-+
-+#define opp_regs(id)\
-+[id] = {\
-+	OPP_DCE_80_REG_LIST(id),\
-+}
-+
-+static const struct dce_opp_registers opp_regs[] = {
-+	opp_regs(0),
-+	opp_regs(1),
-+	opp_regs(2),
-+	opp_regs(3),
-+	opp_regs(4),
-+	opp_regs(5)
-+};
-+
-+static const struct dce_opp_shift opp_shift = {
-+	OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
-+};
-+
-+static const struct dce_opp_mask opp_mask = {
-+	OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
-+};
-+
-+#define audio_regs(id)\
-+[id] = {\
-+	AUD_COMMON_REG_LIST(id)\
-+}
-+
-+static const struct dce_audio_registers audio_regs[] = {
-+	audio_regs(0),
-+	audio_regs(1),
-+	audio_regs(2),
-+	audio_regs(3),
-+	audio_regs(4),
-+	audio_regs(5),
-+	audio_regs(6),
-+};
-+
-+static const struct dce_audio_shift audio_shift = {
-+		AUD_COMMON_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct dce_aduio_mask audio_mask = {
-+		AUD_COMMON_MASK_SH_LIST(_MASK)
-+};
-+
-+#define clk_src_regs(id)\
-+[id] = {\
-+	CS_COMMON_REG_LIST_DCE_80(id),\
-+}
-+
-+
-+static const struct dce110_clk_src_regs clk_src_regs[] = {
-+	clk_src_regs(0),
-+	clk_src_regs(1),
-+	clk_src_regs(2)
-+};
-+
-+static const struct dce110_clk_src_shift cs_shift = {
-+		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
-+};
-+
-+static const struct dce110_clk_src_mask cs_mask = {
-+		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
-+};
-+
-+static const struct bios_registers bios_regs = {
-+	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
-+};
-+
-+static const struct resource_caps res_cap = {
-+		.num_timing_generator = 6,
-+		.num_audio = 6,
-+		.num_stream_encoder = 6,
-+		.num_pll = 3,
-+};
-+
-+static const struct resource_caps res_cap_81 = {
-+		.num_timing_generator = 4,
-+		.num_audio = 7,
-+		.num_stream_encoder = 7,
-+		.num_pll = 3,
-+};
-+
-+static const struct resource_caps res_cap_83 = {
-+		.num_timing_generator = 2,
-+		.num_audio = 6,
-+		.num_stream_encoder = 6,
-+		.num_pll = 2,
-+};
-+
-+#define CTX  ctx
-+#define REG(reg) mm ## reg
-+
-+#ifndef mmCC_DC_HDMI_STRAPS
-+#define mmCC_DC_HDMI_STRAPS 0x1918
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
-+#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
-+#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
-+#endif
-+
-+static void read_dce_straps(
-+	struct dc_context *ctx,
-+	struct resource_straps *straps)
-+{
-+	REG_GET_2(CC_DC_HDMI_STRAPS,
-+			HDMI_DISABLE, &straps->hdmi_disable,
-+			AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
-+
-+	REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
-+}
-+
-+static struct audio *create_audio(
-+		struct dc_context *ctx, unsigned int inst)
-+{
-+	return dce_audio_create(ctx, inst,
-+			&audio_regs[inst], &audio_shift, &audio_mask);
-+}
-+
-+static struct timing_generator *dce80_timing_generator_create(
-+		struct dc_context *ctx,
-+		uint32_t instance,
-+		const struct dce110_timing_generator_offsets *offsets)
-+{
-+	struct dce110_timing_generator *tg110 =
-+		kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
-+
-+	if (!tg110)
-+		return NULL;
-+
-+	dce80_timing_generator_construct(tg110, ctx, instance, offsets);
-+	return &tg110->base;
-+}
-+
-+static struct output_pixel_processor *dce80_opp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce110_opp *opp =
-+		kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
-+
-+	if (!opp)
-+		return NULL;
-+
-+	dce110_opp_construct(opp,
-+			     ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
-+	return &opp->base;
-+}
-+
-+static struct stream_encoder *dce80_stream_encoder_create(
-+	enum engine_id eng_id,
-+	struct dc_context *ctx)
-+{
-+	struct dce110_stream_encoder *enc110 =
-+		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
-+					&stream_enc_regs[eng_id],
-+					&se_shift, &se_mask);
-+	return &enc110->base;
-+}
-+
-+#define SRII(reg_name, block, id)\
-+	.reg_name[id] = mm ## block ## id ## _ ## reg_name
-+
-+static const struct dce_hwseq_registers hwseq_reg = {
-+		HWSEQ_DCE8_REG_LIST()
-+};
-+
-+static const struct dce_hwseq_shift hwseq_shift = {
-+		HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct dce_hwseq_mask hwseq_mask = {
-+		HWSEQ_DCE8_MASK_SH_LIST(_MASK)
-+};
-+
-+static struct dce_hwseq *dce80_hwseq_create(
-+	struct dc_context *ctx)
-+{
-+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
-+
-+	if (hws) {
-+		hws->ctx = ctx;
-+		hws->regs = &hwseq_reg;
-+		hws->shifts = &hwseq_shift;
-+		hws->masks = &hwseq_mask;
-+	}
-+	return hws;
-+}
-+
-+static const struct resource_create_funcs res_create_funcs = {
-+	.read_dce_straps = read_dce_straps,
-+	.create_audio = create_audio,
-+	.create_stream_encoder = dce80_stream_encoder_create,
-+	.create_hwseq = dce80_hwseq_create,
-+};
-+
-+#define mi_inst_regs(id) { \
-+	MI_DCE8_REG_LIST(id), \
-+	.MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
-+}
-+static const struct dce_mem_input_registers mi_regs[] = {
-+		mi_inst_regs(0),
-+		mi_inst_regs(1),
-+		mi_inst_regs(2),
-+		mi_inst_regs(3),
-+		mi_inst_regs(4),
-+		mi_inst_regs(5),
-+};
-+
-+static const struct dce_mem_input_shift mi_shifts = {
-+		MI_DCE8_MASK_SH_LIST(__SHIFT),
-+		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
-+};
-+
-+static const struct dce_mem_input_mask mi_masks = {
-+		MI_DCE8_MASK_SH_LIST(_MASK),
-+		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
-+};
-+
-+static struct mem_input *dce80_mem_input_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
-+					       GFP_KERNEL);
-+
-+	if (!dce_mi) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
-+	dce_mi->wa.single_head_rdreq_dmif_limit = 2;
-+	return &dce_mi->base;
-+}
-+
-+static void dce80_transform_destroy(struct transform **xfm)
-+{
-+	kfree(TO_DCE_TRANSFORM(*xfm));
-+	*xfm = NULL;
-+}
-+
-+static struct transform *dce80_transform_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dce_transform *transform =
-+		kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
-+
-+	if (!transform)
-+		return NULL;
-+
-+	dce_transform_construct(transform, ctx, inst,
-+				&xfm_regs[inst], &xfm_shift, &xfm_mask);
-+	transform->prescaler_on = false;
-+	return &transform->base;
-+}
-+
-+static const struct encoder_feature_support link_enc_feature = {
-+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
-+		.max_hdmi_pixel_clock = 297000,
-+		.flags.bits.IS_HBR2_CAPABLE = true,
-+		.flags.bits.IS_TPS3_CAPABLE = true,
-+		.flags.bits.IS_YCBCR_CAPABLE = true
-+};
-+
-+struct link_encoder *dce80_link_encoder_create(
-+	const struct encoder_init_data *enc_init_data)
-+{
-+	struct dce110_link_encoder *enc110 =
-+		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	dce110_link_encoder_construct(enc110,
-+				      enc_init_data,
-+				      &link_enc_feature,
-+				      &link_enc_regs[enc_init_data->transmitter],
-+				      &link_enc_aux_regs[enc_init_data->channel - 1],
-+				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
-+	return &enc110->base;
-+}
-+
-+struct clock_source *dce80_clock_source_create(
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id id,
-+	const struct dce110_clk_src_regs *regs,
-+	bool dp_clk_src)
-+{
-+	struct dce110_clk_src *clk_src =
-+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
-+
-+	if (!clk_src)
-+		return NULL;
-+
-+	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
-+			regs, &cs_shift, &cs_mask)) {
-+		clk_src->base.dp_clk_src = dp_clk_src;
-+		return &clk_src->base;
-+	}
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
-+void dce80_clock_source_destroy(struct clock_source **clk_src)
-+{
-+	kfree(TO_DCE110_CLK_SRC(*clk_src));
-+	*clk_src = NULL;
-+}
-+
-+static struct input_pixel_processor *dce80_ipp_create(
-+	struct dc_context *ctx, uint32_t inst)
-+{
-+	struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
-+
-+	if (!ipp) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dce_ipp_construct(ipp, ctx, inst,
-+			&ipp_regs[inst], &ipp_shift, &ipp_mask);
-+	return &ipp->base;
-+}
-+
-+static void destruct(struct dce110_resource_pool *pool)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < pool->base.pipe_count; i++) {
-+		if (pool->base.opps[i] != NULL)
-+			dce110_opp_destroy(&pool->base.opps[i]);
-+
-+		if (pool->base.transforms[i] != NULL)
-+			dce80_transform_destroy(&pool->base.transforms[i]);
-+
-+		if (pool->base.ipps[i] != NULL)
-+			dce_ipp_destroy(&pool->base.ipps[i]);
-+
-+		if (pool->base.mis[i] != NULL) {
-+			kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
-+			pool->base.mis[i] = NULL;
-+		}
-+
-+		if (pool->base.timing_generators[i] != NULL)	{
-+			kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
-+			pool->base.timing_generators[i] = NULL;
-+		}
-+	}
-+
-+	for (i = 0; i < pool->base.stream_enc_count; i++) {
-+		if (pool->base.stream_enc[i] != NULL)
-+			kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
-+	}
-+
-+	for (i = 0; i < pool->base.clk_src_count; i++) {
-+		if (pool->base.clock_sources[i] != NULL) {
-+			dce80_clock_source_destroy(&pool->base.clock_sources[i]);
-+		}
-+	}
-+
-+	if (pool->base.dp_clock_source != NULL)
-+		dce80_clock_source_destroy(&pool->base.dp_clock_source);
-+
-+	for (i = 0; i < pool->base.audio_count; i++)	{
-+		if (pool->base.audios[i] != NULL) {
-+			dce_aud_destroy(&pool->base.audios[i]);
-+		}
-+	}
-+
-+	if (pool->base.display_clock != NULL)
-+		dce_disp_clk_destroy(&pool->base.display_clock);
-+
-+	if (pool->base.irqs != NULL) {
-+		dal_irq_service_destroy(&pool->base.irqs);
-+	}
-+}
-+
-+static enum dc_status build_mapped_resource(
-+		const struct dc *dc,
-+		struct dc_state *context,
-+		struct dc_stream_state *stream)
-+{
-+	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
-+
-+	if (!pipe_ctx)
-+		return DC_ERROR_UNEXPECTED;
-+
-+	dce110_resource_build_pipe_hw_param(pipe_ctx);
-+
-+	resource_build_info_frame(pipe_ctx);
-+
-+	return DC_OK;
-+}
-+
-+bool dce80_validate_bandwidth(
-+	struct dc *dc,
-+	struct dc_state *context)
-+{
-+	/* TODO implement when needed but for now hardcode max value*/
-+	context->bw.dce.dispclk_khz = 681000;
-+	context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
-+
-+	return true;
-+}
-+
-+static bool dce80_validate_surface_sets(
-+		struct dc_state *context)
-+{
-+	int i;
-+
-+	for (i = 0; i < context->stream_count; i++) {
-+		if (context->stream_status[i].plane_count == 0)
-+			continue;
-+
-+		if (context->stream_status[i].plane_count > 1)
-+			return false;
-+
-+		if (context->stream_status[i].plane_states[0]->format
-+				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
-+			return false;
-+	}
-+
-+	return true;
-+}
-+
-+enum dc_status dce80_validate_global(
-+		struct dc *dc,
-+		struct dc_state *context)
-+{
-+	if (!dce80_validate_surface_sets(context))
-+		return DC_FAIL_SURFACE_VALIDATE;
-+
-+	return DC_OK;
-+}
-+
-+enum dc_status dce80_validate_guaranteed(
-+		struct dc *dc,
-+		struct dc_stream_state *dc_stream,
-+		struct dc_state *context)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+
-+	context->streams[0] = dc_stream;
-+	dc_stream_retain(context->streams[0]);
-+	context->stream_count++;
-+
-+	result = resource_map_pool_resources(dc, context, dc_stream);
-+
-+	if (result == DC_OK)
-+		result = resource_map_clock_resources(dc, context, dc_stream);
-+
-+	if (result == DC_OK)
-+		result = build_mapped_resource(dc, context, dc_stream);
-+
-+	if (result == DC_OK) {
-+		validate_guaranteed_copy_streams(
-+				context, dc->caps.max_streams);
-+		result = resource_build_scaling_params_for_context(dc, context);
-+	}
-+
-+	if (result == DC_OK)
-+		result = dce80_validate_bandwidth(dc, context);
-+
-+	return result;
-+}
-+
-+static void dce80_destroy_resource_pool(struct resource_pool **pool)
-+{
-+	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
-+
-+	destruct(dce110_pool);
-+	kfree(dce110_pool);
-+	*pool = NULL;
-+}
-+
-+static const struct resource_funcs dce80_res_pool_funcs = {
-+	.destroy = dce80_destroy_resource_pool,
-+	.link_enc_create = dce80_link_encoder_create,
-+	.validate_guaranteed = dce80_validate_guaranteed,
-+	.validate_bandwidth = dce80_validate_bandwidth,
-+	.validate_plane = dce100_validate_plane,
-+	.add_stream_to_ctx = dce100_add_stream_to_ctx,
-+	.validate_global = dce80_validate_global
-+};
-+
-+static bool dce80_construct(
-+	uint8_t num_virtual_links,
-+	struct dc *dc,
-+	struct dce110_resource_pool *pool)
-+{
-+	unsigned int i;
-+	struct dc_context *ctx = dc->ctx;
-+	struct dc_firmware_info info;
-+	struct dc_bios *bp;
-+	struct dm_pp_static_clock_info static_clk_info = {0};
-+
-+	ctx->dc_bios->regs = &bios_regs;
-+
-+	pool->base.res_cap = &res_cap;
-+	pool->base.funcs = &dce80_res_pool_funcs;
-+
-+
-+	/*************************************************
-+	 *  Resource + asic cap harcoding                *
-+	 *************************************************/
-+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
-+	pool->base.pipe_count = res_cap.num_timing_generator;
-+	dc->caps.max_downscale_ratio = 200;
-+	dc->caps.i2c_speed_in_khz = 40;
-+	dc->caps.max_cursor_size = 128;
-+
-+	/*************************************************
-+	 *  Create resources                             *
-+	 *************************************************/
-+
-+	bp = ctx->dc_bios;
-+
-+	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
-+		info.external_clock_source_frequency_for_dp != 0) {
-+		pool->base.dp_clock_source =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
-+
-+		pool->base.clock_sources[0] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
-+		pool->base.clock_sources[1] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
-+		pool->base.clock_sources[2] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
-+		pool->base.clk_src_count = 3;
-+
-+	} else {
-+		pool->base.dp_clock_source =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
-+
-+		pool->base.clock_sources[0] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
-+		pool->base.clock_sources[1] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
-+		pool->base.clk_src_count = 2;
-+	}
-+
-+	if (pool->base.dp_clock_source == NULL) {
-+		dm_error("DC: failed to create dp clock source!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->base.clk_src_count; i++) {
-+		if (pool->base.clock_sources[i] == NULL) {
-+			dm_error("DC: failed to create clock sources!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto res_create_fail;
-+		}
-+	}
-+
-+	pool->base.display_clock = dce_disp_clk_create(ctx,
-+			&disp_clk_regs,
-+			&disp_clk_shift,
-+			&disp_clk_mask);
-+	if (pool->base.display_clock == NULL) {
-+		dm_error("DC: failed to create display clock!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+
-+	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
-+		pool->base.display_clock->max_clks_state =
-+					static_clk_info.max_clocks_state;
-+
-+	{
-+		struct irq_service_init_data init_data;
-+		init_data.ctx = dc->ctx;
-+		pool->base.irqs = dal_irq_service_dce80_create(&init_data);
-+		if (!pool->base.irqs)
-+			goto res_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->base.pipe_count; i++) {
-+		pool->base.timing_generators[i] = dce80_timing_generator_create(
-+				ctx, i, &dce80_tg_offsets[i]);
-+		if (pool->base.timing_generators[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create tg!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.mis[i] = dce80_mem_input_create(ctx, i);
-+		if (pool->base.mis[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create memory input!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.ipps[i] = dce80_ipp_create(ctx, i);
-+		if (pool->base.ipps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create input pixel processor!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.transforms[i] = dce80_transform_create(ctx, i);
-+		if (pool->base.transforms[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create transform!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.opps[i] = dce80_opp_create(ctx, i);
-+		if (pool->base.opps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create output pixel processor!\n");
-+			goto res_create_fail;
-+		}
-+	}
-+
-+	dc->caps.max_planes =  pool->base.pipe_count;
-+
-+	if (!resource_construct(num_virtual_links, dc, &pool->base,
-+			&res_create_funcs))
-+		goto res_create_fail;
-+
-+	/* Create hardware sequencer */
-+	dce80_hw_sequencer_construct(dc);
-+
-+	return true;
-+
-+res_create_fail:
-+	destruct(pool);
-+	return false;
-+}
-+
-+struct resource_pool *dce80_create_resource_pool(
-+	uint8_t num_virtual_links,
-+	struct dc *dc)
-+{
-+	struct dce110_resource_pool *pool =
-+		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
-+
-+	if (!pool)
-+		return NULL;
-+
-+	if (dce80_construct(num_virtual_links, dc, pool))
-+		return &pool->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
-+static bool dce81_construct(
-+	uint8_t num_virtual_links,
-+	struct dc *dc,
-+	struct dce110_resource_pool *pool)
-+{
-+	unsigned int i;
-+	struct dc_context *ctx = dc->ctx;
-+	struct dc_firmware_info info;
-+	struct dc_bios *bp;
-+	struct dm_pp_static_clock_info static_clk_info = {0};
-+
-+	ctx->dc_bios->regs = &bios_regs;
-+
-+	pool->base.res_cap = &res_cap_81;
-+	pool->base.funcs = &dce80_res_pool_funcs;
-+
-+
-+	/*************************************************
-+	 *  Resource + asic cap harcoding                *
-+	 *************************************************/
-+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
-+	pool->base.pipe_count = res_cap_81.num_timing_generator;
-+	dc->caps.max_downscale_ratio = 200;
-+	dc->caps.i2c_speed_in_khz = 40;
-+	dc->caps.max_cursor_size = 128;
-+	dc->caps.is_apu = true;
-+
-+	/*************************************************
-+	 *  Create resources                             *
-+	 *************************************************/
-+
-+	bp = ctx->dc_bios;
-+
-+	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
-+		info.external_clock_source_frequency_for_dp != 0) {
-+		pool->base.dp_clock_source =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
-+
-+		pool->base.clock_sources[0] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
-+		pool->base.clock_sources[1] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
-+		pool->base.clock_sources[2] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
-+		pool->base.clk_src_count = 3;
-+
-+	} else {
-+		pool->base.dp_clock_source =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
-+
-+		pool->base.clock_sources[0] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
-+		pool->base.clock_sources[1] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
-+		pool->base.clk_src_count = 2;
-+	}
-+
-+	if (pool->base.dp_clock_source == NULL) {
-+		dm_error("DC: failed to create dp clock source!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->base.clk_src_count; i++) {
-+		if (pool->base.clock_sources[i] == NULL) {
-+			dm_error("DC: failed to create clock sources!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto res_create_fail;
-+		}
-+	}
-+
-+	pool->base.display_clock = dce_disp_clk_create(ctx,
-+			&disp_clk_regs,
-+			&disp_clk_shift,
-+			&disp_clk_mask);
-+	if (pool->base.display_clock == NULL) {
-+		dm_error("DC: failed to create display clock!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+
-+	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
-+		pool->base.display_clock->max_clks_state =
-+					static_clk_info.max_clocks_state;
-+
-+	{
-+		struct irq_service_init_data init_data;
-+		init_data.ctx = dc->ctx;
-+		pool->base.irqs = dal_irq_service_dce80_create(&init_data);
-+		if (!pool->base.irqs)
-+			goto res_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->base.pipe_count; i++) {
-+		pool->base.timing_generators[i] = dce80_timing_generator_create(
-+				ctx, i, &dce80_tg_offsets[i]);
-+		if (pool->base.timing_generators[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create tg!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.mis[i] = dce80_mem_input_create(ctx, i);
-+		if (pool->base.mis[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create memory input!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.ipps[i] = dce80_ipp_create(ctx, i);
-+		if (pool->base.ipps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create input pixel processor!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.transforms[i] = dce80_transform_create(ctx, i);
-+		if (pool->base.transforms[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create transform!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.opps[i] = dce80_opp_create(ctx, i);
-+		if (pool->base.opps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create output pixel processor!\n");
-+			goto res_create_fail;
-+		}
-+	}
-+
-+	dc->caps.max_planes =  pool->base.pipe_count;
-+
-+	if (!resource_construct(num_virtual_links, dc, &pool->base,
-+			&res_create_funcs))
-+		goto res_create_fail;
-+
-+	/* Create hardware sequencer */
-+	dce80_hw_sequencer_construct(dc);
-+
-+	return true;
-+
-+res_create_fail:
-+	destruct(pool);
-+	return false;
-+}
-+
-+struct resource_pool *dce81_create_resource_pool(
-+	uint8_t num_virtual_links,
-+	struct dc *dc)
-+{
-+	struct dce110_resource_pool *pool =
-+		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
-+
-+	if (!pool)
-+		return NULL;
-+
-+	if (dce81_construct(num_virtual_links, dc, pool))
-+		return &pool->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
-+static bool dce83_construct(
-+	uint8_t num_virtual_links,
-+	struct dc *dc,
-+	struct dce110_resource_pool *pool)
-+{
-+	unsigned int i;
-+	struct dc_context *ctx = dc->ctx;
-+	struct dc_firmware_info info;
-+	struct dc_bios *bp;
-+	struct dm_pp_static_clock_info static_clk_info = {0};
-+
-+	ctx->dc_bios->regs = &bios_regs;
-+
-+	pool->base.res_cap = &res_cap_83;
-+	pool->base.funcs = &dce80_res_pool_funcs;
-+
-+
-+	/*************************************************
-+	 *  Resource + asic cap harcoding                *
-+	 *************************************************/
-+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
-+	pool->base.pipe_count = res_cap_83.num_timing_generator;
-+	dc->caps.max_downscale_ratio = 200;
-+	dc->caps.i2c_speed_in_khz = 40;
-+	dc->caps.max_cursor_size = 128;
-+	dc->caps.is_apu = true;
-+
-+	/*************************************************
-+	 *  Create resources                             *
-+	 *************************************************/
-+
-+	bp = ctx->dc_bios;
-+
-+	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
-+		info.external_clock_source_frequency_for_dp != 0) {
-+		pool->base.dp_clock_source =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
-+
-+		pool->base.clock_sources[0] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
-+		pool->base.clock_sources[1] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
-+		pool->base.clk_src_count = 2;
-+
-+	} else {
-+		pool->base.dp_clock_source =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
-+
-+		pool->base.clock_sources[0] =
-+				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
-+		pool->base.clk_src_count = 1;
-+	}
-+
-+	if (pool->base.dp_clock_source == NULL) {
-+		dm_error("DC: failed to create dp clock source!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->base.clk_src_count; i++) {
-+		if (pool->base.clock_sources[i] == NULL) {
-+			dm_error("DC: failed to create clock sources!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto res_create_fail;
-+		}
-+	}
-+
-+	pool->base.display_clock = dce_disp_clk_create(ctx,
-+			&disp_clk_regs,
-+			&disp_clk_shift,
-+			&disp_clk_mask);
-+	if (pool->base.display_clock == NULL) {
-+		dm_error("DC: failed to create display clock!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto res_create_fail;
-+	}
-+
-+
-+	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
-+		pool->base.display_clock->max_clks_state =
-+					static_clk_info.max_clocks_state;
-+
-+	{
-+		struct irq_service_init_data init_data;
-+		init_data.ctx = dc->ctx;
-+		pool->base.irqs = dal_irq_service_dce80_create(&init_data);
-+		if (!pool->base.irqs)
-+			goto res_create_fail;
-+	}
-+
-+	for (i = 0; i < pool->base.pipe_count; i++) {
-+		pool->base.timing_generators[i] = dce80_timing_generator_create(
-+				ctx, i, &dce80_tg_offsets[i]);
-+		if (pool->base.timing_generators[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create tg!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.mis[i] = dce80_mem_input_create(ctx, i);
-+		if (pool->base.mis[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create memory input!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.ipps[i] = dce80_ipp_create(ctx, i);
-+		if (pool->base.ipps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create input pixel processor!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.transforms[i] = dce80_transform_create(ctx, i);
-+		if (pool->base.transforms[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create transform!\n");
-+			goto res_create_fail;
-+		}
-+
-+		pool->base.opps[i] = dce80_opp_create(ctx, i);
-+		if (pool->base.opps[i] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create output pixel processor!\n");
-+			goto res_create_fail;
-+		}
-+	}
-+
-+	dc->caps.max_planes =  pool->base.pipe_count;
-+
-+	if (!resource_construct(num_virtual_links, dc, &pool->base,
-+			&res_create_funcs))
-+		goto res_create_fail;
-+
-+	/* Create hardware sequencer */
-+	dce80_hw_sequencer_construct(dc);
-+
-+	return true;
-+
-+res_create_fail:
-+	destruct(pool);
-+	return false;
-+}
-+
-+struct resource_pool *dce83_create_resource_pool(
-+	uint8_t num_virtual_links,
-+	struct dc *dc)
-+{
-+	struct dce110_resource_pool *pool =
-+		kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
-+
-+	if (!pool)
-+		return NULL;
-+
-+	if (dce83_construct(num_virtual_links, dc, pool))
-+		return &pool->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h.0130~	2017-12-14 06:39:58.414903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h	2017-12-14 06:39:58.414903567 +0100
-@@ -0,0 +1,47 @@
-+/*
-+* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_RESOURCE_DCE80_H__
-+#define __DC_RESOURCE_DCE80_H__
-+
-+#include "core_types.h"
-+
-+struct dc;
-+struct resource_pool;
-+
-+struct resource_pool *dce80_create_resource_pool(
-+	uint8_t num_virtual_links,
-+	struct dc *dc);
-+
-+struct resource_pool *dce81_create_resource_pool(
-+	uint8_t num_virtual_links,
-+	struct dc *dc);
-+
-+struct resource_pool *dce83_create_resource_pool(
-+	uint8_t num_virtual_links,
-+	struct dc *dc);
-+
-+#endif /* __DC_RESOURCE_DCE80_H__ */
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c.0130~	2017-12-14 06:39:58.414903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c	2017-12-14 06:39:58.414903567 +0100
-@@ -0,0 +1,239 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/* include DCE8 register header files */
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#include "dc_types.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/logger_interface.h"
-+#include "../dce110/dce110_timing_generator.h"
-+#include "dce80_timing_generator.h"
-+
-+#include "timing_generator.h"
-+
-+enum black_color_format {
-+	BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,	/* used as index in array */
-+	BLACK_COLOR_FORMAT_RGB_LIMITED,
-+	BLACK_COLOR_FORMAT_YUV_TV,
-+	BLACK_COLOR_FORMAT_YUV_CV,
-+	BLACK_COLOR_FORMAT_YUV_SUPER_AA,
-+
-+	BLACK_COLOR_FORMAT_COUNT
-+};
-+
-+static const struct dce110_timing_generator_offsets reg_offsets[] = {
-+{
-+	.crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+},
-+{
-+	.crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
-+	.dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
-+}
-+};
-+
-+#define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
-+
-+#define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
-+#define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
-+
-+#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
-+#define DCP_REG(reg) (reg + tg110->offsets.dcp)
-+#define DMIF_REG(reg) (reg + tg110->offsets.dmif)
-+
-+void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
-+{
-+	uint64_t pix_dur;
-+	uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
-+					+ DCE110TG_FROM_TG(tg)->offsets.dmif;
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	if (pix_clk_khz == 0)
-+		return;
-+
-+	pix_dur = 1000000000 / pix_clk_khz;
-+
-+	set_reg_field_value(
-+		value,
-+		pix_dur,
-+		DPG_PIPE_ARBITRATION_CONTROL1,
-+		PIXEL_DURATION);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+}
-+
-+static void program_timing(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing,
-+	bool use_vbios)
-+{
-+	if (!use_vbios)
-+		program_pix_dur(tg, timing->pix_clk_khz);
-+
-+	dce110_tg_program_timing(tg, timing, use_vbios);
-+}
-+
-+static const struct timing_generator_funcs dce80_tg_funcs = {
-+		.validate_timing = dce110_tg_validate_timing,
-+		.program_timing = program_timing,
-+		.enable_crtc = dce110_timing_generator_enable_crtc,
-+		.disable_crtc = dce110_timing_generator_disable_crtc,
-+		.is_counter_moving = dce110_timing_generator_is_counter_moving,
-+		.get_position = dce110_timing_generator_get_position,
-+		.get_frame_count = dce110_timing_generator_get_vblank_counter,
-+		.get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
-+		.set_early_control = dce110_timing_generator_set_early_control,
-+		.wait_for_state = dce110_tg_wait_for_state,
-+		.set_blank = dce110_tg_set_blank,
-+		.is_blanked = dce110_tg_is_blanked,
-+		.set_colors = dce110_tg_set_colors,
-+		.set_overscan_blank_color =
-+				dce110_timing_generator_set_overscan_color_black,
-+		.set_blank_color = dce110_timing_generator_program_blank_color,
-+		.disable_vga = dce110_timing_generator_disable_vga,
-+		.did_triggered_reset_occur =
-+				dce110_timing_generator_did_triggered_reset_occur,
-+		.setup_global_swap_lock =
-+				dce110_timing_generator_setup_global_swap_lock,
-+		.enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
-+		.disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
-+		.tear_down_global_swap_lock =
-+				dce110_timing_generator_tear_down_global_swap_lock,
-+		.set_drr = dce110_timing_generator_set_drr,
-+		.set_static_screen_control =
-+			dce110_timing_generator_set_static_screen_control,
-+		.set_test_pattern = dce110_timing_generator_set_test_pattern,
-+		.arm_vert_intr = dce110_arm_vert_intr,
-+
-+		/* DCE8.0 overrides */
-+		.enable_advanced_request =
-+				dce80_timing_generator_enable_advanced_request,
-+};
-+
-+void dce80_timing_generator_construct(
-+	struct dce110_timing_generator *tg110,
-+	struct dc_context *ctx,
-+	uint32_t instance,
-+	const struct dce110_timing_generator_offsets *offsets)
-+{
-+	tg110->controller_id = CONTROLLER_ID_D0 + instance;
-+	tg110->base.inst = instance;
-+	tg110->offsets = *offsets;
-+	tg110->derived_offsets = reg_offsets[instance];
-+
-+	tg110->base.funcs = &dce80_tg_funcs;
-+
-+	tg110->base.ctx = ctx;
-+	tg110->base.bp = ctx->dc_bios;
-+
-+	tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
-+	tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
-+
-+	tg110->min_h_blank = 56;
-+	tg110->min_h_front_porch = 4;
-+	tg110->min_h_back_porch = 4;
-+}
-+
-+void dce80_timing_generator_enable_advanced_request(
-+	struct timing_generator *tg,
-+	bool enable,
-+	const struct dc_crtc_timing *timing)
-+{
-+	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-+	uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
-+	uint32_t value = dm_read_reg(tg->ctx, addr);
-+
-+	if (enable) {
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_LEGACY_REQUESTOR_EN);
-+	} else {
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_LEGACY_REQUESTOR_EN);
-+	}
-+
-+	if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
-+		set_reg_field_value(
-+			value,
-+			3,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_ADVANCED_START_LINE_POSITION);
-+		set_reg_field_value(
-+			value,
-+			0,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_PREFETCH_EN);
-+	} else {
-+		set_reg_field_value(
-+			value,
-+			4,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_ADVANCED_START_LINE_POSITION);
-+		set_reg_field_value(
-+			value,
-+			1,
-+			CRTC_START_LINE_CONTROL,
-+			CRTC_PREFETCH_EN);
-+	}
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		CRTC_START_LINE_CONTROL,
-+		CRTC_PROGRESSIVE_START_LINE_EARLY);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		CRTC_START_LINE_CONTROL,
-+		CRTC_INTERLACE_START_LINE_EARLY);
-+
-+	dm_write_reg(tg->ctx, addr, value);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h.0130~	2017-12-14 06:39:58.415903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.h	2017-12-14 06:39:58.415903567 +0100
-@@ -0,0 +1,45 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_TIMING_GENERATOR_DCE80_H__
-+#define __DC_TIMING_GENERATOR_DCE80_H__
-+
-+#include "timing_generator.h"
-+#include "../include/grph_object_id.h"
-+
-+/* DCE8.0 implementation inherits from DCE11.0 */
-+void dce80_timing_generator_construct(
-+	struct dce110_timing_generator *tg,
-+	struct dc_context *ctx,
-+	uint32_t instance,
-+	const struct dce110_timing_generator_offsets *offsets);
-+
-+/******** HW programming ************/
-+void dce80_timing_generator_enable_advanced_request(
-+	struct timing_generator *tg,
-+	bool enable,
-+	const struct dc_crtc_timing *timing);
-+
-+#endif /* __DC_TIMING_GENERATOR_DCE80_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/Makefile.0130~	2017-12-14 06:39:58.415903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce80/Makefile	2017-12-14 06:39:58.415903567 +0100
-@@ -0,0 +1,13 @@
-+#
-+# Makefile for the 'controller' sub-component of DAL.
-+# It provides the control and status of HW CRTC block.
-+
-+DCE80 = dce80_timing_generator.o dce80_compressor.o dce80_hw_sequencer.o \
-+	dce80_resource.o
-+
-+AMD_DAL_DCE80 = $(addprefix $(AMDDALPATH)/dc/dce80/,$(DCE80))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_DCE80)
-+
-+
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c.0130~	2017-12-14 06:39:58.415903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c	2017-12-14 06:39:58.415903567 +0100
-@@ -0,0 +1,485 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dce_abm.h"
-+#include "dm_services.h"
-+#include "reg_helper.h"
-+#include "fixed32_32.h"
-+#include "dc.h"
-+
-+#include "atom.h"
-+
-+
-+#define TO_DCE_ABM(abm)\
-+	container_of(abm, struct dce_abm, base)
-+
-+#define REG(reg) \
-+	(abm_dce->regs->reg)
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	abm_dce->abm_shift->field_name, abm_dce->abm_mask->field_name
-+
-+#define CTX \
-+	abm_dce->base.ctx
-+
-+#define MCP_ABM_LEVEL_SET 0x65
-+#define MCP_ABM_PIPE_SET 0x66
-+#define MCP_BL_SET 0x67
-+
-+#define MCP_DISABLE_ABM_IMMEDIATELY 255
-+
-+struct abm_backlight_registers {
-+	unsigned int BL_PWM_CNTL;
-+	unsigned int BL_PWM_CNTL2;
-+	unsigned int BL_PWM_PERIOD_CNTL;
-+	unsigned int LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV;
-+};
-+
-+/* registers setting needs to be save and restored used at InitBacklight */
-+static struct abm_backlight_registers stored_backlight_registers = {0};
-+
-+
-+static unsigned int get_current_backlight_16_bit(struct dce_abm *abm_dce)
-+{
-+	uint64_t current_backlight;
-+	uint32_t round_result;
-+	uint32_t pwm_period_cntl, bl_period, bl_int_count;
-+	uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en;
-+	uint32_t bl_period_mask, bl_pwm_mask;
-+
-+	pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
-+	REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
-+	REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
-+
-+	bl_pwm_cntl = REG_READ(BL_PWM_CNTL);
-+	REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));
-+	REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
-+
-+	if (bl_int_count == 0)
-+		bl_int_count = 16;
-+
-+	bl_period_mask = (1 << bl_int_count) - 1;
-+	bl_period &= bl_period_mask;
-+
-+	bl_pwm_mask = bl_period_mask << (16 - bl_int_count);
-+
-+	if (fractional_duty_cycle_en == 0)
-+		bl_pwm &= bl_pwm_mask;
-+	else
-+		bl_pwm &= 0xFFFF;
-+
-+	current_backlight = bl_pwm << (1 + bl_int_count);
-+
-+	if (bl_period == 0)
-+		bl_period = 0xFFFF;
-+
-+	current_backlight = div_u64(current_backlight, bl_period);
-+	current_backlight = (current_backlight + 1) >> 1;
-+
-+	current_backlight = (uint64_t)(current_backlight) * bl_period;
-+
-+	round_result = (uint32_t)(current_backlight & 0xFFFFFFFF);
-+
-+	round_result = (round_result >> (bl_int_count-1)) & 1;
-+
-+	current_backlight >>= bl_int_count;
-+	current_backlight += round_result;
-+
-+	return (uint32_t)(current_backlight);
-+}
-+
-+static void driver_set_backlight_level(struct dce_abm *abm_dce, uint32_t level)
-+{
-+	uint32_t backlight_24bit;
-+	uint32_t backlight_17bit;
-+	uint32_t backlight_16bit;
-+	uint32_t masked_pwm_period;
-+	uint8_t rounding_bit;
-+	uint8_t bit_count;
-+	uint64_t active_duty_cycle;
-+	uint32_t pwm_period_bitcnt;
-+
-+	/*
-+	 * 1. Convert 8-bit value to 17 bit U1.16 format
-+	 * (1 integer, 16 fractional bits)
-+	 */
-+
-+	/* 1.1 multiply 8 bit value by 0x10101 to get a 24 bit value,
-+	 * effectively multiplying value by 256/255
-+	 * eg. for a level of 0xEF, backlight_24bit = 0xEF * 0x10101 = 0xEFEFEF
-+	 */
-+	backlight_24bit = level * 0x10101;
-+
-+	/* 1.2 The upper 16 bits of the 24 bit value is the fraction, lower 8
-+	 * used for rounding, take most significant bit of fraction for
-+	 * rounding, e.g. for 0xEFEFEF, rounding bit is 1
-+	 */
-+	rounding_bit = (backlight_24bit >> 7) & 1;
-+
-+	/* 1.3 Add the upper 16 bits of the 24 bit value with the rounding bit
-+	 * resulting in a 17 bit value e.g. 0xEFF0 = (0xEFEFEF >> 8) + 1
-+	 */
-+	backlight_17bit = (backlight_24bit >> 8) + rounding_bit;
-+
-+	/*
-+	 * 2. Find  16 bit backlight active duty cycle, where 0 <= backlight
-+	 * active duty cycle <= backlight period
-+	 */
-+
-+	/* 2.1 Apply bitmask for backlight period value based on value of BITCNT
-+	 */
-+	REG_GET_2(BL_PWM_PERIOD_CNTL,
-+			BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt,
-+			BL_PWM_PERIOD, &masked_pwm_period);
-+
-+	if (pwm_period_bitcnt == 0)
-+		bit_count = 16;
-+	else
-+		bit_count = pwm_period_bitcnt;
-+
-+	/* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */
-+	masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1);
-+
-+	/* 2.2 Calculate integer active duty cycle required upper 16 bits
-+	 * contain integer component, lower 16 bits contain fractional component
-+	 * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24
-+	 */
-+	active_duty_cycle = backlight_17bit * masked_pwm_period;
-+
-+	/* 2.3 Calculate 16 bit active duty cycle from integer and fractional
-+	 * components shift by bitCount then mask 16 bits and add rounding bit
-+	 * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0
-+	 */
-+	backlight_16bit = active_duty_cycle >> bit_count;
-+	backlight_16bit &= 0xFFFF;
-+	backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1;
-+
-+	/*
-+	 * 3. Program register with updated value
-+	 */
-+
-+	/* 3.1 Lock group 2 backlight registers */
-+
-+	REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK,
-+			BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1,
-+			BL_PWM_GRP1_REG_LOCK, 1);
-+
-+	// 3.2 Write new active duty cycle
-+	REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit);
-+
-+	/* 3.3 Unlock group 2 backlight registers */
-+	REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
-+			BL_PWM_GRP1_REG_LOCK, 0);
-+
-+	/* 5.4.4 Wait for pending bit to be cleared */
-+	REG_WAIT(BL_PWM_GRP1_REG_LOCK,
-+			BL_PWM_GRP1_REG_UPDATE_PENDING, 0,
-+			1, 10000);
-+}
-+
-+static void dmcu_set_backlight_level(
-+	struct dce_abm *abm_dce,
-+	uint32_t level,
-+	uint32_t frame_ramp,
-+	uint32_t controller_id)
-+{
-+	unsigned int backlight_16_bit = (level * 0x10101) >> 8;
-+	unsigned int backlight_17_bit = backlight_16_bit +
-+				(((backlight_16_bit & 0x80) >> 7) & 1);
-+	uint32_t rampingBoundary = 0xFFFF;
-+	uint32_t s2;
-+
-+	/* set ramping boundary */
-+	REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary);
-+
-+	/* setDMCUParam_Pipe */
-+	REG_UPDATE_2(MASTER_COMM_CMD_REG,
-+			MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET,
-+			MASTER_COMM_CMD_REG_BYTE1, controller_id);
-+
-+	/* notifyDMCUMsg */
-+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-+
-+	/* waitDMCUReadyForCmd */
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
-+			0, 1, 80000);
-+
-+	/* setDMCUParam_BL */
-+	REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_17_bit);
-+
-+	/* write ramp */
-+	if (controller_id == 0)
-+		frame_ramp = 0;
-+	REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp);
-+
-+	/* setDMCUParam_Cmd */
-+	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET);
-+
-+	/* notifyDMCUMsg */
-+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-+
-+	/* UpdateRequestedBacklightLevel */
-+	s2 = REG_READ(BIOS_SCRATCH_2);
-+
-+	s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
-+	level &= (ATOM_S2_CURRENT_BL_LEVEL_MASK >>
-+				ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
-+	s2 |= (level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
-+
-+	REG_WRITE(BIOS_SCRATCH_2, s2);
-+}
-+
-+static void dce_abm_init(struct abm *abm)
-+{
-+	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
-+	unsigned int backlight = get_current_backlight_16_bit(abm_dce);
-+
-+	REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103);
-+	REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);
-+	REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103);
-+	REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101);
-+	REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101);
-+
-+	REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0,
-+			ABM1_HG_NUM_OF_BINS_SEL, 0,
-+			ABM1_HG_VMAX_SEL, 1,
-+			ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0);
-+
-+	REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0,
-+			ABM1_IPCSC_COEFF_SEL_R, 2,
-+			ABM1_IPCSC_COEFF_SEL_G, 4,
-+			ABM1_IPCSC_COEFF_SEL_B, 2);
-+
-+	REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL,
-+			BL1_PWM_CURRENT_ABM_LEVEL, backlight);
-+
-+	REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL,
-+			BL1_PWM_TARGET_ABM_LEVEL, backlight);
-+
-+	REG_UPDATE(BL1_PWM_USER_LEVEL,
-+			BL1_PWM_USER_LEVEL, backlight);
-+
-+	REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES,
-+			ABM1_LS_MIN_PIXEL_VALUE_THRES, 0,
-+			ABM1_LS_MAX_PIXEL_VALUE_THRES, 1000);
-+
-+	REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0,
-+			ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, 1,
-+			ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, 1,
-+			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1);
-+}
-+
-+static unsigned int dce_abm_get_current_backlight_8_bit(struct abm *abm)
-+{
-+	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
-+	unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
-+
-+	return (backlight >> 8);
-+}
-+
-+static bool dce_abm_set_level(struct abm *abm, uint32_t level)
-+{
-+	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
-+
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
-+			1, 80000);
-+
-+	/* setDMCUParam_ABMLevel */
-+	REG_UPDATE_2(MASTER_COMM_CMD_REG,
-+			MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
-+			MASTER_COMM_CMD_REG_BYTE2, level);
-+
-+	/* notifyDMCUMsg */
-+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-+
-+	return true;
-+}
-+
-+static bool dce_abm_immediate_disable(struct abm *abm)
-+{
-+	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
-+
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
-+			1, 80000);
-+
-+	/* setDMCUParam_ABMLevel */
-+	REG_UPDATE_2(MASTER_COMM_CMD_REG,
-+			MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
-+			MASTER_COMM_CMD_REG_BYTE2, MCP_DISABLE_ABM_IMMEDIATELY);
-+
-+	/* notifyDMCUMsg */
-+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-+
-+	return true;
-+}
-+
-+static bool dce_abm_init_backlight(struct abm *abm)
-+{
-+	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
-+	uint32_t value;
-+
-+	/* It must not be 0, so we have to restore them
-+	 * Bios bug w/a - period resets to zero,
-+	 * restoring to cache values which is always correct
-+	 */
-+	REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
-+	if (value == 0 || value == 1) {
-+		if (stored_backlight_registers.BL_PWM_CNTL != 0) {
-+			REG_WRITE(BL_PWM_CNTL,
-+				stored_backlight_registers.BL_PWM_CNTL);
-+			REG_WRITE(BL_PWM_CNTL2,
-+				stored_backlight_registers.BL_PWM_CNTL2);
-+			REG_WRITE(BL_PWM_PERIOD_CNTL,
-+				stored_backlight_registers.BL_PWM_PERIOD_CNTL);
-+			REG_UPDATE(LVTMA_PWRSEQ_REF_DIV,
-+				BL_PWM_REF_DIV,
-+				stored_backlight_registers.
-+				LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
-+		} else {
-+			/* TODO: Note: This should not really happen since VBIOS
-+			 * should have initialized PWM registers on boot.
-+			 */
-+			REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
-+			REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
-+		}
-+	} else {
-+		stored_backlight_registers.BL_PWM_CNTL =
-+				REG_READ(BL_PWM_CNTL);
-+		stored_backlight_registers.BL_PWM_CNTL2 =
-+				REG_READ(BL_PWM_CNTL2);
-+		stored_backlight_registers.BL_PWM_PERIOD_CNTL =
-+				REG_READ(BL_PWM_PERIOD_CNTL);
-+
-+		REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
-+				&stored_backlight_registers.
-+				LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
-+	}
-+
-+	/* Have driver take backlight control
-+	 * TakeBacklightControl(true)
-+	 */
-+	value = REG_READ(BIOS_SCRATCH_2);
-+	value |= ATOM_S2_VRI_BRIGHT_ENABLE;
-+	REG_WRITE(BIOS_SCRATCH_2, value);
-+
-+	/* Enable the backlight output */
-+	REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
-+
-+	/* Unlock group 2 backlight registers */
-+	REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
-+			BL_PWM_GRP1_REG_LOCK, 0);
-+
-+	return true;
-+}
-+
-+static bool is_dmcu_initialized(struct abm *abm)
-+{
-+	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
-+	unsigned int dmcu_uc_reset;
-+
-+	REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset);
-+
-+	return !dmcu_uc_reset;
-+}
-+
-+static bool dce_abm_set_backlight_level(
-+		struct abm *abm,
-+		unsigned int backlight_level,
-+		unsigned int frame_ramp,
-+		unsigned int controller_id)
-+{
-+	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
-+
-+	dm_logger_write(abm->ctx->logger, LOG_BACKLIGHT,
-+			"New Backlight level: %d (0x%X)\n",
-+			backlight_level, backlight_level);
-+
-+	/* If DMCU is in reset state, DMCU is uninitialized */
-+	if (is_dmcu_initialized(abm))
-+		dmcu_set_backlight_level(abm_dce,
-+				backlight_level,
-+				frame_ramp,
-+				controller_id);
-+	else
-+		driver_set_backlight_level(abm_dce, backlight_level);
-+
-+	return true;
-+}
-+
-+static const struct abm_funcs dce_funcs = {
-+	.abm_init = dce_abm_init,
-+	.set_abm_level = dce_abm_set_level,
-+	.init_backlight = dce_abm_init_backlight,
-+	.set_backlight_level = dce_abm_set_backlight_level,
-+	.get_current_backlight_8_bit = dce_abm_get_current_backlight_8_bit,
-+	.set_abm_immediate_disable = dce_abm_immediate_disable,
-+	.is_dmcu_initialized = is_dmcu_initialized
-+};
-+
-+static void dce_abm_construct(
-+	struct dce_abm *abm_dce,
-+	struct dc_context *ctx,
-+	const struct dce_abm_registers *regs,
-+	const struct dce_abm_shift *abm_shift,
-+	const struct dce_abm_mask *abm_mask)
-+{
-+	struct abm *base = &abm_dce->base;
-+
-+	base->ctx = ctx;
-+	base->funcs = &dce_funcs;
-+
-+	abm_dce->regs = regs;
-+	abm_dce->abm_shift = abm_shift;
-+	abm_dce->abm_mask = abm_mask;
-+}
-+
-+struct abm *dce_abm_create(
-+	struct dc_context *ctx,
-+	const struct dce_abm_registers *regs,
-+	const struct dce_abm_shift *abm_shift,
-+	const struct dce_abm_mask *abm_mask)
-+{
-+	struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
-+
-+	if (abm_dce == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dce_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask);
-+
-+	abm_dce->base.funcs = &dce_funcs;
-+
-+	return &abm_dce->base;
-+}
-+
-+void dce_abm_destroy(struct abm **abm)
-+{
-+	struct dce_abm *abm_dce = TO_DCE_ABM(*abm);
-+
-+	kfree(abm_dce);
-+	*abm = NULL;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h.0130~	2017-12-14 06:39:58.415903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h	2017-12-14 06:39:58.415903567 +0100
-@@ -0,0 +1,228 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+
-+#ifndef _DCE_ABM_H_
-+#define _DCE_ABM_H_
-+
-+#include "abm.h"
-+
-+#define ABM_COMMON_REG_LIST_DCE_BASE() \
-+	SR(BL_PWM_PERIOD_CNTL), \
-+	SR(BL_PWM_CNTL), \
-+	SR(BL_PWM_CNTL2), \
-+	SR(BL_PWM_GRP1_REG_LOCK), \
-+	SR(LVTMA_PWRSEQ_REF_DIV), \
-+	SR(MASTER_COMM_CNTL_REG), \
-+	SR(MASTER_COMM_CMD_REG), \
-+	SR(MASTER_COMM_DATA_REG1), \
-+	SR(DMCU_STATUS)
-+
-+#define ABM_DCE110_COMMON_REG_LIST() \
-+	ABM_COMMON_REG_LIST_DCE_BASE(), \
-+	SR(DC_ABM1_HG_SAMPLE_RATE), \
-+	SR(DC_ABM1_LS_SAMPLE_RATE), \
-+	SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
-+	SR(DC_ABM1_HG_MISC_CTRL), \
-+	SR(DC_ABM1_IPCSC_COEFF_SEL), \
-+	SR(BL1_PWM_CURRENT_ABM_LEVEL), \
-+	SR(BL1_PWM_TARGET_ABM_LEVEL), \
-+	SR(BL1_PWM_USER_LEVEL), \
-+	SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
-+	SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
-+	SR(BIOS_SCRATCH_2)
-+
-+#define ABM_DCN10_REG_LIST(id)\
-+	ABM_COMMON_REG_LIST_DCE_BASE(), \
-+	SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
-+	SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
-+	SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
-+	SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
-+	SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
-+	SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
-+	SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
-+	SRI(BL1_PWM_USER_LEVEL, ABM, id), \
-+	SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
-+	SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
-+	NBIO_SR(BIOS_SCRATCH_2)
-+
-+#define ABM_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+#define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
-+	ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
-+	ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
-+	ABM_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
-+	ABM_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
-+	ABM_SF(BL_PWM_CNTL, BL_PWM_EN, mask_sh), \
-+	ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
-+	ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
-+	ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh), \
-+	ABM_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
-+	ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
-+	ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
-+	ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
-+	ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh), \
-+	ABM_SF(DMCU_STATUS, UC_IN_RESET, mask_sh)
-+
-+#define ABM_MASK_SH_LIST_DCE110(mask_sh) \
-+	ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
-+	ABM_SF(DC_ABM1_HG_MISC_CTRL, \
-+			ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
-+	ABM_SF(DC_ABM1_HG_MISC_CTRL, \
-+			ABM1_HG_VMAX_SEL, mask_sh), \
-+	ABM_SF(DC_ABM1_HG_MISC_CTRL, \
-+			ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
-+	ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
-+			ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
-+	ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
-+			ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
-+	ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
-+			ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
-+	ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \
-+			BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
-+	ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \
-+			BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
-+	ABM_SF(BL1_PWM_USER_LEVEL, \
-+			BL1_PWM_USER_LEVEL, mask_sh), \
-+	ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
-+			ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
-+	ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
-+			ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
-+	ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
-+			ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
-+	ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
-+			ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
-+	ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
-+			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
-+
-+#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
-+	ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
-+	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
-+			ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
-+	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
-+			ABM1_HG_VMAX_SEL, mask_sh), \
-+	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
-+			ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
-+	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
-+			ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
-+	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
-+			ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
-+	ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
-+			ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
-+	ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
-+			BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
-+	ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
-+			BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
-+	ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
-+			BL1_PWM_USER_LEVEL, mask_sh), \
-+	ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
-+			ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
-+	ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
-+			ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
-+	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
-+			ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
-+	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
-+			ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
-+	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
-+			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
-+
-+#define ABM_REG_FIELD_LIST(type) \
-+	type ABM1_HG_NUM_OF_BINS_SEL; \
-+	type ABM1_HG_VMAX_SEL; \
-+	type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \
-+	type ABM1_IPCSC_COEFF_SEL_R; \
-+	type ABM1_IPCSC_COEFF_SEL_G; \
-+	type ABM1_IPCSC_COEFF_SEL_B; \
-+	type BL1_PWM_CURRENT_ABM_LEVEL; \
-+	type BL1_PWM_TARGET_ABM_LEVEL; \
-+	type BL1_PWM_USER_LEVEL; \
-+	type ABM1_LS_MIN_PIXEL_VALUE_THRES; \
-+	type ABM1_LS_MAX_PIXEL_VALUE_THRES; \
-+	type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \
-+	type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \
-+	type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \
-+	type BL_PWM_PERIOD; \
-+	type BL_PWM_PERIOD_BITCNT; \
-+	type BL_ACTIVE_INT_FRAC_CNT; \
-+	type BL_PWM_FRACTIONAL_EN; \
-+	type MASTER_COMM_INTERRUPT; \
-+	type MASTER_COMM_CMD_REG_BYTE0; \
-+	type MASTER_COMM_CMD_REG_BYTE1; \
-+	type MASTER_COMM_CMD_REG_BYTE2; \
-+	type BL_PWM_REF_DIV; \
-+	type BL_PWM_EN; \
-+	type UC_IN_RESET; \
-+	type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
-+	type BL_PWM_GRP1_REG_LOCK; \
-+	type BL_PWM_GRP1_REG_UPDATE_PENDING
-+
-+struct dce_abm_shift {
-+	ABM_REG_FIELD_LIST(uint8_t);
-+};
-+
-+struct dce_abm_mask {
-+	ABM_REG_FIELD_LIST(uint32_t);
-+};
-+
-+struct dce_abm_registers {
-+	uint32_t BL_PWM_PERIOD_CNTL;
-+	uint32_t BL_PWM_CNTL;
-+	uint32_t BL_PWM_CNTL2;
-+	uint32_t LVTMA_PWRSEQ_REF_DIV;
-+	uint32_t DC_ABM1_HG_SAMPLE_RATE;
-+	uint32_t DC_ABM1_LS_SAMPLE_RATE;
-+	uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;
-+	uint32_t DC_ABM1_HG_MISC_CTRL;
-+	uint32_t DC_ABM1_IPCSC_COEFF_SEL;
-+	uint32_t BL1_PWM_CURRENT_ABM_LEVEL;
-+	uint32_t BL1_PWM_TARGET_ABM_LEVEL;
-+	uint32_t BL1_PWM_USER_LEVEL;
-+	uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
-+	uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
-+	uint32_t MASTER_COMM_CNTL_REG;
-+	uint32_t MASTER_COMM_CMD_REG;
-+	uint32_t MASTER_COMM_DATA_REG1;
-+	uint32_t BIOS_SCRATCH_2;
-+	uint32_t DMCU_STATUS;
-+	uint32_t BL_PWM_GRP1_REG_LOCK;
-+};
-+
-+struct dce_abm {
-+	struct abm base;
-+	const struct dce_abm_registers *regs;
-+	const struct dce_abm_shift *abm_shift;
-+	const struct dce_abm_mask *abm_mask;
-+};
-+
-+struct abm *dce_abm_create(
-+	struct dc_context *ctx,
-+	const struct dce_abm_registers *regs,
-+	const struct dce_abm_shift *abm_shift,
-+	const struct dce_abm_mask *abm_mask);
-+
-+void dce_abm_destroy(struct abm **abm);
-+
-+#endif /* _DCE_ABM_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c.0130~	2017-12-14 06:39:58.415903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c	2017-12-14 06:39:58.415903567 +0100
-@@ -0,0 +1,945 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "reg_helper.h"
-+#include "dce_audio.h"
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#define DCE_AUD(audio)\
-+	container_of(audio, struct dce_audio, base)
-+
-+#define CTX \
-+	aud->base.ctx
-+#define REG(reg)\
-+	(aud->regs->reg)
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	aud->shifts->field_name, aud->masks->field_name
-+
-+#define IX_REG(reg)\
-+	ix ## reg
-+
-+#define AZ_REG_READ(reg_name) \
-+		read_indirect_azalia_reg(audio, IX_REG(reg_name))
-+
-+#define AZ_REG_WRITE(reg_name, value) \
-+		write_indirect_azalia_reg(audio, IX_REG(reg_name), value)
-+
-+static void write_indirect_azalia_reg(struct audio *audio,
-+	uint32_t reg_index,
-+	uint32_t reg_data)
-+{
-+	struct dce_audio *aud = DCE_AUD(audio);
-+
-+	/* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
-+	REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
-+			AZALIA_ENDPOINT_REG_INDEX, reg_index);
-+
-+	/* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
-+	REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
-+			AZALIA_ENDPOINT_REG_DATA, reg_data);
-+
-+	dm_logger_write(CTX->logger, LOG_HW_AUDIO,
-+		"AUDIO:write_indirect_azalia_reg: index: %u  data: %u\n",
-+		reg_index, reg_data);
-+}
-+
-+static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index)
-+{
-+	struct dce_audio *aud = DCE_AUD(audio);
-+
-+	uint32_t value = 0;
-+
-+	/* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
-+	REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
-+			AZALIA_ENDPOINT_REG_INDEX, reg_index);
-+
-+	/* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
-+	value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
-+
-+	dm_logger_write(CTX->logger, LOG_HW_AUDIO,
-+		"AUDIO:read_indirect_azalia_reg: index: %u  data: %u\n",
-+		reg_index, value);
-+
-+	return value;
-+}
-+
-+static bool is_audio_format_supported(
-+	const struct audio_info *audio_info,
-+	enum audio_format_code audio_format_code,
-+	uint32_t *format_index)
-+{
-+	uint32_t index;
-+	uint32_t max_channe_index = 0;
-+	bool found = false;
-+
-+	if (audio_info == NULL)
-+		return found;
-+
-+	/* pass through whole array */
-+	for (index = 0; index < audio_info->mode_count; index++) {
-+		if (audio_info->modes[index].format_code == audio_format_code) {
-+			if (found) {
-+				/* format has multiply entries, choose one with
-+				 *  highst number of channels */
-+				if (audio_info->modes[index].channel_count >
-+		audio_info->modes[max_channe_index].channel_count) {
-+					max_channe_index = index;
-+				}
-+			} else {
-+				/* format found, save it's index */
-+				found = true;
-+				max_channe_index = index;
-+			}
-+		}
-+	}
-+
-+	/* return index */
-+	if (found && format_index != NULL)
-+		*format_index = max_channe_index;
-+
-+	return found;
-+}
-+
-+/*For HDMI, calculate if specified sample rates can fit into a given timing */
-+static void check_audio_bandwidth_hdmi(
-+	const struct audio_crtc_info *crtc_info,
-+	uint32_t channel_count,
-+	union audio_sample_rates *sample_rates)
-+{
-+	uint32_t samples;
-+	uint32_t  h_blank;
-+	bool limit_freq_to_48_khz = false;
-+	bool limit_freq_to_88_2_khz = false;
-+	bool limit_freq_to_96_khz = false;
-+	bool limit_freq_to_174_4_khz = false;
-+
-+	/* For two channels supported return whatever sink support,unmodified*/
-+	if (channel_count > 2) {
-+
-+		/* Based on HDMI spec 1.3 Table 7.5 */
-+		if ((crtc_info->requested_pixel_clock <= 27000) &&
-+		(crtc_info->v_active <= 576) &&
-+		!(crtc_info->interlaced) &&
-+		!(crtc_info->pixel_repetition == 2 ||
-+		crtc_info->pixel_repetition == 4)) {
-+			limit_freq_to_48_khz = true;
-+
-+		} else if ((crtc_info->requested_pixel_clock <= 27000) &&
-+				(crtc_info->v_active <= 576) &&
-+				(crtc_info->interlaced) &&
-+				(crtc_info->pixel_repetition == 2)) {
-+			limit_freq_to_88_2_khz = true;
-+
-+		} else if ((crtc_info->requested_pixel_clock <= 54000) &&
-+				(crtc_info->v_active <= 576) &&
-+				!(crtc_info->interlaced)) {
-+			limit_freq_to_174_4_khz = true;
-+		}
-+	}
-+
-+	/* Also do some calculation for the available Audio Bandwidth for the
-+	 * 8 ch (i.e. for the Layout 1 => ch > 2)
-+	 */
-+	h_blank = crtc_info->h_total - crtc_info->h_active;
-+
-+	if (crtc_info->pixel_repetition)
-+		h_blank *= crtc_info->pixel_repetition;
-+
-+	/*based on HDMI spec 1.3 Table 7.5 */
-+	h_blank -= 58;
-+	/*for Control Period */
-+	h_blank -= 16;
-+
-+	samples = h_blank * 10;
-+	/* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
-+	 * of Audio samples per line multiplied by 10 - Layout 1)
-+	 */
-+	samples /= 32;
-+	samples *= crtc_info->v_active;
-+	/*Number of samples multiplied by 10, per second */
-+	samples *= crtc_info->refresh_rate;
-+	/*Number of Audio samples per second */
-+	samples /= 10;
-+
-+	/* @todo do it after deep color is implemented
-+	 * 8xx - deep color bandwidth scaling
-+	 * Extra bandwidth is avaliable in deep color b/c link runs faster than
-+	 * pixel rate. This has the effect of allowing more tmds characters to
-+	 * be transmitted during blank
-+	 */
-+
-+	switch (crtc_info->color_depth) {
-+	case COLOR_DEPTH_888:
-+		samples *= 4;
-+		break;
-+	case COLOR_DEPTH_101010:
-+		samples *= 5;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		samples *= 6;
-+		break;
-+	default:
-+		samples *= 4;
-+		break;
-+	}
-+
-+	samples /= 4;
-+
-+	/*check limitation*/
-+	if (samples < 88200)
-+		limit_freq_to_48_khz = true;
-+	else if (samples < 96000)
-+		limit_freq_to_88_2_khz = true;
-+	else if (samples < 176400)
-+		limit_freq_to_96_khz = true;
-+	else if (samples < 192000)
-+		limit_freq_to_174_4_khz = true;
-+
-+	if (sample_rates != NULL) {
-+		/* limit frequencies */
-+		if (limit_freq_to_174_4_khz)
-+			sample_rates->rate.RATE_192 = 0;
-+
-+		if (limit_freq_to_96_khz) {
-+			sample_rates->rate.RATE_192 = 0;
-+			sample_rates->rate.RATE_176_4 = 0;
-+		}
-+		if (limit_freq_to_88_2_khz) {
-+			sample_rates->rate.RATE_192 = 0;
-+			sample_rates->rate.RATE_176_4 = 0;
-+			sample_rates->rate.RATE_96 = 0;
-+		}
-+		if (limit_freq_to_48_khz) {
-+			sample_rates->rate.RATE_192 = 0;
-+			sample_rates->rate.RATE_176_4 = 0;
-+			sample_rates->rate.RATE_96 = 0;
-+			sample_rates->rate.RATE_88_2 = 0;
-+		}
-+	}
-+}
-+
-+/*For DP SST, calculate if specified sample rates can fit into a given timing */
-+static void check_audio_bandwidth_dpsst(
-+	const struct audio_crtc_info *crtc_info,
-+	uint32_t channel_count,
-+	union audio_sample_rates *sample_rates)
-+{
-+	/* do nothing */
-+}
-+
-+/*For DP MST, calculate if specified sample rates can fit into a given timing */
-+static void check_audio_bandwidth_dpmst(
-+	const struct audio_crtc_info *crtc_info,
-+	uint32_t channel_count,
-+	union audio_sample_rates *sample_rates)
-+{
-+	/* do nothing  */
-+}
-+
-+static void check_audio_bandwidth(
-+	const struct audio_crtc_info *crtc_info,
-+	uint32_t channel_count,
-+	enum signal_type signal,
-+	union audio_sample_rates *sample_rates)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		check_audio_bandwidth_hdmi(
-+			crtc_info, channel_count, sample_rates);
-+		break;
-+	case SIGNAL_TYPE_EDP:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+		check_audio_bandwidth_dpsst(
-+			crtc_info, channel_count, sample_rates);
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		check_audio_bandwidth_dpmst(
-+			crtc_info, channel_count, sample_rates);
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+/* expose/not expose HBR capability to Audio driver */
-+static void set_high_bit_rate_capable(
-+	struct audio *audio,
-+	bool capable)
-+{
-+	uint32_t value = 0;
-+
-+	/* set high bit rate audio capable*/
-+	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
-+
-+	set_reg_field_value(value, capable,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
-+		HBR_CAPABLE);
-+
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value);
-+}
-+
-+/* set video latency in in ms/2+1 */
-+static void set_video_latency(
-+	struct audio *audio,
-+	int latency_in_ms)
-+{
-+	uint32_t value = 0;
-+
-+	if ((latency_in_ms < 0) || (latency_in_ms > 255))
-+		return;
-+
-+	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
-+
-+	set_reg_field_value(value, latency_in_ms,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		VIDEO_LIPSYNC);
-+
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		value);
-+}
-+
-+/* set audio latency in in ms/2+1 */
-+static void set_audio_latency(
-+	struct audio *audio,
-+	int latency_in_ms)
-+{
-+	uint32_t value = 0;
-+
-+	if (latency_in_ms < 0)
-+		latency_in_ms = 0;
-+
-+	if (latency_in_ms > 255)
-+		latency_in_ms = 255;
-+
-+	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
-+
-+	set_reg_field_value(value, latency_in_ms,
-+		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		AUDIO_LIPSYNC);
-+
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
-+		value);
-+}
-+
-+void dce_aud_az_enable(struct audio *audio)
-+{
-+	struct dce_audio *aud = DCE_AUD(audio);
-+	uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
-+
-+	set_reg_field_value(value, 1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+			CLOCK_GATING_DISABLE);
-+		set_reg_field_value(value, 1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+			AUDIO_ENABLED);
-+
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
-+	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
-+
-+	dm_logger_write(CTX->logger, LOG_HW_AUDIO,
-+			"\n\t========= AUDIO:dce_aud_az_enable: index: %u  data: 0x%x\n",
-+			audio->inst, value);
-+}
-+
-+void dce_aud_az_disable(struct audio *audio)
-+{
-+	uint32_t value;
-+	struct dce_audio *aud = DCE_AUD(audio);
-+
-+	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
-+
-+	set_reg_field_value(value, 0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+		AUDIO_ENABLED);
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
-+
-+	set_reg_field_value(value, 0,
-+			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+			CLOCK_GATING_DISABLE);
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
-+	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
-+	dm_logger_write(CTX->logger, LOG_HW_AUDIO,
-+			"\n\t========= AUDIO:dce_aud_az_disable: index: %u  data: 0x%x\n",
-+			audio->inst, value);
-+}
-+
-+void dce_aud_az_configure(
-+	struct audio *audio,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_info *audio_info)
-+{
-+	struct dce_audio *aud = DCE_AUD(audio);
-+
-+	uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
-+	uint32_t value;
-+	uint32_t field = 0;
-+	enum audio_format_code audio_format_code;
-+	uint32_t format_index;
-+	uint32_t index;
-+	bool is_ac3_supported = false;
-+	union audio_sample_rates sample_rate;
-+	uint32_t strlen = 0;
-+	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
-+	set_reg_field_value(value, 1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+			CLOCK_GATING_DISABLE);
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
-+
-+	/* Speaker Allocation */
-+	/*
-+	uint32_t value;
-+	uint32_t field = 0;*/
-+	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
-+
-+	set_reg_field_value(value,
-+		speakers,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		SPEAKER_ALLOCATION);
-+
-+	/* LFE_PLAYBACK_LEVEL = LFEPBL
-+	 * LFEPBL = 0 : Unknown or refer to other information
-+	 * LFEPBL = 1 : 0dB playback
-+	 * LFEPBL = 2 : +10dB playback
-+	 * LFE_BL = 3 : Reserved
-+	 */
-+	set_reg_field_value(value,
-+		0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		LFE_PLAYBACK_LEVEL);
-+	/* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only.
-+	 *  why are we writing to it?  DCE8 does not write this */
-+
-+
-+	set_reg_field_value(value,
-+		0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		HDMI_CONNECTION);
-+
-+	set_reg_field_value(value,
-+		0,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		DP_CONNECTION);
-+
-+	field = get_reg_field_value(value,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			EXTRA_CONNECTION_INFO);
-+
-+	field &= ~0x1;
-+
-+	set_reg_field_value(value,
-+		field,
-+		AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+		EXTRA_CONNECTION_INFO);
-+
-+	/* set audio for output signal */
-+	switch (signal) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		set_reg_field_value(value,
-+			1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			HDMI_CONNECTION);
-+
-+		break;
-+
-+	case SIGNAL_TYPE_EDP:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		set_reg_field_value(value,
-+			1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
-+			DP_CONNECTION);
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value);
-+
-+	/*  Audio Descriptors   */
-+	/* pass through all formats */
-+	for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
-+			format_index++) {
-+		audio_format_code =
-+			(AUDIO_FORMAT_CODE_FIRST + format_index);
-+
-+		/* those are unsupported, skip programming */
-+		if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
-+			audio_format_code == AUDIO_FORMAT_CODE_DST)
-+			continue;
-+
-+		value = 0;
-+
-+		/* check if supported */
-+		if (is_audio_format_supported(
-+				audio_info, audio_format_code, &index)) {
-+			const struct audio_mode *audio_mode =
-+					&audio_info->modes[index];
-+			union audio_sample_rates sample_rates =
-+					audio_mode->sample_rates;
-+			uint8_t byte2 = audio_mode->max_bit_rate;
-+
-+			/* adjust specific properties */
-+			switch (audio_format_code) {
-+			case AUDIO_FORMAT_CODE_LINEARPCM: {
-+				check_audio_bandwidth(
-+					crtc_info,
-+					audio_mode->channel_count,
-+					signal,
-+					&sample_rates);
-+
-+				byte2 = audio_mode->sample_size;
-+
-+				set_reg_field_value(value,
-+						sample_rates.all,
-+						AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+						SUPPORTED_FREQUENCIES_STEREO);
-+				}
-+				break;
-+			case AUDIO_FORMAT_CODE_AC3:
-+				is_ac3_supported = true;
-+				break;
-+			case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
-+			case AUDIO_FORMAT_CODE_DTS_HD:
-+			case AUDIO_FORMAT_CODE_MAT_MLP:
-+			case AUDIO_FORMAT_CODE_DST:
-+			case AUDIO_FORMAT_CODE_WMAPRO:
-+				byte2 = audio_mode->vendor_specific;
-+				break;
-+			default:
-+				break;
-+			}
-+
-+			/* fill audio format data */
-+			set_reg_field_value(value,
-+					audio_mode->channel_count - 1,
-+					AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+					MAX_CHANNELS);
-+
-+			set_reg_field_value(value,
-+					sample_rates.all,
-+					AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+					SUPPORTED_FREQUENCIES);
-+
-+			set_reg_field_value(value,
-+					byte2,
-+					AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
-+					DESCRIPTOR_BYTE_2);
-+		} /* if */
-+
-+		AZ_REG_WRITE(
-+				AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index,
-+				value);
-+	} /* for */
-+
-+	if (is_ac3_supported)
-+		/* todo: this reg global.  why program global register? */
-+		REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
-+				0x05);
-+
-+	/* check for 192khz/8-Ch support for HBR requirements */
-+	sample_rate.all = 0;
-+	sample_rate.rate.RATE_192 = 1;
-+
-+	check_audio_bandwidth(
-+		crtc_info,
-+		8,
-+		signal,
-+		&sample_rate);
-+
-+	set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192);
-+
-+	/* Audio and Video Lipsync */
-+	set_video_latency(audio, audio_info->video_latency);
-+	set_audio_latency(audio, audio_info->audio_latency);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->manufacture_id,
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+		MANUFACTURER_ID);
-+
-+	set_reg_field_value(value, audio_info->product_id,
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+		PRODUCT_ID);
-+
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
-+		value);
-+
-+	value = 0;
-+
-+	/*get display name string length */
-+	while (audio_info->display_name[strlen++] != '\0') {
-+		if (strlen >=
-+		MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
-+			break;
-+		}
-+	set_reg_field_value(value, strlen,
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
-+		SINK_DESCRIPTION_LEN);
-+
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
-+		value);
-+
-+	/*
-+	*write the port ID:
-+	*PORT_ID0 = display index
-+	*PORT_ID1 = 16bit BDF
-+	*(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
-+	*/
-+
-+	value = 0;
-+
-+	set_reg_field_value(value, audio_info->port_id[0],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
-+		PORT_ID0);
-+
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->port_id[1],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
-+		PORT_ID1);
-+
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value);
-+
-+	/*write the 18 char monitor string */
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[0],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION0);
-+
-+	set_reg_field_value(value, audio_info->display_name[1],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION1);
-+
-+	set_reg_field_value(value, audio_info->display_name[2],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION2);
-+
-+	set_reg_field_value(value, audio_info->display_name[3],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
-+		DESCRIPTION3);
-+
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[4],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION4);
-+
-+	set_reg_field_value(value, audio_info->display_name[5],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION5);
-+
-+	set_reg_field_value(value, audio_info->display_name[6],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION6);
-+
-+	set_reg_field_value(value, audio_info->display_name[7],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
-+		DESCRIPTION7);
-+
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[8],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION8);
-+
-+	set_reg_field_value(value, audio_info->display_name[9],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION9);
-+
-+	set_reg_field_value(value, audio_info->display_name[10],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION10);
-+
-+	set_reg_field_value(value, audio_info->display_name[11],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
-+		DESCRIPTION11);
-+
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[12],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION12);
-+
-+	set_reg_field_value(value, audio_info->display_name[13],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION13);
-+
-+	set_reg_field_value(value, audio_info->display_name[14],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION14);
-+
-+	set_reg_field_value(value, audio_info->display_name[15],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
-+		DESCRIPTION15);
-+
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value);
-+
-+	value = 0;
-+	set_reg_field_value(value, audio_info->display_name[16],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-+		DESCRIPTION16);
-+
-+	set_reg_field_value(value, audio_info->display_name[17],
-+		AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
-+		DESCRIPTION17);
-+
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value);
-+}
-+
-+/*
-+* todo: wall clk related functionality probably belong to clock_src.
-+*/
-+
-+/* search pixel clock value for Azalia HDMI Audio */
-+static void get_azalia_clock_info_hdmi(
-+	uint32_t crtc_pixel_clock_in_khz,
-+	uint32_t actual_pixel_clock_in_khz,
-+	struct azalia_clock_info *azalia_clock_info)
-+{
-+	/* audio_dto_phase= 24 * 10,000;
-+	 *   24MHz in [100Hz] units */
-+	azalia_clock_info->audio_dto_phase =
-+			24 * 10000;
-+
-+	/* audio_dto_module = PCLKFrequency * 10,000;
-+	 *  [khz] -> [100Hz] */
-+	azalia_clock_info->audio_dto_module =
-+			actual_pixel_clock_in_khz * 10;
-+}
-+
-+static void get_azalia_clock_info_dp(
-+	uint32_t requested_pixel_clock_in_khz,
-+	const struct audio_pll_info *pll_info,
-+	struct azalia_clock_info *azalia_clock_info)
-+{
-+	/* Reported dpDtoSourceClockInkhz value for
-+	 * DCE8 already adjusted for SS, do not need any
-+	 * adjustment here anymore
-+	 */
-+
-+	/*audio_dto_phase = 24 * 10,000;
-+	 * 24MHz in [100Hz] units */
-+	azalia_clock_info->audio_dto_phase = 24 * 10000;
-+
-+	/*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
-+	 *  [khz] ->[100Hz] */
-+	azalia_clock_info->audio_dto_module =
-+		pll_info->dp_dto_source_clock_in_khz * 10;
-+}
-+
-+void dce_aud_wall_dto_setup(
-+	struct audio *audio,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info)
-+{
-+	struct dce_audio *aud = DCE_AUD(audio);
-+
-+	struct azalia_clock_info clock_info = { 0 };
-+
-+	if (dc_is_hdmi_signal(signal)) {
-+		uint32_t src_sel;
-+
-+		/*DTO0 Programming goal:
-+		-generate 24MHz, 128*Fs from 24MHz
-+		-use DTO0 when an active HDMI port is connected
-+		(optionally a DP is connected) */
-+
-+		/* calculate DTO settings */
-+		get_azalia_clock_info_hdmi(
-+			crtc_info->requested_pixel_clock,
-+			crtc_info->calculated_pixel_clock,
-+			&clock_info);
-+
-+		dm_logger_write(audio->ctx->logger, LOG_HW_AUDIO,\
-+				"\n%s:Input::requested_pixel_clock = %d"\
-+				"calculated_pixel_clock =%d\n"\
-+				"audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
-+				crtc_info->requested_pixel_clock,\
-+				crtc_info->calculated_pixel_clock,\
-+				clock_info.audio_dto_module,\
-+				clock_info.audio_dto_phase);
-+
-+		/* On TN/SI, Program DTO source select and DTO select before
-+		programming DTO modulo and DTO phase. These bits must be
-+		programmed first, otherwise there will be no HDMI audio at boot
-+		up. This is a HW sequence change (different from old ASICs).
-+		Caution when changing this programming sequence.
-+
-+		HDMI enabled, using DTO0
-+		program master CRTC for DTO0 */
-+		src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
-+		REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
-+			DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
-+			DCCG_AUDIO_DTO_SEL, 0);
-+
-+		/* module */
-+		REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
-+			DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
-+
-+		/* phase */
-+		REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
-+			DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
-+	} else {
-+		/*DTO1 Programming goal:
-+		-generate 24MHz, 512*Fs, 128*Fs from 24MHz
-+		-default is to used DTO1, and switch to DTO0 when an audio
-+		master HDMI port is connected
-+		-use as default for DP
-+
-+		calculate DTO settings */
-+		get_azalia_clock_info_dp(
-+			crtc_info->requested_pixel_clock,
-+			pll_info,
-+			&clock_info);
-+
-+		/* Program DTO select before programming DTO modulo and DTO
-+		phase. default to use DTO1 */
-+
-+		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
-+				DCCG_AUDIO_DTO_SEL, 1);
-+
-+		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
-+			DCCG_AUDIO_DTO_SEL, 1);
-+			/* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
-+			 * Select 512fs for DP TODO: web register definition
-+			 * does not match register header file
-+			 * DCE11 version it's commented out while DCE8 it's set to 1
-+			*/
-+
-+		/* module */
-+		REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
-+				DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
-+
-+		/* phase */
-+		REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
-+				DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
-+
-+		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
-+				DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1);
-+
-+	}
-+}
-+
-+static bool dce_aud_endpoint_valid(struct audio *audio)
-+{
-+	uint32_t value;
-+	uint32_t port_connectivity;
-+
-+	value = AZ_REG_READ(
-+			AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
-+
-+	port_connectivity = get_reg_field_value(value,
-+			AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
-+			PORT_CONNECTIVITY);
-+
-+	return !(port_connectivity == 1);
-+}
-+
-+/* initialize HW state */
-+void dce_aud_hw_init(
-+		struct audio *audio)
-+{
-+	uint32_t value;
-+	struct dce_audio *aud = DCE_AUD(audio);
-+
-+	/* we only need to program the following registers once, so we only do
-+	it for the inst 0*/
-+	if (audio->inst != 0)
-+		return;
-+
-+	/* Suport R5 - 32khz
-+	 * Suport R6 - 44.1khz
-+	 * Suport R7 - 48khz
-+	 */
-+	/*disable clock gating before write to endpoint register*/
-+	value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
-+	set_reg_field_value(value, 1,
-+			AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
-+			CLOCK_GATING_DISABLE);
-+	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
-+	REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
-+			AUDIO_RATE_CAPABILITIES, 0x70);
-+
-+	/*Keep alive bit to verify HW block in BU. */
-+	REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
-+			CLKSTOP, 1,
-+			EPSS, 1);
-+}
-+
-+static const struct audio_funcs funcs = {
-+	.endpoint_valid = dce_aud_endpoint_valid,
-+	.hw_init = dce_aud_hw_init,
-+	.wall_dto_setup = dce_aud_wall_dto_setup,
-+	.az_enable = dce_aud_az_enable,
-+	.az_disable = dce_aud_az_disable,
-+	.az_configure = dce_aud_az_configure,
-+	.destroy = dce_aud_destroy,
-+};
-+
-+void dce_aud_destroy(struct audio **audio)
-+{
-+	struct dce_audio *aud = DCE_AUD(*audio);
-+
-+	kfree(aud);
-+	*audio = NULL;
-+}
-+
-+struct audio *dce_audio_create(
-+		struct dc_context *ctx,
-+		unsigned int inst,
-+		const struct dce_audio_registers *reg,
-+		const struct dce_audio_shift *shifts,
-+		const struct dce_aduio_mask *masks
-+		)
-+{
-+	struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
-+
-+	if (audio == NULL) {
-+		ASSERT_CRITICAL(audio);
-+		return NULL;
-+	}
-+
-+	audio->base.ctx = ctx;
-+	audio->base.inst = inst;
-+	audio->base.funcs = &funcs;
-+
-+	audio->regs = reg;
-+	audio->shifts = shifts;
-+	audio->masks = masks;
-+
-+	return &audio->base;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h.0130~	2017-12-14 06:39:58.415903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h	2017-12-14 06:39:58.415903567 +0100
-@@ -0,0 +1,148 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_AUDIO_DCE_110_H__
-+#define __DAL_AUDIO_DCE_110_H__
-+
-+#include "audio.h"
-+
-+#define AUD_COMMON_REG_LIST(id)\
-+	SRI(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZF0ENDPOINT, id),\
-+	SRI(AZALIA_F0_CODEC_ENDPOINT_DATA, AZF0ENDPOINT, id),\
-+	SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
-+	SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
-+	SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
-+	SR(DCCG_AUDIO_DTO_SOURCE),\
-+	SR(DCCG_AUDIO_DTO0_MODULE),\
-+	SR(DCCG_AUDIO_DTO0_PHASE),\
-+	SR(DCCG_AUDIO_DTO1_MODULE),\
-+	SR(DCCG_AUDIO_DTO1_PHASE)
-+
-+
-+ /* set field name */
-+#define SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+
-+#define AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)\
-+		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
-+		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
-+		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
-+		SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
-+		SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
-+		SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
-+		SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
-+		SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\
-+		SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\
-+		SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh)
-+
-+#define AUD_COMMON_MASK_SH_LIST(mask_sh)\
-+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh),\
-+		SF(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
-+		SF(AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh)
-+
-+
-+struct dce_audio_registers {
-+	uint32_t AZALIA_F0_CODEC_ENDPOINT_INDEX;
-+	uint32_t AZALIA_F0_CODEC_ENDPOINT_DATA;
-+
-+	uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS;
-+	uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES;
-+	uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES;
-+
-+	uint32_t DCCG_AUDIO_DTO_SOURCE;
-+	uint32_t DCCG_AUDIO_DTO0_MODULE;
-+	uint32_t DCCG_AUDIO_DTO0_PHASE;
-+	uint32_t DCCG_AUDIO_DTO1_MODULE;
-+	uint32_t DCCG_AUDIO_DTO1_PHASE;
-+
-+	uint32_t AUDIO_RATE_CAPABILITIES;
-+};
-+
-+struct dce_audio_shift {
-+	uint8_t AZALIA_ENDPOINT_REG_INDEX;
-+	uint8_t AZALIA_ENDPOINT_REG_DATA;
-+
-+	uint8_t AUDIO_RATE_CAPABILITIES;
-+	uint8_t CLKSTOP;
-+	uint8_t EPSS;
-+
-+	uint8_t DCCG_AUDIO_DTO0_SOURCE_SEL;
-+	uint8_t DCCG_AUDIO_DTO_SEL;
-+	uint8_t DCCG_AUDIO_DTO0_MODULE;
-+	uint8_t DCCG_AUDIO_DTO0_PHASE;
-+	uint8_t DCCG_AUDIO_DTO1_MODULE;
-+	uint8_t DCCG_AUDIO_DTO1_PHASE;
-+	uint8_t DCCG_AUDIO_DTO2_USE_512FBR_DTO;
-+};
-+
-+struct dce_aduio_mask {
-+	uint32_t AZALIA_ENDPOINT_REG_INDEX;
-+	uint32_t AZALIA_ENDPOINT_REG_DATA;
-+
-+	uint32_t AUDIO_RATE_CAPABILITIES;
-+	uint32_t CLKSTOP;
-+	uint32_t EPSS;
-+
-+	uint32_t DCCG_AUDIO_DTO0_SOURCE_SEL;
-+	uint32_t DCCG_AUDIO_DTO_SEL;
-+	uint32_t DCCG_AUDIO_DTO0_MODULE;
-+	uint32_t DCCG_AUDIO_DTO0_PHASE;
-+	uint32_t DCCG_AUDIO_DTO1_MODULE;
-+	uint32_t DCCG_AUDIO_DTO1_PHASE;
-+	uint32_t DCCG_AUDIO_DTO2_USE_512FBR_DTO;
-+};
-+
-+struct dce_audio {
-+	struct audio base;
-+	const struct dce_audio_registers *regs;
-+	const struct dce_audio_shift *shifts;
-+	const struct dce_aduio_mask *masks;
-+};
-+
-+struct audio *dce_audio_create(
-+		struct dc_context *ctx,
-+		unsigned int inst,
-+		const struct dce_audio_registers *reg,
-+		const struct dce_audio_shift *shifts,
-+		const struct dce_aduio_mask *masks);
-+
-+void dce_aud_destroy(struct audio **audio);
-+
-+void dce_aud_hw_init(struct audio *audio);
-+
-+void dce_aud_az_enable(struct audio *audio);
-+void dce_aud_az_disable(struct audio *audio);
-+
-+void dce_aud_az_configure(struct audio *audio,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_info *audio_info);
-+
-+void dce_aud_wall_dto_setup(struct audio *audio,
-+	enum signal_type signal,
-+	const struct audio_crtc_info *crtc_info,
-+	const struct audio_pll_info *pll_info);
-+
-+#endif   /*__DAL_AUDIO_DCE_110_H__*/
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c.0130~	2017-12-14 06:39:58.415903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c	2017-12-14 06:39:58.415903567 +0100
-@@ -0,0 +1,827 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dce_clocks.h"
-+#include "dm_services.h"
-+#include "reg_helper.h"
-+#include "fixed32_32.h"
-+#include "bios_parser_interface.h"
-+#include "dc.h"
-+#include "dce_abm.h"
-+#include "dmcu.h"
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+#include "dcn_calcs.h"
-+#endif
-+#include "core_types.h"
-+
-+
-+#define TO_DCE_CLOCKS(clocks)\
-+	container_of(clocks, struct dce_disp_clk, base)
-+
-+#define REG(reg) \
-+	(clk_dce->regs->reg)
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	clk_dce->clk_shift->field_name, clk_dce->clk_mask->field_name
-+
-+#define CTX \
-+	clk_dce->base.ctx
-+
-+/* Max clock values for each state indexed by "enum clocks_state": */
-+static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
-+/* ClocksStateInvalid - should not be used */
-+{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-+/* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
-+{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-+/* ClocksStateLow */
-+{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
-+/* ClocksStateNominal */
-+{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
-+/* ClocksStatePerformance */
-+{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
-+
-+static const struct state_dependent_clocks dce110_max_clks_by_state[] = {
-+/*ClocksStateInvalid - should not be used*/
-+{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-+/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-+{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
-+/*ClocksStateLow*/
-+{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
-+/*ClocksStateNominal*/
-+{ .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
-+/*ClocksStatePerformance*/
-+{ .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
-+
-+static const struct state_dependent_clocks dce112_max_clks_by_state[] = {
-+/*ClocksStateInvalid - should not be used*/
-+{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-+/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-+{ .display_clk_khz = 389189, .pixel_clk_khz = 346672 },
-+/*ClocksStateLow*/
-+{ .display_clk_khz = 459000, .pixel_clk_khz = 400000 },
-+/*ClocksStateNominal*/
-+{ .display_clk_khz = 667000, .pixel_clk_khz = 600000 },
-+/*ClocksStatePerformance*/
-+{ .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
-+
-+static const struct state_dependent_clocks dce120_max_clks_by_state[] = {
-+/*ClocksStateInvalid - should not be used*/
-+{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-+/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-+{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-+/*ClocksStateLow*/
-+{ .display_clk_khz = 460000, .pixel_clk_khz = 400000 },
-+/*ClocksStateNominal*/
-+{ .display_clk_khz = 670000, .pixel_clk_khz = 600000 },
-+/*ClocksStatePerformance*/
-+{ .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
-+
-+/* Starting point for each divider range.*/
-+enum dce_divider_range_start {
-+	DIVIDER_RANGE_01_START = 200, /* 2.00*/
-+	DIVIDER_RANGE_02_START = 1600, /* 16.00*/
-+	DIVIDER_RANGE_03_START = 3200, /* 32.00*/
-+	DIVIDER_RANGE_SCALE_FACTOR = 100 /* Results are scaled up by 100.*/
-+};
-+
-+/* Ranges for divider identifiers (Divider ID or DID)
-+ mmDENTIST_DISPCLK_CNTL.DENTIST_DISPCLK_WDIVIDER*/
-+enum dce_divider_id_register_setting {
-+	DIVIDER_RANGE_01_BASE_DIVIDER_ID = 0X08,
-+	DIVIDER_RANGE_02_BASE_DIVIDER_ID = 0X40,
-+	DIVIDER_RANGE_03_BASE_DIVIDER_ID = 0X60,
-+	DIVIDER_RANGE_MAX_DIVIDER_ID = 0X80
-+};
-+
-+/* Step size between each divider within a range.
-+ Incrementing the DENTIST_DISPCLK_WDIVIDER by one
-+ will increment the divider by this much.*/
-+enum dce_divider_range_step_size {
-+	DIVIDER_RANGE_01_STEP_SIZE = 25, /* 0.25*/
-+	DIVIDER_RANGE_02_STEP_SIZE = 50, /* 0.50*/
-+	DIVIDER_RANGE_03_STEP_SIZE = 100 /* 1.00 */
-+};
-+
-+static bool dce_divider_range_construct(
-+	struct dce_divider_range *div_range,
-+	int range_start,
-+	int range_step,
-+	int did_min,
-+	int did_max)
-+{
-+	div_range->div_range_start = range_start;
-+	div_range->div_range_step = range_step;
-+	div_range->did_min = did_min;
-+	div_range->did_max = did_max;
-+
-+	if (div_range->div_range_step == 0) {
-+		div_range->div_range_step = 1;
-+		/*div_range_step cannot be zero*/
-+		BREAK_TO_DEBUGGER();
-+	}
-+	/* Calculate this based on the other inputs.*/
-+	/* See DividerRange.h for explanation of */
-+	/* the relationship between divider id (DID) and a divider.*/
-+	/* Number of Divider IDs = (Maximum Divider ID - Minimum Divider ID)*/
-+	/* Maximum divider identified in this range =
-+	 * (Number of Divider IDs)*Step size between dividers
-+	 *  + The start of this range.*/
-+	div_range->div_range_end = (did_max - did_min) * range_step
-+		+ range_start;
-+	return true;
-+}
-+
-+static int dce_divider_range_calc_divider(
-+	struct dce_divider_range *div_range,
-+	int did)
-+{
-+	/* Is this DID within our range?*/
-+	if ((did < div_range->did_min) || (did >= div_range->did_max))
-+		return INVALID_DIVIDER;
-+
-+	return ((did - div_range->did_min) * div_range->div_range_step)
-+			+ div_range->div_range_start;
-+
-+}
-+
-+static int dce_divider_range_get_divider(
-+	struct dce_divider_range *div_range,
-+	int ranges_num,
-+	int did)
-+{
-+	int div = INVALID_DIVIDER;
-+	int i;
-+
-+	for (i = 0; i < ranges_num; i++) {
-+		/* Calculate divider with given divider ID*/
-+		div = dce_divider_range_calc_divider(&div_range[i], did);
-+		/* Found a valid return divider*/
-+		if (div != INVALID_DIVIDER)
-+			break;
-+	}
-+	return div;
-+}
-+
-+static int dce_clocks_get_dp_ref_freq(struct display_clock *clk)
-+{
-+	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
-+	int dprefclk_wdivider;
-+	int dprefclk_src_sel;
-+	int dp_ref_clk_khz = 600000;
-+	int target_div = INVALID_DIVIDER;
-+
-+	/* ASSERT DP Reference Clock source is from DFS*/
-+	REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
-+	ASSERT(dprefclk_src_sel == 0);
-+
-+	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently
-+	 * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
-+	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
-+
-+	/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
-+	target_div = dce_divider_range_get_divider(
-+			clk_dce->divider_ranges,
-+			DIVIDER_RANGE_MAX,
-+			dprefclk_wdivider);
-+
-+	if (target_div != INVALID_DIVIDER) {
-+		/* Calculate the current DFS clock, in kHz.*/
-+		dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR
-+			* clk_dce->dentist_vco_freq_khz) / target_div;
-+	}
-+
-+	/* SW will adjust DP REF Clock average value for all purposes
-+	 * (DP DTO / DP Audio DTO and DP GTC)
-+	 if clock is spread for all cases:
-+	 -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
-+	 calculations for DS_INCR/DS_MODULO (this is planned to be default case)
-+	 -if SS enabled on DP Ref clock and HW de-spreading enabled with HW
-+	 calculations (not planned to be used, but average clock should still
-+	 be valid)
-+	 -if SS enabled on DP Ref clock and HW de-spreading disabled
-+	 (should not be case with CIK) then SW should program all rates
-+	 generated according to average value (case as with previous ASICs)
-+	  */
-+	if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {
-+		struct fixed32_32 ss_percentage = dal_fixed32_32_div_int(
-+				dal_fixed32_32_from_fraction(
-+						clk_dce->dprefclk_ss_percentage,
-+						clk_dce->dprefclk_ss_divider), 200);
-+		struct fixed32_32 adj_dp_ref_clk_khz;
-+
-+		ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one,
-+								ss_percentage);
-+		adj_dp_ref_clk_khz =
-+			dal_fixed32_32_mul_int(
-+				ss_percentage,
-+				dp_ref_clk_khz);
-+		dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz);
-+	}
-+
-+	return dp_ref_clk_khz;
-+}
-+
-+/* TODO: This is DCN DPREFCLK: it could be program by DENTIST by VBIOS
-+ * or CLK0_CLK11 by SMU. For DCE120, it is wlays 600Mhz. Will re-visit
-+ * clock implementation
-+ */
-+static int dce_clocks_get_dp_ref_freq_wrkaround(struct display_clock *clk)
-+{
-+	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
-+	int dp_ref_clk_khz = 600000;
-+
-+	if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {
-+		struct fixed32_32 ss_percentage = dal_fixed32_32_div_int(
-+				dal_fixed32_32_from_fraction(
-+						clk_dce->dprefclk_ss_percentage,
-+						clk_dce->dprefclk_ss_divider), 200);
-+		struct fixed32_32 adj_dp_ref_clk_khz;
-+
-+		ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one,
-+								ss_percentage);
-+		adj_dp_ref_clk_khz =
-+			dal_fixed32_32_mul_int(
-+				ss_percentage,
-+				dp_ref_clk_khz);
-+		dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz);
-+	}
-+
-+	return dp_ref_clk_khz;
-+}
-+static enum dm_pp_clocks_state dce_get_required_clocks_state(
-+	struct display_clock *clk,
-+	struct state_dependent_clocks *req_clocks)
-+{
-+	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
-+	int i;
-+	enum dm_pp_clocks_state low_req_clk;
-+
-+	/* Iterate from highest supported to lowest valid state, and update
-+	 * lowest RequiredState with the lowest state that satisfies
-+	 * all required clocks
-+	 */
-+	for (i = clk->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
-+		if (req_clocks->display_clk_khz >
-+				clk_dce->max_clks_by_state[i].display_clk_khz
-+			|| req_clocks->pixel_clk_khz >
-+				clk_dce->max_clks_by_state[i].pixel_clk_khz)
-+			break;
-+
-+	low_req_clk = i + 1;
-+	if (low_req_clk > clk->max_clks_state) {
-+		dm_logger_write(clk->ctx->logger, LOG_WARNING,
-+				"%s: clocks unsupported", __func__);
-+		low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
-+	}
-+
-+	return low_req_clk;
-+}
-+
-+static bool dce_clock_set_min_clocks_state(
-+	struct display_clock *clk,
-+	enum dm_pp_clocks_state clocks_state)
-+{
-+	struct dm_pp_power_level_change_request level_change_req = {
-+			clocks_state };
-+
-+	if (clocks_state > clk->max_clks_state) {
-+		/*Requested state exceeds max supported state.*/
-+		dm_logger_write(clk->ctx->logger, LOG_WARNING,
-+				"Requested state exceeds max supported state");
-+		return false;
-+	} else if (clocks_state == clk->cur_min_clks_state) {
-+		/*if we're trying to set the same state, we can just return
-+		 * since nothing needs to be done*/
-+		return true;
-+	}
-+
-+	/* get max clock state from PPLIB */
-+	if (dm_pp_apply_power_level_change_request(clk->ctx, &level_change_req))
-+		clk->cur_min_clks_state = clocks_state;
-+
-+	return true;
-+}
-+
-+static int dce_set_clock(
-+	struct display_clock *clk,
-+	int requested_clk_khz)
-+{
-+	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
-+	struct bp_pixel_clock_parameters pxl_clk_params = { 0 };
-+	struct dc_bios *bp = clk->ctx->dc_bios;
-+	int actual_clock = requested_clk_khz;
-+
-+	/* Make sure requested clock isn't lower than minimum threshold*/
-+	if (requested_clk_khz > 0)
-+		requested_clk_khz = max(requested_clk_khz,
-+				clk_dce->dentist_vco_freq_khz / 64);
-+
-+	/* Prepare to program display clock*/
-+	pxl_clk_params.target_pixel_clock = requested_clk_khz;
-+	pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
-+
-+	bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
-+
-+	if (clk_dce->dfs_bypass_enabled) {
-+
-+		/* Cache the fixed display clock*/
-+		clk_dce->dfs_bypass_disp_clk =
-+			pxl_clk_params.dfs_bypass_display_clock;
-+		actual_clock = pxl_clk_params.dfs_bypass_display_clock;
-+	}
-+
-+	/* from power down, we need mark the clock state as ClocksStateNominal
-+	 * from HWReset, so when resume we will call pplib voltage regulator.*/
-+	if (requested_clk_khz == 0)
-+		clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-+	return actual_clock;
-+}
-+
-+static int dce_psr_set_clock(
-+	struct display_clock *clk,
-+	int requested_clk_khz)
-+{
-+	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
-+	struct dc_context *ctx = clk_dce->base.ctx;
-+	struct dc *core_dc = ctx->dc;
-+	struct dmcu *dmcu = core_dc->res_pool->dmcu;
-+	int actual_clk_khz = requested_clk_khz;
-+
-+	actual_clk_khz = dce_set_clock(clk, requested_clk_khz);
-+
-+	dmcu->funcs->set_psr_wait_loop(dmcu, actual_clk_khz / 1000 / 7);
-+	return actual_clk_khz;
-+}
-+
-+static int dce112_set_clock(
-+	struct display_clock *clk,
-+	int requested_clk_khz)
-+{
-+	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
-+	struct bp_set_dce_clock_parameters dce_clk_params;
-+	struct dc_bios *bp = clk->ctx->dc_bios;
-+	struct dc *core_dc = clk->ctx->dc;
-+	struct abm *abm =  core_dc->res_pool->abm;
-+	struct dmcu *dmcu = core_dc->res_pool->dmcu;
-+	int actual_clock = requested_clk_khz;
-+	/* Prepare to program display clock*/
-+	memset(&dce_clk_params, 0, sizeof(dce_clk_params));
-+
-+	/* Make sure requested clock isn't lower than minimum threshold*/
-+	if (requested_clk_khz > 0)
-+		requested_clk_khz = max(requested_clk_khz,
-+				clk_dce->dentist_vco_freq_khz / 62);
-+
-+	dce_clk_params.target_clock_frequency = requested_clk_khz;
-+	dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
-+	dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
-+
-+	bp->funcs->set_dce_clock(bp, &dce_clk_params);
-+	actual_clock = dce_clk_params.target_clock_frequency;
-+
-+	/* from power down, we need mark the clock state as ClocksStateNominal
-+	 * from HWReset, so when resume we will call pplib voltage regulator.*/
-+	if (requested_clk_khz == 0)
-+		clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-+
-+	/*Program DP ref Clock*/
-+	/*VBIOS will determine DPREFCLK frequency, so we don't set it*/
-+	dce_clk_params.target_clock_frequency = 0;
-+	dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
-+	dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
-+			(dce_clk_params.pll_id ==
-+					CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
-+
-+	bp->funcs->set_dce_clock(bp, &dce_clk_params);
-+
-+	if (abm->funcs->is_dmcu_initialized(abm) && clk_dce->dfs_bypass_disp_clk != actual_clock)
-+		dmcu->funcs->set_psr_wait_loop(dmcu,
-+				actual_clock / 1000 / 7);
-+	clk_dce->dfs_bypass_disp_clk = actual_clock;
-+	return actual_clock;
-+}
-+
-+static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce)
-+{
-+	struct dc_debug *debug = &clk_dce->base.ctx->dc->debug;
-+	struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
-+	struct integrated_info info = { { { 0 } } };
-+	struct dc_firmware_info fw_info = { { 0 } };
-+	int i;
-+
-+	if (bp->integrated_info)
-+		info = *bp->integrated_info;
-+
-+	clk_dce->dentist_vco_freq_khz = info.dentist_vco_freq;
-+	if (clk_dce->dentist_vco_freq_khz == 0) {
-+		bp->funcs->get_firmware_info(bp, &fw_info);
-+		clk_dce->dentist_vco_freq_khz =
-+			fw_info.smu_gpu_pll_output_freq;
-+		if (clk_dce->dentist_vco_freq_khz == 0)
-+			clk_dce->dentist_vco_freq_khz = 3600000;
-+	}
-+
-+	/*update the maximum display clock for each power state*/
-+	for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
-+		enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
-+
-+		switch (i) {
-+		case 0:
-+			clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
-+			break;
-+
-+		case 1:
-+			clk_state = DM_PP_CLOCKS_STATE_LOW;
-+			break;
-+
-+		case 2:
-+			clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
-+			break;
-+
-+		case 3:
-+			clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
-+			break;
-+
-+		default:
-+			clk_state = DM_PP_CLOCKS_STATE_INVALID;
-+			break;
-+		}
-+
-+		/*Do not allow bad VBIOS/SBIOS to override with invalid values,
-+		 * check for > 100MHz*/
-+		if (info.disp_clk_voltage[i].max_supported_clk >= 100000)
-+			clk_dce->max_clks_by_state[clk_state].display_clk_khz =
-+				info.disp_clk_voltage[i].max_supported_clk;
-+	}
-+
-+	if (!debug->disable_dfs_bypass && bp->integrated_info)
-+		if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
-+			clk_dce->dfs_bypass_enabled = true;
-+
-+	clk_dce->use_max_disp_clk = debug->max_disp_clk;
-+}
-+
-+static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)
-+{
-+	struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
-+	int ss_info_num = bp->funcs->get_ss_entry_number(
-+			bp, AS_SIGNAL_TYPE_GPU_PLL);
-+
-+	if (ss_info_num) {
-+		struct spread_spectrum_info info = { { 0 } };
-+		enum bp_result result = bp->funcs->get_spread_spectrum_info(
-+				bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
-+
-+		/* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
-+		 * even if SS not enabled and in that case
-+		 * SSInfo.spreadSpectrumPercentage !=0 would be sign
-+		 * that SS is enabled
-+		 */
-+		if (result == BP_RESULT_OK &&
-+				info.spread_spectrum_percentage != 0) {
-+			clk_dce->ss_on_dprefclk = true;
-+			clk_dce->dprefclk_ss_divider = info.spread_percentage_divider;
-+
-+			if (info.type.CENTER_MODE == 0) {
-+				/* TODO: Currently for DP Reference clock we
-+				 * need only SS percentage for
-+				 * downspread */
-+				clk_dce->dprefclk_ss_percentage =
-+						info.spread_spectrum_percentage;
-+			}
-+
-+			return;
-+		}
-+
-+		result = bp->funcs->get_spread_spectrum_info(
-+				bp, AS_SIGNAL_TYPE_DISPLAY_PORT, 0, &info);
-+
-+		/* Based on VBIOS, VBIOS will keep entry for DPREFCLK SS
-+		 * even if SS not enabled and in that case
-+		 * SSInfo.spreadSpectrumPercentage !=0 would be sign
-+		 * that SS is enabled
-+		 */
-+		if (result == BP_RESULT_OK &&
-+				info.spread_spectrum_percentage != 0) {
-+			clk_dce->ss_on_dprefclk = true;
-+			clk_dce->dprefclk_ss_divider = info.spread_percentage_divider;
-+
-+			if (info.type.CENTER_MODE == 0) {
-+				/* Currently for DP Reference clock we
-+				 * need only SS percentage for
-+				 * downspread */
-+				clk_dce->dprefclk_ss_percentage =
-+						info.spread_spectrum_percentage;
-+			}
-+		}
-+	}
-+}
-+
-+static bool dce_apply_clock_voltage_request(
-+	struct display_clock *clk,
-+	enum dm_pp_clock_type clocks_type,
-+	int clocks_in_khz,
-+	bool pre_mode_set,
-+	bool update_dp_phyclk)
-+{
-+	bool send_request = false;
-+	struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
-+
-+	switch (clocks_type) {
-+	case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
-+	case DM_PP_CLOCK_TYPE_PIXELCLK:
-+	case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	clock_voltage_req.clk_type = clocks_type;
-+	clock_voltage_req.clocks_in_khz = clocks_in_khz;
-+
-+	/* to pplib */
-+	if (pre_mode_set) {
-+		switch (clocks_type) {
-+		case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
-+			if (clocks_in_khz > clk->cur_clocks_value.dispclk_in_khz) {
-+				clk->cur_clocks_value.dispclk_notify_pplib_done = true;
-+				send_request = true;
-+			} else
-+				clk->cur_clocks_value.dispclk_notify_pplib_done = false;
-+			/* no matter incrase or decrase clock, update current clock value */
-+			clk->cur_clocks_value.dispclk_in_khz = clocks_in_khz;
-+			break;
-+		case DM_PP_CLOCK_TYPE_PIXELCLK:
-+			if (clocks_in_khz > clk->cur_clocks_value.max_pixelclk_in_khz) {
-+				clk->cur_clocks_value.pixelclk_notify_pplib_done = true;
-+				send_request = true;
-+			} else
-+				clk->cur_clocks_value.pixelclk_notify_pplib_done = false;
-+			/* no matter incrase or decrase clock, update current clock value */
-+			clk->cur_clocks_value.max_pixelclk_in_khz = clocks_in_khz;
-+			break;
-+		case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
-+			if (clocks_in_khz > clk->cur_clocks_value.max_non_dp_phyclk_in_khz) {
-+				clk->cur_clocks_value.phyclk_notigy_pplib_done = true;
-+				send_request = true;
-+			} else
-+				clk->cur_clocks_value.phyclk_notigy_pplib_done = false;
-+			/* no matter incrase or decrase clock, update current clock value */
-+			clk->cur_clocks_value.max_non_dp_phyclk_in_khz = clocks_in_khz;
-+			break;
-+		default:
-+			ASSERT(0);
-+			break;
-+		}
-+
-+	} else {
-+		switch (clocks_type) {
-+		case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
-+			if (!clk->cur_clocks_value.dispclk_notify_pplib_done)
-+				send_request = true;
-+			break;
-+		case DM_PP_CLOCK_TYPE_PIXELCLK:
-+			if (!clk->cur_clocks_value.pixelclk_notify_pplib_done)
-+				send_request = true;
-+			break;
-+		case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
-+			if (!clk->cur_clocks_value.phyclk_notigy_pplib_done)
-+				send_request = true;
-+			break;
-+		default:
-+			ASSERT(0);
-+			break;
-+		}
-+	}
-+	if (send_request) {
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+		if (clk->ctx->dce_version >= DCN_VERSION_1_0) {
-+			struct dc *core_dc = clk->ctx->dc;
-+			/*use dcfclk request voltage*/
-+			clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
-+			clock_voltage_req.clocks_in_khz =
-+				dcn_find_dcfclk_suits_all(core_dc, &clk->cur_clocks_value);
-+		}
-+#endif
-+		dm_pp_apply_clock_for_voltage_request(
-+			clk->ctx, &clock_voltage_req);
-+	}
-+	if (update_dp_phyclk && (clocks_in_khz >
-+	clk->cur_clocks_value.max_dp_phyclk_in_khz))
-+		clk->cur_clocks_value.max_dp_phyclk_in_khz = clocks_in_khz;
-+
-+	return true;
-+}
-+
-+
-+static const struct display_clock_funcs dce120_funcs = {
-+	.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq_wrkaround,
-+	.apply_clock_voltage_request = dce_apply_clock_voltage_request,
-+	.set_clock = dce112_set_clock
-+};
-+
-+static const struct display_clock_funcs dce112_funcs = {
-+	.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,
-+	.get_required_clocks_state = dce_get_required_clocks_state,
-+	.set_min_clocks_state = dce_clock_set_min_clocks_state,
-+	.set_clock = dce112_set_clock
-+};
-+
-+static const struct display_clock_funcs dce110_funcs = {
-+	.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,
-+	.get_required_clocks_state = dce_get_required_clocks_state,
-+	.set_min_clocks_state = dce_clock_set_min_clocks_state,
-+	.set_clock = dce_psr_set_clock
-+};
-+
-+static const struct display_clock_funcs dce_funcs = {
-+	.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,
-+	.get_required_clocks_state = dce_get_required_clocks_state,
-+	.set_min_clocks_state = dce_clock_set_min_clocks_state,
-+	.set_clock = dce_set_clock
-+};
-+
-+static void dce_disp_clk_construct(
-+	struct dce_disp_clk *clk_dce,
-+	struct dc_context *ctx,
-+	const struct dce_disp_clk_registers *regs,
-+	const struct dce_disp_clk_shift *clk_shift,
-+	const struct dce_disp_clk_mask *clk_mask)
-+{
-+	struct display_clock *base = &clk_dce->base;
-+
-+	base->ctx = ctx;
-+	base->funcs = &dce_funcs;
-+
-+	clk_dce->regs = regs;
-+	clk_dce->clk_shift = clk_shift;
-+	clk_dce->clk_mask = clk_mask;
-+
-+	clk_dce->dfs_bypass_disp_clk = 0;
-+
-+	clk_dce->dprefclk_ss_percentage = 0;
-+	clk_dce->dprefclk_ss_divider = 1000;
-+	clk_dce->ss_on_dprefclk = false;
-+
-+	base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-+	base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
-+
-+	dce_clock_read_integrated_info(clk_dce);
-+	dce_clock_read_ss_info(clk_dce);
-+
-+	dce_divider_range_construct(
-+		&clk_dce->divider_ranges[DIVIDER_RANGE_01],
-+		DIVIDER_RANGE_01_START,
-+		DIVIDER_RANGE_01_STEP_SIZE,
-+		DIVIDER_RANGE_01_BASE_DIVIDER_ID,
-+		DIVIDER_RANGE_02_BASE_DIVIDER_ID);
-+	dce_divider_range_construct(
-+		&clk_dce->divider_ranges[DIVIDER_RANGE_02],
-+		DIVIDER_RANGE_02_START,
-+		DIVIDER_RANGE_02_STEP_SIZE,
-+		DIVIDER_RANGE_02_BASE_DIVIDER_ID,
-+		DIVIDER_RANGE_03_BASE_DIVIDER_ID);
-+	dce_divider_range_construct(
-+		&clk_dce->divider_ranges[DIVIDER_RANGE_03],
-+		DIVIDER_RANGE_03_START,
-+		DIVIDER_RANGE_03_STEP_SIZE,
-+		DIVIDER_RANGE_03_BASE_DIVIDER_ID,
-+		DIVIDER_RANGE_MAX_DIVIDER_ID);
-+}
-+
-+struct display_clock *dce_disp_clk_create(
-+	struct dc_context *ctx,
-+	const struct dce_disp_clk_registers *regs,
-+	const struct dce_disp_clk_shift *clk_shift,
-+	const struct dce_disp_clk_mask *clk_mask)
-+{
-+	struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
-+
-+	if (clk_dce == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	memcpy(clk_dce->max_clks_by_state,
-+		dce80_max_clks_by_state,
-+		sizeof(dce80_max_clks_by_state));
-+
-+	dce_disp_clk_construct(
-+		clk_dce, ctx, regs, clk_shift, clk_mask);
-+
-+	return &clk_dce->base;
-+}
-+
-+struct display_clock *dce110_disp_clk_create(
-+	struct dc_context *ctx,
-+	const struct dce_disp_clk_registers *regs,
-+	const struct dce_disp_clk_shift *clk_shift,
-+	const struct dce_disp_clk_mask *clk_mask)
-+{
-+	struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
-+
-+	if (clk_dce == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	memcpy(clk_dce->max_clks_by_state,
-+		dce110_max_clks_by_state,
-+		sizeof(dce110_max_clks_by_state));
-+
-+	dce_disp_clk_construct(
-+		clk_dce, ctx, regs, clk_shift, clk_mask);
-+
-+	clk_dce->base.funcs = &dce110_funcs;
-+
-+	return &clk_dce->base;
-+}
-+
-+struct display_clock *dce112_disp_clk_create(
-+	struct dc_context *ctx,
-+	const struct dce_disp_clk_registers *regs,
-+	const struct dce_disp_clk_shift *clk_shift,
-+	const struct dce_disp_clk_mask *clk_mask)
-+{
-+	struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
-+
-+	if (clk_dce == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	memcpy(clk_dce->max_clks_by_state,
-+		dce112_max_clks_by_state,
-+		sizeof(dce112_max_clks_by_state));
-+
-+	dce_disp_clk_construct(
-+		clk_dce, ctx, regs, clk_shift, clk_mask);
-+
-+	clk_dce->base.funcs = &dce112_funcs;
-+
-+	return &clk_dce->base;
-+}
-+
-+struct display_clock *dce120_disp_clk_create(struct dc_context *ctx)
-+{
-+	struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
-+	struct dm_pp_clock_levels_with_voltage clk_level_info = {0};
-+
-+	if (clk_dce == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	memcpy(clk_dce->max_clks_by_state,
-+		dce120_max_clks_by_state,
-+		sizeof(dce120_max_clks_by_state));
-+
-+	dce_disp_clk_construct(
-+		clk_dce, ctx, NULL, NULL, NULL);
-+
-+	clk_dce->base.funcs = &dce120_funcs;
-+
-+	/* new in dce120 */
-+	if (!ctx->dc->debug.disable_pplib_clock_request  &&
-+			dm_pp_get_clock_levels_by_type_with_voltage(
-+			ctx, DM_PP_CLOCK_TYPE_DISPLAY_CLK, &clk_level_info)
-+						&& clk_level_info.num_levels)
-+		clk_dce->max_displ_clk_in_khz =
-+			clk_level_info.data[clk_level_info.num_levels - 1].clocks_in_khz;
-+	else
-+		clk_dce->max_displ_clk_in_khz = 1133000;
-+
-+	return &clk_dce->base;
-+}
-+
-+void dce_disp_clk_destroy(struct display_clock **disp_clk)
-+{
-+	struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(*disp_clk);
-+
-+	kfree(clk_dce);
-+	*disp_clk = NULL;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h.0130~	2017-12-14 06:39:58.415903567 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h	2017-12-14 06:39:58.415903567 +0100
-@@ -0,0 +1,137 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+
-+#ifndef _DCE_CLOCKS_H_
-+#define _DCE_CLOCKS_H_
-+
-+#include "display_clock.h"
-+
-+#define CLK_COMMON_REG_LIST_DCE_BASE() \
-+	.DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
-+	.DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
-+
-+#define CLK_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+#define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
-+	CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
-+	CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
-+
-+#define CLK_REG_FIELD_LIST(type) \
-+	type DPREFCLK_SRC_SEL; \
-+	type DENTIST_DPREFCLK_WDIVIDER;
-+
-+struct dce_disp_clk_shift {
-+	CLK_REG_FIELD_LIST(uint8_t)
-+};
-+
-+struct dce_disp_clk_mask {
-+	CLK_REG_FIELD_LIST(uint32_t)
-+};
-+
-+struct dce_disp_clk_registers {
-+	uint32_t DPREFCLK_CNTL;
-+	uint32_t DENTIST_DISPCLK_CNTL;
-+};
-+
-+/* Array identifiers and count for the divider ranges.*/
-+enum dce_divider_range_count {
-+	DIVIDER_RANGE_01 = 0,
-+	DIVIDER_RANGE_02,
-+	DIVIDER_RANGE_03,
-+	DIVIDER_RANGE_MAX /* == 3*/
-+};
-+
-+enum dce_divider_error_types {
-+	INVALID_DID = 0,
-+	INVALID_DIVIDER = 1
-+};
-+
-+struct dce_divider_range {
-+	int div_range_start;
-+	/* The end of this range of dividers.*/
-+	int div_range_end;
-+	/* The distance between each divider in this range.*/
-+	int div_range_step;
-+	/* The divider id for the lowest divider.*/
-+	int did_min;
-+	/* The divider id for the highest divider.*/
-+	int did_max;
-+};
-+
-+struct dce_disp_clk {
-+	struct display_clock base;
-+	const struct dce_disp_clk_registers *regs;
-+	const struct dce_disp_clk_shift *clk_shift;
-+	const struct dce_disp_clk_mask *clk_mask;
-+
-+	struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
-+	struct dce_divider_range divider_ranges[DIVIDER_RANGE_MAX];
-+
-+	bool use_max_disp_clk;
-+	int dentist_vco_freq_khz;
-+
-+	/* Cache the status of DFS-bypass feature*/
-+	bool dfs_bypass_enabled;
-+	/* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
-+	 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
-+	int dfs_bypass_disp_clk;
-+
-+	/* Flag for Enabled SS on DPREFCLK */
-+	bool ss_on_dprefclk;
-+	/* DPREFCLK SS percentage (if down-spread enabled) */
-+	int dprefclk_ss_percentage;
-+	/* DPREFCLK SS percentage Divider (100 or 1000) */
-+	int dprefclk_ss_divider;
-+
-+	/* max disp_clk from PPLIB for max validation display clock*/
-+	int max_displ_clk_in_khz;
-+};
-+
-+
-+struct display_clock *dce_disp_clk_create(
-+	struct dc_context *ctx,
-+	const struct dce_disp_clk_registers *regs,
-+	const struct dce_disp_clk_shift *clk_shift,
-+	const struct dce_disp_clk_mask *clk_mask);
-+
-+struct display_clock *dce110_disp_clk_create(
-+	struct dc_context *ctx,
-+	const struct dce_disp_clk_registers *regs,
-+	const struct dce_disp_clk_shift *clk_shift,
-+	const struct dce_disp_clk_mask *clk_mask);
-+
-+struct display_clock *dce112_disp_clk_create(
-+	struct dc_context *ctx,
-+	const struct dce_disp_clk_registers *regs,
-+	const struct dce_disp_clk_shift *clk_shift,
-+	const struct dce_disp_clk_mask *clk_mask);
-+
-+struct display_clock *dce120_disp_clk_create(struct dc_context *ctx);
-+
-+void dce_disp_clk_destroy(struct display_clock **disp_clk);
-+
-+#endif /* _DCE_CLOCKS_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c.0130~	2017-12-14 06:39:58.416903568 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c	2017-12-14 06:39:58.416903568 +0100
-@@ -0,0 +1,1383 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+
-+#include "dc_types.h"
-+#include "core_types.h"
-+
-+#include "include/grph_object_id.h"
-+#include "include/logger_interface.h"
-+
-+#include "dce_clock_source.h"
-+
-+#include "reg_helper.h"
-+
-+#define REG(reg)\
-+	(clk_src->regs->reg)
-+
-+#define CTX \
-+	clk_src->base.ctx
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
-+
-+#define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6
-+#define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
-+#define MAX_PLL_CALC_ERROR 0xFFFFFFFF
-+
-+static const struct spread_spectrum_data *get_ss_data_entry(
-+		struct dce110_clk_src *clk_src,
-+		enum signal_type signal,
-+		uint32_t pix_clk_khz)
-+{
-+
-+	uint32_t entrys_num;
-+	uint32_t i;
-+	struct spread_spectrum_data *ss_parm = NULL;
-+	struct spread_spectrum_data *ret = NULL;
-+
-+	switch (signal) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		ss_parm = clk_src->dvi_ss_params;
-+		entrys_num = clk_src->dvi_ss_params_cnt;
-+		break;
-+
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		ss_parm = clk_src->hdmi_ss_params;
-+		entrys_num = clk_src->hdmi_ss_params_cnt;
-+		break;
-+
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+	case SIGNAL_TYPE_VIRTUAL:
-+		ss_parm = clk_src->dp_ss_params;
-+		entrys_num = clk_src->dp_ss_params_cnt;
-+		break;
-+
-+	default:
-+		ss_parm = NULL;
-+		entrys_num = 0;
-+		break;
-+	}
-+
-+	if (ss_parm == NULL)
-+		return ret;
-+
-+	for (i = 0; i < entrys_num; ++i, ++ss_parm) {
-+		if (ss_parm->freq_range_khz >= pix_clk_khz) {
-+			ret = ss_parm;
-+			break;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+/**
-+* Function: calculate_fb_and_fractional_fb_divider
-+*
-+* * DESCRIPTION: Calculates feedback and fractional feedback dividers values
-+*
-+*PARAMETERS:
-+* targetPixelClock             Desired frequency in 10 KHz
-+* ref_divider                  Reference divider (already known)
-+* postDivider                  Post Divider (already known)
-+* feedback_divider_param       Pointer where to store
-+*					calculated feedback divider value
-+* fract_feedback_divider_param Pointer where to store
-+*					calculated fract feedback divider value
-+*
-+*RETURNS:
-+* It fills the locations pointed by feedback_divider_param
-+*					and fract_feedback_divider_param
-+* It returns	- true if feedback divider not 0
-+*		- false should never happen)
-+*/
-+static bool calculate_fb_and_fractional_fb_divider(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		uint32_t target_pix_clk_khz,
-+		uint32_t ref_divider,
-+		uint32_t post_divider,
-+		uint32_t *feedback_divider_param,
-+		uint32_t *fract_feedback_divider_param)
-+{
-+	uint64_t feedback_divider;
-+
-+	feedback_divider =
-+		(uint64_t)(target_pix_clk_khz * ref_divider * post_divider);
-+	feedback_divider *= 10;
-+	/* additional factor, since we divide by 10 afterwards */
-+	feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
-+	feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz);
-+
-+/*Round to the number of precision
-+ * The following code replace the old code (ullfeedbackDivider + 5)/10
-+ * for example if the difference between the number
-+ * of fractional feedback decimal point and the fractional FB Divider precision
-+ * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/
-+
-+	feedback_divider += (uint64_t)
-+			(5 * calc_pll_cs->fract_fb_divider_precision_factor);
-+	feedback_divider =
-+		div_u64(feedback_divider,
-+			calc_pll_cs->fract_fb_divider_precision_factor * 10);
-+	feedback_divider *= (uint64_t)
-+			(calc_pll_cs->fract_fb_divider_precision_factor);
-+
-+	*feedback_divider_param =
-+		div_u64_rem(
-+			feedback_divider,
-+			calc_pll_cs->fract_fb_divider_factor,
-+			fract_feedback_divider_param);
-+
-+	if (*feedback_divider_param != 0)
-+		return true;
-+	return false;
-+}
-+
-+/**
-+*calc_fb_divider_checking_tolerance
-+*
-+*DESCRIPTION: Calculates Feedback and Fractional Feedback divider values
-+*		for passed Reference and Post divider, checking for tolerance.
-+*PARAMETERS:
-+* pll_settings		Pointer to structure
-+* ref_divider		Reference divider (already known)
-+* postDivider		Post Divider (already known)
-+* tolerance		Tolerance for Calculated Pixel Clock to be within
-+*
-+*RETURNS:
-+* It fills the PLLSettings structure with PLL Dividers values
-+* if calculated values are within required tolerance
-+* It returns	- true if eror is within tolerance
-+*		- false if eror is not within tolerance
-+*/
-+static bool calc_fb_divider_checking_tolerance(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		struct pll_settings *pll_settings,
-+		uint32_t ref_divider,
-+		uint32_t post_divider,
-+		uint32_t tolerance)
-+{
-+	uint32_t feedback_divider;
-+	uint32_t fract_feedback_divider;
-+	uint32_t actual_calculated_clock_khz;
-+	uint32_t abs_err;
-+	uint64_t actual_calc_clk_khz;
-+
-+	calculate_fb_and_fractional_fb_divider(
-+			calc_pll_cs,
-+			pll_settings->adjusted_pix_clk,
-+			ref_divider,
-+			post_divider,
-+			&feedback_divider,
-+			&fract_feedback_divider);
-+
-+	/*Actual calculated value*/
-+	actual_calc_clk_khz = (uint64_t)(feedback_divider *
-+					calc_pll_cs->fract_fb_divider_factor) +
-+							fract_feedback_divider;
-+	actual_calc_clk_khz *= calc_pll_cs->ref_freq_khz;
-+	actual_calc_clk_khz =
-+		div_u64(actual_calc_clk_khz,
-+			ref_divider * post_divider *
-+				calc_pll_cs->fract_fb_divider_factor);
-+
-+	actual_calculated_clock_khz = (uint32_t)(actual_calc_clk_khz);
-+
-+	abs_err = (actual_calculated_clock_khz >
-+					pll_settings->adjusted_pix_clk)
-+			? actual_calculated_clock_khz -
-+					pll_settings->adjusted_pix_clk
-+			: pll_settings->adjusted_pix_clk -
-+						actual_calculated_clock_khz;
-+
-+	if (abs_err <= tolerance) {
-+		/*found good values*/
-+		pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;
-+		pll_settings->reference_divider = ref_divider;
-+		pll_settings->feedback_divider = feedback_divider;
-+		pll_settings->fract_feedback_divider = fract_feedback_divider;
-+		pll_settings->pix_clk_post_divider = post_divider;
-+		pll_settings->calculated_pix_clk =
-+			actual_calculated_clock_khz;
-+		pll_settings->vco_freq =
-+			actual_calculated_clock_khz * post_divider;
-+		return true;
-+	}
-+	return false;
-+}
-+
-+static bool calc_pll_dividers_in_range(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		struct pll_settings *pll_settings,
-+		uint32_t min_ref_divider,
-+		uint32_t max_ref_divider,
-+		uint32_t min_post_divider,
-+		uint32_t max_post_divider,
-+		uint32_t err_tolerance)
-+{
-+	uint32_t ref_divider;
-+	uint32_t post_divider;
-+	uint32_t tolerance;
-+
-+/* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25%
-+ * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/
-+	tolerance = (pll_settings->adjusted_pix_clk * err_tolerance) /
-+									10000;
-+	if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE)
-+		tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE;
-+
-+	for (
-+			post_divider = max_post_divider;
-+			post_divider >= min_post_divider;
-+			--post_divider) {
-+		for (
-+				ref_divider = min_ref_divider;
-+				ref_divider <= max_ref_divider;
-+				++ref_divider) {
-+			if (calc_fb_divider_checking_tolerance(
-+					calc_pll_cs,
-+					pll_settings,
-+					ref_divider,
-+					post_divider,
-+					tolerance)) {
-+				return true;
-+			}
-+		}
-+	}
-+
-+	return false;
-+}
-+
-+static uint32_t calculate_pixel_clock_pll_dividers(
-+		struct calc_pll_clock_source *calc_pll_cs,
-+		struct pll_settings *pll_settings)
-+{
-+	uint32_t err_tolerance;
-+	uint32_t min_post_divider;
-+	uint32_t max_post_divider;
-+	uint32_t min_ref_divider;
-+	uint32_t max_ref_divider;
-+
-+	if (pll_settings->adjusted_pix_clk == 0) {
-+		dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
-+			"%s Bad requested pixel clock", __func__);
-+		return MAX_PLL_CALC_ERROR;
-+	}
-+
-+/* 1) Find Post divider ranges */
-+	if (pll_settings->pix_clk_post_divider) {
-+		min_post_divider = pll_settings->pix_clk_post_divider;
-+		max_post_divider = pll_settings->pix_clk_post_divider;
-+	} else {
-+		min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider;
-+		if (min_post_divider * pll_settings->adjusted_pix_clk <
-+						calc_pll_cs->min_vco_khz) {
-+			min_post_divider = calc_pll_cs->min_vco_khz /
-+					pll_settings->adjusted_pix_clk;
-+			if ((min_post_divider *
-+					pll_settings->adjusted_pix_clk) <
-+						calc_pll_cs->min_vco_khz)
-+				min_post_divider++;
-+		}
-+
-+		max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider;
-+		if (max_post_divider * pll_settings->adjusted_pix_clk
-+				> calc_pll_cs->max_vco_khz)
-+			max_post_divider = calc_pll_cs->max_vco_khz /
-+					pll_settings->adjusted_pix_clk;
-+	}
-+
-+/* 2) Find Reference divider ranges
-+ * When SS is enabled, or for Display Port even without SS,
-+ * pll_settings->referenceDivider is not zero.
-+ * So calculate PPLL FB and fractional FB divider
-+ * using the passed reference divider*/
-+
-+	if (pll_settings->reference_divider) {
-+		min_ref_divider = pll_settings->reference_divider;
-+		max_ref_divider = pll_settings->reference_divider;
-+	} else {
-+		min_ref_divider = ((calc_pll_cs->ref_freq_khz
-+				/ calc_pll_cs->max_pll_input_freq_khz)
-+				> calc_pll_cs->min_pll_ref_divider)
-+			? calc_pll_cs->ref_freq_khz
-+					/ calc_pll_cs->max_pll_input_freq_khz
-+			: calc_pll_cs->min_pll_ref_divider;
-+
-+		max_ref_divider = ((calc_pll_cs->ref_freq_khz
-+				/ calc_pll_cs->min_pll_input_freq_khz)
-+				< calc_pll_cs->max_pll_ref_divider)
-+			? calc_pll_cs->ref_freq_khz /
-+					calc_pll_cs->min_pll_input_freq_khz
-+			: calc_pll_cs->max_pll_ref_divider;
-+	}
-+
-+/* If some parameters are invalid we could have scenario when  "min">"max"
-+ * which produced endless loop later.
-+ * We should investigate why we get the wrong parameters.
-+ * But to follow the similar logic when "adjustedPixelClock" is set to be 0
-+ * it is better to return here than cause system hang/watchdog timeout later.
-+ *  ## SVS Wed 15 Jul 2009 */
-+
-+	if (min_post_divider > max_post_divider) {
-+		dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
-+			"%s Post divider range is invalid", __func__);
-+		return MAX_PLL_CALC_ERROR;
-+	}
-+
-+	if (min_ref_divider > max_ref_divider) {
-+		dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
-+			"%s Reference divider range is invalid", __func__);
-+		return MAX_PLL_CALC_ERROR;
-+	}
-+
-+/* 3) Try to find PLL dividers given ranges
-+ * starting with minimal error tolerance.
-+ * Increase error tolerance until PLL dividers found*/
-+	err_tolerance = MAX_PLL_CALC_ERROR;
-+
-+	while (!calc_pll_dividers_in_range(
-+			calc_pll_cs,
-+			pll_settings,
-+			min_ref_divider,
-+			max_ref_divider,
-+			min_post_divider,
-+			max_post_divider,
-+			err_tolerance))
-+		err_tolerance += (err_tolerance > 10)
-+				? (err_tolerance / 10)
-+				: 1;
-+
-+	return err_tolerance;
-+}
-+
-+static bool pll_adjust_pix_clk(
-+		struct dce110_clk_src *clk_src,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	uint32_t actual_pix_clk_khz = 0;
-+	uint32_t requested_clk_khz = 0;
-+	struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = {
-+							0 };
-+	enum bp_result bp_result;
-+	switch (pix_clk_params->signal_type) {
-+	case SIGNAL_TYPE_HDMI_TYPE_A: {
-+		requested_clk_khz = pix_clk_params->requested_pix_clk;
-+		if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
-+			switch (pix_clk_params->color_depth) {
-+			case COLOR_DEPTH_101010:
-+				requested_clk_khz = (requested_clk_khz * 5) >> 2;
-+				break; /* x1.25*/
-+			case COLOR_DEPTH_121212:
-+				requested_clk_khz = (requested_clk_khz * 6) >> 2;
-+				break; /* x1.5*/
-+			case COLOR_DEPTH_161616:
-+				requested_clk_khz = requested_clk_khz * 2;
-+				break; /* x2.0*/
-+			default:
-+				break;
-+			}
-+		}
-+		actual_pix_clk_khz = requested_clk_khz;
-+	}
-+		break;
-+
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case SIGNAL_TYPE_EDP:
-+		requested_clk_khz = pix_clk_params->requested_sym_clk;
-+		actual_pix_clk_khz = pix_clk_params->requested_pix_clk;
-+		break;
-+
-+	default:
-+		requested_clk_khz = pix_clk_params->requested_pix_clk;
-+		actual_pix_clk_khz = pix_clk_params->requested_pix_clk;
-+		break;
-+	}
-+
-+	bp_adjust_pixel_clock_params.pixel_clock = requested_clk_khz;
-+	bp_adjust_pixel_clock_params.
-+		encoder_object_id = pix_clk_params->encoder_object_id;
-+	bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
-+	bp_adjust_pixel_clock_params.
-+		ss_enable = pix_clk_params->flags.ENABLE_SS;
-+	bp_result = clk_src->bios->funcs->adjust_pixel_clock(
-+			clk_src->bios, &bp_adjust_pixel_clock_params);
-+	if (bp_result == BP_RESULT_OK) {
-+		pll_settings->actual_pix_clk = actual_pix_clk_khz;
-+		pll_settings->adjusted_pix_clk =
-+			bp_adjust_pixel_clock_params.adjusted_pixel_clock;
-+		pll_settings->reference_divider =
-+			bp_adjust_pixel_clock_params.reference_divider;
-+		pll_settings->pix_clk_post_divider =
-+			bp_adjust_pixel_clock_params.pixel_clock_post_divider;
-+
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+/**
-+ * Calculate PLL Dividers for given Clock Value.
-+ * First will call VBIOS Adjust Exec table to check if requested Pixel clock
-+ * will be Adjusted based on usage.
-+ * Then it will calculate PLL Dividers for this Adjusted clock using preferred
-+ * method (Maximum VCO frequency).
-+ *
-+ * \return
-+ *     Calculation error in units of 0.01%
-+ */
-+
-+static uint32_t dce110_get_pix_clk_dividers_helper (
-+		struct dce110_clk_src *clk_src,
-+		struct pll_settings *pll_settings,
-+		struct pixel_clk_params *pix_clk_params)
-+{
-+	uint32_t field = 0;
-+	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
-+
-+	/* Check if reference clock is external (not pcie/xtalin)
-+	* HW Dce80 spec:
-+	* 00 - PCIE_REFCLK, 01 - XTALIN,    02 - GENERICA,    03 - GENERICB
-+	* 04 - HSYNCA,      05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
-+	REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field);
-+	pll_settings->use_external_clk = (field > 1);
-+
-+	/* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always
-+	 * (we do not care any more from SI for some older DP Sink which
-+	 * does not report SS support, no known issues) */
-+	if ((pix_clk_params->flags.ENABLE_SS) ||
-+			(dc_is_dp_signal(pix_clk_params->signal_type))) {
-+
-+		const struct spread_spectrum_data *ss_data = get_ss_data_entry(
-+					clk_src,
-+					pix_clk_params->signal_type,
-+					pll_settings->adjusted_pix_clk);
-+
-+		if (NULL != ss_data)
-+			pll_settings->ss_percentage = ss_data->percentage;
-+	}
-+
-+	/* Check VBIOS AdjustPixelClock Exec table */
-+	if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
-+		/* Should never happen, ASSERT and fill up values to be able
-+		 * to continue. */
-+		dm_logger_write(clk_src->base.ctx->logger, LOG_ERROR,
-+			"%s: Failed to adjust pixel clock!!", __func__);
-+		pll_settings->actual_pix_clk =
-+				pix_clk_params->requested_pix_clk;
-+		pll_settings->adjusted_pix_clk =
-+				pix_clk_params->requested_pix_clk;
-+
-+		if (dc_is_dp_signal(pix_clk_params->signal_type))
-+			pll_settings->adjusted_pix_clk = 100000;
-+	}
-+
-+	/* Calculate Dividers */
-+	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
-+		/*Calculate Dividers by HDMI object, no SS case or SS case */
-+		pll_calc_error =
-+			calculate_pixel_clock_pll_dividers(
-+					&clk_src->calc_pll_hdmi,
-+					pll_settings);
-+	else
-+		/*Calculate Dividers by default object, no SS case or SS case */
-+		pll_calc_error =
-+			calculate_pixel_clock_pll_dividers(
-+					&clk_src->calc_pll,
-+					pll_settings);
-+
-+	return pll_calc_error;
-+}
-+
-+static void dce112_get_pix_clk_dividers_helper (
-+		struct dce110_clk_src *clk_src,
-+		struct pll_settings *pll_settings,
-+		struct pixel_clk_params *pix_clk_params)
-+{
-+	uint32_t actualPixelClockInKHz;
-+
-+	actualPixelClockInKHz = pix_clk_params->requested_pix_clk;
-+	/* Calculate Dividers */
-+	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
-+		switch (pix_clk_params->color_depth) {
-+		case COLOR_DEPTH_101010:
-+			actualPixelClockInKHz = (actualPixelClockInKHz * 5) >> 2;
-+			break;
-+		case COLOR_DEPTH_121212:
-+			actualPixelClockInKHz = (actualPixelClockInKHz * 6) >> 2;
-+			break;
-+		case COLOR_DEPTH_161616:
-+			actualPixelClockInKHz = actualPixelClockInKHz * 2;
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+	pll_settings->actual_pix_clk = actualPixelClockInKHz;
-+	pll_settings->adjusted_pix_clk = actualPixelClockInKHz;
-+	pll_settings->calculated_pix_clk = pix_clk_params->requested_pix_clk;
-+}
-+
-+static uint32_t dce110_get_pix_clk_dividers(
-+		struct clock_source *cs,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
-+	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
-+
-+	if (pix_clk_params == NULL || pll_settings == NULL
-+			|| pix_clk_params->requested_pix_clk == 0) {
-+		dm_logger_write(clk_src->base.ctx->logger, LOG_ERROR,
-+			"%s: Invalid parameters!!\n", __func__);
-+		return pll_calc_error;
-+	}
-+
-+	memset(pll_settings, 0, sizeof(*pll_settings));
-+
-+	if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
-+			cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
-+		pll_settings->adjusted_pix_clk = clk_src->ext_clk_khz;
-+		pll_settings->calculated_pix_clk = clk_src->ext_clk_khz;
-+		pll_settings->actual_pix_clk =
-+					pix_clk_params->requested_pix_clk;
-+		return 0;
-+	}
-+
-+	switch (cs->ctx->dce_version) {
-+	case DCE_VERSION_8_0:
-+	case DCE_VERSION_8_1:
-+	case DCE_VERSION_8_3:
-+	case DCE_VERSION_10_0:
-+	case DCE_VERSION_11_0:
-+		pll_calc_error =
-+			dce110_get_pix_clk_dividers_helper(clk_src,
-+			pll_settings, pix_clk_params);
-+		break;
-+	case DCE_VERSION_11_2:
-+	case DCE_VERSION_12_0:
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	case DCN_VERSION_1_0:
-+#endif
-+
-+		dce112_get_pix_clk_dividers_helper(clk_src,
-+				pll_settings, pix_clk_params);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return pll_calc_error;
-+}
-+
-+static uint32_t dce110_get_pll_pixel_rate_in_hz(
-+	struct clock_source *cs,
-+	struct pixel_clk_params *pix_clk_params,
-+	struct pll_settings *pll_settings)
-+{
-+	uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
-+	struct dc *dc_core = cs->ctx->dc;
-+	struct dc_state *context = dc_core->current_state;
-+	struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst];
-+
-+	/* This function need separate to different DCE version, before separate, just use pixel clock */
-+	return pipe_ctx->stream->phy_pix_clk;
-+
-+}
-+
-+static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll(
-+	struct clock_source *cs,
-+	struct pixel_clk_params *pix_clk_params,
-+	struct pll_settings *pll_settings)
-+{
-+	uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
-+	struct dc *dc_core = cs->ctx->dc;
-+	struct dc_state *context = dc_core->current_state;
-+	struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst];
-+
-+	/* This function need separate to different DCE version, before separate, just use pixel clock */
-+	return pipe_ctx->stream->phy_pix_clk;
-+}
-+
-+static uint32_t dce110_get_d_to_pixel_rate_in_hz(
-+	struct clock_source *cs,
-+	struct pixel_clk_params *pix_clk_params,
-+	struct pll_settings *pll_settings)
-+{
-+	uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
-+	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
-+	int dto_enabled = 0;
-+	struct fixed31_32 pix_rate;
-+
-+	REG_GET(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, &dto_enabled);
-+
-+	if (dto_enabled) {
-+		uint32_t phase = 0;
-+		uint32_t modulo = 0;
-+		REG_GET(PHASE[inst], DP_DTO0_PHASE, &phase);
-+		REG_GET(MODULO[inst], DP_DTO0_MODULO, &modulo);
-+
-+		if (modulo == 0) {
-+			return 0;
-+		}
-+
-+		pix_rate = dal_fixed31_32_from_int(clk_src->ref_freq_khz);
-+		pix_rate = dal_fixed31_32_mul_int(pix_rate, 1000);
-+		pix_rate = dal_fixed31_32_mul_int(pix_rate, phase);
-+		pix_rate = dal_fixed31_32_div_int(pix_rate, modulo);
-+
-+		return dal_fixed31_32_round(pix_rate);
-+	} else {
-+		return dce110_get_dp_pixel_rate_from_combo_phy_pll(cs, pix_clk_params, pll_settings);
-+	}
-+}
-+
-+static uint32_t dce110_get_pix_rate_in_hz(
-+	struct clock_source *cs,
-+	struct pixel_clk_params *pix_clk_params,
-+	struct pll_settings *pll_settings)
-+{
-+	uint32_t pix_rate = 0;
-+	switch (pix_clk_params->signal_type) {
-+	case	SIGNAL_TYPE_DISPLAY_PORT:
-+	case	SIGNAL_TYPE_DISPLAY_PORT_MST:
-+	case	SIGNAL_TYPE_EDP:
-+	case	SIGNAL_TYPE_VIRTUAL:
-+		pix_rate = dce110_get_d_to_pixel_rate_in_hz(cs, pix_clk_params, pll_settings);
-+		break;
-+	case	SIGNAL_TYPE_HDMI_TYPE_A:
-+	default:
-+		pix_rate = dce110_get_pll_pixel_rate_in_hz(cs, pix_clk_params, pll_settings);
-+		break;
-+	}
-+
-+	return pix_rate;
-+}
-+
-+static bool disable_spread_spectrum(struct dce110_clk_src *clk_src)
-+{
-+	enum bp_result result;
-+	struct bp_spread_spectrum_parameters bp_ss_params = {0};
-+
-+	bp_ss_params.pll_id = clk_src->base.id;
-+
-+	/*Call ASICControl to process ATOMBIOS Exec table*/
-+	result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll(
-+			clk_src->bios,
-+			&bp_ss_params,
-+			false);
-+
-+	return result == BP_RESULT_OK;
-+}
-+
-+static bool calculate_ss(
-+		const struct pll_settings *pll_settings,
-+		const struct spread_spectrum_data *ss_data,
-+		struct delta_sigma_data *ds_data)
-+{
-+	struct fixed32_32 fb_div;
-+	struct fixed32_32 ss_amount;
-+	struct fixed32_32 ss_nslip_amount;
-+	struct fixed32_32 ss_ds_frac_amount;
-+	struct fixed32_32 ss_step_size;
-+	struct fixed32_32 modulation_time;
-+
-+	if (ds_data == NULL)
-+		return false;
-+	if (ss_data == NULL)
-+		return false;
-+	if (ss_data->percentage == 0)
-+		return false;
-+	if (pll_settings == NULL)
-+		return false;
-+
-+	memset(ds_data, 0, sizeof(struct delta_sigma_data));
-+
-+	/* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
-+	/* 6 decimal point support in fractional feedback divider */
-+	fb_div  = dal_fixed32_32_from_fraction(
-+		pll_settings->fract_feedback_divider, 1000000);
-+	fb_div = dal_fixed32_32_add_int(fb_div, pll_settings->feedback_divider);
-+
-+	ds_data->ds_frac_amount = 0;
-+	/*spreadSpectrumPercentage is in the unit of .01%,
-+	 * so have to divided by 100 * 100*/
-+	ss_amount = dal_fixed32_32_mul(
-+		fb_div, dal_fixed32_32_from_fraction(ss_data->percentage,
-+					100 * ss_data->percentage_divider));
-+	ds_data->feedback_amount = dal_fixed32_32_floor(ss_amount);
-+
-+	ss_nslip_amount = dal_fixed32_32_sub(ss_amount,
-+		dal_fixed32_32_from_int(ds_data->feedback_amount));
-+	ss_nslip_amount = dal_fixed32_32_mul_int(ss_nslip_amount, 10);
-+	ds_data->nfrac_amount = dal_fixed32_32_floor(ss_nslip_amount);
-+
-+	ss_ds_frac_amount = dal_fixed32_32_sub(ss_nslip_amount,
-+		dal_fixed32_32_from_int(ds_data->nfrac_amount));
-+	ss_ds_frac_amount = dal_fixed32_32_mul_int(ss_ds_frac_amount, 65536);
-+	ds_data->ds_frac_amount = dal_fixed32_32_floor(ss_ds_frac_amount);
-+
-+	/* compute SS_STEP_SIZE_DSFRAC */
-+	modulation_time = dal_fixed32_32_from_fraction(
-+		pll_settings->reference_freq * 1000,
-+		pll_settings->reference_divider * ss_data->modulation_freq_hz);
-+
-+	if (ss_data->flags.CENTER_SPREAD)
-+		modulation_time = dal_fixed32_32_div_int(modulation_time, 4);
-+	else
-+		modulation_time = dal_fixed32_32_div_int(modulation_time, 2);
-+
-+	ss_step_size = dal_fixed32_32_div(ss_amount, modulation_time);
-+	/* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/
-+	ss_step_size = dal_fixed32_32_mul_int(ss_step_size, 65536 * 10);
-+	ds_data->ds_frac_size =  dal_fixed32_32_floor(ss_step_size);
-+
-+	return true;
-+}
-+
-+static bool enable_spread_spectrum(
-+		struct dce110_clk_src *clk_src,
-+		enum signal_type signal, struct pll_settings *pll_settings)
-+{
-+	struct bp_spread_spectrum_parameters bp_params = {0};
-+	struct delta_sigma_data d_s_data;
-+	const struct spread_spectrum_data *ss_data = NULL;
-+
-+	ss_data = get_ss_data_entry(
-+			clk_src,
-+			signal,
-+			pll_settings->calculated_pix_clk);
-+
-+/* Pixel clock PLL has been programmed to generate desired pixel clock,
-+ * now enable SS on pixel clock */
-+/* TODO is it OK to return true not doing anything ??*/
-+	if (ss_data != NULL && pll_settings->ss_percentage != 0) {
-+		if (calculate_ss(pll_settings, ss_data, &d_s_data)) {
-+			bp_params.ds.feedback_amount =
-+					d_s_data.feedback_amount;
-+			bp_params.ds.nfrac_amount =
-+					d_s_data.nfrac_amount;
-+			bp_params.ds.ds_frac_size = d_s_data.ds_frac_size;
-+			bp_params.ds_frac_amount =
-+					d_s_data.ds_frac_amount;
-+			bp_params.flags.DS_TYPE = 1;
-+			bp_params.pll_id = clk_src->base.id;
-+			bp_params.percentage = ss_data->percentage;
-+			if (ss_data->flags.CENTER_SPREAD)
-+				bp_params.flags.CENTER_SPREAD = 1;
-+			if (ss_data->flags.EXTERNAL_SS)
-+				bp_params.flags.EXTERNAL_SS = 1;
-+
-+			if (BP_RESULT_OK !=
-+				clk_src->bios->funcs->
-+					enable_spread_spectrum_on_ppll(
-+							clk_src->bios,
-+							&bp_params,
-+							true))
-+				return false;
-+		} else
-+			return false;
-+	}
-+	return true;
-+}
-+
-+static void dce110_program_pixel_clk_resync(
-+		struct dce110_clk_src *clk_src,
-+		enum signal_type signal_type,
-+		enum dc_color_depth colordepth)
-+{
-+	REG_UPDATE(RESYNC_CNTL,
-+			DCCG_DEEP_COLOR_CNTL1, 0);
-+	/*
-+	 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
-+	 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
-+	 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
-+	 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
-+	 */
-+	if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
-+		return;
-+
-+	switch (colordepth) {
-+	case COLOR_DEPTH_888:
-+		REG_UPDATE(RESYNC_CNTL,
-+				DCCG_DEEP_COLOR_CNTL1, 0);
-+		break;
-+	case COLOR_DEPTH_101010:
-+		REG_UPDATE(RESYNC_CNTL,
-+				DCCG_DEEP_COLOR_CNTL1, 1);
-+		break;
-+	case COLOR_DEPTH_121212:
-+		REG_UPDATE(RESYNC_CNTL,
-+				DCCG_DEEP_COLOR_CNTL1, 2);
-+		break;
-+	case COLOR_DEPTH_161616:
-+		REG_UPDATE(RESYNC_CNTL,
-+				DCCG_DEEP_COLOR_CNTL1, 3);
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+static void dce112_program_pixel_clk_resync(
-+		struct dce110_clk_src *clk_src,
-+		enum signal_type signal_type,
-+		enum dc_color_depth colordepth,
-+		bool enable_ycbcr420)
-+{
-+	uint32_t deep_color_cntl = 0;
-+	uint32_t double_rate_enable = 0;
-+
-+	/*
-+	 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
-+	 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
-+	 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
-+	 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
-+	 */
-+	if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
-+		double_rate_enable = enable_ycbcr420 ? 1 : 0;
-+
-+		switch (colordepth) {
-+		case COLOR_DEPTH_888:
-+			deep_color_cntl = 0;
-+			break;
-+		case COLOR_DEPTH_101010:
-+			deep_color_cntl = 1;
-+			break;
-+		case COLOR_DEPTH_121212:
-+			deep_color_cntl = 2;
-+			break;
-+		case COLOR_DEPTH_161616:
-+			deep_color_cntl = 3;
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE)
-+		REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
-+				PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl,
-+				PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable);
-+	else
-+		REG_UPDATE(PIXCLK_RESYNC_CNTL,
-+				PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl);
-+
-+}
-+
-+static bool dce110_program_pix_clk(
-+		struct clock_source *clock_source,
-+		struct pixel_clk_params *pix_clk_params,
-+		struct pll_settings *pll_settings)
-+{
-+	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
-+	struct bp_pixel_clock_parameters bp_pc_params = {0};
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
-+		unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
-+		unsigned dp_dto_ref_kHz = 600000;
-+		/* DPREF clock from FPGA TODO: Does FPGA have this value? */
-+		unsigned clock_kHz = pll_settings->actual_pix_clk;
-+
-+		/* For faster simulation, if mode pixe clock less than 290MHz,
-+		 * pixel clock can be hard coded to 290Mhz. For 4K mode, pixel clock
-+		 * is greater than 500Mhz, need real pixel clock
-+		 * clock_kHz = 290000;
-+		 */
-+		/* TODO: un-hardcode when we can set display clock properly*/
-+		/*clock_kHz = pix_clk_params->requested_pix_clk;*/
-+		clock_kHz = 290000;
-+
-+		/* Set DTO values: phase = target clock, modulo = reference clock */
-+		REG_WRITE(PHASE[inst], clock_kHz);
-+		REG_WRITE(MODULO[inst], dp_dto_ref_kHz);
-+
-+		/* Enable DTO */
-+		REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
-+		return true;
-+	}
-+#endif
-+	/* First disable SS
-+	 * ATOMBIOS will enable by default SS on PLL for DP,
-+	 * do not disable it here
-+	 */
-+	if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
-+			!dc_is_dp_signal(pix_clk_params->signal_type) &&
-+			clock_source->ctx->dce_version <= DCE_VERSION_11_0)
-+		disable_spread_spectrum(clk_src);
-+
-+	/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
-+	bp_pc_params.controller_id = pix_clk_params->controller_id;
-+	bp_pc_params.pll_id = clock_source->id;
-+	bp_pc_params.target_pixel_clock = pll_settings->actual_pix_clk;
-+	bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
-+	bp_pc_params.signal_type = pix_clk_params->signal_type;
-+
-+	switch (clock_source->ctx->dce_version) {
-+	case DCE_VERSION_8_0:
-+	case DCE_VERSION_8_1:
-+	case DCE_VERSION_8_3:
-+	case DCE_VERSION_10_0:
-+	case DCE_VERSION_11_0:
-+		bp_pc_params.reference_divider = pll_settings->reference_divider;
-+		bp_pc_params.feedback_divider = pll_settings->feedback_divider;
-+		bp_pc_params.fractional_feedback_divider =
-+				pll_settings->fract_feedback_divider;
-+		bp_pc_params.pixel_clock_post_divider =
-+				pll_settings->pix_clk_post_divider;
-+		bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
-+						pll_settings->use_external_clk;
-+
-+		if (clk_src->bios->funcs->set_pixel_clock(
-+				clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
-+			return false;
-+		/* Enable SS
-+		 * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock),
-+		 * based on HW display PLL team, SS control settings should be programmed
-+		 * during PLL Reset, but they do not have effect
-+		 * until SS_EN is asserted.*/
-+		if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL
-+				&& !dc_is_dp_signal(pix_clk_params->signal_type)) {
-+
-+			if (pix_clk_params->flags.ENABLE_SS)
-+				if (!enable_spread_spectrum(clk_src,
-+								pix_clk_params->signal_type,
-+								pll_settings))
-+					return false;
-+
-+			/* Resync deep color DTO */
-+			dce110_program_pixel_clk_resync(clk_src,
-+						pix_clk_params->signal_type,
-+						pix_clk_params->color_depth);
-+		}
-+
-+		break;
-+	case DCE_VERSION_11_2:
-+	case DCE_VERSION_12_0:
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	case DCN_VERSION_1_0:
-+#endif
-+
-+		if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
-+			bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
-+							pll_settings->use_external_clk;
-+			bp_pc_params.flags.SET_XTALIN_REF_SRC =
-+							!pll_settings->use_external_clk;
-+			if (pix_clk_params->flags.SUPPORT_YCBCR420) {
-+				bp_pc_params.flags.SUPPORT_YUV_420 = 1;
-+			}
-+		}
-+		if (clk_src->bios->funcs->set_pixel_clock(
-+				clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
-+			return false;
-+		/* Resync deep color DTO */
-+		if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
-+			dce112_program_pixel_clk_resync(clk_src,
-+						pix_clk_params->signal_type,
-+						pix_clk_params->color_depth,
-+						pix_clk_params->flags.SUPPORT_YCBCR420);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return true;
-+}
-+
-+static bool dce110_clock_source_power_down(
-+		struct clock_source *clk_src)
-+{
-+	struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src);
-+	enum bp_result bp_result;
-+	struct bp_pixel_clock_parameters bp_pixel_clock_params = {0};
-+
-+	if (clk_src->dp_clk_src)
-+		return true;
-+
-+	/* If Pixel Clock is 0 it means Power Down Pll*/
-+	bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED;
-+	bp_pixel_clock_params.pll_id = clk_src->id;
-+	bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
-+
-+	/*Call ASICControl to process ATOMBIOS Exec table*/
-+	bp_result = dce110_clk_src->bios->funcs->set_pixel_clock(
-+			dce110_clk_src->bios,
-+			&bp_pixel_clock_params);
-+
-+	return bp_result == BP_RESULT_OK;
-+}
-+
-+/*****************************************/
-+/* Constructor                           */
-+/*****************************************/
-+static const struct clock_source_funcs dce110_clk_src_funcs = {
-+	.cs_power_down = dce110_clock_source_power_down,
-+	.program_pix_clk = dce110_program_pix_clk,
-+	.get_pix_clk_dividers = dce110_get_pix_clk_dividers,
-+	.get_pix_rate_in_hz = dce110_get_pix_rate_in_hz
-+};
-+
-+static void get_ss_info_from_atombios(
-+		struct dce110_clk_src *clk_src,
-+		enum as_signal_type as_signal,
-+		struct spread_spectrum_data *spread_spectrum_data[],
-+		uint32_t *ss_entries_num)
-+{
-+	enum bp_result bp_result = BP_RESULT_FAILURE;
-+	struct spread_spectrum_info *ss_info;
-+	struct spread_spectrum_data *ss_data;
-+	struct spread_spectrum_info *ss_info_cur;
-+	struct spread_spectrum_data *ss_data_cur;
-+	uint32_t i;
-+
-+	if (ss_entries_num == NULL) {
-+		dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
-+			"Invalid entry !!!\n");
-+		return;
-+	}
-+	if (spread_spectrum_data == NULL) {
-+		dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
-+			"Invalid array pointer!!!\n");
-+		return;
-+	}
-+
-+	spread_spectrum_data[0] = NULL;
-+	*ss_entries_num = 0;
-+
-+	*ss_entries_num = clk_src->bios->funcs->get_ss_entry_number(
-+			clk_src->bios,
-+			as_signal);
-+
-+	if (*ss_entries_num == 0)
-+		return;
-+
-+	ss_info = kzalloc(sizeof(struct spread_spectrum_info) * (*ss_entries_num),
-+			  GFP_KERNEL);
-+	ss_info_cur = ss_info;
-+	if (ss_info == NULL)
-+		return;
-+
-+	ss_data = kzalloc(sizeof(struct spread_spectrum_data) * (*ss_entries_num),
-+			  GFP_KERNEL);
-+	if (ss_data == NULL)
-+		goto out_free_info;
-+
-+	for (i = 0, ss_info_cur = ss_info;
-+		i < (*ss_entries_num);
-+		++i, ++ss_info_cur) {
-+
-+		bp_result = clk_src->bios->funcs->get_spread_spectrum_info(
-+				clk_src->bios,
-+				as_signal,
-+				i,
-+				ss_info_cur);
-+
-+		if (bp_result != BP_RESULT_OK)
-+			goto out_free_data;
-+	}
-+
-+	for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data;
-+		i < (*ss_entries_num);
-+		++i, ++ss_info_cur, ++ss_data_cur) {
-+
-+		if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
-+			dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
-+				"Invalid ATOMBIOS SS Table!!!\n");
-+			goto out_free_data;
-+		}
-+
-+		/* for HDMI check SS percentage,
-+		 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/
-+		if (as_signal == AS_SIGNAL_TYPE_HDMI
-+				&& ss_info_cur->spread_spectrum_percentage > 6){
-+			/* invalid input, do nothing */
-+			dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
-+				"Invalid SS percentage ");
-+			dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
-+				"for HDMI in ATOMBIOS info Table!!!\n");
-+			continue;
-+		}
-+		if (ss_info_cur->spread_percentage_divider == 1000) {
-+			/* Keep previous precision from ATOMBIOS for these
-+			* in case new precision set by ATOMBIOS for these
-+			* (otherwise all code in DCE specific classes
-+			* for all previous ASICs would need
-+			* to be updated for SS calculations,
-+			* Audio SS compensation and DP DTO SS compensation
-+			* which assumes fixed SS percentage Divider = 100)*/
-+			ss_info_cur->spread_spectrum_percentage /= 10;
-+			ss_info_cur->spread_percentage_divider = 100;
-+		}
-+
-+		ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range;
-+		ss_data_cur->percentage =
-+				ss_info_cur->spread_spectrum_percentage;
-+		ss_data_cur->percentage_divider =
-+				ss_info_cur->spread_percentage_divider;
-+		ss_data_cur->modulation_freq_hz =
-+				ss_info_cur->spread_spectrum_range;
-+
-+		if (ss_info_cur->type.CENTER_MODE)
-+			ss_data_cur->flags.CENTER_SPREAD = 1;
-+
-+		if (ss_info_cur->type.EXTERNAL)
-+			ss_data_cur->flags.EXTERNAL_SS = 1;
-+
-+	}
-+
-+	*spread_spectrum_data = ss_data;
-+	kfree(ss_info);
-+	return;
-+
-+out_free_data:
-+	kfree(ss_data);
-+	*ss_entries_num = 0;
-+out_free_info:
-+	kfree(ss_info);
-+}
-+
-+static void ss_info_from_atombios_create(
-+	struct dce110_clk_src *clk_src)
-+{
-+	get_ss_info_from_atombios(
-+		clk_src,
-+		AS_SIGNAL_TYPE_DISPLAY_PORT,
-+		&clk_src->dp_ss_params,
-+		&clk_src->dp_ss_params_cnt);
-+	get_ss_info_from_atombios(
-+		clk_src,
-+		AS_SIGNAL_TYPE_HDMI,
-+		&clk_src->hdmi_ss_params,
-+		&clk_src->hdmi_ss_params_cnt);
-+	get_ss_info_from_atombios(
-+		clk_src,
-+		AS_SIGNAL_TYPE_DVI,
-+		&clk_src->dvi_ss_params,
-+		&clk_src->dvi_ss_params_cnt);
-+}
-+
-+static bool calc_pll_max_vco_construct(
-+			struct calc_pll_clock_source *calc_pll_cs,
-+			struct calc_pll_clock_source_init_data *init_data)
-+{
-+	uint32_t i;
-+	struct dc_firmware_info fw_info = { { 0 } };
-+	if (calc_pll_cs == NULL ||
-+			init_data == NULL ||
-+			init_data->bp == NULL)
-+		return false;
-+
-+	if (init_data->bp->funcs->get_firmware_info(
-+				init_data->bp,
-+				&fw_info) != BP_RESULT_OK)
-+		return false;
-+
-+	calc_pll_cs->ctx = init_data->ctx;
-+	calc_pll_cs->ref_freq_khz = fw_info.pll_info.crystal_frequency;
-+	calc_pll_cs->min_vco_khz =
-+			fw_info.pll_info.min_output_pxl_clk_pll_frequency;
-+	calc_pll_cs->max_vco_khz =
-+			fw_info.pll_info.max_output_pxl_clk_pll_frequency;
-+
-+	if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
-+		calc_pll_cs->max_pll_input_freq_khz =
-+			init_data->max_override_input_pxl_clk_pll_freq_khz;
-+	else
-+		calc_pll_cs->max_pll_input_freq_khz =
-+			fw_info.pll_info.max_input_pxl_clk_pll_frequency;
-+
-+	if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
-+		calc_pll_cs->min_pll_input_freq_khz =
-+			init_data->min_override_input_pxl_clk_pll_freq_khz;
-+	else
-+		calc_pll_cs->min_pll_input_freq_khz =
-+			fw_info.pll_info.min_input_pxl_clk_pll_frequency;
-+
-+	calc_pll_cs->min_pix_clock_pll_post_divider =
-+			init_data->min_pix_clk_pll_post_divider;
-+	calc_pll_cs->max_pix_clock_pll_post_divider =
-+			init_data->max_pix_clk_pll_post_divider;
-+	calc_pll_cs->min_pll_ref_divider =
-+			init_data->min_pll_ref_divider;
-+	calc_pll_cs->max_pll_ref_divider =
-+			init_data->max_pll_ref_divider;
-+
-+	if (init_data->num_fract_fb_divider_decimal_point == 0 ||
-+		init_data->num_fract_fb_divider_decimal_point_precision >
-+				init_data->num_fract_fb_divider_decimal_point) {
-+		dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
-+			"The dec point num or precision is incorrect!");
-+		return false;
-+	}
-+	if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
-+		dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
-+			"Incorrect fract feedback divider precision num!");
-+		return false;
-+	}
-+
-+	calc_pll_cs->fract_fb_divider_decimal_points_num =
-+				init_data->num_fract_fb_divider_decimal_point;
-+	calc_pll_cs->fract_fb_divider_precision =
-+			init_data->num_fract_fb_divider_decimal_point_precision;
-+	calc_pll_cs->fract_fb_divider_factor = 1;
-+	for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i)
-+		calc_pll_cs->fract_fb_divider_factor *= 10;
-+
-+	calc_pll_cs->fract_fb_divider_precision_factor = 1;
-+	for (
-+		i = 0;
-+		i < (calc_pll_cs->fract_fb_divider_decimal_points_num -
-+				calc_pll_cs->fract_fb_divider_precision);
-+		++i)
-+		calc_pll_cs->fract_fb_divider_precision_factor *= 10;
-+
-+	return true;
-+}
-+
-+bool dce110_clk_src_construct(
-+	struct dce110_clk_src *clk_src,
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id id,
-+	const struct dce110_clk_src_regs *regs,
-+	const struct dce110_clk_src_shift *cs_shift,
-+	const struct dce110_clk_src_mask *cs_mask)
-+{
-+	struct dc_firmware_info fw_info = { { 0 } };
-+	struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi;
-+	struct calc_pll_clock_source_init_data calc_pll_cs_init_data;
-+
-+	clk_src->base.ctx = ctx;
-+	clk_src->bios = bios;
-+	clk_src->base.id = id;
-+	clk_src->base.funcs = &dce110_clk_src_funcs;
-+
-+	clk_src->regs = regs;
-+	clk_src->cs_shift = cs_shift;
-+	clk_src->cs_mask = cs_mask;
-+
-+	if (clk_src->bios->funcs->get_firmware_info(
-+			clk_src->bios, &fw_info) != BP_RESULT_OK) {
-+		ASSERT_CRITICAL(false);
-+		goto unexpected_failure;
-+	}
-+
-+	clk_src->ext_clk_khz =
-+			fw_info.external_clock_source_frequency_for_dp;
-+
-+	switch (clk_src->base.ctx->dce_version) {
-+	case DCE_VERSION_8_0:
-+	case DCE_VERSION_8_1:
-+	case DCE_VERSION_8_3:
-+	case DCE_VERSION_10_0:
-+	case DCE_VERSION_11_0:
-+
-+		/* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
-+		calc_pll_cs_init_data.bp = bios;
-+		calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1;
-+		calc_pll_cs_init_data.max_pix_clk_pll_post_divider =
-+				clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
-+		calc_pll_cs_init_data.min_pll_ref_divider =	1;
-+		calc_pll_cs_init_data.max_pll_ref_divider =	clk_src->cs_mask->PLL_REF_DIV;
-+		/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
-+		calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz =	0;
-+		/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
-+		calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz =	0;
-+		/*numberOfFractFBDividerDecimalPoints*/
-+		calc_pll_cs_init_data.num_fract_fb_divider_decimal_point =
-+				FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
-+		/*number of decimal point to round off for fractional feedback divider value*/
-+		calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision =
-+				FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
-+		calc_pll_cs_init_data.ctx =	ctx;
-+
-+		/*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */
-+		calc_pll_cs_init_data_hdmi.bp = bios;
-+		calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1;
-+		calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider =
-+				clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
-+		calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1;
-+		calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
-+		/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
-+		calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500;
-+		/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
-+		calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000;
-+		/*numberOfFractFBDividerDecimalPoints*/
-+		calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point =
-+				FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
-+		/*number of decimal point to round off for fractional feedback divider value*/
-+		calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision =
-+				FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
-+		calc_pll_cs_init_data_hdmi.ctx = ctx;
-+
-+		clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency;
-+
-+		if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL)
-+			return true;
-+
-+		/* PLL only from here on */
-+		ss_info_from_atombios_create(clk_src);
-+
-+		if (!calc_pll_max_vco_construct(
-+				&clk_src->calc_pll,
-+				&calc_pll_cs_init_data)) {
-+			ASSERT_CRITICAL(false);
-+			goto unexpected_failure;
-+		}
-+
-+
-+		calc_pll_cs_init_data_hdmi.
-+				min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2;
-+		calc_pll_cs_init_data_hdmi.
-+				max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz;
-+
-+
-+		if (!calc_pll_max_vco_construct(
-+				&clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) {
-+			ASSERT_CRITICAL(false);
-+			goto unexpected_failure;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return true;
-+
-+unexpected_failure:
-+	return false;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h.0130~	2017-12-14 06:39:58.416903568 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h	2017-12-14 06:39:58.416903568 +0100
-@@ -0,0 +1,145 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_CLOCK_SOURCE_DCE_H__
-+#define __DC_CLOCK_SOURCE_DCE_H__
-+
-+#include "../inc/clock_source.h"
-+
-+#define TO_DCE110_CLK_SRC(clk_src)\
-+	container_of(clk_src, struct dce110_clk_src, base)
-+
-+#define CS_COMMON_REG_LIST_DCE_100_110(id) \
-+		SRI(RESYNC_CNTL, PIXCLK, id), \
-+		SRI(PLL_CNTL, BPHYC_PLL, id)
-+
-+#define CS_COMMON_REG_LIST_DCE_80(id) \
-+		SRI(RESYNC_CNTL, PIXCLK, id), \
-+		SRI(PLL_CNTL, DCCG_PLL, id)
-+
-+#define CS_COMMON_REG_LIST_DCE_112(id) \
-+		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
-+
-+
-+#define CS_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+#define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
-+	CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\
-+	CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\
-+	CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\
-+	CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)
-+
-+#define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
-+	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
-+	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+
-+#define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
-+		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
-+		SRII(PHASE, DP_DTO, 0),\
-+		SRII(PHASE, DP_DTO, 1),\
-+		SRII(PHASE, DP_DTO, 2),\
-+		SRII(PHASE, DP_DTO, 3),\
-+		SRII(MODULO, DP_DTO, 0),\
-+		SRII(MODULO, DP_DTO, 1),\
-+		SRII(MODULO, DP_DTO, 2),\
-+		SRII(MODULO, DP_DTO, 3),\
-+		SRII(PIXEL_RATE_CNTL, OTG, 0), \
-+		SRII(PIXEL_RATE_CNTL, OTG, 1), \
-+		SRII(PIXEL_RATE_CNTL, OTG, 2), \
-+		SRII(PIXEL_RATE_CNTL, OTG, 3)
-+
-+#define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
-+	CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
-+	CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
-+	CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
-+	CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
-+
-+#endif
-+
-+#define CS_REG_FIELD_LIST(type) \
-+	type PLL_REF_DIV_SRC; \
-+	type DCCG_DEEP_COLOR_CNTL1; \
-+	type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \
-+	type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \
-+	type PLL_POST_DIV_PIXCLK; \
-+	type PLL_REF_DIV; \
-+	type DP_DTO0_PHASE; \
-+	type DP_DTO0_MODULO; \
-+	type DP_DTO0_ENABLE;
-+
-+struct dce110_clk_src_shift {
-+	CS_REG_FIELD_LIST(uint8_t)
-+};
-+
-+struct dce110_clk_src_mask{
-+	CS_REG_FIELD_LIST(uint32_t)
-+};
-+
-+struct dce110_clk_src_regs {
-+	uint32_t RESYNC_CNTL;
-+	uint32_t PIXCLK_RESYNC_CNTL;
-+	uint32_t PLL_CNTL;
-+
-+	/* below are for DTO.
-+	 * todo: should probably use different struct to not waste space
-+	 */
-+	uint32_t PHASE[MAX_PIPES];
-+	uint32_t MODULO[MAX_PIPES];
-+	uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
-+};
-+
-+struct dce110_clk_src {
-+	struct clock_source base;
-+	const struct dce110_clk_src_regs *regs;
-+	const struct dce110_clk_src_mask *cs_mask;
-+	const struct dce110_clk_src_shift *cs_shift;
-+	struct dc_bios *bios;
-+
-+	struct spread_spectrum_data *dp_ss_params;
-+	uint32_t dp_ss_params_cnt;
-+	struct spread_spectrum_data *hdmi_ss_params;
-+	uint32_t hdmi_ss_params_cnt;
-+	struct spread_spectrum_data *dvi_ss_params;
-+	uint32_t dvi_ss_params_cnt;
-+
-+	uint32_t ext_clk_khz;
-+	uint32_t ref_freq_khz;
-+
-+	struct calc_pll_clock_source calc_pll;
-+	struct calc_pll_clock_source calc_pll_hdmi;
-+};
-+
-+bool dce110_clk_src_construct(
-+	struct dce110_clk_src *clk_src,
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id,
-+	const struct dce110_clk_src_regs *regs,
-+	const struct dce110_clk_src_shift *cs_shift,
-+	const struct dce110_clk_src_mask *cs_mask);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c.0130~	2017-12-14 06:39:58.416903568 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c	2017-12-14 06:39:58.416903568 +0100
-@@ -0,0 +1,784 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "core_types.h"
-+#include "link_encoder.h"
-+#include "dce_dmcu.h"
-+#include "dm_services.h"
-+#include "reg_helper.h"
-+#include "fixed32_32.h"
-+#include "dc.h"
-+
-+#define TO_DCE_DMCU(dmcu)\
-+	container_of(dmcu, struct dce_dmcu, base)
-+
-+#define REG(reg) \
-+	(dmcu_dce->regs->reg)
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name
-+
-+#define CTX \
-+	dmcu_dce->base.ctx
-+
-+/* PSR related commands */
-+#define PSR_ENABLE 0x20
-+#define PSR_EXIT 0x21
-+#define PSR_SET 0x23
-+#define PSR_SET_WAITLOOP 0x31
-+#define MCP_INIT_DMCU 0x88
-+#define MCP_INIT_IRAM 0x89
-+#define MCP_DMCU_VERSION 0x90
-+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK   0x00000001L
-+unsigned int cached_wait_loop_number = 0;
-+
-+static bool dce_dmcu_init(struct dmcu *dmcu)
-+{
-+	// Do nothing
-+	return true;
-+}
-+
-+bool dce_dmcu_load_iram(struct dmcu *dmcu,
-+		unsigned int start_offset,
-+		const char *src,
-+		unsigned int bytes)
-+{
-+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
-+	unsigned int count = 0;
-+
-+	/* Enable write access to IRAM */
-+	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
-+			IRAM_HOST_ACCESS_EN, 1,
-+			IRAM_WR_ADDR_AUTO_INC, 1);
-+
-+	REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
-+
-+	REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
-+
-+	for (count = 0; count < bytes; count++)
-+		REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
-+
-+	/* Disable write access to IRAM to allow dynamic sleep state */
-+	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
-+			IRAM_HOST_ACCESS_EN, 0,
-+			IRAM_WR_ADDR_AUTO_INC, 0);
-+
-+	return true;
-+}
-+
-+static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
-+{
-+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
-+
-+	uint32_t psr_state_offset = 0xf0;
-+
-+	/* Enable write access to IRAM */
-+	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
-+
-+	REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
-+
-+	/* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
-+	REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
-+
-+	/* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
-+	*psr_state = REG_READ(DMCU_IRAM_RD_DATA);
-+
-+	/* Disable write access to IRAM after finished using IRAM
-+	 * in order to allow dynamic sleep state
-+	 */
-+	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
-+}
-+
-+static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
-+{
-+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
-+	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
-+	unsigned int dmcu_wait_reg_ready_interval = 100;
-+
-+	unsigned int retryCount;
-+	uint32_t psr_state = 0;
-+
-+	/* waitDMCUReadyForCmd */
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
-+				dmcu_wait_reg_ready_interval,
-+				dmcu_max_retry_on_wait_reg_ready);
-+
-+	/* setDMCUParam_Cmd */
-+	if (enable)
-+		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
-+				PSR_ENABLE);
-+	else
-+		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
-+				PSR_EXIT);
-+
-+	/* notifyDMCUMsg */
-+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-+	if (wait == true) {
-+		for (retryCount = 0; retryCount <= 100; retryCount++) {
-+			dce_get_dmcu_psr_state(dmcu, &psr_state);
-+			if (enable) {
-+				if (psr_state != 0)
-+					break;
-+			} else {
-+				if (psr_state == 0)
-+					break;
-+			}
-+			udelay(10);
-+		}
-+	}
-+}
-+
-+static void dce_dmcu_setup_psr(struct dmcu *dmcu,
-+		struct dc_link *link,
-+		struct psr_context *psr_context)
-+{
-+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
-+
-+	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
-+	unsigned int dmcu_wait_reg_ready_interval = 100;
-+
-+	union dce_dmcu_psr_config_data_reg1 masterCmdData1;
-+	union dce_dmcu_psr_config_data_reg2 masterCmdData2;
-+	union dce_dmcu_psr_config_data_reg3 masterCmdData3;
-+
-+	link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
-+			psr_context->psrExitLinkTrainingRequired);
-+
-+	/* Enable static screen interrupts for PSR supported display */
-+	/* Disable the interrupt coming from other displays. */
-+	REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
-+			STATIC_SCREEN1_INT_TO_UC_EN, 0,
-+			STATIC_SCREEN2_INT_TO_UC_EN, 0,
-+			STATIC_SCREEN3_INT_TO_UC_EN, 0,
-+			STATIC_SCREEN4_INT_TO_UC_EN, 0);
-+
-+	switch (psr_context->controllerId) {
-+	/* Driver uses case 1 for unconfigured */
-+	case 1:
-+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-+				STATIC_SCREEN1_INT_TO_UC_EN, 1);
-+		break;
-+	case 2:
-+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-+				STATIC_SCREEN2_INT_TO_UC_EN, 1);
-+		break;
-+	case 3:
-+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-+				STATIC_SCREEN3_INT_TO_UC_EN, 1);
-+		break;
-+	case 4:
-+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-+				STATIC_SCREEN4_INT_TO_UC_EN, 1);
-+		break;
-+	case 5:
-+		/* CZ/NL only has 4 CRTC!!
-+		 * really valid.
-+		 * There is no interrupt enable mask for these instances.
-+		 */
-+		break;
-+	case 6:
-+		/* CZ/NL only has 4 CRTC!!
-+		 * These are here because they are defined in HW regspec,
-+		 * but not really valid. There is no interrupt enable mask
-+		 * for these instances.
-+		 */
-+		break;
-+	default:
-+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-+				STATIC_SCREEN1_INT_TO_UC_EN, 1);
-+		break;
-+	}
-+
-+	link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
-+			psr_context->sdpTransmitLineNumDeadline);
-+
-+	if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)
-+		REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
-+
-+	/* waitDMCUReadyForCmd */
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
-+					dmcu_wait_reg_ready_interval,
-+					dmcu_max_retry_on_wait_reg_ready);
-+
-+	/* setDMCUParam_PSRHostConfigData */
-+	masterCmdData1.u32All = 0;
-+	masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
-+	masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
-+	masterCmdData1.bits.rfb_update_auto_en =
-+			psr_context->rfb_update_auto_en;
-+	masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
-+	masterCmdData1.bits.dcp_sel = psr_context->controllerId;
-+	masterCmdData1.bits.phy_type  = psr_context->phyType;
-+	masterCmdData1.bits.frame_cap_ind =
-+			psr_context->psrFrameCaptureIndicationReq;
-+	masterCmdData1.bits.aux_chan = psr_context->channel;
-+	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
-+	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
-+					masterCmdData1.u32All);
-+
-+	masterCmdData2.u32All = 0;
-+	masterCmdData2.bits.dig_fe = psr_context->engineId;
-+	masterCmdData2.bits.dig_be = psr_context->transmitterId;
-+	masterCmdData2.bits.skip_wait_for_pll_lock =
-+			psr_context->skipPsrWaitForPllLock;
-+	masterCmdData2.bits.frame_delay = psr_context->frame_delay;
-+	masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
-+	masterCmdData2.bits.num_of_controllers =
-+			psr_context->numberOfControllers;
-+	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
-+			masterCmdData2.u32All);
-+
-+	masterCmdData3.u32All = 0;
-+	masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
-+	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
-+			masterCmdData3.u32All);
-+
-+	/* setDMCUParam_Cmd */
-+	REG_UPDATE(MASTER_COMM_CMD_REG,
-+			MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
-+
-+	/* notifyDMCUMsg */
-+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-+}
-+
-+static void dce_psr_wait_loop(
-+	struct dmcu *dmcu,
-+	unsigned int wait_loop_number)
-+{
-+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
-+	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
-+	if (cached_wait_loop_number == wait_loop_number)
-+		return;
-+
-+	/* waitDMCUReadyForCmd */
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
-+
-+	masterCmdData1.u32 = 0;
-+	masterCmdData1.bits.wait_loop = wait_loop_number;
-+	cached_wait_loop_number = wait_loop_number;
-+	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
-+
-+	/* setDMCUParam_Cmd */
-+	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
-+
-+	/* notifyDMCUMsg */
-+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-+}
-+
-+static void dce_get_psr_wait_loop(unsigned int *psr_wait_loop_number)
-+{
-+	*psr_wait_loop_number = cached_wait_loop_number;
-+	return;
-+}
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+static void dcn10_get_dmcu_state(struct dmcu *dmcu)
-+{
-+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
-+	uint32_t dmcu_state_offset = 0xf6;
-+
-+	/* Enable write access to IRAM */
-+	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
-+			IRAM_HOST_ACCESS_EN, 1,
-+			IRAM_RD_ADDR_AUTO_INC, 1);
-+
-+	REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
-+
-+	/* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
-+	REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_state_offset);
-+
-+	/* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
-+	dmcu->dmcu_state = REG_READ(DMCU_IRAM_RD_DATA);
-+
-+	/* Disable write access to IRAM to allow dynamic sleep state */
-+	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
-+			IRAM_HOST_ACCESS_EN, 0,
-+			IRAM_RD_ADDR_AUTO_INC, 0);
-+}
-+
-+static void dcn10_get_dmcu_version(struct dmcu *dmcu)
-+{
-+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
-+	uint32_t dmcu_version_offset = 0xf1;
-+
-+	/* Clear scratch */
-+	REG_WRITE(DC_DMCU_SCRATCH, 0);
-+
-+	/* Enable write access to IRAM */
-+	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
-+			IRAM_HOST_ACCESS_EN, 1,
-+			IRAM_RD_ADDR_AUTO_INC, 1);
-+
-+	REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
-+
-+	/* Write address to IRAM_RD_ADDR and read from DATA register */
-+	REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);
-+	dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);
-+	dmcu->dmcu_version.year = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
-+						REG_READ(DMCU_IRAM_RD_DATA));
-+	dmcu->dmcu_version.month = REG_READ(DMCU_IRAM_RD_DATA);
-+	dmcu->dmcu_version.day = REG_READ(DMCU_IRAM_RD_DATA);
-+
-+	/* Disable write access to IRAM to allow dynamic sleep state */
-+	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
-+			IRAM_HOST_ACCESS_EN, 0,
-+			IRAM_RD_ADDR_AUTO_INC, 0);
-+
-+	/* Send MCP command message to DMCU to get version reply from FW.
-+	 * We expect this version should match the one in IRAM, otherwise
-+	 * something is wrong with DMCU and we should fail and disable UC.
-+	 */
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
-+
-+	/* Set command to get DMCU version from microcontroller */
-+	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
-+			MCP_DMCU_VERSION);
-+
-+	/* Notify microcontroller of new command */
-+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-+
-+	/* Ensure command has been executed before continuing */
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
-+
-+	/* Somehow version does not match, so fail and return version 0 */
-+	if (dmcu->dmcu_version.interface_version != REG_READ(DC_DMCU_SCRATCH))
-+		dmcu->dmcu_version.interface_version = 0;
-+}
-+
-+static bool dcn10_dmcu_init(struct dmcu *dmcu)
-+{
-+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
-+
-+	/* DMCU FW should populate the scratch register if running */
-+	if (REG_READ(DC_DMCU_SCRATCH) == 0)
-+		return false;
-+
-+	/* Check state is uninitialized */
-+	dcn10_get_dmcu_state(dmcu);
-+
-+	/* If microcontroller is already initialized, do nothing */
-+	if (dmcu->dmcu_state == DMCU_RUNNING)
-+		return true;
-+
-+	/* Retrieve and cache the DMCU firmware version. */
-+	dcn10_get_dmcu_version(dmcu);
-+
-+	/* Check interface version to confirm firmware is loaded and running */
-+	if (dmcu->dmcu_version.interface_version == 0)
-+		return false;
-+
-+	/* Wait until microcontroller is ready to process interrupt */
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
-+
-+	/* Set initialized ramping boundary value */
-+	REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF);
-+
-+	/* Set command to initialize microcontroller */
-+	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
-+			MCP_INIT_DMCU);
-+
-+	/* Notify microcontroller of new command */
-+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-+
-+	/* Ensure command has been executed before continuing */
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
-+
-+	// Check state is initialized
-+	dcn10_get_dmcu_state(dmcu);
-+
-+	// If microcontroller is not in running state, fail
-+	if (dmcu->dmcu_state != DMCU_RUNNING)
-+		return false;
-+
-+	return true;
-+}
-+
-+static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
-+		unsigned int start_offset,
-+		const char *src,
-+		unsigned int bytes)
-+{
-+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
-+	unsigned int count = 0;
-+
-+	/* If microcontroller is not running, do nothing */
-+	if (dmcu->dmcu_state != DMCU_RUNNING)
-+		return false;
-+
-+	/* Enable write access to IRAM */
-+	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
-+			IRAM_HOST_ACCESS_EN, 1,
-+			IRAM_WR_ADDR_AUTO_INC, 1);
-+
-+	REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
-+
-+	REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
-+
-+	for (count = 0; count < bytes; count++)
-+		REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
-+
-+	/* Disable write access to IRAM to allow dynamic sleep state */
-+	REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
-+			IRAM_HOST_ACCESS_EN, 0,
-+			IRAM_WR_ADDR_AUTO_INC, 0);
-+
-+	/* Wait until microcontroller is ready to process interrupt */
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
-+
-+	/* Set command to signal IRAM is loaded and to initialize IRAM */
-+	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
-+			MCP_INIT_IRAM);
-+
-+	/* Notify microcontroller of new command */
-+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-+
-+	/* Ensure command has been executed before continuing */
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
-+
-+	return true;
-+}
-+
-+static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
-+{
-+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
-+
-+	uint32_t psr_state_offset = 0xf0;
-+
-+	/* If microcontroller is not running, do nothing */
-+	if (dmcu->dmcu_state != DMCU_RUNNING)
-+		return;
-+
-+	/* Enable write access to IRAM */
-+	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
-+
-+	REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
-+
-+	/* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
-+	REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
-+
-+	/* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
-+	*psr_state = REG_READ(DMCU_IRAM_RD_DATA);
-+
-+	/* Disable write access to IRAM after finished using IRAM
-+	 * in order to allow dynamic sleep state
-+	 */
-+	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
-+}
-+
-+static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
-+{
-+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
-+	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
-+	unsigned int dmcu_wait_reg_ready_interval = 100;
-+
-+	unsigned int retryCount;
-+	uint32_t psr_state = 0;
-+
-+	/* If microcontroller is not running, do nothing */
-+	if (dmcu->dmcu_state != DMCU_RUNNING)
-+		return;
-+
-+	/* waitDMCUReadyForCmd */
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
-+				dmcu_wait_reg_ready_interval,
-+				dmcu_max_retry_on_wait_reg_ready);
-+
-+	/* setDMCUParam_Cmd */
-+	if (enable)
-+		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
-+				PSR_ENABLE);
-+	else
-+		REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
-+				PSR_EXIT);
-+
-+	/* notifyDMCUMsg */
-+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-+
-+	/* Below loops 1000 x 500us = 500 ms.
-+	 *  Exit PSR may need to wait 1-2 frames to power up. Timeout after at
-+	 *  least a few frames. Should never hit the max retry assert below.
-+	 */
-+	if (wait == true) {
-+	for (retryCount = 0; retryCount <= 1000; retryCount++) {
-+		dcn10_get_dmcu_psr_state(dmcu, &psr_state);
-+		if (enable) {
-+			if (psr_state != 0)
-+				break;
-+		} else {
-+			if (psr_state == 0)
-+				break;
-+		}
-+		udelay(500);
-+	}
-+
-+	/* assert if max retry hit */
-+	ASSERT(retryCount <= 1000);
-+	}
-+}
-+
-+static void dcn10_dmcu_setup_psr(struct dmcu *dmcu,
-+		struct dc_link *link,
-+		struct psr_context *psr_context)
-+{
-+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
-+
-+	unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
-+	unsigned int dmcu_wait_reg_ready_interval = 100;
-+
-+	union dce_dmcu_psr_config_data_reg1 masterCmdData1;
-+	union dce_dmcu_psr_config_data_reg2 masterCmdData2;
-+	union dce_dmcu_psr_config_data_reg3 masterCmdData3;
-+
-+	/* If microcontroller is not running, do nothing */
-+	if (dmcu->dmcu_state != DMCU_RUNNING)
-+		return;
-+
-+	link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
-+			psr_context->psrExitLinkTrainingRequired);
-+
-+	/* Enable static screen interrupts for PSR supported display */
-+	/* Disable the interrupt coming from other displays. */
-+	REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
-+			STATIC_SCREEN1_INT_TO_UC_EN, 0,
-+			STATIC_SCREEN2_INT_TO_UC_EN, 0,
-+			STATIC_SCREEN3_INT_TO_UC_EN, 0,
-+			STATIC_SCREEN4_INT_TO_UC_EN, 0);
-+
-+	switch (psr_context->controllerId) {
-+	/* Driver uses case 1 for unconfigured */
-+	case 1:
-+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-+				STATIC_SCREEN1_INT_TO_UC_EN, 1);
-+		break;
-+	case 2:
-+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-+				STATIC_SCREEN2_INT_TO_UC_EN, 1);
-+		break;
-+	case 3:
-+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-+				STATIC_SCREEN3_INT_TO_UC_EN, 1);
-+		break;
-+	case 4:
-+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-+				STATIC_SCREEN4_INT_TO_UC_EN, 1);
-+		break;
-+	case 5:
-+		/* CZ/NL only has 4 CRTC!!
-+		 * really valid.
-+		 * There is no interrupt enable mask for these instances.
-+		 */
-+		break;
-+	case 6:
-+		/* CZ/NL only has 4 CRTC!!
-+		 * These are here because they are defined in HW regspec,
-+		 * but not really valid. There is no interrupt enable mask
-+		 * for these instances.
-+		 */
-+		break;
-+	default:
-+		REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
-+				STATIC_SCREEN1_INT_TO_UC_EN, 1);
-+		break;
-+	}
-+
-+	link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
-+			psr_context->sdpTransmitLineNumDeadline);
-+
-+	if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)
-+		REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
-+
-+	/* waitDMCUReadyForCmd */
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
-+			dmcu_wait_reg_ready_interval,
-+			dmcu_max_retry_on_wait_reg_ready);
-+
-+	/* setDMCUParam_PSRHostConfigData */
-+	masterCmdData1.u32All = 0;
-+	masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
-+	masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
-+	masterCmdData1.bits.rfb_update_auto_en =
-+			psr_context->rfb_update_auto_en;
-+	masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
-+	masterCmdData1.bits.dcp_sel = psr_context->controllerId;
-+	masterCmdData1.bits.phy_type  = psr_context->phyType;
-+	masterCmdData1.bits.frame_cap_ind =
-+			psr_context->psrFrameCaptureIndicationReq;
-+	masterCmdData1.bits.aux_chan = psr_context->channel;
-+	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
-+	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
-+					masterCmdData1.u32All);
-+
-+	masterCmdData2.u32All = 0;
-+	masterCmdData2.bits.dig_fe = psr_context->engineId;
-+	masterCmdData2.bits.dig_be = psr_context->transmitterId;
-+	masterCmdData2.bits.skip_wait_for_pll_lock =
-+			psr_context->skipPsrWaitForPllLock;
-+	masterCmdData2.bits.frame_delay = psr_context->frame_delay;
-+	masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
-+	masterCmdData2.bits.num_of_controllers =
-+			psr_context->numberOfControllers;
-+	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
-+			masterCmdData2.u32All);
-+
-+	masterCmdData3.u32All = 0;
-+	masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
-+	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
-+			masterCmdData3.u32All);
-+
-+	/* setDMCUParam_Cmd */
-+	REG_UPDATE(MASTER_COMM_CMD_REG,
-+			MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
-+
-+	/* notifyDMCUMsg */
-+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-+}
-+
-+static void dcn10_psr_wait_loop(
-+	struct dmcu *dmcu,
-+	unsigned int wait_loop_number)
-+{
-+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
-+	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
-+
-+	/* If microcontroller is not running, do nothing */
-+	if (dmcu->dmcu_state != DMCU_RUNNING)
-+		return;
-+
-+	if (wait_loop_number != 0) {
-+	/* waitDMCUReadyForCmd */
-+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
-+
-+	masterCmdData1.u32 = 0;
-+	masterCmdData1.bits.wait_loop = wait_loop_number;
-+	cached_wait_loop_number = wait_loop_number;
-+	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
-+
-+	/* setDMCUParam_Cmd */
-+	REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
-+
-+	/* notifyDMCUMsg */
-+	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-+	}
-+}
-+
-+static void dcn10_get_psr_wait_loop(unsigned int *psr_wait_loop_number)
-+{
-+	*psr_wait_loop_number = cached_wait_loop_number;
-+	return;
-+}
-+
-+#endif
-+
-+static const struct dmcu_funcs dce_funcs = {
-+	.dmcu_init = dce_dmcu_init,
-+	.load_iram = dce_dmcu_load_iram,
-+	.set_psr_enable = dce_dmcu_set_psr_enable,
-+	.setup_psr = dce_dmcu_setup_psr,
-+	.get_psr_state = dce_get_dmcu_psr_state,
-+	.set_psr_wait_loop = dce_psr_wait_loop,
-+	.get_psr_wait_loop = dce_get_psr_wait_loop
-+};
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+static const struct dmcu_funcs dcn10_funcs = {
-+	.dmcu_init = dcn10_dmcu_init,
-+	.load_iram = dcn10_dmcu_load_iram,
-+	.set_psr_enable = dcn10_dmcu_set_psr_enable,
-+	.setup_psr = dcn10_dmcu_setup_psr,
-+	.get_psr_state = dcn10_get_dmcu_psr_state,
-+	.set_psr_wait_loop = dcn10_psr_wait_loop,
-+	.get_psr_wait_loop = dcn10_get_psr_wait_loop
-+};
-+#endif
-+
-+static void dce_dmcu_construct(
-+	struct dce_dmcu *dmcu_dce,
-+	struct dc_context *ctx,
-+	const struct dce_dmcu_registers *regs,
-+	const struct dce_dmcu_shift *dmcu_shift,
-+	const struct dce_dmcu_mask *dmcu_mask)
-+{
-+	struct dmcu *base = &dmcu_dce->base;
-+
-+	base->ctx = ctx;
-+	base->funcs = &dce_funcs;
-+
-+	dmcu_dce->regs = regs;
-+	dmcu_dce->dmcu_shift = dmcu_shift;
-+	dmcu_dce->dmcu_mask = dmcu_mask;
-+}
-+
-+struct dmcu *dce_dmcu_create(
-+	struct dc_context *ctx,
-+	const struct dce_dmcu_registers *regs,
-+	const struct dce_dmcu_shift *dmcu_shift,
-+	const struct dce_dmcu_mask *dmcu_mask)
-+{
-+	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
-+
-+	if (dmcu_dce == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dce_dmcu_construct(
-+		dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
-+
-+	dmcu_dce->base.funcs = &dce_funcs;
-+
-+	return &dmcu_dce->base;
-+}
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+struct dmcu *dcn10_dmcu_create(
-+	struct dc_context *ctx,
-+	const struct dce_dmcu_registers *regs,
-+	const struct dce_dmcu_shift *dmcu_shift,
-+	const struct dce_dmcu_mask *dmcu_mask)
-+{
-+	struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
-+
-+	if (dmcu_dce == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dce_dmcu_construct(
-+		dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
-+
-+	dmcu_dce->base.funcs = &dcn10_funcs;
-+
-+	return &dmcu_dce->base;
-+}
-+#endif
-+
-+void dce_dmcu_destroy(struct dmcu **dmcu)
-+{
-+	struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
-+
-+	kfree(dmcu_dce);
-+	*dmcu = NULL;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h.0130~	2017-12-14 06:39:58.416903568 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h	2017-12-14 06:39:58.416903568 +0100
-@@ -0,0 +1,228 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+
-+#ifndef _DCE_DMCU_H_
-+#define _DCE_DMCU_H_
-+
-+#include "dmcu.h"
-+
-+#define DMCU_COMMON_REG_LIST_DCE_BASE() \
-+	SR(DMCU_CTRL), \
-+	SR(DMCU_STATUS), \
-+	SR(DMCU_RAM_ACCESS_CTRL), \
-+	SR(DMCU_IRAM_WR_CTRL), \
-+	SR(DMCU_IRAM_WR_DATA), \
-+	SR(MASTER_COMM_DATA_REG1), \
-+	SR(MASTER_COMM_DATA_REG2), \
-+	SR(MASTER_COMM_DATA_REG3), \
-+	SR(MASTER_COMM_CMD_REG), \
-+	SR(MASTER_COMM_CNTL_REG), \
-+	SR(DMCU_IRAM_RD_CTRL), \
-+	SR(DMCU_IRAM_RD_DATA), \
-+	SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
-+	SR(SMU_INTERRUPT_CONTROL), \
-+	SR(DC_DMCU_SCRATCH)
-+
-+#define DMCU_DCE110_COMMON_REG_LIST() \
-+	DMCU_COMMON_REG_LIST_DCE_BASE(), \
-+	SR(DCI_MEM_PWR_STATUS)
-+
-+#define DMCU_DCN10_REG_LIST()\
-+	DMCU_COMMON_REG_LIST_DCE_BASE(), \
-+	SR(DMU_MEM_PWR_CNTL)
-+
-+#define DMCU_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+#define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
-+	DMCU_SF(DMCU_CTRL, \
-+			DMCU_ENABLE, mask_sh), \
-+	DMCU_SF(DMCU_STATUS, \
-+			UC_IN_STOP_MODE, mask_sh), \
-+	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
-+			IRAM_HOST_ACCESS_EN, mask_sh), \
-+	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
-+			IRAM_WR_ADDR_AUTO_INC, mask_sh), \
-+	DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
-+			IRAM_RD_ADDR_AUTO_INC, mask_sh), \
-+	DMCU_SF(MASTER_COMM_CMD_REG, \
-+			MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
-+	DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
-+	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
-+			STATIC_SCREEN1_INT_TO_UC_EN, mask_sh), \
-+	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
-+			STATIC_SCREEN2_INT_TO_UC_EN, mask_sh), \
-+	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
-+			STATIC_SCREEN3_INT_TO_UC_EN, mask_sh), \
-+	DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
-+			STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \
-+	DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
-+
-+#define DMCU_MASK_SH_LIST_DCE110(mask_sh) \
-+	DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
-+	DMCU_SF(DCI_MEM_PWR_STATUS, \
-+		DMCU_IRAM_MEM_PWR_STATE, mask_sh)
-+
-+#define DMCU_MASK_SH_LIST_DCN10(mask_sh) \
-+	DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
-+	DMCU_SF(DMU_MEM_PWR_CNTL, \
-+			DMCU_IRAM_MEM_PWR_STATE, mask_sh)
-+
-+#define DMCU_REG_FIELD_LIST(type) \
-+	type DMCU_IRAM_MEM_PWR_STATE; \
-+	type IRAM_HOST_ACCESS_EN; \
-+	type IRAM_WR_ADDR_AUTO_INC; \
-+	type IRAM_RD_ADDR_AUTO_INC; \
-+	type DMCU_ENABLE; \
-+	type UC_IN_STOP_MODE; \
-+	type MASTER_COMM_CMD_REG_BYTE0; \
-+	type MASTER_COMM_INTERRUPT; \
-+	type DPHY_RX_FAST_TRAINING_CAPABLE; \
-+	type DPHY_LOAD_BS_COUNT; \
-+	type STATIC_SCREEN1_INT_TO_UC_EN; \
-+	type STATIC_SCREEN2_INT_TO_UC_EN; \
-+	type STATIC_SCREEN3_INT_TO_UC_EN; \
-+	type STATIC_SCREEN4_INT_TO_UC_EN; \
-+	type DP_SEC_GSP0_LINE_NUM; \
-+	type DP_SEC_GSP0_PRIORITY; \
-+	type DC_SMU_INT_ENABLE
-+
-+struct dce_dmcu_shift {
-+	DMCU_REG_FIELD_LIST(uint8_t);
-+};
-+
-+struct dce_dmcu_mask {
-+	DMCU_REG_FIELD_LIST(uint32_t);
-+};
-+
-+struct dce_dmcu_registers {
-+	uint32_t DMCU_CTRL;
-+	uint32_t DMCU_STATUS;
-+	uint32_t DMCU_RAM_ACCESS_CTRL;
-+	uint32_t DCI_MEM_PWR_STATUS;
-+	uint32_t DMU_MEM_PWR_CNTL;
-+	uint32_t DMCU_IRAM_WR_CTRL;
-+	uint32_t DMCU_IRAM_WR_DATA;
-+
-+	uint32_t MASTER_COMM_DATA_REG1;
-+	uint32_t MASTER_COMM_DATA_REG2;
-+	uint32_t MASTER_COMM_DATA_REG3;
-+	uint32_t MASTER_COMM_CMD_REG;
-+	uint32_t MASTER_COMM_CNTL_REG;
-+	uint32_t DMCU_IRAM_RD_CTRL;
-+	uint32_t DMCU_IRAM_RD_DATA;
-+	uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
-+	uint32_t SMU_INTERRUPT_CONTROL;
-+	uint32_t DC_DMCU_SCRATCH;
-+};
-+
-+struct dce_dmcu {
-+	struct dmcu base;
-+	const struct dce_dmcu_registers *regs;
-+	const struct dce_dmcu_shift *dmcu_shift;
-+	const struct dce_dmcu_mask *dmcu_mask;
-+};
-+
-+/*******************************************************************
-+ *   MASTER_COMM_DATA_REG1   Bit position    Data
-+ *                           7:0	            hyst_frames[7:0]
-+ *                           14:8	        hyst_lines[6:0]
-+ *                           15	            RFB_UPDATE_AUTO_EN
-+ *                           18:16	        phy_num[2:0]
-+ *                           21:19	        dcp_sel[2:0]
-+ *                           22	            phy_type
-+ *                           23	            frame_cap_ind
-+ *                           26:24	        aux_chan[2:0]
-+ *                           30:27	        aux_repeat[3:0]
-+ *                           31:31	        reserved[31:31]
-+ ******************************************************************/
-+union dce_dmcu_psr_config_data_reg1 {
-+	struct {
-+		unsigned int timehyst_frames:8;    /*[7:0]*/
-+		unsigned int hyst_lines:7;         /*[14:8]*/
-+		unsigned int rfb_update_auto_en:1; /*[15:15]*/
-+		unsigned int dp_port_num:3;        /*[18:16]*/
-+		unsigned int dcp_sel:3;            /*[21:19]*/
-+		unsigned int phy_type:1;           /*[22:22]*/
-+		unsigned int frame_cap_ind:1;      /*[23:23]*/
-+		unsigned int aux_chan:3;           /*[26:24]*/
-+		unsigned int aux_repeat:4;         /*[30:27]*/
-+		unsigned int reserved:1;           /*[31:31]*/
-+	} bits;
-+	unsigned int u32All;
-+};
-+
-+/*******************************************************************
-+ *   MASTER_COMM_DATA_REG2
-+ *******************************************************************/
-+union dce_dmcu_psr_config_data_reg2 {
-+	struct {
-+		unsigned int dig_fe:3;                  /*[2:0]*/
-+		unsigned int dig_be:3;                  /*[5:3]*/
-+		unsigned int skip_wait_for_pll_lock:1;  /*[6:6]*/
-+		unsigned int reserved:9;                /*[15:7]*/
-+		unsigned int frame_delay:8;             /*[23:16]*/
-+		unsigned int smu_phy_id:4;              /*[27:24]*/
-+		unsigned int num_of_controllers:4;      /*[31:28]*/
-+	} bits;
-+	unsigned int u32All;
-+};
-+
-+/*******************************************************************
-+ *   MASTER_COMM_DATA_REG3
-+ *******************************************************************/
-+union dce_dmcu_psr_config_data_reg3 {
-+	struct {
-+		unsigned int psr_level:16;      /*[15:0]*/
-+		unsigned int link_rate:4;       /*[19:16]*/
-+		unsigned int reserved:12;       /*[31:20]*/
-+	} bits;
-+	unsigned int u32All;
-+};
-+
-+union dce_dmcu_psr_config_data_wait_loop_reg1 {
-+	struct {
-+		unsigned int wait_loop:16; /* [15:0] */
-+		unsigned int reserved:16; /* [31:16] */
-+	} bits;
-+	unsigned int u32;
-+};
-+
-+struct dmcu *dce_dmcu_create(
-+	struct dc_context *ctx,
-+	const struct dce_dmcu_registers *regs,
-+	const struct dce_dmcu_shift *dmcu_shift,
-+	const struct dce_dmcu_mask *dmcu_mask);
-+
-+struct dmcu *dcn10_dmcu_create(
-+	struct dc_context *ctx,
-+	const struct dce_dmcu_registers *regs,
-+	const struct dce_dmcu_shift *dmcu_shift,
-+	const struct dce_dmcu_mask *dmcu_mask);
-+
-+void dce_dmcu_destroy(struct dmcu **dmcu);
-+
-+#endif /* _DCE_ABM_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c.0130~	2017-12-14 06:39:58.416903568 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c	2017-12-14 06:39:58.416903568 +0100
-@@ -0,0 +1,209 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dce_hwseq.h"
-+#include "reg_helper.h"
-+#include "hw_sequencer.h"
-+#include "core_types.h"
-+
-+#define CTX \
-+	hws->ctx
-+#define REG(reg)\
-+	hws->regs->reg
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	hws->shifts->field_name, hws->masks->field_name
-+
-+void dce_enable_fe_clock(struct dce_hwseq *hws,
-+		unsigned int fe_inst, bool enable)
-+{
-+	REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst],
-+			DCFE_CLOCK_ENABLE, enable);
-+}
-+
-+void dce_pipe_control_lock(struct dc *dc,
-+		struct pipe_ctx *pipe,
-+		bool lock)
-+{
-+	uint32_t lock_val = lock ? 1 : 0;
-+	uint32_t dcp_grph, scl, blnd, update_lock_mode, val;
-+	struct dce_hwseq *hws = dc->hwseq;
-+
-+	/* Not lock pipe when blank */
-+	if (lock && pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
-+		return;
-+
-+	val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx],
-+			BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
-+			BLND_SCL_V_UPDATE_LOCK, &scl,
-+			BLND_BLND_V_UPDATE_LOCK, &blnd,
-+			BLND_V_UPDATE_LOCK_MODE, &update_lock_mode);
-+
-+	dcp_grph = lock_val;
-+	scl = lock_val;
-+	blnd = lock_val;
-+	update_lock_mode = lock_val;
-+
-+	REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val,
-+			BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph,
-+			BLND_SCL_V_UPDATE_LOCK, scl);
-+
-+	if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0)
-+		REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val,
-+				BLND_BLND_V_UPDATE_LOCK, blnd,
-+				BLND_V_UPDATE_LOCK_MODE, update_lock_mode);
-+
-+	if (hws->wa.blnd_crtc_trigger) {
-+		if (!lock) {
-+			uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->pipe_idx]);
-+			REG_WRITE(CRTC_H_BLANK_START_END[pipe->pipe_idx], value);
-+		}
-+	}
-+}
-+
-+void dce_set_blender_mode(struct dce_hwseq *hws,
-+	unsigned int blnd_inst,
-+	enum blnd_mode mode)
-+{
-+	uint32_t feedthrough = 1;
-+	uint32_t blnd_mode = 0;
-+	uint32_t multiplied_mode = 0;
-+	uint32_t alpha_mode = 2;
-+
-+	switch (mode) {
-+	case BLND_MODE_OTHER_PIPE:
-+		feedthrough = 0;
-+		blnd_mode = 1;
-+		alpha_mode = 0;
-+		break;
-+	case BLND_MODE_BLENDING:
-+		feedthrough = 0;
-+		blnd_mode = 2;
-+		alpha_mode = 0;
-+		multiplied_mode = 1;
-+		break;
-+	case BLND_MODE_CURRENT_PIPE:
-+	default:
-+		if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||
-+				blnd_inst == 0)
-+			feedthrough = 0;
-+		break;
-+	}
-+
-+	REG_UPDATE(BLND_CONTROL[blnd_inst],
-+		BLND_MODE, blnd_mode);
-+
-+	if (hws->masks->BLND_ALPHA_MODE != 0) {
-+		REG_UPDATE_3(BLND_CONTROL[blnd_inst],
-+			BLND_FEEDTHROUGH_EN, feedthrough,
-+			BLND_ALPHA_MODE, alpha_mode,
-+			BLND_MULTIPLIED_MODE, multiplied_mode);
-+	}
-+}
-+
-+
-+static void dce_disable_sram_shut_down(struct dce_hwseq *hws)
-+{
-+	if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))
-+		REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL,
-+				DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
-+}
-+
-+static void dce_underlay_clock_enable(struct dce_hwseq *hws)
-+{
-+	/* todo: why do we need this at boot? is dce_enable_fe_clock enough? */
-+	if (REG(DCFEV_CLOCK_CONTROL))
-+		REG_UPDATE(DCFEV_CLOCK_CONTROL,
-+				DCFEV_CLOCK_ENABLE, 1);
-+}
-+
-+static void enable_hw_base_light_sleep(void)
-+{
-+	/* TODO: implement */
-+}
-+
-+static void disable_sw_manual_control_light_sleep(void)
-+{
-+	/* TODO: implement */
-+}
-+
-+void dce_clock_gating_power_up(struct dce_hwseq *hws,
-+		bool enable)
-+{
-+	if (enable) {
-+		enable_hw_base_light_sleep();
-+		disable_sw_manual_control_light_sleep();
-+	} else {
-+		dce_disable_sram_shut_down(hws);
-+		dce_underlay_clock_enable(hws);
-+	}
-+}
-+
-+void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
-+		struct clock_source *clk_src,
-+		unsigned int tg_inst)
-+{
-+	if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO || clk_src->dp_clk_src) {
-+		REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
-+				DP_DTO0_ENABLE, 1);
-+
-+	} else if (clk_src->id >= CLOCK_SOURCE_COMBO_PHY_PLL0) {
-+		uint32_t rate_source = clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0;
-+
-+		REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
-+				PHYPLL_PIXEL_RATE_SOURCE, rate_source,
-+				PIXEL_RATE_PLL_SOURCE, 0);
-+
-+		REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
-+				DP_DTO0_ENABLE, 0);
-+
-+	} else if (clk_src->id <= CLOCK_SOURCE_ID_PLL2) {
-+		uint32_t rate_source = clk_src->id - CLOCK_SOURCE_ID_PLL0;
-+
-+		REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst],
-+				PIXEL_RATE_SOURCE, rate_source,
-+				DP_DTO0_ENABLE, 0);
-+
-+		if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))
-+			REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
-+					PIXEL_RATE_PLL_SOURCE, 1);
-+	} else {
-+		DC_ERR("Unknown clock source. clk_src id: %d, TG_inst: %d",
-+		       clk_src->id, tg_inst);
-+	}
-+}
-+
-+/* Only use LUT for 8 bit formats */
-+bool dce_use_lut(const struct dc_plane_state *plane_state)
-+{
-+	switch (plane_state->format) {
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
-+		return true;
-+	default:
-+		return false;
-+	}
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h.0130~	2017-12-14 06:39:58.416903568 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h	2017-12-14 06:39:58.416903568 +0100
-@@ -0,0 +1,622 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DCE_HWSEQ_H__
-+#define __DCE_HWSEQ_H__
-+
-+#include "hw_sequencer.h"
-+
-+#define BL_REG_LIST()\
-+	SR(LVTMA_PWRSEQ_CNTL), \
-+	SR(LVTMA_PWRSEQ_STATE)
-+
-+#define HWSEQ_DCEF_REG_LIST_DCE8() \
-+	.DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \
-+	.DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \
-+	.DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \
-+	.DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \
-+	.DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \
-+	.DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL
-+
-+#define HWSEQ_DCEF_REG_LIST() \
-+	SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
-+	SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
-+	SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
-+	SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
-+	SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
-+	SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
-+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
-+
-+#define HWSEQ_BLND_REG_LIST() \
-+	SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
-+	SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
-+	SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
-+	SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
-+	SRII(BLND_V_UPDATE_LOCK, BLND, 4), \
-+	SRII(BLND_V_UPDATE_LOCK, BLND, 5), \
-+	SRII(BLND_CONTROL, BLND, 0), \
-+	SRII(BLND_CONTROL, BLND, 1), \
-+	SRII(BLND_CONTROL, BLND, 2), \
-+	SRII(BLND_CONTROL, BLND, 3), \
-+	SRII(BLND_CONTROL, BLND, 4), \
-+	SRII(BLND_CONTROL, BLND, 5)
-+
-+#define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
-+	SRII(PIXEL_RATE_CNTL, blk, 0), \
-+	SRII(PIXEL_RATE_CNTL, blk, 1), \
-+	SRII(PIXEL_RATE_CNTL, blk, 2), \
-+	SRII(PIXEL_RATE_CNTL, blk, 3), \
-+	SRII(PIXEL_RATE_CNTL, blk, 4), \
-+	SRII(PIXEL_RATE_CNTL, blk, 5)
-+
-+#define HWSEQ_PHYPLL_REG_LIST(blk) \
-+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
-+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \
-+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \
-+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
-+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
-+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
-+
-+#define HWSEQ_DCE11_REG_LIST_BASE() \
-+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
-+	SR(DCFEV_CLOCK_CONTROL), \
-+	SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
-+	SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
-+	SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
-+	SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
-+	SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
-+	SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
-+	SRII(BLND_CONTROL, BLND, 0),\
-+	SRII(BLND_CONTROL, BLND, 1),\
-+	SR(BLNDV_CONTROL),\
-+	HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\
-+	BL_REG_LIST()
-+
-+#define HWSEQ_DCE8_REG_LIST() \
-+	HWSEQ_DCEF_REG_LIST_DCE8(), \
-+	HWSEQ_BLND_REG_LIST(), \
-+	HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\
-+	BL_REG_LIST()
-+
-+#define HWSEQ_DCE10_REG_LIST() \
-+	HWSEQ_DCEF_REG_LIST(), \
-+	HWSEQ_BLND_REG_LIST(), \
-+	HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
-+	BL_REG_LIST()
-+
-+#define HWSEQ_ST_REG_LIST() \
-+	HWSEQ_DCE11_REG_LIST_BASE(), \
-+	.DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \
-+	.CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \
-+	.BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \
-+	.BLND_CONTROL[2] = mmBLNDV_CONTROL
-+
-+#define HWSEQ_CZ_REG_LIST() \
-+	HWSEQ_DCE11_REG_LIST_BASE(), \
-+	SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
-+	SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
-+	SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
-+	SRII(BLND_CONTROL, BLND, 2), \
-+	.DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \
-+	.CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \
-+	.BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \
-+	.BLND_CONTROL[3] = mmBLNDV_CONTROL
-+
-+#define HWSEQ_DCE120_REG_LIST() \
-+	HWSEQ_DCE10_REG_LIST(), \
-+	HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
-+	HWSEQ_PHYPLL_REG_LIST(CRTC), \
-+	SR(DCHUB_FB_LOCATION),\
-+	SR(DCHUB_AGP_BASE),\
-+	SR(DCHUB_AGP_BOT),\
-+	SR(DCHUB_AGP_TOP), \
-+	BL_REG_LIST()
-+
-+#define HWSEQ_DCE112_REG_LIST() \
-+	HWSEQ_DCE10_REG_LIST(), \
-+	HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
-+	HWSEQ_PHYPLL_REG_LIST(CRTC), \
-+	BL_REG_LIST()
-+
-+#define HWSEQ_DCN_REG_LIST()\
-+	SRII(DCHUBP_CNTL, HUBP, 0), \
-+	SRII(DCHUBP_CNTL, HUBP, 1), \
-+	SRII(DCHUBP_CNTL, HUBP, 2), \
-+	SRII(DCHUBP_CNTL, HUBP, 3), \
-+	SRII(HUBP_CLK_CNTL, HUBP, 0), \
-+	SRII(HUBP_CLK_CNTL, HUBP, 1), \
-+	SRII(HUBP_CLK_CNTL, HUBP, 2), \
-+	SRII(HUBP_CLK_CNTL, HUBP, 3), \
-+	SRII(DPP_CONTROL, DPP_TOP, 0), \
-+	SRII(DPP_CONTROL, DPP_TOP, 1), \
-+	SRII(DPP_CONTROL, DPP_TOP, 2), \
-+	SRII(DPP_CONTROL, DPP_TOP, 3), \
-+	SRII(OPP_PIPE_CONTROL, OPP_PIPE, 0), \
-+	SRII(OPP_PIPE_CONTROL, OPP_PIPE, 1), \
-+	SRII(OPP_PIPE_CONTROL, OPP_PIPE, 2), \
-+	SRII(OPP_PIPE_CONTROL, OPP_PIPE, 3), \
-+	SR(REFCLK_CNTL), \
-+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
-+	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
-+	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
-+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
-+	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
-+	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
-+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
-+	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
-+	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
-+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
-+	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
-+	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
-+	SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
-+	SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
-+	SR(DCHUBBUB_ARB_SAT_LEVEL),\
-+	SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
-+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
-+	SR(DCHUBBUB_TEST_DEBUG_INDEX), \
-+	SR(DCHUBBUB_TEST_DEBUG_DATA), \
-+	SR(DIO_MEM_PWR_CTRL), \
-+	SR(DCCG_GATE_DISABLE_CNTL), \
-+	SR(DCCG_GATE_DISABLE_CNTL2), \
-+	SR(DCFCLK_CNTL),\
-+	SR(DCFCLK_CNTL), \
-+	/* todo:  get these from GVM instead of reading registers ourselves */\
-+	MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
-+	MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
-+	MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
-+	MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
-+	MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
-+	MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
-+	MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
-+	MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
-+	MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
-+	MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
-+	MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
-+	MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
-+
-+#define HWSEQ_SR_WATERMARK_REG_LIST()\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)
-+
-+#define HWSEQ_DCN1_REG_LIST()\
-+	HWSEQ_DCN_REG_LIST(), \
-+	HWSEQ_SR_WATERMARK_REG_LIST(), \
-+	HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
-+	HWSEQ_PHYPLL_REG_LIST(OTG), \
-+	SR(DCHUBBUB_SDPIF_FB_TOP),\
-+	SR(DCHUBBUB_SDPIF_FB_BASE),\
-+	SR(DCHUBBUB_SDPIF_FB_OFFSET),\
-+	SR(DCHUBBUB_SDPIF_AGP_BASE),\
-+	SR(DCHUBBUB_SDPIF_AGP_BOT),\
-+	SR(DCHUBBUB_SDPIF_AGP_TOP),\
-+	SR(DOMAIN0_PG_CONFIG), \
-+	SR(DOMAIN1_PG_CONFIG), \
-+	SR(DOMAIN2_PG_CONFIG), \
-+	SR(DOMAIN3_PG_CONFIG), \
-+	SR(DOMAIN4_PG_CONFIG), \
-+	SR(DOMAIN5_PG_CONFIG), \
-+	SR(DOMAIN6_PG_CONFIG), \
-+	SR(DOMAIN7_PG_CONFIG), \
-+	SR(DOMAIN0_PG_STATUS), \
-+	SR(DOMAIN1_PG_STATUS), \
-+	SR(DOMAIN2_PG_STATUS), \
-+	SR(DOMAIN3_PG_STATUS), \
-+	SR(DOMAIN4_PG_STATUS), \
-+	SR(DOMAIN5_PG_STATUS), \
-+	SR(DOMAIN6_PG_STATUS), \
-+	SR(DOMAIN7_PG_STATUS), \
-+	SR(D1VGA_CONTROL), \
-+	SR(D2VGA_CONTROL), \
-+	SR(D3VGA_CONTROL), \
-+	SR(D4VGA_CONTROL), \
-+	SR(DC_IP_REQUEST_CNTL), \
-+	BL_REG_LIST()
-+
-+struct dce_hwseq_registers {
-+
-+		/* Backlight registers */
-+	uint32_t LVTMA_PWRSEQ_CNTL;
-+	uint32_t LVTMA_PWRSEQ_STATE;
-+
-+	uint32_t DCFE_CLOCK_CONTROL[6];
-+	uint32_t DCFEV_CLOCK_CONTROL;
-+	uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;
-+	uint32_t BLND_V_UPDATE_LOCK[6];
-+	uint32_t BLND_CONTROL[6];
-+	uint32_t BLNDV_CONTROL;
-+	uint32_t CRTC_H_BLANK_START_END[6];
-+	uint32_t PIXEL_RATE_CNTL[6];
-+	uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
-+	/*DCHUB*/
-+	uint32_t DCHUB_FB_LOCATION;
-+	uint32_t DCHUB_AGP_BASE;
-+	uint32_t DCHUB_AGP_BOT;
-+	uint32_t DCHUB_AGP_TOP;
-+
-+	uint32_t DCHUBP_CNTL[4];
-+	uint32_t HUBP_CLK_CNTL[4];
-+	uint32_t DPP_CONTROL[4];
-+	uint32_t OPP_PIPE_CONTROL[4];
-+	uint32_t REFCLK_CNTL;
-+	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
-+	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
-+	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
-+	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
-+	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
-+	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
-+	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
-+	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
-+	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
-+	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
-+	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
-+	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
-+	uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
-+	uint32_t DCHUBBUB_ARB_SAT_LEVEL;
-+	uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
-+	uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
-+	uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
-+	uint32_t DCHUBBUB_TEST_DEBUG_INDEX;
-+	uint32_t DCHUBBUB_TEST_DEBUG_DATA;
-+	uint32_t DCHUBBUB_SDPIF_FB_TOP;
-+	uint32_t DCHUBBUB_SDPIF_FB_BASE;
-+	uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
-+	uint32_t DCHUBBUB_SDPIF_AGP_BASE;
-+	uint32_t DCHUBBUB_SDPIF_AGP_BOT;
-+	uint32_t DCHUBBUB_SDPIF_AGP_TOP;
-+	uint32_t DC_IP_REQUEST_CNTL;
-+	uint32_t DOMAIN0_PG_CONFIG;
-+	uint32_t DOMAIN1_PG_CONFIG;
-+	uint32_t DOMAIN2_PG_CONFIG;
-+	uint32_t DOMAIN3_PG_CONFIG;
-+	uint32_t DOMAIN4_PG_CONFIG;
-+	uint32_t DOMAIN5_PG_CONFIG;
-+	uint32_t DOMAIN6_PG_CONFIG;
-+	uint32_t DOMAIN7_PG_CONFIG;
-+	uint32_t DOMAIN0_PG_STATUS;
-+	uint32_t DOMAIN1_PG_STATUS;
-+	uint32_t DOMAIN2_PG_STATUS;
-+	uint32_t DOMAIN3_PG_STATUS;
-+	uint32_t DOMAIN4_PG_STATUS;
-+	uint32_t DOMAIN5_PG_STATUS;
-+	uint32_t DOMAIN6_PG_STATUS;
-+	uint32_t DOMAIN7_PG_STATUS;
-+	uint32_t DIO_MEM_PWR_CTRL;
-+	uint32_t DCCG_GATE_DISABLE_CNTL;
-+	uint32_t DCCG_GATE_DISABLE_CNTL2;
-+	uint32_t DCFCLK_CNTL;
-+	uint32_t MICROSECOND_TIME_BASE_DIV;
-+	uint32_t MILLISECOND_TIME_BASE_DIV;
-+	uint32_t DISPCLK_FREQ_CHANGE_CNTL;
-+	uint32_t RBBMIF_TIMEOUT_DIS;
-+	uint32_t RBBMIF_TIMEOUT_DIS_2;
-+	uint32_t DENTIST_DISPCLK_CNTL;
-+	uint32_t DCHUBBUB_CRC_CTRL;
-+	uint32_t DPP_TOP0_DPP_CRC_CTRL;
-+	uint32_t DPP_TOP0_DPP_CRC_VAL_R_G;
-+	uint32_t DPP_TOP0_DPP_CRC_VAL_B_A;
-+	uint32_t MPC_CRC_CTRL;
-+	uint32_t MPC_CRC_RESULT_GB;
-+	uint32_t MPC_CRC_RESULT_C;
-+	uint32_t MPC_CRC_RESULT_AR;
-+	uint32_t D1VGA_CONTROL;
-+	uint32_t D2VGA_CONTROL;
-+	uint32_t D3VGA_CONTROL;
-+	uint32_t D4VGA_CONTROL;
-+	/* MMHUB registers. read only. temporary hack */
-+	uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
-+	uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
-+	uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32;
-+	uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32;
-+	uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32;
-+	uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32;
-+	uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32;
-+	uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32;
-+	uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
-+	uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
-+	uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR;
-+	uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR;
-+};
-+ /* set field name */
-+#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
-+	.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
-+
-+#define HWS_SF1(blk_name, reg_name, field_name, post_fix)\
-+	.field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix
-+
-+
-+#define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
-+	HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
-+	SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
-+
-+#define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\
-+	HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
-+	HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
-+	HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
-+	HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\
-+	HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\
-+	HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\
-+	HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\
-+	HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
-+	HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
-+
-+#define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\
-+	HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\
-+	HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
-+
-+#define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\
-+	HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
-+	HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
-+
-+#define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
-+	.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
-+	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
-+	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
-+	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
-+	HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
-+	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
-+	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
-+	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
-+
-+#define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
-+	HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
-+	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
-+	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \
-+	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
-+	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
-+
-+#define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
-+	HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
-+	SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
-+	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
-+	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
-+	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
-+
-+#define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
-+	HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
-+	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
-+	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
-+	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
-+
-+#define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
-+	SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
-+	SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
-+	SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
-+	SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
-+	SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \
-+	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
-+	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
-+
-+#define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
-+	HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
-+	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
-+	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
-+	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\
-+	HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \
-+	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
-+	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
-+
-+#define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
-+	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
-+	HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
-+	HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \
-+	HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \
-+	HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
-+	HWS_SF(OPP_PIPE0_, OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh),\
-+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
-+	HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
-+	HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
-+	HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
-+	HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
-+	HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \
-+	HWS_SF(, DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \
-+	HWS_SF(, DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
-+	HWS_SF(, DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \
-+	HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh)
-+
-+#define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\
-+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
-+	HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \
-+	HWS_SF(, DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \
-+	HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
-+	HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
-+	HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
-+	HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
-+	HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \
-+	HWS_SF(DPP_TOP0_, DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh), \
-+	/* todo:  get these from GVM instead of reading registers ourselves */\
-+	HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
-+	HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
-+	HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
-+	HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
-+	HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\
-+	HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\
-+	HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\
-+	HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\
-+	HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\
-+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
-+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
-+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
-+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
-+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
-+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
-+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
-+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
-+	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
-+	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
-+	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
-+	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
-+	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
-+	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
-+	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
-+	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
-+	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
-+	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
-+	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
-+	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
-+	HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
-+	HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
-+	HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
-+	HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
-+	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
-+	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
-+	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
-+
-+#define HWSEQ_REG_FIELD_LIST(type) \
-+	type DCFE_CLOCK_ENABLE; \
-+	type DCFEV_CLOCK_ENABLE; \
-+	type DC_MEM_GLOBAL_PWR_REQ_DIS; \
-+	type BLND_DCP_GRPH_V_UPDATE_LOCK; \
-+	type BLND_SCL_V_UPDATE_LOCK; \
-+	type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \
-+	type BLND_BLND_V_UPDATE_LOCK; \
-+	type BLND_V_UPDATE_LOCK_MODE; \
-+	type BLND_FEEDTHROUGH_EN; \
-+	type BLND_ALPHA_MODE; \
-+	type BLND_MODE; \
-+	type BLND_MULTIPLIED_MODE; \
-+	type DP_DTO0_ENABLE; \
-+	type PIXEL_RATE_SOURCE; \
-+	type PHYPLL_PIXEL_RATE_SOURCE; \
-+	type PIXEL_RATE_PLL_SOURCE; \
-+	/* todo:  get these from GVM instead of reading registers ourselves */\
-+	type PAGE_DIRECTORY_ENTRY_HI32;\
-+	type PAGE_DIRECTORY_ENTRY_LO32;\
-+	type LOGICAL_PAGE_NUMBER_HI4;\
-+	type LOGICAL_PAGE_NUMBER_LO32;\
-+	type PHYSICAL_PAGE_ADDR_HI4;\
-+	type PHYSICAL_PAGE_ADDR_LO32;\
-+	type PHYSICAL_PAGE_NUMBER_MSB;\
-+	type PHYSICAL_PAGE_NUMBER_LSB;\
-+	type LOGICAL_ADDR; \
-+	type ENABLE_L1_TLB;\
-+	type SYSTEM_ACCESS_MODE;\
-+	type LVTMA_BLON;\
-+	type LVTMA_PWRSEQ_TARGET_STATE_R;
-+
-+#define HWSEQ_DCN_REG_FIELD_LIST(type) \
-+	type HUBP_VTG_SEL; \
-+	type HUBP_CLOCK_ENABLE; \
-+	type DPP_CLOCK_ENABLE; \
-+	type DPPCLK_RATE_CONTROL; \
-+	type SDPIF_FB_TOP;\
-+	type SDPIF_FB_BASE;\
-+	type SDPIF_FB_OFFSET;\
-+	type SDPIF_AGP_BASE;\
-+	type SDPIF_AGP_BOT;\
-+	type SDPIF_AGP_TOP;\
-+	type FB_TOP;\
-+	type FB_BASE;\
-+	type FB_OFFSET;\
-+	type AGP_BASE;\
-+	type AGP_BOT;\
-+	type AGP_TOP;\
-+	type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
-+	type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
-+	type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
-+	type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
-+	type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
-+	type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\
-+	type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\
-+	type DCHUBBUB_ARB_SAT_LEVEL;\
-+	type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
-+	type OPP_PIPE_CLOCK_EN;\
-+	type IP_REQUEST_EN; \
-+	type DOMAIN0_POWER_FORCEON; \
-+	type DOMAIN0_POWER_GATE; \
-+	type DOMAIN1_POWER_FORCEON; \
-+	type DOMAIN1_POWER_GATE; \
-+	type DOMAIN2_POWER_FORCEON; \
-+	type DOMAIN2_POWER_GATE; \
-+	type DOMAIN3_POWER_FORCEON; \
-+	type DOMAIN3_POWER_GATE; \
-+	type DOMAIN4_POWER_FORCEON; \
-+	type DOMAIN4_POWER_GATE; \
-+	type DOMAIN5_POWER_FORCEON; \
-+	type DOMAIN5_POWER_GATE; \
-+	type DOMAIN6_POWER_FORCEON; \
-+	type DOMAIN6_POWER_GATE; \
-+	type DOMAIN7_POWER_FORCEON; \
-+	type DOMAIN7_POWER_GATE; \
-+	type DOMAIN0_PGFSM_PWR_STATUS; \
-+	type DOMAIN1_PGFSM_PWR_STATUS; \
-+	type DOMAIN2_PGFSM_PWR_STATUS; \
-+	type DOMAIN3_PGFSM_PWR_STATUS; \
-+	type DOMAIN4_PGFSM_PWR_STATUS; \
-+	type DOMAIN5_PGFSM_PWR_STATUS; \
-+	type DOMAIN6_PGFSM_PWR_STATUS; \
-+	type DOMAIN7_PGFSM_PWR_STATUS; \
-+	type DCFCLK_GATE_DIS; \
-+	type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
-+	type DENTIST_DPPCLK_WDIVIDER;
-+
-+struct dce_hwseq_shift {
-+	HWSEQ_REG_FIELD_LIST(uint8_t)
-+	HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
-+};
-+
-+struct dce_hwseq_mask {
-+	HWSEQ_REG_FIELD_LIST(uint32_t)
-+	HWSEQ_DCN_REG_FIELD_LIST(uint32_t)
-+};
-+
-+
-+enum blnd_mode {
-+	BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
-+	BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
-+	BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
-+};
-+
-+void dce_enable_fe_clock(struct dce_hwseq *hwss,
-+		unsigned int inst, bool enable);
-+
-+void dce_pipe_control_lock(struct dc *dc,
-+		struct pipe_ctx *pipe,
-+		bool lock);
-+
-+void dce_set_blender_mode(struct dce_hwseq *hws,
-+	unsigned int blnd_inst, enum blnd_mode mode);
-+
-+void dce_clock_gating_power_up(struct dce_hwseq *hws,
-+		bool enable);
-+
-+void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
-+		struct clock_source *clk_src,
-+		unsigned int tg_inst);
-+
-+bool dce_use_lut(const struct dc_plane_state *plane_state);
-+#endif   /*__DCE_HWSEQ_H__*/
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c.0130~	2017-12-14 06:39:58.417903569 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c	2017-12-14 06:39:58.417903569 +0100
-@@ -0,0 +1,265 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dce_ipp.h"
-+#include "reg_helper.h"
-+#include "dm_services.h"
-+
-+#define REG(reg) \
-+	(ipp_dce->regs->reg)
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	ipp_dce->ipp_shift->field_name, ipp_dce->ipp_mask->field_name
-+
-+#define CTX \
-+	ipp_dce->base.ctx
-+
-+
-+static void dce_ipp_cursor_set_position(
-+	struct input_pixel_processor *ipp,
-+	const struct dc_cursor_position *position,
-+	const struct dc_cursor_mi_param *param)
-+{
-+	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
-+
-+	/* lock cursor registers */
-+	REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);
-+
-+	/* Flag passed in structure differentiates cursor enable/disable. */
-+	/* Update if it differs from cached state. */
-+	REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable);
-+
-+	REG_SET_2(CUR_POSITION, 0,
-+		CURSOR_X_POSITION, position->x,
-+		CURSOR_Y_POSITION, position->y);
-+
-+	REG_SET_2(CUR_HOT_SPOT, 0,
-+		CURSOR_HOT_SPOT_X, position->x_hotspot,
-+		CURSOR_HOT_SPOT_Y, position->y_hotspot);
-+
-+	/* unlock cursor registers */
-+	REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);
-+}
-+
-+static void dce_ipp_cursor_set_attributes(
-+	struct input_pixel_processor *ipp,
-+	const struct dc_cursor_attributes *attributes)
-+{
-+	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
-+	int mode;
-+
-+	/* Lock cursor registers */
-+	REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);
-+
-+	/* Program cursor control */
-+	switch (attributes->color_format) {
-+	case CURSOR_MODE_MONO:
-+		mode = 0;
-+		break;
-+	case CURSOR_MODE_COLOR_1BIT_AND:
-+		mode = 1;
-+		break;
-+	case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
-+		mode = 2;
-+		break;
-+	case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
-+		mode = 3;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER(); /* unsupported */
-+		mode = 0;
-+	}
-+
-+	REG_UPDATE_3(CUR_CONTROL,
-+		CURSOR_MODE, mode,
-+		CURSOR_2X_MAGNIFY, attributes->attribute_flags.bits.ENABLE_MAGNIFICATION,
-+		CUR_INV_TRANS_CLAMP, attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING);
-+
-+	if (attributes->color_format == CURSOR_MODE_MONO) {
-+		REG_SET_3(CUR_COLOR1, 0,
-+			CUR_COLOR1_BLUE, 0,
-+			CUR_COLOR1_GREEN, 0,
-+			CUR_COLOR1_RED, 0);
-+
-+		REG_SET_3(CUR_COLOR2, 0,
-+			CUR_COLOR2_BLUE, 0xff,
-+			CUR_COLOR2_GREEN, 0xff,
-+			CUR_COLOR2_RED, 0xff);
-+	}
-+
-+	/*
-+	 * Program cursor size -- NOTE: HW spec specifies that HW register
-+	 * stores size as (height - 1, width - 1)
-+	 */
-+	REG_SET_2(CUR_SIZE, 0,
-+		CURSOR_WIDTH, attributes->width-1,
-+		CURSOR_HEIGHT, attributes->height-1);
-+
-+	/* Program cursor surface address */
-+	/* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor
-+	 * surface base address in byte. It is 4K byte aligned.
-+	 * The correct way to program cursor surface address is to first write
-+	 * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS
-+	 */
-+	REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0,
-+		CURSOR_SURFACE_ADDRESS_HIGH, attributes->address.high_part);
-+
-+	REG_SET(CUR_SURFACE_ADDRESS, 0,
-+		CURSOR_SURFACE_ADDRESS, attributes->address.low_part);
-+
-+	/* Unlock Cursor registers. */
-+	REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);
-+}
-+
-+
-+static void dce_ipp_program_prescale(struct input_pixel_processor *ipp,
-+				     struct ipp_prescale_params *params)
-+{
-+	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
-+
-+	/* set to bypass mode first before change */
-+	REG_UPDATE(PRESCALE_GRPH_CONTROL,
-+		   GRPH_PRESCALE_BYPASS, 1);
-+
-+	REG_SET_2(PRESCALE_VALUES_GRPH_R, 0,
-+		  GRPH_PRESCALE_SCALE_R, params->scale,
-+		  GRPH_PRESCALE_BIAS_R, params->bias);
-+
-+	REG_SET_2(PRESCALE_VALUES_GRPH_G, 0,
-+		  GRPH_PRESCALE_SCALE_G, params->scale,
-+		  GRPH_PRESCALE_BIAS_G, params->bias);
-+
-+	REG_SET_2(PRESCALE_VALUES_GRPH_B, 0,
-+		  GRPH_PRESCALE_SCALE_B, params->scale,
-+		  GRPH_PRESCALE_BIAS_B, params->bias);
-+
-+	if (params->mode != IPP_PRESCALE_MODE_BYPASS) {
-+		REG_UPDATE(PRESCALE_GRPH_CONTROL,
-+			   GRPH_PRESCALE_BYPASS, 0);
-+
-+		/* If prescale is in use, then legacy lut should be bypassed */
-+		REG_UPDATE(INPUT_GAMMA_CONTROL,
-+			   GRPH_INPUT_GAMMA_MODE, 1);
-+	}
-+}
-+
-+static void dce_ipp_program_input_lut(
-+	struct input_pixel_processor *ipp,
-+	const struct dc_gamma *gamma)
-+{
-+	int i;
-+	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
-+
-+	/* power on LUT memory */
-+	if (REG(DCFE_MEM_PWR_CTRL))
-+		REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1);
-+
-+	/* enable all */
-+	REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7);
-+
-+	/* 256 entry mode */
-+	REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0);
-+
-+	/* LUT-256, unsigned, integer, new u0.12 format */
-+	REG_SET_3(DC_LUT_CONTROL, 0,
-+		DC_LUT_DATA_R_FORMAT, 3,
-+		DC_LUT_DATA_G_FORMAT, 3,
-+		DC_LUT_DATA_B_FORMAT, 3);
-+
-+	/* start from index 0 */
-+	REG_SET(DC_LUT_RW_INDEX, 0,
-+		DC_LUT_RW_INDEX, 0);
-+
-+	for (i = 0; i < gamma->num_entries; i++) {
-+		REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
-+				dal_fixed31_32_round(
-+					gamma->entries.red[i]));
-+		REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
-+				dal_fixed31_32_round(
-+					gamma->entries.green[i]));
-+		REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
-+				dal_fixed31_32_round(
-+					gamma->entries.blue[i]));
-+	}
-+
-+	/* power off LUT memory */
-+	if (REG(DCFE_MEM_PWR_CTRL))
-+		REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0);
-+
-+	/* bypass prescale, enable legacy LUT */
-+	REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
-+	REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
-+}
-+
-+static void dce_ipp_set_degamma(
-+	struct input_pixel_processor *ipp,
-+	enum ipp_degamma_mode mode)
-+{
-+	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
-+	uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;
-+
-+	ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB);
-+
-+	REG_SET_3(DEGAMMA_CONTROL, 0,
-+		  GRPH_DEGAMMA_MODE, degamma_type,
-+		  CURSOR_DEGAMMA_MODE, degamma_type,
-+		  CURSOR2_DEGAMMA_MODE, degamma_type);
-+}
-+
-+static const struct ipp_funcs dce_ipp_funcs = {
-+	.ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes,
-+	.ipp_cursor_set_position = dce_ipp_cursor_set_position,
-+	.ipp_program_prescale = dce_ipp_program_prescale,
-+	.ipp_program_input_lut = dce_ipp_program_input_lut,
-+	.ipp_set_degamma = dce_ipp_set_degamma
-+};
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+void dce_ipp_construct(
-+	struct dce_ipp *ipp_dce,
-+	struct dc_context *ctx,
-+	int inst,
-+	const struct dce_ipp_registers *regs,
-+	const struct dce_ipp_shift *ipp_shift,
-+	const struct dce_ipp_mask *ipp_mask)
-+{
-+	ipp_dce->base.ctx = ctx;
-+	ipp_dce->base.inst = inst;
-+	ipp_dce->base.funcs = &dce_ipp_funcs;
-+
-+	ipp_dce->regs = regs;
-+	ipp_dce->ipp_shift = ipp_shift;
-+	ipp_dce->ipp_mask = ipp_mask;
-+}
-+
-+void dce_ipp_destroy(struct input_pixel_processor **ipp)
-+{
-+	kfree(TO_DCE_IPP(*ipp));
-+	*ipp = NULL;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h.0130~	2017-12-14 06:39:58.417903569 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h	2017-12-14 06:39:58.417903569 +0100
-@@ -0,0 +1,238 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef _DCE_IPP_H_
-+#define _DCE_IPP_H_
-+
-+#include "ipp.h"
-+
-+#define TO_DCE_IPP(ipp)\
-+	container_of(ipp, struct dce_ipp, base)
-+
-+#define IPP_COMMON_REG_LIST_DCE_BASE(id) \
-+	SRI(CUR_UPDATE, DCP, id), \
-+	SRI(CUR_CONTROL, DCP, id), \
-+	SRI(CUR_POSITION, DCP, id), \
-+	SRI(CUR_HOT_SPOT, DCP, id), \
-+	SRI(CUR_COLOR1, DCP, id), \
-+	SRI(CUR_COLOR2, DCP, id), \
-+	SRI(CUR_SIZE, DCP, id), \
-+	SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \
-+	SRI(CUR_SURFACE_ADDRESS, DCP, id), \
-+	SRI(PRESCALE_GRPH_CONTROL, DCP, id), \
-+	SRI(PRESCALE_VALUES_GRPH_R, DCP, id), \
-+	SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \
-+	SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \
-+	SRI(INPUT_GAMMA_CONTROL, DCP, id), \
-+	SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \
-+	SRI(DC_LUT_RW_MODE, DCP, id), \
-+	SRI(DC_LUT_CONTROL, DCP, id), \
-+	SRI(DC_LUT_RW_INDEX, DCP, id), \
-+	SRI(DC_LUT_SEQ_COLOR, DCP, id), \
-+	SRI(DEGAMMA_CONTROL, DCP, id)
-+
-+#define IPP_DCE100_REG_LIST_DCE_BASE(id) \
-+	IPP_COMMON_REG_LIST_DCE_BASE(id), \
-+	SRI(DCFE_MEM_PWR_CTRL, CRTC, id)
-+
-+#define IPP_DCE110_REG_LIST_DCE_BASE(id) \
-+	IPP_COMMON_REG_LIST_DCE_BASE(id), \
-+	SRI(DCFE_MEM_PWR_CTRL, DCFE, id)
-+
-+#define IPP_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+#define IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
-+	IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
-+	IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \
-+	IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \
-+	IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
-+	IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
-+	IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \
-+	IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \
-+	IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
-+	IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
-+	IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
-+	IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \
-+	IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
-+	IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \
-+	IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \
-+	IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
-+	IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \
-+	IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
-+	IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
-+	IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
-+	IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
-+	IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \
-+	IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \
-+	IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \
-+	IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \
-+	IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
-+	IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
-+	IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
-+	IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
-+	IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
-+	IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
-+	IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \
-+	IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \
-+	IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \
-+	IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \
-+	IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \
-+	IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \
-+	IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)
-+
-+#define IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
-+	IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
-+	IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh)
-+
-+#define IPP_DCE120_MASK_SH_LIST_SOC_BASE(mask_sh) \
-+	IPP_SF(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
-+	IPP_SF(DCP0_CUR_CONTROL, CURSOR_EN, mask_sh), \
-+	IPP_SF(DCP0_CUR_CONTROL, CURSOR_MODE, mask_sh), \
-+	IPP_SF(DCP0_CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
-+	IPP_SF(DCP0_CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
-+	IPP_SF(DCP0_CUR_POSITION, CURSOR_X_POSITION, mask_sh), \
-+	IPP_SF(DCP0_CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \
-+	IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
-+	IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
-+	IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
-+	IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \
-+	IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
-+	IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \
-+	IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \
-+	IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
-+	IPP_SF(DCP0_CUR_SIZE, CURSOR_WIDTH, mask_sh), \
-+	IPP_SF(DCP0_CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
-+	IPP_SF(DCP0_CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
-+	IPP_SF(DCP0_CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
-+	IPP_SF(DCP0_PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
-+	IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \
-+	IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \
-+	IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \
-+	IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \
-+	IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
-+	IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
-+	IPP_SF(DCP0_INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
-+	IPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \
-+	IPP_SF(DCP0_DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
-+	IPP_SF(DCP0_DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
-+	IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
-+	IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \
-+	IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \
-+	IPP_SF(DCP0_DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \
-+	IPP_SF(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \
-+	IPP_SF(DCP0_DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \
-+	IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \
-+	IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)
-+
-+#define IPP_REG_FIELD_LIST(type) \
-+	type CURSOR_UPDATE_LOCK; \
-+	type CURSOR_EN; \
-+	type CURSOR_X_POSITION; \
-+	type CURSOR_Y_POSITION; \
-+	type CURSOR_HOT_SPOT_X; \
-+	type CURSOR_HOT_SPOT_Y; \
-+	type CURSOR_MODE; \
-+	type CURSOR_2X_MAGNIFY; \
-+	type CUR_INV_TRANS_CLAMP; \
-+	type CUR_COLOR1_BLUE; \
-+	type CUR_COLOR1_GREEN; \
-+	type CUR_COLOR1_RED; \
-+	type CUR_COLOR2_BLUE; \
-+	type CUR_COLOR2_GREEN; \
-+	type CUR_COLOR2_RED; \
-+	type CURSOR_WIDTH; \
-+	type CURSOR_HEIGHT; \
-+	type CURSOR_SURFACE_ADDRESS_HIGH; \
-+	type CURSOR_SURFACE_ADDRESS; \
-+	type GRPH_PRESCALE_BYPASS; \
-+	type GRPH_PRESCALE_SCALE_R; \
-+	type GRPH_PRESCALE_BIAS_R; \
-+	type GRPH_PRESCALE_SCALE_G; \
-+	type GRPH_PRESCALE_BIAS_G; \
-+	type GRPH_PRESCALE_SCALE_B; \
-+	type GRPH_PRESCALE_BIAS_B; \
-+	type GRPH_INPUT_GAMMA_MODE; \
-+	type DCP_LUT_MEM_PWR_DIS; \
-+	type DC_LUT_WRITE_EN_MASK; \
-+	type DC_LUT_RW_MODE; \
-+	type DC_LUT_DATA_R_FORMAT; \
-+	type DC_LUT_DATA_G_FORMAT; \
-+	type DC_LUT_DATA_B_FORMAT; \
-+	type DC_LUT_RW_INDEX; \
-+	type DC_LUT_SEQ_COLOR; \
-+	type GRPH_DEGAMMA_MODE; \
-+	type CURSOR_DEGAMMA_MODE; \
-+	type CURSOR2_DEGAMMA_MODE
-+
-+struct dce_ipp_shift {
-+	IPP_REG_FIELD_LIST(uint8_t);
-+};
-+
-+struct dce_ipp_mask {
-+	IPP_REG_FIELD_LIST(uint32_t);
-+};
-+
-+struct dce_ipp_registers {
-+	uint32_t CUR_UPDATE;
-+	uint32_t CUR_CONTROL;
-+	uint32_t CUR_POSITION;
-+	uint32_t CUR_HOT_SPOT;
-+	uint32_t CUR_COLOR1;
-+	uint32_t CUR_COLOR2;
-+	uint32_t CUR_SIZE;
-+	uint32_t CUR_SURFACE_ADDRESS_HIGH;
-+	uint32_t CUR_SURFACE_ADDRESS;
-+	uint32_t PRESCALE_GRPH_CONTROL;
-+	uint32_t PRESCALE_VALUES_GRPH_R;
-+	uint32_t PRESCALE_VALUES_GRPH_G;
-+	uint32_t PRESCALE_VALUES_GRPH_B;
-+	uint32_t INPUT_GAMMA_CONTROL;
-+	uint32_t DCFE_MEM_PWR_CTRL;
-+	uint32_t DC_LUT_WRITE_EN_MASK;
-+	uint32_t DC_LUT_RW_MODE;
-+	uint32_t DC_LUT_CONTROL;
-+	uint32_t DC_LUT_RW_INDEX;
-+	uint32_t DC_LUT_SEQ_COLOR;
-+	uint32_t DEGAMMA_CONTROL;
-+};
-+
-+struct dce_ipp {
-+	struct input_pixel_processor base;
-+	const struct dce_ipp_registers *regs;
-+	const struct dce_ipp_shift *ipp_shift;
-+	const struct dce_ipp_mask *ipp_mask;
-+};
-+
-+void dce_ipp_construct(struct dce_ipp *ipp_dce,
-+	struct dc_context *ctx,
-+	int inst,
-+	const struct dce_ipp_registers *regs,
-+	const struct dce_ipp_shift *ipp_shift,
-+	const struct dce_ipp_mask *ipp_mask);
-+
-+void dce_ipp_destroy(struct input_pixel_processor **ipp);
-+
-+#endif /* _DCE_IPP_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c.0130~	2017-12-14 06:39:58.417903569 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c	2017-12-14 06:39:58.417903569 +0100
-@@ -0,0 +1,1375 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "reg_helper.h"
-+
-+#include "core_types.h"
-+#include "link_encoder.h"
-+#include "dce_link_encoder.h"
-+#include "stream_encoder.h"
-+#include "i2caux_interface.h"
-+#include "dc_bios_types.h"
-+
-+#include "gpio_service_interface.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+#include "dce/dce_11_0_enum.h"
-+
-+#ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT
-+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa
-+#endif
-+
-+#ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK
-+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L
-+#endif
-+
-+#ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK
-+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK  0x10000000L
-+#endif
-+
-+#ifndef HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT
-+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT  0x1c
-+#endif
-+
-+#define CTX \
-+	enc110->base.ctx
-+
-+#define REG(reg)\
-+	(enc110->link_regs->reg)
-+
-+#define AUX_REG(reg)\
-+	(enc110->aux_regs->reg)
-+
-+#define HPD_REG(reg)\
-+	(enc110->hpd_regs->reg)
-+
-+#define DEFAULT_AUX_MAX_DATA_SIZE 16
-+#define AUX_MAX_DEFER_WRITE_RETRY 20
-+/*
-+ * @brief
-+ * Trigger Source Select
-+ * ASIC-dependent, actual values for register programming
-+ */
-+#define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0
-+#define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1
-+#define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2
-+#define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4
-+#define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08
-+#define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10
-+#define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
-+#define DCE110_DIG_FE_SOURCE_SELECT_DIGG 0x40
-+
-+/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
-+#define TMDS_MIN_PIXEL_CLOCK 25000
-+/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
-+#define TMDS_MAX_PIXEL_CLOCK 165000
-+/* For current ASICs pixel clock - 600MHz */
-+#define MAX_ENCODER_CLOCK 600000
-+
-+enum {
-+	DP_MST_UPDATE_MAX_RETRY = 50
-+};
-+
-+#define DIG_REG(reg)\
-+	(reg + enc110->offsets.dig)
-+
-+#define DP_REG(reg)\
-+	(reg + enc110->offsets.dp)
-+
-+static const struct link_encoder_funcs dce110_lnk_enc_funcs = {
-+	.validate_output_with_stream =
-+		dce110_link_encoder_validate_output_with_stream,
-+	.hw_init = dce110_link_encoder_hw_init,
-+	.setup = dce110_link_encoder_setup,
-+	.enable_tmds_output = dce110_link_encoder_enable_tmds_output,
-+	.enable_dp_output = dce110_link_encoder_enable_dp_output,
-+	.enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
-+	.disable_output = dce110_link_encoder_disable_output,
-+	.dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
-+	.dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
-+	.update_mst_stream_allocation_table =
-+		dce110_link_encoder_update_mst_stream_allocation_table,
-+	.psr_program_dp_dphy_fast_training =
-+			dce110_psr_program_dp_dphy_fast_training,
-+	.psr_program_secondary_packet = dce110_psr_program_secondary_packet,
-+	.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
-+	.enable_hpd = dce110_link_encoder_enable_hpd,
-+	.disable_hpd = dce110_link_encoder_disable_hpd,
-+	.destroy = dce110_link_encoder_destroy
-+};
-+
-+static enum bp_result link_transmitter_control(
-+	struct dce110_link_encoder *enc110,
-+	struct bp_transmitter_control *cntl)
-+{
-+	enum bp_result result;
-+	struct dc_bios *bp = enc110->base.ctx->dc_bios;
-+
-+	result = bp->funcs->transmitter_control(bp, cntl);
-+
-+	return result;
-+}
-+
-+static void enable_phy_bypass_mode(
-+	struct dce110_link_encoder *enc110,
-+	bool enable)
-+{
-+	/* This register resides in DP back end block;
-+	 * transmitter is used for the offset */
-+
-+	REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
-+
-+}
-+
-+static void disable_prbs_symbols(
-+	struct dce110_link_encoder *enc110,
-+	bool disable)
-+{
-+	/* This register resides in DP back end block;
-+	 * transmitter is used for the offset */
-+
-+	REG_UPDATE_4(DP_DPHY_CNTL,
-+			DPHY_ATEST_SEL_LANE0, disable,
-+			DPHY_ATEST_SEL_LANE1, disable,
-+			DPHY_ATEST_SEL_LANE2, disable,
-+			DPHY_ATEST_SEL_LANE3, disable);
-+}
-+
-+static void disable_prbs_mode(
-+	struct dce110_link_encoder *enc110)
-+{
-+	REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
-+}
-+
-+static void program_pattern_symbols(
-+	struct dce110_link_encoder *enc110,
-+	uint16_t pattern_symbols[8])
-+{
-+	/* This register resides in DP back end block;
-+	 * transmitter is used for the offset */
-+
-+	REG_SET_3(DP_DPHY_SYM0, 0,
-+			DPHY_SYM1, pattern_symbols[0],
-+			DPHY_SYM2, pattern_symbols[1],
-+			DPHY_SYM3, pattern_symbols[2]);
-+
-+	/* This register resides in DP back end block;
-+	 * transmitter is used for the offset */
-+
-+	REG_SET_3(DP_DPHY_SYM1, 0,
-+			DPHY_SYM4, pattern_symbols[3],
-+			DPHY_SYM5, pattern_symbols[4],
-+			DPHY_SYM6, pattern_symbols[5]);
-+
-+	/* This register resides in DP back end block;
-+	 * transmitter is used for the offset */
-+
-+	REG_SET_2(DP_DPHY_SYM2, 0,
-+			DPHY_SYM7, pattern_symbols[6],
-+			DPHY_SYM8, pattern_symbols[7]);
-+}
-+
-+static void set_dp_phy_pattern_d102(
-+	struct dce110_link_encoder *enc110)
-+{
-+	/* Disable PHY Bypass mode to setup the test pattern */
-+	enable_phy_bypass_mode(enc110, false);
-+
-+	/* For 10-bit PRBS or debug symbols
-+	 * please use the following sequence: */
-+
-+	/* Enable debug symbols on the lanes */
-+
-+	disable_prbs_symbols(enc110, true);
-+
-+	/* Disable PRBS mode */
-+	disable_prbs_mode(enc110);
-+
-+	/* Program debug symbols to be output */
-+	{
-+		uint16_t pattern_symbols[8] = {
-+			0x2AA, 0x2AA, 0x2AA, 0x2AA,
-+			0x2AA, 0x2AA, 0x2AA, 0x2AA
-+		};
-+
-+		program_pattern_symbols(enc110, pattern_symbols);
-+	}
-+
-+	/* Enable phy bypass mode to enable the test pattern */
-+
-+	enable_phy_bypass_mode(enc110, true);
-+}
-+
-+static void set_link_training_complete(
-+	struct dce110_link_encoder *enc110,
-+	bool complete)
-+{
-+	/* This register resides in DP back end block;
-+	 * transmitter is used for the offset */
-+
-+	REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
-+
-+}
-+
-+void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
-+	struct link_encoder *enc,
-+	uint32_t index)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	/* Write Training Pattern */
-+
-+	REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
-+
-+	/* Set HW Register Training Complete to false */
-+
-+	set_link_training_complete(enc110, false);
-+
-+	/* Disable PHY Bypass mode to output Training Pattern */
-+
-+	enable_phy_bypass_mode(enc110, false);
-+
-+	/* Disable PRBS mode */
-+	disable_prbs_mode(enc110);
-+}
-+
-+static void setup_panel_mode(
-+	struct dce110_link_encoder *enc110,
-+	enum dp_panel_mode panel_mode)
-+{
-+	uint32_t value;
-+
-+	ASSERT(REG(DP_DPHY_INTERNAL_CTRL));
-+	value = REG_READ(DP_DPHY_INTERNAL_CTRL);
-+
-+	switch (panel_mode) {
-+	case DP_PANEL_MODE_EDP:
-+		value = 0x1;
-+		break;
-+	case DP_PANEL_MODE_SPECIAL:
-+		value = 0x11;
-+		break;
-+	default:
-+		value = 0x0;
-+		break;
-+	}
-+
-+	REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
-+}
-+
-+static void set_dp_phy_pattern_symbol_error(
-+	struct dce110_link_encoder *enc110)
-+{
-+	/* Disable PHY Bypass mode to setup the test pattern */
-+	enable_phy_bypass_mode(enc110, false);
-+
-+	/* program correct panel mode*/
-+	setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
-+
-+	/* A PRBS23 pattern is used for most DP electrical measurements. */
-+
-+	/* Enable PRBS symbols on the lanes */
-+	disable_prbs_symbols(enc110, false);
-+
-+	/* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
-+	REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
-+			DPHY_PRBS_SEL, 1,
-+			DPHY_PRBS_EN, 1);
-+
-+	/* Enable phy bypass mode to enable the test pattern */
-+	enable_phy_bypass_mode(enc110, true);
-+}
-+
-+static void set_dp_phy_pattern_prbs7(
-+	struct dce110_link_encoder *enc110)
-+{
-+	/* Disable PHY Bypass mode to setup the test pattern */
-+	enable_phy_bypass_mode(enc110, false);
-+
-+	/* A PRBS7 pattern is used for most DP electrical measurements. */
-+
-+	/* Enable PRBS symbols on the lanes */
-+	disable_prbs_symbols(enc110, false);
-+
-+	/* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
-+	REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
-+			DPHY_PRBS_SEL, 0,
-+			DPHY_PRBS_EN, 1);
-+
-+	/* Enable phy bypass mode to enable the test pattern */
-+	enable_phy_bypass_mode(enc110, true);
-+}
-+
-+static void set_dp_phy_pattern_80bit_custom(
-+	struct dce110_link_encoder *enc110,
-+	const uint8_t *pattern)
-+{
-+	/* Disable PHY Bypass mode to setup the test pattern */
-+	enable_phy_bypass_mode(enc110, false);
-+
-+	/* Enable debug symbols on the lanes */
-+
-+	disable_prbs_symbols(enc110, true);
-+
-+	/* Enable PHY bypass mode to enable the test pattern */
-+	/* TODO is it really needed ? */
-+
-+	enable_phy_bypass_mode(enc110, true);
-+
-+	/* Program 80 bit custom pattern */
-+	{
-+		uint16_t pattern_symbols[8];
-+
-+		pattern_symbols[0] =
-+			((pattern[1] & 0x03) << 8) | pattern[0];
-+		pattern_symbols[1] =
-+			((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
-+		pattern_symbols[2] =
-+			((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
-+		pattern_symbols[3] =
-+			(pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
-+		pattern_symbols[4] =
-+			((pattern[6] & 0x03) << 8) | pattern[5];
-+		pattern_symbols[5] =
-+			((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
-+		pattern_symbols[6] =
-+			((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
-+		pattern_symbols[7] =
-+			(pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
-+
-+		program_pattern_symbols(enc110, pattern_symbols);
-+	}
-+
-+	/* Enable phy bypass mode to enable the test pattern */
-+
-+	enable_phy_bypass_mode(enc110, true);
-+}
-+
-+static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
-+	struct dce110_link_encoder *enc110,
-+	unsigned int cp2520_pattern)
-+{
-+
-+	/* previously there is a register DP_HBR2_EYE_PATTERN
-+	 * that is enabled to get the pattern.
-+	 * But it does not work with the latest spec change,
-+	 * so we are programming the following registers manually.
-+	 *
-+	 * The following settings have been confirmed
-+	 * by Nick Chorney and Sandra Liu */
-+
-+	/* Disable PHY Bypass mode to setup the test pattern */
-+
-+	enable_phy_bypass_mode(enc110, false);
-+
-+	/* Setup DIG encoder in DP SST mode */
-+	enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT);
-+
-+	/* ensure normal panel mode. */
-+	setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
-+
-+	/* no vbid after BS (SR)
-+	 * DP_LINK_FRAMING_CNTL changed history Sandra Liu
-+	 * 11000260 / 11000104 / 110000FC */
-+	REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
-+			DP_IDLE_BS_INTERVAL, 0xFC,
-+			DP_VBID_DISABLE, 1,
-+			DP_VID_ENHANCED_FRAME_MODE, 1);
-+
-+	/* swap every BS with SR */
-+	REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
-+
-+	/* select cp2520 patterns */
-+	if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
-+		REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
-+				DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
-+	else
-+		/* pre-DCE11 can only generate CP2520 pattern 2 */
-+		ASSERT(cp2520_pattern == 2);
-+
-+	/* set link training complete */
-+	set_link_training_complete(enc110, true);
-+
-+	/* disable video stream */
-+	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
-+
-+	/* Disable PHY Bypass mode to setup the test pattern */
-+	enable_phy_bypass_mode(enc110, false);
-+}
-+
-+static void set_dp_phy_pattern_passthrough_mode(
-+	struct dce110_link_encoder *enc110,
-+	enum dp_panel_mode panel_mode)
-+{
-+	/* program correct panel mode */
-+	setup_panel_mode(enc110, panel_mode);
-+
-+	/* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
-+	 * in case we were doing HBR2 compliance pattern before
-+	 */
-+	REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
-+			DP_IDLE_BS_INTERVAL, 0x2000,
-+			DP_VBID_DISABLE, 0,
-+			DP_VID_ENHANCED_FRAME_MODE, 1);
-+
-+	REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
-+
-+	/* set link training complete */
-+	set_link_training_complete(enc110, true);
-+
-+	/* Disable PHY Bypass mode to setup the test pattern */
-+	enable_phy_bypass_mode(enc110, false);
-+
-+	/* Disable PRBS mode */
-+	disable_prbs_mode(enc110);
-+}
-+
-+/* return value is bit-vector */
-+static uint8_t get_frontend_source(
-+	enum engine_id engine)
-+{
-+	switch (engine) {
-+	case ENGINE_ID_DIGA:
-+		return DCE110_DIG_FE_SOURCE_SELECT_DIGA;
-+	case ENGINE_ID_DIGB:
-+		return DCE110_DIG_FE_SOURCE_SELECT_DIGB;
-+	case ENGINE_ID_DIGC:
-+		return DCE110_DIG_FE_SOURCE_SELECT_DIGC;
-+	case ENGINE_ID_DIGD:
-+		return DCE110_DIG_FE_SOURCE_SELECT_DIGD;
-+	case ENGINE_ID_DIGE:
-+		return DCE110_DIG_FE_SOURCE_SELECT_DIGE;
-+	case ENGINE_ID_DIGF:
-+		return DCE110_DIG_FE_SOURCE_SELECT_DIGF;
-+	case ENGINE_ID_DIGG:
-+		return DCE110_DIG_FE_SOURCE_SELECT_DIGG;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return DCE110_DIG_FE_SOURCE_SELECT_INVALID;
-+	}
-+}
-+
-+static void configure_encoder(
-+	struct dce110_link_encoder *enc110,
-+	const struct dc_link_settings *link_settings)
-+{
-+	/* set number of lanes */
-+
-+	REG_SET(DP_CONFIG, 0,
-+			DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
-+
-+	/* setup scrambler */
-+	REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
-+}
-+
-+static void aux_initialize(
-+	struct dce110_link_encoder *enc110)
-+{
-+	struct dc_context *ctx = enc110->base.ctx;
-+	enum hpd_source_id hpd_source = enc110->base.hpd_source;
-+	uint32_t addr = AUX_REG(AUX_CONTROL);
-+	uint32_t value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL);
-+	set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN);
-+	dm_write_reg(ctx, addr, value);
-+
-+	addr = AUX_REG(AUX_DPHY_RX_CONTROL0);
-+	value = dm_read_reg(ctx, addr);
-+
-+	/* 1/4 window (the maximum allowed) */
-+	set_reg_field_value(value, 1,
-+			AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW);
-+	dm_write_reg(ctx, addr, value);
-+
-+}
-+
-+void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
-+			bool exit_link_training_required)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+
-+	if (exit_link_training_required)
-+		REG_UPDATE(DP_DPHY_FAST_TRAINING,
-+				DPHY_RX_FAST_TRAINING_CAPABLE, 1);
-+	else {
-+		REG_UPDATE(DP_DPHY_FAST_TRAINING,
-+				DPHY_RX_FAST_TRAINING_CAPABLE, 0);
-+		/*In DCE 11, we are able to pre-program a Force SR register
-+		 * to be able to trigger SR symbol after 5 idle patterns
-+		 * transmitted. Upon PSR Exit, DMCU can trigger
-+		 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
-+		 * DPHY_LOAD_BS_COUNT_START and the internal counter
-+		 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
-+		 * replaced by SR symbol once.
-+		 */
-+
-+		REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
-+	}
-+}
-+
-+void dce110_psr_program_secondary_packet(struct link_encoder *enc,
-+			unsigned int sdp_transmit_line_num_deadline)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+
-+	REG_UPDATE_2(DP_SEC_CNTL1,
-+		DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
-+		DP_SEC_GSP0_PRIORITY, 1);
-+}
-+
-+static bool is_dig_enabled(const struct dce110_link_encoder *enc110)
-+{
-+	uint32_t value;
-+
-+	REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
-+	return value;
-+}
-+
-+static void link_encoder_disable(struct dce110_link_encoder *enc110)
-+{
-+	/* reset training pattern */
-+	REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
-+			DPHY_TRAINING_PATTERN_SEL, 0);
-+
-+	/* reset training complete */
-+	REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
-+
-+	/* reset panel mode */
-+	setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
-+}
-+
-+static void hpd_initialize(
-+	struct dce110_link_encoder *enc110)
-+{
-+	/* Associate HPD with DIG_BE */
-+	enum hpd_source_id hpd_source = enc110->base.hpd_source;
-+
-+	REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
-+}
-+
-+bool dce110_link_encoder_validate_dvi_output(
-+	const struct dce110_link_encoder *enc110,
-+	enum signal_type connector_signal,
-+	enum signal_type signal,
-+	const struct dc_crtc_timing *crtc_timing)
-+{
-+	uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
-+
-+	if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
-+		max_pixel_clock *= 2;
-+
-+	/* This handles the case of HDMI downgrade to DVI we don't want to
-+	 * we don't want to cap the pixel clock if the DDI is not DVI.
-+	 */
-+	if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
-+			connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
-+		max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock;
-+
-+	/* DVI only support RGB pixel encoding */
-+	if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
-+		return false;
-+
-+	/*connect DVI via adpater's HDMI connector*/
-+	if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
-+		connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
-+		signal != SIGNAL_TYPE_HDMI_TYPE_A &&
-+		crtc_timing->pix_clk_khz > TMDS_MAX_PIXEL_CLOCK)
-+		return false;
-+	if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
-+		return false;
-+
-+	if (crtc_timing->pix_clk_khz > max_pixel_clock)
-+		return false;
-+
-+	/* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
-+	switch (crtc_timing->display_color_depth) {
-+	case COLOR_DEPTH_666:
-+	case COLOR_DEPTH_888:
-+	break;
-+	case COLOR_DEPTH_101010:
-+	case COLOR_DEPTH_161616:
-+		if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
-+			return false;
-+	break;
-+	default:
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+static bool dce110_link_encoder_validate_hdmi_output(
-+	const struct dce110_link_encoder *enc110,
-+	const struct dc_crtc_timing *crtc_timing,
-+	int adjusted_pix_clk_khz)
-+{
-+	enum dc_color_depth max_deep_color =
-+			enc110->base.features.max_hdmi_deep_color;
-+
-+	if (max_deep_color < crtc_timing->display_color_depth)
-+		return false;
-+
-+	if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
-+		return false;
-+	if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
-+		return false;
-+
-+	if ((adjusted_pix_clk_khz == 0) ||
-+		(adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock))
-+		return false;
-+
-+	/* DCE11 HW does not support 420 */
-+	if (!enc110->base.features.ycbcr420_supported &&
-+			crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
-+		return false;
-+
-+	if (!enc110->base.features.flags.bits.HDMI_6GB_EN &&
-+		adjusted_pix_clk_khz >= 300000)
-+		return false;
-+	return true;
-+}
-+
-+bool dce110_link_encoder_validate_dp_output(
-+	const struct dce110_link_encoder *enc110,
-+	const struct dc_crtc_timing *crtc_timing)
-+{
-+	/* default RGB only */
-+	if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
-+		return true;
-+
-+	if (enc110->base.features.flags.bits.IS_YCBCR_CAPABLE)
-+		return true;
-+
-+	/* for DCE 8.x or later DP Y-only feature,
-+	 * we need ASIC cap + FeatureSupportDPYonly, not support 666 */
-+	if (crtc_timing->flags.Y_ONLY &&
-+		enc110->base.features.flags.bits.IS_YCBCR_CAPABLE &&
-+		crtc_timing->display_color_depth != COLOR_DEPTH_666)
-+		return true;
-+
-+	return false;
-+}
-+
-+void dce110_link_encoder_construct(
-+	struct dce110_link_encoder *enc110,
-+	const struct encoder_init_data *init_data,
-+	const struct encoder_feature_support *enc_features,
-+	const struct dce110_link_enc_registers *link_regs,
-+	const struct dce110_link_enc_aux_registers *aux_regs,
-+	const struct dce110_link_enc_hpd_registers *hpd_regs)
-+{
-+	struct bp_encoder_cap_info bp_cap_info = {0};
-+	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
-+
-+	enc110->base.funcs = &dce110_lnk_enc_funcs;
-+	enc110->base.ctx = init_data->ctx;
-+	enc110->base.id = init_data->encoder;
-+
-+	enc110->base.hpd_source = init_data->hpd_source;
-+	enc110->base.connector = init_data->connector;
-+
-+	enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
-+
-+	enc110->base.features = *enc_features;
-+
-+	enc110->base.transmitter = init_data->transmitter;
-+
-+	/* set the flag to indicate whether driver poll the I2C data pin
-+	 * while doing the DP sink detect
-+	 */
-+
-+/*	if (dal_adapter_service_is_feature_supported(as,
-+		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
-+		enc110->base.features.flags.bits.
-+			DP_SINK_DETECT_POLL_DATA_PIN = true;*/
-+
-+	enc110->base.output_signals =
-+		SIGNAL_TYPE_DVI_SINGLE_LINK |
-+		SIGNAL_TYPE_DVI_DUAL_LINK |
-+		SIGNAL_TYPE_LVDS |
-+		SIGNAL_TYPE_DISPLAY_PORT |
-+		SIGNAL_TYPE_DISPLAY_PORT_MST |
-+		SIGNAL_TYPE_EDP |
-+		SIGNAL_TYPE_HDMI_TYPE_A;
-+
-+	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
-+	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
-+	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
-+	 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
-+	 * Prefer DIG assignment is decided by board design.
-+	 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
-+	 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
-+	 * By this, adding DIGG should not hurt DCE 8.0.
-+	 * This will let DCE 8.1 share DCE 8.0 as much as possible
-+	 */
-+
-+	enc110->link_regs = link_regs;
-+	enc110->aux_regs = aux_regs;
-+	enc110->hpd_regs = hpd_regs;
-+
-+	switch (enc110->base.transmitter) {
-+	case TRANSMITTER_UNIPHY_A:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGA;
-+	break;
-+	case TRANSMITTER_UNIPHY_B:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGB;
-+	break;
-+	case TRANSMITTER_UNIPHY_C:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGC;
-+	break;
-+	case TRANSMITTER_UNIPHY_D:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGD;
-+	break;
-+	case TRANSMITTER_UNIPHY_E:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGE;
-+	break;
-+	case TRANSMITTER_UNIPHY_F:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGF;
-+	break;
-+	case TRANSMITTER_UNIPHY_G:
-+		enc110->base.preferred_engine = ENGINE_ID_DIGG;
-+	break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
-+	}
-+
-+	/* Override features with DCE-specific values */
-+	if (BP_RESULT_OK == bp_funcs->get_encoder_cap_info(
-+			enc110->base.ctx->dc_bios, enc110->base.id,
-+			&bp_cap_info)) {
-+		enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
-+				bp_cap_info.DP_HBR2_EN;
-+		enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
-+				bp_cap_info.DP_HBR3_EN;
-+		enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
-+	}
-+}
-+
-+bool dce110_link_encoder_validate_output_with_stream(
-+	struct link_encoder *enc,
-+	const struct dc_stream_state *stream)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	bool is_valid;
-+
-+	switch (stream->signal) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		is_valid = dce110_link_encoder_validate_dvi_output(
-+			enc110,
-+			stream->sink->link->connector_signal,
-+			stream->signal,
-+			&stream->timing);
-+	break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		is_valid = dce110_link_encoder_validate_hdmi_output(
-+				enc110,
-+				&stream->timing,
-+				stream->phy_pix_clk);
-+	break;
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		is_valid = dce110_link_encoder_validate_dp_output(
-+					enc110, &stream->timing);
-+	break;
-+	case SIGNAL_TYPE_EDP:
-+		is_valid =
-+			(stream->timing.
-+				pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
-+	break;
-+	case SIGNAL_TYPE_VIRTUAL:
-+		is_valid = true;
-+		break;
-+	default:
-+		is_valid = false;
-+	break;
-+	}
-+
-+	return is_valid;
-+}
-+
-+void dce110_link_encoder_hw_init(
-+	struct link_encoder *enc)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result result;
-+
-+	cntl.action = TRANSMITTER_CONTROL_INIT;
-+	cntl.engine_id = ENGINE_ID_UNKNOWN;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.connector_obj_id = enc110->base.connector;
-+	cntl.lanes_number = LANE_COUNT_FOUR;
-+	cntl.coherent = false;
-+	cntl.hpd_sel = enc110->base.hpd_source;
-+
-+	result = link_transmitter_control(enc110, &cntl);
-+
-+	if (result != BP_RESULT_OK) {
-+		dm_logger_write(ctx->logger, LOG_ERROR,
-+			"%s: Failed to execute VBIOS command table!\n",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	if (enc110->base.connector.id == CONNECTOR_ID_LVDS) {
-+		cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
-+
-+		result = link_transmitter_control(enc110, &cntl);
-+
-+		ASSERT(result == BP_RESULT_OK);
-+
-+	}
-+	aux_initialize(enc110);
-+
-+	/* reinitialize HPD.
-+	 * hpd_initialize() will pass DIG_FE id to HW context.
-+	 * All other routine within HW context will use fe_engine_offset
-+	 * as DIG_FE id even caller pass DIG_FE id.
-+	 * So this routine must be called first. */
-+	hpd_initialize(enc110);
-+}
-+
-+void dce110_link_encoder_destroy(struct link_encoder **enc)
-+{
-+	kfree(TO_DCE110_LINK_ENC(*enc));
-+	*enc = NULL;
-+}
-+
-+void dce110_link_encoder_setup(
-+	struct link_encoder *enc,
-+	enum signal_type signal)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+
-+	switch (signal) {
-+	case SIGNAL_TYPE_EDP:
-+	case SIGNAL_TYPE_DISPLAY_PORT:
-+		/* DP SST */
-+		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
-+		break;
-+	case SIGNAL_TYPE_LVDS:
-+		/* LVDS */
-+		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
-+		break;
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		/* TMDS-DVI */
-+		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
-+		break;
-+	case SIGNAL_TYPE_HDMI_TYPE_A:
-+		/* TMDS-HDMI */
-+		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
-+		break;
-+	case SIGNAL_TYPE_DISPLAY_PORT_MST:
-+		/* DP MST */
-+		REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		/* invalid mode ! */
-+		break;
-+	}
-+
-+}
-+
-+/* TODO: still need depth or just pass in adjusted pixel clock? */
-+void dce110_link_encoder_enable_tmds_output(
-+	struct link_encoder *enc,
-+	enum clock_source_id clock_source,
-+	enum dc_color_depth color_depth,
-+	bool hdmi,
-+	bool dual_link,
-+	uint32_t pixel_clock)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result result;
-+
-+	/* Enable the PHY */
-+
-+	cntl.action = TRANSMITTER_CONTROL_ENABLE;
-+	cntl.engine_id = enc->preferred_engine;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.pll_id = clock_source;
-+	if (hdmi) {
-+		cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
-+		cntl.lanes_number = 4;
-+	} else if (dual_link) {
-+		cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
-+		cntl.lanes_number = 8;
-+	} else {
-+		cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
-+		cntl.lanes_number = 4;
-+	}
-+	cntl.hpd_sel = enc110->base.hpd_source;
-+
-+	cntl.pixel_clock = pixel_clock;
-+	cntl.color_depth = color_depth;
-+
-+	result = link_transmitter_control(enc110, &cntl);
-+
-+	if (result != BP_RESULT_OK) {
-+		dm_logger_write(ctx->logger, LOG_ERROR,
-+			"%s: Failed to execute VBIOS command table!\n",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+	}
-+}
-+
-+/* enables DP PHY output */
-+void dce110_link_encoder_enable_dp_output(
-+	struct link_encoder *enc,
-+	const struct dc_link_settings *link_settings,
-+	enum clock_source_id clock_source)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result result;
-+
-+	/* Enable the PHY */
-+
-+	/* number_of_lanes is used for pixel clock adjust,
-+	 * but it's not passed to asic_control.
-+	 * We need to set number of lanes manually.
-+	 */
-+	configure_encoder(enc110, link_settings);
-+
-+	cntl.action = TRANSMITTER_CONTROL_ENABLE;
-+	cntl.engine_id = enc->preferred_engine;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.pll_id = clock_source;
-+	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
-+	cntl.lanes_number = link_settings->lane_count;
-+	cntl.hpd_sel = enc110->base.hpd_source;
-+	cntl.pixel_clock = link_settings->link_rate
-+						* LINK_RATE_REF_FREQ_IN_KHZ;
-+	/* TODO: check if undefined works */
-+	cntl.color_depth = COLOR_DEPTH_UNDEFINED;
-+
-+	result = link_transmitter_control(enc110, &cntl);
-+
-+	if (result != BP_RESULT_OK) {
-+		dm_logger_write(ctx->logger, LOG_ERROR,
-+			"%s: Failed to execute VBIOS command table!\n",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+	}
-+}
-+
-+/* enables DP PHY output in MST mode */
-+void dce110_link_encoder_enable_dp_mst_output(
-+	struct link_encoder *enc,
-+	const struct dc_link_settings *link_settings,
-+	enum clock_source_id clock_source)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result result;
-+
-+	/* Enable the PHY */
-+
-+	/* number_of_lanes is used for pixel clock adjust,
-+	 * but it's not passed to asic_control.
-+	 * We need to set number of lanes manually.
-+	 */
-+	configure_encoder(enc110, link_settings);
-+
-+	cntl.action = TRANSMITTER_CONTROL_ENABLE;
-+	cntl.engine_id = ENGINE_ID_UNKNOWN;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.pll_id = clock_source;
-+	cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
-+	cntl.lanes_number = link_settings->lane_count;
-+	cntl.hpd_sel = enc110->base.hpd_source;
-+	cntl.pixel_clock = link_settings->link_rate
-+						* LINK_RATE_REF_FREQ_IN_KHZ;
-+	/* TODO: check if undefined works */
-+	cntl.color_depth = COLOR_DEPTH_UNDEFINED;
-+
-+	result = link_transmitter_control(enc110, &cntl);
-+
-+	if (result != BP_RESULT_OK) {
-+		dm_logger_write(ctx->logger, LOG_ERROR,
-+			"%s: Failed to execute VBIOS command table!\n",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+	}
-+}
-+/*
-+ * @brief
-+ * Disable transmitter and its encoder
-+ */
-+void dce110_link_encoder_disable_output(
-+	struct link_encoder *enc,
-+	enum signal_type signal)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	struct bp_transmitter_control cntl = { 0 };
-+	enum bp_result result;
-+
-+	if (!is_dig_enabled(enc110)) {
-+		/* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
-+		return;
-+	}
-+	/* Power-down RX and disable GPU PHY should be paired.
-+	 * Disabling PHY without powering down RX may cause
-+	 * symbol lock loss, on which we will get DP Sink interrupt. */
-+
-+	/* There is a case for the DP active dongles
-+	 * where we want to disable the PHY but keep RX powered,
-+	 * for those we need to ignore DP Sink interrupt
-+	 * by checking lane count that has been set
-+	 * on the last do_enable_output(). */
-+
-+	/* disable transmitter */
-+	cntl.action = TRANSMITTER_CONTROL_DISABLE;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.hpd_sel = enc110->base.hpd_source;
-+	cntl.signal = signal;
-+	cntl.connector_obj_id = enc110->base.connector;
-+
-+	result = link_transmitter_control(enc110, &cntl);
-+
-+	if (result != BP_RESULT_OK) {
-+		dm_logger_write(ctx->logger, LOG_ERROR,
-+			"%s: Failed to execute VBIOS command table!\n",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	/* disable encoder */
-+	if (dc_is_dp_signal(signal))
-+		link_encoder_disable(enc110);
-+
-+	/*
-+	 * TODO: Power control cause regression, we should implement
-+	 * it properly, for now just comment it.
-+	 */
-+//	if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
-+//		/* power down eDP panel */
-+//		link_encoder_edp_wait_for_hpd_ready(
-+//				enc,
-+//				enc->connector,
-+//				false);
-+//
-+//		link_encoder_edp_power_control(
-+//				enc, false);
-+//	}
-+}
-+
-+void dce110_link_encoder_dp_set_lane_settings(
-+	struct link_encoder *enc,
-+	const struct link_training_settings *link_settings)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	union dpcd_training_lane_set training_lane_set = { { 0 } };
-+	int32_t lane = 0;
-+	struct bp_transmitter_control cntl = { 0 };
-+
-+	if (!link_settings) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
-+	cntl.transmitter = enc110->base.transmitter;
-+	cntl.connector_obj_id = enc110->base.connector;
-+	cntl.lanes_number = link_settings->link_settings.lane_count;
-+	cntl.hpd_sel = enc110->base.hpd_source;
-+	cntl.pixel_clock = link_settings->link_settings.link_rate *
-+						LINK_RATE_REF_FREQ_IN_KHZ;
-+
-+	for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
-+		/* translate lane settings */
-+
-+		training_lane_set.bits.VOLTAGE_SWING_SET =
-+			link_settings->lane_settings[lane].VOLTAGE_SWING;
-+		training_lane_set.bits.PRE_EMPHASIS_SET =
-+			link_settings->lane_settings[lane].PRE_EMPHASIS;
-+
-+		/* post cursor 2 setting only applies to HBR2 link rate */
-+		if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
-+			/* this is passed to VBIOS
-+			 * to program post cursor 2 level */
-+
-+			training_lane_set.bits.POST_CURSOR2_SET =
-+				link_settings->lane_settings[lane].POST_CURSOR2;
-+		}
-+
-+		cntl.lane_select = lane;
-+		cntl.lane_settings = training_lane_set.raw;
-+
-+		/* call VBIOS table to set voltage swing and pre-emphasis */
-+		link_transmitter_control(enc110, &cntl);
-+	}
-+}
-+
-+/* set DP PHY test and training patterns */
-+void dce110_link_encoder_dp_set_phy_pattern(
-+	struct link_encoder *enc,
-+	const struct encoder_set_dp_phy_pattern_param *param)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+
-+	switch (param->dp_phy_pattern) {
-+	case DP_TEST_PATTERN_TRAINING_PATTERN1:
-+		dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
-+		break;
-+	case DP_TEST_PATTERN_TRAINING_PATTERN2:
-+		dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
-+		break;
-+	case DP_TEST_PATTERN_TRAINING_PATTERN3:
-+		dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
-+		break;
-+	case DP_TEST_PATTERN_TRAINING_PATTERN4:
-+		dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
-+		break;
-+	case DP_TEST_PATTERN_D102:
-+		set_dp_phy_pattern_d102(enc110);
-+		break;
-+	case DP_TEST_PATTERN_SYMBOL_ERROR:
-+		set_dp_phy_pattern_symbol_error(enc110);
-+		break;
-+	case DP_TEST_PATTERN_PRBS7:
-+		set_dp_phy_pattern_prbs7(enc110);
-+		break;
-+	case DP_TEST_PATTERN_80BIT_CUSTOM:
-+		set_dp_phy_pattern_80bit_custom(
-+			enc110, param->custom_pattern);
-+		break;
-+	case DP_TEST_PATTERN_CP2520_1:
-+		set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1);
-+		break;
-+	case DP_TEST_PATTERN_CP2520_2:
-+		set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2);
-+		break;
-+	case DP_TEST_PATTERN_CP2520_3:
-+		set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3);
-+		break;
-+	case DP_TEST_PATTERN_VIDEO_MODE: {
-+		set_dp_phy_pattern_passthrough_mode(
-+			enc110, param->dp_panel_mode);
-+		break;
-+	}
-+
-+	default:
-+		/* invalid phy pattern */
-+		ASSERT_CRITICAL(false);
-+		break;
-+	}
-+}
-+
-+static void fill_stream_allocation_row_info(
-+	const struct link_mst_stream_allocation *stream_allocation,
-+	uint32_t *src,
-+	uint32_t *slots)
-+{
-+	const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
-+
-+	if (stream_enc) {
-+		*src = stream_enc->id;
-+		*slots = stream_allocation->slot_count;
-+	} else {
-+		*src = 0;
-+		*slots = 0;
-+	}
-+}
-+
-+/* programs DP MST VC payload allocation */
-+void dce110_link_encoder_update_mst_stream_allocation_table(
-+	struct link_encoder *enc,
-+	const struct link_mst_stream_allocation_table *table)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	uint32_t value0 = 0;
-+	uint32_t value1 = 0;
-+	uint32_t value2 = 0;
-+	uint32_t slots = 0;
-+	uint32_t src = 0;
-+	uint32_t retries = 0;
-+
-+	/* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
-+
-+	/* --- Set MSE Stream Attribute -
-+	 * Setup VC Payload Table on Tx Side,
-+	 * Issue allocation change trigger
-+	 * to commit payload on both tx and rx side */
-+
-+	/* we should clean-up table each time */
-+
-+	if (table->stream_count >= 1) {
-+		fill_stream_allocation_row_info(
-+			&table->stream_allocations[0],
-+			&src,
-+			&slots);
-+	} else {
-+		src = 0;
-+		slots = 0;
-+	}
-+
-+	REG_UPDATE_2(DP_MSE_SAT0,
-+			DP_MSE_SAT_SRC0, src,
-+			DP_MSE_SAT_SLOT_COUNT0, slots);
-+
-+	if (table->stream_count >= 2) {
-+		fill_stream_allocation_row_info(
-+			&table->stream_allocations[1],
-+			&src,
-+			&slots);
-+	} else {
-+		src = 0;
-+		slots = 0;
-+	}
-+
-+	REG_UPDATE_2(DP_MSE_SAT0,
-+			DP_MSE_SAT_SRC1, src,
-+			DP_MSE_SAT_SLOT_COUNT1, slots);
-+
-+	if (table->stream_count >= 3) {
-+		fill_stream_allocation_row_info(
-+			&table->stream_allocations[2],
-+			&src,
-+			&slots);
-+	} else {
-+		src = 0;
-+		slots = 0;
-+	}
-+
-+	REG_UPDATE_2(DP_MSE_SAT1,
-+			DP_MSE_SAT_SRC2, src,
-+			DP_MSE_SAT_SLOT_COUNT2, slots);
-+
-+	if (table->stream_count >= 4) {
-+		fill_stream_allocation_row_info(
-+			&table->stream_allocations[3],
-+			&src,
-+			&slots);
-+	} else {
-+		src = 0;
-+		slots = 0;
-+	}
-+
-+	REG_UPDATE_2(DP_MSE_SAT1,
-+			DP_MSE_SAT_SRC3, src,
-+			DP_MSE_SAT_SLOT_COUNT3, slots);
-+
-+	/* --- wait for transaction finish */
-+
-+	/* send allocation change trigger (ACT) ?
-+	 * this step first sends the ACT,
-+	 * then double buffers the SAT into the hardware
-+	 * making the new allocation active on the DP MST mode link */
-+
-+
-+	/* DP_MSE_SAT_UPDATE:
-+	 * 0 - No Action
-+	 * 1 - Update SAT with trigger
-+	 * 2 - Update SAT without trigger */
-+
-+	REG_UPDATE(DP_MSE_SAT_UPDATE,
-+			DP_MSE_SAT_UPDATE, 1);
-+
-+	/* wait for update to complete
-+	 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
-+	 * then wait for the transmission
-+	 * of at least 16 MTP headers on immediate local link.
-+	 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
-+	 * a value of 1 indicates that DP MST mode
-+	 * is in the 16 MTP keepout region after a VC has been added.
-+	 * MST stream bandwidth (VC rate) can be configured
-+	 * after this bit is cleared */
-+
-+	do {
-+		udelay(10);
-+
-+		value0 = REG_READ(DP_MSE_SAT_UPDATE);
-+
-+		REG_GET(DP_MSE_SAT_UPDATE,
-+				DP_MSE_SAT_UPDATE, &value1);
-+
-+		REG_GET(DP_MSE_SAT_UPDATE,
-+				DP_MSE_16_MTP_KEEPOUT, &value2);
-+
-+		/* bit field DP_MSE_SAT_UPDATE is set to 1 already */
-+		if (!value1 && !value2)
-+			break;
-+		++retries;
-+	} while (retries < DP_MST_UPDATE_MAX_RETRY);
-+}
-+
-+void dce110_link_encoder_connect_dig_be_to_fe(
-+	struct link_encoder *enc,
-+	enum engine_id engine,
-+	bool connect)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	uint32_t field;
-+
-+	if (engine != ENGINE_ID_UNKNOWN) {
-+
-+		REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
-+
-+		if (connect)
-+			field |= get_frontend_source(engine);
-+		else
-+			field &= ~get_frontend_source(engine);
-+
-+		REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
-+	}
-+}
-+
-+void dce110_link_encoder_enable_hpd(struct link_encoder *enc)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = HPD_REG(DC_HPD_CONTROL);
-+	uint32_t hpd_enable = 0;
-+	uint32_t value = dm_read_reg(ctx, addr);
-+
-+	get_reg_field_value(hpd_enable, DC_HPD_CONTROL, DC_HPD_EN);
-+
-+	if (hpd_enable == 0)
-+		set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN);
-+}
-+
-+void dce110_link_encoder_disable_hpd(struct link_encoder *enc)
-+{
-+	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t addr = HPD_REG(DC_HPD_CONTROL);
-+	uint32_t value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h.0130~	2017-12-14 06:39:58.417903569 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h	2017-12-14 06:39:58.417903569 +0100
-@@ -0,0 +1,267 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_LINK_ENCODER__DCE110_H__
-+#define __DC_LINK_ENCODER__DCE110_H__
-+
-+#include "link_encoder.h"
-+
-+#define TO_DCE110_LINK_ENC(link_encoder)\
-+	container_of(link_encoder, struct dce110_link_encoder, base)
-+
-+/* Not found regs in dce120 spec
-+ * BIOS_SCRATCH_2
-+ * DP_DPHY_INTERNAL_CTRL
-+ */
-+
-+#define AUX_REG_LIST(id)\
-+	SRI(AUX_CONTROL, DP_AUX, id), \
-+	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
-+
-+#define HPD_REG_LIST(id)\
-+	SRI(DC_HPD_CONTROL, HPD, id)
-+
-+#define LE_COMMON_REG_LIST_BASE(id) \
-+	SR(DMCU_RAM_ACCESS_CTRL), \
-+	SR(DMCU_IRAM_RD_CTRL), \
-+	SR(DMCU_IRAM_RD_DATA), \
-+	SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
-+	SRI(DIG_BE_CNTL, DIG, id), \
-+	SRI(DIG_BE_EN_CNTL, DIG, id), \
-+	SRI(DP_CONFIG, DP, id), \
-+	SRI(DP_DPHY_CNTL, DP, id), \
-+	SRI(DP_DPHY_PRBS_CNTL, DP, id), \
-+	SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
-+	SRI(DP_DPHY_SYM0, DP, id), \
-+	SRI(DP_DPHY_SYM1, DP, id), \
-+	SRI(DP_DPHY_SYM2, DP, id), \
-+	SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
-+	SRI(DP_LINK_CNTL, DP, id), \
-+	SRI(DP_LINK_FRAMING_CNTL, DP, id), \
-+	SRI(DP_MSE_SAT0, DP, id), \
-+	SRI(DP_MSE_SAT1, DP, id), \
-+	SRI(DP_MSE_SAT2, DP, id), \
-+	SRI(DP_MSE_SAT_UPDATE, DP, id), \
-+	SRI(DP_SEC_CNTL, DP, id), \
-+	SRI(DP_VID_STREAM_CNTL, DP, id), \
-+	SRI(DP_DPHY_FAST_TRAINING, DP, id), \
-+	SRI(DP_SEC_CNTL1, DP, id)
-+
-+#define LE_COMMON_REG_LIST(id)\
-+	LE_COMMON_REG_LIST_BASE(id), \
-+	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
-+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
-+	SR(DCI_MEM_PWR_STATUS)
-+
-+#define LE_DCE80_REG_LIST(id)\
-+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
-+	LE_COMMON_REG_LIST_BASE(id)
-+
-+#define LE_DCE100_REG_LIST(id)\
-+	LE_COMMON_REG_LIST_BASE(id), \
-+	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
-+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
-+	SR(DCI_MEM_PWR_STATUS)
-+
-+#define LE_DCE110_REG_LIST(id)\
-+	LE_COMMON_REG_LIST_BASE(id), \
-+	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
-+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
-+	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
-+	SR(DCI_MEM_PWR_STATUS)
-+
-+#define LE_DCE120_REG_LIST(id)\
-+	LE_COMMON_REG_LIST_BASE(id), \
-+	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
-+	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
-+	SR(DCI_MEM_PWR_STATUS)
-+
-+#define LE_DCN10_REG_LIST(id)\
-+	LE_COMMON_REG_LIST_BASE(id), \
-+	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
-+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
-+	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
-+
-+struct dce110_link_enc_aux_registers {
-+	uint32_t AUX_CONTROL;
-+	uint32_t AUX_DPHY_RX_CONTROL0;
-+};
-+
-+struct dce110_link_enc_hpd_registers {
-+	uint32_t DC_HPD_CONTROL;
-+};
-+
-+struct dce110_link_enc_registers {
-+	/* DMCU registers */
-+	uint32_t MASTER_COMM_DATA_REG1;
-+	uint32_t MASTER_COMM_DATA_REG2;
-+	uint32_t MASTER_COMM_DATA_REG3;
-+	uint32_t MASTER_COMM_CMD_REG;
-+	uint32_t MASTER_COMM_CNTL_REG;
-+	uint32_t DMCU_RAM_ACCESS_CTRL;
-+	uint32_t DCI_MEM_PWR_STATUS;
-+	uint32_t DMU_MEM_PWR_CNTL;
-+	uint32_t DMCU_IRAM_RD_CTRL;
-+	uint32_t DMCU_IRAM_RD_DATA;
-+	uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
-+
-+	/* Common DP registers */
-+	uint32_t DIG_BE_CNTL;
-+	uint32_t DIG_BE_EN_CNTL;
-+	uint32_t DP_CONFIG;
-+	uint32_t DP_DPHY_CNTL;
-+	uint32_t DP_DPHY_INTERNAL_CTRL;
-+	uint32_t DP_DPHY_PRBS_CNTL;
-+	uint32_t DP_DPHY_SCRAM_CNTL;
-+	uint32_t DP_DPHY_SYM0;
-+	uint32_t DP_DPHY_SYM1;
-+	uint32_t DP_DPHY_SYM2;
-+	uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
-+	uint32_t DP_LINK_CNTL;
-+	uint32_t DP_LINK_FRAMING_CNTL;
-+	uint32_t DP_MSE_SAT0;
-+	uint32_t DP_MSE_SAT1;
-+	uint32_t DP_MSE_SAT2;
-+	uint32_t DP_MSE_SAT_UPDATE;
-+	uint32_t DP_SEC_CNTL;
-+	uint32_t DP_VID_STREAM_CNTL;
-+	uint32_t DP_DPHY_FAST_TRAINING;
-+	uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
-+	uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
-+	uint32_t DP_SEC_CNTL1;
-+};
-+
-+struct dce110_link_encoder {
-+	struct link_encoder base;
-+	const struct dce110_link_enc_registers *link_regs;
-+	const struct dce110_link_enc_aux_registers *aux_regs;
-+	const struct dce110_link_enc_hpd_registers *hpd_regs;
-+};
-+
-+
-+void dce110_link_encoder_construct(
-+	struct dce110_link_encoder *enc110,
-+	const struct encoder_init_data *init_data,
-+	const struct encoder_feature_support *enc_features,
-+	const struct dce110_link_enc_registers *link_regs,
-+	const struct dce110_link_enc_aux_registers *aux_regs,
-+	const struct dce110_link_enc_hpd_registers *hpd_regs);
-+
-+bool dce110_link_encoder_validate_dvi_output(
-+	const struct dce110_link_encoder *enc110,
-+	enum signal_type connector_signal,
-+	enum signal_type signal,
-+	const struct dc_crtc_timing *crtc_timing);
-+
-+bool dce110_link_encoder_validate_rgb_output(
-+	const struct dce110_link_encoder *enc110,
-+	const struct dc_crtc_timing *crtc_timing);
-+
-+bool dce110_link_encoder_validate_dp_output(
-+	const struct dce110_link_encoder *enc110,
-+	const struct dc_crtc_timing *crtc_timing);
-+
-+bool dce110_link_encoder_validate_wireless_output(
-+	const struct dce110_link_encoder *enc110,
-+	const struct dc_crtc_timing *crtc_timing);
-+
-+bool dce110_link_encoder_validate_output_with_stream(
-+	struct link_encoder *enc,
-+	const struct dc_stream_state *stream);
-+
-+/****************** HW programming ************************/
-+
-+/* initialize HW */  /* why do we initialze aux in here? */
-+void dce110_link_encoder_hw_init(struct link_encoder *enc);
-+
-+void dce110_link_encoder_destroy(struct link_encoder **enc);
-+
-+/* program DIG_MODE in DIG_BE */
-+/* TODO can this be combined with enable_output? */
-+void dce110_link_encoder_setup(
-+	struct link_encoder *enc,
-+	enum signal_type signal);
-+
-+/* enables TMDS PHY output */
-+/* TODO: still need depth or just pass in adjusted pixel clock? */
-+void dce110_link_encoder_enable_tmds_output(
-+	struct link_encoder *enc,
-+	enum clock_source_id clock_source,
-+	enum dc_color_depth color_depth,
-+	bool hdmi,
-+	bool dual_link,
-+	uint32_t pixel_clock);
-+
-+/* enables DP PHY output */
-+void dce110_link_encoder_enable_dp_output(
-+	struct link_encoder *enc,
-+	const struct dc_link_settings *link_settings,
-+	enum clock_source_id clock_source);
-+
-+/* enables DP PHY output in MST mode */
-+void dce110_link_encoder_enable_dp_mst_output(
-+	struct link_encoder *enc,
-+	const struct dc_link_settings *link_settings,
-+	enum clock_source_id clock_source);
-+
-+/* disable PHY output */
-+void dce110_link_encoder_disable_output(
-+	struct link_encoder *enc,
-+	enum signal_type signal);
-+
-+/* set DP lane settings */
-+void dce110_link_encoder_dp_set_lane_settings(
-+	struct link_encoder *enc,
-+	const struct link_training_settings *link_settings);
-+
-+void dce110_link_encoder_dp_set_phy_pattern(
-+	struct link_encoder *enc,
-+	const struct encoder_set_dp_phy_pattern_param *param);
-+
-+/* programs DP MST VC payload allocation */
-+void dce110_link_encoder_update_mst_stream_allocation_table(
-+	struct link_encoder *enc,
-+	const struct link_mst_stream_allocation_table *table);
-+
-+void dce110_link_encoder_connect_dig_be_to_fe(
-+	struct link_encoder *enc,
-+	enum engine_id engine,
-+	bool connect);
-+
-+void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
-+	struct link_encoder *enc,
-+	uint32_t index);
-+
-+void dce110_link_encoder_enable_hpd(struct link_encoder *enc);
-+
-+void dce110_link_encoder_disable_hpd(struct link_encoder *enc);
-+
-+void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
-+			bool exit_link_training_required);
-+
-+void dce110_psr_program_secondary_packet(struct link_encoder *enc,
-+			unsigned int sdp_transmit_line_num_deadline);
-+
-+#endif /* __DC_LINK_ENCODER__DCE110_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c.0130~	2017-12-14 06:39:58.417903569 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c	2017-12-14 06:39:58.417903569 +0100
-@@ -0,0 +1,700 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dce_mem_input.h"
-+#include "reg_helper.h"
-+#include "basics/conversion.h"
-+
-+#define CTX \
-+	dce_mi->base.ctx
-+#define REG(reg)\
-+	dce_mi->regs->reg
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	dce_mi->shifts->field_name, dce_mi->masks->field_name
-+
-+struct pte_setting {
-+	unsigned int bpp;
-+	unsigned int page_width;
-+	unsigned int page_height;
-+	unsigned char min_pte_before_flip_horiz_scan;
-+	unsigned char min_pte_before_flip_vert_scan;
-+	unsigned char pte_req_per_chunk;
-+	unsigned char param_6;
-+	unsigned char param_7;
-+	unsigned char param_8;
-+};
-+
-+enum mi_bits_per_pixel {
-+	mi_bpp_8 = 0,
-+	mi_bpp_16,
-+	mi_bpp_32,
-+	mi_bpp_64,
-+	mi_bpp_count,
-+};
-+
-+enum mi_tiling_format {
-+	mi_tiling_linear = 0,
-+	mi_tiling_1D,
-+	mi_tiling_2D,
-+	mi_tiling_count,
-+};
-+
-+static const struct pte_setting pte_settings[mi_tiling_count][mi_bpp_count] = {
-+	[mi_tiling_linear] = {
-+		{  8, 4096, 1, 8, 0, 1, 0, 0, 0},
-+		{ 16, 2048, 1, 8, 0, 1, 0, 0, 0},
-+		{ 32, 1024, 1, 8, 0, 1, 0, 0, 0},
-+		{ 64,  512, 1, 8, 0, 1, 0, 0, 0}, /* new for 64bpp from HW */
-+	},
-+	[mi_tiling_1D] = {
-+		{  8, 512, 8, 1, 0, 1, 0, 0, 0},  /* 0 for invalid */
-+		{ 16, 256, 8, 2, 0, 1, 0, 0, 0},
-+		{ 32, 128, 8, 4, 0, 1, 0, 0, 0},
-+		{ 64,  64, 8, 4, 0, 1, 0, 0, 0}, /* fake */
-+	},
-+	[mi_tiling_2D] = {
-+		{  8, 64, 64,  8,  8, 1, 4, 0, 0},
-+		{ 16, 64, 32,  8, 16, 1, 8, 0, 0},
-+		{ 32, 32, 32, 16, 16, 1, 8, 0, 0},
-+		{ 64,  8, 32, 16, 16, 1, 8, 0, 0}, /* fake */
-+	},
-+};
-+
-+static enum mi_bits_per_pixel get_mi_bpp(
-+		enum surface_pixel_format format)
-+{
-+	if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616)
-+		return mi_bpp_64;
-+	else if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888)
-+		return mi_bpp_32;
-+	else if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB1555)
-+		return mi_bpp_16;
-+	else
-+		return mi_bpp_8;
-+}
-+
-+static enum mi_tiling_format get_mi_tiling(
-+		union dc_tiling_info *tiling_info)
-+{
-+	switch (tiling_info->gfx8.array_mode) {
-+	case DC_ARRAY_1D_TILED_THIN1:
-+	case DC_ARRAY_1D_TILED_THICK:
-+	case DC_ARRAY_PRT_TILED_THIN1:
-+		return mi_tiling_1D;
-+	case DC_ARRAY_2D_TILED_THIN1:
-+	case DC_ARRAY_2D_TILED_THICK:
-+	case DC_ARRAY_2D_TILED_X_THICK:
-+	case DC_ARRAY_PRT_2D_TILED_THIN1:
-+	case DC_ARRAY_PRT_2D_TILED_THICK:
-+		return mi_tiling_2D;
-+	case DC_ARRAY_LINEAR_GENERAL:
-+	case DC_ARRAY_LINEAR_ALLIGNED:
-+		return mi_tiling_linear;
-+	default:
-+		return mi_tiling_2D;
-+	}
-+}
-+
-+static bool is_vert_scan(enum dc_rotation_angle rotation)
-+{
-+	switch (rotation) {
-+	case ROTATION_ANGLE_90:
-+	case ROTATION_ANGLE_270:
-+		return true;
-+	default:
-+		return false;
-+	}
-+}
-+
-+static void dce_mi_program_pte_vm(
-+		struct mem_input *mi,
-+		enum surface_pixel_format format,
-+		union dc_tiling_info *tiling_info,
-+		enum dc_rotation_angle rotation)
-+{
-+	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
-+	enum mi_bits_per_pixel mi_bpp = get_mi_bpp(format);
-+	enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info);
-+	const struct pte_setting *pte = &pte_settings[mi_tiling][mi_bpp];
-+
-+	unsigned int page_width = log_2(pte->page_width);
-+	unsigned int page_height = log_2(pte->page_height);
-+	unsigned int min_pte_before_flip = is_vert_scan(rotation) ?
-+			pte->min_pte_before_flip_vert_scan :
-+			pte->min_pte_before_flip_horiz_scan;
-+
-+	REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT,
-+			GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 0xff);
-+
-+	REG_UPDATE_3(DVMM_PTE_CONTROL,
-+			DVMM_PAGE_WIDTH, page_width,
-+			DVMM_PAGE_HEIGHT, page_height,
-+			DVMM_MIN_PTE_BEFORE_FLIP, min_pte_before_flip);
-+
-+	REG_UPDATE_2(DVMM_PTE_ARB_CONTROL,
-+			DVMM_PTE_REQ_PER_CHUNK, pte->pte_req_per_chunk,
-+			DVMM_MAX_PTE_REQ_OUTSTANDING, 0xff);
-+}
-+
-+static void program_urgency_watermark(
-+	struct dce_mem_input *dce_mi,
-+	uint32_t wm_select,
-+	uint32_t urgency_low_wm,
-+	uint32_t urgency_high_wm)
-+{
-+	REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
-+		URGENCY_WATERMARK_MASK, wm_select);
-+
-+	REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,
-+		URGENCY_LOW_WATERMARK, urgency_low_wm,
-+		URGENCY_HIGH_WATERMARK, urgency_high_wm);
-+}
-+
-+static void program_nbp_watermark(
-+	struct dce_mem_input *dce_mi,
-+	uint32_t wm_select,
-+	uint32_t nbp_wm)
-+{
-+	if (REG(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL)) {
-+		REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
-+				NB_PSTATE_CHANGE_WATERMARK_MASK, wm_select);
-+
-+		REG_UPDATE_3(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+				NB_PSTATE_CHANGE_ENABLE, 1,
-+				NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, 1,
-+				NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, 1);
-+
-+		REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,
-+				NB_PSTATE_CHANGE_WATERMARK, nbp_wm);
-+	}
-+
-+	if (REG(DPG_PIPE_LOW_POWER_CONTROL)) {
-+		REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
-+				PSTATE_CHANGE_WATERMARK_MASK, wm_select);
-+
-+		REG_UPDATE_3(DPG_PIPE_LOW_POWER_CONTROL,
-+				PSTATE_CHANGE_ENABLE, 1,
-+				PSTATE_CHANGE_URGENT_DURING_REQUEST, 1,
-+				PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, 1);
-+
-+		REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL,
-+				PSTATE_CHANGE_WATERMARK, nbp_wm);
-+	}
-+}
-+
-+static void program_stutter_watermark(
-+	struct dce_mem_input *dce_mi,
-+	uint32_t wm_select,
-+	uint32_t stutter_mark)
-+{
-+	REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
-+		STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select);
-+
-+	if (REG(DPG_PIPE_STUTTER_CONTROL2))
-+		REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2,
-+				STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark);
-+	else
-+		REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,
-+				STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark);
-+}
-+
-+static void dce_mi_program_display_marks(
-+	struct mem_input *mi,
-+	struct dce_watermarks nbp,
-+	struct dce_watermarks stutter,
-+	struct dce_watermarks urgent,
-+	uint32_t total_dest_line_time_ns)
-+{
-+	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
-+	uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
-+
-+	program_urgency_watermark(dce_mi, 2, /* set a */
-+			urgent.a_mark, total_dest_line_time_ns);
-+	program_urgency_watermark(dce_mi, 1, /* set d */
-+			urgent.d_mark, total_dest_line_time_ns);
-+
-+	REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_ENABLE, stutter_en,
-+		STUTTER_IGNORE_FBC, 1);
-+	program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */
-+	program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */
-+
-+	program_stutter_watermark(dce_mi, 2, stutter.a_mark); /* set a */
-+	program_stutter_watermark(dce_mi, 1, stutter.d_mark); /* set d */
-+}
-+
-+static void dce120_mi_program_display_marks(struct mem_input *mi,
-+	struct dce_watermarks nbp,
-+	struct dce_watermarks stutter,
-+	struct dce_watermarks urgent,
-+	uint32_t total_dest_line_time_ns)
-+{
-+	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
-+	uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
-+
-+	program_urgency_watermark(dce_mi, 0, /* set a */
-+			urgent.a_mark, total_dest_line_time_ns);
-+	program_urgency_watermark(dce_mi, 1, /* set b */
-+			urgent.b_mark, total_dest_line_time_ns);
-+	program_urgency_watermark(dce_mi, 2, /* set c */
-+			urgent.c_mark, total_dest_line_time_ns);
-+	program_urgency_watermark(dce_mi, 3, /* set d */
-+			urgent.d_mark, total_dest_line_time_ns);
-+
-+	REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
-+		STUTTER_ENABLE, stutter_en,
-+		STUTTER_IGNORE_FBC, 1);
-+	program_nbp_watermark(dce_mi, 0, nbp.a_mark); /* set a */
-+	program_nbp_watermark(dce_mi, 1, nbp.b_mark); /* set b */
-+	program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */
-+	program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */
-+
-+	program_stutter_watermark(dce_mi, 0, stutter.a_mark); /* set a */
-+	program_stutter_watermark(dce_mi, 1, stutter.b_mark); /* set b */
-+	program_stutter_watermark(dce_mi, 2, stutter.c_mark); /* set c */
-+	program_stutter_watermark(dce_mi, 3, stutter.d_mark); /* set d */
-+}
-+
-+static void program_tiling(
-+	struct dce_mem_input *dce_mi, const union dc_tiling_info *info)
-+{
-+	if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */
-+		REG_UPDATE_6(GRPH_CONTROL,
-+				GRPH_SW_MODE, info->gfx9.swizzle,
-+				GRPH_NUM_BANKS, log_2(info->gfx9.num_banks),
-+				GRPH_NUM_SHADER_ENGINES, log_2(info->gfx9.num_shader_engines),
-+				GRPH_NUM_PIPES, log_2(info->gfx9.num_pipes),
-+				GRPH_COLOR_EXPANSION_MODE, 1,
-+				GRPH_SE_ENABLE, info->gfx9.shaderEnable);
-+		/* TODO: DCP0_GRPH_CONTROL__GRPH_SE_ENABLE where to get info
-+		GRPH_SE_ENABLE, 1,
-+		GRPH_Z, 0);
-+		 */
-+	}
-+
-+	if (dce_mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */
-+		REG_UPDATE_9(GRPH_CONTROL,
-+				GRPH_NUM_BANKS, info->gfx8.num_banks,
-+				GRPH_BANK_WIDTH, info->gfx8.bank_width,
-+				GRPH_BANK_HEIGHT, info->gfx8.bank_height,
-+				GRPH_MACRO_TILE_ASPECT, info->gfx8.tile_aspect,
-+				GRPH_TILE_SPLIT, info->gfx8.tile_split,
-+				GRPH_MICRO_TILE_MODE, info->gfx8.tile_mode,
-+				GRPH_PIPE_CONFIG, info->gfx8.pipe_config,
-+				GRPH_ARRAY_MODE, info->gfx8.array_mode,
-+				GRPH_COLOR_EXPANSION_MODE, 1);
-+		/* 01 - DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP: zero expansion for YCbCr */
-+		/*
-+				GRPH_Z, 0);
-+				*/
-+	}
-+}
-+
-+
-+static void program_size_and_rotation(
-+	struct dce_mem_input *dce_mi,
-+	enum dc_rotation_angle rotation,
-+	const union plane_size *plane_size)
-+{
-+	const struct rect *in_rect = &plane_size->grph.surface_size;
-+	struct rect hw_rect = plane_size->grph.surface_size;
-+	const uint32_t rotation_angles[ROTATION_ANGLE_COUNT] = {
-+			[ROTATION_ANGLE_0] = 0,
-+			[ROTATION_ANGLE_90] = 1,
-+			[ROTATION_ANGLE_180] = 2,
-+			[ROTATION_ANGLE_270] = 3,
-+	};
-+
-+	if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) {
-+		hw_rect.x = in_rect->y;
-+		hw_rect.y = in_rect->x;
-+
-+		hw_rect.height = in_rect->width;
-+		hw_rect.width = in_rect->height;
-+	}
-+
-+	REG_SET(GRPH_X_START, 0,
-+			GRPH_X_START, hw_rect.x);
-+
-+	REG_SET(GRPH_Y_START, 0,
-+			GRPH_Y_START, hw_rect.y);
-+
-+	REG_SET(GRPH_X_END, 0,
-+			GRPH_X_END, hw_rect.width);
-+
-+	REG_SET(GRPH_Y_END, 0,
-+			GRPH_Y_END, hw_rect.height);
-+
-+	REG_SET(GRPH_PITCH, 0,
-+			GRPH_PITCH, plane_size->grph.surface_pitch);
-+
-+	REG_SET(HW_ROTATION, 0,
-+			GRPH_ROTATION_ANGLE, rotation_angles[rotation]);
-+}
-+
-+static void program_grph_pixel_format(
-+	struct dce_mem_input *dce_mi,
-+	enum surface_pixel_format format)
-+{
-+	uint32_t red_xbar = 0, blue_xbar = 0; /* no swap */
-+	uint32_t grph_depth = 0, grph_format = 0;
-+	uint32_t sign = 0, floating = 0;
-+
-+	if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 ||
-+			/*todo: doesn't look like we handle BGRA here,
-+			 *  should problem swap endian*/
-+		format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 ||
-+		format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS ||
-+		format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
-+		/* ABGR formats */
-+		red_xbar = 2;
-+		blue_xbar = 2;
-+	}
-+
-+	REG_SET_2(GRPH_SWAP_CNTL, 0,
-+			GRPH_RED_CROSSBAR, red_xbar,
-+			GRPH_BLUE_CROSSBAR, blue_xbar);
-+
-+	switch (format) {
-+	case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
-+		grph_depth = 0;
-+		grph_format = 0;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
-+		grph_depth = 1;
-+		grph_format = 0;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
-+		grph_depth = 1;
-+		grph_format = 1;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
-+		grph_depth = 2;
-+		grph_format = 0;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
-+		grph_depth = 2;
-+		grph_format = 1;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+		sign = 1;
-+		floating = 1;
-+		/* no break */
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: /* shouldn't this get float too? */
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+		grph_depth = 3;
-+		grph_format = 0;
-+		break;
-+	default:
-+		DC_ERR("unsupported grph pixel format");
-+		break;
-+	}
-+
-+	REG_UPDATE_2(GRPH_CONTROL,
-+			GRPH_DEPTH, grph_depth,
-+			GRPH_FORMAT, grph_format);
-+
-+	REG_UPDATE_4(PRESCALE_GRPH_CONTROL,
-+			GRPH_PRESCALE_SELECT, floating,
-+			GRPH_PRESCALE_R_SIGN, sign,
-+			GRPH_PRESCALE_G_SIGN, sign,
-+			GRPH_PRESCALE_B_SIGN, sign);
-+}
-+
-+static void dce_mi_program_surface_config(
-+	struct mem_input *mi,
-+	enum surface_pixel_format format,
-+	union dc_tiling_info *tiling_info,
-+	union plane_size *plane_size,
-+	enum dc_rotation_angle rotation,
-+	struct dc_plane_dcc_param *dcc,
-+	bool horizontal_mirror)
-+{
-+	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
-+	REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);
-+
-+	program_tiling(dce_mi, tiling_info);
-+	program_size_and_rotation(dce_mi, rotation, plane_size);
-+
-+	if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
-+		format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
-+		program_grph_pixel_format(dce_mi, format);
-+}
-+
-+static uint32_t get_dmif_switch_time_us(
-+	uint32_t h_total,
-+	uint32_t v_total,
-+	uint32_t pix_clk_khz)
-+{
-+	uint32_t frame_time;
-+	uint32_t pixels_per_second;
-+	uint32_t pixels_per_frame;
-+	uint32_t refresh_rate;
-+	const uint32_t us_in_sec = 1000000;
-+	const uint32_t min_single_frame_time_us = 30000;
-+	/*return double of frame time*/
-+	const uint32_t single_frame_time_multiplier = 2;
-+
-+	if (!h_total || v_total || !pix_clk_khz)
-+		return single_frame_time_multiplier * min_single_frame_time_us;
-+
-+	/*TODO: should we use pixel format normalized pixel clock here?*/
-+	pixels_per_second = pix_clk_khz * 1000;
-+	pixels_per_frame = h_total * v_total;
-+
-+	if (!pixels_per_second || !pixels_per_frame) {
-+		/* avoid division by zero */
-+		ASSERT(pixels_per_frame);
-+		ASSERT(pixels_per_second);
-+		return single_frame_time_multiplier * min_single_frame_time_us;
-+	}
-+
-+	refresh_rate = pixels_per_second / pixels_per_frame;
-+
-+	if (!refresh_rate) {
-+		/* avoid division by zero*/
-+		ASSERT(refresh_rate);
-+		return single_frame_time_multiplier * min_single_frame_time_us;
-+	}
-+
-+	frame_time = us_in_sec / refresh_rate;
-+
-+	if (frame_time < min_single_frame_time_us)
-+		frame_time = min_single_frame_time_us;
-+
-+	frame_time *= single_frame_time_multiplier;
-+
-+	return frame_time;
-+}
-+
-+static void dce_mi_allocate_dmif(
-+	struct mem_input *mi,
-+	uint32_t h_total,
-+	uint32_t v_total,
-+	uint32_t pix_clk_khz,
-+	uint32_t total_stream_num)
-+{
-+	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
-+	const uint32_t retry_delay = 10;
-+	uint32_t retry_count = get_dmif_switch_time_us(
-+			h_total,
-+			v_total,
-+			pix_clk_khz) / retry_delay;
-+
-+	uint32_t pix_dur;
-+	uint32_t buffers_allocated;
-+	uint32_t dmif_buffer_control;
-+
-+	dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL,
-+			DMIF_BUFFERS_ALLOCATED, &buffers_allocated);
-+
-+	if (buffers_allocated == 2)
-+		return;
-+
-+	REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control,
-+			DMIF_BUFFERS_ALLOCATED, 2);
-+
-+	REG_WAIT(DMIF_BUFFER_CONTROL,
-+			DMIF_BUFFERS_ALLOCATION_COMPLETED, 1,
-+			retry_delay, retry_count);
-+
-+	if (pix_clk_khz != 0) {
-+		pix_dur = 1000000000ULL / pix_clk_khz;
-+
-+		REG_UPDATE(DPG_PIPE_ARBITRATION_CONTROL1,
-+			PIXEL_DURATION, pix_dur);
-+	}
-+
-+	if (dce_mi->wa.single_head_rdreq_dmif_limit) {
-+		uint32_t eanble =  (total_stream_num > 1) ? 0 :
-+				dce_mi->wa.single_head_rdreq_dmif_limit;
-+
-+		REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,
-+				ENABLE, eanble);
-+	}
-+}
-+
-+static void dce_mi_free_dmif(
-+		struct mem_input *mi,
-+		uint32_t total_stream_num)
-+{
-+	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
-+	uint32_t buffers_allocated;
-+	uint32_t dmif_buffer_control;
-+
-+	dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL,
-+			DMIF_BUFFERS_ALLOCATED, &buffers_allocated);
-+
-+	if (buffers_allocated == 0)
-+		return;
-+
-+	REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control,
-+			DMIF_BUFFERS_ALLOCATED, 0);
-+
-+	REG_WAIT(DMIF_BUFFER_CONTROL,
-+			DMIF_BUFFERS_ALLOCATION_COMPLETED, 1,
-+			10, 3500);
-+
-+	if (dce_mi->wa.single_head_rdreq_dmif_limit) {
-+		uint32_t eanble =  (total_stream_num > 1) ? 0 :
-+				dce_mi->wa.single_head_rdreq_dmif_limit;
-+
-+		REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,
-+				ENABLE, eanble);
-+	}
-+}
-+
-+
-+static void program_sec_addr(
-+	struct dce_mem_input *dce_mi,
-+	PHYSICAL_ADDRESS_LOC address)
-+{
-+	/*high register MUST be programmed first*/
-+	REG_SET(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
-+		GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
-+		address.high_part);
-+
-+	REG_SET_2(GRPH_SECONDARY_SURFACE_ADDRESS, 0,
-+		GRPH_SECONDARY_SURFACE_ADDRESS, address.low_part >> 8,
-+		GRPH_SECONDARY_DFQ_ENABLE, 0);
-+}
-+
-+static void program_pri_addr(
-+	struct dce_mem_input *dce_mi,
-+	PHYSICAL_ADDRESS_LOC address)
-+{
-+	/*high register MUST be programmed first*/
-+	REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
-+		GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
-+		address.high_part);
-+
-+	REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS, 0,
-+		GRPH_PRIMARY_SURFACE_ADDRESS,
-+		address.low_part >> 8);
-+}
-+
-+
-+static bool dce_mi_is_flip_pending(struct mem_input *mem_input)
-+{
-+	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mem_input);
-+	uint32_t update_pending;
-+
-+	REG_GET(GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, &update_pending);
-+	if (update_pending)
-+		return true;
-+
-+	mem_input->current_address = mem_input->request_address;
-+	return false;
-+}
-+
-+static bool dce_mi_program_surface_flip_and_addr(
-+	struct mem_input *mem_input,
-+	const struct dc_plane_address *address,
-+	bool flip_immediate)
-+{
-+	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mem_input);
-+
-+	REG_UPDATE(GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
-+
-+	REG_UPDATE(
-+		GRPH_FLIP_CONTROL,
-+		GRPH_SURFACE_UPDATE_H_RETRACE_EN, flip_immediate ? 1 : 0);
-+
-+	switch (address->type) {
-+	case PLN_ADDR_TYPE_GRAPHICS:
-+		if (address->grph.addr.quad_part == 0)
-+			break;
-+		program_pri_addr(dce_mi, address->grph.addr);
-+		break;
-+	case PLN_ADDR_TYPE_GRPH_STEREO:
-+		if (address->grph_stereo.left_addr.quad_part == 0 ||
-+		    address->grph_stereo.right_addr.quad_part == 0)
-+			break;
-+		program_pri_addr(dce_mi, address->grph_stereo.left_addr);
-+		program_sec_addr(dce_mi, address->grph_stereo.right_addr);
-+		break;
-+	default:
-+		/* not supported */
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+
-+	mem_input->request_address = *address;
-+
-+	if (flip_immediate)
-+		mem_input->current_address = *address;
-+
-+	REG_UPDATE(GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
-+
-+	return true;
-+}
-+
-+static struct mem_input_funcs dce_mi_funcs = {
-+	.mem_input_program_display_marks = dce_mi_program_display_marks,
-+	.allocate_mem_input = dce_mi_allocate_dmif,
-+	.free_mem_input = dce_mi_free_dmif,
-+	.mem_input_program_surface_flip_and_addr =
-+			dce_mi_program_surface_flip_and_addr,
-+	.mem_input_program_pte_vm = dce_mi_program_pte_vm,
-+	.mem_input_program_surface_config =
-+			dce_mi_program_surface_config,
-+	.mem_input_is_flip_pending = dce_mi_is_flip_pending
-+};
-+
-+
-+void dce_mem_input_construct(
-+	struct dce_mem_input *dce_mi,
-+	struct dc_context *ctx,
-+	int inst,
-+	const struct dce_mem_input_registers *regs,
-+	const struct dce_mem_input_shift *mi_shift,
-+	const struct dce_mem_input_mask *mi_mask)
-+{
-+	dce_mi->base.ctx = ctx;
-+
-+	dce_mi->base.inst = inst;
-+	dce_mi->base.funcs = &dce_mi_funcs;
-+
-+	dce_mi->regs = regs;
-+	dce_mi->shifts = mi_shift;
-+	dce_mi->masks = mi_mask;
-+}
-+
-+void dce112_mem_input_construct(
-+	struct dce_mem_input *dce_mi,
-+	struct dc_context *ctx,
-+	int inst,
-+	const struct dce_mem_input_registers *regs,
-+	const struct dce_mem_input_shift *mi_shift,
-+	const struct dce_mem_input_mask *mi_mask)
-+{
-+	dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
-+	dce_mi->base.funcs->mem_input_program_display_marks = dce120_mi_program_display_marks;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h.0130~	2017-12-14 06:39:58.417903569 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h	2017-12-14 06:39:58.417903569 +0100
-@@ -0,0 +1,347 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DCE_MEM_INPUT_H__
-+#define __DCE_MEM_INPUT_H__
-+
-+#include "dc_hw_types.h"
-+#include "mem_input.h"
-+
-+#define TO_DCE_MEM_INPUT(mem_input)\
-+	container_of(mem_input, struct dce_mem_input, base)
-+
-+#define MI_DCE_BASE_REG_LIST(id)\
-+	SRI(GRPH_ENABLE, DCP, id),\
-+	SRI(GRPH_CONTROL, DCP, id),\
-+	SRI(GRPH_X_START, DCP, id),\
-+	SRI(GRPH_Y_START, DCP, id),\
-+	SRI(GRPH_X_END, DCP, id),\
-+	SRI(GRPH_Y_END, DCP, id),\
-+	SRI(GRPH_PITCH, DCP, id),\
-+	SRI(HW_ROTATION, DCP, id),\
-+	SRI(GRPH_SWAP_CNTL, DCP, id),\
-+	SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
-+	SRI(GRPH_UPDATE, DCP, id),\
-+	SRI(GRPH_FLIP_CONTROL, DCP, id),\
-+	SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\
-+	SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\
-+	SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\
-+	SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\
-+	SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\
-+	SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\
-+	SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\
-+	SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\
-+	SRI(DMIF_BUFFER_CONTROL, PIPE, id)
-+
-+#define MI_DCE_PTE_REG_LIST(id)\
-+	SRI(DVMM_PTE_CONTROL, DCP, id),\
-+	SRI(DVMM_PTE_ARB_CONTROL, DCP, id)
-+
-+#define MI_DCE8_REG_LIST(id)\
-+	MI_DCE_BASE_REG_LIST(id),\
-+	SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id)
-+
-+#define MI_DCE11_2_REG_LIST(id)\
-+	MI_DCE8_REG_LIST(id),\
-+	SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id)
-+
-+#define MI_DCE11_REG_LIST(id)\
-+	MI_DCE11_2_REG_LIST(id),\
-+	MI_DCE_PTE_REG_LIST(id)
-+
-+#define MI_DCE12_REG_LIST(id)\
-+	MI_DCE_BASE_REG_LIST(id),\
-+	MI_DCE_PTE_REG_LIST(id),\
-+	SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\
-+	SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\
-+	SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id),\
-+	SR(DCHUB_FB_LOCATION),\
-+	SR(DCHUB_AGP_BASE),\
-+	SR(DCHUB_AGP_BOT),\
-+	SR(DCHUB_AGP_TOP)
-+
-+struct dce_mem_input_registers {
-+	/* DCP */
-+	uint32_t GRPH_ENABLE;
-+	uint32_t GRPH_CONTROL;
-+	uint32_t GRPH_X_START;
-+	uint32_t GRPH_Y_START;
-+	uint32_t GRPH_X_END;
-+	uint32_t GRPH_Y_END;
-+	uint32_t GRPH_PITCH;
-+	uint32_t HW_ROTATION;
-+	uint32_t GRPH_SWAP_CNTL;
-+	uint32_t PRESCALE_GRPH_CONTROL;
-+	uint32_t GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT;
-+	uint32_t DVMM_PTE_CONTROL;
-+	uint32_t DVMM_PTE_ARB_CONTROL;
-+	uint32_t GRPH_UPDATE;
-+	uint32_t GRPH_FLIP_CONTROL;
-+	uint32_t GRPH_PRIMARY_SURFACE_ADDRESS;
-+	uint32_t GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
-+	uint32_t GRPH_SECONDARY_SURFACE_ADDRESS;
-+	uint32_t GRPH_SECONDARY_SURFACE_ADDRESS_HIGH;
-+	/* DMIF_PG */
-+	uint32_t DPG_PIPE_ARBITRATION_CONTROL1;
-+	uint32_t DPG_WATERMARK_MASK_CONTROL;
-+	uint32_t DPG_PIPE_URGENCY_CONTROL;
-+	uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
-+	uint32_t DPG_PIPE_LOW_POWER_CONTROL;
-+	uint32_t DPG_PIPE_STUTTER_CONTROL;
-+	uint32_t DPG_PIPE_STUTTER_CONTROL2;
-+	/* DCI */
-+	uint32_t DMIF_BUFFER_CONTROL;
-+	/* MC_HUB */
-+	uint32_t MC_HUB_RDREQ_DMIF_LIMIT;
-+	/*DCHUB*/
-+	uint32_t DCHUB_FB_LOCATION;
-+	uint32_t DCHUB_AGP_BASE;
-+	uint32_t DCHUB_AGP_BOT;
-+	uint32_t DCHUB_AGP_TOP;
-+};
-+
-+/* Set_Filed_for_Block */
-+#define SFB(blk_name, reg_name, field_name, post_fix)\
-+	.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
-+
-+#define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
-+	SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
-+
-+#define MI_DCP_MASK_SH_LIST(mask_sh, blk)\
-+	SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
-+	SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
-+	SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
-+	SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
-+	SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
-+	SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
-+	SFB(blk, HW_ROTATION, GRPH_ROTATION_ANGLE, mask_sh),\
-+	SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\
-+	SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\
-+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
-+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
-+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
-+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\
-+	SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
-+	SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\
-+	SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
-+	SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\
-+	SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\
-+	SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\
-+	SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
-+
-+#define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\
-+	SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh)
-+
-+#define MI_DCP_PTE_MASK_SH_LIST(mask_sh, blk)\
-+	SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH, mask_sh),\
-+	SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT, mask_sh),\
-+	SFB(blk, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP, mask_sh),\
-+	SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK, mask_sh),\
-+	SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING, mask_sh)
-+
-+#define MI_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\
-+	SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\
-+	SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\
-+	SFB(blk, DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\
-+	SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
-+	SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
-+	SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\
-+	SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\
-+	SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
-+	SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
-+
-+#define MI_DMIF_PG_MASK_SH_DCE(mask_sh, blk)\
-+	SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
-+	SFB(blk, DPG_WATERMARK_MASK_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
-+	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\
-+	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
-+	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
-+	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh)
-+
-+#define MI_DCE8_MASK_SH_LIST(mask_sh)\
-+	MI_DCP_MASK_SH_LIST(mask_sh, ),\
-+	MI_DMIF_PG_MASK_SH_LIST(mask_sh, ),\
-+	MI_DMIF_PG_MASK_SH_DCE(mask_sh, ),\
-+	MI_GFX8_TILE_MASK_SH_LIST(mask_sh, )
-+
-+#define MI_DCE11_2_MASK_SH_LIST(mask_sh)\
-+	MI_DCE8_MASK_SH_LIST(mask_sh),\
-+	MI_DCP_DCE11_MASK_SH_LIST(mask_sh, )
-+
-+#define MI_DCE11_MASK_SH_LIST(mask_sh)\
-+	MI_DCE11_2_MASK_SH_LIST(mask_sh),\
-+	MI_DCP_PTE_MASK_SH_LIST(mask_sh, )
-+
-+#define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\
-+	SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_NUM_PIPES, mask_sh),\
-+	SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
-+
-+#define MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\
-+	SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
-+	SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
-+	SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\
-+	SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
-+	SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
-+	SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh)
-+
-+#define MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
-+	SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
-+	SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
-+	SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
-+	SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
-+	SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
-+
-+#define MI_DCE12_MASK_SH_LIST(mask_sh)\
-+	MI_DCP_MASK_SH_LIST(mask_sh, DCP0_),\
-+	SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\
-+	MI_DCP_DCE11_MASK_SH_LIST(mask_sh, DCP0_),\
-+	MI_DCP_PTE_MASK_SH_LIST(mask_sh, DCP0_),\
-+	MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\
-+	MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\
-+	MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_),\
-+	MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh)
-+
-+#define MI_REG_FIELD_LIST(type) \
-+	type GRPH_ENABLE; \
-+	type GRPH_X_START; \
-+	type GRPH_Y_START; \
-+	type GRPH_X_END; \
-+	type GRPH_Y_END; \
-+	type GRPH_PITCH; \
-+	type GRPH_ROTATION_ANGLE; \
-+	type GRPH_RED_CROSSBAR; \
-+	type GRPH_BLUE_CROSSBAR; \
-+	type GRPH_PRESCALE_SELECT; \
-+	type GRPH_PRESCALE_R_SIGN; \
-+	type GRPH_PRESCALE_G_SIGN; \
-+	type GRPH_PRESCALE_B_SIGN; \
-+	type GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT; \
-+	type DVMM_PAGE_WIDTH; \
-+	type DVMM_PAGE_HEIGHT; \
-+	type DVMM_MIN_PTE_BEFORE_FLIP; \
-+	type DVMM_PTE_REQ_PER_CHUNK; \
-+	type DVMM_MAX_PTE_REQ_OUTSTANDING; \
-+	type GRPH_DEPTH; \
-+	type GRPH_FORMAT; \
-+	type GRPH_NUM_BANKS; \
-+	type GRPH_BANK_WIDTH;\
-+	type GRPH_BANK_HEIGHT;\
-+	type GRPH_MACRO_TILE_ASPECT;\
-+	type GRPH_TILE_SPLIT;\
-+	type GRPH_MICRO_TILE_MODE;\
-+	type GRPH_PIPE_CONFIG;\
-+	type GRPH_ARRAY_MODE;\
-+	type GRPH_COLOR_EXPANSION_MODE;\
-+	type GRPH_SW_MODE; \
-+	type GRPH_SE_ENABLE; \
-+	type GRPH_NUM_SHADER_ENGINES; \
-+	type GRPH_NUM_PIPES; \
-+	type GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; \
-+	type GRPH_SECONDARY_SURFACE_ADDRESS; \
-+	type GRPH_SECONDARY_DFQ_ENABLE; \
-+	type GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; \
-+	type GRPH_PRIMARY_SURFACE_ADDRESS; \
-+	type GRPH_SURFACE_UPDATE_PENDING; \
-+	type GRPH_SURFACE_UPDATE_H_RETRACE_EN; \
-+	type GRPH_UPDATE_LOCK; \
-+	type PIXEL_DURATION; \
-+	type URGENCY_WATERMARK_MASK; \
-+	type PSTATE_CHANGE_WATERMARK_MASK; \
-+	type NB_PSTATE_CHANGE_WATERMARK_MASK; \
-+	type STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK; \
-+	type URGENCY_LOW_WATERMARK; \
-+	type URGENCY_HIGH_WATERMARK; \
-+	type NB_PSTATE_CHANGE_ENABLE; \
-+	type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST; \
-+	type NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \
-+	type NB_PSTATE_CHANGE_WATERMARK; \
-+	type PSTATE_CHANGE_ENABLE; \
-+	type PSTATE_CHANGE_URGENT_DURING_REQUEST; \
-+	type PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \
-+	type PSTATE_CHANGE_WATERMARK; \
-+	type STUTTER_ENABLE; \
-+	type STUTTER_IGNORE_FBC; \
-+	type STUTTER_EXIT_SELF_REFRESH_WATERMARK; \
-+	type DMIF_BUFFERS_ALLOCATED; \
-+	type DMIF_BUFFERS_ALLOCATION_COMPLETED; \
-+	type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\
-+	type FB_BASE; \
-+	type FB_TOP; \
-+	type AGP_BASE; \
-+	type AGP_TOP; \
-+	type AGP_BOT; \
-+
-+struct dce_mem_input_shift {
-+	MI_REG_FIELD_LIST(uint8_t)
-+};
-+
-+struct dce_mem_input_mask {
-+	MI_REG_FIELD_LIST(uint32_t)
-+};
-+
-+struct dce_mem_input_wa {
-+	uint8_t single_head_rdreq_dmif_limit;
-+};
-+
-+struct dce_mem_input {
-+	struct mem_input base;
-+
-+	const struct dce_mem_input_registers *regs;
-+	const struct dce_mem_input_shift *shifts;
-+	const struct dce_mem_input_mask *masks;
-+
-+	struct dce_mem_input_wa wa;
-+};
-+
-+void dce_mem_input_construct(
-+	struct dce_mem_input *dce_mi,
-+	struct dc_context *ctx,
-+	int inst,
-+	const struct dce_mem_input_registers *regs,
-+	const struct dce_mem_input_shift *mi_shift,
-+	const struct dce_mem_input_mask *mi_mask);
-+
-+void dce112_mem_input_construct(
-+	struct dce_mem_input *dce_mi,
-+	struct dc_context *ctx,
-+	int inst,
-+	const struct dce_mem_input_registers *regs,
-+	const struct dce_mem_input_shift *mi_shift,
-+	const struct dce_mem_input_mask *mi_mask);
-+
-+#endif /*__DCE_MEM_INPUT_H__*/
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c.0130~	2017-12-14 06:39:58.418903570 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c	2017-12-14 06:39:58.418903570 +0100
-@@ -0,0 +1,567 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "basics/conversion.h"
-+
-+#include "dce_opp.h"
-+
-+#include "reg_helper.h"
-+
-+#define REG(reg)\
-+	(opp110->regs->reg)
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	opp110->opp_shift->field_name, opp110->opp_mask->field_name
-+
-+#define CTX \
-+	opp110->base.ctx
-+
-+enum {
-+	MAX_PWL_ENTRY = 128,
-+	MAX_REGIONS_NUMBER = 16
-+};
-+
-+enum {
-+	MAX_LUT_ENTRY = 256,
-+	MAX_NUMBER_OF_ENTRIES = 256
-+};
-+
-+
-+enum {
-+	OUTPUT_CSC_MATRIX_SIZE = 12
-+};
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+
-+/*
-+ *****************************************************************************
-+ *  Function: regamma_config_regions_and_segments
-+ *
-+ *     build regamma curve by using predefined hw points
-+ *     uses interface parameters ,like EDID coeff.
-+ *
-+ * @param   : parameters   interface parameters
-+ *  @return void
-+ *
-+ *  @note
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+
-+
-+
-+/**
-+ *	set_truncation
-+ *	1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
-+ *	2) enable truncation
-+ *	3) HW remove 12bit FMT support for DCE11 power saving reason.
-+ */
-+static void set_truncation(
-+		struct dce110_opp *opp110,
-+		const struct bit_depth_reduction_params *params)
-+{
-+	/*Disable truncation*/
-+	REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
-+			FMT_TRUNCATE_EN, 0,
-+			FMT_TRUNCATE_DEPTH, 0,
-+			FMT_TRUNCATE_MODE, 0);
-+
-+
-+	if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
-+		/*  8bpc trunc on YCbCr422*/
-+		if (params->flags.TRUNCATE_DEPTH == 1)
-+			REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
-+					FMT_TRUNCATE_EN, 1,
-+					FMT_TRUNCATE_DEPTH, 1,
-+					FMT_TRUNCATE_MODE, 0);
-+		else if (params->flags.TRUNCATE_DEPTH == 2)
-+			/*  10bpc trunc on YCbCr422*/
-+			REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
-+					FMT_TRUNCATE_EN, 1,
-+					FMT_TRUNCATE_DEPTH, 2,
-+					FMT_TRUNCATE_MODE, 0);
-+		return;
-+	}
-+	/* on other format-to do */
-+	if (params->flags.TRUNCATE_ENABLED == 0 ||
-+			params->flags.TRUNCATE_DEPTH == 2)
-+		return;
-+	/*Set truncation depth and Enable truncation*/
-+	REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
-+				FMT_TRUNCATE_EN, 1,
-+				FMT_TRUNCATE_DEPTH,
-+				params->flags.TRUNCATE_MODE,
-+				FMT_TRUNCATE_MODE,
-+				params->flags.TRUNCATE_DEPTH);
-+}
-+
-+
-+/**
-+ *	set_spatial_dither
-+ *	1) set spatial dithering mode: pattern of seed
-+ *	2) set spatical dithering depth: 0 for 18bpp or 1 for 24bpp
-+ *	3) set random seed
-+ *	4) set random mode
-+ *		lfsr is reset every frame or not reset
-+ *		RGB dithering method
-+ *		0: RGB data are all dithered with x^28+x^3+1
-+ *		1: R data is dithered with x^28+x^3+1
-+ *		G data is dithered with x^28+X^9+1
-+ *		B data is dithered with x^28+x^13+1
-+ *		enable high pass filter or not
-+ *	5) enable spatical dithering
-+ */
-+static void set_spatial_dither(
-+	struct dce110_opp *opp110,
-+	const struct bit_depth_reduction_params *params)
-+{
-+	/*Disable spatial (random) dithering*/
-+	REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
-+		FMT_SPATIAL_DITHER_EN, 0,
-+		FMT_SPATIAL_DITHER_DEPTH, 0,
-+		FMT_SPATIAL_DITHER_MODE, 0);
-+
-+	REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
-+		FMT_HIGHPASS_RANDOM_ENABLE, 0,
-+		FMT_FRAME_RANDOM_ENABLE, 0,
-+		FMT_RGB_RANDOM_ENABLE, 0);
-+
-+	REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_EN, 0);
-+
-+	/* no 10bpc on DCE11*/
-+	if (params->flags.SPATIAL_DITHER_ENABLED == 0 ||
-+		params->flags.SPATIAL_DITHER_DEPTH == 2)
-+		return;
-+
-+	/* only use FRAME_COUNTER_MAX if frameRandom == 1*/
-+
-+	if (opp110->opp_mask->FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX &&
-+			opp110->opp_mask->FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP) {
-+		if (params->flags.FRAME_RANDOM == 1) {
-+			if (params->flags.SPATIAL_DITHER_DEPTH == 0 ||
-+			params->flags.SPATIAL_DITHER_DEPTH == 1) {
-+				REG_UPDATE_2(FMT_CONTROL,
-+					FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15,
-+					FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2);
-+			} else if (params->flags.SPATIAL_DITHER_DEPTH == 2) {
-+				REG_UPDATE_2(FMT_CONTROL,
-+					FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3,
-+					FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1);
-+			} else
-+				return;
-+		} else {
-+			REG_UPDATE_2(FMT_CONTROL,
-+					FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0,
-+					FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0);
-+		}
-+	}
-+	/* Set seed for random values for
-+	 * spatial dithering for R,G,B channels
-+	 */
-+	REG_UPDATE(FMT_DITHER_RAND_R_SEED,
-+			FMT_RAND_R_SEED, params->r_seed_value);
-+
-+	REG_UPDATE(FMT_DITHER_RAND_G_SEED,
-+			FMT_RAND_G_SEED, params->g_seed_value);
-+
-+	REG_UPDATE(FMT_DITHER_RAND_B_SEED,
-+			FMT_RAND_B_SEED, params->b_seed_value);
-+
-+	/* FMT_OFFSET_R_Cr  31:16 0x0 Setting the zero
-+	 * offset for the R/Cr channel, lower 4LSB
-+	 * is forced to zeros. Typically set to 0
-+	 * RGB and 0x80000 YCbCr.
-+	 */
-+	/* FMT_OFFSET_G_Y   31:16 0x0 Setting the zero
-+	 * offset for the G/Y  channel, lower 4LSB is
-+	 * forced to zeros. Typically set to 0 RGB
-+	 * and 0x80000 YCbCr.
-+	 */
-+	/* FMT_OFFSET_B_Cb  31:16 0x0 Setting the zero
-+	 * offset for the B/Cb channel, lower 4LSB is
-+	 * forced to zeros. Typically set to 0 RGB and
-+	 * 0x80000 YCbCr.
-+	 */
-+
-+	/* Disable High pass filter
-+	 * Reset only at startup
-+	 * Set RGB data dithered with x^28+x^3+1
-+	 */
-+	REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
-+		FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM,
-+		FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM,
-+		FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
-+
-+	/* Set spatial dithering bit depth
-+	 * Set spatial dithering mode
-+	 * (default is Seed patterrn AAAA...)
-+	 * Enable spatial dithering
-+	 */
-+	REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
-+		FMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH,
-+		FMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE,
-+		FMT_SPATIAL_DITHER_EN, 1);
-+}
-+
-+/**
-+ *	SetTemporalDither (Frame Modulation)
-+ *	1) set temporal dither depth
-+ *	2) select pattern: from hard-coded pattern or programmable pattern
-+ *	3) select optimized strips for BGR or RGB LCD sub-pixel
-+ *	4) set s matrix
-+ *	5) set t matrix
-+ *	6) set grey level for 0.25, 0.5, 0.75
-+ *	7) enable temporal dithering
-+ */
-+
-+static void set_temporal_dither(
-+	struct dce110_opp *opp110,
-+	const struct bit_depth_reduction_params *params)
-+{
-+	/*Disable temporal (frame modulation) dithering first*/
-+	REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_EN, 0,
-+		FMT_TEMPORAL_DITHER_RESET, 0,
-+		FMT_TEMPORAL_DITHER_OFFSET, 0);
-+
-+	REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_DEPTH, 0,
-+		FMT_TEMPORAL_LEVEL, 0);
-+
-+	REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
-+		FMT_25FRC_SEL, 0,
-+		FMT_50FRC_SEL, 0,
-+		FMT_75FRC_SEL, 0);
-+
-+	/* no 10bpc dither on DCE11*/
-+	if (params->flags.FRAME_MODULATION_ENABLED == 0 ||
-+		params->flags.FRAME_MODULATION_DEPTH == 2)
-+		return;
-+
-+	/* Set temporal dithering depth*/
-+	REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_DEPTH, params->flags.FRAME_MODULATION_DEPTH,
-+		FMT_TEMPORAL_DITHER_RESET, 0,
-+		FMT_TEMPORAL_DITHER_OFFSET, 0);
-+
-+	/*Select legacy pattern based on FRC and Temporal level*/
-+	if (REG(FMT_TEMPORAL_DITHER_PATTERN_CONTROL)) {
-+		REG_WRITE(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, 0);
-+		/*Set s matrix*/
-+		REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, 0);
-+		/*Set t matrix*/
-+		REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, 0);
-+	}
-+
-+	/*Select patterns for 0.25, 0.5 and 0.75 grey level*/
-+	REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_LEVEL, params->flags.TEMPORAL_LEVEL);
-+
-+	REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
-+		FMT_25FRC_SEL, params->flags.FRC25,
-+		FMT_50FRC_SEL, params->flags.FRC50,
-+		FMT_75FRC_SEL, params->flags.FRC75);
-+
-+	/*Enable bit reduction by temporal (frame modulation) dithering*/
-+	REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
-+		FMT_TEMPORAL_DITHER_EN, 1);
-+}
-+
-+/**
-+ *	Set Clamping
-+ *	1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
-+ *		1 for 8 bpc
-+ *		2 for 10 bpc
-+ *		3 for 12 bpc
-+ *		7 for programable
-+ *	2) Enable clamp if Limited range requested
-+ */
-+void dce110_opp_set_clamping(
-+	struct dce110_opp *opp110,
-+	const struct clamping_and_pixel_encoding_params *params)
-+{
-+	REG_SET_2(FMT_CLAMP_CNTL, 0,
-+		FMT_CLAMP_DATA_EN, 0,
-+		FMT_CLAMP_COLOR_FORMAT, 0);
-+
-+	switch (params->clamping_level) {
-+	case CLAMPING_FULL_RANGE:
-+		break;
-+	case CLAMPING_LIMITED_RANGE_8BPC:
-+		REG_SET_2(FMT_CLAMP_CNTL, 0,
-+			FMT_CLAMP_DATA_EN, 1,
-+			FMT_CLAMP_COLOR_FORMAT, 1);
-+		break;
-+	case CLAMPING_LIMITED_RANGE_10BPC:
-+		REG_SET_2(FMT_CLAMP_CNTL, 0,
-+			FMT_CLAMP_DATA_EN, 1,
-+			FMT_CLAMP_COLOR_FORMAT, 2);
-+		break;
-+	case CLAMPING_LIMITED_RANGE_12BPC:
-+		REG_SET_2(FMT_CLAMP_CNTL, 0,
-+			FMT_CLAMP_DATA_EN, 1,
-+			FMT_CLAMP_COLOR_FORMAT, 3);
-+		break;
-+	case CLAMPING_LIMITED_RANGE_PROGRAMMABLE:
-+		/*Set clamp control*/
-+		REG_SET_2(FMT_CLAMP_CNTL, 0,
-+			FMT_CLAMP_DATA_EN, 1,
-+			FMT_CLAMP_COLOR_FORMAT, 7);
-+
-+		/*set the defaults*/
-+		REG_SET_2(FMT_CLAMP_COMPONENT_R, 0,
-+			FMT_CLAMP_LOWER_R, 0x10,
-+			FMT_CLAMP_UPPER_R, 0xFEF);
-+
-+		REG_SET_2(FMT_CLAMP_COMPONENT_G, 0,
-+			FMT_CLAMP_LOWER_G, 0x10,
-+			FMT_CLAMP_UPPER_G, 0xFEF);
-+
-+		REG_SET_2(FMT_CLAMP_COMPONENT_B, 0,
-+			FMT_CLAMP_LOWER_B, 0x10,
-+			FMT_CLAMP_UPPER_B, 0xFEF);
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+/**
-+ *	set_pixel_encoding
-+ *
-+ *	Set Pixel Encoding
-+ *		0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
-+ *		1: YCbCr 4:2:2
-+ */
-+static void set_pixel_encoding(
-+	struct dce110_opp *opp110,
-+	const struct clamping_and_pixel_encoding_params *params)
-+{
-+	if (opp110->opp_mask->FMT_CBCR_BIT_REDUCTION_BYPASS)
-+		REG_UPDATE_3(FMT_CONTROL,
-+				FMT_PIXEL_ENCODING, 0,
-+				FMT_SUBSAMPLING_MODE, 0,
-+				FMT_CBCR_BIT_REDUCTION_BYPASS, 0);
-+	else
-+		REG_UPDATE_2(FMT_CONTROL,
-+				FMT_PIXEL_ENCODING, 0,
-+				FMT_SUBSAMPLING_MODE, 0);
-+
-+	if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
-+		REG_UPDATE_2(FMT_CONTROL,
-+				FMT_PIXEL_ENCODING, 1,
-+				FMT_SUBSAMPLING_ORDER, 0);
-+	}
-+	if (params->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
-+		REG_UPDATE_3(FMT_CONTROL,
-+				FMT_PIXEL_ENCODING, 2,
-+				FMT_SUBSAMPLING_MODE, 2,
-+				FMT_CBCR_BIT_REDUCTION_BYPASS, 1);
-+	}
-+
-+}
-+
-+void dce110_opp_program_bit_depth_reduction(
-+	struct output_pixel_processor *opp,
-+	const struct bit_depth_reduction_params *params)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+
-+	set_truncation(opp110, params);
-+	set_spatial_dither(opp110, params);
-+	set_temporal_dither(opp110, params);
-+}
-+
-+void dce110_opp_program_clamping_and_pixel_encoding(
-+	struct output_pixel_processor *opp,
-+	const struct clamping_and_pixel_encoding_params *params)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+
-+	dce110_opp_set_clamping(opp110, params);
-+	set_pixel_encoding(opp110, params);
-+}
-+
-+static void program_formatter_420_memory(struct output_pixel_processor *opp)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+	uint32_t fmt_mem_cntl_value;
-+
-+	/* Program source select*/
-+	/* Use HW default source select for FMT_MEMORYx_CONTROL */
-+	/* Use that value for FMT_SRC_SELECT as well*/
-+	REG_GET(CONTROL,
-+			FMT420_MEM0_SOURCE_SEL, &fmt_mem_cntl_value);
-+
-+	REG_UPDATE(FMT_CONTROL,
-+			FMT_SRC_SELECT, fmt_mem_cntl_value);
-+
-+	/* Turn on the memory */
-+	REG_UPDATE(CONTROL,
-+			FMT420_MEM0_PWR_FORCE, 0);
-+}
-+
-+void dce110_opp_set_dyn_expansion(
-+	struct output_pixel_processor *opp,
-+	enum dc_color_space color_sp,
-+	enum dc_color_depth color_dpth,
-+	enum signal_type signal)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+
-+	REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
-+			FMT_DYNAMIC_EXP_EN, 0,
-+			FMT_DYNAMIC_EXP_MODE, 0);
-+
-+	/*00 - 10-bit -> 12-bit dynamic expansion*/
-+	/*01 - 8-bit  -> 12-bit dynamic expansion*/
-+	if (signal == SIGNAL_TYPE_HDMI_TYPE_A ||
-+		signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+		signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
-+		switch (color_dpth) {
-+		case COLOR_DEPTH_888:
-+			REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
-+				FMT_DYNAMIC_EXP_EN, 1,
-+				FMT_DYNAMIC_EXP_MODE, 1);
-+			break;
-+		case COLOR_DEPTH_101010:
-+			REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
-+				FMT_DYNAMIC_EXP_EN, 1,
-+				FMT_DYNAMIC_EXP_MODE, 0);
-+			break;
-+		case COLOR_DEPTH_121212:
-+			REG_UPDATE_2(
-+				FMT_DYNAMIC_EXP_CNTL,
-+				FMT_DYNAMIC_EXP_EN, 1,/*otherwise last two bits are zero*/
-+				FMT_DYNAMIC_EXP_MODE, 0);
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+}
-+
-+static void program_formatter_reset_dig_resync_fifo(struct output_pixel_processor *opp)
-+{
-+	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
-+
-+	/* clear previous phase lock status*/
-+	REG_UPDATE(FMT_CONTROL,
-+			FMT_420_PIXEL_PHASE_LOCKED_CLEAR, 1);
-+
-+	/* poll until FMT_420_PIXEL_PHASE_LOCKED become 1*/
-+	REG_WAIT(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, 1, 10, 10);
-+
-+}
-+
-+void dce110_opp_program_fmt(
-+	struct output_pixel_processor *opp,
-+	struct bit_depth_reduction_params *fmt_bit_depth,
-+	struct clamping_and_pixel_encoding_params *clamping)
-+{
-+	/* dithering is affected by <CrtcSourceSelect>, hence should be
-+	 * programmed afterwards */
-+
-+	if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
-+		program_formatter_420_memory(opp);
-+
-+	dce110_opp_program_bit_depth_reduction(
-+		opp,
-+		fmt_bit_depth);
-+
-+	dce110_opp_program_clamping_and_pixel_encoding(
-+		opp,
-+		clamping);
-+
-+	if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
-+		program_formatter_reset_dig_resync_fifo(opp);
-+
-+	return;
-+}
-+
-+
-+
-+
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+static const struct opp_funcs funcs = {
-+	.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
-+	.opp_destroy = dce110_opp_destroy,
-+	.opp_program_fmt = dce110_opp_program_fmt,
-+	.opp_program_bit_depth_reduction = dce110_opp_program_bit_depth_reduction
-+};
-+
-+void dce110_opp_construct(struct dce110_opp *opp110,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce_opp_registers *regs,
-+	const struct dce_opp_shift *opp_shift,
-+	const struct dce_opp_mask *opp_mask)
-+{
-+	opp110->base.funcs = &funcs;
-+
-+	opp110->base.ctx = ctx;
-+
-+	opp110->base.inst = inst;
-+
-+	opp110->regs = regs;
-+	opp110->opp_shift = opp_shift;
-+	opp110->opp_mask = opp_mask;
-+}
-+
-+void dce110_opp_destroy(struct output_pixel_processor **opp)
-+{
-+	if (*opp)
-+		kfree(FROM_DCE11_OPP(*opp));
-+	*opp = NULL;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h.0130~	2017-12-14 06:39:58.418903570 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h	2017-12-14 06:39:58.418903570 +0100
-@@ -0,0 +1,310 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_OPP_DCE_H__
-+#define __DC_OPP_DCE_H__
-+
-+#include "dc_types.h"
-+#include "opp.h"
-+#include "core_types.h"
-+
-+#define FROM_DCE11_OPP(opp)\
-+	container_of(opp, struct dce110_opp, base)
-+
-+enum dce110_opp_reg_type {
-+	DCE110_OPP_REG_DCP = 0,
-+	DCE110_OPP_REG_DCFE,
-+	DCE110_OPP_REG_FMT,
-+
-+	DCE110_OPP_REG_MAX
-+};
-+
-+#define OPP_COMMON_REG_LIST_BASE(id) \
-+	SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
-+	SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
-+	SRI(FMT_CONTROL, FMT, id), \
-+	SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
-+	SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
-+	SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
-+	SRI(FMT_CLAMP_CNTL, FMT, id), \
-+	SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \
-+	SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \
-+	SRI(FMT_CLAMP_COMPONENT_B, FMT, id)
-+
-+#define OPP_DCE_80_REG_LIST(id) \
-+	OPP_COMMON_REG_LIST_BASE(id), \
-+	SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
-+	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
-+	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
-+
-+#define OPP_DCE_100_REG_LIST(id) \
-+	OPP_COMMON_REG_LIST_BASE(id), \
-+	SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
-+	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
-+	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
-+
-+#define OPP_DCE_110_REG_LIST(id) \
-+	OPP_COMMON_REG_LIST_BASE(id), \
-+	SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
-+	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
-+	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
-+
-+#define OPP_DCE_112_REG_LIST(id) \
-+	OPP_COMMON_REG_LIST_BASE(id), \
-+	SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
-+	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
-+	SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \
-+	SRI(CONTROL, FMT_MEMORY, id)
-+
-+#define OPP_DCE_120_REG_LIST(id) \
-+	OPP_COMMON_REG_LIST_BASE(id), \
-+	SRI(CONTROL, FMT_MEMORY, id)
-+
-+#define OPP_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+#define OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
-+	OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\
-+	OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
-+	OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
-+	OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
-+	OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\
-+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
-+	OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\
-+	OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\
-+	OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\
-+	OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\
-+	OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\
-+	OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\
-+	OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\
-+	OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh)
-+
-+#define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\
-+	OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
-+
-+#define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\
-+	OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
-+
-+#define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
-+	OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
-+	OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\
-+	OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
-+	OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
-+
-+#define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\
-+	OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
-+
-+#define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\
-+	OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\
-+	OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
-+	OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
-+	OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
-+	OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh),\
-+	OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
-+	OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
-+	OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
-+	OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\
-+	OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\
-+	OPP_SF(FMT0_FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
-+	OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\
-+	OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\
-+	OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\
-+	OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\
-+	OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\
-+	OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\
-+	OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\
-+	OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\
-+	OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\
-+	OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\
-+	OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\
-+	OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\
-+	OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\
-+	OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh)
-+
-+#define OPP_REG_FIELD_LIST(type) \
-+	type FMT_DYNAMIC_EXP_EN; \
-+	type FMT_DYNAMIC_EXP_MODE; \
-+	type FMT_TRUNCATE_EN; \
-+	type FMT_TRUNCATE_DEPTH; \
-+	type FMT_TRUNCATE_MODE; \
-+	type FMT_SPATIAL_DITHER_EN; \
-+	type FMT_SPATIAL_DITHER_DEPTH; \
-+	type FMT_SPATIAL_DITHER_MODE; \
-+	type FMT_TEMPORAL_DITHER_EN; \
-+	type FMT_TEMPORAL_DITHER_RESET; \
-+	type FMT_TEMPORAL_DITHER_OFFSET; \
-+	type FMT_TEMPORAL_DITHER_DEPTH; \
-+	type FMT_TEMPORAL_LEVEL; \
-+	type FMT_25FRC_SEL; \
-+	type FMT_50FRC_SEL; \
-+	type FMT_75FRC_SEL; \
-+	type FMT_HIGHPASS_RANDOM_ENABLE; \
-+	type FMT_FRAME_RANDOM_ENABLE; \
-+	type FMT_RGB_RANDOM_ENABLE; \
-+	type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \
-+	type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \
-+	type FMT_STEREOSYNC_OVERRIDE; \
-+	type FMT_RAND_R_SEED; \
-+	type FMT_RAND_G_SEED; \
-+	type FMT_RAND_B_SEED; \
-+	type FMT420_MEM0_SOURCE_SEL; \
-+	type FMT420_MEM0_PWR_FORCE; \
-+	type FMT_SRC_SELECT; \
-+	type FMT_420_PIXEL_PHASE_LOCKED_CLEAR; \
-+	type FMT_420_PIXEL_PHASE_LOCKED; \
-+	type FMT_CLAMP_DATA_EN; \
-+	type FMT_CLAMP_COLOR_FORMAT; \
-+	type FMT_CLAMP_LOWER_R; \
-+	type FMT_CLAMP_UPPER_R; \
-+	type FMT_CLAMP_LOWER_G; \
-+	type FMT_CLAMP_UPPER_G; \
-+	type FMT_CLAMP_LOWER_B; \
-+	type FMT_CLAMP_UPPER_B; \
-+	type FMT_PIXEL_ENCODING; \
-+	type FMT_SUBSAMPLING_ORDER; \
-+	type FMT_SUBSAMPLING_MODE; \
-+	type FMT_CBCR_BIT_REDUCTION_BYPASS;\
-+
-+struct dce_opp_shift {
-+	OPP_REG_FIELD_LIST(uint8_t)
-+};
-+
-+struct dce_opp_mask {
-+	OPP_REG_FIELD_LIST(uint32_t)
-+};
-+
-+struct dce_opp_registers {
-+	uint32_t FMT_DYNAMIC_EXP_CNTL;
-+	uint32_t FMT_BIT_DEPTH_CONTROL;
-+	uint32_t FMT_CONTROL;
-+	uint32_t FMT_DITHER_RAND_R_SEED;
-+	uint32_t FMT_DITHER_RAND_G_SEED;
-+	uint32_t FMT_DITHER_RAND_B_SEED;
-+	uint32_t FMT_TEMPORAL_DITHER_PATTERN_CONTROL;
-+	uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX;
-+	uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX;
-+	uint32_t CONTROL;
-+	uint32_t FMT_CLAMP_CNTL;
-+	uint32_t FMT_CLAMP_COMPONENT_R;
-+	uint32_t FMT_CLAMP_COMPONENT_G;
-+	uint32_t FMT_CLAMP_COMPONENT_B;
-+};
-+
-+/* OPP RELATED */
-+#define TO_DCE110_OPP(opp)\
-+	container_of(opp, struct dce110_opp, base)
-+
-+struct dce110_opp {
-+	struct output_pixel_processor base;
-+	const struct dce_opp_registers *regs;
-+	const struct dce_opp_shift *opp_shift;
-+	const struct dce_opp_mask *opp_mask;
-+};
-+
-+void dce110_opp_construct(struct dce110_opp *opp110,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce_opp_registers *regs,
-+	const struct dce_opp_shift *opp_shift,
-+	const struct dce_opp_mask *opp_mask);
-+
-+void dce110_opp_destroy(struct output_pixel_processor **opp);
-+
-+
-+
-+/* FORMATTER RELATED */
-+void dce110_opp_program_bit_depth_reduction(
-+	struct output_pixel_processor *opp,
-+	const struct bit_depth_reduction_params *params);
-+
-+void dce110_opp_program_clamping_and_pixel_encoding(
-+	struct output_pixel_processor *opp,
-+	const struct clamping_and_pixel_encoding_params *params);
-+
-+void dce110_opp_set_dyn_expansion(
-+	struct output_pixel_processor *opp,
-+	enum dc_color_space color_sp,
-+	enum dc_color_depth color_dpth,
-+	enum signal_type signal);
-+
-+void dce110_opp_program_fmt(
-+	struct output_pixel_processor *opp,
-+	struct bit_depth_reduction_params *fmt_bit_depth,
-+	struct clamping_and_pixel_encoding_params *clamping);
-+
-+void dce110_opp_set_clamping(
-+	struct dce110_opp *opp110,
-+	const struct clamping_and_pixel_encoding_params *params);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c.0130~	2017-12-14 06:39:58.418903570 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c	2017-12-14 06:39:58.418903570 +0100
-@@ -0,0 +1,1119 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "transform.h"
-+
-+static const uint16_t filter_2tap_16p[18] = {
-+	4096, 0,
-+	3840, 256,
-+	3584, 512,
-+	3328, 768,
-+	3072, 1024,
-+	2816, 1280,
-+	2560, 1536,
-+	2304, 1792,
-+	2048, 2048
-+};
-+
-+static const uint16_t filter_3tap_16p_upscale[27] = {
-+	2048, 2048, 0,
-+	1708, 2424, 16348,
-+	1372, 2796, 16308,
-+	1056, 3148, 16272,
-+	768, 3464, 16244,
-+	512, 3728, 16236,
-+	296, 3928, 16252,
-+	124, 4052, 16296,
-+	0, 4096, 0
-+};
-+
-+static const uint16_t filter_3tap_16p_117[27] = {
-+	2048, 2048, 0,
-+	1824, 2276, 16376,
-+	1600, 2496, 16380,
-+	1376, 2700, 16,
-+	1156, 2880, 52,
-+	948, 3032, 108,
-+	756, 3144, 192,
-+	580, 3212, 296,
-+	428, 3236, 428
-+};
-+
-+static const uint16_t filter_3tap_16p_150[27] = {
-+	2048, 2048, 0,
-+	1872, 2184, 36,
-+	1692, 2308, 88,
-+	1516, 2420, 156,
-+	1340, 2516, 236,
-+	1168, 2592, 328,
-+	1004, 2648, 440,
-+	844, 2684, 560,
-+	696, 2696, 696
-+};
-+
-+static const uint16_t filter_3tap_16p_183[27] = {
-+	2048, 2048, 0,
-+	1892, 2104, 92,
-+	1744, 2152, 196,
-+	1592, 2196, 300,
-+	1448, 2232, 412,
-+	1304, 2256, 528,
-+	1168, 2276, 648,
-+	1032, 2288, 772,
-+	900, 2292, 900
-+};
-+
-+static const uint16_t filter_4tap_16p_upscale[36] = {
-+	0, 4096, 0, 0,
-+	16240, 4056, 180, 16380,
-+	16136, 3952, 404, 16364,
-+	16072, 3780, 664, 16344,
-+	16040, 3556, 952, 16312,
-+	16036, 3284, 1268, 16272,
-+	16052, 2980, 1604, 16224,
-+	16084, 2648, 1952, 16176,
-+	16128, 2304, 2304, 16128
-+};
-+
-+static const uint16_t filter_4tap_16p_117[36] = {
-+	428, 3236, 428, 0,
-+	276, 3232, 604, 16364,
-+	148, 3184, 800, 16340,
-+	44, 3104, 1016, 16312,
-+	16344, 2984, 1244, 16284,
-+	16284, 2832, 1488, 16256,
-+	16244, 2648, 1732, 16236,
-+	16220, 2440, 1976, 16220,
-+	16212, 2216, 2216, 16212
-+};
-+
-+static const uint16_t filter_4tap_16p_150[36] = {
-+	696, 2700, 696, 0,
-+	560, 2700, 848, 16364,
-+	436, 2676, 1008, 16348,
-+	328, 2628, 1180, 16336,
-+	232, 2556, 1356, 16328,
-+	152, 2460, 1536, 16328,
-+	84, 2344, 1716, 16332,
-+	28, 2208, 1888, 16348,
-+	16376, 2052, 2052, 16376
-+};
-+
-+static const uint16_t filter_4tap_16p_183[36] = {
-+	940, 2208, 940, 0,
-+	832, 2200, 1052, 4,
-+	728, 2180, 1164, 16,
-+	628, 2148, 1280, 36,
-+	536, 2100, 1392, 60,
-+	448, 2044, 1504, 92,
-+	368, 1976, 1612, 132,
-+	296, 1900, 1716, 176,
-+	232, 1812, 1812, 232
-+};
-+
-+static const uint16_t filter_2tap_64p[66] = {
-+	4096, 0,
-+	4032, 64,
-+	3968, 128,
-+	3904, 192,
-+	3840, 256,
-+	3776, 320,
-+	3712, 384,
-+	3648, 448,
-+	3584, 512,
-+	3520, 576,
-+	3456, 640,
-+	3392, 704,
-+	3328, 768,
-+	3264, 832,
-+	3200, 896,
-+	3136, 960,
-+	3072, 1024,
-+	3008, 1088,
-+	2944, 1152,
-+	2880, 1216,
-+	2816, 1280,
-+	2752, 1344,
-+	2688, 1408,
-+	2624, 1472,
-+	2560, 1536,
-+	2496, 1600,
-+	2432, 1664,
-+	2368, 1728,
-+	2304, 1792,
-+	2240, 1856,
-+	2176, 1920,
-+	2112, 1984,
-+	2048, 2048 };
-+
-+static const uint16_t filter_3tap_64p_upscale[99] = {
-+	2048, 2048, 0,
-+	1960, 2140, 16376,
-+	1876, 2236, 16364,
-+	1792, 2328, 16356,
-+	1708, 2424, 16348,
-+	1620, 2516, 16336,
-+	1540, 2612, 16328,
-+	1456, 2704, 16316,
-+	1372, 2796, 16308,
-+	1292, 2884, 16296,
-+	1212, 2976, 16288,
-+	1136, 3060, 16280,
-+	1056, 3148, 16272,
-+	984, 3228, 16264,
-+	908, 3312, 16256,
-+	836, 3388, 16248,
-+	768, 3464, 16244,
-+	700, 3536, 16240,
-+	636, 3604, 16236,
-+	572, 3668, 16236,
-+	512, 3728, 16236,
-+	456, 3784, 16236,
-+	400, 3836, 16240,
-+	348, 3884, 16244,
-+	296, 3928, 16252,
-+	252, 3964, 16260,
-+	204, 4000, 16268,
-+	164, 4028, 16284,
-+	124, 4052, 16296,
-+	88, 4072, 16316,
-+	56, 4084, 16336,
-+	24, 4092, 16356,
-+	0, 4096, 0
-+};
-+
-+static const uint16_t filter_3tap_64p_117[99] = {
-+	2048, 2048, 0,
-+	1992, 2104, 16380,
-+	1936, 2160, 16380,
-+	1880, 2220, 16376,
-+	1824, 2276, 16376,
-+	1768, 2332, 16376,
-+	1712, 2388, 16376,
-+	1656, 2444, 16376,
-+	1600, 2496, 16380,
-+	1544, 2548, 0,
-+	1488, 2600, 4,
-+	1432, 2652, 8,
-+	1376, 2700, 16,
-+	1320, 2748, 20,
-+	1264, 2796, 32,
-+	1212, 2840, 40,
-+	1156, 2880, 52,
-+	1104, 2920, 64,
-+	1052, 2960, 80,
-+	1000, 2996, 92,
-+	948, 3032, 108,
-+	900, 3060, 128,
-+	852, 3092, 148,
-+	804, 3120, 168,
-+	756, 3144, 192,
-+	712, 3164, 216,
-+	668, 3184, 240,
-+	624, 3200, 268,
-+	580, 3212, 296,
-+	540, 3220, 328,
-+	500, 3228, 360,
-+	464, 3232, 392,
-+	428, 3236, 428
-+};
-+
-+static const uint16_t filter_3tap_64p_150[99] = {
-+	2048, 2048, 0,
-+	2004, 2080, 8,
-+	1960, 2116, 16,
-+	1916, 2148, 28,
-+	1872, 2184, 36,
-+	1824, 2216, 48,
-+	1780, 2248, 60,
-+	1736, 2280, 76,
-+	1692, 2308, 88,
-+	1648, 2336, 104,
-+	1604, 2368, 120,
-+	1560, 2392, 136,
-+	1516, 2420, 156,
-+	1472, 2444, 172,
-+	1428, 2472, 192,
-+	1384, 2492, 212,
-+	1340, 2516, 236,
-+	1296, 2536, 256,
-+	1252, 2556, 280,
-+	1212, 2576, 304,
-+	1168, 2592, 328,
-+	1124, 2608, 356,
-+	1084, 2624, 384,
-+	1044, 2636, 412,
-+	1004, 2648, 440,
-+	964, 2660, 468,
-+	924, 2668, 500,
-+	884, 2676, 528,
-+	844, 2684, 560,
-+	808, 2688, 596,
-+	768, 2692, 628,
-+	732, 2696, 664,
-+	696, 2696, 696
-+};
-+
-+static const uint16_t filter_3tap_64p_183[99] = {
-+	2048, 2048, 0,
-+	2008, 2060, 20,
-+	1968, 2076, 44,
-+	1932, 2088, 68,
-+	1892, 2104, 92,
-+	1856, 2116, 120,
-+	1816, 2128, 144,
-+	1780, 2140, 168,
-+	1744, 2152, 196,
-+	1704, 2164, 220,
-+	1668, 2176, 248,
-+	1632, 2188, 272,
-+	1592, 2196, 300,
-+	1556, 2204, 328,
-+	1520, 2216, 356,
-+	1484, 2224, 384,
-+	1448, 2232, 412,
-+	1412, 2240, 440,
-+	1376, 2244, 468,
-+	1340, 2252, 496,
-+	1304, 2256, 528,
-+	1272, 2264, 556,
-+	1236, 2268, 584,
-+	1200, 2272, 616,
-+	1168, 2276, 648,
-+	1132, 2280, 676,
-+	1100, 2284, 708,
-+	1064, 2288, 740,
-+	1032, 2288, 772,
-+	996, 2292, 800,
-+	964, 2292, 832,
-+	932, 2292, 868,
-+	900, 2292, 900
-+};
-+
-+static const uint16_t filter_4tap_64p_upscale[132] = {
-+	0, 4096, 0, 0,
-+	16344, 4092, 40, 0,
-+	16308, 4084, 84, 16380,
-+	16272, 4072, 132, 16380,
-+	16240, 4056, 180, 16380,
-+	16212, 4036, 232, 16376,
-+	16184, 4012, 288, 16372,
-+	16160, 3984, 344, 16368,
-+	16136, 3952, 404, 16364,
-+	16116, 3916, 464, 16360,
-+	16100, 3872, 528, 16356,
-+	16084, 3828, 596, 16348,
-+	16072, 3780, 664, 16344,
-+	16060, 3728, 732, 16336,
-+	16052, 3676, 804, 16328,
-+	16044, 3616, 876, 16320,
-+	16040, 3556, 952, 16312,
-+	16036, 3492, 1028, 16300,
-+	16032, 3424, 1108, 16292,
-+	16032, 3356, 1188, 16280,
-+	16036, 3284, 1268, 16272,
-+	16036, 3212, 1352, 16260,
-+	16040, 3136, 1436, 16248,
-+	16044, 3056, 1520, 16236,
-+	16052, 2980, 1604, 16224,
-+	16060, 2896, 1688, 16212,
-+	16064, 2816, 1776, 16200,
-+	16076, 2732, 1864, 16188,
-+	16084, 2648, 1952, 16176,
-+	16092, 2564, 2040, 16164,
-+	16104, 2476, 2128, 16152,
-+	16116, 2388, 2216, 16140,
-+	16128, 2304, 2304, 16128 };
-+
-+static const uint16_t filter_4tap_64p_117[132] = {
-+	420, 3248, 420, 0,
-+	380, 3248, 464, 16380,
-+	344, 3248, 508, 16372,
-+	308, 3248, 552, 16368,
-+	272, 3240, 596, 16364,
-+	236, 3236, 644, 16356,
-+	204, 3224, 692, 16352,
-+	172, 3212, 744, 16344,
-+	144, 3196, 796, 16340,
-+	116, 3180, 848, 16332,
-+	88, 3160, 900, 16324,
-+	60, 3136, 956, 16320,
-+	36, 3112, 1012, 16312,
-+	16, 3084, 1068, 16304,
-+	16380, 3056, 1124, 16296,
-+	16360, 3024, 1184, 16292,
-+	16340, 2992, 1244, 16284,
-+	16324, 2956, 1304, 16276,
-+	16308, 2920, 1364, 16268,
-+	16292, 2880, 1424, 16264,
-+	16280, 2836, 1484, 16256,
-+	16268, 2792, 1548, 16252,
-+	16256, 2748, 1608, 16244,
-+	16248, 2700, 1668, 16240,
-+	16240, 2652, 1732, 16232,
-+	16232, 2604, 1792, 16228,
-+	16228, 2552, 1856, 16224,
-+	16220, 2500, 1916, 16220,
-+	16216, 2444, 1980, 16216,
-+	16216, 2388, 2040, 16216,
-+	16212, 2332, 2100, 16212,
-+	16212, 2276, 2160, 16212,
-+	16212, 2220, 2220, 16212 };
-+
-+static const uint16_t filter_4tap_64p_150[132] = {
-+	696, 2700, 696, 0,
-+	660, 2704, 732, 16380,
-+	628, 2704, 768, 16376,
-+	596, 2704, 804, 16372,
-+	564, 2700, 844, 16364,
-+	532, 2696, 884, 16360,
-+	500, 2692, 924, 16356,
-+	472, 2684, 964, 16352,
-+	440, 2676, 1004, 16352,
-+	412, 2668, 1044, 16348,
-+	384, 2656, 1088, 16344,
-+	360, 2644, 1128, 16340,
-+	332, 2632, 1172, 16336,
-+	308, 2616, 1216, 16336,
-+	284, 2600, 1260, 16332,
-+	260, 2580, 1304, 16332,
-+	236, 2560, 1348, 16328,
-+	216, 2540, 1392, 16328,
-+	196, 2516, 1436, 16328,
-+	176, 2492, 1480, 16324,
-+	156, 2468, 1524, 16324,
-+	136, 2440, 1568, 16328,
-+	120, 2412, 1612, 16328,
-+	104, 2384, 1656, 16328,
-+	88, 2352, 1700, 16332,
-+	72, 2324, 1744, 16332,
-+	60, 2288, 1788, 16336,
-+	48, 2256, 1828, 16340,
-+	36, 2220, 1872, 16344,
-+	24, 2184, 1912, 16352,
-+	12, 2148, 1952, 16356,
-+	4, 2112, 1996, 16364,
-+	16380, 2072, 2036, 16372 };
-+
-+static const uint16_t filter_4tap_64p_183[132] = {
-+	944, 2204, 944, 0,
-+	916, 2204, 972, 0,
-+	888, 2200, 996, 0,
-+	860, 2200, 1024, 4,
-+	832, 2196, 1052, 4,
-+	808, 2192, 1080, 8,
-+	780, 2188, 1108, 12,
-+	756, 2180, 1140, 12,
-+	728, 2176, 1168, 16,
-+	704, 2168, 1196, 20,
-+	680, 2160, 1224, 24,
-+	656, 2152, 1252, 28,
-+	632, 2144, 1280, 36,
-+	608, 2132, 1308, 40,
-+	584, 2120, 1336, 48,
-+	560, 2112, 1364, 52,
-+	536, 2096, 1392, 60,
-+	516, 2084, 1420, 68,
-+	492, 2072, 1448, 76,
-+	472, 2056, 1476, 84,
-+	452, 2040, 1504, 92,
-+	428, 2024, 1532, 100,
-+	408, 2008, 1560, 112,
-+	392, 1992, 1584, 120,
-+	372, 1972, 1612, 132,
-+	352, 1956, 1636, 144,
-+	336, 1936, 1664, 156,
-+	316, 1916, 1688, 168,
-+	300, 1896, 1712, 180,
-+	284, 1876, 1736, 192,
-+	268, 1852, 1760, 208,
-+	252, 1832, 1784, 220,
-+	236, 1808, 1808, 236 };
-+
-+static const uint16_t filter_5tap_64p_upscale[165] = {
-+	15936, 2496, 2496, 15936, 0,
-+	15948, 2404, 2580, 15924, 0,
-+	15960, 2312, 2664, 15912, 4,
-+	15976, 2220, 2748, 15904, 8,
-+	15992, 2128, 2832, 15896, 12,
-+	16004, 2036, 2912, 15888, 16,
-+	16020, 1944, 2992, 15880, 20,
-+	16036, 1852, 3068, 15876, 20,
-+	16056, 1760, 3140, 15876, 24,
-+	16072, 1668, 3216, 15872, 28,
-+	16088, 1580, 3284, 15872, 32,
-+	16104, 1492, 3352, 15876, 32,
-+	16120, 1404, 3420, 15876, 36,
-+	16140, 1316, 3480, 15884, 40,
-+	16156, 1228, 3540, 15892, 40,
-+	16172, 1144, 3600, 15900, 40,
-+	16188, 1060, 3652, 15908, 44,
-+	16204, 980, 3704, 15924, 44,
-+	16220, 900, 3756, 15936, 44,
-+	16236, 824, 3800, 15956, 44,
-+	16248, 744, 3844, 15972, 44,
-+	16264, 672, 3884, 15996, 44,
-+	16276, 600, 3920, 16020, 44,
-+	16292, 528, 3952, 16044, 40,
-+	16304, 460, 3980, 16072, 40,
-+	16316, 396, 4008, 16104, 36,
-+	16328, 332, 4032, 16136, 32,
-+	16336, 272, 4048, 16172, 28,
-+	16348, 212, 4064, 16208, 24,
-+	16356, 156, 4080, 16248, 16,
-+	16368, 100, 4088, 16292, 12,
-+	16376, 48, 4092, 16336, 4,
-+	0, 0, 4096, 0, 0 };
-+
-+static const uint16_t filter_5tap_64p_117[165] = {
-+	16056, 2372, 2372, 16056, 0,
-+	16052, 2312, 2432, 16060, 0,
-+	16052, 2252, 2488, 16064, 0,
-+	16052, 2188, 2548, 16072, 0,
-+	16052, 2124, 2600, 16076, 0,
-+	16052, 2064, 2656, 16088, 0,
-+	16052, 2000, 2708, 16096, 0,
-+	16056, 1932, 2760, 16108, 0,
-+	16060, 1868, 2808, 16120, 0,
-+	16064, 1804, 2856, 16132, 0,
-+	16068, 1740, 2904, 16148, 16380,
-+	16076, 1676, 2948, 16164, 16380,
-+	16080, 1612, 2992, 16180, 16376,
-+	16088, 1544, 3032, 16200, 16372,
-+	16096, 1480, 3072, 16220, 16372,
-+	16104, 1420, 3108, 16244, 16368,
-+	16112, 1356, 3144, 16268, 16364,
-+	16120, 1292, 3180, 16292, 16360,
-+	16128, 1232, 3212, 16320, 16356,
-+	16136, 1168, 3240, 16344, 16352,
-+	16144, 1108, 3268, 16376, 16344,
-+	16156, 1048, 3292, 20, 16340,
-+	16164, 988, 3316, 52, 16332,
-+	16172, 932, 3336, 88, 16328,
-+	16184, 872, 3356, 124, 16320,
-+	16192, 816, 3372, 160, 16316,
-+	16204, 760, 3388, 196, 16308,
-+	16212, 708, 3400, 236, 16300,
-+	16220, 656, 3412, 276, 16292,
-+	16232, 604, 3420, 320, 16284,
-+	16240, 552, 3424, 364, 16276,
-+	16248, 504, 3428, 408, 16268,
-+	16256, 456, 3428, 456, 16256 };
-+
-+static const uint16_t filter_5tap_64p_150[165] = {
-+	16368, 2064, 2064, 16368, 0,
-+	16352, 2028, 2100, 16380, 16380,
-+	16340, 1996, 2132, 12, 16376,
-+	16328, 1960, 2168, 24, 16376,
-+	16316, 1924, 2204, 44, 16372,
-+	16308, 1888, 2236, 60, 16368,
-+	16296, 1848, 2268, 76, 16364,
-+	16288, 1812, 2300, 96, 16360,
-+	16280, 1772, 2328, 116, 16356,
-+	16272, 1736, 2360, 136, 16352,
-+	16268, 1696, 2388, 160, 16348,
-+	16260, 1656, 2416, 180, 16344,
-+	16256, 1616, 2440, 204, 16340,
-+	16248, 1576, 2464, 228, 16336,
-+	16244, 1536, 2492, 252, 16332,
-+	16240, 1496, 2512, 276, 16324,
-+	16240, 1456, 2536, 304, 16320,
-+	16236, 1416, 2556, 332, 16316,
-+	16232, 1376, 2576, 360, 16312,
-+	16232, 1336, 2592, 388, 16308,
-+	16232, 1296, 2612, 416, 16300,
-+	16232, 1256, 2628, 448, 16296,
-+	16232, 1216, 2640, 480, 16292,
-+	16232, 1172, 2652, 512, 16288,
-+	16232, 1132, 2664, 544, 16284,
-+	16232, 1092, 2676, 576, 16280,
-+	16236, 1056, 2684, 608, 16272,
-+	16236, 1016, 2692, 644, 16268,
-+	16240, 976, 2700, 680, 16264,
-+	16240, 936, 2704, 712, 16260,
-+	16244, 900, 2708, 748, 16256,
-+	16248, 860, 2708, 788, 16252,
-+	16248, 824, 2708, 824, 16248 };
-+
-+static const uint16_t filter_5tap_64p_183[165] = {
-+	228, 1816, 1816, 228, 0,
-+	216, 1792, 1836, 248, 16380,
-+	200, 1772, 1860, 264, 16376,
-+	184, 1748, 1884, 280, 16376,
-+	168, 1728, 1904, 300, 16372,
-+	156, 1704, 1928, 316, 16368,
-+	144, 1680, 1948, 336, 16364,
-+	128, 1656, 1968, 356, 16364,
-+	116, 1632, 1988, 376, 16360,
-+	104, 1604, 2008, 396, 16356,
-+	96, 1580, 2024, 416, 16356,
-+	84, 1556, 2044, 440, 16352,
-+	72, 1528, 2060, 460, 16348,
-+	64, 1504, 2076, 484, 16348,
-+	52, 1476, 2092, 504, 16344,
-+	44, 1448, 2104, 528, 16344,
-+	36, 1424, 2120, 552, 16340,
-+	28, 1396, 2132, 576, 16340,
-+	20, 1368, 2144, 600, 16340,
-+	12, 1340, 2156, 624, 16336,
-+	4, 1312, 2168, 652, 16336,
-+	0, 1284, 2180, 676, 16336,
-+	16376, 1256, 2188, 700, 16332,
-+	16372, 1228, 2196, 728, 16332,
-+	16368, 1200, 2204, 752, 16332,
-+	16364, 1172, 2212, 780, 16332,
-+	16356, 1144, 2216, 808, 16332,
-+	16352, 1116, 2220, 836, 16332,
-+	16352, 1084, 2224, 860, 16332,
-+	16348, 1056, 2228, 888, 16336,
-+	16344, 1028, 2232, 916, 16336,
-+	16340, 1000, 2232, 944, 16336,
-+	16340, 972, 2232, 972, 16340 };
-+
-+static const uint16_t filter_6tap_64p_upscale[198] = {
-+	0, 0, 4092, 0, 0, 0,
-+	12, 16332, 4092, 52, 16368, 0,
-+	24, 16280, 4088, 108, 16356, 0,
-+	36, 16236, 4080, 168, 16340, 0,
-+	44, 16188, 4064, 228, 16324, 0,
-+	56, 16148, 4052, 292, 16308, 0,
-+	64, 16108, 4032, 356, 16292, 4,
-+	72, 16072, 4008, 424, 16276, 4,
-+	80, 16036, 3980, 492, 16256, 4,
-+	88, 16004, 3952, 564, 16240, 8,
-+	96, 15972, 3920, 636, 16220, 8,
-+	100, 15944, 3884, 712, 16204, 12,
-+	108, 15916, 3844, 788, 16184, 16,
-+	112, 15896, 3800, 864, 16164, 20,
-+	116, 15872, 3756, 944, 16144, 20,
-+	120, 15852, 3708, 1024, 16124, 24,
-+	120, 15836, 3656, 1108, 16104, 28,
-+	124, 15824, 3600, 1192, 16084, 32,
-+	124, 15808, 3544, 1276, 16064, 36,
-+	124, 15800, 3484, 1360, 16044, 40,
-+	128, 15792, 3420, 1448, 16024, 44,
-+	128, 15784, 3352, 1536, 16004, 48,
-+	124, 15780, 3288, 1624, 15988, 52,
-+	124, 15776, 3216, 1712, 15968, 56,
-+	124, 15776, 3144, 1800, 15948, 64,
-+	120, 15776, 3068, 1888, 15932, 68,
-+	120, 15780, 2992, 1976, 15912, 72,
-+	116, 15784, 2916, 2064, 15896, 76,
-+	112, 15792, 2836, 2152, 15880, 80,
-+	108, 15796, 2752, 2244, 15868, 84,
-+	104, 15804, 2672, 2328, 15852, 88,
-+	104, 15816, 2588, 2416, 15840, 92,
-+	100, 15828, 2504, 2504, 15828, 100 };
-+
-+static const uint16_t filter_6tap_64p_117[198] = {
-+	16168, 476, 3568, 476, 16168, 0,
-+	16180, 428, 3564, 528, 16156, 0,
-+	16192, 376, 3556, 584, 16144, 4,
-+	16204, 328, 3548, 636, 16128, 4,
-+	16216, 280, 3540, 692, 16116, 8,
-+	16228, 232, 3524, 748, 16104, 12,
-+	16240, 188, 3512, 808, 16092, 12,
-+	16252, 148, 3492, 864, 16080, 16,
-+	16264, 104, 3472, 924, 16068, 16,
-+	16276, 64, 3452, 984, 16056, 20,
-+	16284, 28, 3428, 1044, 16048, 24,
-+	16296, 16376, 3400, 1108, 16036, 24,
-+	16304, 16340, 3372, 1168, 16024, 28,
-+	16316, 16304, 3340, 1232, 16016, 32,
-+	16324, 16272, 3308, 1296, 16004, 32,
-+	16332, 16244, 3272, 1360, 15996, 36,
-+	16344, 16212, 3236, 1424, 15988, 36,
-+	16352, 16188, 3200, 1488, 15980, 40,
-+	16360, 16160, 3160, 1552, 15972, 40,
-+	16368, 16136, 3116, 1616, 15964, 40,
-+	16372, 16112, 3072, 1680, 15956, 44,
-+	16380, 16092, 3028, 1744, 15952, 44,
-+	0, 16072, 2980, 1808, 15948, 44,
-+	8, 16052, 2932, 1872, 15944, 48,
-+	12, 16036, 2880, 1936, 15940, 48,
-+	16, 16020, 2828, 2000, 15936, 48,
-+	20, 16008, 2776, 2064, 15936, 48,
-+	24, 15996, 2724, 2128, 15936, 48,
-+	28, 15984, 2668, 2192, 15936, 48,
-+	32, 15972, 2612, 2252, 15940, 44,
-+	36, 15964, 2552, 2316, 15940, 44,
-+	40, 15956, 2496, 2376, 15944, 44,
-+	40, 15952, 2436, 2436, 15952, 40 };
-+
-+static const uint16_t filter_6tap_64p_150[198] = {
-+	16148, 920, 2724, 920, 16148, 0,
-+	16152, 880, 2724, 956, 16148, 0,
-+	16152, 844, 2720, 996, 16144, 0,
-+	16156, 804, 2716, 1032, 16144, 0,
-+	16156, 768, 2712, 1072, 16144, 0,
-+	16160, 732, 2708, 1112, 16144, 16380,
-+	16164, 696, 2700, 1152, 16144, 16380,
-+	16168, 660, 2692, 1192, 16148, 16380,
-+	16172, 628, 2684, 1232, 16148, 16380,
-+	16176, 592, 2672, 1272, 16152, 16376,
-+	16180, 560, 2660, 1312, 16152, 16376,
-+	16184, 524, 2648, 1348, 16156, 16376,
-+	16192, 492, 2632, 1388, 16160, 16372,
-+	16196, 460, 2616, 1428, 16164, 16372,
-+	16200, 432, 2600, 1468, 16168, 16368,
-+	16204, 400, 2584, 1508, 16176, 16364,
-+	16212, 368, 2564, 1548, 16180, 16364,
-+	16216, 340, 2544, 1588, 16188, 16360,
-+	16220, 312, 2524, 1628, 16196, 16356,
-+	16228, 284, 2504, 1668, 16204, 16356,
-+	16232, 256, 2480, 1704, 16212, 16352,
-+	16240, 232, 2456, 1744, 16224, 16348,
-+	16244, 204, 2432, 1780, 16232, 16344,
-+	16248, 180, 2408, 1820, 16244, 16340,
-+	16256, 156, 2380, 1856, 16256, 16336,
-+	16260, 132, 2352, 1896, 16268, 16332,
-+	16268, 108, 2324, 1932, 16280, 16328,
-+	16272, 88, 2296, 1968, 16292, 16324,
-+	16276, 64, 2268, 2004, 16308, 16320,
-+	16284, 44, 2236, 2036, 16324, 16312,
-+	16288, 24, 2204, 2072, 16340, 16308,
-+	16292, 8, 2172, 2108, 16356, 16304,
-+	16300, 16372, 2140, 2140, 16372, 16300 };
-+
-+static const uint16_t filter_6tap_64p_183[198] = {
-+	16296, 1032, 2196, 1032, 16296, 0,
-+	16292, 1004, 2200, 1060, 16304, 16380,
-+	16288, 976, 2200, 1088, 16308, 16380,
-+	16284, 952, 2196, 1116, 16312, 16376,
-+	16284, 924, 2196, 1144, 16320, 16376,
-+	16280, 900, 2192, 1172, 16324, 16372,
-+	16276, 872, 2192, 1200, 16332, 16368,
-+	16276, 848, 2188, 1228, 16340, 16368,
-+	16272, 820, 2180, 1256, 16348, 16364,
-+	16272, 796, 2176, 1280, 16356, 16360,
-+	16268, 768, 2168, 1308, 16364, 16360,
-+	16268, 744, 2164, 1336, 16372, 16356,
-+	16268, 716, 2156, 1364, 16380, 16352,
-+	16264, 692, 2148, 1392, 4, 16352,
-+	16264, 668, 2136, 1420, 16, 16348,
-+	16264, 644, 2128, 1448, 28, 16344,
-+	16264, 620, 2116, 1472, 36, 16340,
-+	16264, 596, 2108, 1500, 48, 16340,
-+	16268, 572, 2096, 1524, 60, 16336,
-+	16268, 548, 2080, 1552, 72, 16332,
-+	16268, 524, 2068, 1576, 88, 16328,
-+	16268, 504, 2056, 1604, 100, 16324,
-+	16272, 480, 2040, 1628, 112, 16324,
-+	16272, 456, 2024, 1652, 128, 16320,
-+	16272, 436, 2008, 1680, 144, 16316,
-+	16276, 416, 1992, 1704, 156, 16312,
-+	16276, 392, 1976, 1724, 172, 16308,
-+	16280, 372, 1956, 1748, 188, 16308,
-+	16280, 352, 1940, 1772, 204, 16304,
-+	16284, 332, 1920, 1796, 224, 16300,
-+	16288, 312, 1900, 1816, 240, 16296,
-+	16288, 296, 1880, 1840, 256, 16296,
-+	16292, 276, 1860, 1860, 276, 16292 };
-+
-+static const uint16_t filter_7tap_64p_upscale[231] = {
-+	176, 15760, 2488, 2488, 15760, 176, 0,
-+	172, 15772, 2404, 2572, 15752, 180, 16380,
-+	168, 15784, 2324, 2656, 15740, 184, 16380,
-+	164, 15800, 2240, 2736, 15732, 188, 16376,
-+	160, 15812, 2152, 2816, 15728, 192, 16376,
-+	152, 15828, 2068, 2896, 15724, 192, 16376,
-+	148, 15848, 1984, 2972, 15720, 196, 16372,
-+	140, 15864, 1896, 3048, 15720, 196, 16372,
-+	136, 15884, 1812, 3124, 15720, 196, 16368,
-+	128, 15900, 1724, 3196, 15720, 196, 16368,
-+	120, 15920, 1640, 3268, 15724, 196, 16368,
-+	116, 15940, 1552, 3336, 15732, 196, 16364,
-+	108, 15964, 1468, 3400, 15740, 196, 16364,
-+	104, 15984, 1384, 3464, 15748, 192, 16364,
-+	96, 16004, 1300, 3524, 15760, 188, 16364,
-+	88, 16028, 1216, 3584, 15776, 184, 16364,
-+	84, 16048, 1132, 3640, 15792, 180, 16360,
-+	76, 16072, 1048, 3692, 15812, 176, 16360,
-+	68, 16092, 968, 3744, 15832, 168, 16360,
-+	64, 16116, 888, 3788, 15856, 160, 16360,
-+	56, 16140, 812, 3832, 15884, 152, 16360,
-+	52, 16160, 732, 3876, 15912, 144, 16360,
-+	44, 16184, 656, 3912, 15944, 136, 16364,
-+	40, 16204, 584, 3944, 15976, 124, 16364,
-+	32, 16228, 512, 3976, 16012, 116, 16364,
-+	28, 16248, 440, 4004, 16048, 104, 16364,
-+	24, 16268, 372, 4028, 16092, 88, 16368,
-+	20, 16288, 304, 4048, 16132, 76, 16368,
-+	12, 16308, 240, 4064, 16180, 60, 16372,
-+	8, 16328, 176, 4076, 16228, 48, 16372,
-+	4, 16348, 112, 4088, 16276, 32, 16376,
-+	0, 16364, 56, 4092, 16328, 16, 16380,
-+	0, 0, 0, 4096, 0, 0, 0 };
-+
-+static const uint16_t filter_7tap_64p_117[231] = {
-+	92, 15868, 2464, 2464, 15868, 92, 0,
-+	96, 15864, 2404, 2528, 15876, 88, 0,
-+	100, 15860, 2344, 2584, 15884, 84, 0,
-+	104, 15856, 2280, 2644, 15892, 76, 0,
-+	108, 15852, 2216, 2700, 15904, 72, 0,
-+	108, 15852, 2152, 2756, 15916, 64, 0,
-+	112, 15852, 2088, 2812, 15932, 60, 0,
-+	112, 15852, 2024, 2864, 15948, 52, 0,
-+	112, 15856, 1960, 2916, 15964, 44, 0,
-+	116, 15860, 1892, 2964, 15984, 36, 0,
-+	116, 15864, 1828, 3016, 16004, 24, 4,
-+	116, 15868, 1760, 3060, 16024, 16, 4,
-+	116, 15876, 1696, 3108, 16048, 8, 8,
-+	116, 15884, 1628, 3152, 16072, 16380, 8,
-+	112, 15892, 1564, 3192, 16100, 16372, 8,
-+	112, 15900, 1496, 3232, 16124, 16360, 12,
-+	112, 15908, 1428, 3268, 16156, 16348, 12,
-+	108, 15920, 1364, 3304, 16188, 16336, 16,
-+	108, 15928, 1300, 3340, 16220, 16324, 20,
-+	104, 15940, 1232, 3372, 16252, 16312, 20,
-+	104, 15952, 1168, 3400, 16288, 16300, 24,
-+	100, 15964, 1104, 3428, 16328, 16284, 28,
-+	96, 15980, 1040, 3452, 16364, 16272, 28,
-+	96, 15992, 976, 3476, 20, 16256, 32,
-+	92, 16004, 916, 3496, 64, 16244, 36,
-+	88, 16020, 856, 3516, 108, 16228, 40,
-+	84, 16032, 792, 3532, 152, 16216, 44,
-+	80, 16048, 732, 3544, 200, 16200, 48,
-+	80, 16064, 676, 3556, 248, 16184, 48,
-+	76, 16080, 616, 3564, 296, 16168, 52,
-+	72, 16092, 560, 3568, 344, 16156, 56,
-+	68, 16108, 504, 3572, 396, 16140, 60,
-+	64, 16124, 452, 3576, 452, 16124, 64 };
-+
-+static const uint16_t filter_7tap_64p_150[231] = {
-+	16224, 16380, 2208, 2208, 16380, 16224, 0,
-+	16232, 16360, 2172, 2236, 16, 16216, 0,
-+	16236, 16340, 2140, 2268, 40, 16212, 0,
-+	16244, 16324, 2104, 2296, 60, 16204, 4,
-+	16252, 16304, 2072, 2324, 84, 16196, 4,
-+	16256, 16288, 2036, 2352, 108, 16192, 4,
-+	16264, 16268, 2000, 2380, 132, 16184, 8,
-+	16272, 16252, 1960, 2408, 160, 16176, 8,
-+	16276, 16240, 1924, 2432, 184, 16172, 8,
-+	16284, 16224, 1888, 2456, 212, 16164, 8,
-+	16288, 16212, 1848, 2480, 240, 16160, 12,
-+	16296, 16196, 1812, 2500, 268, 16152, 12,
-+	16300, 16184, 1772, 2524, 296, 16144, 12,
-+	16308, 16172, 1736, 2544, 324, 16140, 12,
-+	16312, 16164, 1696, 2564, 356, 16136, 12,
-+	16320, 16152, 1656, 2584, 388, 16128, 12,
-+	16324, 16144, 1616, 2600, 416, 16124, 12,
-+	16328, 16136, 1576, 2616, 448, 16116, 12,
-+	16332, 16128, 1536, 2632, 480, 16112, 12,
-+	16340, 16120, 1496, 2648, 516, 16108, 12,
-+	16344, 16112, 1456, 2660, 548, 16104, 12,
-+	16348, 16104, 1416, 2672, 580, 16100, 12,
-+	16352, 16100, 1376, 2684, 616, 16096, 12,
-+	16356, 16096, 1336, 2696, 652, 16092, 12,
-+	16360, 16092, 1296, 2704, 688, 16088, 12,
-+	16364, 16088, 1256, 2712, 720, 16084, 12,
-+	16368, 16084, 1220, 2720, 760, 16084, 8,
-+	16368, 16080, 1180, 2724, 796, 16080, 8,
-+	16372, 16080, 1140, 2732, 832, 16080, 8,
-+	16376, 16076, 1100, 2732, 868, 16076, 4,
-+	16380, 16076, 1060, 2736, 908, 16076, 4,
-+	16380, 16076, 1020, 2740, 944, 16076, 0,
-+	0, 16076, 984, 2740, 984, 16076, 0 };
-+
-+static const uint16_t filter_7tap_64p_183[231] = {
-+	16216, 324, 1884, 1884, 324, 16216, 0,
-+	16220, 304, 1864, 1904, 344, 16216, 0,
-+	16224, 284, 1844, 1924, 364, 16216, 0,
-+	16224, 264, 1824, 1944, 384, 16212, 16380,
-+	16228, 248, 1804, 1960, 408, 16212, 16380,
-+	16228, 228, 1784, 1976, 428, 16208, 16380,
-+	16232, 212, 1760, 1996, 452, 16208, 16380,
-+	16236, 192, 1740, 2012, 472, 16208, 16376,
-+	16240, 176, 1716, 2028, 496, 16208, 16376,
-+	16240, 160, 1696, 2040, 516, 16208, 16376,
-+	16244, 144, 1672, 2056, 540, 16208, 16376,
-+	16248, 128, 1648, 2068, 564, 16208, 16372,
-+	16252, 112, 1624, 2084, 588, 16208, 16372,
-+	16256, 96, 1600, 2096, 612, 16208, 16368,
-+	16256, 84, 1576, 2108, 636, 16208, 16368,
-+	16260, 68, 1552, 2120, 660, 16208, 16368,
-+	16264, 56, 1524, 2132, 684, 16212, 16364,
-+	16268, 40, 1500, 2140, 712, 16212, 16364,
-+	16272, 28, 1476, 2152, 736, 16216, 16360,
-+	16276, 16, 1448, 2160, 760, 16216, 16356,
-+	16280, 4, 1424, 2168, 788, 16220, 16356,
-+	16284, 16376, 1396, 2176, 812, 16224, 16352,
-+	16288, 16368, 1372, 2184, 840, 16224, 16352,
-+	16292, 16356, 1344, 2188, 864, 16228, 16348,
-+	16292, 16344, 1320, 2196, 892, 16232, 16344,
-+	16296, 16336, 1292, 2200, 916, 16236, 16344,
-+	16300, 16324, 1264, 2204, 944, 16240, 16340,
-+	16304, 16316, 1240, 2208, 972, 16248, 16336,
-+	16308, 16308, 1212, 2212, 996, 16252, 16332,
-+	16312, 16300, 1184, 2216, 1024, 16256, 16332,
-+	16316, 16292, 1160, 2216, 1052, 16264, 16328,
-+	16316, 16284, 1132, 2216, 1076, 16268, 16324,
-+	16320, 16276, 1104, 2216, 1104, 16276, 16320 };
-+
-+static const uint16_t filter_8tap_64p_upscale[264] = {
-+	0, 0, 0, 4096, 0, 0, 0, 0,
-+	16376, 20, 16328, 4092, 56, 16364, 4, 0,
-+	16372, 36, 16272, 4088, 116, 16340, 12, 0,
-+	16364, 56, 16220, 4080, 180, 16320, 20, 0,
-+	16360, 76, 16172, 4064, 244, 16296, 24, 16380,
-+	16356, 92, 16124, 4048, 312, 16276, 32, 16380,
-+	16352, 108, 16080, 4032, 380, 16252, 40, 16380,
-+	16344, 124, 16036, 4008, 452, 16228, 48, 16380,
-+	16340, 136, 15996, 3980, 524, 16204, 56, 16380,
-+	16340, 152, 15956, 3952, 600, 16180, 64, 16376,
-+	16336, 164, 15920, 3920, 672, 16156, 76, 16376,
-+	16332, 176, 15888, 3884, 752, 16132, 84, 16376,
-+	16328, 188, 15860, 3844, 828, 16104, 92, 16372,
-+	16328, 200, 15828, 3800, 908, 16080, 100, 16372,
-+	16324, 208, 15804, 3756, 992, 16056, 108, 16372,
-+	16324, 216, 15780, 3708, 1072, 16032, 120, 16368,
-+	16320, 224, 15760, 3656, 1156, 16008, 128, 16368,
-+	16320, 232, 15740, 3604, 1240, 15984, 136, 16364,
-+	16320, 240, 15724, 3548, 1324, 15960, 144, 16364,
-+	16320, 244, 15708, 3488, 1412, 15936, 152, 16360,
-+	16320, 248, 15696, 3428, 1496, 15912, 160, 16360,
-+	16320, 252, 15688, 3364, 1584, 15892, 172, 16356,
-+	16320, 256, 15680, 3296, 1672, 15868, 180, 16352,
-+	16320, 256, 15672, 3228, 1756, 15848, 188, 16352,
-+	16320, 256, 15668, 3156, 1844, 15828, 192, 16348,
-+	16320, 260, 15668, 3084, 1932, 15808, 200, 16348,
-+	16320, 256, 15668, 3012, 2020, 15792, 208, 16344,
-+	16324, 256, 15668, 2936, 2108, 15772, 216, 16344,
-+	16324, 256, 15672, 2856, 2192, 15756, 220, 16340,
-+	16324, 252, 15676, 2776, 2280, 15740, 228, 16336,
-+	16328, 252, 15684, 2696, 2364, 15728, 232, 16336,
-+	16328, 248, 15692, 2616, 2448, 15716, 240, 16332,
-+	16332, 244, 15704, 2532, 2532, 15704, 244, 16332 };
-+
-+static const uint16_t filter_8tap_64p_117[264] = {
-+	116, 16100, 428, 3564, 428, 16100, 116, 0,
-+	112, 16116, 376, 3564, 484, 16084, 120, 16380,
-+	104, 16136, 324, 3560, 540, 16064, 124, 16380,
-+	100, 16152, 272, 3556, 600, 16048, 128, 16380,
-+	96, 16168, 220, 3548, 656, 16032, 136, 16376,
-+	88, 16188, 172, 3540, 716, 16016, 140, 16376,
-+	84, 16204, 124, 3528, 780, 16000, 144, 16376,
-+	80, 16220, 76, 3512, 840, 15984, 148, 16372,
-+	76, 16236, 32, 3496, 904, 15968, 152, 16372,
-+	68, 16252, 16376, 3480, 968, 15952, 156, 16372,
-+	64, 16268, 16332, 3456, 1032, 15936, 160, 16372,
-+	60, 16284, 16292, 3432, 1096, 15920, 164, 16368,
-+	56, 16300, 16252, 3408, 1164, 15908, 164, 16368,
-+	48, 16316, 16216, 3380, 1228, 15892, 168, 16368,
-+	44, 16332, 16180, 3348, 1296, 15880, 168, 16368,
-+	40, 16348, 16148, 3316, 1364, 15868, 172, 16364,
-+	36, 16360, 16116, 3284, 1428, 15856, 172, 16364,
-+	32, 16376, 16084, 3248, 1496, 15848, 176, 16364,
-+	28, 4, 16052, 3208, 1564, 15836, 176, 16364,
-+	24, 16, 16028, 3168, 1632, 15828, 176, 16364,
-+	20, 28, 16000, 3124, 1700, 15820, 176, 16364,
-+	16, 40, 15976, 3080, 1768, 15812, 176, 16364,
-+	12, 52, 15952, 3036, 1836, 15808, 176, 16364,
-+	8, 64, 15932, 2988, 1904, 15800, 176, 16364,
-+	4, 76, 15912, 2940, 1972, 15800, 172, 16364,
-+	4, 84, 15892, 2888, 2040, 15796, 172, 16364,
-+	0, 96, 15876, 2836, 2104, 15792, 168, 16364,
-+	16380, 104, 15864, 2780, 2172, 15792, 164, 16364,
-+	16380, 112, 15848, 2724, 2236, 15792, 160, 16364,
-+	16376, 120, 15836, 2668, 2300, 15796, 156, 16368,
-+	16376, 128, 15828, 2608, 2364, 15800, 152, 16368,
-+	16372, 136, 15816, 2548, 2428, 15804, 148, 16368,
-+	16372, 140, 15812, 2488, 2488, 15812, 140, 16372 };
-+
-+static const uint16_t filter_8tap_64p_150[264] = {
-+	16380, 16020, 1032, 2756, 1032, 16020, 16380, 0,
-+	0, 16020, 992, 2756, 1068, 16024, 16376, 0,
-+	4, 16020, 952, 2752, 1108, 16024, 16372, 0,
-+	8, 16020, 916, 2748, 1148, 16028, 16368, 0,
-+	12, 16020, 876, 2744, 1184, 16032, 16364, 4,
-+	16, 16020, 840, 2740, 1224, 16036, 16356, 4,
-+	20, 16024, 800, 2732, 1264, 16040, 16352, 4,
-+	20, 16024, 764, 2724, 1304, 16044, 16348, 8,
-+	24, 16028, 728, 2716, 1344, 16052, 16340, 8,
-+	28, 16028, 692, 2704, 1380, 16056, 16336, 12,
-+	28, 16032, 656, 2696, 1420, 16064, 16328, 12,
-+	32, 16036, 620, 2684, 1460, 16072, 16324, 12,
-+	36, 16040, 584, 2668, 1500, 16080, 16316, 16,
-+	36, 16044, 548, 2656, 1536, 16088, 16308, 16,
-+	36, 16048, 516, 2640, 1576, 16096, 16304, 20,
-+	40, 16052, 480, 2624, 1612, 16108, 16296, 20,
-+	40, 16060, 448, 2608, 1652, 16120, 16288, 20,
-+	44, 16064, 416, 2588, 1692, 16132, 16280, 24,
-+	44, 16068, 384, 2568, 1728, 16144, 16276, 24,
-+	44, 16076, 352, 2548, 1764, 16156, 16268, 28,
-+	44, 16080, 320, 2528, 1804, 16168, 16260, 28,
-+	44, 16088, 292, 2508, 1840, 16184, 16252, 28,
-+	44, 16096, 264, 2484, 1876, 16200, 16244, 32,
-+	48, 16100, 232, 2460, 1912, 16216, 16236, 32,
-+	48, 16108, 204, 2436, 1948, 16232, 16228, 32,
-+	48, 16116, 176, 2412, 1980, 16248, 16220, 36,
-+	48, 16124, 152, 2384, 2016, 16264, 16216, 36,
-+	44, 16128, 124, 2356, 2052, 16284, 16208, 36,
-+	44, 16136, 100, 2328, 2084, 16304, 16200, 40,
-+	44, 16144, 72, 2300, 2116, 16324, 16192, 40,
-+	44, 16152, 48, 2272, 2148, 16344, 16184, 40,
-+	44, 16160, 24, 2244, 2180, 16364, 16176, 40,
-+	44, 16168, 4, 2212, 2212, 4, 16168, 44 };
-+
-+static const uint16_t filter_8tap_64p_183[264] = {
-+	16264, 16264, 1164, 2244, 1164, 16264, 16264, 0,
-+	16268, 16256, 1136, 2240, 1188, 16272, 16260, 0,
-+	16272, 16248, 1108, 2240, 1216, 16280, 16256, 0,
-+	16276, 16240, 1080, 2236, 1240, 16292, 16252, 0,
-+	16280, 16232, 1056, 2236, 1268, 16300, 16248, 0,
-+	16284, 16224, 1028, 2232, 1292, 16312, 16244, 0,
-+	16288, 16216, 1000, 2228, 1320, 16324, 16240, 0,
-+	16292, 16212, 976, 2224, 1344, 16336, 16236, 0,
-+	16296, 16204, 948, 2220, 1372, 16348, 16232, 0,
-+	16300, 16200, 920, 2212, 1396, 16360, 16228, 4,
-+	16304, 16196, 896, 2204, 1424, 16372, 16224, 4,
-+	16308, 16188, 868, 2200, 1448, 0, 16220, 4,
-+	16312, 16184, 844, 2192, 1472, 12, 16216, 4,
-+	16316, 16180, 816, 2184, 1500, 28, 16212, 4,
-+	16320, 16176, 792, 2172, 1524, 40, 16208, 4,
-+	16324, 16172, 764, 2164, 1548, 56, 16204, 0,
-+	16328, 16172, 740, 2156, 1572, 72, 16200, 0,
-+	16328, 16168, 712, 2144, 1596, 88, 16196, 0,
-+	16332, 16164, 688, 2132, 1620, 100, 16192, 0,
-+	16336, 16164, 664, 2120, 1644, 120, 16192, 0,
-+	16340, 16160, 640, 2108, 1668, 136, 16188, 0,
-+	16344, 16160, 616, 2096, 1688, 152, 16184, 0,
-+	16344, 16160, 592, 2080, 1712, 168, 16180, 0,
-+	16348, 16156, 568, 2068, 1736, 188, 16176, 16380,
-+	16352, 16156, 544, 2052, 1756, 204, 16176, 16380,
-+	16352, 16156, 520, 2036, 1780, 224, 16172, 16380,
-+	16356, 16156, 496, 2024, 1800, 244, 16172, 16380,
-+	16360, 16156, 472, 2008, 1820, 260, 16168, 16376,
-+	16360, 16156, 452, 1988, 1840, 280, 16164, 16376,
-+	16364, 16156, 428, 1972, 1860, 300, 16164, 16376,
-+	16364, 16156, 408, 1956, 1880, 320, 16164, 16372,
-+	16368, 16160, 384, 1936, 1900, 344, 16160, 16372,
-+	16368, 16160, 364, 1920, 1920, 364, 16160, 16368 };
-+
-+const uint16_t *get_filter_3tap_16p(struct fixed31_32 ratio)
-+{
-+	if (ratio.value < dal_fixed31_32_one.value)
-+		return filter_3tap_16p_upscale;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
-+		return filter_3tap_16p_117;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
-+		return filter_3tap_16p_150;
-+	else
-+		return filter_3tap_16p_183;
-+}
-+
-+const uint16_t *get_filter_3tap_64p(struct fixed31_32 ratio)
-+{
-+	if (ratio.value < dal_fixed31_32_one.value)
-+		return filter_3tap_64p_upscale;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
-+		return filter_3tap_64p_117;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
-+		return filter_3tap_64p_150;
-+	else
-+		return filter_3tap_64p_183;
-+}
-+
-+const uint16_t *get_filter_4tap_16p(struct fixed31_32 ratio)
-+{
-+	if (ratio.value < dal_fixed31_32_one.value)
-+		return filter_4tap_16p_upscale;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
-+		return filter_4tap_16p_117;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
-+		return filter_4tap_16p_150;
-+	else
-+		return filter_4tap_16p_183;
-+}
-+
-+const uint16_t *get_filter_4tap_64p(struct fixed31_32 ratio)
-+{
-+	if (ratio.value < dal_fixed31_32_one.value)
-+		return filter_4tap_64p_upscale;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
-+		return filter_4tap_64p_117;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
-+		return filter_4tap_64p_150;
-+	else
-+		return filter_4tap_64p_183;
-+}
-+
-+const uint16_t *get_filter_5tap_64p(struct fixed31_32 ratio)
-+{
-+	if (ratio.value < dal_fixed31_32_one.value)
-+		return filter_5tap_64p_upscale;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
-+		return filter_5tap_64p_117;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
-+		return filter_5tap_64p_150;
-+	else
-+		return filter_5tap_64p_183;
-+}
-+
-+const uint16_t *get_filter_6tap_64p(struct fixed31_32 ratio)
-+{
-+	if (ratio.value < dal_fixed31_32_one.value)
-+		return filter_6tap_64p_upscale;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
-+		return filter_6tap_64p_117;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
-+		return filter_6tap_64p_150;
-+	else
-+		return filter_6tap_64p_183;
-+}
-+
-+const uint16_t *get_filter_7tap_64p(struct fixed31_32 ratio)
-+{
-+	if (ratio.value < dal_fixed31_32_one.value)
-+		return filter_7tap_64p_upscale;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
-+		return filter_7tap_64p_117;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
-+		return filter_7tap_64p_150;
-+	else
-+		return filter_7tap_64p_183;
-+}
-+
-+const uint16_t *get_filter_8tap_64p(struct fixed31_32 ratio)
-+{
-+	if (ratio.value < dal_fixed31_32_one.value)
-+		return filter_8tap_64p_upscale;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
-+		return filter_8tap_64p_117;
-+	else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
-+		return filter_8tap_64p_150;
-+	else
-+		return filter_8tap_64p_183;
-+}
-+
-+const uint16_t *get_filter_2tap_16p(void)
-+{
-+	return filter_2tap_16p;
-+}
-+
-+const uint16_t *get_filter_2tap_64p(void)
-+{
-+	return filter_2tap_64p;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c.0130~	2017-12-14 06:39:58.418903570 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c	2017-12-14 06:39:58.418903570 +0100
-@@ -0,0 +1,1635 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dc_bios_types.h"
-+#include "dce_stream_encoder.h"
-+#include "reg_helper.h"
-+
-+enum DP_PIXEL_ENCODING {
-+DP_PIXEL_ENCODING_RGB444                 = 0x00000000,
-+DP_PIXEL_ENCODING_YCBCR422               = 0x00000001,
-+DP_PIXEL_ENCODING_YCBCR444               = 0x00000002,
-+DP_PIXEL_ENCODING_RGB_WIDE_GAMUT         = 0x00000003,
-+DP_PIXEL_ENCODING_Y_ONLY                 = 0x00000004,
-+DP_PIXEL_ENCODING_YCBCR420               = 0x00000005,
-+DP_PIXEL_ENCODING_RESERVED               = 0x00000006,
-+};
-+
-+
-+enum DP_COMPONENT_DEPTH {
-+DP_COMPONENT_DEPTH_6BPC                  = 0x00000000,
-+DP_COMPONENT_DEPTH_8BPC                  = 0x00000001,
-+DP_COMPONENT_DEPTH_10BPC                 = 0x00000002,
-+DP_COMPONENT_DEPTH_12BPC                 = 0x00000003,
-+DP_COMPONENT_DEPTH_16BPC                 = 0x00000004,
-+DP_COMPONENT_DEPTH_RESERVED              = 0x00000005,
-+};
-+
-+
-+#define REG(reg)\
-+	(enc110->regs->reg)
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	enc110->se_shift->field_name, enc110->se_mask->field_name
-+
-+#define VBI_LINE_0 0
-+#define DP_BLANK_MAX_RETRY 20
-+#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
-+
-+#ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
-+	#define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK       0x00000010L
-+	#define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK         0x00000300L
-+	#define	TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT     0x00000004
-+	#define	TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT       0x00000008
-+#endif
-+
-+enum {
-+	DP_MST_UPDATE_MAX_RETRY = 50
-+};
-+
-+#define DCE110_SE(audio)\
-+	container_of(audio, struct dce110_stream_encoder, base)
-+
-+#define CTX \
-+	enc110->base.ctx
-+
-+static void dce110_update_generic_info_packet(
-+	struct dce110_stream_encoder *enc110,
-+	uint32_t packet_index,
-+	const struct encoder_info_packet *info_packet)
-+{
-+	uint32_t regval;
-+	/* TODOFPGA Figure out a proper number for max_retries polling for lock
-+	 * use 50 for now.
-+	 */
-+	uint32_t max_retries = 50;
-+
-+	if (REG(AFMT_VBI_PACKET_CONTROL1)) {
-+		if (packet_index >= 8)
-+			ASSERT(0);
-+
-+		/* poll dig_update_lock is not locked -> asic internal signal
-+		 * assume otg master lock will unlock it
-+		 */
-+/*		REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
-+				0, 10, max_retries);*/
-+
-+		/* check if HW reading GSP memory */
-+		REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
-+				0, 10, max_retries);
-+
-+		/* HW does is not reading GSP memory not reading too long ->
-+		 * something wrong. clear GPS memory access and notify?
-+		 * hw SW is writing to GSP memory
-+		 */
-+		REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
-+	}
-+	/* choose which generic packet to use */
-+	{
-+		regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
-+		REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
-+				AFMT_GENERIC_INDEX, packet_index);
-+	}
-+
-+	/* write generic packet header
-+	 * (4th byte is for GENERIC0 only) */
-+	{
-+		REG_SET_4(AFMT_GENERIC_HDR, 0,
-+				AFMT_GENERIC_HB0, info_packet->hb0,
-+				AFMT_GENERIC_HB1, info_packet->hb1,
-+				AFMT_GENERIC_HB2, info_packet->hb2,
-+				AFMT_GENERIC_HB3, info_packet->hb3);
-+	}
-+
-+	/* write generic packet contents
-+	 * (we never use last 4 bytes)
-+	 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
-+	{
-+		const uint32_t *content =
-+			(const uint32_t *) &info_packet->sb[0];
-+
-+		REG_WRITE(AFMT_GENERIC_0, *content++);
-+		REG_WRITE(AFMT_GENERIC_1, *content++);
-+		REG_WRITE(AFMT_GENERIC_2, *content++);
-+		REG_WRITE(AFMT_GENERIC_3, *content++);
-+		REG_WRITE(AFMT_GENERIC_4, *content++);
-+		REG_WRITE(AFMT_GENERIC_5, *content++);
-+		REG_WRITE(AFMT_GENERIC_6, *content++);
-+		REG_WRITE(AFMT_GENERIC_7, *content);
-+	}
-+
-+	if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
-+		/* force double-buffered packet update */
-+		REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
-+			AFMT_GENERIC0_UPDATE, (packet_index == 0),
-+			AFMT_GENERIC2_UPDATE, (packet_index == 2));
-+	}
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	if (REG(AFMT_VBI_PACKET_CONTROL1)) {
-+		switch (packet_index) {
-+		case 0:
-+			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
-+					AFMT_GENERIC0_FRAME_UPDATE, 1);
-+			break;
-+		case 1:
-+			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
-+					AFMT_GENERIC1_FRAME_UPDATE, 1);
-+			break;
-+		case 2:
-+			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
-+					AFMT_GENERIC2_FRAME_UPDATE, 1);
-+			break;
-+		case 3:
-+			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
-+					AFMT_GENERIC3_FRAME_UPDATE, 1);
-+			break;
-+		case 4:
-+			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
-+					AFMT_GENERIC4_FRAME_UPDATE, 1);
-+			break;
-+		case 5:
-+			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
-+					AFMT_GENERIC5_FRAME_UPDATE, 1);
-+			break;
-+		case 6:
-+			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
-+					AFMT_GENERIC6_FRAME_UPDATE, 1);
-+			break;
-+		case 7:
-+			REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
-+					AFMT_GENERIC7_FRAME_UPDATE, 1);
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+#endif
-+}
-+
-+static void dce110_update_hdmi_info_packet(
-+	struct dce110_stream_encoder *enc110,
-+	uint32_t packet_index,
-+	const struct encoder_info_packet *info_packet)
-+{
-+	struct dc_context *ctx = enc110->base.ctx;
-+	uint32_t cont, send, line;
-+
-+	if (info_packet->valid) {
-+		dce110_update_generic_info_packet(
-+			enc110,
-+			packet_index,
-+			info_packet);
-+
-+		/* enable transmission of packet(s) -
-+		 * packet transmission begins on the next frame */
-+		cont = 1;
-+		/* send packet(s) every frame */
-+		send = 1;
-+		/* select line number to send packets on */
-+		line = 2;
-+	} else {
-+		cont = 0;
-+		send = 0;
-+		line = 0;
-+	}
-+
-+	/* choose which generic packet control to use */
-+	switch (packet_index) {
-+	case 0:
-+		REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
-+				HDMI_GENERIC0_CONT, cont,
-+				HDMI_GENERIC0_SEND, send,
-+				HDMI_GENERIC0_LINE, line);
-+		break;
-+	case 1:
-+		REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
-+				HDMI_GENERIC1_CONT, cont,
-+				HDMI_GENERIC1_SEND, send,
-+				HDMI_GENERIC1_LINE, line);
-+		break;
-+	case 2:
-+		REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
-+				HDMI_GENERIC0_CONT, cont,
-+				HDMI_GENERIC0_SEND, send,
-+				HDMI_GENERIC0_LINE, line);
-+		break;
-+	case 3:
-+		REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
-+				HDMI_GENERIC1_CONT, cont,
-+				HDMI_GENERIC1_SEND, send,
-+				HDMI_GENERIC1_LINE, line);
-+		break;
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	case 4:
-+		if (REG(HDMI_GENERIC_PACKET_CONTROL2))
-+			REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
-+					HDMI_GENERIC0_CONT, cont,
-+					HDMI_GENERIC0_SEND, send,
-+					HDMI_GENERIC0_LINE, line);
-+		break;
-+	case 5:
-+		if (REG(HDMI_GENERIC_PACKET_CONTROL2))
-+			REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
-+					HDMI_GENERIC1_CONT, cont,
-+					HDMI_GENERIC1_SEND, send,
-+					HDMI_GENERIC1_LINE, line);
-+		break;
-+	case 6:
-+		if (REG(HDMI_GENERIC_PACKET_CONTROL3))
-+			REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
-+					HDMI_GENERIC0_CONT, cont,
-+					HDMI_GENERIC0_SEND, send,
-+					HDMI_GENERIC0_LINE, line);
-+		break;
-+	case 7:
-+		if (REG(HDMI_GENERIC_PACKET_CONTROL3))
-+			REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
-+					HDMI_GENERIC1_CONT, cont,
-+					HDMI_GENERIC1_SEND, send,
-+					HDMI_GENERIC1_LINE, line);
-+		break;
-+#endif
-+	default:
-+		/* invalid HW packet index */
-+		dm_logger_write(
-+			ctx->logger, LOG_WARNING,
-+			"Invalid HW packet index: %s()\n",
-+			__func__);
-+		return;
-+	}
-+}
-+
-+/* setup stream encoder in dp mode */
-+static void dce110_stream_encoder_dp_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	enum dc_color_space output_color_space)
-+{
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	uint32_t h_active_start;
-+	uint32_t v_active_start;
-+	uint32_t misc0 = 0;
-+	uint32_t misc1 = 0;
-+	uint32_t h_blank;
-+	uint32_t h_back_porch;
-+	uint8_t synchronous_clock = 0; /* asynchronous mode */
-+	uint8_t colorimetry_bpc;
-+	uint8_t dynamic_range_rgb = 0; /*full range*/
-+	uint8_t dynamic_range_ycbcr = 1; /*bt709*/
-+#endif
-+
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	if (REG(DP_DB_CNTL))
-+		REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
-+#endif
-+
-+	/* set pixel encoding */
-+	switch (crtc_timing->pixel_encoding) {
-+	case PIXEL_ENCODING_YCBCR422:
-+		REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-+				DP_PIXEL_ENCODING_YCBCR422);
-+		break;
-+	case PIXEL_ENCODING_YCBCR444:
-+		REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-+				DP_PIXEL_ENCODING_YCBCR444);
-+
-+		if (crtc_timing->flags.Y_ONLY)
-+			if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
-+				/* HW testing only, no use case yet.
-+				 * Color depth of Y-only could be
-+				 * 8, 10, 12, 16 bits */
-+				REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-+						DP_PIXEL_ENCODING_Y_ONLY);
-+		/* Note: DP_MSA_MISC1 bit 7 is the indicator
-+		 * of Y-only mode.
-+		 * This bit is set in HW if register
-+		 * DP_PIXEL_ENCODING is programmed to 0x4 */
-+		break;
-+	case PIXEL_ENCODING_YCBCR420:
-+		REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-+				DP_PIXEL_ENCODING_YCBCR420);
-+		if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
-+			REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+		if (enc110->se_mask->DP_VID_N_MUL)
-+			REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
-+#endif
-+		break;
-+	default:
-+		REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-+				DP_PIXEL_ENCODING_RGB444);
-+		break;
-+	}
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	if (REG(DP_MSA_MISC))
-+		misc1 = REG_READ(DP_MSA_MISC);
-+#endif
-+
-+	/* set color depth */
-+
-+	switch (crtc_timing->display_color_depth) {
-+	case COLOR_DEPTH_666:
-+		REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-+				0);
-+		break;
-+	case COLOR_DEPTH_888:
-+		REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-+				DP_COMPONENT_DEPTH_8BPC);
-+		break;
-+	case COLOR_DEPTH_101010:
-+		REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-+				DP_COMPONENT_DEPTH_10BPC);
-+
-+		break;
-+	case COLOR_DEPTH_121212:
-+		REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-+				DP_COMPONENT_DEPTH_12BPC);
-+		break;
-+	default:
-+		REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
-+				DP_COMPONENT_DEPTH_6BPC);
-+		break;
-+	}
-+
-+	/* set dynamic range and YCbCr range */
-+
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	switch (crtc_timing->display_color_depth) {
-+	case COLOR_DEPTH_666:
-+		colorimetry_bpc = 0;
-+		break;
-+	case COLOR_DEPTH_888:
-+		colorimetry_bpc = 1;
-+		break;
-+	case COLOR_DEPTH_101010:
-+		colorimetry_bpc = 2;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		colorimetry_bpc = 3;
-+		break;
-+	default:
-+		colorimetry_bpc = 0;
-+		break;
-+	}
-+
-+	misc0 = misc0 | synchronous_clock;
-+	misc0 = colorimetry_bpc << 5;
-+
-+	if (REG(DP_MSA_TIMING_PARAM1)) {
-+		switch (output_color_space) {
-+		case COLOR_SPACE_SRGB:
-+			misc0 = misc0 | 0x0;
-+			misc1 = misc1 & ~0x80; /* bit7 = 0*/
-+			dynamic_range_rgb = 0; /*full range*/
-+			break;
-+		case COLOR_SPACE_SRGB_LIMITED:
-+			misc0 = misc0 | 0x8; /* bit3=1 */
-+			misc1 = misc1 & ~0x80; /* bit7 = 0*/
-+			dynamic_range_rgb = 1; /*limited range*/
-+			break;
-+		case COLOR_SPACE_YCBCR601:
-+		case COLOR_SPACE_YCBCR601_LIMITED:
-+			misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
-+			misc1 = misc1 & ~0x80; /* bit7 = 0*/
-+			dynamic_range_ycbcr = 0; /*bt601*/
-+			if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
-+				misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
-+			else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
-+				misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
-+			break;
-+		case COLOR_SPACE_YCBCR709:
-+		case COLOR_SPACE_YCBCR709_LIMITED:
-+			misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
-+			misc1 = misc1 & ~0x80; /* bit7 = 0*/
-+			dynamic_range_ycbcr = 1; /*bt709*/
-+			if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
-+				misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
-+			else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
-+				misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
-+			break;
-+		case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
-+			dynamic_range_rgb = 1; /*limited range*/
-+			break;
-+		case COLOR_SPACE_2020_RGB_FULLRANGE:
-+		case COLOR_SPACE_2020_YCBCR:
-+		case COLOR_SPACE_XR_RGB:
-+		case COLOR_SPACE_MSREF_SCRGB:
-+		case COLOR_SPACE_ADOBERGB:
-+		case COLOR_SPACE_DCIP3:
-+		case COLOR_SPACE_XV_YCC_709:
-+		case COLOR_SPACE_XV_YCC_601:
-+		case COLOR_SPACE_DISPLAYNATIVE:
-+		case COLOR_SPACE_DOLBYVISION:
-+		case COLOR_SPACE_APPCTRL:
-+		case COLOR_SPACE_CUSTOMPOINTS:
-+		case COLOR_SPACE_UNKNOWN:
-+			/* do nothing */
-+			break;
-+		}
-+		if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
-+			REG_UPDATE_2(
-+				DP_PIXEL_FORMAT,
-+				DP_DYN_RANGE, dynamic_range_rgb,
-+				DP_YCBCR_RANGE, dynamic_range_ycbcr);
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+		if (REG(DP_MSA_COLORIMETRY))
-+			REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
-+
-+		if (REG(DP_MSA_MISC))
-+			REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
-+
-+	/* dcn new register
-+	 * dc_crtc_timing is vesa dmt struct. data from edid
-+	 */
-+		if (REG(DP_MSA_TIMING_PARAM1))
-+			REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
-+					DP_MSA_HTOTAL, crtc_timing->h_total,
-+					DP_MSA_VTOTAL, crtc_timing->v_total);
-+#endif
-+
-+		/* calcuate from vesa timing parameters
-+		 * h_active_start related to leading edge of sync
-+		 */
-+
-+		h_blank = crtc_timing->h_total - crtc_timing->h_border_left -
-+				crtc_timing->h_addressable - crtc_timing->h_border_right;
-+
-+		h_back_porch = h_blank - crtc_timing->h_front_porch -
-+				crtc_timing->h_sync_width;
-+
-+		/* start at begining of left border */
-+		h_active_start = crtc_timing->h_sync_width + h_back_porch;
-+
-+
-+		v_active_start = crtc_timing->v_total - crtc_timing->v_border_top -
-+				crtc_timing->v_addressable - crtc_timing->v_border_bottom -
-+				crtc_timing->v_front_porch;
-+
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+		/* start at begining of left border */
-+		if (REG(DP_MSA_TIMING_PARAM2))
-+			REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
-+				DP_MSA_HSTART, h_active_start,
-+				DP_MSA_VSTART, v_active_start);
-+
-+		if (REG(DP_MSA_TIMING_PARAM3))
-+			REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
-+					DP_MSA_HSYNCWIDTH,
-+					crtc_timing->h_sync_width,
-+					DP_MSA_HSYNCPOLARITY,
-+					!crtc_timing->flags.HSYNC_POSITIVE_POLARITY,
-+					DP_MSA_VSYNCWIDTH,
-+					crtc_timing->v_sync_width,
-+					DP_MSA_VSYNCPOLARITY,
-+					!crtc_timing->flags.VSYNC_POSITIVE_POLARITY);
-+
-+		/* HWDITH include border or overscan */
-+		if (REG(DP_MSA_TIMING_PARAM4))
-+			REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
-+				DP_MSA_HWIDTH, crtc_timing->h_border_left +
-+				crtc_timing->h_addressable + crtc_timing->h_border_right,
-+				DP_MSA_VHEIGHT, crtc_timing->v_border_top +
-+				crtc_timing->v_addressable + crtc_timing->v_border_bottom);
-+#endif
-+	}
-+#endif
-+}
-+
-+static void dce110_stream_encoder_set_stream_attribute_helper(
-+		struct dce110_stream_encoder *enc110,
-+		struct dc_crtc_timing *crtc_timing)
-+{
-+	if (enc110->regs->TMDS_CNTL) {
-+		switch (crtc_timing->pixel_encoding) {
-+		case PIXEL_ENCODING_YCBCR422:
-+			REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
-+			break;
-+		default:
-+			REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
-+			break;
-+		}
-+		REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);
-+	} else if (enc110->regs->DIG_FE_CNTL) {
-+		switch (crtc_timing->pixel_encoding) {
-+		case PIXEL_ENCODING_YCBCR422:
-+			REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
-+			break;
-+		default:
-+			REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
-+			break;
-+		}
-+		REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
-+	}
-+
-+}
-+
-+/* setup stream encoder in hdmi mode */
-+static void dce110_stream_encoder_hdmi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	int actual_pix_clk_khz,
-+	bool enable_audio)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct bp_encoder_control cntl = {0};
-+
-+	cntl.action = ENCODER_CONTROL_SETUP;
-+	cntl.engine_id = enc110->base.id;
-+	cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
-+	cntl.enable_dp_audio = enable_audio;
-+	cntl.pixel_clock = actual_pix_clk_khz;
-+	cntl.lanes_number = LANE_COUNT_FOUR;
-+
-+	if (enc110->base.bp->funcs->encoder_control(
-+			enc110->base.bp, &cntl) != BP_RESULT_OK)
-+		return;
-+
-+	dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
-+
-+	/* setup HDMI engine */
-+	if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
-+		REG_UPDATE_3(HDMI_CONTROL,
-+			HDMI_PACKET_GEN_VERSION, 1,
-+			HDMI_KEEPOUT_MODE, 1,
-+			HDMI_DEEP_COLOR_ENABLE, 0);
-+	} else if (enc110->regs->DIG_FE_CNTL) {
-+		REG_UPDATE_5(HDMI_CONTROL,
-+			HDMI_PACKET_GEN_VERSION, 1,
-+			HDMI_KEEPOUT_MODE, 1,
-+			HDMI_DEEP_COLOR_ENABLE, 0,
-+			HDMI_DATA_SCRAMBLE_EN, 0,
-+			HDMI_CLOCK_CHANNEL_RATE, 0);
-+	}
-+
-+	switch (crtc_timing->display_color_depth) {
-+	case COLOR_DEPTH_888:
-+		REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
-+		break;
-+	case COLOR_DEPTH_101010:
-+		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
-+			REG_UPDATE_2(HDMI_CONTROL,
-+					HDMI_DEEP_COLOR_DEPTH, 1,
-+					HDMI_DEEP_COLOR_ENABLE, 0);
-+		} else {
-+			REG_UPDATE_2(HDMI_CONTROL,
-+					HDMI_DEEP_COLOR_DEPTH, 1,
-+					HDMI_DEEP_COLOR_ENABLE, 1);
-+			}
-+		break;
-+	case COLOR_DEPTH_121212:
-+		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
-+			REG_UPDATE_2(HDMI_CONTROL,
-+					HDMI_DEEP_COLOR_DEPTH, 2,
-+					HDMI_DEEP_COLOR_ENABLE, 0);
-+		} else {
-+			REG_UPDATE_2(HDMI_CONTROL,
-+					HDMI_DEEP_COLOR_DEPTH, 2,
-+					HDMI_DEEP_COLOR_ENABLE, 1);
-+			}
-+		break;
-+	case COLOR_DEPTH_161616:
-+		REG_UPDATE_2(HDMI_CONTROL,
-+				HDMI_DEEP_COLOR_DEPTH, 3,
-+				HDMI_DEEP_COLOR_ENABLE, 1);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
-+		if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
-+			/* enable HDMI data scrambler
-+			 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
-+			 * Clock channel frequency is 1/4 of character rate.
-+			 */
-+			REG_UPDATE_2(HDMI_CONTROL,
-+				HDMI_DATA_SCRAMBLE_EN, 1,
-+				HDMI_CLOCK_CHANNEL_RATE, 1);
-+		} else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
-+
-+			/* TODO: New feature for DCE11, still need to implement */
-+
-+			/* enable HDMI data scrambler
-+			 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
-+			 * Clock channel frequency is the same
-+			 * as character rate
-+			 */
-+			REG_UPDATE_2(HDMI_CONTROL,
-+				HDMI_DATA_SCRAMBLE_EN, 1,
-+				HDMI_CLOCK_CHANNEL_RATE, 0);
-+		}
-+	}
-+
-+	REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
-+		HDMI_GC_CONT, 1,
-+		HDMI_GC_SEND, 1,
-+		HDMI_NULL_SEND, 1);
-+
-+	/* following belongs to audio */
-+	REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
-+
-+	REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
-+
-+	REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
-+				VBI_LINE_0 + 2);
-+
-+	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
-+
-+}
-+
-+/* setup stream encoder in dvi mode */
-+static void dce110_stream_encoder_dvi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	bool is_dual_link)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	struct bp_encoder_control cntl = {0};
-+
-+	cntl.action = ENCODER_CONTROL_SETUP;
-+	cntl.engine_id = enc110->base.id;
-+	cntl.signal = is_dual_link ?
-+			SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
-+	cntl.enable_dp_audio = false;
-+	cntl.pixel_clock = crtc_timing->pix_clk_khz;
-+	cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
-+
-+	if (enc110->base.bp->funcs->encoder_control(
-+			enc110->base.bp, &cntl) != BP_RESULT_OK)
-+		return;
-+
-+	ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
-+	ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
-+	dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
-+}
-+
-+static void dce110_stream_encoder_set_mst_bandwidth(
-+	struct stream_encoder *enc,
-+	struct fixed31_32 avg_time_slots_per_mtp)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	uint32_t x = dal_fixed31_32_floor(
-+		avg_time_slots_per_mtp);
-+	uint32_t y = dal_fixed31_32_ceil(
-+		dal_fixed31_32_shl(
-+			dal_fixed31_32_sub_int(
-+				avg_time_slots_per_mtp,
-+				x),
-+			26));
-+
-+	{
-+		REG_SET_2(DP_MSE_RATE_CNTL, 0,
-+			DP_MSE_RATE_X, x,
-+			DP_MSE_RATE_Y, y);
-+	}
-+
-+	/* wait for update to be completed on the link */
-+	/* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
-+	/* is reset to 0 (not pending) */
-+	REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
-+			0,
-+			10, DP_MST_UPDATE_MAX_RETRY);
-+}
-+
-+static void dce110_stream_encoder_update_hdmi_info_packets(
-+	struct stream_encoder *enc,
-+	const struct encoder_info_frame *info_frame)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+
-+	if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
-+			enc110->se_mask->HDMI_AVI_INFO_SEND) {
-+
-+		if (info_frame->avi.valid) {
-+			const uint32_t *content =
-+				(const uint32_t *) &info_frame->avi.sb[0];
-+
-+			REG_WRITE(AFMT_AVI_INFO0, content[0]);
-+
-+			REG_WRITE(AFMT_AVI_INFO1, content[1]);
-+
-+			REG_WRITE(AFMT_AVI_INFO2, content[2]);
-+
-+			REG_WRITE(AFMT_AVI_INFO3, content[3]);
-+
-+			REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
-+						info_frame->avi.hb1);
-+
-+			REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
-+					HDMI_AVI_INFO_SEND, 1,
-+					HDMI_AVI_INFO_CONT, 1);
-+
-+			REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
-+							VBI_LINE_0 + 2);
-+
-+		} else {
-+			REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
-+				HDMI_AVI_INFO_SEND, 0,
-+				HDMI_AVI_INFO_CONT, 0);
-+		}
-+	}
-+
-+	if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
-+			enc110->se_mask->HDMI_AVI_INFO_SEND) {
-+		dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
-+		dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
-+		dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
-+		dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
-+	}
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	if (enc110->se_mask->HDMI_DB_DISABLE) {
-+		/* for bring up, disable dp double  TODO */
-+		if (REG(HDMI_DB_CONTROL))
-+			REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
-+
-+		dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
-+		dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
-+		dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
-+		dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
-+		dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
-+	}
-+#endif
-+}
-+
-+static void dce110_stream_encoder_stop_hdmi_info_packets(
-+	struct stream_encoder *enc)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+
-+	/* stop generic packets 0 & 1 on HDMI */
-+	REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
-+		HDMI_GENERIC1_CONT, 0,
-+		HDMI_GENERIC1_LINE, 0,
-+		HDMI_GENERIC1_SEND, 0,
-+		HDMI_GENERIC0_CONT, 0,
-+		HDMI_GENERIC0_LINE, 0,
-+		HDMI_GENERIC0_SEND, 0);
-+
-+	/* stop generic packets 2 & 3 on HDMI */
-+	REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
-+		HDMI_GENERIC0_CONT, 0,
-+		HDMI_GENERIC0_LINE, 0,
-+		HDMI_GENERIC0_SEND, 0,
-+		HDMI_GENERIC1_CONT, 0,
-+		HDMI_GENERIC1_LINE, 0,
-+		HDMI_GENERIC1_SEND, 0);
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	/* stop generic packets 2 & 3 on HDMI */
-+	if (REG(HDMI_GENERIC_PACKET_CONTROL2))
-+		REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
-+			HDMI_GENERIC0_CONT, 0,
-+			HDMI_GENERIC0_LINE, 0,
-+			HDMI_GENERIC0_SEND, 0,
-+			HDMI_GENERIC1_CONT, 0,
-+			HDMI_GENERIC1_LINE, 0,
-+			HDMI_GENERIC1_SEND, 0);
-+
-+	if (REG(HDMI_GENERIC_PACKET_CONTROL3))
-+		REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
-+			HDMI_GENERIC0_CONT, 0,
-+			HDMI_GENERIC0_LINE, 0,
-+			HDMI_GENERIC0_SEND, 0,
-+			HDMI_GENERIC1_CONT, 0,
-+			HDMI_GENERIC1_LINE, 0,
-+			HDMI_GENERIC1_SEND, 0);
-+#endif
-+}
-+
-+static void dce110_stream_encoder_update_dp_info_packets(
-+	struct stream_encoder *enc,
-+	const struct encoder_info_frame *info_frame)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	uint32_t value = REG_READ(DP_SEC_CNTL);
-+
-+	if (info_frame->vsc.valid)
-+		dce110_update_generic_info_packet(
-+					enc110,
-+					0,  /* packetIndex */
-+					&info_frame->vsc);
-+
-+	if (info_frame->spd.valid)
-+		dce110_update_generic_info_packet(
-+				enc110,
-+				2,  /* packetIndex */
-+				&info_frame->spd);
-+
-+	if (info_frame->hdrsmd.valid)
-+		dce110_update_generic_info_packet(
-+				enc110,
-+				3,  /* packetIndex */
-+				&info_frame->hdrsmd);
-+
-+	/* enable/disable transmission of packet(s).
-+	*  If enabled, packet transmission begins on the next frame
-+	*/
-+	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
-+	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
-+	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
-+
-+	/* This bit is the master enable bit.
-+	* When enabling secondary stream engine,
-+	* this master bit must also be set.
-+	* This register shared with audio info frame.
-+	* Therefore we need to enable master bit
-+	* if at least on of the fields is not 0
-+	*/
-+	if (value)
-+		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
-+}
-+
-+static void dce110_stream_encoder_stop_dp_info_packets(
-+	struct stream_encoder *enc)
-+{
-+	/* stop generic packets on DP */
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	uint32_t value = REG_READ(DP_SEC_CNTL);
-+
-+	if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
-+		REG_SET_7(DP_SEC_CNTL, 0,
-+			DP_SEC_GSP0_ENABLE, 0,
-+			DP_SEC_GSP1_ENABLE, 0,
-+			DP_SEC_GSP2_ENABLE, 0,
-+			DP_SEC_GSP3_ENABLE, 0,
-+			DP_SEC_AVI_ENABLE, 0,
-+			DP_SEC_MPG_ENABLE, 0,
-+			DP_SEC_STREAM_ENABLE, 0);
-+	}
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	if (enc110->se_mask->DP_SEC_GSP7_ENABLE) {
-+		REG_SET_10(DP_SEC_CNTL, 0,
-+			DP_SEC_GSP0_ENABLE, 0,
-+			DP_SEC_GSP1_ENABLE, 0,
-+			DP_SEC_GSP2_ENABLE, 0,
-+			DP_SEC_GSP3_ENABLE, 0,
-+			DP_SEC_GSP4_ENABLE, 0,
-+			DP_SEC_GSP5_ENABLE, 0,
-+			DP_SEC_GSP6_ENABLE, 0,
-+			DP_SEC_GSP7_ENABLE, 0,
-+			DP_SEC_MPG_ENABLE, 0,
-+			DP_SEC_STREAM_ENABLE, 0);
-+	}
-+#endif
-+	/* this register shared with audio info frame.
-+	 * therefore we need to keep master enabled
-+	 * if at least one of the fields is not 0 */
-+
-+	if (value)
-+		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
-+
-+}
-+
-+static void dce110_stream_encoder_dp_blank(
-+	struct stream_encoder *enc)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	uint32_t retries = 0;
-+	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
-+
-+	/* Note: For CZ, we are changing driver default to disable
-+	 * stream deferred to next VBLANK. If results are positive, we
-+	 * will make the same change to all DCE versions. There are a
-+	 * handful of panels that cannot handle disable stream at
-+	 * HBLANK and will result in a white line flash across the
-+	 * screen on stream disable. */
-+
-+	/* Specify the video stream disable point
-+	 * (2 = start of the next vertical blank) */
-+	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
-+	/* Larger delay to wait until VBLANK - use max retry of
-+	* 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
-+	* a little more because we may not trust delay accuracy.
-+	*/
-+	max_retries = DP_BLANK_MAX_RETRY * 150;
-+
-+	/* disable DP stream */
-+	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
-+
-+	/* the encoder stops sending the video stream
-+	* at the start of the vertical blanking.
-+	* Poll for DP_VID_STREAM_STATUS == 0
-+	*/
-+
-+	REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
-+			0,
-+			10, max_retries);
-+
-+	ASSERT(retries <= max_retries);
-+
-+	/* Tell the DP encoder to ignore timing from CRTC, must be done after
-+	* the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
-+	* complete, stream status will be stuck in video stream enabled state,
-+	* i.e. DP_VID_STREAM_STATUS stuck at 1.
-+	*/
-+
-+	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
-+}
-+
-+/* output video stream to link encoder */
-+static void dce110_stream_encoder_dp_unblank(
-+	struct stream_encoder *enc,
-+	const struct encoder_unblank_param *param)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+
-+	if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
-+		uint32_t n_vid = 0x8000;
-+		uint32_t m_vid;
-+
-+		/* M / N = Fstream / Flink
-+		* m_vid / n_vid = pixel rate / link rate
-+		*/
-+
-+		uint64_t m_vid_l = n_vid;
-+
-+		m_vid_l *= param->pixel_clk_khz;
-+		m_vid_l = div_u64(m_vid_l,
-+			param->link_settings.link_rate
-+				* LINK_RATE_REF_FREQ_IN_KHZ);
-+
-+		m_vid = (uint32_t) m_vid_l;
-+
-+		/* enable auto measurement */
-+
-+		REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
-+
-+		/* auto measurement need 1 full 0x8000 symbol cycle to kick in,
-+		 * therefore program initial value for Mvid and Nvid
-+		 */
-+
-+		REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
-+
-+		REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
-+
-+		REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
-+	}
-+
-+	/* set DIG_START to 0x1 to resync FIFO */
-+
-+	REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
-+
-+	/* switch DP encoder to CRTC data */
-+
-+	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
-+
-+	/* wait 100us for DIG/DP logic to prime
-+	* (i.e. a few video lines)
-+	*/
-+	udelay(100);
-+
-+	/* the hardware would start sending video at the start of the next DP
-+	* frame (i.e. rising edge of the vblank).
-+	* NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
-+	* register has no effect on enable transition! HW always guarantees
-+	* VID_STREAM enable at start of next frame, and this is not
-+	* programmable
-+	*/
-+
-+	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
-+}
-+
-+static void dce110_stream_encoder_set_avmute(
-+	struct stream_encoder *enc,
-+	bool enable)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	unsigned int value = enable ? 1 : 0;
-+
-+	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
-+}
-+
-+
-+#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
-+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
-+
-+#include "include/audio_types.h"
-+
-+/**
-+* speakersToChannels
-+*
-+* @brief
-+*  translate speakers to channels
-+*
-+*  FL  - Front Left
-+*  FR  - Front Right
-+*  RL  - Rear Left
-+*  RR  - Rear Right
-+*  RC  - Rear Center
-+*  FC  - Front Center
-+*  FLC - Front Left Center
-+*  FRC - Front Right Center
-+*  RLC - Rear Left Center
-+*  RRC - Rear Right Center
-+*  LFE - Low Freq Effect
-+*
-+*               FC
-+*          FLC      FRC
-+*    FL                    FR
-+*
-+*                    LFE
-+*              ()
-+*
-+*
-+*    RL                    RR
-+*          RLC      RRC
-+*               RC
-+*
-+*             ch  8   7   6   5   4   3   2   1
-+* 0b00000011      -   -   -   -   -   -   FR  FL
-+* 0b00000111      -   -   -   -   -   LFE FR  FL
-+* 0b00001011      -   -   -   -   FC  -   FR  FL
-+* 0b00001111      -   -   -   -   FC  LFE FR  FL
-+* 0b00010011      -   -   -   RC  -   -   FR  FL
-+* 0b00010111      -   -   -   RC  -   LFE FR  FL
-+* 0b00011011      -   -   -   RC  FC  -   FR  FL
-+* 0b00011111      -   -   -   RC  FC  LFE FR  FL
-+* 0b00110011      -   -   RR  RL  -   -   FR  FL
-+* 0b00110111      -   -   RR  RL  -   LFE FR  FL
-+* 0b00111011      -   -   RR  RL  FC  -   FR  FL
-+* 0b00111111      -   -   RR  RL  FC  LFE FR  FL
-+* 0b01110011      -   RC  RR  RL  -   -   FR  FL
-+* 0b01110111      -   RC  RR  RL  -   LFE FR  FL
-+* 0b01111011      -   RC  RR  RL  FC  -   FR  FL
-+* 0b01111111      -   RC  RR  RL  FC  LFE FR  FL
-+* 0b11110011      RRC RLC RR  RL  -   -   FR  FL
-+* 0b11110111      RRC RLC RR  RL  -   LFE FR  FL
-+* 0b11111011      RRC RLC RR  RL  FC  -   FR  FL
-+* 0b11111111      RRC RLC RR  RL  FC  LFE FR  FL
-+* 0b11000011      FRC FLC -   -   -   -   FR  FL
-+* 0b11000111      FRC FLC -   -   -   LFE FR  FL
-+* 0b11001011      FRC FLC -   -   FC  -   FR  FL
-+* 0b11001111      FRC FLC -   -   FC  LFE FR  FL
-+* 0b11010011      FRC FLC -   RC  -   -   FR  FL
-+* 0b11010111      FRC FLC -   RC  -   LFE FR  FL
-+* 0b11011011      FRC FLC -   RC  FC  -   FR  FL
-+* 0b11011111      FRC FLC -   RC  FC  LFE FR  FL
-+* 0b11110011      FRC FLC RR  RL  -   -   FR  FL
-+* 0b11110111      FRC FLC RR  RL  -   LFE FR  FL
-+* 0b11111011      FRC FLC RR  RL  FC  -   FR  FL
-+* 0b11111111      FRC FLC RR  RL  FC  LFE FR  FL
-+*
-+* @param
-+*  speakers - speaker information as it comes from CEA audio block
-+*/
-+/* translate speakers to channels */
-+
-+union audio_cea_channels {
-+	uint8_t all;
-+	struct audio_cea_channels_bits {
-+		uint32_t FL:1;
-+		uint32_t FR:1;
-+		uint32_t LFE:1;
-+		uint32_t FC:1;
-+		uint32_t RL_RC:1;
-+		uint32_t RR:1;
-+		uint32_t RC_RLC_FLC:1;
-+		uint32_t RRC_FRC:1;
-+	} channels;
-+};
-+
-+struct audio_clock_info {
-+	/* pixel clock frequency*/
-+	uint32_t pixel_clock_in_10khz;
-+	/* N - 32KHz audio */
-+	uint32_t n_32khz;
-+	/* CTS - 32KHz audio*/
-+	uint32_t cts_32khz;
-+	uint32_t n_44khz;
-+	uint32_t cts_44khz;
-+	uint32_t n_48khz;
-+	uint32_t cts_48khz;
-+};
-+
-+/* 25.2MHz/1.001*/
-+/* 25.2MHz/1.001*/
-+/* 25.2MHz*/
-+/* 27MHz */
-+/* 27MHz*1.001*/
-+/* 27MHz*1.001*/
-+/* 54MHz*/
-+/* 54MHz*1.001*/
-+/* 74.25MHz/1.001*/
-+/* 74.25MHz*/
-+/* 148.5MHz/1.001*/
-+/* 148.5MHz*/
-+
-+static const struct audio_clock_info audio_clock_info_table[16] = {
-+	{2517, 4576, 28125, 7007, 31250, 6864, 28125},
-+	{2518, 4576, 28125, 7007, 31250, 6864, 28125},
-+	{2520, 4096, 25200, 6272, 28000, 6144, 25200},
-+	{2700, 4096, 27000, 6272, 30000, 6144, 27000},
-+	{2702, 4096, 27027, 6272, 30030, 6144, 27027},
-+	{2703, 4096, 27027, 6272, 30030, 6144, 27027},
-+	{5400, 4096, 54000, 6272, 60000, 6144, 54000},
-+	{5405, 4096, 54054, 6272, 60060, 6144, 54054},
-+	{7417, 11648, 210937, 17836, 234375, 11648, 140625},
-+	{7425, 4096, 74250, 6272, 82500, 6144, 74250},
-+	{14835, 11648, 421875, 8918, 234375, 5824, 140625},
-+	{14850, 4096, 148500, 6272, 165000, 6144, 148500},
-+	{29670, 5824, 421875, 4459, 234375, 5824, 281250},
-+	{29700, 3072, 222750, 4704, 247500, 5120, 247500},
-+	{59340, 5824, 843750, 8918, 937500, 5824, 562500},
-+	{59400, 3072, 445500, 9408, 990000, 6144, 594000}
-+};
-+
-+static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
-+	{2517,  9152,  84375,  7007,  48875,  9152,  56250},
-+	{2518,  9152,  84375,  7007,  48875,  9152,  56250},
-+	{2520,  4096,  37800,  6272,  42000,  6144,  37800},
-+	{2700,  4096,  40500,  6272,  45000,  6144,  40500},
-+	{2702,  8192,  81081,  6272,  45045,  8192,  54054},
-+	{2703,  8192,  81081,  6272,  45045,  8192,  54054},
-+	{5400,  4096,  81000,  6272,  90000,  6144,  81000},
-+	{5405,  4096,  81081,  6272,  90090,  6144,  81081},
-+	{7417, 11648, 316406, 17836, 351562, 11648, 210937},
-+	{7425, 4096, 111375,  6272, 123750,  6144, 111375},
-+	{14835, 11648, 632812, 17836, 703125, 11648, 421875},
-+	{14850, 4096, 222750,  6272, 247500,  6144, 222750},
-+	{29670, 5824, 632812,  8918, 703125,  5824, 421875},
-+	{29700, 4096, 445500,  4704, 371250,  5120, 371250}
-+};
-+
-+static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
-+	{2517,  4576,  56250,  7007,  62500,  6864,  56250},
-+	{2518,  4576,  56250,  7007,  62500,  6864,  56250},
-+	{2520,  4096,  50400,  6272,  56000,  6144,  50400},
-+	{2700,  4096,  54000,  6272,  60000,  6144,  54000},
-+	{2702,  4096,  54054,  6267,  60060,  8192,  54054},
-+	{2703,  4096,  54054,  6272,  60060,  8192,  54054},
-+	{5400,  4096, 108000,  6272, 120000,  6144, 108000},
-+	{5405,  4096, 108108,  6272, 120120,  6144, 108108},
-+	{7417, 11648, 421875, 17836, 468750, 11648, 281250},
-+	{7425,  4096, 148500,  6272, 165000,  6144, 148500},
-+	{14835, 11648, 843750,  8918, 468750, 11648, 281250},
-+	{14850, 4096, 297000,  6272, 330000,  6144, 297000},
-+	{29670, 5824, 843750,  4459, 468750,  5824, 562500},
-+	{29700, 3072, 445500,  4704, 495000,  5120, 495000}
-+
-+
-+};
-+
-+static union audio_cea_channels speakers_to_channels(
-+	struct audio_speaker_flags speaker_flags)
-+{
-+	union audio_cea_channels cea_channels = {0};
-+
-+	/* these are one to one */
-+	cea_channels.channels.FL = speaker_flags.FL_FR;
-+	cea_channels.channels.FR = speaker_flags.FL_FR;
-+	cea_channels.channels.LFE = speaker_flags.LFE;
-+	cea_channels.channels.FC = speaker_flags.FC;
-+
-+	/* if Rear Left and Right exist move RC speaker to channel 7
-+	 * otherwise to channel 5
-+	 */
-+	if (speaker_flags.RL_RR) {
-+		cea_channels.channels.RL_RC = speaker_flags.RL_RR;
-+		cea_channels.channels.RR = speaker_flags.RL_RR;
-+		cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
-+	} else {
-+		cea_channels.channels.RL_RC = speaker_flags.RC;
-+	}
-+
-+	/* FRONT Left Right Center and REAR Left Right Center are exclusive */
-+	if (speaker_flags.FLC_FRC) {
-+		cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
-+		cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
-+	} else {
-+		cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
-+		cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
-+	}
-+
-+	return cea_channels;
-+}
-+
-+static uint32_t calc_max_audio_packets_per_line(
-+	const struct audio_crtc_info *crtc_info)
-+{
-+	uint32_t max_packets_per_line;
-+
-+	max_packets_per_line =
-+		crtc_info->h_total - crtc_info->h_active;
-+
-+	if (crtc_info->pixel_repetition)
-+		max_packets_per_line *= crtc_info->pixel_repetition;
-+
-+	/* for other hdmi features */
-+	max_packets_per_line -= 58;
-+	/* for Control Period */
-+	max_packets_per_line -= 16;
-+	/* Number of Audio Packets per Line */
-+	max_packets_per_line /= 32;
-+
-+	return max_packets_per_line;
-+}
-+
-+static void get_audio_clock_info(
-+	enum dc_color_depth color_depth,
-+	uint32_t crtc_pixel_clock_in_khz,
-+	uint32_t actual_pixel_clock_in_khz,
-+	struct audio_clock_info *audio_clock_info)
-+{
-+	const struct audio_clock_info *clock_info;
-+	uint32_t index;
-+	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
-+	uint32_t audio_array_size;
-+
-+	switch (color_depth) {
-+	case COLOR_DEPTH_161616:
-+		clock_info = audio_clock_info_table_48bpc;
-+		audio_array_size = ARRAY_SIZE(
-+				audio_clock_info_table_48bpc);
-+		break;
-+	case COLOR_DEPTH_121212:
-+		clock_info = audio_clock_info_table_36bpc;
-+		audio_array_size = ARRAY_SIZE(
-+				audio_clock_info_table_36bpc);
-+		break;
-+	default:
-+		clock_info = audio_clock_info_table;
-+		audio_array_size = ARRAY_SIZE(
-+				audio_clock_info_table);
-+		break;
-+	}
-+
-+	if (clock_info != NULL) {
-+		/* search for exact pixel clock in table */
-+		for (index = 0; index < audio_array_size; index++) {
-+			if (clock_info[index].pixel_clock_in_10khz >
-+				crtc_pixel_clock_in_10khz)
-+				break;  /* not match */
-+			else if (clock_info[index].pixel_clock_in_10khz ==
-+					crtc_pixel_clock_in_10khz) {
-+				/* match found */
-+				*audio_clock_info = clock_info[index];
-+				return;
-+			}
-+		}
-+	}
-+
-+	/* not found */
-+	if (actual_pixel_clock_in_khz == 0)
-+		actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
-+
-+	/* See HDMI spec  the table entry under
-+	 *  pixel clock of "Other". */
-+	audio_clock_info->pixel_clock_in_10khz =
-+			actual_pixel_clock_in_khz / 10;
-+	audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
-+	audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
-+	audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
-+
-+	audio_clock_info->n_32khz = 4096;
-+	audio_clock_info->n_44khz = 6272;
-+	audio_clock_info->n_48khz = 6144;
-+}
-+
-+static void dce110_se_audio_setup(
-+	struct stream_encoder *enc,
-+	unsigned int az_inst,
-+	struct audio_info *audio_info)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+
-+	uint32_t speakers = 0;
-+	uint32_t channels = 0;
-+
-+	ASSERT(audio_info);
-+	if (audio_info == NULL)
-+		/* This should not happen.it does so we don't get BSOD*/
-+		return;
-+
-+	speakers = audio_info->flags.info.ALLSPEAKERS;
-+	channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
-+
-+	/* setup the audio stream source select (audio -> dig mapping) */
-+	REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
-+
-+	/* Channel allocation */
-+	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
-+}
-+
-+static void dce110_se_setup_hdmi_audio(
-+	struct stream_encoder *enc,
-+	const struct audio_crtc_info *crtc_info)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+
-+	struct audio_clock_info audio_clock_info = {0};
-+	uint32_t max_packets_per_line;
-+
-+	/* For now still do calculation, although this field is ignored when
-+	above HDMI_PACKET_GEN_VERSION set to 1 */
-+	max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
-+
-+	/* HDMI_AUDIO_PACKET_CONTROL */
-+	REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
-+			HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
-+			HDMI_AUDIO_DELAY_EN, 1);
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL */
-+	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL2 */
-+	REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
-+			AFMT_AUDIO_LAYOUT_OVRD, 0,
-+			AFMT_60958_OSF_OVRD, 0);
-+
-+	/* HDMI_ACR_PACKET_CONTROL */
-+	REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
-+			HDMI_ACR_AUTO_SEND, 1,
-+			HDMI_ACR_SOURCE, 0,
-+			HDMI_ACR_AUDIO_PRIORITY, 0);
-+
-+	/* Program audio clock sample/regeneration parameters */
-+	get_audio_clock_info(crtc_info->color_depth,
-+			     crtc_info->requested_pixel_clock,
-+			     crtc_info->calculated_pixel_clock,
-+			     &audio_clock_info);
-+	dm_logger_write(enc->ctx->logger, LOG_HW_AUDIO,
-+			"\n%s:Input::requested_pixel_clock = %d"	\
-+			"calculated_pixel_clock = %d \n", __func__,	\
-+			crtc_info->requested_pixel_clock,		\
-+			crtc_info->calculated_pixel_clock);
-+
-+	/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
-+	REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
-+
-+	/* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
-+	REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
-+
-+	/* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
-+	REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
-+
-+	/* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
-+	REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
-+
-+	/* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
-+	REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
-+
-+	/* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
-+	REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
-+
-+	/* Video driver cannot know in advance which sample rate will
-+	   be used by HD Audio driver
-+	   HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
-+	   programmed below in interruppt callback */
-+
-+	/* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
-+	AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
-+	REG_UPDATE_2(AFMT_60958_0,
-+			AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
-+			AFMT_60958_CS_CLOCK_ACCURACY, 0);
-+
-+	/* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
-+	REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
-+
-+	/*AFMT_60958_2 now keep this settings until
-+	 *  Programming guide comes out*/
-+	REG_UPDATE_6(AFMT_60958_2,
-+			AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
-+			AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
-+			AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
-+			AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
-+			AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
-+			AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
-+}
-+
-+static void dce110_se_setup_dp_audio(
-+	struct stream_encoder *enc)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+
-+	/* --- DP Audio packet configurations --- */
-+
-+	/* ATP Configuration */
-+	REG_SET(DP_SEC_AUD_N, 0,
-+			DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
-+
-+	/* Async/auto-calc timestamp mode */
-+	REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
-+			DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
-+
-+	/* --- The following are the registers
-+	 *  copied from the SetupHDMI --- */
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL */
-+	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
-+
-+	/* AFMT_AUDIO_PACKET_CONTROL2 */
-+	/* Program the ATP and AIP next */
-+	REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
-+			AFMT_AUDIO_LAYOUT_OVRD, 0,
-+			AFMT_60958_OSF_OVRD, 0);
-+
-+	/* AFMT_INFOFRAME_CONTROL0 */
-+	REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
-+
-+	/* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
-+	REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
-+}
-+
-+static void dce110_se_enable_audio_clock(
-+	struct stream_encoder *enc,
-+	bool enable)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+
-+	if (REG(AFMT_CNTL) == 0)
-+		return;   /* DCE8/10 does not have this register */
-+
-+	REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
-+
-+	/* wait for AFMT clock to turn on,
-+	 * expectation: this should complete in 1-2 reads
-+	 *
-+	 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
-+	 *
-+	 * TODO: wait for clock_on does not work well. May need HW
-+	 * program sequence. But audio seems work normally even without wait
-+	 * for clock_on status change
-+	 */
-+}
-+
-+static void dce110_se_enable_dp_audio(
-+	struct stream_encoder *enc)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+
-+	/* Enable Audio packets */
-+	REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
-+
-+	/* Program the ATP and AIP next */
-+	REG_UPDATE_2(DP_SEC_CNTL,
-+			DP_SEC_ATP_ENABLE, 1,
-+			DP_SEC_AIP_ENABLE, 1);
-+
-+	/* Program STREAM_ENABLE after all the other enables. */
-+	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
-+}
-+
-+static void dce110_se_disable_dp_audio(
-+	struct stream_encoder *enc)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	uint32_t value = REG_READ(DP_SEC_CNTL);
-+
-+	/* Disable Audio packets */
-+	REG_UPDATE_5(DP_SEC_CNTL,
-+			DP_SEC_ASP_ENABLE, 0,
-+			DP_SEC_ATP_ENABLE, 0,
-+			DP_SEC_AIP_ENABLE, 0,
-+			DP_SEC_ACM_ENABLE, 0,
-+			DP_SEC_STREAM_ENABLE, 0);
-+
-+	/* This register shared with encoder info frame. Therefore we need to
-+	keep master enabled if at least on of the fields is not 0 */
-+	if (value != 0)
-+		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
-+
-+}
-+
-+void dce110_se_audio_mute_control(
-+	struct stream_encoder *enc,
-+	bool mute)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+
-+	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
-+}
-+
-+void dce110_se_dp_audio_setup(
-+	struct stream_encoder *enc,
-+	unsigned int az_inst,
-+	struct audio_info *info)
-+{
-+	dce110_se_audio_setup(enc, az_inst, info);
-+}
-+
-+void dce110_se_dp_audio_enable(
-+	struct stream_encoder *enc)
-+{
-+	dce110_se_enable_audio_clock(enc, true);
-+	dce110_se_setup_dp_audio(enc);
-+	dce110_se_enable_dp_audio(enc);
-+}
-+
-+void dce110_se_dp_audio_disable(
-+	struct stream_encoder *enc)
-+{
-+	dce110_se_disable_dp_audio(enc);
-+	dce110_se_enable_audio_clock(enc, false);
-+}
-+
-+void dce110_se_hdmi_audio_setup(
-+	struct stream_encoder *enc,
-+	unsigned int az_inst,
-+	struct audio_info *info,
-+	struct audio_crtc_info *audio_crtc_info)
-+{
-+	dce110_se_enable_audio_clock(enc, true);
-+	dce110_se_setup_hdmi_audio(enc, audio_crtc_info);
-+	dce110_se_audio_setup(enc, az_inst, info);
-+}
-+
-+void dce110_se_hdmi_audio_disable(
-+	struct stream_encoder *enc)
-+{
-+	dce110_se_enable_audio_clock(enc, false);
-+}
-+
-+
-+static void setup_stereo_sync(
-+	struct stream_encoder *enc,
-+	int tg_inst, bool enable)
-+{
-+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-+	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
-+	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
-+}
-+
-+
-+static const struct stream_encoder_funcs dce110_str_enc_funcs = {
-+	.dp_set_stream_attribute =
-+		dce110_stream_encoder_dp_set_stream_attribute,
-+	.hdmi_set_stream_attribute =
-+		dce110_stream_encoder_hdmi_set_stream_attribute,
-+	.dvi_set_stream_attribute =
-+		dce110_stream_encoder_dvi_set_stream_attribute,
-+	.set_mst_bandwidth =
-+		dce110_stream_encoder_set_mst_bandwidth,
-+	.update_hdmi_info_packets =
-+		dce110_stream_encoder_update_hdmi_info_packets,
-+	.stop_hdmi_info_packets =
-+		dce110_stream_encoder_stop_hdmi_info_packets,
-+	.update_dp_info_packets =
-+		dce110_stream_encoder_update_dp_info_packets,
-+	.stop_dp_info_packets =
-+		dce110_stream_encoder_stop_dp_info_packets,
-+	.dp_blank =
-+		dce110_stream_encoder_dp_blank,
-+	.dp_unblank =
-+		dce110_stream_encoder_dp_unblank,
-+	.audio_mute_control = dce110_se_audio_mute_control,
-+
-+	.dp_audio_setup = dce110_se_dp_audio_setup,
-+	.dp_audio_enable = dce110_se_dp_audio_enable,
-+	.dp_audio_disable = dce110_se_dp_audio_disable,
-+
-+	.hdmi_audio_setup = dce110_se_hdmi_audio_setup,
-+	.hdmi_audio_disable = dce110_se_hdmi_audio_disable,
-+	.setup_stereo_sync  = setup_stereo_sync,
-+	.set_avmute = dce110_stream_encoder_set_avmute,
-+
-+};
-+
-+void dce110_stream_encoder_construct(
-+	struct dce110_stream_encoder *enc110,
-+	struct dc_context *ctx,
-+	struct dc_bios *bp,
-+	enum engine_id eng_id,
-+	const struct dce110_stream_enc_registers *regs,
-+	const struct dce_stream_encoder_shift *se_shift,
-+	const struct dce_stream_encoder_mask *se_mask)
-+{
-+	enc110->base.funcs = &dce110_str_enc_funcs;
-+	enc110->base.ctx = ctx;
-+	enc110->base.id = eng_id;
-+	enc110->base.bp = bp;
-+	enc110->regs = regs;
-+	enc110->se_shift = se_shift;
-+	enc110->se_mask = se_mask;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h.0130~	2017-12-14 06:39:58.419903570 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h	2017-12-14 06:39:58.419903570 +0100
-@@ -0,0 +1,733 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_STREAM_ENCODER_DCE110_H__
-+#define __DC_STREAM_ENCODER_DCE110_H__
-+
-+#include "stream_encoder.h"
-+
-+#define DCE110STRENC_FROM_STRENC(stream_encoder)\
-+	container_of(stream_encoder, struct dce110_stream_encoder, base)
-+
-+#ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
-+	#define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK       0x00000010L
-+	#define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK         0x00000300L
-+	#define	TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT     0x00000004
-+	#define	TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT       0x00000008
-+#endif
-+
-+
-+#define SE_COMMON_REG_LIST_DCE_BASE(id) \
-+	SE_COMMON_REG_LIST_BASE(id),\
-+	SRI(AFMT_AVI_INFO0, DIG, id), \
-+	SRI(AFMT_AVI_INFO1, DIG, id), \
-+	SRI(AFMT_AVI_INFO2, DIG, id), \
-+	SRI(AFMT_AVI_INFO3, DIG, id)
-+
-+#define SE_COMMON_REG_LIST_BASE(id) \
-+	SRI(AFMT_GENERIC_0, DIG, id), \
-+	SRI(AFMT_GENERIC_1, DIG, id), \
-+	SRI(AFMT_GENERIC_2, DIG, id), \
-+	SRI(AFMT_GENERIC_3, DIG, id), \
-+	SRI(AFMT_GENERIC_4, DIG, id), \
-+	SRI(AFMT_GENERIC_5, DIG, id), \
-+	SRI(AFMT_GENERIC_6, DIG, id), \
-+	SRI(AFMT_GENERIC_7, DIG, id), \
-+	SRI(AFMT_GENERIC_HDR, DIG, id), \
-+	SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
-+	SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
-+	SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
-+	SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
-+	SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
-+	SRI(AFMT_60958_0, DIG, id), \
-+	SRI(AFMT_60958_1, DIG, id), \
-+	SRI(AFMT_60958_2, DIG, id), \
-+	SRI(DIG_FE_CNTL, DIG, id), \
-+	SRI(HDMI_CONTROL, DIG, id), \
-+	SRI(HDMI_GC, DIG, id), \
-+	SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
-+	SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
-+	SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
-+	SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
-+	SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
-+	SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
-+	SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
-+	SRI(HDMI_ACR_32_0, DIG, id),\
-+	SRI(HDMI_ACR_32_1, DIG, id),\
-+	SRI(HDMI_ACR_44_0, DIG, id),\
-+	SRI(HDMI_ACR_44_1, DIG, id),\
-+	SRI(HDMI_ACR_48_0, DIG, id),\
-+	SRI(HDMI_ACR_48_1, DIG, id),\
-+	SRI(TMDS_CNTL, DIG, id), \
-+	SRI(DP_MSE_RATE_CNTL, DP, id), \
-+	SRI(DP_MSE_RATE_UPDATE, DP, id), \
-+	SRI(DP_PIXEL_FORMAT, DP, id), \
-+	SRI(DP_SEC_CNTL, DP, id), \
-+	SRI(DP_STEER_FIFO, DP, id), \
-+	SRI(DP_VID_M, DP, id), \
-+	SRI(DP_VID_N, DP, id), \
-+	SRI(DP_VID_STREAM_CNTL, DP, id), \
-+	SRI(DP_VID_TIMING, DP, id), \
-+	SRI(DP_SEC_AUD_N, DP, id), \
-+	SRI(DP_SEC_TIMESTAMP, DP, id)
-+
-+#define SE_COMMON_REG_LIST(id)\
-+	SE_COMMON_REG_LIST_DCE_BASE(id), \
-+	SRI(AFMT_CNTL, DIG, id)
-+
-+#define SE_DCN_REG_LIST(id)\
-+	SE_COMMON_REG_LIST_BASE(id),\
-+	SRI(AFMT_CNTL, DIG, id),\
-+	SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\
-+	SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
-+	SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
-+	SRI(DP_DB_CNTL, DP, id), \
-+	SRI(DP_MSA_MISC, DP, id), \
-+	SRI(DP_MSA_COLORIMETRY, DP, id), \
-+	SRI(DP_MSA_TIMING_PARAM1, DP, id), \
-+	SRI(DP_MSA_TIMING_PARAM2, DP, id), \
-+	SRI(DP_MSA_TIMING_PARAM3, DP, id), \
-+	SRI(DP_MSA_TIMING_PARAM4, DP, id), \
-+	SRI(HDMI_DB_CONTROL, DIG, id)
-+
-+#define SE_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+#define SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
-+	SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
-+	SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
-+	SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
-+	SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
-+	SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
-+	SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
-+	SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
-+	SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
-+	SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
-+	SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
-+	SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
-+	SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
-+	SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
-+	SE_SF(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
-+	SE_SF(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
-+	SE_SF(DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
-+	SE_SF(DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\
-+	SE_SF(HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
-+	SE_SF(HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
-+	SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
-+	SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
-+	SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
-+	SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
-+	SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
-+	SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
-+	SE_SF(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
-+	SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
-+	SE_SF(HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
-+	SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
-+	SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
-+	SE_SF(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
-+	SE_SF(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
-+	SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\
-+	SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
-+	SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
-+	SE_SF(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
-+	SE_SF(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
-+	SE_SF(DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
-+	SE_SF(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
-+	SE_SF(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
-+	SE_SF(DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
-+	SE_SF(DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
-+	SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
-+	SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
-+	SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
-+	SE_SF(DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
-+	SE_SF(DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
-+	SE_SF(DP_VID_N, DP_VID_N, mask_sh),\
-+	SE_SF(DP_VID_M, DP_VID_M, mask_sh),\
-+	SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\
-+	SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
-+	SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
-+	SE_SF(AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
-+	SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
-+	SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
-+	SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
-+	SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
-+	SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
-+	SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
-+	SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
-+	SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
-+	SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
-+	SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
-+	SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
-+	SE_SF(HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
-+	SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
-+	SE_SF(HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
-+	SE_SF(HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
-+	SE_SF(AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
-+	SE_SF(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
-+	SE_SF(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
-+	SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
-+	SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
-+	SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
-+	SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
-+	SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
-+	SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
-+	SE_SF(DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
-+	SE_SF(DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
-+	SE_SF(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
-+	SE_SF(DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
-+	SE_SF(DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
-+	SE_SF(DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
-+	SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh)
-+
-+#define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\
-+	SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
-+
-+#define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
-+	SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
-+	SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
-+	SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
-+	SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
-+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
-+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
-+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
-+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
-+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
-+	SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
-+	SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
-+	SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
-+	SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
-+	SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
-+	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
-+	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
-+	SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
-+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
-+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
-+	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
-+	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
-+	SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
-+	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
-+	SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
-+	SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
-+	SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
-+	SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
-+	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
-+	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
-+	SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
-+	SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
-+	SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
-+	SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
-+	SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
-+	SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
-+	SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
-+	SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
-+	SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
-+	SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
-+	SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
-+	SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
-+	SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
-+	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
-+	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
-+	SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
-+	SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
-+	SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
-+	SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
-+	SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
-+	SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
-+	SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
-+	SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
-+	SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
-+	SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
-+	SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
-+	SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
-+	SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
-+	SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
-+	SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
-+	SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
-+	SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
-+	SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
-+	SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
-+	SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
-+	SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
-+	SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
-+	SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
-+	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
-+	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh)
-+
-+#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
-+	SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
-+
-+#define SE_COMMON_MASK_SH_LIST_DCE80_100(mask_sh)\
-+	SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
-+	SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
-+	SE_SF(TMDS_CNTL, TMDS_COLOR_FORMAT, mask_sh)
-+
-+#define SE_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
-+	SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
-+	SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
-+	SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
-+	SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
-+	SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
-+	SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
-+	SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
-+	SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh)
-+
-+#define SE_COMMON_MASK_SH_LIST_DCE112(mask_sh)\
-+	SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
-+	SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
-+	SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
-+	SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
-+	SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
-+	SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
-+	SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
-+
-+#define SE_COMMON_MASK_SH_LIST_DCE120(mask_sh)\
-+	SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
-+	SE_SF(DP0_DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
-+	SE_SF(DP0_DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\
-+	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\
-+	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
-+	SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
-+	SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
-+	SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
-+
-+#define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
-+	SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
-+	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
-+	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
-+	SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
-+	SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
-+	SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
-+	SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
-+	SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
-+	SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
-+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
-+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
-+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
-+	SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
-+	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
-+	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
-+	SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
-+	SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
-+
-+struct dce_stream_encoder_shift {
-+	uint8_t AFMT_GENERIC_INDEX;
-+	uint8_t AFMT_GENERIC0_UPDATE;
-+	uint8_t AFMT_GENERIC2_UPDATE;
-+	uint8_t AFMT_GENERIC_HB0;
-+	uint8_t AFMT_GENERIC_HB1;
-+	uint8_t AFMT_GENERIC_HB2;
-+	uint8_t AFMT_GENERIC_HB3;
-+	uint8_t AFMT_GENERIC_LOCK_STATUS;
-+	uint8_t AFMT_GENERIC_CONFLICT;
-+	uint8_t AFMT_GENERIC_CONFLICT_CLR;
-+	uint8_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
-+	uint8_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
-+	uint8_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
-+	uint8_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
-+	uint8_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
-+	uint8_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
-+	uint8_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
-+	uint8_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
-+	uint8_t AFMT_GENERIC0_FRAME_UPDATE;
-+	uint8_t AFMT_GENERIC1_FRAME_UPDATE;
-+	uint8_t AFMT_GENERIC2_FRAME_UPDATE;
-+	uint8_t AFMT_GENERIC3_FRAME_UPDATE;
-+	uint8_t AFMT_GENERIC4_FRAME_UPDATE;
-+	uint8_t AFMT_GENERIC5_FRAME_UPDATE;
-+	uint8_t AFMT_GENERIC6_FRAME_UPDATE;
-+	uint8_t AFMT_GENERIC7_FRAME_UPDATE;
-+	uint8_t HDMI_GENERIC0_CONT;
-+	uint8_t HDMI_GENERIC0_SEND;
-+	uint8_t HDMI_GENERIC0_LINE;
-+	uint8_t HDMI_GENERIC1_CONT;
-+	uint8_t HDMI_GENERIC1_SEND;
-+	uint8_t HDMI_GENERIC1_LINE;
-+	uint8_t DP_PIXEL_ENCODING;
-+	uint8_t DP_COMPONENT_DEPTH;
-+	uint8_t DP_DYN_RANGE;
-+	uint8_t DP_YCBCR_RANGE;
-+	uint8_t HDMI_PACKET_GEN_VERSION;
-+	uint8_t HDMI_KEEPOUT_MODE;
-+	uint8_t HDMI_DEEP_COLOR_ENABLE;
-+	uint8_t HDMI_CLOCK_CHANNEL_RATE;
-+	uint8_t HDMI_DEEP_COLOR_DEPTH;
-+	uint8_t HDMI_GC_CONT;
-+	uint8_t HDMI_GC_SEND;
-+	uint8_t HDMI_NULL_SEND;
-+	uint8_t HDMI_DATA_SCRAMBLE_EN;
-+	uint8_t HDMI_AUDIO_INFO_SEND;
-+	uint8_t AFMT_AUDIO_INFO_UPDATE;
-+	uint8_t HDMI_AUDIO_INFO_LINE;
-+	uint8_t HDMI_GC_AVMUTE;
-+	uint8_t DP_MSE_RATE_X;
-+	uint8_t DP_MSE_RATE_Y;
-+	uint8_t DP_MSE_RATE_UPDATE_PENDING;
-+	uint8_t AFMT_AVI_INFO_VERSION;
-+	uint8_t HDMI_AVI_INFO_SEND;
-+	uint8_t HDMI_AVI_INFO_CONT;
-+	uint8_t HDMI_AVI_INFO_LINE;
-+	uint8_t DP_SEC_GSP0_ENABLE;
-+	uint8_t DP_SEC_STREAM_ENABLE;
-+	uint8_t DP_SEC_GSP1_ENABLE;
-+	uint8_t DP_SEC_GSP2_ENABLE;
-+	uint8_t DP_SEC_GSP3_ENABLE;
-+	uint8_t DP_SEC_GSP4_ENABLE;
-+	uint8_t DP_SEC_GSP5_ENABLE;
-+	uint8_t DP_SEC_GSP6_ENABLE;
-+	uint8_t DP_SEC_GSP7_ENABLE;
-+	uint8_t DP_SEC_AVI_ENABLE;
-+	uint8_t DP_SEC_MPG_ENABLE;
-+	uint8_t DP_VID_STREAM_DIS_DEFER;
-+	uint8_t DP_VID_STREAM_ENABLE;
-+	uint8_t DP_VID_STREAM_STATUS;
-+	uint8_t DP_STEER_FIFO_RESET;
-+	uint8_t DP_VID_M_N_GEN_EN;
-+	uint8_t DP_VID_N;
-+	uint8_t DP_VID_M;
-+	uint8_t DIG_START;
-+	uint8_t AFMT_AUDIO_SRC_SELECT;
-+	uint8_t AFMT_AUDIO_CHANNEL_ENABLE;
-+	uint8_t HDMI_AUDIO_PACKETS_PER_LINE;
-+	uint8_t HDMI_AUDIO_DELAY_EN;
-+	uint8_t AFMT_60958_CS_UPDATE;
-+	uint8_t AFMT_AUDIO_LAYOUT_OVRD;
-+	uint8_t AFMT_60958_OSF_OVRD;
-+	uint8_t HDMI_ACR_AUTO_SEND;
-+	uint8_t HDMI_ACR_SOURCE;
-+	uint8_t HDMI_ACR_AUDIO_PRIORITY;
-+	uint8_t HDMI_ACR_CTS_32;
-+	uint8_t HDMI_ACR_N_32;
-+	uint8_t HDMI_ACR_CTS_44;
-+	uint8_t HDMI_ACR_N_44;
-+	uint8_t HDMI_ACR_CTS_48;
-+	uint8_t HDMI_ACR_N_48;
-+	uint8_t AFMT_60958_CS_CHANNEL_NUMBER_L;
-+	uint8_t AFMT_60958_CS_CLOCK_ACCURACY;
-+	uint8_t AFMT_60958_CS_CHANNEL_NUMBER_R;
-+	uint8_t AFMT_60958_CS_CHANNEL_NUMBER_2;
-+	uint8_t AFMT_60958_CS_CHANNEL_NUMBER_3;
-+	uint8_t AFMT_60958_CS_CHANNEL_NUMBER_4;
-+	uint8_t AFMT_60958_CS_CHANNEL_NUMBER_5;
-+	uint8_t AFMT_60958_CS_CHANNEL_NUMBER_6;
-+	uint8_t AFMT_60958_CS_CHANNEL_NUMBER_7;
-+	uint8_t DP_SEC_AUD_N;
-+	uint8_t DP_SEC_TIMESTAMP_MODE;
-+	uint8_t DP_SEC_ASP_ENABLE;
-+	uint8_t DP_SEC_ATP_ENABLE;
-+	uint8_t DP_SEC_AIP_ENABLE;
-+	uint8_t DP_SEC_ACM_ENABLE;
-+	uint8_t AFMT_AUDIO_SAMPLE_SEND;
-+	uint8_t AFMT_AUDIO_CLOCK_EN;
-+	uint8_t TMDS_PIXEL_ENCODING;
-+	uint8_t TMDS_COLOR_FORMAT;
-+	uint8_t DIG_STEREOSYNC_SELECT;
-+	uint8_t DIG_STEREOSYNC_GATE_EN;
-+	uint8_t DP_DB_DISABLE;
-+	uint8_t DP_MSA_MISC0;
-+	uint8_t DP_MSA_HTOTAL;
-+	uint8_t DP_MSA_VTOTAL;
-+	uint8_t DP_MSA_HSTART;
-+	uint8_t DP_MSA_VSTART;
-+	uint8_t DP_MSA_HSYNCWIDTH;
-+	uint8_t DP_MSA_HSYNCPOLARITY;
-+	uint8_t DP_MSA_VSYNCWIDTH;
-+	uint8_t DP_MSA_VSYNCPOLARITY;
-+	uint8_t DP_MSA_HWIDTH;
-+	uint8_t DP_MSA_VHEIGHT;
-+	uint8_t HDMI_DB_DISABLE;
-+	uint8_t DP_VID_N_MUL;
-+	uint8_t DP_VID_M_DOUBLE_VALUE_EN;
-+};
-+
-+struct dce_stream_encoder_mask {
-+	uint32_t AFMT_GENERIC_INDEX;
-+	uint32_t AFMT_GENERIC0_UPDATE;
-+	uint32_t AFMT_GENERIC2_UPDATE;
-+	uint32_t AFMT_GENERIC_HB0;
-+	uint32_t AFMT_GENERIC_HB1;
-+	uint32_t AFMT_GENERIC_HB2;
-+	uint32_t AFMT_GENERIC_HB3;
-+	uint32_t AFMT_GENERIC_LOCK_STATUS;
-+	uint32_t AFMT_GENERIC_CONFLICT;
-+	uint32_t AFMT_GENERIC_CONFLICT_CLR;
-+	uint32_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
-+	uint32_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
-+	uint32_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
-+	uint32_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
-+	uint32_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
-+	uint32_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
-+	uint32_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
-+	uint32_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
-+	uint32_t AFMT_GENERIC0_FRAME_UPDATE;
-+	uint32_t AFMT_GENERIC1_FRAME_UPDATE;
-+	uint32_t AFMT_GENERIC2_FRAME_UPDATE;
-+	uint32_t AFMT_GENERIC3_FRAME_UPDATE;
-+	uint32_t AFMT_GENERIC4_FRAME_UPDATE;
-+	uint32_t AFMT_GENERIC5_FRAME_UPDATE;
-+	uint32_t AFMT_GENERIC6_FRAME_UPDATE;
-+	uint32_t AFMT_GENERIC7_FRAME_UPDATE;
-+	uint32_t HDMI_GENERIC0_CONT;
-+	uint32_t HDMI_GENERIC0_SEND;
-+	uint32_t HDMI_GENERIC0_LINE;
-+	uint32_t HDMI_GENERIC1_CONT;
-+	uint32_t HDMI_GENERIC1_SEND;
-+	uint32_t HDMI_GENERIC1_LINE;
-+	uint32_t DP_PIXEL_ENCODING;
-+	uint32_t DP_COMPONENT_DEPTH;
-+	uint32_t DP_DYN_RANGE;
-+	uint32_t DP_YCBCR_RANGE;
-+	uint32_t HDMI_PACKET_GEN_VERSION;
-+	uint32_t HDMI_KEEPOUT_MODE;
-+	uint32_t HDMI_DEEP_COLOR_ENABLE;
-+	uint32_t HDMI_CLOCK_CHANNEL_RATE;
-+	uint32_t HDMI_DEEP_COLOR_DEPTH;
-+	uint32_t HDMI_GC_CONT;
-+	uint32_t HDMI_GC_SEND;
-+	uint32_t HDMI_NULL_SEND;
-+	uint32_t HDMI_DATA_SCRAMBLE_EN;
-+	uint32_t HDMI_AUDIO_INFO_SEND;
-+	uint32_t AFMT_AUDIO_INFO_UPDATE;
-+	uint32_t HDMI_AUDIO_INFO_LINE;
-+	uint32_t HDMI_GC_AVMUTE;
-+	uint32_t DP_MSE_RATE_X;
-+	uint32_t DP_MSE_RATE_Y;
-+	uint32_t DP_MSE_RATE_UPDATE_PENDING;
-+	uint32_t AFMT_AVI_INFO_VERSION;
-+	uint32_t HDMI_AVI_INFO_SEND;
-+	uint32_t HDMI_AVI_INFO_CONT;
-+	uint32_t HDMI_AVI_INFO_LINE;
-+	uint32_t DP_SEC_GSP0_ENABLE;
-+	uint32_t DP_SEC_STREAM_ENABLE;
-+	uint32_t DP_SEC_GSP1_ENABLE;
-+	uint32_t DP_SEC_GSP2_ENABLE;
-+	uint32_t DP_SEC_GSP3_ENABLE;
-+	uint32_t DP_SEC_GSP4_ENABLE;
-+	uint32_t DP_SEC_GSP5_ENABLE;
-+	uint32_t DP_SEC_GSP6_ENABLE;
-+	uint32_t DP_SEC_GSP7_ENABLE;
-+	uint32_t DP_SEC_AVI_ENABLE;
-+	uint32_t DP_SEC_MPG_ENABLE;
-+	uint32_t DP_VID_STREAM_DIS_DEFER;
-+	uint32_t DP_VID_STREAM_ENABLE;
-+	uint32_t DP_VID_STREAM_STATUS;
-+	uint32_t DP_STEER_FIFO_RESET;
-+	uint32_t DP_VID_M_N_GEN_EN;
-+	uint32_t DP_VID_N;
-+	uint32_t DP_VID_M;
-+	uint32_t DIG_START;
-+	uint32_t AFMT_AUDIO_SRC_SELECT;
-+	uint32_t AFMT_AUDIO_CHANNEL_ENABLE;
-+	uint32_t HDMI_AUDIO_PACKETS_PER_LINE;
-+	uint32_t HDMI_AUDIO_DELAY_EN;
-+	uint32_t AFMT_60958_CS_UPDATE;
-+	uint32_t AFMT_AUDIO_LAYOUT_OVRD;
-+	uint32_t AFMT_60958_OSF_OVRD;
-+	uint32_t HDMI_ACR_AUTO_SEND;
-+	uint32_t HDMI_ACR_SOURCE;
-+	uint32_t HDMI_ACR_AUDIO_PRIORITY;
-+	uint32_t HDMI_ACR_CTS_32;
-+	uint32_t HDMI_ACR_N_32;
-+	uint32_t HDMI_ACR_CTS_44;
-+	uint32_t HDMI_ACR_N_44;
-+	uint32_t HDMI_ACR_CTS_48;
-+	uint32_t HDMI_ACR_N_48;
-+	uint32_t AFMT_60958_CS_CHANNEL_NUMBER_L;
-+	uint32_t AFMT_60958_CS_CLOCK_ACCURACY;
-+	uint32_t AFMT_60958_CS_CHANNEL_NUMBER_R;
-+	uint32_t AFMT_60958_CS_CHANNEL_NUMBER_2;
-+	uint32_t AFMT_60958_CS_CHANNEL_NUMBER_3;
-+	uint32_t AFMT_60958_CS_CHANNEL_NUMBER_4;
-+	uint32_t AFMT_60958_CS_CHANNEL_NUMBER_5;
-+	uint32_t AFMT_60958_CS_CHANNEL_NUMBER_6;
-+	uint32_t AFMT_60958_CS_CHANNEL_NUMBER_7;
-+	uint32_t DP_SEC_AUD_N;
-+	uint32_t DP_SEC_TIMESTAMP_MODE;
-+	uint32_t DP_SEC_ASP_ENABLE;
-+	uint32_t DP_SEC_ATP_ENABLE;
-+	uint32_t DP_SEC_AIP_ENABLE;
-+	uint32_t DP_SEC_ACM_ENABLE;
-+	uint32_t AFMT_AUDIO_SAMPLE_SEND;
-+	uint32_t AFMT_AUDIO_CLOCK_EN;
-+	uint32_t TMDS_PIXEL_ENCODING;
-+	uint32_t DIG_STEREOSYNC_SELECT;
-+	uint32_t DIG_STEREOSYNC_GATE_EN;
-+	uint32_t TMDS_COLOR_FORMAT;
-+	uint32_t DP_DB_DISABLE;
-+	uint32_t DP_MSA_MISC0;
-+	uint32_t DP_MSA_HTOTAL;
-+	uint32_t DP_MSA_VTOTAL;
-+	uint32_t DP_MSA_HSTART;
-+	uint32_t DP_MSA_VSTART;
-+	uint32_t DP_MSA_HSYNCWIDTH;
-+	uint32_t DP_MSA_HSYNCPOLARITY;
-+	uint32_t DP_MSA_VSYNCWIDTH;
-+	uint32_t DP_MSA_VSYNCPOLARITY;
-+	uint32_t DP_MSA_HWIDTH;
-+	uint32_t DP_MSA_VHEIGHT;
-+	uint32_t HDMI_DB_DISABLE;
-+	uint32_t DP_VID_N_MUL;
-+	uint32_t DP_VID_M_DOUBLE_VALUE_EN;
-+};
-+
-+struct dce110_stream_enc_registers {
-+	uint32_t AFMT_CNTL;
-+	uint32_t AFMT_AVI_INFO0;
-+	uint32_t AFMT_AVI_INFO1;
-+	uint32_t AFMT_AVI_INFO2;
-+	uint32_t AFMT_AVI_INFO3;
-+	uint32_t AFMT_GENERIC_0;
-+	uint32_t AFMT_GENERIC_1;
-+	uint32_t AFMT_GENERIC_2;
-+	uint32_t AFMT_GENERIC_3;
-+	uint32_t AFMT_GENERIC_4;
-+	uint32_t AFMT_GENERIC_5;
-+	uint32_t AFMT_GENERIC_6;
-+	uint32_t AFMT_GENERIC_7;
-+	uint32_t AFMT_GENERIC_HDR;
-+	uint32_t AFMT_INFOFRAME_CONTROL0;
-+	uint32_t AFMT_VBI_PACKET_CONTROL;
-+	uint32_t AFMT_VBI_PACKET_CONTROL1;
-+	uint32_t AFMT_AUDIO_PACKET_CONTROL;
-+	uint32_t AFMT_AUDIO_PACKET_CONTROL2;
-+	uint32_t AFMT_AUDIO_SRC_CONTROL;
-+	uint32_t AFMT_60958_0;
-+	uint32_t AFMT_60958_1;
-+	uint32_t AFMT_60958_2;
-+	uint32_t DIG_FE_CNTL;
-+	uint32_t DP_MSE_RATE_CNTL;
-+	uint32_t DP_MSE_RATE_UPDATE;
-+	uint32_t DP_PIXEL_FORMAT;
-+	uint32_t DP_SEC_CNTL;
-+	uint32_t DP_STEER_FIFO;
-+	uint32_t DP_VID_M;
-+	uint32_t DP_VID_N;
-+	uint32_t DP_VID_STREAM_CNTL;
-+	uint32_t DP_VID_TIMING;
-+	uint32_t DP_SEC_AUD_N;
-+	uint32_t DP_SEC_TIMESTAMP;
-+	uint32_t HDMI_CONTROL;
-+	uint32_t HDMI_GC;
-+	uint32_t HDMI_GENERIC_PACKET_CONTROL0;
-+	uint32_t HDMI_GENERIC_PACKET_CONTROL1;
-+	uint32_t HDMI_GENERIC_PACKET_CONTROL2;
-+	uint32_t HDMI_GENERIC_PACKET_CONTROL3;
-+	uint32_t HDMI_INFOFRAME_CONTROL0;
-+	uint32_t HDMI_INFOFRAME_CONTROL1;
-+	uint32_t HDMI_VBI_PACKET_CONTROL;
-+	uint32_t HDMI_AUDIO_PACKET_CONTROL;
-+	uint32_t HDMI_ACR_PACKET_CONTROL;
-+	uint32_t HDMI_ACR_32_0;
-+	uint32_t HDMI_ACR_32_1;
-+	uint32_t HDMI_ACR_44_0;
-+	uint32_t HDMI_ACR_44_1;
-+	uint32_t HDMI_ACR_48_0;
-+	uint32_t HDMI_ACR_48_1;
-+	uint32_t TMDS_CNTL;
-+	uint32_t DP_DB_CNTL;
-+	uint32_t DP_MSA_MISC;
-+	uint32_t DP_MSA_COLORIMETRY;
-+	uint32_t DP_MSA_TIMING_PARAM1;
-+	uint32_t DP_MSA_TIMING_PARAM2;
-+	uint32_t DP_MSA_TIMING_PARAM3;
-+	uint32_t DP_MSA_TIMING_PARAM4;
-+	uint32_t HDMI_DB_CONTROL;
-+};
-+
-+struct dce110_stream_encoder {
-+	struct stream_encoder base;
-+	const struct dce110_stream_enc_registers *regs;
-+	const struct dce_stream_encoder_shift *se_shift;
-+	const struct dce_stream_encoder_mask *se_mask;
-+};
-+
-+void dce110_stream_encoder_construct(
-+	struct dce110_stream_encoder *enc110,
-+	struct dc_context *ctx,
-+	struct dc_bios *bp,
-+	enum engine_id eng_id,
-+	const struct dce110_stream_enc_registers *regs,
-+	const struct dce_stream_encoder_shift *se_shift,
-+	const struct dce_stream_encoder_mask *se_mask);
-+
-+
-+void dce110_se_audio_mute_control(
-+	struct stream_encoder *enc, bool mute);
-+
-+void dce110_se_dp_audio_setup(
-+	struct stream_encoder *enc,
-+	unsigned int az_inst,
-+	struct audio_info *info);
-+
-+void dce110_se_dp_audio_enable(
-+		struct stream_encoder *enc);
-+
-+void dce110_se_dp_audio_disable(
-+		struct stream_encoder *enc);
-+
-+void dce110_se_hdmi_audio_setup(
-+	struct stream_encoder *enc,
-+	unsigned int az_inst,
-+	struct audio_info *info,
-+	struct audio_crtc_info *audio_crtc_info);
-+
-+void dce110_se_hdmi_audio_disable(
-+	struct stream_encoder *enc);
-+
-+#endif /* __DC_STREAM_ENCODER_DCE110_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c.0130~	2017-12-14 06:39:58.419903570 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c	2017-12-14 06:39:58.419903570 +0100
-@@ -0,0 +1,1411 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dce_transform.h"
-+#include "reg_helper.h"
-+#include "opp.h"
-+#include "basics/conversion.h"
-+#include "dc.h"
-+
-+#define REG(reg) \
-+	(xfm_dce->regs->reg)
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	xfm_dce->xfm_shift->field_name, xfm_dce->xfm_mask->field_name
-+
-+#define CTX \
-+	xfm_dce->base.ctx
-+
-+#define IDENTITY_RATIO(ratio) (dal_fixed31_32_u2d19(ratio) == (1 << 19))
-+#define GAMUT_MATRIX_SIZE 12
-+#define SCL_PHASES 16
-+
-+enum dcp_out_trunc_round_mode {
-+	DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
-+	DCP_OUT_TRUNC_ROUND_MODE_ROUND
-+};
-+
-+enum dcp_out_trunc_round_depth {
-+	DCP_OUT_TRUNC_ROUND_DEPTH_14BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_13BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_12BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_11BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_10BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_9BIT,
-+	DCP_OUT_TRUNC_ROUND_DEPTH_8BIT
-+};
-+
-+/*  defines the various methods of bit reduction available for use */
-+enum dcp_bit_depth_reduction_mode {
-+	DCP_BIT_DEPTH_REDUCTION_MODE_DITHER,
-+	DCP_BIT_DEPTH_REDUCTION_MODE_ROUND,
-+	DCP_BIT_DEPTH_REDUCTION_MODE_TRUNCATE,
-+	DCP_BIT_DEPTH_REDUCTION_MODE_DISABLED,
-+	DCP_BIT_DEPTH_REDUCTION_MODE_INVALID
-+};
-+
-+enum dcp_spatial_dither_mode {
-+	DCP_SPATIAL_DITHER_MODE_AAAA,
-+	DCP_SPATIAL_DITHER_MODE_A_AA_A,
-+	DCP_SPATIAL_DITHER_MODE_AABBAABB,
-+	DCP_SPATIAL_DITHER_MODE_AABBCCAABBCC,
-+	DCP_SPATIAL_DITHER_MODE_INVALID
-+};
-+
-+enum dcp_spatial_dither_depth {
-+	DCP_SPATIAL_DITHER_DEPTH_30BPP,
-+	DCP_SPATIAL_DITHER_DEPTH_24BPP
-+};
-+
-+enum csc_color_mode {
-+	/* 00 - BITS2:0 Bypass */
-+	CSC_COLOR_MODE_GRAPHICS_BYPASS,
-+	/* 01 - hard coded coefficient TV RGB */
-+	CSC_COLOR_MODE_GRAPHICS_PREDEFINED,
-+	/* 04 - programmable OUTPUT CSC coefficient */
-+	CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC,
-+};
-+
-+enum grph_color_adjust_option {
-+	GRPH_COLOR_MATRIX_HW_DEFAULT = 1,
-+	GRPH_COLOR_MATRIX_SW
-+};
-+
-+static const struct out_csc_color_matrix global_color_matrix[] = {
-+{ COLOR_SPACE_SRGB,
-+	{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
-+{ COLOR_SPACE_SRGB_LIMITED,
-+	{ 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
-+{ COLOR_SPACE_YCBCR601,
-+	{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
-+		0xF6B9, 0xE00, 0x1000} },
-+{ COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
-+	0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
-+/* TODO: correct values below */
-+{ COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
-+	0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
-+{ COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
-+	0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }
-+};
-+
-+static bool setup_scaling_configuration(
-+	struct dce_transform *xfm_dce,
-+	const struct scaler_data *data)
-+{
-+	REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0);
-+
-+	if (data->taps.h_taps + data->taps.v_taps <= 2) {
-+		/* Set bypass */
-+		if (xfm_dce->xfm_mask->SCL_PSCL_EN != 0)
-+			REG_UPDATE_2(SCL_MODE, SCL_MODE, 0, SCL_PSCL_EN, 0);
-+		else
-+			REG_UPDATE(SCL_MODE, SCL_MODE, 0);
-+		return false;
-+	}
-+
-+	REG_SET_2(SCL_TAP_CONTROL, 0,
-+			SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1,
-+			SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1);
-+
-+	if (data->format <= PIXEL_FORMAT_GRPH_END)
-+		REG_UPDATE(SCL_MODE, SCL_MODE, 1);
-+	else
-+		REG_UPDATE(SCL_MODE, SCL_MODE, 2);
-+
-+	if (xfm_dce->xfm_mask->SCL_PSCL_EN != 0)
-+		REG_UPDATE(SCL_MODE, SCL_PSCL_EN, 1);
-+
-+	/* 1 - Replace out of bound pixels with edge */
-+	REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1);
-+
-+	return true;
-+}
-+
-+static void program_overscan(
-+		struct dce_transform *xfm_dce,
-+		const struct scaler_data *data)
-+{
-+	int overscan_right = data->h_active
-+			- data->recout.x - data->recout.width;
-+	int overscan_bottom = data->v_active
-+			- data->recout.y - data->recout.height;
-+
-+	if (xfm_dce->base.ctx->dc->debug.surface_visual_confirm) {
-+		overscan_bottom += 2;
-+		overscan_right += 2;
-+	}
-+
-+	if (overscan_right < 0) {
-+		BREAK_TO_DEBUGGER();
-+		overscan_right = 0;
-+	}
-+	if (overscan_bottom < 0) {
-+		BREAK_TO_DEBUGGER();
-+		overscan_bottom = 0;
-+	}
-+
-+	REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0,
-+			EXT_OVERSCAN_LEFT, data->recout.x,
-+			EXT_OVERSCAN_RIGHT, overscan_right);
-+	REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0,
-+			EXT_OVERSCAN_TOP, data->recout.y,
-+			EXT_OVERSCAN_BOTTOM, overscan_bottom);
-+}
-+
-+static void program_multi_taps_filter(
-+	struct dce_transform *xfm_dce,
-+	int taps,
-+	const uint16_t *coeffs,
-+	enum ram_filter_type filter_type)
-+{
-+	int phase, pair;
-+	int array_idx = 0;
-+	int taps_pairs = (taps + 1) / 2;
-+	int phases_to_program = SCL_PHASES / 2 + 1;
-+
-+	uint32_t power_ctl = 0;
-+
-+	if (!coeffs)
-+		return;
-+
-+	/*We need to disable power gating on coeff memory to do programming*/
-+	if (REG(DCFE_MEM_PWR_CTRL)) {
-+		power_ctl = REG_READ(DCFE_MEM_PWR_CTRL);
-+		REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1);
-+
-+		REG_WAIT(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, 0, 1, 10);
-+	}
-+	for (phase = 0; phase < phases_to_program; phase++) {
-+		/*we always program N/2 + 1 phases, total phases N, but N/2-1 are just mirror
-+		phase 0 is unique and phase N/2 is unique if N is even*/
-+		for (pair = 0; pair < taps_pairs; pair++) {
-+			uint16_t odd_coeff = 0;
-+			uint16_t even_coeff = coeffs[array_idx];
-+
-+			REG_SET_3(SCL_COEF_RAM_SELECT, 0,
-+					SCL_C_RAM_FILTER_TYPE, filter_type,
-+					SCL_C_RAM_PHASE, phase,
-+					SCL_C_RAM_TAP_PAIR_IDX, pair);
-+
-+			if (taps % 2 && pair == taps_pairs - 1)
-+				array_idx++;
-+			else {
-+				odd_coeff = coeffs[array_idx + 1];
-+				array_idx += 2;
-+			}
-+
-+			REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
-+					SCL_C_RAM_EVEN_TAP_COEF_EN, 1,
-+					SCL_C_RAM_EVEN_TAP_COEF, even_coeff,
-+					SCL_C_RAM_ODD_TAP_COEF_EN, 1,
-+					SCL_C_RAM_ODD_TAP_COEF, odd_coeff);
-+		}
-+	}
-+
-+	/*We need to restore power gating on coeff memory to initial state*/
-+	if (REG(DCFE_MEM_PWR_CTRL))
-+		REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl);
-+}
-+
-+static void program_viewport(
-+	struct dce_transform *xfm_dce,
-+	const struct rect *view_port)
-+{
-+	REG_SET_2(VIEWPORT_START, 0,
-+			VIEWPORT_X_START, view_port->x,
-+			VIEWPORT_Y_START, view_port->y);
-+
-+	REG_SET_2(VIEWPORT_SIZE, 0,
-+			VIEWPORT_HEIGHT, view_port->height,
-+			VIEWPORT_WIDTH, view_port->width);
-+
-+	/* TODO: add stereo support */
-+}
-+
-+static void calculate_inits(
-+	struct dce_transform *xfm_dce,
-+	const struct scaler_data *data,
-+	struct scl_ratios_inits *inits)
-+{
-+	struct fixed31_32 h_init;
-+	struct fixed31_32 v_init;
-+
-+	inits->h_int_scale_ratio =
-+		dal_fixed31_32_u2d19(data->ratios.horz) << 5;
-+	inits->v_int_scale_ratio =
-+		dal_fixed31_32_u2d19(data->ratios.vert) << 5;
-+
-+	h_init =
-+		dal_fixed31_32_div_int(
-+			dal_fixed31_32_add(
-+				data->ratios.horz,
-+				dal_fixed31_32_from_int(data->taps.h_taps + 1)),
-+				2);
-+	inits->h_init.integer = dal_fixed31_32_floor(h_init);
-+	inits->h_init.fraction = dal_fixed31_32_u0d19(h_init) << 5;
-+
-+	v_init =
-+		dal_fixed31_32_div_int(
-+			dal_fixed31_32_add(
-+				data->ratios.vert,
-+				dal_fixed31_32_from_int(data->taps.v_taps + 1)),
-+				2);
-+	inits->v_init.integer = dal_fixed31_32_floor(v_init);
-+	inits->v_init.fraction = dal_fixed31_32_u0d19(v_init) << 5;
-+}
-+
-+static void program_scl_ratios_inits(
-+	struct dce_transform *xfm_dce,
-+	struct scl_ratios_inits *inits)
-+{
-+
-+	REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
-+			SCL_H_SCALE_RATIO, inits->h_int_scale_ratio);
-+
-+	REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
-+			SCL_V_SCALE_RATIO, inits->v_int_scale_ratio);
-+
-+	REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
-+			SCL_H_INIT_INT, inits->h_init.integer,
-+			SCL_H_INIT_FRAC, inits->h_init.fraction);
-+
-+	REG_SET_2(SCL_VERT_FILTER_INIT, 0,
-+			SCL_V_INIT_INT, inits->v_init.integer,
-+			SCL_V_INIT_FRAC, inits->v_init.fraction);
-+
-+	REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
-+}
-+
-+static const uint16_t *get_filter_coeffs_16p(int taps, struct fixed31_32 ratio)
-+{
-+	if (taps == 4)
-+		return get_filter_4tap_16p(ratio);
-+	else if (taps == 3)
-+		return get_filter_3tap_16p(ratio);
-+	else if (taps == 2)
-+		return get_filter_2tap_16p();
-+	else if (taps == 1)
-+		return NULL;
-+	else {
-+		/* should never happen, bug */
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+}
-+
-+static void dce_transform_set_scaler(
-+	struct transform *xfm,
-+	const struct scaler_data *data)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+	bool is_scaling_required;
-+	bool filter_updated = false;
-+	const uint16_t *coeffs_v, *coeffs_h;
-+
-+	/*Use all three pieces of memory always*/
-+	REG_SET_2(LB_MEMORY_CTRL, 0,
-+			LB_MEMORY_CONFIG, 0,
-+			LB_MEMORY_SIZE, xfm_dce->lb_memory_size);
-+
-+	/* Clear SCL_F_SHARP_CONTROL value to 0 */
-+	REG_WRITE(SCL_F_SHARP_CONTROL, 0);
-+
-+	/* 1. Program overscan */
-+	program_overscan(xfm_dce, data);
-+
-+	/* 2. Program taps and configuration */
-+	is_scaling_required = setup_scaling_configuration(xfm_dce, data);
-+
-+	if (is_scaling_required) {
-+		/* 3. Calculate and program ratio, filter initialization */
-+		struct scl_ratios_inits inits = { 0 };
-+
-+		calculate_inits(xfm_dce, data, &inits);
-+
-+		program_scl_ratios_inits(xfm_dce, &inits);
-+
-+		coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert);
-+		coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz);
-+
-+		if (coeffs_v != xfm_dce->filter_v || coeffs_h != xfm_dce->filter_h) {
-+			/* 4. Program vertical filters */
-+			if (xfm_dce->filter_v == NULL)
-+				REG_SET(SCL_VERT_FILTER_CONTROL, 0,
-+						SCL_V_2TAP_HARDCODE_COEF_EN, 0);
-+			program_multi_taps_filter(
-+					xfm_dce,
-+					data->taps.v_taps,
-+					coeffs_v,
-+					FILTER_TYPE_RGB_Y_VERTICAL);
-+			program_multi_taps_filter(
-+					xfm_dce,
-+					data->taps.v_taps,
-+					coeffs_v,
-+					FILTER_TYPE_ALPHA_VERTICAL);
-+
-+			/* 5. Program horizontal filters */
-+			if (xfm_dce->filter_h == NULL)
-+				REG_SET(SCL_HORZ_FILTER_CONTROL, 0,
-+						SCL_H_2TAP_HARDCODE_COEF_EN, 0);
-+			program_multi_taps_filter(
-+					xfm_dce,
-+					data->taps.h_taps,
-+					coeffs_h,
-+					FILTER_TYPE_RGB_Y_HORIZONTAL);
-+			program_multi_taps_filter(
-+					xfm_dce,
-+					data->taps.h_taps,
-+					coeffs_h,
-+					FILTER_TYPE_ALPHA_HORIZONTAL);
-+
-+			xfm_dce->filter_v = coeffs_v;
-+			xfm_dce->filter_h = coeffs_h;
-+			filter_updated = true;
-+		}
-+	}
-+
-+	/* 6. Program the viewport */
-+	program_viewport(xfm_dce, &data->viewport);
-+
-+	/* 7. Set bit to flip to new coefficient memory */
-+	if (filter_updated)
-+		REG_UPDATE(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, 1);
-+
-+	REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en);
-+}
-+
-+/*****************************************************************************
-+ * set_clamp
-+ *
-+ * @param depth : bit depth to set the clamp to (should match denorm)
-+ *
-+ * @brief
-+ *     Programs clamp according to panel bit depth.
-+ *
-+ *******************************************************************************/
-+static void set_clamp(
-+	struct dce_transform *xfm_dce,
-+	enum dc_color_depth depth)
-+{
-+	int clamp_max = 0;
-+
-+	/* At the clamp block the data will be MSB aligned, so we set the max
-+	 * clamp accordingly.
-+	 * For example, the max value for 6 bits MSB aligned (14 bit bus) would
-+	 * be "11 1111 0000 0000" in binary, so 0x3F00.
-+	 */
-+	switch (depth) {
-+	case COLOR_DEPTH_666:
-+		/* 6bit MSB aligned on 14 bit bus '11 1111 0000 0000' */
-+		clamp_max = 0x3F00;
-+		break;
-+	case COLOR_DEPTH_888:
-+		/* 8bit MSB aligned on 14 bit bus '11 1111 1100 0000' */
-+		clamp_max = 0x3FC0;
-+		break;
-+	case COLOR_DEPTH_101010:
-+		/* 10bit MSB aligned on 14 bit bus '11 1111 1111 1100' */
-+		clamp_max = 0x3FFC;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		/* 12bit MSB aligned on 14 bit bus '11 1111 1111 1111' */
-+		clamp_max = 0x3FFF;
-+		break;
-+	default:
-+		clamp_max = 0x3FC0;
-+		BREAK_TO_DEBUGGER(); /* Invalid clamp bit depth */
-+	}
-+	REG_SET_2(OUT_CLAMP_CONTROL_B_CB, 0,
-+			OUT_CLAMP_MIN_B_CB, 0,
-+			OUT_CLAMP_MAX_B_CB, clamp_max);
-+
-+	REG_SET_2(OUT_CLAMP_CONTROL_G_Y, 0,
-+			OUT_CLAMP_MIN_G_Y, 0,
-+			OUT_CLAMP_MAX_G_Y, clamp_max);
-+
-+	REG_SET_2(OUT_CLAMP_CONTROL_R_CR, 0,
-+			OUT_CLAMP_MIN_R_CR, 0,
-+			OUT_CLAMP_MAX_R_CR, clamp_max);
-+}
-+
-+/*******************************************************************************
-+ * set_round
-+ *
-+ * @brief
-+ *     Programs Round/Truncate
-+ *
-+ * @param [in] mode  :round or truncate
-+ * @param [in] depth :bit depth to round/truncate to
-+ OUT_ROUND_TRUNC_MODE 3:0 0xA Output data round or truncate mode
-+ POSSIBLE VALUES:
-+      00 - truncate to u0.12
-+      01 - truncate to u0.11
-+      02 - truncate to u0.10
-+      03 - truncate to u0.9
-+      04 - truncate to u0.8
-+      05 - reserved
-+      06 - truncate to u0.14
-+      07 - truncate to u0.13		set_reg_field_value(
-+			value,
-+			clamp_max,
-+			OUT_CLAMP_CONTROL_R_CR,
-+			OUT_CLAMP_MAX_R_CR);
-+      08 - round to u0.12
-+      09 - round to u0.11
-+      10 - round to u0.10
-+      11 - round to u0.9
-+      12 - round to u0.8
-+      13 - reserved
-+      14 - round to u0.14
-+      15 - round to u0.13
-+
-+ ******************************************************************************/
-+static void set_round(
-+	struct dce_transform *xfm_dce,
-+	enum dcp_out_trunc_round_mode mode,
-+	enum dcp_out_trunc_round_depth depth)
-+{
-+	int depth_bits = 0;
-+	int mode_bit = 0;
-+
-+	/*  set up bit depth */
-+	switch (depth) {
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_14BIT:
-+		depth_bits = 6;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_13BIT:
-+		depth_bits = 7;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_12BIT:
-+		depth_bits = 0;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_11BIT:
-+		depth_bits = 1;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_10BIT:
-+		depth_bits = 2;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_9BIT:
-+		depth_bits = 3;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_DEPTH_8BIT:
-+		depth_bits = 4;
-+		break;
-+	default:
-+		depth_bits = 4;
-+		BREAK_TO_DEBUGGER(); /* Invalid dcp_out_trunc_round_depth */
-+	}
-+
-+	/*  set up round or truncate */
-+	switch (mode) {
-+	case DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE:
-+		mode_bit = 0;
-+		break;
-+	case DCP_OUT_TRUNC_ROUND_MODE_ROUND:
-+		mode_bit = 1;
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER(); /* Invalid dcp_out_trunc_round_mode */
-+	}
-+
-+	depth_bits |= mode_bit << 3;
-+
-+	REG_SET(OUT_ROUND_CONTROL, 0, OUT_ROUND_TRUNC_MODE, depth_bits);
-+}
-+
-+/*****************************************************************************
-+ * set_dither
-+ *
-+ * @brief
-+ *     Programs Dither
-+ *
-+ * @param [in] dither_enable        : enable dither
-+ * @param [in] dither_mode           : dither mode to set
-+ * @param [in] dither_depth          : bit depth to dither to
-+ * @param [in] frame_random_enable    : enable frame random
-+ * @param [in] rgb_random_enable      : enable rgb random
-+ * @param [in] highpass_random_enable : enable highpass random
-+ *
-+ ******************************************************************************/
-+
-+static void set_dither(
-+	struct dce_transform *xfm_dce,
-+	bool dither_enable,
-+	enum dcp_spatial_dither_mode dither_mode,
-+	enum dcp_spatial_dither_depth dither_depth,
-+	bool frame_random_enable,
-+	bool rgb_random_enable,
-+	bool highpass_random_enable)
-+{
-+	int dither_depth_bits = 0;
-+	int dither_mode_bits = 0;
-+
-+	switch (dither_mode) {
-+	case DCP_SPATIAL_DITHER_MODE_AAAA:
-+		dither_mode_bits = 0;
-+		break;
-+	case DCP_SPATIAL_DITHER_MODE_A_AA_A:
-+		dither_mode_bits = 1;
-+		break;
-+	case DCP_SPATIAL_DITHER_MODE_AABBAABB:
-+		dither_mode_bits = 2;
-+		break;
-+	case DCP_SPATIAL_DITHER_MODE_AABBCCAABBCC:
-+		dither_mode_bits = 3;
-+		break;
-+	default:
-+		/* Invalid dcp_spatial_dither_mode */
-+		BREAK_TO_DEBUGGER();
-+	}
-+
-+	switch (dither_depth) {
-+	case DCP_SPATIAL_DITHER_DEPTH_30BPP:
-+		dither_depth_bits = 0;
-+		break;
-+	case DCP_SPATIAL_DITHER_DEPTH_24BPP:
-+		dither_depth_bits = 1;
-+		break;
-+	default:
-+		/* Invalid dcp_spatial_dither_depth */
-+		BREAK_TO_DEBUGGER();
-+	}
-+
-+	/*  write the register */
-+	REG_SET_6(DCP_SPATIAL_DITHER_CNTL, 0,
-+			DCP_SPATIAL_DITHER_EN, dither_enable,
-+			DCP_SPATIAL_DITHER_MODE, dither_mode_bits,
-+			DCP_SPATIAL_DITHER_DEPTH, dither_depth_bits,
-+			DCP_FRAME_RANDOM_ENABLE, frame_random_enable,
-+			DCP_RGB_RANDOM_ENABLE, rgb_random_enable,
-+			DCP_HIGHPASS_RANDOM_ENABLE, highpass_random_enable);
-+}
-+
-+/*****************************************************************************
-+ * dce_transform_bit_depth_reduction_program
-+ *
-+ * @brief
-+ *     Programs the DCP bit depth reduction registers (Clamp, Round/Truncate,
-+ *      Dither) for dce
-+ *
-+ * @param depth : bit depth to set the clamp to (should match denorm)
-+ *
-+ ******************************************************************************/
-+static void program_bit_depth_reduction(
-+	struct dce_transform *xfm_dce,
-+	enum dc_color_depth depth,
-+	const struct bit_depth_reduction_params *bit_depth_params)
-+{
-+	enum dcp_bit_depth_reduction_mode depth_reduction_mode;
-+	enum dcp_spatial_dither_mode spatial_dither_mode;
-+	bool frame_random_enable;
-+	bool rgb_random_enable;
-+	bool highpass_random_enable;
-+
-+	ASSERT(depth < COLOR_DEPTH_121212); /* Invalid clamp bit depth */
-+
-+	if (bit_depth_params->flags.SPATIAL_DITHER_ENABLED) {
-+		depth_reduction_mode = DCP_BIT_DEPTH_REDUCTION_MODE_DITHER;
-+		frame_random_enable = true;
-+		rgb_random_enable = true;
-+		highpass_random_enable = true;
-+
-+	} else {
-+		depth_reduction_mode = DCP_BIT_DEPTH_REDUCTION_MODE_DISABLED;
-+		frame_random_enable = false;
-+		rgb_random_enable = false;
-+		highpass_random_enable = false;
-+	}
-+
-+	spatial_dither_mode = DCP_SPATIAL_DITHER_MODE_A_AA_A;
-+
-+	set_clamp(xfm_dce, depth);
-+
-+	switch (depth_reduction_mode) {
-+	case DCP_BIT_DEPTH_REDUCTION_MODE_DITHER:
-+		/*  Spatial Dither: Set round/truncate to bypass (12bit),
-+		 *  enable Dither (30bpp) */
-+		set_round(xfm_dce,
-+			DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
-+			DCP_OUT_TRUNC_ROUND_DEPTH_12BIT);
-+
-+		set_dither(xfm_dce, true, spatial_dither_mode,
-+			DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
-+			rgb_random_enable, highpass_random_enable);
-+		break;
-+	case DCP_BIT_DEPTH_REDUCTION_MODE_ROUND:
-+		/*  Round: Enable round (10bit), disable Dither */
-+		set_round(xfm_dce,
-+			DCP_OUT_TRUNC_ROUND_MODE_ROUND,
-+			DCP_OUT_TRUNC_ROUND_DEPTH_10BIT);
-+
-+		set_dither(xfm_dce, false, spatial_dither_mode,
-+			DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
-+			rgb_random_enable, highpass_random_enable);
-+		break;
-+	case DCP_BIT_DEPTH_REDUCTION_MODE_TRUNCATE: /*  Truncate */
-+		/*  Truncate: Enable truncate (10bit), disable Dither */
-+		set_round(xfm_dce,
-+			DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
-+			DCP_OUT_TRUNC_ROUND_DEPTH_10BIT);
-+
-+		set_dither(xfm_dce, false, spatial_dither_mode,
-+			DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
-+			rgb_random_enable, highpass_random_enable);
-+		break;
-+
-+	case DCP_BIT_DEPTH_REDUCTION_MODE_DISABLED: /*  Disabled */
-+		/*  Truncate: Set round/truncate to bypass (12bit),
-+		 * disable Dither */
-+		set_round(xfm_dce,
-+			DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE,
-+			DCP_OUT_TRUNC_ROUND_DEPTH_12BIT);
-+
-+		set_dither(xfm_dce, false, spatial_dither_mode,
-+			DCP_SPATIAL_DITHER_DEPTH_30BPP, frame_random_enable,
-+			rgb_random_enable, highpass_random_enable);
-+		break;
-+	default:
-+		/* Invalid DCP Depth reduction mode */
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+}
-+
-+static int dce_transform_get_max_num_of_supported_lines(
-+	struct dce_transform *xfm_dce,
-+	enum lb_pixel_depth depth,
-+	int pixel_width)
-+{
-+	int pixels_per_entries = 0;
-+	int max_pixels_supports = 0;
-+
-+	ASSERT(pixel_width);
-+
-+	/* Find number of pixels that can fit into a single LB entry and
-+	 * take floor of the value since we cannot store a single pixel
-+	 * across multiple entries. */
-+	switch (depth) {
-+	case LB_PIXEL_DEPTH_18BPP:
-+		pixels_per_entries = xfm_dce->lb_bits_per_entry / 18;
-+		break;
-+
-+	case LB_PIXEL_DEPTH_24BPP:
-+		pixels_per_entries = xfm_dce->lb_bits_per_entry / 24;
-+		break;
-+
-+	case LB_PIXEL_DEPTH_30BPP:
-+		pixels_per_entries = xfm_dce->lb_bits_per_entry / 30;
-+		break;
-+
-+	case LB_PIXEL_DEPTH_36BPP:
-+		pixels_per_entries = xfm_dce->lb_bits_per_entry / 36;
-+		break;
-+
-+	default:
-+		dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING,
-+			"%s: Invalid LB pixel depth",
-+			__func__);
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+
-+	ASSERT(pixels_per_entries);
-+
-+	max_pixels_supports =
-+			pixels_per_entries *
-+			xfm_dce->lb_memory_size;
-+
-+	return (max_pixels_supports / pixel_width);
-+}
-+
-+static void set_denormalization(
-+	struct dce_transform *xfm_dce,
-+	enum dc_color_depth depth)
-+{
-+	int denorm_mode = 0;
-+
-+	switch (depth) {
-+	case COLOR_DEPTH_666:
-+		/* 63/64 for 6 bit output color depth */
-+		denorm_mode = 1;
-+		break;
-+	case COLOR_DEPTH_888:
-+		/* Unity for 8 bit output color depth
-+		 * because prescale is disabled by default */
-+		denorm_mode = 0;
-+		break;
-+	case COLOR_DEPTH_101010:
-+		/* 1023/1024 for 10 bit output color depth */
-+		denorm_mode = 3;
-+		break;
-+	case COLOR_DEPTH_121212:
-+		/* 4095/4096 for 12 bit output color depth */
-+		denorm_mode = 5;
-+		break;
-+	case COLOR_DEPTH_141414:
-+	case COLOR_DEPTH_161616:
-+	default:
-+		/* not valid used case! */
-+		break;
-+	}
-+
-+	REG_SET(DENORM_CONTROL, 0, DENORM_MODE, denorm_mode);
-+}
-+
-+static void dce_transform_set_pixel_storage_depth(
-+	struct transform *xfm,
-+	enum lb_pixel_depth depth,
-+	const struct bit_depth_reduction_params *bit_depth_params)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+	int pixel_depth, expan_mode;
-+	enum dc_color_depth color_depth;
-+
-+	switch (depth) {
-+	case LB_PIXEL_DEPTH_18BPP:
-+		color_depth = COLOR_DEPTH_666;
-+		pixel_depth = 2;
-+		expan_mode  = 1;
-+		break;
-+	case LB_PIXEL_DEPTH_24BPP:
-+		color_depth = COLOR_DEPTH_888;
-+		pixel_depth = 1;
-+		expan_mode  = 1;
-+		break;
-+	case LB_PIXEL_DEPTH_30BPP:
-+		color_depth = COLOR_DEPTH_101010;
-+		pixel_depth = 0;
-+		expan_mode  = 1;
-+		break;
-+	case LB_PIXEL_DEPTH_36BPP:
-+		color_depth = COLOR_DEPTH_121212;
-+		pixel_depth = 3;
-+		expan_mode  = 0;
-+		break;
-+	default:
-+		color_depth = COLOR_DEPTH_101010;
-+		pixel_depth = 0;
-+		expan_mode  = 1;
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+
-+	set_denormalization(xfm_dce, color_depth);
-+	program_bit_depth_reduction(xfm_dce, color_depth, bit_depth_params);
-+
-+	REG_UPDATE_2(LB_DATA_FORMAT,
-+			PIXEL_DEPTH, pixel_depth,
-+			PIXEL_EXPAN_MODE, expan_mode);
-+
-+	if (!(xfm_dce->lb_pixel_depth_supported & depth)) {
-+		/*we should use unsupported capabilities
-+		 *  unless it is required by w/a*/
-+		dm_logger_write(xfm->ctx->logger, LOG_WARNING,
-+			"%s: Capability not supported",
-+			__func__);
-+	}
-+}
-+
-+static void program_gamut_remap(
-+	struct dce_transform *xfm_dce,
-+	const uint16_t *reg_val)
-+{
-+	if (reg_val) {
-+		REG_SET_2(GAMUT_REMAP_C11_C12, 0,
-+				GAMUT_REMAP_C11, reg_val[0],
-+				GAMUT_REMAP_C12, reg_val[1]);
-+		REG_SET_2(GAMUT_REMAP_C13_C14, 0,
-+				GAMUT_REMAP_C13, reg_val[2],
-+				GAMUT_REMAP_C14, reg_val[3]);
-+		REG_SET_2(GAMUT_REMAP_C21_C22, 0,
-+				GAMUT_REMAP_C21, reg_val[4],
-+				GAMUT_REMAP_C22, reg_val[5]);
-+		REG_SET_2(GAMUT_REMAP_C23_C24, 0,
-+				GAMUT_REMAP_C23, reg_val[6],
-+				GAMUT_REMAP_C24, reg_val[7]);
-+		REG_SET_2(GAMUT_REMAP_C31_C32, 0,
-+				GAMUT_REMAP_C31, reg_val[8],
-+				GAMUT_REMAP_C32, reg_val[9]);
-+		REG_SET_2(GAMUT_REMAP_C33_C34, 0,
-+				GAMUT_REMAP_C33, reg_val[10],
-+				GAMUT_REMAP_C34, reg_val[11]);
-+
-+		REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 1);
-+	} else
-+		REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 0);
-+
-+}
-+
-+/**
-+ *****************************************************************************
-+ *  Function: dal_transform_wide_gamut_set_gamut_remap
-+ *
-+ *  @param [in] const struct xfm_grph_csc_adjustment *adjust
-+ *
-+ *  @return
-+ *     void
-+ *
-+ *  @note calculate and apply color temperature adjustment to in Rgb color space
-+ *
-+ *  @see
-+ *
-+ *****************************************************************************
-+ */
-+static void dce_transform_set_gamut_remap(
-+	struct transform *xfm,
-+	const struct xfm_grph_csc_adjustment *adjust)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+
-+	if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
-+		/* Bypass if type is bypass or hw */
-+		program_gamut_remap(xfm_dce, NULL);
-+	else {
-+		struct fixed31_32 arr_matrix[GAMUT_MATRIX_SIZE];
-+		uint16_t arr_reg_val[GAMUT_MATRIX_SIZE];
-+
-+		arr_matrix[0] = adjust->temperature_matrix[0];
-+		arr_matrix[1] = adjust->temperature_matrix[1];
-+		arr_matrix[2] = adjust->temperature_matrix[2];
-+		arr_matrix[3] = dal_fixed31_32_zero;
-+
-+		arr_matrix[4] = adjust->temperature_matrix[3];
-+		arr_matrix[5] = adjust->temperature_matrix[4];
-+		arr_matrix[6] = adjust->temperature_matrix[5];
-+		arr_matrix[7] = dal_fixed31_32_zero;
-+
-+		arr_matrix[8] = adjust->temperature_matrix[6];
-+		arr_matrix[9] = adjust->temperature_matrix[7];
-+		arr_matrix[10] = adjust->temperature_matrix[8];
-+		arr_matrix[11] = dal_fixed31_32_zero;
-+
-+		convert_float_matrix(
-+			arr_reg_val, arr_matrix, GAMUT_MATRIX_SIZE);
-+
-+		program_gamut_remap(xfm_dce, arr_reg_val);
-+	}
-+}
-+
-+static uint32_t decide_taps(struct fixed31_32 ratio, uint32_t in_taps, bool chroma)
-+{
-+	uint32_t taps;
-+
-+	if (IDENTITY_RATIO(ratio)) {
-+		return 1;
-+	} else if (in_taps != 0) {
-+		taps = in_taps;
-+	} else {
-+		taps = 4;
-+	}
-+
-+	if (chroma) {
-+		taps /= 2;
-+		if (taps < 2)
-+			taps = 2;
-+	}
-+
-+	return taps;
-+}
-+
-+
-+bool dce_transform_get_optimal_number_of_taps(
-+	struct transform *xfm,
-+	struct scaler_data *scl_data,
-+	const struct scaling_taps *in_taps)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+	int pixel_width = scl_data->viewport.width;
-+	int max_num_of_lines;
-+
-+	if (xfm_dce->prescaler_on &&
-+			(scl_data->viewport.width > scl_data->recout.width))
-+		pixel_width = scl_data->recout.width;
-+
-+	max_num_of_lines = dce_transform_get_max_num_of_supported_lines(
-+		xfm_dce,
-+		scl_data->lb_params.depth,
-+		pixel_width);
-+
-+	/* Fail if in_taps are impossible */
-+	if (in_taps->v_taps >= max_num_of_lines)
-+		return false;
-+
-+	/*
-+	 * Set taps according to this policy (in this order)
-+	 * - Use 1 for no scaling
-+	 * - Use input taps
-+	 * - Use 4 and reduce as required by line buffer size
-+	 * - Decide chroma taps if chroma is scaled
-+	 *
-+	 * Ignore input chroma taps. Decide based on non-chroma
-+	 */
-+	scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false);
-+	scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false);
-+	scl_data->taps.h_taps_c = decide_taps(scl_data->ratios.horz_c, in_taps->h_taps, true);
-+	scl_data->taps.v_taps_c = decide_taps(scl_data->ratios.vert_c, in_taps->v_taps, true);
-+
-+	if (!IDENTITY_RATIO(scl_data->ratios.vert)) {
-+		/* reduce v_taps if needed but ensure we have at least two */
-+		if (in_taps->v_taps == 0
-+				&& max_num_of_lines <= scl_data->taps.v_taps
-+				&& scl_data->taps.v_taps > 1) {
-+			scl_data->taps.v_taps = max_num_of_lines - 1;
-+		}
-+
-+		if (scl_data->taps.v_taps <= 1)
-+			return false;
-+	}
-+
-+	if (!IDENTITY_RATIO(scl_data->ratios.vert_c)) {
-+		/* reduce chroma v_taps if needed but ensure we have at least two */
-+		if (max_num_of_lines <= scl_data->taps.v_taps_c && scl_data->taps.v_taps_c > 1) {
-+			scl_data->taps.v_taps_c = max_num_of_lines - 1;
-+		}
-+
-+		if (scl_data->taps.v_taps_c <= 1)
-+			return false;
-+	}
-+
-+	/* we've got valid taps */
-+	return true;
-+}
-+
-+static void dce_transform_reset(struct transform *xfm)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+
-+	xfm_dce->filter_h = NULL;
-+	xfm_dce->filter_v = NULL;
-+}
-+
-+static void program_color_matrix(
-+	struct dce_transform *xfm_dce,
-+	const struct out_csc_color_matrix *tbl_entry,
-+	enum grph_color_adjust_option options)
-+{
-+	{
-+		REG_SET_2(OUTPUT_CSC_C11_C12, 0,
-+			OUTPUT_CSC_C11, tbl_entry->regval[0],
-+			OUTPUT_CSC_C12, tbl_entry->regval[1]);
-+	}
-+	{
-+		REG_SET_2(OUTPUT_CSC_C13_C14, 0,
-+			OUTPUT_CSC_C11, tbl_entry->regval[2],
-+			OUTPUT_CSC_C12, tbl_entry->regval[3]);
-+	}
-+	{
-+		REG_SET_2(OUTPUT_CSC_C21_C22, 0,
-+			OUTPUT_CSC_C11, tbl_entry->regval[4],
-+			OUTPUT_CSC_C12, tbl_entry->regval[5]);
-+	}
-+	{
-+		REG_SET_2(OUTPUT_CSC_C23_C24, 0,
-+			OUTPUT_CSC_C11, tbl_entry->regval[6],
-+			OUTPUT_CSC_C12, tbl_entry->regval[7]);
-+	}
-+	{
-+		REG_SET_2(OUTPUT_CSC_C31_C32, 0,
-+			OUTPUT_CSC_C11, tbl_entry->regval[8],
-+			OUTPUT_CSC_C12, tbl_entry->regval[9]);
-+	}
-+	{
-+		REG_SET_2(OUTPUT_CSC_C33_C34, 0,
-+			OUTPUT_CSC_C11, tbl_entry->regval[10],
-+			OUTPUT_CSC_C12, tbl_entry->regval[11]);
-+	}
-+}
-+
-+static bool configure_graphics_mode(
-+	struct dce_transform *xfm_dce,
-+	enum csc_color_mode config,
-+	enum graphics_csc_adjust_type csc_adjust_type,
-+	enum dc_color_space color_space)
-+{
-+	REG_SET(OUTPUT_CSC_CONTROL, 0,
-+		OUTPUT_CSC_GRPH_MODE, 0);
-+
-+	if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) {
-+		if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC) {
-+			REG_SET(OUTPUT_CSC_CONTROL, 0,
-+				OUTPUT_CSC_GRPH_MODE, 4);
-+		} else {
-+
-+			switch (color_space) {
-+			case COLOR_SPACE_SRGB:
-+				/* by pass */
-+				REG_SET(OUTPUT_CSC_CONTROL, 0,
-+					OUTPUT_CSC_GRPH_MODE, 0);
-+				break;
-+			case COLOR_SPACE_SRGB_LIMITED:
-+				/* TV RGB */
-+				REG_SET(OUTPUT_CSC_CONTROL, 0,
-+					OUTPUT_CSC_GRPH_MODE, 1);
-+				break;
-+			case COLOR_SPACE_YCBCR601:
-+			case COLOR_SPACE_YCBCR601_LIMITED:
-+				/* YCbCr601 */
-+				REG_SET(OUTPUT_CSC_CONTROL, 0,
-+					OUTPUT_CSC_GRPH_MODE, 2);
-+				break;
-+			case COLOR_SPACE_YCBCR709:
-+			case COLOR_SPACE_YCBCR709_LIMITED:
-+				/* YCbCr709 */
-+				REG_SET(OUTPUT_CSC_CONTROL, 0,
-+					OUTPUT_CSC_GRPH_MODE, 3);
-+				break;
-+			default:
-+				return false;
-+			}
-+		}
-+	} else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) {
-+		switch (color_space) {
-+		case COLOR_SPACE_SRGB:
-+			/* by pass */
-+			REG_SET(OUTPUT_CSC_CONTROL, 0,
-+				OUTPUT_CSC_GRPH_MODE, 0);
-+			break;
-+			break;
-+		case COLOR_SPACE_SRGB_LIMITED:
-+			/* TV RGB */
-+			REG_SET(OUTPUT_CSC_CONTROL, 0,
-+				OUTPUT_CSC_GRPH_MODE, 1);
-+			break;
-+		case COLOR_SPACE_YCBCR601:
-+		case COLOR_SPACE_YCBCR601_LIMITED:
-+			/* YCbCr601 */
-+			REG_SET(OUTPUT_CSC_CONTROL, 0,
-+				OUTPUT_CSC_GRPH_MODE, 2);
-+			break;
-+		case COLOR_SPACE_YCBCR709:
-+		case COLOR_SPACE_YCBCR709_LIMITED:
-+			 /* YCbCr709 */
-+			REG_SET(OUTPUT_CSC_CONTROL, 0,
-+				OUTPUT_CSC_GRPH_MODE, 3);
-+			break;
-+		default:
-+			return false;
-+		}
-+
-+	} else
-+		/* by pass */
-+		REG_SET(OUTPUT_CSC_CONTROL, 0,
-+			OUTPUT_CSC_GRPH_MODE, 0);
-+
-+	return true;
-+}
-+
-+void dce110_opp_set_csc_adjustment(
-+	struct transform *xfm,
-+	const struct out_csc_color_matrix *tbl_entry)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+	enum csc_color_mode config =
-+			CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
-+
-+	program_color_matrix(
-+			xfm_dce, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW);
-+
-+	/*  We did everything ,now program DxOUTPUT_CSC_CONTROL */
-+	configure_graphics_mode(xfm_dce, config, GRAPHICS_CSC_ADJUST_TYPE_SW,
-+			tbl_entry->color_space);
-+}
-+
-+void dce110_opp_set_csc_default(
-+	struct transform *xfm,
-+	const struct default_adjustment *default_adjust)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+	enum csc_color_mode config =
-+			CSC_COLOR_MODE_GRAPHICS_PREDEFINED;
-+
-+	if (default_adjust->force_hw_default == false) {
-+		const struct out_csc_color_matrix *elm;
-+		/* currently parameter not in use */
-+		enum grph_color_adjust_option option =
-+			GRPH_COLOR_MATRIX_HW_DEFAULT;
-+		uint32_t i;
-+		/*
-+		 * HW default false we program locally defined matrix
-+		 * HW default true  we use predefined hw matrix and we
-+		 * do not need to program matrix
-+		 * OEM wants the HW default via runtime parameter.
-+		 */
-+		option = GRPH_COLOR_MATRIX_SW;
-+
-+		for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {
-+			elm = &global_color_matrix[i];
-+			if (elm->color_space != default_adjust->out_color_space)
-+				continue;
-+			/* program the matrix with default values from this
-+			 * file */
-+			program_color_matrix(xfm_dce, elm, option);
-+			config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
-+			break;
-+		}
-+	}
-+
-+	/* configure the what we programmed :
-+	 * 1. Default values from this file
-+	 * 2. Use hardware default from ROM_A and we do not need to program
-+	 * matrix */
-+
-+	configure_graphics_mode(xfm_dce, config,
-+		default_adjust->csc_adjust_type,
-+		default_adjust->out_color_space);
-+}
-+
-+static void program_pwl(struct dce_transform *xfm_dce,
-+			const struct pwl_params *params)
-+{
-+	int retval;
-+	uint8_t max_tries = 10;
-+	uint8_t counter = 0;
-+	uint32_t i = 0;
-+	const struct pwl_result_data *rgb = params->rgb_resulted;
-+
-+	/* Power on LUT memory */
-+	if (REG(DCFE_MEM_PWR_CTRL))
-+		REG_UPDATE(DCFE_MEM_PWR_CTRL,
-+			   DCP_REGAMMA_MEM_PWR_DIS, 1);
-+	else
-+		REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
-+			   REGAMMA_LUT_LIGHT_SLEEP_DIS, 1);
-+
-+	while (counter < max_tries) {
-+		if (REG(DCFE_MEM_PWR_STATUS)) {
-+			REG_GET(DCFE_MEM_PWR_STATUS,
-+				DCP_REGAMMA_MEM_PWR_STATE,
-+				&retval);
-+
-+			if (retval == 0)
-+				break;
-+			++counter;
-+		} else {
-+			REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,
-+				REGAMMA_LUT_MEM_PWR_STATE,
-+				&retval);
-+
-+			if (retval == 0)
-+				break;
-+			++counter;
-+		}
-+	}
-+
-+	if (counter == max_tries) {
-+		dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING,
-+				"%s: regamma lut was not powered on "
-+				"in a timely manner,"
-+				" programming still proceeds\n",
-+				__func__);
-+	}
-+
-+	REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK,
-+		   REGAMMA_LUT_WRITE_EN_MASK, 7);
-+
-+	REG_WRITE(REGAMMA_LUT_INDEX, 0);
-+
-+	/* Program REGAMMA_LUT_DATA */
-+	while (i != params->hw_points_num) {
-+
-+		REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg);
-+		REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg);
-+		REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg);
-+		REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg);
-+		REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg);
-+		REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg);
-+
-+		++rgb;
-+		++i;
-+	}
-+
-+	/*  we are done with DCP LUT memory; re-enable low power mode */
-+	if (REG(DCFE_MEM_PWR_CTRL))
-+		REG_UPDATE(DCFE_MEM_PWR_CTRL,
-+			   DCP_REGAMMA_MEM_PWR_DIS, 0);
-+	else
-+		REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,
-+			   REGAMMA_LUT_LIGHT_SLEEP_DIS, 0);
-+}
-+
-+static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce,
-+						const struct pwl_params *params)
-+{
-+	const struct gamma_curve *curve;
-+
-+	REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0,
-+		  REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x,
-+		  REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0);
-+
-+	REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0,
-+		REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope);
-+
-+	REG_SET(REGAMMA_CNTLA_END_CNTL1, 0,
-+		REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x);
-+
-+	REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0,
-+		  REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y,
-+		  REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[1].custom_float_slope);
-+
-+	curve = params->arr_curve_points;
-+
-+	REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0,
-+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-+	curve += 2;
-+
-+	REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0,
-+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-+	curve += 2;
-+
-+	REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0,
-+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-+	curve += 2;
-+
-+	REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0,
-+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-+	curve += 2;
-+
-+	REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0,
-+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-+	curve += 2;
-+
-+	REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0,
-+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-+	curve += 2;
-+
-+	REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0,
-+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-+	curve += 2;
-+
-+	REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0,
-+		  REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
-+		  REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
-+		  REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
-+		  REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
-+}
-+
-+
-+
-+void dce110_opp_program_regamma_pwl(struct transform *xfm,
-+				    const struct pwl_params *params)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+
-+	/* Setup regions */
-+	regamma_config_regions_and_segments(xfm_dce, params);
-+
-+	/* Program PWL */
-+	program_pwl(xfm_dce, params);
-+}
-+
-+void dce110_opp_power_on_regamma_lut(struct transform *xfm,
-+				     bool power_on)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+
-+	if (REG(DCFE_MEM_PWR_CTRL))
-+		REG_UPDATE_2(DCFE_MEM_PWR_CTRL,
-+			     DCP_REGAMMA_MEM_PWR_DIS, power_on,
-+			     DCP_LUT_MEM_PWR_DIS, power_on);
-+	else
-+		REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL,
-+			    REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on,
-+			    DCP_LUT_LIGHT_SLEEP_DIS, power_on);
-+
-+}
-+
-+void dce110_opp_set_regamma_mode(struct transform *xfm,
-+				 enum opp_regamma mode)
-+{
-+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
-+
-+	REG_SET(REGAMMA_CONTROL, 0,
-+		GRPH_REGAMMA_MODE, mode);
-+}
-+
-+static const struct transform_funcs dce_transform_funcs = {
-+	.transform_reset = dce_transform_reset,
-+	.transform_set_scaler = dce_transform_set_scaler,
-+	.transform_set_gamut_remap = dce_transform_set_gamut_remap,
-+	.opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
-+	.opp_set_csc_default = dce110_opp_set_csc_default,
-+	.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
-+	.opp_program_regamma_pwl = dce110_opp_program_regamma_pwl,
-+	.opp_set_regamma_mode = dce110_opp_set_regamma_mode,
-+	.transform_set_pixel_storage_depth = dce_transform_set_pixel_storage_depth,
-+	.transform_get_optimal_number_of_taps = dce_transform_get_optimal_number_of_taps
-+};
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+void dce_transform_construct(
-+	struct dce_transform *xfm_dce,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce_transform_registers *regs,
-+	const struct dce_transform_shift *xfm_shift,
-+	const struct dce_transform_mask *xfm_mask)
-+{
-+	xfm_dce->base.ctx = ctx;
-+
-+	xfm_dce->base.inst = inst;
-+	xfm_dce->base.funcs = &dce_transform_funcs;
-+
-+	xfm_dce->regs = regs;
-+	xfm_dce->xfm_shift = xfm_shift;
-+	xfm_dce->xfm_mask = xfm_mask;
-+
-+	xfm_dce->prescaler_on = true;
-+	xfm_dce->lb_pixel_depth_supported =
-+			LB_PIXEL_DEPTH_18BPP |
-+			LB_PIXEL_DEPTH_24BPP |
-+			LB_PIXEL_DEPTH_30BPP;
-+
-+	xfm_dce->lb_bits_per_entry = LB_BITS_PER_ENTRY;
-+	xfm_dce->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x6B0*/
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h.0130~	2017-12-14 06:39:58.419903570 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h	2017-12-14 06:39:58.419903570 +0100
-@@ -0,0 +1,516 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef _DCE_DCE_TRANSFORM_H_
-+#define _DCE_DCE_TRANSFORM_H_
-+
-+
-+#include "transform.h"
-+
-+#define TO_DCE_TRANSFORM(transform)\
-+	container_of(transform, struct dce_transform, base)
-+
-+#define LB_TOTAL_NUMBER_OF_ENTRIES 1712
-+#define LB_BITS_PER_ENTRY 144
-+
-+#define XFM_COMMON_REG_LIST_DCE_BASE(id) \
-+	SRI(LB_DATA_FORMAT, LB, id), \
-+	SRI(GAMUT_REMAP_CONTROL, DCP, id), \
-+	SRI(GAMUT_REMAP_C11_C12, DCP, id), \
-+	SRI(GAMUT_REMAP_C13_C14, DCP, id), \
-+	SRI(GAMUT_REMAP_C21_C22, DCP, id), \
-+	SRI(GAMUT_REMAP_C23_C24, DCP, id), \
-+	SRI(GAMUT_REMAP_C31_C32, DCP, id), \
-+	SRI(GAMUT_REMAP_C33_C34, DCP, id), \
-+	SRI(OUTPUT_CSC_C11_C12, DCP, id), \
-+	SRI(OUTPUT_CSC_C13_C14, DCP, id), \
-+	SRI(OUTPUT_CSC_C21_C22, DCP, id), \
-+	SRI(OUTPUT_CSC_C23_C24, DCP, id), \
-+	SRI(OUTPUT_CSC_C31_C32, DCP, id), \
-+	SRI(OUTPUT_CSC_C33_C34, DCP, id), \
-+	SRI(OUTPUT_CSC_CONTROL, DCP, id), \
-+	SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \
-+	SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \
-+	SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \
-+	SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \
-+	SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \
-+	SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \
-+	SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \
-+	SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \
-+	SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \
-+	SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \
-+	SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \
-+	SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \
-+	SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \
-+	SRI(REGAMMA_LUT_INDEX, DCP, id), \
-+	SRI(REGAMMA_LUT_DATA, DCP, id), \
-+	SRI(REGAMMA_CONTROL, DCP, id), \
-+	SRI(DENORM_CONTROL, DCP, id), \
-+	SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
-+	SRI(OUT_ROUND_CONTROL, DCP, id), \
-+	SRI(OUT_CLAMP_CONTROL_R_CR, DCP, id), \
-+	SRI(OUT_CLAMP_CONTROL_G_Y, DCP, id), \
-+	SRI(OUT_CLAMP_CONTROL_B_CB, DCP, id), \
-+	SRI(SCL_MODE, SCL, id), \
-+	SRI(SCL_TAP_CONTROL, SCL, id), \
-+	SRI(SCL_CONTROL, SCL, id), \
-+	SRI(SCL_BYPASS_CONTROL, SCL, id), \
-+	SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
-+	SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
-+	SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
-+	SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
-+	SRI(SCL_COEF_RAM_SELECT, SCL, id), \
-+	SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
-+	SRI(VIEWPORT_START, SCL, id), \
-+	SRI(VIEWPORT_SIZE, SCL, id), \
-+	SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
-+	SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
-+	SRI(SCL_HORZ_FILTER_INIT, SCL, id), \
-+	SRI(SCL_VERT_FILTER_INIT, SCL, id), \
-+	SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
-+	SRI(LB_MEMORY_CTRL, LB, id), \
-+	SRI(SCL_UPDATE, SCL, id), \
-+	SRI(SCL_F_SHARP_CONTROL, SCL, id)
-+
-+#define XFM_COMMON_REG_LIST_DCE80(id) \
-+	XFM_COMMON_REG_LIST_DCE_BASE(id), \
-+	SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
-+
-+#define XFM_COMMON_REG_LIST_DCE100(id) \
-+	XFM_COMMON_REG_LIST_DCE_BASE(id), \
-+	SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
-+	SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
-+
-+#define XFM_COMMON_REG_LIST_DCE110(id) \
-+	XFM_COMMON_REG_LIST_DCE_BASE(id), \
-+	SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
-+	SRI(DCFE_MEM_PWR_STATUS, DCFE, id)
-+
-+#define XFM_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+#define XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
-+	XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \
-+	XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \
-+	XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \
-+	XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \
-+	XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \
-+	XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \
-+	XFM_SF(OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \
-+	XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \
-+	XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \
-+	XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \
-+	XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \
-+	XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \
-+	XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \
-+	XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
-+	XFM_SF(LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \
-+	XFM_SF(LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \
-+	XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \
-+	XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \
-+	XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \
-+	XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \
-+	XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \
-+	XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \
-+	XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \
-+	XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \
-+	XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \
-+	XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \
-+	XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
-+	XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
-+	XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
-+	XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
-+	XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
-+	XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
-+	XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
-+	XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
-+	XFM_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
-+	XFM_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
-+	XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
-+	XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
-+	XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
-+	XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
-+	XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
-+	XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
-+	XFM_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
-+	XFM_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
-+	XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \
-+	XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
-+	XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
-+	XFM_SF(SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \
-+	XFM_SF(SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \
-+	XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \
-+	XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \
-+	XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \
-+	XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \
-+	XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
-+	XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
-+	XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
-+	XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \
-+	XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \
-+	XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \
-+	XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \
-+	XFM_SF(VIEWPORT_START, VIEWPORT_X_START, mask_sh), \
-+	XFM_SF(VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \
-+	XFM_SF(VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \
-+	XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \
-+	XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \
-+	XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \
-+	XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \
-+	XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \
-+	XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \
-+	XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \
-+	XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \
-+	XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \
-+	XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \
-+	XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \
-+	XFM_SF(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \
-+	XFM_SF(LB_DATA_FORMAT, ALPHA_EN, mask_sh)
-+
-+#define XFM_COMMON_MASK_SH_LIST_DCE80(mask_sh) \
-+	XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
-+	OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\
-+	OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\
-+	OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh)
-+
-+#define XFM_COMMON_MASK_SH_LIST_DCE110(mask_sh) \
-+	XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
-+	XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
-+	XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
-+	XFM_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
-+	XFM_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
-+	XFM_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
-+	XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
-+
-+#define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
-+	XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \
-+	XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \
-+	XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \
-+	XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \
-+	XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \
-+	XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \
-+	XFM_SF(DCP0_OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \
-+	XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \
-+	XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \
-+	XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \
-+	XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \
-+	XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \
-+	XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \
-+	XFM_SF(DCP0_DENORM_CONTROL, DENORM_MODE, mask_sh), \
-+	XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \
-+	XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \
-+	XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \
-+	XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \
-+	XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \
-+	XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \
-+	XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \
-+	XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \
-+	XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \
-+	XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \
-+	XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \
-+	XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \
-+	XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
-+	XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
-+	XFM_SF(DCP0_GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
-+	XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
-+	XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
-+	XFM_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
-+	XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
-+	XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
-+	XFM_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
-+	XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
-+	XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
-+	XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
-+	XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
-+	XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
-+	XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
-+	XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
-+	XFM_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
-+	XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \
-+	XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
-+	XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
-+	XFM_SF(SCL0_SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \
-+	XFM_SF(SCL0_SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \
-+	XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \
-+	XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \
-+	XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \
-+	XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \
-+	XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
-+	XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
-+	XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
-+	XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \
-+	XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \
-+	XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \
-+	XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \
-+	XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_X_START, mask_sh), \
-+	XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \
-+	XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \
-+	XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \
-+	XFM_SF(SCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \
-+	XFM_SF(SCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \
-+	XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \
-+	XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \
-+	XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \
-+	XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \
-+	XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \
-+	XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \
-+	XFM_SF(SCL0_SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \
-+	XFM_SF(SCL0_SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \
-+	XFM_SF(SCL0_SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \
-+	XFM_SF(LB0_LB_DATA_FORMAT, ALPHA_EN, mask_sh), \
-+	XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
-+	XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
-+	XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
-+	XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
-+	XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh)
-+
-+#define XFM_REG_FIELD_LIST(type) \
-+	type OUT_CLAMP_MIN_B_CB; \
-+	type OUT_CLAMP_MAX_B_CB; \
-+	type OUT_CLAMP_MIN_G_Y; \
-+	type OUT_CLAMP_MAX_G_Y; \
-+	type OUT_CLAMP_MIN_R_CR; \
-+	type OUT_CLAMP_MAX_R_CR; \
-+	type OUT_ROUND_TRUNC_MODE; \
-+	type DCP_SPATIAL_DITHER_EN; \
-+	type DCP_SPATIAL_DITHER_MODE; \
-+	type DCP_SPATIAL_DITHER_DEPTH; \
-+	type DCP_FRAME_RANDOM_ENABLE; \
-+	type DCP_RGB_RANDOM_ENABLE; \
-+	type DCP_HIGHPASS_RANDOM_ENABLE; \
-+	type DENORM_MODE; \
-+	type PIXEL_DEPTH; \
-+	type PIXEL_EXPAN_MODE; \
-+	type GAMUT_REMAP_C11; \
-+	type GAMUT_REMAP_C12; \
-+	type GAMUT_REMAP_C13; \
-+	type GAMUT_REMAP_C14; \
-+	type GAMUT_REMAP_C21; \
-+	type GAMUT_REMAP_C22; \
-+	type GAMUT_REMAP_C23; \
-+	type GAMUT_REMAP_C24; \
-+	type GAMUT_REMAP_C31; \
-+	type GAMUT_REMAP_C32; \
-+	type GAMUT_REMAP_C33; \
-+	type GAMUT_REMAP_C34; \
-+	type GRPH_GAMUT_REMAP_MODE; \
-+	type OUTPUT_CSC_C11; \
-+	type OUTPUT_CSC_C12; \
-+	type OUTPUT_CSC_GRPH_MODE; \
-+	type DCP_REGAMMA_MEM_PWR_DIS; \
-+	type DCP_LUT_MEM_PWR_DIS; \
-+	type REGAMMA_LUT_LIGHT_SLEEP_DIS; \
-+	type DCP_LUT_LIGHT_SLEEP_DIS; \
-+	type REGAMMA_CNTLA_EXP_REGION_START; \
-+	type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \
-+	type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \
-+	type REGAMMA_CNTLA_EXP_REGION_END; \
-+	type REGAMMA_CNTLA_EXP_REGION_END_BASE; \
-+	type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \
-+	type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \
-+	type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \
-+	type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \
-+	type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \
-+	type DCP_REGAMMA_MEM_PWR_STATE; \
-+	type REGAMMA_LUT_MEM_PWR_STATE; \
-+	type REGAMMA_LUT_WRITE_EN_MASK; \
-+	type GRPH_REGAMMA_MODE; \
-+	type SCL_MODE; \
-+	type SCL_BYPASS_MODE; \
-+	type SCL_PSCL_EN; \
-+	type SCL_H_NUM_OF_TAPS; \
-+	type SCL_V_NUM_OF_TAPS; \
-+	type SCL_BOUNDARY_MODE; \
-+	type EXT_OVERSCAN_LEFT; \
-+	type EXT_OVERSCAN_RIGHT; \
-+	type EXT_OVERSCAN_TOP; \
-+	type EXT_OVERSCAN_BOTTOM; \
-+	type SCL_COEFF_MEM_PWR_DIS; \
-+	type SCL_COEFF_MEM_PWR_STATE; \
-+	type SCL_C_RAM_FILTER_TYPE; \
-+	type SCL_C_RAM_PHASE; \
-+	type SCL_C_RAM_TAP_PAIR_IDX; \
-+	type SCL_C_RAM_EVEN_TAP_COEF_EN; \
-+	type SCL_C_RAM_EVEN_TAP_COEF; \
-+	type SCL_C_RAM_ODD_TAP_COEF_EN; \
-+	type SCL_C_RAM_ODD_TAP_COEF; \
-+	type VIEWPORT_X_START; \
-+	type VIEWPORT_Y_START; \
-+	type VIEWPORT_HEIGHT; \
-+	type VIEWPORT_WIDTH; \
-+	type SCL_H_SCALE_RATIO; \
-+	type SCL_V_SCALE_RATIO; \
-+	type SCL_H_INIT_INT; \
-+	type SCL_H_INIT_FRAC; \
-+	type SCL_V_INIT_INT; \
-+	type SCL_V_INIT_FRAC; \
-+	type LB_MEMORY_CONFIG; \
-+	type LB_MEMORY_SIZE; \
-+	type SCL_V_2TAP_HARDCODE_COEF_EN; \
-+	type SCL_H_2TAP_HARDCODE_COEF_EN; \
-+	type SCL_COEF_UPDATE_COMPLETE; \
-+	type ALPHA_EN
-+
-+struct dce_transform_shift {
-+	XFM_REG_FIELD_LIST(uint8_t);
-+};
-+
-+struct dce_transform_mask {
-+	XFM_REG_FIELD_LIST(uint32_t);
-+};
-+
-+struct dce_transform_registers {
-+	uint32_t LB_DATA_FORMAT;
-+	uint32_t GAMUT_REMAP_CONTROL;
-+	uint32_t GAMUT_REMAP_C11_C12;
-+	uint32_t GAMUT_REMAP_C13_C14;
-+	uint32_t GAMUT_REMAP_C21_C22;
-+	uint32_t GAMUT_REMAP_C23_C24;
-+	uint32_t GAMUT_REMAP_C31_C32;
-+	uint32_t GAMUT_REMAP_C33_C34;
-+	uint32_t OUTPUT_CSC_C11_C12;
-+	uint32_t OUTPUT_CSC_C13_C14;
-+	uint32_t OUTPUT_CSC_C21_C22;
-+	uint32_t OUTPUT_CSC_C23_C24;
-+	uint32_t OUTPUT_CSC_C31_C32;
-+	uint32_t OUTPUT_CSC_C33_C34;
-+	uint32_t OUTPUT_CSC_CONTROL;
-+	uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL;
-+	uint32_t REGAMMA_CNTLA_START_CNTL;
-+	uint32_t REGAMMA_CNTLA_SLOPE_CNTL;
-+	uint32_t REGAMMA_CNTLA_END_CNTL1;
-+	uint32_t REGAMMA_CNTLA_END_CNTL2;
-+	uint32_t REGAMMA_CNTLA_REGION_0_1;
-+	uint32_t REGAMMA_CNTLA_REGION_2_3;
-+	uint32_t REGAMMA_CNTLA_REGION_4_5;
-+	uint32_t REGAMMA_CNTLA_REGION_6_7;
-+	uint32_t REGAMMA_CNTLA_REGION_8_9;
-+	uint32_t REGAMMA_CNTLA_REGION_10_11;
-+	uint32_t REGAMMA_CNTLA_REGION_12_13;
-+	uint32_t REGAMMA_CNTLA_REGION_14_15;
-+	uint32_t REGAMMA_LUT_WRITE_EN_MASK;
-+	uint32_t REGAMMA_LUT_INDEX;
-+	uint32_t REGAMMA_LUT_DATA;
-+	uint32_t REGAMMA_CONTROL;
-+	uint32_t DENORM_CONTROL;
-+	uint32_t DCP_SPATIAL_DITHER_CNTL;
-+	uint32_t OUT_ROUND_CONTROL;
-+	uint32_t OUT_CLAMP_CONTROL_R_CR;
-+	uint32_t OUT_CLAMP_CONTROL_G_Y;
-+	uint32_t OUT_CLAMP_CONTROL_B_CB;
-+	uint32_t SCL_MODE;
-+	uint32_t SCL_TAP_CONTROL;
-+	uint32_t SCL_CONTROL;
-+	uint32_t SCL_BYPASS_CONTROL;
-+	uint32_t EXT_OVERSCAN_LEFT_RIGHT;
-+	uint32_t EXT_OVERSCAN_TOP_BOTTOM;
-+	uint32_t SCL_VERT_FILTER_CONTROL;
-+	uint32_t SCL_HORZ_FILTER_CONTROL;
-+	uint32_t DCFE_MEM_PWR_CTRL;
-+	uint32_t DCFE_MEM_PWR_STATUS;
-+	uint32_t SCL_COEF_RAM_SELECT;
-+	uint32_t SCL_COEF_RAM_TAP_DATA;
-+	uint32_t VIEWPORT_START;
-+	uint32_t VIEWPORT_SIZE;
-+	uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
-+	uint32_t SCL_VERT_FILTER_SCALE_RATIO;
-+	uint32_t SCL_HORZ_FILTER_INIT;
-+	uint32_t SCL_VERT_FILTER_INIT;
-+	uint32_t SCL_AUTOMATIC_MODE_CONTROL;
-+	uint32_t LB_MEMORY_CTRL;
-+	uint32_t SCL_UPDATE;
-+	uint32_t SCL_F_SHARP_CONTROL;
-+};
-+
-+struct init_int_and_frac {
-+	uint32_t integer;
-+	uint32_t fraction;
-+};
-+
-+struct scl_ratios_inits {
-+	uint32_t h_int_scale_ratio;
-+	uint32_t v_int_scale_ratio;
-+	struct init_int_and_frac h_init;
-+	struct init_int_and_frac v_init;
-+};
-+
-+enum ram_filter_type {
-+	FILTER_TYPE_RGB_Y_VERTICAL	= 0, /* 0 - RGB/Y Vertical filter */
-+	FILTER_TYPE_CBCR_VERTICAL	= 1, /* 1 - CbCr  Vertical filter */
-+	FILTER_TYPE_RGB_Y_HORIZONTAL	= 2, /* 1 - RGB/Y Horizontal filter */
-+	FILTER_TYPE_CBCR_HORIZONTAL	= 3, /* 3 - CbCr  Horizontal filter */
-+	FILTER_TYPE_ALPHA_VERTICAL	= 4, /* 4 - Alpha Vertical filter. */
-+	FILTER_TYPE_ALPHA_HORIZONTAL	= 5, /* 5 - Alpha Horizontal filter. */
-+};
-+
-+struct dce_transform {
-+	struct transform base;
-+	const struct dce_transform_registers *regs;
-+	const struct dce_transform_shift *xfm_shift;
-+	const struct dce_transform_mask *xfm_mask;
-+
-+	const uint16_t *filter_v;
-+	const uint16_t *filter_h;
-+	const uint16_t *filter_v_c;
-+	const uint16_t *filter_h_c;
-+	int lb_pixel_depth_supported;
-+	int lb_memory_size;
-+	int lb_bits_per_entry;
-+	bool prescaler_on;
-+};
-+
-+void dce_transform_construct(struct dce_transform *xfm_dce,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dce_transform_registers *regs,
-+	const struct dce_transform_shift *xfm_shift,
-+	const struct dce_transform_mask *xfm_mask);
-+
-+bool dce_transform_get_optimal_number_of_taps(
-+	struct transform *xfm,
-+	struct scaler_data *scl_data,
-+	const struct scaling_taps *in_taps);
-+
-+void dce110_opp_set_csc_adjustment(
-+	struct transform *xfm,
-+	const struct out_csc_color_matrix *tbl_entry);
-+
-+void dce110_opp_set_csc_default(
-+	struct transform *xfm,
-+	const struct default_adjustment *default_adjust);
-+
-+/* REGAMMA RELATED */
-+void dce110_opp_power_on_regamma_lut(
-+	struct transform *xfm,
-+	bool power_on);
-+
-+void dce110_opp_program_regamma_pwl(
-+	struct transform *xfm,
-+	const struct pwl_params *params);
-+
-+void dce110_opp_set_regamma_mode(struct transform *xfm,
-+		enum opp_regamma mode);
-+
-+#endif /* _DCE_DCE_TRANSFORM_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dce/Makefile.0130~	2017-12-14 06:39:58.419903570 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dce/Makefile	2017-12-14 06:39:58.419903570 +0100
-@@ -0,0 +1,15 @@
-+#
-+# Makefile for common 'dce' logic
-+# HW object file under this folder follow similar pattern for HW programming
-+#   - register offset and/or shift + mask stored in the dec_hw struct
-+#   - register programming through common macros that look up register 
-+#     offset/shift/mask stored in dce_hw struct
-+
-+DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \
-+dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \
-+dce_clocks.o dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o
-+
-+
-+AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_DCE)
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dc.h.0130~	2017-12-14 06:39:58.419903570 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dc.h	2017-12-14 06:39:58.419903570 +0100
-@@ -0,0 +1,704 @@
-+/*
-+ * Copyright 2012-14 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef DC_INTERFACE_H_
-+#define DC_INTERFACE_H_
-+
-+#include "dc_types.h"
-+#include "grph_object_defs.h"
-+#include "logger_types.h"
-+#include "gpio_types.h"
-+#include "link_service_types.h"
-+#include "grph_object_ctrl_defs.h"
-+#include <inc/hw/opp.h>
-+
-+#include "inc/hw_sequencer.h"
-+#include "inc/compressor.h"
-+#include "dml/display_mode_lib.h"
-+
-+#define DC_VER "3.1.16"
-+
-+#define MAX_SURFACES 3
-+#define MAX_STREAMS 6
-+#define MAX_SINKS_PER_LINK 4
-+
-+
-+/*******************************************************************************
-+ * Display Core Interfaces
-+ ******************************************************************************/
-+struct dc_caps {
-+	uint32_t max_streams;
-+	uint32_t max_links;
-+	uint32_t max_audios;
-+	uint32_t max_slave_planes;
-+	uint32_t max_planes;
-+	uint32_t max_downscale_ratio;
-+	uint32_t i2c_speed_in_khz;
-+	unsigned int max_cursor_size;
-+	unsigned int max_video_width;
-+	int linear_pitch_alignment;
-+	bool dcc_const_color;
-+	bool dynamic_audio;
-+	bool is_apu;
-+};
-+
-+struct dc_dcc_surface_param {
-+	struct dc_size surface_size;
-+	enum surface_pixel_format format;
-+	enum swizzle_mode_values swizzle_mode;
-+	enum dc_scan_direction scan;
-+};
-+
-+struct dc_dcc_setting {
-+	unsigned int max_compressed_blk_size;
-+	unsigned int max_uncompressed_blk_size;
-+	bool independent_64b_blks;
-+};
-+
-+struct dc_surface_dcc_cap {
-+	union {
-+		struct {
-+			struct dc_dcc_setting rgb;
-+		} grph;
-+
-+		struct {
-+			struct dc_dcc_setting luma;
-+			struct dc_dcc_setting chroma;
-+		} video;
-+	};
-+
-+	bool capable;
-+	bool const_color_support;
-+};
-+
-+struct dc_static_screen_events {
-+	bool cursor_update;
-+	bool surface_update;
-+	bool overlay_update;
-+};
-+
-+
-+/* Surface update type is used by dc_update_surfaces_and_stream
-+ * The update type is determined at the very beginning of the function based
-+ * on parameters passed in and decides how much programming (or updating) is
-+ * going to be done during the call.
-+ *
-+ * UPDATE_TYPE_FAST is used for really fast updates that do not require much
-+ * logical calculations or hardware register programming. This update MUST be
-+ * ISR safe on windows. Currently fast update will only be used to flip surface
-+ * address.
-+ *
-+ * UPDATE_TYPE_MED is used for slower updates which require significant hw
-+ * re-programming however do not affect bandwidth consumption or clock
-+ * requirements. At present, this is the level at which front end updates
-+ * that do not require us to run bw_calcs happen. These are in/out transfer func
-+ * updates, viewport offset changes, recout size changes and pixel depth changes.
-+ * This update can be done at ISR, but we want to minimize how often this happens.
-+ *
-+ * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
-+ * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
-+ * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
-+ * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
-+ * a full update. This cannot be done at ISR level and should be a rare event.
-+ * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
-+ * underscan we don't expect to see this call at all.
-+ */
-+
-+enum surface_update_type {
-+	UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
-+	UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
-+	UPDATE_TYPE_FULL, /* may need to shuffle resources */
-+};
-+
-+/* Forward declaration*/
-+struct dc;
-+struct dc_plane_state;
-+struct dc_state;
-+
-+
-+struct dc_cap_funcs {
-+	bool (*get_dcc_compression_cap)(const struct dc *dc,
-+			const struct dc_dcc_surface_param *input,
-+			struct dc_surface_dcc_cap *output);
-+};
-+
-+struct link_training_settings;
-+
-+struct dc_link_funcs {
-+	void (*set_drive_settings)(struct dc *dc,
-+			struct link_training_settings *lt_settings,
-+			const struct dc_link *link);
-+	void (*perform_link_training)(struct dc *dc,
-+			struct dc_link_settings *link_setting,
-+			bool skip_video_pattern);
-+	void (*set_preferred_link_settings)(struct dc *dc,
-+			struct dc_link_settings *link_setting,
-+			struct dc_link *link);
-+	void (*enable_hpd)(const struct dc_link *link);
-+	void (*disable_hpd)(const struct dc_link *link);
-+	void (*set_test_pattern)(
-+			struct dc_link *link,
-+			enum dp_test_pattern test_pattern,
-+			const struct link_training_settings *p_link_settings,
-+			const unsigned char *p_custom_pattern,
-+			unsigned int cust_pattern_size);
-+};
-+
-+/* Structure to hold configuration flags set by dm at dc creation. */
-+struct dc_config {
-+	bool gpu_vm_support;
-+	bool disable_disp_pll_sharing;
-+};
-+
-+enum dcc_option {
-+	DCC_ENABLE = 0,
-+	DCC_DISABLE = 1,
-+	DCC_HALF_REQ_DISALBE = 2,
-+};
-+
-+enum pipe_split_policy {
-+	MPC_SPLIT_DYNAMIC = 0,
-+	MPC_SPLIT_AVOID = 1,
-+	MPC_SPLIT_AVOID_MULT_DISP = 2,
-+};
-+
-+enum wm_report_mode {
-+	WM_REPORT_DEFAULT = 0,
-+	WM_REPORT_OVERRIDE = 1,
-+};
-+
-+struct dc_debug {
-+	bool surface_visual_confirm;
-+	bool sanity_checks;
-+	bool max_disp_clk;
-+	bool surface_trace;
-+	bool timing_trace;
-+	bool clock_trace;
-+	bool validation_trace;
-+
-+	/* stutter efficiency related */
-+	bool disable_stutter;
-+	bool use_max_lb;
-+	enum dcc_option disable_dcc;
-+	enum pipe_split_policy pipe_split_policy;
-+	bool force_single_disp_pipe_split;
-+	bool voltage_align_fclk;
-+
-+	bool disable_dfs_bypass;
-+	bool disable_dpp_power_gate;
-+	bool disable_hubp_power_gate;
-+	bool disable_pplib_wm_range;
-+	enum wm_report_mode pplib_wm_report_mode;
-+	unsigned int min_disp_clk_khz;
-+	int sr_exit_time_dpm0_ns;
-+	int sr_enter_plus_exit_time_dpm0_ns;
-+	int sr_exit_time_ns;
-+	int sr_enter_plus_exit_time_ns;
-+	int urgent_latency_ns;
-+	int percent_of_ideal_drambw;
-+	int dram_clock_change_latency_ns;
-+	int always_scale;
-+	bool disable_pplib_clock_request;
-+	bool disable_clock_gate;
-+	bool disable_dmcu;
-+	bool disable_psr;
-+	bool force_abm_enable;
-+	bool disable_hbup_pg;
-+	bool disable_dpp_pg;
-+	bool disable_stereo_support;
-+	bool vsr_support;
-+	bool performance_trace;
-+};
-+struct dc_state;
-+struct resource_pool;
-+struct dce_hwseq;
-+struct dc {
-+	struct dc_caps caps;
-+	struct dc_cap_funcs cap_funcs;
-+	struct dc_link_funcs link_funcs;
-+	struct dc_config config;
-+	struct dc_debug debug;
-+
-+	struct dc_context *ctx;
-+
-+	uint8_t link_count;
-+	struct dc_link *links[MAX_PIPES * 2];
-+
-+	struct dc_state *current_state;
-+	struct resource_pool *res_pool;
-+
-+	/* Display Engine Clock levels */
-+	struct dm_pp_clock_levels sclk_lvls;
-+
-+	/* Inputs into BW and WM calculations. */
-+	struct bw_calcs_dceip *bw_dceip;
-+	struct bw_calcs_vbios *bw_vbios;
-+#ifdef CONFIG_DRM_AMD_DC_DCN1_0
-+	struct dcn_soc_bounding_box *dcn_soc;
-+	struct dcn_ip_params *dcn_ip;
-+	struct display_mode_lib dml;
-+#endif
-+
-+	/* HW functions */
-+	struct hw_sequencer_funcs hwss;
-+	struct dce_hwseq *hwseq;
-+
-+	/* temp store of dm_pp_display_configuration
-+	 * to compare to see if display config changed
-+	 */
-+	struct dm_pp_display_configuration prev_display_config;
-+
-+	/* FBC compressor */
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+	struct compressor *fbc_compressor;
-+#endif
-+};
-+
-+enum frame_buffer_mode {
-+	FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
-+	FRAME_BUFFER_MODE_ZFB_ONLY,
-+	FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
-+} ;
-+
-+struct dchub_init_data {
-+	int64_t zfb_phys_addr_base;
-+	int64_t zfb_mc_base_addr;
-+	uint64_t zfb_size_in_byte;
-+	enum frame_buffer_mode fb_mode;
-+	bool dchub_initialzied;
-+	bool dchub_info_valid;
-+};
-+
-+struct dc_init_data {
-+	struct hw_asic_id asic_id;
-+	void *driver; /* ctx */
-+	struct cgs_device *cgs_device;
-+
-+	int num_virtual_links;
-+	/*
-+	 * If 'vbios_override' not NULL, it will be called instead
-+	 * of the real VBIOS. Intended use is Diagnostics on FPGA.
-+	 */
-+	struct dc_bios *vbios_override;
-+	enum dce_environment dce_environment;
-+
-+	struct dc_config flags;
-+	uint32_t log_mask;
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+	uint64_t fbc_gpu_addr;
-+#endif
-+};
-+
-+struct dc *dc_create(const struct dc_init_data *init_params);
-+
-+void dc_destroy(struct dc **dc);
-+
-+/*******************************************************************************
-+ * Surface Interfaces
-+ ******************************************************************************/
-+
-+enum {
-+	TRANSFER_FUNC_POINTS = 1025
-+};
-+
-+// Moved here from color module for linux
-+enum color_transfer_func {
-+	transfer_func_unknown,
-+	transfer_func_srgb,
-+	transfer_func_bt709,
-+	transfer_func_pq2084,
-+	transfer_func_pq2084_interim,
-+	transfer_func_linear_0_1,
-+	transfer_func_linear_0_125,
-+	transfer_func_dolbyvision,
-+	transfer_func_gamma_22,
-+	transfer_func_gamma_26
-+};
-+
-+struct dc_hdr_static_metadata {
-+	/* display chromaticities and white point in units of 0.00001 */
-+	unsigned int chromaticity_green_x;
-+	unsigned int chromaticity_green_y;
-+	unsigned int chromaticity_blue_x;
-+	unsigned int chromaticity_blue_y;
-+	unsigned int chromaticity_red_x;
-+	unsigned int chromaticity_red_y;
-+	unsigned int chromaticity_white_point_x;
-+	unsigned int chromaticity_white_point_y;
-+
-+	uint32_t min_luminance;
-+	uint32_t max_luminance;
-+	uint32_t maximum_content_light_level;
-+	uint32_t maximum_frame_average_light_level;
-+
-+	bool hdr_supported;
-+	bool is_hdr;
-+};
-+
-+enum dc_transfer_func_type {
-+	TF_TYPE_PREDEFINED,
-+	TF_TYPE_DISTRIBUTED_POINTS,
-+	TF_TYPE_BYPASS
-+};
-+
-+struct dc_transfer_func_distributed_points {
-+	struct fixed31_32 red[TRANSFER_FUNC_POINTS];
-+	struct fixed31_32 green[TRANSFER_FUNC_POINTS];
-+	struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
-+
-+	uint16_t end_exponent;
-+	uint16_t x_point_at_y1_red;
-+	uint16_t x_point_at_y1_green;
-+	uint16_t x_point_at_y1_blue;
-+};
-+
-+enum dc_transfer_func_predefined {
-+	TRANSFER_FUNCTION_SRGB,
-+	TRANSFER_FUNCTION_BT709,
-+	TRANSFER_FUNCTION_PQ,
-+	TRANSFER_FUNCTION_LINEAR,
-+};
-+
-+struct dc_transfer_func {
-+	struct kref refcount;
-+	struct dc_transfer_func_distributed_points tf_pts;
-+	enum dc_transfer_func_type type;
-+	enum dc_transfer_func_predefined tf;
-+	struct dc_context *ctx;
-+};
-+
-+/*
-+ * This structure is filled in by dc_surface_get_status and contains
-+ * the last requested address and the currently active address so the called
-+ * can determine if there are any outstanding flips
-+ */
-+struct dc_plane_status {
-+	struct dc_plane_address requested_address;
-+	struct dc_plane_address current_address;
-+	bool is_flip_pending;
-+	bool is_right_eye;
-+};
-+
-+union surface_update_flags {
-+
-+	struct {
-+		/* Medium updates */
-+		uint32_t color_space_change:1;
-+		uint32_t input_tf_change:1;
-+		uint32_t horizontal_mirror_change:1;
-+		uint32_t per_pixel_alpha_change:1;
-+		uint32_t rotation_change:1;
-+		uint32_t swizzle_change:1;
-+		uint32_t scaling_change:1;
-+		uint32_t position_change:1;
-+		uint32_t in_transfer_func:1;
-+		uint32_t input_csc_change:1;
-+
-+		/* Full updates */
-+		uint32_t new_plane:1;
-+		uint32_t bpp_change:1;
-+		uint32_t bandwidth_change:1;
-+		uint32_t clock_change:1;
-+		uint32_t stereo_format_change:1;
-+		uint32_t full_update:1;
-+	} bits;
-+
-+	uint32_t raw;
-+};
-+
-+struct dc_plane_state {
-+	struct dc_plane_address address;
-+	struct scaling_taps scaling_quality;
-+	struct rect src_rect;
-+	struct rect dst_rect;
-+	struct rect clip_rect;
-+
-+	union plane_size plane_size;
-+	union dc_tiling_info tiling_info;
-+
-+	struct dc_plane_dcc_param dcc;
-+
-+	struct dc_gamma *gamma_correction;
-+	struct dc_transfer_func *in_transfer_func;
-+	struct dc_bias_and_scale *bias_and_scale;
-+	struct csc_transform input_csc_color_matrix;
-+	struct fixed31_32 coeff_reduction_factor;
-+
-+	// TODO: No longer used, remove
-+	struct dc_hdr_static_metadata hdr_static_ctx;
-+
-+	enum dc_color_space color_space;
-+	enum color_transfer_func input_tf;
-+
-+	enum surface_pixel_format format;
-+	enum dc_rotation_angle rotation;
-+	enum plane_stereo_format stereo_format;
-+
-+	bool per_pixel_alpha;
-+	bool visible;
-+	bool flip_immediate;
-+	bool horizontal_mirror;
-+
-+	union surface_update_flags update_flags;
-+	/* private to DC core */
-+	struct dc_plane_status status;
-+	struct dc_context *ctx;
-+
-+	/* private to dc_surface.c */
-+	enum dc_irq_source irq_source;
-+	struct kref refcount;
-+};
-+
-+struct dc_plane_info {
-+	union plane_size plane_size;
-+	union dc_tiling_info tiling_info;
-+	struct dc_plane_dcc_param dcc;
-+	enum surface_pixel_format format;
-+	enum dc_rotation_angle rotation;
-+	enum plane_stereo_format stereo_format;
-+	enum dc_color_space color_space;
-+	enum color_transfer_func input_tf;
-+	bool horizontal_mirror;
-+	bool visible;
-+	bool per_pixel_alpha;
-+	bool input_csc_enabled;
-+};
-+
-+struct dc_scaling_info {
-+	struct rect src_rect;
-+	struct rect dst_rect;
-+	struct rect clip_rect;
-+	struct scaling_taps scaling_quality;
-+};
-+
-+struct dc_surface_update {
-+	struct dc_plane_state *surface;
-+
-+	/* isr safe update parameters.  null means no updates */
-+	struct dc_flip_addrs *flip_addr;
-+	struct dc_plane_info *plane_info;
-+	struct dc_scaling_info *scaling_info;
-+
-+	/* following updates require alloc/sleep/spin that is not isr safe,
-+	 * null means no updates
-+	 */
-+	/* gamma TO BE REMOVED */
-+	struct dc_gamma *gamma;
-+	enum color_transfer_func color_input_tf;
-+	enum color_transfer_func color_output_tf;
-+	struct dc_transfer_func *in_transfer_func;
-+
-+	struct csc_transform *input_csc_color_matrix;
-+	struct fixed31_32 *coeff_reduction_factor;
-+};
-+
-+/*
-+ * Create a new surface with default parameters;
-+ */
-+struct dc_plane_state *dc_create_plane_state(struct dc *dc);
-+const struct dc_plane_status *dc_plane_get_status(
-+		const struct dc_plane_state *plane_state);
-+
-+void dc_plane_state_retain(struct dc_plane_state *plane_state);
-+void dc_plane_state_release(struct dc_plane_state *plane_state);
-+
-+void dc_gamma_retain(struct dc_gamma *dc_gamma);
-+void dc_gamma_release(struct dc_gamma **dc_gamma);
-+struct dc_gamma *dc_create_gamma(void);
-+
-+void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
-+void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
-+struct dc_transfer_func *dc_create_transfer_func(void);
-+
-+/*
-+ * This structure holds a surface address.  There could be multiple addresses
-+ * in cases such as Stereo 3D, Planar YUV, etc.  Other per-flip attributes such
-+ * as frame durations and DCC format can also be set.
-+ */
-+struct dc_flip_addrs {
-+	struct dc_plane_address address;
-+	bool flip_immediate;
-+	/* TODO: add flip duration for FreeSync */
-+};
-+
-+bool dc_post_update_surfaces_to_stream(
-+		struct dc *dc);
-+
-+#include "dc_stream.h"
-+
-+/*
-+ * Structure to store surface/stream associations for validation
-+ */
-+struct dc_validation_set {
-+	struct dc_stream_state *stream;
-+	struct dc_plane_state *plane_states[MAX_SURFACES];
-+	uint8_t plane_count;
-+};
-+
-+enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
-+
-+enum dc_status dc_validate_global_state(
-+		struct dc *dc,
-+		struct dc_state *new_ctx);
-+
-+
-+void dc_resource_state_construct(
-+		const struct dc *dc,
-+		struct dc_state *dst_ctx);
-+
-+void dc_resource_state_copy_construct(
-+		const struct dc_state *src_ctx,
-+		struct dc_state *dst_ctx);
-+
-+void dc_resource_state_copy_construct_current(
-+		const struct dc *dc,
-+		struct dc_state *dst_ctx);
-+
-+void dc_resource_state_destruct(struct dc_state *context);
-+
-+/*
-+ * TODO update to make it about validation sets
-+ * Set up streams and links associated to drive sinks
-+ * The streams parameter is an absolute set of all active streams.
-+ *
-+ * After this call:
-+ *   Phy, Encoder, Timing Generator are programmed and enabled.
-+ *   New streams are enabled with blank stream; no memory read.
-+ */
-+bool dc_commit_state(struct dc *dc, struct dc_state *context);
-+
-+
-+struct dc_state *dc_create_state(void);
-+void dc_retain_state(struct dc_state *context);
-+void dc_release_state(struct dc_state *context);
-+
-+/*******************************************************************************
-+ * Link Interfaces
-+ ******************************************************************************/
-+
-+struct dpcd_caps {
-+	union dpcd_rev dpcd_rev;
-+	union max_lane_count max_ln_count;
-+	union max_down_spread max_down_spread;
-+
-+	/* dongle type (DP converter, CV smart dongle) */
-+	enum display_dongle_type dongle_type;
-+	/* Dongle's downstream count. */
-+	union sink_count sink_count;
-+	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
-+	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
-+	struct dc_dongle_caps dongle_caps;
-+
-+	uint32_t sink_dev_id;
-+	uint32_t branch_dev_id;
-+	int8_t branch_dev_name[6];
-+	int8_t branch_hw_revision;
-+
-+	bool allow_invalid_MSA_timing_param;
-+	bool panel_mode_edp;
-+	bool dpcd_display_control_capable;
-+};
-+
-+#include "dc_link.h"
-+
-+/*******************************************************************************
-+ * Sink Interfaces - A sink corresponds to a display output device
-+ ******************************************************************************/
-+
-+struct dc_container_id {
-+	// 128bit GUID in binary form
-+	unsigned char  guid[16];
-+	// 8 byte port ID -> ELD.PortID
-+	unsigned int   portId[2];
-+	// 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
-+	unsigned short manufacturerName;
-+	// 2 byte product code -> ELD.ProductCode
-+	unsigned short productCode;
-+};
-+
-+
-+
-+/*
-+ * The sink structure contains EDID and other display device properties
-+ */
-+struct dc_sink {
-+	enum signal_type sink_signal;
-+	struct dc_edid dc_edid; /* raw edid */
-+	struct dc_edid_caps edid_caps; /* parse display caps */
-+	struct dc_container_id *dc_container_id;
-+	uint32_t dongle_max_pix_clk;
-+	void *priv;
-+	struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
-+	bool converter_disable_audio;
-+
-+	/* private to DC core */
-+	struct dc_link *link;
-+	struct dc_context *ctx;
-+
-+	/* private to dc_sink.c */
-+	struct kref refcount;
-+
-+};
-+
-+void dc_sink_retain(struct dc_sink *sink);
-+void dc_sink_release(struct dc_sink *sink);
-+
-+struct dc_sink_init_data {
-+	enum signal_type sink_signal;
-+	struct dc_link *link;
-+	uint32_t dongle_max_pix_clk;
-+	bool converter_disable_audio;
-+};
-+
-+struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
-+
-+/* Newer interfaces  */
-+struct dc_cursor {
-+	struct dc_plane_address address;
-+	struct dc_cursor_attributes attributes;
-+};
-+
-+/*******************************************************************************
-+ * Interrupt interfaces
-+ ******************************************************************************/
-+enum dc_irq_source dc_interrupt_to_irq_source(
-+		struct dc *dc,
-+		uint32_t src_id,
-+		uint32_t ext_id);
-+void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
-+void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
-+enum dc_irq_source dc_get_hpd_irq_source_at_index(
-+		struct dc *dc, uint32_t link_index);
-+
-+/*******************************************************************************
-+ * Power Interfaces
-+ ******************************************************************************/
-+
-+void dc_set_power_state(
-+		struct dc *dc,
-+		enum dc_acpi_cm_power_state power_state);
-+void dc_resume(struct dc *dc);
-+
-+#endif /* DC_INTERFACE_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dc_helper.c.0130~	2017-12-14 06:39:58.420903571 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dc_helper.c	2017-12-14 06:39:58.420903571 +0100
-@@ -0,0 +1,176 @@
-+/*
-+ * dc_helper.c
-+ *
-+ *  Created on: Aug 30, 2016
-+ *      Author: agrodzov
-+ */
-+#include "dm_services.h"
-+#include <stdarg.h>
-+
-+uint32_t generic_reg_update_ex(const struct dc_context *ctx,
-+		uint32_t addr, uint32_t reg_val, int n,
-+		uint8_t shift1, uint32_t mask1, uint32_t field_value1,
-+		...)
-+{
-+	uint32_t shift, mask, field_value;
-+	int i = 1;
-+
-+	va_list ap;
-+	va_start(ap, field_value1);
-+
-+	reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1);
-+
-+	while (i < n) {
-+		shift = va_arg(ap, uint32_t);
-+		mask = va_arg(ap, uint32_t);
-+		field_value = va_arg(ap, uint32_t);
-+
-+		reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);
-+		i++;
-+	}
-+
-+	dm_write_reg(ctx, addr, reg_val);
-+	va_end(ap);
-+
-+	return reg_val;
-+}
-+
-+uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,
-+		uint8_t shift, uint32_t mask, uint32_t *field_value)
-+{
-+	uint32_t reg_val = dm_read_reg(ctx, addr);
-+	*field_value = get_reg_field_value_ex(reg_val, mask, shift);
-+	return reg_val;
-+}
-+
-+uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,
-+		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
-+		uint8_t shift2, uint32_t mask2, uint32_t *field_value2)
-+{
-+	uint32_t reg_val = dm_read_reg(ctx, addr);
-+	*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
-+	*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
-+	return reg_val;
-+}
-+
-+uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
-+		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
-+		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
-+		uint8_t shift3, uint32_t mask3, uint32_t *field_value3)
-+{
-+	uint32_t reg_val = dm_read_reg(ctx, addr);
-+	*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
-+	*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
-+	*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
-+	return reg_val;
-+}
-+
-+uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr,
-+		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
-+		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
-+		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
-+		uint8_t shift4, uint32_t mask4, uint32_t *field_value4)
-+{
-+	uint32_t reg_val = dm_read_reg(ctx, addr);
-+	*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
-+	*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
-+	*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
-+	*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
-+	return reg_val;
-+}
-+
-+uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
-+		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
-+		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
-+		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
-+		uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
-+		uint8_t shift5, uint32_t mask5, uint32_t *field_value5)
-+{
-+	uint32_t reg_val = dm_read_reg(ctx, addr);
-+	*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
-+	*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
-+	*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
-+	*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
-+	*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
-+	return reg_val;
-+}
-+
-+/* note:  va version of this is pretty bad idea, since there is a output parameter pass by pointer
-+ * compiler won't be able to check for size match and is prone to stack corruption type of bugs
-+
-+uint32_t generic_reg_get(const struct dc_context *ctx,
-+		uint32_t addr, int n, ...)
-+{
-+	uint32_t shift, mask;
-+	uint32_t *field_value;
-+	uint32_t reg_val;
-+	int i = 0;
-+
-+	reg_val = dm_read_reg(ctx, addr);
-+
-+	va_list ap;
-+	va_start(ap, n);
-+
-+	while (i < n) {
-+		shift = va_arg(ap, uint32_t);
-+		mask = va_arg(ap, uint32_t);
-+		field_value = va_arg(ap, uint32_t *);
-+
-+		*field_value = get_reg_field_value_ex(reg_val, mask, shift);
-+		i++;
-+	}
-+
-+	va_end(ap);
-+
-+	return reg_val;
-+}
-+*/
-+
-+uint32_t generic_reg_wait(const struct dc_context *ctx,
-+	uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value,
-+	unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
-+	const char *func_name, int line)
-+{
-+	uint32_t field_value;
-+	uint32_t reg_val;
-+	int i;
-+
-+	/* something is terribly wrong if time out is > 200ms. (5Hz) */
-+	ASSERT(delay_between_poll_us * time_out_num_tries <= 200000);
-+
-+	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
-+		/* 35 seconds */
-+		delay_between_poll_us = 35000;
-+		time_out_num_tries = 1000;
-+	}
-+
-+	for (i = 0; i <= time_out_num_tries; i++) {
-+		if (i) {
-+			if (delay_between_poll_us >= 1000)
-+				msleep(delay_between_poll_us/1000);
-+			else if (delay_between_poll_us > 0)
-+				udelay(delay_between_poll_us);
-+		}
-+
-+		reg_val = dm_read_reg(ctx, addr);
-+
-+		field_value = get_reg_field_value_ex(reg_val, mask, shift);
-+
-+		if (field_value == condition_value) {
-+			if (i * delay_between_poll_us > 1000)
-+				dm_output_to_console("REG_WAIT taking a while: %dms in %s line:%d\n",
-+						delay_between_poll_us * i / 1000,
-+						func_name, line);
-+			return reg_val;
-+		}
-+	}
-+
-+	dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n",
-+			delay_between_poll_us, time_out_num_tries,
-+			func_name, line);
-+
-+	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
-+		BREAK_TO_DEBUGGER();
-+
-+	return reg_val;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dc_hw_types.h.0130~	2017-12-14 06:39:58.420903571 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dc_hw_types.h	2017-12-14 06:39:58.420903571 +0100
-@@ -0,0 +1,731 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef DC_HW_TYPES_H
-+#define DC_HW_TYPES_H
-+
-+#include "os_types.h"
-+#include "fixed31_32.h"
-+#include "signal_types.h"
-+
-+/******************************************************************************
-+ * Data types for Virtual HW Layer of DAL3.
-+ * (see DAL3 design documents for HW Layer definition)
-+ *
-+ * The intended uses are:
-+ * 1. Generation pseudocode sequences for HW programming.
-+ * 2. Implementation of real HW programming by HW Sequencer of DAL3.
-+ *
-+ * Note: do *not* add any types which are *not* used for HW programming - this
-+ * will ensure separation of Logic layer from HW layer.
-+ ******************************************************************************/
-+
-+union large_integer {
-+	struct {
-+		uint32_t low_part;
-+		int32_t high_part;
-+	};
-+
-+	struct {
-+		uint32_t low_part;
-+		int32_t high_part;
-+	} u;
-+
-+	int64_t quad_part;
-+};
-+
-+#define PHYSICAL_ADDRESS_LOC union large_integer
-+
-+enum dc_plane_addr_type {
-+	PLN_ADDR_TYPE_GRAPHICS = 0,
-+	PLN_ADDR_TYPE_GRPH_STEREO,
-+	PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
-+};
-+
-+struct dc_plane_address {
-+	enum dc_plane_addr_type type;
-+	bool tmz_surface;
-+	union {
-+		struct{
-+			PHYSICAL_ADDRESS_LOC addr;
-+			PHYSICAL_ADDRESS_LOC meta_addr;
-+			union large_integer dcc_const_color;
-+		} grph;
-+
-+		/*stereo*/
-+		struct {
-+			PHYSICAL_ADDRESS_LOC left_addr;
-+			PHYSICAL_ADDRESS_LOC left_meta_addr;
-+			union large_integer left_dcc_const_color;
-+
-+			PHYSICAL_ADDRESS_LOC right_addr;
-+			PHYSICAL_ADDRESS_LOC right_meta_addr;
-+			union large_integer right_dcc_const_color;
-+
-+		} grph_stereo;
-+
-+		/*video  progressive*/
-+		struct {
-+			PHYSICAL_ADDRESS_LOC luma_addr;
-+			PHYSICAL_ADDRESS_LOC luma_meta_addr;
-+			union large_integer luma_dcc_const_color;
-+
-+			PHYSICAL_ADDRESS_LOC chroma_addr;
-+			PHYSICAL_ADDRESS_LOC chroma_meta_addr;
-+			union large_integer chroma_dcc_const_color;
-+		} video_progressive;
-+	};
-+};
-+
-+struct dc_size {
-+	int width;
-+	int height;
-+};
-+
-+struct rect {
-+	int x;
-+	int y;
-+	int width;
-+	int height;
-+};
-+
-+union plane_size {
-+	/* Grph or Video will be selected
-+	 * based on format above:
-+	 * Use Video structure if
-+	 * format >= DalPixelFormat_VideoBegin
-+	 * else use Grph structure
-+	 */
-+	struct {
-+		struct rect surface_size;
-+		/* Graphic surface pitch in pixels.
-+		 * In LINEAR_GENERAL mode, pitch
-+		 * is 32 pixel aligned.
-+		 */
-+		int surface_pitch;
-+	} grph;
-+
-+	struct {
-+		struct rect luma_size;
-+		/* Graphic surface pitch in pixels.
-+		 * In LINEAR_GENERAL mode, pitch is
-+		 * 32 pixel aligned.
-+		 */
-+		int luma_pitch;
-+
-+		struct rect chroma_size;
-+		/* Graphic surface pitch in pixels.
-+		 * In LINEAR_GENERAL mode, pitch is
-+		 * 32 pixel aligned.
-+		 */
-+		int chroma_pitch;
-+	} video;
-+};
-+
-+struct dc_plane_dcc_param {
-+	bool enable;
-+
-+	union {
-+		struct {
-+			int meta_pitch;
-+			bool independent_64b_blks;
-+		} grph;
-+
-+		struct {
-+			int meta_pitch_l;
-+			bool independent_64b_blks_l;
-+
-+			int meta_pitch_c;
-+			bool independent_64b_blks_c;
-+		} video;
-+	};
-+};
-+
-+/*Displayable pixel format in fb*/
-+enum surface_pixel_format {
-+	SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
-+	/*TOBE REMOVED paletta 256 colors*/
-+	SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
-+		SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
-+	/*16 bpp*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
-+	/*16 bpp*/
-+	SURFACE_PIXEL_FORMAT_GRPH_RGB565,
-+	/*32 bpp*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
-+	/*32 bpp swaped*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ABGR8888,
-+
-+	SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
-+	/*swaped*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
-+	/*TOBE REMOVED swaped, XR_BIAS has no differance
-+	 * for pixel layout than previous and we can
-+	 * delete this after discusion*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
-+	/*64 bpp */
-+	SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
-+	/*float*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F,
-+	/*swaped & float*/
-+	SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
-+	/*grow graphics here if necessary */
-+
-+	SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
-+	SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
-+		SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
-+	SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
-+	SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
-+	SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
-+	SURFACE_PIXEL_FORMAT_INVALID
-+
-+	/*grow 444 video here if necessary */
-+};
-+
-+
-+
-+/* Pixel format */
-+enum pixel_format {
-+	/*graph*/
-+	PIXEL_FORMAT_UNINITIALIZED,
-+	PIXEL_FORMAT_INDEX8,
-+	PIXEL_FORMAT_RGB565,
-+	PIXEL_FORMAT_ARGB8888,
-+	PIXEL_FORMAT_ARGB2101010,
-+	PIXEL_FORMAT_ARGB2101010_XRBIAS,
-+	PIXEL_FORMAT_FP16,
-+	/*video*/
-+	PIXEL_FORMAT_420BPP8,
-+	PIXEL_FORMAT_420BPP10,
-+	/*end of pixel format definition*/
-+	PIXEL_FORMAT_INVALID,
-+
-+	PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
-+	PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
-+	PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8,
-+	PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10,
-+	PIXEL_FORMAT_UNKNOWN
-+};
-+
-+enum tile_split_values {
-+	DC_DISPLAY_MICRO_TILING = 0x0,
-+	DC_THIN_MICRO_TILING = 0x1,
-+	DC_DEPTH_MICRO_TILING = 0x2,
-+	DC_ROTATED_MICRO_TILING = 0x3,
-+};
-+
-+/* TODO: These values come from hardware spec. We need to readdress this
-+ * if they ever change.
-+ */
-+enum array_mode_values {
-+	DC_ARRAY_LINEAR_GENERAL = 0,
-+	DC_ARRAY_LINEAR_ALLIGNED,
-+	DC_ARRAY_1D_TILED_THIN1,
-+	DC_ARRAY_1D_TILED_THICK,
-+	DC_ARRAY_2D_TILED_THIN1,
-+	DC_ARRAY_PRT_TILED_THIN1,
-+	DC_ARRAY_PRT_2D_TILED_THIN1,
-+	DC_ARRAY_2D_TILED_THICK,
-+	DC_ARRAY_2D_TILED_X_THICK,
-+	DC_ARRAY_PRT_TILED_THICK,
-+	DC_ARRAY_PRT_2D_TILED_THICK,
-+	DC_ARRAY_PRT_3D_TILED_THIN1,
-+	DC_ARRAY_3D_TILED_THIN1,
-+	DC_ARRAY_3D_TILED_THICK,
-+	DC_ARRAY_3D_TILED_X_THICK,
-+	DC_ARRAY_PRT_3D_TILED_THICK,
-+};
-+
-+enum tile_mode_values {
-+	DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
-+	DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
-+};
-+
-+enum swizzle_mode_values {
-+	DC_SW_LINEAR = 0,
-+	DC_SW_256B_S = 1,
-+	DC_SW_256_D = 2,
-+	DC_SW_256_R = 3,
-+	DC_SW_4KB_S = 5,
-+	DC_SW_4KB_D = 6,
-+	DC_SW_4KB_R = 7,
-+	DC_SW_64KB_S = 9,
-+	DC_SW_64KB_D = 10,
-+	DC_SW_64KB_R = 11,
-+	DC_SW_VAR_S = 13,
-+	DC_SW_VAR_D = 14,
-+	DC_SW_VAR_R = 15,
-+	DC_SW_64KB_S_T = 17,
-+	DC_SW_64KB_D_T = 18,
-+	DC_SW_4KB_S_X = 21,
-+	DC_SW_4KB_D_X = 22,
-+	DC_SW_4KB_R_X = 23,
-+	DC_SW_64KB_S_X = 25,
-+	DC_SW_64KB_D_X = 26,
-+	DC_SW_64KB_R_X = 27,
-+	DC_SW_VAR_S_X = 29,
-+	DC_SW_VAR_D_X = 30,
-+	DC_SW_VAR_R_X = 31,
-+	DC_SW_MAX
-+};
-+
-+union dc_tiling_info {
-+
-+	struct {
-+		/* Specifies the number of memory banks for tiling
-+		 *	purposes.
-+		 * Only applies to 2D and 3D tiling modes.
-+		 *	POSSIBLE VALUES: 2,4,8,16
-+		 */
-+		unsigned int num_banks;
-+		/* Specifies the number of tiles in the x direction
-+		 *	to be incorporated into the same bank.
-+		 * Only applies to 2D and 3D tiling modes.
-+		 *	POSSIBLE VALUES: 1,2,4,8
-+		 */
-+		unsigned int bank_width;
-+		unsigned int bank_width_c;
-+		/* Specifies the number of tiles in the y direction to
-+		 *	be incorporated into the same bank.
-+		 * Only applies to 2D and 3D tiling modes.
-+		 *	POSSIBLE VALUES: 1,2,4,8
-+		 */
-+		unsigned int bank_height;
-+		unsigned int bank_height_c;
-+		/* Specifies the macro tile aspect ratio. Only applies
-+		 * to 2D and 3D tiling modes.
-+		 */
-+		unsigned int tile_aspect;
-+		unsigned int tile_aspect_c;
-+		/* Specifies the number of bytes that will be stored
-+		 *	contiguously for each tile.
-+		 * If the tile data requires more storage than this
-+		 *	amount, it is split into multiple slices.
-+		 * This field must not be larger than
-+		 *	GB_ADDR_CONFIG.DRAM_ROW_SIZE.
-+		 * Only applies to 2D and 3D tiling modes.
-+		 * For color render targets, TILE_SPLIT >= 256B.
-+		 */
-+		enum tile_split_values tile_split;
-+		enum tile_split_values tile_split_c;
-+		/* Specifies the addressing within a tile.
-+		 *	0x0 - DISPLAY_MICRO_TILING
-+		 *	0x1 - THIN_MICRO_TILING
-+		 *	0x2 - DEPTH_MICRO_TILING
-+		 *	0x3 - ROTATED_MICRO_TILING
-+		 */
-+		enum tile_mode_values tile_mode;
-+		enum tile_mode_values tile_mode_c;
-+		/* Specifies the number of pipes and how they are
-+		 *	interleaved in the surface.
-+		 * Refer to memory addressing document for complete
-+		 *	details and constraints.
-+		 */
-+		unsigned int pipe_config;
-+		/* Specifies the tiling mode of the surface.
-+		 * THIN tiles use an 8x8x1 tile size.
-+		 * THICK tiles use an 8x8x4 tile size.
-+		 * 2D tiling modes rotate banks for successive Z slices
-+		 * 3D tiling modes rotate pipes and banks for Z slices
-+		 * Refer to memory addressing document for complete
-+		 *	details and constraints.
-+		 */
-+		enum array_mode_values array_mode;
-+	} gfx8;
-+
-+	struct {
-+		unsigned int num_pipes;
-+		unsigned int num_banks;
-+		unsigned int pipe_interleave;
-+		unsigned int num_shader_engines;
-+		unsigned int num_rb_per_se;
-+		unsigned int max_compressed_frags;
-+		bool shaderEnable;
-+
-+		enum swizzle_mode_values swizzle;
-+		bool meta_linear;
-+		bool rb_aligned;
-+		bool pipe_aligned;
-+	} gfx9;
-+};
-+
-+/* Rotation angle */
-+enum dc_rotation_angle {
-+	ROTATION_ANGLE_0 = 0,
-+	ROTATION_ANGLE_90,
-+	ROTATION_ANGLE_180,
-+	ROTATION_ANGLE_270,
-+	ROTATION_ANGLE_COUNT
-+};
-+
-+enum dc_scan_direction {
-+	SCAN_DIRECTION_UNKNOWN = 0,
-+	SCAN_DIRECTION_HORIZONTAL = 1,  /* 0, 180 rotation */
-+	SCAN_DIRECTION_VERTICAL = 2,    /* 90, 270 rotation */
-+};
-+
-+struct dc_cursor_position {
-+	uint32_t x;
-+	uint32_t y;
-+
-+	uint32_t x_hotspot;
-+	uint32_t y_hotspot;
-+
-+	/*
-+	 * This parameter indicates whether HW cursor should be enabled
-+	 */
-+	bool enable;
-+
-+};
-+
-+struct dc_cursor_mi_param {
-+	unsigned int pixel_clk_khz;
-+	unsigned int ref_clk_khz;
-+	unsigned int viewport_x_start;
-+	unsigned int viewport_width;
-+	struct fixed31_32 h_scale_ratio;
-+};
-+
-+/* IPP related types */
-+
-+enum {
-+	GAMMA_RGB_256_ENTRIES = 256,
-+	GAMMA_RGB_FLOAT_1024_ENTRIES = 1024,
-+	GAMMA_MAX_ENTRIES = 1024
-+};
-+
-+enum dc_gamma_type {
-+	GAMMA_RGB_256 = 1,
-+	GAMMA_RGB_FLOAT_1024 = 2
-+};
-+
-+struct dc_gamma {
-+	struct kref refcount;
-+	enum dc_gamma_type type;
-+	unsigned int num_entries;
-+
-+	struct dc_gamma_entries {
-+		struct fixed31_32 red[GAMMA_MAX_ENTRIES];
-+		struct fixed31_32 green[GAMMA_MAX_ENTRIES];
-+		struct fixed31_32 blue[GAMMA_MAX_ENTRIES];
-+	} entries;
-+
-+	/* private to DC core */
-+	struct dc_context *ctx;
-+};
-+
-+/* Used by both ipp amd opp functions*/
-+/* TODO: to be consolidated with enum color_space */
-+
-+/*
-+ * This enum is for programming CURSOR_MODE register field. What this register
-+ * should be programmed to depends on OS requested cursor shape flags and what
-+ * we stored in the cursor surface.
-+ */
-+enum dc_cursor_color_format {
-+	CURSOR_MODE_MONO,
-+	CURSOR_MODE_COLOR_1BIT_AND,
-+	CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
-+	CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
-+};
-+
-+/*
-+ * This is all the parameters required by DAL in order to update the cursor
-+ * attributes, including the new cursor image surface address, size, hotspot
-+ * location, color format, etc.
-+ */
-+
-+union dc_cursor_attribute_flags {
-+	struct {
-+		uint32_t ENABLE_MAGNIFICATION:1;
-+		uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
-+		uint32_t HORIZONTAL_MIRROR:1;
-+		uint32_t VERTICAL_MIRROR:1;
-+		uint32_t INVERT_PIXEL_DATA:1;
-+		uint32_t ZERO_EXPANSION:1;
-+		uint32_t MIN_MAX_INVERT:1;
-+		uint32_t RESERVED:25;
-+	} bits;
-+	uint32_t value;
-+};
-+
-+struct dc_cursor_attributes {
-+	PHYSICAL_ADDRESS_LOC address;
-+	uint32_t pitch;
-+
-+	/* Width and height should correspond to cursor surface width x heigh */
-+	uint32_t width;
-+	uint32_t height;
-+
-+	enum dc_cursor_color_format color_format;
-+
-+	/* In case we support HW Cursor rotation in the future */
-+	enum dc_rotation_angle rotation_angle;
-+
-+	union dc_cursor_attribute_flags attribute_flags;
-+};
-+
-+/* OPP */
-+
-+enum dc_color_space {
-+	COLOR_SPACE_UNKNOWN,
-+	COLOR_SPACE_SRGB,
-+	COLOR_SPACE_XR_RGB,
-+	COLOR_SPACE_SRGB_LIMITED,
-+	COLOR_SPACE_MSREF_SCRGB,
-+	COLOR_SPACE_YCBCR601,
-+	COLOR_SPACE_YCBCR709,
-+	COLOR_SPACE_XV_YCC_709,
-+	COLOR_SPACE_XV_YCC_601,
-+	COLOR_SPACE_YCBCR601_LIMITED,
-+	COLOR_SPACE_YCBCR709_LIMITED,
-+	COLOR_SPACE_2020_RGB_FULLRANGE,
-+	COLOR_SPACE_2020_RGB_LIMITEDRANGE,
-+	COLOR_SPACE_2020_YCBCR,
-+	COLOR_SPACE_ADOBERGB,
-+	COLOR_SPACE_DCIP3,
-+	COLOR_SPACE_DISPLAYNATIVE,
-+	COLOR_SPACE_DOLBYVISION,
-+	COLOR_SPACE_APPCTRL,
-+	COLOR_SPACE_CUSTOMPOINTS,
-+};
-+
-+enum dc_dither_option {
-+	DITHER_OPTION_DEFAULT,
-+	DITHER_OPTION_DISABLE,
-+	DITHER_OPTION_FM6,
-+	DITHER_OPTION_FM8,
-+	DITHER_OPTION_FM10,
-+	DITHER_OPTION_SPATIAL6_FRAME_RANDOM,
-+	DITHER_OPTION_SPATIAL8_FRAME_RANDOM,
-+	DITHER_OPTION_SPATIAL10_FRAME_RANDOM,
-+	DITHER_OPTION_SPATIAL6,
-+	DITHER_OPTION_SPATIAL8,
-+	DITHER_OPTION_SPATIAL10,
-+	DITHER_OPTION_TRUN6,
-+	DITHER_OPTION_TRUN8,
-+	DITHER_OPTION_TRUN10,
-+	DITHER_OPTION_TRUN10_SPATIAL8,
-+	DITHER_OPTION_TRUN10_SPATIAL6,
-+	DITHER_OPTION_TRUN10_FM8,
-+	DITHER_OPTION_TRUN10_FM6,
-+	DITHER_OPTION_TRUN10_SPATIAL8_FM6,
-+	DITHER_OPTION_SPATIAL10_FM8,
-+	DITHER_OPTION_SPATIAL10_FM6,
-+	DITHER_OPTION_TRUN8_SPATIAL6,
-+	DITHER_OPTION_TRUN8_FM6,
-+	DITHER_OPTION_SPATIAL8_FM6,
-+	DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6,
-+	DITHER_OPTION_INVALID
-+};
-+
-+enum dc_quantization_range {
-+	QUANTIZATION_RANGE_UNKNOWN,
-+	QUANTIZATION_RANGE_FULL,
-+	QUANTIZATION_RANGE_LIMITED
-+};
-+
-+/* XFM */
-+
-+/* used in  struct dc_plane_state */
-+struct scaling_taps {
-+	uint32_t v_taps;
-+	uint32_t h_taps;
-+	uint32_t v_taps_c;
-+	uint32_t h_taps_c;
-+};
-+
-+enum dc_timing_standard {
-+	TIMING_STANDARD_UNDEFINED,
-+	TIMING_STANDARD_DMT,
-+	TIMING_STANDARD_GTF,
-+	TIMING_STANDARD_CVT,
-+	TIMING_STANDARD_CVT_RB,
-+	TIMING_STANDARD_CEA770,
-+	TIMING_STANDARD_CEA861,
-+	TIMING_STANDARD_HDMI,
-+	TIMING_STANDARD_TV_NTSC,
-+	TIMING_STANDARD_TV_NTSC_J,
-+	TIMING_STANDARD_TV_PAL,
-+	TIMING_STANDARD_TV_PAL_M,
-+	TIMING_STANDARD_TV_PAL_CN,
-+	TIMING_STANDARD_TV_SECAM,
-+	TIMING_STANDARD_EXPLICIT,
-+	/*!< For explicit timings from EDID, VBIOS, etc.*/
-+	TIMING_STANDARD_USER_OVERRIDE,
-+	/*!< For mode timing override by user*/
-+	TIMING_STANDARD_MAX
-+};
-+
-+
-+
-+enum dc_color_depth {
-+	COLOR_DEPTH_UNDEFINED,
-+	COLOR_DEPTH_666,
-+	COLOR_DEPTH_888,
-+	COLOR_DEPTH_101010,
-+	COLOR_DEPTH_121212,
-+	COLOR_DEPTH_141414,
-+	COLOR_DEPTH_161616,
-+	COLOR_DEPTH_COUNT
-+};
-+
-+enum dc_pixel_encoding {
-+	PIXEL_ENCODING_UNDEFINED,
-+	PIXEL_ENCODING_RGB,
-+	PIXEL_ENCODING_YCBCR422,
-+	PIXEL_ENCODING_YCBCR444,
-+	PIXEL_ENCODING_YCBCR420,
-+	PIXEL_ENCODING_COUNT
-+};
-+
-+enum dc_aspect_ratio {
-+	ASPECT_RATIO_NO_DATA,
-+	ASPECT_RATIO_4_3,
-+	ASPECT_RATIO_16_9,
-+	ASPECT_RATIO_64_27,
-+	ASPECT_RATIO_256_135,
-+	ASPECT_RATIO_FUTURE
-+};
-+
-+enum scanning_type {
-+	SCANNING_TYPE_NODATA = 0,
-+	SCANNING_TYPE_OVERSCAN,
-+	SCANNING_TYPE_UNDERSCAN,
-+	SCANNING_TYPE_FUTURE,
-+	SCANNING_TYPE_UNDEFINED
-+};
-+
-+struct dc_crtc_timing_flags {
-+	uint32_t INTERLACE :1;
-+	uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
-+	 it is positive polarity --reversed with dal1 or video bios define*/
-+	uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
-+	 it is positive polarity --reversed with dal1 or video bios define*/
-+
-+	uint32_t HORZ_COUNT_BY_TWO:1;
-+
-+	uint32_t EXCLUSIVE_3D :1; /* if this bit set,
-+	 timing can be driven in 3D format only
-+	 and there is no corresponding 2D timing*/
-+	uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
-+	 (right eye = '1', left eye = '0') */
-+	uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right  images subsampled
-+	 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
-+	uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
-+	 because corresponding 2D timing also present in the list*/
-+	uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
-+	 and we want to match priority of corresponding 3D timing*/
-+	uint32_t Y_ONLY :1;
-+
-+	uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
-+	uint32_t DTD_COUNTER :5; /* values 1 to 16 */
-+
-+	uint32_t FORCE_HDR :1;
-+
-+	/* HDMI 2.0 - Support scrambling for TMDS character
-+	 * rates less than or equal to 340Mcsc */
-+	uint32_t LTE_340MCSC_SCRAMBLE:1;
-+
-+};
-+
-+enum dc_timing_3d_format {
-+	TIMING_3D_FORMAT_NONE,
-+	TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
-+	TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
-+	TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
-+	/* for active DP-HDMI dongle*/
-+	TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
-+	TIMING_3D_FORMAT_HW_FRAME_PACKING,
-+	TIMING_3D_FORMAT_SW_FRAME_PACKING,
-+	TIMING_3D_FORMAT_ROW_INTERLEAVE,
-+	TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
-+	TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
-+	TIMING_3D_FORMAT_SIDE_BY_SIDE,
-+	TIMING_3D_FORMAT_TOP_AND_BOTTOM,
-+	TIMING_3D_FORMAT_SBS_SW_PACKED,
-+	/* Side-by-side, packed by application/driver into 2D frame*/
-+	TIMING_3D_FORMAT_TB_SW_PACKED,
-+	/* Top-and-bottom, packed by application/driver into 2D frame*/
-+
-+	TIMING_3D_FORMAT_MAX,
-+};
-+
-+enum trigger_delay {
-+	TRIGGER_DELAY_NEXT_PIXEL = 0,
-+	TRIGGER_DELAY_NEXT_LINE,
-+};
-+
-+enum crtc_event {
-+	CRTC_EVENT_VSYNC_RISING = 0,
-+	CRTC_EVENT_VSYNC_FALLING
-+};
-+
-+struct crtc_trigger_info {
-+	bool enabled;
-+	struct dc_stream_state *event_source;
-+	enum crtc_event event;
-+	enum trigger_delay delay;
-+};
-+
-+struct dc_crtc_timing {
-+
-+	uint32_t h_total;
-+	uint32_t h_border_left;
-+	uint32_t h_addressable;
-+	uint32_t h_border_right;
-+	uint32_t h_front_porch;
-+	uint32_t h_sync_width;
-+
-+	uint32_t v_total;
-+	uint32_t v_border_top;
-+	uint32_t v_addressable;
-+	uint32_t v_border_bottom;
-+	uint32_t v_front_porch;
-+	uint32_t v_sync_width;
-+
-+	uint32_t pix_clk_khz;
-+
-+	uint32_t vic;
-+	uint32_t hdmi_vic;
-+	enum dc_timing_3d_format timing_3d_format;
-+	enum dc_color_depth display_color_depth;
-+	enum dc_pixel_encoding pixel_encoding;
-+	enum dc_aspect_ratio aspect_ratio;
-+	enum scanning_type scan_type;
-+
-+	struct dc_crtc_timing_flags flags;
-+};
-+
-+#define MAX_TG_COLOR_VALUE 0x3FF
-+struct tg_color {
-+	/* Maximum 10 bits color value */
-+	uint16_t color_r_cr;
-+	uint16_t color_g_y;
-+	uint16_t color_b_cb;
-+};
-+
-+#endif /* DC_HW_TYPES_H */
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dc_link.h.0130~	2017-12-14 06:39:58.420903571 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dc_link.h	2017-12-14 06:39:58.420903571 +0100
-@@ -0,0 +1,207 @@
-+/*
-+ * Copyright 2012-14 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef DC_LINK_H_
-+#define DC_LINK_H_
-+
-+#include "dc_types.h"
-+#include "grph_object_defs.h"
-+
-+struct dc_link_status {
-+	struct dpcd_caps *dpcd_caps;
-+};
-+
-+/* DP MST stream allocation (payload bandwidth number) */
-+struct link_mst_stream_allocation {
-+	/* DIG front */
-+	const struct stream_encoder *stream_enc;
-+	/* associate DRM payload table with DC stream encoder */
-+	uint8_t vcp_id;
-+	/* number of slots required for the DP stream in transport packet */
-+	uint8_t slot_count;
-+};
-+
-+/* DP MST stream allocation table */
-+struct link_mst_stream_allocation_table {
-+	/* number of DP video streams */
-+	int stream_count;
-+	/* array of stream allocations */
-+	struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
-+};
-+
-+/*
-+ * A link contains one or more sinks and their connected status.
-+ * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
-+ */
-+struct dc_link {
-+	struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
-+	unsigned int sink_count;
-+	struct dc_sink *local_sink;
-+	unsigned int link_index;
-+	enum dc_connection_type type;
-+	enum signal_type connector_signal;
-+	enum dc_irq_source irq_source_hpd;
-+	enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */
-+	/* caps is the same as reported_link_cap. link_traing use
-+	 * reported_link_cap. Will clean up.  TODO
-+	 */
-+	struct dc_link_settings reported_link_cap;
-+	struct dc_link_settings verified_link_cap;
-+	struct dc_link_settings cur_link_settings;
-+	struct dc_lane_settings cur_lane_setting;
-+	struct dc_link_settings preferred_link_setting;
-+
-+	uint8_t ddc_hw_inst;
-+
-+	uint8_t hpd_src;
-+
-+	uint8_t link_enc_hw_inst;
-+
-+	bool test_pattern_enabled;
-+	union compliance_test_state compliance_test_state;
-+
-+	void *priv;
-+
-+	struct ddc_service *ddc;
-+
-+	bool aux_mode;
-+
-+	/* Private to DC core */
-+
-+	const struct dc *dc;
-+
-+	struct dc_context *ctx;
-+
-+	struct link_encoder *link_enc;
-+	struct graphics_object_id link_id;
-+	union ddi_channel_mapping ddi_channel_mapping;
-+	struct connector_device_tag_info device_tag;
-+	struct dpcd_caps dpcd_caps;
-+	unsigned short chip_caps;
-+	unsigned int dpcd_sink_count;
-+	enum edp_revision edp_revision;
-+	bool psr_enabled;
-+
-+	/* MST record stream using this link */
-+	struct link_flags {
-+		bool dp_keep_receiver_powered;
-+	} wa_flags;
-+	struct link_mst_stream_allocation_table mst_stream_alloc_table;
-+
-+	struct dc_link_status link_status;
-+
-+};
-+
-+const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
-+
-+/*
-+ * Return an enumerated dc_link.  dc_link order is constant and determined at
-+ * boot time.  They cannot be created or destroyed.
-+ * Use dc_get_caps() to get number of links.
-+ */
-+static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index)
-+{
-+	return dc->links[link_index];
-+}
-+
-+/* Set backlight level of an embedded panel (eDP, LVDS). */
-+bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
-+		uint32_t frame_ramp, const struct dc_stream_state *stream);
-+
-+bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait);
-+
-+bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
-+
-+bool dc_link_setup_psr(struct dc_link *dc_link,
-+		const struct dc_stream_state *stream, struct psr_config *psr_config,
-+		struct psr_context *psr_context);
-+
-+/* Request DC to detect if there is a Panel connected.
-+ * boot - If this call is during initial boot.
-+ * Return false for any type of detection failure or MST detection
-+ * true otherwise. True meaning further action is required (status update
-+ * and OS notification).
-+ */
-+enum dc_detect_reason {
-+	DETECT_REASON_BOOT,
-+	DETECT_REASON_HPD,
-+	DETECT_REASON_HPDRX,
-+};
-+
-+bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason);
-+
-+/* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
-+ * Return:
-+ * true - Downstream port status changed. DM should call DC to do the
-+ * detection.
-+ * false - no change in Downstream port status. No further action required
-+ * from DM. */
-+bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
-+		union hpd_irq_data *hpd_irq_dpcd_data);
-+
-+struct dc_sink_init_data;
-+
-+struct dc_sink *dc_link_add_remote_sink(
-+		struct dc_link *dc_link,
-+		const uint8_t *edid,
-+		int len,
-+		struct dc_sink_init_data *init_data);
-+
-+void dc_link_remove_remote_sink(
-+	struct dc_link *link,
-+	struct dc_sink *sink);
-+
-+/* Used by diagnostics for virtual link at the moment */
-+
-+void dc_link_dp_set_drive_settings(
-+	struct dc_link *link,
-+	struct link_training_settings *lt_settings);
-+
-+enum link_training_result dc_link_dp_perform_link_training(
-+	struct dc_link *link,
-+	const struct dc_link_settings *link_setting,
-+	bool skip_video_pattern);
-+
-+void dc_link_dp_enable_hpd(const struct dc_link *link);
-+
-+void dc_link_dp_disable_hpd(const struct dc_link *link);
-+
-+bool dc_link_dp_set_test_pattern(
-+	struct dc_link *link,
-+	enum dp_test_pattern test_pattern,
-+	const struct link_training_settings *p_link_settings,
-+	const unsigned char *p_custom_pattern,
-+	unsigned int cust_pattern_size);
-+
-+/*
-+ * DPCD access interfaces
-+ */
-+
-+bool dc_submit_i2c(
-+		struct dc *dc,
-+		uint32_t link_index,
-+		struct i2c_command *cmd);
-+
-+#endif /* DC_LINK_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c.0130~	2017-12-14 06:39:58.420903571 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c	2017-12-14 06:39:58.420903571 +0100
-@@ -0,0 +1,123 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "reg_helper.h"
-+#include "dcn10_dpp.h"
-+
-+#include "dcn10_cm_common.h"
-+
-+#define REG(reg) reg
-+
-+#define CTX \
-+	ctx
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	reg->shifts.field_name, reg->masks.field_name
-+
-+void cm_helper_program_color_matrices(
-+		struct dc_context *ctx,
-+		const uint16_t *regval,
-+		const struct color_matrices_reg *reg)
-+{
-+	uint32_t cur_csc_reg;
-+	unsigned int i = 0;
-+
-+	for (cur_csc_reg = reg->csc_c11_c12;
-+			cur_csc_reg <= reg->csc_c33_c34;
-+			cur_csc_reg++) {
-+
-+		const uint16_t *regval0 = &(regval[2 * i]);
-+		const uint16_t *regval1 = &(regval[(2 * i) + 1]);
-+
-+		REG_SET_2(cur_csc_reg, 0,
-+				csc_c11, *regval0,
-+				csc_c12, *regval1);
-+
-+		i++;
-+	}
-+
-+}
-+
-+void cm_helper_program_xfer_func(
-+		struct dc_context *ctx,
-+		const struct pwl_params *params,
-+		const struct xfer_func_reg *reg)
-+{
-+	uint32_t reg_region_cur;
-+	unsigned int i = 0;
-+
-+	REG_SET_2(reg->start_cntl_b, 0,
-+			exp_region_start, params->arr_points[0].custom_float_x,
-+			exp_resion_start_segment, 0);
-+	REG_SET_2(reg->start_cntl_g, 0,
-+			exp_region_start, params->arr_points[0].custom_float_x,
-+			exp_resion_start_segment, 0);
-+	REG_SET_2(reg->start_cntl_r, 0,
-+			exp_region_start, params->arr_points[0].custom_float_x,
-+			exp_resion_start_segment, 0);
-+
-+	REG_SET(reg->start_slope_cntl_b, 0,
-+			field_region_linear_slope, params->arr_points[0].custom_float_slope);
-+	REG_SET(reg->start_slope_cntl_g, 0,
-+			field_region_linear_slope, params->arr_points[0].custom_float_slope);
-+	REG_SET(reg->start_slope_cntl_r, 0,
-+			field_region_linear_slope, params->arr_points[0].custom_float_slope);
-+
-+	REG_SET(reg->start_end_cntl1_b, 0,
-+			field_region_end, params->arr_points[1].custom_float_x);
-+	REG_SET_2(reg->start_end_cntl2_b, 0,
-+			field_region_end_slope, params->arr_points[1].custom_float_slope,
-+			field_region_end_base, params->arr_points[1].custom_float_y);
-+
-+	REG_SET(reg->start_end_cntl1_g, 0,
-+			field_region_end, params->arr_points[1].custom_float_x);
-+	REG_SET_2(reg->start_end_cntl2_g, 0,
-+			field_region_end_slope, params->arr_points[1].custom_float_slope,
-+		field_region_end_base, params->arr_points[1].custom_float_y);
-+
-+	REG_SET(reg->start_end_cntl1_r, 0,
-+			field_region_end, params->arr_points[1].custom_float_x);
-+	REG_SET_2(reg->start_end_cntl2_r, 0,
-+			field_region_end_slope, params->arr_points[1].custom_float_slope,
-+		field_region_end_base, params->arr_points[1].custom_float_y);
-+
-+	for (reg_region_cur = reg->region_start;
-+			reg_region_cur <= reg->region_end;
-+			reg_region_cur++) {
-+
-+		const struct gamma_curve *curve0 = &(params->arr_curve_points[2 * i]);
-+		const struct gamma_curve *curve1 = &(params->arr_curve_points[(2 * i) + 1]);
-+
-+		REG_SET_4(reg_region_cur, 0,
-+				exp_region0_lut_offset, curve0->offset,
-+				exp_region0_num_segments, curve0->segments_num,
-+				exp_region1_lut_offset, curve1->offset,
-+				exp_region1_num_segments, curve1->segments_num);
-+
-+		i++;
-+	}
-+
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h.0130~	2017-12-14 06:39:58.420903571 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h	2017-12-14 06:39:58.420903571 +0100
-@@ -0,0 +1,99 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DCN10_CM_COMMON_H__
-+#define __DAL_DCN10_CM_COMMON_H__
-+
-+#define TF_HELPER_REG_FIELD_LIST(type) \
-+	type exp_region0_lut_offset; \
-+	type exp_region0_num_segments; \
-+	type exp_region1_lut_offset; \
-+	type exp_region1_num_segments;\
-+	type field_region_end;\
-+	type field_region_end_slope;\
-+	type field_region_end_base;\
-+	type exp_region_start;\
-+	type exp_resion_start_segment;\
-+	type field_region_linear_slope
-+
-+#define TF_CM_REG_FIELD_LIST(type) \
-+	type csc_c11; \
-+	type csc_c12
-+
-+struct xfer_func_shift {
-+	TF_HELPER_REG_FIELD_LIST(uint8_t);
-+};
-+
-+struct xfer_func_mask {
-+	TF_HELPER_REG_FIELD_LIST(uint32_t);
-+};
-+
-+struct xfer_func_reg {
-+	struct xfer_func_shift shifts;
-+	struct xfer_func_mask masks;
-+
-+	uint32_t start_cntl_b;
-+	uint32_t start_cntl_g;
-+	uint32_t start_cntl_r;
-+	uint32_t start_slope_cntl_b;
-+	uint32_t start_slope_cntl_g;
-+	uint32_t start_slope_cntl_r;
-+	uint32_t start_end_cntl1_b;
-+	uint32_t start_end_cntl2_b;
-+	uint32_t start_end_cntl1_g;
-+	uint32_t start_end_cntl2_g;
-+	uint32_t start_end_cntl1_r;
-+	uint32_t start_end_cntl2_r;
-+	uint32_t region_start;
-+	uint32_t region_end;
-+};
-+
-+struct cm_color_matrix_shift {
-+	TF_CM_REG_FIELD_LIST(uint8_t);
-+};
-+
-+struct cm_color_matrix_mask {
-+	TF_CM_REG_FIELD_LIST(uint32_t);
-+};
-+
-+struct color_matrices_reg{
-+	struct cm_color_matrix_shift shifts;
-+	struct cm_color_matrix_mask masks;
-+
-+	uint32_t csc_c11_c12;
-+	uint32_t csc_c33_c34;
-+};
-+
-+void cm_helper_program_color_matrices(
-+		struct dc_context *ctx,
-+		const uint16_t *regval,
-+		const struct color_matrices_reg *reg);
-+
-+void cm_helper_program_xfer_func(
-+		struct dc_context *ctx,
-+		const struct pwl_params *params,
-+		const struct xfer_func_reg *reg);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c.0130~	2017-12-14 06:39:58.420903571 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c	2017-12-14 06:39:58.420903571 +0100
-@@ -0,0 +1,493 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "core_types.h"
-+
-+#include "reg_helper.h"
-+#include "dcn10_dpp.h"
-+#include "basics/conversion.h"
-+
-+#define NUM_PHASES    64
-+#define HORZ_MAX_TAPS 8
-+#define VERT_MAX_TAPS 8
-+
-+#define BLACK_OFFSET_RGB_Y 0x0
-+#define BLACK_OFFSET_CBCR  0x8000
-+
-+#define REG(reg)\
-+	dpp->tf_regs->reg
-+
-+#define CTX \
-+	dpp->base.ctx
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	dpp->tf_shift->field_name, dpp->tf_mask->field_name
-+
-+enum pixel_format_description {
-+	PIXEL_FORMAT_FIXED = 0,
-+	PIXEL_FORMAT_FIXED16,
-+	PIXEL_FORMAT_FLOAT
-+
-+};
-+
-+enum dcn10_coef_filter_type_sel {
-+	SCL_COEF_LUMA_VERT_FILTER = 0,
-+	SCL_COEF_LUMA_HORZ_FILTER = 1,
-+	SCL_COEF_CHROMA_VERT_FILTER = 2,
-+	SCL_COEF_CHROMA_HORZ_FILTER = 3,
-+	SCL_COEF_ALPHA_VERT_FILTER = 4,
-+	SCL_COEF_ALPHA_HORZ_FILTER = 5
-+};
-+
-+enum dscl_autocal_mode {
-+	AUTOCAL_MODE_OFF = 0,
-+
-+	/* Autocal calculate the scaling ratio and initial phase and the
-+	 * DSCL_MODE_SEL must be set to 1
-+	 */
-+	AUTOCAL_MODE_AUTOSCALE = 1,
-+	/* Autocal perform auto centering without replication and the
-+	 * DSCL_MODE_SEL must be set to 0
-+	 */
-+	AUTOCAL_MODE_AUTOCENTER = 2,
-+	/* Autocal perform auto centering and auto replication and the
-+	 * DSCL_MODE_SEL must be set to 0
-+	 */
-+	AUTOCAL_MODE_AUTOREPLICATE = 3
-+};
-+
-+enum dscl_mode_sel {
-+	DSCL_MODE_SCALING_444_BYPASS = 0,
-+	DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
-+	DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
-+	DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
-+	DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
-+	DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
-+	DSCL_MODE_DSCL_BYPASS = 6
-+};
-+
-+enum gamut_remap_select {
-+	GAMUT_REMAP_BYPASS = 0,
-+	GAMUT_REMAP_COEFF,
-+	GAMUT_REMAP_COMA_COEFF,
-+	GAMUT_REMAP_COMB_COEFF
-+};
-+
-+/* Program gamut remap in bypass mode */
-+void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
-+{
-+	REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
-+			CM_GAMUT_REMAP_MODE, 0);
-+	/* Gamut remap in bypass */
-+}
-+
-+#define IDENTITY_RATIO(ratio) (dal_fixed31_32_u2d19(ratio) == (1 << 19))
-+
-+
-+bool dpp_get_optimal_number_of_taps(
-+		struct dpp *dpp,
-+		struct scaler_data *scl_data,
-+		const struct scaling_taps *in_taps)
-+{
-+	uint32_t pixel_width;
-+
-+	if (scl_data->viewport.width > scl_data->recout.width)
-+		pixel_width = scl_data->recout.width;
-+	else
-+		pixel_width = scl_data->viewport.width;
-+
-+	/* TODO: add lb check */
-+
-+	/* No support for programming ratio of 4, drop to 3.99999.. */
-+	if (scl_data->ratios.horz.value == (4ll << 32))
-+		scl_data->ratios.horz.value--;
-+	if (scl_data->ratios.vert.value == (4ll << 32))
-+		scl_data->ratios.vert.value--;
-+	if (scl_data->ratios.horz_c.value == (4ll << 32))
-+		scl_data->ratios.horz_c.value--;
-+	if (scl_data->ratios.vert_c.value == (4ll << 32))
-+		scl_data->ratios.vert_c.value--;
-+
-+	/* Set default taps if none are provided */
-+	if (in_taps->h_taps == 0)
-+		scl_data->taps.h_taps = 4;
-+	else
-+		scl_data->taps.h_taps = in_taps->h_taps;
-+	if (in_taps->v_taps == 0)
-+		scl_data->taps.v_taps = 4;
-+	else
-+		scl_data->taps.v_taps = in_taps->v_taps;
-+	if (in_taps->v_taps_c == 0)
-+		scl_data->taps.v_taps_c = 2;
-+	else
-+		scl_data->taps.v_taps_c = in_taps->v_taps_c;
-+	if (in_taps->h_taps_c == 0)
-+		scl_data->taps.h_taps_c = 2;
-+	/* Only 1 and even h_taps_c are supported by hw */
-+	else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
-+		scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
-+	else
-+		scl_data->taps.h_taps_c = in_taps->h_taps_c;
-+
-+	if (!dpp->ctx->dc->debug.always_scale) {
-+		if (IDENTITY_RATIO(scl_data->ratios.horz))
-+			scl_data->taps.h_taps = 1;
-+		if (IDENTITY_RATIO(scl_data->ratios.vert))
-+			scl_data->taps.v_taps = 1;
-+		/*
-+		 * Spreadsheet doesn't handle taps_c is one properly,
-+		 * need to force Chroma to always be scaled to pass
-+		 * bandwidth validation.
-+		 */
-+	}
-+
-+	return true;
-+}
-+
-+void dpp_reset(struct dpp *dpp_base)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+
-+	dpp->filter_h_c = NULL;
-+	dpp->filter_v_c = NULL;
-+	dpp->filter_h = NULL;
-+	dpp->filter_v = NULL;
-+
-+	memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));
-+	memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));
-+}
-+
-+
-+
-+static void dpp1_cm_set_regamma_pwl(
-+	struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	uint32_t re_mode = 0;
-+
-+	switch (mode) {
-+	case OPP_REGAMMA_BYPASS:
-+		re_mode = 0;
-+		break;
-+	case OPP_REGAMMA_SRGB:
-+		re_mode = 1;
-+		break;
-+	case OPP_REGAMMA_3_6:
-+		re_mode = 2;
-+		break;
-+	case OPP_REGAMMA_USER:
-+		re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;
-+		if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)
-+			break;
-+
-+		dpp1_cm_power_on_regamma_lut(dpp_base, true);
-+		dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
-+
-+		if (dpp->is_write_to_ram_a_safe)
-+			dpp1_cm_program_regamma_luta_settings(dpp_base, params);
-+		else
-+			dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
-+
-+		dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted,
-+					    params->hw_points_num);
-+		dpp->pwl_data = *params;
-+
-+		re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
-+		dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
-+		break;
-+	default:
-+		break;
-+	}
-+	REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
-+}
-+
-+static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\
-+						enum pixel_format_description *fmt)
-+{
-+
-+	if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F ||
-+		input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F)
-+		*fmt = PIXEL_FORMAT_FLOAT;
-+	else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616)
-+		*fmt = PIXEL_FORMAT_FIXED16;
-+	else
-+		*fmt = PIXEL_FORMAT_FIXED;
-+}
-+
-+static void dpp1_set_degamma_format_float(
-+		struct dpp *dpp_base,
-+		bool is_float)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+
-+	if (is_float) {
-+		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
-+		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
-+	} else {
-+		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
-+		REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
-+	}
-+}
-+
-+void dpp1_cnv_setup (
-+		struct dpp *dpp_base,
-+		enum surface_pixel_format format,
-+		enum expansion_mode mode,
-+		struct csc_transform input_csc_color_matrix,
-+		enum dc_color_space input_color_space)
-+{
-+	uint32_t pixel_format;
-+	uint32_t alpha_en;
-+	enum pixel_format_description fmt ;
-+	enum dc_color_space color_space;
-+	enum dcn10_input_csc_select select;
-+	bool is_float;
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	bool force_disable_cursor = false;
-+	struct out_csc_color_matrix tbl_entry;
-+	int i = 0;
-+
-+	dpp1_setup_format_flags(format, &fmt);
-+	alpha_en = 1;
-+	pixel_format = 0;
-+	color_space = COLOR_SPACE_SRGB;
-+	select = INPUT_CSC_SELECT_BYPASS;
-+	is_float = false;
-+
-+	switch (fmt) {
-+	case PIXEL_FORMAT_FIXED:
-+	case PIXEL_FORMAT_FIXED16:
-+	/*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/
-+		REG_SET_3(FORMAT_CONTROL, 0,
-+			CNVC_BYPASS, 0,
-+			FORMAT_EXPANSION_MODE, mode,
-+			OUTPUT_FP, 0);
-+		break;
-+	case PIXEL_FORMAT_FLOAT:
-+		REG_SET_3(FORMAT_CONTROL, 0,
-+			CNVC_BYPASS, 0,
-+			FORMAT_EXPANSION_MODE, mode,
-+			OUTPUT_FP, 1);
-+		is_float = true;
-+		break;
-+	default:
-+
-+		break;
-+	}
-+
-+	dpp1_set_degamma_format_float(dpp_base, is_float);
-+
-+	switch (format) {
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
-+		pixel_format = 1;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
-+		pixel_format = 3;
-+		alpha_en = 0;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
-+		pixel_format = 8;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+		pixel_format = 10;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
-+		force_disable_cursor = false;
-+		pixel_format = 65;
-+		color_space = COLOR_SPACE_YCBCR709;
-+		select = INPUT_CSC_SELECT_ICSC;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
-+		force_disable_cursor = true;
-+		pixel_format = 64;
-+		color_space = COLOR_SPACE_YCBCR709;
-+		select = INPUT_CSC_SELECT_ICSC;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
-+		force_disable_cursor = true;
-+		pixel_format = 67;
-+		color_space = COLOR_SPACE_YCBCR709;
-+		select = INPUT_CSC_SELECT_ICSC;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
-+		force_disable_cursor = true;
-+		pixel_format = 66;
-+		color_space = COLOR_SPACE_YCBCR709;
-+		select = INPUT_CSC_SELECT_ICSC;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+		pixel_format = 22;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
-+		pixel_format = 24;
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+		pixel_format = 25;
-+		break;
-+	default:
-+		break;
-+	}
-+	REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
-+			CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
-+	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
-+
-+	// if input adjustments exist, program icsc with those values
-+
-+	if (input_csc_color_matrix.enable_adjustment
-+				== true) {
-+		for (i = 0; i < 12; i++)
-+			tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
-+
-+		tbl_entry.color_space = input_color_space;
-+
-+		if (color_space >= COLOR_SPACE_YCBCR601)
-+			select = INPUT_CSC_SELECT_ICSC;
-+		else
-+			select = INPUT_CSC_SELECT_BYPASS;
-+
-+		dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry);
-+	} else
-+		dpp1_program_input_csc(dpp_base, color_space, select, NULL);
-+
-+	if (force_disable_cursor) {
-+		REG_UPDATE(CURSOR_CONTROL,
-+				CURSOR_ENABLE, 0);
-+		REG_UPDATE(CURSOR0_CONTROL,
-+				CUR0_ENABLE, 0);
-+	}
-+}
-+
-+void dpp1_set_cursor_attributes(
-+		struct dpp *dpp_base,
-+		const struct dc_cursor_attributes *attr)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	enum dc_cursor_color_format color_format = attr->color_format;
-+
-+	REG_UPDATE_2(CURSOR0_CONTROL,
-+			CUR0_MODE, color_format,
-+			CUR0_EXPANSION_MODE, 0);
-+
-+	if (color_format == CURSOR_MODE_MONO) {
-+		/* todo: clarify what to program these to */
-+		REG_UPDATE(CURSOR0_COLOR0,
-+				CUR0_COLOR0, 0x00000000);
-+		REG_UPDATE(CURSOR0_COLOR1,
-+				CUR0_COLOR1, 0xFFFFFFFF);
-+	}
-+
-+	/* TODO: Fixed vs float */
-+
-+	REG_UPDATE_3(FORMAT_CONTROL,
-+				CNVC_BYPASS, 0,
-+				FORMAT_CONTROL__ALPHA_EN, 1,
-+				FORMAT_EXPANSION_MODE, 0);
-+}
-+
-+
-+void dpp1_set_cursor_position(
-+		struct dpp *dpp_base,
-+		const struct dc_cursor_position *pos,
-+		const struct dc_cursor_mi_param *param,
-+		uint32_t width)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start;
-+	uint32_t cur_en = pos->enable ? 1 : 0;
-+
-+	if (src_x_offset >= (int)param->viewport_width)
-+		cur_en = 0;  /* not visible beyond right edge*/
-+
-+	if (src_x_offset + (int)width < 0)
-+		cur_en = 0;  /* not visible beyond left edge*/
-+
-+	REG_UPDATE(CURSOR0_CONTROL,
-+			CUR0_ENABLE, cur_en);
-+
-+}
-+
-+static const struct dpp_funcs dcn10_dpp_funcs = {
-+		.dpp_reset = dpp_reset,
-+		.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
-+		.dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,
-+		.dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
-+		.dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
-+		.dpp_set_csc_default = dpp1_cm_set_output_csc_default,
-+		.dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
-+		.dpp_program_regamma_lut = dpp1_cm_program_regamma_lut,
-+		.dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
-+		.dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
-+		.dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
-+		.dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
-+		.dpp_program_bias_and_scale = dpp1_program_bias_and_scale,
-+		.dpp_set_degamma = dpp1_set_degamma,
-+		.dpp_program_input_lut		= dpp1_program_input_lut,
-+		.dpp_program_degamma_pwl	= dpp1_set_degamma_pwl,
-+		.dpp_setup			= dpp1_cnv_setup,
-+		.dpp_full_bypass		= dpp1_full_bypass,
-+		.set_cursor_attributes = dpp1_set_cursor_attributes,
-+		.set_cursor_position = dpp1_set_cursor_position,
-+};
-+
-+static struct dpp_caps dcn10_dpp_cap = {
-+	.dscl_data_proc_format = DSCL_DATA_PRCESSING_FIXED_FORMAT,
-+	.dscl_calc_lb_num_partitions = dpp1_dscl_calc_lb_num_partitions,
-+};
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+void dpp1_construct(
-+	struct dcn10_dpp *dpp,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dcn_dpp_registers *tf_regs,
-+	const struct dcn_dpp_shift *tf_shift,
-+	const struct dcn_dpp_mask *tf_mask)
-+{
-+	dpp->base.ctx = ctx;
-+
-+	dpp->base.inst = inst;
-+	dpp->base.funcs = &dcn10_dpp_funcs;
-+	dpp->base.caps = &dcn10_dpp_cap;
-+
-+	dpp->tf_regs = tf_regs;
-+	dpp->tf_shift = tf_shift;
-+	dpp->tf_mask = tf_mask;
-+
-+	dpp->lb_pixel_depth_supported =
-+		LB_PIXEL_DEPTH_18BPP |
-+		LB_PIXEL_DEPTH_24BPP |
-+		LB_PIXEL_DEPTH_30BPP;
-+
-+	dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
-+	dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c.0130~	2017-12-14 06:39:58.420903571 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c	2017-12-14 06:39:58.420903571 +0100
-@@ -0,0 +1,837 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "core_types.h"
-+
-+#include "reg_helper.h"
-+#include "dcn10_dpp.h"
-+#include "basics/conversion.h"
-+#include "dcn10_cm_common.h"
-+
-+#define NUM_PHASES    64
-+#define HORZ_MAX_TAPS 8
-+#define VERT_MAX_TAPS 8
-+
-+#define BLACK_OFFSET_RGB_Y 0x0
-+#define BLACK_OFFSET_CBCR  0x8000
-+
-+#define REG(reg)\
-+	dpp->tf_regs->reg
-+
-+#define CTX \
-+	dpp->base.ctx
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	dpp->tf_shift->field_name, dpp->tf_mask->field_name
-+
-+struct dcn10_input_csc_matrix {
-+	enum dc_color_space color_space;
-+	uint16_t regval[12];
-+};
-+
-+enum dcn10_coef_filter_type_sel {
-+	SCL_COEF_LUMA_VERT_FILTER = 0,
-+	SCL_COEF_LUMA_HORZ_FILTER = 1,
-+	SCL_COEF_CHROMA_VERT_FILTER = 2,
-+	SCL_COEF_CHROMA_HORZ_FILTER = 3,
-+	SCL_COEF_ALPHA_VERT_FILTER = 4,
-+	SCL_COEF_ALPHA_HORZ_FILTER = 5
-+};
-+
-+enum dscl_autocal_mode {
-+	AUTOCAL_MODE_OFF = 0,
-+
-+	/* Autocal calculate the scaling ratio and initial phase and the
-+	 * DSCL_MODE_SEL must be set to 1
-+	 */
-+	AUTOCAL_MODE_AUTOSCALE = 1,
-+	/* Autocal perform auto centering without replication and the
-+	 * DSCL_MODE_SEL must be set to 0
-+	 */
-+	AUTOCAL_MODE_AUTOCENTER = 2,
-+	/* Autocal perform auto centering and auto replication and the
-+	 * DSCL_MODE_SEL must be set to 0
-+	 */
-+	AUTOCAL_MODE_AUTOREPLICATE = 3
-+};
-+
-+enum dscl_mode_sel {
-+	DSCL_MODE_SCALING_444_BYPASS = 0,
-+	DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
-+	DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
-+	DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
-+	DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
-+	DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
-+	DSCL_MODE_DSCL_BYPASS = 6
-+};
-+
-+enum gamut_remap_select {
-+	GAMUT_REMAP_BYPASS = 0,
-+	GAMUT_REMAP_COEFF,
-+	GAMUT_REMAP_COMA_COEFF,
-+	GAMUT_REMAP_COMB_COEFF
-+};
-+
-+static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = {
-+	{COLOR_SPACE_SRGB,
-+		{0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
-+	{COLOR_SPACE_SRGB_LIMITED,
-+		{0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
-+	{COLOR_SPACE_YCBCR601,
-+		{0x2cdd, 0x2000, 0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef,
-+						0, 0x2000, 0x38b4, 0xe3a6} },
-+	{COLOR_SPACE_YCBCR601_LIMITED,
-+		{0x3353, 0x2568, 0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108,
-+						0, 0x2568, 0x40de, 0xdd3a} },
-+	{COLOR_SPACE_YCBCR709,
-+		{0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
-+						0x2000, 0x3b61, 0xe24f} },
-+
-+	{COLOR_SPACE_YCBCR709_LIMITED,
-+		{0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0,
-+						0x2568, 0x43ee, 0xdbb2} }
-+};
-+
-+
-+
-+static void program_gamut_remap(
-+		struct dcn10_dpp *dpp,
-+		const uint16_t *regval,
-+		enum gamut_remap_select select)
-+{
-+	uint16_t selection = 0;
-+	struct color_matrices_reg gam_regs;
-+
-+	if (regval == NULL || select == GAMUT_REMAP_BYPASS) {
-+		REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
-+				CM_GAMUT_REMAP_MODE, 0);
-+		return;
-+	}
-+	switch (select) {
-+	case GAMUT_REMAP_COEFF:
-+		selection = 1;
-+		break;
-+	case GAMUT_REMAP_COMA_COEFF:
-+		selection = 2;
-+		break;
-+	case GAMUT_REMAP_COMB_COEFF:
-+		selection = 3;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
-+	gam_regs.masks.csc_c11  = dpp->tf_mask->CM_GAMUT_REMAP_C11;
-+	gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
-+	gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
-+
-+
-+	if (select == GAMUT_REMAP_COEFF) {
-+		gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
-+		gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
-+
-+		cm_helper_program_color_matrices(
-+				dpp->base.ctx,
-+				regval,
-+				&gam_regs);
-+
-+	} else  if (select == GAMUT_REMAP_COMA_COEFF) {
-+
-+		gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
-+		gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
-+
-+		cm_helper_program_color_matrices(
-+				dpp->base.ctx,
-+				regval,
-+				&gam_regs);
-+
-+	} else {
-+
-+		gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
-+		gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
-+
-+		cm_helper_program_color_matrices(
-+				dpp->base.ctx,
-+				regval,
-+				&gam_regs);
-+	}
-+
-+	REG_SET(
-+			CM_GAMUT_REMAP_CONTROL, 0,
-+			CM_GAMUT_REMAP_MODE, selection);
-+
-+}
-+
-+void dpp1_cm_set_gamut_remap(
-+	struct dpp *dpp_base,
-+	const struct dpp_grph_csc_adjustment *adjust)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+
-+	if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
-+		/* Bypass if type is bypass or hw */
-+		program_gamut_remap(dpp, NULL, GAMUT_REMAP_BYPASS);
-+	else {
-+		struct fixed31_32 arr_matrix[12];
-+		uint16_t arr_reg_val[12];
-+
-+		arr_matrix[0] = adjust->temperature_matrix[0];
-+		arr_matrix[1] = adjust->temperature_matrix[1];
-+		arr_matrix[2] = adjust->temperature_matrix[2];
-+		arr_matrix[3] = dal_fixed31_32_zero;
-+
-+		arr_matrix[4] = adjust->temperature_matrix[3];
-+		arr_matrix[5] = adjust->temperature_matrix[4];
-+		arr_matrix[6] = adjust->temperature_matrix[5];
-+		arr_matrix[7] = dal_fixed31_32_zero;
-+
-+		arr_matrix[8] = adjust->temperature_matrix[6];
-+		arr_matrix[9] = adjust->temperature_matrix[7];
-+		arr_matrix[10] = adjust->temperature_matrix[8];
-+		arr_matrix[11] = dal_fixed31_32_zero;
-+
-+		convert_float_matrix(
-+			arr_reg_val, arr_matrix, 12);
-+
-+		program_gamut_remap(dpp, arr_reg_val, GAMUT_REMAP_COEFF);
-+	}
-+}
-+
-+void dpp1_cm_set_output_csc_default(
-+		struct dpp *dpp_base,
-+		enum dc_color_space colorspace)
-+{
-+
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	uint32_t ocsc_mode = 0;
-+
-+	switch (colorspace) {
-+		case COLOR_SPACE_SRGB:
-+		case COLOR_SPACE_2020_RGB_FULLRANGE:
-+			ocsc_mode = 0;
-+			break;
-+		case COLOR_SPACE_SRGB_LIMITED:
-+		case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
-+			ocsc_mode = 1;
-+			break;
-+		case COLOR_SPACE_YCBCR601:
-+		case COLOR_SPACE_YCBCR601_LIMITED:
-+			ocsc_mode = 2;
-+			break;
-+		case COLOR_SPACE_YCBCR709:
-+		case COLOR_SPACE_YCBCR709_LIMITED:
-+		case COLOR_SPACE_2020_YCBCR:
-+			ocsc_mode = 3;
-+			break;
-+		case COLOR_SPACE_UNKNOWN:
-+		default:
-+			break;
-+	}
-+
-+	REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
-+
-+}
-+
-+static void dpp1_cm_get_reg_field(
-+		struct dcn10_dpp *dpp,
-+		struct xfer_func_reg *reg)
-+{
-+	reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
-+	reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
-+	reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
-+	reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
-+	reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
-+	reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
-+	reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
-+	reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
-+
-+	reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;
-+	reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;
-+	reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
-+	reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
-+	reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
-+	reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
-+	reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
-+	reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
-+	reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B;
-+	reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B;
-+	reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
-+	reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
-+}
-+
-+static void dpp1_cm_program_color_matrix(
-+		struct dcn10_dpp *dpp,
-+		const struct out_csc_color_matrix *tbl_entry)
-+{
-+	uint32_t mode;
-+	struct color_matrices_reg gam_regs;
-+
-+	REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
-+
-+	if (tbl_entry == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;
-+	gam_regs.masks.csc_c11  = dpp->tf_mask->CM_OCSC_C11;
-+	gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;
-+	gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
-+
-+	if (mode == 4) {
-+
-+		gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);
-+		gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);
-+
-+		cm_helper_program_color_matrices(
-+				dpp->base.ctx,
-+				tbl_entry->regval,
-+				&gam_regs);
-+
-+	} else {
-+
-+		gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
-+		gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
-+
-+		cm_helper_program_color_matrices(
-+				dpp->base.ctx,
-+				tbl_entry->regval,
-+				&gam_regs);
-+	}
-+}
-+
-+void dpp1_cm_set_output_csc_adjustment(
-+		struct dpp *dpp_base,
-+		const struct out_csc_color_matrix *tbl_entry)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	//enum csc_color_mode config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
-+	uint32_t ocsc_mode = 4;
-+
-+	/**
-+	*if (tbl_entry != NULL) {
-+	*	switch (tbl_entry->color_space) {
-+	*	case COLOR_SPACE_SRGB:
-+	*	case COLOR_SPACE_2020_RGB_FULLRANGE:
-+	*		ocsc_mode = 0;
-+	*		break;
-+	*	case COLOR_SPACE_SRGB_LIMITED:
-+	*	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
-+	*		ocsc_mode = 1;
-+	*		break;
-+	*	case COLOR_SPACE_YCBCR601:
-+	*	case COLOR_SPACE_YCBCR601_LIMITED:
-+	*		ocsc_mode = 2;
-+	*		break;
-+	*	case COLOR_SPACE_YCBCR709:
-+	*	case COLOR_SPACE_YCBCR709_LIMITED:
-+	*	case COLOR_SPACE_2020_YCBCR:
-+	*		ocsc_mode = 3;
-+	*		break;
-+	*	case COLOR_SPACE_UNKNOWN:
-+	*	default:
-+	*		break;
-+	*	}
-+	*}
-+	*/
-+
-+	REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
-+	dpp1_cm_program_color_matrix(dpp, tbl_entry);
-+}
-+
-+void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base,
-+				  bool power_on)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+
-+	REG_SET(CM_MEM_PWR_CTRL, 0,
-+		RGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
-+
-+}
-+
-+void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,
-+				 const struct pwl_result_data *rgb,
-+				 uint32_t num)
-+{
-+	uint32_t i;
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+
-+	for (i = 0 ; i < num; i++) {
-+		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
-+		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
-+		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg);
-+
-+		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);
-+		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);
-+		REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);
-+
-+	}
-+
-+}
-+
-+void dpp1_cm_configure_regamma_lut(
-+		struct dpp *dpp_base,
-+		bool is_ram_a)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+
-+	REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,
-+			CM_RGAM_LUT_WRITE_EN_MASK, 7);
-+	REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,
-+			CM_RGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
-+	REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0);
-+}
-+
-+/*program re gamma RAM A*/
-+void dpp1_cm_program_regamma_luta_settings(
-+		struct dpp *dpp_base,
-+		const struct pwl_params *params)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	struct xfer_func_reg gam_regs;
-+
-+	dpp1_cm_get_reg_field(dpp, &gam_regs);
-+
-+	gam_regs.start_cntl_b = REG(CM_RGAM_RAMA_START_CNTL_B);
-+	gam_regs.start_cntl_g = REG(CM_RGAM_RAMA_START_CNTL_G);
-+	gam_regs.start_cntl_r = REG(CM_RGAM_RAMA_START_CNTL_R);
-+	gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMA_SLOPE_CNTL_B);
-+	gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMA_SLOPE_CNTL_G);
-+	gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMA_SLOPE_CNTL_R);
-+	gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMA_END_CNTL1_B);
-+	gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMA_END_CNTL2_B);
-+	gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMA_END_CNTL1_G);
-+	gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMA_END_CNTL2_G);
-+	gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMA_END_CNTL1_R);
-+	gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMA_END_CNTL2_R);
-+	gam_regs.region_start = REG(CM_RGAM_RAMA_REGION_0_1);
-+	gam_regs.region_end = REG(CM_RGAM_RAMA_REGION_32_33);
-+
-+	cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
-+
-+}
-+
-+/*program re gamma RAM B*/
-+void dpp1_cm_program_regamma_lutb_settings(
-+		struct dpp *dpp_base,
-+		const struct pwl_params *params)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	struct xfer_func_reg gam_regs;
-+
-+	dpp1_cm_get_reg_field(dpp, &gam_regs);
-+
-+	gam_regs.start_cntl_b = REG(CM_RGAM_RAMB_START_CNTL_B);
-+	gam_regs.start_cntl_g = REG(CM_RGAM_RAMB_START_CNTL_G);
-+	gam_regs.start_cntl_r = REG(CM_RGAM_RAMB_START_CNTL_R);
-+	gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMB_SLOPE_CNTL_B);
-+	gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMB_SLOPE_CNTL_G);
-+	gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMB_SLOPE_CNTL_R);
-+	gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMB_END_CNTL1_B);
-+	gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMB_END_CNTL2_B);
-+	gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMB_END_CNTL1_G);
-+	gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMB_END_CNTL2_G);
-+	gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMB_END_CNTL1_R);
-+	gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMB_END_CNTL2_R);
-+	gam_regs.region_start = REG(CM_RGAM_RAMB_REGION_0_1);
-+	gam_regs.region_end = REG(CM_RGAM_RAMB_REGION_32_33);
-+
-+	cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
-+}
-+
-+void dpp1_program_input_csc(
-+		struct dpp *dpp_base,
-+		enum dc_color_space color_space,
-+		enum dcn10_input_csc_select select,
-+		const struct out_csc_color_matrix *tbl_entry)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	int i;
-+	int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
-+	const uint16_t *regval = NULL;
-+	uint32_t selection = 1;
-+	struct color_matrices_reg gam_regs;
-+
-+	if (select == INPUT_CSC_SELECT_BYPASS) {
-+		REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);
-+		return;
-+	}
-+
-+	if (tbl_entry == NULL) {
-+		for (i = 0; i < arr_size; i++)
-+			if (dcn10_input_csc_matrix[i].color_space == color_space) {
-+				regval = dcn10_input_csc_matrix[i].regval;
-+				break;
-+			}
-+
-+		if (regval == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			return;
-+		}
-+	} else {
-+		regval = tbl_entry->regval;
-+	}
-+
-+	if (select == INPUT_CSC_SELECT_COMA)
-+		selection = 2;
-+	REG_SET(CM_ICSC_CONTROL, 0,
-+			CM_ICSC_MODE, selection);
-+
-+	gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;
-+	gam_regs.masks.csc_c11  = dpp->tf_mask->CM_ICSC_C11;
-+	gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;
-+	gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;
-+
-+
-+	if (select == INPUT_CSC_SELECT_ICSC) {
-+
-+		gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);
-+		gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);
-+
-+		cm_helper_program_color_matrices(
-+				dpp->base.ctx,
-+				regval,
-+				&gam_regs);
-+	} else {
-+
-+		gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
-+		gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
-+
-+		cm_helper_program_color_matrices(
-+				dpp->base.ctx,
-+				regval,
-+				&gam_regs);
-+	}
-+}
-+
-+//keep here for now, decide multi dce support later
-+void dpp1_program_bias_and_scale(
-+	struct dpp *dpp_base,
-+	struct dc_bias_and_scale *params)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+
-+	REG_SET_2(CM_BNS_VALUES_R, 0,
-+		CM_BNS_SCALE_R, params->scale_red,
-+		CM_BNS_BIAS_R, params->bias_red);
-+
-+	REG_SET_2(CM_BNS_VALUES_G, 0,
-+		CM_BNS_SCALE_G, params->scale_green,
-+		CM_BNS_BIAS_G, params->bias_green);
-+
-+	REG_SET_2(CM_BNS_VALUES_B, 0,
-+		CM_BNS_SCALE_B, params->scale_blue,
-+		CM_BNS_BIAS_B, params->bias_blue);
-+
-+}
-+
-+/*program de gamma RAM B*/
-+void dpp1_program_degamma_lutb_settings(
-+		struct dpp *dpp_base,
-+		const struct pwl_params *params)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	struct xfer_func_reg gam_regs;
-+
-+	dpp1_cm_get_reg_field(dpp, &gam_regs);
-+
-+	gam_regs.start_cntl_b = REG(CM_DGAM_RAMB_START_CNTL_B);
-+	gam_regs.start_cntl_g = REG(CM_DGAM_RAMB_START_CNTL_G);
-+	gam_regs.start_cntl_r = REG(CM_DGAM_RAMB_START_CNTL_R);
-+	gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMB_SLOPE_CNTL_B);
-+	gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMB_SLOPE_CNTL_G);
-+	gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMB_SLOPE_CNTL_R);
-+	gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMB_END_CNTL1_B);
-+	gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMB_END_CNTL2_B);
-+	gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMB_END_CNTL1_G);
-+	gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMB_END_CNTL2_G);
-+	gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMB_END_CNTL1_R);
-+	gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMB_END_CNTL2_R);
-+	gam_regs.region_start = REG(CM_DGAM_RAMB_REGION_0_1);
-+	gam_regs.region_end = REG(CM_DGAM_RAMB_REGION_14_15);
-+
-+
-+	cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
-+}
-+
-+/*program de gamma RAM A*/
-+void dpp1_program_degamma_luta_settings(
-+		struct dpp *dpp_base,
-+		const struct pwl_params *params)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	struct xfer_func_reg gam_regs;
-+
-+	dpp1_cm_get_reg_field(dpp, &gam_regs);
-+
-+	gam_regs.start_cntl_b = REG(CM_DGAM_RAMA_START_CNTL_B);
-+	gam_regs.start_cntl_g = REG(CM_DGAM_RAMA_START_CNTL_G);
-+	gam_regs.start_cntl_r = REG(CM_DGAM_RAMA_START_CNTL_R);
-+	gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMA_SLOPE_CNTL_B);
-+	gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMA_SLOPE_CNTL_G);
-+	gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMA_SLOPE_CNTL_R);
-+	gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMA_END_CNTL1_B);
-+	gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMA_END_CNTL2_B);
-+	gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMA_END_CNTL1_G);
-+	gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMA_END_CNTL2_G);
-+	gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMA_END_CNTL1_R);
-+	gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMA_END_CNTL2_R);
-+	gam_regs.region_start = REG(CM_DGAM_RAMA_REGION_0_1);
-+	gam_regs.region_end = REG(CM_DGAM_RAMA_REGION_14_15);
-+
-+	cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);
-+}
-+
-+void dpp1_power_on_degamma_lut(
-+		struct dpp *dpp_base,
-+	bool power_on)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+
-+	REG_SET(CM_MEM_PWR_CTRL, 0,
-+			SHARED_MEM_PWR_DIS, power_on == true ? 0:1);
-+
-+}
-+
-+static void dpp1_enable_cm_block(
-+		struct dpp *dpp_base)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+
-+	REG_UPDATE(CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, 8);
-+	REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
-+}
-+
-+void dpp1_set_degamma(
-+		struct dpp *dpp_base,
-+		enum ipp_degamma_mode mode)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	dpp1_enable_cm_block(dpp_base);
-+
-+	switch (mode) {
-+	case IPP_DEGAMMA_MODE_BYPASS:
-+		/* Setting de gamma bypass for now */
-+		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0);
-+		break;
-+	case IPP_DEGAMMA_MODE_HW_sRGB:
-+		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1);
-+		break;
-+	case IPP_DEGAMMA_MODE_HW_xvYCC:
-+		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);
-+			break;
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+}
-+
-+void dpp1_degamma_ram_select(
-+		struct dpp *dpp_base,
-+							bool use_ram_a)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+
-+	if (use_ram_a)
-+		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);
-+	else
-+		REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4);
-+
-+}
-+
-+static bool dpp1_degamma_ram_inuse(
-+		struct dpp *dpp_base,
-+							bool *ram_a_inuse)
-+{
-+	bool ret = false;
-+	uint32_t status_reg = 0;
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+
-+	REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
-+			&status_reg);
-+
-+	if (status_reg == 9) {
-+		*ram_a_inuse = true;
-+		ret = true;
-+	} else if (status_reg == 10) {
-+		*ram_a_inuse = false;
-+		ret = true;
-+	}
-+	return ret;
-+}
-+
-+void dpp1_program_degamma_lut(
-+		struct dpp *dpp_base,
-+		const struct pwl_result_data *rgb,
-+		uint32_t num,
-+		bool is_ram_a)
-+{
-+	uint32_t i;
-+
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, 0);
-+	REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK,
-+				   CM_DGAM_LUT_WRITE_EN_MASK, 7);
-+	REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL,
-+					is_ram_a == true ? 0:1);
-+
-+	REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0);
-+	for (i = 0 ; i < num; i++) {
-+		REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg);
-+		REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg);
-+		REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg);
-+
-+		REG_SET(CM_DGAM_LUT_DATA, 0,
-+				CM_DGAM_LUT_DATA, rgb[i].delta_red_reg);
-+		REG_SET(CM_DGAM_LUT_DATA, 0,
-+				CM_DGAM_LUT_DATA, rgb[i].delta_green_reg);
-+		REG_SET(CM_DGAM_LUT_DATA, 0,
-+				CM_DGAM_LUT_DATA, rgb[i].delta_blue_reg);
-+	}
-+}
-+
-+void dpp1_set_degamma_pwl(struct dpp *dpp_base,
-+								 const struct pwl_params *params)
-+{
-+	bool is_ram_a = true;
-+
-+	dpp1_power_on_degamma_lut(dpp_base, true);
-+	dpp1_enable_cm_block(dpp_base);
-+	dpp1_degamma_ram_inuse(dpp_base, &is_ram_a);
-+	if (is_ram_a == true)
-+		dpp1_program_degamma_lutb_settings(dpp_base, params);
-+	else
-+		dpp1_program_degamma_luta_settings(dpp_base, params);
-+
-+	dpp1_program_degamma_lut(dpp_base, params->rgb_resulted,
-+							params->hw_points_num, !is_ram_a);
-+	dpp1_degamma_ram_select(dpp_base, !is_ram_a);
-+}
-+
-+void dpp1_full_bypass(struct dpp *dpp_base)
-+{
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+
-+	/* Input pixel format: ARGB8888 */
-+	REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
-+			CNVC_SURFACE_PIXEL_FORMAT, 0x8);
-+
-+	/* Zero expansion */
-+	REG_SET_3(FORMAT_CONTROL, 0,
-+			CNVC_BYPASS, 0,
-+			FORMAT_CONTROL__ALPHA_EN, 0,
-+			FORMAT_EXPANSION_MODE, 0);
-+
-+	/* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */
-+	if (dpp->tf_mask->CM_BYPASS_EN)
-+		REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
-+
-+	/* Setting degamma bypass for now */
-+	REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);
-+}
-+
-+static bool dpp1_ingamma_ram_inuse(struct dpp *dpp_base,
-+							bool *ram_a_inuse)
-+{
-+	bool in_use = false;
-+	uint32_t status_reg = 0;
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+
-+	REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,
-+				&status_reg);
-+
-+	// 1 => IGAM_RAMA, 3 => IGAM_RAMA & DGAM_ROMA, 4 => IGAM_RAMA & DGAM_ROMB
-+	if (status_reg == 1 || status_reg == 3 || status_reg == 4) {
-+		*ram_a_inuse = true;
-+		in_use = true;
-+	// 2 => IGAM_RAMB, 5 => IGAM_RAMB & DGAM_ROMA, 6 => IGAM_RAMB & DGAM_ROMB
-+	} else if (status_reg == 2 || status_reg == 5 || status_reg == 6) {
-+		*ram_a_inuse = false;
-+		in_use = true;
-+	}
-+	return in_use;
-+}
-+
-+/*
-+ * Input gamma LUT currently supports 256 values only. This means input color
-+ * can have a maximum of 8 bits per channel (= 256 possible values) in order to
-+ * have a one-to-one mapping with the LUT. Truncation will occur with color
-+ * values greater than 8 bits.
-+ *
-+ * In the future, this function should support additional input gamma methods,
-+ * such as piecewise linear mapping, and input gamma bypass.
-+ */
-+void dpp1_program_input_lut(
-+		struct dpp *dpp_base,
-+		const struct dc_gamma *gamma)
-+{
-+	int i;
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	bool rama_occupied = false;
-+	uint32_t ram_num;
-+	// Power on LUT memory.
-+	REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 1);
-+	dpp1_enable_cm_block(dpp_base);
-+	// Determine whether to use RAM A or RAM B
-+	dpp1_ingamma_ram_inuse(dpp_base, &rama_occupied);
-+	if (!rama_occupied)
-+		REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 0);
-+	else
-+		REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 1);
-+	// RW mode is 256-entry LUT
-+	REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, 0);
-+	// IGAM Input format should be 8 bits per channel.
-+	REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 0);
-+	// Do not mask any R,G,B values
-+	REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, 7);
-+	// LUT-256, unsigned, integer, new u0.12 format
-+	REG_UPDATE_3(
-+		CM_IGAM_CONTROL,
-+		CM_IGAM_LUT_FORMAT_R, 3,
-+		CM_IGAM_LUT_FORMAT_G, 3,
-+		CM_IGAM_LUT_FORMAT_B, 3);
-+	// Start at index 0 of IGAM LUT
-+	REG_UPDATE(CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, 0);
-+	for (i = 0; i < gamma->num_entries; i++) {
-+		REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
-+				dal_fixed31_32_round(
-+					gamma->entries.red[i]));
-+		REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
-+				dal_fixed31_32_round(
-+					gamma->entries.green[i]));
-+		REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
-+				dal_fixed31_32_round(
-+					gamma->entries.blue[i]));
-+	}
-+	// Power off LUT memory
-+	REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 0);
-+	// Enable IGAM LUT on ram we just wrote to. 2 => RAMA, 3 => RAMB
-+	REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, rama_occupied ? 3 : 2);
-+	REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c.0130~	2017-12-14 06:39:58.420903571 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c	2017-12-14 06:39:58.420903571 +0100
-@@ -0,0 +1,707 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "core_types.h"
-+
-+#include "reg_helper.h"
-+#include "dcn10_dpp.h"
-+#include "basics/conversion.h"
-+
-+
-+#define NUM_PHASES    64
-+#define HORZ_MAX_TAPS 8
-+#define VERT_MAX_TAPS 8
-+
-+#define BLACK_OFFSET_RGB_Y 0x0
-+#define BLACK_OFFSET_CBCR  0x8000
-+
-+#define REG(reg)\
-+	dpp->tf_regs->reg
-+
-+#define CTX \
-+	dpp->base.ctx
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	dpp->tf_shift->field_name, dpp->tf_mask->field_name
-+
-+enum dcn10_coef_filter_type_sel {
-+	SCL_COEF_LUMA_VERT_FILTER = 0,
-+	SCL_COEF_LUMA_HORZ_FILTER = 1,
-+	SCL_COEF_CHROMA_VERT_FILTER = 2,
-+	SCL_COEF_CHROMA_HORZ_FILTER = 3,
-+	SCL_COEF_ALPHA_VERT_FILTER = 4,
-+	SCL_COEF_ALPHA_HORZ_FILTER = 5
-+};
-+
-+enum dscl_autocal_mode {
-+	AUTOCAL_MODE_OFF = 0,
-+
-+	/* Autocal calculate the scaling ratio and initial phase and the
-+	 * DSCL_MODE_SEL must be set to 1
-+	 */
-+	AUTOCAL_MODE_AUTOSCALE = 1,
-+	/* Autocal perform auto centering without replication and the
-+	 * DSCL_MODE_SEL must be set to 0
-+	 */
-+	AUTOCAL_MODE_AUTOCENTER = 2,
-+	/* Autocal perform auto centering and auto replication and the
-+	 * DSCL_MODE_SEL must be set to 0
-+	 */
-+	AUTOCAL_MODE_AUTOREPLICATE = 3
-+};
-+
-+enum dscl_mode_sel {
-+	DSCL_MODE_SCALING_444_BYPASS = 0,
-+	DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
-+	DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
-+	DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
-+	DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
-+	DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
-+	DSCL_MODE_DSCL_BYPASS = 6
-+};
-+
-+static void dpp1_dscl_set_overscan(
-+	struct dcn10_dpp *dpp,
-+	const struct scaler_data *data)
-+{
-+	uint32_t left = data->recout.x;
-+	uint32_t top = data->recout.y;
-+
-+	int right = data->h_active - data->recout.x - data->recout.width;
-+	int bottom = data->v_active - data->recout.y - data->recout.height;
-+
-+	if (right < 0) {
-+		BREAK_TO_DEBUGGER();
-+		right = 0;
-+	}
-+	if (bottom < 0) {
-+		BREAK_TO_DEBUGGER();
-+		bottom = 0;
-+	}
-+
-+	REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0,
-+		EXT_OVERSCAN_LEFT, left,
-+		EXT_OVERSCAN_RIGHT, right);
-+
-+	REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0,
-+		EXT_OVERSCAN_BOTTOM, bottom,
-+		EXT_OVERSCAN_TOP, top);
-+}
-+
-+static void dpp1_dscl_set_otg_blank(
-+		struct dcn10_dpp *dpp, const struct scaler_data *data)
-+{
-+	uint32_t h_blank_start = data->h_active;
-+	uint32_t h_blank_end = 0;
-+	uint32_t v_blank_start = data->v_active;
-+	uint32_t v_blank_end = 0;
-+
-+	REG_SET_2(OTG_H_BLANK, 0,
-+			OTG_H_BLANK_START, h_blank_start,
-+			OTG_H_BLANK_END, h_blank_end);
-+
-+	REG_SET_2(OTG_V_BLANK, 0,
-+			OTG_V_BLANK_START, v_blank_start,
-+			OTG_V_BLANK_END, v_blank_end);
-+}
-+
-+static int dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth)
-+{
-+	if (depth == LB_PIXEL_DEPTH_30BPP)
-+		return 0; /* 10 bpc */
-+	else if (depth == LB_PIXEL_DEPTH_24BPP)
-+		return 1; /* 8 bpc */
-+	else if (depth == LB_PIXEL_DEPTH_18BPP)
-+		return 2; /* 6 bpc */
-+	else if (depth == LB_PIXEL_DEPTH_36BPP)
-+		return 3; /* 12 bpc */
-+	else {
-+		ASSERT(0);
-+		return -1; /* Unsupported */
-+	}
-+}
-+
-+static bool dpp1_dscl_is_video_format(enum pixel_format format)
-+{
-+	if (format >= PIXEL_FORMAT_VIDEO_BEGIN
-+			&& format <= PIXEL_FORMAT_VIDEO_END)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+static bool dpp1_dscl_is_420_format(enum pixel_format format)
-+{
-+	if (format == PIXEL_FORMAT_420BPP8 ||
-+			format == PIXEL_FORMAT_420BPP10)
-+		return true;
-+	else
-+		return false;
-+}
-+
-+static enum dscl_mode_sel dpp1_dscl_get_dscl_mode(
-+		struct dpp *dpp_base,
-+		const struct scaler_data *data,
-+		bool dbg_always_scale)
-+{
-+	const long long one = dal_fixed31_32_one.value;
-+
-+	if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
-+		/* DSCL is processing data in fixed format */
-+		if (data->format == PIXEL_FORMAT_FP16)
-+			return DSCL_MODE_DSCL_BYPASS;
-+	}
-+
-+	if (data->ratios.horz.value == one
-+			&& data->ratios.vert.value == one
-+			&& data->ratios.horz_c.value == one
-+			&& data->ratios.vert_c.value == one
-+			&& !dbg_always_scale)
-+		return DSCL_MODE_SCALING_444_BYPASS;
-+
-+	if (!dpp1_dscl_is_420_format(data->format)) {
-+		if (dpp1_dscl_is_video_format(data->format))
-+			return DSCL_MODE_SCALING_444_YCBCR_ENABLE;
-+		else
-+			return DSCL_MODE_SCALING_444_RGB_ENABLE;
-+	}
-+	if (data->ratios.horz.value == one && data->ratios.vert.value == one)
-+		return DSCL_MODE_SCALING_420_LUMA_BYPASS;
-+	if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one)
-+		return DSCL_MODE_SCALING_420_CHROMA_BYPASS;
-+
-+	return DSCL_MODE_SCALING_420_YCBCR_ENABLE;
-+}
-+
-+static void dpp1_dscl_set_lb(
-+	struct dcn10_dpp *dpp,
-+	const struct line_buffer_params *lb_params,
-+	enum lb_memory_config mem_size_config)
-+{
-+	/* LB */
-+	if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
-+		/* DSCL caps: pixel data processed in fixed format */
-+		uint32_t pixel_depth = dpp1_dscl_get_pixel_depth_val(lb_params->depth);
-+		uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth;
-+
-+		REG_SET_7(LB_DATA_FORMAT, 0,
-+			PIXEL_DEPTH, pixel_depth, /* Pixel depth stored in LB */
-+			PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode, /* Pixel expansion mode */
-+			PIXEL_REDUCE_MODE, 1, /* Pixel reduction mode: Rounding */
-+			DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, /* Dynamic expansion pixel depth */
-+			DITHER_EN, 0, /* Dithering enable: Disabled */
-+			INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
-+			LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
-+	}
-+
-+	REG_SET_2(LB_MEMORY_CTRL, 0,
-+		MEMORY_CONFIG, mem_size_config,
-+		LB_MAX_PARTITIONS, 63);
-+}
-+
-+static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
-+{
-+	if (taps == 8)
-+		return get_filter_8tap_64p(ratio);
-+	else if (taps == 7)
-+		return get_filter_7tap_64p(ratio);
-+	else if (taps == 6)
-+		return get_filter_6tap_64p(ratio);
-+	else if (taps == 5)
-+		return get_filter_5tap_64p(ratio);
-+	else if (taps == 4)
-+		return get_filter_4tap_64p(ratio);
-+	else if (taps == 3)
-+		return get_filter_3tap_64p(ratio);
-+	else if (taps == 2)
-+		return get_filter_2tap_64p();
-+	else if (taps == 1)
-+		return NULL;
-+	else {
-+		/* should never happen, bug */
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+}
-+
-+static void dpp1_dscl_set_scaler_filter(
-+		struct dcn10_dpp *dpp,
-+		uint32_t taps,
-+		enum dcn10_coef_filter_type_sel filter_type,
-+		const uint16_t *filter)
-+{
-+	const int tap_pairs = (taps + 1) / 2;
-+	int phase;
-+	int pair;
-+	uint16_t odd_coef, even_coef;
-+
-+	REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0,
-+		SCL_COEF_RAM_TAP_PAIR_IDX, 0,
-+		SCL_COEF_RAM_PHASE, 0,
-+		SCL_COEF_RAM_FILTER_TYPE, filter_type);
-+
-+	for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
-+		for (pair = 0; pair < tap_pairs; pair++) {
-+			even_coef = filter[phase * taps + 2 * pair];
-+			if ((pair * 2 + 1) < taps)
-+				odd_coef = filter[phase * taps + 2 * pair + 1];
-+			else
-+				odd_coef = 0;
-+
-+			REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
-+				/* Even tap coefficient (bits 1:0 fixed to 0) */
-+				SCL_COEF_RAM_EVEN_TAP_COEF, even_coef,
-+				/* Write/read control for even coefficient */
-+				SCL_COEF_RAM_EVEN_TAP_COEF_EN, 1,
-+				/* Odd tap coefficient (bits 1:0 fixed to 0) */
-+				SCL_COEF_RAM_ODD_TAP_COEF, odd_coef,
-+				/* Write/read control for odd coefficient */
-+				SCL_COEF_RAM_ODD_TAP_COEF_EN, 1);
-+		}
-+	}
-+
-+}
-+
-+static void dpp1_dscl_set_scl_filter(
-+		struct dcn10_dpp *dpp,
-+		const struct scaler_data *scl_data,
-+		bool chroma_coef_mode)
-+{
-+	bool h_2tap_hardcode_coef_en = false;
-+	bool v_2tap_hardcode_coef_en = false;
-+	bool h_2tap_sharp_en = false;
-+	bool v_2tap_sharp_en = false;
-+	uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz;
-+	uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert;
-+	bool coef_ram_current;
-+	const uint16_t *filter_h = NULL;
-+	const uint16_t *filter_v = NULL;
-+	const uint16_t *filter_h_c = NULL;
-+	const uint16_t *filter_v_c = NULL;
-+
-+	h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3
-+					&& scl_data->taps.h_taps_c < 3
-+		&& (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1);
-+	v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3
-+					&& scl_data->taps.v_taps_c < 3
-+		&& (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1);
-+
-+	h_2tap_sharp_en = h_2tap_hardcode_coef_en && h_2tap_sharp_factor != 0;
-+	v_2tap_sharp_en = v_2tap_hardcode_coef_en && v_2tap_sharp_factor != 0;
-+
-+	REG_UPDATE_6(DSCL_2TAP_CONTROL,
-+		SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en,
-+		SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en,
-+		SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor,
-+		SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en,
-+		SCL_V_2TAP_SHARP_EN, v_2tap_sharp_en,
-+		SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor);
-+
-+	if (!v_2tap_hardcode_coef_en || !h_2tap_hardcode_coef_en) {
-+		bool filter_updated = false;
-+
-+		filter_h = dpp1_dscl_get_filter_coeffs_64p(
-+				scl_data->taps.h_taps, scl_data->ratios.horz);
-+		filter_v = dpp1_dscl_get_filter_coeffs_64p(
-+				scl_data->taps.v_taps, scl_data->ratios.vert);
-+
-+		filter_updated = (filter_h && (filter_h != dpp->filter_h))
-+				|| (filter_v && (filter_v != dpp->filter_v));
-+
-+		if (chroma_coef_mode) {
-+			filter_h_c = dpp1_dscl_get_filter_coeffs_64p(
-+					scl_data->taps.h_taps_c, scl_data->ratios.horz_c);
-+			filter_v_c = dpp1_dscl_get_filter_coeffs_64p(
-+					scl_data->taps.v_taps_c, scl_data->ratios.vert_c);
-+			filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))
-+							|| (filter_v_c && (filter_v_c != dpp->filter_v_c));
-+		}
-+
-+		if (filter_updated) {
-+			uint32_t scl_mode = REG_READ(SCL_MODE);
-+
-+			if (!h_2tap_hardcode_coef_en && filter_h) {
-+				dpp1_dscl_set_scaler_filter(
-+					dpp, scl_data->taps.h_taps,
-+					SCL_COEF_LUMA_HORZ_FILTER, filter_h);
-+			}
-+			dpp->filter_h = filter_h;
-+			if (!v_2tap_hardcode_coef_en && filter_v) {
-+				dpp1_dscl_set_scaler_filter(
-+					dpp, scl_data->taps.v_taps,
-+					SCL_COEF_LUMA_VERT_FILTER, filter_v);
-+			}
-+			dpp->filter_v = filter_v;
-+			if (chroma_coef_mode) {
-+				if (!h_2tap_hardcode_coef_en && filter_h_c) {
-+					dpp1_dscl_set_scaler_filter(
-+						dpp, scl_data->taps.h_taps_c,
-+						SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c);
-+				}
-+				if (!v_2tap_hardcode_coef_en && filter_v_c) {
-+					dpp1_dscl_set_scaler_filter(
-+						dpp, scl_data->taps.v_taps_c,
-+						SCL_COEF_CHROMA_VERT_FILTER, filter_v_c);
-+				}
-+			}
-+			dpp->filter_h_c = filter_h_c;
-+			dpp->filter_v_c = filter_v_c;
-+
-+			coef_ram_current = get_reg_field_value_ex(
-+				scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,
-+				dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);
-+
-+			/* Swap coefficient RAM and set chroma coefficient mode */
-+			REG_SET_2(SCL_MODE, scl_mode,
-+					SCL_COEF_RAM_SELECT, !coef_ram_current,
-+					SCL_CHROMA_COEF_MODE, chroma_coef_mode);
-+		}
-+	}
-+}
-+
-+static int dpp1_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth)
-+{
-+	if (depth == LB_PIXEL_DEPTH_30BPP)
-+		return 10;
-+	else if (depth == LB_PIXEL_DEPTH_24BPP)
-+		return 8;
-+	else if (depth == LB_PIXEL_DEPTH_18BPP)
-+		return 6;
-+	else if (depth == LB_PIXEL_DEPTH_36BPP)
-+		return 12;
-+	else {
-+		BREAK_TO_DEBUGGER();
-+		return -1; /* Unsupported */
-+	}
-+}
-+
-+void dpp1_dscl_calc_lb_num_partitions(
-+		const struct scaler_data *scl_data,
-+		enum lb_memory_config lb_config,
-+		int *num_part_y,
-+		int *num_part_c)
-+{
-+	int line_size = scl_data->viewport.width < scl_data->recout.width ?
-+			scl_data->viewport.width : scl_data->recout.width;
-+	int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
-+			scl_data->viewport_c.width : scl_data->recout.width;
-+	int lb_bpc = dpp1_dscl_get_lb_depth_bpc(scl_data->lb_params.depth);
-+	int memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */
-+	int memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */
-+	int memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
-+	int lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;
-+
-+	if (lb_config == LB_MEMORY_CONFIG_1) {
-+		lb_memory_size = 816;
-+		lb_memory_size_c = 816;
-+		lb_memory_size_a = 984;
-+	} else if (lb_config == LB_MEMORY_CONFIG_2) {
-+		lb_memory_size = 1088;
-+		lb_memory_size_c = 1088;
-+		lb_memory_size_a = 1312;
-+	} else if (lb_config == LB_MEMORY_CONFIG_3) {
-+		/* 420 mode: using 3rd mem from Y, Cr and Cb */
-+		lb_memory_size = 816 + 1088 + 848 + 848 + 848;
-+		lb_memory_size_c = 816 + 1088;
-+		lb_memory_size_a = 984 + 1312 + 456;
-+	} else {
-+		lb_memory_size = 816 + 1088 + 848;
-+		lb_memory_size_c = 816 + 1088 + 848;
-+		lb_memory_size_a = 984 + 1312 + 456;
-+	}
-+	*num_part_y = lb_memory_size / memory_line_size_y;
-+	*num_part_c = lb_memory_size_c / memory_line_size_c;
-+	num_partitions_a = lb_memory_size_a / memory_line_size_a;
-+
-+	if (scl_data->lb_params.alpha_en
-+			&& (num_partitions_a < *num_part_y))
-+		*num_part_y = num_partitions_a;
-+
-+	if (*num_part_y > 64)
-+		*num_part_y = 64;
-+	if (*num_part_c > 64)
-+		*num_part_c = 64;
-+
-+}
-+
-+bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps)
-+{
-+	if (ceil_vratio > 2)
-+		return vtaps <= (num_partitions - ceil_vratio + 2);
-+	else
-+		return vtaps <= num_partitions;
-+}
-+
-+/*find first match configuration which meets the min required lb size*/
-+static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp,
-+		const struct scaler_data *scl_data)
-+{
-+	int num_part_y, num_part_c;
-+	int vtaps = scl_data->taps.v_taps;
-+	int vtaps_c = scl_data->taps.v_taps_c;
-+	int ceil_vratio = dal_fixed31_32_ceil(scl_data->ratios.vert);
-+	int ceil_vratio_c = dal_fixed31_32_ceil(scl_data->ratios.vert_c);
-+	enum lb_memory_config mem_cfg = LB_MEMORY_CONFIG_0;
-+
-+	if (dpp->base.ctx->dc->debug.use_max_lb)
-+		return mem_cfg;
-+
-+	dpp->base.caps->dscl_calc_lb_num_partitions(
-+			scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c);
-+
-+	if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
-+			&& dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
-+		return LB_MEMORY_CONFIG_1;
-+
-+	dpp->base.caps->dscl_calc_lb_num_partitions(
-+			scl_data, LB_MEMORY_CONFIG_2, &num_part_y, &num_part_c);
-+
-+	if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
-+			&& dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
-+		return LB_MEMORY_CONFIG_2;
-+
-+	if (scl_data->format == PIXEL_FORMAT_420BPP8
-+			|| scl_data->format == PIXEL_FORMAT_420BPP10) {
-+		dpp->base.caps->dscl_calc_lb_num_partitions(
-+				scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c);
-+
-+		if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
-+				&& dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
-+			return LB_MEMORY_CONFIG_3;
-+	}
-+
-+	dpp->base.caps->dscl_calc_lb_num_partitions(
-+			scl_data, LB_MEMORY_CONFIG_0, &num_part_y, &num_part_c);
-+
-+	/*Ensure we can support the requested number of vtaps*/
-+	ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
-+			&& dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c));
-+
-+	return LB_MEMORY_CONFIG_0;
-+}
-+
-+void dpp1_dscl_set_scaler_auto_scale(
-+	struct dpp *dpp_base,
-+	const struct scaler_data *scl_data)
-+{
-+	enum lb_memory_config lb_config;
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
-+			dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
-+	bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
-+				&& scl_data->format <= PIXEL_FORMAT_VIDEO_END;
-+
-+	dpp1_dscl_set_overscan(dpp, scl_data);
-+
-+	dpp1_dscl_set_otg_blank(dpp, scl_data);
-+
-+	REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
-+
-+	if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
-+		return;
-+
-+	lb_config =  dpp1_dscl_find_lb_memory_config(dpp, scl_data);
-+	dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
-+
-+	if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
-+		return;
-+
-+	/* TODO: v_min */
-+	REG_SET_3(DSCL_AUTOCAL, 0,
-+		AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE,
-+		AUTOCAL_NUM_PIPE, 0,
-+		AUTOCAL_PIPE_ID, 0);
-+
-+	/* Black offsets */
-+	if (ycbcr)
-+		REG_SET_2(SCL_BLACK_OFFSET, 0,
-+				SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
-+				SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
-+	else
-+
-+		REG_SET_2(SCL_BLACK_OFFSET, 0,
-+				SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
-+				SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
-+
-+	REG_SET_4(SCL_TAP_CONTROL, 0,
-+		SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
-+		SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
-+		SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
-+		SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
-+
-+	dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
-+}
-+
-+
-+static void dpp1_dscl_set_manual_ratio_init(
-+		struct dcn10_dpp *dpp, const struct scaler_data *data)
-+{
-+	uint32_t init_frac = 0;
-+	uint32_t init_int = 0;
-+
-+	REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
-+			SCL_H_SCALE_RATIO, dal_fixed31_32_u2d19(data->ratios.horz) << 5);
-+
-+	REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
-+			SCL_V_SCALE_RATIO, dal_fixed31_32_u2d19(data->ratios.vert) << 5);
-+
-+	REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,
-+			SCL_H_SCALE_RATIO_C, dal_fixed31_32_u2d19(data->ratios.horz_c) << 5);
-+
-+	REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,
-+			SCL_V_SCALE_RATIO_C, dal_fixed31_32_u2d19(data->ratios.vert_c) << 5);
-+
-+	/*
-+	 * 0.24 format for fraction, first five bits zeroed
-+	 */
-+	init_frac = dal_fixed31_32_u0d19(data->inits.h) << 5;
-+	init_int = dal_fixed31_32_floor(data->inits.h);
-+	REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
-+		SCL_H_INIT_FRAC, init_frac,
-+		SCL_H_INIT_INT, init_int);
-+
-+	init_frac = dal_fixed31_32_u0d19(data->inits.h_c) << 5;
-+	init_int = dal_fixed31_32_floor(data->inits.h_c);
-+	REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,
-+		SCL_H_INIT_FRAC_C, init_frac,
-+		SCL_H_INIT_INT_C, init_int);
-+
-+	init_frac = dal_fixed31_32_u0d19(data->inits.v) << 5;
-+	init_int = dal_fixed31_32_floor(data->inits.v);
-+	REG_SET_2(SCL_VERT_FILTER_INIT, 0,
-+		SCL_V_INIT_FRAC, init_frac,
-+		SCL_V_INIT_INT, init_int);
-+
-+	init_frac = dal_fixed31_32_u0d19(data->inits.v_bot) << 5;
-+	init_int = dal_fixed31_32_floor(data->inits.v_bot);
-+	REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,
-+		SCL_V_INIT_FRAC_BOT, init_frac,
-+		SCL_V_INIT_INT_BOT, init_int);
-+
-+	init_frac = dal_fixed31_32_u0d19(data->inits.v_c) << 5;
-+	init_int = dal_fixed31_32_floor(data->inits.v_c);
-+	REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,
-+		SCL_V_INIT_FRAC_C, init_frac,
-+		SCL_V_INIT_INT_C, init_int);
-+
-+	init_frac = dal_fixed31_32_u0d19(data->inits.v_c_bot) << 5;
-+	init_int = dal_fixed31_32_floor(data->inits.v_c_bot);
-+	REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,
-+		SCL_V_INIT_FRAC_BOT_C, init_frac,
-+		SCL_V_INIT_INT_BOT_C, init_int);
-+}
-+
-+
-+
-+static void dpp1_dscl_set_recout(
-+			struct dcn10_dpp *dpp, const struct rect *recout)
-+{
-+	REG_SET_2(RECOUT_START, 0,
-+		/* First pixel of RECOUT */
-+			 RECOUT_START_X, recout->x,
-+		/* First line of RECOUT */
-+			 RECOUT_START_Y, recout->y);
-+
-+	REG_SET_2(RECOUT_SIZE, 0,
-+		/* Number of RECOUT horizontal pixels */
-+			 RECOUT_WIDTH, recout->width,
-+		/* Number of RECOUT vertical lines */
-+			 RECOUT_HEIGHT, recout->height
-+			 - dpp->base.ctx->dc->debug.surface_visual_confirm * 4 *
-+			 (dpp->base.inst + 1));
-+}
-+
-+/* Main function to program scaler and line buffer in manual scaling mode */
-+void dpp1_dscl_set_scaler_manual_scale(
-+	struct dpp *dpp_base,
-+	const struct scaler_data *scl_data)
-+{
-+	enum lb_memory_config lb_config;
-+	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-+	enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
-+			dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
-+	bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
-+				&& scl_data->format <= PIXEL_FORMAT_VIDEO_END;
-+
-+	if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)
-+		return;
-+
-+	dpp->scl_data = *scl_data;
-+
-+	/* Recout */
-+	dpp1_dscl_set_recout(dpp, &scl_data->recout);
-+
-+	/* MPC Size */
-+	REG_SET_2(MPC_SIZE, 0,
-+		/* Number of horizontal pixels of MPC */
-+			 MPC_WIDTH, scl_data->h_active,
-+		/* Number of vertical lines of MPC */
-+			 MPC_HEIGHT, scl_data->v_active);
-+
-+	/* SCL mode */
-+	REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
-+
-+	if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
-+		return;
-+
-+	/* LB */
-+	lb_config =  dpp1_dscl_find_lb_memory_config(dpp, scl_data);
-+	dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
-+
-+	if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
-+		return;
-+
-+	/* Autocal off */
-+	REG_SET_3(DSCL_AUTOCAL, 0,
-+		AUTOCAL_MODE, AUTOCAL_MODE_OFF,
-+		AUTOCAL_NUM_PIPE, 0,
-+		AUTOCAL_PIPE_ID, 0);
-+
-+	/* Black offsets */
-+	if (ycbcr)
-+		REG_SET_2(SCL_BLACK_OFFSET, 0,
-+				SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
-+				SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
-+	else
-+
-+		REG_SET_2(SCL_BLACK_OFFSET, 0,
-+				SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
-+				SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
-+
-+	/* Manually calculate scale ratio and init values */
-+	dpp1_dscl_set_manual_ratio_init(dpp, scl_data);
-+
-+	/* HTaps/VTaps */
-+	REG_SET_4(SCL_TAP_CONTROL, 0,
-+		SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
-+		SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
-+		SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
-+		SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
-+
-+	dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h.0130~	2017-12-14 06:39:58.421903572 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h	2017-12-14 06:39:58.421903572 +0100
-@@ -0,0 +1,1403 @@
-+/* Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DPP_DCN10_H__
-+#define __DAL_DPP_DCN10_H__
-+
-+#include "dpp.h"
-+
-+#define TO_DCN10_DPP(dpp)\
-+	container_of(dpp, struct dcn10_dpp, base)
-+
-+/* TODO: Use correct number of taps. Using polaris values for now */
-+#define LB_TOTAL_NUMBER_OF_ENTRIES 5124
-+#define LB_BITS_PER_ENTRY 144
-+
-+#define TF_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+//Used to resolve corner case
-+#define TF2_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## _ ## field_name ## post_fix
-+
-+#define TF_REG_LIST_DCN(id) \
-+	SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
-+	SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
-+	SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
-+	SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
-+	SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
-+	SRI(OTG_H_BLANK, DSCL, id), \
-+	SRI(OTG_V_BLANK, DSCL, id), \
-+	SRI(SCL_MODE, DSCL, id), \
-+	SRI(LB_DATA_FORMAT, DSCL, id), \
-+	SRI(LB_MEMORY_CTRL, DSCL, id), \
-+	SRI(DSCL_AUTOCAL, DSCL, id), \
-+	SRI(SCL_BLACK_OFFSET, DSCL, id), \
-+	SRI(SCL_TAP_CONTROL, DSCL, id), \
-+	SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
-+	SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
-+	SRI(DSCL_2TAP_CONTROL, DSCL, id), \
-+	SRI(MPC_SIZE, DSCL, id), \
-+	SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
-+	SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
-+	SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
-+	SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
-+	SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
-+	SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
-+	SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
-+	SRI(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \
-+	SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
-+	SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
-+	SRI(RECOUT_START, DSCL, id), \
-+	SRI(RECOUT_SIZE, DSCL, id), \
-+	SRI(CM_ICSC_CONTROL, CM, id), \
-+	SRI(CM_ICSC_C11_C12, CM, id), \
-+	SRI(CM_ICSC_C33_C34, CM, id), \
-+	SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
-+	SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
-+	SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
-+	SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \
-+	SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \
-+	SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \
-+	SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \
-+	SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \
-+	SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \
-+	SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \
-+	SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \
-+	SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \
-+	SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \
-+	SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \
-+	SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \
-+	SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \
-+	SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \
-+	SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \
-+	SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \
-+	SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \
-+	SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \
-+	SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \
-+	SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \
-+	SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \
-+	SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \
-+	SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \
-+	SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \
-+	SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
-+	SRI(CM_MEM_PWR_CTRL, CM, id), \
-+	SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
-+	SRI(CM_DGAM_LUT_INDEX, CM, id), \
-+	SRI(CM_DGAM_LUT_DATA, CM, id), \
-+	SRI(CM_CONTROL, CM, id), \
-+	SRI(CM_DGAM_CONTROL, CM, id), \
-+	SRI(FORMAT_CONTROL, CNVC_CFG, id), \
-+	SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
-+	SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
-+	SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
-+	SRI(CURSOR0_COLOR1, CNVC_CUR, id)
-+
-+
-+
-+#define TF_REG_LIST_DCN10(id) \
-+	TF_REG_LIST_DCN(id), \
-+	SRI(CM_COMA_C11_C12, CM, id),\
-+	SRI(CM_COMA_C33_C34, CM, id),\
-+	SRI(CM_COMB_C11_C12, CM, id),\
-+	SRI(CM_COMB_C33_C34, CM, id),\
-+	SRI(CM_OCSC_CONTROL, CM, id), \
-+	SRI(CM_OCSC_C11_C12, CM, id), \
-+	SRI(CM_OCSC_C33_C34, CM, id), \
-+	SRI(CM_BNS_VALUES_R, CM, id), \
-+	SRI(CM_BNS_VALUES_G, CM, id), \
-+	SRI(CM_BNS_VALUES_B, CM, id), \
-+	SRI(CM_MEM_PWR_CTRL, CM, id), \
-+	SRI(CM_RGAM_LUT_DATA, CM, id), \
-+	SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\
-+	SRI(CM_RGAM_LUT_INDEX, CM, id), \
-+	SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \
-+	SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \
-+	SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \
-+	SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \
-+	SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \
-+	SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \
-+	SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \
-+	SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \
-+	SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \
-+	SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \
-+	SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \
-+	SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \
-+	SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \
-+	SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \
-+	SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \
-+	SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \
-+	SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \
-+	SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \
-+	SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \
-+	SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \
-+	SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \
-+	SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \
-+	SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \
-+	SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \
-+	SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \
-+	SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \
-+	SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \
-+	SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \
-+	SRI(CM_RGAM_CONTROL, CM, id), \
-+	SRI(CM_IGAM_CONTROL, CM, id), \
-+	SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
-+	SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
-+	SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
-+	SRI(CURSOR_CONTROL, CURSOR, id), \
-+	SRI(CM_CMOUT_CONTROL, CM, id)
-+
-+
-+#define TF_REG_LIST_SH_MASK_DCN(mask_sh)\
-+	TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
-+	TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
-+	TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
-+	TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
-+	TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
-+	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
-+	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
-+	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\
-+	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\
-+	TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\
-+	TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
-+	TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
-+	TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
-+	TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
-+	TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\
-+	TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
-+	TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\
-+	TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\
-+	TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\
-+	TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
-+	TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\
-+	TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\
-+	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
-+	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
-+	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
-+	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\
-+	TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
-+	TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\
-+	TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\
-+	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
-+	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
-+	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
-+	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
-+	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
-+	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\
-+	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\
-+	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\
-+	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
-+	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
-+	TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
-+	TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
-+	TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\
-+	TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\
-+	TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\
-+	TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\
-+	TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
-+	TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
-+	TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\
-+	TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\
-+	TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\
-+	TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\
-+	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\
-+	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\
-+	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\
-+	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\
-+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\
-+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\
-+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\
-+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\
-+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\
-+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\
-+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\
-+	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\
-+	TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
-+	TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
-+	TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
-+	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
-+	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
-+	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
-+	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
-+	TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
-+	TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
-+	TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \
-+	TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
-+	TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
-+	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
-+	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
-+	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
-+	TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
-+	TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh)
-+
-+#define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\
-+	TF_REG_LIST_SH_MASK_DCN(mask_sh),\
-+	TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\
-+	TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\
-+	TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\
-+	TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\
-+	TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\
-+	TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh),\
-+	TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh),\
-+	TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh),\
-+	TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh),\
-+	TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh),\
-+	TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh),\
-+	TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\
-+	TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh),\
-+	TF_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \
-+	TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \
-+	TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
-+	TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
-+	TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \
-+	TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \
-+	TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \
-+	TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \
-+	TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_SCALE_R, mask_sh), \
-+	TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_SCALE_G, mask_sh), \
-+	TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_SCALE_B, mask_sh), \
-+	TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
-+	TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
-+	TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
-+	TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \
-+	TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \
-+	TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \
-+	TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \
-+	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \
-+	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \
-+	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \
-+	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \
-+	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \
-+	TF_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \
-+	TF_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \
-+	TF_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \
-+	TF_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh), \
-+	TF_SF(CM0_CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, mask_sh), \
-+	TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
-+	TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
-+	TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
-+	TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh)
-+
-+#define TF_REG_FIELD_LIST(type) \
-+	type EXT_OVERSCAN_LEFT; \
-+	type EXT_OVERSCAN_RIGHT; \
-+	type EXT_OVERSCAN_BOTTOM; \
-+	type EXT_OVERSCAN_TOP; \
-+	type OTG_H_BLANK_START; \
-+	type OTG_H_BLANK_END; \
-+	type OTG_V_BLANK_START; \
-+	type OTG_V_BLANK_END; \
-+	type PIXEL_DEPTH; \
-+	type PIXEL_EXPAN_MODE; \
-+	type PIXEL_REDUCE_MODE; \
-+	type DYNAMIC_PIXEL_DEPTH; \
-+	type DITHER_EN; \
-+	type INTERLEAVE_EN; \
-+	type LB_DATA_FORMAT__ALPHA_EN; \
-+	type MEMORY_CONFIG; \
-+	type LB_MAX_PARTITIONS; \
-+	type AUTOCAL_MODE; \
-+	type AUTOCAL_NUM_PIPE; \
-+	type AUTOCAL_PIPE_ID; \
-+	type SCL_BLACK_OFFSET_RGB_Y; \
-+	type SCL_BLACK_OFFSET_CBCR; \
-+	type SCL_V_NUM_TAPS; \
-+	type SCL_H_NUM_TAPS; \
-+	type SCL_V_NUM_TAPS_C; \
-+	type SCL_H_NUM_TAPS_C; \
-+	type SCL_COEF_RAM_TAP_PAIR_IDX; \
-+	type SCL_COEF_RAM_PHASE; \
-+	type SCL_COEF_RAM_FILTER_TYPE; \
-+	type SCL_COEF_RAM_EVEN_TAP_COEF; \
-+	type SCL_COEF_RAM_EVEN_TAP_COEF_EN; \
-+	type SCL_COEF_RAM_ODD_TAP_COEF; \
-+	type SCL_COEF_RAM_ODD_TAP_COEF_EN; \
-+	type SCL_H_2TAP_HARDCODE_COEF_EN; \
-+	type SCL_H_2TAP_SHARP_EN; \
-+	type SCL_H_2TAP_SHARP_FACTOR; \
-+	type SCL_V_2TAP_HARDCODE_COEF_EN; \
-+	type SCL_V_2TAP_SHARP_EN; \
-+	type SCL_V_2TAP_SHARP_FACTOR; \
-+	type SCL_COEF_RAM_SELECT; \
-+	type DSCL_MODE; \
-+	type RECOUT_START_X; \
-+	type RECOUT_START_Y; \
-+	type RECOUT_WIDTH; \
-+	type RECOUT_HEIGHT; \
-+	type MPC_WIDTH; \
-+	type MPC_HEIGHT; \
-+	type SCL_H_SCALE_RATIO; \
-+	type SCL_V_SCALE_RATIO; \
-+	type SCL_H_SCALE_RATIO_C; \
-+	type SCL_V_SCALE_RATIO_C; \
-+	type SCL_H_INIT_FRAC; \
-+	type SCL_H_INIT_INT; \
-+	type SCL_H_INIT_FRAC_C; \
-+	type SCL_H_INIT_INT_C; \
-+	type SCL_V_INIT_FRAC; \
-+	type SCL_V_INIT_INT; \
-+	type SCL_V_INIT_FRAC_BOT; \
-+	type SCL_V_INIT_INT_BOT; \
-+	type SCL_V_INIT_FRAC_C; \
-+	type SCL_V_INIT_INT_C; \
-+	type SCL_V_INIT_FRAC_BOT_C; \
-+	type SCL_V_INIT_INT_BOT_C; \
-+	type SCL_CHROMA_COEF_MODE; \
-+	type SCL_COEF_RAM_SELECT_CURRENT; \
-+	type CM_GAMUT_REMAP_MODE; \
-+	type CM_GAMUT_REMAP_C11; \
-+	type CM_GAMUT_REMAP_C12; \
-+	type CM_GAMUT_REMAP_C33; \
-+	type CM_GAMUT_REMAP_C34; \
-+	type CM_COMA_C11; \
-+	type CM_COMA_C12; \
-+	type CM_COMA_C33; \
-+	type CM_COMA_C34; \
-+	type CM_COMB_C11; \
-+	type CM_COMB_C12; \
-+	type CM_COMB_C33; \
-+	type CM_COMB_C34; \
-+	type CM_OCSC_MODE; \
-+	type CM_OCSC_C11; \
-+	type CM_OCSC_C12; \
-+	type CM_OCSC_C33; \
-+	type CM_OCSC_C34; \
-+	type RGAM_MEM_PWR_FORCE; \
-+	type CM_RGAM_LUT_DATA; \
-+	type CM_RGAM_LUT_WRITE_EN_MASK; \
-+	type CM_RGAM_LUT_WRITE_SEL; \
-+	type CM_RGAM_LUT_INDEX; \
-+	type CM_RGAM_RAMB_EXP_REGION_START_B; \
-+	type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
-+	type CM_RGAM_RAMB_EXP_REGION_START_G; \
-+	type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
-+	type CM_RGAM_RAMB_EXP_REGION_START_R; \
-+	type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
-+	type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
-+	type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
-+	type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
-+	type CM_RGAM_RAMB_EXP_REGION_END_B; \
-+	type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; \
-+	type CM_RGAM_RAMB_EXP_REGION_END_BASE_B; \
-+	type CM_RGAM_RAMB_EXP_REGION_END_G; \
-+	type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G; \
-+	type CM_RGAM_RAMB_EXP_REGION_END_BASE_G; \
-+	type CM_RGAM_RAMB_EXP_REGION_END_R; \
-+	type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R; \
-+	type CM_RGAM_RAMB_EXP_REGION_END_BASE_R; \
-+	type CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
-+	type CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
-+	type CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
-+	type CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
-+	type CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET; \
-+	type CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \
-+	type CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET; \
-+	type CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \
-+	type CM_RGAM_RAMA_EXP_REGION_START_B; \
-+	type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
-+	type CM_RGAM_RAMA_EXP_REGION_START_G; \
-+	type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
-+	type CM_RGAM_RAMA_EXP_REGION_START_R; \
-+	type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
-+	type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
-+	type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
-+	type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
-+	type CM_RGAM_RAMA_EXP_REGION_END_B; \
-+	type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B; \
-+	type CM_RGAM_RAMA_EXP_REGION_END_BASE_B; \
-+	type CM_RGAM_RAMA_EXP_REGION_END_G; \
-+	type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G; \
-+	type CM_RGAM_RAMA_EXP_REGION_END_BASE_G; \
-+	type CM_RGAM_RAMA_EXP_REGION_END_R; \
-+	type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R; \
-+	type CM_RGAM_RAMA_EXP_REGION_END_BASE_R; \
-+	type CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
-+	type CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
-+	type CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
-+	type CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
-+	type CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET; \
-+	type CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \
-+	type CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET; \
-+	type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
-+	type CM_RGAM_LUT_MODE; \
-+	type CM_CMOUT_ROUND_TRUNC_MODE; \
-+	type CM_BLNDGAM_LUT_MODE; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_START_B; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_START_G; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_START_R; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_END_B; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_END_G; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_END_R; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_START_B; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_START_G; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_START_R; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_END_B; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_END_G; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_END_R; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET; \
-+	type CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
-+	type CM_BLNDGAM_LUT_WRITE_EN_MASK; \
-+	type CM_BLNDGAM_LUT_WRITE_SEL; \
-+	type CM_BLNDGAM_LUT_INDEX; \
-+	type CM_BLNDGAM_LUT_DATA; \
-+	type CM_3DLUT_MODE; \
-+	type CM_3DLUT_SIZE; \
-+	type CM_3DLUT_INDEX; \
-+	type CM_3DLUT_DATA0; \
-+	type CM_3DLUT_DATA1; \
-+	type CM_3DLUT_DATA_30BIT; \
-+	type CM_3DLUT_WRITE_EN_MASK; \
-+	type CM_3DLUT_RAM_SEL; \
-+	type CM_3DLUT_30BIT_EN; \
-+	type CM_3DLUT_CONFIG_STATUS; \
-+	type CM_3DLUT_READ_SEL; \
-+	type CM_SHAPER_LUT_MODE; \
-+	type CM_SHAPER_RAMB_EXP_REGION_START_B; \
-+	type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B; \
-+	type CM_SHAPER_RAMB_EXP_REGION_START_G; \
-+	type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G; \
-+	type CM_SHAPER_RAMB_EXP_REGION_START_R; \
-+	type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R; \
-+	type CM_SHAPER_RAMB_EXP_REGION_END_B; \
-+	type CM_SHAPER_RAMB_EXP_REGION_END_BASE_B; \
-+	type CM_SHAPER_RAMB_EXP_REGION_END_G; \
-+	type CM_SHAPER_RAMB_EXP_REGION_END_BASE_G; \
-+	type CM_SHAPER_RAMB_EXP_REGION_END_R; \
-+	type CM_SHAPER_RAMB_EXP_REGION_END_BASE_R; \
-+	type CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET; \
-+	type CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION_START_B; \
-+	type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B; \
-+	type CM_SHAPER_RAMA_EXP_REGION_START_G; \
-+	type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G; \
-+	type CM_SHAPER_RAMA_EXP_REGION_START_R; \
-+	type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R; \
-+	type CM_SHAPER_RAMA_EXP_REGION_END_B; \
-+	type CM_SHAPER_RAMA_EXP_REGION_END_BASE_B; \
-+	type CM_SHAPER_RAMA_EXP_REGION_END_G; \
-+	type CM_SHAPER_RAMA_EXP_REGION_END_BASE_G; \
-+	type CM_SHAPER_RAMA_EXP_REGION_END_R; \
-+	type CM_SHAPER_RAMA_EXP_REGION_END_BASE_R; \
-+	type CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS; \
-+	type CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET; \
-+	type CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS; \
-+	type CM_SHAPER_LUT_WRITE_EN_MASK; \
-+	type CM_SHAPER_LUT_WRITE_SEL; \
-+	type CM_SHAPER_LUT_INDEX; \
-+	type CM_SHAPER_LUT_DATA; \
-+	type CM_DGAM_CONFIG_STATUS; \
-+	type CM_ICSC_MODE; \
-+	type CM_ICSC_C11; \
-+	type CM_ICSC_C12; \
-+	type CM_ICSC_C33; \
-+	type CM_ICSC_C34; \
-+	type CM_BNS_BIAS_R; \
-+	type CM_BNS_BIAS_G; \
-+	type CM_BNS_BIAS_B; \
-+	type CM_BNS_SCALE_R; \
-+	type CM_BNS_SCALE_G; \
-+	type CM_BNS_SCALE_B; \
-+	type CM_DGAM_RAMB_EXP_REGION_START_B; \
-+	type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
-+	type CM_DGAM_RAMB_EXP_REGION_START_G; \
-+	type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
-+	type CM_DGAM_RAMB_EXP_REGION_START_R; \
-+	type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
-+	type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
-+	type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
-+	type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
-+	type CM_DGAM_RAMB_EXP_REGION_END_B; \
-+	type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; \
-+	type CM_DGAM_RAMB_EXP_REGION_END_BASE_B; \
-+	type CM_DGAM_RAMB_EXP_REGION_END_G; \
-+	type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G; \
-+	type CM_DGAM_RAMB_EXP_REGION_END_BASE_G; \
-+	type CM_DGAM_RAMB_EXP_REGION_END_R; \
-+	type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R; \
-+	type CM_DGAM_RAMB_EXP_REGION_END_BASE_R; \
-+	type CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
-+	type CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
-+	type CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
-+	type CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
-+	type CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
-+	type CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
-+	type CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
-+	type CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
-+	type CM_DGAM_RAMA_EXP_REGION_START_B; \
-+	type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
-+	type CM_DGAM_RAMA_EXP_REGION_START_G; \
-+	type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
-+	type CM_DGAM_RAMA_EXP_REGION_START_R; \
-+	type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
-+	type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
-+	type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
-+	type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
-+	type CM_DGAM_RAMA_EXP_REGION_END_B; \
-+	type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B; \
-+	type CM_DGAM_RAMA_EXP_REGION_END_BASE_B; \
-+	type CM_DGAM_RAMA_EXP_REGION_END_G; \
-+	type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G; \
-+	type CM_DGAM_RAMA_EXP_REGION_END_BASE_G; \
-+	type CM_DGAM_RAMA_EXP_REGION_END_R; \
-+	type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R; \
-+	type CM_DGAM_RAMA_EXP_REGION_END_BASE_R; \
-+	type CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
-+	type CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
-+	type CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
-+	type CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
-+	type CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
-+	type CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
-+	type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
-+	type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
-+	type SHARED_MEM_PWR_DIS; \
-+	type CM_IGAM_LUT_FORMAT_R; \
-+	type CM_IGAM_LUT_FORMAT_G; \
-+	type CM_IGAM_LUT_FORMAT_B; \
-+	type CM_IGAM_LUT_HOST_EN; \
-+	type CM_IGAM_LUT_RW_MODE; \
-+	type CM_IGAM_LUT_WRITE_EN_MASK; \
-+	type CM_IGAM_LUT_SEL; \
-+	type CM_IGAM_LUT_SEQ_COLOR; \
-+	type CM_IGAM_DGAM_CONFIG_STATUS; \
-+	type CM_DGAM_LUT_WRITE_EN_MASK; \
-+	type CM_DGAM_LUT_WRITE_SEL; \
-+	type CM_DGAM_LUT_INDEX; \
-+	type CM_DGAM_LUT_DATA; \
-+	type CM_DGAM_LUT_MODE; \
-+	type CM_IGAM_LUT_MODE; \
-+	type CM_IGAM_INPUT_FORMAT; \
-+	type CM_IGAM_LUT_RW_INDEX; \
-+	type CM_BYPASS_EN; \
-+	type FORMAT_EXPANSION_MODE; \
-+	type CNVC_BYPASS; \
-+	type OUTPUT_FP; \
-+	type CNVC_SURFACE_PIXEL_FORMAT; \
-+	type CURSOR_MODE; \
-+	type CURSOR_PITCH; \
-+	type CURSOR_LINES_PER_CHUNK; \
-+	type CURSOR_ENABLE; \
-+	type CUR0_MODE; \
-+	type CUR0_EXPANSION_MODE; \
-+	type CUR0_ENABLE; \
-+	type CM_BYPASS; \
-+	type FORMAT_CONTROL__ALPHA_EN; \
-+	type CUR0_COLOR0; \
-+	type CUR0_COLOR1
-+
-+
-+
-+struct dcn_dpp_shift {
-+	TF_REG_FIELD_LIST(uint8_t);
-+};
-+
-+struct dcn_dpp_mask {
-+	TF_REG_FIELD_LIST(uint32_t);
-+};
-+
-+
-+
-+
-+struct dcn_dpp_registers {
-+	uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT;
-+	uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM;
-+	uint32_t OTG_H_BLANK;
-+	uint32_t OTG_V_BLANK;
-+	uint32_t SCL_MODE;
-+	uint32_t LB_DATA_FORMAT;
-+	uint32_t LB_MEMORY_CTRL;
-+	uint32_t DSCL_AUTOCAL;
-+	uint32_t SCL_BLACK_OFFSET;
-+	uint32_t SCL_TAP_CONTROL;
-+	uint32_t SCL_COEF_RAM_TAP_SELECT;
-+	uint32_t SCL_COEF_RAM_TAP_DATA;
-+	uint32_t DSCL_2TAP_CONTROL;
-+	uint32_t MPC_SIZE;
-+	uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
-+	uint32_t SCL_VERT_FILTER_SCALE_RATIO;
-+	uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C;
-+	uint32_t SCL_VERT_FILTER_SCALE_RATIO_C;
-+	uint32_t SCL_HORZ_FILTER_INIT;
-+	uint32_t SCL_HORZ_FILTER_INIT_C;
-+	uint32_t SCL_VERT_FILTER_INIT;
-+	uint32_t SCL_VERT_FILTER_INIT_BOT;
-+	uint32_t SCL_VERT_FILTER_INIT_C;
-+	uint32_t SCL_VERT_FILTER_INIT_BOT_C;
-+	uint32_t RECOUT_START;
-+	uint32_t RECOUT_SIZE;
-+	uint32_t CM_GAMUT_REMAP_CONTROL;
-+	uint32_t CM_GAMUT_REMAP_C11_C12;
-+	uint32_t CM_GAMUT_REMAP_C33_C34;
-+	uint32_t CM_COMA_C11_C12;
-+	uint32_t CM_COMA_C33_C34;
-+	uint32_t CM_COMB_C11_C12;
-+	uint32_t CM_COMB_C33_C34;
-+	uint32_t CM_OCSC_CONTROL;
-+	uint32_t CM_OCSC_C11_C12;
-+	uint32_t CM_OCSC_C33_C34;
-+	uint32_t CM_MEM_PWR_CTRL;
-+	uint32_t CM_RGAM_LUT_DATA;
-+	uint32_t CM_RGAM_LUT_WRITE_EN_MASK;
-+	uint32_t CM_RGAM_LUT_INDEX;
-+	uint32_t CM_RGAM_RAMB_START_CNTL_B;
-+	uint32_t CM_RGAM_RAMB_START_CNTL_G;
-+	uint32_t CM_RGAM_RAMB_START_CNTL_R;
-+	uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B;
-+	uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G;
-+	uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R;
-+	uint32_t CM_RGAM_RAMB_END_CNTL1_B;
-+	uint32_t CM_RGAM_RAMB_END_CNTL2_B;
-+	uint32_t CM_RGAM_RAMB_END_CNTL1_G;
-+	uint32_t CM_RGAM_RAMB_END_CNTL2_G;
-+	uint32_t CM_RGAM_RAMB_END_CNTL1_R;
-+	uint32_t CM_RGAM_RAMB_END_CNTL2_R;
-+	uint32_t CM_RGAM_RAMB_REGION_0_1;
-+	uint32_t CM_RGAM_RAMB_REGION_32_33;
-+	uint32_t CM_RGAM_RAMA_START_CNTL_B;
-+	uint32_t CM_RGAM_RAMA_START_CNTL_G;
-+	uint32_t CM_RGAM_RAMA_START_CNTL_R;
-+	uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B;
-+	uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G;
-+	uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R;
-+	uint32_t CM_RGAM_RAMA_END_CNTL1_B;
-+	uint32_t CM_RGAM_RAMA_END_CNTL2_B;
-+	uint32_t CM_RGAM_RAMA_END_CNTL1_G;
-+	uint32_t CM_RGAM_RAMA_END_CNTL2_G;
-+	uint32_t CM_RGAM_RAMA_END_CNTL1_R;
-+	uint32_t CM_RGAM_RAMA_END_CNTL2_R;
-+	uint32_t CM_RGAM_RAMA_REGION_0_1;
-+	uint32_t CM_RGAM_RAMA_REGION_32_33;
-+	uint32_t CM_RGAM_CONTROL;
-+	uint32_t CM_CMOUT_CONTROL;
-+	uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK;
-+	uint32_t CM_BLNDGAM_CONTROL;
-+	uint32_t CM_BLNDGAM_RAMB_START_CNTL_B;
-+	uint32_t CM_BLNDGAM_RAMB_START_CNTL_G;
-+	uint32_t CM_BLNDGAM_RAMB_START_CNTL_R;
-+	uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B;
-+	uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G;
-+	uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R;
-+	uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B;
-+	uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B;
-+	uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G;
-+	uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G;
-+	uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R;
-+	uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_0_1;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_2_3;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_4_5;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_6_7;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_8_9;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_10_11;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_12_13;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_14_15;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_16_17;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_18_19;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_20_21;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_22_23;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_24_25;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_26_27;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_28_29;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_30_31;
-+	uint32_t CM_BLNDGAM_RAMB_REGION_32_33;
-+	uint32_t CM_BLNDGAM_RAMA_START_CNTL_B;
-+	uint32_t CM_BLNDGAM_RAMA_START_CNTL_G;
-+	uint32_t CM_BLNDGAM_RAMA_START_CNTL_R;
-+	uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B;
-+	uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G;
-+	uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R;
-+	uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B;
-+	uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B;
-+	uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G;
-+	uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G;
-+	uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R;
-+	uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_0_1;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_2_3;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_4_5;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_6_7;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_8_9;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_10_11;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_12_13;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_14_15;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_16_17;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_18_19;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_20_21;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_22_23;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_24_25;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_26_27;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_28_29;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_30_31;
-+	uint32_t CM_BLNDGAM_RAMA_REGION_32_33;
-+	uint32_t CM_BLNDGAM_LUT_INDEX;
-+	uint32_t CM_BLNDGAM_LUT_DATA;
-+	uint32_t CM_3DLUT_MODE;
-+	uint32_t CM_3DLUT_INDEX;
-+	uint32_t CM_3DLUT_DATA;
-+	uint32_t CM_3DLUT_DATA_30BIT;
-+	uint32_t CM_3DLUT_READ_WRITE_CONTROL;
-+	uint32_t CM_SHAPER_LUT_WRITE_EN_MASK;
-+	uint32_t CM_SHAPER_CONTROL;
-+	uint32_t CM_SHAPER_RAMB_START_CNTL_B;
-+	uint32_t CM_SHAPER_RAMB_START_CNTL_G;
-+	uint32_t CM_SHAPER_RAMB_START_CNTL_R;
-+	uint32_t CM_SHAPER_RAMB_END_CNTL_B;
-+	uint32_t CM_SHAPER_RAMB_END_CNTL_G;
-+	uint32_t CM_SHAPER_RAMB_END_CNTL_R;
-+	uint32_t CM_SHAPER_RAMB_REGION_0_1;
-+	uint32_t CM_SHAPER_RAMB_REGION_2_3;
-+	uint32_t CM_SHAPER_RAMB_REGION_4_5;
-+	uint32_t CM_SHAPER_RAMB_REGION_6_7;
-+	uint32_t CM_SHAPER_RAMB_REGION_8_9;
-+	uint32_t CM_SHAPER_RAMB_REGION_10_11;
-+	uint32_t CM_SHAPER_RAMB_REGION_12_13;
-+	uint32_t CM_SHAPER_RAMB_REGION_14_15;
-+	uint32_t CM_SHAPER_RAMB_REGION_16_17;
-+	uint32_t CM_SHAPER_RAMB_REGION_18_19;
-+	uint32_t CM_SHAPER_RAMB_REGION_20_21;
-+	uint32_t CM_SHAPER_RAMB_REGION_22_23;
-+	uint32_t CM_SHAPER_RAMB_REGION_24_25;
-+	uint32_t CM_SHAPER_RAMB_REGION_26_27;
-+	uint32_t CM_SHAPER_RAMB_REGION_28_29;
-+	uint32_t CM_SHAPER_RAMB_REGION_30_31;
-+	uint32_t CM_SHAPER_RAMB_REGION_32_33;
-+	uint32_t CM_SHAPER_RAMA_START_CNTL_B;
-+	uint32_t CM_SHAPER_RAMA_START_CNTL_G;
-+	uint32_t CM_SHAPER_RAMA_START_CNTL_R;
-+	uint32_t CM_SHAPER_RAMA_END_CNTL_B;
-+	uint32_t CM_SHAPER_RAMA_END_CNTL_G;
-+	uint32_t CM_SHAPER_RAMA_END_CNTL_R;
-+	uint32_t CM_SHAPER_RAMA_REGION_0_1;
-+	uint32_t CM_SHAPER_RAMA_REGION_2_3;
-+	uint32_t CM_SHAPER_RAMA_REGION_4_5;
-+	uint32_t CM_SHAPER_RAMA_REGION_6_7;
-+	uint32_t CM_SHAPER_RAMA_REGION_8_9;
-+	uint32_t CM_SHAPER_RAMA_REGION_10_11;
-+	uint32_t CM_SHAPER_RAMA_REGION_12_13;
-+	uint32_t CM_SHAPER_RAMA_REGION_14_15;
-+	uint32_t CM_SHAPER_RAMA_REGION_16_17;
-+	uint32_t CM_SHAPER_RAMA_REGION_18_19;
-+	uint32_t CM_SHAPER_RAMA_REGION_20_21;
-+	uint32_t CM_SHAPER_RAMA_REGION_22_23;
-+	uint32_t CM_SHAPER_RAMA_REGION_24_25;
-+	uint32_t CM_SHAPER_RAMA_REGION_26_27;
-+	uint32_t CM_SHAPER_RAMA_REGION_28_29;
-+	uint32_t CM_SHAPER_RAMA_REGION_30_31;
-+	uint32_t CM_SHAPER_RAMA_REGION_32_33;
-+	uint32_t CM_SHAPER_LUT_INDEX;
-+	uint32_t CM_SHAPER_LUT_DATA;
-+	uint32_t CM_ICSC_CONTROL;
-+	uint32_t CM_ICSC_C11_C12;
-+	uint32_t CM_ICSC_C33_C34;
-+	uint32_t CM_BNS_VALUES_R;
-+	uint32_t CM_BNS_VALUES_G;
-+	uint32_t CM_BNS_VALUES_B;
-+	uint32_t CM_DGAM_RAMB_START_CNTL_B;
-+	uint32_t CM_DGAM_RAMB_START_CNTL_G;
-+	uint32_t CM_DGAM_RAMB_START_CNTL_R;
-+	uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B;
-+	uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G;
-+	uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R;
-+	uint32_t CM_DGAM_RAMB_END_CNTL1_B;
-+	uint32_t CM_DGAM_RAMB_END_CNTL2_B;
-+	uint32_t CM_DGAM_RAMB_END_CNTL1_G;
-+	uint32_t CM_DGAM_RAMB_END_CNTL2_G;
-+	uint32_t CM_DGAM_RAMB_END_CNTL1_R;
-+	uint32_t CM_DGAM_RAMB_END_CNTL2_R;
-+	uint32_t CM_DGAM_RAMB_REGION_0_1;
-+	uint32_t CM_DGAM_RAMB_REGION_14_15;
-+	uint32_t CM_DGAM_RAMA_START_CNTL_B;
-+	uint32_t CM_DGAM_RAMA_START_CNTL_G;
-+	uint32_t CM_DGAM_RAMA_START_CNTL_R;
-+	uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B;
-+	uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G;
-+	uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R;
-+	uint32_t CM_DGAM_RAMA_END_CNTL1_B;
-+	uint32_t CM_DGAM_RAMA_END_CNTL2_B;
-+	uint32_t CM_DGAM_RAMA_END_CNTL1_G;
-+	uint32_t CM_DGAM_RAMA_END_CNTL2_G;
-+	uint32_t CM_DGAM_RAMA_END_CNTL1_R;
-+	uint32_t CM_DGAM_RAMA_END_CNTL2_R;
-+	uint32_t CM_DGAM_RAMA_REGION_0_1;
-+	uint32_t CM_DGAM_RAMA_REGION_14_15;
-+	uint32_t CM_DGAM_LUT_WRITE_EN_MASK;
-+	uint32_t CM_DGAM_LUT_INDEX;
-+	uint32_t CM_DGAM_LUT_DATA;
-+	uint32_t CM_CONTROL;
-+	uint32_t CM_DGAM_CONTROL;
-+	uint32_t CM_IGAM_CONTROL;
-+	uint32_t CM_IGAM_LUT_RW_CONTROL;
-+	uint32_t CM_IGAM_LUT_RW_INDEX;
-+	uint32_t CM_IGAM_LUT_SEQ_COLOR;
-+	uint32_t FORMAT_CONTROL;
-+	uint32_t CNVC_SURFACE_PIXEL_FORMAT;
-+	uint32_t CURSOR_CONTROL;
-+	uint32_t CURSOR0_CONTROL;
-+	uint32_t CURSOR0_COLOR0;
-+	uint32_t CURSOR0_COLOR1;
-+};
-+
-+struct dcn10_dpp {
-+	struct dpp base;
-+
-+	const struct dcn_dpp_registers *tf_regs;
-+	const struct dcn_dpp_shift *tf_shift;
-+	const struct dcn_dpp_mask *tf_mask;
-+
-+	const uint16_t *filter_v;
-+	const uint16_t *filter_h;
-+	const uint16_t *filter_v_c;
-+	const uint16_t *filter_h_c;
-+	int lb_pixel_depth_supported;
-+	int lb_memory_size;
-+	int lb_bits_per_entry;
-+	bool is_write_to_ram_a_safe;
-+	struct scaler_data scl_data;
-+	struct pwl_params pwl_data;
-+};
-+
-+enum dcn10_input_csc_select {
-+	INPUT_CSC_SELECT_BYPASS = 0,
-+	INPUT_CSC_SELECT_ICSC,
-+	INPUT_CSC_SELECT_COMA
-+};
-+
-+bool dpp1_dscl_is_lb_conf_valid(
-+		int ceil_vratio,
-+		int num_partitions,
-+		int vtaps);
-+
-+void dpp1_dscl_calc_lb_num_partitions(
-+		const struct scaler_data *scl_data,
-+		enum lb_memory_config lb_config,
-+		int *num_part_y,
-+		int *num_part_c);
-+
-+void dpp1_degamma_ram_select(
-+		struct dpp *dpp_base,
-+							bool use_ram_a);
-+
-+void dpp1_program_degamma_luta_settings(
-+		struct dpp *dpp_base,
-+		const struct pwl_params *params);
-+
-+void dpp1_program_degamma_lutb_settings(
-+		struct dpp *dpp_base,
-+		const struct pwl_params *params);
-+
-+void dpp1_program_degamma_lut(
-+		struct dpp *dpp_base,
-+		const struct pwl_result_data *rgb,
-+		uint32_t num,
-+		bool is_ram_a);
-+
-+void dpp1_power_on_degamma_lut(
-+		struct dpp *dpp_base,
-+	bool power_on);
-+
-+void dpp1_program_input_csc(
-+		struct dpp *dpp_base,
-+		enum dc_color_space color_space,
-+		enum dcn10_input_csc_select select,
-+		const struct out_csc_color_matrix *tbl_entry);
-+
-+void dpp1_program_bias_and_scale(
-+		struct dpp *dpp_base,
-+		struct dc_bias_and_scale *params);
-+
-+void dpp1_program_input_lut(
-+		struct dpp *dpp_base,
-+		const struct dc_gamma *gamma);
-+
-+void dpp1_full_bypass(struct dpp *dpp_base);
-+
-+void dpp1_set_degamma(
-+		struct dpp *dpp_base,
-+		enum ipp_degamma_mode mode);
-+
-+void dpp1_set_degamma_pwl(struct dpp *dpp_base,
-+								 const struct pwl_params *params);
-+
-+bool dpp_get_optimal_number_of_taps(
-+		struct dpp *dpp,
-+		struct scaler_data *scl_data,
-+		const struct scaling_taps *in_taps);
-+
-+void dpp_reset(struct dpp *dpp_base);
-+
-+void dpp1_cm_program_regamma_lut(
-+		struct dpp *dpp_base,
-+		const struct pwl_result_data *rgb,
-+		uint32_t num);
-+
-+void dpp1_cm_power_on_regamma_lut(
-+	struct dpp *dpp_base,
-+	bool power_on);
-+
-+void dpp1_cm_configure_regamma_lut(
-+		struct dpp *dpp_base,
-+		bool is_ram_a);
-+
-+/*program re gamma RAM A*/
-+void dpp1_cm_program_regamma_luta_settings(
-+		struct dpp *dpp_base,
-+		const struct pwl_params *params);
-+
-+/*program re gamma RAM B*/
-+void dpp1_cm_program_regamma_lutb_settings(
-+		struct dpp *dpp_base,
-+		const struct pwl_params *params);
-+void dpp1_cm_set_output_csc_adjustment(
-+		struct dpp *dpp_base,
-+		const struct out_csc_color_matrix *tbl_entry);
-+
-+void dpp1_cm_set_output_csc_default(
-+		struct dpp *dpp_base,
-+		enum dc_color_space colorspace);
-+
-+void dpp1_cm_set_gamut_remap(
-+	struct dpp *dpp,
-+	const struct dpp_grph_csc_adjustment *adjust);
-+
-+void dpp1_dscl_set_scaler_manual_scale(
-+	struct dpp *dpp_base,
-+	const struct scaler_data *scl_data);
-+
-+void dpp1_cnv_setup (
-+		struct dpp *dpp_base,
-+		enum surface_pixel_format format,
-+		enum expansion_mode mode,
-+		struct csc_transform input_csc_color_matrix,
-+		enum dc_color_space input_color_space);
-+
-+void dpp1_full_bypass(struct dpp *dpp_base);
-+
-+void dpp1_construct(struct dcn10_dpp *dpp1,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dcn_dpp_registers *tf_regs,
-+	const struct dcn_dpp_shift *tf_shift,
-+	const struct dcn_dpp_mask *tf_mask);
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c.0130~	2017-12-14 06:39:58.421903572 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c	2017-12-14 06:39:58.421903572 +0100
-@@ -0,0 +1,516 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dcn10_hubp.h"
-+#include "dcn10_hubbub.h"
-+#include "reg_helper.h"
-+
-+#define CTX \
-+	hubbub->ctx
-+#define REG(reg)\
-+	hubbub->regs->reg
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	hubbub->shifts->field_name, hubbub->masks->field_name
-+
-+void hubbub1_wm_read_state(struct hubbub *hubbub,
-+		struct dcn_hubbub_wm *wm)
-+{
-+	struct dcn_hubbub_wm_set *s;
-+
-+	memset(wm, 0, sizeof(struct dcn_hubbub_wm));
-+
-+	s = &wm->sets[0];
-+	s->wm_set = 0;
-+	s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
-+	s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
-+	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
-+		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
-+		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
-+	}
-+	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
-+
-+	s = &wm->sets[1];
-+	s->wm_set = 1;
-+	s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
-+	s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
-+	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
-+		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
-+		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
-+	}
-+	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
-+
-+	s = &wm->sets[2];
-+	s->wm_set = 2;
-+	s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
-+	s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
-+	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
-+		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
-+		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
-+	}
-+	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
-+
-+	s = &wm->sets[3];
-+	s->wm_set = 3;
-+	s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
-+	s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
-+	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
-+		s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
-+		s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
-+	}
-+	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
-+}
-+
-+bool hubbub1_verify_allow_pstate_change_high(
-+	struct hubbub *hubbub)
-+{
-+	/* pstate latency is ~20us so if we wait over 40us and pstate allow
-+	 * still not asserted, we are probably stuck and going to hang
-+	 *
-+	 * TODO: Figure out why it takes ~100us on linux
-+	 * pstate takes around ~100us on linux. Unknown currently as to
-+	 * why it takes that long on linux
-+	 */
-+	static unsigned int pstate_wait_timeout_us = 200;
-+	static unsigned int pstate_wait_expected_timeout_us = 40;
-+	static unsigned int max_sampled_pstate_wait_us; /* data collection */
-+	static bool forced_pstate_allow; /* help with revert wa */
-+
-+	unsigned int debug_index = 0x7;
-+	unsigned int debug_data;
-+	unsigned int i;
-+
-+	if (forced_pstate_allow) {
-+		/* we hacked to force pstate allow to prevent hang last time
-+		 * we verify_allow_pstate_change_high.  so disable force
-+		 * here so we can check status
-+		 */
-+		REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
-+			     DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 0,
-+			     DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 0);
-+		forced_pstate_allow = false;
-+	}
-+
-+	/* description "3-0:   Pipe0 cursor0 QOS
-+	 * 7-4:   Pipe1 cursor0 QOS
-+	 * 11-8:  Pipe2 cursor0 QOS
-+	 * 15-12: Pipe3 cursor0 QOS
-+	 * 16:    Pipe0 Plane0 Allow Pstate Change
-+	 * 17:    Pipe1 Plane0 Allow Pstate Change
-+	 * 18:    Pipe2 Plane0 Allow Pstate Change
-+	 * 19:    Pipe3 Plane0 Allow Pstate Change
-+	 * 20:    Pipe0 Plane1 Allow Pstate Change
-+	 * 21:    Pipe1 Plane1 Allow Pstate Change
-+	 * 22:    Pipe2 Plane1 Allow Pstate Change
-+	 * 23:    Pipe3 Plane1 Allow Pstate Change
-+	 * 24:    Pipe0 cursor0 Allow Pstate Change
-+	 * 25:    Pipe1 cursor0 Allow Pstate Change
-+	 * 26:    Pipe2 cursor0 Allow Pstate Change
-+	 * 27:    Pipe3 cursor0 Allow Pstate Change
-+	 * 28:    WB0 Allow Pstate Change
-+	 * 29:    WB1 Allow Pstate Change
-+	 * 30:    Arbiter's allow_pstate_change
-+	 * 31:    SOC pstate change request
-+	 */
-+
-+	REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, debug_index);
-+
-+	for (i = 0; i < pstate_wait_timeout_us; i++) {
-+		debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
-+
-+		if (debug_data & (1 << 30)) {
-+
-+			if (i > pstate_wait_expected_timeout_us)
-+				dm_logger_write(hubbub->ctx->logger, LOG_WARNING,
-+						"pstate took longer than expected ~%dus\n",
-+						i);
-+
-+			return true;
-+		}
-+		if (max_sampled_pstate_wait_us < i)
-+			max_sampled_pstate_wait_us = i;
-+
-+		udelay(1);
-+	}
-+
-+	/* force pstate allow to prevent system hang
-+	 * and break to debugger to investigate
-+	 */
-+	REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
-+		     DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 1,
-+		     DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1);
-+	forced_pstate_allow = true;
-+
-+	dm_logger_write(hubbub->ctx->logger, LOG_WARNING,
-+			"pstate TEST_DEBUG_DATA: 0x%X\n",
-+			debug_data);
-+
-+	return false;
-+}
-+
-+static uint32_t convert_and_clamp(
-+	uint32_t wm_ns,
-+	uint32_t refclk_mhz,
-+	uint32_t clamp_value)
-+{
-+	uint32_t ret_val = 0;
-+	ret_val = wm_ns * refclk_mhz;
-+	ret_val /= 1000;
-+
-+	if (ret_val > clamp_value)
-+		ret_val = clamp_value;
-+
-+	return ret_val;
-+}
-+
-+
-+void hubbub1_program_watermarks(
-+		struct hubbub *hubbub,
-+		struct dcn_watermark_set *watermarks,
-+		unsigned int refclk_mhz)
-+{
-+	uint32_t force_en = hubbub->ctx->dc->debug.disable_stutter ? 1 : 0;
-+	/*
-+	 * Need to clamp to max of the register values (i.e. no wrap)
-+	 * for dcn1, all wm registers are 21-bit wide
-+	 */
-+	uint32_t prog_wm_value;
-+
-+	REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
-+			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
-+
-+	/* Repeat for water mark set A, B, C and D. */
-+	/* clock state A */
-+	prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
-+			refclk_mhz, 0x1fffff);
-+	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
-+
-+	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"URGENCY_WATERMARK_A calculated =%d\n"
-+		"HW register value = 0x%x\n",
-+		watermarks->a.urgent_ns, prog_wm_value);
-+
-+	prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
-+			refclk_mhz, 0x1fffff);
-+	REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
-+	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
-+		"HW register value = 0x%x\n",
-+		watermarks->a.pte_meta_urgent_ns, prog_wm_value);
-+
-+	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
-+		prog_wm_value = convert_and_clamp(
-+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
-+				refclk_mhz, 0x1fffff);
-+		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
-+		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
-+			"HW register value = 0x%x\n",
-+			watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
-+
-+
-+		prog_wm_value = convert_and_clamp(
-+				watermarks->a.cstate_pstate.cstate_exit_ns,
-+				refclk_mhz, 0x1fffff);
-+		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
-+		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"SR_EXIT_WATERMARK_A calculated =%d\n"
-+			"HW register value = 0x%x\n",
-+			watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
-+	}
-+
-+	prog_wm_value = convert_and_clamp(
-+			watermarks->a.cstate_pstate.pstate_change_ns,
-+			refclk_mhz, 0x1fffff);
-+	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
-+	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
-+		"HW register value = 0x%x\n\n",
-+		watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
-+
-+
-+	/* clock state B */
-+	prog_wm_value = convert_and_clamp(
-+			watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);
-+	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
-+	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"URGENCY_WATERMARK_B calculated =%d\n"
-+		"HW register value = 0x%x\n",
-+		watermarks->b.urgent_ns, prog_wm_value);
-+
-+
-+	prog_wm_value = convert_and_clamp(
-+			watermarks->b.pte_meta_urgent_ns,
-+			refclk_mhz, 0x1fffff);
-+	REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
-+	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
-+		"HW register value = 0x%x\n",
-+		watermarks->b.pte_meta_urgent_ns, prog_wm_value);
-+
-+
-+	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
-+		prog_wm_value = convert_and_clamp(
-+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
-+				refclk_mhz, 0x1fffff);
-+		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
-+		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"SR_ENTER_WATERMARK_B calculated =%d\n"
-+			"HW register value = 0x%x\n",
-+			watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
-+
-+
-+		prog_wm_value = convert_and_clamp(
-+				watermarks->b.cstate_pstate.cstate_exit_ns,
-+				refclk_mhz, 0x1fffff);
-+		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
-+		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"SR_EXIT_WATERMARK_B calculated =%d\n"
-+			"HW register value = 0x%x\n",
-+			watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
-+	}
-+
-+	prog_wm_value = convert_and_clamp(
-+			watermarks->b.cstate_pstate.pstate_change_ns,
-+			refclk_mhz, 0x1fffff);
-+	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
-+	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"
-+		"HW register value = 0x%x\n",
-+		watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
-+
-+	/* clock state C */
-+	prog_wm_value = convert_and_clamp(
-+			watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);
-+	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
-+	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"URGENCY_WATERMARK_C calculated =%d\n"
-+		"HW register value = 0x%x\n",
-+		watermarks->c.urgent_ns, prog_wm_value);
-+
-+
-+	prog_wm_value = convert_and_clamp(
-+			watermarks->c.pte_meta_urgent_ns,
-+			refclk_mhz, 0x1fffff);
-+	REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
-+	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
-+		"HW register value = 0x%x\n",
-+		watermarks->c.pte_meta_urgent_ns, prog_wm_value);
-+
-+
-+	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
-+		prog_wm_value = convert_and_clamp(
-+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
-+				refclk_mhz, 0x1fffff);
-+		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
-+		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"SR_ENTER_WATERMARK_C calculated =%d\n"
-+			"HW register value = 0x%x\n",
-+			watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
-+
-+
-+		prog_wm_value = convert_and_clamp(
-+				watermarks->c.cstate_pstate.cstate_exit_ns,
-+				refclk_mhz, 0x1fffff);
-+		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
-+		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"SR_EXIT_WATERMARK_C calculated =%d\n"
-+			"HW register value = 0x%x\n",
-+			watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
-+	}
-+
-+	prog_wm_value = convert_and_clamp(
-+			watermarks->c.cstate_pstate.pstate_change_ns,
-+			refclk_mhz, 0x1fffff);
-+	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
-+	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"
-+		"HW register value = 0x%x\n",
-+		watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
-+
-+	/* clock state D */
-+	prog_wm_value = convert_and_clamp(
-+			watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);
-+	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
-+	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"URGENCY_WATERMARK_D calculated =%d\n"
-+		"HW register value = 0x%x\n",
-+		watermarks->d.urgent_ns, prog_wm_value);
-+
-+	prog_wm_value = convert_and_clamp(
-+			watermarks->d.pte_meta_urgent_ns,
-+			refclk_mhz, 0x1fffff);
-+	REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
-+	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
-+		"HW register value = 0x%x\n",
-+		watermarks->d.pte_meta_urgent_ns, prog_wm_value);
-+
-+
-+	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
-+		prog_wm_value = convert_and_clamp(
-+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
-+				refclk_mhz, 0x1fffff);
-+		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
-+		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"SR_ENTER_WATERMARK_D calculated =%d\n"
-+			"HW register value = 0x%x\n",
-+			watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
-+
-+
-+		prog_wm_value = convert_and_clamp(
-+				watermarks->d.cstate_pstate.cstate_exit_ns,
-+				refclk_mhz, 0x1fffff);
-+		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
-+		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"SR_EXIT_WATERMARK_D calculated =%d\n"
-+			"HW register value = 0x%x\n",
-+			watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
-+	}
-+
-+
-+	prog_wm_value = convert_and_clamp(
-+			watermarks->d.cstate_pstate.pstate_change_ns,
-+			refclk_mhz, 0x1fffff);
-+	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
-+	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
-+		"DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
-+		"HW register value = 0x%x\n\n",
-+		watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
-+
-+	REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
-+			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
-+
-+	REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
-+			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
-+	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
-+			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
-+
-+	REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
-+			DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
-+			DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
-+
-+#if 0
-+	REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
-+			DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,
-+			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
-+#endif
-+}
-+
-+void hubbub1_update_dchub(
-+	struct hubbub *hubbub,
-+	struct dchub_init_data *dh_data)
-+{
-+	/* TODO: port code from dal2 */
-+	switch (dh_data->fb_mode) {
-+	case FRAME_BUFFER_MODE_ZFB_ONLY:
-+		/*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
-+		REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
-+				SDPIF_FB_TOP, 0);
-+
-+		REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
-+				SDPIF_FB_BASE, 0x0FFFF);
-+
-+		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
-+				SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
-+
-+		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
-+				SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
-+
-+		REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
-+				SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
-+						dh_data->zfb_size_in_byte - 1) >> 22);
-+		break;
-+	case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
-+		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
-+
-+		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
-+				SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
-+
-+		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
-+				SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
-+
-+		REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
-+				SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
-+						dh_data->zfb_size_in_byte - 1) >> 22);
-+		break;
-+	case FRAME_BUFFER_MODE_LOCAL_ONLY:
-+		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
-+		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
-+				SDPIF_AGP_BASE, 0);
-+
-+		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
-+				SDPIF_AGP_BOT, 0X03FFFF);
-+
-+		REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
-+				SDPIF_AGP_TOP, 0);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	dh_data->dchub_initialzied = true;
-+	dh_data->dchub_info_valid = false;
-+}
-+
-+void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub)
-+{
-+	uint32_t watermark_change_req;
-+
-+	REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
-+			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, &watermark_change_req);
-+
-+	if (watermark_change_req)
-+		watermark_change_req = 0;
-+	else
-+		watermark_change_req = 1;
-+
-+	REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
-+			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);
-+}
-+
-+static const struct hubbub_funcs hubbub1_funcs = {
-+	.update_dchub = hubbub1_update_dchub
-+};
-+
-+void hubbub1_construct(struct hubbub *hubbub,
-+	struct dc_context *ctx,
-+	const struct dcn_hubbub_registers *hubbub_regs,
-+	const struct dcn_hubbub_shift *hubbub_shift,
-+	const struct dcn_hubbub_mask *hubbub_mask)
-+{
-+	hubbub->ctx = ctx;
-+
-+	hubbub->funcs = &hubbub1_funcs;
-+
-+	hubbub->regs = hubbub_regs;
-+	hubbub->shifts = hubbub_shift;
-+	hubbub->masks = hubbub_mask;
-+
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h.0130~	2017-12-14 06:39:58.421903572 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h	2017-12-14 06:39:58.421903572 +0100
-@@ -0,0 +1,214 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_HUBBUB_DCN10_H__
-+#define __DC_HUBBUB_DCN10_H__
-+
-+#include "core_types.h"
-+
-+#define HUBHUB_REG_LIST_DCN()\
-+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
-+	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
-+	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
-+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
-+	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
-+	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
-+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
-+	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
-+	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
-+	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
-+	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
-+	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
-+	SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
-+	SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\
-+	SR(DCHUBBUB_ARB_SAT_LEVEL),\
-+	SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
-+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
-+	SR(DCHUBBUB_TEST_DEBUG_INDEX), \
-+	SR(DCHUBBUB_TEST_DEBUG_DATA)
-+
-+#define HUBBUB_SR_WATERMARK_REG_LIST()\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
-+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)
-+
-+#define HUBBUB_REG_LIST_DCN10(id)\
-+	HUBHUB_REG_LIST_DCN(), \
-+	HUBBUB_SR_WATERMARK_REG_LIST(), \
-+	SR(DCHUBBUB_SDPIF_FB_TOP),\
-+	SR(DCHUBBUB_SDPIF_FB_BASE),\
-+	SR(DCHUBBUB_SDPIF_FB_OFFSET),\
-+	SR(DCHUBBUB_SDPIF_AGP_BASE),\
-+	SR(DCHUBBUB_SDPIF_AGP_BOT),\
-+	SR(DCHUBBUB_SDPIF_AGP_TOP)
-+
-+struct dcn_hubbub_registers {
-+	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
-+	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
-+	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
-+	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
-+	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
-+	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
-+	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
-+	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
-+	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
-+	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
-+	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
-+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
-+	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
-+	uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
-+	uint32_t DCHUBBUB_ARB_SAT_LEVEL;
-+	uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
-+	uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
-+	uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;
-+	uint32_t DCHUBBUB_TEST_DEBUG_INDEX;
-+	uint32_t DCHUBBUB_TEST_DEBUG_DATA;
-+	uint32_t DCHUBBUB_SDPIF_FB_TOP;
-+	uint32_t DCHUBBUB_SDPIF_FB_BASE;
-+	uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
-+	uint32_t DCHUBBUB_SDPIF_AGP_BASE;
-+	uint32_t DCHUBBUB_SDPIF_AGP_BOT;
-+	uint32_t DCHUBBUB_SDPIF_AGP_TOP;
-+	uint32_t DCHUBBUB_CRC_CTRL;
-+};
-+
-+/* set field name */
-+#define HUBBUB_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+
-+#define HUBBUB_MASK_SH_LIST_DCN(mask_sh)\
-+		HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
-+		HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
-+		HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
-+		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
-+		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \
-+		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \
-+		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \
-+		HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \
-+		HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh)
-+
-+#define HUBBUB_MASK_SH_LIST_DCN10(mask_sh)\
-+		HUBBUB_MASK_SH_LIST_DCN(mask_sh), \
-+		HUBBUB_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \
-+		HUBBUB_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
-+		HUBBUB_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
-+		HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
-+		HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
-+		HUBBUB_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh)
-+
-+#define DCN_HUBBUB_REG_FIELD_LIST(type) \
-+		type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
-+		type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
-+		type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
-+		type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
-+		type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
-+		type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\
-+		type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\
-+		type DCHUBBUB_ARB_SAT_LEVEL;\
-+		type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
-+		type DCHUBBUB_GLOBAL_TIMER_REFDIV;\
-+		type SDPIF_FB_TOP;\
-+		type SDPIF_FB_BASE;\
-+		type SDPIF_FB_OFFSET;\
-+		type SDPIF_AGP_BASE;\
-+		type SDPIF_AGP_BOT;\
-+		type SDPIF_AGP_TOP
-+
-+
-+struct dcn_hubbub_shift {
-+	DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
-+};
-+
-+struct dcn_hubbub_mask {
-+	DCN_HUBBUB_REG_FIELD_LIST(uint32_t);
-+};
-+
-+struct dc;
-+
-+struct dcn_hubbub_wm_set {
-+	uint32_t wm_set;
-+	uint32_t data_urgent;
-+	uint32_t pte_meta_urgent;
-+	uint32_t sr_enter;
-+	uint32_t sr_exit;
-+	uint32_t dram_clk_chanage;
-+};
-+
-+struct dcn_hubbub_wm {
-+	struct dcn_hubbub_wm_set sets[4];
-+};
-+
-+struct hubbub_funcs {
-+	void (*update_dchub)(
-+			struct hubbub *hubbub,
-+			struct dchub_init_data *dh_data);
-+};
-+
-+struct hubbub {
-+	const struct hubbub_funcs *funcs;
-+	struct dc_context *ctx;
-+	const struct dcn_hubbub_registers *regs;
-+	const struct dcn_hubbub_shift *shifts;
-+	const struct dcn_hubbub_mask *masks;
-+};
-+
-+void hubbub1_update_dchub(
-+	struct hubbub *hubbub,
-+	struct dchub_init_data *dh_data);
-+
-+bool hubbub1_verify_allow_pstate_change_high(
-+	struct hubbub *hubbub);
-+
-+void hubbub1_program_watermarks(
-+		struct hubbub *hubbub,
-+		struct dcn_watermark_set *watermarks,
-+		unsigned int refclk_mhz);
-+
-+void hubbub1_toggle_watermark_change_req(
-+		struct hubbub *hubbub);
-+
-+void hubbub1_wm_read_state(struct hubbub *hubbub,
-+		struct dcn_hubbub_wm *wm);
-+
-+void hubbub1_construct(struct hubbub *hubbub,
-+	struct dc_context *ctx,
-+	const struct dcn_hubbub_registers *hubbub_regs,
-+	const struct dcn_hubbub_shift *hubbub_shift,
-+	const struct dcn_hubbub_mask *hubbub_mask);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c.0130~	2017-12-14 06:39:58.421903572 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c	2017-12-14 06:39:58.421903572 +0100
-@@ -0,0 +1,969 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "dm_services.h"
-+#include "dce_calcs.h"
-+#include "reg_helper.h"
-+#include "basics/conversion.h"
-+#include "dcn10_hubp.h"
-+
-+#define REG(reg)\
-+	hubp1->hubp_regs->reg
-+
-+#define CTX \
-+	hubp1->base.ctx
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name
-+
-+void hubp1_set_blank(struct hubp *hubp, bool blank)
-+{
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+	uint32_t blank_en = blank ? 1 : 0;
-+
-+	REG_UPDATE_2(DCHUBP_CNTL,
-+			HUBP_BLANK_EN, blank_en,
-+			HUBP_TTU_DISABLE, blank_en);
-+
-+	if (blank) {
-+		REG_WAIT(DCHUBP_CNTL,
-+				HUBP_NO_OUTSTANDING_REQ, 1,
-+				1, 200);
-+		hubp->mpcc_id = 0xf;
-+		hubp->opp_id = 0xf;
-+	}
-+}
-+
-+static void hubp1_disconnect(struct hubp *hubp)
-+{
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+
-+	REG_UPDATE(DCHUBP_CNTL,
-+			HUBP_TTU_DISABLE, 1);
-+}
-+
-+static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
-+{
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+	uint32_t blank_en = blank ? 1 : 0;
-+
-+	REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en);
-+}
-+
-+static void hubp1_vready_workaround(struct hubp *hubp,
-+		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
-+{
-+	uint32_t value = 0;
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+
-+	/* set HBUBREQ_DEBUG_DB[12] = 1 */
-+	value = REG_READ(HUBPREQ_DEBUG_DB);
-+
-+	/* hack mode disable */
-+	value |= 0x100;
-+	value &= ~0x1000;
-+
-+	if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width
-+		+ pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
-+		/* if (eco_fix_needed(otg_global_sync_timing)
-+		 * set HBUBREQ_DEBUG_DB[12] = 1 */
-+		value |= 0x1000;
-+	}
-+
-+	REG_WRITE(HUBPREQ_DEBUG_DB, value);
-+}
-+
-+void hubp1_program_tiling(
-+	struct dcn10_hubp *hubp1,
-+	const union dc_tiling_info *info,
-+	const enum surface_pixel_format pixel_format)
-+{
-+	REG_UPDATE_6(DCSURF_ADDR_CONFIG,
-+			NUM_PIPES, log_2(info->gfx9.num_pipes),
-+			NUM_BANKS, log_2(info->gfx9.num_banks),
-+			PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
-+			NUM_SE, log_2(info->gfx9.num_shader_engines),
-+			NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
-+			MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
-+
-+	REG_UPDATE_4(DCSURF_TILING_CONFIG,
-+			SW_MODE, info->gfx9.swizzle,
-+			META_LINEAR, info->gfx9.meta_linear,
-+			RB_ALIGNED, info->gfx9.rb_aligned,
-+			PIPE_ALIGNED, info->gfx9.pipe_aligned);
-+}
-+
-+void hubp1_program_size_and_rotation(
-+	struct dcn10_hubp *hubp1,
-+	enum dc_rotation_angle rotation,
-+	enum surface_pixel_format format,
-+	const union plane_size *plane_size,
-+	struct dc_plane_dcc_param *dcc,
-+	bool horizontal_mirror)
-+{
-+	uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c, mirror;
-+
-+	/* Program data and meta surface pitch (calculation from addrlib)
-+	 * 444 or 420 luma
-+	 */
-+	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-+		pitch = plane_size->video.luma_pitch - 1;
-+		meta_pitch = dcc->video.meta_pitch_l - 1;
-+		pitch_c = plane_size->video.chroma_pitch - 1;
-+		meta_pitch_c = dcc->video.meta_pitch_c - 1;
-+	} else {
-+		pitch = plane_size->grph.surface_pitch - 1;
-+		meta_pitch = dcc->grph.meta_pitch - 1;
-+		pitch_c = 0;
-+		meta_pitch_c = 0;
-+	}
-+
-+	if (!dcc->enable) {
-+		meta_pitch = 0;
-+		meta_pitch_c = 0;
-+	}
-+
-+	REG_UPDATE_2(DCSURF_SURFACE_PITCH,
-+			PITCH, pitch, META_PITCH, meta_pitch);
-+
-+	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
-+		REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
-+			PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
-+
-+	if (horizontal_mirror)
-+		mirror = 1;
-+	else
-+		mirror = 0;
-+
-+
-+	/* Program rotation angle and horz mirror - no mirror */
-+	if (rotation == ROTATION_ANGLE_0)
-+		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
-+				ROTATION_ANGLE, 0,
-+				H_MIRROR_EN, mirror);
-+	else if (rotation == ROTATION_ANGLE_90)
-+		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
-+				ROTATION_ANGLE, 1,
-+				H_MIRROR_EN, mirror);
-+	else if (rotation == ROTATION_ANGLE_180)
-+		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
-+				ROTATION_ANGLE, 2,
-+				H_MIRROR_EN, mirror);
-+	else if (rotation == ROTATION_ANGLE_270)
-+		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
-+				ROTATION_ANGLE, 3,
-+				H_MIRROR_EN, mirror);
-+}
-+
-+void hubp1_program_pixel_format(
-+	struct dcn10_hubp *hubp1,
-+	enum surface_pixel_format format)
-+{
-+	uint32_t red_bar = 3;
-+	uint32_t blue_bar = 2;
-+
-+	/* swap for ABGR format */
-+	if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
-+			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
-+			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
-+			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
-+		red_bar = 2;
-+		blue_bar = 3;
-+	}
-+
-+	REG_UPDATE_2(HUBPRET_CONTROL,
-+			CROSSBAR_SRC_CB_B, blue_bar,
-+			CROSSBAR_SRC_CR_R, red_bar);
-+
-+	/* Mapping is same as ipp programming (cnvc) */
-+
-+	switch (format)	{
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
-+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
-+				SURFACE_PIXEL_FORMAT, 1);
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
-+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
-+				SURFACE_PIXEL_FORMAT, 3);
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
-+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
-+				SURFACE_PIXEL_FORMAT, 8);
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
-+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
-+				SURFACE_PIXEL_FORMAT, 10);
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
-+				SURFACE_PIXEL_FORMAT, 22);
-+		break;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
-+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
-+				SURFACE_PIXEL_FORMAT, 24);
-+		break;
-+
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
-+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
-+				SURFACE_PIXEL_FORMAT, 65);
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
-+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
-+				SURFACE_PIXEL_FORMAT, 64);
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
-+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
-+				SURFACE_PIXEL_FORMAT, 67);
-+		break;
-+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
-+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
-+				SURFACE_PIXEL_FORMAT, 66);
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+
-+	/* don't see the need of program the xbar in DCN 1.0 */
-+}
-+
-+bool hubp1_program_surface_flip_and_addr(
-+	struct hubp *hubp,
-+	const struct dc_plane_address *address,
-+	bool flip_immediate)
-+{
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+
-+	/* program flip type */
-+	REG_SET(DCSURF_FLIP_CONTROL, 0,
-+			SURFACE_FLIP_TYPE, flip_immediate);
-+
-+	/* HW automatically latch rest of address register on write to
-+	 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
-+	 *
-+	 * program high first and then the low addr, order matters!
-+	 */
-+	switch (address->type) {
-+	case PLN_ADDR_TYPE_GRAPHICS:
-+		/* DCN1.0 does not support const color
-+		 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
-+		 * base on address->grph.dcc_const_color
-+		 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
-+		 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
-+		 */
-+
-+		if (address->grph.addr.quad_part == 0)
-+			break;
-+
-+		REG_UPDATE(DCSURF_SURFACE_CONTROL,
-+				PRIMARY_SURFACE_TMZ, address->tmz_surface);
-+
-+		if (address->grph.meta_addr.quad_part != 0) {
-+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
-+					PRIMARY_META_SURFACE_ADDRESS_HIGH,
-+					address->grph.meta_addr.high_part);
-+
-+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
-+					PRIMARY_META_SURFACE_ADDRESS,
-+					address->grph.meta_addr.low_part);
-+		}
-+
-+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
-+				PRIMARY_SURFACE_ADDRESS_HIGH,
-+				address->grph.addr.high_part);
-+
-+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
-+				PRIMARY_SURFACE_ADDRESS,
-+				address->grph.addr.low_part);
-+		break;
-+	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
-+		if (address->video_progressive.luma_addr.quad_part == 0
-+			|| address->video_progressive.chroma_addr.quad_part == 0)
-+			break;
-+
-+		REG_UPDATE(DCSURF_SURFACE_CONTROL,
-+				PRIMARY_SURFACE_TMZ, address->tmz_surface);
-+
-+		if (address->video_progressive.luma_meta_addr.quad_part != 0) {
-+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
-+				PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
-+				address->video_progressive.chroma_meta_addr.high_part);
-+
-+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
-+				PRIMARY_META_SURFACE_ADDRESS_C,
-+				address->video_progressive.chroma_meta_addr.low_part);
-+
-+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
-+				PRIMARY_META_SURFACE_ADDRESS_HIGH,
-+				address->video_progressive.luma_meta_addr.high_part);
-+
-+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
-+				PRIMARY_META_SURFACE_ADDRESS,
-+				address->video_progressive.luma_meta_addr.low_part);
-+		}
-+
-+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
-+			PRIMARY_SURFACE_ADDRESS_HIGH_C,
-+			address->video_progressive.chroma_addr.high_part);
-+
-+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
-+			PRIMARY_SURFACE_ADDRESS_C,
-+			address->video_progressive.chroma_addr.low_part);
-+
-+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
-+			PRIMARY_SURFACE_ADDRESS_HIGH,
-+			address->video_progressive.luma_addr.high_part);
-+
-+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
-+			PRIMARY_SURFACE_ADDRESS,
-+			address->video_progressive.luma_addr.low_part);
-+		break;
-+	case PLN_ADDR_TYPE_GRPH_STEREO:
-+		if (address->grph_stereo.left_addr.quad_part == 0)
-+			break;
-+		if (address->grph_stereo.right_addr.quad_part == 0)
-+			break;
-+
-+		REG_UPDATE(DCSURF_SURFACE_CONTROL,
-+				PRIMARY_SURFACE_TMZ, address->tmz_surface);
-+
-+		if (address->grph_stereo.right_meta_addr.quad_part != 0) {
-+
-+			REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
-+					SECONDARY_META_SURFACE_ADDRESS_HIGH,
-+					address->grph_stereo.right_meta_addr.high_part);
-+
-+			REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
-+					SECONDARY_META_SURFACE_ADDRESS,
-+					address->grph_stereo.right_meta_addr.low_part);
-+		}
-+		if (address->grph_stereo.left_meta_addr.quad_part != 0) {
-+
-+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
-+					PRIMARY_META_SURFACE_ADDRESS_HIGH,
-+					address->grph_stereo.left_meta_addr.high_part);
-+
-+			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
-+					PRIMARY_META_SURFACE_ADDRESS,
-+					address->grph_stereo.left_meta_addr.low_part);
-+		}
-+
-+		REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
-+				SECONDARY_SURFACE_ADDRESS_HIGH,
-+				address->grph_stereo.right_addr.high_part);
-+
-+		REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
-+				SECONDARY_SURFACE_ADDRESS,
-+				address->grph_stereo.right_addr.low_part);
-+
-+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
-+				PRIMARY_SURFACE_ADDRESS_HIGH,
-+				address->grph_stereo.left_addr.high_part);
-+
-+		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
-+				PRIMARY_SURFACE_ADDRESS,
-+				address->grph_stereo.left_addr.low_part);
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+
-+	hubp->request_address = *address;
-+
-+	if (flip_immediate)
-+		hubp->current_address = *address;
-+
-+	return true;
-+}
-+
-+void hubp1_dcc_control(struct hubp *hubp, bool enable,
-+		bool independent_64b_blks)
-+{
-+	uint32_t dcc_en = enable ? 1 : 0;
-+	uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+
-+	REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
-+			PRIMARY_SURFACE_DCC_EN, dcc_en,
-+			PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
-+}
-+
-+void hubp1_program_surface_config(
-+	struct hubp *hubp,
-+	enum surface_pixel_format format,
-+	union dc_tiling_info *tiling_info,
-+	union plane_size *plane_size,
-+	enum dc_rotation_angle rotation,
-+	struct dc_plane_dcc_param *dcc,
-+	bool horizontal_mirror)
-+{
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+
-+	hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
-+	hubp1_program_tiling(hubp1, tiling_info, format);
-+	hubp1_program_size_and_rotation(
-+			hubp1, rotation, format, plane_size, dcc, horizontal_mirror);
-+	hubp1_program_pixel_format(hubp1, format);
-+}
-+
-+void hubp1_program_requestor(
-+		struct hubp *hubp,
-+		struct _vcs_dpi_display_rq_regs_st *rq_regs)
-+{
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+
-+	REG_UPDATE(HUBPRET_CONTROL,
-+			DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
-+	REG_SET_4(DCN_EXPANSION_MODE, 0,
-+			DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
-+			PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
-+			MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
-+			CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
-+	REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
-+		CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
-+		MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
-+		META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
-+		MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
-+		DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
-+		MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
-+		SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
-+		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
-+	REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
-+		CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
-+		MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
-+		META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
-+		MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
-+		DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
-+		MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
-+		SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
-+		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
-+}
-+
-+
-+void hubp1_program_deadline(
-+		struct hubp *hubp,
-+		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
-+		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
-+{
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+
-+	/* DLG - Per hubp */
-+	REG_SET_2(BLANK_OFFSET_0, 0,
-+		REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
-+		DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
-+
-+	REG_SET(BLANK_OFFSET_1, 0,
-+		MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
-+
-+	REG_SET(DST_DIMENSIONS, 0,
-+		REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
-+
-+	REG_SET_2(DST_AFTER_SCALER, 0,
-+		REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
-+		DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
-+
-+	if (REG(PREFETCH_SETTINS))
-+		REG_SET_2(PREFETCH_SETTINS, 0,
-+			DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
-+			VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
-+	else
-+		REG_SET_2(PREFETCH_SETTINGS, 0,
-+			DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
-+			VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
-+
-+	REG_SET_2(VBLANK_PARAMETERS_0, 0,
-+		DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
-+		DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
-+
-+	REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
-+		REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
-+
-+	/* DLG - Per luma/chroma */
-+	REG_SET(VBLANK_PARAMETERS_1, 0,
-+		REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
-+
-+	REG_SET(VBLANK_PARAMETERS_3, 0,
-+		REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
-+
-+	REG_SET(NOM_PARAMETERS_0, 0,
-+		DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
-+
-+	REG_SET(NOM_PARAMETERS_1, 0,
-+		REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
-+
-+	REG_SET(NOM_PARAMETERS_4, 0,
-+		DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
-+
-+	REG_SET(NOM_PARAMETERS_5, 0,
-+		REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
-+
-+	REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
-+		REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
-+		REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
-+
-+	REG_SET_2(PER_LINE_DELIVERY, 0,
-+		REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
-+		REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
-+
-+	if (REG(PREFETCH_SETTINS_C))
-+		REG_SET(PREFETCH_SETTINS_C, 0,
-+			VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
-+	else
-+		REG_SET(PREFETCH_SETTINGS_C, 0,
-+			VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
-+
-+	REG_SET(VBLANK_PARAMETERS_2, 0,
-+		REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
-+
-+	REG_SET(VBLANK_PARAMETERS_4, 0,
-+		REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
-+
-+	REG_SET(NOM_PARAMETERS_2, 0,
-+		DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
-+
-+	REG_SET(NOM_PARAMETERS_3, 0,
-+		REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
-+
-+	REG_SET(NOM_PARAMETERS_6, 0,
-+		DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
-+
-+	REG_SET(NOM_PARAMETERS_7, 0,
-+		REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
-+
-+	/* TTU - per hubp */
-+	REG_SET_2(DCN_TTU_QOS_WM, 0,
-+		QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
-+		QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
-+
-+	REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
-+		MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
-+		QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
-+
-+	/* TTU - per luma/chroma */
-+	/* Assumed surf0 is luma and 1 is chroma */
-+
-+	REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
-+		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
-+		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
-+		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
-+
-+	REG_SET(DCN_SURF0_TTU_CNTL1, 0,
-+		REFCYC_PER_REQ_DELIVERY_PRE,
-+		ttu_attr->refcyc_per_req_delivery_pre_l);
-+
-+	REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
-+		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
-+		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
-+		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
-+
-+	REG_SET(DCN_SURF1_TTU_CNTL1, 0,
-+		REFCYC_PER_REQ_DELIVERY_PRE,
-+		ttu_attr->refcyc_per_req_delivery_pre_c);
-+}
-+
-+static void hubp1_setup(
-+		struct hubp *hubp,
-+		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
-+		struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
-+		struct _vcs_dpi_display_rq_regs_st *rq_regs,
-+		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
-+{
-+	/* otg is locked when this func is called. Register are double buffered.
-+	 * disable the requestors is not needed
-+	 */
-+	hubp1_program_requestor(hubp, rq_regs);
-+	hubp1_program_deadline(hubp, dlg_attr, ttu_attr);
-+	hubp1_vready_workaround(hubp, pipe_dest);
-+}
-+
-+bool hubp1_is_flip_pending(struct hubp *hubp)
-+{
-+	uint32_t flip_pending = 0;
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+	struct dc_plane_address earliest_inuse_address;
-+
-+	REG_GET(DCSURF_FLIP_CONTROL,
-+			SURFACE_FLIP_PENDING, &flip_pending);
-+
-+	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
-+			SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
-+
-+	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
-+			SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
-+
-+	if (flip_pending)
-+		return true;
-+
-+	if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
-+		return true;
-+
-+	hubp->current_address = hubp->request_address;
-+	return false;
-+}
-+
-+uint32_t aperture_default_system = 1;
-+uint32_t context0_default_system; /* = 0;*/
-+
-+static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp,
-+		struct vm_system_aperture_param *apt)
-+{
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+	PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
-+	PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
-+	PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
-+
-+	mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
-+	mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12;
-+	mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12;
-+
-+	REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0,
-+		MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */
-+		MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
-+	REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
-+		MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
-+
-+	REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0,
-+			MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part);
-+	REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0,
-+			MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part);
-+
-+	REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0,
-+			MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part);
-+	REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0,
-+			MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part);
-+}
-+
-+static void hubp1_set_vm_context0_settings(struct hubp *hubp,
-+		const struct vm_context0_param *vm0)
-+{
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+	/* pte base */
-+	REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0,
-+			VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part);
-+	REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0,
-+			VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part);
-+
-+	/* pte start */
-+	REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0,
-+			VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part);
-+	REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0,
-+			VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part);
-+
-+	/* pte end */
-+	REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0,
-+			VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part);
-+	REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0,
-+			VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part);
-+
-+	/* fault handling */
-+	REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
-+			VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part,
-+			VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system);
-+	REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
-+			VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part);
-+
-+	/* control: enable VM PTE*/
-+	REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
-+			ENABLE_L1_TLB, 1,
-+			SYSTEM_ACCESS_MODE, 3);
-+}
-+
-+void min_set_viewport(
-+	struct hubp *hubp,
-+	const struct rect *viewport,
-+	const struct rect *viewport_c)
-+{
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+
-+	REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
-+		  PRI_VIEWPORT_WIDTH, viewport->width,
-+		  PRI_VIEWPORT_HEIGHT, viewport->height);
-+
-+	REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
-+		  PRI_VIEWPORT_X_START, viewport->x,
-+		  PRI_VIEWPORT_Y_START, viewport->y);
-+
-+	/*for stereo*/
-+	REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
-+		  SEC_VIEWPORT_WIDTH, viewport->width,
-+		  SEC_VIEWPORT_HEIGHT, viewport->height);
-+
-+	REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
-+		  SEC_VIEWPORT_X_START, viewport->x,
-+		  SEC_VIEWPORT_Y_START, viewport->y);
-+
-+	/* DC supports NV12 only at the moment */
-+	REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
-+		  PRI_VIEWPORT_WIDTH_C, viewport_c->width,
-+		  PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
-+
-+	REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
-+		  PRI_VIEWPORT_X_START_C, viewport_c->x,
-+		  PRI_VIEWPORT_Y_START_C, viewport_c->y);
-+}
-+
-+void hubp1_read_state(struct dcn10_hubp *hubp1,
-+		struct dcn_hubp_state *s)
-+{
-+	REG_GET(DCSURF_SURFACE_CONFIG,
-+			SURFACE_PIXEL_FORMAT, &s->pixel_format);
-+
-+	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
-+			SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
-+
-+	REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
-+			PRI_VIEWPORT_WIDTH, &s->viewport_width,
-+			PRI_VIEWPORT_HEIGHT, &s->viewport_height);
-+
-+	REG_GET_2(DCSURF_SURFACE_CONFIG,
-+			ROTATION_ANGLE, &s->rotation_angle,
-+			H_MIRROR_EN, &s->h_mirror_en);
-+
-+	REG_GET(DCSURF_TILING_CONFIG,
-+			SW_MODE, &s->sw_mode);
-+
-+	REG_GET(DCSURF_SURFACE_CONTROL,
-+			PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
-+
-+	REG_GET_3(DCHUBP_CNTL,
-+			HUBP_BLANK_EN, &s->blank_en,
-+			HUBP_TTU_DISABLE, &s->ttu_disable,
-+			HUBP_UNDERFLOW_STATUS, &s->underflow_status);
-+
-+	REG_GET(DCN_GLOBAL_TTU_CNTL,
-+			MIN_TTU_VBLANK, &s->min_ttu_vblank);
-+
-+	REG_GET_2(DCN_TTU_QOS_WM,
-+			QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
-+			QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
-+}
-+
-+enum cursor_pitch {
-+	CURSOR_PITCH_64_PIXELS = 0,
-+	CURSOR_PITCH_128_PIXELS,
-+	CURSOR_PITCH_256_PIXELS
-+};
-+
-+enum cursor_lines_per_chunk {
-+	CURSOR_LINE_PER_CHUNK_2 = 1,
-+	CURSOR_LINE_PER_CHUNK_4,
-+	CURSOR_LINE_PER_CHUNK_8,
-+	CURSOR_LINE_PER_CHUNK_16
-+};
-+
-+static bool ippn10_cursor_program_control(
-+		struct dcn10_hubp *hubp1,
-+		bool pixel_data_invert,
-+		enum dc_cursor_color_format color_format)
-+{
-+	if (REG(CURSOR_SETTINS))
-+		REG_SET_2(CURSOR_SETTINS, 0,
-+				/* no shift of the cursor HDL schedule */
-+				CURSOR0_DST_Y_OFFSET, 0,
-+				 /* used to shift the cursor chunk request deadline */
-+				CURSOR0_CHUNK_HDL_ADJUST, 3);
-+	else
-+		REG_SET_2(CURSOR_SETTINGS, 0,
-+				/* no shift of the cursor HDL schedule */
-+				CURSOR0_DST_Y_OFFSET, 0,
-+				 /* used to shift the cursor chunk request deadline */
-+				CURSOR0_CHUNK_HDL_ADJUST, 3);
-+
-+	return true;
-+}
-+
-+static enum cursor_pitch ippn10_get_cursor_pitch(
-+		unsigned int pitch)
-+{
-+	enum cursor_pitch hw_pitch;
-+
-+	switch (pitch) {
-+	case 64:
-+		hw_pitch = CURSOR_PITCH_64_PIXELS;
-+		break;
-+	case 128:
-+		hw_pitch = CURSOR_PITCH_128_PIXELS;
-+		break;
-+	case 256:
-+		hw_pitch = CURSOR_PITCH_256_PIXELS;
-+		break;
-+	default:
-+		DC_ERR("Invalid cursor pitch of %d. "
-+				"Only 64/128/256 is supported on DCN.\n", pitch);
-+		hw_pitch = CURSOR_PITCH_64_PIXELS;
-+		break;
-+	}
-+	return hw_pitch;
-+}
-+
-+static enum cursor_lines_per_chunk ippn10_get_lines_per_chunk(
-+		unsigned int cur_width,
-+		enum dc_cursor_color_format format)
-+{
-+	enum cursor_lines_per_chunk line_per_chunk;
-+
-+	if (format == CURSOR_MODE_MONO)
-+		/* impl B. expansion in CUR Buffer reader */
-+		line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
-+	else if (cur_width <= 32)
-+		line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
-+	else if (cur_width <= 64)
-+		line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
-+	else if (cur_width <= 128)
-+		line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
-+	else
-+		line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
-+
-+	return line_per_chunk;
-+}
-+
-+void hubp1_cursor_set_attributes(
-+		struct hubp *hubp,
-+		const struct dc_cursor_attributes *attr)
-+{
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+	enum cursor_pitch hw_pitch = ippn10_get_cursor_pitch(attr->pitch);
-+	enum cursor_lines_per_chunk lpc = ippn10_get_lines_per_chunk(
-+			attr->width, attr->color_format);
-+
-+	hubp->curs_attr = *attr;
-+
-+	REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
-+			CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
-+	REG_UPDATE(CURSOR_SURFACE_ADDRESS,
-+			CURSOR_SURFACE_ADDRESS, attr->address.low_part);
-+
-+	REG_UPDATE_2(CURSOR_SIZE,
-+			CURSOR_WIDTH, attr->width,
-+			CURSOR_HEIGHT, attr->height);
-+	REG_UPDATE_3(CURSOR_CONTROL,
-+			CURSOR_MODE, attr->color_format,
-+			CURSOR_PITCH, hw_pitch,
-+			CURSOR_LINES_PER_CHUNK, lpc);
-+	ippn10_cursor_program_control(hubp1,
-+			attr->attribute_flags.bits.INVERT_PIXEL_DATA,
-+			attr->color_format);
-+}
-+
-+void hubp1_cursor_set_position(
-+		struct hubp *hubp,
-+		const struct dc_cursor_position *pos,
-+		const struct dc_cursor_mi_param *param)
-+{
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+	int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start;
-+	uint32_t cur_en = pos->enable ? 1 : 0;
-+	uint32_t dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
-+
-+	/*
-+	 * Guard aganst cursor_set_position() from being called with invalid
-+	 * attributes
-+	 *
-+	 * TODO: Look at combining cursor_set_position() and
-+	 * cursor_set_attributes() into cursor_update()
-+	 */
-+	if (hubp->curs_attr.address.quad_part == 0)
-+		return;
-+
-+	dst_x_offset *= param->ref_clk_khz;
-+	dst_x_offset /= param->pixel_clk_khz;
-+
-+	ASSERT(param->h_scale_ratio.value);
-+
-+	if (param->h_scale_ratio.value)
-+		dst_x_offset = dal_fixed31_32_floor(dal_fixed31_32_div(
-+				dal_fixed31_32_from_int(dst_x_offset),
-+				param->h_scale_ratio));
-+
-+	if (src_x_offset >= (int)param->viewport_width)
-+		cur_en = 0;  /* not visible beyond right edge*/
-+
-+	if (src_x_offset + (int)hubp->curs_attr.width < 0)
-+		cur_en = 0;  /* not visible beyond left edge*/
-+
-+	if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
-+		hubp1_cursor_set_attributes(hubp, &hubp->curs_attr);
-+	REG_UPDATE(CURSOR_CONTROL,
-+			CURSOR_ENABLE, cur_en);
-+
-+	REG_SET_2(CURSOR_POSITION, 0,
-+			CURSOR_X_POSITION, pos->x,
-+			CURSOR_Y_POSITION, pos->y);
-+
-+	REG_SET_2(CURSOR_HOT_SPOT, 0,
-+			CURSOR_HOT_SPOT_X, pos->x_hotspot,
-+			CURSOR_HOT_SPOT_Y, pos->y_hotspot);
-+
-+	REG_SET(CURSOR_DST_OFFSET, 0,
-+			CURSOR_DST_X_OFFSET, dst_x_offset);
-+	/* TODO Handle surface pixel formats other than 4:4:4 */
-+}
-+
-+static struct hubp_funcs dcn10_hubp_funcs = {
-+	.hubp_program_surface_flip_and_addr =
-+			hubp1_program_surface_flip_and_addr,
-+	.hubp_program_surface_config =
-+			hubp1_program_surface_config,
-+	.hubp_is_flip_pending = hubp1_is_flip_pending,
-+	.hubp_setup = hubp1_setup,
-+	.hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings,
-+	.hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings,
-+	.set_blank = hubp1_set_blank,
-+	.dcc_control = hubp1_dcc_control,
-+	.mem_program_viewport = min_set_viewport,
-+	.set_hubp_blank_en = hubp1_set_hubp_blank_en,
-+	.set_cursor_attributes	= hubp1_cursor_set_attributes,
-+	.set_cursor_position	= hubp1_cursor_set_position,
-+	.hubp_disconnect = hubp1_disconnect,
-+};
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+void dcn10_hubp_construct(
-+	struct dcn10_hubp *hubp1,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dcn_mi_registers *hubp_regs,
-+	const struct dcn_mi_shift *hubp_shift,
-+	const struct dcn_mi_mask *hubp_mask)
-+{
-+	hubp1->base.funcs = &dcn10_hubp_funcs;
-+	hubp1->base.ctx = ctx;
-+	hubp1->hubp_regs = hubp_regs;
-+	hubp1->hubp_shift = hubp_shift;
-+	hubp1->hubp_mask = hubp_mask;
-+	hubp1->base.inst = inst;
-+	hubp1->base.opp_id = 0xf;
-+	hubp1->base.mpcc_id = 0xf;
-+}
-+
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h.0130~	2017-12-14 06:39:58.422903572 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h	2017-12-14 06:39:58.422903572 +0100
-@@ -0,0 +1,684 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_MEM_INPUT_DCN10_H__
-+#define __DC_MEM_INPUT_DCN10_H__
-+
-+#include "hubp.h"
-+
-+#define TO_DCN10_HUBP(hubp)\
-+	container_of(hubp, struct dcn10_hubp, base)
-+
-+#define HUBP_REG_LIST_DCN(id)\
-+	SRI(DCHUBP_CNTL, HUBP, id),\
-+	SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
-+	SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
-+	SRI(DCSURF_TILING_CONFIG, HUBP, id),\
-+	SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
-+	SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
-+	SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
-+	SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
-+	SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
-+	SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
-+	SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
-+	SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
-+	SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
-+	SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
-+	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
-+	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
-+	SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
-+	SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\
-+	SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
-+	SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
-+	SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
-+	SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
-+	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
-+	SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
-+	SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
-+	SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
-+	SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
-+	SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
-+	SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
-+	SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\
-+	SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\
-+	SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\
-+	SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\
-+	SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\
-+	SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
-+	SRI(HUBPRET_CONTROL, HUBPRET, id),\
-+	SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
-+	SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
-+	SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\
-+	SRI(BLANK_OFFSET_0, HUBPREQ, id),\
-+	SRI(BLANK_OFFSET_1, HUBPREQ, id),\
-+	SRI(DST_DIMENSIONS, HUBPREQ, id),\
-+	SRI(DST_AFTER_SCALER, HUBPREQ, id),\
-+	SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
-+	SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
-+	SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
-+	SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
-+	SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
-+	SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
-+	SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
-+	SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
-+	SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
-+	SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
-+	SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
-+	SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
-+	SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
-+	SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
-+	SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
-+	SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
-+	SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
-+	SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\
-+	SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\
-+	SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
-+	SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
-+	SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
-+	SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
-+
-+#define HUBP_REG_LIST_DCN10(id)\
-+	HUBP_REG_LIST_DCN(id),\
-+	SRI(PREFETCH_SETTINS, HUBPREQ, id),\
-+	SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
-+	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
-+	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
-+	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
-+	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\
-+	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\
-+	SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\
-+	SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\
-+	SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\
-+	SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\
-+	SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\
-+	SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\
-+	SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
-+	SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
-+	SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
-+	SR(DCHUBBUB_SDPIF_FB_BASE),\
-+	SR(DCHUBBUB_SDPIF_FB_OFFSET),\
-+	SRI(CURSOR_SETTINS, HUBPREQ, id), \
-+	SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
-+	SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
-+	SRI(CURSOR_SIZE, CURSOR, id), \
-+	SRI(CURSOR_CONTROL, CURSOR, id), \
-+	SRI(CURSOR_POSITION, CURSOR, id), \
-+	SRI(CURSOR_HOT_SPOT, CURSOR, id), \
-+	SRI(CURSOR_DST_OFFSET, CURSOR, id)
-+
-+
-+
-+struct dcn_mi_registers {
-+	uint32_t DCHUBP_CNTL;
-+	uint32_t HUBPREQ_DEBUG_DB;
-+	uint32_t DCSURF_ADDR_CONFIG;
-+	uint32_t DCSURF_TILING_CONFIG;
-+	uint32_t DCSURF_SURFACE_PITCH;
-+	uint32_t DCSURF_SURFACE_PITCH_C;
-+	uint32_t DCSURF_SURFACE_CONFIG;
-+	uint32_t DCSURF_FLIP_CONTROL;
-+	uint32_t DCSURF_PRI_VIEWPORT_DIMENSION;
-+	uint32_t DCSURF_PRI_VIEWPORT_START;
-+	uint32_t DCSURF_SEC_VIEWPORT_DIMENSION;
-+	uint32_t DCSURF_SEC_VIEWPORT_START;
-+	uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C;
-+	uint32_t DCSURF_PRI_VIEWPORT_START_C;
-+	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
-+	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;
-+	uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH;
-+	uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS;
-+	uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;
-+	uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS;
-+	uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH;
-+	uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS;
-+	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
-+	uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
-+	uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
-+	uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
-+	uint32_t DCSURF_SURFACE_INUSE;
-+	uint32_t DCSURF_SURFACE_INUSE_HIGH;
-+	uint32_t DCSURF_SURFACE_INUSE_C;
-+	uint32_t DCSURF_SURFACE_INUSE_HIGH_C;
-+	uint32_t DCSURF_SURFACE_EARLIEST_INUSE;
-+	uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH;
-+	uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C;
-+	uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C;
-+	uint32_t DCSURF_SURFACE_CONTROL;
-+	uint32_t HUBPRET_CONTROL;
-+	uint32_t DCN_EXPANSION_MODE;
-+	uint32_t DCHUBP_REQ_SIZE_CONFIG;
-+	uint32_t DCHUBP_REQ_SIZE_CONFIG_C;
-+	uint32_t BLANK_OFFSET_0;
-+	uint32_t BLANK_OFFSET_1;
-+	uint32_t DST_DIMENSIONS;
-+	uint32_t DST_AFTER_SCALER;
-+	uint32_t PREFETCH_SETTINS;
-+	uint32_t PREFETCH_SETTINGS;
-+	uint32_t VBLANK_PARAMETERS_0;
-+	uint32_t REF_FREQ_TO_PIX_FREQ;
-+	uint32_t VBLANK_PARAMETERS_1;
-+	uint32_t VBLANK_PARAMETERS_3;
-+	uint32_t NOM_PARAMETERS_0;
-+	uint32_t NOM_PARAMETERS_1;
-+	uint32_t NOM_PARAMETERS_4;
-+	uint32_t NOM_PARAMETERS_5;
-+	uint32_t PER_LINE_DELIVERY_PRE;
-+	uint32_t PER_LINE_DELIVERY;
-+	uint32_t PREFETCH_SETTINS_C;
-+	uint32_t PREFETCH_SETTINGS_C;
-+	uint32_t VBLANK_PARAMETERS_2;
-+	uint32_t VBLANK_PARAMETERS_4;
-+	uint32_t NOM_PARAMETERS_2;
-+	uint32_t NOM_PARAMETERS_3;
-+	uint32_t NOM_PARAMETERS_6;
-+	uint32_t NOM_PARAMETERS_7;
-+	uint32_t DCN_TTU_QOS_WM;
-+	uint32_t DCN_GLOBAL_TTU_CNTL;
-+	uint32_t DCN_SURF0_TTU_CNTL0;
-+	uint32_t DCN_SURF0_TTU_CNTL1;
-+	uint32_t DCN_SURF1_TTU_CNTL0;
-+	uint32_t DCN_SURF1_TTU_CNTL1;
-+	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;
-+	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;
-+	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;
-+	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;
-+	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;
-+	uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;
-+	uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
-+	uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
-+	uint32_t DCN_VM_MX_L1_TLB_CNTL;
-+	uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
-+	uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
-+	uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;
-+	uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;
-+	uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;
-+	uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;
-+	uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR;
-+	uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR;
-+	uint32_t DCHUBBUB_SDPIF_FB_BASE;
-+	uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
-+	uint32_t DCN_VM_FB_LOCATION_TOP;
-+	uint32_t DCN_VM_FB_LOCATION_BASE;
-+	uint32_t DCN_VM_FB_OFFSET;
-+	uint32_t DCN_VM_AGP_BASE;
-+	uint32_t DCN_VM_AGP_BOT;
-+	uint32_t DCN_VM_AGP_TOP;
-+	uint32_t CURSOR_SETTINS;
-+	uint32_t CURSOR_SETTINGS;
-+	uint32_t CURSOR_SURFACE_ADDRESS_HIGH;
-+	uint32_t CURSOR_SURFACE_ADDRESS;
-+	uint32_t CURSOR_SIZE;
-+	uint32_t CURSOR_CONTROL;
-+	uint32_t CURSOR_POSITION;
-+	uint32_t CURSOR_HOT_SPOT;
-+	uint32_t CURSOR_DST_OFFSET;
-+};
-+
-+#define HUBP_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+#define HUBP_MASK_SH_LIST_DCN(mask_sh)\
-+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
-+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
-+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
-+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
-+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
-+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
-+	HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
-+	HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
-+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
-+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
-+	HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
-+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
-+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
-+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
-+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
-+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
-+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
-+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
-+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
-+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh)
-+
-+#define HUBP_MASK_SH_LIST_DCN10(mask_sh)\
-+	HUBP_MASK_SH_LIST_DCN(mask_sh),\
-+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
-+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
-+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
-+	HUBP_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\
-+	HUBP_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
-+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
-+	HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
-+	HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
-+	HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
-+	HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
-+	HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
-+	HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
-+	HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
-+	HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
-+	HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
-+	HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
-+	HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
-+	HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
-+	HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
-+	HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
-+	HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
-+	HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
-+
-+
-+#define DCN_HUBP_REG_FIELD_LIST(type) \
-+	type HUBP_BLANK_EN;\
-+	type HUBP_TTU_DISABLE;\
-+	type HUBP_NO_OUTSTANDING_REQ;\
-+	type HUBP_UNDERFLOW_STATUS;\
-+	type NUM_PIPES;\
-+	type NUM_BANKS;\
-+	type PIPE_INTERLEAVE;\
-+	type NUM_SE;\
-+	type NUM_RB_PER_SE;\
-+	type MAX_COMPRESSED_FRAGS;\
-+	type SW_MODE;\
-+	type META_LINEAR;\
-+	type RB_ALIGNED;\
-+	type PIPE_ALIGNED;\
-+	type PITCH;\
-+	type META_PITCH;\
-+	type PITCH_C;\
-+	type META_PITCH_C;\
-+	type ROTATION_ANGLE;\
-+	type H_MIRROR_EN;\
-+	type SURFACE_PIXEL_FORMAT;\
-+	type SURFACE_FLIP_TYPE;\
-+	type SURFACE_UPDATE_LOCK;\
-+	type SURFACE_FLIP_PENDING;\
-+	type PRI_VIEWPORT_WIDTH; \
-+	type PRI_VIEWPORT_HEIGHT; \
-+	type PRI_VIEWPORT_X_START; \
-+	type PRI_VIEWPORT_Y_START; \
-+	type SEC_VIEWPORT_WIDTH; \
-+	type SEC_VIEWPORT_HEIGHT; \
-+	type SEC_VIEWPORT_X_START; \
-+	type SEC_VIEWPORT_Y_START; \
-+	type PRI_VIEWPORT_WIDTH_C; \
-+	type PRI_VIEWPORT_HEIGHT_C; \
-+	type PRI_VIEWPORT_X_START_C; \
-+	type PRI_VIEWPORT_Y_START_C; \
-+	type PRIMARY_SURFACE_ADDRESS_HIGH;\
-+	type PRIMARY_SURFACE_ADDRESS;\
-+	type SECONDARY_SURFACE_ADDRESS_HIGH;\
-+	type SECONDARY_SURFACE_ADDRESS;\
-+	type PRIMARY_META_SURFACE_ADDRESS_HIGH;\
-+	type PRIMARY_META_SURFACE_ADDRESS;\
-+	type SECONDARY_META_SURFACE_ADDRESS_HIGH;\
-+	type SECONDARY_META_SURFACE_ADDRESS;\
-+	type PRIMARY_SURFACE_ADDRESS_HIGH_C;\
-+	type PRIMARY_SURFACE_ADDRESS_C;\
-+	type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\
-+	type PRIMARY_META_SURFACE_ADDRESS_C;\
-+	type SURFACE_INUSE_ADDRESS;\
-+	type SURFACE_INUSE_ADDRESS_HIGH;\
-+	type SURFACE_INUSE_ADDRESS_C;\
-+	type SURFACE_INUSE_ADDRESS_HIGH_C;\
-+	type SURFACE_EARLIEST_INUSE_ADDRESS;\
-+	type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\
-+	type SURFACE_EARLIEST_INUSE_ADDRESS_C;\
-+	type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\
-+	type PRIMARY_SURFACE_TMZ;\
-+	type PRIMARY_SURFACE_DCC_EN;\
-+	type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
-+	type DET_BUF_PLANE1_BASE_ADDRESS;\
-+	type CROSSBAR_SRC_CB_B;\
-+	type CROSSBAR_SRC_CR_R;\
-+	type DRQ_EXPANSION_MODE;\
-+	type PRQ_EXPANSION_MODE;\
-+	type MRQ_EXPANSION_MODE;\
-+	type CRQ_EXPANSION_MODE;\
-+	type CHUNK_SIZE;\
-+	type MIN_CHUNK_SIZE;\
-+	type META_CHUNK_SIZE;\
-+	type MIN_META_CHUNK_SIZE;\
-+	type DPTE_GROUP_SIZE;\
-+	type MPTE_GROUP_SIZE;\
-+	type SWATH_HEIGHT;\
-+	type PTE_ROW_HEIGHT_LINEAR;\
-+	type CHUNK_SIZE_C;\
-+	type MIN_CHUNK_SIZE_C;\
-+	type META_CHUNK_SIZE_C;\
-+	type MIN_META_CHUNK_SIZE_C;\
-+	type DPTE_GROUP_SIZE_C;\
-+	type MPTE_GROUP_SIZE_C;\
-+	type SWATH_HEIGHT_C;\
-+	type PTE_ROW_HEIGHT_LINEAR_C;\
-+	type REFCYC_H_BLANK_END;\
-+	type DLG_V_BLANK_END;\
-+	type MIN_DST_Y_NEXT_START;\
-+	type REFCYC_PER_HTOTAL;\
-+	type REFCYC_X_AFTER_SCALER;\
-+	type DST_Y_AFTER_SCALER;\
-+	type DST_Y_PREFETCH;\
-+	type VRATIO_PREFETCH;\
-+	type DST_Y_PER_VM_VBLANK;\
-+	type DST_Y_PER_ROW_VBLANK;\
-+	type REF_FREQ_TO_PIX_FREQ;\
-+	type REFCYC_PER_PTE_GROUP_VBLANK_L;\
-+	type REFCYC_PER_META_CHUNK_VBLANK_L;\
-+	type DST_Y_PER_PTE_ROW_NOM_L;\
-+	type REFCYC_PER_PTE_GROUP_NOM_L;\
-+	type DST_Y_PER_META_ROW_NOM_L;\
-+	type REFCYC_PER_META_CHUNK_NOM_L;\
-+	type REFCYC_PER_LINE_DELIVERY_PRE_L;\
-+	type REFCYC_PER_LINE_DELIVERY_PRE_C;\
-+	type REFCYC_PER_LINE_DELIVERY_L;\
-+	type REFCYC_PER_LINE_DELIVERY_C;\
-+	type VRATIO_PREFETCH_C;\
-+	type REFCYC_PER_PTE_GROUP_VBLANK_C;\
-+	type REFCYC_PER_META_CHUNK_VBLANK_C;\
-+	type DST_Y_PER_PTE_ROW_NOM_C;\
-+	type REFCYC_PER_PTE_GROUP_NOM_C;\
-+	type DST_Y_PER_META_ROW_NOM_C;\
-+	type REFCYC_PER_META_CHUNK_NOM_C;\
-+	type QoS_LEVEL_LOW_WM;\
-+	type QoS_LEVEL_HIGH_WM;\
-+	type MIN_TTU_VBLANK;\
-+	type QoS_LEVEL_FLIP;\
-+	type REFCYC_PER_REQ_DELIVERY;\
-+	type QoS_LEVEL_FIXED;\
-+	type QoS_RAMP_DISABLE;\
-+	type REFCYC_PER_REQ_DELIVERY_PRE;\
-+	type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;\
-+	type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;\
-+	type VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;\
-+	type VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;\
-+	type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\
-+	type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\
-+	type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
-+	type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM;\
-+	type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\
-+	type ENABLE_L1_TLB;\
-+	type SYSTEM_ACCESS_MODE;\
-+	type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
-+	type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
-+	type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
-+	type MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;\
-+	type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\
-+	type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\
-+	type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\
-+	type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\
-+	type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\
-+	type SDPIF_FB_TOP;\
-+	type SDPIF_FB_BASE;\
-+	type SDPIF_FB_OFFSET;\
-+	type SDPIF_AGP_BASE;\
-+	type SDPIF_AGP_BOT;\
-+	type SDPIF_AGP_TOP;\
-+	type FB_TOP;\
-+	type FB_BASE;\
-+	type FB_OFFSET;\
-+	type AGP_BASE;\
-+	type AGP_BOT;\
-+	type AGP_TOP;\
-+	/* todo:  get these from GVM instead of reading registers ourselves */\
-+	type PAGE_DIRECTORY_ENTRY_HI32;\
-+	type PAGE_DIRECTORY_ENTRY_LO32;\
-+	type LOGICAL_PAGE_NUMBER_HI4;\
-+	type LOGICAL_PAGE_NUMBER_LO32;\
-+	type PHYSICAL_PAGE_ADDR_HI4;\
-+	type PHYSICAL_PAGE_ADDR_LO32;\
-+	type PHYSICAL_PAGE_NUMBER_MSB;\
-+	type PHYSICAL_PAGE_NUMBER_LSB;\
-+	type LOGICAL_ADDR;\
-+	type CURSOR0_DST_Y_OFFSET; \
-+	type CURSOR0_CHUNK_HDL_ADJUST; \
-+	type CURSOR_SURFACE_ADDRESS_HIGH; \
-+	type CURSOR_SURFACE_ADDRESS; \
-+	type CURSOR_WIDTH; \
-+	type CURSOR_HEIGHT; \
-+	type CURSOR_MODE; \
-+	type CURSOR_2X_MAGNIFY; \
-+	type CURSOR_PITCH; \
-+	type CURSOR_LINES_PER_CHUNK; \
-+	type CURSOR_ENABLE; \
-+	type CURSOR_X_POSITION; \
-+	type CURSOR_Y_POSITION; \
-+	type CURSOR_HOT_SPOT_X; \
-+	type CURSOR_HOT_SPOT_Y; \
-+	type CURSOR_DST_X_OFFSET; \
-+	type OUTPUT_FP
-+
-+struct dcn_mi_shift {
-+	DCN_HUBP_REG_FIELD_LIST(uint8_t);
-+};
-+
-+struct dcn_mi_mask {
-+	DCN_HUBP_REG_FIELD_LIST(uint32_t);
-+};
-+
-+struct dcn10_hubp {
-+	struct hubp base;
-+	const struct dcn_mi_registers *hubp_regs;
-+	const struct dcn_mi_shift *hubp_shift;
-+	const struct dcn_mi_mask *hubp_mask;
-+};
-+
-+void hubp1_program_surface_config(
-+	struct hubp *hubp,
-+	enum surface_pixel_format format,
-+	union dc_tiling_info *tiling_info,
-+	union plane_size *plane_size,
-+	enum dc_rotation_angle rotation,
-+	struct dc_plane_dcc_param *dcc,
-+	bool horizontal_mirror);
-+
-+void hubp1_program_deadline(
-+		struct hubp *hubp,
-+		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
-+		struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
-+
-+void hubp1_program_requestor(
-+		struct hubp *hubp,
-+		struct _vcs_dpi_display_rq_regs_st *rq_regs);
-+
-+void hubp1_program_pixel_format(
-+	struct dcn10_hubp *hubp,
-+	enum surface_pixel_format format);
-+
-+void hubp1_program_size_and_rotation(
-+	struct dcn10_hubp *hubp,
-+	enum dc_rotation_angle rotation,
-+	enum surface_pixel_format format,
-+	const union plane_size *plane_size,
-+	struct dc_plane_dcc_param *dcc,
-+	bool horizontal_mirror);
-+
-+void hubp1_program_tiling(
-+	struct dcn10_hubp *hubp,
-+	const union dc_tiling_info *info,
-+	const enum surface_pixel_format pixel_format);
-+
-+void hubp1_dcc_control(struct hubp *hubp,
-+		bool enable,
-+		bool independent_64b_blks);
-+
-+bool hubp1_program_surface_flip_and_addr(
-+	struct hubp *hubp,
-+	const struct dc_plane_address *address,
-+	bool flip_immediate);
-+
-+bool hubp1_is_flip_pending(struct hubp *hubp);
-+
-+void hubp1_cursor_set_attributes(
-+		struct hubp *hubp,
-+		const struct dc_cursor_attributes *attr);
-+
-+void hubp1_cursor_set_position(
-+		struct hubp *hubp,
-+		const struct dc_cursor_position *pos,
-+		const struct dc_cursor_mi_param *param);
-+
-+void hubp1_set_blank(struct hubp *hubp, bool blank);
-+
-+void min_set_viewport(struct hubp *hubp,
-+		const struct rect *viewport,
-+		const struct rect *viewport_c);
-+
-+void dcn10_hubp_construct(
-+	struct dcn10_hubp *hubp1,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dcn_mi_registers *hubp_regs,
-+	const struct dcn_mi_shift *hubp_shift,
-+	const struct dcn_mi_mask *hubp_mask);
-+
-+
-+struct dcn_hubp_state {
-+	uint32_t pixel_format;
-+	uint32_t inuse_addr_hi;
-+	uint32_t viewport_width;
-+	uint32_t viewport_height;
-+	uint32_t rotation_angle;
-+	uint32_t h_mirror_en;
-+	uint32_t sw_mode;
-+	uint32_t dcc_en;
-+	uint32_t blank_en;
-+	uint32_t underflow_status;
-+	uint32_t ttu_disable;
-+	uint32_t min_ttu_vblank;
-+	uint32_t qos_level_low_wm;
-+	uint32_t qos_level_high_wm;
-+};
-+void hubp1_read_state(struct dcn10_hubp *hubp1,
-+		struct dcn_hubp_state *s);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c.0130~	2017-12-14 06:39:58.422903572 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c	2017-12-14 06:39:58.422903572 +0100
-@@ -0,0 +1,2520 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "core_types.h"
-+#include "resource.h"
-+#include "custom_float.h"
-+#include "dcn10_hw_sequencer.h"
-+#include "dce110/dce110_hw_sequencer.h"
-+#include "dce/dce_hwseq.h"
-+#include "abm.h"
-+#include "dmcu.h"
-+#include "dcn10/dcn10_timing_generator.h"
-+#include "dcn10/dcn10_dpp.h"
-+#include "dcn10/dcn10_mpc.h"
-+#include "timing_generator.h"
-+#include "opp.h"
-+#include "ipp.h"
-+#include "mpc.h"
-+#include "reg_helper.h"
-+#include "custom_float.h"
-+#include "dcn10_hubp.h"
-+#include "dcn10_hubbub.h"
-+
-+#define CTX \
-+	hws->ctx
-+#define REG(reg)\
-+	hws->regs->reg
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	hws->shifts->field_name, hws->masks->field_name
-+
-+#define DTN_INFO_MICRO_SEC(ref_cycle) \
-+	print_microsec(dc_ctx, ref_cycle)
-+
-+void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
-+{
-+	static const uint32_t ref_clk_mhz = 48;
-+	static const unsigned int frac = 10;
-+	uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
-+
-+	DTN_INFO("%d.%d \t ",
-+			us_x10 / frac,
-+			us_x10 % frac);
-+}
-+
-+
-+static void log_mpc_crc(struct dc *dc)
-+{
-+	struct dc_context *dc_ctx = dc->ctx;
-+	struct dce_hwseq *hws = dc->hwseq;
-+
-+	if (REG(MPC_CRC_RESULT_GB))
-+		DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
-+		REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
-+	if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
-+		DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
-+		REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
-+}
-+
-+void dcn10_log_hubbub_state(struct dc *dc)
-+{
-+	struct dc_context *dc_ctx = dc->ctx;
-+	struct dcn_hubbub_wm wm;
-+	int i;
-+
-+	hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
-+
-+	DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
-+			"sr_enter \t sr_exit \t dram_clk_change \n");
-+
-+	for (i = 0; i < 4; i++) {
-+		struct dcn_hubbub_wm_set *s;
-+
-+		s = &wm.sets[i];
-+		DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
-+		DTN_INFO_MICRO_SEC(s->data_urgent);
-+		DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
-+		DTN_INFO_MICRO_SEC(s->sr_enter);
-+		DTN_INFO_MICRO_SEC(s->sr_exit);
-+		DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
-+		DTN_INFO("\n");
-+	}
-+
-+	DTN_INFO("\n");
-+}
-+
-+void dcn10_log_hw_state(struct dc *dc)
-+{
-+	struct dc_context *dc_ctx = dc->ctx;
-+	struct resource_pool *pool = dc->res_pool;
-+	int i;
-+
-+	DTN_INFO_BEGIN();
-+
-+	dcn10_log_hubbub_state(dc);
-+
-+	DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
-+			"rotation \t mirror \t  sw_mode \t "
-+			"dcc_en \t blank_en \t ttu_dis \t underflow \t "
-+			"min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
-+
-+	for (i = 0; i < pool->pipe_count; i++) {
-+		struct hubp *hubp = pool->hubps[i];
-+		struct dcn_hubp_state s;
-+
-+		hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
-+
-+		DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
-+				"%xh \t %xh \t %xh \t "
-+				"%d \t %d \t %d \t %xh \t",
-+				i,
-+				s.pixel_format,
-+				s.inuse_addr_hi,
-+				s.viewport_width,
-+				s.viewport_height,
-+				s.rotation_angle,
-+				s.h_mirror_en,
-+				s.sw_mode,
-+				s.dcc_en,
-+				s.blank_en,
-+				s.ttu_disable,
-+				s.underflow_status);
-+		DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
-+		DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
-+		DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
-+		DTN_INFO("\n");
-+	}
-+	DTN_INFO("\n");
-+
-+	DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
-+			"h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
-+
-+	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
-+		struct timing_generator *tg = pool->timing_generators[i];
-+		struct dcn_otg_state s = {0};
-+
-+		tgn10_read_otg_state(DCN10TG_FROM_TG(tg), &s);
-+
-+		//only print if OTG master is enabled
-+		if ((s.otg_enabled & 1) == 0)
-+			continue;
-+
-+		DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
-+				"%d \t %d \t %d \t %d \t %d \t %d \t "
-+				"%d \t %d \t %d \t %d \t %d \t ",
-+				i,
-+				s.v_blank_start,
-+				s.v_blank_end,
-+				s.v_sync_a_start,
-+				s.v_sync_a_end,
-+				s.v_sync_a_pol,
-+				s.v_total_max,
-+				s.v_total_min,
-+				s.h_blank_start,
-+				s.h_blank_end,
-+				s.h_sync_a_start,
-+				s.h_sync_a_end,
-+				s.h_sync_a_pol,
-+				s.h_total,
-+				s.v_total,
-+				s.underflow_occurred_status);
-+		DTN_INFO("\n");
-+	}
-+	DTN_INFO("\n");
-+
-+	log_mpc_crc(dc);
-+
-+	DTN_INFO_END();
-+}
-+
-+static void enable_dppclk(
-+	struct dce_hwseq *hws,
-+	uint8_t plane_id,
-+	uint32_t requested_pix_clk,
-+	bool dppclk_div)
-+{
-+	dm_logger_write(hws->ctx->logger, LOG_SURFACE,
-+			"dppclk_rate_control for pipe %d programed to %d\n",
-+			plane_id,
-+			dppclk_div);
-+
-+	if (hws->shifts->DPPCLK_RATE_CONTROL)
-+		REG_UPDATE_2(DPP_CONTROL[plane_id],
-+			DPPCLK_RATE_CONTROL, dppclk_div,
-+			DPP_CLOCK_ENABLE, 1);
-+	else
-+		REG_UPDATE(DPP_CONTROL[plane_id],
-+			DPP_CLOCK_ENABLE, 1);
-+}
-+
-+static void enable_power_gating_plane(
-+	struct dce_hwseq *hws,
-+	bool enable)
-+{
-+	bool force_on = 1; /* disable power gating */
-+
-+	if (enable)
-+		force_on = 0;
-+
-+	/* DCHUBP0/1/2/3 */
-+	REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
-+	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
-+	REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
-+	REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
-+
-+	/* DPP0/1/2/3 */
-+	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
-+	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
-+	REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
-+	REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
-+}
-+
-+static void disable_vga(
-+	struct dce_hwseq *hws)
-+{
-+	REG_WRITE(D1VGA_CONTROL, 0);
-+	REG_WRITE(D2VGA_CONTROL, 0);
-+	REG_WRITE(D3VGA_CONTROL, 0);
-+	REG_WRITE(D4VGA_CONTROL, 0);
-+}
-+
-+static void dpp_pg_control(
-+		struct dce_hwseq *hws,
-+		unsigned int dpp_inst,
-+		bool power_on)
-+{
-+	uint32_t power_gate = power_on ? 0 : 1;
-+	uint32_t pwr_status = power_on ? 0 : 2;
-+
-+	if (hws->ctx->dc->debug.disable_dpp_power_gate)
-+		return;
-+
-+	switch (dpp_inst) {
-+	case 0: /* DPP0 */
-+		REG_UPDATE(DOMAIN1_PG_CONFIG,
-+				DOMAIN1_POWER_GATE, power_gate);
-+
-+		REG_WAIT(DOMAIN1_PG_STATUS,
-+				DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
-+				1, 1000);
-+		break;
-+	case 1: /* DPP1 */
-+		REG_UPDATE(DOMAIN3_PG_CONFIG,
-+				DOMAIN3_POWER_GATE, power_gate);
-+
-+		REG_WAIT(DOMAIN3_PG_STATUS,
-+				DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
-+				1, 1000);
-+		break;
-+	case 2: /* DPP2 */
-+		REG_UPDATE(DOMAIN5_PG_CONFIG,
-+				DOMAIN5_POWER_GATE, power_gate);
-+
-+		REG_WAIT(DOMAIN5_PG_STATUS,
-+				DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
-+				1, 1000);
-+		break;
-+	case 3: /* DPP3 */
-+		REG_UPDATE(DOMAIN7_PG_CONFIG,
-+				DOMAIN7_POWER_GATE, power_gate);
-+
-+		REG_WAIT(DOMAIN7_PG_STATUS,
-+				DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
-+				1, 1000);
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+}
-+
-+static void hubp_pg_control(
-+		struct dce_hwseq *hws,
-+		unsigned int hubp_inst,
-+		bool power_on)
-+{
-+	uint32_t power_gate = power_on ? 0 : 1;
-+	uint32_t pwr_status = power_on ? 0 : 2;
-+
-+	if (hws->ctx->dc->debug.disable_hubp_power_gate)
-+		return;
-+
-+	switch (hubp_inst) {
-+	case 0: /* DCHUBP0 */
-+		REG_UPDATE(DOMAIN0_PG_CONFIG,
-+				DOMAIN0_POWER_GATE, power_gate);
-+
-+		REG_WAIT(DOMAIN0_PG_STATUS,
-+				DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
-+				1, 1000);
-+		break;
-+	case 1: /* DCHUBP1 */
-+		REG_UPDATE(DOMAIN2_PG_CONFIG,
-+				DOMAIN2_POWER_GATE, power_gate);
-+
-+		REG_WAIT(DOMAIN2_PG_STATUS,
-+				DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
-+				1, 1000);
-+		break;
-+	case 2: /* DCHUBP2 */
-+		REG_UPDATE(DOMAIN4_PG_CONFIG,
-+				DOMAIN4_POWER_GATE, power_gate);
-+
-+		REG_WAIT(DOMAIN4_PG_STATUS,
-+				DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
-+				1, 1000);
-+		break;
-+	case 3: /* DCHUBP3 */
-+		REG_UPDATE(DOMAIN6_PG_CONFIG,
-+				DOMAIN6_POWER_GATE, power_gate);
-+
-+		REG_WAIT(DOMAIN6_PG_STATUS,
-+				DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
-+				1, 1000);
-+		break;
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		break;
-+	}
-+}
-+
-+static void power_on_plane(
-+	struct dce_hwseq *hws,
-+	int plane_id)
-+{
-+	if (REG(DC_IP_REQUEST_CNTL)) {
-+		REG_SET(DC_IP_REQUEST_CNTL, 0,
-+				IP_REQUEST_EN, 1);
-+		dpp_pg_control(hws, plane_id, true);
-+		hubp_pg_control(hws, plane_id, true);
-+		REG_SET(DC_IP_REQUEST_CNTL, 0,
-+				IP_REQUEST_EN, 0);
-+		dm_logger_write(hws->ctx->logger, LOG_DEBUG,
-+				"Un-gated front end for pipe %d\n", plane_id);
-+	}
-+}
-+
-+static void undo_DEGVIDCN10_253_wa(struct dc *dc)
-+{
-+	struct dce_hwseq *hws = dc->hwseq;
-+	struct hubp *hubp = dc->res_pool->hubps[0];
-+
-+	if (!hws->wa_state.DEGVIDCN10_253_applied)
-+		return;
-+
-+	hubp->funcs->set_blank(hubp, true);
-+
-+	REG_SET(DC_IP_REQUEST_CNTL, 0,
-+			IP_REQUEST_EN, 1);
-+
-+	hubp_pg_control(hws, 0, false);
-+	REG_SET(DC_IP_REQUEST_CNTL, 0,
-+			IP_REQUEST_EN, 0);
-+
-+	hws->wa_state.DEGVIDCN10_253_applied = false;
-+}
-+
-+static void apply_DEGVIDCN10_253_wa(struct dc *dc)
-+{
-+	struct dce_hwseq *hws = dc->hwseq;
-+	struct hubp *hubp = dc->res_pool->hubps[0];
-+	int i;
-+
-+	if (dc->debug.disable_stutter)
-+		return;
-+
-+	if (!hws->wa.DEGVIDCN10_253)
-+		return;
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		if (!dc->res_pool->hubps[i]->power_gated)
-+			return;
-+	}
-+
-+	/* all pipe power gated, apply work around to enable stutter. */
-+
-+	REG_SET(DC_IP_REQUEST_CNTL, 0,
-+			IP_REQUEST_EN, 1);
-+
-+	hubp_pg_control(hws, 0, true);
-+	REG_SET(DC_IP_REQUEST_CNTL, 0,
-+			IP_REQUEST_EN, 0);
-+
-+	hubp->funcs->set_hubp_blank_en(hubp, false);
-+	hws->wa_state.DEGVIDCN10_253_applied = true;
-+}
-+
-+static void bios_golden_init(struct dc *dc)
-+{
-+	struct dc_bios *bp = dc->ctx->dc_bios;
-+	int i;
-+
-+	/* initialize dcn global */
-+	bp->funcs->enable_disp_power_gating(bp,
-+			CONTROLLER_ID_D0, ASIC_PIPE_INIT);
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		/* initialize dcn per pipe */
-+		bp->funcs->enable_disp_power_gating(bp,
-+				CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
-+	}
-+}
-+
-+static enum dc_status dcn10_prog_pixclk_crtc_otg(
-+		struct pipe_ctx *pipe_ctx,
-+		struct dc_state *context,
-+		struct dc *dc)
-+{
-+	struct dc_stream_state *stream = pipe_ctx->stream;
-+	enum dc_color_space color_space;
-+	struct tg_color black_color = {0};
-+	bool enableStereo    = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
-+			false:true;
-+	bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY;
-+
-+	/* by upper caller loop, pipe0 is parent pipe and be called first.
-+	 * back end is set up by for pipe0. Other children pipe share back end
-+	 * with pipe 0. No program is needed.
-+	 */
-+	if (pipe_ctx->top_pipe != NULL)
-+		return DC_OK;
-+
-+	/* TODO check if timing_changed, disable stream if timing changed */
-+
-+	/* HW program guide assume display already disable
-+	 * by unplug sequence. OTG assume stop.
-+	 */
-+	pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
-+
-+	if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
-+			pipe_ctx->clock_source,
-+			&pipe_ctx->stream_res.pix_clk_params,
-+			&pipe_ctx->pll_settings)) {
-+		BREAK_TO_DEBUGGER();
-+		return DC_ERROR_UNEXPECTED;
-+	}
-+	pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
-+	pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
-+	pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
-+	pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
-+
-+	pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
-+
-+	pipe_ctx->stream_res.tg->funcs->program_timing(
-+			pipe_ctx->stream_res.tg,
-+			&stream->timing,
-+			true);
-+
-+	pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity(
-+				pipe_ctx->stream_res.opp,
-+				enableStereo,
-+				rightEyePolarity);
-+
-+#if 0 /* move to after enable_crtc */
-+	/* TODO: OPP FMT, ABM. etc. should be done here. */
-+	/* or FPGA now. instance 0 only. TODO: move to opp.c */
-+
-+	inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
-+
-+	pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
-+				pipe_ctx->stream_res.opp,
-+				&stream->bit_depth_params,
-+				&stream->clamping);
-+#endif
-+	/* program otg blank color */
-+	color_space = stream->output_color_space;
-+	color_space_to_black_color(dc, color_space, &black_color);
-+	pipe_ctx->stream_res.tg->funcs->set_blank_color(
-+			pipe_ctx->stream_res.tg,
-+			&black_color);
-+
-+	pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
-+	hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
-+
-+	/* VTG is  within DCHUB command block. DCFCLK is always on */
-+	if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
-+		BREAK_TO_DEBUGGER();
-+		return DC_ERROR_UNEXPECTED;
-+	}
-+
-+	/* TODO program crtc source select for non-virtual signal*/
-+	/* TODO program FMT */
-+	/* TODO setup link_enc */
-+	/* TODO set stream attributes */
-+	/* TODO program audio */
-+	/* TODO enable stream if timing changed */
-+	/* TODO unblank stream if DP */
-+
-+	return DC_OK;
-+}
-+
-+static void reset_back_end_for_pipe(
-+		struct dc *dc,
-+		struct pipe_ctx *pipe_ctx,
-+		struct dc_state *context)
-+{
-+	int i;
-+
-+	if (pipe_ctx->stream_res.stream_enc == NULL) {
-+		pipe_ctx->stream = NULL;
-+		return;
-+	}
-+
-+	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
-+		/* DPMS may already disable */
-+		if (!pipe_ctx->stream->dpms_off)
-+			core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
-+	}
-+
-+	/* by upper caller loop, parent pipe: pipe0, will be reset last.
-+	 * back end share by all pipes and will be disable only when disable
-+	 * parent pipe.
-+	 */
-+	if (pipe_ctx->top_pipe == NULL) {
-+		pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
-+
-+		pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
-+	}
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++)
-+		if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
-+			break;
-+
-+	if (i == dc->res_pool->pipe_count)
-+		return;
-+
-+	pipe_ctx->stream = NULL;
-+	dm_logger_write(dc->ctx->logger, LOG_DEBUG,
-+					"Reset back end for pipe %d, tg:%d\n",
-+					pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
-+}
-+
-+static void dcn10_verify_allow_pstate_change_high(struct dc *dc)
-+{
-+	static bool should_log_hw_state; /* prevent hw state log by default */
-+
-+	if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
-+		if (should_log_hw_state) {
-+			dcn10_log_hw_state(dc);
-+		}
-+
-+		BREAK_TO_DEBUGGER();
-+	}
-+}
-+
-+/* trigger HW to start disconnect plane from stream on the next vsync */
-+static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
-+{
-+	int fe_idx = pipe_ctx->pipe_idx;
-+	struct hubp *hubp = dc->res_pool->hubps[fe_idx];
-+	struct mpc *mpc = dc->res_pool->mpc;
-+	int opp_id, z_idx;
-+	int mpcc_id = -1;
-+
-+	/* look at tree rather than mi here to know if we already reset */
-+	for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
-+		struct output_pixel_processor *opp = dc->res_pool->opps[opp_id];
-+
-+		for (z_idx = 0; z_idx < opp->mpc_tree.num_pipes; z_idx++) {
-+			if (opp->mpc_tree.dpp[z_idx] == fe_idx) {
-+				mpcc_id = opp->mpc_tree.mpcc[z_idx];
-+				break;
-+			}
-+		}
-+		if (mpcc_id != -1)
-+			break;
-+	}
-+	/*Already reset*/
-+	if (opp_id == dc->res_pool->pipe_count)
-+		return;
-+
-+	mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree),
-+					dc->res_pool->opps[opp_id]->inst, fe_idx);
-+
-+	if (hubp->funcs->hubp_disconnect)
-+		hubp->funcs->hubp_disconnect(hubp);
-+
-+	if (dc->debug.sanity_checks)
-+		dcn10_verify_allow_pstate_change_high(dc);
-+
-+	pipe_ctx->stream = NULL;
-+	memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
-+	memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
-+	pipe_ctx->top_pipe = NULL;
-+	pipe_ctx->bottom_pipe = NULL;
-+	pipe_ctx->plane_state = NULL;
-+}
-+
-+static void plane_atomic_power_down(struct dc *dc, int fe_idx)
-+{
-+	struct dce_hwseq *hws = dc->hwseq;
-+	struct dpp *dpp = dc->res_pool->dpps[fe_idx];
-+
-+	if (REG(DC_IP_REQUEST_CNTL)) {
-+		REG_SET(DC_IP_REQUEST_CNTL, 0,
-+				IP_REQUEST_EN, 1);
-+		dpp_pg_control(hws, fe_idx, false);
-+		hubp_pg_control(hws, fe_idx, false);
-+		dpp->funcs->dpp_reset(dpp);
-+		REG_SET(DC_IP_REQUEST_CNTL, 0,
-+				IP_REQUEST_EN, 0);
-+		dm_logger_write(dc->ctx->logger, LOG_DEBUG,
-+				"Power gated front end %d\n", fe_idx);
-+	}
-+}
-+
-+/* disable HW used by plane.
-+ * note:  cannot disable until disconnect is complete
-+ */
-+static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
-+{
-+	int fe_idx = pipe_ctx->pipe_idx;
-+	struct dce_hwseq *hws = dc->hwseq;
-+	struct hubp *hubp = dc->res_pool->hubps[fe_idx];
-+	struct mpc *mpc = dc->res_pool->mpc;
-+	int opp_id = hubp->opp_id;
-+	struct output_pixel_processor *opp;
-+
-+	if (opp_id != 0xf) {
-+		mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id);
-+		opp = dc->res_pool->opps[hubp->opp_id];
-+		opp->mpcc_disconnect_pending[hubp->mpcc_id] = false;
-+		hubp->funcs->set_blank(hubp, true);
-+	}
-+
-+	REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
-+			HUBP_CLOCK_ENABLE, 0);
-+	REG_UPDATE(DPP_CONTROL[fe_idx],
-+			DPP_CLOCK_ENABLE, 0);
-+
-+	if (opp_id != 0xf && dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0)
-+		REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
-+				OPP_PIPE_CLOCK_EN, 0);
-+
-+	hubp->power_gated = true;
-+
-+	plane_atomic_power_down(dc, fe_idx);
-+}
-+
-+static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
-+{
-+	if (dc->res_pool->hubps[pipe_ctx->pipe_idx]->power_gated)
-+		return;
-+
-+	plane_atomic_disable(dc, pipe_ctx);
-+
-+	apply_DEGVIDCN10_253_wa(dc);
-+
-+	dm_logger_write(dc->ctx->logger, LOG_DC,
-+					"Power down front end %d\n",
-+					pipe_ctx->pipe_idx);
-+}
-+
-+static void dcn10_init_hw(struct dc *dc)
-+{
-+	int i;
-+	struct abm *abm = dc->res_pool->abm;
-+	struct dmcu *dmcu = dc->res_pool->dmcu;
-+	struct dce_hwseq *hws = dc->hwseq;
-+	struct dc_bios *dcb = dc->ctx->dc_bios;
-+	struct dc_state  *context = dc->current_state;
-+
-+	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
-+		REG_WRITE(REFCLK_CNTL, 0);
-+		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
-+		REG_WRITE(DIO_MEM_PWR_CTRL, 0);
-+
-+		if (!dc->debug.disable_clock_gate) {
-+			/* enable all DCN clock gating */
-+			REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
-+
-+			REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
-+
-+			REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
-+		}
-+
-+		enable_power_gating_plane(dc->hwseq, true);
-+		return;
-+	}
-+	/* end of FPGA. Below if real ASIC */
-+
-+	if (!dcb->funcs->is_accelerated_mode(dcb)) {
-+		bios_golden_init(dc);
-+		disable_vga(dc->hwseq);
-+	}
-+
-+	for (i = 0; i < dc->link_count; i++) {
-+		/* Power up AND update implementation according to the
-+		 * required signal (which may be different from the
-+		 * default signal on connector).
-+		 */
-+		struct dc_link *link = dc->links[i];
-+
-+		if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
-+			dc->hwss.edp_power_control(link, true);
-+
-+		link->link_enc->funcs->hw_init(link->link_enc);
-+	}
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
-+
-+		if (tg->funcs->is_tg_enabled(tg))
-+			tg->funcs->lock(tg);
-+	}
-+
-+	/* Blank controller using driver code instead of
-+	 * command table.
-+	 */
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
-+
-+		if (tg->funcs->is_tg_enabled(tg)) {
-+			tg->funcs->set_blank(tg, true);
-+			hwss_wait_for_blank_complete(tg);
-+		}
-+	}
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+		pipe_ctx->stream_res.tg = tg;
-+		pipe_ctx->pipe_idx = i;
-+		pipe_ctx->plane_res.hubp = dc->res_pool->hubps[i];
-+		pipe_ctx->plane_res.hubp->mpcc_id = i;
-+		pipe_ctx->plane_res.hubp->opp_id =
-+				dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i);
-+
-+		plane_atomic_disconnect(dc, pipe_ctx);
-+	}
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
-+
-+		if (tg->funcs->is_tg_enabled(tg))
-+			tg->funcs->unlock(tg);
-+	}
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+		dcn10_disable_plane(dc, pipe_ctx);
-+
-+		pipe_ctx->stream_res.tg = NULL;
-+		pipe_ctx->plane_res.hubp = NULL;
-+
-+		tg->funcs->tg_init(tg);
-+	}
-+
-+	for (i = 0; i < dc->res_pool->audio_count; i++) {
-+		struct audio *audio = dc->res_pool->audios[i];
-+
-+		audio->funcs->hw_init(audio);
-+	}
-+
-+	if (abm != NULL) {
-+		abm->funcs->init_backlight(abm);
-+		abm->funcs->abm_init(abm);
-+	}
-+
-+	if (dmcu != NULL)
-+		dmcu->funcs->dmcu_init(dmcu);
-+
-+	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
-+	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
-+
-+	if (!dc->debug.disable_clock_gate) {
-+		/* enable all DCN clock gating */
-+		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
-+
-+		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
-+
-+		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
-+	}
-+
-+	enable_power_gating_plane(dc->hwseq, true);
-+}
-+
-+static void reset_hw_ctx_wrap(
-+		struct dc *dc,
-+		struct dc_state *context)
-+{
-+	int i;
-+
-+	/* Reset Back End*/
-+	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
-+		struct pipe_ctx *pipe_ctx_old =
-+			&dc->current_state->res_ctx.pipe_ctx[i];
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+		if (!pipe_ctx_old->stream)
-+			continue;
-+
-+		if (pipe_ctx_old->top_pipe)
-+			continue;
-+
-+		if (!pipe_ctx->stream ||
-+				pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
-+			struct clock_source *old_clk = pipe_ctx_old->clock_source;
-+
-+			reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
-+			if (old_clk)
-+				old_clk->funcs->cs_power_down(old_clk);
-+		}
-+	}
-+
-+}
-+
-+static bool patch_address_for_sbs_tb_stereo(
-+		struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
-+{
-+	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-+	bool sec_split = pipe_ctx->top_pipe &&
-+			pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
-+	if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
-+		(pipe_ctx->stream->timing.timing_3d_format ==
-+		 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
-+		 pipe_ctx->stream->timing.timing_3d_format ==
-+		 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
-+		*addr = plane_state->address.grph_stereo.left_addr;
-+		plane_state->address.grph_stereo.left_addr =
-+		plane_state->address.grph_stereo.right_addr;
-+		return true;
-+	} else {
-+		if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
-+			plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
-+			plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
-+			plane_state->address.grph_stereo.right_addr =
-+			plane_state->address.grph_stereo.left_addr;
-+		}
-+	}
-+	return false;
-+}
-+
-+
-+
-+static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
-+{
-+	bool addr_patched = false;
-+	PHYSICAL_ADDRESS_LOC addr;
-+	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-+
-+	if (plane_state == NULL)
-+		return;
-+	addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
-+	pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
-+			pipe_ctx->plane_res.hubp,
-+			&plane_state->address,
-+			plane_state->flip_immediate);
-+	plane_state->status.requested_address = plane_state->address;
-+	if (addr_patched)
-+		pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
-+}
-+
-+static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
-+					  const struct dc_plane_state *plane_state)
-+{
-+	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
-+	const struct dc_transfer_func *tf = NULL;
-+	bool result = true;
-+
-+	if (dpp_base == NULL)
-+		return false;
-+
-+	if (plane_state->in_transfer_func)
-+		tf = plane_state->in_transfer_func;
-+
-+	if (plane_state->gamma_correction && dce_use_lut(plane_state))
-+		dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
-+
-+	if (tf == NULL)
-+		dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
-+	else if (tf->type == TF_TYPE_PREDEFINED) {
-+		switch (tf->tf) {
-+		case TRANSFER_FUNCTION_SRGB:
-+			dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
-+			break;
-+		case TRANSFER_FUNCTION_BT709:
-+			dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
-+			break;
-+		case TRANSFER_FUNCTION_LINEAR:
-+			dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
-+			break;
-+		case TRANSFER_FUNCTION_PQ:
-+		default:
-+			result = false;
-+			break;
-+		}
-+	} else if (tf->type == TF_TYPE_BYPASS) {
-+		dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
-+	} else {
-+		/*TF_TYPE_DISTRIBUTED_POINTS*/
-+		result = false;
-+	}
-+
-+	return result;
-+}
-+/*modify the method to handle rgb for arr_points*/
-+static bool convert_to_custom_float(
-+		struct pwl_result_data *rgb_resulted,
-+		struct curve_points *arr_points,
-+		uint32_t hw_points_num)
-+{
-+	struct custom_float_format fmt;
-+
-+	struct pwl_result_data *rgb = rgb_resulted;
-+
-+	uint32_t i = 0;
-+
-+	fmt.exponenta_bits = 6;
-+	fmt.mantissa_bits = 12;
-+	fmt.sign = false;
-+
-+	if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
-+					    &arr_points[0].custom_float_x)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
-+					    &arr_points[0].custom_float_offset)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
-+					    &arr_points[0].custom_float_slope)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	fmt.mantissa_bits = 10;
-+	fmt.sign = false;
-+
-+	if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
-+					    &arr_points[1].custom_float_x)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
-+					    &arr_points[1].custom_float_y)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
-+					    &arr_points[1].custom_float_slope)) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	fmt.mantissa_bits = 12;
-+	fmt.sign = true;
-+
-+	while (i != hw_points_num) {
-+		if (!convert_to_custom_float_format(rgb->red, &fmt,
-+						    &rgb->red_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(rgb->green, &fmt,
-+						    &rgb->green_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(rgb->blue, &fmt,
-+						    &rgb->blue_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
-+						    &rgb->delta_red_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
-+						    &rgb->delta_green_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
-+						    &rgb->delta_blue_reg)) {
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+
-+		++rgb;
-+		++i;
-+	}
-+
-+	return true;
-+}
-+#define MAX_REGIONS_NUMBER 34
-+#define MAX_LOW_POINT      25
-+#define NUMBER_SEGMENTS    32
-+
-+static bool
-+dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
-+				     struct pwl_params *regamma_params)
-+{
-+	struct curve_points *arr_points;
-+	struct pwl_result_data *rgb_resulted;
-+	struct pwl_result_data *rgb;
-+	struct pwl_result_data *rgb_plus_1;
-+	struct fixed31_32 y_r;
-+	struct fixed31_32 y_g;
-+	struct fixed31_32 y_b;
-+	struct fixed31_32 y1_min;
-+	struct fixed31_32 y3_max;
-+
-+	int32_t segment_start, segment_end;
-+	int32_t i;
-+	uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
-+
-+	if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
-+		return false;
-+
-+	arr_points = regamma_params->arr_points;
-+	rgb_resulted = regamma_params->rgb_resulted;
-+	hw_points = 0;
-+
-+	memset(regamma_params, 0, sizeof(struct pwl_params));
-+	memset(seg_distr, 0, sizeof(seg_distr));
-+
-+	if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
-+		/* 32 segments
-+		 * segments are from 2^-25 to 2^7
-+		 */
-+		for (i = 0; i < 32 ; i++)
-+			seg_distr[i] = 3;
-+
-+		segment_start = -25;
-+		segment_end   = 7;
-+	} else {
-+		/* 10 segments
-+		 * segment is from 2^-10 to 2^0
-+		 * There are less than 256 points, for optimization
-+		 */
-+		seg_distr[0] = 3;
-+		seg_distr[1] = 4;
-+		seg_distr[2] = 4;
-+		seg_distr[3] = 4;
-+		seg_distr[4] = 4;
-+		seg_distr[5] = 4;
-+		seg_distr[6] = 4;
-+		seg_distr[7] = 4;
-+		seg_distr[8] = 5;
-+		seg_distr[9] = 5;
-+
-+		segment_start = -10;
-+		segment_end = 0;
-+	}
-+
-+	for (i = segment_end - segment_start; i < MAX_REGIONS_NUMBER ; i++)
-+		seg_distr[i] = -1;
-+
-+	for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
-+		if (seg_distr[k] != -1)
-+			hw_points += (1 << seg_distr[k]);
-+	}
-+
-+	j = 0;
-+	for (k = 0; k < (segment_end - segment_start); k++) {
-+		increment = NUMBER_SEGMENTS / (1 << seg_distr[k]);
-+		start_index = (segment_start + k + MAX_LOW_POINT) * NUMBER_SEGMENTS;
-+		for (i = start_index; i < start_index + NUMBER_SEGMENTS; i += increment) {
-+			if (j == hw_points - 1)
-+				break;
-+			rgb_resulted[j].red = output_tf->tf_pts.red[i];
-+			rgb_resulted[j].green = output_tf->tf_pts.green[i];
-+			rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
-+			j++;
-+		}
-+	}
-+
-+	/* last point */
-+	start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS;
-+	rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
-+	rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
-+	rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
-+
-+	arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-+					     dal_fixed31_32_from_int(segment_start));
-+	arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-+					     dal_fixed31_32_from_int(segment_end));
-+
-+	y_r = rgb_resulted[0].red;
-+	y_g = rgb_resulted[0].green;
-+	y_b = rgb_resulted[0].blue;
-+
-+	y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
-+
-+	arr_points[0].y = y1_min;
-+	arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, arr_points[0].x);
-+	y_r = rgb_resulted[hw_points - 1].red;
-+	y_g = rgb_resulted[hw_points - 1].green;
-+	y_b = rgb_resulted[hw_points - 1].blue;
-+
-+	/* see comment above, m_arrPoints[1].y should be the Y value for the
-+	 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
-+	 */
-+	y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
-+
-+	arr_points[1].y = y3_max;
-+
-+	arr_points[1].slope = dal_fixed31_32_zero;
-+
-+	if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
-+		/* for PQ, we want to have a straight line from last HW X point,
-+		 * and the slope to be such that we hit 1.0 at 10000 nits.
-+		 */
-+		const struct fixed31_32 end_value =
-+				dal_fixed31_32_from_int(125);
-+
-+		arr_points[1].slope = dal_fixed31_32_div(
-+			dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
-+			dal_fixed31_32_sub(end_value, arr_points[1].x));
-+	}
-+
-+	regamma_params->hw_points_num = hw_points;
-+
-+	i = 1;
-+	for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
-+		if (seg_distr[k] != -1) {
-+			regamma_params->arr_curve_points[k].segments_num =
-+					seg_distr[k];
-+			regamma_params->arr_curve_points[i].offset =
-+					regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
-+		}
-+		i++;
-+	}
-+
-+	if (seg_distr[k] != -1)
-+		regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
-+
-+	rgb = rgb_resulted;
-+	rgb_plus_1 = rgb_resulted + 1;
-+
-+	i = 1;
-+
-+	while (i != hw_points + 1) {
-+		if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
-+			rgb_plus_1->red = rgb->red;
-+		if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
-+			rgb_plus_1->green = rgb->green;
-+		if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
-+			rgb_plus_1->blue = rgb->blue;
-+
-+		rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red);
-+		rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green);
-+		rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue);
-+
-+		++rgb_plus_1;
-+		++rgb;
-+		++i;
-+	}
-+
-+	convert_to_custom_float(rgb_resulted, arr_points, hw_points);
-+
-+	return true;
-+}
-+
-+static bool
-+dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
-+			       const struct dc_stream_state *stream)
-+{
-+	struct dpp *dpp = pipe_ctx->plane_res.dpp;
-+
-+	if (dpp == NULL)
-+		return false;
-+
-+	dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
-+
-+	if (stream->out_transfer_func &&
-+	    stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
-+	    stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
-+		dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
-+	else if (dcn10_translate_regamma_to_hw_format(stream->out_transfer_func, &dpp->regamma_params))
-+		dpp->funcs->dpp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER);
-+	else
-+		dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
-+
-+	return true;
-+}
-+
-+static void dcn10_pipe_control_lock(
-+	struct dc *dc,
-+	struct pipe_ctx *pipe,
-+	bool lock)
-+{
-+	struct hubp *hubp = NULL;
-+	hubp = dc->res_pool->hubps[pipe->pipe_idx];
-+	/* use TG master update lock to lock everything on the TG
-+	 * therefore only top pipe need to lock
-+	 */
-+	if (pipe->top_pipe)
-+		return;
-+
-+	if (dc->debug.sanity_checks)
-+		dcn10_verify_allow_pstate_change_high(dc);
-+
-+	if (lock)
-+		pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
-+	else
-+		pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
-+
-+	if (dc->debug.sanity_checks)
-+		dcn10_verify_allow_pstate_change_high(dc);
-+}
-+
-+static bool wait_for_reset_trigger_to_occur(
-+	struct dc_context *dc_ctx,
-+	struct timing_generator *tg)
-+{
-+	bool rc = false;
-+
-+	/* To avoid endless loop we wait at most
-+	 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
-+	const uint32_t frames_to_wait_on_triggered_reset = 10;
-+	int i;
-+
-+	for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
-+
-+		if (!tg->funcs->is_counter_moving(tg)) {
-+			DC_ERROR("TG counter is not moving!\n");
-+			break;
-+		}
-+
-+		if (tg->funcs->did_triggered_reset_occur(tg)) {
-+			rc = true;
-+			/* usually occurs at i=1 */
-+			DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
-+					i);
-+			break;
-+		}
-+
-+		/* Wait for one frame. */
-+		tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
-+		tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
-+	}
-+
-+	if (false == rc)
-+		DC_ERROR("GSL: Timeout on reset trigger!\n");
-+
-+	return rc;
-+}
-+
-+static void dcn10_enable_timing_synchronization(
-+	struct dc *dc,
-+	int group_index,
-+	int group_size,
-+	struct pipe_ctx *grouped_pipes[])
-+{
-+	struct dc_context *dc_ctx = dc->ctx;
-+	int i;
-+
-+	DC_SYNC_INFO("Setting up OTG reset trigger\n");
-+
-+	for (i = 1; i < group_size; i++)
-+		grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
-+				grouped_pipes[i]->stream_res.tg,
-+				grouped_pipes[0]->stream_res.tg->inst);
-+
-+	DC_SYNC_INFO("Waiting for trigger\n");
-+
-+	/* Need to get only check 1 pipe for having reset as all the others are
-+	 * synchronized. Look at last pipe programmed to reset.
-+	 */
-+
-+	wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
-+	for (i = 1; i < group_size; i++)
-+		grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
-+				grouped_pipes[i]->stream_res.tg);
-+
-+	DC_SYNC_INFO("Sync complete\n");
-+}
-+
-+static void dcn10_enable_per_frame_crtc_position_reset(
-+	struct dc *dc,
-+	int group_size,
-+	struct pipe_ctx *grouped_pipes[])
-+{
-+	struct dc_context *dc_ctx = dc->ctx;
-+	int i;
-+
-+	DC_SYNC_INFO("Setting up\n");
-+	for (i = 0; i < group_size; i++)
-+		grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
-+				grouped_pipes[i]->stream_res.tg,
-+				grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
-+				&grouped_pipes[i]->stream->triggered_crtc_reset);
-+
-+	DC_SYNC_INFO("Waiting for trigger\n");
-+
-+	for (i = 1; i < group_size; i++)
-+		wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
-+
-+	DC_SYNC_INFO("Multi-display sync is complete\n");
-+}
-+
-+/*static void print_rq_dlg_ttu(
-+		struct dc *core_dc,
-+		struct pipe_ctx *pipe_ctx)
-+{
-+	dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"\n============== DML TTU Output parameters [%d] ==============\n"
-+			"qos_level_low_wm: %d, \n"
-+			"qos_level_high_wm: %d, \n"
-+			"min_ttu_vblank: %d, \n"
-+			"qos_level_flip: %d, \n"
-+			"refcyc_per_req_delivery_l: %d, \n"
-+			"qos_level_fixed_l: %d, \n"
-+			"qos_ramp_disable_l: %d, \n"
-+			"refcyc_per_req_delivery_pre_l: %d, \n"
-+			"refcyc_per_req_delivery_c: %d, \n"
-+			"qos_level_fixed_c: %d, \n"
-+			"qos_ramp_disable_c: %d, \n"
-+			"refcyc_per_req_delivery_pre_c: %d\n"
-+			"=============================================================\n",
-+			pipe_ctx->pipe_idx,
-+			pipe_ctx->ttu_regs.qos_level_low_wm,
-+			pipe_ctx->ttu_regs.qos_level_high_wm,
-+			pipe_ctx->ttu_regs.min_ttu_vblank,
-+			pipe_ctx->ttu_regs.qos_level_flip,
-+			pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
-+			pipe_ctx->ttu_regs.qos_level_fixed_l,
-+			pipe_ctx->ttu_regs.qos_ramp_disable_l,
-+			pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
-+			pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
-+			pipe_ctx->ttu_regs.qos_level_fixed_c,
-+			pipe_ctx->ttu_regs.qos_ramp_disable_c,
-+			pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
-+			);
-+
-+	dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"\n============== DML DLG Output parameters [%d] ==============\n"
-+			"refcyc_h_blank_end: %d, \n"
-+			"dlg_vblank_end: %d, \n"
-+			"min_dst_y_next_start: %d, \n"
-+			"refcyc_per_htotal: %d, \n"
-+			"refcyc_x_after_scaler: %d, \n"
-+			"dst_y_after_scaler: %d, \n"
-+			"dst_y_prefetch: %d, \n"
-+			"dst_y_per_vm_vblank: %d, \n"
-+			"dst_y_per_row_vblank: %d, \n"
-+			"ref_freq_to_pix_freq: %d, \n"
-+			"vratio_prefetch: %d, \n"
-+			"refcyc_per_pte_group_vblank_l: %d, \n"
-+			"refcyc_per_meta_chunk_vblank_l: %d, \n"
-+			"dst_y_per_pte_row_nom_l: %d, \n"
-+			"refcyc_per_pte_group_nom_l: %d, \n",
-+			pipe_ctx->pipe_idx,
-+			pipe_ctx->dlg_regs.refcyc_h_blank_end,
-+			pipe_ctx->dlg_regs.dlg_vblank_end,
-+			pipe_ctx->dlg_regs.min_dst_y_next_start,
-+			pipe_ctx->dlg_regs.refcyc_per_htotal,
-+			pipe_ctx->dlg_regs.refcyc_x_after_scaler,
-+			pipe_ctx->dlg_regs.dst_y_after_scaler,
-+			pipe_ctx->dlg_regs.dst_y_prefetch,
-+			pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
-+			pipe_ctx->dlg_regs.dst_y_per_row_vblank,
-+			pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
-+			pipe_ctx->dlg_regs.vratio_prefetch,
-+			pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
-+			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
-+			pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
-+			pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
-+			);
-+
-+	dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"\ndst_y_per_meta_row_nom_l: %d, \n"
-+			"refcyc_per_meta_chunk_nom_l: %d, \n"
-+			"refcyc_per_line_delivery_pre_l: %d, \n"
-+			"refcyc_per_line_delivery_l: %d, \n"
-+			"vratio_prefetch_c: %d, \n"
-+			"refcyc_per_pte_group_vblank_c: %d, \n"
-+			"refcyc_per_meta_chunk_vblank_c: %d, \n"
-+			"dst_y_per_pte_row_nom_c: %d, \n"
-+			"refcyc_per_pte_group_nom_c: %d, \n"
-+			"dst_y_per_meta_row_nom_c: %d, \n"
-+			"refcyc_per_meta_chunk_nom_c: %d, \n"
-+			"refcyc_per_line_delivery_pre_c: %d, \n"
-+			"refcyc_per_line_delivery_c: %d \n"
-+			"========================================================\n",
-+			pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
-+			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
-+			pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
-+			pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
-+			pipe_ctx->dlg_regs.vratio_prefetch_c,
-+			pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
-+			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
-+			pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
-+			pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
-+			pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
-+			pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
-+			pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
-+			pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
-+			);
-+
-+	dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"\n============== DML RQ Output parameters [%d] ==============\n"
-+			"chunk_size: %d \n"
-+			"min_chunk_size: %d \n"
-+			"meta_chunk_size: %d \n"
-+			"min_meta_chunk_size: %d \n"
-+			"dpte_group_size: %d \n"
-+			"mpte_group_size: %d \n"
-+			"swath_height: %d \n"
-+			"pte_row_height_linear: %d \n"
-+			"========================================================\n",
-+			pipe_ctx->pipe_idx,
-+			pipe_ctx->rq_regs.rq_regs_l.chunk_size,
-+			pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
-+			pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
-+			pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
-+			pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
-+			pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
-+			pipe_ctx->rq_regs.rq_regs_l.swath_height,
-+			pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
-+			);
-+}
-+*/
-+
-+static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
-+		struct vm_system_aperture_param *apt,
-+		struct dce_hwseq *hws)
-+{
-+	PHYSICAL_ADDRESS_LOC physical_page_number;
-+	uint32_t logical_addr_low;
-+	uint32_t logical_addr_high;
-+
-+	REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
-+			PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
-+	REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
-+			PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
-+
-+	REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
-+			LOGICAL_ADDR, &logical_addr_low);
-+
-+	REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-+			LOGICAL_ADDR, &logical_addr_high);
-+
-+	apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
-+	apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
-+	apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
-+}
-+
-+/* Temporary read settings, future will get values from kmd directly */
-+static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
-+		struct vm_context0_param *vm0,
-+		struct dce_hwseq *hws)
-+{
-+	PHYSICAL_ADDRESS_LOC fb_base;
-+	PHYSICAL_ADDRESS_LOC fb_offset;
-+	uint32_t fb_base_value;
-+	uint32_t fb_offset_value;
-+
-+	REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
-+	REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
-+
-+	REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
-+			PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
-+	REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
-+			PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
-+
-+	REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
-+			LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
-+	REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
-+			LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
-+
-+	REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
-+			LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
-+	REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
-+			LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
-+
-+	REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
-+			PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
-+	REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
-+			PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
-+
-+	/*
-+	 * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
-+	 * Therefore we need to do
-+	 * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
-+	 * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
-+	 */
-+	fb_base.quad_part = (uint64_t)fb_base_value << 24;
-+	fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
-+	vm0->pte_base.quad_part += fb_base.quad_part;
-+	vm0->pte_base.quad_part -= fb_offset.quad_part;
-+}
-+
-+
-+static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
-+{
-+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-+	struct vm_system_aperture_param apt = { {{ 0 } } };
-+	struct vm_context0_param vm0 = { { { 0 } } };
-+
-+	mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
-+	mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
-+
-+	hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
-+	hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
-+}
-+
-+static void dcn10_enable_plane(
-+	struct dc *dc,
-+	struct pipe_ctx *pipe_ctx,
-+	struct dc_state *context)
-+{
-+	struct dce_hwseq *hws = dc->hwseq;
-+
-+	if (dc->debug.sanity_checks) {
-+		dcn10_verify_allow_pstate_change_high(dc);
-+	}
-+
-+	undo_DEGVIDCN10_253_wa(dc);
-+
-+	power_on_plane(dc->hwseq,
-+		pipe_ctx->pipe_idx);
-+
-+	/* enable DCFCLK current DCHUB */
-+	REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx],
-+			HUBP_CLOCK_ENABLE, 1);
-+
-+	/* make sure OPP_PIPE_CLOCK_EN = 1 */
-+	REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
-+			OPP_PIPE_CLOCK_EN, 1);
-+	/*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/
-+
-+/* TODO: enable/disable in dm as per update type.
-+	if (plane_state) {
-+		dm_logger_write(dc->ctx->logger, LOG_DC,
-+				"Pipe:%d 0x%x: addr hi:0x%x, "
-+				"addr low:0x%x, "
-+				"src: %d, %d, %d,"
-+				" %d; dst: %d, %d, %d, %d;\n",
-+				pipe_ctx->pipe_idx,
-+				plane_state,
-+				plane_state->address.grph.addr.high_part,
-+				plane_state->address.grph.addr.low_part,
-+				plane_state->src_rect.x,
-+				plane_state->src_rect.y,
-+				plane_state->src_rect.width,
-+				plane_state->src_rect.height,
-+				plane_state->dst_rect.x,
-+				plane_state->dst_rect.y,
-+				plane_state->dst_rect.width,
-+				plane_state->dst_rect.height);
-+
-+		dm_logger_write(dc->ctx->logger, LOG_DC,
-+				"Pipe %d: width, height, x, y         format:%d\n"
-+				"viewport:%d, %d, %d, %d\n"
-+				"recout:  %d, %d, %d, %d\n",
-+				pipe_ctx->pipe_idx,
-+				plane_state->format,
-+				pipe_ctx->plane_res.scl_data.viewport.width,
-+				pipe_ctx->plane_res.scl_data.viewport.height,
-+				pipe_ctx->plane_res.scl_data.viewport.x,
-+				pipe_ctx->plane_res.scl_data.viewport.y,
-+				pipe_ctx->plane_res.scl_data.recout.width,
-+				pipe_ctx->plane_res.scl_data.recout.height,
-+				pipe_ctx->plane_res.scl_data.recout.x,
-+				pipe_ctx->plane_res.scl_data.recout.y);
-+		print_rq_dlg_ttu(dc, pipe_ctx);
-+	}
-+*/
-+	if (dc->config.gpu_vm_support)
-+		dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
-+
-+	if (dc->debug.sanity_checks) {
-+		dcn10_verify_allow_pstate_change_high(dc);
-+	}
-+}
-+
-+static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
-+{
-+	struct dpp_grph_csc_adjustment adjust;
-+	memset(&adjust, 0, sizeof(adjust));
-+	adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
-+
-+
-+	if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
-+		adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
-+		adjust.temperature_matrix[0] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[0];
-+		adjust.temperature_matrix[1] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[1];
-+		adjust.temperature_matrix[2] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[2];
-+		adjust.temperature_matrix[3] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[4];
-+		adjust.temperature_matrix[4] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[5];
-+		adjust.temperature_matrix[5] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[6];
-+		adjust.temperature_matrix[6] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[8];
-+		adjust.temperature_matrix[7] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[9];
-+		adjust.temperature_matrix[8] =
-+				pipe_ctx->stream->
-+				gamut_remap_matrix.matrix[10];
-+	}
-+
-+	pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
-+}
-+
-+
-+static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
-+		enum dc_color_space colorspace,
-+		uint16_t *matrix)
-+{
-+	int i;
-+	struct out_csc_color_matrix tbl_entry;
-+
-+	if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
-+			enum dc_color_space color_space =
-+				pipe_ctx->stream->output_color_space;
-+
-+			//uint16_t matrix[12];
-+			for (i = 0; i < 12; i++)
-+				tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
-+
-+			tbl_entry.color_space = color_space;
-+			//tbl_entry.regval = matrix;
-+
-+			pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry);
-+	} else {
-+		pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
-+	}
-+}
-+
-+static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
-+{
-+	if (pipe_ctx->plane_state->visible)
-+		return true;
-+	if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
-+		return true;
-+	return false;
-+}
-+
-+static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
-+{
-+	if (pipe_ctx->plane_state->visible)
-+		return true;
-+	if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
-+		return true;
-+	return false;
-+}
-+
-+static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
-+{
-+	if (pipe_ctx->plane_state->visible)
-+		return true;
-+	if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
-+		return true;
-+	if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
-+		return true;
-+	return false;
-+}
-+
-+static bool is_rgb_cspace(enum dc_color_space output_color_space)
-+{
-+	switch (output_color_space) {
-+	case COLOR_SPACE_SRGB:
-+	case COLOR_SPACE_SRGB_LIMITED:
-+	case COLOR_SPACE_2020_RGB_FULLRANGE:
-+	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
-+	case COLOR_SPACE_ADOBERGB:
-+		return true;
-+	case COLOR_SPACE_YCBCR601:
-+	case COLOR_SPACE_YCBCR709:
-+	case COLOR_SPACE_YCBCR601_LIMITED:
-+	case COLOR_SPACE_YCBCR709_LIMITED:
-+	case COLOR_SPACE_2020_YCBCR:
-+		return false;
-+	default:
-+		/* Add a case to switch */
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
-+
-+static void dcn10_get_surface_visual_confirm_color(
-+		const struct pipe_ctx *pipe_ctx,
-+		struct tg_color *color)
-+{
-+	uint32_t color_value = MAX_TG_COLOR_VALUE;
-+
-+	switch (pipe_ctx->plane_res.scl_data.format) {
-+	case PIXEL_FORMAT_ARGB8888:
-+		/* set boarder color to red */
-+		color->color_r_cr = color_value;
-+		break;
-+
-+	case PIXEL_FORMAT_ARGB2101010:
-+		/* set boarder color to blue */
-+		color->color_b_cb = color_value;
-+		break;
-+	case PIXEL_FORMAT_420BPP8:
-+		/* set boarder color to green */
-+		color->color_g_y = color_value;
-+		break;
-+	case PIXEL_FORMAT_420BPP10:
-+		/* set boarder color to yellow */
-+		color->color_g_y = color_value;
-+		color->color_r_cr = color_value;
-+		break;
-+	case PIXEL_FORMAT_FP16:
-+		/* set boarder color to white */
-+		color->color_r_cr = color_value;
-+		color->color_b_cb = color_value;
-+		color->color_g_y = color_value;
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+static uint16_t fixed_point_to_int_frac(
-+	struct fixed31_32 arg,
-+	uint8_t integer_bits,
-+	uint8_t fractional_bits)
-+{
-+	int32_t numerator;
-+	int32_t divisor = 1 << fractional_bits;
-+
-+	uint16_t result;
-+
-+	uint16_t d = (uint16_t)dal_fixed31_32_floor(
-+		dal_fixed31_32_abs(
-+			arg));
-+
-+	if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
-+		numerator = (uint16_t)dal_fixed31_32_floor(
-+			dal_fixed31_32_mul_int(
-+				arg,
-+				divisor));
-+	else {
-+		numerator = dal_fixed31_32_floor(
-+			dal_fixed31_32_sub(
-+				dal_fixed31_32_from_int(
-+					1LL << integer_bits),
-+				dal_fixed31_32_recip(
-+					dal_fixed31_32_from_int(
-+						divisor))));
-+	}
-+
-+	if (numerator >= 0)
-+		result = (uint16_t)numerator;
-+	else
-+		result = (uint16_t)(
-+		(1 << (integer_bits + fractional_bits + 1)) + numerator);
-+
-+	if ((result != 0) && dal_fixed31_32_lt(
-+		arg, dal_fixed31_32_zero))
-+		result |= 1 << (integer_bits + fractional_bits);
-+
-+	return result;
-+}
-+
-+void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
-+		const struct dc_plane_state *plane_state)
-+{
-+	if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
-+			&& plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
-+			&& plane_state->input_csc_color_matrix.enable_adjustment
-+			&& plane_state->coeff_reduction_factor.value != 0) {
-+		bias_and_scale->scale_blue = fixed_point_to_int_frac(
-+			dal_fixed31_32_mul(plane_state->coeff_reduction_factor,
-+					dal_fixed31_32_from_fraction(256, 255)),
-+				2,
-+				13);
-+		bias_and_scale->scale_red = bias_and_scale->scale_blue;
-+		bias_and_scale->scale_green = bias_and_scale->scale_blue;
-+	} else {
-+		bias_and_scale->scale_blue = 0x2000;
-+		bias_and_scale->scale_red = 0x2000;
-+		bias_and_scale->scale_green = 0x2000;
-+	}
-+}
-+
-+static void update_dchubp_dpp(
-+	struct dc *dc,
-+	struct pipe_ctx *pipe_ctx,
-+	struct dc_state *context)
-+{
-+	struct dce_hwseq *hws = dc->hwseq;
-+	struct hubp *hubp = pipe_ctx->plane_res.hubp;
-+	struct dpp *dpp = pipe_ctx->plane_res.dpp;
-+	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-+	union plane_size size = plane_state->plane_size;
-+	struct mpcc_cfg mpcc_cfg = {0};
-+	struct pipe_ctx *top_pipe;
-+	bool per_pixel_alpha = plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
-+	struct dc_bias_and_scale bns_params = {0};
-+
-+	/* TODO: proper fix once fpga works */
-+	/* depends on DML calculation, DPP clock value may change dynamically */
-+	enable_dppclk(
-+		dc->hwseq,
-+		pipe_ctx->pipe_idx,
-+		pipe_ctx->stream_res.pix_clk_params.requested_pix_clk,
-+		context->bw.dcn.calc_clk.dppclk_div);
-+	dc->current_state->bw.dcn.cur_clk.dppclk_div =
-+			context->bw.dcn.calc_clk.dppclk_div;
-+	context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div;
-+
-+	/* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
-+	 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
-+	 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
-+	 */
-+	REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst);
-+
-+	hubp->funcs->hubp_setup(
-+		hubp,
-+		&pipe_ctx->dlg_regs,
-+		&pipe_ctx->ttu_regs,
-+		&pipe_ctx->rq_regs,
-+		&pipe_ctx->pipe_dlg_param);
-+
-+	size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
-+
-+	// program the input csc
-+	dpp->funcs->dpp_setup(dpp,
-+			plane_state->format,
-+			EXPANSION_MODE_ZERO,
-+			plane_state->input_csc_color_matrix,
-+			COLOR_SPACE_YCBCR601_LIMITED);
-+
-+	//set scale and bias registers
-+	build_prescale_params(&bns_params, plane_state);
-+	if (dpp->funcs->dpp_program_bias_and_scale)
-+		dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
-+
-+	mpcc_cfg.dpp_id = hubp->inst;
-+	mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst;
-+	mpcc_cfg.tree_cfg = &(pipe_ctx->stream_res.opp->mpc_tree);
-+	for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe)
-+		mpcc_cfg.z_index++;
-+	if (dc->debug.surface_visual_confirm)
-+		dcn10_get_surface_visual_confirm_color(
-+				pipe_ctx, &mpcc_cfg.black_color);
-+	else
-+		color_space_to_black_color(
-+			dc, pipe_ctx->stream->output_color_space,
-+			&mpcc_cfg.black_color);
-+	mpcc_cfg.per_pixel_alpha = per_pixel_alpha;
-+	/* DCN1.0 has output CM before MPC which seems to screw with
-+	 * pre-multiplied alpha.
-+	 */
-+	mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace(
-+			pipe_ctx->stream->output_color_space)
-+					&& per_pixel_alpha;
-+	hubp->mpcc_id = dc->res_pool->mpc->funcs->add(dc->res_pool->mpc, &mpcc_cfg);
-+	hubp->opp_id = mpcc_cfg.opp_id;
-+
-+	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
-+	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
-+	/* scaler configuration */
-+	pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
-+			pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
-+
-+	hubp->funcs->mem_program_viewport(hubp,
-+			&pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c);
-+
-+	/*gamut remap*/
-+	program_gamut_remap(pipe_ctx);
-+
-+	program_csc_matrix(pipe_ctx,
-+			pipe_ctx->stream->output_color_space,
-+			pipe_ctx->stream->csc_color_matrix.matrix);
-+
-+
-+	hubp->funcs->hubp_program_surface_config(
-+		hubp,
-+		plane_state->format,
-+		&plane_state->tiling_info,
-+		&size,
-+		plane_state->rotation,
-+		&plane_state->dcc,
-+		plane_state->horizontal_mirror);
-+
-+	hubp->power_gated = false;
-+
-+	dc->hwss.update_plane_addr(dc, pipe_ctx);
-+
-+	if (is_pipe_tree_visible(pipe_ctx))
-+		hubp->funcs->set_blank(hubp, false);
-+}
-+
-+
-+static void program_all_pipe_in_tree(
-+		struct dc *dc,
-+		struct pipe_ctx *pipe_ctx,
-+		struct dc_state *context)
-+{
-+	if (pipe_ctx->top_pipe == NULL) {
-+
-+		if (dc->debug.sanity_checks) {
-+			/* pstate stuck check after watermark update */
-+			dcn10_verify_allow_pstate_change_high(dc);
-+		}
-+
-+		pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
-+		pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
-+		pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
-+		pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
-+		pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
-+
-+		pipe_ctx->stream_res.tg->funcs->program_global_sync(
-+				pipe_ctx->stream_res.tg);
-+		pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, !is_pipe_tree_visible(pipe_ctx));
-+	}
-+
-+	if (pipe_ctx->plane_state != NULL) {
-+		struct pipe_ctx *cur_pipe_ctx =
-+				&dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
-+
-+		if (pipe_ctx->plane_state->update_flags.bits.full_update)
-+			dcn10_enable_plane(dc, pipe_ctx, context);
-+
-+		if (pipe_ctx->plane_state->update_flags.raw != 0)
-+			update_dchubp_dpp(dc, pipe_ctx, context);
-+
-+		if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
-+			dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
-+		}
-+
-+		/*
-+		 * TODO: This can be further optimized/cleaned up
-+		 * Always call this for now since it does memcmp inside before
-+		 * doing heavy calculation and programming
-+		 */
-+		dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
-+	}
-+
-+	if (dc->debug.sanity_checks) {
-+		/* pstate stuck check after each pipe is programmed */
-+		dcn10_verify_allow_pstate_change_high(dc);
-+	}
-+
-+	if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
-+		program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
-+}
-+
-+static void dcn10_pplib_apply_display_requirements(
-+	struct dc *dc,
-+	struct dc_state *context)
-+{
-+	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
-+
-+	pp_display_cfg->all_displays_in_sync = false;/*todo*/
-+	pp_display_cfg->nb_pstate_switch_disable = false;
-+	pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
-+	pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
-+	pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
-+	pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
-+	pp_display_cfg->avail_mclk_switch_time_us =
-+			context->bw.dcn.cur_clk.dram_ccm_us > 0 ? context->bw.dcn.cur_clk.dram_ccm_us : 0;
-+	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
-+			context->bw.dcn.cur_clk.min_active_dram_ccm_us > 0 ? context->bw.dcn.cur_clk.min_active_dram_ccm_us : 0;
-+	pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
-+	pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
-+	dce110_fill_display_configs(context, pp_display_cfg);
-+
-+	if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
-+			struct dm_pp_display_configuration)) !=  0)
-+		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
-+
-+	dc->prev_display_config = *pp_display_cfg;
-+}
-+
-+static void optimize_shared_resources(struct dc *dc)
-+{
-+	if (dc->current_state->stream_count == 0) {
-+		/* S0i2 message */
-+		dcn10_pplib_apply_display_requirements(dc, dc->current_state);
-+	}
-+
-+	if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
-+		dcn_bw_notify_pplib_of_wm_ranges(dc);
-+}
-+
-+static void ready_shared_resources(struct dc *dc, struct dc_state *context)
-+{
-+	/* S0i2 message */
-+	if (dc->current_state->stream_count == 0 &&
-+			context->stream_count != 0)
-+		dcn10_pplib_apply_display_requirements(dc, context);
-+}
-+
-+static struct pipe_ctx *find_top_pipe_for_stream(
-+		struct dc *dc,
-+		struct dc_state *context,
-+		const struct dc_stream_state *stream)
-+{
-+	int i;
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+		struct pipe_ctx *old_pipe_ctx =
-+				&dc->current_state->res_ctx.pipe_ctx[i];
-+
-+		if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
-+			continue;
-+
-+		if (pipe_ctx->stream != stream)
-+			continue;
-+
-+		if (!pipe_ctx->top_pipe)
-+			return pipe_ctx;
-+	}
-+	return NULL;
-+}
-+
-+static void dcn10_apply_ctx_for_surface(
-+		struct dc *dc,
-+		const struct dc_stream_state *stream,
-+		int num_planes,
-+		struct dc_state *context)
-+{
-+	int i;
-+	struct timing_generator *tg;
-+	bool removed_pipe[4] = { false };
-+	unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
-+
-+	struct pipe_ctx *top_pipe_to_program =
-+			find_top_pipe_for_stream(dc, context, stream);
-+
-+	if (!top_pipe_to_program)
-+		return;
-+
-+	tg = top_pipe_to_program->stream_res.tg;
-+
-+	if (dc->debug.sanity_checks)
-+		dcn10_verify_allow_pstate_change_high(dc);
-+
-+	tg->funcs->lock(tg);
-+
-+	if (num_planes == 0) {
-+
-+		/* OTG blank before remove all front end */
-+		tg->funcs->set_blank(tg, true);
-+	}
-+
-+	/* Disconnect unused mpcc */
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+		struct pipe_ctx *old_pipe_ctx =
-+				&dc->current_state->res_ctx.pipe_ctx[i];
-+		/*
-+		 * Powergate reused pipes that are not powergated
-+		 * fairly hacky right now, using opp_id as indicator
-+		 * TODO: After move dc_post to dc_update, this will
-+		 * be removed.
-+		 */
-+		if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
-+			if (old_pipe_ctx->stream_res.tg == tg &&
-+				old_pipe_ctx->plane_res.hubp &&
-+				old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
-+				dcn10_disable_plane(dc, pipe_ctx);
-+				/*
-+				 * power down fe will unlock when calling reset, need
-+				 * to lock it back here. Messy, need rework.
-+				 */
-+				pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
-+			}
-+		}
-+
-+		if (!pipe_ctx->plane_state &&
-+			old_pipe_ctx->plane_state &&
-+			old_pipe_ctx->stream_res.tg == tg) {
-+
-+			plane_atomic_disconnect(dc, old_pipe_ctx);
-+			removed_pipe[i] = true;
-+
-+			dm_logger_write(dc->ctx->logger, LOG_DC,
-+					"Reset mpcc for pipe %d\n",
-+					old_pipe_ctx->pipe_idx);
-+		}
-+	}
-+
-+	if (num_planes > 0) {
-+		struct dc_stream_state *stream_for_cursor = NULL;
-+
-+		program_all_pipe_in_tree(dc, top_pipe_to_program, context);
-+
-+		for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-+
-+			if (stream == pipe_ctx->stream) {
-+				stream_for_cursor = pipe_ctx->stream;
-+				break;
-+			}
-+		}
-+
-+		/* TODO: this is a hack w/a for switching from mpo to pipe split */
-+		if (stream_for_cursor->cursor_attributes.address.quad_part != 0) {
-+			struct dc_cursor_position position = { 0 };
-+
-+			dc_stream_set_cursor_position(stream_for_cursor, &position);
-+			dc_stream_set_cursor_attributes(stream_for_cursor,
-+				&stream_for_cursor->cursor_attributes);
-+		}
-+	}
-+
-+	tg->funcs->unlock(tg);
-+
-+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-+		struct pipe_ctx *old_pipe_ctx =
-+				&dc->current_state->res_ctx.pipe_ctx[i];
-+
-+		if (removed_pipe[i] && num_planes == 0)
-+			dcn10_disable_plane(dc, old_pipe_ctx);
-+	}
-+
-+	if (dc->debug.sanity_checks) {
-+		/* pstate stuck check after watermark update */
-+		dcn10_verify_allow_pstate_change_high(dc);
-+	}
-+	/* watermark is for all pipes */
-+	hubbub1_program_watermarks(dc->res_pool->hubbub,
-+			&context->bw.dcn.watermarks, ref_clk_mhz);
-+
-+	if (dc->debug.sanity_checks) {
-+		/* pstate stuck check after watermark update */
-+		dcn10_verify_allow_pstate_change_high(dc);
-+	}
-+
-+	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"\n============== Watermark parameters ==============\n"
-+			"a.urgent_ns: %d \n"
-+			"a.cstate_enter_plus_exit: %d \n"
-+			"a.cstate_exit: %d \n"
-+			"a.pstate_change: %d \n"
-+			"a.pte_meta_urgent: %d \n"
-+			"b.urgent_ns: %d \n"
-+			"b.cstate_enter_plus_exit: %d \n"
-+			"b.cstate_exit: %d \n"
-+			"b.pstate_change: %d \n"
-+			"b.pte_meta_urgent: %d \n",
-+			context->bw.dcn.watermarks.a.urgent_ns,
-+			context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
-+			context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
-+			context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
-+			context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
-+			context->bw.dcn.watermarks.b.urgent_ns,
-+			context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
-+			context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
-+			context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
-+			context->bw.dcn.watermarks.b.pte_meta_urgent_ns
-+			);
-+	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
-+			"\nc.urgent_ns: %d \n"
-+			"c.cstate_enter_plus_exit: %d \n"
-+			"c.cstate_exit: %d \n"
-+			"c.pstate_change: %d \n"
-+			"c.pte_meta_urgent: %d \n"
-+			"d.urgent_ns: %d \n"
-+			"d.cstate_enter_plus_exit: %d \n"
-+			"d.cstate_exit: %d \n"
-+			"d.pstate_change: %d \n"
-+			"d.pte_meta_urgent: %d \n"
-+			"========================================================\n",
-+			context->bw.dcn.watermarks.c.urgent_ns,
-+			context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
-+			context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
-+			context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
-+			context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
-+			context->bw.dcn.watermarks.d.urgent_ns,
-+			context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
-+			context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
-+			context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
-+			context->bw.dcn.watermarks.d.pte_meta_urgent_ns
-+			);
-+
-+	if (dc->debug.sanity_checks)
-+		dcn10_verify_allow_pstate_change_high(dc);
-+}
-+
-+static void dcn10_set_bandwidth(
-+		struct dc *dc,
-+		struct dc_state *context,
-+		bool decrease_allowed)
-+{
-+	struct pp_smu_display_requirement_rv *smu_req_cur =
-+			&dc->res_pool->pp_smu_req;
-+	struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
-+	struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
-+
-+	if (dc->debug.sanity_checks) {
-+		dcn10_verify_allow_pstate_change_high(dc);
-+	}
-+
-+	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
-+		return;
-+
-+	if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz
-+			> dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
-+		dc->res_pool->display_clock->funcs->set_clock(
-+				dc->res_pool->display_clock,
-+				context->bw.dcn.calc_clk.dispclk_khz);
-+		dc->current_state->bw.dcn.cur_clk.dispclk_khz =
-+				context->bw.dcn.calc_clk.dispclk_khz;
-+	}
-+	if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz
-+			> dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
-+		smu_req.hard_min_dcefclk_khz =
-+				context->bw.dcn.calc_clk.dcfclk_khz;
-+	}
-+	if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz
-+			> dc->current_state->bw.dcn.cur_clk.fclk_khz) {
-+		smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
-+	}
-+	if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz
-+			> dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) {
-+		dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz =
-+				context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
-+		context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
-+				context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
-+	}
-+
-+	smu_req.display_count = context->stream_count;
-+
-+	if (pp_smu->set_display_requirement)
-+		pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
-+
-+	*smu_req_cur = smu_req;
-+
-+	/* Decrease in freq is increase in period so opposite comparison for dram_ccm */
-+	if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us
-+			< dc->current_state->bw.dcn.cur_clk.dram_ccm_us) {
-+		dc->current_state->bw.dcn.calc_clk.dram_ccm_us =
-+				context->bw.dcn.calc_clk.dram_ccm_us;
-+		context->bw.dcn.cur_clk.dram_ccm_us =
-+				context->bw.dcn.calc_clk.dram_ccm_us;
-+	}
-+	if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us
-+			< dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) {
-+		dc->current_state->bw.dcn.calc_clk.min_active_dram_ccm_us =
-+				context->bw.dcn.calc_clk.min_active_dram_ccm_us;
-+		context->bw.dcn.cur_clk.min_active_dram_ccm_us =
-+				context->bw.dcn.calc_clk.min_active_dram_ccm_us;
-+	}
-+	dcn10_pplib_apply_display_requirements(dc, context);
-+
-+	if (dc->debug.sanity_checks) {
-+		dcn10_verify_allow_pstate_change_high(dc);
-+	}
-+
-+	/* need to fix this function.  not doing the right thing here */
-+}
-+
-+static void set_drr(struct pipe_ctx **pipe_ctx,
-+		int num_pipes, int vmin, int vmax)
-+{
-+	int i = 0;
-+	struct drr_params params = {0};
-+
-+	params.vertical_total_max = vmax;
-+	params.vertical_total_min = vmin;
-+
-+	/* TODO: If multiple pipes are to be supported, you need
-+	 * some GSL stuff
-+	 */
-+	for (i = 0; i < num_pipes; i++) {
-+		pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
-+	}
-+}
-+
-+static void get_position(struct pipe_ctx **pipe_ctx,
-+		int num_pipes,
-+		struct crtc_position *position)
-+{
-+	int i = 0;
-+
-+	/* TODO: handle pipes > 1
-+	 */
-+	for (i = 0; i < num_pipes; i++)
-+		pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
-+}
-+
-+static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
-+		int num_pipes, const struct dc_static_screen_events *events)
-+{
-+	unsigned int i;
-+	unsigned int value = 0;
-+
-+	if (events->surface_update)
-+		value |= 0x80;
-+	if (events->cursor_update)
-+		value |= 0x2;
-+
-+	for (i = 0; i < num_pipes; i++)
-+		pipe_ctx[i]->stream_res.tg->funcs->
-+			set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
-+}
-+
-+static void set_plane_config(
-+	const struct dc *dc,
-+	struct pipe_ctx *pipe_ctx,
-+	struct resource_context *res_ctx)
-+{
-+	/* TODO */
-+	program_gamut_remap(pipe_ctx);
-+}
-+
-+static void dcn10_config_stereo_parameters(
-+		struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
-+{
-+	enum view_3d_format view_format = stream->view_format;
-+	enum dc_timing_3d_format timing_3d_format =\
-+			stream->timing.timing_3d_format;
-+	bool non_stereo_timing = false;
-+
-+	if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
-+		timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
-+		timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
-+		non_stereo_timing = true;
-+
-+	if (non_stereo_timing == false &&
-+		view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
-+
-+		flags->PROGRAM_STEREO         = 1;
-+		flags->PROGRAM_POLARITY       = 1;
-+		if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
-+			timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
-+			timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
-+			enum display_dongle_type dongle = \
-+					stream->sink->link->ddc->dongle_type;
-+			if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
-+				dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
-+				dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
-+				flags->DISABLE_STEREO_DP_SYNC = 1;
-+		}
-+		flags->RIGHT_EYE_POLARITY =\
-+				stream->timing.flags.RIGHT_EYE_3D_POLARITY;
-+		if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
-+			flags->FRAME_PACKED = 1;
-+	}
-+
-+	return;
-+}
-+
-+static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
-+{
-+	struct crtc_stereo_flags flags = { 0 };
-+	struct dc_stream_state *stream = pipe_ctx->stream;
-+
-+	dcn10_config_stereo_parameters(stream, &flags);
-+
-+	pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity(
-+		pipe_ctx->stream_res.opp,
-+		flags.PROGRAM_STEREO == 1 ? true:false,
-+		stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false);
-+
-+	pipe_ctx->stream_res.tg->funcs->program_stereo(
-+		pipe_ctx->stream_res.tg,
-+		&stream->timing,
-+		&flags);
-+
-+	return;
-+}
-+
-+static void dcn10_wait_for_mpcc_disconnect(
-+		struct dc *dc,
-+		struct resource_pool *res_pool,
-+		struct pipe_ctx *pipe_ctx)
-+{
-+	int i;
-+
-+	if (dc->debug.sanity_checks) {
-+		dcn10_verify_allow_pstate_change_high(dc);
-+	}
-+
-+	if (!pipe_ctx->stream_res.opp)
-+		return;
-+
-+	for (i = 0; i < MAX_PIPES; i++) {
-+		if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i]) {
-+			res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, i);
-+			pipe_ctx->stream_res.opp->mpcc_disconnect_pending[i] = false;
-+			res_pool->hubps[i]->funcs->set_blank(res_pool->hubps[i], true);
-+			/*dm_logger_write(dc->ctx->logger, LOG_ERROR,
-+					"[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
-+					i);*/
-+		}
-+	}
-+
-+	if (dc->debug.sanity_checks) {
-+		dcn10_verify_allow_pstate_change_high(dc);
-+	}
-+
-+}
-+
-+static bool dcn10_dummy_display_power_gating(
-+	struct dc *dc,
-+	uint8_t controller_id,
-+	struct dc_bios *dcb,
-+	enum pipe_gating_control power_gating)
-+{
-+	return true;
-+}
-+
-+void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
-+{
-+	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-+	struct timing_generator *tg = pipe_ctx->stream_res.tg;
-+
-+	if (plane_state == NULL)
-+		return;
-+
-+	plane_state->status.is_flip_pending =
-+			pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
-+					pipe_ctx->plane_res.hubp);
-+
-+	plane_state->status.current_address = pipe_ctx->plane_res.hubp->current_address;
-+	if (pipe_ctx->plane_res.hubp->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
-+			tg->funcs->is_stereo_left_eye) {
-+		plane_state->status.is_right_eye =
-+				!tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
-+	}
-+}
-+
-+void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
-+{
-+	if (hws->ctx->dc->res_pool->hubbub != NULL)
-+		hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
-+}
-+
-+static const struct hw_sequencer_funcs dcn10_funcs = {
-+	.program_gamut_remap = program_gamut_remap,
-+	.program_csc_matrix = program_csc_matrix,
-+	.init_hw = dcn10_init_hw,
-+	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
-+	.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
-+	.set_plane_config = set_plane_config,
-+	.update_plane_addr = dcn10_update_plane_addr,
-+	.update_dchub = dcn10_update_dchub,
-+	.update_pending_status = dcn10_update_pending_status,
-+	.set_input_transfer_func = dcn10_set_input_transfer_func,
-+	.set_output_transfer_func = dcn10_set_output_transfer_func,
-+	.power_down = dce110_power_down,
-+	.enable_accelerated_mode = dce110_enable_accelerated_mode,
-+	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
-+	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
-+	.update_info_frame = dce110_update_info_frame,
-+	.enable_stream = dce110_enable_stream,
-+	.disable_stream = dce110_disable_stream,
-+	.unblank_stream = dce110_unblank_stream,
-+	.enable_display_power_gating = dcn10_dummy_display_power_gating,
-+	.disable_plane = dcn10_disable_plane,
-+	.pipe_control_lock = dcn10_pipe_control_lock,
-+	.set_bandwidth = dcn10_set_bandwidth,
-+	.reset_hw_ctx_wrap = reset_hw_ctx_wrap,
-+	.prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
-+	.set_drr = set_drr,
-+	.get_position = get_position,
-+	.set_static_screen_control = set_static_screen_control,
-+	.setup_stereo = dcn10_setup_stereo,
-+	.set_avmute = dce110_set_avmute,
-+	.log_hw_state = dcn10_log_hw_state,
-+	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
-+	.ready_shared_resources = ready_shared_resources,
-+	.optimize_shared_resources = optimize_shared_resources,
-+	.pplib_apply_display_requirements =
-+			dcn10_pplib_apply_display_requirements,
-+	.edp_backlight_control = hwss_edp_backlight_control,
-+	.edp_power_control = hwss_edp_power_control
-+};
-+
-+
-+void dcn10_hw_sequencer_construct(struct dc *dc)
-+{
-+	dc->hwss = dcn10_funcs;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h.0130~	2017-12-14 06:39:58.422903572 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h	2017-12-14 06:39:58.422903572 +0100
-@@ -0,0 +1,39 @@
-+/*
-+* Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_HWSS_DCN10_H__
-+#define __DC_HWSS_DCN10_H__
-+
-+#include "core_types.h"
-+
-+struct dc;
-+
-+void dcn10_hw_sequencer_construct(struct dc *dc);
-+extern void fill_display_configs(
-+	const struct dc_state *context,
-+	struct dm_pp_display_configuration *pp_display_cfg);
-+
-+
-+#endif /* __DC_HWSS_DCN10_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c.0130~	2017-12-14 06:39:58.422903572 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c	2017-12-14 06:39:58.422903572 +0100
-@@ -0,0 +1,70 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dcn10_ipp.h"
-+#include "reg_helper.h"
-+
-+#define REG(reg) \
-+	(ippn10->regs->reg)
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	ippn10->ipp_shift->field_name, ippn10->ipp_mask->field_name
-+
-+#define CTX \
-+	ippn10->base.ctx
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+static void dcn10_ipp_destroy(struct input_pixel_processor **ipp)
-+{
-+	kfree(TO_DCN10_IPP(*ipp));
-+	*ipp = NULL;
-+}
-+
-+static const struct ipp_funcs dcn10_ipp_funcs = {
-+	.ipp_destroy			= dcn10_ipp_destroy
-+};
-+
-+void dcn10_ipp_construct(
-+	struct dcn10_ipp *ippn10,
-+	struct dc_context *ctx,
-+	int inst,
-+	const struct dcn10_ipp_registers *regs,
-+	const struct dcn10_ipp_shift *ipp_shift,
-+	const struct dcn10_ipp_mask *ipp_mask)
-+{
-+	ippn10->base.ctx = ctx;
-+	ippn10->base.inst = inst;
-+	ippn10->base.funcs = &dcn10_ipp_funcs;
-+
-+	ippn10->regs = regs;
-+	ippn10->ipp_shift = ipp_shift;
-+	ippn10->ipp_mask = ipp_mask;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h.0130~	2017-12-14 06:39:58.422903572 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h	2017-12-14 06:39:58.422903572 +0100
-@@ -0,0 +1,167 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef _DCN10_IPP_H_
-+#define _DCN10_IPP_H_
-+
-+#include "ipp.h"
-+
-+#define TO_DCN10_IPP(ipp)\
-+	container_of(ipp, struct dcn10_ipp, base)
-+
-+#define IPP_REG_LIST_DCN(id) \
-+	SRI(FORMAT_CONTROL, CNVC_CFG, id), \
-+	SRI(DPP_CONTROL, DPP_TOP, id), \
-+	SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
-+	SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
-+	SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
-+	SRI(CURSOR0_COLOR1, CNVC_CUR, id)
-+
-+#define IPP_REG_LIST_DCN10(id) \
-+	IPP_REG_LIST_DCN(id), \
-+	SRI(CURSOR_SETTINS, HUBPREQ, id), \
-+	SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
-+	SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
-+	SRI(CURSOR_SIZE, CURSOR, id), \
-+	SRI(CURSOR_CONTROL, CURSOR, id), \
-+	SRI(CURSOR_POSITION, CURSOR, id), \
-+	SRI(CURSOR_HOT_SPOT, CURSOR, id), \
-+	SRI(CURSOR_DST_OFFSET, CURSOR, id)
-+
-+#define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT	0x4
-+#define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK		0x00000010L
-+#define CURSOR1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT	0x4
-+#define CURSOR1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK		0x00000010L
-+#define CURSOR2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT	0x4
-+#define CURSOR2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK		0x00000010L
-+#define CURSOR3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT	0x4
-+#define CURSOR3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK		0x00000010L
-+
-+#define IPP_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+#define IPP_MASK_SH_LIST_DCN(mask_sh) \
-+	IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
-+	IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
-+	IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \
-+	IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
-+	IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
-+	IPP_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
-+	IPP_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
-+	IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
-+	IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh)
-+
-+#define IPP_MASK_SH_LIST_DCN10(mask_sh) \
-+	IPP_MASK_SH_LIST_DCN(mask_sh),\
-+	IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
-+	IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
-+	IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
-+	IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
-+	IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
-+	IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
-+	IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
-+	IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
-+	IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
-+	IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
-+	IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
-+	IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
-+	IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
-+	IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
-+	IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
-+	IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
-+	IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh)
-+
-+#define IPP_DCN10_REG_FIELD_LIST(type) \
-+	type CNVC_SURFACE_PIXEL_FORMAT; \
-+	type CNVC_BYPASS; \
-+	type ALPHA_EN; \
-+	type FORMAT_EXPANSION_MODE; \
-+	type CURSOR0_DST_Y_OFFSET; \
-+	type CURSOR0_CHUNK_HDL_ADJUST; \
-+	type CUR0_MODE; \
-+	type CUR0_COLOR0; \
-+	type CUR0_COLOR1; \
-+	type CUR0_EXPANSION_MODE; \
-+	type CURSOR_SURFACE_ADDRESS_HIGH; \
-+	type CURSOR_SURFACE_ADDRESS; \
-+	type CURSOR_WIDTH; \
-+	type CURSOR_HEIGHT; \
-+	type CURSOR_MODE; \
-+	type CURSOR_2X_MAGNIFY; \
-+	type CURSOR_PITCH; \
-+	type CURSOR_LINES_PER_CHUNK; \
-+	type CURSOR_ENABLE; \
-+	type CUR0_ENABLE; \
-+	type CURSOR_X_POSITION; \
-+	type CURSOR_Y_POSITION; \
-+	type CURSOR_HOT_SPOT_X; \
-+	type CURSOR_HOT_SPOT_Y; \
-+	type CURSOR_DST_X_OFFSET; \
-+	type OUTPUT_FP
-+
-+struct dcn10_ipp_shift {
-+	IPP_DCN10_REG_FIELD_LIST(uint8_t);
-+};
-+
-+struct dcn10_ipp_mask {
-+	IPP_DCN10_REG_FIELD_LIST(uint32_t);
-+};
-+
-+struct dcn10_ipp_registers {
-+	uint32_t DPP_CONTROL;
-+	uint32_t CURSOR_SETTINS;
-+	uint32_t CURSOR_SETTINGS;
-+	uint32_t CNVC_SURFACE_PIXEL_FORMAT;
-+	uint32_t CURSOR0_CONTROL;
-+	uint32_t CURSOR0_COLOR0;
-+	uint32_t CURSOR0_COLOR1;
-+	uint32_t FORMAT_CONTROL;
-+	uint32_t CURSOR_SURFACE_ADDRESS_HIGH;
-+	uint32_t CURSOR_SURFACE_ADDRESS;
-+	uint32_t CURSOR_SIZE;
-+	uint32_t CURSOR_CONTROL;
-+	uint32_t CURSOR_POSITION;
-+	uint32_t CURSOR_HOT_SPOT;
-+	uint32_t CURSOR_DST_OFFSET;
-+};
-+
-+struct dcn10_ipp {
-+	struct input_pixel_processor base;
-+
-+	const struct dcn10_ipp_registers *regs;
-+	const struct dcn10_ipp_shift *ipp_shift;
-+	const struct dcn10_ipp_mask *ipp_mask;
-+
-+	struct dc_cursor_attributes curs_attr;
-+};
-+
-+void dcn10_ipp_construct(struct dcn10_ipp *ippn10,
-+	struct dc_context *ctx,
-+	int inst,
-+	const struct dcn10_ipp_registers *regs,
-+	const struct dcn10_ipp_shift *ipp_shift,
-+	const struct dcn10_ipp_mask *ipp_mask);
-+
-+#endif /* _DCN10_IPP_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c.0130~	2017-12-14 06:39:58.423903573 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c	2017-12-14 06:39:58.423903573 +0100
-@@ -0,0 +1,374 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "reg_helper.h"
-+#include "dcn10_mpc.h"
-+#include "dc.h"
-+#include "mem_input.h"
-+
-+#define REG(reg)\
-+	mpc10->mpc_regs->reg
-+
-+#define CTX \
-+	mpc10->base.ctx
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
-+
-+#define MODE_TOP_ONLY 1
-+#define MODE_BLEND 3
-+#define BLND_PP_ALPHA 0
-+#define BLND_GLOBAL_ALPHA 2
-+
-+
-+static void mpc10_set_bg_color(
-+		struct dcn10_mpc *mpc10,
-+		struct tg_color *bg_color,
-+		int id)
-+{
-+	/* mpc color is 12 bit.  tg_color is 10 bit */
-+	/* todo: might want to use 16 bit to represent color and have each
-+	 * hw block translate to correct color depth.
-+	 */
-+	uint32_t bg_r_cr = bg_color->color_r_cr << 2;
-+	uint32_t bg_g_y = bg_color->color_g_y << 2;
-+	uint32_t bg_b_cb = bg_color->color_b_cb << 2;
-+
-+	REG_SET(MPCC_BG_R_CR[id], 0,
-+			MPCC_BG_R_CR, bg_r_cr);
-+	REG_SET(MPCC_BG_G_Y[id], 0,
-+			MPCC_BG_G_Y, bg_g_y);
-+	REG_SET(MPCC_BG_B_CB[id], 0,
-+			MPCC_BG_B_CB, bg_b_cb);
-+}
-+
-+void mpc10_assert_idle_mpcc(struct mpc *mpc, int id)
-+{
-+	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
-+
-+	ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id));
-+	REG_WAIT(MPCC_STATUS[id],
-+			MPCC_IDLE, 1,
-+			1, 100000);
-+}
-+
-+static int mpc10_get_idle_mpcc_id(struct dcn10_mpc *mpc10)
-+{
-+	int i;
-+	int last_free_mpcc_id = -1;
-+
-+	for (i = 0; i < mpc10->num_mpcc; i++) {
-+		uint32_t is_idle = 0;
-+
-+		if (mpc10->mpcc_in_use_mask & 1 << i)
-+			continue;
-+
-+		last_free_mpcc_id = i;
-+		REG_GET(MPCC_STATUS[i], MPCC_IDLE, &is_idle);
-+		if (is_idle)
-+			return i;
-+	}
-+
-+	/* This assert should never trigger, we have mpcc leak if it does */
-+	ASSERT(last_free_mpcc_id != -1);
-+
-+	mpc10_assert_idle_mpcc(&mpc10->base, last_free_mpcc_id);
-+	return last_free_mpcc_id;
-+}
-+
-+static void mpc10_assert_mpcc_idle_before_connect(struct dcn10_mpc *mpc10, int id)
-+{
-+	unsigned int top_sel, mpc_busy, mpc_idle;
-+
-+	REG_GET(MPCC_TOP_SEL[id],
-+			MPCC_TOP_SEL, &top_sel);
-+
-+	if (top_sel == 0xf) {
-+		REG_GET_2(MPCC_STATUS[id],
-+				MPCC_BUSY, &mpc_busy,
-+				MPCC_IDLE, &mpc_idle);
-+
-+		ASSERT(mpc_busy == 0);
-+		ASSERT(mpc_idle == 1);
-+	}
-+}
-+
-+void mpc10_mpcc_remove(
-+		struct mpc *mpc,
-+		struct mpc_tree_cfg *tree_cfg,
-+		int opp_id,
-+		int dpp_id)
-+{
-+	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
-+	int mpcc_id, z_idx;
-+
-+	/* find z_idx for the dpp to be removed */
-+	for (z_idx = 0; z_idx < tree_cfg->num_pipes; z_idx++)
-+		if (tree_cfg->dpp[z_idx] == dpp_id)
-+			break;
-+
-+	if (z_idx == tree_cfg->num_pipes) {
-+		/* In case of resume from S3/S4, remove mpcc from bios left over */
-+		REG_SET(MPCC_OPP_ID[dpp_id], 0,
-+				MPCC_OPP_ID, 0xf);
-+		REG_SET(MPCC_TOP_SEL[dpp_id], 0,
-+				MPCC_TOP_SEL, 0xf);
-+		REG_SET(MPCC_BOT_SEL[dpp_id], 0,
-+				MPCC_BOT_SEL, 0xf);
-+		return;
-+	}
-+
-+	mpcc_id = tree_cfg->mpcc[z_idx];
-+
-+	REG_SET(MPCC_OPP_ID[mpcc_id], 0,
-+			MPCC_OPP_ID, 0xf);
-+	REG_SET(MPCC_TOP_SEL[mpcc_id], 0,
-+			MPCC_TOP_SEL, 0xf);
-+	REG_SET(MPCC_BOT_SEL[mpcc_id], 0,
-+			MPCC_BOT_SEL, 0xf);
-+
-+	if (z_idx > 0) {
-+		int top_mpcc_id = tree_cfg->mpcc[z_idx - 1];
-+
-+		if (z_idx + 1 < tree_cfg->num_pipes)
-+			/* mpcc to be removed is in the middle of the tree */
-+			REG_SET(MPCC_BOT_SEL[top_mpcc_id], 0,
-+					MPCC_BOT_SEL, tree_cfg->mpcc[z_idx + 1]);
-+		else {
-+			/* mpcc to be removed is at the bottom of the tree */
-+			REG_SET(MPCC_BOT_SEL[top_mpcc_id], 0,
-+					MPCC_BOT_SEL, 0xf);
-+			REG_UPDATE(MPCC_CONTROL[top_mpcc_id],
-+					MPCC_MODE, MODE_TOP_ONLY);
-+		}
-+	} else if (tree_cfg->num_pipes > 1)
-+		/* mpcc to be removed is at the top of the tree */
-+		REG_SET(MUX[opp_id], 0,
-+				MPC_OUT_MUX, tree_cfg->mpcc[z_idx + 1]);
-+	else
-+		/* mpcc to be removed is the only one in the tree */
-+		REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, 0xf);
-+
-+	/* mark this mpcc as not in use */
-+	mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id);
-+	tree_cfg->num_pipes--;
-+	for (; z_idx < tree_cfg->num_pipes; z_idx++) {
-+		tree_cfg->dpp[z_idx] = tree_cfg->dpp[z_idx + 1];
-+		tree_cfg->mpcc[z_idx] = tree_cfg->mpcc[z_idx + 1];
-+	}
-+	tree_cfg->dpp[tree_cfg->num_pipes] = 0xdeadbeef;
-+	tree_cfg->mpcc[tree_cfg->num_pipes] = 0xdeadbeef;
-+}
-+
-+static void mpc10_add_to_tree_cfg(
-+	struct mpc *mpc,
-+	struct mpcc_cfg *cfg,
-+	int mpcc_id)
-+{
-+	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
-+	int mpcc_mode = MODE_TOP_ONLY;
-+	int position = cfg->z_index;
-+	struct mpc_tree_cfg *tree_cfg = cfg->tree_cfg;
-+	int alpha_blnd_mode = cfg->per_pixel_alpha ?
-+			BLND_PP_ALPHA : BLND_GLOBAL_ALPHA;
-+	int z_idx;
-+
-+	REG_SET(MPCC_OPP_ID[mpcc_id], 0,
-+			MPCC_OPP_ID, cfg->opp_id);
-+
-+	REG_SET(MPCC_TOP_SEL[mpcc_id], 0,
-+			MPCC_TOP_SEL, cfg->dpp_id);
-+
-+	if (position == 0) {
-+		/* idle dpp/mpcc is added to the top layer of tree */
-+
-+		if (tree_cfg->num_pipes > 0) {
-+			/* get instance of previous top mpcc */
-+			int prev_top_mpcc_id = tree_cfg->mpcc[0];
-+
-+			REG_SET(MPCC_BOT_SEL[mpcc_id], 0,
-+					MPCC_BOT_SEL, prev_top_mpcc_id);
-+			mpcc_mode = MODE_BLEND;
-+		}
-+
-+		/* opp will get new output. from new added mpcc */
-+		REG_SET(MUX[cfg->opp_id], 0, MPC_OUT_MUX, mpcc_id);
-+
-+	} else if (position == tree_cfg->num_pipes) {
-+		/* idle dpp/mpcc is added to the bottom layer of tree */
-+
-+		/* get instance of previous bottom mpcc, set to middle layer */
-+		int prev_bot_mpcc_id = tree_cfg->mpcc[tree_cfg->num_pipes - 1];
-+
-+		REG_SET(MPCC_BOT_SEL[prev_bot_mpcc_id], 0,
-+				MPCC_BOT_SEL, mpcc_id);
-+		REG_UPDATE(MPCC_CONTROL[prev_bot_mpcc_id],
-+				MPCC_MODE, MODE_BLEND);
-+
-+		/* mpcc_id become new bottom mpcc*/
-+		REG_SET(MPCC_BOT_SEL[mpcc_id], 0,
-+				MPCC_BOT_SEL, 0xf);
-+
-+	} else {
-+		/* idle dpp/mpcc is added to middle of tree */
-+		int above_mpcc_id = tree_cfg->mpcc[position - 1];
-+		int below_mpcc_id = tree_cfg->mpcc[position];
-+
-+		/* mpcc above new mpcc_id has new bottom mux*/
-+		REG_SET(MPCC_BOT_SEL[above_mpcc_id], 0,
-+				MPCC_BOT_SEL, mpcc_id);
-+		REG_UPDATE(MPCC_CONTROL[above_mpcc_id],
-+				MPCC_MODE, MODE_BLEND);
-+
-+		/* mpcc_id bottom mux is from below mpcc*/
-+		REG_SET(MPCC_BOT_SEL[mpcc_id], 0,
-+				MPCC_BOT_SEL, below_mpcc_id);
-+		mpcc_mode = MODE_BLEND;
-+	}
-+
-+	REG_SET_4(MPCC_CONTROL[mpcc_id], 0xffffffff,
-+		MPCC_MODE, mpcc_mode,
-+		MPCC_ALPHA_BLND_MODE, alpha_blnd_mode,
-+		MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha,
-+		MPCC_BLND_ACTIVE_OVERLAP_ONLY, false);
-+
-+	/* update mpc_tree_cfg with new mpcc */
-+	for (z_idx = tree_cfg->num_pipes; z_idx > position; z_idx--) {
-+		tree_cfg->dpp[z_idx] = tree_cfg->dpp[z_idx - 1];
-+		tree_cfg->mpcc[z_idx] = tree_cfg->mpcc[z_idx - 1];
-+	}
-+	tree_cfg->dpp[position] = cfg->dpp_id;
-+	tree_cfg->mpcc[position] = mpcc_id;
-+	tree_cfg->num_pipes++;
-+}
-+
-+int mpc10_mpcc_add(struct mpc *mpc, struct mpcc_cfg *cfg)
-+{
-+	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
-+	int mpcc_id, z_idx;
-+
-+	ASSERT(cfg->z_index < mpc10->num_mpcc);
-+
-+	/* check in dpp already exists in mpc tree */
-+	for (z_idx = 0; z_idx < cfg->tree_cfg->num_pipes; z_idx++)
-+		if (cfg->tree_cfg->dpp[z_idx] == cfg->dpp_id)
-+			break;
-+	if (z_idx == cfg->tree_cfg->num_pipes) {
-+		ASSERT(cfg->z_index <= cfg->tree_cfg->num_pipes);
-+		mpcc_id = mpc10_get_idle_mpcc_id(mpc10);
-+
-+		/*
-+		 * TODO: remove hack
-+		 * Note: currently there is a bug in init_hw such that
-+		 * on resume from hibernate, BIOS sets up MPCC0, and
-+		 * we do mpcc_remove but the mpcc cannot go to idle
-+		 * after remove. This cause us to pick mpcc1 here,
-+		 * which causes a pstate hang for yet unknown reason.
-+		 */
-+		mpcc_id = cfg->dpp_id;
-+		/* end hack*/
-+
-+		ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id));
-+
-+		if (mpc->ctx->dc->debug.sanity_checks)
-+			mpc10_assert_mpcc_idle_before_connect(mpc10, mpcc_id);
-+	} else {
-+		ASSERT(cfg->z_index < cfg->tree_cfg->num_pipes);
-+		mpcc_id = cfg->tree_cfg->mpcc[z_idx];
-+		mpc10_mpcc_remove(mpc, cfg->tree_cfg, cfg->opp_id, cfg->dpp_id);
-+	}
-+
-+	/* add dpp/mpcc pair to mpc_tree_cfg and update mpcc registers */
-+	mpc10_add_to_tree_cfg(mpc, cfg, mpcc_id);
-+
-+	/* set background color */
-+	mpc10_set_bg_color(mpc10, &cfg->black_color, mpcc_id);
-+
-+	/* mark this mpcc as in use */
-+	mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
-+
-+	return mpcc_id;
-+}
-+
-+void mpc10_update_blend_mode(
-+		struct mpc *mpc,
-+		struct mpcc_cfg *cfg)
-+{
-+	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
-+	int mpcc_id, z_idx;
-+	int alpha_blnd_mode = cfg->per_pixel_alpha ?
-+			BLND_PP_ALPHA : BLND_GLOBAL_ALPHA;
-+
-+	/* find z_idx for the dpp that requires blending mode update*/
-+	for (z_idx = 0; z_idx < cfg->tree_cfg->num_pipes; z_idx++)
-+		if (cfg->tree_cfg->dpp[z_idx] == cfg->dpp_id)
-+			break;
-+
-+	ASSERT(z_idx < cfg->tree_cfg->num_pipes);
-+	mpcc_id = cfg->tree_cfg->mpcc[z_idx];
-+
-+	REG_UPDATE_2(MPCC_CONTROL[mpcc_id],
-+			MPCC_ALPHA_BLND_MODE, alpha_blnd_mode,
-+			MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha);
-+}
-+
-+int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id)
-+{
-+	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
-+	int opp_id = 0xF;
-+
-+	REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
-+
-+	return opp_id;
-+}
-+
-+const struct mpc_funcs dcn10_mpc_funcs = {
-+		.add = mpc10_mpcc_add,
-+		.remove = mpc10_mpcc_remove,
-+		.wait_for_idle = mpc10_assert_idle_mpcc,
-+		.update_blend_mode = mpc10_update_blend_mode,
-+		.get_opp_id = mpc10_get_opp_id,
-+};
-+
-+void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
-+	struct dc_context *ctx,
-+	const struct dcn_mpc_registers *mpc_regs,
-+	const struct dcn_mpc_shift *mpc_shift,
-+	const struct dcn_mpc_mask *mpc_mask,
-+	int num_mpcc)
-+{
-+	mpc10->base.ctx = ctx;
-+
-+	mpc10->base.funcs = &dcn10_mpc_funcs;
-+
-+	mpc10->mpc_regs = mpc_regs;
-+	mpc10->mpc_shift = mpc_shift;
-+	mpc10->mpc_mask = mpc_mask;
-+
-+	mpc10->mpcc_in_use_mask = 0;
-+	mpc10->num_mpcc = num_mpcc;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h.0130~	2017-12-14 06:39:58.423903573 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h	2017-12-14 06:39:58.423903573 +0100
-@@ -0,0 +1,139 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_MPCC_DCN10_H__
-+#define __DC_MPCC_DCN10_H__
-+
-+#include "mpc.h"
-+
-+#define TO_DCN10_MPC(mpc_base) \
-+	container_of(mpc_base, struct dcn10_mpc, base)
-+
-+#define MAX_MPCC 6
-+#define MAX_OPP 6
-+
-+#define MPC_COMMON_REG_LIST_DCN1_0(inst) \
-+	SRII(MPCC_TOP_SEL, MPCC, inst),\
-+	SRII(MPCC_BOT_SEL, MPCC, inst),\
-+	SRII(MPCC_CONTROL, MPCC, inst),\
-+	SRII(MPCC_STATUS, MPCC, inst),\
-+	SRII(MPCC_OPP_ID, MPCC, inst),\
-+	SRII(MPCC_BG_G_Y, MPCC, inst),\
-+	SRII(MPCC_BG_R_CR, MPCC, inst),\
-+	SRII(MPCC_BG_B_CB, MPCC, inst),\
-+	SRII(MPCC_BG_B_CB, MPCC, inst)
-+
-+#define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \
-+	SRII(MUX, MPC_OUT, inst)
-+
-+#define MPC_COMMON_REG_VARIABLE_LIST \
-+	uint32_t MPCC_TOP_SEL[MAX_MPCC]; \
-+	uint32_t MPCC_BOT_SEL[MAX_MPCC]; \
-+	uint32_t MPCC_CONTROL[MAX_MPCC]; \
-+	uint32_t MPCC_STATUS[MAX_MPCC]; \
-+	uint32_t MPCC_OPP_ID[MAX_MPCC]; \
-+	uint32_t MPCC_BG_G_Y[MAX_MPCC]; \
-+	uint32_t MPCC_BG_R_CR[MAX_MPCC]; \
-+	uint32_t MPCC_BG_B_CB[MAX_MPCC]; \
-+	uint32_t MUX[MAX_OPP];
-+
-+#define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
-+	SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
-+	SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
-+	SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
-+	SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
-+	SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
-+	SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
-+	SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
-+	SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\
-+	SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\
-+	SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\
-+	SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\
-+	SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\
-+	SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh)
-+
-+#define MPC_REG_FIELD_LIST(type) \
-+	type MPCC_TOP_SEL;\
-+	type MPCC_BOT_SEL;\
-+	type MPCC_MODE;\
-+	type MPCC_ALPHA_BLND_MODE;\
-+	type MPCC_ALPHA_MULTIPLIED_MODE;\
-+	type MPCC_BLND_ACTIVE_OVERLAP_ONLY;\
-+	type MPCC_IDLE;\
-+	type MPCC_BUSY;\
-+	type MPCC_OPP_ID;\
-+	type MPCC_BG_G_Y;\
-+	type MPCC_BG_R_CR;\
-+	type MPCC_BG_B_CB;\
-+	type MPC_OUT_MUX;
-+
-+struct dcn_mpc_registers {
-+	MPC_COMMON_REG_VARIABLE_LIST
-+};
-+
-+struct dcn_mpc_shift {
-+	MPC_REG_FIELD_LIST(uint8_t)
-+};
-+
-+struct dcn_mpc_mask {
-+	MPC_REG_FIELD_LIST(uint32_t)
-+};
-+
-+struct dcn10_mpc {
-+	struct mpc base;
-+
-+	int mpcc_in_use_mask;
-+	int num_mpcc;
-+	const struct dcn_mpc_registers *mpc_regs;
-+	const struct dcn_mpc_shift *mpc_shift;
-+	const struct dcn_mpc_mask *mpc_mask;
-+};
-+
-+void dcn10_mpc_construct(struct dcn10_mpc *mpcc10,
-+	struct dc_context *ctx,
-+	const struct dcn_mpc_registers *mpc_regs,
-+	const struct dcn_mpc_shift *mpc_shift,
-+	const struct dcn_mpc_mask *mpc_mask,
-+	int num_mpcc);
-+
-+int mpc10_mpcc_add(
-+		struct mpc *mpc,
-+		struct mpcc_cfg *cfg);
-+
-+void mpc10_mpcc_remove(
-+		struct mpc *mpc,
-+		struct mpc_tree_cfg *tree_cfg,
-+		int opp_id,
-+		int dpp_id);
-+
-+void mpc10_assert_idle_mpcc(
-+		struct mpc *mpc,
-+		int id);
-+
-+void mpc10_update_blend_mode(
-+		struct mpc *mpc,
-+		struct mpcc_cfg *cfg);
-+int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c.0130~	2017-12-14 06:39:58.423903573 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c	2017-12-14 06:39:58.423903573 +0100
-@@ -0,0 +1,348 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dcn10_opp.h"
-+#include "reg_helper.h"
-+
-+#define REG(reg) \
-+	(oppn10->regs->reg)
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	oppn10->opp_shift->field_name, oppn10->opp_mask->field_name
-+
-+#define CTX \
-+	oppn10->base.ctx
-+
-+
-+/************* FORMATTER ************/
-+
-+/**
-+ *	set_truncation
-+ *	1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
-+ *	2) enable truncation
-+ *	3) HW remove 12bit FMT support for DCE11 power saving reason.
-+ */
-+static void opp1_set_truncation(
-+		struct dcn10_opp *oppn10,
-+		const struct bit_depth_reduction_params *params)
-+{
-+	REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
-+		FMT_TRUNCATE_EN, params->flags.TRUNCATE_ENABLED,
-+		FMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH,
-+		FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE);
-+}
-+
-+static void opp1_set_spatial_dither(
-+	struct dcn10_opp *oppn10,
-+	const struct bit_depth_reduction_params *params)
-+{
-+	/*Disable spatial (random) dithering*/
-+	REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL,
-+			FMT_SPATIAL_DITHER_EN, 0,
-+			FMT_SPATIAL_DITHER_MODE, 0,
-+			FMT_SPATIAL_DITHER_DEPTH, 0,
-+			FMT_TEMPORAL_DITHER_EN, 0,
-+			FMT_HIGHPASS_RANDOM_ENABLE, 0,
-+			FMT_FRAME_RANDOM_ENABLE, 0,
-+			FMT_RGB_RANDOM_ENABLE, 0);
-+
-+
-+	/* only use FRAME_COUNTER_MAX if frameRandom == 1*/
-+	if (params->flags.FRAME_RANDOM == 1) {
-+		if (params->flags.SPATIAL_DITHER_DEPTH == 0 || params->flags.SPATIAL_DITHER_DEPTH == 1) {
-+			REG_UPDATE_2(FMT_CONTROL,
-+					FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15,
-+					FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2);
-+		} else if (params->flags.SPATIAL_DITHER_DEPTH == 2) {
-+			REG_UPDATE_2(FMT_CONTROL,
-+					FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3,
-+					FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1);
-+		} else {
-+			return;
-+		}
-+	} else {
-+		REG_UPDATE_2(FMT_CONTROL,
-+				FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0,
-+				FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0);
-+	}
-+
-+	/*Set seed for random values for
-+	 * spatial dithering for R,G,B channels*/
-+
-+	REG_SET(FMT_DITHER_RAND_R_SEED, 0,
-+			FMT_RAND_R_SEED, params->r_seed_value);
-+
-+	REG_SET(FMT_DITHER_RAND_G_SEED, 0,
-+			FMT_RAND_G_SEED, params->g_seed_value);
-+
-+	REG_SET(FMT_DITHER_RAND_B_SEED, 0,
-+			FMT_RAND_B_SEED, params->b_seed_value);
-+
-+	/* FMT_OFFSET_R_Cr  31:16 0x0 Setting the zero
-+	 * offset for the R/Cr channel, lower 4LSB
-+	 * is forced to zeros. Typically set to 0
-+	 * RGB and 0x80000 YCbCr.
-+	 */
-+	/* FMT_OFFSET_G_Y   31:16 0x0 Setting the zero
-+	 * offset for the G/Y  channel, lower 4LSB is
-+	 * forced to zeros. Typically set to 0 RGB
-+	 * and 0x80000 YCbCr.
-+	 */
-+	/* FMT_OFFSET_B_Cb  31:16 0x0 Setting the zero
-+	 * offset for the B/Cb channel, lower 4LSB is
-+	 * forced to zeros. Typically set to 0 RGB and
-+	 * 0x80000 YCbCr.
-+	 */
-+
-+	REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL,
-+			/*Enable spatial dithering*/
-+			FMT_SPATIAL_DITHER_EN, params->flags.SPATIAL_DITHER_ENABLED,
-+			/* Set spatial dithering mode
-+			 * (default is Seed patterrn AAAA...)
-+			 */
-+			FMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE,
-+			/*Set spatial dithering bit depth*/
-+			FMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH,
-+			/*Disable High pass filter*/
-+			FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM,
-+			/*Reset only at startup*/
-+			FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM,
-+			/*Set RGB data dithered with x^28+x^3+1*/
-+			FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
-+}
-+
-+void opp1_program_bit_depth_reduction(
-+	struct output_pixel_processor *opp,
-+	const struct bit_depth_reduction_params *params)
-+{
-+	struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
-+
-+	opp1_set_truncation(oppn10, params);
-+	opp1_set_spatial_dither(oppn10, params);
-+	/* TODO
-+	 * set_temporal_dither(oppn10, params);
-+	 */
-+}
-+
-+/**
-+ *	set_pixel_encoding
-+ *
-+ *	Set Pixel Encoding
-+ *		0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
-+ *		1: YCbCr 4:2:2
-+ */
-+static void opp1_set_pixel_encoding(
-+	struct dcn10_opp *oppn10,
-+	const struct clamping_and_pixel_encoding_params *params)
-+{
-+	switch (params->pixel_encoding)	{
-+
-+	case PIXEL_ENCODING_RGB:
-+	case PIXEL_ENCODING_YCBCR444:
-+		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
-+		break;
-+	case PIXEL_ENCODING_YCBCR422:
-+		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1);
-+		break;
-+	case PIXEL_ENCODING_YCBCR420:
-+		REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+/**
-+ *	Set Clamping
-+ *	1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
-+ *		1 for 8 bpc
-+ *		2 for 10 bpc
-+ *		3 for 12 bpc
-+ *		7 for programable
-+ *	2) Enable clamp if Limited range requested
-+ */
-+static void opp1_set_clamping(
-+	struct dcn10_opp *oppn10,
-+	const struct clamping_and_pixel_encoding_params *params)
-+{
-+	REG_UPDATE_2(FMT_CLAMP_CNTL,
-+			FMT_CLAMP_DATA_EN, 0,
-+			FMT_CLAMP_COLOR_FORMAT, 0);
-+
-+	switch (params->clamping_level) {
-+	case CLAMPING_FULL_RANGE:
-+		REG_UPDATE_2(FMT_CLAMP_CNTL,
-+				FMT_CLAMP_DATA_EN, 1,
-+				FMT_CLAMP_COLOR_FORMAT, 0);
-+		break;
-+	case CLAMPING_LIMITED_RANGE_8BPC:
-+		REG_UPDATE_2(FMT_CLAMP_CNTL,
-+				FMT_CLAMP_DATA_EN, 1,
-+				FMT_CLAMP_COLOR_FORMAT, 1);
-+		break;
-+	case CLAMPING_LIMITED_RANGE_10BPC:
-+		REG_UPDATE_2(FMT_CLAMP_CNTL,
-+				FMT_CLAMP_DATA_EN, 1,
-+				FMT_CLAMP_COLOR_FORMAT, 2);
-+
-+		break;
-+	case CLAMPING_LIMITED_RANGE_12BPC:
-+		REG_UPDATE_2(FMT_CLAMP_CNTL,
-+				FMT_CLAMP_DATA_EN, 1,
-+				FMT_CLAMP_COLOR_FORMAT, 3);
-+		break;
-+	case CLAMPING_LIMITED_RANGE_PROGRAMMABLE:
-+		/* TODO */
-+	default:
-+		break;
-+	}
-+
-+}
-+
-+void opp1_set_dyn_expansion(
-+	struct output_pixel_processor *opp,
-+	enum dc_color_space color_sp,
-+	enum dc_color_depth color_dpth,
-+	enum signal_type signal)
-+{
-+	struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
-+
-+	REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
-+			FMT_DYNAMIC_EXP_EN, 0,
-+			FMT_DYNAMIC_EXP_MODE, 0);
-+
-+	/*00 - 10-bit -> 12-bit dynamic expansion*/
-+	/*01 - 8-bit  -> 12-bit dynamic expansion*/
-+	if (signal == SIGNAL_TYPE_HDMI_TYPE_A ||
-+		signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+		signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
-+		signal == SIGNAL_TYPE_VIRTUAL) {
-+		switch (color_dpth) {
-+		case COLOR_DEPTH_888:
-+			REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
-+				FMT_DYNAMIC_EXP_EN, 1,
-+				FMT_DYNAMIC_EXP_MODE, 1);
-+			break;
-+		case COLOR_DEPTH_101010:
-+			REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
-+				FMT_DYNAMIC_EXP_EN, 1,
-+				FMT_DYNAMIC_EXP_MODE, 0);
-+			break;
-+		case COLOR_DEPTH_121212:
-+			REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
-+				FMT_DYNAMIC_EXP_EN, 1,/*otherwise last two bits are zero*/
-+				FMT_DYNAMIC_EXP_MODE, 0);
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+}
-+
-+static void opp1_program_clamping_and_pixel_encoding(
-+	struct output_pixel_processor *opp,
-+	const struct clamping_and_pixel_encoding_params *params)
-+{
-+	struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
-+
-+	opp1_set_clamping(oppn10, params);
-+	opp1_set_pixel_encoding(oppn10, params);
-+}
-+
-+void opp1_program_fmt(
-+	struct output_pixel_processor *opp,
-+	struct bit_depth_reduction_params *fmt_bit_depth,
-+	struct clamping_and_pixel_encoding_params *clamping)
-+{
-+	struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
-+
-+	if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
-+		REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0);
-+
-+	/* dithering is affected by <CrtcSourceSelect>, hence should be
-+	 * programmed afterwards */
-+	opp1_program_bit_depth_reduction(
-+		opp,
-+		fmt_bit_depth);
-+
-+	opp1_program_clamping_and_pixel_encoding(
-+		opp,
-+		clamping);
-+
-+	return;
-+}
-+
-+void opp1_set_stereo_polarity(
-+		struct output_pixel_processor *opp,
-+		bool enable, bool rightEyePolarity)
-+{
-+	struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
-+
-+	REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, enable);
-+}
-+
-+/*****************************************/
-+/* Constructor, Destructor               */
-+/*****************************************/
-+
-+void opp1_destroy(struct output_pixel_processor **opp)
-+{
-+	kfree(TO_DCN10_OPP(*opp));
-+	*opp = NULL;
-+}
-+
-+static struct opp_funcs dcn10_opp_funcs = {
-+		.opp_set_dyn_expansion = opp1_set_dyn_expansion,
-+		.opp_program_fmt = opp1_program_fmt,
-+		.opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction,
-+		.opp_set_stereo_polarity = opp1_set_stereo_polarity,
-+		.opp_destroy = opp1_destroy
-+};
-+
-+void dcn10_opp_construct(struct dcn10_opp *oppn10,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dcn10_opp_registers *regs,
-+	const struct dcn10_opp_shift *opp_shift,
-+	const struct dcn10_opp_mask *opp_mask)
-+{
-+	int i;
-+	oppn10->base.ctx = ctx;
-+	oppn10->base.inst = inst;
-+	oppn10->base.funcs = &dcn10_opp_funcs;
-+
-+	oppn10->base.mpc_tree.dpp[0] = inst;
-+	oppn10->base.mpc_tree.mpcc[0] = inst;
-+	oppn10->base.mpc_tree.num_pipes = 1;
-+	for (i = 0; i < MAX_PIPES; i++)
-+		oppn10->base.mpcc_disconnect_pending[i] = false;
-+
-+	oppn10->regs = regs;
-+	oppn10->opp_shift = opp_shift;
-+	oppn10->opp_mask = opp_mask;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h.0130~	2017-12-14 06:39:58.423903573 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h	2017-12-14 06:39:58.423903573 +0100
-@@ -0,0 +1,157 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_OPP_DCN10_H__
-+#define __DC_OPP_DCN10_H__
-+
-+#include "opp.h"
-+
-+#define TO_DCN10_OPP(opp)\
-+	container_of(opp, struct dcn10_opp, base)
-+
-+#define OPP_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+#define OPP_REG_LIST_DCN(id) \
-+	SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
-+	SRI(FMT_CONTROL, FMT, id), \
-+	SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
-+	SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
-+	SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
-+	SRI(FMT_CLAMP_CNTL, FMT, id), \
-+	SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
-+	SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id)
-+
-+#define OPP_REG_LIST_DCN10(id) \
-+	OPP_REG_LIST_DCN(id)
-+
-+#define OPP_MASK_SH_LIST_DCN(mask_sh) \
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh), \
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh), \
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh), \
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh), \
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh), \
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh), \
-+	OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \
-+	OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \
-+	OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \
-+	OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \
-+	OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh), \
-+	OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \
-+	OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \
-+	OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \
-+	OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \
-+	OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \
-+	OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \
-+	OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \
-+	OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh)
-+
-+#define OPP_MASK_SH_LIST_DCN10(mask_sh) \
-+	OPP_MASK_SH_LIST_DCN(mask_sh)
-+
-+#define OPP_DCN10_REG_FIELD_LIST(type) \
-+	type FMT_TRUNCATE_EN; \
-+	type FMT_TRUNCATE_DEPTH; \
-+	type FMT_TRUNCATE_MODE; \
-+	type FMT_SPATIAL_DITHER_EN; \
-+	type FMT_SPATIAL_DITHER_MODE; \
-+	type FMT_SPATIAL_DITHER_DEPTH; \
-+	type FMT_TEMPORAL_DITHER_EN; \
-+	type FMT_HIGHPASS_RANDOM_ENABLE; \
-+	type FMT_FRAME_RANDOM_ENABLE; \
-+	type FMT_RGB_RANDOM_ENABLE; \
-+	type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \
-+	type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \
-+	type FMT_RAND_R_SEED; \
-+	type FMT_RAND_G_SEED; \
-+	type FMT_RAND_B_SEED; \
-+	type FMT_PIXEL_ENCODING; \
-+	type FMT_CLAMP_DATA_EN; \
-+	type FMT_CLAMP_COLOR_FORMAT; \
-+	type FMT_DYNAMIC_EXP_EN; \
-+	type FMT_DYNAMIC_EXP_MODE; \
-+	type FMT_MAP420MEM_PWR_FORCE; \
-+	type FMT_STEREOSYNC_OVERRIDE;
-+
-+struct dcn10_opp_shift {
-+	OPP_DCN10_REG_FIELD_LIST(uint8_t)
-+};
-+
-+struct dcn10_opp_mask {
-+	OPP_DCN10_REG_FIELD_LIST(uint32_t)
-+};
-+
-+struct dcn10_opp_registers {
-+	uint32_t FMT_BIT_DEPTH_CONTROL;
-+	uint32_t FMT_CONTROL;
-+	uint32_t FMT_DITHER_RAND_R_SEED;
-+	uint32_t FMT_DITHER_RAND_G_SEED;
-+	uint32_t FMT_DITHER_RAND_B_SEED;
-+	uint32_t FMT_CLAMP_CNTL;
-+	uint32_t FMT_DYNAMIC_EXP_CNTL;
-+	uint32_t FMT_MAP420_MEMORY_CONTROL;
-+};
-+
-+struct dcn10_opp {
-+	struct output_pixel_processor base;
-+
-+	const struct dcn10_opp_registers *regs;
-+	const struct dcn10_opp_shift *opp_shift;
-+	const struct dcn10_opp_mask *opp_mask;
-+
-+	bool is_write_to_ram_a_safe;
-+};
-+
-+void dcn10_opp_construct(struct dcn10_opp *oppn10,
-+	struct dc_context *ctx,
-+	uint32_t inst,
-+	const struct dcn10_opp_registers *regs,
-+	const struct dcn10_opp_shift *opp_shift,
-+	const struct dcn10_opp_mask *opp_mask);
-+
-+void opp1_set_dyn_expansion(
-+	struct output_pixel_processor *opp,
-+	enum dc_color_space color_sp,
-+	enum dc_color_depth color_dpth,
-+	enum signal_type signal);
-+
-+void opp1_program_fmt(
-+	struct output_pixel_processor *opp,
-+	struct bit_depth_reduction_params *fmt_bit_depth,
-+	struct clamping_and_pixel_encoding_params *clamping);
-+
-+void opp1_program_bit_depth_reduction(
-+	struct output_pixel_processor *opp,
-+	const struct bit_depth_reduction_params *params);
-+
-+void opp1_set_stereo_polarity(
-+		struct output_pixel_processor *opp,
-+		bool enable, bool rightEyePolarity);
-+
-+void opp1_destroy(struct output_pixel_processor **opp);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c.0130~	2017-12-14 06:39:58.423903573 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c	2017-12-14 06:39:58.423903573 +0100
-@@ -0,0 +1,1500 @@
-+/*
-+* Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dc.h"
-+
-+#include "resource.h"
-+#include "include/irq_service_interface.h"
-+#include "dcn10/dcn10_resource.h"
-+
-+#include "dcn10/dcn10_ipp.h"
-+#include "dcn10/dcn10_mpc.h"
-+#include "irq/dcn10/irq_service_dcn10.h"
-+#include "dcn10/dcn10_dpp.h"
-+#include "dcn10/dcn10_timing_generator.h"
-+#include "dcn10/dcn10_hw_sequencer.h"
-+#include "dce110/dce110_hw_sequencer.h"
-+#include "dcn10/dcn10_opp.h"
-+#include "dce/dce_link_encoder.h"
-+#include "dce/dce_stream_encoder.h"
-+#include "dce/dce_clocks.h"
-+#include "dce/dce_clock_source.h"
-+#include "dce/dce_audio.h"
-+#include "dce/dce_hwseq.h"
-+#include "../virtual/virtual_stream_encoder.h"
-+#include "dce110/dce110_resource.h"
-+#include "dce112/dce112_resource.h"
-+#include "dcn10_hubp.h"
-+#include "dcn10_hubbub.h"
-+
-+#include "vega10/soc15ip.h"
-+
-+#include "raven1/DCN/dcn_1_0_offset.h"
-+#include "raven1/DCN/dcn_1_0_sh_mask.h"
-+
-+#include "raven1/NBIO/nbio_7_0_offset.h"
-+
-+#include "raven1/MMHUB/mmhub_9_1_offset.h"
-+#include "raven1/MMHUB/mmhub_9_1_sh_mask.h"
-+
-+#include "reg_helper.h"
-+#include "dce/dce_abm.h"
-+#include "dce/dce_dmcu.h"
-+
-+#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
-+	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f
-+	#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
-+	#define mmDP1_DP_DPHY_INTERNAL_CTRL		0x220f
-+	#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
-+	#define mmDP2_DP_DPHY_INTERNAL_CTRL		0x230f
-+	#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
-+	#define mmDP3_DP_DPHY_INTERNAL_CTRL		0x240f
-+	#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
-+	#define mmDP4_DP_DPHY_INTERNAL_CTRL		0x250f
-+	#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
-+	#define mmDP5_DP_DPHY_INTERNAL_CTRL		0x260f
-+	#define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
-+	#define mmDP6_DP_DPHY_INTERNAL_CTRL		0x270f
-+	#define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
-+#endif
-+
-+
-+enum dcn10_clk_src_array_id {
-+	DCN10_CLK_SRC_PLL0,
-+	DCN10_CLK_SRC_PLL1,
-+	DCN10_CLK_SRC_PLL2,
-+	DCN10_CLK_SRC_PLL3,
-+	DCN10_CLK_SRC_TOTAL
-+};
-+
-+/* begin *********************
-+ * macros to expend register list macro defined in HW object header file */
-+
-+/* DCN */
-+#define BASE_INNER(seg) \
-+	DCE_BASE__INST0_SEG ## seg
-+
-+#define BASE(seg) \
-+	BASE_INNER(seg)
-+
-+#define SR(reg_name)\
-+		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
-+					mm ## reg_name
-+
-+#define SRI(reg_name, block, id)\
-+	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-+					mm ## block ## id ## _ ## reg_name
-+
-+
-+#define SRII(reg_name, block, id)\
-+	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-+					mm ## block ## id ## _ ## reg_name
-+
-+/* NBIO */
-+#define NBIO_BASE_INNER(seg) \
-+	NBIF_BASE__INST0_SEG ## seg
-+
-+#define NBIO_BASE(seg) \
-+	NBIO_BASE_INNER(seg)
-+
-+#define NBIO_SR(reg_name)\
-+		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) +  \
-+					mm ## reg_name
-+
-+/* MMHUB */
-+#define MMHUB_BASE_INNER(seg) \
-+	MMHUB_BASE__INST0_SEG ## seg
-+
-+#define MMHUB_BASE(seg) \
-+	MMHUB_BASE_INNER(seg)
-+
-+#define MMHUB_SR(reg_name)\
-+		.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
-+					mm ## reg_name
-+
-+/* macros to expend register list macro defined in HW object header file
-+ * end *********************/
-+
-+
-+static const struct dce_dmcu_registers dmcu_regs = {
-+		DMCU_DCN10_REG_LIST()
-+};
-+
-+static const struct dce_dmcu_shift dmcu_shift = {
-+		DMCU_MASK_SH_LIST_DCN10(__SHIFT)
-+};
-+
-+static const struct dce_dmcu_mask dmcu_mask = {
-+		DMCU_MASK_SH_LIST_DCN10(_MASK)
-+};
-+
-+static const struct dce_abm_registers abm_regs = {
-+		ABM_DCN10_REG_LIST(0)
-+};
-+
-+static const struct dce_abm_shift abm_shift = {
-+		ABM_MASK_SH_LIST_DCN10(__SHIFT)
-+};
-+
-+static const struct dce_abm_mask abm_mask = {
-+		ABM_MASK_SH_LIST_DCN10(_MASK)
-+};
-+
-+#define stream_enc_regs(id)\
-+[id] = {\
-+	SE_DCN_REG_LIST(id),\
-+	.TMDS_CNTL = 0,\
-+	.AFMT_AVI_INFO0 = 0,\
-+	.AFMT_AVI_INFO1 = 0,\
-+	.AFMT_AVI_INFO2 = 0,\
-+	.AFMT_AVI_INFO3 = 0,\
-+}
-+
-+static const struct dce110_stream_enc_registers stream_enc_regs[] = {
-+	stream_enc_regs(0),
-+	stream_enc_regs(1),
-+	stream_enc_regs(2),
-+	stream_enc_regs(3),
-+};
-+
-+static const struct dce_stream_encoder_shift se_shift = {
-+		SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
-+};
-+
-+static const struct dce_stream_encoder_mask se_mask = {
-+		SE_COMMON_MASK_SH_LIST_DCN10(_MASK),
-+		.AFMT_GENERIC0_UPDATE = 0,
-+		.AFMT_GENERIC2_UPDATE = 0,
-+		.DP_DYN_RANGE = 0,
-+		.DP_YCBCR_RANGE = 0,
-+		.HDMI_AVI_INFO_SEND = 0,
-+		.HDMI_AVI_INFO_CONT = 0,
-+		.HDMI_AVI_INFO_LINE = 0,
-+		.DP_SEC_AVI_ENABLE = 0,
-+		.AFMT_AVI_INFO_VERSION = 0
-+};
-+
-+#define audio_regs(id)\
-+[id] = {\
-+		AUD_COMMON_REG_LIST(id)\
-+}
-+
-+static const struct dce_audio_registers audio_regs[] = {
-+	audio_regs(0),
-+	audio_regs(1),
-+	audio_regs(2),
-+	audio_regs(3),
-+};
-+
-+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
-+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
-+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
-+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
-+
-+static const struct dce_audio_shift audio_shift = {
-+		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct dce_aduio_mask audio_mask = {
-+		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
-+};
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	AUX_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
-+		aux_regs(0),
-+		aux_regs(1),
-+		aux_regs(2),
-+		aux_regs(3),
-+		aux_regs(4),
-+		aux_regs(5)
-+};
-+
-+#define hpd_regs(id)\
-+[id] = {\
-+	HPD_REG_LIST(id)\
-+}
-+
-+static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
-+		hpd_regs(0),
-+		hpd_regs(1),
-+		hpd_regs(2),
-+		hpd_regs(3),
-+		hpd_regs(4),
-+		hpd_regs(5)
-+};
-+
-+#define link_regs(id)\
-+[id] = {\
-+	LE_DCN10_REG_LIST(id), \
-+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
-+}
-+
-+static const struct dce110_link_enc_registers link_enc_regs[] = {
-+	link_regs(0),
-+	link_regs(1),
-+	link_regs(2),
-+	link_regs(3),
-+	link_regs(4),
-+	link_regs(5),
-+	link_regs(6),
-+};
-+
-+#define ipp_regs(id)\
-+[id] = {\
-+	IPP_REG_LIST_DCN10(id),\
-+}
-+
-+static const struct dcn10_ipp_registers ipp_regs[] = {
-+	ipp_regs(0),
-+	ipp_regs(1),
-+	ipp_regs(2),
-+	ipp_regs(3),
-+};
-+
-+static const struct dcn10_ipp_shift ipp_shift = {
-+		IPP_MASK_SH_LIST_DCN10(__SHIFT)
-+};
-+
-+static const struct dcn10_ipp_mask ipp_mask = {
-+		IPP_MASK_SH_LIST_DCN10(_MASK),
-+};
-+
-+#define opp_regs(id)\
-+[id] = {\
-+	OPP_REG_LIST_DCN10(id),\
-+}
-+
-+static const struct dcn10_opp_registers opp_regs[] = {
-+	opp_regs(0),
-+	opp_regs(1),
-+	opp_regs(2),
-+	opp_regs(3),
-+};
-+
-+static const struct dcn10_opp_shift opp_shift = {
-+		OPP_MASK_SH_LIST_DCN10(__SHIFT)
-+};
-+
-+static const struct dcn10_opp_mask opp_mask = {
-+		OPP_MASK_SH_LIST_DCN10(_MASK),
-+};
-+
-+#define tf_regs(id)\
-+[id] = {\
-+	TF_REG_LIST_DCN10(id),\
-+}
-+
-+static const struct dcn_dpp_registers tf_regs[] = {
-+	tf_regs(0),
-+	tf_regs(1),
-+	tf_regs(2),
-+	tf_regs(3),
-+};
-+
-+static const struct dcn_dpp_shift tf_shift = {
-+	TF_REG_LIST_SH_MASK_DCN10(__SHIFT)
-+};
-+
-+static const struct dcn_dpp_mask tf_mask = {
-+	TF_REG_LIST_SH_MASK_DCN10(_MASK),
-+};
-+
-+static const struct dcn_mpc_registers mpc_regs = {
-+		MPC_COMMON_REG_LIST_DCN1_0(0),
-+		MPC_COMMON_REG_LIST_DCN1_0(1),
-+		MPC_COMMON_REG_LIST_DCN1_0(2),
-+		MPC_COMMON_REG_LIST_DCN1_0(3),
-+		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
-+		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
-+		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
-+		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
-+};
-+
-+static const struct dcn_mpc_shift mpc_shift = {
-+	MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
-+};
-+
-+static const struct dcn_mpc_mask mpc_mask = {
-+	MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),
-+};
-+
-+#define tg_regs(id)\
-+[id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
-+
-+static const struct dcn_tg_registers tg_regs[] = {
-+	tg_regs(0),
-+	tg_regs(1),
-+	tg_regs(2),
-+	tg_regs(3),
-+};
-+
-+static const struct dcn_tg_shift tg_shift = {
-+	TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
-+};
-+
-+static const struct dcn_tg_mask tg_mask = {
-+	TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
-+};
-+
-+
-+static const struct bios_registers bios_regs = {
-+		NBIO_SR(BIOS_SCRATCH_6)
-+};
-+
-+#define hubp_regs(id)\
-+[id] = {\
-+	HUBP_REG_LIST_DCN10(id)\
-+}
-+
-+
-+static const struct dcn_mi_registers hubp_regs[] = {
-+	hubp_regs(0),
-+	hubp_regs(1),
-+	hubp_regs(2),
-+	hubp_regs(3),
-+};
-+
-+static const struct dcn_mi_shift hubp_shift = {
-+		HUBP_MASK_SH_LIST_DCN10(__SHIFT)
-+};
-+
-+static const struct dcn_mi_mask hubp_mask = {
-+		HUBP_MASK_SH_LIST_DCN10(_MASK)
-+};
-+
-+
-+static const struct dcn_hubbub_registers hubbub_reg = {
-+		HUBBUB_REG_LIST_DCN10(0)
-+};
-+
-+static const struct dcn_hubbub_shift hubbub_shift = {
-+		HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
-+};
-+
-+static const struct dcn_hubbub_mask hubbub_mask = {
-+		HUBBUB_MASK_SH_LIST_DCN10(_MASK)
-+};
-+
-+#define clk_src_regs(index, pllid)\
-+[index] = {\
-+	CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
-+}
-+
-+static const struct dce110_clk_src_regs clk_src_regs[] = {
-+	clk_src_regs(0, A),
-+	clk_src_regs(1, B),
-+	clk_src_regs(2, C),
-+	clk_src_regs(3, D)
-+};
-+
-+static const struct dce110_clk_src_shift cs_shift = {
-+		CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
-+};
-+
-+static const struct dce110_clk_src_mask cs_mask = {
-+		CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
-+};
-+
-+
-+static const struct resource_caps res_cap = {
-+		.num_timing_generator = 4,
-+		.num_video_plane = 4,
-+		.num_audio = 4,
-+		.num_stream_encoder = 4,
-+		.num_pll = 4,
-+};
-+
-+static const struct dc_debug debug_defaults_drv = {
-+		.sanity_checks = true,
-+		.disable_dmcu = true,
-+		.force_abm_enable = false,
-+		.timing_trace = false,
-+		.clock_trace = true,
-+
-+		.min_disp_clk_khz = 300000,
-+
-+		.disable_pplib_clock_request = true,
-+		.disable_pplib_wm_range = false,
-+		.pplib_wm_report_mode = WM_REPORT_DEFAULT,
-+		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
-+		.force_single_disp_pipe_split = true,
-+		.disable_dcc = DCC_ENABLE,
-+		.voltage_align_fclk = true,
-+		.disable_stereo_support = true,
-+		.vsr_support = true,
-+		.performance_trace = false,
-+};
-+
-+static const struct dc_debug debug_defaults_diags = {
-+		.disable_dmcu = true,
-+		.force_abm_enable = false,
-+		.timing_trace = true,
-+		.clock_trace = true,
-+		.disable_stutter = true,
-+		.disable_pplib_clock_request = true,
-+		.disable_pplib_wm_range = true
-+};
-+
-+static void dcn10_dpp_destroy(struct dpp **dpp)
-+{
-+	kfree(TO_DCN10_DPP(*dpp));
-+	*dpp = NULL;
-+}
-+
-+static struct dpp *dcn10_dpp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dcn10_dpp *dpp =
-+		kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL);
-+
-+	if (!dpp)
-+		return NULL;
-+
-+	dpp1_construct(dpp, ctx, inst,
-+		       &tf_regs[inst], &tf_shift, &tf_mask);
-+	return &dpp->base;
-+}
-+
-+static struct input_pixel_processor *dcn10_ipp_create(
-+	struct dc_context *ctx, uint32_t inst)
-+{
-+	struct dcn10_ipp *ipp =
-+		kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
-+
-+	if (!ipp) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dcn10_ipp_construct(ipp, ctx, inst,
-+			&ipp_regs[inst], &ipp_shift, &ipp_mask);
-+	return &ipp->base;
-+}
-+
-+
-+static struct output_pixel_processor *dcn10_opp_create(
-+	struct dc_context *ctx, uint32_t inst)
-+{
-+	struct dcn10_opp *opp =
-+		kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL);
-+
-+	if (!opp) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dcn10_opp_construct(opp, ctx, inst,
-+			&opp_regs[inst], &opp_shift, &opp_mask);
-+	return &opp->base;
-+}
-+
-+static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
-+{
-+	struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
-+					  GFP_KERNEL);
-+
-+	if (!mpc10)
-+		return NULL;
-+
-+	dcn10_mpc_construct(mpc10, ctx,
-+			&mpc_regs,
-+			&mpc_shift,
-+			&mpc_mask,
-+			4);
-+
-+	return &mpc10->base;
-+}
-+
-+static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
-+{
-+	struct hubbub *hubbub = kzalloc(sizeof(struct hubbub),
-+					  GFP_KERNEL);
-+
-+	if (!hubbub)
-+		return NULL;
-+
-+	hubbub1_construct(hubbub, ctx,
-+			&hubbub_reg,
-+			&hubbub_shift,
-+			&hubbub_mask);
-+
-+	return hubbub;
-+}
-+
-+static struct timing_generator *dcn10_timing_generator_create(
-+		struct dc_context *ctx,
-+		uint32_t instance)
-+{
-+	struct dcn10_timing_generator *tgn10 =
-+		kzalloc(sizeof(struct dcn10_timing_generator), GFP_KERNEL);
-+
-+	if (!tgn10)
-+		return NULL;
-+
-+	tgn10->base.inst = instance;
-+	tgn10->base.ctx = ctx;
-+
-+	tgn10->tg_regs = &tg_regs[instance];
-+	tgn10->tg_shift = &tg_shift;
-+	tgn10->tg_mask = &tg_mask;
-+
-+	dcn10_timing_generator_init(tgn10);
-+
-+	return &tgn10->base;
-+}
-+
-+static const struct encoder_feature_support link_enc_feature = {
-+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
-+		.max_hdmi_pixel_clock = 600000,
-+		.ycbcr420_supported = true,
-+		.flags.bits.IS_HBR2_CAPABLE = true,
-+		.flags.bits.IS_HBR3_CAPABLE = true,
-+		.flags.bits.IS_TPS3_CAPABLE = true,
-+		.flags.bits.IS_TPS4_CAPABLE = true,
-+		.flags.bits.IS_YCBCR_CAPABLE = true
-+};
-+
-+struct link_encoder *dcn10_link_encoder_create(
-+	const struct encoder_init_data *enc_init_data)
-+{
-+	struct dce110_link_encoder *enc110 =
-+		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	dce110_link_encoder_construct(enc110,
-+				      enc_init_data,
-+				      &link_enc_feature,
-+				      &link_enc_regs[enc_init_data->transmitter],
-+				      &link_enc_aux_regs[enc_init_data->channel - 1],
-+				      &link_enc_hpd_regs[enc_init_data->hpd_source]);
-+
-+	return &enc110->base;
-+}
-+
-+struct clock_source *dcn10_clock_source_create(
-+	struct dc_context *ctx,
-+	struct dc_bios *bios,
-+	enum clock_source_id id,
-+	const struct dce110_clk_src_regs *regs,
-+	bool dp_clk_src)
-+{
-+	struct dce110_clk_src *clk_src =
-+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
-+
-+	if (!clk_src)
-+		return NULL;
-+
-+	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
-+			regs, &cs_shift, &cs_mask)) {
-+		clk_src->base.dp_clk_src = dp_clk_src;
-+		return &clk_src->base;
-+	}
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
-+
-+static void read_dce_straps(
-+	struct dc_context *ctx,
-+	struct resource_straps *straps)
-+{
-+	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
-+		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
-+}
-+
-+static struct audio *create_audio(
-+		struct dc_context *ctx, unsigned int inst)
-+{
-+	return dce_audio_create(ctx, inst,
-+			&audio_regs[inst], &audio_shift, &audio_mask);
-+}
-+
-+static struct stream_encoder *dcn10_stream_encoder_create(
-+	enum engine_id eng_id,
-+	struct dc_context *ctx)
-+{
-+	struct dce110_stream_encoder *enc110 =
-+		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
-+
-+	if (!enc110)
-+		return NULL;
-+
-+	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
-+					&stream_enc_regs[eng_id],
-+					&se_shift, &se_mask);
-+	return &enc110->base;
-+}
-+
-+static const struct dce_hwseq_registers hwseq_reg = {
-+		HWSEQ_DCN1_REG_LIST()
-+};
-+
-+static const struct dce_hwseq_shift hwseq_shift = {
-+		HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct dce_hwseq_mask hwseq_mask = {
-+		HWSEQ_DCN1_MASK_SH_LIST(_MASK)
-+};
-+
-+static struct dce_hwseq *dcn10_hwseq_create(
-+	struct dc_context *ctx)
-+{
-+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
-+
-+	if (hws) {
-+		hws->ctx = ctx;
-+		hws->regs = &hwseq_reg;
-+		hws->shifts = &hwseq_shift;
-+		hws->masks = &hwseq_mask;
-+		hws->wa.DEGVIDCN10_253 = true;
-+	}
-+	return hws;
-+}
-+
-+static const struct resource_create_funcs res_create_funcs = {
-+	.read_dce_straps = read_dce_straps,
-+	.create_audio = create_audio,
-+	.create_stream_encoder = dcn10_stream_encoder_create,
-+	.create_hwseq = dcn10_hwseq_create,
-+};
-+
-+static const struct resource_create_funcs res_create_maximus_funcs = {
-+	.read_dce_straps = NULL,
-+	.create_audio = NULL,
-+	.create_stream_encoder = NULL,
-+	.create_hwseq = dcn10_hwseq_create,
-+};
-+
-+void dcn10_clock_source_destroy(struct clock_source **clk_src)
-+{
-+	kfree(TO_DCE110_CLK_SRC(*clk_src));
-+	*clk_src = NULL;
-+}
-+
-+static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx)
-+{
-+	struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
-+
-+	if (!pp_smu)
-+		return pp_smu;
-+
-+	dm_pp_get_funcs_rv(ctx, pp_smu);
-+	return pp_smu;
-+}
-+
-+static void destruct(struct dcn10_resource_pool *pool)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < pool->base.stream_enc_count; i++) {
-+		if (pool->base.stream_enc[i] != NULL) {
-+			/* TODO: free dcn version of stream encoder once implemented
-+			 * rather than using virtual stream encoder
-+			 */
-+			kfree(pool->base.stream_enc[i]);
-+			pool->base.stream_enc[i] = NULL;
-+		}
-+	}
-+
-+	if (pool->base.mpc != NULL) {
-+		kfree(TO_DCN10_MPC(pool->base.mpc));
-+		pool->base.mpc = NULL;
-+	}
-+
-+	if (pool->base.hubbub != NULL) {
-+		kfree(pool->base.hubbub);
-+		pool->base.hubbub = NULL;
-+	}
-+
-+	for (i = 0; i < pool->base.pipe_count; i++) {
-+		if (pool->base.opps[i] != NULL)
-+			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
-+
-+		if (pool->base.dpps[i] != NULL)
-+			dcn10_dpp_destroy(&pool->base.dpps[i]);
-+
-+		if (pool->base.ipps[i] != NULL)
-+			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
-+
-+		if (pool->base.hubps[i] != NULL) {
-+			kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
-+			pool->base.hubps[i] = NULL;
-+		}
-+
-+		if (pool->base.irqs != NULL) {
-+			dal_irq_service_destroy(&pool->base.irqs);
-+		}
-+
-+		if (pool->base.timing_generators[i] != NULL)	{
-+			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
-+			pool->base.timing_generators[i] = NULL;
-+		}
-+	}
-+
-+	for (i = 0; i < pool->base.stream_enc_count; i++)
-+		kfree(pool->base.stream_enc[i]);
-+
-+	for (i = 0; i < pool->base.audio_count; i++) {
-+		if (pool->base.audios[i])
-+			dce_aud_destroy(&pool->base.audios[i]);
-+	}
-+
-+	for (i = 0; i < pool->base.clk_src_count; i++) {
-+		if (pool->base.clock_sources[i] != NULL) {
-+			dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
-+			pool->base.clock_sources[i] = NULL;
-+		}
-+	}
-+
-+	if (pool->base.dp_clock_source != NULL) {
-+		dcn10_clock_source_destroy(&pool->base.dp_clock_source);
-+		pool->base.dp_clock_source = NULL;
-+	}
-+
-+	if (pool->base.abm != NULL)
-+		dce_abm_destroy(&pool->base.abm);
-+
-+	if (pool->base.dmcu != NULL)
-+		dce_dmcu_destroy(&pool->base.dmcu);
-+
-+	if (pool->base.display_clock != NULL)
-+		dce_disp_clk_destroy(&pool->base.display_clock);
-+
-+	kfree(pool->base.pp_smu);
-+}
-+
-+static struct hubp *dcn10_hubp_create(
-+	struct dc_context *ctx,
-+	uint32_t inst)
-+{
-+	struct dcn10_hubp *hubp1 =
-+		kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL);
-+
-+	if (!hubp1)
-+		return NULL;
-+
-+	dcn10_hubp_construct(hubp1, ctx, inst,
-+			     &hubp_regs[inst], &hubp_shift, &hubp_mask);
-+	return &hubp1->base;
-+}
-+
-+static void get_pixel_clock_parameters(
-+	const struct pipe_ctx *pipe_ctx,
-+	struct pixel_clk_params *pixel_clk_params)
-+{
-+	const struct dc_stream_state *stream = pipe_ctx->stream;
-+	pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
-+	pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
-+	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
-+	pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
-+	/* TODO: un-hardcode*/
-+	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
-+		LINK_RATE_REF_FREQ_IN_KHZ;
-+	pixel_clk_params->flags.ENABLE_SS = 0;
-+	pixel_clk_params->color_depth =
-+		stream->timing.display_color_depth;
-+	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
-+	pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
-+
-+	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
-+		pixel_clk_params->color_depth = COLOR_DEPTH_888;
-+
-+	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
-+		pixel_clk_params->requested_pix_clk  /= 2;
-+
-+}
-+
-+static void build_clamping_params(struct dc_stream_state *stream)
-+{
-+	stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
-+	stream->clamping.c_depth = stream->timing.display_color_depth;
-+	stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
-+}
-+
-+static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
-+{
-+
-+	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
-+
-+	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
-+		pipe_ctx->clock_source,
-+		&pipe_ctx->stream_res.pix_clk_params,
-+		&pipe_ctx->pll_settings);
-+
-+	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
-+
-+	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
-+					&pipe_ctx->stream->bit_depth_params);
-+	build_clamping_params(pipe_ctx->stream);
-+}
-+
-+static enum dc_status build_mapped_resource(
-+		const struct dc *dc,
-+		struct dc_state *context,
-+		struct dc_stream_state *stream)
-+{
-+	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
-+
-+	/*TODO Seems unneeded anymore */
-+	/*	if (old_context && resource_is_stream_unchanged(old_context, stream)) {
-+			if (stream != NULL && old_context->streams[i] != NULL) {
-+				 todo: shouldn't have to copy missing parameter here
-+				resource_build_bit_depth_reduction_params(stream,
-+						&stream->bit_depth_params);
-+				stream->clamping.pixel_encoding =
-+						stream->timing.pixel_encoding;
-+
-+				resource_build_bit_depth_reduction_params(stream,
-+								&stream->bit_depth_params);
-+				build_clamping_params(stream);
-+
-+				continue;
-+			}
-+		}
-+	*/
-+
-+	if (!pipe_ctx)
-+		return DC_ERROR_UNEXPECTED;
-+
-+	build_pipe_hw_param(pipe_ctx);
-+	return DC_OK;
-+}
-+
-+enum dc_status dcn10_add_stream_to_ctx(
-+		struct dc *dc,
-+		struct dc_state *new_ctx,
-+		struct dc_stream_state *dc_stream)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+
-+	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
-+
-+	if (result == DC_OK)
-+		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
-+
-+
-+	if (result == DC_OK)
-+		result = build_mapped_resource(dc, new_ctx, dc_stream);
-+
-+	return result;
-+}
-+
-+enum dc_status dcn10_validate_guaranteed(
-+		struct dc *dc,
-+		struct dc_stream_state *dc_stream,
-+		struct dc_state *context)
-+{
-+	enum dc_status result = DC_ERROR_UNEXPECTED;
-+
-+	context->streams[0] = dc_stream;
-+	dc_stream_retain(context->streams[0]);
-+	context->stream_count++;
-+
-+	result = resource_map_pool_resources(dc, context, dc_stream);
-+
-+	if (result == DC_OK)
-+		result = resource_map_phy_clock_resources(dc, context, dc_stream);
-+
-+	if (result == DC_OK)
-+		result = build_mapped_resource(dc, context, dc_stream);
-+
-+	if (result == DC_OK) {
-+		validate_guaranteed_copy_streams(
-+				context, dc->caps.max_streams);
-+		result = resource_build_scaling_params_for_context(dc, context);
-+	}
-+	if (result == DC_OK && !dcn_validate_bandwidth(dc, context))
-+		return DC_FAIL_BANDWIDTH_VALIDATE;
-+
-+	return result;
-+}
-+
-+static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
-+		struct dc_state *context,
-+		const struct resource_pool *pool,
-+		struct dc_stream_state *stream)
-+{
-+	struct resource_context *res_ctx = &context->res_ctx;
-+	struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
-+	struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool);
-+
-+	if (!head_pipe)
-+		ASSERT(0);
-+
-+	if (!idle_pipe)
-+		return false;
-+
-+	idle_pipe->stream = head_pipe->stream;
-+	idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
-+	idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
-+
-+	idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
-+	idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
-+	idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
-+
-+	return idle_pipe;
-+}
-+
-+enum dcc_control {
-+	dcc_control__256_256_xxx,
-+	dcc_control__128_128_xxx,
-+	dcc_control__256_64_64,
-+};
-+
-+enum segment_order {
-+	segment_order__na,
-+	segment_order__contiguous,
-+	segment_order__non_contiguous,
-+};
-+
-+static bool dcc_support_pixel_format(
-+		enum surface_pixel_format format,
-+		unsigned int *bytes_per_element)
-+{
-+	/* DML: get_bytes_per_element */
-+	switch (format) {
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
-+	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
-+		*bytes_per_element = 2;
-+		return true;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-+		*bytes_per_element = 4;
-+		return true;
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
-+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-+		*bytes_per_element = 8;
-+		return true;
-+	default:
-+		return false;
-+	}
-+}
-+
-+static bool dcc_support_swizzle(
-+		enum swizzle_mode_values swizzle,
-+		unsigned int bytes_per_element,
-+		enum segment_order *segment_order_horz,
-+		enum segment_order *segment_order_vert)
-+{
-+	bool standard_swizzle = false;
-+	bool display_swizzle = false;
-+
-+	switch (swizzle) {
-+	case DC_SW_4KB_S:
-+	case DC_SW_64KB_S:
-+	case DC_SW_VAR_S:
-+	case DC_SW_4KB_S_X:
-+	case DC_SW_64KB_S_X:
-+	case DC_SW_VAR_S_X:
-+		standard_swizzle = true;
-+		break;
-+	case DC_SW_4KB_D:
-+	case DC_SW_64KB_D:
-+	case DC_SW_VAR_D:
-+	case DC_SW_4KB_D_X:
-+	case DC_SW_64KB_D_X:
-+	case DC_SW_VAR_D_X:
-+		display_swizzle = true;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	if (bytes_per_element == 1 && standard_swizzle) {
-+		*segment_order_horz = segment_order__contiguous;
-+		*segment_order_vert = segment_order__na;
-+		return true;
-+	}
-+	if (bytes_per_element == 2 && standard_swizzle) {
-+		*segment_order_horz = segment_order__non_contiguous;
-+		*segment_order_vert = segment_order__contiguous;
-+		return true;
-+	}
-+	if (bytes_per_element == 4 && standard_swizzle) {
-+		*segment_order_horz = segment_order__non_contiguous;
-+		*segment_order_vert = segment_order__contiguous;
-+		return true;
-+	}
-+	if (bytes_per_element == 8 && standard_swizzle) {
-+		*segment_order_horz = segment_order__na;
-+		*segment_order_vert = segment_order__contiguous;
-+		return true;
-+	}
-+	if (bytes_per_element == 8 && display_swizzle) {
-+		*segment_order_horz = segment_order__contiguous;
-+		*segment_order_vert = segment_order__non_contiguous;
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+static void get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
-+		unsigned int bytes_per_element)
-+{
-+	/* copied from DML.  might want to refactor DML to leverage from DML */
-+	/* DML : get_blk256_size */
-+	if (bytes_per_element == 1) {
-+		*blk256_width = 16;
-+		*blk256_height = 16;
-+	} else if (bytes_per_element == 2) {
-+		*blk256_width = 16;
-+		*blk256_height = 8;
-+	} else if (bytes_per_element == 4) {
-+		*blk256_width = 8;
-+		*blk256_height = 8;
-+	} else if (bytes_per_element == 8) {
-+		*blk256_width = 8;
-+		*blk256_height = 4;
-+	}
-+}
-+
-+static void det_request_size(
-+		unsigned int height,
-+		unsigned int width,
-+		unsigned int bpe,
-+		bool *req128_horz_wc,
-+		bool *req128_vert_wc)
-+{
-+	unsigned int detile_buf_size = 164 * 1024;  /* 164KB for DCN1.0 */
-+
-+	unsigned int blk256_height = 0;
-+	unsigned int blk256_width = 0;
-+	unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
-+
-+	get_blk256_size(&blk256_width, &blk256_height, bpe);
-+
-+	swath_bytes_horz_wc = height * blk256_height * bpe;
-+	swath_bytes_vert_wc = width * blk256_width * bpe;
-+
-+	*req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
-+			false : /* full 256B request */
-+			true; /* half 128b request */
-+
-+	*req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
-+			false : /* full 256B request */
-+			true; /* half 128b request */
-+}
-+
-+static bool get_dcc_compression_cap(const struct dc *dc,
-+		const struct dc_dcc_surface_param *input,
-+		struct dc_surface_dcc_cap *output)
-+{
-+	/* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
-+	enum dcc_control dcc_control;
-+	unsigned int bpe;
-+	enum segment_order segment_order_horz, segment_order_vert;
-+	bool req128_horz_wc, req128_vert_wc;
-+
-+	memset(output, 0, sizeof(*output));
-+
-+	if (dc->debug.disable_dcc == DCC_DISABLE)
-+		return false;
-+
-+	if (!dcc_support_pixel_format(input->format,
-+			&bpe))
-+		return false;
-+
-+	if (!dcc_support_swizzle(input->swizzle_mode, bpe,
-+			&segment_order_horz, &segment_order_vert))
-+		return false;
-+
-+	det_request_size(input->surface_size.height,  input->surface_size.width,
-+			bpe, &req128_horz_wc, &req128_vert_wc);
-+
-+	if (!req128_horz_wc && !req128_vert_wc) {
-+		dcc_control = dcc_control__256_256_xxx;
-+	} else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
-+		if (!req128_horz_wc)
-+			dcc_control = dcc_control__256_256_xxx;
-+		else if (segment_order_horz == segment_order__contiguous)
-+			dcc_control = dcc_control__128_128_xxx;
-+		else
-+			dcc_control = dcc_control__256_64_64;
-+	} else if (input->scan == SCAN_DIRECTION_VERTICAL) {
-+		if (!req128_vert_wc)
-+			dcc_control = dcc_control__256_256_xxx;
-+		else if (segment_order_vert == segment_order__contiguous)
-+			dcc_control = dcc_control__128_128_xxx;
-+		else
-+			dcc_control = dcc_control__256_64_64;
-+	} else {
-+		if ((req128_horz_wc &&
-+			segment_order_horz == segment_order__non_contiguous) ||
-+			(req128_vert_wc &&
-+			segment_order_vert == segment_order__non_contiguous))
-+			/* access_dir not known, must use most constraining */
-+			dcc_control = dcc_control__256_64_64;
-+		else
-+			/* reg128 is true for either horz and vert
-+			 * but segment_order is contiguous
-+			 */
-+			dcc_control = dcc_control__128_128_xxx;
-+	}
-+
-+	if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
-+		dcc_control != dcc_control__256_256_xxx)
-+		return false;
-+
-+	switch (dcc_control) {
-+	case dcc_control__256_256_xxx:
-+		output->grph.rgb.max_uncompressed_blk_size = 256;
-+		output->grph.rgb.max_compressed_blk_size = 256;
-+		output->grph.rgb.independent_64b_blks = false;
-+		break;
-+	case dcc_control__128_128_xxx:
-+		output->grph.rgb.max_uncompressed_blk_size = 128;
-+		output->grph.rgb.max_compressed_blk_size = 128;
-+		output->grph.rgb.independent_64b_blks = false;
-+		break;
-+	case dcc_control__256_64_64:
-+		output->grph.rgb.max_uncompressed_blk_size = 256;
-+		output->grph.rgb.max_compressed_blk_size = 64;
-+		output->grph.rgb.independent_64b_blks = true;
-+		break;
-+	}
-+
-+	output->capable = true;
-+	output->const_color_support = false;
-+
-+	return true;
-+}
-+
-+
-+static void dcn10_destroy_resource_pool(struct resource_pool **pool)
-+{
-+	struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
-+
-+	destruct(dcn10_pool);
-+	kfree(dcn10_pool);
-+	*pool = NULL;
-+}
-+
-+static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
-+{
-+	if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
-+			&& caps->max_video_width != 0
-+			&& plane_state->src_rect.width > caps->max_video_width)
-+		return DC_FAIL_SURFACE_VALIDATE;
-+
-+	return DC_OK;
-+}
-+
-+static struct dc_cap_funcs cap_funcs = {
-+	.get_dcc_compression_cap = get_dcc_compression_cap
-+};
-+
-+static struct resource_funcs dcn10_res_pool_funcs = {
-+	.destroy = dcn10_destroy_resource_pool,
-+	.link_enc_create = dcn10_link_encoder_create,
-+	.validate_guaranteed = dcn10_validate_guaranteed,
-+	.validate_bandwidth = dcn_validate_bandwidth,
-+	.acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
-+	.validate_plane = dcn10_validate_plane,
-+	.add_stream_to_ctx = dcn10_add_stream_to_ctx
-+};
-+
-+static uint32_t read_pipe_fuses(struct dc_context *ctx)
-+{
-+	uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
-+	/* RV1 support max 4 pipes */
-+	value = value & 0xf;
-+	return value;
-+}
-+
-+static bool construct(
-+	uint8_t num_virtual_links,
-+	struct dc *dc,
-+	struct dcn10_resource_pool *pool)
-+{
-+	int i;
-+	int j;
-+	struct dc_context *ctx = dc->ctx;
-+	uint32_t pipe_fuses = read_pipe_fuses(ctx);
-+
-+	ctx->dc_bios->regs = &bios_regs;
-+
-+	pool->base.res_cap = &res_cap;
-+	pool->base.funcs = &dcn10_res_pool_funcs;
-+
-+	/*
-+	 * TODO fill in from actual raven resource when we create
-+	 * more than virtual encoder
-+	 */
-+
-+	/*************************************************
-+	 *  Resource + asic cap harcoding                *
-+	 *************************************************/
-+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
-+
-+	/* max pipe num for ASIC before check pipe fuses */
-+	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
-+
-+	dc->caps.max_video_width = 3840;
-+	dc->caps.max_downscale_ratio = 200;
-+	dc->caps.i2c_speed_in_khz = 100;
-+	dc->caps.max_cursor_size = 256;
-+	dc->caps.max_slave_planes = 1;
-+	dc->caps.is_apu = true;
-+
-+	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
-+		dc->debug = debug_defaults_drv;
-+	else
-+		dc->debug = debug_defaults_diags;
-+
-+	/*************************************************
-+	 *  Create resources                             *
-+	 *************************************************/
-+
-+	pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
-+			dcn10_clock_source_create(ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL0,
-+				&clk_src_regs[0], false);
-+	pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
-+			dcn10_clock_source_create(ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL1,
-+				&clk_src_regs[1], false);
-+	pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
-+			dcn10_clock_source_create(ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL2,
-+				&clk_src_regs[2], false);
-+	pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
-+			dcn10_clock_source_create(ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_COMBO_PHY_PLL3,
-+				&clk_src_regs[3], false);
-+
-+	pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
-+
-+	pool->base.dp_clock_source =
-+			dcn10_clock_source_create(ctx, ctx->dc_bios,
-+				CLOCK_SOURCE_ID_DP_DTO,
-+				/* todo: not reuse phy_pll registers */
-+				&clk_src_regs[0], true);
-+
-+	for (i = 0; i < pool->base.clk_src_count; i++) {
-+		if (pool->base.clock_sources[i] == NULL) {
-+			dm_error("DC: failed to create clock sources!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto fail;
-+		}
-+	}
-+
-+	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
-+		pool->base.display_clock = dce120_disp_clk_create(ctx);
-+		if (pool->base.display_clock == NULL) {
-+			dm_error("DC: failed to create display clock!\n");
-+			BREAK_TO_DEBUGGER();
-+			goto fail;
-+		}
-+	}
-+
-+	pool->base.dmcu = dcn10_dmcu_create(ctx,
-+			&dmcu_regs,
-+			&dmcu_shift,
-+			&dmcu_mask);
-+	if (pool->base.dmcu == NULL) {
-+		dm_error("DC: failed to create dmcu!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto fail;
-+	}
-+
-+	pool->base.abm = dce_abm_create(ctx,
-+			&abm_regs,
-+			&abm_shift,
-+			&abm_mask);
-+	if (pool->base.abm == NULL) {
-+		dm_error("DC: failed to create abm!\n");
-+		BREAK_TO_DEBUGGER();
-+		goto fail;
-+	}
-+
-+	dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1);
-+	memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
-+	memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
-+
-+	if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
-+		dc->dcn_soc->urgent_latency = 3;
-+		dc->debug.disable_dmcu = true;
-+		dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
-+	}
-+
-+
-+	dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
-+	ASSERT(dc->dcn_soc->number_of_channels < 3);
-+	if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
-+		dc->dcn_soc->number_of_channels = 2;
-+
-+	if (dc->dcn_soc->number_of_channels == 1) {
-+		dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
-+		dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
-+		dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
-+		dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
-+		if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
-+			dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
-+		}
-+	}
-+
-+	pool->base.pp_smu = dcn10_pp_smu_create(ctx);
-+
-+	if (!dc->debug.disable_pplib_clock_request)
-+		dcn_bw_update_from_pplib(dc);
-+	dcn_bw_sync_calcs_and_dml(dc);
-+	if (!dc->debug.disable_pplib_wm_range) {
-+		dc->res_pool = &pool->base;
-+		dcn_bw_notify_pplib_of_wm_ranges(dc);
-+	}
-+
-+	{
-+		struct irq_service_init_data init_data;
-+		init_data.ctx = dc->ctx;
-+		pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
-+		if (!pool->base.irqs)
-+			goto fail;
-+	}
-+
-+	/* index to valid pipe resource  */
-+	j = 0;
-+	/* mem input -> ipp -> dpp -> opp -> TG */
-+	for (i = 0; i < pool->base.pipe_count; i++) {
-+		/* if pipe is disabled, skip instance of HW pipe,
-+		 * i.e, skip ASIC register instance
-+		 */
-+		if ((pipe_fuses & (1 << i)) != 0)
-+			continue;
-+
-+		pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
-+		if (pool->base.hubps[j] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create memory input!\n");
-+			goto fail;
-+		}
-+
-+		pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
-+		if (pool->base.ipps[j] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create input pixel processor!\n");
-+			goto fail;
-+		}
-+
-+		pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
-+		if (pool->base.dpps[j] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create dpp!\n");
-+			goto fail;
-+		}
-+
-+		pool->base.opps[j] = dcn10_opp_create(ctx, i);
-+		if (pool->base.opps[j] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error(
-+				"DC: failed to create output pixel processor!\n");
-+			goto fail;
-+		}
-+
-+		pool->base.timing_generators[j] = dcn10_timing_generator_create(
-+				ctx, i);
-+		if (pool->base.timing_generators[j] == NULL) {
-+			BREAK_TO_DEBUGGER();
-+			dm_error("DC: failed to create tg!\n");
-+			goto fail;
-+		}
-+
-+		/* check next valid pipe */
-+		j++;
-+	}
-+
-+	/* valid pipe num */
-+	pool->base.pipe_count = j;
-+
-+	/* within dml lib, it is hard code to 4. If ASIC pipe is fused,
-+	 * the value may be changed
-+	 */
-+	dc->dml.ip.max_num_dpp = pool->base.pipe_count;
-+	dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
-+
-+	pool->base.mpc = dcn10_mpc_create(ctx);
-+	if (pool->base.mpc == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		dm_error("DC: failed to create mpc!\n");
-+		goto fail;
-+	}
-+
-+	pool->base.hubbub = dcn10_hubbub_create(ctx);
-+	if (pool->base.hubbub == NULL) {
-+		BREAK_TO_DEBUGGER();
-+		dm_error("DC: failed to create hubbub!\n");
-+		goto fail;
-+	}
-+
-+	if (!resource_construct(num_virtual_links, dc, &pool->base,
-+			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
-+			&res_create_funcs : &res_create_maximus_funcs)))
-+			goto fail;
-+
-+	dcn10_hw_sequencer_construct(dc);
-+	dc->caps.max_planes =  pool->base.pipe_count;
-+
-+	dc->cap_funcs = cap_funcs;
-+
-+	return true;
-+
-+fail:
-+
-+	destruct(pool);
-+
-+	return false;
-+}
-+
-+struct resource_pool *dcn10_create_resource_pool(
-+		uint8_t num_virtual_links,
-+		struct dc *dc)
-+{
-+	struct dcn10_resource_pool *pool =
-+		kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL);
-+
-+	if (!pool)
-+		return NULL;
-+
-+	if (construct(num_virtual_links, dc, pool))
-+		return &pool->base;
-+
-+	BREAK_TO_DEBUGGER();
-+	return NULL;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h.0130~	2017-12-14 06:39:58.423903573 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h	2017-12-14 06:39:58.423903573 +0100
-@@ -0,0 +1,47 @@
-+/*
-+* Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_RESOURCE_DCN10_H__
-+#define __DC_RESOURCE_DCN10_H__
-+
-+#include "core_types.h"
-+
-+#define TO_DCN10_RES_POOL(pool)\
-+	container_of(pool, struct dcn10_resource_pool, base)
-+
-+struct dc;
-+struct resource_pool;
-+struct _vcs_dpi_display_pipe_params_st;
-+
-+struct dcn10_resource_pool {
-+	struct resource_pool base;
-+};
-+struct resource_pool *dcn10_create_resource_pool(
-+		uint8_t num_virtual_links,
-+		struct dc *dc);
-+
-+
-+#endif /* __DC_RESOURCE_DCN10_H__ */
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c.0130~	2017-12-14 06:39:58.424903574 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c	2017-12-14 06:39:58.424903574 +0100
-@@ -0,0 +1,1266 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "reg_helper.h"
-+#include "dcn10_timing_generator.h"
-+#include "dc.h"
-+
-+#define REG(reg)\
-+	tgn10->tg_regs->reg
-+
-+#define CTX \
-+	tgn10->base.ctx
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	tgn10->tg_shift->field_name, tgn10->tg_mask->field_name
-+
-+#define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
-+
-+/**
-+* apply_front_porch_workaround  TODO FPGA still need?
-+*
-+* This is a workaround for a bug that has existed since R5xx and has not been
-+* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
-+*/
-+static void tgn10_apply_front_porch_workaround(
-+	struct timing_generator *tg,
-+	struct dc_crtc_timing *timing)
-+{
-+	if (timing->flags.INTERLACE == 1) {
-+		if (timing->v_front_porch < 2)
-+			timing->v_front_porch = 2;
-+	} else {
-+		if (timing->v_front_porch < 1)
-+			timing->v_front_porch = 1;
-+	}
-+}
-+
-+static void tgn10_program_global_sync(
-+		struct timing_generator *tg)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	if (tg->dlg_otg_param.vstartup_start == 0) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	REG_SET(OTG_VSTARTUP_PARAM, 0,
-+		VSTARTUP_START, tg->dlg_otg_param.vstartup_start);
-+
-+	REG_SET_2(OTG_VUPDATE_PARAM, 0,
-+			VUPDATE_OFFSET, tg->dlg_otg_param.vupdate_offset,
-+			VUPDATE_WIDTH, tg->dlg_otg_param.vupdate_width);
-+
-+	REG_SET(OTG_VREADY_PARAM, 0,
-+			VREADY_OFFSET, tg->dlg_otg_param.vready_offset);
-+}
-+
-+static void tgn10_disable_stereo(struct timing_generator *tg)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	REG_SET(OTG_STEREO_CONTROL, 0,
-+		OTG_STEREO_EN, 0);
-+
-+	REG_SET_3(OTG_3D_STRUCTURE_CONTROL, 0,
-+		OTG_3D_STRUCTURE_EN, 0,
-+		OTG_3D_STRUCTURE_V_UPDATE_MODE, 0,
-+		OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
-+
-+	REG_UPDATE(OPPBUF_CONTROL,
-+		OPPBUF_ACTIVE_WIDTH, 0);
-+	REG_UPDATE(OPPBUF_3D_PARAMETERS_0,
-+		OPPBUF_3D_VACT_SPACE1_SIZE, 0);
-+}
-+
-+/**
-+ * program_timing_generator   used by mode timing set
-+ * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
-+ * Including SYNC. Call BIOS command table to program Timings.
-+ */
-+static void tgn10_program_timing(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *dc_crtc_timing,
-+	bool use_vbios)
-+{
-+	struct dc_crtc_timing patched_crtc_timing;
-+	uint32_t vesa_sync_start;
-+	uint32_t asic_blank_end;
-+	uint32_t asic_blank_start;
-+	uint32_t v_total;
-+	uint32_t v_sync_end;
-+	uint32_t v_init, v_fp2;
-+	uint32_t h_sync_polarity, v_sync_polarity;
-+	uint32_t interlace_factor;
-+	uint32_t start_point = 0;
-+	uint32_t field_num = 0;
-+	uint32_t h_div_2;
-+	int32_t vertical_line_start;
-+
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	patched_crtc_timing = *dc_crtc_timing;
-+	tgn10_apply_front_porch_workaround(tg, &patched_crtc_timing);
-+
-+	/* Load horizontal timing */
-+
-+	/* CRTC_H_TOTAL = vesa.h_total - 1 */
-+	REG_SET(OTG_H_TOTAL, 0,
-+			OTG_H_TOTAL,  patched_crtc_timing.h_total - 1);
-+
-+	/* h_sync_start = 0, h_sync_end = vesa.h_sync_width */
-+	REG_UPDATE_2(OTG_H_SYNC_A,
-+			OTG_H_SYNC_A_START, 0,
-+			OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
-+
-+	/* asic_h_blank_end = HsyncWidth + HbackPorch =
-+	 * vesa. usHorizontalTotal - vesa. usHorizontalSyncStart -
-+	 * vesa.h_left_border
-+	 */
-+	vesa_sync_start = patched_crtc_timing.h_addressable +
-+			patched_crtc_timing.h_border_right +
-+			patched_crtc_timing.h_front_porch;
-+
-+	asic_blank_end = patched_crtc_timing.h_total -
-+			vesa_sync_start -
-+			patched_crtc_timing.h_border_left;
-+
-+	/* h_blank_start = v_blank_end + v_active */
-+	asic_blank_start = asic_blank_end +
-+			patched_crtc_timing.h_border_left +
-+			patched_crtc_timing.h_addressable +
-+			patched_crtc_timing.h_border_right;
-+
-+	REG_UPDATE_2(OTG_H_BLANK_START_END,
-+			OTG_H_BLANK_START, asic_blank_start,
-+			OTG_H_BLANK_END, asic_blank_end);
-+
-+	/* h_sync polarity */
-+	h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ?
-+			0 : 1;
-+
-+	REG_UPDATE(OTG_H_SYNC_A_CNTL,
-+			OTG_H_SYNC_A_POL, h_sync_polarity);
-+
-+	/* Load vertical timing */
-+
-+	/* CRTC_V_TOTAL = v_total - 1 */
-+	if (patched_crtc_timing.flags.INTERLACE) {
-+		interlace_factor = 2;
-+		v_total = 2 * patched_crtc_timing.v_total;
-+	} else {
-+		interlace_factor = 1;
-+		v_total = patched_crtc_timing.v_total - 1;
-+	}
-+	REG_SET(OTG_V_TOTAL, 0,
-+			OTG_V_TOTAL, v_total);
-+
-+	/* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
-+	 * OTG_V_TOTAL_MIN are equal to V_TOTAL.
-+	 */
-+	REG_SET(OTG_V_TOTAL_MAX, 0,
-+		OTG_V_TOTAL_MAX, v_total);
-+	REG_SET(OTG_V_TOTAL_MIN, 0,
-+		OTG_V_TOTAL_MIN, v_total);
-+
-+	/* v_sync_start = 0, v_sync_end = v_sync_width */
-+	v_sync_end = patched_crtc_timing.v_sync_width * interlace_factor;
-+
-+	REG_UPDATE_2(OTG_V_SYNC_A,
-+			OTG_V_SYNC_A_START, 0,
-+			OTG_V_SYNC_A_END, v_sync_end);
-+
-+	vesa_sync_start = patched_crtc_timing.v_addressable +
-+			patched_crtc_timing.v_border_bottom +
-+			patched_crtc_timing.v_front_porch;
-+
-+	asic_blank_end = (patched_crtc_timing.v_total -
-+			vesa_sync_start -
-+			patched_crtc_timing.v_border_top)
-+			* interlace_factor;
-+
-+	/* v_blank_start = v_blank_end + v_active */
-+	asic_blank_start = asic_blank_end +
-+			(patched_crtc_timing.v_border_top +
-+			patched_crtc_timing.v_addressable +
-+			patched_crtc_timing.v_border_bottom)
-+			* interlace_factor;
-+
-+	REG_UPDATE_2(OTG_V_BLANK_START_END,
-+			OTG_V_BLANK_START, asic_blank_start,
-+			OTG_V_BLANK_END, asic_blank_end);
-+
-+	/* Use OTG_VERTICAL_INTERRUPT2 replace VUPDATE interrupt,
-+	 * program the reg for interrupt postition.
-+	 */
-+	vertical_line_start = asic_blank_end - tg->dlg_otg_param.vstartup_start + 1;
-+	if (vertical_line_start < 0) {
-+		ASSERT(0);
-+		vertical_line_start = 0;
-+	}
-+	REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
-+			OTG_VERTICAL_INTERRUPT2_LINE_START, vertical_line_start);
-+
-+	/* v_sync polarity */
-+	v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
-+			0 : 1;
-+
-+	REG_UPDATE(OTG_V_SYNC_A_CNTL,
-+			OTG_V_SYNC_A_POL, v_sync_polarity);
-+
-+	v_init = asic_blank_start;
-+	if (tg->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+		tg->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
-+		tg->dlg_otg_param.signal == SIGNAL_TYPE_EDP) {
-+		start_point = 1;
-+		if (patched_crtc_timing.flags.INTERLACE == 1)
-+			field_num = 1;
-+	}
-+	v_fp2 = 0;
-+	if (tg->dlg_otg_param.vstartup_start > asic_blank_end)
-+		v_fp2 = tg->dlg_otg_param.vstartup_start > asic_blank_end;
-+
-+	/* Interlace */
-+	if (patched_crtc_timing.flags.INTERLACE == 1) {
-+		REG_UPDATE(OTG_INTERLACE_CONTROL,
-+				OTG_INTERLACE_ENABLE, 1);
-+		v_init = v_init / 2;
-+		if ((tg->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end)
-+			v_fp2 = v_fp2 / 2;
-+	}
-+	else
-+		REG_UPDATE(OTG_INTERLACE_CONTROL,
-+				OTG_INTERLACE_ENABLE, 0);
-+
-+
-+	/* VTG enable set to 0 first VInit */
-+	REG_UPDATE(CONTROL,
-+			VTG0_ENABLE, 0);
-+
-+	REG_UPDATE_2(CONTROL,
-+			VTG0_FP2, v_fp2,
-+			VTG0_VCOUNT_INIT, v_init);
-+
-+	/* original code is using VTG offset to address OTG reg, seems wrong */
-+	REG_UPDATE_2(OTG_CONTROL,
-+			OTG_START_POINT_CNTL, start_point,
-+			OTG_FIELD_NUMBER_CNTL, field_num);
-+
-+	tgn10_program_global_sync(tg);
-+
-+	/* TODO
-+	 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
-+	 * program_horz_count_by_2
-+	 * for DVI 30bpp mode, 0 otherwise
-+	 * program_horz_count_by_2(tg, &patched_crtc_timing);
-+	 */
-+
-+	/* Enable stereo - only when we need to pack 3D frame. Other types
-+	 * of stereo handled in explicit call
-+	 */
-+	h_div_2 = (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) ?
-+			1 : 0;
-+
-+	REG_UPDATE(OTG_H_TIMING_CNTL,
-+			OTG_H_TIMING_DIV_BY2, h_div_2);
-+
-+}
-+
-+static void tgn10_set_blank_data_double_buffer(struct timing_generator *tg, bool enable)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
-+
-+	REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
-+			OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
-+}
-+
-+/**
-+ * unblank_crtc
-+ * Call ASIC Control Object to UnBlank CRTC.
-+ */
-+static void tgn10_unblank_crtc(struct timing_generator *tg)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+	uint32_t vertical_interrupt_enable = 0;
-+
-+	REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,
-+			OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &vertical_interrupt_enable);
-+
-+	/* temporary work around for vertical interrupt, once vertical interrupt enabled,
-+	 * this check will be removed.
-+	 */
-+	if (vertical_interrupt_enable)
-+		tgn10_set_blank_data_double_buffer(tg, true);
-+
-+	REG_UPDATE_2(OTG_BLANK_CONTROL,
-+			OTG_BLANK_DATA_EN, 0,
-+			OTG_BLANK_DE_MODE, 0);
-+}
-+
-+/**
-+ * blank_crtc
-+ * Call ASIC Control Object to Blank CRTC.
-+ */
-+
-+static void tgn10_blank_crtc(struct timing_generator *tg)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	REG_UPDATE_2(OTG_BLANK_CONTROL,
-+			OTG_BLANK_DATA_EN, 1,
-+			OTG_BLANK_DE_MODE, 0);
-+
-+	/* todo: why are we waiting for BLANK_DATA_EN?  shouldn't we be waiting
-+	 * for status?
-+	 */
-+	REG_WAIT(OTG_BLANK_CONTROL,
-+			OTG_BLANK_DATA_EN, 1,
-+			1, 100000);
-+
-+	tgn10_set_blank_data_double_buffer(tg, false);
-+}
-+
-+static void tgn10_set_blank(struct timing_generator *tg,
-+		bool enable_blanking)
-+{
-+	if (enable_blanking)
-+		tgn10_blank_crtc(tg);
-+	else
-+		tgn10_unblank_crtc(tg);
-+}
-+
-+static bool tgn10_is_blanked(struct timing_generator *tg)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+	uint32_t blank_en;
-+	uint32_t blank_state;
-+
-+	REG_GET_2(OTG_BLANK_CONTROL,
-+			OTG_BLANK_DATA_EN, &blank_en,
-+			OTG_CURRENT_BLANK_STATE, &blank_state);
-+
-+	return blank_en && blank_state;
-+}
-+
-+static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	if (enable) {
-+		REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
-+				OPTC_INPUT_CLK_EN, 1,
-+				OPTC_INPUT_CLK_GATE_DIS, 1);
-+
-+		REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
-+				OPTC_INPUT_CLK_ON, 1,
-+				1, 1000);
-+
-+		/* Enable clock */
-+		REG_UPDATE_2(OTG_CLOCK_CONTROL,
-+				OTG_CLOCK_EN, 1,
-+				OTG_CLOCK_GATE_DIS, 1);
-+		REG_WAIT(OTG_CLOCK_CONTROL,
-+				OTG_CLOCK_ON, 1,
-+				1, 1000);
-+	} else  {
-+		REG_UPDATE_2(OTG_CLOCK_CONTROL,
-+				OTG_CLOCK_GATE_DIS, 0,
-+				OTG_CLOCK_EN, 0);
-+
-+		REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
-+				OPTC_INPUT_CLK_GATE_DIS, 0,
-+				OPTC_INPUT_CLK_EN, 0);
-+	}
-+}
-+
-+/**
-+ * Enable CRTC
-+ * Enable CRTC - call ASIC Control Object to enable Timing generator.
-+ */
-+static bool tgn10_enable_crtc(struct timing_generator *tg)
-+{
-+	/* TODO FPGA wait for answer
-+	 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
-+	 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
-+	 */
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	/* opp instance for OTG. For DCN1.0, ODM is remoed.
-+	 * OPP and OPTC should 1:1 mapping
-+	 */
-+	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
-+			OPTC_SRC_SEL, tg->inst);
-+
-+	/* VTG enable first is for HW workaround */
-+	REG_UPDATE(CONTROL,
-+			VTG0_ENABLE, 1);
-+
-+	/* Enable CRTC */
-+	REG_UPDATE_2(OTG_CONTROL,
-+			OTG_DISABLE_POINT_CNTL, 3,
-+			OTG_MASTER_EN, 1);
-+
-+	return true;
-+}
-+
-+/* disable_crtc - call ASIC Control Object to disable Timing generator. */
-+static bool tgn10_disable_crtc(struct timing_generator *tg)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	/* disable otg request until end of the first line
-+	 * in the vertical blank region
-+	 */
-+	REG_UPDATE_2(OTG_CONTROL,
-+			OTG_DISABLE_POINT_CNTL, 3,
-+			OTG_MASTER_EN, 0);
-+
-+	REG_UPDATE(CONTROL,
-+			VTG0_ENABLE, 0);
-+
-+	/* CRTC disabled, so disable  clock. */
-+	REG_WAIT(OTG_CLOCK_CONTROL,
-+			OTG_BUSY, 0,
-+			1, 100000);
-+
-+	return true;
-+}
-+
-+
-+static void tgn10_program_blank_color(
-+		struct timing_generator *tg,
-+		const struct tg_color *black_color)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	REG_SET_3(OTG_BLACK_COLOR, 0,
-+			OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
-+			OTG_BLACK_COLOR_G_Y, black_color->color_g_y,
-+			OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
-+}
-+
-+static bool tgn10_validate_timing(
-+	struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing)
-+{
-+	uint32_t interlace_factor;
-+	uint32_t v_blank;
-+	uint32_t h_blank;
-+	uint32_t min_v_blank;
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	ASSERT(timing != NULL);
-+
-+	interlace_factor = timing->flags.INTERLACE ? 2 : 1;
-+	v_blank = (timing->v_total - timing->v_addressable -
-+					timing->v_border_top - timing->v_border_bottom) *
-+					interlace_factor;
-+
-+	h_blank = (timing->h_total - timing->h_addressable -
-+		timing->h_border_right -
-+		timing->h_border_left);
-+
-+	if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
-+		timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
-+		timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
-+		timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
-+		timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
-+		timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
-+		return false;
-+
-+	/* Temporarily blocking interlacing mode until it's supported */
-+	if (timing->flags.INTERLACE == 1)
-+		return false;
-+
-+	/* Check maximum number of pixels supported by Timing Generator
-+	 * (Currently will never fail, in order to fail needs display which
-+	 * needs more than 8192 horizontal and
-+	 * more than 8192 vertical total pixels)
-+	 */
-+	if (timing->h_total > tgn10->max_h_total ||
-+		timing->v_total > tgn10->max_v_total)
-+		return false;
-+
-+
-+	if (h_blank < tgn10->min_h_blank)
-+		return false;
-+
-+	if (timing->h_sync_width  < tgn10->min_h_sync_width ||
-+		 timing->v_sync_width  < tgn10->min_v_sync_width)
-+		return false;
-+
-+	min_v_blank = timing->flags.INTERLACE?tgn10->min_v_blank_interlace:tgn10->min_v_blank;
-+
-+	if (v_blank < min_v_blank)
-+		return false;
-+
-+	return true;
-+
-+}
-+
-+/*
-+ * get_vblank_counter
-+ *
-+ * @brief
-+ * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
-+ * holds the counter of frames.
-+ *
-+ * @param
-+ * struct timing_generator *tg - [in] timing generator which controls the
-+ * desired CRTC
-+ *
-+ * @return
-+ * Counter of frames, which should equal to number of vblanks.
-+ */
-+static uint32_t tgn10_get_vblank_counter(struct timing_generator *tg)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+	uint32_t frame_count;
-+
-+	REG_GET(OTG_STATUS_FRAME_COUNT,
-+		OTG_FRAME_COUNT, &frame_count);
-+
-+	return frame_count;
-+}
-+
-+static void tgn10_lock(struct timing_generator *tg)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	REG_SET(OTG_GLOBAL_CONTROL0, 0,
-+			OTG_MASTER_UPDATE_LOCK_SEL, tg->inst);
-+	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-+			OTG_MASTER_UPDATE_LOCK, 1);
-+
-+	/* Should be fast, status does not update on maximus */
-+	if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-+		REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-+				UPDATE_LOCK_STATUS, 1,
-+				1, 10);
-+}
-+
-+static void tgn10_unlock(struct timing_generator *tg)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-+			OTG_MASTER_UPDATE_LOCK, 0);
-+}
-+
-+static void tgn10_get_position(struct timing_generator *tg,
-+		struct crtc_position *position)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	REG_GET_2(OTG_STATUS_POSITION,
-+			OTG_HORZ_COUNT, &position->horizontal_count,
-+			OTG_VERT_COUNT, &position->vertical_count);
-+
-+	REG_GET(OTG_NOM_VERT_POSITION,
-+			OTG_VERT_COUNT_NOM, &position->nominal_vcount);
-+}
-+
-+static bool tgn10_is_counter_moving(struct timing_generator *tg)
-+{
-+	struct crtc_position position1, position2;
-+
-+	tg->funcs->get_position(tg, &position1);
-+	tg->funcs->get_position(tg, &position2);
-+
-+	if (position1.horizontal_count == position2.horizontal_count &&
-+		position1.vertical_count == position2.vertical_count)
-+		return false;
-+	else
-+		return true;
-+}
-+
-+static bool tgn10_did_triggered_reset_occur(
-+	struct timing_generator *tg)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+	uint32_t occurred_force, occurred_vsync;
-+
-+	REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
-+		OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
-+
-+	REG_GET(OTG_VERT_SYNC_CONTROL,
-+		OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
-+
-+	return occurred_vsync != 0 || occurred_force != 0;
-+}
-+
-+static void tgn10_disable_reset_trigger(struct timing_generator *tg)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	REG_WRITE(OTG_TRIGA_CNTL, 0);
-+
-+	REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
-+		OTG_FORCE_COUNT_NOW_CLEAR, 1);
-+
-+	REG_SET(OTG_VERT_SYNC_CONTROL, 0,
-+		OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
-+}
-+
-+static void tgn10_enable_reset_trigger(struct timing_generator *tg, int source_tg_inst)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+	uint32_t falling_edge;
-+
-+	REG_GET(OTG_V_SYNC_A_CNTL,
-+			OTG_V_SYNC_A_POL, &falling_edge);
-+
-+	if (falling_edge)
-+		REG_SET_3(OTG_TRIGA_CNTL, 0,
-+				/* vsync signal from selected OTG pipe based
-+				 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
-+				 */
-+				OTG_TRIGA_SOURCE_SELECT, 20,
-+				OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
-+				/* always detect falling edge */
-+				OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1);
-+	else
-+		REG_SET_3(OTG_TRIGA_CNTL, 0,
-+				/* vsync signal from selected OTG pipe based
-+				 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
-+				 */
-+				OTG_TRIGA_SOURCE_SELECT, 20,
-+				OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
-+				/* always detect rising edge */
-+				OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1);
-+
-+	REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
-+			/* force H count to H_TOTAL and V count to V_TOTAL in
-+			 * progressive mode and V_TOTAL-1 in interlaced mode
-+			 */
-+			OTG_FORCE_COUNT_NOW_MODE, 2);
-+}
-+
-+void tgn10_enable_crtc_reset(
-+		struct timing_generator *tg,
-+		int source_tg_inst,
-+		struct crtc_trigger_info *crtc_tp)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+	uint32_t falling_edge = 0;
-+	uint32_t rising_edge = 0;
-+
-+	switch (crtc_tp->event) {
-+
-+	case CRTC_EVENT_VSYNC_RISING:
-+		rising_edge = 1;
-+		break;
-+
-+	case CRTC_EVENT_VSYNC_FALLING:
-+		falling_edge = 1;
-+		break;
-+	}
-+
-+	REG_SET_4(OTG_TRIGA_CNTL, 0,
-+		 /* vsync signal from selected OTG pipe based
-+		  * on OTG_TRIG_SOURCE_PIPE_SELECT setting
-+		  */
-+		  OTG_TRIGA_SOURCE_SELECT, 20,
-+		  OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
-+		  /* always detect falling edge */
-+		  OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
-+		  OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
-+
-+	switch (crtc_tp->delay) {
-+	case TRIGGER_DELAY_NEXT_LINE:
-+		REG_SET(OTG_VERT_SYNC_CONTROL, 0,
-+				OTG_AUTO_FORCE_VSYNC_MODE, 1);
-+		break;
-+	case TRIGGER_DELAY_NEXT_PIXEL:
-+		REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
-+			/* force H count to H_TOTAL and V count to V_TOTAL in
-+			 * progressive mode and V_TOTAL-1 in interlaced mode
-+			 */
-+			OTG_FORCE_COUNT_NOW_MODE, 2);
-+		break;
-+	}
-+}
-+
-+static void tgn10_wait_for_state(struct timing_generator *tg,
-+		enum crtc_state state)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	switch (state) {
-+	case CRTC_STATE_VBLANK:
-+		REG_WAIT(OTG_STATUS,
-+				OTG_V_BLANK, 1,
-+				1, 100000); /* 1 vupdate at 10hz */
-+		break;
-+
-+	case CRTC_STATE_VACTIVE:
-+		REG_WAIT(OTG_STATUS,
-+				OTG_V_ACTIVE_DISP, 1,
-+				1, 100000); /* 1 vupdate at 10hz */
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+static void tgn10_set_early_control(
-+	struct timing_generator *tg,
-+	uint32_t early_cntl)
-+{
-+	/* asic design change, do not need this control
-+	 * empty for share caller logic
-+	 */
-+}
-+
-+
-+static void tgn10_set_static_screen_control(
-+	struct timing_generator *tg,
-+	uint32_t value)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	/* Bit 8 is no longer applicable in RV for PSR case,
-+	 * set bit 8 to 0 if given
-+	 */
-+	if ((value & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN)
-+			!= 0)
-+		value = value &
-+		~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN;
-+
-+	REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
-+			OTG_STATIC_SCREEN_EVENT_MASK, value,
-+			OTG_STATIC_SCREEN_FRAME_COUNT, 2);
-+}
-+
-+
-+/**
-+ *****************************************************************************
-+ *  Function: set_drr
-+ *
-+ *  @brief
-+ *     Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
-+ *
-+ *****************************************************************************
-+ */
-+static void tgn10_set_drr(
-+	struct timing_generator *tg,
-+	const struct drr_params *params)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	if (params != NULL &&
-+		params->vertical_total_max > 0 &&
-+		params->vertical_total_min > 0) {
-+
-+		REG_SET(OTG_V_TOTAL_MAX, 0,
-+			OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
-+
-+		REG_SET(OTG_V_TOTAL_MIN, 0,
-+			OTG_V_TOTAL_MIN, params->vertical_total_min - 1);
-+
-+		REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
-+				OTG_V_TOTAL_MIN_SEL, 1,
-+				OTG_V_TOTAL_MAX_SEL, 1,
-+				OTG_FORCE_LOCK_ON_EVENT, 0,
-+				OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
-+				OTG_SET_V_TOTAL_MIN_MASK, 0);
-+	} else {
-+		REG_SET(OTG_V_TOTAL_MIN, 0,
-+			OTG_V_TOTAL_MIN, 0);
-+
-+		REG_SET(OTG_V_TOTAL_MAX, 0,
-+			OTG_V_TOTAL_MAX, 0);
-+
-+		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
-+				OTG_SET_V_TOTAL_MIN_MASK, 0,
-+				OTG_V_TOTAL_MIN_SEL, 0,
-+				OTG_V_TOTAL_MAX_SEL, 0,
-+				OTG_FORCE_LOCK_ON_EVENT, 0);
-+	}
-+}
-+
-+static void tgn10_set_test_pattern(
-+	struct timing_generator *tg,
-+	/* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
-+	 * because this is not DP-specific (which is probably somewhere in DP
-+	 * encoder) */
-+	enum controller_dp_test_pattern test_pattern,
-+	enum dc_color_depth color_depth)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+	enum test_pattern_color_format bit_depth;
-+	enum test_pattern_dyn_range dyn_range;
-+	enum test_pattern_mode mode;
-+	uint32_t pattern_mask;
-+	uint32_t pattern_data;
-+	/* color ramp generator mixes 16-bits color */
-+	uint32_t src_bpc = 16;
-+	/* requested bpc */
-+	uint32_t dst_bpc;
-+	uint32_t index;
-+	/* RGB values of the color bars.
-+	 * Produce two RGB colors: RGB0 - white (all Fs)
-+	 * and RGB1 - black (all 0s)
-+	 * (three RGB components for two colors)
-+	 */
-+	uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
-+						0x0000, 0x0000};
-+	/* dest color (converted to the specified color format) */
-+	uint16_t dst_color[6];
-+	uint32_t inc_base;
-+
-+	/* translate to bit depth */
-+	switch (color_depth) {
-+	case COLOR_DEPTH_666:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
-+	break;
-+	case COLOR_DEPTH_888:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
-+	break;
-+	case COLOR_DEPTH_101010:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
-+	break;
-+	case COLOR_DEPTH_121212:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
-+	break;
-+	default:
-+		bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
-+	break;
-+	}
-+
-+	switch (test_pattern) {
-+	case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
-+	case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
-+	{
-+		dyn_range = (test_pattern ==
-+				CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
-+				TEST_PATTERN_DYN_RANGE_CEA :
-+				TEST_PATTERN_DYN_RANGE_VESA);
-+		mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
-+
-+		REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
-+				OTG_TEST_PATTERN_VRES, 6,
-+				OTG_TEST_PATTERN_HRES, 6);
-+
-+		REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
-+				OTG_TEST_PATTERN_EN, 1,
-+				OTG_TEST_PATTERN_MODE, mode,
-+				OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
-+				OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
-+	}
-+	break;
-+
-+	case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
-+	case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
-+	{
-+		mode = (test_pattern ==
-+			CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
-+			TEST_PATTERN_MODE_VERTICALBARS :
-+			TEST_PATTERN_MODE_HORIZONTALBARS);
-+
-+		switch (bit_depth) {
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_6:
-+			dst_bpc = 6;
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_8:
-+			dst_bpc = 8;
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_10:
-+			dst_bpc = 10;
-+		break;
-+		default:
-+			dst_bpc = 8;
-+		break;
-+		}
-+
-+		/* adjust color to the required colorFormat */
-+		for (index = 0; index < 6; index++) {
-+			/* dst = 2^dstBpc * src / 2^srcBpc = src >>
-+			 * (srcBpc - dstBpc);
-+			 */
-+			dst_color[index] =
-+				src_color[index] >> (src_bpc - dst_bpc);
-+		/* CRTC_TEST_PATTERN_DATA has 16 bits,
-+		 * lowest 6 are hardwired to ZERO
-+		 * color bits should be left aligned aligned to MSB
-+		 * XXXXXXXXXX000000 for 10 bit,
-+		 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
-+		 */
-+			dst_color[index] <<= (16 - dst_bpc);
-+		}
-+
-+		REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
-+
-+		/* We have to write the mask before data, similar to pipeline.
-+		 * For example, for 8 bpc, if we want RGB0 to be magenta,
-+		 * and RGB1 to be cyan,
-+		 * we need to make 7 writes:
-+		 * MASK   DATA
-+		 * 000001 00000000 00000000                     set mask to R0
-+		 * 000010 11111111 00000000     R0 255, 0xFF00, set mask to G0
-+		 * 000100 00000000 00000000     G0 0,   0x0000, set mask to B0
-+		 * 001000 11111111 00000000     B0 255, 0xFF00, set mask to R1
-+		 * 010000 00000000 00000000     R1 0,   0x0000, set mask to G1
-+		 * 100000 11111111 00000000     G1 255, 0xFF00, set mask to B1
-+		 * 100000 11111111 00000000     B1 255, 0xFF00
-+		 *
-+		 * we will make a loop of 6 in which we prepare the mask,
-+		 * then write, then prepare the color for next write.
-+		 * first iteration will write mask only,
-+		 * but each next iteration color prepared in
-+		 * previous iteration will be written within new mask,
-+		 * the last component will written separately,
-+		 * mask is not changing between 6th and 7th write
-+		 * and color will be prepared by last iteration
-+		 */
-+
-+		/* write color, color values mask in CRTC_TEST_PATTERN_MASK
-+		 * is B1, G1, R1, B0, G0, R0
-+		 */
-+		pattern_data = 0;
-+		for (index = 0; index < 6; index++) {
-+			/* prepare color mask, first write PATTERN_DATA
-+			 * will have all zeros
-+			 */
-+			pattern_mask = (1 << index);
-+
-+			/* write color component */
-+			REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
-+					OTG_TEST_PATTERN_MASK, pattern_mask,
-+					OTG_TEST_PATTERN_DATA, pattern_data);
-+
-+			/* prepare next color component,
-+			 * will be written in the next iteration
-+			 */
-+			pattern_data = dst_color[index];
-+		}
-+		/* write last color component,
-+		 * it's been already prepared in the loop
-+		 */
-+		REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
-+				OTG_TEST_PATTERN_MASK, pattern_mask,
-+				OTG_TEST_PATTERN_DATA, pattern_data);
-+
-+		/* enable test pattern */
-+		REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
-+				OTG_TEST_PATTERN_EN, 1,
-+				OTG_TEST_PATTERN_MODE, mode,
-+				OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
-+				OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
-+	}
-+	break;
-+
-+	case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
-+	{
-+		mode = (bit_depth ==
-+			TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
-+			TEST_PATTERN_MODE_DUALRAMP_RGB :
-+			TEST_PATTERN_MODE_SINGLERAMP_RGB);
-+
-+		switch (bit_depth) {
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_6:
-+			dst_bpc = 6;
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_8:
-+			dst_bpc = 8;
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_10:
-+			dst_bpc = 10;
-+		break;
-+		default:
-+			dst_bpc = 8;
-+		break;
-+		}
-+
-+		/* increment for the first ramp for one color gradation
-+		 * 1 gradation for 6-bit color is 2^10
-+		 * gradations in 16-bit color
-+		 */
-+		inc_base = (src_bpc - dst_bpc);
-+
-+		switch (bit_depth) {
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_6:
-+		{
-+			REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
-+					OTG_TEST_PATTERN_INC0, inc_base,
-+					OTG_TEST_PATTERN_INC1, 0,
-+					OTG_TEST_PATTERN_HRES, 6,
-+					OTG_TEST_PATTERN_VRES, 6,
-+					OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
-+		}
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_8:
-+		{
-+			REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
-+					OTG_TEST_PATTERN_INC0, inc_base,
-+					OTG_TEST_PATTERN_INC1, 0,
-+					OTG_TEST_PATTERN_HRES, 8,
-+					OTG_TEST_PATTERN_VRES, 6,
-+					OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
-+		}
-+		break;
-+		case TEST_PATTERN_COLOR_FORMAT_BPC_10:
-+		{
-+			REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
-+					OTG_TEST_PATTERN_INC0, inc_base,
-+					OTG_TEST_PATTERN_INC1, inc_base + 2,
-+					OTG_TEST_PATTERN_HRES, 8,
-+					OTG_TEST_PATTERN_VRES, 5,
-+					OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
-+		}
-+		break;
-+		default:
-+		break;
-+		}
-+
-+		REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
-+
-+		/* enable test pattern */
-+		REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
-+
-+		REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
-+				OTG_TEST_PATTERN_EN, 1,
-+				OTG_TEST_PATTERN_MODE, mode,
-+				OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
-+				OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
-+	}
-+	break;
-+	case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
-+	{
-+		REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
-+		REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
-+		REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
-+	}
-+	break;
-+	default:
-+		break;
-+
-+	}
-+}
-+
-+static void tgn10_get_crtc_scanoutpos(
-+	struct timing_generator *tg,
-+	uint32_t *v_blank_start,
-+	uint32_t *v_blank_end,
-+	uint32_t *h_position,
-+	uint32_t *v_position)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+	struct crtc_position position;
-+
-+	REG_GET_2(OTG_V_BLANK_START_END,
-+			OTG_V_BLANK_START, v_blank_start,
-+			OTG_V_BLANK_END, v_blank_end);
-+
-+	tgn10_get_position(tg, &position);
-+
-+	*h_position = position.horizontal_count;
-+	*v_position = position.vertical_count;
-+}
-+
-+
-+
-+static void tgn10_enable_stereo(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	uint32_t active_width = timing->h_addressable;
-+	uint32_t space1_size = timing->v_total - timing->v_addressable;
-+
-+	if (flags) {
-+		uint32_t stereo_en;
-+		stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
-+
-+		if (flags->PROGRAM_STEREO)
-+			REG_UPDATE_3(OTG_STEREO_CONTROL,
-+				OTG_STEREO_EN, stereo_en,
-+				OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
-+				OTG_STEREO_SYNC_OUTPUT_POLARITY, 0);
-+
-+		if (flags->PROGRAM_POLARITY)
-+			REG_UPDATE(OTG_STEREO_CONTROL,
-+				OTG_STEREO_EYE_FLAG_POLARITY,
-+				flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
-+
-+		if (flags->DISABLE_STEREO_DP_SYNC)
-+			REG_UPDATE(OTG_STEREO_CONTROL,
-+				OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
-+
-+		if (flags->PROGRAM_STEREO)
-+			REG_UPDATE_3(OTG_3D_STRUCTURE_CONTROL,
-+				OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
-+				OTG_3D_STRUCTURE_V_UPDATE_MODE, flags->FRAME_PACKED,
-+				OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED);
-+
-+	}
-+
-+	REG_UPDATE(OPPBUF_CONTROL,
-+		OPPBUF_ACTIVE_WIDTH, active_width);
-+
-+	REG_UPDATE(OPPBUF_3D_PARAMETERS_0,
-+		OPPBUF_3D_VACT_SPACE1_SIZE, space1_size);
-+}
-+
-+static void tgn10_program_stereo(struct timing_generator *tg,
-+	const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
-+{
-+	if (flags->PROGRAM_STEREO)
-+		tgn10_enable_stereo(tg, timing, flags);
-+	else
-+		tgn10_disable_stereo(tg);
-+}
-+
-+
-+static bool tgn10_is_stereo_left_eye(struct timing_generator *tg)
-+{
-+	bool ret = false;
-+	uint32_t left_eye = 0;
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	REG_GET(OTG_STEREO_STATUS,
-+		OTG_STEREO_CURRENT_EYE, &left_eye);
-+	if (left_eye == 1)
-+		ret = true;
-+	else
-+		ret = false;
-+
-+	return ret;
-+}
-+
-+void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10,
-+		struct dcn_otg_state *s)
-+{
-+	REG_GET(OTG_CONTROL,
-+			OTG_MASTER_EN, &s->otg_enabled);
-+
-+	REG_GET_2(OTG_V_BLANK_START_END,
-+			OTG_V_BLANK_START, &s->v_blank_start,
-+			OTG_V_BLANK_END, &s->v_blank_end);
-+
-+	REG_GET(OTG_V_SYNC_A_CNTL,
-+			OTG_V_SYNC_A_POL, &s->v_sync_a_pol);
-+
-+	REG_GET(OTG_V_TOTAL,
-+			OTG_V_TOTAL, &s->v_total);
-+
-+	REG_GET(OTG_V_TOTAL_MAX,
-+			OTG_V_TOTAL_MAX, &s->v_total_max);
-+
-+	REG_GET(OTG_V_TOTAL_MIN,
-+			OTG_V_TOTAL_MIN, &s->v_total_min);
-+
-+	REG_GET_2(OTG_V_SYNC_A,
-+			OTG_V_SYNC_A_START, &s->v_sync_a_start,
-+			OTG_V_SYNC_A_END, &s->v_sync_a_end);
-+
-+	REG_GET_2(OTG_H_BLANK_START_END,
-+			OTG_H_BLANK_START, &s->h_blank_start,
-+			OTG_H_BLANK_END, &s->h_blank_end);
-+
-+	REG_GET_2(OTG_H_SYNC_A,
-+			OTG_H_SYNC_A_START, &s->h_sync_a_start,
-+			OTG_H_SYNC_A_END, &s->h_sync_a_end);
-+
-+	REG_GET(OTG_H_SYNC_A_CNTL,
-+			OTG_H_SYNC_A_POL, &s->h_sync_a_pol);
-+
-+	REG_GET(OTG_H_TOTAL,
-+			OTG_H_TOTAL, &s->h_total);
-+
-+	REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
-+			OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
-+}
-+
-+static void tgn10_tg_init(struct timing_generator *tg)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+
-+	tgn10_set_blank_data_double_buffer(tg, true);
-+	REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
-+}
-+
-+static bool tgn10_is_tg_enabled(struct timing_generator *tg)
-+{
-+	struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
-+	uint32_t otg_enabled = 0;
-+
-+	REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
-+
-+	return (otg_enabled != 0);
-+
-+}
-+static const struct timing_generator_funcs dcn10_tg_funcs = {
-+		.validate_timing = tgn10_validate_timing,
-+		.program_timing = tgn10_program_timing,
-+		.program_global_sync = tgn10_program_global_sync,
-+		.enable_crtc = tgn10_enable_crtc,
-+		.disable_crtc = tgn10_disable_crtc,
-+		/* used by enable_timing_synchronization. Not need for FPGA */
-+		.is_counter_moving = tgn10_is_counter_moving,
-+		.get_position = tgn10_get_position,
-+		.get_frame_count = tgn10_get_vblank_counter,
-+		.get_scanoutpos = tgn10_get_crtc_scanoutpos,
-+		.set_early_control = tgn10_set_early_control,
-+		/* used by enable_timing_synchronization. Not need for FPGA */
-+		.wait_for_state = tgn10_wait_for_state,
-+		.set_blank = tgn10_set_blank,
-+		.is_blanked = tgn10_is_blanked,
-+		.set_blank_color = tgn10_program_blank_color,
-+		.did_triggered_reset_occur = tgn10_did_triggered_reset_occur,
-+		.enable_reset_trigger = tgn10_enable_reset_trigger,
-+		.enable_crtc_reset = tgn10_enable_crtc_reset,
-+		.disable_reset_trigger = tgn10_disable_reset_trigger,
-+		.lock = tgn10_lock,
-+		.unlock = tgn10_unlock,
-+		.enable_optc_clock = tgn10_enable_optc_clock,
-+		.set_drr = tgn10_set_drr,
-+		.set_static_screen_control = tgn10_set_static_screen_control,
-+		.set_test_pattern = tgn10_set_test_pattern,
-+		.program_stereo = tgn10_program_stereo,
-+		.is_stereo_left_eye = tgn10_is_stereo_left_eye,
-+		.set_blank_data_double_buffer = tgn10_set_blank_data_double_buffer,
-+		.tg_init = tgn10_tg_init,
-+		.is_tg_enabled = tgn10_is_tg_enabled,
-+};
-+
-+void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10)
-+{
-+	tgn10->base.funcs = &dcn10_tg_funcs;
-+
-+	tgn10->max_h_total = tgn10->tg_mask->OTG_H_TOTAL + 1;
-+	tgn10->max_v_total = tgn10->tg_mask->OTG_V_TOTAL + 1;
-+
-+	tgn10->min_h_blank = 32;
-+	tgn10->min_v_blank = 3;
-+	tgn10->min_v_blank_interlace = 5;
-+	tgn10->min_h_sync_width = 8;
-+	tgn10->min_v_sync_width = 1;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h.0130~	2017-12-14 06:39:58.424903574 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h	2017-12-14 06:39:58.424903574 +0100
-@@ -0,0 +1,403 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ *  and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_TIMING_GENERATOR_DCN10_H__
-+#define __DC_TIMING_GENERATOR_DCN10_H__
-+
-+#include "timing_generator.h"
-+
-+#define DCN10TG_FROM_TG(tg)\
-+	container_of(tg, struct dcn10_timing_generator, base)
-+
-+#define TG_COMMON_REG_LIST_DCN(inst) \
-+	SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
-+	SRI(OTG_VUPDATE_PARAM, OTG, inst),\
-+	SRI(OTG_VREADY_PARAM, OTG, inst),\
-+	SRI(OTG_BLANK_CONTROL, OTG, inst),\
-+	SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
-+	SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
-+	SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
-+	SRI(OTG_H_TOTAL, OTG, inst),\
-+	SRI(OTG_H_BLANK_START_END, OTG, inst),\
-+	SRI(OTG_H_SYNC_A, OTG, inst),\
-+	SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
-+	SRI(OTG_H_TIMING_CNTL, OTG, inst),\
-+	SRI(OTG_V_TOTAL, OTG, inst),\
-+	SRI(OTG_V_BLANK_START_END, OTG, inst),\
-+	SRI(OTG_V_SYNC_A, OTG, inst),\
-+	SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
-+	SRI(OTG_INTERLACE_CONTROL, OTG, inst),\
-+	SRI(OTG_CONTROL, OTG, inst),\
-+	SRI(OTG_STEREO_CONTROL, OTG, inst),\
-+	SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
-+	SRI(OTG_STEREO_STATUS, OTG, inst),\
-+	SRI(OTG_V_TOTAL_MAX, OTG, inst),\
-+	SRI(OTG_V_TOTAL_MIN, OTG, inst),\
-+	SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
-+	SRI(OTG_TRIGA_CNTL, OTG, inst),\
-+	SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
-+	SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
-+	SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
-+	SRI(OTG_STATUS, OTG, inst),\
-+	SRI(OTG_STATUS_POSITION, OTG, inst),\
-+	SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
-+	SRI(OTG_BLACK_COLOR, OTG, inst),\
-+	SRI(OTG_CLOCK_CONTROL, OTG, inst),\
-+	SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
-+	SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
-+	SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
-+	SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
-+	SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
-+	SRI(OPPBUF_CONTROL, OPPBUF, inst),\
-+	SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, inst),\
-+	SRI(CONTROL, VTG, inst),\
-+	SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
-+	SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\
-+	SRI(OTG_GSL_CONTROL, OTG, inst)
-+
-+#define TG_COMMON_REG_LIST_DCN1_0(inst) \
-+	TG_COMMON_REG_LIST_DCN(inst),\
-+	SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
-+	SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
-+	SRI(OTG_TEST_PATTERN_COLOR, OTG, inst)
-+
-+
-+struct dcn_tg_registers {
-+	uint32_t OTG_VERT_SYNC_CONTROL;
-+	uint32_t OTG_MASTER_UPDATE_MODE;
-+	uint32_t OTG_GSL_CONTROL;
-+	uint32_t OTG_VSTARTUP_PARAM;
-+	uint32_t OTG_VUPDATE_PARAM;
-+	uint32_t OTG_VREADY_PARAM;
-+	uint32_t OTG_BLANK_CONTROL;
-+	uint32_t OTG_MASTER_UPDATE_LOCK;
-+	uint32_t OTG_GLOBAL_CONTROL0;
-+	uint32_t OTG_DOUBLE_BUFFER_CONTROL;
-+	uint32_t OTG_H_TOTAL;
-+	uint32_t OTG_H_BLANK_START_END;
-+	uint32_t OTG_H_SYNC_A;
-+	uint32_t OTG_H_SYNC_A_CNTL;
-+	uint32_t OTG_H_TIMING_CNTL;
-+	uint32_t OTG_V_TOTAL;
-+	uint32_t OTG_V_BLANK_START_END;
-+	uint32_t OTG_V_SYNC_A;
-+	uint32_t OTG_V_SYNC_A_CNTL;
-+	uint32_t OTG_INTERLACE_CONTROL;
-+	uint32_t OTG_CONTROL;
-+	uint32_t OTG_STEREO_CONTROL;
-+	uint32_t OTG_3D_STRUCTURE_CONTROL;
-+	uint32_t OTG_STEREO_STATUS;
-+	uint32_t OTG_V_TOTAL_MAX;
-+	uint32_t OTG_V_TOTAL_MIN;
-+	uint32_t OTG_V_TOTAL_CONTROL;
-+	uint32_t OTG_TRIGA_CNTL;
-+	uint32_t OTG_FORCE_COUNT_NOW_CNTL;
-+	uint32_t OTG_STATIC_SCREEN_CONTROL;
-+	uint32_t OTG_STATUS_FRAME_COUNT;
-+	uint32_t OTG_STATUS;
-+	uint32_t OTG_STATUS_POSITION;
-+	uint32_t OTG_NOM_VERT_POSITION;
-+	uint32_t OTG_BLACK_COLOR;
-+	uint32_t OTG_TEST_PATTERN_PARAMETERS;
-+	uint32_t OTG_TEST_PATTERN_CONTROL;
-+	uint32_t OTG_TEST_PATTERN_COLOR;
-+	uint32_t OTG_CLOCK_CONTROL;
-+	uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL;
-+	uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;
-+	uint32_t OPTC_INPUT_CLOCK_CONTROL;
-+	uint32_t OPTC_DATA_SOURCE_SELECT;
-+	uint32_t OPTC_INPUT_GLOBAL_CONTROL;
-+	uint32_t OPPBUF_CONTROL;
-+	uint32_t OPPBUF_3D_PARAMETERS_0;
-+	uint32_t CONTROL;
-+};
-+
-+#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
-+	SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
-+	SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
-+	SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
-+	SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
-+	SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
-+	SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
-+	SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
-+	SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
-+	SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
-+	SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
-+	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
-+	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\
-+	SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
-+	SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
-+	SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
-+	SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
-+	SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
-+	SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
-+	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\
-+	SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
-+	SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
-+	SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
-+	SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
-+	SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
-+	SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
-+	SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\
-+	SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
-+	SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
-+	SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
-+	SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
-+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
-+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
-+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
-+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
-+	SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
-+	SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
-+	SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
-+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
-+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
-+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
-+	SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
-+	SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
-+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
-+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
-+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
-+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
-+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
-+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
-+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
-+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
-+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
-+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
-+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
-+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
-+	SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
-+	SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
-+	SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
-+	SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
-+	SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
-+	SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
-+	SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
-+	SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
-+	SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\
-+	SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\
-+	SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\
-+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
-+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
-+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
-+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
-+	SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
-+	SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
-+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
-+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
-+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
-+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
-+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
-+	SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\
-+	SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\
-+	SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
-+	SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
-+	SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
-+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
-+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
-+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
-+	SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\
-+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
-+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
-+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
-+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
-+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
-+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh)
-+
-+
-+#define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
-+	TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
-+	SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\
-+	SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\
-+	SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\
-+	SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\
-+	SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\
-+	SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\
-+	SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\
-+	SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\
-+	SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\
-+	SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\
-+	SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\
-+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh)
-+
-+#define TG_REG_FIELD_LIST(type) \
-+	type VSTARTUP_START;\
-+	type VUPDATE_OFFSET;\
-+	type VUPDATE_WIDTH;\
-+	type VREADY_OFFSET;\
-+	type OTG_BLANK_DATA_EN;\
-+	type OTG_BLANK_DE_MODE;\
-+	type OTG_CURRENT_BLANK_STATE;\
-+	type OTG_MASTER_UPDATE_LOCK;\
-+	type UPDATE_LOCK_STATUS;\
-+	type OTG_UPDATE_PENDING;\
-+	type OTG_MASTER_UPDATE_LOCK_SEL;\
-+	type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\
-+	type OTG_H_TOTAL;\
-+	type OTG_H_BLANK_START;\
-+	type OTG_H_BLANK_END;\
-+	type OTG_H_SYNC_A_START;\
-+	type OTG_H_SYNC_A_END;\
-+	type OTG_H_SYNC_A_POL;\
-+	type OTG_H_TIMING_DIV_BY2;\
-+	type OTG_V_TOTAL;\
-+	type OTG_V_BLANK_START;\
-+	type OTG_V_BLANK_END;\
-+	type OTG_V_SYNC_A_START;\
-+	type OTG_V_SYNC_A_END;\
-+	type OTG_V_SYNC_A_POL;\
-+	type OTG_INTERLACE_ENABLE;\
-+	type OTG_MASTER_EN;\
-+	type OTG_START_POINT_CNTL;\
-+	type OTG_DISABLE_POINT_CNTL;\
-+	type OTG_FIELD_NUMBER_CNTL;\
-+	type OTG_STEREO_EN;\
-+	type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\
-+	type OTG_STEREO_SYNC_OUTPUT_POLARITY;\
-+	type OTG_STEREO_EYE_FLAG_POLARITY;\
-+	type OTG_STEREO_CURRENT_EYE;\
-+	type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\
-+	type OTG_3D_STRUCTURE_EN;\
-+	type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
-+	type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\
-+	type OTG_V_TOTAL_MAX;\
-+	type OTG_V_TOTAL_MIN;\
-+	type OTG_V_TOTAL_MIN_SEL;\
-+	type OTG_V_TOTAL_MAX_SEL;\
-+	type OTG_FORCE_LOCK_ON_EVENT;\
-+	type OTG_SET_V_TOTAL_MIN_MASK_EN;\
-+	type OTG_SET_V_TOTAL_MIN_MASK;\
-+	type OTG_FORCE_COUNT_NOW_CLEAR;\
-+	type OTG_FORCE_COUNT_NOW_MODE;\
-+	type OTG_FORCE_COUNT_NOW_OCCURRED;\
-+	type OTG_TRIGA_SOURCE_SELECT;\
-+	type OTG_TRIGA_SOURCE_PIPE_SELECT;\
-+	type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\
-+	type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\
-+	type OTG_STATIC_SCREEN_EVENT_MASK;\
-+	type OTG_STATIC_SCREEN_FRAME_COUNT;\
-+	type OTG_FRAME_COUNT;\
-+	type OTG_V_BLANK;\
-+	type OTG_V_ACTIVE_DISP;\
-+	type OTG_HORZ_COUNT;\
-+	type OTG_VERT_COUNT;\
-+	type OTG_VERT_COUNT_NOM;\
-+	type OTG_BLACK_COLOR_B_CB;\
-+	type OTG_BLACK_COLOR_G_Y;\
-+	type OTG_BLACK_COLOR_R_CR;\
-+	type OTG_TEST_PATTERN_INC0;\
-+	type OTG_TEST_PATTERN_INC1;\
-+	type OTG_TEST_PATTERN_VRES;\
-+	type OTG_TEST_PATTERN_HRES;\
-+	type OTG_TEST_PATTERN_RAMP0_OFFSET;\
-+	type OTG_TEST_PATTERN_EN;\
-+	type OTG_TEST_PATTERN_MODE;\
-+	type OTG_TEST_PATTERN_DYNAMIC_RANGE;\
-+	type OTG_TEST_PATTERN_COLOR_FORMAT;\
-+	type OTG_TEST_PATTERN_MASK;\
-+	type OTG_TEST_PATTERN_DATA;\
-+	type OTG_BUSY;\
-+	type OTG_CLOCK_EN;\
-+	type OTG_CLOCK_ON;\
-+	type OTG_CLOCK_GATE_DIS;\
-+	type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\
-+	type OTG_VERTICAL_INTERRUPT2_LINE_START;\
-+	type OPTC_INPUT_CLK_EN;\
-+	type OPTC_INPUT_CLK_ON;\
-+	type OPTC_INPUT_CLK_GATE_DIS;\
-+	type OPTC_SRC_SEL;\
-+	type OPTC_SEG0_SRC_SEL;\
-+	type OPTC_UNDERFLOW_OCCURRED_STATUS;\
-+	type OPTC_UNDERFLOW_CLEAR;\
-+	type OPPBUF_ACTIVE_WIDTH;\
-+	type OPPBUF_3D_VACT_SPACE1_SIZE;\
-+	type VTG0_ENABLE;\
-+	type VTG0_FP2;\
-+	type VTG0_VCOUNT_INIT;\
-+	type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\
-+	type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\
-+	type OTG_AUTO_FORCE_VSYNC_MODE;\
-+	type MASTER_UPDATE_INTERLACED_MODE;\
-+	type OTG_GSL0_EN;\
-+	type OTG_GSL1_EN;\
-+	type OTG_GSL2_EN;\
-+	type OTG_GSL_MASTER_EN;\
-+	type OTG_GSL_FORCE_DELAY;\
-+	type OTG_GSL_CHECK_ALL_FIELDS;
-+
-+struct dcn_tg_shift {
-+	TG_REG_FIELD_LIST(uint8_t)
-+};
-+
-+struct dcn_tg_mask {
-+	TG_REG_FIELD_LIST(uint32_t)
-+};
-+
-+struct dcn10_timing_generator {
-+	struct timing_generator base;
-+
-+	const struct dcn_tg_registers *tg_regs;
-+	const struct dcn_tg_shift *tg_shift;
-+	const struct dcn_tg_mask *tg_mask;
-+
-+	enum controller_id controller_id;
-+
-+	uint32_t max_h_total;
-+	uint32_t max_v_total;
-+
-+	uint32_t min_h_blank;
-+
-+	uint32_t min_h_sync_width;
-+	uint32_t min_v_sync_width;
-+	uint32_t min_v_blank;
-+	uint32_t min_v_blank_interlace;
-+};
-+
-+void dcn10_timing_generator_init(struct dcn10_timing_generator *tg);
-+
-+struct dcn_otg_state {
-+	uint32_t v_blank_start;
-+	uint32_t v_blank_end;
-+	uint32_t v_sync_a_pol;
-+	uint32_t v_total;
-+	uint32_t v_total_max;
-+	uint32_t v_total_min;
-+	uint32_t v_sync_a_start;
-+	uint32_t v_sync_a_end;
-+	uint32_t h_blank_start;
-+	uint32_t h_blank_end;
-+	uint32_t h_sync_a_start;
-+	uint32_t h_sync_a_end;
-+	uint32_t h_sync_a_pol;
-+	uint32_t h_total;
-+	uint32_t underflow_occurred_status;
-+	uint32_t otg_enabled;
-+};
-+
-+void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10,
-+		struct dcn_otg_state *s);
-+
-+#endif /* __DC_TIMING_GENERATOR_DCN10_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/Makefile.0130~	2017-12-14 06:39:58.424903574 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dcn10/Makefile	2017-12-14 06:39:58.424903574 +0100
-@@ -0,0 +1,12 @@
-+#
-+# Makefile for DCN.
-+
-+DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
-+		dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \
-+		dcn10_hubp.o dcn10_mpc.o \
-+		dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
-+		dcn10_hubbub.o
-+
-+AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_DCN10)
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dc_stream.h.0130~	2017-12-14 06:39:58.424903574 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dc_stream.h	2017-12-14 06:39:58.424903574 +0100
-@@ -0,0 +1,289 @@
-+/*
-+ * Copyright 2012-14 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef DC_STREAM_H_
-+#define DC_STREAM_H_
-+
-+#include "dc_types.h"
-+#include "grph_object_defs.h"
-+
-+/*******************************************************************************
-+ * Stream Interfaces
-+ ******************************************************************************/
-+
-+struct dc_stream_status {
-+	int primary_otg_inst;
-+	int stream_enc_inst;
-+	int plane_count;
-+	struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
-+
-+	/*
-+	 * link this stream passes through
-+	 */
-+	struct dc_link *link;
-+};
-+
-+struct dc_stream_state {
-+	struct dc_sink *sink;
-+	struct dc_crtc_timing timing;
-+
-+	struct rect src; /* composition area */
-+	struct rect dst; /* stream addressable area */
-+
-+	struct audio_info audio_info;
-+
-+	struct freesync_context freesync_ctx;
-+
-+	struct dc_hdr_static_metadata hdr_static_metadata;
-+	struct dc_transfer_func *out_transfer_func;
-+	struct colorspace_transform gamut_remap_matrix;
-+	struct csc_transform csc_color_matrix;
-+
-+	enum dc_color_space output_color_space;
-+	enum dc_dither_option dither_option;
-+
-+	enum view_3d_format view_format;
-+
-+	bool ignore_msa_timing_param;
-+	/* TODO: custom INFO packets */
-+	/* TODO: ABM info (DMCU) */
-+	/* TODO: PSR info */
-+	/* TODO: CEA VIC */
-+
-+	/* from core_stream struct */
-+	struct dc_context *ctx;
-+
-+	/* used by DCP and FMT */
-+	struct bit_depth_reduction_params bit_depth_params;
-+	struct clamping_and_pixel_encoding_params clamping;
-+
-+	int phy_pix_clk;
-+	enum signal_type signal;
-+	bool dpms_off;
-+
-+	struct dc_stream_status status;
-+
-+	struct dc_cursor_attributes cursor_attributes;
-+
-+	/* from stream struct */
-+	struct kref refcount;
-+
-+	struct crtc_trigger_info triggered_crtc_reset;
-+
-+};
-+
-+struct dc_stream_update {
-+	struct rect src;
-+	struct rect dst;
-+	struct dc_transfer_func *out_transfer_func;
-+	struct dc_hdr_static_metadata *hdr_static_metadata;
-+};
-+
-+bool dc_is_stream_unchanged(
-+	struct dc_stream_state *old_stream, struct dc_stream_state *stream);
-+bool dc_is_stream_scaling_unchanged(
-+	struct dc_stream_state *old_stream, struct dc_stream_state *stream);
-+
-+/*
-+ * Set up surface attributes and associate to a stream
-+ * The surfaces parameter is an absolute set of all surface active for the stream.
-+ * If no surfaces are provided, the stream will be blanked; no memory read.
-+ * Any flip related attribute changes must be done through this interface.
-+ *
-+ * After this call:
-+ *   Surfaces attributes are programmed and configured to be composed into stream.
-+ *   This does not trigger a flip.  No surface address is programmed.
-+ */
-+
-+bool dc_commit_planes_to_stream(
-+		struct dc *dc,
-+		struct dc_plane_state **plane_states,
-+		uint8_t new_plane_count,
-+		struct dc_stream_state *dc_stream,
-+		struct dc_state *state);
-+
-+void dc_commit_updates_for_stream(struct dc *dc,
-+		struct dc_surface_update *srf_updates,
-+		int surface_count,
-+		struct dc_stream_state *stream,
-+		struct dc_stream_update *stream_update,
-+		struct dc_plane_state **plane_states,
-+		struct dc_state *state);
-+/*
-+ * Log the current stream state.
-+ */
-+void dc_stream_log(
-+	const struct dc_stream_state *stream,
-+	struct dal_logger *dc_logger,
-+	enum dc_log_type log_type);
-+
-+uint8_t dc_get_current_stream_count(struct dc *dc);
-+struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
-+
-+/*
-+ * Return the current frame counter.
-+ */
-+uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
-+
-+/* TODO: Return parsed values rather than direct register read
-+ * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
-+ * being refactored properly to be dce-specific
-+ */
-+bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
-+				  uint32_t *v_blank_start,
-+				  uint32_t *v_blank_end,
-+				  uint32_t *h_position,
-+				  uint32_t *v_position);
-+
-+enum dc_status dc_add_stream_to_ctx(
-+			struct dc *dc,
-+		struct dc_state *new_ctx,
-+		struct dc_stream_state *stream);
-+
-+enum dc_status dc_remove_stream_from_ctx(
-+		struct dc *dc,
-+			struct dc_state *new_ctx,
-+			struct dc_stream_state *stream);
-+
-+
-+bool dc_add_plane_to_context(
-+		const struct dc *dc,
-+		struct dc_stream_state *stream,
-+		struct dc_plane_state *plane_state,
-+		struct dc_state *context);
-+
-+bool dc_remove_plane_from_context(
-+		const struct dc *dc,
-+		struct dc_stream_state *stream,
-+		struct dc_plane_state *plane_state,
-+		struct dc_state *context);
-+
-+bool dc_rem_all_planes_for_stream(
-+		const struct dc *dc,
-+		struct dc_stream_state *stream,
-+		struct dc_state *context);
-+
-+bool dc_add_all_planes_for_stream(
-+		const struct dc *dc,
-+		struct dc_stream_state *stream,
-+		struct dc_plane_state * const *plane_states,
-+		int plane_count,
-+		struct dc_state *context);
-+
-+enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
-+
-+/*
-+ * This function takes a stream and checks if it is guaranteed to be supported.
-+ * Guaranteed means that MAX_COFUNC similar streams are supported.
-+ *
-+ * After this call:
-+ *   No hardware is programmed for call.  Only validation is done.
-+ */
-+
-+/*
-+ * Set up streams and links associated to drive sinks
-+ * The streams parameter is an absolute set of all active streams.
-+ *
-+ * After this call:
-+ *   Phy, Encoder, Timing Generator are programmed and enabled.
-+ *   New streams are enabled with blank stream; no memory read.
-+ */
-+/*
-+ * Enable stereo when commit_streams is not required,
-+ * for example, frame alternate.
-+ */
-+bool dc_enable_stereo(
-+	struct dc *dc,
-+	struct dc_state *context,
-+	struct dc_stream_state *streams[],
-+	uint8_t stream_count);
-+
-+
-+enum surface_update_type dc_check_update_surfaces_for_stream(
-+		struct dc *dc,
-+		struct dc_surface_update *updates,
-+		int surface_count,
-+		struct dc_stream_update *stream_update,
-+		const struct dc_stream_status *stream_status);
-+
-+/**
-+ * Create a new default stream for the requested sink
-+ */
-+struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
-+
-+void dc_stream_retain(struct dc_stream_state *dc_stream);
-+void dc_stream_release(struct dc_stream_state *dc_stream);
-+
-+struct dc_stream_status *dc_stream_get_status(
-+	struct dc_stream_state *dc_stream);
-+
-+/*******************************************************************************
-+ * Cursor interfaces - To manages the cursor within a stream
-+ ******************************************************************************/
-+/* TODO: Deprecated once we switch to dc_set_cursor_position */
-+bool dc_stream_set_cursor_attributes(
-+	struct dc_stream_state *stream,
-+	const struct dc_cursor_attributes *attributes);
-+
-+bool dc_stream_set_cursor_position(
-+	struct dc_stream_state *stream,
-+	const struct dc_cursor_position *position);
-+
-+bool dc_stream_adjust_vmin_vmax(struct dc *dc,
-+				struct dc_stream_state **stream,
-+				int num_streams,
-+				int vmin,
-+				int vmax);
-+
-+bool dc_stream_get_crtc_position(struct dc *dc,
-+				 struct dc_stream_state **stream,
-+				 int num_streams,
-+				 unsigned int *v_pos,
-+				 unsigned int *nom_v_pos);
-+
-+void dc_stream_set_static_screen_events(struct dc *dc,
-+					struct dc_stream_state **stream,
-+					int num_streams,
-+					const struct dc_static_screen_events *events);
-+
-+
-+bool dc_stream_adjust_vmin_vmax(struct dc *dc,
-+				struct dc_stream_state **stream,
-+				int num_streams,
-+				int vmin,
-+				int vmax);
-+
-+bool dc_stream_get_crtc_position(struct dc *dc,
-+				 struct dc_stream_state **stream,
-+				 int num_streams,
-+				 unsigned int *v_pos,
-+				 unsigned int *nom_v_pos);
-+
-+void dc_stream_set_static_screen_events(struct dc *dc,
-+					struct dc_stream_state **stream,
-+					int num_streams,
-+					const struct dc_static_screen_events *events);
-+
-+#endif /* DC_STREAM_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dc_types.h.0130~	2017-12-14 06:39:58.424903574 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dc_types.h	2017-12-14 06:39:58.424903574 +0100
-@@ -0,0 +1,647 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef DC_TYPES_H_
-+#define DC_TYPES_H_
-+
-+#include "fixed32_32.h"
-+#include "fixed31_32.h"
-+#include "irq_types.h"
-+#include "dc_dp_types.h"
-+#include "dc_hw_types.h"
-+#include "dal_types.h"
-+#include "grph_object_defs.h"
-+
-+/* forward declarations */
-+struct dc_plane_state;
-+struct dc_stream_state;
-+struct dc_link;
-+struct dc_sink;
-+struct dal;
-+
-+/********************************
-+ * Environment definitions
-+ ********************************/
-+enum dce_environment {
-+	DCE_ENV_PRODUCTION_DRV = 0,
-+	/* Emulation on FPGA, in "Maximus" System.
-+	 * This environment enforces that *only* DC registers accessed.
-+	 * (access to non-DC registers will hang FPGA) */
-+	DCE_ENV_FPGA_MAXIMUS,
-+	/* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
-+	 * requirements of Diagnostics team. */
-+	DCE_ENV_DIAG
-+};
-+
-+/* Note: use these macro definitions instead of direct comparison! */
-+#define IS_FPGA_MAXIMUS_DC(dce_environment) \
-+	(dce_environment == DCE_ENV_FPGA_MAXIMUS)
-+
-+#define IS_DIAG_DC(dce_environment) \
-+	(IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
-+
-+struct hw_asic_id {
-+	uint32_t chip_id;
-+	uint32_t chip_family;
-+	uint32_t pci_revision_id;
-+	uint32_t hw_internal_rev;
-+	uint32_t vram_type;
-+	uint32_t vram_width;
-+	uint32_t feature_flags;
-+	uint32_t fake_paths_num;
-+	void *atombios_base_address;
-+};
-+
-+struct dc_context {
-+	struct dc *dc;
-+
-+	void *driver_context; /* e.g. amdgpu_device */
-+
-+	struct dal_logger *logger;
-+	void *cgs_device;
-+
-+	enum dce_environment dce_environment;
-+	struct hw_asic_id asic_id;
-+
-+	/* todo: below should probably move to dc.  to facilitate removal
-+	 * of AS we will store these here
-+	 */
-+	enum dce_version dce_version;
-+	struct dc_bios *dc_bios;
-+	bool created_bios;
-+	struct gpio_service *gpio_service;
-+	struct i2caux *i2caux;
-+#if defined(CONFIG_DRM_AMD_DC_FBC)
-+	uint64_t fbc_gpu_addr;
-+#endif
-+};
-+
-+
-+#define MAX_EDID_BUFFER_SIZE 512
-+#define EDID_BLOCK_SIZE 128
-+#define MAX_SURFACE_NUM 4
-+#define NUM_PIXEL_FORMATS 10
-+
-+#include "dc_ddc_types.h"
-+
-+enum tiling_mode {
-+	TILING_MODE_INVALID,
-+	TILING_MODE_LINEAR,
-+	TILING_MODE_TILED,
-+	TILING_MODE_COUNT
-+};
-+
-+enum view_3d_format {
-+	VIEW_3D_FORMAT_NONE = 0,
-+	VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
-+	VIEW_3D_FORMAT_SIDE_BY_SIDE,
-+	VIEW_3D_FORMAT_TOP_AND_BOTTOM,
-+	VIEW_3D_FORMAT_COUNT,
-+	VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
-+};
-+
-+enum plane_stereo_format {
-+	PLANE_STEREO_FORMAT_NONE = 0,
-+	PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
-+	PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
-+	PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
-+	PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
-+	PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
-+	PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
-+};
-+
-+/* TODO: Find way to calculate number of bits
-+ *  Please increase if pixel_format enum increases
-+ * num  from  PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
-+ */
-+
-+enum dc_edid_connector_type {
-+	EDID_CONNECTOR_UNKNOWN = 0,
-+	EDID_CONNECTOR_ANALOG = 1,
-+	EDID_CONNECTOR_DIGITAL = 10,
-+	EDID_CONNECTOR_DVI = 11,
-+	EDID_CONNECTOR_HDMIA = 12,
-+	EDID_CONNECTOR_MDDI = 14,
-+	EDID_CONNECTOR_DISPLAYPORT = 15
-+};
-+
-+enum dc_edid_status {
-+	EDID_OK,
-+	EDID_BAD_INPUT,
-+	EDID_NO_RESPONSE,
-+	EDID_BAD_CHECKSUM,
-+	EDID_THE_SAME,
-+};
-+
-+/* audio capability from EDID*/
-+struct dc_cea_audio_mode {
-+	uint8_t format_code; /* ucData[0] [6:3]*/
-+	uint8_t channel_count; /* ucData[0] [2:0]*/
-+	uint8_t sample_rate; /* ucData[1]*/
-+	union {
-+		uint8_t sample_size; /* for LPCM*/
-+		/*  for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
-+		uint8_t max_bit_rate;
-+		uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
-+	};
-+};
-+
-+struct dc_edid {
-+	uint32_t length;
-+	uint8_t raw_edid[MAX_EDID_BUFFER_SIZE];
-+};
-+
-+/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
-+ * is used. In this case we assume speaker location are: front left, front
-+ * right and front center. */
-+#define DEFAULT_SPEAKER_LOCATION 5
-+
-+#define DC_MAX_AUDIO_DESC_COUNT 16
-+
-+#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
-+
-+union display_content_support {
-+	unsigned int raw;
-+	struct {
-+		unsigned int valid_content_type :1;
-+		unsigned int game_content :1;
-+		unsigned int cinema_content :1;
-+		unsigned int photo_content :1;
-+		unsigned int graphics_content :1;
-+		unsigned int reserved :27;
-+	} bits;
-+};
-+
-+struct dc_edid_caps {
-+	/* sink identification */
-+	uint16_t manufacturer_id;
-+	uint16_t product_id;
-+	uint32_t serial_number;
-+	uint8_t manufacture_week;
-+	uint8_t manufacture_year;
-+	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
-+
-+	/* audio caps */
-+	uint8_t speaker_flags;
-+	uint32_t audio_mode_count;
-+	struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
-+	uint32_t audio_latency;
-+	uint32_t video_latency;
-+
-+	union display_content_support content_support;
-+
-+	uint8_t qs_bit;
-+	uint8_t qy_bit;
-+
-+	/*HDMI 2.0 caps*/
-+	bool lte_340mcsc_scramble;
-+
-+	bool edid_hdmi;
-+};
-+
-+struct view {
-+	uint32_t width;
-+	uint32_t height;
-+};
-+
-+struct dc_mode_flags {
-+	/* note: part of refresh rate flag*/
-+	uint32_t INTERLACE :1;
-+	/* native display timing*/
-+	uint32_t NATIVE :1;
-+	/* preferred is the recommended mode, one per display */
-+	uint32_t PREFERRED :1;
-+	/* true if this mode should use reduced blanking timings
-+	 *_not_ related to the Reduced Blanking adjustment*/
-+	uint32_t REDUCED_BLANKING :1;
-+	/* note: part of refreshrate flag*/
-+	uint32_t VIDEO_OPTIMIZED_RATE :1;
-+	/* should be reported to upper layers as mode_flags*/
-+	uint32_t PACKED_PIXEL_FORMAT :1;
-+	/*< preferred view*/
-+	uint32_t PREFERRED_VIEW :1;
-+	/* this timing should be used only in tiled mode*/
-+	uint32_t TILED_MODE :1;
-+	uint32_t DSE_MODE :1;
-+	/* Refresh rate divider when Miracast sink is using a
-+	 different rate than the output display device
-+	 Must be zero for wired displays and non-zero for
-+	 Miracast displays*/
-+	uint32_t MIRACAST_REFRESH_DIVIDER;
-+};
-+
-+
-+enum dc_timing_source {
-+	TIMING_SOURCE_UNDEFINED,
-+
-+	/* explicitly specifed by user, most important*/
-+	TIMING_SOURCE_USER_FORCED,
-+	TIMING_SOURCE_USER_OVERRIDE,
-+	TIMING_SOURCE_CUSTOM,
-+	TIMING_SOURCE_EXPLICIT,
-+
-+	/* explicitly specified by the display device, more important*/
-+	TIMING_SOURCE_EDID_CEA_SVD_3D,
-+	TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
-+	TIMING_SOURCE_EDID_CEA_SVD_420,
-+	TIMING_SOURCE_EDID_DETAILED,
-+	TIMING_SOURCE_EDID_ESTABLISHED,
-+	TIMING_SOURCE_EDID_STANDARD,
-+	TIMING_SOURCE_EDID_CEA_SVD,
-+	TIMING_SOURCE_EDID_CVT_3BYTE,
-+	TIMING_SOURCE_EDID_4BYTE,
-+	TIMING_SOURCE_VBIOS,
-+	TIMING_SOURCE_CV,
-+	TIMING_SOURCE_TV,
-+	TIMING_SOURCE_HDMI_VIC,
-+
-+	/* implicitly specified by display device, still safe but less important*/
-+	TIMING_SOURCE_DEFAULT,
-+
-+	/* only used for custom base modes */
-+	TIMING_SOURCE_CUSTOM_BASE,
-+
-+	/* these timing might not work, least important*/
-+	TIMING_SOURCE_RANGELIMIT,
-+	TIMING_SOURCE_OS_FORCED,
-+	TIMING_SOURCE_IMPLICIT,
-+
-+	/* only used by default mode list*/
-+	TIMING_SOURCE_BASICMODE,
-+
-+	TIMING_SOURCE_COUNT
-+};
-+
-+
-+struct stereo_3d_features {
-+	bool supported			;
-+	bool allTimings			;
-+	bool cloneMode			;
-+	bool scaling			;
-+	bool singleFrameSWPacked;
-+};
-+
-+enum dc_timing_support_method {
-+	TIMING_SUPPORT_METHOD_UNDEFINED,
-+	TIMING_SUPPORT_METHOD_EXPLICIT,
-+	TIMING_SUPPORT_METHOD_IMPLICIT,
-+	TIMING_SUPPORT_METHOD_NATIVE
-+};
-+
-+struct dc_mode_info {
-+	uint32_t pixel_width;
-+	uint32_t pixel_height;
-+	uint32_t field_rate;
-+	/* Vertical refresh rate for progressive modes.
-+	* Field rate for interlaced modes.*/
-+
-+	enum dc_timing_standard timing_standard;
-+	enum dc_timing_source timing_source;
-+	struct dc_mode_flags flags;
-+};
-+
-+enum dc_power_state {
-+	DC_POWER_STATE_ON = 1,
-+	DC_POWER_STATE_STANDBY,
-+	DC_POWER_STATE_SUSPEND,
-+	DC_POWER_STATE_OFF
-+};
-+
-+/* DC PowerStates */
-+enum dc_video_power_state {
-+	DC_VIDEO_POWER_UNSPECIFIED = 0,
-+	DC_VIDEO_POWER_ON = 1,
-+	DC_VIDEO_POWER_STANDBY,
-+	DC_VIDEO_POWER_SUSPEND,
-+	DC_VIDEO_POWER_OFF,
-+	DC_VIDEO_POWER_HIBERNATE,
-+	DC_VIDEO_POWER_SHUTDOWN,
-+	DC_VIDEO_POWER_ULPS,	/* BACO or Ultra-Light-Power-State */
-+	DC_VIDEO_POWER_AFTER_RESET,
-+	DC_VIDEO_POWER_MAXIMUM
-+};
-+
-+enum dc_acpi_cm_power_state {
-+	DC_ACPI_CM_POWER_STATE_D0 = 1,
-+	DC_ACPI_CM_POWER_STATE_D1 = 2,
-+	DC_ACPI_CM_POWER_STATE_D2 = 4,
-+	DC_ACPI_CM_POWER_STATE_D3 = 8
-+};
-+
-+enum dc_connection_type {
-+	dc_connection_none,
-+	dc_connection_single,
-+	dc_connection_mst_branch,
-+	dc_connection_active_dongle
-+};
-+
-+struct dc_csc_adjustments {
-+	struct fixed31_32 contrast;
-+	struct fixed31_32 saturation;
-+	struct fixed31_32 brightness;
-+	struct fixed31_32 hue;
-+};
-+
-+enum {
-+	MAX_LANES = 2,
-+	MAX_COFUNC_PATH = 6,
-+	LAYER_INDEX_PRIMARY = -1,
-+};
-+
-+enum dpcd_downstream_port_max_bpc {
-+	DOWN_STREAM_MAX_8BPC = 0,
-+	DOWN_STREAM_MAX_10BPC,
-+	DOWN_STREAM_MAX_12BPC,
-+	DOWN_STREAM_MAX_16BPC
-+};
-+struct dc_dongle_caps {
-+	/* dongle type (DP converter, CV smart dongle) */
-+	enum display_dongle_type dongle_type;
-+	bool extendedCapValid;
-+	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
-+	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
-+	bool is_dp_hdmi_s3d_converter;
-+	bool is_dp_hdmi_ycbcr422_pass_through;
-+	bool is_dp_hdmi_ycbcr420_pass_through;
-+	bool is_dp_hdmi_ycbcr422_converter;
-+	bool is_dp_hdmi_ycbcr420_converter;
-+	uint32_t dp_hdmi_max_bpc;
-+	uint32_t dp_hdmi_max_pixel_clk;
-+};
-+/* Scaling format */
-+enum scaling_transformation {
-+	SCALING_TRANSFORMATION_UNINITIALIZED,
-+	SCALING_TRANSFORMATION_IDENTITY = 0x0001,
-+	SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
-+	SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
-+	SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
-+	SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
-+	SCALING_TRANSFORMATION_INVALID = 0x80000000,
-+
-+	/* Flag the first and last */
-+	SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
-+	SCALING_TRANSFORMATION_END =
-+		SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
-+};
-+
-+enum display_content_type {
-+	DISPLAY_CONTENT_TYPE_NO_DATA = 0,
-+	DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
-+	DISPLAY_CONTENT_TYPE_PHOTO = 2,
-+	DISPLAY_CONTENT_TYPE_CINEMA = 4,
-+	DISPLAY_CONTENT_TYPE_GAME = 8
-+};
-+
-+/* audio*/
-+
-+union audio_sample_rates {
-+	struct sample_rates {
-+		uint8_t RATE_32:1;
-+		uint8_t RATE_44_1:1;
-+		uint8_t RATE_48:1;
-+		uint8_t RATE_88_2:1;
-+		uint8_t RATE_96:1;
-+		uint8_t RATE_176_4:1;
-+		uint8_t RATE_192:1;
-+	} rate;
-+
-+	uint8_t all;
-+};
-+
-+struct audio_speaker_flags {
-+	uint32_t FL_FR:1;
-+	uint32_t LFE:1;
-+	uint32_t FC:1;
-+	uint32_t RL_RR:1;
-+	uint32_t RC:1;
-+	uint32_t FLC_FRC:1;
-+	uint32_t RLC_RRC:1;
-+	uint32_t SUPPORT_AI:1;
-+};
-+
-+struct audio_speaker_info {
-+	uint32_t ALLSPEAKERS:7;
-+	uint32_t SUPPORT_AI:1;
-+};
-+
-+
-+struct audio_info_flags {
-+
-+	union {
-+
-+		struct audio_speaker_flags speaker_flags;
-+		struct audio_speaker_info   info;
-+
-+		uint8_t all;
-+	};
-+};
-+
-+enum audio_format_code {
-+	AUDIO_FORMAT_CODE_FIRST = 1,
-+	AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
-+
-+	AUDIO_FORMAT_CODE_AC3,
-+	/*Layers 1 & 2 */
-+	AUDIO_FORMAT_CODE_MPEG1,
-+	/*MPEG1 Layer 3 */
-+	AUDIO_FORMAT_CODE_MP3,
-+	/*multichannel */
-+	AUDIO_FORMAT_CODE_MPEG2,
-+	AUDIO_FORMAT_CODE_AAC,
-+	AUDIO_FORMAT_CODE_DTS,
-+	AUDIO_FORMAT_CODE_ATRAC,
-+	AUDIO_FORMAT_CODE_1BITAUDIO,
-+	AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
-+	AUDIO_FORMAT_CODE_DTS_HD,
-+	AUDIO_FORMAT_CODE_MAT_MLP,
-+	AUDIO_FORMAT_CODE_DST,
-+	AUDIO_FORMAT_CODE_WMAPRO,
-+	AUDIO_FORMAT_CODE_LAST,
-+	AUDIO_FORMAT_CODE_COUNT =
-+		AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
-+};
-+
-+struct audio_mode {
-+	 /* ucData[0] [6:3] */
-+	enum audio_format_code format_code;
-+	/* ucData[0] [2:0] */
-+	uint8_t channel_count;
-+	/* ucData[1] */
-+	union audio_sample_rates sample_rates;
-+	union {
-+		/* for LPCM */
-+		uint8_t sample_size;
-+		/* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
-+		uint8_t max_bit_rate;
-+		/* for Audio Formats 9-15 */
-+		uint8_t vendor_specific;
-+	};
-+};
-+
-+struct audio_info {
-+	struct audio_info_flags flags;
-+	uint32_t video_latency;
-+	uint32_t audio_latency;
-+	uint32_t display_index;
-+	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
-+	uint32_t manufacture_id;
-+	uint32_t product_id;
-+	/* PortID used for ContainerID when defined */
-+	uint32_t port_id[2];
-+	uint32_t mode_count;
-+	/* this field must be last in this struct */
-+	struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
-+};
-+
-+struct freesync_context {
-+	bool supported;
-+	bool enabled;
-+	bool active;
-+
-+	unsigned int min_refresh_in_micro_hz;
-+	unsigned int nominal_refresh_in_micro_hz;
-+};
-+
-+struct psr_config {
-+	unsigned char psr_version;
-+	unsigned int psr_rfb_setup_time;
-+	bool psr_exit_link_training_required;
-+
-+	bool psr_frame_capture_indication_req;
-+	unsigned int psr_sdp_transmit_line_num_deadline;
-+};
-+
-+union dmcu_psr_level {
-+	struct {
-+		unsigned int SKIP_CRC:1;
-+		unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
-+		unsigned int SKIP_PHY_POWER_DOWN:1;
-+		unsigned int SKIP_AUX_ACK_CHECK:1;
-+		unsigned int SKIP_CRTC_DISABLE:1;
-+		unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
-+		unsigned int SKIP_SMU_NOTIFICATION:1;
-+		unsigned int SKIP_AUTO_STATE_ADVANCE:1;
-+		unsigned int DISABLE_PSR_ENTRY_ABORT:1;
-+		unsigned int SKIP_SINGLE_OTG_DISABLE:1;
-+		unsigned int RESERVED:22;
-+	} bits;
-+	unsigned int u32all;
-+};
-+
-+enum physical_phy_id {
-+	PHYLD_0,
-+	PHYLD_1,
-+	PHYLD_2,
-+	PHYLD_3,
-+	PHYLD_4,
-+	PHYLD_5,
-+	PHYLD_6,
-+	PHYLD_7,
-+	PHYLD_8,
-+	PHYLD_9,
-+	PHYLD_COUNT,
-+	PHYLD_UNKNOWN = (-1L)
-+};
-+
-+enum phy_type {
-+	PHY_TYPE_UNKNOWN  = 1,
-+	PHY_TYPE_PCIE_PHY = 2,
-+	PHY_TYPE_UNIPHY = 3,
-+};
-+
-+struct psr_context {
-+	/* ddc line */
-+	enum channel_id channel;
-+	/* Transmitter id */
-+	enum transmitter transmitterId;
-+	/* Engine Id is used for Dig Be source select */
-+	enum engine_id engineId;
-+	/* Controller Id used for Dig Fe source select */
-+	enum controller_id controllerId;
-+	/* Pcie or Uniphy */
-+	enum phy_type phyType;
-+	/* Physical PHY Id used by SMU interpretation */
-+	enum physical_phy_id smuPhyId;
-+	/* Vertical total pixels from crtc timing.
-+	 * This is used for static screen detection.
-+	 * ie. If we want to detect half a frame,
-+	 * we use this to determine the hyst lines.
-+	 */
-+	unsigned int crtcTimingVerticalTotal;
-+	/* PSR supported from panel capabilities and
-+	 * current display configuration
-+	 */
-+	bool psrSupportedDisplayConfig;
-+	/* Whether fast link training is supported by the panel */
-+	bool psrExitLinkTrainingRequired;
-+	/* If RFB setup time is greater than the total VBLANK time,
-+	 * it is not possible for the sink to capture the video frame
-+	 * in the same frame the SDP is sent. In this case,
-+	 * the frame capture indication bit should be set and an extra
-+	 * static frame should be transmitted to the sink.
-+	 */
-+	bool psrFrameCaptureIndicationReq;
-+	/* Set the last possible line SDP may be transmitted without violating
-+	 * the RFB setup time or entering the active video frame.
-+	 */
-+	unsigned int sdpTransmitLineNumDeadline;
-+	/* The VSync rate in Hz used to calculate the
-+	 * step size for smooth brightness feature
-+	 */
-+	unsigned int vsyncRateHz;
-+	unsigned int skipPsrWaitForPllLock;
-+	unsigned int numberOfControllers;
-+	/* Unused, for future use. To indicate that first changed frame from
-+	 * state3 shouldn't result in psr_inactive, but rather to perform
-+	 * an automatic single frame rfb_update.
-+	 */
-+	bool rfb_update_auto_en;
-+	/* Number of frame before entering static screen */
-+	unsigned int timehyst_frames;
-+	/* Partial frames before entering static screen */
-+	unsigned int hyst_lines;
-+	/* # of repeated AUX transaction attempts to make before
-+	 * indicating failure to the driver
-+	 */
-+	unsigned int aux_repeats;
-+	/* Controls hw blocks to power down during PSR active state */
-+	union dmcu_psr_level psr_level;
-+	/* Controls additional delay after remote frame capture before
-+	 * continuing powerd own
-+	 */
-+	unsigned int frame_delay;
-+};
-+
-+struct colorspace_transform {
-+	struct fixed31_32 matrix[12];
-+	bool enable_remap;
-+};
-+
-+enum i2c_mot_mode {
-+	I2C_MOT_UNDEF,
-+	I2C_MOT_TRUE,
-+	I2C_MOT_FALSE
-+};
-+
-+#endif /* DC_TYPES_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dm_helpers.h.0130~	2017-12-14 06:39:58.424903574 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dm_helpers.h	2017-12-14 06:39:58.424903574 +0100
-@@ -0,0 +1,105 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/**
-+ * This file defines helper functions provided by the Display Manager to
-+ * Display Core.
-+ */
-+#ifndef __DM_HELPERS__
-+#define __DM_HELPERS__
-+
-+#include "dc_types.h"
-+#include "dc.h"
-+
-+struct dp_mst_stream_allocation_table;
-+
-+enum dc_edid_status dm_helpers_parse_edid_caps(
-+	struct dc_context *ctx,
-+	const struct dc_edid *edid,
-+	struct dc_edid_caps *edid_caps);
-+
-+/*
-+ * Writes payload allocation table in immediate downstream device.
-+ */
-+bool dm_helpers_dp_mst_write_payload_allocation_table(
-+		struct dc_context *ctx,
-+		const struct dc_stream_state *stream,
-+		struct dp_mst_stream_allocation_table *proposed_table,
-+		bool enable);
-+
-+/*
-+ * Polls for ACT (allocation change trigger) handled and
-+ */
-+bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
-+		struct dc_context *ctx,
-+		const struct dc_stream_state *stream);
-+/*
-+ * Sends ALLOCATE_PAYLOAD message.
-+ */
-+bool dm_helpers_dp_mst_send_payload_allocation(
-+		struct dc_context *ctx,
-+		const struct dc_stream_state *stream,
-+		bool enable);
-+
-+bool dm_helpers_dp_mst_start_top_mgr(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		bool boot);
-+
-+void dm_helpers_dp_mst_stop_top_mgr(
-+		struct dc_context *ctx,
-+		const struct dc_link *link);
-+/**
-+ * OS specific aux read callback.
-+ */
-+bool dm_helpers_dp_read_dpcd(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint32_t address,
-+		uint8_t *data,
-+		uint32_t size);
-+
-+/**
-+ * OS specific aux write callback.
-+ */
-+bool dm_helpers_dp_write_dpcd(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint32_t address,
-+		const uint8_t *data,
-+		uint32_t size);
-+
-+bool dm_helpers_submit_i2c(
-+		struct dc_context *ctx,
-+		const struct dc_link *link,
-+		struct i2c_command *cmd);
-+
-+enum dc_edid_status dm_helpers_read_local_edid(
-+		struct dc_context *ctx,
-+		struct dc_link *link,
-+		struct dc_sink *sink);
-+
-+
-+#endif /* __DM_HELPERS__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/dc_features.h.0130~	2017-12-14 06:39:58.424903574 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/dc_features.h	2017-12-14 06:39:58.424903574 +0100
-@@ -0,0 +1,559 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DC_FEATURES_H__
-+#define __DC_FEATURES_H__
-+
-+// local features
-+#define DC__PRESENT 1
-+#define DC__PRESENT__1 1
-+#define DC__NUM_DPP 4
-+#define DC__VOLTAGE_STATES 7
-+#define DC__NUM_DPP__4 1
-+#define DC__NUM_DPP__0_PRESENT 1
-+#define DC__NUM_DPP__1_PRESENT 1
-+#define DC__NUM_DPP__2_PRESENT 1
-+#define DC__NUM_DPP__3_PRESENT 1
-+#define DC__NUM_DPP__MAX 8
-+#define DC__NUM_DPP__MAX__8 1
-+#define DC__PIPE_10BIT 0
-+#define DC__PIPE_10BIT__0 1
-+#define DC__PIPE_10BIT__MAX 1
-+#define DC__PIPE_10BIT__MAX__1 1
-+#define DC__NUM_OPP 4
-+#define DC__NUM_OPP__4 1
-+#define DC__NUM_OPP__0_PRESENT 1
-+#define DC__NUM_OPP__1_PRESENT 1
-+#define DC__NUM_OPP__2_PRESENT 1
-+#define DC__NUM_OPP__3_PRESENT 1
-+#define DC__NUM_OPP__MAX 6
-+#define DC__NUM_OPP__MAX__6 1
-+#define DC__NUM_DSC 0
-+#define DC__NUM_DSC__0 1
-+#define DC__NUM_DSC__MAX 6
-+#define DC__NUM_DSC__MAX__6 1
-+#define DC__NUM_ABM 1
-+#define DC__NUM_ABM__1 1
-+#define DC__NUM_ABM__0_PRESENT 1
-+#define DC__NUM_ABM__MAX 2
-+#define DC__NUM_ABM__MAX__2 1
-+#define DC__ODM_PRESENT 0
-+#define DC__ODM_PRESENT__0 1
-+#define DC__NUM_OTG 4
-+#define DC__NUM_OTG__4 1
-+#define DC__NUM_OTG__0_PRESENT 1
-+#define DC__NUM_OTG__1_PRESENT 1
-+#define DC__NUM_OTG__2_PRESENT 1
-+#define DC__NUM_OTG__3_PRESENT 1
-+#define DC__NUM_OTG__MAX 6
-+#define DC__NUM_OTG__MAX__6 1
-+#define DC__NUM_DWB 2
-+#define DC__NUM_DWB__2 1
-+#define DC__NUM_DWB__0_PRESENT 1
-+#define DC__NUM_DWB__1_PRESENT 1
-+#define DC__NUM_DWB__MAX 2
-+#define DC__NUM_DWB__MAX__2 1
-+#define DC__NUM_DIG 4
-+#define DC__NUM_DIG__4 1
-+#define DC__NUM_DIG__0_PRESENT 1
-+#define DC__NUM_DIG__1_PRESENT 1
-+#define DC__NUM_DIG__2_PRESENT 1
-+#define DC__NUM_DIG__3_PRESENT 1
-+#define DC__NUM_DIG__MAX 6
-+#define DC__NUM_DIG__MAX__6 1
-+#define DC__NUM_AUX 4
-+#define DC__NUM_AUX__4 1
-+#define DC__NUM_AUX__0_PRESENT 1
-+#define DC__NUM_AUX__1_PRESENT 1
-+#define DC__NUM_AUX__2_PRESENT 1
-+#define DC__NUM_AUX__3_PRESENT 1
-+#define DC__NUM_AUX__MAX 6
-+#define DC__NUM_AUX__MAX__6 1
-+#define DC__NUM_AUDIO_STREAMS 4
-+#define DC__NUM_AUDIO_STREAMS__4 1
-+#define DC__NUM_AUDIO_STREAMS__0_PRESENT 1
-+#define DC__NUM_AUDIO_STREAMS__1_PRESENT 1
-+#define DC__NUM_AUDIO_STREAMS__2_PRESENT 1
-+#define DC__NUM_AUDIO_STREAMS__3_PRESENT 1
-+#define DC__NUM_AUDIO_STREAMS__MAX 8
-+#define DC__NUM_AUDIO_STREAMS__MAX__8 1
-+#define DC__NUM_AUDIO_ENDPOINTS 6
-+#define DC__NUM_AUDIO_ENDPOINTS__6 1
-+#define DC__NUM_AUDIO_ENDPOINTS__0_PRESENT 1
-+#define DC__NUM_AUDIO_ENDPOINTS__1_PRESENT 1
-+#define DC__NUM_AUDIO_ENDPOINTS__2_PRESENT 1
-+#define DC__NUM_AUDIO_ENDPOINTS__3_PRESENT 1
-+#define DC__NUM_AUDIO_ENDPOINTS__4_PRESENT 1
-+#define DC__NUM_AUDIO_ENDPOINTS__5_PRESENT 1
-+#define DC__NUM_AUDIO_ENDPOINTS__MAX 8
-+#define DC__NUM_AUDIO_ENDPOINTS__MAX__8 1
-+#define DC__NUM_AUDIO_INPUT_STREAMS 0
-+#define DC__NUM_AUDIO_INPUT_STREAMS__0 1
-+#define DC__NUM_AUDIO_INPUT_STREAMS__MAX 8
-+#define DC__NUM_AUDIO_INPUT_STREAMS__MAX__8 1
-+#define DC__NUM_AUDIO_INPUT_ENDPOINTS 0
-+#define DC__NUM_AUDIO_INPUT_ENDPOINTS__0 1
-+#define DC__NUM_AUDIO_INPUT_ENDPOINTS__MAX 8
-+#define DC__NUM_AUDIO_INPUT_ENDPOINTS__MAX__8 1
-+#define DC__NUM_CURSOR 1
-+#define DC__NUM_CURSOR__1 1
-+#define DC__NUM_CURSOR__0_PRESENT 1
-+#define DC__NUM_CURSOR__MAX 2
-+#define DC__NUM_CURSOR__MAX__2 1
-+#define DC__DIGITAL_BYPASS_PRESENT 0
-+#define DC__DIGITAL_BYPASS_PRESENT__0 1
-+#define DC__HCID_HWMAJVER 1
-+#define DC__HCID_HWMAJVER__1 1
-+#define DC__HCID_HWMINVER 0
-+#define DC__HCID_HWMINVER__0 1
-+#define DC__HCID_HWREV 0
-+#define DC__HCID_HWREV__0 1
-+#define DC__ROMSTRAP_PRESENT 0
-+#define DC__ROMSTRAP_PRESENT__0 1
-+#define DC__NUM_RBBMIF_DECODES 30
-+#define DC__NUM_RBBMIF_DECODES__30 1
-+#define DC__NUM_DBG_REGS 36
-+#define DC__NUM_DBG_REGS__36 1
-+#define DC__NUM_PIPES_UNDERLAY 0
-+#define DC__NUM_PIPES_UNDERLAY__0 1
-+#define DC__NUM_PIPES_UNDERLAY__MAX 2
-+#define DC__NUM_PIPES_UNDERLAY__MAX__2 1
-+#define DC__NUM_VCE_ENGINE 1
-+#define DC__NUM_VCE_ENGINE__1 1
-+#define DC__NUM_VCE_ENGINE__0_PRESENT 1
-+#define DC__NUM_VCE_ENGINE__MAX 2
-+#define DC__NUM_VCE_ENGINE__MAX__2 1
-+#define DC__OTG_EXTERNAL_SYNC_PRESENT 0
-+#define DC__OTG_EXTERNAL_SYNC_PRESENT__0 1
-+#define DC__OTG_CRC_PRESENT 1
-+#define DC__OTG_CRC_PRESENT__1 1
-+#define DC__VIP_PRESENT 0
-+#define DC__VIP_PRESENT__0 1
-+#define DC__DTMTEST_PRESENT 0
-+#define DC__DTMTEST_PRESENT__0 1
-+#define DC__POWER_GATE_PRESENT 1
-+#define DC__POWER_GATE_PRESENT__1 1
-+#define DC__MEM_PG 1
-+#define DC__MEM_PG__1 1
-+#define DC__FMT_SRC_SEL_PRESENT 0
-+#define DC__FMT_SRC_SEL_PRESENT__0 1
-+#define DC__DIG_FEATURES__HDMI_PRESENT 1
-+#define DC__DIG_FEATURES__HDMI_PRESENT__1 1
-+#define DC__DIG_FEATURES__DP_PRESENT 1
-+#define DC__DIG_FEATURES__DP_PRESENT__1 1
-+#define DC__DIG_FEATURES__DP_MST_PRESENT 1
-+#define DC__DIG_FEATURES__DP_MST_PRESENT__1 1
-+#define DC__DIG_LP_FEATURES__HDMI_PRESENT 0
-+#define DC__DIG_LP_FEATURES__HDMI_PRESENT__0 1
-+#define DC__DIG_LP_FEATURES__DP_PRESENT 1
-+#define DC__DIG_LP_FEATURES__DP_PRESENT__1 1
-+#define DC__DIG_LP_FEATURES__DP_MST_PRESENT 0
-+#define DC__DIG_LP_FEATURES__DP_MST_PRESENT__0 1
-+#define DC__DIG_RESYNC_FIFO_SIZE 14
-+#define DC__DIG_RESYNC_FIFO_SIZE__14 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__0_PRESENT 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__1_PRESENT 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__2_PRESENT 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__3_PRESENT 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__4_PRESENT 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__5_PRESENT 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__6_PRESENT 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__7_PRESENT 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__8_PRESENT 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__9_PRESENT 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__10_PRESENT 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__11_PRESENT 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__12_PRESENT 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__13_PRESENT 1
-+#define DC__DIG_RESYNC_FIFO_SIZE__MAX 16
-+#define DC__DIG_RESYNC_FIFO_SIZE__MAX__16 1
-+#define DC__DAC_RESYNC_FIFO_SIZE 12
-+#define DC__DAC_RESYNC_FIFO_SIZE__12 1
-+#define DC__DAC_RESYNC_FIFO_SIZE__0_PRESENT 1
-+#define DC__DAC_RESYNC_FIFO_SIZE__1_PRESENT 1
-+#define DC__DAC_RESYNC_FIFO_SIZE__2_PRESENT 1
-+#define DC__DAC_RESYNC_FIFO_SIZE__3_PRESENT 1
-+#define DC__DAC_RESYNC_FIFO_SIZE__4_PRESENT 1
-+#define DC__DAC_RESYNC_FIFO_SIZE__5_PRESENT 1
-+#define DC__DAC_RESYNC_FIFO_SIZE__6_PRESENT 1
-+#define DC__DAC_RESYNC_FIFO_SIZE__7_PRESENT 1
-+#define DC__DAC_RESYNC_FIFO_SIZE__8_PRESENT 1
-+#define DC__DAC_RESYNC_FIFO_SIZE__9_PRESENT 1
-+#define DC__DAC_RESYNC_FIFO_SIZE__10_PRESENT 1
-+#define DC__DAC_RESYNC_FIFO_SIZE__11_PRESENT 1
-+#define DC__DAC_RESYNC_FIFO_SIZE__MAX 16
-+#define DC__DAC_RESYNC_FIFO_SIZE__MAX__16 1
-+#define DC__DVO_RESYNC_FIFO_SIZE 12
-+#define DC__DVO_RESYNC_FIFO_SIZE__12 1
-+#define DC__DVO_RESYNC_FIFO_SIZE__0_PRESENT 1
-+#define DC__DVO_RESYNC_FIFO_SIZE__1_PRESENT 1
-+#define DC__DVO_RESYNC_FIFO_SIZE__2_PRESENT 1
-+#define DC__DVO_RESYNC_FIFO_SIZE__3_PRESENT 1
-+#define DC__DVO_RESYNC_FIFO_SIZE__4_PRESENT 1
-+#define DC__DVO_RESYNC_FIFO_SIZE__5_PRESENT 1
-+#define DC__DVO_RESYNC_FIFO_SIZE__6_PRESENT 1
-+#define DC__DVO_RESYNC_FIFO_SIZE__7_PRESENT 1
-+#define DC__DVO_RESYNC_FIFO_SIZE__8_PRESENT 1
-+#define DC__DVO_RESYNC_FIFO_SIZE__9_PRESENT 1
-+#define DC__DVO_RESYNC_FIFO_SIZE__10_PRESENT 1
-+#define DC__DVO_RESYNC_FIFO_SIZE__11_PRESENT 1
-+#define DC__DVO_RESYNC_FIFO_SIZE__MAX 16
-+#define DC__DVO_RESYNC_FIFO_SIZE__MAX__16 1
-+#define DC__MEM_CDC_PRESENT 1
-+#define DC__MEM_CDC_PRESENT__1 1
-+#define DC__NUM_HPD 4
-+#define DC__NUM_HPD__4 1
-+#define DC__NUM_HPD__0_PRESENT 1
-+#define DC__NUM_HPD__1_PRESENT 1
-+#define DC__NUM_HPD__2_PRESENT 1
-+#define DC__NUM_HPD__3_PRESENT 1
-+#define DC__NUM_HPD__MAX 6
-+#define DC__NUM_HPD__MAX__6 1
-+#define DC__NUM_DDC_PAIRS 4
-+#define DC__NUM_DDC_PAIRS__4 1
-+#define DC__NUM_DDC_PAIRS__0_PRESENT 1
-+#define DC__NUM_DDC_PAIRS__1_PRESENT 1
-+#define DC__NUM_DDC_PAIRS__2_PRESENT 1
-+#define DC__NUM_DDC_PAIRS__3_PRESENT 1
-+#define DC__NUM_DDC_PAIRS__MAX 6
-+#define DC__NUM_DDC_PAIRS__MAX__6 1
-+#define DC__NUM_AUDIO_PLL 0
-+#define DC__NUM_AUDIO_PLL__0 1
-+#define DC__NUM_AUDIO_PLL__MAX 2
-+#define DC__NUM_AUDIO_PLL__MAX__2 1
-+#define DC__NUM_PIXEL_PLL 1
-+#define DC__NUM_PIXEL_PLL__1 1
-+#define DC__NUM_PIXEL_PLL__0_PRESENT 1
-+#define DC__NUM_PIXEL_PLL__MAX 4
-+#define DC__NUM_PIXEL_PLL__MAX__4 1
-+#define DC__NUM_CASCADED_PLL 0
-+#define DC__NUM_CASCADED_PLL__0 1
-+#define DC__NUM_CASCADED_PLL__MAX 3
-+#define DC__NUM_CASCADED_PLL__MAX__3 1
-+#define DC__PIXCLK_FROM_PHYPLL 1
-+#define DC__PIXCLK_FROM_PHYPLL__1 1
-+#define DC__NB_STUTTER_MODE_PRESENT 0
-+#define DC__NB_STUTTER_MODE_PRESENT__0 1
-+#define DC__I2S0_AND_SPDIF0_PRESENT 0
-+#define DC__I2S0_AND_SPDIF0_PRESENT__0 1
-+#define DC__I2S1_PRESENT 0
-+#define DC__I2S1_PRESENT__0 1
-+#define DC__SPDIF1_PRESENT 0
-+#define DC__SPDIF1_PRESENT__0 1
-+#define DC__DSI_PRESENT 0
-+#define DC__DSI_PRESENT__0 1
-+#define DC__DACA_PRESENT 0
-+#define DC__DACA_PRESENT__0 1
-+#define DC__DACB_PRESENT 0
-+#define DC__DACB_PRESENT__0 1
-+#define DC__NUM_PIPES 4
-+#define DC__NUM_PIPES__4 1
-+#define DC__NUM_PIPES__0_PRESENT 1
-+#define DC__NUM_PIPES__1_PRESENT 1
-+#define DC__NUM_PIPES__2_PRESENT 1
-+#define DC__NUM_PIPES__3_PRESENT 1
-+#define DC__NUM_PIPES__MAX 6
-+#define DC__NUM_PIPES__MAX__6 1
-+#define DC__NUM_DIG_LP 0
-+#define DC__NUM_DIG_LP__0 1
-+#define DC__NUM_DIG_LP__MAX 2
-+#define DC__NUM_DIG_LP__MAX__2 1
-+#define DC__DPDEBUG_PRESENT 0
-+#define DC__DPDEBUG_PRESENT__0 1
-+#define DC__DISPLAY_WB_PRESENT 1
-+#define DC__DISPLAY_WB_PRESENT__1 1
-+#define DC__NUM_CWB 0
-+#define DC__NUM_CWB__0 1
-+#define DC__NUM_CWB__MAX 2
-+#define DC__NUM_CWB__MAX__2 1
-+#define DC__MVP_PRESENT 0
-+#define DC__MVP_PRESENT__0 1
-+#define DC__DVO_PRESENT 0
-+#define DC__DVO_PRESENT__0 1
-+#define DC__ABM_PRESENT 0
-+#define DC__ABM_PRESENT__0 1
-+#define DC__BPHYC_PLL_PRESENT 0
-+#define DC__BPHYC_PLL_PRESENT__0 1
-+#define DC__BPHYC_UNIPHY_PRESENT 0
-+#define DC__BPHYC_UNIPHY_PRESENT__0 1
-+#define DC__PHY_BROADCAST_PRESENT 0
-+#define DC__PHY_BROADCAST_PRESENT__0 1
-+#define DC__NUM_OF_DCRX_SD 0
-+#define DC__NUM_OF_DCRX_SD__0 1
-+#define DC__DVO_17BIT_MAPPING 0
-+#define DC__DVO_17BIT_MAPPING__0 1
-+#define DC__AVSYNC_PRESENT 0
-+#define DC__AVSYNC_PRESENT__0 1
-+#define DC__NUM_OF_DCRX_PORTS 0
-+#define DC__NUM_OF_DCRX_PORTS__0 1
-+#define DC__NUM_OF_DCRX_PORTS__MAX 1
-+#define DC__NUM_OF_DCRX_PORTS__MAX__1 1
-+#define DC__NUM_PHY 4
-+#define DC__NUM_PHY__4 1
-+#define DC__NUM_PHY__0_PRESENT 1
-+#define DC__NUM_PHY__1_PRESENT 1
-+#define DC__NUM_PHY__2_PRESENT 1
-+#define DC__NUM_PHY__3_PRESENT 1
-+#define DC__NUM_PHY__MAX 7
-+#define DC__NUM_PHY__MAX__7 1
-+#define DC__NUM_PHY_LP 0
-+#define DC__NUM_PHY_LP__0 1
-+#define DC__NUM_PHY_LP__MAX 2
-+#define DC__NUM_PHY_LP__MAX__2 1
-+#define DC__SYNC_CELL vid_sync_gf14lpp
-+#define DC__SYNC_CELL__VID_SYNC_GF14LPP 1
-+#define DC__USE_NEW_VSS 1
-+#define DC__USE_NEW_VSS__1 1
-+#define DC__SYNC_CELL_DISPCLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_DISPCLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_DVOCLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_DVOCLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_PIXCLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_PIXCLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_SYMCLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_SYMCLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_DPPCLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_DPPCLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_DPREFCLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_DPREFCLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_REFCLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_REFCLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_PCIE_REFCLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_PCIE_REFCLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_MVPCLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_MVPCLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_SCLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_SCLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_DCEFCLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_DCEFCLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_AMCLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_AMCLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_DSICLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_DSICLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_BYTECLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_BYTECLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_ESCCLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_ESCCLK_NUM_LATCHES__6 1
-+#define DC__SYNC_CELL_DB_CLK_NUM_LATCHES 6
-+#define DC__SYNC_CELL_DB_CLK_NUM_LATCHES__6 1
-+#define UNIPHYA_PRESENT 1
-+#define UNIPHYA_PRESENT__1 1
-+#define DC__UNIPHYA_PRESENT 1
-+#define DC__UNIPHYA_PRESENT__1 1
-+#define UNIPHYB_PRESENT 1
-+#define UNIPHYB_PRESENT__1 1
-+#define DC__UNIPHYB_PRESENT 1
-+#define DC__UNIPHYB_PRESENT__1 1
-+#define UNIPHYC_PRESENT 1
-+#define UNIPHYC_PRESENT__1 1
-+#define DC__UNIPHYC_PRESENT 1
-+#define DC__UNIPHYC_PRESENT__1 1
-+#define UNIPHYD_PRESENT 1
-+#define UNIPHYD_PRESENT__1 1
-+#define DC__UNIPHYD_PRESENT 1
-+#define DC__UNIPHYD_PRESENT__1 1
-+#define UNIPHYE_PRESENT 0
-+#define UNIPHYE_PRESENT__0 1
-+#define DC__UNIPHYE_PRESENT 0
-+#define DC__UNIPHYE_PRESENT__0 1
-+#define UNIPHYF_PRESENT 0
-+#define UNIPHYF_PRESENT__0 1
-+#define DC__UNIPHYF_PRESENT 0
-+#define DC__UNIPHYF_PRESENT__0 1
-+#define UNIPHYG_PRESENT 0
-+#define UNIPHYG_PRESENT__0 1
-+#define DC__UNIPHYG_PRESENT 0
-+#define DC__UNIPHYG_PRESENT__0 1
-+#define DC__TMDS_LINK tmds_link_dual
-+#define DC__TMDS_LINK__TMDS_LINK_DUAL 1
-+#define DC__WBSCL_PIXBW 8
-+#define DC__WBSCL_PIXBW__8 1
-+#define DC__DWB_CSC_PRESENT 0
-+#define DC__DWB_CSC_PRESENT__0 1
-+#define DC__DWB_LUMA_SCL_PRESENT 0
-+#define DC__DWB_LUMA_SCL_PRESENT__0 1
-+#define DC__DENTIST_INTERFACE_PRESENT 1
-+#define DC__DENTIST_INTERFACE_PRESENT__1 1
-+#define DC__GENERICA_PRESENT 1
-+#define DC__GENERICA_PRESENT__1 1
-+#define DC__GENERICB_PRESENT 1
-+#define DC__GENERICB_PRESENT__1 1
-+#define DC__GENERICC_PRESENT 0
-+#define DC__GENERICC_PRESENT__0 1
-+#define DC__GENERICD_PRESENT 0
-+#define DC__GENERICD_PRESENT__0 1
-+#define DC__GENERICE_PRESENT 0
-+#define DC__GENERICE_PRESENT__0 1
-+#define DC__GENERICF_PRESENT 0
-+#define DC__GENERICF_PRESENT__0 1
-+#define DC__GENERICG_PRESENT 0
-+#define DC__GENERICG_PRESENT__0 1
-+#define DC__UNIPHY_VOLTAGE_MODE 1
-+#define DC__UNIPHY_VOLTAGE_MODE__1 1
-+#define DC__BLON_TYPE dedicated
-+#define DC__BLON_TYPE__DEDICATED 1
-+#define DC__UNIPHY_STAGGER_CH_PRESENT 1
-+#define DC__UNIPHY_STAGGER_CH_PRESENT__1 1
-+#define DC__XDMA_PRESENT 0
-+#define DC__XDMA_PRESENT__0 1
-+#define XDMA__PRESENT 0
-+#define XDMA__PRESENT__0 1
-+#define DC__DP_MEM_PG 0
-+#define DC__DP_MEM_PG__0 1
-+#define DP__MEM_PG 0
-+#define DP__MEM_PG__0 1
-+#define DC__AFMT_MEM_PG 0
-+#define DC__AFMT_MEM_PG__0 1
-+#define AFMT__MEM_PG 0
-+#define AFMT__MEM_PG__0 1
-+#define DC__HDMI_MEM_PG 0
-+#define DC__HDMI_MEM_PG__0 1
-+#define HDMI__MEM_PG 0
-+#define HDMI__MEM_PG__0 1
-+#define DC__I2C_MEM_PG 0
-+#define DC__I2C_MEM_PG__0 1
-+#define I2C__MEM_PG 0
-+#define I2C__MEM_PG__0 1
-+#define DC__DSCL_MEM_PG 0
-+#define DC__DSCL_MEM_PG__0 1
-+#define DSCL__MEM_PG 0
-+#define DSCL__MEM_PG__0 1
-+#define DC__CM_MEM_PG 0
-+#define DC__CM_MEM_PG__0 1
-+#define CM__MEM_PG 0
-+#define CM__MEM_PG__0 1
-+#define DC__OBUF_MEM_PG 0
-+#define DC__OBUF_MEM_PG__0 1
-+#define OBUF__MEM_PG 0
-+#define OBUF__MEM_PG__0 1
-+#define DC__WBIF_MEM_PG 1
-+#define DC__WBIF_MEM_PG__1 1
-+#define WBIF__MEM_PG 1
-+#define WBIF__MEM_PG__1 1
-+#define DC__VGA_MEM_PG 0
-+#define DC__VGA_MEM_PG__0 1
-+#define VGA__MEM_PG 0
-+#define VGA__MEM_PG__0 1
-+#define DC__FMT_MEM_PG 0
-+#define DC__FMT_MEM_PG__0 1
-+#define FMT__MEM_PG 0
-+#define FMT__MEM_PG__0 1
-+#define DC__ODM_MEM_PG 0
-+#define DC__ODM_MEM_PG__0 1
-+#define ODM__MEM_PG 0
-+#define ODM__MEM_PG__0 1
-+#define DC__DSI_MEM_PG 0
-+#define DC__DSI_MEM_PG__0 1
-+#define DSI__MEM_PG 0
-+#define DSI__MEM_PG__0 1
-+#define DC__AZ_MEM_PG 1
-+#define DC__AZ_MEM_PG__1 1
-+#define AZ__MEM_PG 1
-+#define AZ__MEM_PG__1 1
-+#define DC__WBSCL_MEM1P1024X64QS_MEM_PG 1
-+#define DC__WBSCL_MEM1P1024X64QS_MEM_PG__1 1
-+#define WBSCL_MEM1P1024X64QS__MEM_PG 1
-+#define WBSCL_MEM1P1024X64QS__MEM_PG__1 1
-+#define DC__WBSCL_MEM1P528X64QS_MEM_PG 1
-+#define DC__WBSCL_MEM1P528X64QS_MEM_PG__1 1
-+#define WBSCL_MEM1P528X64QS__MEM_PG 1
-+#define WBSCL_MEM1P528X64QS__MEM_PG__1 1
-+#define DC__DMCU_MEM1P1024X32BQS_MEM_PG 1
-+#define DC__DMCU_MEM1P1024X32BQS_MEM_PG__1 1
-+#define DMCU_MEM1P1024X32BQS__MEM_PG 1
-+#define DMCU_MEM1P1024X32BQS__MEM_PG__1 1
-+#define DC__HUBBUB_SDP_TAG_INT_MEM_PG 0
-+#define DC__HUBBUB_SDP_TAG_INT_MEM_PG__0 1
-+#define HUBBUB_SDP_TAG_INT__MEM_PG 0
-+#define HUBBUB_SDP_TAG_INT__MEM_PG__0 1
-+#define DC__HUBBUB_SDP_TAG_EXT_MEM_PG 0
-+#define DC__HUBBUB_SDP_TAG_EXT_MEM_PG__0 1
-+#define HUBBUB_SDP_TAG_EXT__MEM_PG 0
-+#define HUBBUB_SDP_TAG_EXT__MEM_PG__0 1
-+#define DC__HUBBUB_RET_ZERO_MEM_PG 0
-+#define DC__HUBBUB_RET_ZERO_MEM_PG__0 1
-+#define HUBBUB_RET_ZERO__MEM_PG 0
-+#define HUBBUB_RET_ZERO__MEM_PG__0 1
-+#define DC__HUBBUB_RET_ROB_MEM_PG 0
-+#define DC__HUBBUB_RET_ROB_MEM_PG__0 1
-+#define HUBBUB_RET_ROB__MEM_PG 0
-+#define HUBBUB_RET_ROB__MEM_PG__0 1
-+#define DC__HUBPRET_CUR_ROB_MEM_PG 0
-+#define DC__HUBPRET_CUR_ROB_MEM_PG__0 1
-+#define HUBPRET_CUR_ROB__MEM_PG 0
-+#define HUBPRET_CUR_ROB__MEM_PG__0 1
-+#define DC__HUBPRET_CUR_CDC_MEM_PG 0
-+#define DC__HUBPRET_CUR_CDC_MEM_PG__0 1
-+#define HUBPRET_CUR_CDC__MEM_PG 0
-+#define HUBPRET_CUR_CDC__MEM_PG__0 1
-+#define DC__HUBPREQ_MPTE_MEM_PG 0
-+#define DC__HUBPREQ_MPTE_MEM_PG__0 1
-+#define HUBPREQ_MPTE__MEM_PG 0
-+#define HUBPREQ_MPTE__MEM_PG__0 1
-+#define DC__HUBPREQ_META_MEM_PG 0
-+#define DC__HUBPREQ_META_MEM_PG__0 1
-+#define HUBPREQ_META__MEM_PG 0
-+#define HUBPREQ_META__MEM_PG__0 1
-+#define DC__HUBPREQ_DPTE_MEM_PG 0
-+#define DC__HUBPREQ_DPTE_MEM_PG__0 1
-+#define HUBPREQ_DPTE__MEM_PG 0
-+#define HUBPREQ_DPTE__MEM_PG__0 1
-+#define DC__HUBPRET_DET_MEM_PG 0
-+#define DC__HUBPRET_DET_MEM_PG__0 1
-+#define HUBPRET_DET__MEM_PG 0
-+#define HUBPRET_DET__MEM_PG__0 1
-+#define DC__HUBPRET_PIX_CDC_MEM_PG 0
-+#define DC__HUBPRET_PIX_CDC_MEM_PG__0 1
-+#define HUBPRET_PIX_CDC__MEM_PG 0
-+#define HUBPRET_PIX_CDC__MEM_PG__0 1
-+#define DC__TOP_BLKS__DCCG 1
-+#define DC__TOP_BLKS__DCHUBBUB 1
-+#define DC__TOP_BLKS__DCHUBP 1
-+#define DC__TOP_BLKS__HDA 1
-+#define DC__TOP_BLKS__DIO 1
-+#define DC__TOP_BLKS__DCIO 1
-+#define DC__TOP_BLKS__DMU 1
-+#define DC__TOP_BLKS__DPP 1
-+#define DC__TOP_BLKS__MPC 1
-+#define DC__TOP_BLKS__OPP 1
-+#define DC__TOP_BLKS__OPTC 1
-+#define DC__TOP_BLKS__MMHUBBUB 1
-+#define DC__TOP_BLKS__WB 1
-+#define DC__TOP_BLKS__MAX 13
-+#define DC__TOP_BLKS__MAX__13 1
-+#define DC__DCHUBP_DPP_SF_PIXEL_CREDITS 9
-+#define DC__DCHUBP_DPP_SF_PIXEL_CREDITS__9 1
-+#define DC__DPP_MPC_SF_PIXEL_CREDITS 9
-+#define DC__DPP_MPC_SF_PIXEL_CREDITS__9 1
-+#define DC__MPC_OPP_SF_PIXEL_CREDITS 8
-+#define DC__MPC_OPP_SF_PIXEL_CREDITS__8 1
-+#define DC__OPP_OPTC_SF_PIXEL_CREDITS 8
-+#define DC__OPP_OPTC_SF_PIXEL_CREDITS__8 1
-+#define DC__SFR_SFT_ROUND_TRIP_DELAY 5
-+#define DC__SFR_SFT_ROUND_TRIP_DELAY__5 1
-+#define DC__REPEATER_PROJECT_MAX 8
-+#define DC__REPEATER_PROJECT_MAX__8 1
-+#define DC__SURFACE_422_CAPABLE 0
-+#define DC__SURFACE_422_CAPABLE__0 1
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h.0130~	2017-12-14 06:39:58.424903574 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h	2017-12-14 06:39:58.424903574 +0100
-@@ -0,0 +1,111 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DISPLAY_MODE_ENUMS_H__
-+#define __DISPLAY_MODE_ENUMS_H__
-+
-+enum output_encoder_class {
-+	dm_dp = 0, dm_hdmi = 1, dm_wb = 2, dm_edp
-+};
-+enum output_format_class {
-+	dm_444 = 0, dm_420 = 1, dm_n422, dm_s422
-+};
-+enum source_format_class {
-+	dm_444_16 = 0,
-+	dm_444_32 = 1,
-+	dm_444_64 = 2,
-+	dm_420_8 = 3,
-+	dm_420_10 = 4,
-+	dm_422_8 = 5,
-+	dm_422_10 = 6,
-+	dm_444_8 = 7,
-+	dm_mono_8,
-+	dm_mono_16
-+};
-+enum output_bpc_class {
-+	dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4
-+};
-+enum scan_direction_class {
-+	dm_horz = 0, dm_vert = 1
-+};
-+enum dm_swizzle_mode {
-+	dm_sw_linear = 0,
-+	dm_sw_256b_s = 1,
-+	dm_sw_256b_d = 2,
-+	dm_sw_SPARE_0 = 3,
-+	dm_sw_SPARE_1 = 4,
-+	dm_sw_4kb_s = 5,
-+	dm_sw_4kb_d = 6,
-+	dm_sw_SPARE_2 = 7,
-+	dm_sw_SPARE_3 = 8,
-+	dm_sw_64kb_s = 9,
-+	dm_sw_64kb_d = 10,
-+	dm_sw_SPARE_4 = 11,
-+	dm_sw_SPARE_5 = 12,
-+	dm_sw_var_s = 13,
-+	dm_sw_var_d = 14,
-+	dm_sw_SPARE_6 = 15,
-+	dm_sw_SPARE_7 = 16,
-+	dm_sw_64kb_s_t = 17,
-+	dm_sw_64kb_d_t = 18,
-+	dm_sw_SPARE_10 = 19,
-+	dm_sw_SPARE_11 = 20,
-+	dm_sw_4kb_s_x = 21,
-+	dm_sw_4kb_d_x = 22,
-+	dm_sw_SPARE_12 = 23,
-+	dm_sw_SPARE_13 = 24,
-+	dm_sw_64kb_s_x = 25,
-+	dm_sw_64kb_d_x = 26,
-+	dm_sw_SPARE_14 = 27,
-+	dm_sw_SPARE_15 = 28,
-+	dm_sw_var_s_x = 29,
-+	dm_sw_var_d_x = 30,
-+	dm_sw_64kb_r_x,
-+	dm_sw_gfx7_2d_thin_lvp,
-+	dm_sw_gfx7_2d_thin_gl
-+};
-+enum lb_depth {
-+	dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16
-+};
-+enum voltage_state {
-+	dm_vmin = 0, dm_vmid = 1, dm_vnom = 2, dm_vmax = 3
-+};
-+enum source_macro_tile_size {
-+	dm_4k_tile = 0, dm_64k_tile = 1, dm_256k_tile = 2
-+};
-+enum cursor_bpp {
-+	dm_cur_2bit = 0, dm_cur_32bit = 1, dm_cur_64bit = 2
-+};
-+enum clock_change_support {
-+	dm_dram_clock_change_uninitialized = 0,
-+	dm_dram_clock_change_vactive,
-+	dm_dram_clock_change_vblank,
-+	dm_dram_clock_change_unsupported
-+};
-+
-+enum output_standard {
-+	dm_std_uninitialized = 0, dm_std_cvtr2, dm_std_cvt
-+};
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c.0130~	2017-12-14 06:39:58.425903574 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c	2017-12-14 06:39:58.425903574 +0100
-@@ -0,0 +1,138 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "display_mode_lib.h"
-+#include "dc_features.h"
-+
-+static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum dml_project project)
-+{
-+	if (project == DML_PROJECT_RAVEN1) {
-+		soc->sr_exit_time_us = 9.0;
-+		soc->sr_enter_plus_exit_time_us = 11.0;
-+		soc->urgent_latency_us = 4.0;
-+		soc->writeback_latency_us = 12.0;
-+		soc->ideal_dram_bw_after_urgent_percent = 80.0;
-+		soc->max_request_size_bytes = 256;
-+
-+		soc->vmin.dcfclk_mhz = 300.0;
-+		soc->vmin.dispclk_mhz = 608.0;
-+		soc->vmin.dppclk_mhz = 435.0;
-+		soc->vmin.dram_bw_per_chan_gbps = 12.8;
-+		soc->vmin.phyclk_mhz = 540.0;
-+		soc->vmin.socclk_mhz = 208.0;
-+
-+		soc->vmid.dcfclk_mhz = 600.0;
-+		soc->vmid.dispclk_mhz = 661.0;
-+		soc->vmid.dppclk_mhz = 661.0;
-+		soc->vmid.dram_bw_per_chan_gbps = 12.8;
-+		soc->vmid.phyclk_mhz = 540.0;
-+		soc->vmid.socclk_mhz = 208.0;
-+
-+		soc->vnom.dcfclk_mhz = 600.0;
-+		soc->vnom.dispclk_mhz = 661.0;
-+		soc->vnom.dppclk_mhz = 661.0;
-+		soc->vnom.dram_bw_per_chan_gbps = 38.4;
-+		soc->vnom.phyclk_mhz = 810;
-+		soc->vnom.socclk_mhz = 208.0;
-+
-+		soc->vmax.dcfclk_mhz = 600.0;
-+		soc->vmax.dispclk_mhz = 1086.0;
-+		soc->vmax.dppclk_mhz = 661.0;
-+		soc->vmax.dram_bw_per_chan_gbps = 38.4;
-+		soc->vmax.phyclk_mhz = 810.0;
-+		soc->vmax.socclk_mhz = 208.0;
-+
-+		soc->downspread_percent = 0.5;
-+		soc->dram_page_open_time_ns = 50.0;
-+		soc->dram_rw_turnaround_time_ns = 17.5;
-+		soc->dram_return_buffer_per_channel_bytes = 8192;
-+		soc->round_trip_ping_latency_dcfclk_cycles = 128;
-+		soc->urgent_out_of_order_return_per_channel_bytes = 256;
-+		soc->channel_interleave_bytes = 256;
-+		soc->num_banks = 8;
-+		soc->num_chans = 2;
-+		soc->vmm_page_size_bytes = 4096;
-+		soc->dram_clock_change_latency_us = 17.0;
-+		soc->writeback_dram_clock_change_latency_us = 23.0;
-+		soc->return_bus_width_bytes = 64;
-+	} else {
-+		BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
-+	}
-+}
-+
-+static void set_ip_params(struct _vcs_dpi_ip_params_st *ip, enum dml_project project)
-+{
-+	if (project == DML_PROJECT_RAVEN1) {
-+		ip->rob_buffer_size_kbytes = 64;
-+		ip->det_buffer_size_kbytes = 164;
-+		ip->dpte_buffer_size_in_pte_reqs = 42;
-+		ip->dpp_output_buffer_pixels = 2560;
-+		ip->opp_output_buffer_lines = 1;
-+		ip->pixel_chunk_size_kbytes = 8;
-+		ip->pte_enable = 1;
-+		ip->pte_chunk_size_kbytes = 2;
-+		ip->meta_chunk_size_kbytes = 2;
-+		ip->writeback_chunk_size_kbytes = 2;
-+		ip->line_buffer_size_bits = 589824;
-+		ip->max_line_buffer_lines = 12;
-+		ip->IsLineBufferBppFixed = 0;
-+		ip->LineBufferFixedBpp = -1;
-+		ip->writeback_luma_buffer_size_kbytes = 12;
-+		ip->writeback_chroma_buffer_size_kbytes = 8;
-+		ip->max_num_dpp = 4;
-+		ip->max_num_wb = 2;
-+		ip->max_dchub_pscl_bw_pix_per_clk = 4;
-+		ip->max_pscl_lb_bw_pix_per_clk = 2;
-+		ip->max_lb_vscl_bw_pix_per_clk = 4;
-+		ip->max_vscl_hscl_bw_pix_per_clk = 4;
-+		ip->max_hscl_ratio = 4;
-+		ip->max_vscl_ratio = 4;
-+		ip->hscl_mults = 4;
-+		ip->vscl_mults = 4;
-+		ip->max_hscl_taps = 8;
-+		ip->max_vscl_taps = 8;
-+		ip->dispclk_ramp_margin_percent = 1;
-+		ip->underscan_factor = 1.10;
-+		ip->min_vblank_lines = 14;
-+		ip->dppclk_delay_subtotal = 90;
-+		ip->dispclk_delay_subtotal = 42;
-+		ip->dcfclk_cstate_latency = 10;
-+		ip->max_inter_dcn_tile_repeaters = 8;
-+		ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0;
-+		ip->bug_forcing_LC_req_same_size_fixed = 0;
-+	} else {
-+		BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
-+	}
-+}
-+
-+void dml_init_instance(struct display_mode_lib *lib, enum dml_project project)
-+{
-+	if (lib->project != project) {
-+		set_soc_bounding_box(&lib->soc, project);
-+		set_ip_params(&lib->ip, project);
-+		lib->project = project;
-+	}
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h.0130~	2017-12-14 06:39:58.425903574 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h	2017-12-14 06:39:58.425903574 +0100
-@@ -0,0 +1,50 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DISPLAY_MODE_LIB_H__
-+#define __DISPLAY_MODE_LIB_H__
-+
-+
-+#include "dml_common_defs.h"
-+#include "soc_bounding_box.h"
-+#include "display_mode_vba.h"
-+#include "display_rq_dlg_calc.h"
-+#include "dml1_display_rq_dlg_calc.h"
-+
-+enum dml_project {
-+	DML_PROJECT_UNDEFINED,
-+	DML_PROJECT_RAVEN1
-+};
-+
-+struct display_mode_lib {
-+	struct _vcs_dpi_ip_params_st ip;
-+	struct _vcs_dpi_soc_bounding_box_st soc;
-+	enum dml_project project;
-+	struct vba_vars_st vba;
-+	struct dal_logger *logger;
-+};
-+
-+void dml_init_instance(struct display_mode_lib *lib, enum dml_project project);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h.0130~	2017-12-14 06:39:58.425903574 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h	2017-12-14 06:39:58.425903574 +0100
-@@ -0,0 +1,557 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DISPLAY_MODE_STRUCTS_H__
-+#define __DISPLAY_MODE_STRUCTS_H__
-+
-+typedef struct _vcs_dpi_voltage_scaling_st	voltage_scaling_st;
-+typedef struct _vcs_dpi_soc_bounding_box_st	soc_bounding_box_st;
-+typedef struct _vcs_dpi_ip_params_st	ip_params_st;
-+typedef struct _vcs_dpi_display_pipe_source_params_st	display_pipe_source_params_st;
-+typedef struct _vcs_dpi_display_output_params_st	display_output_params_st;
-+typedef struct _vcs_dpi_display_bandwidth_st	display_bandwidth_st;
-+typedef struct _vcs_dpi_scaler_ratio_depth_st	scaler_ratio_depth_st;
-+typedef struct _vcs_dpi_scaler_taps_st	scaler_taps_st;
-+typedef struct _vcs_dpi_display_pipe_dest_params_st	display_pipe_dest_params_st;
-+typedef struct _vcs_dpi_display_pipe_params_st	display_pipe_params_st;
-+typedef struct _vcs_dpi_display_clocks_and_cfg_st	display_clocks_and_cfg_st;
-+typedef struct _vcs_dpi_display_e2e_pipe_params_st	display_e2e_pipe_params_st;
-+typedef struct _vcs_dpi_dchub_buffer_sizing_st	dchub_buffer_sizing_st;
-+typedef struct _vcs_dpi_watermarks_perf_st	watermarks_perf_st;
-+typedef struct _vcs_dpi_cstate_pstate_watermarks_st	cstate_pstate_watermarks_st;
-+typedef struct _vcs_dpi_wm_calc_pipe_params_st	wm_calc_pipe_params_st;
-+typedef struct _vcs_dpi_vratio_pre_st	vratio_pre_st;
-+typedef struct _vcs_dpi_display_data_rq_misc_params_st	display_data_rq_misc_params_st;
-+typedef struct _vcs_dpi_display_data_rq_sizing_params_st	display_data_rq_sizing_params_st;
-+typedef struct _vcs_dpi_display_data_rq_dlg_params_st	display_data_rq_dlg_params_st;
-+typedef struct _vcs_dpi_display_cur_rq_dlg_params_st	display_cur_rq_dlg_params_st;
-+typedef struct _vcs_dpi_display_rq_dlg_params_st	display_rq_dlg_params_st;
-+typedef struct _vcs_dpi_display_rq_sizing_params_st	display_rq_sizing_params_st;
-+typedef struct _vcs_dpi_display_rq_misc_params_st	display_rq_misc_params_st;
-+typedef struct _vcs_dpi_display_rq_params_st	display_rq_params_st;
-+typedef struct _vcs_dpi_display_dlg_regs_st	display_dlg_regs_st;
-+typedef struct _vcs_dpi_display_ttu_regs_st	display_ttu_regs_st;
-+typedef struct _vcs_dpi_display_data_rq_regs_st	display_data_rq_regs_st;
-+typedef struct _vcs_dpi_display_rq_regs_st	display_rq_regs_st;
-+typedef struct _vcs_dpi_display_dlg_sys_params_st	display_dlg_sys_params_st;
-+typedef struct _vcs_dpi_display_dlg_prefetch_param_st	display_dlg_prefetch_param_st;
-+typedef struct _vcs_dpi_display_pipe_clock_st	display_pipe_clock_st;
-+typedef struct _vcs_dpi_display_arb_params_st	display_arb_params_st;
-+
-+struct _vcs_dpi_voltage_scaling_st {
-+	int state;
-+	double dscclk_mhz;
-+	double dcfclk_mhz;
-+	double socclk_mhz;
-+	double dram_speed_mhz;
-+	double fabricclk_mhz;
-+	double dispclk_mhz;
-+	double dram_bw_per_chan_gbps;
-+	double phyclk_mhz;
-+	double dppclk_mhz;
-+};
-+
-+struct	_vcs_dpi_soc_bounding_box_st	{
-+	double	sr_exit_time_us;
-+	double	sr_enter_plus_exit_time_us;
-+	double	urgent_latency_us;
-+	double	writeback_latency_us;
-+	double	ideal_dram_bw_after_urgent_percent;
-+	unsigned int	max_request_size_bytes;
-+	struct _vcs_dpi_voltage_scaling_st	vmin;
-+	struct _vcs_dpi_voltage_scaling_st	vmid;
-+	struct _vcs_dpi_voltage_scaling_st	vnom;
-+	struct _vcs_dpi_voltage_scaling_st	vmax;
-+	double	downspread_percent;
-+	double	dram_page_open_time_ns;
-+	double	dram_rw_turnaround_time_ns;
-+	double	dram_return_buffer_per_channel_bytes;
-+	double	dram_channel_width_bytes;
-+	double fabric_datapath_to_dcn_data_return_bytes;
-+	double dcn_downspread_percent;
-+	double dispclk_dppclk_vco_speed_mhz;
-+	double dfs_vco_period_ps;
-+	unsigned int	round_trip_ping_latency_dcfclk_cycles;
-+	unsigned int	urgent_out_of_order_return_per_channel_bytes;
-+	unsigned int	channel_interleave_bytes;
-+	unsigned int	num_banks;
-+	unsigned int	num_chans;
-+	unsigned int	vmm_page_size_bytes;
-+	double	dram_clock_change_latency_us;
-+	double	writeback_dram_clock_change_latency_us;
-+	unsigned int	return_bus_width_bytes;
-+	unsigned int	voltage_override;
-+	double	xfc_bus_transport_time_us;
-+	double	xfc_xbuf_latency_tolerance_us;
-+	struct _vcs_dpi_voltage_scaling_st clock_limits[7];
-+};
-+
-+struct	_vcs_dpi_ip_params_st	{
-+	unsigned int	max_inter_dcn_tile_repeaters;
-+	unsigned int	num_dsc;
-+	unsigned int	odm_capable;
-+	unsigned int	rob_buffer_size_kbytes;
-+	unsigned int	det_buffer_size_kbytes;
-+	unsigned int	dpte_buffer_size_in_pte_reqs;
-+	unsigned int	pde_proc_buffer_size_64k_reqs;
-+	unsigned int	dpp_output_buffer_pixels;
-+	unsigned int	opp_output_buffer_lines;
-+	unsigned int	pixel_chunk_size_kbytes;
-+	unsigned char	pte_enable;
-+	unsigned int	pte_chunk_size_kbytes;
-+	unsigned int	meta_chunk_size_kbytes;
-+	unsigned int	writeback_chunk_size_kbytes;
-+	unsigned int	line_buffer_size_bits;
-+	unsigned int	max_line_buffer_lines;
-+	unsigned int	writeback_luma_buffer_size_kbytes;
-+	unsigned int	writeback_chroma_buffer_size_kbytes;
-+	unsigned int	writeback_chroma_line_buffer_width_pixels;
-+	unsigned int	max_page_table_levels;
-+	unsigned int	max_num_dpp;
-+	unsigned int	max_num_otg;
-+	unsigned int	cursor_chunk_size;
-+	unsigned int	cursor_buffer_size;
-+	unsigned int	max_num_wb;
-+	unsigned int	max_dchub_pscl_bw_pix_per_clk;
-+	unsigned int	max_pscl_lb_bw_pix_per_clk;
-+	unsigned int	max_lb_vscl_bw_pix_per_clk;
-+	unsigned int	max_vscl_hscl_bw_pix_per_clk;
-+	double	max_hscl_ratio;
-+	double	max_vscl_ratio;
-+	unsigned int	hscl_mults;
-+	unsigned int	vscl_mults;
-+	unsigned int	max_hscl_taps;
-+	unsigned int	max_vscl_taps;
-+	unsigned int	xfc_supported;
-+	unsigned int	ptoi_supported;
-+	unsigned int	xfc_fill_constant_bytes;
-+	double	dispclk_ramp_margin_percent;
-+	double	xfc_fill_bw_overhead_percent;
-+	double	underscan_factor;
-+	unsigned int	min_vblank_lines;
-+	unsigned int	dppclk_delay_subtotal;
-+	unsigned int	dispclk_delay_subtotal;
-+	unsigned int	dcfclk_cstate_latency;
-+	unsigned int	dppclk_delay_scl;
-+	unsigned int	dppclk_delay_scl_lb_only;
-+	unsigned int	dppclk_delay_cnvc_formatter;
-+	unsigned int	dppclk_delay_cnvc_cursor;
-+	unsigned int	is_line_buffer_bpp_fixed;
-+	unsigned int	line_buffer_fixed_bpp;
-+	unsigned int	dcc_supported;
-+
-+	unsigned int IsLineBufferBppFixed;
-+	unsigned int LineBufferFixedBpp;
-+	unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
-+	unsigned int bug_forcing_LC_req_same_size_fixed;
-+};
-+
-+struct _vcs_dpi_display_xfc_params_st {
-+	double xfc_tslv_vready_offset_us;
-+	double xfc_tslv_vupdate_width_us;
-+	double xfc_tslv_vupdate_offset_us;
-+	int xfc_slv_chunk_size_bytes;
-+};
-+
-+struct	_vcs_dpi_display_pipe_source_params_st	{
-+	int	source_format;
-+	unsigned char	dcc;
-+	unsigned int	dcc_override;
-+	unsigned int	dcc_rate;
-+	unsigned char	dcc_use_global;
-+	unsigned char	vm;
-+	unsigned char	vm_levels_force_en;
-+	unsigned int	vm_levels_force;
-+	int	source_scan;
-+	int	sw_mode;
-+	int	macro_tile_size;
-+	unsigned char	is_display_sw;
-+	unsigned int	viewport_width;
-+	unsigned int	viewport_height;
-+	unsigned int	viewport_y_y;
-+	unsigned int	viewport_y_c;
-+	unsigned int	viewport_width_c;
-+	unsigned int	viewport_height_c;
-+	unsigned int	data_pitch;
-+	unsigned int	data_pitch_c;
-+	unsigned int	meta_pitch;
-+	unsigned int	meta_pitch_c;
-+	unsigned int	cur0_src_width;
-+	int	cur0_bpp;
-+	unsigned int	cur1_src_width;
-+	int	cur1_bpp;
-+	int	num_cursors;
-+	unsigned char	is_hsplit;
-+	unsigned char	dynamic_metadata_enable;
-+	unsigned int	dynamic_metadata_lines_before_active;
-+	unsigned int	dynamic_metadata_xmit_bytes;
-+	unsigned int	hsplit_grp;
-+	unsigned char	xfc_enable;
-+	unsigned char	xfc_slave;
-+	struct _vcs_dpi_display_xfc_params_st xfc_params;
-+};
-+struct writeback_st {
-+	int wb_src_height;
-+	int wb_dst_width;
-+	int wb_dst_height;
-+	int wb_pixel_format;
-+	int wb_htaps_luma;
-+	int wb_vtaps_luma;
-+	int wb_htaps_chroma;
-+	int wb_vtaps_chroma;
-+	int wb_hratio;
-+	int wb_vratio;
-+};
-+
-+struct	_vcs_dpi_display_output_params_st	{
-+	int	dp_lanes;
-+	int	output_bpp;
-+	int	dsc_enable;
-+	int	wb_enable;
-+	int	output_bpc;
-+	int	output_type;
-+	int	output_format;
-+	int	output_standard;
-+	int	dsc_slices;
-+	struct writeback_st wb;
-+};
-+
-+struct	_vcs_dpi_display_bandwidth_st	{
-+	double	total_bw_consumed_gbps;
-+	double	guaranteed_urgent_return_bw_gbps;
-+};
-+
-+struct	_vcs_dpi_scaler_ratio_depth_st	{
-+	double	hscl_ratio;
-+	double	vscl_ratio;
-+	double	hscl_ratio_c;
-+	double	vscl_ratio_c;
-+	double	vinit;
-+	double	vinit_c;
-+	double	vinit_bot;
-+	double	vinit_bot_c;
-+	int	lb_depth;
-+	int	scl_enable;
-+};
-+
-+struct	_vcs_dpi_scaler_taps_st	{
-+	unsigned int	htaps;
-+	unsigned int	vtaps;
-+	unsigned int	htaps_c;
-+	unsigned int	vtaps_c;
-+};
-+
-+struct	_vcs_dpi_display_pipe_dest_params_st	{
-+	unsigned int	recout_width;
-+	unsigned int	recout_height;
-+	unsigned int	full_recout_width;
-+	unsigned int	full_recout_height;
-+	unsigned int	hblank_start;
-+	unsigned int	hblank_end;
-+	unsigned int	vblank_start;
-+	unsigned int	vblank_end;
-+	unsigned int	htotal;
-+	unsigned int	vtotal;
-+	unsigned int	vactive;
-+	unsigned int	hactive;
-+	unsigned int	vstartup_start;
-+	unsigned int	vupdate_offset;
-+	unsigned int	vupdate_width;
-+	unsigned int	vready_offset;
-+	unsigned char	interlaced;
-+	unsigned char	underscan;
-+	double	pixel_rate_mhz;
-+	unsigned char	synchronized_vblank_all_planes;
-+	unsigned char	otg_inst;
-+	unsigned char	odm_split_cnt;
-+	unsigned char	odm_combine;
-+};
-+
-+struct	_vcs_dpi_display_pipe_params_st	{
-+	display_pipe_source_params_st	src;
-+	display_pipe_dest_params_st	dest;
-+	scaler_ratio_depth_st	scale_ratio_depth;
-+	scaler_taps_st	scale_taps;
-+};
-+
-+struct	_vcs_dpi_display_clocks_and_cfg_st	{
-+	int	voltage;
-+	double	dppclk_mhz;
-+	double	refclk_mhz;
-+	double	dispclk_mhz;
-+	double	dcfclk_mhz;
-+	double	socclk_mhz;
-+};
-+
-+struct	_vcs_dpi_display_e2e_pipe_params_st	{
-+	display_pipe_params_st	pipe;
-+	display_output_params_st	dout;
-+	display_clocks_and_cfg_st	clks_cfg;
-+};
-+
-+struct	_vcs_dpi_dchub_buffer_sizing_st	{
-+	unsigned int	swath_width_y;
-+	unsigned int	swath_height_y;
-+	unsigned int	swath_height_c;
-+	unsigned int	detail_buffer_size_y;
-+};
-+
-+struct	_vcs_dpi_watermarks_perf_st	{
-+	double	stutter_eff_in_active_region_percent;
-+	double	urgent_latency_supported_us;
-+	double	non_urgent_latency_supported_us;
-+	double	dram_clock_change_margin_us;
-+	double	dram_access_eff_percent;
-+};
-+
-+struct	_vcs_dpi_cstate_pstate_watermarks_st	{
-+	double	cstate_exit_us;
-+	double	cstate_enter_plus_exit_us;
-+	double	pstate_change_us;
-+};
-+
-+struct	_vcs_dpi_wm_calc_pipe_params_st	{
-+	unsigned int	num_dpp;
-+	int	voltage;
-+	int	output_type;
-+	double	dcfclk_mhz;
-+	double	socclk_mhz;
-+	double	dppclk_mhz;
-+	double	pixclk_mhz;
-+	unsigned char	interlace_en;
-+	unsigned char	pte_enable;
-+	unsigned char	dcc_enable;
-+	double	dcc_rate;
-+	double	bytes_per_pixel_c;
-+	double	bytes_per_pixel_y;
-+	unsigned int	swath_width_y;
-+	unsigned int	swath_height_y;
-+	unsigned int	swath_height_c;
-+	unsigned int	det_buffer_size_y;
-+	double	h_ratio;
-+	double	v_ratio;
-+	unsigned int	h_taps;
-+	unsigned int	h_total;
-+	unsigned int	v_total;
-+	unsigned int	v_active;
-+	unsigned int	e2e_index;
-+	double	display_pipe_line_delivery_time;
-+	double	read_bw;
-+	unsigned int	lines_in_det_y;
-+	unsigned int	lines_in_det_y_rounded_down_to_swath;
-+	double	full_det_buffering_time;
-+	double	dcfclk_deepsleep_mhz_per_plane;
-+};
-+
-+struct	_vcs_dpi_vratio_pre_st	{
-+	double	vratio_pre_l;
-+	double	vratio_pre_c;
-+};
-+
-+struct	_vcs_dpi_display_data_rq_misc_params_st	{
-+	unsigned int	full_swath_bytes;
-+	unsigned int	stored_swath_bytes;
-+	unsigned int	blk256_height;
-+	unsigned int	blk256_width;
-+	unsigned int	req_height;
-+	unsigned int	req_width;
-+};
-+
-+struct	_vcs_dpi_display_data_rq_sizing_params_st	{
-+	unsigned int	chunk_bytes;
-+	unsigned int	min_chunk_bytes;
-+	unsigned int	meta_chunk_bytes;
-+	unsigned int	min_meta_chunk_bytes;
-+	unsigned int	mpte_group_bytes;
-+	unsigned int	dpte_group_bytes;
-+};
-+
-+struct	_vcs_dpi_display_data_rq_dlg_params_st	{
-+	unsigned int	swath_width_ub;
-+	unsigned int	swath_height;
-+	unsigned int	req_per_swath_ub;
-+	unsigned int	meta_pte_bytes_per_frame_ub;
-+	unsigned int	dpte_req_per_row_ub;
-+	unsigned int	dpte_groups_per_row_ub;
-+	unsigned int	dpte_row_height;
-+	unsigned int	dpte_bytes_per_row_ub;
-+	unsigned int	meta_chunks_per_row_ub;
-+	unsigned int	meta_req_per_row_ub;
-+	unsigned int	meta_row_height;
-+	unsigned int	meta_bytes_per_row_ub;
-+};
-+
-+struct	_vcs_dpi_display_cur_rq_dlg_params_st	{
-+	unsigned char	enable;
-+	unsigned int	swath_height;
-+	unsigned int	req_per_line;
-+};
-+
-+struct	_vcs_dpi_display_rq_dlg_params_st	{
-+	display_data_rq_dlg_params_st	rq_l;
-+	display_data_rq_dlg_params_st	rq_c;
-+	display_cur_rq_dlg_params_st	rq_cur0;
-+};
-+
-+struct	_vcs_dpi_display_rq_sizing_params_st	{
-+	display_data_rq_sizing_params_st	rq_l;
-+	display_data_rq_sizing_params_st	rq_c;
-+};
-+
-+struct	_vcs_dpi_display_rq_misc_params_st	{
-+	display_data_rq_misc_params_st	rq_l;
-+	display_data_rq_misc_params_st	rq_c;
-+};
-+
-+struct	_vcs_dpi_display_rq_params_st	{
-+	unsigned char	yuv420;
-+	unsigned char	yuv420_10bpc;
-+	display_rq_misc_params_st	misc;
-+	display_rq_sizing_params_st	sizing;
-+	display_rq_dlg_params_st	dlg;
-+};
-+
-+struct	_vcs_dpi_display_dlg_regs_st	{
-+	unsigned int	refcyc_h_blank_end;
-+	unsigned int	dlg_vblank_end;
-+	unsigned int	min_dst_y_next_start;
-+	unsigned int	refcyc_per_htotal;
-+	unsigned int	refcyc_x_after_scaler;
-+	unsigned int	dst_y_after_scaler;
-+	unsigned int	dst_y_prefetch;
-+	unsigned int	dst_y_per_vm_vblank;
-+	unsigned int	dst_y_per_row_vblank;
-+	unsigned int	dst_y_per_vm_flip;
-+	unsigned int	dst_y_per_row_flip;
-+	unsigned int	ref_freq_to_pix_freq;
-+	unsigned int	vratio_prefetch;
-+	unsigned int	vratio_prefetch_c;
-+	unsigned int	refcyc_per_pte_group_vblank_l;
-+	unsigned int	refcyc_per_pte_group_vblank_c;
-+	unsigned int	refcyc_per_meta_chunk_vblank_l;
-+	unsigned int	refcyc_per_meta_chunk_vblank_c;
-+	unsigned int	refcyc_per_pte_group_flip_l;
-+	unsigned int	refcyc_per_pte_group_flip_c;
-+	unsigned int	refcyc_per_meta_chunk_flip_l;
-+	unsigned int	refcyc_per_meta_chunk_flip_c;
-+	unsigned int	dst_y_per_pte_row_nom_l;
-+	unsigned int	dst_y_per_pte_row_nom_c;
-+	unsigned int	refcyc_per_pte_group_nom_l;
-+	unsigned int	refcyc_per_pte_group_nom_c;
-+	unsigned int	dst_y_per_meta_row_nom_l;
-+	unsigned int	dst_y_per_meta_row_nom_c;
-+	unsigned int	refcyc_per_meta_chunk_nom_l;
-+	unsigned int	refcyc_per_meta_chunk_nom_c;
-+	unsigned int	refcyc_per_line_delivery_pre_l;
-+	unsigned int	refcyc_per_line_delivery_pre_c;
-+	unsigned int	refcyc_per_line_delivery_l;
-+	unsigned int	refcyc_per_line_delivery_c;
-+	unsigned int	chunk_hdl_adjust_cur0;
-+	unsigned int	chunk_hdl_adjust_cur1;
-+	unsigned int	vready_after_vcount0;
-+	unsigned int	dst_y_offset_cur0;
-+	unsigned int	dst_y_offset_cur1;
-+	unsigned int	xfc_reg_transfer_delay;
-+	unsigned int	xfc_reg_precharge_delay;
-+	unsigned int	xfc_reg_remote_surface_flip_latency;
-+	unsigned int	xfc_reg_prefetch_margin;
-+	unsigned int	dst_y_delta_drq_limit;
-+};
-+
-+struct	_vcs_dpi_display_ttu_regs_st	{
-+	unsigned int	qos_level_low_wm;
-+	unsigned int	qos_level_high_wm;
-+	unsigned int	min_ttu_vblank;
-+	unsigned int	qos_level_flip;
-+	unsigned int	refcyc_per_req_delivery_l;
-+	unsigned int	refcyc_per_req_delivery_c;
-+	unsigned int	refcyc_per_req_delivery_cur0;
-+	unsigned int	refcyc_per_req_delivery_cur1;
-+	unsigned int	refcyc_per_req_delivery_pre_l;
-+	unsigned int	refcyc_per_req_delivery_pre_c;
-+	unsigned int	refcyc_per_req_delivery_pre_cur0;
-+	unsigned int	refcyc_per_req_delivery_pre_cur1;
-+	unsigned int	qos_level_fixed_l;
-+	unsigned int	qos_level_fixed_c;
-+	unsigned int	qos_level_fixed_cur0;
-+	unsigned int	qos_level_fixed_cur1;
-+	unsigned int	qos_ramp_disable_l;
-+	unsigned int	qos_ramp_disable_c;
-+	unsigned int	qos_ramp_disable_cur0;
-+	unsigned int	qos_ramp_disable_cur1;
-+};
-+
-+struct	_vcs_dpi_display_data_rq_regs_st	{
-+	unsigned int	chunk_size;
-+	unsigned int	min_chunk_size;
-+	unsigned int	meta_chunk_size;
-+	unsigned int	min_meta_chunk_size;
-+	unsigned int	dpte_group_size;
-+	unsigned int	mpte_group_size;
-+	unsigned int	swath_height;
-+	unsigned int	pte_row_height_linear;
-+};
-+
-+struct	_vcs_dpi_display_rq_regs_st	{
-+	display_data_rq_regs_st	rq_regs_l;
-+	display_data_rq_regs_st	rq_regs_c;
-+	unsigned int	drq_expansion_mode;
-+	unsigned int	prq_expansion_mode;
-+	unsigned int	mrq_expansion_mode;
-+	unsigned int	crq_expansion_mode;
-+	unsigned int	plane1_base_address;
-+};
-+
-+struct	_vcs_dpi_display_dlg_sys_params_st	{
-+	double	t_mclk_wm_us;
-+	double	t_urg_wm_us;
-+	double	t_sr_wm_us;
-+	double	t_extra_us;
-+	double	mem_trip_us;
-+	double	t_srx_delay_us;
-+	double	deepsleep_dcfclk_mhz;
-+	double	total_flip_bw;
-+	unsigned int	total_flip_bytes;
-+};
-+
-+struct	_vcs_dpi_display_dlg_prefetch_param_st	{
-+	double	prefetch_bw;
-+	unsigned int	flip_bytes;
-+};
-+
-+struct	_vcs_dpi_display_pipe_clock_st	{
-+	double	dcfclk_mhz;
-+	double	dispclk_mhz;
-+	double	socclk_mhz;
-+	double	dscclk_mhz[6];
-+	double	dppclk_mhz[6];
-+};
-+
-+struct	_vcs_dpi_display_arb_params_st	{
-+	int	max_req_outstanding;
-+	int	min_req_outstanding;
-+	int	sat_level_us;
-+};
-+
-+#endif /*__DISPLAY_MODE_STRUCTS_H__*/
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c.0130~	2017-12-14 06:39:58.426903575 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c	2017-12-14 06:39:58.426903575 +0100
-@@ -0,0 +1,6124 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "display_mode_lib.h"
-+#include "display_mode_vba.h"
-+
-+#include "dml_inline_defs.h"
-+
-+static const unsigned int NumberOfStates = DC__VOLTAGE_STATES;
-+
-+static void fetch_socbb_params(struct display_mode_lib *mode_lib);
-+static void fetch_ip_params(struct display_mode_lib *mode_lib);
-+static void fetch_pipe_params(struct display_mode_lib *mode_lib);
-+static void recalculate_params(
-+		struct display_mode_lib *mode_lib,
-+		const display_e2e_pipe_params_st *pipes,
-+		unsigned int num_pipes);
-+static void recalculate(struct display_mode_lib *mode_lib);
-+static double adjust_ReturnBW(
-+		struct display_mode_lib *mode_lib,
-+		double ReturnBW,
-+		bool DCCEnabledAnyPlane,
-+		double ReturnBandwidthToDCN);
-+static void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib);
-+static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
-+static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
-+		struct display_mode_lib *mode_lib);
-+static unsigned int dscceComputeDelay(
-+		unsigned int bpc,
-+		double bpp,
-+		unsigned int sliceWidth,
-+		unsigned int numSlices,
-+		enum output_format_class pixelFormat);
-+static unsigned int dscComputeDelay(enum output_format_class pixelFormat);
-+// Super monster function with some 45 argument
-+static bool CalculatePrefetchSchedule(
-+		struct display_mode_lib *mode_lib,
-+		double DPPCLK,
-+		double DISPCLK,
-+		double PixelClock,
-+		double DCFClkDeepSleep,
-+		unsigned int DSCDelay,
-+		unsigned int DPPPerPlane,
-+		bool ScalerEnabled,
-+		unsigned int NumberOfCursors,
-+		double DPPCLKDelaySubtotal,
-+		double DPPCLKDelaySCL,
-+		double DPPCLKDelaySCLLBOnly,
-+		double DPPCLKDelayCNVCFormater,
-+		double DPPCLKDelayCNVCCursor,
-+		double DISPCLKDelaySubtotal,
-+		unsigned int ScalerRecoutWidth,
-+		enum output_format_class OutputFormat,
-+		unsigned int VBlank,
-+		unsigned int HTotal,
-+		unsigned int MaxInterDCNTileRepeaters,
-+		unsigned int VStartup,
-+		unsigned int PageTableLevels,
-+		bool VirtualMemoryEnable,
-+		bool DynamicMetadataEnable,
-+		unsigned int DynamicMetadataLinesBeforeActiveRequired,
-+		unsigned int DynamicMetadataTransmittedBytes,
-+		bool DCCEnable,
-+		double UrgentLatency,
-+		double UrgentExtraLatency,
-+		double TCalc,
-+		unsigned int PDEAndMetaPTEBytesFrame,
-+		unsigned int MetaRowByte,
-+		unsigned int PixelPTEBytesPerRow,
-+		double PrefetchSourceLinesY,
-+		unsigned int SwathWidthY,
-+		double BytePerPixelDETY,
-+		double VInitPreFillY,
-+		unsigned int MaxNumSwathY,
-+		double PrefetchSourceLinesC,
-+		double BytePerPixelDETC,
-+		double VInitPreFillC,
-+		unsigned int MaxNumSwathC,
-+		unsigned int SwathHeightY,
-+		unsigned int SwathHeightC,
-+		double TWait,
-+		bool XFCEnabled,
-+		double XFCRemoteSurfaceFlipDelay,
-+		bool InterlaceEnable,
-+		bool ProgressiveToInterlaceUnitInOPP,
-+		double *DSTXAfterScaler,
-+		double *DSTYAfterScaler,
-+		double *DestinationLinesForPrefetch,
-+		double *PrefetchBandwidth,
-+		double *DestinationLinesToRequestVMInVBlank,
-+		double *DestinationLinesToRequestRowInVBlank,
-+		double *VRatioPrefetchY,
-+		double *VRatioPrefetchC,
-+		double *RequiredPrefetchPixDataBW,
-+		unsigned int *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata,
-+		double *Tno_bw,
-+		unsigned int *VUpdateOffsetPix,
-+		unsigned int *VUpdateWidthPix,
-+		unsigned int *VReadyOffsetPix);
-+static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
-+static double RoundToDFSGranularityDown(double Clock, double VCOSpeed);
-+static double CalculatePrefetchSourceLines(
-+		struct display_mode_lib *mode_lib,
-+		double VRatio,
-+		double vtaps,
-+		bool Interlace,
-+		bool ProgressiveToInterlaceUnitInOPP,
-+		unsigned int SwathHeight,
-+		unsigned int ViewportYStart,
-+		double *VInitPreFill,
-+		unsigned int *MaxNumSwath);
-+static unsigned int CalculateVMAndRowBytes(
-+		struct display_mode_lib *mode_lib,
-+		bool DCCEnable,
-+		unsigned int BlockHeight256Bytes,
-+		unsigned int BlockWidth256Bytes,
-+		enum source_format_class SourcePixelFormat,
-+		unsigned int SurfaceTiling,
-+		unsigned int BytePerPixel,
-+		enum scan_direction_class ScanDirection,
-+		unsigned int ViewportWidth,
-+		unsigned int ViewportHeight,
-+		unsigned int SwathWidthY,
-+		bool VirtualMemoryEnable,
-+		unsigned int VMMPageSize,
-+		unsigned int PTEBufferSizeInRequests,
-+		unsigned int PDEProcessingBufIn64KBReqs,
-+		unsigned int Pitch,
-+		unsigned int DCCMetaPitch,
-+		unsigned int *MacroTileWidth,
-+		unsigned int *MetaRowByte,
-+		unsigned int *PixelPTEBytesPerRow,
-+		bool *PTEBufferSizeNotExceeded,
-+		unsigned int *dpte_row_height,
-+		unsigned int *meta_row_height);
-+static double CalculateTWait(
-+		unsigned int PrefetchMode,
-+		double DRAMClockChangeLatency,
-+		double UrgentLatency,
-+		double SREnterPlusExitTime);
-+static double CalculateRemoteSurfaceFlipDelay(
-+		struct display_mode_lib *mode_lib,
-+		double VRatio,
-+		double SwathWidth,
-+		double Bpp,
-+		double LineTime,
-+		double XFCTSlvVupdateOffset,
-+		double XFCTSlvVupdateWidth,
-+		double XFCTSlvVreadyOffset,
-+		double XFCXBUFLatencyTolerance,
-+		double XFCFillBWOverhead,
-+		double XFCSlvChunkSize,
-+		double XFCBusTransportTime,
-+		double TCalc,
-+		double TWait,
-+		double *SrcActiveDrainRate,
-+		double *TInitXFill,
-+		double *TslvChk);
-+static double CalculateWriteBackDISPCLK(
-+		enum source_format_class WritebackPixelFormat,
-+		double PixelClock,
-+		double WritebackHRatio,
-+		double WritebackVRatio,
-+		unsigned int WritebackLumaHTaps,
-+		unsigned int WritebackLumaVTaps,
-+		unsigned int WritebackChromaHTaps,
-+		unsigned int WritebackChromaVTaps,
-+		double WritebackDestinationWidth,
-+		unsigned int HTotal,
-+		unsigned int WritebackChromaLineBufferWidth);
-+static void CalculateActiveRowBandwidth(
-+		bool VirtualMemoryEnable,
-+		enum source_format_class SourcePixelFormat,
-+		double VRatio,
-+		bool DCCEnable,
-+		double LineTime,
-+		unsigned int MetaRowByteLuma,
-+		unsigned int MetaRowByteChroma,
-+		unsigned int meta_row_height_luma,
-+		unsigned int meta_row_height_chroma,
-+		unsigned int PixelPTEBytesPerRowLuma,
-+		unsigned int PixelPTEBytesPerRowChroma,
-+		unsigned int dpte_row_height_luma,
-+		unsigned int dpte_row_height_chroma,
-+		double *meta_row_bw,
-+		double *dpte_row_bw,
-+		double *qual_row_bw);
-+static void CalculateFlipSchedule(
-+		struct display_mode_lib *mode_lib,
-+		double UrgentExtraLatency,
-+		double UrgentLatency,
-+		unsigned int MaxPageTableLevels,
-+		bool VirtualMemoryEnable,
-+		double BandwidthAvailableForImmediateFlip,
-+		unsigned int TotImmediateFlipBytes,
-+		enum source_format_class SourcePixelFormat,
-+		unsigned int ImmediateFlipBytes,
-+		double LineTime,
-+		double Tno_bw,
-+		double VRatio,
-+		double PDEAndMetaPTEBytesFrame,
-+		unsigned int MetaRowByte,
-+		unsigned int PixelPTEBytesPerRow,
-+		bool DCCEnable,
-+		unsigned int dpte_row_height,
-+		unsigned int meta_row_height,
-+		double qual_row_bw,
-+		double *DestinationLinesToRequestVMInImmediateFlip,
-+		double *DestinationLinesToRequestRowInImmediateFlip,
-+		double *final_flip_bw,
-+		bool *ImmediateFlipSupportedForPipe);
-+static double CalculateWriteBackDelay(
-+		enum source_format_class WritebackPixelFormat,
-+		double WritebackHRatio,
-+		double WritebackVRatio,
-+		unsigned int WritebackLumaHTaps,
-+		unsigned int WritebackLumaVTaps,
-+		unsigned int WritebackChromaHTaps,
-+		unsigned int WritebackChromaVTaps,
-+		unsigned int WritebackDestinationWidth);
-+static void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
-+static unsigned int CursorBppEnumToBits(enum cursor_bpp ebpp);
-+static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
-+
-+void set_prefetch_mode(
-+		struct display_mode_lib *mode_lib,
-+		bool cstate_en,
-+		bool pstate_en,
-+		bool ignore_viewport_pos,
-+		bool immediate_flip_support)
-+{
-+	unsigned int prefetch_mode;
-+
-+	if (cstate_en && pstate_en)
-+		prefetch_mode = 0;
-+	else if (cstate_en)
-+		prefetch_mode = 1;
-+	else
-+		prefetch_mode = 2;
-+	if (prefetch_mode != mode_lib->vba.PrefetchMode
-+			|| ignore_viewport_pos != mode_lib->vba.IgnoreViewportPositioning
-+			|| immediate_flip_support != mode_lib->vba.ImmediateFlipSupport) {
-+		DTRACE(
-+				"   Prefetch mode has changed from %i to %i. Recalculating.",
-+				prefetch_mode,
-+				mode_lib->vba.PrefetchMode);
-+		mode_lib->vba.PrefetchMode = prefetch_mode;
-+		mode_lib->vba.IgnoreViewportPositioning = ignore_viewport_pos;
-+		mode_lib->vba.ImmediateFlipSupport = immediate_flip_support;
-+		recalculate(mode_lib);
-+	}
-+}
-+
-+unsigned int dml_get_voltage_level(
-+		struct display_mode_lib *mode_lib,
-+		const display_e2e_pipe_params_st *pipes,
-+		unsigned int num_pipes)
-+{
-+	bool need_recalculate = memcmp(&mode_lib->soc, &mode_lib->vba.soc, sizeof(mode_lib->vba.soc)) != 0
-+			|| memcmp(&mode_lib->ip, &mode_lib->vba.ip, sizeof(mode_lib->vba.ip)) != 0
-+			|| num_pipes != mode_lib->vba.cache_num_pipes
-+			|| memcmp(pipes, mode_lib->vba.cache_pipes,
-+					sizeof(display_e2e_pipe_params_st) * num_pipes) != 0;
-+
-+	mode_lib->vba.soc = mode_lib->soc;
-+	mode_lib->vba.ip = mode_lib->ip;
-+	memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes);
-+	mode_lib->vba.cache_num_pipes = num_pipes;
-+
-+	if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0)
-+		recalculate(mode_lib);
-+	else {
-+		fetch_socbb_params(mode_lib);
-+		fetch_ip_params(mode_lib);
-+		fetch_pipe_params(mode_lib);
-+	}
-+	ModeSupportAndSystemConfigurationFull(mode_lib);
-+
-+	return mode_lib->vba.VoltageLevel;
-+}
-+
-+#define dml_get_attr_func(attr, var)  double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes) \
-+{ \
-+	recalculate_params(mode_lib, pipes, num_pipes); \
-+	return var; \
-+}
-+
-+dml_get_attr_func(clk_dcf_deepsleep, mode_lib->vba.DCFClkDeepSleep);
-+dml_get_attr_func(wm_urgent, mode_lib->vba.UrgentWatermark);
-+dml_get_attr_func(wm_memory_trip, mode_lib->vba.MemoryTripWatermark);
-+dml_get_attr_func(wm_writeback_urgent, mode_lib->vba.WritebackUrgentWatermark);
-+dml_get_attr_func(wm_stutter_exit, mode_lib->vba.StutterExitWatermark);
-+dml_get_attr_func(wm_stutter_enter_exit, mode_lib->vba.StutterEnterPlusExitWatermark);
-+dml_get_attr_func(wm_dram_clock_change, mode_lib->vba.DRAMClockChangeWatermark);
-+dml_get_attr_func(wm_writeback_dram_clock_change, mode_lib->vba.WritebackDRAMClockChangeWatermark);
-+dml_get_attr_func(wm_xfc_underflow, mode_lib->vba.UrgentWatermark); // xfc_underflow maps to urgent
-+dml_get_attr_func(stutter_efficiency, mode_lib->vba.StutterEfficiency);
-+dml_get_attr_func(stutter_efficiency_no_vblank, mode_lib->vba.StutterEfficiencyNotIncludingVBlank);
-+dml_get_attr_func(urgent_latency, mode_lib->vba.MinUrgentLatencySupportUs);
-+dml_get_attr_func(urgent_extra_latency, mode_lib->vba.UrgentExtraLatency);
-+dml_get_attr_func(nonurgent_latency, mode_lib->vba.NonUrgentLatencyTolerance);
-+dml_get_attr_func(
-+		dram_clock_change_latency,
-+		mode_lib->vba.MinActiveDRAMClockChangeLatencySupported);
-+dml_get_attr_func(dispclk_calculated, mode_lib->vba.DISPCLK_calculated);
-+dml_get_attr_func(total_data_read_bw, mode_lib->vba.TotalDataReadBandwidth);
-+dml_get_attr_func(return_bw, mode_lib->vba.ReturnBW);
-+dml_get_attr_func(tcalc, mode_lib->vba.TCalc);
-+
-+#define dml_get_pipe_attr_func(attr, var)  double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) \
-+{\
-+	unsigned int which_plane; \
-+	recalculate_params(mode_lib, pipes, num_pipes); \
-+	which_plane = mode_lib->vba.pipe_plane[which_pipe]; \
-+	return var[which_plane]; \
-+}
-+
-+dml_get_pipe_attr_func(dsc_delay, mode_lib->vba.DSCDelay);
-+dml_get_pipe_attr_func(dppclk_calculated, mode_lib->vba.DPPCLK_calculated);
-+dml_get_pipe_attr_func(dscclk_calculated, mode_lib->vba.DSCCLK_calculated);
-+dml_get_pipe_attr_func(min_ttu_vblank, mode_lib->vba.MinTTUVBlank);
-+dml_get_pipe_attr_func(vratio_prefetch_l, mode_lib->vba.VRatioPrefetchY);
-+dml_get_pipe_attr_func(vratio_prefetch_c, mode_lib->vba.VRatioPrefetchC);
-+dml_get_pipe_attr_func(dst_x_after_scaler, mode_lib->vba.DSTXAfterScaler);
-+dml_get_pipe_attr_func(dst_y_after_scaler, mode_lib->vba.DSTYAfterScaler);
-+dml_get_pipe_attr_func(dst_y_per_vm_vblank, mode_lib->vba.DestinationLinesToRequestVMInVBlank);
-+dml_get_pipe_attr_func(dst_y_per_row_vblank, mode_lib->vba.DestinationLinesToRequestRowInVBlank);
-+dml_get_pipe_attr_func(dst_y_prefetch, mode_lib->vba.DestinationLinesForPrefetch);
-+dml_get_pipe_attr_func(dst_y_per_vm_flip, mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip);
-+dml_get_pipe_attr_func(
-+		dst_y_per_row_flip,
-+		mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip);
-+
-+dml_get_pipe_attr_func(xfc_transfer_delay, mode_lib->vba.XFCTransferDelay);
-+dml_get_pipe_attr_func(xfc_precharge_delay, mode_lib->vba.XFCPrechargeDelay);
-+dml_get_pipe_attr_func(xfc_remote_surface_flip_latency, mode_lib->vba.XFCRemoteSurfaceFlipLatency);
-+dml_get_pipe_attr_func(xfc_prefetch_margin, mode_lib->vba.XFCPrefetchMargin);
-+
-+unsigned int get_vstartup_calculated(
-+		struct display_mode_lib *mode_lib,
-+		const display_e2e_pipe_params_st *pipes,
-+		unsigned int num_pipes,
-+		unsigned int which_pipe)
-+{
-+	unsigned int which_plane;
-+
-+	recalculate_params(mode_lib, pipes, num_pipes);
-+	which_plane = mode_lib->vba.pipe_plane[which_pipe];
-+	return mode_lib->vba.VStartup[which_plane];
-+}
-+
-+double get_total_immediate_flip_bytes(
-+		struct display_mode_lib *mode_lib,
-+		const display_e2e_pipe_params_st *pipes,
-+		unsigned int num_pipes)
-+{
-+	recalculate_params(mode_lib, pipes, num_pipes);
-+	return mode_lib->vba.TotImmediateFlipBytes;
-+}
-+
-+double get_total_immediate_flip_bw(
-+		struct display_mode_lib *mode_lib,
-+		const display_e2e_pipe_params_st *pipes,
-+		unsigned int num_pipes)
-+{
-+	recalculate_params(mode_lib, pipes, num_pipes);
-+	return mode_lib->vba.ImmediateFlipBW;
-+}
-+
-+double get_total_prefetch_bw(
-+		struct display_mode_lib *mode_lib,
-+		const display_e2e_pipe_params_st *pipes,
-+		unsigned int num_pipes)
-+{
-+	unsigned int k;
-+	double total_prefetch_bw = 0.0;
-+
-+	recalculate_params(mode_lib, pipes, num_pipes);
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
-+		total_prefetch_bw += mode_lib->vba.PrefetchBandwidth[k];
-+	return total_prefetch_bw;
-+}
-+
-+static void fetch_socbb_params(struct display_mode_lib *mode_lib)
-+{
-+	soc_bounding_box_st *soc = &mode_lib->vba.soc;
-+	unsigned int i;
-+
-+	// SOC Bounding Box Parameters
-+	mode_lib->vba.ReturnBusWidth = soc->return_bus_width_bytes;
-+	mode_lib->vba.NumberOfChannels = soc->num_chans;
-+	mode_lib->vba.PercentOfIdealDRAMAndFabricBWReceivedAfterUrgLatency =
-+			soc->ideal_dram_bw_after_urgent_percent; // there's always that one bastard variable that's so long it throws everything out of alignment!
-+	mode_lib->vba.UrgentLatency = soc->urgent_latency_us;
-+	mode_lib->vba.RoundTripPingLatencyCycles = soc->round_trip_ping_latency_dcfclk_cycles;
-+	mode_lib->vba.UrgentOutOfOrderReturnPerChannel =
-+			soc->urgent_out_of_order_return_per_channel_bytes;
-+	mode_lib->vba.WritebackLatency = soc->writeback_latency_us;
-+	mode_lib->vba.SRExitTime = soc->sr_exit_time_us;
-+	mode_lib->vba.SREnterPlusExitTime = soc->sr_enter_plus_exit_time_us;
-+	mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us;
-+	mode_lib->vba.Downspreading = soc->downspread_percent;
-+	mode_lib->vba.DRAMChannelWidth = soc->dram_channel_width_bytes;   // new!
-+	mode_lib->vba.FabricDatapathToDCNDataReturn = soc->fabric_datapath_to_dcn_data_return_bytes; // new!
-+	mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading = soc->dcn_downspread_percent;   // new
-+	mode_lib->vba.DISPCLKDPPCLKVCOSpeed = soc->dispclk_dppclk_vco_speed_mhz;   // new
-+	mode_lib->vba.VMMPageSize = soc->vmm_page_size_bytes;
-+	// Set the voltage scaling clocks as the defaults. Most of these will
-+	// be set to different values by the test
-+	for (i = 0; i < DC__VOLTAGE_STATES; i++)
-+		if (soc->clock_limits[i].state == mode_lib->vba.VoltageLevel)
-+			break;
-+
-+	mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz;
-+	mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz;
-+	mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mhz;
-+	mode_lib->vba.FabricClock = soc->clock_limits[i].fabricclk_mhz;
-+
-+	mode_lib->vba.XFCBusTransportTime = soc->xfc_bus_transport_time_us;
-+	mode_lib->vba.XFCXBUFLatencyTolerance = soc->xfc_xbuf_latency_tolerance_us;
-+
-+	mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp = false;
-+	mode_lib->vba.MaxHSCLRatio = 4;
-+	mode_lib->vba.MaxVSCLRatio = 4;
-+	mode_lib->vba.MaxNumWriteback = 0; /*TODO*/
-+	mode_lib->vba.WritebackLumaAndChromaScalingSupported = true;
-+	mode_lib->vba.Cursor64BppSupport = true;
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz;
-+		mode_lib->vba.FabricClockPerState[i] = soc->clock_limits[i].fabricclk_mhz;
-+		mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz;
-+		mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz;
-+		mode_lib->vba.MaxDppclk[i] = soc->clock_limits[i].dppclk_mhz;
-+		mode_lib->vba.MaxDSCCLK[i] = soc->clock_limits[i].dscclk_mhz;
-+		mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mhz;
-+		mode_lib->vba.MaxDispclk[i] = soc->clock_limits[i].dispclk_mhz;
-+	}
-+}
-+
-+static void fetch_ip_params(struct display_mode_lib *mode_lib)
-+{
-+	ip_params_st *ip = &mode_lib->vba.ip;
-+
-+	// IP Parameters
-+	mode_lib->vba.MaxNumDPP = ip->max_num_dpp;
-+	mode_lib->vba.MaxNumOTG = ip->max_num_otg;
-+	mode_lib->vba.CursorChunkSize = ip->cursor_chunk_size;
-+	mode_lib->vba.CursorBufferSize = ip->cursor_buffer_size;
-+
-+	mode_lib->vba.MaxDCHUBToPSCLThroughput = ip->max_dchub_pscl_bw_pix_per_clk;
-+	mode_lib->vba.MaxPSCLToLBThroughput = ip->max_pscl_lb_bw_pix_per_clk;
-+	mode_lib->vba.ROBBufferSizeInKByte = ip->rob_buffer_size_kbytes;
-+	mode_lib->vba.DETBufferSizeInKByte = ip->det_buffer_size_kbytes;
-+	mode_lib->vba.PixelChunkSizeInKByte = ip->pixel_chunk_size_kbytes;
-+	mode_lib->vba.MetaChunkSize = ip->meta_chunk_size_kbytes;
-+	mode_lib->vba.PTEChunkSize = ip->pte_chunk_size_kbytes;
-+	mode_lib->vba.WritebackChunkSize = ip->writeback_chunk_size_kbytes;
-+	mode_lib->vba.LineBufferSize = ip->line_buffer_size_bits;
-+	mode_lib->vba.MaxLineBufferLines = ip->max_line_buffer_lines;
-+	mode_lib->vba.PTEBufferSizeInRequests = ip->dpte_buffer_size_in_pte_reqs;
-+	mode_lib->vba.DPPOutputBufferPixels = ip->dpp_output_buffer_pixels;
-+	mode_lib->vba.OPPOutputBufferLines = ip->opp_output_buffer_lines;
-+	mode_lib->vba.WritebackInterfaceLumaBufferSize = ip->writeback_luma_buffer_size_kbytes;
-+	mode_lib->vba.WritebackInterfaceChromaBufferSize = ip->writeback_chroma_buffer_size_kbytes;
-+	mode_lib->vba.WritebackChromaLineBufferWidth =
-+			ip->writeback_chroma_line_buffer_width_pixels;
-+	mode_lib->vba.MaxPageTableLevels = ip->max_page_table_levels;
-+	mode_lib->vba.MaxInterDCNTileRepeaters = ip->max_inter_dcn_tile_repeaters;
-+	mode_lib->vba.NumberOfDSC = ip->num_dsc;
-+	mode_lib->vba.ODMCapability = ip->odm_capable;
-+	mode_lib->vba.DISPCLKRampingMargin = ip->dispclk_ramp_margin_percent;
-+
-+	mode_lib->vba.XFCSupported = ip->xfc_supported;
-+	mode_lib->vba.XFCFillBWOverhead = ip->xfc_fill_bw_overhead_percent;
-+	mode_lib->vba.XFCFillConstant = ip->xfc_fill_constant_bytes;
-+	mode_lib->vba.DPPCLKDelaySubtotal = ip->dppclk_delay_subtotal;
-+	mode_lib->vba.DPPCLKDelaySCL = ip->dppclk_delay_scl;
-+	mode_lib->vba.DPPCLKDelaySCLLBOnly = ip->dppclk_delay_scl_lb_only;
-+	mode_lib->vba.DPPCLKDelayCNVCFormater = ip->dppclk_delay_cnvc_formatter;
-+	mode_lib->vba.DPPCLKDelayCNVCCursor = ip->dppclk_delay_cnvc_cursor;
-+	mode_lib->vba.DISPCLKDelaySubtotal = ip->dispclk_delay_subtotal;
-+
-+	mode_lib->vba.ProgressiveToInterlaceUnitInOPP = ip->ptoi_supported;
-+
-+	mode_lib->vba.PDEProcessingBufIn64KBReqs = ip->pde_proc_buffer_size_64k_reqs;
-+}
-+
-+static void fetch_pipe_params(struct display_mode_lib *mode_lib)
-+{
-+	display_e2e_pipe_params_st *pipes = mode_lib->vba.cache_pipes;
-+	ip_params_st *ip = &mode_lib->vba.ip;
-+
-+	unsigned int OTGInstPlane[DC__NUM_DPP__MAX];
-+	unsigned int j, k;
-+	bool PlaneVisited[DC__NUM_DPP__MAX];
-+	bool visited[DC__NUM_DPP__MAX];
-+
-+	// Convert Pipes to Planes
-+	for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k)
-+		visited[k] = false;
-+
-+	mode_lib->vba.NumberOfActivePlanes = 0;
-+	for (j = 0; j < mode_lib->vba.cache_num_pipes; ++j) {
-+		display_pipe_source_params_st *src = &pipes[j].pipe.src;
-+		display_pipe_dest_params_st *dst = &pipes[j].pipe.dest;
-+		scaler_ratio_depth_st *scl = &pipes[j].pipe.scale_ratio_depth;
-+		scaler_taps_st *taps = &pipes[j].pipe.scale_taps;
-+		display_output_params_st *dout = &pipes[j].dout;
-+		display_clocks_and_cfg_st *clks = &pipes[j].clks_cfg;
-+
-+		if (visited[j])
-+			continue;
-+		visited[j] = true;
-+
-+		mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes;
-+
-+		mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes] = 1;
-+		mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes] =
-+				(enum scan_direction_class) (src->source_scan);
-+		mode_lib->vba.ViewportWidth[mode_lib->vba.NumberOfActivePlanes] =
-+				src->viewport_width;
-+		mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] =
-+				src->viewport_height;
-+		mode_lib->vba.ViewportYStartY[mode_lib->vba.NumberOfActivePlanes] =
-+				src->viewport_y_y;
-+		mode_lib->vba.ViewportYStartC[mode_lib->vba.NumberOfActivePlanes] =
-+				src->viewport_y_c;
-+		mode_lib->vba.PitchY[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch;
-+		mode_lib->vba.PitchC[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch_c;
-+		mode_lib->vba.DCCMetaPitchY[mode_lib->vba.NumberOfActivePlanes] = src->meta_pitch;
-+		mode_lib->vba.HRatio[mode_lib->vba.NumberOfActivePlanes] = scl->hscl_ratio;
-+		mode_lib->vba.VRatio[mode_lib->vba.NumberOfActivePlanes] = scl->vscl_ratio;
-+		mode_lib->vba.ScalerEnabled[mode_lib->vba.NumberOfActivePlanes] = scl->scl_enable;
-+		mode_lib->vba.Interlace[mode_lib->vba.NumberOfActivePlanes] = dst->interlaced;
-+		if (mode_lib->vba.Interlace[mode_lib->vba.NumberOfActivePlanes])
-+			mode_lib->vba.VRatio[mode_lib->vba.NumberOfActivePlanes] *= 2.0;
-+		mode_lib->vba.htaps[mode_lib->vba.NumberOfActivePlanes] = taps->htaps;
-+		mode_lib->vba.vtaps[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps;
-+		mode_lib->vba.HTAPsChroma[mode_lib->vba.NumberOfActivePlanes] = taps->htaps_c;
-+		mode_lib->vba.VTAPsChroma[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps_c;
-+		mode_lib->vba.HTotal[mode_lib->vba.NumberOfActivePlanes] = dst->htotal;
-+		mode_lib->vba.VTotal[mode_lib->vba.NumberOfActivePlanes] = dst->vtotal;
-+		mode_lib->vba.DCCEnable[mode_lib->vba.NumberOfActivePlanes] =
-+				src->dcc_use_global ?
-+						ip->dcc_supported : src->dcc && ip->dcc_supported;
-+		mode_lib->vba.DCCRate[mode_lib->vba.NumberOfActivePlanes] = src->dcc_rate;
-+		mode_lib->vba.SourcePixelFormat[mode_lib->vba.NumberOfActivePlanes] =
-+				(enum source_format_class) (src->source_format);
-+		mode_lib->vba.HActive[mode_lib->vba.NumberOfActivePlanes] = dst->hactive;
-+		mode_lib->vba.VActive[mode_lib->vba.NumberOfActivePlanes] = dst->vactive;
-+		mode_lib->vba.SurfaceTiling[mode_lib->vba.NumberOfActivePlanes] =
-+				(enum dm_swizzle_mode) (src->sw_mode);
-+		mode_lib->vba.ScalerRecoutWidth[mode_lib->vba.NumberOfActivePlanes] =
-+				dst->recout_width; // TODO: or should this be full_recout_width???...maybe only when in hsplit mode?
-+		mode_lib->vba.ODMCombineEnabled[mode_lib->vba.NumberOfActivePlanes] =
-+				dst->odm_combine;
-+		mode_lib->vba.OutputFormat[mode_lib->vba.NumberOfActivePlanes] =
-+				(enum output_format_class) (dout->output_format);
-+		mode_lib->vba.Output[mode_lib->vba.NumberOfActivePlanes] =
-+				(enum output_encoder_class) (dout->output_type);
-+		mode_lib->vba.OutputBpp[mode_lib->vba.NumberOfActivePlanes] = dout->output_bpp;
-+		mode_lib->vba.OutputLinkDPLanes[mode_lib->vba.NumberOfActivePlanes] =
-+				dout->dp_lanes;
-+		mode_lib->vba.DSCEnabled[mode_lib->vba.NumberOfActivePlanes] = dout->dsc_enable;
-+		mode_lib->vba.NumberOfDSCSlices[mode_lib->vba.NumberOfActivePlanes] =
-+				dout->dsc_slices;
-+		mode_lib->vba.DSCInputBitPerComponent[mode_lib->vba.NumberOfActivePlanes] =
-+				dout->output_bpc == 0 ? 12 : dout->output_bpc;
-+		mode_lib->vba.WritebackEnable[mode_lib->vba.NumberOfActivePlanes] = dout->wb_enable;
-+		mode_lib->vba.WritebackSourceHeight[mode_lib->vba.NumberOfActivePlanes] =
-+				dout->wb.wb_src_height;
-+		mode_lib->vba.WritebackDestinationWidth[mode_lib->vba.NumberOfActivePlanes] =
-+				dout->wb.wb_dst_width;
-+		mode_lib->vba.WritebackDestinationHeight[mode_lib->vba.NumberOfActivePlanes] =
-+				dout->wb.wb_dst_height;
-+		mode_lib->vba.WritebackPixelFormat[mode_lib->vba.NumberOfActivePlanes] =
-+				(enum source_format_class) (dout->wb.wb_pixel_format);
-+		mode_lib->vba.WritebackLumaHTaps[mode_lib->vba.NumberOfActivePlanes] =
-+				dout->wb.wb_htaps_luma;
-+		mode_lib->vba.WritebackLumaVTaps[mode_lib->vba.NumberOfActivePlanes] =
-+				dout->wb.wb_vtaps_luma;
-+		mode_lib->vba.WritebackChromaHTaps[mode_lib->vba.NumberOfActivePlanes] =
-+				dout->wb.wb_htaps_chroma;
-+		mode_lib->vba.WritebackChromaVTaps[mode_lib->vba.NumberOfActivePlanes] =
-+				dout->wb.wb_vtaps_chroma;
-+		mode_lib->vba.WritebackHRatio[mode_lib->vba.NumberOfActivePlanes] =
-+				dout->wb.wb_hratio;
-+		mode_lib->vba.WritebackVRatio[mode_lib->vba.NumberOfActivePlanes] =
-+				dout->wb.wb_vratio;
-+
-+		mode_lib->vba.DynamicMetadataEnable[mode_lib->vba.NumberOfActivePlanes] =
-+				src->dynamic_metadata_enable;
-+		mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[mode_lib->vba.NumberOfActivePlanes] =
-+				src->dynamic_metadata_lines_before_active;
-+		mode_lib->vba.DynamicMetadataTransmittedBytes[mode_lib->vba.NumberOfActivePlanes] =
-+				src->dynamic_metadata_xmit_bytes;
-+
-+		mode_lib->vba.XFCEnabled[mode_lib->vba.NumberOfActivePlanes] = src->xfc_enable
-+				&& ip->xfc_supported;
-+		mode_lib->vba.XFCSlvChunkSize = src->xfc_params.xfc_slv_chunk_size_bytes;
-+		mode_lib->vba.XFCTSlvVupdateOffset = src->xfc_params.xfc_tslv_vupdate_offset_us;
-+		mode_lib->vba.XFCTSlvVupdateWidth = src->xfc_params.xfc_tslv_vupdate_width_us;
-+		mode_lib->vba.XFCTSlvVreadyOffset = src->xfc_params.xfc_tslv_vready_offset_us;
-+		mode_lib->vba.PixelClock[mode_lib->vba.NumberOfActivePlanes] = dst->pixel_rate_mhz;
-+		mode_lib->vba.DPPCLK[mode_lib->vba.NumberOfActivePlanes] = clks->dppclk_mhz;
-+		if (ip->is_line_buffer_bpp_fixed)
-+			mode_lib->vba.LBBitPerPixel[mode_lib->vba.NumberOfActivePlanes] =
-+					ip->line_buffer_fixed_bpp;
-+		else {
-+			unsigned int lb_depth;
-+
-+			switch (scl->lb_depth) {
-+			case dm_lb_6:
-+				lb_depth = 18;
-+				break;
-+			case dm_lb_8:
-+				lb_depth = 24;
-+				break;
-+			case dm_lb_10:
-+				lb_depth = 30;
-+				break;
-+			case dm_lb_12:
-+				lb_depth = 36;
-+				break;
-+			case dm_lb_16:
-+				lb_depth = 48;
-+				break;
-+			default:
-+				lb_depth = 36;
-+			}
-+			mode_lib->vba.LBBitPerPixel[mode_lib->vba.NumberOfActivePlanes] = lb_depth;
-+		}
-+		mode_lib->vba.NumberOfCursors[mode_lib->vba.NumberOfActivePlanes] = 0;
-+		// The DML spreadsheet assumes that the two cursors utilize the same amount of bandwidth. We'll
-+		// calculate things a little more accurately
-+		for (k = 0; k < DC__NUM_CURSOR__MAX; ++k) {
-+			switch (k) {
-+			case 0:
-+				mode_lib->vba.CursorBPP[mode_lib->vba.NumberOfActivePlanes][0] =
-+						CursorBppEnumToBits(
-+								(enum cursor_bpp) (src->cur0_bpp));
-+				mode_lib->vba.CursorWidth[mode_lib->vba.NumberOfActivePlanes][0] =
-+						src->cur0_src_width;
-+				if (src->cur0_src_width > 0)
-+					mode_lib->vba.NumberOfCursors[mode_lib->vba.NumberOfActivePlanes]++;
-+				break;
-+			case 1:
-+				mode_lib->vba.CursorBPP[mode_lib->vba.NumberOfActivePlanes][1] =
-+						CursorBppEnumToBits(
-+								(enum cursor_bpp) (src->cur1_bpp));
-+				mode_lib->vba.CursorWidth[mode_lib->vba.NumberOfActivePlanes][1] =
-+						src->cur1_src_width;
-+				if (src->cur1_src_width > 0)
-+					mode_lib->vba.NumberOfCursors[mode_lib->vba.NumberOfActivePlanes]++;
-+				break;
-+			default:
-+				dml_print(
-+						"ERROR: Number of cursors specified exceeds supported maximum\n")
-+				;
-+			}
-+		}
-+
-+		OTGInstPlane[mode_lib->vba.NumberOfActivePlanes] = dst->otg_inst;
-+
-+		if (dst->odm_combine && !src->is_hsplit)
-+			dml_print(
-+					"ERROR: ODM Combine is specified but is_hsplit has not be specified for pipe %i\n",
-+					j);
-+
-+		if (src->is_hsplit) {
-+			for (k = j + 1; k < mode_lib->vba.cache_num_pipes; ++k) {
-+				display_pipe_source_params_st *src_k = &pipes[k].pipe.src;
-+				display_output_params_st *dout_k = &pipes[k].dout;
-+
-+				if (src_k->is_hsplit && !visited[k]
-+						&& src->hsplit_grp == src_k->hsplit_grp) {
-+					mode_lib->vba.pipe_plane[k] =
-+							mode_lib->vba.NumberOfActivePlanes;
-+					mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes]++;
-+					if (mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes]
-+							== dm_horz)
-+						mode_lib->vba.ViewportWidth[mode_lib->vba.NumberOfActivePlanes] +=
-+								src_k->viewport_width;
-+					else
-+						mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] +=
-+								src_k->viewport_height;
-+
-+					mode_lib->vba.NumberOfDSCSlices[mode_lib->vba.NumberOfActivePlanes] +=
-+							dout_k->dsc_slices;
-+					visited[k] = true;
-+				}
-+			}
-+		}
-+
-+		mode_lib->vba.NumberOfActivePlanes++;
-+	}
-+
-+	// handle overlays through dml_ml->vba.BlendingAndTiming
-+	// dml_ml->vba.BlendingAndTiming tells you which instance to look at to get timing, the so called 'master'
-+
-+	for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j)
-+		PlaneVisited[j] = false;
-+
-+	for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) {
-+		for (k = j + 1; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+			if (!PlaneVisited[k] && OTGInstPlane[j] == OTGInstPlane[k]) {
-+				// doesn't matter, so choose the smaller one
-+				mode_lib->vba.BlendingAndTiming[j] = j;
-+				PlaneVisited[j] = true;
-+				mode_lib->vba.BlendingAndTiming[k] = j;
-+				PlaneVisited[k] = true;
-+			}
-+		}
-+
-+		if (!PlaneVisited[j]) {
-+			mode_lib->vba.BlendingAndTiming[j] = j;
-+			PlaneVisited[j] = true;
-+		}
-+	}
-+
-+	// TODO: dml_ml->vba.ODMCombineEnabled => 2 * dml_ml->vba.DPPPerPlane...actually maybe not since all pipes are specified
-+	// Do we want the dscclk to automatically be halved? Guess not since the value is specified
-+
-+	mode_lib->vba.SynchronizedVBlank = pipes[0].pipe.dest.synchronized_vblank_all_planes;
-+	for (k = 1; k < mode_lib->vba.cache_num_pipes; ++k)
-+		ASSERT(mode_lib->vba.SynchronizedVBlank == pipes[k].pipe.dest.synchronized_vblank_all_planes);
-+
-+	mode_lib->vba.VirtualMemoryEnable = false;
-+	mode_lib->vba.OverridePageTableLevels = 0;
-+
-+	for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
-+		mode_lib->vba.VirtualMemoryEnable = mode_lib->vba.VirtualMemoryEnable
-+				|| !!pipes[k].pipe.src.vm;
-+		mode_lib->vba.OverridePageTableLevels =
-+				(pipes[k].pipe.src.vm_levels_force_en
-+						&& mode_lib->vba.OverridePageTableLevels
-+								< pipes[k].pipe.src.vm_levels_force) ?
-+						pipes[k].pipe.src.vm_levels_force :
-+						mode_lib->vba.OverridePageTableLevels;
-+	}
-+
-+	if (mode_lib->vba.OverridePageTableLevels)
-+		mode_lib->vba.MaxPageTableLevels = mode_lib->vba.OverridePageTableLevels;
-+
-+	mode_lib->vba.VirtualMemoryEnable = mode_lib->vba.VirtualMemoryEnable && !!ip->pte_enable;
-+
-+	mode_lib->vba.FabricAndDRAMBandwidth = dml_min(
-+			mode_lib->vba.DRAMSpeed * mode_lib->vba.NumberOfChannels
-+					* mode_lib->vba.DRAMChannelWidth,
-+			mode_lib->vba.FabricClock * mode_lib->vba.FabricDatapathToDCNDataReturn)
-+			/ 1000.0;
-+
-+	// TODO: Must be consistent across all pipes
-+	// DCCProgrammingAssumesScanDirectionUnknown = src.dcc_scan_dir_unknown;
-+}
-+
-+static void recalculate(struct display_mode_lib *mode_lib)
-+{
-+	ModeSupportAndSystemConfiguration(mode_lib);
-+	PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib);
-+	DisplayPipeConfiguration(mode_lib);
-+	DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(mode_lib);
-+}
-+
-+// in wm mode we pull the parameters needed from the display_e2e_pipe_params_st structs
-+// rather than working them out as in recalculate_ms
-+static void recalculate_params(
-+		struct display_mode_lib *mode_lib,
-+		const display_e2e_pipe_params_st *pipes,
-+		unsigned int num_pipes)
-+{
-+	// This is only safe to use memcmp because there are non-POD types in struct display_mode_lib
-+	if (memcmp(&mode_lib->soc, &mode_lib->vba.soc, sizeof(mode_lib->vba.soc)) != 0
-+			|| memcmp(&mode_lib->ip, &mode_lib->vba.ip, sizeof(mode_lib->vba.ip)) != 0
-+			|| num_pipes != mode_lib->vba.cache_num_pipes
-+			|| memcmp(
-+					pipes,
-+					mode_lib->vba.cache_pipes,
-+					sizeof(display_e2e_pipe_params_st) * num_pipes) != 0) {
-+		mode_lib->vba.soc = mode_lib->soc;
-+		mode_lib->vba.ip = mode_lib->ip;
-+		memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes);
-+		mode_lib->vba.cache_num_pipes = num_pipes;
-+		recalculate(mode_lib);
-+	}
-+}
-+
-+static void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib)
-+{
-+	soc_bounding_box_st *soc = &mode_lib->vba.soc;
-+	unsigned int i, k;
-+	unsigned int total_pipes = 0;
-+
-+	mode_lib->vba.VoltageLevel = mode_lib->vba.cache_pipes[0].clks_cfg.voltage;
-+	for (i = 1; i < mode_lib->vba.cache_num_pipes; ++i)
-+		ASSERT(mode_lib->vba.VoltageLevel == -1 || mode_lib->vba.VoltageLevel == mode_lib->vba.cache_pipes[i].clks_cfg.voltage);
-+
-+	mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz;
-+	mode_lib->vba.SOCCLK = mode_lib->vba.cache_pipes[0].clks_cfg.socclk_mhz;
-+
-+	if (mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz > 0.0)
-+		mode_lib->vba.DISPCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz;
-+	else
-+		mode_lib->vba.DISPCLK = soc->clock_limits[mode_lib->vba.VoltageLevel].dispclk_mhz;
-+
-+	fetch_socbb_params(mode_lib);
-+	fetch_ip_params(mode_lib);
-+	fetch_pipe_params(mode_lib);
-+
-+	// Total Available Pipes Support Check
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
-+		total_pipes += mode_lib->vba.DPPPerPlane[k];
-+	ASSERT(total_pipes <= DC__NUM_DPP__MAX);
-+}
-+
-+static double adjust_ReturnBW(
-+		struct display_mode_lib *mode_lib,
-+		double ReturnBW,
-+		bool DCCEnabledAnyPlane,
-+		double ReturnBandwidthToDCN)
-+{
-+	double CriticalCompression;
-+
-+	if (DCCEnabledAnyPlane
-+			&& ReturnBandwidthToDCN
-+					> mode_lib->vba.DCFCLK * mode_lib->vba.ReturnBusWidth / 4.0)
-+		ReturnBW =
-+				dml_min(
-+						ReturnBW,
-+						ReturnBandwidthToDCN * 4
-+								* (1.0
-+										- mode_lib->vba.UrgentLatency
-+												/ ((mode_lib->vba.ROBBufferSizeInKByte
-+														- mode_lib->vba.PixelChunkSizeInKByte)
-+														* 1024
-+														/ ReturnBandwidthToDCN
-+														- mode_lib->vba.DCFCLK
-+																* mode_lib->vba.ReturnBusWidth
-+																/ 4)
-+										+ mode_lib->vba.UrgentLatency));
-+
-+	CriticalCompression = 2.0 * mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK
-+			* mode_lib->vba.UrgentLatency
-+			/ (ReturnBandwidthToDCN * mode_lib->vba.UrgentLatency
-+					+ (mode_lib->vba.ROBBufferSizeInKByte
-+							- mode_lib->vba.PixelChunkSizeInKByte)
-+							* 1024);
-+
-+	if (DCCEnabledAnyPlane && CriticalCompression > 1.0 && CriticalCompression < 4.0)
-+		ReturnBW =
-+				dml_min(
-+						ReturnBW,
-+						4.0 * ReturnBandwidthToDCN
-+								* (mode_lib->vba.ROBBufferSizeInKByte
-+										- mode_lib->vba.PixelChunkSizeInKByte)
-+								* 1024
-+								* mode_lib->vba.ReturnBusWidth
-+								* mode_lib->vba.DCFCLK
-+								* mode_lib->vba.UrgentLatency
-+								/ dml_pow(
-+										(ReturnBandwidthToDCN
-+												* mode_lib->vba.UrgentLatency
-+												+ (mode_lib->vba.ROBBufferSizeInKByte
-+														- mode_lib->vba.PixelChunkSizeInKByte)
-+														* 1024),
-+										2));
-+
-+	return ReturnBW;
-+}
-+
-+static unsigned int dscceComputeDelay(
-+		unsigned int bpc,
-+		double bpp,
-+		unsigned int sliceWidth,
-+		unsigned int numSlices,
-+		enum output_format_class pixelFormat)
-+{
-+	// valid bpc         = source bits per component in the set of {8, 10, 12}
-+	// valid bpp         = increments of 1/16 of a bit
-+	//                    min = 6/7/8 in N420/N422/444, respectively
-+	//                    max = such that compression is 1:1
-+	//valid sliceWidth  = number of pixels per slice line, must be less than or equal to 5184/numSlices (or 4096/numSlices in 420 mode)
-+	//valid numSlices   = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4}
-+	//valid pixelFormat = pixel/color format in the set of {:N444_RGB, :S422, :N422, :N420}
-+
-+	// fixed value
-+	unsigned int rcModelSize = 8192;
-+
-+	// N422/N420 operate at 2 pixels per clock
-+	unsigned int pixelsPerClock, lstall, D, initalXmitDelay, w, s, ix, wx, p, l0, a, ax, l,
-+			Delay, pixels;
-+
-+	if (pixelFormat == dm_n422 || pixelFormat == dm_420)
-+		pixelsPerClock = 2;
-+	// #all other modes operate at 1 pixel per clock
-+	else
-+		pixelsPerClock = 1;
-+
-+	//initial transmit delay as per PPS
-+	initalXmitDelay = dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock);
-+
-+	//compute ssm delay
-+	if (bpc == 8)
-+		D = 81;
-+	else if (bpc == 10)
-+		D = 89;
-+	else
-+		D = 113;
-+
-+	//divide by pixel per cycle to compute slice width as seen by DSC
-+	w = sliceWidth / pixelsPerClock;
-+
-+	//422 mode has an additional cycle of delay
-+	if (pixelFormat == dm_s422)
-+		s = 1;
-+	else
-+		s = 0;
-+
-+	//main calculation for the dscce
-+	ix = initalXmitDelay + 45;
-+	wx = (w + 2) / 3;
-+	p = 3 * wx - w;
-+	l0 = ix / w;
-+	a = ix + p * l0;
-+	ax = (a + 2) / 3 + D + 6 + 1;
-+	l = (ax + wx - 1) / wx;
-+	if ((ix % w) == 0 && p != 0)
-+		lstall = 1;
-+	else
-+		lstall = 0;
-+	Delay = l * wx * (numSlices - 1) + ax + s + lstall + 22;
-+
-+	//dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels
-+	pixels = Delay * 3 * pixelsPerClock;
-+	return pixels;
-+}
-+
-+static unsigned int dscComputeDelay(enum output_format_class pixelFormat)
-+{
-+	unsigned int Delay = 0;
-+
-+	if (pixelFormat == dm_420) {
-+		//   sfr
-+		Delay = Delay + 2;
-+		//   dsccif
-+		Delay = Delay + 0;
-+		//   dscc - input deserializer
-+		Delay = Delay + 3;
-+		//   dscc gets pixels every other cycle
-+		Delay = Delay + 2;
-+		//   dscc - input cdc fifo
-+		Delay = Delay + 12;
-+		//   dscc gets pixels every other cycle
-+		Delay = Delay + 13;
-+		//   dscc - cdc uncertainty
-+		Delay = Delay + 2;
-+		//   dscc - output cdc fifo
-+		Delay = Delay + 7;
-+		//   dscc gets pixels every other cycle
-+		Delay = Delay + 3;
-+		//   dscc - cdc uncertainty
-+		Delay = Delay + 2;
-+		//   dscc - output serializer
-+		Delay = Delay + 1;
-+		//   sft
-+		Delay = Delay + 1;
-+	} else if (pixelFormat == dm_n422) {
-+		//   sfr
-+		Delay = Delay + 2;
-+		//   dsccif
-+		Delay = Delay + 1;
-+		//   dscc - input deserializer
-+		Delay = Delay + 5;
-+		//  dscc - input cdc fifo
-+		Delay = Delay + 25;
-+		//   dscc - cdc uncertainty
-+		Delay = Delay + 2;
-+		//   dscc - output cdc fifo
-+		Delay = Delay + 10;
-+		//   dscc - cdc uncertainty
-+		Delay = Delay + 2;
-+		//   dscc - output serializer
-+		Delay = Delay + 1;
-+		//   sft
-+		Delay = Delay + 1;
-+	} else {
-+		//   sfr
-+		Delay = Delay + 2;
-+		//   dsccif
-+		Delay = Delay + 0;
-+		//   dscc - input deserializer
-+		Delay = Delay + 3;
-+		//   dscc - input cdc fifo
-+		Delay = Delay + 12;
-+		//   dscc - cdc uncertainty
-+		Delay = Delay + 2;
-+		//   dscc - output cdc fifo
-+		Delay = Delay + 7;
-+		//   dscc - output serializer
-+		Delay = Delay + 1;
-+		//   dscc - cdc uncertainty
-+		Delay = Delay + 2;
-+		//   sft
-+		Delay = Delay + 1;
-+	}
-+
-+	return Delay;
-+}
-+
-+static bool CalculatePrefetchSchedule(
-+		struct display_mode_lib *mode_lib,
-+		double DPPCLK,
-+		double DISPCLK,
-+		double PixelClock,
-+		double DCFClkDeepSleep,
-+		unsigned int DSCDelay,
-+		unsigned int DPPPerPlane,
-+		bool ScalerEnabled,
-+		unsigned int NumberOfCursors,
-+		double DPPCLKDelaySubtotal,
-+		double DPPCLKDelaySCL,
-+		double DPPCLKDelaySCLLBOnly,
-+		double DPPCLKDelayCNVCFormater,
-+		double DPPCLKDelayCNVCCursor,
-+		double DISPCLKDelaySubtotal,
-+		unsigned int ScalerRecoutWidth,
-+		enum output_format_class OutputFormat,
-+		unsigned int VBlank,
-+		unsigned int HTotal,
-+		unsigned int MaxInterDCNTileRepeaters,
-+		unsigned int VStartup,
-+		unsigned int PageTableLevels,
-+		bool VirtualMemoryEnable,
-+		bool DynamicMetadataEnable,
-+		unsigned int DynamicMetadataLinesBeforeActiveRequired,
-+		unsigned int DynamicMetadataTransmittedBytes,
-+		bool DCCEnable,
-+		double UrgentLatency,
-+		double UrgentExtraLatency,
-+		double TCalc,
-+		unsigned int PDEAndMetaPTEBytesFrame,
-+		unsigned int MetaRowByte,
-+		unsigned int PixelPTEBytesPerRow,
-+		double PrefetchSourceLinesY,
-+		unsigned int SwathWidthY,
-+		double BytePerPixelDETY,
-+		double VInitPreFillY,
-+		unsigned int MaxNumSwathY,
-+		double PrefetchSourceLinesC,
-+		double BytePerPixelDETC,
-+		double VInitPreFillC,
-+		unsigned int MaxNumSwathC,
-+		unsigned int SwathHeightY,
-+		unsigned int SwathHeightC,
-+		double TWait,
-+		bool XFCEnabled,
-+		double XFCRemoteSurfaceFlipDelay,
-+		bool InterlaceEnable,
-+		bool ProgressiveToInterlaceUnitInOPP,
-+		double *DSTXAfterScaler,
-+		double *DSTYAfterScaler,
-+		double *DestinationLinesForPrefetch,
-+		double *PrefetchBandwidth,
-+		double *DestinationLinesToRequestVMInVBlank,
-+		double *DestinationLinesToRequestRowInVBlank,
-+		double *VRatioPrefetchY,
-+		double *VRatioPrefetchC,
-+		double *RequiredPrefetchPixDataBW,
-+		unsigned int *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata,
-+		double *Tno_bw,
-+		unsigned int *VUpdateOffsetPix,
-+		unsigned int *VUpdateWidthPix,
-+		unsigned int *VReadyOffsetPix)
-+{
-+	bool MyError = false;
-+	unsigned int DPPCycles, DISPCLKCycles;
-+	double DSTTotalPixelsAfterScaler, TotalRepeaterDelayTime;
-+	double Tdm, LineTime, Tsetup;
-+	double dst_y_prefetch_equ;
-+	double Tsw_oto;
-+	double prefetch_bw_oto;
-+	double Tvm_oto;
-+	double Tr0_oto;
-+	double Tpre_oto;
-+	double dst_y_prefetch_oto;
-+	double TimeForFetchingMetaPTE = 0;
-+	double TimeForFetchingRowInVBlank = 0;
-+	double LinesToRequestPrefetchPixelData = 0;
-+
-+	if (ScalerEnabled)
-+		DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCL;
-+	else
-+		DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly;
-+
-+	DPPCycles = DPPCycles + DPPCLKDelayCNVCFormater + NumberOfCursors * DPPCLKDelayCNVCCursor;
-+
-+	DISPCLKCycles = DISPCLKDelaySubtotal;
-+
-+	if (DPPCLK == 0.0 || DISPCLK == 0.0)
-+		return true;
-+
-+	*DSTXAfterScaler = DPPCycles * PixelClock / DPPCLK + DISPCLKCycles * PixelClock / DISPCLK
-+			+ DSCDelay;
-+
-+	if (DPPPerPlane > 1)
-+		*DSTXAfterScaler = *DSTXAfterScaler + ScalerRecoutWidth;
-+
-+	if (OutputFormat == dm_420 || (InterlaceEnable && ProgressiveToInterlaceUnitInOPP))
-+		*DSTYAfterScaler = 1;
-+	else
-+		*DSTYAfterScaler = 0;
-+
-+	DSTTotalPixelsAfterScaler = ((double) (*DSTYAfterScaler * HTotal)) + *DSTXAfterScaler;
-+	*DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / HTotal, 1);
-+	*DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * HTotal));
-+
-+	*VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1);
-+	TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK);
-+	*VUpdateWidthPix = (14.0 / DCFClkDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime)
-+			* PixelClock;
-+
-+	*VReadyOffsetPix = dml_max(
-+			150.0 / DPPCLK,
-+			TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / DPPCLK)
-+			* PixelClock;
-+
-+	Tsetup = (double) (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock;
-+
-+	LineTime = (double) HTotal / PixelClock;
-+
-+	if (DynamicMetadataEnable) {
-+		double Tdmbf, Tdmec, Tdmsks;
-+
-+		Tdm = dml_max(0.0, UrgentExtraLatency - TCalc);
-+		Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK;
-+		Tdmec = LineTime;
-+		if (DynamicMetadataLinesBeforeActiveRequired == 0)
-+			Tdmsks = VBlank * LineTime / 2.0;
-+		else
-+			Tdmsks = DynamicMetadataLinesBeforeActiveRequired * LineTime;
-+		if (InterlaceEnable && !ProgressiveToInterlaceUnitInOPP)
-+			Tdmsks = Tdmsks / 2;
-+		if (VStartup * LineTime
-+				< Tsetup + TWait + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) {
-+			MyError = true;
-+			*VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (Tsetup + TWait
-+					+ UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) / LineTime;
-+		} else
-+			*VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = 0.0;
-+	} else
-+		Tdm = 0;
-+
-+	if (VirtualMemoryEnable) {
-+		if (PageTableLevels == 4)
-+			*Tno_bw = UrgentExtraLatency + UrgentLatency;
-+		else if (PageTableLevels == 3)
-+			*Tno_bw = UrgentExtraLatency;
-+		else
-+			*Tno_bw = 0;
-+	} else if (DCCEnable)
-+		*Tno_bw = LineTime;
-+	else
-+		*Tno_bw = LineTime / 4;
-+
-+	dst_y_prefetch_equ = VStartup - dml_max(TCalc + TWait, XFCRemoteSurfaceFlipDelay) / LineTime
-+			- (Tsetup + Tdm) / LineTime
-+			- (*DSTYAfterScaler + *DSTXAfterScaler / HTotal);
-+
-+	Tsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime;
-+
-+	prefetch_bw_oto = (MetaRowByte + PixelPTEBytesPerRow
-+			+ PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1)
-+			+ PrefetchSourceLinesC * SwathWidthY / 2 * dml_ceil(BytePerPixelDETC, 2))
-+			/ Tsw_oto;
-+
-+	if (VirtualMemoryEnable == true) {
-+		Tvm_oto =
-+				dml_max(
-+						*Tno_bw + PDEAndMetaPTEBytesFrame / prefetch_bw_oto,
-+						dml_max(
-+								UrgentExtraLatency
-+										+ UrgentLatency
-+												* (PageTableLevels
-+														- 1),
-+								LineTime / 4.0));
-+	} else
-+		Tvm_oto = LineTime / 4.0;
-+
-+	if ((VirtualMemoryEnable == true || DCCEnable == true)) {
-+		Tr0_oto = dml_max(
-+				(MetaRowByte + PixelPTEBytesPerRow) / prefetch_bw_oto,
-+				dml_max(UrgentLatency, dml_max(LineTime - Tvm_oto, LineTime / 4)));
-+	} else
-+		Tr0_oto = LineTime - Tvm_oto;
-+
-+	Tpre_oto = Tvm_oto + Tr0_oto + Tsw_oto;
-+
-+	dst_y_prefetch_oto = Tpre_oto / LineTime;
-+
-+	if (dst_y_prefetch_oto < dst_y_prefetch_equ)
-+		*DestinationLinesForPrefetch = dst_y_prefetch_oto;
-+	else
-+		*DestinationLinesForPrefetch = dst_y_prefetch_equ;
-+
-+	*DestinationLinesForPrefetch = dml_floor(4.0 * (*DestinationLinesForPrefetch + 0.125), 1)
-+			/ 4;
-+
-+	dml_print("DML: VStartup: %d\n", VStartup);
-+	dml_print("DML: TCalc: %f\n", TCalc);
-+	dml_print("DML: TWait: %f\n", TWait);
-+	dml_print("DML: XFCRemoteSurfaceFlipDelay: %f\n", XFCRemoteSurfaceFlipDelay);
-+	dml_print("DML: LineTime: %f\n", LineTime);
-+	dml_print("DML: Tsetup: %f\n", Tsetup);
-+	dml_print("DML: Tdm: %f\n", Tdm);
-+	dml_print("DML: DSTYAfterScaler: %f\n", *DSTYAfterScaler);
-+	dml_print("DML: DSTXAfterScaler: %f\n", *DSTXAfterScaler);
-+	dml_print("DML: HTotal: %d\n", HTotal);
-+
-+	*PrefetchBandwidth = 0;
-+	*DestinationLinesToRequestVMInVBlank = 0;
-+	*DestinationLinesToRequestRowInVBlank = 0;
-+	*VRatioPrefetchY = 0;
-+	*VRatioPrefetchC = 0;
-+	*RequiredPrefetchPixDataBW = 0;
-+	if (*DestinationLinesForPrefetch > 1) {
-+		*PrefetchBandwidth = (PDEAndMetaPTEBytesFrame + 2 * MetaRowByte
-+				+ 2 * PixelPTEBytesPerRow
-+				+ PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1)
-+				+ PrefetchSourceLinesC * SwathWidthY / 2
-+						* dml_ceil(BytePerPixelDETC, 2))
-+				/ (*DestinationLinesForPrefetch * LineTime - *Tno_bw);
-+		if (VirtualMemoryEnable) {
-+			TimeForFetchingMetaPTE =
-+					dml_max(
-+							*Tno_bw
-+									+ (double) PDEAndMetaPTEBytesFrame
-+											/ *PrefetchBandwidth,
-+							dml_max(
-+									UrgentExtraLatency
-+											+ UrgentLatency
-+													* (PageTableLevels
-+															- 1),
-+									LineTime / 4));
-+		} else {
-+			if (NumberOfCursors > 0 || XFCEnabled)
-+				TimeForFetchingMetaPTE = LineTime / 4;
-+			else
-+				TimeForFetchingMetaPTE = 0.0;
-+		}
-+
-+		if ((VirtualMemoryEnable == true || DCCEnable == true)) {
-+			TimeForFetchingRowInVBlank =
-+					dml_max(
-+							(MetaRowByte + PixelPTEBytesPerRow)
-+									/ *PrefetchBandwidth,
-+							dml_max(
-+									UrgentLatency,
-+									dml_max(
-+											LineTime
-+													- TimeForFetchingMetaPTE,
-+											LineTime
-+													/ 4.0)));
-+		} else {
-+			if (NumberOfCursors > 0 || XFCEnabled)
-+				TimeForFetchingRowInVBlank = LineTime - TimeForFetchingMetaPTE;
-+			else
-+				TimeForFetchingRowInVBlank = 0.0;
-+		}
-+
-+		*DestinationLinesToRequestVMInVBlank = dml_floor(
-+				4.0 * (TimeForFetchingMetaPTE / LineTime + 0.125),
-+				1) / 4.0;
-+
-+		*DestinationLinesToRequestRowInVBlank = dml_floor(
-+				4.0 * (TimeForFetchingRowInVBlank / LineTime + 0.125),
-+				1) / 4.0;
-+
-+		LinesToRequestPrefetchPixelData =
-+				*DestinationLinesForPrefetch
-+						- ((NumberOfCursors > 0 || VirtualMemoryEnable
-+								|| DCCEnable) ?
-+								(*DestinationLinesToRequestVMInVBlank
-+										+ *DestinationLinesToRequestRowInVBlank) :
-+								0.0);
-+
-+		if (LinesToRequestPrefetchPixelData > 0) {
-+
-+			*VRatioPrefetchY = (double) PrefetchSourceLinesY
-+					/ LinesToRequestPrefetchPixelData;
-+			*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
-+			if ((SwathHeightY > 4) && (VInitPreFillY > 3)) {
-+				if (LinesToRequestPrefetchPixelData > (VInitPreFillY - 3.0) / 2.0) {
-+					*VRatioPrefetchY =
-+							dml_max(
-+									(double) PrefetchSourceLinesY
-+											/ LinesToRequestPrefetchPixelData,
-+									(double) MaxNumSwathY
-+											* SwathHeightY
-+											/ (LinesToRequestPrefetchPixelData
-+													- (VInitPreFillY
-+															- 3.0)
-+															/ 2.0));
-+					*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
-+				} else {
-+					MyError = true;
-+					*VRatioPrefetchY = 0;
-+				}
-+			}
-+
-+			*VRatioPrefetchC = (double) PrefetchSourceLinesC
-+					/ LinesToRequestPrefetchPixelData;
-+			*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
-+
-+			if ((SwathHeightC > 4)) {
-+				if (LinesToRequestPrefetchPixelData > (VInitPreFillC - 3.0) / 2.0) {
-+					*VRatioPrefetchC =
-+							dml_max(
-+									*VRatioPrefetchC,
-+									(double) MaxNumSwathC
-+											* SwathHeightC
-+											/ (LinesToRequestPrefetchPixelData
-+													- (VInitPreFillC
-+															- 3.0)
-+															/ 2.0));
-+					*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
-+				} else {
-+					MyError = true;
-+					*VRatioPrefetchC = 0;
-+				}
-+			}
-+
-+			*RequiredPrefetchPixDataBW =
-+					DPPPerPlane
-+							* ((double) PrefetchSourceLinesY
-+									/ LinesToRequestPrefetchPixelData
-+									* dml_ceil(
-+											BytePerPixelDETY,
-+											1)
-+									+ (double) PrefetchSourceLinesC
-+											/ LinesToRequestPrefetchPixelData
-+											* dml_ceil(
-+													BytePerPixelDETC,
-+													2)
-+											/ 2)
-+							* SwathWidthY / LineTime;
-+		} else {
-+			MyError = true;
-+			*VRatioPrefetchY = 0;
-+			*VRatioPrefetchC = 0;
-+			*RequiredPrefetchPixDataBW = 0;
-+		}
-+
-+	} else {
-+		MyError = true;
-+	}
-+
-+	if (MyError) {
-+		*PrefetchBandwidth = 0;
-+		TimeForFetchingMetaPTE = 0;
-+		TimeForFetchingRowInVBlank = 0;
-+		*DestinationLinesToRequestVMInVBlank = 0;
-+		*DestinationLinesToRequestRowInVBlank = 0;
-+		*DestinationLinesForPrefetch = 0;
-+		LinesToRequestPrefetchPixelData = 0;
-+		*VRatioPrefetchY = 0;
-+		*VRatioPrefetchC = 0;
-+		*RequiredPrefetchPixDataBW = 0;
-+	}
-+
-+	return MyError;
-+}
-+
-+static double RoundToDFSGranularityUp(double Clock, double VCOSpeed)
-+{
-+	return VCOSpeed * 4 / dml_floor(VCOSpeed * 4 / Clock, 1);
-+}
-+
-+static double RoundToDFSGranularityDown(double Clock, double VCOSpeed)
-+{
-+	return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1);
-+}
-+
-+static double CalculatePrefetchSourceLines(
-+		struct display_mode_lib *mode_lib,
-+		double VRatio,
-+		double vtaps,
-+		bool Interlace,
-+		bool ProgressiveToInterlaceUnitInOPP,
-+		unsigned int SwathHeight,
-+		unsigned int ViewportYStart,
-+		double *VInitPreFill,
-+		unsigned int *MaxNumSwath)
-+{
-+	unsigned int MaxPartialSwath;
-+
-+	if (ProgressiveToInterlaceUnitInOPP)
-+		*VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1);
-+	else
-+		*VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
-+
-+	if (!mode_lib->vba.IgnoreViewportPositioning) {
-+
-+		*MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0;
-+
-+		if (*VInitPreFill > 1.0)
-+			MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight;
-+		else
-+			MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2)
-+					% SwathHeight;
-+		MaxPartialSwath = dml_max(1U, MaxPartialSwath);
-+
-+	} else {
-+
-+		if (ViewportYStart != 0)
-+			dml_print(
-+					"WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n");
-+
-+		*MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1);
-+
-+		if (*VInitPreFill > 1.0)
-+			MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight;
-+		else
-+			MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 1)
-+					% SwathHeight;
-+	}
-+
-+	return *MaxNumSwath * SwathHeight + MaxPartialSwath;
-+}
-+
-+static unsigned int CalculateVMAndRowBytes(
-+		struct display_mode_lib *mode_lib,
-+		bool DCCEnable,
-+		unsigned int BlockHeight256Bytes,
-+		unsigned int BlockWidth256Bytes,
-+		enum source_format_class SourcePixelFormat,
-+		unsigned int SurfaceTiling,
-+		unsigned int BytePerPixel,
-+		enum scan_direction_class ScanDirection,
-+		unsigned int ViewportWidth,
-+		unsigned int ViewportHeight,
-+		unsigned int SwathWidth,
-+		bool VirtualMemoryEnable,
-+		unsigned int VMMPageSize,
-+		unsigned int PTEBufferSizeInRequests,
-+		unsigned int PDEProcessingBufIn64KBReqs,
-+		unsigned int Pitch,
-+		unsigned int DCCMetaPitch,
-+		unsigned int *MacroTileWidth,
-+		unsigned int *MetaRowByte,
-+		unsigned int *PixelPTEBytesPerRow,
-+		bool *PTEBufferSizeNotExceeded,
-+		unsigned int *dpte_row_height,
-+		unsigned int *meta_row_height)
-+{
-+	unsigned int MetaRequestHeight;
-+	unsigned int MetaRequestWidth;
-+	unsigned int MetaSurfWidth;
-+	unsigned int MetaSurfHeight;
-+	unsigned int MPDEBytesFrame;
-+	unsigned int MetaPTEBytesFrame;
-+	unsigned int DCCMetaSurfaceBytes;
-+
-+	unsigned int MacroTileSizeBytes;
-+	unsigned int MacroTileHeight;
-+	unsigned int DPDE0BytesFrame;
-+	unsigned int ExtraDPDEBytesFrame;
-+	unsigned int PDEAndMetaPTEBytesFrame;
-+
-+	if (DCCEnable == true) {
-+		MetaRequestHeight = 8 * BlockHeight256Bytes;
-+		MetaRequestWidth = 8 * BlockWidth256Bytes;
-+		if (ScanDirection == dm_horz) {
-+			*meta_row_height = MetaRequestHeight;
-+			MetaSurfWidth = dml_ceil((double) SwathWidth - 1, MetaRequestWidth)
-+					+ MetaRequestWidth;
-+			*MetaRowByte = MetaSurfWidth * MetaRequestHeight * BytePerPixel / 256.0;
-+		} else {
-+			*meta_row_height = MetaRequestWidth;
-+			MetaSurfHeight = dml_ceil((double) SwathWidth - 1, MetaRequestHeight)
-+					+ MetaRequestHeight;
-+			*MetaRowByte = MetaSurfHeight * MetaRequestWidth * BytePerPixel / 256.0;
-+		}
-+		if (ScanDirection == dm_horz) {
-+			DCCMetaSurfaceBytes = DCCMetaPitch
-+					* (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes)
-+							+ 64 * BlockHeight256Bytes) * BytePerPixel
-+					/ 256;
-+		} else {
-+			DCCMetaSurfaceBytes = DCCMetaPitch
-+					* (dml_ceil(
-+							(double) ViewportHeight - 1,
-+							64 * BlockHeight256Bytes)
-+							+ 64 * BlockHeight256Bytes) * BytePerPixel
-+					/ 256;
-+		}
-+		if (VirtualMemoryEnable == true) {
-+			MetaPTEBytesFrame = (dml_ceil(
-+					(double) (DCCMetaSurfaceBytes - VMMPageSize)
-+							/ (8 * VMMPageSize),
-+					1) + 1) * 64;
-+			MPDEBytesFrame = 128 * (mode_lib->vba.MaxPageTableLevels - 1);
-+		} else {
-+			MetaPTEBytesFrame = 0;
-+			MPDEBytesFrame = 0;
-+		}
-+	} else {
-+		MetaPTEBytesFrame = 0;
-+		MPDEBytesFrame = 0;
-+		*MetaRowByte = 0;
-+	}
-+
-+	if (SurfaceTiling == dm_sw_linear) {
-+		MacroTileSizeBytes = 256;
-+		MacroTileHeight = 1;
-+	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
-+			|| SurfaceTiling == dm_sw_4kb_d || SurfaceTiling == dm_sw_4kb_d_x) {
-+		MacroTileSizeBytes = 4096;
-+		MacroTileHeight = 4 * BlockHeight256Bytes;
-+	} else if (SurfaceTiling == dm_sw_64kb_s || SurfaceTiling == dm_sw_64kb_s_t
-+			|| SurfaceTiling == dm_sw_64kb_s_x || SurfaceTiling == dm_sw_64kb_d
-+			|| SurfaceTiling == dm_sw_64kb_d_t || SurfaceTiling == dm_sw_64kb_d_x
-+			|| SurfaceTiling == dm_sw_64kb_r_x) {
-+		MacroTileSizeBytes = 65536;
-+		MacroTileHeight = 16 * BlockHeight256Bytes;
-+	} else {
-+		MacroTileSizeBytes = 262144;
-+		MacroTileHeight = 32 * BlockHeight256Bytes;
-+	}
-+	*MacroTileWidth = MacroTileSizeBytes / BytePerPixel / MacroTileHeight;
-+
-+	if (VirtualMemoryEnable == true && mode_lib->vba.MaxPageTableLevels > 1) {
-+		if (ScanDirection == dm_horz) {
-+			DPDE0BytesFrame =
-+					64
-+							* (dml_ceil(
-+									((Pitch
-+											* (dml_ceil(
-+													ViewportHeight
-+															- 1,
-+													MacroTileHeight)
-+													+ MacroTileHeight)
-+											* BytePerPixel)
-+											- MacroTileSizeBytes)
-+											/ (8
-+													* 2097152),
-+									1) + 1);
-+		} else {
-+			DPDE0BytesFrame =
-+					64
-+							* (dml_ceil(
-+									((Pitch
-+											* (dml_ceil(
-+													(double) SwathWidth
-+															- 1,
-+													MacroTileHeight)
-+													+ MacroTileHeight)
-+											* BytePerPixel)
-+											- MacroTileSizeBytes)
-+											/ (8
-+													* 2097152),
-+									1) + 1);
-+		}
-+		ExtraDPDEBytesFrame = 128 * (mode_lib->vba.MaxPageTableLevels - 2);
-+	} else {
-+		DPDE0BytesFrame = 0;
-+		ExtraDPDEBytesFrame = 0;
-+	}
-+
-+	PDEAndMetaPTEBytesFrame = MetaPTEBytesFrame + MPDEBytesFrame + DPDE0BytesFrame
-+			+ ExtraDPDEBytesFrame;
-+
-+	if (VirtualMemoryEnable == true) {
-+		unsigned int PTERequestSize;
-+		unsigned int PixelPTEReqHeight;
-+		unsigned int PixelPTEReqWidth;
-+		double FractionOfPTEReturnDrop;
-+		unsigned int EffectivePDEProcessingBufIn64KBReqs;
-+
-+		if (SurfaceTiling == dm_sw_linear) {
-+			PixelPTEReqHeight = 1;
-+			PixelPTEReqWidth = 8.0 * VMMPageSize / BytePerPixel;
-+			PTERequestSize = 64;
-+			FractionOfPTEReturnDrop = 0;
-+		} else if (MacroTileSizeBytes == 4096) {
-+			PixelPTEReqHeight = MacroTileHeight;
-+			PixelPTEReqWidth = 8 * *MacroTileWidth;
-+			PTERequestSize = 64;
-+			if (ScanDirection == dm_horz)
-+				FractionOfPTEReturnDrop = 0;
-+			else
-+				FractionOfPTEReturnDrop = 7 / 8;
-+		} else if (VMMPageSize == 4096 && MacroTileSizeBytes > 4096) {
-+			PixelPTEReqHeight = 16 * BlockHeight256Bytes;
-+			PixelPTEReqWidth = 16 * BlockWidth256Bytes;
-+			PTERequestSize = 128;
-+			FractionOfPTEReturnDrop = 0;
-+		} else {
-+			PixelPTEReqHeight = MacroTileHeight;
-+			PixelPTEReqWidth = 8 * *MacroTileWidth;
-+			PTERequestSize = 64;
-+			FractionOfPTEReturnDrop = 0;
-+		}
-+
-+		if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10)
-+			EffectivePDEProcessingBufIn64KBReqs = PDEProcessingBufIn64KBReqs / 2;
-+		else
-+			EffectivePDEProcessingBufIn64KBReqs = PDEProcessingBufIn64KBReqs;
-+
-+		if (SurfaceTiling == dm_sw_linear) {
-+			*dpte_row_height =
-+					dml_min(
-+							128,
-+							1
-+									<< (unsigned int) dml_floor(
-+											dml_log2(
-+													dml_min(
-+															(double) PTEBufferSizeInRequests
-+																	* PixelPTEReqWidth,
-+															EffectivePDEProcessingBufIn64KBReqs
-+																	* 65536.0
-+																	/ BytePerPixel)
-+															/ Pitch),
-+											1));
-+			*PixelPTEBytesPerRow = PTERequestSize
-+					* (dml_ceil(
-+							(double) (Pitch * *dpte_row_height - 1)
-+									/ PixelPTEReqWidth,
-+							1) + 1);
-+		} else if (ScanDirection == dm_horz) {
-+			*dpte_row_height = PixelPTEReqHeight;
-+			*PixelPTEBytesPerRow = PTERequestSize
-+					* (dml_ceil(((double) SwathWidth - 1) / PixelPTEReqWidth, 1)
-+							+ 1);
-+		} else {
-+			*dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth);
-+			*PixelPTEBytesPerRow = PTERequestSize
-+					* (dml_ceil(
-+							((double) SwathWidth - 1)
-+									/ PixelPTEReqHeight,
-+							1) + 1);
-+		}
-+		if (*PixelPTEBytesPerRow * (1 - FractionOfPTEReturnDrop)
-+				<= 64 * PTEBufferSizeInRequests) {
-+			*PTEBufferSizeNotExceeded = true;
-+		} else {
-+			*PTEBufferSizeNotExceeded = false;
-+		}
-+	} else {
-+		*PixelPTEBytesPerRow = 0;
-+		*PTEBufferSizeNotExceeded = true;
-+	}
-+
-+	return PDEAndMetaPTEBytesFrame;
-+}
-+
-+static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
-+		struct display_mode_lib *mode_lib)
-+{
-+	unsigned int j, k;
-+
-+	mode_lib->vba.WritebackDISPCLK = 0.0;
-+	mode_lib->vba.DISPCLKWithRamping = 0;
-+	mode_lib->vba.DISPCLKWithoutRamping = 0;
-+	mode_lib->vba.GlobalDPPCLK = 0.0;
-+
-+	// dml_ml->vba.DISPCLK and dml_ml->vba.DPPCLK Calculation
-+	//
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		if (mode_lib->vba.WritebackEnable[k]) {
-+			mode_lib->vba.WritebackDISPCLK =
-+					dml_max(
-+							mode_lib->vba.WritebackDISPCLK,
-+							CalculateWriteBackDISPCLK(
-+									mode_lib->vba.WritebackPixelFormat[k],
-+									mode_lib->vba.PixelClock[k],
-+									mode_lib->vba.WritebackHRatio[k],
-+									mode_lib->vba.WritebackVRatio[k],
-+									mode_lib->vba.WritebackLumaHTaps[k],
-+									mode_lib->vba.WritebackLumaVTaps[k],
-+									mode_lib->vba.WritebackChromaHTaps[k],
-+									mode_lib->vba.WritebackChromaVTaps[k],
-+									mode_lib->vba.WritebackDestinationWidth[k],
-+									mode_lib->vba.HTotal[k],
-+									mode_lib->vba.WritebackChromaLineBufferWidth));
-+		}
-+	}
-+
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		if (mode_lib->vba.HRatio[k] > 1) {
-+			mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
-+					mode_lib->vba.MaxDCHUBToPSCLThroughput,
-+					mode_lib->vba.MaxPSCLToLBThroughput
-+							* mode_lib->vba.HRatio[k]
-+							/ dml_ceil(
-+									mode_lib->vba.htaps[k]
-+											/ 6.0,
-+									1));
-+		} else {
-+			mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
-+					mode_lib->vba.MaxDCHUBToPSCLThroughput,
-+					mode_lib->vba.MaxPSCLToLBThroughput);
-+		}
-+
-+		mode_lib->vba.DPPCLKUsingSingleDPPLuma =
-+				mode_lib->vba.PixelClock[k]
-+						* dml_max(
-+								mode_lib->vba.vtaps[k] / 6.0
-+										* dml_min(
-+												1.0,
-+												mode_lib->vba.HRatio[k]),
-+								dml_max(
-+										mode_lib->vba.HRatio[k]
-+												* mode_lib->vba.VRatio[k]
-+												/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k],
-+										1.0));
-+
-+		if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6)
-+				&& mode_lib->vba.DPPCLKUsingSingleDPPLuma
-+						< 2 * mode_lib->vba.PixelClock[k]) {
-+			mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k];
-+		}
-+
-+		if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
-+				&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
-+			mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = 0.0;
-+			mode_lib->vba.DPPCLKUsingSingleDPP[k] =
-+					mode_lib->vba.DPPCLKUsingSingleDPPLuma;
-+		} else {
-+			if (mode_lib->vba.HRatio[k] > 1) {
-+				mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] =
-+						dml_min(
-+								mode_lib->vba.MaxDCHUBToPSCLThroughput,
-+								mode_lib->vba.MaxPSCLToLBThroughput
-+										* mode_lib->vba.HRatio[k]
-+										/ 2
-+										/ dml_ceil(
-+												mode_lib->vba.HTAPsChroma[k]
-+														/ 6.0,
-+												1.0));
-+			} else {
-+				mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = dml_min(
-+						mode_lib->vba.MaxDCHUBToPSCLThroughput,
-+						mode_lib->vba.MaxPSCLToLBThroughput);
-+			}
-+			mode_lib->vba.DPPCLKUsingSingleDPPChroma =
-+					mode_lib->vba.PixelClock[k]
-+							* dml_max(
-+									mode_lib->vba.VTAPsChroma[k]
-+											/ 6.0
-+											* dml_min(
-+													1.0,
-+													mode_lib->vba.HRatio[k]
-+															/ 2),
-+									dml_max(
-+											mode_lib->vba.HRatio[k]
-+													* mode_lib->vba.VRatio[k]
-+													/ 4
-+													/ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k],
-+											1.0));
-+
-+			if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6)
-+					&& mode_lib->vba.DPPCLKUsingSingleDPPChroma
-+							< 2 * mode_lib->vba.PixelClock[k]) {
-+				mode_lib->vba.DPPCLKUsingSingleDPPChroma = 2
-+						* mode_lib->vba.PixelClock[k];
-+			}
-+
-+			mode_lib->vba.DPPCLKUsingSingleDPP[k] = dml_max(
-+					mode_lib->vba.DPPCLKUsingSingleDPPLuma,
-+					mode_lib->vba.DPPCLKUsingSingleDPPChroma);
-+		}
-+	}
-+
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		if (mode_lib->vba.BlendingAndTiming[k] != k)
-+			continue;
-+		if (mode_lib->vba.ODMCombineEnabled[k]) {
-+			mode_lib->vba.DISPCLKWithRamping =
-+					dml_max(
-+							mode_lib->vba.DISPCLKWithRamping,
-+							mode_lib->vba.PixelClock[k] / 2
-+									* (1
-+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+													/ 100)
-+									* (1
-+											+ mode_lib->vba.DISPCLKRampingMargin
-+													/ 100));
-+			mode_lib->vba.DISPCLKWithoutRamping =
-+					dml_max(
-+							mode_lib->vba.DISPCLKWithoutRamping,
-+							mode_lib->vba.PixelClock[k] / 2
-+									* (1
-+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+													/ 100));
-+		} else if (!mode_lib->vba.ODMCombineEnabled[k]) {
-+			mode_lib->vba.DISPCLKWithRamping =
-+					dml_max(
-+							mode_lib->vba.DISPCLKWithRamping,
-+							mode_lib->vba.PixelClock[k]
-+									* (1
-+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+													/ 100)
-+									* (1
-+											+ mode_lib->vba.DISPCLKRampingMargin
-+													/ 100));
-+			mode_lib->vba.DISPCLKWithoutRamping =
-+					dml_max(
-+							mode_lib->vba.DISPCLKWithoutRamping,
-+							mode_lib->vba.PixelClock[k]
-+									* (1
-+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+													/ 100));
-+		}
-+	}
-+
-+	mode_lib->vba.DISPCLKWithRamping = dml_max(
-+			mode_lib->vba.DISPCLKWithRamping,
-+			mode_lib->vba.WritebackDISPCLK);
-+	mode_lib->vba.DISPCLKWithoutRamping = dml_max(
-+			mode_lib->vba.DISPCLKWithoutRamping,
-+			mode_lib->vba.WritebackDISPCLK);
-+
-+	ASSERT(mode_lib->vba.DISPCLKDPPCLKVCOSpeed != 0);
-+	mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(
-+			mode_lib->vba.DISPCLKWithRamping,
-+			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
-+	mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(
-+			mode_lib->vba.DISPCLKWithoutRamping,
-+			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
-+	mode_lib->vba.MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown(
-+			mode_lib->vba.soc.clock_limits[NumberOfStates - 1].dispclk_mhz,
-+			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
-+	if (mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity
-+			> mode_lib->vba.MaxDispclkRoundedToDFSGranularity) {
-+		mode_lib->vba.DISPCLK_calculated =
-+				mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity;
-+	} else if (mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity
-+			> mode_lib->vba.MaxDispclkRoundedToDFSGranularity) {
-+		mode_lib->vba.DISPCLK_calculated = mode_lib->vba.MaxDispclkRoundedToDFSGranularity;
-+	} else {
-+		mode_lib->vba.DISPCLK_calculated =
-+				mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity;
-+	}
-+	DTRACE("   dispclk_mhz (calculated) = %f", mode_lib->vba.DISPCLK_calculated);
-+
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.DPPCLKUsingSingleDPP[k]
-+				/ mode_lib->vba.DPPPerPlane[k]
-+				* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-+		mode_lib->vba.GlobalDPPCLK = dml_max(
-+				mode_lib->vba.GlobalDPPCLK,
-+				mode_lib->vba.DPPCLK_calculated[k]);
-+	}
-+	mode_lib->vba.GlobalDPPCLK = RoundToDFSGranularityUp(
-+			mode_lib->vba.GlobalDPPCLK,
-+			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255
-+				* dml_ceil(
-+						mode_lib->vba.DPPCLK_calculated[k] * 255
-+								/ mode_lib->vba.GlobalDPPCLK,
-+						1);
-+		DTRACE("   dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]);
-+	}
-+
-+	// Urgent Watermark
-+	mode_lib->vba.DCCEnabledAnyPlane = false;
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
-+		if (mode_lib->vba.DCCEnable[k])
-+			mode_lib->vba.DCCEnabledAnyPlane = true;
-+
-+	mode_lib->vba.ReturnBandwidthToDCN = dml_min(
-+			mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK,
-+			mode_lib->vba.FabricAndDRAMBandwidth * 1000)
-+			* mode_lib->vba.PercentOfIdealDRAMAndFabricBWReceivedAfterUrgLatency / 100;
-+
-+	mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBandwidthToDCN;
-+	mode_lib->vba.ReturnBW = adjust_ReturnBW(
-+			mode_lib,
-+			mode_lib->vba.ReturnBW,
-+			mode_lib->vba.DCCEnabledAnyPlane,
-+			mode_lib->vba.ReturnBandwidthToDCN);
-+
-+	// Let's do this calculation again??
-+	mode_lib->vba.ReturnBandwidthToDCN = dml_min(
-+			mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK,
-+			mode_lib->vba.FabricAndDRAMBandwidth * 1000);
-+	mode_lib->vba.ReturnBW = adjust_ReturnBW(
-+			mode_lib,
-+			mode_lib->vba.ReturnBW,
-+			mode_lib->vba.DCCEnabledAnyPlane,
-+			mode_lib->vba.ReturnBandwidthToDCN);
-+
-+	DTRACE("   dcfclk_mhz         = %f", mode_lib->vba.DCFCLK);
-+	DTRACE("   return_bw_to_dcn   = %f", mode_lib->vba.ReturnBandwidthToDCN);
-+	DTRACE("   return_bus_bw      = %f", mode_lib->vba.ReturnBW);
-+
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		bool MainPlaneDoesODMCombine = false;
-+
-+		if (mode_lib->vba.SourceScan[k] == dm_horz)
-+			mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k];
-+		else
-+			mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k];
-+
-+		if (mode_lib->vba.ODMCombineEnabled[k] == true)
-+			MainPlaneDoesODMCombine = true;
-+		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j)
-+			if (mode_lib->vba.BlendingAndTiming[k] == j
-+					&& mode_lib->vba.ODMCombineEnabled[j] == true)
-+				MainPlaneDoesODMCombine = true;
-+
-+		if (MainPlaneDoesODMCombine == true)
-+			mode_lib->vba.SwathWidthY[k] = dml_min(
-+					(double) mode_lib->vba.SwathWidthSingleDPPY[k],
-+					dml_round(
-+							mode_lib->vba.HActive[k] / 2.0
-+									* mode_lib->vba.HRatio[k]));
-+		else
-+			mode_lib->vba.SwathWidthY[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
-+					/ mode_lib->vba.DPPPerPlane[k];
-+	}
-+
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
-+			mode_lib->vba.BytePerPixelDETY[k] = 8;
-+			mode_lib->vba.BytePerPixelDETC[k] = 0;
-+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
-+			mode_lib->vba.BytePerPixelDETY[k] = 4;
-+			mode_lib->vba.BytePerPixelDETC[k] = 0;
-+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
-+			mode_lib->vba.BytePerPixelDETY[k] = 2;
-+			mode_lib->vba.BytePerPixelDETC[k] = 0;
-+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
-+			mode_lib->vba.BytePerPixelDETY[k] = 1;
-+			mode_lib->vba.BytePerPixelDETC[k] = 0;
-+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
-+			mode_lib->vba.BytePerPixelDETY[k] = 1;
-+			mode_lib->vba.BytePerPixelDETC[k] = 2;
-+		} else { // dm_420_10
-+			mode_lib->vba.BytePerPixelDETY[k] = 4.0 / 3.0;
-+			mode_lib->vba.BytePerPixelDETC[k] = 8.0 / 3.0;
-+		}
-+	}
-+
-+	mode_lib->vba.TotalDataReadBandwidth = 0.0;
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		mode_lib->vba.ReadBandwidthPlaneLuma[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
-+				* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1)
-+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
-+				* mode_lib->vba.VRatio[k];
-+		mode_lib->vba.ReadBandwidthPlaneChroma[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
-+				/ 2 * dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2)
-+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
-+				* mode_lib->vba.VRatio[k] / 2;
-+		DTRACE(
-+				"   read_bw[%i] = %fBps",
-+				k,
-+				mode_lib->vba.ReadBandwidthPlaneLuma[k]
-+						+ mode_lib->vba.ReadBandwidthPlaneChroma[k]);
-+		mode_lib->vba.TotalDataReadBandwidth += mode_lib->vba.ReadBandwidthPlaneLuma[k]
-+				+ mode_lib->vba.ReadBandwidthPlaneChroma[k];
-+	}
-+
-+	mode_lib->vba.TotalDCCActiveDPP = 0;
-+	mode_lib->vba.TotalActiveDPP = 0;
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP
-+				+ mode_lib->vba.DPPPerPlane[k];
-+		if (mode_lib->vba.DCCEnable[k])
-+			mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP
-+					+ mode_lib->vba.DPPPerPlane[k];
-+	}
-+
-+	mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency =
-+			(mode_lib->vba.RoundTripPingLatencyCycles + 32) / mode_lib->vba.DCFCLK
-+					+ mode_lib->vba.UrgentOutOfOrderReturnPerChannel
-+							* mode_lib->vba.NumberOfChannels
-+							/ mode_lib->vba.ReturnBW;
-+
-+	mode_lib->vba.LastPixelOfLineExtraWatermark = 0;
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		double DataFabricLineDeliveryTimeLuma, DataFabricLineDeliveryTimeChroma;
-+
-+		if (mode_lib->vba.VRatio[k] <= 1.0)
-+			mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
-+					(double) mode_lib->vba.SwathWidthY[k]
-+							* mode_lib->vba.DPPPerPlane[k]
-+							/ mode_lib->vba.HRatio[k]
-+							/ mode_lib->vba.PixelClock[k];
-+		else
-+			mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
-+					(double) mode_lib->vba.SwathWidthY[k]
-+							/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
-+							/ mode_lib->vba.DPPCLK[k];
-+
-+		DataFabricLineDeliveryTimeLuma = mode_lib->vba.SwathWidthSingleDPPY[k]
-+				* mode_lib->vba.SwathHeightY[k]
-+				* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1)
-+				/ (mode_lib->vba.ReturnBW * mode_lib->vba.ReadBandwidthPlaneLuma[k]
-+						/ mode_lib->vba.TotalDataReadBandwidth);
-+		mode_lib->vba.LastPixelOfLineExtraWatermark = dml_max(
-+				mode_lib->vba.LastPixelOfLineExtraWatermark,
-+				DataFabricLineDeliveryTimeLuma
-+						- mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k]);
-+
-+		if (mode_lib->vba.BytePerPixelDETC[k] == 0)
-+			mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = 0.0;
-+		else if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0)
-+			mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
-+					mode_lib->vba.SwathWidthY[k] / 2.0
-+							* mode_lib->vba.DPPPerPlane[k]
-+							/ (mode_lib->vba.HRatio[k] / 2.0)
-+							/ mode_lib->vba.PixelClock[k];
-+		else
-+			mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
-+					mode_lib->vba.SwathWidthY[k] / 2.0
-+							/ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
-+							/ mode_lib->vba.DPPCLK[k];
-+
-+		DataFabricLineDeliveryTimeChroma = mode_lib->vba.SwathWidthSingleDPPY[k] / 2.0
-+				* mode_lib->vba.SwathHeightC[k]
-+				* dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2)
-+				/ (mode_lib->vba.ReturnBW
-+						* mode_lib->vba.ReadBandwidthPlaneChroma[k]
-+						/ mode_lib->vba.TotalDataReadBandwidth);
-+		mode_lib->vba.LastPixelOfLineExtraWatermark =
-+				dml_max(
-+						mode_lib->vba.LastPixelOfLineExtraWatermark,
-+						DataFabricLineDeliveryTimeChroma
-+								- mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k]);
-+	}
-+
-+	mode_lib->vba.UrgentExtraLatency = mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency
-+			+ (mode_lib->vba.TotalActiveDPP * mode_lib->vba.PixelChunkSizeInKByte
-+					+ mode_lib->vba.TotalDCCActiveDPP
-+							* mode_lib->vba.MetaChunkSize) * 1024.0
-+					/ mode_lib->vba.ReturnBW;
-+
-+	if (mode_lib->vba.VirtualMemoryEnable)
-+		mode_lib->vba.UrgentExtraLatency += mode_lib->vba.TotalActiveDPP
-+				* mode_lib->vba.PTEChunkSize * 1024.0 / mode_lib->vba.ReturnBW;
-+
-+	mode_lib->vba.UrgentWatermark = mode_lib->vba.UrgentLatency
-+			+ mode_lib->vba.LastPixelOfLineExtraWatermark
-+			+ mode_lib->vba.UrgentExtraLatency;
-+
-+	DTRACE("   urgent_extra_latency = %fus", mode_lib->vba.UrgentExtraLatency);
-+	DTRACE("   wm_urgent = %fus", mode_lib->vba.UrgentWatermark);
-+
-+	mode_lib->vba.MemoryTripWatermark = mode_lib->vba.UrgentLatency;
-+
-+	mode_lib->vba.TotalActiveWriteback = 0;
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		if (mode_lib->vba.WritebackEnable[k])
-+			mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + 1;
-+	}
-+
-+	if (mode_lib->vba.TotalActiveWriteback <= 1)
-+		mode_lib->vba.WritebackUrgentWatermark = mode_lib->vba.WritebackLatency;
-+	else
-+		mode_lib->vba.WritebackUrgentWatermark = mode_lib->vba.WritebackLatency
-+				+ mode_lib->vba.WritebackChunkSize * 1024.0 / 32
-+						/ mode_lib->vba.SOCCLK;
-+
-+	DTRACE("   wm_wb_urgent = %fus", mode_lib->vba.WritebackUrgentWatermark);
-+
-+	// NB P-State/DRAM Clock Change Watermark
-+	mode_lib->vba.DRAMClockChangeWatermark = mode_lib->vba.DRAMClockChangeLatency
-+			+ mode_lib->vba.UrgentWatermark;
-+
-+	DTRACE("   wm_pstate_change = %fus", mode_lib->vba.DRAMClockChangeWatermark);
-+
-+	DTRACE("   calculating wb pstate watermark");
-+	DTRACE("      total wb outputs %d", mode_lib->vba.TotalActiveWriteback);
-+	DTRACE("      socclk frequency %f Mhz", mode_lib->vba.SOCCLK);
-+
-+	if (mode_lib->vba.TotalActiveWriteback <= 1)
-+		mode_lib->vba.WritebackDRAMClockChangeWatermark =
-+				mode_lib->vba.DRAMClockChangeLatency
-+						+ mode_lib->vba.WritebackLatency;
-+	else
-+		mode_lib->vba.WritebackDRAMClockChangeWatermark =
-+				mode_lib->vba.DRAMClockChangeLatency
-+						+ mode_lib->vba.WritebackLatency
-+						+ mode_lib->vba.WritebackChunkSize * 1024.0 / 32
-+								/ mode_lib->vba.SOCCLK;
-+
-+	DTRACE("   wm_wb_pstate %fus", mode_lib->vba.WritebackDRAMClockChangeWatermark);
-+
-+	// Stutter Efficiency
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		mode_lib->vba.LinesInDETY[k] = mode_lib->vba.DETBufferSizeY[k]
-+				/ mode_lib->vba.BytePerPixelDETY[k] / mode_lib->vba.SwathWidthY[k];
-+		mode_lib->vba.LinesInDETYRoundedDownToSwath[k] = dml_floor(
-+				mode_lib->vba.LinesInDETY[k],
-+				mode_lib->vba.SwathHeightY[k]);
-+		mode_lib->vba.FullDETBufferingTimeY[k] =
-+				mode_lib->vba.LinesInDETYRoundedDownToSwath[k]
-+						* (mode_lib->vba.HTotal[k]
-+								/ mode_lib->vba.PixelClock[k])
-+						/ mode_lib->vba.VRatio[k];
-+		if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
-+			mode_lib->vba.LinesInDETC[k] = mode_lib->vba.DETBufferSizeC[k]
-+					/ mode_lib->vba.BytePerPixelDETC[k]
-+					/ (mode_lib->vba.SwathWidthY[k] / 2);
-+			mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = dml_floor(
-+					mode_lib->vba.LinesInDETC[k],
-+					mode_lib->vba.SwathHeightC[k]);
-+			mode_lib->vba.FullDETBufferingTimeC[k] =
-+					mode_lib->vba.LinesInDETCRoundedDownToSwath[k]
-+							* (mode_lib->vba.HTotal[k]
-+									/ mode_lib->vba.PixelClock[k])
-+							/ (mode_lib->vba.VRatio[k] / 2);
-+		} else {
-+			mode_lib->vba.LinesInDETC[k] = 0;
-+			mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = 0;
-+			mode_lib->vba.FullDETBufferingTimeC[k] = 999999;
-+		}
-+	}
-+
-+	mode_lib->vba.MinFullDETBufferingTime = 999999.0;
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		if (mode_lib->vba.FullDETBufferingTimeY[k]
-+				< mode_lib->vba.MinFullDETBufferingTime) {
-+			mode_lib->vba.MinFullDETBufferingTime =
-+					mode_lib->vba.FullDETBufferingTimeY[k];
-+			mode_lib->vba.FrameTimeForMinFullDETBufferingTime =
-+					(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
-+							/ mode_lib->vba.PixelClock[k];
-+		}
-+		if (mode_lib->vba.FullDETBufferingTimeC[k]
-+				< mode_lib->vba.MinFullDETBufferingTime) {
-+			mode_lib->vba.MinFullDETBufferingTime =
-+					mode_lib->vba.FullDETBufferingTimeC[k];
-+			mode_lib->vba.FrameTimeForMinFullDETBufferingTime =
-+					(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
-+							/ mode_lib->vba.PixelClock[k];
-+		}
-+	}
-+
-+	mode_lib->vba.AverageReadBandwidthGBytePerSecond = 0.0;
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		if (mode_lib->vba.DCCEnable[k]) {
-+			mode_lib->vba.AverageReadBandwidthGBytePerSecond =
-+					mode_lib->vba.AverageReadBandwidthGBytePerSecond
-+							+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
-+									/ mode_lib->vba.DCCRate[k]
-+									/ 1000
-+							+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
-+									/ mode_lib->vba.DCCRate[k]
-+									/ 1000;
-+		} else {
-+			mode_lib->vba.AverageReadBandwidthGBytePerSecond =
-+					mode_lib->vba.AverageReadBandwidthGBytePerSecond
-+							+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
-+									/ 1000
-+							+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
-+									/ 1000;
-+		}
-+		if (mode_lib->vba.DCCEnable[k]) {
-+			mode_lib->vba.AverageReadBandwidthGBytePerSecond =
-+					mode_lib->vba.AverageReadBandwidthGBytePerSecond
-+							+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
-+									/ 1000 / 256
-+							+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
-+									/ 1000 / 256;
-+		}
-+		if (mode_lib->vba.VirtualMemoryEnable) {
-+			mode_lib->vba.AverageReadBandwidthGBytePerSecond =
-+					mode_lib->vba.AverageReadBandwidthGBytePerSecond
-+							+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
-+									/ 1000 / 512
-+							+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
-+									/ 1000 / 512;
-+		}
-+	}
-+
-+	mode_lib->vba.PartOfBurstThatFitsInROB =
-+			dml_min(
-+					mode_lib->vba.MinFullDETBufferingTime
-+							* mode_lib->vba.TotalDataReadBandwidth,
-+					mode_lib->vba.ROBBufferSizeInKByte * 1024
-+							* mode_lib->vba.TotalDataReadBandwidth
-+							/ (mode_lib->vba.AverageReadBandwidthGBytePerSecond
-+									* 1000));
-+	mode_lib->vba.StutterBurstTime = mode_lib->vba.PartOfBurstThatFitsInROB
-+			* (mode_lib->vba.AverageReadBandwidthGBytePerSecond * 1000)
-+			/ mode_lib->vba.TotalDataReadBandwidth / mode_lib->vba.ReturnBW
-+			+ (mode_lib->vba.MinFullDETBufferingTime
-+					* mode_lib->vba.TotalDataReadBandwidth
-+					- mode_lib->vba.PartOfBurstThatFitsInROB)
-+					/ (mode_lib->vba.DCFCLK * 64);
-+	if (mode_lib->vba.TotalActiveWriteback == 0) {
-+		mode_lib->vba.StutterEfficiencyNotIncludingVBlank = (1
-+				- (mode_lib->vba.SRExitTime + mode_lib->vba.StutterBurstTime)
-+						/ mode_lib->vba.MinFullDETBufferingTime) * 100;
-+	} else {
-+		mode_lib->vba.StutterEfficiencyNotIncludingVBlank = 0;
-+	}
-+
-+	mode_lib->vba.SmallestVBlank = 999999;
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
-+			mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k]
-+					- mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k]
-+					/ mode_lib->vba.PixelClock[k];
-+		} else {
-+			mode_lib->vba.VBlankTime = 0;
-+		}
-+		mode_lib->vba.SmallestVBlank = dml_min(
-+				mode_lib->vba.SmallestVBlank,
-+				mode_lib->vba.VBlankTime);
-+	}
-+
-+	mode_lib->vba.StutterEfficiency = (mode_lib->vba.StutterEfficiencyNotIncludingVBlank / 100
-+			* (mode_lib->vba.FrameTimeForMinFullDETBufferingTime
-+					- mode_lib->vba.SmallestVBlank)
-+			+ mode_lib->vba.SmallestVBlank)
-+			/ mode_lib->vba.FrameTimeForMinFullDETBufferingTime * 100;
-+
-+	// dml_ml->vba.DCFCLK Deep Sleep
-+	mode_lib->vba.DCFClkDeepSleep = 8.0;
-+
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++) {
-+		if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
-+			mode_lib->vba.DCFCLKDeepSleepPerPlane =
-+					dml_max(
-+							1.1 * mode_lib->vba.SwathWidthY[k]
-+									* dml_ceil(
-+											mode_lib->vba.BytePerPixelDETY[k],
-+											1) / 32
-+									/ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k],
-+							1.1 * mode_lib->vba.SwathWidthY[k] / 2.0
-+									* dml_ceil(
-+											mode_lib->vba.BytePerPixelDETC[k],
-+											2) / 32
-+									/ mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k]);
-+		} else
-+			mode_lib->vba.DCFCLKDeepSleepPerPlane = 1.1 * mode_lib->vba.SwathWidthY[k]
-+					* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1) / 64.0
-+					/ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k];
-+		mode_lib->vba.DCFCLKDeepSleepPerPlane = dml_max(
-+				mode_lib->vba.DCFCLKDeepSleepPerPlane,
-+				mode_lib->vba.PixelClock[k] / 16.0);
-+		mode_lib->vba.DCFClkDeepSleep = dml_max(
-+				mode_lib->vba.DCFClkDeepSleep,
-+				mode_lib->vba.DCFCLKDeepSleepPerPlane);
-+
-+		DTRACE(
-+				"   dcfclk_deepsleep_per_plane[%i] = %fMHz",
-+				k,
-+				mode_lib->vba.DCFCLKDeepSleepPerPlane);
-+	}
-+
-+	DTRACE("   dcfclk_deepsleep_mhz = %fMHz", mode_lib->vba.DCFClkDeepSleep);
-+
-+	// Stutter Watermark
-+	mode_lib->vba.StutterExitWatermark = mode_lib->vba.SRExitTime
-+			+ mode_lib->vba.LastPixelOfLineExtraWatermark
-+			+ mode_lib->vba.UrgentExtraLatency + 10 / mode_lib->vba.DCFClkDeepSleep;
-+	mode_lib->vba.StutterEnterPlusExitWatermark = mode_lib->vba.SREnterPlusExitTime
-+			+ mode_lib->vba.LastPixelOfLineExtraWatermark
-+			+ mode_lib->vba.UrgentExtraLatency;
-+
-+	DTRACE("   wm_cstate_exit       = %fus", mode_lib->vba.StutterExitWatermark);
-+	DTRACE("   wm_cstate_enter_exit = %fus", mode_lib->vba.StutterEnterPlusExitWatermark);
-+
-+	// Urgent Latency Supported
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		mode_lib->vba.EffectiveDETPlusLBLinesLuma =
-+				dml_floor(
-+						mode_lib->vba.LinesInDETY[k]
-+								+ dml_min(
-+										mode_lib->vba.LinesInDETY[k]
-+												* mode_lib->vba.DPPCLK[k]
-+												* mode_lib->vba.BytePerPixelDETY[k]
-+												* mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
-+												/ (mode_lib->vba.ReturnBW
-+														/ mode_lib->vba.DPPPerPlane[k]),
-+										(double) mode_lib->vba.EffectiveLBLatencyHidingSourceLinesLuma),
-+						mode_lib->vba.SwathHeightY[k]);
-+
-+		mode_lib->vba.UrgentLatencySupportUsLuma = mode_lib->vba.EffectiveDETPlusLBLinesLuma
-+				* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
-+				/ mode_lib->vba.VRatio[k]
-+				- mode_lib->vba.EffectiveDETPlusLBLinesLuma
-+						* mode_lib->vba.SwathWidthY[k]
-+						* mode_lib->vba.BytePerPixelDETY[k]
-+						/ (mode_lib->vba.ReturnBW
-+								/ mode_lib->vba.DPPPerPlane[k]);
-+
-+		if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
-+			mode_lib->vba.EffectiveDETPlusLBLinesChroma =
-+					dml_floor(
-+							mode_lib->vba.LinesInDETC[k]
-+									+ dml_min(
-+											mode_lib->vba.LinesInDETC[k]
-+													* mode_lib->vba.DPPCLK[k]
-+													* mode_lib->vba.BytePerPixelDETC[k]
-+													* mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
-+													/ (mode_lib->vba.ReturnBW
-+															/ mode_lib->vba.DPPPerPlane[k]),
-+											(double) mode_lib->vba.EffectiveLBLatencyHidingSourceLinesChroma),
-+							mode_lib->vba.SwathHeightC[k]);
-+			mode_lib->vba.UrgentLatencySupportUsChroma =
-+					mode_lib->vba.EffectiveDETPlusLBLinesChroma
-+							* (mode_lib->vba.HTotal[k]
-+									/ mode_lib->vba.PixelClock[k])
-+							/ (mode_lib->vba.VRatio[k] / 2)
-+							- mode_lib->vba.EffectiveDETPlusLBLinesChroma
-+									* (mode_lib->vba.SwathWidthY[k]
-+											/ 2)
-+									* mode_lib->vba.BytePerPixelDETC[k]
-+									/ (mode_lib->vba.ReturnBW
-+											/ mode_lib->vba.DPPPerPlane[k]);
-+			mode_lib->vba.UrgentLatencySupportUs[k] = dml_min(
-+					mode_lib->vba.UrgentLatencySupportUsLuma,
-+					mode_lib->vba.UrgentLatencySupportUsChroma);
-+		} else {
-+			mode_lib->vba.UrgentLatencySupportUs[k] =
-+					mode_lib->vba.UrgentLatencySupportUsLuma;
-+		}
-+	}
-+
-+	mode_lib->vba.MinUrgentLatencySupportUs = 999999;
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		mode_lib->vba.MinUrgentLatencySupportUs = dml_min(
-+				mode_lib->vba.MinUrgentLatencySupportUs,
-+				mode_lib->vba.UrgentLatencySupportUs[k]);
-+	}
-+
-+	// Non-Urgent Latency Tolerance
-+	mode_lib->vba.NonUrgentLatencyTolerance = mode_lib->vba.MinUrgentLatencySupportUs
-+			- mode_lib->vba.UrgentWatermark;
-+
-+	// DSCCLK
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
-+			mode_lib->vba.DSCCLK_calculated[k] = 0.0;
-+		} else {
-+			if (mode_lib->vba.OutputFormat[k] == dm_420
-+					|| mode_lib->vba.OutputFormat[k] == dm_n422)
-+				mode_lib->vba.DSCFormatFactor = 2;
-+			else
-+				mode_lib->vba.DSCFormatFactor = 1;
-+			if (mode_lib->vba.ODMCombineEnabled[k])
-+				mode_lib->vba.DSCCLK_calculated[k] =
-+						mode_lib->vba.PixelClockBackEnd[k] / 6
-+								/ mode_lib->vba.DSCFormatFactor
-+								/ (1
-+										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+												/ 100);
-+			else
-+				mode_lib->vba.DSCCLK_calculated[k] =
-+						mode_lib->vba.PixelClockBackEnd[k] / 3
-+								/ mode_lib->vba.DSCFormatFactor
-+								/ (1
-+										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+												/ 100);
-+		}
-+	}
-+
-+	// DSC Delay
-+	// TODO
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		double bpp = mode_lib->vba.OutputBpp[k];
-+		unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k];
-+
-+		if (mode_lib->vba.DSCEnabled[k] && bpp != 0) {
-+			if (!mode_lib->vba.ODMCombineEnabled[k]) {
-+				mode_lib->vba.DSCDelay[k] =
-+						dscceComputeDelay(
-+								mode_lib->vba.DSCInputBitPerComponent[k],
-+								bpp,
-+								dml_ceil(
-+										(double) mode_lib->vba.HActive[k]
-+												/ mode_lib->vba.NumberOfDSCSlices[k],
-+										1),
-+								slices,
-+								mode_lib->vba.OutputFormat[k])
-+								+ dscComputeDelay(
-+										mode_lib->vba.OutputFormat[k]);
-+			} else {
-+				mode_lib->vba.DSCDelay[k] =
-+						2
-+								* (dscceComputeDelay(
-+										mode_lib->vba.DSCInputBitPerComponent[k],
-+										bpp,
-+										dml_ceil(
-+												(double) mode_lib->vba.HActive[k]
-+														/ mode_lib->vba.NumberOfDSCSlices[k],
-+												1),
-+										slices / 2.0,
-+										mode_lib->vba.OutputFormat[k])
-+										+ dscComputeDelay(
-+												mode_lib->vba.OutputFormat[k]));
-+			}
-+			mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[k]
-+					* mode_lib->vba.PixelClock[k]
-+					/ mode_lib->vba.PixelClockBackEnd[k];
-+		} else {
-+			mode_lib->vba.DSCDelay[k] = 0;
-+		}
-+	}
-+
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
-+		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) // NumberOfPlanes
-+			if (j != k && mode_lib->vba.BlendingAndTiming[k] == j
-+					&& mode_lib->vba.DSCEnabled[j])
-+				mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[j];
-+
-+	// Prefetch
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		unsigned int PDEAndMetaPTEBytesFrameY;
-+		unsigned int PixelPTEBytesPerRowY;
-+		unsigned int MetaRowByteY;
-+		unsigned int MetaRowByteC;
-+		unsigned int PDEAndMetaPTEBytesFrameC;
-+		unsigned int PixelPTEBytesPerRowC;
-+
-+		Calculate256BBlockSizes(
-+				mode_lib->vba.SourcePixelFormat[k],
-+				mode_lib->vba.SurfaceTiling[k],
-+				dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
-+				dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2),
-+				&mode_lib->vba.BlockHeight256BytesY[k],
-+				&mode_lib->vba.BlockHeight256BytesC[k],
-+				&mode_lib->vba.BlockWidth256BytesY[k],
-+				&mode_lib->vba.BlockWidth256BytesC[k]);
-+		PDEAndMetaPTEBytesFrameY = CalculateVMAndRowBytes(
-+				mode_lib,
-+				mode_lib->vba.DCCEnable[k],
-+				mode_lib->vba.BlockHeight256BytesY[k],
-+				mode_lib->vba.BlockWidth256BytesY[k],
-+				mode_lib->vba.SourcePixelFormat[k],
-+				mode_lib->vba.SurfaceTiling[k],
-+				dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
-+				mode_lib->vba.SourceScan[k],
-+				mode_lib->vba.ViewportWidth[k],
-+				mode_lib->vba.ViewportHeight[k],
-+				mode_lib->vba.SwathWidthY[k],
-+				mode_lib->vba.VirtualMemoryEnable,
-+				mode_lib->vba.VMMPageSize,
-+				mode_lib->vba.PTEBufferSizeInRequests,
-+				mode_lib->vba.PDEProcessingBufIn64KBReqs,
-+				mode_lib->vba.PitchY[k],
-+				mode_lib->vba.DCCMetaPitchY[k],
-+				&mode_lib->vba.MacroTileWidthY[k],
-+				&MetaRowByteY,
-+				&PixelPTEBytesPerRowY,
-+				&mode_lib->vba.PTEBufferSizeNotExceeded[mode_lib->vba.VoltageLevel],
-+				&mode_lib->vba.dpte_row_height[k],
-+				&mode_lib->vba.meta_row_height[k]);
-+		mode_lib->vba.PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
-+				mode_lib,
-+				mode_lib->vba.VRatio[k],
-+				mode_lib->vba.vtaps[k],
-+				mode_lib->vba.Interlace[k],
-+				mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
-+				mode_lib->vba.SwathHeightY[k],
-+				mode_lib->vba.ViewportYStartY[k],
-+				&mode_lib->vba.VInitPreFillY[k],
-+				&mode_lib->vba.MaxNumSwathY[k]);
-+
-+		if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
-+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
-+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
-+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) {
-+			PDEAndMetaPTEBytesFrameC =
-+					CalculateVMAndRowBytes(
-+							mode_lib,
-+							mode_lib->vba.DCCEnable[k],
-+							mode_lib->vba.BlockHeight256BytesC[k],
-+							mode_lib->vba.BlockWidth256BytesC[k],
-+							mode_lib->vba.SourcePixelFormat[k],
-+							mode_lib->vba.SurfaceTiling[k],
-+							dml_ceil(
-+									mode_lib->vba.BytePerPixelDETC[k],
-+									2),
-+							mode_lib->vba.SourceScan[k],
-+							mode_lib->vba.ViewportWidth[k] / 2,
-+							mode_lib->vba.ViewportHeight[k] / 2,
-+							mode_lib->vba.SwathWidthY[k] / 2,
-+							mode_lib->vba.VirtualMemoryEnable,
-+							mode_lib->vba.VMMPageSize,
-+							mode_lib->vba.PTEBufferSizeInRequests,
-+							mode_lib->vba.PDEProcessingBufIn64KBReqs,
-+							mode_lib->vba.PitchC[k],
-+							0,
-+							&mode_lib->vba.MacroTileWidthC[k],
-+							&MetaRowByteC,
-+							&PixelPTEBytesPerRowC,
-+							&mode_lib->vba.PTEBufferSizeNotExceeded[mode_lib->vba.VoltageLevel],
-+							&mode_lib->vba.dpte_row_height_chroma[k],
-+							&mode_lib->vba.meta_row_height_chroma[k]);
-+			mode_lib->vba.PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
-+					mode_lib,
-+					mode_lib->vba.VRatio[k] / 2,
-+					mode_lib->vba.VTAPsChroma[k],
-+					mode_lib->vba.Interlace[k],
-+					mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
-+					mode_lib->vba.SwathHeightC[k],
-+					mode_lib->vba.ViewportYStartC[k],
-+					&mode_lib->vba.VInitPreFillC[k],
-+					&mode_lib->vba.MaxNumSwathC[k]);
-+		} else {
-+			PixelPTEBytesPerRowC = 0;
-+			PDEAndMetaPTEBytesFrameC = 0;
-+			MetaRowByteC = 0;
-+			mode_lib->vba.MaxNumSwathC[k] = 0;
-+			mode_lib->vba.PrefetchSourceLinesC[k] = 0;
-+		}
-+
-+		mode_lib->vba.PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
-+		mode_lib->vba.PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY
-+				+ PDEAndMetaPTEBytesFrameC;
-+		mode_lib->vba.MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
-+
-+		CalculateActiveRowBandwidth(
-+				mode_lib->vba.VirtualMemoryEnable,
-+				mode_lib->vba.SourcePixelFormat[k],
-+				mode_lib->vba.VRatio[k],
-+				mode_lib->vba.DCCEnable[k],
-+				mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
-+				MetaRowByteY,
-+				MetaRowByteC,
-+				mode_lib->vba.meta_row_height[k],
-+				mode_lib->vba.meta_row_height_chroma[k],
-+				PixelPTEBytesPerRowY,
-+				PixelPTEBytesPerRowC,
-+				mode_lib->vba.dpte_row_height[k],
-+				mode_lib->vba.dpte_row_height_chroma[k],
-+				&mode_lib->vba.meta_row_bw[k],
-+				&mode_lib->vba.dpte_row_bw[k],
-+				&mode_lib->vba.qual_row_bw[k]);
-+	}
-+
-+	mode_lib->vba.TCalc = 24.0 / mode_lib->vba.DCFClkDeepSleep;
-+
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
-+			if (mode_lib->vba.WritebackEnable[k] == true) {
-+				mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
-+						mode_lib->vba.WritebackLatency
-+								+ CalculateWriteBackDelay(
-+										mode_lib->vba.WritebackPixelFormat[k],
-+										mode_lib->vba.WritebackHRatio[k],
-+										mode_lib->vba.WritebackVRatio[k],
-+										mode_lib->vba.WritebackLumaHTaps[k],
-+										mode_lib->vba.WritebackLumaVTaps[k],
-+										mode_lib->vba.WritebackChromaHTaps[k],
-+										mode_lib->vba.WritebackChromaVTaps[k],
-+										mode_lib->vba.WritebackDestinationWidth[k])
-+										/ mode_lib->vba.DISPCLK;
-+			} else
-+				mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
-+			for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) {
-+				if (mode_lib->vba.BlendingAndTiming[j] == k
-+						&& mode_lib->vba.WritebackEnable[j] == true) {
-+					mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
-+							dml_max(
-+									mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k],
-+									mode_lib->vba.WritebackLatency
-+											+ CalculateWriteBackDelay(
-+													mode_lib->vba.WritebackPixelFormat[j],
-+													mode_lib->vba.WritebackHRatio[j],
-+													mode_lib->vba.WritebackVRatio[j],
-+													mode_lib->vba.WritebackLumaHTaps[j],
-+													mode_lib->vba.WritebackLumaVTaps[j],
-+													mode_lib->vba.WritebackChromaHTaps[j],
-+													mode_lib->vba.WritebackChromaVTaps[j],
-+													mode_lib->vba.WritebackDestinationWidth[j])
-+													/ mode_lib->vba.DISPCLK);
-+				}
-+			}
-+		}
-+	}
-+
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
-+		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j)
-+			if (mode_lib->vba.BlendingAndTiming[k] == j)
-+				mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
-+						mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][j];
-+
-+	mode_lib->vba.VStartupLines = 13;
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		mode_lib->vba.MaxVStartupLines[k] =
-+				mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
-+						- dml_max(
-+								1.0,
-+								dml_ceil(
-+										mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k]
-+												/ (mode_lib->vba.HTotal[k]
-+														/ mode_lib->vba.PixelClock[k]),
-+										1));
-+	}
-+
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
-+		mode_lib->vba.MaximumMaxVStartupLines = dml_max(
-+				mode_lib->vba.MaximumMaxVStartupLines,
-+				mode_lib->vba.MaxVStartupLines[k]);
-+
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		mode_lib->vba.cursor_bw[k] = 0.0;
-+		for (j = 0; j < mode_lib->vba.NumberOfCursors[k]; ++j)
-+			mode_lib->vba.cursor_bw[k] += mode_lib->vba.CursorWidth[k][j]
-+					* mode_lib->vba.CursorBPP[k][j] / 8.0
-+					/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
-+					* mode_lib->vba.VRatio[k];
-+	}
-+
-+	do {
-+		double MaxTotalRDBandwidth = 0;
-+		bool DestinationLineTimesForPrefetchLessThan2 = false;
-+		bool VRatioPrefetchMoreThan4 = false;
-+		bool prefetch_vm_bw_valid = true;
-+		bool prefetch_row_bw_valid = true;
-+		double TWait = CalculateTWait(
-+				mode_lib->vba.PrefetchMode,
-+				mode_lib->vba.DRAMClockChangeLatency,
-+				mode_lib->vba.UrgentLatency,
-+				mode_lib->vba.SREnterPlusExitTime);
-+
-+		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+			if (mode_lib->vba.XFCEnabled[k] == true) {
-+				mode_lib->vba.XFCRemoteSurfaceFlipDelay =
-+						CalculateRemoteSurfaceFlipDelay(
-+								mode_lib,
-+								mode_lib->vba.VRatio[k],
-+								mode_lib->vba.SwathWidthY[k],
-+								dml_ceil(
-+										mode_lib->vba.BytePerPixelDETY[k],
-+										1),
-+								mode_lib->vba.HTotal[k]
-+										/ mode_lib->vba.PixelClock[k],
-+								mode_lib->vba.XFCTSlvVupdateOffset,
-+								mode_lib->vba.XFCTSlvVupdateWidth,
-+								mode_lib->vba.XFCTSlvVreadyOffset,
-+								mode_lib->vba.XFCXBUFLatencyTolerance,
-+								mode_lib->vba.XFCFillBWOverhead,
-+								mode_lib->vba.XFCSlvChunkSize,
-+								mode_lib->vba.XFCBusTransportTime,
-+								mode_lib->vba.TCalc,
-+								TWait,
-+								&mode_lib->vba.SrcActiveDrainRate,
-+								&mode_lib->vba.TInitXFill,
-+								&mode_lib->vba.TslvChk);
-+			} else {
-+				mode_lib->vba.XFCRemoteSurfaceFlipDelay = 0;
-+			}
-+			mode_lib->vba.ErrorResult[k] =
-+					CalculatePrefetchSchedule(
-+							mode_lib,
-+							mode_lib->vba.DPPCLK[k],
-+							mode_lib->vba.DISPCLK,
-+							mode_lib->vba.PixelClock[k],
-+							mode_lib->vba.DCFClkDeepSleep,
-+							mode_lib->vba.DSCDelay[k],
-+							mode_lib->vba.DPPPerPlane[k],
-+							mode_lib->vba.ScalerEnabled[k],
-+							mode_lib->vba.NumberOfCursors[k],
-+							mode_lib->vba.DPPCLKDelaySubtotal,
-+							mode_lib->vba.DPPCLKDelaySCL,
-+							mode_lib->vba.DPPCLKDelaySCLLBOnly,
-+							mode_lib->vba.DPPCLKDelayCNVCFormater,
-+							mode_lib->vba.DPPCLKDelayCNVCCursor,
-+							mode_lib->vba.DISPCLKDelaySubtotal,
-+							(unsigned int) (mode_lib->vba.SwathWidthY[k]
-+									/ mode_lib->vba.HRatio[k]),
-+							mode_lib->vba.OutputFormat[k],
-+							mode_lib->vba.VTotal[k]
-+									- mode_lib->vba.VActive[k],
-+							mode_lib->vba.HTotal[k],
-+							mode_lib->vba.MaxInterDCNTileRepeaters,
-+							dml_min(
-+									mode_lib->vba.VStartupLines,
-+									mode_lib->vba.MaxVStartupLines[k]),
-+							mode_lib->vba.MaxPageTableLevels,
-+							mode_lib->vba.VirtualMemoryEnable,
-+							mode_lib->vba.DynamicMetadataEnable[k],
-+							mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
-+							mode_lib->vba.DynamicMetadataTransmittedBytes[k],
-+							mode_lib->vba.DCCEnable[k],
-+							mode_lib->vba.UrgentLatency,
-+							mode_lib->vba.UrgentExtraLatency,
-+							mode_lib->vba.TCalc,
-+							mode_lib->vba.PDEAndMetaPTEBytesFrame[k],
-+							mode_lib->vba.MetaRowByte[k],
-+							mode_lib->vba.PixelPTEBytesPerRow[k],
-+							mode_lib->vba.PrefetchSourceLinesY[k],
-+							mode_lib->vba.SwathWidthY[k],
-+							mode_lib->vba.BytePerPixelDETY[k],
-+							mode_lib->vba.VInitPreFillY[k],
-+							mode_lib->vba.MaxNumSwathY[k],
-+							mode_lib->vba.PrefetchSourceLinesC[k],
-+							mode_lib->vba.BytePerPixelDETC[k],
-+							mode_lib->vba.VInitPreFillC[k],
-+							mode_lib->vba.MaxNumSwathC[k],
-+							mode_lib->vba.SwathHeightY[k],
-+							mode_lib->vba.SwathHeightC[k],
-+							TWait,
-+							mode_lib->vba.XFCEnabled[k],
-+							mode_lib->vba.XFCRemoteSurfaceFlipDelay,
-+							mode_lib->vba.Interlace[k],
-+							mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
-+							&mode_lib->vba.DSTXAfterScaler[k],
-+							&mode_lib->vba.DSTYAfterScaler[k],
-+							&mode_lib->vba.DestinationLinesForPrefetch[k],
-+							&mode_lib->vba.PrefetchBandwidth[k],
-+							&mode_lib->vba.DestinationLinesToRequestVMInVBlank[k],
-+							&mode_lib->vba.DestinationLinesToRequestRowInVBlank[k],
-+							&mode_lib->vba.VRatioPrefetchY[k],
-+							&mode_lib->vba.VRatioPrefetchC[k],
-+							&mode_lib->vba.RequiredPrefetchPixDataBW[k],
-+							&mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata,
-+							&mode_lib->vba.Tno_bw[k],
-+							&mode_lib->vba.VUpdateOffsetPix[k],
-+							&mode_lib->vba.VUpdateWidthPix[k],
-+							&mode_lib->vba.VReadyOffsetPix[k]);
-+			if (mode_lib->vba.BlendingAndTiming[k] == k) {
-+				mode_lib->vba.VStartup[k] = dml_min(
-+						mode_lib->vba.VStartupLines,
-+						mode_lib->vba.MaxVStartupLines[k]);
-+				if (mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata
-+						!= 0) {
-+					mode_lib->vba.VStartup[k] =
-+							mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
-+				}
-+			} else {
-+				mode_lib->vba.VStartup[k] =
-+						dml_min(
-+								mode_lib->vba.VStartupLines,
-+								mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]);
-+			}
-+		}
-+
-+		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+
-+			if (mode_lib->vba.PDEAndMetaPTEBytesFrame[k] == 0)
-+				mode_lib->vba.prefetch_vm_bw[k] = 0;
-+			else if (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] > 0) {
-+				mode_lib->vba.prefetch_vm_bw[k] =
-+						(double) mode_lib->vba.PDEAndMetaPTEBytesFrame[k]
-+								/ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
-+										* mode_lib->vba.HTotal[k]
-+										/ mode_lib->vba.PixelClock[k]);
-+			} else {
-+				mode_lib->vba.prefetch_vm_bw[k] = 0;
-+				prefetch_vm_bw_valid = false;
-+			}
-+			if (mode_lib->vba.MetaRowByte[k] + mode_lib->vba.PixelPTEBytesPerRow[k]
-+					== 0)
-+				mode_lib->vba.prefetch_row_bw[k] = 0;
-+			else if (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k] > 0) {
-+				mode_lib->vba.prefetch_row_bw[k] =
-+						(double) (mode_lib->vba.MetaRowByte[k]
-+								+ mode_lib->vba.PixelPTEBytesPerRow[k])
-+								/ (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]
-+										* mode_lib->vba.HTotal[k]
-+										/ mode_lib->vba.PixelClock[k]);
-+			} else {
-+				mode_lib->vba.prefetch_row_bw[k] = 0;
-+				prefetch_row_bw_valid = false;
-+			}
-+
-+			MaxTotalRDBandwidth =
-+					MaxTotalRDBandwidth + mode_lib->vba.cursor_bw[k]
-+							+ dml_max(
-+									mode_lib->vba.prefetch_vm_bw[k],
-+									dml_max(
-+											mode_lib->vba.prefetch_row_bw[k],
-+											dml_max(
-+													mode_lib->vba.ReadBandwidthPlaneLuma[k]
-+															+ mode_lib->vba.ReadBandwidthPlaneChroma[k],
-+													mode_lib->vba.RequiredPrefetchPixDataBW[k])
-+													+ mode_lib->vba.meta_row_bw[k]
-+													+ mode_lib->vba.dpte_row_bw[k]));
-+
-+			if (mode_lib->vba.DestinationLinesForPrefetch[k] < 2)
-+				DestinationLineTimesForPrefetchLessThan2 = true;
-+			if (mode_lib->vba.VRatioPrefetchY[k] > 4
-+					|| mode_lib->vba.VRatioPrefetchC[k] > 4)
-+				VRatioPrefetchMoreThan4 = true;
-+		}
-+
-+		if (MaxTotalRDBandwidth <= mode_lib->vba.ReturnBW && prefetch_vm_bw_valid
-+				&& prefetch_row_bw_valid && !VRatioPrefetchMoreThan4
-+				&& !DestinationLineTimesForPrefetchLessThan2)
-+			mode_lib->vba.PrefetchModeSupported = true;
-+		else {
-+			mode_lib->vba.PrefetchModeSupported = false;
-+			dml_print(
-+					"DML: CalculatePrefetchSchedule ***failed***. Bandwidth violation. Results are NOT valid\n");
-+		}
-+
-+		if (mode_lib->vba.PrefetchModeSupported == true) {
-+			double final_flip_bw[DC__NUM_DPP__MAX];
-+			unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
-+			double total_dcn_read_bw_with_flip = 0;
-+
-+			mode_lib->vba.BandwidthAvailableForImmediateFlip = mode_lib->vba.ReturnBW;
-+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+				mode_lib->vba.BandwidthAvailableForImmediateFlip =
-+						mode_lib->vba.BandwidthAvailableForImmediateFlip
-+								- mode_lib->vba.cursor_bw[k]
-+								- dml_max(
-+										mode_lib->vba.ReadBandwidthPlaneLuma[k]
-+												+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
-+												+ mode_lib->vba.qual_row_bw[k],
-+										mode_lib->vba.PrefetchBandwidth[k]);
-+			}
-+
-+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+				ImmediateFlipBytes[k] = 0;
-+				if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
-+						&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
-+					ImmediateFlipBytes[k] =
-+							mode_lib->vba.PDEAndMetaPTEBytesFrame[k]
-+									+ mode_lib->vba.MetaRowByte[k]
-+									+ mode_lib->vba.PixelPTEBytesPerRow[k];
-+				}
-+			}
-+			mode_lib->vba.TotImmediateFlipBytes = 0;
-+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+				if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
-+						&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
-+					mode_lib->vba.TotImmediateFlipBytes =
-+							mode_lib->vba.TotImmediateFlipBytes
-+									+ ImmediateFlipBytes[k];
-+				}
-+			}
-+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+				CalculateFlipSchedule(
-+						mode_lib,
-+						mode_lib->vba.UrgentExtraLatency,
-+						mode_lib->vba.UrgentLatency,
-+						mode_lib->vba.MaxPageTableLevels,
-+						mode_lib->vba.VirtualMemoryEnable,
-+						mode_lib->vba.BandwidthAvailableForImmediateFlip,
-+						mode_lib->vba.TotImmediateFlipBytes,
-+						mode_lib->vba.SourcePixelFormat[k],
-+						ImmediateFlipBytes[k],
-+						mode_lib->vba.HTotal[k]
-+								/ mode_lib->vba.PixelClock[k],
-+						mode_lib->vba.VRatio[k],
-+						mode_lib->vba.Tno_bw[k],
-+						mode_lib->vba.PDEAndMetaPTEBytesFrame[k],
-+						mode_lib->vba.MetaRowByte[k],
-+						mode_lib->vba.PixelPTEBytesPerRow[k],
-+						mode_lib->vba.DCCEnable[k],
-+						mode_lib->vba.dpte_row_height[k],
-+						mode_lib->vba.meta_row_height[k],
-+						mode_lib->vba.qual_row_bw[k],
-+						&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
-+						&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
-+						&final_flip_bw[k],
-+						&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
-+			}
-+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+				total_dcn_read_bw_with_flip =
-+						total_dcn_read_bw_with_flip
-+								+ mode_lib->vba.cursor_bw[k]
-+								+ dml_max(
-+										mode_lib->vba.prefetch_vm_bw[k],
-+										dml_max(
-+												mode_lib->vba.prefetch_row_bw[k],
-+												final_flip_bw[k]
-+														+ dml_max(
-+																mode_lib->vba.ReadBandwidthPlaneLuma[k]
-+																		+ mode_lib->vba.ReadBandwidthPlaneChroma[k],
-+																mode_lib->vba.RequiredPrefetchPixDataBW[k])));
-+			}
-+			mode_lib->vba.ImmediateFlipSupported = true;
-+			if (total_dcn_read_bw_with_flip > mode_lib->vba.ReturnBW) {
-+				mode_lib->vba.ImmediateFlipSupported = false;
-+			}
-+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+				if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
-+					mode_lib->vba.ImmediateFlipSupported = false;
-+				}
-+			}
-+		} else {
-+			mode_lib->vba.ImmediateFlipSupported = false;
-+		}
-+
-+		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+			if (mode_lib->vba.ErrorResult[k]) {
-+				mode_lib->vba.PrefetchModeSupported = false;
-+				dml_print(
-+						"DML: CalculatePrefetchSchedule ***failed***. Prefetch schedule violation. Results are NOT valid\n");
-+			}
-+		}
-+
-+		mode_lib->vba.VStartupLines = mode_lib->vba.VStartupLines + 1;
-+	} while (!((mode_lib->vba.PrefetchModeSupported
-+			&& (!mode_lib->vba.ImmediateFlipSupport
-+					|| mode_lib->vba.ImmediateFlipSupported))
-+			|| mode_lib->vba.MaximumMaxVStartupLines < mode_lib->vba.VStartupLines));
-+
-+	//Display Pipeline Delivery Time in Prefetch
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		if (mode_lib->vba.VRatioPrefetchY[k] <= 1) {
-+			mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
-+					mode_lib->vba.SwathWidthY[k] * mode_lib->vba.DPPPerPlane[k]
-+							/ mode_lib->vba.HRatio[k]
-+							/ mode_lib->vba.PixelClock[k];
-+		} else {
-+			mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
-+					mode_lib->vba.SwathWidthY[k]
-+							/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
-+							/ mode_lib->vba.DPPCLK[k];
-+		}
-+		if (mode_lib->vba.BytePerPixelDETC[k] == 0) {
-+			mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
-+		} else {
-+			if (mode_lib->vba.VRatioPrefetchC[k] <= 1) {
-+				mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
-+						mode_lib->vba.SwathWidthY[k]
-+								* mode_lib->vba.DPPPerPlane[k]
-+								/ mode_lib->vba.HRatio[k]
-+								/ mode_lib->vba.PixelClock[k];
-+			} else {
-+				mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
-+						mode_lib->vba.SwathWidthY[k]
-+								/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
-+								/ mode_lib->vba.DPPCLK[k];
-+			}
-+		}
-+	}
-+
-+	// Min TTUVBlank
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		if (mode_lib->vba.PrefetchMode == 0) {
-+			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = true;
-+			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
-+			mode_lib->vba.MinTTUVBlank[k] = dml_max(
-+					mode_lib->vba.DRAMClockChangeWatermark,
-+					dml_max(
-+							mode_lib->vba.StutterEnterPlusExitWatermark,
-+							mode_lib->vba.UrgentWatermark));
-+		} else if (mode_lib->vba.PrefetchMode == 1) {
-+			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
-+			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
-+			mode_lib->vba.MinTTUVBlank[k] = dml_max(
-+					mode_lib->vba.StutterEnterPlusExitWatermark,
-+					mode_lib->vba.UrgentWatermark);
-+		} else {
-+			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
-+			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = false;
-+			mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark;
-+		}
-+		if (!mode_lib->vba.DynamicMetadataEnable[k])
-+			mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.TCalc
-+					+ mode_lib->vba.MinTTUVBlank[k];
-+	}
-+
-+	// DCC Configuration
-+	mode_lib->vba.ActiveDPPs = 0;
-+	// NB P-State/DRAM Clock Change Support
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		mode_lib->vba.ActiveDPPs = mode_lib->vba.ActiveDPPs + mode_lib->vba.DPPPerPlane[k];
-+	}
-+
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		double EffectiveLBLatencyHidingY;
-+		double EffectiveLBLatencyHidingC;
-+		double DPPOutputBufferLinesY;
-+		double DPPOutputBufferLinesC;
-+		double DPPOPPBufferingY;
-+		double MaxDETBufferingTimeY;
-+		double ActiveDRAMClockChangeLatencyMarginY;
-+
-+		mode_lib->vba.LBLatencyHidingSourceLinesY =
-+				dml_min(
-+						mode_lib->vba.MaxLineBufferLines,
-+						(unsigned int) dml_floor(
-+								(double) mode_lib->vba.LineBufferSize
-+										/ mode_lib->vba.LBBitPerPixel[k]
-+										/ (mode_lib->vba.SwathWidthY[k]
-+												/ dml_max(
-+														mode_lib->vba.HRatio[k],
-+														1.0)),
-+								1)) - (mode_lib->vba.vtaps[k] - 1);
-+
-+		mode_lib->vba.LBLatencyHidingSourceLinesC =
-+				dml_min(
-+						mode_lib->vba.MaxLineBufferLines,
-+						(unsigned int) dml_floor(
-+								(double) mode_lib->vba.LineBufferSize
-+										/ mode_lib->vba.LBBitPerPixel[k]
-+										/ (mode_lib->vba.SwathWidthY[k]
-+												/ 2.0
-+												/ dml_max(
-+														mode_lib->vba.HRatio[k]
-+																/ 2,
-+														1.0)),
-+								1))
-+						- (mode_lib->vba.VTAPsChroma[k] - 1);
-+
-+		EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY
-+				/ mode_lib->vba.VRatio[k]
-+				* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
-+
-+		EffectiveLBLatencyHidingC = mode_lib->vba.LBLatencyHidingSourceLinesC
-+				/ (mode_lib->vba.VRatio[k] / 2)
-+				* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
-+
-+		if (mode_lib->vba.SwathWidthY[k] > 2 * mode_lib->vba.DPPOutputBufferPixels) {
-+			DPPOutputBufferLinesY = mode_lib->vba.DPPOutputBufferPixels
-+					/ mode_lib->vba.SwathWidthY[k];
-+		} else if (mode_lib->vba.SwathWidthY[k] > mode_lib->vba.DPPOutputBufferPixels) {
-+			DPPOutputBufferLinesY = 0.5;
-+		} else {
-+			DPPOutputBufferLinesY = 1;
-+		}
-+
-+		if (mode_lib->vba.SwathWidthY[k] / 2 > 2 * mode_lib->vba.DPPOutputBufferPixels) {
-+			DPPOutputBufferLinesC = mode_lib->vba.DPPOutputBufferPixels
-+					/ (mode_lib->vba.SwathWidthY[k] / 2);
-+		} else if (mode_lib->vba.SwathWidthY[k] / 2 > mode_lib->vba.DPPOutputBufferPixels) {
-+			DPPOutputBufferLinesC = 0.5;
-+		} else {
-+			DPPOutputBufferLinesC = 1;
-+		}
-+
-+		DPPOPPBufferingY = (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
-+				* (DPPOutputBufferLinesY + mode_lib->vba.OPPOutputBufferLines);
-+		MaxDETBufferingTimeY = mode_lib->vba.FullDETBufferingTimeY[k]
-+				+ (mode_lib->vba.LinesInDETY[k]
-+						- mode_lib->vba.LinesInDETYRoundedDownToSwath[k])
-+						/ mode_lib->vba.SwathHeightY[k]
-+						* (mode_lib->vba.HTotal[k]
-+								/ mode_lib->vba.PixelClock[k]);
-+
-+		ActiveDRAMClockChangeLatencyMarginY = DPPOPPBufferingY + EffectiveLBLatencyHidingY
-+				+ MaxDETBufferingTimeY - mode_lib->vba.DRAMClockChangeWatermark;
-+
-+		if (mode_lib->vba.ActiveDPPs > 1) {
-+			ActiveDRAMClockChangeLatencyMarginY =
-+					ActiveDRAMClockChangeLatencyMarginY
-+							- (1 - 1 / (mode_lib->vba.ActiveDPPs - 1))
-+									* mode_lib->vba.SwathHeightY[k]
-+									* (mode_lib->vba.HTotal[k]
-+											/ mode_lib->vba.PixelClock[k]);
-+		}
-+
-+		if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
-+			double DPPOPPBufferingC = (mode_lib->vba.HTotal[k]
-+					/ mode_lib->vba.PixelClock[k])
-+					* (DPPOutputBufferLinesC
-+							+ mode_lib->vba.OPPOutputBufferLines);
-+			double MaxDETBufferingTimeC =
-+					mode_lib->vba.FullDETBufferingTimeC[k]
-+							+ (mode_lib->vba.LinesInDETC[k]
-+									- mode_lib->vba.LinesInDETCRoundedDownToSwath[k])
-+									/ mode_lib->vba.SwathHeightC[k]
-+									* (mode_lib->vba.HTotal[k]
-+											/ mode_lib->vba.PixelClock[k]);
-+			double ActiveDRAMClockChangeLatencyMarginC = DPPOPPBufferingC
-+					+ EffectiveLBLatencyHidingC + MaxDETBufferingTimeC
-+					- mode_lib->vba.DRAMClockChangeWatermark;
-+
-+			if (mode_lib->vba.ActiveDPPs > 1) {
-+				ActiveDRAMClockChangeLatencyMarginC =
-+						ActiveDRAMClockChangeLatencyMarginC
-+								- (1
-+										- 1
-+												/ (mode_lib->vba.ActiveDPPs
-+														- 1))
-+										* mode_lib->vba.SwathHeightC[k]
-+										* (mode_lib->vba.HTotal[k]
-+												/ mode_lib->vba.PixelClock[k]);
-+			}
-+			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
-+					ActiveDRAMClockChangeLatencyMarginY,
-+					ActiveDRAMClockChangeLatencyMarginC);
-+		} else {
-+			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] =
-+					ActiveDRAMClockChangeLatencyMarginY;
-+		}
-+
-+		if (mode_lib->vba.WritebackEnable[k]) {
-+			double WritebackDRAMClockChangeLatencyMargin;
-+
-+			if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
-+				WritebackDRAMClockChangeLatencyMargin =
-+						(double) (mode_lib->vba.WritebackInterfaceLumaBufferSize
-+								+ mode_lib->vba.WritebackInterfaceChromaBufferSize)
-+								/ (mode_lib->vba.WritebackDestinationWidth[k]
-+										* mode_lib->vba.WritebackDestinationHeight[k]
-+										/ (mode_lib->vba.WritebackSourceHeight[k]
-+												* mode_lib->vba.HTotal[k]
-+												/ mode_lib->vba.PixelClock[k])
-+										* 4)
-+								- mode_lib->vba.WritebackDRAMClockChangeWatermark;
-+			} else if (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
-+				WritebackDRAMClockChangeLatencyMargin =
-+						dml_min(
-+								(double) mode_lib->vba.WritebackInterfaceLumaBufferSize
-+										* 8.0 / 10,
-+								2.0
-+										* mode_lib->vba.WritebackInterfaceChromaBufferSize
-+										* 8 / 10)
-+								/ (mode_lib->vba.WritebackDestinationWidth[k]
-+										* mode_lib->vba.WritebackDestinationHeight[k]
-+										/ (mode_lib->vba.WritebackSourceHeight[k]
-+												* mode_lib->vba.HTotal[k]
-+												/ mode_lib->vba.PixelClock[k]))
-+								- mode_lib->vba.WritebackDRAMClockChangeWatermark;
-+			} else {
-+				WritebackDRAMClockChangeLatencyMargin =
-+						dml_min(
-+								(double) mode_lib->vba.WritebackInterfaceLumaBufferSize,
-+								2.0
-+										* mode_lib->vba.WritebackInterfaceChromaBufferSize)
-+								/ (mode_lib->vba.WritebackDestinationWidth[k]
-+										* mode_lib->vba.WritebackDestinationHeight[k]
-+										/ (mode_lib->vba.WritebackSourceHeight[k]
-+												* mode_lib->vba.HTotal[k]
-+												/ mode_lib->vba.PixelClock[k]))
-+								- mode_lib->vba.WritebackDRAMClockChangeWatermark;
-+			}
-+			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
-+					mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k],
-+					WritebackDRAMClockChangeLatencyMargin);
-+		}
-+	}
-+
-+	mode_lib->vba.MinActiveDRAMClockChangeMargin = 999999;
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
-+				< mode_lib->vba.MinActiveDRAMClockChangeMargin) {
-+			mode_lib->vba.MinActiveDRAMClockChangeMargin =
-+					mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
-+		}
-+	}
-+
-+	mode_lib->vba.MinActiveDRAMClockChangeLatencySupported =
-+			mode_lib->vba.MinActiveDRAMClockChangeMargin
-+					+ mode_lib->vba.DRAMClockChangeLatency;
-+
-+	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
-+		mode_lib->vba.DRAMClockChangeSupport = dm_dram_clock_change_vactive;
-+	} else {
-+		if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
-+			mode_lib->vba.DRAMClockChangeSupport = dm_dram_clock_change_vblank;
-+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+				if (!mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k]) {
-+					mode_lib->vba.DRAMClockChangeSupport =
-+							dm_dram_clock_change_unsupported;
-+				}
-+			}
-+		} else {
-+			mode_lib->vba.DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
-+		}
-+	}
-+
-+	//XFC Parameters:
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		if (mode_lib->vba.XFCEnabled[k] == true) {
-+			double TWait;
-+
-+			mode_lib->vba.XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset;
-+			mode_lib->vba.XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth;
-+			mode_lib->vba.XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset;
-+			TWait = CalculateTWait(
-+					mode_lib->vba.PrefetchMode,
-+					mode_lib->vba.DRAMClockChangeLatency,
-+					mode_lib->vba.UrgentLatency,
-+					mode_lib->vba.SREnterPlusExitTime);
-+			mode_lib->vba.XFCRemoteSurfaceFlipDelay = CalculateRemoteSurfaceFlipDelay(
-+					mode_lib,
-+					mode_lib->vba.VRatio[k],
-+					mode_lib->vba.SwathWidthY[k],
-+					dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
-+					mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
-+					mode_lib->vba.XFCTSlvVupdateOffset,
-+					mode_lib->vba.XFCTSlvVupdateWidth,
-+					mode_lib->vba.XFCTSlvVreadyOffset,
-+					mode_lib->vba.XFCXBUFLatencyTolerance,
-+					mode_lib->vba.XFCFillBWOverhead,
-+					mode_lib->vba.XFCSlvChunkSize,
-+					mode_lib->vba.XFCBusTransportTime,
-+					mode_lib->vba.TCalc,
-+					TWait,
-+					&mode_lib->vba.SrcActiveDrainRate,
-+					&mode_lib->vba.TInitXFill,
-+					&mode_lib->vba.TslvChk);
-+			mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] =
-+					dml_floor(
-+							mode_lib->vba.XFCRemoteSurfaceFlipDelay
-+									/ (mode_lib->vba.HTotal[k]
-+											/ mode_lib->vba.PixelClock[k]),
-+							1);
-+			mode_lib->vba.XFCTransferDelay[k] =
-+					dml_ceil(
-+							mode_lib->vba.XFCBusTransportTime
-+									/ (mode_lib->vba.HTotal[k]
-+											/ mode_lib->vba.PixelClock[k]),
-+							1);
-+			mode_lib->vba.XFCPrechargeDelay[k] =
-+					dml_ceil(
-+							(mode_lib->vba.XFCBusTransportTime
-+									+ mode_lib->vba.TInitXFill
-+									+ mode_lib->vba.TslvChk)
-+									/ (mode_lib->vba.HTotal[k]
-+											/ mode_lib->vba.PixelClock[k]),
-+							1);
-+			mode_lib->vba.InitFillLevel = mode_lib->vba.XFCXBUFLatencyTolerance
-+					* mode_lib->vba.SrcActiveDrainRate;
-+			mode_lib->vba.FinalFillMargin =
-+					(mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
-+							+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
-+							* mode_lib->vba.HTotal[k]
-+							/ mode_lib->vba.PixelClock[k]
-+							* mode_lib->vba.SrcActiveDrainRate
-+							+ mode_lib->vba.XFCFillConstant;
-+			mode_lib->vba.FinalFillLevel = mode_lib->vba.XFCRemoteSurfaceFlipDelay
-+					* mode_lib->vba.SrcActiveDrainRate
-+					+ mode_lib->vba.FinalFillMargin;
-+			mode_lib->vba.RemainingFillLevel = dml_max(
-+					0.0,
-+					mode_lib->vba.FinalFillLevel - mode_lib->vba.InitFillLevel);
-+			mode_lib->vba.TFinalxFill = mode_lib->vba.RemainingFillLevel
-+					/ (mode_lib->vba.SrcActiveDrainRate
-+							* mode_lib->vba.XFCFillBWOverhead / 100);
-+			mode_lib->vba.XFCPrefetchMargin[k] =
-+					mode_lib->vba.XFCRemoteSurfaceFlipDelay
-+							+ mode_lib->vba.TFinalxFill
-+							+ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
-+									+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
-+									* mode_lib->vba.HTotal[k]
-+									/ mode_lib->vba.PixelClock[k];
-+		} else {
-+			mode_lib->vba.XFCSlaveVUpdateOffset[k] = 0;
-+			mode_lib->vba.XFCSlaveVupdateWidth[k] = 0;
-+			mode_lib->vba.XFCSlaveVReadyOffset[k] = 0;
-+			mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = 0;
-+			mode_lib->vba.XFCPrechargeDelay[k] = 0;
-+			mode_lib->vba.XFCTransferDelay[k] = 0;
-+			mode_lib->vba.XFCPrefetchMargin[k] = 0;
-+		}
-+	}
-+}
-+
-+static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
-+{
-+	double BytePerPixDETY;
-+	double BytePerPixDETC;
-+	double Read256BytesBlockHeightY;
-+	double Read256BytesBlockHeightC;
-+	double Read256BytesBlockWidthY;
-+	double Read256BytesBlockWidthC;
-+	double MaximumSwathHeightY;
-+	double MaximumSwathHeightC;
-+	double MinimumSwathHeightY;
-+	double MinimumSwathHeightC;
-+	double SwathWidth;
-+	double SwathWidthGranularityY;
-+	double SwathWidthGranularityC;
-+	double RoundedUpMaxSwathSizeBytesY;
-+	double RoundedUpMaxSwathSizeBytesC;
-+	unsigned int j, k;
-+
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		bool MainPlaneDoesODMCombine = false;
-+
-+		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
-+			BytePerPixDETY = 8;
-+			BytePerPixDETC = 0;
-+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
-+			BytePerPixDETY = 4;
-+			BytePerPixDETC = 0;
-+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
-+			BytePerPixDETY = 2;
-+			BytePerPixDETC = 0;
-+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
-+			BytePerPixDETY = 1;
-+			BytePerPixDETC = 0;
-+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
-+			BytePerPixDETY = 1;
-+			BytePerPixDETC = 2;
-+		} else {
-+			BytePerPixDETY = 4.0 / 3.0;
-+			BytePerPixDETC = 8.0 / 3.0;
-+		}
-+
-+		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
-+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
-+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
-+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
-+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
-+				Read256BytesBlockHeightY = 1;
-+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
-+				Read256BytesBlockHeightY = 4;
-+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32
-+					|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
-+				Read256BytesBlockHeightY = 8;
-+			} else {
-+				Read256BytesBlockHeightY = 16;
-+			}
-+			Read256BytesBlockWidthY = 256 / dml_ceil(BytePerPixDETY, 1)
-+					/ Read256BytesBlockHeightY;
-+			Read256BytesBlockHeightC = 0;
-+			Read256BytesBlockWidthC = 0;
-+		} else {
-+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
-+				Read256BytesBlockHeightY = 1;
-+				Read256BytesBlockHeightC = 1;
-+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
-+				Read256BytesBlockHeightY = 16;
-+				Read256BytesBlockHeightC = 8;
-+			} else {
-+				Read256BytesBlockHeightY = 8;
-+				Read256BytesBlockHeightC = 8;
-+			}
-+			Read256BytesBlockWidthY = 256 / dml_ceil(BytePerPixDETY, 1)
-+					/ Read256BytesBlockHeightY;
-+			Read256BytesBlockWidthC = 256 / dml_ceil(BytePerPixDETC, 2)
-+					/ Read256BytesBlockHeightC;
-+		}
-+
-+		if (mode_lib->vba.SourceScan[k] == dm_horz) {
-+			MaximumSwathHeightY = Read256BytesBlockHeightY;
-+			MaximumSwathHeightC = Read256BytesBlockHeightC;
-+		} else {
-+			MaximumSwathHeightY = Read256BytesBlockWidthY;
-+			MaximumSwathHeightC = Read256BytesBlockWidthC;
-+		}
-+
-+		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
-+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
-+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
-+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
-+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
-+					|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
-+							&& (mode_lib->vba.SurfaceTiling[k]
-+									== dm_sw_4kb_s
-+									|| mode_lib->vba.SurfaceTiling[k]
-+											== dm_sw_4kb_s_x
-+									|| mode_lib->vba.SurfaceTiling[k]
-+											== dm_sw_64kb_s
-+									|| mode_lib->vba.SurfaceTiling[k]
-+											== dm_sw_64kb_s_t
-+									|| mode_lib->vba.SurfaceTiling[k]
-+											== dm_sw_64kb_s_x
-+									|| mode_lib->vba.SurfaceTiling[k]
-+											== dm_sw_var_s
-+									|| mode_lib->vba.SurfaceTiling[k]
-+											== dm_sw_var_s_x)
-+							&& mode_lib->vba.SourceScan[k] == dm_horz)) {
-+				MinimumSwathHeightY = MaximumSwathHeightY;
-+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8
-+					&& mode_lib->vba.SourceScan[k] != dm_horz) {
-+				MinimumSwathHeightY = MaximumSwathHeightY;
-+			} else {
-+				MinimumSwathHeightY = MaximumSwathHeightY / 2.0;
-+			}
-+			MinimumSwathHeightC = MaximumSwathHeightC;
-+		} else {
-+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
-+				MinimumSwathHeightY = MaximumSwathHeightY;
-+				MinimumSwathHeightC = MaximumSwathHeightC;
-+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
-+					&& mode_lib->vba.SourceScan[k] == dm_horz) {
-+				MinimumSwathHeightY = MaximumSwathHeightY / 2.0;
-+				MinimumSwathHeightC = MaximumSwathHeightC;
-+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
-+					&& mode_lib->vba.SourceScan[k] == dm_horz) {
-+				MinimumSwathHeightC = MaximumSwathHeightC / 2.0;
-+				MinimumSwathHeightY = MaximumSwathHeightY;
-+			} else {
-+				MinimumSwathHeightY = MaximumSwathHeightY;
-+				MinimumSwathHeightC = MaximumSwathHeightC;
-+			}
-+		}
-+
-+		if (mode_lib->vba.SourceScan[k] == dm_horz) {
-+			SwathWidth = mode_lib->vba.ViewportWidth[k];
-+		} else {
-+			SwathWidth = mode_lib->vba.ViewportHeight[k];
-+		}
-+
-+		if (mode_lib->vba.ODMCombineEnabled[k] == true) {
-+			MainPlaneDoesODMCombine = true;
-+		}
-+		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) {
-+			if (mode_lib->vba.BlendingAndTiming[k] == j
-+					&& mode_lib->vba.ODMCombineEnabled[j] == true) {
-+				MainPlaneDoesODMCombine = true;
-+			}
-+		}
-+
-+		if (MainPlaneDoesODMCombine == true) {
-+			SwathWidth = dml_min(
-+					SwathWidth,
-+					mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]);
-+		} else {
-+			SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k];
-+		}
-+
-+		SwathWidthGranularityY = 256 / dml_ceil(BytePerPixDETY, 1) / MaximumSwathHeightY;
-+		RoundedUpMaxSwathSizeBytesY = (dml_ceil(
-+				(double) (SwathWidth - 1),
-+				SwathWidthGranularityY) + SwathWidthGranularityY) * BytePerPixDETY
-+				* MaximumSwathHeightY;
-+		if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
-+			RoundedUpMaxSwathSizeBytesY = dml_ceil(RoundedUpMaxSwathSizeBytesY, 256)
-+					+ 256;
-+		}
-+		if (MaximumSwathHeightC > 0) {
-+			SwathWidthGranularityC = 256.0 / dml_ceil(BytePerPixDETC, 2)
-+					/ MaximumSwathHeightC;
-+			RoundedUpMaxSwathSizeBytesC = (dml_ceil(
-+					(double) (SwathWidth / 2.0 - 1),
-+					SwathWidthGranularityC) + SwathWidthGranularityC)
-+					* BytePerPixDETC * MaximumSwathHeightC;
-+			if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
-+				RoundedUpMaxSwathSizeBytesC = dml_ceil(
-+						RoundedUpMaxSwathSizeBytesC,
-+						256) + 256;
-+			}
-+		} else
-+			RoundedUpMaxSwathSizeBytesC = 0.0;
-+
-+		if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC
-+				<= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) {
-+			mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY;
-+			mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC;
-+		} else {
-+			mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY;
-+			mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC;
-+		}
-+
-+		if (mode_lib->vba.SwathHeightC[k] == 0) {
-+			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte * 1024;
-+			mode_lib->vba.DETBufferSizeC[k] = 0;
-+		} else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) {
-+			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte
-+					* 1024.0 / 2;
-+			mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte
-+					* 1024.0 / 2;
-+		} else {
-+			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte
-+					* 1024.0 * 2 / 3;
-+			mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte
-+					* 1024.0 / 3;
-+		}
-+	}
-+}
-+
-+bool Calculate256BBlockSizes(
-+		enum source_format_class SourcePixelFormat,
-+		enum dm_swizzle_mode SurfaceTiling,
-+		unsigned int BytePerPixelY,
-+		unsigned int BytePerPixelC,
-+		unsigned int *BlockHeight256BytesY,
-+		unsigned int *BlockHeight256BytesC,
-+		unsigned int *BlockWidth256BytesY,
-+		unsigned int *BlockWidth256BytesC)
-+{
-+	if ((SourcePixelFormat == dm_444_64 || SourcePixelFormat == dm_444_32
-+			|| SourcePixelFormat == dm_444_16
-+			|| SourcePixelFormat == dm_444_8)) {
-+		if (SurfaceTiling == dm_sw_linear) {
-+			*BlockHeight256BytesY = 1;
-+		} else if (SourcePixelFormat == dm_444_64) {
-+			*BlockHeight256BytesY = 4;
-+		} else if (SourcePixelFormat == dm_444_8) {
-+			*BlockHeight256BytesY = 16;
-+		} else {
-+			*BlockHeight256BytesY = 8;
-+		}
-+		*BlockWidth256BytesY = 256 / BytePerPixelY / *BlockHeight256BytesY;
-+		*BlockHeight256BytesC = 0;
-+		*BlockWidth256BytesC = 0;
-+	} else {
-+		if (SurfaceTiling == dm_sw_linear) {
-+			*BlockHeight256BytesY = 1;
-+			*BlockHeight256BytesC = 1;
-+		} else if (SourcePixelFormat == dm_420_8) {
-+			*BlockHeight256BytesY = 16;
-+			*BlockHeight256BytesC = 8;
-+		} else {
-+			*BlockHeight256BytesY = 8;
-+			*BlockHeight256BytesC = 8;
-+		}
-+		*BlockWidth256BytesY = 256 / BytePerPixelY / *BlockHeight256BytesY;
-+		*BlockWidth256BytesC = 256 / BytePerPixelC / *BlockHeight256BytesC;
-+	}
-+	return true;
-+}
-+
-+static double CalculateTWait(
-+		unsigned int PrefetchMode,
-+		double DRAMClockChangeLatency,
-+		double UrgentLatency,
-+		double SREnterPlusExitTime)
-+{
-+	if (PrefetchMode == 0) {
-+		return dml_max(
-+				DRAMClockChangeLatency + UrgentLatency,
-+				dml_max(SREnterPlusExitTime, UrgentLatency));
-+	} else if (PrefetchMode == 1) {
-+		return dml_max(SREnterPlusExitTime, UrgentLatency);
-+	} else {
-+		return UrgentLatency;
-+	}
-+}
-+
-+static double CalculateRemoteSurfaceFlipDelay(
-+		struct display_mode_lib *mode_lib,
-+		double VRatio,
-+		double SwathWidth,
-+		double Bpp,
-+		double LineTime,
-+		double XFCTSlvVupdateOffset,
-+		double XFCTSlvVupdateWidth,
-+		double XFCTSlvVreadyOffset,
-+		double XFCXBUFLatencyTolerance,
-+		double XFCFillBWOverhead,
-+		double XFCSlvChunkSize,
-+		double XFCBusTransportTime,
-+		double TCalc,
-+		double TWait,
-+		double *SrcActiveDrainRate,
-+		double *TInitXFill,
-+		double *TslvChk)
-+{
-+	double TSlvSetup, AvgfillRate, result;
-+
-+	*SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime;
-+	TSlvSetup = XFCTSlvVupdateOffset + XFCTSlvVupdateWidth + XFCTSlvVreadyOffset;
-+	*TInitXFill = XFCXBUFLatencyTolerance / (1 + XFCFillBWOverhead / 100);
-+	AvgfillRate = *SrcActiveDrainRate * (1 + XFCFillBWOverhead / 100);
-+	*TslvChk = XFCSlvChunkSize / AvgfillRate;
-+	dml_print(
-+			"DML::CalculateRemoteSurfaceFlipDelay: SrcActiveDrainRate: %f\n",
-+			*SrcActiveDrainRate);
-+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TSlvSetup: %f\n", TSlvSetup);
-+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TInitXFill: %f\n", *TInitXFill);
-+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: AvgfillRate: %f\n", AvgfillRate);
-+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TslvChk: %f\n", *TslvChk);
-+	result = 2 * XFCBusTransportTime + TSlvSetup + TCalc + TWait + *TslvChk + *TInitXFill; // TODO: This doesn't seem to match programming guide
-+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: RemoteSurfaceFlipDelay: %f\n", result);
-+	return result;
-+}
-+
-+static double CalculateWriteBackDISPCLK(
-+		enum source_format_class WritebackPixelFormat,
-+		double PixelClock,
-+		double WritebackHRatio,
-+		double WritebackVRatio,
-+		unsigned int WritebackLumaHTaps,
-+		unsigned int WritebackLumaVTaps,
-+		unsigned int WritebackChromaHTaps,
-+		unsigned int WritebackChromaVTaps,
-+		double WritebackDestinationWidth,
-+		unsigned int HTotal,
-+		unsigned int WritebackChromaLineBufferWidth)
-+{
-+	double CalculateWriteBackDISPCLK =
-+			1.01 * PixelClock
-+					* dml_max(
-+							dml_ceil(WritebackLumaHTaps / 4.0, 1)
-+									/ WritebackHRatio,
-+							dml_max(
-+									(WritebackLumaVTaps
-+											* dml_ceil(
-+													1.0
-+															/ WritebackVRatio,
-+													1)
-+											* dml_ceil(
-+													WritebackDestinationWidth
-+															/ 4.0,
-+													1)
-+											+ dml_ceil(
-+													WritebackDestinationWidth
-+															/ 4.0,
-+													1))
-+											/ (double) HTotal
-+											+ dml_ceil(
-+													1.0
-+															/ WritebackVRatio,
-+													1)
-+													* (dml_ceil(
-+															WritebackLumaVTaps
-+																	/ 4.0,
-+															1)
-+															+ 4.0)
-+													/ (double) HTotal,
-+									dml_ceil(
-+											1.0
-+													/ WritebackVRatio,
-+											1)
-+											* WritebackDestinationWidth
-+											/ (double) HTotal));
-+	if (WritebackPixelFormat != dm_444_32) {
-+		CalculateWriteBackDISPCLK =
-+				dml_max(
-+						CalculateWriteBackDISPCLK,
-+						1.01 * PixelClock
-+								* dml_max(
-+										dml_ceil(
-+												WritebackChromaHTaps
-+														/ 2.0,
-+												1)
-+												/ (2
-+														* WritebackHRatio),
-+										dml_max(
-+												(WritebackChromaVTaps
-+														* dml_ceil(
-+																1
-+																		/ (2
-+																				* WritebackVRatio),
-+																1)
-+														* dml_ceil(
-+																WritebackDestinationWidth
-+																		/ 2.0
-+																		/ 2.0,
-+																1)
-+														+ dml_ceil(
-+																WritebackDestinationWidth
-+																		/ 2.0
-+																		/ WritebackChromaLineBufferWidth,
-+																1))
-+														/ HTotal
-+														+ dml_ceil(
-+																1
-+																		/ (2
-+																				* WritebackVRatio),
-+																1)
-+																* (dml_ceil(
-+																		WritebackChromaVTaps
-+																				/ 4.0,
-+																		1)
-+																		+ 4)
-+																/ HTotal,
-+												dml_ceil(
-+														1.0
-+																/ (2
-+																		* WritebackVRatio),
-+														1)
-+														* WritebackDestinationWidth
-+														/ 2.0
-+														/ HTotal)));
-+	}
-+	return CalculateWriteBackDISPCLK;
-+}
-+
-+static double CalculateWriteBackDelay(
-+		enum source_format_class WritebackPixelFormat,
-+		double WritebackHRatio,
-+		double WritebackVRatio,
-+		unsigned int WritebackLumaHTaps,
-+		unsigned int WritebackLumaVTaps,
-+		unsigned int WritebackChromaHTaps,
-+		unsigned int WritebackChromaVTaps,
-+		unsigned int WritebackDestinationWidth)
-+{
-+	double CalculateWriteBackDelay =
-+			dml_max(
-+					dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio,
-+					WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1)
-+							* dml_ceil(
-+									WritebackDestinationWidth
-+											/ 4.0,
-+									1)
-+							+ dml_ceil(1.0 / WritebackVRatio, 1)
-+									* (dml_ceil(
-+											WritebackLumaVTaps
-+													/ 4.0,
-+											1) + 4));
-+
-+	if (WritebackPixelFormat != dm_444_32) {
-+		CalculateWriteBackDelay =
-+				dml_max(
-+						CalculateWriteBackDelay,
-+						dml_max(
-+								dml_ceil(
-+										WritebackChromaHTaps
-+												/ 2.0,
-+										1)
-+										/ (2
-+												* WritebackHRatio),
-+								WritebackChromaVTaps
-+										* dml_ceil(
-+												1
-+														/ (2
-+																* WritebackVRatio),
-+												1)
-+										* dml_ceil(
-+												WritebackDestinationWidth
-+														/ 2.0
-+														/ 2.0,
-+												1)
-+										+ dml_ceil(
-+												1
-+														/ (2
-+																* WritebackVRatio),
-+												1)
-+												* (dml_ceil(
-+														WritebackChromaVTaps
-+																/ 4.0,
-+														1)
-+														+ 4)));
-+	}
-+	return CalculateWriteBackDelay;
-+}
-+
-+static void CalculateActiveRowBandwidth(
-+		bool VirtualMemoryEnable,
-+		enum source_format_class SourcePixelFormat,
-+		double VRatio,
-+		bool DCCEnable,
-+		double LineTime,
-+		unsigned int MetaRowByteLuma,
-+		unsigned int MetaRowByteChroma,
-+		unsigned int meta_row_height_luma,
-+		unsigned int meta_row_height_chroma,
-+		unsigned int PixelPTEBytesPerRowLuma,
-+		unsigned int PixelPTEBytesPerRowChroma,
-+		unsigned int dpte_row_height_luma,
-+		unsigned int dpte_row_height_chroma,
-+		double *meta_row_bw,
-+		double *dpte_row_bw,
-+		double *qual_row_bw)
-+{
-+	if (DCCEnable != true) {
-+		*meta_row_bw = 0;
-+	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
-+		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime)
-+				+ VRatio / 2 * MetaRowByteChroma
-+						/ (meta_row_height_chroma * LineTime);
-+	} else {
-+		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime);
-+	}
-+
-+	if (VirtualMemoryEnable != true) {
-+		*dpte_row_bw = 0;
-+	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
-+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime)
-+				+ VRatio / 2 * PixelPTEBytesPerRowChroma
-+						/ (dpte_row_height_chroma * LineTime);
-+	} else {
-+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime);
-+	}
-+
-+	if ((SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10)) {
-+		*qual_row_bw = *meta_row_bw + *dpte_row_bw;
-+	} else {
-+		*qual_row_bw = 0;
-+	}
-+}
-+
-+static void CalculateFlipSchedule(
-+		struct display_mode_lib *mode_lib,
-+		double UrgentExtraLatency,
-+		double UrgentLatency,
-+		unsigned int MaxPageTableLevels,
-+		bool VirtualMemoryEnable,
-+		double BandwidthAvailableForImmediateFlip,
-+		unsigned int TotImmediateFlipBytes,
-+		enum source_format_class SourcePixelFormat,
-+		unsigned int ImmediateFlipBytes,
-+		double LineTime,
-+		double Tno_bw,
-+		double VRatio,
-+		double PDEAndMetaPTEBytesFrame,
-+		unsigned int MetaRowByte,
-+		unsigned int PixelPTEBytesPerRow,
-+		bool DCCEnable,
-+		unsigned int dpte_row_height,
-+		unsigned int meta_row_height,
-+		double qual_row_bw,
-+		double *DestinationLinesToRequestVMInImmediateFlip,
-+		double *DestinationLinesToRequestRowInImmediateFlip,
-+		double *final_flip_bw,
-+		bool *ImmediateFlipSupportedForPipe)
-+{
-+	double min_row_time = 0.0;
-+
-+	if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
-+		*DestinationLinesToRequestVMInImmediateFlip = 0.0;
-+		*DestinationLinesToRequestRowInImmediateFlip = 0.0;
-+		*final_flip_bw = qual_row_bw;
-+		*ImmediateFlipSupportedForPipe = true;
-+	} else {
-+		double TimeForFetchingMetaPTEImmediateFlip;
-+		double TimeForFetchingRowInVBlankImmediateFlip;
-+
-+		if (VirtualMemoryEnable == true) {
-+			mode_lib->vba.ImmediateFlipBW = BandwidthAvailableForImmediateFlip
-+					* ImmediateFlipBytes / TotImmediateFlipBytes;
-+			TimeForFetchingMetaPTEImmediateFlip =
-+					dml_max(
-+							Tno_bw
-+									+ PDEAndMetaPTEBytesFrame
-+											/ mode_lib->vba.ImmediateFlipBW,
-+							dml_max(
-+									UrgentExtraLatency
-+											+ UrgentLatency
-+													* (MaxPageTableLevels
-+															- 1),
-+									LineTime / 4.0));
-+		} else {
-+			TimeForFetchingMetaPTEImmediateFlip = 0;
-+		}
-+
-+		*DestinationLinesToRequestVMInImmediateFlip = dml_floor(
-+				4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime + 0.125),
-+				1) / 4.0;
-+
-+		if ((VirtualMemoryEnable == true || DCCEnable == true)) {
-+			mode_lib->vba.ImmediateFlipBW = BandwidthAvailableForImmediateFlip
-+					* ImmediateFlipBytes / TotImmediateFlipBytes;
-+			TimeForFetchingRowInVBlankImmediateFlip = dml_max(
-+					(MetaRowByte + PixelPTEBytesPerRow)
-+							/ mode_lib->vba.ImmediateFlipBW,
-+					dml_max(UrgentLatency, LineTime / 4.0));
-+		} else {
-+			TimeForFetchingRowInVBlankImmediateFlip = 0;
-+		}
-+
-+		*DestinationLinesToRequestRowInImmediateFlip = dml_floor(
-+				4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime + 0.125),
-+				1) / 4.0;
-+
-+		if (VirtualMemoryEnable == true) {
-+			*final_flip_bw =
-+					dml_max(
-+							PDEAndMetaPTEBytesFrame
-+									/ (*DestinationLinesToRequestVMInImmediateFlip
-+											* LineTime),
-+							(MetaRowByte + PixelPTEBytesPerRow)
-+									/ (TimeForFetchingRowInVBlankImmediateFlip
-+											* LineTime));
-+		} else if (MetaRowByte + PixelPTEBytesPerRow > 0) {
-+			*final_flip_bw = (MetaRowByte + PixelPTEBytesPerRow)
-+					/ (TimeForFetchingRowInVBlankImmediateFlip * LineTime);
-+		} else {
-+			*final_flip_bw = 0;
-+		}
-+
-+		if (VirtualMemoryEnable && !DCCEnable)
-+			min_row_time = dpte_row_height * LineTime / VRatio;
-+		else if (!VirtualMemoryEnable && DCCEnable)
-+			min_row_time = meta_row_height * LineTime / VRatio;
-+		else
-+			min_row_time = dml_min(dpte_row_height, meta_row_height) * LineTime
-+					/ VRatio;
-+
-+		if (*DestinationLinesToRequestVMInImmediateFlip >= 8
-+				|| *DestinationLinesToRequestRowInImmediateFlip >= 16
-+				|| TimeForFetchingMetaPTEImmediateFlip
-+						+ 2 * TimeForFetchingRowInVBlankImmediateFlip
-+						> min_row_time)
-+			*ImmediateFlipSupportedForPipe = false;
-+		else
-+			*ImmediateFlipSupportedForPipe = true;
-+	}
-+}
-+
-+static void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib)
-+{
-+	unsigned int k;
-+
-+	//Progressive To dml_ml->vba.Interlace Unit Effect
-+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-+		mode_lib->vba.PixelClockBackEnd[k] = mode_lib->vba.PixelClock[k];
-+		if (mode_lib->vba.Interlace[k] == 1
-+				&& mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true) {
-+			mode_lib->vba.PixelClock[k] = 2 * mode_lib->vba.PixelClock[k];
-+		}
-+	}
-+}
-+
-+static unsigned int CursorBppEnumToBits(enum cursor_bpp ebpp)
-+{
-+	switch (ebpp) {
-+	case dm_cur_2bit:
-+		return 2;
-+	case dm_cur_32bit:
-+		return 32;
-+	case dm_cur_64bit:
-+		return 64;
-+	default:
-+		return 0;
-+	}
-+}
-+
-+static unsigned int TruncToValidBPP(
-+		double DecimalBPP,
-+		bool DSCEnabled,
-+		enum output_encoder_class Output,
-+		enum output_format_class Format,
-+		unsigned int DSCInputBitPerComponent)
-+{
-+	if (Output == dm_hdmi) {
-+		if (Format == dm_420) {
-+			if (DecimalBPP >= 18)
-+				return 18;
-+			else if (DecimalBPP >= 15)
-+				return 15;
-+			else if (DecimalBPP >= 12)
-+				return 12;
-+			else
-+				return 0;
-+		} else if (Format == dm_444) {
-+			if (DecimalBPP >= 36)
-+				return 36;
-+			else if (DecimalBPP >= 30)
-+				return 30;
-+			else if (DecimalBPP >= 24)
-+				return 24;
-+			else
-+				return 0;
-+		} else {
-+			if (DecimalBPP / 1.5 >= 24)
-+				return 24;
-+			else if (DecimalBPP / 1.5 >= 20)
-+				return 20;
-+			else if (DecimalBPP / 1.5 >= 16)
-+				return 16;
-+			else
-+				return 0;
-+		}
-+	} else {
-+		if (DSCEnabled) {
-+			if (Format == dm_420) {
-+				if (DecimalBPP < 6)
-+					return 0;
-+				else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1 / 16)
-+					return 1.5 * DSCInputBitPerComponent - 1 / 16;
-+				else
-+					return dml_floor(16 * DecimalBPP, 1) / 16;
-+			} else if (Format == dm_n422) {
-+				if (DecimalBPP < 7)
-+					return 0;
-+				else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1 / 16)
-+					return 2 * DSCInputBitPerComponent - 1 / 16;
-+				else
-+					return dml_floor(16 * DecimalBPP, 1) / 16;
-+			} else {
-+				if (DecimalBPP < 8)
-+					return 0;
-+				else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1 / 16)
-+					return 3 * DSCInputBitPerComponent - 1 / 16;
-+				else
-+					return dml_floor(16 * DecimalBPP, 1) / 16;
-+			}
-+		} else if (Format == dm_420) {
-+			if (DecimalBPP >= 18)
-+				return 18;
-+			else if (DecimalBPP >= 15)
-+				return 15;
-+			else if (DecimalBPP >= 12)
-+				return 12;
-+			else
-+				return 0;
-+		} else if (Format == dm_s422 || Format == dm_n422) {
-+			if (DecimalBPP >= 24)
-+				return 24;
-+			else if (DecimalBPP >= 20)
-+				return 20;
-+			else if (DecimalBPP >= 16)
-+				return 16;
-+			else
-+				return 0;
-+		} else {
-+			if (DecimalBPP >= 36)
-+				return 36;
-+			else if (DecimalBPP >= 30)
-+				return 30;
-+			else if (DecimalBPP >= 24)
-+				return 24;
-+			else
-+				return 0;
-+		}
-+	}
-+}
-+
-+static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
-+{
-+	int i;
-+	unsigned int j, k;
-+	/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
-+
-+	/*Scale Ratio, taps Support Check*/
-+
-+	mode_lib->vba.ScaleRatioAndTapsSupport = true;
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if (mode_lib->vba.ScalerEnabled[k] == false
-+				&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
-+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
-+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
-+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
-+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)
-+						|| mode_lib->vba.HRatio[k] != 1.0
-+						|| mode_lib->vba.htaps[k] != 1.0
-+						|| mode_lib->vba.VRatio[k] != 1.0
-+						|| mode_lib->vba.vtaps[k] != 1.0)) {
-+			mode_lib->vba.ScaleRatioAndTapsSupport = false;
-+		} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0
-+				|| mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0
-+				|| (mode_lib->vba.htaps[k] > 1.0
-+						&& (mode_lib->vba.htaps[k] % 2) == 1)
-+				|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
-+				|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
-+				|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
-+				|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
-+				|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
-+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
-+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
-+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
-+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
-+						&& (mode_lib->vba.HRatio[k] / 2.0
-+								> mode_lib->vba.HTAPsChroma[k]
-+								|| mode_lib->vba.VRatio[k] / 2.0
-+										> mode_lib->vba.VTAPsChroma[k]))) {
-+			mode_lib->vba.ScaleRatioAndTapsSupport = false;
-+		}
-+	}
-+	/*Source Format, Pixel Format and Scan Support Check*/
-+
-+	mode_lib->vba.SourceFormatPixelAndScanSupport = true;
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
-+				&& mode_lib->vba.SourceScan[k] != dm_horz)
-+				|| ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x)
-+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_64)
-+				|| (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x
-+						&& (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8
-+								|| mode_lib->vba.SourcePixelFormat[k]
-+										== dm_420_8
-+								|| mode_lib->vba.SourcePixelFormat[k]
-+										== dm_420_10))
-+				|| (((mode_lib->vba.SurfaceTiling[k]
-+						== dm_sw_gfx7_2d_thin_gl
-+						|| mode_lib->vba.SurfaceTiling[k]
-+								== dm_sw_gfx7_2d_thin_lvp)
-+						&& !((mode_lib->vba.SourcePixelFormat[k]
-+								== dm_444_64
-+								|| mode_lib->vba.SourcePixelFormat[k]
-+										== dm_444_32)
-+								&& mode_lib->vba.SourceScan[k]
-+										== dm_horz
-+								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
-+										== true
-+								&& mode_lib->vba.DCCEnable[k]
-+										== false))
-+						|| (mode_lib->vba.DCCEnable[k] == true
-+								&& (mode_lib->vba.SurfaceTiling[k]
-+										== dm_sw_linear
-+										|| mode_lib->vba.SourcePixelFormat[k]
-+												== dm_420_8
-+										|| mode_lib->vba.SourcePixelFormat[k]
-+												== dm_420_10)))) {
-+			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
-+		}
-+	}
-+	/*Bandwidth Support Check*/
-+
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if (mode_lib->vba.SourceScan[k] == dm_horz) {
-+			mode_lib->vba.SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
-+		} else {
-+			mode_lib->vba.SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
-+		}
-+		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
-+			mode_lib->vba.BytePerPixelInDETY[k] = 8.0;
-+			mode_lib->vba.BytePerPixelInDETC[k] = 0.0;
-+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
-+			mode_lib->vba.BytePerPixelInDETY[k] = 4.0;
-+			mode_lib->vba.BytePerPixelInDETC[k] = 0.0;
-+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16
-+				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
-+			mode_lib->vba.BytePerPixelInDETY[k] = 2.0;
-+			mode_lib->vba.BytePerPixelInDETC[k] = 0.0;
-+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
-+			mode_lib->vba.BytePerPixelInDETY[k] = 1.0;
-+			mode_lib->vba.BytePerPixelInDETC[k] = 0.0;
-+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
-+			mode_lib->vba.BytePerPixelInDETY[k] = 1.0;
-+			mode_lib->vba.BytePerPixelInDETC[k] = 2.0;
-+		} else {
-+			mode_lib->vba.BytePerPixelInDETY[k] = 4.0 / 3;
-+			mode_lib->vba.BytePerPixelInDETC[k] = 8.0 / 3;
-+		}
-+	}
-+	mode_lib->vba.TotalReadBandwidthConsumedGBytePerSecond = 0.0;
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		mode_lib->vba.ReadBandwidth[k] = mode_lib->vba.SwathWidthYSingleDPP[k]
-+				* (dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0)
-+						* mode_lib->vba.VRatio[k]
-+						+ dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0)
-+								/ 2.0 * mode_lib->vba.VRatio[k] / 2)
-+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
-+		if (mode_lib->vba.DCCEnable[k] == true) {
-+			mode_lib->vba.ReadBandwidth[k] = mode_lib->vba.ReadBandwidth[k]
-+					* (1 + 1 / 256);
-+		}
-+		if (mode_lib->vba.VirtualMemoryEnable == true
-+				&& mode_lib->vba.SourceScan[k] != dm_horz
-+				&& (mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_s
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_s_x
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x)) {
-+			mode_lib->vba.ReadBandwidth[k] = mode_lib->vba.ReadBandwidth[k]
-+					* (1 + 1 / 64);
-+		} else if (mode_lib->vba.VirtualMemoryEnable == true
-+				&& mode_lib->vba.SourceScan[k] == dm_horz
-+				&& (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
-+						|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32)
-+				&& (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_s
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_s_t
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_s_x
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x
-+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x)) {
-+			mode_lib->vba.ReadBandwidth[k] = mode_lib->vba.ReadBandwidth[k]
-+					* (1 + 1 / 256);
-+		} else if (mode_lib->vba.VirtualMemoryEnable == true) {
-+			mode_lib->vba.ReadBandwidth[k] = mode_lib->vba.ReadBandwidth[k]
-+					* (1 + 1 / 512);
-+		}
-+		mode_lib->vba.TotalReadBandwidthConsumedGBytePerSecond =
-+				mode_lib->vba.TotalReadBandwidthConsumedGBytePerSecond
-+						+ mode_lib->vba.ReadBandwidth[k] / 1000.0;
-+	}
-+	mode_lib->vba.TotalWriteBandwidthConsumedGBytePerSecond = 0.0;
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if (mode_lib->vba.WritebackEnable[k] == true
-+				&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
-+			mode_lib->vba.WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
-+					* mode_lib->vba.WritebackDestinationHeight[k]
-+					/ (mode_lib->vba.WritebackSourceHeight[k]
-+							* mode_lib->vba.HTotal[k]
-+							/ mode_lib->vba.PixelClock[k]) * 4.0;
-+		} else if (mode_lib->vba.WritebackEnable[k] == true
-+				&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
-+			mode_lib->vba.WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
-+					* mode_lib->vba.WritebackDestinationHeight[k]
-+					/ (mode_lib->vba.WritebackSourceHeight[k]
-+							* mode_lib->vba.HTotal[k]
-+							/ mode_lib->vba.PixelClock[k]) * 3.0;
-+		} else if (mode_lib->vba.WritebackEnable[k] == true) {
-+			mode_lib->vba.WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
-+					* mode_lib->vba.WritebackDestinationHeight[k]
-+					/ (mode_lib->vba.WritebackSourceHeight[k]
-+							* mode_lib->vba.HTotal[k]
-+							/ mode_lib->vba.PixelClock[k]) * 1.5;
-+		} else {
-+			mode_lib->vba.WriteBandwidth[k] = 0.0;
-+		}
-+		mode_lib->vba.TotalWriteBandwidthConsumedGBytePerSecond =
-+				mode_lib->vba.TotalWriteBandwidthConsumedGBytePerSecond
-+						+ mode_lib->vba.WriteBandwidth[k] / 1000.0;
-+	}
-+	mode_lib->vba.TotalBandwidthConsumedGBytePerSecond =
-+			mode_lib->vba.TotalReadBandwidthConsumedGBytePerSecond
-+					+ mode_lib->vba.TotalWriteBandwidthConsumedGBytePerSecond;
-+	mode_lib->vba.DCCEnabledInAnyPlane = false;
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if (mode_lib->vba.DCCEnable[k] == true) {
-+			mode_lib->vba.DCCEnabledInAnyPlane = true;
-+		}
-+	}
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		mode_lib->vba.FabricAndDRAMBandwidthPerState[i] = dml_min(
-+				mode_lib->vba.DRAMSpeedPerState[i] * mode_lib->vba.NumberOfChannels
-+						* mode_lib->vba.DRAMChannelWidth,
-+				mode_lib->vba.FabricClockPerState[i]
-+						* mode_lib->vba.FabricDatapathToDCNDataReturn)
-+				/ 1000;
-+		mode_lib->vba.ReturnBWToDCNPerState = dml_min(
-+				mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKPerState[i],
-+				mode_lib->vba.FabricAndDRAMBandwidthPerState[i] * 1000.0)
-+				* mode_lib->vba.PercentOfIdealDRAMAndFabricBWReceivedAfterUrgLatency
-+				/ 100;
-+		mode_lib->vba.ReturnBWPerState[i] = mode_lib->vba.ReturnBWToDCNPerState;
-+		if (mode_lib->vba.DCCEnabledInAnyPlane == true
-+				&& mode_lib->vba.ReturnBWToDCNPerState
-+						> mode_lib->vba.DCFCLKPerState[i]
-+								* mode_lib->vba.ReturnBusWidth
-+								/ 4.0) {
-+			mode_lib->vba.ReturnBWPerState[i] =
-+					dml_min(
-+							mode_lib->vba.ReturnBWPerState[i],
-+							mode_lib->vba.ReturnBWToDCNPerState * 4.0
-+									* (1.0
-+											- mode_lib->vba.UrgentLatency
-+													/ ((mode_lib->vba.ROBBufferSizeInKByte
-+															- mode_lib->vba.PixelChunkSizeInKByte)
-+															* 1024.0
-+															/ (mode_lib->vba.ReturnBWToDCNPerState
-+																	- mode_lib->vba.DCFCLKPerState[i]
-+																			* mode_lib->vba.ReturnBusWidth
-+																			/ 4.0)
-+															+ mode_lib->vba.UrgentLatency)));
-+		}
-+		mode_lib->vba.CriticalPoint =
-+				2.0 * mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKPerState[i]
-+						* mode_lib->vba.UrgentLatency
-+						/ (mode_lib->vba.ReturnBWToDCNPerState
-+								* mode_lib->vba.UrgentLatency
-+								+ (mode_lib->vba.ROBBufferSizeInKByte
-+										- mode_lib->vba.PixelChunkSizeInKByte)
-+										* 1024.0);
-+		if (mode_lib->vba.DCCEnabledInAnyPlane == true && mode_lib->vba.CriticalPoint > 1.0
-+				&& mode_lib->vba.CriticalPoint < 4.0) {
-+			mode_lib->vba.ReturnBWPerState[i] =
-+					dml_min(
-+							mode_lib->vba.ReturnBWPerState[i],
-+							dml_pow(
-+									4.0
-+											* mode_lib->vba.ReturnBWToDCNPerState
-+											* (mode_lib->vba.ROBBufferSizeInKByte
-+													- mode_lib->vba.PixelChunkSizeInKByte)
-+											* 1024.0
-+											* mode_lib->vba.ReturnBusWidth
-+											* mode_lib->vba.DCFCLKPerState[i]
-+											* mode_lib->vba.UrgentLatency
-+											/ (mode_lib->vba.ReturnBWToDCNPerState
-+													* mode_lib->vba.UrgentLatency
-+													+ (mode_lib->vba.ROBBufferSizeInKByte
-+															- mode_lib->vba.PixelChunkSizeInKByte)
-+															* 1024.0),
-+									2));
-+		}
-+		mode_lib->vba.ReturnBWToDCNPerState = dml_min(
-+				mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKPerState[i],
-+				mode_lib->vba.FabricAndDRAMBandwidthPerState[i] * 1000.0);
-+		if (mode_lib->vba.DCCEnabledInAnyPlane == true
-+				&& mode_lib->vba.ReturnBWToDCNPerState
-+						> mode_lib->vba.DCFCLKPerState[i]
-+								* mode_lib->vba.ReturnBusWidth
-+								/ 4.0) {
-+			mode_lib->vba.ReturnBWPerState[i] =
-+					dml_min(
-+							mode_lib->vba.ReturnBWPerState[i],
-+							mode_lib->vba.ReturnBWToDCNPerState * 4.0
-+									* (1.0
-+											- mode_lib->vba.UrgentLatency
-+													/ ((mode_lib->vba.ROBBufferSizeInKByte
-+															- mode_lib->vba.PixelChunkSizeInKByte)
-+															* 1024.0
-+															/ (mode_lib->vba.ReturnBWToDCNPerState
-+																	- mode_lib->vba.DCFCLKPerState[i]
-+																			* mode_lib->vba.ReturnBusWidth
-+																			/ 4.0)
-+															+ mode_lib->vba.UrgentLatency)));
-+		}
-+		mode_lib->vba.CriticalPoint =
-+				2.0 * mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKPerState[i]
-+						* mode_lib->vba.UrgentLatency
-+						/ (mode_lib->vba.ReturnBWToDCNPerState
-+								* mode_lib->vba.UrgentLatency
-+								+ (mode_lib->vba.ROBBufferSizeInKByte
-+										- mode_lib->vba.PixelChunkSizeInKByte)
-+										* 1024.0);
-+		if (mode_lib->vba.DCCEnabledInAnyPlane == true && mode_lib->vba.CriticalPoint > 1.0
-+				&& mode_lib->vba.CriticalPoint < 4.0) {
-+			mode_lib->vba.ReturnBWPerState[i] =
-+					dml_min(
-+							mode_lib->vba.ReturnBWPerState[i],
-+							dml_pow(
-+									4.0
-+											* mode_lib->vba.ReturnBWToDCNPerState
-+											* (mode_lib->vba.ROBBufferSizeInKByte
-+													- mode_lib->vba.PixelChunkSizeInKByte)
-+											* 1024.0
-+											* mode_lib->vba.ReturnBusWidth
-+											* mode_lib->vba.DCFCLKPerState[i]
-+											* mode_lib->vba.UrgentLatency
-+											/ (mode_lib->vba.ReturnBWToDCNPerState
-+													* mode_lib->vba.UrgentLatency
-+													+ (mode_lib->vba.ROBBufferSizeInKByte
-+															- mode_lib->vba.PixelChunkSizeInKByte)
-+															* 1024.0),
-+									2));
-+		}
-+	}
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		if ((mode_lib->vba.TotalReadBandwidthConsumedGBytePerSecond * 1000.0
-+				<= mode_lib->vba.ReturnBWPerState[i])
-+				&& (mode_lib->vba.TotalBandwidthConsumedGBytePerSecond * 1000.0
-+						<= mode_lib->vba.FabricAndDRAMBandwidthPerState[i]
-+								* 1000.0
-+								* mode_lib->vba.PercentOfIdealDRAMAndFabricBWReceivedAfterUrgLatency
-+								/ 100.0)) {
-+			mode_lib->vba.BandwidthSupport[i] = true;
-+		} else {
-+			mode_lib->vba.BandwidthSupport[i] = false;
-+		}
-+	}
-+	/*Writeback Latency support check*/
-+
-+	mode_lib->vba.WritebackLatencySupport = true;
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if (mode_lib->vba.WritebackEnable[k] == true) {
-+			if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
-+				if (mode_lib->vba.WriteBandwidth[k]
-+						> (mode_lib->vba.WritebackInterfaceLumaBufferSize
-+								+ mode_lib->vba.WritebackInterfaceChromaBufferSize)
-+								/ mode_lib->vba.WritebackLatency) {
-+					mode_lib->vba.WritebackLatencySupport = false;
-+				}
-+			} else {
-+				if (mode_lib->vba.WriteBandwidth[k]
-+						> 1.5
-+								* dml_min(
-+										mode_lib->vba.WritebackInterfaceLumaBufferSize,
-+										2.0
-+												* mode_lib->vba.WritebackInterfaceChromaBufferSize)
-+								/ mode_lib->vba.WritebackLatency) {
-+					mode_lib->vba.WritebackLatencySupport = false;
-+				}
-+			}
-+		}
-+	}
-+	/*Re-ordering Buffer Support Check*/
-+
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		mode_lib->vba.UrgentRoundTripAndOutOfOrderLatencyPerState[i] =
-+				(mode_lib->vba.RoundTripPingLatencyCycles + 32.0)
-+						/ mode_lib->vba.DCFCLKPerState[i]
-+						+ mode_lib->vba.UrgentOutOfOrderReturnPerChannel
-+								* mode_lib->vba.NumberOfChannels
-+								/ mode_lib->vba.ReturnBWPerState[i];
-+		if ((mode_lib->vba.ROBBufferSizeInKByte - mode_lib->vba.PixelChunkSizeInKByte)
-+				* 1024.0 / mode_lib->vba.ReturnBWPerState[i]
-+				> mode_lib->vba.UrgentRoundTripAndOutOfOrderLatencyPerState[i]) {
-+			mode_lib->vba.ROBSupport[i] = true;
-+		} else {
-+			mode_lib->vba.ROBSupport[i] = false;
-+		}
-+	}
-+	/*Writeback Mode Support Check*/
-+
-+	mode_lib->vba.TotalNumberOfActiveWriteback = 0;
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if (mode_lib->vba.WritebackEnable[k] == true) {
-+			mode_lib->vba.TotalNumberOfActiveWriteback =
-+					mode_lib->vba.TotalNumberOfActiveWriteback + 1;
-+		}
-+	}
-+	mode_lib->vba.WritebackModeSupport = true;
-+	if (mode_lib->vba.TotalNumberOfActiveWriteback > mode_lib->vba.MaxNumWriteback) {
-+		mode_lib->vba.WritebackModeSupport = false;
-+	}
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if (mode_lib->vba.WritebackEnable[k] == true
-+				&& mode_lib->vba.Writeback10bpc420Supported != true
-+				&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
-+			mode_lib->vba.WritebackModeSupport = false;
-+		}
-+	}
-+	/*Writeback Scale Ratio and Taps Support Check*/
-+
-+	mode_lib->vba.WritebackScaleRatioAndTapsSupport = true;
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if (mode_lib->vba.WritebackEnable[k] == true) {
-+			if (mode_lib->vba.WritebackLumaAndChromaScalingSupported == false
-+					&& (mode_lib->vba.WritebackHRatio[k] != 1.0
-+							|| mode_lib->vba.WritebackVRatio[k] != 1.0)) {
-+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
-+			}
-+			if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
-+					|| mode_lib->vba.WritebackVRatio[k]
-+							> mode_lib->vba.WritebackMaxVSCLRatio
-+					|| mode_lib->vba.WritebackHRatio[k]
-+							< mode_lib->vba.WritebackMinHSCLRatio
-+					|| mode_lib->vba.WritebackVRatio[k]
-+							< mode_lib->vba.WritebackMinVSCLRatio
-+					|| mode_lib->vba.WritebackLumaHTaps[k]
-+							> mode_lib->vba.WritebackMaxHSCLTaps
-+					|| mode_lib->vba.WritebackLumaVTaps[k]
-+							> mode_lib->vba.WritebackMaxVSCLTaps
-+					|| mode_lib->vba.WritebackHRatio[k]
-+							> mode_lib->vba.WritebackLumaHTaps[k]
-+					|| mode_lib->vba.WritebackVRatio[k]
-+							> mode_lib->vba.WritebackLumaVTaps[k]
-+					|| (mode_lib->vba.WritebackLumaHTaps[k] > 2.0
-+							&& ((mode_lib->vba.WritebackLumaHTaps[k] % 2)
-+									== 1))
-+					|| (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32
-+							&& (mode_lib->vba.WritebackChromaHTaps[k]
-+									> mode_lib->vba.WritebackMaxHSCLTaps
-+									|| mode_lib->vba.WritebackChromaVTaps[k]
-+											> mode_lib->vba.WritebackMaxVSCLTaps
-+									|| 2.0
-+											* mode_lib->vba.WritebackHRatio[k]
-+											> mode_lib->vba.WritebackChromaHTaps[k]
-+									|| 2.0
-+											* mode_lib->vba.WritebackVRatio[k]
-+											> mode_lib->vba.WritebackChromaVTaps[k]
-+									|| (mode_lib->vba.WritebackChromaHTaps[k] > 2.0
-+										&& ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) {
-+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
-+			}
-+			if (mode_lib->vba.WritebackVRatio[k] < 1.0) {
-+				mode_lib->vba.WritebackLumaVExtra =
-+						dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0);
-+			} else {
-+				mode_lib->vba.WritebackLumaVExtra = -1;
-+			}
-+			if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32
-+					&& mode_lib->vba.WritebackLumaVTaps[k]
-+							> (mode_lib->vba.WritebackLineBufferLumaBufferSize
-+									+ mode_lib->vba.WritebackLineBufferChromaBufferSize)
-+									/ 3.0
-+									/ mode_lib->vba.WritebackDestinationWidth[k]
-+									- mode_lib->vba.WritebackLumaVExtra)
-+					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
-+							&& mode_lib->vba.WritebackLumaVTaps[k]
-+									> mode_lib->vba.WritebackLineBufferLumaBufferSize
-+											/ mode_lib->vba.WritebackDestinationWidth[k]
-+											- mode_lib->vba.WritebackLumaVExtra)
-+					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
-+							&& mode_lib->vba.WritebackLumaVTaps[k]
-+									> mode_lib->vba.WritebackLineBufferLumaBufferSize
-+											* 8.0 / 10.0
-+											/ mode_lib->vba.WritebackDestinationWidth[k]
-+											- mode_lib->vba.WritebackLumaVExtra)) {
-+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
-+			}
-+			if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) {
-+				mode_lib->vba.WritebackChromaVExtra = 0.0;
-+			} else {
-+				mode_lib->vba.WritebackChromaVExtra = -1;
-+			}
-+			if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
-+					&& mode_lib->vba.WritebackChromaVTaps[k]
-+							> mode_lib->vba.WritebackLineBufferChromaBufferSize
-+									/ mode_lib->vba.WritebackDestinationWidth[k]
-+									- mode_lib->vba.WritebackChromaVExtra)
-+					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
-+							&& mode_lib->vba.WritebackChromaVTaps[k]
-+									> mode_lib->vba.WritebackLineBufferChromaBufferSize
-+											* 8.0 / 10.0
-+											/ mode_lib->vba.WritebackDestinationWidth[k]
-+											- mode_lib->vba.WritebackChromaVExtra)) {
-+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
-+			}
-+		}
-+	}
-+	/*Maximum DISPCLK/DPPCLK Support check*/
-+
-+	mode_lib->vba.WritebackRequiredDISPCLK = 0.0;
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if (mode_lib->vba.WritebackEnable[k] == true) {
-+			mode_lib->vba.WritebackRequiredDISPCLK =
-+					dml_max(
-+							mode_lib->vba.WritebackRequiredDISPCLK,
-+							CalculateWriteBackDISPCLK(
-+									mode_lib->vba.WritebackPixelFormat[k],
-+									mode_lib->vba.PixelClock[k],
-+									mode_lib->vba.WritebackHRatio[k],
-+									mode_lib->vba.WritebackVRatio[k],
-+									mode_lib->vba.WritebackLumaHTaps[k],
-+									mode_lib->vba.WritebackLumaVTaps[k],
-+									mode_lib->vba.WritebackChromaHTaps[k],
-+									mode_lib->vba.WritebackChromaVTaps[k],
-+									mode_lib->vba.WritebackDestinationWidth[k],
-+									mode_lib->vba.HTotal[k],
-+									mode_lib->vba.WritebackChromaLineBufferWidth));
-+		}
-+	}
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if (mode_lib->vba.HRatio[k] > 1.0) {
-+			mode_lib->vba.PSCL_FACTOR[k] = dml_min(
-+					mode_lib->vba.MaxDCHUBToPSCLThroughput,
-+					mode_lib->vba.MaxPSCLToLBThroughput
-+							* mode_lib->vba.HRatio[k]
-+							/ dml_ceil(
-+									mode_lib->vba.htaps[k]
-+											/ 6.0,
-+									1.0));
-+		} else {
-+			mode_lib->vba.PSCL_FACTOR[k] = dml_min(
-+					mode_lib->vba.MaxDCHUBToPSCLThroughput,
-+					mode_lib->vba.MaxPSCLToLBThroughput);
-+		}
-+		if (mode_lib->vba.BytePerPixelInDETC[k] == 0.0) {
-+			mode_lib->vba.PSCL_FACTOR_CHROMA[k] = 0.0;
-+			mode_lib->vba.MinDPPCLKUsingSingleDPP[k] =
-+					mode_lib->vba.PixelClock[k]
-+							* dml_max3(
-+									mode_lib->vba.vtaps[k] / 6.0
-+											* dml_min(
-+													1.0,
-+													mode_lib->vba.HRatio[k]),
-+									mode_lib->vba.HRatio[k]
-+											* mode_lib->vba.VRatio[k]
-+											/ mode_lib->vba.PSCL_FACTOR[k],
-+									1.0);
-+			if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0)
-+					&& mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
-+							< 2.0 * mode_lib->vba.PixelClock[k]) {
-+				mode_lib->vba.MinDPPCLKUsingSingleDPP[k] = 2.0
-+						* mode_lib->vba.PixelClock[k];
-+			}
-+		} else {
-+			if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) {
-+				mode_lib->vba.PSCL_FACTOR_CHROMA[k] =
-+						dml_min(
-+								mode_lib->vba.MaxDCHUBToPSCLThroughput,
-+								mode_lib->vba.MaxPSCLToLBThroughput
-+										* mode_lib->vba.HRatio[k]
-+										/ 2.0
-+										/ dml_ceil(
-+												mode_lib->vba.HTAPsChroma[k]
-+														/ 6.0,
-+												1.0));
-+			} else {
-+				mode_lib->vba.PSCL_FACTOR_CHROMA[k] = dml_min(
-+						mode_lib->vba.MaxDCHUBToPSCLThroughput,
-+						mode_lib->vba.MaxPSCLToLBThroughput);
-+			}
-+			mode_lib->vba.MinDPPCLKUsingSingleDPP[k] =
-+					mode_lib->vba.PixelClock[k]
-+							* dml_max5(
-+									mode_lib->vba.vtaps[k] / 6.0
-+											* dml_min(
-+													1.0,
-+													mode_lib->vba.HRatio[k]),
-+									mode_lib->vba.HRatio[k]
-+											* mode_lib->vba.VRatio[k]
-+											/ mode_lib->vba.PSCL_FACTOR[k],
-+									mode_lib->vba.VTAPsChroma[k]
-+											/ 6.0
-+											* dml_min(
-+													1.0,
-+													mode_lib->vba.HRatio[k]
-+															/ 2.0),
-+									mode_lib->vba.HRatio[k]
-+											* mode_lib->vba.VRatio[k]
-+											/ 4.0
-+											/ mode_lib->vba.PSCL_FACTOR_CHROMA[k],
-+									1.0);
-+			if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0
-+					|| mode_lib->vba.HTAPsChroma[k] > 6.0
-+					|| mode_lib->vba.VTAPsChroma[k] > 6.0)
-+					&& mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
-+							< 2.0 * mode_lib->vba.PixelClock[k]) {
-+				mode_lib->vba.MinDPPCLKUsingSingleDPP[k] = 2.0
-+						* mode_lib->vba.PixelClock[k];
-+			}
-+		}
-+	}
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		Calculate256BBlockSizes(
-+				mode_lib->vba.SourcePixelFormat[k],
-+				mode_lib->vba.SurfaceTiling[k],
-+				dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0),
-+				dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0),
-+				&mode_lib->vba.Read256BlockHeightY[k],
-+				&mode_lib->vba.Read256BlockHeightC[k],
-+				&mode_lib->vba.Read256BlockWidthY[k],
-+				&mode_lib->vba.Read256BlockWidthC[k]);
-+		if (mode_lib->vba.SourceScan[k] == dm_horz) {
-+			mode_lib->vba.MaxSwathHeightY[k] = mode_lib->vba.Read256BlockHeightY[k];
-+			mode_lib->vba.MaxSwathHeightC[k] = mode_lib->vba.Read256BlockHeightC[k];
-+		} else {
-+			mode_lib->vba.MaxSwathHeightY[k] = mode_lib->vba.Read256BlockWidthY[k];
-+			mode_lib->vba.MaxSwathHeightC[k] = mode_lib->vba.Read256BlockWidthC[k];
-+		}
-+		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
-+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
-+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
-+				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16
-+				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) {
-+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
-+					|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
-+							&& (mode_lib->vba.SurfaceTiling[k]
-+									== dm_sw_4kb_s
-+									|| mode_lib->vba.SurfaceTiling[k]
-+											== dm_sw_4kb_s_x
-+									|| mode_lib->vba.SurfaceTiling[k]
-+											== dm_sw_64kb_s
-+									|| mode_lib->vba.SurfaceTiling[k]
-+											== dm_sw_64kb_s_t
-+									|| mode_lib->vba.SurfaceTiling[k]
-+											== dm_sw_64kb_s_x
-+									|| mode_lib->vba.SurfaceTiling[k]
-+											== dm_sw_var_s
-+									|| mode_lib->vba.SurfaceTiling[k]
-+											== dm_sw_var_s_x)
-+							&& mode_lib->vba.SourceScan[k] == dm_horz)) {
-+				mode_lib->vba.MinSwathHeightY[k] = mode_lib->vba.MaxSwathHeightY[k];
-+			} else {
-+				mode_lib->vba.MinSwathHeightY[k] = mode_lib->vba.MaxSwathHeightY[k]
-+						/ 2.0;
-+			}
-+			mode_lib->vba.MinSwathHeightC[k] = mode_lib->vba.MaxSwathHeightC[k];
-+		} else {
-+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
-+				mode_lib->vba.MinSwathHeightY[k] = mode_lib->vba.MaxSwathHeightY[k];
-+				mode_lib->vba.MinSwathHeightC[k] = mode_lib->vba.MaxSwathHeightC[k];
-+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
-+					&& mode_lib->vba.SourceScan[k] == dm_horz) {
-+				mode_lib->vba.MinSwathHeightY[k] = mode_lib->vba.MaxSwathHeightY[k]
-+						/ 2.0;
-+				mode_lib->vba.MinSwathHeightC[k] = mode_lib->vba.MaxSwathHeightC[k];
-+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
-+					&& mode_lib->vba.SourceScan[k] == dm_horz) {
-+				mode_lib->vba.MinSwathHeightC[k] = mode_lib->vba.MaxSwathHeightC[k]
-+						/ 2.0;
-+				mode_lib->vba.MinSwathHeightY[k] = mode_lib->vba.MaxSwathHeightY[k];
-+			} else {
-+				mode_lib->vba.MinSwathHeightY[k] = mode_lib->vba.MaxSwathHeightY[k];
-+				mode_lib->vba.MinSwathHeightC[k] = mode_lib->vba.MaxSwathHeightC[k];
-+			}
-+		}
-+		if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
-+			mode_lib->vba.MaximumSwathWidthSupport = 8192.0;
-+		} else {
-+			mode_lib->vba.MaximumSwathWidthSupport = 5120.0;
-+		}
-+		mode_lib->vba.MaximumSwathWidthInDETBuffer =
-+				dml_min(
-+						mode_lib->vba.MaximumSwathWidthSupport,
-+						mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0
-+								/ (mode_lib->vba.BytePerPixelInDETY[k]
-+										* mode_lib->vba.MinSwathHeightY[k]
-+										+ mode_lib->vba.BytePerPixelInDETC[k]
-+												/ 2.0
-+												* mode_lib->vba.MinSwathHeightC[k]));
-+		if (mode_lib->vba.BytePerPixelInDETC[k] == 0.0) {
-+			mode_lib->vba.MaximumSwathWidthInLineBuffer =
-+					mode_lib->vba.LineBufferSize
-+							* dml_max(mode_lib->vba.HRatio[k], 1.0)
-+							/ mode_lib->vba.LBBitPerPixel[k]
-+							/ (mode_lib->vba.vtaps[k]
-+									+ dml_max(
-+											dml_ceil(
-+													mode_lib->vba.VRatio[k],
-+													1.0)
-+													- 2,
-+											0.0));
-+		} else {
-+			mode_lib->vba.MaximumSwathWidthInLineBuffer =
-+					dml_min(
-+							mode_lib->vba.LineBufferSize
-+									* dml_max(
-+											mode_lib->vba.HRatio[k],
-+											1.0)
-+									/ mode_lib->vba.LBBitPerPixel[k]
-+									/ (mode_lib->vba.vtaps[k]
-+											+ dml_max(
-+													dml_ceil(
-+															mode_lib->vba.VRatio[k],
-+															1.0)
-+															- 2,
-+													0.0)),
-+							2.0 * mode_lib->vba.LineBufferSize
-+									* dml_max(
-+											mode_lib->vba.HRatio[k]
-+													/ 2.0,
-+											1.0)
-+									/ mode_lib->vba.LBBitPerPixel[k]
-+									/ (mode_lib->vba.VTAPsChroma[k]
-+											+ dml_max(
-+													dml_ceil(
-+															mode_lib->vba.VRatio[k]
-+																	/ 2.0,
-+															1.0)
-+															- 2,
-+													0.0)));
-+		}
-+		mode_lib->vba.MaximumSwathWidth[k] = dml_min(
-+				mode_lib->vba.MaximumSwathWidthInDETBuffer,
-+				mode_lib->vba.MaximumSwathWidthInLineBuffer);
-+	}
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(
-+				mode_lib->vba.MaxDispclk[i],
-+				mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
-+		mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(
-+				mode_lib->vba.MaxDppclk[i],
-+				mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
-+		mode_lib->vba.RequiredDISPCLK[i] = 0.0;
-+		mode_lib->vba.DISPCLK_DPPCLK_Support[i] = true;
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine =
-+					mode_lib->vba.PixelClock[k]
-+							* (1.0
-+									+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+											/ 100.0)
-+							* (1.0
-+									+ mode_lib->vba.DISPCLKRampingMargin
-+											/ 100.0);
-+			if (mode_lib->vba.ODMCapability == true
-+					&& mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine
-+							> mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
-+				mode_lib->vba.ODMCombineEnablePerState[i][k] = true;
-+				mode_lib->vba.PlaneRequiredDISPCLK =
-+						mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine
-+								/ 2.0;
-+			} else {
-+				mode_lib->vba.ODMCombineEnablePerState[i][k] = false;
-+				mode_lib->vba.PlaneRequiredDISPCLK =
-+						mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
-+			}
-+			if (mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
-+					* (1.0
-+							+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+									/ 100.0)
-+					<= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
-+					&& mode_lib->vba.SwathWidthYSingleDPP[k]
-+							<= mode_lib->vba.MaximumSwathWidth[k]
-+					&& mode_lib->vba.ODMCombineEnablePerState[i][k] == false) {
-+				mode_lib->vba.NoOfDPP[i][k] = 1;
-+				mode_lib->vba.RequiredDPPCLK[i][k] =
-+						mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
-+								* (1.0
-+										+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+												/ 100.0);
-+			} else {
-+				mode_lib->vba.NoOfDPP[i][k] = 2;
-+				mode_lib->vba.RequiredDPPCLK[i][k] =
-+						mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
-+								* (1.0
-+										+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+												/ 100.0)
-+								/ 2.0;
-+			}
-+			mode_lib->vba.RequiredDISPCLK[i] = dml_max(
-+					mode_lib->vba.RequiredDISPCLK[i],
-+					mode_lib->vba.PlaneRequiredDISPCLK);
-+			if ((mode_lib->vba.MinDPPCLKUsingSingleDPP[k] / mode_lib->vba.NoOfDPP[i][k]
-+					* (1.0
-+							+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+									/ 100.0)
-+					> mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity)
-+					|| (mode_lib->vba.PlaneRequiredDISPCLK
-+							> mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity)) {
-+				mode_lib->vba.DISPCLK_DPPCLK_Support[i] = false;
-+			}
-+		}
-+		mode_lib->vba.TotalNumberOfActiveDPP[i] = 0.0;
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			mode_lib->vba.TotalNumberOfActiveDPP[i] =
-+					mode_lib->vba.TotalNumberOfActiveDPP[i]
-+							+ mode_lib->vba.NoOfDPP[i][k];
-+		}
-+		if ((mode_lib->vba.MaxDispclk[i] == mode_lib->vba.MaxDispclk[DC__VOLTAGE_STATES]
-+				&& mode_lib->vba.MaxDppclk[i]
-+						== mode_lib->vba.MaxDppclk[DC__VOLTAGE_STATES])
-+				&& (mode_lib->vba.TotalNumberOfActiveDPP[i]
-+						> mode_lib->vba.MaxNumDPP
-+						|| mode_lib->vba.DISPCLK_DPPCLK_Support[i] == false)) {
-+			mode_lib->vba.RequiredDISPCLK[i] = 0.0;
-+			mode_lib->vba.DISPCLK_DPPCLK_Support[i] = true;
-+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+				mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine =
-+						mode_lib->vba.PixelClock[k]
-+								* (1.0
-+										+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+												/ 100.0);
-+				if (mode_lib->vba.ODMCapability == true
-+						&& mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine
-+								> mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
-+					mode_lib->vba.ODMCombineEnablePerState[i][k] = true;
-+					mode_lib->vba.PlaneRequiredDISPCLK =
-+							mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine
-+									/ 2.0;
-+				} else {
-+					mode_lib->vba.ODMCombineEnablePerState[i][k] = false;
-+					mode_lib->vba.PlaneRequiredDISPCLK =
-+							mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
-+				}
-+				if (mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
-+						* (1.0
-+								+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+										/ 100.0)
-+						<= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
-+						&& mode_lib->vba.SwathWidthYSingleDPP[k]
-+								<= mode_lib->vba.MaximumSwathWidth[k]
-+						&& mode_lib->vba.ODMCombineEnablePerState[i][k]
-+								== false) {
-+					mode_lib->vba.NoOfDPP[i][k] = 1;
-+					mode_lib->vba.RequiredDPPCLK[i][k] =
-+							mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
-+									* (1.0
-+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+													/ 100.0);
-+				} else {
-+					mode_lib->vba.NoOfDPP[i][k] = 2;
-+					mode_lib->vba.RequiredDPPCLK[i][k] =
-+							mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
-+									* (1.0
-+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+													/ 100.0)
-+									/ 2.0;
-+				}
-+				mode_lib->vba.RequiredDISPCLK[i] = dml_max(
-+						mode_lib->vba.RequiredDISPCLK[i],
-+						mode_lib->vba.PlaneRequiredDISPCLK);
-+				if ((mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
-+						/ mode_lib->vba.NoOfDPP[i][k]
-+						* (1.0
-+								+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+										/ 100.0)
-+						> mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity)
-+						|| (mode_lib->vba.PlaneRequiredDISPCLK
-+								> mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity)) {
-+					mode_lib->vba.DISPCLK_DPPCLK_Support[i] = false;
-+				}
-+			}
-+			mode_lib->vba.TotalNumberOfActiveDPP[i] = 0.0;
-+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+				mode_lib->vba.TotalNumberOfActiveDPP[i] =
-+						mode_lib->vba.TotalNumberOfActiveDPP[i]
-+								+ mode_lib->vba.NoOfDPP[i][k];
-+			}
-+		}
-+		if (mode_lib->vba.TotalNumberOfActiveDPP[i] > mode_lib->vba.MaxNumDPP) {
-+			mode_lib->vba.RequiredDISPCLK[i] = 0.0;
-+			mode_lib->vba.DISPCLK_DPPCLK_Support[i] = true;
-+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+				mode_lib->vba.ODMCombineEnablePerState[i][k] = false;
-+				if (mode_lib->vba.SwathWidthYSingleDPP[k]
-+						<= mode_lib->vba.MaximumSwathWidth[k]) {
-+					mode_lib->vba.NoOfDPP[i][k] = 1;
-+					mode_lib->vba.RequiredDPPCLK[i][k] =
-+							mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
-+									* (1.0
-+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+													/ 100.0);
-+				} else {
-+					mode_lib->vba.NoOfDPP[i][k] = 2;
-+					mode_lib->vba.RequiredDPPCLK[i][k] =
-+							mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
-+									* (1.0
-+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+													/ 100.0)
-+									/ 2.0;
-+				}
-+				if (!(mode_lib->vba.MaxDispclk[i]
-+						== mode_lib->vba.MaxDispclk[DC__VOLTAGE_STATES]
-+						&& mode_lib->vba.MaxDppclk[i]
-+								== mode_lib->vba.MaxDppclk[DC__VOLTAGE_STATES])) {
-+					mode_lib->vba.PlaneRequiredDISPCLK =
-+							mode_lib->vba.PixelClock[k]
-+									* (1.0
-+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+													/ 100.0)
-+									* (1.0
-+											+ mode_lib->vba.DISPCLKRampingMargin
-+													/ 100.0);
-+				} else {
-+					mode_lib->vba.PlaneRequiredDISPCLK =
-+							mode_lib->vba.PixelClock[k]
-+									* (1.0
-+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+													/ 100.0);
-+				}
-+				mode_lib->vba.RequiredDISPCLK[i] = dml_max(
-+						mode_lib->vba.RequiredDISPCLK[i],
-+						mode_lib->vba.PlaneRequiredDISPCLK);
-+				if ((mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
-+						/ mode_lib->vba.NoOfDPP[i][k]
-+						* (1.0
-+								+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+										/ 100.0)
-+						> mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity)
-+						|| (mode_lib->vba.PlaneRequiredDISPCLK
-+								> mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity)) {
-+					mode_lib->vba.DISPCLK_DPPCLK_Support[i] = false;
-+				}
-+			}
-+			mode_lib->vba.TotalNumberOfActiveDPP[i] = 0.0;
-+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+				mode_lib->vba.TotalNumberOfActiveDPP[i] =
-+						mode_lib->vba.TotalNumberOfActiveDPP[i]
-+								+ mode_lib->vba.NoOfDPP[i][k];
-+			}
-+		}
-+		mode_lib->vba.RequiredDISPCLK[i] = dml_max(
-+				mode_lib->vba.RequiredDISPCLK[i],
-+				mode_lib->vba.WritebackRequiredDISPCLK);
-+		if (mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity
-+				< mode_lib->vba.WritebackRequiredDISPCLK) {
-+			mode_lib->vba.DISPCLK_DPPCLK_Support[i] = false;
-+		}
-+	}
-+	/*Viewport Size Check*/
-+
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		mode_lib->vba.ViewportSizeSupport[i] = true;
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			if (mode_lib->vba.ODMCombineEnablePerState[i][k] == true) {
-+				if (dml_min(
-+						mode_lib->vba.SwathWidthYSingleDPP[k],
-+						dml_round(
-+								mode_lib->vba.HActive[k] / 2.0
-+										* mode_lib->vba.HRatio[k]))
-+						> mode_lib->vba.MaximumSwathWidth[k]) {
-+					mode_lib->vba.ViewportSizeSupport[i] = false;
-+				}
-+			} else {
-+				if (mode_lib->vba.SwathWidthYSingleDPP[k] / 2.0
-+						> mode_lib->vba.MaximumSwathWidth[k]) {
-+					mode_lib->vba.ViewportSizeSupport[i] = false;
-+				}
-+			}
-+		}
-+	}
-+	/*Total Available Pipes Support Check*/
-+
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		if (mode_lib->vba.TotalNumberOfActiveDPP[i] <= mode_lib->vba.MaxNumDPP) {
-+			mode_lib->vba.TotalAvailablePipesSupport[i] = true;
-+		} else {
-+			mode_lib->vba.TotalAvailablePipesSupport[i] = false;
-+		}
-+	}
-+	/*Total Available OTG Support Check*/
-+
-+	mode_lib->vba.TotalNumberOfActiveOTG = 0.0;
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
-+			mode_lib->vba.TotalNumberOfActiveOTG = mode_lib->vba.TotalNumberOfActiveOTG
-+					+ 1.0;
-+		}
-+	}
-+	if (mode_lib->vba.TotalNumberOfActiveOTG <= mode_lib->vba.MaxNumOTG) {
-+		mode_lib->vba.NumberOfOTGSupport = true;
-+	} else {
-+		mode_lib->vba.NumberOfOTGSupport = false;
-+	}
-+	/*Display IO and DSC Support Check*/
-+
-+	mode_lib->vba.NonsupportedDSCInputBPC = false;
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
-+				|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
-+				|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) {
-+			mode_lib->vba.NonsupportedDSCInputBPC = true;
-+		}
-+	}
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			mode_lib->vba.RequiresDSC[i][k] = 0;
-+			mode_lib->vba.RequiresFEC[i][k] = 0;
-+			if (mode_lib->vba.BlendingAndTiming[k] == k) {
-+				if (mode_lib->vba.Output[k] == dm_hdmi) {
-+					mode_lib->vba.RequiresDSC[i][k] = 0;
-+					mode_lib->vba.RequiresFEC[i][k] = 0;
-+					mode_lib->vba.OutputBppPerState[i][k] =
-+							TruncToValidBPP(
-+									dml_min(
-+											600.0,
-+											mode_lib->vba.PHYCLKPerState[i])
-+											/ mode_lib->vba.PixelClockBackEnd[k]
-+											* 24,
-+									false,
-+									mode_lib->vba.Output[k],
-+									mode_lib->vba.OutputFormat[k],
-+									mode_lib->vba.DSCInputBitPerComponent[k]);
-+				} else if (mode_lib->vba.Output[k] == dm_dp
-+						|| mode_lib->vba.Output[k] == dm_edp) {
-+					if (mode_lib->vba.Output[k] == dm_edp) {
-+						mode_lib->vba.EffectiveFECOverhead = 0.0;
-+					} else {
-+						mode_lib->vba.EffectiveFECOverhead =
-+								mode_lib->vba.FECOverhead;
-+					}
-+					if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) {
-+						mode_lib->vba.Outbpp =
-+								TruncToValidBPP(
-+										(1.0
-+												- mode_lib->vba.Downspreading
-+														/ 100.0)
-+												* 270.0
-+												* mode_lib->vba.OutputLinkDPLanes[k]
-+												/ mode_lib->vba.PixelClockBackEnd[k]
-+												* 8.0,
-+										false,
-+										mode_lib->vba.Output[k],
-+										mode_lib->vba.OutputFormat[k],
-+										mode_lib->vba.DSCInputBitPerComponent[k]);
-+						mode_lib->vba.OutbppDSC =
-+								TruncToValidBPP(
-+										(1.0
-+												- mode_lib->vba.Downspreading
-+														/ 100.0)
-+												* (1.0
-+														- mode_lib->vba.EffectiveFECOverhead
-+																/ 100.0)
-+												* 270.0
-+												* mode_lib->vba.OutputLinkDPLanes[k]
-+												/ mode_lib->vba.PixelClockBackEnd[k]
-+												* 8.0,
-+										true,
-+										mode_lib->vba.Output[k],
-+										mode_lib->vba.OutputFormat[k],
-+										mode_lib->vba.DSCInputBitPerComponent[k]);
-+						if (mode_lib->vba.DSCEnabled[k] == true) {
-+							mode_lib->vba.RequiresDSC[i][k] = true;
-+							if (mode_lib->vba.Output[k] == dm_dp) {
-+								mode_lib->vba.RequiresFEC[i][k] =
-+										true;
-+							} else {
-+								mode_lib->vba.RequiresFEC[i][k] =
-+										false;
-+							}
-+							mode_lib->vba.Outbpp =
-+									mode_lib->vba.OutbppDSC;
-+						} else {
-+							mode_lib->vba.RequiresDSC[i][k] = false;
-+							mode_lib->vba.RequiresFEC[i][k] = false;
-+						}
-+						mode_lib->vba.OutputBppPerState[i][k] =
-+								mode_lib->vba.Outbpp;
-+					}
-+					if (mode_lib->vba.Outbpp == 0) {
-+						mode_lib->vba.Outbpp =
-+								TruncToValidBPP(
-+										(1.0
-+												- mode_lib->vba.Downspreading
-+														/ 100.0)
-+												* 540.0
-+												* mode_lib->vba.OutputLinkDPLanes[k]
-+												/ mode_lib->vba.PixelClockBackEnd[k]
-+												* 8.0,
-+										false,
-+										mode_lib->vba.Output[k],
-+										mode_lib->vba.OutputFormat[k],
-+										mode_lib->vba.DSCInputBitPerComponent[k]);
-+						mode_lib->vba.OutbppDSC =
-+								TruncToValidBPP(
-+										(1.0
-+												- mode_lib->vba.Downspreading
-+														/ 100.0)
-+												* (1.0
-+														- mode_lib->vba.EffectiveFECOverhead
-+																/ 100.0)
-+												* 540.0
-+												* mode_lib->vba.OutputLinkDPLanes[k]
-+												/ mode_lib->vba.PixelClockBackEnd[k]
-+												* 8.0,
-+										true,
-+										mode_lib->vba.Output[k],
-+										mode_lib->vba.OutputFormat[k],
-+										mode_lib->vba.DSCInputBitPerComponent[k]);
-+						if (mode_lib->vba.DSCEnabled[k] == true) {
-+							mode_lib->vba.RequiresDSC[i][k] = true;
-+							if (mode_lib->vba.Output[k] == dm_dp) {
-+								mode_lib->vba.RequiresFEC[i][k] =
-+										true;
-+							} else {
-+								mode_lib->vba.RequiresFEC[i][k] =
-+										false;
-+							}
-+							mode_lib->vba.Outbpp =
-+									mode_lib->vba.OutbppDSC;
-+						} else {
-+							mode_lib->vba.RequiresDSC[i][k] = false;
-+							mode_lib->vba.RequiresFEC[i][k] = false;
-+						}
-+						mode_lib->vba.OutputBppPerState[i][k] =
-+								mode_lib->vba.Outbpp;
-+					}
-+					if (mode_lib->vba.Outbpp == 0
-+							&& mode_lib->vba.PHYCLKPerState[i]
-+									>= 810.0) {
-+						mode_lib->vba.Outbpp =
-+								TruncToValidBPP(
-+										(1.0
-+												- mode_lib->vba.Downspreading
-+														/ 100.0)
-+												* 810.0
-+												* mode_lib->vba.OutputLinkDPLanes[k]
-+												/ mode_lib->vba.PixelClockBackEnd[k]
-+												* 8.0,
-+										false,
-+										mode_lib->vba.Output[k],
-+										mode_lib->vba.OutputFormat[k],
-+										mode_lib->vba.DSCInputBitPerComponent[k]);
-+						mode_lib->vba.OutbppDSC =
-+								TruncToValidBPP(
-+										(1.0
-+												- mode_lib->vba.Downspreading
-+														/ 100.0)
-+												* (1.0
-+														- mode_lib->vba.EffectiveFECOverhead
-+																/ 100.0)
-+												* 810.0
-+												* mode_lib->vba.OutputLinkDPLanes[k]
-+												/ mode_lib->vba.PixelClockBackEnd[k]
-+												* 8.0,
-+										true,
-+										mode_lib->vba.Output[k],
-+										mode_lib->vba.OutputFormat[k],
-+										mode_lib->vba.DSCInputBitPerComponent[k]);
-+						if (mode_lib->vba.DSCEnabled[k] == true
-+								|| mode_lib->vba.Outbpp == 0) {
-+							mode_lib->vba.RequiresDSC[i][k] = true;
-+							if (mode_lib->vba.Output[k] == dm_dp) {
-+								mode_lib->vba.RequiresFEC[i][k] =
-+										true;
-+							} else {
-+								mode_lib->vba.RequiresFEC[i][k] =
-+										false;
-+							}
-+							mode_lib->vba.Outbpp =
-+									mode_lib->vba.OutbppDSC;
-+						} else {
-+							mode_lib->vba.RequiresDSC[i][k] = false;
-+							mode_lib->vba.RequiresFEC[i][k] = false;
-+						}
-+						mode_lib->vba.OutputBppPerState[i][k] =
-+								mode_lib->vba.Outbpp;
-+					}
-+				}
-+			} else {
-+				mode_lib->vba.OutputBppPerState[i][k] = 0;
-+			}
-+		}
-+	}
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		mode_lib->vba.DIOSupport[i] = true;
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			if (mode_lib->vba.OutputBppPerState[i][k] == 0
-+					|| (mode_lib->vba.OutputFormat[k] == dm_420
-+							&& mode_lib->vba.ProgressiveToInterlaceUnitInOPP
-+									== true)) {
-+				mode_lib->vba.DIOSupport[i] = false;
-+			}
-+		}
-+	}
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] = false;
-+			if (mode_lib->vba.BlendingAndTiming[k] == k) {
-+				if ((mode_lib->vba.Output[k] == dm_dp
-+						|| mode_lib->vba.Output[k] == dm_edp)) {
-+					if (mode_lib->vba.OutputFormat[k] == dm_420
-+							|| mode_lib->vba.OutputFormat[k]
-+									== dm_n422) {
-+						mode_lib->vba.DSCFormatFactor = 2;
-+					} else {
-+						mode_lib->vba.DSCFormatFactor = 1;
-+					}
-+					if (mode_lib->vba.RequiresDSC[i][k] == true) {
-+						if (mode_lib->vba.ODMCombineEnablePerState[i][k]
-+								== true) {
-+							if (mode_lib->vba.PixelClockBackEnd[k] / 6.0
-+									/ mode_lib->vba.DSCFormatFactor
-+									> (1.0
-+											- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+													/ 100.0)
-+											* mode_lib->vba.MaxDSCCLK[i]) {
-+								mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] =
-+										true;
-+							}
-+						} else {
-+							if (mode_lib->vba.PixelClockBackEnd[k] / 3.0
-+									/ mode_lib->vba.DSCFormatFactor
-+									> (1.0
-+											- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-+													/ 100.0)
-+											* mode_lib->vba.MaxDSCCLK[i]) {
-+								mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] =
-+										true;
-+							}
-+						}
-+					}
-+				}
-+			}
-+		}
-+	}
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		mode_lib->vba.NotEnoughDSCUnits[i] = false;
-+		mode_lib->vba.TotalDSCUnitsRequired = 0.0;
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			if (mode_lib->vba.RequiresDSC[i][k] == true) {
-+				if (mode_lib->vba.ODMCombineEnablePerState[i][k] == true) {
-+					mode_lib->vba.TotalDSCUnitsRequired =
-+							mode_lib->vba.TotalDSCUnitsRequired + 2.0;
-+				} else {
-+					mode_lib->vba.TotalDSCUnitsRequired =
-+							mode_lib->vba.TotalDSCUnitsRequired + 1.0;
-+				}
-+			}
-+		}
-+		if (mode_lib->vba.TotalDSCUnitsRequired > mode_lib->vba.NumberOfDSC) {
-+			mode_lib->vba.NotEnoughDSCUnits[i] = true;
-+		}
-+	}
-+	/*DSC Delay per state*/
-+
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			if (mode_lib->vba.BlendingAndTiming[k] != k) {
-+				mode_lib->vba.slices = 0;
-+			} else if (mode_lib->vba.RequiresDSC[i][k] == 0
-+					|| mode_lib->vba.RequiresDSC[i][k] == false) {
-+				mode_lib->vba.slices = 0;
-+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) {
-+				mode_lib->vba.slices = dml_ceil(
-+						mode_lib->vba.PixelClockBackEnd[k] / 400.0,
-+						4.0);
-+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) {
-+				mode_lib->vba.slices = 8.0;
-+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) {
-+				mode_lib->vba.slices = 4.0;
-+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) {
-+				mode_lib->vba.slices = 2.0;
-+			} else {
-+				mode_lib->vba.slices = 1.0;
-+			}
-+			if (mode_lib->vba.OutputBppPerState[i][k] == 0
-+					|| mode_lib->vba.OutputBppPerState[i][k] == 0) {
-+				mode_lib->vba.bpp = 0.0;
-+			} else {
-+				mode_lib->vba.bpp = mode_lib->vba.OutputBppPerState[i][k];
-+			}
-+			if (mode_lib->vba.RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) {
-+				if (mode_lib->vba.ODMCombineEnablePerState[i][k] == false) {
-+					mode_lib->vba.DSCDelayPerState[i][k] =
-+							dscceComputeDelay(
-+									mode_lib->vba.DSCInputBitPerComponent[k],
-+									mode_lib->vba.bpp,
-+									dml_ceil(
-+											mode_lib->vba.HActive[k]
-+													/ mode_lib->vba.slices,
-+											1.0),
-+									mode_lib->vba.slices,
-+									mode_lib->vba.OutputFormat[k])
-+									+ dscComputeDelay(
-+											mode_lib->vba.OutputFormat[k]);
-+				} else {
-+					mode_lib->vba.DSCDelayPerState[i][k] =
-+							2.0
-+									* (dscceComputeDelay(
-+											mode_lib->vba.DSCInputBitPerComponent[k],
-+											mode_lib->vba.bpp,
-+											dml_ceil(
-+													mode_lib->vba.HActive[k]
-+															/ mode_lib->vba.slices,
-+													1.0),
-+											mode_lib->vba.slices
-+													/ 2,
-+											mode_lib->vba.OutputFormat[k])
-+											+ dscComputeDelay(
-+													mode_lib->vba.OutputFormat[k]));
-+				}
-+				mode_lib->vba.DSCDelayPerState[i][k] =
-+						mode_lib->vba.DSCDelayPerState[i][k]
-+								* mode_lib->vba.PixelClock[k]
-+								/ mode_lib->vba.PixelClockBackEnd[k];
-+			} else {
-+				mode_lib->vba.DSCDelayPerState[i][k] = 0.0;
-+			}
-+		}
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			for (j = 0; j <= mode_lib->vba.NumberOfActivePlanes - 1; j++) {
-+				if (mode_lib->vba.BlendingAndTiming[k] == j
-+						&& mode_lib->vba.RequiresDSC[i][j] == true) {
-+					mode_lib->vba.DSCDelayPerState[i][k] =
-+							mode_lib->vba.DSCDelayPerState[i][j];
-+				}
-+			}
-+		}
-+	}
-+	/*Urgent Latency Support Check*/
-+
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+			if (mode_lib->vba.ODMCombineEnablePerState[i][k] == true) {
-+				mode_lib->vba.SwathWidthYPerState[i][k] =
-+						dml_min(
-+								mode_lib->vba.SwathWidthYSingleDPP[k],
-+								dml_round(
-+										mode_lib->vba.HActive[k]
-+												/ 2.0
-+												* mode_lib->vba.HRatio[k]));
-+			} else {
-+				mode_lib->vba.SwathWidthYPerState[i][k] =
-+						mode_lib->vba.SwathWidthYSingleDPP[k]
-+								/ mode_lib->vba.NoOfDPP[i][k];
-+			}
-+			mode_lib->vba.SwathWidthGranularityY = 256.0
-+					/ dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0)
-+					/ mode_lib->vba.MaxSwathHeightY[k];
-+			mode_lib->vba.RoundedUpMaxSwathSizeBytesY = (dml_ceil(
-+					mode_lib->vba.SwathWidthYPerState[i][k] - 1.0,
-+					mode_lib->vba.SwathWidthGranularityY)
-+					+ mode_lib->vba.SwathWidthGranularityY)
-+					* mode_lib->vba.BytePerPixelInDETY[k]
-+					* mode_lib->vba.MaxSwathHeightY[k];
-+			if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
-+				mode_lib->vba.RoundedUpMaxSwathSizeBytesY = dml_ceil(
-+						mode_lib->vba.RoundedUpMaxSwathSizeBytesY,
-+						256.0) + 256;
-+			}
-+			if (mode_lib->vba.MaxSwathHeightC[k] > 0.0) {
-+				mode_lib->vba.SwathWidthGranularityC = 256.0
-+						/ dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0)
-+						/ mode_lib->vba.MaxSwathHeightC[k];
-+				mode_lib->vba.RoundedUpMaxSwathSizeBytesC = (dml_ceil(
-+						mode_lib->vba.SwathWidthYPerState[i][k] / 2.0 - 1.0,
-+						mode_lib->vba.SwathWidthGranularityC)
-+						+ mode_lib->vba.SwathWidthGranularityC)
-+						* mode_lib->vba.BytePerPixelInDETC[k]
-+						* mode_lib->vba.MaxSwathHeightC[k];
-+				if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
-+					mode_lib->vba.RoundedUpMaxSwathSizeBytesC = dml_ceil(
-+							mode_lib->vba.RoundedUpMaxSwathSizeBytesC,
-+							256.0) + 256;
-+				}
-+			} else {
-+				mode_lib->vba.RoundedUpMaxSwathSizeBytesC = 0.0;
-+			}
-+			if (mode_lib->vba.RoundedUpMaxSwathSizeBytesY
-+					+ mode_lib->vba.RoundedUpMaxSwathSizeBytesC
-+					<= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) {
-+				mode_lib->vba.SwathHeightYPerState[i][k] =
-+						mode_lib->vba.MaxSwathHeightY[k];
-+				mode_lib->vba.SwathHeightCPerState[i][k] =
-+						mode_lib->vba.MaxSwathHeightC[k];
-+			} else {
-+				mode_lib->vba.SwathHeightYPerState[i][k] =
-+						mode_lib->vba.MinSwathHeightY[k];
-+				mode_lib->vba.SwathHeightCPerState[i][k] =
-+						mode_lib->vba.MinSwathHeightC[k];
-+			}
-+			if (mode_lib->vba.BytePerPixelInDETC[k] == 0.0) {
-+				mode_lib->vba.LinesInDETLuma = mode_lib->vba.DETBufferSizeInKByte
-+						* 1024.0 / mode_lib->vba.BytePerPixelInDETY[k]
-+						/ mode_lib->vba.SwathWidthYPerState[i][k];
-+				mode_lib->vba.LinesInDETChroma = 0.0;
-+			} else if (mode_lib->vba.SwathHeightYPerState[i][k]
-+					<= mode_lib->vba.SwathHeightCPerState[i][k]) {
-+				mode_lib->vba.LinesInDETLuma = mode_lib->vba.DETBufferSizeInKByte
-+						* 1024.0 / 2.0 / mode_lib->vba.BytePerPixelInDETY[k]
-+						/ mode_lib->vba.SwathWidthYPerState[i][k];
-+				mode_lib->vba.LinesInDETChroma = mode_lib->vba.DETBufferSizeInKByte
-+						* 1024.0 / 2.0 / mode_lib->vba.BytePerPixelInDETC[k]
-+						/ (mode_lib->vba.SwathWidthYPerState[i][k] / 2.0);
-+			} else {
-+				mode_lib->vba.LinesInDETLuma = mode_lib->vba.DETBufferSizeInKByte
-+						* 1024.0 * 2.0 / 3.0
-+						/ mode_lib->vba.BytePerPixelInDETY[k]
-+						/ mode_lib->vba.SwathWidthYPerState[i][k];
-+				mode_lib->vba.LinesInDETChroma = mode_lib->vba.DETBufferSizeInKByte
-+						* 1024.0 / 3.0 / mode_lib->vba.BytePerPixelInDETY[k]
-+						/ (mode_lib->vba.SwathWidthYPerState[i][k] / 2.0);
-+			}
-+			mode_lib->vba.EffectiveLBLatencyHidingSourceLinesLuma =
-+					dml_min(
-+							mode_lib->vba.MaxLineBufferLines,
-+							dml_floor(
-+									mode_lib->vba.LineBufferSize
-+											/ mode_lib->vba.LBBitPerPixel[k]
-+											/ (mode_lib->vba.SwathWidthYPerState[i][k]
-+													/ dml_max(
-+															mode_lib->vba.HRatio[k],
-+															1.0)),
-+									1.0))
-+							- (mode_lib->vba.vtaps[k] - 1.0);
-+			mode_lib->vba.EffectiveLBLatencyHidingSourceLinesChroma =
-+					dml_min(
-+							mode_lib->vba.MaxLineBufferLines,
-+							dml_floor(
-+									mode_lib->vba.LineBufferSize
-+											/ mode_lib->vba.LBBitPerPixel[k]
-+											/ (mode_lib->vba.SwathWidthYPerState[i][k]
-+													/ 2.0
-+													/ dml_max(
-+															mode_lib->vba.HRatio[k]
-+																	/ 2.0,
-+															1.0)),
-+									1.0))
-+							- (mode_lib->vba.VTAPsChroma[k] - 1.0);
-+			mode_lib->vba.EffectiveDETLBLinesLuma =
-+					dml_floor(
-+							mode_lib->vba.LinesInDETLuma
-+									+ dml_min(
-+											mode_lib->vba.LinesInDETLuma
-+													* mode_lib->vba.RequiredDISPCLK[i]
-+													* mode_lib->vba.BytePerPixelInDETY[k]
-+													* mode_lib->vba.PSCL_FACTOR[k]
-+													/ mode_lib->vba.ReturnBWPerState[i],
-+											mode_lib->vba.EffectiveLBLatencyHidingSourceLinesLuma),
-+							mode_lib->vba.SwathHeightYPerState[i][k]);
-+			mode_lib->vba.EffectiveDETLBLinesChroma =
-+					dml_floor(
-+							mode_lib->vba.LinesInDETChroma
-+									+ dml_min(
-+											mode_lib->vba.LinesInDETChroma
-+													* mode_lib->vba.RequiredDISPCLK[i]
-+													* mode_lib->vba.BytePerPixelInDETC[k]
-+													* mode_lib->vba.PSCL_FACTOR_CHROMA[k]
-+													/ mode_lib->vba.ReturnBWPerState[i],
-+											mode_lib->vba.EffectiveLBLatencyHidingSourceLinesChroma),
-+							mode_lib->vba.SwathHeightCPerState[i][k]);
-+			if (mode_lib->vba.BytePerPixelInDETC[k] == 0.0) {
-+				mode_lib->vba.UrgentLatencySupportUsPerState[i][k] =
-+						mode_lib->vba.EffectiveDETLBLinesLuma
-+								* (mode_lib->vba.HTotal[k]
-+										/ mode_lib->vba.PixelClock[k])
-+								/ mode_lib->vba.VRatio[k]
-+								- mode_lib->vba.EffectiveDETLBLinesLuma
-+										* mode_lib->vba.SwathWidthYPerState[i][k]
-+										* dml_ceil(
-+												mode_lib->vba.BytePerPixelInDETY[k],
-+												1.0)
-+										/ (mode_lib->vba.ReturnBWPerState[i]
-+												/ mode_lib->vba.NoOfDPP[i][k]);
-+			} else {
-+				mode_lib->vba.UrgentLatencySupportUsPerState[i][k] =
-+						dml_min(
-+								mode_lib->vba.EffectiveDETLBLinesLuma
-+										* (mode_lib->vba.HTotal[k]
-+												/ mode_lib->vba.PixelClock[k])
-+										/ mode_lib->vba.VRatio[k]
-+										- mode_lib->vba.EffectiveDETLBLinesLuma
-+												* mode_lib->vba.SwathWidthYPerState[i][k]
-+												* dml_ceil(
-+														mode_lib->vba.BytePerPixelInDETY[k],
-+														1.0)
-+												/ (mode_lib->vba.ReturnBWPerState[i]
-+														/ mode_lib->vba.NoOfDPP[i][k]),
-+								mode_lib->vba.EffectiveDETLBLinesChroma
-+										* (mode_lib->vba.HTotal[k]
-+												/ mode_lib->vba.PixelClock[k])
-+										/ (mode_lib->vba.VRatio[k]
-+												/ 2.0)
-+										- mode_lib->vba.EffectiveDETLBLinesChroma
-+												* mode_lib->vba.SwathWidthYPerState[i][k]
-+												/ 2.0
-+												* dml_ceil(
-+														mode_lib->vba.BytePerPixelInDETC[k],
-+														2.0)
-+												/ (mode_lib->vba.ReturnBWPerState[i]
-+														/ mode_lib->vba.NoOfDPP[i][k]));
-+			}
-+		}
-+	}
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		mode_lib->vba.UrgentLatencySupport[i] = true;
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			if (mode_lib->vba.UrgentLatencySupportUsPerState[i][k]
-+					< mode_lib->vba.UrgentLatency / 1.0) {
-+				mode_lib->vba.UrgentLatencySupport[i] = false;
-+			}
-+		}
-+	}
-+	/*Prefetch Check*/
-+
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		mode_lib->vba.TotalNumberOfDCCActiveDPP[i] = 0.0;
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			if (mode_lib->vba.DCCEnable[k] == true) {
-+				mode_lib->vba.TotalNumberOfDCCActiveDPP[i] =
-+						mode_lib->vba.TotalNumberOfDCCActiveDPP[i]
-+								+ mode_lib->vba.NoOfDPP[i][k];
-+			}
-+		}
-+	}
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		mode_lib->vba.ProjectedDCFCLKDeepSleep = 8.0;
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			mode_lib->vba.ProjectedDCFCLKDeepSleep = dml_max(
-+					mode_lib->vba.ProjectedDCFCLKDeepSleep,
-+					mode_lib->vba.PixelClock[k] / 16.0);
-+			if (mode_lib->vba.BytePerPixelInDETC[k] == 0.0) {
-+				if (mode_lib->vba.VRatio[k] <= 1.0) {
-+					mode_lib->vba.ProjectedDCFCLKDeepSleep =
-+							dml_max(
-+									mode_lib->vba.ProjectedDCFCLKDeepSleep,
-+									1.1
-+											* dml_ceil(
-+													mode_lib->vba.BytePerPixelInDETY[k],
-+													1.0)
-+											/ 64.0
-+											* mode_lib->vba.HRatio[k]
-+											* mode_lib->vba.PixelClock[k]
-+											/ mode_lib->vba.NoOfDPP[i][k]);
-+				} else {
-+					mode_lib->vba.ProjectedDCFCLKDeepSleep =
-+							dml_max(
-+									mode_lib->vba.ProjectedDCFCLKDeepSleep,
-+									1.1
-+											* dml_ceil(
-+													mode_lib->vba.BytePerPixelInDETY[k],
-+													1.0)
-+											/ 64.0
-+											* mode_lib->vba.PSCL_FACTOR[k]
-+											* mode_lib->vba.RequiredDPPCLK[i][k]);
-+				}
-+			} else {
-+				if (mode_lib->vba.VRatio[k] <= 1.0) {
-+					mode_lib->vba.ProjectedDCFCLKDeepSleep =
-+							dml_max(
-+									mode_lib->vba.ProjectedDCFCLKDeepSleep,
-+									1.1
-+											* dml_ceil(
-+													mode_lib->vba.BytePerPixelInDETY[k],
-+													1.0)
-+											/ 32.0
-+											* mode_lib->vba.HRatio[k]
-+											* mode_lib->vba.PixelClock[k]
-+											/ mode_lib->vba.NoOfDPP[i][k]);
-+				} else {
-+					mode_lib->vba.ProjectedDCFCLKDeepSleep =
-+							dml_max(
-+									mode_lib->vba.ProjectedDCFCLKDeepSleep,
-+									1.1
-+											* dml_ceil(
-+													mode_lib->vba.BytePerPixelInDETY[k],
-+													1.0)
-+											/ 32.0
-+											* mode_lib->vba.PSCL_FACTOR[k]
-+											* mode_lib->vba.RequiredDPPCLK[i][k]);
-+				}
-+				if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0) {
-+					mode_lib->vba.ProjectedDCFCLKDeepSleep =
-+							dml_max(
-+									mode_lib->vba.ProjectedDCFCLKDeepSleep,
-+									1.1
-+											* dml_ceil(
-+													mode_lib->vba.BytePerPixelInDETC[k],
-+													2.0)
-+											/ 32.0
-+											* mode_lib->vba.HRatio[k]
-+											/ 2.0
-+											* mode_lib->vba.PixelClock[k]
-+											/ mode_lib->vba.NoOfDPP[i][k]);
-+				} else {
-+					mode_lib->vba.ProjectedDCFCLKDeepSleep =
-+							dml_max(
-+									mode_lib->vba.ProjectedDCFCLKDeepSleep,
-+									1.1
-+											* dml_ceil(
-+													mode_lib->vba.BytePerPixelInDETC[k],
-+													2.0)
-+											/ 32.0
-+											* mode_lib->vba.PSCL_FACTOR_CHROMA[k]
-+											* mode_lib->vba.RequiredDPPCLK[i][k]);
-+				}
-+			}
-+		}
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			mode_lib->vba.PDEAndMetaPTEBytesPerFrameY = CalculateVMAndRowBytes(
-+					mode_lib,
-+					mode_lib->vba.DCCEnable[k],
-+					mode_lib->vba.Read256BlockHeightY[k],
-+					mode_lib->vba.Read256BlockWidthY[k],
-+					mode_lib->vba.SourcePixelFormat[k],
-+					mode_lib->vba.SurfaceTiling[k],
-+					dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0),
-+					mode_lib->vba.SourceScan[k],
-+					mode_lib->vba.ViewportWidth[k],
-+					mode_lib->vba.ViewportHeight[k],
-+					mode_lib->vba.SwathWidthYPerState[i][k],
-+					mode_lib->vba.VirtualMemoryEnable,
-+					mode_lib->vba.VMMPageSize,
-+					mode_lib->vba.PTEBufferSizeInRequests,
-+					mode_lib->vba.PDEProcessingBufIn64KBReqs,
-+					mode_lib->vba.PitchY[k],
-+					mode_lib->vba.DCCMetaPitchY[k],
-+					&mode_lib->vba.MacroTileWidthY[k],
-+					&mode_lib->vba.MetaRowBytesY,
-+					&mode_lib->vba.DPTEBytesPerRowY,
-+					&mode_lib->vba.PTEBufferSizeNotExceededY[i][k],
-+					&mode_lib->vba.dpte_row_height[k],
-+					&mode_lib->vba.meta_row_height[k]);
-+			mode_lib->vba.PrefetchLinesY[k] = CalculatePrefetchSourceLines(
-+					mode_lib,
-+					mode_lib->vba.VRatio[k],
-+					mode_lib->vba.vtaps[k],
-+					mode_lib->vba.Interlace[k],
-+					mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
-+					mode_lib->vba.SwathHeightYPerState[i][k],
-+					mode_lib->vba.ViewportYStartY[k],
-+					&mode_lib->vba.PrefillY[k],
-+					&mode_lib->vba.MaxNumSwY[k]);
-+			if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
-+					&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
-+					&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
-+					&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
-+					&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) {
-+				mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = CalculateVMAndRowBytes(
-+						mode_lib,
-+						mode_lib->vba.DCCEnable[k],
-+						mode_lib->vba.Read256BlockHeightY[k],
-+						mode_lib->vba.Read256BlockWidthY[k],
-+						mode_lib->vba.SourcePixelFormat[k],
-+						mode_lib->vba.SurfaceTiling[k],
-+						dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0),
-+						mode_lib->vba.SourceScan[k],
-+						mode_lib->vba.ViewportWidth[k] / 2.0,
-+						mode_lib->vba.ViewportHeight[k] / 2.0,
-+						mode_lib->vba.SwathWidthYPerState[i][k] / 2.0,
-+						mode_lib->vba.VirtualMemoryEnable,
-+						mode_lib->vba.VMMPageSize,
-+						mode_lib->vba.PTEBufferSizeInRequests,
-+						mode_lib->vba.PDEProcessingBufIn64KBReqs,
-+						mode_lib->vba.PitchC[k],
-+						0.0,
-+						&mode_lib->vba.MacroTileWidthC[k],
-+						&mode_lib->vba.MetaRowBytesC,
-+						&mode_lib->vba.DPTEBytesPerRowC,
-+						&mode_lib->vba.PTEBufferSizeNotExceededC[i][k],
-+						&mode_lib->vba.dpte_row_height_chroma[k],
-+						&mode_lib->vba.meta_row_height_chroma[k]);
-+				mode_lib->vba.PrefetchLinesC[k] = CalculatePrefetchSourceLines(
-+						mode_lib,
-+						mode_lib->vba.VRatio[k] / 2.0,
-+						mode_lib->vba.VTAPsChroma[k],
-+						mode_lib->vba.Interlace[k],
-+						mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
-+						mode_lib->vba.SwathHeightCPerState[i][k],
-+						mode_lib->vba.ViewportYStartC[k],
-+						&mode_lib->vba.PrefillC[k],
-+						&mode_lib->vba.MaxNumSwC[k]);
-+			} else {
-+				mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = 0.0;
-+				mode_lib->vba.MetaRowBytesC = 0.0;
-+				mode_lib->vba.DPTEBytesPerRowC = 0.0;
-+				mode_lib->vba.PrefetchLinesC[k] = 0.0;
-+				mode_lib->vba.PTEBufferSizeNotExceededC[i][k] = true;
-+			}
-+			mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k] =
-+					mode_lib->vba.PDEAndMetaPTEBytesPerFrameY
-+							+ mode_lib->vba.PDEAndMetaPTEBytesPerFrameC;
-+			mode_lib->vba.MetaRowBytes[k] = mode_lib->vba.MetaRowBytesY
-+					+ mode_lib->vba.MetaRowBytesC;
-+			mode_lib->vba.DPTEBytesPerRow[k] = mode_lib->vba.DPTEBytesPerRowY
-+					+ mode_lib->vba.DPTEBytesPerRowC;
-+		}
-+		mode_lib->vba.ExtraLatency =
-+				mode_lib->vba.UrgentRoundTripAndOutOfOrderLatencyPerState[i]
-+						+ (mode_lib->vba.TotalNumberOfActiveDPP[i]
-+								* mode_lib->vba.PixelChunkSizeInKByte
-+								+ mode_lib->vba.TotalNumberOfDCCActiveDPP[i]
-+										* mode_lib->vba.MetaChunkSize)
-+								* 1024.0
-+								/ mode_lib->vba.ReturnBWPerState[i];
-+		if (mode_lib->vba.VirtualMemoryEnable == true) {
-+			mode_lib->vba.ExtraLatency = mode_lib->vba.ExtraLatency
-+					+ mode_lib->vba.TotalNumberOfActiveDPP[i]
-+							* mode_lib->vba.PTEChunkSize * 1024.0
-+							/ mode_lib->vba.ReturnBWPerState[i];
-+		}
-+		mode_lib->vba.TimeCalc = 24.0 / mode_lib->vba.ProjectedDCFCLKDeepSleep;
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			if (mode_lib->vba.BlendingAndTiming[k] == k) {
-+				if (mode_lib->vba.WritebackEnable[k] == true) {
-+					mode_lib->vba.WritebackDelay[i][k] =
-+							mode_lib->vba.WritebackLatency
-+									+ CalculateWriteBackDelay(
-+											mode_lib->vba.WritebackPixelFormat[k],
-+											mode_lib->vba.WritebackHRatio[k],
-+											mode_lib->vba.WritebackVRatio[k],
-+											mode_lib->vba.WritebackLumaHTaps[k],
-+											mode_lib->vba.WritebackLumaVTaps[k],
-+											mode_lib->vba.WritebackChromaHTaps[k],
-+											mode_lib->vba.WritebackChromaVTaps[k],
-+											mode_lib->vba.WritebackDestinationWidth[k])
-+											/ mode_lib->vba.RequiredDISPCLK[i];
-+				} else {
-+					mode_lib->vba.WritebackDelay[i][k] = 0.0;
-+				}
-+				for (j = 0; j <= mode_lib->vba.NumberOfActivePlanes - 1; j++) {
-+					if (mode_lib->vba.BlendingAndTiming[j] == k
-+							&& mode_lib->vba.WritebackEnable[j]
-+									== true) {
-+						mode_lib->vba.WritebackDelay[i][k] =
-+								dml_max(
-+										mode_lib->vba.WritebackDelay[i][k],
-+										mode_lib->vba.WritebackLatency
-+												+ CalculateWriteBackDelay(
-+														mode_lib->vba.WritebackPixelFormat[j],
-+														mode_lib->vba.WritebackHRatio[j],
-+														mode_lib->vba.WritebackVRatio[j],
-+														mode_lib->vba.WritebackLumaHTaps[j],
-+														mode_lib->vba.WritebackLumaVTaps[j],
-+														mode_lib->vba.WritebackChromaHTaps[j],
-+														mode_lib->vba.WritebackChromaVTaps[j],
-+														mode_lib->vba.WritebackDestinationWidth[j])
-+														/ mode_lib->vba.RequiredDISPCLK[i]);
-+					}
-+				}
-+			}
-+		}
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			for (j = 0; j <= mode_lib->vba.NumberOfActivePlanes - 1; j++) {
-+				if (mode_lib->vba.BlendingAndTiming[k] == j) {
-+					mode_lib->vba.WritebackDelay[i][k] =
-+							mode_lib->vba.WritebackDelay[i][j];
-+				}
-+			}
-+		}
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			mode_lib->vba.MaximumVStartup[k] =
-+					mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
-+							- dml_max(
-+									1.0,
-+									dml_ceil(
-+											mode_lib->vba.WritebackDelay[i][k]
-+													/ (mode_lib->vba.HTotal[k]
-+															/ mode_lib->vba.PixelClock[k]),
-+											1.0));
-+		}
-+		mode_lib->vba.TWait = CalculateTWait(
-+				mode_lib->vba.PrefetchMode,
-+				mode_lib->vba.DRAMClockChangeLatency,
-+				mode_lib->vba.UrgentLatency,
-+				mode_lib->vba.SREnterPlusExitTime);
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			if (mode_lib->vba.XFCEnabled[k] == true) {
-+				mode_lib->vba.XFCRemoteSurfaceFlipDelay =
-+						CalculateRemoteSurfaceFlipDelay(
-+								mode_lib,
-+								mode_lib->vba.VRatio[k],
-+								mode_lib->vba.SwathWidthYPerState[i][k],
-+								dml_ceil(
-+										mode_lib->vba.BytePerPixelInDETY[k],
-+										1.0),
-+								mode_lib->vba.HTotal[k]
-+										/ mode_lib->vba.PixelClock[k],
-+								mode_lib->vba.XFCTSlvVupdateOffset,
-+								mode_lib->vba.XFCTSlvVupdateWidth,
-+								mode_lib->vba.XFCTSlvVreadyOffset,
-+								mode_lib->vba.XFCXBUFLatencyTolerance,
-+								mode_lib->vba.XFCFillBWOverhead,
-+								mode_lib->vba.XFCSlvChunkSize,
-+								mode_lib->vba.XFCBusTransportTime,
-+								mode_lib->vba.TimeCalc,
-+								mode_lib->vba.TWait,
-+								&mode_lib->vba.SrcActiveDrainRate,
-+								&mode_lib->vba.TInitXFill,
-+								&mode_lib->vba.TslvChk);
-+			} else {
-+				mode_lib->vba.XFCRemoteSurfaceFlipDelay = 0.0;
-+			}
-+			mode_lib->vba.IsErrorResult[i][k] =
-+					CalculatePrefetchSchedule(
-+							mode_lib,
-+							mode_lib->vba.RequiredDPPCLK[i][k],
-+							mode_lib->vba.RequiredDISPCLK[i],
-+							mode_lib->vba.PixelClock[k],
-+							mode_lib->vba.ProjectedDCFCLKDeepSleep,
-+							mode_lib->vba.DSCDelayPerState[i][k],
-+							mode_lib->vba.NoOfDPP[i][k],
-+							mode_lib->vba.ScalerEnabled[k],
-+							mode_lib->vba.NumberOfCursors[k],
-+							mode_lib->vba.DPPCLKDelaySubtotal,
-+							mode_lib->vba.DPPCLKDelaySCL,
-+							mode_lib->vba.DPPCLKDelaySCLLBOnly,
-+							mode_lib->vba.DPPCLKDelayCNVCFormater,
-+							mode_lib->vba.DPPCLKDelayCNVCCursor,
-+							mode_lib->vba.DISPCLKDelaySubtotal,
-+							mode_lib->vba.SwathWidthYPerState[i][k]
-+									/ mode_lib->vba.HRatio[k],
-+							mode_lib->vba.OutputFormat[k],
-+							mode_lib->vba.VTotal[k]
-+									- mode_lib->vba.VActive[k],
-+							mode_lib->vba.HTotal[k],
-+							mode_lib->vba.MaxInterDCNTileRepeaters,
-+							mode_lib->vba.MaximumVStartup[k],
-+							mode_lib->vba.MaxPageTableLevels,
-+							mode_lib->vba.VirtualMemoryEnable,
-+							mode_lib->vba.DynamicMetadataEnable[k],
-+							mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
-+							mode_lib->vba.DynamicMetadataTransmittedBytes[k],
-+							mode_lib->vba.DCCEnable[k],
-+							mode_lib->vba.UrgentLatency,
-+							mode_lib->vba.ExtraLatency,
-+							mode_lib->vba.TimeCalc,
-+							mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k],
-+							mode_lib->vba.MetaRowBytes[k],
-+							mode_lib->vba.DPTEBytesPerRow[k],
-+							mode_lib->vba.PrefetchLinesY[k],
-+							mode_lib->vba.SwathWidthYPerState[i][k],
-+							mode_lib->vba.BytePerPixelInDETY[k],
-+							mode_lib->vba.PrefillY[k],
-+							mode_lib->vba.MaxNumSwY[k],
-+							mode_lib->vba.PrefetchLinesC[k],
-+							mode_lib->vba.BytePerPixelInDETC[k],
-+							mode_lib->vba.PrefillC[k],
-+							mode_lib->vba.MaxNumSwC[k],
-+							mode_lib->vba.SwathHeightYPerState[i][k],
-+							mode_lib->vba.SwathHeightCPerState[i][k],
-+							mode_lib->vba.TWait,
-+							mode_lib->vba.XFCEnabled[k],
-+							mode_lib->vba.XFCRemoteSurfaceFlipDelay,
-+							mode_lib->vba.Interlace[k],
-+							mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
-+							mode_lib->vba.DSTXAfterScaler,
-+							mode_lib->vba.DSTYAfterScaler,
-+							&mode_lib->vba.LineTimesForPrefetch[k],
-+							&mode_lib->vba.PrefetchBW[k],
-+							&mode_lib->vba.LinesForMetaPTE[k],
-+							&mode_lib->vba.LinesForMetaAndDPTERow[k],
-+							&mode_lib->vba.VRatioPreY[i][k],
-+							&mode_lib->vba.VRatioPreC[i][k],
-+							&mode_lib->vba.RequiredPrefetchPixelDataBW[i][k],
-+							&mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata,
-+							&mode_lib->vba.Tno_bw[k],
-+							&mode_lib->vba.VUpdateOffsetPix[k],
-+							&mode_lib->vba.VUpdateWidthPix[k],
-+							&mode_lib->vba.VReadyOffsetPix[k]);
-+		}
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			mode_lib->vba.cursor_bw[k] = mode_lib->vba.NumberOfCursors[k]
-+					* mode_lib->vba.CursorWidth[k][0]
-+					* mode_lib->vba.CursorBPP[k][0] / 8.0
-+					/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
-+					* mode_lib->vba.VRatio[k];
-+		}
-+		mode_lib->vba.MaximumReadBandwidthWithPrefetch = 0.0;
-+		mode_lib->vba.prefetch_vm_bw_valid = true;
-+		mode_lib->vba.prefetch_row_bw_valid = true;
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			if (mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k] == 0.0) {
-+				mode_lib->vba.prefetch_vm_bw[k] = 0.0;
-+			} else if (mode_lib->vba.LinesForMetaPTE[k] > 0.0) {
-+				mode_lib->vba.prefetch_vm_bw[k] =
-+						mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k]
-+								/ (mode_lib->vba.LinesForMetaPTE[k]
-+										* mode_lib->vba.HTotal[k]
-+										/ mode_lib->vba.PixelClock[k]);
-+			} else {
-+				mode_lib->vba.prefetch_vm_bw[k] = 0.0;
-+				mode_lib->vba.prefetch_vm_bw_valid = false;
-+			}
-+			if (mode_lib->vba.MetaRowBytes[k] + mode_lib->vba.DPTEBytesPerRow[k]
-+					== 0.0) {
-+				mode_lib->vba.prefetch_row_bw[k] = 0.0;
-+			} else if (mode_lib->vba.LinesForMetaAndDPTERow[k] > 0.0) {
-+				mode_lib->vba.prefetch_row_bw[k] = (mode_lib->vba.MetaRowBytes[k]
-+						+ mode_lib->vba.DPTEBytesPerRow[k])
-+						/ (mode_lib->vba.LinesForMetaAndDPTERow[k]
-+								* mode_lib->vba.HTotal[k]
-+								/ mode_lib->vba.PixelClock[k]);
-+			} else {
-+				mode_lib->vba.prefetch_row_bw[k] = 0.0;
-+				mode_lib->vba.prefetch_row_bw_valid = false;
-+			}
-+			mode_lib->vba.MaximumReadBandwidthWithPrefetch =
-+					mode_lib->vba.MaximumReadBandwidthWithPrefetch
-+							+ mode_lib->vba.cursor_bw[k]
-+							+ dml_max4(
-+									mode_lib->vba.prefetch_vm_bw[k],
-+									mode_lib->vba.prefetch_row_bw[k],
-+									mode_lib->vba.ReadBandwidth[k],
-+									mode_lib->vba.RequiredPrefetchPixelDataBW[i][k]);
-+		}
-+		mode_lib->vba.PrefetchSupported[i] = true;
-+		if (mode_lib->vba.MaximumReadBandwidthWithPrefetch
-+				> mode_lib->vba.ReturnBWPerState[i]
-+				|| mode_lib->vba.prefetch_vm_bw_valid == false
-+				|| mode_lib->vba.prefetch_row_bw_valid == false) {
-+			mode_lib->vba.PrefetchSupported[i] = false;
-+		}
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			if (mode_lib->vba.LineTimesForPrefetch[k] < 2.0
-+					|| mode_lib->vba.LinesForMetaPTE[k] >= 8.0
-+					|| mode_lib->vba.LinesForMetaAndDPTERow[k] >= 16.0
-+					|| mode_lib->vba.IsErrorResult[i][k] == true) {
-+				mode_lib->vba.PrefetchSupported[i] = false;
-+			}
-+		}
-+		mode_lib->vba.VRatioInPrefetchSupported[i] = true;
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			if (mode_lib->vba.VRatioPreY[i][k] > 4.0
-+					|| mode_lib->vba.VRatioPreC[i][k] > 4.0
-+					|| mode_lib->vba.IsErrorResult[i][k] == true) {
-+				mode_lib->vba.VRatioInPrefetchSupported[i] = false;
-+			}
-+		}
-+		if (mode_lib->vba.PrefetchSupported[i] == true
-+				&& mode_lib->vba.VRatioInPrefetchSupported[i] == true) {
-+			mode_lib->vba.BandwidthAvailableForImmediateFlip =
-+					mode_lib->vba.ReturnBWPerState[i];
-+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+				mode_lib->vba.BandwidthAvailableForImmediateFlip =
-+						mode_lib->vba.BandwidthAvailableForImmediateFlip
-+								- mode_lib->vba.cursor_bw[k]
-+								- dml_max(
-+										mode_lib->vba.ReadBandwidth[k],
-+										mode_lib->vba.PrefetchBW[k]);
-+			}
-+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+				mode_lib->vba.ImmediateFlipBytes[k] = 0.0;
-+				if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
-+						&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
-+					mode_lib->vba.ImmediateFlipBytes[k] =
-+							mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k]
-+									+ mode_lib->vba.MetaRowBytes[k]
-+									+ mode_lib->vba.DPTEBytesPerRow[k];
-+				}
-+			}
-+			mode_lib->vba.TotImmediateFlipBytes = 0.0;
-+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+				if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
-+						&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
-+					mode_lib->vba.TotImmediateFlipBytes =
-+							mode_lib->vba.TotImmediateFlipBytes
-+									+ mode_lib->vba.ImmediateFlipBytes[k];
-+				}
-+			}
-+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+				CalculateFlipSchedule(
-+						mode_lib,
-+						mode_lib->vba.ExtraLatency,
-+						mode_lib->vba.UrgentLatency,
-+						mode_lib->vba.MaxPageTableLevels,
-+						mode_lib->vba.VirtualMemoryEnable,
-+						mode_lib->vba.BandwidthAvailableForImmediateFlip,
-+						mode_lib->vba.TotImmediateFlipBytes,
-+						mode_lib->vba.SourcePixelFormat[k],
-+						mode_lib->vba.ImmediateFlipBytes[k],
-+						mode_lib->vba.HTotal[k]
-+								/ mode_lib->vba.PixelClock[k],
-+						mode_lib->vba.VRatio[k],
-+						mode_lib->vba.Tno_bw[k],
-+						mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k],
-+						mode_lib->vba.MetaRowBytes[k],
-+						mode_lib->vba.DPTEBytesPerRow[k],
-+						mode_lib->vba.DCCEnable[k],
-+						mode_lib->vba.dpte_row_height[k],
-+						mode_lib->vba.meta_row_height[k],
-+						mode_lib->vba.qual_row_bw[k],
-+						&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
-+						&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
-+						&mode_lib->vba.final_flip_bw[k],
-+						&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
-+			}
-+			mode_lib->vba.total_dcn_read_bw_with_flip = 0.0;
-+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+				mode_lib->vba.total_dcn_read_bw_with_flip =
-+						mode_lib->vba.total_dcn_read_bw_with_flip
-+								+ mode_lib->vba.cursor_bw[k]
-+								+ dml_max3(
-+										mode_lib->vba.prefetch_vm_bw[k],
-+										mode_lib->vba.prefetch_row_bw[k],
-+										mode_lib->vba.final_flip_bw[k]
-+												+ dml_max(
-+														mode_lib->vba.ReadBandwidth[k],
-+														mode_lib->vba.RequiredPrefetchPixelDataBW[i][k]));
-+			}
-+			mode_lib->vba.ImmediateFlipSupportedForState[i] = true;
-+			if (mode_lib->vba.total_dcn_read_bw_with_flip
-+					> mode_lib->vba.ReturnBWPerState[i]) {
-+				mode_lib->vba.ImmediateFlipSupportedForState[i] = false;
-+			}
-+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+				if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
-+					mode_lib->vba.ImmediateFlipSupportedForState[i] = false;
-+				}
-+			}
-+		} else {
-+			mode_lib->vba.ImmediateFlipSupportedForState[i] = false;
-+		}
-+	}
-+	/*PTE Buffer Size Check*/
-+
-+	for (i = 0; i <= DC__VOLTAGE_STATES; i++) {
-+		mode_lib->vba.PTEBufferSizeNotExceeded[i] = true;
-+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+			if (mode_lib->vba.PTEBufferSizeNotExceededY[i][k] == false
-+					|| mode_lib->vba.PTEBufferSizeNotExceededC[i][k] == false) {
-+				mode_lib->vba.PTEBufferSizeNotExceeded[i] = false;
-+			}
-+		}
-+	}
-+	/*Cursor Support Check*/
-+
-+	mode_lib->vba.CursorSupport = true;
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if (mode_lib->vba.CursorWidth[k][0] > 0.0) {
-+			if (dml_floor(
-+					dml_floor(
-+							mode_lib->vba.CursorBufferSize
-+									- mode_lib->vba.CursorChunkSize,
-+							mode_lib->vba.CursorChunkSize) * 1024.0
-+							/ (mode_lib->vba.CursorWidth[k][0]
-+									* mode_lib->vba.CursorBPP[k][0]
-+									/ 8.0),
-+					1.0)
-+					* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
-+					/ mode_lib->vba.VRatio[k] < mode_lib->vba.UrgentLatency
-+					|| (mode_lib->vba.CursorBPP[k][0] == 64.0
-+							&& mode_lib->vba.Cursor64BppSupport == false)) {
-+				mode_lib->vba.CursorSupport = false;
-+			}
-+		}
-+	}
-+	/*Valid Pitch Check*/
-+
-+	mode_lib->vba.PitchSupport = true;
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		mode_lib->vba.AlignedYPitch[k] = dml_ceil(
-+				dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]),
-+				mode_lib->vba.MacroTileWidthY[k]);
-+		if (mode_lib->vba.AlignedYPitch[k] > mode_lib->vba.PitchY[k]) {
-+			mode_lib->vba.PitchSupport = false;
-+		}
-+		if (mode_lib->vba.DCCEnable[k] == true) {
-+			mode_lib->vba.AlignedDCCMetaPitch[k] = dml_ceil(
-+					dml_max(
-+							mode_lib->vba.DCCMetaPitchY[k],
-+							mode_lib->vba.ViewportWidth[k]),
-+					64.0 * mode_lib->vba.Read256BlockWidthY[k]);
-+		} else {
-+			mode_lib->vba.AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k];
-+		}
-+		if (mode_lib->vba.AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) {
-+			mode_lib->vba.PitchSupport = false;
-+		}
-+		if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
-+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
-+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
-+				&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
-+				&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
-+			mode_lib->vba.AlignedCPitch[k] = dml_ceil(
-+					dml_max(
-+							mode_lib->vba.PitchC[k],
-+							mode_lib->vba.ViewportWidth[k] / 2.0),
-+					mode_lib->vba.MacroTileWidthC[k]);
-+		} else {
-+			mode_lib->vba.AlignedCPitch[k] = mode_lib->vba.PitchC[k];
-+		}
-+		if (mode_lib->vba.AlignedCPitch[k] > mode_lib->vba.PitchC[k]) {
-+			mode_lib->vba.PitchSupport = false;
-+		}
-+	}
-+	/*Mode Support, Voltage State and SOC Configuration*/
-+
-+	for (i = DC__VOLTAGE_STATES; i >= 0; i--) {
-+		if (mode_lib->vba.ScaleRatioAndTapsSupport == true
-+				&& mode_lib->vba.SourceFormatPixelAndScanSupport == true
-+				&& mode_lib->vba.ViewportSizeSupport[i] == true
-+				&& mode_lib->vba.BandwidthSupport[i] == true
-+				&& mode_lib->vba.DIOSupport[i] == true
-+				&& mode_lib->vba.NotEnoughDSCUnits[i] == false
-+				&& mode_lib->vba.DSCCLKRequiredMoreThanSupported[i] == false
-+				&& mode_lib->vba.UrgentLatencySupport[i] == true
-+				&& mode_lib->vba.ROBSupport[i] == true
-+				&& mode_lib->vba.DISPCLK_DPPCLK_Support[i] == true
-+				&& mode_lib->vba.TotalAvailablePipesSupport[i] == true
-+				&& mode_lib->vba.NumberOfOTGSupport == true
-+				&& mode_lib->vba.WritebackModeSupport == true
-+				&& mode_lib->vba.WritebackLatencySupport == true
-+				&& mode_lib->vba.WritebackScaleRatioAndTapsSupport == true
-+				&& mode_lib->vba.CursorSupport == true
-+				&& mode_lib->vba.PitchSupport == true
-+				&& mode_lib->vba.PrefetchSupported[i] == true
-+				&& mode_lib->vba.VRatioInPrefetchSupported[i] == true
-+				&& mode_lib->vba.PTEBufferSizeNotExceeded[i] == true
-+				&& mode_lib->vba.NonsupportedDSCInputBPC == false) {
-+			mode_lib->vba.ModeSupport[i] = true;
-+		} else {
-+			mode_lib->vba.ModeSupport[i] = false;
-+		}
-+	}
-+	for (i = DC__VOLTAGE_STATES; i >= 0; i--) {
-+		if (i == DC__VOLTAGE_STATES || mode_lib->vba.ModeSupport[i] == true) {
-+			mode_lib->vba.VoltageLevel = i;
-+		}
-+	}
-+	mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKPerState[mode_lib->vba.VoltageLevel];
-+	mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel];
-+	mode_lib->vba.FabricClock = mode_lib->vba.FabricClockPerState[mode_lib->vba.VoltageLevel];
-+	mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel];
-+	mode_lib->vba.FabricAndDRAMBandwidth =
-+			mode_lib->vba.FabricAndDRAMBandwidthPerState[mode_lib->vba.VoltageLevel];
-+	mode_lib->vba.ImmediateFlipSupport =
-+			mode_lib->vba.ImmediateFlipSupportedForState[mode_lib->vba.VoltageLevel];
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		mode_lib->vba.DPPPerPlane[k] = mode_lib->vba.NoOfDPP[mode_lib->vba.VoltageLevel][k];
-+	}
-+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
-+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
-+			mode_lib->vba.ODMCombineEnabled[k] =
-+					mode_lib->vba.ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
-+		} else {
-+			mode_lib->vba.ODMCombineEnabled[k] = 0;
-+		}
-+		mode_lib->vba.DSCEnabled[k] =
-+				mode_lib->vba.RequiresDSC[mode_lib->vba.VoltageLevel][k];
-+		mode_lib->vba.OutputBpp[k] =
-+				mode_lib->vba.OutputBppPerState[mode_lib->vba.VoltageLevel][k];
-+	}
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h.0130~	2017-12-14 06:39:58.427903576 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h	2017-12-14 06:39:58.427903576 +0100
-@@ -0,0 +1,598 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DML2_DISPLAY_MODE_VBA_H__
-+#define __DML2_DISPLAY_MODE_VBA_H__
-+
-+#include "dml_common_defs.h"
-+
-+struct display_mode_lib;
-+
-+void set_prefetch_mode(struct display_mode_lib *mode_lib,
-+		bool cstate_en,
-+		bool pstate_en,
-+		bool ignore_viewport_pos,
-+		bool immediate_flip_support);
-+
-+#define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
-+
-+dml_get_attr_decl(clk_dcf_deepsleep);
-+dml_get_attr_decl(wm_urgent);
-+dml_get_attr_decl(wm_memory_trip);
-+dml_get_attr_decl(wm_writeback_urgent);
-+dml_get_attr_decl(wm_stutter_exit);
-+dml_get_attr_decl(wm_stutter_enter_exit);
-+dml_get_attr_decl(wm_dram_clock_change);
-+dml_get_attr_decl(wm_writeback_dram_clock_change);
-+dml_get_attr_decl(wm_xfc_underflow);
-+dml_get_attr_decl(stutter_efficiency_no_vblank);
-+dml_get_attr_decl(stutter_efficiency);
-+dml_get_attr_decl(urgent_latency);
-+dml_get_attr_decl(urgent_extra_latency);
-+dml_get_attr_decl(nonurgent_latency);
-+dml_get_attr_decl(dram_clock_change_latency);
-+dml_get_attr_decl(dispclk_calculated);
-+dml_get_attr_decl(total_data_read_bw);
-+dml_get_attr_decl(return_bw);
-+dml_get_attr_decl(tcalc);
-+
-+#define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
-+
-+dml_get_pipe_attr_decl(dsc_delay);
-+dml_get_pipe_attr_decl(dppclk_calculated);
-+dml_get_pipe_attr_decl(dscclk_calculated);
-+dml_get_pipe_attr_decl(min_ttu_vblank);
-+dml_get_pipe_attr_decl(vratio_prefetch_l);
-+dml_get_pipe_attr_decl(vratio_prefetch_c);
-+dml_get_pipe_attr_decl(dst_x_after_scaler);
-+dml_get_pipe_attr_decl(dst_y_after_scaler);
-+dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
-+dml_get_pipe_attr_decl(dst_y_per_row_vblank);
-+dml_get_pipe_attr_decl(dst_y_prefetch);
-+dml_get_pipe_attr_decl(dst_y_per_vm_flip);
-+dml_get_pipe_attr_decl(dst_y_per_row_flip);
-+dml_get_pipe_attr_decl(xfc_transfer_delay);
-+dml_get_pipe_attr_decl(xfc_precharge_delay);
-+dml_get_pipe_attr_decl(xfc_remote_surface_flip_latency);
-+dml_get_pipe_attr_decl(xfc_prefetch_margin);
-+
-+unsigned int get_vstartup_calculated(
-+		struct display_mode_lib *mode_lib,
-+		const display_e2e_pipe_params_st *pipes,
-+		unsigned int num_pipes,
-+		unsigned int which_pipe);
-+
-+double get_total_immediate_flip_bytes(
-+		struct display_mode_lib *mode_lib,
-+		const display_e2e_pipe_params_st *pipes,
-+		unsigned int num_pipes);
-+double get_total_immediate_flip_bw(
-+		struct display_mode_lib *mode_lib,
-+		const display_e2e_pipe_params_st *pipes,
-+		unsigned int num_pipes);
-+double get_total_prefetch_bw(
-+		struct display_mode_lib *mode_lib,
-+		const display_e2e_pipe_params_st *pipes,
-+		unsigned int num_pipes);
-+
-+unsigned int dml_get_voltage_level(
-+		struct display_mode_lib *mode_lib,
-+		const display_e2e_pipe_params_st *pipes,
-+		unsigned int num_pipes);
-+
-+bool Calculate256BBlockSizes(
-+		enum source_format_class SourcePixelFormat,
-+		enum dm_swizzle_mode SurfaceTiling,
-+		unsigned int BytePerPixelY,
-+		unsigned int BytePerPixelC,
-+		unsigned int *BlockHeight256BytesY,
-+		unsigned int *BlockHeight256BytesC,
-+		unsigned int *BlockWidth256BytesY,
-+		unsigned int *BlockWidth256BytesC);
-+
-+
-+struct vba_vars_st {
-+	ip_params_st	ip;
-+	soc_bounding_box_st	soc;
-+
-+	unsigned int MaximumMaxVStartupLines;
-+	double cursor_bw[DC__NUM_DPP__MAX];
-+	double meta_row_bw[DC__NUM_DPP__MAX];
-+	double dpte_row_bw[DC__NUM_DPP__MAX];
-+	double qual_row_bw[DC__NUM_DPP__MAX];
-+	double WritebackDISPCLK;
-+	double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
-+	double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
-+	double DPPCLKUsingSingleDPPLuma;
-+	double DPPCLKUsingSingleDPPChroma;
-+	double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
-+	double DISPCLKWithRamping;
-+	double DISPCLKWithoutRamping;
-+	double GlobalDPPCLK;
-+	double DISPCLKWithRampingRoundedToDFSGranularity;
-+	double DISPCLKWithoutRampingRoundedToDFSGranularity;
-+	double MaxDispclkRoundedToDFSGranularity;
-+	bool DCCEnabledAnyPlane;
-+	double ReturnBandwidthToDCN;
-+	unsigned int SwathWidthY[DC__NUM_DPP__MAX];
-+	unsigned int SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
-+	double BytePerPixelDETY[DC__NUM_DPP__MAX];
-+	double BytePerPixelDETC[DC__NUM_DPP__MAX];
-+	double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
-+	double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
-+	unsigned int TotalActiveDPP;
-+	unsigned int TotalDCCActiveDPP;
-+	double UrgentRoundTripAndOutOfOrderLatency;
-+	double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX];                     // WM
-+	double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX];                     // WM
-+	double LinesInDETY[DC__NUM_DPP__MAX];                     // WM
-+	double LinesInDETC[DC__NUM_DPP__MAX];                     // WM
-+	unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];                     // WM
-+	unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];                     // WM
-+	double FullDETBufferingTimeY[DC__NUM_DPP__MAX];                     // WM
-+	double FullDETBufferingTimeC[DC__NUM_DPP__MAX];                     // WM
-+	double MinFullDETBufferingTime;
-+	double FrameTimeForMinFullDETBufferingTime;
-+	double AverageReadBandwidthGBytePerSecond;
-+	double PartOfBurstThatFitsInROB;
-+	double StutterBurstTime;
-+	//unsigned int     NextPrefetchMode;
-+	double VBlankTime;
-+	double SmallestVBlank;
-+	double DCFCLKDeepSleepPerPlane;
-+	double EffectiveDETPlusLBLinesLuma;
-+	double EffectiveDETPlusLBLinesChroma;
-+	double UrgentLatencySupportUsLuma;
-+	double UrgentLatencySupportUsChroma;
-+	double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
-+	unsigned int DSCFormatFactor;
-+	unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
-+	unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
-+	unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
-+	unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
-+	double VInitPreFillY[DC__NUM_DPP__MAX];
-+	double VInitPreFillC[DC__NUM_DPP__MAX];
-+	unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
-+	unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
-+	double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
-+	double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
-+	double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
-+	double MetaRowByte[DC__NUM_DPP__MAX];
-+	unsigned int dpte_row_height[DC__NUM_DPP__MAX];
-+	unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
-+	unsigned int meta_row_height[DC__NUM_DPP__MAX];
-+	unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
-+
-+	unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
-+	unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
-+	unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
-+	double WritebackDelay[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	bool PrefetchModeSupported;
-+	bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
-+	bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
-+	double RequiredPrefetchPixDataBW[DC__NUM_DPP__MAX];
-+	double XFCRemoteSurfaceFlipDelay;
-+	double TInitXFill;
-+	double TslvChk;
-+	double SrcActiveDrainRate;
-+	double Tno_bw[DC__NUM_DPP__MAX];
-+	bool ImmediateFlipSupported;
-+
-+	double prefetch_vm_bw[DC__NUM_DPP__MAX];
-+	double prefetch_row_bw[DC__NUM_DPP__MAX];
-+	bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
-+	unsigned int VStartupLines;
-+	double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
-+	double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
-+	unsigned int ActiveDPPs;
-+	unsigned int LBLatencyHidingSourceLinesY;
-+	unsigned int LBLatencyHidingSourceLinesC;
-+	double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
-+	double MinActiveDRAMClockChangeMargin;
-+	double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
-+	double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
-+	double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
-+	double InitFillLevel;
-+	double FinalFillMargin;
-+	double FinalFillLevel;
-+	double RemainingFillLevel;
-+	double TFinalxFill;
-+
-+
-+	//
-+	// SOC Bounding Box Parameters
-+	//
-+	double SRExitTime;
-+	double SREnterPlusExitTime;
-+	double UrgentLatency;
-+	double WritebackLatency;
-+	double PercentOfIdealDRAMAndFabricBWReceivedAfterUrgLatency;
-+	double NumberOfChannels;
-+	double DRAMChannelWidth;
-+	double FabricDatapathToDCNDataReturn;
-+	double ReturnBusWidth;
-+	double Downspreading;
-+	double DISPCLKDPPCLKDSCCLKDownSpreading;
-+	double DISPCLKDPPCLKVCOSpeed;
-+	double RoundTripPingLatencyCycles;
-+	double UrgentOutOfOrderReturnPerChannel;
-+	unsigned int VMMPageSize;
-+	double DRAMClockChangeLatency;
-+	double XFCBusTransportTime;
-+	double XFCXBUFLatencyTolerance;
-+
-+	//
-+	// IP Parameters
-+	//
-+	unsigned int ROBBufferSizeInKByte;
-+	double DETBufferSizeInKByte;
-+	unsigned int DPPOutputBufferPixels;
-+	unsigned int OPPOutputBufferLines;
-+	unsigned int PixelChunkSizeInKByte;
-+	double ReturnBW;
-+	bool VirtualMemoryEnable;
-+	unsigned int MaxPageTableLevels;
-+	unsigned int OverridePageTableLevels;
-+	unsigned int PTEChunkSize;
-+	unsigned int MetaChunkSize;
-+	unsigned int WritebackChunkSize;
-+	bool ODMCapability;
-+	unsigned int NumberOfDSC;
-+	unsigned int LineBufferSize;
-+	unsigned int MaxLineBufferLines;
-+	unsigned int WritebackInterfaceLumaBufferSize;
-+	unsigned int WritebackInterfaceChromaBufferSize;
-+	unsigned int WritebackChromaLineBufferWidth;
-+	double MaxDCHUBToPSCLThroughput;
-+	double MaxPSCLToLBThroughput;
-+	unsigned int PTEBufferSizeInRequests;
-+	double DISPCLKRampingMargin;
-+	unsigned int MaxInterDCNTileRepeaters;
-+	bool XFCSupported;
-+	double XFCSlvChunkSize;
-+	double XFCFillBWOverhead;
-+	double XFCFillConstant;
-+	double XFCTSlvVupdateOffset;
-+	double XFCTSlvVupdateWidth;
-+	double XFCTSlvVreadyOffset;
-+	double DPPCLKDelaySubtotal;
-+	double DPPCLKDelaySCL;
-+	double DPPCLKDelaySCLLBOnly;
-+	double DPPCLKDelayCNVCFormater;
-+	double DPPCLKDelayCNVCCursor;
-+	double DISPCLKDelaySubtotal;
-+	bool ProgressiveToInterlaceUnitInOPP;
-+	unsigned int PDEProcessingBufIn64KBReqs;
-+
-+	// Pipe/Plane Parameters
-+	int VoltageLevel;
-+	double FabricAndDRAMBandwidth;
-+	double FabricClock;
-+	double DRAMSpeed;
-+	double DISPCLK;
-+	double SOCCLK;
-+	double DCFCLK;
-+
-+	unsigned int NumberOfActivePlanes;
-+	unsigned int ViewportWidth[DC__NUM_DPP__MAX];
-+	unsigned int ViewportHeight[DC__NUM_DPP__MAX];
-+	unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
-+	unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
-+	unsigned int PitchY[DC__NUM_DPP__MAX];
-+	unsigned int PitchC[DC__NUM_DPP__MAX];
-+	double HRatio[DC__NUM_DPP__MAX];
-+	double VRatio[DC__NUM_DPP__MAX];
-+	unsigned int htaps[DC__NUM_DPP__MAX];
-+	unsigned int vtaps[DC__NUM_DPP__MAX];
-+	unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
-+	unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
-+	unsigned int HTotal[DC__NUM_DPP__MAX];
-+	unsigned int VTotal[DC__NUM_DPP__MAX];
-+	unsigned int DPPPerPlane[DC__NUM_DPP__MAX];
-+	double PixelClock[DC__NUM_DPP__MAX];
-+	double PixelClockBackEnd[DC__NUM_DPP__MAX];
-+	double DPPCLK[DC__NUM_DPP__MAX];
-+	bool DCCEnable[DC__NUM_DPP__MAX];
-+	unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
-+	enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
-+	enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
-+	bool WritebackEnable[DC__NUM_DPP__MAX];
-+	double WritebackDestinationWidth[DC__NUM_DPP__MAX];
-+	double WritebackDestinationHeight[DC__NUM_DPP__MAX];
-+	double WritebackSourceHeight[DC__NUM_DPP__MAX];
-+	enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
-+	unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
-+	unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
-+	unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
-+	unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
-+	double WritebackHRatio[DC__NUM_DPP__MAX];
-+	double WritebackVRatio[DC__NUM_DPP__MAX];
-+	unsigned int HActive[DC__NUM_DPP__MAX];
-+	unsigned int VActive[DC__NUM_DPP__MAX];
-+	bool Interlace[DC__NUM_DPP__MAX];
-+	enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
-+	unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
-+	bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
-+	unsigned int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
-+	unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
-+	double DCCRate[DC__NUM_DPP__MAX];
-+	bool ODMCombineEnabled[DC__NUM_DPP__MAX];
-+	double OutputBpp[DC__NUM_DPP__MAX];
-+	unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
-+	bool DSCEnabled[DC__NUM_DPP__MAX];
-+	unsigned int DSCDelay[DC__NUM_DPP__MAX];
-+	unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
-+	enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
-+	enum output_encoder_class Output[DC__NUM_DPP__MAX];
-+	unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
-+	bool SynchronizedVBlank;
-+	unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
-+	unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
-+	unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
-+	bool XFCEnabled[DC__NUM_DPP__MAX];
-+	bool ScalerEnabled[DC__NUM_DPP__MAX];
-+
-+	// Intermediates/Informational
-+	bool ImmediateFlipSupport;
-+	unsigned int SwathHeightY[DC__NUM_DPP__MAX];
-+	unsigned int SwathHeightC[DC__NUM_DPP__MAX];
-+	unsigned int DETBufferSizeY[DC__NUM_DPP__MAX];
-+	unsigned int DETBufferSizeC[DC__NUM_DPP__MAX];
-+	unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
-+	double LastPixelOfLineExtraWatermark;
-+	double TotalDataReadBandwidth;
-+	unsigned int TotalActiveWriteback;
-+	unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
-+	unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
-+	double BandwidthAvailableForImmediateFlip;
-+	unsigned int PrefetchMode;
-+	bool IgnoreViewportPositioning;
-+	double PrefetchBandwidth[DC__NUM_DPP__MAX];
-+	bool ErrorResult[DC__NUM_DPP__MAX];
-+	double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
-+
-+	//
-+	// Calculated dml_ml->vba.Outputs
-+	//
-+	double DCFClkDeepSleep;
-+	double UrgentWatermark;
-+	double UrgentExtraLatency;
-+	double MemoryTripWatermark;
-+	double WritebackUrgentWatermark;
-+	double StutterExitWatermark;
-+	double StutterEnterPlusExitWatermark;
-+	double DRAMClockChangeWatermark;
-+	double WritebackDRAMClockChangeWatermark;
-+	double StutterEfficiency;
-+	double StutterEfficiencyNotIncludingVBlank;
-+	double MinUrgentLatencySupportUs;
-+	double NonUrgentLatencyTolerance;
-+	double MinActiveDRAMClockChangeLatencySupported;
-+	enum clock_change_support DRAMClockChangeSupport;
-+
-+	// These are the clocks calcuated by the library but they are not actually
-+	// used explicitly. They are fetched by tests and then possibly used. The
-+	// ultimate values to use are the ones specified by the parameters to DML
-+	double DISPCLK_calculated;
-+	double DSCCLK_calculated[DC__NUM_DPP__MAX];
-+	double DPPCLK_calculated[DC__NUM_DPP__MAX];
-+
-+	unsigned int VStartup[DC__NUM_DPP__MAX];
-+	unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
-+	unsigned int VUpdateWidthPix[DC__NUM_DPP__MAX];
-+	unsigned int VReadyOffsetPix[DC__NUM_DPP__MAX];
-+	unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
-+
-+	double ImmediateFlipBW;
-+	unsigned int TotImmediateFlipBytes;
-+	double TCalc;
-+	double MinTTUVBlank[DC__NUM_DPP__MAX];
-+	double VRatioPrefetchY[DC__NUM_DPP__MAX];
-+	double VRatioPrefetchC[DC__NUM_DPP__MAX];
-+	double DSTXAfterScaler[DC__NUM_DPP__MAX];
-+	double DSTYAfterScaler[DC__NUM_DPP__MAX];
-+
-+	double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
-+	double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
-+	double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
-+	double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
-+	double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
-+
-+	double XFCTransferDelay[DC__NUM_DPP__MAX];
-+	double XFCPrechargeDelay[DC__NUM_DPP__MAX];
-+	double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
-+	double XFCPrefetchMargin[DC__NUM_DPP__MAX];
-+
-+	display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
-+	unsigned int cache_num_pipes;
-+	unsigned int pipe_plane[DC__NUM_DPP__MAX];
-+
-+	/* vba mode support */
-+	/*inputs*/
-+	bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
-+	double MaxHSCLRatio;
-+	double MaxVSCLRatio;
-+	unsigned int  MaxNumWriteback;
-+	bool WritebackLumaAndChromaScalingSupported;
-+	bool Cursor64BppSupport;
-+	double DCFCLKPerState[DC__VOLTAGE_STATES + 1];
-+	double FabricClockPerState[DC__VOLTAGE_STATES + 1];
-+	double SOCCLKPerState[DC__VOLTAGE_STATES + 1];
-+	double PHYCLKPerState[DC__VOLTAGE_STATES + 1];
-+	double MaxDppclk[DC__VOLTAGE_STATES + 1];
-+	double MaxDSCCLK[DC__VOLTAGE_STATES + 1];
-+	double DRAMSpeedPerState[DC__VOLTAGE_STATES + 1];
-+	double MaxDispclk[DC__VOLTAGE_STATES + 1];
-+
-+	/*outputs*/
-+	bool ScaleRatioAndTapsSupport;
-+	bool SourceFormatPixelAndScanSupport;
-+	unsigned int SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
-+	double BytePerPixelInDETY[DC__NUM_DPP__MAX];
-+	double BytePerPixelInDETC[DC__NUM_DPP__MAX];
-+	double TotalReadBandwidthConsumedGBytePerSecond;
-+	double ReadBandwidth[DC__NUM_DPP__MAX];
-+	double TotalWriteBandwidthConsumedGBytePerSecond;
-+	double WriteBandwidth[DC__NUM_DPP__MAX];
-+	double TotalBandwidthConsumedGBytePerSecond;
-+	bool DCCEnabledInAnyPlane;
-+	bool WritebackLatencySupport;
-+	bool WritebackModeSupport;
-+	bool Writeback10bpc420Supported;
-+	bool BandwidthSupport[DC__VOLTAGE_STATES + 1];
-+	unsigned int TotalNumberOfActiveWriteback;
-+	double CriticalPoint;
-+	double ReturnBWToDCNPerState;
-+	double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES + 1];
-+	double ReturnBWPerState[DC__VOLTAGE_STATES + 1];
-+	double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES + 1];
-+	bool ODMCombineEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	bool PrefetchSupported[DC__VOLTAGE_STATES + 1];
-+	bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES + 1];
-+	bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES + 1];
-+	bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES + 1];
-+	bool UrgentLatencySupport[DC__VOLTAGE_STATES + 1];
-+	bool ModeSupport[DC__VOLTAGE_STATES + 1];
-+	bool DIOSupport[DC__VOLTAGE_STATES + 1];
-+	bool NotEnoughDSCUnits[DC__VOLTAGE_STATES + 1];
-+	bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
-+	bool ROBSupport[DC__VOLTAGE_STATES + 1];
-+	bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES + 1];
-+	bool RequiresDSC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	bool IsErrorResult[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	bool ViewportSizeSupport[DC__VOLTAGE_STATES + 1];
-+	bool prefetch_vm_bw_valid;
-+	bool prefetch_row_bw_valid;
-+	bool NumberOfOTGSupport;
-+	bool NonsupportedDSCInputBPC;
-+	bool WritebackScaleRatioAndTapsSupport;
-+	bool CursorSupport;
-+	bool PitchSupport;
-+
-+	double WritebackLineBufferLumaBufferSize;
-+	double WritebackLineBufferChromaBufferSize;
-+	double WritebackMinHSCLRatio;
-+	double WritebackMinVSCLRatio;
-+	double WritebackMaxHSCLRatio;
-+	double WritebackMaxVSCLRatio;
-+	double WritebackMaxHSCLTaps;
-+	double WritebackMaxVSCLTaps;
-+	unsigned int MaxNumDPP;
-+	unsigned int MaxNumOTG;
-+	double CursorBufferSize;
-+	double CursorChunkSize;
-+	unsigned int Mode;
-+	unsigned int NoOfDPP[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	double OutputLinkDPLanes[DC__NUM_DPP__MAX];
-+	double SwathWidthYPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	double SwathHeightYPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	double SwathHeightCPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	double VRatioPreY[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	double VRatioPreC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	double RequiredPrefetchPixelDataBW[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	double RequiredDPPCLK[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	double RequiredDISPCLK[DC__VOLTAGE_STATES + 1];
-+	double TotalNumberOfActiveDPP[DC__VOLTAGE_STATES + 1];
-+	double TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES + 1];
-+	double PrefetchBW[DC__NUM_DPP__MAX];
-+	double PDEAndMetaPTEBytesPerFrame[DC__NUM_DPP__MAX];
-+	double MetaRowBytes[DC__NUM_DPP__MAX];
-+	double DPTEBytesPerRow[DC__NUM_DPP__MAX];
-+	double PrefetchLinesY[DC__NUM_DPP__MAX];
-+	double PrefetchLinesC[DC__NUM_DPP__MAX];
-+	unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
-+	unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
-+	double PrefillY[DC__NUM_DPP__MAX];
-+	double PrefillC[DC__NUM_DPP__MAX];
-+	double LineTimesForPrefetch[DC__NUM_DPP__MAX];
-+	double LinesForMetaPTE[DC__NUM_DPP__MAX];
-+	double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
-+	double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
-+	double RequiresFEC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	unsigned int OutputBppPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	double DSCDelayPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-+	unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
-+	unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
-+	unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
-+	unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
-+	unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
-+	double MaxSwathHeightY[DC__NUM_DPP__MAX];
-+	double MaxSwathHeightC[DC__NUM_DPP__MAX];
-+	double MinSwathHeightY[DC__NUM_DPP__MAX];
-+	double MinSwathHeightC[DC__NUM_DPP__MAX];
-+	double PSCL_FACTOR[DC__NUM_DPP__MAX];
-+	double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
-+	double MaximumVStartup[DC__NUM_DPP__MAX];
-+	double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
-+	double AlignedYPitch[DC__NUM_DPP__MAX];
-+	double AlignedCPitch[DC__NUM_DPP__MAX];
-+	double MaximumSwathWidth[DC__NUM_DPP__MAX];
-+	double final_flip_bw[DC__NUM_DPP__MAX];
-+	double ImmediateFlipSupportedForState[DC__VOLTAGE_STATES + 1];
-+
-+	double WritebackLumaVExtra;
-+	double WritebackChromaVExtra;
-+	double WritebackRequiredDISPCLK;
-+	double MaximumSwathWidthSupport;
-+	double MaximumSwathWidthInDETBuffer;
-+	double MaximumSwathWidthInLineBuffer;
-+	double MaxDispclkRoundedDownToDFSGranularity;
-+	double MaxDppclkRoundedDownToDFSGranularity;
-+	double PlaneRequiredDISPCLKWithoutODMCombine;
-+	double PlaneRequiredDISPCLK;
-+	double TotalNumberOfActiveOTG;
-+	double FECOverhead;
-+	double EffectiveFECOverhead;
-+	unsigned int Outbpp;
-+	unsigned int OutbppDSC;
-+	double TotalDSCUnitsRequired;
-+	double bpp;
-+	unsigned int slices;
-+	double SwathWidthGranularityY;
-+	double RoundedUpMaxSwathSizeBytesY;
-+	double SwathWidthGranularityC;
-+	double RoundedUpMaxSwathSizeBytesC;
-+	double LinesInDETLuma;
-+	double LinesInDETChroma;
-+	double EffectiveDETLBLinesLuma;
-+	double EffectiveDETLBLinesChroma;
-+	double ProjectedDCFCLKDeepSleep;
-+	double PDEAndMetaPTEBytesPerFrameY;
-+	double PDEAndMetaPTEBytesPerFrameC;
-+	unsigned int MetaRowBytesY;
-+	unsigned int MetaRowBytesC;
-+	unsigned int DPTEBytesPerRowC;
-+	unsigned int DPTEBytesPerRowY;
-+	double ExtraLatency;
-+	double TimeCalc;
-+	double TWait;
-+	double MaximumReadBandwidthWithPrefetch;
-+	double total_dcn_read_bw_with_flip;
-+};
-+
-+#endif /* _DML2_DISPLAY_MODE_VBA_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c.0130~	2017-12-14 06:39:58.427903576 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c	2017-12-14 06:39:58.427903576 +0100
-@@ -0,0 +1,1763 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "display_mode_lib.h"
-+#include "display_mode_vba.h"
-+#include "display_rq_dlg_calc.h"
-+
-+static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
-+		double *refcyc_per_req_delivery_pre_cur,
-+		double *refcyc_per_req_delivery_cur,
-+		double refclk_freq_in_mhz,
-+		double ref_freq_to_pix_freq,
-+		double hscale_pixel_rate_l,
-+		double hscl_ratio,
-+		double vratio_pre_l,
-+		double vratio_l,
-+		unsigned int cur_width,
-+		enum cursor_bpp cur_bpp);
-+
-+#include "dml_inline_defs.h"
-+
-+static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
-+{
-+	unsigned int ret_val = 0;
-+
-+	if (source_format == dm_444_16) {
-+		if (!is_chroma)
-+			ret_val = 2;
-+	} else if (source_format == dm_444_32) {
-+		if (!is_chroma)
-+			ret_val = 4;
-+	} else if (source_format == dm_444_64) {
-+		if (!is_chroma)
-+			ret_val = 8;
-+	} else if (source_format == dm_420_8) {
-+		if (is_chroma)
-+			ret_val = 2;
-+		else
-+			ret_val = 1;
-+	} else if (source_format == dm_420_10) {
-+		if (is_chroma)
-+			ret_val = 4;
-+		else
-+			ret_val = 2;
-+	} else if (source_format == dm_444_8) {
-+		ret_val = 1;
-+	}
-+	return ret_val;
-+}
-+
-+static bool is_dual_plane(enum source_format_class source_format)
-+{
-+	bool ret_val = 0;
-+
-+	if ((source_format == dm_420_8) || (source_format == dm_420_10))
-+		ret_val = 1;
-+
-+	return ret_val;
-+}
-+
-+static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib,
-+		double refclk_freq_in_mhz,
-+		double pclk_freq_in_mhz,
-+		bool odm_combine,
-+		unsigned int recout_width,
-+		unsigned int hactive,
-+		double vratio,
-+		double hscale_pixel_rate,
-+		unsigned int delivery_width,
-+		unsigned int req_per_swath_ub)
-+{
-+	double refcyc_per_delivery = 0.0;
-+
-+	if (vratio <= 1.0) {
-+		if (odm_combine)
-+			refcyc_per_delivery = (double) refclk_freq_in_mhz
-+					* dml_min((double) recout_width, (double) hactive / 2.0)
-+					/ pclk_freq_in_mhz / (double) req_per_swath_ub;
-+		else
-+			refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width
-+					/ pclk_freq_in_mhz / (double) req_per_swath_ub;
-+	} else {
-+		refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width
-+				/ (double) hscale_pixel_rate / (double) req_per_swath_ub;
-+	}
-+
-+	dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
-+	dml_print("DML_DLG: %s: pclk_freq_in_mhz   = %3.2f\n", __func__, pclk_freq_in_mhz);
-+	dml_print("DML_DLG: %s: recout_width       = %d\n", __func__, recout_width);
-+	dml_print("DML_DLG: %s: vratio             = %3.2f\n", __func__, vratio);
-+	dml_print("DML_DLG: %s: req_per_swath_ub   = %d\n", __func__, req_per_swath_ub);
-+	dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery);
-+
-+	return refcyc_per_delivery;
-+
-+}
-+
-+static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
-+{
-+	if (tile_size == dm_256k_tile)
-+		return (256 * 1024);
-+	else if (tile_size == dm_64k_tile)
-+		return (64 * 1024);
-+	else
-+		return (4 * 1024);
-+}
-+
-+static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib,
-+		display_data_rq_regs_st *rq_regs,
-+		const display_data_rq_sizing_params_st rq_sizing)
-+{
-+	dml_print("DML_DLG: %s: rq_sizing param\n", __func__);
-+	print__data_rq_sizing_params_st(mode_lib, rq_sizing);
-+
-+	rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
-+
-+	if (rq_sizing.min_chunk_bytes == 0)
-+		rq_regs->min_chunk_size = 0;
-+	else
-+		rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
-+
-+	rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
-+	if (rq_sizing.min_meta_chunk_bytes == 0)
-+		rq_regs->min_meta_chunk_size = 0;
-+	else
-+		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
-+
-+	rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
-+	rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
-+}
-+
-+static void extract_rq_regs(struct display_mode_lib *mode_lib,
-+		display_rq_regs_st *rq_regs,
-+		const display_rq_params_st rq_param)
-+{
-+	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
-+	unsigned int detile_buf_plane1_addr = 0;
-+
-+	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
-+
-+	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
-+			1) - 3;
-+
-+	if (rq_param.yuv420) {
-+		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
-+		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),
-+				1) - 3;
-+	}
-+
-+	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
-+	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
-+
-+	// FIXME: take the max between luma, chroma chunk size?
-+	// okay for now, as we are setting chunk_bytes to 8kb anyways
-+	if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb
-+		rq_regs->drq_expansion_mode = 0;
-+	} else {
-+		rq_regs->drq_expansion_mode = 2;
-+	}
-+	rq_regs->prq_expansion_mode = 1;
-+	rq_regs->mrq_expansion_mode = 1;
-+	rq_regs->crq_expansion_mode = 1;
-+
-+	if (rq_param.yuv420) {
-+		if ((double) rq_param.misc.rq_l.stored_swath_bytes
-+				/ (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {
-+			detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma
-+		} else {
-+			detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
-+					256,
-+					0) / 64.0; // 2/3 to chroma
-+		}
-+	}
-+	rq_regs->plane1_base_address = detile_buf_plane1_addr;
-+}
-+
-+static void handle_det_buf_split(struct display_mode_lib *mode_lib,
-+		display_rq_params_st *rq_param,
-+		const display_pipe_source_params_st pipe_src_param)
-+{
-+	unsigned int total_swath_bytes = 0;
-+	unsigned int swath_bytes_l = 0;
-+	unsigned int swath_bytes_c = 0;
-+	unsigned int full_swath_bytes_packed_l = 0;
-+	unsigned int full_swath_bytes_packed_c = 0;
-+	bool req128_l = 0;
-+	bool req128_c = 0;
-+	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
-+	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
-+	unsigned int log2_swath_height_l = 0;
-+	unsigned int log2_swath_height_c = 0;
-+	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
-+
-+	full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
-+	full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
-+
-+	if (rq_param->yuv420_10bpc) {
-+		full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2 / 3,
-+				256,
-+				1) + 256;
-+		full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2 / 3,
-+				256,
-+				1) + 256;
-+	}
-+
-+	if (rq_param->yuv420) {
-+		total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
-+
-+		if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request
-+			req128_l = 0;
-+			req128_c = 0;
-+			swath_bytes_l = full_swath_bytes_packed_l;
-+			swath_bytes_c = full_swath_bytes_packed_c;
-+		} else { //128b request (for luma only for yuv420 8bpc)
-+			req128_l = 1;
-+			req128_c = 0;
-+			swath_bytes_l = full_swath_bytes_packed_l / 2;
-+			swath_bytes_c = full_swath_bytes_packed_c;
-+		}
-+		// Note: assumption, the config that pass in will fit into
-+		//       the detiled buffer.
-+	} else {
-+		total_swath_bytes = 2 * full_swath_bytes_packed_l;
-+
-+		if (total_swath_bytes <= detile_buf_size_in_bytes)
-+			req128_l = 0;
-+		else
-+			req128_l = 1;
-+
-+		swath_bytes_l = total_swath_bytes;
-+		swath_bytes_c = 0;
-+	}
-+	rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
-+	rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
-+
-+	if (surf_linear) {
-+		log2_swath_height_l = 0;
-+		log2_swath_height_c = 0;
-+	} else if (!surf_vert) {
-+		log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
-+		log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
-+	} else {
-+		log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
-+		log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
-+	}
-+	rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
-+	rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
-+
-+	dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l);
-+	dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c);
-+	dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n",
-+			__func__,
-+			full_swath_bytes_packed_l);
-+	dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n",
-+			__func__,
-+			full_swath_bytes_packed_c);
-+}
-+
-+static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,
-+		display_data_rq_dlg_params_st *rq_dlg_param,
-+		display_data_rq_misc_params_st *rq_misc_param,
-+		display_data_rq_sizing_params_st *rq_sizing_param,
-+		unsigned int vp_width,
-+		unsigned int vp_height,
-+		unsigned int data_pitch,
-+		unsigned int meta_pitch,
-+		unsigned int source_format,
-+		unsigned int tiling,
-+		unsigned int macro_tile_size,
-+		unsigned int source_scan,
-+		unsigned int is_chroma)
-+{
-+	bool surf_linear = (tiling == dm_sw_linear);
-+	bool surf_vert = (source_scan == dm_vert);
-+
-+	unsigned int bytes_per_element;
-+	unsigned int bytes_per_element_y = get_bytes_per_element((enum source_format_class)(source_format),
-+			false);
-+	unsigned int bytes_per_element_c = get_bytes_per_element((enum source_format_class)(source_format),
-+			true);
-+
-+	unsigned int blk256_width = 0;
-+	unsigned int blk256_height = 0;
-+
-+	unsigned int blk256_width_y = 0;
-+	unsigned int blk256_height_y = 0;
-+	unsigned int blk256_width_c = 0;
-+	unsigned int blk256_height_c = 0;
-+	unsigned int log2_bytes_per_element;
-+	unsigned int log2_blk256_width;
-+	unsigned int log2_blk256_height;
-+	unsigned int blk_bytes;
-+	unsigned int log2_blk_bytes;
-+	unsigned int log2_blk_height;
-+	unsigned int log2_blk_width;
-+	unsigned int log2_meta_req_bytes;
-+	unsigned int log2_meta_req_height;
-+	unsigned int log2_meta_req_width;
-+	unsigned int meta_req_width;
-+	unsigned int meta_req_height;
-+	unsigned int log2_meta_row_height;
-+	unsigned int meta_row_width_ub;
-+	unsigned int log2_meta_chunk_bytes;
-+	unsigned int log2_meta_chunk_height;
-+
-+	//full sized meta chunk width in unit of data elements
-+	unsigned int log2_meta_chunk_width;
-+	unsigned int log2_min_meta_chunk_bytes;
-+	unsigned int min_meta_chunk_width;
-+	unsigned int meta_chunk_width;
-+	unsigned int meta_chunk_per_row_int;
-+	unsigned int meta_row_remainder;
-+	unsigned int meta_chunk_threshold;
-+	unsigned int meta_blk_bytes;
-+	unsigned int meta_blk_height;
-+	unsigned int meta_blk_width;
-+	unsigned int meta_surface_bytes;
-+	unsigned int vmpg_bytes;
-+	unsigned int meta_pte_req_per_frame_ub;
-+	unsigned int meta_pte_bytes_per_frame_ub;
-+	const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
-+	const unsigned int dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs;
-+	const unsigned int pde_proc_buffer_size_64k_reqs =
-+			mode_lib->ip.pde_proc_buffer_size_64k_reqs;
-+
-+	unsigned int log2_vmpg_height = 0;
-+	unsigned int log2_vmpg_width = 0;
-+	unsigned int log2_dpte_req_height_ptes = 0;
-+	unsigned int log2_dpte_req_height = 0;
-+	unsigned int log2_dpte_req_width = 0;
-+	unsigned int log2_dpte_row_height_linear = 0;
-+	unsigned int log2_dpte_row_height = 0;
-+	unsigned int log2_dpte_group_width = 0;
-+	unsigned int dpte_row_width_ub = 0;
-+	unsigned int dpte_req_height = 0;
-+	unsigned int dpte_req_width = 0;
-+	unsigned int dpte_group_width = 0;
-+	unsigned int log2_dpte_group_bytes = 0;
-+	unsigned int log2_dpte_group_length = 0;
-+	unsigned int pde_buf_entries;
-+	bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10);
-+
-+	Calculate256BBlockSizes((enum source_format_class)(source_format),
-+			(enum dm_swizzle_mode)(tiling),
-+			bytes_per_element_y,
-+			bytes_per_element_c,
-+			&blk256_height_y,
-+			&blk256_height_c,
-+			&blk256_width_y,
-+			&blk256_width_c);
-+
-+	if (!is_chroma) {
-+		blk256_width = blk256_width_y;
-+		blk256_height = blk256_height_y;
-+		bytes_per_element = bytes_per_element_y;
-+	} else {
-+		blk256_width = blk256_width_c;
-+		blk256_height = blk256_height_c;
-+		bytes_per_element = bytes_per_element_c;
-+	}
-+
-+	log2_bytes_per_element = dml_log2(bytes_per_element);
-+
-+	dml_print("DML_DLG: %s: surf_linear        = %d\n", __func__, surf_linear);
-+	dml_print("DML_DLG: %s: surf_vert          = %d\n", __func__, surf_vert);
-+	dml_print("DML_DLG: %s: blk256_width       = %d\n", __func__, blk256_width);
-+	dml_print("DML_DLG: %s: blk256_height      = %d\n", __func__, blk256_height);
-+
-+	log2_blk256_width = dml_log2((double) blk256_width);
-+	log2_blk256_height = dml_log2((double) blk256_height);
-+	blk_bytes = surf_linear ?
-+			256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
-+	log2_blk_bytes = dml_log2((double) blk_bytes);
-+	log2_blk_height = 0;
-+	log2_blk_width = 0;
-+
-+	// remember log rule
-+	// "+" in log is multiply
-+	// "-" in log is divide
-+	// "/2" is like square root
-+	// blk is vertical biased
-+	if (tiling != dm_sw_linear)
-+		log2_blk_height = log2_blk256_height
-+				+ dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
-+	else
-+		log2_blk_height = 0;  // blk height of 1
-+
-+	log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
-+
-+	if (!surf_vert) {
-+		rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
-+				+ blk256_width;
-+		rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width;
-+	} else {
-+		rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_height - 1, blk256_height, 1)
-+				+ blk256_height;
-+		rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height;
-+	}
-+
-+	if (!surf_vert)
-+		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height
-+				* bytes_per_element;
-+	else
-+		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width
-+				* bytes_per_element;
-+
-+	rq_misc_param->blk256_height = blk256_height;
-+	rq_misc_param->blk256_width = blk256_width;
-+
-+	// -------
-+	// meta
-+	// -------
-+	log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element
-+
-+	// each 64b meta request for dcn is 8x8 meta elements and
-+	// a meta element covers one 256b block of the the data surface.
-+	log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256
-+	log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
-+			- log2_meta_req_height;
-+	meta_req_width = 1 << log2_meta_req_width;
-+	meta_req_height = 1 << log2_meta_req_height;
-+	log2_meta_row_height = 0;
-+	meta_row_width_ub = 0;
-+
-+	// the dimensions of a meta row are meta_row_width x meta_row_height in elements.
-+	// calculate upper bound of the meta_row_width
-+	if (!surf_vert) {
-+		log2_meta_row_height = log2_meta_req_height;
-+		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
-+				+ meta_req_width;
-+		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
-+	} else {
-+		log2_meta_row_height = log2_meta_req_width;
-+		meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1)
-+				+ meta_req_height;
-+		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
-+	}
-+	rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
-+
-+	rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
-+
-+	log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
-+	log2_meta_chunk_height = log2_meta_row_height;
-+
-+	//full sized meta chunk width in unit of data elements
-+	log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element
-+			- log2_meta_chunk_height;
-+	log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
-+	min_meta_chunk_width = 1
-+			<< (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element
-+					- log2_meta_chunk_height);
-+	meta_chunk_width = 1 << log2_meta_chunk_width;
-+	meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
-+	meta_row_remainder = meta_row_width_ub % meta_chunk_width;
-+	meta_chunk_threshold = 0;
-+	meta_blk_bytes = 4096;
-+	meta_blk_height = blk256_height * 64;
-+	meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height;
-+	meta_surface_bytes = meta_pitch
-+			* (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height)
-+			* bytes_per_element / 256;
-+	vmpg_bytes = mode_lib->soc.vmm_page_size_bytes;
-+	meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes,
-+			8 * vmpg_bytes,
-+			1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
-+	meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request
-+	rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
-+
-+	dml_print("DML_DLG: %s: meta_blk_height             = %d\n", __func__, meta_blk_height);
-+	dml_print("DML_DLG: %s: meta_blk_width              = %d\n", __func__, meta_blk_width);
-+	dml_print("DML_DLG: %s: meta_surface_bytes          = %d\n", __func__, meta_surface_bytes);
-+	dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub   = %d\n",
-+			__func__,
-+			meta_pte_req_per_frame_ub);
-+	dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n",
-+			__func__,
-+			meta_pte_bytes_per_frame_ub);
-+
-+	if (!surf_vert)
-+		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
-+	else
-+		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
-+
-+	if (meta_row_remainder <= meta_chunk_threshold)
-+		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
-+	else
-+		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
-+
-+	// ------
-+	// dpte
-+	// ------
-+	if (surf_linear) {
-+		log2_vmpg_height = 0;   // one line high
-+	} else {
-+		log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
-+	}
-+	log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
-+
-+	// only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4.
-+	if (surf_linear) { //one 64B PTE request returns 8 PTEs
-+		log2_dpte_req_height_ptes = 0;
-+		log2_dpte_req_width = log2_vmpg_width + 3;
-+		log2_dpte_req_height = 0;
-+	} else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size
-+		//one 64B req gives 8x1 PTEs for 4KB tile
-+		log2_dpte_req_height_ptes = 0;
-+		log2_dpte_req_width = log2_blk_width + 3;
-+		log2_dpte_req_height = log2_blk_height + 0;
-+	} else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB
-+		//two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB
-+		log2_dpte_req_height_ptes = 4;
-+		log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width
-+		log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height
-+	} else { //64KB page size and must 64KB tile block
-+		 //one 64B req gives 8x1 PTEs for 64KB tile
-+		log2_dpte_req_height_ptes = 0;
-+		log2_dpte_req_width = log2_blk_width + 3;
-+		log2_dpte_req_height = log2_blk_height + 0;
-+	}
-+
-+	// The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
-+	// log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
-+	// That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
-+	//log2_dpte_req_height    = log2_vmpg_height + log2_dpte_req_height_ptes;
-+	//log2_dpte_req_width     = log2_vmpg_width + log2_dpte_req_width_ptes;
-+	dpte_req_height = 1 << log2_dpte_req_height;
-+	dpte_req_width = 1 << log2_dpte_req_width;
-+
-+	// calculate pitch dpte row buffer can hold
-+	// round the result down to a power of two.
-+	pde_buf_entries = yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs;
-+	if (surf_linear) {
-+		unsigned int dpte_row_height;
-+
-+		log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries
-+										/ bytes_per_element,
-+								dpte_buf_in_pte_reqs
-+										* dpte_req_width)
-+								/ data_pitch),
-+				1);
-+
-+		ASSERT(log2_dpte_row_height_linear >= 3);
-+
-+		if (log2_dpte_row_height_linear > 7)
-+			log2_dpte_row_height_linear = 7;
-+
-+		log2_dpte_row_height = log2_dpte_row_height_linear;
-+		// For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
-+		// the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
-+		dpte_row_height = 1 << log2_dpte_row_height;
-+		dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
-+				dpte_req_width,
-+				1) + dpte_req_width;
-+		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
-+	} else {
-+		// the upper bound of the dpte_row_width without dependency on viewport position follows.
-+		// for tiled mode, row height is the same as req height and row store up to vp size upper bound
-+		if (!surf_vert) {
-+			log2_dpte_row_height = log2_dpte_req_height;
-+			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
-+					+ dpte_req_width;
-+			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
-+		} else {
-+			log2_dpte_row_height =
-+					(log2_blk_width < log2_dpte_req_width) ?
-+							log2_blk_width : log2_dpte_req_width;
-+			dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
-+					+ dpte_req_height;
-+			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
-+		}
-+	}
-+	if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB
-+		rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request
-+	else
-+		rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request
-+
-+	rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
-+
-+	// the dpte_group_bytes is reduced for the specific case of vertical
-+	// access of a tile surface that has dpte request of 8x1 ptes.
-+	if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group
-+		rq_sizing_param->dpte_group_bytes = 512;
-+	else
-+		//full size
-+		rq_sizing_param->dpte_group_bytes = 2048;
-+
-+	//since pte request size is 64byte, the number of data pte requests per full sized group is as follows.
-+	log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
-+	log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests
-+
-+	// full sized data pte group width in elements
-+	if (!surf_vert)
-+		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
-+	else
-+		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
-+
-+	//But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B
-+	if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB
-+		log2_dpte_group_width = log2_dpte_group_width - 1;
-+
-+	dpte_group_width = 1 << log2_dpte_group_width;
-+
-+	// since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
-+	// the upper bound for the dpte groups per row is as follows.
-+	rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
-+			1);
-+}
-+
-+static void get_surf_rq_param(struct display_mode_lib *mode_lib,
-+		display_data_rq_sizing_params_st *rq_sizing_param,
-+		display_data_rq_dlg_params_st *rq_dlg_param,
-+		display_data_rq_misc_params_st *rq_misc_param,
-+		const display_pipe_source_params_st pipe_src_param,
-+		bool is_chroma)
-+{
-+	bool mode_422 = 0;
-+	unsigned int vp_width = 0;
-+	unsigned int vp_height = 0;
-+	unsigned int data_pitch = 0;
-+	unsigned int meta_pitch = 0;
-+	unsigned int ppe = mode_422 ? 2 : 1;
-+
-+	// FIXME check if ppe apply for both luma and chroma in 422 case
-+	if (is_chroma) {
-+		vp_width = pipe_src_param.viewport_width_c / ppe;
-+		vp_height = pipe_src_param.viewport_height_c;
-+		data_pitch = pipe_src_param.data_pitch_c;
-+		meta_pitch = pipe_src_param.meta_pitch_c;
-+	} else {
-+		vp_width = pipe_src_param.viewport_width / ppe;
-+		vp_height = pipe_src_param.viewport_height;
-+		data_pitch = pipe_src_param.data_pitch;
-+		meta_pitch = pipe_src_param.meta_pitch;
-+	}
-+
-+	rq_sizing_param->chunk_bytes = 8192;
-+
-+	if (rq_sizing_param->chunk_bytes == 64 * 1024)
-+		rq_sizing_param->min_chunk_bytes = 0;
-+	else
-+		rq_sizing_param->min_chunk_bytes = 1024;
-+
-+	rq_sizing_param->meta_chunk_bytes = 2048;
-+	rq_sizing_param->min_meta_chunk_bytes = 256;
-+
-+	rq_sizing_param->mpte_group_bytes = 2048;
-+
-+	get_meta_and_pte_attr(mode_lib,
-+			rq_dlg_param,
-+			rq_misc_param,
-+			rq_sizing_param,
-+			vp_width,
-+			vp_height,
-+			data_pitch,
-+			meta_pitch,
-+			pipe_src_param.source_format,
-+			pipe_src_param.sw_mode,
-+			pipe_src_param.macro_tile_size,
-+			pipe_src_param.source_scan,
-+			is_chroma);
-+}
-+
-+void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib,
-+		display_rq_params_st *rq_param,
-+		const display_pipe_source_params_st pipe_src_param)
-+{
-+	// get param for luma surface
-+	rq_param->yuv420 = pipe_src_param.source_format == dm_420_8
-+			|| pipe_src_param.source_format == dm_420_10;
-+	rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10;
-+
-+	get_surf_rq_param(mode_lib,
-+			&(rq_param->sizing.rq_l),
-+			&(rq_param->dlg.rq_l),
-+			&(rq_param->misc.rq_l),
-+			pipe_src_param,
-+			0);
-+
-+	if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) {
-+		// get param for chroma surface
-+		get_surf_rq_param(mode_lib,
-+				&(rq_param->sizing.rq_c),
-+				&(rq_param->dlg.rq_c),
-+				&(rq_param->misc.rq_c),
-+				pipe_src_param,
-+				1);
-+	}
-+
-+	// calculate how to split the det buffer space between luma and chroma
-+	handle_det_buf_split(mode_lib, rq_param, pipe_src_param);
-+	print__rq_params_st(mode_lib, *rq_param);
-+}
-+
-+void dml_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
-+		display_rq_regs_st *rq_regs,
-+		const display_pipe_source_params_st pipe_src_param)
-+{
-+	display_rq_params_st rq_param = {0};
-+
-+	memset(rq_regs, 0, sizeof(*rq_regs));
-+	dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_src_param);
-+	extract_rq_regs(mode_lib, rq_regs, rq_param);
-+
-+	print__rq_regs_st(mode_lib, *rq_regs);
-+}
-+
-+// Note: currently taken in as is.
-+// Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
-+void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
-+		const display_e2e_pipe_params_st *e2e_pipe_param,
-+		const unsigned int num_pipes,
-+		const unsigned int pipe_idx,
-+		display_dlg_regs_st *disp_dlg_regs,
-+		display_ttu_regs_st *disp_ttu_regs,
-+		const display_rq_dlg_params_st rq_dlg_param,
-+		const display_dlg_sys_params_st dlg_sys_param,
-+		const bool cstate_en,
-+		const bool pstate_en,
-+		const bool vm_en,
-+		const bool ignore_viewport_pos,
-+		const bool immediate_flip_support)
-+{
-+	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
-+	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
-+	const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
-+	const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
-+	const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
-+	const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
-+
-+	// -------------------------
-+	// Section 1.15.2.1: OTG dependent Params
-+	// -------------------------
-+	// Timing
-+	unsigned int htotal = dst->htotal;
-+//    unsigned int hblank_start = dst.hblank_start; // TODO: Remove
-+	unsigned int hblank_end = dst->hblank_end;
-+	unsigned int vblank_start = dst->vblank_start;
-+	unsigned int vblank_end = dst->vblank_end;
-+	unsigned int min_vblank = mode_lib->ip.min_vblank_lines;
-+
-+	double dppclk_freq_in_mhz = clks->dppclk_mhz;
-+	double dispclk_freq_in_mhz = clks->dispclk_mhz;
-+	double refclk_freq_in_mhz = clks->refclk_mhz;
-+	double pclk_freq_in_mhz = dst->pixel_rate_mhz;
-+	bool interlaced = dst->interlaced;
-+
-+	double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
-+
-+	double min_dcfclk_mhz;
-+	double t_calc_us;
-+	double min_ttu_vblank;
-+
-+	double min_dst_y_ttu_vblank;
-+	unsigned int dlg_vblank_start;
-+	bool dual_plane;
-+	bool mode_422;
-+	unsigned int access_dir;
-+	unsigned int vp_height_l;
-+	unsigned int vp_width_l;
-+	unsigned int vp_height_c;
-+	unsigned int vp_width_c;
-+
-+	// Scaling
-+	unsigned int htaps_l;
-+	unsigned int htaps_c;
-+	double hratio_l;
-+	double hratio_c;
-+	double vratio_l;
-+	double vratio_c;
-+	bool scl_enable;
-+
-+	double line_time_in_us;
-+	//    double vinit_l;
-+	//    double vinit_c;
-+	//    double vinit_bot_l;
-+	//    double vinit_bot_c;
-+
-+	//    unsigned int swath_height_l;
-+	unsigned int swath_width_ub_l;
-+	//    unsigned int dpte_bytes_per_row_ub_l;
-+	unsigned int dpte_groups_per_row_ub_l;
-+	//    unsigned int meta_pte_bytes_per_frame_ub_l;
-+	//    unsigned int meta_bytes_per_row_ub_l;
-+
-+	//    unsigned int swath_height_c;
-+	unsigned int swath_width_ub_c;
-+	//   unsigned int dpte_bytes_per_row_ub_c;
-+	unsigned int dpte_groups_per_row_ub_c;
-+
-+	unsigned int meta_chunks_per_row_ub_l;
-+	unsigned int meta_chunks_per_row_ub_c;
-+	unsigned int vupdate_offset;
-+	unsigned int vupdate_width;
-+	unsigned int vready_offset;
-+
-+	unsigned int dppclk_delay_subtotal;
-+	unsigned int dispclk_delay_subtotal;
-+	unsigned int pixel_rate_delay_subtotal;
-+
-+	unsigned int vstartup_start;
-+	unsigned int dst_x_after_scaler;
-+	unsigned int dst_y_after_scaler;
-+	double line_wait;
-+	double dst_y_prefetch;
-+	double dst_y_per_vm_vblank;
-+	double dst_y_per_row_vblank;
-+	double dst_y_per_vm_flip;
-+	double dst_y_per_row_flip;
-+	double min_dst_y_per_vm_vblank;
-+	double min_dst_y_per_row_vblank;
-+	double lsw;
-+	double vratio_pre_l;
-+	double vratio_pre_c;
-+	unsigned int req_per_swath_ub_l;
-+	unsigned int req_per_swath_ub_c;
-+	unsigned int meta_row_height_l;
-+	unsigned int meta_row_height_c;
-+	unsigned int swath_width_pixels_ub_l;
-+	unsigned int swath_width_pixels_ub_c;
-+	unsigned int scaler_rec_in_width_l;
-+	unsigned int scaler_rec_in_width_c;
-+	unsigned int dpte_row_height_l;
-+	unsigned int dpte_row_height_c;
-+	double hscale_pixel_rate_l;
-+	double hscale_pixel_rate_c;
-+	double min_hratio_fact_l;
-+	double min_hratio_fact_c;
-+	double refcyc_per_line_delivery_pre_l;
-+	double refcyc_per_line_delivery_pre_c;
-+	double refcyc_per_line_delivery_l;
-+	double refcyc_per_line_delivery_c;
-+
-+	double refcyc_per_req_delivery_pre_l;
-+	double refcyc_per_req_delivery_pre_c;
-+	double refcyc_per_req_delivery_l;
-+	double refcyc_per_req_delivery_c;
-+
-+	unsigned int full_recout_width;
-+	double xfc_transfer_delay;
-+	double xfc_precharge_delay;
-+	double xfc_remote_surface_flip_latency;
-+	double xfc_dst_y_delta_drq_limit;
-+	double xfc_prefetch_margin;
-+	double refcyc_per_req_delivery_pre_cur0;
-+	double refcyc_per_req_delivery_cur0;
-+	double refcyc_per_req_delivery_pre_cur1;
-+	double refcyc_per_req_delivery_cur1;
-+
-+	memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
-+	memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
-+
-+	dml_print("DML_DLG: %s:  cstate_en = %d\n", __func__, cstate_en);
-+	dml_print("DML_DLG: %s:  pstate_en = %d\n", __func__, pstate_en);
-+	dml_print("DML_DLG: %s:  vm_en     = %d\n", __func__, vm_en);
-+	dml_print("DML_DLG: %s:  ignore_viewport_pos  = %d\n", __func__, ignore_viewport_pos);
-+	dml_print("DML_DLG: %s:  immediate_flip_support  = %d\n", __func__, immediate_flip_support);
-+
-+	dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
-+	dml_print("DML_DLG: %s: dispclk_freq_in_mhz    = %3.2f\n", __func__, dispclk_freq_in_mhz);
-+	dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
-+	dml_print("DML_DLG: %s: pclk_freq_in_mhz       = %3.2f\n", __func__, pclk_freq_in_mhz);
-+	dml_print("DML_DLG: %s: interlaced             = %d\n", __func__, interlaced);
-+	ASSERT(ref_freq_to_pix_freq < 4.0);
-+
-+	disp_dlg_regs->ref_freq_to_pix_freq =
-+			(unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
-+	disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
-+			* dml_pow(2, 8));
-+	disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
-+	disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end
-+			* (double) ref_freq_to_pix_freq);
-+	ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));
-+
-+	min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
-+	set_prefetch_mode(mode_lib, cstate_en, pstate_en, ignore_viewport_pos, immediate_flip_support);
-+	t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes);
-+	min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
-+
-+	min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
-+	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
-+
-+	disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
-+			+ min_dst_y_ttu_vblank) * dml_pow(2, 2));
-+	ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
-+
-+	dml_print("DML_DLG: %s: min_dcfclk_mhz                         = %3.2f\n",
-+			__func__,
-+			min_dcfclk_mhz);
-+	dml_print("DML_DLG: %s: min_ttu_vblank                         = %3.2f\n",
-+			__func__,
-+			min_ttu_vblank);
-+	dml_print("DML_DLG: %s: min_dst_y_ttu_vblank                   = %3.2f\n",
-+			__func__,
-+			min_dst_y_ttu_vblank);
-+	dml_print("DML_DLG: %s: t_calc_us                              = %3.2f\n",
-+			__func__,
-+			t_calc_us);
-+	dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start    = 0x%0x\n",
-+			__func__,
-+			disp_dlg_regs->min_dst_y_next_start);
-+	dml_print("DML_DLG: %s: ref_freq_to_pix_freq                   = %3.2f\n",
-+			__func__,
-+			ref_freq_to_pix_freq);
-+
-+	// -------------------------
-+	// Section 1.15.2.2: Prefetch, Active and TTU
-+	// -------------------------
-+	// Prefetch Calc
-+	// Source
-+//             dcc_en              = src.dcc;
-+	dual_plane = is_dual_plane((enum source_format_class)(src->source_format));
-+	mode_422 = 0; // FIXME
-+	access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
-+//      bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);
-+//      bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);
-+	vp_height_l = src->viewport_height;
-+	vp_width_l = src->viewport_width;
-+	vp_height_c = src->viewport_height_c;
-+	vp_width_c = src->viewport_width_c;
-+
-+	// Scaling
-+	htaps_l = taps->htaps;
-+	htaps_c = taps->htaps_c;
-+	hratio_l = scl->hscl_ratio;
-+	hratio_c = scl->hscl_ratio_c;
-+	vratio_l = scl->vscl_ratio;
-+	vratio_c = scl->vscl_ratio_c;
-+	scl_enable = scl->scl_enable;
-+
-+	line_time_in_us = (htotal / pclk_freq_in_mhz);
-+//     vinit_l         = scl.vinit;
-+//     vinit_c         = scl.vinit_c;
-+//     vinit_bot_l     = scl.vinit_bot;
-+//     vinit_bot_c     = scl.vinit_bot_c;
-+
-+//    unsigned int swath_height_l                 = rq_dlg_param.rq_l.swath_height;
-+	swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
-+//    unsigned int dpte_bytes_per_row_ub_l        = rq_dlg_param.rq_l.dpte_bytes_per_row_ub;
-+	dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
-+//    unsigned int meta_pte_bytes_per_frame_ub_l  = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub;
-+//    unsigned int meta_bytes_per_row_ub_l        = rq_dlg_param.rq_l.meta_bytes_per_row_ub;
-+
-+//    unsigned int swath_height_c                 = rq_dlg_param.rq_c.swath_height;
-+	swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
-+	//   dpte_bytes_per_row_ub_c        = rq_dlg_param.rq_c.dpte_bytes_per_row_ub;
-+	dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
-+
-+	meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
-+	meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub;
-+	vupdate_offset = dst->vupdate_offset;
-+	vupdate_width = dst->vupdate_width;
-+	vready_offset = dst->vready_offset;
-+
-+	dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
-+	dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
-+
-+	if (scl_enable)
-+		dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl;
-+	else
-+		dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only;
-+
-+	dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter
-+			+ src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor;
-+
-+	if (dout->dsc_enable) {
-+		double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
-+
-+		dispclk_delay_subtotal += dsc_delay;
-+	}
-+
-+	pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz
-+			+ dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz;
-+
-+	vstartup_start = dst->vstartup_start;
-+	if (interlaced) {
-+		if (vstartup_start / 2.0
-+				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
-+				<= vblank_end / 2.0)
-+			disp_dlg_regs->vready_after_vcount0 = 1;
-+		else
-+			disp_dlg_regs->vready_after_vcount0 = 0;
-+	} else {
-+		if (vstartup_start
-+				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
-+				<= vblank_end)
-+			disp_dlg_regs->vready_after_vcount0 = 1;
-+		else
-+			disp_dlg_regs->vready_after_vcount0 = 0;
-+	}
-+
-+	// TODO: Where is this coming from?
-+	if (interlaced)
-+		vstartup_start = vstartup_start / 2;
-+
-+	// TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp?
-+	if (vstartup_start >= min_vblank) {
-+		dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",
-+				__func__,
-+				vblank_start,
-+				vblank_end);
-+		dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
-+				__func__,
-+				vstartup_start,
-+				min_vblank);
-+		min_vblank = vstartup_start + 1;
-+		dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
-+				__func__,
-+				vstartup_start,
-+				min_vblank);
-+	}
-+
-+	dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
-+	dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
-+
-+	dml_print("DML_DLG: %s: htotal                                 = %d\n", __func__, htotal);
-+	dml_print("DML_DLG: %s: pixel_rate_delay_subtotal              = %d\n",
-+			__func__,
-+			pixel_rate_delay_subtotal);
-+	dml_print("DML_DLG: %s: dst_x_after_scaler                     = %d\n",
-+			__func__,
-+			dst_x_after_scaler);
-+	dml_print("DML_DLG: %s: dst_y_after_scaler                     = %d\n",
-+			__func__,
-+			dst_y_after_scaler);
-+
-+	// Lwait
-+	line_wait = mode_lib->soc.urgent_latency_us;
-+	if (cstate_en)
-+		line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
-+	if (pstate_en)
-+		line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us
-+						+ mode_lib->soc.urgent_latency_us,
-+				line_wait);
-+	line_wait = line_wait / line_time_in_us;
-+
-+	dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
-+	dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
-+
-+	dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib,
-+			e2e_pipe_param,
-+			num_pipes,
-+			pipe_idx);
-+	dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib,
-+			e2e_pipe_param,
-+			num_pipes,
-+			pipe_idx);
-+	dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
-+	dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
-+
-+	min_dst_y_per_vm_vblank = 8.0;
-+	min_dst_y_per_row_vblank = 16.0;
-+
-+	// magic!
-+	if (htotal <= 75) {
-+		min_vblank = 300;
-+		min_dst_y_per_vm_vblank = 100.0;
-+		min_dst_y_per_row_vblank = 100.0;
-+	}
-+
-+	dml_print("DML_DLG: %s: dst_y_per_vm_vblank    = %3.2f\n", __func__, dst_y_per_vm_vblank);
-+	dml_print("DML_DLG: %s: dst_y_per_row_vblank   = %3.2f\n", __func__, dst_y_per_row_vblank);
-+
-+	ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank);
-+	ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank);
-+
-+	ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
-+	lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank);
-+
-+	dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw);
-+
-+	vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
-+	vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
-+
-+	dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l);
-+	dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c);
-+
-+	// Active
-+	req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
-+	req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
-+	meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
-+	meta_row_height_c = rq_dlg_param.rq_c.meta_row_height;
-+	swath_width_pixels_ub_l = 0;
-+	swath_width_pixels_ub_c = 0;
-+	scaler_rec_in_width_l = 0;
-+	scaler_rec_in_width_c = 0;
-+	dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
-+	dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
-+
-+	if (mode_422) {
-+		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element
-+		swath_width_pixels_ub_c = swath_width_ub_c * 2;
-+	} else {
-+		swath_width_pixels_ub_l = swath_width_ub_l * 1;
-+		swath_width_pixels_ub_c = swath_width_ub_c * 1;
-+	}
-+
-+	hscale_pixel_rate_l = 0.;
-+	hscale_pixel_rate_c = 0.;
-+	min_hratio_fact_l = 1.0;
-+	min_hratio_fact_c = 1.0;
-+
-+	if (htaps_l <= 1)
-+		min_hratio_fact_l = 2.0;
-+	else if (htaps_l <= 6) {
-+		if ((hratio_l * 2.0) > 4.0)
-+			min_hratio_fact_l = 4.0;
-+		else
-+			min_hratio_fact_l = hratio_l * 2.0;
-+	} else {
-+		if (hratio_l > 4.0)
-+			min_hratio_fact_l = 4.0;
-+		else
-+			min_hratio_fact_l = hratio_l;
-+	}
-+
-+	hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
-+
-+	if (htaps_c <= 1)
-+		min_hratio_fact_c = 2.0;
-+	else if (htaps_c <= 6) {
-+		if ((hratio_c * 2.0) > 4.0)
-+			min_hratio_fact_c = 4.0;
-+		else
-+			min_hratio_fact_c = hratio_c * 2.0;
-+	} else {
-+		if (hratio_c > 4.0)
-+			min_hratio_fact_c = 4.0;
-+		else
-+			min_hratio_fact_c = hratio_c;
-+	}
-+
-+	hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
-+
-+	refcyc_per_line_delivery_pre_l = 0.;
-+	refcyc_per_line_delivery_pre_c = 0.;
-+	refcyc_per_line_delivery_l = 0.;
-+	refcyc_per_line_delivery_c = 0.;
-+
-+	refcyc_per_req_delivery_pre_l = 0.;
-+	refcyc_per_req_delivery_pre_c = 0.;
-+	refcyc_per_req_delivery_l = 0.;
-+	refcyc_per_req_delivery_c = 0.;
-+
-+	full_recout_width = 0;
-+	// In ODM
-+	if (src->is_hsplit) {
-+		// This "hack"  is only allowed (and valid) for MPC combine. In ODM
-+		// combine, you MUST specify the full_recout_width...according to Oswin
-+		if (dst->full_recout_width == 0 && !dst->odm_combine) {
-+			dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n",
-+					__func__);
-+			full_recout_width = dst->recout_width * 2; // assume half split for dcn1
-+		} else
-+			full_recout_width = dst->full_recout_width;
-+	} else
-+		full_recout_width = dst->recout_width;
-+
-+	// mpc_combine and odm_combine are mutually exclusive
-+	refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib,
-+			refclk_freq_in_mhz,
-+			pclk_freq_in_mhz,
-+			dst->odm_combine,
-+			full_recout_width,
-+			dst->hactive,
-+			vratio_pre_l,
-+			hscale_pixel_rate_l,
-+			swath_width_pixels_ub_l,
-+			1); // per line
-+
-+	refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib,
-+			refclk_freq_in_mhz,
-+			pclk_freq_in_mhz,
-+			dst->odm_combine,
-+			full_recout_width,
-+			dst->hactive,
-+			vratio_l,
-+			hscale_pixel_rate_l,
-+			swath_width_pixels_ub_l,
-+			1); // per line
-+
-+	dml_print("DML_DLG: %s: full_recout_width              = %d\n",
-+			__func__,
-+			full_recout_width);
-+	dml_print("DML_DLG: %s: hscale_pixel_rate_l            = %3.2f\n",
-+			__func__,
-+			hscale_pixel_rate_l);
-+	dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n",
-+			__func__,
-+			refcyc_per_line_delivery_pre_l);
-+	dml_print("DML_DLG: %s: refcyc_per_line_delivery_l     = %3.2f\n",
-+			__func__,
-+			refcyc_per_line_delivery_l);
-+
-+	if (dual_plane) {
-+		refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib,
-+				refclk_freq_in_mhz,
-+				pclk_freq_in_mhz,
-+				dst->odm_combine,
-+				full_recout_width,
-+				dst->hactive,
-+				vratio_pre_c,
-+				hscale_pixel_rate_c,
-+				swath_width_pixels_ub_c,
-+				1); // per line
-+
-+		refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib,
-+				refclk_freq_in_mhz,
-+				pclk_freq_in_mhz,
-+				dst->odm_combine,
-+				full_recout_width,
-+				dst->hactive,
-+				vratio_c,
-+				hscale_pixel_rate_c,
-+				swath_width_pixels_ub_c,
-+				1);  // per line
-+
-+		dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",
-+				__func__,
-+				refcyc_per_line_delivery_pre_c);
-+		dml_print("DML_DLG: %s: refcyc_per_line_delivery_c     = %3.2f\n",
-+				__func__,
-+				refcyc_per_line_delivery_c);
-+	}
-+
-+	// TTU - Luma / Chroma
-+	if (access_dir) {  // vertical access
-+		scaler_rec_in_width_l = vp_height_l;
-+		scaler_rec_in_width_c = vp_height_c;
-+	} else {
-+		scaler_rec_in_width_l = vp_width_l;
-+		scaler_rec_in_width_c = vp_width_c;
-+	}
-+
-+	refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib,
-+			refclk_freq_in_mhz,
-+			pclk_freq_in_mhz,
-+			dst->odm_combine,
-+			full_recout_width,
-+			dst->hactive,
-+			vratio_pre_l,
-+			hscale_pixel_rate_l,
-+			scaler_rec_in_width_l,
-+			req_per_swath_ub_l);  // per req
-+	refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib,
-+			refclk_freq_in_mhz,
-+			pclk_freq_in_mhz,
-+			dst->odm_combine,
-+			full_recout_width,
-+			dst->hactive,
-+			vratio_l,
-+			hscale_pixel_rate_l,
-+			scaler_rec_in_width_l,
-+			req_per_swath_ub_l);  // per req
-+
-+	dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n",
-+			__func__,
-+			refcyc_per_req_delivery_pre_l);
-+	dml_print("DML_DLG: %s: refcyc_per_req_delivery_l     = %3.2f\n",
-+			__func__,
-+			refcyc_per_req_delivery_l);
-+
-+	ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
-+	ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
-+
-+	if (dual_plane) {
-+		refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib,
-+				refclk_freq_in_mhz,
-+				pclk_freq_in_mhz,
-+				dst->odm_combine,
-+				full_recout_width,
-+				dst->hactive,
-+				vratio_pre_c,
-+				hscale_pixel_rate_c,
-+				scaler_rec_in_width_c,
-+				req_per_swath_ub_c);  // per req
-+		refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib,
-+				refclk_freq_in_mhz,
-+				pclk_freq_in_mhz,
-+				dst->odm_combine,
-+				full_recout_width,
-+				dst->hactive,
-+				vratio_c,
-+				hscale_pixel_rate_c,
-+				scaler_rec_in_width_c,
-+				req_per_swath_ub_c);  // per req
-+
-+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",
-+				__func__,
-+				refcyc_per_req_delivery_pre_c);
-+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_c     = %3.2f\n",
-+				__func__,
-+				refcyc_per_req_delivery_c);
-+
-+		ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
-+		ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
-+	}
-+
-+	// XFC
-+	xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
-+	xfc_precharge_delay = get_xfc_precharge_delay(mode_lib,
-+			e2e_pipe_param,
-+			num_pipes,
-+			pipe_idx);
-+	xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(mode_lib,
-+			e2e_pipe_param,
-+			num_pipes,
-+			pipe_idx);
-+	xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;
-+	xfc_prefetch_margin = get_xfc_prefetch_margin(mode_lib,
-+			e2e_pipe_param,
-+			num_pipes,
-+			pipe_idx);
-+
-+	// TTU - Cursor
-+	refcyc_per_req_delivery_pre_cur0 = 0.0;
-+	refcyc_per_req_delivery_cur0 = 0.0;
-+	if (src->num_cursors > 0) {
-+		calculate_ttu_cursor(mode_lib,
-+				&refcyc_per_req_delivery_pre_cur0,
-+				&refcyc_per_req_delivery_cur0,
-+				refclk_freq_in_mhz,
-+				ref_freq_to_pix_freq,
-+				hscale_pixel_rate_l,
-+				scl->hscl_ratio,
-+				vratio_pre_l,
-+				vratio_l,
-+				src->cur0_src_width,
-+				(enum cursor_bpp)(src->cur0_bpp));
-+	}
-+
-+	refcyc_per_req_delivery_pre_cur1 = 0.0;
-+	refcyc_per_req_delivery_cur1 = 0.0;
-+	if (src->num_cursors > 1) {
-+		calculate_ttu_cursor(mode_lib,
-+				&refcyc_per_req_delivery_pre_cur1,
-+				&refcyc_per_req_delivery_cur1,
-+				refclk_freq_in_mhz,
-+				ref_freq_to_pix_freq,
-+				hscale_pixel_rate_l,
-+				scl->hscl_ratio,
-+				vratio_pre_l,
-+				vratio_l,
-+				src->cur1_src_width,
-+				(enum cursor_bpp)(src->cur1_bpp));
-+	}
-+
-+	// TTU - Misc
-+	// all hard-coded
-+
-+	// Assignment to register structures
-+	disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line
-+	disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk
-+	ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));
-+	disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
-+	disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
-+	disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
-+	disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
-+	disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
-+
-+	disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
-+	disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
-+
-+	disp_dlg_regs->refcyc_per_pte_group_vblank_l =
-+			(unsigned int) (dst_y_per_row_vblank * (double) htotal
-+					* ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
-+	ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));
-+
-+	if (dual_plane) {
-+		disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank
-+				* (double) htotal * ref_freq_to_pix_freq
-+				/ (double) dpte_groups_per_row_ub_c);
-+		ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
-+						< (unsigned int) dml_pow(2, 13));
-+	}
-+
-+	disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
-+			(unsigned int) (dst_y_per_row_vblank * (double) htotal
-+					* ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
-+	ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
-+
-+	disp_dlg_regs->refcyc_per_meta_chunk_vblank_c =
-+			disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
-+
-+	disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
-+			* ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l;
-+	disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
-+			* ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l;
-+
-+	if (dual_plane) {
-+		disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip
-+				* htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c;
-+		disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip
-+				* htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c;
-+	}
-+
-+	disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l
-+			/ (double) vratio_l * dml_pow(2, 2));
-+	ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));
-+
-+	if (dual_plane) {
-+		disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c
-+				/ (double) vratio_c * dml_pow(2, 2));
-+		if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
-+			dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",
-+					__func__,
-+					disp_dlg_regs->dst_y_per_pte_row_nom_c,
-+					(unsigned int) dml_pow(2, 17) - 1);
-+		}
-+	}
-+
-+	disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
-+			/ (double) vratio_l * dml_pow(2, 2));
-+	ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
-+
-+	disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
-+
-+	disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l
-+			/ (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
-+			/ (double) dpte_groups_per_row_ub_l);
-+	if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
-+		disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
-+	disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l
-+			/ (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
-+			/ (double) meta_chunks_per_row_ub_l);
-+	if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
-+		disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
-+
-+	if (dual_plane) {
-+		disp_dlg_regs->refcyc_per_pte_group_nom_c =
-+				(unsigned int) ((double) dpte_row_height_c / (double) vratio_c
-+						* (double) htotal * ref_freq_to_pix_freq
-+						/ (double) dpte_groups_per_row_ub_c);
-+		if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
-+			disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
-+
-+		// TODO: Is this the right calculation? Does htotal need to be halved?
-+		disp_dlg_regs->refcyc_per_meta_chunk_nom_c =
-+				(unsigned int) ((double) meta_row_height_c / (double) vratio_c
-+						* (double) htotal * ref_freq_to_pix_freq
-+						/ (double) meta_chunks_per_row_ub_c);
-+		if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
-+			disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
-+	}
-+
-+	disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l,
-+			1);
-+	disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l,
-+			1);
-+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
-+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));
-+
-+	disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c,
-+			1);
-+	disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c,
-+			1);
-+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));
-+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));
-+
-+	disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
-+	disp_dlg_regs->dst_y_offset_cur0 = 0;
-+	disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;
-+	disp_dlg_regs->dst_y_offset_cur1 = 0;
-+
-+	disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay;
-+	disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay;
-+	disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency;
-+	disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz,
-+			1);
-+
-+	// slave has to have this value also set to off
-+	if (src->xfc_enable && !src->xfc_slave)
-+		disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
-+	else
-+		disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
-+
-+	disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l
-+			* dml_pow(2, 10));
-+	disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l
-+			* dml_pow(2, 10));
-+	disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c
-+			* dml_pow(2, 10));
-+	disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c
-+			* dml_pow(2, 10));
-+	disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 =
-+			(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
-+	disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0
-+			* dml_pow(2, 10));
-+	disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 =
-+			(unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));
-+	disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1
-+			* dml_pow(2, 10));
-+	disp_ttu_regs->qos_level_low_wm = 0;
-+	ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
-+	disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
-+			* ref_freq_to_pix_freq);
-+	ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
-+
-+	disp_ttu_regs->qos_level_flip = 14;
-+	disp_ttu_regs->qos_level_fixed_l = 8;
-+	disp_ttu_regs->qos_level_fixed_c = 8;
-+	disp_ttu_regs->qos_level_fixed_cur0 = 8;
-+	disp_ttu_regs->qos_ramp_disable_l = 0;
-+	disp_ttu_regs->qos_ramp_disable_c = 0;
-+	disp_ttu_regs->qos_ramp_disable_cur0 = 0;
-+
-+	disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
-+	ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
-+
-+	print__ttu_regs_st(mode_lib, *disp_ttu_regs);
-+	print__dlg_regs_st(mode_lib, *disp_dlg_regs);
-+}
-+
-+void dml_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
-+		display_dlg_regs_st *dlg_regs,
-+		display_ttu_regs_st *ttu_regs,
-+		display_e2e_pipe_params_st *e2e_pipe_param,
-+		const unsigned int num_pipes,
-+		const unsigned int pipe_idx,
-+		const bool cstate_en,
-+		const bool pstate_en,
-+		const bool vm_en,
-+		const bool ignore_viewport_pos,
-+		const bool immediate_flip_support)
-+{
-+	display_rq_params_st rq_param = {0};
-+	display_dlg_sys_params_st dlg_sys_param = {0};
-+
-+	// Get watermark and Tex.
-+	dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
-+	dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib,
-+			e2e_pipe_param,
-+			num_pipes);
-+	dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
-+	dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
-+	dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
-+	dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes);
-+	dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib,
-+			e2e_pipe_param,
-+			num_pipes);
-+	dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib,
-+			e2e_pipe_param,
-+			num_pipes);
-+	dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency
-+			/ dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated
-+
-+	print__dlg_sys_params_st(mode_lib, dlg_sys_param);
-+
-+	// system parameter calculation done
-+
-+	dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
-+	dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src);
-+	dml_rq_dlg_get_dlg_params(mode_lib,
-+			e2e_pipe_param,
-+			num_pipes,
-+			pipe_idx,
-+			dlg_regs,
-+			ttu_regs,
-+			rq_param.dlg,
-+			dlg_sys_param,
-+			cstate_en,
-+			pstate_en,
-+			vm_en,
-+			ignore_viewport_pos,
-+			immediate_flip_support);
-+	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
-+}
-+
-+void dml_rq_dlg_get_arb_params(struct display_mode_lib *mode_lib, display_arb_params_st *arb_param)
-+{
-+	memset(arb_param, 0, sizeof(*arb_param));
-+	arb_param->max_req_outstanding = 256;
-+	arb_param->min_req_outstanding = 68;
-+	arb_param->sat_level_us = 60;
-+}
-+
-+void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
-+		double *refcyc_per_req_delivery_pre_cur,
-+		double *refcyc_per_req_delivery_cur,
-+		double refclk_freq_in_mhz,
-+		double ref_freq_to_pix_freq,
-+		double hscale_pixel_rate_l,
-+		double hscl_ratio,
-+		double vratio_pre_l,
-+		double vratio_l,
-+		unsigned int cur_width,
-+		enum cursor_bpp cur_bpp)
-+{
-+	unsigned int cur_src_width = cur_width;
-+	unsigned int cur_req_size = 0;
-+	unsigned int cur_req_width = 0;
-+	double cur_width_ub = 0.0;
-+	double cur_req_per_width = 0.0;
-+	double hactive_cur = 0.0;
-+
-+	ASSERT(cur_src_width <= 256);
-+
-+	*refcyc_per_req_delivery_pre_cur = 0.0;
-+	*refcyc_per_req_delivery_cur = 0.0;
-+	if (cur_src_width > 0) {
-+		unsigned int cur_bit_per_pixel = 0;
-+
-+		if (cur_bpp == dm_cur_2bit) {
-+			cur_req_size = 64; // byte
-+			cur_bit_per_pixel = 2;
-+		} else { // 32bit
-+			cur_bit_per_pixel = 32;
-+			if (cur_src_width >= 1 && cur_src_width <= 16)
-+				cur_req_size = 64;
-+			else if (cur_src_width >= 17 && cur_src_width <= 31)
-+				cur_req_size = 128;
-+			else
-+				cur_req_size = 256;
-+		}
-+
-+		cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0);
-+		cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
-+				* (double) cur_req_width;
-+		cur_req_per_width = cur_width_ub / (double) cur_req_width;
-+		hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
-+
-+		if (vratio_pre_l <= 1.0) {
-+			*refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq
-+					/ (double) cur_req_per_width;
-+		} else {
-+			*refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz
-+					* (double) cur_src_width / hscale_pixel_rate_l
-+					/ (double) cur_req_per_width;
-+		}
-+
-+		ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
-+
-+		if (vratio_l <= 1.0) {
-+			*refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq
-+					/ (double) cur_req_per_width;
-+		} else {
-+			*refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz
-+					* (double) cur_src_width / hscale_pixel_rate_l
-+					/ (double) cur_req_per_width;
-+		}
-+
-+		dml_print("DML_DLG: %s: cur_req_width                     = %d\n",
-+				__func__,
-+				cur_req_width);
-+		dml_print("DML_DLG: %s: cur_width_ub                      = %3.2f\n",
-+				__func__,
-+				cur_width_ub);
-+		dml_print("DML_DLG: %s: cur_req_per_width                 = %3.2f\n",
-+				__func__,
-+				cur_req_per_width);
-+		dml_print("DML_DLG: %s: hactive_cur                       = %3.2f\n",
-+				__func__,
-+				hactive_cur);
-+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur   = %3.2f\n",
-+				__func__,
-+				*refcyc_per_req_delivery_pre_cur);
-+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur       = %3.2f\n",
-+				__func__,
-+				*refcyc_per_req_delivery_cur);
-+
-+		ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
-+	}
-+}
-+
-+unsigned int dml_rq_dlg_get_calculated_vstartup(struct display_mode_lib *mode_lib,
-+		display_e2e_pipe_params_st *e2e_pipe_param,
-+		const unsigned int num_pipes,
-+		const unsigned int pipe_idx)
-+{
-+	unsigned int vstartup_pipe[DC__NUM_PIPES__MAX];
-+	bool visited[DC__NUM_PIPES__MAX];
-+	unsigned int pipe_inst = 0;
-+	unsigned int i, j, k;
-+
-+	for (k = 0; k < num_pipes; ++k)
-+		visited[k] = false;
-+
-+	for (i = 0; i < num_pipes; i++) {
-+		if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) {
-+			unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp;
-+
-+			for (j = i; j < num_pipes; j++) {
-+				if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp
-+						&& e2e_pipe_param[j].pipe.src.is_hsplit
-+						&& !visited[j]) {
-+					vstartup_pipe[j] = get_vstartup_calculated(mode_lib,
-+							e2e_pipe_param,
-+							num_pipes,
-+							pipe_inst);
-+					visited[j] = true;
-+				}
-+			}
-+
-+			pipe_inst++;
-+		}
-+
-+		if (!visited[i]) {
-+			vstartup_pipe[i] = get_vstartup_calculated(mode_lib,
-+					e2e_pipe_param,
-+					num_pipes,
-+					pipe_inst);
-+			visited[i] = true;
-+			pipe_inst++;
-+		}
-+	}
-+
-+	return vstartup_pipe[pipe_idx];
-+
-+}
-+
-+void dml_rq_dlg_get_row_heights(struct display_mode_lib *mode_lib,
-+		unsigned int *o_dpte_row_height,
-+		unsigned int *o_meta_row_height,
-+		unsigned int vp_width,
-+		unsigned int data_pitch,
-+		int source_format,
-+		int tiling,
-+		int macro_tile_size,
-+		int source_scan,
-+		int is_chroma)
-+{
-+	display_data_rq_dlg_params_st rq_dlg_param;
-+	display_data_rq_misc_params_st rq_misc_param;
-+	display_data_rq_sizing_params_st rq_sizing_param;
-+
-+	get_meta_and_pte_attr(mode_lib,
-+			&rq_dlg_param,
-+			&rq_misc_param,
-+			&rq_sizing_param,
-+			vp_width,
-+			0, // dummy
-+			data_pitch,
-+			0, // dummy
-+			source_format,
-+			tiling,
-+			macro_tile_size,
-+			source_scan,
-+			is_chroma);
-+
-+	*o_dpte_row_height = rq_dlg_param.dpte_row_height;
-+	*o_meta_row_height = rq_dlg_param.meta_row_height;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.h.0130~	2017-12-14 06:39:58.427903576 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.h	2017-12-14 06:39:58.427903576 +0100
-@@ -0,0 +1,148 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DML2_DISPLAY_RQ_DLG_CALC_H__
-+#define __DML2_DISPLAY_RQ_DLG_CALC_H__
-+
-+#include "dml_common_defs.h"
-+#include "display_rq_dlg_helpers.h"
-+
-+struct display_mode_lib;
-+
-+// Function: dml_rq_dlg_get_rq_params
-+//  Calculate requestor related parameters that register definition agnostic
-+//  (i.e. this layer does try to separate real values from register definition)
-+// Input:
-+//  pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
-+// Output:
-+//  rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
-+//
-+void dml_rq_dlg_get_rq_params(
-+		struct display_mode_lib *mode_lib,
-+		display_rq_params_st *rq_param,
-+		const display_pipe_source_params_st pipe_src_param);
-+
-+// Function: dml_rq_dlg_get_rq_reg
-+//  Main entry point for test to get the register values out of this DML class.
-+//  This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
-+//  and then populate the rq_regs struct
-+// Input:
-+//  pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
-+// Output:
-+//  rq_regs - struct that holds all the RQ registers field value.
-+//            See also: <display_rq_regs_st>
-+void dml_rq_dlg_get_rq_reg(
-+		struct display_mode_lib *mode_lib,
-+		display_rq_regs_st *rq_regs,
-+		const display_pipe_source_params_st pipe_src_param);
-+
-+// Function: dml_rq_dlg_get_dlg_params
-+//  Calculate deadline related parameters
-+//
-+void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
-+		const display_e2e_pipe_params_st *e2e_pipe_param,
-+		const unsigned int num_pipes,
-+		const unsigned int pipe_idx,
-+		display_dlg_regs_st *disp_dlg_regs,
-+		display_ttu_regs_st *disp_ttu_regs,
-+		const display_rq_dlg_params_st rq_dlg_param,
-+		const display_dlg_sys_params_st dlg_sys_param,
-+		const bool cstate_en,
-+		const bool pstate_en,
-+		const bool vm_en,
-+		const bool ignore_viewport_pos,
-+		const bool immediate_flip_support);
-+
-+// Function: dml_rq_dlg_get_dlg_param_prefetch
-+//   For flip_bw programming guide change, now dml needs to calculate the flip_bytes and prefetch_bw
-+//   for ALL pipes and use this info to calculate the prefetch programming.
-+// Output: prefetch_param.prefetch_bw and flip_bytes
-+void dml_rq_dlg_get_dlg_params_prefetch(
-+		struct display_mode_lib *mode_lib,
-+		display_dlg_prefetch_param_st *prefetch_param,
-+		display_rq_dlg_params_st rq_dlg_param,
-+		display_dlg_sys_params_st dlg_sys_param,
-+		display_e2e_pipe_params_st e2e_pipe_param,
-+		const bool cstate_en,
-+		const bool pstate_en,
-+		const bool vm_en);
-+
-+// Function: dml_rq_dlg_get_dlg_reg
-+//   Calculate and return DLG and TTU register struct given the system setting
-+// Output:
-+//  dlg_regs - output DLG register struct
-+//  ttu_regs - output DLG TTU register struct
-+// Input:
-+//  e2e_pipe_param - "compacted" array of e2e pipe param struct
-+//  num_pipes - num of active "pipe" or "route"
-+//  pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
-+//  cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
-+//           Added for legacy or unrealistic timing tests.
-+void dml_rq_dlg_get_dlg_reg(
-+		struct display_mode_lib *mode_lib,
-+		display_dlg_regs_st *dlg_regs,
-+		display_ttu_regs_st *ttu_regs,
-+		display_e2e_pipe_params_st *e2e_pipe_param,
-+		const unsigned int num_pipes,
-+		const unsigned int pipe_idx,
-+		const bool cstate_en,
-+		const bool pstate_en,
-+		const bool vm_en,
-+		const bool ignore_viewport_pos,
-+		const bool immediate_flip_support);
-+
-+// Function: dml_rq_dlg_get_calculated_vstartup
-+//   Calculate and return vstartup
-+// Output:
-+//  unsigned int vstartup
-+// Input:
-+//  e2e_pipe_param - "compacted" array of e2e pipe param struct
-+//  num_pipes - num of active "pipe" or "route"
-+//  pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
-+// NOTE: this MUST be called after setting the prefetch mode!
-+unsigned int dml_rq_dlg_get_calculated_vstartup(
-+		struct display_mode_lib *mode_lib,
-+		display_e2e_pipe_params_st *e2e_pipe_param,
-+		const unsigned int num_pipes,
-+		const unsigned int pipe_idx);
-+
-+// Function: dml_rq_dlg_get_row_heights
-+//  Calculate dpte and meta row heights
-+void dml_rq_dlg_get_row_heights(
-+		struct display_mode_lib *mode_lib,
-+		unsigned int *o_dpte_row_height,
-+		unsigned int *o_meta_row_height,
-+		unsigned int vp_width,
-+		unsigned int data_pitch,
-+		int source_format,
-+		int tiling,
-+		int macro_tile_size,
-+		int source_scan,
-+		int is_chroma);
-+
-+// Function: dml_rq_dlg_get_arb_params
-+void dml_rq_dlg_get_arb_params(struct display_mode_lib *mode_lib, display_arb_params_st *arb_param);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c.0130~	2017-12-14 06:39:58.427903576 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c	2017-12-14 06:39:58.427903576 +0100
-@@ -0,0 +1,392 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "display_rq_dlg_helpers.h"
-+
-+void print__rq_params_st(struct display_mode_lib *mode_lib, display_rq_params_st rq_param)
-+{
-+	dml_print("DML_RQ_DLG_CALC: ***************************\n");
-+	dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST\n");
-+	dml_print("DML_RQ_DLG_CALC:  <LUMA>\n");
-+	print__data_rq_sizing_params_st(mode_lib, rq_param.sizing.rq_l);
-+	dml_print("DML_RQ_DLG_CALC:  <CHROMA> ===\n");
-+	print__data_rq_sizing_params_st(mode_lib, rq_param.sizing.rq_c);
-+
-+	dml_print("DML_RQ_DLG_CALC: <LUMA>\n");
-+	print__data_rq_dlg_params_st(mode_lib, rq_param.dlg.rq_l);
-+	dml_print("DML_RQ_DLG_CALC: <CHROMA>\n");
-+	print__data_rq_dlg_params_st(mode_lib, rq_param.dlg.rq_c);
-+
-+	dml_print("DML_RQ_DLG_CALC: <LUMA>\n");
-+	print__data_rq_misc_params_st(mode_lib, rq_param.misc.rq_l);
-+	dml_print("DML_RQ_DLG_CALC: <CHROMA>\n");
-+	print__data_rq_misc_params_st(mode_lib, rq_param.misc.rq_c);
-+	dml_print("DML_RQ_DLG_CALC: ***************************\n");
-+}
-+
-+void print__data_rq_sizing_params_st(struct display_mode_lib *mode_lib, display_data_rq_sizing_params_st rq_sizing)
-+{
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+	dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST\n");
-+	dml_print("DML_RQ_DLG_CALC:    chunk_bytes           = %0d\n", rq_sizing.chunk_bytes);
-+	dml_print("DML_RQ_DLG_CALC:    min_chunk_bytes       = %0d\n", rq_sizing.min_chunk_bytes);
-+	dml_print("DML_RQ_DLG_CALC:    meta_chunk_bytes      = %0d\n", rq_sizing.meta_chunk_bytes);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    min_meta_chunk_bytes  = %0d\n",
-+			rq_sizing.min_meta_chunk_bytes);
-+	dml_print("DML_RQ_DLG_CALC:    mpte_group_bytes      = %0d\n", rq_sizing.mpte_group_bytes);
-+	dml_print("DML_RQ_DLG_CALC:    dpte_group_bytes      = %0d\n", rq_sizing.dpte_group_bytes);
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+}
-+
-+void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st rq_dlg_param)
-+{
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+	dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST\n");
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    swath_width_ub              = %0d\n",
-+			rq_dlg_param.swath_width_ub);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    swath_height                = %0d\n",
-+			rq_dlg_param.swath_height);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    req_per_swath_ub            = %0d\n",
-+			rq_dlg_param.req_per_swath_ub);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    meta_pte_bytes_per_frame_ub = %0d\n",
-+			rq_dlg_param.meta_pte_bytes_per_frame_ub);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dpte_req_per_row_ub         = %0d\n",
-+			rq_dlg_param.dpte_req_per_row_ub);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dpte_groups_per_row_ub      = %0d\n",
-+			rq_dlg_param.dpte_groups_per_row_ub);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dpte_row_height             = %0d\n",
-+			rq_dlg_param.dpte_row_height);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dpte_bytes_per_row_ub       = %0d\n",
-+			rq_dlg_param.dpte_bytes_per_row_ub);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    meta_chunks_per_row_ub      = %0d\n",
-+			rq_dlg_param.meta_chunks_per_row_ub);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    meta_req_per_row_ub         = %0d\n",
-+			rq_dlg_param.meta_req_per_row_ub);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    meta_row_height             = %0d\n",
-+			rq_dlg_param.meta_row_height);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    meta_bytes_per_row_ub       = %0d\n",
-+			rq_dlg_param.meta_bytes_per_row_ub);
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+}
-+
-+void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, display_data_rq_misc_params_st rq_misc_param)
-+{
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+	dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST\n");
-+	dml_print(
-+			"DML_RQ_DLG_CALC:     full_swath_bytes   = %0d\n",
-+			rq_misc_param.full_swath_bytes);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:     stored_swath_bytes = %0d\n",
-+			rq_misc_param.stored_swath_bytes);
-+	dml_print("DML_RQ_DLG_CALC:     blk256_width       = %0d\n", rq_misc_param.blk256_width);
-+	dml_print("DML_RQ_DLG_CALC:     blk256_height      = %0d\n", rq_misc_param.blk256_height);
-+	dml_print("DML_RQ_DLG_CALC:     req_width          = %0d\n", rq_misc_param.req_width);
-+	dml_print("DML_RQ_DLG_CALC:     req_height         = %0d\n", rq_misc_param.req_height);
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+}
-+
-+void print__rq_dlg_params_st(struct display_mode_lib *mode_lib, display_rq_dlg_params_st rq_dlg_param)
-+{
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+	dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n");
-+	dml_print("DML_RQ_DLG_CALC:  <LUMA>\n");
-+	print__data_rq_dlg_params_st(mode_lib, rq_dlg_param.rq_l);
-+	dml_print("DML_RQ_DLG_CALC:  <CHROMA>\n");
-+	print__data_rq_dlg_params_st(mode_lib, rq_dlg_param.rq_c);
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+}
-+
-+void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, display_dlg_sys_params_st dlg_sys_param)
-+{
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+	dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST\n");
-+	dml_print("DML_RQ_DLG_CALC:    t_mclk_wm_us         = %3.2f\n", dlg_sys_param.t_mclk_wm_us);
-+	dml_print("DML_RQ_DLG_CALC:    t_urg_wm_us          = %3.2f\n", dlg_sys_param.t_urg_wm_us);
-+	dml_print("DML_RQ_DLG_CALC:    t_sr_wm_us           = %3.2f\n", dlg_sys_param.t_sr_wm_us);
-+	dml_print("DML_RQ_DLG_CALC:    t_extra_us           = %3.2f\n", dlg_sys_param.t_extra_us);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    t_srx_delay_us       = %3.2f\n",
-+			dlg_sys_param.t_srx_delay_us);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    deepsleep_dcfclk_mhz = %3.2f\n",
-+			dlg_sys_param.deepsleep_dcfclk_mhz);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    total_flip_bw        = %3.2f\n",
-+			dlg_sys_param.total_flip_bw);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    total_flip_bytes     = %i\n",
-+			dlg_sys_param.total_flip_bytes);
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+}
-+
-+void print__data_rq_regs_st(struct display_mode_lib *mode_lib, display_data_rq_regs_st rq_regs)
-+{
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+	dml_print("DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST\n");
-+	dml_print("DML_RQ_DLG_CALC:    chunk_size              = 0x%0x\n", rq_regs.chunk_size);
-+	dml_print("DML_RQ_DLG_CALC:    min_chunk_size          = 0x%0x\n", rq_regs.min_chunk_size);
-+	dml_print("DML_RQ_DLG_CALC:    meta_chunk_size         = 0x%0x\n", rq_regs.meta_chunk_size);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    min_meta_chunk_size     = 0x%0x\n",
-+			rq_regs.min_meta_chunk_size);
-+	dml_print("DML_RQ_DLG_CALC:    dpte_group_size         = 0x%0x\n", rq_regs.dpte_group_size);
-+	dml_print("DML_RQ_DLG_CALC:    mpte_group_size         = 0x%0x\n", rq_regs.mpte_group_size);
-+	dml_print("DML_RQ_DLG_CALC:    swath_height            = 0x%0x\n", rq_regs.swath_height);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    pte_row_height_linear   = 0x%0x\n",
-+			rq_regs.pte_row_height_linear);
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+}
-+
-+void print__rq_regs_st(struct display_mode_lib *mode_lib, display_rq_regs_st rq_regs)
-+{
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+	dml_print("DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST\n");
-+	dml_print("DML_RQ_DLG_CALC:  <LUMA>\n");
-+	print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_l);
-+	dml_print("DML_RQ_DLG_CALC:  <CHROMA>\n");
-+	print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_c);
-+	dml_print("DML_RQ_DLG_CALC:    drq_expansion_mode  = 0x%0x\n", rq_regs.drq_expansion_mode);
-+	dml_print("DML_RQ_DLG_CALC:    prq_expansion_mode  = 0x%0x\n", rq_regs.prq_expansion_mode);
-+	dml_print("DML_RQ_DLG_CALC:    mrq_expansion_mode  = 0x%0x\n", rq_regs.mrq_expansion_mode);
-+	dml_print("DML_RQ_DLG_CALC:    crq_expansion_mode  = 0x%0x\n", rq_regs.crq_expansion_mode);
-+	dml_print("DML_RQ_DLG_CALC:    plane1_base_address = 0x%0x\n", rq_regs.plane1_base_address);
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+}
-+
-+void print__dlg_regs_st(struct display_mode_lib *mode_lib, display_dlg_regs_st dlg_regs)
-+{
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+	dml_print("DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST\n");
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_h_blank_end              = 0x%0x\n",
-+			dlg_regs.refcyc_h_blank_end);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dlg_vblank_end                  = 0x%0x\n",
-+			dlg_regs.dlg_vblank_end);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    min_dst_y_next_start            = 0x%0x\n",
-+			dlg_regs.min_dst_y_next_start);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_htotal               = 0x%0x\n",
-+			dlg_regs.refcyc_per_htotal);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_x_after_scaler           = 0x%0x\n",
-+			dlg_regs.refcyc_x_after_scaler);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dst_y_after_scaler              = 0x%0x\n",
-+			dlg_regs.dst_y_after_scaler);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dst_y_prefetch                  = 0x%0x\n",
-+			dlg_regs.dst_y_prefetch);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dst_y_per_vm_vblank             = 0x%0x\n",
-+			dlg_regs.dst_y_per_vm_vblank);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dst_y_per_row_vblank            = 0x%0x\n",
-+			dlg_regs.dst_y_per_row_vblank);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dst_y_per_vm_flip               = 0x%0x\n",
-+			dlg_regs.dst_y_per_vm_flip);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dst_y_per_row_flip              = 0x%0x\n",
-+			dlg_regs.dst_y_per_row_flip);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    ref_freq_to_pix_freq            = 0x%0x\n",
-+			dlg_regs.ref_freq_to_pix_freq);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    vratio_prefetch                 = 0x%0x\n",
-+			dlg_regs.vratio_prefetch);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    vratio_prefetch_c               = 0x%0x\n",
-+			dlg_regs.vratio_prefetch_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_pte_group_vblank_l   = 0x%0x\n",
-+			dlg_regs.refcyc_per_pte_group_vblank_l);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_pte_group_vblank_c   = 0x%0x\n",
-+			dlg_regs.refcyc_per_pte_group_vblank_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_vblank_l  = 0x%0x\n",
-+			dlg_regs.refcyc_per_meta_chunk_vblank_l);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_vblank_c  = 0x%0x\n",
-+			dlg_regs.refcyc_per_meta_chunk_vblank_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_pte_group_flip_l     = 0x%0x\n",
-+			dlg_regs.refcyc_per_pte_group_flip_l);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_pte_group_flip_c     = 0x%0x\n",
-+			dlg_regs.refcyc_per_pte_group_flip_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_flip_l    = 0x%0x\n",
-+			dlg_regs.refcyc_per_meta_chunk_flip_l);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_flip_c    = 0x%0x\n",
-+			dlg_regs.refcyc_per_meta_chunk_flip_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dst_y_per_pte_row_nom_l         = 0x%0x\n",
-+			dlg_regs.dst_y_per_pte_row_nom_l);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dst_y_per_pte_row_nom_c         = 0x%0x\n",
-+			dlg_regs.dst_y_per_pte_row_nom_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_pte_group_nom_l      = 0x%0x\n",
-+			dlg_regs.refcyc_per_pte_group_nom_l);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_pte_group_nom_c      = 0x%0x\n",
-+			dlg_regs.refcyc_per_pte_group_nom_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dst_y_per_meta_row_nom_l        = 0x%0x\n",
-+			dlg_regs.dst_y_per_meta_row_nom_l);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dst_y_per_meta_row_nom_c        = 0x%0x\n",
-+			dlg_regs.dst_y_per_meta_row_nom_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_nom_l     = 0x%0x\n",
-+			dlg_regs.refcyc_per_meta_chunk_nom_l);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_meta_chunk_nom_c     = 0x%0x\n",
-+			dlg_regs.refcyc_per_meta_chunk_nom_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_line_delivery_pre_l  = 0x%0x\n",
-+			dlg_regs.refcyc_per_line_delivery_pre_l);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_line_delivery_pre_c  = 0x%0x\n",
-+			dlg_regs.refcyc_per_line_delivery_pre_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_line_delivery_l      = 0x%0x\n",
-+			dlg_regs.refcyc_per_line_delivery_l);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_line_delivery_c      = 0x%0x\n",
-+			dlg_regs.refcyc_per_line_delivery_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    chunk_hdl_adjust_cur0           = 0x%0x\n",
-+			dlg_regs.chunk_hdl_adjust_cur0);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dst_y_offset_cur1               = 0x%0x\n",
-+			dlg_regs.dst_y_offset_cur1);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    chunk_hdl_adjust_cur1           = 0x%0x\n",
-+			dlg_regs.chunk_hdl_adjust_cur1);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    vready_after_vcount0            = 0x%0x\n",
-+			dlg_regs.vready_after_vcount0);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    dst_y_delta_drq_limit           = 0x%0x\n",
-+			dlg_regs.dst_y_delta_drq_limit);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    xfc_reg_transfer_delay          = 0x%0x\n",
-+			dlg_regs.xfc_reg_transfer_delay);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    xfc_reg_precharge_delay         = 0x%0x\n",
-+			dlg_regs.xfc_reg_precharge_delay);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    xfc_reg_remote_surface_flip_latency = 0x%0x\n",
-+			dlg_regs.xfc_reg_remote_surface_flip_latency);
-+
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+}
-+
-+void print__ttu_regs_st(struct display_mode_lib *mode_lib, display_ttu_regs_st ttu_regs)
-+{
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+	dml_print("DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST\n");
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    qos_level_low_wm                  = 0x%0x\n",
-+			ttu_regs.qos_level_low_wm);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    qos_level_high_wm                 = 0x%0x\n",
-+			ttu_regs.qos_level_high_wm);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    min_ttu_vblank                    = 0x%0x\n",
-+			ttu_regs.min_ttu_vblank);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    qos_level_flip                    = 0x%0x\n",
-+			ttu_regs.qos_level_flip);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_l     = 0x%0x\n",
-+			ttu_regs.refcyc_per_req_delivery_pre_l);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_l         = 0x%0x\n",
-+			ttu_regs.refcyc_per_req_delivery_l);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_c     = 0x%0x\n",
-+			ttu_regs.refcyc_per_req_delivery_pre_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_c         = 0x%0x\n",
-+			ttu_regs.refcyc_per_req_delivery_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_cur0      = 0x%0x\n",
-+			ttu_regs.refcyc_per_req_delivery_cur0);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_cur0  = 0x%0x\n",
-+			ttu_regs.refcyc_per_req_delivery_pre_cur0);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_cur1      = 0x%0x\n",
-+			ttu_regs.refcyc_per_req_delivery_cur1);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    refcyc_per_req_delivery_pre_cur1  = 0x%0x\n",
-+			ttu_regs.refcyc_per_req_delivery_pre_cur1);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    qos_level_fixed_l                 = 0x%0x\n",
-+			ttu_regs.qos_level_fixed_l);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    qos_ramp_disable_l                = 0x%0x\n",
-+			ttu_regs.qos_ramp_disable_l);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    qos_level_fixed_c                 = 0x%0x\n",
-+			ttu_regs.qos_level_fixed_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    qos_ramp_disable_c                = 0x%0x\n",
-+			ttu_regs.qos_ramp_disable_c);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    qos_level_fixed_cur0              = 0x%0x\n",
-+			ttu_regs.qos_level_fixed_cur0);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    qos_ramp_disable_cur0             = 0x%0x\n",
-+			ttu_regs.qos_ramp_disable_cur0);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    qos_level_fixed_cur1              = 0x%0x\n",
-+			ttu_regs.qos_level_fixed_cur1);
-+	dml_print(
-+			"DML_RQ_DLG_CALC:    qos_ramp_disable_cur1             = 0x%0x\n",
-+			ttu_regs.qos_ramp_disable_cur1);
-+	dml_print("DML_RQ_DLG_CALC: =====================================\n");
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h.0130~	2017-12-14 06:39:58.427903576 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h	2017-12-14 06:39:58.427903576 +0100
-@@ -0,0 +1,47 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DISPLAY_RQ_DLG_HELPERS_H__
-+#define __DISPLAY_RQ_DLG_HELPERS_H__
-+
-+#include "dml_common_defs.h"
-+#include "display_mode_lib.h"
-+
-+/* Function: Printer functions
-+ *  Print various struct
-+ */
-+void print__rq_params_st(struct display_mode_lib *mode_lib, display_rq_params_st rq_param);
-+void print__data_rq_sizing_params_st(struct display_mode_lib *mode_lib, display_data_rq_sizing_params_st rq_sizing);
-+void print__data_rq_dlg_params_st(struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st rq_dlg_param);
-+void print__data_rq_misc_params_st(struct display_mode_lib *mode_lib, display_data_rq_misc_params_st rq_misc_param);
-+void print__rq_dlg_params_st(struct display_mode_lib *mode_lib, display_rq_dlg_params_st rq_dlg_param);
-+void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, display_dlg_sys_params_st dlg_sys_param);
-+
-+void print__data_rq_regs_st(struct display_mode_lib *mode_lib, display_data_rq_regs_st data_rq_regs);
-+void print__rq_regs_st(struct display_mode_lib *mode_lib, display_rq_regs_st rq_regs);
-+void print__dlg_regs_st(struct display_mode_lib *mode_lib, display_dlg_regs_st dlg_regs);
-+void print__ttu_regs_st(struct display_mode_lib *mode_lib, display_ttu_regs_st ttu_regs);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c.0130~	2017-12-14 06:39:58.428903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c	2017-12-14 06:39:58.428903577 +0100
-@@ -0,0 +1,1905 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dml1_display_rq_dlg_calc.h"
-+#include "display_mode_lib.h"
-+
-+#include "dml_inline_defs.h"
-+
-+static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
-+{
-+	unsigned int ret_val = 0;
-+
-+	if (source_format == dm_444_16) {
-+		if (!is_chroma)
-+			ret_val = 2;
-+	} else if (source_format == dm_444_32) {
-+		if (!is_chroma)
-+			ret_val = 4;
-+	} else if (source_format == dm_444_64) {
-+		if (!is_chroma)
-+			ret_val = 8;
-+	} else if (source_format == dm_420_8) {
-+		if (is_chroma)
-+			ret_val = 2;
-+		else
-+			ret_val = 1;
-+	} else if (source_format == dm_420_10) {
-+		if (is_chroma)
-+			ret_val = 4;
-+		else
-+			ret_val = 2;
-+	}
-+	return ret_val;
-+}
-+
-+static bool is_dual_plane(enum source_format_class source_format)
-+{
-+	bool ret_val = 0;
-+
-+	if ((source_format == dm_420_8) || (source_format == dm_420_10))
-+		ret_val = 1;
-+
-+	return ret_val;
-+}
-+
-+static void get_blk256_size(
-+		unsigned int *blk256_width,
-+		unsigned int *blk256_height,
-+		unsigned int bytes_per_element)
-+{
-+	if (bytes_per_element == 1) {
-+		*blk256_width = 16;
-+		*blk256_height = 16;
-+	} else if (bytes_per_element == 2) {
-+		*blk256_width = 16;
-+		*blk256_height = 8;
-+	} else if (bytes_per_element == 4) {
-+		*blk256_width = 8;
-+		*blk256_height = 8;
-+	} else if (bytes_per_element == 8) {
-+		*blk256_width = 8;
-+		*blk256_height = 4;
-+	}
-+}
-+
-+static double get_refcyc_per_delivery(
-+		struct display_mode_lib *mode_lib,
-+		double refclk_freq_in_mhz,
-+		double pclk_freq_in_mhz,
-+		unsigned int recout_width,
-+		double vratio,
-+		double hscale_pixel_rate,
-+		unsigned int delivery_width,
-+		unsigned int req_per_swath_ub)
-+{
-+	double refcyc_per_delivery = 0.0;
-+
-+	if (vratio <= 1.0) {
-+		refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width
-+				/ pclk_freq_in_mhz / (double) req_per_swath_ub;
-+	} else {
-+		refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width
-+				/ (double) hscale_pixel_rate / (double) req_per_swath_ub;
-+	}
-+
-+	DTRACE("DLG: %s: refclk_freq_in_mhz = %3.2f", __func__, refclk_freq_in_mhz);
-+	DTRACE("DLG: %s: pclk_freq_in_mhz   = %3.2f", __func__, pclk_freq_in_mhz);
-+	DTRACE("DLG: %s: recout_width       = %d", __func__, recout_width);
-+	DTRACE("DLG: %s: vratio             = %3.2f", __func__, vratio);
-+	DTRACE("DLG: %s: req_per_swath_ub   = %d", __func__, req_per_swath_ub);
-+	DTRACE("DLG: %s: refcyc_per_delivery= %3.2f", __func__, refcyc_per_delivery);
-+
-+	return refcyc_per_delivery;
-+
-+}
-+
-+static double get_vratio_pre(
-+		struct display_mode_lib *mode_lib,
-+		unsigned int max_num_sw,
-+		unsigned int max_partial_sw,
-+		unsigned int swath_height,
-+		double vinit,
-+		double l_sw)
-+{
-+	double prefill = dml_floor(vinit, 1);
-+	double vratio_pre = 1.0;
-+
-+	vratio_pre = (max_num_sw * swath_height + max_partial_sw) / l_sw;
-+
-+	if (swath_height > 4) {
-+		double tmp0 = (max_num_sw * swath_height) / (l_sw - (prefill - 3.0) / 2.0);
-+
-+		if (tmp0 > vratio_pre)
-+			vratio_pre = tmp0;
-+	}
-+
-+	DTRACE("DLG: %s: max_num_sw        = %0d", __func__, max_num_sw);
-+	DTRACE("DLG: %s: max_partial_sw    = %0d", __func__, max_partial_sw);
-+	DTRACE("DLG: %s: swath_height      = %0d", __func__, swath_height);
-+	DTRACE("DLG: %s: vinit             = %3.2f", __func__, vinit);
-+	DTRACE("DLG: %s: vratio_pre        = %3.2f", __func__, vratio_pre);
-+
-+	if (vratio_pre < 1.0) {
-+		DTRACE("WARNING_DLG: %s:  vratio_pre=%3.2f < 1.0, set to 1.0", __func__, vratio_pre);
-+		vratio_pre = 1.0;
-+	}
-+
-+	if (vratio_pre > 4.0) {
-+		DTRACE(
-+				"WARNING_DLG: %s:  vratio_pre=%3.2f > 4.0 (max scaling ratio). set to 4.0",
-+				__func__,
-+				vratio_pre);
-+		vratio_pre = 4.0;
-+	}
-+
-+	return vratio_pre;
-+}
-+
-+static void get_swath_need(
-+		struct display_mode_lib *mode_lib,
-+		unsigned int *max_num_sw,
-+		unsigned int *max_partial_sw,
-+		unsigned int swath_height,
-+		double vinit)
-+{
-+	double prefill = dml_floor(vinit, 1);
-+	unsigned int max_partial_sw_int;
-+
-+	DTRACE("DLG: %s: swath_height      = %0d", __func__, swath_height);
-+	DTRACE("DLG: %s: vinit             = %3.2f", __func__, vinit);
-+
-+	ASSERT(prefill > 0.0 && prefill <= 8.0);
-+
-+	*max_num_sw = (unsigned int) (dml_ceil((prefill - 1.0) / (double) swath_height, 1) + 1.0); /* prefill has to be >= 1 */
-+	max_partial_sw_int =
-+			(prefill == 1) ?
-+					(swath_height - 1) :
-+					((unsigned int) (prefill - 2.0) % swath_height);
-+	*max_partial_sw = (max_partial_sw_int < 1) ? 1 : max_partial_sw_int; /* ensure minimum of 1 is used */
-+
-+	DTRACE("DLG: %s: max_num_sw        = %0d", __func__, *max_num_sw);
-+	DTRACE("DLG: %s: max_partial_sw    = %0d", __func__, *max_partial_sw);
-+}
-+
-+static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
-+{
-+	if (tile_size == dm_256k_tile)
-+		return (256 * 1024);
-+	else if (tile_size == dm_64k_tile)
-+		return (64 * 1024);
-+	else
-+		return (4 * 1024);
-+}
-+
-+static void extract_rq_sizing_regs(
-+		struct display_mode_lib *mode_lib,
-+		struct _vcs_dpi_display_data_rq_regs_st *rq_regs,
-+		const struct _vcs_dpi_display_data_rq_sizing_params_st rq_sizing)
-+{
-+	DTRACE("DLG: %s: rq_sizing param", __func__);
-+	print__data_rq_sizing_params_st(mode_lib, rq_sizing);
-+
-+	rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
-+
-+	if (rq_sizing.min_chunk_bytes == 0)
-+		rq_regs->min_chunk_size = 0;
-+	else
-+		rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
-+
-+	rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
-+	if (rq_sizing.min_meta_chunk_bytes == 0)
-+		rq_regs->min_meta_chunk_size = 0;
-+	else
-+		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
-+
-+	rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
-+	rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
-+}
-+
-+void dml1_extract_rq_regs(
-+		struct display_mode_lib *mode_lib,
-+		struct _vcs_dpi_display_rq_regs_st *rq_regs,
-+		const struct _vcs_dpi_display_rq_params_st rq_param)
-+{
-+	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
-+	unsigned int detile_buf_plane1_addr = 0;
-+
-+	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
-+	if (rq_param.yuv420)
-+		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
-+
-+	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
-+	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
-+
-+	/* FIXME: take the max between luma, chroma chunk size?
-+	 * okay for now, as we are setting chunk_bytes to 8kb anyways
-+	 */
-+	if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { /*32kb */
-+		rq_regs->drq_expansion_mode = 0;
-+	} else {
-+		rq_regs->drq_expansion_mode = 2;
-+	}
-+	rq_regs->prq_expansion_mode = 1;
-+	rq_regs->mrq_expansion_mode = 1;
-+	rq_regs->crq_expansion_mode = 1;
-+
-+	if (rq_param.yuv420) {
-+		if ((double) rq_param.misc.rq_l.stored_swath_bytes
-+				/ (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {
-+			detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); /* half to chroma */
-+		} else {
-+			detile_buf_plane1_addr = dml_round_to_multiple(
-+					(unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
-+					256,
-+					0) / 64.0; /* 2/3 to chroma */
-+		}
-+	}
-+	rq_regs->plane1_base_address = detile_buf_plane1_addr;
-+}
-+
-+static void handle_det_buf_split(
-+		struct display_mode_lib *mode_lib,
-+		struct _vcs_dpi_display_rq_params_st *rq_param,
-+		const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param)
-+{
-+	unsigned int total_swath_bytes = 0;
-+	unsigned int swath_bytes_l = 0;
-+	unsigned int swath_bytes_c = 0;
-+	unsigned int full_swath_bytes_packed_l = 0;
-+	unsigned int full_swath_bytes_packed_c = 0;
-+	bool req128_l = 0;
-+	bool req128_c = 0;
-+	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
-+	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
-+	unsigned int log2_swath_height_l = 0;
-+	unsigned int log2_swath_height_c = 0;
-+	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
-+
-+	full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
-+	full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
-+
-+	if (rq_param->yuv420_10bpc) {
-+		full_swath_bytes_packed_l = dml_round_to_multiple(
-+				rq_param->misc.rq_l.full_swath_bytes * 2 / 3,
-+				256,
-+				1) + 256;
-+		full_swath_bytes_packed_c = dml_round_to_multiple(
-+				rq_param->misc.rq_c.full_swath_bytes * 2 / 3,
-+				256,
-+				1) + 256;
-+	}
-+
-+	if (rq_param->yuv420) {
-+		total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
-+
-+		if (total_swath_bytes <= detile_buf_size_in_bytes) { /*full 256b request */
-+			req128_l = 0;
-+			req128_c = 0;
-+			swath_bytes_l = full_swath_bytes_packed_l;
-+			swath_bytes_c = full_swath_bytes_packed_c;
-+		} else { /*128b request (for luma only for yuv420 8bpc) */
-+			req128_l = 1;
-+			req128_c = 0;
-+			swath_bytes_l = full_swath_bytes_packed_l / 2;
-+			swath_bytes_c = full_swath_bytes_packed_c;
-+		}
-+
-+		/* Bug workaround, luma and chroma req size needs to be the same. (see: DEGVIDCN10-137)
-+		 * TODO: Remove after rtl fix
-+		 */
-+		if (req128_l == 1) {
-+			req128_c = 1;
-+			DTRACE("DLG: %s: bug workaround DEGVIDCN10-137", __func__);
-+		}
-+
-+		/* Note: assumption, the config that pass in will fit into
-+		 *       the detiled buffer.
-+		 */
-+	} else {
-+		total_swath_bytes = 2 * full_swath_bytes_packed_l;
-+
-+		if (total_swath_bytes <= detile_buf_size_in_bytes)
-+			req128_l = 0;
-+		else
-+			req128_l = 1;
-+
-+		swath_bytes_l = total_swath_bytes;
-+		swath_bytes_c = 0;
-+	}
-+	rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
-+	rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
-+
-+	if (surf_linear) {
-+		log2_swath_height_l = 0;
-+		log2_swath_height_c = 0;
-+	} else if (!surf_vert) {
-+		log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
-+		log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
-+	} else {
-+		log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
-+		log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
-+	}
-+	rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
-+	rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
-+
-+	DTRACE("DLG: %s: req128_l = %0d", __func__, req128_l);
-+	DTRACE("DLG: %s: req128_c = %0d", __func__, req128_c);
-+	DTRACE("DLG: %s: full_swath_bytes_packed_l = %0d", __func__, full_swath_bytes_packed_l);
-+	DTRACE("DLG: %s: full_swath_bytes_packed_c = %0d", __func__, full_swath_bytes_packed_c);
-+}
-+
-+/* Need refactor. */
-+static void dml1_rq_dlg_get_row_heights(
-+		struct display_mode_lib *mode_lib,
-+		unsigned int *o_dpte_row_height,
-+		unsigned int *o_meta_row_height,
-+		unsigned int vp_width,
-+		unsigned int data_pitch,
-+		int source_format,
-+		int tiling,
-+		int macro_tile_size,
-+		int source_scan,
-+		int is_chroma)
-+{
-+	bool surf_linear = (tiling == dm_sw_linear);
-+	bool surf_vert = (source_scan == dm_vert);
-+
-+	unsigned int bytes_per_element = get_bytes_per_element(
-+			(enum source_format_class) source_format,
-+			is_chroma);
-+	unsigned int log2_bytes_per_element = dml_log2(bytes_per_element);
-+	unsigned int blk256_width = 0;
-+	unsigned int blk256_height = 0;
-+
-+	unsigned int log2_blk256_height;
-+	unsigned int blk_bytes;
-+	unsigned int log2_blk_bytes;
-+	unsigned int log2_blk_height;
-+	unsigned int log2_blk_width;
-+	unsigned int log2_meta_req_bytes;
-+	unsigned int log2_meta_req_height;
-+	unsigned int log2_meta_req_width;
-+	unsigned int log2_meta_row_height;
-+	unsigned int log2_vmpg_bytes;
-+	unsigned int dpte_buf_in_pte_reqs;
-+	unsigned int log2_vmpg_height;
-+	unsigned int log2_vmpg_width;
-+	unsigned int log2_dpte_req_height_ptes;
-+	unsigned int log2_dpte_req_width_ptes;
-+	unsigned int log2_dpte_req_height;
-+	unsigned int log2_dpte_req_width;
-+	unsigned int log2_dpte_row_height_linear;
-+	unsigned int log2_dpte_row_height;
-+	unsigned int dpte_req_width;
-+
-+	if (surf_linear) {
-+		blk256_width = 256;
-+		blk256_height = 1;
-+	} else {
-+		get_blk256_size(&blk256_width, &blk256_height, bytes_per_element);
-+	}
-+
-+	log2_blk256_height = dml_log2((double) blk256_height);
-+	blk_bytes = surf_linear ?
-+			256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
-+	log2_blk_bytes = dml_log2((double) blk_bytes);
-+	log2_blk_height = 0;
-+	log2_blk_width = 0;
-+
-+	/* remember log rule
-+	 * "+" in log is multiply
-+	 * "-" in log is divide
-+	 * "/2" is like square root
-+	 * blk is vertical biased
-+	 */
-+	if (tiling != dm_sw_linear)
-+		log2_blk_height = log2_blk256_height
-+				+ dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
-+	else
-+		log2_blk_height = 0; /* blk height of 1 */
-+
-+	log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
-+
-+	/* ------- */
-+	/* meta    */
-+	/* ------- */
-+	log2_meta_req_bytes = 6; /* meta request is 64b and is 8x8byte meta element */
-+
-+	/* each 64b meta request for dcn is 8x8 meta elements and
-+	 * a meta element covers one 256b block of the the data surface.
-+	 */
-+	log2_meta_req_height = log2_blk256_height + 3; /* meta req is 8x8 */
-+	log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
-+			- log2_meta_req_height;
-+	log2_meta_row_height = 0;
-+
-+	/* the dimensions of a meta row are meta_row_width x meta_row_height in elements.
-+	 * calculate upper bound of the meta_row_width
-+	 */
-+	if (!surf_vert)
-+		log2_meta_row_height = log2_meta_req_height;
-+	else
-+		log2_meta_row_height = log2_meta_req_width;
-+
-+	*o_meta_row_height = 1 << log2_meta_row_height;
-+
-+	/* ------ */
-+	/* dpte   */
-+	/* ------ */
-+	log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
-+	dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs;
-+
-+	log2_vmpg_height = 0;
-+	log2_vmpg_width = 0;
-+	log2_dpte_req_height_ptes = 0;
-+	log2_dpte_req_width_ptes = 0;
-+	log2_dpte_req_height = 0;
-+	log2_dpte_req_width = 0;
-+	log2_dpte_row_height_linear = 0;
-+	log2_dpte_row_height = 0;
-+	dpte_req_width = 0; /* 64b dpte req width in data element */
-+
-+	if (surf_linear)
-+		log2_vmpg_height = 0; /* one line high */
-+	else
-+		log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
-+	log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
-+
-+	/* only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. */
-+	if (log2_blk_bytes <= log2_vmpg_bytes)
-+		log2_dpte_req_height_ptes = 0;
-+	else if (log2_blk_height - log2_vmpg_height >= 2)
-+		log2_dpte_req_height_ptes = 2;
-+	else
-+		log2_dpte_req_height_ptes = log2_blk_height - log2_vmpg_height;
-+	log2_dpte_req_width_ptes = 3 - log2_dpte_req_height_ptes;
-+
-+	ASSERT((log2_dpte_req_width_ptes == 3 && log2_dpte_req_height_ptes == 0) || /* 8x1 */
-+			(log2_dpte_req_width_ptes == 2 && log2_dpte_req_height_ptes == 1) || /* 4x2 */
-+			(log2_dpte_req_width_ptes == 1 && log2_dpte_req_height_ptes == 2)); /* 2x4 */
-+
-+	/* the dpte request dimensions in data elements is dpte_req_width x dpte_req_height
-+	 * log2_wmpg_width is how much 1 pte represent, now trying to calculate how much 64b pte req represent
-+	 */
-+	log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes;
-+	log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes;
-+	dpte_req_width = 1 << log2_dpte_req_width;
-+
-+	/* calculate pitch dpte row buffer can hold
-+	 * round the result down to a power of two.
-+	 */
-+	if (surf_linear) {
-+		log2_dpte_row_height_linear = dml_floor(
-+				dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch),
-+				1);
-+
-+		ASSERT(log2_dpte_row_height_linear >= 3);
-+
-+		if (log2_dpte_row_height_linear > 7)
-+			log2_dpte_row_height_linear = 7;
-+
-+		log2_dpte_row_height = log2_dpte_row_height_linear;
-+	} else {
-+		/* the upper bound of the dpte_row_width without dependency on viewport position follows.  */
-+		if (!surf_vert)
-+			log2_dpte_row_height = log2_dpte_req_height;
-+		else
-+			log2_dpte_row_height =
-+					(log2_blk_width < log2_dpte_req_width) ?
-+							log2_blk_width : log2_dpte_req_width;
-+	}
-+
-+	/* From programming guide:
-+	 * There is a special case of saving only half of ptes returned due to buffer space limits.
-+	 * this case applies to 4 and 8bpe in horizontal access of a vp_width greater than 2560+16
-+	 * when the pte request is 2x4 ptes (which happens when vmpg_bytes =4kb and tile blk_bytes >=64kb).
-+	 */
-+	if (!surf_vert && vp_width > (2560 + 16) && bytes_per_element >= 4 && log2_vmpg_bytes == 12
-+			&& log2_blk_bytes >= 16)
-+		log2_dpte_row_height = log2_dpte_row_height - 1; /*half of the full height */
-+
-+	*o_dpte_row_height = 1 << log2_dpte_row_height;
-+}
-+
-+static void get_surf_rq_param(
-+		struct display_mode_lib *mode_lib,
-+		struct _vcs_dpi_display_data_rq_sizing_params_st *rq_sizing_param,
-+		struct _vcs_dpi_display_data_rq_dlg_params_st *rq_dlg_param,
-+		struct _vcs_dpi_display_data_rq_misc_params_st *rq_misc_param,
-+		const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param,
-+		bool is_chroma)
-+{
-+	bool mode_422 = 0;
-+	unsigned int vp_width = 0;
-+	unsigned int vp_height = 0;
-+	unsigned int data_pitch = 0;
-+	unsigned int meta_pitch = 0;
-+	unsigned int ppe = mode_422 ? 2 : 1;
-+	bool surf_linear;
-+	bool surf_vert;
-+	unsigned int bytes_per_element;
-+	unsigned int log2_bytes_per_element;
-+	unsigned int blk256_width;
-+	unsigned int blk256_height;
-+	unsigned int log2_blk256_width;
-+	unsigned int log2_blk256_height;
-+	unsigned int blk_bytes;
-+	unsigned int log2_blk_bytes;
-+	unsigned int log2_blk_height;
-+	unsigned int log2_blk_width;
-+	unsigned int log2_meta_req_bytes;
-+	unsigned int log2_meta_req_height;
-+	unsigned int log2_meta_req_width;
-+	unsigned int meta_req_width;
-+	unsigned int meta_req_height;
-+	unsigned int log2_meta_row_height;
-+	unsigned int meta_row_width_ub;
-+	unsigned int log2_meta_chunk_bytes;
-+	unsigned int log2_meta_chunk_height;
-+	unsigned int log2_meta_chunk_width;
-+	unsigned int log2_min_meta_chunk_bytes;
-+	unsigned int min_meta_chunk_width;
-+	unsigned int meta_chunk_width;
-+	unsigned int meta_chunk_per_row_int;
-+	unsigned int meta_row_remainder;
-+	unsigned int meta_chunk_threshold;
-+	unsigned int meta_blk_bytes;
-+	unsigned int meta_blk_height;
-+	unsigned int meta_blk_width;
-+	unsigned int meta_surface_bytes;
-+	unsigned int vmpg_bytes;
-+	unsigned int meta_pte_req_per_frame_ub;
-+	unsigned int meta_pte_bytes_per_frame_ub;
-+	unsigned int log2_vmpg_bytes;
-+	unsigned int dpte_buf_in_pte_reqs;
-+	unsigned int log2_vmpg_height;
-+	unsigned int log2_vmpg_width;
-+	unsigned int log2_dpte_req_height_ptes;
-+	unsigned int log2_dpte_req_width_ptes;
-+	unsigned int log2_dpte_req_height;
-+	unsigned int log2_dpte_req_width;
-+	unsigned int log2_dpte_row_height_linear;
-+	unsigned int log2_dpte_row_height;
-+	unsigned int log2_dpte_group_width;
-+	unsigned int dpte_row_width_ub;
-+	unsigned int dpte_row_height;
-+	unsigned int dpte_req_height;
-+	unsigned int dpte_req_width;
-+	unsigned int dpte_group_width;
-+	unsigned int log2_dpte_group_bytes;
-+	unsigned int log2_dpte_group_length;
-+	unsigned int func_meta_row_height, func_dpte_row_height;
-+
-+	/* FIXME check if ppe apply for both luma and chroma in 422 case */
-+	if (is_chroma) {
-+		vp_width = pipe_src_param.viewport_width_c / ppe;
-+		vp_height = pipe_src_param.viewport_height_c;
-+		data_pitch = pipe_src_param.data_pitch_c;
-+		meta_pitch = pipe_src_param.meta_pitch_c;
-+	} else {
-+		vp_width = pipe_src_param.viewport_width / ppe;
-+		vp_height = pipe_src_param.viewport_height;
-+		data_pitch = pipe_src_param.data_pitch;
-+		meta_pitch = pipe_src_param.meta_pitch;
-+	}
-+
-+	rq_sizing_param->chunk_bytes = 8192;
-+
-+	if (rq_sizing_param->chunk_bytes == 64 * 1024)
-+		rq_sizing_param->min_chunk_bytes = 0;
-+	else
-+		rq_sizing_param->min_chunk_bytes = 1024;
-+
-+	rq_sizing_param->meta_chunk_bytes = 2048;
-+	rq_sizing_param->min_meta_chunk_bytes = 256;
-+
-+	rq_sizing_param->mpte_group_bytes = 2048;
-+
-+	surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
-+	surf_vert = (pipe_src_param.source_scan == dm_vert);
-+
-+	bytes_per_element = get_bytes_per_element(
-+			(enum source_format_class) pipe_src_param.source_format,
-+			is_chroma);
-+	log2_bytes_per_element = dml_log2(bytes_per_element);
-+	blk256_width = 0;
-+	blk256_height = 0;
-+
-+	if (surf_linear) {
-+		blk256_width = 256 / bytes_per_element;
-+		blk256_height = 1;
-+	} else {
-+		get_blk256_size(&blk256_width, &blk256_height, bytes_per_element);
-+	}
-+
-+	DTRACE("DLG: %s: surf_linear        = %d", __func__, surf_linear);
-+	DTRACE("DLG: %s: surf_vert          = %d", __func__, surf_vert);
-+	DTRACE("DLG: %s: blk256_width       = %d", __func__, blk256_width);
-+	DTRACE("DLG: %s: blk256_height      = %d", __func__, blk256_height);
-+
-+	log2_blk256_width = dml_log2((double) blk256_width);
-+	log2_blk256_height = dml_log2((double) blk256_height);
-+	blk_bytes =
-+			surf_linear ? 256 : get_blk_size_bytes(
-+							(enum source_macro_tile_size) pipe_src_param.macro_tile_size);
-+	log2_blk_bytes = dml_log2((double) blk_bytes);
-+	log2_blk_height = 0;
-+	log2_blk_width = 0;
-+
-+	/* remember log rule
-+	 * "+" in log is multiply
-+	 * "-" in log is divide
-+	 * "/2" is like square root
-+	 * blk is vertical biased
-+	 */
-+	if (pipe_src_param.sw_mode != dm_sw_linear)
-+		log2_blk_height = log2_blk256_height
-+				+ dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
-+	else
-+		log2_blk_height = 0; /* blk height of 1 */
-+
-+	log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
-+
-+	if (!surf_vert) {
-+		rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
-+				+ blk256_width;
-+		rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width;
-+	} else {
-+		rq_dlg_param->swath_width_ub = dml_round_to_multiple(
-+				vp_height - 1,
-+				blk256_height,
-+				1) + blk256_height;
-+		rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height;
-+	}
-+
-+	if (!surf_vert)
-+		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height
-+				* bytes_per_element;
-+	else
-+		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width
-+				* bytes_per_element;
-+
-+	rq_misc_param->blk256_height = blk256_height;
-+	rq_misc_param->blk256_width = blk256_width;
-+
-+	/* -------  */
-+	/* meta     */
-+	/* -------  */
-+	log2_meta_req_bytes = 6; /* meta request is 64b and is 8x8byte meta element */
-+
-+	/* each 64b meta request for dcn is 8x8 meta elements and
-+	 * a meta element covers one 256b block of the the data surface.
-+	 */
-+	log2_meta_req_height = log2_blk256_height + 3; /* meta req is 8x8 byte, each byte represent 1 blk256 */
-+	log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
-+			- log2_meta_req_height;
-+	meta_req_width = 1 << log2_meta_req_width;
-+	meta_req_height = 1 << log2_meta_req_height;
-+	log2_meta_row_height = 0;
-+	meta_row_width_ub = 0;
-+
-+	/* the dimensions of a meta row are meta_row_width x meta_row_height in elements.
-+	 * calculate upper bound of the meta_row_width
-+	 */
-+	if (!surf_vert) {
-+		log2_meta_row_height = log2_meta_req_height;
-+		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
-+				+ meta_req_width;
-+		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
-+	} else {
-+		log2_meta_row_height = log2_meta_req_width;
-+		meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1)
-+				+ meta_req_height;
-+		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
-+	}
-+	rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
-+
-+	log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
-+	log2_meta_chunk_height = log2_meta_row_height;
-+
-+	/*full sized meta chunk width in unit of data elements */
-+	log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element
-+			- log2_meta_chunk_height;
-+	log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
-+	min_meta_chunk_width = 1
-+			<< (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element
-+					- log2_meta_chunk_height);
-+	meta_chunk_width = 1 << log2_meta_chunk_width;
-+	meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
-+	meta_row_remainder = meta_row_width_ub % meta_chunk_width;
-+	meta_chunk_threshold = 0;
-+	meta_blk_bytes = 4096;
-+	meta_blk_height = blk256_height * 64;
-+	meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height;
-+	meta_surface_bytes = meta_pitch
-+			* (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1)
-+					+ meta_blk_height) * bytes_per_element / 256;
-+	vmpg_bytes = mode_lib->soc.vmm_page_size_bytes;
-+	meta_pte_req_per_frame_ub = (dml_round_to_multiple(
-+			meta_surface_bytes - vmpg_bytes,
-+			8 * vmpg_bytes,
-+			1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
-+	meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; /*64B mpte request */
-+	rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
-+
-+	DTRACE("DLG: %s: meta_blk_height             = %d", __func__, meta_blk_height);
-+	DTRACE("DLG: %s: meta_blk_width              = %d", __func__, meta_blk_width);
-+	DTRACE("DLG: %s: meta_surface_bytes          = %d", __func__, meta_surface_bytes);
-+	DTRACE("DLG: %s: meta_pte_req_per_frame_ub   = %d", __func__, meta_pte_req_per_frame_ub);
-+	DTRACE("DLG: %s: meta_pte_bytes_per_frame_ub = %d", __func__, meta_pte_bytes_per_frame_ub);
-+
-+	if (!surf_vert)
-+		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
-+	else
-+		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
-+
-+	if (meta_row_remainder <= meta_chunk_threshold)
-+		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
-+	else
-+		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
-+
-+	rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
-+
-+	/* ------ */
-+	/* dpte   */
-+	/* ------ */
-+	log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
-+	dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs;
-+
-+	log2_vmpg_height = 0;
-+	log2_vmpg_width = 0;
-+	log2_dpte_req_height_ptes = 0;
-+	log2_dpte_req_width_ptes = 0;
-+	log2_dpte_req_height = 0;
-+	log2_dpte_req_width = 0;
-+	log2_dpte_row_height_linear = 0;
-+	log2_dpte_row_height = 0;
-+	log2_dpte_group_width = 0;
-+	dpte_row_width_ub = 0;
-+	dpte_row_height = 0;
-+	dpte_req_height = 0; /* 64b dpte req height in data element */
-+	dpte_req_width = 0; /* 64b dpte req width in data element */
-+	dpte_group_width = 0;
-+	log2_dpte_group_bytes = 0;
-+	log2_dpte_group_length = 0;
-+
-+	if (surf_linear)
-+		log2_vmpg_height = 0; /* one line high */
-+	else
-+		log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
-+	log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
-+
-+	/* only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. */
-+	if (log2_blk_bytes <= log2_vmpg_bytes)
-+		log2_dpte_req_height_ptes = 0;
-+	else if (log2_blk_height - log2_vmpg_height >= 2)
-+		log2_dpte_req_height_ptes = 2;
-+	else
-+		log2_dpte_req_height_ptes = log2_blk_height - log2_vmpg_height;
-+	log2_dpte_req_width_ptes = 3 - log2_dpte_req_height_ptes;
-+
-+	/* Ensure we only have the 3 shapes */
-+	ASSERT((log2_dpte_req_width_ptes == 3 && log2_dpte_req_height_ptes == 0) || /* 8x1 */
-+			(log2_dpte_req_width_ptes == 2 && log2_dpte_req_height_ptes == 1) || /* 4x2 */
-+			(log2_dpte_req_width_ptes == 1 && log2_dpte_req_height_ptes == 2)); /* 2x4 */
-+
-+	/* The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
-+	 * log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
-+	 * That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
-+	 */
-+	log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes;
-+	log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes;
-+	dpte_req_height = 1 << log2_dpte_req_height;
-+	dpte_req_width = 1 << log2_dpte_req_width;
-+
-+	/* calculate pitch dpte row buffer can hold
-+	 * round the result down to a power of two.
-+	 */
-+	if (surf_linear) {
-+		log2_dpte_row_height_linear = dml_floor(
-+				dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch),
-+				1);
-+
-+		ASSERT(log2_dpte_row_height_linear >= 3);
-+
-+		if (log2_dpte_row_height_linear > 7)
-+			log2_dpte_row_height_linear = 7;
-+
-+		log2_dpte_row_height = log2_dpte_row_height_linear;
-+		rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
-+
-+		/* For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
-+		 * the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
-+		 */
-+		dpte_row_width_ub = dml_round_to_multiple(
-+				data_pitch * dpte_row_height - 1,
-+				dpte_req_width,
-+				1) + dpte_req_width;
-+		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
-+	} else {
-+		/* for tiled mode, row height is the same as req height and row store up to vp size upper bound */
-+		if (!surf_vert) {
-+			log2_dpte_row_height = log2_dpte_req_height;
-+			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
-+					+ dpte_req_width;
-+			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
-+		} else {
-+			log2_dpte_row_height =
-+					(log2_blk_width < log2_dpte_req_width) ?
-+							log2_blk_width : log2_dpte_req_width;
-+			dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
-+					+ dpte_req_height;
-+			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
-+		}
-+		rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
-+	}
-+	rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64;
-+
-+	/* From programming guide:
-+	 * There is a special case of saving only half of ptes returned due to buffer space limits.
-+	 * this case applies to 4 and 8bpe in horizontal access of a vp_width greater than 2560+16
-+	 * when the pte request is 2x4 ptes (which happens when vmpg_bytes =4kb and tile blk_bytes >=64kb).
-+	 */
-+	if (!surf_vert && vp_width > (2560 + 16) && bytes_per_element >= 4 && log2_vmpg_bytes == 12
-+			&& log2_blk_bytes >= 16) {
-+		log2_dpte_row_height = log2_dpte_row_height - 1; /*half of the full height */
-+		rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
-+	}
-+
-+	/* the dpte_group_bytes is reduced for the specific case of vertical
-+	 * access of a tile surface that has dpte request of 8x1 ptes.
-+	 */
-+	if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) /*reduced, in this case, will have page fault within a group */
-+		rq_sizing_param->dpte_group_bytes = 512;
-+	else
-+		/*full size */
-+		rq_sizing_param->dpte_group_bytes = 2048;
-+
-+	/*since pte request size is 64byte, the number of data pte requests per full sized group is as follows.  */
-+	log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
-+	log2_dpte_group_length = log2_dpte_group_bytes - 6; /*length in 64b requests  */
-+
-+	/* full sized data pte group width in elements */
-+	if (!surf_vert)
-+		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
-+	else
-+		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
-+
-+	dpte_group_width = 1 << log2_dpte_group_width;
-+
-+	/* since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
-+	 * the upper bound for the dpte groups per row is as follows.
-+	 */
-+	rq_dlg_param->dpte_groups_per_row_ub = dml_ceil(
-+			(double) dpte_row_width_ub / dpte_group_width,
-+			1);
-+
-+	dml1_rq_dlg_get_row_heights(
-+			mode_lib,
-+			&func_dpte_row_height,
-+			&func_meta_row_height,
-+			vp_width,
-+			data_pitch,
-+			pipe_src_param.source_format,
-+			pipe_src_param.sw_mode,
-+			pipe_src_param.macro_tile_size,
-+			pipe_src_param.source_scan,
-+			is_chroma);
-+
-+	/* Just a check to make sure this function and the new one give the same
-+	 * result. The standalone get_row_heights() function is based off of the
-+	 * code in this function so the same changes need to be made to both.
-+	 */
-+	if (rq_dlg_param->meta_row_height != func_meta_row_height) {
-+		DTRACE(
-+				"MISMATCH: rq_dlg_param->meta_row_height = %d",
-+				rq_dlg_param->meta_row_height);
-+		DTRACE("MISMATCH: func_meta_row_height = %d", func_meta_row_height);
-+		ASSERT(0);
-+	}
-+
-+	if (rq_dlg_param->dpte_row_height != func_dpte_row_height) {
-+		DTRACE(
-+				"MISMATCH: rq_dlg_param->dpte_row_height = %d",
-+				rq_dlg_param->dpte_row_height);
-+		DTRACE("MISMATCH: func_dpte_row_height = %d", func_dpte_row_height);
-+		ASSERT(0);
-+	}
-+}
-+
-+void dml1_rq_dlg_get_rq_params(
-+		struct display_mode_lib *mode_lib,
-+		struct _vcs_dpi_display_rq_params_st *rq_param,
-+		const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param)
-+{
-+	/* get param for luma surface */
-+	rq_param->yuv420 = pipe_src_param.source_format == dm_420_8
-+			|| pipe_src_param.source_format == dm_420_10;
-+	rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10;
-+
-+	get_surf_rq_param(
-+			mode_lib,
-+			&(rq_param->sizing.rq_l),
-+			&(rq_param->dlg.rq_l),
-+			&(rq_param->misc.rq_l),
-+			pipe_src_param,
-+			0);
-+
-+	if (is_dual_plane((enum source_format_class) pipe_src_param.source_format)) {
-+		/* get param for chroma surface */
-+		get_surf_rq_param(
-+				mode_lib,
-+				&(rq_param->sizing.rq_c),
-+				&(rq_param->dlg.rq_c),
-+				&(rq_param->misc.rq_c),
-+				pipe_src_param,
-+				1);
-+	}
-+
-+	/* calculate how to split the det buffer space between luma and chroma */
-+	handle_det_buf_split(mode_lib, rq_param, pipe_src_param);
-+	print__rq_params_st(mode_lib, *rq_param);
-+}
-+
-+/* Note: currently taken in as is.
-+ * Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
-+ */
-+void dml1_rq_dlg_get_dlg_params(
-+		struct display_mode_lib *mode_lib,
-+		struct _vcs_dpi_display_dlg_regs_st *disp_dlg_regs,
-+		struct _vcs_dpi_display_ttu_regs_st *disp_ttu_regs,
-+		const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
-+		const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
-+		const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
-+		const bool cstate_en,
-+		const bool pstate_en,
-+		const bool vm_en,
-+		const bool iflip_en)
-+{
-+	/* Timing */
-+	unsigned int htotal = e2e_pipe_param.pipe.dest.htotal;
-+	unsigned int hblank_end = e2e_pipe_param.pipe.dest.hblank_end;
-+	unsigned int vblank_start = e2e_pipe_param.pipe.dest.vblank_start;
-+	unsigned int vblank_end = e2e_pipe_param.pipe.dest.vblank_end;
-+	bool interlaced = e2e_pipe_param.pipe.dest.interlaced;
-+	unsigned int min_vblank = mode_lib->ip.min_vblank_lines;
-+
-+	double pclk_freq_in_mhz = e2e_pipe_param.pipe.dest.pixel_rate_mhz;
-+	double refclk_freq_in_mhz = e2e_pipe_param.clks_cfg.refclk_mhz;
-+	double dppclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dppclk_mhz;
-+	double dispclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dispclk_mhz;
-+
-+	double ref_freq_to_pix_freq;
-+	double prefetch_xy_calc_in_dcfclk;
-+	double min_dcfclk_mhz;
-+	double t_calc_us;
-+	double min_ttu_vblank;
-+	double min_dst_y_ttu_vblank;
-+	unsigned int dlg_vblank_start;
-+	bool dcc_en;
-+	bool dual_plane;
-+	bool mode_422;
-+	unsigned int access_dir;
-+	unsigned int bytes_per_element_l;
-+	unsigned int bytes_per_element_c;
-+	unsigned int vp_height_l;
-+	unsigned int vp_width_l;
-+	unsigned int vp_height_c;
-+	unsigned int vp_width_c;
-+	unsigned int htaps_l;
-+	unsigned int htaps_c;
-+	double hratios_l;
-+	double hratios_c;
-+	double vratio_l;
-+	double vratio_c;
-+	double line_time_in_us;
-+	double vinit_l;
-+	double vinit_c;
-+	double vinit_bot_l;
-+	double vinit_bot_c;
-+	unsigned int swath_height_l;
-+	unsigned int swath_width_ub_l;
-+	unsigned int dpte_bytes_per_row_ub_l;
-+	unsigned int dpte_groups_per_row_ub_l;
-+	unsigned int meta_pte_bytes_per_frame_ub_l;
-+	unsigned int meta_bytes_per_row_ub_l;
-+	unsigned int swath_height_c;
-+	unsigned int swath_width_ub_c;
-+	unsigned int dpte_bytes_per_row_ub_c;
-+	unsigned int dpte_groups_per_row_ub_c;
-+	unsigned int meta_chunks_per_row_ub_l;
-+	unsigned int vupdate_offset;
-+	unsigned int vupdate_width;
-+	unsigned int vready_offset;
-+	unsigned int dppclk_delay_subtotal;
-+	unsigned int dispclk_delay_subtotal;
-+	unsigned int pixel_rate_delay_subtotal;
-+	unsigned int vstartup_start;
-+	unsigned int dst_x_after_scaler;
-+	unsigned int dst_y_after_scaler;
-+	double line_wait;
-+	double line_o;
-+	double line_setup;
-+	double line_calc;
-+	double dst_y_prefetch;
-+	double t_pre_us;
-+	unsigned int vm_bytes;
-+	unsigned int meta_row_bytes;
-+	unsigned int max_num_sw_l;
-+	unsigned int max_num_sw_c;
-+	unsigned int max_partial_sw_l;
-+	unsigned int max_partial_sw_c;
-+	double max_vinit_l;
-+	double max_vinit_c;
-+	unsigned int lsw_l;
-+	unsigned int lsw_c;
-+	unsigned int sw_bytes_ub_l;
-+	unsigned int sw_bytes_ub_c;
-+	unsigned int sw_bytes;
-+	unsigned int dpte_row_bytes;
-+	double prefetch_bw;
-+	double flip_bw;
-+	double t_vm_us;
-+	double t_r0_us;
-+	double dst_y_per_vm_vblank;
-+	double dst_y_per_row_vblank;
-+	double min_dst_y_per_vm_vblank;
-+	double min_dst_y_per_row_vblank;
-+	double lsw;
-+	double vratio_pre_l;
-+	double vratio_pre_c;
-+	unsigned int req_per_swath_ub_l;
-+	unsigned int req_per_swath_ub_c;
-+	unsigned int meta_row_height_l;
-+	unsigned int swath_width_pixels_ub_l;
-+	unsigned int swath_width_pixels_ub_c;
-+	unsigned int scaler_rec_in_width_l;
-+	unsigned int scaler_rec_in_width_c;
-+	unsigned int dpte_row_height_l;
-+	unsigned int dpte_row_height_c;
-+	double hscale_pixel_rate_l;
-+	double hscale_pixel_rate_c;
-+	double min_hratio_fact_l;
-+	double min_hratio_fact_c;
-+	double refcyc_per_line_delivery_pre_l;
-+	double refcyc_per_line_delivery_pre_c;
-+	double refcyc_per_line_delivery_l;
-+	double refcyc_per_line_delivery_c;
-+	double refcyc_per_req_delivery_pre_l;
-+	double refcyc_per_req_delivery_pre_c;
-+	double refcyc_per_req_delivery_l;
-+	double refcyc_per_req_delivery_c;
-+	double refcyc_per_req_delivery_pre_cur0;
-+	double refcyc_per_req_delivery_cur0;
-+	unsigned int full_recout_width;
-+	double hratios_cur0;
-+	unsigned int cur0_src_width;
-+	enum cursor_bpp cur0_bpp;
-+	unsigned int cur0_req_size;
-+	unsigned int cur0_req_width;
-+	double cur0_width_ub;
-+	double cur0_req_per_width;
-+	double hactive_cur0;
-+
-+	memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
-+	memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
-+
-+	DTRACE("DLG: %s: cstate_en = %d", __func__, cstate_en);
-+	DTRACE("DLG: %s: pstate_en = %d", __func__, pstate_en);
-+	DTRACE("DLG: %s: vm_en     = %d", __func__, vm_en);
-+	DTRACE("DLG: %s: iflip_en  = %d", __func__, iflip_en);
-+
-+	/* ------------------------- */
-+	/* Section 1.5.2.1: OTG dependent Params */
-+	/* ------------------------- */
-+	DTRACE("DLG: %s: dppclk_freq_in_mhz     = %3.2f", __func__, dppclk_freq_in_mhz);
-+	DTRACE("DLG: %s: dispclk_freq_in_mhz    = %3.2f", __func__, dispclk_freq_in_mhz);
-+	DTRACE("DLG: %s: refclk_freq_in_mhz     = %3.2f", __func__, refclk_freq_in_mhz);
-+	DTRACE("DLG: %s: pclk_freq_in_mhz       = %3.2f", __func__, pclk_freq_in_mhz);
-+	DTRACE("DLG: %s: interlaced             = %d", __func__, interlaced);
-+
-+	ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
-+	ASSERT(ref_freq_to_pix_freq < 4.0);
-+	disp_dlg_regs->ref_freq_to_pix_freq =
-+			(unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
-+	disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
-+			* dml_pow(2, 8));
-+	disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end
-+			* (double) ref_freq_to_pix_freq);
-+	ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));
-+	disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */
-+
-+	prefetch_xy_calc_in_dcfclk = 24.0; /* FIXME: ip_param */
-+	min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
-+	t_calc_us = prefetch_xy_calc_in_dcfclk / min_dcfclk_mhz;
-+	min_ttu_vblank = dlg_sys_param.t_urg_wm_us;
-+	if (cstate_en)
-+		min_ttu_vblank = dml_max(dlg_sys_param.t_sr_wm_us, min_ttu_vblank);
-+	if (pstate_en)
-+		min_ttu_vblank = dml_max(dlg_sys_param.t_mclk_wm_us, min_ttu_vblank);
-+	min_ttu_vblank = min_ttu_vblank + t_calc_us;
-+
-+	min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
-+	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
-+
-+	disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
-+			+ min_dst_y_ttu_vblank) * dml_pow(2, 2));
-+	ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
-+
-+	DTRACE("DLG: %s: min_dcfclk_mhz                         = %3.2f", __func__, min_dcfclk_mhz);
-+	DTRACE("DLG: %s: min_ttu_vblank                         = %3.2f", __func__, min_ttu_vblank);
-+	DTRACE(
-+			"DLG: %s: min_dst_y_ttu_vblank                   = %3.2f",
-+			__func__,
-+			min_dst_y_ttu_vblank);
-+	DTRACE("DLG: %s: t_calc_us                              = %3.2f", __func__, t_calc_us);
-+	DTRACE(
-+			"DLG: %s: disp_dlg_regs->min_dst_y_next_start    = 0x%0x",
-+			__func__,
-+			disp_dlg_regs->min_dst_y_next_start);
-+	DTRACE(
-+			"DLG: %s: ref_freq_to_pix_freq                   = %3.2f",
-+			__func__,
-+			ref_freq_to_pix_freq);
-+
-+	/* ------------------------- */
-+	/* Section 1.5.2.2: Prefetch, Active and TTU  */
-+	/* ------------------------- */
-+	/* Prefetch Calc */
-+	/* Source */
-+	dcc_en = e2e_pipe_param.pipe.src.dcc;
-+	dual_plane = is_dual_plane(
-+			(enum source_format_class) e2e_pipe_param.pipe.src.source_format);
-+	mode_422 = 0; /* FIXME */
-+	access_dir = (e2e_pipe_param.pipe.src.source_scan == dm_vert); /* vp access direction: horizontal or vertical accessed */
-+	bytes_per_element_l = get_bytes_per_element(
-+			(enum source_format_class) e2e_pipe_param.pipe.src.source_format,
-+			0);
-+	bytes_per_element_c = get_bytes_per_element(
-+			(enum source_format_class) e2e_pipe_param.pipe.src.source_format,
-+			1);
-+	vp_height_l = e2e_pipe_param.pipe.src.viewport_height;
-+	vp_width_l = e2e_pipe_param.pipe.src.viewport_width;
-+	vp_height_c = e2e_pipe_param.pipe.src.viewport_height_c;
-+	vp_width_c = e2e_pipe_param.pipe.src.viewport_width_c;
-+
-+	/* Scaling */
-+	htaps_l = e2e_pipe_param.pipe.scale_taps.htaps;
-+	htaps_c = e2e_pipe_param.pipe.scale_taps.htaps_c;
-+	hratios_l = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio;
-+	hratios_c = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio_c;
-+	vratio_l = e2e_pipe_param.pipe.scale_ratio_depth.vscl_ratio;
-+	vratio_c = e2e_pipe_param.pipe.scale_ratio_depth.vscl_ratio_c;
-+
-+	line_time_in_us = (htotal / pclk_freq_in_mhz);
-+	vinit_l = e2e_pipe_param.pipe.scale_ratio_depth.vinit;
-+	vinit_c = e2e_pipe_param.pipe.scale_ratio_depth.vinit_c;
-+	vinit_bot_l = e2e_pipe_param.pipe.scale_ratio_depth.vinit_bot;
-+	vinit_bot_c = e2e_pipe_param.pipe.scale_ratio_depth.vinit_bot_c;
-+
-+	swath_height_l = rq_dlg_param.rq_l.swath_height;
-+	swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
-+	dpte_bytes_per_row_ub_l = rq_dlg_param.rq_l.dpte_bytes_per_row_ub;
-+	dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
-+	meta_pte_bytes_per_frame_ub_l = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub;
-+	meta_bytes_per_row_ub_l = rq_dlg_param.rq_l.meta_bytes_per_row_ub;
-+
-+	swath_height_c = rq_dlg_param.rq_c.swath_height;
-+	swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
-+	dpte_bytes_per_row_ub_c = rq_dlg_param.rq_c.dpte_bytes_per_row_ub;
-+	dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
-+
-+	meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
-+	vupdate_offset = e2e_pipe_param.pipe.dest.vupdate_offset;
-+	vupdate_width = e2e_pipe_param.pipe.dest.vupdate_width;
-+	vready_offset = e2e_pipe_param.pipe.dest.vready_offset;
-+
-+	dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
-+	dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
-+	pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz
-+			+ dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz;
-+
-+	vstartup_start = e2e_pipe_param.pipe.dest.vstartup_start;
-+
-+	if (interlaced)
-+		vstartup_start = vstartup_start / 2;
-+
-+	if (vstartup_start >= min_vblank) {
-+		DTRACE(
-+				"WARNING_DLG: %s:  vblank_start=%d vblank_end=%d",
-+				__func__,
-+				vblank_start,
-+				vblank_end);
-+		DTRACE(
-+				"WARNING_DLG: %s:  vstartup_start=%d should be less than min_vblank=%d",
-+				__func__,
-+				vstartup_start,
-+				min_vblank);
-+		min_vblank = vstartup_start + 1;
-+		DTRACE(
-+				"WARNING_DLG: %s:  vstartup_start=%d should be less than min_vblank=%d",
-+				__func__,
-+				vstartup_start,
-+				min_vblank);
-+	}
-+
-+	dst_x_after_scaler = 0;
-+	dst_y_after_scaler = 0;
-+
-+	if (e2e_pipe_param.pipe.src.is_hsplit)
-+		dst_x_after_scaler = pixel_rate_delay_subtotal
-+				+ e2e_pipe_param.pipe.dest.recout_width;
-+	else
-+		dst_x_after_scaler = pixel_rate_delay_subtotal;
-+
-+	if (e2e_pipe_param.dout.output_format == dm_420)
-+		dst_y_after_scaler = 1;
-+	else
-+		dst_y_after_scaler = 0;
-+
-+	if (dst_x_after_scaler >= htotal) {
-+		dst_x_after_scaler = dst_x_after_scaler - htotal;
-+		dst_y_after_scaler = dst_y_after_scaler + 1;
-+	}
-+
-+	DTRACE("DLG: %s: htotal                                 = %d", __func__, htotal);
-+	DTRACE(
-+			"DLG: %s: pixel_rate_delay_subtotal              = %d",
-+			__func__,
-+			pixel_rate_delay_subtotal);
-+	DTRACE("DLG: %s: dst_x_after_scaler                     = %d", __func__, dst_x_after_scaler);
-+	DTRACE("DLG: %s: dst_y_after_scaler                     = %d", __func__, dst_y_after_scaler);
-+
-+	line_wait = mode_lib->soc.urgent_latency_us;
-+	if (cstate_en)
-+		line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
-+	if (pstate_en)
-+		line_wait = dml_max(
-+				mode_lib->soc.dram_clock_change_latency_us
-+						+ mode_lib->soc.urgent_latency_us,
-+				line_wait);
-+	line_wait = line_wait / line_time_in_us;
-+
-+	line_o = (double) dst_y_after_scaler + dst_x_after_scaler / (double) htotal;
-+	line_setup = (double) (vupdate_offset + vupdate_width + vready_offset) / (double) htotal;
-+	line_calc = t_calc_us / line_time_in_us;
-+
-+	DTRACE(
-+			"DLG: %s: soc.sr_enter_plus_exit_time_us     = %3.2f",
-+			__func__,
-+			(double) mode_lib->soc.sr_enter_plus_exit_time_us);
-+	DTRACE(
-+			"DLG: %s: soc.dram_clock_change_latency_us   = %3.2f",
-+			__func__,
-+			(double) mode_lib->soc.dram_clock_change_latency_us);
-+	DTRACE(
-+			"DLG: %s: soc.urgent_latency_us              = %3.2f",
-+			__func__,
-+			mode_lib->soc.urgent_latency_us);
-+
-+	DTRACE("DLG: %s: swath_height_l     = %d", __func__, swath_height_l);
-+	if (dual_plane)
-+		DTRACE("DLG: %s: swath_height_c     = %d", __func__, swath_height_c);
-+
-+	DTRACE(
-+			"DLG: %s: t_srx_delay_us     = %3.2f",
-+			__func__,
-+			(double) dlg_sys_param.t_srx_delay_us);
-+	DTRACE("DLG: %s: line_time_in_us    = %3.2f", __func__, (double) line_time_in_us);
-+	DTRACE("DLG: %s: vupdate_offset     = %d", __func__, vupdate_offset);
-+	DTRACE("DLG: %s: vupdate_width      = %d", __func__, vupdate_width);
-+	DTRACE("DLG: %s: vready_offset      = %d", __func__, vready_offset);
-+	DTRACE("DLG: %s: line_time_in_us    = %3.2f", __func__, line_time_in_us);
-+	DTRACE("DLG: %s: line_wait          = %3.2f", __func__, line_wait);
-+	DTRACE("DLG: %s: line_o             = %3.2f", __func__, line_o);
-+	DTRACE("DLG: %s: line_setup         = %3.2f", __func__, line_setup);
-+	DTRACE("DLG: %s: line_calc          = %3.2f", __func__, line_calc);
-+
-+	dst_y_prefetch = ((double) min_vblank - 1.0)
-+			- (line_setup + line_calc + line_wait + line_o);
-+	DTRACE("DLG: %s: dst_y_prefetch (before rnd) = %3.2f", __func__, dst_y_prefetch);
-+	ASSERT(dst_y_prefetch >= 2.0);
-+
-+	dst_y_prefetch = dml_floor(4.0 * (dst_y_prefetch + 0.125), 1) / 4;
-+	DTRACE("DLG: %s: dst_y_prefetch (after rnd) = %3.2f", __func__, dst_y_prefetch);
-+
-+	t_pre_us = dst_y_prefetch * line_time_in_us;
-+	vm_bytes = 0;
-+	meta_row_bytes = 0;
-+
-+	if (dcc_en && vm_en)
-+		vm_bytes = meta_pte_bytes_per_frame_ub_l;
-+	if (dcc_en)
-+		meta_row_bytes = meta_bytes_per_row_ub_l;
-+
-+	max_num_sw_l = 0;
-+	max_num_sw_c = 0;
-+	max_partial_sw_l = 0;
-+	max_partial_sw_c = 0;
-+
-+	max_vinit_l = interlaced ? dml_max(vinit_l, vinit_bot_l) : vinit_l;
-+	max_vinit_c = interlaced ? dml_max(vinit_c, vinit_bot_c) : vinit_c;
-+
-+	get_swath_need(mode_lib, &max_num_sw_l, &max_partial_sw_l, swath_height_l, max_vinit_l);
-+	if (dual_plane)
-+		get_swath_need(
-+				mode_lib,
-+				&max_num_sw_c,
-+				&max_partial_sw_c,
-+				swath_height_c,
-+				max_vinit_c);
-+
-+	lsw_l = max_num_sw_l * swath_height_l + max_partial_sw_l;
-+	lsw_c = max_num_sw_c * swath_height_c + max_partial_sw_c;
-+	sw_bytes_ub_l = lsw_l * swath_width_ub_l * bytes_per_element_l;
-+	sw_bytes_ub_c = lsw_c * swath_width_ub_c * bytes_per_element_c;
-+	sw_bytes = 0;
-+	dpte_row_bytes = 0;
-+
-+	if (vm_en) {
-+		if (dual_plane)
-+			dpte_row_bytes = dpte_bytes_per_row_ub_l + dpte_bytes_per_row_ub_c;
-+		else
-+			dpte_row_bytes = dpte_bytes_per_row_ub_l;
-+	} else {
-+		dpte_row_bytes = 0;
-+	}
-+
-+	if (dual_plane)
-+		sw_bytes = sw_bytes_ub_l + sw_bytes_ub_c;
-+	else
-+		sw_bytes = sw_bytes_ub_l;
-+
-+	DTRACE("DLG: %s: sw_bytes_ub_l           = %d", __func__, sw_bytes_ub_l);
-+	DTRACE("DLG: %s: sw_bytes_ub_c           = %d", __func__, sw_bytes_ub_c);
-+	DTRACE("DLG: %s: sw_bytes                = %d", __func__, sw_bytes);
-+	DTRACE("DLG: %s: vm_bytes                = %d", __func__, vm_bytes);
-+	DTRACE("DLG: %s: meta_row_bytes          = %d", __func__, meta_row_bytes);
-+	DTRACE("DLG: %s: dpte_row_bytes          = %d", __func__, dpte_row_bytes);
-+
-+	prefetch_bw = (vm_bytes + 2 * dpte_row_bytes + 2 * meta_row_bytes + sw_bytes) / t_pre_us;
-+	flip_bw = ((vm_bytes + dpte_row_bytes + meta_row_bytes) * dlg_sys_param.total_flip_bw)
-+			/ (double) dlg_sys_param.total_flip_bytes;
-+	t_vm_us = line_time_in_us / 4.0;
-+	if (vm_en && dcc_en) {
-+		t_vm_us = dml_max(
-+				dlg_sys_param.t_extra_us,
-+				dml_max((double) vm_bytes / prefetch_bw, t_vm_us));
-+
-+		if (iflip_en && !dual_plane) {
-+			t_vm_us = dml_max(mode_lib->soc.urgent_latency_us, t_vm_us);
-+			if (flip_bw > 0.)
-+				t_vm_us = dml_max(vm_bytes / flip_bw, t_vm_us);
-+		}
-+	}
-+
-+	t_r0_us = dml_max(dlg_sys_param.t_extra_us - t_vm_us, line_time_in_us - t_vm_us);
-+
-+	if (vm_en || dcc_en) {
-+		t_r0_us = dml_max(
-+				(double) (dpte_row_bytes + meta_row_bytes) / prefetch_bw,
-+				dlg_sys_param.t_extra_us);
-+		t_r0_us = dml_max((double) (line_time_in_us - t_vm_us), t_r0_us);
-+
-+		if (iflip_en && !dual_plane) {
-+			t_r0_us = dml_max(mode_lib->soc.urgent_latency_us * 2.0, t_r0_us);
-+			if (flip_bw > 0.)
-+				t_r0_us = dml_max(
-+						(dpte_row_bytes + meta_row_bytes) / flip_bw,
-+						t_r0_us);
-+		}
-+	}
-+
-+	disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; /* in terms of line */
-+	disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; /* in terms of refclk */
-+	ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));
-+	DTRACE(
-+			"DLG: %s: disp_dlg_regs->dst_y_after_scaler      = 0x%0x",
-+			__func__,
-+			disp_dlg_regs->dst_y_after_scaler);
-+	DTRACE(
-+			"DLG: %s: disp_dlg_regs->refcyc_x_after_scaler   = 0x%0x",
-+			__func__,
-+			disp_dlg_regs->refcyc_x_after_scaler);
-+
-+	disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
-+	DTRACE(
-+			"DLG: %s: disp_dlg_regs->dst_y_prefetch  = %d",
-+			__func__,
-+			disp_dlg_regs->dst_y_prefetch);
-+
-+	dst_y_per_vm_vblank = 0.0;
-+	dst_y_per_row_vblank = 0.0;
-+
-+	dst_y_per_vm_vblank = t_vm_us / line_time_in_us;
-+	dst_y_per_vm_vblank = dml_floor(4.0 * (dst_y_per_vm_vblank + 0.125), 1) / 4.0;
-+	disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
-+
-+	dst_y_per_row_vblank = t_r0_us / line_time_in_us;
-+	dst_y_per_row_vblank = dml_floor(4.0 * (dst_y_per_row_vblank + 0.125), 1) / 4.0;
-+	disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
-+
-+	DTRACE("DLG: %s: lsw_l                   = %d", __func__, lsw_l);
-+	DTRACE("DLG: %s: lsw_c                   = %d", __func__, lsw_c);
-+	DTRACE("DLG: %s: dpte_bytes_per_row_ub_l = %d", __func__, dpte_bytes_per_row_ub_l);
-+	DTRACE("DLG: %s: dpte_bytes_per_row_ub_c = %d", __func__, dpte_bytes_per_row_ub_c);
-+
-+	DTRACE("DLG: %s: prefetch_bw            = %3.2f", __func__, prefetch_bw);
-+	DTRACE("DLG: %s: flip_bw                = %3.2f", __func__, flip_bw);
-+	DTRACE("DLG: %s: t_pre_us               = %3.2f", __func__, t_pre_us);
-+	DTRACE("DLG: %s: t_vm_us                = %3.2f", __func__, t_vm_us);
-+	DTRACE("DLG: %s: t_r0_us                = %3.2f", __func__, t_r0_us);
-+	DTRACE("DLG: %s: dst_y_per_vm_vblank    = %3.2f", __func__, dst_y_per_vm_vblank);
-+	DTRACE("DLG: %s: dst_y_per_row_vblank   = %3.2f", __func__, dst_y_per_row_vblank);
-+	DTRACE("DLG: %s: dst_y_prefetch         = %3.2f", __func__, dst_y_prefetch);
-+
-+	min_dst_y_per_vm_vblank = 8.0;
-+	min_dst_y_per_row_vblank = 16.0;
-+	if (htotal <= 75) {
-+		min_vblank = 300;
-+		min_dst_y_per_vm_vblank = 100.0;
-+		min_dst_y_per_row_vblank = 100.0;
-+	}
-+
-+	ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank);
-+	ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank);
-+
-+	ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
-+	lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank);
-+
-+	DTRACE("DLG: %s: lsw = %3.2f", __func__, lsw);
-+
-+	vratio_pre_l = get_vratio_pre(
-+			mode_lib,
-+			max_num_sw_l,
-+			max_partial_sw_l,
-+			swath_height_l,
-+			max_vinit_l,
-+			lsw);
-+	vratio_pre_c = 1.0;
-+	if (dual_plane)
-+		vratio_pre_c = get_vratio_pre(
-+				mode_lib,
-+				max_num_sw_c,
-+				max_partial_sw_c,
-+				swath_height_c,
-+				max_vinit_c,
-+				lsw);
-+
-+	DTRACE("DLG: %s: vratio_pre_l=%3.2f", __func__, vratio_pre_l);
-+	DTRACE("DLG: %s: vratio_pre_c=%3.2f", __func__, vratio_pre_c);
-+
-+	ASSERT(vratio_pre_l <= 4.0);
-+	if (vratio_pre_l >= 4.0)
-+		disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 21) - 1;
-+	else
-+		disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
-+
-+	ASSERT(vratio_pre_c <= 4.0);
-+	if (vratio_pre_c >= 4.0)
-+		disp_dlg_regs->vratio_prefetch_c = (unsigned int) dml_pow(2, 21) - 1;
-+	else
-+		disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
-+
-+	disp_dlg_regs->refcyc_per_pte_group_vblank_l =
-+			(unsigned int) (dst_y_per_row_vblank * (double) htotal
-+					* ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
-+	ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));
-+
-+	disp_dlg_regs->refcyc_per_pte_group_vblank_c =
-+			(unsigned int) (dst_y_per_row_vblank * (double) htotal
-+					* ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c);
-+	ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13));
-+
-+	disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
-+			(unsigned int) (dst_y_per_row_vblank * (double) htotal
-+					* ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
-+	ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
-+
-+	disp_dlg_regs->refcyc_per_meta_chunk_vblank_c =
-+			disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;/* dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now */
-+
-+	/* Active */
-+	req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
-+	req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
-+	meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
-+	swath_width_pixels_ub_l = 0;
-+	swath_width_pixels_ub_c = 0;
-+	scaler_rec_in_width_l = 0;
-+	scaler_rec_in_width_c = 0;
-+	dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
-+	dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
-+
-+	disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l
-+			/ (double) vratio_l * dml_pow(2, 2));
-+	ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));
-+
-+	disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c
-+			/ (double) vratio_c * dml_pow(2, 2));
-+	ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_c < (unsigned int) dml_pow(2, 17));
-+
-+	disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
-+			/ (double) vratio_l * dml_pow(2, 2));
-+	ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
-+
-+	disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; /* dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now */
-+
-+	disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l
-+			/ (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
-+			/ (double) dpte_groups_per_row_ub_l);
-+	if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
-+		disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
-+
-+	disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c
-+			/ (double) vratio_c * (double) htotal * ref_freq_to_pix_freq
-+			/ (double) dpte_groups_per_row_ub_c);
-+	if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
-+		disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
-+
-+	disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l
-+			/ (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
-+			/ (double) meta_chunks_per_row_ub_l);
-+	if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
-+		disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
-+
-+	if (mode_422) {
-+		swath_width_pixels_ub_l = swath_width_ub_l * 2; /* *2 for 2 pixel per element */
-+		swath_width_pixels_ub_c = swath_width_ub_c * 2;
-+	} else {
-+		swath_width_pixels_ub_l = swath_width_ub_l * 1;
-+		swath_width_pixels_ub_c = swath_width_ub_c * 1;
-+	}
-+
-+	hscale_pixel_rate_l = 0.;
-+	hscale_pixel_rate_c = 0.;
-+	min_hratio_fact_l = 1.0;
-+	min_hratio_fact_c = 1.0;
-+
-+	if (htaps_l <= 1)
-+		min_hratio_fact_l = 2.0;
-+	else if (htaps_l <= 6) {
-+		if ((hratios_l * 2.0) > 4.0)
-+			min_hratio_fact_l = 4.0;
-+		else
-+			min_hratio_fact_l = hratios_l * 2.0;
-+	} else {
-+		if (hratios_l > 4.0)
-+			min_hratio_fact_l = 4.0;
-+		else
-+			min_hratio_fact_l = hratios_l;
-+	}
-+
-+	hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
-+
-+	if (htaps_c <= 1)
-+		min_hratio_fact_c = 2.0;
-+	else if (htaps_c <= 6) {
-+		if ((hratios_c * 2.0) > 4.0)
-+			min_hratio_fact_c = 4.0;
-+		else
-+			min_hratio_fact_c = hratios_c * 2.0;
-+	} else {
-+		if (hratios_c > 4.0)
-+			min_hratio_fact_c = 4.0;
-+		else
-+			min_hratio_fact_c = hratios_c;
-+	}
-+
-+	hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
-+
-+	refcyc_per_line_delivery_pre_l = 0.;
-+	refcyc_per_line_delivery_pre_c = 0.;
-+	refcyc_per_line_delivery_l = 0.;
-+	refcyc_per_line_delivery_c = 0.;
-+
-+	refcyc_per_req_delivery_pre_l = 0.;
-+	refcyc_per_req_delivery_pre_c = 0.;
-+	refcyc_per_req_delivery_l = 0.;
-+	refcyc_per_req_delivery_c = 0.;
-+	refcyc_per_req_delivery_pre_cur0 = 0.;
-+	refcyc_per_req_delivery_cur0 = 0.;
-+
-+	full_recout_width = 0;
-+	if (e2e_pipe_param.pipe.src.is_hsplit) {
-+		if (e2e_pipe_param.pipe.dest.full_recout_width == 0) {
-+			DTRACE("DLG: %s: Warningfull_recout_width not set in hsplit mode", __func__);
-+			full_recout_width = e2e_pipe_param.pipe.dest.recout_width * 2; /* assume half split for dcn1 */
-+		} else
-+			full_recout_width = e2e_pipe_param.pipe.dest.full_recout_width;
-+	} else
-+		full_recout_width = e2e_pipe_param.pipe.dest.recout_width;
-+
-+	refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(
-+			mode_lib,
-+			refclk_freq_in_mhz,
-+			pclk_freq_in_mhz,
-+			full_recout_width,
-+			vratio_pre_l,
-+			hscale_pixel_rate_l,
-+			swath_width_pixels_ub_l,
-+			1); /* per line */
-+
-+	refcyc_per_line_delivery_l = get_refcyc_per_delivery(
-+			mode_lib,
-+			refclk_freq_in_mhz,
-+			pclk_freq_in_mhz,
-+			full_recout_width,
-+			vratio_l,
-+			hscale_pixel_rate_l,
-+			swath_width_pixels_ub_l,
-+			1); /* per line */
-+
-+	DTRACE("DLG: %s: full_recout_width              = %d", __func__, full_recout_width);
-+	DTRACE("DLG: %s: hscale_pixel_rate_l            = %3.2f", __func__, hscale_pixel_rate_l);
-+	DTRACE(
-+			"DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f",
-+			__func__,
-+			refcyc_per_line_delivery_pre_l);
-+	DTRACE(
-+			"DLG: %s: refcyc_per_line_delivery_l     = %3.2f",
-+			__func__,
-+			refcyc_per_line_delivery_l);
-+
-+	disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(
-+			refcyc_per_line_delivery_pre_l,
-+			1);
-+	disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(
-+			refcyc_per_line_delivery_l,
-+			1);
-+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
-+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));
-+
-+	if (dual_plane) {
-+		refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(
-+				mode_lib,
-+				refclk_freq_in_mhz,
-+				pclk_freq_in_mhz,
-+				full_recout_width,
-+				vratio_pre_c,
-+				hscale_pixel_rate_c,
-+				swath_width_pixels_ub_c,
-+				1); /* per line */
-+
-+		refcyc_per_line_delivery_c = get_refcyc_per_delivery(
-+				mode_lib,
-+				refclk_freq_in_mhz,
-+				pclk_freq_in_mhz,
-+				full_recout_width,
-+				vratio_c,
-+				hscale_pixel_rate_c,
-+				swath_width_pixels_ub_c,
-+				1); /* per line */
-+
-+		DTRACE(
-+				"DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f",
-+				__func__,
-+				refcyc_per_line_delivery_pre_c);
-+		DTRACE(
-+				"DLG: %s: refcyc_per_line_delivery_c     = %3.2f",
-+				__func__,
-+				refcyc_per_line_delivery_c);
-+
-+		disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(
-+				refcyc_per_line_delivery_pre_c,
-+				1);
-+		disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(
-+				refcyc_per_line_delivery_c,
-+				1);
-+		ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));
-+		ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));
-+	}
-+	disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
-+
-+	/* TTU - Luma / Chroma */
-+	if (access_dir) { /* vertical access */
-+		scaler_rec_in_width_l = vp_height_l;
-+		scaler_rec_in_width_c = vp_height_c;
-+	} else {
-+		scaler_rec_in_width_l = vp_width_l;
-+		scaler_rec_in_width_c = vp_width_c;
-+	}
-+
-+	refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(
-+			mode_lib,
-+			refclk_freq_in_mhz,
-+			pclk_freq_in_mhz,
-+			full_recout_width,
-+			vratio_pre_l,
-+			hscale_pixel_rate_l,
-+			scaler_rec_in_width_l,
-+			req_per_swath_ub_l); /* per req */
-+	refcyc_per_req_delivery_l = get_refcyc_per_delivery(
-+			mode_lib,
-+			refclk_freq_in_mhz,
-+			pclk_freq_in_mhz,
-+			full_recout_width,
-+			vratio_l,
-+			hscale_pixel_rate_l,
-+			scaler_rec_in_width_l,
-+			req_per_swath_ub_l); /* per req */
-+
-+	DTRACE(
-+			"DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f",
-+			__func__,
-+			refcyc_per_req_delivery_pre_l);
-+	DTRACE(
-+			"DLG: %s: refcyc_per_req_delivery_l     = %3.2f",
-+			__func__,
-+			refcyc_per_req_delivery_l);
-+
-+	disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l
-+			* dml_pow(2, 10));
-+	disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l
-+			* dml_pow(2, 10));
-+
-+	ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
-+	ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
-+
-+	if (dual_plane) {
-+		refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(
-+				mode_lib,
-+				refclk_freq_in_mhz,
-+				pclk_freq_in_mhz,
-+				full_recout_width,
-+				vratio_pre_c,
-+				hscale_pixel_rate_c,
-+				scaler_rec_in_width_c,
-+				req_per_swath_ub_c); /* per req  */
-+		refcyc_per_req_delivery_c = get_refcyc_per_delivery(
-+				mode_lib,
-+				refclk_freq_in_mhz,
-+				pclk_freq_in_mhz,
-+				full_recout_width,
-+				vratio_c,
-+				hscale_pixel_rate_c,
-+				scaler_rec_in_width_c,
-+				req_per_swath_ub_c); /* per req */
-+
-+		DTRACE(
-+				"DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f",
-+				__func__,
-+				refcyc_per_req_delivery_pre_c);
-+		DTRACE(
-+				"DLG: %s: refcyc_per_req_delivery_c     = %3.2f",
-+				__func__,
-+				refcyc_per_req_delivery_c);
-+
-+		disp_ttu_regs->refcyc_per_req_delivery_pre_c =
-+				(unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));
-+		disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c
-+				* dml_pow(2, 10));
-+
-+		ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
-+		ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
-+	}
-+
-+	/* TTU - Cursor */
-+	hratios_cur0 = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio;
-+	cur0_src_width = e2e_pipe_param.pipe.src.cur0_src_width; /* cursor source width */
-+	cur0_bpp = (enum cursor_bpp) e2e_pipe_param.pipe.src.cur0_bpp;
-+	cur0_req_size = 0;
-+	cur0_req_width = 0;
-+	cur0_width_ub = 0.0;
-+	cur0_req_per_width = 0.0;
-+	hactive_cur0 = 0.0;
-+
-+	ASSERT(cur0_src_width <= 256);
-+
-+	if (cur0_src_width > 0) {
-+		unsigned int cur0_bit_per_pixel = 0;
-+
-+		if (cur0_bpp == dm_cur_2bit) {
-+			cur0_req_size = 64; /* byte */
-+			cur0_bit_per_pixel = 2;
-+		} else { /* 32bit */
-+			cur0_bit_per_pixel = 32;
-+			if (cur0_src_width >= 1 && cur0_src_width <= 16)
-+				cur0_req_size = 64;
-+			else if (cur0_src_width >= 17 && cur0_src_width <= 31)
-+				cur0_req_size = 128;
-+			else
-+				cur0_req_size = 256;
-+		}
-+
-+		cur0_req_width = (double) cur0_req_size / ((double) cur0_bit_per_pixel / 8.0);
-+		cur0_width_ub = dml_ceil((double) cur0_src_width / (double) cur0_req_width, 1)
-+				* (double) cur0_req_width;
-+		cur0_req_per_width = cur0_width_ub / (double) cur0_req_width;
-+		hactive_cur0 = (double) cur0_src_width / hratios_cur0; /* FIXME: oswin to think about what to do for cursor */
-+
-+		if (vratio_pre_l <= 1.0) {
-+			refcyc_per_req_delivery_pre_cur0 = hactive_cur0 * ref_freq_to_pix_freq
-+					/ (double) cur0_req_per_width;
-+		} else {
-+			refcyc_per_req_delivery_pre_cur0 = (double) refclk_freq_in_mhz
-+					* (double) cur0_src_width / hscale_pixel_rate_l
-+					/ (double) cur0_req_per_width;
-+		}
-+
-+		disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 =
-+				(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
-+		ASSERT(refcyc_per_req_delivery_pre_cur0 < dml_pow(2, 13));
-+
-+		if (vratio_l <= 1.0) {
-+			refcyc_per_req_delivery_cur0 = hactive_cur0 * ref_freq_to_pix_freq
-+					/ (double) cur0_req_per_width;
-+		} else {
-+			refcyc_per_req_delivery_cur0 = (double) refclk_freq_in_mhz
-+					* (double) cur0_src_width / hscale_pixel_rate_l
-+					/ (double) cur0_req_per_width;
-+		}
-+
-+		DTRACE("DLG: %s: cur0_req_width                     = %d", __func__, cur0_req_width);
-+		DTRACE(
-+				"DLG: %s: cur0_width_ub                      = %3.2f",
-+				__func__,
-+				cur0_width_ub);
-+		DTRACE(
-+				"DLG: %s: cur0_req_per_width                 = %3.2f",
-+				__func__,
-+				cur0_req_per_width);
-+		DTRACE(
-+				"DLG: %s: hactive_cur0                       = %3.2f",
-+				__func__,
-+				hactive_cur0);
-+		DTRACE(
-+				"DLG: %s: refcyc_per_req_delivery_pre_cur0   = %3.2f",
-+				__func__,
-+				refcyc_per_req_delivery_pre_cur0);
-+		DTRACE(
-+				"DLG: %s: refcyc_per_req_delivery_cur0       = %3.2f",
-+				__func__,
-+				refcyc_per_req_delivery_cur0);
-+
-+		disp_ttu_regs->refcyc_per_req_delivery_cur0 =
-+				(unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));
-+		ASSERT(refcyc_per_req_delivery_cur0 < dml_pow(2, 13));
-+	} else {
-+		disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = 0;
-+		disp_ttu_regs->refcyc_per_req_delivery_cur0 = 0;
-+	}
-+
-+	/* TTU - Misc */
-+	disp_ttu_regs->qos_level_low_wm = 0;
-+	ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
-+	disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
-+			* ref_freq_to_pix_freq);
-+	ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
-+
-+	disp_ttu_regs->qos_level_flip = 14;
-+	disp_ttu_regs->qos_level_fixed_l = 8;
-+	disp_ttu_regs->qos_level_fixed_c = 8;
-+	disp_ttu_regs->qos_level_fixed_cur0 = 8;
-+	disp_ttu_regs->qos_ramp_disable_l = 0;
-+	disp_ttu_regs->qos_ramp_disable_c = 0;
-+	disp_ttu_regs->qos_ramp_disable_cur0 = 0;
-+
-+	disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
-+	ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
-+
-+	print__ttu_regs_st(mode_lib, *disp_ttu_regs);
-+	print__dlg_regs_st(mode_lib, *disp_dlg_regs);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.h.0130~	2017-12-14 06:39:58.428903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.h	2017-12-14 06:39:58.428903577 +0100
-@@ -0,0 +1,67 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DISPLAY_RQ_DLG_CALC_H__
-+#define __DISPLAY_RQ_DLG_CALC_H__
-+
-+#include "dml_common_defs.h"
-+#include "display_rq_dlg_helpers.h"
-+
-+struct display_mode_lib;
-+
-+void dml1_extract_rq_regs(
-+		struct display_mode_lib *mode_lib,
-+		struct _vcs_dpi_display_rq_regs_st *rq_regs,
-+		const struct _vcs_dpi_display_rq_params_st rq_param);
-+/* Function: dml_rq_dlg_get_rq_params
-+ *  Calculate requestor related parameters that register definition agnostic
-+ *  (i.e. this layer does try to separate real values from register definition)
-+ * Input:
-+ *  pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
-+ * Output:
-+ *  rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
-+ */
-+void dml1_rq_dlg_get_rq_params(
-+		struct display_mode_lib *mode_lib,
-+		struct _vcs_dpi_display_rq_params_st *rq_param,
-+		const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param);
-+
-+
-+/* Function: dml_rq_dlg_get_dlg_params
-+ *  Calculate deadline related parameters
-+ */
-+void dml1_rq_dlg_get_dlg_params(
-+		struct display_mode_lib *mode_lib,
-+		struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
-+		struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
-+		const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
-+		const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
-+		const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
-+		const bool cstate_en,
-+		const bool pstate_en,
-+		const bool vm_en,
-+		const bool iflip_en);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c.0130~	2017-12-14 06:39:58.428903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c	2017-12-14 06:39:58.428903577 +0100
-@@ -0,0 +1,43 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dml_common_defs.h"
-+#include "../calcs/dcn_calc_math.h"
-+
-+#include "dml_inline_defs.h"
-+
-+double dml_round(double a)
-+{
-+	double round_pt = 0.5;
-+	double ceil = dml_ceil(a, 1);
-+	double floor = dml_floor(a, 1);
-+
-+	if (a - floor >= round_pt)
-+		return ceil;
-+	else
-+		return floor;
-+}
-+
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h.0130~	2017-12-14 06:39:58.428903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h	2017-12-14 06:39:58.428903577 +0100
-@@ -0,0 +1,39 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_COMMON_DEFS_H__
-+#define __DC_COMMON_DEFS_H__
-+
-+#include "dm_services.h"
-+#include "dc_features.h"
-+#include "display_mode_structs.h"
-+#include "display_mode_enums.h"
-+
-+#define dml_print(str, ...) {dm_logger_write(mode_lib->logger, LOG_DML, str, ##__VA_ARGS__); }
-+#define DTRACE(str, ...) {dm_logger_write(mode_lib->logger, LOG_DML, str, ##__VA_ARGS__); }
-+
-+double dml_round(double a);
-+
-+#endif /* __DC_COMMON_DEFS_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h.0130~	2017-12-14 06:39:58.428903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h	2017-12-14 06:39:58.428903577 +0100
-@@ -0,0 +1,121 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DML_INLINE_DEFS_H__
-+#define __DML_INLINE_DEFS_H__
-+
-+#include "dml_common_defs.h"
-+#include "../calcs/dcn_calc_math.h"
-+
-+static inline double dml_min(double a, double b)
-+{
-+	return (double) dcn_bw_min2(a, b);
-+}
-+
-+static inline double dml_max(double a, double b)
-+{
-+	return (double) dcn_bw_max2(a, b);
-+}
-+
-+static inline double dml_max3(double a, double b, double c)
-+{
-+	return dml_max(dml_max(a, b), c);
-+}
-+
-+static inline double dml_max4(double a, double b, double c, double d)
-+{
-+	return dml_max(dml_max(a, b), dml_max(c, d));
-+}
-+
-+static inline double dml_max5(double a, double b, double c, double d, double e)
-+{
-+	return dml_max(dml_max4(a, b, c, d), e);
-+}
-+
-+static inline double dml_ceil(double a, double granularity)
-+{
-+	return (double) dcn_bw_ceil2(a, granularity);
-+}
-+
-+static inline double dml_floor(double a, double granularity)
-+{
-+	return (double) dcn_bw_floor2(a, granularity);
-+}
-+
-+static inline int dml_log2(double x)
-+{
-+	return dml_round((double)dcn_bw_log(x, 2));
-+}
-+
-+static inline double dml_pow(double a, int exp)
-+{
-+	return (double) dcn_bw_pow(a, exp);
-+}
-+
-+static inline double dml_fmod(double f, int val)
-+{
-+	return (double) dcn_bw_mod(f, val);
-+}
-+
-+static inline double dml_ceil_2(double f)
-+{
-+	return (double) dcn_bw_ceil2(f, 2);
-+}
-+
-+static inline double dml_ceil_ex(double x, double granularity)
-+{
-+	return (double) dcn_bw_ceil2(x, granularity);
-+}
-+
-+static inline double dml_floor_ex(double x, double granularity)
-+{
-+	return (double) dcn_bw_floor2(x, granularity);
-+}
-+
-+static inline double dml_log(double x, double base)
-+{
-+	return (double) dcn_bw_log(x, base);
-+}
-+
-+static inline unsigned int dml_round_to_multiple(unsigned int num,
-+						 unsigned int multiple,
-+						 bool up)
-+{
-+	unsigned int remainder;
-+
-+	if (multiple == 0)
-+		return num;
-+
-+	remainder = num % multiple;
-+
-+	if (remainder == 0)
-+		return num;
-+
-+	if (up)
-+		return (num + multiple - remainder);
-+	else
-+		return (num - remainder);
-+}
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/Makefile.0130~	2017-12-14 06:39:58.428903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/Makefile	2017-12-14 06:39:58.428903577 +0100
-@@ -0,0 +1,22 @@
-+#
-+# Makefile for the 'utils' sub-component of DAL.
-+# It provides the general basic services required by other DAL
-+# subcomponents.
-+
-+CFLAGS_display_mode_vba.o := -mhard-float -msse -mpreferred-stack-boundary=4
-+CFLAGS_display_mode_lib.o := -mhard-float -msse -mpreferred-stack-boundary=4
-+CFLAGS_display_pipe_clocks.o := -mhard-float -msse -mpreferred-stack-boundary=4
-+CFLAGS_display_rq_dlg_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4
-+CFLAGS_dml1_display_rq_dlg_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4
-+CFLAGS_display_rq_dlg_helpers.o := -mhard-float -msse -mpreferred-stack-boundary=4
-+CFLAGS_soc_bounding_box.o := -mhard-float -msse -mpreferred-stack-boundary=4
-+CFLAGS_dml_common_defs.o := -mhard-float -msse -mpreferred-stack-boundary=4
-+
-+
-+DML = display_mode_lib.o display_rq_dlg_calc.o \
-+	  display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
-+	  soc_bounding_box.o dml_common_defs.o display_mode_vba.o
-+
-+AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_DML)
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c.0130~	2017-12-14 06:39:58.428903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c	2017-12-14 06:39:58.428903577 +0100
-@@ -0,0 +1,69 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#include "soc_bounding_box.h"
-+#include "display_mode_lib.h"
-+#include "dc_features.h"
-+
-+#include "dml_inline_defs.h"
-+void dml_socbb_set_latencies(soc_bounding_box_st *to_box, soc_bounding_box_st *from_box)
-+{
-+	to_box->dram_clock_change_latency_us = from_box->dram_clock_change_latency_us;
-+	to_box->sr_exit_time_us = from_box->sr_exit_time_us;
-+	to_box->sr_enter_plus_exit_time_us = from_box->sr_enter_plus_exit_time_us;
-+	to_box->urgent_latency_us = from_box->urgent_latency_us;
-+	to_box->writeback_latency_us = from_box->writeback_latency_us;
-+}
-+
-+voltage_scaling_st dml_socbb_voltage_scaling(
-+		const soc_bounding_box_st *soc,
-+		enum voltage_state voltage)
-+{
-+	const voltage_scaling_st *voltage_state;
-+	const voltage_scaling_st * const voltage_end = soc->clock_limits + DC__VOLTAGE_STATES;
-+
-+	for (voltage_state = soc->clock_limits;
-+			voltage_state < voltage_end && voltage_state->state != voltage;
-+			voltage_state++) {
-+	}
-+
-+	if (voltage_state < voltage_end)
-+		return *voltage_state;
-+	return soc->clock_limits[DC__VOLTAGE_STATES - 1];
-+}
-+
-+double dml_socbb_return_bw_mhz(soc_bounding_box_st *box, enum voltage_state voltage)
-+{
-+	double return_bw;
-+
-+	voltage_scaling_st state = dml_socbb_voltage_scaling(box, voltage);
-+
-+	return_bw = dml_min((double) box->return_bus_width_bytes * state.dcfclk_mhz,
-+			state.dram_bw_per_chan_gbps * 1000.0 * (double) box->num_chans
-+					* box->ideal_dram_bw_after_urgent_percent / 100.0);
-+
-+	return_bw = dml_min((double) box->return_bus_width_bytes * state.fabricclk_mhz, return_bw);
-+
-+	return return_bw;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.h.0130~	2017-12-14 06:39:58.428903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.h	2017-12-14 06:39:58.428903577 +0100
-@@ -0,0 +1,35 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __SOC_BOUNDING_BOX_H__
-+#define __SOC_BOUNDING_BOX_H__
-+
-+#include "dml_common_defs.h"
-+
-+void dml_socbb_set_latencies(soc_bounding_box_st *to_box, soc_bounding_box_st *from_box);
-+voltage_scaling_st dml_socbb_voltage_scaling(const soc_bounding_box_st *box, enum voltage_state voltage);
-+double dml_socbb_return_bw_mhz(soc_bounding_box_st *box, enum voltage_state voltage);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h.0130~	2017-12-14 06:39:58.429903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h	2017-12-14 06:39:58.429903577 +0100
-@@ -0,0 +1,131 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef DM_PP_SMU_IF__H
-+#define DM_PP_SMU_IF__H
-+
-+/*
-+ * interface to PPLIB/SMU to setup clocks and pstate requirements on SoC
-+ */
-+
-+
-+struct pp_smu {
-+	struct dc_context *ctx;
-+};
-+
-+enum wm_set_id {
-+	WM_A,
-+	WM_B,
-+	WM_C,
-+	WM_D,
-+	WM_COUNT,
-+};
-+
-+struct pp_smu_wm_set_range {
-+	enum wm_set_id wm_inst;
-+	uint32_t min_fill_clk_khz;
-+	uint32_t max_fill_clk_khz;
-+	uint32_t min_drain_clk_khz;
-+	uint32_t max_drain_clk_khz;
-+};
-+
-+struct pp_smu_wm_range_sets {
-+	uint32_t num_reader_wm_sets;
-+	struct pp_smu_wm_set_range reader_wm_sets[WM_COUNT];
-+
-+	uint32_t num_writer_wm_sets;
-+	struct pp_smu_wm_set_range writer_wm_sets[WM_COUNT];
-+};
-+
-+struct pp_smu_display_requirement_rv {
-+	/* PPSMC_MSG_SetDisplayCount: count
-+	 *  0 triggers S0i2 optimization
-+	 */
-+	unsigned int display_count;
-+
-+	/* PPSMC_MSG_SetHardMinFclkByFreq: khz
-+	 *  FCLK will vary with DPM, but never below requested hard min
-+	 */
-+	unsigned int hard_min_fclk_khz;
-+
-+	/* PPSMC_MSG_SetHardMinDcefclkByFreq: khz
-+	 *  fixed clock at requested freq, either from FCH bypass or DFS
-+	 */
-+	unsigned int hard_min_dcefclk_khz;
-+
-+	/* PPSMC_MSG_SetMinDeepSleepDcefclk: mhz
-+	 *  when DF is in cstate, dcf clock is further divided down
-+	 *  to just above given frequency
-+	 */
-+	unsigned int min_deep_sleep_dcefclk_mhz;
-+};
-+
-+struct pp_smu_funcs_rv {
-+	struct pp_smu pp_smu;
-+
-+	void (*set_display_requirement)(struct pp_smu *pp,
-+			struct pp_smu_display_requirement_rv *req);
-+
-+	/* which SMU message?  are reader and writer WM separate SMU msg? */
-+	void (*set_wm_ranges)(struct pp_smu *pp,
-+			struct pp_smu_wm_range_sets *ranges);
-+
-+};
-+
-+#if 0
-+struct pp_smu_funcs_rv {
-+
-+	/* PPSMC_MSG_SetDisplayCount
-+	 *  0 triggers S0i2 optimization
-+	 */
-+	void (*set_display_count)(struct pp_smu *pp, int count);
-+
-+	/* PPSMC_MSG_SetHardMinFclkByFreq
-+	 *  FCLK will vary with DPM, but never below requested hard min
-+	 */
-+	void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int khz);
-+
-+	/* PPSMC_MSG_SetHardMinDcefclkByFreq
-+	 *  fixed clock at requested freq, either from FCH bypass or DFS
-+	 */
-+	void (*set_hard_min_dcefclk_by_freq)(struct pp_smu *pp, int khz);
-+
-+	/* PPSMC_MSG_SetMinDeepSleepDcefclk
-+	 *  when DF is in cstate, dcf clock is further divided down
-+	 *  to just above given frequency
-+	 */
-+	void (*set_min_deep_sleep_dcefclk)(struct pp_smu *pp, int mhz);
-+
-+	/* todo: aesthetic
-+	 * watermark range table
-+	 */
-+
-+	/* todo: functional/feature
-+	 * PPSMC_MSG_SetHardMinSocclkByFreq: required to support DWB
-+	 */
-+};
-+#endif
-+
-+#endif /* DM_PP_SMU_IF__H */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dm_services.h.0130~	2017-12-14 06:39:58.429903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dm_services.h	2017-12-14 06:39:58.429903577 +0100
-@@ -0,0 +1,387 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/**
-+ * This file defines external dependencies of Display Core.
-+ */
-+
-+#ifndef __DM_SERVICES_H__
-+
-+#define __DM_SERVICES_H__
-+
-+/* TODO: remove when DC is complete. */
-+#include "dm_services_types.h"
-+#include "logger_interface.h"
-+#include "link_service_types.h"
-+
-+#undef DEPRECATED
-+
-+irq_handler_idx dm_register_interrupt(
-+	struct dc_context *ctx,
-+	struct dc_interrupt_params *int_params,
-+	interrupt_handler ih,
-+	void *handler_args);
-+
-+
-+/*
-+ *
-+ * GPU registers access
-+ *
-+ */
-+
-+/* enable for debugging new code, this adds 50k to the driver size. */
-+/* #define DM_CHECK_ADDR_0 */
-+
-+#define dm_read_reg(ctx, address)	\
-+		dm_read_reg_func(ctx, address, __func__)
-+
-+static inline uint32_t dm_read_reg_func(
-+	const struct dc_context *ctx,
-+	uint32_t address,
-+	const char *func_name)
-+{
-+	uint32_t value;
-+#ifdef DM_CHECK_ADDR_0
-+	if (address == 0) {
-+		DC_ERR("invalid register read; address = 0\n");
-+		return 0;
-+	}
-+#endif
-+	value = cgs_read_register(ctx->cgs_device, address);
-+
-+	return value;
-+}
-+
-+#define dm_write_reg(ctx, address, value)	\
-+	dm_write_reg_func(ctx, address, value, __func__)
-+
-+static inline void dm_write_reg_func(
-+	const struct dc_context *ctx,
-+	uint32_t address,
-+	uint32_t value,
-+	const char *func_name)
-+{
-+#ifdef DM_CHECK_ADDR_0
-+	if (address == 0) {
-+		DC_ERR("invalid register write. address = 0");
-+		return;
-+	}
-+#endif
-+	cgs_write_register(ctx->cgs_device, address, value);
-+}
-+
-+static inline uint32_t dm_read_index_reg(
-+	const struct dc_context *ctx,
-+	enum cgs_ind_reg addr_space,
-+	uint32_t index)
-+{
-+	return cgs_read_ind_register(ctx->cgs_device, addr_space, index);
-+}
-+
-+static inline void dm_write_index_reg(
-+	const struct dc_context *ctx,
-+	enum cgs_ind_reg addr_space,
-+	uint32_t index,
-+	uint32_t value)
-+{
-+	cgs_write_ind_register(ctx->cgs_device, addr_space, index, value);
-+}
-+
-+static inline uint32_t get_reg_field_value_ex(
-+	uint32_t reg_value,
-+	uint32_t mask,
-+	uint8_t shift)
-+{
-+	return (mask & reg_value) >> shift;
-+}
-+
-+#define get_reg_field_value(reg_value, reg_name, reg_field)\
-+	get_reg_field_value_ex(\
-+		(reg_value),\
-+		reg_name ## __ ## reg_field ## _MASK,\
-+		reg_name ## __ ## reg_field ## __SHIFT)
-+
-+static inline uint32_t set_reg_field_value_ex(
-+	uint32_t reg_value,
-+	uint32_t value,
-+	uint32_t mask,
-+	uint8_t shift)
-+{
-+	ASSERT(mask != 0);
-+	return (reg_value & ~mask) | (mask & (value << shift));
-+}
-+
-+#define set_reg_field_value(reg_value, value, reg_name, reg_field)\
-+	(reg_value) = set_reg_field_value_ex(\
-+		(reg_value),\
-+		(value),\
-+		reg_name ## __ ## reg_field ## _MASK,\
-+		reg_name ## __ ## reg_field ## __SHIFT)
-+
-+uint32_t generic_reg_update_ex(const struct dc_context *ctx,
-+		uint32_t addr, uint32_t reg_val, int n,
-+		uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
-+
-+#define FD(reg_field)	reg_field ## __SHIFT, \
-+						reg_field ## _MASK
-+
-+/*
-+ * return number of poll before condition is met
-+ * return 0 if condition is not meet after specified time out tries
-+ */
-+unsigned int generic_reg_wait(const struct dc_context *ctx,
-+	uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value,
-+	unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
-+	const char *func_name, int line);
-+
-+
-+/* These macros need to be used with soc15 registers in order to retrieve
-+ * the actual offset.
-+ */
-+#define dm_write_reg_soc15(ctx, reg, inst_offset, value)	\
-+		dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__)
-+
-+#define dm_read_reg_soc15(ctx, reg, inst_offset)	\
-+		dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__)
-+
-+#define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\
-+		generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] +  mm##reg_name + inst_offset, \
-+		dm_read_reg_func(ctx, mm##reg_name + DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + inst_offset, __func__), \
-+		n, __VA_ARGS__)
-+
-+#define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\
-+		generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \
-+		n, __VA_ARGS__)
-+
-+#define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\
-+	get_reg_field_value_ex(\
-+		(reg_value),\
-+		block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
-+		block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
-+
-+#define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\
-+	(reg_value) = set_reg_field_value_ex(\
-+		(reg_value),\
-+		(value),\
-+		block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
-+		block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
-+
-+/**************************************
-+ * Power Play (PP) interfaces
-+ **************************************/
-+
-+/* DAL calls this function to notify PP about clocks it needs for the Mode Set.
-+ * This is done *before* it changes DCE clock.
-+ *
-+ * If required clock is higher than current, then PP will increase the voltage.
-+ *
-+ * If required clock is lower than current, then PP will defer reduction of
-+ * voltage until the call to dc_service_pp_post_dce_clock_change().
-+ *
-+ * \input - Contains clocks needed for Mode Set.
-+ *
-+ * \output - Contains clocks adjusted by PP which DAL should use for Mode Set.
-+ *		Valid only if function returns zero.
-+ *
-+ * \returns	true - call is successful
-+ *		false - call failed
-+ */
-+bool dm_pp_pre_dce_clock_change(
-+	struct dc_context *ctx,
-+	struct dm_pp_gpu_clock_range *requested_state,
-+	struct dm_pp_gpu_clock_range *actual_state);
-+
-+/* The returned clocks range are 'static' system clocks which will be used for
-+ * mode validation purposes.
-+ *
-+ * \returns	true - call is successful
-+ *		false - call failed
-+ */
-+bool dc_service_get_system_clocks_range(
-+	const struct dc_context *ctx,
-+	struct dm_pp_gpu_clock_range *sys_clks);
-+
-+/* Gets valid clocks levels from pplib
-+ *
-+ * input: clk_type - display clk / sclk / mem clk
-+ *
-+ * output: array of valid clock levels for given type in ascending order,
-+ * with invalid levels filtered out
-+ *
-+ */
-+bool dm_pp_get_clock_levels_by_type(
-+	const struct dc_context *ctx,
-+	enum dm_pp_clock_type clk_type,
-+	struct dm_pp_clock_levels *clk_level_info);
-+
-+bool dm_pp_get_clock_levels_by_type_with_latency(
-+	const struct dc_context *ctx,
-+	enum dm_pp_clock_type clk_type,
-+	struct dm_pp_clock_levels_with_latency *clk_level_info);
-+
-+bool dm_pp_get_clock_levels_by_type_with_voltage(
-+	const struct dc_context *ctx,
-+	enum dm_pp_clock_type clk_type,
-+	struct dm_pp_clock_levels_with_voltage *clk_level_info);
-+
-+bool dm_pp_notify_wm_clock_changes(
-+	const struct dc_context *ctx,
-+	struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);
-+
-+void dm_pp_get_funcs_rv(struct dc_context *ctx,
-+		struct pp_smu_funcs_rv *funcs);
-+
-+/* DAL calls this function to notify PP about completion of Mode Set.
-+ * For PP it means that current DCE clocks are those which were returned
-+ * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
-+ *
-+ * If the clocks are higher than before, then PP does nothing.
-+ *
-+ * If the clocks are lower than before, then PP reduces the voltage.
-+ *
-+ * \returns	true - call is successful
-+ *		false - call failed
-+ */
-+bool dm_pp_apply_display_requirements(
-+	const struct dc_context *ctx,
-+	const struct dm_pp_display_configuration *pp_display_cfg);
-+
-+bool dm_pp_apply_power_level_change_request(
-+	const struct dc_context *ctx,
-+	struct dm_pp_power_level_change_request *level_change_req);
-+
-+bool dm_pp_apply_clock_for_voltage_request(
-+	const struct dc_context *ctx,
-+	struct dm_pp_clock_for_voltage_req *clock_for_voltage_req);
-+
-+bool dm_pp_get_static_clocks(
-+	const struct dc_context *ctx,
-+	struct dm_pp_static_clock_info *static_clk_info);
-+
-+/****** end of PP interfaces ******/
-+
-+struct persistent_data_flag {
-+	bool save_per_link;
-+	bool save_per_edid;
-+};
-+
-+/* Call to write data in registry editor for persistent data storage.
-+ *
-+ * \inputs      sink - identify edid/link for registry folder creation
-+ *              module name - identify folders for registry
-+ *              key name - identify keys within folders for registry
-+ *              params - value to write in defined folder/key
-+ *              size - size of the input params
-+ *              flag - determine whether to save by link or edid
-+ *
-+ * \returns     true - call is successful
-+ *              false - call failed
-+ *
-+ * sink         module         key
-+ * -----------------------------------------------------------------------------
-+ * NULL         NULL           NULL     - failure
-+ * NULL         NULL           -        - create key with param value
-+ *                                                      under base folder
-+ * NULL         -              NULL     - create module folder under base folder
-+ * -            NULL           NULL     - failure
-+ * NULL         -              -        - create key under module folder
-+ *                                            with no edid/link identification
-+ * -            NULL           -        - create key with param value
-+ *                                                       under base folder
-+ * -            -              NULL     - create module folder under base folder
-+ * -            -              -        - create key under module folder
-+ *                                              with edid/link identification
-+ */
-+bool dm_write_persistent_data(struct dc_context *ctx,
-+		const struct dc_sink *sink,
-+		const char *module_name,
-+		const char *key_name,
-+		void *params,
-+		unsigned int size,
-+		struct persistent_data_flag *flag);
-+
-+
-+/* Call to read data in registry editor for persistent data storage.
-+ *
-+ * \inputs      sink - identify edid/link for registry folder creation
-+ *              module name - identify folders for registry
-+ *              key name - identify keys within folders for registry
-+ *              size - size of the output params
-+ *              flag - determine whether it was save by link or edid
-+ *
-+ * \returns     params - value read from defined folder/key
-+ *              true - call is successful
-+ *              false - call failed
-+ *
-+ * sink         module         key
-+ * -----------------------------------------------------------------------------
-+ * NULL         NULL           NULL     - failure
-+ * NULL         NULL           -        - read key under base folder
-+ * NULL         -              NULL     - failure
-+ * -            NULL           NULL     - failure
-+ * NULL         -              -        - read key under module folder
-+ *                                             with no edid/link identification
-+ * -            NULL           -        - read key under base folder
-+ * -            -              NULL     - failure
-+ * -            -              -        - read key under module folder
-+ *                                              with edid/link identification
-+ */
-+bool dm_read_persistent_data(struct dc_context *ctx,
-+		const struct dc_sink *sink,
-+		const char *module_name,
-+		const char *key_name,
-+		void *params,
-+		unsigned int size,
-+		struct persistent_data_flag *flag);
-+
-+bool dm_query_extended_brightness_caps
-+	(struct dc_context *ctx, enum dm_acpi_display_type display,
-+			struct dm_acpi_atif_backlight_caps *pCaps);
-+
-+bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);
-+
-+/*
-+ *
-+ * print-out services
-+ *
-+ */
-+#define dm_log_to_buffer(buffer, size, fmt, args)\
-+	vsnprintf(buffer, size, fmt, args)
-+
-+unsigned long long dm_get_timestamp(struct dc_context *ctx);
-+
-+/*
-+ * Debug and verification hooks
-+ */
-+bool dm_helpers_dc_conn_log(
-+		struct dc_context *ctx,
-+		struct log_entry *entry,
-+		enum dc_log_type event);
-+
-+void dm_dtn_log_begin(struct dc_context *ctx);
-+void dm_dtn_log_append_v(struct dc_context *ctx, const char *msg, ...);
-+void dm_dtn_log_end(struct dc_context *ctx);
-+
-+#endif /* __DM_SERVICES_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/dm_services_types.h.0130~	2017-12-14 06:39:58.429903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/dm_services_types.h	2017-12-14 06:39:58.429903577 +0100
-@@ -0,0 +1,282 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DM_SERVICES_TYPES_H__
-+#define __DM_SERVICES_TYPES_H__
-+
-+#include "os_types.h"
-+#include "dc_types.h"
-+
-+#include "dm_pp_smu.h"
-+
-+struct dm_pp_clock_range {
-+	int min_khz;
-+	int max_khz;
-+};
-+
-+enum dm_pp_clocks_state {
-+	DM_PP_CLOCKS_STATE_INVALID,
-+	DM_PP_CLOCKS_STATE_ULTRA_LOW,
-+	DM_PP_CLOCKS_STATE_LOW,
-+	DM_PP_CLOCKS_STATE_NOMINAL,
-+	DM_PP_CLOCKS_STATE_PERFORMANCE,
-+
-+	/* Starting from DCE11, Max 8 levels of DPM state supported. */
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DM_PP_CLOCKS_STATE_INVALID,
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_0,
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_1,
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_2,
-+	/* to be backward compatible */
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_3,
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_4,
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_5,
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_6,
-+	DM_PP_CLOCKS_DPM_STATE_LEVEL_7,
-+
-+	DM_PP_CLOCKS_MAX_STATES
-+};
-+
-+struct dm_pp_gpu_clock_range {
-+	enum dm_pp_clocks_state clock_state;
-+	struct dm_pp_clock_range sclk;
-+	struct dm_pp_clock_range mclk;
-+	struct dm_pp_clock_range eclk;
-+	struct dm_pp_clock_range dclk;
-+};
-+
-+enum dm_pp_clock_type {
-+	DM_PP_CLOCK_TYPE_DISPLAY_CLK = 1,
-+	DM_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */
-+	DM_PP_CLOCK_TYPE_MEMORY_CLK,
-+	DM_PP_CLOCK_TYPE_DCFCLK,
-+	DM_PP_CLOCK_TYPE_DCEFCLK,
-+	DM_PP_CLOCK_TYPE_SOCCLK,
-+	DM_PP_CLOCK_TYPE_PIXELCLK,
-+	DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
-+	DM_PP_CLOCK_TYPE_DPPCLK,
-+	DM_PP_CLOCK_TYPE_FCLK,
-+};
-+
-+#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
-+	(clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
-+	(clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
-+	(clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : "Invalid"
-+
-+#define DM_PP_MAX_CLOCK_LEVELS 8
-+
-+struct dm_pp_clock_levels {
-+	uint32_t num_levels;
-+	uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS];
-+};
-+
-+struct dm_pp_clock_with_latency {
-+	uint32_t clocks_in_khz;
-+	uint32_t latency_in_us;
-+};
-+
-+struct dm_pp_clock_levels_with_latency {
-+	uint32_t num_levels;
-+	struct dm_pp_clock_with_latency data[DM_PP_MAX_CLOCK_LEVELS];
-+};
-+
-+struct dm_pp_clock_with_voltage {
-+	uint32_t clocks_in_khz;
-+	uint32_t voltage_in_mv;
-+};
-+
-+struct dm_pp_clock_levels_with_voltage {
-+	uint32_t num_levels;
-+	struct dm_pp_clock_with_voltage data[DM_PP_MAX_CLOCK_LEVELS];
-+};
-+
-+struct dm_pp_single_disp_config {
-+	enum signal_type signal;
-+	uint8_t transmitter;
-+	uint8_t ddi_channel_mapping;
-+	uint8_t pipe_idx;
-+	uint32_t src_height;
-+	uint32_t src_width;
-+	uint32_t v_refresh;
-+	uint32_t sym_clock; /* HDMI only */
-+	struct dc_link_settings link_settings; /* DP only */
-+};
-+
-+#define MAX_WM_SETS 4
-+
-+enum dm_pp_wm_set_id {
-+	WM_SET_A = 0,
-+	WM_SET_B,
-+	WM_SET_C,
-+	WM_SET_D,
-+	WM_SET_INVALID = 0xffff,
-+};
-+
-+struct dm_pp_clock_range_for_wm_set {
-+	enum dm_pp_wm_set_id wm_set_id;
-+	uint32_t wm_min_eng_clk_in_khz;
-+	uint32_t wm_max_eng_clk_in_khz;
-+	uint32_t wm_min_memg_clk_in_khz;
-+	uint32_t wm_max_mem_clk_in_khz;
-+};
-+
-+struct dm_pp_wm_sets_with_clock_ranges {
-+	uint32_t num_wm_sets;
-+	struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS];
-+};
-+
-+struct dm_pp_clock_range_for_dmif_wm_set_soc15 {
-+	enum dm_pp_wm_set_id wm_set_id;
-+	uint32_t wm_min_dcfclk_clk_in_khz;
-+	uint32_t wm_max_dcfclk_clk_in_khz;
-+	uint32_t wm_min_memg_clk_in_khz;
-+	uint32_t wm_max_mem_clk_in_khz;
-+};
-+
-+struct dm_pp_clock_range_for_mcif_wm_set_soc15 {
-+	enum dm_pp_wm_set_id wm_set_id;
-+	uint32_t wm_min_socclk_clk_in_khz;
-+	uint32_t wm_max_socclk_clk_in_khz;
-+	uint32_t wm_min_memg_clk_in_khz;
-+	uint32_t wm_max_mem_clk_in_khz;
-+};
-+
-+struct dm_pp_wm_sets_with_clock_ranges_soc15 {
-+	uint32_t num_wm_dmif_sets;
-+	uint32_t num_wm_mcif_sets;
-+	struct dm_pp_clock_range_for_dmif_wm_set_soc15
-+		wm_dmif_clocks_ranges[MAX_WM_SETS];
-+	struct dm_pp_clock_range_for_mcif_wm_set_soc15
-+		wm_mcif_clocks_ranges[MAX_WM_SETS];
-+};
-+
-+#define MAX_DISPLAY_CONFIGS 6
-+
-+struct dm_pp_display_configuration {
-+	bool nb_pstate_switch_disable;/* controls NB PState switch */
-+	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
-+	bool cpu_pstate_disable;
-+	uint32_t cpu_pstate_separation_time;
-+
-+	uint32_t min_memory_clock_khz;
-+	uint32_t min_engine_clock_khz;
-+	uint32_t min_engine_clock_deep_sleep_khz;
-+
-+	uint32_t avail_mclk_switch_time_us;
-+	uint32_t avail_mclk_switch_time_in_disp_active_us;
-+	uint32_t min_dcfclock_khz;
-+	uint32_t min_dcfc_deep_sleep_clock_khz;
-+
-+	uint32_t disp_clk_khz;
-+
-+	bool all_displays_in_sync;
-+
-+	uint8_t display_count;
-+	struct dm_pp_single_disp_config disp_configs[MAX_DISPLAY_CONFIGS];
-+
-+	/*Controller Index of primary display - used in MCLK SMC switching hang
-+	 * SW Workaround*/
-+	uint8_t crtc_index;
-+	/*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
-+	uint32_t line_time_in_us;
-+};
-+
-+struct dm_bl_data_point {
-+		/* Brightness level in percentage */
-+		uint8_t luminance;
-+		/* Brightness level as effective value in range 0-255,
-+		 * corresponding to above percentage
-+		 */
-+		uint8_t signalLevel;
-+};
-+
-+/* Total size of the structure should not exceed 256 bytes */
-+struct dm_acpi_atif_backlight_caps {
-+
-+
-+	uint16_t size; /* Bytes 0-1 (2 bytes) */
-+	uint16_t flags; /* Byted 2-3 (2 bytes) */
-+	uint8_t  errorCode; /* Byte 4 */
-+	uint8_t  acLevelPercentage; /* Byte 5 */
-+	uint8_t  dcLevelPercentage; /* Byte 6 */
-+	uint8_t  minInputSignal; /* Byte 7 */
-+	uint8_t  maxInputSignal; /* Byte 8 */
-+	uint8_t  numOfDataPoints; /* Byte 9 */
-+	struct dm_bl_data_point dataPoints[99]; /* Bytes 10-207 (198 bytes)*/
-+};
-+
-+enum dm_acpi_display_type {
-+	AcpiDisplayType_LCD1 = 0,
-+	AcpiDisplayType_CRT1 = 1,
-+	AcpiDisplayType_DFP1 = 3,
-+	AcpiDisplayType_CRT2 = 4,
-+	AcpiDisplayType_LCD2 = 5,
-+	AcpiDisplayType_DFP2 = 7,
-+	AcpiDisplayType_DFP3 = 9,
-+	AcpiDisplayType_DFP4 = 10,
-+	AcpiDisplayType_DFP5 = 11,
-+	AcpiDisplayType_DFP6 = 12
-+};
-+
-+enum dm_pp_power_level {
-+	DM_PP_POWER_LEVEL_INVALID,
-+	DM_PP_POWER_LEVEL_ULTRA_LOW,
-+	DM_PP_POWER_LEVEL_LOW,
-+	DM_PP_POWER_LEVEL_NOMINAL,
-+	DM_PP_POWER_LEVEL_PERFORMANCE,
-+
-+	DM_PP_POWER_LEVEL_0 = DM_PP_POWER_LEVEL_ULTRA_LOW,
-+	DM_PP_POWER_LEVEL_1 = DM_PP_POWER_LEVEL_LOW,
-+	DM_PP_POWER_LEVEL_2 = DM_PP_POWER_LEVEL_NOMINAL,
-+	DM_PP_POWER_LEVEL_3 = DM_PP_POWER_LEVEL_PERFORMANCE,
-+	DM_PP_POWER_LEVEL_4 = DM_PP_CLOCKS_DPM_STATE_LEVEL_3 + 1,
-+	DM_PP_POWER_LEVEL_5 = DM_PP_CLOCKS_DPM_STATE_LEVEL_4 + 1,
-+	DM_PP_POWER_LEVEL_6 = DM_PP_CLOCKS_DPM_STATE_LEVEL_5 + 1,
-+	DM_PP_POWER_LEVEL_7 = DM_PP_CLOCKS_DPM_STATE_LEVEL_6 + 1,
-+};
-+
-+struct dm_pp_power_level_change_request {
-+	enum dm_pp_power_level power_level;
-+};
-+
-+struct dm_pp_clock_for_voltage_req {
-+	enum dm_pp_clock_type clk_type;
-+	uint32_t clocks_in_khz;
-+};
-+
-+struct dm_pp_static_clock_info {
-+	uint32_t max_sclk_khz;
-+	uint32_t max_mclk_khz;
-+
-+	/* max possible display block clocks state */
-+	enum dm_pp_clocks_state max_clocks_state;
-+};
-+
-+struct dtn_min_clk_info {
-+	uint32_t disp_clk_khz;
-+	uint32_t min_engine_clock_khz;
-+	uint32_t min_memory_clock_khz;
-+};
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c.0130~	2017-12-14 06:39:58.429903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c	2017-12-14 06:39:58.429903577 +0100
-@@ -0,0 +1,178 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "include/gpio_types.h"
-+#include "../hw_factory.h"
-+
-+#include "hw_factory_dce110.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+/* set field name */
-+#define SF_HPD(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+#define REG(reg_name)\
-+		mm ## reg_name
-+
-+#define REGI(reg_name, block, id)\
-+	mm ## block ## id ## _ ## reg_name
-+
-+#include "../hw_gpio.h"
-+#include "../hw_ddc.h"
-+#include "../hw_hpd.h"
-+
-+#include "reg_helper.h"
-+#include "../hpd_regs.h"
-+
-+#define hpd_regs(id) \
-+{\
-+	HPD_REG_LIST(id)\
-+}
-+
-+static const struct hpd_registers hpd_regs[] = {
-+	hpd_regs(0),
-+	hpd_regs(1),
-+	hpd_regs(2),
-+	hpd_regs(3),
-+	hpd_regs(4),
-+	hpd_regs(5)
-+};
-+
-+static const struct hpd_sh_mask hpd_shift = {
-+		HPD_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct hpd_sh_mask hpd_mask = {
-+		HPD_MASK_SH_LIST(_MASK)
-+};
-+
-+#include "../ddc_regs.h"
-+
-+ /* set field name */
-+#define SF_DDC(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+static const struct ddc_registers ddc_data_regs[] = {
-+	ddc_data_regs(1),
-+	ddc_data_regs(2),
-+	ddc_data_regs(3),
-+	ddc_data_regs(4),
-+	ddc_data_regs(5),
-+	ddc_data_regs(6),
-+	ddc_vga_data_regs,
-+	ddc_i2c_data_regs
-+};
-+
-+static const struct ddc_registers ddc_clk_regs[] = {
-+	ddc_clk_regs(1),
-+	ddc_clk_regs(2),
-+	ddc_clk_regs(3),
-+	ddc_clk_regs(4),
-+	ddc_clk_regs(5),
-+	ddc_clk_regs(6),
-+	ddc_vga_clk_regs,
-+	ddc_i2c_clk_regs
-+};
-+
-+static const struct ddc_sh_mask ddc_shift = {
-+		DDC_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct ddc_sh_mask ddc_mask = {
-+		DDC_MASK_SH_LIST(_MASK)
-+};
-+
-+static void define_ddc_registers(
-+		struct hw_gpio_pin *pin,
-+		uint32_t en)
-+{
-+	struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
-+
-+	switch (pin->id) {
-+	case GPIO_ID_DDC_DATA:
-+		ddc->regs = &ddc_data_regs[en];
-+		ddc->base.regs = &ddc_data_regs[en].gpio;
-+		break;
-+	case GPIO_ID_DDC_CLOCK:
-+		ddc->regs = &ddc_clk_regs[en];
-+		ddc->base.regs = &ddc_clk_regs[en].gpio;
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return;
-+	}
-+
-+	ddc->shifts = &ddc_shift;
-+	ddc->masks = &ddc_mask;
-+
-+}
-+
-+static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
-+{
-+	struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
-+
-+	hpd->regs = &hpd_regs[en];
-+	hpd->shifts = &hpd_shift;
-+	hpd->masks = &hpd_mask;
-+	hpd->base.regs = &hpd_regs[en].gpio;
-+}
-+
-+static const struct hw_factory_funcs funcs = {
-+	.create_ddc_data = dal_hw_ddc_create,
-+	.create_ddc_clock = dal_hw_ddc_create,
-+	.create_generic = NULL,
-+	.create_hpd = dal_hw_hpd_create,
-+	.create_sync = NULL,
-+	.create_gsl = NULL,
-+	.define_hpd_registers = define_hpd_registers,
-+	.define_ddc_registers = define_ddc_registers
-+};
-+
-+/*
-+ * dal_hw_factory_dce110_init
-+ *
-+ * @brief
-+ * Initialize HW factory function pointers and pin info
-+ *
-+ * @param
-+ * struct hw_factory *factory - [out] struct of function pointers
-+ */
-+void dal_hw_factory_dce110_init(struct hw_factory *factory)
-+{
-+	/*TODO check ASIC CAPs*/
-+	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
-+	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
-+	factory->number_of_pins[GPIO_ID_GENERIC] = 7;
-+	factory->number_of_pins[GPIO_ID_HPD] = 6;
-+	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
-+	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
-+	factory->number_of_pins[GPIO_ID_SYNC] = 2;
-+	factory->number_of_pins[GPIO_ID_GSL] = 4;
-+
-+	factory->funcs = &funcs;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.h.0130~	2017-12-14 06:39:58.429903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.h	2017-12-14 06:39:58.429903577 +0100
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_FACTORY_DCE110_H__
-+#define __DAL_HW_FACTORY_DCE110_H__
-+
-+/* Initialize HW factory function pointers and pin info */
-+void dal_hw_factory_dce110_init(struct hw_factory *factory);
-+
-+#endif /* __DAL_HW_FACTORY_DCE110_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c.0130~	2017-12-14 06:39:58.429903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c	2017-12-14 06:39:58.429903577 +0100
-@@ -0,0 +1,387 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "dm_services.h"
-+#include "include/gpio_types.h"
-+#include "../hw_translate.h"
-+
-+#include "hw_translate_dce110.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+static bool offset_to_id(
-+	uint32_t offset,
-+	uint32_t mask,
-+	enum gpio_id *id,
-+	uint32_t *en)
-+{
-+	switch (offset) {
-+	/* GENERIC */
-+	case mmDC_GPIO_GENERIC_A:
-+		*id = GPIO_ID_GENERIC;
-+		switch (mask) {
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
-+			*en = GPIO_GENERIC_A;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
-+			*en = GPIO_GENERIC_B;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
-+			*en = GPIO_GENERIC_C;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
-+			*en = GPIO_GENERIC_D;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
-+			*en = GPIO_GENERIC_E;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
-+			*en = GPIO_GENERIC_F;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
-+			*en = GPIO_GENERIC_G;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* HPD */
-+	case mmDC_GPIO_HPD_A:
-+		*id = GPIO_ID_HPD;
-+		switch (mask) {
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
-+			*en = GPIO_HPD_1;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
-+			*en = GPIO_HPD_2;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
-+			*en = GPIO_HPD_3;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
-+			*en = GPIO_HPD_4;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
-+			*en = GPIO_HPD_5;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
-+			*en = GPIO_HPD_6;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* SYNCA */
-+	case mmDC_GPIO_SYNCA_A:
-+		*id = GPIO_ID_SYNC;
-+		switch (mask) {
-+		case DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK:
-+			*en = GPIO_SYNC_HSYNC_A;
-+			return true;
-+		case DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK:
-+			*en = GPIO_SYNC_VSYNC_A;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* mmDC_GPIO_GENLK_MASK */
-+	case mmDC_GPIO_GENLK_A:
-+		*id = GPIO_ID_GSL;
-+		switch (mask) {
-+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
-+			*en = GPIO_GSL_GENLOCK_CLOCK;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
-+			*en = GPIO_GSL_GENLOCK_VSYNC;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
-+			*en = GPIO_GSL_SWAPLOCK_A;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
-+			*en = GPIO_GSL_SWAPLOCK_B;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* DDC */
-+	/* we don't care about the GPIO_ID for DDC
-+	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
-+	 * directly in the create method */
-+	case mmDC_GPIO_DDC1_A:
-+		*en = GPIO_DDC_LINE_DDC1;
-+		return true;
-+	case mmDC_GPIO_DDC2_A:
-+		*en = GPIO_DDC_LINE_DDC2;
-+		return true;
-+	case mmDC_GPIO_DDC3_A:
-+		*en = GPIO_DDC_LINE_DDC3;
-+		return true;
-+	case mmDC_GPIO_DDC4_A:
-+		*en = GPIO_DDC_LINE_DDC4;
-+		return true;
-+	case mmDC_GPIO_DDC5_A:
-+		*en = GPIO_DDC_LINE_DDC5;
-+		return true;
-+	case mmDC_GPIO_DDC6_A:
-+		*en = GPIO_DDC_LINE_DDC6;
-+		return true;
-+	case mmDC_GPIO_DDCVGA_A:
-+		*en = GPIO_DDC_LINE_DDC_VGA;
-+		return true;
-+	/* GPIO_I2CPAD */
-+	case mmDC_GPIO_I2CPAD_A:
-+		*en = GPIO_DDC_LINE_I2C_PAD;
-+		return true;
-+	/* Not implemented */
-+	case mmDC_GPIO_PWRSEQ_A:
-+	case mmDC_GPIO_PAD_STRENGTH_1:
-+	case mmDC_GPIO_PAD_STRENGTH_2:
-+	case mmDC_GPIO_DEBUG:
-+		return false;
-+	/* UNEXPECTED */
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+}
-+
-+static bool id_to_offset(
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct gpio_pin_info *info)
-+{
-+	bool result = true;
-+
-+	switch (id) {
-+	case GPIO_ID_DDC_DATA:
-+		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
-+		switch (en) {
-+		case GPIO_DDC_LINE_DDC1:
-+			info->offset = mmDC_GPIO_DDC1_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC2:
-+			info->offset = mmDC_GPIO_DDC2_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC3:
-+			info->offset = mmDC_GPIO_DDC3_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC4:
-+			info->offset = mmDC_GPIO_DDC4_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC5:
-+			info->offset = mmDC_GPIO_DDC5_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC6:
-+			info->offset = mmDC_GPIO_DDC6_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			info->offset = mmDC_GPIO_DDCVGA_A;
-+		break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			info->offset = mmDC_GPIO_I2CPAD_A;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_DDC_CLOCK:
-+		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
-+		switch (en) {
-+		case GPIO_DDC_LINE_DDC1:
-+			info->offset = mmDC_GPIO_DDC1_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC2:
-+			info->offset = mmDC_GPIO_DDC2_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC3:
-+			info->offset = mmDC_GPIO_DDC3_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC4:
-+			info->offset = mmDC_GPIO_DDC4_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC5:
-+			info->offset = mmDC_GPIO_DDC5_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC6:
-+			info->offset = mmDC_GPIO_DDC6_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			info->offset = mmDC_GPIO_DDCVGA_A;
-+		break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			info->offset = mmDC_GPIO_I2CPAD_A;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_GENERIC:
-+		info->offset = mmDC_GPIO_GENERIC_A;
-+		switch (en) {
-+		case GPIO_GENERIC_A:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
-+		break;
-+		case GPIO_GENERIC_B:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
-+		break;
-+		case GPIO_GENERIC_C:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
-+		break;
-+		case GPIO_GENERIC_D:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
-+		break;
-+		case GPIO_GENERIC_E:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
-+		break;
-+		case GPIO_GENERIC_F:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
-+		break;
-+		case GPIO_GENERIC_G:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_HPD:
-+		info->offset = mmDC_GPIO_HPD_A;
-+		switch (en) {
-+		case GPIO_HPD_1:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
-+		break;
-+		case GPIO_HPD_2:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
-+		break;
-+		case GPIO_HPD_3:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
-+		break;
-+		case GPIO_HPD_4:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
-+		break;
-+		case GPIO_HPD_5:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
-+		break;
-+		case GPIO_HPD_6:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_SYNC:
-+		switch (en) {
-+		case GPIO_SYNC_HSYNC_A:
-+			info->offset = mmDC_GPIO_SYNCA_A;
-+			info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;
-+		break;
-+		case GPIO_SYNC_VSYNC_A:
-+			info->offset = mmDC_GPIO_SYNCA_A;
-+			info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;
-+		break;
-+		case GPIO_SYNC_HSYNC_B:
-+		case GPIO_SYNC_VSYNC_B:
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_GSL:
-+		switch (en) {
-+		case GPIO_GSL_GENLOCK_CLOCK:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;
-+		break;
-+		case GPIO_GSL_GENLOCK_VSYNC:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask =
-+				DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK;
-+		break;
-+		case GPIO_GSL_SWAPLOCK_A:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;
-+		break;
-+		case GPIO_GSL_SWAPLOCK_B:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_VIP_PAD:
-+	default:
-+		ASSERT_CRITICAL(false);
-+		result = false;
-+	}
-+
-+	if (result) {
-+		info->offset_y = info->offset + 2;
-+		info->offset_en = info->offset + 1;
-+		info->offset_mask = info->offset - 1;
-+
-+		info->mask_y = info->mask;
-+		info->mask_en = info->mask;
-+		info->mask_mask = info->mask;
-+	}
-+
-+	return result;
-+}
-+
-+/* function table */
-+static const struct hw_translate_funcs funcs = {
-+	.offset_to_id = offset_to_id,
-+	.id_to_offset = id_to_offset,
-+};
-+
-+/*
-+ * dal_hw_translate_dce110_init
-+ *
-+ * @brief
-+ * Initialize Hw translate function pointers.
-+ *
-+ * @param
-+ * struct hw_translate *tr - [out] struct of function pointers
-+ *
-+ */
-+void dal_hw_translate_dce110_init(struct hw_translate *tr)
-+{
-+	tr->funcs = &funcs;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.h.0130~	2017-12-14 06:39:58.429903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.h	2017-12-14 06:39:58.429903577 +0100
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_TRANSLATE_DCE110_H__
-+#define __DAL_HW_TRANSLATE_DCE110_H__
-+
-+struct hw_translate;
-+
-+/* Initialize Hw translate function pointers */
-+void dal_hw_translate_dce110_init(struct hw_translate *tr);
-+
-+#endif /* __DAL_HW_TRANSLATE_DCE110_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c.0130~	2017-12-14 06:39:58.429903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c	2017-12-14 06:39:58.429903577 +0100
-@@ -0,0 +1,197 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "include/gpio_types.h"
-+#include "../hw_factory.h"
-+
-+
-+#include "../hw_gpio.h"
-+#include "../hw_ddc.h"
-+#include "../hw_hpd.h"
-+
-+#include "hw_factory_dce120.h"
-+
-+#include "vega10/DC/dce_12_0_offset.h"
-+#include "vega10/DC/dce_12_0_sh_mask.h"
-+#include "vega10/soc15ip.h"
-+
-+#define block HPD
-+#define reg_num 0
-+
-+/* set field name */
-+#define SF_HPD(reg_name, field_name, post_fix)\
-+	.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
-+
-+/* set field name */
-+#define SF_HPD(reg_name, field_name, post_fix)\
-+	.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
-+
-+#define BASE_INNER(seg) \
-+	DCE_BASE__INST0_SEG ## seg
-+
-+/* compile time expand base address. */
-+#define BASE(seg) \
-+	BASE_INNER(seg)
-+
-+#define REG(reg_name)\
-+		BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
-+
-+#define REGI(reg_name, block, id)\
-+	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-+				mm ## block ## id ## _ ## reg_name
-+
-+
-+#include "reg_helper.h"
-+#include "../hpd_regs.h"
-+
-+#define hpd_regs(id) \
-+{\
-+	HPD_REG_LIST(id)\
-+}
-+
-+static const struct hpd_registers hpd_regs[] = {
-+	hpd_regs(0),
-+	hpd_regs(1),
-+	hpd_regs(2),
-+	hpd_regs(3),
-+	hpd_regs(4),
-+	hpd_regs(5)
-+};
-+
-+static const struct hpd_sh_mask hpd_shift = {
-+		HPD_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct hpd_sh_mask hpd_mask = {
-+		HPD_MASK_SH_LIST(_MASK)
-+};
-+
-+#include "../ddc_regs.h"
-+
-+ /* set field name */
-+#define SF_DDC(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+static const struct ddc_registers ddc_data_regs[] = {
-+	ddc_data_regs(1),
-+	ddc_data_regs(2),
-+	ddc_data_regs(3),
-+	ddc_data_regs(4),
-+	ddc_data_regs(5),
-+	ddc_data_regs(6),
-+	ddc_vga_data_regs,
-+	ddc_i2c_data_regs
-+};
-+
-+static const struct ddc_registers ddc_clk_regs[] = {
-+	ddc_clk_regs(1),
-+	ddc_clk_regs(2),
-+	ddc_clk_regs(3),
-+	ddc_clk_regs(4),
-+	ddc_clk_regs(5),
-+	ddc_clk_regs(6),
-+	ddc_vga_clk_regs,
-+	ddc_i2c_clk_regs
-+};
-+
-+static const struct ddc_sh_mask ddc_shift = {
-+		DDC_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct ddc_sh_mask ddc_mask = {
-+		DDC_MASK_SH_LIST(_MASK)
-+};
-+
-+static void define_ddc_registers(
-+		struct hw_gpio_pin *pin,
-+		uint32_t en)
-+{
-+	struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
-+
-+	switch (pin->id) {
-+	case GPIO_ID_DDC_DATA:
-+		ddc->regs = &ddc_data_regs[en];
-+		ddc->base.regs = &ddc_data_regs[en].gpio;
-+		break;
-+	case GPIO_ID_DDC_CLOCK:
-+		ddc->regs = &ddc_clk_regs[en];
-+		ddc->base.regs = &ddc_clk_regs[en].gpio;
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return;
-+	}
-+
-+	ddc->shifts = &ddc_shift;
-+	ddc->masks = &ddc_mask;
-+
-+}
-+
-+static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
-+{
-+	struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
-+
-+	hpd->regs = &hpd_regs[en];
-+	hpd->shifts = &hpd_shift;
-+	hpd->masks = &hpd_mask;
-+	hpd->base.regs = &hpd_regs[en].gpio;
-+}
-+
-+
-+/* fucntion table */
-+static const struct hw_factory_funcs funcs = {
-+	.create_ddc_data = dal_hw_ddc_create,
-+	.create_ddc_clock = dal_hw_ddc_create,
-+	.create_generic = NULL,
-+	.create_hpd = dal_hw_hpd_create,
-+	.create_sync = NULL,
-+	.create_gsl = NULL,
-+	.define_hpd_registers = define_hpd_registers,
-+	.define_ddc_registers = define_ddc_registers
-+};
-+/*
-+ * dal_hw_factory_dce120_init
-+ *
-+ * @brief
-+ * Initialize HW factory function pointers and pin info
-+ *
-+ * @param
-+ * struct hw_factory *factory - [out] struct of function pointers
-+ */
-+void dal_hw_factory_dce120_init(struct hw_factory *factory)
-+{
-+	/*TODO check ASIC CAPs*/
-+	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
-+	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
-+	factory->number_of_pins[GPIO_ID_GENERIC] = 7;
-+	factory->number_of_pins[GPIO_ID_HPD] = 6;
-+	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
-+	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
-+	factory->number_of_pins[GPIO_ID_SYNC] = 2;
-+	factory->number_of_pins[GPIO_ID_GSL] = 4;
-+
-+	factory->funcs = &funcs;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.h.0130~	2017-12-14 06:39:58.429903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.h	2017-12-14 06:39:58.429903577 +0100
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_FACTORY_DCE120_H__
-+#define __DAL_HW_FACTORY_DCE120_H__
-+
-+/* Initialize HW factory function pointers and pin info */
-+void dal_hw_factory_dce120_init(struct hw_factory *factory);
-+
-+#endif /* __DAL_HW_FACTORY_DCE120_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c.0130~	2017-12-14 06:39:58.429903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c	2017-12-14 06:39:58.429903577 +0100
-@@ -0,0 +1,408 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "hw_translate_dce120.h"
-+
-+#include "dm_services.h"
-+#include "include/gpio_types.h"
-+#include "../hw_translate.h"
-+
-+#include "vega10/DC/dce_12_0_offset.h"
-+#include "vega10/DC/dce_12_0_sh_mask.h"
-+#include "vega10/soc15ip.h"
-+
-+/* begin *********************
-+ * macros to expend register list macro defined in HW object header file */
-+
-+#define BASE_INNER(seg) \
-+	DCE_BASE__INST0_SEG ## seg
-+
-+/* compile time expand base address. */
-+#define BASE(seg) \
-+	BASE_INNER(seg)
-+
-+#define REG(reg_name)\
-+		BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
-+
-+#define REGI(reg_name, block, id)\
-+	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-+				mm ## block ## id ## _ ## reg_name
-+
-+/* macros to expend register list macro defined in HW object header file
-+ * end *********************/
-+
-+static bool offset_to_id(
-+	uint32_t offset,
-+	uint32_t mask,
-+	enum gpio_id *id,
-+	uint32_t *en)
-+{
-+	switch (offset) {
-+	/* GENERIC */
-+	case REG(DC_GPIO_GENERIC_A):
-+		*id = GPIO_ID_GENERIC;
-+		switch (mask) {
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
-+			*en = GPIO_GENERIC_A;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
-+			*en = GPIO_GENERIC_B;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
-+			*en = GPIO_GENERIC_C;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
-+			*en = GPIO_GENERIC_D;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
-+			*en = GPIO_GENERIC_E;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
-+			*en = GPIO_GENERIC_F;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
-+			*en = GPIO_GENERIC_G;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* HPD */
-+	case REG(DC_GPIO_HPD_A):
-+		*id = GPIO_ID_HPD;
-+		switch (mask) {
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
-+			*en = GPIO_HPD_1;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
-+			*en = GPIO_HPD_2;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
-+			*en = GPIO_HPD_3;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
-+			*en = GPIO_HPD_4;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
-+			*en = GPIO_HPD_5;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
-+			*en = GPIO_HPD_6;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* SYNCA */
-+	case REG(DC_GPIO_SYNCA_A):
-+		*id = GPIO_ID_SYNC;
-+		switch (mask) {
-+		case DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK:
-+			*en = GPIO_SYNC_HSYNC_A;
-+			return true;
-+		case DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK:
-+			*en = GPIO_SYNC_VSYNC_A;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* REG(DC_GPIO_GENLK_MASK */
-+	case REG(DC_GPIO_GENLK_A):
-+		*id = GPIO_ID_GSL;
-+		switch (mask) {
-+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
-+			*en = GPIO_GSL_GENLOCK_CLOCK;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
-+			*en = GPIO_GSL_GENLOCK_VSYNC;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
-+			*en = GPIO_GSL_SWAPLOCK_A;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
-+			*en = GPIO_GSL_SWAPLOCK_B;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* DDC */
-+	/* we don't care about the GPIO_ID for DDC
-+	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
-+	 * directly in the create method */
-+	case REG(DC_GPIO_DDC1_A):
-+		*en = GPIO_DDC_LINE_DDC1;
-+		return true;
-+	case REG(DC_GPIO_DDC2_A):
-+		*en = GPIO_DDC_LINE_DDC2;
-+		return true;
-+	case REG(DC_GPIO_DDC3_A):
-+		*en = GPIO_DDC_LINE_DDC3;
-+		return true;
-+	case REG(DC_GPIO_DDC4_A):
-+		*en = GPIO_DDC_LINE_DDC4;
-+		return true;
-+	case REG(DC_GPIO_DDC5_A):
-+		*en = GPIO_DDC_LINE_DDC5;
-+		return true;
-+	case REG(DC_GPIO_DDC6_A):
-+		*en = GPIO_DDC_LINE_DDC6;
-+		return true;
-+	case REG(DC_GPIO_DDCVGA_A):
-+		*en = GPIO_DDC_LINE_DDC_VGA;
-+		return true;
-+	/* GPIO_I2CPAD */
-+	case REG(DC_GPIO_I2CPAD_A):
-+		*en = GPIO_DDC_LINE_I2C_PAD;
-+		return true;
-+	/* Not implemented */
-+	case REG(DC_GPIO_PWRSEQ_A):
-+	case REG(DC_GPIO_PAD_STRENGTH_1):
-+	case REG(DC_GPIO_PAD_STRENGTH_2):
-+	case REG(DC_GPIO_DEBUG):
-+		return false;
-+	/* UNEXPECTED */
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+}
-+
-+static bool id_to_offset(
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct gpio_pin_info *info)
-+{
-+	bool result = true;
-+
-+	switch (id) {
-+	case GPIO_ID_DDC_DATA:
-+		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
-+		switch (en) {
-+		case GPIO_DDC_LINE_DDC1:
-+			info->offset = REG(DC_GPIO_DDC1_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC2:
-+			info->offset = REG(DC_GPIO_DDC2_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC3:
-+			info->offset = REG(DC_GPIO_DDC3_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC4:
-+			info->offset = REG(DC_GPIO_DDC4_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC5:
-+			info->offset = REG(DC_GPIO_DDC5_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC6:
-+			info->offset = REG(DC_GPIO_DDC6_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			info->offset = REG(DC_GPIO_DDCVGA_A);
-+		break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			info->offset = REG(DC_GPIO_I2CPAD_A);
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_DDC_CLOCK:
-+		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
-+		switch (en) {
-+		case GPIO_DDC_LINE_DDC1:
-+			info->offset = REG(DC_GPIO_DDC1_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC2:
-+			info->offset = REG(DC_GPIO_DDC2_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC3:
-+			info->offset = REG(DC_GPIO_DDC3_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC4:
-+			info->offset = REG(DC_GPIO_DDC4_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC5:
-+			info->offset = REG(DC_GPIO_DDC5_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC6:
-+			info->offset = REG(DC_GPIO_DDC6_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			info->offset = REG(DC_GPIO_DDCVGA_A);
-+		break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			info->offset = REG(DC_GPIO_I2CPAD_A);
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_GENERIC:
-+		info->offset = REG(DC_GPIO_GENERIC_A);
-+		switch (en) {
-+		case GPIO_GENERIC_A:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
-+		break;
-+		case GPIO_GENERIC_B:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
-+		break;
-+		case GPIO_GENERIC_C:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
-+		break;
-+		case GPIO_GENERIC_D:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
-+		break;
-+		case GPIO_GENERIC_E:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
-+		break;
-+		case GPIO_GENERIC_F:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
-+		break;
-+		case GPIO_GENERIC_G:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_HPD:
-+		info->offset = REG(DC_GPIO_HPD_A);
-+		switch (en) {
-+		case GPIO_HPD_1:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
-+		break;
-+		case GPIO_HPD_2:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
-+		break;
-+		case GPIO_HPD_3:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
-+		break;
-+		case GPIO_HPD_4:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
-+		break;
-+		case GPIO_HPD_5:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
-+		break;
-+		case GPIO_HPD_6:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_SYNC:
-+		switch (en) {
-+		case GPIO_SYNC_HSYNC_A:
-+			info->offset = REG(DC_GPIO_SYNCA_A);
-+			info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;
-+		break;
-+		case GPIO_SYNC_VSYNC_A:
-+			info->offset = REG(DC_GPIO_SYNCA_A);
-+			info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;
-+		break;
-+		case GPIO_SYNC_HSYNC_B:
-+		case GPIO_SYNC_VSYNC_B:
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_GSL:
-+		switch (en) {
-+		case GPIO_GSL_GENLOCK_CLOCK:
-+			info->offset = REG(DC_GPIO_GENLK_A);
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;
-+		break;
-+		case GPIO_GSL_GENLOCK_VSYNC:
-+			info->offset = REG(DC_GPIO_GENLK_A);
-+			info->mask =
-+				DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK;
-+		break;
-+		case GPIO_GSL_SWAPLOCK_A:
-+			info->offset = REG(DC_GPIO_GENLK_A);
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;
-+		break;
-+		case GPIO_GSL_SWAPLOCK_B:
-+			info->offset = REG(DC_GPIO_GENLK_A);
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_VIP_PAD:
-+	default:
-+		ASSERT_CRITICAL(false);
-+		result = false;
-+	}
-+
-+	if (result) {
-+		info->offset_y = info->offset + 2;
-+		info->offset_en = info->offset + 1;
-+		info->offset_mask = info->offset - 1;
-+
-+		info->mask_y = info->mask;
-+		info->mask_en = info->mask;
-+		info->mask_mask = info->mask;
-+	}
-+
-+	return result;
-+}
-+
-+/* function table */
-+static const struct hw_translate_funcs funcs = {
-+	.offset_to_id = offset_to_id,
-+	.id_to_offset = id_to_offset,
-+};
-+
-+/*
-+ * dal_hw_translate_dce120_init
-+ *
-+ * @brief
-+ * Initialize Hw translate function pointers.
-+ *
-+ * @param
-+ * struct hw_translate *tr - [out] struct of function pointers
-+ *
-+ */
-+void dal_hw_translate_dce120_init(struct hw_translate *tr)
-+{
-+	tr->funcs = &funcs;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.h.0130~	2017-12-14 06:39:58.429903577 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.h	2017-12-14 06:39:58.429903577 +0100
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_TRANSLATE_DCE120_H__
-+#define __DAL_HW_TRANSLATE_DCE120_H__
-+
-+struct hw_translate;
-+
-+/* Initialize Hw translate function pointers */
-+void dal_hw_translate_dce120_init(struct hw_translate *tr);
-+
-+#endif /* __DAL_HW_TRANSLATE_DCE120_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c.0130~	2017-12-14 06:39:58.430903578 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c	2017-12-14 06:39:58.430903578 +0100
-@@ -0,0 +1,173 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "include/gpio_types.h"
-+#include "../hw_factory.h"
-+
-+#include "hw_factory_dce80.h"
-+
-+#include "../hw_gpio.h"
-+#include "../hw_ddc.h"
-+#include "../hw_hpd.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#define REG(reg_name)\
-+		mm ## reg_name
-+
-+#include "reg_helper.h"
-+#include "../hpd_regs.h"
-+
-+#define HPD_REG_LIST_DCE8(id) \
-+	HPD_GPIO_REG_LIST(id), \
-+	.int_status = mmDC_HPD ## id ## _INT_STATUS,\
-+	.toggle_filt_cntl = mmDC_HPD ## id ## _TOGGLE_FILT_CNTL
-+
-+#define HPD_MASK_SH_LIST_DCE8(mask_sh) \
-+		.DC_HPD_SENSE_DELAYED = DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED ## mask_sh,\
-+		.DC_HPD_SENSE = DC_HPD1_INT_STATUS__DC_HPD1_SENSE ## mask_sh,\
-+		.DC_HPD_CONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY ## mask_sh,\
-+		.DC_HPD_DISCONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY ## mask_sh
-+
-+#define hpd_regs(id) \
-+{\
-+	HPD_REG_LIST_DCE8(id)\
-+}
-+
-+static const struct hpd_registers hpd_regs[] = {
-+	hpd_regs(1),
-+	hpd_regs(2),
-+	hpd_regs(3),
-+	hpd_regs(4),
-+	hpd_regs(5),
-+	hpd_regs(6)
-+};
-+
-+static const struct hpd_sh_mask hpd_shift = {
-+		HPD_MASK_SH_LIST_DCE8(__SHIFT)
-+};
-+
-+static const struct hpd_sh_mask hpd_mask = {
-+		HPD_MASK_SH_LIST_DCE8(_MASK)
-+};
-+
-+#include "../ddc_regs.h"
-+
-+ /* set field name */
-+#define SF_DDC(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+static const struct ddc_registers ddc_data_regs[] = {
-+	ddc_data_regs(1),
-+	ddc_data_regs(2),
-+	ddc_data_regs(3),
-+	ddc_data_regs(4),
-+	ddc_data_regs(5),
-+	ddc_data_regs(6),
-+	ddc_vga_data_regs,
-+	ddc_i2c_data_regs
-+};
-+
-+static const struct ddc_registers ddc_clk_regs[] = {
-+	ddc_clk_regs(1),
-+	ddc_clk_regs(2),
-+	ddc_clk_regs(3),
-+	ddc_clk_regs(4),
-+	ddc_clk_regs(5),
-+	ddc_clk_regs(6),
-+	ddc_vga_clk_regs,
-+	ddc_i2c_clk_regs
-+};
-+
-+static const struct ddc_sh_mask ddc_shift = {
-+		DDC_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct ddc_sh_mask ddc_mask = {
-+		DDC_MASK_SH_LIST(_MASK)
-+};
-+
-+static void define_ddc_registers(
-+		struct hw_gpio_pin *pin,
-+		uint32_t en)
-+{
-+	struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
-+
-+	switch (pin->id) {
-+	case GPIO_ID_DDC_DATA:
-+		ddc->regs = &ddc_data_regs[en];
-+		ddc->base.regs = &ddc_data_regs[en].gpio;
-+		break;
-+	case GPIO_ID_DDC_CLOCK:
-+		ddc->regs = &ddc_clk_regs[en];
-+		ddc->base.regs = &ddc_clk_regs[en].gpio;
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return;
-+	}
-+
-+	ddc->shifts = &ddc_shift;
-+	ddc->masks = &ddc_mask;
-+
-+}
-+
-+static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
-+{
-+	struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
-+
-+	hpd->regs = &hpd_regs[en];
-+	hpd->shifts = &hpd_shift;
-+	hpd->masks = &hpd_mask;
-+	hpd->base.regs = &hpd_regs[en].gpio;
-+}
-+
-+static const struct hw_factory_funcs funcs = {
-+	.create_ddc_data = dal_hw_ddc_create,
-+	.create_ddc_clock = dal_hw_ddc_create,
-+	.create_generic = NULL,
-+	.create_hpd = dal_hw_hpd_create,
-+	.create_sync = NULL,
-+	.create_gsl = NULL,
-+	.define_hpd_registers = define_hpd_registers,
-+	.define_ddc_registers = define_ddc_registers
-+};
-+
-+void dal_hw_factory_dce80_init(
-+	struct hw_factory *factory)
-+{
-+	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
-+	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
-+	factory->number_of_pins[GPIO_ID_GENERIC] = 7;
-+	factory->number_of_pins[GPIO_ID_HPD] = 6;
-+	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
-+	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
-+	factory->number_of_pins[GPIO_ID_SYNC] = 2;
-+	factory->number_of_pins[GPIO_ID_GSL] = 4;
-+
-+	factory->funcs = &funcs;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.h.0130~	2017-12-14 06:39:58.430903578 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.h	2017-12-14 06:39:58.430903578 +0100
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_FACTORY_DCE80_H__
-+#define __DAL_HW_FACTORY_DCE80_H__
-+
-+void dal_hw_factory_dce80_init(
-+	struct hw_factory *factory);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c.0130~	2017-12-14 06:39:58.430903578 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c	2017-12-14 06:39:58.430903578 +0100
-@@ -0,0 +1,411 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/gpio_types.h"
-+#include "../hw_translate.h"
-+
-+#include "hw_translate_dce80.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+#include "smu/smu_7_0_1_d.h"
-+
-+/*
-+ * @brief
-+ * Returns index of first bit (starting with LSB) which is set
-+ */
-+static uint32_t index_from_vector(
-+	uint32_t vector)
-+{
-+	uint32_t result = 0;
-+	uint32_t mask = 1;
-+
-+	do {
-+		if (vector == mask)
-+			return result;
-+
-+		++result;
-+		mask <<= 1;
-+	} while (mask);
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	return GPIO_ENUM_UNKNOWN;
-+}
-+
-+static bool offset_to_id(
-+	uint32_t offset,
-+	uint32_t mask,
-+	enum gpio_id *id,
-+	uint32_t *en)
-+{
-+	switch (offset) {
-+	/* GENERIC */
-+	case mmDC_GPIO_GENERIC_A:
-+		*id = GPIO_ID_GENERIC;
-+		switch (mask) {
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
-+			*en = GPIO_GENERIC_A;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
-+			*en = GPIO_GENERIC_B;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
-+			*en = GPIO_GENERIC_C;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
-+			*en = GPIO_GENERIC_D;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
-+			*en = GPIO_GENERIC_E;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
-+			*en = GPIO_GENERIC_F;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
-+			*en = GPIO_GENERIC_G;
-+			return true;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+	break;
-+	/* HPD */
-+	case mmDC_GPIO_HPD_A:
-+		*id = GPIO_ID_HPD;
-+		switch (mask) {
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
-+			*en = GPIO_HPD_1;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
-+			*en = GPIO_HPD_2;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
-+			*en = GPIO_HPD_3;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
-+			*en = GPIO_HPD_4;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
-+			*en = GPIO_HPD_5;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
-+			*en = GPIO_HPD_6;
-+			return true;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+	break;
-+	/* SYNCA */
-+	case mmDC_GPIO_SYNCA_A:
-+		*id = GPIO_ID_SYNC;
-+		switch (mask) {
-+		case DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK:
-+			*en = GPIO_SYNC_HSYNC_A;
-+			return true;
-+		case DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK:
-+			*en = GPIO_SYNC_VSYNC_A;
-+			return true;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+	break;
-+	/* mmDC_GPIO_GENLK_MASK */
-+	case mmDC_GPIO_GENLK_A:
-+		*id = GPIO_ID_GSL;
-+		switch (mask) {
-+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
-+			*en = GPIO_GSL_GENLOCK_CLOCK;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
-+			*en = GPIO_GSL_GENLOCK_VSYNC;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
-+			*en = GPIO_GSL_SWAPLOCK_A;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
-+			*en = GPIO_GSL_SWAPLOCK_B;
-+			return true;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			return false;
-+		}
-+	break;
-+	/* GPIOPAD */
-+	case mmGPIOPAD_A:
-+		*id = GPIO_ID_GPIO_PAD;
-+		*en = index_from_vector(mask);
-+		return (*en <= GPIO_GPIO_PAD_MAX);
-+	/* DDC */
-+	/* we don't care about the GPIO_ID for DDC
-+	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
-+	 * directly in the create method */
-+	case mmDC_GPIO_DDC1_A:
-+		*en = GPIO_DDC_LINE_DDC1;
-+		return true;
-+	case mmDC_GPIO_DDC2_A:
-+		*en = GPIO_DDC_LINE_DDC2;
-+		return true;
-+	case mmDC_GPIO_DDC3_A:
-+		*en = GPIO_DDC_LINE_DDC3;
-+		return true;
-+	case mmDC_GPIO_DDC4_A:
-+		*en = GPIO_DDC_LINE_DDC4;
-+		return true;
-+	case mmDC_GPIO_DDC5_A:
-+		*en = GPIO_DDC_LINE_DDC5;
-+		return true;
-+	case mmDC_GPIO_DDC6_A:
-+		*en = GPIO_DDC_LINE_DDC6;
-+		return true;
-+	case mmDC_GPIO_DDCVGA_A:
-+		*en = GPIO_DDC_LINE_DDC_VGA;
-+		return true;
-+	/* GPIO_I2CPAD */
-+	case mmDC_GPIO_I2CPAD_A:
-+		*en = GPIO_DDC_LINE_I2C_PAD;
-+		return true;
-+	/* Not implemented */
-+	case mmDC_GPIO_PWRSEQ_A:
-+	case mmDC_GPIO_PAD_STRENGTH_1:
-+	case mmDC_GPIO_PAD_STRENGTH_2:
-+	case mmDC_GPIO_DEBUG:
-+		return false;
-+	/* UNEXPECTED */
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
-+
-+static bool id_to_offset(
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct gpio_pin_info *info)
-+{
-+	bool result = true;
-+
-+	switch (id) {
-+	case GPIO_ID_DDC_DATA:
-+		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
-+		switch (en) {
-+		case GPIO_DDC_LINE_DDC1:
-+			info->offset = mmDC_GPIO_DDC1_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC2:
-+			info->offset = mmDC_GPIO_DDC2_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC3:
-+			info->offset = mmDC_GPIO_DDC3_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC4:
-+			info->offset = mmDC_GPIO_DDC4_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC5:
-+			info->offset = mmDC_GPIO_DDC5_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC6:
-+			info->offset = mmDC_GPIO_DDC6_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			info->offset = mmDC_GPIO_DDCVGA_A;
-+		break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			info->offset = mmDC_GPIO_I2CPAD_A;
-+		break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_DDC_CLOCK:
-+		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
-+		switch (en) {
-+		case GPIO_DDC_LINE_DDC1:
-+			info->offset = mmDC_GPIO_DDC1_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC2:
-+			info->offset = mmDC_GPIO_DDC2_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC3:
-+			info->offset = mmDC_GPIO_DDC3_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC4:
-+			info->offset = mmDC_GPIO_DDC4_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC5:
-+			info->offset = mmDC_GPIO_DDC5_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC6:
-+			info->offset = mmDC_GPIO_DDC6_A;
-+		break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			info->offset = mmDC_GPIO_DDCVGA_A;
-+		break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			info->offset = mmDC_GPIO_I2CPAD_A;
-+		break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_GENERIC:
-+		info->offset = mmDC_GPIO_GENERIC_A;
-+		switch (en) {
-+		case GPIO_GENERIC_A:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
-+		break;
-+		case GPIO_GENERIC_B:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
-+		break;
-+		case GPIO_GENERIC_C:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
-+		break;
-+		case GPIO_GENERIC_D:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
-+		break;
-+		case GPIO_GENERIC_E:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
-+		break;
-+		case GPIO_GENERIC_F:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
-+		break;
-+		case GPIO_GENERIC_G:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
-+		break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_HPD:
-+		info->offset = mmDC_GPIO_HPD_A;
-+		switch (en) {
-+		case GPIO_HPD_1:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
-+		break;
-+		case GPIO_HPD_2:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
-+		break;
-+		case GPIO_HPD_3:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
-+		break;
-+		case GPIO_HPD_4:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
-+		break;
-+		case GPIO_HPD_5:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
-+		break;
-+		case GPIO_HPD_6:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
-+		break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_SYNC:
-+		switch (en) {
-+		case GPIO_SYNC_HSYNC_A:
-+			info->offset = mmDC_GPIO_SYNCA_A;
-+			info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;
-+		break;
-+		case GPIO_SYNC_VSYNC_A:
-+			info->offset = mmDC_GPIO_SYNCA_A;
-+			info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;
-+		break;
-+		case GPIO_SYNC_HSYNC_B:
-+		case GPIO_SYNC_VSYNC_B:
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_GSL:
-+		switch (en) {
-+		case GPIO_GSL_GENLOCK_CLOCK:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;
-+		break;
-+		case GPIO_GSL_GENLOCK_VSYNC:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask =
-+				DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK;
-+		break;
-+		case GPIO_GSL_SWAPLOCK_A:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;
-+		break;
-+		case GPIO_GSL_SWAPLOCK_B:
-+			info->offset = mmDC_GPIO_GENLK_A;
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;
-+		break;
-+		default:
-+			BREAK_TO_DEBUGGER();
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_GPIO_PAD:
-+		info->offset = mmGPIOPAD_A;
-+		info->mask = (1 << en);
-+		result = (info->mask <= GPIO_GPIO_PAD_MAX);
-+	break;
-+	case GPIO_ID_VIP_PAD:
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		result = false;
-+	}
-+
-+	if (result) {
-+		info->offset_y = info->offset + 2;
-+		info->offset_en = info->offset + 1;
-+		info->offset_mask = info->offset - 1;
-+
-+		info->mask_y = info->mask;
-+		info->mask_en = info->mask;
-+		info->mask_mask = info->mask;
-+	}
-+
-+	return result;
-+}
-+
-+static const struct hw_translate_funcs funcs = {
-+		.offset_to_id = offset_to_id,
-+		.id_to_offset = id_to_offset,
-+};
-+
-+void dal_hw_translate_dce80_init(
-+	struct hw_translate *translate)
-+{
-+	translate->funcs = &funcs;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.h.0130~	2017-12-14 06:39:58.430903578 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.h	2017-12-14 06:39:58.430903578 +0100
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_TRANSLATE_DCE80_H__
-+#define __DAL_HW_TRANSLATE_DCE80_H__
-+
-+void dal_hw_translate_dce80_init(
-+	struct hw_translate *tr);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c.0130~	2017-12-14 06:39:58.430903578 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c	2017-12-14 06:39:58.430903578 +0100
-@@ -0,0 +1,192 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "include/gpio_types.h"
-+#include "../hw_factory.h"
-+
-+
-+#include "../hw_gpio.h"
-+#include "../hw_ddc.h"
-+#include "../hw_hpd.h"
-+
-+#include "hw_factory_dcn10.h"
-+
-+#include "raven1/DCN/dcn_1_0_offset.h"
-+#include "raven1/DCN/dcn_1_0_sh_mask.h"
-+#include "vega10/soc15ip.h"
-+
-+#define block HPD
-+#define reg_num 0
-+
-+/* set field name */
-+#define SF_HPD(reg_name, field_name, post_fix)\
-+	.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
-+
-+#define BASE_INNER(seg) \
-+	DCE_BASE__INST0_SEG ## seg
-+
-+/* compile time expand base address. */
-+#define BASE(seg) \
-+	BASE_INNER(seg)
-+
-+#define REG(reg_name)\
-+		BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
-+
-+#define REGI(reg_name, block, id)\
-+	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-+				mm ## block ## id ## _ ## reg_name
-+
-+#include "reg_helper.h"
-+#include "../hpd_regs.h"
-+
-+#define hpd_regs(id) \
-+{\
-+	HPD_REG_LIST(id)\
-+}
-+
-+static const struct hpd_registers hpd_regs[] = {
-+	hpd_regs(0),
-+	hpd_regs(1),
-+	hpd_regs(2),
-+	hpd_regs(3),
-+	hpd_regs(4),
-+	hpd_regs(5)
-+};
-+
-+static const struct hpd_sh_mask hpd_shift = {
-+		HPD_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct hpd_sh_mask hpd_mask = {
-+		HPD_MASK_SH_LIST(_MASK)
-+};
-+
-+#include "../ddc_regs.h"
-+
-+ /* set field name */
-+#define SF_DDC(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+static const struct ddc_registers ddc_data_regs[] = {
-+	ddc_data_regs(1),
-+	ddc_data_regs(2),
-+	ddc_data_regs(3),
-+	ddc_data_regs(4),
-+	ddc_data_regs(5),
-+	ddc_data_regs(6),
-+	ddc_vga_data_regs,
-+	ddc_i2c_data_regs
-+};
-+
-+static const struct ddc_registers ddc_clk_regs[] = {
-+	ddc_clk_regs(1),
-+	ddc_clk_regs(2),
-+	ddc_clk_regs(3),
-+	ddc_clk_regs(4),
-+	ddc_clk_regs(5),
-+	ddc_clk_regs(6),
-+	ddc_vga_clk_regs,
-+	ddc_i2c_clk_regs
-+};
-+
-+static const struct ddc_sh_mask ddc_shift = {
-+		DDC_MASK_SH_LIST(__SHIFT)
-+};
-+
-+static const struct ddc_sh_mask ddc_mask = {
-+		DDC_MASK_SH_LIST(_MASK)
-+};
-+
-+static void define_ddc_registers(
-+		struct hw_gpio_pin *pin,
-+		uint32_t en)
-+{
-+	struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
-+
-+	switch (pin->id) {
-+	case GPIO_ID_DDC_DATA:
-+		ddc->regs = &ddc_data_regs[en];
-+		ddc->base.regs = &ddc_data_regs[en].gpio;
-+		break;
-+	case GPIO_ID_DDC_CLOCK:
-+		ddc->regs = &ddc_clk_regs[en];
-+		ddc->base.regs = &ddc_clk_regs[en].gpio;
-+		break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return;
-+	}
-+
-+	ddc->shifts = &ddc_shift;
-+	ddc->masks = &ddc_mask;
-+
-+}
-+
-+static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
-+{
-+	struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
-+
-+	hpd->regs = &hpd_regs[en];
-+	hpd->shifts = &hpd_shift;
-+	hpd->masks = &hpd_mask;
-+	hpd->base.regs = &hpd_regs[en].gpio;
-+}
-+
-+
-+/* fucntion table */
-+static const struct hw_factory_funcs funcs = {
-+	.create_ddc_data = dal_hw_ddc_create,
-+	.create_ddc_clock = dal_hw_ddc_create,
-+	.create_generic = NULL,
-+	.create_hpd = dal_hw_hpd_create,
-+	.create_sync = NULL,
-+	.create_gsl = NULL,
-+	.define_hpd_registers = define_hpd_registers,
-+	.define_ddc_registers = define_ddc_registers
-+};
-+/*
-+ * dal_hw_factory_dcn10_init
-+ *
-+ * @brief
-+ * Initialize HW factory function pointers and pin info
-+ *
-+ * @param
-+ * struct hw_factory *factory - [out] struct of function pointers
-+ */
-+void dal_hw_factory_dcn10_init(struct hw_factory *factory)
-+{
-+	/*TODO check ASIC CAPs*/
-+	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
-+	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
-+	factory->number_of_pins[GPIO_ID_GENERIC] = 7;
-+	factory->number_of_pins[GPIO_ID_HPD] = 6;
-+	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
-+	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
-+	factory->number_of_pins[GPIO_ID_SYNC] = 2;
-+	factory->number_of_pins[GPIO_ID_GSL] = 4;
-+
-+	factory->funcs = &funcs;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.h.0130~	2017-12-14 06:39:58.430903578 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.h	2017-12-14 06:39:58.430903578 +0100
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_FACTORY_DCN10_H__
-+#define __DAL_HW_FACTORY_DCN10_H__
-+
-+/* Initialize HW factory function pointers and pin info */
-+void dal_hw_factory_dcn10_init(struct hw_factory *factory);
-+
-+#endif /* __DAL_HW_FACTORY_DCN10_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c.0130~	2017-12-14 06:39:58.430903578 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c	2017-12-14 06:39:58.430903578 +0100
-@@ -0,0 +1,408 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "hw_translate_dcn10.h"
-+
-+#include "dm_services.h"
-+#include "include/gpio_types.h"
-+#include "../hw_translate.h"
-+
-+#include "raven1/DCN/dcn_1_0_offset.h"
-+#include "raven1/DCN/dcn_1_0_sh_mask.h"
-+#include "vega10/soc15ip.h"
-+
-+/* begin *********************
-+ * macros to expend register list macro defined in HW object header file */
-+
-+#define BASE_INNER(seg) \
-+	DCE_BASE__INST0_SEG ## seg
-+
-+/* compile time expand base address. */
-+#define BASE(seg) \
-+	BASE_INNER(seg)
-+
-+#define REG(reg_name)\
-+		BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
-+
-+#define REGI(reg_name, block, id)\
-+	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-+				mm ## block ## id ## _ ## reg_name
-+
-+/* macros to expend register list macro defined in HW object header file
-+ * end *********************/
-+
-+static bool offset_to_id(
-+	uint32_t offset,
-+	uint32_t mask,
-+	enum gpio_id *id,
-+	uint32_t *en)
-+{
-+	switch (offset) {
-+	/* GENERIC */
-+	case REG(DC_GPIO_GENERIC_A):
-+		*id = GPIO_ID_GENERIC;
-+		switch (mask) {
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
-+			*en = GPIO_GENERIC_A;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
-+			*en = GPIO_GENERIC_B;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
-+			*en = GPIO_GENERIC_C;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
-+			*en = GPIO_GENERIC_D;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
-+			*en = GPIO_GENERIC_E;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
-+			*en = GPIO_GENERIC_F;
-+			return true;
-+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
-+			*en = GPIO_GENERIC_G;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* HPD */
-+	case REG(DC_GPIO_HPD_A):
-+		*id = GPIO_ID_HPD;
-+		switch (mask) {
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
-+			*en = GPIO_HPD_1;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
-+			*en = GPIO_HPD_2;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
-+			*en = GPIO_HPD_3;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
-+			*en = GPIO_HPD_4;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
-+			*en = GPIO_HPD_5;
-+			return true;
-+		case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
-+			*en = GPIO_HPD_6;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* SYNCA */
-+	case REG(DC_GPIO_SYNCA_A):
-+		*id = GPIO_ID_SYNC;
-+		switch (mask) {
-+		case DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK:
-+			*en = GPIO_SYNC_HSYNC_A;
-+			return true;
-+		case DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK:
-+			*en = GPIO_SYNC_VSYNC_A;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* REG(DC_GPIO_GENLK_MASK */
-+	case REG(DC_GPIO_GENLK_A):
-+		*id = GPIO_ID_GSL;
-+		switch (mask) {
-+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
-+			*en = GPIO_GSL_GENLOCK_CLOCK;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
-+			*en = GPIO_GSL_GENLOCK_VSYNC;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
-+			*en = GPIO_GSL_SWAPLOCK_A;
-+			return true;
-+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
-+			*en = GPIO_GSL_SWAPLOCK_B;
-+			return true;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			return false;
-+		}
-+	break;
-+	/* DDC */
-+	/* we don't care about the GPIO_ID for DDC
-+	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
-+	 * directly in the create method */
-+	case REG(DC_GPIO_DDC1_A):
-+		*en = GPIO_DDC_LINE_DDC1;
-+		return true;
-+	case REG(DC_GPIO_DDC2_A):
-+		*en = GPIO_DDC_LINE_DDC2;
-+		return true;
-+	case REG(DC_GPIO_DDC3_A):
-+		*en = GPIO_DDC_LINE_DDC3;
-+		return true;
-+	case REG(DC_GPIO_DDC4_A):
-+		*en = GPIO_DDC_LINE_DDC4;
-+		return true;
-+	case REG(DC_GPIO_DDC5_A):
-+		*en = GPIO_DDC_LINE_DDC5;
-+		return true;
-+	case REG(DC_GPIO_DDC6_A):
-+		*en = GPIO_DDC_LINE_DDC6;
-+		return true;
-+	case REG(DC_GPIO_DDCVGA_A):
-+		*en = GPIO_DDC_LINE_DDC_VGA;
-+		return true;
-+	/* GPIO_I2CPAD */
-+	case REG(DC_GPIO_I2CPAD_A):
-+		*en = GPIO_DDC_LINE_I2C_PAD;
-+		return true;
-+	/* Not implemented */
-+	case REG(DC_GPIO_PWRSEQ_A):
-+	case REG(DC_GPIO_PAD_STRENGTH_1):
-+	case REG(DC_GPIO_PAD_STRENGTH_2):
-+	case REG(DC_GPIO_DEBUG):
-+		return false;
-+	/* UNEXPECTED */
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+}
-+
-+static bool id_to_offset(
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct gpio_pin_info *info)
-+{
-+	bool result = true;
-+
-+	switch (id) {
-+	case GPIO_ID_DDC_DATA:
-+		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
-+		switch (en) {
-+		case GPIO_DDC_LINE_DDC1:
-+			info->offset = REG(DC_GPIO_DDC1_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC2:
-+			info->offset = REG(DC_GPIO_DDC2_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC3:
-+			info->offset = REG(DC_GPIO_DDC3_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC4:
-+			info->offset = REG(DC_GPIO_DDC4_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC5:
-+			info->offset = REG(DC_GPIO_DDC5_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC6:
-+			info->offset = REG(DC_GPIO_DDC6_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			info->offset = REG(DC_GPIO_DDCVGA_A);
-+		break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			info->offset = REG(DC_GPIO_I2CPAD_A);
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_DDC_CLOCK:
-+		info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
-+		switch (en) {
-+		case GPIO_DDC_LINE_DDC1:
-+			info->offset = REG(DC_GPIO_DDC1_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC2:
-+			info->offset = REG(DC_GPIO_DDC2_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC3:
-+			info->offset = REG(DC_GPIO_DDC3_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC4:
-+			info->offset = REG(DC_GPIO_DDC4_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC5:
-+			info->offset = REG(DC_GPIO_DDC5_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC6:
-+			info->offset = REG(DC_GPIO_DDC6_A);
-+		break;
-+		case GPIO_DDC_LINE_DDC_VGA:
-+			info->offset = REG(DC_GPIO_DDCVGA_A);
-+		break;
-+		case GPIO_DDC_LINE_I2C_PAD:
-+			info->offset = REG(DC_GPIO_I2CPAD_A);
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_GENERIC:
-+		info->offset = REG(DC_GPIO_GENERIC_A);
-+		switch (en) {
-+		case GPIO_GENERIC_A:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
-+		break;
-+		case GPIO_GENERIC_B:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
-+		break;
-+		case GPIO_GENERIC_C:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
-+		break;
-+		case GPIO_GENERIC_D:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
-+		break;
-+		case GPIO_GENERIC_E:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
-+		break;
-+		case GPIO_GENERIC_F:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
-+		break;
-+		case GPIO_GENERIC_G:
-+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_HPD:
-+		info->offset = REG(DC_GPIO_HPD_A);
-+		switch (en) {
-+		case GPIO_HPD_1:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
-+		break;
-+		case GPIO_HPD_2:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
-+		break;
-+		case GPIO_HPD_3:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
-+		break;
-+		case GPIO_HPD_4:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
-+		break;
-+		case GPIO_HPD_5:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
-+		break;
-+		case GPIO_HPD_6:
-+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_SYNC:
-+		switch (en) {
-+		case GPIO_SYNC_HSYNC_A:
-+			info->offset = REG(DC_GPIO_SYNCA_A);
-+			info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;
-+		break;
-+		case GPIO_SYNC_VSYNC_A:
-+			info->offset = REG(DC_GPIO_SYNCA_A);
-+			info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;
-+		break;
-+		case GPIO_SYNC_HSYNC_B:
-+		case GPIO_SYNC_VSYNC_B:
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_GSL:
-+		switch (en) {
-+		case GPIO_GSL_GENLOCK_CLOCK:
-+			info->offset = REG(DC_GPIO_GENLK_A);
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;
-+		break;
-+		case GPIO_GSL_GENLOCK_VSYNC:
-+			info->offset = REG(DC_GPIO_GENLK_A);
-+			info->mask =
-+				DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK;
-+		break;
-+		case GPIO_GSL_SWAPLOCK_A:
-+			info->offset = REG(DC_GPIO_GENLK_A);
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;
-+		break;
-+		case GPIO_GSL_SWAPLOCK_B:
-+			info->offset = REG(DC_GPIO_GENLK_A);
-+			info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;
-+		break;
-+		default:
-+			ASSERT_CRITICAL(false);
-+			result = false;
-+		}
-+	break;
-+	case GPIO_ID_VIP_PAD:
-+	default:
-+		ASSERT_CRITICAL(false);
-+		result = false;
-+	}
-+
-+	if (result) {
-+		info->offset_y = info->offset + 2;
-+		info->offset_en = info->offset + 1;
-+		info->offset_mask = info->offset - 1;
-+
-+		info->mask_y = info->mask;
-+		info->mask_en = info->mask;
-+		info->mask_mask = info->mask;
-+	}
-+
-+	return result;
-+}
-+
-+/* function table */
-+static const struct hw_translate_funcs funcs = {
-+	.offset_to_id = offset_to_id,
-+	.id_to_offset = id_to_offset,
-+};
-+
-+/*
-+ * dal_hw_translate_dcn10_init
-+ *
-+ * @brief
-+ * Initialize Hw translate function pointers.
-+ *
-+ * @param
-+ * struct hw_translate *tr - [out] struct of function pointers
-+ *
-+ */
-+void dal_hw_translate_dcn10_init(struct hw_translate *tr)
-+{
-+	tr->funcs = &funcs;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.h.0130~	2017-12-14 06:39:58.430903578 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.h	2017-12-14 06:39:58.430903578 +0100
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2013-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_TRANSLATE_DCN10_H__
-+#define __DAL_HW_TRANSLATE_DCN10_H__
-+
-+struct hw_translate;
-+
-+/* Initialize Hw translate function pointers */
-+void dal_hw_translate_dcn10_init(struct hw_translate *tr);
-+
-+#endif /* __DAL_HW_TRANSLATE_DCN10_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h.0130~	2017-12-14 06:39:58.430903578 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h	2017-12-14 06:39:58.430903578 +0100
-@@ -0,0 +1,150 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_
-+#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_
-+
-+#include "gpio_regs.h"
-+
-+/****************************** new register headers */
-+/*** following in header */
-+
-+#define DDC_GPIO_REG_LIST_ENTRY(type,cd,id) \
-+	.type ## _reg =   REG(DC_GPIO_DDC ## id ## _ ## type),\
-+	.type ## _mask =  DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\
-+	.type ## _shift = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## __SHIFT
-+
-+#define DDC_GPIO_REG_LIST(cd,id) \
-+	{\
-+	DDC_GPIO_REG_LIST_ENTRY(MASK,cd,id),\
-+	DDC_GPIO_REG_LIST_ENTRY(A,cd,id),\
-+	DDC_GPIO_REG_LIST_ENTRY(EN,cd,id),\
-+	DDC_GPIO_REG_LIST_ENTRY(Y,cd,id)\
-+	}
-+
-+#define DDC_REG_LIST(cd,id) \
-+	DDC_GPIO_REG_LIST(cd,id),\
-+	.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)
-+
-+#define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\
-+	.type ## _reg =   REG(DC_GPIO_DDCVGA_ ## type),\
-+	.type ## _mask =  DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\
-+	.type ## _shift = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## __SHIFT
-+
-+#define DDC_GPIO_VGA_REG_LIST(cd) \
-+	{\
-+	DDC_GPIO_VGA_REG_LIST_ENTRY(MASK,cd),\
-+	DDC_GPIO_VGA_REG_LIST_ENTRY(A,cd),\
-+	DDC_GPIO_VGA_REG_LIST_ENTRY(EN,cd),\
-+	DDC_GPIO_VGA_REG_LIST_ENTRY(Y,cd)\
-+	}
-+
-+#define DDC_VGA_REG_LIST(cd) \
-+	DDC_GPIO_VGA_REG_LIST(cd),\
-+	.ddc_setup = mmDC_I2C_DDCVGA_SETUP
-+
-+#define DDC_GPIO_I2C_REG_LIST_ENTRY(type,cd) \
-+	.type ## _reg =   REG(DC_GPIO_I2CPAD_ ## type),\
-+	.type ## _mask =  DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\
-+	.type ## _shift = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## __SHIFT
-+
-+#define DDC_GPIO_I2C_REG_LIST(cd) \
-+	{\
-+	DDC_GPIO_I2C_REG_LIST_ENTRY(MASK,cd),\
-+	DDC_GPIO_I2C_REG_LIST_ENTRY(A,cd),\
-+	DDC_GPIO_I2C_REG_LIST_ENTRY(EN,cd),\
-+	DDC_GPIO_I2C_REG_LIST_ENTRY(Y,cd)\
-+	}
-+
-+#define DDC_I2C_REG_LIST(cd) \
-+	DDC_GPIO_I2C_REG_LIST(cd),\
-+	.ddc_setup = 0
-+
-+#define DDC_MASK_SH_LIST(mask_sh) \
-+		SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
-+		SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\
-+		SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_MODE, mask_sh),\
-+		SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1DATA_PD_EN, mask_sh),\
-+		SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1CLK_PD_EN, mask_sh),\
-+		SF_DDC(DC_GPIO_DDC1_MASK, AUX_PAD1_MODE, mask_sh),\
-+		SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\
-+		SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh)
-+
-+
-+struct ddc_registers {
-+	struct gpio_registers gpio;
-+	uint32_t ddc_setup;
-+};
-+
-+struct ddc_sh_mask {
-+	/* i2c_dd_setup */
-+	uint32_t DC_I2C_DDC1_ENABLE;
-+	uint32_t DC_I2C_DDC1_EDID_DETECT_ENABLE;
-+	uint32_t DC_I2C_DDC1_EDID_DETECT_MODE;
-+	/* ddc1_mask */
-+	uint32_t DC_GPIO_DDC1DATA_PD_EN;
-+	uint32_t DC_GPIO_DDC1CLK_PD_EN;
-+	uint32_t AUX_PAD1_MODE;
-+	/* i2cpad_mask */
-+	uint32_t DC_GPIO_SDA_PD_DIS;
-+	uint32_t DC_GPIO_SCL_PD_DIS;
-+};
-+
-+
-+
-+/*** following in dc_resource */
-+
-+#define ddc_data_regs(id) \
-+{\
-+	DDC_REG_LIST(DATA,id)\
-+}
-+
-+#define ddc_clk_regs(id) \
-+{\
-+	DDC_REG_LIST(CLK,id)\
-+}
-+
-+#define ddc_vga_data_regs \
-+{\
-+	DDC_VGA_REG_LIST(DATA)\
-+}
-+
-+#define ddc_vga_clk_regs \
-+{\
-+	DDC_VGA_REG_LIST(CLK)\
-+}
-+
-+#define ddc_i2c_data_regs \
-+{\
-+	DDC_I2C_REG_LIST(SDA)\
-+}
-+
-+#define ddc_i2c_clk_regs \
-+{\
-+	DDC_I2C_REG_LIST(SCL)\
-+}
-+
-+
-+#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c.0130~	2017-12-14 06:39:58.430903578 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c	2017-12-14 06:39:58.430903578 +0100
-@@ -0,0 +1,63 @@
-+/*
-+ * Copyright 2013-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "dm_services.h"
-+#include "include/gpio_types.h"
-+#include "../hw_factory.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "../hw_gpio.h"
-+#include "../hw_ddc.h"
-+#include "../hw_hpd.h"
-+
-+/* function table */
-+static const struct hw_factory_funcs funcs = {
-+	.create_ddc_data = NULL,
-+	.create_ddc_clock = NULL,
-+	.create_generic = NULL,
-+	.create_hpd = NULL,
-+	.create_sync = NULL,
-+	.create_gsl = NULL,
-+};
-+
-+void dal_hw_factory_diag_fpga_init(struct hw_factory *factory)
-+{
-+	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
-+	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
-+	factory->number_of_pins[GPIO_ID_GENERIC] = 7;
-+	factory->number_of_pins[GPIO_ID_HPD] = 6;
-+	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
-+	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
-+	factory->number_of_pins[GPIO_ID_SYNC] = 2;
-+	factory->number_of_pins[GPIO_ID_GSL] = 4;
-+	factory->funcs = &funcs;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.h.0130~	2017-12-14 06:39:58.430903578 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.h	2017-12-14 06:39:58.430903578 +0100
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2013-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_FACTORY_DIAG_FPGA_H__
-+#define __DAL_HW_FACTORY_DIAG_FPGA_H__
-+
-+/* Initialize HW factory function pointers and pin info */
-+void dal_hw_factory_diag_fpga_init(struct hw_factory *factory);
-+
-+#endif /* __DAL_HW_FACTORY_DIAG_FPGA_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.c.0130~	2017-12-14 06:39:58.430903578 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.c	2017-12-14 06:39:58.430903578 +0100
-@@ -0,0 +1,40 @@
-+/*
-+ * Copyright 2013-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "include/gpio_types.h"
-+
-+#include "../hw_translate.h"
-+
-+/* function table */
-+static const struct hw_translate_funcs funcs = {
-+	.offset_to_id = NULL,
-+	.id_to_offset = NULL,
-+};
-+
-+void dal_hw_translate_diag_fpga_init(struct hw_translate *tr)
-+{
-+	tr->funcs = &funcs;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.h.0130~	2017-12-14 06:39:58.430903578 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_translate_diag.h	2017-12-14 06:39:58.430903578 +0100
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2013-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_TRANSLATE_DIAG_FPGA_H__
-+#define __DAL_HW_TRANSLATE_DIAG_FPGA_H__
-+
-+struct hw_translate;
-+
-+/* Initialize Hw translate function pointers */
-+void dal_hw_translate_diag_fpga_init(struct hw_translate *tr);
-+
-+#endif /* __DAL_HW_TRANSLATE_DIAG_FPGA_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c.0130~	2017-12-14 06:39:58.431903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c	2017-12-14 06:39:58.431903579 +0100
-@@ -0,0 +1,272 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/gpio_interface.h"
-+#include "include/gpio_service_interface.h"
-+#include "hw_gpio.h"
-+#include "hw_translate.h"
-+#include "hw_factory.h"
-+#include "gpio_service.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+/*
-+ * @brief
-+ * Public API
-+ */
-+
-+enum gpio_result dal_gpio_open(
-+	struct gpio *gpio,
-+	enum gpio_mode mode)
-+{
-+	return dal_gpio_open_ex(gpio, mode);
-+}
-+
-+enum gpio_result dal_gpio_open_ex(
-+	struct gpio *gpio,
-+	enum gpio_mode mode)
-+{
-+	if (gpio->pin) {
-+		ASSERT_CRITICAL(false);
-+		return GPIO_RESULT_ALREADY_OPENED;
-+	}
-+
-+	gpio->mode = mode;
-+
-+	return dal_gpio_service_open(
-+		gpio->service, gpio->id, gpio->en, mode, &gpio->pin);
-+}
-+
-+enum gpio_result dal_gpio_get_value(
-+	const struct gpio *gpio,
-+	uint32_t *value)
-+{
-+	if (!gpio->pin) {
-+		BREAK_TO_DEBUGGER();
-+		return GPIO_RESULT_NULL_HANDLE;
-+	}
-+
-+	return gpio->pin->funcs->get_value(gpio->pin, value);
-+}
-+
-+enum gpio_result dal_gpio_set_value(
-+	const struct gpio *gpio,
-+	uint32_t value)
-+{
-+	if (!gpio->pin) {
-+		BREAK_TO_DEBUGGER();
-+		return GPIO_RESULT_NULL_HANDLE;
-+	}
-+
-+	return gpio->pin->funcs->set_value(gpio->pin, value);
-+}
-+
-+enum gpio_mode dal_gpio_get_mode(
-+	const struct gpio *gpio)
-+{
-+	return gpio->mode;
-+}
-+
-+enum gpio_result dal_gpio_change_mode(
-+	struct gpio *gpio,
-+	enum gpio_mode mode)
-+{
-+	if (!gpio->pin) {
-+		BREAK_TO_DEBUGGER();
-+		return GPIO_RESULT_NULL_HANDLE;
-+	}
-+
-+	return gpio->pin->funcs->change_mode(gpio->pin, mode);
-+}
-+
-+enum gpio_id dal_gpio_get_id(
-+	const struct gpio *gpio)
-+{
-+	return gpio->id;
-+}
-+
-+uint32_t dal_gpio_get_enum(
-+	const struct gpio *gpio)
-+{
-+	return gpio->en;
-+}
-+
-+enum gpio_result dal_gpio_set_config(
-+	struct gpio *gpio,
-+	const struct gpio_config_data *config_data)
-+{
-+	if (!gpio->pin) {
-+		BREAK_TO_DEBUGGER();
-+		return GPIO_RESULT_NULL_HANDLE;
-+	}
-+
-+	return gpio->pin->funcs->set_config(gpio->pin, config_data);
-+}
-+
-+enum gpio_result dal_gpio_get_pin_info(
-+	const struct gpio *gpio,
-+	struct gpio_pin_info *pin_info)
-+{
-+	return gpio->service->translate.funcs->id_to_offset(
-+		gpio->id, gpio->en, pin_info) ?
-+		GPIO_RESULT_OK : GPIO_RESULT_INVALID_DATA;
-+}
-+
-+enum sync_source dal_gpio_get_sync_source(
-+	const struct gpio *gpio)
-+{
-+	switch (gpio->id) {
-+	case GPIO_ID_GENERIC:
-+		switch (gpio->en) {
-+		case GPIO_GENERIC_A:
-+			return SYNC_SOURCE_IO_GENERIC_A;
-+		case GPIO_GENERIC_B:
-+			return SYNC_SOURCE_IO_GENERIC_B;
-+		case GPIO_GENERIC_C:
-+			return SYNC_SOURCE_IO_GENERIC_C;
-+		case GPIO_GENERIC_D:
-+			return SYNC_SOURCE_IO_GENERIC_D;
-+		case GPIO_GENERIC_E:
-+			return SYNC_SOURCE_IO_GENERIC_E;
-+		case GPIO_GENERIC_F:
-+			return SYNC_SOURCE_IO_GENERIC_F;
-+		default:
-+			return SYNC_SOURCE_NONE;
-+		}
-+	break;
-+	case GPIO_ID_SYNC:
-+		switch (gpio->en) {
-+		case GPIO_SYNC_HSYNC_A:
-+			return SYNC_SOURCE_IO_HSYNC_A;
-+		case GPIO_SYNC_VSYNC_A:
-+			return SYNC_SOURCE_IO_VSYNC_A;
-+		case GPIO_SYNC_HSYNC_B:
-+			return SYNC_SOURCE_IO_HSYNC_B;
-+		case GPIO_SYNC_VSYNC_B:
-+			return SYNC_SOURCE_IO_VSYNC_B;
-+		default:
-+			return SYNC_SOURCE_NONE;
-+		}
-+	break;
-+	case GPIO_ID_HPD:
-+		switch (gpio->en) {
-+		case GPIO_HPD_1:
-+			return SYNC_SOURCE_IO_HPD1;
-+		case GPIO_HPD_2:
-+			return SYNC_SOURCE_IO_HPD2;
-+		default:
-+			return SYNC_SOURCE_NONE;
-+		}
-+	break;
-+	case GPIO_ID_GSL:
-+		switch (gpio->en) {
-+		case GPIO_GSL_GENLOCK_CLOCK:
-+			return SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK;
-+		case GPIO_GSL_GENLOCK_VSYNC:
-+			return SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC;
-+		case GPIO_GSL_SWAPLOCK_A:
-+			return SYNC_SOURCE_GSL_IO_SWAPLOCK_A;
-+		case GPIO_GSL_SWAPLOCK_B:
-+			return SYNC_SOURCE_GSL_IO_SWAPLOCK_B;
-+		default:
-+			return SYNC_SOURCE_NONE;
-+		}
-+	break;
-+	default:
-+		return SYNC_SOURCE_NONE;
-+	}
-+}
-+
-+enum gpio_pin_output_state dal_gpio_get_output_state(
-+	const struct gpio *gpio)
-+{
-+	return gpio->output_state;
-+}
-+
-+void dal_gpio_close(
-+	struct gpio *gpio)
-+{
-+	if (!gpio)
-+		return;
-+
-+	dal_gpio_service_close(gpio->service, &gpio->pin);
-+
-+	gpio->mode = GPIO_MODE_UNKNOWN;
-+}
-+
-+/*
-+ * @brief
-+ * Creation and destruction
-+ */
-+
-+struct gpio *dal_gpio_create(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en,
-+	enum gpio_pin_output_state output_state)
-+{
-+	struct gpio *gpio = kzalloc(sizeof(struct gpio), GFP_KERNEL);
-+
-+	if (!gpio) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	gpio->service = service;
-+	gpio->pin = NULL;
-+	gpio->id = id;
-+	gpio->en = en;
-+	gpio->mode = GPIO_MODE_UNKNOWN;
-+	gpio->output_state = output_state;
-+
-+	return gpio;
-+}
-+
-+void dal_gpio_destroy(
-+	struct gpio **gpio)
-+{
-+	if (!gpio || !*gpio) {
-+		ASSERT_CRITICAL(false);
-+		return;
-+	}
-+
-+	dal_gpio_close(*gpio);
-+
-+	kfree(*gpio);
-+
-+	*gpio = NULL;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h.0130~	2017-12-14 06:39:58.431903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/gpio_regs.h	2017-12-14 06:39:58.431903579 +0100
-@@ -0,0 +1,45 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_GPIO_REGS_H_
-+#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_GPIO_REGS_H_
-+
-+struct gpio_registers {
-+	uint32_t MASK_reg;
-+	uint32_t MASK_mask;
-+	uint32_t MASK_shift;
-+	uint32_t A_reg;
-+	uint32_t A_mask;
-+	uint32_t A_shift;
-+	uint32_t EN_reg;
-+	uint32_t EN_mask;
-+	uint32_t EN_shift;
-+	uint32_t Y_reg;
-+	uint32_t Y_mask;
-+	uint32_t Y_shift;
-+};
-+
-+
-+#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_GPIO_REGS_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c.0130~	2017-12-14 06:39:58.431903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c	2017-12-14 06:39:58.431903579 +0100
-@@ -0,0 +1,591 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "dm_services.h"
-+#include "include/gpio_interface.h"
-+#include "include/gpio_service_interface.h"
-+#include "hw_translate.h"
-+#include "hw_factory.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "gpio_service.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "hw_gpio.h"
-+
-+/*
-+ * @brief
-+ * Public API.
-+ */
-+
-+struct gpio_service *dal_gpio_service_create(
-+	enum dce_version dce_version_major,
-+	enum dce_version dce_version_minor,
-+	struct dc_context *ctx)
-+{
-+	struct gpio_service *service;
-+
-+	uint32_t index_of_id;
-+
-+	service = kzalloc(sizeof(struct gpio_service), GFP_KERNEL);
-+
-+	if (!service) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if (!dal_hw_translate_init(&service->translate, dce_version_major,
-+			dce_version_minor)) {
-+		BREAK_TO_DEBUGGER();
-+		goto failure_1;
-+	}
-+
-+	if (!dal_hw_factory_init(&service->factory, dce_version_major,
-+			dce_version_minor)) {
-+		BREAK_TO_DEBUGGER();
-+		goto failure_1;
-+	}
-+
-+	/* allocate and initialize business storage */
-+	{
-+		const uint32_t bits_per_uint = sizeof(uint32_t) << 3;
-+
-+		index_of_id = 0;
-+		service->ctx = ctx;
-+
-+		do {
-+			uint32_t number_of_bits =
-+				service->factory.number_of_pins[index_of_id];
-+
-+			uint32_t number_of_uints =
-+				(number_of_bits + bits_per_uint - 1) /
-+				bits_per_uint;
-+
-+			uint32_t *slot;
-+
-+			if (number_of_bits) {
-+				uint32_t index_of_uint = 0;
-+
-+				slot = kzalloc(number_of_uints * sizeof(uint32_t),
-+					       GFP_KERNEL);
-+
-+				if (!slot) {
-+					BREAK_TO_DEBUGGER();
-+					goto failure_2;
-+				}
-+
-+				do {
-+					slot[index_of_uint] = 0;
-+
-+					++index_of_uint;
-+				} while (index_of_uint < number_of_uints);
-+			} else
-+				slot = NULL;
-+
-+			service->busyness[index_of_id] = slot;
-+
-+			++index_of_id;
-+		} while (index_of_id < GPIO_ID_COUNT);
-+	}
-+
-+	return service;
-+
-+failure_2:
-+	while (index_of_id) {
-+		uint32_t *slot;
-+
-+		--index_of_id;
-+
-+		slot = service->busyness[index_of_id];
-+
-+		kfree(slot);
-+	}
-+
-+failure_1:
-+	kfree(service);
-+
-+	return NULL;
-+}
-+
-+struct gpio *dal_gpio_service_create_irq(
-+	struct gpio_service *service,
-+	uint32_t offset,
-+	uint32_t mask)
-+{
-+	enum gpio_id id;
-+	uint32_t en;
-+
-+	if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	return dal_gpio_create_irq(service, id, en);
-+}
-+
-+void dal_gpio_service_destroy(
-+	struct gpio_service **ptr)
-+{
-+	if (!ptr || !*ptr) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	/* free business storage */
-+	{
-+		uint32_t index_of_id = 0;
-+
-+		do {
-+			uint32_t *slot = (*ptr)->busyness[index_of_id];
-+
-+			kfree(slot);
-+
-+			++index_of_id;
-+		} while (index_of_id < GPIO_ID_COUNT);
-+	}
-+
-+	kfree(*ptr);
-+
-+	*ptr = NULL;
-+}
-+
-+/*
-+ * @brief
-+ * Private API.
-+ */
-+
-+static bool is_pin_busy(
-+	const struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	const uint32_t bits_per_uint = sizeof(uint32_t) << 3;
-+
-+	const uint32_t *slot = service->busyness[id] + (en / bits_per_uint);
-+
-+	return 0 != (*slot & (1 << (en % bits_per_uint)));
-+}
-+
-+static void set_pin_busy(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	const uint32_t bits_per_uint = sizeof(uint32_t) << 3;
-+
-+	service->busyness[id][en / bits_per_uint] |=
-+		(1 << (en % bits_per_uint));
-+}
-+
-+static void set_pin_free(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	const uint32_t bits_per_uint = sizeof(uint32_t) << 3;
-+
-+	service->busyness[id][en / bits_per_uint] &=
-+		~(1 << (en % bits_per_uint));
-+}
-+
-+enum gpio_result dal_gpio_service_open(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en,
-+	enum gpio_mode mode,
-+	struct hw_gpio_pin **ptr)
-+{
-+	struct hw_gpio_pin *pin;
-+
-+	if (!service->busyness[id]) {
-+		ASSERT_CRITICAL(false);
-+		return GPIO_RESULT_OPEN_FAILED;
-+	}
-+
-+	if (is_pin_busy(service, id, en)) {
-+		ASSERT_CRITICAL(false);
-+		return GPIO_RESULT_DEVICE_BUSY;
-+	}
-+
-+	switch (id) {
-+	case GPIO_ID_DDC_DATA:
-+		pin = service->factory.funcs->create_ddc_data(
-+			service->ctx, id, en);
-+		service->factory.funcs->define_ddc_registers(pin, en);
-+	break;
-+	case GPIO_ID_DDC_CLOCK:
-+		pin = service->factory.funcs->create_ddc_clock(
-+			service->ctx, id, en);
-+		service->factory.funcs->define_ddc_registers(pin, en);
-+	break;
-+	case GPIO_ID_GENERIC:
-+		pin = service->factory.funcs->create_generic(
-+			service->ctx, id, en);
-+	break;
-+	case GPIO_ID_HPD:
-+		pin = service->factory.funcs->create_hpd(
-+			service->ctx, id, en);
-+		service->factory.funcs->define_hpd_registers(pin, en);
-+	break;
-+	case GPIO_ID_SYNC:
-+		pin = service->factory.funcs->create_sync(
-+			service->ctx, id, en);
-+	break;
-+	case GPIO_ID_GSL:
-+		pin = service->factory.funcs->create_gsl(
-+			service->ctx, id, en);
-+	break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+	}
-+
-+	if (!pin) {
-+		ASSERT_CRITICAL(false);
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+	}
-+
-+	if (!pin->funcs->open(pin, mode)) {
-+		ASSERT_CRITICAL(false);
-+		dal_gpio_service_close(service, &pin);
-+		return GPIO_RESULT_OPEN_FAILED;
-+	}
-+
-+	set_pin_busy(service, id, en);
-+	*ptr = pin;
-+	return GPIO_RESULT_OK;
-+}
-+
-+void dal_gpio_service_close(
-+	struct gpio_service *service,
-+	struct hw_gpio_pin **ptr)
-+{
-+	struct hw_gpio_pin *pin;
-+
-+	if (!ptr) {
-+		ASSERT_CRITICAL(false);
-+		return;
-+	}
-+
-+	pin = *ptr;
-+
-+	if (pin) {
-+		set_pin_free(service, pin->id, pin->en);
-+
-+		pin->funcs->close(pin);
-+
-+		pin->funcs->destroy(ptr);
-+	}
-+}
-+
-+
-+enum dc_irq_source dal_irq_get_source(
-+	const struct gpio *irq)
-+{
-+	enum gpio_id id = dal_gpio_get_id(irq);
-+
-+	switch (id) {
-+	case GPIO_ID_HPD:
-+		return (enum dc_irq_source)(DC_IRQ_SOURCE_HPD1 +
-+			dal_gpio_get_enum(irq));
-+	case GPIO_ID_GPIO_PAD:
-+		return (enum dc_irq_source)(DC_IRQ_SOURCE_GPIOPAD0 +
-+			dal_gpio_get_enum(irq));
-+	default:
-+		return DC_IRQ_SOURCE_INVALID;
-+	}
-+}
-+
-+enum dc_irq_source dal_irq_get_rx_source(
-+	const struct gpio *irq)
-+{
-+	enum gpio_id id = dal_gpio_get_id(irq);
-+
-+	switch (id) {
-+	case GPIO_ID_HPD:
-+		return (enum dc_irq_source)(DC_IRQ_SOURCE_HPD1RX +
-+			dal_gpio_get_enum(irq));
-+	default:
-+		return DC_IRQ_SOURCE_INVALID;
-+	}
-+}
-+
-+enum gpio_result dal_irq_setup_hpd_filter(
-+	struct gpio *irq,
-+	struct gpio_hpd_config *config)
-+{
-+	struct gpio_config_data config_data;
-+
-+	if (!config)
-+		return GPIO_RESULT_INVALID_DATA;
-+
-+	config_data.type = GPIO_CONFIG_TYPE_HPD;
-+	config_data.config.hpd = *config;
-+
-+	return dal_gpio_set_config(irq, &config_data);
-+}
-+
-+/*
-+ * @brief
-+ * Creation and destruction
-+ */
-+
-+struct gpio *dal_gpio_create_irq(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	struct gpio *irq;
-+
-+	switch (id) {
-+	case GPIO_ID_HPD:
-+	case GPIO_ID_GPIO_PAD:
-+	break;
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	irq = dal_gpio_create(
-+		service, id, en, GPIO_PIN_OUTPUT_STATE_DEFAULT);
-+
-+	if (irq)
-+		return irq;
-+
-+	ASSERT_CRITICAL(false);
-+	return NULL;
-+}
-+
-+void dal_gpio_destroy_irq(
-+	struct gpio **irq)
-+{
-+	if (!irq || !*irq) {
-+		ASSERT_CRITICAL(false);
-+		return;
-+	}
-+
-+	dal_gpio_close(*irq);
-+	dal_gpio_destroy(irq);
-+	kfree(*irq);
-+
-+	*irq = NULL;
-+}
-+
-+struct ddc *dal_gpio_create_ddc(
-+	struct gpio_service *service,
-+	uint32_t offset,
-+	uint32_t mask,
-+	struct gpio_ddc_hw_info *info)
-+{
-+	enum gpio_id id;
-+	uint32_t en;
-+	struct ddc *ddc;
-+
-+	if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en))
-+		return NULL;
-+
-+	ddc = kzalloc(sizeof(struct ddc), GFP_KERNEL);
-+
-+	if (!ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	ddc->pin_data = dal_gpio_create(
-+		service, GPIO_ID_DDC_DATA, en, GPIO_PIN_OUTPUT_STATE_DEFAULT);
-+
-+	if (!ddc->pin_data) {
-+		BREAK_TO_DEBUGGER();
-+		goto failure_1;
-+	}
-+
-+	ddc->pin_clock = dal_gpio_create(
-+		service, GPIO_ID_DDC_CLOCK, en, GPIO_PIN_OUTPUT_STATE_DEFAULT);
-+
-+	if (!ddc->pin_clock) {
-+		BREAK_TO_DEBUGGER();
-+		goto failure_2;
-+	}
-+
-+	ddc->hw_info = *info;
-+
-+	ddc->ctx = service->ctx;
-+
-+	return ddc;
-+
-+failure_2:
-+	dal_gpio_destroy(&ddc->pin_data);
-+
-+failure_1:
-+	kfree(ddc);
-+
-+	return NULL;
-+}
-+
-+void dal_gpio_destroy_ddc(
-+	struct ddc **ddc)
-+{
-+	if (!ddc || !*ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	dal_ddc_close(*ddc);
-+	dal_gpio_destroy(&(*ddc)->pin_data);
-+	dal_gpio_destroy(&(*ddc)->pin_clock);
-+	kfree(*ddc);
-+
-+	*ddc = NULL;
-+}
-+
-+enum gpio_result dal_ddc_open(
-+	struct ddc *ddc,
-+	enum gpio_mode mode,
-+	enum gpio_ddc_config_type config_type)
-+{
-+	enum gpio_result result;
-+
-+	struct gpio_config_data config_data;
-+	struct hw_gpio *hw_data;
-+	struct hw_gpio *hw_clock;
-+
-+	result = dal_gpio_open_ex(ddc->pin_data, mode);
-+
-+	if (result != GPIO_RESULT_OK) {
-+		BREAK_TO_DEBUGGER();
-+		return result;
-+	}
-+
-+	result = dal_gpio_open_ex(ddc->pin_clock, mode);
-+
-+	if (result != GPIO_RESULT_OK) {
-+		BREAK_TO_DEBUGGER();
-+		goto failure;
-+	}
-+
-+	/* DDC clock and data pins should belong
-+	 * to the same DDC block id,
-+	 * we use the data pin to set the pad mode. */
-+
-+	if (mode == GPIO_MODE_INPUT)
-+		/* this is from detect_sink_type,
-+		 * we need extra delay there */
-+		config_data.type = GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE;
-+	else
-+		config_data.type = GPIO_CONFIG_TYPE_DDC;
-+
-+	config_data.config.ddc.type = config_type;
-+
-+	hw_data = FROM_HW_GPIO_PIN(ddc->pin_data->pin);
-+	hw_clock = FROM_HW_GPIO_PIN(ddc->pin_clock->pin);
-+
-+	config_data.config.ddc.data_en_bit_present = hw_data->store.en != 0;
-+	config_data.config.ddc.clock_en_bit_present = hw_clock->store.en != 0;
-+
-+	result = dal_gpio_set_config(ddc->pin_data, &config_data);
-+
-+	if (result == GPIO_RESULT_OK)
-+		return result;
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	dal_gpio_close(ddc->pin_clock);
-+
-+failure:
-+	dal_gpio_close(ddc->pin_data);
-+
-+	return result;
-+}
-+
-+enum gpio_result dal_ddc_change_mode(
-+	struct ddc *ddc,
-+	enum gpio_mode mode)
-+{
-+	enum gpio_result result;
-+
-+	enum gpio_mode original_mode =
-+		dal_gpio_get_mode(ddc->pin_data);
-+
-+	result = dal_gpio_change_mode(ddc->pin_data, mode);
-+
-+	/* [anaumov] DAL2 code returns GPIO_RESULT_NON_SPECIFIC_ERROR
-+	 * in case of failures;
-+	 * set_mode() is so that, in case of failure,
-+	 * we must explicitly set original mode */
-+
-+	if (result != GPIO_RESULT_OK)
-+		goto failure;
-+
-+	result = dal_gpio_change_mode(ddc->pin_clock, mode);
-+
-+	if (result == GPIO_RESULT_OK)
-+		return result;
-+
-+	dal_gpio_change_mode(ddc->pin_clock, original_mode);
-+
-+failure:
-+	dal_gpio_change_mode(ddc->pin_data, original_mode);
-+
-+	return result;
-+}
-+
-+enum gpio_ddc_line dal_ddc_get_line(
-+	const struct ddc *ddc)
-+{
-+	return (enum gpio_ddc_line)dal_gpio_get_enum(ddc->pin_data);
-+}
-+
-+enum gpio_result dal_ddc_set_config(
-+	struct ddc *ddc,
-+	enum gpio_ddc_config_type config_type)
-+{
-+	struct gpio_config_data config_data;
-+
-+	config_data.type = GPIO_CONFIG_TYPE_DDC;
-+
-+	config_data.config.ddc.type = config_type;
-+	config_data.config.ddc.data_en_bit_present = false;
-+	config_data.config.ddc.clock_en_bit_present = false;
-+
-+	return dal_gpio_set_config(ddc->pin_data, &config_data);
-+}
-+
-+void dal_ddc_close(
-+	struct ddc *ddc)
-+{
-+	dal_gpio_close(ddc->pin_clock);
-+	dal_gpio_close(ddc->pin_data);
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h.0130~	2017-12-14 06:39:58.431903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h	2017-12-14 06:39:58.431903579 +0100
-@@ -0,0 +1,56 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GPIO_SERVICE_H__
-+#define __DAL_GPIO_SERVICE_H__
-+
-+struct hw_translate;
-+struct hw_factory;
-+
-+struct gpio_service {
-+	struct dc_context *ctx;
-+	struct hw_translate translate;
-+	struct hw_factory factory;
-+	/*
-+	 * @brief
-+	 * Business storage.
-+	 * For each member of 'enum gpio_id',
-+	 * store array of bits (packed into uint32_t slots),
-+	 * index individual bit by 'en' value */
-+	uint32_t *busyness[GPIO_ID_COUNT];
-+};
-+
-+enum gpio_result dal_gpio_service_open(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en,
-+	enum gpio_mode mode,
-+	struct hw_gpio_pin **ptr);
-+
-+void dal_gpio_service_close(
-+	struct gpio_service *service,
-+	struct hw_gpio_pin **ptr);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h.0130~	2017-12-14 06:39:58.431903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h	2017-12-14 06:39:58.431903579 +0100
-@@ -0,0 +1,79 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_HPD_REGS_H_
-+#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_HPD_REGS_H_
-+
-+#include "gpio_regs.h"
-+
-+#define ONE_MORE_0 1
-+#define ONE_MORE_1 2
-+#define ONE_MORE_2 3
-+#define ONE_MORE_3 4
-+#define ONE_MORE_4 5
-+#define ONE_MORE_5 6
-+
-+
-+#define HPD_GPIO_REG_LIST_ENTRY(type,cd,id) \
-+	.type ## _reg =  REG(DC_GPIO_HPD_## type),\
-+	.type ## _mask =  DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## _MASK,\
-+	.type ## _shift = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## __SHIFT
-+
-+#define HPD_GPIO_REG_LIST(id) \
-+	{\
-+	HPD_GPIO_REG_LIST_ENTRY(MASK,cd,id),\
-+	HPD_GPIO_REG_LIST_ENTRY(A,cd,id),\
-+	HPD_GPIO_REG_LIST_ENTRY(EN,cd,id),\
-+	HPD_GPIO_REG_LIST_ENTRY(Y,cd,id)\
-+	}
-+
-+#define HPD_REG_LIST(id) \
-+	HPD_GPIO_REG_LIST(ONE_MORE_ ## id), \
-+	.int_status = REGI(DC_HPD_INT_STATUS, HPD, id),\
-+	.toggle_filt_cntl = REGI(DC_HPD_TOGGLE_FILT_CNTL, HPD, id)
-+
-+ #define HPD_MASK_SH_LIST(mask_sh) \
-+		SF_HPD(DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED, mask_sh),\
-+		SF_HPD(DC_HPD_INT_STATUS, DC_HPD_SENSE, mask_sh),\
-+		SF_HPD(DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_CONNECT_INT_DELAY, mask_sh),\
-+		SF_HPD(DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_DISCONNECT_INT_DELAY, mask_sh)
-+
-+struct hpd_registers {
-+	struct gpio_registers gpio;
-+	uint32_t int_status;
-+	uint32_t toggle_filt_cntl;
-+};
-+
-+struct hpd_sh_mask {
-+	/* int_status */
-+	uint32_t DC_HPD_SENSE_DELAYED;
-+	uint32_t DC_HPD_SENSE;
-+	/* toggle_filt_cntl */
-+	uint32_t DC_HPD_CONNECT_INT_DELAY;
-+	uint32_t DC_HPD_DISCONNECT_INT_DELAY;
-+};
-+
-+
-+#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_HPD_REGS_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c.0130~	2017-12-14 06:39:58.431903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c	2017-12-14 06:39:58.431903579 +0100
-@@ -0,0 +1,232 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/gpio_types.h"
-+#include "hw_gpio.h"
-+#include "hw_ddc.h"
-+
-+#include "reg_helper.h"
-+#include "gpio_regs.h"
-+
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	ddc->shifts->field_name, ddc->masks->field_name
-+
-+#define CTX \
-+	ddc->base.base.ctx
-+#define REG(reg)\
-+	(ddc->regs->reg)
-+
-+static void destruct(
-+	struct hw_ddc *pin)
-+{
-+	dal_hw_gpio_destruct(&pin->base);
-+}
-+
-+static void destroy(
-+	struct hw_gpio_pin **ptr)
-+{
-+	struct hw_ddc *pin = HW_DDC_FROM_BASE(*ptr);
-+
-+	destruct(pin);
-+
-+	kfree(pin);
-+
-+	*ptr = NULL;
-+}
-+
-+static enum gpio_result set_config(
-+	struct hw_gpio_pin *ptr,
-+	const struct gpio_config_data *config_data)
-+{
-+	struct hw_ddc *ddc = HW_DDC_FROM_BASE(ptr);
-+	struct hw_gpio *hw_gpio = NULL;
-+	uint32_t regval;
-+	uint32_t ddc_data_pd_en = 0;
-+	uint32_t ddc_clk_pd_en = 0;
-+	uint32_t aux_pad_mode = 0;
-+
-+	hw_gpio = &ddc->base;
-+
-+	if (hw_gpio == NULL) {
-+		ASSERT_CRITICAL(false);
-+		return GPIO_RESULT_NULL_HANDLE;
-+	}
-+
-+	regval = REG_GET_3(gpio.MASK_reg,
-+			DC_GPIO_DDC1DATA_PD_EN, &ddc_data_pd_en,
-+			DC_GPIO_DDC1CLK_PD_EN, &ddc_clk_pd_en,
-+			AUX_PAD1_MODE, &aux_pad_mode);
-+
-+	switch (config_data->config.ddc.type) {
-+	case GPIO_DDC_CONFIG_TYPE_MODE_I2C:
-+		/* On plug-in, there is a transient level on the pad
-+		 * which must be discharged through the internal pull-down.
-+		 * Enable internal pull-down, 2.5msec discharge time
-+		 * is required for detection of AUX mode */
-+		if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) {
-+			if (!ddc_data_pd_en || !ddc_clk_pd_en) {
-+
-+				REG_SET_2(gpio.MASK_reg, regval,
-+						DC_GPIO_DDC1DATA_PD_EN, 1,
-+						DC_GPIO_DDC1CLK_PD_EN, 1);
-+
-+				if (config_data->type ==
-+						GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
-+					msleep(3);
-+			}
-+		} else {
-+			uint32_t reg2;
-+			uint32_t sda_pd_dis = 0;
-+			uint32_t scl_pd_dis = 0;
-+
-+			reg2 = REG_GET_2(gpio.MASK_reg,
-+					DC_GPIO_SDA_PD_DIS, &sda_pd_dis,
-+					DC_GPIO_SCL_PD_DIS, &scl_pd_dis);
-+
-+			if (sda_pd_dis) {
-+				REG_SET(gpio.MASK_reg, regval,
-+						DC_GPIO_SDA_PD_DIS, 0);
-+
-+				if (config_data->type ==
-+						GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
-+					msleep(3);
-+			}
-+
-+			if (!scl_pd_dis) {
-+				REG_SET(gpio.MASK_reg, regval,
-+						DC_GPIO_SCL_PD_DIS, 1);
-+
-+				if (config_data->type ==
-+						GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
-+					msleep(3);
-+			}
-+		}
-+
-+		if (aux_pad_mode) {
-+			/* let pins to get de-asserted
-+			 * before setting pad to I2C mode */
-+			if (config_data->config.ddc.data_en_bit_present ||
-+				config_data->config.ddc.clock_en_bit_present)
-+				/* [anaumov] in DAL2, there was
-+				 * dc_service_delay_in_microseconds(2000); */
-+				msleep(2);
-+
-+			/* set the I2C pad mode */
-+			/* read the register again,
-+			 * some bits may have been changed */
-+			REG_UPDATE(gpio.MASK_reg,
-+					AUX_PAD1_MODE, 0);
-+		}
-+
-+		return GPIO_RESULT_OK;
-+	case GPIO_DDC_CONFIG_TYPE_MODE_AUX:
-+		/* set the AUX pad mode */
-+		if (!aux_pad_mode) {
-+			REG_SET(gpio.MASK_reg, regval,
-+					AUX_PAD1_MODE, 1);
-+		}
-+
-+		return GPIO_RESULT_OK;
-+	case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT:
-+		if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-+			(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
-+			REG_UPDATE_3(ddc_setup,
-+				DC_I2C_DDC1_ENABLE, 1,
-+				DC_I2C_DDC1_EDID_DETECT_ENABLE, 1,
-+				DC_I2C_DDC1_EDID_DETECT_MODE, 0);
-+			return GPIO_RESULT_OK;
-+		}
-+	break;
-+	case GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT:
-+		if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-+			(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
-+			REG_UPDATE_3(ddc_setup,
-+				DC_I2C_DDC1_ENABLE, 1,
-+				DC_I2C_DDC1_EDID_DETECT_ENABLE, 1,
-+				DC_I2C_DDC1_EDID_DETECT_MODE, 1);
-+			return GPIO_RESULT_OK;
-+		}
-+	break;
-+	case GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING:
-+		if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-+			(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
-+			REG_UPDATE_2(ddc_setup,
-+				DC_I2C_DDC1_ENABLE, 0,
-+				DC_I2C_DDC1_EDID_DETECT_ENABLE, 0);
-+			return GPIO_RESULT_OK;
-+		}
-+	break;
-+	}
-+
-+	BREAK_TO_DEBUGGER();
-+
-+	return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+}
-+
-+static const struct hw_gpio_pin_funcs funcs = {
-+	.destroy = destroy,
-+	.open = dal_hw_gpio_open,
-+	.get_value = dal_hw_gpio_get_value,
-+	.set_value = dal_hw_gpio_set_value,
-+	.set_config = set_config,
-+	.change_mode = dal_hw_gpio_change_mode,
-+	.close = dal_hw_gpio_close,
-+};
-+
-+static void construct(
-+	struct hw_ddc *ddc,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	dal_hw_gpio_construct(&ddc->base, id, en, ctx);
-+	ddc->base.base.funcs = &funcs;
-+}
-+
-+struct hw_gpio_pin *dal_hw_ddc_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	struct hw_ddc *pin;
-+
-+	if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	pin = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL);
-+	if (!pin) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	construct(pin, id, en, ctx);
-+	return &pin->base.base;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h.0130~	2017-12-14 06:39:58.431903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h	2017-12-14 06:39:58.431903579 +0100
-@@ -0,0 +1,46 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_DDC_H__
-+#define __DAL_HW_DDC_H__
-+
-+#include "ddc_regs.h"
-+
-+struct hw_ddc {
-+	struct hw_gpio base;
-+	const struct ddc_registers *regs;
-+	const struct ddc_sh_mask *shifts;
-+	const struct ddc_sh_mask *masks;
-+};
-+
-+#define HW_DDC_FROM_BASE(hw_gpio) \
-+	container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_ddc, base)
-+
-+struct hw_gpio_pin *dal_hw_ddc_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c.0130~	2017-12-14 06:39:58.431903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c	2017-12-14 06:39:58.431903579 +0100
-@@ -0,0 +1,107 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/gpio_types.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "hw_factory.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "dce80/hw_factory_dce80.h"
-+#include "dce110/hw_factory_dce110.h"
-+#include "dce120/hw_factory_dce120.h"
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+#include "dcn10/hw_factory_dcn10.h"
-+#endif
-+
-+#include "diagnostics/hw_factory_diag.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+bool dal_hw_factory_init(
-+	struct hw_factory *factory,
-+	enum dce_version dce_version,
-+	enum dce_environment dce_environment)
-+{
-+	if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
-+		dal_hw_factory_diag_fpga_init(factory);
-+		return true;
-+	}
-+
-+	switch (dce_version) {
-+	case DCE_VERSION_8_0:
-+	case DCE_VERSION_8_1:
-+	case DCE_VERSION_8_3:
-+		dal_hw_factory_dce80_init(factory);
-+		return true;
-+
-+	case DCE_VERSION_10_0:
-+		dal_hw_factory_dce110_init(factory);
-+		return true;
-+	case DCE_VERSION_11_0:
-+	case DCE_VERSION_11_2:
-+		dal_hw_factory_dce110_init(factory);
-+		return true;
-+	case DCE_VERSION_12_0:
-+		dal_hw_factory_dce120_init(factory);
-+		return true;
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	case DCN_VERSION_1_0:
-+		dal_hw_factory_dcn10_init(factory);
-+		return true;
-+#endif
-+
-+	default:
-+		ASSERT_CRITICAL(false);
-+		return false;
-+	}
-+}
-+
-+void dal_hw_factory_destroy(
-+	struct dc_context *ctx,
-+	struct hw_factory **factory)
-+{
-+	if (!factory || !*factory) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	kfree(*factory);
-+
-+	*factory = NULL;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h.0130~	2017-12-14 06:39:58.431903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h	2017-12-14 06:39:58.431903579 +0100
-@@ -0,0 +1,74 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_FACTORY_H__
-+#define __DAL_HW_FACTORY_H__
-+
-+struct hw_gpio_pin;
-+struct hw_hpd;
-+
-+struct hw_factory {
-+	uint32_t number_of_pins[GPIO_ID_COUNT];
-+
-+	const struct hw_factory_funcs {
-+		struct hw_gpio_pin *(*create_ddc_data)(
-+			struct dc_context *ctx,
-+			enum gpio_id id,
-+			uint32_t en);
-+		struct hw_gpio_pin *(*create_ddc_clock)(
-+			struct dc_context *ctx,
-+			enum gpio_id id,
-+			uint32_t en);
-+		struct hw_gpio_pin *(*create_generic)(
-+			struct dc_context *ctx,
-+			enum gpio_id id,
-+			uint32_t en);
-+		struct hw_gpio_pin *(*create_hpd)(
-+			struct dc_context *ctx,
-+			enum gpio_id id,
-+			uint32_t en);
-+		struct hw_gpio_pin *(*create_sync)(
-+			struct dc_context *ctx,
-+			enum gpio_id id,
-+			uint32_t en);
-+		struct hw_gpio_pin *(*create_gsl)(
-+			struct dc_context *ctx,
-+			enum gpio_id id,
-+			uint32_t en);
-+		void (*define_hpd_registers)(
-+				struct hw_gpio_pin *pin,
-+				uint32_t en);
-+		void (*define_ddc_registers)(
-+				struct hw_gpio_pin *pin,
-+				uint32_t en);
-+	} *funcs;
-+};
-+
-+bool dal_hw_factory_init(
-+	struct hw_factory *factory,
-+	enum dce_version dce_version,
-+	enum dce_environment dce_environment);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c.0130~	2017-12-14 06:39:58.431903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c	2017-12-14 06:39:58.431903579 +0100
-@@ -0,0 +1,203 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "include/gpio_types.h"
-+#include "hw_gpio.h"
-+
-+#include "reg_helper.h"
-+#include "gpio_regs.h"
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	gpio->regs->field_name ## _shift, gpio->regs->field_name ## _mask
-+
-+#define CTX \
-+	gpio->base.ctx
-+#define REG(reg)\
-+	(gpio->regs->reg)
-+
-+static void store_registers(
-+	struct hw_gpio *gpio)
-+{
-+	REG_GET(MASK_reg, MASK, &gpio->store.mask);
-+	REG_GET(A_reg, A, &gpio->store.a);
-+	REG_GET(EN_reg, EN, &gpio->store.en);
-+	/* TODO store GPIO_MUX_CONTROL if we ever use it */
-+}
-+
-+static void restore_registers(
-+	struct hw_gpio *gpio)
-+{
-+	REG_UPDATE(MASK_reg, MASK, gpio->store.mask);
-+	REG_UPDATE(A_reg, A, gpio->store.a);
-+	REG_UPDATE(EN_reg, EN, gpio->store.en);
-+	/* TODO restore GPIO_MUX_CONTROL if we ever use it */
-+}
-+
-+bool dal_hw_gpio_open(
-+	struct hw_gpio_pin *ptr,
-+	enum gpio_mode mode)
-+{
-+	struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	store_registers(pin);
-+
-+	ptr->opened = (dal_hw_gpio_config_mode(pin, mode) == GPIO_RESULT_OK);
-+
-+	return ptr->opened;
-+}
-+
-+enum gpio_result dal_hw_gpio_get_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t *value)
-+{
-+	const struct hw_gpio *gpio = FROM_HW_GPIO_PIN(ptr);
-+
-+	enum gpio_result result = GPIO_RESULT_OK;
-+
-+	switch (ptr->mode) {
-+	case GPIO_MODE_INPUT:
-+	case GPIO_MODE_OUTPUT:
-+	case GPIO_MODE_HARDWARE:
-+	case GPIO_MODE_FAST_OUTPUT:
-+		REG_GET(Y_reg, Y, value);
-+		break;
-+	default:
-+		result = GPIO_RESULT_NON_SPECIFIC_ERROR;
-+	}
-+
-+	return result;
-+}
-+
-+enum gpio_result dal_hw_gpio_set_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t value)
-+{
-+	struct hw_gpio *gpio = FROM_HW_GPIO_PIN(ptr);
-+
-+	/* This is the public interface
-+	 * where the input comes from client, not shifted yet
-+	 * (because client does not know the shifts). */
-+
-+	switch (ptr->mode) {
-+	case GPIO_MODE_OUTPUT:
-+		REG_UPDATE(A_reg, A, value);
-+		return GPIO_RESULT_OK;
-+	case GPIO_MODE_FAST_OUTPUT:
-+		/* We use (EN) to faster switch (used in DDC GPIO).
-+		 * So (A) is grounded, output is driven by (EN = 0)
-+		 * to pull the line down (output == 0) and (EN=1)
-+		 * then output is tri-state */
-+		REG_UPDATE(EN_reg, EN, ~value);
-+		return GPIO_RESULT_OK;
-+	default:
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+	}
-+}
-+
-+enum gpio_result dal_hw_gpio_change_mode(
-+	struct hw_gpio_pin *ptr,
-+	enum gpio_mode mode)
-+{
-+	struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	return dal_hw_gpio_config_mode(pin, mode);
-+}
-+
-+void dal_hw_gpio_close(
-+	struct hw_gpio_pin *ptr)
-+{
-+	struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr);
-+
-+	restore_registers(pin);
-+
-+	ptr->mode = GPIO_MODE_UNKNOWN;
-+	ptr->opened = false;
-+}
-+
-+enum gpio_result dal_hw_gpio_config_mode(
-+	struct hw_gpio *gpio,
-+	enum gpio_mode mode)
-+{
-+	gpio->base.mode = mode;
-+
-+	switch (mode) {
-+	case GPIO_MODE_INPUT:
-+		/* turn off output enable, act as input pin;
-+		 * program the pin as GPIO, mask out signal driven by HW */
-+		REG_UPDATE(EN_reg, EN, 0);
-+		REG_UPDATE(MASK_reg, MASK, 1);
-+		return GPIO_RESULT_OK;
-+	case GPIO_MODE_OUTPUT:
-+		/* turn on output enable, act as output pin;
-+		 * program the pin as GPIO, mask out signal driven by HW */
-+		REG_UPDATE(A_reg, A, 0);
-+		REG_UPDATE(MASK_reg, MASK, 1);
-+		return GPIO_RESULT_OK;
-+	case GPIO_MODE_FAST_OUTPUT:
-+		/* grounding the A register then use the EN register bit
-+		 * will have faster effect on the rise time */
-+		REG_UPDATE(A_reg, A, 0);
-+		REG_UPDATE(MASK_reg, MASK, 1);
-+		return GPIO_RESULT_OK;
-+	case GPIO_MODE_HARDWARE:
-+		/* program the pin as tri-state, pin is driven by HW */
-+		REG_UPDATE(MASK_reg, MASK, 0);
-+		return GPIO_RESULT_OK;
-+	case GPIO_MODE_INTERRUPT:
-+		/* Interrupt mode supported only by HPD (IrqGpio) pins. */
-+		REG_UPDATE(MASK_reg, MASK, 0);
-+		return GPIO_RESULT_OK;
-+	default:
-+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
-+	}
-+}
-+
-+void dal_hw_gpio_construct(
-+	struct hw_gpio *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	pin->base.ctx = ctx;
-+	pin->base.id = id;
-+	pin->base.en = en;
-+	pin->base.mode = GPIO_MODE_UNKNOWN;
-+	pin->base.opened = false;
-+
-+	pin->store.mask = 0;
-+	pin->store.a = 0;
-+	pin->store.en = 0;
-+	pin->store.mux = 0;
-+
-+	pin->mux_supported = false;
-+}
-+
-+void dal_hw_gpio_destruct(
-+	struct hw_gpio *pin)
-+{
-+	ASSERT(!pin->base.opened);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h.0130~	2017-12-14 06:39:58.431903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h	2017-12-14 06:39:58.431903579 +0100
-@@ -0,0 +1,144 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_GPIO_H__
-+#define __DAL_HW_GPIO_H__
-+
-+#include "gpio_regs.h"
-+
-+#define FROM_HW_GPIO_PIN(ptr) \
-+	container_of((ptr), struct hw_gpio, base)
-+
-+struct addr_mask {
-+	uint32_t addr;
-+	uint32_t mask;
-+};
-+
-+struct hw_gpio_pin {
-+	const struct hw_gpio_pin_funcs *funcs;
-+	enum gpio_id id;
-+	uint32_t en;
-+	enum gpio_mode mode;
-+	bool opened;
-+	struct dc_context *ctx;
-+};
-+
-+struct hw_gpio_pin_funcs {
-+	void (*destroy)(
-+		struct hw_gpio_pin **ptr);
-+	bool (*open)(
-+		struct hw_gpio_pin *pin,
-+		enum gpio_mode mode);
-+	enum gpio_result (*get_value)(
-+		const struct hw_gpio_pin *pin,
-+		uint32_t *value);
-+	enum gpio_result (*set_value)(
-+		const struct hw_gpio_pin *pin,
-+		uint32_t value);
-+	enum gpio_result (*set_config)(
-+		struct hw_gpio_pin *pin,
-+		const struct gpio_config_data *config_data);
-+	enum gpio_result (*change_mode)(
-+		struct hw_gpio_pin *pin,
-+		enum gpio_mode mode);
-+	void (*close)(
-+		struct hw_gpio_pin *pin);
-+};
-+
-+
-+struct hw_gpio;
-+
-+/* Register indices are represented by member variables
-+ * and are to be filled in by constructors of derived classes.
-+ * These members permit the use of common code
-+ * for programming registers, where the sequence is the same
-+ * but register sets are different.
-+ * Some GPIOs have HW mux which allows to choose
-+ * what is the source of the signal in HW mode */
-+
-+struct hw_gpio_pin_reg {
-+	struct addr_mask DC_GPIO_DATA_MASK;
-+	struct addr_mask DC_GPIO_DATA_A;
-+	struct addr_mask DC_GPIO_DATA_EN;
-+	struct addr_mask DC_GPIO_DATA_Y;
-+};
-+
-+struct hw_gpio_mux_reg {
-+	struct addr_mask GPIO_MUX_CONTROL;
-+	struct addr_mask GPIO_MUX_STEREO_SEL;
-+};
-+
-+struct hw_gpio {
-+	struct hw_gpio_pin base;
-+
-+	/* variables to save register value */
-+	struct {
-+		uint32_t mask;
-+		uint32_t a;
-+		uint32_t en;
-+		uint32_t mux;
-+	} store;
-+
-+	/* GPIO MUX support */
-+	bool mux_supported;
-+	const struct gpio_registers *regs;
-+};
-+
-+#define HW_GPIO_FROM_BASE(hw_gpio_pin) \
-+	container_of((hw_gpio_pin), struct hw_gpio, base)
-+
-+void dal_hw_gpio_construct(
-+	struct hw_gpio *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx);
-+
-+bool dal_hw_gpio_open(
-+	struct hw_gpio_pin *pin,
-+	enum gpio_mode mode);
-+
-+enum gpio_result dal_hw_gpio_get_value(
-+	const struct hw_gpio_pin *pin,
-+	uint32_t *value);
-+
-+enum gpio_result dal_hw_gpio_config_mode(
-+	struct hw_gpio *pin,
-+	enum gpio_mode mode);
-+
-+void dal_hw_gpio_destruct(
-+	struct hw_gpio *pin);
-+
-+enum gpio_result dal_hw_gpio_set_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t value);
-+
-+enum gpio_result dal_hw_gpio_change_mode(
-+	struct hw_gpio_pin *ptr,
-+	enum gpio_mode mode);
-+
-+void dal_hw_gpio_close(
-+	struct hw_gpio_pin *ptr);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c.0130~	2017-12-14 06:39:58.431903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c	2017-12-14 06:39:58.431903579 +0100
-@@ -0,0 +1,162 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/gpio_types.h"
-+#include "hw_gpio.h"
-+#include "hw_hpd.h"
-+
-+#include "reg_helper.h"
-+#include "hpd_regs.h"
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	hpd->shifts->field_name, hpd->masks->field_name
-+
-+#define CTX \
-+	hpd->base.base.ctx
-+#define REG(reg)\
-+	(hpd->regs->reg)
-+
-+static void dal_hw_hpd_construct(
-+	struct hw_hpd *pin,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	dal_hw_gpio_construct(&pin->base, id, en, ctx);
-+}
-+
-+static void dal_hw_hpd_destruct(
-+	struct hw_hpd *pin)
-+{
-+	dal_hw_gpio_destruct(&pin->base);
-+}
-+
-+
-+static void destruct(
-+	struct hw_hpd *hpd)
-+{
-+	dal_hw_hpd_destruct(hpd);
-+}
-+
-+static void destroy(
-+	struct hw_gpio_pin **ptr)
-+{
-+	struct hw_hpd *hpd = HW_HPD_FROM_BASE(*ptr);
-+
-+	destruct(hpd);
-+
-+	kfree(hpd);
-+
-+	*ptr = NULL;
-+}
-+
-+static enum gpio_result get_value(
-+	const struct hw_gpio_pin *ptr,
-+	uint32_t *value)
-+{
-+	struct hw_hpd *hpd = HW_HPD_FROM_BASE(ptr);
-+	uint32_t hpd_delayed = 0;
-+
-+	/* in Interrupt mode we ask for SENSE bit */
-+
-+	if (ptr->mode == GPIO_MODE_INTERRUPT) {
-+
-+		REG_GET(int_status,
-+			DC_HPD_SENSE_DELAYED, &hpd_delayed);
-+
-+		*value = hpd_delayed;
-+		return GPIO_RESULT_OK;
-+	}
-+
-+	/* in any other modes, operate as normal GPIO */
-+
-+	return dal_hw_gpio_get_value(ptr, value);
-+}
-+
-+static enum gpio_result set_config(
-+	struct hw_gpio_pin *ptr,
-+	const struct gpio_config_data *config_data)
-+{
-+	struct hw_hpd *hpd = HW_HPD_FROM_BASE(ptr);
-+
-+	if (!config_data)
-+		return GPIO_RESULT_INVALID_DATA;
-+
-+	REG_UPDATE_2(toggle_filt_cntl,
-+		DC_HPD_CONNECT_INT_DELAY, config_data->config.hpd.delay_on_connect / 10,
-+		DC_HPD_DISCONNECT_INT_DELAY, config_data->config.hpd.delay_on_disconnect / 10);
-+
-+	return GPIO_RESULT_OK;
-+}
-+
-+static const struct hw_gpio_pin_funcs funcs = {
-+	.destroy = destroy,
-+	.open = dal_hw_gpio_open,
-+	.get_value = get_value,
-+	.set_value = dal_hw_gpio_set_value,
-+	.set_config = set_config,
-+	.change_mode = dal_hw_gpio_change_mode,
-+	.close = dal_hw_gpio_close,
-+};
-+
-+static void construct(
-+	struct hw_hpd *hpd,
-+	enum gpio_id id,
-+	uint32_t en,
-+	struct dc_context *ctx)
-+{
-+	dal_hw_hpd_construct(hpd, id, en, ctx);
-+	hpd->base.base.funcs = &funcs;
-+}
-+
-+struct hw_gpio_pin *dal_hw_hpd_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en)
-+{
-+	struct hw_hpd *hpd;
-+
-+	if (id != GPIO_ID_HPD) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	if ((en < GPIO_HPD_MIN) || (en > GPIO_HPD_MAX)) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	hpd = kzalloc(sizeof(struct hw_hpd), GFP_KERNEL);
-+	if (!hpd) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	construct(hpd, id, en, ctx);
-+	return &hpd->base.base;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h.0130~	2017-12-14 06:39:58.431903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h	2017-12-14 06:39:58.431903579 +0100
-@@ -0,0 +1,46 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_HPD_H__
-+#define __DAL_HW_HPD_H__
-+
-+#include "hpd_regs.h"
-+
-+struct hw_hpd {
-+	struct hw_gpio base;
-+	const struct hpd_registers *regs;
-+	const struct hpd_sh_mask *shifts;
-+	const struct hpd_sh_mask *masks;
-+};
-+
-+#define HW_HPD_FROM_BASE(hw_gpio) \
-+	container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_hpd, base)
-+
-+struct hw_gpio_pin *dal_hw_hpd_create(
-+	struct dc_context *ctx,
-+	enum gpio_id id,
-+	uint32_t en);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c.0130~	2017-12-14 06:39:58.432903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c	2017-12-14 06:39:58.432903579 +0100
-@@ -0,0 +1,90 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/gpio_types.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "hw_translate.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "dce80/hw_translate_dce80.h"
-+#include "dce110/hw_translate_dce110.h"
-+#include "dce120/hw_translate_dce120.h"
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+#include "dcn10/hw_translate_dcn10.h"
-+#endif
-+
-+#include "diagnostics/hw_translate_diag.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+bool dal_hw_translate_init(
-+	struct hw_translate *translate,
-+	enum dce_version dce_version,
-+	enum dce_environment dce_environment)
-+{
-+	if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
-+		dal_hw_translate_diag_fpga_init(translate);
-+		return true;
-+	}
-+
-+	switch (dce_version) {
-+	case DCE_VERSION_8_0:
-+	case DCE_VERSION_8_1:
-+	case DCE_VERSION_8_3:
-+		dal_hw_translate_dce80_init(translate);
-+		return true;
-+	case DCE_VERSION_10_0:
-+	case DCE_VERSION_11_0:
-+	case DCE_VERSION_11_2:
-+		dal_hw_translate_dce110_init(translate);
-+		return true;
-+	case DCE_VERSION_12_0:
-+		dal_hw_translate_dce120_init(translate);
-+		return true;
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	case DCN_VERSION_1_0:
-+		dal_hw_translate_dcn10_init(translate);
-+		return true;
-+#endif
-+
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.h.0130~	2017-12-14 06:39:58.432903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.h	2017-12-14 06:39:58.432903579 +0100
-@@ -0,0 +1,50 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_TRANSLATE_H__
-+#define __DAL_HW_TRANSLATE_H__
-+
-+struct hw_translate_funcs {
-+	bool (*offset_to_id)(
-+		uint32_t offset,
-+		uint32_t mask,
-+		enum gpio_id *id,
-+		uint32_t *en);
-+	bool (*id_to_offset)(
-+		enum gpio_id id,
-+		uint32_t en,
-+		struct gpio_pin_info *info);
-+};
-+
-+struct hw_translate {
-+	const struct hw_translate_funcs *funcs;
-+};
-+
-+bool dal_hw_translate_init(
-+	struct hw_translate *translate,
-+	enum dce_version dce_version,
-+	enum dce_environment dce_environment);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/Makefile.0130~	2017-12-14 06:39:58.432903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/gpio/Makefile	2017-12-14 06:39:58.432903579 +0100
-@@ -0,0 +1,58 @@
-+#
-+# Makefile for the 'gpio' sub-component of DAL.
-+# It provides the control and status of HW GPIO pins.
-+
-+GPIO = gpio_base.o gpio_service.o hw_factory.o \
-+       hw_gpio.o hw_hpd.o hw_ddc.o hw_translate.o
-+
-+AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO)
-+
-+###############################################################################
-+# DCE 8x
-+###############################################################################
-+# all DCE8.x are derived from DCE8.0
-+GPIO_DCE80 = hw_translate_dce80.o hw_factory_dce80.o
-+	
-+AMD_DAL_GPIO_DCE80 = $(addprefix $(AMDDALPATH)/dc/gpio/dce80/,$(GPIO_DCE80))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE80)
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+GPIO_DCE110 = hw_translate_dce110.o hw_factory_dce110.o
-+
-+AMD_DAL_GPIO_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpio/dce110/,$(GPIO_DCE110))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE110)
-+
-+###############################################################################
-+# DCE 12x
-+###############################################################################
-+GPIO_DCE120 = hw_translate_dce120.o hw_factory_dce120.o
-+
-+AMD_DAL_GPIO_DCE120 = $(addprefix $(AMDDALPATH)/dc/gpio/dce120/,$(GPIO_DCE120))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120)
-+
-+###############################################################################
-+# DCN 1x
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DC_DCN1_0
-+GPIO_DCN10 = hw_translate_dcn10.o hw_factory_dcn10.o
-+
-+AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN10)
-+endif
-+
-+###############################################################################
-+# Diagnostics on FPGA
-+###############################################################################
-+GPIO_DIAG_FPGA = hw_translate_diag.o hw_factory_diag.o
-+
-+AMD_DAL_GPIO_DIAG_FPGA = $(addprefix $(AMDDALPATH)/dc/gpio/diagnostics/,$(GPIO_DIAG_FPGA))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DIAG_FPGA)
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c.0130~	2017-12-14 06:39:58.432903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c	2017-12-14 06:39:58.432903579 +0100
-@@ -0,0 +1,571 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "aux_engine.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "include/link_service_types.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+enum {
-+	AUX_INVALID_REPLY_RETRY_COUNTER = 1,
-+	AUX_TIMED_OUT_RETRY_COUNTER = 2,
-+	AUX_DEFER_RETRY_COUNTER = 6
-+};
-+
-+#define FROM_ENGINE(ptr) \
-+	container_of((ptr), struct aux_engine, base)
-+
-+enum i2caux_engine_type dal_aux_engine_get_engine_type(
-+	const struct engine *engine)
-+{
-+	return I2CAUX_ENGINE_TYPE_AUX;
-+}
-+
-+bool dal_aux_engine_acquire(
-+	struct engine *engine,
-+	struct ddc *ddc)
-+{
-+	struct aux_engine *aux_engine = FROM_ENGINE(engine);
-+
-+	enum gpio_result result;
-+	if (aux_engine->funcs->is_engine_available) {
-+		/*check whether SW could use the engine*/
-+		if (!aux_engine->funcs->is_engine_available(aux_engine)) {
-+			return false;
-+		}
-+	}
-+
-+	result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
-+		GPIO_DDC_CONFIG_TYPE_MODE_AUX);
-+
-+	if (result != GPIO_RESULT_OK)
-+		return false;
-+
-+	if (!aux_engine->funcs->acquire_engine(aux_engine)) {
-+		dal_ddc_close(ddc);
-+		return false;
-+	}
-+
-+	engine->ddc = ddc;
-+
-+	return true;
-+}
-+
-+struct read_command_context {
-+	uint8_t *buffer;
-+	uint32_t current_read_length;
-+	uint32_t offset;
-+	enum i2caux_transaction_status status;
-+
-+	struct aux_request_transaction_data request;
-+	struct aux_reply_transaction_data reply;
-+
-+	uint8_t returned_byte;
-+
-+	uint32_t timed_out_retry_aux;
-+	uint32_t invalid_reply_retry_aux;
-+	uint32_t defer_retry_aux;
-+	uint32_t defer_retry_i2c;
-+	uint32_t invalid_reply_retry_aux_on_ack;
-+
-+	bool transaction_complete;
-+	bool operation_succeeded;
-+};
-+
-+static void process_read_reply(
-+	struct aux_engine *engine,
-+	struct read_command_context *ctx)
-+{
-+	engine->funcs->process_channel_reply(engine, &ctx->reply);
-+
-+	switch (ctx->reply.status) {
-+	case AUX_TRANSACTION_REPLY_AUX_ACK:
-+		ctx->defer_retry_aux = 0;
-+		if (ctx->returned_byte > ctx->current_read_length) {
-+			ctx->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-+			ctx->operation_succeeded = false;
-+		} else if (ctx->returned_byte < ctx->current_read_length) {
-+			ctx->current_read_length -= ctx->returned_byte;
-+
-+			ctx->offset += ctx->returned_byte;
-+
-+			++ctx->invalid_reply_retry_aux_on_ack;
-+
-+			if (ctx->invalid_reply_retry_aux_on_ack >
-+				AUX_INVALID_REPLY_RETRY_COUNTER) {
-+				ctx->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-+				ctx->operation_succeeded = false;
-+			}
-+		} else {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-+			ctx->transaction_complete = true;
-+			ctx->operation_succeeded = true;
-+		}
-+	break;
-+	case AUX_TRANSACTION_REPLY_AUX_NACK:
-+		ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-+		ctx->operation_succeeded = false;
-+	break;
-+	case AUX_TRANSACTION_REPLY_AUX_DEFER:
-+		++ctx->defer_retry_aux;
-+
-+		if (ctx->defer_retry_aux > AUX_DEFER_RETRY_COUNTER) {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+			ctx->operation_succeeded = false;
-+		}
-+	break;
-+	case AUX_TRANSACTION_REPLY_I2C_DEFER:
-+		ctx->defer_retry_aux = 0;
-+
-+		++ctx->defer_retry_i2c;
-+
-+		if (ctx->defer_retry_i2c > AUX_DEFER_RETRY_COUNTER) {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+			ctx->operation_succeeded = false;
-+		}
-+	break;
-+	default:
-+		ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-+		ctx->operation_succeeded = false;
-+	}
-+}
-+
-+static void process_read_request(
-+	struct aux_engine *engine,
-+	struct read_command_context *ctx)
-+{
-+	enum aux_channel_operation_result operation_result;
-+
-+	engine->funcs->submit_channel_request(engine, &ctx->request);
-+
-+	operation_result = engine->funcs->get_channel_status(
-+		engine, &ctx->returned_byte);
-+
-+	switch (operation_result) {
-+	case AUX_CHANNEL_OPERATION_SUCCEEDED:
-+		if (ctx->returned_byte > ctx->current_read_length) {
-+			ctx->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-+			ctx->operation_succeeded = false;
-+		} else {
-+			ctx->timed_out_retry_aux = 0;
-+			ctx->invalid_reply_retry_aux = 0;
-+
-+			ctx->reply.length = ctx->returned_byte;
-+			ctx->reply.data = ctx->buffer;
-+
-+			process_read_reply(engine, ctx);
-+		}
-+	break;
-+	case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
-+		++ctx->invalid_reply_retry_aux;
-+
-+		if (ctx->invalid_reply_retry_aux >
-+			AUX_INVALID_REPLY_RETRY_COUNTER) {
-+			ctx->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-+			ctx->operation_succeeded = false;
-+		} else
-+			udelay(400);
-+	break;
-+	case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
-+		++ctx->timed_out_retry_aux;
-+
-+		if (ctx->timed_out_retry_aux > AUX_TIMED_OUT_RETRY_COUNTER) {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+			ctx->operation_succeeded = false;
-+		} else {
-+			/* DP 1.2a, table 2-58:
-+			 * "S3: AUX Request CMD PENDING:
-+			 * retry 3 times, with 400usec wait on each"
-+			 * The HW timeout is set to 550usec,
-+			 * so we should not wait here */
-+		}
-+	break;
-+	default:
-+		ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-+		ctx->operation_succeeded = false;
-+	}
-+}
-+
-+static bool read_command(
-+	struct aux_engine *engine,
-+	struct i2caux_transaction_request *request,
-+	bool middle_of_transaction)
-+{
-+	struct read_command_context ctx;
-+
-+	ctx.buffer = request->payload.data;
-+	ctx.current_read_length = request->payload.length;
-+	ctx.offset = 0;
-+	ctx.timed_out_retry_aux = 0;
-+	ctx.invalid_reply_retry_aux = 0;
-+	ctx.defer_retry_aux = 0;
-+	ctx.defer_retry_i2c = 0;
-+	ctx.invalid_reply_retry_aux_on_ack = 0;
-+	ctx.transaction_complete = false;
-+	ctx.operation_succeeded = true;
-+
-+	if (request->payload.address_space ==
-+		I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
-+		ctx.request.type = AUX_TRANSACTION_TYPE_DP;
-+		ctx.request.action = I2CAUX_TRANSACTION_ACTION_DP_READ;
-+		ctx.request.address = request->payload.address;
-+	} else if (request->payload.address_space ==
-+		I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C) {
-+		ctx.request.type = AUX_TRANSACTION_TYPE_I2C;
-+		ctx.request.action = middle_of_transaction ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_READ;
-+		ctx.request.address = request->payload.address >> 1;
-+	} else {
-+		/* in DAL2, there was no return in such case */
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	ctx.request.delay = 0;
-+
-+	do {
-+		memset(ctx.buffer + ctx.offset, 0, ctx.current_read_length);
-+
-+		ctx.request.data = ctx.buffer + ctx.offset;
-+		ctx.request.length = ctx.current_read_length;
-+
-+		process_read_request(engine, &ctx);
-+
-+		request->status = ctx.status;
-+
-+		if (ctx.operation_succeeded && !ctx.transaction_complete)
-+			if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
-+				msleep(engine->delay);
-+	} while (ctx.operation_succeeded && !ctx.transaction_complete);
-+
-+	return ctx.operation_succeeded;
-+}
-+
-+struct write_command_context {
-+	bool mot;
-+
-+	uint8_t *buffer;
-+	uint32_t current_write_length;
-+	enum i2caux_transaction_status status;
-+
-+	struct aux_request_transaction_data request;
-+	struct aux_reply_transaction_data reply;
-+
-+	uint8_t returned_byte;
-+
-+	uint32_t timed_out_retry_aux;
-+	uint32_t invalid_reply_retry_aux;
-+	uint32_t defer_retry_aux;
-+	uint32_t defer_retry_i2c;
-+	uint32_t max_defer_retry;
-+	uint32_t ack_m_retry;
-+
-+	uint8_t reply_data[DEFAULT_AUX_MAX_DATA_SIZE];
-+
-+	bool transaction_complete;
-+	bool operation_succeeded;
-+};
-+
-+static void process_write_reply(
-+	struct aux_engine *engine,
-+	struct write_command_context *ctx)
-+{
-+	engine->funcs->process_channel_reply(engine, &ctx->reply);
-+
-+	switch (ctx->reply.status) {
-+	case AUX_TRANSACTION_REPLY_AUX_ACK:
-+		ctx->operation_succeeded = true;
-+
-+		if (ctx->returned_byte) {
-+			ctx->request.action = ctx->mot ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST;
-+
-+			ctx->current_write_length = 0;
-+
-+			++ctx->ack_m_retry;
-+
-+			if (ctx->ack_m_retry > AUX_DEFER_RETRY_COUNTER) {
-+				ctx->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+				ctx->operation_succeeded = false;
-+			} else
-+				udelay(300);
-+		} else {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-+			ctx->defer_retry_aux = 0;
-+			ctx->ack_m_retry = 0;
-+			ctx->transaction_complete = true;
-+		}
-+	break;
-+	case AUX_TRANSACTION_REPLY_AUX_NACK:
-+		ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-+		ctx->operation_succeeded = false;
-+	break;
-+	case AUX_TRANSACTION_REPLY_AUX_DEFER:
-+		++ctx->defer_retry_aux;
-+
-+		if (ctx->defer_retry_aux > ctx->max_defer_retry) {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+			ctx->operation_succeeded = false;
-+		}
-+	break;
-+	case AUX_TRANSACTION_REPLY_I2C_DEFER:
-+		ctx->defer_retry_aux = 0;
-+		ctx->current_write_length = 0;
-+
-+		ctx->request.action = ctx->mot ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST;
-+
-+		++ctx->defer_retry_i2c;
-+
-+		if (ctx->defer_retry_i2c > ctx->max_defer_retry) {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+			ctx->operation_succeeded = false;
-+		}
-+	break;
-+	default:
-+		ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-+		ctx->operation_succeeded = false;
-+	}
-+}
-+
-+static void process_write_request(
-+	struct aux_engine *engine,
-+	struct write_command_context *ctx)
-+{
-+	enum aux_channel_operation_result operation_result;
-+
-+	engine->funcs->submit_channel_request(engine, &ctx->request);
-+
-+	operation_result = engine->funcs->get_channel_status(
-+		engine, &ctx->returned_byte);
-+
-+	switch (operation_result) {
-+	case AUX_CHANNEL_OPERATION_SUCCEEDED:
-+		ctx->timed_out_retry_aux = 0;
-+		ctx->invalid_reply_retry_aux = 0;
-+
-+		ctx->reply.length = ctx->returned_byte;
-+		ctx->reply.data = ctx->reply_data;
-+
-+		process_write_reply(engine, ctx);
-+	break;
-+	case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
-+		++ctx->invalid_reply_retry_aux;
-+
-+		if (ctx->invalid_reply_retry_aux >
-+			AUX_INVALID_REPLY_RETRY_COUNTER) {
-+			ctx->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-+			ctx->operation_succeeded = false;
-+		} else
-+			udelay(400);
-+	break;
-+	case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
-+		++ctx->timed_out_retry_aux;
-+
-+		if (ctx->timed_out_retry_aux > AUX_TIMED_OUT_RETRY_COUNTER) {
-+			ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+			ctx->operation_succeeded = false;
-+		} else {
-+			/* DP 1.2a, table 2-58:
-+			 * "S3: AUX Request CMD PENDING:
-+			 * retry 3 times, with 400usec wait on each"
-+			 * The HW timeout is set to 550usec,
-+			 * so we should not wait here */
-+		}
-+	break;
-+	default:
-+		ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-+		ctx->operation_succeeded = false;
-+	}
-+}
-+
-+static bool write_command(
-+	struct aux_engine *engine,
-+	struct i2caux_transaction_request *request,
-+	bool middle_of_transaction)
-+{
-+	struct write_command_context ctx;
-+
-+	ctx.mot = middle_of_transaction;
-+	ctx.buffer = request->payload.data;
-+	ctx.current_write_length = request->payload.length;
-+	ctx.timed_out_retry_aux = 0;
-+	ctx.invalid_reply_retry_aux = 0;
-+	ctx.defer_retry_aux = 0;
-+	ctx.defer_retry_i2c = 0;
-+	ctx.ack_m_retry = 0;
-+	ctx.transaction_complete = false;
-+	ctx.operation_succeeded = true;
-+
-+	if (request->payload.address_space ==
-+		I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
-+		ctx.request.type = AUX_TRANSACTION_TYPE_DP;
-+		ctx.request.action = I2CAUX_TRANSACTION_ACTION_DP_WRITE;
-+		ctx.request.address = request->payload.address;
-+	} else if (request->payload.address_space ==
-+		I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C) {
-+		ctx.request.type = AUX_TRANSACTION_TYPE_I2C;
-+		ctx.request.action = middle_of_transaction ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
-+		ctx.request.address = request->payload.address >> 1;
-+	} else {
-+		/* in DAL2, there was no return in such case */
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	ctx.request.delay = 0;
-+
-+	ctx.max_defer_retry =
-+		(engine->max_defer_write_retry > AUX_DEFER_RETRY_COUNTER) ?
-+			engine->max_defer_write_retry : AUX_DEFER_RETRY_COUNTER;
-+
-+	do {
-+		ctx.request.data = ctx.buffer;
-+		ctx.request.length = ctx.current_write_length;
-+
-+		process_write_request(engine, &ctx);
-+
-+		request->status = ctx.status;
-+
-+		if (ctx.operation_succeeded && !ctx.transaction_complete)
-+			if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
-+				msleep(engine->delay);
-+	} while (ctx.operation_succeeded && !ctx.transaction_complete);
-+
-+	return ctx.operation_succeeded;
-+}
-+
-+static bool end_of_transaction_command(
-+	struct aux_engine *engine,
-+	struct i2caux_transaction_request *request)
-+{
-+	struct i2caux_transaction_request dummy_request;
-+	uint8_t dummy_data;
-+
-+	/* [tcheng] We only need to send the stop (read with MOT = 0)
-+	 * for I2C-over-Aux, not native AUX */
-+
-+	if (request->payload.address_space !=
-+		I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C)
-+		return false;
-+
-+	dummy_request.operation = request->operation;
-+	dummy_request.payload.address_space = request->payload.address_space;
-+	dummy_request.payload.address = request->payload.address;
-+
-+	/*
-+	 * Add a dummy byte due to some receiver quirk
-+	 * where one byte is sent along with MOT = 0.
-+	 * Ideally this should be 0.
-+	 */
-+
-+	dummy_request.payload.length = 0;
-+	dummy_request.payload.data = &dummy_data;
-+
-+	if (request->operation == I2CAUX_TRANSACTION_READ)
-+		return read_command(engine, &dummy_request, false);
-+	else
-+		return write_command(engine, &dummy_request, false);
-+
-+	/* according Syed, it does not need now DoDummyMOT */
-+}
-+
-+bool dal_aux_engine_submit_request(
-+	struct engine *engine,
-+	struct i2caux_transaction_request *request,
-+	bool middle_of_transaction)
-+{
-+	struct aux_engine *aux_engine = FROM_ENGINE(engine);
-+
-+	bool result;
-+	bool mot_used = true;
-+
-+	switch (request->operation) {
-+	case I2CAUX_TRANSACTION_READ:
-+		result = read_command(aux_engine, request, mot_used);
-+	break;
-+	case I2CAUX_TRANSACTION_WRITE:
-+		result = write_command(aux_engine, request, mot_used);
-+	break;
-+	default:
-+		result = false;
-+	}
-+
-+	/* [tcheng]
-+	 * need to send stop for the last transaction to free up the AUX
-+	 * if the above command fails, this would be the last transaction */
-+
-+	if (!middle_of_transaction || !result)
-+		end_of_transaction_command(aux_engine, request);
-+
-+	/* mask AUX interrupt */
-+
-+	return result;
-+}
-+
-+void dal_aux_engine_construct(
-+	struct aux_engine *engine,
-+	struct dc_context *ctx)
-+{
-+	dal_i2caux_construct_engine(&engine->base, ctx);
-+	engine->delay = 0;
-+	engine->max_defer_write_retry = 0;
-+}
-+
-+void dal_aux_engine_destruct(
-+	struct aux_engine *engine)
-+{
-+	dal_i2caux_destruct_engine(&engine->base);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h.0130~	2017-12-14 06:39:58.432903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h	2017-12-14 06:39:58.432903579 +0100
-@@ -0,0 +1,119 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_AUX_ENGINE_H__
-+#define __DAL_AUX_ENGINE_H__
-+
-+enum aux_transaction_type {
-+	AUX_TRANSACTION_TYPE_DP,
-+	AUX_TRANSACTION_TYPE_I2C
-+};
-+
-+struct aux_request_transaction_data {
-+	enum aux_transaction_type type;
-+	enum i2caux_transaction_action action;
-+	/* 20-bit AUX channel transaction address */
-+	uint32_t address;
-+	/* delay, in 100-microsecond units */
-+	uint8_t delay;
-+	uint32_t length;
-+	uint8_t *data;
-+};
-+
-+enum aux_transaction_reply {
-+	AUX_TRANSACTION_REPLY_AUX_ACK = 0x00,
-+	AUX_TRANSACTION_REPLY_AUX_NACK = 0x01,
-+	AUX_TRANSACTION_REPLY_AUX_DEFER = 0x02,
-+
-+	AUX_TRANSACTION_REPLY_I2C_ACK = 0x00,
-+	AUX_TRANSACTION_REPLY_I2C_NACK = 0x10,
-+	AUX_TRANSACTION_REPLY_I2C_DEFER = 0x20,
-+
-+	AUX_TRANSACTION_REPLY_INVALID = 0xFF
-+};
-+
-+struct aux_reply_transaction_data {
-+	enum aux_transaction_reply status;
-+	uint32_t length;
-+	uint8_t *data;
-+};
-+
-+enum aux_channel_operation_result {
-+	AUX_CHANNEL_OPERATION_SUCCEEDED,
-+	AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN,
-+	AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY,
-+	AUX_CHANNEL_OPERATION_FAILED_TIMEOUT
-+};
-+
-+struct aux_engine;
-+
-+struct aux_engine_funcs {
-+	void (*destroy)(
-+		struct aux_engine **ptr);
-+	bool (*acquire_engine)(
-+		struct aux_engine *engine);
-+	void (*configure)(
-+		struct aux_engine *engine,
-+		union aux_config cfg);
-+	void (*submit_channel_request)(
-+		struct aux_engine *engine,
-+		struct aux_request_transaction_data *request);
-+	void (*process_channel_reply)(
-+		struct aux_engine *engine,
-+		struct aux_reply_transaction_data *reply);
-+	enum aux_channel_operation_result (*get_channel_status)(
-+		struct aux_engine *engine,
-+		uint8_t *returned_bytes);
-+	bool (*is_engine_available) (
-+		struct aux_engine *engine);
-+};
-+
-+struct aux_engine {
-+	struct engine base;
-+	const struct aux_engine_funcs *funcs;
-+	/* following values are expressed in milliseconds */
-+	uint32_t delay;
-+	uint32_t max_defer_write_retry;
-+
-+	bool acquire_reset;
-+};
-+
-+void dal_aux_engine_construct(
-+	struct aux_engine *engine,
-+	struct dc_context *ctx);
-+
-+void dal_aux_engine_destruct(
-+	struct aux_engine *engine);
-+bool dal_aux_engine_submit_request(
-+	struct engine *ptr,
-+	struct i2caux_transaction_request *request,
-+	bool middle_of_transaction);
-+bool dal_aux_engine_acquire(
-+	struct engine *ptr,
-+	struct ddc *ddc);
-+enum i2caux_engine_type dal_aux_engine_get_engine_type(
-+	const struct engine *engine);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c.0130~	2017-12-14 06:39:58.432903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c	2017-12-14 06:39:58.432903579 +0100
-@@ -0,0 +1,105 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/i2caux_interface.h"
-+#include "../i2caux.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_sw_engine.h"
-+#include "../i2c_hw_engine.h"
-+
-+#include "../dce110/aux_engine_dce110.h"
-+#include "../dce110/i2c_hw_engine_dce110.h"
-+#include "../dce110/i2caux_dce110.h"
-+
-+#include "dce/dce_10_0_d.h"
-+#include "dce/dce_10_0_sh_mask.h"
-+
-+/* set register offset */
-+#define SR(reg_name)\
-+	.reg_name = mm ## reg_name
-+
-+/* set register offset with instance */
-+#define SRI(reg_name, block, id)\
-+	.reg_name = mm ## block ## id ## _ ## reg_name
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	AUX_COMMON_REG_LIST(id), \
-+	.AUX_RESET_MASK = 0 \
-+}
-+
-+#define hw_engine_regs(id)\
-+{\
-+		I2C_HW_ENGINE_COMMON_REG_LIST(id) \
-+}
-+
-+static const struct dce110_aux_registers dce100_aux_regs[] = {
-+		aux_regs(0),
-+		aux_regs(1),
-+		aux_regs(2),
-+		aux_regs(3),
-+		aux_regs(4),
-+		aux_regs(5),
-+};
-+
-+static const struct dce110_i2c_hw_engine_registers dce100_hw_engine_regs[] = {
-+		hw_engine_regs(1),
-+		hw_engine_regs(2),
-+		hw_engine_regs(3),
-+		hw_engine_regs(4),
-+		hw_engine_regs(5),
-+		hw_engine_regs(6)
-+};
-+
-+static const struct dce110_i2c_hw_engine_shift i2c_shift = {
-+		I2C_COMMON_MASK_SH_LIST_DCE100(__SHIFT)
-+};
-+
-+static const struct dce110_i2c_hw_engine_mask i2c_mask = {
-+		I2C_COMMON_MASK_SH_LIST_DCE100(_MASK)
-+};
-+
-+struct i2caux *dal_i2caux_dce100_create(
-+	struct dc_context *ctx)
-+{
-+	struct i2caux_dce110 *i2caux_dce110 =
-+		kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
-+
-+	if (!i2caux_dce110) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	dal_i2caux_dce110_construct(i2caux_dce110,
-+				    ctx,
-+				    dce100_aux_regs,
-+				    dce100_hw_engine_regs,
-+				    &i2c_shift,
-+				    &i2c_mask);
-+	return &i2caux_dce110->base;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.h.0130~	2017-12-14 06:39:58.432903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.h	2017-12-14 06:39:58.432903579 +0100
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_AUX_DCE100_H__
-+#define __DAL_I2C_AUX_DCE100_H__
-+
-+struct i2caux *dal_i2caux_dce100_create(
-+	struct dc_context *ctx);
-+
-+#endif /* __DAL_I2C_AUX_DCE100_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c.0130~	2017-12-14 06:39:58.432903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c	2017-12-14 06:39:58.432903579 +0100
-@@ -0,0 +1,470 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "../engine.h"
-+#include "../aux_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "aux_engine_dce110.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#define CTX \
-+	aux110->base.base.ctx
-+#define REG(reg_name)\
-+	(aux110->regs->reg_name)
-+#include "reg_helper.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+/*
-+ * @brief
-+ * Cast 'struct aux_engine *'
-+ * to 'struct aux_engine_dce110 *'
-+ */
-+#define FROM_AUX_ENGINE(ptr) \
-+	container_of((ptr), struct aux_engine_dce110, base)
-+
-+/*
-+ * @brief
-+ * Cast 'struct engine *'
-+ * to 'struct aux_engine_dce110 *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_AUX_ENGINE(container_of((ptr), struct aux_engine, base))
-+
-+static void release_engine(
-+	struct engine *engine)
-+{
-+	struct aux_engine_dce110 *aux110 = FROM_ENGINE(engine);
-+
-+	REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1);
-+}
-+
-+static void destruct(
-+	struct aux_engine_dce110 *engine);
-+
-+static void destroy(
-+	struct aux_engine **aux_engine)
-+{
-+	struct aux_engine_dce110 *engine = FROM_AUX_ENGINE(*aux_engine);
-+
-+	destruct(engine);
-+
-+	kfree(engine);
-+
-+	*aux_engine = NULL;
-+}
-+
-+#define SW_CAN_ACCESS_AUX 1
-+#define DMCU_CAN_ACCESS_AUX 2
-+
-+static bool is_engine_available(
-+	struct aux_engine *engine)
-+{
-+	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
-+
-+	uint32_t value = REG_READ(AUX_ARB_CONTROL);
-+	uint32_t field = get_reg_field_value(
-+			value,
-+			AUX_ARB_CONTROL,
-+			AUX_REG_RW_CNTL_STATUS);
-+
-+	return (field != DMCU_CAN_ACCESS_AUX);
-+}
-+static bool acquire_engine(
-+	struct aux_engine *engine)
-+{
-+	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
-+
-+	uint32_t value = REG_READ(AUX_ARB_CONTROL);
-+	uint32_t field = get_reg_field_value(
-+			value,
-+			AUX_ARB_CONTROL,
-+			AUX_REG_RW_CNTL_STATUS);
-+	if (field == DMCU_CAN_ACCESS_AUX)
-+	 return false;
-+	/* enable AUX before request SW to access AUX */
-+	value = REG_READ(AUX_CONTROL);
-+	field = get_reg_field_value(value,
-+				AUX_CONTROL,
-+				AUX_EN);
-+
-+	if (field == 0) {
-+		set_reg_field_value(
-+				value,
-+				1,
-+				AUX_CONTROL,
-+				AUX_EN);
-+
-+		if (REG(AUX_RESET_MASK)) {
-+			/*DP_AUX block as part of the enable sequence*/
-+			set_reg_field_value(
-+				value,
-+				1,
-+				AUX_CONTROL,
-+				AUX_RESET);
-+		}
-+
-+		REG_WRITE(AUX_CONTROL, value);
-+
-+		if (REG(AUX_RESET_MASK)) {
-+			/*poll HW to make sure reset it done*/
-+
-+			REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1,
-+					1, 11);
-+
-+			set_reg_field_value(
-+				value,
-+				0,
-+				AUX_CONTROL,
-+				AUX_RESET);
-+
-+			REG_WRITE(AUX_CONTROL, value);
-+
-+			REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0,
-+					1, 11);
-+		}
-+	} /*if (field)*/
-+
-+	/* request SW to access AUX */
-+	REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, 1);
-+
-+	value = REG_READ(AUX_ARB_CONTROL);
-+	field = get_reg_field_value(
-+			value,
-+			AUX_ARB_CONTROL,
-+			AUX_REG_RW_CNTL_STATUS);
-+
-+	return (field == SW_CAN_ACCESS_AUX);
-+}
-+
-+#define COMPOSE_AUX_SW_DATA_16_20(command, address) \
-+	((command) | ((0xF0000 & (address)) >> 16))
-+
-+#define COMPOSE_AUX_SW_DATA_8_15(address) \
-+	((0xFF00 & (address)) >> 8)
-+
-+#define COMPOSE_AUX_SW_DATA_0_7(address) \
-+	(0xFF & (address))
-+
-+static void submit_channel_request(
-+	struct aux_engine *engine,
-+	struct aux_request_transaction_data *request)
-+{
-+	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
-+	uint32_t value;
-+	uint32_t length;
-+
-+	bool is_write =
-+		((request->type == AUX_TRANSACTION_TYPE_DP) &&
-+		 (request->action == I2CAUX_TRANSACTION_ACTION_DP_WRITE)) ||
-+		((request->type == AUX_TRANSACTION_TYPE_I2C) &&
-+		((request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
-+		 (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT)));
-+
-+	/* clear_aux_error */
-+	REG_UPDATE_SEQ(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK,
-+			1,
-+			0);
-+
-+	REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK,
-+			1,
-+			0);
-+
-+	/* force_default_calibrate */
-+	REG_UPDATE_1BY1_2(AUXN_IMPCAL,
-+			AUXN_IMPCAL_ENABLE, 1,
-+			AUXN_IMPCAL_OVERRIDE_ENABLE, 0);
-+
-+	/* bug? why AUXN update EN and OVERRIDE_EN 1 by 1 while AUX P toggles OVERRIDE? */
-+
-+	REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE,
-+			1,
-+			0);
-+
-+	/* set the delay and the number of bytes to write */
-+
-+	/* The length include
-+	 * the 4 bit header and the 20 bit address
-+	 * (that is 3 byte).
-+	 * If the requested length is non zero this means
-+	 * an addition byte specifying the length is required. */
-+
-+	length = request->length ? 4 : 3;
-+	if (is_write)
-+		length += request->length;
-+
-+	REG_UPDATE_2(AUX_SW_CONTROL,
-+			AUX_SW_START_DELAY, request->delay,
-+			AUX_SW_WR_BYTES, length);
-+
-+	/* program action and address and payload data (if 'is_write') */
-+	value = REG_UPDATE_4(AUX_SW_DATA,
-+			AUX_SW_INDEX, 0,
-+			AUX_SW_DATA_RW, 0,
-+			AUX_SW_AUTOINCREMENT_DISABLE, 1,
-+			AUX_SW_DATA, COMPOSE_AUX_SW_DATA_16_20(request->action, request->address));
-+
-+	value = REG_SET_2(AUX_SW_DATA, value,
-+			AUX_SW_AUTOINCREMENT_DISABLE, 0,
-+			AUX_SW_DATA, COMPOSE_AUX_SW_DATA_8_15(request->address));
-+
-+	value = REG_SET(AUX_SW_DATA, value,
-+			AUX_SW_DATA, COMPOSE_AUX_SW_DATA_0_7(request->address));
-+
-+	if (request->length) {
-+		value = REG_SET(AUX_SW_DATA, value,
-+				AUX_SW_DATA, request->length - 1);
-+	}
-+
-+	if (is_write) {
-+		/* Load the HW buffer with the Data to be sent.
-+		 * This is relevant for write operation.
-+		 * For read, the data recived data will be
-+		 * processed in process_channel_reply(). */
-+		uint32_t i = 0;
-+
-+		while (i < request->length) {
-+			value = REG_SET(AUX_SW_DATA, value,
-+					AUX_SW_DATA, request->data[i]);
-+
-+			++i;
-+		}
-+	}
-+
-+	REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
-+	REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
-+				10, aux110->timeout_period/10);
-+	REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
-+}
-+
-+static void process_channel_reply(
-+	struct aux_engine *engine,
-+	struct aux_reply_transaction_data *reply)
-+{
-+	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
-+
-+	/* Need to do a read to get the number of bytes to process
-+	 * Alternatively, this information can be passed -
-+	 * but that causes coupling which isn't good either. */
-+
-+	uint32_t bytes_replied;
-+	uint32_t value;
-+
-+	value = REG_GET(AUX_SW_STATUS,
-+			AUX_SW_REPLY_BYTE_COUNT, &bytes_replied);
-+
-+	if (bytes_replied) {
-+		uint32_t reply_result;
-+
-+		REG_UPDATE_1BY1_3(AUX_SW_DATA,
-+				AUX_SW_INDEX, 0,
-+				AUX_SW_AUTOINCREMENT_DISABLE, 1,
-+				AUX_SW_DATA_RW, 1);
-+
-+		REG_GET(AUX_SW_DATA,
-+				AUX_SW_DATA, &reply_result);
-+
-+		reply_result = reply_result >> 4;
-+
-+		switch (reply_result) {
-+		case 0: /* ACK */ {
-+			uint32_t i = 0;
-+
-+			/* first byte was already used
-+			 * to get the command status */
-+			--bytes_replied;
-+
-+			while (i < bytes_replied) {
-+				uint32_t aux_sw_data_val;
-+
-+				REG_GET(AUX_SW_DATA,
-+						AUX_SW_DATA, &aux_sw_data_val);
-+
-+				reply->data[i] = aux_sw_data_val;
-+				++i;
-+			}
-+
-+			reply->status = AUX_TRANSACTION_REPLY_AUX_ACK;
-+		}
-+		break;
-+		case 1: /* NACK */
-+			reply->status = AUX_TRANSACTION_REPLY_AUX_NACK;
-+		break;
-+		case 2: /* DEFER */
-+			reply->status = AUX_TRANSACTION_REPLY_AUX_DEFER;
-+		break;
-+		case 4: /* AUX ACK / I2C NACK */
-+			reply->status = AUX_TRANSACTION_REPLY_I2C_NACK;
-+		break;
-+		case 8: /* AUX ACK / I2C DEFER */
-+			reply->status = AUX_TRANSACTION_REPLY_I2C_DEFER;
-+		break;
-+		default:
-+			reply->status = AUX_TRANSACTION_REPLY_INVALID;
-+		}
-+	} else {
-+		/* Need to handle an error case...
-+		 * hopefully, upper layer function won't call this function
-+		 * if the number of bytes in the reply was 0
-+		 * because there was surely an error that was asserted
-+		 * that should have been handled
-+		 * for hot plug case, this could happens*/
-+		if (!(value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
-+			ASSERT_CRITICAL(false);
-+	}
-+}
-+
-+static enum aux_channel_operation_result get_channel_status(
-+	struct aux_engine *engine,
-+	uint8_t *returned_bytes)
-+{
-+	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
-+
-+	uint32_t value;
-+
-+	if (returned_bytes == NULL) {
-+		/*caller pass NULL pointer*/
-+		ASSERT_CRITICAL(false);
-+		return AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN;
-+	}
-+	*returned_bytes = 0;
-+
-+	/* poll to make sure that SW_DONE is asserted */
-+	value = REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,
-+				10, aux110->timeout_period/10);
-+
-+	/* Note that the following bits are set in 'status.bits'
-+	 * during CTS 4.2.1.2 (FW 3.3.1):
-+	 * AUX_SW_RX_MIN_COUNT_VIOL, AUX_SW_RX_INVALID_STOP,
-+	 * AUX_SW_RX_RECV_NO_DET, AUX_SW_RX_RECV_INVALID_H.
-+	 *
-+	 * AUX_SW_RX_MIN_COUNT_VIOL is an internal,
-+	 * HW debugging bit and should be ignored. */
-+	if (value & AUX_SW_STATUS__AUX_SW_DONE_MASK) {
-+		if ((value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK) ||
-+			(value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK))
-+			return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT;
-+
-+		else if ((value & AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK) ||
-+			(value & AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK) ||
-+			(value &
-+				AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK) ||
-+			(value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK))
-+			return AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY;
-+
-+		*returned_bytes = get_reg_field_value(value,
-+				AUX_SW_STATUS,
-+				AUX_SW_REPLY_BYTE_COUNT);
-+
-+		if (*returned_bytes == 0)
-+			return
-+			AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY;
-+		else {
-+			*returned_bytes -= 1;
-+			return AUX_CHANNEL_OPERATION_SUCCEEDED;
-+		}
-+	} else {
-+		/*time_elapsed >= aux_engine->timeout_period */
-+		if (!(value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
-+			ASSERT_CRITICAL(false);
-+
-+		return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT;
-+	}
-+}
-+
-+static const struct aux_engine_funcs aux_engine_funcs = {
-+	.destroy = destroy,
-+	.acquire_engine = acquire_engine,
-+	.submit_channel_request = submit_channel_request,
-+	.process_channel_reply = process_channel_reply,
-+	.get_channel_status = get_channel_status,
-+	.is_engine_available = is_engine_available,
-+};
-+
-+static const struct engine_funcs engine_funcs = {
-+	.release_engine = release_engine,
-+	.submit_request = dal_aux_engine_submit_request,
-+	.get_engine_type = dal_aux_engine_get_engine_type,
-+	.acquire = dal_aux_engine_acquire,
-+};
-+
-+static void construct(
-+	struct aux_engine_dce110 *engine,
-+	const struct aux_engine_dce110_init_data *aux_init_data)
-+{
-+	dal_aux_engine_construct(&engine->base, aux_init_data->ctx);
-+	engine->base.base.funcs = &engine_funcs;
-+	engine->base.funcs = &aux_engine_funcs;
-+
-+	engine->timeout_period = aux_init_data->timeout_period;
-+	engine->regs = aux_init_data->regs;
-+}
-+
-+static void destruct(
-+	struct aux_engine_dce110 *engine)
-+{
-+	struct aux_engine_dce110 *aux110 = engine;
-+/*temp w/a, to do*/
-+	REG_UPDATE(AUX_ARB_CONTROL, AUX_DMCU_DONE_USING_AUX_REG, 1);
-+	REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1);
-+	dal_aux_engine_destruct(&engine->base);
-+}
-+
-+struct aux_engine *dal_aux_engine_dce110_create(
-+	const struct aux_engine_dce110_init_data *aux_init_data)
-+{
-+	struct aux_engine_dce110 *engine;
-+
-+	if (!aux_init_data) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	engine = kzalloc(sizeof(*engine), GFP_KERNEL);
-+
-+	if (!engine) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	construct(engine, aux_init_data);
-+	return &engine->base;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h.0130~	2017-12-14 06:39:58.432903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h	2017-12-14 06:39:58.432903579 +0100
-@@ -0,0 +1,78 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_AUX_ENGINE_DCE110_H__
-+#define __DAL_AUX_ENGINE_DCE110_H__
-+
-+#include "../aux_engine.h"
-+
-+#define AUX_COMMON_REG_LIST(id)\
-+	SRI(AUX_CONTROL, DP_AUX, id), \
-+	SRI(AUX_ARB_CONTROL, DP_AUX, id), \
-+	SRI(AUX_SW_DATA, DP_AUX, id), \
-+	SRI(AUX_SW_CONTROL, DP_AUX, id), \
-+	SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
-+	SRI(AUX_SW_STATUS, DP_AUX, id), \
-+	SR(AUXN_IMPCAL), \
-+	SR(AUXP_IMPCAL)
-+
-+struct dce110_aux_registers {
-+	uint32_t AUX_CONTROL;
-+	uint32_t AUX_ARB_CONTROL;
-+	uint32_t AUX_SW_DATA;
-+	uint32_t AUX_SW_CONTROL;
-+	uint32_t AUX_INTERRUPT_CONTROL;
-+	uint32_t AUX_SW_STATUS;
-+	uint32_t AUXN_IMPCAL;
-+	uint32_t AUXP_IMPCAL;
-+
-+	uint32_t AUX_RESET_MASK;
-+};
-+
-+struct aux_engine_dce110 {
-+	struct aux_engine base;
-+	const struct dce110_aux_registers *regs;
-+	struct {
-+		uint32_t aux_control;
-+		uint32_t aux_arb_control;
-+		uint32_t aux_sw_data;
-+		uint32_t aux_sw_control;
-+		uint32_t aux_interrupt_control;
-+		uint32_t aux_sw_status;
-+	} addr;
-+	uint32_t timeout_period;
-+};
-+
-+struct aux_engine_dce110_init_data {
-+	uint32_t engine_id;
-+	uint32_t timeout_period;
-+	struct dc_context *ctx;
-+	const struct dce110_aux_registers *regs;
-+};
-+
-+struct aux_engine *dal_aux_engine_dce110_create(
-+	const struct aux_engine_dce110_init_data *aux_init_data);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c.0130~	2017-12-14 06:39:58.432903579 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c	2017-12-14 06:39:58.432903579 +0100
-@@ -0,0 +1,311 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "../i2caux.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_sw_engine.h"
-+#include "../i2c_hw_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+#include "i2caux_dce110.h"
-+
-+#include "i2c_sw_engine_dce110.h"
-+#include "i2c_hw_engine_dce110.h"
-+#include "aux_engine_dce110.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+/*cast pointer to struct i2caux TO pointer to struct i2caux_dce110*/
-+#define FROM_I2C_AUX(ptr) \
-+	container_of((ptr), struct i2caux_dce110, base)
-+
-+static void destruct(
-+	struct i2caux_dce110 *i2caux_dce110)
-+{
-+	dal_i2caux_destruct(&i2caux_dce110->base);
-+}
-+
-+static void destroy(
-+	struct i2caux **i2c_engine)
-+{
-+	struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(*i2c_engine);
-+
-+	destruct(i2caux_dce110);
-+
-+	kfree(i2caux_dce110);
-+
-+	*i2c_engine = NULL;
-+}
-+
-+static struct i2c_engine *acquire_i2c_hw_engine(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc)
-+{
-+	struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
-+
-+	struct i2c_engine *engine = NULL;
-+	/* generic hw engine is not used for EDID read
-+	 * It may be needed for external i2c device, like thermal chip,
-+	 * TODO will be implemented when needed.
-+	 * check dce80 bool non_generic for generic hw engine;
-+	 */
-+
-+	if (!ddc)
-+		return NULL;
-+
-+	if (ddc->hw_info.hw_supported) {
-+		enum gpio_ddc_line line = dal_ddc_get_line(ddc);
-+
-+		if (line < GPIO_DDC_LINE_COUNT)
-+			engine = i2caux->i2c_hw_engines[line];
-+	}
-+
-+	if (!engine)
-+		return NULL;
-+
-+	if (!i2caux_dce110->i2c_hw_buffer_in_use &&
-+		engine->base.funcs->acquire(&engine->base, ddc)) {
-+		i2caux_dce110->i2c_hw_buffer_in_use = true;
-+		return engine;
-+	}
-+
-+	return NULL;
-+}
-+
-+static void release_engine(
-+	struct i2caux *i2caux,
-+	struct engine *engine)
-+{
-+	struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
-+
-+	if (engine->funcs->get_engine_type(engine) ==
-+		I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
-+		i2caux_dce110->i2c_hw_buffer_in_use = false;
-+
-+	dal_i2caux_release_engine(i2caux, engine);
-+}
-+
-+static const enum gpio_ddc_line hw_ddc_lines[] = {
-+	GPIO_DDC_LINE_DDC1,
-+	GPIO_DDC_LINE_DDC2,
-+	GPIO_DDC_LINE_DDC3,
-+	GPIO_DDC_LINE_DDC4,
-+	GPIO_DDC_LINE_DDC5,
-+	GPIO_DDC_LINE_DDC6,
-+};
-+
-+static const enum gpio_ddc_line hw_aux_lines[] = {
-+	GPIO_DDC_LINE_DDC1,
-+	GPIO_DDC_LINE_DDC2,
-+	GPIO_DDC_LINE_DDC3,
-+	GPIO_DDC_LINE_DDC4,
-+	GPIO_DDC_LINE_DDC5,
-+	GPIO_DDC_LINE_DDC6,
-+};
-+
-+/* function table */
-+static const struct i2caux_funcs i2caux_funcs = {
-+	.destroy = destroy,
-+	.acquire_i2c_hw_engine = acquire_i2c_hw_engine,
-+	.release_engine = release_engine,
-+	.acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
-+	.acquire_aux_engine = dal_i2caux_acquire_aux_engine,
-+};
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+/* set register offset */
-+#define SR(reg_name)\
-+	.reg_name = mm ## reg_name
-+
-+/* set register offset with instance */
-+#define SRI(reg_name, block, id)\
-+	.reg_name = mm ## block ## id ## _ ## reg_name
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	AUX_COMMON_REG_LIST(id), \
-+	.AUX_RESET_MASK = AUX_CONTROL__AUX_RESET_MASK \
-+}
-+
-+#define hw_engine_regs(id)\
-+{\
-+		I2C_HW_ENGINE_COMMON_REG_LIST(id) \
-+}
-+
-+static const struct dce110_aux_registers dce110_aux_regs[] = {
-+		aux_regs(0),
-+		aux_regs(1),
-+		aux_regs(2),
-+		aux_regs(3),
-+		aux_regs(4),
-+		aux_regs(5)
-+};
-+
-+static const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[] = {
-+		hw_engine_regs(1),
-+		hw_engine_regs(2),
-+		hw_engine_regs(3),
-+		hw_engine_regs(4),
-+		hw_engine_regs(5),
-+		hw_engine_regs(6)
-+};
-+
-+static const struct dce110_i2c_hw_engine_shift i2c_shift = {
-+		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-+};
-+
-+static const struct dce110_i2c_hw_engine_mask i2c_mask = {
-+		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
-+};
-+
-+void dal_i2caux_dce110_construct(
-+	struct i2caux_dce110 *i2caux_dce110,
-+	struct dc_context *ctx,
-+	const struct dce110_aux_registers aux_regs[],
-+	const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[],
-+	const struct dce110_i2c_hw_engine_shift *i2c_shift,
-+	const struct dce110_i2c_hw_engine_mask *i2c_mask)
-+{
-+	uint32_t i = 0;
-+	uint32_t reference_frequency = 0;
-+	bool use_i2c_sw_engine = false;
-+	struct i2caux *base = NULL;
-+	/*TODO: For CZ bring up, if dal_i2caux_get_reference_clock
-+	 * does not return 48KHz, we need hard coded for 48Khz.
-+	 * Some BIOS setting incorrect cause this
-+	 * For production, we always get value from BIOS*/
-+	reference_frequency =
-+		dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
-+
-+	base = &i2caux_dce110->base;
-+
-+	dal_i2caux_construct(base, ctx);
-+
-+	i2caux_dce110->base.funcs = &i2caux_funcs;
-+	i2caux_dce110->i2c_hw_buffer_in_use = false;
-+	/* Create I2C engines (DDC lines per connector)
-+	 * different I2C/AUX usage cases, DDC, Generic GPIO, AUX.
-+	 */
-+	do {
-+		enum gpio_ddc_line line_id = hw_ddc_lines[i];
-+
-+		struct i2c_hw_engine_dce110_create_arg hw_arg_dce110;
-+
-+		if (use_i2c_sw_engine) {
-+			struct i2c_sw_engine_dce110_create_arg sw_arg;
-+
-+			sw_arg.engine_id = i;
-+			sw_arg.default_speed = base->default_i2c_sw_speed;
-+			sw_arg.ctx = ctx;
-+			base->i2c_sw_engines[line_id] =
-+				dal_i2c_sw_engine_dce110_create(&sw_arg);
-+		}
-+
-+		hw_arg_dce110.engine_id = i;
-+		hw_arg_dce110.reference_frequency = reference_frequency;
-+		hw_arg_dce110.default_speed = base->default_i2c_hw_speed;
-+		hw_arg_dce110.ctx = ctx;
-+		hw_arg_dce110.regs = &i2c_hw_engine_regs[i];
-+		hw_arg_dce110.i2c_shift = i2c_shift;
-+		hw_arg_dce110.i2c_mask = i2c_mask;
-+
-+		base->i2c_hw_engines[line_id] =
-+			dal_i2c_hw_engine_dce110_create(&hw_arg_dce110);
-+
-+		++i;
-+	} while (i < ARRAY_SIZE(hw_ddc_lines));
-+
-+	/* Create AUX engines for all lines which has assisted HW AUX
-+	 * 'i' (loop counter) used as DDC/AUX engine_id */
-+
-+	i = 0;
-+
-+	do {
-+		enum gpio_ddc_line line_id = hw_aux_lines[i];
-+
-+		struct aux_engine_dce110_init_data aux_init_data;
-+
-+		aux_init_data.engine_id = i;
-+		aux_init_data.timeout_period = base->aux_timeout_period;
-+		aux_init_data.ctx = ctx;
-+		aux_init_data.regs = &aux_regs[i];
-+
-+		base->aux_engines[line_id] =
-+			dal_aux_engine_dce110_create(&aux_init_data);
-+
-+		++i;
-+	} while (i < ARRAY_SIZE(hw_aux_lines));
-+
-+	/*TODO Generic I2C SW and HW*/
-+}
-+
-+/*
-+ * dal_i2caux_dce110_create
-+ *
-+ * @brief
-+ * public interface to allocate memory for DCE11 I2CAUX
-+ *
-+ * @param
-+ * struct adapter_service *as - [in]
-+ * struct dc_context *ctx - [in]
-+ *
-+ * @return
-+ * pointer to the base struct of DCE11 I2CAUX
-+ */
-+struct i2caux *dal_i2caux_dce110_create(
-+	struct dc_context *ctx)
-+{
-+	struct i2caux_dce110 *i2caux_dce110 =
-+		kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
-+
-+	if (!i2caux_dce110) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	dal_i2caux_dce110_construct(i2caux_dce110,
-+				    ctx,
-+				    dce110_aux_regs,
-+				    i2c_hw_engine_regs,
-+				    &i2c_shift,
-+				    &i2c_mask);
-+	return &i2caux_dce110->base;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.h.0130~	2017-12-14 06:39:58.433903580 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.h	2017-12-14 06:39:58.432903579 +0100
-@@ -0,0 +1,53 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_AUX_DCE110_H__
-+#define __DAL_I2C_AUX_DCE110_H__
-+
-+#include "../i2caux.h"
-+
-+struct i2caux_dce110 {
-+	struct i2caux base;
-+	/* indicate the I2C HW circular buffer is in use */
-+	bool i2c_hw_buffer_in_use;
-+};
-+
-+struct dce110_aux_registers;
-+struct dce110_i2c_hw_engine_registers;
-+struct dce110_i2c_hw_engine_shift;
-+struct dce110_i2c_hw_engine_mask;
-+
-+struct i2caux *dal_i2caux_dce110_create(
-+	struct dc_context *ctx);
-+
-+void dal_i2caux_dce110_construct(
-+	struct i2caux_dce110 *i2caux_dce110,
-+	struct dc_context *ctx,
-+	const struct dce110_aux_registers *aux_regs,
-+	const struct dce110_i2c_hw_engine_registers *i2c_hw_engine_regs,
-+	const struct dce110_i2c_hw_engine_shift *i2c_shift,
-+	const struct dce110_i2c_hw_engine_mask *i2c_mask);
-+
-+#endif /* __DAL_I2C_AUX_DCE110_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c.0130~	2017-12-14 06:39:58.433903580 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c	2017-12-14 06:39:58.433903580 +0100
-@@ -0,0 +1,570 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "include/logger_interface.h"
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+
-+#include "include/i2caux_interface.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_hw_engine.h"
-+#include "../i2c_generic_hw_engine.h"
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_hw_engine_dce110.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+#include "reg_helper.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+enum dc_i2c_status {
-+	DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
-+	DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
-+	DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
-+};
-+
-+enum dc_i2c_arbitration {
-+	DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
-+	DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
-+};
-+
-+enum {
-+	/* No timeout in HW
-+	 * (timeout implemented in SW by querying status) */
-+	I2C_SETUP_TIME_LIMIT = 255,
-+	I2C_HW_BUFFER_SIZE = 538
-+};
-+
-+/*
-+ * @brief
-+ * Cast pointer to 'struct i2c_hw_engine *'
-+ * to pointer 'struct i2c_hw_engine_dce110 *'
-+ */
-+#define FROM_I2C_HW_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_hw_engine_dce110, base)
-+/*
-+ * @brief
-+ * Cast pointer to 'struct i2c_engine *'
-+ * to pointer to 'struct i2c_hw_engine_dce110 *'
-+ */
-+#define FROM_I2C_ENGINE(ptr) \
-+	FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
-+
-+/*
-+ * @brief
-+ * Cast pointer to 'struct engine *'
-+ * to 'pointer to struct i2c_hw_engine_dce110 *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-+
-+#define CTX \
-+		hw_engine->base.base.base.ctx
-+
-+#define REG(reg_name)\
-+	(hw_engine->regs->reg_name)
-+
-+#undef FN
-+#define FN(reg_name, field_name) \
-+	hw_engine->i2c_shift->field_name, hw_engine->i2c_mask->field_name
-+
-+#include "reg_helper.h"
-+
-+static void disable_i2c_hw_engine(
-+	struct i2c_hw_engine_dce110 *hw_engine)
-+{
-+	REG_UPDATE_N(SETUP, 1, FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 0);
-+}
-+
-+static void release_engine(
-+	struct engine *engine)
-+{
-+	struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine);
-+
-+	struct i2c_engine *base = NULL;
-+	bool safe_to_reset;
-+
-+	base = &hw_engine->base.base;
-+
-+	/* Restore original HW engine speed */
-+
-+	base->funcs->set_speed(base, hw_engine->base.original_speed);
-+
-+	/* Release I2C */
-+	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1);
-+
-+	/* Reset HW engine */
-+	{
-+		uint32_t i2c_sw_status = 0;
-+		REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
-+		/* if used by SW, safe to reset */
-+		safe_to_reset = (i2c_sw_status == 1);
-+	}
-+
-+	if (safe_to_reset)
-+		REG_UPDATE_2(
-+			DC_I2C_CONTROL,
-+			DC_I2C_SOFT_RESET, 1,
-+			DC_I2C_SW_STATUS_RESET, 1);
-+	else
-+		REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
-+
-+	/* HW I2c engine - clock gating feature */
-+	if (!hw_engine->engine_keep_power_up_count)
-+		disable_i2c_hw_engine(hw_engine);
-+}
-+
-+static bool setup_engine(
-+	struct i2c_engine *i2c_engine)
-+{
-+	struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine);
-+
-+	/* Program pin select */
-+	REG_UPDATE_6(
-+			DC_I2C_CONTROL,
-+			DC_I2C_GO, 0,
-+			DC_I2C_SOFT_RESET, 0,
-+			DC_I2C_SEND_RESET, 0,
-+			DC_I2C_SW_STATUS_RESET, 1,
-+			DC_I2C_TRANSACTION_COUNT, 0,
-+			DC_I2C_DDC_SELECT, hw_engine->engine_id);
-+
-+	/* Program time limit */
-+	REG_UPDATE_N(
-+			SETUP, 2,
-+			FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), I2C_SETUP_TIME_LIMIT,
-+			FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
-+
-+	/* Program HW priority
-+	 * set to High - interrupt software I2C at any time
-+	 * Enable restart of SW I2C that was interrupted by HW
-+	 * disable queuing of software while I2C is in use by HW */
-+	REG_UPDATE_2(
-+			DC_I2C_ARBITRATION,
-+			DC_I2C_NO_QUEUED_SW_GO, 0,
-+			DC_I2C_SW_PRIORITY, DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL);
-+
-+	return true;
-+}
-+
-+static uint32_t get_speed(
-+	const struct i2c_engine *i2c_engine)
-+{
-+	const struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine);
-+	uint32_t pre_scale = 0;
-+
-+	REG_GET(SPEED, DC_I2C_DDC1_PRESCALE, &pre_scale);
-+
-+	/* [anaumov] it seems following is unnecessary */
-+	/*ASSERT(value.bits.DC_I2C_DDC1_PRESCALE);*/
-+	return pre_scale ?
-+		hw_engine->reference_frequency / pre_scale :
-+		hw_engine->base.default_speed;
-+}
-+
-+static void set_speed(
-+	struct i2c_engine *i2c_engine,
-+	uint32_t speed)
-+{
-+	struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine);
-+
-+	if (speed) {
-+		if (hw_engine->i2c_mask->DC_I2C_DDC1_START_STOP_TIMING_CNTL)
-+			REG_UPDATE_N(
-+				SPEED, 3,
-+				FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), hw_engine->reference_frequency / speed,
-+				FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2,
-+				FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL), speed > 50 ? 2:1);
-+		else
-+			REG_UPDATE_N(
-+				SPEED, 2,
-+				FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), hw_engine->reference_frequency / speed,
-+				FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2);
-+	}
-+}
-+
-+static inline void reset_hw_engine(struct engine *engine)
-+{
-+	struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine);
-+
-+	REG_UPDATE_2(
-+			DC_I2C_CONTROL,
-+			DC_I2C_SW_STATUS_RESET, 1,
-+			DC_I2C_SW_STATUS_RESET, 1);
-+}
-+
-+static bool is_hw_busy(struct engine *engine)
-+{
-+	struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine);
-+	uint32_t i2c_sw_status = 0;
-+
-+	REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
-+	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
-+		return false;
-+
-+	reset_hw_engine(engine);
-+
-+	REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
-+	return i2c_sw_status != DC_I2C_STATUS__DC_I2C_STATUS_IDLE;
-+}
-+
-+
-+#define STOP_TRANS_PREDICAT \
-+		((hw_engine->transaction_count == 3) ||	\
-+				(request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||	\
-+				(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ))
-+
-+#define SET_I2C_TRANSACTION(id)	\
-+		do {	\
-+			REG_UPDATE_N(DC_I2C_TRANSACTION##id, 5,	\
-+				FN(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0), 1,	\
-+				FN(DC_I2C_TRANSACTION0, DC_I2C_START0), 1,	\
-+				FN(DC_I2C_TRANSACTION0, DC_I2C_STOP0), STOP_TRANS_PREDICAT ? 1:0,	\
-+				FN(DC_I2C_TRANSACTION0, DC_I2C_RW0), (0 != (request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)),	\
-+				FN(DC_I2C_TRANSACTION0, DC_I2C_COUNT0), length);	\
-+				if (STOP_TRANS_PREDICAT)	\
-+					last_transaction = true;	\
-+		} while (false)
-+
-+
-+static bool process_transaction(
-+	struct i2c_hw_engine_dce110 *hw_engine,
-+	struct i2c_request_transaction_data *request)
-+{
-+	uint32_t length = request->length;
-+	uint8_t *buffer = request->data;
-+	uint32_t value = 0;
-+
-+	bool last_transaction = false;
-+
-+	struct dc_context *ctx = NULL;
-+
-+	ctx = hw_engine->base.base.base.ctx;
-+
-+
-+
-+	switch (hw_engine->transaction_count) {
-+	case 0:
-+		SET_I2C_TRANSACTION(0);
-+		break;
-+	case 1:
-+		SET_I2C_TRANSACTION(1);
-+		break;
-+	case 2:
-+		SET_I2C_TRANSACTION(2);
-+		break;
-+	case 3:
-+		SET_I2C_TRANSACTION(3);
-+		break;
-+	default:
-+		/* TODO Warning ? */
-+		break;
-+	}
-+
-+
-+	/* Write the I2C address and I2C data
-+	 * into the hardware circular buffer, one byte per entry.
-+	 * As an example, the 7-bit I2C slave address for CRT monitor
-+	 * for reading DDC/EDID information is 0b1010001.
-+	 * For an I2C send operation, the LSB must be programmed to 0;
-+	 * for I2C receive operation, the LSB must be programmed to 1. */
-+	if (hw_engine->transaction_count == 0) {
-+		value = REG_SET_4(DC_I2C_DATA, 0,
-+				  DC_I2C_DATA_RW, false,
-+				  DC_I2C_DATA, request->address,
-+				  DC_I2C_INDEX, 0,
-+				  DC_I2C_INDEX_WRITE, 1);
-+		hw_engine->buffer_used_write = 0;
-+	} else
-+		value = REG_SET_2(DC_I2C_DATA, 0,
-+				  DC_I2C_DATA_RW, false,
-+				  DC_I2C_DATA, request->address);
-+
-+	hw_engine->buffer_used_write++;
-+
-+	if (!(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-+		while (length) {
-+			REG_SET_2(DC_I2C_DATA, value,
-+					DC_I2C_INDEX_WRITE, 0,
-+					DC_I2C_DATA, *buffer++);
-+			hw_engine->buffer_used_write++;
-+			--length;
-+		}
-+	}
-+
-+	++hw_engine->transaction_count;
-+	hw_engine->buffer_used_bytes += length + 1;
-+
-+	return last_transaction;
-+}
-+
-+static void execute_transaction(
-+	struct i2c_hw_engine_dce110 *hw_engine)
-+{
-+	REG_UPDATE_N(SETUP, 5,
-+		FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN), 0,
-+		FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN), 0,
-+		FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL), 0,
-+		FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY), 0,
-+		FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY), 0);
-+
-+
-+	REG_UPDATE_5(DC_I2C_CONTROL,
-+		DC_I2C_SOFT_RESET, 0,
-+		DC_I2C_SW_STATUS_RESET, 0,
-+		DC_I2C_SEND_RESET, 0,
-+		DC_I2C_GO, 0,
-+		DC_I2C_TRANSACTION_COUNT, hw_engine->transaction_count - 1);
-+
-+	/* start I2C transfer */
-+	REG_UPDATE(DC_I2C_CONTROL, DC_I2C_GO, 1);
-+
-+	/* all transactions were executed and HW buffer became empty
-+	 * (even though it actually happens when status becomes DONE) */
-+	hw_engine->transaction_count = 0;
-+	hw_engine->buffer_used_bytes = 0;
-+}
-+
-+static void submit_channel_request(
-+	struct i2c_engine *engine,
-+	struct i2c_request_transaction_data *request)
-+{
-+	request->status = I2C_CHANNEL_OPERATION_SUCCEEDED;
-+
-+	if (!process_transaction(FROM_I2C_ENGINE(engine), request))
-+		return;
-+
-+	if (is_hw_busy(&engine->base)) {
-+		request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
-+		return;
-+	}
-+
-+	execute_transaction(FROM_I2C_ENGINE(engine));
-+}
-+
-+static void process_channel_reply(
-+	struct i2c_engine *engine,
-+	struct i2c_reply_transaction_data *reply)
-+{
-+	uint32_t length = reply->length;
-+	uint8_t *buffer = reply->data;
-+
-+	struct i2c_hw_engine_dce110 *hw_engine =
-+		FROM_I2C_ENGINE(engine);
-+
-+
-+	REG_SET_3(DC_I2C_DATA, 0,
-+			DC_I2C_INDEX, hw_engine->buffer_used_write,
-+			DC_I2C_DATA_RW, 1,
-+			DC_I2C_INDEX_WRITE, 1);
-+
-+	while (length) {
-+		/* after reading the status,
-+		 * if the I2C operation executed successfully
-+		 * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
-+		 * should read data bytes from I2C circular data buffer */
-+
-+		uint32_t i2c_data;
-+
-+		REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data);
-+		*buffer++ = i2c_data;
-+
-+		--length;
-+	}
-+}
-+
-+static enum i2c_channel_operation_result get_channel_status(
-+	struct i2c_engine *i2c_engine,
-+	uint8_t *returned_bytes)
-+{
-+	uint32_t i2c_sw_status = 0;
-+	struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine);
-+	uint32_t value =
-+			REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
-+
-+	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
-+		return I2C_CHANNEL_OPERATION_ENGINE_BUSY;
-+	else if (value & hw_engine->i2c_mask->DC_I2C_SW_STOPPED_ON_NACK)
-+		return I2C_CHANNEL_OPERATION_NO_RESPONSE;
-+	else if (value & hw_engine->i2c_mask->DC_I2C_SW_TIMEOUT)
-+		return I2C_CHANNEL_OPERATION_TIMEOUT;
-+	else if (value & hw_engine->i2c_mask->DC_I2C_SW_ABORTED)
-+		return I2C_CHANNEL_OPERATION_FAILED;
-+	else if (value & hw_engine->i2c_mask->DC_I2C_SW_DONE)
-+		return I2C_CHANNEL_OPERATION_SUCCEEDED;
-+
-+	/*
-+	 * this is the case when HW used for communication, I2C_SW_STATUS
-+	 * could be zero
-+	 */
-+	return I2C_CHANNEL_OPERATION_SUCCEEDED;
-+}
-+
-+static uint32_t get_hw_buffer_available_size(
-+	const struct i2c_hw_engine *engine)
-+{
-+	return I2C_HW_BUFFER_SIZE -
-+		FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes;
-+}
-+
-+static uint32_t get_transaction_timeout(
-+	const struct i2c_hw_engine *engine,
-+	uint32_t length)
-+{
-+	uint32_t speed = engine->base.funcs->get_speed(&engine->base);
-+
-+	uint32_t period_timeout;
-+	uint32_t num_of_clock_stretches;
-+
-+	if (!speed)
-+		return 0;
-+
-+	period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed;
-+
-+	num_of_clock_stretches = 1 + (length << 3) + 1;
-+	num_of_clock_stretches +=
-+		(FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes << 3) +
-+		(FROM_I2C_HW_ENGINE(engine)->transaction_count << 1);
-+
-+	return period_timeout * num_of_clock_stretches;
-+}
-+
-+static void destroy(
-+	struct i2c_engine **i2c_engine)
-+{
-+	struct i2c_hw_engine_dce110 *engine_dce110 =
-+			FROM_I2C_ENGINE(*i2c_engine);
-+
-+	dal_i2c_hw_engine_destruct(&engine_dce110->base);
-+
-+	kfree(engine_dce110);
-+
-+	*i2c_engine = NULL;
-+}
-+
-+static const struct i2c_engine_funcs i2c_engine_funcs = {
-+	.destroy = destroy,
-+	.get_speed = get_speed,
-+	.set_speed = set_speed,
-+	.setup_engine = setup_engine,
-+	.submit_channel_request = submit_channel_request,
-+	.process_channel_reply = process_channel_reply,
-+	.get_channel_status = get_channel_status,
-+	.acquire_engine = dal_i2c_hw_engine_acquire_engine,
-+};
-+
-+static const struct engine_funcs engine_funcs = {
-+	.release_engine = release_engine,
-+	.get_engine_type = dal_i2c_hw_engine_get_engine_type,
-+	.acquire = dal_i2c_engine_acquire,
-+	.submit_request = dal_i2c_hw_engine_submit_request,
-+};
-+
-+static const struct i2c_hw_engine_funcs i2c_hw_engine_funcs = {
-+	.get_hw_buffer_available_size = get_hw_buffer_available_size,
-+	.get_transaction_timeout = get_transaction_timeout,
-+	.wait_on_operation_result = dal_i2c_hw_engine_wait_on_operation_result,
-+};
-+
-+static void construct(
-+	struct i2c_hw_engine_dce110 *hw_engine,
-+	const struct i2c_hw_engine_dce110_create_arg *arg)
-+{
-+	uint32_t xtal_ref_div = 0;
-+
-+	dal_i2c_hw_engine_construct(&hw_engine->base, arg->ctx);
-+
-+	hw_engine->base.base.base.funcs = &engine_funcs;
-+	hw_engine->base.base.funcs = &i2c_engine_funcs;
-+	hw_engine->base.funcs = &i2c_hw_engine_funcs;
-+	hw_engine->base.default_speed = arg->default_speed;
-+
-+	hw_engine->regs = arg->regs;
-+	hw_engine->i2c_shift = arg->i2c_shift;
-+	hw_engine->i2c_mask = arg->i2c_mask;
-+
-+	hw_engine->engine_id = arg->engine_id;
-+
-+	hw_engine->buffer_used_bytes = 0;
-+	hw_engine->transaction_count = 0;
-+	hw_engine->engine_keep_power_up_count = 1;
-+
-+
-+	REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);
-+
-+	if (xtal_ref_div == 0) {
-+		dm_logger_write(
-+				hw_engine->base.base.base.ctx->logger, LOG_WARNING,
-+				"Invalid base timer divider\n",
-+				__func__);
-+		xtal_ref_div = 2;
-+	}
-+
-+	/*Calculating Reference Clock by divding original frequency by
-+	 * XTAL_REF_DIV.
-+	 * At upper level, uint32_t reference_frequency =
-+	 *  dal_i2caux_get_reference_clock(as) >> 1
-+	 *  which already divided by 2. So we need x2 to get original
-+	 *  reference clock from ppll_info
-+	 */
-+	hw_engine->reference_frequency =
-+		(arg->reference_frequency * 2) / xtal_ref_div;
-+}
-+
-+struct i2c_engine *dal_i2c_hw_engine_dce110_create(
-+	const struct i2c_hw_engine_dce110_create_arg *arg)
-+{
-+	struct i2c_hw_engine_dce110 *engine_dce10;
-+
-+	if (!arg) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+	if (!arg->reference_frequency) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	engine_dce10 = kzalloc(sizeof(struct i2c_hw_engine_dce110),
-+			       GFP_KERNEL);
-+
-+	if (!engine_dce10) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	construct(engine_dce10, arg);
-+	return &engine_dce10->base.base;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h.0130~	2017-12-14 06:39:58.433903580 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h	2017-12-14 06:39:58.433903580 +0100
-@@ -0,0 +1,210 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_HW_ENGINE_DCE110_H__
-+#define __DAL_I2C_HW_ENGINE_DCE110_H__
-+
-+#define I2C_HW_ENGINE_COMMON_REG_LIST(id)\
-+	SRI(SETUP, DC_I2C_DDC, id),\
-+	SRI(SPEED, DC_I2C_DDC, id),\
-+	SR(DC_I2C_ARBITRATION),\
-+	SR(DC_I2C_CONTROL),\
-+	SR(DC_I2C_SW_STATUS),\
-+	SR(DC_I2C_TRANSACTION0),\
-+	SR(DC_I2C_TRANSACTION1),\
-+	SR(DC_I2C_TRANSACTION2),\
-+	SR(DC_I2C_TRANSACTION3),\
-+	SR(DC_I2C_DATA),\
-+	SR(MICROSECOND_TIME_BASE_DIV)
-+
-+#define I2C_SF(reg_name, field_name, post_fix)\
-+	.field_name = reg_name ## __ ## field_name ## post_fix
-+
-+#define I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
-+	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
-+	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT, mask_sh),\
-+	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN, mask_sh),\
-+	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN, mask_sh),\
-+	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL, mask_sh),\
-+	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY, mask_sh),\
-+	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY, mask_sh),\
-+	I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, mask_sh),\
-+	I2C_SF(DC_I2C_ARBITRATION, DC_I2C_NO_QUEUED_SW_GO, mask_sh),\
-+	I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_PRIORITY, mask_sh),\
-+	I2C_SF(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, mask_sh),\
-+	I2C_SF(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, mask_sh),\
-+	I2C_SF(DC_I2C_CONTROL, DC_I2C_GO, mask_sh),\
-+	I2C_SF(DC_I2C_CONTROL, DC_I2C_SEND_RESET, mask_sh),\
-+	I2C_SF(DC_I2C_CONTROL, DC_I2C_TRANSACTION_COUNT, mask_sh),\
-+	I2C_SF(DC_I2C_CONTROL, DC_I2C_DDC_SELECT, mask_sh),\
-+	I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE, mask_sh),\
-+	I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD, mask_sh),\
-+	I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STOPPED_ON_NACK, mask_sh),\
-+	I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_TIMEOUT, mask_sh),\
-+	I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_ABORTED, mask_sh),\
-+	I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_DONE, mask_sh),\
-+	I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, mask_sh),\
-+	I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0, mask_sh),\
-+	I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_START0, mask_sh),\
-+	I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_RW0, mask_sh),\
-+	I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP0, mask_sh),\
-+	I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_COUNT0, mask_sh),\
-+	I2C_SF(DC_I2C_DATA, DC_I2C_DATA_RW, mask_sh),\
-+	I2C_SF(DC_I2C_DATA, DC_I2C_DATA, mask_sh),\
-+	I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\
-+	I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\
-+	I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh)
-+
-+#define I2C_COMMON_MASK_SH_LIST_DCE100(mask_sh)\
-+	I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
-+
-+#define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
-+	I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
-+	I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL, mask_sh)
-+
-+struct dce110_i2c_hw_engine_shift {
-+	uint8_t DC_I2C_DDC1_ENABLE;
-+	uint8_t DC_I2C_DDC1_TIME_LIMIT;
-+	uint8_t DC_I2C_DDC1_DATA_DRIVE_EN;
-+	uint8_t DC_I2C_DDC1_CLK_DRIVE_EN;
-+	uint8_t DC_I2C_DDC1_DATA_DRIVE_SEL;
-+	uint8_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
-+	uint8_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
-+	uint8_t DC_I2C_SW_DONE_USING_I2C_REG;
-+	uint8_t DC_I2C_NO_QUEUED_SW_GO;
-+	uint8_t DC_I2C_SW_PRIORITY;
-+	uint8_t DC_I2C_SOFT_RESET;
-+	uint8_t DC_I2C_SW_STATUS_RESET;
-+	uint8_t DC_I2C_GO;
-+	uint8_t DC_I2C_SEND_RESET;
-+	uint8_t DC_I2C_TRANSACTION_COUNT;
-+	uint8_t DC_I2C_DDC_SELECT;
-+	uint8_t DC_I2C_DDC1_PRESCALE;
-+	uint8_t DC_I2C_DDC1_THRESHOLD;
-+	uint8_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;
-+	uint8_t DC_I2C_SW_STOPPED_ON_NACK;
-+	uint8_t DC_I2C_SW_TIMEOUT;
-+	uint8_t DC_I2C_SW_ABORTED;
-+	uint8_t DC_I2C_SW_DONE;
-+	uint8_t DC_I2C_SW_STATUS;
-+	uint8_t DC_I2C_STOP_ON_NACK0;
-+	uint8_t DC_I2C_START0;
-+	uint8_t DC_I2C_RW0;
-+	uint8_t DC_I2C_STOP0;
-+	uint8_t DC_I2C_COUNT0;
-+	uint8_t DC_I2C_DATA_RW;
-+	uint8_t DC_I2C_DATA;
-+	uint8_t DC_I2C_INDEX;
-+	uint8_t DC_I2C_INDEX_WRITE;
-+	uint8_t XTAL_REF_DIV;
-+};
-+
-+struct dce110_i2c_hw_engine_mask {
-+	uint32_t DC_I2C_DDC1_ENABLE;
-+	uint32_t DC_I2C_DDC1_TIME_LIMIT;
-+	uint32_t DC_I2C_DDC1_DATA_DRIVE_EN;
-+	uint32_t DC_I2C_DDC1_CLK_DRIVE_EN;
-+	uint32_t DC_I2C_DDC1_DATA_DRIVE_SEL;
-+	uint32_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
-+	uint32_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
-+	uint32_t DC_I2C_SW_DONE_USING_I2C_REG;
-+	uint32_t DC_I2C_NO_QUEUED_SW_GO;
-+	uint32_t DC_I2C_SW_PRIORITY;
-+	uint32_t DC_I2C_SOFT_RESET;
-+	uint32_t DC_I2C_SW_STATUS_RESET;
-+	uint32_t DC_I2C_GO;
-+	uint32_t DC_I2C_SEND_RESET;
-+	uint32_t DC_I2C_TRANSACTION_COUNT;
-+	uint32_t DC_I2C_DDC_SELECT;
-+	uint32_t DC_I2C_DDC1_PRESCALE;
-+	uint32_t DC_I2C_DDC1_THRESHOLD;
-+	uint32_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;
-+	uint32_t DC_I2C_SW_STOPPED_ON_NACK;
-+	uint32_t DC_I2C_SW_TIMEOUT;
-+	uint32_t DC_I2C_SW_ABORTED;
-+	uint32_t DC_I2C_SW_DONE;
-+	uint32_t DC_I2C_SW_STATUS;
-+	uint32_t DC_I2C_STOP_ON_NACK0;
-+	uint32_t DC_I2C_START0;
-+	uint32_t DC_I2C_RW0;
-+	uint32_t DC_I2C_STOP0;
-+	uint32_t DC_I2C_COUNT0;
-+	uint32_t DC_I2C_DATA_RW;
-+	uint32_t DC_I2C_DATA;
-+	uint32_t DC_I2C_INDEX;
-+	uint32_t DC_I2C_INDEX_WRITE;
-+	uint32_t XTAL_REF_DIV;
-+};
-+
-+struct dce110_i2c_hw_engine_registers {
-+	uint32_t SETUP;
-+	uint32_t SPEED;
-+	uint32_t DC_I2C_ARBITRATION;
-+	uint32_t DC_I2C_CONTROL;
-+	uint32_t DC_I2C_SW_STATUS;
-+	uint32_t DC_I2C_TRANSACTION0;
-+	uint32_t DC_I2C_TRANSACTION1;
-+	uint32_t DC_I2C_TRANSACTION2;
-+	uint32_t DC_I2C_TRANSACTION3;
-+	uint32_t DC_I2C_DATA;
-+	uint32_t MICROSECOND_TIME_BASE_DIV;
-+};
-+
-+struct i2c_hw_engine_dce110 {
-+	struct i2c_hw_engine base;
-+	const struct dce110_i2c_hw_engine_registers *regs;
-+	const struct dce110_i2c_hw_engine_shift *i2c_shift;
-+	const struct dce110_i2c_hw_engine_mask *i2c_mask;
-+	struct {
-+		uint32_t DC_I2C_DDCX_SETUP;
-+		uint32_t DC_I2C_DDCX_SPEED;
-+	} addr;
-+	uint32_t engine_id;
-+	/* expressed in kilohertz */
-+	uint32_t reference_frequency;
-+	/* number of bytes currently used in HW buffer */
-+	uint32_t buffer_used_bytes;
-+	/* number of bytes used for write transaction in HW buffer
-+	 * - this will be used as the index to read from*/
-+	uint32_t buffer_used_write;
-+	/* number of pending transactions (before GO) */
-+	uint32_t transaction_count;
-+	uint32_t engine_keep_power_up_count;
-+};
-+
-+struct i2c_hw_engine_dce110_create_arg {
-+	uint32_t engine_id;
-+	uint32_t reference_frequency;
-+	uint32_t default_speed;
-+	struct dc_context *ctx;
-+	const struct dce110_i2c_hw_engine_registers *regs;
-+	const struct dce110_i2c_hw_engine_shift *i2c_shift;
-+	const struct dce110_i2c_hw_engine_mask *i2c_mask;
-+};
-+
-+struct i2c_engine *dal_i2c_hw_engine_dce110_create(
-+	const struct i2c_hw_engine_dce110_create_arg *arg);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c.0130~	2017-12-14 06:39:58.433903580 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c	2017-12-14 06:39:58.433903580 +0100
-@@ -0,0 +1,160 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_sw_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_sw_engine_dce110.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_sw_engine *'
-+ * to 'struct i2c_sw_engine_dce110 *'
-+ */
-+#define FROM_I2C_SW_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_sw_engine_dce110, base)
-+/*
-+ * @brief
-+ * Cast 'struct i2c_engine *'
-+ * to 'struct i2c_sw_engine_dce80 *'
-+ */
-+#define FROM_I2C_ENGINE(ptr) \
-+	FROM_I2C_SW_ENGINE(container_of((ptr), struct i2c_sw_engine, base))
-+
-+/*
-+ * @brief
-+ * Cast 'struct engine *'
-+ * to 'struct i2c_sw_engine_dce80 *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-+
-+static void release_engine(
-+	struct engine *engine)
-+{
-+}
-+
-+static void destruct(
-+	struct i2c_sw_engine_dce110 *engine)
-+{
-+	dal_i2c_sw_engine_destruct(&engine->base);
-+}
-+
-+static void destroy(
-+	struct i2c_engine **engine)
-+{
-+	struct i2c_sw_engine_dce110 *sw_engine = FROM_I2C_ENGINE(*engine);
-+
-+	destruct(sw_engine);
-+
-+	kfree(sw_engine);
-+
-+	*engine = NULL;
-+}
-+
-+static bool acquire_engine(
-+	struct i2c_engine *engine,
-+	struct ddc *ddc_handle)
-+{
-+	return dal_i2caux_i2c_sw_engine_acquire_engine(engine, ddc_handle);
-+}
-+
-+static const struct i2c_engine_funcs i2c_engine_funcs = {
-+	.acquire_engine = acquire_engine,
-+	.destroy = destroy,
-+	.get_speed = dal_i2c_sw_engine_get_speed,
-+	.set_speed = dal_i2c_sw_engine_set_speed,
-+	.setup_engine = dal_i2c_engine_setup_i2c_engine,
-+	.submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
-+	.process_channel_reply = dal_i2c_engine_process_channel_reply,
-+	.get_channel_status = dal_i2c_sw_engine_get_channel_status,
-+};
-+
-+static const struct engine_funcs engine_funcs = {
-+	.release_engine = release_engine,
-+	.get_engine_type = dal_i2c_sw_engine_get_engine_type,
-+	.acquire = dal_i2c_engine_acquire,
-+	.submit_request = dal_i2c_sw_engine_submit_request,
-+};
-+
-+static void construct(
-+	struct i2c_sw_engine_dce110 *engine_dce110,
-+	const struct i2c_sw_engine_dce110_create_arg *arg_dce110)
-+{
-+	struct i2c_sw_engine_create_arg arg_base;
-+
-+	arg_base.ctx = arg_dce110->ctx;
-+	arg_base.default_speed = arg_dce110->default_speed;
-+
-+	dal_i2c_sw_engine_construct(&engine_dce110->base, &arg_base);
-+
-+	/*struct engine   struct engine_funcs*/
-+	engine_dce110->base.base.base.funcs = &engine_funcs;
-+	/*struct i2c_engine  struct i2c_engine_funcs*/
-+	engine_dce110->base.base.funcs = &i2c_engine_funcs;
-+	engine_dce110->base.default_speed = arg_dce110->default_speed;
-+	engine_dce110->engine_id = arg_dce110->engine_id;
-+}
-+
-+struct i2c_engine *dal_i2c_sw_engine_dce110_create(
-+	const struct i2c_sw_engine_dce110_create_arg *arg)
-+{
-+	struct i2c_sw_engine_dce110 *engine_dce110;
-+
-+	if (!arg) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	engine_dce110 = kzalloc(sizeof(struct i2c_sw_engine_dce110),
-+				GFP_KERNEL);
-+
-+	if (!engine_dce110) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	construct(engine_dce110, arg);
-+	return &engine_dce110->base.base;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.h.0130~	2017-12-14 06:39:58.433903580 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.h	2017-12-14 06:39:58.433903580 +0100
-@@ -0,0 +1,43 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_SW_ENGINE_DCE110_H__
-+#define __DAL_I2C_SW_ENGINE_DCE110_H__
-+
-+struct i2c_sw_engine_dce110 {
-+	struct i2c_sw_engine base;
-+	uint32_t engine_id;
-+};
-+
-+struct i2c_sw_engine_dce110_create_arg {
-+	uint32_t engine_id;
-+	uint32_t default_speed;
-+	struct dc_context *ctx;
-+};
-+
-+struct i2c_engine *dal_i2c_sw_engine_dce110_create(
-+	const struct i2c_sw_engine_dce110_create_arg *arg);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c.0130~	2017-12-14 06:39:58.433903580 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c	2017-12-14 06:39:58.433903580 +0100
-@@ -0,0 +1,128 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/i2caux_interface.h"
-+#include "../i2caux.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_sw_engine.h"
-+#include "../i2c_hw_engine.h"
-+
-+#include "../dce110/i2caux_dce110.h"
-+#include "i2caux_dce112.h"
-+
-+#include "../dce110/aux_engine_dce110.h"
-+
-+#include "../dce110/i2c_hw_engine_dce110.h"
-+
-+#include "dce/dce_11_2_d.h"
-+#include "dce/dce_11_2_sh_mask.h"
-+
-+/* set register offset */
-+#define SR(reg_name)\
-+	.reg_name = mm ## reg_name
-+
-+/* set register offset with instance */
-+#define SRI(reg_name, block, id)\
-+	.reg_name = mm ## block ## id ## _ ## reg_name
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	AUX_COMMON_REG_LIST(id), \
-+	.AUX_RESET_MASK = AUX_CONTROL__AUX_RESET_MASK \
-+}
-+
-+#define hw_engine_regs(id)\
-+{\
-+		I2C_HW_ENGINE_COMMON_REG_LIST(id) \
-+}
-+
-+static const struct dce110_aux_registers dce112_aux_regs[] = {
-+		aux_regs(0),
-+		aux_regs(1),
-+		aux_regs(2),
-+		aux_regs(3),
-+		aux_regs(4),
-+		aux_regs(5),
-+};
-+
-+static const struct dce110_i2c_hw_engine_registers dce112_hw_engine_regs[] = {
-+		hw_engine_regs(1),
-+		hw_engine_regs(2),
-+		hw_engine_regs(3),
-+		hw_engine_regs(4),
-+		hw_engine_regs(5),
-+		hw_engine_regs(6)
-+};
-+
-+static const struct dce110_i2c_hw_engine_shift i2c_shift = {
-+		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-+};
-+
-+static const struct dce110_i2c_hw_engine_mask i2c_mask = {
-+		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
-+};
-+
-+static void construct(
-+	struct i2caux_dce110 *i2caux_dce110,
-+	struct dc_context *ctx)
-+{
-+	dal_i2caux_dce110_construct(i2caux_dce110,
-+				    ctx,
-+				    dce112_aux_regs,
-+				    dce112_hw_engine_regs,
-+				    &i2c_shift,
-+				    &i2c_mask);
-+}
-+
-+/*
-+ * dal_i2caux_dce110_create
-+ *
-+ * @brief
-+ * public interface to allocate memory for DCE11 I2CAUX
-+ *
-+ * @param
-+ * struct adapter_service *as - [in]
-+ * struct dc_context *ctx - [in]
-+ *
-+ * @return
-+ * pointer to the base struct of DCE11 I2CAUX
-+ */
-+struct i2caux *dal_i2caux_dce112_create(
-+	struct dc_context *ctx)
-+{
-+	struct i2caux_dce110 *i2caux_dce110 =
-+		kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
-+
-+	if (!i2caux_dce110) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	construct(i2caux_dce110, ctx);
-+	return &i2caux_dce110->base;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.h.0130~	2017-12-14 06:39:58.433903580 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.h	2017-12-14 06:39:58.433903580 +0100
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_AUX_DCE112_H__
-+#define __DAL_I2C_AUX_DCE112_H__
-+
-+struct i2caux *dal_i2caux_dce112_create(
-+	struct dc_context *ctx);
-+
-+#endif /* __DAL_I2C_AUX_DCE112_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c.0130~	2017-12-14 06:39:58.433903580 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c	2017-12-14 06:39:58.433903580 +0100
-@@ -0,0 +1,118 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/i2caux_interface.h"
-+#include "../i2caux.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_sw_engine.h"
-+#include "../i2c_hw_engine.h"
-+
-+#include "../dce110/i2c_hw_engine_dce110.h"
-+#include "../dce110/aux_engine_dce110.h"
-+#include "../dce110/i2caux_dce110.h"
-+
-+#include "vega10/DC/dce_12_0_offset.h"
-+#include "vega10/DC/dce_12_0_sh_mask.h"
-+#include "vega10/soc15ip.h"
-+
-+/* begin *********************
-+ * macros to expend register list macro defined in HW object header file */
-+
-+#define BASE_INNER(seg) \
-+	DCE_BASE__INST0_SEG ## seg
-+
-+/* compile time expand base address. */
-+#define BASE(seg) \
-+	BASE_INNER(seg)
-+
-+#define SR(reg_name)\
-+		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
-+					mm ## reg_name
-+
-+#define SRI(reg_name, block, id)\
-+	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-+					mm ## block ## id ## _ ## reg_name
-+/* macros to expend register list macro defined in HW object header file
-+ * end *********************/
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	AUX_COMMON_REG_LIST(id), \
-+	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK \
-+}
-+
-+static const struct dce110_aux_registers dce120_aux_regs[] = {
-+		aux_regs(0),
-+		aux_regs(1),
-+		aux_regs(2),
-+		aux_regs(3),
-+		aux_regs(4),
-+		aux_regs(5),
-+};
-+
-+#define hw_engine_regs(id)\
-+{\
-+		I2C_HW_ENGINE_COMMON_REG_LIST(id) \
-+}
-+
-+static const struct dce110_i2c_hw_engine_registers dce120_hw_engine_regs[] = {
-+		hw_engine_regs(1),
-+		hw_engine_regs(2),
-+		hw_engine_regs(3),
-+		hw_engine_regs(4),
-+		hw_engine_regs(5),
-+		hw_engine_regs(6)
-+};
-+
-+static const struct dce110_i2c_hw_engine_shift i2c_shift = {
-+		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-+};
-+
-+static const struct dce110_i2c_hw_engine_mask i2c_mask = {
-+		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
-+};
-+
-+struct i2caux *dal_i2caux_dce120_create(
-+	struct dc_context *ctx)
-+{
-+	struct i2caux_dce110 *i2caux_dce110 =
-+		kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
-+
-+	if (!i2caux_dce110) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	dal_i2caux_dce110_construct(i2caux_dce110,
-+				    ctx,
-+				    dce120_aux_regs,
-+				    dce120_hw_engine_regs,
-+				    &i2c_shift,
-+				    &i2c_mask);
-+	return &i2caux_dce110->base;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.h.0130~	2017-12-14 06:39:58.433903580 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.h	2017-12-14 06:39:58.433903580 +0100
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_AUX_DCE120_H__
-+#define __DAL_I2C_AUX_DCE120_H__
-+
-+struct i2caux *dal_i2caux_dce120_create(
-+	struct dc_context *ctx);
-+
-+#endif /* __DAL_I2C_AUX_DCE120_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c.0130~	2017-12-14 06:39:58.433903580 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c	2017-12-14 06:39:58.433903580 +0100
-@@ -0,0 +1,284 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "../i2caux.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2caux_dce80.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_sw_engine.h"
-+#include "i2c_sw_engine_dce80.h"
-+#include "../i2c_hw_engine.h"
-+#include "i2c_hw_engine_dce80.h"
-+#include "../i2c_generic_hw_engine.h"
-+#include "../aux_engine.h"
-+
-+
-+#include "../dce110/aux_engine_dce110.h"
-+#include "../dce110/i2caux_dce110.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+
-+/* set register offset */
-+#define SR(reg_name)\
-+	.reg_name = mm ## reg_name
-+
-+/* set register offset with instance */
-+#define SRI(reg_name, block, id)\
-+	.reg_name = mm ## block ## id ## _ ## reg_name
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	AUX_COMMON_REG_LIST(id), \
-+	.AUX_RESET_MASK = 0 \
-+}
-+
-+static const struct dce110_aux_registers dce80_aux_regs[] = {
-+		aux_regs(0),
-+		aux_regs(1),
-+		aux_regs(2),
-+		aux_regs(3),
-+		aux_regs(4),
-+		aux_regs(5)
-+};
-+
-+/*
-+ * This unit
-+ */
-+
-+#define FROM_I2C_AUX(ptr) \
-+	container_of((ptr), struct i2caux_dce80, base)
-+
-+static void destruct(
-+	struct i2caux_dce80 *i2caux_dce80)
-+{
-+	dal_i2caux_destruct(&i2caux_dce80->base);
-+}
-+
-+static void destroy(
-+	struct i2caux **i2c_engine)
-+{
-+	struct i2caux_dce80 *i2caux_dce80 = FROM_I2C_AUX(*i2c_engine);
-+
-+	destruct(i2caux_dce80);
-+
-+	kfree(i2caux_dce80);
-+
-+	*i2c_engine = NULL;
-+}
-+
-+static struct i2c_engine *acquire_i2c_hw_engine(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc)
-+{
-+	struct i2caux_dce80 *i2caux_dce80 = FROM_I2C_AUX(i2caux);
-+
-+	struct i2c_engine *engine = NULL;
-+	bool non_generic;
-+
-+	if (!ddc)
-+		return NULL;
-+
-+	if (ddc->hw_info.hw_supported) {
-+		enum gpio_ddc_line line = dal_ddc_get_line(ddc);
-+
-+		if (line < GPIO_DDC_LINE_COUNT) {
-+			non_generic = true;
-+			engine = i2caux->i2c_hw_engines[line];
-+		}
-+	}
-+
-+	if (!engine) {
-+		non_generic = false;
-+		engine = i2caux->i2c_generic_hw_engine;
-+	}
-+
-+	if (!engine)
-+		return NULL;
-+
-+	if (non_generic) {
-+		if (!i2caux_dce80->i2c_hw_buffer_in_use &&
-+			engine->base.funcs->acquire(&engine->base, ddc)) {
-+			i2caux_dce80->i2c_hw_buffer_in_use = true;
-+			return engine;
-+		}
-+	} else {
-+		if (engine->base.funcs->acquire(&engine->base, ddc))
-+			return engine;
-+	}
-+
-+	return NULL;
-+}
-+
-+static void release_engine(
-+	struct i2caux *i2caux,
-+	struct engine *engine)
-+{
-+	if (engine->funcs->get_engine_type(engine) ==
-+		I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
-+		FROM_I2C_AUX(i2caux)->i2c_hw_buffer_in_use = false;
-+
-+	dal_i2caux_release_engine(i2caux, engine);
-+}
-+
-+static const enum gpio_ddc_line hw_ddc_lines[] = {
-+	GPIO_DDC_LINE_DDC1,
-+	GPIO_DDC_LINE_DDC2,
-+	GPIO_DDC_LINE_DDC3,
-+	GPIO_DDC_LINE_DDC4,
-+	GPIO_DDC_LINE_DDC5,
-+	GPIO_DDC_LINE_DDC6,
-+	GPIO_DDC_LINE_DDC_VGA
-+};
-+
-+static const enum gpio_ddc_line hw_aux_lines[] = {
-+	GPIO_DDC_LINE_DDC1,
-+	GPIO_DDC_LINE_DDC2,
-+	GPIO_DDC_LINE_DDC3,
-+	GPIO_DDC_LINE_DDC4,
-+	GPIO_DDC_LINE_DDC5,
-+	GPIO_DDC_LINE_DDC6
-+};
-+
-+static const struct i2caux_funcs i2caux_funcs = {
-+	.destroy = destroy,
-+	.acquire_i2c_hw_engine = acquire_i2c_hw_engine,
-+	.release_engine = release_engine,
-+	.acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
-+	.acquire_aux_engine = dal_i2caux_acquire_aux_engine,
-+};
-+
-+static void construct(
-+	struct i2caux_dce80 *i2caux_dce80,
-+	struct dc_context *ctx)
-+{
-+	/* Entire family have I2C engine reference clock frequency
-+	 * changed from XTALIN (27) to XTALIN/2 (13.5) */
-+
-+	struct i2caux *base = &i2caux_dce80->base;
-+
-+	uint32_t reference_frequency =
-+		dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
-+
-+	/*bool use_i2c_sw_engine = dal_adapter_service_is_feature_supported(as,
-+		FEATURE_RESTORE_USAGE_I2C_SW_ENGINE);*/
-+
-+	/* Use SWI2C for dce8 currently, sicne we have bug with hwi2c */
-+	bool use_i2c_sw_engine = true;
-+
-+	uint32_t i;
-+
-+	dal_i2caux_construct(base, ctx);
-+
-+	i2caux_dce80->base.funcs = &i2caux_funcs;
-+	i2caux_dce80->i2c_hw_buffer_in_use = false;
-+
-+	/* Create I2C HW engines (HW + SW pairs)
-+	 * for all lines which has assisted HW DDC
-+	 * 'i' (loop counter) used as DDC/AUX engine_id */
-+
-+	i = 0;
-+
-+	do {
-+		enum gpio_ddc_line line_id = hw_ddc_lines[i];
-+
-+		struct i2c_hw_engine_dce80_create_arg hw_arg;
-+
-+		if (use_i2c_sw_engine) {
-+			struct i2c_sw_engine_dce80_create_arg sw_arg;
-+
-+			sw_arg.engine_id = i;
-+			sw_arg.default_speed = base->default_i2c_sw_speed;
-+			sw_arg.ctx = ctx;
-+			base->i2c_sw_engines[line_id] =
-+				dal_i2c_sw_engine_dce80_create(&sw_arg);
-+		}
-+
-+		hw_arg.engine_id = i;
-+		hw_arg.reference_frequency = reference_frequency;
-+		hw_arg.default_speed = base->default_i2c_hw_speed;
-+		hw_arg.ctx = ctx;
-+
-+		base->i2c_hw_engines[line_id] =
-+			dal_i2c_hw_engine_dce80_create(&hw_arg);
-+
-+		++i;
-+	} while (i < ARRAY_SIZE(hw_ddc_lines));
-+
-+	/* Create AUX engines for all lines which has assisted HW AUX
-+	 * 'i' (loop counter) used as DDC/AUX engine_id */
-+
-+	i = 0;
-+
-+	do {
-+		enum gpio_ddc_line line_id = hw_aux_lines[i];
-+
-+		struct aux_engine_dce110_init_data arg;
-+
-+		arg.engine_id = i;
-+		arg.timeout_period = base->aux_timeout_period;
-+		arg.ctx = ctx;
-+		arg.regs = &dce80_aux_regs[i];
-+
-+		base->aux_engines[line_id] =
-+			dal_aux_engine_dce110_create(&arg);
-+
-+		++i;
-+	} while (i < ARRAY_SIZE(hw_aux_lines));
-+
-+	/* TODO Generic I2C SW and HW */
-+}
-+
-+struct i2caux *dal_i2caux_dce80_create(
-+	struct dc_context *ctx)
-+{
-+	struct i2caux_dce80 *i2caux_dce80 =
-+		kzalloc(sizeof(struct i2caux_dce80), GFP_KERNEL);
-+
-+	if (!i2caux_dce80) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	construct(i2caux_dce80, ctx);
-+	return &i2caux_dce80->base;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.h.0130~	2017-12-14 06:39:58.433903580 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.h	2017-12-14 06:39:58.433903580 +0100
-@@ -0,0 +1,38 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_AUX_DCE80_H__
-+#define __DAL_I2C_AUX_DCE80_H__
-+
-+struct i2caux_dce80 {
-+	struct i2caux base;
-+	/* indicate the I2C HW circular buffer is in use */
-+	bool i2c_hw_buffer_in_use;
-+};
-+
-+struct i2caux *dal_i2caux_dce80_create(
-+	struct dc_context *ctx);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c.0130~	2017-12-14 06:39:58.434903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c	2017-12-14 06:39:58.434903581 +0100
-@@ -0,0 +1,875 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_hw_engine.h"
-+#include "../i2c_generic_hw_engine.h"
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_hw_engine_dce80.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+/*
-+ * This unit
-+ */
-+
-+enum dc_i2c_status {
-+	DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
-+	DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
-+	DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
-+};
-+
-+enum dc_i2c_arbitration {
-+	DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
-+	DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
-+};
-+
-+enum {
-+	/* No timeout in HW
-+	 * (timeout implemented in SW by querying status) */
-+	I2C_SETUP_TIME_LIMIT = 255,
-+	I2C_HW_BUFFER_SIZE = 144
-+};
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_hw_engine *'
-+ * to 'struct i2c_hw_engine_dce80 *'
-+ */
-+#define FROM_I2C_HW_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_hw_engine_dce80, base)
-+
-+/*
-+ * @brief
-+ * Cast pointer to 'struct i2c_engine *'
-+ * to pointer to 'struct i2c_hw_engine_dce80 *'
-+ */
-+#define FROM_I2C_ENGINE(ptr) \
-+	FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
-+
-+/*
-+ * @brief
-+ * Cast pointer to 'struct engine *'
-+ * to 'pointer to struct i2c_hw_engine_dce80 *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-+
-+static void disable_i2c_hw_engine(
-+	struct i2c_hw_engine_dce80 *engine)
-+{
-+	const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
-+	uint32_t value = 0;
-+
-+	struct dc_context *ctx = NULL;
-+
-+	ctx = engine->base.base.base.ctx;
-+
-+	value = dm_read_reg(ctx, addr);
-+
-+	set_reg_field_value(
-+		value,
-+		0,
-+		DC_I2C_DDC1_SETUP,
-+		DC_I2C_DDC1_ENABLE);
-+
-+	dm_write_reg(ctx, addr, value);
-+}
-+
-+static void release_engine(
-+	struct engine *engine)
-+{
-+	struct i2c_hw_engine_dce80 *hw_engine = FROM_ENGINE(engine);
-+
-+	struct i2c_engine *base = NULL;
-+	bool safe_to_reset;
-+	uint32_t value = 0;
-+
-+	base = &hw_engine->base.base;
-+
-+	/* Restore original HW engine speed */
-+
-+	base->funcs->set_speed(base, hw_engine->base.original_speed);
-+
-+	/* Release I2C */
-+	{
-+		value = dm_read_reg(engine->ctx, mmDC_I2C_ARBITRATION);
-+
-+		set_reg_field_value(
-+				value,
-+				1,
-+				DC_I2C_ARBITRATION,
-+				DC_I2C_SW_DONE_USING_I2C_REG);
-+
-+		dm_write_reg(engine->ctx, mmDC_I2C_ARBITRATION, value);
-+	}
-+
-+	/* Reset HW engine */
-+	{
-+		uint32_t i2c_sw_status = 0;
-+
-+		value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-+
-+		i2c_sw_status = get_reg_field_value(
-+				value,
-+				DC_I2C_SW_STATUS,
-+				DC_I2C_SW_STATUS);
-+		/* if used by SW, safe to reset */
-+		safe_to_reset = (i2c_sw_status == 1);
-+	}
-+	{
-+		value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
-+
-+		if (safe_to_reset)
-+			set_reg_field_value(
-+				value,
-+				1,
-+				DC_I2C_CONTROL,
-+				DC_I2C_SOFT_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SW_STATUS_RESET);
-+
-+		dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
-+	}
-+
-+	/* HW I2c engine - clock gating feature */
-+	if (!hw_engine->engine_keep_power_up_count)
-+		disable_i2c_hw_engine(hw_engine);
-+}
-+
-+static void destruct(
-+	struct i2c_hw_engine_dce80 *engine)
-+{
-+	dal_i2c_hw_engine_destruct(&engine->base);
-+}
-+
-+static void destroy(
-+	struct i2c_engine **i2c_engine)
-+{
-+	struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(*i2c_engine);
-+
-+	destruct(engine);
-+
-+	kfree(engine);
-+
-+	*i2c_engine = NULL;
-+}
-+
-+static bool setup_engine(
-+	struct i2c_engine *i2c_engine)
-+{
-+	uint32_t value = 0;
-+	struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
-+
-+	/* Program pin select */
-+	{
-+		const uint32_t addr = mmDC_I2C_CONTROL;
-+
-+		value = dm_read_reg(i2c_engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_GO);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SOFT_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SEND_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SW_STATUS_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_TRANSACTION_COUNT);
-+
-+		set_reg_field_value(
-+			value,
-+			engine->engine_id,
-+			DC_I2C_CONTROL,
-+			DC_I2C_DDC_SELECT);
-+
-+		dm_write_reg(i2c_engine->base.ctx, addr, value);
-+	}
-+
-+	/* Program time limit */
-+	{
-+		const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
-+
-+		value = dm_read_reg(i2c_engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			I2C_SETUP_TIME_LIMIT,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_TIME_LIMIT);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_ENABLE);
-+
-+		dm_write_reg(i2c_engine->base.ctx, addr, value);
-+	}
-+
-+	/* Program HW priority
-+	 * set to High - interrupt software I2C at any time
-+	 * Enable restart of SW I2C that was interrupted by HW
-+	 * disable queuing of software while I2C is in use by HW */
-+	{
-+		value = dm_read_reg(i2c_engine->base.ctx,
-+				mmDC_I2C_ARBITRATION);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_ARBITRATION,
-+			DC_I2C_NO_QUEUED_SW_GO);
-+
-+		set_reg_field_value(
-+			value,
-+			DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
-+			DC_I2C_ARBITRATION,
-+			DC_I2C_SW_PRIORITY);
-+
-+		dm_write_reg(i2c_engine->base.ctx,
-+				mmDC_I2C_ARBITRATION, value);
-+	}
-+
-+	return true;
-+}
-+
-+static uint32_t get_speed(
-+	const struct i2c_engine *i2c_engine)
-+{
-+	const struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
-+
-+	const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
-+
-+	uint32_t pre_scale = 0;
-+
-+	uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
-+
-+	pre_scale = get_reg_field_value(
-+			value,
-+			DC_I2C_DDC1_SPEED,
-+			DC_I2C_DDC1_PRESCALE);
-+
-+	/* [anaumov] it seems following is unnecessary */
-+	/*ASSERT(value.bits.DC_I2C_DDC1_PRESCALE);*/
-+
-+	return pre_scale ?
-+		engine->reference_frequency / pre_scale :
-+		engine->base.default_speed;
-+}
-+
-+static void set_speed(
-+	struct i2c_engine *i2c_engine,
-+	uint32_t speed)
-+{
-+	struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
-+
-+	if (speed) {
-+		const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
-+
-+		uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			engine->reference_frequency / speed,
-+			DC_I2C_DDC1_SPEED,
-+			DC_I2C_DDC1_PRESCALE);
-+
-+		set_reg_field_value(
-+			value,
-+			2,
-+			DC_I2C_DDC1_SPEED,
-+			DC_I2C_DDC1_THRESHOLD);
-+
-+		dm_write_reg(i2c_engine->base.ctx, addr, value);
-+	}
-+}
-+
-+static inline void reset_hw_engine(struct engine *engine)
-+{
-+	uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DC_I2C_CONTROL,
-+		DC_I2C_SOFT_RESET);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DC_I2C_CONTROL,
-+		DC_I2C_SW_STATUS_RESET);
-+
-+	dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
-+}
-+
-+static bool is_hw_busy(struct engine *engine)
-+{
-+	uint32_t i2c_sw_status = 0;
-+
-+	uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-+
-+	i2c_sw_status = get_reg_field_value(
-+			value,
-+			DC_I2C_SW_STATUS,
-+			DC_I2C_SW_STATUS);
-+
-+	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
-+		return false;
-+
-+	reset_hw_engine(engine);
-+
-+	value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-+
-+	i2c_sw_status = get_reg_field_value(
-+			value,
-+			DC_I2C_SW_STATUS,
-+			DC_I2C_SW_STATUS);
-+
-+	return i2c_sw_status != DC_I2C_STATUS__DC_I2C_STATUS_IDLE;
-+}
-+
-+/*
-+ * @brief
-+ * DC_GPIO_DDC MM register offsets
-+ */
-+static const uint32_t transaction_addr[] = {
-+	mmDC_I2C_TRANSACTION0,
-+	mmDC_I2C_TRANSACTION1,
-+	mmDC_I2C_TRANSACTION2,
-+	mmDC_I2C_TRANSACTION3
-+};
-+
-+static bool process_transaction(
-+	struct i2c_hw_engine_dce80 *engine,
-+	struct i2c_request_transaction_data *request)
-+{
-+	uint32_t length = request->length;
-+	uint8_t *buffer = request->data;
-+
-+	bool last_transaction = false;
-+	uint32_t value = 0;
-+
-+	struct dc_context *ctx = NULL;
-+
-+	ctx = engine->base.base.base.ctx;
-+
-+	{
-+		const uint32_t addr =
-+			transaction_addr[engine->transaction_count];
-+
-+		value = dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_TRANSACTION0,
-+			DC_I2C_STOP_ON_NACK0);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_TRANSACTION0,
-+			DC_I2C_START0);
-+
-+		if ((engine->transaction_count == 3) ||
-+		(request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
-+		(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-+
-+			set_reg_field_value(
-+				value,
-+				1,
-+				DC_I2C_TRANSACTION0,
-+				DC_I2C_STOP0);
-+
-+			last_transaction = true;
-+		} else
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DC_I2C_TRANSACTION0,
-+				DC_I2C_STOP0);
-+
-+		set_reg_field_value(
-+			value,
-+			(0 != (request->action &
-+					I2CAUX_TRANSACTION_ACTION_I2C_READ)),
-+			DC_I2C_TRANSACTION0,
-+			DC_I2C_RW0);
-+
-+		set_reg_field_value(
-+			value,
-+			length,
-+			DC_I2C_TRANSACTION0,
-+			DC_I2C_COUNT0);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+
-+	/* Write the I2C address and I2C data
-+	 * into the hardware circular buffer, one byte per entry.
-+	 * As an example, the 7-bit I2C slave address for CRT monitor
-+	 * for reading DDC/EDID information is 0b1010001.
-+	 * For an I2C send operation, the LSB must be programmed to 0;
-+	 * for I2C receive operation, the LSB must be programmed to 1. */
-+
-+	{
-+		value = 0;
-+
-+		set_reg_field_value(
-+			value,
-+			false,
-+			DC_I2C_DATA,
-+			DC_I2C_DATA_RW);
-+
-+		set_reg_field_value(
-+			value,
-+			request->address,
-+			DC_I2C_DATA,
-+			DC_I2C_DATA);
-+
-+		if (engine->transaction_count == 0) {
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DC_I2C_DATA,
-+				DC_I2C_INDEX);
-+
-+			/*enable index write*/
-+			set_reg_field_value(
-+				value,
-+				1,
-+				DC_I2C_DATA,
-+				DC_I2C_INDEX_WRITE);
-+		}
-+
-+		dm_write_reg(ctx, mmDC_I2C_DATA, value);
-+
-+		if (!(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-+
-+			set_reg_field_value(
-+				value,
-+				0,
-+				DC_I2C_DATA,
-+				DC_I2C_INDEX_WRITE);
-+
-+			while (length) {
-+
-+				set_reg_field_value(
-+					value,
-+					*buffer++,
-+					DC_I2C_DATA,
-+					DC_I2C_DATA);
-+
-+				dm_write_reg(ctx, mmDC_I2C_DATA, value);
-+				--length;
-+			}
-+		}
-+	}
-+
-+	++engine->transaction_count;
-+	engine->buffer_used_bytes += length + 1;
-+
-+	return last_transaction;
-+}
-+
-+static void execute_transaction(
-+	struct i2c_hw_engine_dce80 *engine)
-+{
-+	uint32_t value = 0;
-+	struct dc_context *ctx = NULL;
-+
-+	ctx = engine->base.base.base.ctx;
-+
-+	{
-+		const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
-+
-+		value = dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_DATA_DRIVE_EN);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_CLK_DRIVE_EN);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_DATA_DRIVE_SEL);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_INTRA_TRANSACTION_DELAY);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_DDC1_SETUP,
-+			DC_I2C_DDC1_INTRA_BYTE_DELAY);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+
-+	{
-+		const uint32_t addr = mmDC_I2C_CONTROL;
-+
-+		value = dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SOFT_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SW_STATUS_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_SEND_RESET);
-+
-+		set_reg_field_value(
-+			value,
-+			0,
-+			DC_I2C_CONTROL,
-+			DC_I2C_GO);
-+
-+		set_reg_field_value(
-+			value,
-+			engine->transaction_count - 1,
-+			DC_I2C_CONTROL,
-+			DC_I2C_TRANSACTION_COUNT);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+
-+	/* start I2C transfer */
-+	{
-+		const uint32_t addr = mmDC_I2C_CONTROL;
-+
-+		value	= dm_read_reg(ctx, addr);
-+
-+		set_reg_field_value(
-+			value,
-+			1,
-+			DC_I2C_CONTROL,
-+			DC_I2C_GO);
-+
-+		dm_write_reg(ctx, addr, value);
-+	}
-+
-+	/* all transactions were executed and HW buffer became empty
-+	 * (even though it actually happens when status becomes DONE) */
-+	engine->transaction_count = 0;
-+	engine->buffer_used_bytes = 0;
-+}
-+
-+static void submit_channel_request(
-+	struct i2c_engine *engine,
-+	struct i2c_request_transaction_data *request)
-+{
-+	request->status = I2C_CHANNEL_OPERATION_SUCCEEDED;
-+
-+	if (!process_transaction(FROM_I2C_ENGINE(engine), request))
-+		return;
-+
-+	if (is_hw_busy(&engine->base)) {
-+		request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
-+		return;
-+	}
-+
-+	execute_transaction(FROM_I2C_ENGINE(engine));
-+}
-+
-+static void process_channel_reply(
-+	struct i2c_engine *engine,
-+	struct i2c_reply_transaction_data *reply)
-+{
-+	uint32_t length = reply->length;
-+	uint8_t *buffer = reply->data;
-+
-+	uint32_t value = 0;
-+
-+	/*set index*/
-+	set_reg_field_value(
-+		value,
-+		length - 1,
-+		DC_I2C_DATA,
-+		DC_I2C_INDEX);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DC_I2C_DATA,
-+		DC_I2C_DATA_RW);
-+
-+	set_reg_field_value(
-+		value,
-+		1,
-+		DC_I2C_DATA,
-+		DC_I2C_INDEX_WRITE);
-+
-+	dm_write_reg(engine->base.ctx, mmDC_I2C_DATA, value);
-+
-+	while (length) {
-+		/* after reading the status,
-+		 * if the I2C operation executed successfully
-+		 * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
-+		 * should read data bytes from I2C circular data buffer */
-+
-+		value = dm_read_reg(engine->base.ctx, mmDC_I2C_DATA);
-+
-+		*buffer++ = get_reg_field_value(
-+				value,
-+				DC_I2C_DATA,
-+				DC_I2C_DATA);
-+
-+		--length;
-+	}
-+}
-+
-+static enum i2c_channel_operation_result get_channel_status(
-+	struct i2c_engine *engine,
-+	uint8_t *returned_bytes)
-+{
-+	uint32_t i2c_sw_status = 0;
-+	uint32_t value = dm_read_reg(engine->base.ctx, mmDC_I2C_SW_STATUS);
-+
-+	i2c_sw_status = get_reg_field_value(
-+			value,
-+			DC_I2C_SW_STATUS,
-+			DC_I2C_SW_STATUS);
-+
-+	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
-+		return I2C_CHANNEL_OPERATION_ENGINE_BUSY;
-+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK)
-+		return I2C_CHANNEL_OPERATION_NO_RESPONSE;
-+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK)
-+		return I2C_CHANNEL_OPERATION_TIMEOUT;
-+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK)
-+		return I2C_CHANNEL_OPERATION_FAILED;
-+	else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK)
-+		return I2C_CHANNEL_OPERATION_SUCCEEDED;
-+
-+	/*
-+	 * this is the case when HW used for communication, I2C_SW_STATUS
-+	 * could be zero
-+	 */
-+	return I2C_CHANNEL_OPERATION_SUCCEEDED;
-+}
-+
-+static uint32_t get_hw_buffer_available_size(
-+	const struct i2c_hw_engine *engine)
-+{
-+	return I2C_HW_BUFFER_SIZE -
-+		FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes;
-+}
-+
-+static uint32_t get_transaction_timeout(
-+	const struct i2c_hw_engine *engine,
-+	uint32_t length)
-+{
-+	uint32_t speed = engine->base.funcs->get_speed(&engine->base);
-+
-+	uint32_t period_timeout;
-+	uint32_t num_of_clock_stretches;
-+
-+	if (!speed)
-+		return 0;
-+
-+	period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed;
-+
-+	num_of_clock_stretches = 1 + (length << 3) + 1;
-+	num_of_clock_stretches +=
-+		(FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes << 3) +
-+		(FROM_I2C_HW_ENGINE(engine)->transaction_count << 1);
-+
-+	return period_timeout * num_of_clock_stretches;
-+}
-+
-+/*
-+ * @brief
-+ * DC_I2C_DDC1_SETUP MM register offsets
-+ *
-+ * @note
-+ * The indices of this offset array are DDC engine IDs
-+ */
-+static const int32_t ddc_setup_offset[] = {
-+
-+	mmDC_I2C_DDC1_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 1 */
-+	mmDC_I2C_DDC2_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 2 */
-+	mmDC_I2C_DDC3_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 3 */
-+	mmDC_I2C_DDC4_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 4 */
-+	mmDC_I2C_DDC5_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 5 */
-+	mmDC_I2C_DDC6_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 6 */
-+	mmDC_I2C_DDCVGA_SETUP - mmDC_I2C_DDC1_SETUP /* DDC Engine 7 */
-+};
-+
-+/*
-+ * @brief
-+ * DC_I2C_DDC1_SPEED MM register offsets
-+ *
-+ * @note
-+ * The indices of this offset array are DDC engine IDs
-+ */
-+static const int32_t ddc_speed_offset[] = {
-+	mmDC_I2C_DDC1_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 1 */
-+	mmDC_I2C_DDC2_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 2 */
-+	mmDC_I2C_DDC3_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 3 */
-+	mmDC_I2C_DDC4_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 4 */
-+	mmDC_I2C_DDC5_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 5 */
-+	mmDC_I2C_DDC6_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 6 */
-+	mmDC_I2C_DDCVGA_SPEED - mmDC_I2C_DDC1_SPEED /* DDC Engine 7 */
-+};
-+
-+static const struct i2c_engine_funcs i2c_engine_funcs = {
-+	.destroy = destroy,
-+	.get_speed = get_speed,
-+	.set_speed = set_speed,
-+	.setup_engine = setup_engine,
-+	.submit_channel_request = submit_channel_request,
-+	.process_channel_reply = process_channel_reply,
-+	.get_channel_status = get_channel_status,
-+	.acquire_engine = dal_i2c_hw_engine_acquire_engine,
-+};
-+
-+static const struct engine_funcs engine_funcs = {
-+	.release_engine = release_engine,
-+	.get_engine_type = dal_i2c_hw_engine_get_engine_type,
-+	.acquire = dal_i2c_engine_acquire,
-+	.submit_request = dal_i2c_hw_engine_submit_request,
-+};
-+
-+static const struct i2c_hw_engine_funcs i2c_hw_engine_funcs = {
-+	.get_hw_buffer_available_size =
-+		get_hw_buffer_available_size,
-+	.get_transaction_timeout =
-+		get_transaction_timeout,
-+	.wait_on_operation_result =
-+		dal_i2c_hw_engine_wait_on_operation_result,
-+};
-+
-+static void construct(
-+	struct i2c_hw_engine_dce80 *engine,
-+	const struct i2c_hw_engine_dce80_create_arg *arg)
-+{
-+	dal_i2c_hw_engine_construct(&engine->base, arg->ctx);
-+
-+	engine->base.base.base.funcs = &engine_funcs;
-+	engine->base.base.funcs = &i2c_engine_funcs;
-+	engine->base.funcs = &i2c_hw_engine_funcs;
-+	engine->base.default_speed = arg->default_speed;
-+	engine->addr.DC_I2C_DDCX_SETUP =
-+		mmDC_I2C_DDC1_SETUP + ddc_setup_offset[arg->engine_id];
-+	engine->addr.DC_I2C_DDCX_SPEED =
-+		mmDC_I2C_DDC1_SPEED + ddc_speed_offset[arg->engine_id];
-+
-+	engine->engine_id = arg->engine_id;
-+	engine->reference_frequency = arg->reference_frequency;
-+	engine->buffer_used_bytes = 0;
-+	engine->transaction_count = 0;
-+	engine->engine_keep_power_up_count = 1;
-+}
-+
-+struct i2c_engine *dal_i2c_hw_engine_dce80_create(
-+	const struct i2c_hw_engine_dce80_create_arg *arg)
-+{
-+	struct i2c_hw_engine_dce80 *engine;
-+
-+	if (!arg) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	if ((arg->engine_id >= sizeof(ddc_setup_offset) / sizeof(int32_t)) ||
-+	    (arg->engine_id >= sizeof(ddc_speed_offset) / sizeof(int32_t)) ||
-+	    !arg->reference_frequency) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	engine = kzalloc(sizeof(struct i2c_hw_engine_dce80), GFP_KERNEL);
-+
-+	if (!engine) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	construct(engine, arg);
-+	return &engine->base.base;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.h.0130~	2017-12-14 06:39:58.434903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.h	2017-12-14 06:39:58.434903581 +0100
-@@ -0,0 +1,54 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_HW_ENGINE_DCE80_H__
-+#define __DAL_I2C_HW_ENGINE_DCE80_H__
-+
-+struct i2c_hw_engine_dce80 {
-+	struct i2c_hw_engine base;
-+	struct {
-+		uint32_t DC_I2C_DDCX_SETUP;
-+		uint32_t DC_I2C_DDCX_SPEED;
-+	} addr;
-+	uint32_t engine_id;
-+	/* expressed in kilohertz */
-+	uint32_t reference_frequency;
-+	/* number of bytes currently used in HW buffer */
-+	uint32_t buffer_used_bytes;
-+	/* number of pending transactions (before GO) */
-+	uint32_t transaction_count;
-+	uint32_t engine_keep_power_up_count;
-+};
-+
-+struct i2c_hw_engine_dce80_create_arg {
-+	uint32_t engine_id;
-+	uint32_t reference_frequency;
-+	uint32_t default_speed;
-+	struct dc_context *ctx;
-+};
-+
-+struct i2c_engine *dal_i2c_hw_engine_dce80_create(
-+	const struct i2c_hw_engine_dce80_create_arg *arg);
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c.0130~	2017-12-14 06:39:58.434903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c	2017-12-14 06:39:58.434903581 +0100
-@@ -0,0 +1,173 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_sw_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_sw_engine_dce80.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+static const uint32_t ddc_hw_status_addr[] = {
-+	mmDC_I2C_DDC1_HW_STATUS,
-+	mmDC_I2C_DDC2_HW_STATUS,
-+	mmDC_I2C_DDC3_HW_STATUS,
-+	mmDC_I2C_DDC4_HW_STATUS,
-+	mmDC_I2C_DDC5_HW_STATUS,
-+	mmDC_I2C_DDC6_HW_STATUS,
-+	mmDC_I2C_DDCVGA_HW_STATUS
-+};
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_sw_engine *'
-+ * to 'struct i2c_sw_engine_dce80 *'
-+ */
-+#define FROM_I2C_SW_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_sw_engine_dce80, base)
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_engine *'
-+ * to 'struct i2c_sw_engine_dce80 *'
-+ */
-+#define FROM_I2C_ENGINE(ptr) \
-+	FROM_I2C_SW_ENGINE(container_of((ptr), struct i2c_sw_engine, base))
-+
-+/*
-+ * @brief
-+ * Cast 'struct engine *'
-+ * to 'struct i2c_sw_engine_dce80 *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-+
-+static void release_engine(
-+	struct engine *engine)
-+{
-+
-+}
-+
-+static void destruct(
-+	struct i2c_sw_engine_dce80 *engine)
-+{
-+	dal_i2c_sw_engine_destruct(&engine->base);
-+}
-+
-+static void destroy(
-+	struct i2c_engine **engine)
-+{
-+	struct i2c_sw_engine_dce80 *sw_engine = FROM_I2C_ENGINE(*engine);
-+
-+	destruct(sw_engine);
-+
-+	kfree(sw_engine);
-+
-+	*engine = NULL;
-+}
-+
-+static bool acquire_engine(
-+	struct i2c_engine *engine,
-+	struct ddc *ddc_handle)
-+{
-+	return dal_i2caux_i2c_sw_engine_acquire_engine(engine, ddc_handle);
-+}
-+
-+static const struct i2c_engine_funcs i2c_engine_funcs = {
-+	.acquire_engine = acquire_engine,
-+	.destroy = destroy,
-+	.get_speed = dal_i2c_sw_engine_get_speed,
-+	.set_speed = dal_i2c_sw_engine_set_speed,
-+	.setup_engine = dal_i2c_engine_setup_i2c_engine,
-+	.submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
-+	.process_channel_reply = dal_i2c_engine_process_channel_reply,
-+	.get_channel_status = dal_i2c_sw_engine_get_channel_status,
-+};
-+
-+static const struct engine_funcs engine_funcs = {
-+	.release_engine = release_engine,
-+	.get_engine_type = dal_i2c_sw_engine_get_engine_type,
-+	.acquire = dal_i2c_engine_acquire,
-+	.submit_request = dal_i2c_sw_engine_submit_request,
-+};
-+
-+static void construct(
-+	struct i2c_sw_engine_dce80 *engine,
-+	const struct i2c_sw_engine_dce80_create_arg *arg)
-+{
-+	struct i2c_sw_engine_create_arg arg_base;
-+
-+	arg_base.ctx = arg->ctx;
-+	arg_base.default_speed = arg->default_speed;
-+
-+	dal_i2c_sw_engine_construct(&engine->base, &arg_base);
-+
-+	engine->base.base.base.funcs = &engine_funcs;
-+	engine->base.base.funcs = &i2c_engine_funcs;
-+	engine->base.default_speed = arg->default_speed;
-+	engine->engine_id = arg->engine_id;
-+}
-+
-+struct i2c_engine *dal_i2c_sw_engine_dce80_create(
-+	const struct i2c_sw_engine_dce80_create_arg *arg)
-+{
-+	struct i2c_sw_engine_dce80 *engine;
-+
-+	if (!arg) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	engine = kzalloc(sizeof(struct i2c_sw_engine_dce80), GFP_KERNEL);
-+
-+	if (!engine) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	construct(engine, arg);
-+	return &engine->base.base;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.h.0130~	2017-12-14 06:39:58.434903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.h	2017-12-14 06:39:58.434903581 +0100
-@@ -0,0 +1,43 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_SW_ENGINE_DCE80_H__
-+#define __DAL_I2C_SW_ENGINE_DCE80_H__
-+
-+struct i2c_sw_engine_dce80 {
-+	struct i2c_sw_engine base;
-+	uint32_t engine_id;
-+};
-+
-+struct i2c_sw_engine_dce80_create_arg {
-+	uint32_t engine_id;
-+	uint32_t default_speed;
-+	struct dc_context *ctx;
-+};
-+
-+struct i2c_engine *dal_i2c_sw_engine_dce80_create(
-+	const struct i2c_sw_engine_dce80_create_arg *arg);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c.0130~	2017-12-14 06:39:58.434903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c	2017-12-14 06:39:58.434903581 +0100
-@@ -0,0 +1,118 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/i2caux_interface.h"
-+#include "../i2caux.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_sw_engine.h"
-+#include "../i2c_hw_engine.h"
-+
-+#include "../dce110/aux_engine_dce110.h"
-+#include "../dce110/i2c_hw_engine_dce110.h"
-+#include "../dce110/i2caux_dce110.h"
-+
-+#include "raven1/DCN/dcn_1_0_offset.h"
-+#include "raven1/DCN/dcn_1_0_sh_mask.h"
-+#include "vega10/soc15ip.h"
-+
-+/* begin *********************
-+ * macros to expend register list macro defined in HW object header file */
-+
-+#define BASE_INNER(seg) \
-+	DCE_BASE__INST0_SEG ## seg
-+
-+/* compile time expand base address. */
-+#define BASE(seg) \
-+	BASE_INNER(seg)
-+
-+#define SR(reg_name)\
-+		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
-+					mm ## reg_name
-+
-+#define SRI(reg_name, block, id)\
-+	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-+					mm ## block ## id ## _ ## reg_name
-+/* macros to expend register list macro defined in HW object header file
-+ * end *********************/
-+
-+#define aux_regs(id)\
-+[id] = {\
-+	AUX_COMMON_REG_LIST(id), \
-+	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK \
-+}
-+
-+#define hw_engine_regs(id)\
-+{\
-+		I2C_HW_ENGINE_COMMON_REG_LIST(id) \
-+}
-+
-+static const struct dce110_aux_registers dcn10_aux_regs[] = {
-+		aux_regs(0),
-+		aux_regs(1),
-+		aux_regs(2),
-+		aux_regs(3),
-+		aux_regs(4),
-+		aux_regs(5),
-+};
-+
-+static const struct dce110_i2c_hw_engine_registers dcn10_hw_engine_regs[] = {
-+		hw_engine_regs(1),
-+		hw_engine_regs(2),
-+		hw_engine_regs(3),
-+		hw_engine_regs(4),
-+		hw_engine_regs(5),
-+		hw_engine_regs(6)
-+};
-+
-+static const struct dce110_i2c_hw_engine_shift i2c_shift = {
-+		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-+};
-+
-+static const struct dce110_i2c_hw_engine_mask i2c_mask = {
-+		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
-+};
-+
-+struct i2caux *dal_i2caux_dcn10_create(
-+	struct dc_context *ctx)
-+{
-+	struct i2caux_dce110 *i2caux_dce110 =
-+		kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
-+
-+	if (!i2caux_dce110) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	dal_i2caux_dce110_construct(i2caux_dce110,
-+				    ctx,
-+				    dcn10_aux_regs,
-+				    dcn10_hw_engine_regs,
-+				    &i2c_shift,
-+				    &i2c_mask);
-+	return &i2caux_dce110->base;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h.0130~	2017-12-14 06:39:58.434903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h	2017-12-14 06:39:58.434903581 +0100
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_AUX_DCN10_H__
-+#define __DAL_I2C_AUX_DCN10_H__
-+
-+struct i2caux *dal_i2caux_dcn10_create(
-+	struct dc_context *ctx);
-+
-+#endif /* __DAL_I2C_AUX_DCN10_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c.0130~	2017-12-14 06:39:58.434903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c	2017-12-14 06:39:58.434903581 +0100
-@@ -0,0 +1,97 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "../i2caux.h"
-+#include "../engine.h"
-+#include "../i2c_engine.h"
-+#include "../i2c_sw_engine.h"
-+#include "../i2c_hw_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+#include "i2caux_diag.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+static void destruct(
-+	struct i2caux *i2caux)
-+{
-+	dal_i2caux_destruct(i2caux);
-+}
-+
-+static void destroy(
-+	struct i2caux **i2c_engine)
-+{
-+	destruct(*i2c_engine);
-+
-+	kfree(*i2c_engine);
-+
-+	*i2c_engine = NULL;
-+}
-+
-+/* function table */
-+static const struct i2caux_funcs i2caux_funcs = {
-+	.destroy = destroy,
-+	.acquire_i2c_hw_engine = NULL,
-+	.release_engine = NULL,
-+	.acquire_i2c_sw_engine = NULL,
-+	.acquire_aux_engine = NULL,
-+};
-+
-+static void construct(
-+	struct i2caux *i2caux,
-+	struct dc_context *ctx)
-+{
-+	dal_i2caux_construct(i2caux, ctx);
-+	i2caux->funcs = &i2caux_funcs;
-+}
-+
-+struct i2caux *dal_i2caux_diag_fpga_create(
-+	struct dc_context *ctx)
-+{
-+	struct i2caux *i2caux =	kzalloc(sizeof(struct i2caux),
-+					       GFP_KERNEL);
-+
-+	if (!i2caux) {
-+		ASSERT_CRITICAL(false);
-+		return NULL;
-+	}
-+
-+	construct(i2caux, ctx);
-+	return i2caux;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.h.0130~	2017-12-14 06:39:58.434903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.h	2017-12-14 06:39:58.434903581 +0100
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_AUX_DIAG_FPGA_H__
-+#define __DAL_I2C_AUX_DIAG_FPGA_H__
-+
-+struct i2caux *dal_i2caux_diag_fpga_create(
-+	struct dc_context *ctx);
-+
-+#endif /* __DAL_I2C_AUX_DIAG_FPGA_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/engine_base.c.0130~	2017-12-14 06:39:58.434903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/engine_base.c	2017-12-14 06:39:58.434903581 +0100
-@@ -0,0 +1,52 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "engine.h"
-+
-+void dal_i2caux_construct_engine(
-+	struct engine *engine,
-+	struct dc_context *ctx)
-+{
-+	engine->ddc = NULL;
-+	engine->ctx = ctx;
-+}
-+
-+void dal_i2caux_destruct_engine(
-+	struct engine *engine)
-+{
-+	/* nothing to do */
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/engine.h.0130~	2017-12-14 06:39:58.434903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/engine.h	2017-12-14 06:39:58.434903581 +0100
-@@ -0,0 +1,120 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ENGINE_H__
-+#define __DAL_ENGINE_H__
-+
-+enum i2caux_transaction_operation {
-+	I2CAUX_TRANSACTION_READ,
-+	I2CAUX_TRANSACTION_WRITE
-+};
-+
-+enum i2caux_transaction_address_space {
-+	I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C = 1,
-+	I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD
-+};
-+
-+struct i2caux_transaction_payload {
-+	enum i2caux_transaction_address_space address_space;
-+	uint32_t address;
-+	uint32_t length;
-+	uint8_t *data;
-+};
-+
-+enum i2caux_transaction_status {
-+	I2CAUX_TRANSACTION_STATUS_UNKNOWN = (-1L),
-+	I2CAUX_TRANSACTION_STATUS_SUCCEEDED,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_NACK,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION,
-+	I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW
-+};
-+
-+struct i2caux_transaction_request {
-+	enum i2caux_transaction_operation operation;
-+	struct i2caux_transaction_payload payload;
-+	enum i2caux_transaction_status status;
-+};
-+
-+enum i2caux_engine_type {
-+	I2CAUX_ENGINE_TYPE_UNKNOWN = (-1L),
-+	I2CAUX_ENGINE_TYPE_AUX,
-+	I2CAUX_ENGINE_TYPE_I2C_DDC_HW,
-+	I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW,
-+	I2CAUX_ENGINE_TYPE_I2C_SW
-+};
-+
-+enum i2c_default_speed {
-+	I2CAUX_DEFAULT_I2C_HW_SPEED = 50,
-+	I2CAUX_DEFAULT_I2C_SW_SPEED = 50
-+};
-+
-+enum i2caux_transaction_action {
-+	I2CAUX_TRANSACTION_ACTION_I2C_WRITE = 0x00,
-+	I2CAUX_TRANSACTION_ACTION_I2C_READ = 0x10,
-+	I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST = 0x20,
-+
-+	I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT = 0x40,
-+	I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT = 0x50,
-+	I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT = 0x60,
-+
-+	I2CAUX_TRANSACTION_ACTION_DP_WRITE = 0x80,
-+	I2CAUX_TRANSACTION_ACTION_DP_READ = 0x90
-+};
-+
-+struct engine;
-+
-+struct engine_funcs {
-+	enum i2caux_engine_type (*get_engine_type)(
-+		const struct engine *engine);
-+	bool (*acquire)(
-+		struct engine *engine,
-+		struct ddc *ddc);
-+	bool (*submit_request)(
-+		struct engine *engine,
-+		struct i2caux_transaction_request *request,
-+		bool middle_of_transaction);
-+	void (*release_engine)(
-+		struct engine *engine);
-+};
-+
-+struct engine {
-+	const struct engine_funcs *funcs;
-+	struct ddc *ddc;
-+	struct dc_context *ctx;
-+};
-+
-+void dal_i2caux_construct_engine(
-+	struct engine *engine,
-+	struct dc_context *ctx);
-+
-+void dal_i2caux_destruct_engine(
-+	struct engine *engine);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c.0130~	2017-12-14 06:39:58.434903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c	2017-12-14 06:39:58.434903581 +0100
-@@ -0,0 +1,485 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "dc_bios_types.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2caux.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+#include "engine.h"
-+#include "i2c_engine.h"
-+#include "aux_engine.h"
-+
-+/*
-+ * This unit
-+ */
-+
-+#include "dce80/i2caux_dce80.h"
-+
-+#include "dce100/i2caux_dce100.h"
-+
-+#include "dce110/i2caux_dce110.h"
-+
-+#include "dce112/i2caux_dce112.h"
-+
-+#include "dce120/i2caux_dce120.h"
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+#include "dcn10/i2caux_dcn10.h"
-+#endif
-+
-+#include "diagnostics/i2caux_diag.h"
-+
-+/*
-+ * @brief
-+ * Plain API, available publicly
-+ */
-+
-+struct i2caux *dal_i2caux_create(
-+	struct dc_context *ctx)
-+{
-+	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
-+		return dal_i2caux_diag_fpga_create(ctx);
-+	}
-+
-+	switch (ctx->dce_version) {
-+	case DCE_VERSION_8_0:
-+	case DCE_VERSION_8_1:
-+	case DCE_VERSION_8_3:
-+		return dal_i2caux_dce80_create(ctx);
-+	case DCE_VERSION_11_2:
-+		return dal_i2caux_dce112_create(ctx);
-+	case DCE_VERSION_11_0:
-+		return dal_i2caux_dce110_create(ctx);
-+	case DCE_VERSION_10_0:
-+		return dal_i2caux_dce100_create(ctx);
-+	case DCE_VERSION_12_0:
-+		return dal_i2caux_dce120_create(ctx);
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+	case DCN_VERSION_1_0:
-+		return dal_i2caux_dcn10_create(ctx);
-+#endif
-+
-+	default:
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+}
-+
-+bool dal_i2caux_submit_i2c_command(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc,
-+	struct i2c_command *cmd)
-+{
-+	struct i2c_engine *engine;
-+	uint8_t index_of_payload = 0;
-+	bool result;
-+
-+	if (!ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!cmd) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	/*
-+	 * default will be SW, however there is a feature flag in adapter
-+	 * service that determines whether SW i2c_engine will be available or
-+	 * not, if sw i2c is not available we will fallback to hw. This feature
-+	 * flag is set to not creating sw i2c engine for every dce except dce80
-+	 * currently
-+	 */
-+	switch (cmd->engine) {
-+	case I2C_COMMAND_ENGINE_DEFAULT:
-+	case I2C_COMMAND_ENGINE_SW:
-+		/* try to acquire SW engine first,
-+		 * acquire HW engine if SW engine not available */
-+		engine = i2caux->funcs->acquire_i2c_sw_engine(i2caux, ddc);
-+
-+		if (!engine)
-+			engine = i2caux->funcs->acquire_i2c_hw_engine(
-+				i2caux, ddc);
-+	break;
-+	case I2C_COMMAND_ENGINE_HW:
-+	default:
-+		/* try to acquire HW engine first,
-+		 * acquire SW engine if HW engine not available */
-+		engine = i2caux->funcs->acquire_i2c_hw_engine(i2caux, ddc);
-+
-+		if (!engine)
-+			engine = i2caux->funcs->acquire_i2c_sw_engine(
-+				i2caux, ddc);
-+	}
-+
-+	if (!engine)
-+		return false;
-+
-+	engine->funcs->set_speed(engine, cmd->speed);
-+
-+	result = true;
-+
-+	while (index_of_payload < cmd->number_of_payloads) {
-+		bool mot = (index_of_payload != cmd->number_of_payloads - 1);
-+
-+		struct i2c_payload *payload = cmd->payloads + index_of_payload;
-+
-+		struct i2caux_transaction_request request = { 0 };
-+
-+		request.operation = payload->write ?
-+			I2CAUX_TRANSACTION_WRITE :
-+			I2CAUX_TRANSACTION_READ;
-+
-+		request.payload.address_space =
-+			I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C;
-+		request.payload.address = (payload->address << 1) |
-+			!payload->write;
-+		request.payload.length = payload->length;
-+		request.payload.data = payload->data;
-+
-+		if (!engine->base.funcs->submit_request(
-+			&engine->base, &request, mot)) {
-+			result = false;
-+			break;
-+		}
-+
-+		++index_of_payload;
-+	}
-+
-+	i2caux->funcs->release_engine(i2caux, &engine->base);
-+
-+	return result;
-+}
-+
-+bool dal_i2caux_submit_aux_command(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc,
-+	struct aux_command *cmd)
-+{
-+	struct aux_engine *engine;
-+	uint8_t index_of_payload = 0;
-+	bool result;
-+	bool mot;
-+
-+	if (!ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!cmd) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	engine = i2caux->funcs->acquire_aux_engine(i2caux, ddc);
-+
-+	if (!engine)
-+		return false;
-+
-+	engine->delay = cmd->defer_delay;
-+	engine->max_defer_write_retry = cmd->max_defer_write_retry;
-+
-+	result = true;
-+
-+	while (index_of_payload < cmd->number_of_payloads) {
-+		struct aux_payload *payload = cmd->payloads + index_of_payload;
-+		struct i2caux_transaction_request request = { 0 };
-+
-+		if (cmd->mot == I2C_MOT_UNDEF)
-+			mot = (index_of_payload != cmd->number_of_payloads - 1);
-+		else
-+			mot = (cmd->mot == I2C_MOT_TRUE);
-+
-+		request.operation = payload->write ?
-+			I2CAUX_TRANSACTION_WRITE :
-+			I2CAUX_TRANSACTION_READ;
-+
-+		if (payload->i2c_over_aux) {
-+			request.payload.address_space =
-+				I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C;
-+
-+			request.payload.address = (payload->address << 1) |
-+				!payload->write;
-+		} else {
-+			request.payload.address_space =
-+				I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD;
-+
-+			request.payload.address = payload->address;
-+		}
-+
-+		request.payload.length = payload->length;
-+		request.payload.data = payload->data;
-+
-+		if (!engine->base.funcs->submit_request(
-+			&engine->base, &request, mot)) {
-+			result = false;
-+			break;
-+		}
-+
-+		++index_of_payload;
-+	}
-+
-+	i2caux->funcs->release_engine(i2caux, &engine->base);
-+
-+	return result;
-+}
-+
-+static bool get_hw_supported_ddc_line(
-+	struct ddc *ddc,
-+	enum gpio_ddc_line *line)
-+{
-+	enum gpio_ddc_line line_found;
-+
-+	*line = GPIO_DDC_LINE_UNKNOWN;
-+
-+	if (!ddc) {
-+		BREAK_TO_DEBUGGER();
-+		return false;
-+	}
-+
-+	if (!ddc->hw_info.hw_supported)
-+		return false;
-+
-+	line_found = dal_ddc_get_line(ddc);
-+
-+	if (line_found >= GPIO_DDC_LINE_COUNT)
-+		return false;
-+
-+	*line = line_found;
-+
-+	return true;
-+}
-+
-+void dal_i2caux_configure_aux(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc,
-+	union aux_config cfg)
-+{
-+	struct aux_engine *engine =
-+		i2caux->funcs->acquire_aux_engine(i2caux, ddc);
-+
-+	if (!engine)
-+		return;
-+
-+	engine->funcs->configure(engine, cfg);
-+
-+	i2caux->funcs->release_engine(i2caux, &engine->base);
-+}
-+
-+void dal_i2caux_destroy(
-+	struct i2caux **i2caux)
-+{
-+	if (!i2caux || !*i2caux) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	(*i2caux)->funcs->destroy(i2caux);
-+
-+	*i2caux = NULL;
-+}
-+
-+/*
-+ * @brief
-+ * An utility function used by 'struct i2caux' and its descendants
-+ */
-+
-+uint32_t dal_i2caux_get_reference_clock(
-+		struct dc_bios *bios)
-+{
-+	struct dc_firmware_info info = { { 0 } };
-+
-+	if (bios->funcs->get_firmware_info(bios, &info) != BP_RESULT_OK)
-+		return 0;
-+
-+	return info.pll_info.crystal_frequency;
-+}
-+
-+/*
-+ * @brief
-+ * i2caux
-+ */
-+
-+enum {
-+	/* following are expressed in KHz */
-+	DEFAULT_I2C_SW_SPEED = 50,
-+	DEFAULT_I2C_HW_SPEED = 50,
-+
-+	DEFAULT_I2C_SW_SPEED_100KHZ = 100,
-+	DEFAULT_I2C_HW_SPEED_100KHZ = 100,
-+
-+	/* This is the timeout as defined in DP 1.2a,
-+	 * 2.3.4 "Detailed uPacket TX AUX CH State Description". */
-+	AUX_TIMEOUT_PERIOD = 400,
-+
-+	/* Ideally, the SW timeout should be just above 550usec
-+	 * which is programmed in HW.
-+	 * But the SW timeout of 600usec is not reliable,
-+	 * because on some systems, delay_in_microseconds()
-+	 * returns faster than it should.
-+	 * EPR #379763: by trial-and-error on different systems,
-+	 * 700usec is the minimum reliable SW timeout for polling
-+	 * the AUX_SW_STATUS.AUX_SW_DONE bit.
-+	 * This timeout expires *only* when there is
-+	 * AUX Error or AUX Timeout conditions - not during normal operation.
-+	 * During normal operation, AUX_SW_STATUS.AUX_SW_DONE bit is set
-+	 * at most within ~240usec. That means,
-+	 * increasing this timeout will not affect normal operation,
-+	 * and we'll timeout after
-+	 * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 1600usec.
-+	 * This timeout is especially important for
-+	 * resume from S3 and CTS. */
-+	SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 4
-+};
-+
-+struct i2c_engine *dal_i2caux_acquire_i2c_sw_engine(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc)
-+{
-+	enum gpio_ddc_line line;
-+	struct i2c_engine *engine = NULL;
-+
-+	if (get_hw_supported_ddc_line(ddc, &line))
-+		engine = i2caux->i2c_sw_engines[line];
-+
-+	if (!engine)
-+		engine = i2caux->i2c_generic_sw_engine;
-+
-+	if (!engine)
-+		return NULL;
-+
-+	if (!engine->base.funcs->acquire(&engine->base, ddc))
-+		return NULL;
-+
-+	return engine;
-+}
-+
-+struct aux_engine *dal_i2caux_acquire_aux_engine(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc)
-+{
-+	enum gpio_ddc_line line;
-+	struct aux_engine *engine;
-+
-+	if (!get_hw_supported_ddc_line(ddc, &line))
-+		return NULL;
-+
-+	engine = i2caux->aux_engines[line];
-+
-+	if (!engine)
-+		return NULL;
-+
-+	if (!engine->base.funcs->acquire(&engine->base, ddc))
-+		return NULL;
-+
-+	return engine;
-+}
-+
-+void dal_i2caux_release_engine(
-+	struct i2caux *i2caux,
-+	struct engine *engine)
-+{
-+	engine->funcs->release_engine(engine);
-+
-+	dal_ddc_close(engine->ddc);
-+
-+	engine->ddc = NULL;
-+}
-+
-+void dal_i2caux_construct(
-+	struct i2caux *i2caux,
-+	struct dc_context *ctx)
-+{
-+	uint32_t i = 0;
-+
-+	i2caux->ctx = ctx;
-+	do {
-+		i2caux->i2c_sw_engines[i] = NULL;
-+		i2caux->i2c_hw_engines[i] = NULL;
-+		i2caux->aux_engines[i] = NULL;
-+
-+		++i;
-+	} while (i < GPIO_DDC_LINE_COUNT);
-+
-+	i2caux->i2c_generic_sw_engine = NULL;
-+	i2caux->i2c_generic_hw_engine = NULL;
-+
-+	i2caux->aux_timeout_period =
-+		SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD;
-+
-+	if (ctx->dce_version >= DCE_VERSION_11_2) {
-+		i2caux->default_i2c_hw_speed = DEFAULT_I2C_HW_SPEED_100KHZ;
-+		i2caux->default_i2c_sw_speed = DEFAULT_I2C_SW_SPEED_100KHZ;
-+	} else {
-+		i2caux->default_i2c_hw_speed = DEFAULT_I2C_HW_SPEED;
-+		i2caux->default_i2c_sw_speed = DEFAULT_I2C_SW_SPEED;
-+	}
-+}
-+
-+void dal_i2caux_destruct(
-+	struct i2caux *i2caux)
-+{
-+	uint32_t i = 0;
-+
-+	if (i2caux->i2c_generic_hw_engine)
-+		i2caux->i2c_generic_hw_engine->funcs->destroy(
-+			&i2caux->i2c_generic_hw_engine);
-+
-+	if (i2caux->i2c_generic_sw_engine)
-+		i2caux->i2c_generic_sw_engine->funcs->destroy(
-+			&i2caux->i2c_generic_sw_engine);
-+
-+	do {
-+		if (i2caux->aux_engines[i])
-+			i2caux->aux_engines[i]->funcs->destroy(
-+				&i2caux->aux_engines[i]);
-+
-+		if (i2caux->i2c_hw_engines[i])
-+			i2caux->i2c_hw_engines[i]->funcs->destroy(
-+				&i2caux->i2c_hw_engines[i]);
-+
-+		if (i2caux->i2c_sw_engines[i])
-+			i2caux->i2c_sw_engines[i]->funcs->destroy(
-+				&i2caux->i2c_sw_engines[i]);
-+
-+		++i;
-+	} while (i < GPIO_DDC_LINE_COUNT);
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.h.0130~	2017-12-14 06:39:58.434903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.h	2017-12-14 06:39:58.434903581 +0100
-@@ -0,0 +1,122 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_AUX_H__
-+#define __DAL_I2C_AUX_H__
-+
-+uint32_t dal_i2caux_get_reference_clock(
-+	struct dc_bios *bios);
-+
-+struct i2caux;
-+
-+struct engine;
-+
-+struct i2caux_funcs {
-+	void (*destroy)(struct i2caux **ptr);
-+	struct i2c_engine * (*acquire_i2c_sw_engine)(
-+		struct i2caux *i2caux,
-+		struct ddc *ddc);
-+	struct i2c_engine * (*acquire_i2c_hw_engine)(
-+		struct i2caux *i2caux,
-+		struct ddc *ddc);
-+	struct aux_engine * (*acquire_aux_engine)(
-+		struct i2caux *i2caux,
-+		struct ddc *ddc);
-+	void (*release_engine)(
-+		struct i2caux *i2caux,
-+		struct engine *engine);
-+};
-+
-+struct i2c_engine;
-+struct aux_engine;
-+
-+struct i2caux {
-+	struct dc_context *ctx;
-+	const struct i2caux_funcs *funcs;
-+	/* On ASIC we have certain amount of lines with HW DDC engine
-+	 * (4, 6, or maybe more in the future).
-+	 * For every such line, we create separate HW DDC engine
-+	 * (since we have these engines in HW) and separate SW DDC engine
-+	 * (to allow concurrent use of few lines).
-+	 * In similar way we have AUX engines. */
-+
-+	/* I2C SW engines, per DDC line.
-+	 * Only lines with HW DDC support will be initialized */
-+	struct i2c_engine *i2c_sw_engines[GPIO_DDC_LINE_COUNT];
-+
-+	/* I2C HW engines, per DDC line.
-+	 * Only lines with HW DDC support will be initialized */
-+	struct i2c_engine *i2c_hw_engines[GPIO_DDC_LINE_COUNT];
-+
-+	/* AUX engines, per DDC line.
-+	 * Only lines with HW AUX support will be initialized */
-+	struct aux_engine *aux_engines[GPIO_DDC_LINE_COUNT];
-+
-+	/* For all other lines, we can use
-+	 * single instance of generic I2C HW engine
-+	 * (since in HW, there is single instance of it)
-+	 * or single instance of generic I2C SW engine.
-+	 * AUX is not supported for other lines. */
-+
-+	/* General-purpose I2C SW engine.
-+	 * Can be assigned dynamically to any line per transaction */
-+	struct i2c_engine *i2c_generic_sw_engine;
-+
-+	/* General-purpose I2C generic HW engine.
-+	 * Can be assigned dynamically to almost any line per transaction */
-+	struct i2c_engine *i2c_generic_hw_engine;
-+
-+	/* [anaumov] in DAL2, there is a Mutex */
-+
-+	uint32_t aux_timeout_period;
-+
-+	/* expressed in KHz */
-+	uint32_t default_i2c_sw_speed;
-+	uint32_t default_i2c_hw_speed;
-+};
-+
-+void dal_i2caux_construct(
-+	struct i2caux *i2caux,
-+	struct dc_context *ctx);
-+
-+void dal_i2caux_release_engine(
-+	struct i2caux *i2caux,
-+	struct engine *engine);
-+
-+void dal_i2caux_destruct(
-+	struct i2caux *i2caux);
-+
-+void dal_i2caux_destroy(
-+	struct i2caux **ptr);
-+
-+struct i2c_engine *dal_i2caux_acquire_i2c_sw_engine(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc);
-+
-+struct aux_engine *dal_i2caux_acquire_aux_engine(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.c.0130~	2017-12-14 06:39:58.435903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.c	2017-12-14 06:39:58.434903581 +0100
-@@ -0,0 +1,118 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_engine.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+#define FROM_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_engine, base)
-+
-+bool dal_i2c_engine_acquire(
-+	struct engine *engine,
-+	struct ddc *ddc_handle)
-+{
-+	struct i2c_engine *i2c_engine = FROM_ENGINE(engine);
-+
-+	uint32_t counter = 0;
-+	bool result;
-+
-+	do {
-+		result = i2c_engine->funcs->acquire_engine(
-+			i2c_engine, ddc_handle);
-+
-+		if (result)
-+			break;
-+
-+		/* i2c_engine is busy by VBios, lets wait and retry */
-+
-+		udelay(10);
-+
-+		++counter;
-+	} while (counter < 2);
-+
-+	if (result) {
-+		if (!i2c_engine->funcs->setup_engine(i2c_engine)) {
-+			engine->funcs->release_engine(engine);
-+			result = false;
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+bool dal_i2c_engine_setup_i2c_engine(
-+	struct i2c_engine *engine)
-+{
-+	/* Derivative classes do not have to override this */
-+
-+	return true;
-+}
-+
-+void dal_i2c_engine_submit_channel_request(
-+	struct i2c_engine *engine,
-+	struct i2c_request_transaction_data *request)
-+{
-+
-+}
-+
-+void dal_i2c_engine_process_channel_reply(
-+	struct i2c_engine *engine,
-+	struct i2c_reply_transaction_data *reply)
-+{
-+
-+}
-+
-+void dal_i2c_engine_construct(
-+	struct i2c_engine *engine,
-+	struct dc_context *ctx)
-+{
-+	dal_i2caux_construct_engine(&engine->base, ctx);
-+	engine->timeout_delay = 0;
-+}
-+
-+void dal_i2c_engine_destruct(
-+	struct i2c_engine *engine)
-+{
-+	dal_i2caux_destruct_engine(&engine->base);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.h.0130~	2017-12-14 06:39:58.435903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.h	2017-12-14 06:39:58.435903581 +0100
-@@ -0,0 +1,113 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_ENGINE_H__
-+#define __DAL_I2C_ENGINE_H__
-+
-+enum i2c_channel_operation_result {
-+	I2C_CHANNEL_OPERATION_SUCCEEDED,
-+	I2C_CHANNEL_OPERATION_FAILED,
-+	I2C_CHANNEL_OPERATION_NOT_GRANTED,
-+	I2C_CHANNEL_OPERATION_IS_BUSY,
-+	I2C_CHANNEL_OPERATION_NO_HANDLE_PROVIDED,
-+	I2C_CHANNEL_OPERATION_CHANNEL_IN_USE,
-+	I2C_CHANNEL_OPERATION_CHANNEL_CLIENT_MAX_ALLOWED,
-+	I2C_CHANNEL_OPERATION_ENGINE_BUSY,
-+	I2C_CHANNEL_OPERATION_TIMEOUT,
-+	I2C_CHANNEL_OPERATION_NO_RESPONSE,
-+	I2C_CHANNEL_OPERATION_HW_REQUEST_I2C_BUS,
-+	I2C_CHANNEL_OPERATION_WRONG_PARAMETER,
-+	I2C_CHANNEL_OPERATION_OUT_NB_OF_RETRIES,
-+	I2C_CHANNEL_OPERATION_NOT_STARTED
-+};
-+
-+struct i2c_request_transaction_data {
-+	enum i2caux_transaction_action action;
-+	enum i2c_channel_operation_result status;
-+	uint8_t address;
-+	uint32_t length;
-+	uint8_t *data;
-+};
-+
-+struct i2c_reply_transaction_data {
-+	uint32_t length;
-+	uint8_t *data;
-+};
-+
-+struct i2c_engine;
-+
-+struct i2c_engine_funcs {
-+	void (*destroy)(
-+		struct i2c_engine **ptr);
-+	uint32_t (*get_speed)(
-+		const struct i2c_engine *engine);
-+	void (*set_speed)(
-+		struct i2c_engine *engine,
-+		uint32_t speed);
-+	bool (*acquire_engine)(
-+		struct i2c_engine *engine,
-+		struct ddc *ddc);
-+	bool (*setup_engine)(
-+		struct i2c_engine *engine);
-+	void (*submit_channel_request)(
-+		struct i2c_engine *engine,
-+		struct i2c_request_transaction_data *request);
-+	void (*process_channel_reply)(
-+		struct i2c_engine *engine,
-+		struct i2c_reply_transaction_data *reply);
-+	enum i2c_channel_operation_result (*get_channel_status)(
-+		struct i2c_engine *engine,
-+		uint8_t *returned_bytes);
-+};
-+
-+struct i2c_engine {
-+	struct engine base;
-+	const struct i2c_engine_funcs *funcs;
-+	uint32_t timeout_delay;
-+};
-+
-+void dal_i2c_engine_construct(
-+	struct i2c_engine *engine,
-+	struct dc_context *ctx);
-+
-+void dal_i2c_engine_destruct(
-+	struct i2c_engine *engine);
-+
-+bool dal_i2c_engine_setup_i2c_engine(
-+	struct i2c_engine *engine);
-+
-+void dal_i2c_engine_submit_channel_request(
-+	struct i2c_engine *engine,
-+	struct i2c_request_transaction_data *request);
-+
-+void dal_i2c_engine_process_channel_reply(
-+	struct i2c_engine *engine,
-+	struct i2c_reply_transaction_data *reply);
-+
-+bool dal_i2c_engine_acquire(
-+	struct engine *ptr,
-+	struct ddc *ddc_handle);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c.0130~	2017-12-14 06:39:58.435903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c	2017-12-14 06:39:58.435903581 +0100
-@@ -0,0 +1,284 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "engine.h"
-+#include "i2c_engine.h"
-+#include "i2c_hw_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_generic_hw_engine.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_hw_engine *'
-+ * to 'struct i2c_generic_hw_engine *'
-+ */
-+#define FROM_I2C_HW_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_generic_hw_engine, base)
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_engine *'
-+ * to 'struct i2c_generic_hw_engine *'
-+ */
-+#define FROM_I2C_ENGINE(ptr) \
-+	FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
-+
-+/*
-+ * @brief
-+ * Cast 'struct engine *'
-+ * to 'struct i2c_generic_hw_engine *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-+
-+enum i2caux_engine_type dal_i2c_generic_hw_engine_get_engine_type(
-+	const struct engine *engine)
-+{
-+	return I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW;
-+}
-+
-+/*
-+ * @brief
-+ * Single transaction handling.
-+ * Since transaction may be bigger than HW buffer size,
-+ * it divides transaction to sub-transactions
-+ * and uses batch transaction feature of the engine.
-+ */
-+bool dal_i2c_generic_hw_engine_submit_request(
-+	struct engine *engine,
-+	struct i2caux_transaction_request *i2caux_request,
-+	bool middle_of_transaction)
-+{
-+	struct i2c_generic_hw_engine *hw_engine = FROM_ENGINE(engine);
-+
-+	struct i2c_hw_engine *base = &hw_engine->base;
-+
-+	uint32_t max_payload_size =
-+		base->funcs->get_hw_buffer_available_size(base);
-+
-+	bool initial_stop_bit = !middle_of_transaction;
-+
-+	struct i2c_generic_transaction_attributes attributes;
-+
-+	enum i2c_channel_operation_result operation_result =
-+		I2C_CHANNEL_OPERATION_FAILED;
-+
-+	bool result = false;
-+
-+	/* setup transaction initial properties */
-+
-+	uint8_t address = i2caux_request->payload.address;
-+	uint8_t *current_payload = i2caux_request->payload.data;
-+	uint32_t remaining_payload_size = i2caux_request->payload.length;
-+
-+	bool first_iteration = true;
-+
-+	if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
-+		attributes.action = I2CAUX_TRANSACTION_ACTION_I2C_READ;
-+	else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
-+		attributes.action = I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
-+	else {
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
-+		return false;
-+	}
-+
-+	/* Do batch transaction.
-+	 * Divide read/write data into payloads which fit HW buffer size.
-+	 * 1. Single transaction:
-+	 *    start_bit = 1, stop_bit depends on session state, ack_on_read = 0;
-+	 * 2. Start of batch transaction:
-+	 *    start_bit = 1, stop_bit = 0, ack_on_read = 1;
-+	 * 3. Middle of batch transaction:
-+	 *    start_bit = 0, stop_bit = 0, ack_on_read = 1;
-+	 * 4. End of batch transaction:
-+	 *    start_bit = 0, stop_bit depends on session state, ack_on_read = 0.
-+	 * Session stop bit is set if 'middle_of_transaction' = 0. */
-+
-+	while (remaining_payload_size) {
-+		uint32_t current_transaction_size;
-+		uint32_t current_payload_size;
-+
-+		bool last_iteration;
-+		bool stop_bit;
-+
-+		/* Calculate current transaction size and payload size.
-+		 * Transaction size = total number of bytes in transaction,
-+		 * including slave's address;
-+		 * Payload size = number of data bytes in transaction. */
-+
-+		if (first_iteration) {
-+			/* In the first sub-transaction we send slave's address
-+			 * thus we need to reserve one byte for it */
-+			current_transaction_size =
-+			(remaining_payload_size > max_payload_size - 1) ?
-+				max_payload_size :
-+				remaining_payload_size + 1;
-+
-+			current_payload_size = current_transaction_size - 1;
-+		} else {
-+			/* Second and further sub-transactions will have
-+			 * entire buffer reserved for data */
-+			current_transaction_size =
-+				(remaining_payload_size > max_payload_size) ?
-+				max_payload_size :
-+				remaining_payload_size;
-+
-+			current_payload_size = current_transaction_size;
-+		}
-+
-+		last_iteration =
-+			(remaining_payload_size == current_payload_size);
-+
-+		stop_bit = last_iteration ? initial_stop_bit : false;
-+
-+		/* write slave device address */
-+
-+		if (first_iteration)
-+			hw_engine->funcs->write_address(hw_engine, address);
-+
-+		/* write current portion of data, if requested */
-+
-+		if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
-+			hw_engine->funcs->write_data(
-+				hw_engine,
-+				current_payload,
-+				current_payload_size);
-+
-+		/* execute transaction */
-+
-+		attributes.start_bit = first_iteration;
-+		attributes.stop_bit = stop_bit;
-+		attributes.last_read = last_iteration;
-+		attributes.transaction_size = current_transaction_size;
-+
-+		hw_engine->funcs->execute_transaction(hw_engine, &attributes);
-+
-+		/* wait until transaction is processed; if it fails - quit */
-+
-+		operation_result = base->funcs->wait_on_operation_result(
-+			base,
-+			base->funcs->get_transaction_timeout(
-+				base, current_transaction_size),
-+			I2C_CHANNEL_OPERATION_ENGINE_BUSY);
-+
-+		if (operation_result != I2C_CHANNEL_OPERATION_SUCCEEDED)
-+			break;
-+
-+		/* read current portion of data, if requested */
-+
-+		/* the read offset should be 1 for first sub-transaction,
-+		 * and 0 for any next one */
-+
-+		if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
-+			hw_engine->funcs->read_data(hw_engine, current_payload,
-+				current_payload_size, first_iteration ? 1 : 0);
-+
-+		/* update loop variables */
-+
-+		first_iteration = false;
-+		current_payload += current_payload_size;
-+		remaining_payload_size -= current_payload_size;
-+	}
-+
-+	/* update transaction status */
-+
-+	switch (operation_result) {
-+	case I2C_CHANNEL_OPERATION_SUCCEEDED:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-+		result = true;
-+	break;
-+	case I2C_CHANNEL_OPERATION_NO_RESPONSE:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-+	break;
-+	case I2C_CHANNEL_OPERATION_TIMEOUT:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+	break;
-+	case I2C_CHANNEL_OPERATION_FAILED:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
-+	break;
-+	default:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
-+	}
-+
-+	return result;
-+}
-+
-+/*
-+ * @brief
-+ * Returns number of microseconds to wait until timeout to be considered
-+ */
-+uint32_t dal_i2c_generic_hw_engine_get_transaction_timeout(
-+	const struct i2c_hw_engine *engine,
-+	uint32_t length)
-+{
-+	const struct i2c_engine *base = &engine->base;
-+
-+	uint32_t speed = base->funcs->get_speed(base);
-+
-+	if (!speed)
-+		return 0;
-+
-+	/* total timeout = period_timeout * (start + data bits count + stop) */
-+
-+	return ((1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed) *
-+		(1 + (length << 3) + 1);
-+}
-+
-+void dal_i2c_generic_hw_engine_construct(
-+	struct i2c_generic_hw_engine *engine,
-+	struct dc_context *ctx)
-+{
-+	dal_i2c_hw_engine_construct(&engine->base, ctx);
-+}
-+
-+void dal_i2c_generic_hw_engine_destruct(
-+	struct i2c_generic_hw_engine *engine)
-+{
-+	dal_i2c_hw_engine_destruct(&engine->base);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h.0130~	2017-12-14 06:39:58.435903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h	2017-12-14 06:39:58.435903581 +0100
-@@ -0,0 +1,77 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_GENERIC_HW_ENGINE_H__
-+#define __DAL_I2C_GENERIC_HW_ENGINE_H__
-+
-+struct i2c_generic_transaction_attributes {
-+	enum i2caux_transaction_action action;
-+	uint32_t transaction_size;
-+	bool start_bit;
-+	bool stop_bit;
-+	bool last_read;
-+};
-+
-+struct i2c_generic_hw_engine;
-+
-+struct i2c_generic_hw_engine_funcs {
-+	void (*write_address)(
-+		struct i2c_generic_hw_engine *engine,
-+		uint8_t address);
-+	void (*write_data)(
-+		struct i2c_generic_hw_engine *engine,
-+		const uint8_t *buffer,
-+		uint32_t length);
-+	void (*read_data)(
-+		struct i2c_generic_hw_engine *engine,
-+		uint8_t *buffer,
-+		uint32_t length,
-+		uint32_t offset);
-+	void (*execute_transaction)(
-+		struct i2c_generic_hw_engine *engine,
-+		struct i2c_generic_transaction_attributes *attributes);
-+};
-+
-+struct i2c_generic_hw_engine {
-+	struct i2c_hw_engine base;
-+	const struct i2c_generic_hw_engine_funcs *funcs;
-+};
-+
-+void dal_i2c_generic_hw_engine_construct(
-+	struct i2c_generic_hw_engine *engine,
-+	struct dc_context *ctx);
-+
-+void dal_i2c_generic_hw_engine_destruct(
-+	struct i2c_generic_hw_engine *engine);
-+enum i2caux_engine_type dal_i2c_generic_hw_engine_get_engine_type(
-+	const struct engine *engine);
-+bool dal_i2c_generic_hw_engine_submit_request(
-+	struct engine *ptr,
-+	struct i2caux_transaction_request *i2caux_request,
-+	bool middle_of_transaction);
-+uint32_t dal_i2c_generic_hw_engine_get_transaction_timeout(
-+	const struct i2c_hw_engine *engine,
-+	uint32_t length);
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.c.0130~	2017-12-14 06:39:58.435903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.c	2017-12-14 06:39:58.435903581 +0100
-@@ -0,0 +1,244 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "engine.h"
-+#include "i2c_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_hw_engine.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_engine *'
-+ * to 'struct i2c_hw_engine *'
-+ */
-+#define FROM_I2C_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_hw_engine, base)
-+
-+/*
-+ * @brief
-+ * Cast 'struct engine *'
-+ * to 'struct i2c_hw_engine *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-+
-+enum i2caux_engine_type dal_i2c_hw_engine_get_engine_type(
-+	const struct engine *engine)
-+{
-+	return I2CAUX_ENGINE_TYPE_I2C_DDC_HW;
-+}
-+
-+bool dal_i2c_hw_engine_submit_request(
-+	struct engine *engine,
-+	struct i2caux_transaction_request *i2caux_request,
-+	bool middle_of_transaction)
-+{
-+	struct i2c_hw_engine *hw_engine = FROM_ENGINE(engine);
-+
-+	struct i2c_request_transaction_data request;
-+
-+	uint32_t transaction_timeout;
-+
-+	enum i2c_channel_operation_result operation_result;
-+
-+	bool result = false;
-+
-+	/* We need following:
-+	 * transaction length will not exceed
-+	 * the number of free bytes in HW buffer (minus one for address)*/
-+
-+	if (i2caux_request->payload.length >=
-+		hw_engine->funcs->get_hw_buffer_available_size(hw_engine)) {
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW;
-+		return false;
-+	}
-+
-+	if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
-+		request.action = middle_of_transaction ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_READ;
-+	else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
-+		request.action = middle_of_transaction ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
-+	else {
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
-+		/* [anaumov] in DAL2, there was no "return false" */
-+		return false;
-+	}
-+
-+	request.address = (uint8_t)i2caux_request->payload.address;
-+	request.length = i2caux_request->payload.length;
-+	request.data = i2caux_request->payload.data;
-+
-+	/* obtain timeout value before submitting request */
-+
-+	transaction_timeout = hw_engine->funcs->get_transaction_timeout(
-+		hw_engine, i2caux_request->payload.length + 1);
-+
-+	hw_engine->base.funcs->submit_channel_request(
-+		&hw_engine->base, &request);
-+
-+	if ((request.status == I2C_CHANNEL_OPERATION_FAILED) ||
-+		(request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY)) {
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY;
-+		return false;
-+	}
-+
-+	/* wait until transaction proceed */
-+
-+	operation_result = hw_engine->funcs->wait_on_operation_result(
-+		hw_engine,
-+		transaction_timeout,
-+		I2C_CHANNEL_OPERATION_ENGINE_BUSY);
-+
-+	/* update transaction status */
-+
-+	switch (operation_result) {
-+	case I2C_CHANNEL_OPERATION_SUCCEEDED:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-+		result = true;
-+	break;
-+	case I2C_CHANNEL_OPERATION_NO_RESPONSE:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-+	break;
-+	case I2C_CHANNEL_OPERATION_TIMEOUT:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+	break;
-+	case I2C_CHANNEL_OPERATION_FAILED:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
-+	break;
-+	default:
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
-+	}
-+
-+	if (result && (i2caux_request->operation == I2CAUX_TRANSACTION_READ)) {
-+		struct i2c_reply_transaction_data reply;
-+
-+		reply.data = i2caux_request->payload.data;
-+		reply.length = i2caux_request->payload.length;
-+
-+		hw_engine->base.funcs->
-+			process_channel_reply(&hw_engine->base, &reply);
-+	}
-+
-+	return result;
-+}
-+
-+bool dal_i2c_hw_engine_acquire_engine(
-+	struct i2c_engine *engine,
-+	struct ddc *ddc)
-+{
-+	enum gpio_result result;
-+	uint32_t current_speed;
-+
-+	result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
-+		GPIO_DDC_CONFIG_TYPE_MODE_I2C);
-+
-+	if (result != GPIO_RESULT_OK)
-+		return false;
-+
-+	engine->base.ddc = ddc;
-+
-+	current_speed = engine->funcs->get_speed(engine);
-+
-+	if (current_speed)
-+		FROM_I2C_ENGINE(engine)->original_speed = current_speed;
-+
-+	return true;
-+}
-+/*
-+ * @brief
-+ * Queries in a loop for current engine status
-+ * until retrieved status matches 'expected_result', or timeout occurs.
-+ * Timeout given in microseconds
-+ * and the status query frequency is also one per microsecond.
-+ */
-+enum i2c_channel_operation_result dal_i2c_hw_engine_wait_on_operation_result(
-+	struct i2c_hw_engine *engine,
-+	uint32_t timeout,
-+	enum i2c_channel_operation_result expected_result)
-+{
-+	enum i2c_channel_operation_result result;
-+	uint32_t i = 0;
-+
-+	if (!timeout)
-+		return I2C_CHANNEL_OPERATION_SUCCEEDED;
-+
-+	do {
-+		result = engine->base.funcs->get_channel_status(
-+			&engine->base, NULL);
-+
-+		if (result != expected_result)
-+			break;
-+
-+		udelay(1);
-+
-+		++i;
-+	} while (i < timeout);
-+
-+	return result;
-+}
-+
-+void dal_i2c_hw_engine_construct(
-+	struct i2c_hw_engine *engine,
-+	struct dc_context *ctx)
-+{
-+	dal_i2c_engine_construct(&engine->base, ctx);
-+	engine->original_speed = I2CAUX_DEFAULT_I2C_HW_SPEED;
-+	engine->default_speed = I2CAUX_DEFAULT_I2C_HW_SPEED;
-+}
-+
-+void dal_i2c_hw_engine_destruct(
-+	struct i2c_hw_engine *engine)
-+{
-+	dal_i2c_engine_destruct(&engine->base);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.h.0130~	2017-12-14 06:39:58.435903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.h	2017-12-14 06:39:58.435903581 +0100
-@@ -0,0 +1,80 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_HW_ENGINE_H__
-+#define __DAL_I2C_HW_ENGINE_H__
-+
-+enum {
-+	TRANSACTION_TIMEOUT_IN_I2C_CLOCKS = 32
-+};
-+
-+struct i2c_hw_engine;
-+
-+struct i2c_hw_engine_funcs {
-+	uint32_t (*get_hw_buffer_available_size)(
-+		const struct i2c_hw_engine *engine);
-+	enum i2c_channel_operation_result (*wait_on_operation_result)(
-+		struct i2c_hw_engine *engine,
-+		uint32_t timeout,
-+		enum i2c_channel_operation_result expected_result);
-+	uint32_t (*get_transaction_timeout)(
-+		const struct i2c_hw_engine *engine,
-+		uint32_t length);
-+};
-+
-+struct i2c_hw_engine {
-+	struct i2c_engine base;
-+	const struct i2c_hw_engine_funcs *funcs;
-+
-+	/* Values below are in kilohertz */
-+	uint32_t original_speed;
-+	uint32_t default_speed;
-+};
-+
-+void dal_i2c_hw_engine_construct(
-+	struct i2c_hw_engine *engine,
-+	struct dc_context *ctx);
-+
-+void dal_i2c_hw_engine_destruct(
-+	struct i2c_hw_engine *engine);
-+
-+enum i2c_channel_operation_result dal_i2c_hw_engine_wait_on_operation_result(
-+	struct i2c_hw_engine *engine,
-+	uint32_t timeout,
-+	enum i2c_channel_operation_result expected_result);
-+
-+bool dal_i2c_hw_engine_acquire_engine(
-+	struct i2c_engine *engine,
-+	struct ddc *ddc);
-+
-+bool dal_i2c_hw_engine_submit_request(
-+	struct engine *ptr,
-+	struct i2caux_transaction_request *i2caux_request,
-+	bool middle_of_transaction);
-+
-+enum i2caux_engine_type dal_i2c_hw_engine_get_engine_type(
-+	const struct engine *engine);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c.0130~	2017-12-14 06:39:58.435903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c	2017-12-14 06:39:58.435903581 +0100
-@@ -0,0 +1,601 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+/*
-+ * Pre-requisites: headers required by header of this unit
-+ */
-+#include "include/i2caux_interface.h"
-+#include "engine.h"
-+#include "i2c_engine.h"
-+
-+/*
-+ * Header of this unit
-+ */
-+
-+#include "i2c_sw_engine.h"
-+
-+/*
-+ * Post-requisites: headers required by this unit
-+ */
-+
-+/*
-+ * This unit
-+ */
-+
-+#define SCL false
-+#define SDA true
-+
-+static inline bool read_bit_from_ddc(
-+	struct ddc *ddc,
-+	bool data_nor_clock)
-+{
-+	uint32_t value = 0;
-+
-+	if (data_nor_clock)
-+		dal_gpio_get_value(ddc->pin_data, &value);
-+	else
-+		dal_gpio_get_value(ddc->pin_clock, &value);
-+
-+	return (value != 0);
-+}
-+
-+static inline void write_bit_to_ddc(
-+	struct ddc *ddc,
-+	bool data_nor_clock,
-+	bool bit)
-+{
-+	uint32_t value = bit ? 1 : 0;
-+
-+	if (data_nor_clock)
-+		dal_gpio_set_value(ddc->pin_data, value);
-+	else
-+		dal_gpio_set_value(ddc->pin_clock, value);
-+}
-+
-+static bool wait_for_scl_high(
-+	struct dc_context *ctx,
-+	struct ddc *ddc,
-+	uint16_t clock_delay_div_4)
-+{
-+	uint32_t scl_retry = 0;
-+	uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4;
-+
-+	udelay(clock_delay_div_4);
-+
-+	/* 3 milliseconds delay
-+	 * to wake up some displays from "low power" state.
-+	 */
-+
-+	do {
-+		if (read_bit_from_ddc(ddc, SCL))
-+			return true;
-+
-+		udelay(clock_delay_div_4);
-+
-+		++scl_retry;
-+	} while (scl_retry <= scl_retry_max);
-+
-+	return false;
-+}
-+
-+static bool start_sync(
-+	struct dc_context *ctx,
-+	struct ddc *ddc_handle,
-+	uint16_t clock_delay_div_4)
-+{
-+	uint32_t retry = 0;
-+
-+	/* The I2C communications start signal is:
-+	 * the SDA going low from high, while the SCL is high. */
-+
-+	write_bit_to_ddc(ddc_handle, SCL, true);
-+
-+	udelay(clock_delay_div_4);
-+
-+	do {
-+		write_bit_to_ddc(ddc_handle, SDA, true);
-+
-+		if (!read_bit_from_ddc(ddc_handle, SDA)) {
-+			++retry;
-+			continue;
-+		}
-+
-+		udelay(clock_delay_div_4);
-+
-+		write_bit_to_ddc(ddc_handle, SCL, true);
-+
-+		if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-+			break;
-+
-+		write_bit_to_ddc(ddc_handle, SDA, false);
-+
-+		udelay(clock_delay_div_4);
-+
-+		write_bit_to_ddc(ddc_handle, SCL, false);
-+
-+		udelay(clock_delay_div_4);
-+
-+		return true;
-+	} while (retry <= I2C_SW_RETRIES);
-+
-+	return false;
-+}
-+
-+static bool stop_sync(
-+	struct dc_context *ctx,
-+	struct ddc *ddc_handle,
-+	uint16_t clock_delay_div_4)
-+{
-+	uint32_t retry = 0;
-+
-+	/* The I2C communications stop signal is:
-+	 * the SDA going high from low, while the SCL is high. */
-+
-+	write_bit_to_ddc(ddc_handle, SCL, false);
-+
-+	udelay(clock_delay_div_4);
-+
-+	write_bit_to_ddc(ddc_handle, SDA, false);
-+
-+	udelay(clock_delay_div_4);
-+
-+	write_bit_to_ddc(ddc_handle, SCL, true);
-+
-+	if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-+		return false;
-+
-+	write_bit_to_ddc(ddc_handle, SDA, true);
-+
-+	do {
-+		udelay(clock_delay_div_4);
-+
-+		if (read_bit_from_ddc(ddc_handle, SDA))
-+			return true;
-+
-+		++retry;
-+	} while (retry <= 2);
-+
-+	return false;
-+}
-+
-+static bool write_byte(
-+	struct dc_context *ctx,
-+	struct ddc *ddc_handle,
-+	uint16_t clock_delay_div_4,
-+	uint8_t byte)
-+{
-+	int32_t shift = 7;
-+	bool ack;
-+
-+	/* bits are transmitted serially, starting from MSB */
-+
-+	do {
-+		udelay(clock_delay_div_4);
-+
-+		write_bit_to_ddc(ddc_handle, SDA, (byte >> shift) & 1);
-+
-+		udelay(clock_delay_div_4);
-+
-+		write_bit_to_ddc(ddc_handle, SCL, true);
-+
-+		if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-+			return false;
-+
-+		write_bit_to_ddc(ddc_handle, SCL, false);
-+
-+		--shift;
-+	} while (shift >= 0);
-+
-+	/* The display sends ACK by preventing the SDA from going high
-+	 * after the SCL pulse we use to send our last data bit.
-+	 * If the SDA goes high after that bit, it's a NACK */
-+
-+	udelay(clock_delay_div_4);
-+
-+	write_bit_to_ddc(ddc_handle, SDA, true);
-+
-+	udelay(clock_delay_div_4);
-+
-+	write_bit_to_ddc(ddc_handle, SCL, true);
-+
-+	if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-+		return false;
-+
-+	/* read ACK bit */
-+
-+	ack = !read_bit_from_ddc(ddc_handle, SDA);
-+
-+	udelay(clock_delay_div_4 << 1);
-+
-+	write_bit_to_ddc(ddc_handle, SCL, false);
-+
-+	udelay(clock_delay_div_4 << 1);
-+
-+	return ack;
-+}
-+
-+static bool read_byte(
-+	struct dc_context *ctx,
-+	struct ddc *ddc_handle,
-+	uint16_t clock_delay_div_4,
-+	uint8_t *byte,
-+	bool more)
-+{
-+	int32_t shift = 7;
-+
-+	uint8_t data = 0;
-+
-+	/* The data bits are read from MSB to LSB;
-+	 * bit is read while SCL is high */
-+
-+	do {
-+		write_bit_to_ddc(ddc_handle, SCL, true);
-+
-+		if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-+			return false;
-+
-+		if (read_bit_from_ddc(ddc_handle, SDA))
-+			data |= (1 << shift);
-+
-+		write_bit_to_ddc(ddc_handle, SCL, false);
-+
-+		udelay(clock_delay_div_4 << 1);
-+
-+		--shift;
-+	} while (shift >= 0);
-+
-+	/* read only whole byte */
-+
-+	*byte = data;
-+
-+	udelay(clock_delay_div_4);
-+
-+	/* send the acknowledge bit:
-+	 * SDA low means ACK, SDA high means NACK */
-+
-+	write_bit_to_ddc(ddc_handle, SDA, !more);
-+
-+	udelay(clock_delay_div_4);
-+
-+	write_bit_to_ddc(ddc_handle, SCL, true);
-+
-+	if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-+		return false;
-+
-+	write_bit_to_ddc(ddc_handle, SCL, false);
-+
-+	udelay(clock_delay_div_4);
-+
-+	write_bit_to_ddc(ddc_handle, SDA, true);
-+
-+	udelay(clock_delay_div_4);
-+
-+	return true;
-+}
-+
-+static bool i2c_write(
-+	struct dc_context *ctx,
-+	struct ddc *ddc_handle,
-+	uint16_t clock_delay_div_4,
-+	uint8_t address,
-+	uint32_t length,
-+	const uint8_t *data)
-+{
-+	uint32_t i = 0;
-+
-+	if (!write_byte(ctx, ddc_handle, clock_delay_div_4, address))
-+		return false;
-+
-+	while (i < length) {
-+		if (!write_byte(ctx, ddc_handle, clock_delay_div_4, data[i]))
-+			return false;
-+		++i;
-+	}
-+
-+	return true;
-+}
-+
-+static bool i2c_read(
-+	struct dc_context *ctx,
-+	struct ddc *ddc_handle,
-+	uint16_t clock_delay_div_4,
-+	uint8_t address,
-+	uint32_t length,
-+	uint8_t *data)
-+{
-+	uint32_t i = 0;
-+
-+	if (!write_byte(ctx, ddc_handle, clock_delay_div_4, address))
-+		return false;
-+
-+	while (i < length) {
-+		if (!read_byte(ctx, ddc_handle, clock_delay_div_4, data + i,
-+			i < length - 1))
-+			return false;
-+		++i;
-+	}
-+
-+	return true;
-+}
-+
-+/*
-+ * @brief
-+ * Cast 'struct i2c_engine *'
-+ * to 'struct i2c_sw_engine *'
-+ */
-+#define FROM_I2C_ENGINE(ptr) \
-+	container_of((ptr), struct i2c_sw_engine, base)
-+
-+/*
-+ * @brief
-+ * Cast 'struct engine *'
-+ * to 'struct i2c_sw_engine *'
-+ */
-+#define FROM_ENGINE(ptr) \
-+	FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-+
-+enum i2caux_engine_type dal_i2c_sw_engine_get_engine_type(
-+	const struct engine *engine)
-+{
-+	return I2CAUX_ENGINE_TYPE_I2C_SW;
-+}
-+
-+bool dal_i2c_sw_engine_submit_request(
-+	struct engine *engine,
-+	struct i2caux_transaction_request *i2caux_request,
-+	bool middle_of_transaction)
-+{
-+	struct i2c_sw_engine *sw_engine = FROM_ENGINE(engine);
-+
-+	struct i2c_engine *base = &sw_engine->base;
-+
-+	struct i2c_request_transaction_data request;
-+	bool operation_succeeded = false;
-+
-+	if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
-+		request.action = middle_of_transaction ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_READ;
-+	else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
-+		request.action = middle_of_transaction ?
-+			I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
-+			I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
-+	else {
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
-+		/* in DAL2, there was no "return false" */
-+		return false;
-+	}
-+
-+	request.address = (uint8_t)i2caux_request->payload.address;
-+	request.length = i2caux_request->payload.length;
-+	request.data = i2caux_request->payload.data;
-+
-+	base->funcs->submit_channel_request(base, &request);
-+
-+	if ((request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY) ||
-+		(request.status == I2C_CHANNEL_OPERATION_FAILED))
-+		i2caux_request->status =
-+			I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY;
-+	else {
-+		enum i2c_channel_operation_result operation_result;
-+
-+		do {
-+			operation_result =
-+				base->funcs->get_channel_status(base, NULL);
-+
-+			switch (operation_result) {
-+			case I2C_CHANNEL_OPERATION_SUCCEEDED:
-+				i2caux_request->status =
-+					I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-+				operation_succeeded = true;
-+			break;
-+			case I2C_CHANNEL_OPERATION_NO_RESPONSE:
-+				i2caux_request->status =
-+					I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-+			break;
-+			case I2C_CHANNEL_OPERATION_TIMEOUT:
-+				i2caux_request->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-+			break;
-+			case I2C_CHANNEL_OPERATION_FAILED:
-+				i2caux_request->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
-+			break;
-+			default:
-+				i2caux_request->status =
-+				I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
-+			break;
-+			}
-+		} while (operation_result == I2C_CHANNEL_OPERATION_ENGINE_BUSY);
-+	}
-+
-+	return operation_succeeded;
-+}
-+
-+uint32_t dal_i2c_sw_engine_get_speed(
-+	const struct i2c_engine *engine)
-+{
-+	return FROM_I2C_ENGINE(engine)->speed;
-+}
-+
-+void dal_i2c_sw_engine_set_speed(
-+	struct i2c_engine *engine,
-+	uint32_t speed)
-+{
-+	struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
-+
-+	ASSERT(speed);
-+
-+	sw_engine->speed = speed ? speed : I2CAUX_DEFAULT_I2C_SW_SPEED;
-+
-+	sw_engine->clock_delay = 1000 / sw_engine->speed;
-+
-+	if (sw_engine->clock_delay < 12)
-+		sw_engine->clock_delay = 12;
-+}
-+
-+bool dal_i2caux_i2c_sw_engine_acquire_engine(
-+	struct i2c_engine *engine,
-+	struct ddc *ddc)
-+{
-+	enum gpio_result result;
-+
-+	result = dal_ddc_open(ddc, GPIO_MODE_FAST_OUTPUT,
-+		GPIO_DDC_CONFIG_TYPE_MODE_I2C);
-+
-+	if (result != GPIO_RESULT_OK)
-+		return false;
-+
-+	engine->base.ddc = ddc;
-+
-+	return true;
-+}
-+
-+void dal_i2c_sw_engine_submit_channel_request(
-+	struct i2c_engine *engine,
-+	struct i2c_request_transaction_data *req)
-+{
-+	struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
-+
-+	struct ddc *ddc = engine->base.ddc;
-+	uint16_t clock_delay_div_4 = sw_engine->clock_delay >> 2;
-+
-+	/* send sync (start / repeated start) */
-+
-+	bool result = start_sync(engine->base.ctx, ddc, clock_delay_div_4);
-+
-+	/* process payload */
-+
-+	if (result) {
-+		switch (req->action) {
-+		case I2CAUX_TRANSACTION_ACTION_I2C_WRITE:
-+		case I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT:
-+			result = i2c_write(engine->base.ctx, ddc, clock_delay_div_4,
-+				req->address, req->length, req->data);
-+		break;
-+		case I2CAUX_TRANSACTION_ACTION_I2C_READ:
-+		case I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT:
-+			result = i2c_read(engine->base.ctx, ddc, clock_delay_div_4,
-+				req->address, req->length, req->data);
-+		break;
-+		default:
-+			result = false;
-+		break;
-+		}
-+	}
-+
-+	/* send stop if not 'mot' or operation failed */
-+
-+	if (!result ||
-+		(req->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
-+		(req->action == I2CAUX_TRANSACTION_ACTION_I2C_READ))
-+		if (!stop_sync(engine->base.ctx, ddc, clock_delay_div_4))
-+			result = false;
-+
-+	req->status = result ?
-+		I2C_CHANNEL_OPERATION_SUCCEEDED :
-+		I2C_CHANNEL_OPERATION_FAILED;
-+}
-+
-+enum i2c_channel_operation_result dal_i2c_sw_engine_get_channel_status(
-+	struct i2c_engine *engine,
-+	uint8_t *returned_bytes)
-+{
-+	/* No arbitration with VBIOS is performed since DCE 6.0 */
-+	return I2C_CHANNEL_OPERATION_SUCCEEDED;
-+}
-+
-+void dal_i2c_sw_engine_destruct(
-+	struct i2c_sw_engine *engine)
-+{
-+	dal_i2c_engine_destruct(&engine->base);
-+}
-+
-+static void destroy(
-+	struct i2c_engine **ptr)
-+{
-+	dal_i2c_sw_engine_destruct(FROM_I2C_ENGINE(*ptr));
-+
-+	kfree(*ptr);
-+	*ptr = NULL;
-+}
-+
-+static const struct i2c_engine_funcs i2c_engine_funcs = {
-+	.acquire_engine = dal_i2caux_i2c_sw_engine_acquire_engine,
-+	.destroy = destroy,
-+	.get_speed = dal_i2c_sw_engine_get_speed,
-+	.set_speed = dal_i2c_sw_engine_set_speed,
-+	.setup_engine = dal_i2c_engine_setup_i2c_engine,
-+	.submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
-+	.process_channel_reply = dal_i2c_engine_process_channel_reply,
-+	.get_channel_status = dal_i2c_sw_engine_get_channel_status,
-+};
-+
-+static void release_engine(
-+	struct engine *engine)
-+{
-+
-+}
-+
-+static const struct engine_funcs engine_funcs = {
-+	.release_engine = release_engine,
-+	.get_engine_type = dal_i2c_sw_engine_get_engine_type,
-+	.acquire = dal_i2c_engine_acquire,
-+	.submit_request = dal_i2c_sw_engine_submit_request,
-+};
-+
-+void dal_i2c_sw_engine_construct(
-+	struct i2c_sw_engine *engine,
-+	const struct i2c_sw_engine_create_arg *arg)
-+{
-+	dal_i2c_engine_construct(&engine->base, arg->ctx);
-+	dal_i2c_sw_engine_set_speed(&engine->base, arg->default_speed);
-+	engine->base.funcs = &i2c_engine_funcs;
-+	engine->base.base.funcs = &engine_funcs;
-+}
-+
-+struct i2c_engine *dal_i2c_sw_engine_create(
-+	const struct i2c_sw_engine_create_arg *arg)
-+{
-+	struct i2c_sw_engine *engine;
-+
-+	if (!arg) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	engine = kzalloc(sizeof(struct i2c_sw_engine), GFP_KERNEL);
-+
-+	if (!engine) {
-+		BREAK_TO_DEBUGGER();
-+		return NULL;
-+	}
-+
-+	dal_i2c_sw_engine_construct(engine, arg);
-+	return &engine->base;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.h.0130~	2017-12-14 06:39:58.435903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.h	2017-12-14 06:39:58.435903581 +0100
-@@ -0,0 +1,81 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2C_SW_ENGINE_H__
-+#define __DAL_I2C_SW_ENGINE_H__
-+
-+enum {
-+	I2C_SW_RETRIES = 10,
-+	I2C_SW_SCL_READ_RETRIES = 128,
-+	/* following value is in microseconds */
-+	I2C_SW_TIMEOUT_DELAY = 3000
-+};
-+
-+struct i2c_sw_engine;
-+
-+struct i2c_sw_engine {
-+	struct i2c_engine base;
-+	uint32_t clock_delay;
-+	/* Values below are in KHz */
-+	uint32_t speed;
-+	uint32_t default_speed;
-+};
-+
-+struct i2c_sw_engine_create_arg {
-+	uint32_t default_speed;
-+	struct dc_context *ctx;
-+};
-+
-+void dal_i2c_sw_engine_construct(
-+	struct i2c_sw_engine *engine,
-+	const struct i2c_sw_engine_create_arg *arg);
-+
-+bool dal_i2caux_i2c_sw_engine_acquire_engine(
-+	struct i2c_engine *engine,
-+	struct ddc *ddc_handle);
-+
-+void dal_i2c_sw_engine_destruct(
-+	struct i2c_sw_engine *engine);
-+
-+struct i2c_engine *dal_i2c_sw_engine_create(
-+	const struct i2c_sw_engine_create_arg *arg);
-+enum i2caux_engine_type dal_i2c_sw_engine_get_engine_type(
-+	const struct engine *engine);
-+bool dal_i2c_sw_engine_submit_request(
-+	struct engine *ptr,
-+	struct i2caux_transaction_request *i2caux_request,
-+	bool middle_of_transaction);
-+uint32_t dal_i2c_sw_engine_get_speed(
-+	const struct i2c_engine *engine);
-+void dal_i2c_sw_engine_set_speed(
-+	struct i2c_engine *ptr,
-+	uint32_t speed);
-+void dal_i2c_sw_engine_submit_channel_request(
-+	struct i2c_engine *ptr,
-+	struct i2c_request_transaction_data *req);
-+enum i2c_channel_operation_result dal_i2c_sw_engine_get_channel_status(
-+	struct i2c_engine *engine,
-+	uint8_t *returned_bytes);
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/Makefile.0130~	2017-12-14 06:39:58.435903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/i2caux/Makefile	2017-12-14 06:39:58.435903581 +0100
-@@ -0,0 +1,78 @@
-+#
-+# Makefile for the 'i2c' sub-component of DAL.
-+# It provides the control and status of HW i2c engine of the adapter.
-+
-+I2CAUX = aux_engine.o engine_base.o i2caux.o i2c_engine.o \
-+	 i2c_generic_hw_engine.o i2c_hw_engine.o i2c_sw_engine.o
-+
-+AMD_DAL_I2CAUX = $(addprefix $(AMDDALPATH)/dc/i2caux/,$(I2CAUX))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX)
-+
-+###############################################################################
-+# DCE 8x family
-+###############################################################################
-+I2CAUX_DCE80 = i2caux_dce80.o i2c_hw_engine_dce80.o \
-+	i2c_sw_engine_dce80.o
-+
-+AMD_DAL_I2CAUX_DCE80 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce80/,$(I2CAUX_DCE80))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE80)
-+
-+###############################################################################
-+# DCE 100 family
-+###############################################################################
-+I2CAUX_DCE100 = i2caux_dce100.o
-+
-+AMD_DAL_I2CAUX_DCE100 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce100/,$(I2CAUX_DCE100))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE100)
-+
-+###############################################################################
-+# DCE 110 family
-+###############################################################################
-+I2CAUX_DCE110 = i2caux_dce110.o i2c_sw_engine_dce110.o i2c_hw_engine_dce110.o \
-+	aux_engine_dce110.o
-+
-+AMD_DAL_I2CAUX_DCE110 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce110/,$(I2CAUX_DCE110))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE110)
-+
-+###############################################################################
-+# DCE 112 family
-+###############################################################################
-+I2CAUX_DCE112 = i2caux_dce112.o
-+
-+AMD_DAL_I2CAUX_DCE112 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce112/,$(I2CAUX_DCE112))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112)
-+
-+###############################################################################
-+# DCN 1.0 family
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DC_DCN1_0
-+I2CAUX_DCN1 = i2caux_dcn10.o
-+
-+AMD_DAL_I2CAUX_DCN1 = $(addprefix $(AMDDALPATH)/dc/i2caux/dcn10/,$(I2CAUX_DCN1))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCN1)
-+endif
-+
-+###############################################################################
-+# DCE 120 family
-+###############################################################################
-+I2CAUX_DCE120 = i2caux_dce120.o
-+
-+AMD_DAL_I2CAUX_DCE120 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce120/,$(I2CAUX_DCE120))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE120)
-+
-+###############################################################################
-+# Diagnostics on FPGA
-+###############################################################################
-+I2CAUX_DIAG = i2caux_diag.o
-+
-+AMD_DAL_I2CAUX_DIAG = $(addprefix $(AMDDALPATH)/dc/i2caux/diagnostics/,$(I2CAUX_DIAG))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DIAG)
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h.0130~	2017-12-14 06:39:58.435903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h	2017-12-14 06:39:58.435903581 +0100
-@@ -0,0 +1,166 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef BW_FIXED_H_
-+#define BW_FIXED_H_
-+
-+#define BW_FIXED_BITS_PER_FRACTIONAL_PART 24
-+
-+#define BW_FIXED_GET_INTEGER_PART(x) ((x) >> BW_FIXED_BITS_PER_FRACTIONAL_PART)
-+struct bw_fixed {
-+	int64_t value;
-+};
-+
-+#define BW_FIXED_MIN_I32 \
-+	(int64_t)(-(1LL << (63 - BW_FIXED_BITS_PER_FRACTIONAL_PART)))
-+
-+#define BW_FIXED_MAX_I32 \
-+	(int64_t)((1ULL << (63 - BW_FIXED_BITS_PER_FRACTIONAL_PART)) - 1)
-+
-+static inline struct bw_fixed bw_min2(const struct bw_fixed arg1,
-+				      const struct bw_fixed arg2)
-+{
-+	return (arg1.value <= arg2.value) ? arg1 : arg2;
-+}
-+
-+static inline struct bw_fixed bw_max2(const struct bw_fixed arg1,
-+				      const struct bw_fixed arg2)
-+{
-+	return (arg2.value <= arg1.value) ? arg1 : arg2;
-+}
-+
-+static inline struct bw_fixed bw_min3(struct bw_fixed v1,
-+				      struct bw_fixed v2,
-+				      struct bw_fixed v3)
-+{
-+	return bw_min2(bw_min2(v1, v2), v3);
-+}
-+
-+static inline struct bw_fixed bw_max3(struct bw_fixed v1,
-+				      struct bw_fixed v2,
-+				      struct bw_fixed v3)
-+{
-+	return bw_max2(bw_max2(v1, v2), v3);
-+}
-+
-+struct bw_fixed bw_int_to_fixed_nonconst(int64_t value);
-+static inline struct bw_fixed bw_int_to_fixed(int64_t value)
-+{
-+	if (__builtin_constant_p(value)) {
-+		struct bw_fixed res;
-+		BUILD_BUG_ON(value > BW_FIXED_MAX_I32 || value < BW_FIXED_MIN_I32);
-+		res.value = value << BW_FIXED_BITS_PER_FRACTIONAL_PART;
-+		return res;
-+	} else
-+		return bw_int_to_fixed_nonconst(value);
-+}
-+
-+static inline int32_t bw_fixed_to_int(struct bw_fixed value)
-+{
-+	return BW_FIXED_GET_INTEGER_PART(value.value);
-+}
-+
-+struct bw_fixed bw_frc_to_fixed(int64_t num, int64_t denum);
-+
-+static inline struct bw_fixed fixed31_32_to_bw_fixed(int64_t raw)
-+{
-+	struct bw_fixed result = { 0 };
-+
-+	if (raw < 0) {
-+		raw = -raw;
-+		result.value = -(raw >> (32 - BW_FIXED_BITS_PER_FRACTIONAL_PART));
-+	} else {
-+		result.value = raw >> (32 - BW_FIXED_BITS_PER_FRACTIONAL_PART);
-+	}
-+
-+	return result;
-+}
-+
-+static inline struct bw_fixed bw_add(const struct bw_fixed arg1,
-+				     const struct bw_fixed arg2)
-+{
-+	struct bw_fixed res;
-+
-+	res.value = arg1.value + arg2.value;
-+
-+	return res;
-+}
-+
-+static inline struct bw_fixed bw_sub(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	struct bw_fixed res;
-+
-+	res.value = arg1.value - arg2.value;
-+
-+	return res;
-+}
-+
-+struct bw_fixed bw_mul(const struct bw_fixed arg1, const struct bw_fixed arg2);
-+static inline struct bw_fixed bw_div(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return bw_frc_to_fixed(arg1.value, arg2.value);
-+}
-+
-+static inline struct bw_fixed bw_mod(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	struct bw_fixed res;
-+	div64_u64_rem(arg1.value, arg2.value, &res.value);
-+	return res;
-+}
-+
-+struct bw_fixed bw_floor2(const struct bw_fixed arg, const struct bw_fixed significance);
-+struct bw_fixed bw_ceil2(const struct bw_fixed arg, const struct bw_fixed significance);
-+
-+static inline bool bw_equ(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return arg1.value == arg2.value;
-+}
-+
-+static inline bool bw_neq(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return arg1.value != arg2.value;
-+}
-+
-+static inline bool bw_leq(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return arg1.value <= arg2.value;
-+}
-+
-+static inline bool bw_meq(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return arg1.value >= arg2.value;
-+}
-+
-+static inline bool bw_ltn(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return arg1.value < arg2.value;
-+}
-+
-+static inline bool bw_mtn(const struct bw_fixed arg1, const struct bw_fixed arg2)
-+{
-+	return arg1.value > arg2.value;
-+}
-+
-+#endif //BW_FIXED_H_
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/clock_source.h.0130~	2017-12-14 06:39:58.435903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/clock_source.h	2017-12-14 06:39:58.435903581 +0100
-@@ -0,0 +1,182 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_CLOCK_SOURCE_H__
-+#define __DC_CLOCK_SOURCE_H__
-+
-+#include "dc_types.h"
-+#include "include/grph_object_id.h"
-+#include "include/bios_parser_types.h"
-+
-+struct clock_source;
-+
-+struct spread_spectrum_data {
-+	uint32_t percentage;		/*> In unit of 0.01% or 0.001%*/
-+	uint32_t percentage_divider;	/*> 100 or 1000	*/
-+	uint32_t freq_range_khz;
-+	uint32_t modulation_freq_hz;
-+
-+	struct spread_spectrum_flags flags;
-+};
-+
-+struct delta_sigma_data {
-+	uint32_t feedback_amount;
-+	uint32_t nfrac_amount;
-+	uint32_t ds_frac_size;
-+	uint32_t ds_frac_amount;
-+};
-+
-+/**
-+ *  Pixel Clock Parameters structure
-+ *  These parameters are required as input
-+ *  when calculating Pixel Clock Dividers for requested Pixel Clock
-+ */
-+struct pixel_clk_flags {
-+	uint32_t ENABLE_SS:1;
-+	uint32_t DISPLAY_BLANKED:1;
-+	uint32_t PROGRAM_PIXEL_CLOCK:1;
-+	uint32_t PROGRAM_ID_CLOCK:1;
-+	uint32_t SUPPORT_YCBCR420:1;
-+};
-+
-+/**
-+ *  Display Port HW De spread of Reference Clock related Parameters structure
-+ *  Store it once at boot for later usage
-+  */
-+struct csdp_ref_clk_ds_params {
-+	bool hw_dso_n_dp_ref_clk;
-+/* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/
-+	uint32_t avg_dp_ref_clk_khz;
-+/* Average DP Reference clock (in KHz)*/
-+	uint32_t ss_percentage_on_dp_ref_clk;
-+/* DP Reference clock SS percentage
-+ * (not to be mixed with DP IDCLK SS from PLL Settings)*/
-+	uint32_t ss_percentage_divider;
-+/* DP Reference clock SS percentage divider */
-+};
-+
-+struct pixel_clk_params {
-+	uint32_t requested_pix_clk; /* in KHz */
-+/*> Requested Pixel Clock
-+ * (based on Video Timing standard used for requested mode)*/
-+	uint32_t requested_sym_clk; /* in KHz */
-+/*> Requested Sym Clock (relevant only for display port)*/
-+	uint32_t dp_ref_clk; /* in KHz */
-+/*> DP reference clock - calculated only for DP signal for specific cases*/
-+	struct graphics_object_id encoder_object_id;
-+/*> Encoder object Id - needed by VBIOS Exec table*/
-+	enum signal_type signal_type;
-+/*> signalType -> Encoder Mode - needed by VBIOS Exec table*/
-+	enum controller_id controller_id;
-+/*> ControllerId - which controller using this PLL*/
-+	enum dc_color_depth color_depth;
-+	struct csdp_ref_clk_ds_params de_spread_params;
-+/*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
-+	enum dc_pixel_encoding pixel_encoding;
-+	struct pixel_clk_flags flags;
-+};
-+
-+/**
-+ *  Pixel Clock Dividers structure with desired Pixel Clock
-+ *  (adjusted after VBIOS exec table),
-+ *  with actually calculated Clock and reference Crystal frequency
-+ */
-+struct pll_settings {
-+	uint32_t actual_pix_clk;
-+	uint32_t adjusted_pix_clk;
-+	uint32_t calculated_pix_clk;
-+	uint32_t vco_freq;
-+	uint32_t reference_freq;
-+	uint32_t reference_divider;
-+	uint32_t feedback_divider;
-+	uint32_t fract_feedback_divider;
-+	uint32_t pix_clk_post_divider;
-+	uint32_t ss_percentage;
-+	bool use_external_clk;
-+};
-+
-+struct calc_pll_clock_source_init_data {
-+	struct dc_bios *bp;
-+	uint32_t min_pix_clk_pll_post_divider;
-+	uint32_t max_pix_clk_pll_post_divider;
-+	uint32_t min_pll_ref_divider;
-+	uint32_t max_pll_ref_divider;
-+	uint32_t min_override_input_pxl_clk_pll_freq_khz;
-+/* if not 0, override the firmware info */
-+
-+	uint32_t max_override_input_pxl_clk_pll_freq_khz;
-+/* if not 0, override the firmware info */
-+
-+	uint32_t num_fract_fb_divider_decimal_point;
-+/* number of decimal point for fractional feedback divider value */
-+
-+	uint32_t num_fract_fb_divider_decimal_point_precision;
-+/* number of decimal point to round off for fractional feedback divider value*/
-+	struct dc_context *ctx;
-+
-+};
-+
-+struct calc_pll_clock_source {
-+	uint32_t ref_freq_khz;
-+	uint32_t min_pix_clock_pll_post_divider;
-+	uint32_t max_pix_clock_pll_post_divider;
-+	uint32_t min_pll_ref_divider;
-+	uint32_t max_pll_ref_divider;
-+
-+	uint32_t max_vco_khz;
-+	uint32_t min_vco_khz;
-+	uint32_t min_pll_input_freq_khz;
-+	uint32_t max_pll_input_freq_khz;
-+
-+	uint32_t fract_fb_divider_decimal_points_num;
-+	uint32_t fract_fb_divider_factor;
-+	uint32_t fract_fb_divider_precision;
-+	uint32_t fract_fb_divider_precision_factor;
-+	struct dc_context *ctx;
-+};
-+
-+struct clock_source_funcs {
-+	bool (*cs_power_down)(
-+			struct clock_source *);
-+	bool (*program_pix_clk)(struct clock_source *,
-+			struct pixel_clk_params *, struct pll_settings *);
-+	uint32_t (*get_pix_clk_dividers)(
-+			struct clock_source *,
-+			struct pixel_clk_params *,
-+			struct pll_settings *);
-+	uint32_t (*get_pix_rate_in_hz)(
-+			struct clock_source *,
-+			struct pixel_clk_params *,
-+			struct pll_settings *);
-+};
-+
-+struct clock_source {
-+	const struct clock_source_funcs *funcs;
-+	struct dc_context *ctx;
-+	enum clock_source_id id;
-+	bool dp_clk_src;
-+};
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/compressor.h.0130~	2017-12-14 06:39:58.435903581 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/compressor.h	2017-12-14 06:39:58.435903581 +0100
-@@ -0,0 +1,136 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_COMPRESSOR_H__
-+#define __DAL_COMPRESSOR_H__
-+
-+#include "include/grph_object_id.h"
-+#include "bios_parser_interface.h"
-+
-+enum fbc_compress_ratio {
-+	FBC_COMPRESS_RATIO_INVALID = 0,
-+	FBC_COMPRESS_RATIO_1TO1 = 1,
-+	FBC_COMPRESS_RATIO_2TO1 = 2,
-+	FBC_COMPRESS_RATIO_4TO1 = 4,
-+	FBC_COMPRESS_RATIO_8TO1 = 8,
-+};
-+
-+union fbc_physical_address {
-+	struct {
-+		uint32_t low_part;
-+		int32_t high_part;
-+	} addr;
-+	uint64_t quad_part;
-+};
-+
-+struct compr_addr_and_pitch_params {
-+	/* enum controller_id controller_id; */
-+	uint32_t inst;
-+	uint32_t source_view_width;
-+	uint32_t source_view_height;
-+};
-+
-+enum fbc_hw_max_resolution_supported {
-+	FBC_MAX_X = 3840,
-+	FBC_MAX_Y = 2400,
-+	FBC_MAX_X_SG = 1920,
-+	FBC_MAX_Y_SG = 1080,
-+};
-+
-+struct compressor;
-+
-+struct compressor_funcs {
-+
-+	void (*power_up_fbc)(struct compressor *cp);
-+	void (*enable_fbc)(struct compressor *cp,
-+		struct compr_addr_and_pitch_params *params);
-+	void (*disable_fbc)(struct compressor *cp);
-+	void (*set_fbc_invalidation_triggers)(struct compressor *cp,
-+		uint32_t fbc_trigger);
-+	void (*surface_address_and_pitch)(
-+		struct compressor *cp,
-+		struct compr_addr_and_pitch_params *params);
-+	bool (*is_fbc_enabled_in_hw)(struct compressor *cp,
-+		uint32_t *fbc_mapped_crtc_id);
-+};
-+struct compressor {
-+	struct dc_context *ctx;
-+	uint32_t attached_inst;
-+	bool is_enabled;
-+	const struct compressor_funcs *funcs;
-+	union {
-+		uint32_t raw;
-+		struct {
-+			uint32_t FBC_SUPPORT:1;
-+			uint32_t FB_POOL:1;
-+			uint32_t DYNAMIC_ALLOC:1;
-+			uint32_t LPT_SUPPORT:1;
-+			uint32_t LPT_MC_CONFIG:1;
-+			uint32_t DUMMY_BACKEND:1;
-+			uint32_t CLK_GATING_DISABLED:1;
-+
-+		} bits;
-+	} options;
-+
-+	union fbc_physical_address compr_surface_address;
-+
-+	uint32_t embedded_panel_h_size;
-+	uint32_t embedded_panel_v_size;
-+	uint32_t memory_bus_width;
-+	uint32_t banks_num;
-+	uint32_t raw_size;
-+	uint32_t channel_interleave_size;
-+	uint32_t dram_channels_num;
-+
-+	uint32_t allocated_size;
-+	uint32_t preferred_requested_size;
-+	uint32_t lpt_channels_num;
-+	enum fbc_compress_ratio min_compress_ratio;
-+};
-+
-+struct fbc_input_info {
-+	bool           dynamic_fbc_buffer_alloc;
-+	unsigned int   source_view_width;
-+	unsigned int   source_view_height;
-+	unsigned int   num_of_active_targets;
-+};
-+
-+
-+struct fbc_requested_compressed_size {
-+	unsigned int   preferred_size;
-+	unsigned int   preferred_size_alignment;
-+	unsigned int   min_size;
-+	unsigned int   min_size_alignment;
-+	union {
-+		struct {
-+			/* Above preferedSize must be allocated in FB pool */
-+			unsigned int preferred_must_be_framebuffer_pool : 1;
-+			/* Above minSize must be allocated in FB pool */
-+			unsigned int min_must_be_framebuffer_pool : 1;
-+		} bits;
-+		unsigned int flags;
-+	};
-+};
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/core_status.h.0130~	2017-12-14 06:39:58.436903582 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/core_status.h	2017-12-14 06:39:58.436903582 +0100
-@@ -0,0 +1,50 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef _CORE_STATUS_H_
-+#define _CORE_STATUS_H_
-+
-+enum dc_status {
-+	DC_OK = 1,
-+
-+	DC_NO_CONTROLLER_RESOURCE = 2,
-+	DC_NO_STREAM_ENG_RESOURCE = 3,
-+	DC_NO_CLOCK_SOURCE_RESOURCE = 4,
-+	DC_FAIL_CONTROLLER_VALIDATE = 5,
-+	DC_FAIL_ENC_VALIDATE = 6,
-+	DC_FAIL_ATTACH_SURFACES = 7,
-+	DC_FAIL_DETACH_SURFACES = 8,
-+	DC_FAIL_SURFACE_VALIDATE = 9,
-+	DC_NO_DP_LINK_BANDWIDTH = 10,
-+	DC_EXCEED_DONGLE_CAP = 11,
-+	DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED = 12,
-+	DC_FAIL_BANDWIDTH_VALIDATE = 13, /* BW and Watermark validation */
-+	DC_FAIL_SCALING = 14,
-+	DC_FAIL_DP_LINK_TRAINING = 15,
-+
-+	DC_ERROR_UNEXPECTED = -1
-+};
-+
-+#endif /* _CORE_STATUS_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/core_types.h.0130~	2017-12-14 06:39:58.436903582 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/core_types.h	2017-12-14 06:39:58.436903582 +0100
-@@ -0,0 +1,284 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef _CORE_TYPES_H_
-+#define _CORE_TYPES_H_
-+
-+#include "dc.h"
-+#include "dce_calcs.h"
-+#include "dcn_calcs.h"
-+#include "ddc_service_types.h"
-+#include "dc_bios_types.h"
-+#include "mem_input.h"
-+#include "hubp.h"
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+#include "mpc.h"
-+#endif
-+
-+#define MAX_CLOCK_SOURCES 7
-+
-+void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
-+		uint32_t controller_id);
-+
-+#include "grph_object_id.h"
-+#include "link_encoder.h"
-+#include "stream_encoder.h"
-+#include "clock_source.h"
-+#include "audio.h"
-+#include "dm_pp_smu.h"
-+
-+
-+/************ link *****************/
-+struct link_init_data {
-+	const struct dc *dc;
-+	struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
-+	uint32_t connector_index; /* this will be mapped to the HPD pins */
-+	uint32_t link_index; /* this is mapped to DAL display_index
-+				TODO: remove it when DC is complete. */
-+};
-+
-+enum {
-+	FREE_ACQUIRED_RESOURCE = 0,
-+	KEEP_ACQUIRED_RESOURCE = 1,
-+};
-+
-+struct dc_link *link_create(const struct link_init_data *init_params);
-+void link_destroy(struct dc_link **link);
-+
-+enum dc_status dc_link_validate_mode_timing(
-+		const struct dc_stream_state *stream,
-+		struct dc_link *link,
-+		const struct dc_crtc_timing *timing);
-+
-+void core_link_resume(struct dc_link *link);
-+
-+void core_link_enable_stream(
-+		struct dc_state *state,
-+		struct pipe_ctx *pipe_ctx);
-+
-+void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option);
-+
-+void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
-+/********** DAL Core*********************/
-+#include "display_clock.h"
-+#include "transform.h"
-+#include "dpp.h"
-+
-+struct resource_pool;
-+struct dc_state;
-+struct resource_context;
-+
-+struct resource_funcs {
-+	void (*destroy)(struct resource_pool **pool);
-+	struct link_encoder *(*link_enc_create)(
-+			const struct encoder_init_data *init);
-+
-+	enum dc_status (*validate_guaranteed)(
-+					struct dc *dc,
-+					struct dc_stream_state *stream,
-+					struct dc_state *context);
-+
-+	bool (*validate_bandwidth)(
-+					struct dc *dc,
-+					struct dc_state *context);
-+
-+	enum dc_status (*validate_global)(
-+		struct dc *dc,
-+		struct dc_state *context);
-+
-+	struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
-+			struct dc_state *context,
-+			const struct resource_pool *pool,
-+			struct dc_stream_state *stream);
-+
-+	enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps);
-+
-+	enum dc_status (*add_stream_to_ctx)(
-+			struct dc *dc,
-+			struct dc_state *new_ctx,
-+			struct dc_stream_state *dc_stream);
-+};
-+
-+struct audio_support{
-+	bool dp_audio;
-+	bool hdmi_audio_on_dongle;
-+	bool hdmi_audio_native;
-+};
-+
-+#define NO_UNDERLAY_PIPE -1
-+
-+struct resource_pool {
-+	struct mem_input *mis[MAX_PIPES];
-+	struct hubp *hubps[MAX_PIPES];
-+	struct input_pixel_processor *ipps[MAX_PIPES];
-+	struct transform *transforms[MAX_PIPES];
-+	struct dpp *dpps[MAX_PIPES];
-+	struct output_pixel_processor *opps[MAX_PIPES];
-+	struct timing_generator *timing_generators[MAX_PIPES];
-+	struct stream_encoder *stream_enc[MAX_PIPES * 2];
-+
-+	struct hubbub *hubbub;
-+	struct mpc *mpc;
-+	struct pp_smu_funcs_rv *pp_smu;
-+	struct pp_smu_display_requirement_rv pp_smu_req;
-+
-+	unsigned int pipe_count;
-+	unsigned int underlay_pipe_index;
-+	unsigned int stream_enc_count;
-+	unsigned int ref_clock_inKhz;
-+
-+	/*
-+	 * reserved clock source for DP
-+	 */
-+	struct clock_source *dp_clock_source;
-+
-+	struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
-+	unsigned int clk_src_count;
-+
-+	struct audio *audios[MAX_PIPES];
-+	unsigned int audio_count;
-+	struct audio_support audio_support;
-+
-+	struct display_clock *display_clock;
-+	struct irq_service *irqs;
-+
-+	struct abm *abm;
-+	struct dmcu *dmcu;
-+
-+	const struct resource_funcs *funcs;
-+	const struct resource_caps *res_cap;
-+};
-+
-+struct stream_resource {
-+	struct output_pixel_processor *opp;
-+	struct timing_generator *tg;
-+	struct stream_encoder *stream_enc;
-+	struct audio *audio;
-+
-+	struct pixel_clk_params pix_clk_params;
-+	struct encoder_info_frame encoder_info_frame;
-+};
-+
-+struct plane_resource {
-+	struct scaler_data scl_data;
-+	struct hubp *hubp;
-+	struct mem_input *mi;
-+	struct input_pixel_processor *ipp;
-+	struct transform *xfm;
-+	struct dpp *dpp;
-+};
-+
-+struct pipe_ctx {
-+	struct dc_plane_state *plane_state;
-+	struct dc_stream_state *stream;
-+
-+	struct plane_resource plane_res;
-+	struct stream_resource stream_res;
-+
-+	struct clock_source *clock_source;
-+
-+	struct pll_settings pll_settings;
-+
-+	uint8_t pipe_idx;
-+
-+	struct pipe_ctx *top_pipe;
-+	struct pipe_ctx *bottom_pipe;
-+
-+#ifdef CONFIG_DRM_AMD_DC_DCN1_0
-+	struct _vcs_dpi_display_dlg_regs_st dlg_regs;
-+	struct _vcs_dpi_display_ttu_regs_st ttu_regs;
-+	struct _vcs_dpi_display_rq_regs_st rq_regs;
-+	struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
-+#endif
-+	struct dwbc *dwbc;
-+};
-+
-+struct resource_context {
-+	struct pipe_ctx pipe_ctx[MAX_PIPES];
-+	bool is_stream_enc_acquired[MAX_PIPES * 2];
-+	bool is_audio_acquired[MAX_PIPES];
-+	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
-+	uint8_t dp_clock_source_ref_count;
-+};
-+
-+struct dce_bw_output {
-+	bool cpuc_state_change_enable;
-+	bool cpup_state_change_enable;
-+	bool stutter_mode_enable;
-+	bool nbp_state_change_enable;
-+	bool all_displays_in_sync;
-+	struct dce_watermarks urgent_wm_ns[MAX_PIPES];
-+	struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
-+	struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
-+	int sclk_khz;
-+	int sclk_deep_sleep_khz;
-+	int yclk_khz;
-+	int dispclk_khz;
-+	int blackout_recovery_time_us;
-+};
-+
-+struct dcn_bw_clocks {
-+	int dispclk_khz;
-+	bool dppclk_div;
-+	int dcfclk_khz;
-+	int dcfclk_deep_sleep_khz;
-+	int fclk_khz;
-+	int dram_ccm_us;
-+	int min_active_dram_ccm_us;
-+};
-+
-+struct dcn_bw_output {
-+	struct dcn_bw_clocks cur_clk;
-+	struct dcn_bw_clocks calc_clk;
-+	struct dcn_watermark_set watermarks;
-+};
-+
-+union bw_context {
-+	struct dcn_bw_output dcn;
-+	struct dce_bw_output dce;
-+};
-+
-+struct dc_state {
-+	struct dc_stream_state *streams[MAX_PIPES];
-+	struct dc_stream_status stream_status[MAX_PIPES];
-+	uint8_t stream_count;
-+
-+	struct resource_context res_ctx;
-+
-+	/* The output from BW and WM calculations. */
-+	union bw_context bw;
-+
-+	/* Note: these are big structures, do *not* put on stack! */
-+	struct dm_pp_display_configuration pp_display_cfg;
-+#ifdef CONFIG_DRM_AMD_DC_DCN1_0
-+	struct dcn_bw_internal_vars dcn_bw_vars;
-+#endif
-+
-+	struct display_clock *dis_clk;
-+
-+	struct kref refcount;
-+};
-+
-+#endif /* _CORE_TYPES_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/custom_float.h.0130~	2017-12-14 06:39:58.436903582 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/custom_float.h	2017-12-14 06:39:58.436903582 +0100
-@@ -0,0 +1,40 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef CUSTOM_FLOAT_H_
-+#define CUSTOM_FLOAT_H_
-+
-+#include "bw_fixed.h"
-+#include "hw_shared.h"
-+#include "opp.h"
-+
-+
-+bool convert_to_custom_float_format(
-+	struct fixed31_32 value,
-+	const struct custom_float_format *format,
-+	uint32_t *result);
-+
-+
-+#endif //CUSTOM_FLOAT_H_
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h.0130~	2017-12-14 06:39:58.436903582 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h	2017-12-14 06:39:58.436903582 +0100
-@@ -0,0 +1,481 @@
-+/*
-+ * Copyright 2015-2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/**
-+ * Bandwidth and Watermark calculations interface.
-+ * (Refer to "DCEx_mode_support.xlsm" from Perforce.)
-+ */
-+#ifndef __DCE_CALCS_H__
-+#define __DCE_CALCS_H__
-+
-+#include "bw_fixed.h"
-+
-+struct pipe_ctx;
-+struct dc;
-+struct dc_state;
-+struct dce_bw_output;
-+
-+enum bw_calcs_version {
-+	BW_CALCS_VERSION_INVALID,
-+	BW_CALCS_VERSION_CARRIZO,
-+	BW_CALCS_VERSION_POLARIS10,
-+	BW_CALCS_VERSION_POLARIS11,
-+	BW_CALCS_VERSION_STONEY,
-+	BW_CALCS_VERSION_VEGA10
-+};
-+
-+/*******************************************************************************
-+ * There are three types of input into Calculations:
-+ * 1. per-DCE static values - these are "hardcoded" properties of the DCEIP
-+ * 2. board-level values - these are generally coming from VBIOS parser
-+ * 3. mode/configuration values - depending Mode, Scaling number of Displays etc.
-+ ******************************************************************************/
-+
-+enum bw_defines {
-+	//Common
-+	bw_def_no = 0,
-+	bw_def_none = 0,
-+	bw_def_yes = 1,
-+	bw_def_ok = 1,
-+	bw_def_high = 2,
-+	bw_def_mid = 1,
-+	bw_def_low = 0,
-+
-+	//Internal
-+	bw_defs_start = 255,
-+	bw_def_underlay422,
-+	bw_def_underlay420_luma,
-+	bw_def_underlay420_chroma,
-+	bw_def_underlay444,
-+	bw_def_graphics,
-+	bw_def_display_write_back420_luma,
-+	bw_def_display_write_back420_chroma,
-+	bw_def_portrait,
-+	bw_def_hsr_mtn_4,
-+	bw_def_hsr_mtn_h_taps,
-+	bw_def_ceiling__h_taps_div_4___meq_hsr,
-+	bw_def_invalid_linear_or_stereo_mode,
-+	bw_def_invalid_rotation_or_bpp_or_stereo,
-+	bw_def_vsr_mtn_v_taps,
-+	bw_def_vsr_mtn_4,
-+	bw_def_auto,
-+	bw_def_manual,
-+	bw_def_exceeded_allowed_maximum_sclk,
-+	bw_def_exceeded_allowed_page_close_open,
-+	bw_def_exceeded_allowed_outstanding_pte_req_queue_size,
-+	bw_def_exceeded_allowed_maximum_bw,
-+	bw_def_landscape,
-+
-+	//Panning and bezel
-+	bw_def_any_lines,
-+
-+	//Underlay mode
-+	bw_def_underlay_only,
-+	bw_def_blended,
-+	bw_def_blend,
-+
-+	//Stereo mode
-+	bw_def_mono,
-+	bw_def_side_by_side,
-+	bw_def_top_bottom,
-+
-+	//Underlay surface type
-+	bw_def_420,
-+	bw_def_422,
-+	bw_def_444,
-+
-+	//Tiling mode
-+	bw_def_linear,
-+	bw_def_tiled,
-+	bw_def_array_linear_general,
-+	bw_def_array_linear_aligned,
-+	bw_def_rotated_micro_tiling,
-+	bw_def_display_micro_tiling,
-+
-+	//Memory type
-+	bw_def_gddr5,
-+	bw_def_hbm,
-+
-+	//Voltage
-+	bw_def_high_no_nbp_state_change,
-+	bw_def_0_72,
-+	bw_def_0_8,
-+	bw_def_0_9,
-+
-+	bw_def_notok = -1,
-+	bw_def_na = -1
-+};
-+
-+struct bw_calcs_dceip {
-+	enum bw_calcs_version version;
-+	bool large_cursor;
-+	uint32_t cursor_max_outstanding_group_num;
-+	bool dmif_pipe_en_fbc_chunk_tracker;
-+	struct bw_fixed dmif_request_buffer_size;
-+	uint32_t lines_interleaved_into_lb;
-+	uint32_t low_power_tiling_mode;
-+	uint32_t chunk_width;
-+	uint32_t number_of_graphics_pipes;
-+	uint32_t number_of_underlay_pipes;
-+	bool display_write_back_supported;
-+	bool argb_compression_support;
-+	struct bw_fixed underlay_vscaler_efficiency6_bit_per_component;
-+	struct bw_fixed underlay_vscaler_efficiency8_bit_per_component;
-+	struct bw_fixed underlay_vscaler_efficiency10_bit_per_component;
-+	struct bw_fixed underlay_vscaler_efficiency12_bit_per_component;
-+	struct bw_fixed graphics_vscaler_efficiency6_bit_per_component;
-+	struct bw_fixed graphics_vscaler_efficiency8_bit_per_component;
-+	struct bw_fixed graphics_vscaler_efficiency10_bit_per_component;
-+	struct bw_fixed graphics_vscaler_efficiency12_bit_per_component;
-+	struct bw_fixed alpha_vscaler_efficiency;
-+	uint32_t max_dmif_buffer_allocated;
-+	uint32_t graphics_dmif_size;
-+	uint32_t underlay_luma_dmif_size;
-+	uint32_t underlay_chroma_dmif_size;
-+	bool pre_downscaler_enabled;
-+	bool underlay_downscale_prefetch_enabled;
-+	struct bw_fixed lb_write_pixels_per_dispclk;
-+	struct bw_fixed lb_size_per_component444;
-+	bool graphics_lb_nodownscaling_multi_line_prefetching;
-+	struct bw_fixed stutter_and_dram_clock_state_change_gated_before_cursor;
-+	struct bw_fixed underlay420_luma_lb_size_per_component;
-+	struct bw_fixed underlay420_chroma_lb_size_per_component;
-+	struct bw_fixed underlay422_lb_size_per_component;
-+	struct bw_fixed cursor_chunk_width;
-+	struct bw_fixed cursor_dcp_buffer_lines;
-+	struct bw_fixed underlay_maximum_width_efficient_for_tiling;
-+	struct bw_fixed underlay_maximum_height_efficient_for_tiling;
-+	struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display;
-+	struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation;
-+	struct bw_fixed minimum_outstanding_pte_request_limit;
-+	struct bw_fixed maximum_total_outstanding_pte_requests_allowed_by_saw;
-+	bool limit_excessive_outstanding_dmif_requests;
-+	struct bw_fixed linear_mode_line_request_alternation_slice;
-+	uint32_t scatter_gather_lines_of_pte_prefetching_in_linear_mode;
-+	uint32_t display_write_back420_luma_mcifwr_buffer_size;
-+	uint32_t display_write_back420_chroma_mcifwr_buffer_size;
-+	struct bw_fixed request_efficiency;
-+	struct bw_fixed dispclk_per_request;
-+	struct bw_fixed dispclk_ramping_factor;
-+	struct bw_fixed display_pipe_throughput_factor;
-+	uint32_t scatter_gather_pte_request_rows_in_tiling_mode;
-+	struct bw_fixed mcifwr_all_surfaces_burst_time;
-+};
-+
-+struct bw_calcs_vbios {
-+	enum bw_defines memory_type;
-+	uint32_t dram_channel_width_in_bits;
-+	uint32_t number_of_dram_channels;
-+	uint32_t number_of_dram_banks;
-+	struct bw_fixed low_yclk; /*m_hz*/
-+	struct bw_fixed mid_yclk; /*m_hz*/
-+	struct bw_fixed high_yclk; /*m_hz*/
-+	struct bw_fixed low_sclk; /*m_hz*/
-+	struct bw_fixed mid1_sclk; /*m_hz*/
-+	struct bw_fixed mid2_sclk; /*m_hz*/
-+	struct bw_fixed mid3_sclk; /*m_hz*/
-+	struct bw_fixed mid4_sclk; /*m_hz*/
-+	struct bw_fixed mid5_sclk; /*m_hz*/
-+	struct bw_fixed mid6_sclk; /*m_hz*/
-+	struct bw_fixed high_sclk; /*m_hz*/
-+	struct bw_fixed low_voltage_max_dispclk; /*m_hz*/
-+	struct bw_fixed mid_voltage_max_dispclk; /*m_hz*/
-+	struct bw_fixed high_voltage_max_dispclk; /*m_hz*/
-+	struct bw_fixed low_voltage_max_phyclk;
-+	struct bw_fixed mid_voltage_max_phyclk;
-+	struct bw_fixed high_voltage_max_phyclk;
-+	struct bw_fixed data_return_bus_width;
-+	struct bw_fixed trc;
-+	struct bw_fixed dmifmc_urgent_latency;
-+	struct bw_fixed stutter_self_refresh_exit_latency;
-+	struct bw_fixed stutter_self_refresh_entry_latency;
-+	struct bw_fixed nbp_state_change_latency;
-+	struct bw_fixed mcifwrmc_urgent_latency;
-+	bool scatter_gather_enable;
-+	struct bw_fixed down_spread_percentage;
-+	uint32_t cursor_width;
-+	uint32_t average_compression_rate;
-+	uint32_t number_of_request_slots_gmc_reserves_for_dmif_per_channel;
-+	struct bw_fixed blackout_duration;
-+	struct bw_fixed maximum_blackout_recovery_time;
-+};
-+
-+/*******************************************************************************
-+ * Temporary data structure(s).
-+ ******************************************************************************/
-+#define maximum_number_of_surfaces 12
-+/*Units : MHz, us */
-+
-+struct bw_calcs_data {
-+	/* data for all displays */
-+	uint32_t number_of_displays;
-+	enum bw_defines underlay_surface_type;
-+	enum bw_defines panning_and_bezel_adjustment;
-+	enum bw_defines graphics_tiling_mode;
-+	uint32_t graphics_lb_bpc;
-+	uint32_t underlay_lb_bpc;
-+	enum bw_defines underlay_tiling_mode;
-+	enum bw_defines d0_underlay_mode;
-+	bool d1_display_write_back_dwb_enable;
-+	enum bw_defines d1_underlay_mode;
-+
-+	bool cpup_state_change_enable;
-+	bool cpuc_state_change_enable;
-+	bool nbp_state_change_enable;
-+	bool stutter_mode_enable;
-+	uint32_t y_clk_level;
-+	uint32_t sclk_level;
-+	uint32_t number_of_underlay_surfaces;
-+	uint32_t number_of_dram_wrchannels;
-+	uint32_t chunk_request_delay;
-+	uint32_t number_of_dram_channels;
-+	enum bw_defines underlay_micro_tile_mode;
-+	enum bw_defines graphics_micro_tile_mode;
-+	struct bw_fixed max_phyclk;
-+	struct bw_fixed dram_efficiency;
-+	struct bw_fixed src_width_after_surface_type;
-+	struct bw_fixed src_height_after_surface_type;
-+	struct bw_fixed hsr_after_surface_type;
-+	struct bw_fixed vsr_after_surface_type;
-+	struct bw_fixed src_width_after_rotation;
-+	struct bw_fixed src_height_after_rotation;
-+	struct bw_fixed hsr_after_rotation;
-+	struct bw_fixed vsr_after_rotation;
-+	struct bw_fixed source_height_pixels;
-+	struct bw_fixed hsr_after_stereo;
-+	struct bw_fixed vsr_after_stereo;
-+	struct bw_fixed source_width_in_lb;
-+	struct bw_fixed lb_line_pitch;
-+	struct bw_fixed underlay_maximum_source_efficient_for_tiling;
-+	struct bw_fixed num_lines_at_frame_start;
-+	struct bw_fixed min_dmif_size_in_time;
-+	struct bw_fixed min_mcifwr_size_in_time;
-+	struct bw_fixed total_requests_for_dmif_size;
-+	struct bw_fixed peak_pte_request_to_eviction_ratio_limiting;
-+	struct bw_fixed useful_pte_per_pte_request;
-+	struct bw_fixed scatter_gather_pte_request_rows;
-+	struct bw_fixed scatter_gather_row_height;
-+	struct bw_fixed scatter_gather_pte_requests_in_vblank;
-+	struct bw_fixed inefficient_linear_pitch_in_bytes;
-+	struct bw_fixed cursor_total_data;
-+	struct bw_fixed cursor_total_request_groups;
-+	struct bw_fixed scatter_gather_total_pte_requests;
-+	struct bw_fixed scatter_gather_total_pte_request_groups;
-+	struct bw_fixed tile_width_in_pixels;
-+	struct bw_fixed dmif_total_number_of_data_request_page_close_open;
-+	struct bw_fixed mcifwr_total_number_of_data_request_page_close_open;
-+	struct bw_fixed bytes_per_page_close_open;
-+	struct bw_fixed mcifwr_total_page_close_open_time;
-+	struct bw_fixed total_requests_for_adjusted_dmif_size;
-+	struct bw_fixed total_dmifmc_urgent_trips;
-+	struct bw_fixed total_dmifmc_urgent_latency;
-+	struct bw_fixed total_display_reads_required_data;
-+	struct bw_fixed total_display_reads_required_dram_access_data;
-+	struct bw_fixed total_display_writes_required_data;
-+	struct bw_fixed total_display_writes_required_dram_access_data;
-+	struct bw_fixed display_reads_required_data;
-+	struct bw_fixed display_reads_required_dram_access_data;
-+	struct bw_fixed dmif_total_page_close_open_time;
-+	struct bw_fixed min_cursor_memory_interface_buffer_size_in_time;
-+	struct bw_fixed min_read_buffer_size_in_time;
-+	struct bw_fixed display_reads_time_for_data_transfer;
-+	struct bw_fixed display_writes_time_for_data_transfer;
-+	struct bw_fixed dmif_required_dram_bandwidth;
-+	struct bw_fixed mcifwr_required_dram_bandwidth;
-+	struct bw_fixed required_dmifmc_urgent_latency_for_page_close_open;
-+	struct bw_fixed required_mcifmcwr_urgent_latency;
-+	struct bw_fixed required_dram_bandwidth_gbyte_per_second;
-+	struct bw_fixed dram_bandwidth;
-+	struct bw_fixed dmif_required_sclk;
-+	struct bw_fixed mcifwr_required_sclk;
-+	struct bw_fixed required_sclk;
-+	struct bw_fixed downspread_factor;
-+	struct bw_fixed v_scaler_efficiency;
-+	struct bw_fixed scaler_limits_factor;
-+	struct bw_fixed display_pipe_pixel_throughput;
-+	struct bw_fixed total_dispclk_required_with_ramping;
-+	struct bw_fixed total_dispclk_required_without_ramping;
-+	struct bw_fixed total_read_request_bandwidth;
-+	struct bw_fixed total_write_request_bandwidth;
-+	struct bw_fixed dispclk_required_for_total_read_request_bandwidth;
-+	struct bw_fixed total_dispclk_required_with_ramping_with_request_bandwidth;
-+	struct bw_fixed total_dispclk_required_without_ramping_with_request_bandwidth;
-+	struct bw_fixed dispclk;
-+	struct bw_fixed blackout_recovery_time;
-+	struct bw_fixed min_pixels_per_data_fifo_entry;
-+	struct bw_fixed sclk_deep_sleep;
-+	struct bw_fixed chunk_request_time;
-+	struct bw_fixed cursor_request_time;
-+	struct bw_fixed line_source_pixels_transfer_time;
-+	struct bw_fixed dmifdram_access_efficiency;
-+	struct bw_fixed mcifwrdram_access_efficiency;
-+	struct bw_fixed total_average_bandwidth_no_compression;
-+	struct bw_fixed total_average_bandwidth;
-+	struct bw_fixed total_stutter_cycle_duration;
-+	struct bw_fixed stutter_burst_time;
-+	struct bw_fixed time_in_self_refresh;
-+	struct bw_fixed stutter_efficiency;
-+	struct bw_fixed worst_number_of_trips_to_memory;
-+	struct bw_fixed immediate_flip_time;
-+	struct bw_fixed latency_for_non_dmif_clients;
-+	struct bw_fixed latency_for_non_mcifwr_clients;
-+	struct bw_fixed dmifmc_urgent_latency_supported_in_high_sclk_and_yclk;
-+	struct bw_fixed nbp_state_dram_speed_change_margin;
-+	struct bw_fixed display_reads_time_for_data_transfer_and_urgent_latency;
-+	struct bw_fixed dram_speed_change_margin;
-+	struct bw_fixed min_vblank_dram_speed_change_margin;
-+	struct bw_fixed min_stutter_refresh_duration;
-+	uint32_t total_stutter_dmif_buffer_size;
-+	uint32_t total_bytes_requested;
-+	uint32_t min_stutter_dmif_buffer_size;
-+	uint32_t num_stutter_bursts;
-+	struct bw_fixed v_blank_nbp_state_dram_speed_change_latency_supported;
-+	struct bw_fixed nbp_state_dram_speed_change_latency_supported;
-+	bool fbc_en[maximum_number_of_surfaces];
-+	bool lpt_en[maximum_number_of_surfaces];
-+	bool displays_match_flag[maximum_number_of_surfaces];
-+	bool use_alpha[maximum_number_of_surfaces];
-+	bool orthogonal_rotation[maximum_number_of_surfaces];
-+	bool enable[maximum_number_of_surfaces];
-+	bool access_one_channel_only[maximum_number_of_surfaces];
-+	bool scatter_gather_enable_for_pipe[maximum_number_of_surfaces];
-+	bool interlace_mode[maximum_number_of_surfaces];
-+	bool display_pstate_change_enable[maximum_number_of_surfaces];
-+	bool line_buffer_prefetch[maximum_number_of_surfaces];
-+	uint32_t bytes_per_pixel[maximum_number_of_surfaces];
-+	uint32_t max_chunks_non_fbc_mode[maximum_number_of_surfaces];
-+	uint32_t lb_bpc[maximum_number_of_surfaces];
-+	uint32_t output_bpphdmi[maximum_number_of_surfaces];
-+	uint32_t output_bppdp4_lane_hbr[maximum_number_of_surfaces];
-+	uint32_t output_bppdp4_lane_hbr2[maximum_number_of_surfaces];
-+	uint32_t output_bppdp4_lane_hbr3[maximum_number_of_surfaces];
-+	enum bw_defines stereo_mode[maximum_number_of_surfaces];
-+	struct bw_fixed dmif_buffer_transfer_time[maximum_number_of_surfaces];
-+	struct bw_fixed displays_with_same_mode[maximum_number_of_surfaces];
-+	struct bw_fixed stutter_dmif_buffer_size[maximum_number_of_surfaces];
-+	struct bw_fixed stutter_refresh_duration[maximum_number_of_surfaces];
-+	struct bw_fixed stutter_exit_watermark[maximum_number_of_surfaces];
-+	struct bw_fixed stutter_entry_watermark[maximum_number_of_surfaces];
-+	struct bw_fixed h_total[maximum_number_of_surfaces];
-+	struct bw_fixed v_total[maximum_number_of_surfaces];
-+	struct bw_fixed pixel_rate[maximum_number_of_surfaces];
-+	struct bw_fixed src_width[maximum_number_of_surfaces];
-+	struct bw_fixed pitch_in_pixels[maximum_number_of_surfaces];
-+	struct bw_fixed pitch_in_pixels_after_surface_type[maximum_number_of_surfaces];
-+	struct bw_fixed src_height[maximum_number_of_surfaces];
-+	struct bw_fixed scale_ratio[maximum_number_of_surfaces];
-+	struct bw_fixed h_taps[maximum_number_of_surfaces];
-+	struct bw_fixed v_taps[maximum_number_of_surfaces];
-+	struct bw_fixed h_scale_ratio[maximum_number_of_surfaces];
-+	struct bw_fixed v_scale_ratio[maximum_number_of_surfaces];
-+	struct bw_fixed rotation_angle[maximum_number_of_surfaces];
-+	struct bw_fixed compression_rate[maximum_number_of_surfaces];
-+	struct bw_fixed hsr[maximum_number_of_surfaces];
-+	struct bw_fixed vsr[maximum_number_of_surfaces];
-+	struct bw_fixed source_width_rounded_up_to_chunks[maximum_number_of_surfaces];
-+	struct bw_fixed source_width_pixels[maximum_number_of_surfaces];
-+	struct bw_fixed source_height_rounded_up_to_chunks[maximum_number_of_surfaces];
-+	struct bw_fixed display_bandwidth[maximum_number_of_surfaces];
-+	struct bw_fixed request_bandwidth[maximum_number_of_surfaces];
-+	struct bw_fixed bytes_per_request[maximum_number_of_surfaces];
-+	struct bw_fixed useful_bytes_per_request[maximum_number_of_surfaces];
-+	struct bw_fixed lines_interleaved_in_mem_access[maximum_number_of_surfaces];
-+	struct bw_fixed latency_hiding_lines[maximum_number_of_surfaces];
-+	struct bw_fixed lb_partitions[maximum_number_of_surfaces];
-+	struct bw_fixed lb_partitions_max[maximum_number_of_surfaces];
-+	struct bw_fixed dispclk_required_with_ramping[maximum_number_of_surfaces];
-+	struct bw_fixed dispclk_required_without_ramping[maximum_number_of_surfaces];
-+	struct bw_fixed data_buffer_size[maximum_number_of_surfaces];
-+	struct bw_fixed outstanding_chunk_request_limit[maximum_number_of_surfaces];
-+	struct bw_fixed urgent_watermark[maximum_number_of_surfaces];
-+	struct bw_fixed nbp_state_change_watermark[maximum_number_of_surfaces];
-+	struct bw_fixed v_filter_init[maximum_number_of_surfaces];
-+	struct bw_fixed stutter_cycle_duration[maximum_number_of_surfaces];
-+	struct bw_fixed average_bandwidth[maximum_number_of_surfaces];
-+	struct bw_fixed average_bandwidth_no_compression[maximum_number_of_surfaces];
-+	struct bw_fixed scatter_gather_pte_request_limit[maximum_number_of_surfaces];
-+	struct bw_fixed lb_size_per_component[maximum_number_of_surfaces];
-+	struct bw_fixed memory_chunk_size_in_bytes[maximum_number_of_surfaces];
-+	struct bw_fixed pipe_chunk_size_in_bytes[maximum_number_of_surfaces];
-+	struct bw_fixed number_of_trips_to_memory_for_getting_apte_row[maximum_number_of_surfaces];
-+	struct bw_fixed adjusted_data_buffer_size[maximum_number_of_surfaces];
-+	struct bw_fixed adjusted_data_buffer_size_in_memory[maximum_number_of_surfaces];
-+	struct bw_fixed pixels_per_data_fifo_entry[maximum_number_of_surfaces];
-+	struct bw_fixed scatter_gather_pte_requests_in_row[maximum_number_of_surfaces];
-+	struct bw_fixed pte_request_per_chunk[maximum_number_of_surfaces];
-+	struct bw_fixed scatter_gather_page_width[maximum_number_of_surfaces];
-+	struct bw_fixed scatter_gather_page_height[maximum_number_of_surfaces];
-+	struct bw_fixed lb_lines_in_per_line_out_in_beginning_of_frame[maximum_number_of_surfaces];
-+	struct bw_fixed lb_lines_in_per_line_out_in_middle_of_frame[maximum_number_of_surfaces];
-+	struct bw_fixed cursor_width_pixels[maximum_number_of_surfaces];
-+	struct bw_fixed minimum_latency_hiding[maximum_number_of_surfaces];
-+	struct bw_fixed maximum_latency_hiding[maximum_number_of_surfaces];
-+	struct bw_fixed minimum_latency_hiding_with_cursor[maximum_number_of_surfaces];
-+	struct bw_fixed maximum_latency_hiding_with_cursor[maximum_number_of_surfaces];
-+	struct bw_fixed src_pixels_for_first_output_pixel[maximum_number_of_surfaces];
-+	struct bw_fixed src_pixels_for_last_output_pixel[maximum_number_of_surfaces];
-+	struct bw_fixed src_data_for_first_output_pixel[maximum_number_of_surfaces];
-+	struct bw_fixed src_data_for_last_output_pixel[maximum_number_of_surfaces];
-+	struct bw_fixed active_time[maximum_number_of_surfaces];
-+	struct bw_fixed horizontal_blank_and_chunk_granularity_factor[maximum_number_of_surfaces];
-+	struct bw_fixed cursor_latency_hiding[maximum_number_of_surfaces];
-+	struct bw_fixed v_blank_dram_speed_change_margin[maximum_number_of_surfaces];
-+	uint32_t num_displays_with_margin[3][8];
-+	struct bw_fixed dmif_burst_time[3][8];
-+	struct bw_fixed mcifwr_burst_time[3][8];
-+	struct bw_fixed line_source_transfer_time[maximum_number_of_surfaces][3][8];
-+	struct bw_fixed dram_speed_change_line_source_transfer_time[maximum_number_of_surfaces][3][8];
-+	struct bw_fixed min_dram_speed_change_margin[3][8];
-+	struct bw_fixed dispclk_required_for_dram_speed_change[3][8];
-+	struct bw_fixed blackout_duration_margin[3][8];
-+	struct bw_fixed dispclk_required_for_blackout_duration[3][8];
-+	struct bw_fixed dispclk_required_for_blackout_recovery[3][8];
-+	struct bw_fixed dmif_required_sclk_for_urgent_latency[6];
-+};
-+
-+/**
-+ * Initialize structures with data which will NOT change at runtime.
-+ */
-+void bw_calcs_init(
-+	struct bw_calcs_dceip *bw_dceip,
-+	struct bw_calcs_vbios *bw_vbios,
-+	struct hw_asic_id asic_id);
-+
-+/**
-+ * Return:
-+ *	true -	Display(s) configuration supported.
-+ *		In this case 'calcs_output' contains data for HW programming
-+ *	false - Display(s) configuration not supported (not enough bandwidth).
-+ */
-+bool bw_calcs(
-+	struct dc_context *ctx,
-+	const struct bw_calcs_dceip *dceip,
-+	const struct bw_calcs_vbios *vbios,
-+	const struct pipe_ctx *pipe,
-+	int pipe_count,
-+	struct dce_bw_output *calcs_output);
-+
-+#endif /* __BANDWIDTH_CALCS_H__ */
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h.0130~	2017-12-14 06:39:58.436903582 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h	2017-12-14 06:39:58.436903582 +0100
-@@ -0,0 +1,141 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DDC_SERVICE_H__
-+#define __DAL_DDC_SERVICE_H__
-+
-+#include "include/ddc_service_types.h"
-+#include "include/i2caux_interface.h"
-+
-+#define EDID_SEGMENT_SIZE 256
-+
-+/* Address range from 0x00 to 0x1F.*/
-+#define DP_ADAPTOR_TYPE2_SIZE 0x20
-+#define DP_ADAPTOR_TYPE2_REG_ID 0x10
-+#define DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK 0x1D
-+/* Identifies adaptor as Dual-mode adaptor */
-+#define DP_ADAPTOR_TYPE2_ID 0xA0
-+/* MHz*/
-+#define DP_ADAPTOR_TYPE2_MAX_TMDS_CLK 600
-+/* MHz*/
-+#define DP_ADAPTOR_TYPE2_MIN_TMDS_CLK 25
-+/* kHZ*/
-+#define DP_ADAPTOR_DVI_MAX_TMDS_CLK 165000
-+/* kHZ*/
-+#define DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK 165000
-+
-+#define DDC_I2C_COMMAND_ENGINE I2C_COMMAND_ENGINE_SW
-+
-+struct ddc_service;
-+struct graphics_object_id;
-+enum ddc_result;
-+struct av_sync_data;
-+struct dp_receiver_id_info;
-+
-+struct i2c_payloads;
-+struct aux_payloads;
-+
-+void dal_ddc_i2c_payloads_add(
-+		struct i2c_payloads *payloads,
-+		uint32_t address,
-+		uint32_t len,
-+		uint8_t *data,
-+		bool write);
-+
-+void dal_ddc_aux_payloads_add(
-+		struct aux_payloads *payloads,
-+		uint32_t address,
-+		uint32_t len,
-+		uint8_t *data,
-+		bool write);
-+
-+struct ddc_service_init_data {
-+	struct graphics_object_id id;
-+	struct dc_context *ctx;
-+	struct dc_link *link;
-+};
-+
-+struct ddc_service *dal_ddc_service_create(
-+		struct ddc_service_init_data *ddc_init_data);
-+
-+void dal_ddc_service_destroy(struct ddc_service **ddc);
-+
-+enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc);
-+
-+void dal_ddc_service_set_transaction_type(
-+		struct ddc_service *ddc,
-+		enum ddc_transaction_type type);
-+
-+bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc);
-+
-+void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
-+		struct ddc_service *ddc,
-+		struct display_sink_capability *sink_cap);
-+
-+bool dal_ddc_service_query_ddc_data(
-+		struct ddc_service *ddc,
-+		uint32_t address,
-+		uint8_t *write_buf,
-+		uint32_t write_size,
-+		uint8_t *read_buf,
-+		uint32_t read_size);
-+
-+enum ddc_result dal_ddc_service_read_dpcd_data(
-+		struct ddc_service *ddc,
-+		bool i2c,
-+		enum i2c_mot_mode mot,
-+		uint32_t address,
-+		uint8_t *data,
-+		uint32_t len);
-+
-+enum ddc_result dal_ddc_service_write_dpcd_data(
-+		struct ddc_service *ddc,
-+		bool i2c,
-+		enum i2c_mot_mode mot,
-+		uint32_t address,
-+		const uint8_t *data,
-+		uint32_t len);
-+
-+void dal_ddc_service_write_scdc_data(
-+		struct ddc_service *ddc_service,
-+		uint32_t pix_clk,
-+		bool lte_340_scramble);
-+
-+void dal_ddc_service_read_scdc_data(
-+		struct ddc_service *ddc_service);
-+
-+void ddc_service_set_dongle_type(struct ddc_service *ddc,
-+		enum display_dongle_type dongle_type);
-+
-+void dal_ddc_service_set_ddc_pin(
-+		struct ddc_service *ddc_service,
-+		struct ddc *ddc);
-+
-+struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service);
-+
-+uint32_t get_defer_delay(struct ddc_service *ddc);
-+
-+#endif /* __DAL_DDC_SERVICE_H__ */
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h.0130~	2017-12-14 06:39:58.436903582 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h	2017-12-14 06:39:58.436903582 +0100
-@@ -0,0 +1,64 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_LINK_DP_H__
-+#define __DC_LINK_DP_H__
-+
-+#define LINK_TRAINING_ATTEMPTS 4
-+#define LINK_TRAINING_RETRY_DELAY 50 /* ms */
-+
-+struct dc_link;
-+struct dc_stream_state;
-+struct dc_link_settings;
-+
-+bool dp_hbr_verify_link_cap(
-+	struct dc_link *link,
-+	struct dc_link_settings *known_limit_link_setting);
-+
-+bool dp_validate_mode_timing(
-+	struct dc_link *link,
-+	const struct dc_crtc_timing *timing);
-+
-+void decide_link_settings(
-+	struct dc_stream_state *stream,
-+	struct dc_link_settings *link_setting);
-+
-+bool perform_link_training_with_retries(
-+	struct dc_link *link,
-+	const struct dc_link_settings *link_setting,
-+	bool skip_video_pattern,
-+	int attempts);
-+
-+bool is_mst_supported(struct dc_link *link);
-+
-+void detect_dp_sink_caps(struct dc_link *link);
-+
-+void detect_edp_sink_caps(struct dc_link *link);
-+
-+bool is_dp_active_dongle(const struct dc_link *link);
-+
-+void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
-+
-+#endif /* __DC_LINK_DP_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h.0130~	2017-12-14 06:39:58.436903582 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h	2017-12-14 06:39:58.436903582 +0100
-@@ -0,0 +1,635 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+/**
-+ * Bandwidth and Watermark calculations interface.
-+ * (Refer to "DCEx_mode_support.xlsm" from Perforce.)
-+ */
-+#ifndef __DCN_CALCS_H__
-+#define __DCN_CALCS_H__
-+
-+#include "bw_fixed.h"
-+#include "display_clock.h"
-+#include "../dml/display_mode_lib.h"
-+
-+struct dc;
-+struct dc_state;
-+
-+/*******************************************************************************
-+ * DCN data structures.
-+ ******************************************************************************/
-+
-+#define number_of_planes   6
-+#define number_of_planes_minus_one   5
-+#define number_of_states   4
-+#define number_of_states_plus_one   5
-+
-+#define ddr4_dram_width   64
-+#define ddr4_dram_factor_single_Channel   16
-+enum dcn_bw_defs {
-+	dcn_bw_v_min0p65,
-+	dcn_bw_v_mid0p72,
-+	dcn_bw_v_nom0p8,
-+	dcn_bw_v_max0p9,
-+	dcn_bw_v_max0p91,
-+	dcn_bw_no_support = 5,
-+	dcn_bw_yes,
-+	dcn_bw_hor,
-+	dcn_bw_vert,
-+	dcn_bw_override,
-+	dcn_bw_rgb_sub_64,
-+	dcn_bw_rgb_sub_32,
-+	dcn_bw_rgb_sub_16,
-+	dcn_bw_no,
-+	dcn_bw_sw_linear,
-+	dcn_bw_sw_4_kb_d,
-+	dcn_bw_sw_4_kb_d_x,
-+	dcn_bw_sw_64_kb_d,
-+	dcn_bw_sw_64_kb_d_t,
-+	dcn_bw_sw_64_kb_d_x,
-+	dcn_bw_sw_var_d,
-+	dcn_bw_sw_var_d_x,
-+	dcn_bw_yuv420_sub_8,
-+	dcn_bw_sw_4_kb_s,
-+	dcn_bw_sw_4_kb_s_x,
-+	dcn_bw_sw_64_kb_s,
-+	dcn_bw_sw_64_kb_s_t,
-+	dcn_bw_sw_64_kb_s_x,
-+	dcn_bw_writeback,
-+	dcn_bw_444,
-+	dcn_bw_dp,
-+	dcn_bw_420,
-+	dcn_bw_hdmi,
-+	dcn_bw_sw_var_s,
-+	dcn_bw_sw_var_s_x,
-+	dcn_bw_yuv420_sub_10,
-+	dcn_bw_supported_in_v_active,
-+	dcn_bw_supported_in_v_blank,
-+	dcn_bw_not_supported,
-+	dcn_bw_na,
-+	dcn_bw_encoder_8bpc,
-+	dcn_bw_encoder_10bpc,
-+	dcn_bw_encoder_12bpc,
-+	dcn_bw_encoder_16bpc,
-+};
-+
-+/*bounding box parameters*/
-+/*mode parameters*/
-+/*system configuration*/
-+/* display configuration*/
-+struct dcn_bw_internal_vars {
-+	float voltage[number_of_states_plus_one + 1];
-+	float max_dispclk[number_of_states_plus_one + 1];
-+	float max_dppclk[number_of_states_plus_one + 1];
-+	float dcfclk_per_state[number_of_states_plus_one + 1];
-+	float phyclk_per_state[number_of_states_plus_one + 1];
-+	float fabric_and_dram_bandwidth_per_state[number_of_states_plus_one + 1];
-+	float sr_exit_time;
-+	float sr_enter_plus_exit_time;
-+	float dram_clock_change_latency;
-+	float urgent_latency;
-+	float write_back_latency;
-+	float percent_of_ideal_drambw_received_after_urg_latency;
-+	float dcfclkv_max0p9;
-+	float dcfclkv_nom0p8;
-+	float dcfclkv_mid0p72;
-+	float dcfclkv_min0p65;
-+	float max_dispclk_vmax0p9;
-+	float max_dppclk_vmax0p9;
-+	float max_dispclk_vnom0p8;
-+	float max_dppclk_vnom0p8;
-+	float max_dispclk_vmid0p72;
-+	float max_dppclk_vmid0p72;
-+	float max_dispclk_vmin0p65;
-+	float max_dppclk_vmin0p65;
-+	float socclk;
-+	float fabric_and_dram_bandwidth_vmax0p9;
-+	float fabric_and_dram_bandwidth_vnom0p8;
-+	float fabric_and_dram_bandwidth_vmid0p72;
-+	float fabric_and_dram_bandwidth_vmin0p65;
-+	float round_trip_ping_latency_cycles;
-+	float urgent_out_of_order_return_per_channel;
-+	float number_of_channels;
-+	float vmm_page_size;
-+	float return_bus_width;
-+	float rob_buffer_size_in_kbyte;
-+	float det_buffer_size_in_kbyte;
-+	float dpp_output_buffer_pixels;
-+	float opp_output_buffer_lines;
-+	float pixel_chunk_size_in_kbyte;
-+	float pte_chunk_size;
-+	float meta_chunk_size;
-+	float writeback_chunk_size;
-+	enum dcn_bw_defs odm_capability;
-+	enum dcn_bw_defs dsc_capability;
-+	float line_buffer_size;
-+	enum dcn_bw_defs is_line_buffer_bpp_fixed;
-+	float line_buffer_fixed_bpp;
-+	float max_line_buffer_lines;
-+	float writeback_luma_buffer_size;
-+	float writeback_chroma_buffer_size;
-+	float max_num_dpp;
-+	float max_num_writeback;
-+	float max_dchub_topscl_throughput;
-+	float max_pscl_tolb_throughput;
-+	float max_lb_tovscl_throughput;
-+	float max_vscl_tohscl_throughput;
-+	float max_hscl_ratio;
-+	float max_vscl_ratio;
-+	float max_hscl_taps;
-+	float max_vscl_taps;
-+	float under_scan_factor;
-+	float phyclkv_max0p9;
-+	float phyclkv_nom0p8;
-+	float phyclkv_mid0p72;
-+	float phyclkv_min0p65;
-+	float pte_buffer_size_in_requests;
-+	float dispclk_ramping_margin;
-+	float downspreading;
-+	float max_inter_dcn_tile_repeaters;
-+	enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
-+	enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed;
-+	int mode;
-+	float viewport_width[number_of_planes_minus_one + 1];
-+	float htotal[number_of_planes_minus_one + 1];
-+	float vtotal[number_of_planes_minus_one + 1];
-+	float v_sync_plus_back_porch[number_of_planes_minus_one + 1];
-+	float vactive[number_of_planes_minus_one + 1];
-+	float pixel_clock[number_of_planes_minus_one + 1]; /*MHz*/
-+	float viewport_height[number_of_planes_minus_one + 1];
-+	enum dcn_bw_defs dcc_enable[number_of_planes_minus_one + 1];
-+	float dcc_rate[number_of_planes_minus_one + 1];
-+	enum dcn_bw_defs source_scan[number_of_planes_minus_one + 1];
-+	float lb_bit_per_pixel[number_of_planes_minus_one + 1];
-+	enum dcn_bw_defs source_pixel_format[number_of_planes_minus_one + 1];
-+	enum dcn_bw_defs source_surface_mode[number_of_planes_minus_one + 1];
-+	enum dcn_bw_defs output_format[number_of_planes_minus_one + 1];
-+	enum dcn_bw_defs output_deep_color[number_of_planes_minus_one + 1];
-+	enum dcn_bw_defs output[number_of_planes_minus_one + 1];
-+	float scaler_rec_out_width[number_of_planes_minus_one + 1];
-+	float scaler_recout_height[number_of_planes_minus_one + 1];
-+	float underscan_output[number_of_planes_minus_one + 1];
-+	float interlace_output[number_of_planes_minus_one + 1];
-+	float override_hta_ps[number_of_planes_minus_one + 1];
-+	float override_vta_ps[number_of_planes_minus_one + 1];
-+	float override_hta_pschroma[number_of_planes_minus_one + 1];
-+	float override_vta_pschroma[number_of_planes_minus_one + 1];
-+	float urgent_latency_support_us[number_of_planes_minus_one + 1];
-+	float h_ratio[number_of_planes_minus_one + 1];
-+	float v_ratio[number_of_planes_minus_one + 1];
-+	float htaps[number_of_planes_minus_one + 1];
-+	float vtaps[number_of_planes_minus_one + 1];
-+	float hta_pschroma[number_of_planes_minus_one + 1];
-+	float vta_pschroma[number_of_planes_minus_one + 1];
-+	enum dcn_bw_defs pte_enable;
-+	enum dcn_bw_defs synchronized_vblank;
-+	enum dcn_bw_defs ta_pscalculation;
-+	int voltage_override_level;
-+	int number_of_active_planes;
-+	int voltage_level;
-+	enum dcn_bw_defs immediate_flip_supported;
-+	float dcfclk;
-+	float max_phyclk;
-+	float fabric_and_dram_bandwidth;
-+	float dpp_per_plane_per_ratio[1 + 1][number_of_planes_minus_one + 1];
-+	enum dcn_bw_defs dispclk_dppclk_support_per_ratio[1 + 1];
-+	float required_dispclk_per_ratio[1 + 1];
-+	enum dcn_bw_defs error_message[1 + 1];
-+	int dispclk_dppclk_ratio;
-+	float dpp_per_plane[number_of_planes_minus_one + 1];
-+	float det_buffer_size_y[number_of_planes_minus_one + 1];
-+	float det_buffer_size_c[number_of_planes_minus_one + 1];
-+	float swath_height_y[number_of_planes_minus_one + 1];
-+	float swath_height_c[number_of_planes_minus_one + 1];
-+	enum dcn_bw_defs final_error_message;
-+	float frequency;
-+	float header_line;
-+	float header;
-+	enum dcn_bw_defs voltage_override;
-+	enum dcn_bw_defs allow_different_hratio_vratio;
-+	float acceptable_quality_hta_ps;
-+	float acceptable_quality_vta_ps;
-+	float no_of_dpp[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
-+	float swath_width_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
-+	float swath_height_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
-+	float swath_height_cper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
-+	float urgent_latency_support_us_per_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
-+	float v_ratio_pre_ywith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
-+	float v_ratio_pre_cwith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
-+	float required_prefetch_pixel_data_bw_with_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
-+	float v_ratio_pre_ywithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
-+	float v_ratio_pre_cwithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
-+	float required_prefetch_pixel_data_bw_without_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
-+	enum dcn_bw_defs prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1];
-+	enum dcn_bw_defs prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1];
-+	enum dcn_bw_defs v_ratio_in_prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1];
-+	enum dcn_bw_defs v_ratio_in_prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1];
-+	float required_dispclk[number_of_states_plus_one + 1][1 + 1];
-+	enum dcn_bw_defs dispclk_dppclk_support[number_of_states_plus_one + 1][1 + 1];
-+	enum dcn_bw_defs total_available_pipes_support[number_of_states_plus_one + 1][1 + 1];
-+	float total_number_of_active_dpp[number_of_states_plus_one + 1][1 + 1];
-+	float total_number_of_dcc_active_dpp[number_of_states_plus_one + 1][1 + 1];
-+	enum dcn_bw_defs urgent_latency_support[number_of_states_plus_one + 1][1 + 1];
-+	enum dcn_bw_defs mode_support_with_immediate_flip[number_of_states_plus_one + 1][1 + 1];
-+	enum dcn_bw_defs mode_support_without_immediate_flip[number_of_states_plus_one + 1][1 + 1];
-+	float return_bw_per_state[number_of_states_plus_one + 1];
-+	enum dcn_bw_defs dio_support[number_of_states_plus_one + 1];
-+	float urgent_round_trip_and_out_of_order_latency_per_state[number_of_states_plus_one + 1];
-+	enum dcn_bw_defs rob_support[number_of_states_plus_one + 1];
-+	enum dcn_bw_defs bandwidth_support[number_of_states_plus_one + 1];
-+	float prefetch_bw[number_of_planes_minus_one + 1];
-+	float meta_pte_bytes_per_frame[number_of_planes_minus_one + 1];
-+	float meta_row_bytes[number_of_planes_minus_one + 1];
-+	float dpte_bytes_per_row[number_of_planes_minus_one + 1];
-+	float prefetch_lines_y[number_of_planes_minus_one + 1];
-+	float prefetch_lines_c[number_of_planes_minus_one + 1];
-+	float max_num_sw_y[number_of_planes_minus_one + 1];
-+	float max_num_sw_c[number_of_planes_minus_one + 1];
-+	float line_times_for_prefetch[number_of_planes_minus_one + 1];
-+	float lines_for_meta_pte_with_immediate_flip[number_of_planes_minus_one + 1];
-+	float lines_for_meta_pte_without_immediate_flip[number_of_planes_minus_one + 1];
-+	float lines_for_meta_and_dpte_row_with_immediate_flip[number_of_planes_minus_one + 1];
-+	float lines_for_meta_and_dpte_row_without_immediate_flip[number_of_planes_minus_one + 1];
-+	float min_dppclk_using_single_dpp[number_of_planes_minus_one + 1];
-+	float swath_width_ysingle_dpp[number_of_planes_minus_one + 1];
-+	float byte_per_pixel_in_dety[number_of_planes_minus_one + 1];
-+	float byte_per_pixel_in_detc[number_of_planes_minus_one + 1];
-+	float number_of_dpp_required_for_det_and_lb_size[number_of_planes_minus_one + 1];
-+	float required_phyclk[number_of_planes_minus_one + 1];
-+	float read256_block_height_y[number_of_planes_minus_one + 1];
-+	float read256_block_width_y[number_of_planes_minus_one + 1];
-+	float read256_block_height_c[number_of_planes_minus_one + 1];
-+	float read256_block_width_c[number_of_planes_minus_one + 1];
-+	float max_swath_height_y[number_of_planes_minus_one + 1];
-+	float max_swath_height_c[number_of_planes_minus_one + 1];
-+	float min_swath_height_y[number_of_planes_minus_one + 1];
-+	float min_swath_height_c[number_of_planes_minus_one + 1];
-+	float read_bandwidth[number_of_planes_minus_one + 1];
-+	float write_bandwidth[number_of_planes_minus_one + 1];
-+	float pscl_factor[number_of_planes_minus_one + 1];
-+	float pscl_factor_chroma[number_of_planes_minus_one + 1];
-+	enum dcn_bw_defs scale_ratio_support;
-+	enum dcn_bw_defs source_format_pixel_and_scan_support;
-+	float total_read_bandwidth_consumed_gbyte_per_second;
-+	float total_write_bandwidth_consumed_gbyte_per_second;
-+	float total_bandwidth_consumed_gbyte_per_second;
-+	enum dcn_bw_defs dcc_enabled_in_any_plane;
-+	float return_bw_todcn_per_state;
-+	float critical_point;
-+	enum dcn_bw_defs writeback_latency_support;
-+	float required_output_bw;
-+	float total_number_of_active_writeback;
-+	enum dcn_bw_defs total_available_writeback_support;
-+	float maximum_swath_width;
-+	float number_of_dpp_required_for_det_size;
-+	float number_of_dpp_required_for_lb_size;
-+	float min_dispclk_using_single_dpp;
-+	float min_dispclk_using_dual_dpp;
-+	enum dcn_bw_defs viewport_size_support;
-+	float swath_width_granularity_y;
-+	float rounded_up_max_swath_size_bytes_y;
-+	float swath_width_granularity_c;
-+	float rounded_up_max_swath_size_bytes_c;
-+	float lines_in_det_luma;
-+	float lines_in_det_chroma;
-+	float effective_lb_latency_hiding_source_lines_luma;
-+	float effective_lb_latency_hiding_source_lines_chroma;
-+	float effective_detlb_lines_luma;
-+	float effective_detlb_lines_chroma;
-+	float projected_dcfclk_deep_sleep;
-+	float meta_req_height_y;
-+	float meta_req_width_y;
-+	float meta_surface_width_y;
-+	float meta_surface_height_y;
-+	float meta_pte_bytes_per_frame_y;
-+	float meta_row_bytes_y;
-+	float macro_tile_block_size_bytes_y;
-+	float macro_tile_block_height_y;
-+	float data_pte_req_height_y;
-+	float data_pte_req_width_y;
-+	float dpte_bytes_per_row_y;
-+	float meta_req_height_c;
-+	float meta_req_width_c;
-+	float meta_surface_width_c;
-+	float meta_surface_height_c;
-+	float meta_pte_bytes_per_frame_c;
-+	float meta_row_bytes_c;
-+	float macro_tile_block_size_bytes_c;
-+	float macro_tile_block_height_c;
-+	float macro_tile_block_width_c;
-+	float data_pte_req_height_c;
-+	float data_pte_req_width_c;
-+	float dpte_bytes_per_row_c;
-+	float v_init_y;
-+	float max_partial_sw_y;
-+	float v_init_c;
-+	float max_partial_sw_c;
-+	float dst_x_after_scaler;
-+	float dst_y_after_scaler;
-+	float time_calc;
-+	float v_update_offset[number_of_planes_minus_one + 1];
-+	float total_repeater_delay;
-+	float v_update_width[number_of_planes_minus_one + 1];
-+	float v_ready_offset[number_of_planes_minus_one + 1];
-+	float time_setup;
-+	float extra_latency;
-+	float maximum_vstartup;
-+	float bw_available_for_immediate_flip;
-+	float total_immediate_flip_bytes[number_of_planes_minus_one + 1];
-+	float time_for_meta_pte_with_immediate_flip;
-+	float time_for_meta_pte_without_immediate_flip;
-+	float time_for_meta_and_dpte_row_with_immediate_flip;
-+	float time_for_meta_and_dpte_row_without_immediate_flip;
-+	float line_times_to_request_prefetch_pixel_data_with_immediate_flip;
-+	float line_times_to_request_prefetch_pixel_data_without_immediate_flip;
-+	float maximum_read_bandwidth_with_prefetch_with_immediate_flip;
-+	float maximum_read_bandwidth_with_prefetch_without_immediate_flip;
-+	float voltage_level_with_immediate_flip;
-+	float voltage_level_without_immediate_flip;
-+	float total_number_of_active_dpp_per_ratio[1 + 1];
-+	float byte_per_pix_dety;
-+	float byte_per_pix_detc;
-+	float read256_bytes_block_height_y;
-+	float read256_bytes_block_width_y;
-+	float read256_bytes_block_height_c;
-+	float read256_bytes_block_width_c;
-+	float maximum_swath_height_y;
-+	float maximum_swath_height_c;
-+	float minimum_swath_height_y;
-+	float minimum_swath_height_c;
-+	float swath_width;
-+	float prefetch_bandwidth[number_of_planes_minus_one + 1];
-+	float v_init_pre_fill_y[number_of_planes_minus_one + 1];
-+	float v_init_pre_fill_c[number_of_planes_minus_one + 1];
-+	float max_num_swath_y[number_of_planes_minus_one + 1];
-+	float max_num_swath_c[number_of_planes_minus_one + 1];
-+	float prefill_y[number_of_planes_minus_one + 1];
-+	float prefill_c[number_of_planes_minus_one + 1];
-+	float v_startup[number_of_planes_minus_one + 1];
-+	enum dcn_bw_defs allow_dram_clock_change_during_vblank[number_of_planes_minus_one + 1];
-+	float allow_dram_self_refresh_during_vblank[number_of_planes_minus_one + 1];
-+	float v_ratio_prefetch_y[number_of_planes_minus_one + 1];
-+	float v_ratio_prefetch_c[number_of_planes_minus_one + 1];
-+	float destination_lines_for_prefetch[number_of_planes_minus_one + 1];
-+	float destination_lines_to_request_vm_inv_blank[number_of_planes_minus_one + 1];
-+	float destination_lines_to_request_row_in_vblank[number_of_planes_minus_one + 1];
-+	float min_ttuv_blank[number_of_planes_minus_one + 1];
-+	float byte_per_pixel_dety[number_of_planes_minus_one + 1];
-+	float byte_per_pixel_detc[number_of_planes_minus_one + 1];
-+	float swath_width_y[number_of_planes_minus_one + 1];
-+	float lines_in_dety[number_of_planes_minus_one + 1];
-+	float lines_in_dety_rounded_down_to_swath[number_of_planes_minus_one + 1];
-+	float lines_in_detc[number_of_planes_minus_one + 1];
-+	float lines_in_detc_rounded_down_to_swath[number_of_planes_minus_one + 1];
-+	float full_det_buffering_time_y[number_of_planes_minus_one + 1];
-+	float full_det_buffering_time_c[number_of_planes_minus_one + 1];
-+	float active_dram_clock_change_latency_margin[number_of_planes_minus_one + 1];
-+	float v_blank_dram_clock_change_latency_margin[number_of_planes_minus_one + 1];
-+	float dcfclk_deep_sleep_per_plane[number_of_planes_minus_one + 1];
-+	float read_bandwidth_plane_luma[number_of_planes_minus_one + 1];
-+	float read_bandwidth_plane_chroma[number_of_planes_minus_one + 1];
-+	float display_pipe_line_delivery_time_luma[number_of_planes_minus_one + 1];
-+	float display_pipe_line_delivery_time_chroma[number_of_planes_minus_one + 1];
-+	float display_pipe_line_delivery_time_luma_prefetch[number_of_planes_minus_one + 1];
-+	float display_pipe_line_delivery_time_chroma_prefetch[number_of_planes_minus_one + 1];
-+	float pixel_pte_bytes_per_row[number_of_planes_minus_one + 1];
-+	float meta_pte_bytes_frame[number_of_planes_minus_one + 1];
-+	float meta_row_byte[number_of_planes_minus_one + 1];
-+	float prefetch_source_lines_y[number_of_planes_minus_one + 1];
-+	float prefetch_source_lines_c[number_of_planes_minus_one + 1];
-+	float pscl_throughput[number_of_planes_minus_one + 1];
-+	float pscl_throughput_chroma[number_of_planes_minus_one + 1];
-+	float output_bpphdmi[number_of_planes_minus_one + 1];
-+	float output_bppdp4_lane_hbr[number_of_planes_minus_one + 1];
-+	float output_bppdp4_lane_hbr2[number_of_planes_minus_one + 1];
-+	float output_bppdp4_lane_hbr3[number_of_planes_minus_one + 1];
-+	float max_vstartup_lines[number_of_planes_minus_one + 1];
-+	float dispclk_with_ramping;
-+	float dispclk_without_ramping;
-+	float dppclk_using_single_dpp_luma;
-+	float dppclk_using_single_dpp;
-+	float dppclk_using_single_dpp_chroma;
-+	enum dcn_bw_defs odm_capable;
-+	float dispclk;
-+	float dppclk;
-+	float return_bandwidth_to_dcn;
-+	enum dcn_bw_defs dcc_enabled_any_plane;
-+	float return_bw;
-+	float critical_compression;
-+	float total_data_read_bandwidth;
-+	float total_active_dpp;
-+	float total_dcc_active_dpp;
-+	float urgent_round_trip_and_out_of_order_latency;
-+	float last_pixel_of_line_extra_watermark;
-+	float data_fabric_line_delivery_time_luma;
-+	float data_fabric_line_delivery_time_chroma;
-+	float urgent_extra_latency;
-+	float urgent_watermark;
-+	float ptemeta_urgent_watermark;
-+	float dram_clock_change_watermark;
-+	float total_active_writeback;
-+	float writeback_dram_clock_change_watermark;
-+	float min_full_det_buffering_time;
-+	float frame_time_for_min_full_det_buffering_time;
-+	float average_read_bandwidth_gbyte_per_second;
-+	float part_of_burst_that_fits_in_rob;
-+	float stutter_burst_time;
-+	float stutter_efficiency_not_including_vblank;
-+	float smallest_vblank;
-+	float v_blank_time;
-+	float stutter_efficiency;
-+	float dcf_clk_deep_sleep;
-+	float stutter_exit_watermark;
-+	float stutter_enter_plus_exit_watermark;
-+	float effective_det_plus_lb_lines_luma;
-+	float urgent_latency_support_us_luma;
-+	float effective_det_plus_lb_lines_chroma;
-+	float urgent_latency_support_us_chroma;
-+	float min_urgent_latency_support_us;
-+	float non_urgent_latency_tolerance;
-+	float block_height256_bytes_y;
-+	float block_height256_bytes_c;
-+	float meta_request_width_y;
-+	float meta_surf_width_y;
-+	float meta_surf_height_y;
-+	float meta_pte_bytes_frame_y;
-+	float meta_row_byte_y;
-+	float macro_tile_size_byte_y;
-+	float macro_tile_height_y;
-+	float pixel_pte_req_height_y;
-+	float pixel_pte_req_width_y;
-+	float pixel_pte_bytes_per_row_y;
-+	float meta_request_width_c;
-+	float meta_surf_width_c;
-+	float meta_surf_height_c;
-+	float meta_pte_bytes_frame_c;
-+	float meta_row_byte_c;
-+	float macro_tile_size_bytes_c;
-+	float macro_tile_height_c;
-+	float pixel_pte_req_height_c;
-+	float pixel_pte_req_width_c;
-+	float pixel_pte_bytes_per_row_c;
-+	float max_partial_swath_y;
-+	float max_partial_swath_c;
-+	float t_calc;
-+	float next_prefetch_mode;
-+	float v_startup_lines;
-+	enum dcn_bw_defs planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw;
-+	enum dcn_bw_defs planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4;
-+	enum dcn_bw_defs planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2;
-+	enum dcn_bw_defs v_ratio_prefetch_more_than4;
-+	enum dcn_bw_defs destination_line_times_for_prefetch_less_than2;
-+	float prefetch_mode;
-+	float dstx_after_scaler;
-+	float dsty_after_scaler;
-+	float v_update_offset_pix;
-+	float total_repeater_delay_time;
-+	float v_update_width_pix;
-+	float v_ready_offset_pix;
-+	float t_setup;
-+	float t_wait;
-+	float bandwidth_available_for_immediate_flip;
-+	float tot_immediate_flip_bytes;
-+	float max_rd_bandwidth;
-+	float time_for_fetching_meta_pte;
-+	float time_for_fetching_row_in_vblank;
-+	float lines_to_request_prefetch_pixel_data;
-+	float required_prefetch_pix_data_bw;
-+	enum dcn_bw_defs prefetch_mode_supported;
-+	float active_dp_ps;
-+	float lb_latency_hiding_source_lines_y;
-+	float lb_latency_hiding_source_lines_c;
-+	float effective_lb_latency_hiding_y;
-+	float effective_lb_latency_hiding_c;
-+	float dpp_output_buffer_lines_y;
-+	float dpp_output_buffer_lines_c;
-+	float dppopp_buffering_y;
-+	float max_det_buffering_time_y;
-+	float active_dram_clock_change_latency_margin_y;
-+	float dppopp_buffering_c;
-+	float max_det_buffering_time_c;
-+	float active_dram_clock_change_latency_margin_c;
-+	float writeback_dram_clock_change_latency_margin;
-+	float min_active_dram_clock_change_margin;
-+	float v_blank_of_min_active_dram_clock_change_margin;
-+	float second_min_active_dram_clock_change_margin;
-+	float min_vblank_dram_clock_change_margin;
-+	float dram_clock_change_margin;
-+	float dram_clock_change_support;
-+	float wr_bandwidth;
-+	float max_used_bw;
-+};
-+
-+struct dcn_soc_bounding_box {
-+	float sr_exit_time; /*us*/
-+	float sr_enter_plus_exit_time; /*us*/
-+	float urgent_latency; /*us*/
-+	float write_back_latency; /*us*/
-+	float percent_of_ideal_drambw_received_after_urg_latency; /*%*/
-+	int max_request_size; /*bytes*/
-+	float dcfclkv_max0p9; /*MHz*/
-+	float dcfclkv_nom0p8; /*MHz*/
-+	float dcfclkv_mid0p72; /*MHz*/
-+	float dcfclkv_min0p65; /*MHz*/
-+	float max_dispclk_vmax0p9; /*MHz*/
-+	float max_dispclk_vmid0p72; /*MHz*/
-+	float max_dispclk_vnom0p8; /*MHz*/
-+	float max_dispclk_vmin0p65; /*MHz*/
-+	float max_dppclk_vmax0p9; /*MHz*/
-+	float max_dppclk_vnom0p8; /*MHz*/
-+	float max_dppclk_vmid0p72; /*MHz*/
-+	float max_dppclk_vmin0p65; /*MHz*/
-+	float socclk; /*MHz*/
-+	float fabric_and_dram_bandwidth_vmax0p9; /*GB/s*/
-+	float fabric_and_dram_bandwidth_vnom0p8; /*GB/s*/
-+	float fabric_and_dram_bandwidth_vmid0p72; /*GB/s*/
-+	float fabric_and_dram_bandwidth_vmin0p65; /*GB/s*/
-+	float phyclkv_max0p9; /*MHz*/
-+	float phyclkv_nom0p8; /*MHz*/
-+	float phyclkv_mid0p72; /*MHz*/
-+	float phyclkv_min0p65; /*MHz*/
-+	float downspreading; /*%*/
-+	int round_trip_ping_latency_cycles; /*DCFCLK Cycles*/
-+	int urgent_out_of_order_return_per_channel; /*bytes*/
-+	int number_of_channels;
-+	int vmm_page_size; /*bytes*/
-+	float dram_clock_change_latency; /*us*/
-+	int return_bus_width; /*bytes*/
-+	float percent_disp_bw_limit; /*%*/
-+};
-+extern const struct dcn_soc_bounding_box dcn10_soc_defaults;
-+
-+struct dcn_ip_params {
-+	float rob_buffer_size_in_kbyte;
-+	float det_buffer_size_in_kbyte;
-+	float dpp_output_buffer_pixels;
-+	float opp_output_buffer_lines;
-+	float pixel_chunk_size_in_kbyte;
-+	enum dcn_bw_defs pte_enable;
-+	int pte_chunk_size; /*kbytes*/
-+	int meta_chunk_size; /*kbytes*/
-+	int writeback_chunk_size; /*kbytes*/
-+	enum dcn_bw_defs odm_capability;
-+	enum dcn_bw_defs dsc_capability;
-+	int line_buffer_size; /*bit*/
-+	int max_line_buffer_lines;
-+	enum dcn_bw_defs is_line_buffer_bpp_fixed;
-+	int line_buffer_fixed_bpp;
-+	int writeback_luma_buffer_size; /*kbytes*/
-+	int writeback_chroma_buffer_size; /*kbytes*/
-+	int max_num_dpp;
-+	int max_num_writeback;
-+	int max_dchub_topscl_throughput; /*pixels/dppclk*/
-+	int max_pscl_tolb_throughput; /*pixels/dppclk*/
-+	int max_lb_tovscl_throughput; /*pixels/dppclk*/
-+	int max_vscl_tohscl_throughput; /*pixels/dppclk*/
-+	float max_hscl_ratio;
-+	float max_vscl_ratio;
-+	int max_hscl_taps;
-+	int max_vscl_taps;
-+	int pte_buffer_size_in_requests;
-+	float dispclk_ramping_margin; /*%*/
-+	float under_scan_factor;
-+	int max_inter_dcn_tile_repeaters;
-+	enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
-+	enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed;
-+	int dcfclk_cstate_latency;
-+};
-+extern const struct dcn_ip_params dcn10_ip_defaults;
-+
-+bool dcn_validate_bandwidth(
-+		struct dc *dc,
-+		struct dc_state *context);
-+
-+unsigned int dcn_find_dcfclk_suits_all(
-+	const struct dc *dc,
-+	struct clocks_value *clocks);
-+
-+void dcn_bw_update_from_pplib(struct dc *dc);
-+void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc);
-+void dcn_bw_sync_calcs_and_dml(struct dc *dc);
-+
-+#endif /* __DCN_CALCS_H__ */
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h.0130~	2017-12-14 06:39:58.436903582 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h	2017-12-14 06:39:58.436903582 +0100
-@@ -0,0 +1,48 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_ABM_H__
-+#define __DC_ABM_H__
-+
-+#include "dm_services_types.h"
-+
-+struct abm {
-+	struct dc_context *ctx;
-+	const struct abm_funcs *funcs;
-+};
-+
-+struct abm_funcs {
-+	void (*abm_init)(struct abm *abm);
-+	bool (*set_abm_level)(struct abm *abm, unsigned int abm_level);
-+	bool (*set_abm_immediate_disable)(struct abm *abm);
-+	bool (*init_backlight)(struct abm *abm);
-+	bool (*set_backlight_level)(struct abm *abm,
-+			unsigned int backlight_level,
-+			unsigned int frame_ramp,
-+			unsigned int controller_id);
-+	unsigned int (*get_current_backlight_8_bit)(struct abm *abm);
-+	bool (*is_dmcu_initialized)(struct abm *abm);
-+};
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/audio.h.0130~	2017-12-14 06:39:58.436903582 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/audio.h	2017-12-14 06:39:58.436903582 +0100
-@@ -0,0 +1,62 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_AUDIO_H__
-+#define __DAL_AUDIO_H__
-+
-+#include "audio_types.h"
-+
-+struct audio;
-+
-+struct audio_funcs {
-+
-+	bool (*endpoint_valid)(struct audio *audio);
-+
-+	void (*hw_init)(struct audio *audio);
-+
-+	void (*az_enable)(struct audio *audio);
-+
-+	void (*az_disable)(struct audio *audio);
-+
-+	void (*az_configure)(struct audio *audio,
-+		enum signal_type signal,
-+		const struct audio_crtc_info *crtc_info,
-+		const struct audio_info *audio_info);
-+
-+	void (*wall_dto_setup)(struct audio *audio,
-+		enum signal_type signal,
-+		const struct audio_crtc_info *crtc_info,
-+		const struct audio_pll_info *pll_info);
-+
-+	void (*destroy)(struct audio **audio);
-+};
-+
-+struct audio {
-+	const struct audio_funcs *funcs;
-+	struct dc_context *ctx;
-+	unsigned int inst;
-+};
-+
-+#endif  /* __DAL_AUDIO__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h.0130~	2017-12-14 06:39:58.436903582 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h	2017-12-14 06:39:58.436903582 +0100
-@@ -0,0 +1,85 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DISPLAY_CLOCK_H__
-+#define __DISPLAY_CLOCK_H__
-+
-+#include "dm_services_types.h"
-+
-+
-+struct clocks_value {
-+	int dispclk_in_khz;
-+	int max_pixelclk_in_khz;
-+	int max_non_dp_phyclk_in_khz;
-+	int max_dp_phyclk_in_khz;
-+	bool dispclk_notify_pplib_done;
-+	bool pixelclk_notify_pplib_done;
-+	bool phyclk_notigy_pplib_done;
-+	int dcfclock_in_khz;
-+	int dppclk_in_khz;
-+	int mclk_in_khz;
-+	int phyclk_in_khz;
-+	int common_vdd_level;
-+};
-+
-+
-+/* Structure containing all state-dependent clocks
-+ * (dependent on "enum clocks_state") */
-+struct state_dependent_clocks {
-+	int display_clk_khz;
-+	int pixel_clk_khz;
-+};
-+
-+struct display_clock {
-+	struct dc_context *ctx;
-+	const struct display_clock_funcs *funcs;
-+
-+	enum dm_pp_clocks_state max_clks_state;
-+	enum dm_pp_clocks_state cur_min_clks_state;
-+	struct clocks_value cur_clocks_value;
-+};
-+
-+struct display_clock_funcs {
-+	int (*set_clock)(struct display_clock *disp_clk,
-+		int requested_clock_khz);
-+
-+	enum dm_pp_clocks_state (*get_required_clocks_state)(
-+		struct display_clock *disp_clk,
-+		struct state_dependent_clocks *req_clocks);
-+
-+	bool (*set_min_clocks_state)(struct display_clock *disp_clk,
-+		enum dm_pp_clocks_state dm_pp_clocks_state);
-+
-+	int (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
-+
-+	bool (*apply_clock_voltage_request)(
-+		struct display_clock *disp_clk,
-+		enum dm_pp_clock_type clocks_type,
-+		int clocks_in_khz,
-+		bool pre_mode_set,
-+		bool update_dp_phyclk);
-+};
-+
-+#endif /* __DISPLAY_CLOCK_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h.0130~	2017-12-14 06:39:58.436903582 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h	2017-12-14 06:39:58.436903582 +0100
-@@ -0,0 +1,66 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_DMCU_H__
-+#define __DC_DMCU_H__
-+
-+#include "dm_services_types.h"
-+
-+enum dmcu_state {
-+	DMCU_NOT_INITIALIZED = 0,
-+	DMCU_RUNNING = 1
-+};
-+
-+struct dmcu_version {
-+	unsigned int day;
-+	unsigned int month;
-+	unsigned int year;
-+	unsigned int interface_version;
-+};
-+
-+struct dmcu {
-+	struct dc_context *ctx;
-+	const struct dmcu_funcs *funcs;
-+
-+	enum dmcu_state dmcu_state;
-+	struct dmcu_version dmcu_version;
-+};
-+
-+struct dmcu_funcs {
-+	bool (*dmcu_init)(struct dmcu *dmcu);
-+	bool (*load_iram)(struct dmcu *dmcu,
-+			unsigned int start_offset,
-+			const char *src,
-+			unsigned int bytes);
-+	void (*set_psr_enable)(struct dmcu *dmcu, bool enable, bool wait);
-+	void (*setup_psr)(struct dmcu *dmcu,
-+			struct dc_link *link,
-+			struct psr_context *psr_context);
-+	void (*get_psr_state)(struct dmcu *dmcu, uint32_t *psr_state);
-+	void (*set_psr_wait_loop)(struct dmcu *dmcu,
-+			unsigned int wait_loop_number);
-+	void (*get_psr_wait_loop)(unsigned int *psr_wait_loop_number);
-+};
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h.0130~	2017-12-14 06:39:58.437903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h	2017-12-14 06:39:58.437903583 +0100
-@@ -0,0 +1,138 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+
-+#ifndef __DAL_DPP_H__
-+#define __DAL_DPP_H__
-+
-+#include "transform.h"
-+
-+struct dpp {
-+	const struct dpp_funcs *funcs;
-+	struct dc_context *ctx;
-+	int inst;
-+	struct dpp_caps *caps;
-+	struct pwl_params regamma_params;
-+};
-+
-+struct dpp_grph_csc_adjustment {
-+	struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
-+	enum graphics_gamut_adjust_type gamut_adjust_type;
-+};
-+
-+struct dpp_funcs {
-+	void (*dpp_reset)(struct dpp *dpp);
-+
-+	void (*dpp_set_scaler)(struct dpp *dpp,
-+			const struct scaler_data *scl_data);
-+
-+	void (*dpp_set_pixel_storage_depth)(
-+			struct dpp *dpp,
-+			enum lb_pixel_depth depth,
-+			const struct bit_depth_reduction_params *bit_depth_params);
-+
-+	bool (*dpp_get_optimal_number_of_taps)(
-+			struct dpp *dpp,
-+			struct scaler_data *scl_data,
-+			const struct scaling_taps *in_taps);
-+
-+	void (*dpp_set_gamut_remap)(
-+			struct dpp *dpp,
-+			const struct dpp_grph_csc_adjustment *adjust);
-+
-+	void (*dpp_set_csc_default)(
-+		struct dpp *dpp,
-+		enum dc_color_space colorspace);
-+
-+	void (*dpp_set_csc_adjustment)(
-+		struct dpp *dpp,
-+		const struct out_csc_color_matrix *tbl_entry);
-+
-+	void (*dpp_power_on_regamma_lut)(
-+		struct dpp *dpp,
-+		bool power_on);
-+
-+	void (*dpp_program_regamma_lut)(
-+			struct dpp *dpp,
-+			const struct pwl_result_data *rgb,
-+			uint32_t num);
-+
-+	void (*dpp_configure_regamma_lut)(
-+			struct dpp *dpp,
-+			bool is_ram_a);
-+
-+	void (*dpp_program_regamma_lutb_settings)(
-+			struct dpp *dpp,
-+			const struct pwl_params *params);
-+
-+	void (*dpp_program_regamma_luta_settings)(
-+			struct dpp *dpp,
-+			const struct pwl_params *params);
-+
-+	void (*dpp_program_regamma_pwl)(
-+		struct dpp *dpp,
-+		const struct pwl_params *params,
-+		enum opp_regamma mode);
-+
-+	void (*dpp_program_bias_and_scale)(
-+			struct dpp *dpp,
-+			struct dc_bias_and_scale *params);
-+
-+	void (*dpp_set_degamma)(
-+			struct dpp *dpp_base,
-+			enum ipp_degamma_mode mode);
-+
-+	void (*dpp_program_input_lut)(
-+			struct dpp *dpp_base,
-+			const struct dc_gamma *gamma);
-+
-+	void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,
-+									 const struct pwl_params *params);
-+
-+	void (*dpp_setup)(
-+			struct dpp *dpp_base,
-+			enum surface_pixel_format format,
-+			enum expansion_mode mode,
-+			struct csc_transform input_csc_color_matrix,
-+			enum dc_color_space input_color_space);
-+
-+	void (*dpp_full_bypass)(struct dpp *dpp_base);
-+
-+	void (*set_cursor_attributes)(
-+			struct dpp *dpp_base,
-+			const struct dc_cursor_attributes *attr);
-+
-+	void (*set_cursor_position)(
-+			struct dpp *dpp_base,
-+			const struct dc_cursor_position *pos,
-+			const struct dc_cursor_mi_param *param,
-+			uint32_t width
-+			);
-+
-+};
-+
-+
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h.0130~	2017-12-14 06:39:58.437903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h	2017-12-14 06:39:58.437903583 +0100
-@@ -0,0 +1,86 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GPIO_H__
-+#define __DAL_GPIO_H__
-+
-+#include "gpio_types.h"
-+
-+struct gpio {
-+	struct gpio_service *service;
-+	struct hw_gpio_pin *pin;
-+	enum gpio_id id;
-+	uint32_t en;
-+	enum gpio_mode mode;
-+	/* when GPIO comes from VBIOS, it has defined output state */
-+	enum gpio_pin_output_state output_state;
-+};
-+
-+#if 0
-+struct gpio_funcs {
-+
-+	struct hw_gpio_pin *(*create_ddc_data)(
-+		struct dc_context *ctx,
-+		enum gpio_id id,
-+		uint32_t en);
-+	struct hw_gpio_pin *(*create_ddc_clock)(
-+		struct dc_context *ctx,
-+		enum gpio_id id,
-+		uint32_t en);
-+	struct hw_gpio_pin *(*create_generic)(
-+		struct dc_context *ctx,
-+		enum gpio_id id,
-+		uint32_t en);
-+	struct hw_gpio_pin *(*create_hpd)(
-+		struct dc_context *ctx,
-+		enum gpio_id id,
-+		uint32_t en);
-+	struct hw_gpio_pin *(*create_gpio_pad)(
-+		struct dc_context *ctx,
-+		enum gpio_id id,
-+		uint32_t en);
-+	struct hw_gpio_pin *(*create_sync)(
-+		struct dc_context *ctx,
-+		enum gpio_id id,
-+		uint32_t en);
-+	struct hw_gpio_pin *(*create_gsl)(
-+		struct dc_context *ctx,
-+		enum gpio_id id,
-+		uint32_t en);
-+
-+	/* HW translation */
-+	bool (*offset_to_id)(
-+		uint32_t offset,
-+		uint32_t mask,
-+		enum gpio_id *id,
-+		uint32_t *en);
-+	bool (*id_to_offset)(
-+		enum gpio_id id,
-+		uint32_t en,
-+		struct gpio_pin_info *info);
-+};
-+#endif
-+
-+#endif  /* __DAL_GPIO__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h.0130~	2017-12-14 06:39:58.437903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h	2017-12-14 06:39:58.437903583 +0100
-@@ -0,0 +1,110 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HUBP_H__
-+#define __DAL_HUBP_H__
-+
-+#include "mem_input.h"
-+
-+struct hubp {
-+	struct hubp_funcs *funcs;
-+	struct dc_context *ctx;
-+	struct dc_plane_address request_address;
-+	struct dc_plane_address current_address;
-+	int inst;
-+
-+	/* run time states */
-+	int opp_id;
-+	int mpcc_id;
-+	struct dc_cursor_attributes curs_attr;
-+	bool power_gated;
-+};
-+
-+
-+struct hubp_funcs {
-+	void (*hubp_setup)(
-+			struct hubp *hubp,
-+			struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
-+			struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
-+			struct _vcs_dpi_display_rq_regs_st *rq_regs,
-+			struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
-+
-+	void (*dcc_control)(struct hubp *hubp, bool enable,
-+			bool independent_64b_blks);
-+	void (*mem_program_viewport)(
-+			struct hubp *hubp,
-+			const struct rect *viewport,
-+			const struct rect *viewport_c);
-+
-+	bool (*hubp_program_surface_flip_and_addr)(
-+		struct hubp *hubp,
-+		const struct dc_plane_address *address,
-+		bool flip_immediate);
-+
-+	void (*hubp_program_pte_vm)(
-+		struct hubp *hubp,
-+		enum surface_pixel_format format,
-+		union dc_tiling_info *tiling_info,
-+		enum dc_rotation_angle rotation);
-+
-+	void (*hubp_set_vm_system_aperture_settings)(
-+			struct hubp *hubp,
-+			struct vm_system_aperture_param *apt);
-+
-+	void (*hubp_set_vm_context0_settings)(
-+			struct hubp *hubp,
-+			const struct vm_context0_param *vm0);
-+
-+	void (*hubp_program_surface_config)(
-+		struct hubp *hubp,
-+		enum surface_pixel_format format,
-+		union dc_tiling_info *tiling_info,
-+		union plane_size *plane_size,
-+		enum dc_rotation_angle rotation,
-+		struct dc_plane_dcc_param *dcc,
-+		bool horizontal_mirror);
-+
-+	bool (*hubp_is_flip_pending)(struct hubp *hubp);
-+
-+	void (*hubp_update_dchub)(struct hubp *hubp,
-+				struct dchub_init_data *dh_data);
-+
-+	void (*set_blank)(struct hubp *hubp, bool blank);
-+	void (*set_hubp_blank_en)(struct hubp *hubp, bool blank);
-+
-+	void (*set_cursor_attributes)(
-+			struct hubp *hubp,
-+			const struct dc_cursor_attributes *attr);
-+
-+	void (*set_cursor_position)(
-+			struct hubp *hubp,
-+			const struct dc_cursor_position *pos,
-+			const struct dc_cursor_mi_param *param);
-+
-+	void (*hubp_disconnect)(struct hubp *hubp);
-+
-+};
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h.0130~	2017-12-14 06:39:58.437903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h	2017-12-14 06:39:58.437903583 +0100
-@@ -0,0 +1,155 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_HW_SHARED_H__
-+#define __DAL_HW_SHARED_H__
-+
-+#include "os_types.h"
-+#include "fixed31_32.h"
-+#include "dc_hw_types.h"
-+
-+/******************************************************************************
-+ * Data types shared between different Virtual HW blocks
-+ ******************************************************************************/
-+
-+#define MAX_PIPES 6
-+
-+struct gamma_curve {
-+	uint32_t offset;
-+	uint32_t segments_num;
-+};
-+
-+struct curve_points {
-+	struct fixed31_32 x;
-+	struct fixed31_32 y;
-+	struct fixed31_32 offset;
-+	struct fixed31_32 slope;
-+
-+	uint32_t custom_float_x;
-+	uint32_t custom_float_y;
-+	uint32_t custom_float_offset;
-+	uint32_t custom_float_slope;
-+};
-+
-+struct pwl_result_data {
-+	struct fixed31_32 red;
-+	struct fixed31_32 green;
-+	struct fixed31_32 blue;
-+
-+	struct fixed31_32 delta_red;
-+	struct fixed31_32 delta_green;
-+	struct fixed31_32 delta_blue;
-+
-+	uint32_t red_reg;
-+	uint32_t green_reg;
-+	uint32_t blue_reg;
-+
-+	uint32_t delta_red_reg;
-+	uint32_t delta_green_reg;
-+	uint32_t delta_blue_reg;
-+};
-+
-+struct pwl_params {
-+	struct gamma_curve arr_curve_points[34];
-+	struct curve_points arr_points[2];
-+	struct pwl_result_data rgb_resulted[256 + 3];
-+	uint32_t hw_points_num;
-+};
-+
-+/* move to dpp
-+ * while we are moving functionality out of opp to dpp to align
-+ * HW programming to HW IP, we define these struct in hw_shared
-+ * so we can still compile while refactoring
-+ */
-+
-+enum lb_pixel_depth {
-+	/* do not change the values because it is used as bit vector */
-+	LB_PIXEL_DEPTH_18BPP = 1,
-+	LB_PIXEL_DEPTH_24BPP = 2,
-+	LB_PIXEL_DEPTH_30BPP = 4,
-+	LB_PIXEL_DEPTH_36BPP = 8
-+};
-+
-+enum graphics_csc_adjust_type {
-+	GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
-+	GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
-+	GRAPHICS_CSC_ADJUST_TYPE_SW  /*use adjustments */
-+};
-+
-+enum ipp_degamma_mode {
-+	IPP_DEGAMMA_MODE_BYPASS,
-+	IPP_DEGAMMA_MODE_HW_sRGB,
-+	IPP_DEGAMMA_MODE_HW_xvYCC,
-+	IPP_DEGAMMA_MODE_USER_PWL
-+};
-+
-+enum ipp_output_format {
-+	IPP_OUTPUT_FORMAT_12_BIT_FIX,
-+	IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
-+	IPP_OUTPUT_FORMAT_FLOAT
-+};
-+
-+enum expansion_mode {
-+	EXPANSION_MODE_DYNAMIC,
-+	EXPANSION_MODE_ZERO
-+};
-+
-+struct default_adjustment {
-+	enum lb_pixel_depth lb_color_depth;
-+	enum dc_color_space out_color_space;
-+	enum dc_color_space in_color_space;
-+	enum dc_color_depth color_depth;
-+	enum pixel_format surface_pixel_format;
-+	enum graphics_csc_adjust_type csc_adjust_type;
-+	bool force_hw_default;
-+};
-+
-+struct out_csc_color_matrix {
-+	enum dc_color_space color_space;
-+	uint16_t regval[12];
-+};
-+
-+enum opp_regamma {
-+	OPP_REGAMMA_BYPASS = 0,
-+	OPP_REGAMMA_SRGB,
-+	OPP_REGAMMA_3_6,
-+	OPP_REGAMMA_USER
-+};
-+
-+struct csc_transform {
-+	uint16_t matrix[12];
-+	bool enable_adjustment;
-+};
-+
-+struct dc_bias_and_scale {
-+	uint16_t scale_red;
-+	uint16_t bias_red;
-+	uint16_t scale_green;
-+	uint16_t bias_green;
-+	uint16_t scale_blue;
-+	uint16_t bias_blue;
-+};
-+
-+#endif /* __DAL_HW_SHARED_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h.0130~	2017-12-14 06:39:58.437903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h	2017-12-14 06:39:58.437903583 +0100
-@@ -0,0 +1,114 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IPP_H__
-+#define __DAL_IPP_H__
-+
-+#include "hw_shared.h"
-+#include "dc_hw_types.h"
-+
-+#define MAXTRIX_COEFFICIENTS_NUMBER 12
-+#define MAXTRIX_COEFFICIENTS_WRAP_NUMBER (MAXTRIX_COEFFICIENTS_NUMBER + 4)
-+#define MAX_OVL_MATRIX_COUNT 12
-+
-+/* IPP RELATED */
-+struct input_pixel_processor {
-+	struct  dc_context *ctx;
-+	unsigned int inst;
-+	const struct ipp_funcs *funcs;
-+};
-+
-+enum ipp_prescale_mode {
-+	IPP_PRESCALE_MODE_BYPASS,
-+	IPP_PRESCALE_MODE_FIXED_SIGNED,
-+	IPP_PRESCALE_MODE_FLOAT_SIGNED,
-+	IPP_PRESCALE_MODE_FIXED_UNSIGNED,
-+	IPP_PRESCALE_MODE_FLOAT_UNSIGNED
-+};
-+
-+struct ipp_prescale_params {
-+	enum ipp_prescale_mode mode;
-+	uint16_t bias;
-+	uint16_t scale;
-+};
-+
-+
-+
-+enum ovl_color_space {
-+	OVL_COLOR_SPACE_UNKNOWN = 0,
-+	OVL_COLOR_SPACE_RGB,
-+	OVL_COLOR_SPACE_YUV601,
-+	OVL_COLOR_SPACE_YUV709
-+};
-+
-+
-+struct ipp_funcs {
-+
-+	/*** cursor ***/
-+	void (*ipp_cursor_set_position)(
-+		struct input_pixel_processor *ipp,
-+		const struct dc_cursor_position *position,
-+		const struct dc_cursor_mi_param *param);
-+
-+	void (*ipp_cursor_set_attributes)(
-+		struct input_pixel_processor *ipp,
-+		const struct dc_cursor_attributes *attributes);
-+
-+	/*** setup input pixel processing ***/
-+
-+	/* put the entire pixel processor to bypass */
-+	void (*ipp_full_bypass)(
-+			struct input_pixel_processor *ipp);
-+
-+	/* setup ipp to expand/convert input to pixel processor internal format */
-+	void (*ipp_setup)(
-+		struct input_pixel_processor *ipp,
-+		enum surface_pixel_format format,
-+		enum expansion_mode mode,
-+		struct csc_transform input_csc_color_matrix,
-+		enum dc_color_space input_color_space);
-+
-+	/* DCE function to setup IPP.  TODO: see if we can consolidate to setup */
-+	void (*ipp_program_prescale)(
-+			struct input_pixel_processor *ipp,
-+			struct ipp_prescale_params *params);
-+
-+	void (*ipp_program_input_lut)(
-+			struct input_pixel_processor *ipp,
-+			const struct dc_gamma *gamma);
-+
-+	/*** DEGAMMA RELATED ***/
-+	void (*ipp_set_degamma)(
-+		struct input_pixel_processor *ipp,
-+		enum ipp_degamma_mode mode);
-+
-+	void (*ipp_program_degamma_pwl)(
-+		struct input_pixel_processor *ipp,
-+		const struct pwl_params *params);
-+
-+	void (*ipp_destroy)(struct input_pixel_processor **ipp);
-+};
-+
-+#endif /* __DAL_IPP_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h.0130~	2017-12-14 06:39:58.437903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h	2017-12-14 06:39:58.437903583 +0100
-@@ -0,0 +1,134 @@
-+/*
-+ * link_encoder.h
-+ *
-+ *  Created on: Oct 6, 2015
-+ *      Author: yonsun
-+ */
-+
-+#ifndef LINK_ENCODER_H_
-+#define LINK_ENCODER_H_
-+
-+#include "grph_object_defs.h"
-+#include "signal_types.h"
-+#include "dc_types.h"
-+
-+struct dc_context;
-+struct encoder_set_dp_phy_pattern_param;
-+struct link_mst_stream_allocation_table;
-+struct dc_link_settings;
-+struct link_training_settings;
-+struct pipe_ctx;
-+
-+struct encoder_init_data {
-+	enum channel_id channel;
-+	struct graphics_object_id connector;
-+	enum hpd_source_id hpd_source;
-+	/* TODO: in DAL2, here was pointer to EventManagerInterface */
-+	struct graphics_object_id encoder;
-+	struct dc_context *ctx;
-+	enum transmitter transmitter;
-+};
-+
-+struct encoder_feature_support {
-+	union {
-+		struct {
-+			uint32_t IS_HBR2_CAPABLE:1;
-+			uint32_t IS_HBR3_CAPABLE:1;
-+			uint32_t IS_TPS3_CAPABLE:1;
-+			uint32_t IS_TPS4_CAPABLE:1;
-+			uint32_t IS_YCBCR_CAPABLE:1;
-+			uint32_t HDMI_6GB_EN:1;
-+		} bits;
-+		uint32_t raw;
-+	} flags;
-+
-+	enum dc_color_depth max_hdmi_deep_color;
-+	unsigned int max_hdmi_pixel_clock;
-+	bool ycbcr420_supported;
-+};
-+
-+union dpcd_psr_configuration {
-+	struct {
-+		unsigned char ENABLE                    : 1;
-+		unsigned char TRANSMITTER_ACTIVE_IN_PSR : 1;
-+		unsigned char CRC_VERIFICATION          : 1;
-+		unsigned char FRAME_CAPTURE_INDICATION  : 1;
-+		/* For eDP 1.4, PSR v2*/
-+		unsigned char LINE_CAPTURE_INDICATION   : 1;
-+		/* For eDP 1.4, PSR v2*/
-+		unsigned char IRQ_HPD_WITH_CRC_ERROR    : 1;
-+		unsigned char RESERVED                  : 2;
-+	} bits;
-+	unsigned char raw;
-+};
-+
-+union psr_error_status {
-+	struct {
-+		unsigned char LINK_CRC_ERROR        :1;
-+		unsigned char RFB_STORAGE_ERROR     :1;
-+		unsigned char RESERVED              :6;
-+	} bits;
-+	unsigned char raw;
-+};
-+
-+union psr_sink_psr_status {
-+	struct {
-+	unsigned char SINK_SELF_REFRESH_STATUS  :3;
-+	unsigned char RESERVED                  :5;
-+	} bits;
-+	unsigned char raw;
-+};
-+
-+struct link_encoder {
-+	const struct link_encoder_funcs *funcs;
-+	int32_t aux_channel_offset;
-+	struct dc_context *ctx;
-+	struct graphics_object_id id;
-+	struct graphics_object_id connector;
-+	uint32_t output_signals;
-+	enum engine_id preferred_engine;
-+	struct encoder_feature_support features;
-+	enum transmitter transmitter;
-+	enum hpd_source_id hpd_source;
-+};
-+
-+struct link_encoder_funcs {
-+	bool (*validate_output_with_stream)(
-+		struct link_encoder *enc, const struct dc_stream_state *stream);
-+	void (*hw_init)(struct link_encoder *enc);
-+	void (*setup)(struct link_encoder *enc,
-+		enum signal_type signal);
-+	void (*enable_tmds_output)(struct link_encoder *enc,
-+		enum clock_source_id clock_source,
-+		enum dc_color_depth color_depth,
-+		bool hdmi,
-+		bool dual_link,
-+		uint32_t pixel_clock);
-+	void (*enable_dp_output)(struct link_encoder *enc,
-+		const struct dc_link_settings *link_settings,
-+		enum clock_source_id clock_source);
-+	void (*enable_dp_mst_output)(struct link_encoder *enc,
-+		const struct dc_link_settings *link_settings,
-+		enum clock_source_id clock_source);
-+	void (*disable_output)(struct link_encoder *link_enc,
-+		enum signal_type signal);
-+	void (*dp_set_lane_settings)(struct link_encoder *enc,
-+		const struct link_training_settings *link_settings);
-+	void (*dp_set_phy_pattern)(struct link_encoder *enc,
-+		const struct encoder_set_dp_phy_pattern_param *para);
-+	void (*update_mst_stream_allocation_table)(
-+		struct link_encoder *enc,
-+		const struct link_mst_stream_allocation_table *table);
-+	void (*psr_program_dp_dphy_fast_training)(struct link_encoder *enc,
-+			bool exit_link_training_required);
-+	void (*psr_program_secondary_packet)(struct link_encoder *enc,
-+				unsigned int sdp_transmit_line_num_deadline);
-+	void (*connect_dig_be_to_fe)(struct link_encoder *enc,
-+		enum engine_id engine,
-+		bool connect);
-+	void (*enable_hpd)(struct link_encoder *enc);
-+	void (*disable_hpd)(struct link_encoder *enc);
-+	void (*destroy)(struct link_encoder **enc);
-+};
-+
-+#endif /* LINK_ENCODER_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h.0130~	2017-12-14 06:39:58.437903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h	2017-12-14 06:39:58.437903583 +0100
-@@ -0,0 +1,175 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_MEM_INPUT_H__
-+#define __DAL_MEM_INPUT_H__
-+
-+#include "dc.h"
-+#include "include/grph_object_id.h"
-+
-+#include "dml/display_mode_structs.h"
-+
-+struct dchub_init_data;
-+struct cstate_pstate_watermarks_st {
-+	uint32_t cstate_exit_ns;
-+	uint32_t cstate_enter_plus_exit_ns;
-+	uint32_t pstate_change_ns;
-+};
-+
-+struct dcn_watermarks {
-+	uint32_t pte_meta_urgent_ns;
-+	uint32_t urgent_ns;
-+	struct cstate_pstate_watermarks_st cstate_pstate;
-+};
-+
-+struct dcn_watermark_set {
-+	struct dcn_watermarks a;
-+	struct dcn_watermarks b;
-+	struct dcn_watermarks c;
-+	struct dcn_watermarks d;
-+};
-+
-+struct dce_watermarks {
-+	int a_mark;
-+	int b_mark;
-+	int c_mark;
-+	int d_mark;
-+};
-+
-+struct stutter_modes {
-+	bool enhanced;
-+	bool quad_dmif_buffer;
-+	bool watermark_nb_pstate;
-+};
-+
-+struct mem_input {
-+	struct mem_input_funcs *funcs;
-+	struct dc_context *ctx;
-+	struct dc_plane_address request_address;
-+	struct dc_plane_address current_address;
-+	int inst;
-+	struct stutter_modes stutter_mode;
-+};
-+
-+struct vm_system_aperture_param {
-+	PHYSICAL_ADDRESS_LOC sys_default;
-+	PHYSICAL_ADDRESS_LOC sys_low;
-+	PHYSICAL_ADDRESS_LOC sys_high;
-+};
-+
-+struct vm_context0_param {
-+	PHYSICAL_ADDRESS_LOC pte_base;
-+	PHYSICAL_ADDRESS_LOC pte_start;
-+	PHYSICAL_ADDRESS_LOC pte_end;
-+	PHYSICAL_ADDRESS_LOC fault_default;
-+};
-+
-+struct mem_input_funcs {
-+	void (*mem_input_setup)(
-+			struct mem_input *mem_input,
-+			struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
-+			struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
-+			struct _vcs_dpi_display_rq_regs_st *rq_regs,
-+			struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
-+
-+	void (*dcc_control)(struct mem_input *mem_input, bool enable,
-+			bool independent_64b_blks);
-+	void (*mem_program_viewport)(
-+			struct mem_input *mem_input,
-+			const struct rect *viewport,
-+			const struct rect *viewport_c);
-+
-+	void (*mem_input_program_display_marks)(
-+		struct mem_input *mem_input,
-+		struct dce_watermarks nbp,
-+		struct dce_watermarks stutter,
-+		struct dce_watermarks urgent,
-+		uint32_t total_dest_line_time_ns);
-+
-+	void (*mem_input_program_chroma_display_marks)(
-+			struct mem_input *mem_input,
-+			struct dce_watermarks nbp,
-+			struct dce_watermarks stutter,
-+			struct dce_watermarks urgent,
-+			uint32_t total_dest_line_time_ns);
-+
-+	void (*allocate_mem_input)(
-+		struct mem_input *mem_input,
-+		uint32_t h_total,/* for current target */
-+		uint32_t v_total,/* for current target */
-+		uint32_t pix_clk_khz,/* for current target */
-+		uint32_t total_streams_num);
-+
-+	void (*free_mem_input)(
-+		struct mem_input *mem_input,
-+		uint32_t paths_num);
-+
-+	bool (*mem_input_program_surface_flip_and_addr)(
-+		struct mem_input *mem_input,
-+		const struct dc_plane_address *address,
-+		bool flip_immediate);
-+
-+	void (*mem_input_program_pte_vm)(
-+		struct mem_input *mem_input,
-+		enum surface_pixel_format format,
-+		union dc_tiling_info *tiling_info,
-+		enum dc_rotation_angle rotation);
-+
-+	void (*mem_input_set_vm_system_aperture_settings)(
-+			struct mem_input *mem_input,
-+			struct vm_system_aperture_param *apt);
-+
-+	void (*mem_input_set_vm_context0_settings)(
-+			struct mem_input *mem_input,
-+			const struct vm_context0_param *vm0);
-+
-+	void (*mem_input_program_surface_config)(
-+		struct mem_input *mem_input,
-+		enum surface_pixel_format format,
-+		union dc_tiling_info *tiling_info,
-+		union plane_size *plane_size,
-+		enum dc_rotation_angle rotation,
-+		struct dc_plane_dcc_param *dcc,
-+		bool horizontal_mirror);
-+
-+	bool (*mem_input_is_flip_pending)(struct mem_input *mem_input);
-+
-+	void (*mem_input_update_dchub)(struct mem_input *mem_input,
-+				struct dchub_init_data *dh_data);
-+
-+	void (*set_blank)(struct mem_input *mi, bool blank);
-+	void (*set_hubp_blank_en)(struct mem_input *mi, bool blank);
-+
-+	void (*set_cursor_attributes)(
-+			struct mem_input *mem_input,
-+			const struct dc_cursor_attributes *attr);
-+
-+	void (*set_cursor_position)(
-+			struct mem_input *mem_input,
-+			const struct dc_cursor_position *pos,
-+			const struct dc_cursor_mi_param *param);
-+
-+};
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h.0130~	2017-12-14 06:39:58.437903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h	2017-12-14 06:39:58.437903583 +0100
-@@ -0,0 +1,63 @@
-+/* Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_MPCC_H__
-+#define __DC_MPCC_H__
-+
-+#include "dc_hw_types.h"
-+#include "opp.h"
-+
-+struct mpcc_cfg {
-+	int dpp_id;
-+	int opp_id;
-+	struct mpc_tree_cfg *tree_cfg;
-+	unsigned int z_index;
-+
-+	struct tg_color black_color;
-+	bool per_pixel_alpha;
-+	bool pre_multiplied_alpha;
-+};
-+
-+struct mpc {
-+	const struct mpc_funcs *funcs;
-+	struct dc_context *ctx;
-+};
-+
-+struct mpc_funcs {
-+	int (*add)(struct mpc *mpc, struct mpcc_cfg *cfg);
-+
-+	void (*remove)(struct mpc *mpc,
-+			struct mpc_tree_cfg *tree_cfg,
-+			int opp_id,
-+			int mpcc_inst);
-+
-+	void (*wait_for_idle)(struct mpc *mpc, int id);
-+
-+	void (*update_blend_mode)(struct mpc *mpc, struct mpcc_cfg *cfg);
-+
-+	int (*get_opp_id)(struct mpc *mpc, int mpcc_id);
-+
-+};
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h.0130~	2017-12-14 06:39:58.437903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h	2017-12-14 06:39:58.437903583 +0100
-@@ -0,0 +1,301 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_OPP_H__
-+#define __DAL_OPP_H__
-+
-+#include "hw_shared.h"
-+#include "dc_hw_types.h"
-+#include "transform.h"
-+
-+struct fixed31_32;
-+
-+/* TODO: Need cleanup */
-+enum clamping_range {
-+	CLAMPING_FULL_RANGE = 0,	   /* No Clamping */
-+	CLAMPING_LIMITED_RANGE_8BPC,   /* 8  bpc: Clamping 1  to FE */
-+	CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4  to 3FB */
-+	CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */
-+	/* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */
-+	CLAMPING_LIMITED_RANGE_PROGRAMMABLE
-+};
-+
-+struct clamping_and_pixel_encoding_params {
-+	enum dc_pixel_encoding pixel_encoding; /* Pixel Encoding */
-+	enum clamping_range clamping_level; /* Clamping identifier */
-+	enum dc_color_depth c_depth; /* Deep color use. */
-+};
-+
-+struct bit_depth_reduction_params {
-+	struct {
-+		/* truncate/round */
-+		/* trunc/round enabled*/
-+		uint32_t TRUNCATE_ENABLED:1;
-+		/* 2 bits: 0=6 bpc, 1=8 bpc, 2 = 10bpc*/
-+		uint32_t TRUNCATE_DEPTH:2;
-+		/* truncate or round*/
-+		uint32_t TRUNCATE_MODE:1;
-+
-+		/* spatial dither */
-+		/* Spatial Bit Depth Reduction enabled*/
-+		uint32_t SPATIAL_DITHER_ENABLED:1;
-+		/* 2 bits: 0=6 bpc, 1 = 8 bpc, 2 = 10bpc*/
-+		uint32_t SPATIAL_DITHER_DEPTH:2;
-+		/* 0-3 to select patterns*/
-+		uint32_t SPATIAL_DITHER_MODE:2;
-+		/* Enable RGB random dithering*/
-+		uint32_t RGB_RANDOM:1;
-+		/* Enable Frame random dithering*/
-+		uint32_t FRAME_RANDOM:1;
-+		/* Enable HighPass random dithering*/
-+		uint32_t HIGHPASS_RANDOM:1;
-+
-+		/* temporal dither*/
-+		 /* frame modulation enabled*/
-+		uint32_t FRAME_MODULATION_ENABLED:1;
-+		/* same as for trunc/spatial*/
-+		uint32_t FRAME_MODULATION_DEPTH:2;
-+		/* 2/4 gray levels*/
-+		uint32_t TEMPORAL_LEVEL:1;
-+		uint32_t FRC25:2;
-+		uint32_t FRC50:2;
-+		uint32_t FRC75:2;
-+	} flags;
-+
-+	uint32_t r_seed_value;
-+	uint32_t b_seed_value;
-+	uint32_t g_seed_value;
-+	enum dc_pixel_encoding pixel_encoding;
-+};
-+
-+enum wide_gamut_regamma_mode {
-+	/*  0x0  - BITS2:0 Bypass */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS,
-+	/*  0x1  - Fixed curve sRGB 2.4 */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_SRGB24,
-+	/*  0x2  - Fixed curve xvYCC 2.22 */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_XYYCC22,
-+	/*  0x3  - Programmable control A */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_A,
-+	/*  0x4  - Programmable control B */
-+	WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_B,
-+	/*  0x0  - BITS6:4 Bypass */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_BYPASS,
-+	/*  0x1  - Fixed curve sRGB 2.4 */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_SRGB24,
-+	/*  0x2  - Fixed curve xvYCC 2.22 */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_XYYCC22,
-+	/*  0x3  - Programmable control A */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_A,
-+	/*  0x4  - Programmable control B */
-+	WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_B
-+};
-+
-+struct gamma_pixel {
-+	struct fixed31_32 r;
-+	struct fixed31_32 g;
-+	struct fixed31_32 b;
-+};
-+
-+enum channel_name {
-+	CHANNEL_NAME_RED,
-+	CHANNEL_NAME_GREEN,
-+	CHANNEL_NAME_BLUE
-+};
-+
-+struct custom_float_format {
-+	uint32_t mantissa_bits;
-+	uint32_t exponenta_bits;
-+	bool sign;
-+};
-+
-+struct custom_float_value {
-+	uint32_t mantissa;
-+	uint32_t exponenta;
-+	uint32_t value;
-+	bool negative;
-+};
-+
-+struct hw_x_point {
-+	uint32_t custom_float_x;
-+	struct fixed31_32 x;
-+	struct fixed31_32 regamma_y_red;
-+	struct fixed31_32 regamma_y_green;
-+	struct fixed31_32 regamma_y_blue;
-+
-+};
-+
-+struct pwl_float_data_ex {
-+	struct fixed31_32 r;
-+	struct fixed31_32 g;
-+	struct fixed31_32 b;
-+	struct fixed31_32 delta_r;
-+	struct fixed31_32 delta_g;
-+	struct fixed31_32 delta_b;
-+};
-+
-+enum hw_point_position {
-+	/* hw point sits between left and right sw points */
-+	HW_POINT_POSITION_MIDDLE,
-+	/* hw point lays left from left (smaller) sw point */
-+	HW_POINT_POSITION_LEFT,
-+	/* hw point lays stays from right (bigger) sw point */
-+	HW_POINT_POSITION_RIGHT
-+};
-+
-+struct gamma_point {
-+	int32_t left_index;
-+	int32_t right_index;
-+	enum hw_point_position pos;
-+	struct fixed31_32 coeff;
-+};
-+
-+struct pixel_gamma_point {
-+	struct gamma_point r;
-+	struct gamma_point g;
-+	struct gamma_point b;
-+};
-+
-+struct gamma_coefficients {
-+	struct fixed31_32 a0[3];
-+	struct fixed31_32 a1[3];
-+	struct fixed31_32 a2[3];
-+	struct fixed31_32 a3[3];
-+	struct fixed31_32 user_gamma[3];
-+	struct fixed31_32 user_contrast;
-+	struct fixed31_32 user_brightness;
-+};
-+
-+struct pwl_float_data {
-+	struct fixed31_32 r;
-+	struct fixed31_32 g;
-+	struct fixed31_32 b;
-+};
-+
-+struct mpc_tree_cfg {
-+	int num_pipes;
-+	int dpp[MAX_PIPES];
-+	int mpcc[MAX_PIPES];
-+};
-+
-+struct output_pixel_processor {
-+	struct dc_context *ctx;
-+	uint32_t inst;
-+	struct pwl_params regamma_params;
-+	struct mpc_tree_cfg mpc_tree;
-+	bool mpcc_disconnect_pending[MAX_PIPES];
-+	const struct opp_funcs *funcs;
-+};
-+
-+enum fmt_stereo_action {
-+	FMT_STEREO_ACTION_ENABLE = 0,
-+	FMT_STEREO_ACTION_DISABLE,
-+	FMT_STEREO_ACTION_UPDATE_POLARITY
-+};
-+
-+struct opp_grph_csc_adjustment {
-+	//enum grph_color_adjust_option color_adjust_option;
-+	enum dc_color_space c_space;
-+	enum dc_color_depth color_depth; /* clean up to uint32_t */
-+	enum graphics_csc_adjust_type   csc_adjust_type;
-+	int32_t adjust_divider;
-+	int32_t grph_cont;
-+	int32_t grph_sat;
-+	int32_t grph_bright;
-+	int32_t grph_hue;
-+};
-+
-+/* Underlay related types */
-+
-+struct hw_adjustment_range {
-+	int32_t hw_default;
-+	int32_t min;
-+	int32_t max;
-+	int32_t step;
-+	uint32_t divider; /* (actually HW range is min/divider; divider !=0) */
-+};
-+
-+enum ovl_csc_adjust_item {
-+	OVERLAY_BRIGHTNESS = 0,
-+	OVERLAY_GAMMA,
-+	OVERLAY_CONTRAST,
-+	OVERLAY_SATURATION,
-+	OVERLAY_HUE,
-+	OVERLAY_ALPHA,
-+	OVERLAY_ALPHA_PER_PIX,
-+	OVERLAY_COLOR_TEMPERATURE
-+};
-+
-+struct opp_funcs {
-+
-+
-+	/* FORMATTER RELATED */
-+
-+	void (*opp_program_fmt)(
-+			struct output_pixel_processor *opp,
-+			struct bit_depth_reduction_params *fmt_bit_depth,
-+			struct clamping_and_pixel_encoding_params *clamping);
-+
-+	void (*opp_set_dyn_expansion)(
-+		struct output_pixel_processor *opp,
-+		enum dc_color_space color_sp,
-+		enum dc_color_depth color_dpth,
-+		enum signal_type signal);
-+
-+	void (*opp_program_bit_depth_reduction)(
-+		struct output_pixel_processor *opp,
-+		const struct bit_depth_reduction_params *params);
-+
-+	/* underlay related */
-+	void (*opp_get_underlay_adjustment_range)(
-+			struct output_pixel_processor *opp,
-+			enum ovl_csc_adjust_item overlay_adjust_item,
-+			struct hw_adjustment_range *range);
-+
-+	void (*opp_destroy)(struct output_pixel_processor **opp);
-+
-+	void (*opp_set_stereo_polarity)(
-+			struct output_pixel_processor *opp,
-+			bool enable,
-+			bool rightEyePolarity);
-+
-+	void (*opp_set_test_pattern)(
-+			struct output_pixel_processor *opp,
-+			bool enable);
-+
-+	void (*opp_dpg_blank_enable)(
-+			struct output_pixel_processor *opp,
-+			bool enable,
-+			const struct tg_color *color,
-+			int width,
-+			int height);
-+
-+	void (*opp_convert_pti)(
-+		struct output_pixel_processor *opp,
-+		bool enable,
-+		bool polarity);
-+};
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h.0130~	2017-12-14 06:39:58.437903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h	2017-12-14 06:39:58.437903583 +0100
-@@ -0,0 +1,212 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_HW_SEQUENCER_H__
-+#define __DC_HW_SEQUENCER_H__
-+#include "dc_types.h"
-+#include "clock_source.h"
-+#include "inc/hw/timing_generator.h"
-+#include "inc/hw/link_encoder.h"
-+#include "core_status.h"
-+
-+enum pipe_gating_control {
-+	PIPE_GATING_CONTROL_DISABLE = 0,
-+	PIPE_GATING_CONTROL_ENABLE,
-+	PIPE_GATING_CONTROL_INIT
-+};
-+
-+struct dce_hwseq_wa {
-+	bool blnd_crtc_trigger;
-+	bool DEGVIDCN10_253;
-+};
-+
-+struct hwseq_wa_state {
-+	bool DEGVIDCN10_253_applied;
-+};
-+
-+struct dce_hwseq {
-+	struct dc_context *ctx;
-+	const struct dce_hwseq_registers *regs;
-+	const struct dce_hwseq_shift *shifts;
-+	const struct dce_hwseq_mask *masks;
-+	struct dce_hwseq_wa wa;
-+	struct hwseq_wa_state wa_state;
-+};
-+
-+struct pipe_ctx;
-+struct dc_state;
-+struct dchub_init_data;
-+struct dc_static_screen_events;
-+struct resource_pool;
-+struct resource_context;
-+
-+struct hw_sequencer_funcs {
-+
-+	void (*init_hw)(struct dc *dc);
-+
-+	enum dc_status (*apply_ctx_to_hw)(
-+			struct dc *dc, struct dc_state *context);
-+
-+	void (*reset_hw_ctx_wrap)(
-+			struct dc *dc, struct dc_state *context);
-+
-+	void (*apply_ctx_for_surface)(
-+			struct dc *dc,
-+			const struct dc_stream_state *stream,
-+			int num_planes,
-+			struct dc_state *context);
-+
-+	void (*set_plane_config)(
-+			const struct dc *dc,
-+			struct pipe_ctx *pipe_ctx,
-+			struct resource_context *res_ctx);
-+
-+	void (*program_gamut_remap)(
-+			struct pipe_ctx *pipe_ctx);
-+
-+	void (*program_csc_matrix)(
-+			struct pipe_ctx *pipe_ctx,
-+			enum dc_color_space colorspace,
-+			uint16_t *matrix);
-+
-+	void (*update_plane_addr)(
-+		const struct dc *dc,
-+		struct pipe_ctx *pipe_ctx);
-+
-+	void (*update_dchub)(
-+		struct dce_hwseq *hws,
-+		struct dchub_init_data *dh_data);
-+
-+	void (*update_pending_status)(
-+			struct pipe_ctx *pipe_ctx);
-+
-+	bool (*set_input_transfer_func)(
-+				struct pipe_ctx *pipe_ctx,
-+				const struct dc_plane_state *plane_state);
-+
-+	bool (*set_output_transfer_func)(
-+				struct pipe_ctx *pipe_ctx,
-+				const struct dc_stream_state *stream);
-+
-+	void (*power_down)(struct dc *dc);
-+
-+	void (*enable_accelerated_mode)(struct dc *dc);
-+
-+	void (*enable_timing_synchronization)(
-+			struct dc *dc,
-+			int group_index,
-+			int group_size,
-+			struct pipe_ctx *grouped_pipes[]);
-+
-+	void (*enable_per_frame_crtc_position_reset)(
-+			struct dc *dc,
-+			int group_size,
-+			struct pipe_ctx *grouped_pipes[]);
-+
-+	void (*enable_display_pipe_clock_gating)(
-+					struct dc_context *ctx,
-+					bool clock_gating);
-+
-+	bool (*enable_display_power_gating)(
-+					struct dc *dc,
-+					uint8_t controller_id,
-+					struct dc_bios *dcb,
-+					enum pipe_gating_control power_gating);
-+
-+	void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
-+
-+	void (*enable_plane)(struct dc *dc,
-+			struct pipe_ctx *pipe,
-+			struct dc_state *context);
-+
-+	void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
-+
-+	void (*enable_stream)(struct pipe_ctx *pipe_ctx);
-+
-+	void (*disable_stream)(struct pipe_ctx *pipe_ctx,
-+			int option);
-+
-+	void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
-+			struct dc_link_settings *link_settings);
-+
-+	void (*pipe_control_lock)(
-+				struct dc *dc,
-+				struct pipe_ctx *pipe,
-+				bool lock);
-+
-+	void (*set_bandwidth)(
-+			struct dc *dc,
-+			struct dc_state *context,
-+			bool decrease_allowed);
-+
-+	void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
-+			int vmin, int vmax);
-+
-+	void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
-+			struct crtc_position *position);
-+
-+	void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
-+			int num_pipes, const struct dc_static_screen_events *events);
-+
-+	enum dc_status (*prog_pixclk_crtc_otg)(
-+			struct pipe_ctx *pipe_ctx,
-+			struct dc_state *context,
-+			struct dc *dc);
-+
-+	void (*setup_stereo)(
-+			struct pipe_ctx *pipe_ctx,
-+			struct dc *dc);
-+
-+	void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
-+
-+	void (*log_hw_state)(struct dc *dc);
-+
-+	void (*wait_for_mpcc_disconnect)(struct dc *dc,
-+			struct resource_pool *res_pool,
-+			struct pipe_ctx *pipe_ctx);
-+
-+	void (*ready_shared_resources)(struct dc *dc, struct dc_state *context);
-+	void (*optimize_shared_resources)(struct dc *dc);
-+	void (*pplib_apply_display_requirements)(
-+			struct dc *dc,
-+			struct dc_state *context);
-+	void (*edp_power_control)(
-+			struct dc_link *link,
-+			bool enable);
-+	void (*edp_backlight_control)(
-+			struct dc_link *link,
-+			bool enable);
-+
-+};
-+
-+void color_space_to_black_color(
-+	const struct dc *dc,
-+	enum dc_color_space colorspace,
-+	struct tg_color *black_color);
-+
-+bool hwss_wait_for_blank_complete(
-+		struct timing_generator *tg);
-+
-+#endif /* __DC_HW_SEQUENCER_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h.0130~	2017-12-14 06:39:58.437903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h	2017-12-14 06:39:58.437903583 +0100
-@@ -0,0 +1,130 @@
-+/*
-+ * stream_encoder.h
-+ *
-+ */
-+
-+#ifndef STREAM_ENCODER_H_
-+#define STREAM_ENCODER_H_
-+
-+#include "audio_types.h"
-+
-+struct dc_bios;
-+struct dc_context;
-+struct dc_crtc_timing;
-+
-+struct encoder_info_packet {
-+	bool valid;
-+	uint8_t hb0;
-+	uint8_t hb1;
-+	uint8_t hb2;
-+	uint8_t hb3;
-+	uint8_t sb[32];
-+};
-+
-+struct encoder_info_frame {
-+	/* auxiliary video information */
-+	struct encoder_info_packet avi;
-+	struct encoder_info_packet gamut;
-+	struct encoder_info_packet vendor;
-+	/* source product description */
-+	struct encoder_info_packet spd;
-+	/* video stream configuration */
-+	struct encoder_info_packet vsc;
-+	/* HDR Static MetaData */
-+	struct encoder_info_packet hdrsmd;
-+};
-+
-+struct encoder_unblank_param {
-+	struct dc_link_settings link_settings;
-+	unsigned int pixel_clk_khz;
-+};
-+
-+struct encoder_set_dp_phy_pattern_param {
-+	enum dp_test_pattern dp_phy_pattern;
-+	const uint8_t *custom_pattern;
-+	uint32_t custom_pattern_size;
-+	enum dp_panel_mode dp_panel_mode;
-+};
-+
-+struct stream_encoder {
-+	const struct stream_encoder_funcs *funcs;
-+	struct dc_context *ctx;
-+	struct dc_bios *bp;
-+	enum engine_id id;
-+};
-+
-+struct stream_encoder_funcs {
-+	void (*dp_set_stream_attribute)(
-+		struct stream_encoder *enc,
-+		struct dc_crtc_timing *crtc_timing,
-+		enum dc_color_space output_color_space);
-+
-+	void (*hdmi_set_stream_attribute)(
-+		struct stream_encoder *enc,
-+		struct dc_crtc_timing *crtc_timing,
-+		int actual_pix_clk_khz,
-+		bool enable_audio);
-+
-+	void (*dvi_set_stream_attribute)(
-+		struct stream_encoder *enc,
-+		struct dc_crtc_timing *crtc_timing,
-+		bool is_dual_link);
-+
-+	void (*set_mst_bandwidth)(
-+		struct stream_encoder *enc,
-+		struct fixed31_32 avg_time_slots_per_mtp);
-+
-+	void (*update_hdmi_info_packets)(
-+		struct stream_encoder *enc,
-+		const struct encoder_info_frame *info_frame);
-+
-+	void (*stop_hdmi_info_packets)(
-+		struct stream_encoder *enc);
-+
-+	void (*update_dp_info_packets)(
-+		struct stream_encoder *enc,
-+		const struct encoder_info_frame *info_frame);
-+
-+	void (*stop_dp_info_packets)(
-+		struct stream_encoder *enc);
-+
-+	void (*dp_blank)(
-+		struct stream_encoder *enc);
-+
-+	void (*dp_unblank)(
-+		struct stream_encoder *enc,
-+		const struct encoder_unblank_param *param);
-+
-+	void (*audio_mute_control)(
-+		struct stream_encoder *enc, bool mute);
-+
-+	void (*dp_audio_setup)(
-+		struct stream_encoder *enc,
-+		unsigned int az_inst,
-+		struct audio_info *info);
-+
-+	void (*dp_audio_enable) (
-+			struct stream_encoder *enc);
-+
-+	void (*dp_audio_disable) (
-+			struct stream_encoder *enc);
-+
-+	void (*hdmi_audio_setup)(
-+		struct stream_encoder *enc,
-+		unsigned int az_inst,
-+		struct audio_info *info,
-+		struct audio_crtc_info *audio_crtc_info);
-+
-+	void (*hdmi_audio_disable) (
-+			struct stream_encoder *enc);
-+
-+	void (*setup_stereo_sync) (
-+			struct stream_encoder *enc,
-+			int tg_inst,
-+			bool enable);
-+
-+	void (*set_avmute)(
-+		struct stream_encoder *enc, bool enable);
-+};
-+
-+#endif /* STREAM_ENCODER_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h.0130~	2017-12-14 06:39:58.437903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h	2017-12-14 06:39:58.437903583 +0100
-@@ -0,0 +1,192 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
-+#define __DAL_TIMING_GENERATOR_TYPES_H__
-+
-+struct dc_bios;
-+
-+/* Contains CRTC vertical/horizontal pixel counters */
-+struct crtc_position {
-+	int32_t vertical_count;
-+	int32_t horizontal_count;
-+	int32_t nominal_vcount;
-+};
-+
-+struct dcp_gsl_params {
-+	int gsl_group;
-+	int gsl_master;
-+};
-+
-+/* define the structure of Dynamic Refresh Mode */
-+struct drr_params {
-+	uint32_t vertical_total_min;
-+	uint32_t vertical_total_max;
-+	bool immediate_flip;
-+};
-+
-+#define LEFT_EYE_3D_PRIMARY_SURFACE 1
-+#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
-+
-+enum test_pattern_dyn_range {
-+	TEST_PATTERN_DYN_RANGE_VESA = 0,
-+	TEST_PATTERN_DYN_RANGE_CEA
-+};
-+
-+enum test_pattern_mode {
-+	TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
-+	TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
-+	TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
-+	TEST_PATTERN_MODE_VERTICALBARS,
-+	TEST_PATTERN_MODE_HORIZONTALBARS,
-+	TEST_PATTERN_MODE_SINGLERAMP_RGB,
-+	TEST_PATTERN_MODE_DUALRAMP_RGB
-+};
-+
-+enum test_pattern_color_format {
-+	TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_8,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_10,
-+	TEST_PATTERN_COLOR_FORMAT_BPC_12
-+};
-+
-+enum controller_dp_test_pattern {
-+	CONTROLLER_DP_TEST_PATTERN_D102 = 0,
-+	CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
-+	CONTROLLER_DP_TEST_PATTERN_PRBS7,
-+	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
-+	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
-+	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
-+	CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
-+	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
-+	CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
-+	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
-+};
-+
-+enum crtc_state {
-+	CRTC_STATE_VBLANK = 0,
-+	CRTC_STATE_VACTIVE
-+};
-+
-+struct _dlg_otg_param {
-+	int vstartup_start;
-+	int vupdate_offset;
-+	int vupdate_width;
-+	int vready_offset;
-+	enum signal_type signal;
-+};
-+
-+struct crtc_stereo_flags {
-+	uint8_t PROGRAM_STEREO         : 1;
-+	uint8_t PROGRAM_POLARITY       : 1;
-+	uint8_t RIGHT_EYE_POLARITY     : 1;
-+	uint8_t FRAME_PACKED           : 1;
-+	uint8_t DISABLE_STEREO_DP_SYNC : 1;
-+};
-+
-+struct timing_generator {
-+	const struct timing_generator_funcs *funcs;
-+	struct dc_bios *bp;
-+	struct dc_context *ctx;
-+	struct _dlg_otg_param dlg_otg_param;
-+	int inst;
-+};
-+
-+struct dc_crtc_timing;
-+
-+struct drr_params;
-+
-+struct timing_generator_funcs {
-+	bool (*validate_timing)(struct timing_generator *tg,
-+							const struct dc_crtc_timing *timing);
-+	void (*program_timing)(struct timing_generator *tg,
-+							const struct dc_crtc_timing *timing,
-+							bool use_vbios);
-+	bool (*enable_crtc)(struct timing_generator *tg);
-+	bool (*disable_crtc)(struct timing_generator *tg);
-+	bool (*is_counter_moving)(struct timing_generator *tg);
-+	void (*get_position)(struct timing_generator *tg,
-+				struct crtc_position *position);
-+
-+	uint32_t (*get_frame_count)(struct timing_generator *tg);
-+	void (*get_scanoutpos)(
-+		struct timing_generator *tg,
-+		uint32_t *v_blank_start,
-+		uint32_t *v_blank_end,
-+		uint32_t *h_position,
-+		uint32_t *v_position);
-+	void (*set_early_control)(struct timing_generator *tg,
-+							   uint32_t early_cntl);
-+	void (*wait_for_state)(struct timing_generator *tg,
-+							enum crtc_state state);
-+	void (*set_blank)(struct timing_generator *tg,
-+					bool enable_blanking);
-+	bool (*is_blanked)(struct timing_generator *tg);
-+	void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color);
-+	void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color);
-+	void (*set_colors)(struct timing_generator *tg,
-+						const struct tg_color *blank_color,
-+						const struct tg_color *overscan_color);
-+
-+	void (*disable_vga)(struct timing_generator *tg);
-+	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
-+	void (*setup_global_swap_lock)(struct timing_generator *tg,
-+							const struct dcp_gsl_params *gsl_params);
-+	void (*unlock)(struct timing_generator *tg);
-+	void (*lock)(struct timing_generator *tg);
-+	void (*enable_reset_trigger)(struct timing_generator *tg,
-+				     int source_tg_inst);
-+	void (*enable_crtc_reset)(struct timing_generator *tg,
-+				  int source_tg_inst,
-+				  struct crtc_trigger_info *crtc_tp);
-+	void (*disable_reset_trigger)(struct timing_generator *tg);
-+	void (*tear_down_global_swap_lock)(struct timing_generator *tg);
-+	void (*enable_advanced_request)(struct timing_generator *tg,
-+					bool enable, const struct dc_crtc_timing *timing);
-+	void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
-+	void (*set_static_screen_control)(struct timing_generator *tg,
-+							uint32_t value);
-+	void (*set_test_pattern)(
-+		struct timing_generator *tg,
-+		enum controller_dp_test_pattern test_pattern,
-+		enum dc_color_depth color_depth);
-+
-+	bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);
-+
-+	void (*program_global_sync)(struct timing_generator *tg);
-+	void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
-+	void (*program_stereo)(struct timing_generator *tg,
-+		const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
-+	bool (*is_stereo_left_eye)(struct timing_generator *tg);
-+
-+	void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
-+
-+	void (*tg_init)(struct timing_generator *tg);
-+	bool (*is_tg_enabled)(struct timing_generator *tg);
-+};
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h.0130~	2017-12-14 06:39:58.438903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h	2017-12-14 06:39:58.438903583 +0100
-@@ -0,0 +1,313 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TRANSFORM_H__
-+#define __DAL_TRANSFORM_H__
-+
-+#include "hw_shared.h"
-+#include "dc_hw_types.h"
-+#include "fixed31_32.h"
-+
-+#define CSC_TEMPERATURE_MATRIX_SIZE 9
-+
-+struct bit_depth_reduction_params;
-+
-+struct transform {
-+	const struct transform_funcs *funcs;
-+	struct dc_context *ctx;
-+	int inst;
-+	struct dpp_caps *caps;
-+	struct pwl_params regamma_params;
-+};
-+
-+/* Colorimetry */
-+enum colorimetry {
-+	COLORIMETRY_NO_DATA = 0,
-+	COLORIMETRY_ITU601 = 1,
-+	COLORIMETRY_ITU709 = 2,
-+	COLORIMETRY_EXTENDED = 3
-+};
-+
-+enum colorimetry_ext {
-+	COLORIMETRYEX_XVYCC601 = 0,
-+	COLORIMETRYEX_XVYCC709 = 1,
-+	COLORIMETRYEX_SYCC601 = 2,
-+	COLORIMETRYEX_ADOBEYCC601 = 3,
-+	COLORIMETRYEX_ADOBERGB = 4,
-+	COLORIMETRYEX_BT2020YCC = 5,
-+	COLORIMETRYEX_BT2020RGBYCBCR = 6,
-+	COLORIMETRYEX_RESERVED = 7
-+};
-+
-+enum active_format_info {
-+	ACTIVE_FORMAT_NO_DATA = 0,
-+	ACTIVE_FORMAT_VALID = 1
-+};
-+
-+/* Active format aspect ratio */
-+enum active_format_aspect_ratio {
-+	ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE = 8,
-+	ACTIVE_FORMAT_ASPECT_RATIO_4_3 = 9,
-+	ACTIVE_FORMAT_ASPECT_RATIO_16_9 = 0XA,
-+	ACTIVE_FORMAT_ASPECT_RATIO_14_9 = 0XB
-+};
-+
-+enum bar_info {
-+	BAR_INFO_NOT_VALID = 0,
-+	BAR_INFO_VERTICAL_VALID = 1,
-+	BAR_INFO_HORIZONTAL_VALID = 2,
-+	BAR_INFO_BOTH_VALID = 3
-+};
-+
-+enum picture_scaling {
-+	PICTURE_SCALING_UNIFORM = 0,
-+	PICTURE_SCALING_HORIZONTAL = 1,
-+	PICTURE_SCALING_VERTICAL = 2,
-+	PICTURE_SCALING_BOTH = 3
-+};
-+
-+/* RGB quantization range */
-+enum rgb_quantization_range {
-+	RGB_QUANTIZATION_DEFAULT_RANGE = 0,
-+	RGB_QUANTIZATION_LIMITED_RANGE = 1,
-+	RGB_QUANTIZATION_FULL_RANGE = 2,
-+	RGB_QUANTIZATION_RESERVED = 3
-+};
-+
-+/* YYC quantization range */
-+enum yyc_quantization_range {
-+	YYC_QUANTIZATION_LIMITED_RANGE = 0,
-+	YYC_QUANTIZATION_FULL_RANGE = 1,
-+	YYC_QUANTIZATION_RESERVED2 = 2,
-+	YYC_QUANTIZATION_RESERVED3 = 3
-+};
-+
-+enum graphics_gamut_adjust_type {
-+	GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS = 0,
-+	GRAPHICS_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
-+	GRAPHICS_GAMUT_ADJUST_TYPE_SW /* use adjustments */
-+};
-+
-+enum lb_memory_config {
-+	/* Enable all 3 pieces of memory */
-+	LB_MEMORY_CONFIG_0 = 0,
-+
-+	/* Enable only the first piece of memory */
-+	LB_MEMORY_CONFIG_1 = 1,
-+
-+	/* Enable only the second piece of memory */
-+	LB_MEMORY_CONFIG_2 = 2,
-+
-+	/* Only applicable in 4:2:0 mode, enable all 3 pieces of memory and the
-+	 * last piece of chroma memory used for the luma storage
-+	 */
-+	LB_MEMORY_CONFIG_3 = 3
-+};
-+
-+struct xfm_grph_csc_adjustment {
-+	struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
-+	enum graphics_gamut_adjust_type gamut_adjust_type;
-+};
-+
-+struct overscan_info {
-+	int left;
-+	int right;
-+	int top;
-+	int bottom;
-+};
-+
-+struct scaling_ratios {
-+	struct fixed31_32 horz;
-+	struct fixed31_32 vert;
-+	struct fixed31_32 horz_c;
-+	struct fixed31_32 vert_c;
-+};
-+
-+struct sharpness_adj {
-+	int horz;
-+	int vert;
-+};
-+
-+struct line_buffer_params {
-+	bool alpha_en;
-+	bool pixel_expan_mode;
-+	bool interleave_en;
-+	int dynamic_pixel_depth;
-+	enum lb_pixel_depth depth;
-+};
-+
-+struct scl_inits {
-+	struct fixed31_32 h;
-+	struct fixed31_32 h_c;
-+	struct fixed31_32 v;
-+	struct fixed31_32 v_bot;
-+	struct fixed31_32 v_c;
-+	struct fixed31_32 v_c_bot;
-+};
-+
-+struct scaler_data {
-+	int h_active;
-+	int v_active;
-+	struct scaling_taps taps;
-+	struct rect viewport;
-+	struct rect viewport_c;
-+	struct rect recout;
-+	struct scaling_ratios ratios;
-+	struct scl_inits inits;
-+	struct sharpness_adj sharpness;
-+	enum pixel_format format;
-+	struct line_buffer_params lb_params;
-+};
-+
-+struct transform_funcs {
-+	void (*transform_reset)(struct transform *xfm);
-+
-+	void (*transform_set_scaler)(struct transform *xfm,
-+			const struct scaler_data *scl_data);
-+
-+	void (*transform_set_pixel_storage_depth)(
-+			struct transform *xfm,
-+			enum lb_pixel_depth depth,
-+			const struct bit_depth_reduction_params *bit_depth_params);
-+
-+	bool (*transform_get_optimal_number_of_taps)(
-+			struct transform *xfm,
-+			struct scaler_data *scl_data,
-+			const struct scaling_taps *in_taps);
-+
-+	void (*transform_set_gamut_remap)(
-+			struct transform *xfm,
-+			const struct xfm_grph_csc_adjustment *adjust);
-+
-+	void (*opp_set_csc_default)(
-+		struct transform *xfm,
-+		const struct default_adjustment *default_adjust);
-+
-+	void (*opp_set_csc_adjustment)(
-+		struct transform *xfm,
-+		const struct out_csc_color_matrix *tbl_entry);
-+
-+	void (*opp_power_on_regamma_lut)(
-+		struct transform *xfm,
-+		bool power_on);
-+
-+	void (*opp_program_regamma_lut)(
-+			struct transform *xfm,
-+			const struct pwl_result_data *rgb,
-+			uint32_t num);
-+
-+	void (*opp_configure_regamma_lut)(
-+			struct transform *xfm,
-+			bool is_ram_a);
-+
-+	void (*opp_program_regamma_lutb_settings)(
-+			struct transform *xfm,
-+			const struct pwl_params *params);
-+
-+	void (*opp_program_regamma_luta_settings)(
-+			struct transform *xfm,
-+			const struct pwl_params *params);
-+
-+	void (*opp_program_regamma_pwl)(
-+		struct transform *xfm, const struct pwl_params *params);
-+
-+	void (*opp_set_regamma_mode)(
-+			struct transform *xfm_base,
-+			enum opp_regamma mode);
-+
-+	void (*ipp_set_degamma)(
-+			struct transform *xfm_base,
-+			enum ipp_degamma_mode mode);
-+
-+	void (*ipp_program_input_lut)(
-+			struct transform *xfm_base,
-+			const struct dc_gamma *gamma);
-+
-+	void (*ipp_program_degamma_pwl)(struct transform *xfm_base,
-+									 const struct pwl_params *params);
-+
-+	void (*ipp_setup)(
-+			struct transform *xfm_base,
-+			enum surface_pixel_format format,
-+			enum expansion_mode mode,
-+			struct csc_transform input_csc_color_matrix,
-+			enum dc_color_space input_color_space);
-+
-+	void (*ipp_full_bypass)(struct transform *xfm_base);
-+
-+	void (*set_cursor_attributes)(
-+			struct transform *xfm_base,
-+			const struct dc_cursor_attributes *attr);
-+
-+	void (*set_cursor_position)(
-+			struct transform *xfm_base,
-+			const struct dc_cursor_position *pos,
-+			const struct dc_cursor_mi_param *param,
-+			uint32_t width
-+			);
-+
-+};
-+
-+const uint16_t *get_filter_2tap_16p(void);
-+const uint16_t *get_filter_2tap_64p(void);
-+const uint16_t *get_filter_3tap_16p(struct fixed31_32 ratio);
-+const uint16_t *get_filter_3tap_64p(struct fixed31_32 ratio);
-+const uint16_t *get_filter_4tap_16p(struct fixed31_32 ratio);
-+const uint16_t *get_filter_4tap_64p(struct fixed31_32 ratio);
-+const uint16_t *get_filter_5tap_64p(struct fixed31_32 ratio);
-+const uint16_t *get_filter_6tap_64p(struct fixed31_32 ratio);
-+const uint16_t *get_filter_7tap_64p(struct fixed31_32 ratio);
-+const uint16_t *get_filter_8tap_64p(struct fixed31_32 ratio);
-+
-+
-+/* Defines the pixel processing capability of the DSCL */
-+enum dscl_data_processing_format {
-+	DSCL_DATA_PRCESSING_FIXED_FORMAT,	/* The DSCL processes pixel data in fixed format */
-+	DSCL_DATA_PRCESSING_FLOAT_FORMAT,	/* The DSCL processes pixel data in float format */
-+};
-+
-+/*
-+ * The DPP capabilities structure contains enumerations to specify the
-+ * HW processing features and an associated function pointers to
-+ * provide the function interface that can be overloaded for implementations
-+ * based on different capabilities
-+ */
-+struct dpp_caps {
-+	/* DSCL processing pixel data in fixed or float format */
-+	enum dscl_data_processing_format dscl_data_proc_format;
-+
-+	/* Calculates the number of partitions in the line buffer.
-+	 * The implementation of this function is overloaded for
-+	 * different versions of DSCL LB.
-+	 */
-+	void (*dscl_calc_lb_num_partitions)(
-+			const struct scaler_data *scl_data,
-+			enum lb_memory_config lb_config,
-+			int *num_part_y,
-+			int *num_part_c);
-+};
-+
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h.0130~	2017-12-14 06:39:58.438903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h	2017-12-14 06:39:58.438903583 +0100
-@@ -0,0 +1,79 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_LINK_HWSS_H__
-+#define __DC_LINK_HWSS_H__
-+
-+#include "inc/core_status.h"
-+
-+enum dc_status core_link_read_dpcd(
-+	struct dc_link *link,
-+	uint32_t address,
-+	uint8_t *data,
-+	uint32_t size);
-+
-+enum dc_status core_link_write_dpcd(
-+	struct dc_link *link,
-+	uint32_t address,
-+	const uint8_t *data,
-+	uint32_t size);
-+
-+struct gpio *get_hpd_gpio(struct dc_bios *dcb,
-+		struct graphics_object_id link_id,
-+		struct gpio_service *gpio_service);
-+
-+void dp_enable_link_phy(
-+	struct dc_link *link,
-+	enum signal_type signal,
-+	enum clock_source_id clock_source,
-+	const struct dc_link_settings *link_settings);
-+
-+void dp_receiver_power_ctrl(struct dc_link *link, bool on);
-+
-+void dp_disable_link_phy(struct dc_link *link, enum signal_type signal);
-+
-+void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal);
-+
-+bool dp_set_hw_training_pattern(
-+	struct dc_link *link,
-+	enum hw_dp_training_pattern pattern);
-+
-+void dp_set_hw_lane_settings(
-+	struct dc_link *link,
-+	const struct link_training_settings *link_settings);
-+
-+void dp_set_hw_test_pattern(
-+	struct dc_link *link,
-+	enum dp_test_pattern test_pattern,
-+	uint8_t *custom_pattern,
-+	uint32_t custom_pattern_size);
-+
-+enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
-+
-+void dp_retrain_link_dp_test(struct dc_link *link,
-+		struct dc_link_settings *link_setting,
-+		bool skip_video_pattern);
-+
-+#endif /* __DC_LINK_HWSS_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h.0130~	2017-12-14 06:39:58.438903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h	2017-12-14 06:39:58.438903583 +0100
-@@ -0,0 +1,392 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ */
-+
-+#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_
-+#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_
-+
-+#include "dm_services.h"
-+
-+/* macro for register read/write
-+ * user of macro need to define
-+ *
-+ * CTX ==> macro to ptr to dc_context
-+ *    eg. aud110->base.ctx
-+ *
-+ * REG ==> macro to location of register offset
-+ *    eg. aud110->regs->reg
-+ */
-+#define REG_READ(reg_name) \
-+		dm_read_reg(CTX, REG(reg_name))
-+
-+#define REG_WRITE(reg_name, value) \
-+		dm_write_reg(CTX, REG(reg_name), value)
-+
-+#ifdef REG_SET
-+#undef REG_SET
-+#endif
-+
-+#ifdef REG_GET
-+#undef REG_GET
-+#endif
-+
-+/* macro to set register fields. */
-+#define REG_SET_N(reg_name, n, initial_val, ...)	\
-+		generic_reg_update_ex(CTX, \
-+				REG(reg_name), \
-+				initial_val, \
-+				n, __VA_ARGS__)
-+
-+#define FN(reg_name, field) \
-+	FD(reg_name##__##field)
-+
-+#define REG_SET(reg_name, initial_val, field, val)	\
-+		REG_SET_N(reg_name, 1, initial_val, \
-+				FN(reg_name, field), val)
-+
-+#define REG_SET_2(reg, init_value, f1, v1, f2, v2)	\
-+		REG_SET_N(reg, 2, init_value, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2)
-+
-+#define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3)	\
-+		REG_SET_N(reg, 3, init_value, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2,\
-+				FN(reg, f3), v3)
-+
-+#define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4)	\
-+		REG_SET_N(reg, 4, init_value, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2,\
-+				FN(reg, f3), v3,\
-+				FN(reg, f4), v4)
-+
-+#define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4,	\
-+		f5, v5)	\
-+		REG_SET_N(reg, 5, init_value, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2,\
-+				FN(reg, f3), v3,\
-+				FN(reg, f4), v4,\
-+				FN(reg, f5), v5)
-+
-+#define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4,	\
-+		f5, v5, f6, v6)	\
-+		REG_SET_N(reg, 6, init_value, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2,\
-+				FN(reg, f3), v3,\
-+				FN(reg, f4), v4,\
-+				FN(reg, f5), v5,\
-+				FN(reg, f6), v6)
-+
-+#define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4,	\
-+		f5, v5, f6, v6, f7, v7)	\
-+		REG_SET_N(reg, 7, init_value, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2,\
-+				FN(reg, f3), v3,\
-+				FN(reg, f4), v4,\
-+				FN(reg, f5), v5,\
-+				FN(reg, f6), v6,\
-+				FN(reg, f7), v7)
-+
-+#define REG_SET_8(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4,	\
-+		f5, v5, f6, v6, f7, v7, f8, v8)	\
-+		REG_SET_N(reg, 8, init_value, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2,\
-+				FN(reg, f3), v3,\
-+				FN(reg, f4), v4,\
-+				FN(reg, f5), v5,\
-+				FN(reg, f6), v6,\
-+				FN(reg, f7), v7,\
-+				FN(reg, f8), v8)
-+
-+#define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \
-+		v5, f6, v6, f7, v7, f8, v8, f9, v9)	\
-+		REG_SET_N(reg, 9, init_value, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2, \
-+				FN(reg, f3), v3, \
-+				FN(reg, f4), v4, \
-+				FN(reg, f5), v5, \
-+				FN(reg, f6), v6, \
-+				FN(reg, f7), v7, \
-+				FN(reg, f8), v8, \
-+				FN(reg, f9), v9)
-+
-+#define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \
-+		v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)	\
-+		REG_SET_N(reg, 10, init_value, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2, \
-+				FN(reg, f3), v3, \
-+				FN(reg, f4), v4, \
-+				FN(reg, f5), v5, \
-+				FN(reg, f6), v6, \
-+				FN(reg, f7), v7, \
-+				FN(reg, f8), v8, \
-+				FN(reg, f9), v9, \
-+				FN(reg, f10), v10)
-+
-+/* macro to get register fields
-+ * read given register and fill in field value in output parameter */
-+#define REG_GET(reg_name, field, val)	\
-+		generic_reg_get(CTX, REG(reg_name), \
-+				FN(reg_name, field), val)
-+
-+#define REG_GET_2(reg_name, f1, v1, f2, v2)	\
-+		generic_reg_get2(CTX, REG(reg_name), \
-+				FN(reg_name, f1), v1, \
-+				FN(reg_name, f2), v2)
-+
-+#define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3)	\
-+		generic_reg_get3(CTX, REG(reg_name), \
-+				FN(reg_name, f1), v1, \
-+				FN(reg_name, f2), v2, \
-+				FN(reg_name, f3), v3)
-+
-+#define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4)	\
-+		generic_reg_get4(CTX, REG(reg_name), \
-+				FN(reg_name, f1), v1, \
-+				FN(reg_name, f2), v2, \
-+				FN(reg_name, f3), v3, \
-+				FN(reg_name, f4), v4)
-+
-+#define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)	\
-+		generic_reg_get5(CTX, REG(reg_name), \
-+				FN(reg_name, f1), v1, \
-+				FN(reg_name, f2), v2, \
-+				FN(reg_name, f3), v3, \
-+				FN(reg_name, f4), v4, \
-+				FN(reg_name, f5), v5)
-+
-+/* macro to poll and wait for a register field to read back given value */
-+
-+#define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try)	\
-+		generic_reg_wait(CTX, \
-+				REG(reg_name), FN(reg_name, field), val,\
-+				delay_between_poll_us, max_try, __func__, __LINE__)
-+
-+/* macro to update (read, modify, write) register fields
-+ */
-+#define REG_UPDATE_N(reg_name, n, ...)	\
-+		generic_reg_update_ex(CTX, \
-+				REG(reg_name), \
-+				REG_READ(reg_name), \
-+				n, __VA_ARGS__)
-+
-+#define REG_UPDATE(reg_name, field, val)	\
-+		REG_UPDATE_N(reg_name, 1, \
-+				FN(reg_name, field), val)
-+
-+#define REG_UPDATE_2(reg, f1, v1, f2, v2)	\
-+		REG_UPDATE_N(reg, 2,\
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2)
-+
-+#define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3)	\
-+		REG_UPDATE_N(reg, 3, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2, \
-+				FN(reg, f3), v3)
-+
-+#define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4)	\
-+		REG_UPDATE_N(reg, 4, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2, \
-+				FN(reg, f3), v3, \
-+				FN(reg, f4), v4)
-+
-+#define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)	\
-+		REG_UPDATE_N(reg, 5, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2, \
-+				FN(reg, f3), v3, \
-+				FN(reg, f4), v4, \
-+				FN(reg, f5), v5)
-+
-+#define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)	\
-+		REG_UPDATE_N(reg, 6, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2, \
-+				FN(reg, f3), v3, \
-+				FN(reg, f4), v4, \
-+				FN(reg, f5), v5, \
-+				FN(reg, f6), v6)
-+
-+#define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)	\
-+		REG_UPDATE_N(reg, 7, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2, \
-+				FN(reg, f3), v3, \
-+				FN(reg, f4), v4, \
-+				FN(reg, f5), v5, \
-+				FN(reg, f6), v6, \
-+				FN(reg, f7), v7)
-+
-+#define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)	\
-+		REG_UPDATE_N(reg, 8, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2, \
-+				FN(reg, f3), v3, \
-+				FN(reg, f4), v4, \
-+				FN(reg, f5), v5, \
-+				FN(reg, f6), v6, \
-+				FN(reg, f7), v7, \
-+				FN(reg, f8), v8)
-+
-+#define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9)	\
-+		REG_UPDATE_N(reg, 9, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2, \
-+				FN(reg, f3), v3, \
-+				FN(reg, f4), v4, \
-+				FN(reg, f5), v5, \
-+				FN(reg, f6), v6, \
-+				FN(reg, f7), v7, \
-+				FN(reg, f8), v8, \
-+				FN(reg, f9), v9)
-+
-+#define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\
-+		REG_UPDATE_N(reg, 10, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2, \
-+				FN(reg, f3), v3, \
-+				FN(reg, f4), v4, \
-+				FN(reg, f5), v5, \
-+				FN(reg, f6), v6, \
-+				FN(reg, f7), v7, \
-+				FN(reg, f8), v8, \
-+				FN(reg, f9), v9, \
-+				FN(reg, f10), v10)
-+
-+#define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
-+		v10, f11, v11, f12, v12, f13, v13, f14, v14)\
-+		REG_UPDATE_N(reg, 14, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2, \
-+				FN(reg, f3), v3, \
-+				FN(reg, f4), v4, \
-+				FN(reg, f5), v5, \
-+				FN(reg, f6), v6, \
-+				FN(reg, f7), v7, \
-+				FN(reg, f8), v8, \
-+				FN(reg, f9), v9, \
-+				FN(reg, f10), v10, \
-+				FN(reg, f11), v11, \
-+				FN(reg, f12), v12, \
-+				FN(reg, f13), v13, \
-+				FN(reg, f14), v14)
-+
-+#define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
-+		v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19)\
-+		REG_UPDATE_N(reg, 19, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2, \
-+				FN(reg, f3), v3, \
-+				FN(reg, f4), v4, \
-+				FN(reg, f5), v5, \
-+				FN(reg, f6), v6, \
-+				FN(reg, f7), v7, \
-+				FN(reg, f8), v8, \
-+				FN(reg, f9), v9, \
-+				FN(reg, f10), v10, \
-+				FN(reg, f11), v11, \
-+				FN(reg, f12), v12, \
-+				FN(reg, f13), v13, \
-+				FN(reg, f14), v14, \
-+				FN(reg, f15), v15, \
-+				FN(reg, f16), v16, \
-+				FN(reg, f17), v17, \
-+				FN(reg, f18), v18, \
-+				FN(reg, f19), v19)
-+
-+#define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
-+		v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19, f20, v20)\
-+		REG_UPDATE_N(reg, 20, \
-+				FN(reg, f1), v1,\
-+				FN(reg, f2), v2, \
-+				FN(reg, f3), v3, \
-+				FN(reg, f4), v4, \
-+				FN(reg, f5), v5, \
-+				FN(reg, f6), v6, \
-+				FN(reg, f7), v7, \
-+				FN(reg, f8), v8, \
-+				FN(reg, f9), v9, \
-+				FN(reg, f10), v10, \
-+				FN(reg, f11), v11, \
-+				FN(reg, f12), v12, \
-+				FN(reg, f13), v13, \
-+				FN(reg, f14), v14, \
-+				FN(reg, f15), v15, \
-+				FN(reg, f16), v16, \
-+				FN(reg, f17), v17, \
-+				FN(reg, f18), v18, \
-+				FN(reg, f19), v19, \
-+				FN(reg, f20), v20)
-+/* macro to update a register field to specified values in given sequences.
-+ * useful when toggling bits
-+ */
-+#define REG_UPDATE_SEQ(reg, field, value1, value2) \
-+{	uint32_t val = REG_UPDATE(reg, field, value1); \
-+	REG_SET(reg, val, field, value2); }
-+
-+/* macro to update fields in register 1 field at a time in given order */
-+#define REG_UPDATE_1BY1_2(reg, f1, v1, f2, v2) \
-+{	uint32_t val = REG_UPDATE(reg, f1, v1); \
-+	REG_SET(reg, val, f2, v2); }
-+
-+#define REG_UPDATE_1BY1_3(reg, f1, v1, f2, v2, f3, v3) \
-+{	uint32_t val = REG_UPDATE(reg, f1, v1); \
-+	val = REG_SET(reg, val, f2, v2); \
-+	REG_SET(reg, val, f3, v3); }
-+
-+uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,
-+		uint8_t shift, uint32_t mask, uint32_t *field_value);
-+
-+uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,
-+		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
-+		uint8_t shift2, uint32_t mask2, uint32_t *field_value2);
-+
-+uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
-+		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
-+		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
-+		uint8_t shift3, uint32_t mask3, uint32_t *field_value3);
-+
-+uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr,
-+		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
-+		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
-+		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
-+		uint8_t shift4, uint32_t mask4, uint32_t *field_value4);
-+
-+uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
-+		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
-+		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
-+		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
-+		uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
-+		uint8_t shift5, uint32_t mask5, uint32_t *field_value5);
-+
-+#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/inc/resource.h.0130~	2017-12-14 06:39:58.438903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/inc/resource.h	2017-12-14 06:39:58.438903583 +0100
-@@ -0,0 +1,172 @@
-+/*
-+ * Copyright 2015 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ */
-+
-+#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_
-+#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_
-+
-+#include "core_types.h"
-+#include "core_status.h"
-+#include "dal_asic_id.h"
-+#include "dm_pp_smu.h"
-+
-+/* TODO unhardcode, 4 for CZ*/
-+#define MEMORY_TYPE_MULTIPLIER 4
-+
-+enum dce_version resource_parse_asic_id(
-+		struct hw_asic_id asic_id);
-+
-+struct resource_caps {
-+	int num_timing_generator;
-+	int num_video_plane;
-+	int num_audio;
-+	int num_stream_encoder;
-+	int num_pll;
-+	int num_dwb;
-+};
-+
-+struct resource_straps {
-+	uint32_t hdmi_disable;
-+	uint32_t dc_pinstraps_audio;
-+	uint32_t audio_stream_number;
-+};
-+
-+struct resource_create_funcs {
-+	void (*read_dce_straps)(
-+			struct dc_context *ctx, struct resource_straps *straps);
-+
-+	struct audio *(*create_audio)(
-+			struct dc_context *ctx, unsigned int inst);
-+
-+	struct stream_encoder *(*create_stream_encoder)(
-+			enum engine_id eng_id, struct dc_context *ctx);
-+
-+	struct dce_hwseq *(*create_hwseq)(
-+			struct dc_context *ctx);
-+};
-+
-+bool resource_construct(
-+	unsigned int num_virtual_links,
-+	struct dc *dc,
-+	struct resource_pool *pool,
-+	const struct resource_create_funcs *create_funcs);
-+
-+struct resource_pool *dc_create_resource_pool(
-+				struct dc *dc,
-+				int num_virtual_links,
-+				enum dce_version dc_version,
-+				struct hw_asic_id asic_id);
-+
-+void dc_destroy_resource_pool(struct dc *dc);
-+
-+enum dc_status resource_map_pool_resources(
-+		const struct dc *dc,
-+		struct dc_state *context,
-+		struct dc_stream_state *stream);
-+
-+bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);
-+
-+enum dc_status resource_build_scaling_params_for_context(
-+		const struct dc *dc,
-+		struct dc_state *context);
-+
-+void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
-+
-+void resource_unreference_clock_source(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool,
-+		struct clock_source *clock_source);
-+
-+void resource_reference_clock_source(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool,
-+		struct clock_source *clock_source);
-+
-+bool resource_are_streams_timing_synchronizable(
-+		struct dc_stream_state *stream1,
-+		struct dc_stream_state *stream2);
-+
-+struct clock_source *resource_find_used_clk_src_for_sharing(
-+		struct resource_context *res_ctx,
-+		struct pipe_ctx *pipe_ctx);
-+
-+struct clock_source *dc_resource_find_first_free_pll(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool);
-+
-+struct pipe_ctx *resource_get_head_pipe_for_stream(
-+		struct resource_context *res_ctx,
-+		struct dc_stream_state *stream);
-+
-+bool resource_attach_surfaces_to_context(
-+		struct dc_plane_state *const *plane_state,
-+		int surface_count,
-+		struct dc_stream_state *dc_stream,
-+		struct dc_state *context,
-+		const struct resource_pool *pool);
-+
-+struct pipe_ctx *find_idle_secondary_pipe(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool);
-+
-+bool resource_is_stream_unchanged(
-+	struct dc_state *old_context, struct dc_stream_state *stream);
-+
-+bool resource_validate_attach_surfaces(
-+		const struct dc_validation_set set[],
-+		int set_count,
-+		const struct dc_state *old_context,
-+		struct dc_state *context,
-+		const struct resource_pool *pool);
-+
-+void validate_guaranteed_copy_streams(
-+		struct dc_state *context,
-+		int max_streams);
-+
-+void resource_validate_ctx_update_pointer_after_copy(
-+		const struct dc_state *src_ctx,
-+		struct dc_state *dst_ctx);
-+
-+enum dc_status resource_map_clock_resources(
-+		const struct dc *dc,
-+		struct dc_state *context,
-+		struct dc_stream_state *stream);
-+
-+enum dc_status resource_map_phy_clock_resources(
-+		const struct dc *dc,
-+		struct dc_state *context,
-+		struct dc_stream_state *stream);
-+
-+bool pipe_need_reprogram(
-+		struct pipe_ctx *pipe_ctx_old,
-+		struct pipe_ctx *pipe_ctx);
-+
-+void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
-+		struct bit_depth_reduction_params *fmt_bit_depth);
-+
-+void update_audio_usage(
-+		struct resource_context *res_ctx,
-+		const struct resource_pool *pool,
-+		struct audio *audio,
-+		bool acquired);
-+#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c.0130~	2017-12-14 06:39:58.438903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c	2017-12-14 06:39:58.438903583 +0100
-@@ -0,0 +1,430 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "irq_service_dce110.h"
-+
-+#include "dce/dce_11_0_d.h"
-+#include "dce/dce_11_0_sh_mask.h"
-+
-+#include "ivsrcid/ivsrcid_vislands30.h"
-+
-+#include "dc.h"
-+#include "core_types.h"
-+static bool hpd_ack(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info)
-+{
-+	uint32_t addr = info->status_reg;
-+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
-+	uint32_t current_status =
-+		get_reg_field_value(
-+			value,
-+			DC_HPD_INT_STATUS,
-+			DC_HPD_SENSE_DELAYED);
-+
-+	dal_irq_service_ack_generic(irq_service, info);
-+
-+	value = dm_read_reg(irq_service->ctx, info->enable_reg);
-+
-+	set_reg_field_value(
-+		value,
-+		current_status ? 0 : 1,
-+		DC_HPD_INT_CONTROL,
-+		DC_HPD_INT_POLARITY);
-+
-+	dm_write_reg(irq_service->ctx, info->enable_reg, value);
-+
-+	return true;
-+}
-+
-+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = hpd_ack
-+};
-+
-+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = NULL
-+};
-+
-+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = NULL
-+};
-+
-+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
-+	.set = dce110_vblank_set,
-+	.ack = NULL
-+};
-+
-+#define hpd_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
-+		.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
-+		.enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
-+		.enable_value = {\
-+			DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
-+			~DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK\
-+		},\
-+		.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
-+		.ack_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
-+		.ack_value = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
-+		.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
-+		.funcs = &hpd_irq_info_funcs\
-+	}
-+
-+#define hpd_rx_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
-+		.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
-+		.enable_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
-+		.enable_value = {\
-+			DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
-+			~DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK },\
-+		.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
-+		.ack_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
-+		.ack_value = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
-+		.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
-+		.funcs = &hpd_rx_irq_info_funcs\
-+	}
-+#define pflip_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
-+		.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
-+		.enable_mask =\
-+		GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
-+		.enable_value = {\
-+			GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
-+			~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
-+		.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
-+		.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
-+		.ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
-+		.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
-+		.funcs = &pflip_irq_info_funcs\
-+	}
-+
-+#define vupdate_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
-+		.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
-+		.enable_mask =\
-+		CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
-+		.enable_value = {\
-+			CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
-+			~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
-+		.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
-+		.ack_mask =\
-+		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
-+		.ack_value =\
-+		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
-+		.funcs = &vblank_irq_info_funcs\
-+	}
-+
-+#define vblank_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
-+		.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
-+		.enable_mask =\
-+		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
-+		.enable_value = {\
-+			CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
-+			~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
-+		.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
-+		.ack_mask =\
-+		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
-+		.ack_value =\
-+		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
-+		.funcs = &vblank_irq_info_funcs,\
-+		.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
-+	}
-+
-+#define dummy_irq_entry() \
-+	{\
-+		.funcs = &dummy_irq_info_funcs\
-+	}
-+
-+#define i2c_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
-+
-+#define dp_sink_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
-+
-+#define gpio_pad_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
-+
-+#define dc_underflow_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
-+
-+bool dal_irq_service_dummy_set(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info,
-+	bool enable)
-+{
-+	dm_logger_write(
-+		irq_service->ctx->logger, LOG_ERROR,
-+		"%s: called for non-implemented irq source\n",
-+		__func__);
-+	return false;
-+}
-+
-+bool dal_irq_service_dummy_ack(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info)
-+{
-+	dm_logger_write(
-+		irq_service->ctx->logger, LOG_ERROR,
-+		"%s: called for non-implemented irq source\n",
-+		__func__);
-+	return false;
-+}
-+
-+
-+bool dce110_vblank_set(
-+		struct irq_service *irq_service,
-+		const struct irq_source_info *info,
-+		bool enable)
-+{
-+	struct dc_context *dc_ctx = irq_service->ctx;
-+	struct dc *core_dc = irq_service->ctx->dc;
-+	enum dc_irq_source dal_irq_src = dc_interrupt_to_irq_source(
-+										irq_service->ctx->dc,
-+										info->src_id,
-+										info->ext_id);
-+	uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
-+
-+	struct timing_generator *tg =
-+			core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
-+
-+	if (enable) {
-+		if (!tg->funcs->arm_vert_intr(tg, 2)) {
-+			DC_ERROR("Failed to get VBLANK!\n");
-+			return false;
-+		}
-+	}
-+
-+	dal_irq_service_set_generic(irq_service, info, enable);
-+	return true;
-+
-+}
-+
-+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
-+	.set = dal_irq_service_dummy_set,
-+	.ack = dal_irq_service_dummy_ack
-+};
-+
-+static const struct irq_source_info
-+irq_source_info_dce110[DAL_IRQ_SOURCES_NUMBER] = {
-+	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
-+	hpd_int_entry(0),
-+	hpd_int_entry(1),
-+	hpd_int_entry(2),
-+	hpd_int_entry(3),
-+	hpd_int_entry(4),
-+	hpd_int_entry(5),
-+	hpd_rx_int_entry(0),
-+	hpd_rx_int_entry(1),
-+	hpd_rx_int_entry(2),
-+	hpd_rx_int_entry(3),
-+	hpd_rx_int_entry(4),
-+	hpd_rx_int_entry(5),
-+	i2c_int_entry(1),
-+	i2c_int_entry(2),
-+	i2c_int_entry(3),
-+	i2c_int_entry(4),
-+	i2c_int_entry(5),
-+	i2c_int_entry(6),
-+	dp_sink_int_entry(1),
-+	dp_sink_int_entry(2),
-+	dp_sink_int_entry(3),
-+	dp_sink_int_entry(4),
-+	dp_sink_int_entry(5),
-+	dp_sink_int_entry(6),
-+	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
-+	pflip_int_entry(0),
-+	pflip_int_entry(1),
-+	pflip_int_entry(2),
-+	pflip_int_entry(3),
-+	pflip_int_entry(4),
-+	pflip_int_entry(5),
-+	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
-+	gpio_pad_int_entry(0),
-+	gpio_pad_int_entry(1),
-+	gpio_pad_int_entry(2),
-+	gpio_pad_int_entry(3),
-+	gpio_pad_int_entry(4),
-+	gpio_pad_int_entry(5),
-+	gpio_pad_int_entry(6),
-+	gpio_pad_int_entry(7),
-+	gpio_pad_int_entry(8),
-+	gpio_pad_int_entry(9),
-+	gpio_pad_int_entry(10),
-+	gpio_pad_int_entry(11),
-+	gpio_pad_int_entry(12),
-+	gpio_pad_int_entry(13),
-+	gpio_pad_int_entry(14),
-+	gpio_pad_int_entry(15),
-+	gpio_pad_int_entry(16),
-+	gpio_pad_int_entry(17),
-+	gpio_pad_int_entry(18),
-+	gpio_pad_int_entry(19),
-+	gpio_pad_int_entry(20),
-+	gpio_pad_int_entry(21),
-+	gpio_pad_int_entry(22),
-+	gpio_pad_int_entry(23),
-+	gpio_pad_int_entry(24),
-+	gpio_pad_int_entry(25),
-+	gpio_pad_int_entry(26),
-+	gpio_pad_int_entry(27),
-+	gpio_pad_int_entry(28),
-+	gpio_pad_int_entry(29),
-+	gpio_pad_int_entry(30),
-+	dc_underflow_int_entry(1),
-+	dc_underflow_int_entry(2),
-+	dc_underflow_int_entry(3),
-+	dc_underflow_int_entry(4),
-+	dc_underflow_int_entry(5),
-+	dc_underflow_int_entry(6),
-+	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
-+	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
-+	vupdate_int_entry(0),
-+	vupdate_int_entry(1),
-+	vupdate_int_entry(2),
-+	vupdate_int_entry(3),
-+	vupdate_int_entry(4),
-+	vupdate_int_entry(5),
-+	vblank_int_entry(0),
-+	vblank_int_entry(1),
-+	vblank_int_entry(2),
-+	vblank_int_entry(3),
-+	vblank_int_entry(4),
-+	vblank_int_entry(5),
-+
-+};
-+
-+enum dc_irq_source to_dal_irq_source_dce110(
-+		struct irq_service *irq_service,
-+		uint32_t src_id,
-+		uint32_t ext_id)
-+{
-+	switch (src_id) {
-+	case VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0:
-+		return DC_IRQ_SOURCE_VBLANK1;
-+	case VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0:
-+		return DC_IRQ_SOURCE_VBLANK2;
-+	case VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0:
-+		return DC_IRQ_SOURCE_VBLANK3;
-+	case VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0:
-+		return DC_IRQ_SOURCE_VBLANK4;
-+	case VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0:
-+		return DC_IRQ_SOURCE_VBLANK5;
-+	case VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0:
-+		return DC_IRQ_SOURCE_VBLANK6;
-+	case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT:
-+		return DC_IRQ_SOURCE_VUPDATE1;
-+	case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT:
-+		return DC_IRQ_SOURCE_VUPDATE2;
-+	case VISLANDS30_IV_SRCID_D3_V_UPDATE_INT:
-+		return DC_IRQ_SOURCE_VUPDATE3;
-+	case VISLANDS30_IV_SRCID_D4_V_UPDATE_INT:
-+		return DC_IRQ_SOURCE_VUPDATE4;
-+	case VISLANDS30_IV_SRCID_D5_V_UPDATE_INT:
-+		return DC_IRQ_SOURCE_VUPDATE5;
-+	case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT:
-+		return DC_IRQ_SOURCE_VUPDATE6;
-+	case VISLANDS30_IV_SRCID_D1_GRPH_PFLIP:
-+		return DC_IRQ_SOURCE_PFLIP1;
-+	case VISLANDS30_IV_SRCID_D2_GRPH_PFLIP:
-+		return DC_IRQ_SOURCE_PFLIP2;
-+	case VISLANDS30_IV_SRCID_D3_GRPH_PFLIP:
-+		return DC_IRQ_SOURCE_PFLIP3;
-+	case VISLANDS30_IV_SRCID_D4_GRPH_PFLIP:
-+		return DC_IRQ_SOURCE_PFLIP4;
-+	case VISLANDS30_IV_SRCID_D5_GRPH_PFLIP:
-+		return DC_IRQ_SOURCE_PFLIP5;
-+	case VISLANDS30_IV_SRCID_D6_GRPH_PFLIP:
-+		return DC_IRQ_SOURCE_PFLIP6;
-+
-+	case VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A:
-+		/* generic src_id for all HPD and HPDRX interrupts */
-+		switch (ext_id) {
-+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A:
-+			return DC_IRQ_SOURCE_HPD1;
-+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B:
-+			return DC_IRQ_SOURCE_HPD2;
-+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C:
-+			return DC_IRQ_SOURCE_HPD3;
-+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D:
-+			return DC_IRQ_SOURCE_HPD4;
-+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E:
-+			return DC_IRQ_SOURCE_HPD5;
-+		case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F:
-+			return DC_IRQ_SOURCE_HPD6;
-+		case VISLANDS30_IV_EXTID_HPD_RX_A:
-+			return DC_IRQ_SOURCE_HPD1RX;
-+		case VISLANDS30_IV_EXTID_HPD_RX_B:
-+			return DC_IRQ_SOURCE_HPD2RX;
-+		case VISLANDS30_IV_EXTID_HPD_RX_C:
-+			return DC_IRQ_SOURCE_HPD3RX;
-+		case VISLANDS30_IV_EXTID_HPD_RX_D:
-+			return DC_IRQ_SOURCE_HPD4RX;
-+		case VISLANDS30_IV_EXTID_HPD_RX_E:
-+			return DC_IRQ_SOURCE_HPD5RX;
-+		case VISLANDS30_IV_EXTID_HPD_RX_F:
-+			return DC_IRQ_SOURCE_HPD6RX;
-+		default:
-+			return DC_IRQ_SOURCE_INVALID;
-+		}
-+		break;
-+
-+	default:
-+		return DC_IRQ_SOURCE_INVALID;
-+	}
-+}
-+
-+static const struct irq_service_funcs irq_service_funcs_dce110 = {
-+		.to_dal_irq_source = to_dal_irq_source_dce110
-+};
-+
-+static void construct(
-+	struct irq_service *irq_service,
-+	struct irq_service_init_data *init_data)
-+{
-+	dal_irq_service_construct(irq_service, init_data);
-+
-+	irq_service->info = irq_source_info_dce110;
-+	irq_service->funcs = &irq_service_funcs_dce110;
-+}
-+
-+struct irq_service *dal_irq_service_dce110_create(
-+	struct irq_service_init_data *init_data)
-+{
-+	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
-+						  GFP_KERNEL);
-+
-+	if (!irq_service)
-+		return NULL;
-+
-+	construct(irq_service, init_data);
-+	return irq_service;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.h.0130~	2017-12-14 06:39:58.438903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.h	2017-12-14 06:39:58.438903583 +0100
-@@ -0,0 +1,53 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IRQ_SERVICE_DCE110_H__
-+#define __DAL_IRQ_SERVICE_DCE110_H__
-+
-+#include "../irq_service.h"
-+
-+struct irq_service *dal_irq_service_dce110_create(
-+	struct irq_service_init_data *init_data);
-+
-+enum dc_irq_source to_dal_irq_source_dce110(
-+		struct irq_service *irq_service,
-+		uint32_t src_id,
-+		uint32_t ext_id);
-+
-+bool dal_irq_service_dummy_set(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info,
-+	bool enable);
-+
-+bool dal_irq_service_dummy_ack(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info);
-+
-+bool dce110_vblank_set(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info,
-+	bool enable);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c.0130~	2017-12-14 06:39:58.438903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c	2017-12-14 06:39:58.438903583 +0100
-@@ -0,0 +1,289 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "irq_service_dce120.h"
-+#include "../dce110/irq_service_dce110.h"
-+
-+#include "vega10/DC/dce_12_0_offset.h"
-+#include "vega10/DC/dce_12_0_sh_mask.h"
-+#include "vega10/soc15ip.h"
-+
-+#include "ivsrcid/ivsrcid_vislands30.h"
-+
-+static bool hpd_ack(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info)
-+{
-+	uint32_t addr = info->status_reg;
-+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
-+	uint32_t current_status =
-+		get_reg_field_value(
-+			value,
-+			HPD0_DC_HPD_INT_STATUS,
-+			DC_HPD_SENSE_DELAYED);
-+
-+	dal_irq_service_ack_generic(irq_service, info);
-+
-+	value = dm_read_reg(irq_service->ctx, info->enable_reg);
-+
-+	set_reg_field_value(
-+		value,
-+		current_status ? 0 : 1,
-+		HPD0_DC_HPD_INT_CONTROL,
-+		DC_HPD_INT_POLARITY);
-+
-+	dm_write_reg(irq_service->ctx, info->enable_reg, value);
-+
-+	return true;
-+}
-+
-+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = hpd_ack
-+};
-+
-+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = NULL
-+};
-+
-+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = NULL
-+};
-+
-+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
-+	.set = dce110_vblank_set,
-+	.ack = NULL
-+};
-+
-+#define BASE_INNER(seg) \
-+	DCE_BASE__INST0_SEG ## seg
-+
-+#define BASE(seg) \
-+	BASE_INNER(seg)
-+
-+#define SRI(reg_name, block, id)\
-+	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-+			mm ## block ## id ## _ ## reg_name
-+
-+
-+#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
-+	.enable_reg = SRI(reg1, block, reg_num),\
-+	.enable_mask = \
-+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-+	.enable_value = {\
-+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-+		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
-+	},\
-+	.ack_reg = SRI(reg2, block, reg_num),\
-+	.ack_mask = \
-+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
-+	.ack_value = \
-+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
-+
-+#define hpd_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
-+		IRQ_REG_ENTRY(HPD, reg_num,\
-+			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
-+			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
-+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
-+		.funcs = &hpd_irq_info_funcs\
-+	}
-+
-+#define hpd_rx_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
-+		IRQ_REG_ENTRY(HPD, reg_num,\
-+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
-+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
-+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
-+		.funcs = &hpd_rx_irq_info_funcs\
-+	}
-+#define pflip_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
-+		IRQ_REG_ENTRY(DCP, reg_num, \
-+			GRPH_INTERRUPT_CONTROL, GRPH_PFLIP_INT_MASK, \
-+			GRPH_INTERRUPT_STATUS, GRPH_PFLIP_INT_CLEAR),\
-+		.status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\
-+		.funcs = &pflip_irq_info_funcs\
-+	}
-+
-+#define vupdate_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
-+		IRQ_REG_ENTRY(CRTC, reg_num,\
-+			CRTC_INTERRUPT_CONTROL, CRTC_V_UPDATE_INT_MSK,\
-+			CRTC_V_UPDATE_INT_STATUS, CRTC_V_UPDATE_INT_CLEAR),\
-+		.funcs = &vblank_irq_info_funcs\
-+	}
-+
-+#define vblank_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
-+		IRQ_REG_ENTRY(CRTC, reg_num,\
-+				CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_INT_ENABLE,\
-+				CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_CLEAR),\
-+		.funcs = &vblank_irq_info_funcs,\
-+		.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
-+	}
-+
-+#define dummy_irq_entry() \
-+	{\
-+		.funcs = &dummy_irq_info_funcs\
-+	}
-+
-+#define i2c_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
-+
-+#define dp_sink_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
-+
-+#define gpio_pad_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
-+
-+#define dc_underflow_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
-+
-+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
-+	.set = dal_irq_service_dummy_set,
-+	.ack = dal_irq_service_dummy_ack
-+};
-+
-+static const struct irq_source_info
-+irq_source_info_dce120[DAL_IRQ_SOURCES_NUMBER] = {
-+	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
-+	hpd_int_entry(0),
-+	hpd_int_entry(1),
-+	hpd_int_entry(2),
-+	hpd_int_entry(3),
-+	hpd_int_entry(4),
-+	hpd_int_entry(5),
-+	hpd_rx_int_entry(0),
-+	hpd_rx_int_entry(1),
-+	hpd_rx_int_entry(2),
-+	hpd_rx_int_entry(3),
-+	hpd_rx_int_entry(4),
-+	hpd_rx_int_entry(5),
-+	i2c_int_entry(1),
-+	i2c_int_entry(2),
-+	i2c_int_entry(3),
-+	i2c_int_entry(4),
-+	i2c_int_entry(5),
-+	i2c_int_entry(6),
-+	dp_sink_int_entry(1),
-+	dp_sink_int_entry(2),
-+	dp_sink_int_entry(3),
-+	dp_sink_int_entry(4),
-+	dp_sink_int_entry(5),
-+	dp_sink_int_entry(6),
-+	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
-+	pflip_int_entry(0),
-+	pflip_int_entry(1),
-+	pflip_int_entry(2),
-+	pflip_int_entry(3),
-+	pflip_int_entry(4),
-+	pflip_int_entry(5),
-+	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
-+	gpio_pad_int_entry(0),
-+	gpio_pad_int_entry(1),
-+	gpio_pad_int_entry(2),
-+	gpio_pad_int_entry(3),
-+	gpio_pad_int_entry(4),
-+	gpio_pad_int_entry(5),
-+	gpio_pad_int_entry(6),
-+	gpio_pad_int_entry(7),
-+	gpio_pad_int_entry(8),
-+	gpio_pad_int_entry(9),
-+	gpio_pad_int_entry(10),
-+	gpio_pad_int_entry(11),
-+	gpio_pad_int_entry(12),
-+	gpio_pad_int_entry(13),
-+	gpio_pad_int_entry(14),
-+	gpio_pad_int_entry(15),
-+	gpio_pad_int_entry(16),
-+	gpio_pad_int_entry(17),
-+	gpio_pad_int_entry(18),
-+	gpio_pad_int_entry(19),
-+	gpio_pad_int_entry(20),
-+	gpio_pad_int_entry(21),
-+	gpio_pad_int_entry(22),
-+	gpio_pad_int_entry(23),
-+	gpio_pad_int_entry(24),
-+	gpio_pad_int_entry(25),
-+	gpio_pad_int_entry(26),
-+	gpio_pad_int_entry(27),
-+	gpio_pad_int_entry(28),
-+	gpio_pad_int_entry(29),
-+	gpio_pad_int_entry(30),
-+	dc_underflow_int_entry(1),
-+	dc_underflow_int_entry(2),
-+	dc_underflow_int_entry(3),
-+	dc_underflow_int_entry(4),
-+	dc_underflow_int_entry(5),
-+	dc_underflow_int_entry(6),
-+	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
-+	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
-+	vupdate_int_entry(0),
-+	vupdate_int_entry(1),
-+	vupdate_int_entry(2),
-+	vupdate_int_entry(3),
-+	vupdate_int_entry(4),
-+	vupdate_int_entry(5),
-+	vblank_int_entry(0),
-+	vblank_int_entry(1),
-+	vblank_int_entry(2),
-+	vblank_int_entry(3),
-+	vblank_int_entry(4),
-+	vblank_int_entry(5),
-+};
-+
-+static const struct irq_service_funcs irq_service_funcs_dce120 = {
-+		.to_dal_irq_source = to_dal_irq_source_dce110
-+};
-+
-+static void construct(
-+	struct irq_service *irq_service,
-+	struct irq_service_init_data *init_data)
-+{
-+	dal_irq_service_construct(irq_service, init_data);
-+
-+	irq_service->info = irq_source_info_dce120;
-+	irq_service->funcs = &irq_service_funcs_dce120;
-+}
-+
-+struct irq_service *dal_irq_service_dce120_create(
-+	struct irq_service_init_data *init_data)
-+{
-+	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
-+						  GFP_KERNEL);
-+
-+	if (!irq_service)
-+		return NULL;
-+
-+	construct(irq_service, init_data);
-+	return irq_service;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.h.0130~	2017-12-14 06:39:58.438903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.h	2017-12-14 06:39:58.438903583 +0100
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IRQ_SERVICE_DCE120_H__
-+#define __DAL_IRQ_SERVICE_DCE120_H__
-+
-+#include "../irq_service.h"
-+
-+struct irq_service *dal_irq_service_dce120_create(
-+	struct irq_service_init_data *init_data);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c.0130~	2017-12-14 06:39:58.438903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c	2017-12-14 06:39:58.438903583 +0100
-@@ -0,0 +1,303 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "irq_service_dce80.h"
-+#include "../dce110/irq_service_dce110.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#include "ivsrcid/ivsrcid_vislands30.h"
-+
-+#include "dc_types.h"
-+
-+static bool hpd_ack(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info)
-+{
-+	uint32_t addr = info->status_reg;
-+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
-+	uint32_t current_status =
-+		get_reg_field_value(
-+			value,
-+			DC_HPD1_INT_STATUS,
-+			DC_HPD1_SENSE_DELAYED);
-+
-+	dal_irq_service_ack_generic(irq_service, info);
-+
-+	value = dm_read_reg(irq_service->ctx, info->enable_reg);
-+
-+	set_reg_field_value(
-+		value,
-+		current_status ? 0 : 1,
-+		DC_HPD1_INT_CONTROL,
-+		DC_HPD1_INT_POLARITY);
-+
-+	dm_write_reg(irq_service->ctx, info->enable_reg, value);
-+
-+	return true;
-+}
-+
-+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = hpd_ack
-+};
-+
-+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = NULL
-+};
-+
-+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = NULL
-+};
-+
-+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
-+	.set = dce110_vblank_set,
-+	.ack = NULL
-+};
-+
-+
-+#define hpd_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_INVALID + reg_num] = {\
-+		.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
-+		.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
-+		.enable_value = {\
-+			DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
-+			~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
-+		},\
-+		.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
-+		.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
-+		.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
-+		.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
-+		.funcs = &hpd_irq_info_funcs\
-+	}
-+
-+#define hpd_rx_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_HPD6 + reg_num] = {\
-+		.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
-+		.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
-+		.enable_value = {\
-+				DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
-+			~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
-+		.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
-+		.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
-+		.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
-+		.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
-+		.funcs = &hpd_rx_irq_info_funcs\
-+	}
-+
-+#define pflip_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
-+		.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\
-+		.enable_mask =\
-+		GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
-+		.enable_value = {\
-+			GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
-+			~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
-+		.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
-+		.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
-+		.ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
-+		.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
-+		.funcs = &pflip_irq_info_funcs\
-+ 	}
-+
-+#define vupdate_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
-+		.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\
-+		.enable_mask =\
-+		CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
-+		.enable_value = {\
-+			CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
-+			~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
-+		.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
-+		.ack_mask =\
-+		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
-+		.ack_value =\
-+		CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
-+		.funcs = &vblank_irq_info_funcs\
-+	}
-+
-+#define vblank_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
-+		.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
-+		.enable_mask =\
-+		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
-+		.enable_value = {\
-+			CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
-+			~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
-+		.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
-+		.ack_mask =\
-+		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
-+		.ack_value =\
-+		CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
-+		.funcs = &vblank_irq_info_funcs,\
-+		.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
-+	}
-+
-+#define dummy_irq_entry() \
-+	{\
-+		.funcs = &dummy_irq_info_funcs\
-+	}
-+
-+#define i2c_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
-+
-+#define dp_sink_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
-+
-+#define gpio_pad_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
-+
-+#define dc_underflow_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
-+
-+
-+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
-+	.set = dal_irq_service_dummy_set,
-+	.ack = dal_irq_service_dummy_ack
-+};
-+
-+static const struct irq_source_info
-+irq_source_info_dce80[DAL_IRQ_SOURCES_NUMBER] = {
-+	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
-+	hpd_int_entry(1),
-+	hpd_int_entry(2),
-+	hpd_int_entry(3),
-+	hpd_int_entry(4),
-+	hpd_int_entry(5),
-+	hpd_int_entry(6),
-+	hpd_rx_int_entry(1),
-+	hpd_rx_int_entry(2),
-+	hpd_rx_int_entry(3),
-+	hpd_rx_int_entry(4),
-+	hpd_rx_int_entry(5),
-+	hpd_rx_int_entry(6),
-+	i2c_int_entry(1),
-+	i2c_int_entry(2),
-+	i2c_int_entry(3),
-+	i2c_int_entry(4),
-+	i2c_int_entry(5),
-+	i2c_int_entry(6),
-+	dp_sink_int_entry(1),
-+	dp_sink_int_entry(2),
-+	dp_sink_int_entry(3),
-+	dp_sink_int_entry(4),
-+	dp_sink_int_entry(5),
-+	dp_sink_int_entry(6),
-+	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
-+	pflip_int_entry(0),
-+	pflip_int_entry(1),
-+	pflip_int_entry(2),
-+	pflip_int_entry(3),
-+	pflip_int_entry(4),
-+	pflip_int_entry(5),
-+	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
-+	gpio_pad_int_entry(0),
-+	gpio_pad_int_entry(1),
-+	gpio_pad_int_entry(2),
-+	gpio_pad_int_entry(3),
-+	gpio_pad_int_entry(4),
-+	gpio_pad_int_entry(5),
-+	gpio_pad_int_entry(6),
-+	gpio_pad_int_entry(7),
-+	gpio_pad_int_entry(8),
-+	gpio_pad_int_entry(9),
-+	gpio_pad_int_entry(10),
-+	gpio_pad_int_entry(11),
-+	gpio_pad_int_entry(12),
-+	gpio_pad_int_entry(13),
-+	gpio_pad_int_entry(14),
-+	gpio_pad_int_entry(15),
-+	gpio_pad_int_entry(16),
-+	gpio_pad_int_entry(17),
-+	gpio_pad_int_entry(18),
-+	gpio_pad_int_entry(19),
-+	gpio_pad_int_entry(20),
-+	gpio_pad_int_entry(21),
-+	gpio_pad_int_entry(22),
-+	gpio_pad_int_entry(23),
-+	gpio_pad_int_entry(24),
-+	gpio_pad_int_entry(25),
-+	gpio_pad_int_entry(26),
-+	gpio_pad_int_entry(27),
-+	gpio_pad_int_entry(28),
-+	gpio_pad_int_entry(29),
-+	gpio_pad_int_entry(30),
-+	dc_underflow_int_entry(1),
-+	dc_underflow_int_entry(2),
-+	dc_underflow_int_entry(3),
-+	dc_underflow_int_entry(4),
-+	dc_underflow_int_entry(5),
-+	dc_underflow_int_entry(6),
-+	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
-+	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
-+	vupdate_int_entry(0),
-+	vupdate_int_entry(1),
-+	vupdate_int_entry(2),
-+	vupdate_int_entry(3),
-+	vupdate_int_entry(4),
-+	vupdate_int_entry(5),
-+	vblank_int_entry(0),
-+	vblank_int_entry(1),
-+	vblank_int_entry(2),
-+	vblank_int_entry(3),
-+	vblank_int_entry(4),
-+	vblank_int_entry(5),
-+};
-+
-+static const struct irq_service_funcs irq_service_funcs_dce80 = {
-+		.to_dal_irq_source = to_dal_irq_source_dce110
-+};
-+
-+static void construct(
-+	struct irq_service *irq_service,
-+	struct irq_service_init_data *init_data)
-+{
-+	dal_irq_service_construct(irq_service, init_data);
-+
-+	irq_service->info = irq_source_info_dce80;
-+	irq_service->funcs = &irq_service_funcs_dce80;
-+}
-+
-+struct irq_service *dal_irq_service_dce80_create(
-+	struct irq_service_init_data *init_data)
-+{
-+	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
-+						  GFP_KERNEL);
-+
-+	if (!irq_service)
-+		return NULL;
-+
-+	construct(irq_service, init_data);
-+	return irq_service;
-+}
-+
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.h.0130~	2017-12-14 06:39:58.438903583 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.h	2017-12-14 06:39:58.438903583 +0100
-@@ -0,0 +1,35 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IRQ_SERVICE_DCE80_H__
-+#define __DAL_IRQ_SERVICE_DCE80_H__
-+
-+#include "../irq_service.h"
-+
-+struct irq_service *dal_irq_service_dce80_create(
-+	struct irq_service_init_data *init_data);
-+
-+#endif
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c.0130~	2017-12-14 06:39:58.439903584 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,356 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/logger_interface.h"
-+
-+#include "../dce110/irq_service_dce110.h"
-+
-+#include "raven1/DCN/dcn_1_0_offset.h"
-+#include "raven1/DCN/dcn_1_0_sh_mask.h"
-+#include "vega10/soc15ip.h"
-+
-+#include "irq_service_dcn10.h"
-+
-+#include "ivsrcid/irqsrcs_dcn_1_0.h"
-+
-+enum dc_irq_source to_dal_irq_source_dcn10(
-+		struct irq_service *irq_service,
-+		uint32_t src_id,
-+		uint32_t ext_id)
-+{
-+	switch (src_id) {
-+	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
-+		return DC_IRQ_SOURCE_VBLANK1;
-+	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
-+		return DC_IRQ_SOURCE_VBLANK2;
-+	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
-+		return DC_IRQ_SOURCE_VBLANK3;
-+	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
-+		return DC_IRQ_SOURCE_VBLANK4;
-+	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
-+		return DC_IRQ_SOURCE_VBLANK5;
-+	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
-+		return DC_IRQ_SOURCE_VBLANK6;
-+	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
-+		return DC_IRQ_SOURCE_PFLIP1;
-+	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
-+		return DC_IRQ_SOURCE_PFLIP2;
-+	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
-+		return DC_IRQ_SOURCE_PFLIP3;
-+	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
-+		return DC_IRQ_SOURCE_PFLIP4;
-+	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
-+		return DC_IRQ_SOURCE_PFLIP5;
-+	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
-+		return DC_IRQ_SOURCE_PFLIP6;
-+
-+	case DCN_1_0__SRCID__DC_HPD1_INT:
-+		/* generic src_id for all HPD and HPDRX interrupts */
-+		switch (ext_id) {
-+		case DCN_1_0__CTXID__DC_HPD1_INT:
-+			return DC_IRQ_SOURCE_HPD1;
-+		case DCN_1_0__CTXID__DC_HPD2_INT:
-+			return DC_IRQ_SOURCE_HPD2;
-+		case DCN_1_0__CTXID__DC_HPD3_INT:
-+			return DC_IRQ_SOURCE_HPD3;
-+		case DCN_1_0__CTXID__DC_HPD4_INT:
-+			return DC_IRQ_SOURCE_HPD4;
-+		case DCN_1_0__CTXID__DC_HPD5_INT:
-+			return DC_IRQ_SOURCE_HPD5;
-+		case DCN_1_0__CTXID__DC_HPD6_INT:
-+			return DC_IRQ_SOURCE_HPD6;
-+		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
-+			return DC_IRQ_SOURCE_HPD1RX;
-+		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
-+			return DC_IRQ_SOURCE_HPD2RX;
-+		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
-+			return DC_IRQ_SOURCE_HPD3RX;
-+		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
-+			return DC_IRQ_SOURCE_HPD4RX;
-+		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
-+			return DC_IRQ_SOURCE_HPD5RX;
-+		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
-+			return DC_IRQ_SOURCE_HPD6RX;
-+		default:
-+			return DC_IRQ_SOURCE_INVALID;
-+		}
-+		break;
-+
-+	default:
-+		return DC_IRQ_SOURCE_INVALID;
-+	}
-+}
-+
-+static bool hpd_ack(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info)
-+{
-+	uint32_t addr = info->status_reg;
-+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
-+	uint32_t current_status =
-+		get_reg_field_value(
-+			value,
-+			HPD0_DC_HPD_INT_STATUS,
-+			DC_HPD_SENSE_DELAYED);
-+
-+	dal_irq_service_ack_generic(irq_service, info);
-+
-+	value = dm_read_reg(irq_service->ctx, info->enable_reg);
-+
-+	set_reg_field_value(
-+		value,
-+		current_status ? 0 : 1,
-+		HPD0_DC_HPD_INT_CONTROL,
-+		DC_HPD_INT_POLARITY);
-+
-+	dm_write_reg(irq_service->ctx, info->enable_reg, value);
-+
-+	return true;
-+}
-+
-+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = hpd_ack
-+};
-+
-+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = NULL
-+};
-+
-+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = NULL
-+};
-+
-+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
-+	.set = NULL,
-+	.ack = NULL
-+};
-+
-+#define BASE_INNER(seg) \
-+	DCE_BASE__INST0_SEG ## seg
-+
-+#define BASE(seg) \
-+	BASE_INNER(seg)
-+
-+#define SRI(reg_name, block, id)\
-+	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-+			mm ## block ## id ## _ ## reg_name
-+
-+
-+#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
-+	.enable_reg = SRI(reg1, block, reg_num),\
-+	.enable_mask = \
-+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-+	.enable_value = {\
-+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
-+		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
-+	},\
-+	.ack_reg = SRI(reg2, block, reg_num),\
-+	.ack_mask = \
-+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
-+	.ack_value = \
-+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
-+
-+#define hpd_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
-+		IRQ_REG_ENTRY(HPD, reg_num,\
-+			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
-+			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
-+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
-+		.funcs = &hpd_irq_info_funcs\
-+	}
-+
-+#define hpd_rx_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
-+		IRQ_REG_ENTRY(HPD, reg_num,\
-+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
-+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
-+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
-+		.funcs = &hpd_rx_irq_info_funcs\
-+	}
-+#define pflip_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
-+		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
-+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
-+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
-+		.funcs = &pflip_irq_info_funcs\
-+	}
-+
-+#define vupdate_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
-+		IRQ_REG_ENTRY(OTG, reg_num,\
-+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
-+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
-+		.funcs = &vblank_irq_info_funcs\
-+	}
-+
-+#define vblank_int_entry(reg_num)\
-+	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
-+		IRQ_REG_ENTRY(OTG, reg_num,\
-+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
-+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
-+		.funcs = &vblank_irq_info_funcs\
-+	}
-+
-+#define dummy_irq_entry() \
-+	{\
-+		.funcs = &dummy_irq_info_funcs\
-+	}
-+
-+#define i2c_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
-+
-+#define dp_sink_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
-+
-+#define gpio_pad_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
-+
-+#define dc_underflow_int_entry(reg_num) \
-+	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
-+
-+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
-+	.set = dal_irq_service_dummy_set,
-+	.ack = dal_irq_service_dummy_ack
-+};
-+
-+static const struct irq_source_info
-+irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = {
-+	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
-+	hpd_int_entry(0),
-+	hpd_int_entry(1),
-+	hpd_int_entry(2),
-+	hpd_int_entry(3),
-+	hpd_int_entry(4),
-+	hpd_int_entry(5),
-+	hpd_rx_int_entry(0),
-+	hpd_rx_int_entry(1),
-+	hpd_rx_int_entry(2),
-+	hpd_rx_int_entry(3),
-+	hpd_rx_int_entry(4),
-+	hpd_rx_int_entry(5),
-+	i2c_int_entry(1),
-+	i2c_int_entry(2),
-+	i2c_int_entry(3),
-+	i2c_int_entry(4),
-+	i2c_int_entry(5),
-+	i2c_int_entry(6),
-+	dp_sink_int_entry(1),
-+	dp_sink_int_entry(2),
-+	dp_sink_int_entry(3),
-+	dp_sink_int_entry(4),
-+	dp_sink_int_entry(5),
-+	dp_sink_int_entry(6),
-+	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
-+	pflip_int_entry(0),
-+	pflip_int_entry(1),
-+	pflip_int_entry(2),
-+	pflip_int_entry(3),
-+	[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
-+	[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
-+	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
-+	gpio_pad_int_entry(0),
-+	gpio_pad_int_entry(1),
-+	gpio_pad_int_entry(2),
-+	gpio_pad_int_entry(3),
-+	gpio_pad_int_entry(4),
-+	gpio_pad_int_entry(5),
-+	gpio_pad_int_entry(6),
-+	gpio_pad_int_entry(7),
-+	gpio_pad_int_entry(8),
-+	gpio_pad_int_entry(9),
-+	gpio_pad_int_entry(10),
-+	gpio_pad_int_entry(11),
-+	gpio_pad_int_entry(12),
-+	gpio_pad_int_entry(13),
-+	gpio_pad_int_entry(14),
-+	gpio_pad_int_entry(15),
-+	gpio_pad_int_entry(16),
-+	gpio_pad_int_entry(17),
-+	gpio_pad_int_entry(18),
-+	gpio_pad_int_entry(19),
-+	gpio_pad_int_entry(20),
-+	gpio_pad_int_entry(21),
-+	gpio_pad_int_entry(22),
-+	gpio_pad_int_entry(23),
-+	gpio_pad_int_entry(24),
-+	gpio_pad_int_entry(25),
-+	gpio_pad_int_entry(26),
-+	gpio_pad_int_entry(27),
-+	gpio_pad_int_entry(28),
-+	gpio_pad_int_entry(29),
-+	gpio_pad_int_entry(30),
-+	dc_underflow_int_entry(1),
-+	dc_underflow_int_entry(2),
-+	dc_underflow_int_entry(3),
-+	dc_underflow_int_entry(4),
-+	dc_underflow_int_entry(5),
-+	dc_underflow_int_entry(6),
-+	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
-+	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
-+	vupdate_int_entry(0),
-+	vupdate_int_entry(1),
-+	vupdate_int_entry(2),
-+	vupdate_int_entry(3),
-+	vupdate_int_entry(4),
-+	vupdate_int_entry(5),
-+	vblank_int_entry(0),
-+	vblank_int_entry(1),
-+	vblank_int_entry(2),
-+	vblank_int_entry(3),
-+	vblank_int_entry(4),
-+	vblank_int_entry(5),
-+};
-+
-+static const struct irq_service_funcs irq_service_funcs_dcn10 = {
-+		.to_dal_irq_source = to_dal_irq_source_dcn10
-+};
-+
-+static void construct(
-+	struct irq_service *irq_service,
-+	struct irq_service_init_data *init_data)
-+{
-+	dal_irq_service_construct(irq_service, init_data);
-+
-+	irq_service->info = irq_source_info_dcn10;
-+	irq_service->funcs = &irq_service_funcs_dcn10;
-+}
-+
-+struct irq_service *dal_irq_service_dcn10_create(
-+	struct irq_service_init_data *init_data)
-+{
-+	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
-+						  GFP_KERNEL);
-+
-+	if (!irq_service)
-+		return NULL;
-+
-+	construct(irq_service, init_data);
-+	return irq_service;
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.h.0130~	2017-12-14 06:39:58.439903584 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.h	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IRQ_SERVICE_DCN10_H__
-+#define __DAL_IRQ_SERVICE_DCN10_H__
-+
-+#include "../irq_service.h"
-+
-+struct irq_service *dal_irq_service_dcn10_create(
-+	struct irq_service_init_data *init_data);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/irq/irq_service.c.0130~	2017-12-14 06:39:58.439903584 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/irq/irq_service.c	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,170 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+
-+#include "include/irq_service_interface.h"
-+#include "include/logger_interface.h"
-+
-+#include "dce110/irq_service_dce110.h"
-+
-+
-+#include "dce80/irq_service_dce80.h"
-+
-+#include "dce120/irq_service_dce120.h"
-+
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+#include "dcn10/irq_service_dcn10.h"
-+#endif
-+
-+#include "reg_helper.h"
-+#include "irq_service.h"
-+
-+
-+
-+#define CTX \
-+		irq_service->ctx
-+
-+void dal_irq_service_construct(
-+	struct irq_service *irq_service,
-+	struct irq_service_init_data *init_data)
-+{
-+	if (!init_data || !init_data->ctx) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	irq_service->ctx = init_data->ctx;
-+}
-+
-+void dal_irq_service_destroy(struct irq_service **irq_service)
-+{
-+	if (!irq_service || !*irq_service) {
-+		BREAK_TO_DEBUGGER();
-+		return;
-+	}
-+
-+	kfree(*irq_service);
-+
-+	*irq_service = NULL;
-+}
-+
-+const struct irq_source_info *find_irq_source_info(
-+	struct irq_service *irq_service,
-+	enum dc_irq_source source)
-+{
-+	if (source > DAL_IRQ_SOURCES_NUMBER || source < DC_IRQ_SOURCE_INVALID)
-+		return NULL;
-+
-+	return &irq_service->info[source];
-+}
-+
-+void dal_irq_service_set_generic(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info,
-+	bool enable)
-+{
-+	uint32_t addr = info->enable_reg;
-+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
-+
-+	value = (value & ~info->enable_mask) |
-+		(info->enable_value[enable ? 0 : 1] & info->enable_mask);
-+	dm_write_reg(irq_service->ctx, addr, value);
-+}
-+
-+bool dal_irq_service_set(
-+	struct irq_service *irq_service,
-+	enum dc_irq_source source,
-+	bool enable)
-+{
-+	const struct irq_source_info *info =
-+		find_irq_source_info(irq_service, source);
-+
-+	if (!info) {
-+		dm_logger_write(
-+			irq_service->ctx->logger, LOG_ERROR,
-+			"%s: cannot find irq info table entry for %d\n",
-+			__func__,
-+			source);
-+		return false;
-+	}
-+
-+	dal_irq_service_ack(irq_service, source);
-+
-+	if (info->funcs->set)
-+		return info->funcs->set(irq_service, info, enable);
-+
-+	dal_irq_service_set_generic(irq_service, info, enable);
-+
-+	return true;
-+}
-+
-+void dal_irq_service_ack_generic(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info)
-+{
-+	uint32_t addr = info->ack_reg;
-+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
-+
-+	value = (value & ~info->ack_mask) |
-+		(info->ack_value & info->ack_mask);
-+	dm_write_reg(irq_service->ctx, addr, value);
-+}
-+
-+bool dal_irq_service_ack(
-+	struct irq_service *irq_service,
-+	enum dc_irq_source source)
-+{
-+	const struct irq_source_info *info =
-+		find_irq_source_info(irq_service, source);
-+
-+	if (!info) {
-+		dm_logger_write(
-+			irq_service->ctx->logger, LOG_ERROR,
-+			"%s: cannot find irq info table entry for %d\n",
-+			__func__,
-+			source);
-+		return false;
-+	}
-+
-+	if (info->funcs->ack)
-+		return info->funcs->ack(irq_service, info);
-+
-+	dal_irq_service_ack_generic(irq_service, info);
-+
-+	return true;
-+}
-+
-+enum dc_irq_source dal_irq_service_to_irq_source(
-+		struct irq_service *irq_service,
-+		uint32_t src_id,
-+		uint32_t ext_id)
-+{
-+	return irq_service->funcs->to_dal_irq_source(
-+		irq_service,
-+		src_id,
-+		ext_id);
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/dc/irq/irq_service.h.0130~	2017-12-14 06:39:58.439903584 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/irq/irq_service.h	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,85 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IRQ_SERVICE_H__
-+#define __DAL_IRQ_SERVICE_H__
-+
-+#include "include/irq_service_interface.h"
-+
-+#include "irq_types.h"
-+
-+struct irq_service;
-+struct irq_source_info;
-+
-+struct irq_source_info_funcs {
-+	bool (*set)(
-+		struct irq_service *irq_service,
-+		const struct irq_source_info *info,
-+		bool enable);
-+	bool (*ack)(
-+		struct irq_service *irq_service,
-+		const struct irq_source_info *info);
-+};
-+
-+struct irq_source_info {
-+	uint32_t src_id;
-+	uint32_t ext_id;
-+	uint32_t enable_reg;
-+	uint32_t enable_mask;
-+	uint32_t enable_value[2];
-+	uint32_t ack_reg;
-+	uint32_t ack_mask;
-+	uint32_t ack_value;
-+	uint32_t status_reg;
-+	const struct irq_source_info_funcs *funcs;
-+};
-+
-+struct irq_service_funcs {
-+	enum dc_irq_source (*to_dal_irq_source)(
-+			struct irq_service *irq_service,
-+			uint32_t src_id,
-+			uint32_t ext_id);
-+};
-+
-+struct irq_service {
-+	struct dc_context *ctx;
-+	const struct irq_source_info *info;
-+	const struct irq_service_funcs *funcs;
-+};
-+
-+void dal_irq_service_construct(
-+	struct irq_service *irq_service,
-+	struct irq_service_init_data *init_data);
-+
-+void dal_irq_service_ack_generic(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info);
-+
-+void dal_irq_service_set_generic(
-+	struct irq_service *irq_service,
-+	const struct irq_source_info *info,
-+	bool enable);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/irq/Makefile.0130~	2017-12-14 06:39:58.439903584 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/irq/Makefile	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,48 @@
-+#
-+# Makefile for the 'audio' sub-component of DAL.
-+# It provides the control and status of HW adapter resources,
-+# that are global for the ASIC and sharable between pipes.
-+
-+IRQ = irq_service.o
-+
-+AMD_DAL_IRQ = $(addprefix $(AMDDALPATH)/dc/irq/,$(IRQ))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ)
-+
-+###############################################################################
-+# DCE 8x
-+###############################################################################
-+IRQ_DCE80 = irq_service_dce80.o
-+
-+AMD_DAL_IRQ_DCE80 = $(addprefix $(AMDDALPATH)/dc/irq/dce80/,$(IRQ_DCE80))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE80)
-+
-+###############################################################################
-+# DCE 11x
-+###############################################################################
-+IRQ_DCE11 = irq_service_dce110.o
-+
-+AMD_DAL_IRQ_DCE11 = $(addprefix $(AMDDALPATH)/dc/irq/dce110/,$(IRQ_DCE11))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE11)
-+
-+###############################################################################
-+# DCE 12x
-+###############################################################################
-+IRQ_DCE12 = irq_service_dce120.o
-+
-+AMD_DAL_IRQ_DCE12 = $(addprefix $(AMDDALPATH)/dc/irq/dce120/,$(IRQ_DCE12))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12)
-+
-+###############################################################################
-+# DCN 1x
-+###############################################################################
-+ifdef CONFIG_DRM_AMD_DC_DCN1_0
-+IRQ_DCN1 = irq_service_dcn10.o
-+
-+AMD_DAL_IRQ_DCN1 = $(addprefix $(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN1)
-+endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/irq_types.h.0130~	2017-12-14 06:39:58.439903584 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/irq_types.h	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,193 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IRQ_TYPES_H__
-+#define __DAL_IRQ_TYPES_H__
-+
-+struct dc_context;
-+
-+typedef void (*interrupt_handler)(void *);
-+
-+typedef void *irq_handler_idx;
-+#define DAL_INVALID_IRQ_HANDLER_IDX NULL
-+
-+/* The order of the IRQ sources is important and MUST match the one's
-+of base driver */
-+enum dc_irq_source {
-+	/* Use as mask to specify invalid irq source */
-+	DC_IRQ_SOURCE_INVALID = 0,
-+
-+	DC_IRQ_SOURCE_HPD1,
-+	DC_IRQ_SOURCE_HPD2,
-+	DC_IRQ_SOURCE_HPD3,
-+	DC_IRQ_SOURCE_HPD4,
-+	DC_IRQ_SOURCE_HPD5,
-+	DC_IRQ_SOURCE_HPD6,
-+
-+	DC_IRQ_SOURCE_HPD1RX,
-+	DC_IRQ_SOURCE_HPD2RX,
-+	DC_IRQ_SOURCE_HPD3RX,
-+	DC_IRQ_SOURCE_HPD4RX,
-+	DC_IRQ_SOURCE_HPD5RX,
-+	DC_IRQ_SOURCE_HPD6RX,
-+
-+	DC_IRQ_SOURCE_I2C_DDC1,
-+	DC_IRQ_SOURCE_I2C_DDC2,
-+	DC_IRQ_SOURCE_I2C_DDC3,
-+	DC_IRQ_SOURCE_I2C_DDC4,
-+	DC_IRQ_SOURCE_I2C_DDC5,
-+	DC_IRQ_SOURCE_I2C_DDC6,
-+
-+	DC_IRQ_SOURCE_DPSINK1,
-+	DC_IRQ_SOURCE_DPSINK2,
-+	DC_IRQ_SOURCE_DPSINK3,
-+	DC_IRQ_SOURCE_DPSINK4,
-+	DC_IRQ_SOURCE_DPSINK5,
-+	DC_IRQ_SOURCE_DPSINK6,
-+
-+	DC_IRQ_SOURCE_TIMER,
-+
-+	DC_IRQ_SOURCE_PFLIP_FIRST,
-+	DC_IRQ_SOURCE_PFLIP1 = DC_IRQ_SOURCE_PFLIP_FIRST,
-+	DC_IRQ_SOURCE_PFLIP2,
-+	DC_IRQ_SOURCE_PFLIP3,
-+	DC_IRQ_SOURCE_PFLIP4,
-+	DC_IRQ_SOURCE_PFLIP5,
-+	DC_IRQ_SOURCE_PFLIP6,
-+	DC_IRQ_SOURCE_PFLIP_UNDERLAY0,
-+	DC_IRQ_SOURCE_PFLIP_LAST = DC_IRQ_SOURCE_PFLIP_UNDERLAY0,
-+
-+	DC_IRQ_SOURCE_GPIOPAD0,
-+	DC_IRQ_SOURCE_GPIOPAD1,
-+	DC_IRQ_SOURCE_GPIOPAD2,
-+	DC_IRQ_SOURCE_GPIOPAD3,
-+	DC_IRQ_SOURCE_GPIOPAD4,
-+	DC_IRQ_SOURCE_GPIOPAD5,
-+	DC_IRQ_SOURCE_GPIOPAD6,
-+	DC_IRQ_SOURCE_GPIOPAD7,
-+	DC_IRQ_SOURCE_GPIOPAD8,
-+	DC_IRQ_SOURCE_GPIOPAD9,
-+	DC_IRQ_SOURCE_GPIOPAD10,
-+	DC_IRQ_SOURCE_GPIOPAD11,
-+	DC_IRQ_SOURCE_GPIOPAD12,
-+	DC_IRQ_SOURCE_GPIOPAD13,
-+	DC_IRQ_SOURCE_GPIOPAD14,
-+	DC_IRQ_SOURCE_GPIOPAD15,
-+	DC_IRQ_SOURCE_GPIOPAD16,
-+	DC_IRQ_SOURCE_GPIOPAD17,
-+	DC_IRQ_SOURCE_GPIOPAD18,
-+	DC_IRQ_SOURCE_GPIOPAD19,
-+	DC_IRQ_SOURCE_GPIOPAD20,
-+	DC_IRQ_SOURCE_GPIOPAD21,
-+	DC_IRQ_SOURCE_GPIOPAD22,
-+	DC_IRQ_SOURCE_GPIOPAD23,
-+	DC_IRQ_SOURCE_GPIOPAD24,
-+	DC_IRQ_SOURCE_GPIOPAD25,
-+	DC_IRQ_SOURCE_GPIOPAD26,
-+	DC_IRQ_SOURCE_GPIOPAD27,
-+	DC_IRQ_SOURCE_GPIOPAD28,
-+	DC_IRQ_SOURCE_GPIOPAD29,
-+	DC_IRQ_SOURCE_GPIOPAD30,
-+
-+	DC_IRQ_SOURCE_DC1UNDERFLOW,
-+	DC_IRQ_SOURCE_DC2UNDERFLOW,
-+	DC_IRQ_SOURCE_DC3UNDERFLOW,
-+	DC_IRQ_SOURCE_DC4UNDERFLOW,
-+	DC_IRQ_SOURCE_DC5UNDERFLOW,
-+	DC_IRQ_SOURCE_DC6UNDERFLOW,
-+
-+	DC_IRQ_SOURCE_DMCU_SCP,
-+	DC_IRQ_SOURCE_VBIOS_SW,
-+
-+	DC_IRQ_SOURCE_VUPDATE1,
-+	DC_IRQ_SOURCE_VUPDATE2,
-+	DC_IRQ_SOURCE_VUPDATE3,
-+	DC_IRQ_SOURCE_VUPDATE4,
-+	DC_IRQ_SOURCE_VUPDATE5,
-+	DC_IRQ_SOURCE_VUPDATE6,
-+
-+	DC_IRQ_SOURCE_VBLANK1,
-+	DC_IRQ_SOURCE_VBLANK2,
-+	DC_IRQ_SOURCE_VBLANK3,
-+	DC_IRQ_SOURCE_VBLANK4,
-+	DC_IRQ_SOURCE_VBLANK5,
-+	DC_IRQ_SOURCE_VBLANK6,
-+
-+	DAL_IRQ_SOURCES_NUMBER
-+};
-+
-+enum irq_type
-+{
-+	IRQ_TYPE_PFLIP = DC_IRQ_SOURCE_PFLIP1,
-+	IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1,
-+	IRQ_TYPE_VBLANK = DC_IRQ_SOURCE_VBLANK1,
-+};
-+
-+#define DAL_VALID_IRQ_SRC_NUM(src) \
-+	((src) <= DAL_IRQ_SOURCES_NUMBER && (src) > DC_IRQ_SOURCE_INVALID)
-+
-+/* Number of Page Flip IRQ Sources. */
-+#define DAL_PFLIP_IRQ_SRC_NUM \
-+	(DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1)
-+
-+/* the number of contexts may be expanded in the future based on needs */
-+enum dc_interrupt_context {
-+	INTERRUPT_LOW_IRQ_CONTEXT = 0,
-+	INTERRUPT_HIGH_IRQ_CONTEXT,
-+	INTERRUPT_CONTEXT_NUMBER
-+};
-+
-+enum dc_interrupt_porlarity {
-+	INTERRUPT_POLARITY_DEFAULT = 0,
-+	INTERRUPT_POLARITY_LOW = INTERRUPT_POLARITY_DEFAULT,
-+	INTERRUPT_POLARITY_HIGH,
-+	INTERRUPT_POLARITY_BOTH
-+};
-+
-+#define DC_DECODE_INTERRUPT_POLARITY(int_polarity) \
-+	(int_polarity == INTERRUPT_POLARITY_LOW) ? "Low" : \
-+	(int_polarity == INTERRUPT_POLARITY_HIGH) ? "High" : \
-+	(int_polarity == INTERRUPT_POLARITY_BOTH) ? "Both" : "Invalid"
-+
-+struct dc_timer_interrupt_params {
-+	uint32_t micro_sec_interval;
-+	enum dc_interrupt_context int_context;
-+};
-+
-+struct dc_interrupt_params {
-+	/* The polarity *change* which will trigger an interrupt.
-+	 * If 'requested_polarity == INTERRUPT_POLARITY_BOTH', then
-+	 * 'current_polarity' must be initialised. */
-+	enum dc_interrupt_porlarity requested_polarity;
-+	/* If 'requested_polarity == INTERRUPT_POLARITY_BOTH',
-+	 * 'current_polarity' should contain the current state, which means
-+	 * the interrupt will be triggered when state changes from what is,
-+	 * in 'current_polarity'. */
-+	enum dc_interrupt_porlarity current_polarity;
-+	enum dc_irq_source irq_source;
-+	enum dc_interrupt_context int_context;
-+};
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/dc/Makefile.0130~	2017-12-14 06:39:58.439903584 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/Makefile	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,33 @@
-+#
-+# Makefile for Display Core (dc) component.
-+#
-+
-+DC_LIBS = basics bios calcs dce gpio i2caux irq virtual
-+
-+ifdef CONFIG_DRM_AMD_DC_DCN1_0
-+DC_LIBS += dcn10 dml
-+endif
-+
-+DC_LIBS += dce120
-+
-+DC_LIBS += dce112
-+DC_LIBS += dce110
-+DC_LIBS += dce100
-+DC_LIBS += dce80
-+
-+AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LIBS)))
-+
-+include $(AMD_DC)
-+
-+DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
-+dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o
-+
-+AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
-+
-+AMD_DM_REG_UPDATE = $(addprefix $(AMDDALPATH)/dc/,dc_helper.o)
-+
-+AMD_DISPLAY_FILES += $(AMD_DISPLAY_CORE)
-+AMD_DISPLAY_FILES += $(AMD_DM_REG_UPDATE)
-+
-+
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/os_types.h.0130~	2017-12-14 06:39:58.439903584 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/os_types.h	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,96 @@
-+/*
-+ * Copyright 2012-16 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef _OS_TYPES_H_
-+#define _OS_TYPES_H_
-+
-+#if defined __KERNEL__
-+
-+#include <asm/byteorder.h>
-+#include <linux/types.h>
-+#include <drm/drmP.h>
-+
-+#include <linux/kref.h>
-+
-+#include "cgs_linux.h"
-+
-+#if defined(__BIG_ENDIAN) && !defined(BIGENDIAN_CPU)
-+#define BIGENDIAN_CPU
-+#elif defined(__LITTLE_ENDIAN) && !defined(LITTLEENDIAN_CPU)
-+#define LITTLEENDIAN_CPU
-+#endif
-+
-+#undef READ
-+#undef WRITE
-+#undef FRAME_SIZE
-+
-+#define dm_output_to_console(fmt, ...) DRM_INFO(fmt, ##__VA_ARGS__)
-+
-+#define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
-+
-+#define dm_debug(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__)
-+
-+#define dm_vlog(fmt, args) vprintk(fmt, args)
-+
-+#endif
-+
-+/*
-+ *
-+ * general debug capabilities
-+ *
-+ */
-+#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB)
-+#define ASSERT_CRITICAL(expr) do {	\
-+	if (WARN_ON(!(expr))) { \
-+		kgdb_breakpoint(); \
-+	} \
-+} while (0)
-+#else
-+#define ASSERT_CRITICAL(expr) do {	\
-+	if (WARN_ON(!(expr))) { \
-+		; \
-+	} \
-+} while (0)
-+#endif
-+
-+#if defined(CONFIG_DEBUG_KERNEL_DC)
-+#define ASSERT(expr) ASSERT_CRITICAL(expr)
-+
-+#else
-+#define ASSERT(expr) WARN_ON(!(expr))
-+#endif
-+
-+#define BREAK_TO_DEBUGGER() ASSERT(0)
-+
-+#define DC_ERR(...)  do { \
-+	dm_error(__VA_ARGS__); \
-+	BREAK_TO_DEBUGGER(); \
-+} while (0)
-+
-+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-+#include <asm/fpu/api.h>
-+#endif
-+
-+#endif /* _OS_TYPES_H_ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/virtual/Makefile.0130~	2017-12-14 06:39:58.439903584 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/virtual/Makefile	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,9 @@
-+#
-+# Makefile for the virtual sub-component of DAL.
-+# It provides the control and status of HW CRTC block.
-+
-+VIRTUAL = virtual_link_encoder.o virtual_stream_encoder.o
-+
-+AMD_DAL_VIRTUAL = $(addprefix $(AMDDALPATH)/dc/virtual/,$(VIRTUAL))
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_VIRTUAL)
---- linux-4.14/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c.0130~	2017-12-14 06:39:58.439903584 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,123 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dm_services_types.h"
-+
-+#include "virtual_link_encoder.h"
-+
-+static bool virtual_link_encoder_validate_output_with_stream(
-+	struct link_encoder *enc,
-+	const struct dc_stream_state *stream) { return true; }
-+
-+static void virtual_link_encoder_hw_init(struct link_encoder *enc) {}
-+
-+static void virtual_link_encoder_setup(
-+	struct link_encoder *enc,
-+	enum signal_type signal) {}
-+
-+static void virtual_link_encoder_enable_tmds_output(
-+	struct link_encoder *enc,
-+	enum clock_source_id clock_source,
-+	enum dc_color_depth color_depth,
-+	bool hdmi,
-+	bool dual_link,
-+	uint32_t pixel_clock) {}
-+
-+static void virtual_link_encoder_enable_dp_output(
-+	struct link_encoder *enc,
-+	const struct dc_link_settings *link_settings,
-+	enum clock_source_id clock_source) {}
-+
-+static void virtual_link_encoder_enable_dp_mst_output(
-+	struct link_encoder *enc,
-+	const struct dc_link_settings *link_settings,
-+	enum clock_source_id clock_source) {}
-+
-+static void virtual_link_encoder_disable_output(
-+	struct link_encoder *link_enc,
-+	enum signal_type signal) {}
-+
-+static void virtual_link_encoder_dp_set_lane_settings(
-+	struct link_encoder *enc,
-+	const struct link_training_settings *link_settings) {}
-+
-+static void virtual_link_encoder_dp_set_phy_pattern(
-+	struct link_encoder *enc,
-+	const struct encoder_set_dp_phy_pattern_param *param) {}
-+
-+static void virtual_link_encoder_update_mst_stream_allocation_table(
-+	struct link_encoder *enc,
-+	const struct link_mst_stream_allocation_table *table) {}
-+
-+static void virtual_link_encoder_connect_dig_be_to_fe(
-+	struct link_encoder *enc,
-+	enum engine_id engine,
-+	bool connect) {}
-+
-+static void virtual_link_encoder_destroy(struct link_encoder **enc)
-+{
-+	kfree(*enc);
-+	*enc = NULL;
-+}
-+
-+
-+static const struct link_encoder_funcs virtual_lnk_enc_funcs = {
-+	.validate_output_with_stream =
-+		virtual_link_encoder_validate_output_with_stream,
-+	.hw_init = virtual_link_encoder_hw_init,
-+	.setup = virtual_link_encoder_setup,
-+	.enable_tmds_output = virtual_link_encoder_enable_tmds_output,
-+	.enable_dp_output = virtual_link_encoder_enable_dp_output,
-+	.enable_dp_mst_output = virtual_link_encoder_enable_dp_mst_output,
-+	.disable_output = virtual_link_encoder_disable_output,
-+	.dp_set_lane_settings = virtual_link_encoder_dp_set_lane_settings,
-+	.dp_set_phy_pattern = virtual_link_encoder_dp_set_phy_pattern,
-+	.update_mst_stream_allocation_table =
-+		virtual_link_encoder_update_mst_stream_allocation_table,
-+	.connect_dig_be_to_fe = virtual_link_encoder_connect_dig_be_to_fe,
-+	.destroy = virtual_link_encoder_destroy
-+};
-+
-+bool virtual_link_encoder_construct(
-+	struct link_encoder *enc, const struct encoder_init_data *init_data)
-+{
-+	enc->funcs = &virtual_lnk_enc_funcs;
-+	enc->ctx = init_data->ctx;
-+	enc->id = init_data->encoder;
-+
-+	enc->hpd_source = init_data->hpd_source;
-+	enc->connector = init_data->connector;
-+
-+	enc->transmitter = init_data->transmitter;
-+
-+	enc->output_signals = SIGNAL_TYPE_VIRTUAL;
-+
-+	enc->preferred_engine = ENGINE_ID_VIRTUAL;
-+
-+	return true;
-+}
-+
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.h.0130~	2017-12-14 06:39:58.439903584 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.h	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_VIRTUAL_LINK_ENCODER_H__
-+#define __DC_VIRTUAL_LINK_ENCODER_H__
-+
-+#include "link_encoder.h"
-+
-+bool virtual_link_encoder_construct(
-+	struct link_encoder *enc, const struct encoder_init_data *init_data);
-+
-+#endif /* __DC_VIRTUAL_LINK_ENCODER_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c.0130~	2017-12-14 06:39:58.439903584 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,136 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "virtual_stream_encoder.h"
-+
-+static void virtual_stream_encoder_dp_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	enum dc_color_space output_color_space) {}
-+
-+static void virtual_stream_encoder_hdmi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	int actual_pix_clk_khz,
-+	bool enable_audio) {}
-+
-+static void virtual_stream_encoder_dvi_set_stream_attribute(
-+	struct stream_encoder *enc,
-+	struct dc_crtc_timing *crtc_timing,
-+	bool is_dual_link) {}
-+
-+static void virtual_stream_encoder_set_mst_bandwidth(
-+	struct stream_encoder *enc,
-+	struct fixed31_32 avg_time_slots_per_mtp) {}
-+
-+static void virtual_stream_encoder_update_hdmi_info_packets(
-+	struct stream_encoder *enc,
-+	const struct encoder_info_frame *info_frame) {}
-+
-+static void virtual_stream_encoder_stop_hdmi_info_packets(
-+	struct stream_encoder *enc) {}
-+
-+static void virtual_stream_encoder_set_avmute(
-+	struct stream_encoder *enc,
-+	bool enable) {}
-+static void virtual_stream_encoder_update_dp_info_packets(
-+	struct stream_encoder *enc,
-+	const struct encoder_info_frame *info_frame) {}
-+
-+static void virtual_stream_encoder_stop_dp_info_packets(
-+	struct stream_encoder *enc) {}
-+
-+static void virtual_stream_encoder_dp_blank(
-+	struct stream_encoder *enc) {}
-+
-+static void virtual_stream_encoder_dp_unblank(
-+	struct stream_encoder *enc,
-+	const struct encoder_unblank_param *param) {}
-+
-+static void virtual_audio_mute_control(
-+	struct stream_encoder *enc,
-+	bool mute) {}
-+
-+static const struct stream_encoder_funcs virtual_str_enc_funcs = {
-+	.dp_set_stream_attribute =
-+		virtual_stream_encoder_dp_set_stream_attribute,
-+	.hdmi_set_stream_attribute =
-+		virtual_stream_encoder_hdmi_set_stream_attribute,
-+	.dvi_set_stream_attribute =
-+		virtual_stream_encoder_dvi_set_stream_attribute,
-+	.set_mst_bandwidth =
-+		virtual_stream_encoder_set_mst_bandwidth,
-+	.update_hdmi_info_packets =
-+		virtual_stream_encoder_update_hdmi_info_packets,
-+	.stop_hdmi_info_packets =
-+		virtual_stream_encoder_stop_hdmi_info_packets,
-+	.update_dp_info_packets =
-+		virtual_stream_encoder_update_dp_info_packets,
-+	.stop_dp_info_packets =
-+		virtual_stream_encoder_stop_dp_info_packets,
-+	.dp_blank =
-+		virtual_stream_encoder_dp_blank,
-+	.dp_unblank =
-+		virtual_stream_encoder_dp_unblank,
-+
-+	.audio_mute_control = virtual_audio_mute_control,
-+	.set_avmute = virtual_stream_encoder_set_avmute,
-+};
-+
-+bool virtual_stream_encoder_construct(
-+	struct stream_encoder *enc,
-+	struct dc_context *ctx,
-+	struct dc_bios *bp)
-+{
-+	if (!enc)
-+		return false;
-+	if (!bp)
-+		return false;
-+
-+	enc->funcs = &virtual_str_enc_funcs;
-+	enc->ctx = ctx;
-+	enc->id = ENGINE_ID_VIRTUAL;
-+	enc->bp = bp;
-+
-+	return true;
-+}
-+
-+struct stream_encoder *virtual_stream_encoder_create(
-+	struct dc_context *ctx, struct dc_bios *bp)
-+{
-+	struct stream_encoder *enc = kzalloc(sizeof(*enc), GFP_KERNEL);
-+
-+	if (!enc)
-+		return NULL;
-+
-+	if (virtual_stream_encoder_construct(enc, ctx, bp))
-+		return enc;
-+
-+	BREAK_TO_DEBUGGER();
-+	kfree(enc);
-+	return NULL;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.h.0130~	2017-12-14 06:39:58.439903584 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.h	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,39 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_VIRTUAL_STREAM_ENCODER_H__
-+#define __DC_VIRTUAL_STREAM_ENCODER_H__
-+
-+#include "stream_encoder.h"
-+
-+struct stream_encoder *virtual_stream_encoder_create(
-+	struct dc_context *ctx, struct dc_bios *bp);
-+
-+bool virtual_stream_encoder_construct(
-+	struct stream_encoder *enc,
-+	struct dc_context *ctx,
-+	struct dc_bios *bp);
-+
-+#endif /* __DC_VIRTUAL_STREAM_ENCODER_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/include/audio_types.h.0130~	2017-12-14 06:39:58.439903584 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/audio_types.h	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,106 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __AUDIO_TYPES_H__
-+#define __AUDIO_TYPES_H__
-+
-+#include "signal_types.h"
-+
-+#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
-+#define MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 18
-+#define MULTI_CHANNEL_SPLIT_NO_ASSO_INFO 0xFFFFFFFF
-+
-+
-+struct audio_crtc_info {
-+	uint32_t h_total;
-+	uint32_t h_active;
-+	uint32_t v_active;
-+	uint32_t pixel_repetition;
-+	uint32_t requested_pixel_clock; /* in KHz */
-+	uint32_t calculated_pixel_clock; /* in KHz */
-+	uint32_t refresh_rate;
-+	enum dc_color_depth color_depth;
-+	bool interlaced;
-+};
-+struct azalia_clock_info {
-+	uint32_t pixel_clock_in_10khz;
-+	uint32_t audio_dto_phase;
-+	uint32_t audio_dto_module;
-+	uint32_t audio_dto_wall_clock_ratio;
-+};
-+
-+enum audio_dto_source {
-+	DTO_SOURCE_UNKNOWN = 0,
-+	DTO_SOURCE_ID0,
-+	DTO_SOURCE_ID1,
-+	DTO_SOURCE_ID2,
-+	DTO_SOURCE_ID3,
-+	DTO_SOURCE_ID4,
-+	DTO_SOURCE_ID5
-+};
-+
-+/* PLL information required for AZALIA DTO calculation */
-+
-+struct audio_pll_info {
-+	uint32_t dp_dto_source_clock_in_khz;
-+	uint32_t feed_back_divider;
-+	enum audio_dto_source dto_source;
-+	bool ss_enabled;
-+	uint32_t ss_percentage;
-+	uint32_t ss_percentage_divider;
-+};
-+
-+struct audio_channel_associate_info {
-+	union {
-+		struct {
-+			uint32_t ALL_CHANNEL_FL:4;
-+			uint32_t ALL_CHANNEL_FR:4;
-+			uint32_t ALL_CHANNEL_FC:4;
-+			uint32_t ALL_CHANNEL_Sub:4;
-+			uint32_t ALL_CHANNEL_SL:4;
-+			uint32_t ALL_CHANNEL_SR:4;
-+			uint32_t ALL_CHANNEL_BL:4;
-+			uint32_t ALL_CHANNEL_BR:4;
-+		} bits;
-+		uint32_t u32all;
-+	};
-+};
-+
-+struct audio_output {
-+	/* Front DIG id. */
-+	enum engine_id engine_id;
-+	/* encoder output signal */
-+	enum signal_type signal;
-+	/* video timing */
-+	struct audio_crtc_info crtc_info;
-+	/* PLL for audio */
-+	struct audio_pll_info pll_info;
-+};
-+
-+enum audio_payload {
-+	CHANNEL_SPLIT_MAPPINGCHANG = 0x9,
-+};
-+
-+#endif /* __AUDIO_TYPES_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/include/bios_parser_interface.h.0130~	2017-12-14 06:39:58.440903585 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/bios_parser_interface.h	2017-12-14 06:39:58.439903584 +0100
-@@ -0,0 +1,44 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_INTERFACE_H__
-+#define __DAL_BIOS_PARSER_INTERFACE_H__
-+
-+#include "dc_bios_types.h"
-+
-+struct bios_parser;
-+
-+struct bp_init_data {
-+	struct dc_context *ctx;
-+	uint8_t *bios;
-+};
-+
-+struct dc_bios *dal_bios_parser_create(
-+	struct bp_init_data *init,
-+	enum dce_version dce_version);
-+
-+void dal_bios_parser_destroy(struct dc_bios **dcb);
-+
-+#endif /* __DAL_BIOS_PARSER_INTERFACE_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/include/bios_parser_types.h.0130~	2017-12-14 06:39:58.440903585 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/bios_parser_types.h	2017-12-14 06:39:58.440903585 +0100
-@@ -0,0 +1,310 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_BIOS_PARSER_TYPES_H__
-+
-+#define __DAL_BIOS_PARSER_TYPES_H__
-+
-+#include "dm_services.h"
-+#include "include/signal_types.h"
-+#include "include/grph_object_ctrl_defs.h"
-+#include "include/gpio_types.h"
-+#include "include/link_service_types.h"
-+
-+/* TODO: include signal_types.h and remove this enum */
-+enum as_signal_type {
-+	AS_SIGNAL_TYPE_NONE = 0L, /* no signal */
-+	AS_SIGNAL_TYPE_DVI,
-+	AS_SIGNAL_TYPE_HDMI,
-+	AS_SIGNAL_TYPE_LVDS,
-+	AS_SIGNAL_TYPE_DISPLAY_PORT,
-+	AS_SIGNAL_TYPE_GPU_PLL,
-+	AS_SIGNAL_TYPE_UNKNOWN
-+};
-+
-+enum bp_result {
-+	BP_RESULT_OK = 0, /* There was no error */
-+	BP_RESULT_BADINPUT, /*Bad input parameter */
-+	BP_RESULT_BADBIOSTABLE, /* Bad BIOS table */
-+	BP_RESULT_UNSUPPORTED, /* BIOS Table is not supported */
-+	BP_RESULT_NORECORD, /* Record can't be found */
-+	BP_RESULT_FAILURE
-+};
-+
-+enum bp_encoder_control_action {
-+	/* direct VBIOS translation! Just to simplify the translation */
-+	ENCODER_CONTROL_DISABLE = 0,
-+	ENCODER_CONTROL_ENABLE,
-+	ENCODER_CONTROL_SETUP,
-+	ENCODER_CONTROL_INIT
-+};
-+
-+enum bp_transmitter_control_action {
-+	/* direct VBIOS translation! Just to simplify the translation */
-+	TRANSMITTER_CONTROL_DISABLE = 0,
-+	TRANSMITTER_CONTROL_ENABLE,
-+	TRANSMITTER_CONTROL_BACKLIGHT_OFF,
-+	TRANSMITTER_CONTROL_BACKLIGHT_ON,
-+	TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS,
-+	TRANSMITTER_CONTROL_LCD_SETF_TEST_START,
-+	TRANSMITTER_CONTROL_LCD_SELF_TEST_STOP,
-+	TRANSMITTER_CONTROL_INIT,
-+	TRANSMITTER_CONTROL_DEACTIVATE,
-+	TRANSMITTER_CONTROL_ACTIAVATE,
-+	TRANSMITTER_CONTROL_SETUP,
-+	TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS,
-+	/* ATOM_TRANSMITTER_ACTION_POWER_ON. This action is for eDP only
-+	 * (power up the panel)
-+	 */
-+	TRANSMITTER_CONTROL_POWER_ON,
-+	/* ATOM_TRANSMITTER_ACTION_POWER_OFF. This action is for eDP only
-+	 * (power down the panel)
-+	 */
-+	TRANSMITTER_CONTROL_POWER_OFF
-+};
-+
-+enum bp_external_encoder_control_action {
-+	EXTERNAL_ENCODER_CONTROL_DISABLE = 0,
-+	EXTERNAL_ENCODER_CONTROL_ENABLE = 1,
-+	EXTERNAL_ENCODER_CONTROL_INIT = 0x7,
-+	EXTERNAL_ENCODER_CONTROL_SETUP = 0xf,
-+	EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10,
-+	EXTERNAL_ENCODER_CONTROL_BLANK = 0x11,
-+};
-+
-+enum bp_pipe_control_action {
-+	ASIC_PIPE_DISABLE = 0,
-+	ASIC_PIPE_ENABLE,
-+	ASIC_PIPE_INIT
-+};
-+
-+struct bp_encoder_control {
-+	enum bp_encoder_control_action action;
-+	enum engine_id engine_id;
-+	enum transmitter transmitter;
-+	enum signal_type signal;
-+	enum dc_lane_count lanes_number;
-+	enum dc_color_depth color_depth;
-+	bool enable_dp_audio;
-+	uint32_t pixel_clock; /* khz */
-+};
-+
-+struct bp_external_encoder_control {
-+	enum bp_external_encoder_control_action action;
-+	enum engine_id engine_id;
-+	enum dc_link_rate link_rate;
-+	enum dc_lane_count lanes_number;
-+	enum signal_type signal;
-+	enum dc_color_depth color_depth;
-+	bool coherent;
-+	struct graphics_object_id encoder_id;
-+	struct graphics_object_id connector_obj_id;
-+	uint32_t pixel_clock; /* in KHz */
-+};
-+
-+struct bp_crtc_source_select {
-+	enum engine_id engine_id;
-+	enum controller_id controller_id;
-+	/* from GPU Tx aka asic_signal */
-+	enum signal_type signal;
-+	/* sink_signal may differ from asicSignal if Translator encoder */
-+	enum signal_type sink_signal;
-+	enum display_output_bit_depth display_output_bit_depth;
-+	bool enable_dp_audio;
-+};
-+
-+struct bp_transmitter_control {
-+	enum bp_transmitter_control_action action;
-+	enum engine_id engine_id;
-+	enum transmitter transmitter; /* PhyId */
-+	enum dc_lane_count lanes_number;
-+	enum clock_source_id pll_id; /* needed for DCE 4.0 */
-+	enum signal_type signal;
-+	enum dc_color_depth color_depth; /* not used for DCE6.0 */
-+	enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */
-+	struct graphics_object_id connector_obj_id;
-+	/* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should
-+	 * be pixel clock * deep_color_ratio (in KHz)
-+	 */
-+	uint32_t pixel_clock;
-+	uint32_t lane_select;
-+	uint32_t lane_settings;
-+	bool coherent;
-+	bool multi_path;
-+	bool single_pll_mode;
-+};
-+
-+struct bp_hw_crtc_timing_parameters {
-+	enum controller_id controller_id;
-+	/* horizontal part */
-+	uint32_t h_total;
-+	uint32_t h_addressable;
-+	uint32_t h_overscan_left;
-+	uint32_t h_overscan_right;
-+	uint32_t h_sync_start;
-+	uint32_t h_sync_width;
-+
-+	/* vertical part */
-+	uint32_t v_total;
-+	uint32_t v_addressable;
-+	uint32_t v_overscan_top;
-+	uint32_t v_overscan_bottom;
-+	uint32_t v_sync_start;
-+	uint32_t v_sync_width;
-+
-+	struct timing_flags {
-+		uint32_t INTERLACE:1;
-+		uint32_t PIXEL_REPETITION:4;
-+		uint32_t HSYNC_POSITIVE_POLARITY:1;
-+		uint32_t VSYNC_POSITIVE_POLARITY:1;
-+		uint32_t HORZ_COUNT_BY_TWO:1;
-+	} flags;
-+};
-+
-+struct bp_adjust_pixel_clock_parameters {
-+	/* Input: Signal Type - to be converted to Encoder mode */
-+	enum signal_type signal_type;
-+	/* Input: Encoder object id */
-+	struct graphics_object_id encoder_object_id;
-+	/* Input: Pixel Clock (requested Pixel clock based on Video timing
-+	 * standard used) in KHz
-+	 */
-+	uint32_t pixel_clock;
-+	/* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */
-+	uint32_t adjusted_pixel_clock;
-+	/* Output: If non-zero, this refDiv value should be used to calculate
-+	 * other ppll params */
-+	uint32_t reference_divider;
-+	/* Output: If non-zero, this postDiv value should be used to calculate
-+	 * other ppll params */
-+	uint32_t pixel_clock_post_divider;
-+	/* Input: Enable spread spectrum */
-+	bool ss_enable;
-+};
-+
-+struct bp_pixel_clock_parameters {
-+	enum controller_id controller_id; /* (Which CRTC uses this PLL) */
-+	enum clock_source_id pll_id; /* Clock Source Id */
-+	/* signal_type -> Encoder Mode - needed by VBIOS Exec table */
-+	enum signal_type signal_type;
-+	/* Adjusted Pixel Clock (after VBIOS exec table)
-+	 * that becomes Target Pixel Clock (KHz) */
-+	uint32_t target_pixel_clock;
-+	/* Calculated Reference divider of Display PLL */
-+	uint32_t reference_divider;
-+	/* Calculated Feedback divider of Display PLL */
-+	uint32_t feedback_divider;
-+	/* Calculated Fractional Feedback divider of Display PLL */
-+	uint32_t fractional_feedback_divider;
-+	/* Calculated Pixel Clock Post divider of Display PLL */
-+	uint32_t pixel_clock_post_divider;
-+	struct graphics_object_id encoder_object_id; /* Encoder object id */
-+	/* VBIOS returns a fixed display clock when DFS-bypass feature
-+	 * is enabled (KHz) */
-+	uint32_t dfs_bypass_display_clock;
-+	/* color depth to support HDMI deep color */
-+	enum transmitter_color_depth color_depth;
-+
-+	struct program_pixel_clock_flags {
-+		uint32_t FORCE_PROGRAMMING_OF_PLL:1;
-+		/* Use Engine Clock as source for Display Clock when
-+		 * programming PLL */
-+		uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1;
-+		/* Use external reference clock (refDivSrc for PLL) */
-+		uint32_t SET_EXTERNAL_REF_DIV_SRC:1;
-+		/* Force program PHY PLL only */
-+		uint32_t PROGRAM_PHY_PLL_ONLY:1;
-+		/* Support for YUV420 */
-+		uint32_t SUPPORT_YUV_420:1;
-+		/* Use XTALIN reference clock source */
-+		uint32_t SET_XTALIN_REF_SRC:1;
-+		/* Use GENLK reference clock source */
-+		uint32_t SET_GENLOCK_REF_DIV_SRC:1;
-+	} flags;
-+};
-+
-+enum bp_dce_clock_type {
-+	DCECLOCK_TYPE_DISPLAY_CLOCK = 0,
-+	DCECLOCK_TYPE_DPREFCLK      = 1
-+};
-+
-+/* DCE Clock Parameters structure for SetDceClock Exec command table */
-+struct bp_set_dce_clock_parameters {
-+	enum clock_source_id pll_id; /* Clock Source Id */
-+	/* Display clock or DPREFCLK value */
-+	uint32_t target_clock_frequency;
-+	/* Clock to set: =0: DISPCLK  =1: DPREFCLK  =2: PIXCLK */
-+	enum bp_dce_clock_type clock_type;
-+
-+	struct set_dce_clock_flags {
-+		uint32_t USE_GENERICA_AS_SOURCE_FOR_DPREFCLK:1;
-+		/* Use XTALIN reference clock source */
-+		uint32_t USE_XTALIN_AS_SOURCE_FOR_DPREFCLK:1;
-+		/* Use PCIE reference clock source */
-+		uint32_t USE_PCIE_AS_SOURCE_FOR_DPREFCLK:1;
-+		/* Use GENLK reference clock source */
-+		uint32_t USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK:1;
-+	} flags;
-+};
-+
-+struct spread_spectrum_flags {
-+	/* 1 = Center Spread; 0 = down spread */
-+	uint32_t CENTER_SPREAD:1;
-+	/* 1 = external; 0 = internal */
-+	uint32_t EXTERNAL_SS:1;
-+	/* 1 = delta-sigma type parameter; 0 = ver1 */
-+	uint32_t DS_TYPE:1;
-+};
-+
-+struct bp_spread_spectrum_parameters {
-+	enum clock_source_id pll_id;
-+	uint32_t percentage;
-+	uint32_t ds_frac_amount;
-+
-+	union {
-+		struct {
-+			uint32_t step;
-+			uint32_t delay;
-+			uint32_t range; /* In Hz unit */
-+		} ver1;
-+		struct {
-+			uint32_t feedback_amount;
-+			uint32_t nfrac_amount;
-+			uint32_t ds_frac_size;
-+		} ds;
-+	};
-+
-+	struct spread_spectrum_flags flags;
-+};
-+
-+struct bp_encoder_cap_info {
-+	uint32_t DP_HBR2_CAP:1;
-+	uint32_t DP_HBR2_EN:1;
-+	uint32_t DP_HBR3_EN:1;
-+	uint32_t HDMI_6GB_EN:1;
-+	uint32_t RESERVED:30;
-+};
-+
-+#endif /*__DAL_BIOS_PARSER_TYPES_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/include/dal_asic_id.h.0130~	2017-12-14 06:39:58.440903585 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/dal_asic_id.h	2017-12-14 06:39:58.440903585 +0100
-@@ -0,0 +1,143 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_ASIC_ID_H__
-+#define __DAL_ASIC_ID_H__
-+
-+/*
-+ * ASIC internal revision ID
-+ */
-+
-+/* DCE80 (based on ci_id.h in Perforce) */
-+#define	CI_BONAIRE_M_A0 0x14
-+#define	CI_BONAIRE_M_A1	0x15
-+#define	CI_HAWAII_P_A0	0x28
-+
-+#define CI_UNKNOWN	0xFF
-+
-+#define ASIC_REV_IS_BONAIRE_M(rev) \
-+	((rev >= CI_BONAIRE_M_A0) && (rev < CI_HAWAII_P_A0))
-+
-+#define ASIC_REV_IS_HAWAII_P(rev) \
-+	(rev >= CI_HAWAII_P_A0)
-+
-+/* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
-+#define KV_SPECTRE_A0 0x01
-+
-+/* KV2 with Spooky GFX core, including downgraded from Spectre core,
-+ * 3-4-1-1 (CU-Pix-Primitive-RB) */
-+#define KV_SPOOKY_A0 0x41
-+
-+/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
-+#define KB_KALINDI_A0 0x81
-+
-+/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
-+#define KB_KALINDI_A1 0x82
-+
-+/* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
-+#define BV_KALINDI_A2 0x85
-+
-+/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
-+#define ML_GODAVARI_A0 0xA1
-+
-+/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
-+#define ML_GODAVARI_A1 0xA2
-+
-+#define KV_UNKNOWN 0xFF
-+
-+#define ASIC_REV_IS_KALINDI(rev) \
-+	((rev >= KB_KALINDI_A0) && (rev < KV_UNKNOWN))
-+
-+#define ASIC_REV_IS_BHAVANI(rev) \
-+	((rev >= BV_KALINDI_A2) && (rev < ML_GODAVARI_A0))
-+
-+#define ASIC_REV_IS_GODAVARI(rev) \
-+	((rev >= ML_GODAVARI_A0) && (rev < KV_UNKNOWN))
-+
-+/* VI Family */
-+/* DCE10 */
-+#define VI_TONGA_P_A0 20
-+#define VI_TONGA_P_A1 21
-+#define VI_FIJI_P_A0 60
-+
-+/* DCE112 */
-+#define VI_POLARIS10_P_A0 80
-+#define VI_POLARIS11_M_A0 90
-+#define VI_POLARIS12_V_A0 100
-+
-+#define VI_UNKNOWN 0xFF
-+
-+#define ASIC_REV_IS_TONGA_P(eChipRev) ((eChipRev >= VI_TONGA_P_A0) && \
-+		(eChipRev < 40))
-+#define ASIC_REV_IS_FIJI_P(eChipRev) ((eChipRev >= VI_FIJI_P_A0) && \
-+		(eChipRev < 80))
-+
-+#define ASIC_REV_IS_POLARIS10_P(eChipRev) ((eChipRev >= VI_POLARIS10_P_A0) && \
-+		(eChipRev < VI_POLARIS11_M_A0))
-+#define ASIC_REV_IS_POLARIS11_M(eChipRev) ((eChipRev >= VI_POLARIS11_M_A0) &&  \
-+		(eChipRev < VI_POLARIS12_V_A0))
-+#define ASIC_REV_IS_POLARIS12_V(eChipRev) (eChipRev >= VI_POLARIS12_V_A0)
-+
-+/* DCE11 */
-+#define CZ_CARRIZO_A0 0x01
-+
-+#define STONEY_A0 0x61
-+#define CZ_UNKNOWN 0xFF
-+
-+#define ASIC_REV_IS_STONEY(rev) \
-+	((rev >= STONEY_A0) && (rev < CZ_UNKNOWN))
-+
-+/* DCN1_0 */
-+#define INTERNAL_REV_RAVEN_A0             0x00    /* First spin of Raven */
-+#define RAVEN_A0 0x01
-+#define RAVEN_B0 0x21
-+#define RAVEN_UNKNOWN 0xFF
-+
-+#define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
-+#define RAVEN1_F0 0xF0
-+#define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
-+
-+
-+#define FAMILY_RV 142 /* DCN 1*/
-+
-+/*
-+ * ASIC chip ID
-+ */
-+/* DCE80 */
-+#define DEVICE_ID_KALINDI_9834 0x9834
-+#define DEVICE_ID_TEMASH_9839 0x9839
-+#define DEVICE_ID_TEMASH_983D 0x983D
-+
-+/* Asic Family IDs for different asic family. */
-+#define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
-+#define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
-+#define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
-+#define FAMILY_CZ 135 /* Carrizo */
-+
-+#define FAMILY_AI 141
-+
-+#define	FAMILY_UNKNOWN 0xFF
-+
-+#endif /* __DAL_ASIC_ID_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/include/dal_types.h.0130~	2017-12-14 06:39:58.440903585 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/dal_types.h	2017-12-14 06:39:58.440903585 +0100
-@@ -0,0 +1,49 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_TYPES_H__
-+#define __DAL_TYPES_H__
-+
-+#include "signal_types.h"
-+#include "dc_types.h"
-+
-+struct dal_logger;
-+struct dc_bios;
-+
-+enum dce_version {
-+	DCE_VERSION_UNKNOWN = (-1),
-+	DCE_VERSION_8_0,
-+	DCE_VERSION_8_1,
-+	DCE_VERSION_8_3,
-+	DCE_VERSION_10_0,
-+	DCE_VERSION_11_0,
-+	DCE_VERSION_11_2,
-+	DCE_VERSION_12_0,
-+	DCE_VERSION_MAX,
-+	DCN_VERSION_1_0,
-+	DCN_VERSION_MAX
-+};
-+
-+#endif /* __DAL_TYPES_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/include/ddc_service_types.h.0130~	2017-12-14 06:39:58.440903585 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/ddc_service_types.h	2017-12-14 06:39:58.440903585 +0100
-@@ -0,0 +1,121 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+#ifndef __DAL_DDC_SERVICE_TYPES_H__
-+#define __DAL_DDC_SERVICE_TYPES_H__
-+
-+#define DP_BRANCH_DEVICE_ID_1 0x0010FA
-+#define DP_BRANCH_DEVICE_ID_2 0x0022B9
-+#define DP_BRANCH_DEVICE_ID_3 0x00001A
-+#define DP_BRANCH_DEVICE_ID_4 0x0080e1
-+
-+enum ddc_result {
-+	DDC_RESULT_UNKNOWN = 0,
-+	DDC_RESULT_SUCESSFULL,
-+	DDC_RESULT_FAILED_CHANNEL_BUSY,
-+	DDC_RESULT_FAILED_TIMEOUT,
-+	DDC_RESULT_FAILED_PROTOCOL_ERROR,
-+	DDC_RESULT_FAILED_NACK,
-+	DDC_RESULT_FAILED_INCOMPLETE,
-+	DDC_RESULT_FAILED_OPERATION,
-+	DDC_RESULT_FAILED_INVALID_OPERATION,
-+	DDC_RESULT_FAILED_BUFFER_OVERFLOW
-+};
-+
-+enum ddc_service_type {
-+	DDC_SERVICE_TYPE_CONNECTOR,
-+	DDC_SERVICE_TYPE_DISPLAY_PORT_MST,
-+};
-+
-+/**
-+ * display sink capability
-+ */
-+struct display_sink_capability {
-+	/* dongle type (DP converter, CV smart dongle) */
-+	enum display_dongle_type dongle_type;
-+
-+	/**********************************************************
-+	 capabilities going INTO SINK DEVICE (stream capabilities)
-+	 **********************************************************/
-+	/* Dongle's downstream count. */
-+	uint32_t downstrm_sink_count;
-+	/* Is dongle's downstream count info field (downstrm_sink_count)
-+	 * valid. */
-+	bool downstrm_sink_count_valid;
-+
-+	/* Maximum additional audio delay in microsecond (us) */
-+	uint32_t additional_audio_delay;
-+	/* Audio latency value in microsecond (us) */
-+	uint32_t audio_latency;
-+	/* Interlace video latency value in microsecond (us) */
-+	uint32_t video_latency_interlace;
-+	/* Progressive video latency value in microsecond (us) */
-+	uint32_t video_latency_progressive;
-+	/* Dongle caps: Maximum pixel clock supported over dongle for HDMI */
-+	uint32_t max_hdmi_pixel_clock;
-+	/* Dongle caps: Maximum deep color supported over dongle for HDMI */
-+	enum dc_color_depth max_hdmi_deep_color;
-+
-+	/************************************************************
-+	 capabilities going OUT OF SOURCE DEVICE (link capabilities)
-+	 ************************************************************/
-+	/* support for Spread Spectrum(SS) */
-+	bool ss_supported;
-+	/* DP link settings (laneCount, linkRate, Spread) */
-+	uint32_t dp_link_lane_count;
-+	uint32_t dp_link_rate;
-+	uint32_t dp_link_spead;
-+
-+	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
-+	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
-+	bool is_dp_hdmi_s3d_converter;
-+	/* to check if we have queried the display capability
-+	 * for eDP panel already. */
-+	bool is_edp_sink_cap_valid;
-+
-+	enum ddc_transaction_type transaction_type;
-+	enum signal_type signal;
-+};
-+
-+struct av_sync_data {
-+	uint8_t av_granularity;/* DPCD 00023h */
-+	uint8_t aud_dec_lat1;/* DPCD 00024h */
-+	uint8_t aud_dec_lat2;/* DPCD 00025h */
-+	uint8_t aud_pp_lat1;/* DPCD 00026h */
-+	uint8_t aud_pp_lat2;/* DPCD 00027h */
-+	uint8_t vid_inter_lat;/* DPCD 00028h */
-+	uint8_t vid_prog_lat;/* DPCD 00029h */
-+	uint8_t aud_del_ins1;/* DPCD 0002Bh */
-+	uint8_t aud_del_ins2;/* DPCD 0002Ch */
-+	uint8_t aud_del_ins3;/* DPCD 0002Dh */
-+};
-+
-+/*Travis*/
-+static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
-+/*Nutmeg*/
-+static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
-+/*DP to Dual link DVI converter*/
-+static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
-+
-+#endif /* __DAL_DDC_SERVICE_TYPES_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/include/dpcd_defs.h.0130~	2017-12-14 06:39:58.440903585 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/dpcd_defs.h	2017-12-14 06:39:58.440903585 +0100
-@@ -0,0 +1,149 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_DPCD_DEFS_H__
-+#define __DAL_DPCD_DEFS_H__
-+
-+#include <drm/drm_dp_helper.h>
-+
-+enum dpcd_revision {
-+	DPCD_REV_10 = 0x10,
-+	DPCD_REV_11 = 0x11,
-+	DPCD_REV_12 = 0x12,
-+	DPCD_REV_13 = 0x13,
-+	DPCD_REV_14 = 0x14
-+};
-+
-+/* these are the types stored at DOWNSTREAMPORT_PRESENT */
-+enum dpcd_downstream_port_type {
-+	DOWNSTREAM_DP = 0,
-+	DOWNSTREAM_VGA,
-+	DOWNSTREAM_DVI_HDMI,
-+	DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */
-+};
-+
-+enum dpcd_link_test_patterns {
-+	LINK_TEST_PATTERN_NONE = 0,
-+	LINK_TEST_PATTERN_COLOR_RAMP,
-+	LINK_TEST_PATTERN_VERTICAL_BARS,
-+	LINK_TEST_PATTERN_COLOR_SQUARES
-+};
-+
-+enum dpcd_test_color_format {
-+	TEST_COLOR_FORMAT_RGB = 0,
-+	TEST_COLOR_FORMAT_YCBCR422,
-+	TEST_COLOR_FORMAT_YCBCR444
-+};
-+
-+enum dpcd_test_bit_depth {
-+	TEST_BIT_DEPTH_6 = 0,
-+	TEST_BIT_DEPTH_8,
-+	TEST_BIT_DEPTH_10,
-+	TEST_BIT_DEPTH_12,
-+	TEST_BIT_DEPTH_16
-+};
-+
-+/* PHY (encoder) test patterns
-+The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248)
-+*/
-+enum dpcd_phy_test_patterns {
-+	PHY_TEST_PATTERN_NONE = 0,
-+	PHY_TEST_PATTERN_D10_2,
-+	PHY_TEST_PATTERN_SYMBOL_ERROR,
-+	PHY_TEST_PATTERN_PRBS7,
-+	PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */
-+	PHY_TEST_PATTERN_CP2520_1,
-+	PHY_TEST_PATTERN_CP2520_2,
-+	PHY_TEST_PATTERN_CP2520_3, /* same as TPS4 */
-+};
-+
-+enum dpcd_test_dyn_range {
-+	TEST_DYN_RANGE_VESA = 0,
-+	TEST_DYN_RANGE_CEA
-+};
-+
-+enum dpcd_audio_test_pattern {
-+	AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */
-+	AUDIO_TEST_PATTERN_SAWTOOTH
-+};
-+
-+enum dpcd_audio_sampling_rate {
-+	AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */
-+	AUDIO_SAMPLING_RATE_44_1KHZ,
-+	AUDIO_SAMPLING_RATE_48KHZ,
-+	AUDIO_SAMPLING_RATE_88_2KHZ,
-+	AUDIO_SAMPLING_RATE_96KHZ,
-+	AUDIO_SAMPLING_RATE_176_4KHZ,
-+	AUDIO_SAMPLING_RATE_192KHZ
-+};
-+
-+enum dpcd_audio_channels {
-+	AUDIO_CHANNELS_1 = 0,/* direct HW translation */
-+	AUDIO_CHANNELS_2,
-+	AUDIO_CHANNELS_3,
-+	AUDIO_CHANNELS_4,
-+	AUDIO_CHANNELS_5,
-+	AUDIO_CHANNELS_6,
-+	AUDIO_CHANNELS_7,
-+	AUDIO_CHANNELS_8,
-+
-+	AUDIO_CHANNELS_COUNT
-+};
-+
-+enum dpcd_audio_test_pattern_periods {
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_3,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_6,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_12,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_24,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_48,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_96,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_192,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_384,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_768,
-+	DPCD_AUDIO_TEST_PATTERN_PERIOD_1536
-+};
-+
-+/* This enum is for programming DPCD TRAINING_PATTERN_SET */
-+enum dpcd_training_patterns {
-+	DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */
-+	DPCD_TRAINING_PATTERN_1,
-+	DPCD_TRAINING_PATTERN_2,
-+	DPCD_TRAINING_PATTERN_3,
-+	DPCD_TRAINING_PATTERN_4 = 7
-+};
-+
-+/* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus
-+It defines the possible PSR states. */
-+enum dpcd_psr_sink_states {
-+	PSR_SINK_STATE_INACTIVE = 0,
-+	PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1,
-+	PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2,
-+	PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3,
-+	PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4,
-+	PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7,
-+};
-+
-+#endif /* __DAL_DPCD_DEFS_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/include/fixed31_32.h.0130~	2017-12-14 06:39:58.440903585 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/fixed31_32.h	2017-12-14 06:39:58.440903585 +0100
-@@ -0,0 +1,466 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_FIXED31_32_H__
-+#define __DAL_FIXED31_32_H__
-+
-+#include "os_types.h"
-+
-+#define FIXED31_32_BITS_PER_FRACTIONAL_PART 32
-+
-+/*
-+ * @brief
-+ * Arithmetic operations on real numbers
-+ * represented as fixed-point numbers.
-+ * There are: 1 bit for sign,
-+ * 31 bit for integer part,
-+ * 32 bits for fractional part.
-+ *
-+ * @note
-+ * Currently, overflows and underflows are asserted;
-+ * no special result returned.
-+ */
-+
-+struct fixed31_32 {
-+	int64_t value;
-+};
-+
-+/*
-+ * @brief
-+ * Useful constants
-+ */
-+
-+static const struct fixed31_32 dal_fixed31_32_zero = { 0 };
-+static const struct fixed31_32 dal_fixed31_32_epsilon = { 1LL };
-+static const struct fixed31_32 dal_fixed31_32_half = { 0x80000000LL };
-+static const struct fixed31_32 dal_fixed31_32_one = { 0x100000000LL };
-+
-+static const struct fixed31_32 dal_fixed31_32_pi = { 13493037705LL };
-+static const struct fixed31_32 dal_fixed31_32_two_pi = { 26986075409LL };
-+static const struct fixed31_32 dal_fixed31_32_e = { 11674931555LL };
-+static const struct fixed31_32 dal_fixed31_32_ln2 = { 2977044471LL };
-+static const struct fixed31_32 dal_fixed31_32_ln2_div_2 = { 1488522236LL };
-+
-+/*
-+ * @brief
-+ * Initialization routines
-+ */
-+
-+/*
-+ * @brief
-+ * result = numerator / denominator
-+ */
-+struct fixed31_32 dal_fixed31_32_from_fraction(
-+	int64_t numerator,
-+	int64_t denominator);
-+
-+/*
-+ * @brief
-+ * result = arg
-+ */
-+struct fixed31_32 dal_fixed31_32_from_int_nonconst(int64_t arg);
-+static inline struct fixed31_32 dal_fixed31_32_from_int(int64_t arg)
-+{
-+	if (__builtin_constant_p(arg)) {
-+		struct fixed31_32 res;
-+		BUILD_BUG_ON((LONG_MIN > arg) || (arg > LONG_MAX));
-+		res.value = arg << FIXED31_32_BITS_PER_FRACTIONAL_PART;
-+		return res;
-+	} else
-+		return dal_fixed31_32_from_int_nonconst(arg);
-+}
-+
-+/*
-+ * @brief
-+ * Unary operators
-+ */
-+
-+/*
-+ * @brief
-+ * result = -arg
-+ */
-+static inline struct fixed31_32 dal_fixed31_32_neg(struct fixed31_32 arg)
-+{
-+	struct fixed31_32 res;
-+
-+	res.value = -arg.value;
-+
-+	return res;
-+}
-+
-+/*
-+ * @brief
-+ * result = abs(arg) := (arg >= 0) ? arg : -arg
-+ */
-+static inline struct fixed31_32 dal_fixed31_32_abs(struct fixed31_32 arg)
-+{
-+	if (arg.value < 0)
-+		return dal_fixed31_32_neg(arg);
-+	else
-+		return arg;
-+}
-+
-+/*
-+ * @brief
-+ * Binary relational operators
-+ */
-+
-+/*
-+ * @brief
-+ * result = arg1 < arg2
-+ */
-+static inline bool dal_fixed31_32_lt(struct fixed31_32 arg1,
-+				     struct fixed31_32 arg2)
-+{
-+	return arg1.value < arg2.value;
-+}
-+
-+/*
-+ * @brief
-+ * result = arg1 <= arg2
-+ */
-+static inline bool dal_fixed31_32_le(struct fixed31_32 arg1,
-+				     struct fixed31_32 arg2)
-+{
-+	return arg1.value <= arg2.value;
-+}
-+
-+/*
-+ * @brief
-+ * result = arg1 == arg2
-+ */
-+static inline bool dal_fixed31_32_eq(struct fixed31_32 arg1,
-+				     struct fixed31_32 arg2)
-+{
-+	return arg1.value == arg2.value;
-+}
-+
-+/*
-+ * @brief
-+ * result = min(arg1, arg2) := (arg1 <= arg2) ? arg1 : arg2
-+ */
-+static inline struct fixed31_32 dal_fixed31_32_min(struct fixed31_32 arg1,
-+						   struct fixed31_32 arg2)
-+{
-+	if (arg1.value <= arg2.value)
-+		return arg1;
-+	else
-+		return arg2;
-+}
-+
-+/*
-+ * @brief
-+ * result = max(arg1, arg2) := (arg1 <= arg2) ? arg2 : arg1
-+ */
-+static inline struct fixed31_32 dal_fixed31_32_max(struct fixed31_32 arg1,
-+						   struct fixed31_32 arg2)
-+{
-+	if (arg1.value <= arg2.value)
-+		return arg2;
-+	else
-+		return arg1;
-+}
-+
-+/*
-+ * @brief
-+ *          | min_value, when arg <= min_value
-+ * result = | arg, when min_value < arg < max_value
-+ *          | max_value, when arg >= max_value
-+ */
-+static inline struct fixed31_32 dal_fixed31_32_clamp(
-+	struct fixed31_32 arg,
-+	struct fixed31_32 min_value,
-+	struct fixed31_32 max_value)
-+{
-+	if (dal_fixed31_32_le(arg, min_value))
-+		return min_value;
-+	else if (dal_fixed31_32_le(max_value, arg))
-+		return max_value;
-+	else
-+		return arg;
-+}
-+
-+/*
-+ * @brief
-+ * Binary shift operators
-+ */
-+
-+/*
-+ * @brief
-+ * result = arg << shift
-+ */
-+struct fixed31_32 dal_fixed31_32_shl(
-+	struct fixed31_32 arg,
-+	uint8_t shift);
-+
-+/*
-+ * @brief
-+ * result = arg >> shift
-+ */
-+static inline struct fixed31_32 dal_fixed31_32_shr(
-+	struct fixed31_32 arg,
-+	uint8_t shift)
-+{
-+	struct fixed31_32 res;
-+	res.value = arg.value >> shift;
-+	return res;
-+}
-+
-+/*
-+ * @brief
-+ * Binary additive operators
-+ */
-+
-+/*
-+ * @brief
-+ * result = arg1 + arg2
-+ */
-+struct fixed31_32 dal_fixed31_32_add(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2);
-+
-+/*
-+ * @brief
-+ * result = arg1 + arg2
-+ */
-+static inline struct fixed31_32 dal_fixed31_32_add_int(struct fixed31_32 arg1,
-+						       int32_t arg2)
-+{
-+	return dal_fixed31_32_add(arg1,
-+				  dal_fixed31_32_from_int(arg2));
-+}
-+
-+/*
-+ * @brief
-+ * result = arg1 - arg2
-+ */
-+struct fixed31_32 dal_fixed31_32_sub(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2);
-+
-+/*
-+ * @brief
-+ * result = arg1 - arg2
-+ */
-+static inline struct fixed31_32 dal_fixed31_32_sub_int(struct fixed31_32 arg1,
-+						       int32_t arg2)
-+{
-+	return dal_fixed31_32_sub(arg1,
-+				  dal_fixed31_32_from_int(arg2));
-+}
-+
-+
-+/*
-+ * @brief
-+ * Binary multiplicative operators
-+ */
-+
-+/*
-+ * @brief
-+ * result = arg1 * arg2
-+ */
-+struct fixed31_32 dal_fixed31_32_mul(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2);
-+
-+
-+/*
-+ * @brief
-+ * result = arg1 * arg2
-+ */
-+static inline struct fixed31_32 dal_fixed31_32_mul_int(struct fixed31_32 arg1,
-+						       int32_t arg2)
-+{
-+	return dal_fixed31_32_mul(arg1,
-+				  dal_fixed31_32_from_int(arg2));
-+}
-+
-+/*
-+ * @brief
-+ * result = square(arg) := arg * arg
-+ */
-+struct fixed31_32 dal_fixed31_32_sqr(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * result = arg1 / arg2
-+ */
-+static inline struct fixed31_32 dal_fixed31_32_div_int(struct fixed31_32 arg1,
-+						       int64_t arg2)
-+{
-+	return dal_fixed31_32_from_fraction(arg1.value,
-+					    dal_fixed31_32_from_int(arg2).value);
-+}
-+
-+/*
-+ * @brief
-+ * result = arg1 / arg2
-+ */
-+static inline struct fixed31_32 dal_fixed31_32_div(struct fixed31_32 arg1,
-+						   struct fixed31_32 arg2)
-+{
-+	return dal_fixed31_32_from_fraction(arg1.value,
-+					    arg2.value);
-+}
-+
-+/*
-+ * @brief
-+ * Reciprocal function
-+ */
-+
-+/*
-+ * @brief
-+ * result = reciprocal(arg) := 1 / arg
-+ *
-+ * @note
-+ * No special actions taken in case argument is zero.
-+ */
-+struct fixed31_32 dal_fixed31_32_recip(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * Trigonometric functions
-+ */
-+
-+/*
-+ * @brief
-+ * result = sinc(arg) := sin(arg) / arg
-+ *
-+ * @note
-+ * Argument specified in radians,
-+ * internally it's normalized to [-2pi...2pi] range.
-+ */
-+struct fixed31_32 dal_fixed31_32_sinc(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * result = sin(arg)
-+ *
-+ * @note
-+ * Argument specified in radians,
-+ * internally it's normalized to [-2pi...2pi] range.
-+ */
-+struct fixed31_32 dal_fixed31_32_sin(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * result = cos(arg)
-+ *
-+ * @note
-+ * Argument specified in radians
-+ * and should be in [-2pi...2pi] range -
-+ * passing arguments outside that range
-+ * will cause incorrect result!
-+ */
-+struct fixed31_32 dal_fixed31_32_cos(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * Transcendent functions
-+ */
-+
-+/*
-+ * @brief
-+ * result = exp(arg)
-+ *
-+ * @note
-+ * Currently, function is verified for abs(arg) <= 1.
-+ */
-+struct fixed31_32 dal_fixed31_32_exp(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * result = log(arg)
-+ *
-+ * @note
-+ * Currently, abs(arg) should be less than 1.
-+ * No normalization is done.
-+ * Currently, no special actions taken
-+ * in case of invalid argument(s). Take care!
-+ */
-+struct fixed31_32 dal_fixed31_32_log(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * Power function
-+ */
-+
-+/*
-+ * @brief
-+ * result = pow(arg1, arg2)
-+ *
-+ * @note
-+ * Currently, abs(arg1) should be less than 1. Take care!
-+ */
-+struct fixed31_32 dal_fixed31_32_pow(
-+	struct fixed31_32 arg1,
-+	struct fixed31_32 arg2);
-+
-+/*
-+ * @brief
-+ * Rounding functions
-+ */
-+
-+/*
-+ * @brief
-+ * result = floor(arg) := greatest integer lower than or equal to arg
-+ */
-+int32_t dal_fixed31_32_floor(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * result = round(arg) := integer nearest to arg
-+ */
-+int32_t dal_fixed31_32_round(
-+	struct fixed31_32 arg);
-+
-+/*
-+ * @brief
-+ * result = ceil(arg) := lowest integer greater than or equal to arg
-+ */
-+int32_t dal_fixed31_32_ceil(
-+	struct fixed31_32 arg);
-+
-+/* the following two function are used in scaler hw programming to convert fixed
-+ * point value to format 2 bits from integer part and 19 bits from fractional
-+ * part. The same applies for u0d19, 0 bits from integer part and 19 bits from
-+ * fractional
-+ */
-+
-+uint32_t dal_fixed31_32_u2d19(
-+	struct fixed31_32 arg);
-+
-+uint32_t dal_fixed31_32_u0d19(
-+	struct fixed31_32 arg);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/include/fixed32_32.h.0130~	2017-12-14 06:39:58.440903585 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/fixed32_32.h	2017-12-14 06:39:58.440903585 +0100
-@@ -0,0 +1,129 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+
-+#ifndef __DAL_FIXED32_32_H__
-+#define __DAL_FIXED32_32_H__
-+
-+#include "os_types.h"
-+
-+struct fixed32_32 {
-+	uint64_t value;
-+};
-+
-+static const struct fixed32_32 dal_fixed32_32_zero = { 0 };
-+static const struct fixed32_32 dal_fixed32_32_one = { 0x100000000LL };
-+static const struct fixed32_32 dal_fixed32_32_half = { 0x80000000LL };
-+
-+struct fixed32_32 dal_fixed32_32_from_fraction(uint32_t n, uint32_t d);
-+static inline struct fixed32_32 dal_fixed32_32_from_int(uint32_t value)
-+{
-+	struct fixed32_32 fx;
-+
-+	fx.value = (uint64_t)value<<32;
-+	return fx;
-+}
-+
-+struct fixed32_32 dal_fixed32_32_add(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs);
-+struct fixed32_32 dal_fixed32_32_add_int(
-+	struct fixed32_32 lhs,
-+	uint32_t rhs);
-+struct fixed32_32 dal_fixed32_32_sub(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs);
-+struct fixed32_32 dal_fixed32_32_sub_int(
-+	struct fixed32_32 lhs,
-+	uint32_t rhs);
-+struct fixed32_32 dal_fixed32_32_mul(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs);
-+struct fixed32_32 dal_fixed32_32_mul_int(
-+	struct fixed32_32 lhs,
-+	uint32_t rhs);
-+struct fixed32_32 dal_fixed32_32_div(
-+	struct fixed32_32 lhs,
-+	struct fixed32_32 rhs);
-+struct fixed32_32 dal_fixed32_32_div_int(
-+	struct fixed32_32 lhs,
-+	uint32_t rhs);
-+
-+static inline struct fixed32_32 dal_fixed32_32_min(struct fixed32_32 lhs,
-+						   struct fixed32_32 rhs)
-+{
-+	return (lhs.value < rhs.value) ? lhs : rhs;
-+}
-+
-+static inline struct fixed32_32 dal_fixed32_32_max(struct fixed32_32 lhs,
-+						   struct fixed32_32 rhs)
-+{
-+	return (lhs.value > rhs.value) ? lhs : rhs;
-+}
-+
-+static inline bool dal_fixed32_32_gt(struct fixed32_32 lhs, struct fixed32_32 rhs)
-+{
-+	return lhs.value > rhs.value;
-+}
-+
-+static inline bool dal_fixed32_32_gt_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+	return lhs.value > ((uint64_t)rhs<<32);
-+}
-+
-+static inline bool dal_fixed32_32_lt(struct fixed32_32 lhs, struct fixed32_32 rhs)
-+{
-+	return lhs.value < rhs.value;
-+}
-+
-+static inline bool dal_fixed32_32_lt_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+	return lhs.value < ((uint64_t)rhs<<32);
-+}
-+
-+static inline bool dal_fixed32_32_le(struct fixed32_32 lhs, struct fixed32_32 rhs)
-+{
-+	return lhs.value <= rhs.value;
-+}
-+
-+static inline bool dal_fixed32_32_le_int(struct fixed32_32 lhs, uint32_t rhs)
-+{
-+	return lhs.value <= ((uint64_t)rhs<<32);
-+}
-+
-+static inline bool dal_fixed32_32_eq(struct fixed32_32 lhs, struct fixed32_32 rhs)
-+{
-+	return lhs.value == rhs.value;
-+}
-+
-+uint32_t dal_fixed32_32_ceil(struct fixed32_32 value);
-+static inline uint32_t dal_fixed32_32_floor(struct fixed32_32 value)
-+{
-+	return value.value>>32;
-+}
-+
-+uint32_t dal_fixed32_32_round(struct fixed32_32 value);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/include/gpio_interface.h.0130~	2017-12-14 06:39:58.440903585 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/gpio_interface.h	2017-12-14 06:39:58.440903585 +0100
-@@ -0,0 +1,92 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GPIO_INTERFACE_H__
-+#define __DAL_GPIO_INTERFACE_H__
-+
-+#include "gpio_types.h"
-+#include "grph_object_defs.h"
-+
-+struct gpio;
-+
-+/* Open the handle for future use */
-+enum gpio_result dal_gpio_open(
-+	struct gpio *gpio,
-+	enum gpio_mode mode);
-+
-+enum gpio_result dal_gpio_open_ex(
-+	struct gpio *gpio,
-+	enum gpio_mode mode);
-+
-+/* Get high or low from the pin */
-+enum gpio_result dal_gpio_get_value(
-+	const struct gpio *gpio,
-+	uint32_t *value);
-+
-+/* Set pin high or low */
-+enum gpio_result dal_gpio_set_value(
-+	const struct gpio *gpio,
-+	uint32_t value);
-+
-+/* Get current mode */
-+enum gpio_mode dal_gpio_get_mode(
-+	const struct gpio *gpio);
-+
-+/* Change mode of the handle */
-+enum gpio_result dal_gpio_change_mode(
-+	struct gpio *gpio,
-+	enum gpio_mode mode);
-+
-+/* Get the GPIO id */
-+enum gpio_id dal_gpio_get_id(
-+	const struct gpio *gpio);
-+
-+/* Get the GPIO enum */
-+uint32_t dal_gpio_get_enum(
-+	const struct gpio *gpio);
-+
-+/* Set the GPIO pin configuration */
-+enum gpio_result dal_gpio_set_config(
-+	struct gpio *gpio,
-+	const struct gpio_config_data *config_data);
-+
-+/* Obtain GPIO pin info */
-+enum gpio_result dal_gpio_get_pin_info(
-+	const struct gpio *gpio,
-+	struct gpio_pin_info *pin_info);
-+
-+/* Obtain GPIO sync source */
-+enum sync_source dal_gpio_get_sync_source(
-+	const struct gpio *gpio);
-+
-+/* Obtain GPIO pin output state (active low or active high) */
-+enum gpio_pin_output_state dal_gpio_get_output_state(
-+	const struct gpio *gpio);
-+
-+/* Close the handle */
-+void dal_gpio_close(
-+	struct gpio *gpio);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/include/gpio_service_interface.h.0130~	2017-12-14 06:39:58.440903585 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/gpio_service_interface.h	2017-12-14 06:39:58.440903585 +0100
-@@ -0,0 +1,105 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GPIO_SERVICE_INTERFACE_H__
-+#define __DAL_GPIO_SERVICE_INTERFACE_H__
-+
-+#include "gpio_types.h"
-+#include "gpio_interface.h"
-+#include "hw/gpio.h"
-+
-+struct gpio_service;
-+
-+struct gpio *dal_gpio_create(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en,
-+	enum gpio_pin_output_state output_state);
-+
-+void dal_gpio_destroy(
-+	struct gpio **ptr);
-+
-+struct gpio_service *dal_gpio_service_create(
-+	enum dce_version dce_version_major,
-+	enum dce_version dce_version_minor,
-+	struct dc_context *ctx);
-+
-+struct gpio *dal_gpio_service_create_irq(
-+	struct gpio_service *service,
-+	uint32_t offset,
-+	uint32_t mask);
-+
-+struct ddc *dal_gpio_create_ddc(
-+	struct gpio_service *service,
-+	uint32_t offset,
-+	uint32_t mask,
-+	struct gpio_ddc_hw_info *info);
-+
-+
-+void dal_gpio_destroy_ddc(
-+	struct ddc **ddc);
-+
-+void dal_gpio_service_destroy(
-+	struct gpio_service **ptr);
-+
-+enum dc_irq_source dal_irq_get_source(
-+	const struct gpio *irq);
-+
-+enum dc_irq_source dal_irq_get_rx_source(
-+	const struct gpio *irq);
-+
-+enum gpio_result dal_irq_setup_hpd_filter(
-+	struct gpio *irq,
-+	struct gpio_hpd_config *config);
-+
-+struct gpio *dal_gpio_create_irq(
-+	struct gpio_service *service,
-+	enum gpio_id id,
-+	uint32_t en);
-+
-+void dal_gpio_destroy_irq(
-+	struct gpio **ptr);
-+
-+
-+enum gpio_result dal_ddc_open(
-+	struct ddc *ddc,
-+	enum gpio_mode mode,
-+	enum gpio_ddc_config_type config_type);
-+
-+enum gpio_result dal_ddc_change_mode(
-+	struct ddc *ddc,
-+	enum gpio_mode mode);
-+
-+enum gpio_ddc_line dal_ddc_get_line(
-+	const struct ddc *ddc);
-+
-+enum gpio_result dal_ddc_set_config(
-+	struct ddc *ddc,
-+	enum gpio_ddc_config_type config_type);
-+
-+void dal_ddc_close(
-+	struct ddc *ddc);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/include/gpio_types.h.0130~	2017-12-14 06:39:58.440903585 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/gpio_types.h	2017-12-14 06:39:58.440903585 +0100
-@@ -0,0 +1,332 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GPIO_TYPES_H__
-+#define __DAL_GPIO_TYPES_H__
-+
-+#define BUNDLE_A_MASK 0x00FFF000L
-+#define BUNDLE_B_MASK 0x00000FFFL
-+
-+/*
-+ * gpio_result
-+ *
-+ * @brief
-+ * The possible return codes that the GPIO object can return.
-+ * These return codes can be generated
-+ * directly by the GPIO object or from the GPIOPin object.
-+ */
-+enum gpio_result {
-+	GPIO_RESULT_OK,
-+	GPIO_RESULT_NULL_HANDLE,
-+	GPIO_RESULT_INVALID_DATA,
-+	GPIO_RESULT_DEVICE_BUSY,
-+	GPIO_RESULT_OPEN_FAILED,
-+	GPIO_RESULT_ALREADY_OPENED,
-+	GPIO_RESULT_NON_SPECIFIC_ERROR
-+};
-+
-+/*
-+ * @brief
-+ * Used to identify the specific GPIO device
-+ *
-+ * @notes
-+ * These constants are used as indices in a vector.
-+ * Thus they should start from zero and be contiguous.
-+ */
-+enum gpio_id {
-+	GPIO_ID_UNKNOWN = (-1),
-+	GPIO_ID_DDC_DATA,
-+	GPIO_ID_DDC_CLOCK,
-+	GPIO_ID_GENERIC,
-+	GPIO_ID_HPD,
-+	GPIO_ID_GPIO_PAD,
-+	GPIO_ID_VIP_PAD,
-+	GPIO_ID_SYNC,
-+	GPIO_ID_GSL, /* global swap lock */
-+	GPIO_ID_COUNT,
-+	GPIO_ID_MIN = GPIO_ID_DDC_DATA,
-+	GPIO_ID_MAX = GPIO_ID_GSL
-+};
-+
-+#define GPIO_ENUM_UNKNOWN \
-+	32
-+
-+struct gpio_pin_info {
-+	uint32_t offset;
-+	uint32_t offset_y;
-+	uint32_t offset_en;
-+	uint32_t offset_mask;
-+
-+	uint32_t mask;
-+	uint32_t mask_y;
-+	uint32_t mask_en;
-+	uint32_t mask_mask;
-+};
-+
-+enum gpio_pin_output_state {
-+	GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW,
-+	GPIO_PIN_OUTPUT_STATE_ACTIVE_HIGH,
-+	GPIO_PIN_OUTPUT_STATE_DEFAULT = GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW
-+};
-+
-+enum gpio_generic {
-+	GPIO_GENERIC_UNKNOWN = (-1),
-+	GPIO_GENERIC_A,
-+	GPIO_GENERIC_B,
-+	GPIO_GENERIC_C,
-+	GPIO_GENERIC_D,
-+	GPIO_GENERIC_E,
-+	GPIO_GENERIC_F,
-+	GPIO_GENERIC_G,
-+	GPIO_GENERIC_COUNT,
-+	GPIO_GENERIC_MIN = GPIO_GENERIC_A,
-+	GPIO_GENERIC_MAX = GPIO_GENERIC_B
-+};
-+
-+enum gpio_hpd {
-+	GPIO_HPD_UNKNOWN = (-1),
-+	GPIO_HPD_1,
-+	GPIO_HPD_2,
-+	GPIO_HPD_3,
-+	GPIO_HPD_4,
-+	GPIO_HPD_5,
-+	GPIO_HPD_6,
-+	GPIO_HPD_COUNT,
-+	GPIO_HPD_MIN = GPIO_HPD_1,
-+	GPIO_HPD_MAX = GPIO_HPD_6
-+};
-+
-+enum gpio_gpio_pad {
-+	GPIO_GPIO_PAD_UNKNOWN = (-1),
-+	GPIO_GPIO_PAD_0,
-+	GPIO_GPIO_PAD_1,
-+	GPIO_GPIO_PAD_2,
-+	GPIO_GPIO_PAD_3,
-+	GPIO_GPIO_PAD_4,
-+	GPIO_GPIO_PAD_5,
-+	GPIO_GPIO_PAD_6,
-+	GPIO_GPIO_PAD_7,
-+	GPIO_GPIO_PAD_8,
-+	GPIO_GPIO_PAD_9,
-+	GPIO_GPIO_PAD_10,
-+	GPIO_GPIO_PAD_11,
-+	GPIO_GPIO_PAD_12,
-+	GPIO_GPIO_PAD_13,
-+	GPIO_GPIO_PAD_14,
-+	GPIO_GPIO_PAD_15,
-+	GPIO_GPIO_PAD_16,
-+	GPIO_GPIO_PAD_17,
-+	GPIO_GPIO_PAD_18,
-+	GPIO_GPIO_PAD_19,
-+	GPIO_GPIO_PAD_20,
-+	GPIO_GPIO_PAD_21,
-+	GPIO_GPIO_PAD_22,
-+	GPIO_GPIO_PAD_23,
-+	GPIO_GPIO_PAD_24,
-+	GPIO_GPIO_PAD_25,
-+	GPIO_GPIO_PAD_26,
-+	GPIO_GPIO_PAD_27,
-+	GPIO_GPIO_PAD_28,
-+	GPIO_GPIO_PAD_29,
-+	GPIO_GPIO_PAD_30,
-+	GPIO_GPIO_PAD_COUNT,
-+	GPIO_GPIO_PAD_MIN = GPIO_GPIO_PAD_0,
-+	GPIO_GPIO_PAD_MAX = GPIO_GPIO_PAD_30
-+};
-+
-+enum gpio_vip_pad {
-+	GPIO_VIP_PAD_UNKNOWN = (-1),
-+	/* following never used -
-+	 * GPIO_ID_DDC_CLOCK::GPIO_DDC_LINE_VIP_PAD defined instead */
-+	GPIO_VIP_PAD_SCL,
-+	/* following never used -
-+	 * GPIO_ID_DDC_DATA::GPIO_DDC_LINE_VIP_PAD defined instead */
-+	GPIO_VIP_PAD_SDA,
-+	GPIO_VIP_PAD_VHAD,
-+	GPIO_VIP_PAD_VPHCTL,
-+	GPIO_VIP_PAD_VIPCLK,
-+	GPIO_VIP_PAD_VID,
-+	GPIO_VIP_PAD_VPCLK0,
-+	GPIO_VIP_PAD_DVALID,
-+	GPIO_VIP_PAD_PSYNC,
-+	GPIO_VIP_PAD_COUNT,
-+	GPIO_VIP_PAD_MIN = GPIO_VIP_PAD_SCL,
-+	GPIO_VIP_PAD_MAX = GPIO_VIP_PAD_PSYNC
-+};
-+
-+enum gpio_sync {
-+	GPIO_SYNC_UNKNOWN = (-1),
-+	GPIO_SYNC_HSYNC_A,
-+	GPIO_SYNC_VSYNC_A,
-+	GPIO_SYNC_HSYNC_B,
-+	GPIO_SYNC_VSYNC_B,
-+	GPIO_SYNC_COUNT,
-+	GPIO_SYNC_MIN = GPIO_SYNC_HSYNC_A,
-+	GPIO_SYNC_MAX = GPIO_SYNC_VSYNC_B
-+};
-+
-+enum gpio_gsl {
-+	GPIO_GSL_UNKNOWN = (-1),
-+	GPIO_GSL_GENLOCK_CLOCK,
-+	GPIO_GSL_GENLOCK_VSYNC,
-+	GPIO_GSL_SWAPLOCK_A,
-+	GPIO_GSL_SWAPLOCK_B,
-+	GPIO_GSL_COUNT,
-+	GPIO_GSL_MIN = GPIO_GSL_GENLOCK_CLOCK,
-+	GPIO_GSL_MAX = GPIO_GSL_SWAPLOCK_B
-+};
-+
-+/*
-+ * @brief
-+ * Unique Id for DDC handle.
-+ * Values are meaningful (used as indexes to array)
-+ */
-+enum gpio_ddc_line {
-+	GPIO_DDC_LINE_UNKNOWN = (-1),
-+	GPIO_DDC_LINE_DDC1,
-+	GPIO_DDC_LINE_DDC2,
-+	GPIO_DDC_LINE_DDC3,
-+	GPIO_DDC_LINE_DDC4,
-+	GPIO_DDC_LINE_DDC5,
-+	GPIO_DDC_LINE_DDC6,
-+	GPIO_DDC_LINE_DDC_VGA,
-+	GPIO_DDC_LINE_VIP_PAD,
-+	GPIO_DDC_LINE_I2C_PAD = GPIO_DDC_LINE_VIP_PAD,
-+	GPIO_DDC_LINE_COUNT,
-+	GPIO_DDC_LINE_MIN = GPIO_DDC_LINE_DDC1,
-+	GPIO_DDC_LINE_MAX = GPIO_DDC_LINE_I2C_PAD
-+};
-+
-+/*
-+ * @brief
-+ * Identifies the mode of operation to open a GPIO device.
-+ * A GPIO device (pin) can be programmed in only one of these modes at a time.
-+ */
-+enum gpio_mode {
-+	GPIO_MODE_UNKNOWN = (-1),
-+	GPIO_MODE_INPUT,
-+	GPIO_MODE_OUTPUT,
-+	GPIO_MODE_FAST_OUTPUT,
-+	GPIO_MODE_HARDWARE,
-+	GPIO_MODE_INTERRUPT
-+};
-+
-+/*
-+ * @brief
-+ * Identifies the source of the signal when GPIO is in HW mode.
-+ * get_signal_source() will return GPIO_SYGNAL_SOURCE__UNKNOWN
-+ * when one of the following holds:
-+ *    1. GPIO is input GPIO
-+ *    2. GPIO is not opened in HW mode
-+ *    3. GPIO does not have fixed signal source
-+ *    (like DC_GenericA have mux instead fixed)
-+ */
-+enum gpio_signal_source {
-+	GPIO_SIGNAL_SOURCE_UNKNOWN = (-1),
-+	GPIO_SIGNAL_SOURCE_DACA_STEREO_SYNC,
-+	GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC,
-+	GPIO_SIGNAL_SOURCE_DACB_STEREO_SYNC,
-+	GPIO_SIGNAL_SOURCE_DACA_HSYNC,
-+	GPIO_SIGNAL_SOURCE_DACB_HSYNC,
-+	GPIO_SIGNAL_SOURCE_DACA_VSYNC,
-+	GPIO_SIGNAL_SOURCE_DACB_VSYNC,
-+};
-+
-+enum gpio_stereo_source {
-+	GPIO_STEREO_SOURCE_UNKNOWN = (-1),
-+	GPIO_STEREO_SOURCE_D1,
-+	GPIO_STEREO_SOURCE_D2,
-+	GPIO_STEREO_SOURCE_D3,
-+	GPIO_STEREO_SOURCE_D4,
-+	GPIO_STEREO_SOURCE_D5,
-+	GPIO_STEREO_SOURCE_D6
-+};
-+
-+/*
-+ * GPIO config
-+ */
-+
-+enum gpio_config_type {
-+	GPIO_CONFIG_TYPE_NONE,
-+	GPIO_CONFIG_TYPE_DDC,
-+	GPIO_CONFIG_TYPE_HPD,
-+	GPIO_CONFIG_TYPE_GENERIC_MUX,
-+	GPIO_CONFIG_TYPE_GSL_MUX,
-+	GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE
-+};
-+
-+/* DDC configuration */
-+
-+enum gpio_ddc_config_type {
-+	GPIO_DDC_CONFIG_TYPE_MODE_AUX,
-+	GPIO_DDC_CONFIG_TYPE_MODE_I2C,
-+	GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT,
-+	GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT,
-+	GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING
-+};
-+
-+struct gpio_ddc_config {
-+	enum gpio_ddc_config_type type;
-+	bool data_en_bit_present;
-+	bool clock_en_bit_present;
-+};
-+
-+/* HPD configuration */
-+
-+struct gpio_hpd_config {
-+	uint32_t delay_on_connect; /* milliseconds */
-+	uint32_t delay_on_disconnect; /* milliseconds */
-+};
-+
-+struct gpio_generic_mux_config {
-+	bool enable_output_from_mux;
-+	enum gpio_signal_source mux_select;
-+	enum gpio_stereo_source stereo_select;
-+};
-+
-+enum gpio_gsl_mux_config_type {
-+	GPIO_GSL_MUX_CONFIG_TYPE_DISABLE,
-+	GPIO_GSL_MUX_CONFIG_TYPE_TIMING_SYNC,
-+	GPIO_GSL_MUX_CONFIG_TYPE_FLIP_SYNC
-+};
-+
-+struct gpio_gsl_mux_config {
-+	enum gpio_gsl_mux_config_type type;
-+	/* Actually sync_source type,
-+	 * however we want to avoid inter-component includes here */
-+	uint32_t gsl_group;
-+};
-+
-+struct gpio_config_data {
-+	enum gpio_config_type type;
-+	union {
-+		struct gpio_ddc_config ddc;
-+		struct gpio_hpd_config hpd;
-+		struct gpio_generic_mux_config generic_mux;
-+		struct gpio_gsl_mux_config gsl_mux;
-+	} config;
-+};
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h.0130~	2017-12-14 06:39:58.440903585 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h	2017-12-14 06:39:58.440903585 +0100
-@@ -0,0 +1,445 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GRPH_OBJECT_CTRL_DEFS_H__
-+#define __DAL_GRPH_OBJECT_CTRL_DEFS_H__
-+
-+#include "grph_object_defs.h"
-+
-+/*
-+ * #####################################################
-+ * #####################################################
-+ *
-+ * These defines shared between asic_control/bios_parser and other
-+ * DAL components
-+ *
-+ * #####################################################
-+ * #####################################################
-+ */
-+
-+enum display_output_bit_depth {
-+	PANEL_UNDEFINE = 0,
-+	PANEL_6BIT_COLOR = 1,
-+	PANEL_8BIT_COLOR = 2,
-+	PANEL_10BIT_COLOR = 3,
-+	PANEL_12BIT_COLOR = 4,
-+	PANEL_16BIT_COLOR = 5,
-+};
-+
-+
-+/* Device type as abstracted by ATOM BIOS */
-+enum dal_device_type {
-+	DEVICE_TYPE_UNKNOWN = 0,
-+	DEVICE_TYPE_LCD,
-+	DEVICE_TYPE_CRT,
-+	DEVICE_TYPE_DFP,
-+	DEVICE_TYPE_CV,
-+	DEVICE_TYPE_TV,
-+	DEVICE_TYPE_CF,
-+	DEVICE_TYPE_WIRELESS
-+};
-+
-+/* Device ID as abstracted by ATOM BIOS */
-+struct device_id {
-+	enum dal_device_type device_type:16;
-+	uint32_t enum_id:16;	/* 1 based enum */
-+	uint16_t raw_device_tag;
-+};
-+
-+struct graphics_object_i2c_info {
-+	struct gpio_info {
-+		uint32_t clk_mask_register_index;
-+		uint32_t clk_en_register_index;
-+		uint32_t clk_y_register_index;
-+		uint32_t clk_a_register_index;
-+		uint32_t data_mask_register_index;
-+		uint32_t data_en_register_index;
-+		uint32_t data_y_register_index;
-+		uint32_t data_a_register_index;
-+
-+		uint32_t clk_mask_shift;
-+		uint32_t clk_en_shift;
-+		uint32_t clk_y_shift;
-+		uint32_t clk_a_shift;
-+		uint32_t data_mask_shift;
-+		uint32_t data_en_shift;
-+		uint32_t data_y_shift;
-+		uint32_t data_a_shift;
-+	} gpio_info;
-+
-+	bool i2c_hw_assist;
-+	uint32_t i2c_line;
-+	uint32_t i2c_engine_id;
-+	uint32_t i2c_slave_address;
-+};
-+
-+struct graphics_object_hpd_info {
-+	uint8_t hpd_int_gpio_uid;
-+	uint8_t hpd_active;
-+};
-+
-+struct connector_device_tag_info {
-+	uint32_t acpi_device;
-+	struct device_id dev_id;
-+};
-+
-+struct device_timing {
-+	struct misc_info {
-+		uint32_t HORIZONTAL_CUT_OFF:1;
-+		/* 0=Active High, 1=Active Low */
-+		uint32_t H_SYNC_POLARITY:1;
-+		/* 0=Active High, 1=Active Low */
-+		uint32_t V_SYNC_POLARITY:1;
-+		uint32_t VERTICAL_CUT_OFF:1;
-+		uint32_t H_REPLICATION_BY2:1;
-+		uint32_t V_REPLICATION_BY2:1;
-+		uint32_t COMPOSITE_SYNC:1;
-+		uint32_t INTERLACE:1;
-+		uint32_t DOUBLE_CLOCK:1;
-+		uint32_t RGB888:1;
-+		uint32_t GREY_LEVEL:2;
-+		uint32_t SPATIAL:1;
-+		uint32_t TEMPORAL:1;
-+		uint32_t API_ENABLED:1;
-+	} misc_info;
-+
-+	uint32_t pixel_clk; /* in KHz */
-+	uint32_t horizontal_addressable;
-+	uint32_t horizontal_blanking_time;
-+	uint32_t vertical_addressable;
-+	uint32_t vertical_blanking_time;
-+	uint32_t horizontal_sync_offset;
-+	uint32_t horizontal_sync_width;
-+	uint32_t vertical_sync_offset;
-+	uint32_t vertical_sync_width;
-+	uint32_t horizontal_border;
-+	uint32_t vertical_border;
-+};
-+
-+struct supported_refresh_rate {
-+	uint32_t REFRESH_RATE_30HZ:1;
-+	uint32_t REFRESH_RATE_40HZ:1;
-+	uint32_t REFRESH_RATE_48HZ:1;
-+	uint32_t REFRESH_RATE_50HZ:1;
-+	uint32_t REFRESH_RATE_60HZ:1;
-+};
-+
-+struct embedded_panel_info {
-+	struct device_timing lcd_timing;
-+	uint32_t ss_id;
-+	struct supported_refresh_rate supported_rr;
-+	uint32_t drr_enabled;
-+	uint32_t min_drr_refresh_rate;
-+	bool realtek_eDPToLVDS;
-+};
-+
-+struct dc_firmware_info {
-+	struct pll_info {
-+		uint32_t crystal_frequency; /* in KHz */
-+		uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */
-+		uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */
-+		uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */
-+		uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */
-+	} pll_info;
-+
-+	struct firmware_feature {
-+		uint32_t memory_clk_ss_percentage;
-+		uint32_t engine_clk_ss_percentage;
-+	} feature;
-+
-+	uint32_t default_display_engine_pll_frequency; /* in KHz */
-+	uint32_t external_clock_source_frequency_for_dp; /* in KHz */
-+	uint32_t smu_gpu_pll_output_freq; /* in KHz */
-+	uint8_t min_allowed_bl_level;
-+	uint8_t remote_display_config;
-+	uint32_t default_memory_clk; /* in KHz */
-+	uint32_t default_engine_clk; /* in KHz */
-+	uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */
-+	uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */
-+
-+
-+};
-+
-+struct step_and_delay_info {
-+	uint32_t step;
-+	uint32_t delay;
-+	uint32_t recommended_ref_div;
-+};
-+
-+struct spread_spectrum_info {
-+	struct spread_spectrum_type {
-+		bool CENTER_MODE:1;
-+		bool EXTERNAL:1;
-+		bool STEP_AND_DELAY_INFO:1;
-+	} type;
-+
-+	/* in unit of 0.01% (spreadPercentageDivider = 100),
-+	otherwise in 0.001% units (spreadPercentageDivider = 1000); */
-+	uint32_t spread_spectrum_percentage;
-+	uint32_t spread_percentage_divider; /* 100 or 1000 */
-+	uint32_t spread_spectrum_range; /* modulation freq (HZ)*/
-+
-+	union {
-+		struct step_and_delay_info step_and_delay_info;
-+		/* For mem/engine/uvd, Clock Out frequence (VCO ),
-+		in unit of kHz. For TMDS/HDMI/LVDS, it is pixel clock,
-+		for DP, it is link clock ( 270000 or 162000 ) */
-+		uint32_t target_clock_range; /* in KHz */
-+	};
-+
-+};
-+
-+struct graphics_object_encoder_cap_info {
-+	uint32_t dp_hbr2_cap:1;
-+	uint32_t dp_hbr2_validated:1;
-+	/*
-+	 * TODO: added MST and HDMI 6G capable flags
-+	 */
-+	uint32_t reserved:15;
-+};
-+
-+struct din_connector_info {
-+	uint32_t gpio_id;
-+	bool gpio_tv_active_state;
-+};
-+
-+/* Invalid channel mapping */
-+enum { INVALID_DDI_CHANNEL_MAPPING = 0x0 };
-+
-+/**
-+ * DDI PHY channel mapping reflecting XBAR setting
-+ */
-+union ddi_channel_mapping {
-+	struct mapping {
-+		uint8_t lane0:2;	/* Mapping for lane 0 */
-+		uint8_t lane1:2;	/* Mapping for lane 1 */
-+		uint8_t lane2:2;	/* Mapping for lane 2 */
-+		uint8_t lane3:2;	/* Mapping for lane 3 */
-+	} mapping;
-+	uint8_t raw;
-+};
-+
-+/**
-+* Transmitter output configuration description
-+*/
-+struct transmitter_configuration_info {
-+	/* DDI PHY ID for the transmitter */
-+	enum transmitter transmitter_phy_id;
-+	/* DDI PHY channel mapping reflecting crossbar setting */
-+	union ddi_channel_mapping output_channel_mapping;
-+};
-+
-+struct transmitter_configuration {
-+	/* Configuration for the primary transmitter */
-+	struct transmitter_configuration_info primary_transmitter_config;
-+	/* Secondary transmitter configuration for Dual-link DVI */
-+	struct transmitter_configuration_info secondary_transmitter_config;
-+};
-+
-+/* These size should be sufficient to store info coming from BIOS */
-+#define NUMBER_OF_UCHAR_FOR_GUID 16
-+#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
-+#define NUMBER_OF_CSR_M3_ARB 10
-+#define NUMBER_OF_DISP_CLK_VOLTAGE 4
-+#define NUMBER_OF_AVAILABLE_SCLK 5
-+
-+struct i2c_reg_info {
-+	unsigned char       i2c_reg_index;
-+	unsigned char       i2c_reg_val;
-+};
-+
-+struct ext_hdmi_settings {
-+	unsigned char   slv_addr;
-+	unsigned char   reg_num;
-+	struct i2c_reg_info      reg_settings[9];
-+	unsigned char   reg_num_6g;
-+	struct i2c_reg_info      reg_settings_6g[3];
-+};
-+
-+
-+/* V6 */
-+struct integrated_info {
-+	struct clock_voltage_caps {
-+		/* The Voltage Index indicated by FUSE, same voltage index
-+		shared with SCLK DPM fuse table */
-+		uint32_t voltage_index;
-+		/* Maximum clock supported with specified voltage index */
-+		uint32_t max_supported_clk; /* in KHz */
-+	} disp_clk_voltage[NUMBER_OF_DISP_CLK_VOLTAGE];
-+
-+	struct display_connection_info {
-+		struct external_display_path {
-+			/* A bit vector to show what devices are supported */
-+			uint32_t device_tag;
-+			/* 16bit device ACPI id. */
-+			uint32_t device_acpi_enum;
-+			/* A physical connector for displays to plug in,
-+			using object connector definitions */
-+			struct graphics_object_id device_connector_id;
-+			/* An index into external AUX/DDC channel LUT */
-+			uint8_t ext_aux_ddc_lut_index;
-+			/* An index into external HPD pin LUT */
-+			uint8_t ext_hpd_pin_lut_index;
-+			/* external encoder object id */
-+			struct graphics_object_id ext_encoder_obj_id;
-+			/* XBAR mapping of the PHY channels */
-+			union ddi_channel_mapping channel_mapping;
-+
-+			unsigned short caps;
-+		} path[MAX_NUMBER_OF_EXT_DISPLAY_PATH];
-+
-+		uint8_t gu_id[NUMBER_OF_UCHAR_FOR_GUID];
-+		uint8_t checksum;
-+	} ext_disp_conn_info; /* exiting long long time */
-+
-+	struct available_s_clk_list {
-+		/* Maximum clock supported with specified voltage index */
-+		uint32_t supported_s_clk; /* in KHz */
-+		/* The Voltage Index indicated by FUSE for specified SCLK */
-+		uint32_t voltage_index;
-+		/* The Voltage ID indicated by FUSE for specified SCLK */
-+		uint32_t voltage_id;
-+	} avail_s_clk[NUMBER_OF_AVAILABLE_SCLK];
-+
-+	uint8_t memory_type;
-+	uint8_t ma_channel_number;
-+	uint32_t boot_up_engine_clock; /* in KHz */
-+	uint32_t dentist_vco_freq; /* in KHz */
-+	uint32_t boot_up_uma_clock; /* in KHz */
-+	uint32_t boot_up_req_display_vector;
-+	uint32_t other_display_misc;
-+	uint32_t gpu_cap_info;
-+	uint32_t sb_mmio_base_addr;
-+	uint32_t system_config;
-+	uint32_t cpu_cap_info;
-+	uint32_t max_nb_voltage;
-+	uint32_t min_nb_voltage;
-+	uint32_t boot_up_nb_voltage;
-+	uint32_t ext_disp_conn_info_offset;
-+	uint32_t csr_m3_arb_cntl_default[NUMBER_OF_CSR_M3_ARB];
-+	uint32_t csr_m3_arb_cntl_uvd[NUMBER_OF_CSR_M3_ARB];
-+	uint32_t csr_m3_arb_cntl_fs3d[NUMBER_OF_CSR_M3_ARB];
-+	uint32_t gmc_restore_reset_time;
-+	uint32_t minimum_n_clk;
-+	uint32_t idle_n_clk;
-+	uint32_t ddr_dll_power_up_time;
-+	uint32_t ddr_pll_power_up_time;
-+	/* start for V6 */
-+	uint32_t pcie_clk_ss_type;
-+	uint32_t lvds_ss_percentage;
-+	uint32_t lvds_sspread_rate_in_10hz;
-+	uint32_t hdmi_ss_percentage;
-+	uint32_t hdmi_sspread_rate_in_10hz;
-+	uint32_t dvi_ss_percentage;
-+	uint32_t dvi_sspread_rate_in_10_hz;
-+	uint32_t sclk_dpm_boost_margin;
-+	uint32_t sclk_dpm_throttle_margin;
-+	uint32_t sclk_dpm_tdp_limit_pg;
-+	uint32_t sclk_dpm_tdp_limit_boost;
-+	uint32_t boost_engine_clock;
-+	uint32_t boost_vid_2bit;
-+	uint32_t enable_boost;
-+	uint32_t gnb_tdp_limit;
-+	/* Start from V7 */
-+	uint32_t max_lvds_pclk_freq_in_single_link;
-+	uint32_t lvds_misc;
-+	uint32_t lvds_pwr_on_seq_dig_on_to_de_in_4ms;
-+	uint32_t lvds_pwr_on_seq_de_to_vary_bl_in_4ms;
-+	uint32_t lvds_pwr_off_seq_vary_bl_to_de_in4ms;
-+	uint32_t lvds_pwr_off_seq_de_to_dig_on_in4ms;
-+	uint32_t lvds_off_to_on_delay_in_4ms;
-+	uint32_t lvds_pwr_on_seq_vary_bl_to_blon_in_4ms;
-+	uint32_t lvds_pwr_off_seq_blon_to_vary_bl_in_4ms;
-+	uint32_t lvds_reserved1;
-+	uint32_t lvds_bit_depth_control_val;
-+	//Start from V9
-+	unsigned char dp0_ext_hdmi_slv_addr;
-+	unsigned char dp0_ext_hdmi_reg_num;
-+	struct i2c_reg_info dp0_ext_hdmi_reg_settings[9];
-+	unsigned char dp0_ext_hdmi_6g_reg_num;
-+	struct i2c_reg_info dp0_ext_hdmi_6g_reg_settings[3];
-+	unsigned char dp1_ext_hdmi_slv_addr;
-+	unsigned char dp1_ext_hdmi_reg_num;
-+	struct i2c_reg_info dp1_ext_hdmi_reg_settings[9];
-+	unsigned char dp1_ext_hdmi_6g_reg_num;
-+	struct i2c_reg_info dp1_ext_hdmi_6g_reg_settings[3];
-+	unsigned char dp2_ext_hdmi_slv_addr;
-+	unsigned char dp2_ext_hdmi_reg_num;
-+	struct i2c_reg_info dp2_ext_hdmi_reg_settings[9];
-+	unsigned char dp2_ext_hdmi_6g_reg_num;
-+	struct i2c_reg_info dp2_ext_hdmi_6g_reg_settings[3];
-+	unsigned char dp3_ext_hdmi_slv_addr;
-+	unsigned char dp3_ext_hdmi_reg_num;
-+	struct i2c_reg_info dp3_ext_hdmi_reg_settings[9];
-+	unsigned char dp3_ext_hdmi_6g_reg_num;
-+	struct i2c_reg_info dp3_ext_hdmi_6g_reg_settings[3];
-+};
-+
-+/**
-+* Power source ids.
-+*/
-+enum power_source {
-+	POWER_SOURCE_AC = 0,
-+	POWER_SOURCE_DC,
-+	POWER_SOURCE_LIMITED_POWER,
-+	POWER_SOURCE_LIMITED_POWER_2,
-+	POWER_SOURCE_MAX
-+};
-+
-+struct bios_event_info {
-+	uint32_t thermal_state;
-+	uint32_t backlight_level;
-+	enum power_source powerSource;
-+	bool has_thermal_state_changed;
-+	bool has_power_source_changed;
-+	bool has_forced_mode_changed;
-+	bool forced_mode;
-+	bool backlight_changed;
-+};
-+
-+enum {
-+	HDMI_PIXEL_CLOCK_IN_KHZ_297 = 297000,
-+	TMDS_PIXEL_CLOCK_IN_KHZ_165 = 165000
-+};
-+
-+/*
-+ * DFS-bypass flag
-+ */
-+/* Copy of SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS from atombios.h */
-+enum {
-+	DFS_BYPASS_ENABLE = 0x10
-+};
-+
-+enum {
-+	INVALID_BACKLIGHT = -1
-+};
-+
-+struct panel_backlight_boundaries {
-+	uint32_t min_signal_level;
-+	uint32_t max_signal_level;
-+};
-+
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/include/grph_object_defs.h.0130~	2017-12-14 06:39:58.441903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/grph_object_defs.h	2017-12-14 06:39:58.441903586 +0100
-@@ -0,0 +1,140 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GRPH_OBJECT_DEFS_H__
-+#define __DAL_GRPH_OBJECT_DEFS_H__
-+
-+#include "grph_object_id.h"
-+
-+/* ********************************************************************
-+ * ********************************************************************
-+ *
-+ *  These defines shared between All Graphics Objects
-+ *
-+ * ********************************************************************
-+ * ********************************************************************
-+ */
-+
-+/* HPD unit id - HW direct translation */
-+enum hpd_source_id {
-+	HPD_SOURCEID1 = 0,
-+	HPD_SOURCEID2,
-+	HPD_SOURCEID3,
-+	HPD_SOURCEID4,
-+	HPD_SOURCEID5,
-+	HPD_SOURCEID6,
-+
-+	HPD_SOURCEID_COUNT,
-+	HPD_SOURCEID_UNKNOWN
-+};
-+
-+/* DDC unit id - HW direct translation */
-+enum channel_id {
-+	CHANNEL_ID_UNKNOWN = 0,
-+	CHANNEL_ID_DDC1,
-+	CHANNEL_ID_DDC2,
-+	CHANNEL_ID_DDC3,
-+	CHANNEL_ID_DDC4,
-+	CHANNEL_ID_DDC5,
-+	CHANNEL_ID_DDC6,
-+	CHANNEL_ID_DDC_VGA,
-+	CHANNEL_ID_I2C_PAD,
-+	CHANNEL_ID_COUNT
-+};
-+
-+#define DECODE_CHANNEL_ID(ch_id) \
-+	(ch_id) == CHANNEL_ID_DDC1 ? "CHANNEL_ID_DDC1" : \
-+	(ch_id) == CHANNEL_ID_DDC2 ? "CHANNEL_ID_DDC2" : \
-+	(ch_id) == CHANNEL_ID_DDC3 ? "CHANNEL_ID_DDC3" : \
-+	(ch_id) == CHANNEL_ID_DDC4 ? "CHANNEL_ID_DDC4" : \
-+	(ch_id) == CHANNEL_ID_DDC5 ? "CHANNEL_ID_DDC5" : \
-+	(ch_id) == CHANNEL_ID_DDC6 ? "CHANNEL_ID_DDC6" : \
-+	(ch_id) == CHANNEL_ID_DDC_VGA ? "CHANNEL_ID_DDC_VGA" : \
-+	(ch_id) == CHANNEL_ID_I2C_PAD ? "CHANNEL_ID_I2C_PAD" : "Invalid"
-+
-+enum transmitter {
-+	TRANSMITTER_UNKNOWN = (-1L),
-+	TRANSMITTER_UNIPHY_A,
-+	TRANSMITTER_UNIPHY_B,
-+	TRANSMITTER_UNIPHY_C,
-+	TRANSMITTER_UNIPHY_D,
-+	TRANSMITTER_UNIPHY_E,
-+	TRANSMITTER_UNIPHY_F,
-+	TRANSMITTER_NUTMEG_CRT,
-+	TRANSMITTER_TRAVIS_CRT,
-+	TRANSMITTER_TRAVIS_LCD,
-+	TRANSMITTER_UNIPHY_G,
-+	TRANSMITTER_COUNT
-+};
-+
-+/* Generic source of the synchronisation input/output signal */
-+/* Can be used for flow control, stereo sync, timing sync, frame sync, etc */
-+enum sync_source {
-+	SYNC_SOURCE_NONE = 0,
-+
-+	/* Source based on controllers */
-+	SYNC_SOURCE_CONTROLLER0,
-+	SYNC_SOURCE_CONTROLLER1,
-+	SYNC_SOURCE_CONTROLLER2,
-+	SYNC_SOURCE_CONTROLLER3,
-+	SYNC_SOURCE_CONTROLLER4,
-+	SYNC_SOURCE_CONTROLLER5,
-+
-+	/* Source based on GSL group */
-+	SYNC_SOURCE_GSL_GROUP0,
-+	SYNC_SOURCE_GSL_GROUP1,
-+	SYNC_SOURCE_GSL_GROUP2,
-+
-+	/* Source based on GSL IOs */
-+	/* These IOs normally used as GSL input/output */
-+	SYNC_SOURCE_GSL_IO_FIRST,
-+	SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK = SYNC_SOURCE_GSL_IO_FIRST,
-+	SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC,
-+	SYNC_SOURCE_GSL_IO_SWAPLOCK_A,
-+	SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
-+	SYNC_SOURCE_GSL_IO_LAST = SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
-+
-+	/* Source based on regular IOs */
-+	SYNC_SOURCE_IO_FIRST,
-+	SYNC_SOURCE_IO_GENERIC_A = SYNC_SOURCE_IO_FIRST,
-+	SYNC_SOURCE_IO_GENERIC_B,
-+	SYNC_SOURCE_IO_GENERIC_C,
-+	SYNC_SOURCE_IO_GENERIC_D,
-+	SYNC_SOURCE_IO_GENERIC_E,
-+	SYNC_SOURCE_IO_GENERIC_F,
-+	SYNC_SOURCE_IO_HPD1,
-+	SYNC_SOURCE_IO_HPD2,
-+	SYNC_SOURCE_IO_HSYNC_A,
-+	SYNC_SOURCE_IO_VSYNC_A,
-+	SYNC_SOURCE_IO_HSYNC_B,
-+	SYNC_SOURCE_IO_VSYNC_B,
-+	SYNC_SOURCE_IO_LAST = SYNC_SOURCE_IO_VSYNC_B,
-+
-+	/* Misc. flow control sources */
-+	SYNC_SOURCE_DUAL_GPU_PIN
-+};
-+
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/include/grph_object_id.h.0130~	2017-12-14 06:39:58.441903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/grph_object_id.h	2017-12-14 06:39:58.441903586 +0100
-@@ -0,0 +1,294 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_GRPH_OBJECT_ID_H__
-+#define __DAL_GRPH_OBJECT_ID_H__
-+
-+/* Types of graphics objects */
-+enum object_type {
-+	OBJECT_TYPE_UNKNOWN  = 0,
-+
-+	/* Direct ATOM BIOS translation */
-+	OBJECT_TYPE_GPU,
-+	OBJECT_TYPE_ENCODER,
-+	OBJECT_TYPE_CONNECTOR,
-+	OBJECT_TYPE_ROUTER,
-+	OBJECT_TYPE_GENERIC,
-+
-+	/* Driver specific */
-+	OBJECT_TYPE_AUDIO,
-+	OBJECT_TYPE_CONTROLLER,
-+	OBJECT_TYPE_CLOCK_SOURCE,
-+	OBJECT_TYPE_ENGINE,
-+
-+	OBJECT_TYPE_COUNT
-+};
-+
-+/* Enumeration inside one type of graphics objects */
-+enum object_enum_id {
-+	ENUM_ID_UNKNOWN = 0,
-+	ENUM_ID_1,
-+	ENUM_ID_2,
-+	ENUM_ID_3,
-+	ENUM_ID_4,
-+	ENUM_ID_5,
-+	ENUM_ID_6,
-+	ENUM_ID_7,
-+
-+	ENUM_ID_COUNT
-+};
-+
-+/* Generic object ids */
-+enum generic_id {
-+	GENERIC_ID_UNKNOWN = 0,
-+	GENERIC_ID_MXM_OPM,
-+	GENERIC_ID_GLSYNC,
-+	GENERIC_ID_STEREO,
-+
-+	GENERIC_ID_COUNT
-+};
-+
-+/* Controller object ids */
-+enum controller_id {
-+	CONTROLLER_ID_UNDEFINED = 0,
-+	CONTROLLER_ID_D0,
-+	CONTROLLER_ID_D1,
-+	CONTROLLER_ID_D2,
-+	CONTROLLER_ID_D3,
-+	CONTROLLER_ID_D4,
-+	CONTROLLER_ID_D5,
-+	CONTROLLER_ID_UNDERLAY0,
-+	CONTROLLER_ID_MAX = CONTROLLER_ID_UNDERLAY0
-+};
-+
-+#define IS_UNDERLAY_CONTROLLER(ctrlr_id) (ctrlr_id >= CONTROLLER_ID_UNDERLAY0)
-+
-+/*
-+ * ClockSource object ids.
-+ * We maintain the order matching (more or less) ATOM BIOS
-+ * to improve optimized acquire
-+ */
-+enum clock_source_id {
-+	CLOCK_SOURCE_ID_UNDEFINED = 0,
-+	CLOCK_SOURCE_ID_PLL0,
-+	CLOCK_SOURCE_ID_PLL1,
-+	CLOCK_SOURCE_ID_PLL2,
-+	CLOCK_SOURCE_ID_EXTERNAL, /* ID (Phy) ref. clk. for DP */
-+	CLOCK_SOURCE_ID_DCPLL,
-+	CLOCK_SOURCE_ID_DFS,	/* DENTIST */
-+	CLOCK_SOURCE_ID_VCE,	/* VCE does not need a real PLL */
-+	/* Used to distinguish between programming pixel clock and ID (Phy) clock */
-+	CLOCK_SOURCE_ID_DP_DTO,
-+
-+	CLOCK_SOURCE_COMBO_PHY_PLL0, /*combo PHY PLL defines (DC 11.2 and up)*/
-+	CLOCK_SOURCE_COMBO_PHY_PLL1,
-+	CLOCK_SOURCE_COMBO_PHY_PLL2,
-+	CLOCK_SOURCE_COMBO_PHY_PLL3,
-+	CLOCK_SOURCE_COMBO_PHY_PLL4,
-+	CLOCK_SOURCE_COMBO_PHY_PLL5,
-+	CLOCK_SOURCE_COMBO_DISPLAY_PLL0
-+};
-+
-+/* Encoder object ids */
-+enum encoder_id {
-+	ENCODER_ID_UNKNOWN = 0,
-+
-+	/* Radeon Class Display Hardware */
-+	ENCODER_ID_INTERNAL_LVDS,
-+	ENCODER_ID_INTERNAL_TMDS1,
-+	ENCODER_ID_INTERNAL_TMDS2,
-+	ENCODER_ID_INTERNAL_DAC1,
-+	ENCODER_ID_INTERNAL_DAC2,	/* TV/CV DAC */
-+
-+	/* External Third Party Encoders */
-+	ENCODER_ID_INTERNAL_LVTM1,	/* not used for Radeon */
-+	ENCODER_ID_INTERNAL_HDMI,
-+
-+	/* Kaledisope (KLDSCP) Class Display Hardware */
-+	ENCODER_ID_INTERNAL_KLDSCP_TMDS1,
-+	ENCODER_ID_INTERNAL_KLDSCP_DAC1,
-+	ENCODER_ID_INTERNAL_KLDSCP_DAC2,	/* Shared with CV/TV and CRT */
-+	/* External TMDS (dual link) */
-+	ENCODER_ID_EXTERNAL_MVPU_FPGA,	/* MVPU FPGA chip */
-+	ENCODER_ID_INTERNAL_DDI,
-+	ENCODER_ID_INTERNAL_UNIPHY,
-+	ENCODER_ID_INTERNAL_KLDSCP_LVTMA,
-+	ENCODER_ID_INTERNAL_UNIPHY1,
-+	ENCODER_ID_INTERNAL_UNIPHY2,
-+	ENCODER_ID_EXTERNAL_NUTMEG,
-+	ENCODER_ID_EXTERNAL_TRAVIS,
-+
-+	ENCODER_ID_INTERNAL_WIRELESS,	/* Internal wireless display encoder */
-+	ENCODER_ID_INTERNAL_UNIPHY3,
-+	ENCODER_ID_INTERNAL_VIRTUAL,
-+};
-+
-+/* Connector object ids */
-+enum connector_id {
-+	CONNECTOR_ID_UNKNOWN = 0,
-+	CONNECTOR_ID_SINGLE_LINK_DVII = 1,
-+	CONNECTOR_ID_DUAL_LINK_DVII = 2,
-+	CONNECTOR_ID_SINGLE_LINK_DVID = 3,
-+	CONNECTOR_ID_DUAL_LINK_DVID = 4,
-+	CONNECTOR_ID_VGA = 5,
-+	CONNECTOR_ID_HDMI_TYPE_A = 12,
-+	CONNECTOR_ID_LVDS = 14,
-+	CONNECTOR_ID_PCIE = 16,
-+	CONNECTOR_ID_HARDCODE_DVI = 18,
-+	CONNECTOR_ID_DISPLAY_PORT = 19,
-+	CONNECTOR_ID_EDP = 20,
-+	CONNECTOR_ID_MXM = 21,
-+	CONNECTOR_ID_WIRELESS = 22,
-+	CONNECTOR_ID_MIRACAST = 23,
-+
-+	CONNECTOR_ID_VIRTUAL = 100
-+};
-+
-+/* Audio object ids */
-+enum audio_id {
-+	AUDIO_ID_UNKNOWN = 0,
-+	AUDIO_ID_INTERNAL_AZALIA
-+};
-+
-+/* Engine object ids */
-+enum engine_id {
-+	ENGINE_ID_DIGA,
-+	ENGINE_ID_DIGB,
-+	ENGINE_ID_DIGC,
-+	ENGINE_ID_DIGD,
-+	ENGINE_ID_DIGE,
-+	ENGINE_ID_DIGF,
-+	ENGINE_ID_DIGG,
-+	ENGINE_ID_DACA,
-+	ENGINE_ID_DACB,
-+	ENGINE_ID_VCE,	/* wireless display pseudo-encoder */
-+	ENGINE_ID_VIRTUAL,
-+
-+	ENGINE_ID_COUNT,
-+	ENGINE_ID_UNKNOWN = (-1L)
-+};
-+
-+enum transmitter_color_depth {
-+	TRANSMITTER_COLOR_DEPTH_24 = 0,  /* 8  bits */
-+	TRANSMITTER_COLOR_DEPTH_30,      /* 10 bits */
-+	TRANSMITTER_COLOR_DEPTH_36,      /* 12 bits */
-+	TRANSMITTER_COLOR_DEPTH_48       /* 16 bits */
-+};
-+
-+/*
-+ *****************************************************************************
-+ * graphics_object_id struct
-+ *
-+ * graphics_object_id is a very simple struct wrapping 32bit Graphics
-+ * Object identication
-+ *
-+ * This struct should stay very simple
-+ *  No dependencies at all (no includes)
-+ *  No debug messages or asserts
-+ *  No #ifndef and preprocessor directives
-+ *  No grow in space (no more data member)
-+ *****************************************************************************
-+ */
-+
-+struct graphics_object_id {
-+	uint32_t  id:8;
-+	uint32_t  enum_id:4;
-+	uint32_t  type:4;
-+	uint32_t  reserved:16; /* for padding. total size should be u32 */
-+};
-+
-+/* some simple functions for convenient graphics_object_id handle */
-+
-+static inline struct graphics_object_id dal_graphics_object_id_init(
-+	uint32_t id,
-+	enum object_enum_id enum_id,
-+	enum object_type type)
-+{
-+	struct graphics_object_id result = {
-+		id, enum_id, type, 0
-+	};
-+
-+	return result;
-+}
-+
-+bool dal_graphics_object_id_is_equal(
-+	struct graphics_object_id id1,
-+	struct graphics_object_id id2);
-+
-+/* Based on internal data members memory layout */
-+static inline uint32_t dal_graphics_object_id_to_uint(
-+	struct graphics_object_id id)
-+{
-+	return id.id + (id.enum_id << 0x8) + (id.type << 0xc);
-+}
-+
-+static inline enum controller_id dal_graphics_object_id_get_controller_id(
-+	struct graphics_object_id id)
-+{
-+	if (id.type == OBJECT_TYPE_CONTROLLER)
-+		return (enum controller_id) id.id;
-+	return CONTROLLER_ID_UNDEFINED;
-+}
-+
-+static inline enum clock_source_id dal_graphics_object_id_get_clock_source_id(
-+	struct graphics_object_id id)
-+{
-+	if (id.type == OBJECT_TYPE_CLOCK_SOURCE)
-+		return (enum clock_source_id) id.id;
-+	return CLOCK_SOURCE_ID_UNDEFINED;
-+}
-+
-+static inline enum encoder_id dal_graphics_object_id_get_encoder_id(
-+	struct graphics_object_id id)
-+{
-+	if (id.type == OBJECT_TYPE_ENCODER)
-+		return (enum encoder_id) id.id;
-+	return ENCODER_ID_UNKNOWN;
-+}
-+
-+static inline enum connector_id dal_graphics_object_id_get_connector_id(
-+	struct graphics_object_id id)
-+{
-+	if (id.type == OBJECT_TYPE_CONNECTOR)
-+		return (enum connector_id) id.id;
-+	return CONNECTOR_ID_UNKNOWN;
-+}
-+
-+static inline enum audio_id dal_graphics_object_id_get_audio_id(
-+	struct graphics_object_id id)
-+{
-+	if (id.type == OBJECT_TYPE_AUDIO)
-+		return (enum audio_id) id.id;
-+	return AUDIO_ID_UNKNOWN;
-+}
-+
-+static inline enum engine_id dal_graphics_object_id_get_engine_id(
-+	struct graphics_object_id id)
-+{
-+	if (id.type == OBJECT_TYPE_ENGINE)
-+		return (enum engine_id) id.id;
-+	return ENGINE_ID_UNKNOWN;
-+}
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/include/i2caux_interface.h.0130~	2017-12-14 06:39:58.441903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/i2caux_interface.h	2017-12-14 06:39:58.441903586 +0100
-@@ -0,0 +1,92 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_I2CAUX_INTERFACE_H__
-+#define __DAL_I2CAUX_INTERFACE_H__
-+
-+#include "dc_types.h"
-+#include "gpio_service_interface.h"
-+
-+
-+#define DEFAULT_AUX_MAX_DATA_SIZE 16
-+#define AUX_MAX_DEFER_WRITE_RETRY 20
-+
-+struct aux_payload {
-+	/* set following flag to read/write I2C data,
-+	 * reset it to read/write DPCD data */
-+	bool i2c_over_aux;
-+	/* set following flag to write data,
-+	 * reset it to read data */
-+	bool write;
-+	uint32_t address;
-+	uint8_t length;
-+	uint8_t *data;
-+};
-+
-+struct aux_command {
-+	struct aux_payload *payloads;
-+	uint8_t number_of_payloads;
-+
-+	/* expressed in milliseconds
-+	 * zero means "use default value" */
-+	uint32_t defer_delay;
-+
-+	/* zero means "use default value" */
-+	uint32_t max_defer_write_retry;
-+
-+	enum i2c_mot_mode mot;
-+};
-+
-+union aux_config {
-+	struct {
-+		uint32_t ALLOW_AUX_WHEN_HPD_LOW:1;
-+	} bits;
-+	uint32_t raw;
-+};
-+
-+struct i2caux;
-+
-+struct i2caux *dal_i2caux_create(
-+	struct dc_context *ctx);
-+
-+bool dal_i2caux_submit_i2c_command(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc,
-+	struct i2c_command *cmd);
-+
-+bool dal_i2caux_submit_aux_command(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc,
-+	struct aux_command *cmd);
-+
-+void dal_i2caux_configure_aux(
-+	struct i2caux *i2caux,
-+	struct ddc *ddc,
-+	union aux_config cfg);
-+
-+void dal_i2caux_destroy(
-+	struct i2caux **ptr);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/include/irq_service_interface.h.0130~	2017-12-14 06:39:58.441903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/irq_service_interface.h	2017-12-14 06:39:58.441903586 +0100
-@@ -0,0 +1,51 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_IRQ_SERVICE_INTERFACE_H__
-+#define __DAL_IRQ_SERVICE_INTERFACE_H__
-+
-+struct irq_service_init_data {
-+	struct dc_context *ctx;
-+};
-+
-+struct irq_service;
-+
-+void dal_irq_service_destroy(struct irq_service **irq_service);
-+
-+bool dal_irq_service_set(
-+	struct irq_service *irq_service,
-+	enum dc_irq_source source,
-+	bool enable);
-+
-+bool dal_irq_service_ack(
-+	struct irq_service *irq_service,
-+	enum dc_irq_source source);
-+
-+enum dc_irq_source dal_irq_service_to_irq_source(
-+		struct irq_service *irq_service,
-+		uint32_t src_id,
-+		uint32_t ext_id);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/include/link_service_types.h.0130~	2017-12-14 06:39:58.441903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/link_service_types.h	2017-12-14 06:39:58.441903586 +0100
-@@ -0,0 +1,170 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_LINK_SERVICE_TYPES_H__
-+#define __DAL_LINK_SERVICE_TYPES_H__
-+
-+#include "grph_object_id.h"
-+#include "dal_types.h"
-+#include "irq_types.h"
-+
-+/*struct mst_mgr_callback_object;*/
-+struct ddc;
-+struct irq_manager;
-+
-+enum {
-+	MAX_CONTROLLER_NUM = 6
-+};
-+
-+enum dp_power_state {
-+	DP_POWER_STATE_D0 = 1,
-+	DP_POWER_STATE_D3
-+};
-+
-+enum edp_revision {
-+	/* eDP version 1.1 or lower */
-+	EDP_REVISION_11 = 0x00,
-+	/* eDP version 1.2 */
-+	EDP_REVISION_12 = 0x01,
-+	/* eDP version 1.3 */
-+	EDP_REVISION_13 = 0x02
-+};
-+
-+enum {
-+	LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/
-+};
-+
-+enum link_training_result {
-+	LINK_TRAINING_SUCCESS,
-+	LINK_TRAINING_CR_FAIL,
-+	/* CR DONE bit is cleared during EQ step */
-+	LINK_TRAINING_EQ_FAIL_CR,
-+	/* other failure during EQ step */
-+	LINK_TRAINING_EQ_FAIL_EQ,
-+};
-+
-+struct link_training_settings {
-+	struct dc_link_settings link_settings;
-+	struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
-+	bool allow_invalid_msa_timing_param;
-+};
-+
-+enum hw_dp_training_pattern {
-+	HW_DP_TRAINING_PATTERN_1 = 0,
-+	HW_DP_TRAINING_PATTERN_2,
-+	HW_DP_TRAINING_PATTERN_3,
-+	HW_DP_TRAINING_PATTERN_4
-+};
-+
-+/*TODO: Move this enum test harness*/
-+/* Test patterns*/
-+enum dp_test_pattern {
-+	/* Input data is pass through Scrambler
-+	 * and 8b10b Encoder straight to output*/
-+	DP_TEST_PATTERN_VIDEO_MODE = 0,
-+
-+	/* phy test patterns*/
-+	DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
-+	DP_TEST_PATTERN_D102 = DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
-+	DP_TEST_PATTERN_SYMBOL_ERROR,
-+	DP_TEST_PATTERN_PRBS7,
-+	DP_TEST_PATTERN_80BIT_CUSTOM,
-+	DP_TEST_PATTERN_CP2520_1,
-+	DP_TEST_PATTERN_CP2520_2,
-+	DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2,
-+	DP_TEST_PATTERN_CP2520_3,
-+
-+	/* Link Training Patterns */
-+	DP_TEST_PATTERN_TRAINING_PATTERN1,
-+	DP_TEST_PATTERN_TRAINING_PATTERN2,
-+	DP_TEST_PATTERN_TRAINING_PATTERN3,
-+	DP_TEST_PATTERN_TRAINING_PATTERN4,
-+	DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_TRAINING_PATTERN4,
-+
-+	/* link test patterns*/
-+	DP_TEST_PATTERN_COLOR_SQUARES,
-+	DP_TEST_PATTERN_COLOR_SQUARES_CEA,
-+	DP_TEST_PATTERN_VERTICAL_BARS,
-+	DP_TEST_PATTERN_HORIZONTAL_BARS,
-+	DP_TEST_PATTERN_COLOR_RAMP,
-+
-+	/* audio test patterns*/
-+	DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED,
-+	DP_TEST_PATTERN_AUDIO_SAWTOOTH,
-+
-+	DP_TEST_PATTERN_UNSUPPORTED
-+};
-+
-+enum dp_panel_mode {
-+	/* not required */
-+	DP_PANEL_MODE_DEFAULT,
-+	/* standard mode for eDP */
-+	DP_PANEL_MODE_EDP,
-+	/* external chips specific settings */
-+	DP_PANEL_MODE_SPECIAL
-+};
-+
-+/* DPCD_ADDR_TRAINING_LANEx_SET registers value */
-+union dpcd_training_lane_set {
-+	struct {
-+#if defined(LITTLEENDIAN_CPU)
-+		uint8_t VOLTAGE_SWING_SET:2;
-+		uint8_t MAX_SWING_REACHED:1;
-+		uint8_t PRE_EMPHASIS_SET:2;
-+		uint8_t MAX_PRE_EMPHASIS_REACHED:1;
-+		/* following is reserved in DP 1.1 */
-+		uint8_t POST_CURSOR2_SET:2;
-+#elif defined(BIGENDIAN_CPU)
-+		uint8_t POST_CURSOR2_SET:2;
-+		uint8_t MAX_PRE_EMPHASIS_REACHED:1;
-+		uint8_t PRE_EMPHASIS_SET:2;
-+		uint8_t MAX_SWING_REACHED:1;
-+		uint8_t VOLTAGE_SWING_SET:2;
-+#else
-+	#error ARCH not defined!
-+#endif
-+	} bits;
-+
-+	uint8_t raw;
-+};
-+
-+
-+/* DP MST stream allocation (payload bandwidth number) */
-+struct dp_mst_stream_allocation {
-+	uint8_t vcp_id;
-+	/* number of slots required for the DP stream in
-+	 * transport packet */
-+	uint8_t slot_count;
-+};
-+
-+/* DP MST stream allocation table */
-+struct dp_mst_stream_allocation_table {
-+	/* number of DP video streams */
-+	int stream_count;
-+	/* array of stream allocations */
-+	struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
-+};
-+
-+#endif /*__DAL_LINK_SERVICE_TYPES_H__*/
---- linux-4.14/drivers/gpu/drm/amd/display/include/logger_interface.h.0130~	2017-12-14 06:39:58.441903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/logger_interface.h	2017-12-14 06:39:58.441903586 +0100
-@@ -0,0 +1,188 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_LOGGER_INTERFACE_H__
-+#define __DAL_LOGGER_INTERFACE_H__
-+
-+#include "logger_types.h"
-+
-+struct dc_context;
-+struct dc_link;
-+struct dc_surface_update;
-+struct resource_context;
-+struct dc_state;
-+
-+/*
-+ *
-+ * DAL logger functionality
-+ *
-+ */
-+
-+struct dal_logger *dal_logger_create(struct dc_context *ctx, uint32_t log_mask);
-+
-+uint32_t dal_logger_destroy(struct dal_logger **logger);
-+
-+void dm_logger_flush_buffer(struct dal_logger *logger, bool should_warn);
-+
-+void dm_logger_write(
-+		struct dal_logger *logger,
-+		enum dc_log_type log_type,
-+		const char *msg,
-+		...);
-+
-+void dm_logger_append(
-+		struct log_entry *entry,
-+		const char *msg,
-+		...);
-+
-+void dm_logger_open(
-+		struct dal_logger *logger,
-+		struct log_entry *entry,
-+		enum dc_log_type log_type);
-+
-+void dm_logger_close(struct log_entry *entry);
-+
-+void dc_conn_log(struct dc_context *ctx,
-+		const struct dc_link *link,
-+		uint8_t *hex_data,
-+		int hex_data_count,
-+		enum dc_log_type event,
-+		const char *msg,
-+		...);
-+
-+void logger_write(struct dal_logger *logger,
-+		enum dc_log_type log_type,
-+		const char *msg,
-+		void *paralist);
-+
-+void pre_surface_trace(
-+		struct dc *dc,
-+		const struct dc_plane_state *const *plane_states,
-+		int surface_count);
-+
-+void update_surface_trace(
-+		struct dc *dc,
-+		const struct dc_surface_update *updates,
-+		int surface_count);
-+
-+void post_surface_trace(struct dc *dc);
-+
-+void context_timing_trace(
-+		struct dc *dc,
-+		struct resource_context *res_ctx);
-+
-+void context_clock_trace(
-+		struct dc *dc,
-+		struct dc_state *context);
-+
-+/* Any function which is empty or have incomplete implementation should be
-+ * marked by this macro.
-+ * Note that the message will be printed exactly once for every function
-+ * it is used in order to avoid repeating of the same message. */
-+#define DAL_LOGGER_NOT_IMPL(fmt, ...) \
-+{ \
-+	static bool print_not_impl = true; \
-+\
-+	if (print_not_impl == true) { \
-+		print_not_impl = false; \
-+		dm_logger_write(ctx->logger, LOG_WARNING, \
-+		"DAL_NOT_IMPL: " fmt, ##__VA_ARGS__); \
-+	} \
-+}
-+
-+/******************************************************************************
-+ * Convenience macros to save on typing.
-+ *****************************************************************************/
-+
-+#define DC_ERROR(...) \
-+	dm_logger_write(dc_ctx->logger, LOG_ERROR, \
-+		__VA_ARGS__)
-+
-+#define DC_SYNC_INFO(...) \
-+	dm_logger_write(dc_ctx->logger, LOG_SYNC, \
-+		__VA_ARGS__)
-+
-+/* Connectivity log format:
-+ * [time stamp]   [drm] [Major_minor] [connector name] message.....
-+ * eg:
-+ * [   26.590965] [drm] [Conn_LKTN]	  [DP-1] HBRx4 pass VS=0, PE=0^
-+ * [   26.881060] [drm] [Conn_Mode]	  [DP-1] {2560x1080, 2784x1111@185580Khz}^
-+ */
-+
-+#define CONN_DATA_DETECT(link, hex_data, hex_len, ...) \
-+		dc_conn_log(link->ctx, link, hex_data, hex_len, \
-+				LOG_EVENT_DETECTION, ##__VA_ARGS__)
-+
-+#define CONN_DATA_LINK_LOSS(link, hex_data, hex_len, ...) \
-+		dc_conn_log(link->ctx, link, hex_data, hex_len, \
-+				LOG_EVENT_LINK_LOSS, ##__VA_ARGS__)
-+
-+#define CONN_MSG_LT(link, ...) \
-+		dc_conn_log(link->ctx, link, NULL, 0, \
-+				LOG_EVENT_LINK_TRAINING, ##__VA_ARGS__)
-+
-+#define CONN_MSG_MODE(link, ...) \
-+		dc_conn_log(link->ctx, link, NULL, 0, \
-+				LOG_EVENT_MODE_SET, ##__VA_ARGS__)
-+
-+/*
-+ * Display Test Next logging
-+ */
-+#define DTN_INFO_BEGIN() \
-+	dm_dtn_log_begin(dc_ctx)
-+
-+#define DTN_INFO(msg, ...) \
-+	dm_dtn_log_append_v(dc_ctx, msg, ##__VA_ARGS__)
-+
-+#define DTN_INFO_END() \
-+	dm_dtn_log_end(dc_ctx)
-+
-+#define PERFORMANCE_TRACE_START() \
-+	unsigned long long perf_trc_start_stmp = dm_get_timestamp(dc->ctx); \
-+	unsigned long long perf_trc_start_log_msk = dc->ctx->logger->mask; \
-+	unsigned int perf_trc_start_log_flags = dc->ctx->logger->flags.value; \
-+	if (dc->debug.performance_trace) {\
-+		dm_logger_flush_buffer(dc->ctx->logger, false);\
-+		dc->ctx->logger->mask = 1<<LOG_PERF_TRACE;\
-+		dc->ctx->logger->flags.bits.ENABLE_CONSOLE = 0;\
-+		dc->ctx->logger->flags.bits.ENABLE_BUFFER = 1;\
-+	}
-+
-+#define PERFORMANCE_TRACE_END() do {\
-+	unsigned long long perf_trc_end_stmp = dm_get_timestamp(dc->ctx);\
-+	if (dc->debug.performance_trace) {\
-+		dm_logger_write(dc->ctx->logger, \
-+				LOG_PERF_TRACE, \
-+				"%s duration: %d ticks\n", __func__,\
-+				perf_trc_end_stmp - perf_trc_start_stmp); \
-+		if (perf_trc_start_log_msk != 1<<LOG_PERF_TRACE) {\
-+			dc->ctx->logger->mask = perf_trc_start_log_msk;\
-+			dc->ctx->logger->flags.value = perf_trc_start_log_flags;\
-+			dm_logger_flush_buffer(dc->ctx->logger, false);\
-+		} \
-+	} \
-+} while (0)
-+
-+#endif /* __DAL_LOGGER_INTERFACE_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/include/logger_types.h.0130~	2017-12-14 06:39:58.441903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/logger_types.h	2017-12-14 06:39:58.441903586 +0100
-@@ -0,0 +1,166 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_LOGGER_TYPES_H__
-+#define __DAL_LOGGER_TYPES_H__
-+
-+#include "os_types.h"
-+
-+#define MAX_NAME_LEN 32
-+
-+struct dal_logger;
-+
-+enum dc_log_type {
-+	LOG_ERROR = 0,
-+	LOG_WARNING,
-+	LOG_DEBUG,
-+	LOG_DC,
-+	LOG_DTN,
-+	LOG_SURFACE,
-+	LOG_HW_HOTPLUG,
-+	LOG_HW_LINK_TRAINING,
-+	LOG_HW_SET_MODE,
-+	LOG_HW_RESUME_S3,
-+	LOG_HW_AUDIO,
-+	LOG_HW_HPD_IRQ,
-+	LOG_MST,
-+	LOG_SCALER,
-+	LOG_BIOS,
-+	LOG_BANDWIDTH_CALCS,
-+	LOG_BANDWIDTH_VALIDATION,
-+	LOG_I2C_AUX,
-+	LOG_SYNC,
-+	LOG_BACKLIGHT,
-+	LOG_FEATURE_OVERRIDE,
-+	LOG_DETECTION_EDID_PARSER,
-+	LOG_DETECTION_DP_CAPS,
-+	LOG_RESOURCE,
-+	LOG_DML,
-+	LOG_EVENT_MODE_SET,
-+	LOG_EVENT_DETECTION,
-+	LOG_EVENT_LINK_TRAINING,
-+	LOG_EVENT_LINK_LOSS,
-+	LOG_EVENT_UNDERFLOW,
-+	LOG_IF_TRACE,
-+	LOG_PERF_TRACE,
-+
-+	LOG_SECTION_TOTAL_COUNT
-+};
-+
-+#define DC_MIN_LOG_MASK ((1 << LOG_ERROR) | \
-+		(1 << LOG_DETECTION_EDID_PARSER))
-+
-+#define DC_DEFAULT_LOG_MASK ((1 << LOG_ERROR) | \
-+		(1 << LOG_WARNING) | \
-+		(1 << LOG_EVENT_MODE_SET) | \
-+		(1 << LOG_EVENT_DETECTION) | \
-+		(1 << LOG_EVENT_LINK_TRAINING) | \
-+		(1 << LOG_EVENT_LINK_LOSS) | \
-+		(1 << LOG_EVENT_UNDERFLOW) | \
-+		(1 << LOG_RESOURCE) | \
-+		(1 << LOG_FEATURE_OVERRIDE) | \
-+		(1 << LOG_DETECTION_EDID_PARSER) | \
-+		(1 << LOG_DC) | \
-+		(1 << LOG_HW_HOTPLUG) | \
-+		(1 << LOG_HW_SET_MODE) | \
-+		(1 << LOG_HW_RESUME_S3) | \
-+		(1 << LOG_HW_HPD_IRQ) | \
-+		(1 << LOG_SYNC) | \
-+		(1 << LOG_BANDWIDTH_VALIDATION) | \
-+		(1 << LOG_MST) | \
-+		(1 << LOG_DETECTION_DP_CAPS) | \
-+		(1 << LOG_BACKLIGHT)) | \
-+		(1 << LOG_I2C_AUX) | \
-+		(1 << LOG_IF_TRACE) | \
-+		(1 << LOG_DTN) /* | \
-+		(1 << LOG_DEBUG) | \
-+		(1 << LOG_BIOS) | \
-+		(1 << LOG_SURFACE) | \
-+		(1 << LOG_SCALER) | \
-+		(1 << LOG_DML) | \
-+		(1 << LOG_HW_LINK_TRAINING) | \
-+		(1 << LOG_HW_AUDIO)| \
-+		(1 << LOG_BANDWIDTH_CALCS)*/
-+
-+union logger_flags {
-+	struct {
-+		uint32_t ENABLE_CONSOLE:1; /* Print to console */
-+		uint32_t ENABLE_BUFFER:1; /* Print to buffer */
-+		uint32_t RESERVED:30;
-+	} bits;
-+	uint32_t value;
-+};
-+
-+struct log_entry {
-+	struct dal_logger *logger;
-+	enum dc_log_type type;
-+
-+	char *buf;
-+	uint32_t buf_offset;
-+	uint32_t max_buf_bytes;
-+};
-+
-+/**
-+* Structure for enumerating log types
-+*/
-+struct dc_log_type_info {
-+	enum dc_log_type type;
-+	char name[MAX_NAME_LEN];
-+};
-+
-+/* Structure for keeping track of offsets, buffer, etc */
-+
-+#define DAL_LOGGER_BUFFER_MAX_SIZE 2048
-+
-+/*Connectivity log needs to output EDID, which needs at lease 256x3 bytes,
-+ * change log line size to 896 to meet the request.
-+ */
-+#define LOG_MAX_LINE_SIZE 896
-+
-+struct dal_logger {
-+
-+	/* How far into the circular buffer has been read by dsat
-+	 * Read offset should never cross write offset. Write \0's to
-+	 * read data just to be sure?
-+	 */
-+	uint32_t buffer_read_offset;
-+
-+	/* How far into the circular buffer we have written
-+	 * Write offset should never cross read offset
-+	 */
-+	uint32_t buffer_write_offset;
-+
-+	uint32_t open_count;
-+
-+	char *log_buffer;	/* Pointer to malloc'ed buffer */
-+	uint32_t log_buffer_size; /* Size of circular buffer */
-+
-+	uint32_t mask; /*array of masks for major elements*/
-+
-+	union logger_flags flags;
-+	struct dc_context *ctx;
-+};
-+
-+#endif /* __DAL_LOGGER_TYPES_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/include/set_mode_types.h.0130~	2017-12-14 06:39:58.441903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/set_mode_types.h	2017-12-14 06:39:58.441903586 +0100
-@@ -0,0 +1,107 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_SET_MODE_TYPES_H__
-+#define __DAL_SET_MODE_TYPES_H__
-+
-+#include "dc_types.h"
-+#include <linux/hdmi.h>
-+
-+/* Info frame packet status */
-+enum info_frame_flag {
-+	INFO_PACKET_PACKET_INVALID = 0,
-+	INFO_PACKET_PACKET_VALID = 1,
-+	INFO_PACKET_PACKET_RESET = 2,
-+	INFO_PACKET_PACKET_UPDATE_SCAN_TYPE = 8
-+};
-+
-+struct hdmi_info_frame_header {
-+	uint8_t info_frame_type;
-+	uint8_t version;
-+	uint8_t length;
-+};
-+
-+#pragma pack(push)
-+#pragma pack(1)
-+
-+struct info_packet_raw_data {
-+	uint8_t hb0;
-+	uint8_t hb1;
-+	uint8_t hb2;
-+	uint8_t sb[28]; /* sb0~sb27 */
-+};
-+
-+union hdmi_info_packet {
-+	struct avi_info_frame {
-+		struct hdmi_info_frame_header header;
-+
-+		uint8_t CHECK_SUM:8;
-+
-+		uint8_t S0_S1:2;
-+		uint8_t B0_B1:2;
-+		uint8_t A0:1;
-+		uint8_t Y0_Y1_Y2:3;
-+
-+		uint8_t R0_R3:4;
-+		uint8_t M0_M1:2;
-+		uint8_t C0_C1:2;
-+
-+		uint8_t SC0_SC1:2;
-+		uint8_t Q0_Q1:2;
-+		uint8_t EC0_EC2:3;
-+		uint8_t ITC:1;
-+
-+		uint8_t VIC0_VIC7:8;
-+
-+		uint8_t PR0_PR3:4;
-+		uint8_t CN0_CN1:2;
-+		uint8_t YQ0_YQ1:2;
-+
-+		uint16_t bar_top;
-+		uint16_t bar_bottom;
-+		uint16_t bar_left;
-+		uint16_t bar_right;
-+
-+		uint8_t reserved[14];
-+	} bits;
-+
-+	struct info_packet_raw_data packet_raw_data;
-+};
-+
-+struct info_packet {
-+	enum info_frame_flag flags;
-+	union hdmi_info_packet info_packet_hdmi;
-+};
-+
-+struct info_frame {
-+	struct info_packet avi_info_packet;
-+	struct info_packet gamut_packet;
-+	struct info_packet vendor_info_packet;
-+	struct info_packet spd_info_packet;
-+};
-+
-+#pragma pack(pop)
-+
-+#endif /* __DAL_SET_MODE_TYPES_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/include/signal_types.h.0130~	2017-12-14 06:39:58.441903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/signal_types.h	2017-12-14 06:39:58.441903586 +0100
-@@ -0,0 +1,95 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DC_SIGNAL_TYPES_H__
-+#define __DC_SIGNAL_TYPES_H__
-+
-+enum signal_type {
-+	SIGNAL_TYPE_NONE		= 0L,		/* no signal */
-+	SIGNAL_TYPE_DVI_SINGLE_LINK	= (1 << 0),
-+	SIGNAL_TYPE_DVI_DUAL_LINK	= (1 << 1),
-+	SIGNAL_TYPE_HDMI_TYPE_A		= (1 << 2),
-+	SIGNAL_TYPE_LVDS		= (1 << 3),
-+	SIGNAL_TYPE_RGB			= (1 << 4),
-+	SIGNAL_TYPE_DISPLAY_PORT	= (1 << 5),
-+	SIGNAL_TYPE_DISPLAY_PORT_MST	= (1 << 6),
-+	SIGNAL_TYPE_EDP			= (1 << 7),
-+	SIGNAL_TYPE_VIRTUAL		= (1 << 9),	/* Virtual Display */
-+};
-+
-+/* help functions for signal types manipulation */
-+static inline bool dc_is_hdmi_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_HDMI_TYPE_A);
-+}
-+
-+static inline bool dc_is_dp_sst_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+		signal == SIGNAL_TYPE_EDP);
-+}
-+
-+static inline bool dc_is_dp_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+		signal == SIGNAL_TYPE_EDP ||
-+		signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
-+}
-+
-+static inline bool dc_is_embedded_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_EDP || signal == SIGNAL_TYPE_LVDS);
-+}
-+
-+static inline bool dc_is_dvi_signal(enum signal_type signal)
-+{
-+	switch (signal) {
-+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
-+	case SIGNAL_TYPE_DVI_DUAL_LINK:
-+		return true;
-+	break;
-+	default:
-+		return false;
-+	}
-+}
-+
-+static inline bool dc_is_dvi_single_link_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_DVI_SINGLE_LINK);
-+}
-+
-+static inline bool dc_is_dual_link_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_DVI_DUAL_LINK);
-+}
-+
-+static inline bool dc_is_audio_capable_signal(enum signal_type signal)
-+{
-+	return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
-+		signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
-+		dc_is_hdmi_signal(signal));
-+}
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/include/vector.h.0130~	2017-12-14 06:39:58.441903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/include/vector.h	2017-12-14 06:39:58.441903586 +0100
-@@ -0,0 +1,150 @@
-+/*
-+ * Copyright 2012-15 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef __DAL_VECTOR_H__
-+#define __DAL_VECTOR_H__
-+
-+struct vector {
-+	uint8_t *container;
-+	uint32_t struct_size;
-+	uint32_t count;
-+	uint32_t capacity;
-+	struct dc_context *ctx;
-+};
-+
-+bool dal_vector_construct(
-+	struct vector *vector,
-+	struct dc_context *ctx,
-+	uint32_t capacity,
-+	uint32_t struct_size);
-+
-+struct vector *dal_vector_create(
-+	struct dc_context *ctx,
-+	uint32_t capacity,
-+	uint32_t struct_size);
-+
-+/* 'initial_value' is optional. If initial_value not supplied,
-+ * each "structure" in the vector will contain zeros by default. */
-+struct vector *dal_vector_presized_create(
-+	struct dc_context *ctx,
-+	uint32_t size,
-+	void *initial_value,
-+	uint32_t struct_size);
-+
-+void dal_vector_destruct(
-+	struct vector *vector);
-+
-+void dal_vector_destroy(
-+	struct vector **vector);
-+
-+uint32_t dal_vector_get_count(
-+	const struct vector *vector);
-+
-+/* dal_vector_insert_at
-+ * reallocate container if necessary
-+ * then shell items at right and insert
-+ * return if the container modified
-+ * do not check that index belongs to container
-+ * since the function is private and index is going to be calculated
-+ * either with by function or as get_count+1 */
-+bool dal_vector_insert_at(
-+	struct vector *vector,
-+	const void *what,
-+	uint32_t position);
-+
-+bool dal_vector_append(
-+	struct vector *vector,
-+	const void *item);
-+
-+/* operator[] */
-+void *dal_vector_at_index(
-+	const struct vector *vector,
-+	uint32_t index);
-+
-+void dal_vector_set_at_index(
-+	const struct vector *vector,
-+	const void *what,
-+	uint32_t index);
-+
-+/* create a clone (copy) of a vector */
-+struct vector *dal_vector_clone(
-+	const struct vector *vector_other);
-+
-+/* dal_vector_remove_at_index
-+ * Shifts elements on the right from remove position to the left,
-+ * removing an element at position by overwrite means*/
-+bool dal_vector_remove_at_index(
-+	struct vector *vector,
-+	uint32_t index);
-+
-+uint32_t dal_vector_capacity(const struct vector *vector);
-+
-+bool dal_vector_reserve(struct vector *vector, uint32_t capacity);
-+
-+void dal_vector_clear(struct vector *vector);
-+
-+/***************************************************************************
-+ * Macro definitions of TYPE-SAFE versions of vector set/get functions.
-+ ***************************************************************************/
-+
-+#define DAL_VECTOR_INSERT_AT(vector_type, type_t) \
-+	static bool vector_type##_vector_insert_at( \
-+		struct vector *vector, \
-+		type_t what, \
-+		uint32_t position) \
-+{ \
-+	return dal_vector_insert_at(vector, what, position); \
-+}
-+
-+#define DAL_VECTOR_APPEND(vector_type, type_t) \
-+	static bool vector_type##_vector_append( \
-+		struct vector *vector, \
-+		type_t item) \
-+{ \
-+	return dal_vector_append(vector, item); \
-+}
-+
-+/* Note: "type_t" is the ONLY token accepted by "checkpatch.pl" and by
-+ * "checkcommit" as *return type*.
-+ * For uniformity reasons "type_t" is used for all type-safe macro
-+ * definitions here. */
-+#define DAL_VECTOR_AT_INDEX(vector_type, type_t) \
-+	static type_t vector_type##_vector_at_index( \
-+		const struct vector *vector, \
-+		uint32_t index) \
-+{ \
-+	return dal_vector_at_index(vector, index); \
-+}
-+
-+#define DAL_VECTOR_SET_AT_INDEX(vector_type, type_t) \
-+	static void vector_type##_vector_set_at_index( \
-+		const struct vector *vector, \
-+		type_t what, \
-+		uint32_t index) \
-+{ \
-+	dal_vector_set_at_index(vector, what, index); \
-+}
-+
-+#endif /* __DAL_VECTOR_H__ */
---- linux-4.14/drivers/gpu/drm/amd/display/Kconfig.0130~	2017-12-14 06:39:58.441903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/Kconfig	2017-12-14 06:39:58.441903586 +0100
-@@ -0,0 +1,45 @@
-+menu "Display Engine Configuration"
-+	depends on DRM && DRM_AMDGPU
-+
-+config DRM_AMD_DC
-+	bool "AMD DC - Enable new display engine"
-+	default y
-+	help
-+	  Choose this option if you want to use the new display engine
-+	  support for AMDGPU. This adds required support for Vega and
-+	  Raven ASICs.
-+
-+config DRM_AMD_DC_PRE_VEGA
-+	bool "DC support for Polaris and older ASICs"
-+	default y
-+	help
-+	  Choose this option to enable the new DC support for older asics
-+	  by default. This includes Polaris, Carrizo, Tonga, Bonaire,
-+	  and Hawaii.
-+
-+config DRM_AMD_DC_FBC
-+	bool "AMD FBC - Enable Frame Buffer Compression"
-+	depends on DRM_AMD_DC
-+	help
-+	  Choose this option if you want to use frame buffer compression
-+	  support.
-+	  This is a power optimisation feature, check its availability
-+	  on your hardware before enabling this option.
-+
-+
-+config DRM_AMD_DC_DCN1_0
-+	bool "DCN 1.0 Raven family"
-+	depends on DRM_AMD_DC && X86
-+	help
-+	  Choose this option if you want to have
-+	  RV family for display engine
-+
-+config DEBUG_KERNEL_DC
-+	bool "Enable kgdb break in DC"
-+	depends on DRM_AMD_DC
-+	help
-+	  Choose this option
-+	  if you want to hit
-+	  kdgb_break in assert.
-+
-+endmenu
---- linux-4.14/drivers/gpu/drm/amd/display/Makefile.0130~	2017-12-14 06:39:58.441903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/Makefile	2017-12-14 06:39:58.441903586 +0100
-@@ -0,0 +1,22 @@
-+#
-+# Makefile for the DAL (Display Abstract Layer), which is a  sub-component
-+# of the AMDGPU drm driver.
-+# It provides the HW control for display related functionalities.
-+
-+AMDDALPATH = $(RELATIVE_AMD_DISPLAY_PATH)
-+
-+subdir-ccflags-y += -I$(AMDDALPATH)/ -I$(AMDDALPATH)/include
-+
-+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/inc/
-+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/inc/hw
-+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/inc
-+subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/freesync
-+
-+#TODO: remove when Timing Sync feature is complete
-+subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0
-+
-+DAL_LIBS = amdgpu_dm dc	modules/freesync
-+
-+AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/,$(DAL_LIBS)))
-+
-+include $(AMD_DAL)
---- linux-4.14/drivers/gpu/drm/amd/display/modules/freesync/freesync.c.0130~	2017-12-14 06:39:58.442903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/modules/freesync/freesync.c	2017-12-14 06:39:58.442903586 +0100
-@@ -0,0 +1,1459 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#include "dm_services.h"
-+#include "dc.h"
-+#include "mod_freesync.h"
-+#include "core_types.h"
-+
-+#define MOD_FREESYNC_MAX_CONCURRENT_STREAMS  32
-+
-+/* Refresh rate ramp at a fixed rate of 65 Hz/second */
-+#define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
-+/* Number of elements in the render times cache array */
-+#define RENDER_TIMES_MAX_COUNT 20
-+/* Threshold to exit BTR (to avoid frequent enter-exits at the lower limit) */
-+#define BTR_EXIT_MARGIN 2000
-+/* Number of consecutive frames to check before entering/exiting fixed refresh*/
-+#define FIXED_REFRESH_ENTER_FRAME_COUNT 5
-+#define FIXED_REFRESH_EXIT_FRAME_COUNT 5
-+
-+#define FREESYNC_REGISTRY_NAME "freesync_v1"
-+
-+#define FREESYNC_NO_STATIC_FOR_EXTERNAL_DP_REGKEY "DalFreeSyncNoStaticForExternalDp"
-+
-+#define FREESYNC_NO_STATIC_FOR_INTERNAL_REGKEY "DalFreeSyncNoStaticForInternal"
-+
-+struct gradual_static_ramp {
-+	bool ramp_is_active;
-+	bool ramp_direction_is_up;
-+	unsigned int ramp_current_frame_duration_in_ns;
-+};
-+
-+struct time_cache {
-+	/* video (48Hz feature) related */
-+	unsigned int update_duration_in_ns;
-+
-+	/* BTR/fixed refresh related */
-+	unsigned int prev_time_stamp_in_us;
-+
-+	unsigned int min_render_time_in_us;
-+	unsigned int max_render_time_in_us;
-+
-+	unsigned int render_times_index;
-+	unsigned int render_times[RENDER_TIMES_MAX_COUNT];
-+};
-+
-+struct below_the_range {
-+	bool btr_active;
-+	bool program_btr;
-+
-+	unsigned int mid_point_in_us;
-+
-+	unsigned int inserted_frame_duration_in_us;
-+	unsigned int frames_to_insert;
-+	unsigned int frame_counter;
-+};
-+
-+struct fixed_refresh {
-+	bool fixed_active;
-+	bool program_fixed;
-+	unsigned int frame_counter;
-+};
-+
-+struct freesync_range {
-+	unsigned int min_refresh;
-+	unsigned int max_frame_duration;
-+	unsigned int vmax;
-+
-+	unsigned int max_refresh;
-+	unsigned int min_frame_duration;
-+	unsigned int vmin;
-+};
-+
-+struct freesync_state {
-+	bool fullscreen;
-+	bool static_screen;
-+	bool video;
-+
-+	unsigned int nominal_refresh_rate_in_micro_hz;
-+	bool windowed_fullscreen;
-+
-+	struct time_cache time;
-+
-+	struct gradual_static_ramp static_ramp;
-+	struct below_the_range btr;
-+	struct fixed_refresh fixed_refresh;
-+	struct freesync_range freesync_range;
-+};
-+
-+struct freesync_entity {
-+	struct dc_stream_state *stream;
-+	struct mod_freesync_caps *caps;
-+	struct freesync_state state;
-+	struct mod_freesync_user_enable user_enable;
-+};
-+
-+struct freesync_registry_options {
-+	bool drr_external_supported;
-+	bool drr_internal_supported;
-+};
-+
-+struct core_freesync {
-+	struct mod_freesync public;
-+	struct dc *dc;
-+	struct freesync_entity *map;
-+	int num_entities;
-+	struct freesync_registry_options opts;
-+};
-+
-+#define MOD_FREESYNC_TO_CORE(mod_freesync)\
-+		container_of(mod_freesync, struct core_freesync, public)
-+
-+struct mod_freesync *mod_freesync_create(struct dc *dc)
-+{
-+	struct core_freesync *core_freesync =
-+			kzalloc(sizeof(struct core_freesync), GFP_KERNEL);
-+
-+
-+	struct persistent_data_flag flag;
-+
-+	int i, data = 0;
-+
-+	if (core_freesync == NULL)
-+		goto fail_alloc_context;
-+
-+	core_freesync->map = kzalloc(sizeof(struct freesync_entity) * MOD_FREESYNC_MAX_CONCURRENT_STREAMS,
-+				     GFP_KERNEL);
-+
-+	if (core_freesync->map == NULL)
-+		goto fail_alloc_map;
-+
-+	for (i = 0; i < MOD_FREESYNC_MAX_CONCURRENT_STREAMS; i++)
-+		core_freesync->map[i].stream = NULL;
-+
-+	core_freesync->num_entities = 0;
-+
-+	if (dc == NULL)
-+		goto fail_construct;
-+
-+	core_freesync->dc = dc;
-+
-+	/* Create initial module folder in registry for freesync enable data */
-+	flag.save_per_edid = true;
-+	flag.save_per_link = false;
-+	dm_write_persistent_data(dc->ctx, NULL, FREESYNC_REGISTRY_NAME,
-+			NULL, NULL, 0, &flag);
-+	flag.save_per_edid = false;
-+	flag.save_per_link = false;
-+
-+	if (dm_read_persistent_data(dc->ctx, NULL, NULL,
-+			FREESYNC_NO_STATIC_FOR_INTERNAL_REGKEY,
-+			&data, sizeof(data), &flag)) {
-+		core_freesync->opts.drr_internal_supported =
-+			(data & 1) ? false : true;
-+	}
-+
-+	if (dm_read_persistent_data(dc->ctx, NULL, NULL,
-+			FREESYNC_NO_STATIC_FOR_EXTERNAL_DP_REGKEY,
-+			&data, sizeof(data), &flag)) {
-+		core_freesync->opts.drr_external_supported =
-+				(data & 1) ? false : true;
-+	}
-+
-+	return &core_freesync->public;
-+
-+fail_construct:
-+	kfree(core_freesync->map);
-+
-+fail_alloc_map:
-+	kfree(core_freesync);
-+
-+fail_alloc_context:
-+	return NULL;
-+}
-+
-+void mod_freesync_destroy(struct mod_freesync *mod_freesync)
-+{
-+	if (mod_freesync != NULL) {
-+		int i;
-+		struct core_freesync *core_freesync =
-+				MOD_FREESYNC_TO_CORE(mod_freesync);
-+
-+		for (i = 0; i < core_freesync->num_entities; i++)
-+			if (core_freesync->map[i].stream)
-+				dc_stream_release(core_freesync->map[i].stream);
-+
-+		kfree(core_freesync->map);
-+
-+		kfree(core_freesync);
-+	}
-+}
-+
-+/* Given a specific dc_stream* this function finds its equivalent
-+ * on the core_freesync->map and returns the corresponding index
-+ */
-+static unsigned int map_index_from_stream(struct core_freesync *core_freesync,
-+		struct dc_stream_state *stream)
-+{
-+	unsigned int index = 0;
-+
-+	for (index = 0; index < core_freesync->num_entities; index++) {
-+		if (core_freesync->map[index].stream == stream) {
-+			return index;
-+		}
-+	}
-+	/* Could not find stream requested */
-+	ASSERT(false);
-+	return index;
-+}
-+
-+bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream, struct mod_freesync_caps *caps)
-+{
-+	struct dc  *dc = NULL;
-+	struct core_freesync *core_freesync = NULL;
-+	int persistent_freesync_enable = 0;
-+	struct persistent_data_flag flag;
-+	unsigned int nom_refresh_rate_uhz;
-+	unsigned long long temp;
-+
-+	if (mod_freesync == NULL)
-+		return false;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+	dc = core_freesync->dc;
-+
-+	flag.save_per_edid = true;
-+	flag.save_per_link = false;
-+
-+	if (core_freesync->num_entities < MOD_FREESYNC_MAX_CONCURRENT_STREAMS) {
-+
-+		dc_stream_retain(stream);
-+
-+		temp = stream->timing.pix_clk_khz;
-+		temp *= 1000ULL * 1000ULL * 1000ULL;
-+		temp = div_u64(temp, stream->timing.h_total);
-+		temp = div_u64(temp, stream->timing.v_total);
-+
-+		nom_refresh_rate_uhz = (unsigned int) temp;
-+
-+		core_freesync->map[core_freesync->num_entities].stream = stream;
-+		core_freesync->map[core_freesync->num_entities].caps = caps;
-+
-+		core_freesync->map[core_freesync->num_entities].state.
-+			fullscreen = false;
-+		core_freesync->map[core_freesync->num_entities].state.
-+			static_screen = false;
-+		core_freesync->map[core_freesync->num_entities].state.
-+			video = false;
-+		core_freesync->map[core_freesync->num_entities].state.time.
-+			update_duration_in_ns = 0;
-+		core_freesync->map[core_freesync->num_entities].state.
-+			static_ramp.ramp_is_active = false;
-+
-+		/* get persistent data from registry */
-+		if (dm_read_persistent_data(dc->ctx, stream->sink,
-+					FREESYNC_REGISTRY_NAME,
-+					"userenable", &persistent_freesync_enable,
-+					sizeof(int), &flag)) {
-+			core_freesync->map[core_freesync->num_entities].user_enable.
-+				enable_for_gaming =
-+				(persistent_freesync_enable & 1) ? true : false;
-+			core_freesync->map[core_freesync->num_entities].user_enable.
-+				enable_for_static =
-+				(persistent_freesync_enable & 2) ? true : false;
-+			core_freesync->map[core_freesync->num_entities].user_enable.
-+				enable_for_video =
-+				(persistent_freesync_enable & 4) ? true : false;
-+		} else {
-+			core_freesync->map[core_freesync->num_entities].user_enable.
-+					enable_for_gaming = false;
-+			core_freesync->map[core_freesync->num_entities].user_enable.
-+					enable_for_static = false;
-+			core_freesync->map[core_freesync->num_entities].user_enable.
-+					enable_for_video = false;
-+		}
-+
-+		if (caps->supported &&
-+			nom_refresh_rate_uhz >= caps->min_refresh_in_micro_hz &&
-+			nom_refresh_rate_uhz <= caps->max_refresh_in_micro_hz)
-+			stream->ignore_msa_timing_param = 1;
-+
-+		core_freesync->num_entities++;
-+		return true;
-+	}
-+	return false;
-+}
-+
-+bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream)
-+{
-+	int i = 0;
-+	struct core_freesync *core_freesync = NULL;
-+	unsigned int index = 0;
-+
-+	if (mod_freesync == NULL)
-+		return false;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+	index = map_index_from_stream(core_freesync, stream);
-+
-+	dc_stream_release(core_freesync->map[index].stream);
-+	core_freesync->map[index].stream = NULL;
-+	/* To remove this entity, shift everything after down */
-+	for (i = index; i < core_freesync->num_entities - 1; i++)
-+		core_freesync->map[i] = core_freesync->map[i + 1];
-+	core_freesync->num_entities--;
-+	return true;
-+}
-+
-+static void update_stream_freesync_context(struct core_freesync *core_freesync,
-+		struct dc_stream_state *stream)
-+{
-+	unsigned int index;
-+	struct freesync_context *ctx;
-+
-+	ctx = &stream->freesync_ctx;
-+
-+	index = map_index_from_stream(core_freesync, stream);
-+
-+	ctx->supported = core_freesync->map[index].caps->supported;
-+	ctx->enabled = (core_freesync->map[index].user_enable.enable_for_gaming ||
-+		core_freesync->map[index].user_enable.enable_for_video ||
-+		core_freesync->map[index].user_enable.enable_for_static);
-+	ctx->active = (core_freesync->map[index].state.fullscreen ||
-+		core_freesync->map[index].state.video ||
-+		core_freesync->map[index].state.static_ramp.ramp_is_active);
-+	ctx->min_refresh_in_micro_hz =
-+			core_freesync->map[index].caps->min_refresh_in_micro_hz;
-+	ctx->nominal_refresh_in_micro_hz = core_freesync->
-+		map[index].state.nominal_refresh_rate_in_micro_hz;
-+
-+}
-+
-+static void update_stream(struct core_freesync *core_freesync,
-+		struct dc_stream_state *stream)
-+{
-+	unsigned int index = map_index_from_stream(core_freesync, stream);
-+	if (core_freesync->map[index].caps->supported) {
-+		stream->ignore_msa_timing_param = 1;
-+		update_stream_freesync_context(core_freesync, stream);
-+	}
-+}
-+
-+static void calc_freesync_range(struct core_freesync *core_freesync,
-+		struct dc_stream_state *stream,
-+		struct freesync_state *state,
-+		unsigned int min_refresh_in_uhz,
-+		unsigned int max_refresh_in_uhz)
-+{
-+	unsigned int min_frame_duration_in_ns = 0, max_frame_duration_in_ns = 0;
-+	unsigned int index = map_index_from_stream(core_freesync, stream);
-+	uint32_t vtotal = stream->timing.v_total;
-+
-+	if ((min_refresh_in_uhz == 0) || (max_refresh_in_uhz == 0)) {
-+		state->freesync_range.min_refresh =
-+				state->nominal_refresh_rate_in_micro_hz;
-+		state->freesync_range.max_refresh =
-+				state->nominal_refresh_rate_in_micro_hz;
-+
-+		state->freesync_range.max_frame_duration = 0;
-+		state->freesync_range.min_frame_duration = 0;
-+
-+		state->freesync_range.vmax = vtotal;
-+		state->freesync_range.vmin = vtotal;
-+
-+		return;
-+	}
-+
-+	min_frame_duration_in_ns = ((unsigned int) (div64_u64(
-+					(1000000000ULL * 1000000),
-+					max_refresh_in_uhz)));
-+	max_frame_duration_in_ns = ((unsigned int) (div64_u64(
-+		(1000000000ULL * 1000000),
-+		min_refresh_in_uhz)));
-+
-+	state->freesync_range.min_refresh = min_refresh_in_uhz;
-+	state->freesync_range.max_refresh = max_refresh_in_uhz;
-+
-+	state->freesync_range.max_frame_duration = max_frame_duration_in_ns;
-+	state->freesync_range.min_frame_duration = min_frame_duration_in_ns;
-+
-+	state->freesync_range.vmax = div64_u64(div64_u64(((unsigned long long)(
-+		max_frame_duration_in_ns) * stream->timing.pix_clk_khz),
-+		stream->timing.h_total), 1000000);
-+	state->freesync_range.vmin = div64_u64(div64_u64(((unsigned long long)(
-+		min_frame_duration_in_ns) * stream->timing.pix_clk_khz),
-+		stream->timing.h_total), 1000000);
-+
-+	/* vmin/vmax cannot be less than vtotal */
-+	if (state->freesync_range.vmin < vtotal) {
-+		/* Error of 1 is permissible */
-+		ASSERT((state->freesync_range.vmin + 1) >= vtotal);
-+		state->freesync_range.vmin = vtotal;
-+	}
-+
-+	if (state->freesync_range.vmax < vtotal) {
-+		/* Error of 1 is permissible */
-+		ASSERT((state->freesync_range.vmax + 1) >= vtotal);
-+		state->freesync_range.vmax = vtotal;
-+	}
-+
-+	/* Determine whether BTR can be supported */
-+	if (max_frame_duration_in_ns >=
-+			2 * min_frame_duration_in_ns)
-+		core_freesync->map[index].caps->btr_supported = true;
-+	else
-+		core_freesync->map[index].caps->btr_supported = false;
-+
-+	/* Cache the time variables */
-+	state->time.max_render_time_in_us =
-+		max_frame_duration_in_ns / 1000;
-+	state->time.min_render_time_in_us =
-+		min_frame_duration_in_ns / 1000;
-+	state->btr.mid_point_in_us =
-+		(max_frame_duration_in_ns +
-+		min_frame_duration_in_ns) / 2000;
-+}
-+
-+static void calc_v_total_from_duration(struct dc_stream_state *stream,
-+		unsigned int duration_in_ns, int *v_total_nominal)
-+{
-+	*v_total_nominal = div64_u64(div64_u64(((unsigned long long)(
-+				duration_in_ns) * stream->timing.pix_clk_khz),
-+				stream->timing.h_total), 1000000);
-+}
-+
-+static void calc_v_total_for_static_ramp(struct core_freesync *core_freesync,
-+		struct dc_stream_state *stream,
-+		unsigned int index, int *v_total)
-+{
-+	unsigned int frame_duration = 0;
-+
-+	struct gradual_static_ramp *static_ramp_variables =
-+				&core_freesync->map[index].state.static_ramp;
-+
-+	/* Calc ratio between new and current frame duration with 3 digit */
-+	unsigned int frame_duration_ratio = div64_u64(1000000,
-+		(1000 +  div64_u64(((unsigned long long)(
-+		STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) *
-+		static_ramp_variables->ramp_current_frame_duration_in_ns),
-+		1000000000)));
-+
-+	/* Calculate delta between new and current frame duration in ns */
-+	unsigned int frame_duration_delta = div64_u64(((unsigned long long)(
-+		static_ramp_variables->ramp_current_frame_duration_in_ns) *
-+		(1000 - frame_duration_ratio)), 1000);
-+
-+	/* Adjust frame duration delta based on ratio between current and
-+	 * standard frame duration (frame duration at 60 Hz refresh rate).
-+	 */
-+	unsigned int ramp_rate_interpolated = div64_u64(((unsigned long long)(
-+		frame_duration_delta) * static_ramp_variables->
-+		ramp_current_frame_duration_in_ns), 16666666);
-+
-+	/* Going to a higher refresh rate (lower frame duration) */
-+	if (static_ramp_variables->ramp_direction_is_up) {
-+		/* reduce frame duration */
-+		static_ramp_variables->ramp_current_frame_duration_in_ns -=
-+			ramp_rate_interpolated;
-+
-+		/* min frame duration */
-+		frame_duration = ((unsigned int) (div64_u64(
-+			(1000000000ULL * 1000000),
-+			core_freesync->map[index].state.
-+			nominal_refresh_rate_in_micro_hz)));
-+
-+		/* adjust for frame duration below min */
-+		if (static_ramp_variables->ramp_current_frame_duration_in_ns <=
-+			frame_duration) {
-+
-+			static_ramp_variables->ramp_is_active = false;
-+			static_ramp_variables->
-+				ramp_current_frame_duration_in_ns =
-+				frame_duration;
-+		}
-+	/* Going to a lower refresh rate (larger frame duration) */
-+	} else {
-+		/* increase frame duration */
-+		static_ramp_variables->ramp_current_frame_duration_in_ns +=
-+			ramp_rate_interpolated;
-+
-+		/* max frame duration */
-+		frame_duration = ((unsigned int) (div64_u64(
-+			(1000000000ULL * 1000000),
-+			core_freesync->map[index].caps->min_refresh_in_micro_hz)));
-+
-+		/* adjust for frame duration above max */
-+		if (static_ramp_variables->ramp_current_frame_duration_in_ns >=
-+			frame_duration) {
-+
-+			static_ramp_variables->ramp_is_active = false;
-+			static_ramp_variables->
-+				ramp_current_frame_duration_in_ns =
-+				frame_duration;
-+		}
-+	}
-+
-+	calc_v_total_from_duration(stream, static_ramp_variables->
-+		ramp_current_frame_duration_in_ns, v_total);
-+}
-+
-+static void reset_freesync_state_variables(struct freesync_state* state)
-+{
-+	state->static_ramp.ramp_is_active = false;
-+	if (state->nominal_refresh_rate_in_micro_hz)
-+		state->static_ramp.ramp_current_frame_duration_in_ns =
-+			((unsigned int) (div64_u64(
-+			(1000000000ULL * 1000000),
-+			state->nominal_refresh_rate_in_micro_hz)));
-+
-+	state->btr.btr_active = false;
-+	state->btr.frame_counter = 0;
-+	state->btr.frames_to_insert = 0;
-+	state->btr.inserted_frame_duration_in_us = 0;
-+	state->btr.program_btr = false;
-+
-+	state->fixed_refresh.fixed_active = false;
-+	state->fixed_refresh.program_fixed = false;
-+}
-+/*
-+ * Sets freesync mode on a stream depending on current freesync state.
-+ */
-+static bool set_freesync_on_streams(struct core_freesync *core_freesync,
-+		struct dc_stream_state **streams, int num_streams)
-+{
-+	int v_total_nominal = 0, v_total_min = 0, v_total_max = 0;
-+	unsigned int stream_idx, map_index = 0;
-+	struct freesync_state *state;
-+
-+	if (num_streams == 0 || streams == NULL || num_streams > 1)
-+		return false;
-+
-+	for (stream_idx = 0; stream_idx < num_streams; stream_idx++) {
-+
-+		map_index = map_index_from_stream(core_freesync,
-+				streams[stream_idx]);
-+
-+		state = &core_freesync->map[map_index].state;
-+
-+		if (core_freesync->map[map_index].caps->supported) {
-+
-+			/* Fullscreen has the topmost priority. If the
-+			 * fullscreen bit is set, we are in a fullscreen
-+			 * application where it should not matter if it is
-+			 * static screen. We should not check the static_screen
-+			 * or video bit.
-+			 *
-+			 * Special cases of fullscreen include btr and fixed
-+			 * refresh. We program btr on every flip and involves
-+			 * programming full range right before the last inserted frame.
-+			 * However, we do not want to program the full freesync range
-+			 * when fixed refresh is active, because we only program
-+			 * that logic once and this will override it.
-+			 */
-+			if (core_freesync->map[map_index].user_enable.
-+				enable_for_gaming == true &&
-+				state->fullscreen == true &&
-+				state->fixed_refresh.fixed_active == false) {
-+				/* Enable freesync */
-+
-+				v_total_min = state->freesync_range.vmin;
-+				v_total_max = state->freesync_range.vmax;
-+
-+				/* Update the freesync context for the stream */
-+				update_stream_freesync_context(core_freesync,
-+						streams[stream_idx]);
-+
-+				dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
-+							   num_streams, v_total_min,
-+							   v_total_max);
-+
-+				return true;
-+
-+			} else if (core_freesync->map[map_index].user_enable.
-+				enable_for_video && state->video == true) {
-+				/* Enable 48Hz feature */
-+
-+				calc_v_total_from_duration(streams[stream_idx],
-+					state->time.update_duration_in_ns,
-+					&v_total_nominal);
-+
-+				/* Program only if v_total_nominal is in range*/
-+				if (v_total_nominal >=
-+					streams[stream_idx]->timing.v_total) {
-+
-+					/* Update the freesync context for
-+					 * the stream
-+					 */
-+					update_stream_freesync_context(
-+						core_freesync,
-+						streams[stream_idx]);
-+
-+					dc_stream_adjust_vmin_vmax(
-+						core_freesync->dc, streams,
-+						num_streams, v_total_nominal,
-+						v_total_nominal);
-+				}
-+				return true;
-+
-+			} else {
-+				/* Disable freesync */
-+				v_total_nominal = streams[stream_idx]->
-+					timing.v_total;
-+
-+				/* Update the freesync context for
-+				 * the stream
-+				 */
-+				update_stream_freesync_context(
-+					core_freesync,
-+					streams[stream_idx]);
-+
-+				dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
-+							   num_streams, v_total_nominal,
-+							   v_total_nominal);
-+
-+				/* Reset the cached variables */
-+				reset_freesync_state_variables(state);
-+
-+				return true;
-+			}
-+		} else {
-+			/* Disable freesync */
-+			v_total_nominal = streams[stream_idx]->
-+				timing.v_total;
-+			/*
-+			 * we have to reset drr always even sink does
-+			 * not support freesync because a former stream has
-+			 * be programmed
-+			 */
-+			dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
-+						   num_streams, v_total_nominal,
-+						   v_total_nominal);
-+			/* Reset the cached variables */
-+			reset_freesync_state_variables(state);
-+		}
-+
-+	}
-+
-+	return false;
-+}
-+
-+static void set_static_ramp_variables(struct core_freesync *core_freesync,
-+		unsigned int index, bool enable_static_screen)
-+{
-+	unsigned int frame_duration = 0;
-+	unsigned int nominal_refresh_rate = core_freesync->map[index].state.
-+			nominal_refresh_rate_in_micro_hz;
-+	unsigned int min_refresh_rate= core_freesync->map[index].caps->
-+			min_refresh_in_micro_hz;
-+	struct gradual_static_ramp *static_ramp_variables =
-+			&core_freesync->map[index].state.static_ramp;
-+
-+	/* If we are ENABLING static screen, refresh rate should go DOWN.
-+	 * If we are DISABLING static screen, refresh rate should go UP.
-+	 */
-+	if (enable_static_screen)
-+		static_ramp_variables->ramp_direction_is_up = false;
-+	else
-+		static_ramp_variables->ramp_direction_is_up = true;
-+
-+	/* If ramp is not active, set initial frame duration depending on
-+	 * whether we are enabling/disabling static screen mode. If the ramp is
-+	 * already active, ramp should continue in the opposite direction
-+	 * starting with the current frame duration
-+	 */
-+	if (!static_ramp_variables->ramp_is_active) {
-+		if (enable_static_screen == true) {
-+			/* Going to lower refresh rate, so start from max
-+			 * refresh rate (min frame duration)
-+			 */
-+			frame_duration = ((unsigned int) (div64_u64(
-+				(1000000000ULL * 1000000),
-+				nominal_refresh_rate)));
-+		} else {
-+			/* Going to higher refresh rate, so start from min
-+			 * refresh rate (max frame duration)
-+			 */
-+			frame_duration = ((unsigned int) (div64_u64(
-+				(1000000000ULL * 1000000),
-+				min_refresh_rate)));
-+		}
-+		static_ramp_variables->
-+			ramp_current_frame_duration_in_ns = frame_duration;
-+
-+		static_ramp_variables->ramp_is_active = true;
-+	}
-+}
-+
-+void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state **streams, int num_streams)
-+{
-+	unsigned int index, v_total, inserted_frame_v_total = 0;
-+	unsigned int min_frame_duration_in_ns, vmax, vmin = 0;
-+	struct freesync_state *state;
-+	struct core_freesync *core_freesync = NULL;
-+	struct dc_static_screen_events triggers = {0};
-+
-+	if (mod_freesync == NULL)
-+		return;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+
-+	if (core_freesync->num_entities == 0)
-+		return;
-+
-+	index = map_index_from_stream(core_freesync,
-+		streams[0]);
-+
-+	if (core_freesync->map[index].caps->supported == false)
-+		return;
-+
-+	state = &core_freesync->map[index].state;
-+
-+	/* Below the Range Logic */
-+
-+	/* Only execute if in fullscreen mode */
-+	if (state->fullscreen == true &&
-+		core_freesync->map[index].user_enable.enable_for_gaming &&
-+		core_freesync->map[index].caps->btr_supported &&
-+		state->btr.btr_active) {
-+
-+		/* TODO: pass in flag for Pre-DCE12 ASIC
-+		 * in order for frame variable duration to take affect,
-+		 * it needs to be done one VSYNC early, which is at
-+		 * frameCounter == 1.
-+		 * For DCE12 and newer updates to V_TOTAL_MIN/MAX
-+		 * will take affect on current frame
-+		 */
-+		if (state->btr.frames_to_insert == state->btr.frame_counter) {
-+
-+			min_frame_duration_in_ns = ((unsigned int) (div64_u64(
-+					(1000000000ULL * 1000000),
-+					state->nominal_refresh_rate_in_micro_hz)));
-+
-+			vmin = state->freesync_range.vmin;
-+
-+			inserted_frame_v_total = vmin;
-+
-+			if (min_frame_duration_in_ns / 1000)
-+				inserted_frame_v_total =
-+					state->btr.inserted_frame_duration_in_us *
-+					vmin / (min_frame_duration_in_ns / 1000);
-+
-+			/* Set length of inserted frames as v_total_max*/
-+			vmax = inserted_frame_v_total;
-+			vmin = inserted_frame_v_total;
-+
-+			/* Program V_TOTAL */
-+			dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
-+						   num_streams, vmin, vmax);
-+		}
-+
-+		if (state->btr.frame_counter > 0)
-+			state->btr.frame_counter--;
-+
-+		/* Restore FreeSync */
-+		if (state->btr.frame_counter == 0)
-+			set_freesync_on_streams(core_freesync, streams, num_streams);
-+	}
-+
-+	/* If in fullscreen freesync mode or in video, do not program
-+	 * static screen ramp values
-+	 */
-+	if (state->fullscreen == true || state->video == true) {
-+
-+		state->static_ramp.ramp_is_active = false;
-+
-+		return;
-+	}
-+
-+	/* Gradual Static Screen Ramping Logic */
-+
-+	/* Execute if ramp is active and user enabled freesync static screen*/
-+	if (state->static_ramp.ramp_is_active &&
-+		core_freesync->map[index].user_enable.enable_for_static) {
-+
-+		calc_v_total_for_static_ramp(core_freesync, streams[0],
-+				index, &v_total);
-+
-+		/* Update the freesync context for the stream */
-+		update_stream_freesync_context(core_freesync, streams[0]);
-+
-+		/* Program static screen ramp values */
-+		dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
-+					   num_streams, v_total,
-+					   v_total);
-+
-+		triggers.overlay_update = true;
-+		triggers.surface_update = true;
-+
-+		dc_stream_set_static_screen_events(core_freesync->dc, streams,
-+						   num_streams, &triggers);
-+	}
-+}
-+
-+void mod_freesync_update_state(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state **streams, int num_streams,
-+		struct mod_freesync_params *freesync_params)
-+{
-+	bool freesync_program_required = false;
-+	unsigned int stream_index;
-+	struct freesync_state *state;
-+	struct core_freesync *core_freesync = NULL;
-+	struct dc_static_screen_events triggers = {0};
-+
-+	if (mod_freesync == NULL)
-+		return;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+
-+	if (core_freesync->num_entities == 0)
-+		return;
-+
-+	for(stream_index = 0; stream_index < num_streams; stream_index++) {
-+
-+		unsigned int map_index = map_index_from_stream(core_freesync,
-+				streams[stream_index]);
-+
-+		bool is_embedded = dc_is_embedded_signal(
-+				streams[stream_index]->sink->sink_signal);
-+
-+		struct freesync_registry_options *opts = &core_freesync->opts;
-+
-+		state = &core_freesync->map[map_index].state;
-+
-+		switch (freesync_params->state){
-+		case FREESYNC_STATE_FULLSCREEN:
-+			state->fullscreen = freesync_params->enable;
-+			freesync_program_required = true;
-+			state->windowed_fullscreen =
-+					freesync_params->windowed_fullscreen;
-+			break;
-+		case FREESYNC_STATE_STATIC_SCREEN:
-+			/* Static screen ramp is disabled by default, but can
-+			 * be enabled through regkey.
-+			 */
-+			if ((is_embedded && opts->drr_internal_supported) ||
-+				(!is_embedded && opts->drr_external_supported))
-+
-+				if (state->static_screen !=
-+						freesync_params->enable) {
-+
-+					/* Change the state flag */
-+					state->static_screen =
-+							freesync_params->enable;
-+
-+					/* Update static screen ramp */
-+					set_static_ramp_variables(core_freesync,
-+						map_index,
-+						freesync_params->enable);
-+				}
-+			/* We program the ramp starting next VUpdate */
-+			break;
-+		case FREESYNC_STATE_VIDEO:
-+			/* Change core variables only if there is a change*/
-+			if(freesync_params->update_duration_in_ns !=
-+				state->time.update_duration_in_ns) {
-+
-+				state->video = freesync_params->enable;
-+				state->time.update_duration_in_ns =
-+					freesync_params->update_duration_in_ns;
-+
-+				freesync_program_required = true;
-+			}
-+			break;
-+		case FREESYNC_STATE_NONE:
-+			/* handle here to avoid warning */
-+			break;
-+		}
-+	}
-+
-+	/* Update mask */
-+	triggers.overlay_update = true;
-+	triggers.surface_update = true;
-+
-+	dc_stream_set_static_screen_events(core_freesync->dc, streams,
-+					   num_streams, &triggers);
-+
-+	if (freesync_program_required)
-+		/* Program freesync according to current state*/
-+		set_freesync_on_streams(core_freesync, streams, num_streams);
-+}
-+
-+
-+bool mod_freesync_get_state(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream,
-+		struct mod_freesync_params *freesync_params)
-+{
-+	unsigned int index = 0;
-+	struct core_freesync *core_freesync = NULL;
-+
-+	if (mod_freesync == NULL)
-+		return false;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+	index = map_index_from_stream(core_freesync, stream);
-+
-+	if (core_freesync->map[index].state.fullscreen) {
-+		freesync_params->state = FREESYNC_STATE_FULLSCREEN;
-+		freesync_params->enable = true;
-+	} else if (core_freesync->map[index].state.static_screen) {
-+		freesync_params->state = FREESYNC_STATE_STATIC_SCREEN;
-+		freesync_params->enable = true;
-+	} else if (core_freesync->map[index].state.video) {
-+		freesync_params->state = FREESYNC_STATE_VIDEO;
-+		freesync_params->enable = true;
-+	} else {
-+		freesync_params->state = FREESYNC_STATE_NONE;
-+		freesync_params->enable = false;
-+	}
-+
-+	freesync_params->update_duration_in_ns =
-+		core_freesync->map[index].state.time.update_duration_in_ns;
-+
-+	freesync_params->windowed_fullscreen =
-+			core_freesync->map[index].state.windowed_fullscreen;
-+
-+	return true;
-+}
-+
-+bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state **streams, int num_streams,
-+		struct mod_freesync_user_enable *user_enable)
-+{
-+	unsigned int stream_index, map_index;
-+	int persistent_data = 0;
-+	struct persistent_data_flag flag;
-+	struct dc  *dc = NULL;
-+	struct core_freesync *core_freesync = NULL;
-+
-+	if (mod_freesync == NULL)
-+		return false;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+	dc = core_freesync->dc;
-+
-+	flag.save_per_edid = true;
-+	flag.save_per_link = false;
-+
-+	for(stream_index = 0; stream_index < num_streams;
-+			stream_index++){
-+
-+		map_index = map_index_from_stream(core_freesync,
-+				streams[stream_index]);
-+
-+		core_freesync->map[map_index].user_enable = *user_enable;
-+
-+		/* Write persistent data in registry*/
-+		if (core_freesync->map[map_index].user_enable.
-+				enable_for_gaming)
-+			persistent_data = persistent_data | 1;
-+		if (core_freesync->map[map_index].user_enable.
-+				enable_for_static)
-+			persistent_data = persistent_data | 2;
-+		if (core_freesync->map[map_index].user_enable.
-+				enable_for_video)
-+			persistent_data = persistent_data | 4;
-+
-+		dm_write_persistent_data(dc->ctx,
-+					streams[stream_index]->sink,
-+					FREESYNC_REGISTRY_NAME,
-+					"userenable",
-+					&persistent_data,
-+					sizeof(int),
-+					&flag);
-+	}
-+
-+	set_freesync_on_streams(core_freesync, streams, num_streams);
-+
-+	return true;
-+}
-+
-+bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream,
-+		struct mod_freesync_user_enable *user_enable)
-+{
-+	unsigned int index = 0;
-+	struct core_freesync *core_freesync = NULL;
-+
-+	if (mod_freesync == NULL)
-+		return false;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+	index = map_index_from_stream(core_freesync, stream);
-+
-+	*user_enable = core_freesync->map[index].user_enable;
-+
-+	return true;
-+}
-+
-+bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream,
-+		bool *is_ramp_active)
-+{
-+	unsigned int index = 0;
-+	struct core_freesync *core_freesync = NULL;
-+
-+	if (mod_freesync == NULL)
-+		return false;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+	index = map_index_from_stream(core_freesync, stream);
-+
-+	*is_ramp_active =
-+		core_freesync->map[index].state.static_ramp.ramp_is_active;
-+
-+	return true;
-+}
-+
-+bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *streams,
-+		unsigned int min_refresh,
-+		unsigned int max_refresh,
-+		struct mod_freesync_caps *caps)
-+{
-+	unsigned int index = 0;
-+	struct core_freesync *core_freesync;
-+	struct freesync_state *state;
-+
-+	if (mod_freesync == NULL)
-+		return false;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+	index = map_index_from_stream(core_freesync, streams);
-+	state = &core_freesync->map[index].state;
-+
-+	if (max_refresh == 0)
-+		max_refresh = state->nominal_refresh_rate_in_micro_hz;
-+
-+	if (min_refresh == 0) {
-+		/* Restore defaults */
-+		calc_freesync_range(core_freesync, streams, state,
-+			core_freesync->map[index].caps->
-+			min_refresh_in_micro_hz,
-+			state->nominal_refresh_rate_in_micro_hz);
-+	} else {
-+		calc_freesync_range(core_freesync, streams,
-+				state,
-+				min_refresh,
-+				max_refresh);
-+
-+		/* Program vtotal min/max */
-+		dc_stream_adjust_vmin_vmax(core_freesync->dc, &streams, 1,
-+					   state->freesync_range.vmin,
-+					   state->freesync_range.vmax);
-+	}
-+
-+	if (min_refresh != 0 &&
-+			dc_is_embedded_signal(streams->sink->sink_signal) &&
-+			(max_refresh - min_refresh >= 10000000)) {
-+		caps->supported = true;
-+		caps->min_refresh_in_micro_hz = min_refresh;
-+		caps->max_refresh_in_micro_hz = max_refresh;
-+	}
-+
-+	/* Update the stream */
-+	update_stream(core_freesync, streams);
-+
-+	return true;
-+}
-+
-+bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream,
-+		unsigned int *min_refresh,
-+		unsigned int *max_refresh)
-+{
-+	unsigned int index = 0;
-+	struct core_freesync *core_freesync = NULL;
-+
-+	if (mod_freesync == NULL)
-+		return false;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+	index = map_index_from_stream(core_freesync, stream);
-+
-+	*min_refresh =
-+		core_freesync->map[index].state.freesync_range.min_refresh;
-+	*max_refresh =
-+		core_freesync->map[index].state.freesync_range.max_refresh;
-+
-+	return true;
-+}
-+
-+bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream,
-+		unsigned int *vmin,
-+		unsigned int *vmax)
-+{
-+	unsigned int index = 0;
-+	struct core_freesync *core_freesync = NULL;
-+
-+	if (mod_freesync == NULL)
-+		return false;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+	index = map_index_from_stream(core_freesync, stream);
-+
-+	*vmin =
-+		core_freesync->map[index].state.freesync_range.vmin;
-+	*vmax =
-+		core_freesync->map[index].state.freesync_range.vmax;
-+
-+	return true;
-+}
-+
-+bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream,
-+		unsigned int *nom_v_pos,
-+		unsigned int *v_pos)
-+{
-+	unsigned int index = 0;
-+	struct core_freesync *core_freesync = NULL;
-+	struct crtc_position position;
-+
-+	if (mod_freesync == NULL)
-+		return false;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+	index = map_index_from_stream(core_freesync, stream);
-+
-+	if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1,
-+					&position.vertical_count,
-+					&position.nominal_vcount)) {
-+
-+		*nom_v_pos = position.nominal_vcount;
-+		*v_pos = position.vertical_count;
-+
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state **streams, int num_streams)
-+{
-+	unsigned int stream_index, map_index;
-+	struct freesync_state *state;
-+	struct core_freesync *core_freesync = NULL;
-+	struct dc_static_screen_events triggers = {0};
-+	unsigned long long temp = 0;
-+
-+	if (mod_freesync == NULL)
-+		return;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+
-+	for (stream_index = 0; stream_index < num_streams; stream_index++) {
-+		map_index = map_index_from_stream(core_freesync,
-+				streams[stream_index]);
-+
-+		state = &core_freesync->map[map_index].state;
-+
-+		/* Update the field rate for new timing */
-+		temp = streams[stream_index]->timing.pix_clk_khz;
-+		temp *= 1000ULL * 1000ULL * 1000ULL;
-+		temp = div_u64(temp,
-+				streams[stream_index]->timing.h_total);
-+		temp = div_u64(temp,
-+				streams[stream_index]->timing.v_total);
-+		state->nominal_refresh_rate_in_micro_hz =
-+				(unsigned int) temp;
-+
-+		if (core_freesync->map[map_index].caps->supported) {
-+
-+			/* Update the stream */
-+			update_stream(core_freesync, streams[stream_index]);
-+
-+			/* Calculate vmin/vmax and refresh rate for
-+			 * current mode
-+			 */
-+			calc_freesync_range(core_freesync, *streams, state,
-+				core_freesync->map[map_index].caps->
-+				min_refresh_in_micro_hz,
-+				state->nominal_refresh_rate_in_micro_hz);
-+
-+			/* Update mask */
-+			triggers.overlay_update = true;
-+			triggers.surface_update = true;
-+
-+			dc_stream_set_static_screen_events(core_freesync->dc,
-+							   streams, num_streams,
-+							   &triggers);
-+		}
-+	}
-+
-+	/* Program freesync according to current state*/
-+	set_freesync_on_streams(core_freesync, streams, num_streams);
-+}
-+
-+/* Add the timestamps to the cache and determine whether BTR programming
-+ * is required, depending on the times calculated
-+ */
-+static void update_timestamps(struct core_freesync *core_freesync,
-+		const struct dc_stream_state *stream, unsigned int map_index,
-+		unsigned int last_render_time_in_us)
-+{
-+	struct freesync_state *state = &core_freesync->map[map_index].state;
-+
-+	state->time.render_times[state->time.render_times_index] =
-+			last_render_time_in_us;
-+	state->time.render_times_index++;
-+
-+	if (state->time.render_times_index >= RENDER_TIMES_MAX_COUNT)
-+		state->time.render_times_index = 0;
-+
-+	if (last_render_time_in_us + BTR_EXIT_MARGIN <
-+		state->time.max_render_time_in_us) {
-+
-+		/* Exit Below the Range */
-+		if (state->btr.btr_active) {
-+
-+			state->btr.program_btr = true;
-+			state->btr.btr_active = false;
-+			state->btr.frame_counter = 0;
-+
-+		/* Exit Fixed Refresh mode */
-+		} else if (state->fixed_refresh.fixed_active) {
-+
-+			state->fixed_refresh.frame_counter++;
-+
-+			if (state->fixed_refresh.frame_counter >
-+					FIXED_REFRESH_EXIT_FRAME_COUNT) {
-+				state->fixed_refresh.frame_counter = 0;
-+				state->fixed_refresh.program_fixed = true;
-+				state->fixed_refresh.fixed_active = false;
-+			}
-+		}
-+
-+	} else if (last_render_time_in_us > state->time.max_render_time_in_us) {
-+
-+		/* Enter Below the Range */
-+		if (!state->btr.btr_active &&
-+			core_freesync->map[map_index].caps->btr_supported) {
-+
-+			state->btr.program_btr = true;
-+			state->btr.btr_active = true;
-+
-+		/* Enter Fixed Refresh mode */
-+		} else if (!state->fixed_refresh.fixed_active &&
-+			!core_freesync->map[map_index].caps->btr_supported) {
-+
-+			state->fixed_refresh.frame_counter++;
-+
-+			if (state->fixed_refresh.frame_counter >
-+					FIXED_REFRESH_ENTER_FRAME_COUNT) {
-+				state->fixed_refresh.frame_counter = 0;
-+				state->fixed_refresh.program_fixed = true;
-+				state->fixed_refresh.fixed_active = true;
-+			}
-+		}
-+	}
-+
-+	/* When Below the Range is active, must react on every frame */
-+	if (state->btr.btr_active)
-+		state->btr.program_btr = true;
-+}
-+
-+static void apply_below_the_range(struct core_freesync *core_freesync,
-+		struct dc_stream_state *stream, unsigned int map_index,
-+		unsigned int last_render_time_in_us)
-+{
-+	unsigned int inserted_frame_duration_in_us = 0;
-+	unsigned int mid_point_frames_ceil = 0;
-+	unsigned int mid_point_frames_floor = 0;
-+	unsigned int frame_time_in_us = 0;
-+	unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
-+	unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
-+	unsigned int frames_to_insert = 0;
-+	unsigned int min_frame_duration_in_ns = 0;
-+	struct freesync_state *state = &core_freesync->map[map_index].state;
-+
-+	if (!state->btr.program_btr)
-+		return;
-+
-+	state->btr.program_btr = false;
-+
-+	min_frame_duration_in_ns = ((unsigned int) (div64_u64(
-+		(1000000000ULL * 1000000),
-+		state->nominal_refresh_rate_in_micro_hz)));
-+
-+	/* Program BTR */
-+
-+	/* BTR set to "not active" so disengage */
-+	if (!state->btr.btr_active)
-+
-+		/* Restore FreeSync */
-+		set_freesync_on_streams(core_freesync, &stream, 1);
-+
-+	/* BTR set to "active" so engage */
-+	else {
-+
-+		/* Calculate number of midPoint frames that could fit within
-+		 * the render time interval- take ceil of this value
-+		 */
-+		mid_point_frames_ceil = (last_render_time_in_us +
-+			state->btr.mid_point_in_us- 1) /
-+			state->btr.mid_point_in_us;
-+
-+		if (mid_point_frames_ceil > 0) {
-+
-+			frame_time_in_us = last_render_time_in_us /
-+				mid_point_frames_ceil;
-+			delta_from_mid_point_in_us_1 =
-+				(state->btr.mid_point_in_us >
-+				frame_time_in_us) ?
-+				(state->btr.mid_point_in_us - frame_time_in_us):
-+				(frame_time_in_us - state->btr.mid_point_in_us);
-+		}
-+
-+		/* Calculate number of midPoint frames that could fit within
-+		 * the render time interval- take floor of this value
-+		 */
-+		mid_point_frames_floor = last_render_time_in_us /
-+			state->btr.mid_point_in_us;
-+
-+		if (mid_point_frames_floor > 0) {
-+
-+			frame_time_in_us = last_render_time_in_us /
-+				mid_point_frames_floor;
-+			delta_from_mid_point_in_us_2 =
-+				(state->btr.mid_point_in_us >
-+				frame_time_in_us) ?
-+				(state->btr.mid_point_in_us - frame_time_in_us):
-+				(frame_time_in_us - state->btr.mid_point_in_us);
-+		}
-+
-+		/* Choose number of frames to insert based on how close it
-+		 * can get to the mid point of the variable range.
-+		 */
-+		if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2)
-+			frames_to_insert = mid_point_frames_ceil;
-+		else
-+			frames_to_insert = mid_point_frames_floor;
-+
-+		/* Either we've calculated the number of frames to insert,
-+		 * or we need to insert min duration frames
-+		 */
-+		if (frames_to_insert > 0)
-+			inserted_frame_duration_in_us = last_render_time_in_us /
-+							frames_to_insert;
-+
-+		if (inserted_frame_duration_in_us <
-+			state->time.min_render_time_in_us)
-+
-+			inserted_frame_duration_in_us =
-+				state->time.min_render_time_in_us;
-+
-+		/* Cache the calculated variables */
-+		state->btr.inserted_frame_duration_in_us =
-+			inserted_frame_duration_in_us;
-+		state->btr.frames_to_insert = frames_to_insert;
-+		state->btr.frame_counter = frames_to_insert;
-+
-+	}
-+}
-+
-+static void apply_fixed_refresh(struct core_freesync *core_freesync,
-+		struct dc_stream_state *stream, unsigned int map_index)
-+{
-+	unsigned int vmin = 0, vmax = 0;
-+	struct freesync_state *state = &core_freesync->map[map_index].state;
-+
-+	if (!state->fixed_refresh.program_fixed)
-+		return;
-+
-+	state->fixed_refresh.program_fixed = false;
-+
-+	/* Program Fixed Refresh */
-+
-+	/* Fixed Refresh set to "not active" so disengage */
-+	if (!state->fixed_refresh.fixed_active) {
-+		set_freesync_on_streams(core_freesync, &stream, 1);
-+
-+	/* Fixed Refresh set to "active" so engage (fix to max) */
-+	} else {
-+
-+		vmin = state->freesync_range.vmin;
-+
-+		vmax = vmin;
-+
-+		dc_stream_adjust_vmin_vmax(core_freesync->dc, &stream,
-+					   1, vmin, vmax);
-+	}
-+}
-+
-+void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state **streams, int num_streams,
-+		unsigned int curr_time_stamp_in_us)
-+{
-+	unsigned int stream_index, map_index, last_render_time_in_us = 0;
-+	struct core_freesync *core_freesync = NULL;
-+
-+	if (mod_freesync == NULL)
-+		return;
-+
-+	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-+
-+	for (stream_index = 0; stream_index < num_streams; stream_index++) {
-+
-+		map_index = map_index_from_stream(core_freesync,
-+						streams[stream_index]);
-+
-+		if (core_freesync->map[map_index].caps->supported) {
-+
-+			last_render_time_in_us = curr_time_stamp_in_us -
-+					core_freesync->map[map_index].state.time.
-+					prev_time_stamp_in_us;
-+
-+			/* Add the timestamps to the cache and determine
-+			 * whether BTR program is required
-+			 */
-+			update_timestamps(core_freesync, streams[stream_index],
-+					map_index, last_render_time_in_us);
-+
-+			if (core_freesync->map[map_index].state.fullscreen &&
-+				core_freesync->map[map_index].user_enable.
-+				enable_for_gaming) {
-+
-+				if (core_freesync->map[map_index].caps->btr_supported) {
-+
-+					apply_below_the_range(core_freesync,
-+						streams[stream_index], map_index,
-+						last_render_time_in_us);
-+				} else {
-+					apply_fixed_refresh(core_freesync,
-+						streams[stream_index], map_index);
-+				}
-+			}
-+
-+			core_freesync->map[map_index].state.time.
-+				prev_time_stamp_in_us = curr_time_stamp_in_us;
-+		}
-+
-+	}
-+}
---- linux-4.14/drivers/gpu/drm/amd/display/modules/freesync/Makefile.0130~	2017-12-14 06:39:58.442903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/modules/freesync/Makefile	2017-12-14 06:39:58.442903586 +0100
-@@ -0,0 +1,10 @@
-+#
-+# Makefile for the 'freesync' sub-module of DAL.
-+#
-+
-+FREESYNC = freesync.o
-+
-+AMD_DAL_FREESYNC = $(addprefix $(AMDDALPATH)/modules/freesync/,$(FREESYNC))
-+#$(info ************  DAL-FREE SYNC_MAKEFILE ************)
-+
-+AMD_DISPLAY_FILES += $(AMD_DAL_FREESYNC)
---- linux-4.14/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h.0130~	2017-12-14 06:39:58.442903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h	2017-12-14 06:39:58.442903586 +0100
-@@ -0,0 +1,167 @@
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+
-+
-+
-+/*
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ * Authors: AMD
-+ *
-+ */
-+
-+#ifndef MOD_FREESYNC_H_
-+#define MOD_FREESYNC_H_
-+
-+#include "dm_services.h"
-+
-+struct mod_freesync *mod_freesync_create(struct dc *dc);
-+void mod_freesync_destroy(struct mod_freesync *mod_freesync);
-+
-+struct mod_freesync {
-+	int dummy;
-+};
-+
-+enum mod_freesync_state {
-+	FREESYNC_STATE_NONE,
-+	FREESYNC_STATE_FULLSCREEN,
-+	FREESYNC_STATE_STATIC_SCREEN,
-+	FREESYNC_STATE_VIDEO
-+};
-+
-+enum mod_freesync_user_enable_mask {
-+	FREESYNC_USER_ENABLE_STATIC = 0x1,
-+	FREESYNC_USER_ENABLE_VIDEO = 0x2,
-+	FREESYNC_USER_ENABLE_GAMING = 0x4
-+};
-+
-+struct mod_freesync_user_enable {
-+	bool enable_for_static;
-+	bool enable_for_video;
-+	bool enable_for_gaming;
-+};
-+
-+struct mod_freesync_caps {
-+	bool supported;
-+	unsigned int min_refresh_in_micro_hz;
-+	unsigned int max_refresh_in_micro_hz;
-+
-+	bool btr_supported;
-+};
-+
-+struct mod_freesync_params {
-+	enum mod_freesync_state state;
-+	bool enable;
-+	unsigned int update_duration_in_ns;
-+	bool windowed_fullscreen;
-+};
-+
-+/*
-+ * Add stream to be tracked by module
-+ */
-+bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream, struct mod_freesync_caps *caps);
-+
-+/*
-+ * Remove stream to be tracked by module
-+ */
-+bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream);
-+
-+/*
-+ * Update the freesync state flags for each display and program
-+ * freesync accordingly
-+ */
-+void mod_freesync_update_state(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state **streams, int num_streams,
-+		struct mod_freesync_params *freesync_params);
-+
-+bool mod_freesync_get_state(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream,
-+		struct mod_freesync_params *freesync_params);
-+
-+bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state **streams, int num_streams,
-+		struct mod_freesync_user_enable *user_enable);
-+
-+bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream,
-+		struct mod_freesync_user_enable *user_enable);
-+
-+bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream,
-+		bool *is_ramp_active);
-+
-+bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *streams,
-+		unsigned int min_refresh,
-+		unsigned int max_refresh,
-+		struct mod_freesync_caps *caps);
-+
-+bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream,
-+		unsigned int *min_refresh,
-+		unsigned int *max_refresh);
-+
-+bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream,
-+		unsigned int *vmin,
-+		unsigned int *vmax);
-+
-+bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state *stream,
-+		unsigned int *nom_v_pos,
-+		unsigned int *v_pos);
-+
-+void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state **streams, int num_streams);
-+
-+void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state **streams, int num_streams);
-+
-+void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync,
-+		struct dc_stream_state **streams, int num_streams,
-+		unsigned int curr_time_stamp);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/display/TODO.0130~	2017-12-14 06:39:58.442903586 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/display/TODO	2017-12-14 06:39:58.442903586 +0100
-@@ -0,0 +1,107 @@
-+===============================================================================
-+TODOs
-+===============================================================================
-+
-+1. Base this on drm-next - WIP
-+
-+
-+2. Cleanup commit history
-+
-+
-+3. WIP - Drop page flip helper and use DRM's version
-+
-+
-+4. DONE - Flatten all DC objects
-+    * dc_stream/core_stream/stream should just be dc_stream
-+    * Same for other DC objects
-+
-+    "Is there any major reason to keep all those abstractions?
-+
-+    Could you collapse everything into struct dc_stream?
-+
-+    I haven't looked recently but I didn't get the impression there was a
-+    lot of design around what was public/protected, more whatever needed
-+    to be used by someone else was in public."
-+    ~ Dave Airlie
-+
-+
-+5. DONE - Rename DC objects to align more with DRM
-+    * dc_surface -> dc_plane_state
-+    * dc_stream -> dc_stream_state
-+
-+
-+6. DONE - Per-plane and per-stream validation
-+
-+
-+7. WIP - Per-plane and per-stream commit
-+
-+
-+8. WIP - Split pipe_ctx into plane and stream resource structs
-+
-+
-+9. Attach plane and stream reources to state object instead of validate_context
-+
-+
-+10. Remove dc_edid_caps and drm_helpers_parse_edid_caps
-+    * Use drm_display_info instead
-+    * Remove DC's edid quirks and rely on DRM's quirks (add quirks if needed)
-+
-+    "Making sure you use the sink-specific helper libraries and kernel
-+    subsystems, since there's really no good reason to have 2nd
-+    implementation of those in the kernel. Looks likes that's done for mst
-+    and edid parsing. There's still a bit a midlayer feeling to the edid
-+    parsing side (e.g. dc_edid_caps and dm_helpers_parse_edid_caps, I
-+    think it'd be much better if you convert that over to reading stuff
-+    from drm_display_info and if needed, push stuff into the core). Also,
-+    I can't come up with a good reason why DC needs all this (except to
-+    reimplement half of our edid quirk table, which really isn't a good
-+    idea). Might be good if you put this onto the list of things to fix
-+    long-term, but imo not a blocker. Definitely make sure new stuff
-+    doesn't slip in (i.e. if you start adding edid quirks to DC instead of
-+    the drm core, refactoring to use the core edid stuff was pointless)."
-+    ~ Daniel Vetter
-+
-+
-+11. Remove dc/i2caux. This folder can be somewhat misleading. It's basically an
-+overy complicated HW programming function for sendind and receiving i2c/aux
-+commands. We can greatly simplify that and move it into dc/dceXYZ like other
-+HW blocks.
-+
-+12. drm_modeset_lock in MST should no longer be needed in recent kernels
-+    * Adopt appropriate locking scheme
-+
-+13. get_modes and best_encoder callbacks look a bit funny. Can probably rip out
-+a few indirections, and consider removing entirely and using the
-+drm_atomic_helper_best_encoder default behaviour.
-+
-+14. core/dc_debug.c, consider switching to the atomic state debug helpers and
-+moving all your driver state printing into the various atomic_print_state
-+callbacks. There's also plans to expose this stuff in a standard way across all
-+drivers, to make debugging userspace compositors easier across different hw.
-+
-+15. Move DP/HDMI dual mode adaptors to drm_dp_dual_mode_helper.c. See
-+dal_ddc_service_i2c_query_dp_dual_mode_adaptor.
-+
-+16. Move to core SCDC helpers (I think those are new since initial DC review).
-+
-+17. There's still a pretty massive layer cake around dp aux and DPCD handling,
-+with like 3 levels of abstraction and using your own structures instead of the
-+stuff in drm_dp_helper.h. drm_dp_helper.h isn't really great and already has 2
-+incompatible styles, just means more reasons not to add a third (or well third
-+one gets to do the cleanup refactor).
-+
-+18. There's a pile of sink handling code, both for DP and HDMI where I didn't
-+immediately recognize the standard. I think long term it'd be best for the drm
-+subsystem if we try to move as much of that into helpers/core as possible, and
-+share it with drivers. But that's a very long term goal, and by far not just an
-+issue with DC - other drivers, especially around DP sink handling, are equally
-+guilty.
-+
-+19. The DC logger is still a rather sore thing, but I know that the DRM_DEBUG
-+stuff just isn't up to the challenges either. We need to figure out something
-+that integrates better with DRM and linux debug printing, while not being
-+useless with filtering output. dynamic debug printing might be an option.
-+
-+20. Use kernel i2c device to program HDMI retimer. Some boards have an HDMI
-+retimer that we need to program to pass PHY compliance. Currently that's
-+bypassing the i2c device and goes directly to HW. This should be changed.
---- linux-4.14/drivers/gpu/drm/amd/include/amd_shared.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/amd_shared.h	2017-12-14 06:39:58.442903586 +0100
-@@ -23,34 +23,9 @@
- #ifndef __AMD_SHARED_H__
- #define __AMD_SHARED_H__
- 
--#define AMD_MAX_USEC_TIMEOUT		200000  /* 200 ms */
-+#include <drm/amd_asic_type.h>
- 
--/*
-- * Supported ASIC types
-- */
--enum amd_asic_type {
--	CHIP_TAHITI = 0,
--	CHIP_PITCAIRN,
--	CHIP_VERDE,
--	CHIP_OLAND,
--	CHIP_HAINAN,
--	CHIP_BONAIRE,
--	CHIP_KAVERI,
--	CHIP_KABINI,
--	CHIP_HAWAII,
--	CHIP_MULLINS,
--	CHIP_TOPAZ,
--	CHIP_TONGA,
--	CHIP_FIJI,
--	CHIP_CARRIZO,
--	CHIP_STONEY,
--	CHIP_POLARIS10,
--	CHIP_POLARIS11,
--	CHIP_POLARIS12,
--	CHIP_VEGA10,
--	CHIP_RAVEN,
--	CHIP_LAST,
--};
-+#define AMD_MAX_USEC_TIMEOUT		200000  /* 200 ms */
- 
- /*
-  * Chip flags
-@@ -84,65 +59,12 @@ enum amd_clockgating_state {
- 	AMD_CG_STATE_UNGATE,
- };
- 
--enum amd_dpm_forced_level {
--	AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
--	AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
--	AMD_DPM_FORCED_LEVEL_LOW = 0x4,
--	AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
--	AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
--	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
--	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
--	AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
--	AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
--};
- 
- enum amd_powergating_state {
- 	AMD_PG_STATE_GATE = 0,
- 	AMD_PG_STATE_UNGATE,
- };
- 
--struct amd_vce_state {
--	/* vce clocks */
--	u32 evclk;
--	u32 ecclk;
--	/* gpu clocks */
--	u32 sclk;
--	u32 mclk;
--	u8 clk_idx;
--	u8 pstate;
--};
--
--
--#define AMD_MAX_VCE_LEVELS 6
--
--enum amd_vce_level {
--	AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
--	AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
--	AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
--	AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
--	AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
--	AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
--};
--
--enum amd_pp_profile_type {
--	AMD_PP_GFX_PROFILE,
--	AMD_PP_COMPUTE_PROFILE,
--};
--
--struct amd_pp_profile {
--	enum amd_pp_profile_type type;
--	uint32_t min_sclk;
--	uint32_t min_mclk;
--	uint16_t activity_threshold;
--	uint8_t up_hyst;
--	uint8_t down_hyst;
--};
--
--enum amd_fan_ctrl_mode {
--	AMD_FAN_CTRL_NONE = 0,
--	AMD_FAN_CTRL_MANUAL = 1,
--	AMD_FAN_CTRL_AUTO = 2,
--};
- 
- /* CG flags */
- #define AMD_CG_SUPPORT_GFX_MGCG			(1 << 0)
-@@ -186,27 +108,6 @@ enum amd_fan_ctrl_mode {
- #define AMD_PG_SUPPORT_GFX_PIPELINE		(1 << 12)
- #define AMD_PG_SUPPORT_MMHUB			(1 << 13)
- 
--enum amd_pm_state_type {
--	/* not used for dpm */
--	POWER_STATE_TYPE_DEFAULT,
--	POWER_STATE_TYPE_POWERSAVE,
--	/* user selectable states */
--	POWER_STATE_TYPE_BATTERY,
--	POWER_STATE_TYPE_BALANCED,
--	POWER_STATE_TYPE_PERFORMANCE,
--	/* internal states */
--	POWER_STATE_TYPE_INTERNAL_UVD,
--	POWER_STATE_TYPE_INTERNAL_UVD_SD,
--	POWER_STATE_TYPE_INTERNAL_UVD_HD,
--	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
--	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
--	POWER_STATE_TYPE_INTERNAL_BOOT,
--	POWER_STATE_TYPE_INTERNAL_THERMAL,
--	POWER_STATE_TYPE_INTERNAL_ACPI,
--	POWER_STATE_TYPE_INTERNAL_ULV,
--	POWER_STATE_TYPE_INTERNAL_3DPERF,
--};
--
- struct amd_ip_funcs {
- 	/* Name of IP block */
- 	char *name;
-@@ -249,4 +150,5 @@ struct amd_ip_funcs {
- 	void (*get_clockgating_state)(void *handle, u32 *flags);
- };
- 
-+
- #endif /* __AMD_SHARED_H__ */
---- linux-4.14/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h	2017-12-14 06:39:58.444903588 +0100
-@@ -2283,6 +2283,10 @@
- #define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
- #define mmDCHUBBUB_SPARE                                                                               0x0534
- #define mmDCHUBBUB_SPARE_BASE_IDX                                                                      2
-+#define mmDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x053a
-+#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2
-+#define mmDCHUBBUB_TEST_DEBUG_DATA                                                                     0x053b
-+#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2
- 
- 
- // addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
-@@ -10361,6 +10365,8 @@
- #define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
- #define mmDCIO_WRCMD_DELAY                                                                             0x287e
- #define mmDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
-+#define mmDC_PINSTRAPS                                                                                 0x2880
-+#define mmDC_PINSTRAPS_BASE_IDX                                                                        2
- #define mmDC_DVODATA_CONFIG                                                                            0x2882
- #define mmDC_DVODATA_CONFIG_BASE_IDX                                                                   2
- #define mmLVTMA_PWRSEQ_CNTL                                                                            0x2883
---- linux-4.14/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h	2017-12-14 06:39:58.452903593 +0100
-@@ -9361,12 +9361,14 @@
- #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
- #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
- //HUBPREQ0_DCSURF_SURFACE_CONTROL
-+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
- #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
- #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT                               0x2
- #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                             0x5
- #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
- #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT                             0xa
- #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                           0xd
-+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
- #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
- #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK                                 0x00000004L
- #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK                               0x00000020L
-@@ -39956,6 +39958,9 @@
- #define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK                                                                     0x00000F00L
- #define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK                                                                  0x0000F000L
- #define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK                                                                     0x000F0000L
-+//DC_PINSTRAPS
-+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
-+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
- //DC_DVODATA_CONFIG
- #define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT                                                                  0x13
- #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT                                                        0x14
---- linux-4.14/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h	2017-12-14 06:39:58.453903594 +0100
-@@ -5454,5 +5454,7 @@
- #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
- #define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
- #define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
-+#define SMC_SYSCON_MISC_CNTL__pre_fetcher_en_MASK  0x1
-+#define SMC_SYSCON_MISC_CNTL__pre_fetcher_en__SHIFT 0
- 
- #endif /* SMU_7_0_1_SH_MASK_H */
---- linux-4.14/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h	2017-12-14 06:39:58.453903594 +0100
-@@ -36,6 +36,16 @@
- #define mmUVD_UDEC_DBW_ADDR_CONFIG                                              0x3bd5
- #define mmUVD_POWER_STATUS_U                                                    0x3bfd
- #define mmUVD_NO_OP                                                             0x3bff
-+#define mmUVD_RB_BASE_LO2                                                       0x3c21
-+#define mmUVD_RB_BASE_HI2                                                       0x3c22
-+#define mmUVD_RB_SIZE2                                                          0x3c23
-+#define mmUVD_RB_RPTR2                                                          0x3c24
-+#define mmUVD_RB_WPTR2                                                          0x3c25
-+#define mmUVD_RB_BASE_LO                                                        0x3c26
-+#define mmUVD_RB_BASE_HI                                                        0x3c27
-+#define mmUVD_RB_SIZE                                                           0x3c28
-+#define mmUVD_RB_RPTR                                                           0x3c29
-+#define mmUVD_RB_WPTR                                                           0x3c2a
- #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW                                          0x3c69
- #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH                                         0x3c68
- #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW                                          0x3c67
-@@ -43,6 +53,11 @@
- #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW                                      0x3c5f
- #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH                                     0x3c5e
- #define mmUVD_SEMA_CNTL                                                         0x3d00
-+#define mmUVD_RB_WPTR3                                                          0x3d1c
-+#define mmUVD_RB_RPTR3                                                          0x3d1b
-+#define mmUVD_RB_BASE_LO3                                                       0x3d1d
-+#define mmUVD_RB_BASE_HI3                                                       0x3d1e
-+#define mmUVD_RB_SIZE3                                                          0x3d1f
- #define mmUVD_LMI_EXT40_ADDR                                                    0x3d26
- #define mmUVD_CTX_INDEX                                                         0x3d28
- #define mmUVD_CTX_DATA                                                          0x3d29
---- linux-4.14/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h	2017-12-14 06:39:58.455903595 +0100
-@@ -1841,6 +1841,10 @@
- #define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
- #define mmDCIO_WRCMD_DELAY                                                                             0x2094
- #define mmDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
-+#define mmDC_PINSTRAPS                                                                                 0x2096
-+#define mmDC_PINSTRAPS_BASE_IDX                                                                        2
-+#define mmCC_DC_MISC_STRAPS                                                                            0x2097
-+#define mmCC_DC_MISC_STRAPS_BASE_IDX                                                                   2
- #define mmDC_DVODATA_CONFIG                                                                            0x2098
- #define mmDC_DVODATA_CONFIG_BASE_IDX                                                                   2
- #define mmLVTMA_PWRSEQ_CNTL                                                                            0x2099
---- linux-4.14/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h	2017-12-14 06:39:58.464903602 +0100
-@@ -2447,6 +2447,14 @@
- //DCCG_CBUS_WRCMD_DELAY
- #define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT                                                    0x0
- #define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK                                                      0x0000000FL
-+//DC_PINSTRAPS
-+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
-+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
-+//CC_DC_MISC_STRAPS
-+#define CC_DC_MISC_STRAPS__HDMI_DISABLE__SHIFT                                                                0x6
-+#define CC_DC_MISC_STRAPS__AUDIO_STREAM_NUMBER__SHIFT                                                         0x8
-+#define CC_DC_MISC_STRAPS__HDMI_DISABLE_MASK                                                                  0x00000040L
-+#define CC_DC_MISC_STRAPS__AUDIO_STREAM_NUMBER_MASK                                                           0x00000700L
- //DCCG_DS_DTO_INCR
- #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT                                                             0x0
- #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK                                                               0xFFFFFFFFL
---- linux-4.14/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h.0130~	2017-12-14 06:39:58.465903602 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h	2017-12-14 06:39:58.465903602 +0100
-@@ -0,0 +1,31 @@
-+/*
-+ * Copyright (C) 2017  Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included
-+ * in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
-+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#ifndef _umc_6_0_DEFAULT_HEADER
-+#define _umc_6_0_DEFAULT_HEADER
-+
-+#define mmUMCCH0_0_EccCtrl_DEFAULT				0x00000000
-+
-+#define mmUMCCH0_0_UMC_CONFIG_DEFAULT				0x00000203
-+
-+#define mmUMCCH0_0_UmcLocalCap_DEFAULT				0x00000000
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h.0130~	2017-12-14 06:39:58.465903602 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h	2017-12-14 06:39:58.465903602 +0100
-@@ -0,0 +1,52 @@
-+/*
-+ * Copyright (C) 2017  Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included
-+ * in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
-+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#ifndef _umc_6_0_OFFSET_H_
-+#define _umc_6_0_OFFSET_H_
-+
-+#define mmUMCCH0_0_EccCtrl				0x0053
-+#define mmUMCCH0_0_EccCtrl_BASE_IDX			0
-+#define mmUMCCH1_0_EccCtrl				0x0853
-+#define mmUMCCH1_0_EccCtrl_BASE_IDX			0
-+#define mmUMCCH2_0_EccCtrl				0x1053
-+#define mmUMCCH2_0_EccCtrl_BASE_IDX			0
-+#define mmUMCCH3_0_EccCtrl				0x1853
-+#define mmUMCCH3_0_EccCtrl_BASE_IDX			0
-+
-+#define mmUMCCH0_0_UMC_CONFIG				0x0040
-+#define mmUMCCH0_0_UMC_CONFIG_BASE_IDX			0
-+#define mmUMCCH1_0_UMC_CONFIG				0x0840
-+#define mmUMCCH1_0_UMC_CONFIG_BASE_IDX			0
-+#define mmUMCCH2_0_UMC_CONFIG				0x1040
-+#define mmUMCCH2_0_UMC_CONFIG_BASE_IDX			0
-+#define mmUMCCH3_0_UMC_CONFIG				0x1840
-+#define mmUMCCH3_0_UMC_CONFIG_BASE_IDX			0
-+
-+#define mmUMCCH0_0_UmcLocalCap				0x0306
-+#define mmUMCCH0_0_UmcLocalCap_BASE_IDX			0
-+#define mmUMCCH1_0_UmcLocalCap				0x0b06
-+#define mmUMCCH1_0_UmcLocalCap_BASE_IDX			0
-+#define mmUMCCH2_0_UmcLocalCap				0x1306
-+#define mmUMCCH2_0_UmcLocalCap_BASE_IDX			0
-+#define mmUMCCH3_0_UmcLocalCap				0x1b06
-+#define mmUMCCH3_0_UmcLocalCap_BASE_IDX			0
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h.0130~	2017-12-14 06:39:58.465903602 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h	2017-12-14 06:39:58.465903602 +0100
-@@ -0,0 +1,36 @@
-+/*
-+ * Copyright (C) 2017  Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included
-+ * in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
-+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#ifndef _umc_6_0_SH_MASK_HEADER
-+#define _umc_6_0_SH_MASK_HEADER
-+
-+#define UMCCH0_0_EccCtrl__RdEccEn_MASK   0x00000400L
-+#define UMCCH0_0_EccCtrl__RdEccEn__SHIFT   0xa
-+#define UMCCH0_0_EccCtrl__WrEccEn_MASK   0x00000001L
-+#define UMCCH0_0_EccCtrl__WrEccEn__SHIFT   0x0
-+
-+#define UMCCH0_0_UMC_CONFIG__DramReady_MASK   0x80000000L
-+#define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT   0x1f
-+
-+#define UMCCH0_0_UmcLocalCap__EccDis_MASK   0x00000001L
-+#define UMCCH0_0_UmcLocalCap__EccDis__SHIFT   0x0
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/include/atombios.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/atombios.h	2017-12-14 06:39:58.466903603 +0100
-@@ -4292,6 +4292,7 @@ typedef struct _ATOM_DPCD_INFO
- #define ATOM_VRAM_OPERATION_FLAGS_SHIFT        30
- #define   ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION   0x1
- #define   ATOM_VRAM_BLOCK_NEEDS_RESERVATION      0x0
-+#define   ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION 0x2
- 
- /***********************************************************************************/
- // Structure used in VRAM_UsageByFirmwareTable
---- linux-4.14/drivers/gpu/drm/amd/include/atomfirmware.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/atomfirmware.h	2017-12-14 06:39:58.466903603 +0100
-@@ -1017,6 +1017,19 @@ struct atom_14nm_combphy_tmds_vs_set
-   uint8_t margin_deemph_lane0__deemph_sel_val;         
- };
- 
-+struct atom_i2c_reg_info {
-+  uint8_t ucI2cRegIndex;
-+  uint8_t ucI2cRegVal;
-+};
-+
-+struct atom_hdmi_retimer_redriver_set {
-+  uint8_t HdmiSlvAddr;
-+  uint8_t HdmiRegNum;
-+  uint8_t Hdmi6GRegNum;
-+  struct atom_i2c_reg_info HdmiRegSetting[9];        //For non 6G Hz use
-+  struct atom_i2c_reg_info Hdmi6GhzRegSetting[3];    //For 6G Hz use.
-+};
-+
- struct atom_integrated_system_info_v1_11
- {
-   struct  atom_common_table_header  table_header;
-@@ -1052,7 +1065,11 @@ struct atom_integrated_system_info_v1_11
-   struct atom_14nm_dpphy_dp_tuningset dp_tuningset;
-   struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset;
-   struct atom_camera_data  camera_info;
--  uint32_t  reserved[138];
-+  struct atom_hdmi_retimer_redriver_set dp0_retimer_set;   //for DP0
-+  struct atom_hdmi_retimer_redriver_set dp1_retimer_set;   //for DP1
-+  struct atom_hdmi_retimer_redriver_set dp2_retimer_set;   //for DP2
-+  struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
-+  uint32_t  reserved[108];
- };
- 
- 
---- linux-4.14/drivers/gpu/drm/amd/include/cgs_common.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/cgs_common.h	2017-12-14 06:39:58.466903603 +0100
-@@ -100,6 +100,7 @@ enum cgs_system_info_id {
- 	CGS_SYSTEM_INFO_GFX_SE_INFO,
- 	CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID,
- 	CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID,
-+	CGS_SYSTEM_INFO_PCIE_BUS_DEVFN,
- 	CGS_SYSTEM_INFO_ID_MAXIMUM,
- };
- 
-@@ -193,8 +194,6 @@ struct cgs_acpi_method_info {
-  * @type:	memory type
-  * @size:	size in bytes
-  * @align:	alignment in bytes
-- * @min_offset: minimum offset from start of heap
-- * @max_offset: maximum offset from start of heap
-  * @handle:	memory handle (output)
-  *
-  * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
-@@ -216,7 +215,6 @@ struct cgs_acpi_method_info {
-  */
- typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
- 				   uint64_t size, uint64_t align,
--				   uint64_t min_offset, uint64_t max_offset,
- 				   cgs_handle_t *handle);
- 
- /**
-@@ -310,6 +308,22 @@ typedef uint32_t (*cgs_read_ind_register
- typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
- 					 unsigned index, uint32_t value);
- 
-+#define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
-+#define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK
-+
-+#define CGS_REG_SET_FIELD(orig_val, reg, field, field_val)			\
-+	(((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) |			\
-+	 (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field))))
-+
-+#define CGS_REG_GET_FIELD(value, reg, field)				\
-+	(((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field))
-+
-+#define CGS_WREG32_FIELD(device, reg, field, val)	\
-+	cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
-+
-+#define CGS_WREG32_FIELD_IND(device, space, reg, field, val)	\
-+	cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
-+
- /**
-  * cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
-  * @cgs_device:	opaque device handle
-@@ -409,6 +423,10 @@ typedef int (*cgs_enter_safe_mode)(struc
- 
- typedef void (*cgs_lock_grbm_idx)(struct cgs_device *cgs_device, bool lock);
- 
-+struct amd_pp_init;
-+typedef void* (*cgs_register_pp_handle)(struct cgs_device *cgs_device,
-+			int (*call_back_func)(struct amd_pp_init *, void **));
-+
- struct cgs_ops {
- 	/* memory management calls (similar to KFD interface) */
- 	cgs_alloc_gpu_mem_t alloc_gpu_mem;
-@@ -445,6 +463,7 @@ struct cgs_ops {
- 	cgs_is_virtualization_enabled_t is_virtualization_enabled;
- 	cgs_enter_safe_mode enter_safe_mode;
- 	cgs_lock_grbm_idx lock_grbm_idx;
-+	cgs_register_pp_handle register_pp_handle;
- };
- 
- struct cgs_os_ops; /* To be define in OS-specific CGS header */
-@@ -463,8 +482,8 @@ struct cgs_device
- #define CGS_OS_CALL(func,dev,...) \
- 	(((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
- 
--#define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle)	\
--	CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
-+#define cgs_alloc_gpu_mem(dev,type,size,align,handle)	\
-+	CGS_CALL(alloc_gpu_mem,dev,type,size,align,handle)
- #define cgs_free_gpu_mem(dev,handle)		\
- 	CGS_CALL(free_gpu_mem,dev,handle)
- #define cgs_gmap_gpu_mem(dev,handle,mcaddr)	\
-@@ -523,4 +542,7 @@ struct cgs_device
- 
- #define cgs_lock_grbm_idx(cgs_device, lock) \
- 		CGS_CALL(lock_grbm_idx, cgs_device, lock)
-+#define cgs_register_pp_handle(cgs_device, call_back_func) \
-+		CGS_CALL(register_pp_handle, cgs_device, call_back_func)
-+
- #endif /* _CGS_COMMON_H */
---- linux-4.14/drivers/gpu/drm/amd/include/dm_pp_interface.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/dm_pp_interface.h	2017-12-14 06:39:58.466903603 +0100
-@@ -25,6 +25,145 @@
- 
- #define PP_MAX_CLOCK_LEVELS 8
- 
-+enum amd_pp_display_config_type{
-+	AMD_PP_DisplayConfigType_None = 0,
-+	AMD_PP_DisplayConfigType_DP54 ,
-+	AMD_PP_DisplayConfigType_DP432 ,
-+	AMD_PP_DisplayConfigType_DP324 ,
-+	AMD_PP_DisplayConfigType_DP27,
-+	AMD_PP_DisplayConfigType_DP243,
-+	AMD_PP_DisplayConfigType_DP216,
-+	AMD_PP_DisplayConfigType_DP162,
-+	AMD_PP_DisplayConfigType_HDMI6G ,
-+	AMD_PP_DisplayConfigType_HDMI297 ,
-+	AMD_PP_DisplayConfigType_HDMI162,
-+	AMD_PP_DisplayConfigType_LVDS,
-+	AMD_PP_DisplayConfigType_DVI,
-+	AMD_PP_DisplayConfigType_WIRELESS,
-+	AMD_PP_DisplayConfigType_VGA
-+};
-+
-+struct single_display_configuration
-+{
-+	uint32_t controller_index;
-+	uint32_t controller_id;
-+	uint32_t signal_type;
-+	uint32_t display_state;
-+	/* phy id for the primary internal transmitter */
-+	uint8_t primary_transmitter_phyi_d;
-+	/* bitmap with the active lanes */
-+	uint8_t primary_transmitter_active_lanemap;
-+	/* phy id for the secondary internal transmitter (for dual-link dvi) */
-+	uint8_t secondary_transmitter_phy_id;
-+	/* bitmap with the active lanes */
-+	uint8_t secondary_transmitter_active_lanemap;
-+	/* misc phy settings for SMU. */
-+	uint32_t config_flags;
-+	uint32_t display_type;
-+	uint32_t view_resolution_cx;
-+	uint32_t view_resolution_cy;
-+	enum amd_pp_display_config_type displayconfigtype;
-+	uint32_t vertical_refresh; /* for active display */
-+};
-+
-+#define MAX_NUM_DISPLAY 32
-+
-+struct amd_pp_display_configuration {
-+	bool nb_pstate_switch_disable;/* controls NB PState switch */
-+	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
-+	bool cpu_pstate_disable;
-+	uint32_t cpu_pstate_separation_time;
-+
-+	uint32_t num_display;  /* total number of display*/
-+	uint32_t num_path_including_non_display;
-+	uint32_t crossfire_display_index;
-+	uint32_t min_mem_set_clock;
-+	uint32_t min_core_set_clock;
-+	/* unit 10KHz x bit*/
-+	uint32_t min_bus_bandwidth;
-+	/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
-+	uint32_t min_core_set_clock_in_sr;
-+
-+	struct single_display_configuration displays[MAX_NUM_DISPLAY];
-+
-+	uint32_t vrefresh; /* for active display*/
-+
-+	uint32_t min_vblank_time; /* for active display*/
-+	bool multi_monitor_in_sync;
-+	/* Controller Index of primary display - used in MCLK SMC switching hang
-+	 * SW Workaround*/
-+	uint32_t crtc_index;
-+	/* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
-+	uint32_t line_time_in_us;
-+	bool invalid_vblank_time;
-+
-+	uint32_t display_clk;
-+	/*
-+	 * for given display configuration if multimonitormnsync == false then
-+	 * Memory clock DPMS with this latency or below is allowed, DPMS with
-+	 * higher latency not allowed.
-+	 */
-+	uint32_t dce_tolerable_mclk_in_active_latency;
-+	uint32_t min_dcef_set_clk;
-+	uint32_t min_dcef_deep_sleep_set_clk;
-+};
-+
-+struct amd_pp_simple_clock_info {
-+	uint32_t	engine_max_clock;
-+	uint32_t	memory_max_clock;
-+	uint32_t	level;
-+};
-+
-+enum PP_DAL_POWERLEVEL {
-+	PP_DAL_POWERLEVEL_INVALID = 0,
-+	PP_DAL_POWERLEVEL_ULTRALOW,
-+	PP_DAL_POWERLEVEL_LOW,
-+	PP_DAL_POWERLEVEL_NOMINAL,
-+	PP_DAL_POWERLEVEL_PERFORMANCE,
-+
-+	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
-+	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
-+	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
-+	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
-+	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
-+	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
-+	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
-+	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
-+};
-+
-+struct amd_pp_clock_info {
-+	uint32_t min_engine_clock;
-+	uint32_t max_engine_clock;
-+	uint32_t min_memory_clock;
-+	uint32_t max_memory_clock;
-+	uint32_t min_bus_bandwidth;
-+	uint32_t max_bus_bandwidth;
-+	uint32_t max_engine_clock_in_sr;
-+	uint32_t min_engine_clock_in_sr;
-+	enum PP_DAL_POWERLEVEL max_clocks_state;
-+};
-+
-+enum amd_pp_clock_type {
-+	amd_pp_disp_clock = 1,
-+	amd_pp_sys_clock,
-+	amd_pp_mem_clock,
-+	amd_pp_dcef_clock,
-+	amd_pp_soc_clock,
-+	amd_pp_pixel_clock,
-+	amd_pp_phy_clock,
-+	amd_pp_dcf_clock,
-+	amd_pp_dpp_clock,
-+	amd_pp_f_clock = amd_pp_dcef_clock,
-+};
-+
-+#define MAX_NUM_CLOCKS 16
-+
-+struct amd_pp_clocks {
-+	uint32_t count;
-+	uint32_t clock[MAX_NUM_CLOCKS];
-+	uint32_t latency[MAX_NUM_CLOCKS];
-+};
-+
- struct pp_clock_with_latency {
- 	uint32_t clocks_in_khz;
- 	uint32_t latency_in_us;
-@@ -45,6 +184,11 @@ struct pp_clock_levels_with_voltage {
- 	struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS];
- };
- 
-+struct pp_display_clock_request {
-+	enum amd_pp_clock_type clock_type;
-+	uint32_t clock_freq_in_khz;
-+};
-+
- #define PP_MAX_WM_SETS 4
- 
- enum pp_wm_set_id {
---- linux-4.14/drivers/gpu/drm/amd/include/kgd_kfd_interface.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/kgd_kfd_interface.h	2017-12-14 06:39:58.466903603 +0100
-@@ -112,6 +112,9 @@ struct tile_config {
-  *
-  * @get_max_engine_clock_in_mhz: Retrieves maximum GPU clock in MHz
-  *
-+ * @alloc_pasid: Allocate a PASID
-+ * @free_pasid: Free a PASID
-+ *
-  * @program_sh_mem_settings: A function that should initiate the memory
-  * properties such as main aperture memory type (cache / non cached) and
-  * secondary aperture base address, size and memory type.
-@@ -160,6 +163,9 @@ struct kfd2kgd_calls {
- 
- 	uint32_t (*get_max_engine_clock_in_mhz)(struct kgd_dev *kgd);
- 
-+	int (*alloc_pasid)(unsigned int bits);
-+	void (*free_pasid)(unsigned int pasid);
-+
- 	/* Register access functions */
- 	void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid,
- 			uint32_t sh_mem_config,	uint32_t sh_mem_ape1_base,
---- linux-4.14/drivers/gpu/drm/amd/include/kgd_pp_interface.h.0130~	2017-12-14 06:39:58.466903603 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/kgd_pp_interface.h	2017-12-14 06:39:58.466903603 +0100
-@@ -0,0 +1,294 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef __KGD_PP_INTERFACE_H__
-+#define __KGD_PP_INTERFACE_H__
-+
-+extern const struct amd_ip_funcs pp_ip_funcs;
-+extern const struct amd_pm_funcs pp_dpm_funcs;
-+
-+struct amd_vce_state {
-+	/* vce clocks */
-+	u32 evclk;
-+	u32 ecclk;
-+	/* gpu clocks */
-+	u32 sclk;
-+	u32 mclk;
-+	u8 clk_idx;
-+	u8 pstate;
-+};
-+
-+
-+enum amd_dpm_forced_level {
-+	AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
-+	AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
-+	AMD_DPM_FORCED_LEVEL_LOW = 0x4,
-+	AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
-+	AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
-+	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
-+	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
-+	AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
-+	AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
-+};
-+
-+enum amd_pm_state_type {
-+	/* not used for dpm */
-+	POWER_STATE_TYPE_DEFAULT,
-+	POWER_STATE_TYPE_POWERSAVE,
-+	/* user selectable states */
-+	POWER_STATE_TYPE_BATTERY,
-+	POWER_STATE_TYPE_BALANCED,
-+	POWER_STATE_TYPE_PERFORMANCE,
-+	/* internal states */
-+	POWER_STATE_TYPE_INTERNAL_UVD,
-+	POWER_STATE_TYPE_INTERNAL_UVD_SD,
-+	POWER_STATE_TYPE_INTERNAL_UVD_HD,
-+	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
-+	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
-+	POWER_STATE_TYPE_INTERNAL_BOOT,
-+	POWER_STATE_TYPE_INTERNAL_THERMAL,
-+	POWER_STATE_TYPE_INTERNAL_ACPI,
-+	POWER_STATE_TYPE_INTERNAL_ULV,
-+	POWER_STATE_TYPE_INTERNAL_3DPERF,
-+};
-+
-+#define AMD_MAX_VCE_LEVELS 6
-+
-+enum amd_vce_level {
-+	AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
-+	AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
-+	AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
-+	AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
-+	AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
-+	AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
-+};
-+
-+enum amd_pp_profile_type {
-+	AMD_PP_GFX_PROFILE,
-+	AMD_PP_COMPUTE_PROFILE,
-+};
-+
-+struct amd_pp_profile {
-+	enum amd_pp_profile_type type;
-+	uint32_t min_sclk;
-+	uint32_t min_mclk;
-+	uint16_t activity_threshold;
-+	uint8_t up_hyst;
-+	uint8_t down_hyst;
-+};
-+
-+enum amd_fan_ctrl_mode {
-+	AMD_FAN_CTRL_NONE = 0,
-+	AMD_FAN_CTRL_MANUAL = 1,
-+	AMD_FAN_CTRL_AUTO = 2,
-+};
-+
-+enum pp_clock_type {
-+	PP_SCLK,
-+	PP_MCLK,
-+	PP_PCIE,
-+};
-+
-+enum amd_pp_sensors {
-+	AMDGPU_PP_SENSOR_GFX_SCLK = 0,
-+	AMDGPU_PP_SENSOR_VDDNB,
-+	AMDGPU_PP_SENSOR_VDDGFX,
-+	AMDGPU_PP_SENSOR_UVD_VCLK,
-+	AMDGPU_PP_SENSOR_UVD_DCLK,
-+	AMDGPU_PP_SENSOR_VCE_ECCLK,
-+	AMDGPU_PP_SENSOR_GPU_LOAD,
-+	AMDGPU_PP_SENSOR_GFX_MCLK,
-+	AMDGPU_PP_SENSOR_GPU_TEMP,
-+	AMDGPU_PP_SENSOR_VCE_POWER,
-+	AMDGPU_PP_SENSOR_UVD_POWER,
-+	AMDGPU_PP_SENSOR_GPU_POWER,
-+};
-+
-+enum amd_pp_task {
-+	AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
-+	AMD_PP_TASK_ENABLE_USER_STATE,
-+	AMD_PP_TASK_READJUST_POWER_STATE,
-+	AMD_PP_TASK_COMPLETE_INIT,
-+	AMD_PP_TASK_MAX
-+};
-+
-+struct amd_pp_init {
-+	struct cgs_device *device;
-+	uint32_t chip_family;
-+	uint32_t chip_id;
-+	bool pm_en;
-+	uint32_t feature_mask;
-+};
-+
-+
-+
-+enum {
-+	PP_GROUP_UNKNOWN = 0,
-+	PP_GROUP_GFX = 1,
-+	PP_GROUP_SYS,
-+	PP_GROUP_MAX
-+};
-+
-+struct pp_states_info {
-+	uint32_t nums;
-+	uint32_t states[16];
-+};
-+
-+struct pp_gpu_power {
-+	uint32_t vddc_power;
-+	uint32_t vddci_power;
-+	uint32_t max_gpu_power;
-+	uint32_t average_gpu_power;
-+};
-+
-+#define PP_GROUP_MASK        0xF0000000
-+#define PP_GROUP_SHIFT       28
-+
-+#define PP_BLOCK_MASK        0x0FFFFF00
-+#define PP_BLOCK_SHIFT       8
-+
-+#define PP_BLOCK_GFX_CG         0x01
-+#define PP_BLOCK_GFX_MG         0x02
-+#define PP_BLOCK_GFX_3D         0x04
-+#define PP_BLOCK_GFX_RLC        0x08
-+#define PP_BLOCK_GFX_CP         0x10
-+#define PP_BLOCK_SYS_BIF        0x01
-+#define PP_BLOCK_SYS_MC         0x02
-+#define PP_BLOCK_SYS_ROM        0x04
-+#define PP_BLOCK_SYS_DRM        0x08
-+#define PP_BLOCK_SYS_HDP        0x10
-+#define PP_BLOCK_SYS_SDMA       0x20
-+
-+#define PP_STATE_MASK           0x0000000F
-+#define PP_STATE_SHIFT          0
-+#define PP_STATE_SUPPORT_MASK   0x000000F0
-+#define PP_STATE_SUPPORT_SHIFT  0
-+
-+#define PP_STATE_CG             0x01
-+#define PP_STATE_LS             0x02
-+#define PP_STATE_DS             0x04
-+#define PP_STATE_SD             0x08
-+#define PP_STATE_SUPPORT_CG     0x10
-+#define PP_STATE_SUPPORT_LS     0x20
-+#define PP_STATE_SUPPORT_DS     0x40
-+#define PP_STATE_SUPPORT_SD     0x80
-+
-+#define PP_CG_MSG_ID(group, block, support, state) \
-+		((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
-+		(support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
-+
-+struct seq_file;
-+enum amd_pp_clock_type;
-+struct amd_pp_simple_clock_info;
-+struct amd_pp_display_configuration;
-+struct amd_pp_clock_info;
-+struct pp_display_clock_request;
-+struct pp_wm_sets_with_clock_ranges_soc15;
-+struct pp_clock_levels_with_voltage;
-+struct pp_clock_levels_with_latency;
-+struct amd_pp_clocks;
-+
-+struct amd_pm_funcs {
-+/* export for dpm on ci and si */
-+	int (*pre_set_power_state)(void *handle);
-+	int (*set_power_state)(void *handle);
-+	void (*post_set_power_state)(void *handle);
-+	void (*display_configuration_changed)(void *handle);
-+	void (*print_power_state)(void *handle, void *ps);
-+	bool (*vblank_too_short)(void *handle);
-+	void (*enable_bapm)(void *handle, bool enable);
-+	int (*check_state_equal)(void *handle,
-+				void  *cps,
-+				void  *rps,
-+				bool  *equal);
-+/* export for sysfs */
-+	int (*get_temperature)(void *handle);
-+	void (*set_fan_control_mode)(void *handle, u32 mode);
-+	u32 (*get_fan_control_mode)(void *handle);
-+	int (*set_fan_speed_percent)(void *handle, u32 speed);
-+	int (*get_fan_speed_percent)(void *handle, u32 *speed);
-+	int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
-+	int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
-+	int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
-+	int (*get_sclk_od)(void *handle);
-+	int (*set_sclk_od)(void *handle, uint32_t value);
-+	int (*get_mclk_od)(void *handle);
-+	int (*set_mclk_od)(void *handle, uint32_t value);
-+	int (*read_sensor)(void *handle, int idx, void *value, int *size);
-+	enum amd_dpm_forced_level (*get_performance_level)(void *handle);
-+	enum amd_pm_state_type (*get_current_power_state)(void *handle);
-+	int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
-+	int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
-+	int (*get_pp_table)(void *handle, char **table);
-+	int (*set_pp_table)(void *handle, const char *buf, size_t size);
-+	void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
-+
-+	int (*reset_power_profile_state)(void *handle,
-+			struct amd_pp_profile *request);
-+	int (*get_power_profile_state)(void *handle,
-+			struct amd_pp_profile *query);
-+	int (*set_power_profile_state)(void *handle,
-+			struct amd_pp_profile *request);
-+	int (*switch_power_profile)(void *handle,
-+			enum amd_pp_profile_type type);
-+/* export to amdgpu */
-+	void (*powergate_uvd)(void *handle, bool gate);
-+	void (*powergate_vce)(void *handle, bool gate);
-+	struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
-+	int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
-+				   void *input, void *output);
-+	int (*load_firmware)(void *handle);
-+	int (*wait_for_fw_loading_complete)(void *handle);
-+	int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
-+	int (*notify_smu_memory_info)(void *handle, uint32_t virtual_addr_low,
-+					uint32_t virtual_addr_hi,
-+					uint32_t mc_addr_low,
-+					uint32_t mc_addr_hi,
-+					uint32_t size);
-+/* export to DC */
-+	u32 (*get_sclk)(void *handle, bool low);
-+	u32 (*get_mclk)(void *handle, bool low);
-+	int (*display_configuration_change)(void *handle,
-+		const struct amd_pp_display_configuration *input);
-+	int (*get_display_power_level)(void *handle,
-+		struct amd_pp_simple_clock_info *output);
-+	int (*get_current_clocks)(void *handle,
-+		struct amd_pp_clock_info *clocks);
-+	int (*get_clock_by_type)(void *handle,
-+		enum amd_pp_clock_type type,
-+		struct amd_pp_clocks *clocks);
-+	int (*get_clock_by_type_with_latency)(void *handle,
-+		enum amd_pp_clock_type type,
-+		struct pp_clock_levels_with_latency *clocks);
-+	int (*get_clock_by_type_with_voltage)(void *handle,
-+		enum amd_pp_clock_type type,
-+		struct pp_clock_levels_with_voltage *clocks);
-+	int (*set_watermarks_for_clocks_ranges)(void *handle,
-+		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
-+	int (*display_clock_voltage_request)(void *handle,
-+				struct pp_display_clock_request *clock);
-+	int (*get_display_mode_validation_clocks)(void *handle,
-+		struct amd_pp_simple_clock_info *clocks);
-+};
-+
-+#endif
-\ No newline at end of file
---- linux-4.14/drivers/gpu/drm/amd/include/linux/chash.h.0130~	2017-12-14 06:39:58.467903604 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/linux/chash.h	2017-12-14 06:39:58.466903603 +0100
-@@ -0,0 +1,366 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef _LINUX_CHASH_H
-+#define _LINUX_CHASH_H
-+
-+#include <linux/types.h>
-+#include <linux/hash.h>
-+#include <linux/bug.h>
-+#include <asm/bitsperlong.h>
-+
-+#if BITS_PER_LONG == 32
-+# define _CHASH_LONG_SHIFT 5
-+#elif BITS_PER_LONG == 64
-+# define _CHASH_LONG_SHIFT 6
-+#else
-+# error "Unexpected BITS_PER_LONG"
-+#endif
-+
-+struct __chash_table {
-+	u8 bits;
-+	u8 key_size;
-+	unsigned int value_size;
-+	u32 size_mask;
-+	unsigned long *occup_bitmap, *valid_bitmap;
-+	union {
-+		u32 *keys32;
-+		u64 *keys64;
-+	};
-+	u8 *values;
-+
-+#ifdef CONFIG_CHASH_STATS
-+	u64 hits, hits_steps, hits_time_ns;
-+	u64 miss, miss_steps, miss_time_ns;
-+	u64 relocs, reloc_dist;
-+#endif
-+};
-+
-+#define __CHASH_BITMAP_SIZE(bits)				\
-+	(((1 << (bits)) + BITS_PER_LONG - 1) / BITS_PER_LONG)
-+#define __CHASH_ARRAY_SIZE(bits, size)				\
-+	((((size) << (bits)) + sizeof(long) - 1) / sizeof(long))
-+
-+#define __CHASH_DATA_SIZE(bits, key_size, value_size)	\
-+	(__CHASH_BITMAP_SIZE(bits) * 2 +		\
-+	 __CHASH_ARRAY_SIZE(bits, key_size) +		\
-+	 __CHASH_ARRAY_SIZE(bits, value_size))
-+
-+#define STRUCT_CHASH_TABLE(bits, key_size, value_size)			\
-+	struct {							\
-+		struct __chash_table table;				\
-+		unsigned long data					\
-+			[__CHASH_DATA_SIZE(bits, key_size, value_size)];\
-+	}
-+
-+/**
-+ * struct chash_table - Dynamically allocated closed hash table
-+ *
-+ * Use this struct for dynamically allocated hash tables (using
-+ * chash_table_alloc and chash_table_free), where the size is
-+ * determined at runtime.
-+ */
-+struct chash_table {
-+	struct __chash_table table;
-+	unsigned long *data;
-+};
-+
-+/**
-+ * DECLARE_CHASH_TABLE - macro to declare a closed hash table
-+ * @table: name of the declared hash table
-+ * @bts: Table size will be 2^bits entries
-+ * @key_sz: Size of hash keys in bytes, 4 or 8
-+ * @val_sz: Size of data values in bytes, can be 0
-+ *
-+ * This declares the hash table variable with a static size.
-+ *
-+ * The closed hash table stores key-value pairs with low memory and
-+ * lookup overhead. In operation it performs no dynamic memory
-+ * management. The data being stored does not require any
-+ * list_heads. The hash table performs best with small @val_sz and as
-+ * long as some space (about 50%) is left free in the table. But the
-+ * table can still work reasonably efficiently even when filled up to
-+ * about 90%. If bigger data items need to be stored and looked up,
-+ * store the pointer to it as value in the hash table.
-+ *
-+ * @val_sz may be 0. This can be useful when all the stored
-+ * information is contained in the key itself and the fact that it is
-+ * in the hash table (or not).
-+ */
-+#define DECLARE_CHASH_TABLE(table, bts, key_sz, val_sz)		\
-+	STRUCT_CHASH_TABLE(bts, key_sz, val_sz) table
-+
-+#ifdef CONFIG_CHASH_STATS
-+#define __CHASH_STATS_INIT(prefix),		\
-+		prefix.hits = 0,		\
-+		prefix.hits_steps = 0,		\
-+		prefix.hits_time_ns = 0,	\
-+		prefix.miss = 0,		\
-+		prefix.miss_steps = 0,		\
-+		prefix.miss_time_ns = 0,	\
-+		prefix.relocs = 0,		\
-+		prefix.reloc_dist = 0
-+#else
-+#define __CHASH_STATS_INIT(prefix)
-+#endif
-+
-+#define __CHASH_TABLE_INIT(prefix, data, bts, key_sz, val_sz)	\
-+	prefix.bits = (bts),					\
-+		prefix.key_size = (key_sz),			\
-+		prefix.value_size = (val_sz),			\
-+		prefix.size_mask = ((1 << bts) - 1),		\
-+		prefix.occup_bitmap = &data[0],			\
-+		prefix.valid_bitmap = &data			\
-+			[__CHASH_BITMAP_SIZE(bts)],		\
-+		prefix.keys64 = (u64 *)&data			\
-+			[__CHASH_BITMAP_SIZE(bts) * 2],		\
-+		prefix.values = (u8 *)&data			\
-+			[__CHASH_BITMAP_SIZE(bts) * 2 +		\
-+			 __CHASH_ARRAY_SIZE(bts, key_sz)]	\
-+		__CHASH_STATS_INIT(prefix)
-+
-+/**
-+ * DEFINE_CHASH_TABLE - macro to define and initialize a closed hash table
-+ * @tbl: name of the declared hash table
-+ * @bts: Table size will be 2^bits entries
-+ * @key_sz: Size of hash keys in bytes, 4 or 8
-+ * @val_sz: Size of data values in bytes, can be 0
-+ *
-+ * Note: the macro can be used for global and local hash table variables.
-+ */
-+#define DEFINE_CHASH_TABLE(tbl, bts, key_sz, val_sz)			\
-+	DECLARE_CHASH_TABLE(tbl, bts, key_sz, val_sz) = {		\
-+		.table = {						\
-+			__CHASH_TABLE_INIT(, (tbl).data, bts, key_sz, val_sz) \
-+		},							\
-+		.data = {0}						\
-+	}
-+
-+/**
-+ * INIT_CHASH_TABLE - Initialize a hash table declared by DECLARE_CHASH_TABLE
-+ * @tbl: name of the declared hash table
-+ * @bts: Table size will be 2^bits entries
-+ * @key_sz: Size of hash keys in bytes, 4 or 8
-+ * @val_sz: Size of data values in bytes, can be 0
-+ */
-+#define INIT_CHASH_TABLE(tbl, bts, key_sz, val_sz)			\
-+	__CHASH_TABLE_INIT(((tbl).table), (tbl).data, bts, key_sz, val_sz)
-+
-+int chash_table_alloc(struct chash_table *table, u8 bits, u8 key_size,
-+		      unsigned int value_size, gfp_t gfp_mask);
-+void chash_table_free(struct chash_table *table);
-+
-+/**
-+ * chash_table_dump_stats - Dump statistics of a closed hash table
-+ * @tbl: Pointer to the table structure
-+ *
-+ * Dumps some performance statistics of the table gathered in operation
-+ * in the kernel log using pr_debug. If CONFIG_DYNAMIC_DEBUG is enabled,
-+ * user must turn on messages for chash.c (file chash.c +p).
-+ */
-+#ifdef CONFIG_CHASH_STATS
-+#define chash_table_dump_stats(tbl) __chash_table_dump_stats(&(*tbl).table)
-+
-+void __chash_table_dump_stats(struct __chash_table *table);
-+#else
-+#define chash_table_dump_stats(tbl)
-+#endif
-+
-+/**
-+ * chash_table_reset_stats - Reset statistics of a closed hash table
-+ * @tbl: Pointer to the table structure
-+ */
-+#ifdef CONFIG_CHASH_STATS
-+#define chash_table_reset_stats(tbl) __chash_table_reset_stats(&(*tbl).table)
-+
-+static inline void __chash_table_reset_stats(struct __chash_table *table)
-+{
-+	(void)table __CHASH_STATS_INIT((*table));
-+}
-+#else
-+#define chash_table_reset_stats(tbl)
-+#endif
-+
-+/**
-+ * chash_table_copy_in - Copy a new value into the hash table
-+ * @tbl: Pointer to the table structure
-+ * @key: Key of the entry to add or update
-+ * @value: Pointer to value to copy, may be NULL
-+ *
-+ * If @key already has an entry, its value is replaced. Otherwise a
-+ * new entry is added. If @value is NULL, the value is left unchanged
-+ * or uninitialized. Returns 1 if an entry already existed, 0 if a new
-+ * entry was added or %-ENOMEM if there was no free space in the
-+ * table.
-+ */
-+#define chash_table_copy_in(tbl, key, value)			\
-+	__chash_table_copy_in(&(*tbl).table, key, value)
-+
-+int __chash_table_copy_in(struct __chash_table *table, u64 key,
-+			  const void *value);
-+
-+/**
-+ * chash_table_copy_out - Copy a value out of the hash table
-+ * @tbl: Pointer to the table structure
-+ * @key: Key of the entry to find
-+ * @value: Pointer to value to copy, may be NULL
-+ *
-+ * If @value is not NULL and the table has a non-0 value_size, the
-+ * value at @key is copied to @value. Returns the slot index of the
-+ * entry or %-EINVAL if @key was not found.
-+ */
-+#define chash_table_copy_out(tbl, key, value)			\
-+	__chash_table_copy_out(&(*tbl).table, key, value, false)
-+
-+int __chash_table_copy_out(struct __chash_table *table, u64 key,
-+			   void *value, bool remove);
-+
-+/**
-+ * chash_table_remove - Remove an entry from the hash table
-+ * @tbl: Pointer to the table structure
-+ * @key: Key of the entry to find
-+ * @value: Pointer to value to copy, may be NULL
-+ *
-+ * If @value is not NULL and the table has a non-0 value_size, the
-+ * value at @key is copied to @value. The entry is removed from the
-+ * table. Returns the slot index of the removed entry or %-EINVAL if
-+ * @key was not found.
-+ */
-+#define chash_table_remove(tbl, key, value)			\
-+	__chash_table_copy_out(&(*tbl).table, key, value, true)
-+
-+/*
-+ * Low level iterator API used internally by the above functions.
-+ */
-+struct chash_iter {
-+	struct __chash_table *table;
-+	unsigned long mask;
-+	int slot;
-+};
-+
-+/**
-+ * CHASH_ITER_INIT - Initialize a hash table iterator
-+ * @tbl: Pointer to hash table to iterate over
-+ * @s: Initial slot number
-+ */
-+#define CHASH_ITER_INIT(table, s) {			\
-+		table,					\
-+		1UL << ((s) & (BITS_PER_LONG - 1)),	\
-+		s					\
-+	}
-+/**
-+ * CHASH_ITER_SET - Set hash table iterator to new slot
-+ * @iter: Iterator
-+ * @s: Slot number
-+ */
-+#define CHASH_ITER_SET(iter, s)					\
-+	(iter).mask = 1UL << ((s) & (BITS_PER_LONG - 1)),	\
-+	(iter).slot = (s)
-+/**
-+ * CHASH_ITER_INC - Increment hash table iterator
-+ * @table: Hash table to iterate over
-+ *
-+ * Wraps around at the end.
-+ */
-+#define CHASH_ITER_INC(iter) do {					\
-+		(iter).mask = (iter).mask << 1 |			\
-+			(iter).mask >> (BITS_PER_LONG - 1);		\
-+		(iter).slot = ((iter).slot + 1) & (iter).table->size_mask; \
-+	} while (0)
-+
-+static inline bool chash_iter_is_valid(const struct chash_iter iter)
-+{
-+	BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
-+	return !!(iter.table->valid_bitmap[iter.slot >> _CHASH_LONG_SHIFT] &
-+		  iter.mask);
-+}
-+static inline bool chash_iter_is_empty(const struct chash_iter iter)
-+{
-+	BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
-+	return !(iter.table->occup_bitmap[iter.slot >> _CHASH_LONG_SHIFT] &
-+		 iter.mask);
-+}
-+
-+static inline void chash_iter_set_valid(const struct chash_iter iter)
-+{
-+	BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
-+	iter.table->valid_bitmap[iter.slot >> _CHASH_LONG_SHIFT] |= iter.mask;
-+	iter.table->occup_bitmap[iter.slot >> _CHASH_LONG_SHIFT] |= iter.mask;
-+}
-+static inline void chash_iter_set_invalid(const struct chash_iter iter)
-+{
-+	BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
-+	iter.table->valid_bitmap[iter.slot >> _CHASH_LONG_SHIFT] &= ~iter.mask;
-+}
-+static inline void chash_iter_set_empty(const struct chash_iter iter)
-+{
-+	BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
-+	iter.table->occup_bitmap[iter.slot >> _CHASH_LONG_SHIFT] &= ~iter.mask;
-+}
-+
-+static inline u32 chash_iter_key32(const struct chash_iter iter)
-+{
-+	BUG_ON(iter.table->key_size != 4);
-+	BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
-+	return iter.table->keys32[iter.slot];
-+}
-+static inline u64 chash_iter_key64(const struct chash_iter iter)
-+{
-+	BUG_ON(iter.table->key_size != 8);
-+	BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
-+	return iter.table->keys64[iter.slot];
-+}
-+static inline u64 chash_iter_key(const struct chash_iter iter)
-+{
-+	BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
-+	return (iter.table->key_size == 4) ?
-+		iter.table->keys32[iter.slot] : iter.table->keys64[iter.slot];
-+}
-+
-+static inline u32 chash_iter_hash32(const struct chash_iter iter)
-+{
-+	BUG_ON(iter.table->key_size != 4);
-+	return hash_32(chash_iter_key32(iter), iter.table->bits);
-+}
-+
-+static inline u32 chash_iter_hash64(const struct chash_iter iter)
-+{
-+	BUG_ON(iter.table->key_size != 8);
-+	return hash_64(chash_iter_key64(iter), iter.table->bits);
-+}
-+
-+static inline u32 chash_iter_hash(const struct chash_iter iter)
-+{
-+	return (iter.table->key_size == 4) ?
-+		hash_32(chash_iter_key32(iter), iter.table->bits) :
-+		hash_64(chash_iter_key64(iter), iter.table->bits);
-+}
-+
-+static inline void *chash_iter_value(const struct chash_iter iter)
-+{
-+	BUG_ON((unsigned)iter.slot >= (1 << iter.table->bits));
-+	return iter.table->values +
-+		((unsigned long)iter.slot * iter.table->value_size);
-+}
-+
-+#endif /* _LINUX_CHASH_H */
---- linux-4.14/drivers/gpu/drm/amd/include/v9_structs.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/v9_structs.h	2017-12-14 06:39:58.467903604 +0100
-@@ -284,8 +284,8 @@ struct v9_mqd {
- 	uint32_t gds_save_mask_hi;
- 	uint32_t ctx_save_base_addr_lo;
- 	uint32_t ctx_save_base_addr_hi;
--	uint32_t reserved_126;
--	uint32_t reserved_127;
-+	uint32_t dynamic_cu_mask_addr_lo;
-+	uint32_t dynamic_cu_mask_addr_hi;
- 	uint32_t cp_mqd_base_addr_lo;
- 	uint32_t cp_mqd_base_addr_hi;
- 	uint32_t cp_hqd_active;
-@@ -672,6 +672,14 @@ struct v9_mqd {
- 	uint32_t reserved_511;
- };
- 
-+struct v9_mqd_allocation {
-+	struct v9_mqd mqd;
-+	uint32_t wptr_poll_mem;
-+	uint32_t rptr_report_mem;
-+	uint32_t dynamic_cu_mask;
-+	uint32_t dynamic_rb_mask;
-+};
-+
- /* from vega10 all CSA format is shifted to chain ib compatible mode */
- struct v9_ce_ib_state {
-     /* section of non chained ib part */
---- linux-4.14/drivers/gpu/drm/amd/include/vi_structs.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/include/vi_structs.h	2017-12-14 06:39:58.467903604 +0100
-@@ -423,265 +423,6 @@ struct vi_mqd_allocation {
- 	uint32_t dynamic_rb_mask;
- };
- 
--struct cz_mqd {
--	uint32_t header;
--	uint32_t compute_dispatch_initiator;
--	uint32_t compute_dim_x;
--	uint32_t compute_dim_y;
--	uint32_t compute_dim_z;
--	uint32_t compute_start_x;
--	uint32_t compute_start_y;
--	uint32_t compute_start_z;
--	uint32_t compute_num_thread_x;
--	uint32_t compute_num_thread_y;
--	uint32_t compute_num_thread_z;
--	uint32_t compute_pipelinestat_enable;
--	uint32_t compute_perfcount_enable;
--	uint32_t compute_pgm_lo;
--	uint32_t compute_pgm_hi;
--	uint32_t compute_tba_lo;
--	uint32_t compute_tba_hi;
--	uint32_t compute_tma_lo;
--	uint32_t compute_tma_hi;
--	uint32_t compute_pgm_rsrc1;
--	uint32_t compute_pgm_rsrc2;
--	uint32_t compute_vmid;
--	uint32_t compute_resource_limits;
--	uint32_t compute_static_thread_mgmt_se0;
--	uint32_t compute_static_thread_mgmt_se1;
--	uint32_t compute_tmpring_size;
--	uint32_t compute_static_thread_mgmt_se2;
--	uint32_t compute_static_thread_mgmt_se3;
--	uint32_t compute_restart_x;
--	uint32_t compute_restart_y;
--	uint32_t compute_restart_z;
--	uint32_t compute_thread_trace_enable;
--	uint32_t compute_misc_reserved;
--	uint32_t compute_dispatch_id;
--	uint32_t compute_threadgroup_id;
--	uint32_t compute_relaunch;
--	uint32_t compute_wave_restore_addr_lo;
--	uint32_t compute_wave_restore_addr_hi;
--	uint32_t compute_wave_restore_control;
--	uint32_t reserved_39;
--	uint32_t reserved_40;
--	uint32_t reserved_41;
--	uint32_t reserved_42;
--	uint32_t reserved_43;
--	uint32_t reserved_44;
--	uint32_t reserved_45;
--	uint32_t reserved_46;
--	uint32_t reserved_47;
--	uint32_t reserved_48;
--	uint32_t reserved_49;
--	uint32_t reserved_50;
--	uint32_t reserved_51;
--	uint32_t reserved_52;
--	uint32_t reserved_53;
--	uint32_t reserved_54;
--	uint32_t reserved_55;
--	uint32_t reserved_56;
--	uint32_t reserved_57;
--	uint32_t reserved_58;
--	uint32_t reserved_59;
--	uint32_t reserved_60;
--	uint32_t reserved_61;
--	uint32_t reserved_62;
--	uint32_t reserved_63;
--	uint32_t reserved_64;
--	uint32_t compute_user_data_0;
--	uint32_t compute_user_data_1;
--	uint32_t compute_user_data_2;
--	uint32_t compute_user_data_3;
--	uint32_t compute_user_data_4;
--	uint32_t compute_user_data_5;
--	uint32_t compute_user_data_6;
--	uint32_t compute_user_data_7;
--	uint32_t compute_user_data_8;
--	uint32_t compute_user_data_9;
--	uint32_t compute_user_data_10;
--	uint32_t compute_user_data_11;
--	uint32_t compute_user_data_12;
--	uint32_t compute_user_data_13;
--	uint32_t compute_user_data_14;
--	uint32_t compute_user_data_15;
--	uint32_t cp_compute_csinvoc_count_lo;
--	uint32_t cp_compute_csinvoc_count_hi;
--	uint32_t reserved_83;
--	uint32_t reserved_84;
--	uint32_t reserved_85;
--	uint32_t cp_mqd_query_time_lo;
--	uint32_t cp_mqd_query_time_hi;
--	uint32_t cp_mqd_connect_start_time_lo;
--	uint32_t cp_mqd_connect_start_time_hi;
--	uint32_t cp_mqd_connect_end_time_lo;
--	uint32_t cp_mqd_connect_end_time_hi;
--	uint32_t cp_mqd_connect_end_wf_count;
--	uint32_t cp_mqd_connect_end_pq_rptr;
--	uint32_t cp_mqd_connect_end_pq_wptr;
--	uint32_t cp_mqd_connect_end_ib_rptr;
--	uint32_t reserved_96;
--	uint32_t reserved_97;
--	uint32_t cp_mqd_save_start_time_lo;
--	uint32_t cp_mqd_save_start_time_hi;
--	uint32_t cp_mqd_save_end_time_lo;
--	uint32_t cp_mqd_save_end_time_hi;
--	uint32_t cp_mqd_restore_start_time_lo;
--	uint32_t cp_mqd_restore_start_time_hi;
--	uint32_t cp_mqd_restore_end_time_lo;
--	uint32_t cp_mqd_restore_end_time_hi;
--	uint32_t reserved_106;
--	uint32_t reserved_107;
--	uint32_t gds_cs_ctxsw_cnt0;
--	uint32_t gds_cs_ctxsw_cnt1;
--	uint32_t gds_cs_ctxsw_cnt2;
--	uint32_t gds_cs_ctxsw_cnt3;
--	uint32_t reserved_112;
--	uint32_t reserved_113;
--	uint32_t cp_pq_exe_status_lo;
--	uint32_t cp_pq_exe_status_hi;
--	uint32_t cp_packet_id_lo;
--	uint32_t cp_packet_id_hi;
--	uint32_t cp_packet_exe_status_lo;
--	uint32_t cp_packet_exe_status_hi;
--	uint32_t gds_save_base_addr_lo;
--	uint32_t gds_save_base_addr_hi;
--	uint32_t gds_save_mask_lo;
--	uint32_t gds_save_mask_hi;
--	uint32_t ctx_save_base_addr_lo;
--	uint32_t ctx_save_base_addr_hi;
--	uint32_t reserved_126;
--	uint32_t reserved_127;
--	uint32_t cp_mqd_base_addr_lo;
--	uint32_t cp_mqd_base_addr_hi;
--	uint32_t cp_hqd_active;
--	uint32_t cp_hqd_vmid;
--	uint32_t cp_hqd_persistent_state;
--	uint32_t cp_hqd_pipe_priority;
--	uint32_t cp_hqd_queue_priority;
--	uint32_t cp_hqd_quantum;
--	uint32_t cp_hqd_pq_base_lo;
--	uint32_t cp_hqd_pq_base_hi;
--	uint32_t cp_hqd_pq_rptr;
--	uint32_t cp_hqd_pq_rptr_report_addr_lo;
--	uint32_t cp_hqd_pq_rptr_report_addr_hi;
--	uint32_t cp_hqd_pq_wptr_poll_addr_lo;
--	uint32_t cp_hqd_pq_wptr_poll_addr_hi;
--	uint32_t cp_hqd_pq_doorbell_control;
--	uint32_t cp_hqd_pq_wptr;
--	uint32_t cp_hqd_pq_control;
--	uint32_t cp_hqd_ib_base_addr_lo;
--	uint32_t cp_hqd_ib_base_addr_hi;
--	uint32_t cp_hqd_ib_rptr;
--	uint32_t cp_hqd_ib_control;
--	uint32_t cp_hqd_iq_timer;
--	uint32_t cp_hqd_iq_rptr;
--	uint32_t cp_hqd_dequeue_request;
--	uint32_t cp_hqd_dma_offload;
--	uint32_t cp_hqd_sema_cmd;
--	uint32_t cp_hqd_msg_type;
--	uint32_t cp_hqd_atomic0_preop_lo;
--	uint32_t cp_hqd_atomic0_preop_hi;
--	uint32_t cp_hqd_atomic1_preop_lo;
--	uint32_t cp_hqd_atomic1_preop_hi;
--	uint32_t cp_hqd_hq_status0;
--	uint32_t cp_hqd_hq_control0;
--	uint32_t cp_mqd_control;
--	uint32_t cp_hqd_hq_status1;
--	uint32_t cp_hqd_hq_control1;
--	uint32_t cp_hqd_eop_base_addr_lo;
--	uint32_t cp_hqd_eop_base_addr_hi;
--	uint32_t cp_hqd_eop_control;
--	uint32_t cp_hqd_eop_rptr;
--	uint32_t cp_hqd_eop_wptr;
--	uint32_t cp_hqd_eop_done_events;
--	uint32_t cp_hqd_ctx_save_base_addr_lo;
--	uint32_t cp_hqd_ctx_save_base_addr_hi;
--	uint32_t cp_hqd_ctx_save_control;
--	uint32_t cp_hqd_cntl_stack_offset;
--	uint32_t cp_hqd_cntl_stack_size;
--	uint32_t cp_hqd_wg_state_offset;
--	uint32_t cp_hqd_ctx_save_size;
--	uint32_t cp_hqd_gds_resource_state;
--	uint32_t cp_hqd_error;
--	uint32_t cp_hqd_eop_wptr_mem;
--	uint32_t cp_hqd_eop_dones;
--	uint32_t reserved_182;
--	uint32_t reserved_183;
--	uint32_t reserved_184;
--	uint32_t reserved_185;
--	uint32_t reserved_186;
--	uint32_t reserved_187;
--	uint32_t reserved_188;
--	uint32_t reserved_189;
--	uint32_t reserved_190;
--	uint32_t reserved_191;
--	uint32_t iqtimer_pkt_header;
--	uint32_t iqtimer_pkt_dw0;
--	uint32_t iqtimer_pkt_dw1;
--	uint32_t iqtimer_pkt_dw2;
--	uint32_t iqtimer_pkt_dw3;
--	uint32_t iqtimer_pkt_dw4;
--	uint32_t iqtimer_pkt_dw5;
--	uint32_t iqtimer_pkt_dw6;
--	uint32_t iqtimer_pkt_dw7;
--	uint32_t iqtimer_pkt_dw8;
--	uint32_t iqtimer_pkt_dw9;
--	uint32_t iqtimer_pkt_dw10;
--	uint32_t iqtimer_pkt_dw11;
--	uint32_t iqtimer_pkt_dw12;
--	uint32_t iqtimer_pkt_dw13;
--	uint32_t iqtimer_pkt_dw14;
--	uint32_t iqtimer_pkt_dw15;
--	uint32_t iqtimer_pkt_dw16;
--	uint32_t iqtimer_pkt_dw17;
--	uint32_t iqtimer_pkt_dw18;
--	uint32_t iqtimer_pkt_dw19;
--	uint32_t iqtimer_pkt_dw20;
--	uint32_t iqtimer_pkt_dw21;
--	uint32_t iqtimer_pkt_dw22;
--	uint32_t iqtimer_pkt_dw23;
--	uint32_t iqtimer_pkt_dw24;
--	uint32_t iqtimer_pkt_dw25;
--	uint32_t iqtimer_pkt_dw26;
--	uint32_t iqtimer_pkt_dw27;
--	uint32_t iqtimer_pkt_dw28;
--	uint32_t iqtimer_pkt_dw29;
--	uint32_t iqtimer_pkt_dw30;
--	uint32_t iqtimer_pkt_dw31;
--	uint32_t reserved_225;
--	uint32_t reserved_226;
--	uint32_t reserved_227;
--	uint32_t set_resources_header;
--	uint32_t set_resources_dw1;
--	uint32_t set_resources_dw2;
--	uint32_t set_resources_dw3;
--	uint32_t set_resources_dw4;
--	uint32_t set_resources_dw5;
--	uint32_t set_resources_dw6;
--	uint32_t set_resources_dw7;
--	uint32_t reserved_236;
--	uint32_t reserved_237;
--	uint32_t reserved_238;
--	uint32_t reserved_239;
--	uint32_t queue_doorbell_id0;
--	uint32_t queue_doorbell_id1;
--	uint32_t queue_doorbell_id2;
--	uint32_t queue_doorbell_id3;
--	uint32_t queue_doorbell_id4;
--	uint32_t queue_doorbell_id5;
--	uint32_t queue_doorbell_id6;
--	uint32_t queue_doorbell_id7;
--	uint32_t queue_doorbell_id8;
--	uint32_t queue_doorbell_id9;
--	uint32_t queue_doorbell_id10;
--	uint32_t queue_doorbell_id11;
--	uint32_t queue_doorbell_id12;
--	uint32_t queue_doorbell_id13;
--	uint32_t queue_doorbell_id14;
--	uint32_t queue_doorbell_id15;
--};
--
- struct vi_ce_ib_state {
- 	uint32_t    ce_ib_completion_status;
- 	uint32_t    ce_constegnine_count;
---- linux-4.14/drivers/gpu/drm/amd/lib/chash.c.0130~	2017-12-14 06:39:58.467903604 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/lib/chash.c	2017-12-14 06:39:58.467903604 +0100
-@@ -0,0 +1,638 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/hash.h>
-+#include <linux/bug.h>
-+#include <linux/slab.h>
-+#include <linux/module.h>
-+#include <linux/sched/clock.h>
-+#include <asm/div64.h>
-+#include <linux/chash.h>
-+
-+/**
-+ * chash_table_alloc - Allocate closed hash table
-+ * @table: Pointer to the table structure
-+ * @bits: Table size will be 2^bits entries
-+ * @key_size: Size of hash keys in bytes, 4 or 8
-+ * @value_size: Size of data values in bytes, can be 0
-+ */
-+int chash_table_alloc(struct chash_table *table, u8 bits, u8 key_size,
-+		      unsigned int value_size, gfp_t gfp_mask)
-+{
-+	if (bits > 31)
-+		return -EINVAL;
-+
-+	if (key_size != 4 && key_size != 8)
-+		return -EINVAL;
-+
-+	table->data = kcalloc(__CHASH_DATA_SIZE(bits, key_size, value_size),
-+		       sizeof(long), gfp_mask);
-+	if (!table->data)
-+		return -ENOMEM;
-+
-+	__CHASH_TABLE_INIT(table->table, table->data,
-+			   bits, key_size, value_size);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(chash_table_alloc);
-+
-+/**
-+ * chash_table_free - Free closed hash table
-+ * @table: Pointer to the table structure
-+ */
-+void chash_table_free(struct chash_table *table)
-+{
-+	kfree(table->data);
-+}
-+EXPORT_SYMBOL(chash_table_free);
-+
-+#ifdef CONFIG_CHASH_STATS
-+
-+#define DIV_FRAC(nom, denom, quot, frac, frac_digits) do {		\
-+		u64 __nom = (nom);					\
-+		u64 __denom = (denom);					\
-+		u64 __quot, __frac;					\
-+		u32 __rem;						\
-+									\
-+		while (__denom >> 32) {					\
-+			__nom   >>= 1;					\
-+			__denom >>= 1;					\
-+		}							\
-+		__quot = __nom;						\
-+		__rem  = do_div(__quot, __denom);			\
-+		__frac = __rem * (frac_digits) + (__denom >> 1);	\
-+		do_div(__frac, __denom);				\
-+		(quot) = __quot;					\
-+		(frac) = __frac;					\
-+	} while (0)
-+
-+void __chash_table_dump_stats(struct __chash_table *table)
-+{
-+	struct chash_iter iter = CHASH_ITER_INIT(table, 0);
-+	u32 filled = 0, empty = 0, tombstones = 0;
-+	u64 quot1, quot2;
-+	u32 frac1, frac2;
-+
-+	do {
-+		if (chash_iter_is_valid(iter))
-+			filled++;
-+		else if (chash_iter_is_empty(iter))
-+			empty++;
-+		else
-+			tombstones++;
-+		CHASH_ITER_INC(iter);
-+	} while (iter.slot);
-+
-+	pr_debug("chash: key size %u, value size %u\n",
-+		 table->key_size, table->value_size);
-+	pr_debug("  Slots total/filled/empty/tombstones: %u / %u / %u / %u\n",
-+		 1 << table->bits, filled, empty, tombstones);
-+	if (table->hits > 0) {
-+		DIV_FRAC(table->hits_steps, table->hits, quot1, frac1, 1000);
-+		DIV_FRAC(table->hits * 1000, table->hits_time_ns,
-+			 quot2, frac2, 1000);
-+	} else {
-+		quot1 = quot2 = 0;
-+		frac1 = frac2 = 0;
-+	}
-+	pr_debug("  Hits   (avg.cost, rate): %llu (%llu.%03u, %llu.%03u M/s)\n",
-+		 table->hits, quot1, frac1, quot2, frac2);
-+	if (table->miss > 0) {
-+		DIV_FRAC(table->miss_steps, table->miss, quot1, frac1, 1000);
-+		DIV_FRAC(table->miss * 1000, table->miss_time_ns,
-+			 quot2, frac2, 1000);
-+	} else {
-+		quot1 = quot2 = 0;
-+		frac1 = frac2 = 0;
-+	}
-+	pr_debug("  Misses (avg.cost, rate): %llu (%llu.%03u, %llu.%03u M/s)\n",
-+		 table->miss, quot1, frac1, quot2, frac2);
-+	if (table->hits + table->miss > 0) {
-+		DIV_FRAC(table->hits_steps + table->miss_steps,
-+			 table->hits + table->miss, quot1, frac1, 1000);
-+		DIV_FRAC((table->hits + table->miss) * 1000,
-+			 (table->hits_time_ns + table->miss_time_ns),
-+			 quot2, frac2, 1000);
-+	} else {
-+		quot1 = quot2 = 0;
-+		frac1 = frac2 = 0;
-+	}
-+	pr_debug("  Total  (avg.cost, rate): %llu (%llu.%03u, %llu.%03u M/s)\n",
-+		 table->hits + table->miss, quot1, frac1, quot2, frac2);
-+	if (table->relocs > 0) {
-+		DIV_FRAC(table->hits + table->miss, table->relocs,
-+			 quot1, frac1, 1000);
-+		DIV_FRAC(table->reloc_dist, table->relocs, quot2, frac2, 1000);
-+		pr_debug("  Relocations (freq, avg.dist): %llu (1:%llu.%03u, %llu.%03u)\n",
-+			 table->relocs, quot1, frac1, quot2, frac2);
-+	} else {
-+		pr_debug("  No relocations\n");
-+	}
-+}
-+EXPORT_SYMBOL(__chash_table_dump_stats);
-+
-+#undef DIV_FRAC
-+#endif
-+
-+#define CHASH_INC(table, a) ((a) = ((a) + 1) & (table)->size_mask)
-+#define CHASH_ADD(table, a, b) (((a) + (b)) & (table)->size_mask)
-+#define CHASH_SUB(table, a, b) (((a) - (b)) & (table)->size_mask)
-+#define CHASH_IN_RANGE(table, slot, first, last) \
-+	(CHASH_SUB(table, slot, first) <= CHASH_SUB(table, last, first))
-+
-+/*#define CHASH_DEBUG Uncomment this to enable verbose debug output*/
-+#ifdef CHASH_DEBUG
-+static void chash_table_dump(struct __chash_table *table)
-+{
-+	struct chash_iter iter = CHASH_ITER_INIT(table, 0);
-+
-+	do {
-+		if ((iter.slot & 3) == 0)
-+			pr_debug("%04x: ", iter.slot);
-+
-+		if (chash_iter_is_valid(iter))
-+			pr_debug("[%016llx] ", chash_iter_key(iter));
-+		else if (chash_iter_is_empty(iter))
-+			pr_debug("[    <empty>     ] ");
-+		else
-+			pr_debug("[  <tombstone>   ] ");
-+
-+		if ((iter.slot & 3) == 3)
-+			pr_debug("\n");
-+
-+		CHASH_ITER_INC(iter);
-+	} while (iter.slot);
-+
-+	if ((iter.slot & 3) != 0)
-+		pr_debug("\n");
-+}
-+
-+static int chash_table_check(struct __chash_table *table)
-+{
-+	u32 hash;
-+	struct chash_iter iter = CHASH_ITER_INIT(table, 0);
-+	struct chash_iter cur = CHASH_ITER_INIT(table, 0);
-+
-+	do {
-+		if (!chash_iter_is_valid(iter)) {
-+			CHASH_ITER_INC(iter);
-+			continue;
-+		}
-+
-+		hash = chash_iter_hash(iter);
-+		CHASH_ITER_SET(cur, hash);
-+		while (cur.slot != iter.slot) {
-+			if (chash_iter_is_empty(cur)) {
-+				pr_err("Path to element at %x with hash %x broken at slot %x\n",
-+				       iter.slot, hash, cur.slot);
-+				chash_table_dump(table);
-+				return -EINVAL;
-+			}
-+			CHASH_ITER_INC(cur);
-+		}
-+
-+		CHASH_ITER_INC(iter);
-+	} while (iter.slot);
-+
-+	return 0;
-+}
-+#endif
-+
-+static void chash_iter_relocate(struct chash_iter dst, struct chash_iter src)
-+{
-+	BUG_ON(src.table == dst.table && src.slot == dst.slot);
-+	BUG_ON(src.table->key_size != dst.table->key_size);
-+	BUG_ON(src.table->value_size != dst.table->value_size);
-+
-+	if (dst.table->key_size == 4)
-+		dst.table->keys32[dst.slot] = src.table->keys32[src.slot];
-+	else
-+		dst.table->keys64[dst.slot] = src.table->keys64[src.slot];
-+
-+	if (dst.table->value_size)
-+		memcpy(chash_iter_value(dst), chash_iter_value(src),
-+		       dst.table->value_size);
-+
-+	chash_iter_set_valid(dst);
-+	chash_iter_set_invalid(src);
-+
-+#ifdef CONFIG_CHASH_STATS
-+	if (src.table == dst.table) {
-+		dst.table->relocs++;
-+		dst.table->reloc_dist +=
-+			CHASH_SUB(dst.table, src.slot, dst.slot);
-+	}
-+#endif
-+}
-+
-+/**
-+ * __chash_table_find - Helper for looking up a hash table entry
-+ * @iter: Pointer to hash table iterator
-+ * @key: Key of the entry to find
-+ * @for_removal: set to true if the element will be removed soon
-+ *
-+ * Searches for an entry in the hash table with a given key. iter must
-+ * be initialized by the caller to point to the home position of the
-+ * hypothetical entry, i.e. it must be initialized with the hash table
-+ * and the key's hash as the initial slot for the search.
-+ *
-+ * This function also does some local clean-up to speed up future
-+ * look-ups by relocating entries to better slots and removing
-+ * tombstones that are no longer needed.
-+ *
-+ * If @for_removal is true, the function avoids relocating the entry
-+ * that is being returned.
-+ *
-+ * Returns 0 if the search is successful. In this case iter is updated
-+ * to point to the found entry. Otherwise %-EINVAL is returned and the
-+ * iter is updated to point to the first available slot for the given
-+ * key. If the table is full, the slot is set to -1.
-+ */
-+static int chash_table_find(struct chash_iter *iter, u64 key,
-+			    bool for_removal)
-+{
-+#ifdef CONFIG_CHASH_STATS
-+	u64 ts1 = local_clock();
-+#endif
-+	u32 hash = iter->slot;
-+	struct chash_iter first_redundant = CHASH_ITER_INIT(iter->table, -1);
-+	int first_avail = (for_removal ? -2 : -1);
-+
-+	while (!chash_iter_is_valid(*iter) || chash_iter_key(*iter) != key) {
-+		if (chash_iter_is_empty(*iter)) {
-+			/* Found an empty slot, which ends the
-+			 * search. Clean up any preceding tombstones
-+			 * that are no longer needed because they lead
-+			 * to no-where
-+			 */
-+			if ((int)first_redundant.slot < 0)
-+				goto not_found;
-+			while (first_redundant.slot != iter->slot) {
-+				if (!chash_iter_is_valid(first_redundant))
-+					chash_iter_set_empty(first_redundant);
-+				CHASH_ITER_INC(first_redundant);
-+			}
-+#ifdef CHASH_DEBUG
-+			chash_table_check(iter->table);
-+#endif
-+			goto not_found;
-+		} else if (!chash_iter_is_valid(*iter)) {
-+			/* Found a tombstone. Remember it as candidate
-+			 * for relocating the entry we're looking for
-+			 * or for adding a new entry with the given key
-+			 */
-+			if (first_avail == -1)
-+				first_avail = iter->slot;
-+			/* Or mark it as the start of a series of
-+			 * potentially redundant tombstones
-+			 */
-+			else if (first_redundant.slot == -1)
-+				CHASH_ITER_SET(first_redundant, iter->slot);
-+		} else if (first_redundant.slot >= 0) {
-+			/* Found a valid, occupied slot with a
-+			 * preceding series of tombstones. Relocate it
-+			 * to a better position that no longer depends
-+			 * on those tombstones
-+			 */
-+			u32 cur_hash = chash_iter_hash(*iter);
-+
-+			if (!CHASH_IN_RANGE(iter->table, cur_hash,
-+					    first_redundant.slot + 1,
-+					    iter->slot)) {
-+				/* This entry has a hash at or before
-+				 * the first tombstone we found. We
-+				 * can relocate it to that tombstone
-+				 * and advance to the next tombstone
-+				 */
-+				chash_iter_relocate(first_redundant, *iter);
-+				do {
-+					CHASH_ITER_INC(first_redundant);
-+				} while (chash_iter_is_valid(first_redundant));
-+			} else if (cur_hash != iter->slot) {
-+				/* Relocate entry to its home position
-+				 * or as close as possible so it no
-+				 * longer depends on any preceding
-+				 * tombstones
-+				 */
-+				struct chash_iter new_iter =
-+					CHASH_ITER_INIT(iter->table, cur_hash);
-+
-+				while (new_iter.slot != iter->slot &&
-+				       chash_iter_is_valid(new_iter))
-+					CHASH_ITER_INC(new_iter);
-+
-+				if (new_iter.slot != iter->slot)
-+					chash_iter_relocate(new_iter, *iter);
-+			}
-+		}
-+
-+		CHASH_ITER_INC(*iter);
-+		if (iter->slot == hash) {
-+			iter->slot = -1;
-+			goto not_found;
-+		}
-+	}
-+
-+#ifdef CONFIG_CHASH_STATS
-+	iter->table->hits++;
-+	iter->table->hits_steps += CHASH_SUB(iter->table, iter->slot, hash) + 1;
-+#endif
-+
-+	if (first_avail >= 0) {
-+		CHASH_ITER_SET(first_redundant, first_avail);
-+		chash_iter_relocate(first_redundant, *iter);
-+		iter->slot = first_redundant.slot;
-+		iter->mask = first_redundant.mask;
-+	}
-+
-+#ifdef CONFIG_CHASH_STATS
-+	iter->table->hits_time_ns += local_clock() - ts1;
-+#endif
-+
-+	return 0;
-+
-+not_found:
-+#ifdef CONFIG_CHASH_STATS
-+	iter->table->miss++;
-+	iter->table->miss_steps += (iter->slot < 0) ?
-+		(1 << iter->table->bits) :
-+		CHASH_SUB(iter->table, iter->slot, hash) + 1;
-+#endif
-+
-+	if (first_avail >= 0)
-+		CHASH_ITER_SET(*iter, first_avail);
-+
-+#ifdef CONFIG_CHASH_STATS
-+	iter->table->miss_time_ns += local_clock() - ts1;
-+#endif
-+
-+	return -EINVAL;
-+}
-+
-+int __chash_table_copy_in(struct __chash_table *table, u64 key,
-+			  const void *value)
-+{
-+	u32 hash = (table->key_size == 4) ?
-+		hash_32(key, table->bits) : hash_64(key, table->bits);
-+	struct chash_iter iter = CHASH_ITER_INIT(table, hash);
-+	int r = chash_table_find(&iter, key, false);
-+
-+	/* Found an existing entry */
-+	if (!r) {
-+		if (value && table->value_size)
-+			memcpy(chash_iter_value(iter), value,
-+			       table->value_size);
-+		return 1;
-+	}
-+
-+	/* Is there a place to add a new entry? */
-+	if (iter.slot < 0) {
-+		pr_err("Hash table overflow\n");
-+		return -ENOMEM;
-+	}
-+
-+	chash_iter_set_valid(iter);
-+
-+	if (table->key_size == 4)
-+		table->keys32[iter.slot] = key;
-+	else
-+		table->keys64[iter.slot] = key;
-+	if (value && table->value_size)
-+		memcpy(chash_iter_value(iter), value, table->value_size);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(__chash_table_copy_in);
-+
-+int __chash_table_copy_out(struct __chash_table *table, u64 key,
-+			   void *value, bool remove)
-+{
-+	u32 hash = (table->key_size == 4) ?
-+		hash_32(key, table->bits) : hash_64(key, table->bits);
-+	struct chash_iter iter = CHASH_ITER_INIT(table, hash);
-+	int r = chash_table_find(&iter, key, remove);
-+
-+	if (r < 0)
-+		return r;
-+
-+	if (value && table->value_size)
-+		memcpy(value, chash_iter_value(iter), table->value_size);
-+
-+	if (remove)
-+		chash_iter_set_invalid(iter);
-+
-+	return iter.slot;
-+}
-+EXPORT_SYMBOL(__chash_table_copy_out);
-+
-+#ifdef CONFIG_CHASH_SELFTEST
-+/**
-+ * chash_self_test - Run a self-test of the hash table implementation
-+ * @bits: Table size will be 2^bits entries
-+ * @key_size: Size of hash keys in bytes, 4 or 8
-+ * @min_fill: Minimum fill level during the test
-+ * @max_fill: Maximum fill level during the test
-+ * @iterations: Number of test iterations
-+ *
-+ * The test adds and removes entries from a hash table, cycling the
-+ * fill level between min_fill and max_fill entries. Also tests lookup
-+ * and value retrieval.
-+ */
-+static int __init chash_self_test(u8 bits, u8 key_size,
-+				  int min_fill, int max_fill,
-+				  u64 iterations)
-+{
-+	struct chash_table table;
-+	int ret;
-+	u64 add_count, rmv_count;
-+	u64 value;
-+
-+	if (key_size == 4 && iterations > 0xffffffff)
-+		return -EINVAL;
-+	if (min_fill >= max_fill)
-+		return -EINVAL;
-+
-+	ret = chash_table_alloc(&table, bits, key_size, sizeof(u64),
-+				GFP_KERNEL);
-+	if (ret) {
-+		pr_err("chash_table_alloc failed: %d\n", ret);
-+		return ret;
-+	}
-+
-+	for (add_count = 0, rmv_count = 0; add_count < iterations;
-+	     add_count++) {
-+		/* When we hit the max_fill level, remove entries down
-+		 * to min_fill
-+		 */
-+		if (add_count - rmv_count == max_fill) {
-+			u64 find_count = rmv_count;
-+
-+			/* First try to find all entries that we're
-+			 * about to remove, confirm their value, test
-+			 * writing them back a second time.
-+			 */
-+			for (; add_count - find_count > min_fill;
-+			     find_count++) {
-+				ret = chash_table_copy_out(&table, find_count,
-+							   &value);
-+				if (ret < 0) {
-+					pr_err("chash_table_copy_out failed: %d\n",
-+					       ret);
-+					goto out;
-+				}
-+				if (value != ~find_count) {
-+					pr_err("Wrong value retrieved for key 0x%llx, expected 0x%llx got 0x%llx\n",
-+					       find_count, ~find_count, value);
-+#ifdef CHASH_DEBUG
-+					chash_table_dump(&table.table);
-+#endif
-+					ret = -EFAULT;
-+					goto out;
-+				}
-+				ret = chash_table_copy_in(&table, find_count,
-+							  &value);
-+				if (ret != 1) {
-+					pr_err("copy_in second time returned %d, expected 1\n",
-+					       ret);
-+					ret = -EFAULT;
-+					goto out;
-+				}
-+			}
-+			/* Remove them until we hit min_fill level */
-+			for (; add_count - rmv_count > min_fill; rmv_count++) {
-+				ret = chash_table_remove(&table, rmv_count,
-+							 NULL);
-+				if (ret < 0) {
-+					pr_err("chash_table_remove failed: %d\n",
-+					       ret);
-+					goto out;
-+				}
-+			}
-+		}
-+
-+		/* Add a new value */
-+		value = ~add_count;
-+		ret = chash_table_copy_in(&table, add_count, &value);
-+		if (ret != 0) {
-+			pr_err("copy_in first time returned %d, expected 0\n",
-+			       ret);
-+			ret = -EFAULT;
-+			goto out;
-+		}
-+	}
-+
-+	chash_table_dump_stats(&table);
-+	chash_table_reset_stats(&table);
-+
-+out:
-+	chash_table_free(&table);
-+	return ret;
-+}
-+
-+static unsigned int chash_test_bits = 10;
-+MODULE_PARM_DESC(test_bits,
-+		 "Selftest number of hash bits ([4..20], default=10)");
-+module_param_named(test_bits, chash_test_bits, uint, 0444);
-+
-+static unsigned int chash_test_keysize = 8;
-+MODULE_PARM_DESC(test_keysize, "Selftest keysize (4 or 8, default=8)");
-+module_param_named(test_keysize, chash_test_keysize, uint, 0444);
-+
-+static unsigned int chash_test_minfill;
-+MODULE_PARM_DESC(test_minfill, "Selftest minimum #entries (default=50%)");
-+module_param_named(test_minfill, chash_test_minfill, uint, 0444);
-+
-+static unsigned int chash_test_maxfill;
-+MODULE_PARM_DESC(test_maxfill, "Selftest maximum #entries (default=80%)");
-+module_param_named(test_maxfill, chash_test_maxfill, uint, 0444);
-+
-+static unsigned long chash_test_iters;
-+MODULE_PARM_DESC(test_iters, "Selftest iterations (default=1000 x #entries)");
-+module_param_named(test_iters, chash_test_iters, ulong, 0444);
-+
-+static int __init chash_init(void)
-+{
-+	int ret;
-+	u64 ts1_ns;
-+
-+	/* Skip self test on user errors */
-+	if (chash_test_bits < 4 || chash_test_bits > 20) {
-+		pr_err("chash: test_bits out of range [4..20].\n");
-+		return 0;
-+	}
-+	if (chash_test_keysize != 4 && chash_test_keysize != 8) {
-+		pr_err("chash: test_keysize invalid. Must be 4 or 8.\n");
-+		return 0;
-+	}
-+
-+	if (!chash_test_minfill)
-+		chash_test_minfill = (1 << chash_test_bits) / 2;
-+	if (!chash_test_maxfill)
-+		chash_test_maxfill = (1 << chash_test_bits) * 4 / 5;
-+	if (!chash_test_iters)
-+		chash_test_iters = (1 << chash_test_bits) * 1000;
-+
-+	if (chash_test_minfill >= (1 << chash_test_bits)) {
-+		pr_err("chash: test_minfill too big. Must be < table size.\n");
-+		return 0;
-+	}
-+	if (chash_test_maxfill >= (1 << chash_test_bits)) {
-+		pr_err("chash: test_maxfill too big. Must be < table size.\n");
-+		return 0;
-+	}
-+	if (chash_test_minfill >= chash_test_maxfill) {
-+		pr_err("chash: test_minfill must be < test_maxfill.\n");
-+		return 0;
-+	}
-+	if (chash_test_keysize == 4 && chash_test_iters > 0xffffffff) {
-+		pr_err("chash: test_iters must be < 4G for 4 byte keys.\n");
-+		return 0;
-+	}
-+
-+	ts1_ns = local_clock();
-+	ret = chash_self_test(chash_test_bits, chash_test_keysize,
-+			      chash_test_minfill, chash_test_maxfill,
-+			      chash_test_iters);
-+	if (!ret) {
-+		u64 ts_delta_us = local_clock() - ts1_ns;
-+		u64 iters_per_second = (u64)chash_test_iters * 1000000;
-+
-+		do_div(ts_delta_us, 1000);
-+		do_div(iters_per_second, ts_delta_us);
-+		pr_info("chash: self test took %llu us, %llu iterations/s\n",
-+			ts_delta_us, iters_per_second);
-+	} else {
-+		pr_err("chash: self test failed: %d\n", ret);
-+	}
-+
-+	return ret;
-+}
-+
-+module_init(chash_init);
-+
-+#endif /* CONFIG_CHASH_SELFTEST */
-+
-+MODULE_DESCRIPTION("Closed hash table");
-+MODULE_LICENSE("GPL and additional rights");
---- linux-4.14/drivers/gpu/drm/amd/lib/Kconfig.0130~	2017-12-14 06:39:58.467903604 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/lib/Kconfig	2017-12-14 06:39:58.467903604 +0100
-@@ -0,0 +1,28 @@
-+menu "AMD Library routines"
-+
-+#
-+# Closed hash table
-+#
-+config CHASH
-+	tristate
-+	default DRM_AMDGPU
-+	help
-+	 Statically sized closed hash table implementation with low
-+	 memory and CPU overhead.
-+
-+config CHASH_STATS
-+	bool "Closed hash table performance statistics"
-+	depends on CHASH
-+	default n
-+	help
-+	 Enable collection of performance statistics for closed hash tables.
-+
-+config CHASH_SELFTEST
-+	bool "Closed hash table self test"
-+	depends on CHASH
-+	default n
-+	help
-+	 Runs a selftest during module load. Several module parameters
-+	 are available to modify the behaviour of the test.
-+
-+endmenu
---- linux-4.14/drivers/gpu/drm/amd/lib/Makefile.0130~	2017-12-14 06:39:58.467903604 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/lib/Makefile	2017-12-14 06:39:58.467903604 +0100
-@@ -0,0 +1,11 @@
-+#
-+# Makefile for AMD library routines, which are used by AMD driver
-+# components.
-+#
-+# This is for common library routines that can be shared between AMD
-+# driver components or later moved to kernel/lib for sharing with
-+# other drivers.
-+
-+ccflags-y := -I$(src)/../include
-+
-+obj-$(CONFIG_CHASH) += chash.o
---- linux-4.14/drivers/gpu/drm/amd/powerplay/amd_powerplay.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/amd_powerplay.c	2017-12-14 06:39:58.467903604 +0100
-@@ -29,158 +29,186 @@
- #include "amd_powerplay.h"
- #include "pp_instance.h"
- #include "power_state.h"
--#include "eventmanager.h"
- 
-+#define PP_DPM_DISABLED 0xCCCC
-+
-+static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
-+		void *input, void *output);
- 
- static inline int pp_check(struct pp_instance *handle)
- {
--	if (handle == NULL || handle->pp_valid != PP_VALID)
-+	if (handle == NULL)
- 		return -EINVAL;
- 
--	if (handle->smu_mgr == NULL || handle->smu_mgr->smumgr_funcs == NULL)
-+	if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL)
- 		return -EINVAL;
- 
- 	if (handle->pm_en == 0)
- 		return PP_DPM_DISABLED;
- 
--	if (handle->hwmgr == NULL || handle->hwmgr->hwmgr_func == NULL
--		|| handle->eventmgr == NULL)
-+	if (handle->hwmgr->hwmgr_func == NULL)
- 		return PP_DPM_DISABLED;
- 
- 	return 0;
- }
- 
-+static int amd_powerplay_create(struct amd_pp_init *pp_init,
-+				void **handle)
-+{
-+	struct pp_instance *instance;
-+
-+	if (pp_init == NULL || handle == NULL)
-+		return -EINVAL;
-+
-+	instance = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
-+	if (instance == NULL)
-+		return -ENOMEM;
-+
-+	instance->chip_family = pp_init->chip_family;
-+	instance->chip_id = pp_init->chip_id;
-+	instance->pm_en = pp_init->pm_en;
-+	instance->feature_mask = pp_init->feature_mask;
-+	instance->device = pp_init->device;
-+	mutex_init(&instance->pp_lock);
-+	*handle = instance;
-+	return 0;
-+}
-+
-+static int amd_powerplay_destroy(void *handle)
-+{
-+	struct pp_instance *instance = (struct pp_instance *)handle;
-+
-+	kfree(instance->hwmgr->hardcode_pp_table);
-+	instance->hwmgr->hardcode_pp_table = NULL;
-+
-+	kfree(instance->hwmgr);
-+	instance->hwmgr = NULL;
-+
-+	kfree(instance);
-+	instance = NULL;
-+	return 0;
-+}
-+
- static int pp_early_init(void *handle)
- {
- 	int ret;
--	struct pp_instance *pp_handle = (struct pp_instance *)handle;
-+	struct pp_instance *pp_handle = NULL;
- 
--	ret = smum_early_init(pp_handle);
--	if (ret)
--		return ret;
-+	pp_handle = cgs_register_pp_handle(handle, amd_powerplay_create);
- 
--	if ((pp_handle->pm_en == 0)
--		|| cgs_is_virtualization_enabled(pp_handle->device))
--		return PP_DPM_DISABLED;
-+	if (!pp_handle)
-+		return -EINVAL;
- 
- 	ret = hwmgr_early_init(pp_handle);
--	if (ret) {
--		pp_handle->pm_en = 0;
--		return PP_DPM_DISABLED;
--	}
--
--	ret = eventmgr_early_init(pp_handle);
--	if (ret) {
--		kfree(pp_handle->hwmgr);
--		pp_handle->hwmgr = NULL;
--		pp_handle->pm_en = 0;
--		return PP_DPM_DISABLED;
--	}
-+	if (ret)
-+		return -EINVAL;
- 
- 	return 0;
- }
- 
- static int pp_sw_init(void *handle)
- {
--	struct pp_smumgr *smumgr;
-+	struct pp_hwmgr *hwmgr;
- 	int ret = 0;
- 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret == 0 || ret == PP_DPM_DISABLED) {
--		smumgr = pp_handle->smu_mgr;
-+	if (ret >= 0) {
-+		hwmgr = pp_handle->hwmgr;
- 
--		if (smumgr->smumgr_funcs->smu_init == NULL)
-+		if (hwmgr->smumgr_funcs->smu_init == NULL)
- 			return -EINVAL;
- 
--		ret = smumgr->smumgr_funcs->smu_init(smumgr);
-+		ret = hwmgr->smumgr_funcs->smu_init(hwmgr);
- 
--		pr_info("amdgpu: powerplay sw initialized\n");
-+		pr_debug("amdgpu: powerplay sw initialized\n");
- 	}
- 	return ret;
- }
- 
- static int pp_sw_fini(void *handle)
- {
--	struct pp_smumgr *smumgr;
-+	struct pp_hwmgr *hwmgr;
- 	int ret = 0;
- 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
- 
- 	ret = pp_check(pp_handle);
--	if (ret == 0 || ret == PP_DPM_DISABLED) {
--		smumgr = pp_handle->smu_mgr;
-+	if (ret >= 0) {
-+		hwmgr = pp_handle->hwmgr;
- 
--		if (smumgr->smumgr_funcs->smu_fini == NULL)
-+		if (hwmgr->smumgr_funcs->smu_fini == NULL)
- 			return -EINVAL;
- 
--		ret = smumgr->smumgr_funcs->smu_fini(smumgr);
-+		ret = hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
- 	}
- 	return ret;
- }
- 
- static int pp_hw_init(void *handle)
- {
--	struct pp_smumgr *smumgr;
--	struct pp_eventmgr *eventmgr;
- 	int ret = 0;
- 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
-+	struct pp_hwmgr *hwmgr;
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret == 0 || ret == PP_DPM_DISABLED) {
--		smumgr = pp_handle->smu_mgr;
-+	if (ret >= 0) {
-+		hwmgr = pp_handle->hwmgr;
- 
--		if (smumgr->smumgr_funcs->start_smu == NULL)
-+		if (hwmgr->smumgr_funcs->start_smu == NULL)
- 			return -EINVAL;
- 
--		if(smumgr->smumgr_funcs->start_smu(smumgr)) {
-+		if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
- 			pr_err("smc start failed\n");
--			smumgr->smumgr_funcs->smu_fini(smumgr);
-+			hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
- 			return -EINVAL;;
- 		}
- 		if (ret == PP_DPM_DISABLED)
--			return PP_DPM_DISABLED;
-+			goto exit;
-+		ret = hwmgr_hw_init(pp_handle);
-+		if (ret)
-+			goto exit;
- 	}
--
--	ret = hwmgr_hw_init(pp_handle);
--	if (ret)
--		goto err;
--
--	eventmgr = pp_handle->eventmgr;
--	if (eventmgr->pp_eventmgr_init == NULL ||
--		eventmgr->pp_eventmgr_init(eventmgr))
--		goto err;
--
--	return 0;
--err:
-+	return ret;
-+exit:
- 	pp_handle->pm_en = 0;
--	kfree(pp_handle->eventmgr);
--	kfree(pp_handle->hwmgr);
--	pp_handle->hwmgr = NULL;
--	pp_handle->eventmgr = NULL;
--	return PP_DPM_DISABLED;
-+	cgs_notify_dpm_enabled(hwmgr->device, false);
-+	return 0;
-+
- }
- 
- static int pp_hw_fini(void *handle)
- {
--	struct pp_eventmgr *eventmgr;
- 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
- 	int ret = 0;
- 
- 	ret = pp_check(pp_handle);
-+	if (ret == 0)
-+		hwmgr_hw_fini(pp_handle);
- 
--	if (ret == 0) {
--		eventmgr = pp_handle->eventmgr;
-+	return 0;
-+}
- 
--		if (eventmgr->pp_eventmgr_fini != NULL)
--			eventmgr->pp_eventmgr_fini(eventmgr);
-+static int pp_late_init(void *handle)
-+{
-+	struct pp_instance *pp_handle = (struct pp_instance *)handle;
-+	int ret = 0;
-+
-+	ret = pp_check(pp_handle);
-+	if (ret == 0)
-+		pp_dpm_dispatch_tasks(pp_handle,
-+					AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
- 
--		hwmgr_hw_fini(pp_handle);
--	}
- 	return 0;
- }
- 
-+static void pp_late_fini(void *handle)
-+{
-+	amd_powerplay_destroy(handle);
-+}
-+
-+
- static bool pp_is_idle(void *handle)
- {
- 	return false;
-@@ -196,28 +224,6 @@ static int pp_sw_reset(void *handle)
- 	return 0;
- }
- 
--
--int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id)
--{
--	struct pp_hwmgr  *hwmgr;
--	struct pp_instance *pp_handle = (struct pp_instance *)handle;
--	int ret = 0;
--
--	ret = pp_check(pp_handle);
--
--	if (ret != 0)
--		return ret;
--
--	hwmgr = pp_handle->hwmgr;
--
--	if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
--		pr_info("%s was not implemented.\n", __func__);
--		return 0;
--	}
--
--	return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
--}
--
- static int pp_set_powergating_state(void *handle,
- 				    enum amd_powergating_state state)
- {
-@@ -227,7 +233,7 @@ static int pp_set_powergating_state(void
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -244,67 +250,52 @@ static int pp_set_powergating_state(void
- 
- static int pp_suspend(void *handle)
- {
--	struct pp_eventmgr *eventmgr;
--	struct pem_event_data event_data = { {0} };
- 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
- 	int ret = 0;
- 
- 	ret = pp_check(pp_handle);
--
--	if (ret == PP_DPM_DISABLED)
--		return 0;
--	else if (ret != 0)
--		return ret;
--
--	eventmgr = pp_handle->eventmgr;
--	pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data);
--
-+	if (ret == 0)
-+		hwmgr_hw_suspend(pp_handle);
- 	return 0;
- }
- 
- static int pp_resume(void *handle)
- {
--	struct pp_eventmgr *eventmgr;
--	struct pem_event_data event_data = { {0} };
--	struct pp_smumgr *smumgr;
--	int ret, ret1;
-+	struct pp_hwmgr  *hwmgr;
-+	int ret;
- 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
- 
--	ret1 = pp_check(pp_handle);
-+	ret = pp_check(pp_handle);
- 
--	if (ret1 != 0 && ret1 != PP_DPM_DISABLED)
--		return ret1;
-+	if (ret < 0)
-+		return ret;
- 
--	smumgr = pp_handle->smu_mgr;
-+	hwmgr = pp_handle->hwmgr;
- 
--	if (smumgr->smumgr_funcs->start_smu == NULL)
-+	if (hwmgr->smumgr_funcs->start_smu == NULL)
- 		return -EINVAL;
- 
--	ret = smumgr->smumgr_funcs->start_smu(smumgr);
--	if (ret) {
-+	if (hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
- 		pr_err("smc start failed\n");
--		smumgr->smumgr_funcs->smu_fini(smumgr);
--		return ret;
-+		hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
-+		return -EINVAL;
- 	}
- 
--	if (ret1 == PP_DPM_DISABLED)
-+	if (ret == PP_DPM_DISABLED)
- 		return 0;
- 
--	eventmgr = pp_handle->eventmgr;
--
--	pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);
--
--	return 0;
-+	return hwmgr_hw_resume(pp_handle);
- }
- 
- const struct amd_ip_funcs pp_ip_funcs = {
- 	.name = "powerplay",
- 	.early_init = pp_early_init,
--	.late_init = NULL,
-+	.late_init = pp_late_init,
- 	.sw_init = pp_sw_init,
- 	.sw_fini = pp_sw_fini,
- 	.hw_init = pp_hw_init,
- 	.hw_fini = pp_hw_fini,
-+	.late_fini = pp_late_fini,
- 	.suspend = pp_suspend,
- 	.resume = pp_resume,
- 	.is_idle = pp_is_idle,
-@@ -324,6 +315,63 @@ static int pp_dpm_fw_loading_complete(vo
- 	return 0;
- }
- 
-+static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
-+{
-+	struct pp_hwmgr  *hwmgr;
-+	struct pp_instance *pp_handle = (struct pp_instance *)handle;
-+	int ret = 0;
-+
-+	ret = pp_check(pp_handle);
-+
-+	if (ret)
-+		return ret;
-+
-+	hwmgr = pp_handle->hwmgr;
-+
-+	if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
-+		pr_info("%s was not implemented.\n", __func__);
-+		return 0;
-+	}
-+
-+	return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
-+}
-+
-+static void pp_dpm_en_umd_pstate(struct pp_hwmgr  *hwmgr,
-+						enum amd_dpm_forced_level *level)
-+{
-+	uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
-+					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
-+					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
-+					AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
-+
-+	if (!(hwmgr->dpm_level & profile_mode_mask)) {
-+		/* enter umd pstate, save current level, disable gfx cg*/
-+		if (*level & profile_mode_mask) {
-+			hwmgr->saved_dpm_level = hwmgr->dpm_level;
-+			hwmgr->en_umd_pstate = true;
-+			cgs_set_clockgating_state(hwmgr->device,
-+						AMD_IP_BLOCK_TYPE_GFX,
-+						AMD_CG_STATE_UNGATE);
-+			cgs_set_powergating_state(hwmgr->device,
-+					AMD_IP_BLOCK_TYPE_GFX,
-+					AMD_PG_STATE_UNGATE);
-+		}
-+	} else {
-+		/* exit umd pstate, restore level, enable gfx cg*/
-+		if (!(*level & profile_mode_mask)) {
-+			if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
-+				*level = hwmgr->saved_dpm_level;
-+			hwmgr->en_umd_pstate = false;
-+			cgs_set_clockgating_state(hwmgr->device,
-+					AMD_IP_BLOCK_TYPE_GFX,
-+					AMD_CG_STATE_GATE);
-+			cgs_set_powergating_state(hwmgr->device,
-+					AMD_IP_BLOCK_TYPE_GFX,
-+					AMD_PG_STATE_GATE);
-+		}
-+	}
-+}
-+
- static int pp_dpm_force_performance_level(void *handle,
- 					enum amd_dpm_forced_level level)
- {
-@@ -333,18 +381,27 @@ static int pp_dpm_force_performance_leve
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
- 
-+	if (level == hwmgr->dpm_level)
-+		return 0;
-+
- 	if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
- 		pr_info("%s was not implemented.\n", __func__);
- 		return 0;
- 	}
- 
- 	mutex_lock(&pp_handle->pp_lock);
--	hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
-+	pp_dpm_en_umd_pstate(hwmgr, &level);
-+	hwmgr->request_dpm_level = level;
-+	hwmgr_handle_task(pp_handle, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
-+	ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
-+	if (!ret)
-+		hwmgr->dpm_level = hwmgr->request_dpm_level;
-+
- 	mutex_unlock(&pp_handle->pp_lock);
- 	return 0;
- }
-@@ -359,7 +416,7 @@ static enum amd_dpm_forced_level pp_dpm_
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -369,15 +426,16 @@ static enum amd_dpm_forced_level pp_dpm_
- 	return level;
- }
- 
--static int pp_dpm_get_sclk(void *handle, bool low)
-+static uint32_t pp_dpm_get_sclk(void *handle, bool low)
- {
- 	struct pp_hwmgr  *hwmgr;
- 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
- 	int ret = 0;
-+	uint32_t clk = 0;
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -387,20 +445,21 @@ static int pp_dpm_get_sclk(void *handle,
- 		return 0;
- 	}
- 	mutex_lock(&pp_handle->pp_lock);
--	ret = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
-+	clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
- 	mutex_unlock(&pp_handle->pp_lock);
--	return ret;
-+	return clk;
- }
- 
--static int pp_dpm_get_mclk(void *handle, bool low)
-+static uint32_t pp_dpm_get_mclk(void *handle, bool low)
- {
- 	struct pp_hwmgr  *hwmgr;
- 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
- 	int ret = 0;
-+	uint32_t clk = 0;
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -410,12 +469,12 @@ static int pp_dpm_get_mclk(void *handle,
- 		return 0;
- 	}
- 	mutex_lock(&pp_handle->pp_lock);
--	ret = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
-+	clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
- 	mutex_unlock(&pp_handle->pp_lock);
--	return ret;
-+	return clk;
- }
- 
--static int pp_dpm_powergate_vce(void *handle, bool gate)
-+static void pp_dpm_powergate_vce(void *handle, bool gate)
- {
- 	struct pp_hwmgr  *hwmgr;
- 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
-@@ -423,22 +482,21 @@ static int pp_dpm_powergate_vce(void *ha
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
--		return ret;
-+	if (ret)
-+		return;
- 
- 	hwmgr = pp_handle->hwmgr;
- 
- 	if (hwmgr->hwmgr_func->powergate_vce == NULL) {
- 		pr_info("%s was not implemented.\n", __func__);
--		return 0;
-+		return;
- 	}
- 	mutex_lock(&pp_handle->pp_lock);
--	ret = hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
-+	hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
- 	mutex_unlock(&pp_handle->pp_lock);
--	return ret;
- }
- 
--static int pp_dpm_powergate_uvd(void *handle, bool gate)
-+static void pp_dpm_powergate_uvd(void *handle, bool gate)
- {
- 	struct pp_hwmgr  *hwmgr;
- 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
-@@ -446,75 +504,35 @@ static int pp_dpm_powergate_uvd(void *ha
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
--		return ret;
-+	if (ret)
-+		return;
- 
- 	hwmgr = pp_handle->hwmgr;
- 
- 	if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
- 		pr_info("%s was not implemented.\n", __func__);
--		return 0;
-+		return;
- 	}
- 	mutex_lock(&pp_handle->pp_lock);
--	ret = hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
-+	hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
- 	mutex_unlock(&pp_handle->pp_lock);
--	return ret;
- }
- 
--static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
--{
--	switch (state) {
--	case POWER_STATE_TYPE_BATTERY:
--		return PP_StateUILabel_Battery;
--	case POWER_STATE_TYPE_BALANCED:
--		return PP_StateUILabel_Balanced;
--	case POWER_STATE_TYPE_PERFORMANCE:
--		return PP_StateUILabel_Performance;
--	default:
--		return PP_StateUILabel_None;
--	}
--}
--
--static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id,
-+static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
- 		void *input, void *output)
- {
- 	int ret = 0;
--	struct pem_event_data data = { {0} };
- 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
--	mutex_lock(&pp_handle->pp_lock);
--	switch (event_id) {
--	case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
--		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
--		break;
--	case AMD_PP_EVENT_ENABLE_USER_STATE:
--	{
--		enum amd_pm_state_type  ps;
- 
--		if (input == NULL) {
--			ret = -EINVAL;
--			break;
--		}
--		ps = *(unsigned long *)input;
--
--		data.requested_ui_label = power_state_convert(ps);
--		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
--		break;
--	}
--	case AMD_PP_EVENT_COMPLETE_INIT:
--		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
--		break;
--	case AMD_PP_EVENT_READJUST_POWER_STATE:
--		ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
--		break;
--	default:
--		break;
--	}
-+	mutex_lock(&pp_handle->pp_lock);
-+	ret = hwmgr_handle_task(pp_handle, task_id, input, output);
- 	mutex_unlock(&pp_handle->pp_lock);
-+
- 	return ret;
- }
- 
-@@ -528,7 +546,7 @@ static enum amd_pm_state_type pp_dpm_get
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -562,7 +580,7 @@ static enum amd_pm_state_type pp_dpm_get
- 	return pm_type;
- }
- 
--static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
-+static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
- {
- 	struct pp_hwmgr  *hwmgr;
- 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
-@@ -570,30 +588,30 @@ static int pp_dpm_set_fan_control_mode(v
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
--		return ret;
-+	if (ret)
-+		return;
- 
- 	hwmgr = pp_handle->hwmgr;
- 
- 	if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
- 		pr_info("%s was not implemented.\n", __func__);
--		return 0;
-+		return;
- 	}
- 	mutex_lock(&pp_handle->pp_lock);
--	ret = hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
-+	hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
- 	mutex_unlock(&pp_handle->pp_lock);
--	return ret;
- }
- 
--static int pp_dpm_get_fan_control_mode(void *handle)
-+static uint32_t pp_dpm_get_fan_control_mode(void *handle)
- {
- 	struct pp_hwmgr  *hwmgr;
- 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
- 	int ret = 0;
-+	uint32_t mode = 0;
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -603,9 +621,9 @@ static int pp_dpm_get_fan_control_mode(v
- 		return 0;
- 	}
- 	mutex_lock(&pp_handle->pp_lock);
--	ret = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
-+	mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
- 	mutex_unlock(&pp_handle->pp_lock);
--	return ret;
-+	return mode;
- }
- 
- static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
-@@ -616,7 +634,7 @@ static int pp_dpm_set_fan_speed_percent(
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -639,7 +657,7 @@ static int pp_dpm_get_fan_speed_percent(
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -663,7 +681,7 @@ static int pp_dpm_get_fan_speed_rpm(void
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -685,7 +703,7 @@ static int pp_dpm_get_temperature(void *
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -710,7 +728,7 @@ static int pp_dpm_get_pp_num_states(void
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -755,7 +773,7 @@ static int pp_dpm_get_pp_table(void *han
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -770,6 +788,26 @@ static int pp_dpm_get_pp_table(void *han
- 	return size;
- }
- 
-+static int amd_powerplay_reset(void *handle)
-+{
-+	struct pp_instance *instance = (struct pp_instance *)handle;
-+	int ret;
-+
-+	ret = pp_check(instance);
-+	if (ret)
-+		return ret;
-+
-+	ret = pp_hw_fini(instance);
-+	if (ret)
-+		return ret;
-+
-+	ret = hwmgr_hw_init(instance);
-+	if (ret)
-+		return ret;
-+
-+	return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
-+}
-+
- static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
- {
- 	struct pp_hwmgr *hwmgr;
-@@ -778,7 +816,7 @@ static int pp_dpm_set_pp_table(void *han
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -820,7 +858,7 @@ static int pp_dpm_force_clock_level(void
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -844,7 +882,7 @@ static int pp_dpm_print_clock_levels(voi
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -867,7 +905,7 @@ static int pp_dpm_get_sclk_od(void *hand
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -890,7 +928,7 @@ static int pp_dpm_set_sclk_od(void *hand
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -914,7 +952,7 @@ static int pp_dpm_get_mclk_od(void *hand
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -937,7 +975,7 @@ static int pp_dpm_set_mclk_od(void *hand
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -961,7 +999,7 @@ static int pp_dpm_read_sensor(void *hand
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -987,7 +1025,7 @@ pp_dpm_get_vce_clock_state(void *handle,
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return NULL;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -1128,118 +1166,41 @@ static int pp_dpm_switch_power_profile(v
- 	return 0;
- }
- 
--const struct amd_powerplay_funcs pp_dpm_funcs = {
--	.get_temperature = pp_dpm_get_temperature,
--	.load_firmware = pp_dpm_load_fw,
--	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
--	.force_performance_level = pp_dpm_force_performance_level,
--	.get_performance_level = pp_dpm_get_performance_level,
--	.get_current_power_state = pp_dpm_get_current_power_state,
--	.get_sclk = pp_dpm_get_sclk,
--	.get_mclk = pp_dpm_get_mclk,
--	.powergate_vce = pp_dpm_powergate_vce,
--	.powergate_uvd = pp_dpm_powergate_uvd,
--	.dispatch_tasks = pp_dpm_dispatch_tasks,
--	.set_fan_control_mode = pp_dpm_set_fan_control_mode,
--	.get_fan_control_mode = pp_dpm_get_fan_control_mode,
--	.set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
--	.get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
--	.get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
--	.get_pp_num_states = pp_dpm_get_pp_num_states,
--	.get_pp_table = pp_dpm_get_pp_table,
--	.set_pp_table = pp_dpm_set_pp_table,
--	.force_clock_level = pp_dpm_force_clock_level,
--	.print_clock_levels = pp_dpm_print_clock_levels,
--	.get_sclk_od = pp_dpm_get_sclk_od,
--	.set_sclk_od = pp_dpm_set_sclk_od,
--	.get_mclk_od = pp_dpm_get_mclk_od,
--	.set_mclk_od = pp_dpm_set_mclk_od,
--	.read_sensor = pp_dpm_read_sensor,
--	.get_vce_clock_state = pp_dpm_get_vce_clock_state,
--	.reset_power_profile_state = pp_dpm_reset_power_profile_state,
--	.get_power_profile_state = pp_dpm_get_power_profile_state,
--	.set_power_profile_state = pp_dpm_set_power_profile_state,
--	.switch_power_profile = pp_dpm_switch_power_profile,
--};
--
--int amd_powerplay_create(struct amd_pp_init *pp_init,
--				void **handle)
-+static int pp_dpm_notify_smu_memory_info(void *handle,
-+					uint32_t virtual_addr_low,
-+					uint32_t virtual_addr_hi,
-+					uint32_t mc_addr_low,
-+					uint32_t mc_addr_hi,
-+					uint32_t size)
- {
--	struct pp_instance *instance;
--
--	if (pp_init == NULL || handle == NULL)
--		return -EINVAL;
--
--	instance = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
--	if (instance == NULL)
--		return -ENOMEM;
--
--	instance->pp_valid = PP_VALID;
--	instance->chip_family = pp_init->chip_family;
--	instance->chip_id = pp_init->chip_id;
--	instance->pm_en = pp_init->pm_en;
--	instance->feature_mask = pp_init->feature_mask;
--	instance->device = pp_init->device;
--	mutex_init(&instance->pp_lock);
--	*handle = instance;
--	return 0;
--}
--
--int amd_powerplay_destroy(void *handle)
--{
--	struct pp_instance *instance = (struct pp_instance *)handle;
--
--	if (instance->pm_en) {
--		kfree(instance->eventmgr);
--		kfree(instance->hwmgr);
--		instance->hwmgr = NULL;
--		instance->eventmgr = NULL;
--	}
--
--	kfree(instance->smu_mgr);
--	instance->smu_mgr = NULL;
--	kfree(instance);
--	instance = NULL;
--	return 0;
--}
--
--int amd_powerplay_reset(void *handle)
--{
--	struct pp_instance *instance = (struct pp_instance *)handle;
--	struct pp_eventmgr *eventmgr;
--	struct pem_event_data event_data = { {0} };
--	int ret;
--
--	if (cgs_is_virtualization_enabled(instance->smu_mgr->device))
--		return PP_DPM_DISABLED;
-+	struct pp_hwmgr  *hwmgr;
-+	struct pp_instance *pp_handle = (struct pp_instance *)handle;
-+	int ret = 0;
- 
--	ret = pp_check(instance);
--	if (ret != 0)
--		return ret;
-+	ret = pp_check(pp_handle);
- 
--	ret = pp_hw_fini(handle);
- 	if (ret)
- 		return ret;
- 
--	ret = hwmgr_hw_init(instance);
--	if (ret)
--		return PP_DPM_DISABLED;
-+	hwmgr = pp_handle->hwmgr;
- 
--	eventmgr = instance->eventmgr;
-+	if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
-+		pr_info("%s was not implemented.\n", __func__);
-+		return -EINVAL;
-+	}
- 
--	if (eventmgr->pp_eventmgr_init == NULL)
--		return PP_DPM_DISABLED;
-+	mutex_lock(&pp_handle->pp_lock);
- 
--	ret = eventmgr->pp_eventmgr_init(eventmgr);
--	if (ret)
--		return ret;
-+	ret = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, virtual_addr_low,
-+					virtual_addr_hi, mc_addr_low, mc_addr_hi,
-+					size);
- 
--	return pem_handle_event(eventmgr, AMD_PP_EVENT_COMPLETE_INIT, &event_data);
--}
-+	mutex_unlock(&pp_handle->pp_lock);
- 
--/* export this function to DAL */
-+	return ret;
-+}
- 
--int amd_powerplay_display_configuration_change(void *handle,
-+static int pp_display_configuration_change(void *handle,
- 	const struct amd_pp_display_configuration *display_config)
- {
- 	struct pp_hwmgr  *hwmgr;
-@@ -1248,7 +1209,7 @@ int amd_powerplay_display_configuration_
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -1258,7 +1219,7 @@ int amd_powerplay_display_configuration_
- 	return 0;
- }
- 
--int amd_powerplay_get_display_power_level(void *handle,
-+static int pp_get_display_power_level(void *handle,
- 		struct amd_pp_simple_clock_info *output)
- {
- 	struct pp_hwmgr  *hwmgr;
-@@ -1267,7 +1228,7 @@ int amd_powerplay_get_display_power_leve
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -1281,7 +1242,7 @@ int amd_powerplay_get_display_power_leve
- 	return ret;
- }
- 
--int amd_powerplay_get_current_clocks(void *handle,
-+static int pp_get_current_clocks(void *handle,
- 		struct amd_pp_clock_info *clocks)
- {
- 	struct amd_pp_simple_clock_info simple_clocks;
-@@ -1292,7 +1253,7 @@ int amd_powerplay_get_current_clocks(voi
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -1309,7 +1270,7 @@ int amd_powerplay_get_current_clocks(voi
- 		ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
- 					&hw_clocks, PHM_PerformanceLevelDesignation_Activity);
- 
--	if (ret != 0) {
-+	if (ret) {
- 		pr_info("Error in phm_get_clock_info \n");
- 		mutex_unlock(&pp_handle->pp_lock);
- 		return -EINVAL;
-@@ -1335,7 +1296,7 @@ int amd_powerplay_get_current_clocks(voi
- 	return 0;
- }
- 
--int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
-+static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
- {
- 	struct pp_hwmgr  *hwmgr;
- 	struct pp_instance *pp_handle = (struct pp_instance *)handle;
-@@ -1343,7 +1304,7 @@ int amd_powerplay_get_clock_by_type(void
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -1357,7 +1318,7 @@ int amd_powerplay_get_clock_by_type(void
- 	return ret;
- }
- 
--int amd_powerplay_get_clock_by_type_with_latency(void *handle,
-+static int pp_get_clock_by_type_with_latency(void *handle,
- 		enum amd_pp_clock_type type,
- 		struct pp_clock_levels_with_latency *clocks)
- {
-@@ -1366,7 +1327,7 @@ int amd_powerplay_get_clock_by_type_with
- 	int ret = 0;
- 
- 	ret = pp_check(pp_handle);
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	if (!clocks)
-@@ -1379,7 +1340,7 @@ int amd_powerplay_get_clock_by_type_with
- 	return ret;
- }
- 
--int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
-+static int pp_get_clock_by_type_with_voltage(void *handle,
- 		enum amd_pp_clock_type type,
- 		struct pp_clock_levels_with_voltage *clocks)
- {
-@@ -1388,7 +1349,7 @@ int amd_powerplay_get_clock_by_type_with
- 	int ret = 0;
- 
- 	ret = pp_check(pp_handle);
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	if (!clocks)
-@@ -1404,7 +1365,7 @@ int amd_powerplay_get_clock_by_type_with
- 	return ret;
- }
- 
--int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
-+static int pp_set_watermarks_for_clocks_ranges(void *handle,
- 		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
- {
- 	struct pp_hwmgr *hwmgr;
-@@ -1412,7 +1373,7 @@ int amd_powerplay_set_watermarks_for_clo
- 	int ret = 0;
- 
- 	ret = pp_check(pp_handle);
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	if (!wm_with_clock_ranges)
-@@ -1428,7 +1389,7 @@ int amd_powerplay_set_watermarks_for_clo
- 	return ret;
- }
- 
--int amd_powerplay_display_clock_voltage_request(void *handle,
-+static int pp_display_clock_voltage_request(void *handle,
- 		struct pp_display_clock_request *clock)
- {
- 	struct pp_hwmgr *hwmgr;
-@@ -1436,7 +1397,7 @@ int amd_powerplay_display_clock_voltage_
- 	int ret = 0;
- 
- 	ret = pp_check(pp_handle);
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	if (!clock)
-@@ -1451,7 +1412,7 @@ int amd_powerplay_display_clock_voltage_
- 	return ret;
- }
- 
--int amd_powerplay_get_display_mode_validation_clocks(void *handle,
-+static int pp_get_display_mode_validation_clocks(void *handle,
- 		struct amd_pp_simple_clock_info *clocks)
- {
- 	struct pp_hwmgr  *hwmgr;
-@@ -1460,7 +1421,7 @@ int amd_powerplay_get_display_mode_valid
- 
- 	ret = pp_check(pp_handle);
- 
--	if (ret != 0)
-+	if (ret)
- 		return ret;
- 
- 	hwmgr = pp_handle->hwmgr;
-@@ -1477,3 +1438,48 @@ int amd_powerplay_get_display_mode_valid
- 	return ret;
- }
- 
-+const struct amd_pm_funcs pp_dpm_funcs = {
-+	.get_temperature = pp_dpm_get_temperature,
-+	.load_firmware = pp_dpm_load_fw,
-+	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
-+	.force_performance_level = pp_dpm_force_performance_level,
-+	.get_performance_level = pp_dpm_get_performance_level,
-+	.get_current_power_state = pp_dpm_get_current_power_state,
-+	.powergate_vce = pp_dpm_powergate_vce,
-+	.powergate_uvd = pp_dpm_powergate_uvd,
-+	.dispatch_tasks = pp_dpm_dispatch_tasks,
-+	.set_fan_control_mode = pp_dpm_set_fan_control_mode,
-+	.get_fan_control_mode = pp_dpm_get_fan_control_mode,
-+	.set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
-+	.get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
-+	.get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
-+	.get_pp_num_states = pp_dpm_get_pp_num_states,
-+	.get_pp_table = pp_dpm_get_pp_table,
-+	.set_pp_table = pp_dpm_set_pp_table,
-+	.force_clock_level = pp_dpm_force_clock_level,
-+	.print_clock_levels = pp_dpm_print_clock_levels,
-+	.get_sclk_od = pp_dpm_get_sclk_od,
-+	.set_sclk_od = pp_dpm_set_sclk_od,
-+	.get_mclk_od = pp_dpm_get_mclk_od,
-+	.set_mclk_od = pp_dpm_set_mclk_od,
-+	.read_sensor = pp_dpm_read_sensor,
-+	.get_vce_clock_state = pp_dpm_get_vce_clock_state,
-+	.reset_power_profile_state = pp_dpm_reset_power_profile_state,
-+	.get_power_profile_state = pp_dpm_get_power_profile_state,
-+	.set_power_profile_state = pp_dpm_set_power_profile_state,
-+	.switch_power_profile = pp_dpm_switch_power_profile,
-+	.set_clockgating_by_smu = pp_set_clockgating_by_smu,
-+	.notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
-+/* export to DC */
-+	.get_sclk = pp_dpm_get_sclk,
-+	.get_mclk = pp_dpm_get_mclk,
-+	.display_configuration_change = pp_display_configuration_change,
-+	.get_display_power_level = pp_get_display_power_level,
-+	.get_current_clocks = pp_get_current_clocks,
-+	.get_clock_by_type = pp_get_clock_by_type,
-+	.get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency,
-+	.get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage,
-+	.set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
-+	.display_clock_voltage_request = pp_display_clock_voltage_request,
-+	.get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
-+};
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c	2017-12-14 06:39:58.468903604 +0100
-@@ -103,16 +103,6 @@ int cz_phm_ungate_all_display_phys(struc
- 	return 0;
- }
- 
--static int cz_tf_uvd_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result)
--{
--	return 0;
--}
--
--static int cz_tf_vce_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result)
--{
--	return 0;
--}
--
- int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-@@ -123,12 +113,12 @@ int cz_enable_disable_uvd_dpm(struct pp_
- 				  PHM_PlatformCaps_UVDDPM)) {
- 		cz_hwmgr->dpm_flags |= DPMFlags_UVD_Enabled;
- 		dpm_features |= UVD_DPM_MASK;
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 			    PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
- 	} else {
- 		dpm_features |= UVD_DPM_MASK;
- 		cz_hwmgr->dpm_flags &= ~DPMFlags_UVD_Enabled;
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 			   PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
- 	}
- 	return 0;
-@@ -144,12 +134,12 @@ int cz_enable_disable_vce_dpm(struct pp_
- 				PHM_PlatformCaps_VCEDPM)) {
- 		cz_hwmgr->dpm_flags |= DPMFlags_VCE_Enabled;
- 		dpm_features |= VCE_DPM_MASK;
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 			    PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
- 	} else {
- 		dpm_features |= VCE_DPM_MASK;
- 		cz_hwmgr->dpm_flags &= ~DPMFlags_VCE_Enabled;
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 			   PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
- 	}
- 
-@@ -157,7 +147,7 @@ int cz_enable_disable_vce_dpm(struct pp_
- }
- 
- 
--int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
-+void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 
-@@ -183,10 +173,9 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr
- 		cz_dpm_update_uvd_dpm(hwmgr, false);
- 	}
- 
--	return 0;
- }
- 
--int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
-+void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 
-@@ -215,29 +204,6 @@ int cz_dpm_powergate_vce(struct pp_hwmgr
- 					AMD_CG_STATE_UNGATE);
- 		cz_dpm_update_vce_dpm(hwmgr);
- 		cz_enable_disable_vce_dpm(hwmgr, true);
--		return 0;
- 	}
--
--	return 0;
- }
- 
--
--static const struct phm_master_table_item cz_enable_clock_power_gatings_list[] = {
--	/*we don't need an exit table here, because there is only D3 cold on Kv*/
--	{
--	  .isFunctionNeededInRuntimeTable = phm_cf_want_uvd_power_gating,
--	  .tableFunction = cz_tf_uvd_power_gating_initialize
--	},
--	{
--	  .isFunctionNeededInRuntimeTable = phm_cf_want_vce_power_gating,
--	  .tableFunction = cz_tf_vce_power_gating_initialize
--	},
--	/* to do { NULL, cz_tf_xdma_power_gating_enable }, */
--	{ }
--};
--
--const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	cz_enable_clock_power_gatings_list
--};
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.h	2017-12-14 06:39:58.468903604 +0100
-@@ -29,8 +29,8 @@
- 
- extern int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating);
- extern const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master;
--extern int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
--extern int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
-+extern void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
-+extern void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
- extern int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
- extern int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable);
- #endif /* _CZ_CLOCK_POWER_GATING_H_ */
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c	2017-12-14 06:39:58.468903604 +0100
-@@ -162,8 +162,8 @@ static uint32_t cz_get_max_sclk_level(st
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 
- 	if (cz_hwmgr->max_sclk_level == 0) {
--		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel);
--		cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1;
-+		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxSclkLevel);
-+		cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr) + 1;
- 	}
- 
- 	return cz_hwmgr->max_sclk_level;
-@@ -440,14 +440,7 @@ static int cz_construct_boot_state(struc
- 	return 0;
- }
- 
--static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
--					void *output, void *storage, int result)
--{
--	return 0;
--}
--
--static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
--				       void *output, void *storage, int result)
-+static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
- {
- 	struct SMU8_Fusion_ClkTable *clock_table;
- 	int ret;
-@@ -469,7 +462,7 @@ static int cz_tf_upload_pptable_to_smu(s
- 	if (!hwmgr->need_pp_table_upload)
- 		return 0;
- 
--	ret = smum_download_powerplay_table(hwmgr->smumgr, &table);
-+	ret = smum_download_powerplay_table(hwmgr, &table);
- 
- 	PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
- 			    "Fail to get clock table from SMU!", return -EINVAL;);
-@@ -561,13 +554,12 @@ static int cz_tf_upload_pptable_to_smu(s
- 			(uint8_t)dividers.pll_post_divider;
- 
- 	}
--	ret = smum_upload_powerplay_table(hwmgr->smumgr);
-+	ret = smum_upload_powerplay_table(hwmgr);
- 
- 	return ret;
- }
- 
--static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
--				 void *output, void *storage, int result)
-+static int cz_init_sclk_limit(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 	struct phm_clock_voltage_dependency_table *table =
-@@ -593,8 +585,7 @@ static int cz_tf_init_sclk_limit(struct
- 	return 0;
- }
- 
--static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
--				void *output, void *storage, int result)
-+static int cz_init_uvd_limit(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 	struct phm_uvd_clock_voltage_dependency_table *table =
-@@ -607,8 +598,8 @@ static int cz_tf_init_uvd_limit(struct p
- 	cz_hwmgr->uvd_dpm.soft_min_clk = 0;
- 	cz_hwmgr->uvd_dpm.hard_min_clk = 0;
- 
--	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel);
--	level = smum_get_argument(hwmgr->smumgr);
-+	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel);
-+	level = smum_get_argument(hwmgr);
- 
- 	if (level < table->count)
- 		clock = table->entries[level].vclk;
-@@ -621,8 +612,7 @@ static int cz_tf_init_uvd_limit(struct p
- 	return 0;
- }
- 
--static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
--				void *output, void *storage, int result)
-+static int cz_init_vce_limit(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 	struct phm_vce_clock_voltage_dependency_table *table =
-@@ -635,8 +625,8 @@ static int cz_tf_init_vce_limit(struct p
- 	cz_hwmgr->vce_dpm.soft_min_clk = 0;
- 	cz_hwmgr->vce_dpm.hard_min_clk = 0;
- 
--	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel);
--	level = smum_get_argument(hwmgr->smumgr);
-+	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel);
-+	level = smum_get_argument(hwmgr);
- 
- 	if (level < table->count)
- 		clock = table->entries[level].ecclk;
-@@ -649,8 +639,7 @@ static int cz_tf_init_vce_limit(struct p
- 	return 0;
- }
- 
--static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
--				void *output, void *storage, int result)
-+static int cz_init_acp_limit(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 	struct phm_acp_clock_voltage_dependency_table *table =
-@@ -663,8 +652,8 @@ static int cz_tf_init_acp_limit(struct p
- 	cz_hwmgr->acp_dpm.soft_min_clk = 0;
- 	cz_hwmgr->acp_dpm.hard_min_clk = 0;
- 
--	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel);
--	level = smum_get_argument(hwmgr->smumgr);
-+	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel);
-+	level = smum_get_argument(hwmgr);
- 
- 	if (level < table->count)
- 		clock = table->entries[level].acpclk;
-@@ -676,8 +665,7 @@ static int cz_tf_init_acp_limit(struct p
- 	return 0;
- }
- 
--static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
--				void *output, void *storage, int result)
-+static void cz_init_power_gate_state(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 
-@@ -686,22 +674,16 @@ static int cz_tf_init_power_gate_state(s
- 	cz_hwmgr->samu_power_gated = false;
- 	cz_hwmgr->acp_power_gated = false;
- 	cz_hwmgr->pgacpinit = true;
--
--	return 0;
- }
- 
--static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
--				void *output, void *storage, int result)
-+static void cz_init_sclk_threshold(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 
- 	cz_hwmgr->low_sclk_interrupt_threshold = 0;
--
--	return 0;
- }
--static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
--					void *input, void *output,
--					void *storage, int result)
-+
-+static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 	struct phm_clock_voltage_dependency_table *table =
-@@ -722,12 +704,12 @@ static int cz_tf_update_sclk_limit(struc
- 
- 	clock = hwmgr->display_config.min_core_set_clock;
- 	if (clock == 0)
--		pr_info("min_core_set_clock not set\n");
-+		pr_debug("min_core_set_clock not set\n");
- 
- 	if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
- 		cz_hwmgr->sclk_dpm.hard_min_clk = clock;
- 
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 						PPSMC_MSG_SetSclkHardMin,
- 						 cz_get_sclk_level(hwmgr,
- 					cz_hwmgr->sclk_dpm.hard_min_clk,
-@@ -753,7 +735,7 @@ static int cz_tf_update_sclk_limit(struc
- 
- 	if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
- 		cz_hwmgr->sclk_dpm.soft_min_clk = clock;
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 						PPSMC_MSG_SetSclkSoftMin,
- 						cz_get_sclk_level(hwmgr,
- 					cz_hwmgr->sclk_dpm.soft_min_clk,
-@@ -764,7 +746,7 @@ static int cz_tf_update_sclk_limit(struc
- 				    PHM_PlatformCaps_StablePState) &&
- 			 cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
- 		cz_hwmgr->sclk_dpm.soft_max_clk = clock;
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 						PPSMC_MSG_SetSclkSoftMax,
- 						cz_get_sclk_level(hwmgr,
- 					cz_hwmgr->sclk_dpm.soft_max_clk,
-@@ -774,9 +756,7 @@ static int cz_tf_update_sclk_limit(struc
- 	return 0;
- }
- 
--static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
--					void *input, void *output,
--					void *storage, int result)
-+static int cz_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr)
- {
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 				PHM_PlatformCaps_SclkDeepSleep)) {
-@@ -786,7 +766,7 @@ static int cz_tf_set_deep_sleep_sclk_thr
- 
- 		PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
- 
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetMinDeepSleepSclk,
- 				clks);
- 	}
-@@ -794,77 +774,84 @@ static int cz_tf_set_deep_sleep_sclk_thr
- 	return 0;
- }
- 
--static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
--					void *input, void *output,
--					void *storage, int result)
-+static int cz_set_watermark_threshold(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *cz_hwmgr =
- 				  (struct cz_hwmgr *)(hwmgr->backend);
- 
--	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_SetWatermarkFrequency,
- 					cz_hwmgr->sclk_dpm.soft_max_clk);
- 
- 	return 0;
- }
- 
--static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
--					void *input, void *output,
--					void *storage, int result)
-+static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
- {
-+	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
-+
-+	if (hw_data->is_nb_dpm_enabled) {
-+		if (enable) {
-+			PP_DBG_LOG("enable Low Memory PState.\n");
-+
-+			return smum_send_msg_to_smc_with_parameter(hwmgr,
-+						PPSMC_MSG_EnableLowMemoryPstate,
-+						(lock ? 1 : 0));
-+		} else {
-+			PP_DBG_LOG("disable Low Memory PState.\n");
-+
-+			return smum_send_msg_to_smc_with_parameter(hwmgr,
-+						PPSMC_MSG_DisableLowMemoryPstate,
-+						(lock ? 1 : 0));
-+		}
-+	}
-+
- 	return 0;
- }
- 
--
--static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
--					void *input, void *output,
--					void *storage, int result)
-+static int cz_disable_nb_dpm(struct pp_hwmgr *hwmgr)
- {
- 	int ret = 0;
- 
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 	unsigned long dpm_features = 0;
- 
--	if (!cz_hwmgr->is_nb_dpm_enabled) {
--		PP_DBG_LOG("enabling ALL SMU features.\n");
-+	if (cz_hwmgr->is_nb_dpm_enabled) {
-+		cz_nbdpm_pstate_enable_disable(hwmgr, true, true);
- 		dpm_features |= NB_DPM_MASK;
- 		ret = smum_send_msg_to_smc_with_parameter(
--							  hwmgr->smumgr,
--							  PPSMC_MSG_EnableAllSmuFeatures,
-+							  hwmgr,
-+							  PPSMC_MSG_DisableAllSmuFeatures,
- 							  dpm_features);
- 		if (ret == 0)
--			cz_hwmgr->is_nb_dpm_enabled = true;
-+			cz_hwmgr->is_nb_dpm_enabled = false;
- 	}
- 
- 	return ret;
- }
- 
--static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
-+static int cz_enable_nb_dpm(struct pp_hwmgr *hwmgr)
- {
--	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
--
--	if (hw_data->is_nb_dpm_enabled) {
--		if (enable) {
--			PP_DBG_LOG("enable Low Memory PState.\n");
-+	int ret = 0;
- 
--			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--						PPSMC_MSG_EnableLowMemoryPstate,
--						(lock ? 1 : 0));
--		} else {
--			PP_DBG_LOG("disable Low Memory PState.\n");
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	unsigned long dpm_features = 0;
- 
--			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--						PPSMC_MSG_DisableLowMemoryPstate,
--						(lock ? 1 : 0));
--		}
-+	if (!cz_hwmgr->is_nb_dpm_enabled) {
-+		PP_DBG_LOG("enabling ALL SMU features.\n");
-+		dpm_features |= NB_DPM_MASK;
-+		ret = smum_send_msg_to_smc_with_parameter(
-+							  hwmgr,
-+							  PPSMC_MSG_EnableAllSmuFeatures,
-+							  dpm_features);
-+		if (ret == 0)
-+			cz_hwmgr->is_nb_dpm_enabled = true;
- 	}
- 
--	return 0;
-+	return ret;
- }
- 
--static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
--					void *input, void *output,
--					void *storage, int result)
-+static int cz_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input)
- {
- 	bool disable_switch;
- 	bool enable_low_mem_state;
-@@ -886,64 +873,64 @@ static int cz_tf_update_low_mem_pstate(s
- 	return 0;
- }
- 
--static const struct phm_master_table_item cz_set_power_state_list[] = {
--	{ .tableFunction = cz_tf_update_sclk_limit },
--	{ .tableFunction = cz_tf_set_deep_sleep_sclk_threshold },
--	{ .tableFunction = cz_tf_set_watermark_threshold },
--	{ .tableFunction = cz_tf_set_enabled_levels },
--	{ .tableFunction = cz_tf_enable_nb_dpm },
--	{ .tableFunction = cz_tf_update_low_mem_pstate },
--	{ }
--};
-+static int cz_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	int ret = 0;
- 
--static const struct phm_master_table_header cz_set_power_state_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	cz_set_power_state_list
--};
-+	cz_update_sclk_limit(hwmgr);
-+	cz_set_deep_sleep_sclk_threshold(hwmgr);
-+	cz_set_watermark_threshold(hwmgr);
-+	ret = cz_enable_nb_dpm(hwmgr);
-+	if (ret)
-+		return ret;
-+	cz_update_low_mem_pstate(hwmgr, input);
- 
--static const struct phm_master_table_item cz_setup_asic_list[] = {
--	{ .tableFunction = cz_tf_reset_active_process_mask },
--	{ .tableFunction = cz_tf_upload_pptable_to_smu },
--	{ .tableFunction = cz_tf_init_sclk_limit },
--	{ .tableFunction = cz_tf_init_uvd_limit },
--	{ .tableFunction = cz_tf_init_vce_limit },
--	{ .tableFunction = cz_tf_init_acp_limit },
--	{ .tableFunction = cz_tf_init_power_gate_state },
--	{ .tableFunction = cz_tf_init_sclk_threshold },
--	{ }
-+	return 0;
- };
- 
--static const struct phm_master_table_header cz_setup_asic_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	cz_setup_asic_list
--};
- 
--static int cz_tf_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr,
--					void *input, void *output,
--					void *storage, int result)
-+static int cz_setup_asic_task(struct pp_hwmgr *hwmgr)
-+{
-+	int ret;
-+
-+	ret = cz_upload_pptable_to_smu(hwmgr);
-+	if (ret)
-+		return ret;
-+	ret = cz_init_sclk_limit(hwmgr);
-+	if (ret)
-+		return ret;
-+	ret = cz_init_uvd_limit(hwmgr);
-+	if (ret)
-+		return ret;
-+	ret = cz_init_vce_limit(hwmgr);
-+	if (ret)
-+		return ret;
-+	ret = cz_init_acp_limit(hwmgr);
-+	if (ret)
-+		return ret;
-+
-+	cz_init_power_gate_state(hwmgr);
-+	cz_init_sclk_threshold(hwmgr);
-+
-+	return 0;
-+}
-+
-+static void cz_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
-+
- 	hw_data->disp_clk_bypass_pending = false;
- 	hw_data->disp_clk_bypass = false;
--
--	return 0;
- }
- 
--static int cz_tf_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr,
--					void *input, void *output,
--					void *storage, int result)
-+static void cz_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
--	hw_data->is_nb_dpm_enabled = false;
- 
--	return 0;
-+	hw_data->is_nb_dpm_enabled = false;
- }
- 
--static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
--					void *input, void *output,
--					void *storage, int result)
-+static void cz_reset_cc6_data(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
- 
-@@ -951,63 +938,68 @@ static int cz_tf_reset_cc6_data(struct p
- 	hw_data->cc6_settings.cpu_pstate_separation_time = 0;
- 	hw_data->cc6_settings.cpu_cc6_disable = false;
- 	hw_data->cc6_settings.cpu_pstate_disable = false;
--
--	return 0;
- }
- 
--static const struct phm_master_table_item cz_power_down_asic_list[] = {
--	{ .tableFunction = cz_tf_power_up_display_clock_sys_pll },
--	{ .tableFunction = cz_tf_clear_nb_dpm_flag },
--	{ .tableFunction = cz_tf_reset_cc6_data },
--	{ }
--};
--
--static const struct phm_master_table_header cz_power_down_asic_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	cz_power_down_asic_list
-+static int cz_power_off_asic(struct pp_hwmgr *hwmgr)
-+{
-+	cz_power_up_display_clock_sys_pll(hwmgr);
-+	cz_clear_nb_dpm_flag(hwmgr);
-+	cz_reset_cc6_data(hwmgr);
-+	return 0;
- };
- 
--static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
--				void *output, void *storage, int result)
-+static void cz_program_voting_clients(struct pp_hwmgr *hwmgr)
- {
- 	PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
- 				PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
--	return 0;
- }
- 
--static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output,
--			   void *storage, int result)
-+static void cz_clear_voting_clients(struct pp_hwmgr *hwmgr)
-+{
-+	PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0, 0);
-+}
-+
-+static int cz_start_dpm(struct pp_hwmgr *hwmgr)
- {
--	int res = 0xff;
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
--	unsigned long dpm_features = 0;
- 
- 	cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
--	dpm_features |= SCLK_DPM_MASK;
- 
--	res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	return smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_EnableAllSmuFeatures,
--				dpm_features);
-+				SCLK_DPM_MASK);
-+}
-+
-+static int cz_stop_dpm(struct pp_hwmgr *hwmgr)
-+{
-+	int ret = 0;
-+	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
-+	unsigned long dpm_features = 0;
- 
--	return res;
-+	if (cz_hwmgr->dpm_flags & DPMFlags_SCLK_Enabled) {
-+		dpm_features |= SCLK_DPM_MASK;
-+		cz_hwmgr->dpm_flags &= ~DPMFlags_SCLK_Enabled;
-+		ret = smum_send_msg_to_smc_with_parameter(hwmgr,
-+					PPSMC_MSG_DisableAllSmuFeatures,
-+					dpm_features);
-+	}
-+	return ret;
- }
- 
--static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
--				void *output, void *storage, int result)
-+static int cz_program_bootup_state(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 
- 	cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
- 	cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
- 
--	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetSclkSoftMin,
- 				cz_get_sclk_level(hwmgr,
- 				cz_hwmgr->sclk_dpm.soft_min_clk,
- 				PPSMC_MSG_SetSclkSoftMin));
- 
--	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetSclkSoftMax,
- 				cz_get_sclk_level(hwmgr,
- 				cz_hwmgr->sclk_dpm.soft_max_clk,
-@@ -1016,13 +1008,11 @@ static int cz_tf_program_bootup_state(st
- 	return 0;
- }
- 
--static int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
--				void *output, void *storage, int result)
-+static void cz_reset_acp_boot_level(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 
- 	cz_hwmgr->acp_boot_level = 0xff;
--	return 0;
- }
- 
- static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
-@@ -1031,67 +1021,52 @@ static bool cz_dpm_check_smu_features(st
- 	int result;
- 	unsigned long features;
- 
--	result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0);
-+	result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetFeatureStatus, 0);
- 	if (result == 0) {
--		features = smum_get_argument(hwmgr->smumgr);
-+		features = smum_get_argument(hwmgr);
- 		if (features & check_feature)
- 			return true;
- 	}
- 
--	return result;
-+	return false;
- }
- 
--static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input,
--				void *output, void *storage, int result)
-+static bool cz_check_for_dpm_enabled(struct pp_hwmgr *hwmgr)
- {
- 	if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
--		return PP_Result_TableImmediateExit;
--	return 0;
-+		return true;
-+	return false;
- }
- 
--static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input,
--				void *output, void *storage, int result)
-+static int cz_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
- {
--	/* TO DO */
--	return 0;
--}
-+	if (!cz_check_for_dpm_enabled(hwmgr)) {
-+		pr_info("dpm has been disabled\n");
-+		return 0;
-+	}
-+	cz_disable_nb_dpm(hwmgr);
- 
--static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
--						void *input, void *output,
--						void *storage, int result)
--{
--	if (!cz_dpm_check_smu_features(hwmgr,
--			     SMU_EnabledFeatureScoreboard_SclkDpmOn))
--		return PP_Result_TableImmediateExit;
--	return 0;
--}
-+	cz_clear_voting_clients(hwmgr);
-+	if (cz_stop_dpm(hwmgr))
-+		return -EINVAL;
- 
--static const struct phm_master_table_item cz_disable_dpm_list[] = {
--	{ .tableFunction = cz_tf_check_for_dpm_enabled },
--	{ },
-+	return 0;
- };
- 
-+static int cz_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
-+{
-+	if (cz_check_for_dpm_enabled(hwmgr)) {
-+		pr_info("dpm has been enabled\n");
-+		return 0;
-+	}
- 
--static const struct phm_master_table_header cz_disable_dpm_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	cz_disable_dpm_list
--};
--
--static const struct phm_master_table_item cz_enable_dpm_list[] = {
--	{ .tableFunction = cz_tf_check_for_dpm_disabled },
--	{ .tableFunction = cz_tf_program_voting_clients },
--	{ .tableFunction = cz_tf_start_dpm },
--	{ .tableFunction = cz_tf_program_bootup_state },
--	{ .tableFunction = cz_tf_enable_didt },
--	{ .tableFunction = cz_tf_reset_acp_boot_level },
--	{ },
--};
-+	cz_program_voting_clients(hwmgr);
-+	if (cz_start_dpm(hwmgr))
-+		return -EINVAL;
-+	cz_program_bootup_state(hwmgr);
-+	cz_reset_acp_boot_level(hwmgr);
- 
--static const struct phm_master_table_header cz_enable_dpm_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	cz_enable_dpm_list
-+	return 0;
- };
- 
- static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
-@@ -1138,7 +1113,11 @@ static int cz_apply_state_adjust_rules(s
- 
- 	cz_ps->action = cz_current_ps->action;
- 
--	if (!force_high && (cz_ps->action == FORCE_HIGH))
-+	if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
-+		cz_nbdpm_pstate_enable_disable(hwmgr, false, false);
-+	else if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD)
-+		cz_nbdpm_pstate_enable_disable(hwmgr, false, true);
-+	else if (!force_high && (cz_ps->action == FORCE_HIGH))
- 		cz_ps->action = CANCEL_FORCE_HIGH;
- 	else if (force_high && (cz_ps->action != FORCE_HIGH))
- 		cz_ps->action = FORCE_HIGH;
-@@ -1173,62 +1152,16 @@ static int cz_hwmgr_backend_init(struct
- 
- 	cz_construct_boot_state(hwmgr);
- 
--	result = phm_construct_table(hwmgr, &cz_setup_asic_master,
--				&(hwmgr->setup_asic));
--	if (result != 0) {
--		pr_err("Fail to construct setup ASIC\n");
--		return result;
--	}
--
--	result = phm_construct_table(hwmgr, &cz_power_down_asic_master,
--				&(hwmgr->power_down_asic));
--	if (result != 0) {
--		pr_err("Fail to construct power down ASIC\n");
--		return result;
--	}
--
--	result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
--				&(hwmgr->disable_dynamic_state_management));
--	if (result != 0) {
--		pr_err("Fail to disable_dynamic_state\n");
--		return result;
--	}
--	result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
--				&(hwmgr->enable_dynamic_state_management));
--	if (result != 0) {
--		pr_err("Fail to enable_dynamic_state\n");
--		return result;
--	}
--	result = phm_construct_table(hwmgr, &cz_set_power_state_master,
--				&(hwmgr->set_power_state));
--	if (result != 0) {
--		pr_err("Fail to construct set_power_state\n");
--		return result;
--	}
- 	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =  CZ_MAX_HARDWARE_POWERLEVELS;
- 
--	result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
--	if (result != 0) {
--		pr_err("Fail to construct enable_clock_power_gatings\n");
--		return result;
--	}
- 	return result;
- }
- 
- static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
- {
- 	if (hwmgr != NULL) {
--		phm_destroy_table(hwmgr, &(hwmgr->enable_clock_power_gatings));
--		phm_destroy_table(hwmgr, &(hwmgr->set_power_state));
--		phm_destroy_table(hwmgr, &(hwmgr->enable_dynamic_state_management));
--		phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management));
--		phm_destroy_table(hwmgr, &(hwmgr->power_down_asic));
--		phm_destroy_table(hwmgr, &(hwmgr->setup_asic));
--
--		if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
--			kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
--			hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
--		}
-+		kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
-+		hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
- 
- 		kfree(hwmgr->backend);
- 		hwmgr->backend = NULL;
-@@ -1240,13 +1173,13 @@ static int cz_phm_force_dpm_highest(stru
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 
--	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_SetSclkSoftMin,
- 					cz_get_sclk_level(hwmgr,
- 					cz_hwmgr->sclk_dpm.soft_max_clk,
- 					PPSMC_MSG_SetSclkSoftMin));
- 
--	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetSclkSoftMax,
- 				cz_get_sclk_level(hwmgr,
- 				cz_hwmgr->sclk_dpm.soft_max_clk,
-@@ -1278,13 +1211,13 @@ static int cz_phm_unforce_dpm_levels(str
- 	cz_hwmgr->sclk_dpm.soft_max_clk = clock;
- 	cz_hwmgr->sclk_dpm.hard_max_clk = clock;
- 
--	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetSclkSoftMin,
- 				cz_get_sclk_level(hwmgr,
- 				cz_hwmgr->sclk_dpm.soft_min_clk,
- 				PPSMC_MSG_SetSclkSoftMin));
- 
--	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetSclkSoftMax,
- 				cz_get_sclk_level(hwmgr,
- 				cz_hwmgr->sclk_dpm.soft_max_clk,
-@@ -1297,13 +1230,13 @@ static int cz_phm_force_dpm_lowest(struc
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 
--	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_SetSclkSoftMax,
- 			cz_get_sclk_level(hwmgr,
- 			cz_hwmgr->sclk_dpm.soft_min_clk,
- 			PPSMC_MSG_SetSclkSoftMax));
- 
--	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetSclkSoftMin,
- 				cz_get_sclk_level(hwmgr,
- 				cz_hwmgr->sclk_dpm.soft_min_clk,
-@@ -1312,106 +1245,25 @@ static int cz_phm_force_dpm_lowest(struc
- 	return 0;
- }
- 
--static int cz_phm_force_dpm_sclk(struct pp_hwmgr *hwmgr, uint32_t sclk)
--{
--	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--				PPSMC_MSG_SetSclkSoftMin,
--				cz_get_sclk_level(hwmgr,
--				sclk,
--				PPSMC_MSG_SetSclkSoftMin));
--
--	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--				PPSMC_MSG_SetSclkSoftMax,
--				cz_get_sclk_level(hwmgr,
--				sclk,
--				PPSMC_MSG_SetSclkSoftMax));
--	return 0;
--}
--
--static int cz_get_profiling_clk(struct pp_hwmgr *hwmgr, uint32_t *sclk)
--{
--	struct phm_clock_voltage_dependency_table *table =
--		hwmgr->dyn_state.vddc_dependency_on_sclk;
--	int32_t tmp_sclk;
--	int32_t count;
--
--	tmp_sclk = table->entries[table->count-1].clk * 70 / 100;
--
--	for (count = table->count-1; count >= 0; count--) {
--		if (tmp_sclk >= table->entries[count].clk) {
--			tmp_sclk = table->entries[count].clk;
--			*sclk = tmp_sclk;
--			break;
--		}
--	}
--	if (count < 0)
--		*sclk = table->entries[0].clk;
--
--	return 0;
--}
--
- static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
- 				enum amd_dpm_forced_level level)
- {
--	uint32_t sclk = 0;
- 	int ret = 0;
--	uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
--					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
--					AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
--
--	if (level == hwmgr->dpm_level)
--		return ret;
--
--	if (!(hwmgr->dpm_level & profile_mode_mask)) {
--		/* enter profile mode, save current level, disable gfx cg*/
--		if (level & profile_mode_mask) {
--			hwmgr->saved_dpm_level = hwmgr->dpm_level;
--			cgs_set_clockgating_state(hwmgr->device,
--						AMD_IP_BLOCK_TYPE_GFX,
--						AMD_CG_STATE_UNGATE);
--		}
--	} else {
--		/* exit profile mode, restore level, enable gfx cg*/
--		if (!(level & profile_mode_mask)) {
--			if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
--				level = hwmgr->saved_dpm_level;
--			cgs_set_clockgating_state(hwmgr->device,
--					AMD_IP_BLOCK_TYPE_GFX,
--					AMD_CG_STATE_GATE);
--		}
--	}
- 
- 	switch (level) {
- 	case AMD_DPM_FORCED_LEVEL_HIGH:
- 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
- 		ret = cz_phm_force_dpm_highest(hwmgr);
--		if (ret)
--			return ret;
--		hwmgr->dpm_level = level;
- 		break;
- 	case AMD_DPM_FORCED_LEVEL_LOW:
- 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
-+	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
- 		ret = cz_phm_force_dpm_lowest(hwmgr);
--		if (ret)
--			return ret;
--		hwmgr->dpm_level = level;
- 		break;
- 	case AMD_DPM_FORCED_LEVEL_AUTO:
- 		ret = cz_phm_unforce_dpm_levels(hwmgr);
--		if (ret)
--			return ret;
--		hwmgr->dpm_level = level;
--		break;
--	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
--		ret = cz_get_profiling_clk(hwmgr, &sclk);
--		if (ret)
--			return ret;
--		hwmgr->dpm_level = level;
--		cz_phm_force_dpm_sclk(hwmgr, sclk);
- 		break;
- 	case AMD_DPM_FORCED_LEVEL_MANUAL:
--		hwmgr->dpm_level = level;
--		break;
- 	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
- 	default:
- 		break;
-@@ -1422,27 +1274,18 @@ static int cz_dpm_force_dpm_level(struct
- 
- int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
- {
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--					 PHM_PlatformCaps_UVDPowerGating))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
--						     PPSMC_MSG_UVDPowerOFF);
-+	if (PP_CAP(PHM_PlatformCaps_UVDPowerGating))
-+		return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF);
- 	return 0;
- }
- 
- int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
- {
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--					 PHM_PlatformCaps_UVDPowerGating)) {
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--				  PHM_PlatformCaps_UVDDynamicPowerGating)) {
--			return smum_send_msg_to_smc_with_parameter(
--								hwmgr->smumgr,
--						   PPSMC_MSG_UVDPowerON, 1);
--		} else {
--			return smum_send_msg_to_smc_with_parameter(
--								hwmgr->smumgr,
--						   PPSMC_MSG_UVDPowerON, 0);
--		}
-+	if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) {
-+		return smum_send_msg_to_smc_with_parameter(
-+			hwmgr,
-+			PPSMC_MSG_UVDPowerON,
-+			PP_CAP(PHM_PlatformCaps_UVDDynamicPowerGating) ? 1 : 0);
- 	}
- 
- 	return 0;
-@@ -1456,16 +1299,16 @@ int cz_dpm_update_uvd_dpm(struct pp_hwmg
- 
- 	if (!bgate) {
- 		/* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--					 PHM_PlatformCaps_StablePState)) {
-+		if (PP_CAP(PHM_PlatformCaps_StablePState) ||
-+		    hwmgr->en_umd_pstate) {
- 			cz_hwmgr->uvd_dpm.hard_min_clk =
- 				   ptable->entries[ptable->count - 1].vclk;
- 
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--						     PPSMC_MSG_SetUvdHardMin,
--						      cz_get_uvd_level(hwmgr,
--					     cz_hwmgr->uvd_dpm.hard_min_clk,
--						   PPSMC_MSG_SetUvdHardMin));
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_SetUvdHardMin,
-+				cz_get_uvd_level(hwmgr,
-+					cz_hwmgr->uvd_dpm.hard_min_clk,
-+					PPSMC_MSG_SetUvdHardMin));
- 
- 			cz_enable_disable_uvd_dpm(hwmgr, true);
- 		} else {
-@@ -1485,32 +1328,32 @@ int  cz_dpm_update_vce_dpm(struct pp_hwm
- 		hwmgr->dyn_state.vce_clock_voltage_dependency_table;
- 
- 	/* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--					 PHM_PlatformCaps_StablePState)) {
-+	if (PP_CAP(PHM_PlatformCaps_StablePState) ||
-+	    hwmgr->en_umd_pstate) {
- 		cz_hwmgr->vce_dpm.hard_min_clk =
- 				  ptable->entries[ptable->count - 1].ecclk;
- 
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--					PPSMC_MSG_SetEclkHardMin,
--					cz_get_eclk_level(hwmgr,
--					     cz_hwmgr->vce_dpm.hard_min_clk,
--						PPSMC_MSG_SetEclkHardMin));
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
-+			PPSMC_MSG_SetEclkHardMin,
-+			cz_get_eclk_level(hwmgr,
-+				cz_hwmgr->vce_dpm.hard_min_clk,
-+				PPSMC_MSG_SetEclkHardMin));
- 	} else {
- 		/*Program HardMin based on the vce_arbiter.ecclk */
- 		if (hwmgr->vce_arbiter.ecclk == 0) {
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
- 					    PPSMC_MSG_SetEclkHardMin, 0);
- 		/* disable ECLK DPM 0. Otherwise VCE could hang if
- 		 * switching SCLK from DPM 0 to 6/7 */
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_SetEclkSoftMin, 1);
- 		} else {
- 			cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--						PPSMC_MSG_SetEclkHardMin,
--						cz_get_eclk_level(hwmgr,
--						cz_hwmgr->vce_dpm.hard_min_clk,
--						PPSMC_MSG_SetEclkHardMin));
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_SetEclkHardMin,
-+				cz_get_eclk_level(hwmgr,
-+					cz_hwmgr->vce_dpm.hard_min_clk,
-+					PPSMC_MSG_SetEclkHardMin));
- 		}
- 	}
- 	return 0;
-@@ -1518,30 +1361,28 @@ int  cz_dpm_update_vce_dpm(struct pp_hwm
- 
- int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
- {
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--					 PHM_PlatformCaps_VCEPowerGating))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
-+	if (PP_CAP(PHM_PlatformCaps_VCEPowerGating))
-+		return smum_send_msg_to_smc(hwmgr,
- 						     PPSMC_MSG_VCEPowerOFF);
- 	return 0;
- }
- 
- int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
- {
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--					 PHM_PlatformCaps_VCEPowerGating))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
-+	if (PP_CAP(PHM_PlatformCaps_VCEPowerGating))
-+		return smum_send_msg_to_smc(hwmgr,
- 						     PPSMC_MSG_VCEPowerON);
- 	return 0;
- }
- 
--static int cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
-+static uint32_t cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
- {
- 	struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
- 
- 	return cz_hwmgr->sys_info.bootup_uma_clock;
- }
- 
--static int cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
-+static uint32_t cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
- {
- 	struct pp_power_state  *ps;
- 	struct cz_power_state  *cz_ps;
-@@ -1679,7 +1520,7 @@ static void cz_hw_print_display_cfg(
- 		PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
- 			data);
- 
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 						PPSMC_MSG_SetDisplaySizePowerParams,
- 						data);
- 	}
-@@ -1744,10 +1585,10 @@ static int cz_force_clock_level(struct p
- 
- 	switch (type) {
- 	case PP_SCLK:
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetSclkSoftMin,
- 				mask);
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetSclkSoftMax,
- 				mask);
- 		break;
-@@ -1989,7 +1830,7 @@ static int cz_read_sensor(struct pp_hwmg
- 		*((uint32_t *)value) = 0;
- 		return 0;
- 	case AMDGPU_PP_SENSOR_GPU_LOAD:
--		result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
-+		result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGraphicsActivity);
- 		if (0 == result) {
- 			activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
- 			activity_percent = activity_percent > 100 ? 100 : activity_percent;
-@@ -2012,10 +1853,36 @@ static int cz_read_sensor(struct pp_hwmg
- 	}
- }
- 
-+static int cz_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
-+					uint32_t virtual_addr_low,
-+					uint32_t virtual_addr_hi,
-+					uint32_t mc_addr_low,
-+					uint32_t mc_addr_hi,
-+					uint32_t size)
-+{
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
-+					PPSMC_MSG_DramAddrHiVirtual,
-+					mc_addr_hi);
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
-+					PPSMC_MSG_DramAddrLoVirtual,
-+					mc_addr_low);
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
-+					PPSMC_MSG_DramAddrHiPhysical,
-+					virtual_addr_hi);
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
-+					PPSMC_MSG_DramAddrLoPhysical,
-+					virtual_addr_low);
-+
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
-+					PPSMC_MSG_DramBufferSize,
-+					size);
-+	return 0;
-+}
-+
-+
- static const struct pp_hwmgr_func cz_hwmgr_funcs = {
- 	.backend_init = cz_hwmgr_backend_init,
- 	.backend_fini = cz_hwmgr_backend_fini,
--	.asic_setup = NULL,
- 	.apply_state_adjust_rules = cz_apply_state_adjust_rules,
- 	.force_dpm_level = cz_dpm_force_dpm_level,
- 	.get_power_state_size = cz_get_power_state_size,
-@@ -2036,7 +1903,14 @@ static const struct pp_hwmgr_func cz_hwm
- 	.get_current_shallow_sleep_clocks = cz_get_current_shallow_sleep_clocks,
- 	.get_clock_by_type = cz_get_clock_by_type,
- 	.get_max_high_clocks = cz_get_max_high_clocks,
-+	.get_temperature = cz_thermal_get_temperature,
- 	.read_sensor = cz_read_sensor,
-+	.power_off_asic = cz_power_off_asic,
-+	.asic_setup = cz_setup_asic_task,
-+	.dynamic_state_management_enable = cz_enable_dpm_tasks,
-+	.power_state_set = cz_set_power_state_tasks,
-+	.dynamic_state_management_disable = cz_disable_dpm_tasks,
-+	.notify_cac_buffer_info = cz_notify_cac_buffer_info,
- };
- 
- int cz_init_function_pointers(struct pp_hwmgr *hwmgr)
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c	2017-12-14 06:39:58.468903604 +0100
-@@ -26,35 +26,22 @@
- #include "hardwaremanager.h"
- #include "power_state.h"
- 
-+
-+#define TEMP_RANGE_MIN (0)
-+#define TEMP_RANGE_MAX (80 * 1000)
-+
- #define PHM_FUNC_CHECK(hw) \
- 	do {							\
- 		if ((hw) == NULL || (hw)->hwmgr_func == NULL)	\
- 			return -EINVAL;				\
- 	} while (0)
- 
--bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
--{
--	return hwmgr->block_hw_access;
--}
--
--int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
--{
--	hwmgr->block_hw_access = block;
--	return 0;
--}
--
- int phm_setup_asic(struct pp_hwmgr *hwmgr)
- {
- 	PHM_FUNC_CHECK(hwmgr);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--		PHM_PlatformCaps_TablelessHardwareInterface)) {
--		if (NULL != hwmgr->hwmgr_func->asic_setup)
--			return hwmgr->hwmgr_func->asic_setup(hwmgr);
--	} else {
--		return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
--					  NULL, NULL);
--	}
-+	if (NULL != hwmgr->hwmgr_func->asic_setup)
-+		return hwmgr->hwmgr_func->asic_setup(hwmgr);
- 
- 	return 0;
- }
-@@ -63,14 +50,8 @@ int phm_power_down_asic(struct pp_hwmgr
- {
- 	PHM_FUNC_CHECK(hwmgr);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--		PHM_PlatformCaps_TablelessHardwareInterface)) {
--		if (NULL != hwmgr->hwmgr_func->power_off_asic)
--			return hwmgr->hwmgr_func->power_off_asic(hwmgr);
--	} else {
--		return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
--					  NULL, NULL);
--	}
-+	if (NULL != hwmgr->hwmgr_func->power_off_asic)
-+		return hwmgr->hwmgr_func->power_off_asic(hwmgr);
- 
- 	return 0;
- }
-@@ -86,13 +67,8 @@ int phm_set_power_state(struct pp_hwmgr
- 	states.pcurrent_state = pcurrent_state;
- 	states.pnew_state = pnew_power_state;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--		PHM_PlatformCaps_TablelessHardwareInterface)) {
--		if (NULL != hwmgr->hwmgr_func->power_state_set)
--			return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
--	} else {
--		return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
--	}
-+	if (NULL != hwmgr->hwmgr_func->power_state_set)
-+		return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
- 
- 	return 0;
- }
-@@ -103,15 +79,8 @@ int phm_enable_dynamic_state_management(
- 	bool enabled;
- 	PHM_FUNC_CHECK(hwmgr);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--		PHM_PlatformCaps_TablelessHardwareInterface)) {
--		if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
--			ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
--	} else {
--		ret = phm_dispatch_table(hwmgr,
--				&(hwmgr->enable_dynamic_state_management),
--				NULL, NULL);
--	}
-+	if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
-+		ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
- 
- 	enabled = ret == 0;
- 
-@@ -127,15 +96,8 @@ int phm_disable_dynamic_state_management
- 
- 	PHM_FUNC_CHECK(hwmgr);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--		PHM_PlatformCaps_TablelessHardwareInterface)) {
--		if (hwmgr->hwmgr_func->dynamic_state_management_disable)
--			ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
--	} else {
--		ret = phm_dispatch_table(hwmgr,
--				&(hwmgr->disable_dynamic_state_management),
--				NULL, NULL);
--	}
-+	if (hwmgr->hwmgr_func->dynamic_state_management_disable)
-+		ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
- 
- 	enabled = ret == 0 ? false : true;
- 
-@@ -193,35 +155,13 @@ int phm_powerdown_uvd(struct pp_hwmgr *h
- 	return 0;
- }
- 
--int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
--{
--	PHM_FUNC_CHECK(hwmgr);
--
--	if (hwmgr->hwmgr_func->powergate_uvd != NULL)
--		return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
--	return 0;
--}
--
--int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
--{
--	PHM_FUNC_CHECK(hwmgr);
--
--	if (hwmgr->hwmgr_func->powergate_vce != NULL)
--		return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
--	return 0;
--}
--
- int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
- {
- 	PHM_FUNC_CHECK(hwmgr);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--		PHM_PlatformCaps_TablelessHardwareInterface)) {
--		if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
--			return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
--	} else {
--		return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
--	}
-+	if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
-+		return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
-+
- 	return 0;
- }
- 
-@@ -229,11 +169,9 @@ int phm_disable_clock_power_gatings(stru
- {
- 	PHM_FUNC_CHECK(hwmgr);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--		PHM_PlatformCaps_TablelessHardwareInterface)) {
--		if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
--			return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
--	}
-+	if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
-+		return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
-+
- 	return 0;
- }
- 
-@@ -242,12 +180,9 @@ int phm_display_configuration_changed(st
- {
- 	PHM_FUNC_CHECK(hwmgr);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--				 PHM_PlatformCaps_TablelessHardwareInterface)) {
--		if (NULL != hwmgr->hwmgr_func->display_config_changed)
--			hwmgr->hwmgr_func->display_config_changed(hwmgr);
--	} else
--		return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
-+	if (NULL != hwmgr->hwmgr_func->display_config_changed)
-+		hwmgr->hwmgr_func->display_config_changed(hwmgr);
-+
- 	return 0;
- }
- 
-@@ -255,9 +190,7 @@ int phm_notify_smc_display_config_after_
- {
- 	PHM_FUNC_CHECK(hwmgr);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--				 PHM_PlatformCaps_TablelessHardwareInterface))
--		if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
-+	if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
- 			hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
- 
- 	return 0;
-@@ -277,10 +210,10 @@ int phm_register_thermal_interrupt(struc
- {
- 	PHM_FUNC_CHECK(hwmgr);
- 
--	if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
--		return -EINVAL;
-+	if (hwmgr->hwmgr_func->register_internal_thermal_interrupt != NULL)
-+		return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
- 
--	return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
-+	return 0;
- }
- 
- /**
-@@ -292,7 +225,21 @@ int phm_register_thermal_interrupt(struc
- */
- int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
- {
--	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
-+	struct PP_TemperatureRange range;
-+
-+	if (temperature_range == NULL) {
-+		range.max = TEMP_RANGE_MAX;
-+		range.min = TEMP_RANGE_MIN;
-+	} else {
-+		range.max = temperature_range->max;
-+		range.min = temperature_range->min;
-+	}
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ThermalController)
-+			&& hwmgr->hwmgr_func->start_thermal_controller != NULL)
-+		return hwmgr->hwmgr_func->start_thermal_controller(hwmgr, &range);
-+
-+	return 0;
- }
- 
- 
-@@ -323,6 +270,9 @@ int phm_check_states_equal(struct pp_hwm
- int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
- 		    const struct amd_pp_display_configuration *display_config)
- {
-+	int index = 0;
-+	int number_of_active_display = 0;
-+
- 	PHM_FUNC_CHECK(hwmgr);
- 
- 	if (display_config == NULL)
-@@ -330,6 +280,17 @@ int phm_store_dal_configuration_data(str
- 
- 	hwmgr->display_config = *display_config;
- 
-+	if (NULL != hwmgr->hwmgr_func->set_deep_sleep_dcefclk)
-+		hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, hwmgr->display_config.min_dcef_deep_sleep_set_clk);
-+
-+	for (index = 0; index < hwmgr->display_config.num_path_including_non_display; index++) {
-+		if (hwmgr->display_config.displays[index].controller_id != 0)
-+			number_of_active_display++;
-+	}
-+
-+	if (NULL != hwmgr->hwmgr_func->set_active_display_count)
-+		hwmgr->hwmgr_func->set_active_display_count(hwmgr, number_of_active_display);
-+
- 	if (hwmgr->hwmgr_func->store_cc6_data == NULL)
- 		return -EINVAL;
- 
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c	2017-12-14 06:39:58.468903604 +0100
-@@ -26,8 +26,8 @@
- #include <linux/kernel.h>
- #include <linux/slab.h>
- #include <linux/types.h>
-+#include <linux/pci.h>
- #include <drm/amdgpu_drm.h>
--#include "cgs_common.h"
- #include "power_state.h"
- #include "hwmgr.h"
- #include "pppcielanes.h"
-@@ -35,21 +35,100 @@
- #include "ppsmc.h"
- #include "pp_acpi.h"
- #include "amd_acpi.h"
-+#include "pp_psm.h"
- 
--extern int cz_init_function_pointers(struct pp_hwmgr *hwmgr);
-+extern const struct pp_smumgr_func ci_smu_funcs;
-+extern const struct pp_smumgr_func cz_smu_funcs;
-+extern const struct pp_smumgr_func iceland_smu_funcs;
-+extern const struct pp_smumgr_func tonga_smu_funcs;
-+extern const struct pp_smumgr_func fiji_smu_funcs;
-+extern const struct pp_smumgr_func polaris10_smu_funcs;
-+extern const struct pp_smumgr_func vega10_smu_funcs;
-+extern const struct pp_smumgr_func rv_smu_funcs;
- 
-+extern int cz_init_function_pointers(struct pp_hwmgr *hwmgr);
- static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
- static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
- static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
- static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
- static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
- static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
-+static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
- 
- uint8_t convert_to_vid(uint16_t vddc)
- {
- 	return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
- }
- 
-+static int phm_get_pci_bus_devfn(struct pp_hwmgr *hwmgr,
-+		struct cgs_system_info *sys_info)
-+{
-+	sys_info->size = sizeof(struct cgs_system_info);
-+	sys_info->info_id = CGS_SYSTEM_INFO_PCIE_BUS_DEVFN;
-+
-+	return cgs_query_system_info(hwmgr->device, sys_info);
-+}
-+
-+static int phm_thermal_l2h_irq(void *private_data,
-+		 unsigned src_id, const uint32_t *iv_entry)
-+{
-+	struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
-+	struct cgs_system_info sys_info = {0};
-+	int result;
-+
-+	result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
-+	if (result)
-+		return -EINVAL;
-+
-+	pr_warn("GPU over temperature range detected on PCIe %lld:%lld.%lld!\n",
-+			PCI_BUS_NUM(sys_info.value),
-+			PCI_SLOT(sys_info.value),
-+			PCI_FUNC(sys_info.value));
-+	return 0;
-+}
-+
-+static int phm_thermal_h2l_irq(void *private_data,
-+		 unsigned src_id, const uint32_t *iv_entry)
-+{
-+	struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
-+	struct cgs_system_info sys_info = {0};
-+	int result;
-+
-+	result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
-+	if (result)
-+		return -EINVAL;
-+
-+	pr_warn("GPU under temperature range detected on PCIe %lld:%lld.%lld!\n",
-+			PCI_BUS_NUM(sys_info.value),
-+			PCI_SLOT(sys_info.value),
-+			PCI_FUNC(sys_info.value));
-+	return 0;
-+}
-+
-+static int phm_ctf_irq(void *private_data,
-+		 unsigned src_id, const uint32_t *iv_entry)
-+{
-+	struct pp_hwmgr *hwmgr = (struct pp_hwmgr *)private_data;
-+	struct cgs_system_info sys_info = {0};
-+	int result;
-+
-+	result = phm_get_pci_bus_devfn(hwmgr, &sys_info);
-+	if (result)
-+		return -EINVAL;
-+
-+	pr_warn("GPU Critical Temperature Fault detected on PCIe %lld:%lld.%lld!\n",
-+			PCI_BUS_NUM(sys_info.value),
-+			PCI_SLOT(sys_info.value),
-+			PCI_FUNC(sys_info.value));
-+	return 0;
-+}
-+
-+static const struct cgs_irq_src_funcs thermal_irq_src[3] = {
-+	{ .handler = phm_thermal_l2h_irq },
-+	{ .handler = phm_thermal_h2l_irq },
-+	{ .handler = phm_ctf_irq }
-+};
-+
- int hwmgr_early_init(struct pp_instance *handle)
- {
- 	struct pp_hwmgr *hwmgr;
-@@ -62,7 +141,6 @@ int hwmgr_early_init(struct pp_instance
- 		return -ENOMEM;
- 
- 	handle->hwmgr = hwmgr;
--	hwmgr->smumgr = handle->smu_mgr;
- 	hwmgr->device = handle->device;
- 	hwmgr->chip_family = handle->chip_family;
- 	hwmgr->chip_id = handle->chip_id;
-@@ -73,24 +151,38 @@ int hwmgr_early_init(struct pp_instance
- 	hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
- 	hwmgr_init_default_caps(hwmgr);
- 	hwmgr_set_user_specify_caps(hwmgr);
-+	hwmgr->fan_ctrl_is_in_default_mode = true;
-+	hwmgr->reload_fw = 1;
- 
- 	switch (hwmgr->chip_family) {
-+	case AMDGPU_FAMILY_CI:
-+		hwmgr->smumgr_funcs = &ci_smu_funcs;
-+		ci_set_asic_special_caps(hwmgr);
-+		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
-+					PP_ENABLE_GFX_CG_THRU_SMU);
-+		hwmgr->pp_table_version = PP_TABLE_V0;
-+		smu7_init_function_pointers(hwmgr);
-+		break;
- 	case AMDGPU_FAMILY_CZ:
-+		hwmgr->smumgr_funcs = &cz_smu_funcs;
- 		cz_init_function_pointers(hwmgr);
- 		break;
- 	case AMDGPU_FAMILY_VI:
- 		switch (hwmgr->chip_id) {
- 		case CHIP_TOPAZ:
-+			hwmgr->smumgr_funcs = &iceland_smu_funcs;
- 			topaz_set_asic_special_caps(hwmgr);
- 			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
- 						PP_ENABLE_GFX_CG_THRU_SMU);
- 			hwmgr->pp_table_version = PP_TABLE_V0;
- 			break;
- 		case CHIP_TONGA:
-+			hwmgr->smumgr_funcs = &tonga_smu_funcs;
- 			tonga_set_asic_special_caps(hwmgr);
- 			hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
- 			break;
- 		case CHIP_FIJI:
-+			hwmgr->smumgr_funcs = &fiji_smu_funcs;
- 			fiji_set_asic_special_caps(hwmgr);
- 			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
- 						PP_ENABLE_GFX_CG_THRU_SMU);
-@@ -98,6 +190,7 @@ int hwmgr_early_init(struct pp_instance
- 		case CHIP_POLARIS11:
- 		case CHIP_POLARIS10:
- 		case CHIP_POLARIS12:
-+			hwmgr->smumgr_funcs = &polaris10_smu_funcs;
- 			polaris_set_asic_special_caps(hwmgr);
- 			hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
- 			break;
-@@ -109,6 +202,7 @@ int hwmgr_early_init(struct pp_instance
- 	case AMDGPU_FAMILY_AI:
- 		switch (hwmgr->chip_id) {
- 		case CHIP_VEGA10:
-+			hwmgr->smumgr_funcs = &vega10_smu_funcs;
- 			vega10_hwmgr_init(hwmgr);
- 			break;
- 		default:
-@@ -118,6 +212,7 @@ int hwmgr_early_init(struct pp_instance
- 	case AMDGPU_FAMILY_RV:
- 		switch (hwmgr->chip_id) {
- 		case CHIP_RAVEN:
-+			hwmgr->smumgr_funcs = &rv_smu_funcs;
- 			rv_init_function_pointers(hwmgr);
- 			break;
- 		default:
-@@ -131,80 +226,6 @@ int hwmgr_early_init(struct pp_instance
- 	return 0;
- }
- 
--static int hw_init_power_state_table(struct pp_hwmgr *hwmgr)
--{
--	int result;
--	unsigned int i;
--	unsigned int table_entries;
--	struct pp_power_state *state;
--	int size;
--
--	if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
--		return -EINVAL;
--
--	if (hwmgr->hwmgr_func->get_power_state_size == NULL)
--		return -EINVAL;
--
--	hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
--
--	hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
--					  sizeof(struct pp_power_state);
--
--	hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL);
--	if (hwmgr->ps == NULL)
--		return -ENOMEM;
--
--	hwmgr->request_ps = kzalloc(size, GFP_KERNEL);
--	if (hwmgr->request_ps == NULL) {
--		kfree(hwmgr->ps);
--		hwmgr->ps = NULL;
--		return -ENOMEM;
--	}
--
--	hwmgr->current_ps = kzalloc(size, GFP_KERNEL);
--	if (hwmgr->current_ps == NULL) {
--		kfree(hwmgr->request_ps);
--		kfree(hwmgr->ps);
--		hwmgr->request_ps = NULL;
--		hwmgr->ps = NULL;
--		return -ENOMEM;
--	}
--
--	state = hwmgr->ps;
--
--	for (i = 0; i < table_entries; i++) {
--		result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state);
--
--		if (state->classification.flags & PP_StateClassificationFlag_Boot) {
--			hwmgr->boot_ps = state;
--			memcpy(hwmgr->current_ps, state, size);
--			memcpy(hwmgr->request_ps, state, size);
--		}
--
--		state->id = i + 1; /* assigned unique num for every power state id */
--
--		if (state->classification.flags & PP_StateClassificationFlag_Uvd)
--			hwmgr->uvd_ps = state;
--		state = (struct pp_power_state *)((unsigned long)state + size);
--	}
--
--	return 0;
--}
--
--static int hw_fini_power_state_table(struct pp_hwmgr *hwmgr)
--{
--	if (hwmgr == NULL)
--		return -EINVAL;
--
--	kfree(hwmgr->current_ps);
--	kfree(hwmgr->request_ps);
--	kfree(hwmgr->ps);
--	hwmgr->request_ps = NULL;
--	hwmgr->ps = NULL;
--	hwmgr->current_ps = NULL;
--	return 0;
--}
--
- int hwmgr_hw_init(struct pp_instance *handle)
- {
- 	struct pp_hwmgr *hwmgr;
-@@ -228,9 +249,26 @@ int hwmgr_hw_init(struct pp_instance *ha
- 	if (ret)
- 		goto err1;
- 
--	ret = hw_init_power_state_table(hwmgr);
-+	ret = psm_init_power_state_table(hwmgr);
-+	if (ret)
-+		goto err2;
-+
-+	ret = phm_setup_asic(hwmgr);
- 	if (ret)
- 		goto err2;
-+
-+	ret = phm_enable_dynamic_state_management(hwmgr);
-+	if (ret)
-+		goto err2;
-+	ret = phm_start_thermal_controller(hwmgr, NULL);
-+	ret |= psm_set_performance_states(hwmgr);
-+	if (ret)
-+		goto err2;
-+
-+	ret = phm_register_thermal_interrupt(hwmgr, &thermal_irq_src);
-+	if (ret)
-+		goto err2;
-+
- 	return 0;
- err2:
- 	if (hwmgr->hwmgr_func->backend_fini)
-@@ -247,19 +285,137 @@ int hwmgr_hw_fini(struct pp_instance *ha
- {
- 	struct pp_hwmgr *hwmgr;
- 
--	if (handle == NULL)
-+	if (handle == NULL || handle->hwmgr == NULL)
- 		return -EINVAL;
- 
- 	hwmgr = handle->hwmgr;
- 
-+	phm_stop_thermal_controller(hwmgr);
-+	psm_set_boot_states(hwmgr);
-+	psm_adjust_power_state_dynamic(hwmgr, false, NULL);
-+	phm_disable_dynamic_state_management(hwmgr);
-+	phm_disable_clock_power_gatings(hwmgr);
-+
- 	if (hwmgr->hwmgr_func->backend_fini)
- 		hwmgr->hwmgr_func->backend_fini(hwmgr);
- 	if (hwmgr->pptable_func->pptable_fini)
- 		hwmgr->pptable_func->pptable_fini(hwmgr);
--	return hw_fini_power_state_table(hwmgr);
-+	return psm_fini_power_state_table(hwmgr);
-+}
-+
-+int hwmgr_hw_suspend(struct pp_instance *handle)
-+{
-+	struct pp_hwmgr *hwmgr;
-+	int ret = 0;
-+
-+	if (handle == NULL || handle->hwmgr == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = handle->hwmgr;
-+	phm_disable_smc_firmware_ctf(hwmgr);
-+	ret = psm_set_boot_states(hwmgr);
-+	if (ret)
-+		return ret;
-+	ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
-+	if (ret)
-+		return ret;
-+	ret = phm_power_down_asic(hwmgr);
-+
-+	return ret;
-+}
-+
-+int hwmgr_hw_resume(struct pp_instance *handle)
-+{
-+	struct pp_hwmgr *hwmgr;
-+	int ret = 0;
-+
-+	if (handle == NULL || handle->hwmgr == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = handle->hwmgr;
-+	ret = phm_setup_asic(hwmgr);
-+	if (ret)
-+		return ret;
-+
-+	ret = phm_enable_dynamic_state_management(hwmgr);
-+	if (ret)
-+		return ret;
-+	ret = phm_start_thermal_controller(hwmgr, NULL);
-+	if (ret)
-+		return ret;
-+
-+	ret |= psm_set_performance_states(hwmgr);
-+	if (ret)
-+		return ret;
-+
-+	ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
-+
-+	return ret;
- }
- 
-+static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
-+{
-+	switch (state) {
-+	case POWER_STATE_TYPE_BATTERY:
-+		return PP_StateUILabel_Battery;
-+	case POWER_STATE_TYPE_BALANCED:
-+		return PP_StateUILabel_Balanced;
-+	case POWER_STATE_TYPE_PERFORMANCE:
-+		return PP_StateUILabel_Performance;
-+	default:
-+		return PP_StateUILabel_None;
-+	}
-+}
- 
-+int hwmgr_handle_task(struct pp_instance *handle, enum amd_pp_task task_id,
-+		void *input, void *output)
-+{
-+	int ret = 0;
-+	struct pp_hwmgr *hwmgr;
-+
-+	if (handle == NULL || handle->hwmgr == NULL)
-+		return -EINVAL;
-+
-+	hwmgr = handle->hwmgr;
-+
-+	switch (task_id) {
-+	case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
-+		ret = phm_set_cpu_power_state(hwmgr);
-+		if (ret)
-+			return ret;
-+		ret = psm_set_performance_states(hwmgr);
-+		if (ret)
-+			return ret;
-+		ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
-+		break;
-+	case AMD_PP_TASK_ENABLE_USER_STATE:
-+	{
-+		enum amd_pm_state_type ps;
-+		enum PP_StateUILabel requested_ui_label;
-+		struct pp_power_state *requested_ps = NULL;
-+
-+		if (input == NULL) {
-+			ret = -EINVAL;
-+			break;
-+		}
-+		ps = *(unsigned long *)input;
-+
-+		requested_ui_label = power_state_convert(ps);
-+		ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
-+		if (ret)
-+			return ret;
-+		ret = psm_adjust_power_state_dynamic(hwmgr, false, requested_ps);
-+		break;
-+	}
-+	case AMD_PP_TASK_COMPLETE_INIT:
-+	case AMD_PP_TASK_READJUST_POWER_STATE:
-+		ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
-+		break;
-+	default:
-+		break;
-+	}
-+	return ret;
-+}
- /**
-  * Returns once the part of the register indicated by the mask has
-  * reached the given value.
-@@ -294,7 +450,7 @@ int phm_wait_on_register(struct pp_hwmgr
-  * reached the given value.The indirect space is described by giving
-  * the memory-mapped index of the indirect index register.
-  */
--void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
-+int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
- 				uint32_t indirect_port,
- 				uint32_t index,
- 				uint32_t value,
-@@ -302,14 +458,50 @@ void phm_wait_on_indirect_register(struc
- {
- 	if (hwmgr == NULL || hwmgr->device == NULL) {
- 		pr_err("Invalid Hardware Manager!");
--		return;
-+		return -EINVAL;
- 	}
- 
- 	cgs_write_register(hwmgr->device, indirect_port, index);
--	phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
-+	return phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
- }
- 
-+int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
-+					uint32_t index,
-+					uint32_t value, uint32_t mask)
-+{
-+	uint32_t i;
-+	uint32_t cur_value;
-+
-+	if (hwmgr == NULL || hwmgr->device == NULL)
-+		return -EINVAL;
-+
-+	for (i = 0; i < hwmgr->usec_timeout; i++) {
-+		cur_value = cgs_read_register(hwmgr->device,
-+									index);
-+		if ((cur_value & mask) != (value & mask))
-+			break;
-+		udelay(1);
-+	}
- 
-+	/* timeout means wrong logic */
-+	if (i == hwmgr->usec_timeout)
-+		return -ETIME;
-+	return 0;
-+}
-+
-+int phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
-+						uint32_t indirect_port,
-+						uint32_t index,
-+						uint32_t value,
-+						uint32_t mask)
-+{
-+	if (hwmgr == NULL || hwmgr->device == NULL)
-+		return -EINVAL;
-+
-+	cgs_write_register(hwmgr->device, indirect_port, index);
-+	return phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
-+						value, mask);
-+}
- 
- bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)
- {
-@@ -678,7 +870,7 @@ void phm_apply_dal_min_voltage_request(s
- 	for (i = 0; i < vddc_table->count; i++) {
- 		if (req_vddc <= vddc_table->entries[i].vddc) {
- 			req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_VddC_Request, req_volt);
- 			return;
- 		}
-@@ -689,28 +881,8 @@ void phm_apply_dal_min_voltage_request(s
- 
- void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
- {
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);
--
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);
--
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
- 
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);
--
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
--
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
- 
-@@ -735,7 +907,6 @@ void hwmgr_init_default_caps(struct pp_h
- 
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 						PHM_PlatformCaps_FanSpeedInTableIsRPM);
--
- 	return;
- }
- 
-@@ -784,7 +955,8 @@ int phm_get_voltage_evv_on_sclk(struct p
- 
- int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
- {
--
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_EVV);
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 						PHM_PlatformCaps_SQRamping);
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-@@ -793,10 +965,6 @@ int polaris_set_asic_special_caps(struct
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 					PHM_PlatformCaps_AutomaticDCTransition);
- 
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_TablelessHardwareInterface);
--
--
- 	if (hwmgr->chip_id != CHIP_POLARIS10)
- 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 					PHM_PlatformCaps_SPLLShutdownSupport);
-@@ -814,6 +982,8 @@ int polaris_set_asic_special_caps(struct
- 
- int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
- {
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_EVV);
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_SQRamping);
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-@@ -822,15 +992,13 @@ int fiji_set_asic_special_caps(struct pp
- 			PHM_PlatformCaps_TDRamping);
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_TCPRamping);
--
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_TablelessHardwareInterface);
--
- 	return 0;
- }
- 
- int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
- {
-+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+						PHM_PlatformCaps_EVV);
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_SQRamping);
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-@@ -844,14 +1012,25 @@ int tonga_set_asic_special_caps(struct p
- 		      PHM_PlatformCaps_UVDPowerGating);
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 		      PHM_PlatformCaps_VCEPowerGating);
-+	return 0;
-+}
- 
-+int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
-+{
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--			 PHM_PlatformCaps_TablelessHardwareInterface);
--
-+						PHM_PlatformCaps_EVV);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SQRamping);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_DBRamping);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_TDRamping);
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_TCPRamping);
- 	return 0;
- }
- 
--int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
-+int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
- {
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_SQRamping);
-@@ -862,8 +1041,8 @@ int topaz_set_asic_special_caps(struct p
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_TCPRamping);
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--			 PHM_PlatformCaps_TablelessHardwareInterface);
-+			PHM_PlatformCaps_MemorySpreadSpectrumSupport);
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--		    PHM_PlatformCaps_EVV);
-+			PHM_PlatformCaps_EngineSpreadSpectrumSupport);
- 	return 0;
- }
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile	2017-12-14 06:39:58.468903604 +0100
-@@ -3,14 +3,15 @@
- # Makefile for the 'hw manager' sub-component of powerplay.
- # It provides the hardware management services for the driver.
- 
--HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
-+HARDWARE_MGR = hwmgr.o processpptables.o \
- 		hardwaremanager.o pp_acpi.o cz_hwmgr.o \
- 		cz_clockpowergating.o pppcielanes.o\
- 		process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \
- 		smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \
- 		smu7_clockpowergating.o \
- 		vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \
--		vega10_thermal.o pp_overdriver.o rv_hwmgr.o
-+		vega10_thermal.o rv_hwmgr.o pp_psm.o\
-+		pp_overdriver.o
- 
- AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
- 
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c	2017-12-14 06:39:58.469903605 +0100
-@@ -470,7 +470,7 @@ uint32_t atomctrl_get_reference_clock(st
-  * SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ.
-  * voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE
-  */
--bool atomctrl_is_voltage_controled_by_gpio_v3(
-+bool atomctrl_is_voltage_controlled_by_gpio_v3(
- 		struct pp_hwmgr *hwmgr,
- 		uint8_t voltage_type,
- 		uint8_t voltage_mode)
-@@ -1100,10 +1100,10 @@ int atomctrl_get_voltage_evv(struct pp_h
- 		}
- 	}
- 
--	PP_ASSERT_WITH_CODE(entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count,
--	        "Can't find requested voltage id in vddc_dependency_on_sclk table!",
-+	if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) {
-+	        pr_debug("Can't find requested voltage id in vddc_dependency_on_sclk table!\n");
- 	        return -EINVAL;
--	);
-+	}
- 
- 	get_voltage_info_param_space.ucVoltageType = VOLTAGE_TYPE_VDDC;
- 	get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
-@@ -1418,3 +1418,83 @@ int  atomctrl_get_svi2_info(struct pp_hw
- 
- 	return 0;
- }
-+
-+int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id)
-+{
-+	int result;
-+	SET_VOLTAGE_PS_ALLOCATION allocation;
-+	SET_VOLTAGE_PARAMETERS_V1_3 *voltage_parameters =
-+			(SET_VOLTAGE_PARAMETERS_V1_3 *)&allocation.sASICSetVoltage;
-+
-+	voltage_parameters->ucVoltageMode = ATOM_GET_LEAKAGE_ID;
-+
-+	result = cgs_atom_exec_cmd_table(hwmgr->device,
-+			GetIndexIntoMasterTable(COMMAND, SetVoltage),
-+			voltage_parameters);
-+
-+	*virtual_voltage_id = voltage_parameters->usVoltageLevel;
-+
-+	return result;
-+}
-+
-+int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
-+					uint16_t *vddc, uint16_t *vddci,
-+					uint16_t virtual_voltage_id,
-+					uint16_t efuse_voltage_id)
-+{
-+	int i, j;
-+	int ix;
-+	u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
-+	ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
-+
-+	*vddc = 0;
-+	*vddci = 0;
-+
-+	ix = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
-+
-+	profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
-+			cgs_atom_get_data_table(hwmgr->device,
-+					ix,
-+					NULL, NULL, NULL);
-+	if (!profile)
-+		return -EINVAL;
-+
-+	if ((profile->asHeader.ucTableFormatRevision >= 2) &&
-+		(profile->asHeader.ucTableContentRevision >= 1) &&
-+		(profile->asHeader.usStructureSize >= sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))) {
-+		leakage_bin = (u16 *)((char *)profile + profile->usLeakageBinArrayOffset);
-+		vddc_id_buf = (u16 *)((char *)profile + profile->usElbVDDC_IdArrayOffset);
-+		vddc_buf = (u16 *)((char *)profile + profile->usElbVDDC_LevelArrayOffset);
-+		if (profile->ucElbVDDC_Num > 0) {
-+			for (i = 0; i < profile->ucElbVDDC_Num; i++) {
-+				if (vddc_id_buf[i] == virtual_voltage_id) {
-+					for (j = 0; j < profile->ucLeakageBinNum; j++) {
-+						if (efuse_voltage_id <= leakage_bin[j]) {
-+							*vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
-+							break;
-+						}
-+					}
-+					break;
-+				}
-+			}
-+		}
-+
-+		vddci_id_buf = (u16 *)((char *)profile + profile->usElbVDDCI_IdArrayOffset);
-+		vddci_buf   = (u16 *)((char *)profile + profile->usElbVDDCI_LevelArrayOffset);
-+		if (profile->ucElbVDDCI_Num > 0) {
-+			for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
-+				if (vddci_id_buf[i] == virtual_voltage_id) {
-+					for (j = 0; j < profile->ucLeakageBinNum; j++) {
-+						if (efuse_voltage_id <= leakage_bin[j]) {
-+							*vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
-+							break;
-+						}
-+					}
-+					break;
-+				}
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h	2017-12-14 06:39:58.469903605 +0100
-@@ -291,7 +291,7 @@ extern uint32_t atomctrl_get_reference_c
- extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
- extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
- extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
--extern bool atomctrl_is_voltage_controled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
-+extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
- extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
- extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
- 		uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
-@@ -314,5 +314,11 @@ extern int atomctrl_get_avfs_information
- extern int  atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
- 				uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,
- 				uint16_t *load_line);
-+
-+extern int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
-+					uint16_t *vddc, uint16_t *vddci,
-+					uint16_t virtual_voltage_id,
-+					uint16_t efuse_voltage_id);
-+extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id);
- #endif
- 
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.c	2017-12-14 06:39:58.471903606 +0100
-@@ -2,1263 +2,1252 @@
- #include "pp_overdriver.h"
- #include <linux/errno.h>
- 
--struct phm_fuses_default vega10_fuses_default[] = {
--	{"0000001000010011111010101001010011011110000011100100100101100100",0x00003C96,0xFFFFE226,0x00000656,0x00002203,0xFFFFF201,0x000003FF,0x00002203,0xFFFFF201,0x000003FF},
--	{"0000001000010011111010101001010011011110000010100001100010000100",0x00003CC5,0xFFFFE23A,0x0000064E,0x00002258,0xFFFFF1F7,0x000003FC,0x00002258,0xFFFFF1F7,0x000003FC},
--	{"0000001000010011111010101001010011011110000011100011000110100100",0x00003CAF,0xFFFFE36E,0x00000602,0x00001E98,0xFFFFF569,0x00000357,0x00001E98,0xFFFFF569,0x00000357},
--	{"0000001000010011111010101001010011011110001011000001000101000100",0x0000391A,0xFFFFE548,0x000005C9,0x00001B98,0xFFFFF707,0x00000324,0x00001B98,0xFFFFF707,0x00000324},
--	{"0000001000010011111010101001010011011110001011000001100011000100",0x00003821,0xFFFFE674,0x00000597,0x00002196,0xFFFFF361,0x000003C0,0x00002196,0xFFFFF361,0x000003C0},
--	{"0000001000010011111010101001010011011110001001100011100010000100",0x000044A2,0xFFFFDCB7,0x00000738,0x0000325C,0xFFFFE6A7,0x000005E6,0x0000325C,0xFFFFE6A7,0x000005E6},
--	{"0000001000010011111010101001010011011110000010000010100100100100",0x00004057,0xFFFFE1CF,0x0000063C,0x00002E2E,0xFFFFEB62,0x000004FD,0x00002E2E,0xFFFFEB62,0x000004FD},
--	{"0000001000010011111010101001010011011110001010000100100100100100",0x00003FD0,0xFFFFDF0F,0x000006E5,0x0000267C,0xFFFFEE2D,0x000004AB,0x0000267C,0xFFFFEE2D,0x000004AB},
--	{"0000001000010011111010101001010011011110001010000000100100000100",0x00003F13,0xFFFFE010,0x000006AD,0x000020E7,0xFFFFF266,0x000003EC,0x000020E7,0xFFFFF266,0x000003EC},
--	{"0000001000010011111010101001010011011110000010000010000001000100",0x00004088,0xFFFFDFAB,0x000006B6,0x0000252B,0xFFFFEFDB,0x00000458,0x0000252B,0xFFFFEFDB,0x00000458},
--	{"0000001000010011111010101001010011011110001010000011100010000100",0x00003EF6,0xFFFFE017,0x000006AA,0x00001F67,0xFFFFF369,0x000003BE,0x00001F67,0xFFFFF369,0x000003BE},
--	{"0000001000010011111010101001010011011110001011000010000110000100",0x00003CDD,0xFFFFE2A7,0x0000063C,0x000026C6,0xFFFFEF38,0x00000478,0x000026C6,0xFFFFEF38,0x00000478},
--	{"0000001000010011111010101001010011011110000100000101000100100100",0x00003FA8,0xFFFFDF02,0x000006F0,0x000027FE,0xFFFFECF6,0x000004EA,0x000027FE,0xFFFFECF6,0x000004EA},
--	{"0000001000010011111010101001010011011110001001100011100011000100",0x00004670,0xFFFFDC40,0x00000742,0x00003A7A,0xFFFFE1A7,0x000006B6,0x00003A7A,0xFFFFE1A7,0x000006B6},
--	{"0000001000010011111010101001010011011110001011000011000000100100",0x00003CDC,0xFFFFE18C,0x00000683,0x00002A69,0xFFFFEBE7,0x00000515,0x00002A69,0xFFFFEBE7,0x00000515},
--	{"0000001000010011111010101001010011011110000011100011100011000100",0x00003CEC,0xFFFFE38E,0x00000601,0x00002752,0xFFFFEFA7,0x00000453,0x00002752,0xFFFFEFA7,0x00000453},
--	{"0000001000010011111010101001010011011110001011000001000100100100",0x000037D0,0xFFFFE634,0x000005A7,0x00001CD2,0xFFFFF644,0x00000348,0x00001CD2,0xFFFFF644,0x00000348},
--	{"0000001000010011111010101001010011011110001010000011100101100100",0x00003DF5,0xFFFFE0A5,0x00000698,0x00001FD5,0xFFFFF30E,0x000003D1,0x00001FD5,0xFFFFF30E,0x000003D1},
--	{"0000001000010011111010101001010011011110000010000010100011000100",0x00004201,0xFFFFE03E,0x00000688,0x00003206,0xFFFFE852,0x0000058A,0x00003206,0xFFFFE852,0x0000058A},
--	{"0000001000010011111010101001010011011110001011000001100001100100",0x00003BED,0xFFFFE2F5,0x00000638,0x0000270D,0xFFFFEED0,0x0000048E,0x0000270D,0xFFFFEED0,0x0000048E},
--	{"0000001000010011111010101001010011011110000010100001100100000100",0x00003E82,0xFFFFE1BE,0x00000654,0x000025FB,0xFFFFEFFA,0x00000448,0x000025FB,0xFFFFEFFA,0x00000448},
--	{"0000001000010011111010101001010011011110001011000100000011000100",0x00003962,0xFFFFE4B9,0x000005EF,0x00002385,0xFFFFF156,0x00000423,0x00002385,0xFFFFF156,0x00000423},
--	{"0000001000010011111010101001010011011110001011000000100101000100",0x00003D88,0xFFFFE21A,0x00000655,0x0000295A,0xFFFFED68,0x000004C4,0x0000295A,0xFFFFED68,0x000004C4},
--	{"0000001000010011111010101001010011011110001011000001000100000100",0x00003AA4,0xFFFFE4A3,0x000005E0,0x000022EF,0xFFFFF250,0x000003EB,0x000022EF,0xFFFFF250,0x000003EB},
--	{"0000001000010011111010101001010011011110000011100010100110100100",0x00003D97,0xFFFFE30D,0x0000060D,0x0000205D,0xFFFFF45D,0x00000380,0x0000205D,0xFFFFF45D,0x00000380},
--	{"0000001000010011111010101001010011011110001011000100000010100100",0x000039B6,0xFFFFE446,0x00000605,0x00002325,0xFFFFF16C,0x0000041F,0x00002325,0xFFFFF16C,0x0000041F},
--	{"0000001000010011111010101001010011011110001001100011100100000100",0x0000457E,0xFFFFDCF6,0x00000722,0x00003972,0xFFFFE27B,0x0000068E,0x00003972,0xFFFFE27B,0x0000068E},
--	{"0000001000010011111010101001010011011110000010100001100100100100",0x00003FB8,0xFFFFE101,0x00000670,0x00002787,0xFFFFEEF5,0x00000471,0x00002787,0xFFFFEEF5,0x00000471},
--	{"0000001000010011111010101001010011011110000011100011100010100100",0x00003BB2,0xFFFFE430,0x000005EA,0x000024A5,0xFFFFF162,0x00000409,0x000024A5,0xFFFFF162,0x00000409},
--	{"0000001000010011111010101001010011011110000010000010000101000100",0x00003EC5,0xFFFFE1BD,0x0000064F,0x000022F0,0xFFFFF227,0x000003E8,0x000022F0,0xFFFFF227,0x000003E8},
--	{"0000001000010011111010101001010011011110001011000011000101100100",0x000038A7,0xFFFFE59F,0x000005C1,0x000021CC,0xFFFFF2DF,0x000003D9,0x000021CC,0xFFFFF2DF,0x000003D9},
--	{"0000001000010011111010101001010011011110001100100100000110000100",0x00002995,0xFFFFEF7A,0x0000044C,0x00001552,0xFFFFFB5D,0x00000292,0x00001552,0xFFFFFB5D,0x00000292},
--	{"0000001000010011111010101001010011011110001011000100000001100100",0x00003B26,0xFFFFE2D3,0x00000649,0x000023B4,0xFFFFF09B,0x00000449,0x000023B4,0xFFFFF09B,0x00000449},
--	{"0000001000010011111010101001010011011110000010000001000100100100",0x000040D2,0xFFFFE00A,0x00000696,0x000022DA,0xFFFFF1E9,0x000003F2,0x000022DA,0xFFFFF1E9,0x000003F2},
--	{"0000001000010011111010101001010011011110001011000011100100100100",0x00003C98,0xFFFFE365,0x00000618,0x00002D5D,0xFFFFEB3A,0x0000051D,0x00002D5D,0xFFFFEB3A,0x0000051D},
--	{"0000001000010011111010101001010011011110001011000001000010100100",0x00003BBD,0xFFFFE37E,0x00000617,0x0000252E,0xFFFFF06E,0x00000441,0x0000252E,0xFFFFF06E,0x00000441},
--	{"0000001000010011111010101001010011011110001001100010100100100100",0x00004363,0xFFFFDF7A,0x000006A0,0x000031F5,0xFFFFE880,0x0000057B,0x000031F5,0xFFFFE880,0x0000057B},
--	{"0000001000010011111010101001010011011110000011100011100001000100",0x00003CFC,0xFFFFE2AF,0x0000062E,0x0000212A,0xFFFFF335,0x000003BF,0x0000212A,0xFFFFF335,0x000003BF},
--	{"0000001000010011111010101001010011011110000111000100100100100100",0x0000252D,0xFFFFF31B,0x000003C3,0x00001A1A,0xFFFFF882,0x00000325,0x00001A1A,0xFFFFF882,0x00000325},
--	{"0000001000010011111010101001010011011110000010100010100110100100",0x00003FE2,0xFFFFDFEF,0x000006AC,0x000025A2,0xFFFFEF84,0x00000462,0x000025A2,0xFFFFEF84,0x00000462},
--	{"0000001000010011111010101001010011011110000010000010000011100100",0x000040A5,0xFFFFE13B,0x0000065B,0x00002C13,0xFFFFEC75,0x000004D7,0x00002C13,0xFFFFEC75,0x000004D7},
--	{"0000001000010011111010101001010011011110000011100100100010100100",0x00003E42,0xFFFFE1B3,0x00000657,0x0000221D,0xFFFFF273,0x000003DE,0x0000221D,0xFFFFF273,0x000003DE},
--	{"0000001000010011111010101001010011011110000010100010000011100100",0x00003E7F,0xFFFFE255,0x00000638,0x00002D30,0xFFFFEB8A,0x00000503,0x00002D30,0xFFFFEB8A,0x00000503},
--	{"0000001000010011111010101001010011011110001011000010100111000100",0x00003E56,0xFFFFE16D,0x00000670,0x000028DC,0xFFFFEDA0,0x000004BA,0x000028DC,0xFFFFEDA0,0x000004BA},
--	{"0000001000010011111010101001010011011110001001100011000010100100",0x000044AD,0xFFFFDE24,0x000006DD,0x000031AD,0xFFFFE850,0x00000585,0x000031AD,0xFFFFE850,0x00000585},
--	{"0000001000010011111010101001010011011110001011000010000011100100",0x00003AF3,0xFFFFE5B0,0x000005A6,0x00002CF6,0xFFFFEC75,0x000004DD,0x00002CF6,0xFFFFEC75,0x000004DD},
--	{"0000001000010011111010101001010011011110000010100010000010000100",0x00003E66,0xFFFFE19E,0x0000065B,0x00002332,0xFFFFF1B9,0x000003FD,0x00002332,0xFFFFF1B9,0x000003FD},
--	{"0000001000010011111010101001010011011110000010000010100010000100",0x00003FB4,0xFFFFE0A5,0x00000686,0x0000253E,0xFFFFF02E,0x00000444,0x0000253E,0xFFFFF02E,0x00000444},
--	{"0000001000010011111010101001010011011110001010000001100010100100",0x00003E28,0xFFFFE14D,0x0000066E,0x00001FE2,0xFFFFF39A,0x000003B1,0x00001FE2,0xFFFFF39A,0x000003B1},
--	{"0000001000010011111010101001010011011110001011000000100100000100",0x000039E6,0xFFFFE44B,0x000005FE,0x0000210C,0xFFFFF2F4,0x000003DA,0x0000210C,0xFFFFF2F4,0x000003DA},
--	{"0000001000010011111010101001010011011110001011000101000100000100",0x00003A4D,0xFFFFE252,0x0000067A,0x000027E2,0xFFFFECED,0x000004FA,0x000027E2,0xFFFFECED,0x000004FA},
--	{"0000001000010011111010101001010011011110000010100010100101100100",0x00004065,0xFFFFE02F,0x0000069B,0x0000299D,0xFFFFED38,0x000004C2,0x0000299D,0xFFFFED38,0x000004C2},
--	{"0000001000010011111010101001010011011110000011100010000010100100",0x000039EE,0xFFFFE603,0x00000594,0x0000214F,0xFFFFF429,0x0000038E,0x0000214F,0xFFFFF429,0x0000038E},
--	{"0000001000010011111010101001010011011110000011100100100011100100",0x00003BD2,0xFFFFE351,0x00000618,0x000020B8,0xFFFFF377,0x000003B4,0x000020B8,0xFFFFF377,0x000003B4},
--	{"0000001000010011111010101001010011011110000010100011000100100100",0x00003FAA,0xFFFFE183,0x0000065E,0x000032AE,0xFFFFE7C2,0x000005A6,0x000032AE,0xFFFFE7C2,0x000005A6},
--	{"0000001000010011111010101001010011011110001011000010100110000100",0x00003AFB,0xFFFFE3E4,0x00000608,0x00002293,0xFFFFF21F,0x000003FA,0x00002293,0xFFFFF21F,0x000003FA},
--	{"0000001000010011111010101001010011011110001001100010000001100100",0x0000448B,0xFFFFDD5D,0x0000070D,0x00002E4E,0xFFFFE9DF,0x00000551,0x00002E4E,0xFFFFE9DF,0x00000551},
--	{"0000001000010011111010101001010011011110000011100010000110000100",0x00003D46,0xFFFFE39B,0x000005F3,0x0000218E,0xFFFFF3CD,0x00000398,0x0000218E,0xFFFFF3CD,0x00000398},
--	{"0000001000010011111010101001010011011110000010000100100011100100",0x00003F01,0xFFFFDFD9,0x000006BF,0x000023AF,0xFFFFF04E,0x0000044C,0x000023AF,0xFFFFF04E,0x0000044C},
--	{"0000001000010011111010101001010011011110000100000010100110100100",0x0000403D,0xFFFFDF6B,0x000006C9,0x0000270D,0xFFFFEE4B,0x0000049E,0x0000270D,0xFFFFEE4B,0x0000049E},
--	{"0000001000010011111010101001010011011110000011100011100101100100",0x00003C11,0xFFFFE35C,0x00000613,0x000020F9,0xFFFFF365,0x000003B9,0x000020F9,0xFFFFF365,0x000003B9},
--	{"0000001000010011111010101001010011011110001011000011100010000100",0x00003B58,0xFFFFE37D,0x0000061F,0x00002698,0xFFFFEF46,0x00000478,0x00002698,0xFFFFEF46,0x00000478},
--	{"0000001000010011111010101001010011011110001010000100000110100100",0x00003EBC,0xFFFFDF7A,0x000006D6,0x0000212B,0xFFFFF195,0x0000041B,0x0000212B,0xFFFFF195,0x0000041B},
--	{"0000001000010011111010101001010011011110000010000100100011000100",0x00004050,0xFFFFDEB3,0x000006FE,0x00002D6C,0xFFFFE961,0x00000582,0x00002D6C,0xFFFFE961,0x00000582},
--	{"0000001000010011111010101001010011011110001001100010000001000100",0x000043F0,0xFFFFDD9C,0x00000702,0x00002B31,0xFFFFEBEA,0x000004F7,0x00002B31,0xFFFFEBEA,0x000004F7},
--	{"0000001000010011111010101001010011011110000100000000100100100100",0x00003EFA,0xFFFFE093,0x00000696,0x000026DB,0xFFFFEEB3,0x00000489,0x000026DB,0xFFFFEEB3,0x00000489},
--	{"0000001000010011111010101001010011011110000010000010000001100100",0x0000425D,0xFFFFDE8D,0x000006E6,0x00002CA4,0xFFFFEAD2,0x00000531,0x00002CA4,0xFFFFEAD2,0x00000531},
--	{"0000001000010011111010101001010011011110001001100011100110100100",0x000043B0,0xFFFFDD03,0x00000728,0x00002946,0xFFFFECA6,0x000004DE,0x00002946,0xFFFFECA6,0x000004DE},
--	{"0000001000010011111010101001010011011110001010000010100001100100",0x00003F6A,0xFFFFE03A,0x0000069D,0x00002208,0xFFFFF1F8,0x000003F6,0x00002208,0xFFFFF1F8,0x000003F6},
--	{"0000001000010011111010101001010011011110001011000010100101100100",0x00003A94,0xFFFFE4A7,0x000005E2,0x000024D0,0xFFFFF100,0x00000426,0x000024D0,0xFFFFF100,0x00000426},
--	{"0000001000010011111010101001010011011110001010000001000011000100",0x00003F2F,0xFFFFE0A3,0x00000688,0x00002198,0xFFFFF271,0x000003E2,0x00002198,0xFFFFF271,0x000003E2},
--	{"0000001000010011111010101001010011011110000100000100100011100100",0x00003EA5,0xFFFFE032,0x000006AE,0x0000227C,0xFFFFF130,0x00000426,0x0000227C,0xFFFFF130,0x00000426},
--	{"0000001000010011111010101001010011011110001001100100000101000100",0x0000442F,0xFFFFDBC4,0x0000078B,0x00003CD6,0xFFFFDE6C,0x0000076C,0x00003CD6,0xFFFFDE6C,0x0000076C},
--	{"0000001000010011111010101001010011011110001010000010100010000100",0x00003DDE,0xFFFFE174,0x00000668,0x00001FF4,0xFFFFF38F,0x000003B1,0x00001FF4,0xFFFFF38F,0x000003B1},
--	{"0000001000010011111010101001010011011110000010100011000101000100",0x000040B0,0xFFFFE016,0x000006A0,0x00002DBB,0xFFFFEA7F,0x00000537,0x00002DBB,0xFFFFEA7F,0x00000537},
--	{"0000001000010011111010101001010011011110001011000011000100000100",0x00003429,0xFFFFEA97,0x000004DD,0x000024D5,0xFFFFF26F,0x000003DF,0x000024D5,0xFFFFF26F,0x000003DF},
--	{"0000001000010011111010101001010011011110000011100001100100000100",0x00003AEB,0xFFFFE590,0x000005A3,0x000022CB,0xFFFFF347,0x000003B2,0x000022CB,0xFFFFF347,0x000003B2},
--	{"0000001000010011111010101001010011011110001010000011100100000100",0x00003B8E,0xFFFFE2EF,0x00000636,0x00002351,0xFFFFF143,0x0000041C,0x00002351,0xFFFFF143,0x0000041C},
--	{"0000001000010011111010101001010011011110001100100100000011000100",0x00002926,0xFFFFF0B0,0x00000410,0x0000194E,0xFFFFF94E,0x000002E9,0x0000194E,0xFFFFF94E,0x000002E9},
--	{"0000001000010011111010101001010011011110001010000011000110000100",0x0000402B,0xFFFFDF78,0x000006C2,0x00002273,0xFFFFF16C,0x00000414,0x00002273,0xFFFFF16C,0x00000414},
--	{"0000001000010011111010101001010011011110000010100001000010100100",0x00003D6A,0xFFFFE1D3,0x00000659,0x00002006,0xFFFFF394,0x000003B1,0x00002006,0xFFFFF394,0x000003B1},
--	{"0000001000010011111010101001010011011110001010000100000001100100",0x00004042,0xFFFFDFD8,0x000006A8,0x00002135,0xFFFFF29F,0x000003D9,0x00002135,0xFFFFF29F,0x000003D9},
--	{"0000001000010011111010101001010011011110000010000010000010100100",0x0000405B,0xFFFFE093,0x00000682,0x0000288F,0xFFFFEE3A,0x00000491,0x0000288F,0xFFFFEE3A,0x00000491},
--	{"0000001000010011111010101001010011011110001011000100100010100100",0x00003A49,0xFFFFE30C,0x00000648,0x000023F9,0xFFFFF02D,0x00000460,0x000023F9,0xFFFFF02D,0x00000460},
--	{"0000001000010011111010101001010011011110001010000010100101100100",0x00003D59,0xFFFFE1CC,0x0000065B,0x00002013,0xFFFFF37D,0x000003B6,0x00002013,0xFFFFF37D,0x000003B6},
--	{"0000001000010011111010101001010011011110001011000011100110000100",0x000040C1,0xFFFFDF8C,0x000006CA,0x00003271,0xFFFFE6CA,0x000005EA,0x00003271,0xFFFFE6CA,0x000005EA},
--	{"0000001000010011111010101001010011011110001001100010000011100100",0x000042E9,0xFFFFDFDC,0x0000068C,0x00002ED9,0xFFFFEAAF,0x0000051B,0x00002ED9,0xFFFFEAAF,0x0000051B},
--	{"0000001000010011111010101001010011011110000010000011000010000100",0x000042ED,0xFFFFDE50,0x000006F0,0x00002FCF,0xFFFFE8BB,0x0000058C,0x00002FCF,0xFFFFE8BB,0x0000058C},
--	{"0000001000010011111010101001010011011110000010100100000100000100",0x00003EBD,0xFFFFE099,0x00000698,0x00002709,0xFFFFEE7B,0x00000495,0x00002709,0xFFFFEE7B,0x00000495},
--	{"0000001000010011111010101001010011011110001010000100100100000100",0x00003F71,0xFFFFDF82,0x000006C9,0x0000219B,0xFFFFF1AD,0x0000040F,0x0000219B,0xFFFFF1AD,0x0000040F},
--	{"0000001000010011111010101001010011011110001010000000100011100100",0x00003E73,0xFFFFE080,0x0000069B,0x000020E7,0xFFFFF273,0x000003E9,0x000020E7,0xFFFFF273,0x000003E9},
--	{"0000001000010011111010101001010011011110000011100011000110000100",0x00003E14,0xFFFFE278,0x0000062C,0x00002275,0xFFFFF2B3,0x000003CE,0x00002275,0xFFFFF2B3,0x000003CE},
--	{"0000001000010011111010101001010011011110001011000010000110100100",0x00003ABB,0xFFFFE3B9,0x00000615,0x00002192,0xFFFFF28F,0x000003EB,0x00002192,0xFFFFF28F,0x000003EB},
--	{"0000001000010011111010101001010011011110001010000011000100100100",0x00003D53,0xFFFFE255,0x00000643,0x0000275B,0xFFFFEEED,0x00000479,0x0000275B,0xFFFFEEED,0x00000479},
--	{"0000001000010011111010101001010011011110001001100010100001100100",0x000043E3,0xFFFFDDC3,0x000006FB,0x00002B6B,0xFFFFEBD6,0x000004FA,0x00002B6B,0xFFFFEBD6,0x000004FA},
--	{"0000001000010011111010101001010011011110000011100010000101000100",0x00003BDE,0xFFFFE507,0x000005B4,0x000022CE,0xFFFFF358,0x000003AB,0x000022CE,0xFFFFF358,0x000003AB},
--	{"0000001000010011111010101001010011011110001100100011000101100100",0x00002460,0xFFFFF3B5,0x000003A2,0x000014E7,0xFFFFFC32,0x0000027C,0x000014E7,0xFFFFFC32,0x0000027C},
--	{"0000001000010011111010101001010011011110001010000010000011000100",0x00003D20,0xFFFFE298,0x0000062F,0x00002080,0xFFFFF3AF,0x000003A8,0x00002080,0xFFFFF3AF,0x000003A8},
--	{"0000001000010011111010101001010011011110000010000001100100000100",0x00003E14,0xFFFFE221,0x00000641,0x000021BB,0xFFFFF2EA,0x000003CA,0x000021BB,0xFFFFF2EA,0x000003CA},
--	{"0000001000010011111010101001010011011110000010100100000011000100",0x00003DE1,0xFFFFE14E,0x00000677,0x00002468,0xFFFFF068,0x00000440,0x00002468,0xFFFFF068,0x00000440},
--	{"0000001000010011111010101001010011011110001001100001000010000100",0x00004372,0xFFFFDDF8,0x000006F5,0x00002B3F,0xFFFFEBE8,0x000004F8,0x00002B3F,0xFFFFEBE8,0x000004F8},
--	{"0000001000010011111010101001010011011110000010100010100011000100",0x00003E4F,0xFFFFE2A3,0x0000062B,0x00002F5A,0xFFFFEA37,0x0000053B,0x00002F5A,0xFFFFEA37,0x0000053B},
--	{"0000001000010011111010101001010011011110001010000101000011100100",0x00003E07,0xFFFFE02F,0x000006B6,0x0000216B,0xFFFFF1A3,0x00000416,0x0000216B,0xFFFFF1A3,0x00000416},
--	{"0000001000010011111010101001010011011110001010000011100010100100",0x00003DAB,0xFFFFE128,0x0000067F,0x0000216F,0xFFFFF236,0x000003F3,0x0000216F,0xFFFFF236,0x000003F3},
--	{"0000001000010011111010101001010011011110001011000010100100100100",0x0000364B,0xFFFFE8CB,0x0000052A,0x00002568,0xFFFFF1B2,0x00000400,0x00002568,0xFFFFF1B2,0x00000400},
--	{"0000001000010011111010101001010011011110001001100001000001100100",0x00004219,0xFFFFDE87,0x000006E8,0x00002C59,0xFFFFEAEE,0x00000529,0x00002C59,0xFFFFEAEE,0x00000529},
--	{"0000001000010011111010101001010011011110000011100001100101000100",0x000039A8,0xFFFFE602,0x00000594,0x00001D06,0xFFFFF6F0,0x00000316,0x00001D06,0xFFFFF6F0,0x00000316},
--	{"0000001000010011111010101001010011011110001001100001000011100100",0x00004052,0xFFFFE01C,0x00000698,0x00002310,0xFFFFF1A1,0x000003FE,0x00002310,0xFFFFF1A1,0x000003FE},
--	{"0000001000010011111010101001010011011110000011100010100000100100",0x00003C1C,0xFFFFE3EB,0x000005F1,0x00002289,0xFFFFF2CF,0x000003C9,0x00002289,0xFFFFF2CF,0x000003C9},
--	{"0000001000010011111010101001010011011110000011100101000100100100",0x00003F19,0xFFFFE085,0x0000069E,0x00002B94,0xFFFFEB72,0x0000051D,0x00002B94,0xFFFFEB72,0x0000051D},
--	{"0000001000010011111010101001010011011110000011100100000110100100",0x00003C51,0xFFFFE2AD,0x00000638,0x0000206B,0xFFFFF361,0x000003BE,0x0000206B,0xFFFFF361,0x000003BE},
--	{"0000001000010011111010101001010011011110001001100001000011000100",0x000040B9,0xFFFFDFBB,0x000006AB,0x0000241F,0xFFFFF0CC,0x00000425,0x0000241F,0xFFFFF0CC,0x00000425},
--	{"0000001000010011111010101001010011011110000010100010000001100100",0x00003E62,0xFFFFE12C,0x00000678,0x00002445,0xFFFFF09E,0x00000435,0x00002445,0xFFFFF09E,0x00000435},
--	{"0000001000010011111010101001010011011110000011100001100110000100",0x00003C97,0xFFFFE399,0x000005FB,0x0000209D,0xFFFFF41D,0x0000038F,0x0000209D,0xFFFFF41D,0x0000038F},
--	{"0000001000010011111010101001010011011110000011100011000101000100",0x00003FF9,0xFFFFE1E9,0x0000063E,0x00002E96,0xFFFFEAF5,0x00000516,0x00002E96,0xFFFFEAF5,0x00000516},
--	{"0000001000010011111010101001010011011110000010100011000010000100",0x00003F04,0xFFFFE109,0x0000067A,0x000026E1,0xFFFFEF0B,0x00000476,0x000026E1,0xFFFFEF0B,0x00000476},
--	{"0000001000010011111010101001010011011110000100000001000100100100",0x00003E3E,0xFFFFE187,0x00000660,0x00002049,0xFFFFF38D,0x000003B0,0x00002049,0xFFFFF38D,0x000003B0},
--	{"0000001000010011111010101001010011011110001010000010100101000100",0x00003D58,0xFFFFE253,0x0000063D,0x00002158,0xFFFFF308,0x000003C3,0x00002158,0xFFFFF308,0x000003C3},
--	{"0000001000010011111010101001010011011110000010000100000011000100",0x00004074,0xFFFFDF8D,0x000006C0,0x00002799,0xFFFFEE19,0x000004A5,0x00002799,0xFFFFEE19,0x000004A5},
--	{"0000001000010011111010101001010011011110001010000001100100100100",0x00003DAF,0xFFFFE1C9,0x00000659,0x000020E5,0xFFFFF313,0x000003C6,0x000020E5,0xFFFFF313,0x000003C6},
--	{"0000001000010011111010101001010011011110000010100011100101100100",0x000041DD,0xFFFFDDFA,0x0000071B,0x0000348D,0xFFFFE4B4,0x0000064C,0x0000348D,0xFFFFE4B4,0x0000064C},
--	{"0000001000010011111010101001010011011110001011000010100010000100",0x00003947,0xFFFFE5AE,0x000005B8,0x000024A6,0xFFFFF140,0x0000041D,0x000024A6,0xFFFFF140,0x0000041D},
--	{"0000001000010011111010101001010011011110000100000001100001000100",0x00003D35,0xFFFFE197,0x0000066E,0x00002248,0xFFFFF1BC,0x00000408,0x00002248,0xFFFFF1BC,0x00000408},
--	{"0000001000010011111010101001010011011110000010100001100011100100",0x00003F4F,0xFFFFE13E,0x0000066D,0x00002AF0,0xFFFFEC99,0x000004DB,0x00002AF0,0xFFFFEC99,0x000004DB},
--	{"0000001000010011111010101001010011011110001001100011100101000100",0x0000430F,0xFFFFDDFB,0x000006FC,0x00002D4D,0xFFFFEA55,0x00000540,0x00002D4D,0xFFFFEA55,0x00000540},
--	{"0000001000010011111010101001010011011110000011100010100101000100",0x00003B22,0xFFFFE543,0x000005B1,0x000022E1,0xFFFFF31B,0x000003B9,0x000022E1,0xFFFFF31B,0x000003B9},
--	{"0000001000010011111010101001010011011110000011100010000010000100",0x00003978,0xFFFFE611,0x00000592,0x00001C36,0xFFFFF771,0x00000302,0x00001C36,0xFFFFF771,0x00000302},
--	{"0000001000010011111010101001010011011110001001100010000101100100",0x000044DF,0xFFFFDDAB,0x000006F2,0x00002CEA,0xFFFFEB47,0x00000507,0x00002CEA,0xFFFFEB47,0x00000507},
--	{"0000001000010011111010101001010011011110000010100011100011000100",0x00003E9B,0xFFFFE12C,0x0000067C,0x00002B79,0xFFFFEBD9,0x00000503,0x00002B79,0xFFFFEBD9,0x00000503},
--	{"0000001000010011111010101001010011011110001001100011000001000100",0x00004464,0xFFFFDCD3,0x00000731,0x00002D14,0xFFFFEA2D,0x0000054E,0x00002D14,0xFFFFEA2D,0x0000054E},
--	{"0000001000010011111010101001010011011110001010000001000100100100",0x00003FB3,0xFFFFE052,0x00000693,0x000020AC,0xFFFFF311,0x000003C6,0x000020AC,0xFFFFF311,0x000003C6},
--	{"0000001000010011111010101001010011011110001011000001000010000100",0x00003BDA,0xFFFFE2FB,0x00000636,0x0000261E,0xFFFFEF72,0x00000471,0x0000261E,0xFFFFEF72,0x00000471},
--	{"0000001000010011111010101001010011011110001011000001100101100100",0x00003D72,0xFFFFE28A,0x0000063E,0x000029D8,0xFFFFED54,0x000004C7,0x000029D8,0xFFFFED54,0x000004C7},
--	{"0000001000010011111010101001010011011110001011000010100000100100",0x00003E26,0xFFFFE102,0x00000694,0x00002DD1,0xFFFFE9CA,0x0000056D,0x00002DD1,0xFFFFE9CA,0x0000056D},
--	{"0000001000010011111010101001010011011110000100000100000100100100",0x000041CD,0xFFFFDE97,0x000006ED,0x00002DE5,0xFFFFE9B9,0x00000565,0x00002DE5,0xFFFFE9B9,0x00000565},
--	{"0000001000010011111010101001010011011110000010100010100110000100",0x00003F30,0xFFFFE06E,0x00000698,0x000024FF,0xFFFFEFFC,0x0000044F,0x000024FF,0xFFFFEFFC,0x0000044F},
--	{"0000001000010011111010101001010011011110001011000011100011000100",0x0000378B,0xFFFFE6B4,0x00000594,0x000023A7,0xFFFFF1DC,0x00000407,0x000023A7,0xFFFFF1DC,0x00000407},
--	{"0000001000010011111010101001010011011110000011100100000101100100",0x00003CD7,0xFFFFE28D,0x00000636,0x00002036,0xFFFFF3B5,0x000003AA,0x00002036,0xFFFFF3B5,0x000003AA},
--	{"0000001000010011111010101001010011011110000010100011100010000100",0x00003EF9,0xFFFFE0AA,0x0000068D,0x000024D3,0xFFFFF02F,0x00000445,0x000024D3,0xFFFFF02F,0x00000445},
--	{"0000001000010011111010101001010011011110001010000011100101000100",0x00003D08,0xFFFFE1BB,0x00000665,0x00002159,0xFFFFF26F,0x000003E6,0x00002159,0xFFFFF26F,0x000003E6},
--	{"0000001000010011111010101001010011011110001011000010000011000100",0x000038A9,0xFFFFE6CA,0x00000580,0x000025D3,0xFFFFF101,0x00000421,0x000025D3,0xFFFFF101,0x00000421},
--	{"0000001000010011111010101001010011011110000010100010000010100100",0x00003E45,0xFFFFE1F8,0x0000064D,0x000027E3,0xFFFFEEBB,0x0000047F,0x000027E3,0xFFFFEEBB,0x0000047F},
--	{"0000001000010011111010101001010011011110000011100011100001100100",0x00003F76,0xFFFFE128,0x0000066E,0x0000286B,0xFFFFEE4C,0x00000493,0x0000286B,0xFFFFEE4C,0x00000493},
--	{"0000001000010011111010101001010011011110001001100100000100000100",0x0000440D,0xFFFFDCA2,0x0000074F,0x00003817,0xFFFFE256,0x000006AF,0x00003817,0xFFFFE256,0x000006AF},
--	{"0000001000010011111010101001010011011110000100000101000100000100",0x00003EE1,0xFFFFDFA7,0x000006D4,0x000027EA,0xFFFFED2B,0x000004DE,0x000027EA,0xFFFFED2B,0x000004DE},
--	{"0000001000010011111010101001010011011110001011000011100001100100",0x00003C62,0xFFFFE285,0x0000064A,0x00002520,0xFFFFF001,0x0000045C,0x00002520,0xFFFFF001,0x0000045C},
--	{"0000001000010011111010101001010011011110001100100011100101100100",0x0000272E,0xFFFFF17A,0x000003FA,0x0000150B,0xFFFFFBD5,0x00000284,0x0000150B,0xFFFFFBD5,0x00000284},
--	{"0000001000010011111010101001010011011110001001100001100100100100",0x00004275,0xFFFFDF69,0x000006A5,0x000025AA,0xFFFFF05C,0x0000042B,0x000025AA,0xFFFFF05C,0x0000042B},
--	{"0000001000010011111010101001010011011110000011100100000011100100",0x00003CAA,0xFFFFE392,0x000005FF,0x000023A8,0xFFFFF20E,0x000003E9,0x000023A8,0xFFFFF20E,0x000003E9},
--	{"0000001000010011111010101001010011011110001011000101000011000100",0x00003CF8,0xFFFFE0FB,0x000006A6,0x00002CA7,0xFFFFE9FF,0x0000056E,0x00002CA7,0xFFFFE9FF,0x0000056E},
--	{"0000001000010011111010101001010011011110001010000010000100100100",0x00003D00,0xFFFFE296,0x00000633,0x000021C1,0xFFFFF2C8,0x000003CF,0x000021C1,0xFFFFF2C8,0x000003CF},
--	{"0000001000010011111010101001010011011110001010000011100011100100",0x00003B46,0xFFFFE301,0x00000632,0x0000204C,0xFFFFF33B,0x000003C8,0x0000204C,0xFFFFF33B,0x000003C8},
--	{"0000001000010011111010101001010011011110001000000100000101100100",0x00002026,0xFFFFF5CE,0x00000368,0x00001598,0xFFFFFB29,0x000002C3,0x00001598,0xFFFFFB29,0x000002C3},
--	{"0000001000010011111010101001010011011110001010000011000101100100",0x00003DCA,0xFFFFE178,0x00000668,0x00001FDB,0xFFFFF39D,0x000003AF,0x00001FDB,0xFFFFF39D,0x000003AF},
--	{"0000001000010011111010101001010011011110001011000100100011000100",0x00003A59,0xFFFFE327,0x00000642,0x000024B9,0xFFFFEFC4,0x00000471,0x000024B9,0xFFFFEFC4,0x00000471},
--	{"0000001000010011111010101001010011011110001011000010100101000100",0x00003C26,0xFFFFE440,0x000005EB,0x00002C0F,0xFFFFEC88,0x000004E0,0x00002C0F,0xFFFFEC88,0x000004E0},
--	{"0000001000010011111010101001010011011110000010000011100010000100",0x00004149,0xFFFFDEB8,0x000006E7,0x0000280A,0xFFFFED89,0x000004C2,0x0000280A,0xFFFFED89,0x000004C2},
--	{"0000001000010011111010101001010011011110000011100100000100100100",0x00003EB4,0xFFFFE1E5,0x0000064D,0x0000299F,0xFFFFEDB3,0x000004A9,0x0000299F,0xFFFFEDB3,0x000004A9},
--	{"0000001000010011111010101001010011011110001011000011100110100100",0x00003BBF,0xFFFFE268,0x0000065A,0x00002504,0xFFFFEFB0,0x00000470,0x00002504,0xFFFFEFB0,0x00000470},
--	{"0000001000010011111010101001010011011110000010000100100100000100",0x00004203,0xFFFFDDC6,0x00000720,0x0000303B,0xFFFFE78F,0x000005D0,0x0000303B,0xFFFFE78F,0x000005D0},
--	{"0000001000010011111010101001010011011110000011100011100110000100",0x00003DA3,0xFFFFE244,0x0000063E,0x000021B4,0xFFFFF2DA,0x000003CD,0x000021B4,0xFFFFF2DA,0x000003CD},
--	{"0000001000010011111010101001010011011110000010100011100011100100",0x00004035,0xFFFFE065,0x0000069B,0x00003323,0xFFFFE6D6,0x000005D8,0x00003323,0xFFFFE6D6,0x000005D8},
--	{"0000001000010011111010101001010011011110001011000001000101100100",0x00003944,0xFFFFE4E5,0x000005E2,0x00001F3C,0xFFFFF456,0x0000039D,0x00001F3C,0xFFFFF456,0x0000039D},
--	{"0000001000010011111010101001010011011110000001100001100100000100",0x000032D8,0xFFFFEAE8,0x000004E6,0x00001812,0xFFFFFA1C,0x000002BC,0x00001812,0xFFFFFA1C,0x000002BC},
--	{"0000001000010011111100001111110101000010110100100010100101000100",0x000041F6,0xFFFFE025,0x0000069A,0x0000241E,0xFFFFF1B4,0x00000402,0x0000241E,0xFFFFF1B4,0x00000402},
--	{"0000001000010011111100001111111010011001000011000011000010100100",0x00003300,0xFFFFEB60,0x000004C1,0x00001E15,0xFFFFF6A6,0x0000033B,0x00001E15,0xFFFFF6A6,0x0000033B},
--	{"0000001000010011111010101001010011011110000001000000100010100100",0x000037F0,0xFFFFE68F,0x0000059B,0x00001F8A,0xFFFFF467,0x000003A3,0x00001F8A,0xFFFFF467,0x000003A3},
--	{"0000001000010011111100001111111010011001000110000010100110000100",0x000025D8,0xFFFFF2AA,0x000003C3,0x000018A8,0xFFFFF9BE,0x000002D2,0x000018A8,0xFFFFF9BE,0x000002D2},
--	{"0000001000010011111100001111111010011001000001100010000011000100",0x0000364F,0xFFFFE988,0x000004FC,0x00001E51,0xFFFFF633,0x0000034F,0x00001E51,0xFFFFF633,0x0000034F},
--	{"0000001000010011111010101001010011011110000001100001000101000100",0x00002288,0xFFFFF483,0x0000036C,0x0000280F,0xFFFFEF39,0x0000047B,0x0000280F,0xFFFFEF39,0x0000047B},
--	{"0000001000010011111100001111111010011001000010000010000010000100",0x00003322,0xFFFFEA7E,0x000004ED,0x00001DAD,0xFFFFF62B,0x00000355,0x00001DAD,0xFFFFF62B,0x00000355},
--	{"0000001000010011111010101001010011011110000000100101000011100100",0x00002B7B,0xFFFFEE4F,0x0000045B,0x00001AA2,0xFFFFF710,0x0000033E,0x00001AA2,0xFFFFF710,0x0000033E},
--	{"0000001000010011111100001111111010011001000001000010000011000100",0x000034CC,0xFFFFEA79,0x000004E4,0x00001B05,0xFFFFF8B3,0x000002EC,0x00001B05,0xFFFFF8B3,0x000002EC},
--	{"0000001000010011111100001111110101000010110111000010100001100100",0x00003837,0xFFFFE5ED,0x000005C3,0x00001ACB,0xFFFFF7B2,0x00000314,0x00001ACB,0xFFFFF7B2,0x00000314},
--	{"0000001000010011111100001111111010011001000001000100000101100100",0x0000352D,0xFFFFE88F,0x00000548,0x000021E6,0xFFFFF3B5,0x000003AA,0x000021E6,0xFFFFF3B5,0x000003AA},
--	{"0000001000010011111100001111111010011001000010100100100010000100",0x00003300,0xFFFFE835,0x0000057B,0x00001A85,0xFFFFF715,0x00000336,0x00001A85,0xFFFFF715,0x00000336},
--	{"0000001000010011111010101001010011011110000001000100100010100100",0x000033FA,0xFFFFE851,0x00000565,0x00001A8E,0xFFFFF727,0x0000033B,0x00001A8E,0xFFFFF727,0x0000033B},
--	{"0000001000010011111100001111110101000010110110100011100100100100",0x000039D3,0xFFFFE5D3,0x000005B0,0x00001888,0xFFFFF978,0x000002C8,0x00001888,0xFFFFF978,0x000002C8},
--	{"0000001000010011111100001111111010011001000011100100100001100100",0x00002F6B,0xFFFFEC53,0x000004B9,0x00001C15,0xFFFFF71B,0x00000337,0x00001C15,0xFFFFF71B,0x00000337},
--	{"0000001000010011111100001111111010011001000001100100000101000100",0x0000384D,0xFFFFE737,0x00000569,0x00001D2D,0xFFFFF673,0x00000343,0x00001D2D,0xFFFFF673,0x00000343},
--	{"0000001000010011111100001111111010011001000001100010000010100100",0x00003A49,0xFFFFE70B,0x0000055F,0x00001A63,0xFFFFF8CD,0x000002E2,0x00001A63,0xFFFFF8CD,0x000002E2},
--	{"0000001000010011111100001111111010011001000001000010100110000100",0x0000311E,0xFFFFEB97,0x000004C6,0x00001EAE,0xFFFFF5A9,0x00000367,0x00001EAE,0xFFFFF5A9,0x00000367},
--	{"0000001000010011111100001111111010011001000011100001000100100100",0x000027D3,0xFFFFF075,0x00000417,0x00002001,0xFFFFF44A,0x000003A2,0x00002001,0xFFFFF44A,0x000003A2},
--	{"0000001000010011111100001111111010011001000001100100100100000100",0x00003B72,0xFFFFE4BD,0x000005DC,0x00001D76,0xFFFFF606,0x0000035A,0x00001D76,0xFFFFF606,0x0000035A},
--	{"0000001000010011111100001111111010011001000100000001000100100100",0x00002E0F,0xFFFFECA7,0x000004AE,0x00001DC6,0xFFFFF5BF,0x0000036A,0x00001DC6,0xFFFFF5BF,0x0000036A},
--	{"0000001000010011111100001111111010011001000000100011100010100100",0x000032C7,0xFFFFEA7A,0x000004F0,0x00001A7B,0xFFFFF827,0x00000301,0x00001A7B,0xFFFFF827,0x00000301},
--	{"0000001000010011111010101001010011011110000001000100100010000100",0x0000312D,0xFFFFEA39,0x00000515,0x00001948,0xFFFFF800,0x00000318,0x00001948,0xFFFFF800,0x00000318},
--	{"0000001000010011111010101001010011011110000001100010000010000100",0x00003611,0xFFFFE8D7,0x00000533,0x00001929,0xFFFFF965,0x000002D2,0x00001929,0xFFFFF965,0x000002D2},
--	{"0000001000010011111100001111111010011001001011000011000011100100",0x00002FE2,0xFFFFED89,0x00000470,0x00001A3C,0xFFFFF955,0x000002D5,0x00001A3C,0xFFFFF955,0x000002D5},
--	{"0000001000010011111010101001010011011110000000100000100010100100",0x000035FF,0xFFFFE884,0x00000548,0x0000182A,0xFFFFF9AB,0x000002CF,0x0000182A,0xFFFFF9AB,0x000002CF},
--	{"0000001000010011111100001111111010011001000000100010000011100100",0x00003597,0xFFFFE904,0x00000528,0x00001A94,0xFFFFF840,0x00000300,0x00001A94,0xFFFFF840,0x00000300},
--	{"0000001000010011111100001111111010011001000110000001100101000100",0x000026CB,0xFFFFF1FB,0x000003E4,0x000017CC,0xFFFFFA25,0x000002C8,0x000017CC,0xFFFFFA25,0x000002C8},
--	{"0000001000010011111010101001010011011110000001100000100011000100",0x00003274,0xFFFFEA39,0x0000050C,0x00001B20,0xFFFFF7C1,0x00000314,0x00001B20,0xFFFFF7C1,0x00000314},
--	{"0000001000010011111100001111110101000010110110000010100100100100",0x0000280B,0xFFFFF283,0x000003B5,0x000018D0,0xFFFFF992,0x000002EC,0x000018D0,0xFFFFF992,0x000002EC},
--	{"0000001000010011111100001111111010011001000001100010000100000100",0x000033AB,0xFFFFEB1B,0x000004C4,0x00001FEE,0xFFFFF53A,0x00000378,0x00001FEE,0xFFFFF53A,0x00000378},
--	{"0000001000010011111100001111111010011001000010100011100101100100",0x00002F79,0xFFFFEB0C,0x000004FA,0x00001E57,0xFFFFF4BF,0x0000039B,0x00001E57,0xFFFFF4BF,0x0000039B},
--	{"0000001000010011111100001111111010011001000001000100100011100100",0x00003487,0xFFFFE8F2,0x00000539,0x0000185B,0xFFFFF9AE,0x000002BA,0x0000185B,0xFFFFF9AE,0x000002BA},
--	{"0000001000010011111100001111111010011001000010100001100010100100",0x00003500,0xFFFFE793,0x0000058A,0x00001AA2,0xFFFFF792,0x0000031D,0x00001AA2,0xFFFFF792,0x0000031D},
--	{"0000001000010011111100001111111010011001000010000001000101100100",0x00003943,0xFFFFE54D,0x000005D9,0x00001BC8,0xFFFFF6E0,0x00000339,0x00001BC8,0xFFFFF6E0,0x00000339},
--	{"0000001000010011111010101001010011011110000001000011000010100100",0x0000306D,0xFFFFEC5E,0x000004A5,0x00001A3A,0xFFFFF85F,0x00000304,0x00001A3A,0xFFFFF85F,0x00000304},
--	{"0000001000010011111100001111110101000010110110000011000010000100",0x00002BA4,0xFFFFEE8D,0x0000046A,0x0000198C,0xFFFFF88E,0x00000307,0x0000198C,0xFFFFF88E,0x00000307},
--	{"0000001000010011111100001111110101000010110100100001100011100100",0x00003D30,0xFFFFE2F6,0x0000062A,0x000025DC,0xFFFFF074,0x00000435,0x000025DC,0xFFFFF074,0x00000435},
--	{"0000001000010011111100001111110101000010110110000011100101100100",0x00002CD6,0xFFFFED79,0x0000049B,0x000016D0,0xFFFFFA53,0x000002BB,0x000016D0,0xFFFFFA53,0x000002BB},
--	{"0000001000010011111100001111111010011001000101100011000101100100",0x00002484,0xFFFFF3BD,0x000003A0,0x000015B8,0xFFFFFB6B,0x000002A4,0x000015B8,0xFFFFFB6B,0x000002A4},
--	{"0000001000010011111100001111111010011001000011100011100101000100",0x000038AE,0xFFFFE6D1,0x00000587,0x00001A2A,0xFFFFF8F1,0x000002D4,0x00001A2A,0xFFFFF8F1,0x000002D4},
--	{"0000001000010011111100001111111010011001000001000100100101000100",0x000036FD,0xFFFFE76C,0x00000576,0x00001EE4,0xFFFFF58D,0x00000361,0x00001EE4,0xFFFFF58D,0x00000361},
--	{"0000001000010011111100001111110101000010110110000011000010100100",0x00002BCF,0xFFFFEF28,0x00000448,0x00001B93,0xFFFFF7BA,0x00000327,0x00001B93,0xFFFFF7BA,0x00000327},
--	{"0000001000010011111100001111111010011001000001100010100010000100",0x00003834,0xFFFFE818,0x0000053B,0x00001AFE,0xFFFFF85C,0x000002F3,0x00001AFE,0xFFFFF85C,0x000002F3},
--	{"0000001000010011111100001111111010011001001100100011000110100100",0x00002EF7,0xFFFFEBFC,0x000004CE,0x00001897,0xFFFFF8EF,0x000002EC,0x00001897,0xFFFFF8EF,0x000002EC},
--	{"0000001000010011111100001111111010011001001011000001100011000100",0x000035BD,0xFFFFE8BB,0x0000053B,0x00001F22,0xFFFFF561,0x00000373,0x00001F22,0xFFFFF561,0x00000373},
--	{"0000001000010011111100001111111010011001000110000011100110000100",0x00002D42,0xFFFFEE1D,0x00000478,0x000016F0,0xFFFFFAAE,0x000002B3,0x000016F0,0xFFFFFAAE,0x000002B3},
--	{"0000001000010011111010101001010011011110000001000101000100100100",0x00002F98,0xFFFFEB3C,0x000004F0,0x00001903,0xFFFFF818,0x00000319,0x00001903,0xFFFFF818,0x00000319},
--	{"0000001000010011111100001111110101000010110101000010000101000100",0x00004081,0xFFFFDF13,0x000006F3,0x00002A6D,0xFFFFEC1B,0x00000509,0x00002A6D,0xFFFFEC1B,0x00000509},
--	{"0000001000010011111010101001010011011110000001000000100100000100",0x00002D68,0xFFFFED21,0x00000498,0x00001FF6,0xFFFFF427,0x000003B0,0x00001FF6,0xFFFFF427,0x000003B0},
--	{"0000001000010011111100001111111010011001000000100011100010000100",0x00003243,0xFFFFEA5C,0x000004FD,0x000020FB,0xFFFFF39E,0x000003C0,0x000020FB,0xFFFFF39E,0x000003C0},
--	{"0000001000010011111100001111110101000010110110000100100010100100",0x00002F20,0xFFFFEC19,0x000004C6,0x00001748,0xFFFFF99F,0x000002DA,0x00001748,0xFFFFF99F,0x000002DA},
--	{"0000001000010011111100001111111010011001000100000011100110000100",0x00002D68,0xFFFFED21,0x00000498,0x00001A43,0xFFFFF843,0x000002F9,0x00001A43,0xFFFFF843,0x000002F9},
--	{"0000001000010011111100001111111010011001000000100010000010100100",0x0000396E,0xFFFFE616,0x000005A9,0x00001A51,0xFFFFF850,0x000002FA,0x00001A51,0xFFFFF850,0x000002FA},
--	{"0000001000010011111100001111111010011001000001000011000101000100",0x0000305C,0xFFFFED4B,0x0000046C,0x00001CF9,0xFFFFF7BA,0x00000304,0x00001CF9,0xFFFFF7BA,0x00000304},
--	{"0000001000010011111100001111110101000010110110100100000101100100",0x0000343C,0xFFFFE869,0x00000559,0x00001CE2,0xFFFFF614,0x00000359,0x00001CE2,0xFFFFF614,0x00000359},
--	{"0000001000010011111100001111111010011001000110000011100101100100",0x00002782,0xFFFFF1FE,0x000003D9,0x000015DC,0xFFFFFB8B,0x00000290,0x000015DC,0xFFFFFB8B,0x00000290},
--	{"0000001000010011111100001111111010011001000110000001100011000100",0x00002B9C,0xFFFFEF63,0x00000443,0x00001369,0xFFFFFD51,0x00000244,0x00001369,0xFFFFFD51,0x00000244},
--	{"0000001000010011111100001111111010011001000010100010000010000100",0x000035F8,0xFFFFE743,0x00000592,0x000018D8,0xFFFFF8EE,0x000002E4,0x000018D8,0xFFFFF8EE,0x000002E4},
--	{"0000001000010011111010101001010011011110000001100010100001000100",0x00002B72,0xFFFFEF1E,0x0000043C,0x00002647,0xFFFFF092,0x0000043E,0x00002647,0xFFFFF092,0x0000043E},
--	{"0000001000010011111100001111111010011001000100000010000110000100",0x00002EC9,0xFFFFEC5F,0x000004B8,0x000018B6,0xFFFFF936,0x000002D8,0x000018B6,0xFFFFF936,0x000002D8},
--	{"0000001000010011111100001111111010011001000001100100000010000100",0x000038A7,0xFFFFE6AC,0x00000589,0x00001C42,0xFFFFF70B,0x00000329,0x00001C42,0xFFFFF70B,0x00000329},
--	{"0000001000010011111100001111111010011001001100000000100010100100",0x00002F6B,0xFFFFEBF6,0x000004CF,0x000018AE,0xFFFFF928,0x000002E3,0x000018AE,0xFFFFF928,0x000002E3},
--	{"0000001000010011111100001111110101000010110110100101000100000100",0x000029CD,0xFFFFEEE1,0x00000459,0x00001AB5,0xFFFFF76F,0x00000324,0x00001AB5,0xFFFFF76F,0x00000324},
--	{"0000001000010011111010101001010011011110000001100011100011000100",0x00003921,0xFFFFE71D,0x00000577,0x00001646,0xFFFFFB24,0x00000293,0x00001646,0xFFFFFB24,0x00000293},
--	{"0000001000010011111010101001010011011110000001000100000101100100",0x00003940,0xFFFFE521,0x000005E8,0x00001947,0xFFFFF839,0x0000030D,0x00001947,0xFFFFF839,0x0000030D},
--	{"0000001000010011111100001111110101000010110100100100000101100100",0x00003DCA,0xFFFFE211,0x00000659,0x0000250E,0xFFFFF072,0x00000443,0x0000250E,0xFFFFF072,0x00000443},
--	{"0000001000010011111100001111111010011001000011000000100100000100",0x00002E95,0xFFFFEC20,0x000004C9,0x000015B4,0xFFFFFAD3,0x0000029D,0x000015B4,0xFFFFFAD3,0x0000029D},
--	{"0000001000010011111100001111111010011001000001000001000010000100",0x00002C11,0xFFFFEE6E,0x00000468,0x00001901,0xFFFFF924,0x000002E7,0x00001901,0xFFFFF924,0x000002E7},
--	{"0000001000010011111010101001010011011110000001100010000100000100",0x0000293F,0xFFFFF158,0x000003E6,0x0000183F,0xFFFFF9F6,0x000002D2,0x0000183F,0xFFFFF9F6,0x000002D2},
--	{"0000001000010011111100001111111010011001000011100001000100000100",0x00002A67,0xFFFFEF34,0x0000043E,0x00001C6F,0xFFFFF6F1,0x0000032B,0x00001C6F,0xFFFFF6F1,0x0000032B},
--	{"0000001000010011111010101001010011011110000001100101000100100100",0x00002F8D,0xFFFFEB77,0x000004DA,0x00001C0D,0xFFFFF627,0x00000365,0x00001C0D,0xFFFFF627,0x00000365},
--	{"0000001000010011111100001111111010011001000011000011100011000100",0x00003476,0xFFFFEA5B,0x000004E7,0x00001DBF,0xFFFFF6C7,0x00000333,0x00001DBF,0xFFFFF6C7,0x00000333},
--	{"0000001000010011111100001111111010011001000011100000100101000100",0x00003336,0xFFFFE92F,0x00000546,0x00001614,0xFFFFFAE0,0x00000296,0x00001614,0xFFFFFAE0,0x00000296},
--	{"0000001000010011111100001111111010011001000101100010000101100100",0x00002513,0xFFFFF323,0x000003BC,0x000016DB,0xFFFFFA79,0x000002CD,0x000016DB,0xFFFFFA79,0x000002CD},
--	{"0000001000010011111100001111111010011001000010100010100101000100",0x000035A7,0xFFFFE78E,0x00000584,0x00001B0D,0xFFFFF77D,0x0000031F,0x00001B0D,0xFFFFF77D,0x0000031F},
--	{"0000001000010011111100001111111010011001001100100011100011100100",0x00003171,0xFFFFEB98,0x000004C6,0x00001C76,0xFFFFF71F,0x0000032F,0x00001C76,0xFFFFF71F,0x0000032F},
--	{"0000001000010011111100001111110101000010110110100001000010000100",0x00002C52,0xFFFFED2E,0x000004A7,0x00002182,0xFFFFF2F4,0x000003E4,0x00002182,0xFFFFF2F4,0x000003E4},
--	{"0000001000010011111100001111111010011001000100000010100100100100",0x000032E1,0xFFFFEB39,0x000004D0,0x00001B55,0xFFFFF859,0x000002FA,0x00001B55,0xFFFFF859,0x000002FA},
--	{"0000001000010011111100001111111010011001000110000100100010100100",0x000029B6,0xFFFFEFF7,0x00000430,0x0000151B,0xFFFFFBC6,0x0000027F,0x0000151B,0xFFFFFBC6,0x0000027F},
--	{"0000001000010011111100001111110101000010110110100001100101100100",0x00002FF7,0xFFFFEB67,0x000004DA,0x000020E9,0xFFFFF363,0x000003CE,0x000020E9,0xFFFFF363,0x000003CE},
--	{"0000001000010011111100001111110101000010110110100101000100100100",0x00003CDD,0xFFFFE2B2,0x00000649,0x00001B18,0xFFFFF739,0x00000329,0x00001B18,0xFFFFF739,0x00000329},
--	{"0000001000010011111100001111111010011001000001100010100010100100",0x00003C82,0xFFFFE5C6,0x0000058E,0x00001F3F,0xFFFFF5AD,0x00000361,0x00001F3F,0xFFFFF5AD,0x00000361},
--	{"0000001000010011111100001111110101000010110111000100000010000100",0x0000319B,0xFFFFEA15,0x0000051B,0x00001CC9,0xFFFFF62E,0x00000358,0x00001CC9,0xFFFFF62E,0x00000358},
--	{"0000001000010011111010101001010011011110000001100011100011100100",0x000032B6,0xFFFFEB2B,0x000004D6,0x000018E0,0xFFFFF966,0x000002DE,0x000018E0,0xFFFFF966,0x000002DE},
--	{"0000001000010011111010101001010011011110000000100011100110000100",0x0000300A,0xFFFFEBA6,0x000004D1,0x00001CFD,0xFFFFF5F6,0x0000036D,0x00001CFD,0xFFFFF5F6,0x0000036D},
--	{"0000001000010011111100001111110101000010110110000010100110000100",0x000026A9,0xFFFFF15D,0x00000400,0x00001561,0xFFFFFB1F,0x000002A0,0x00001561,0xFFFFFB1F,0x000002A0},
--	{"0000001000010011111100001111111010011001000011100101000100100100",0x00003123,0xFFFFEAD2,0x000004FA,0x000018CB,0xFFFFF8F5,0x000002EC,0x000018CB,0xFFFFF8F5,0x000002EC},
--	{"0000001000010011111100001111111010011001000110000100000011000100",0x00003577,0xFFFFE935,0x00000533,0x000016CD,0xFFFFFB44,0x00000289,0x000016CD,0xFFFFFB44,0x00000289},
--	{"0000001000010011111100001111111010011001001010000010000110000100",0x00002875,0xFFFFF170,0x000003F3,0x00001567,0xFFFFFBD5,0x00000289,0x00001567,0xFFFFFBD5,0x00000289},
--	{"0000001000010011111100001111111010011001000010000100000010000100",0x00003AE2,0xFFFFE538,0x000005C1,0x00001CB4,0xFFFFF6A3,0x0000033C,0x00001CB4,0xFFFFF6A3,0x0000033C},
--	{"0000001000010011111100001111111010011001000011000011100011100100",0x000031DF,0xFFFFEC2A,0x000004A3,0x00001EF0,0xFFFFF626,0x00000352,0x00001EF0,0xFFFFF626,0x00000352},
--	{"0000001000010011111100001111110101000010110100100101000101000100",0x00004A6A,0xFFFFDB15,0x00000758,0x000027F3,0xFFFFEEEE,0x00000479,0x000027F3,0xFFFFEEEE,0x00000479},
--	{"0000001000010011111010101001010011011110000001100011100100000100",0x00002BB9,0xFFFFEF5D,0x00000433,0x00001589,0xFFFFFB57,0x00000295,0x00001589,0xFFFFFB57,0x00000295},
--	{"0000001000010011111100001111111010011001000001000010000101100100",0x000033A0,0xFFFFE98F,0x00000528,0x00001CB4,0xFFFFF706,0x0000032D,0x00001CB4,0xFFFFF706,0x0000032D},
--	{"0000001000010011111100001111111010011001000101100011000001100100",0x0000248E,0xFFFFF380,0x000003AC,0x000016EA,0xFFFFFA6C,0x000002CE,0x000016EA,0xFFFFFA6C,0x000002CE},
--	{"0000001000010011111100001111111010011001000000100010000110100100",0x00002FE2,0xFFFFEB2F,0x000004E9,0x00001D4E,0xFFFFF56B,0x00000380,0x00001D4E,0xFFFFF56B,0x00000380},
--	{"0000001000010011111100001111111010011001000010100010100010000100",0x00003283,0xFFFFE9E7,0x0000051D,0x00000694,0xFFFFFD32,0x000003C3,0x00000694,0xFFFFFD32,0x000003C3},
--	{"0000001000010011111100001111110101000010110110000101000011000100",0x00002EE4,0xFFFFEBFD,0x000004D3,0x0000151A,0xFFFFFAF6,0x000002A4,0x0000151A,0xFFFFFAF6,0x000002A4},
--	{"0000001000010011111100001111110101000010110111000001100011100100",0x0000302D,0xFFFFEB7F,0x000004DA,0x00001E6D,0xFFFFF54B,0x00000380,0x00001E6D,0xFFFFF54B,0x00000380},
--	{"0000001000010011111100001111110101000010110110100101000011000100",0x000033DA,0xFFFFE7FB,0x0000057F,0x00001DED,0xFFFFF50E,0x0000038D,0x00001DED,0xFFFFF50E,0x0000038D},
--	{"0000001000010011111100001111111010011001001011000100000010000100",0x000030B5,0xFFFFEBB8,0x000004C4,0x00001C3F,0xFFFFF726,0x0000032A,0x00001C3F,0xFFFFF726,0x0000032A},
--	{"0000001000010011111100001111111010011001000010000011000111000100",0x00003BBD,0xFFFFE55C,0x000005B8,0x000019DB,0xFFFFF8BB,0x000002EF,0x000019DB,0xFFFFF8BB,0x000002EF},
--	{"0000001000010011111100001111111010011001000011100011100010000100",0x00002964,0xFFFFF051,0x0000040E,0x000025CD,0xFFFFF11B,0x0000041F,0x000025CD,0xFFFFF11B,0x0000041F},
--	{"0000001000010011111100001111110101000010110111000100100010000100",0x000033F5,0xFFFFE863,0x00000560,0x00001BCE,0xFFFFF689,0x0000034B,0x00001BCE,0xFFFFF689,0x0000034B},
--	{"0000001000010011111100001111111010011001000010100010100001100100",0x00003294,0xFFFFE924,0x00000548,0x00001D41,0xFFFFF580,0x0000037D,0x00001D41,0xFFFFF580,0x0000037D},
--	{"0000001000010011111100001111110101000010110111000011100110100100",0x000034FB,0xFFFFE7FE,0x0000056D,0x00001CB1,0xFFFFF635,0x00000357,0x00001CB1,0xFFFFF635,0x00000357},
--	{"0000001000010011111100001111111010011001000010100001000010100100",0x00002E28,0xFFFFEBB9,0x000004E0,0x00001B20,0xFFFFF6E3,0x0000033C,0x00001B20,0xFFFFF6E3,0x0000033C},
--	{"0000001000010011111100001111110101000010110110100001100100000100",0x00002799,0xFFFFF0F4,0x000003FC,0x00001C9D,0xFFFFF6A1,0x00000345,0x00001C9D,0xFFFFF6A1,0x00000345},
--	{"0000001000010011111100001111111010011001000001100100000100000100",0x00003AEA,0xFFFFE5DB,0x0000059D,0x00001B61,0xFFFFF7F0,0x00000301,0x00001B61,0xFFFFF7F0,0x00000301},
--	{"0000001000010011111010101001010011011110000001000001100110000100",0x000031F6,0xFFFFEAB8,0x000004F3,0x00001D90,0xFFFFF622,0x00000359,0x00001D90,0xFFFFF622,0x00000359},
--	{"0000001000010011111100001111111010011001000011000100000001100100",0x000031B8,0xFFFFEA61,0x0000050F,0x0000199D,0xFFFFF87C,0x000002FD,0x0000199D,0xFFFFF87C,0x000002FD},
--	{"0000001000010011111100001111110101000010110100100011000101000100",0x00004514,0xFFFFDDFF,0x000006F6,0x000022CD,0xFFFFF29F,0x000003D9,0x000022CD,0xFFFFF29F,0x000003D9},
--	{"0000001000010011111010101001010011011110000001000011000101100100",0x00002F30,0xFFFFECB8,0x000004A0,0x00001B07,0xFFFFF7E2,0x00000313,0x00001B07,0xFFFFF7E2,0x00000313},
--	{"0000001000010011111100001111110101000010110111000011000010100100",0x0000383B,0xFFFFE702,0x00000581,0x00001A08,0xFFFFF8CA,0x000002E2,0x00001A08,0xFFFFF8CA,0x000002E2},
--	{"0000001000010011111100001111111010011001000000100010000101100100",0x00002CC5,0xFFFFEDF8,0x00000465,0x00001F47,0xFFFFF4B2,0x00000393,0x00001F47,0xFFFFF4B2,0x00000393},
--	{"0000001000010011111100001111111010011001000101100010000111000100",0x00002304,0xFFFFF453,0x00000384,0x0000170A,0xFFFFFA3F,0x000002CE,0x0000170A,0xFFFFFA3F,0x000002CE},
--	{"0000001000010011111100001111111010011001000010100101000100100100",0x0000337E,0xFFFFE850,0x0000056E,0x00001BDD,0xFFFFF668,0x00000353,0x00001BDD,0xFFFFF668,0x00000353},
--	{"0000001000010011111100001111111010011001000011100100100100100100",0x00002E2F,0xFFFFEC9B,0x000004AE,0x00001C4D,0xFFFFF6D3,0x00000338,0x00001C4D,0xFFFFF6D3,0x00000338},
--	{"0000001000010011111010101001010011011110000001100001000100100100",0x00002DDD,0xFFFFEDA4,0x00000477,0x00002010,0xFFFFF4BB,0x00000390,0x00002010,0xFFFFF4BB,0x00000390},
--	{"0000001000010011111100001111110101000010110110100100100011100100",0x0000290C,0xFFFFEF61,0x00000445,0x00002133,0xFFFFF324,0x000003D8,0x00002133,0xFFFFF324,0x000003D8},
--	{"0000001000010011111100001111111010011001000001100010100100100100",0x0000371E,0xFFFFE8D5,0x00000524,0x00001C3A,0xFFFFF7AE,0x00000314,0x00001C3A,0xFFFFF7AE,0x00000314},
--	{"0000001000010011111100001111110101000010110110000011100011100100",0x00002A58,0xFFFFF007,0x00000429,0x000018A6,0xFFFFF98F,0x000002E1,0x000018A6,0xFFFFF98F,0x000002E1},
--	{"0000001000010011111100001111111010011001000000100011000010000100",0x00002FED,0xFFFFEC48,0x000004AA,0x00001E9D,0xFFFFF584,0x00000370,0x00001E9D,0xFFFFF584,0x00000370},
--	{"0000001000010011111100001111111010011001000110000001100010000100",0x00002829,0xFFFFF15F,0x000003F7,0x0000157E,0xFFFFFBD4,0x00000282,0x0000157E,0xFFFFFBD4,0x00000282},
--	{"0000001000010011111100001111111010011001000100000001100100100100",0x000030CF,0xFFFFEB8D,0x000004CE,0x00001A4C,0xFFFFF868,0x000002F7,0x00001A4C,0xFFFFF868,0x000002F7},
--	{"0000001000010011111100001111110101000010110110100010000010000100",0x00002C8F,0xFFFFEDD2,0x0000047D,0x00001CCE,0xFFFFF6A1,0x00000343,0x00001CCE,0xFFFFF6A1,0x00000343},
--	{"0000001000010011111100001111111010011001000110000010000101100100",0x00002A84,0xFFFFEFBA,0x0000043E,0x000015EF,0xFFFFFB4B,0x0000029E,0x000015EF,0xFFFFFB4B,0x0000029E},
--	{"0000001000010011111100001111111010011001000011000010100010100100",0x000034CA,0xFFFFEA08,0x000004FF,0x00001C19,0xFFFFF7ED,0x00000309,0x00001C19,0xFFFFF7ED,0x00000309},
--	{"0000001000010011111100001111111010011001000101100011100110100100",0x00002187,0xFFFFF4B0,0x0000037E,0x0000154A,0xFFFFFB0C,0x000002AE,0x0000154A,0xFFFFFB0C,0x000002AE},
--	{"0000001000010011111100001111110101000010110110100011100001000100",0x00002F4F,0xFFFFEB3C,0x000004F8,0x0000181F,0xFFFFF92D,0x000002DF,0x0000181F,0xFFFFF92D,0x000002DF},
--	{"0000001000010011111100001111111010011001000001000001000011100100",0x0000290C,0xFFFFF0B1,0x000003FC,0x00001DB0,0xFFFFF636,0x00000355,0x00001DB0,0xFFFFF636,0x00000355},
--	{"0000001000010011111100001111111010011001000010100001000001100100",0x000034C1,0xFFFFE888,0x0000055A,0x000019BF,0xFFFFF881,0x000002FB,0x000019BF,0xFFFFF881,0x000002FB},
--	{"0000001000010011111100001111110101000010110111000001100011000100",0x00003139,0xFFFFEA98,0x00000504,0x000019F2,0xFFFFF820,0x0000030B,0x000019F2,0xFFFFF820,0x0000030B},
--	{"0000001000010011111100001111110101000010110110000011000101000100",0x00002CAC,0xFFFFEEB2,0x00000458,0x0000152C,0xFFFFFBEF,0x0000027B,0x0000152C,0xFFFFFBEF,0x0000027B},
--	{"0000001000010011111100001111111010011001001011000011100011100100",0x00003577,0xFFFFE99C,0x0000050D,0x00001E64,0xFFFFF679,0x0000033F,0x00001E64,0xFFFFF679,0x0000033F},
--	{"0000001000010011111100001111110101000010110110100100000100000100",0x0000263A,0xFFFFF1E4,0x000003D4,0x00001F68,0xFFFFF4ED,0x00000386,0x00001F68,0xFFFFF4ED,0x00000386},
--	{"0000001000010011111100001111110101000010110110000001100110000100",0x00002CE9,0xFFFFED63,0x00000497,0x00001810,0xFFFFF94D,0x000002E3,0x00001810,0xFFFFF94D,0x000002E3},
--	{"0000001000010011111010101001010011011110000001000100000100000100",0x0000318A,0xFFFFEAC8,0x000004F5,0x0000195C,0xFFFFF896,0x000002FB,0x0000195C,0xFFFFF896,0x000002FB},
--	{"0000001000010011111100001111110101000010110110000011100100000100",0x00002C41,0xFFFFEEC6,0x0000045D,0x000017DD,0xFFFFFA16,0x000002CB,0x000017DD,0xFFFFFA16,0x000002CB},
--	{"0000001000010011111100001111111010011001000000100011000110100100",0x00002DD4,0xFFFFEC98,0x000004AD,0x00001BD7,0xFFFFF69F,0x00000347,0x00001BD7,0xFFFFF69F,0x00000347},
--	{"0000001000010011111100001111110101000010110110100011100101000100",0x00003351,0xFFFFE9B2,0x0000051A,0x00001CA1,0xFFFFF6A4,0x00000341,0x00001CA1,0xFFFFF6A4,0x00000341},
--	{"0000001000010011111100001111111010011001000000100001000100000100",0x0000322D,0xFFFFE9BE,0x00000527,0x00001CF9,0xFFFFF5EB,0x00000366,0x00001CF9,0xFFFFF5EB,0x00000366},
--	{"0000001000010011111100001111111010011001000011000010100011000100",0x00003678,0xFFFFE9A8,0x00000503,0x00001AD4,0xFFFFF8F6,0x000002E3,0x00001AD4,0xFFFFF8F6,0x000002E3},
--	{"0000001000010011111100001111111010011001000101100001100100100100",0x0000260E,0xFFFFF2C1,0x000003CA,0x00001139,0xFFFFFE48,0x00000236,0x00001139,0xFFFFFE48,0x00000236},
--	{"0000001000010011111100001111111010011001000010100010000101100100",0x000033D3,0xFFFFE872,0x00000565,0x00001B72,0xFFFFF713,0x00000332,0x00001B72,0xFFFFF713,0x00000332},
--	{"0000001000010011111100001111111010011001001100100011100001000100",0x0000309B,0xFFFFEB42,0x000004E4,0x00001918,0xFFFFF8C8,0x000002F2,0x00001918,0xFFFFF8C8,0x000002F2},
--	{"0000001000010011111100001111111010011001000110000010100001100100",0x000028B8,0xFFFFF105,0x00000402,0x000018BB,0xFFFFF9BC,0x000002D3,0x000018BB,0xFFFFF9BC,0x000002D3},
--	{"0000001000010011111100001111111010011001000010100001100010000100",0x00003123,0xFFFFE9D1,0x00000534,0x00001B19,0xFFFFF6FE,0x0000033C,0x00001B19,0xFFFFF6FE,0x0000033C},
--	{"0000001000010011111100001111111010011001000000100010000101000100",0x00003216,0xFFFFEA8E,0x000004F6,0x00001F72,0xFFFFF4CE,0x0000038B,0x00001F72,0xFFFFF4CE,0x0000038B},
--	{"0000001000010011111100001111111010011001000101100010100101100100",0x00002564,0xFFFFF32D,0x000003B6,0x00001685,0xFFFFFADB,0x000002BB,0x00001685,0xFFFFFADB,0x000002BB},
--	{"0000001000010011111100001111110101000010110110100010100100100100",0x00002E60,0xFFFFED13,0x00000497,0x00001CA5,0xFFFFF6B9,0x00000346,0x00001CA5,0xFFFFF6B9,0x00000346},
--	{"0000001000010011111100001111111010011001000011100011100110100100",0x0000336D,0xFFFFE934,0x0000053B,0x00001B3E,0xFFFFF763,0x00000327,0x00001B3E,0xFFFFF763,0x00000327},
--	{"0000001000010011111100001111111010011001000100000001000010000100",0x0000274A,0xFFFFF119,0x000003FA,0x00001D75,0xFFFFF5CD,0x0000036F,0x00001D75,0xFFFFF5CD,0x0000036F},
--	{"0000001000010011111100001111110101000010110110100010000101100100",0x0000366B,0xFFFFE70A,0x0000059A,0x00001ED8,0xFFFFF501,0x00000389,0x00001ED8,0xFFFFF501,0x00000389},
--	{"0000001000010011111100001111111010011001001000100011100101100100",0x00003164,0xFFFFEAB4,0x000004FA,0x00001C52,0xFFFFF6E0,0x00000336,0x00001C52,0xFFFFF6E0,0x00000336},
--	{"0000001000010011111100001111110101000010110100100011000001100100",0x00004224,0xFFFFDF7F,0x000006C1,0x00002A52,0xFFFFED5E,0x000004BB,0x00002A52,0xFFFFED5E,0x000004BB},
--	{"0000001000010011111100001111111010011001000100000010100001100100",0x000030E3,0xFFFFEB07,0x000004ED,0x00001FD3,0xFFFFF46D,0x000003A1,0x00001FD3,0xFFFFF46D,0x000003A1},
--	{"0000001000010011111100001111110101000010110110000010100010000100",0x00002AEB,0xFFFFEF1B,0x00000454,0x00001829,0xFFFFF995,0x000002DD,0x00001829,0xFFFFF995,0x000002DD},
--	{"0000001000010011111100001111110101000010110111000101000011100100",0x0000346B,0xFFFFE7A2,0x0000058B,0x000020C5,0xFFFFF2E8,0x000003EC,0x000020C5,0xFFFFF2E8,0x000003EC},
--	{"0000001000010011111100001111110101000010110111000100000101100100",0x000039CF,0xFFFFE5D7,0x000005A9,0x00001D66,0xFFFFF5D6,0x00000366,0x00001D66,0xFFFFF5D6,0x00000366},
--	{"0000001000010011111100001111111010011001000001000001100011100100",0x000034AC,0xFFFFE9AE,0x00000515,0x00001A28,0xFFFFF904,0x000002DC,0x00001A28,0xFFFFF904,0x000002DC},
--	{"0000001000010011111100001111110101000010110111000010000010000100",0x00002D68,0xFFFFED21,0x00000498,0x00001C6F,0xFFFFF686,0x0000034C,0x00001C6F,0xFFFFF686,0x0000034C},
--	{"0000001000010011111100001111111010011001000010000010000011000100",0x0000328B,0xFFFFEBA1,0x000004B4,0x00001DA3,0xFFFFF683,0x00000349,0x00001DA3,0xFFFFF683,0x00000349},
--	{"0000001000010011111100001111111010011001000110000010100011000100",0x000027DC,0xFFFFF295,0x000003BF,0x000019C1,0xFFFFF98E,0x000002E8,0x000019C1,0xFFFFF98E,0x000002E8},
--	{"0000001000010011111100001111111010011001000110000100000010000100",0x00002756,0xFFFFF1D7,0x000003DF,0x000015D9,0xFFFFFB51,0x00000298,0x000015D9,0xFFFFFB51,0x00000298},
--	{"0000001000010011111100001111111010011001000010000011100010000100",0x00003526,0xFFFFE907,0x00000526,0x000017AB,0xFFFFFA12,0x000002AB,0x000017AB,0xFFFFFA12,0x000002AB},
--	{"0000001000010011111100001111110101000010110110100001100011100100",0x0000351B,0xFFFFE8B7,0x00000540,0x00001A86,0xFFFFF821,0x00000303,0x00001A86,0xFFFFF821,0x00000303},
--	{"0000001000010011111100001111111010011001000101100100000101000100",0x000024B2,0xFFFFF34E,0x000003B1,0x000018E2,0xFFFFF926,0x000002FC,0x000018E2,0xFFFFF926,0x000002FC},
--	{"0000001000010011111100001111110101000010110110000010100010100100",0x00002F36,0xFFFFED5D,0x00000486,0x0000157A,0xFFFFFB85,0x00000293,0x0000157A,0xFFFFFB85,0x00000293},
--	{"0000001000010011111100001111110101000010110111000101000011000100",0x00003A6E,0xFFFFE456,0x000005FD,0x00001F68,0xFFFFF3D1,0x000003C3,0x00001F68,0xFFFFF3D1,0x000003C3},
--	{"0000001000010011111100001111111010011001000010100011000110100100",0x00002BC3,0xFFFFED2D,0x000004A7,0x00001C3F,0xFFFFF609,0x00000364,0x00001C3F,0xFFFFF609,0x00000364},
--	{"0000001000010011111100001111111010011001000011100010000010000100",0x000032E1,0xFFFFEA83,0x000004F6,0x00001B37,0xFFFFF842,0x000002F5,0x00001B37,0xFFFFF842,0x000002F5},
--	{"0000001000010011111100001111110101000010110110000011000110000100",0x000028E3,0xFFFFF07F,0x00000412,0x00001676,0xFFFFFA68,0x000002BE,0x00001676,0xFFFFFA68,0x000002BE},
--	{"0000001000010011111100001111110101000010110100100001000100000100",0x0000444C,0xFFFFDDAD,0x00000712,0x00002634,0xFFFFEF89,0x0000046C,0x00002634,0xFFFFEF89,0x0000046C},
--	{"0000001000010011111100001111111010011001000001000001100011000100",0x00003121,0xFFFFEBBB,0x000004C6,0x00001C98,0xFFFFF72B,0x0000032D,0x00001C98,0xFFFFF72B,0x0000032D},
--	{"0000001000010011111100001111110101000010110110000100000010100100",0x00002C31,0xFFFFEDC4,0x00000490,0x0000162D,0xFFFFFA8E,0x000002B4,0x0000162D,0xFFFFFA8E,0x000002B4},
--	{"0000001000010011111100001111110101000010110110100001100011000100",0x00002749,0xFFFFF112,0x000003FC,0x00001C85,0xFFFFF6B8,0x00000342,0x00001C85,0xFFFFF6B8,0x00000342},
--	{"0000001000010011111100001111111010011001000001000100000100000100",0x00003159,0xFFFFEB99,0x000004C2,0x00001BD0,0xFFFFF7CA,0x00000307,0x00001BD0,0xFFFFF7CA,0x00000307},
--	{"0000001000010011111100001111111010011001000101100100000101100100",0x00002610,0xFFFFF1FD,0x000003EC,0x000016BE,0xFFFFFA53,0x000002CB,0x000016BE,0xFFFFFA53,0x000002CB},
--	{"0000001000010011111100001111111010011001000000100011000110000100",0x000037B5,0xFFFFE63D,0x000005B5,0x00002285,0xFFFFF25D,0x000003F7,0x00002285,0xFFFFF25D,0x000003F7},
--	{"0000001000010011111100001111111010011001000010100010100010100100",0x00002FEE,0xFFFFEB47,0x000004EF,0x00001CBE,0xFFFFF64E,0x00000358,0x00001CBE,0xFFFFF64E,0x00000358},
--	{"0000001000010011111100001111111010011001000100000101000100000100",0x00002E90,0xFFFFEC48,0x000004C0,0x00001A47,0xFFFFF7D1,0x0000031A,0x00001A47,0xFFFFF7D1,0x0000031A},
--	{"0000001000010011111100001111110101000010110110100100000010000100",0x000034AB,0xFFFFE84A,0x00000559,0x00001A72,0xFFFFF79A,0x0000031C,0x00001A72,0xFFFFF79A,0x0000031C},
--	{"0000001000010011111100001111111010011001000110000011100010000100",0x00002F7B,0xFFFFECFC,0x0000049C,0x00001814,0xFFFFFA22,0x000002C2,0x00001814,0xFFFFFA22,0x000002C2},
--	{"0000001000010011111100001111111010011001000000100001100101100100",0x00003618,0xFFFFE709,0x00000596,0x00001EBF,0xFFFFF482,0x000003A5,0x00001EBF,0xFFFFF482,0x000003A5},
--	{"0000001000010011111010101001010011011110000000100100100100000100",0x0000341B,0xFFFFE8B2,0x0000054F,0x00001D26,0xFFFFF578,0x00000388,0x00001D26,0xFFFFF578,0x00000388},
--	{"0000001000010011111100001111111010011001000100000010000101000100",0x000030F6,0xFFFFEB89,0x000004CD,0x000019C0,0xFFFFF8CC,0x000002E6,0x000019C0,0xFFFFF8CC,0x000002E6},
--	{"0000001000010011111100001111111010011001001010000100000110100100",0x00002B76,0xFFFFEF6C,0x00000444,0x00001563,0xFFFFFBBE,0x0000028D,0x00001563,0xFFFFFBBE,0x0000028D},
--	{"0000001000010011111100001111110101000010110110000001100001100100",0x00002BA2,0xFFFFEE31,0x0000047F,0x00001A3D,0xFFFFF7F3,0x00000320,0x00001A3D,0xFFFFF7F3,0x00000320},
--	{"0000001000010011111100001111111010011001001011000100100011100100",0x00003545,0xFFFFE87A,0x0000054A,0x00001B5A,0xFFFFF7B0,0x0000030C,0x00001B5A,0xFFFFF7B0,0x0000030C},
--	{"0000001000010011111010101001010011011110000001000010100101000100",0x00003879,0xFFFFE73F,0x00000578,0x00001649,0xFFFFFB57,0x00000283,0x00001649,0xFFFFFB57,0x00000283},
--	{"0000001000010011111100001111110101000010110110000100000011000100",0x00002772,0xFFFFF0F1,0x00000410,0x0000142F,0xFFFFFBCF,0x00000287,0x0000142F,0xFFFFFBCF,0x00000287},
--	{"0000001000010011111100001111110101000010110110100011000110000100",0x00003228,0xFFFFE98E,0x00000535,0x00001F48,0xFFFFF495,0x00000399,0x00001F48,0xFFFFF495,0x00000399},
--	{"0000001000010011111100001111111010011001000011100100000011100100",0x00002887,0xFFFFF119,0x000003E8,0x000021AA,0xFFFFF3F5,0x000003A5,0x000021AA,0xFFFFF3F5,0x000003A5},
--	{"0000001000010011111100001111110101000010110110100010100010100100",0x0000301F,0xFFFFEBB2,0x000004D2,0x00001C02,0xFFFFF736,0x0000032B,0x00001C02,0xFFFFF736,0x0000032B},
--	{"0000001000010011111100001111111010011001000110000010000010100100",0x00002E13,0xFFFFEE3F,0x00000468,0x000016AC,0xFFFFFB32,0x0000029E,0x000016AC,0xFFFFFB32,0x0000029E},
--	{"0000001000010011111100001111111010011001000001000100100100100100",0x00003478,0xFFFFE8F9,0x00000538,0x00001DAB,0xFFFFF645,0x00000345,0x00001DAB,0xFFFFF645,0x00000345},
--	{"0000001000010011111100001111111010011001000001100000100011000100",0x000030C6,0xFFFFEB6C,0x000004D4,0x0000184A,0xFFFFF934,0x000002E1,0x0000184A,0xFFFFF934,0x000002E1},
--	{"0000001000010011111100001111111010011001000010100010000001000100",0x00002F1B,0xFFFFEBD3,0x000004D3,0x000019E7,0xFFFFF813,0x0000030D,0x000019E7,0xFFFFF813,0x0000030D},
--	{"0000001000010011111100001111111010011001000000100011100100000100",0x00003214,0xFFFFEAE9,0x000004E0,0x0000178F,0xFFFFFA1C,0x000002B1,0x0000178F,0xFFFFFA1C,0x000002B1},
--	{"0000001000010011111100001111110101000010110111000011000101000100",0x0000399C,0xFFFFE738,0x0000055E,0x00001EA1,0xFFFFF5E7,0x0000035A,0x00001EA1,0xFFFFF5E7,0x0000035A},
--	{"0000001000010011111100001111111010011001000001100101000011000100",0x00003A01,0xFFFFE5B2,0x000005B6,0x00001D95,0xFFFFF5D2,0x0000036A,0x00001D95,0xFFFFF5D2,0x0000036A},
--	{"0000001000010011111100001111111010011001000001000011100010000100",0x0000310D,0xFFFFEB78,0x000004D0,0x00001C06,0xFFFFF76E,0x0000031A,0x00001C06,0xFFFFF76E,0x0000031A},
--	{"0000001000010011111100001111111010011001000001100011100001100100",0x00003CD1,0xFFFFE42F,0x000005EB,0x00001933,0xFFFFF91F,0x000002D4,0x00001933,0xFFFFF91F,0x000002D4},
--	{"0000001000010011111100001111110101000010110110100011000101100100",0x00003119,0xFFFFEB1B,0x000004E1,0x00001FC7,0xFFFFF46A,0x000003A2,0x00001FC7,0xFFFFF46A,0x000003A2},
--	{"0000001000010011111010101001010011011110000001100100100010100100",0x0000390D,0xFFFFE566,0x000005D8,0x00001EC6,0xFFFFF4DC,0x00000391,0x00001EC6,0xFFFFF4DC,0x00000391},
--	{"0000001000010011111100001111110101000010110110100001000011000100",0x00003446,0xFFFFE858,0x00000561,0x00001FDB,0xFFFFF3FF,0x000003B9,0x00001FDB,0xFFFFF3FF,0x000003B9},
--	{"0000001000010011111100001111111010011001000001000100100100000100",0x000032BA,0xFFFFEA07,0x00000511,0x00001B25,0xFFFFF7C9,0x0000030D,0x00001B25,0xFFFFF7C9,0x0000030D},
--	{"0000001000010011111100001111111010011001000011100001100001100100",0x00002CCF,0xFFFFEDE5,0x00000478,0x00001BC8,0xFFFFF761,0x00000326,0x00001BC8,0xFFFFF761,0x00000326},
--	{"0000001000010011111100001111111010011001000001100010100110000100",0x0000400E,0xFFFFE1CB,0x00000652,0x00001AF8,0xFFFFF7B9,0x00000312,0x00001AF8,0xFFFFF7B9,0x00000312},
--	{"0000001000010011111100001111111010011001000001000000100011100100",0x00002F24,0xFFFFEC2A,0x000004C7,0x00001B94,0xFFFFF748,0x00000333,0x00001B94,0xFFFFF748,0x00000333},
--	{"0000001000010011111100001111110101000010110100100001100100100100",0x00003FDA,0xFFFFE1C1,0x0000064B,0x00002427,0xFFFFF180,0x0000040C,0x00002427,0xFFFFF180,0x0000040C},
--	{"0000001000010011111100001111111010011001000010100001100011000100",0x00002F6B,0xFFFFEBA7,0x000004DD,0x00001C25,0xFFFFF6C1,0x00000344,0x00001C25,0xFFFFF6C1,0x00000344},
--	{"0000001000010011111100001111111010011001000110000010000100000100",0x00002A53,0xFFFFF0EE,0x00000402,0x000017C6,0xFFFFFAA0,0x000002BF,0x000017C6,0xFFFFFAA0,0x000002BF},
--	{"0000001000010011111100001111111010011001000100000101000101000100",0x000031F4,0xFFFFEA34,0x00000517,0x000016FF,0xFFFFFA4E,0x000002AC,0x000016FF,0xFFFFFA4E,0x000002AC},
--	{"0000001000010011111100001111111010011001001100100010000101000100",0x00002E24,0xFFFFED46,0x00000489,0x00001712,0xFFFFFA5D,0x000002AC,0x00001712,0xFFFFFA5D,0x000002AC},
--	{"0000001000010011111100001111111010011001000110000010100000100100",0x000028CD,0xFFFFF0E3,0x0000040E,0x00001606,0xFFFFFB37,0x000002A4,0x00001606,0xFFFFFB37,0x000002A4},
--	{"0000001000010011111100001111111010011001000000100010000011000100",0x00003184,0xFFFFEB88,0x000004C3,0x000018DA,0xFFFFF939,0x000002DB,0x000018DA,0xFFFFF939,0x000002DB},
--	{"0000001000010011111100001111111010011001000101100010000100100100",0x0000239B,0xFFFFF470,0x00000386,0x00001714,0xFFFFFA9F,0x000002C8,0x00001714,0xFFFFFA9F,0x000002C8},
--	{"0000001000010011111100001111110101000010110111000011100011100100",0x00003641,0xFFFFE92B,0x00000515,0x00001BE2,0xFFFFF795,0x0000031B,0x00001BE2,0xFFFFF795,0x0000031B},
--	{"0000001000010011111100001111111010011001001011000001000101000100",0x00003278,0xFFFFEA17,0x00000510,0x00001B71,0xFFFFF778,0x0000031D,0x00001B71,0xFFFFF778,0x0000031D},
--	{"0000001000010011111100001111111010011001000001100010100001000100",0x000035B9,0xFFFFE8DA,0x0000052D,0x00001A6A,0xFFFFF83B,0x000002FF,0x00001A6A,0xFFFFF83B,0x000002FF},
--	{"0000001000010011111100001111111010011001000011100001100011000100",0x00002E5E,0xFFFFED32,0x0000048B,0x00001E7D,0xFFFFF60E,0x0000034E,0x00001E7D,0xFFFFF60E,0x0000034E},
--	{"0000001000010011111100001111111010011001000100000001100110100100",0x00003178,0xFFFFEA52,0x00000513,0x00001AD0,0xFFFFF793,0x0000031F,0x00001AD0,0xFFFFF793,0x0000031F},
--	{"0000001000010011111100001111110101000010110101000100000100000100",0x00003A2C,0xFFFFE346,0x00000641,0x000023D0,0xFFFFF0CE,0x00000433,0x000023D0,0xFFFFF0CE,0x00000433},
--	{"0000001000010011111100001111110101000010110110000001100011000100",0x000028FD,0xFFFFF02A,0x0000042B,0x0000152B,0xFFFFFB90,0x00000289,0x0000152B,0xFFFFFB90,0x00000289},
--	{"0000001000010011111100001111111010011001000011100011000010000100",0x000030DE,0xFFFFEBDF,0x000004BE,0x00001CDC,0xFFFFF747,0x0000031C,0x00001CDC,0xFFFFF747,0x0000031C},
--	{"0000001000010011111100001111111010011001000000100001100101000100",0x000036CB,0xFFFFE6EE,0x00000596,0x00002096,0xFFFFF3C2,0x000003BB,0x00002096,0xFFFFF3C2,0x000003BB},
--	{"0000001000010011111100001111111010011001000011000100100011000100",0x00003172,0xFFFFEAC1,0x000004F4,0x00001C87,0xFFFFF6CD,0x00000337,0x00001C87,0xFFFFF6CD,0x00000337},
--	{"0000001000010011111100001111110101000010110100100100100001100100",0x00004A18,0xFFFFDB34,0x00000758,0x0000213C,0xFFFFF3A2,0x000003AC,0x0000213C,0xFFFFF3A2,0x000003AC},
--	{"0000001000010011111100001111111010011001000000100010000100000100",0x000031F3,0xFFFFEB73,0x000004C6,0x00001B23,0xFFFFF7CB,0x0000031A,0x00001B23,0xFFFFF7CB,0x0000031A},
--	{"0000001000010011111100001111111010011001000010100010100100100100",0x000031C0,0xFFFFEABA,0x000004F7,0x00001A5A,0xFFFFF845,0x000002FF,0x00001A5A,0xFFFFF845,0x000002FF},
--	{"0000001000010011111100001111111010011001000100000100100101000100",0x00003B77,0xFFFFE3B3,0x00000623,0x00001BCA,0xFFFFF6F8,0x00000333,0x00001BCA,0xFFFFF6F8,0x00000333},
--	{"0000001000010011111100001111111010011001000010100011100101000100",0x000035AF,0xFFFFE76D,0x00000588,0x00001C16,0xFFFFF6AB,0x00000341,0x00001C16,0xFFFFF6AB,0x00000341},
--	{"0000001000010011111010101001010011011110000001000011100011000100",0x000032AD,0xFFFFEA8E,0x000004F8,0x00001A3A,0xFFFFF832,0x0000030E,0x00001A3A,0xFFFFF832,0x0000030E},
--	{"0000001000010011111100001111111010011001000100000100100010000100",0x00002E92,0xFFFFEBD2,0x000004DA,0x00001E04,0xFFFFF51E,0x0000038A,0x00001E04,0xFFFFF51E,0x0000038A},
--	{"0000001000010011111100001111110101000010110101000100000010100100",0x00003E57,0xFFFFE0F7,0x0000068F,0x000021F1,0xFFFFF1C6,0x00000411,0x000021F1,0xFFFFF1C6,0x00000411},
--	{"0000001000010011111100001111111010011001000010000010000110100100",0x00003598,0xFFFFE8BB,0x00000535,0x00001B62,0xFFFFF764,0x00000326,0x00001B62,0xFFFFF764,0x00000326},
--	{"0000001000010011111100001111111010011001000010100011100010000100",0x00002B15,0xFFFFEDEC,0x00000487,0x00001E8B,0xFFFFF4AB,0x0000039F,0x00001E8B,0xFFFFF4AB,0x0000039F},
--	{"0000001000010011111010101001010011011110000001100000100100000100",0x0000267E,0xFFFFF1A7,0x000003E1,0x000021C1,0xFFFFF2E9,0x000003EA,0x000021C1,0xFFFFF2E9,0x000003EA},
--	{"0000001000010011111010101001010011011110000000100011100110100100",0x00002ED7,0xFFFFEC88,0x000004A6,0x00001DEC,0xFFFFF57C,0x00000378,0x00001DEC,0xFFFFF57C,0x00000378},
--	{"0000001000010011111010101001010011011110000001000100000110100100",0x00003365,0xFFFFE946,0x00000536,0x000019E9,0xFFFFF7E0,0x0000031D,0x000019E9,0xFFFFF7E0,0x0000031D},
--	{"0000001000010011111100001111111010011001000110000001100011100100",0x000029A4,0xFFFFF0FD,0x000003FE,0x0000163F,0xFFFFFB68,0x00000299,0x0000163F,0xFFFFFB68,0x00000299},
--	{"0000001000010011111010101001010011011110000000100001100100000100",0x0000348D,0xFFFFE9F7,0x00000509,0x000017A0,0xFFFFFA59,0x000002B6,0x000017A0,0xFFFFFA59,0x000002B6},
--	{"0000001000010011111100001111111010011001000001100001000011000100",0x00003144,0xFFFFEB23,0x000004D9,0x00001C9B,0xFFFFF664,0x00000351,0x00001C9B,0xFFFFF664,0x00000351},
--	{"0000001000010011111010101001010011011110000001100010000011100100",0x00002E95,0xFFFFEE1A,0x00000463,0x00001707,0xFFFFFAB7,0x000002B3,0x00001707,0xFFFFFAB7,0x000002B3},
--	{"0000001000010011111100001111110101000010110101000001100001100100",0x0000489C,0xFFFFDA43,0x000007AC,0x00002866,0xFFFFED6B,0x000004D0,0x00002866,0xFFFFED6B,0x000004D0},
--	{"0000001000010011111100001111111010011001000101100001100001000100",0x00002895,0xFFFFF10A,0x0000040A,0x000013E9,0xFFFFFC9F,0x0000026E,0x000013E9,0xFFFFFC9F,0x0000026E},
--	{"0000001000010011111100001111111010011001000001100001100101100100",0x000033A0,0xFFFFE9B1,0x00000510,0x00001D96,0xFFFFF5AE,0x0000036F,0x00001D96,0xFFFFF5AE,0x0000036F},
--	{"0000001000010011111100001111111010011001000010000011100110000100",0x0000327C,0xFFFFEAEA,0x000004DD,0x00001D45,0xFFFFF649,0x00000356,0x00001D45,0xFFFFF649,0x00000356},
--	{"0000001000010011111010101001010011011110000000100100100010100100",0x000031DF,0xFFFFE9AB,0x0000052F,0x000019C8,0xFFFFF7B7,0x00000321,0x000019C8,0xFFFFF7B7,0x00000321},
--	{"0000001000010011111100001111111010011001000101100100000010100100",0x00002BCC,0xFFFFEEF4,0x0000045C,0x000015CD,0xFFFFFB58,0x0000029E,0x000015CD,0xFFFFFB58,0x0000029E},
--	{"0000001000010011111100001111111010011001000001100011100011100100",0x00003534,0xFFFFEA10,0x000004EB,0x00001BB6,0xFFFFF7B9,0x00000314,0x00001BB6,0xFFFFF7B9,0x00000314},
--	{"0000001000010011111100001111111010011001000001000001100110000100",0x00002F4F,0xFFFFEC35,0x000004B9,0x0000205D,0xFFFFF47F,0x00000392,0x0000205D,0xFFFFF47F,0x00000392},
--	{"0000001000010011111100001111111010011001000011000010000010100100",0x00003295,0xFFFFEB1C,0x000004D6,0x000019C1,0xFFFFF931,0x000002D5,0x000019C1,0xFFFFF931,0x000002D5},
--	{"0000001000010011111100001111111010011001000000100100000101000100",0x00003557,0xFFFFE7F7,0x00000568,0x00002342,0xFFFFF1F9,0x00000405,0x00002342,0xFFFFF1F9,0x00000405},
--	{"0000001000010011111100001111111010011001000001000101000011000100",0x00003487,0xFFFFE872,0x0000055D,0x000019D7,0xFFFFF823,0x0000030C,0x000019D7,0xFFFFF823,0x0000030C},
--	{"0000001000010011111100001111111010011001001011000011100101000100",0x0000378F,0xFFFFE7A6,0x00000566,0x00001875,0xFFFFFA04,0x000002AF,0x00001875,0xFFFFFA04,0x000002AF},
--	{"0000001000010011111010101001010011011110000000100011000011100100",0x00002A67,0xFFFFF157,0x000003DD,0x000017BD,0xFFFFFA53,0x000002D1,0x000017BD,0xFFFFFA53,0x000002D1},
--	{"0000001000010011111100001111110101000010110100100010000011100100",0x000030B5,0xFFFFEB32,0x000004D9,0x00002129,0xFFFFF38A,0x000003BB,0x00002129,0xFFFFF38A,0x000003BB},
--	{"0000001000010011111100001111111010011001000001100001000010100100",0x00003786,0xFFFFE703,0x00000584,0x00001D63,0xFFFFF5DC,0x00000367,0x00001D63,0xFFFFF5DC,0x00000367},
--	{"0000001000010011111100001111110101000010110110100010000011000100",0x0000346A,0xFFFFE93E,0x0000052C,0x00001B27,0xFFFFF79D,0x0000031F,0x00001B27,0xFFFFF79D,0x0000031F},
--	{"0000001000010011111100001111111010011001000011100011000000100100",0x0000294E,0xFFFFF0A5,0x00000409,0x00001928,0xFFFFF93B,0x000002E6,0x00001928,0xFFFFF93B,0x000002E6},
--	{"0000001000010011111100001111110101000010110101000001000011000100",0x00003E09,0xFFFFE0FF,0x00000694,0x000025A0,0xFFFFEF0F,0x0000048F,0x000025A0,0xFFFFEF0F,0x0000048F},
--	{"0000001000010011111100001111111010011001000010100010100101100100",0x00003197,0xFFFFEA06,0x00000520,0x00001B42,0xFFFFF73B,0x0000032A,0x00001B42,0xFFFFF73B,0x0000032A},
--	{"0000001000010011111100001111111010011001000101100001100001100100",0x000022CB,0xFFFFF3FC,0x000003A3,0x00001449,0xFFFFFBD0,0x00000297,0x00001449,0xFFFFFBD0,0x00000297},
--	{"0000001000010011111100001111110101000010110110000010100101000100",0x00002A79,0xFFFFEFD2,0x00000433,0x00001585,0xFFFFFB92,0x0000028E,0x00001585,0xFFFFFB92,0x0000028E},
--	{"0000001000010011111100001111111010011001000011000100000110000100",0x00003249,0xFFFFEA92,0x000004F4,0x000019CB,0xFFFFF8CF,0x000002E1,0x000019CB,0xFFFFF8CF,0x000002E1},
--	{"0000001000010011111010101001010011011110000000100001100010100100",0x00002CEA,0xFFFFEE46,0x00000463,0x00001A5E,0xFFFFF83C,0x0000030D,0x00001A5E,0xFFFFF83C,0x0000030D},
--	{"0000001000010011111100001111110101000010110111000101000101000100",0x00003AE2,0xFFFFE422,0x00000600,0x00001C65,0xFFFFF62F,0x0000034B,0x00001C65,0xFFFFF62F,0x0000034B},
--	{"0000001000010011111100001111111010011001000110000001000110000100",0x000026A0,0xFFFFF1C2,0x000003F8,0x000010E5,0xFFFFFE56,0x0000022A,0x000010E5,0xFFFFFE56,0x0000022A},
--	{"0000001000010011111100001111111010011001001010000010100110100100",0x00002A7B,0xFFFFF063,0x00000417,0x000016FC,0xFFFFFAD7,0x000002B1,0x000016FC,0xFFFFFAD7,0x000002B1},
--	{"0000001000010011111100001111111010011001001100100001000011000100",0x00003092,0xFFFFEAB9,0x00000507,0x00001AE3,0xFFFFF783,0x00000323,0x00001AE3,0xFFFFF783,0x00000323},
--	{"0000001000010011111100001111111010011001000001000011100011100100",0x00003265,0xFFFFEBE8,0x000004AA,0x00001D65,0xFFFFF73F,0x00000321,0x00001D65,0xFFFFF73F,0x00000321},
--	{"0000001000010011111010101001010011011110000000100011000010000100",0x00002F14,0xFFFFECC2,0x000004A4,0x00001A8D,0xFFFFF7F3,0x0000031D,0x00001A8D,0xFFFFF7F3,0x0000031D},
--	{"0000001000010011111100001111110101000010110111000001000011100100",0x000035FB,0xFFFFE6D3,0x000005AC,0x00001B19,0xFFFFF712,0x00000338,0x00001B19,0xFFFFF712,0x00000338},
--	{"0000001000010011111100001111110101000010110110100010000100100100",0x00003519,0xFFFFE8CC,0x0000053A,0x00001A0F,0xFFFFF86E,0x000002F5,0x00001A0F,0xFFFFF86E,0x000002F5},
--	{"0000001000010011111100001111111010011001001011000010000101000100",0x0000364C,0xFFFFE879,0x00000541,0x00001A42,0xFFFFF8BA,0x000002E2,0x00001A42,0xFFFFF8BA,0x000002E2},
--	{"0000001000010011111010101001010011011110000000100001100011000100",0x000029BA,0xFFFFF09A,0x00000408,0x00001986,0xFFFFF8D9,0x000002FE,0x00001986,0xFFFFF8D9,0x000002FE},
--	{"0000001000010011111100001111110101000010110110100011100011100100",0x00003507,0xFFFFE961,0x00000518,0x00001B79,0xFFFFF775,0x00000325,0x00001B79,0xFFFFF775,0x00000325},
--	{"0000001000010011111100001111110101000010110111000011000110000100",0x00003AD5,0xFFFFE415,0x00000613,0x00001CB4,0xFFFFF66D,0x00000348,0x00001CB4,0xFFFFF66D,0x00000348},
--	{"0000001000010011111100001111111010011001000101100100000011100100",0x000023D1,0xFFFFF42B,0x0000038F,0x00001546,0xFFFFFBA0,0x0000029F,0x00001546,0xFFFFFBA0,0x0000029F},
--	{"0000001000010011111100001111111010011001000010100001100100100100",0x0000399E,0xFFFFE518,0x000005E7,0x00001990,0xFFFFF871,0x000002FB,0x00001990,0xFFFFF871,0x000002FB},
--	{"0000001000010011111100001111110101000010110110000010100101100100",0x00002EDE,0xFFFFEC93,0x000004B8,0x0000152C,0xFFFFFBB3,0x0000027E,0x0000152C,0xFFFFFBB3,0x0000027E},
--	{"0000001000010011111010101001010011011110000001000010100101100100",0x00003140,0xFFFFEBC9,0x000004BB,0x000016BE,0xFFFFFB0A,0x00000288,0x000016BE,0xFFFFFB0A,0x00000288},
--	{"0000001000010011111100001111111010011001000001100100000001100100",0x000030F6,0xFFFFEB89,0x000004CD,0x0000185D,0xFFFFF95A,0x000002D9,0x0000185D,0xFFFFF95A,0x000002D9},
--	{"0000001000010011111100001111111010011001000000100011100001000100",0x0000389C,0xFFFFE65A,0x000005A2,0x0000195D,0xFFFFF8C8,0x000002E8,0x0000195D,0xFFFFF8C8,0x000002E8},
--	{"0000001000010011111100001111111010011001000001000010000100000100",0x0000362B,0xFFFFE9EC,0x000004F6,0x00001605,0xFFFFFC1C,0x00000263,0x00001605,0xFFFFFC1C,0x00000263},
--	{"0000001000010011111100001111111010011001001010100001100101100100",0x00002946,0xFFFFF04F,0x00000426,0x000015BA,0xFFFFFB2F,0x000002A3,0x000015BA,0xFFFFFB2F,0x000002A3},
--	{"0000001000010011111100001111111010011001000010000010000110000100",0x0000368E,0xFFFFE837,0x0000054A,0x000017D7,0xFFFFF9EB,0x000002BA,0x000017D7,0xFFFFF9EB,0x000002BA},
--	{"0000001000010011111100001111110101000010110110100010100001000100",0x00002E74,0xFFFFEBE8,0x000004DA,0x00001DD6,0xFFFFF57E,0x00000379,0x00001DD6,0xFFFFF57E,0x00000379},
--	{"0000001000010011111100001111111010011001000001000001100101000100",0x0000322D,0xFFFFEAA8,0x000004F5,0x00001B55,0xFFFFF7DD,0x0000030B,0x00001B55,0xFFFFF7DD,0x0000030B},
--	{"0000001000010011111100001111111010011001000110000001100100000100",0x00002A29,0xFFFFF07B,0x00000416,0x00001671,0xFFFFFB3E,0x0000029F,0x00001671,0xFFFFFB3E,0x0000029F},
--	{"0000001000010011111100001111110101000010110110100010000100000100",0x000030F6,0xFFFFEB89,0x000004CD,0x00001815,0xFFFFF9AE,0x000002C9,0x00001815,0xFFFFF9AE,0x000002C9},
--	{"0000001000010011111100001111111010011001000011100001000011100100",0x0000265F,0xFFFFF1CB,0x000003D5,0x00001ED2,0xFFFFF539,0x0000037A,0x00001ED2,0xFFFFF539,0x0000037A},
--	{"0000001000010011111100001111111010011001000101100010000110000100",0x000027A8,0xFFFFF10D,0x00000413,0x000014B5,0xFFFFFBA1,0x00000299,0x000014B5,0xFFFFFBA1,0x00000299},
--	{"0000001000010011111100001111111010011001000001000011000001100100",0x00002CEE,0xFFFFEDF6,0x00000476,0x00001A99,0xFFFFF83E,0x00000305,0x00001A99,0xFFFFF83E,0x00000305},
--	{"0000001000010011111100001111111010011001000001100100000011000100",0x0000346C,0xFFFFEA17,0x000004EF,0x00001D38,0xFFFFF69F,0x0000033D,0x00001D38,0xFFFFF69F,0x0000033D},
--	{"0000001000010011111100001111110101000010110110100010100101000100",0x00002DBB,0xFFFFED35,0x00000490,0x000018C1,0xFFFFF930,0x000002DA,0x000018C1,0xFFFFF930,0x000002DA},
--	{"0000001000010011111100001111111010011001000001000010100100100100",0x000038DF,0xFFFFE8A7,0x0000051E,0x00001B59,0xFFFFF915,0x000002D3,0x00001B59,0xFFFFF915,0x000002D3},
--	{"0000001000010011111100001111111010011001000010000000100101000100",0x00003384,0xFFFFE979,0x00000524,0x00001AF3,0xFFFFF74C,0x0000032F,0x00001AF3,0xFFFFF74C,0x0000032F},
--	{"0000001000010011111100001111111010011001000110000001100001100100",0x0000258B,0xFFFFF2AE,0x000003CB,0x0000190C,0xFFFFF93E,0x000002EF,0x0000190C,0xFFFFF93E,0x000002EF},
--	{"0000001000010011111100001111111010011001000100000011100010000100",0x000034F1,0xFFFFE84B,0x0000055E,0x00001CB8,0xFFFFF670,0x0000034A,0x00001CB8,0xFFFFF670,0x0000034A},
--	{"0000001000010011111100001111111010011001000011000010000100000100",0x000030FB,0xFFFFECD2,0x00000488,0x00001BF4,0xFFFFF821,0x00000302,0x00001BF4,0xFFFFF821,0x00000302},
--	{"0000001000010011111100001111111010011001000001100011000001000100",0x000036A6,0xFFFFE815,0x00000556,0x000018FD,0xFFFFF925,0x000002DF,0x000018FD,0xFFFFF925,0x000002DF},
--	{"0000001000010011111010101001010011011110000000100011000001000100",0x0000302A,0xFFFFEB79,0x000004E0,0x00001C11,0xFFFFF694,0x00000358,0x00001C11,0xFFFFF694,0x00000358},
--	{"0000001000010011111100001111111010011001000110000001000100100100",0x00002555,0xFFFFF2C4,0x000003CB,0x000017E3,0xFFFFFA1F,0x000002CB,0x000017E3,0xFFFFFA1F,0x000002CB},
--	{"0000001000010011111100001111111010011001000010100011000101100100",0x000032A3,0xFFFFE933,0x00000544,0x000019D3,0xFFFFF81A,0x00000306,0x000019D3,0xFFFFF81A,0x00000306},
--	{"0000001000010011111100001111110101000010110110000101000100000100",0x00002B91,0xFFFFED81,0x000004A9,0x0000158B,0xFFFFFAB9,0x000002AC,0x0000158B,0xFFFFFAB9,0x000002AC},
--	{"0000001000010011111100001111111010011001000011100010000011000100",0x00003537,0xFFFFE912,0x0000052C,0x00001C8A,0xFFFFF754,0x0000031B,0x00001C8A,0xFFFFF754,0x0000031B},
--	{"0000001000010011111010101001010011011110000001100011000110000100",0x000032E1,0xFFFFEA5A,0x000004F9,0x000017B4,0xFFFFF9D9,0x000002C2,0x000017B4,0xFFFFF9D9,0x000002C2},
--	{"0000001000010011111100001111110101000010110100100001000011000100",0x00003B76,0xFFFFE330,0x00000636,0x000026FB,0xFFFFEF06,0x00000481,0x000026FB,0xFFFFEF06,0x00000481},
--	{"0000001000010011111100001111111010011001000001000010000101000100",0x0000320C,0xFFFFEB84,0x000004C3,0x00001A3A,0xFFFFF8E9,0x000002DF,0x00001A3A,0xFFFFF8E9,0x000002DF},
--	{"0000001000010011111100001111111010011001000000100011100110000100",0x0000317D,0xFFFFEA1F,0x00000515,0x00002100,0xFFFFF31B,0x000003DD,0x00002100,0xFFFFF31B,0x000003DD},
--	{"0000001000010011111100001111110101000010110101000011000101100100",0x00003DCB,0xFFFFE0B4,0x000006B4,0x00002160,0xFFFFF269,0x000003F0,0x00002160,0xFFFFF269,0x000003F0},
--	{"0000001000010011111100001111111010011001000101100001100011000100",0x00002737,0xFFFFF218,0x000003E1,0x000015B5,0xFFFFFB8F,0x0000029C,0x000015B5,0xFFFFFB8F,0x0000029C},
--	{"0000001000010011111010101001010011011110000000100011000110000100",0x0000318F,0xFFFFEB3F,0x000004D8,0x00001938,0xFFFFF8E9,0x000002EB,0x00001938,0xFFFFF8E9,0x000002EB},
--	{"0000001000010011111100001111111010011001000100000100100011000100",0x000031BD,0xFFFFE9DE,0x00000527,0x000018A7,0xFFFFF8CA,0x000002ED,0x000018A7,0xFFFFF8CA,0x000002ED},
--	{"0000001000010011111100001111110101000010110110100011100010000100",0x00002F77,0xFFFFEC2F,0x000004B4,0x00001D25,0xFFFFF61B,0x0000035D,0x00001D25,0xFFFFF61B,0x0000035D},
--	{"0000001000010011111100001111111010011001000011100100100100000100",0x00002CCA,0xFFFFEDB3,0x0000047C,0x00001FBD,0xFFFFF4A7,0x00000391,0x00001FBD,0xFFFFF4A7,0x00000391},
--	{"0000001000010011111100001111110101000010110101000011100010100100",0x00003FF6,0xFFFFE058,0x000006A2,0x000024CD,0xFFFFF026,0x00000452,0x000024CD,0xFFFFF026,0x00000452},
--	{"0000001000010011111100001111111010011001000010100011100011100100",0x00003161,0xFFFFEAC8,0x000004F3,0x00001BB6,0xFFFFF72A,0x0000032B,0x00001BB6,0xFFFFF72A,0x0000032B},
--	{"0000001000010011111100001111110101000010110110000011100010100100",0x00002EA0,0xFFFFECA6,0x000004B7,0x000018C2,0xFFFFF94E,0x000002E1,0x000018C2,0xFFFFF94E,0x000002E1},
--	{"0000001000010011111100001111111010011001000110000010000110000100",0x00002F62,0xFFFFEC9E,0x000004B8,0x00001531,0xFFFFFBCD,0x00000285,0x00001531,0xFFFFFBCD,0x00000285},
--	{"0000001000010011111100001111111010011001000001000100000010100100",0x00003013,0xFFFFEBD6,0x000004C2,0x00001B01,0xFFFFF802,0x000002FF,0x00001B01,0xFFFFF802,0x000002FF},
--	{"0000001000010011111100001111111010011001000110000011000001100100",0x00002972,0xFFFFF08D,0x00000417,0x00001A32,0xFFFFF8A4,0x00000305,0x00001A32,0xFFFFF8A4,0x00000305},
--	{"0000001000010011111100001111110101000010110110000010000011100100",0x00002E95,0xFFFFED94,0x00000487,0x00001529,0xFFFFFC26,0x00000271,0x00001529,0xFFFFFC26,0x00000271},
--	{"0000001000010011111100001111111010011001000010100001000010000100",0x00002D6A,0xFFFFEC79,0x000004C1,0x00001AE2,0xFFFFF725,0x00000337,0x00001AE2,0xFFFFF725,0x00000337},
--	{"0000001000010011111100001111111010011001000000100001100010000100",0x000036B4,0xFFFFE704,0x00000591,0x00001E7E,0xFFFFF51C,0x00000383,0x00001E7E,0xFFFFF51C,0x00000383},
--	{"0000001000010011111100001111111010011001000001000001100001000100",0x00002A6F,0xFFFFEF70,0x00000443,0x00001BAA,0xFFFFF752,0x00000336,0x00001BAA,0xFFFFF752,0x00000336},
--	{"0000001000010011111100001111111010011001000110000011100101000100",0x00002C66,0xFFFFEF5F,0x0000043A,0x000019F7,0xFFFFF931,0x000002EC,0x000019F7,0xFFFFF931,0x000002EC},
--	{"0000001000010011111010101001010011011110000001100011000111000100",0x00003852,0xFFFFE6AB,0x00000590,0x000019C1,0xFFFFF8B1,0x000002E5,0x000019C1,0xFFFFF8B1,0x000002E5},
--	{"0000001000010011111100001111110101000010110110100011000100100100",0x00003521,0xFFFFE932,0x00000523,0x000018A9,0xFFFFF96B,0x000002D0,0x000018A9,0xFFFFF96B,0x000002D0},
--	{"0000001000010011111100001111111010011001000001100010000101100100",0x000031B9,0xFFFFEB36,0x000004D0,0x00001D65,0xFFFFF612,0x0000035D,0x00001D65,0xFFFFF612,0x0000035D},
--	{"0000001000010011111100001111110101000010110101000001000001100100",0x00003ED0,0xFFFFE135,0x00000679,0x00002351,0xFFFFF0FE,0x00000433,0x00002351,0xFFFFF0FE,0x00000433},
--	{"0000001000010011111100001111111010011001000010100010000011100100",0x000033ED,0xFFFFE91A,0x00000541,0x00001C93,0xFFFFF6A0,0x0000034A,0x00001C93,0xFFFFF6A0,0x0000034A},
--	{"0000001000010011111010101001010011011110000000100001100001000100",0x0000356F,0xFFFFE8F7,0x00000530,0x000016BF,0xFFFFFA85,0x000002AB,0x000016BF,0xFFFFFA85,0x000002AB},
--	{"0000001000010011111100001111111010011001000110000100000011100100",0x00002304,0xFFFFF4F3,0x00000364,0x000017CC,0xFFFFFA41,0x000002CA,0x000017CC,0xFFFFFA41,0x000002CA},
--	{"0000001000010011111100001111111010011001000101100001000101100100",0x00002887,0xFFFFEFD7,0x00000450,0x00001474,0xFFFFFB94,0x00000299,0x00001474,0xFFFFFB94,0x00000299},
--	{"0000001000010011111100001111111010011001000001100011000001100100",0x00003D0B,0xFFFFE416,0x000005EF,0x00001C7E,0xFFFFF71D,0x00000325,0x00001C7E,0xFFFFF71D,0x00000325},
--	{"0000001000010011111100001111111010011001000010000001000011100100",0x00003185,0xFFFFEAFA,0x000004E4,0x00001A12,0xFFFFF83C,0x00000303,0x00001A12,0xFFFFF83C,0x00000303},
--	{"0000001000010011111100001111111010011001000010100001100101000100",0x00003032,0xFFFFEAE6,0x000004FC,0x00001B2A,0xFFFFF73F,0x0000032B,0x00001B2A,0xFFFFF73F,0x0000032B},
--	{"0000001000010011111100001111110101000010110110000011100011000100",0x00002691,0xFFFFF22D,0x000003D6,0x00001700,0xFFFFFA6E,0x000002C0,0x00001700,0xFFFFFA6E,0x000002C0},
--	{"0000001000010011111100001111111010011001000000100001100010100100",0x00002B2F,0xFFFFEEC4,0x0000044B,0x0000215F,0xFFFFF33F,0x000003D2,0x0000215F,0xFFFFF33F,0x000003D2},
--	{"0000001000010011111100001111111010011001000010100100000110000100",0x000034AA,0xFFFFE706,0x000005B1,0x00001B28,0xFFFFF6B5,0x00000349,0x00001B28,0xFFFFF6B5,0x00000349},
--	{"0000001000010011111100001111110101000010110110100010100101100100",0x0000307E,0xFFFFEB38,0x000004E6,0x00001A22,0xFFFFF83F,0x00000300,0x00001A22,0xFFFFF83F,0x00000300},
--	{"0000001000010011111100001111111010011001000001100001100010100100",0x000038D6,0xFFFFE6D8,0x0000057C,0x00001B24,0xFFFFF7E4,0x00000307,0x00001B24,0xFFFFF7E4,0x00000307},
--	{"0000001000010011111100001111111010011001000110000011000001000100",0x00002757,0xFFFFF1E8,0x000003DD,0x000017F5,0xFFFFFA15,0x000002C8,0x000017F5,0xFFFFFA15,0x000002C8},
--	{"0000001000010011111100001111111010011001000010000011000110000100",0x000031FC,0xFFFFEB3E,0x000004CE,0x00001B4C,0xFFFFF7AD,0x00000319,0x00001B4C,0xFFFFF7AD,0x00000319},
--	{"0000001000010011111100001111111010011001001100000001100001100100",0x00002933,0xFFFFF073,0x0000040E,0x00001C3C,0xFFFFF701,0x0000033C,0x00001C3C,0xFFFFF701,0x0000033C},
--	{"0000001000010011111100001111110101000010110100100001100010100100",0x000040BB,0xFFFFE066,0x0000069A,0x0000257F,0xFFFFF08A,0x00000435,0x0000257F,0xFFFFF08A,0x00000435},
--	{"0000001000010011111100001111111010011001000100000001000010100100",0x0000305B,0xFFFFEB9B,0x000004CB,0x00001996,0xFFFFF846,0x00000308,0x00001996,0xFFFFF846,0x00000308},
--	{"0000001000010011111100001111111010011001000001100100100010000100",0x000039C0,0xFFFFE5D3,0x000005B0,0x00001A8D,0xFFFFF7DA,0x00000313,0x00001A8D,0xFFFFF7DA,0x00000313},
--	{"0000001000010011111010101001010011011110000000100001000010100100",0x00002E23,0xFFFFED3F,0x0000048F,0x0000189D,0xFFFFF94C,0x000002DE,0x0000189D,0xFFFFF94C,0x000002DE},
--	{"0000001000010011111010101001010011011110000000100001100110000100",0x0000332B,0xFFFFE9F1,0x00000516,0x000018E6,0xFFFFF8FE,0x000002EC,0x000018E6,0xFFFFF8FE,0x000002EC},
--	{"0000001000010011111100001111111010011001000010000011100011000100",0x000034A0,0xFFFFEA44,0x000004E4,0x00001ECD,0xFFFFF5B4,0x00000364,0x00001ECD,0xFFFFF5B4,0x00000364},
--	{"0000001000010011111100001111110101000010110100100100000100000100",0x0000448C,0xFFFFDF34,0x000006A8,0x0000231C,0xFFFFF286,0x000003D9,0x0000231C,0xFFFFF286,0x000003D9},
--	{"0000001000010011111010101001010011011110000001100010000101000100",0x00002D8C,0xFFFFEE65,0x00000456,0x000018B1,0xFFFFF9C8,0x000002C8,0x000018B1,0xFFFFF9C8,0x000002C8},
--	{"0000001000010011111100001111111010011001000001100001100100000100",0x00003527,0xFFFFE9BF,0x000004FD,0x00001D23,0xFFFFF69F,0x00000342,0x00001D23,0xFFFFF69F,0x00000342},
--	{"0000001000010011111100001111110101000010110111000011100010100100",0x00002C51,0xFFFFEDC3,0x00000483,0x00001BE0,0xFFFFF720,0x0000032D,0x00001BE0,0xFFFFF720,0x0000032D},
--	{"0000001000010011111100001111111010011001000010100011000001000100",0x00002C6C,0xFFFFECEB,0x000004B7,0x00001C86,0xFFFFF5E7,0x00000371,0x00001C86,0xFFFFF5E7,0x00000371},
--	{"0000001000010011111100001111111010011001000001000101000101000100",0x000037CF,0xFFFFE6BE,0x00000599,0x000018CD,0xFFFFF967,0x000002C7,0x000018CD,0xFFFFF967,0x000002C7},
--	{"0000001000010011111100001111111010011001000100000011000101100100",0x00002E6F,0xFFFFED1D,0x0000048E,0x00001ADC,0xFFFFF7F4,0x0000030E,0x00001ADC,0xFFFFF7F4,0x0000030E},
--	{"0000001000010011111100001111110101000010110101000010100110000100",0x00003FF3,0xFFFFDF13,0x000006F9,0x000025BF,0xFFFFEEEE,0x00000497,0x000025BF,0xFFFFEEEE,0x00000497},
--	{"0000001000010011111100001111110101000010110111000101000100000100",0x00004135,0xFFFFDF97,0x000006CC,0x00001D52,0xFFFFF541,0x00000383,0x00001D52,0xFFFFF541,0x00000383},
--	{"0000001000010011111100001111110101000010110111000010000011100100",0x00002EA9,0xFFFFEDDB,0x0000045F,0x0000197C,0xFFFFF8E1,0x000002F0,0x0000197C,0xFFFFF8E1,0x000002F0},
--	{"0000001000010011111010101001010011011110000001000011000010000100",0x0000345C,0xFFFFE922,0x00000532,0x00001922,0xFFFFF8C7,0x000002F1,0x00001922,0xFFFFF8C7,0x000002F1},
--	{"0000001000010011111100001111111010011001000001100100000100100100",0x000035C4,0xFFFFE8FE,0x00000521,0x00001C87,0xFFFFF6F3,0x00000330,0x00001C87,0xFFFFF6F3,0x00000330},
--	{"0000001000010011111100001111110101000010110110000011000101100100",0x00002888,0xFFFFF08A,0x0000041E,0x0000150F,0xFFFFFB87,0x00000291,0x0000150F,0xFFFFFB87,0x00000291},
--	{"0000001000010011111100001111111010011001000010100001000100100100",0x000035E9,0xFFFFE657,0x000005CC,0x00001BD6,0xFFFFF664,0x00000355,0x00001BD6,0xFFFFF664,0x00000355},
--	{"0000001000010011111100001111111010011001000101100100100011100100",0x00002F94,0xFFFFEBD0,0x000004E5,0x00001333,0xFFFFFCA7,0x00000266,0x00001333,0xFFFFFCA7,0x00000266},
--	{"0000001000010011111100001111111010011001000110000001100101100100",0x000029E7,0xFFFFF009,0x00000433,0x0000144A,0xFFFFFC37,0x0000027D,0x0000144A,0xFFFFFC37,0x0000027D},
--	{"0000001000010011111100001111111010011001001011000001100101000100",0x00003418,0xFFFFE979,0x00000521,0x00001D33,0xFFFFF66B,0x0000034A,0x00001D33,0xFFFFF66B,0x0000034A},
--	{"0000001000010011111010101001010011011110000001000100000011100100",0x00003656,0xFFFFE79D,0x0000057A,0x000017C2,0xFFFFF992,0x000002D4,0x000017C2,0xFFFFF992,0x000002D4},
--	{"0000001000010011111100001111111010011001000011000100000011000100",0x00002EB2,0xFFFFECFE,0x00000493,0x00001F2A,0xFFFFF543,0x0000037B,0x00001F2A,0xFFFFF543,0x0000037B},
--	{"0000001000010011111100001111111010011001000000100001000100100100",0x00002FC1,0xFFFFEB3F,0x000004E8,0x00001CD0,0xFFFFF5F7,0x00000364,0x00001CD0,0xFFFFF5F7,0x00000364},
--	{"0000001000010011111100001111111010011001000011000001000100100100",0x0000307B,0xFFFFEB66,0x000004DE,0x00001953,0xFFFFF8ED,0x000002E4,0x00001953,0xFFFFF8ED,0x000002E4},
--	{"0000001000010011111100001111110101000010110110100001100010000100",0x00002CAA,0xFFFFED07,0x000004AC,0x0000251C,0xFFFFF086,0x0000044D,0x0000251C,0xFFFFF086,0x0000044D},
--	{"0000001000010011111010101001010011011110000001000011100101000100",0x00002C94,0xFFFFEE5F,0x0000045B,0x000018D7,0xFFFFF900,0x000002EB,0x000018D7,0xFFFFF900,0x000002EB},
--	{"0000001000010011111100001111111010011001000000100001100001100100",0x000031F1,0xFFFFE9BE,0x0000052E,0x00001DDF,0xFFFFF558,0x00000380,0x00001DDF,0xFFFFF558,0x00000380},
--	{"0000001000010011111100001111111010011001000011100101000011000100",0x00002603,0xFFFFF1E9,0x000003DA,0x00001B37,0xFFFFF75A,0x0000032F,0x00001B37,0xFFFFF75A,0x0000032F},
--	{"0000001000010011111100001111110101000010110110100011000001000100",0x00003992,0xFFFFE4F9,0x000005EB,0x00001775,0xFFFFF9B8,0x000002C2,0x00001775,0xFFFFF9B8,0x000002C2},
--	{"0000001000010011111100001111111010011001000110000100100101100100",0x000029DA,0xFFFFF052,0x0000041F,0x000016E2,0xFFFFFA99,0x000002BB,0x000016E2,0xFFFFFA99,0x000002BB},
--	{"0000001000010011111100001111111010011001000100000001000001100100",0x00002FF2,0xFFFFEB8F,0x000004DF,0x00001AF6,0xFFFFF7A1,0x00000321,0x00001AF6,0xFFFFF7A1,0x00000321},
--	{"0000001000010011111100001111111010011001000101100000100011100100",0x00002590,0xFFFFF222,0x000003EE,0x0000130B,0xFFFFFCC9,0x00000268,0x0000130B,0xFFFFFCC9,0x00000268},
--	{"0000001000010011111100001111111010011001000000100100000001100100",0x000038A2,0xFFFFE65F,0x000005A2,0x000018B1,0xFFFFF917,0x000002E1,0x000018B1,0xFFFFF917,0x000002E1},
--	{"0000001000010011111100001111110101000010110111000100100011100100",0x000035FD,0xFFFFE73C,0x0000058D,0x00001BB3,0xFFFFF6E1,0x00000337,0x00001BB3,0xFFFFF6E1,0x00000337},
--	{"0000001000010011111100001111111010011001000100000011100011000100",0x00002AB7,0xFFFFEF98,0x00000429,0x00001F35,0xFFFFF539,0x0000037C,0x00001F35,0xFFFFF539,0x0000037C},
--	{"0000001000010011111100001111111010011001000010100000100101000100",0x000034BA,0xFFFFE73D,0x000005A6,0x000018A6,0xFFFFF888,0x000002FB,0x000018A6,0xFFFFF888,0x000002FB},
--	{"0000001000010011111100001111111010011001000001100011100001000100",0x000032EA,0xFFFFEA78,0x000004F4,0x00001AB6,0xFFFFF812,0x00000308,0x00001AB6,0xFFFFF812,0x00000308},
--	{"0000001000010011111100001111111010011001000011000011000001000100",0x00002BE9,0xFFFFEE9A,0x00000457,0x00001942,0xFFFFF8D2,0x000002F2,0x00001942,0xFFFFF8D2,0x000002F2},
--	{"0000001000010011111100001111111010011001000100000101000100100100",0x00002FAB,0xFFFFEB76,0x000004E1,0x00001DCA,0xFFFFF57D,0x00000378,0x00001DCA,0xFFFFF57D,0x00000378},
--	{"0000001000010011111100001111111010011001001011100010100001000100",0x0000330A,0xFFFFE9E1,0x0000051B,0x00001CC4,0xFFFFF6DF,0x00000335,0x00001CC4,0xFFFFF6DF,0x00000335},
--	{"0000001000010011111100001111111010011001000110000010100010100100",0x000027D8,0xFFFFF276,0x000003BF,0x0000178A,0xFFFFFABF,0x000002B5,0x0000178A,0xFFFFFABF,0x000002B5},
--	{"0000001000010011111100001111110101000010110111000011100001100100",0x0000340A,0xFFFFE86D,0x00000562,0x00001B85,0xFFFFF719,0x0000032F,0x00001B85,0xFFFFF719,0x0000032F},
--	{"0000001000010011111010101001010011011110000001100011000010000100",0x00003879,0xFFFFE73F,0x00000578,0x0000161C,0xFFFFFB6B,0x00000281,0x0000161C,0xFFFFFB6B,0x00000281},
--	{"0000001000010011111100001111111010011001000110000100000001100100",0x00002879,0xFFFFF0F8,0x0000040A,0x00001749,0xFFFFFA37,0x000002CC,0x00001749,0xFFFFFA37,0x000002CC},
--	{"0000001000010011111100001111111010011001000001000011100101100100",0x00002C3A,0xFFFFEEA0,0x0000044F,0x00001D57,0xFFFFF6C2,0x00000332,0x00001D57,0xFFFFF6C2,0x00000332},
--	{"0000001000010011111010101001010011011110000000100001100101100100",0x000035BB,0xFFFFE90D,0x0000052A,0x000017D9,0xFFFFF9F5,0x000002C3,0x000017D9,0xFFFFF9F5,0x000002C3},
--	{"0000001000010011111010101001010011011110000001000001000100100100",0x000031F1,0xFFFFEAD4,0x000004ED,0x00001F10,0xFFFFF539,0x0000037D,0x00001F10,0xFFFFF539,0x0000037D},
--	{"0000001000010011111100001111111010011001000100000010100000100100",0x00002A1A,0xFFFFEFAD,0x00000430,0x00001D47,0xFFFFF62F,0x0000035E,0x00001D47,0xFFFFF62F,0x0000035E},
--	{"0000001000010011111100001111111010011001000101100100100100100100",0x00002AF0,0xFFFFEEDC,0x00000465,0x0000145F,0xFFFFFBEB,0x00000281,0x0000145F,0xFFFFFBEB,0x00000281},
--	{"0000001000010011111100001111111010011001000110000011000101100100",0x00002657,0xFFFFF2E0,0x000003B6,0x00001664,0xFFFFFB37,0x000002A2,0x00001664,0xFFFFFB37,0x000002A2},
--	{"0000001000010011111100001111110101000010110100000011100001100100",0x00003183,0xFFFFE9F1,0x0000052B,0x00002020,0xFFFFF3CE,0x000003C1,0x00002020,0xFFFFF3CE,0x000003C1},
--	{"0000001000010011111100001111110101000010110001100010100011100100",0x00003240,0xFFFFEB65,0x000004C7,0x00002425,0xFFFFF245,0x000003F3,0x00002425,0xFFFFF245,0x000003F3},
--	{"0000001000010011111010101001010011011110001100100001000100000100",0x000023D0,0xFFFFF400,0x00000397,0x00001345,0xFFFFFD6B,0x00000241,0x00001345,0xFFFFFD6B,0x00000241},
--	{"0000001000010011111100001111110101000010110011100011100010100100",0x00003440,0xFFFFE872,0x0000055B,0x00002247,0xFFFFF296,0x000003E8,0x00002247,0xFFFFF296,0x000003E8},
--	{"0000001000010011111100001111110101000010110100000100100100000100",0x00003275,0xFFFFE970,0x00000538,0x00001F94,0xFFFFF429,0x000003AD,0x00001F94,0xFFFFF429,0x000003AD},
--	{"0000001000010011111100001111110101000010110001100100000010100100",0x00003918,0xFFFFE5DA,0x000005B6,0x000024FC,0xFFFFF106,0x00000426,0x000024FC,0xFFFFF106,0x00000426},
--	{"0000001000010011111010101001010011011110000001100010000001000100",0x0000334B,0xFFFFEA39,0x000004FD,0x00001983,0xFFFFF8F6,0x000002E2,0x00001983,0xFFFFF8F6,0x000002E2},
--	{"0000001000010011111100001111110101000010110001100100100110000100",0x00003B59,0xFFFFE4D0,0x000005DA,0x00002605,0xFFFFF090,0x00000439,0x00002605,0xFFFFF090,0x00000439},
--	{"0000001000010011111100001111110101000010110100000011000100100100",0x00003251,0xFFFFEA46,0x00000511,0x00002781,0xFFFFEF84,0x00000470,0x00002781,0xFFFFEF84,0x00000470},
--	{"0000001000010011111100001111110101000010110010100011000101100100",0x00003304,0xFFFFE926,0x00000542,0x00001EE9,0xFFFFF4E4,0x0000038B,0x00001EE9,0xFFFFF4E4,0x0000038B},
--	{"0000001000010011111100001111110101000010110011000011100011000100",0x00002F4C,0xFFFFEC0C,0x000004C4,0x00001E49,0xFFFFF578,0x00000374,0x00001E49,0xFFFFF578,0x00000374},
--	{"0000001000010011111010101001010011011110000111000010000101100100",0x00002034,0xFFFFF692,0x0000034C,0x000014B8,0xFFFFFC5B,0x00000294,0x000014B8,0xFFFFFC5B,0x00000294},
--	{"0000001000010011111100001111110101000010110011100100100100100100",0x0000385F,0xFFFFE513,0x000005F3,0x000024E7,0xFFFFF053,0x00000450,0x000024E7,0xFFFFF053,0x00000450},
--	{"0000001000010011111010101001010011011110000111000100000011100100",0x00001D70,0xFFFFF821,0x0000030F,0x00001541,0xFFFFFBB4,0x000002B0,0x00001541,0xFFFFFBB4,0x000002B0},
--	{"0000001000010011111100001111110101000010110100000010000010000100",0x000034EB,0xFFFFE7FF,0x00000575,0x000019B4,0xFFFFF836,0x00000308,0x000019B4,0xFFFFF836,0x00000308},
--	{"0000001000010011111100001111110101000010110100000101000011100100",0x000037C9,0xFFFFE5D4,0x000005CD,0x000026A1,0xFFFFEF0C,0x00000491,0x000026A1,0xFFFFEF0C,0x00000491},
--	{"0000001000010011111010101001010011011110000100100001100101000100",0x00002918,0xFFFFF148,0x000003E9,0x00001A49,0xFFFFF94C,0x000002CF,0x00001A49,0xFFFFF94C,0x000002CF},
--	{"0000001000010011111100001111110101000010110010100100000001100100",0x00002F90,0xFFFFEAB5,0x00000514,0x00001707,0xFFFFF9C7,0x000002C4,0x00001707,0xFFFFF9C7,0x000002C4},
--	{"0000001000010011111010101001010011011110000001100010000001100100",0x0000327E,0xFFFFEA99,0x000004F4,0x0000194F,0xFFFFF929,0x000002DC,0x0000194F,0xFFFFF929,0x000002DC},
--	{"0000001000010011111100001111110101000010110001100100000010000100",0x0000326F,0xFFFFE9CF,0x00000519,0x00002240,0xFFFFF299,0x000003E7,0x00002240,0xFFFFF299,0x000003E7},
--	{"0000001000010011111010101001010011011110001100100001000100100100",0x000022FB,0xFFFFF4C6,0x00000371,0x00001506,0xFFFFFC73,0x00000265,0x00001506,0xFFFFFC73,0x00000265},
--	{"0000001000010011111100001111110101000010110010100011100100100100",0x00003AD6,0xFFFFE470,0x000005FE,0x00001F03,0xFFFFF4F3,0x00000387,0x00001F03,0xFFFFF4F3,0x00000387},
--	{"0000001000010011111010101001010011011110001000000001000100100100",0x00001F11,0xFFFFF756,0x00000332,0x00001666,0xFFFFFB8A,0x000002B2,0x00001666,0xFFFFFB8A,0x000002B2},
--	{"0000001000010011111010101001010011011110000000100011100010100100",0x00002A5F,0xFFFFEFA7,0x00000430,0x00001943,0xFFFFF8C6,0x000002F7,0x00001943,0xFFFFF8C6,0x000002F7},
--	{"0000001000010011111010101001010011011110000101100101000011100100",0x0000235E,0xFFFFF3B4,0x000003B3,0x00001489,0xFFFFFBCF,0x0000029B,0x00001489,0xFFFFFBCF,0x0000029B},
--	{"0000001000010011111100001111110101000010110011000011100010100100",0x00003570,0xFFFFE780,0x0000058D,0x00001B1D,0xFFFFF767,0x00000325,0x00001B1D,0xFFFFF767,0x00000325},
--	{"0000001000010011111010101001010011011110000001000010000001100100",0x00003678,0xFFFFE7C3,0x00000569,0x00001831,0xFFFFF98E,0x000002C8,0x00001831,0xFFFFF98E,0x000002C8},
--	{"0000001000010011111010101001010011011110001000000001100001100100",0x000020B9,0xFFFFF625,0x0000035A,0x000015C5,0xFFFFFB8A,0x000002B5,0x000015C5,0xFFFFFB8A,0x000002B5},
--	{"0000001000010011111100001111110101000010110001100011000110000100",0x00003985,0xFFFFE529,0x000005DD,0x00002165,0xFFFFF351,0x000003C5,0x00002165,0xFFFFF351,0x000003C5},
--	{"0000001000010011111100001111110101000010110100000010000001100100",0x0000322A,0xFFFFE99D,0x00000535,0x000019A1,0xFFFFF844,0x00000305,0x000019A1,0xFFFFF844,0x00000305},
--	{"0000001000010011111100001111110101000010110100000101000100000100",0x000033ED,0xFFFFE834,0x00000571,0x00002094,0xFFFFF33A,0x000003DB,0x00002094,0xFFFFF33A,0x000003DB},
--	{"0000001000010011111010101001010011011110001000000100000011000100",0x00001D10,0xFFFFF84D,0x0000030B,0x00001659,0xFFFFFB0A,0x000002CB,0x00001659,0xFFFFFB0A,0x000002CB},
--	{"0000001000010011111010101001010011011110000111000001000100100100",0x0000210F,0xFFFFF644,0x00000355,0x00001A4A,0xFFFFF90F,0x00000310,0x00001A4A,0xFFFFF90F,0x00000310},
--	{"0000001000010011111010101001010011011110000101100100000101100100",0x00001CA8,0xFFFFF813,0x00000316,0x00001440,0xFFFFFC1C,0x0000029D,0x00001440,0xFFFFFC1C,0x0000029D},
--	{"0000001000010011111010101001010011011110001100100001000011000100",0x00002864,0xFFFFF15A,0x000003FA,0x0000137F,0xFFFFFD43,0x00000248,0x0000137F,0xFFFFFD43,0x00000248},
--	{"0000001000010011111100001111110101000010110100000100000110000100",0x00002CDB,0xFFFFECFD,0x000004A7,0x00002472,0xFFFFF0E1,0x00000437,0x00002472,0xFFFFF0E1,0x00000437},
--	{"0000001000010011111100001111110101000010110011000101000100000100",0x00003348,0xFFFFE8CA,0x00000554,0x00001E91,0xFFFFF4D4,0x00000392,0x00001E91,0xFFFFF4D4,0x00000392},
--	{"0000001000010011111100001111110101000010110001100100100101000100",0x00003989,0xFFFFE4BB,0x000005F8,0x00001ACB,0xFFFFF780,0x00000319,0x00001ACB,0xFFFFF780,0x00000319},
--	{"0000001000010011111100001111110101000010110010100010000100000100",0x00003238,0xFFFFEA09,0x0000051E,0x00001F08,0xFFFFF4F4,0x0000038C,0x00001F08,0xFFFFF4F4,0x0000038C},
--	{"0000001000010011111010101001010011011110000100100000100100000100",0x00002453,0xFFFFF3B0,0x0000038D,0x00001AED,0xFFFFF8A2,0x000002EA,0x00001AED,0xFFFFF8A2,0x000002EA},
--	{"0000001000010011111010101001010011011110000111000011000000100100",0x00002459,0xFFFFF409,0x000003A8,0x000017B5,0xFFFFFA53,0x000002E1,0x000017B5,0xFFFFFA53,0x000002E1},
--	{"0000001000010011111010101001010011011110000000100001000110000100",0x0000310D,0xFFFFEB78,0x000004D0,0x00001DC9,0xFFFFF5D5,0x00000368,0x00001DC9,0xFFFFF5D5,0x00000368},
--	{"0000001000010011111010101001010011011110000000100011000100000100",0x000031BF,0xFFFFECA3,0x00000498,0x00001DC9,0xFFFFF717,0x00000336,0x00001DC9,0xFFFFF717,0x00000336},
--	{"0000001000010011111100001111110101000010110011100010000100000100",0x00003896,0xFFFFE5DD,0x000005C5,0x000023E2,0xFFFFF1A1,0x00000416,0x000023E2,0xFFFFF1A1,0x00000416},
--	{"0000001000010011111010101001010011011110001100100011100100000100",0x000023CB,0xFFFFF4C8,0x00000372,0x00001C33,0xFFFFF7D5,0x0000032A,0x00001C33,0xFFFFF7D5,0x0000032A},
--	{"0000001000010011111100001111110101000010110100000010000011000100",0x00002F6B,0xFFFFEBF0,0x000004CE,0x00001C89,0xFFFFF689,0x0000034D,0x00001C89,0xFFFFF689,0x0000034D},
--	{"0000001000010011111100001111110101000010110011100011100100000100",0x00003E72,0xFFFFE211,0x0000065D,0x0000218D,0xFFFFF309,0x000003DC,0x0000218D,0xFFFFF309,0x000003DC},
--	{"0000001000010011111010101001010011011110000000100010000010000100",0x00002612,0xFFFFF2C3,0x000003AD,0x000019F7,0xFFFFF891,0x000002FE,0x000019F7,0xFFFFF891,0x000002FE},
--	{"0000001000010011111010101001010011011110000101100100000110000100",0x0000205D,0xFFFFF59F,0x00000372,0x000012E6,0xFFFFFD0A,0x00000270,0x000012E6,0xFFFFFD0A,0x00000270},
--	{"0000001000010011111100001111110101000010110010100010000100100100",0x00002ECB,0xFFFFEC47,0x000004BD,0x00001936,0xFFFFF8D9,0x000002E4,0x00001936,0xFFFFF8D9,0x000002E4},
--	{"0000001000010011111010101001010011011110000001100100100100000100",0x00002BDB,0xFFFFEE6D,0x00000458,0x00001852,0xFFFFF943,0x000002D9,0x00001852,0xFFFFF943,0x000002D9},
--	{"0000001000010011111010101001010011011110000100100100100100000100",0x00003387,0xFFFFE958,0x00000534,0x00001932,0xFFFFF8FA,0x000002E4,0x00001932,0xFFFFF8FA,0x000002E4},
--	{"0000001000010011111010101001010011011110000000100000100011000100",0x00002E3C,0xFFFFED26,0x00000495,0x00001858,0xFFFFF990,0x000002D1,0x00001858,0xFFFFF990,0x000002D1},
--	{"0000001000010011111010101001010011011110000000100010100101100100",0x000033B8,0xFFFFEA5C,0x000004F9,0x00001BD1,0xFFFFF76A,0x0000032E,0x00001BD1,0xFFFFF76A,0x0000032E},
--	{"0000001000010011111010101001010011011110000001100010100110000100",0x00002BCE,0xFFFFEEE9,0x00000443,0x00001982,0xFFFFF90D,0x000002DF,0x00001982,0xFFFFF90D,0x000002DF},
--	{"0000001000010011111100001111110101000010110100000100100011100100",0x00003495,0xFFFFE7D9,0x0000057B,0x00001D2A,0xFFFFF5A5,0x00000372,0x00001D2A,0xFFFFF5A5,0x00000372},
--	{"0000001000010011111100001111110101000010110010100011100011100100",0x000034B1,0xFFFFE88D,0x00000556,0x00002014,0xFFFFF43A,0x000003AA,0x00002014,0xFFFFF43A,0x000003AA},
--	{"0000001000010011111100001111110101000010110011000011000100100100",0x00002F96,0xFFFFEC84,0x000004AD,0x000024A2,0xFFFFF1CE,0x0000040A,0x000024A2,0xFFFFF1CE,0x0000040A},
--	{"0000001000010011111010101001010011011110000101100001000001100100",0x0000203B,0xFFFFF640,0x00000359,0x000014EC,0xFFFFFC14,0x0000029C,0x000014EC,0xFFFFFC14,0x0000029C},
--	{"0000001000010011111100001111110101000010110100000010100110000100",0x000034E2,0xFFFFE7B8,0x00000582,0x00001938,0xFFFFF872,0x000002FA,0x00001938,0xFFFFF872,0x000002FA},
--	{"0000001000010011111010101001010011011110000001100011000100100100",0x00002AC7,0xFFFFF0C1,0x000003F5,0x00002268,0xFFFFF39C,0x000003C9,0x00002268,0xFFFFF39C,0x000003C9},
--	{"0000001000010011111100001111110101000010110001100011000101000100",0x000036F6,0xFFFFE77F,0x00000571,0x000027D9,0xFFFFEF6F,0x00000461,0x000027D9,0xFFFFEF6F,0x00000461},
--	{"0000001000010011111010101001010011011110000100100011000100100100",0x00002BAB,0xFFFFF018,0x00000419,0x00002126,0xFFFFF4E2,0x0000038F,0x00002126,0xFFFFF4E2,0x0000038F},
--	{"0000001000010011111010101001010011011110001100100011100100100100",0x000028C4,0xFFFFF161,0x000003F8,0x0000180C,0xFFFFFA4B,0x000002C8,0x0000180C,0xFFFFFA4B,0x000002C8},
--	{"0000001000010011111100001111110101000010110010100010100001100100",0x00002F48,0xFFFFEB62,0x000004EE,0x00001912,0xFFFFF8C8,0x000002EA,0x00001912,0xFFFFF8C8,0x000002EA},
--	{"0000001000010011111100001111110101000010110011100010100001100100",0x000032DF,0xFFFFE911,0x00000545,0x00001F06,0xFFFFF485,0x0000039C,0x00001F06,0xFFFFF485,0x0000039C},
--	{"0000001000010011111100001111110101000010110100000100000101000100",0x000035B8,0xFFFFE74F,0x00000590,0x00001FD7,0xFFFFF410,0x000003AF,0x00001FD7,0xFFFFF410,0x000003AF},
--	{"0000001000010011111100001111110101000010110100000101000011000100",0x00003608,0xFFFFE6D7,0x000005A9,0x000024A6,0xFFFFF075,0x00000450,0x000024A6,0xFFFFF075,0x00000450},
--	{"0000001000010011111100001111110101000010110010100011100010000100",0x000030AB,0xFFFFEAED,0x000004F5,0x000019EE,0xFFFFF84E,0x000002FC,0x000019EE,0xFFFFF84E,0x000002FC},
--	{"0000001000010011111010101001010011011110000001100010000011000100",0x000030C6,0xFFFFEC92,0x0000049E,0x000019BB,0xFFFFF8F1,0x000002F3,0x000019BB,0xFFFFF8F1,0x000002F3},
--	{"0000001000010011111100001111110101000010110001100011000010100100",0x00003B27,0xFFFFE544,0x000005C1,0x00002697,0xFFFFF072,0x00000438,0x00002697,0xFFFFF072,0x00000438},
--	{"0000001000010011111010101001010011011110000100100100100011100100",0x00002F23,0xFFFFEC48,0x000004B9,0x0000199A,0xFFFFF8CF,0x000002E9,0x0000199A,0xFFFFF8CF,0x000002E9},
--	{"0000001000010011111010101001010011011110000001100010100110100100",0x00002BD7,0xFFFFEEAC,0x00000450,0x00001991,0xFFFFF8F4,0x000002E2,0x00001991,0xFFFFF8F4,0x000002E2},
--	{"0000001000010011111010101001010011011110000000100010000000100100",0x00003210,0xFFFFEB24,0x000004DE,0x00001BDF,0xFFFFF744,0x00000333,0x00001BDF,0xFFFFF744,0x00000333},
--	{"0000001000010011111010101001010011011110001001000100000101000100",0x00002DDC,0xFFFFED0D,0x000004AC,0x000019D0,0xFFFFF869,0x0000030F,0x000019D0,0xFFFFF869,0x0000030F},
--	{"0000001000010011111010101001010011011110001000000011100101100100",0x000023E6,0xFFFFF40C,0x000003A9,0x000014EB,0xFFFFFBC4,0x000002AF,0x000014EB,0xFFFFFBC4,0x000002AF},
--	{"0000001000010011111100001111110101000010110010100010100110100100",0x000030CE,0xFFFFE9A5,0x0000053C,0x00001C45,0xFFFFF60E,0x0000035D,0x00001C45,0xFFFFF60E,0x0000035D},
--	{"0000001000010011111010101001010011011110000101100001000010000100",0x00001E89,0xFFFFF73A,0x00000337,0x0000157C,0xFFFFFBC0,0x000002AA,0x0000157C,0xFFFFFBC0,0x000002AA},
--	{"0000001000010011111100001111110101000010110100000100000100100100",0x000036C6,0xFFFFE6CF,0x000005A1,0x00002457,0xFFFFF11D,0x0000042D,0x00002457,0xFFFFF11D,0x0000042D},
--	{"0000001000010011111010101001010011011110001100100001100101000100",0x00002815,0xFFFFF19A,0x000003F2,0x000016D2,0xFFFFFB40,0x00000299,0x000016D2,0xFFFFFB40,0x00000299},
--	{"0000001000010011111010101001010011011110000111000001100110100100",0x00001FE2,0xFFFFF660,0x00000354,0x000015A7,0xFFFFFB47,0x000002C1,0x000015A7,0xFFFFFB47,0x000002C1},
--	{"0000001000010011111010101001010011011110000101100001100101100100",0x00002114,0xFFFFF634,0x00000356,0x000016C1,0xFFFFFB43,0x000002B8,0x000016C1,0xFFFFFB43,0x000002B8},
--	{"0000001000010011111100001111110101000010110011000010100011000100",0x000028E3,0xFFFFF075,0x00000414,0x0000203C,0xFFFFF438,0x000003B3,0x0000203C,0xFFFFF438,0x000003B3},
--	{"0000001000010011111010101001010011011110000111000011100100100100",0x00001EEB,0xFFFFF7BB,0x0000031A,0x00001580,0xFFFFFBD7,0x000002AD,0x00001580,0xFFFFFBD7,0x000002AD},
--	{"0000001000010011111010101001010011011110001001000000100011000100",0x00002BB2,0xFFFFEE72,0x00000470,0x0000192C,0xFFFFF91E,0x000002E7,0x0000192C,0xFFFFF91E,0x000002E7},
--	{"0000001000010011111010101001010011011110000001100101000011100100",0x00003A3D,0xFFFFE49D,0x000005F5,0x00001A3B,0xFFFFF7B1,0x00000320,0x00001A3B,0xFFFFF7B1,0x00000320},
--	{"0000001000010011111100001111110101000010110011100011000101100100",0x00002E93,0xFFFFEC5A,0x000004B4,0x000025EB,0xFFFFF03C,0x0000044A,0x000025EB,0xFFFFF03C,0x0000044A},
--	{"0000001000010011111100001111110101000010110010100010000011000100",0x0000331F,0xFFFFE97A,0x00000531,0x00001A06,0xFFFFF850,0x000002FD,0x00001A06,0xFFFFF850,0x000002FD},
--	{"0000001000010011111100001111110101000010110001100011100101100100",0x00003937,0xFFFFE5A0,0x000005C7,0x0000235E,0xFFFFF234,0x000003F2,0x0000235E,0xFFFFF234,0x000003F2},
--	{"0000001000010011111010101001010011011110000111100011100100100100",0x00001DD0,0xFFFFF80E,0x00000319,0x000015C7,0xFFFFFB91,0x000002BC,0x000015C7,0xFFFFFB91,0x000002BC},
--	{"0000001000010011111100001111110101000010110100000011100101100100",0x00003328,0xFFFFE905,0x0000054A,0x00002054,0xFFFFF3BF,0x000003C0,0x00002054,0xFFFFF3BF,0x000003C0},
--	{"0000001000010011111100001111110101000010110011000001000100000100",0x00002FE5,0xFFFFEA65,0x00000520,0x0000188B,0xFFFFF8A7,0x000002F5,0x0000188B,0xFFFFF8A7,0x000002F5},
--	{"0000001000010011111100001111110101000010110010100011100010100100",0x00002ED3,0xFFFFEC51,0x000004B9,0x00001888,0xFFFFF96A,0x000002CA,0x00001888,0xFFFFF96A,0x000002CA},
--	{"0000001000010011111100001111110101000010110100000011000010000100",0x00002FCC,0xFFFFEB60,0x000004EA,0x00001F8D,0xFFFFF436,0x000003B4,0x00001F8D,0xFFFFF436,0x000003B4},
--	{"0000001000010011111100001111110101000010110011100100000010000100",0x0000329F,0xFFFFE8F7,0x0000054F,0x000023DB,0xFFFFF0EE,0x0000043A,0x000023DB,0xFFFFF0EE,0x0000043A},
--	{"0000001000010011111010101001010011011110000001000011100010100100",0x000030B5,0xFFFFEBB8,0x000004C4,0x00001AFD,0xFFFFF781,0x00000329,0x00001AFD,0xFFFFF781,0x00000329},
--	{"0000001000010011111010101001010011011110000111100001100110100100",0x00001BBF,0xFFFFF8E2,0x000002F7,0x00001722,0xFFFFFA85,0x000002DB,0x00001722,0xFFFFFA85,0x000002DB},
--	{"0000001000010011111010101001010011011110000000100010000001000100",0x000030E4,0xFFFFEBE6,0x000004BB,0x00001C80,0xFFFFF6E1,0x0000033E,0x00001C80,0xFFFFF6E1,0x0000033E},
--	{"0000001000010011111010101001010011011110000100100010100101000100",0x000030E2,0xFFFFECD0,0x00000492,0x00001CE0,0xFFFFF753,0x0000032F,0x00001CE0,0xFFFFF753,0x0000032F},
--	{"0000001000010011111010101001010011011110001100100010100001100100",0x00002513,0xFFFFF323,0x000003BC,0x00001965,0xFFFFF93C,0x000002F0,0x00001965,0xFFFFF93C,0x000002F0},
--	{"0000001000010011111010101001010011011110000101100001000010100100",0x00002147,0xFFFFF585,0x0000037A,0x000014CC,0xFFFFFC3B,0x00000296,0x000014CC,0xFFFFFC3B,0x00000296},
--	{"0000001000010011111010101001010011011110001100100010000100100100",0x00002507,0xFFFFF432,0x0000038A,0x00001890,0xFFFFFA61,0x000002C6,0x00001890,0xFFFFFA61,0x000002C6},
--	{"0000001000010011111010101001010011011110000001100011100010100100",0x0000339B,0xFFFFEA7D,0x000004F0,0x0000191E,0xFFFFF944,0x000002DF,0x0000191E,0xFFFFF944,0x000002DF},
--	{"0000001000010011111100001111110101000010110011000010100010100100",0x00002842,0xFFFFF043,0x00000427,0x00001988,0xFFFFF892,0x000002F7,0x00001988,0xFFFFF892,0x000002F7},
--	{"0000001000010011111100001111110101000010110001100001100010100100",0x0000389D,0xFFFFE5D8,0x000005BF,0x00001EE1,0xFFFFF4EF,0x00000387,0x00001EE1,0xFFFFF4EF,0x00000387},
--	{"0000001000010011111100001111110101000010110011100011000110000100",0x0000396D,0xFFFFE4D7,0x000005F2,0x000020DA,0xFFFFF34E,0x000003CD,0x000020DA,0xFFFFF34E,0x000003CD},
--	{"0000001000010011111100001111110101000010110010100011000100000100",0x0000355F,0xFFFFE85A,0x0000055F,0x0000281F,0xFFFFEF28,0x0000047D,0x0000281F,0xFFFFEF28,0x0000047D},
--	{"0000001000010011111010101001010011011110000111000101000011100100",0x00002284,0xFFFFF46E,0x00000399,0x00001498,0xFFFFFBE3,0x0000029C,0x00001498,0xFFFFFBE3,0x0000029C},
--	{"0000001000010011111010101001010011011110000000100011100101000100",0x000031B6,0xFFFFEB42,0x000004D9,0x00001F54,0xFFFFF4D2,0x00000399,0x00001F54,0xFFFFF4D2,0x00000399},
--	{"0000001000010011111100001111110101000010110001100011000001100100",0x000035CE,0xFFFFE79D,0x00000578,0x00001C78,0xFFFFF68C,0x00000344,0x00001C78,0xFFFFF68C,0x00000344},
--	{"0000001000010011111010101001010011011110000111100100100101100100",0x00001C0A,0xFFFFF81B,0x00000318,0x00001492,0xFFFFFBCC,0x000002A5,0x00001492,0xFFFFFBCC,0x000002A5},
--	{"0000001000010011111010101001010011011110000000100010000110000100",0x00003492,0xFFFFE95C,0x00000526,0x00001A97,0xFFFFF81B,0x0000030B,0x00001A97,0xFFFFF81B,0x0000030B},
--	{"0000001000010011111010101001010011011110000101100011000101100100",0x00001E89,0xFFFFF7D0,0x0000031A,0x000017A5,0xFFFFFA99,0x000002D9,0x000017A5,0xFFFFFA99,0x000002D9},
--	{"0000001000010011111100001111110101000010110010100100100011000100",0x00002DCC,0xFFFFEBE0,0x000004DE,0x000019BA,0xFFFFF7F5,0x0000030D,0x000019BA,0xFFFFF7F5,0x0000030D},
--	{"0000001000010011111010101001010011011110000001000010100110000100",0x000030EF,0xFFFFEBC1,0x000004C0,0x00001AA9,0xFFFFF814,0x0000030A,0x00001AA9,0xFFFFF814,0x0000030A},
--	{"0000001000010011111010101001010011011110001001000101000100100100",0x00002EA3,0xFFFFEBF6,0x000004D8,0x00001DCF,0xFFFFF521,0x00000399,0x00001DCF,0xFFFFF521,0x00000399},
--	{"0000001000010011111010101001010011011110001100100100000101100100",0x00002B5F,0xFFFFEEA1,0x0000046C,0x000017EB,0xFFFFF9C9,0x000002D4,0x000017EB,0xFFFFF9C9,0x000002D4},
--	{"0000001000010011111010101001010011011110000000100100000100000100",0x00002C63,0xFFFFEE82,0x00000455,0x00002268,0xFFFFF29D,0x000003F6,0x00002268,0xFFFFF29D,0x000003F6},
--	{"0000001000010011111010101001010011011110000100100001100100000100",0x00002B1A,0xFFFFF016,0x0000041C,0x000019AA,0xFFFFF988,0x000002D2,0x000019AA,0xFFFFF988,0x000002D2},
--	{"0000001000010011111100001111110101000010110010100010100101100100",0x0000332F,0xFFFFE934,0x0000053B,0x00001E47,0xFFFFF566,0x00000374,0x00001E47,0xFFFFF566,0x00000374},
--	{"0000001000010011111100001111110101000010110010100100100011100100",0x00002995,0xFFFFEEC1,0x00000465,0x0000178F,0xFFFFF995,0x000002C5,0x0000178F,0xFFFFF995,0x000002C5},
--	{"0000001000010011111010101001010011011110001000000001100010000100",0x00001C2E,0xFFFFF932,0x000002E9,0x000015C2,0xFFFFFBC5,0x000002AD,0x000015C2,0xFFFFFBC5,0x000002AD},
--	{"0000001000010011111100001111110101000010110001100100000011100100",0x00003B08,0xFFFFE4E8,0x000005D8,0x0000209D,0xFFFFF444,0x00000398,0x0000209D,0xFFFFF444,0x00000398},
--	{"0000001000010011111010101001010011011110000001000101000011100100",0x00002F1F,0xFFFFEB74,0x000004EB,0x00001F4C,0xFFFFF3D4,0x000003CE,0x00001F4C,0xFFFFF3D4,0x000003CE},
--	{"0000001000010011111010101001010011011110000001000011100010000100",0x00003415,0xFFFFE89F,0x00000553,0x0000186B,0xFFFFF8E1,0x000002EF,0x0000186B,0xFFFFF8E1,0x000002EF},
--	{"0000001000010011111100001111110101000010110011000001000011000100",0x00003441,0xFFFFE779,0x0000059D,0x000019EA,0xFFFFF7B2,0x0000031F,0x000019EA,0xFFFFF7B2,0x0000031F},
--	{"0000001000010011111010101001010011011110000101100100000001100100",0x00002174,0xFFFFF546,0x00000378,0x00001456,0xFFFFFC5F,0x00000284,0x00001456,0xFFFFFC5F,0x00000284},
--	{"0000001000010011111100001111110101000010110011100100000011000100",0x00003788,0xFFFFE61E,0x000005BF,0x00001DF4,0xFFFFF562,0x00000374,0x00001DF4,0xFFFFF562,0x00000374},
--	{"0000001000010011111010101001010011011110000111100001100001000100",0x00001C41,0xFFFFF8C1,0x000002FC,0x0000171E,0xFFFFFA93,0x000002DE,0x0000171E,0xFFFFFA93,0x000002DE},
--	{"0000001000010011111100001111110101000010110010100011100001100100",0x00002B15,0xFFFFEDEC,0x00000487,0x000017E4,0xFFFFF934,0x000002DF,0x000017E4,0xFFFFF934,0x000002DF},
--	{"0000001000010011111100001111110101000010110011000011000101000100",0x0000327A,0xFFFFEA71,0x000004FF,0x00001D96,0xFFFFF63B,0x00000351,0x00001D96,0xFFFFF63B,0x00000351},
--	{"0000001000010011111010101001010011011110000111100100000001100100",0x000023C6,0xFFFFF3E5,0x000003B6,0x000014DE,0xFFFFFC29,0x00000294,0x000014DE,0xFFFFFC29,0x00000294},
--	{"0000001000010011111010101001010011011110000101100100100101000100",0x00001F96,0xFFFFF5FA,0x00000364,0x00001397,0xFFFFFC9D,0x0000027D,0x00001397,0xFFFFFC9D,0x0000027D},
--	{"0000001000010011111010101001010011011110000001100011000101000100",0x00002B51,0xFFFFEFB5,0x00000420,0x00001ACA,0xFFFFF824,0x0000030D,0x00001ACA,0xFFFFF824,0x0000030D},
--	{"0000001000010011111010101001010011011110000111100100100101000100",0x000020DB,0xFFFFF55B,0x0000037C,0x0000153D,0xFFFFFB5F,0x000002BA,0x0000153D,0xFFFFFB5F,0x000002BA},
--	{"0000001000010011111010101001010011011110000000100010000110100100",0x000030BB,0xFFFFEBDA,0x000004BC,0x00001B0E,0xFFFFF7A8,0x0000031E,0x00001B0E,0xFFFFF7A8,0x0000031E},
--	{"0000001000010011111100001111110101000010110001100010100100000100",0x000033C4,0xFFFFEA41,0x000004FA,0x000022C6,0xFFFFF363,0x000003BC,0x000022C6,0xFFFFF363,0x000003BC},
--	{"0000001000010011111010101001010011011110001001000000100100100100",0x00002D47,0xFFFFEE01,0x00000477,0x000021CD,0xFFFFF36E,0x000003D6,0x000021CD,0xFFFFF36E,0x000003D6},
--	{"0000001000010011111010101001010011011110000111100011000110100100",0x00001E7B,0xFFFFF733,0x00000339,0x00001668,0xFFFFFB29,0x000002BF,0x00001668,0xFFFFFB29,0x000002BF},
--	{"0000001000010011111100001111110101000010110010100010100110000100",0x00002F7E,0xFFFFEAFF,0x000004FC,0x000018D4,0xFFFFF8BE,0x000002E8,0x000018D4,0xFFFFF8BE,0x000002E8},
--	{"0000001000010011111010101001010011011110001100100011100010100100",0x00002635,0xFFFFF2E1,0x000003BC,0x000017A4,0xFFFFFA67,0x000002C3,0x000017A4,0xFFFFFA67,0x000002C3},
--	{"0000001000010011111010101001010011011110000100100011000010100100",0x000026CA,0xFFFFF2C1,0x000003B2,0x00001C3E,0xFFFFF7AE,0x0000031F,0x00001C3E,0xFFFFF7AE,0x0000031F},
--	{"0000001000010011111010101001010011011110000111000001000001100100",0x00002550,0xFFFFF380,0x000003B5,0x000019F5,0xFFFFF8E7,0x00000313,0x000019F5,0xFFFFF8E7,0x00000313},
--	{"0000001000010011111100001111110101000010110010100100100100000100",0x00002FBC,0xFFFFEAF8,0x000004FA,0x000018CC,0xFFFFF8C6,0x000002E8,0x000018CC,0xFFFFF8C6,0x000002E8},
--	{"0000001000010011111100001111110101000010110100000001100011100100",0x00002FCC,0xFFFFEB60,0x000004EA,0x00001EFF,0xFFFFF4DA,0x0000038F,0x00001EFF,0xFFFFF4DA,0x0000038F},
--	{"0000001000010011111010101001010011011110000101100100000010000100",0x000023E6,0xFFFFF413,0x000003A1,0x00001544,0xFFFFFC16,0x0000028B,0x00001544,0xFFFFFC16,0x0000028B},
--	{"0000001000010011111100001111110101000010110011100011000000100100",0x00003251,0xFFFFEAA2,0x000004F5,0x000025B0,0xFFFFF0DF,0x00000431,0x000025B0,0xFFFFF0DF,0x00000431},
--	{"0000001000010011111100001111110101000010110100000011100110000100",0x00002F6F,0xFFFFEB67,0x000004E6,0x00002275,0xFFFFF249,0x000003FB,0x00002275,0xFFFFF249,0x000003FB},
--	{"0000001000010011111010101001010011011110001100100010100101100100",0x00002597,0xFFFFF34A,0x000003B1,0x00001BCC,0xFFFFF822,0x0000031A,0x00001BCC,0xFFFFF822,0x0000031A},
--	{"0000001000010011111100001111110101000010110001100011100001100100",0x00003B1D,0xFFFFE40E,0x0000060D,0x00001F61,0xFFFFF470,0x0000039F,0x00001F61,0xFFFFF470,0x0000039F},
--	{"0000001000010011111100001111110101000010110001100100000101000100",0x0000379F,0xFFFFE6DB,0x0000058C,0x00002460,0xFFFFF170,0x00000415,0x00002460,0xFFFFF170,0x00000415},
--	{"0000001000010011111010101001010011011110000101100101000101000100",0x00002442,0xFFFFF2FB,0x000003D9,0x00001414,0xFFFFFBDC,0x000002A2,0x00001414,0xFFFFFBDC,0x000002A2},
--	{"0000001000010011111010101001010011011110000000100100000011000100",0x00003270,0xFFFFEA0D,0x0000051C,0x00001AFD,0xFFFFF783,0x00000328,0x00001AFD,0xFFFFF783,0x00000328},
--	{"0000001000010011111010101001010011011110000101100001000100000100",0x00001B23,0xFFFFF94B,0x000002EB,0x000015F1,0xFFFFFB82,0x000002B4,0x000015F1,0xFFFFFB82,0x000002B4},
--	{"0000001000010011111010101001010011011110001100100011100001000100",0x000026AE,0xFFFFF21A,0x000003DB,0x00001827,0xFFFFFA10,0x000002C8,0x00001827,0xFFFFFA10,0x000002C8},
--	{"0000001000010011111100001111110101000010110010100100100010000100",0x00002DCF,0xFFFFEBD8,0x000004DB,0x00001A75,0xFFFFF719,0x0000033A,0x00001A75,0xFFFFF719,0x0000033A},
--	{"0000001000010011111100001111110101000010110011100100000011100100",0x00003983,0xFFFFE500,0x000005EA,0x000022A6,0xFFFFF25F,0x000003F1,0x000022A6,0xFFFFF25F,0x000003F1},
--	{"0000001000010011111010101001010011011110000100100001100011000100",0x00002AD5,0xFFFFF07A,0x00000406,0x000019FB,0xFFFFF961,0x000002D8,0x000019FB,0xFFFFF961,0x000002D8},
--	{"0000001000010011111100001111110101000010110010100011100110100100",0x00002A43,0xFFFFEE43,0x00000474,0x00001D65,0xFFFFF538,0x00000387,0x00001D65,0xFFFFF538,0x00000387},
--	{"0000001000010011111100001111110101000010110001100010000010000100",0x0000311E,0xFFFFEAF8,0x000004E8,0x00001959,0xFFFFF8E4,0x000002DC,0x00001959,0xFFFFF8E4,0x000002DC},
--	{"0000001000010011111100001111110101000010110100000011000110100100",0x0000339A,0xFFFFE8A7,0x00000559,0x00001A04,0xFFFFF7E5,0x00000311,0x00001A04,0xFFFFF7E5,0x00000311},
--	{"0000001000010011111010101001010011011110001000000100000101000100",0x000021B3,0xFFFFF50F,0x00000389,0x00001470,0xFFFFFBF7,0x000002A5,0x00001470,0xFFFFFBF7,0x000002A5},
--	{"0000001000010011111010101001010011011110000000100001100010000100",0x00003417,0xFFFFE9A6,0x0000051D,0x000018A4,0xFFFFF984,0x000002CF,0x000018A4,0xFFFFF984,0x000002CF},
--	{"0000001000010011111010101001010011011110001000000010100110000100",0x00001FED,0xFFFFF6A2,0x00000347,0x00001639,0xFFFFFB59,0x000002BB,0x00001639,0xFFFFFB59,0x000002BB},
--	{"0000001000010011111010101001010011011110000100100001100010100100",0x000032D2,0xFFFFEB18,0x000004DC,0x00001A01,0xFFFFF95E,0x000002CF,0x00001A01,0xFFFFF95E,0x000002CF},
--	{"0000001000010011111100001111110101000010110100000100000010000100",0x00003147,0xFFFFEA3B,0x00000518,0x0000241D,0xFFFFF11C,0x00000431,0x0000241D,0xFFFFF11C,0x00000431},
--	{"0000001000010011111010101001010011011110000111000000100100000100",0x00001D44,0xFFFFF7E7,0x0000031A,0x0000153F,0xFFFFFBBC,0x000002A9,0x0000153F,0xFFFFFBBC,0x000002A9},
--	{"0000001000010011111100001111110101000010110011000100000100000100",0x00003690,0xFFFFE6E3,0x000005A4,0x000018DE,0xFFFFF908,0x000002DD,0x000018DE,0xFFFFF908,0x000002DD},
--	{"0000001000010011111100001111110101000010110011000010000110000100",0x00003561,0xFFFFE6F8,0x000005AB,0x000018B5,0xFFFFF8A0,0x000002F3,0x000018B5,0xFFFFF8A0,0x000002F3},
--	{"0000001000010011111010101001010011011110001100100011000100100100",0x000028F4,0xFFFFF23A,0x000003CE,0x00001BC6,0xFFFFF881,0x00000311,0x00001BC6,0xFFFFF881,0x00000311},
--	{"0000001000010011111100001111110101000010110100000011000110000100",0x000035D7,0xFFFFE71C,0x0000059B,0x00001D49,0xFFFFF5C8,0x00000368,0x00001D49,0xFFFFF5C8,0x00000368},
--	{"0000001000010011111100001111110101000010110011100001100010100100",0x0000397E,0xFFFFE4CB,0x000005F4,0x00001989,0xFFFFF844,0x000002FD,0x00001989,0xFFFFF844,0x000002FD},
--	{"0000001000010011111100001111110101000010110001100010000001100100",0x00003BAB,0xFFFFE332,0x0000063F,0x00001A69,0xFFFFF7B9,0x00000312,0x00001A69,0xFFFFF7B9,0x00000312},
--	{"0000001000010011111100001111110101000010110100000011000001100100",0x00002F26,0xFFFFEB82,0x000004E8,0x00001D7D,0xFFFFF590,0x00000379,0x00001D7D,0xFFFFF590,0x00000379},
--	{"0000001000010011111010101001010011011110000001100011000110100100",0x00002FDC,0xFFFFEBE0,0x000004C3,0x00001940,0xFFFFF8CC,0x000002EE,0x00001940,0xFFFFF8CC,0x000002EE},
--	{"0000001000010011111010101001010011011110000111000000100011100100",0x000021B2,0xFFFFF558,0x00000379,0x00001643,0xFFFFFB1C,0x000002C3,0x00001643,0xFFFFFB1C,0x000002C3},
--	{"0000001000010011111010101001010011011110001100100001100100000100",0x00002897,0xFFFFF181,0x000003F7,0x00001990,0xFFFFF994,0x000002E2,0x00001990,0xFFFFF994,0x000002E2},
--	{"0000001000010011111010101001010011011110000111100000100100100100",0x00001D19,0xFFFFF829,0x0000031A,0x00001558,0xFFFFFBCA,0x000002AF,0x00001558,0xFFFFFBCA,0x000002AF},
--	{"0000001000010011111010101001010011011110000001000011000101000100",0x00003311,0xFFFFEAD9,0x000004E1,0x00001BDC,0xFFFFF79E,0x0000031D,0x00001BDC,0xFFFFF79E,0x0000031D},
--	{"0000001000010011111010101001010011011110000111100010100111000100",0x00001E54,0xFFFFF740,0x00000333,0x000016A1,0xFFFFFAF0,0x000002C4,0x000016A1,0xFFFFFAF0,0x000002C4},
--	{"0000001000010011111100001111110101000010110011100011100101100100",0x00003266,0xFFFFE9A8,0x00000527,0x00002307,0xFFFFF219,0x000003FC,0x00002307,0xFFFFF219,0x000003FC},
--	{"0000001000010011111010101001010011011110001100100001000101000100",0x00001D1F,0xFFFFF82B,0x000002F0,0x000013F0,0xFFFFFD0B,0x0000024E,0x000013F0,0xFFFFFD0B,0x0000024E},
--	{"0000001000010011111100001111110101000010110001100100100010100100",0x0000312E,0xFFFFEA67,0x00000502,0x0000222A,0xFFFFF253,0x000003F9,0x0000222A,0xFFFFF253,0x000003F9},
--	{"0000001000010011111100001111110101000010110010100100000100100100",0x000032B2,0xFFFFE9AD,0x00000523,0x00001E97,0xFFFFF527,0x0000037F,0x00001E97,0xFFFFF527,0x0000037F},
--	{"0000001000010011111010101001010011011110000101100100000011100100",0x00001F6A,0xFFFFF6FC,0x00000338,0x0000164B,0xFFFFFB2C,0x000002C2,0x0000164B,0xFFFFFB2C,0x000002C2},
--	{"0000001000010011111010101001010011011110000000100010100011000100",0x00002603,0xFFFFF386,0x00000392,0x00001EE0,0xFFFFF601,0x00000369,0x00001EE0,0xFFFFF601,0x00000369},
--	{"0000001000010011111010101001010011011110001000000001000101100100",0x00001D0C,0xFFFFF803,0x00000317,0x00001345,0xFFFFFD52,0x00000260,0x00001345,0xFFFFFD52,0x00000260},
--	{"0000001000010011111100001111110101000010110011000001100010000100",0x0000327A,0xFFFFE8E5,0x0000055C,0x00001680,0xFFFFFA2D,0x000002B2,0x00001680,0xFFFFFA2D,0x000002B2},
--	{"0000001000010011111100001111110101000010110010100011100101100100",0x000032B8,0xFFFFE91A,0x0000054A,0x00001BAB,0xFFFFF6EC,0x00000338,0x00001BAB,0xFFFFF6EC,0x00000338},
--	{"0000001000010011111100001111110101000010110011000011000001000100",0x00002F79,0xFFFFEB63,0x000004EF,0x000017BB,0xFFFFF9B1,0x000002CA,0x000017BB,0xFFFFF9B1,0x000002CA},
--	{"0000001000010011111010101001010011011110000001000011100011100100",0x00002AE5,0xFFFFEFCB,0x0000041D,0x0000214A,0xFFFFF3A7,0x000003C7,0x0000214A,0xFFFFF3A7,0x000003C7},
--	{"0000001000010011111010101001010011011110001100100010000001100100",0x0000212C,0xFFFFF5BC,0x0000034F,0x000017ED,0xFFFFFA4C,0x000002C1,0x000017ED,0xFFFFFA4C,0x000002C1},
--	{"0000001000010011111010101001010011011110000100100001000100100100",0x00002BE7,0xFFFFEF40,0x0000043C,0x00001AE2,0xFFFFF8CF,0x000002E3,0x00001AE2,0xFFFFF8CF,0x000002E3},
--	{"0000001000010011111100001111110101000010110100000101000101000100",0x000032DC,0xFFFFE90F,0x00000549,0x00002A2D,0xFFFFECC9,0x000004ED,0x00002A2D,0xFFFFECC9,0x000004ED},
--	{"0000001000010011111010101001010011011110000101100001100010100100",0x00001DE3,0xFFFFF80D,0x00000319,0x000016FA,0xFFFFFB42,0x000002BC,0x000016FA,0xFFFFFB42,0x000002BC},
--	{"0000001000010011111010101001010011011110000111100010100001000100",0x00001F1B,0xFFFFF6DE,0x00000346,0x00001502,0xFFFFFC23,0x00000298,0x00001502,0xFFFFFC23,0x00000298},
--	{"0000001000010011111010101001010011011110000001100001100001100100",0x00003203,0xFFFFEA87,0x000004FE,0x0000194E,0xFFFFF8E3,0x000002EC,0x0000194E,0xFFFFF8E3,0x000002EC},
--	{"0000001000010011111100001111110101000010110100000010000101000100",0x0000337A,0xFFFFE8DD,0x00000551,0x00001E3C,0xFFFFF534,0x00000385,0x00001E3C,0xFFFFF534,0x00000385},
--	{"0000001000010011111100001111110101000010110010100100100001100100",0x000036F6,0xFFFFE62A,0x000005C5,0x000023C0,0xFFFFF117,0x00000435,0x000023C0,0xFFFFF117,0x00000435},
--	{"0000001000010011111100001111110101000010110011000010000101000100",0x00003125,0xFFFFEA4E,0x0000051A,0x00001E6C,0xFFFFF503,0x0000038E,0x00001E6C,0xFFFFF503,0x0000038E},
--	{"0000001000010011111010101001010011011110000111000000100010100100",0x00001CD4,0xFFFFF82D,0x0000030E,0x0000156D,0xFFFFFB64,0x000002B8,0x0000156D,0xFFFFFB64,0x000002B8},
--	{"0000001000010011111010101001010011011110000000100100000010100100",0x00002F14,0xFFFFEC46,0x000004B8,0x000017F1,0xFFFFF977,0x000002D2,0x000017F1,0xFFFFF977,0x000002D2},
--	{"0000001000010011111010101001010011011110000001100100000010100100",0x000031F1,0xFFFFEAD4,0x000004ED,0x0000184C,0xFFFFF983,0x000002D4,0x0000184C,0xFFFFF983,0x000002D4},
--	{"0000001000010011111100001111110101000010110100000100100110000100",0x00002EA9,0xFFFFEBD7,0x000004D5,0x0000288D,0xFFFFEDDB,0x000004C0,0x0000288D,0xFFFFEDDB,0x000004C0},
--	{"0000001000010011111100001111110101000010110010100011100110000100",0x0000335F,0xFFFFE82C,0x00000579,0x00001DBF,0xFFFFF512,0x0000038C,0x00001DBF,0xFFFFF512,0x0000038C},
--	{"0000001000010011111010101001010011011110001000000001000110000100",0x0000224F,0xFFFFF4B5,0x00000391,0x0000138C,0xFFFFFCC3,0x0000027A,0x0000138C,0xFFFFFCC3,0x0000027A},
--	{"0000001000010011111010101001010011011110000100100100000010100100",0x0000320D,0xFFFFEACD,0x000004F5,0x00001976,0xFFFFF913,0x000002E2,0x00001976,0xFFFFF913,0x000002E2},
--	{"0000001000010011111010101001010011011110001000000010000100000100",0x00001BEB,0xFFFFF99C,0x000002E4,0x000016A4,0xFFFFFB77,0x000002C3,0x000016A4,0xFFFFFB77,0x000002C3},
--	{"0000001000010011111010101001010011011110000001100011000001000100",0x0000396E,0xFFFFE616,0x000005A9,0x000018F4,0xFFFFF91A,0x000002E3,0x000018F4,0xFFFFF91A,0x000002E3},
--	{"0000001000010011111010101001010011011110000000100010100001100100",0x00003251,0xFFFFEA8E,0x000004FA,0x000018EF,0xFFFFF910,0x000002E4,0x000018EF,0xFFFFF910,0x000002E4},
--	{"0000001000010011111010101001010011011110000111000001100100100100",0x00001DAF,0xFFFFF857,0x0000030D,0x00001915,0xFFFFF9D8,0x000002F7,0x00001915,0xFFFFF9D8,0x000002F7},
--	{"0000001000010011111010101001010011011110001000000100000110100100",0x000025B6,0xFFFFF26B,0x000003E5,0x00001531,0xFFFFFB68,0x000002AF,0x00001531,0xFFFFFB68,0x000002AF},
--	{"0000001000010011111010101001010011011110000001100001100010000100",0x00002B2E,0xFFFFEF2E,0x00000440,0x00001968,0xFFFFF91A,0x000002DF,0x00001968,0xFFFFF91A,0x000002DF},
--	{"0000001000010011111010101001010011011110000111000010000001100100",0x00002305,0xFFFFF528,0x00000377,0x000018A4,0xFFFFF9EB,0x000002F0,0x000018A4,0xFFFFF9EB,0x000002F0},
--	{"0000001000010011111100001111110101000010110010100100000011000100",0x000032A1,0xFFFFE992,0x0000052E,0x00001A55,0xFFFFF826,0x000002FE,0x00001A55,0xFFFFF826,0x000002FE},
--	{"0000001000010011111010101001010011011110000001000010000110000100",0x00002CCD,0xFFFFEE35,0x00000462,0x00001B09,0xFFFFF7E6,0x0000030F,0x00001B09,0xFFFFF7E6,0x0000030F},
--	{"0000001000010011111010101001010011011110001100100011000010000100",0x00002602,0xFFFFF2CF,0x000003C5,0x000016EE,0xFFFFFAD4,0x000002B4,0x000016EE,0xFFFFFAD4,0x000002B4},
--	{"0000001000010011111100001111110101000010110100000001100101100100",0x00003370,0xFFFFE891,0x00000560,0x000017F0,0xFFFFF930,0x000002DF,0x000017F0,0xFFFFF930,0x000002DF},
--	{"0000001000010011111100001111110101000010110010100001100010000100",0x00002EDC,0xFFFFEB6D,0x000004EC,0x000016E6,0xFFFFF9ED,0x000002BC,0x000016E6,0xFFFFF9ED,0x000002BC},
--	{"0000001000010011111010101001010011011110000100100010100011000100",0x00002A05,0xFFFFF13D,0x000003F0,0x00002065,0xFFFFF57B,0x00000378,0x00002065,0xFFFFF57B,0x00000378},
--	{"0000001000010011111100001111110101000010110011100010000001000100",0x00002F8A,0xFFFFEB6E,0x000004E4,0x00001E3E,0xFFFFF50E,0x0000038D,0x00001E3E,0xFFFFF50E,0x0000038D},
--	{"0000001000010011111100001111110101000010110010100011000001000100",0x00002BB5,0xFFFFED6A,0x000004A1,0x000017BF,0xFFFFF937,0x000002E5,0x000017BF,0xFFFFF937,0x000002E5},
--	{"0000001000010011111010101001010011011110001000000001100101100100",0x0000202C,0xFFFFF6CE,0x0000033F,0x000015EE,0xFFFFFB83,0x000002B9,0x000015EE,0xFFFFFB83,0x000002B9},
--	{"0000001000010011111010101001010011011110000000100010100010000100",0x00002C0C,0xFFFFEF10,0x0000043F,0x00001A73,0xFFFFF83E,0x0000030C,0x00001A73,0xFFFFF83E,0x0000030C},
--	{"0000001000010011111010101001010011011110001100100100000100000100",0x0000234F,0xFFFFF460,0x00000385,0x000018C3,0xFFFFF9A5,0x000002DD,0x000018C3,0xFFFFF9A5,0x000002DD},
--	{"0000001000010011111100001111110101000010110011100001100100000100",0x00003679,0xFFFFE704,0x00000595,0x00002177,0xFFFFF31A,0x000003D7,0x00002177,0xFFFFF31A,0x000003D7},
--	{"0000001000010011111100001111110101000010110010100010100100100100",0x00003008,0xFFFFEBB8,0x000004D5,0x000024FF,0xFFFFF112,0x00000430,0x000024FF,0xFFFFF112,0x00000430},
--	{"0000001000010011111100001111110101000010110001100100000110100100",0x00003848,0xFFFFE6A3,0x00000594,0x00002958,0xFFFFEE37,0x000004A0,0x00002958,0xFFFFEE37,0x000004A0},
--	{"0000001000010011111100001111110101000010110011000001100100100100",0x00002FDF,0xFFFFEB08,0x000004FD,0x00001D77,0xFFFFF58B,0x0000037A,0x00001D77,0xFFFFF58B,0x0000037A},
--	{"0000001000010011111010101001010011011110000001100011000001100100",0x00002EC8,0xFFFFED41,0x00000481,0x00001949,0xFFFFF91C,0x000002DF,0x00001949,0xFFFFF91C,0x000002DF},
--	{"0000001000010011111100001111110101000010110100000100000110100100",0x000037C1,0xFFFFE5BA,0x000005D7,0x0000252C,0xFFFFF023,0x00000460,0x0000252C,0xFFFFF023,0x00000460},
--	{"0000001000010011111100001111110101000010110011100010100101000100",0x00003716,0xFFFFE70C,0x0000058A,0x000028CC,0xFFFFEE57,0x0000049D,0x000028CC,0xFFFFEE57,0x0000049D},
--	{"0000001000010011111100001111110101000010110010100100000011100100",0x000033D1,0xFFFFE8E8,0x00000547,0x00001AB1,0xFFFFF7E5,0x00000309,0x00001AB1,0xFFFFF7E5,0x00000309},
--	{"0000001000010011111100001111110101000010110011000010100101000100",0x00002D72,0xFFFFED65,0x0000048E,0x00001E0D,0xFFFFF5A7,0x00000370,0x00001E0D,0xFFFFF5A7,0x00000370},
--	{"0000001000010011111010101001010011011110000111000011100110100100",0x00002292,0xFFFFF49F,0x00000393,0x000017F4,0xFFFFF9CD,0x000002F5,0x000017F4,0xFFFFF9CD,0x000002F5},
--	{"0000001000010011111010101001010011011110001001000011000001000100",0x000026EE,0xFFFFF18C,0x000003F7,0x000018A7,0xFFFFF95A,0x000002E5,0x000018A7,0xFFFFF95A,0x000002E5},
--	{"0000001000010011111010101001010011011110000001000010000101100100",0x00002F62,0xFFFFEC9B,0x000004A4,0x0000194E,0xFFFFF932,0x000002D9,0x0000194E,0xFFFFF932,0x000002D9},
--	{"0000001000010011111010101001010011011110000111100011100110000100",0x00001CE8,0xFFFFF7FA,0x0000031C,0x000014CE,0xFFFFFBD4,0x000002AB,0x000014CE,0xFFFFFBD4,0x000002AB},
--	{"0000001000010011111010101001010011011110000100100001000011100100",0x00002E5A,0xFFFFEDAB,0x0000047C,0x00001A82,0xFFFFF8F7,0x000002DE,0x00001A82,0xFFFFF8F7,0x000002DE},
--	{"0000001000010011111100001111110101000010110011000011000011100100",0x00003057,0xFFFFEC34,0x000004B9,0x00002296,0xFFFFF342,0x000003D0,0x00002296,0xFFFFF342,0x000003D0},
--	{"0000001000010011111010101001010011011110000001000001100010100100",0x00002B0F,0xFFFFEF58,0x00000434,0x00001BFD,0xFFFFF721,0x00000330,0x00001BFD,0xFFFFF721,0x00000330},
--	{"0000001000010011111010101001010011011110001000000001000010100100",0x00001F01,0xFFFFF751,0x0000032F,0x00001502,0xFFFFFC3E,0x00000296,0x00001502,0xFFFFFC3E,0x00000296},
--	{"0000001000010011111100001111110101000010110010100011000001100100",0x00002FF4,0xFFFFEAE2,0x00000503,0x00001B36,0xFFFFF736,0x00000330,0x00001B36,0xFFFFF736,0x00000330},
--	{"0000001000010011111100001111110101000010110011100010000001100100",0x00003762,0xFFFFE5AB,0x000005DE,0x000018CB,0xFFFFF896,0x000002F4,0x000018CB,0xFFFFF896,0x000002F4},
--	{"0000001000010011111100001111110101000010110011000010000001100100",0x00002890,0xFFFFEF92,0x00000445,0x0000191D,0xFFFFF86F,0x00000302,0x0000191D,0xFFFFF86F,0x00000302},
--	{"0000001000010011111010101001010011011110000001000011000001100100",0x00002F76,0xFFFFEC0E,0x000004BF,0x00001F7D,0xFFFFF41A,0x000003C0,0x00001F7D,0xFFFFF41A,0x000003C0},
--	{"0000001000010011111010101001010011011110000111100000100010100100",0x00001D55,0xFFFFF7F8,0x0000031E,0x000015DF,0xFFFFFB79,0x000002B7,0x000015DF,0xFFFFFB79,0x000002B7},
--	{"0000001000010011111010101001010011011110001000000100100100100100",0x00001FE9,0xFFFFF64A,0x00000353,0x000019E8,0xFFFFF882,0x0000032A,0x000019E8,0xFFFFF882,0x0000032A},
--	{"0000001000010011111010101001010011011110000001100011100101100100",0x000030B5,0xFFFFEBB8,0x000004C4,0x00001857,0xFFFFF968,0x000002D8,0x00001857,0xFFFFF968,0x000002D8},
--	{"0000001000010011111100001111110101000010110010100010100011000100",0x00003398,0xFFFFE9A3,0x00000524,0x00001FF9,0xFFFFF458,0x000003AD,0x00001FF9,0xFFFFF458,0x000003AD},
--	{"0000001000010011111100001111110101000010110011100010100101100100",0x00003897,0xFFFFE5BD,0x000005C8,0x00002519,0xFFFFF0BA,0x00000438,0x00002519,0xFFFFF0BA,0x00000438},
--	{"0000001000010011111100001111110101000010110100000100000001100100",0x00003234,0xFFFFE9B1,0x00000530,0x000022CC,0xFFFFF20E,0x00000409,0x000022CC,0xFFFFF20E,0x00000409},
--	{"0000001000010011111010101001010011011110001000000101000100000100",0x00001FD2,0xFFFFF641,0x00000354,0x000017C9,0xFFFFF9C0,0x000002FB,0x000017C9,0xFFFFF9C0,0x000002FB},
--	{"0000001000010011111100001111110101000010110011100100100011100100",0x00003234,0xFFFFE946,0x0000053D,0x00002267,0xFFFFF1F5,0x0000040D,0x00002267,0xFFFFF1F5,0x0000040D},
--	{"0000001000010011111010101001010011011110001000000010100110100100",0x00002330,0xFFFFF474,0x00000399,0x00001490,0xFFFFFC67,0x00000288,0x00001490,0xFFFFFC67,0x00000288},
--	{"0000001000010011111100001111110101000010110100000011100100100100",0x000032A3,0xFFFFE9EB,0x0000051B,0x0000234D,0xFFFFF23C,0x000003F7,0x0000234D,0xFFFFF23C,0x000003F7},
--	{"0000001000010011111010101001010011011110001000000000100100000100",0x0000217E,0xFFFFF53A,0x00000384,0x00001511,0xFFFFFBF5,0x0000029E,0x00001511,0xFFFFFBF5,0x0000029E},
--	{"0000001000010011111100001111110101000010110011100101000011100100",0x0000384F,0xFFFFE562,0x000005E2,0x0000295A,0xFFFFED53,0x000004D3,0x0000295A,0xFFFFED53,0x000004D3},
--	{"0000001000010011111100001111110101000010110100000101000100100100",0x00003315,0xFFFFE8D1,0x00000552,0x000025D1,0xFFFFEFAF,0x00000471,0x000025D1,0xFFFFEFAF,0x00000471},
--	{"0000001000010011111100001111110101000010110001100100100100100100",0x00004183,0xFFFFDF61,0x000006DA,0x0000193C,0xFFFFF88F,0x000002EC,0x0000193C,0xFFFFF88F,0x000002EC},
--	{"0000001000010011111010101001010011011110001001000010000101100100",0x00002DFC,0xFFFFEDF2,0x0000047A,0x00001755,0xFFFFFAC2,0x000002AC,0x00001755,0xFFFFFAC2,0x000002AC},
--	{"0000001000010011111100001111110101000010110010100011000110100100",0x000033FE,0xFFFFE774,0x0000059F,0x00001E70,0xFFFFF492,0x000003A0,0x00001E70,0xFFFFF492,0x000003A0},
--	{"0000001000010011111100001111110101000010110001100010100110100100",0x000040D7,0xFFFFDFB8,0x000006CE,0x00001AC8,0xFFFFF773,0x0000031D,0x00001AC8,0xFFFFF773,0x0000031D},
--	{"0000001000010011111010101001010011011110000111100001000101100100",0x00001D02,0xFFFFF803,0x00000322,0x000015FE,0xFFFFFB71,0x000002BB,0x000015FE,0xFFFFFB71,0x000002BB},
--	{"0000001000010011111100001111110101000010110100000010100010000100",0x00002EB0,0xFFFFEC31,0x000004C4,0x00001B3C,0xFFFFF73B,0x00000330,0x00001B3C,0xFFFFF73B,0x00000330},
--	{"0000001000010011111100001111110101000010110010100100100110000100",0x00002D9F,0xFFFFECBF,0x000004A8,0x000022B0,0xFFFFF23C,0x000003F9,0x000022B0,0xFFFFF23C,0x000003F9},
--	{"0000001000010011111100001111110101000010110011000001100011100100",0x00002C6A,0xFFFFEDAC,0x00000488,0x00002419,0xFFFFF159,0x00000427,0x00002419,0xFFFFF159,0x00000427},
--	{"0000001000010011111010101001010011011110000100100001000010100100",0x00002991,0xFFFFF06C,0x0000040E,0x00001AA9,0xFFFFF8D0,0x000002E1,0x00001AA9,0xFFFFF8D0,0x000002E1},
--	{"0000001000010011111010101001010011011110000100100011100100000100",0x00002F8E,0xFFFFED1B,0x00000493,0x00001DE4,0xFFFFF69C,0x00000347,0x00001DE4,0xFFFFF69C,0x00000347},
--	{"0000001000010011111010101001010011011110001000000100000110000100",0x00002136,0xFFFFF540,0x0000037C,0x000014FF,0xFFFFFB83,0x000002B2,0x000014FF,0xFFFFFB83,0x000002B2},
--	{"0000001000010011111010101001010011011110000001100001100011100100",0x0000354C,0xFFFFE97D,0x0000051A,0x00001906,0xFFFFF965,0x000002DD,0x00001906,0xFFFFF965,0x000002DD},
--	{"0000001000010011111100001111110101000010110001100010000011000100",0x0000348B,0xFFFFE94D,0x0000051F,0x0000285B,0xFFFFEF1A,0x00000473,0x0000285B,0xFFFFEF1A,0x00000473},
--	{"0000001000010011111010101001010011011110001100100001100010100100",0x000026E6,0xFFFFF24E,0x000003D6,0x0000141F,0xFFFFFCCE,0x00000260,0x0000141F,0xFFFFFCCE,0x00000260},
--	{"0000001000010011111100001111110101000010110001100100000101100100",0x00003CED,0xFFFFE2A5,0x0000064E,0x00002060,0xFFFFF3E0,0x000003B0,0x00002060,0xFFFFF3E0,0x000003B0},
--	{"0000001000010011111010101001010011011110000000100001000010000100",0x000029D4,0xFFFFEFF7,0x00000426,0x00001976,0xFFFFF8E1,0x000002EE,0x00001976,0xFFFFF8E1,0x000002EE},
--	{"0000001000010011111100001111110101000010110010100100000010100100",0x00003767,0xFFFFE601,0x000005CC,0x00001D22,0xFFFFF5F4,0x00000361,0x00001D22,0xFFFFF5F4,0x00000361},
--	{"0000001000010011111100001111110101000010110001100101000011000100",0x00003CE8,0xFFFFE2E8,0x00000637,0x0000232C,0xFFFFF1E7,0x00000405,0x0000232C,0xFFFFF1E7,0x00000405},
--	{"0000001000010011111010101001010011011110001000000001000001100100",0x000023A8,0xFFFFF4CD,0x00000386,0x00001944,0xFFFFF983,0x00000300,0x00001944,0xFFFFF983,0x00000300},
--	{"0000001000010011111100001111110101000010110011000011000010100100",0x00003451,0xFFFFE8B9,0x00000551,0x00001AD7,0xFFFFF7BF,0x00000318,0x00001AD7,0xFFFFF7BF,0x00000318},
--	{"0000001000010011111100001111110101000010110011100010100110000100",0x0000381B,0xFFFFE5A0,0x000005D0,0x00001E0F,0xFFFFF521,0x00000382,0x00001E0F,0xFFFFF521,0x00000382},
--	{"0000001000010011111010101001010011011110001000000011100011000100",0x000023A4,0xFFFFF4A6,0x00000394,0x0000171F,0xFFFFFABB,0x000002D9,0x0000171F,0xFFFFFABB,0x000002D9},
--	{"0000001000010011111100001111110101000010110001100010000010100100",0x00003C2B,0xFFFFE447,0x000005F0,0x0000207F,0xFFFFF44E,0x0000039A,0x0000207F,0xFFFFF44E,0x0000039A},
--	{"0000001000010011111100001111110101000010110011000011100110000100",0x00002F07,0xFFFFEB70,0x000004E9,0x00001765,0xFFFFF9A5,0x000002C6,0x00001765,0xFFFFF9A5,0x000002C6},
--	{"0000001000010011111100001111110101000010110001100010100110000100",0x00003A01,0xFFFFE4E0,0x000005E7,0x0000227A,0xFFFFF292,0x000003E5,0x0000227A,0xFFFFF292,0x000003E5},
--	{"0000001000010011111100001111110101000010110011100010000010100100",0x0000376E,0xFFFFE686,0x000005A6,0x00001FCF,0xFFFFF43B,0x000003A8,0x00001FCF,0xFFFFF43B,0x000003A8},
--	{"0000001000010011111100001111111111101111010110100100100110000100",0x0000485F,0xFFFFDCC1,0x00000713,0x00002CF8,0xFFFFEC45,0x000004DA,0x00002CF8,0xFFFFEC45,0x000004DA},
--	{"0000001000010011111100001111111111101111010111000011000110000100",0x0000331C,0xFFFFE8FF,0x00000541,0x00002366,0xFFFFF19D,0x00000411,0x00002366,0xFFFFF19D,0x00000411},
--	{"0000001000010011111100001111111111101111011001000011100001100100",0x00003CF3,0xFFFFE15A,0x00000694,0x00002FB3,0xFFFFE827,0x000005B9,0x00002FB3,0xFFFFE827,0x000005B9},
--	{"0000001000010011111010101001010011011110001100100001000100000100",0x000023F3,0xFFFFF3EA,0x0000039A,0x00001345,0xFFFFFD6B,0x00000241,0x00001345,0xFFFFFD6B,0x00000241},
--	{"0000001000010011111100001111111111101111010111000010100010100100",0x000038C0,0xFFFFE58A,0x000005CC,0x000023CA,0xFFFFF1AA,0x00000408,0x000023CA,0xFFFFF1AA,0x00000408},
--	{"0000001000010011111100001111111111101111011001100010100101000100",0x00004976,0xFFFFDD6A,0x000006D7,0x000033C6,0xFFFFE8EB,0x0000054D,0x000033C6,0xFFFFE8EB,0x0000054D},
--	{"0000001000010011111100001111111111101111011001000100100100000100",0x00004049,0xFFFFDF6D,0x000006D8,0x00003129,0xFFFFE716,0x000005E9,0x00003129,0xFFFFE716,0x000005E9},
--	{"0000001000010011111100001111111111101111011001100001000101100100",0x000046C2,0xFFFFDCEB,0x0000071C,0x00002E6D,0xFFFFEA8F,0x0000052E,0x00002E6D,0xFFFFEA8F,0x0000052E},
--	{"0000001000010011111100001111111111101111011000100011100010100100",0x00004080,0xFFFFE1E1,0x0000063A,0x0000396D,0xFFFFE40A,0x0000062C,0x0000396D,0xFFFFE40A,0x0000062C},
--	{"0000001000010011111100001111111111101111010111100010000100100100",0x00003DE0,0xFFFFE358,0x0000060C,0x00002AA2,0xFFFFEDBF,0x000004A0,0x00002AA2,0xFFFFEDBF,0x000004A0},
--	{"0000001000010011111100001111111111101111010111100011000101000100",0x00003FC0,0xFFFFE2A1,0x0000061A,0x000027D8,0xFFFFEFEC,0x0000043A,0x000027D8,0xFFFFEFEC,0x0000043A},
--	{"0000001000010011111100001111111111101111011001100001100100100100",0x00003FBF,0xFFFFE2F5,0x00000603,0x000032D7,0xFFFFE900,0x00000552,0x000032D7,0xFFFFE900,0x00000552},
--	{"0000001000010011111100001111111111101111010111000001000011100100",0x000035EE,0xFFFFE6CA,0x000005A2,0x0000247C,0xFFFFF088,0x00000446,0x0000247C,0xFFFFF088,0x00000446},
--	{"0000001000010011111100001111111111101111011001000011100010000100",0x000039C8,0xFFFFE3AE,0x0000062A,0x000028AF,0xFFFFED24,0x000004DF,0x000028AF,0xFFFFED24,0x000004DF},
--	{"0000001000010011111100001111111111101111010111000010100010000100",0x00003BDE,0xFFFFE33B,0x00000632,0x00001B6C,0xFFFFF720,0x00000326,0x00001B6C,0xFFFFF720,0x00000326},
--	{"0000001000010011111100001111111111101111011100100001000010100100",0x00003818,0xFFFFE57D,0x000005D4,0x000020EF,0xFFFFF327,0x000003CE,0x000020EF,0xFFFFF327,0x000003CE},
--	{"0000001000010011111100001111111111101111010111100001100110100100",0x000038DA,0xFFFFE561,0x000005D3,0x0000297D,0xFFFFED6D,0x000004C5,0x0000297D,0xFFFFED6D,0x000004C5},
--	{"0000001000010011111100001111111111101111011010000100100010000100",0x000027AC,0xFFFFF0CE,0x00000417,0x00001F5F,0xFFFFF484,0x000003B2,0x00001F5F,0xFFFFF484,0x000003B2},
--	{"0000001000010011111100001111111111101111011001100100100010100100",0x00003F02,0xFFFFE222,0x00000643,0x000026D4,0xFFFFF000,0x00000443,0x000026D4,0xFFFFF000,0x00000443},
--	{"0000001000010011111100001111111111101111011000100100000101100100",0x00004303,0xFFFFDFE3,0x00000690,0x0000312C,0xFFFFE912,0x00000561,0x0000312C,0xFFFFE912,0x00000561},
--	{"0000001000010011111100001111111111101111011000000000100100000100",0x000039E5,0xFFFFE31F,0x00000657,0x00001D23,0xFFFFF51F,0x00000386,0x00001D23,0xFFFFF51F,0x00000386},
--	{"0000001000010011111100001111111111101111011001100001000101000100",0x000041FA,0xFFFFE01B,0x00000697,0x00002767,0xFFFFEF90,0x00000455,0x00002767,0xFFFFEF90,0x00000455},
--	{"0000001000010011111100001111111111101111011010000011000010100100",0x00002888,0xFFFFF11C,0x00000403,0x00001864,0xFFFFF9D8,0x000002D3,0x00001864,0xFFFFF9D8,0x000002D3},
--	{"0000001000010011111010101001010011011110001000000001100001100100",0x0000215C,0xFFFFF5B6,0x0000036D,0x000015C5,0xFFFFFB8A,0x000002B5,0x000015C5,0xFFFFFB8A,0x000002B5},
--	{"0000001000010011111100001111111111101111011010000011100110000100",0x00002FAF,0xFFFFEC27,0x000004CA,0x00002184,0xFFFFF39C,0x000003CD,0x00002184,0xFFFFF39C,0x000003CD},
--	{"0000001000010011111100001111111111101111010111100001000011000100",0x00004ACE,0xFFFFD9A3,0x000007BC,0x00001A5D,0xFFFFF7F6,0x000002FC,0x00001A5D,0xFFFFF7F6,0x000002FC},
--	{"0000001000010011111100001111111111101111010110100011000001000100",0x00003763,0xFFFFE797,0x0000055F,0x000029B5,0xFFFFEEA1,0x00000474,0x000029B5,0xFFFFEEA1,0x00000474},
--	{"0000001000010011111100001111111111101111010111100011000101100100",0x00003832,0xFFFFE6F9,0x00000575,0x00002C99,0xFFFFEC42,0x000004E3,0x00002C99,0xFFFFEC42,0x000004E3},
--	{"0000001000010011111100001111111111101111011000000100000101100100",0x000041C9,0xFFFFDE33,0x0000071E,0x0000199D,0xFFFFF808,0x000002F9,0x0000199D,0xFFFFF808,0x000002F9},
--	{"0000001000010011111100001111111111101111011001000001000101100100",0x0000474A,0xFFFFD96E,0x00000802,0x00002A30,0xFFFFEB57,0x0000053F,0x00002A30,0xFFFFEB57,0x0000053F},
--	{"0000001000010011111100001111111111101111010111000011000111000100",0x0000312F,0xFFFFEA6A,0x00000508,0x000029D3,0xFFFFED38,0x000004D3,0x000029D3,0xFFFFED38,0x000004D3},
--	{"0000001000010011111100001111111111101111011100100001000011000100",0x00003BD6,0xFFFFE2E7,0x00000644,0x00002093,0xFFFFF37B,0x000003BD,0x00002093,0xFFFFF37B,0x000003BD},
--	{"0000001000010011111100001111111111101111011010000100000011100100",0x00002F94,0xFFFFECD4,0x000004A3,0x00002196,0xFFFFF40B,0x000003B5,0x00002196,0xFFFFF40B,0x000003B5},
--	{"0000001000010011111100001111111111101111010111100001100101000100",0x0000369B,0xFFFFE762,0x00000571,0x00002726,0xFFFFEF99,0x00000459,0x00002726,0xFFFFEF99,0x00000459},
--	{"0000001000010011111100001111111111101111011001000010000001100100",0x00003F57,0xFFFFDF47,0x000006F4,0x00002E5F,0xFFFFE8AE,0x000005AB,0x00002E5F,0xFFFFE8AE,0x000005AB},
--	{"0000001000010011111010101001010011011110000010100100000011000100",0x00004313,0xFFFFDD81,0x0000072D,0x00002468,0xFFFFF068,0x00000440,0x00002468,0xFFFFF068,0x00000440},
--	{"0000001000010011111100001111111111101111011010000011000001000100",0x00002A35,0xFFFFEFA8,0x00000441,0x00001F3F,0xFFFFF4F3,0x000003A0,0x00001F3F,0xFFFFF4F3,0x000003A0},
--	{"0000001000010011111100001111111111101111011001100011000010100100",0x00003E33,0xFFFFE4B0,0x000005AF,0x00002802,0xFFFFF092,0x00000412,0x00002802,0xFFFFF092,0x00000412},
--	{"0000001000010011111010101001010011011110001100100011100100000100",0x00002815,0xFFFFF20E,0x000003DD,0x00001C33,0xFFFFF7D5,0x0000032A,0x00001C33,0xFFFFF7D5,0x0000032A},
--	{"0000001000010011111100001111111111101111010110100010000110000100",0x00003CC2,0xFFFFE43E,0x000005DE,0x00002C16,0xFFFFECED,0x000004BA,0x00002C16,0xFFFFECED,0x000004BA},
--	{"0000001000010011111100001111111111101111010111000100000010000100",0x00003CFA,0xFFFFE1EE,0x00000673,0x00001F7D,0xFFFFF402,0x000003AE,0x00001F7D,0xFFFFF402,0x000003AE},
--	{"0000001000010011111100001111111111101111011000100010000100000100",0x0000486E,0xFFFFDD43,0x000006EE,0x000036F0,0xFFFFE609,0x000005D5,0x000036F0,0xFFFFE609,0x000005D5},
--	{"0000001000010011111100001111111111101111010111000100100101100100",0x000039FE,0xFFFFE41F,0x00000613,0x0000266C,0xFFFFEF35,0x0000047D,0x0000266C,0xFFFFEF35,0x0000047D},
--	{"0000001000010011111010101001010011011110000100100011000100100100",0x00002EA4,0xFFFFEE3B,0x00000462,0x00002126,0xFFFFF4E2,0x0000038F,0x00002126,0xFFFFF4E2,0x0000038F},
--	{"0000001000010011111100001111111111101111011010000011100101000100",0x00002D2E,0xFFFFEE7B,0x00000462,0x0000229D,0xFFFFF363,0x000003D4,0x0000229D,0xFFFFF363,0x000003D4},
--	{"0000001000010011111100001111111111101111010111100010100001000100",0x0000375C,0xFFFFE695,0x0000059D,0x00002319,0xFFFFF237,0x000003EE,0x00002319,0xFFFFF237,0x000003EE},
--	{"0000001000010011111100001111111111101111011100100101000011000100",0x00004522,0xFFFFDC71,0x0000075E,0x0000247E,0xFFFFF0A0,0x0000043C,0x0000247E,0xFFFFF0A0,0x0000043C},
--	{"0000001000010011111010101001010011011110000100100100100011100100",0x00002E58,0xFFFFECB9,0x000004A9,0x0000199A,0xFFFFF8CF,0x000002E9,0x0000199A,0xFFFFF8CF,0x000002E9},
--	{"0000001000010011111100001111111111101111011001000011100011100100",0x00003791,0xFFFFE5FE,0x000005B6,0x000029F5,0xFFFFED0D,0x000004CD,0x000029F5,0xFFFFED0D,0x000004CD},
--	{"0000001000010011111010101001010011011110001001000100000101000100",0x00002E9E,0xFFFFEC8D,0x000004C1,0x000019D0,0xFFFFF869,0x0000030F,0x000019D0,0xFFFFF869,0x0000030F},
--	{"0000001000010011111010101001010011011110001000000011100101100100",0x0000237C,0xFFFFF435,0x000003A6,0x000014EB,0xFFFFFBC4,0x000002AF,0x000014EB,0xFFFFFBC4,0x000002AF},
--	{"0000001000010011111100001111111111101111011001100010100100100100",0x00003FE5,0xFFFFE4A2,0x000005A0,0x00003416,0xFFFFE995,0x00000523,0x00003416,0xFFFFE995,0x00000523},
--	{"0000001000010011111100001111111111101111010111000000100100100100",0x00002B27,0xFFFFED51,0x000004A5,0x000025D1,0xFFFFEF18,0x00000492,0x000025D1,0xFFFFEF18,0x00000492},
--	{"0000001000010011111100001111111111101111011010000100100100000100",0x00002D77,0xFFFFED79,0x00000494,0x00002196,0xFFFFF352,0x000003DE,0x00002196,0xFFFFF352,0x000003DE},
--	{"0000001000010011111100001111111111101111010111000010000011000100",0x00003750,0xFFFFE6AC,0x00000596,0x00002524,0xFFFFF0B5,0x00000431,0x00002524,0xFFFFF0B5,0x00000431},
--	{"0000001000010011111010101001010011011110000100100010100101000100",0x00002896,0xFFFFF1BB,0x000003D9,0x00001CE0,0xFFFFF753,0x0000032F,0x00001CE0,0xFFFFF753,0x0000032F},
--	{"0000001000010011111100001111111111101111011001000001100110000100",0x00003CA7,0xFFFFE0F7,0x000006B1,0x00002CB8,0xFFFFE9AB,0x00000587,0x00002CB8,0xFFFFE9AB,0x00000587},
--	{"0000001000010011111010101001010011011110001100100010100001100100",0x00002513,0xFFFFF323,0x000003BC,0x00001965,0xFFFFF93C,0x000002F0,0x00001965,0xFFFFF93C,0x000002F0},
--	{"0000001000010011111100001111111111101111011001100010000101100100",0x00003914,0xFFFFE683,0x00000586,0x00003120,0xFFFFE9A6,0x00000543,0x00003120,0xFFFFE9A6,0x00000543},
--	{"0000001000010011111100001111111111101111011001000011100100000100",0x000040D0,0xFFFFE007,0x000006AC,0x00002B9E,0xFFFFEBF5,0x000004FB,0x00002B9E,0xFFFFEBF5,0x000004FB},
--	{"0000001000010011111100001111111111101111010110100100100010000100",0x00004412,0xFFFFDF5F,0x000006A9,0x00002A9E,0xFFFFEDCE,0x00000498,0x00002A9E,0xFFFFEDCE,0x00000498},
--	{"0000001000010011111100001111111111101111011000100100100010000100",0x000042A6,0xFFFFDFEF,0x00000696,0x00002E65,0xFFFFEAAE,0x00000529,0x00002E65,0xFFFFEAAE,0x00000529},
--	{"0000001000010011111010101001010011011110001100100010000100100100",0x000022E8,0xFFFFF565,0x0000035F,0x00001890,0xFFFFFA61,0x000002C6,0x00001890,0xFFFFFA61,0x000002C6},
--	{"0000001000010011111100001111111111101111011000100011100110100100",0x00004637,0xFFFFDDD8,0x000006E9,0x0000349D,0xFFFFE6C8,0x000005C7,0x0000349D,0xFFFFE6C8,0x000005C7},
--	{"0000001000010011111010101001010011011110001001100011100100000100",0x00004686,0xFFFFDC58,0x0000073D,0x00003972,0xFFFFE27B,0x0000068E,0x00003972,0xFFFFE27B,0x0000068E},
--	{"0000001000010011111100001111111111101111011010000000100011100100",0x00002B35,0xFFFFEE9C,0x0000046C,0x00001F5B,0xFFFFF4A3,0x000003A9,0x00001F5B,0xFFFFF4A3,0x000003A9},
--	{"0000001000010011111100001111111111101111011100100100000101000100",0x00003AC9,0xFFFFE3B2,0x0000061B,0x000023A1,0xFFFFF170,0x0000040F,0x000023A1,0xFFFFF170,0x0000040F},
--	{"0000001000010011111100001111111111101111010111100001100010000100",0x00003C50,0xFFFFE37E,0x00000617,0x0000218F,0xFFFFF339,0x000003C4,0x0000218F,0xFFFFF339,0x000003C4},
--	{"0000001000010011111100001111111111101111011001100011000001000100",0x00003793,0xFFFFE761,0x0000055D,0x000029C7,0xFFFFEE03,0x00000496,0x000029C7,0xFFFFEE03,0x00000496},
--	{"0000001000010011111100001111111111101111011001000011100010100100",0x000040B5,0xFFFFDF78,0x000006DA,0x00002DED,0xFFFFEA20,0x00000551,0x00002DED,0xFFFFEA20,0x00000551},
--	{"0000001000010011111100001111111111101111011000000001000101000100",0x000039D6,0xFFFFE37D,0x0000063C,0x00001AED,0xFFFFF6E2,0x00000331,0x00001AED,0xFFFFF6E2,0x00000331},
--	{"0000001000010011111100001111111111101111011001100010000101000100",0x0000431F,0xFFFFE09B,0x0000066A,0x00002BDF,0xFFFFED93,0x00000496,0x00002BDF,0xFFFFED93,0x00000496},
--	{"0000001000010011111100001111111111101111011000100011100001100100",0x00004887,0xFFFFDC65,0x00000721,0x00003669,0xFFFFE5C4,0x000005E9,0x00003669,0xFFFFE5C4,0x000005E9},
--	{"0000001000010011111100001111111111101111011001000000100100100100",0x00004120,0xFFFFDDAE,0x00000748,0x0000303B,0xFFFFE70D,0x000005FC,0x0000303B,0xFFFFE70D,0x000005FC},
--	{"0000001000010011111100001111111111101111010111100010100010100100",0x0000415D,0xFFFFE0BE,0x0000067B,0x00002FA7,0xFFFFEA28,0x00000538,0x00002FA7,0xFFFFEA28,0x00000538},
--	{"0000001000010011111100001111111111101111011010000001100100000100",0x00002B12,0xFFFFEFF9,0x00000428,0x00001DDA,0xFFFFF693,0x00000356,0x00001DDA,0xFFFFF693,0x00000356},
--	{"0000001000010011111100001111111111101111010111100011000110000100",0x00003ED3,0xFFFFE28D,0x0000062D,0x00002B00,0xFFFFED4E,0x000004B3,0x00002B00,0xFFFFED4E,0x000004B3},
--	{"0000001000010011111100001111111111101111011000100101000010100100",0x00004218,0xFFFFE039,0x0000068F,0x00002F84,0xFFFFEA0C,0x00000541,0x00002F84,0xFFFFEA0C,0x00000541},
--	{"0000001000010011111100001111111111101111010110100011100001000100",0x00003FF5,0xFFFFE2A3,0x00000617,0x00003017,0xFFFFEA7A,0x00000520,0x00003017,0xFFFFEA7A,0x00000520},
--	{"0000001000010011111100001111111111101111010110100000100010100100",0x00004304,0xFFFFDFCC,0x0000069E,0x00002E0C,0xFFFFEB51,0x00000505,0x00002E0C,0xFFFFEB51,0x00000505},
--	{"0000001000010011111100001111111111101111011001000001100101000100",0x00003D3A,0xFFFFE17F,0x00000687,0x0000284C,0xFFFFED83,0x000004CD,0x0000284C,0xFFFFED83,0x000004CD},
--	{"0000001000010011111100001111111111101111010111100100000010100100",0x000042F5,0xFFFFDF76,0x000006B2,0x000027B6,0xFFFFEF72,0x00000455,0x000027B6,0xFFFFEF72,0x00000455},
--	{"0000001000010011111100001111111111101111010111000011100011000100",0x00004267,0xFFFFDF29,0x000006D5,0x0000298F,0xFFFFEDBD,0x000004AC,0x0000298F,0xFFFFEDBD,0x000004AC},
--	{"0000001000010011111010101001010011011110001001000000100100100100",0x0000303E,0xFFFFEC00,0x000004CB,0x000021CD,0xFFFFF36E,0x000003D6,0x000021CD,0xFFFFF36E,0x000003D6},
--	{"0000001000010011111100001111111111101111010111100010100011000100",0x00003127,0xFFFFEBDB,0x000004A6,0x00002E95,0xFFFFEB78,0x000004F3,0x00002E95,0xFFFFEB78,0x000004F3},
--	{"0000001000010011111010101001010011011110000111000001000001100100",0x00002655,0xFFFFF2D9,0x000003CF,0x000019F5,0xFFFFF8E7,0x00000313,0x000019F5,0xFFFFF8E7,0x00000313},
--	{"0000001000010011111010101001010011011110000101100100000010000100",0x00002372,0xFFFFF449,0x0000039B,0x00001544,0xFFFFFC16,0x0000028B,0x00001544,0xFFFFFC16,0x0000028B},
--	{"0000001000010011111100001111111111101111011001100010100011000100",0x0000348E,0xFFFFEB20,0x000004B2,0x00002BE8,0xFFFFEE80,0x00000467,0x00002BE8,0xFFFFEE80,0x00000467},
--	{"0000001000010011111100001111111111101111010111100001000100000100",0x00004092,0xFFFFE073,0x0000069B,0x00002061,0xFFFFF403,0x000003A0,0x00002061,0xFFFFF403,0x000003A0},
--	{"0000001000010011111100001111111111101111011100100010000011100100",0x000039D1,0xFFFFE55D,0x000005CC,0x000025CB,0xFFFFF0C0,0x00000428,0x000025CB,0xFFFFF0C0,0x00000428},
--	{"0000001000010011111100001111111111101111010111100100100010000100",0x000042AA,0xFFFFDF68,0x000006C2,0x0000290B,0xFFFFEE78,0x00000485,0x0000290B,0xFFFFEE78,0x00000485},
--	{"0000001000010011111100001111111111101111011100100001100011000100",0x0000356F,0xFFFFE7AC,0x0000056E,0x00001BE8,0xFFFFF6E3,0x0000032A,0x00001BE8,0xFFFFF6E3,0x0000032A},
--	{"0000001000010011111100001111111111101111010111100001000101000100",0x00003525,0xFFFFE7FF,0x0000055D,0x0000242C,0xFFFFF12E,0x0000041D,0x0000242C,0xFFFFF12E,0x0000041D},
--	{"0000001000010011111100001111111111101111010111000100100011000100",0x00003360,0xFFFFE895,0x00000550,0x00002175,0xFFFFF29E,0x000003E9,0x00002175,0xFFFFF29E,0x000003E9},
--	{"0000001000010011111100001111111111101111011001000100000010100100",0x00003C94,0xFFFFE1C4,0x0000067E,0x00002E28,0xFFFFE964,0x0000057F,0x00002E28,0xFFFFE964,0x0000057F},
--	{"0000001000010011111100001111111111101111011100100100000100100100",0x0000431C,0xFFFFDE4B,0x000006FF,0x00002270,0xFFFFF268,0x000003E5,0x00002270,0xFFFFF268,0x000003E5},
--	{"0000001000010011111010101001010011011110000100100001100011000100",0x00002B67,0xFFFFF01D,0x00000414,0x000019FB,0xFFFFF961,0x000002D8,0x000019FB,0xFFFFF961,0x000002D8},
--	{"0000001000010011111100001111111111101111010111100011100110000100",0x0000400B,0xFFFFE13D,0x0000066F,0x000024F3,0xFFFFF125,0x00000417,0x000024F3,0xFFFFF125,0x00000417},
--	{"0000001000010011111100001111111111101111010110100010000010100100",0x00004460,0xFFFFE00E,0x0000067B,0x000023DF,0xFFFFF2E6,0x000003BB,0x000023DF,0xFFFFF2E6,0x000003BB},
--	{"0000001000010011111100001111111111101111011001000001100001100100",0x00003AFB,0xFFFFE2C5,0x00000650,0x00002D46,0xFFFFE9C4,0x00000571,0x00002D46,0xFFFFE9C4,0x00000571},
--	{"0000001000010011111100001111111111101111011000100010100100100100",0x00005482,0xFFFFD5BC,0x0000081A,0x00003250,0xFFFFE961,0x00000541,0x00003250,0xFFFFE961,0x00000541},
--	{"0000001000010011111100001111111111101111010111000010100101000100",0x00003D27,0xFFFFE2FA,0x00000632,0x00002A4D,0xFFFFED6A,0x000004BB,0x00002A4D,0xFFFFED6A,0x000004BB},
--	{"0000001000010011111100001111111111101111011000000001100010100100",0x00003E03,0xFFFFE142,0x00000690,0x00001E08,0xFFFFF555,0x0000036C,0x00001E08,0xFFFFF555,0x0000036C},
--	{"0000001000010011111100001111111111101111010111000010000001100100",0x000031B5,0xFFFFE97D,0x00000535,0x0000232E,0xFFFFF166,0x00000422,0x0000232E,0xFFFFF166,0x00000422},
--	{"0000001000010011111100001111111111101111010111100001100011100100",0x00003753,0xFFFFE724,0x00000575,0x0000281A,0xFFFFEF1A,0x0000046B,0x0000281A,0xFFFFEF1A,0x0000046B},
--	{"0000001000010011111010101001010011011110001000000100000101000100",0x00002071,0xFFFFF5C9,0x0000036F,0x00001470,0xFFFFFBF7,0x000002A5,0x00001470,0xFFFFFBF7,0x000002A5},
--	{"0000001000010011111100001111111111101111011010000011000101000100",0x00002799,0xFFFFF223,0x000003CF,0x00001CD3,0xFFFFF74A,0x00000333,0x00001CD3,0xFFFFF74A,0x00000333},
--	{"0000001000010011111100001111111111101111011001100001000011000100",0x000040DF,0xFFFFE11C,0x00000664,0x000031D4,0xFFFFE8BC,0x0000056F,0x000031D4,0xFFFFE8BC,0x0000056F},
--	{"0000001000010011111100001111111111101111011001000100000011000100",0x00003A4D,0xFFFFE3A6,0x00000627,0x00002871,0xFFFFEDA0,0x000004C0,0x00002871,0xFFFFEDA0,0x000004C0},
--	{"0000001000010011111100001111111111101111011010000001100110000100",0x00002AF9,0xFFFFEED7,0x00000464,0x0000219B,0xFFFFF368,0x000003D6,0x0000219B,0xFFFFF368,0x000003D6},
--	{"0000001000010011111010101001010011011110001100100011000100100100",0x000026D5,0xFFFFF36C,0x000003A3,0x00001BC6,0xFFFFF881,0x00000311,0x00001BC6,0xFFFFF881,0x00000311},
--	{"0000001000010011111100001111111111101111010111100010000001000100",0x0000325D,0xFFFFEA07,0x0000050B,0x000026D1,0xFFFFEFB3,0x0000045A,0x000026D1,0xFFFFEFB3,0x0000045A},
--	{"0000001000010011111100001111111111101111011010000010100001100100",0x00002F75,0xFFFFEC64,0x000004BE,0x00001EEB,0xFFFFF559,0x00000386,0x00001EEB,0xFFFFF559,0x00000386},
--	{"0000001000010011111100001111111111101111010110100011100010100100",0x00003C2F,0xFFFFE541,0x000005A3,0x000025B6,0xFFFFF16F,0x000003FA,0x000025B6,0xFFFFF16F,0x000003FA},
--	{"0000001000010011111100001111111111101111011010000100100100100100",0x00002BC2,0xFFFFEE89,0x0000046A,0x00001D04,0xFFFFF651,0x00000361,0x00001D04,0xFFFFF651,0x00000361},
--	{"0000001000010011111100001111111111101111011010000010100110100100",0x00002DD0,0xFFFFED40,0x0000049F,0x00001C8C,0xFFFFF6B3,0x00000353,0x00001C8C,0xFFFFF6B3,0x00000353},
--	{"0000001000010011111010101001010011011110000111000000100011100100",0x000021ED,0xFFFFF530,0x00000380,0x00001643,0xFFFFFB1C,0x000002C3,0x00001643,0xFFFFFB1C,0x000002C3},
--	{"0000001000010011111010101001010011011110001100100001100100000100",0x000028C7,0xFFFFF160,0x000003FD,0x00001990,0xFFFFF994,0x000002E2,0x00001990,0xFFFFF994,0x000002E2},
--	{"0000001000010011111100001111111111101111011001100001000010100100",0x0000431C,0xFFFFDF9D,0x000006A3,0x000034A6,0xFFFFE6B0,0x000005C9,0x000034A6,0xFFFFE6B0,0x000005C9},
--	{"0000001000010011111010101001010011011110001001100011000010100100",0x00004115,0xFFFFE0D6,0x00000667,0x000031AD,0xFFFFE850,0x00000585,0x000031AD,0xFFFFE850,0x00000585},
--	{"0000001000010011111100001111111111101111011001000011100100100100",0x0000424A,0xFFFFDEEC,0x000006E1,0x0000346A,0xFFFFE5EA,0x00000602,0x0000346A,0xFFFFE5EA,0x00000602},
--	{"0000001000010011111100001111111111101111011001100001100110000100",0x00004990,0xFFFFDAFA,0x00000771,0x00002A9C,0xFFFFED37,0x000004BC,0x00002A9C,0xFFFFED37,0x000004BC},
--	{"0000001000010011111100001111111111101111011001000010100010100100",0x00003858,0xFFFFE568,0x000005D2,0x00003030,0xFFFFE8B0,0x0000058E,0x00003030,0xFFFFE8B0,0x0000058E},
--	{"0000001000010011111100001111111111101111011010000100000101100100",0x00001EDC,0xFFFFF6CD,0x00000322,0x00001FCA,0xFFFFF4BD,0x0000039E,0x00001FCA,0xFFFFF4BD,0x0000039E},
--	{"0000001000010011111100001111111111101111011001100010000100100100",0x00004C88,0xFFFFDBA3,0x0000071B,0x000030C4,0xFFFFEAFD,0x000004F7,0x000030C4,0xFFFFEAFD,0x000004F7},
--	{"0000001000010011111100001111111111101111011010000000100100000100",0x00002B9A,0xFFFFEE41,0x0000047D,0x00002131,0xFFFFF344,0x000003E5,0x00002131,0xFFFFF344,0x000003E5},
--	{"0000001000010011111100001111111111101111011000100011100110000100",0x00003E4B,0xFFFFE33C,0x000005FA,0x00003877,0xFFFFE437,0x0000062E,0x00003877,0xFFFFE437,0x0000062E},
--	{"0000001000010011111010101001010011011110001100100010000001100100",0x00002376,0xFFFFF444,0x0000038A,0x000017ED,0xFFFFFA4C,0x000002C1,0x000017ED,0xFFFFFA4C,0x000002C1},
--	{"0000001000010011111100001111111111101111011001100001000010000100",0x00004517,0xFFFFDDF4,0x000006F2,0x000030DC,0xFFFFE8EF,0x00000571,0x000030DC,0xFFFFE8EF,0x00000571},
--	{"0000001000010011111100001111111111101111011010000001100101000100",0x0000270C,0xFFFFF1F3,0x000003DF,0x0000207B,0xFFFFF474,0x000003AD,0x0000207B,0xFFFFF474,0x000003AD},
--	{"0000001000010011111100001111111111101111011001000101000101000100",0x00004086,0xFFFFDF39,0x000006E3,0x00002A24,0xFFFFEC2B,0x000004FF,0x00002A24,0xFFFFEC2B,0x000004FF},
--	{"0000001000010011111100001111111111101111010111000011000100100100",0x00003BDE,0xFFFFE45E,0x000005EB,0x00002CD5,0xFFFFEC45,0x000004DD,0x00002CD5,0xFFFFEC45,0x000004DD},
--	{"0000001000010011111100001111111111101111011100100011000011100100",0x00003803,0xFFFFE714,0x00000579,0x0000288A,0xFFFFEF21,0x0000046B,0x0000288A,0xFFFFEF21,0x0000046B},
--	{"0000001000010011111100001111111111101111011000000001000100000100",0x00003F50,0xFFFFE002,0x000006CD,0x00001AD4,0xFFFFF72E,0x0000031F,0x00001AD4,0xFFFFF72E,0x0000031F},
--	{"0000001000010011111100001111111111101111011010000010000011100100",0x00002968,0xFFFFF100,0x00000402,0x00001FB5,0xFFFFF57C,0x0000037F,0x00001FB5,0xFFFFF57C,0x0000037F},
--	{"0000001000010011111100001111111111101111011001100010000100000100",0x00004283,0xFFFFE2A7,0x000005F5,0x00003165,0xFFFFEB0C,0x000004EC,0x00003165,0xFFFFEB0C,0x000004EC},
--	{"0000001000010011111100001111111111101111011001000011000110100100",0x00004253,0xFFFFDDA8,0x00000732,0x00002E5C,0xFFFFE90A,0x00000593,0x00002E5C,0xFFFFE90A,0x00000593},
--	{"0000001000010011111100001111111111101111010111000101000010100100",0x00003551,0xFFFFE756,0x0000058D,0x000029A7,0xFFFFED0C,0x000004DE,0x000029A7,0xFFFFED0C,0x000004DE},
--	{"0000001000010011111100001111111111101111011001000010100011000100",0x00003728,0xFFFFE604,0x000005C4,0x00002832,0xFFFFEE64,0x00000493,0x00002832,0xFFFFEE64,0x00000493},
--	{"0000001000010011111100001111111111101111011000100011100101100100",0x00004796,0xFFFFDCC8,0x00000715,0x000032AB,0xFFFFE848,0x0000057C,0x000032AB,0xFFFFE848,0x0000057C},
--	{"0000001000010011111100001111111111101111011000100001000011000100",0x000049DF,0xFFFFDB24,0x0000075F,0x00003076,0xFFFFE967,0x0000055C,0x00003076,0xFFFFE967,0x0000055C},
--	{"0000001000010011111100001111111111101111011100100001000100000100",0x00003F13,0xFFFFE099,0x000006A8,0x00002279,0xFFFFF226,0x000003F3,0x00002279,0xFFFFF226,0x000003F3},
--	{"0000001000010011111100001111111111101111011001000011000010100100",0x00003E03,0xFFFFE19F,0x00000674,0x00002D66,0xFFFFEAA7,0x00000537,0x00002D66,0xFFFFEAA7,0x00000537},
--	{"0000001000010011111100001111111111101111010111000100000100000100",0x000037DA,0xFFFFE63F,0x000005A7,0x00002543,0xFFFFF0A0,0x00000431,0x00002543,0xFFFFF0A0,0x00000431},
--	{"0000001000010011111100001111111111101111011000100100100101000100",0x00003D82,0xFFFFE3F5,0x000005D9,0x0000332F,0xFFFFE834,0x00000577,0x0000332F,0xFFFFE834,0x00000577},
--	{"0000001000010011111010101001010011011110000100100010100011000100",0x00002915,0xFFFFF1E0,0x000003D4,0x00002065,0xFFFFF57B,0x00000378,0x00002065,0xFFFFF57B,0x00000378},
--	{"0000001000010011111100001111111111101111010111100100100100000100",0x000036FC,0xFFFFE72D,0x00000577,0x00002811,0xFFFFEF30,0x00000464,0x00002811,0xFFFFEF30,0x00000464},
--	{"0000001000010011111100001111111111101111011000100011000110000100",0x00004767,0xFFFFDD30,0x000006FD,0x00003703,0xFFFFE564,0x000005F8,0x00003703,0xFFFFE564,0x000005F8},
--	{"0000001000010011111100001111111111101111011000000011000110000100",0x00003094,0xFFFFEAA9,0x000004F5,0x000022E7,0xFFFFF200,0x000003FB,0x000022E7,0xFFFFF200,0x000003FB},
--	{"0000001000010011111100001111111111101111011001000001000101000100",0x00003EF0,0xFFFFDF83,0x000006ED,0x00002A27,0xFFFFEB7C,0x00000537,0x00002A27,0xFFFFEB7C,0x00000537},
--	{"0000001000010011111100001111111111101111011010000001000100100100",0x0000243C,0xFFFFF358,0x000003AC,0x00001DC4,0xFFFFF5E9,0x00000372,0x00001DC4,0xFFFFF5E9,0x00000372},
--	{"0000001000010011111100001111111111101111011100100010000101000100",0x0000284B,0xFFFFF036,0x0000040F,0x00001FCD,0xFFFFF445,0x00000395,0x00001FCD,0xFFFFF445,0x00000395},
--	{"0000001000010011111100001111111111101111011010000100000011000100",0x00002611,0xFFFFF285,0x000003C7,0x00001CFE,0xFFFFF6A0,0x00000355,0x00001CFE,0xFFFFF6A0,0x00000355},
--	{"0000001000010011111010101001010011011110000111000011100110100100",0x00002292,0xFFFFF49F,0x00000393,0x000017F4,0xFFFFF9CD,0x000002F5,0x000017F4,0xFFFFF9CD,0x000002F5},
--	{"0000001000010011111100001111111111101111010111100011100010100100",0x000037F3,0xFFFFE68D,0x00000590,0x00002443,0xFFFFF1AD,0x000003FA,0x00002443,0xFFFFF1AD,0x000003FA},
--	{"0000001000010011111100001111111111101111011010000010000101000100",0x00002C01,0xFFFFEF3F,0x00000444,0x0000210A,0xFFFFF475,0x000003A7,0x0000210A,0xFFFFF475,0x000003A7},
--	{"0000001000010011111010101001010011011110000100100001000011100100",0x00002C0E,0xFFFFEF0F,0x00000446,0x00001A82,0xFFFFF8F7,0x000002DE,0x00001A82,0xFFFFF8F7,0x000002DE},
--	{"0000001000010011111100001111111111101111010111100010000011000100",0x00003FA6,0xFFFFE20A,0x0000063F,0x00002E29,0xFFFFEB21,0x00000510,0x00002E29,0xFFFFEB21,0x00000510},
--	{"0000001000010011111100001111111111101111010111000010000101100100",0x00003BCD,0xFFFFE31B,0x0000063C,0x000019AF,0xFFFFF83D,0x000002F8,0x000019AF,0xFFFFF83D,0x000002F8},
--	{"0000001000010011111100001111111111101111011001100100000101100100",0x000044C8,0xFFFFDF08,0x000006B0,0x00002E2E,0xFFFFEB62,0x000004FD,0x00002E2E,0xFFFFEB62,0x000004FD},
--	{"0000001000010011111100001111111111101111010111000001100010000100",0x00003790,0xFFFFE571,0x000005E3,0x00002042,0xFFFFF35D,0x000003CF,0x00002042,0xFFFFF35D,0x000003CF},
--	{"0000001000010011111100001111111111101111011000000101000011100100",0x000038AC,0xFFFFE46C,0x00000609,0x0000215E,0xFFFFF22D,0x00000403,0x0000215E,0xFFFFF22D,0x00000403},
--	{"0000001000010011111100001111111111101111010111100010100110100100",0x00003A1E,0xFFFFE536,0x000005C9,0x000024F3,0xFFFFF11A,0x0000041B,0x000024F3,0xFFFFF11A,0x0000041B},
--	{"0000001000010011111100001111111111101111011001100101000011100100",0x0000431A,0xFFFFDF1B,0x000006C5,0x00002F34,0xFFFFEA02,0x00000545,0x00002F34,0xFFFFEA02,0x00000545},
--	{"0000001000010011111100001111111111101111011001000001100100000100",0x000042DC,0xFFFFDE28,0x0000070C,0x00003B53,0xFFFFE0EA,0x000006E2,0x00003B53,0xFFFFE0EA,0x000006E2},
--	{"0000001000010011111100001111111111101111011010000011000101100100",0x0000264B,0xFFFFF29A,0x000003C4,0x000021D0,0xFFFFF3CE,0x000003C4,0x000021D0,0xFFFFF3CE,0x000003C4},
--	{"0000001000010011111100001111111111101111010110100100000001100100",0x00004225,0xFFFFE0E8,0x00000665,0x00002B53,0xFFFFED89,0x0000049F,0x00002B53,0xFFFFED89,0x0000049F},
--	{"0000001000010011111010101001010011011110001000000100100100100100",0x00001FCC,0xFFFFF63F,0x00000358,0x000019E8,0xFFFFF882,0x0000032A,0x000019E8,0xFFFFF882,0x0000032A},
--	{"0000001000010011111100001111111111101111011000100100000010100100",0x000045E0,0xFFFFDDD0,0x000006ED,0x00003193,0xFFFFE8BD,0x00000572,0x00003193,0xFFFFE8BD,0x00000572},
--	{"0000001000010011111100001111111111101111011010000011100100100100",0x000024FC,0xFFFFF366,0x000003A6,0x00001FE8,0xFFFFF509,0x00000394,0x00001FE8,0xFFFFF509,0x00000394},
--	{"0000001000010011111100001111111111101111010111000100100010000100",0x0000378F,0xFFFFE54B,0x000005F1,0x00001C9B,0xFFFFF5C7,0x00000368,0x00001C9B,0xFFFFF5C7,0x00000368},
--	{"0000001000010011111100001111111111101111011001000001100010100100",0x00003CF3,0xFFFFE15A,0x00000694,0x00002CDD,0xFFFFEA44,0x00000557,0x00002CDD,0xFFFFEA44,0x00000557},
--	{"0000001000010011111010101001010011011110001000000000100100000100",0x000021EC,0xFFFFF4F4,0x0000038F,0x00001511,0xFFFFFBF5,0x0000029E,0x00001511,0xFFFFFBF5,0x0000029E},
--	{"0000001000010011111100001111111111101111011000000001000010100100",0x00003C8A,0xFFFFE1C1,0x00000685,0x000019C7,0xFFFFF7E2,0x00000301,0x000019C7,0xFFFFF7E2,0x00000301},
--	{"0000001000010011111100001111111111101111010111100010000001100100",0x00003908,0xFFFFE5C7,0x000005B3,0x00002793,0xFFFFEF46,0x00000465,0x00002793,0xFFFFEF46,0x00000465},
--	{"0000001000010011111100001111111111101111011000000101000100000100",0x000040A3,0xFFFFDE61,0x00000725,0x00002077,0xFFFFF2CE,0x000003E8,0x00002077,0xFFFFF2CE,0x000003E8},
--	{"0000001000010011111100001111111111101111011001100100000101000100",0x00003DCA,0xFFFFE34D,0x00000608,0x00002D66,0xFFFFEBDF,0x000004E8,0x00002D66,0xFFFFEBDF,0x000004E8},
--	{"0000001000010011111100001111111111101111010111100101000011000100",0x00003085,0xFFFFEB70,0x000004C8,0x000029B1,0xFFFFEDD9,0x000004A5,0x000029B1,0xFFFFEDD9,0x000004A5},
--	{"0000001000010011111010101001010011011110000010000011100010000100",0x00004C73,0xFFFFD676,0x0000086C,0x0000280A,0xFFFFED89,0x000004C2,0x0000280A,0xFFFFED89,0x000004C2},
--	{"0000001000010011111010101001010011011110001001000010000101100100",0x00002CE5,0xFFFFEE8C,0x00000466,0x00001755,0xFFFFFAC2,0x000002AC,0x00001755,0xFFFFFAC2,0x000002AC},
--	{"0000001000010011111100001111111111101111011000100001000100100100",0x0000489F,0xFFFFDBF1,0x0000073E,0x0000332D,0xFFFFE786,0x000005AD,0x0000332D,0xFFFFE786,0x000005AD},
--	{"0000001000010011111100001111111111101111011000000010100001100100",0x00003D09,0xFFFFE193,0x00000689,0x00001E82,0xFFFFF4C0,0x00000386,0x00001E82,0xFFFFF4C0,0x00000386},
--	{"0000001000010011111100001111111111101111011001000100000100000100",0x00003E4C,0xFFFFE131,0x00000689,0x00002F4E,0xFFFFE925,0x0000057B,0x00002F4E,0xFFFFE925,0x0000057B},
--	{"0000001000010011111100001111111111101111010110100100000010000100",0x00003B31,0xFFFFE53F,0x000005B3,0x0000248A,0xFFFFF211,0x000003DF,0x0000248A,0xFFFFF211,0x000003DF},
--	{"0000001000010011111100001111111111101111011001000100000100100100",0x000038DD,0xFFFFE54A,0x000005C9,0x00002B6D,0xFFFFEBDF,0x00000502,0x00002B6D,0xFFFFEBDF,0x00000502},
--	{"0000001000010011111100001111111111101111011010000100000001100100",0x00002698,0xFFFFF1A8,0x000003F2,0x00002163,0xFFFFF34B,0x000003E3,0x00002163,0xFFFFF34B,0x000003E3},
--	{"0000001000010011111010101001010011011110001000000001000001100100",0x000023A8,0xFFFFF4CD,0x00000386,0x00001944,0xFFFFF983,0x00000300,0x00001944,0xFFFFF983,0x00000300},
--	{"0000001000010011111100001111111111101111011001000001100011000100",0x00003EAF,0xFFFFE0C3,0x000006A0,0x000030AB,0xFFFFE829,0x000005A6,0x000030AB,0xFFFFE829,0x000005A6},
--	{"0000001000010011111100001111111111101111011010000100100101000100",0x00002E89,0xFFFFECA6,0x000004B6,0x00001FA0,0xFFFFF4A8,0x000003A3,0x00001FA0,0xFFFFF4A8,0x000003A3},
--	{"0000001000010011111100001111111111101111011010000010100010100100",0x000028A4,0xFFFFF112,0x00000402,0x00001F7C,0xFFFFF545,0x0000038A,0x00001F7C,0xFFFFF545,0x0000038A},
--	{"0000001000010011111100001111111111101111011001100101000010100100",0x00004135,0xFFFFDFA2,0x000006C5,0x0000324C,0xFFFFE7AA,0x000005AF,0x0000324C,0xFFFFE7AA,0x000005AF},
--	{"0000001000010011111010101001010011011110001000000011100011000100",0x00002012,0xFFFFF693,0x00000352,0x0000171F,0xFFFFFABB,0x000002D9,0x0000171F,0xFFFFFABB,0x000002D9},
--	{"0000001000010011111100001111111111101111011001000011000010000100",0x00003D7C,0xFFFFE1BC,0x00000671,0x00002A45,0xFFFFEC84,0x000004EC,0x00002A45,0xFFFFEC84,0x000004EC},
--	{"0000001000010011111100001111111111101111011100100011000001100100",0x00004172,0xFFFFDF58,0x000006DA,0x00002504,0xFFFFF0A6,0x00000431,0x00002504,0xFFFFF0A6,0x00000431},
--	{"0000001000010011111100001111111010011001001010000001100101000100",0x000029C7,0xFFFFF087,0x00000414,0x00001DCB,0xFFFFF675,0x0000035F,0x00001DCB,0xFFFFF675,0x0000035F},
--	{"0000001000010011111100001111111010011001001010100010100110100100",0x000027F0,0xFFFFF05A,0x00000432,0x00001707,0xFFFFFA0E,0x000002D1,0x00001707,0xFFFFFA0E,0x000002D1},
--	{"0000001000010011111100001111111010011001001000100010000101000100",0x00003279,0xFFFFE9F7,0x00000511,0x00001B5E,0xFFFFF787,0x00000317,0x00001B5E,0xFFFFF787,0x00000317},
--	{"0000001000010011111100001111111010011001001100100010000110000100",0x000030A5,0xFFFFEABC,0x000004FF,0x000019D1,0xFFFFF83C,0x00000304,0x000019D1,0xFFFFF83C,0x00000304},
--	{"0000001000010011111100001111111010011001001010000010100001000100",0x0000283B,0xFFFFF122,0x00000402,0x000019C2,0xFFFFF8E9,0x000002FB,0x000019C2,0xFFFFF8E9,0x000002FB},
--	{"0000001000010011111100001111111010011001001011000010000010000100",0x00003376,0xFFFFE9E1,0x00000510,0x000021A7,0xFFFFF39F,0x000003BF,0x000021A7,0xFFFFF39F,0x000003BF},
--	{"0000001000010011111100001111111010011001001100100001100011000100",0x000031D2,0xFFFFEA9C,0x000004FC,0x00001F66,0xFFFFF4E4,0x00000390,0x00001F66,0xFFFFF4E4,0x00000390},
--	{"0000001000010011111100001111111010011001000110100011100001100100",0x00003006,0xFFFFEB18,0x000004F2,0x000019B3,0xFFFFF84E,0x00000301,0x000019B3,0xFFFFF84E,0x00000301},
--	{"0000001000010011111100001111111010011001001100000011100110100100",0x0000364F,0xFFFFE81F,0x00000556,0x00002AC9,0xFFFFED87,0x000004BD,0x00002AC9,0xFFFFED87,0x000004BD},
--	{"0000001000010011111100001111111010011001001011100011100001000100",0x00003043,0xFFFFEBAE,0x000004CD,0x00001B0C,0xFFFFF7ED,0x0000030C,0x00001B0C,0xFFFFF7ED,0x0000030C},
--	{"0000001000010011111100001111111010011001001100000100100010100100",0x000037CE,0xFFFFE69E,0x00000596,0x0000276B,0xFFFFEF65,0x0000046E,0x0000276B,0xFFFFEF65,0x0000046E},
--	{"0000001000010011111100001111111010011001001011000011000100000100",0x00003063,0xFFFFED5E,0x0000046F,0x000024AE,0xFFFFF2C4,0x000003D8,0x000024AE,0xFFFFF2C4,0x000003D8},
--	{"0000001000010011111100001111111010011001001011100000100010100100",0x00002F5D,0xFFFFEBDC,0x000004D3,0x00001EDB,0xFFFFF50F,0x0000038E,0x00001EDB,0xFFFFF50F,0x0000038E},
--	{"0000001000010011111100001111111010011001001011100100100010100100",0x00003148,0xFFFFEA9A,0x000004FB,0x0000192D,0xFFFFF8E9,0x000002DF,0x0000192D,0xFFFFF8E9,0x000002DF},
--	{"0000001000010011111100001111111010011001001011000010000001100100",0x00003682,0xFFFFE7E4,0x0000055C,0x0000250E,0xFFFFF150,0x0000041A,0x0000250E,0xFFFFF150,0x0000041A},
--	{"0000001000010011111100001111111010011001001010100010000010000100",0x0000284E,0xFFFFF15A,0x000003F8,0x00001CE2,0xFFFFF6F9,0x0000034F,0x00001CE2,0xFFFFF6F9,0x0000034F},
--	{"0000001000010011111100001111111010011001001100000001100010100100",0x00003171,0xFFFFEAE9,0x000004ED,0x00001F40,0xFFFFF513,0x00000384,0x00001F40,0xFFFFF513,0x00000384},
--	{"0000001000010011111100001111111010011001001100100011000001000100",0x000031BD,0xFFFFEA64,0x0000050A,0x00001EFD,0xFFFFF4F7,0x00000390,0x00001EFD,0xFFFFF4F7,0x00000390},
--	{"0000001000010011111100001111111010011001001011100101000011100100",0x00003050,0xFFFFEB29,0x000004EA,0x000019B3,0xFFFFF878,0x000002F9,0x000019B3,0xFFFFF878,0x000002F9},
--	{"0000001000010011111100001111111010011001001011000001100100000100",0x00003400,0xFFFFE9A0,0x0000051A,0x00002460,0xFFFFF1DA,0x00000409,0x00002460,0xFFFFF1DA,0x00000409},
--	{"0000001000010011111100001111111010011001001011000100100010000100",0x000034A1,0xFFFFE86F,0x00000558,0x0000255D,0xFFFFF09E,0x00000443,0x0000255D,0xFFFFF09E,0x00000443},
--	{"0000001000010011111100001111111010011001001011100100100011100100",0x00003103,0xFFFFEAD7,0x000004F0,0x00001896,0xFFFFF95A,0x000002CC,0x00001896,0xFFFFF95A,0x000002CC},
--	{"0000001000010011111100001111111010011001001100000001100011100100",0x00003120,0xFFFFEB9E,0x000004CB,0x000021E8,0xFFFFF3A2,0x000003C1,0x000021E8,0xFFFFF3A2,0x000003C1},
--	{"0000001000010011111100001111111010011001000111000101000011100100",0x00003558,0xFFFFE812,0x00000565,0x0000256E,0xFFFFF097,0x00000447,0x0000256E,0xFFFFF097,0x00000447},
--	{"0000001000010011111100001111111010011001000110100010100001000100",0x00002DA8,0xFFFFECA8,0x000004B7,0x0000180B,0xFFFFF96D,0x000002D8,0x0000180B,0xFFFFF96D,0x000002D8},
--	{"0000001000010011111100001111111010011001001011100011000001100100",0x00003232,0xFFFFEA66,0x000004FF,0x00001DDE,0xFFFFF5FE,0x0000035A,0x00001DDE,0xFFFFF5FE,0x0000035A},
--	{"0000001000010011111100001111111010011001001100000101000011100100",0x000034D2,0xFFFFE89F,0x00000548,0x0000246C,0xFFFFF17F,0x00000418,0x0000246C,0xFFFFF17F,0x00000418},
--	{"0000001000010011111100001111111010011001001100000100100100000100",0x000033EC,0xFFFFE954,0x0000052A,0x00002323,0xFFFFF279,0x000003EE,0x00002323,0xFFFFF279,0x000003EE},
--	{"0000001000010011111100001111111010011001001100000011100010000100",0x000033AA,0xFFFFE955,0x0000052D,0x0000229F,0xFFFFF2B2,0x000003E7,0x0000229F,0xFFFFF2B2,0x000003E7},
--	{"0000001000010011111100001111111010011001001100100100100101100100",0x00003258,0xFFFFE9AA,0x0000052A,0x00001D5F,0xFFFFF5D1,0x0000036B,0x00001D5F,0xFFFFF5D1,0x0000036B},
--	{"0000001000010011111100001111111010011001001100000010100110100100",0x0000323A,0xFFFFEA5F,0x00000504,0x00002108,0xFFFFF3D5,0x000003BA,0x00002108,0xFFFFF3D5,0x000003BA},
--	{"0000001000010011111100001111111010011001001011000010000110000100",0x00003216,0xFFFFEA6B,0x000004FF,0x00001D6E,0xFFFFF640,0x00000350,0x00001D6E,0xFFFFF640,0x00000350},
--	{"0000001000010011111100001111111010011001001100100001000011100100",0x000030C5,0xFFFFEAC4,0x000004FC,0x00001924,0xFFFFF8C2,0x000002EE,0x00001924,0xFFFFF8C2,0x000002EE},
--	{"0000001000010011111100001111111010011001001100000101000100000100",0x000032BB,0xFFFFE9F1,0x00000515,0x00002211,0xFFFFF31B,0x000003D5,0x00002211,0xFFFFF31B,0x000003D5},
--	{"0000001000010011111100001111111010011001001100000100100011000100",0x0000352C,0xFFFFE85B,0x00000553,0x00002410,0xFFFFF1B4,0x0000040F,0x00002410,0xFFFFF1B4,0x0000040F},
--	{"0000001000010011111100001111111010011001001000100011100011000100",0x000036A0,0xFFFFE7E8,0x0000055D,0x00002901,0xFFFFEEB8,0x00000489,0x00002901,0xFFFFEEB8,0x00000489},
--	{"0000001000010011111100001111111010011001001011000011000001000100",0x00003340,0xFFFFE9D9,0x00000516,0x00002332,0xFFFFF27A,0x000003F0,0x00002332,0xFFFFF27A,0x000003F0},
--	{"0000001000010011111100001111111010011001000110100011100010100100",0x00003564,0xFFFFE86D,0x0000054E,0x00002613,0xFFFFF07C,0x00000444,0x00002613,0xFFFFF07C,0x00000444},
--	{"0000001000010011111100001111111010011001001010000000100100000100",0x00002AD1,0xFFFFEF0B,0x0000045C,0x00001DEA,0xFFFFF5C8,0x00000381,0x00001DEA,0xFFFFF5C8,0x00000381},
--	{"0000001000010011111100001111111010011001001000100010000011100100",0x000035B0,0xFFFFE846,0x00000555,0x000027BE,0xFFFFEF5D,0x00000474,0x000027BE,0xFFFFEF5D,0x00000474},
--	{"0000001000010011111100001111111010011001001000100011100010100100",0x000032C4,0xFFFFEA48,0x00000502,0x000022C6,0xFFFFF2DF,0x000003DE,0x000022C6,0xFFFFF2DF,0x000003DE},
--	{"0000001000010011111100001111111010011001001100000000100011000100",0x00003036,0xFFFFEB0D,0x000004F9,0x00001FE8,0xFFFFF41A,0x000003BC,0x00001FE8,0xFFFFF41A,0x000003BC},
--	{"0000001000010011111100001111111010011001000110100000100100000100",0x000030F8,0xFFFFEA13,0x00000524,0x00001B6A,0xFFFFF6C9,0x0000034A,0x00001B6A,0xFFFFF6C9,0x0000034A},
--	{"0000001000010011111100001111111010011001001100000001000010100100",0x00002EE2,0xFFFFEC0C,0x000004CB,0x00001A39,0xFFFFF814,0x0000030F,0x00001A39,0xFFFFF814,0x0000030F},
--	{"0000001000010011111100001111111010011001000111000011000110000100",0x00003457,0xFFFFE924,0x0000052A,0x00001E9D,0xFFFFF59C,0x00000363,0x00001E9D,0xFFFFF59C,0x00000363},
--	{"0000001000010011111100001111111010011001001100100010100001000100",0x000030BF,0xFFFFEB18,0x000004ED,0x00001D37,0xFFFFF636,0x0000035C,0x00001D37,0xFFFFF636,0x0000035C},
--	{"0000001000010011111100001111111010011001001011100100000010000100",0x000031AF,0xFFFFEA75,0x000004FE,0x000019F2,0xFFFFF87A,0x000002F0,0x000019F2,0xFFFFF87A,0x000002F0},
--	{"0000001000010011111100001111111010011001001100000010100010000100",0x00003642,0xFFFFE85B,0x00000547,0x00002975,0xFFFFEE98,0x0000048B,0x00002975,0xFFFFEE98,0x0000048B},
--	{"0000001000010011111100001111111010011001001011100010100010000100",0x00002E8B,0xFFFFED1E,0x0000048E,0x000019C1,0xFFFFF917,0x000002D6,0x000019C1,0xFFFFF917,0x000002D6},
--	{"0000001000010011111100001111111010011001001100100100000110100100",0x000033D9,0xFFFFE8E1,0x00000548,0x0000224B,0xFFFFF298,0x000003F4,0x0000224B,0xFFFFF298,0x000003F4},
--	{"0000001000010011111100001111111010011001001011100010100011000100",0x000032BC,0xFFFFEB0F,0x000004D6,0x00002488,0xFFFFF240,0x000003F2,0x00002488,0xFFFFF240,0x000003F2},
--	{"0000001000010011111100001111111010011001001100000100100101000100",0x000035FD,0xFFFFE838,0x00000553,0x00002762,0xFFFFEFBC,0x00000460,0x00002762,0xFFFFEFBC,0x00000460},
--	{"0000001000010011111100001111111010011001001010000001100010100100",0x0000268B,0xFFFFF263,0x000003D1,0x00001914,0xFFFFF977,0x000002E8,0x00001914,0xFFFFF977,0x000002E8},
--	{"0000001000010011111100001111111010011001001011000011000110000100",0x0000330B,0xFFFFEA1E,0x00000505,0x000020B1,0xFFFFF44D,0x0000039E,0x000020B1,0xFFFFF44D,0x0000039E},
--	{"0000001000010011111100001111111010011001001000100010000010000100",0x0000326E,0xFFFFEA26,0x00000508,0x00001C17,0xFFFFF722,0x00000328,0x00001C17,0xFFFFF722,0x00000328},
--	{"0000001000010011111100001111111010011001001010100011000110100100",0x00002A3F,0xFFFFEEE8,0x0000046D,0x00001B2B,0xFFFFF737,0x0000034D,0x00001B2B,0xFFFFF737,0x0000034D},
--	{"0000001000010011111100001111111010011001001011000100000001100100",0x00003732,0xFFFFE765,0x00000574,0x00002A6D,0xFFFFEDA8,0x000004B7,0x00002A6D,0xFFFFEDA8,0x000004B7},
--	{"0000001000010011111100001111111010011001001100000000100100100100",0x000034D3,0xFFFFE827,0x00000569,0x000027AA,0xFFFFEEE7,0x00000492,0x000027AA,0xFFFFEEE7,0x00000492},
--	{"0000001000010011111100001111111010011001001011100100000011000100",0x00003306,0xFFFFEA39,0x000004FC,0x00001DCC,0xFFFFF655,0x00000344,0x00001DCC,0xFFFFF655,0x00000344},
--	{"0000001000010011111100001111111010011001001010000010000001000100",0x00002A48,0xFFFFEFCA,0x00000439,0x00001DED,0xFFFFF60D,0x00000375,0x00001DED,0xFFFFF60D,0x00000375},
--	{"0000001000010011111100001111111010011001001100000011100011000100",0x000033A3,0xFFFFEA36,0x000004F9,0x0000247C,0xFFFFF21F,0x000003F4,0x0000247C,0xFFFFF21F,0x000003F4},
--	{"0000001000010011111100001111111010011001001011000011000101100100",0x0000311B,0xFFFFEB76,0x000004D1,0x00001EB1,0xFFFFF5B6,0x00000366,0x00001EB1,0xFFFFF5B6,0x00000366},
--	{"0000001000010011111100001111111010011001001100100100000101100100",0x00003307,0xFFFFE97F,0x0000052A,0x00001E76,0xFFFFF54D,0x0000037C,0x00001E76,0xFFFFF54D,0x0000037C},
--	{"0000001000010011111100001111111010011001000111000010000101000100",0x0000344B,0xFFFFE9C5,0x00000509,0x000020D6,0xFFFFF486,0x0000038F,0x000020D6,0xFFFFF486,0x0000038F},
--	{"0000001000010011111100001111111010011001001011000011000101000100",0x000034B9,0xFFFFEA0B,0x000004F7,0x000027B3,0xFFFFF057,0x0000043A,0x000027B3,0xFFFFF057,0x0000043A},
--	{"0000001000010011111100001111111010011001001100000001100101100100",0x00003360,0xFFFFE984,0x00000527,0x00002238,0xFFFFF2EE,0x000003E0,0x00002238,0xFFFFF2EE,0x000003E0},
--	{"0000001000010011111100001111111010011001001100000010000100100100",0x0000315C,0xFFFFEC05,0x000004B1,0x000023C8,0xFFFFF2CC,0x000003DE,0x000023C8,0xFFFFF2CC,0x000003DE},
--	{"0000001000010011111100001111111010011001001011000010100001100100",0x0000389B,0xFFFFE6D5,0x00000582,0x00002C6C,0xFFFFEC92,0x000004DE,0x00002C6C,0xFFFFEC92,0x000004DE},
--	{"0000001000010011111100001111111010011001001011100001000100100100",0x00003058,0xFFFFEB30,0x000004E6,0x000019B5,0xFFFFF88B,0x000002F1,0x000019B5,0xFFFFF88B,0x000002F1},
--	{"0000001000010011111100001111111010011001001011100000100100000100",0x00002F69,0xFFFFEB4A,0x000004F1,0x00001B82,0xFFFFF6EC,0x00000341,0x00001B82,0xFFFFF6EC,0x00000341},
--	{"0000001000010011111100001111111010011001000110100001100011100100",0x000031EB,0xFFFFEA64,0x00000508,0x00002059,0xFFFFF427,0x000003B0,0x00002059,0xFFFFF427,0x000003B0},
--	{"0000001000010011111100001111111010011001001000100100000100100100",0x000033E2,0xFFFFE94D,0x0000052A,0x000020BF,0xFFFFF40B,0x000003AB,0x000020BF,0xFFFFF40B,0x000003AB},
--	{"0000001000010011111100001111111010011001001010000011000110000100",0x00002AF9,0xFFFFEFE9,0x00000427,0x00001F72,0xFFFFF57A,0x00000383,0x00001F72,0xFFFFF57A,0x00000383},
--	{"0000001000010011111100001111111010011001001011000010100000100100",0x00003282,0xFFFFEA88,0x000004FA,0x00002561,0xFFFFF126,0x0000042B,0x00002561,0xFFFFF126,0x0000042B},
--	{"0000001000010011111100001111111010011001001100000001000011100100",0x0000308A,0xFFFFEB5D,0x000004E0,0x00001E83,0xFFFFF577,0x00000378,0x00001E83,0xFFFFF577,0x00000378},
--	{"0000001000010011111100001111111010011001001100100100100010000100",0x0000336E,0xFFFFE8C8,0x00000553,0x0000217C,0xFFFFF2E1,0x000003EB,0x0000217C,0xFFFFF2E1,0x000003EB},
--	{"0000001000010011111100001111111010011001000110100010000101100100",0x000034A9,0xFFFFE838,0x00000561,0x000020CE,0xFFFFF38A,0x000003C7,0x000020CE,0xFFFFF38A,0x000003C7},
--	{"0000001000010011111100001111111010011001001000100010000110000100",0x00003152,0xFFFFE9EB,0x00000522,0x00001755,0xFFFFF9A9,0x000002C6,0x00001755,0xFFFFF9A9,0x000002C6},
--	{"0000001000010011111100001111111010011001001010000001100010000100",0x0000286E,0xFFFFF136,0x000003FD,0x00001BAB,0xFFFFF7C3,0x0000032C,0x00001BAB,0xFFFFF7C3,0x0000032C},
--	{"0000001000010011111100001111111010011001001100000000100101000100",0x0000316B,0xFFFFEA02,0x00000528,0x00002247,0xFFFFF24E,0x00000408,0x00002247,0xFFFFF24E,0x00000408},
--	{"0000001000010011111100001111111010011001001011000000100011100100",0x000034CF,0xFFFFE83D,0x00000562,0x00002458,0xFFFFF130,0x00000430,0x00002458,0xFFFFF130,0x00000430},
--	{"0000001000010011111100001111111010011001001011000010100110000100",0x00003352,0xFFFFE9D1,0x00000515,0x0000212A,0xFFFFF3DC,0x000003B4,0x0000212A,0xFFFFF3DC,0x000003B4},
--	{"0000001000010011111100001111111010011001001010000100000010100100",0x00002946,0xFFFFF09B,0x00000415,0x00001DC9,0xFFFFF650,0x00000366,0x00001DC9,0xFFFFF650,0x00000366},
--	{"0000001000010011111100001111111010011001001100000001000100100100",0x00003080,0xFFFFEB47,0x000004E1,0x00001BD5,0xFFFFF73B,0x00000329,0x00001BD5,0xFFFFF73B,0x00000329},
--	{"0000001000010011111100001111111010011001000110100001100010000100",0x00002FBD,0xFFFFEB7B,0x000004DD,0x000017FC,0xFFFFF99E,0x000002C7,0x000017FC,0xFFFFF99E,0x000002C7},
--	{"0000001000010011111100001111111010011001001010000001000100100100",0x00002A28,0xFFFFF032,0x0000041F,0x00001B19,0xFFFFF83A,0x00000312,0x00001B19,0xFFFFF83A,0x00000312},
--	{"0000001000010011111100001111111010011001001000100100000011000100",0x00003420,0xFFFFE936,0x00000530,0x000023C2,0xFFFFF203,0x00000406,0x000023C2,0xFFFFF203,0x00000406},
--	{"0000001000010011111100001111111010011001001100000001000101000100",0x00002F7C,0xFFFFEBBA,0x000004D1,0x0000185D,0xFFFFF975,0x000002CA,0x0000185D,0xFFFFF975,0x000002CA},
--	{"0000001000010011111100001111111010011001001011100010000001000100",0x00002C51,0xFFFFEE3B,0x0000046F,0x000019AA,0xFFFFF8DD,0x000002ED,0x000019AA,0xFFFFF8DD,0x000002ED},
--	{"0000001000010011111100001111111010011001000110100100000101000100",0x000033D6,0xFFFFE8F2,0x0000053D,0x00001D73,0xFFFFF5FB,0x0000035B,0x00001D73,0xFFFFF5FB,0x0000035B},
--	{"0000001000010011111100001111111010011001001100100011000010000100",0x000031D9,0xFFFFEAF7,0x000004E4,0x00001EBD,0xFFFFF5A6,0x00000368,0x00001EBD,0xFFFFF5A6,0x00000368},
--	{"0000001000010011111100001111111010011001000110100010000010100100",0x00003386,0xFFFFE9CE,0x00000515,0x00002422,0xFFFFF1F3,0x00000405,0x00002422,0xFFFFF1F3,0x00000405},
--	{"0000001000010011111100001111111010011001001011000101000011100100",0x000032FB,0xFFFFE9BC,0x00000520,0x00002301,0xFFFFF267,0x000003F7,0x00002301,0xFFFFF267,0x000003F7},
--	{"0000001000010011111100001111111010011001001100100010100100100100",0x000032C2,0xFFFFEAC0,0x000004EA,0x0000250F,0xFFFFF1A2,0x00000413,0x0000250F,0xFFFFF1A2,0x00000413},
--	{"0000001000010011111100001111111010011001000111000010100101000100",0x00003722,0xFFFFE8A6,0x00000527,0x000026E4,0xFFFFF0F5,0x0000041C,0x000026E4,0xFFFFF0F5,0x0000041C},
--	{"0000001000010011111100001111111010011001001011000100100011000100",0x000035A4,0xFFFFE822,0x00000558,0x000022F2,0xFFFFF288,0x000003E8,0x000022F2,0xFFFFF288,0x000003E8},
--	{"0000001000010011111100001111111010011001001010000000100100100100",0x00002CD1,0xFFFFEDC6,0x0000048C,0x00001EAF,0xFFFFF53D,0x00000396,0x00001EAF,0xFFFFF53D,0x00000396},
--	{"0000001000010011111100001111111010011001001100000001000101100100",0x00003156,0xFFFFEA60,0x0000050B,0x00001BBC,0xFFFFF704,0x00000335,0x00001BBC,0xFFFFF704,0x00000335},
--	{"0000001000010011111100001111111010011001001011000101000100000100",0x000034A1,0xFFFFE8C0,0x00000544,0x00002528,0xFFFFF105,0x0000042C,0x00002528,0xFFFFF105,0x0000042C},
--	{"0000001000010011111100001111111010011001001100100011000001100100",0x000032CE,0xFFFFE9D3,0x00000520,0x000021FF,0xFFFFF2FD,0x000003E4,0x000021FF,0xFFFFF2FD,0x000003E4},
--	{"0000001000010011111100001111111010011001000110100101000010100100",0x000034A0,0xFFFFE823,0x0000056D,0x0000256F,0xFFFFF047,0x0000045A,0x0000256F,0xFFFFF047,0x0000045A},
--	{"0000001000010011111100001111111010011001001100000011100101000100",0x00003109,0xFFFFEBD6,0x000004BF,0x000022D4,0xFFFFF32D,0x000003D0,0x000022D4,0xFFFFF32D,0x000003D0},
--	{"0000001000010011111100001111111010011001001011000001000101100100",0x000030B7,0xFFFFEAF0,0x000004F3,0x00001AEC,0xFFFFF7A9,0x0000031B,0x00001AEC,0xFFFFF7A9,0x0000031B},
--	{"0000001000010011111100001111111010011001001011000011100110100100",0x00003078,0xFFFFEBA4,0x000004CF,0x00001E7A,0xFFFFF5AF,0x0000036B,0x00001E7A,0xFFFFF5AF,0x0000036B},
--	{"0000001000010011111100001111111010011001001100000100000100100100",0x00003442,0xFFFFE998,0x00000518,0x000025EA,0xFFFFF0F3,0x0000042B,0x000025EA,0xFFFFF0F3,0x0000042B},
--	{"0000001000010011111100001111111010011001001100000010000110100100",0x000031CB,0xFFFFEA80,0x00000501,0x000020A3,0xFFFFF403,0x000003B2,0x000020A3,0xFFFFF403,0x000003B2},
--	{"0000001000010011111100001111111010011001001010100010100110000100",0x00002947,0xFFFFF018,0x00000433,0x00001BA5,0xFFFFF75C,0x00000340,0x00001BA5,0xFFFFF75C,0x00000340},
--	{"0000001000010011111100001111111010011001001011000011100110000100",0x000033F9,0xFFFFE99D,0x00000518,0x00002231,0xFFFFF358,0x000003C5,0x00002231,0xFFFFF358,0x000003C5},
--	{"0000001000010011111100001111111010011001001100100001000100100100",0x00003131,0xFFFFEA45,0x00000513,0x00001973,0xFFFFF85E,0x00000301,0x00001973,0xFFFFF85E,0x00000301},
--	{"0000001000010011111100001111111010011001000111000010100110100100",0x00003571,0xFFFFE8AC,0x00000539,0x00002049,0xFFFFF49C,0x0000038D,0x00002049,0xFFFFF49C,0x0000038D},
--	{"0000001000010011111100001111111010011001001011100011100001100100",0x0000309E,0xFFFFEB1D,0x000004E8,0x000019ED,0xFFFFF86E,0x000002F8,0x000019ED,0xFFFFF86E,0x000002F8},
--	{"0000001000010011111100001111111010011001001100000010100110000100",0x00003091,0xFFFFEB9B,0x000004CC,0x00001D2C,0xFFFFF6A2,0x0000033D,0x00001D2C,0xFFFFF6A2,0x0000033D},
--	{"0000001000010011111100001111111010011001001100000000100011100100",0x00003069,0xFFFFEAFD,0x000004F8,0x00001E82,0xFFFFF51C,0x0000038D,0x00001E82,0xFFFFF51C,0x0000038D},
--	{"0000001000010011111100001111111010011001001000100001000010100100",0x00003459,0xFFFFE7F2,0x00000572,0x00001DA7,0xFFFFF552,0x0000037F,0x00001DA7,0xFFFFF552,0x0000037F},
--	{"0000001000010011111100001111111010011001001100100001000100000100",0x0000304B,0xFFFFEAFB,0x000004F4,0x0000191E,0xFFFFF8BD,0x000002EE,0x0000191E,0xFFFFF8BD,0x000002EE},
--	{"0000001000010011111100001111111010011001001100000010000011000100",0x0000346E,0xFFFFEA07,0x000004FD,0x00002767,0xFFFFF058,0x00000440,0x00002767,0xFFFFF058,0x00000440},
--	{"0000001000010011111100001111111010011001001011100011000010000100",0x000030B5,0xFFFFEBC1,0x000004C1,0x00001B3C,0xFFFFF818,0x000002FD,0x00001B3C,0xFFFFF818,0x000002FD},
--	{"0000001000010011111100001111111010011001001100000000100100000100",0x0000321F,0xFFFFE9EA,0x00000524,0x00002380,0xFFFFF1C2,0x0000041A,0x00002380,0xFFFFF1C2,0x0000041A},
--	{"0000001000010011111100001111111010011001001011100011000001000100",0x000030DF,0xFFFFEB37,0x000004E2,0x00001E3C,0xFFFFF5BB,0x00000369,0x00001E3C,0xFFFFF5BB,0x00000369},
--	{"0000001000010011111100001111111010011001001010000100100010100100",0x000027E0,0xFFFFF0E2,0x00000416,0x00001A6A,0xFFFFF820,0x00000321,0x00001A6A,0xFFFFF820,0x00000321},
--	{"0000001000010011111100001111111010011001000110100001000010000100",0x00002FA1,0xFFFFEB63,0x000004E7,0x0000196B,0xFFFFF880,0x000002FB,0x0000196B,0xFFFFF880,0x000002FB},
--	{"0000001000010011111100001111111010011001000111000001000010000100",0x0000310C,0xFFFFEAAF,0x000004FC,0x000019EF,0xFFFFF850,0x000002FD,0x000019EF,0xFFFFF850,0x000002FD},
--	{"0000001000010011111100001111111010011001001100100011100100000100",0x0000334A,0xFFFFEA07,0x0000050B,0x00002380,0xFFFFF26F,0x000003F0,0x00002380,0xFFFFF26F,0x000003F0},
--	{"0000001000010011111100001111111010011001001100000010100101000100",0x00002FF9,0xFFFFECDC,0x00000492,0x00002297,0xFFFFF394,0x000003BF,0x00002297,0xFFFFF394,0x000003BF},
--	{"0000001000010011111100001111111010011001001011000010000101100100",0x0000354B,0xFFFFE894,0x00000546,0x000024C4,0xFFFFF16C,0x0000041B,0x000024C4,0xFFFFF16C,0x0000041B},
--	{"0000001000010011111100001111111010011001001000100000100100100100",0x00003245,0xFFFFE92F,0x00000544,0x00001829,0xFFFFF8F1,0x000002EA,0x00001829,0xFFFFF8F1,0x000002EA},
--	{"0000001000010011111100001111111010011001001011100100100010000100",0x0000302F,0xFFFFEB51,0x000004E3,0x0000199F,0xFFFFF894,0x000002F4,0x0000199F,0xFFFFF894,0x000002F4},
--	{"0000001000010011111100001111111010011001001011100001100011000100",0x00002F54,0xFFFFEC86,0x000004A6,0x00001A6F,0xFFFFF891,0x000002EC,0x00001A6F,0xFFFFF891,0x000002EC},
--	{"0000001000010011111100001111111010011001001010000100000101100100",0x00002908,0xFFFFF0D8,0x0000040A,0x00001C9B,0xFFFFF729,0x00000342,0x00001C9B,0xFFFFF729,0x00000342},
--	{"0000001000010011111100001111111010011001001100000010100101100100",0x000031D9,0xFFFFEB40,0x000004D7,0x000023F5,0xFFFFF259,0x000003F4,0x000023F5,0xFFFFF259,0x000003F4},
--	{"0000001000010011111100001111111010011001001100000100100011100100",0x000034C8,0xFFFFE8C6,0x0000053F,0x00002313,0xFFFFF280,0x000003EC,0x00002313,0xFFFFF280,0x000003EC},
--	{"0000001000010011111100001111111010011001001100000101000011000100",0x000037D1,0xFFFFE6A1,0x0000059C,0x00002C6A,0xFFFFEBFF,0x00000504,0x00002C6A,0xFFFFEBFF,0x00000504},
--	{"0000001000010011111100001111111010011001001100100001100101100100",0x000030E9,0xFFFFEA6B,0x0000050F,0x00001A2D,0xFFFFF7DF,0x00000316,0x00001A2D,0xFFFFF7DF,0x00000316},
--	{"0000001000010011111100001111111010011001001100000010000010000100",0x0000323D,0xFFFFEA95,0x000004F4,0x00001ED2,0xFFFFF584,0x0000036C,0x00001ED2,0xFFFFF584,0x0000036C},
--	{"0000001000010011111100001111111010011001001011000011000000100100",0x000033D6,0xFFFFE9DB,0x00000510,0x000027A7,0xFFFFEFC7,0x0000045E,0x000027A7,0xFFFFEFC7,0x0000045E},
--	{"0000001000010011111100001111111010011001000111000011000101100100",0x00003444,0xFFFFE98A,0x00000517,0x000020FD,0xFFFFF43F,0x0000039D,0x000020FD,0xFFFFF43F,0x0000039D},
--	{"0000001000010011111100001111111010011001001010000000100011100100",0x00002987,0xFFFFEFA1,0x0000044B,0x00001B06,0xFFFFF788,0x0000033C,0x00001B06,0xFFFFF788,0x0000033C},
--	{"0000001000010011111100001111111010011001001011000010100011100100",0x0000311D,0xFFFFED20,0x00000474,0x000025DA,0xFFFFF223,0x000003F0,0x000025DA,0xFFFFF223,0x000003F0},
--	{"0000001000010011111100001111111010011001001011000001000100100100",0x000032A2,0xFFFFEA0A,0x0000050D,0x00001D48,0xFFFFF659,0x0000034A,0x00001D48,0xFFFFF659,0x0000034A},
--	{"0000001000010011111100001111111010011001001000100000100011100100",0x00003110,0xFFFFE9EA,0x00000529,0x00001786,0xFFFFF958,0x000002DB,0x00001786,0xFFFFF958,0x000002DB},
--	{"0000001000010011111100001111111010011001001010000010000110100100",0x000027F2,0xFFFFF174,0x000003F7,0x00001C7A,0xFFFFF72A,0x00000348,0x00001C7A,0xFFFFF72A,0x00000348},
--	{"0000001000010011111100001111111010011001000111000001000011100100",0x000031DB,0xFFFFEA7D,0x000004FB,0x000019C4,0xFFFFF8B1,0x000002E6,0x000019C4,0xFFFFF8B1,0x000002E6},
--	{"0000001000010011111100001111111010011001001011000001000100000100",0x00003158,0xFFFFEAAC,0x000004FA,0x00001BC1,0xFFFFF737,0x0000032B,0x00001BC1,0xFFFFF737,0x0000032B},
--	{"0000001000010011111100001111111010011001001100000001000011000100",0x00002F36,0xFFFFEBF9,0x000004CA,0x00001A2A,0xFFFFF83F,0x00000303,0x00001A2A,0xFFFFF83F,0x00000303},
--	{"0000001000010011111100001111111010011001001100100011100010100100",0x000032B4,0xFFFFEA72,0x000004FA,0x000021FF,0xFFFFF378,0x000003C5,0x000021FF,0xFFFFF378,0x000003C5},
--	{"0000001000010011111100001111111010011001001100000011000101100100",0x00003262,0xFFFFEAFA,0x000004DF,0x00002441,0xFFFFF237,0x000003F6,0x00002441,0xFFFFF237,0x000003F6},
--	{"0000001000010011111100001111111010011001001100000011100100100100",0x0000336A,0xFFFFEAFB,0x000004D1,0x00002746,0xFFFFF0B8,0x0000042B,0x00002746,0xFFFFF0B8,0x0000042B},
--	{"0000001000010011111100001111111010011001000110100100000010000100",0x000032E5,0xFFFFE923,0x00000541,0x00001DF0,0xFFFFF552,0x00000380,0x00001DF0,0xFFFFF552,0x00000380},
--	{"0000001000010011111100001111111010011001001100000100000001100100",0x000035D1,0xFFFFE80B,0x0000055F,0x00002780,0xFFFFEF74,0x0000046F,0x00002780,0xFFFFEF74,0x0000046F},
--	{"0000001000010011111100001111111010011001001100000010100010100100",0x000033EC,0xFFFFEA48,0x000004F4,0x0000269F,0xFFFFF0D8,0x0000042A,0x0000269F,0xFFFFF0D8,0x0000042A},
--	{"0000001000010011111100001111111010011001001100100011100010000100",0x000030C4,0xFFFFEB39,0x000004E2,0x00001B44,0xFFFFF7AA,0x00000318,0x00001B44,0xFFFFF7AA,0x00000318},
--	{"0000001000010011111100001111111010011001001010000001000101000100",0x00002926,0xFFFFF0AF,0x0000040E,0x0000194E,0xFFFFF959,0x000002E2,0x0000194E,0xFFFFF959,0x000002E2},
--	{"0000001000010011111100001111111010011001001011000001000011000100",0x00003141,0xFFFFEAAF,0x000004F6,0x00001864,0xFFFFF97C,0x000002C6,0x00001864,0xFFFFF97C,0x000002C6},
--	{"0000001000010011111100001111111010011001001100000001000001100100",0x000030B2,0xFFFFEB7C,0x000004DB,0x000022CE,0xFFFFF2B5,0x000003F0,0x000022CE,0xFFFFF2B5,0x000003F0},
--	{"0000001000010011111100001111111010011001001100000001100101000100",0x0000318C,0xFFFFEAC7,0x000004F6,0x00002113,0xFFFFF3CA,0x000003BD,0x00002113,0xFFFFF3CA,0x000003BD},
--	{"0000001000010011111100001111111010011001001011100001000100000100",0x00002FD2,0xFFFFEB8F,0x000004D9,0x00001996,0xFFFFF89F,0x000002F1,0x00001996,0xFFFFF89F,0x000002F1},
--	{"0000001000010011111100001111111010011001000110100010100010100100",0x0000310D,0xFFFFEB25,0x000004E7,0x00001F67,0xFFFFF4EF,0x0000038E,0x00001F67,0xFFFFF4EF,0x0000038E},
--	{"0000001000010011111100001111111010011001001010100100100101100100",0x00002BBC,0xFFFFEE68,0x00000477,0x00002050,0xFFFFF41D,0x000003C8,0x00002050,0xFFFFF41D,0x000003C8},
--	{"0000001000010011111100001111111010011001001100000010000100000100",0x00003096,0xFFFFECED,0x00000486,0x000024C9,0xFFFFF278,0x000003E7,0x000024C9,0xFFFFF278,0x000003E7},
--	{"0000001000010011111100001111111010011001001011000001000010100100",0x00003401,0xFFFFE8F1,0x0000053C,0x00001E75,0xFFFFF55C,0x00000376,0x00001E75,0xFFFFF55C,0x00000376},
--	{"0000001000010011111100001111111010011001001100000010100001000100",0x0000319E,0xFFFFEAB1,0x000004F8,0x00001EA3,0xFFFFF567,0x00000378,0x00001EA3,0xFFFFF567,0x00000378},
--	{"0000001000010011111100001111111010011001001100100010100101100100",0x000030FD,0xFFFFEB4C,0x000004DB,0x00001CA6,0xFFFFF6E8,0x00000335,0x00001CA6,0xFFFFF6E8,0x00000335},
--	{"0000001000010011111100001111111010011001001011100100000010100100",0x000030D6,0xFFFFEB1A,0x000004E4,0x00001A0D,0xFFFFF87D,0x000002EF,0x00001A0D,0xFFFFF87D,0x000002EF},
--	{"0000001000010011111100001111111010011001001011000010000100100100",0x0000324B,0xFFFFEB17,0x000004D9,0x00002225,0xFFFFF3A8,0x000003BA,0x00002225,0xFFFFF3A8,0x000003BA},
--	{"0000001000010011111100001111111010011001001010000100000010000100",0x00002A00,0xFFFFF02E,0x00000424,0x00001E21,0xFFFFF61D,0x0000036C,0x00001E21,0xFFFFF61D,0x0000036C},
--	{"0000001000010011111100001111111010011001001010100100100010100100",0x000029CF,0xFFFFEF53,0x00000457,0x00001B11,0xFFFFF772,0x0000033D,0x00001B11,0xFFFFF772,0x0000033D},
--	{"0000001000010011111100001111111010011001000110100011000010100100",0x000032A1,0xFFFFEA63,0x000004FB,0x00001F83,0xFFFFF516,0x0000037E,0x00001F83,0xFFFFF516,0x0000037E},
--	{"0000001000010011111100001111111010011001001011100010000011000100",0x0000305C,0xFFFFEC14,0x000004B5,0x00001D0B,0xFFFFF6ED,0x00000332,0x00001D0B,0xFFFFF6ED,0x00000332},
--	{"0000001000010011111100001111111010011001001011000001000001100100",0x00003467,0xFFFFE8D5,0x00000543,0x0000243F,0xFFFFF190,0x00000418,0x0000243F,0xFFFFF190,0x00000418},
--	{"0000001000010011111100001111111010011001001010100010000001100100",0x00002796,0xFFFFF133,0x00000409,0x00001903,0xFFFFF91C,0x000002FC,0x00001903,0xFFFFF91C,0x000002FC},
--	{"0000001000010011111100001111111010011001001100000010000101100100",0x000031F6,0xFFFFEAB7,0x000004F5,0x000022B9,0xFFFFF2D0,0x000003E6,0x000022B9,0xFFFFF2D0,0x000003E6},
--	{"0000001000010011111100001111111010011001001011100101000100000100",0x00003196,0xFFFFEA76,0x00000503,0x00001CC5,0xFFFFF67D,0x0000034A,0x00001CC5,0xFFFFF67D,0x0000034A},
--	{"0000001000010011111100001111111010011001001100100001000101000100",0x00002F9E,0xFFFFEAD9,0x00000505,0x000017C1,0xFFFFF93D,0x000002DF,0x000017C1,0xFFFFF93D,0x000002DF},
--	{"0000001000010011111100001111111010011001001011100010000100100100",0x00002FBC,0xFFFFEC75,0x000004A8,0x00001D6D,0xFFFFF6AC,0x0000033D,0x00001D6D,0xFFFFF6AC,0x0000033D},
--	{"0000001000010011111100001111111010011001001011000011100010100100",0x00003541,0xFFFFE921,0x00000524,0x00002662,0xFFFFF0CB,0x0000042B,0x00002662,0xFFFFF0CB,0x0000042B},
--	{"0000001000010011111100001111111010011001001010100010000110100100",0x00002953,0xFFFFEF76,0x00000459,0x00001C05,0xFFFFF6A0,0x00000368,0x00001C05,0xFFFFF6A0,0x00000368},
--	{"0000001000010011111100001111111010011001001011000100100100100100",0x000034BC,0xFFFFE8DD,0x00000536,0x0000210E,0xFFFFF3F4,0x000003A8,0x0000210E,0xFFFFF3F4,0x000003A8},
--	{"0000001000010011111100001111111010011001001011000010100110100100",0x000034BE,0xFFFFE916,0x0000052F,0x000024A1,0xFFFFF1A6,0x00000410,0x000024A1,0xFFFFF1A6,0x00000410},
--	{"0000001000010011111100001111111010011001001100000100100101100100",0x000037B5,0xFFFFE7A9,0x0000055B,0x000028A1,0xFFFFEF51,0x00000467,0x000028A1,0xFFFFEF51,0x00000467},
--	{"0000001000010011111100001111111010011001001100000001000100000100",0x00002FC5,0xFFFFEBBE,0x000004D1,0x00001BA5,0xFFFFF757,0x00000328,0x00001BA5,0xFFFFF757,0x00000328},
--	{"0000001000010011111100001111111010011001001100000100000010100100",0x000033CB,0xFFFFE944,0x0000052B,0x00001FBE,0xFFFFF4B1,0x0000038C,0x00001FBE,0xFFFFF4B1,0x0000038C},
--	{"0000001000010011111100001111111010011001001100000001100001000100",0x000030AE,0xFFFFEBA0,0x000004D3,0x00002268,0xFFFFF316,0x000003DD,0x00002268,0xFFFFF316,0x000003DD},
--	{"0000001000010011111100001111111010011001001011000010000010100100",0x00002F90,0xFFFFEC5A,0x000004B0,0x00001C3A,0xFFFFF752,0x00000323,0x00001C3A,0xFFFFF752,0x00000323},
--	{"0000001000010011111100001111111010011001001011100011100011100100",0x00003113,0xFFFFEB91,0x000004C8,0x00001E3C,0xFFFFF623,0x0000034E,0x00001E3C,0xFFFFF623,0x0000034E},
--	{"0000001000010011111100001111111010011001001100100011100110000100",0x0000330B,0xFFFFE94B,0x00000539,0x000020E7,0xFFFFF37E,0x000003CD,0x000020E7,0xFFFFF37E,0x000003CD},
--	{"0000001000010011111100001111111010011001001011100010100001100100",0x000031D1,0xFFFFEACB,0x000004ED,0x00001E82,0xFFFFF5B2,0x00000365,0x00001E82,0xFFFFF5B2,0x00000365},
--	{"0000001000010011111100001111111010011001001010100011100110000100",0x00002CD5,0xFFFFEDC1,0x0000048D,0x000020F8,0xFFFFF3C1,0x000003D1,0x000020F8,0xFFFFF3C1,0x000003D1},
--	{ NULL            ,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000,0x000}
-+static const struct phm_fuses_default vega10_fuses_default[] = {
-+	{ 0x0213EA94DE0E4964, 0x00003C96, 0xFFFFE226, 0x00000656, 0x00002203, 0xFFFFF201, 0x000003FF, 0x00002203, 0xFFFFF201, 0x000003FF },
-+	{ 0x0213EA94DE0A1884, 0x00003CC5, 0xFFFFE23A, 0x0000064E, 0x00002258, 0xFFFFF1F7, 0x000003FC, 0x00002258, 0xFFFFF1F7, 0x000003FC },
-+	{ 0x0213EA94DE0E31A4, 0x00003CAF, 0xFFFFE36E, 0x00000602, 0x00001E98, 0xFFFFF569, 0x00000357, 0x00001E98, 0xFFFFF569, 0x00000357 },
-+	{ 0x0213EA94DE2C1144, 0x0000391A, 0xFFFFE548, 0x000005C9, 0x00001B98, 0xFFFFF707, 0x00000324, 0x00001B98, 0xFFFFF707, 0x00000324 },
-+	{ 0x0213EA94DE2C18C4, 0x00003821, 0xFFFFE674, 0x00000597, 0x00002196, 0xFFFFF361, 0x000003C0, 0x00002196, 0xFFFFF361, 0x000003C0 },
-+	{ 0x0213EA94DE263884, 0x000044A2, 0xFFFFDCB7, 0x00000738, 0x0000325C, 0xFFFFE6A7, 0x000005E6, 0x0000325C, 0xFFFFE6A7, 0x000005E6 },
-+	{ 0x0213EA94DE082924, 0x00004057, 0xFFFFE1CF, 0x0000063C, 0x00002E2E, 0xFFFFEB62, 0x000004FD, 0x00002E2E, 0xFFFFEB62, 0x000004FD },
-+	{ 0x0213EA94DE284924, 0x00003FD0, 0xFFFFDF0F, 0x000006E5, 0x0000267C, 0xFFFFEE2D, 0x000004AB, 0x0000267C, 0xFFFFEE2D, 0x000004AB },
-+	{ 0x0213EA94DE280904, 0x00003F13, 0xFFFFE010, 0x000006AD, 0x000020E7, 0xFFFFF266, 0x000003EC, 0x000020E7, 0xFFFFF266, 0x000003EC },
-+	{ 0x0213EA94DE082044, 0x00004088, 0xFFFFDFAB, 0x000006B6, 0x0000252B, 0xFFFFEFDB, 0x00000458, 0x0000252B, 0xFFFFEFDB, 0x00000458 },
-+	{ 0x0213EA94DE283884, 0x00003EF6, 0xFFFFE017, 0x000006AA, 0x00001F67, 0xFFFFF369, 0x000003BE, 0x00001F67, 0xFFFFF369, 0x000003BE },
-+	{ 0x0213EA94DE2C2184, 0x00003CDD, 0xFFFFE2A7, 0x0000063C, 0x000026C6, 0xFFFFEF38, 0x00000478, 0x000026C6, 0xFFFFEF38, 0x00000478 },
-+	{ 0x0213EA94DE105124, 0x00003FA8, 0xFFFFDF02, 0x000006F0, 0x000027FE, 0xFFFFECF6, 0x000004EA, 0x000027FE, 0xFFFFECF6, 0x000004EA },
-+	{ 0x0213EA94DE2638C4, 0x00004670, 0xFFFFDC40, 0x00000742, 0x00003A7A, 0xFFFFE1A7, 0x000006B6, 0x00003A7A, 0xFFFFE1A7, 0x000006B6 },
-+	{ 0x0213EA94DE2C3024, 0x00003CDC, 0xFFFFE18C, 0x00000683, 0x00002A69, 0xFFFFEBE7, 0x00000515, 0x00002A69, 0xFFFFEBE7, 0x00000515 },
-+	{ 0x0213EA94DE0E38C4, 0x00003CEC, 0xFFFFE38E, 0x00000601, 0x00002752, 0xFFFFEFA7, 0x00000453, 0x00002752, 0xFFFFEFA7, 0x00000453 },
-+	{ 0x0213EA94DE2C1124, 0x000037D0, 0xFFFFE634, 0x000005A7, 0x00001CD2, 0xFFFFF644, 0x00000348, 0x00001CD2, 0xFFFFF644, 0x00000348 },
-+	{ 0x0213EA94DE283964, 0x00003DF5, 0xFFFFE0A5, 0x00000698, 0x00001FD5, 0xFFFFF30E, 0x000003D1, 0x00001FD5, 0xFFFFF30E, 0x000003D1 },
-+	{ 0x0213EA94DE0828C4, 0x00004201, 0xFFFFE03E, 0x00000688, 0x00003206, 0xFFFFE852, 0x0000058A, 0x00003206, 0xFFFFE852, 0x0000058A },
-+	{ 0x0213EA94DE2C1864, 0x00003BED, 0xFFFFE2F5, 0x00000638, 0x0000270D, 0xFFFFEED0, 0x0000048E, 0x0000270D, 0xFFFFEED0, 0x0000048E },
-+	{ 0x0213EA94DE0A1904, 0x00003E82, 0xFFFFE1BE, 0x00000654, 0x000025FB, 0xFFFFEFFA, 0x00000448, 0x000025FB, 0xFFFFEFFA, 0x00000448 },
-+	{ 0x0213EA94DE2C40C4, 0x00003962, 0xFFFFE4B9, 0x000005EF, 0x00002385, 0xFFFFF156, 0x00000423, 0x00002385, 0xFFFFF156, 0x00000423 },
-+	{ 0x0213EA94DE2C0944, 0x00003D88, 0xFFFFE21A, 0x00000655, 0x0000295A, 0xFFFFED68, 0x000004C4, 0x0000295A, 0xFFFFED68, 0x000004C4 },
-+	{ 0x0213EA94DE2C1104, 0x00003AA4, 0xFFFFE4A3, 0x000005E0, 0x000022EF, 0xFFFFF250, 0x000003EB, 0x000022EF, 0xFFFFF250, 0x000003EB },
-+	{ 0x0213EA94DE0E29A4, 0x00003D97, 0xFFFFE30D, 0x0000060D, 0x0000205D, 0xFFFFF45D, 0x00000380, 0x0000205D, 0xFFFFF45D, 0x00000380 },
-+	{ 0x0213EA94DE2C40A4, 0x000039B6, 0xFFFFE446, 0x00000605, 0x00002325, 0xFFFFF16C, 0x0000041F, 0x00002325, 0xFFFFF16C, 0x0000041F },
-+	{ 0x0213EA94DE263904, 0x0000457E, 0xFFFFDCF6, 0x00000722, 0x00003972, 0xFFFFE27B, 0x0000068E, 0x00003972, 0xFFFFE27B, 0x0000068E },
-+	{ 0x0213EA94DE0A1924, 0x00003FB8, 0xFFFFE101, 0x00000670, 0x00002787, 0xFFFFEEF5, 0x00000471, 0x00002787, 0xFFFFEEF5, 0x00000471 },
-+	{ 0x0213EA94DE0E38A4, 0x00003BB2, 0xFFFFE430, 0x000005EA, 0x000024A5, 0xFFFFF162, 0x00000409, 0x000024A5, 0xFFFFF162, 0x00000409 },
-+	{ 0x0213EA94DE082144, 0x00003EC5, 0xFFFFE1BD, 0x0000064F, 0x000022F0, 0xFFFFF227, 0x000003E8, 0x000022F0, 0xFFFFF227, 0x000003E8 },
-+	{ 0x0213EA94DE2C3164, 0x000038A7, 0xFFFFE59F, 0x000005C1, 0x000021CC, 0xFFFFF2DF, 0x000003D9, 0x000021CC, 0xFFFFF2DF, 0x000003D9 },
-+	{ 0x0213EA94DE324184, 0x00002995, 0xFFFFEF7A, 0x0000044C, 0x00001552, 0xFFFFFB5D, 0x00000292, 0x00001552, 0xFFFFFB5D, 0x00000292 },
-+	{ 0x0213EA94DE2C4064, 0x00003B26, 0xFFFFE2D3, 0x00000649, 0x000023B4, 0xFFFFF09B, 0x00000449, 0x000023B4, 0xFFFFF09B, 0x00000449 },
-+	{ 0x0213EA94DE081124, 0x000040D2, 0xFFFFE00A, 0x00000696, 0x000022DA, 0xFFFFF1E9, 0x000003F2, 0x000022DA, 0xFFFFF1E9, 0x000003F2 },
-+	{ 0x0213EA94DE2C3924, 0x00003C98, 0xFFFFE365, 0x00000618, 0x00002D5D, 0xFFFFEB3A, 0x0000051D, 0x00002D5D, 0xFFFFEB3A, 0x0000051D },
-+	{ 0x0213EA94DE2C10A4, 0x00003BBD, 0xFFFFE37E, 0x00000617, 0x0000252E, 0xFFFFF06E, 0x00000441, 0x0000252E, 0xFFFFF06E, 0x00000441 },
-+	{ 0x0213EA94DE262924, 0x00004363, 0xFFFFDF7A, 0x000006A0, 0x000031F5, 0xFFFFE880, 0x0000057B, 0x000031F5, 0xFFFFE880, 0x0000057B },
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-+	{ 0x0213F0FE99302844, 0x0000319E, 0xFFFFEAB1, 0x000004F8, 0x00001EA3, 0xFFFFF567, 0x00000378, 0x00001EA3, 0xFFFFF567, 0x00000378 },
-+	{ 0x0213F0FE99322964, 0x000030FD, 0xFFFFEB4C, 0x000004DB, 0x00001CA6, 0xFFFFF6E8, 0x00000335, 0x00001CA6, 0xFFFFF6E8, 0x00000335 },
-+	{ 0x0213F0FE992E40A4, 0x000030D6, 0xFFFFEB1A, 0x000004E4, 0x00001A0D, 0xFFFFF87D, 0x000002EF, 0x00001A0D, 0xFFFFF87D, 0x000002EF },
-+	{ 0x0213F0FE992C2124, 0x0000324B, 0xFFFFEB17, 0x000004D9, 0x00002225, 0xFFFFF3A8, 0x000003BA, 0x00002225, 0xFFFFF3A8, 0x000003BA },
-+	{ 0x0213F0FE99284084, 0x00002A00, 0xFFFFF02E, 0x00000424, 0x00001E21, 0xFFFFF61D, 0x0000036C, 0x00001E21, 0xFFFFF61D, 0x0000036C },
-+	{ 0x0213F0FE992A48A4, 0x000029CF, 0xFFFFEF53, 0x00000457, 0x00001B11, 0xFFFFF772, 0x0000033D, 0x00001B11, 0xFFFFF772, 0x0000033D },
-+	{ 0x0213F0FE991A30A4, 0x000032A1, 0xFFFFEA63, 0x000004FB, 0x00001F83, 0xFFFFF516, 0x0000037E, 0x00001F83, 0xFFFFF516, 0x0000037E },
-+	{ 0x0213F0FE992E20C4, 0x0000305C, 0xFFFFEC14, 0x000004B5, 0x00001D0B, 0xFFFFF6ED, 0x00000332, 0x00001D0B, 0xFFFFF6ED, 0x00000332 },
-+	{ 0x0213F0FE992C1064, 0x00003467, 0xFFFFE8D5, 0x00000543, 0x0000243F, 0xFFFFF190, 0x00000418, 0x0000243F, 0xFFFFF190, 0x00000418 },
-+	{ 0x0213F0FE992A2064, 0x00002796, 0xFFFFF133, 0x00000409, 0x00001903, 0xFFFFF91C, 0x000002FC, 0x00001903, 0xFFFFF91C, 0x000002FC },
-+	{ 0x0213F0FE99302164, 0x000031F6, 0xFFFFEAB7, 0x000004F5, 0x000022B9, 0xFFFFF2D0, 0x000003E6, 0x000022B9, 0xFFFFF2D0, 0x000003E6 },
-+	{ 0x0213F0FE992E5104, 0x00003196, 0xFFFFEA76, 0x00000503, 0x00001CC5, 0xFFFFF67D, 0x0000034A, 0x00001CC5, 0xFFFFF67D, 0x0000034A },
-+	{ 0x0213F0FE99321144, 0x00002F9E, 0xFFFFEAD9, 0x00000505, 0x000017C1, 0xFFFFF93D, 0x000002DF, 0x000017C1, 0xFFFFF93D, 0x000002DF },
-+	{ 0x0213F0FE992E2124, 0x00002FBC, 0xFFFFEC75, 0x000004A8, 0x00001D6D, 0xFFFFF6AC, 0x0000033D, 0x00001D6D, 0xFFFFF6AC, 0x0000033D },
-+	{ 0x0213F0FE992C38A4, 0x00003541, 0xFFFFE921, 0x00000524, 0x00002662, 0xFFFFF0CB, 0x0000042B, 0x00002662, 0xFFFFF0CB, 0x0000042B },
-+	{ 0x0213F0FE992A21A4, 0x00002953, 0xFFFFEF76, 0x00000459, 0x00001C05, 0xFFFFF6A0, 0x00000368, 0x00001C05, 0xFFFFF6A0, 0x00000368 },
-+	{ 0x0213F0FE992C4924, 0x000034BC, 0xFFFFE8DD, 0x00000536, 0x0000210E, 0xFFFFF3F4, 0x000003A8, 0x0000210E, 0xFFFFF3F4, 0x000003A8 },
-+	{ 0x0213F0FE992C29A4, 0x000034BE, 0xFFFFE916, 0x0000052F, 0x000024A1, 0xFFFFF1A6, 0x00000410, 0x000024A1, 0xFFFFF1A6, 0x00000410 },
-+	{ 0x0213F0FE99304964, 0x000037B5, 0xFFFFE7A9, 0x0000055B, 0x000028A1, 0xFFFFEF51, 0x00000467, 0x000028A1, 0xFFFFEF51, 0x00000467 },
-+	{ 0x0213F0FE99301104, 0x00002FC5, 0xFFFFEBBE, 0x000004D1, 0x00001BA5, 0xFFFFF757, 0x00000328, 0x00001BA5, 0xFFFFF757, 0x00000328 },
-+	{ 0x0213F0FE993040A4, 0x000033CB, 0xFFFFE944, 0x0000052B, 0x00001FBE, 0xFFFFF4B1, 0x0000038C, 0x00001FBE, 0xFFFFF4B1, 0x0000038C },
-+	{ 0x0213F0FE99301844, 0x000030AE, 0xFFFFEBA0, 0x000004D3, 0x00002268, 0xFFFFF316, 0x000003DD, 0x00002268, 0xFFFFF316, 0x000003DD },
-+	{ 0x0213F0FE992C20A4, 0x00002F90, 0xFFFFEC5A, 0x000004B0, 0x00001C3A, 0xFFFFF752, 0x00000323, 0x00001C3A, 0xFFFFF752, 0x00000323 },
-+	{ 0x0213F0FE992E38E4, 0x00003113, 0xFFFFEB91, 0x000004C8, 0x00001E3C, 0xFFFFF623, 0x0000034E, 0x00001E3C, 0xFFFFF623, 0x0000034E },
-+	{ 0x0213F0FE99323984, 0x0000330B, 0xFFFFE94B, 0x00000539, 0x000020E7, 0xFFFFF37E, 0x000003CD, 0x000020E7, 0xFFFFF37E, 0x000003CD },
-+	{ 0x0213F0FE992E2864, 0x000031D1, 0xFFFFEACB, 0x000004ED, 0x00001E82, 0xFFFFF5B2, 0x00000365, 0x00001E82, 0xFFFFF5B2, 0x00000365 },
-+	{ 0x0213F0FE992A3984, 0x00002CD5, 0xFFFFEDC1, 0x0000048D, 0x000020F8, 0xFFFFF3C1, 0x000003D1, 0x000020F8, 0xFFFFF3C1, 0x000003D1 },
-+	{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
- };
- 
- int pp_override_get_default_fuse_value(uint64_t key,
--			struct phm_fuses_default list[],
- 			struct phm_fuses_default *result)
- {
-+	const struct phm_fuses_default *list = vega10_fuses_default;
- 	uint32_t i;
--	uint64_t temp_serial_numer;
--	uint32_t bit;
--	const char *temp;
- 
--	for (i = 0; list[i].key != NULL; i++) {
--		temp = list[i].key;
--		temp_serial_numer = 0;
--		do {
--			bit = *temp=='1'? 1 : 0;
--			temp_serial_numer = (temp_serial_numer <<1 ) | bit;
--			temp++;
--		} while (*temp);
--
--		if (key == temp_serial_numer) {
-+	for (i = 0; list[i].key != 0; i++) {
-+		if (key == list[i].key) {
- 			result->key =  list[i].key;
- 			result->VFT2_m1 = list[i].VFT2_m1;
- 			result->VFT2_m2 = list[i].VFT2_m2;
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h	2017-12-14 06:39:58.471903606 +0100
-@@ -28,7 +28,7 @@
- #include <linux/kernel.h>
- 
- struct phm_fuses_default {
--	const char *key;
-+	uint64_t key;
- 	uint32_t VFT2_m1;
- 	uint32_t VFT2_m2;
- 	uint32_t VFT2_b;
-@@ -40,9 +40,7 @@ struct phm_fuses_default {
- 	uint32_t VFT0_b;
- };
- 
--extern struct phm_fuses_default vega10_fuses_default[];
- extern int pp_override_get_default_fuse_value(uint64_t key,
--			struct phm_fuses_default list[],
- 			struct phm_fuses_default *result);
- 
- #endif
-\ No newline at end of file
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c.0130~	2017-12-14 06:39:58.471903606 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c	2017-12-14 06:39:58.471903606 +0100
-@@ -0,0 +1,250 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include "pp_psm.h"
-+
-+int psm_init_power_state_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	unsigned int i;
-+	unsigned int table_entries;
-+	struct pp_power_state *state;
-+	int size;
-+
-+	if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
-+		return -EINVAL;
-+
-+	if (hwmgr->hwmgr_func->get_power_state_size == NULL)
-+		return -EINVAL;
-+
-+	hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
-+
-+	hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
-+					  sizeof(struct pp_power_state);
-+
-+	hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL);
-+	if (hwmgr->ps == NULL)
-+		return -ENOMEM;
-+
-+	hwmgr->request_ps = kzalloc(size, GFP_KERNEL);
-+	if (hwmgr->request_ps == NULL) {
-+		kfree(hwmgr->ps);
-+		hwmgr->ps = NULL;
-+		return -ENOMEM;
-+	}
-+
-+	hwmgr->current_ps = kzalloc(size, GFP_KERNEL);
-+	if (hwmgr->current_ps == NULL) {
-+		kfree(hwmgr->request_ps);
-+		kfree(hwmgr->ps);
-+		hwmgr->request_ps = NULL;
-+		hwmgr->ps = NULL;
-+		return -ENOMEM;
-+	}
-+
-+	state = hwmgr->ps;
-+
-+	for (i = 0; i < table_entries; i++) {
-+		result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state);
-+
-+		if (state->classification.flags & PP_StateClassificationFlag_Boot) {
-+			hwmgr->boot_ps = state;
-+			memcpy(hwmgr->current_ps, state, size);
-+			memcpy(hwmgr->request_ps, state, size);
-+		}
-+
-+		state->id = i + 1; /* assigned unique num for every power state id */
-+
-+		if (state->classification.flags & PP_StateClassificationFlag_Uvd)
-+			hwmgr->uvd_ps = state;
-+		state = (struct pp_power_state *)((unsigned long)state + size);
-+	}
-+
-+	return 0;
-+}
-+
-+int psm_fini_power_state_table(struct pp_hwmgr *hwmgr)
-+{
-+	if (hwmgr == NULL)
-+		return -EINVAL;
-+
-+	kfree(hwmgr->current_ps);
-+	kfree(hwmgr->request_ps);
-+	kfree(hwmgr->ps);
-+	hwmgr->request_ps = NULL;
-+	hwmgr->ps = NULL;
-+	hwmgr->current_ps = NULL;
-+	return 0;
-+}
-+
-+static int psm_get_ui_state(struct pp_hwmgr *hwmgr,
-+				enum PP_StateUILabel ui_label,
-+				unsigned long *state_id)
-+{
-+	struct pp_power_state *state;
-+	int table_entries;
-+	int i;
-+
-+	table_entries = hwmgr->num_ps;
-+	state = hwmgr->ps;
-+
-+	for (i = 0; i < table_entries; i++) {
-+		if (state->classification.ui_label & ui_label) {
-+			*state_id = state->id;
-+			return 0;
-+		}
-+		state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
-+	}
-+	return -EINVAL;
-+}
-+
-+static int psm_get_state_by_classification(struct pp_hwmgr *hwmgr,
-+					enum PP_StateClassificationFlag flag,
-+					unsigned long *state_id)
-+{
-+	struct pp_power_state *state;
-+	int table_entries;
-+	int i;
-+
-+	table_entries = hwmgr->num_ps;
-+	state = hwmgr->ps;
-+
-+	for (i = 0; i < table_entries; i++) {
-+		if (state->classification.flags & flag) {
-+			*state_id = state->id;
-+			return 0;
-+		}
-+		state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
-+	}
-+	return -EINVAL;
-+}
-+
-+static int psm_set_states(struct pp_hwmgr *hwmgr, unsigned long state_id)
-+{
-+	struct pp_power_state *state;
-+	int table_entries;
-+	int i;
-+
-+	table_entries = hwmgr->num_ps;
-+
-+	state = hwmgr->ps;
-+
-+	for (i = 0; i < table_entries; i++) {
-+		if (state->id == state_id) {
-+			memcpy(hwmgr->request_ps, state, hwmgr->ps_size);
-+			return 0;
-+		}
-+		state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
-+	}
-+	return -EINVAL;
-+}
-+
-+int psm_set_boot_states(struct pp_hwmgr *hwmgr)
-+{
-+	unsigned long state_id;
-+	int ret = -EINVAL;
-+
-+	if (!psm_get_state_by_classification(hwmgr, PP_StateClassificationFlag_Boot,
-+					&state_id))
-+		ret = psm_set_states(hwmgr, state_id);
-+
-+	return ret;
-+}
-+
-+int psm_set_performance_states(struct pp_hwmgr *hwmgr)
-+{
-+	unsigned long state_id;
-+	int ret = -EINVAL;
-+
-+	if (!psm_get_ui_state(hwmgr, PP_StateUILabel_Performance,
-+					&state_id))
-+		ret = psm_set_states(hwmgr, state_id);
-+
-+	return ret;
-+}
-+
-+int psm_set_user_performance_state(struct pp_hwmgr *hwmgr,
-+					enum PP_StateUILabel label_id,
-+					struct pp_power_state **state)
-+{
-+	int table_entries;
-+	int i;
-+
-+	table_entries = hwmgr->num_ps;
-+	*state = hwmgr->ps;
-+
-+restart_search:
-+	for (i = 0; i < table_entries; i++) {
-+		if ((*state)->classification.ui_label & label_id)
-+			return 0;
-+		*state = (struct pp_power_state *)((uintptr_t)*state + hwmgr->ps_size);
-+	}
-+
-+	switch (label_id) {
-+	case PP_StateUILabel_Battery:
-+	case PP_StateUILabel_Balanced:
-+		label_id = PP_StateUILabel_Performance;
-+		goto restart_search;
-+	default:
-+		break;
-+	}
-+	return -EINVAL;
-+}
-+
-+int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
-+						struct pp_power_state *new_ps)
-+{
-+	struct pp_power_state *pcurrent;
-+	struct pp_power_state *requested;
-+	bool equal;
-+
-+	if (skip)
-+		return 0;
-+
-+	phm_display_configuration_changed(hwmgr);
-+
-+	if (new_ps != NULL)
-+		requested = new_ps;
-+	else
-+		requested = hwmgr->request_ps;
-+
-+	pcurrent = hwmgr->current_ps;
-+
-+	phm_apply_state_adjust_rules(hwmgr, requested, pcurrent);
-+	if (pcurrent == NULL || (0 != phm_check_states_equal(hwmgr,
-+			&pcurrent->hardware, &requested->hardware, &equal)))
-+		equal = false;
-+
-+	if (!equal || phm_check_smc_update_required_for_display_configuration(hwmgr)) {
-+		phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware);
-+		memcpy(hwmgr->current_ps, hwmgr->request_ps, hwmgr->ps_size);
-+	}
-+
-+	phm_notify_smc_display_config_after_ps_adjustment(hwmgr);
-+
-+	return 0;
-+}
-+
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h.0130~	2017-12-14 06:39:58.471903606 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h	2017-12-14 06:39:58.471903606 +0100
-@@ -0,0 +1,40 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef PP_PSM_H
-+#define PP_PSM_H
-+
-+#include "hwmgr.h"
-+
-+int psm_init_power_state_table(struct pp_hwmgr *hwmgr);
-+int psm_fini_power_state_table(struct pp_hwmgr *hwmgr);
-+int psm_set_boot_states(struct pp_hwmgr *hwmgr);
-+int psm_set_performance_states(struct pp_hwmgr *hwmgr);
-+int psm_set_user_performance_state(struct pp_hwmgr *hwmgr,
-+					enum PP_StateUILabel label_id,
-+					struct pp_power_state **state);
-+int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr,
-+				bool skip,
-+				struct pp_power_state *new_ps);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c	2017-12-14 06:39:58.471903606 +0100
-@@ -24,7 +24,7 @@
- #include <linux/types.h>
- #include <linux/kernel.h>
- #include <linux/slab.h>
--
-+#include <drm/amdgpu_drm.h>
- #include "processpptables.h"
- #include <atom-types.h>
- #include <atombios.h>
-@@ -790,6 +790,39 @@ static const ATOM_PPLIB_STATE_V2 *get_st
- 	return pstate;
- }
- 
-+static const unsigned char soft_dummy_pp_table[] = {
-+	0xe1, 0x01, 0x06, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x00, 0x4a, 0x00, 0x6c, 0x00, 0x00,
-+	0x00, 0x00, 0x00, 0x42, 0x00, 0x02, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
-+	0x00, 0x4e, 0x00, 0x88, 0x00, 0x00, 0x9e, 0x00, 0x17, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
-+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+	0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00,
-+	0x07, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
-+	0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x18, 0x05, 0x00,
-+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00,
-+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe1, 0x00, 0x43, 0x01, 0x00, 0x00, 0x00, 0x00,
-+	0x8e, 0x01, 0x00, 0x00, 0xb8, 0x01, 0x00, 0x00, 0x08, 0x30, 0x75, 0x00, 0x80, 0x00, 0xa0, 0x8c,
-+	0x00, 0x7e, 0x00, 0x71, 0xa5, 0x00, 0x7c, 0x00, 0xe5, 0xc8, 0x00, 0x70, 0x00, 0x91, 0xf4, 0x00,
-+	0x64, 0x00, 0x40, 0x19, 0x01, 0x5a, 0x00, 0x0e, 0x28, 0x01, 0x52, 0x00, 0x80, 0x38, 0x01, 0x4a,
-+	0x00, 0x00, 0x09, 0x30, 0x75, 0x00, 0x30, 0x75, 0x00, 0x40, 0x9c, 0x00, 0x40, 0x9c, 0x00, 0x59,
-+	0xd8, 0x00, 0x59, 0xd8, 0x00, 0x91, 0xf4, 0x00, 0x91, 0xf4, 0x00, 0x0e, 0x28, 0x01, 0x0e, 0x28,
-+	0x01, 0x90, 0x5f, 0x01, 0x90, 0x5f, 0x01, 0x00, 0x77, 0x01, 0x00, 0x77, 0x01, 0xca, 0x91, 0x01,
-+	0xca, 0x91, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x80, 0x00, 0x00, 0x7e, 0x00, 0x01,
-+	0x7c, 0x00, 0x02, 0x70, 0x00, 0x03, 0x64, 0x00, 0x04, 0x5a, 0x00, 0x05, 0x52, 0x00, 0x06, 0x4a,
-+	0x00, 0x07, 0x08, 0x08, 0x00, 0x08, 0x00, 0x01, 0x02, 0x02, 0x02, 0x01, 0x02, 0x02, 0x02, 0x03,
-+	0x02, 0x04, 0x02, 0x00, 0x08, 0x40, 0x9c, 0x00, 0x30, 0x75, 0x00, 0x74, 0xb5, 0x00, 0xa0, 0x8c,
-+	0x00, 0x60, 0xea, 0x00, 0x74, 0xb5, 0x00, 0x0e, 0x28, 0x01, 0x60, 0xea, 0x00, 0x90, 0x5f, 0x01,
-+	0x40, 0x19, 0x01, 0xb2, 0xb0, 0x01, 0x90, 0x5f, 0x01, 0xc0, 0xd4, 0x01, 0x00, 0x77, 0x01, 0x5e,
-+	0xff, 0x01, 0xca, 0x91, 0x01, 0x08, 0x80, 0x00, 0x00, 0x7e, 0x00, 0x01, 0x7c, 0x00, 0x02, 0x70,
-+	0x00, 0x03, 0x64, 0x00, 0x04, 0x5a, 0x00, 0x05, 0x52, 0x00, 0x06, 0x4a, 0x00, 0x07, 0x00, 0x08,
-+	0x80, 0x00, 0x30, 0x75, 0x00, 0x7e, 0x00, 0x40, 0x9c, 0x00, 0x7c, 0x00, 0x59, 0xd8, 0x00, 0x70,
-+	0x00, 0xdc, 0x0b, 0x01, 0x64, 0x00, 0x80, 0x38, 0x01, 0x5a, 0x00, 0x80, 0x38, 0x01, 0x52, 0x00,
-+	0x80, 0x38, 0x01, 0x4a, 0x00, 0x80, 0x38, 0x01, 0x08, 0x30, 0x75, 0x00, 0x80, 0x00, 0xa0, 0x8c,
-+	0x00, 0x7e, 0x00, 0x71, 0xa5, 0x00, 0x7c, 0x00, 0xe5, 0xc8, 0x00, 0x74, 0x00, 0x91, 0xf4, 0x00,
-+	0x66, 0x00, 0x40, 0x19, 0x01, 0x58, 0x00, 0x0e, 0x28, 0x01, 0x52, 0x00, 0x80, 0x38, 0x01, 0x4a,
-+	0x00
-+};
- 
- static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table(
- 				     struct pp_hwmgr *hwmgr)
-@@ -799,12 +832,17 @@ static const ATOM_PPLIB_POWERPLAYTABLE *
- 	uint16_t size;
- 
- 	if (!table_addr) {
--		table_addr = cgs_atom_get_data_table(hwmgr->device,
--				GetIndexIntoMasterTable(DATA, PowerPlayInfo),
--				&size, &frev, &crev);
--
--		hwmgr->soft_pp_table = table_addr;
--		hwmgr->soft_pp_table_size = size;
-+		if (hwmgr->chip_id == CHIP_RAVEN) {
-+			table_addr = &soft_dummy_pp_table[0];
-+			hwmgr->soft_pp_table = &soft_dummy_pp_table[0];
-+			hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table);
-+		} else {
-+			table_addr = cgs_atom_get_data_table(hwmgr->device,
-+					GetIndexIntoMasterTable(DATA, PowerPlayInfo),
-+					&size, &frev, &crev);
-+			hwmgr->soft_pp_table = table_addr;
-+			hwmgr->soft_pp_table_size = size;
-+		}
- 	}
- 
- 	return (const ATOM_PPLIB_POWERPLAYTABLE *)table_addr;
-@@ -924,15 +962,14 @@ int pp_tables_get_entry(struct pp_hwmgr
- 		}
- 	}
- 
--	if ((0 == result) &&
--		(0 != (ps->classification.flags & PP_StateClassificationFlag_Boot)))
--		result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware));
-+	if ((0 == result) && (0 != (ps->classification.flags & PP_StateClassificationFlag_Boot))) {
-+		if (hwmgr->chip_family < AMDGPU_FAMILY_RV)
-+			result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware));
-+	}
- 
- 	return result;
- }
- 
--
--
- static int init_powerplay_tables(
- 			struct pp_hwmgr *hwmgr,
- 			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table
-@@ -1615,85 +1652,53 @@ static int pp_tables_uninitialize(struct
- 	if (hwmgr->chip_id == CHIP_RAVEN)
- 		return 0;
- 
--	if (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) {
--		kfree(hwmgr->dyn_state.vddc_dependency_on_sclk);
--		hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
--	}
-+	kfree(hwmgr->dyn_state.vddc_dependency_on_sclk);
-+	hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
- 
--	if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
--		kfree(hwmgr->dyn_state.vddci_dependency_on_mclk);
--		hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
--	}
-+	kfree(hwmgr->dyn_state.vddci_dependency_on_mclk);
-+	hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
- 
--	if (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) {
--		kfree(hwmgr->dyn_state.vddc_dependency_on_mclk);
--		hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
--	}
-+	kfree(hwmgr->dyn_state.vddc_dependency_on_mclk);
-+	hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
- 
--	if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) {
--		kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk);
--		hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
--	}
-+	kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk);
-+	hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
- 
--	if (NULL != hwmgr->dyn_state.valid_mclk_values) {
--		kfree(hwmgr->dyn_state.valid_mclk_values);
--		hwmgr->dyn_state.valid_mclk_values = NULL;
--	}
-+	kfree(hwmgr->dyn_state.valid_mclk_values);
-+	hwmgr->dyn_state.valid_mclk_values = NULL;
- 
--	if (NULL != hwmgr->dyn_state.valid_sclk_values) {
--		kfree(hwmgr->dyn_state.valid_sclk_values);
--		hwmgr->dyn_state.valid_sclk_values = NULL;
--	}
-+	kfree(hwmgr->dyn_state.valid_sclk_values);
-+	hwmgr->dyn_state.valid_sclk_values = NULL;
- 
--	if (NULL != hwmgr->dyn_state.cac_leakage_table) {
--		kfree(hwmgr->dyn_state.cac_leakage_table);
--		hwmgr->dyn_state.cac_leakage_table = NULL;
--	}
-+	kfree(hwmgr->dyn_state.cac_leakage_table);
-+	hwmgr->dyn_state.cac_leakage_table = NULL;
- 
--	if (NULL != hwmgr->dyn_state.vddc_phase_shed_limits_table) {
--		kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table);
--		hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL;
--	}
-+	kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table);
-+	hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL;
- 
--	if (NULL != hwmgr->dyn_state.vce_clock_voltage_dependency_table) {
--		kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table);
--		hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
--	}
-+	kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table);
-+	hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
- 
--	if (NULL != hwmgr->dyn_state.uvd_clock_voltage_dependency_table) {
--		kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
--		hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
--	}
-+	kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
-+	hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
- 
--	if (NULL != hwmgr->dyn_state.samu_clock_voltage_dependency_table) {
--		kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table);
--		hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
--	}
-+	kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table);
-+	hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
- 
--	if (NULL != hwmgr->dyn_state.acp_clock_voltage_dependency_table) {
--		kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table);
--		hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
--	}
-+	kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table);
-+	hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
- 
--	if (NULL != hwmgr->dyn_state.cac_dtp_table) {
--		kfree(hwmgr->dyn_state.cac_dtp_table);
--		hwmgr->dyn_state.cac_dtp_table = NULL;
--	}
-+	kfree(hwmgr->dyn_state.cac_dtp_table);
-+	hwmgr->dyn_state.cac_dtp_table = NULL;
- 
--	if (NULL != hwmgr->dyn_state.ppm_parameter_table) {
--		kfree(hwmgr->dyn_state.ppm_parameter_table);
--		hwmgr->dyn_state.ppm_parameter_table = NULL;
--	}
-+	kfree(hwmgr->dyn_state.ppm_parameter_table);
-+	hwmgr->dyn_state.ppm_parameter_table = NULL;
- 
--	if (NULL != hwmgr->dyn_state.vdd_gfx_dependency_on_sclk) {
--		kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk);
--		hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;
--	}
-+	kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk);
-+	hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;
- 
--	if (NULL != hwmgr->dyn_state.vq_budgeting_table) {
--		kfree(hwmgr->dyn_state.vq_budgeting_table);
--		hwmgr->dyn_state.vq_budgeting_table = NULL;
--	}
-+	kfree(hwmgr->dyn_state.vq_budgeting_table);
-+	hwmgr->dyn_state.vq_budgeting_table = NULL;
- 
- 	return 0;
- }
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c	2017-12-14 06:39:58.471903606 +0100
-@@ -173,8 +173,6 @@ static int get_vddc_lookup_table(
- 	if (NULL == table)
- 		return -ENOMEM;
- 
--	memset(table, 0x00, table_size);
--
- 	table->count = vddc_lookup_pp_tables->ucNumEntries;
- 
- 	for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++) {
-@@ -335,8 +333,6 @@ static int get_valid_clk(
- 	if (NULL == table)
- 		return -ENOMEM;
- 
--	memset(table, 0x00, table_size);
--
- 	table->count = (uint32_t)clk_volt_pp_table->count;
- 
- 	for (i = 0; i < table->count; i++) {
-@@ -390,8 +386,6 @@ static int get_mclk_voltage_dependency_t
- 	if (NULL == mclk_table)
- 		return -ENOMEM;
- 
--	memset(mclk_table, 0x00, table_size);
--
- 	mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;
- 
- 	for (i = 0; i < mclk_dep_table->ucNumEntries; i++) {
-@@ -439,8 +433,6 @@ static int get_sclk_voltage_dependency_t
- 		if (NULL == sclk_table)
- 			return -ENOMEM;
- 
--		memset(sclk_table, 0x00, table_size);
--
- 		sclk_table->count = (uint32_t)tonga_table->ucNumEntries;
- 
- 		for (i = 0; i < tonga_table->ucNumEntries; i++) {
-@@ -473,8 +465,6 @@ static int get_sclk_voltage_dependency_t
- 		if (NULL == sclk_table)
- 			return -ENOMEM;
- 
--		memset(sclk_table, 0x00, table_size);
--
- 		sclk_table->count = (uint32_t)polaris_table->ucNumEntries;
- 
- 		for (i = 0; i < polaris_table->ucNumEntries; i++) {
-@@ -525,8 +515,6 @@ static int get_pcie_table(
- 		if (pcie_table == NULL)
- 			return -ENOMEM;
- 
--		memset(pcie_table, 0x00, table_size);
--
- 		/*
- 		* Make sure the number of pcie entries are less than or equal to sclk dpm levels.
- 		* Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1.
-@@ -535,8 +523,7 @@ static int get_pcie_table(
- 		if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
- 			pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
- 		else
--			pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
--			Disregarding the excess entries... \n");
-+			pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n");
- 
- 		pcie_table->count = pcie_count;
- 		for (i = 0; i < pcie_count; i++) {
-@@ -567,8 +554,6 @@ static int get_pcie_table(
- 		if (pcie_table == NULL)
- 			return -ENOMEM;
- 
--		memset(pcie_table, 0x00, table_size);
--
- 		/*
- 		* Make sure the number of pcie entries are less than or equal to sclk dpm levels.
- 		* Since first PCIE entry is for ULV, #pcie has to be <= SclkLevel + 1.
-@@ -577,8 +562,7 @@ static int get_pcie_table(
- 		if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
- 			pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
- 		else
--			pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
--			Disregarding the excess entries... \n");
-+			pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n");
- 
- 		pcie_table->count = pcie_count;
- 
-@@ -615,8 +599,6 @@ static int get_cac_tdp_table(
- 	if (NULL == tdp_table)
- 		return -ENOMEM;
- 
--	memset(tdp_table, 0x00, table_size);
--
- 	hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL);
- 
- 	if (NULL == hwmgr->dyn_state.cac_dtp_table) {
-@@ -624,8 +606,6 @@ static int get_cac_tdp_table(
- 		return -ENOMEM;
- 	}
- 
--	memset(hwmgr->dyn_state.cac_dtp_table, 0x00, table_size);
--
- 	if (table->ucRevId < 3) {
- 		const ATOM_Tonga_PowerTune_Table *tonga_table =
- 			(ATOM_Tonga_PowerTune_Table *)table;
-@@ -725,8 +705,6 @@ static int get_mm_clock_voltage_table(
- 	if (NULL == mm_table)
- 		return -ENOMEM;
- 
--	memset(mm_table, 0x00, table_size);
--
- 	mm_table->count = mm_dependency_table->ucNumEntries;
- 
- 	for (i = 0; i < mm_dependency_table->ucNumEntries; i++) {
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c	2017-12-14 06:39:58.472903607 +0100
-@@ -38,20 +38,17 @@
- #include "pp_soc15.h"
- 
- #define RAVEN_MAX_DEEPSLEEP_DIVIDER_ID     5
--#define RAVEN_MINIMUM_ENGINE_CLOCK         800   //8Mhz, the low boundary of engine clock allowed on this chip
-+#define RAVEN_MINIMUM_ENGINE_CLOCK         800   /* 8Mhz, the low boundary of engine clock allowed on this chip */
- #define SCLK_MIN_DIV_INTV_SHIFT         12
--#define RAVEN_DISPCLK_BYPASS_THRESHOLD     10000 //100mhz
-+#define RAVEN_DISPCLK_BYPASS_THRESHOLD     10000 /* 100Mhz */
- #define SMC_RAM_END                     0x40000
- 
- static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Rv_Magic;
-+
-+
- int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
- 		struct pp_display_clock_request *clock_req);
- 
--struct phm_vq_budgeting_record rv_vqtable[] = {
--	/* _TBD
--	 * CUs, SSP low, SSP High, Min Sclk Low, Min Sclk, High, AWD/non-AWD, DCLK, ECLK, Sustainable Sclk, Sustainable CUs */
--	{ 8, 0, 45, 0, 0, VQ_DisplayConfig_NoneAWD, 80000, 120000, 4, 0 },
--};
- 
- static struct rv_power_state *cast_rv_ps(struct pp_hw_power_state *hw_ps)
- {
-@@ -70,101 +67,27 @@ static const struct rv_power_state *cast
- 	return (struct rv_power_state *)hw_ps;
- }
- 
--static int rv_init_vq_budget_table(struct pp_hwmgr *hwmgr)
--{
--	uint32_t table_size, i;
--	struct phm_vq_budgeting_table *ptable;
--	uint32_t num_entries = ARRAY_SIZE(rv_vqtable);
--
--	if (hwmgr->dyn_state.vq_budgeting_table != NULL)
--		return 0;
--
--	table_size = sizeof(struct phm_vq_budgeting_table) +
--			sizeof(struct phm_vq_budgeting_record) * (num_entries - 1);
--
--	ptable = kzalloc(table_size, GFP_KERNEL);
--	if (NULL == ptable)
--		return -ENOMEM;
--
--	ptable->numEntries = (uint8_t) num_entries;
--
--	for (i = 0; i < ptable->numEntries; i++) {
--		ptable->entries[i].ulCUs = rv_vqtable[i].ulCUs;
--		ptable->entries[i].ulSustainableSOCPowerLimitLow = rv_vqtable[i].ulSustainableSOCPowerLimitLow;
--		ptable->entries[i].ulSustainableSOCPowerLimitHigh = rv_vqtable[i].ulSustainableSOCPowerLimitHigh;
--		ptable->entries[i].ulMinSclkLow = rv_vqtable[i].ulMinSclkLow;
--		ptable->entries[i].ulMinSclkHigh = rv_vqtable[i].ulMinSclkHigh;
--		ptable->entries[i].ucDispConfig = rv_vqtable[i].ucDispConfig;
--		ptable->entries[i].ulDClk = rv_vqtable[i].ulDClk;
--		ptable->entries[i].ulEClk = rv_vqtable[i].ulEClk;
--		ptable->entries[i].ulSustainableSclk = rv_vqtable[i].ulSustainableSclk;
--		ptable->entries[i].ulSustainableCUs = rv_vqtable[i].ulSustainableCUs;
--	}
--
--	hwmgr->dyn_state.vq_budgeting_table = ptable;
--
--	return 0;
--}
--
- static int rv_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
- {
- 	struct rv_hwmgr *rv_hwmgr = (struct rv_hwmgr *)(hwmgr->backend);
--	struct cgs_system_info sys_info = {0};
--	int result;
- 
--	rv_hwmgr->ddi_power_gating_disabled = 0;
--	rv_hwmgr->bapm_enabled = 1;
- 	rv_hwmgr->dce_slow_sclk_threshold = 30000;
--	rv_hwmgr->disable_driver_thermal_policy = 1;
- 	rv_hwmgr->thermal_auto_throttling_treshold = 0;
- 	rv_hwmgr->is_nb_dpm_enabled = 1;
- 	rv_hwmgr->dpm_flags = 1;
--	rv_hwmgr->disable_smu_acp_s3_handshake = 1;
--	rv_hwmgr->disable_notify_smu_vpu_recovery = 0;
- 	rv_hwmgr->gfx_off_controled_by_driver = false;
--
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_DynamicM3Arbiter);
--
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_UVDPowerGating);
--
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_UVDDynamicPowerGating);
--
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_VCEPowerGating);
--
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_SamuPowerGating);
--
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_ACP);
-+	rv_hwmgr->need_min_deep_sleep_dcefclk = true;
-+	rv_hwmgr->num_active_display = 0;
-+	rv_hwmgr->deep_sleep_dcefclk = 0;
- 
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 					PHM_PlatformCaps_SclkDeepSleep);
- 
- 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_GFXDynamicMGPowerGating);
--
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 				PHM_PlatformCaps_SclkThrottleLowNotification);
- 
--	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_DisableVoltageIsland);
--
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_DynamicUVDState);
--
--	sys_info.size = sizeof(struct cgs_system_info);
--	sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
--	result = cgs_query_system_info(hwmgr->device, &sys_info);
--	if (!result) {
--		if (sys_info.value & AMD_PG_SUPPORT_GFX_DMG)
--			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--				      PHM_PlatformCaps_GFXDynamicMGPowerGating);
--	}
--
-+				PHM_PlatformCaps_PowerPlaySupport);
- 	return 0;
- }
- 
-@@ -234,102 +157,88 @@ static int rv_construct_boot_state(struc
- 	return 0;
- }
- 
--static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input,
--				void *output, void *storage, int result)
-+static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
- {
- 	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
- 	struct PP_Clocks clocks = {0};
- 	struct pp_display_clock_request clock_req;
- 
- 	clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk;
--	clocks.dcefClockInSR = hwmgr->display_config.min_dcef_deep_sleep_set_clk;
- 	clock_req.clock_type = amd_pp_dcf_clock;
- 	clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
- 
--	if (clocks.dcefClock == 0 && clocks.dcefClockInSR == 0)
--		clock_req.clock_freq_in_khz = rv_data->dcf_actual_hard_min_freq;
--
- 	PP_ASSERT_WITH_CODE(!rv_display_clock_voltage_request(hwmgr, &clock_req),
- 				"Attempt to set DCF Clock Failed!", return -EINVAL);
- 
--	if(rv_data->need_min_deep_sleep_dcefclk && 0 != clocks.dcefClockInSR)
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--					PPSMC_MSG_SetMinDeepSleepDcefclk,
--					clocks.dcefClockInSR / 100);
--	/*
--	if(!rv_data->isp_tileA_power_gated || !rv_data->isp_tileB_power_gated) {
--		if ((hwmgr->ispArbiter.iclk != 0) && (rv_data->ISPActualHardMinFreq != (hwmgr->ispArbiter.iclk / 100) )) {
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
--					PPSMC_MSG_SetHardMinIspclkByFreq, hwmgr->ispArbiter.iclk / 100);
--			rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->ISPActualHardMinFreq),
--		}
--	} */
--
- 	if (((hwmgr->uvd_arbiter.vclk_soft_min / 100) != rv_data->vclk_soft_min) ||
- 	    ((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) {
- 		rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100;
- 		rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100;
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_SetSoftMinVcn,
- 			(rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min);
- 	}
- 
- 	if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
- 		((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) {
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_SetHardMinSocclkByFreq,
- 					hwmgr->gfx_arbiter.sclk_hard_min / 100);
--			rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->soc_actual_hard_min_freq);
-+		rv_read_arg_from_smc(hwmgr, &rv_data->soc_actual_hard_min_freq);
- 	}
- 
- 	if ((hwmgr->gfx_arbiter.gfxclk != 0) &&
- 		(rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) {
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_SetMinVideoGfxclkFreq,
- 					hwmgr->gfx_arbiter.gfxclk / 100);
--		rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->gfx_actual_soft_min_freq);
-+		rv_read_arg_from_smc(hwmgr, &rv_data->gfx_actual_soft_min_freq);
- 	}
- 
- 	if ((hwmgr->gfx_arbiter.fclk != 0) &&
- 		(rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) {
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_SetMinVideoFclkFreq,
- 					hwmgr->gfx_arbiter.fclk / 100);
--		rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->fabric_actual_soft_min_freq);
-+		rv_read_arg_from_smc(hwmgr, &rv_data->fabric_actual_soft_min_freq);
- 	}
- 
- 	return 0;
- }
- 
--static int rv_tf_set_num_active_display(struct pp_hwmgr *hwmgr, void *input,
--				void *output, void *storage, int result)
-+static int rv_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
- {
--	uint32_t  num_of_active_displays = 0;
--	struct cgs_display_info info = {0};
-+	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
- 
--	cgs_get_active_displays_info(hwmgr->device, &info);
--	num_of_active_displays = info.display_count;
-+	if (rv_data->need_min_deep_sleep_dcefclk && rv_data->deep_sleep_dcefclk != clock/100) {
-+		rv_data->deep_sleep_dcefclk = clock/100;
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
-+					PPSMC_MSG_SetMinDeepSleepDcefclk,
-+					rv_data->deep_sleep_dcefclk);
-+	}
-+	return 0;
-+}
- 
--	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+static int rv_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
-+{
-+	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
-+
-+	if (rv_data->num_active_display != count) {
-+		rv_data->num_active_display = count;
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetDisplayCount,
--				num_of_active_displays);
-+				rv_data->num_active_display);
-+	}
-+
- 	return 0;
- }
- 
--static const struct phm_master_table_item rv_set_power_state_list[] = {
--	{ .tableFunction = rv_tf_set_clock_limit },
--	{ .tableFunction = rv_tf_set_num_active_display },
--	{ }
--};
--
--static const struct phm_master_table_header rv_set_power_state_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	rv_set_power_state_list
--};
-+static int rv_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
-+{
-+	return rv_set_clock_limit(hwmgr, input);
-+}
- 
--static int rv_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
--				void *output, void *storage, int result)
-+static int rv_init_power_gate_state(struct pp_hwmgr *hwmgr)
- {
- 	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
- 
-@@ -340,20 +249,13 @@ static int rv_tf_init_power_gate_state(s
- 	return 0;
- }
- 
--static const struct phm_master_table_item rv_setup_asic_list[] = {
--	{ .tableFunction = rv_tf_init_power_gate_state },
--	{ }
--};
- 
--static const struct phm_master_table_header rv_setup_asic_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	rv_setup_asic_list
--};
-+static int rv_setup_asic_task(struct pp_hwmgr *hwmgr)
-+{
-+	return rv_init_power_gate_state(hwmgr);
-+}
- 
--static int rv_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
--					void *input, void *output,
--					void *storage, int result)
-+static int rv_reset_cc6_data(struct pp_hwmgr *hwmgr)
- {
- 	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
- 
-@@ -365,66 +267,42 @@ static int rv_tf_reset_cc6_data(struct p
- 	return 0;
- }
- 
--static const struct phm_master_table_item rv_power_down_asic_list[] = {
--	{ .tableFunction = rv_tf_reset_cc6_data },
--	{ }
--};
--
--static const struct phm_master_table_header rv_power_down_asic_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	rv_power_down_asic_list
--};
--
-+static int rv_power_off_asic(struct pp_hwmgr *hwmgr)
-+{
-+	return rv_reset_cc6_data(hwmgr);
-+}
- 
--static int rv_tf_disable_gfx_off(struct pp_hwmgr *hwmgr,
--						void *input, void *output,
--						void *storage, int result)
-+static int rv_disable_gfx_off(struct pp_hwmgr *hwmgr)
- {
- 	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
- 
- 	if (rv_data->gfx_off_controled_by_driver)
--		smum_send_msg_to_smc(hwmgr->smumgr,
-+		smum_send_msg_to_smc(hwmgr,
- 						PPSMC_MSG_DisableGfxOff);
- 
- 	return 0;
- }
- 
--static const struct phm_master_table_item rv_disable_dpm_list[] = {
--	{ .tableFunction = rv_tf_disable_gfx_off },
--	{ },
--};
--
--
--static const struct phm_master_table_header rv_disable_dpm_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	rv_disable_dpm_list
--};
-+static int rv_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
-+{
-+	return rv_disable_gfx_off(hwmgr);
-+}
- 
--static int rv_tf_enable_gfx_off(struct pp_hwmgr *hwmgr,
--						void *input, void *output,
--						void *storage, int result)
-+static int rv_enable_gfx_off(struct pp_hwmgr *hwmgr)
- {
- 	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
- 
- 	if (rv_data->gfx_off_controled_by_driver)
--		smum_send_msg_to_smc(hwmgr->smumgr,
-+		smum_send_msg_to_smc(hwmgr,
- 						PPSMC_MSG_EnableGfxOff);
- 
- 	return 0;
- }
- 
--static const struct phm_master_table_item rv_enable_dpm_list[] = {
--	{ .tableFunction = rv_tf_enable_gfx_off },
--	{ },
--};
--
--static const struct phm_master_table_header rv_enable_dpm_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	rv_enable_dpm_list
--};
-+static int rv_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
-+{
-+	return rv_enable_gfx_off(hwmgr);
-+}
- 
- static int rv_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
- 				struct pp_power_state  *prequest_ps,
-@@ -434,37 +312,37 @@ static int rv_apply_state_adjust_rules(s
- }
- 
- /* temporary hardcoded clock voltage breakdown tables */
--DpmClock_t VddDcfClk[]= {
-+static const DpmClock_t VddDcfClk[]= {
- 	{ 300, 2600},
- 	{ 600, 3200},
- 	{ 600, 3600},
- };
- 
--DpmClock_t VddSocClk[]= {
-+static const DpmClock_t VddSocClk[]= {
- 	{ 478, 2600},
- 	{ 722, 3200},
- 	{ 722, 3600},
- };
- 
--DpmClock_t VddFClk[]= {
-+static const DpmClock_t VddFClk[]= {
- 	{ 400, 2600},
- 	{1200, 3200},
- 	{1200, 3600},
- };
- 
--DpmClock_t VddDispClk[]= {
-+static const DpmClock_t VddDispClk[]= {
- 	{ 435, 2600},
- 	{ 661, 3200},
- 	{1086, 3600},
- };
- 
--DpmClock_t VddDppClk[]= {
-+static const DpmClock_t VddDppClk[]= {
- 	{ 435, 2600},
- 	{ 661, 3200},
- 	{ 661, 3600},
- };
- 
--DpmClock_t VddPhyClk[]= {
-+static const DpmClock_t VddPhyClk[]= {
- 	{ 540, 2600},
- 	{ 810, 3200},
- 	{ 810, 3600},
-@@ -472,7 +350,7 @@ DpmClock_t VddPhyClk[]= {
- 
- static int rv_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
- 			struct rv_voltage_dependency_table **pptable,
--			uint32_t num_entry, DpmClock_t *pclk_dependency_table)
-+			uint32_t num_entry, const DpmClock_t *pclk_dependency_table)
- {
- 	uint32_t table_size, i;
- 	struct rv_voltage_dependency_table *ptable;
-@@ -505,7 +383,7 @@ static int rv_populate_clock_table(struc
- 	DpmClocks_t  *table = &(rv_data->clock_table);
- 	struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
- 
--	result = rv_copy_table_from_smc(hwmgr->smumgr, (uint8_t *)table, CLOCKTABLE);
-+	result = rv_copy_table_from_smc(hwmgr, (uint8_t *)table, CLOCKTABLE);
- 
- 	PP_ASSERT_WITH_CODE((0 == result),
- 			"Attempt to copy clock table from smc failed",
-@@ -543,6 +421,26 @@ static int rv_populate_clock_table(struc
- 	rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
- 					ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
- 
-+	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
-+			PPSMC_MSG_GetMinGfxclkFrequency),
-+			"Attempt to get min GFXCLK Failed!",
-+			return -1);
-+	PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
-+			&result),
-+			"Attempt to get min GFXCLK Failed!",
-+			return -1);
-+	rv_data->gfx_min_freq_limit = result * 100;
-+
-+	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
-+			PPSMC_MSG_GetMaxGfxclkFrequency),
-+			"Attempt to get max GFXCLK Failed!",
-+			return -1);
-+	PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
-+			&result),
-+			"Attempt to get max GFXCLK Failed!",
-+			return -1);
-+	rv_data->gfx_max_freq_limit = result * 100;
-+
- 	return 0;
- }
- 
-@@ -563,9 +461,6 @@ static int rv_hwmgr_backend_init(struct
- 		return result;
- 	}
- 
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--                PHM_PlatformCaps_PowerPlaySupport);
--
- 	rv_populate_clock_table(hwmgr);
- 
- 	result = rv_get_system_info_data(hwmgr);
-@@ -576,40 +471,6 @@ static int rv_hwmgr_backend_init(struct
- 
- 	rv_construct_boot_state(hwmgr);
- 
--	result = phm_construct_table(hwmgr, &rv_setup_asic_master,
--				&(hwmgr->setup_asic));
--	if (result != 0) {
--		pr_err("Fail to construct setup ASIC\n");
--		return result;
--	}
--
--	result = phm_construct_table(hwmgr, &rv_power_down_asic_master,
--				&(hwmgr->power_down_asic));
--	if (result != 0) {
--		pr_err("Fail to construct power down ASIC\n");
--		return result;
--	}
--
--	result = phm_construct_table(hwmgr, &rv_set_power_state_master,
--				&(hwmgr->set_power_state));
--	if (result != 0) {
--		pr_err("Fail to construct set_power_state\n");
--		return result;
--	}
--
--	result = phm_construct_table(hwmgr, &rv_disable_dpm_master,
--				&(hwmgr->disable_dynamic_state_management));
--	if (result != 0) {
--		pr_err("Fail to disable_dynamic_state\n");
--		return result;
--	}
--	result = phm_construct_table(hwmgr, &rv_enable_dpm_master,
--				&(hwmgr->enable_dynamic_state_management));
--	if (result != 0) {
--		pr_err("Fail to enable_dynamic_state\n");
--		return result;
--	}
--
- 	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
- 						RAVEN_MAX_HARDWARE_POWERLEVELS;
- 
-@@ -624,8 +485,6 @@ static int rv_hwmgr_backend_init(struct
- 
- 	hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
- 
--	rv_init_vq_budget_table(hwmgr);
--
- 	return result;
- }
- 
-@@ -634,46 +493,21 @@ static int rv_hwmgr_backend_fini(struct
- 	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
- 	struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
- 
--	phm_destroy_table(hwmgr, &(hwmgr->set_power_state));
--	phm_destroy_table(hwmgr, &(hwmgr->enable_dynamic_state_management));
--	phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management));
--	phm_destroy_table(hwmgr, &(hwmgr->power_down_asic));
--	phm_destroy_table(hwmgr, &(hwmgr->setup_asic));
--
--	if (pinfo->vdd_dep_on_dcefclk) {
--		kfree(pinfo->vdd_dep_on_dcefclk);
--		pinfo->vdd_dep_on_dcefclk = NULL;
--	}
--	if (pinfo->vdd_dep_on_socclk) {
--		kfree(pinfo->vdd_dep_on_socclk);
--		pinfo->vdd_dep_on_socclk = NULL;
--	}
--	if (pinfo->vdd_dep_on_fclk) {
--		kfree(pinfo->vdd_dep_on_fclk);
--		pinfo->vdd_dep_on_fclk = NULL;
--	}
--	if (pinfo->vdd_dep_on_dispclk) {
--		kfree(pinfo->vdd_dep_on_dispclk);
--		pinfo->vdd_dep_on_dispclk = NULL;
--	}
--	if (pinfo->vdd_dep_on_dppclk) {
--		kfree(pinfo->vdd_dep_on_dppclk);
--		pinfo->vdd_dep_on_dppclk = NULL;
--	}
--	if (pinfo->vdd_dep_on_phyclk) {
--		kfree(pinfo->vdd_dep_on_phyclk);
--		pinfo->vdd_dep_on_phyclk = NULL;
--	}
--
--	if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
--		kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
--		hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
--	}
-+	kfree(pinfo->vdd_dep_on_dcefclk);
-+	pinfo->vdd_dep_on_dcefclk = NULL;
-+	kfree(pinfo->vdd_dep_on_socclk);
-+	pinfo->vdd_dep_on_socclk = NULL;
-+	kfree(pinfo->vdd_dep_on_fclk);
-+	pinfo->vdd_dep_on_fclk = NULL;
-+	kfree(pinfo->vdd_dep_on_dispclk);
-+	pinfo->vdd_dep_on_dispclk = NULL;
-+	kfree(pinfo->vdd_dep_on_dppclk);
-+	pinfo->vdd_dep_on_dppclk = NULL;
-+	kfree(pinfo->vdd_dep_on_phyclk);
-+	pinfo->vdd_dep_on_phyclk = NULL;
- 
--	if (NULL != hwmgr->dyn_state.vq_budgeting_table) {
--		kfree(hwmgr->dyn_state.vq_budgeting_table);
--		hwmgr->dyn_state.vq_budgeting_table = NULL;
--	}
-+	kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
-+	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
- 
- 	kfree(hwmgr->backend);
- 	hwmgr->backend = NULL;
-@@ -687,12 +521,12 @@ static int rv_dpm_force_dpm_level(struct
- 	return 0;
- }
- 
--static int rv_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
-+static uint32_t rv_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
- {
- 	return 0;
- }
- 
--static int rv_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
-+static uint32_t rv_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
- {
- 	return 0;
- }
-@@ -711,18 +545,9 @@ static int rv_dpm_get_pp_table_entry_cal
- {
- 	struct rv_power_state *rv_ps = cast_rv_ps(hw_ps);
- 
--	const ATOM_PPLIB_CZ_CLOCK_INFO *rv_clock_info = clock_info;
--
--	struct phm_clock_voltage_dependency_table *table =
--				    hwmgr->dyn_state.vddc_dependency_on_sclk;
--	uint8_t clock_info_index = rv_clock_info->index;
--
--	if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
--		clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
--
--	rv_ps->levels[index].engine_clock = table->entries[clock_info_index].clk;
--	rv_ps->levels[index].vddc_index = (uint8_t)table->entries[clock_info_index].v;
-+	rv_ps->levels[index].engine_clock = 0;
- 
-+	rv_ps->levels[index].vddc_index = 0;
- 	rv_ps->level = index + 1;
- 
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
-@@ -794,43 +619,74 @@ static int rv_force_clock_level(struct p
- static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
- 		enum pp_clock_type type, char *buf)
- {
--	return 0;
-+	struct rv_hwmgr *data = (struct rv_hwmgr *)(hwmgr->backend);
-+	struct rv_voltage_dependency_table *mclk_table =
-+			data->clock_vol_info.vdd_dep_on_fclk;
-+	int i, now, size = 0;
-+
-+	switch (type) {
-+	case PP_SCLK:
-+		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
-+				PPSMC_MSG_GetGfxclkFrequency),
-+				"Attempt to get current GFXCLK Failed!",
-+				return -1);
-+		PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
-+				&now),
-+				"Attempt to get current GFXCLK Failed!",
-+				return -1);
-+
-+		size += sprintf(buf + size, "0: %uMhz %s\n",
-+				data->gfx_min_freq_limit / 100,
-+				((data->gfx_min_freq_limit / 100)
-+				 == now) ? "*" : "");
-+		size += sprintf(buf + size, "1: %uMhz %s\n",
-+				data->gfx_max_freq_limit / 100,
-+				((data->gfx_max_freq_limit / 100)
-+				 == now) ? "*" : "");
-+		break;
-+	case PP_MCLK:
-+		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
-+				PPSMC_MSG_GetFclkFrequency),
-+				"Attempt to get current MEMCLK Failed!",
-+				return -1);
-+		PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
-+				&now),
-+				"Attempt to get current MEMCLK Failed!",
-+				return -1);
-+
-+		for (i = 0; i < mclk_table->count; i++)
-+			size += sprintf(buf + size, "%d: %uMhz %s\n",
-+					i,
-+					mclk_table->entries[i].clk / 100,
-+					((mclk_table->entries[i].clk / 100)
-+					 == now) ? "*" : "");
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return size;
- }
- 
- static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
- 				PHM_PerformanceLevelDesignation designation, uint32_t index,
- 				PHM_PerformanceLevel *level)
- {
--	const struct rv_power_state *ps;
- 	struct rv_hwmgr *data;
--	uint32_t level_index;
--	uint32_t i;
--	uint32_t vol_dep_record_index = 0;
- 
- 	if (level == NULL || hwmgr == NULL || state == NULL)
- 		return -EINVAL;
- 
- 	data = (struct rv_hwmgr *)(hwmgr->backend);
--	ps = cast_const_rv_ps(state);
- 
--	level_index = index > ps->level - 1 ? ps->level - 1 : index;
--	level->coreClock = ps->levels[level_index].engine_clock;
--
--	if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
--		for (i = 1; i < ps->level; i++) {
--			if (ps->levels[i].engine_clock > data->dce_slow_sclk_threshold) {
--				level->coreClock = ps->levels[i].engine_clock;
--				break;
--			}
--		}
--	}
--
--	if (level_index == 0) {
--		vol_dep_record_index = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
--		level->memory_clock =
--			data->clock_vol_info.vdd_dep_on_fclk->entries[vol_dep_record_index].clk;
--	} else
-+	if (index == 0) {
- 		level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
-+		level->coreClock = data->gfx_min_freq_limit;
-+	} else {
-+		level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[
-+			data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
-+		level->coreClock = data->gfx_max_freq_limit;
-+	}
- 
- 	level->nonLocalMemoryFreq = 0;
- 	level->nonLocalMemoryWidth = 0;
-@@ -993,7 +849,7 @@ int rv_display_clock_voltage_request(str
- 		return -EINVAL;
- 	}
- 
--	result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg,
-+	result = smum_send_msg_to_smc_with_parameter(hwmgr, msg,
- 							clk_freq);
- 
- 	return result;
-@@ -1001,7 +857,8 @@ int rv_display_clock_voltage_request(str
- 
- static int rv_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
- {
--	return -EINVAL;
-+	clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */
-+	return 0;
- }
- 
- static int rv_thermal_get_temperature(struct pp_hwmgr *hwmgr)
-@@ -1023,13 +880,37 @@ static int rv_thermal_get_temperature(st
- static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
- 			  void *value, int *size)
- {
-+	uint32_t sclk, mclk;
-+	int ret = 0;
-+
- 	switch (idx) {
-+	case AMDGPU_PP_SENSOR_GFX_SCLK:
-+		ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
-+		if (!ret) {
-+			rv_read_arg_from_smc(hwmgr, &sclk);
-+			/* in units of 10KHZ */
-+			*((uint32_t *)value) = sclk * 100;
-+			*size = 4;
-+		}
-+		break;
-+	case AMDGPU_PP_SENSOR_GFX_MCLK:
-+		ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
-+		if (!ret) {
-+			rv_read_arg_from_smc(hwmgr, &mclk);
-+			/* in units of 10KHZ */
-+			*((uint32_t *)value) = mclk * 100;
-+			*size = 4;
-+		}
-+		break;
- 	case AMDGPU_PP_SENSOR_GPU_TEMP:
- 		*((uint32_t *)value) = rv_thermal_get_temperature(hwmgr);
--		return 0;
-+		break;
- 	default:
--		return -EINVAL;
-+		ret = -EINVAL;
-+		break;
- 	}
-+
-+	return ret;
- }
- 
- static const struct pp_hwmgr_func rv_hwmgr_funcs = {
-@@ -1058,6 +939,13 @@ static const struct pp_hwmgr_func rv_hwm
- 	.get_clock_by_type_with_voltage = rv_get_clock_by_type_with_voltage,
- 	.get_max_high_clocks = rv_get_max_high_clocks,
- 	.read_sensor = rv_read_sensor,
-+	.set_active_display_count = rv_set_active_display_count,
-+	.set_deep_sleep_dcefclk = rv_set_deep_sleep_dcefclk,
-+	.dynamic_state_management_enable = rv_enable_dpm_tasks,
-+	.power_off_asic = rv_power_off_asic,
-+	.asic_setup = rv_setup_asic_task,
-+	.power_state_set = rv_set_power_state_tasks,
-+	.dynamic_state_management_disable = rv_disable_dpm_tasks,
- };
- 
- int rv_init_function_pointers(struct pp_hwmgr *hwmgr)
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h	2017-12-14 06:39:58.472903607 +0100
-@@ -283,6 +283,8 @@ struct rv_hwmgr {
- 	uint32_t                        vclk_soft_min;
- 	uint32_t                        dclk_soft_min;
- 	uint32_t                        gfx_actual_soft_min_freq;
-+	uint32_t                        gfx_min_freq_limit;
-+	uint32_t                        gfx_max_freq_limit;
- 
- 	bool                           vcn_power_gated;
- 	bool                           vcn_dpg_mode;
-@@ -293,7 +295,9 @@ struct rv_hwmgr {
- 	DpmClocks_t                       clock_table;
- 
- 	uint32_t active_process_mask;
--	bool need_min_deep_sleep_dcefclk; /* disabled by default */
-+	bool need_min_deep_sleep_dcefclk;
-+	uint32_t                             deep_sleep_dcefclk;
-+	uint32_t                             num_active_display;
- };
- 
- struct pp_hwmgr;
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c	2017-12-14 06:39:58.472903607 +0100
-@@ -27,21 +27,21 @@
- 
- static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
- {
--	return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
-+	return smum_send_msg_to_smc(hwmgr, enable ?
- 			PPSMC_MSG_UVDDPM_Enable :
- 			PPSMC_MSG_UVDDPM_Disable);
- }
- 
- static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
- {
--	return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
-+	return smum_send_msg_to_smc(hwmgr, enable ?
- 			PPSMC_MSG_VCEDPM_Enable :
- 			PPSMC_MSG_VCEDPM_Disable);
- }
- 
- static int smu7_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
- {
--	return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
-+	return smum_send_msg_to_smc(hwmgr, enable ?
- 			PPSMC_MSG_SAMUDPM_Enable :
- 			PPSMC_MSG_SAMUDPM_Disable);
- }
-@@ -70,7 +70,7 @@ static int smu7_update_samu_dpm(struct p
- int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
- {
- 	if (phm_cf_want_uvd_power_gating(hwmgr))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
-+		return smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_UVDPowerOFF);
- 	return 0;
- }
-@@ -80,10 +80,10 @@ static int smu7_powerup_uvd(struct pp_hw
- 	if (phm_cf_want_uvd_power_gating(hwmgr)) {
- 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 				  PHM_PlatformCaps_UVDDynamicPowerGating)) {
--			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			return smum_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_UVDPowerON, 1);
- 		} else {
--			return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			return smum_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_UVDPowerON, 0);
- 		}
- 	}
-@@ -94,7 +94,7 @@ static int smu7_powerup_uvd(struct pp_hw
- static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
- {
- 	if (phm_cf_want_vce_power_gating(hwmgr))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
-+		return smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_VCEPowerOFF);
- 	return 0;
- }
-@@ -102,7 +102,7 @@ static int smu7_powerdown_vce(struct pp_
- static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
- {
- 	if (phm_cf_want_vce_power_gating(hwmgr))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
-+		return smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_VCEPowerON);
- 	return 0;
- }
-@@ -111,7 +111,7 @@ static int smu7_powerdown_samu(struct pp
- {
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_SamuPowerGating))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
-+		return smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_SAMPowerOFF);
- 	return 0;
- }
-@@ -120,7 +120,7 @@ static int smu7_powerup_samu(struct pp_h
- {
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_SamuPowerGating))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
-+		return smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_SAMPowerON);
- 	return 0;
- }
-@@ -140,7 +140,7 @@ int smu7_disable_clock_power_gating(stru
- 	return 0;
- }
- 
--int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
-+void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
- {
- 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- 
-@@ -166,10 +166,9 @@ int smu7_powergate_uvd(struct pp_hwmgr *
- 		smu7_update_uvd_dpm(hwmgr, false);
- 	}
- 
--	return 0;
- }
- 
--int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
-+void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
- {
- 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- 
-@@ -194,7 +193,6 @@ int smu7_powergate_vce(struct pp_hwmgr *
- 						AMD_PG_STATE_UNGATE);
- 		smu7_update_vce_dpm(hwmgr, false);
- 	}
--	return 0;
- }
- 
- int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
-@@ -237,7 +235,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_GFX_CGCG_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 			if (PP_STATE_SUPPORT_LS & *msg_id) {
-@@ -247,7 +245,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_GFX_CGLS_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 			break;
-@@ -260,7 +258,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_GFX_3DCG_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 
-@@ -271,7 +269,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_GFX_3DLS_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 			break;
-@@ -284,7 +282,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_GFX_RLC_LS_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 			break;
-@@ -297,7 +295,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_GFX_CP_LS_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 			break;
-@@ -311,7 +309,7 @@ int smu7_update_clock_gatings(struct pp_
- 						CG_GFX_OTHERS_MGCG_MASK);
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 			break;
-@@ -331,7 +329,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_SYS_BIF_MGCG_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 			if  (PP_STATE_SUPPORT_LS & *msg_id) {
-@@ -341,7 +339,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_SYS_BIF_MGLS_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 			break;
-@@ -354,7 +352,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_SYS_MC_MGCG_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 
-@@ -365,7 +363,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_SYS_MC_MGLS_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 			break;
-@@ -378,7 +376,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_SYS_DRM_MGCG_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 			if (PP_STATE_SUPPORT_LS & *msg_id) {
-@@ -388,7 +386,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_SYS_DRM_MGLS_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 			break;
-@@ -401,7 +399,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_SYS_HDP_MGCG_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 
-@@ -412,7 +410,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_SYS_HDP_MGLS_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 			break;
-@@ -425,7 +423,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_SYS_SDMA_MGCG_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 
-@@ -436,7 +434,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_SYS_SDMA_MGLS_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 			break;
-@@ -449,7 +447,7 @@ int smu7_update_clock_gatings(struct pp_
- 				value = CG_SYS_ROM_MASK;
- 
- 				if (smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr, msg, value))
-+						hwmgr, msg, value))
- 					return -EINVAL;
- 			}
- 			break;
-@@ -489,9 +487,9 @@ int smu7_enable_per_cu_power_gating(stru
- 	active_cus = sys_info.value;
- 
- 	if (enable)
--		return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		return smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);
- 	else
--		return smum_send_msg_to_smc(hwmgr->smumgr,
-+		return smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_GFX_CU_PG_DISABLE);
- }
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h	2017-12-14 06:39:58.472903607 +0100
-@@ -27,8 +27,8 @@
- #include "smu7_hwmgr.h"
- #include "pp_asicblocks.h"
- 
--int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
--int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
-+void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
-+void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
- int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr);
- int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
- int smu7_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c	2017-12-14 06:39:58.473903608 +0100
-@@ -26,6 +26,7 @@
- #include <linux/module.h>
- #include <linux/slab.h>
- #include <asm/div64.h>
-+#include <drm/amdgpu_drm.h>
- #include "pp_acpi.h"
- #include "ppatomctrl.h"
- #include "atombios.h"
-@@ -163,7 +164,7 @@ static int smu7_get_current_pcie_lane_nu
- static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
- {
- 	if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
--		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable);
-+		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable);
- 
- 	return 0;
- }
-@@ -300,28 +301,28 @@ static int smu7_construct_voltage_tables
- 			"Failed to retrieve SVI2 VDDC table from dependancy table.", return result;);
- 	}
- 
--	tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDC);
-+	tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
- 	PP_ASSERT_WITH_CODE(
- 			(data->vddc_voltage_table.count <= tmp),
- 		"Too many voltage values for VDDC. Trimming to fit state table.",
- 			phm_trim_voltage_table_to_fit_state_table(tmp,
- 						&(data->vddc_voltage_table)));
- 
--	tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX);
-+	tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
- 	PP_ASSERT_WITH_CODE(
- 			(data->vddgfx_voltage_table.count <= tmp),
- 		"Too many voltage values for VDDC. Trimming to fit state table.",
- 			phm_trim_voltage_table_to_fit_state_table(tmp,
- 						&(data->vddgfx_voltage_table)));
- 
--	tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDCI);
-+	tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
- 	PP_ASSERT_WITH_CODE(
- 			(data->vddci_voltage_table.count <= tmp),
- 		"Too many voltage values for VDDCI. Trimming to fit state table.",
- 			phm_trim_voltage_table_to_fit_state_table(tmp,
- 					&(data->vddci_voltage_table)));
- 
--	tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_MVDD);
-+	tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
- 	PP_ASSERT_WITH_CODE(
- 			(data->mvdd_voltage_table.count <= tmp),
- 		"Too many voltage values for MVDD. Trimming to fit state table.",
-@@ -387,6 +388,7 @@ static int smu7_enable_display_gap(struc
- static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
- {
- 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	int i;
- 
- 	/* Clear reset for voting clients before enabling DPM */
- 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-@@ -394,50 +396,26 @@ static int smu7_program_voting_clients(s
- 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 			SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
- 
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
--
-+	for (i = 0; i < 8; i++)
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixCG_FREQ_TRAN_VOTING_0 + i * 4,
-+					data->voting_rights_clients[i]);
- 	return 0;
- }
- 
- static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
- {
-+	int i;
-+
- 	/* Reset voting clients before disabling DPM */
- 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 			SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
- 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 			SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
- 
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_0, 0);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_1, 0);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_2, 0);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_3, 0);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_4, 0);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_5, 0);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_6, 0);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			ixCG_FREQ_TRAN_VOTING_7, 0);
-+	for (i = 0; i < 8; i++)
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0);
- 
- 	return 0;
- }
-@@ -493,7 +471,7 @@ static int smu7_copy_and_switch_arb_sets
- 
- static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
- {
--	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);
-+	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults);
- }
- 
- /**
-@@ -551,7 +529,7 @@ static int smu7_setup_default_pcie_table
- 		data->pcie_gen_performance = data->pcie_gen_power_saving;
- 		data->pcie_lane_performance = data->pcie_lane_power_saving;
- 	}
--	tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_LINK);
-+	tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
- 	phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
- 					tmp,
- 					MAX_REGULAR_DPM_NUMBER);
-@@ -607,13 +585,20 @@ static int smu7_setup_default_pcie_table
- 		data->dpm_table.pcie_speed_table.count = 6;
- 	}
- 	/* Populate last level for boot PCIE level, but do not increment count. */
--	phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
-+	if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
-+		for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++)
-+			phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i,
-+				get_pcie_gen_support(data->pcie_gen_cap,
-+						PP_Max_PCIEGen),
-+				data->vbios_boot_state.pcie_lane_bootup_value);
-+	} else {
-+		phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
- 			data->dpm_table.pcie_speed_table.count,
- 			get_pcie_gen_support(data->pcie_gen_cap,
- 					PP_Min_PCIEGen),
- 			get_pcie_lane_support(data->pcie_lane_cap,
- 					PP_Max_PCIELane));
--
-+	}
- 	return 0;
- }
- 
-@@ -625,27 +610,27 @@ static int smu7_reset_dpm_tables(struct
- 
- 	phm_reset_single_dpm_table(
- 			&data->dpm_table.sclk_table,
--				smum_get_mac_definition(hwmgr->smumgr,
-+				smum_get_mac_definition(hwmgr,
- 					SMU_MAX_LEVELS_GRAPHICS),
- 					MAX_REGULAR_DPM_NUMBER);
- 	phm_reset_single_dpm_table(
- 			&data->dpm_table.mclk_table,
--			smum_get_mac_definition(hwmgr->smumgr,
-+			smum_get_mac_definition(hwmgr,
- 				SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
- 
- 	phm_reset_single_dpm_table(
- 			&data->dpm_table.vddc_table,
--				smum_get_mac_definition(hwmgr->smumgr,
-+				smum_get_mac_definition(hwmgr,
- 					SMU_MAX_LEVELS_VDDC),
- 					MAX_REGULAR_DPM_NUMBER);
- 	phm_reset_single_dpm_table(
- 			&data->dpm_table.vddci_table,
--			smum_get_mac_definition(hwmgr->smumgr,
-+			smum_get_mac_definition(hwmgr,
- 				SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
- 
- 	phm_reset_single_dpm_table(
- 			&data->dpm_table.mvdd_table,
--				smum_get_mac_definition(hwmgr->smumgr,
-+				smum_get_mac_definition(hwmgr,
- 					SMU_MAX_LEVELS_MVDD),
- 					MAX_REGULAR_DPM_NUMBER);
- 	return 0;
-@@ -689,7 +674,7 @@ static int smu7_setup_dpm_tables_v0(stru
- 				allowed_vdd_sclk_table->entries[i].clk) {
- 			data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
- 				allowed_vdd_sclk_table->entries[i].clk;
--			data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */
-+			data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
- 			data->dpm_table.sclk_table.count++;
- 		}
- 	}
-@@ -703,7 +688,7 @@ static int smu7_setup_dpm_tables_v0(stru
- 			allowed_vdd_mclk_table->entries[i].clk) {
- 			data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
- 				allowed_vdd_mclk_table->entries[i].clk;
--			data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */
-+			data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0;
- 			data->dpm_table.mclk_table.count++;
- 		}
- 	}
-@@ -855,7 +840,7 @@ static int smu7_enable_vrhot_gpio_interr
- 
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_RegulatorHot))
--		return smum_send_msg_to_smc(hwmgr->smumgr,
-+		return smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_EnableVRHotGPIOInterrupt);
- 
- 	return 0;
-@@ -873,7 +858,7 @@ static int smu7_enable_ulv(struct pp_hwm
- 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- 
- 	if (data->ulv_supported)
--		return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
-+		return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV);
- 
- 	return 0;
- }
-@@ -883,7 +868,7 @@ static int smu7_disable_ulv(struct pp_hw
- 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- 
- 	if (data->ulv_supported)
--		return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV);
-+		return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV);
- 
- 	return 0;
- }
-@@ -892,12 +877,12 @@ static int smu7_enable_deep_sleep_master
- {
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_SclkDeepSleep)) {
--		if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
-+		if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON))
- 			PP_ASSERT_WITH_CODE(false,
- 					"Attempt to enable Master Deep Sleep switch failed!",
- 					return -EINVAL);
- 	} else {
--		if (smum_send_msg_to_smc(hwmgr->smumgr,
-+		if (smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_MASTER_DeepSleep_OFF)) {
- 			PP_ASSERT_WITH_CODE(false,
- 					"Attempt to disable Master Deep Sleep switch failed!",
-@@ -912,7 +897,7 @@ static int smu7_disable_deep_sleep_maste
- {
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_SclkDeepSleep)) {
--		if (smum_send_msg_to_smc(hwmgr->smumgr,
-+		if (smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_MASTER_DeepSleep_OFF)) {
- 			PP_ASSERT_WITH_CODE(false,
- 					"Attempt to disable Master Deep Sleep switch failed!",
-@@ -928,12 +913,12 @@ static int smu7_disable_handshake_uvd(st
- 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- 	uint32_t soft_register_value = 0;
- 	uint32_t handshake_disables_offset = data->soft_regs_start
--				+ smum_get_offsetof(hwmgr->smumgr,
-+				+ smum_get_offsetof(hwmgr,
- 					SMU_SoftRegisters, HandshakeDisables);
- 
- 	soft_register_value = cgs_read_ind_register(hwmgr->device,
- 				CGS_IND_REG__SMC, handshake_disables_offset);
--	soft_register_value |= smum_get_mac_definition(hwmgr->smumgr,
-+	soft_register_value |= smum_get_mac_definition(hwmgr,
- 					SMU_UVD_MCLK_HANDSHAKE_DISABLE);
- 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- 			handshake_disables_offset, soft_register_value);
-@@ -947,7 +932,7 @@ static int smu7_enable_sclk_mclk_dpm(str
- 	/* enable SCLK dpm */
- 	if (!data->sclk_dpm_key_disabled)
- 		PP_ASSERT_WITH_CODE(
--		(0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
-+		(0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable)),
- 		"Failed to enable SCLK DPM during DPM Start Function!",
- 		return -EINVAL);
- 
-@@ -956,20 +941,31 @@ static int smu7_enable_sclk_mclk_dpm(str
- 		if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
- 			smu7_disable_handshake_uvd(hwmgr);
- 		PP_ASSERT_WITH_CODE(
--				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				(0 == smum_send_msg_to_smc(hwmgr,
- 						PPSMC_MSG_MCLKDPM_Enable)),
- 				"Failed to enable MCLK DPM during DPM Start Function!",
- 				return -EINVAL);
- 
- 		PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
- 
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
--		udelay(10);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
-+
-+		if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
-+			udelay(10);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
-+		} else {
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
-+			udelay(10);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
-+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
-+		}
- 	}
- 
- 	return 0;
-@@ -993,11 +989,15 @@ static int smu7_start_dpm(struct pp_hwmg
- 
- 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- 			data->soft_regs_start +
--			smum_get_offsetof(hwmgr->smumgr, SMU_SoftRegisters,
-+			smum_get_offsetof(hwmgr, SMU_SoftRegisters,
- 						VoltageChangeTimeout), 0x1000);
- 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
- 			SWRST_COMMAND_1, RESETLC, 0x0);
- 
-+	if (hwmgr->chip_family == AMDGPU_FAMILY_CI)
-+		cgs_write_register(hwmgr->device, 0x1488,
-+			(cgs_read_register(hwmgr->device, 0x1488) & ~0x1));
-+
- 	if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
- 		pr_err("Failed to enable Sclk DPM and Mclk DPM!");
- 		return -EINVAL;
-@@ -1006,7 +1006,7 @@ static int smu7_start_dpm(struct pp_hwmg
- 	/* enable PCIE dpm */
- 	if (0 == data->pcie_dpm_key_disabled) {
- 		PP_ASSERT_WITH_CODE(
--				(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+				(0 == smum_send_msg_to_smc(hwmgr,
- 						PPSMC_MSG_PCIeDPM_Enable)),
- 				"Failed to enable pcie DPM during DPM Start Function!",
- 				return -EINVAL);
-@@ -1014,7 +1014,7 @@ static int smu7_start_dpm(struct pp_hwmg
- 
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 				PHM_PlatformCaps_Falcon_QuickTransition)) {
--		PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_EnableACDCGPIOInterrupt)),
- 				"Failed to enable AC DC GPIO Interrupt!",
- 				);
-@@ -1032,7 +1032,7 @@ static int smu7_disable_sclk_mclk_dpm(st
- 		PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
- 				"Trying to disable SCLK DPM when DPM is disabled",
- 				return 0);
--		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Disable);
-+		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable);
- 	}
- 
- 	/* disable MCLK dpm */
-@@ -1040,7 +1040,7 @@ static int smu7_disable_sclk_mclk_dpm(st
- 		PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
- 				"Trying to disable MCLK DPM when DPM is disabled",
- 				return 0);
--		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MCLKDPM_Disable);
-+		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable);
- 	}
- 
- 	return 0;
-@@ -1060,7 +1060,7 @@ static int smu7_stop_dpm(struct pp_hwmgr
- 	/* disable PCIE dpm */
- 	if (!data->pcie_dpm_key_disabled) {
- 		PP_ASSERT_WITH_CODE(
--				(smum_send_msg_to_smc(hwmgr->smumgr,
-+				(smum_send_msg_to_smc(hwmgr,
- 						PPSMC_MSG_PCIeDPM_Disable) == 0),
- 				"Failed to disable pcie DPM during DPM Stop Function!",
- 				return -EINVAL);
-@@ -1072,7 +1072,7 @@ static int smu7_stop_dpm(struct pp_hwmgr
- 			"Trying to disable voltage DPM when DPM is disabled",
- 			return 0);
- 
--	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Disable);
-+	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable);
- 
- 	return 0;
- }
-@@ -1226,7 +1226,7 @@ static int smu7_enable_dpm_tasks(struct
- 	PP_ASSERT_WITH_CODE((0 == tmp_result),
- 			"Failed to enable VR hot GPIO interrupt!", result = tmp_result);
- 
--	smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_NoDisplay);
-+	smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay);
- 
- 	tmp_result = smu7_enable_sclk_control(hwmgr);
- 	PP_ASSERT_WITH_CODE((0 == tmp_result),
-@@ -1361,14 +1361,14 @@ static void smu7_init_dpm_defaults(struc
- 	data->vddc_vddgfx_delta = 300;
- 	data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
- 	data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
--	data->voting_rights_clients0 = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
--	data->voting_rights_clients1 = SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
--	data->voting_rights_clients2 = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
--	data->voting_rights_clients3 = SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
--	data->voting_rights_clients4 = SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
--	data->voting_rights_clients5 = SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
--	data->voting_rights_clients6 = SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
--	data->voting_rights_clients7 = SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
-+	data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
-+	data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
-+	data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
-+	data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
-+	data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
-+	data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
-+	data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
-+	data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
- 
- 	data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
- 	data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
-@@ -1382,23 +1382,40 @@ static void smu7_init_dpm_defaults(struc
- 	data->force_pcie_gen = PP_PCIEGenInvalid;
- 	data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
- 
--	if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->smumgr->is_kicker) {
-+	if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
- 		uint8_t tmp1, tmp2;
- 		uint16_t tmp3 = 0;
- 		atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
- 						&tmp3);
- 		tmp3 = (tmp3 >> 5) & 0x3;
- 		data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
-+	} else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
-+		data->vddc_phase_shed_control = 1;
-+	} else {
-+		data->vddc_phase_shed_control = 0;
-+	}
-+
-+	if (hwmgr->chip_id  == CHIP_HAWAII) {
-+		data->thermal_temp_setting.temperature_low = 94500;
-+		data->thermal_temp_setting.temperature_high = 95000;
-+		data->thermal_temp_setting.temperature_shutdown = 104000;
-+	} else {
-+		data->thermal_temp_setting.temperature_low = 99500;
-+		data->thermal_temp_setting.temperature_high = 100000;
-+		data->thermal_temp_setting.temperature_shutdown = 104000;
- 	}
- 
- 	data->fast_watermark_threshold = 100;
--	if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+	if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
- 			VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
- 		data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
-+	else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
-+			VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
-+		data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
- 
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_ControlVDDGFX)) {
--		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+		if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
- 			VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
- 			data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
- 		}
-@@ -1406,25 +1423,24 @@ static void smu7_init_dpm_defaults(struc
- 
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_EnableMVDDControl)) {
--		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+		if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
- 				VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
- 			data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
--		else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+		else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
- 				VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
- 			data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
- 	}
- 
--	if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) {
-+	if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control)
- 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_ControlVDDGFX);
--	}
- 
- 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_ControlVDDCI)) {
--		if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+		if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
- 				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
- 			data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
--		else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
-+		else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
- 				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
- 			data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
- 	}
-@@ -1543,7 +1559,7 @@ static int smu7_get_evv_voltages(struct
- 					if (vddc >= 2000 || vddc == 0)
- 						return -EINVAL;
- 				} else {
--					pr_warn("failed to retrieving EVV voltage!\n");
-+					pr_debug("failed to retrieving EVV voltage!\n");
- 					continue;
- 				}
- 
-@@ -1676,7 +1692,7 @@ static int phm_add_voltage(struct pp_hwm
- 	PP_ASSERT_WITH_CODE((0 != look_up_table->count),
- 		"Lookup Table empty.", return -EINVAL);
- 
--	i = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX);
-+	i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
- 	PP_ASSERT_WITH_CODE((i >= look_up_table->count),
- 		"Lookup Table is full.", return -EINVAL);
- 
-@@ -2274,7 +2290,7 @@ static int smu7_set_private_data_based_o
- 		data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
- 	}
- 
--	if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count > 1)
-+	if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1)
- 		hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
- 
- 	return 0;
-@@ -2282,40 +2298,65 @@ static int smu7_set_private_data_based_o
- 
- static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
- {
--	if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
--		kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
--		hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
--	}
--	pp_smu7_thermal_fini(hwmgr);
--	if (NULL != hwmgr->backend) {
--		kfree(hwmgr->backend);
--		hwmgr->backend = NULL;
--	}
-+	kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
-+	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
-+	kfree(hwmgr->backend);
-+	hwmgr->backend = NULL;
-+
-+	return 0;
-+}
-+
-+static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
-+{
-+	uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	int i;
- 
-+	if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) {
-+		for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
-+			virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
-+			if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci,
-+								virtual_voltage_id,
-+								efuse_voltage_id) == 0) {
-+				if (vddc != 0 && vddc != virtual_voltage_id) {
-+					data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
-+					data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
-+					data->vddc_leakage.count++;
-+				}
-+				if (vddci != 0 && vddci != virtual_voltage_id) {
-+					data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci;
-+					data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id;
-+					data->vddci_leakage.count++;
-+				}
-+			}
-+		}
-+	}
- 	return 0;
- }
- 
- static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
- {
- 	struct smu7_hwmgr *data;
--	int result;
-+	int result = 0;
- 
- 	data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL);
- 	if (data == NULL)
- 		return -ENOMEM;
- 
- 	hwmgr->backend = data;
--	pp_smu7_thermal_initialize(hwmgr);
--
- 	smu7_patch_voltage_workaround(hwmgr);
- 	smu7_init_dpm_defaults(hwmgr);
- 
- 	/* Get leakage voltage based on leakage ID. */
--	result = smu7_get_evv_voltages(hwmgr);
--
--	if (result) {
--		pr_info("Get EVV Voltage Failed.  Abort Driver loading!\n");
--		return -EINVAL;
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EVV)) {
-+		result = smu7_get_evv_voltages(hwmgr);
-+		if (result) {
-+			pr_info("Get EVV Voltage Failed.  Abort Driver loading!\n");
-+			return -EINVAL;
-+		}
-+	} else {
-+		smu7_get_elb_voltages(hwmgr);
- 	}
- 
- 	if (hwmgr->pp_table_version == PP_TABLE_V1) {
-@@ -2382,7 +2423,7 @@ static int smu7_force_dpm_highest(struct
- 				level++;
- 
- 			if (level)
--				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				smum_send_msg_to_smc_with_parameter(hwmgr,
- 						PPSMC_MSG_PCIeDPM_ForceLevel, level);
- 		}
- 	}
-@@ -2395,7 +2436,7 @@ static int smu7_force_dpm_highest(struct
- 				level++;
- 
- 			if (level)
--				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				smum_send_msg_to_smc_with_parameter(hwmgr,
- 						PPSMC_MSG_SCLKDPM_SetEnabledMask,
- 						(1 << level));
- 		}
-@@ -2409,7 +2450,7 @@ static int smu7_force_dpm_highest(struct
- 				level++;
- 
- 			if (level)
--				smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+				smum_send_msg_to_smc_with_parameter(hwmgr,
- 						PPSMC_MSG_MCLKDPM_SetEnabledMask,
- 						(1 << level));
- 		}
-@@ -2428,14 +2469,14 @@ static int smu7_upload_dpm_level_enable_
- 
- 	if (!data->sclk_dpm_key_disabled) {
- 		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_SCLKDPM_SetEnabledMask,
- 					data->dpm_level_enable_mask.sclk_dpm_enable_mask);
- 	}
- 
- 	if (!data->mclk_dpm_key_disabled) {
- 		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_MCLKDPM_SetEnabledMask,
- 					data->dpm_level_enable_mask.mclk_dpm_enable_mask);
- 	}
-@@ -2451,7 +2492,7 @@ static int smu7_unforce_dpm_levels(struc
- 		return -EINVAL;
- 
- 	if (!data->pcie_dpm_key_disabled) {
--		smum_send_msg_to_smc(hwmgr->smumgr,
-+		smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_PCIeDPM_UnForceLevel);
- 	}
- 
-@@ -2468,7 +2509,7 @@ static int smu7_force_dpm_lowest(struct
- 		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
- 			level = phm_get_lowest_enabled_level(hwmgr,
- 							      data->dpm_level_enable_mask.sclk_dpm_enable_mask);
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
- 							    PPSMC_MSG_SCLKDPM_SetEnabledMask,
- 							    (1 << level));
- 
-@@ -2478,7 +2519,7 @@ static int smu7_force_dpm_lowest(struct
- 		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
- 			level = phm_get_lowest_enabled_level(hwmgr,
- 							      data->dpm_level_enable_mask.mclk_dpm_enable_mask);
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
- 							    PPSMC_MSG_MCLKDPM_SetEnabledMask,
- 							    (1 << level));
- 		}
-@@ -2488,7 +2529,7 @@ static int smu7_force_dpm_lowest(struct
- 		if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
- 			level = phm_get_lowest_enabled_level(hwmgr,
- 							      data->dpm_level_enable_mask.pcie_dpm_enable_mask);
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
- 							    PPSMC_MSG_PCIeDPM_ForceLevel,
- 							    (level));
- 		}
-@@ -2572,51 +2613,16 @@ static int smu7_force_dpm_level(struct p
- 	uint32_t sclk_mask = 0;
- 	uint32_t mclk_mask = 0;
- 	uint32_t pcie_mask = 0;
--	uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
--					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
--					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
--					AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
--
--	if (level == hwmgr->dpm_level)
--		return ret;
--
--	if (!(hwmgr->dpm_level & profile_mode_mask)) {
--		/* enter profile mode, save current level, disable gfx cg*/
--		if (level & profile_mode_mask) {
--			hwmgr->saved_dpm_level = hwmgr->dpm_level;
--			cgs_set_clockgating_state(hwmgr->device,
--						AMD_IP_BLOCK_TYPE_GFX,
--						AMD_CG_STATE_UNGATE);
--		}
--	} else {
--		/* exit profile mode, restore level, enable gfx cg*/
--		if (!(level & profile_mode_mask)) {
--			if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
--				level = hwmgr->saved_dpm_level;
--			cgs_set_clockgating_state(hwmgr->device,
--					AMD_IP_BLOCK_TYPE_GFX,
--					AMD_CG_STATE_GATE);
--		}
--	}
- 
- 	switch (level) {
- 	case AMD_DPM_FORCED_LEVEL_HIGH:
- 		ret = smu7_force_dpm_highest(hwmgr);
--		if (ret)
--			return ret;
--		hwmgr->dpm_level = level;
- 		break;
- 	case AMD_DPM_FORCED_LEVEL_LOW:
- 		ret = smu7_force_dpm_lowest(hwmgr);
--		if (ret)
--			return ret;
--		hwmgr->dpm_level = level;
- 		break;
- 	case AMD_DPM_FORCED_LEVEL_AUTO:
- 		ret = smu7_unforce_dpm_levels(hwmgr);
--		if (ret)
--			return ret;
--		hwmgr->dpm_level = level;
- 		break;
- 	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
- 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
-@@ -2625,26 +2631,23 @@ static int smu7_force_dpm_level(struct p
- 		ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
- 		if (ret)
- 			return ret;
--		hwmgr->dpm_level = level;
- 		smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
- 		smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
- 		smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask);
--
- 		break;
- 	case AMD_DPM_FORCED_LEVEL_MANUAL:
--		hwmgr->dpm_level = level;
--		break;
- 	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
- 	default:
- 		break;
- 	}
- 
--	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->saved_dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
--		smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
--	else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->saved_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
--		smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
--
--	return 0;
-+	if (!ret) {
-+		if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
-+			smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
-+		else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
-+			smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
-+	}
-+	return ret;
- }
- 
- static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr)
-@@ -2843,7 +2846,7 @@ static int smu7_apply_state_adjust_rules
- }
- 
- 
--static int smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
-+static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
- {
- 	struct pp_power_state  *ps;
- 	struct smu7_power_state  *smu7_ps;
-@@ -2865,7 +2868,7 @@ static int smu7_dpm_get_mclk(struct pp_h
- 				[smu7_ps->performance_level_count-1].memory_clock;
- }
- 
--static int smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
-+static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
- {
- 	struct pp_power_state  *ps;
- 	struct smu7_power_state  *smu7_ps;
-@@ -3002,7 +3005,7 @@ static int smu7_get_pp_table_entry_callb
- 			[smu7_power_state->performance_level_count++]);
- 
- 	PP_ASSERT_WITH_CODE(
--			(smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)),
-+			(smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
- 			"Performance levels exceeds SMC limit!",
- 			return -EINVAL);
- 
-@@ -3071,11 +3074,11 @@ static int smu7_get_pp_table_entry_v1(st
- 	if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
- 		if (dep_mclk_table->entries[0].clk !=
- 				data->vbios_boot_state.mclk_bootup_value)
--			pr_err("Single MCLK entry VDDCI/MCLK dependency table "
-+			pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
- 					"does not match VBIOS boot MCLK level");
- 		if (dep_mclk_table->entries[0].vddci !=
- 				data->vbios_boot_state.vddci_bootup_value)
--			pr_err("Single VDDCI entry VDDCI/MCLK dependency table "
-+			pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
- 					"does not match VBIOS boot VDDCI level");
- 	}
- 
-@@ -3166,7 +3169,7 @@ static int smu7_get_pp_table_entry_callb
- 		data->highest_mclk = memory_clock;
- 
- 	PP_ASSERT_WITH_CODE(
--			(ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)),
-+			(ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
- 			"Performance levels exceeds SMC limit!",
- 			return -EINVAL);
- 
-@@ -3219,11 +3222,11 @@ static int smu7_get_pp_table_entry_v0(st
- 	if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
- 		if (dep_mclk_table->entries[0].clk !=
- 				data->vbios_boot_state.mclk_bootup_value)
--			pr_err("Single MCLK entry VDDCI/MCLK dependency table "
-+			pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
- 					"does not match VBIOS boot MCLK level");
- 		if (dep_mclk_table->entries[0].v !=
- 				data->vbios_boot_state.vddci_bootup_value)
--			pr_err("Single VDDCI entry VDDCI/MCLK dependency table "
-+			pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
- 					"does not match VBIOS boot VDDCI level");
- 	}
- 
-@@ -3312,14 +3315,14 @@ static int smu7_get_pp_table_entry(struc
- static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr,
- 		struct pp_gpu_power *query)
- {
--	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
-+	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- 			PPSMC_MSG_PmStatusLogStart),
- 			"Failed to start pm status log!",
- 			return -1);
- 
- 	msleep_interruptible(20);
- 
--	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
-+	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- 			PPSMC_MSG_PmStatusLogSample),
- 			"Failed to sample pm status log!",
- 			return -1);
-@@ -3353,19 +3356,19 @@ static int smu7_read_sensor(struct pp_hw
- 
- 	switch (idx) {
- 	case AMDGPU_PP_SENSOR_GFX_SCLK:
--		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
-+		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
- 		sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
- 		*((uint32_t *)value) = sclk;
- 		*size = 4;
- 		return 0;
- 	case AMDGPU_PP_SENSOR_GFX_MCLK:
--		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
-+		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
- 		mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
- 		*((uint32_t *)value) = mclk;
- 		*size = 4;
- 		return 0;
- 	case AMDGPU_PP_SENSOR_GPU_LOAD:
--		offset = data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr,
-+		offset = data->soft_regs_start + smum_get_offsetof(hwmgr,
- 								SMU_SoftRegisters,
- 								AverageGraphicsActivity);
- 
-@@ -3532,7 +3535,7 @@ static int smu7_freeze_sclk_mclk_dpm(str
- 		PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
- 				"Trying to freeze SCLK DPM when DPM is disabled",
- 				);
--		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_SCLKDPM_FreezeLevel),
- 				"Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
- 				return -EINVAL);
-@@ -3544,7 +3547,7 @@ static int smu7_freeze_sclk_mclk_dpm(str
- 		PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
- 				"Trying to freeze MCLK DPM when DPM is disabled",
- 				);
--		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_MCLKDPM_FreezeLevel),
- 				"Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
- 				return -EINVAL);
-@@ -3762,7 +3765,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(s
- 		PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
- 				"Trying to Unfreeze SCLK DPM when DPM is disabled",
- 				);
--		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_SCLKDPM_UnfreezeLevel),
- 			"Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
- 			return -EINVAL);
-@@ -3774,8 +3777,8 @@ static int smu7_unfreeze_sclk_mclk_dpm(s
- 		PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
- 				"Trying to Unfreeze MCLK DPM when DPM is disabled",
- 				);
--		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
--				PPSMC_MSG_SCLKDPM_UnfreezeLevel),
-+		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
-+				PPSMC_MSG_MCLKDPM_UnfreezeLevel),
- 		    "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
- 		    return -EINVAL);
- 	}
-@@ -3824,9 +3827,9 @@ static int smu7_notify_smc_display(struc
- 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- 
- 	if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK)
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 			(PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
--	return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ?  0 : -EINVAL;
-+	return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ?  0 : -EINVAL;
- }
- 
- static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
-@@ -3899,10 +3902,7 @@ static int smu7_set_max_fan_pwm_output(s
- 	hwmgr->thermal_controller.
- 	advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
- 
--	if (phm_is_hw_access_blocked(hwmgr))
--		return 0;
--
--	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	return smum_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
- }
- 
-@@ -3911,7 +3911,7 @@ smu7_notify_smc_display_change(struct pp
- {
- 	PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
- 
--	return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
-+	return (smum_send_msg_to_smc(hwmgr, msg) == 0) ?  0 : -1;
- }
- 
- static int
-@@ -3974,12 +3974,12 @@ static int smu7_program_display_gap(stru
- 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
- 
- 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr,
-+			data->soft_regs_start + smum_get_offsetof(hwmgr,
- 							SMU_SoftRegisters,
- 							PreVBlankGap), 0x64);
- 
- 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
--			data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr,
-+			data->soft_regs_start + smum_get_offsetof(hwmgr,
- 							SMU_SoftRegisters,
- 							VBlankTimeout),
- 					(frame_time_in_us - pre_vbi_time_in_us));
-@@ -4004,10 +4004,7 @@ static int smu7_set_max_fan_rpm_output(s
- 	hwmgr->thermal_controller.
- 	advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
- 
--	if (phm_is_hw_access_blocked(hwmgr))
--		return 0;
--
--	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	return smum_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
- }
- 
-@@ -4249,21 +4246,21 @@ static int smu7_force_clock_level(struct
- {
- 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- 
--	if (hwmgr->dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
--				AMD_DPM_FORCED_LEVEL_LOW |
--				AMD_DPM_FORCED_LEVEL_HIGH))
-+	if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
-+					AMD_DPM_FORCED_LEVEL_LOW |
-+					AMD_DPM_FORCED_LEVEL_HIGH))
- 		return -EINVAL;
- 
- 	switch (type) {
- 	case PP_SCLK:
- 		if (!data->sclk_dpm_key_disabled)
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_SCLKDPM_SetEnabledMask,
- 					data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
- 		break;
- 	case PP_MCLK:
- 		if (!data->mclk_dpm_key_disabled)
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_MCLKDPM_SetEnabledMask,
- 					data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
- 		break;
-@@ -4276,7 +4273,7 @@ static int smu7_force_clock_level(struct
- 			level++;
- 
- 		if (!data->pcie_dpm_key_disabled)
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_PCIeDPM_ForceLevel,
- 					level);
- 		break;
-@@ -4300,7 +4297,7 @@ static int smu7_print_clock_levels(struc
- 
- 	switch (type) {
- 	case PP_SCLK:
--		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
-+		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
- 		clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
- 
- 		for (i = 0; i < sclk_table->count; i++) {
-@@ -4316,7 +4313,7 @@ static int smu7_print_clock_levels(struc
- 					(i == now) ? "*" : "");
- 		break;
- 	case PP_MCLK:
--		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
-+		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
- 		clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
- 
- 		for (i = 0; i < mclk_table->count; i++) {
-@@ -4342,9 +4339,9 @@ static int smu7_print_clock_levels(struc
- 
- 		for (i = 0; i < pcie_table->count; i++)
- 			size += sprintf(buf + size, "%d: %s %s\n", i,
--					(pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
--					(pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
--					(pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
-+					(pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" :
-+					(pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
-+					(pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
- 					(i == now) ? "*" : "");
- 		break;
- 	default:
-@@ -4353,31 +4350,27 @@ static int smu7_print_clock_levels(struc
- 	return size;
- }
- 
--static int smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
-+static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
- {
--	int result = 0;
--
- 	switch (mode) {
- 	case AMD_FAN_CTRL_NONE:
--		result = smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
-+		smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
- 		break;
- 	case AMD_FAN_CTRL_MANUAL:
- 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_MicrocodeFanControl))
--			result = smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
-+			smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
- 		break;
- 	case AMD_FAN_CTRL_AUTO:
--		result = smu7_fan_ctrl_set_static_mode(hwmgr, mode);
--		if (!result)
--			result = smu7_fan_ctrl_start_smc_fan_control(hwmgr);
-+		if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode))
-+			smu7_fan_ctrl_start_smc_fan_control(hwmgr);
- 		break;
- 	default:
- 		break;
- 	}
--	return result;
- }
- 
--static int smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)
-+static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)
- {
- 	return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL;
- }
-@@ -4606,7 +4599,7 @@ static int smu7_set_power_profile_state(
- 
- 	if (sclk_mask) {
- 		if (!data->sclk_dpm_key_disabled)
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SCLKDPM_SetEnabledMask,
- 				data->dpm_level_enable_mask.
- 				sclk_dpm_enable_mask &
-@@ -4615,7 +4608,7 @@ static int smu7_set_power_profile_state(
- 
- 	if (mclk_mask) {
- 		if (!data->mclk_dpm_key_disabled)
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_MCLKDPM_SetEnabledMask,
- 				data->dpm_level_enable_mask.
- 				mclk_dpm_enable_mask &
-@@ -4627,8 +4620,7 @@ static int smu7_set_power_profile_state(
- 
- static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
- {
--	struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr);
--	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
-+	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
- 
- 	if (smu_data == NULL)
- 		return -EINVAL;
-@@ -4640,19 +4632,60 @@ static int smu7_avfs_control(struct pp_h
- 		if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
- 				CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
- 			PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
--					hwmgr->smumgr, PPSMC_MSG_EnableAvfs),
-+					hwmgr, PPSMC_MSG_EnableAvfs),
- 					"Failed to enable AVFS!",
- 					return -EINVAL);
- 	} else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
- 			CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
- 		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
--				hwmgr->smumgr, PPSMC_MSG_DisableAvfs),
-+				hwmgr, PPSMC_MSG_DisableAvfs),
- 				"Failed to disable AVFS!",
- 				return -EINVAL);
- 
- 	return 0;
- }
- 
-+static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
-+					uint32_t virtual_addr_low,
-+					uint32_t virtual_addr_hi,
-+					uint32_t mc_addr_low,
-+					uint32_t mc_addr_hi,
-+					uint32_t size)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					data->soft_regs_start +
-+					smum_get_offsetof(hwmgr,
-+					SMU_SoftRegisters, DRAM_LOG_ADDR_H),
-+					mc_addr_hi);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					data->soft_regs_start +
-+					smum_get_offsetof(hwmgr,
-+					SMU_SoftRegisters, DRAM_LOG_ADDR_L),
-+					mc_addr_low);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					data->soft_regs_start +
-+					smum_get_offsetof(hwmgr,
-+					SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H),
-+					virtual_addr_hi);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					data->soft_regs_start +
-+					smum_get_offsetof(hwmgr,
-+					SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L),
-+					virtual_addr_low);
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					data->soft_regs_start +
-+					smum_get_offsetof(hwmgr,
-+					SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE),
-+					size);
-+	return 0;
-+}
-+
- static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
- 	.backend_init = &smu7_hwmgr_backend_init,
- 	.backend_fini = &smu7_hwmgr_backend_fini,
-@@ -4703,6 +4736,8 @@ static const struct pp_hwmgr_func smu7_h
- 	.set_power_profile_state = smu7_set_power_profile_state,
- 	.avfs_control = smu7_avfs_control,
- 	.disable_smc_firmware_ctf = smu7_thermal_disable_alert,
-+	.start_thermal_controller = smu7_start_thermal_controller,
-+	.notify_cac_buffer_info = smu7_notify_cac_buffer_info,
- };
- 
- uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h	2017-12-14 06:39:58.473903608 +0100
-@@ -182,14 +182,7 @@ struct smu7_hwmgr {
- 	struct smu7_dpm_table			dpm_table;
- 	struct smu7_dpm_table			golden_dpm_table;
- 
--	uint32_t						voting_rights_clients0;
--	uint32_t						voting_rights_clients1;
--	uint32_t						voting_rights_clients2;
--	uint32_t						voting_rights_clients3;
--	uint32_t						voting_rights_clients4;
--	uint32_t						voting_rights_clients5;
--	uint32_t						voting_rights_clients6;
--	uint32_t						voting_rights_clients7;
-+	uint32_t						voting_rights_clients[8];
- 	uint32_t						static_screen_threshold_unit;
- 	uint32_t						static_screen_threshold;
- 	uint32_t						voltage_control;
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c	2017-12-14 06:39:58.473903608 +0100
-@@ -629,51 +629,38 @@ static int smu7_enable_didt(struct pp_hw
- 	uint32_t block_en = 0;
- 	int32_t result = 0;
- 	uint32_t didt_block;
--	uint32_t data;
- 
- 	if (hwmgr->chip_id == CHIP_POLARIS11)
- 		didt_block = Polaris11_DIDTBlock_Info;
- 	else
- 		didt_block = DIDTBlock_Info;
- 
--	block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) ? en : 0;
--
--	data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0);
--	data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
--	data |= ((block_en << DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0, data);
-+	block_en = PP_CAP(PHM_PlatformCaps_SQRamping) ? en : 0;
-+	CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
-+			     DIDT_SQ_CTRL0, DIDT_CTRL_EN, block_en);
- 	didt_block &= ~SQ_Enable_MASK;
- 	didt_block |= block_en << SQ_Enable_SHIFT;
- 
--	block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) ? en : 0;
--
--	data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0);
--	data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
--	data |= ((block_en << DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0, data);
-+	block_en = PP_CAP(PHM_PlatformCaps_DBRamping) ? en : 0;
-+	CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
-+			     DIDT_DB_CTRL0, DIDT_CTRL_EN, block_en);
- 	didt_block &= ~DB_Enable_MASK;
- 	didt_block |= block_en << DB_Enable_SHIFT;
- 
--	block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) ? en : 0;
--	data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0);
--	data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
--	data |= ((block_en << DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0, data);
-+	block_en = PP_CAP(PHM_PlatformCaps_TDRamping) ? en : 0;
-+	CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
-+			     DIDT_TD_CTRL0, DIDT_CTRL_EN, block_en);
- 	didt_block &= ~TD_Enable_MASK;
- 	didt_block |= block_en << TD_Enable_SHIFT;
- 
--	block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping) ? en : 0;
--
--	data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0);
--	data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
--	data |= ((block_en << DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK);
--	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0, data);
-+	block_en = PP_CAP(PHM_PlatformCaps_TCPRamping) ? en : 0;
-+	CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
-+			     DIDT_TCP_CTRL0, DIDT_CTRL_EN, block_en);
- 	didt_block &= ~TCP_Enable_MASK;
- 	didt_block |= block_en << TCP_Enable_SHIFT;
- 
--
- 	if (enable)
--		result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_Didt_Block_Function, didt_block);
-+		result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Didt_Block_Function, didt_block);
- 
- 	return result;
- }
-@@ -753,12 +740,13 @@ int smu7_enable_didt_config(struct pp_hw
- 	if (result == 0)
- 		num_se = sys_info.value;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) ||
--		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) ||
--		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) ||
--		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
-+	if (PP_CAP(PHM_PlatformCaps_SQRamping) ||
-+	    PP_CAP(PHM_PlatformCaps_DBRamping) ||
-+	    PP_CAP(PHM_PlatformCaps_TDRamping) ||
-+	    PP_CAP(PHM_PlatformCaps_TCPRamping)) {
- 
- 		cgs_enter_safe_mode(hwmgr->device, true);
-+		cgs_lock_grbm_idx(hwmgr->device, true);
- 		value = 0;
- 		value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX);
- 		for (count = 0; count < num_se; count++) {
-@@ -775,7 +763,7 @@ int smu7_enable_didt_config(struct pp_hw
- 			} else if (hwmgr->chip_id == CHIP_POLARIS11) {
- 				result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
- 				PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
--				if (hwmgr->smumgr->is_kicker)
-+				if (hwmgr->is_kicker)
- 					result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker);
- 				else
- 					result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
-@@ -793,11 +781,12 @@ int smu7_enable_didt_config(struct pp_hw
- 		PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", return result);
- 
- 		if (hwmgr->chip_id == CHIP_POLARIS11) {
--			result = smum_send_msg_to_smc(hwmgr->smumgr,
-+			result = smum_send_msg_to_smc(hwmgr,
- 						(uint16_t)(PPSMC_MSG_EnableDpmDidt));
- 			PP_ASSERT_WITH_CODE((0 == result),
- 					"Failed to enable DPM DIDT.", return result);
- 		}
-+		cgs_lock_grbm_idx(hwmgr->device, false);
- 		cgs_enter_safe_mode(hwmgr->device, false);
- 	}
- 
-@@ -808,10 +797,10 @@ int smu7_disable_didt_config(struct pp_h
- {
- 	int result;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) ||
--		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) ||
--		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) ||
--		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
-+	if (PP_CAP(PHM_PlatformCaps_SQRamping) ||
-+	    PP_CAP(PHM_PlatformCaps_DBRamping) ||
-+	    PP_CAP(PHM_PlatformCaps_TDRamping) ||
-+	    PP_CAP(PHM_PlatformCaps_TCPRamping)) {
- 
- 		cgs_enter_safe_mode(hwmgr->device, true);
- 
-@@ -820,7 +809,7 @@ int smu7_disable_didt_config(struct pp_h
- 				"Post DIDT enable clock gating failed.",
- 				return result);
- 		if (hwmgr->chip_id == CHIP_POLARIS11) {
--			result = smum_send_msg_to_smc(hwmgr->smumgr,
-+			result = smum_send_msg_to_smc(hwmgr,
- 						(uint16_t)(PPSMC_MSG_DisableDpmDidt));
- 			PP_ASSERT_WITH_CODE((0 == result),
- 					"Failed to disable DPM DIDT.", return result);
-@@ -836,10 +825,9 @@ int smu7_enable_smc_cac(struct pp_hwmgr
- 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- 	int result = 0;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_CAC)) {
-+	if (PP_CAP(PHM_PlatformCaps_CAC)) {
- 		int smc_result;
--		smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+		smc_result = smum_send_msg_to_smc(hwmgr,
- 				(uint16_t)(PPSMC_MSG_EnableCac));
- 		PP_ASSERT_WITH_CODE((0 == smc_result),
- 				"Failed to enable CAC in SMC.", result = -1);
-@@ -854,9 +842,8 @@ int smu7_disable_smc_cac(struct pp_hwmgr
- 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- 	int result = 0;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_CAC) && data->cac_enabled) {
--		int smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+	if (PP_CAP(PHM_PlatformCaps_CAC) && data->cac_enabled) {
-+		int smc_result = smum_send_msg_to_smc(hwmgr,
- 				(uint16_t)(PPSMC_MSG_DisableCac));
- 		PP_ASSERT_WITH_CODE((smc_result == 0),
- 				"Failed to disable CAC in SMC.", result = -1);
-@@ -872,7 +859,7 @@ int smu7_set_power_limit(struct pp_hwmgr
- 
- 	if (data->power_containment_features &
- 			POWERCONTAINMENT_FEATURE_PkgPwrLimit)
--		return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		return smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_PkgPwrSetLimit, n);
- 	return 0;
- }
-@@ -880,7 +867,7 @@ int smu7_set_power_limit(struct pp_hwmgr
- static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr,
- 						uint32_t target_tdp)
- {
--	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	return smum_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
- }
- 
-@@ -899,11 +886,9 @@ int smu7_enable_power_containment(struct
- 	else
- 		cac_table = hwmgr->dyn_state.cac_dtp_table;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_PowerContainment)) {
--
-+	if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
- 		if (data->enable_tdc_limit_feature) {
--			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+			smc_result = smum_send_msg_to_smc(hwmgr,
- 					(uint16_t)(PPSMC_MSG_TDCLimitEnable));
- 			PP_ASSERT_WITH_CODE((0 == smc_result),
- 					"Failed to enable TDCLimit in SMC.", result = -1;);
-@@ -913,14 +898,13 @@ int smu7_enable_power_containment(struct
- 		}
- 
- 		if (data->enable_pkg_pwr_tracking_feature) {
--			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+			smc_result = smum_send_msg_to_smc(hwmgr,
- 					(uint16_t)(PPSMC_MSG_PkgPwrLimitEnable));
- 			PP_ASSERT_WITH_CODE((0 == smc_result),
- 					"Failed to enable PkgPwrTracking in SMC.", result = -1;);
- 			if (0 == smc_result) {
- 				uint32_t default_limit =
- 					(uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256);
--
- 				data->power_containment_features |=
- 						POWERCONTAINMENT_FEATURE_PkgPwrLimit;
- 
-@@ -937,14 +921,13 @@ int smu7_disable_power_containment(struc
- 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- 	int result = 0;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_PowerContainment) &&
--			data->power_containment_features) {
-+	if (PP_CAP(PHM_PlatformCaps_PowerContainment) &&
-+	    data->power_containment_features) {
- 		int smc_result;
- 
- 		if (data->power_containment_features &
- 				POWERCONTAINMENT_FEATURE_TDCLimit) {
--			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+			smc_result = smum_send_msg_to_smc(hwmgr,
- 					(uint16_t)(PPSMC_MSG_TDCLimitDisable));
- 			PP_ASSERT_WITH_CODE((smc_result == 0),
- 					"Failed to disable TDCLimit in SMC.",
-@@ -953,7 +936,7 @@ int smu7_disable_power_containment(struc
- 
- 		if (data->power_containment_features &
- 				POWERCONTAINMENT_FEATURE_DTE) {
--			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+			smc_result = smum_send_msg_to_smc(hwmgr,
- 					(uint16_t)(PPSMC_MSG_DisableDTE));
- 			PP_ASSERT_WITH_CODE((smc_result == 0),
- 					"Failed to disable DTE in SMC.",
-@@ -962,7 +945,7 @@ int smu7_disable_power_containment(struc
- 
- 		if (data->power_containment_features &
- 				POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
--			smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
-+			smc_result = smum_send_msg_to_smc(hwmgr,
- 					(uint16_t)(PPSMC_MSG_PkgPwrLimitDisable));
- 			PP_ASSERT_WITH_CODE((smc_result == 0),
- 					"Failed to disable PkgPwrTracking in SMC.",
-@@ -987,16 +970,17 @@ int smu7_power_control_set_level(struct
- 		cac_table = table_info->cac_dtp_table;
- 	else
- 		cac_table = hwmgr->dyn_state.cac_dtp_table;
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_PowerContainment)) {
-+	if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
- 		/* adjustment percentage has already been validated */
- 		adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
- 				hwmgr->platform_descriptor.TDPAdjustment :
- 				(-1 * hwmgr->platform_descriptor.TDPAdjustment);
--		/* SMC requested that target_tdp to be 7 bit fraction in DPM table
--		 * but message to be 8 bit fraction for messages
--		 */
--		target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
-+
-+		 if (hwmgr->chip_id > CHIP_TONGA)
-+			target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
-+		else
-+			target_tdp = ((100 + adjust_percent) * (int)(cac_table->usConfigurableTDP * 256)) / 100;
-+
- 		result = smu7_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
- 	}
- 
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c	2017-12-14 06:39:58.473903608 +0100
-@@ -37,9 +37,8 @@ int smu7_fan_ctrl_get_fan_speed_info(str
- 	fan_speed_info->min_percent = 0;
- 	fan_speed_info->max_percent = 100;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
--		hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
-+	if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
-+	    hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
- 		fan_speed_info->supports_rpm_read = true;
- 		fan_speed_info->supports_rpm_write = true;
- 		fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM;
-@@ -87,8 +86,7 @@ int smu7_fan_ctrl_get_fan_speed_rpm(stru
- 	uint32_t crystal_clock_freq;
- 
- 	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
--			(hwmgr->thermal_controller.fanInfo.
--				ucTachometerPulsesPerRevolution == 0))
-+	    !hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution)
- 		return -ENODEV;
- 
- 	tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-@@ -152,13 +150,11 @@ int smu7_fan_ctrl_start_smc_fan_control(
- {
- 	int result;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
-+	if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
- 		cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY);
--		result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
-+		result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl);
- 
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_FanSpeedInTableIsRPM))
-+		if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM))
- 			hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
- 					hwmgr->thermal_controller.
- 					advanceFanControlParameters.usMaxFanRPM);
-@@ -169,12 +165,12 @@ int smu7_fan_ctrl_start_smc_fan_control(
- 
- 	} else {
- 		cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE);
--		result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
-+		result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl);
- 	}
- 
- 	if (!result && hwmgr->thermal_controller.
- 			advanceFanControlParameters.ucTargetTemperature)
--		result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		result = smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetFanTemperatureTarget,
- 				hwmgr->thermal_controller.
- 				advanceFanControlParameters.ucTargetTemperature);
-@@ -187,7 +183,7 @@ int smu7_fan_ctrl_start_smc_fan_control(
- int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
- {
- 	hwmgr->fan_ctrl_enabled = false;
--	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl);
-+	return smum_send_msg_to_smc(hwmgr, PPSMC_StopFanControl);
- }
- 
- /**
-@@ -209,8 +205,7 @@ int smu7_fan_ctrl_set_fan_speed_percent(
- 	if (speed > 100)
- 		speed = 100;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_MicrocodeFanControl))
-+	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
- 		smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
- 
- 	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-@@ -241,8 +236,7 @@ int smu7_fan_ctrl_reset_fan_speed_to_def
- 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
- 		return 0;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_MicrocodeFanControl)) {
-+	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {
- 		result = smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
- 		if (!result)
- 			result = smu7_fan_ctrl_start_smc_fan_control(hwmgr);
-@@ -270,8 +264,7 @@ int smu7_fan_ctrl_set_fan_speed_rpm(stru
- 			(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
- 		return 0;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_MicrocodeFanControl))
-+	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
- 		smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
- 
- 	crystal_clock_freq = smu7_get_xclk(hwmgr);
-@@ -367,7 +360,7 @@ static int smu7_thermal_initialize(struc
- *
- * @param    hwmgr The address of the hardware manager.
- */
--int smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr)
-+static void smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr)
- {
- 	uint32_t alert;
- 
-@@ -378,7 +371,7 @@ int smu7_thermal_enable_alert(struct pp_
- 			CG_THERMAL_INT, THERM_INT_MASK, alert);
- 
- 	/* send message to SMU to enable internal thermal interrupts */
--	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable);
-+	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Enable);
- }
- 
- /**
-@@ -396,7 +389,7 @@ int smu7_thermal_disable_alert(struct pp
- 			CG_THERMAL_INT, THERM_INT_MASK, alert);
- 
- 	/* send message to SMU to disable internal thermal interrupts */
--	return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable);
-+	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Disable);
- }
- 
- /**
-@@ -423,16 +416,14 @@ int smu7_thermal_stop_thermal_controller
- * @param    Result the last failure code
- * @return   result from set temperature range routine
- */
--static int tf_smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
-+static int smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
- {
- /* If the fantable setup has failed we could have disabled
-  * PHM_PlatformCaps_MicrocodeFanControl even after
-  * this function was included in the table.
-  * Make sure that we still think controlling the fan is OK.
- */
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_MicrocodeFanControl)) {
-+	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {
- 		smu7_fan_ctrl_start_smc_fan_control(hwmgr);
- 		smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
- 	}
-@@ -440,108 +431,34 @@ static int tf_smu7_thermal_start_smc_fan
- 	return 0;
- }
- 
--/**
--* Set temperature range for high and low alerts
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    pInput the pointer to input data
--* @param    pOutput the pointer to output data
--* @param    pStorage the pointer to temporary storage
--* @param    Result the last failure code
--* @return   result from set temperature range routine
--*/
--static int tf_smu7_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
-+int smu7_start_thermal_controller(struct pp_hwmgr *hwmgr,
-+				struct PP_TemperatureRange *range)
- {
--	struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
-+	int ret = 0;
- 
- 	if (range == NULL)
- 		return -EINVAL;
- 
--	return smu7_thermal_set_temperature_range(hwmgr, range->min, range->max);
--}
--
--/**
--* Programs one-time setting registers
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    pInput the pointer to input data
--* @param    pOutput the pointer to output data
--* @param    pStorage the pointer to temporary storage
--* @param    Result the last failure code
--* @return   result from initialize thermal controller routine
--*/
--static int tf_smu7_thermal_initialize(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
--{
--	return smu7_thermal_initialize(hwmgr);
--}
--
--/**
--* Enable high and low alerts
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    pInput the pointer to input data
--* @param    pOutput the pointer to output data
--* @param    pStorage the pointer to temporary storage
--* @param    Result the last failure code
--* @return   result from enable alert routine
--*/
--static int tf_smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
--{
--	return smu7_thermal_enable_alert(hwmgr);
--}
--
--/**
--* Disable high and low alerts
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    pInput the pointer to input data
--* @param    pOutput the pointer to output data
--* @param    pStorage the pointer to temporary storage
--* @param    Result the last failure code
--* @return   result from disable alert routine
--*/
--static int tf_smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
--{
--	return smu7_thermal_disable_alert(hwmgr);
--}
-+	smu7_thermal_initialize(hwmgr);
-+	ret = smu7_thermal_set_temperature_range(hwmgr, range->min, range->max);
-+	if (ret)
-+		return -EINVAL;
-+	smu7_thermal_enable_alert(hwmgr);
-+	ret = smum_thermal_avfs_enable(hwmgr);
-+	if (ret)
-+		return -EINVAL;
- 
--static const struct phm_master_table_item
--phm_thermal_start_thermal_controller_master_list[] = {
--	{ .tableFunction = tf_smu7_thermal_initialize },
--	{ .tableFunction = tf_smu7_thermal_set_temperature_range },
--	{ .tableFunction = tf_smu7_thermal_enable_alert },
--	{ .tableFunction = smum_thermal_avfs_enable },
- /* We should restrict performance levels to low before we halt the SMC.
-  * On the other hand we are still in boot state when we do this
-  * so it would be pointless.
-  * If this assumption changes we have to revisit this table.
-  */
--	{ .tableFunction = smum_thermal_setup_fan_table },
--	{ .tableFunction = tf_smu7_thermal_start_smc_fan_control },
--	{ }
--};
--
--static const struct phm_master_table_header
--phm_thermal_start_thermal_controller_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	phm_thermal_start_thermal_controller_master_list
--};
--
--static const struct phm_master_table_item
--phm_thermal_set_temperature_range_master_list[] = {
--	{ .tableFunction = tf_smu7_thermal_disable_alert },
--	{ .tableFunction = tf_smu7_thermal_set_temperature_range },
--	{ .tableFunction = tf_smu7_thermal_enable_alert },
--	{ }
--};
--
--static const struct phm_master_table_header
--phm_thermal_set_temperature_range_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	phm_thermal_set_temperature_range_master_list
--};
-+	smum_thermal_setup_fan_table(hwmgr);
-+	smu7_thermal_start_smc_fan_control(hwmgr);
-+	return 0;
-+}
-+
-+
- 
- int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
- {
-@@ -550,35 +467,3 @@ int smu7_thermal_ctrl_uninitialize_therm
- 	return 0;
- }
- 
--/**
--* Initializes the thermal controller related functions in the Hardware Manager structure.
--* @param    hwmgr The address of the hardware manager.
--* @exception Any error code from the low-level communication.
--*/
--int pp_smu7_thermal_initialize(struct pp_hwmgr *hwmgr)
--{
--	int result;
--
--	result = phm_construct_table(hwmgr,
--			&phm_thermal_set_temperature_range_master,
--			&(hwmgr->set_temperature_range));
--
--	if (!result) {
--		result = phm_construct_table(hwmgr,
--				&phm_thermal_start_thermal_controller_master,
--				&(hwmgr->start_thermal_controller));
--		if (result)
--			phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));
--	}
--
--	if (!result)
--		hwmgr->fan_ctrl_is_in_default_mode = true;
--	return result;
--}
--
--void pp_smu7_thermal_fini(struct pp_hwmgr *hwmgr)
--{
--	phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range));
--	phm_destroy_table(hwmgr, &(hwmgr->start_thermal_controller));
--	return;
--}
-\ No newline at end of file
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h	2017-12-14 06:39:58.473903608 +0100
-@@ -46,14 +46,13 @@ extern int smu7_fan_ctrl_set_default_mod
- extern int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
- extern int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
- extern int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
--extern int pp_smu7_thermal_initialize(struct pp_hwmgr *hwmgr);
--extern void pp_smu7_thermal_fini(struct pp_hwmgr *hwmgr);
- extern int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
- extern int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
- extern int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
- extern int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
--extern int smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr);
- extern int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr);
- extern int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
-+extern int smu7_start_thermal_controller(struct pp_hwmgr *hwmgr,
-+				struct PP_TemperatureRange *temperature_range);
- #endif
- 
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c	2017-12-14 06:39:58.474903609 +0100
-@@ -56,7 +56,7 @@
- 
- #define HBM_MEMORY_CHANNEL_WIDTH    128
- 
--uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
-+static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
- 
- #define MEM_FREQ_LOW_LATENCY        25000
- #define MEM_FREQ_HIGH_LATENCY       80000
-@@ -81,7 +81,7 @@ uint32_t channel_number[] = {1, 2, 0, 4,
- static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
- 		enum pp_clock_type type, uint32_t mask);
- 
--const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
-+static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
- 
- struct vega10_power_state *cast_phw_vega10_power_state(
- 				  struct pp_hw_power_state *hw_ps)
-@@ -201,9 +201,6 @@ static int vega10_set_features_platform_
- 				PHM_PlatformCaps_ControlVDDCI);
- 
- 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_TablelessHardwareInterface);
--
--	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- 			PHM_PlatformCaps_EnableSMU7ThermalManagement);
- 
- 	sys_info.size = sizeof(struct cgs_system_info);
-@@ -381,12 +378,10 @@ static void vega10_init_dpm_defaults(str
- 	if (!data->registry_data.socclk_dpm_key_disabled)
- 		data->smu_features[GNLD_DPM_SOCCLK].supported = true;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_UVDDPM))
-+	if (PP_CAP(PHM_PlatformCaps_UVDDPM))
- 		data->smu_features[GNLD_DPM_UVD].supported = true;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_VCEDPM))
-+	if (PP_CAP(PHM_PlatformCaps_VCEDPM))
- 		data->smu_features[GNLD_DPM_VCE].supported = true;
- 
- 	if (!data->registry_data.pcie_dpm_key_disabled)
-@@ -395,9 +390,8 @@ static void vega10_init_dpm_defaults(str
- 	if (!data->registry_data.dcefclk_dpm_key_disabled)
- 		data->smu_features[GNLD_DPM_DCEFCLK].supported = true;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_SclkDeepSleep) &&
--			data->registry_data.sclk_deep_sleep_support) {
-+	if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) &&
-+	    data->registry_data.sclk_deep_sleep_support) {
- 		data->smu_features[GNLD_DS_GFXCLK].supported = true;
- 		data->smu_features[GNLD_DS_SOCCLK].supported = true;
- 		data->smu_features[GNLD_DS_LCLK].supported = true;
-@@ -431,8 +425,8 @@ static void vega10_init_dpm_defaults(str
- 	if (data->registry_data.vr0hot_enabled)
- 		data->smu_features[GNLD_VR0HOT].supported = true;
- 
--	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetSmuVersion);
--	vega10_read_arg_from_smc(hwmgr->smumgr, &(data->smu_version));
-+	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
-+	vega10_read_arg_from_smc(hwmgr, &(data->smu_version));
- 		/* ACG firmware has major version 5 */
- 	if ((data->smu_version & 0xff000000) == 0x5000000)
- 		data->smu_features[GNLD_ACG].supported = true;
-@@ -497,8 +491,7 @@ static int vega10_get_evv_voltages(struc
- 
- 		if (!vega10_get_socclk_for_voltage_evv(hwmgr,
- 				table_info->vddc_lookup_table, vv_id, &sclk)) {
--			if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_ClockStretcher)) {
-+			if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) {
- 				for (j = 1; j < socclk_table->count; j++) {
- 					if (socclk_table->entries[j].clk == sclk &&
- 							socclk_table->entries[j].cks_enable == 0) {
-@@ -553,8 +546,7 @@ static void vega10_patch_with_vdd_leakag
- 	}
- 
- 	if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
--		pr_info("Voltage value looks like a Leakage ID \
--				but it's not patched\n");
-+		pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
- }
- 
- /**
-@@ -591,61 +583,37 @@ static int vega10_patch_clock_voltage_li
- static int vega10_patch_voltage_dependency_tables_with_lookup_table(
- 		struct pp_hwmgr *hwmgr)
- {
--	uint8_t entry_id;
--	uint8_t voltage_id;
-+	uint8_t entry_id, voltage_id;
-+	unsigned i;
- 	struct phm_ppt_v2_information *table_info =
- 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
--	struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table =
--			table_info->vdd_dep_on_socclk;
--	struct phm_ppt_v1_clock_voltage_dependency_table *gfxclk_table =
--			table_info->vdd_dep_on_sclk;
--	struct phm_ppt_v1_clock_voltage_dependency_table *dcefclk_table =
--			table_info->vdd_dep_on_dcefclk;
--	struct phm_ppt_v1_clock_voltage_dependency_table *pixclk_table =
--			table_info->vdd_dep_on_pixclk;
--	struct phm_ppt_v1_clock_voltage_dependency_table *dspclk_table =
--			table_info->vdd_dep_on_dispclk;
--	struct phm_ppt_v1_clock_voltage_dependency_table *phyclk_table =
--			table_info->vdd_dep_on_phyclk;
--	struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
--			table_info->vdd_dep_on_mclk;
- 	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
- 			table_info->mm_dep_table;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
-+			table_info->vdd_dep_on_mclk;
- 
--	for (entry_id = 0; entry_id < socclk_table->count; entry_id++) {
--		voltage_id = socclk_table->entries[entry_id].vddInd;
--		socclk_table->entries[entry_id].vddc =
--				table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
--	}
--
--	for (entry_id = 0; entry_id < gfxclk_table->count; entry_id++) {
--		voltage_id = gfxclk_table->entries[entry_id].vddInd;
--		gfxclk_table->entries[entry_id].vddc =
--				table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
--	}
--
--	for (entry_id = 0; entry_id < dcefclk_table->count; entry_id++) {
--		voltage_id = dcefclk_table->entries[entry_id].vddInd;
--		dcefclk_table->entries[entry_id].vddc =
--				table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
--	}
--
--	for (entry_id = 0; entry_id < pixclk_table->count; entry_id++) {
--		voltage_id = pixclk_table->entries[entry_id].vddInd;
--		pixclk_table->entries[entry_id].vddc =
--				table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
--	}
-+	for (i = 0; i < 6; i++) {
-+		struct phm_ppt_v1_clock_voltage_dependency_table *vdt;
-+		switch (i) {
-+			case 0: vdt = table_info->vdd_dep_on_socclk; break;
-+			case 1: vdt = table_info->vdd_dep_on_sclk; break;
-+			case 2: vdt = table_info->vdd_dep_on_dcefclk; break;
-+			case 3: vdt = table_info->vdd_dep_on_pixclk; break;
-+			case 4: vdt = table_info->vdd_dep_on_dispclk; break;
-+			case 5: vdt = table_info->vdd_dep_on_phyclk; break;
-+		}
- 
--	for (entry_id = 0; entry_id < dspclk_table->count; entry_id++) {
--		voltage_id = dspclk_table->entries[entry_id].vddInd;
--		dspclk_table->entries[entry_id].vddc =
--				table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
-+		for (entry_id = 0; entry_id < vdt->count; entry_id++) {
-+			voltage_id = vdt->entries[entry_id].vddInd;
-+			vdt->entries[entry_id].vddc =
-+					table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
-+		}
- 	}
- 
--	for (entry_id = 0; entry_id < phyclk_table->count; entry_id++) {
--		voltage_id = phyclk_table->entries[entry_id].vddInd;
--		phyclk_table->entries[entry_id].vddc =
--				table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
-+	for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
-+		voltage_id = mm_table->entries[entry_id].vddcInd;
-+		mm_table->entries[entry_id].vddc =
-+			table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
- 	}
- 
- 	for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
-@@ -660,11 +628,6 @@ static int vega10_patch_voltage_dependen
- 				table_info->vddmem_lookup_table->entries[voltage_id].us_vdd;
- 	}
- 
--	for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
--		voltage_id = mm_table->entries[entry_id].vddcInd;
--		mm_table->entries[entry_id].vddc =
--			table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
--	}
- 
- 	return 0;
- 
-@@ -737,18 +700,14 @@ static int vega10_set_private_data_based
- 			table_info->vdd_dep_on_mclk;
- 
- 	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
--		"VDD dependency on SCLK table is missing. \
--		This table is mandatory", return -EINVAL);
-+		"VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL);
- 	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
--		"VDD dependency on SCLK table is empty. \
--		This table is mandatory", return -EINVAL);
-+		"VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL);
- 
- 	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
--		"VDD dependency on MCLK table is missing. \
--		This table is mandatory", return -EINVAL);
-+		"VDD dependency on MCLK table is missing.  This table is mandatory", return -EINVAL);
- 	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
--		"VDD dependency on MCLK table is empty. \
--		This table is mandatory", return -EINVAL);
-+		"VDD dependency on MCLK table is empty.  This table is mandatory", return -EINVAL);
- 
- 	table_info->max_clock_voltage_on_ac.sclk =
- 		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
-@@ -789,6 +748,7 @@ static int vega10_hwmgr_backend_init(str
- 	uint32_t config_telemetry = 0;
- 	struct pp_atomfwctrl_voltage_table vol_table;
- 	struct cgs_system_info sys_info = {0};
-+	uint32_t reg;
- 
- 	data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
- 	if (data == NULL)
-@@ -838,8 +798,7 @@ static int vega10_hwmgr_backend_init(str
- 	}
- 
- 	 /* VDDCI_MEM */
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_ControlVDDCI)) {
-+	if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) {
- 		if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
- 				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
- 			data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO;
-@@ -896,6 +855,16 @@ static int vega10_hwmgr_backend_init(str
- 			advanceFanControlParameters.usFanPWMMinLimit *
- 			hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
- 
-+	reg = soc15_get_register_offset(DF_HWID, 0,
-+			mmDF_CS_AON0_DramBaseAddress0_BASE_IDX,
-+			mmDF_CS_AON0_DramBaseAddress0);
-+	data->mem_channels = (cgs_read_register(hwmgr->device, reg) &
-+			DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
-+			DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
-+	PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
-+			"Mem Channel Index Exceeded maximum!",
-+			return -EINVAL);
-+
- 	return result;
- }
- 
-@@ -959,7 +928,7 @@ static bool vega10_is_dpm_running(struct
- {
- 	uint32_t features_enabled;
- 
--	if (!vega10_get_smc_features(hwmgr->smumgr, &features_enabled)) {
-+	if (!vega10_get_smc_features(hwmgr, &features_enabled)) {
- 		if (features_enabled & SMC_DPM_FEATURES)
- 			return true;
- 	}
-@@ -1198,6 +1167,8 @@ static void vega10_setup_default_single_
- {
- 	int i;
- 
-+	dpm_table->count = 0;
-+
- 	for (i = 0; i < dep_table->count; i++) {
- 		if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <=
- 				dep_table->entries[i].clk) {
-@@ -1306,10 +1277,6 @@ static int vega10_setup_default_dpm_tabl
- 			return -EINVAL);
- 
- 	/* Initialize Sclk DPM table based on allow Sclk values */
--	data->dpm_table.soc_table.count = 0;
--	data->dpm_table.gfx_table.count = 0;
--	data->dpm_table.dcef_table.count = 0;
--
- 	dpm_table = &(data->dpm_table.soc_table);
- 	vega10_setup_default_single_dpm_table(hwmgr,
- 			dpm_table,
-@@ -1411,10 +1378,8 @@ static int vega10_setup_default_dpm_tabl
- 	memcpy(&(data->golden_dpm_table), &(data->dpm_table),
- 			sizeof(struct vega10_dpm_table));
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_ODNinACSupport) ||
--		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_ODNinDCSupport)) {
-+	if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) ||
-+	    PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) {
- 		data->odn_dpm_table.odn_core_clock_dpm_levels.
- 		number_of_performance_levels = data->dpm_table.gfx_table.count;
- 		for (i = 0; i < data->dpm_table.gfx_table.count; i++) {
-@@ -1818,7 +1783,7 @@ static int vega10_populate_all_memory_le
- 	struct vega10_single_dpm_table *dpm_table =
- 			&(data->dpm_table.mem_table);
- 	int result = 0;
--	uint32_t i, j, reg, mem_channels;
-+	uint32_t i, j;
- 
- 	for (i = 0; i < dpm_table->count; i++) {
- 		result = vega10_populate_single_memory_level(hwmgr,
-@@ -1842,16 +1807,10 @@ static int vega10_populate_all_memory_le
- 		i++;
- 	}
- 
--	reg = soc15_get_register_offset(DF_HWID, 0,
--			mmDF_CS_AON0_DramBaseAddress0_BASE_IDX,
--			mmDF_CS_AON0_DramBaseAddress0);
--	mem_channels = (cgs_read_register(hwmgr->device, reg) &
--			DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
--			DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
--	pp_table->NumMemoryChannels = cpu_to_le16(mem_channels);
-+	pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
- 	pp_table->MemoryChannelWidth =
--			cpu_to_le16(HBM_MEMORY_CHANNEL_WIDTH *
--					channel_number[mem_channels]);
-+			(uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
-+					channel_number[data->mem_channels]);
- 
- 	pp_table->LowestUclkReservedForUlv =
- 			(uint8_t)(data->lowest_uclk_reserved_for_ulv);
-@@ -2311,21 +2270,21 @@ static int vega10_acg_enable(struct pp_h
- 	uint32_t agc_btc_response;
- 
- 	if (data->smu_features[GNLD_ACG].supported) {
--		if (0 == vega10_enable_smc_features(hwmgr->smumgr, true,
-+		if (0 == vega10_enable_smc_features(hwmgr, true,
- 					data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap))
- 			data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;
- 
--		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_InitializeAcg);
-+		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg);
- 
--		smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgBtc);
--		vega10_read_arg_from_smc(hwmgr->smumgr, &agc_btc_response);
-+		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc);
-+		vega10_read_arg_from_smc(hwmgr, &agc_btc_response);
- 
- 		if (1 == agc_btc_response) {
- 			if (1 == data->acg_loop_state)
--				smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgInClosedLoop);
-+				smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop);
- 			else if (2 == data->acg_loop_state)
--				smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgInOpenLoop);
--			if (0 == vega10_enable_smc_features(hwmgr->smumgr, true,
-+				smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop);
-+			if (0 == vega10_enable_smc_features(hwmgr, true,
- 				data->smu_features[GNLD_ACG].smu_feature_bitmap))
- 					data->smu_features[GNLD_ACG].enabled = true;
- 		} else {
-@@ -2342,13 +2301,11 @@ static int vega10_acg_disable(struct pp_
- 	struct vega10_hwmgr *data =
- 			(struct vega10_hwmgr *)(hwmgr->backend);
- 
--	if (data->smu_features[GNLD_ACG].supported) {
--		if (data->smu_features[GNLD_ACG].enabled) {
--		if (0 == vega10_enable_smc_features(hwmgr->smumgr, false,
--				data->smu_features[GNLD_ACG].smu_feature_bitmap))
-+	if (data->smu_features[GNLD_ACG].supported && 
-+	    data->smu_features[GNLD_ACG].enabled)
-+		if (!vega10_enable_smc_features(hwmgr, false,
-+			data->smu_features[GNLD_ACG].smu_feature_bitmap))
- 			data->smu_features[GNLD_ACG].enabled = false;
--		}
--	}
- 
- 	return 0;
- }
-@@ -2363,9 +2320,8 @@ static int vega10_populate_gpio_paramete
- 
- 	result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);
- 	if (!result) {
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_RegulatorHot) &&
--				(data->registry_data.regulator_hot_gpio_support)) {
-+		if (PP_CAP(PHM_PlatformCaps_RegulatorHot) &&
-+		    data->registry_data.regulator_hot_gpio_support) {
- 			pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio;
- 			pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity;
- 			pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio;
-@@ -2377,9 +2333,8 @@ static int vega10_populate_gpio_paramete
- 			pp_table->VR1HotPolarity = 0;
- 		}
- 
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_AutomaticDCTransition) &&
--				(data->registry_data.ac_dc_switch_gpio_support)) {
-+		if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) &&
-+		    data->registry_data.ac_dc_switch_gpio_support) {
- 			pp_table->AcDcGpio = gpio_params.ucAcDcGpio;
- 			pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity;
- 		} else {
-@@ -2398,16 +2353,16 @@ static int vega10_avfs_enable(struct pp_
- 
- 	if (data->smu_features[GNLD_AVFS].supported) {
- 		if (enable) {
--			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 					true,
- 					data->smu_features[GNLD_AVFS].smu_feature_bitmap),
- 					"[avfs_control] Attempt to Enable AVFS feature Failed!",
- 					return -1);
- 			data->smu_features[GNLD_AVFS].enabled = true;
- 		} else {
--			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 					false,
--					data->smu_features[GNLD_AVFS].smu_feature_id),
-+					data->smu_features[GNLD_AVFS].smu_feature_bitmap),
- 					"[avfs_control] Attempt to Disable AVFS feature Failed!",
- 					return -1);
- 			data->smu_features[GNLD_AVFS].enabled = false;
-@@ -2428,15 +2383,15 @@ static int vega10_populate_and_upload_av
- 	struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
- 	AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
- 
--	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ReadSerialNumTop32);
--	vega10_read_arg_from_smc(hwmgr->smumgr, &top32);
-+	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
-+	vega10_read_arg_from_smc(hwmgr, &top32);
- 
--	smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ReadSerialNumBottom32);
--	vega10_read_arg_from_smc(hwmgr->smumgr, &bottom32);
-+	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
-+	vega10_read_arg_from_smc(hwmgr, &bottom32);
- 
- 	serial_number = ((uint64_t)bottom32 << 32) | top32;
- 
--	if (pp_override_get_default_fuse_value(serial_number, vega10_fuses_default, &fuse) == 0) {
-+	if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) {
- 		avfs_fuse_table->VFT0_b  = fuse.VFT0_b;
- 		avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1;
- 		avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2;
-@@ -2446,7 +2401,7 @@ static int vega10_populate_and_upload_av
- 		avfs_fuse_table->VFT2_b  = fuse.VFT2_b;
- 		avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
- 		avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
--		result = vega10_copy_table_to_smc(hwmgr->smumgr,
-+		result = vega10_copy_table_to_smc(hwmgr,
- 			(uint8_t *)avfs_fuse_table, AVFSFUSETABLE);
- 		PP_ASSERT_WITH_CODE(!result,
- 			"Failed to upload FuseOVerride!",
-@@ -2585,14 +2540,14 @@ static int vega10_init_smc_table(struct
- 		data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
- 		data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
- 		if (0 != boot_up_values.usVddc) {
--			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+			smum_send_msg_to_smc_with_parameter(hwmgr,
- 						PPSMC_MSG_SetFloorSocVoltage,
- 						(boot_up_values.usVddc * 4));
- 			data->vbios_boot_state.bsoc_vddc_lock = true;
- 		} else {
- 			data->vbios_boot_state.bsoc_vddc_lock = false;
- 		}
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetMinDeepSleepDcefclk,
- 			(uint32_t)(data->vbios_boot_state.dcef_clock / 100));
- 	}
-@@ -2618,7 +2573,7 @@ static int vega10_init_smc_table(struct
- 
- 	vega10_populate_and_upload_avfs_fuse_override(hwmgr);
- 
--	result = vega10_copy_table_to_smc(hwmgr->smumgr,
-+	result = vega10_copy_table_to_smc(hwmgr,
- 			(uint8_t *)pp_table, PPTABLE);
- 	PP_ASSERT_WITH_CODE(!result,
- 			"Failed to upload PPtable!", return result);
-@@ -2641,7 +2596,7 @@ static int vega10_enable_thermal_protect
- 			pr_info("THERMAL Feature Already enabled!");
- 
- 		PP_ASSERT_WITH_CODE(
--				!vega10_enable_smc_features(hwmgr->smumgr,
-+				!vega10_enable_smc_features(hwmgr,
- 				true,
- 				data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
- 				"Enable THERMAL Feature Failed!",
-@@ -2661,7 +2616,7 @@ static int vega10_disable_thermal_protec
- 			pr_info("THERMAL Feature Already disabled!");
- 
- 		PP_ASSERT_WITH_CODE(
--				!vega10_enable_smc_features(hwmgr->smumgr,
-+				!vega10_enable_smc_features(hwmgr,
- 				false,
- 				data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
- 				"disable THERMAL Feature Failed!",
-@@ -2677,11 +2632,10 @@ static int vega10_enable_vrhot_feature(s
- 	struct vega10_hwmgr *data =
- 			(struct vega10_hwmgr *)(hwmgr->backend);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_RegulatorHot)) {
-+	if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
- 		if (data->smu_features[GNLD_VR0HOT].supported) {
- 			PP_ASSERT_WITH_CODE(
--					!vega10_enable_smc_features(hwmgr->smumgr,
-+					!vega10_enable_smc_features(hwmgr,
- 					true,
- 					data->smu_features[GNLD_VR0HOT].smu_feature_bitmap),
- 					"Attempt to Enable VR0 Hot feature Failed!",
-@@ -2690,7 +2644,7 @@ static int vega10_enable_vrhot_feature(s
- 		} else {
- 			if (data->smu_features[GNLD_VR1HOT].supported) {
- 				PP_ASSERT_WITH_CODE(
--						!vega10_enable_smc_features(hwmgr->smumgr,
-+						!vega10_enable_smc_features(hwmgr,
- 						true,
- 						data->smu_features[GNLD_VR1HOT].smu_feature_bitmap),
- 						"Attempt to Enable VR0 Hot feature Failed!",
-@@ -2708,7 +2662,7 @@ static int vega10_enable_ulv(struct pp_h
- 			(struct vega10_hwmgr *)(hwmgr->backend);
- 
- 	if (data->registry_data.ulv_support) {
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				true, data->smu_features[GNLD_ULV].smu_feature_bitmap),
- 				"Enable ULV Feature Failed!",
- 				return -1);
-@@ -2724,7 +2678,7 @@ static int vega10_disable_ulv(struct pp_
- 			(struct vega10_hwmgr *)(hwmgr->backend);
- 
- 	if (data->registry_data.ulv_support) {
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				false, data->smu_features[GNLD_ULV].smu_feature_bitmap),
- 				"disable ULV Feature Failed!",
- 				return -EINVAL);
-@@ -2740,7 +2694,7 @@ static int vega10_enable_deep_sleep_mast
- 			(struct vega10_hwmgr *)(hwmgr->backend);
- 
- 	if (data->smu_features[GNLD_DS_GFXCLK].supported) {
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
- 				"Attempt to Enable DS_GFXCLK Feature Failed!",
- 				return -EINVAL);
-@@ -2748,7 +2702,7 @@ static int vega10_enable_deep_sleep_mast
- 	}
- 
- 	if (data->smu_features[GNLD_DS_SOCCLK].supported) {
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
- 				"Attempt to Enable DS_SOCCLK Feature Failed!",
- 				return -EINVAL);
-@@ -2756,7 +2710,7 @@ static int vega10_enable_deep_sleep_mast
- 	}
- 
- 	if (data->smu_features[GNLD_DS_LCLK].supported) {
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
- 				"Attempt to Enable DS_LCLK Feature Failed!",
- 				return -EINVAL);
-@@ -2764,7 +2718,7 @@ static int vega10_enable_deep_sleep_mast
- 	}
- 
- 	if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
- 				"Attempt to Enable DS_DCEFCLK Feature Failed!",
- 				return -EINVAL);
-@@ -2780,7 +2734,7 @@ static int vega10_disable_deep_sleep_mas
- 			(struct vega10_hwmgr *)(hwmgr->backend);
- 
- 	if (data->smu_features[GNLD_DS_GFXCLK].supported) {
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
- 				"Attempt to disable DS_GFXCLK Feature Failed!",
- 				return -EINVAL);
-@@ -2788,7 +2742,7 @@ static int vega10_disable_deep_sleep_mas
- 	}
- 
- 	if (data->smu_features[GNLD_DS_SOCCLK].supported) {
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
- 				"Attempt to disable DS_ Feature Failed!",
- 				return -EINVAL);
-@@ -2796,7 +2750,7 @@ static int vega10_disable_deep_sleep_mas
- 	}
- 
- 	if (data->smu_features[GNLD_DS_LCLK].supported) {
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
- 				"Attempt to disable DS_LCLK Feature Failed!",
- 				return -EINVAL);
-@@ -2804,7 +2758,7 @@ static int vega10_disable_deep_sleep_mas
- 	}
- 
- 	if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
- 				"Attempt to disable DS_DCEFCLK Feature Failed!",
- 				return -EINVAL);
-@@ -2822,7 +2776,7 @@ static int vega10_stop_dpm(struct pp_hwm
- 
- 
- 	if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
- 		"Attempt to disable LED DPM feature failed!", return -EINVAL);
- 		data->smu_features[GNLD_LED_DISPLAY].enabled = false;
-@@ -2840,7 +2794,7 @@ static int vega10_stop_dpm(struct pp_hwm
- 		}
- 	}
- 
--	vega10_enable_smc_features(hwmgr->smumgr, false, feature_mask);
-+	vega10_enable_smc_features(hwmgr, false, feature_mask);
- 
- 	return 0;
- }
-@@ -2870,7 +2824,7 @@ static int vega10_start_dpm(struct pp_hw
- 		}
- 	}
- 
--	if (vega10_enable_smc_features(hwmgr->smumgr,
-+	if (vega10_enable_smc_features(hwmgr,
- 			true, feature_mask)) {
- 		for (i = 0; i < GNLD_DPM_MAX; i++) {
- 			if (data->smu_features[i].smu_feature_bitmap &
-@@ -2880,22 +2834,21 @@ static int vega10_start_dpm(struct pp_hw
- 	}
- 
- 	if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
- 		"Attempt to Enable LED DPM feature Failed!", return -EINVAL);
- 		data->smu_features[GNLD_LED_DISPLAY].enabled = true;
- 	}
- 
- 	if (data->vbios_boot_state.bsoc_vddc_lock) {
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 						PPSMC_MSG_SetFloorSocVoltage, 0);
- 		data->vbios_boot_state.bsoc_vddc_lock = false;
- 	}
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_Falcon_QuickTransition)) {
-+	if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) {
- 		if (data->smu_features[GNLD_ACDC].supported) {
--			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 					true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
- 					"Attempt to Enable DS_GFXCLK Feature Failed!",
- 					return -1);
-@@ -2912,13 +2865,13 @@ static int vega10_enable_dpm_tasks(struc
- 			(struct vega10_hwmgr *)(hwmgr->backend);
- 	int tmp_result, result = 0;
- 
--	tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_ConfigureTelemetry, data->config_telemetry);
- 	PP_ASSERT_WITH_CODE(!tmp_result,
- 			"Failed to configure telemetry!",
- 			return tmp_result);
- 
--	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_NumOfDisplays, 0);
- 
- 	tmp_result = (!vega10_is_dpm_running(hwmgr)) ? 0 : -1;
-@@ -2926,6 +2879,15 @@ static int vega10_enable_dpm_tasks(struc
- 			"DPM is already running right , skipping re-enablement!",
- 			return 0);
- 
-+	if ((data->smu_version == 0x001c2c00) ||
-+			(data->smu_version == 0x001c2d00)) {
-+		tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_UpdatePkgPwrPidAlpha, 1);
-+		PP_ASSERT_WITH_CODE(!tmp_result,
-+				"Failed to set package power PID!",
-+				return tmp_result);
-+	}
-+
- 	tmp_result = vega10_construct_voltage_tables(hwmgr);
- 	PP_ASSERT_WITH_CODE(!tmp_result,
- 			"Failed to contruct voltage tables!",
-@@ -2936,8 +2898,7 @@ static int vega10_enable_dpm_tasks(struc
- 			"Failed to initialize SMC table!",
- 			result = tmp_result);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_ThermalController)) {
-+	if (PP_CAP(PHM_PlatformCaps_ThermalController)) {
- 		tmp_result = vega10_enable_thermal_protection(hwmgr);
- 		PP_ASSERT_WITH_CODE(!tmp_result,
- 				"Failed to enable thermal protection!",
-@@ -3172,8 +3133,9 @@ static int vega10_apply_state_adjust_rul
- 	minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
- 	minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_StablePState)) {
-+	if (PP_CAP(PHM_PlatformCaps_StablePState)) {
-+		stable_pstate_sclk_dpm_percentage =
-+			data->registry_data.stable_pstate_sclk_dpm_percentage;
- 		PP_ASSERT_WITH_CODE(
- 			data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
- 			data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
-@@ -3238,10 +3200,8 @@ static int vega10_apply_state_adjust_rul
- 	disable_mclk_switching_for_frame_lock = phm_cap_enabled(
- 				    hwmgr->platform_descriptor.platformCaps,
- 				    PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
--	disable_mclk_switching_for_vr = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_DisableMclkSwitchForVR);
--	force_mclk_high = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_ForceMclkHigh);
-+	disable_mclk_switching_for_vr = PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
-+	force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
- 
- 	disable_mclk_switching = (info.display_count > 1) ||
- 				    disable_mclk_switching_for_frame_lock ||
-@@ -3292,8 +3252,7 @@ static int vega10_apply_state_adjust_rul
- 					vega10_ps->performance_levels[1].mem_clock;
- 	}
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_StablePState)) {
-+	if (PP_CAP(PHM_PlatformCaps_StablePState)) {
- 		for (i = 0; i < vega10_ps->performance_level_count; i++) {
- 			vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk;
- 			vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
-@@ -3325,10 +3284,8 @@ static int vega10_find_dpm_states_clocks
- 
- 	data->need_update_dpm_table = 0;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_ODNinACSupport) ||
--		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--				PHM_PlatformCaps_ODNinDCSupport)) {
-+	if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) ||
-+	    PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) {
- 		for (i = 0; i < sclk_table->count; i++) {
- 			if (sclk == sclk_table->dpm_levels[i].value)
- 				break;
-@@ -3412,10 +3369,8 @@ static int vega10_populate_and_upload_sc
- 	uint32_t dpm_count, clock_percent;
- 	uint32_t i;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_ODNinACSupport) ||
--		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_ODNinDCSupport)) {
-+	if (PP_CAP(PHM_PlatformCaps_ODNinACSupport) ||
-+	    PP_CAP(PHM_PlatformCaps_ODNinDCSupport)) {
- 
- 		if (!data->need_update_dpm_table &&
- 			!data->apply_optimized_settings &&
-@@ -3456,8 +3411,7 @@ static int vega10_populate_and_upload_sc
- 					DPMTABLE_OD_UPDATE_SCLK)) {
- 			result = vega10_populate_all_graphic_levels(hwmgr);
- 			PP_ASSERT_WITH_CODE(!result,
--					"Failed to populate SCLK during \
--					PopulateNewDPMClocksStates Function!",
-+					"Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
- 					return result);
- 		}
- 
-@@ -3466,8 +3420,7 @@ static int vega10_populate_and_upload_sc
- 					DPMTABLE_OD_UPDATE_MCLK)){
- 			result = vega10_populate_all_memory_levels(hwmgr);
- 			PP_ASSERT_WITH_CODE(!result,
--					"Failed to populate MCLK during \
--					PopulateNewDPMClocksStates Function!",
-+					"Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
- 					return result);
- 		}
- 	} else {
-@@ -3480,10 +3433,8 @@ static int vega10_populate_and_upload_sc
- 				dpm_table->
- 				gfx_table.dpm_levels[dpm_table->gfx_table.count - 1].
- 				value = sclk;
--				if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--						PHM_PlatformCaps_OD6PlusinACSupport) ||
--					phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--							PHM_PlatformCaps_OD6PlusinDCSupport)) {
-+				if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
-+				    PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
- 					/* Need to do calculation based on the golden DPM table
- 					 * as the Heatmap GPU Clock axis is also based on
- 					 * the default values
-@@ -3537,10 +3488,8 @@ static int vega10_populate_and_upload_sc
- 			mem_table.dpm_levels[dpm_table->mem_table.count - 1].
- 			value = mclk;
- 
--			if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--					PHM_PlatformCaps_OD6PlusinACSupport) ||
--				phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--						PHM_PlatformCaps_OD6PlusinDCSupport)) {
-+			if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
-+			    PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
- 
- 				PP_ASSERT_WITH_CODE(
- 					golden_dpm_table->mem_table.dpm_levels
-@@ -3588,8 +3537,7 @@ static int vega10_populate_and_upload_sc
- 			data->apply_optimized_settings) {
- 			result = vega10_populate_all_graphic_levels(hwmgr);
- 			PP_ASSERT_WITH_CODE(!result,
--					"Failed to populate SCLK during \
--					PopulateNewDPMClocksStates Function!",
-+					"Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
- 					return result);
- 		}
- 
-@@ -3597,8 +3545,7 @@ static int vega10_populate_and_upload_sc
- 				(DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
- 			result = vega10_populate_all_memory_levels(hwmgr);
- 			PP_ASSERT_WITH_CODE(!result,
--					"Failed to populate MCLK during \
--					PopulateNewDPMClocksStates Function!",
-+					"Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
- 					return result);
- 		}
- 	}
-@@ -3732,7 +3679,7 @@ static int vega10_upload_dpm_bootup_leve
- 		if (data->smc_state_table.gfx_boot_level !=
- 				data->dpm_table.gfx_table.dpm_state.soft_min_level) {
- 				PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
--				hwmgr->smumgr,
-+				hwmgr,
- 				PPSMC_MSG_SetSoftMinGfxclkByIndex,
- 				data->smc_state_table.gfx_boot_level),
- 				"Failed to set soft min sclk index!",
-@@ -3748,14 +3695,14 @@ static int vega10_upload_dpm_bootup_leve
- 			if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) {
- 				socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
- 				PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
--							hwmgr->smumgr,
-+							hwmgr,
- 						PPSMC_MSG_SetSoftMinSocclkByIndex,
- 						socclk_idx),
- 						"Failed to set soft min uclk index!",
- 						return -EINVAL);
- 			} else {
- 				PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
--						hwmgr->smumgr,
-+						hwmgr,
- 						PPSMC_MSG_SetSoftMinUclkByIndex,
- 						data->smc_state_table.mem_boot_level),
- 						"Failed to set soft min uclk index!",
-@@ -3780,7 +3727,7 @@ static int vega10_upload_dpm_max_level(s
- 		if (data->smc_state_table.gfx_max_level !=
- 				data->dpm_table.gfx_table.dpm_state.soft_max_level) {
- 				PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
--				hwmgr->smumgr,
-+				hwmgr,
- 				PPSMC_MSG_SetSoftMaxGfxclkByIndex,
- 				data->smc_state_table.gfx_max_level),
- 				"Failed to set soft max sclk index!",
-@@ -3794,7 +3741,7 @@ static int vega10_upload_dpm_max_level(s
- 		if (data->smc_state_table.mem_max_level !=
- 				data->dpm_table.mem_table.dpm_state.soft_max_level) {
- 				PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
--				hwmgr->smumgr,
-+				hwmgr,
- 				PPSMC_MSG_SetSoftMaxUclkByIndex,
- 				data->smc_state_table.mem_max_level),
- 				"Failed to set soft max mclk index!",
-@@ -3853,7 +3800,7 @@ int vega10_enable_disable_vce_dpm(struct
- 			(struct vega10_hwmgr *)(hwmgr->backend);
- 
- 	if (data->smu_features[GNLD_DPM_VCE].supported) {
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				enable,
- 				data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
- 				"Attempt to Enable/Disable DPM VCE Failed!",
-@@ -3871,9 +3818,8 @@ static int vega10_update_sclk_threshold(
- 	int result = 0;
- 	uint32_t low_sclk_interrupt_threshold = 0;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_SclkThrottleLowNotification)
--		&& (hwmgr->gfx_arbiter.sclk_threshold !=
-+	if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
-+	    (hwmgr->gfx_arbiter.sclk_threshold !=
- 				data->low_sclk_interrupt_threshold)) {
- 		data->low_sclk_interrupt_threshold =
- 				hwmgr->gfx_arbiter.sclk_threshold;
-@@ -3884,7 +3830,7 @@ static int vega10_update_sclk_threshold(
- 				cpu_to_le32(low_sclk_interrupt_threshold);
- 
- 		/* This message will also enable SmcToHost Interrupt */
--		result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		result = smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetLowGfxclkInterruptThreshold,
- 				(uint32_t)low_sclk_interrupt_threshold);
- 	}
-@@ -3920,7 +3866,7 @@ static int vega10_set_power_state_tasks(
- 			"Failed to update SCLK threshold!",
- 			result = tmp_result);
- 
--	result = vega10_copy_table_to_smc(hwmgr->smumgr,
-+	result = vega10_copy_table_to_smc(hwmgr,
- 			(uint8_t *)pp_table, PPTABLE);
- 	PP_ASSERT_WITH_CODE(!result,
- 			"Failed to upload PPtable!", return result);
-@@ -3931,7 +3877,7 @@ static int vega10_set_power_state_tasks(
- 	return 0;
- }
- 
--static int vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
-+static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
- {
- 	struct pp_power_state *ps;
- 	struct vega10_power_state *vega10_ps;
-@@ -3953,7 +3899,7 @@ static int vega10_dpm_get_sclk(struct pp
- 				[vega10_ps->performance_level_count - 1].gfx_clock;
- }
- 
--static int vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
-+static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
- {
- 	struct pp_power_state *ps;
- 	struct vega10_power_state *vega10_ps;
-@@ -3980,12 +3926,12 @@ static int vega10_get_gpu_power(struct p
- {
- 	uint32_t value;
- 
--	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
-+	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- 			PPSMC_MSG_GetCurrPkgPwr),
- 			"Failed to get current package power!",
- 			return -EINVAL);
- 
--	vega10_read_arg_from_smc(hwmgr->smumgr, &value);
-+	vega10_read_arg_from_smc(hwmgr, &value);
- 	/* power value is an integer */
- 	query->average_gpu_power = value << 8;
- 
-@@ -4002,25 +3948,25 @@ static int vega10_read_sensor(struct pp_
- 
- 	switch (idx) {
- 	case AMDGPU_PP_SENSOR_GFX_SCLK:
--		ret = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetCurrentGfxclkIndex);
-+		ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
- 		if (!ret) {
--			vega10_read_arg_from_smc(hwmgr->smumgr, &sclk_idx);
-+			vega10_read_arg_from_smc(hwmgr, &sclk_idx);
- 			*((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value;
- 			*size = 4;
- 		}
- 		break;
- 	case AMDGPU_PP_SENSOR_GFX_MCLK:
--		ret = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetCurrentUclkIndex);
-+		ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
- 		if (!ret) {
--			vega10_read_arg_from_smc(hwmgr->smumgr, &mclk_idx);
-+			vega10_read_arg_from_smc(hwmgr, &mclk_idx);
- 			*((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
- 			*size = 4;
- 		}
- 		break;
- 	case AMDGPU_PP_SENSOR_GPU_LOAD:
--		ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetAverageGfxActivity, 0);
-+		ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
- 		if (!ret) {
--			vega10_read_arg_from_smc(hwmgr->smumgr, &activity_percent);
-+			vega10_read_arg_from_smc(hwmgr, &activity_percent);
- 			*((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
- 			*size = 4;
- 		}
-@@ -4055,7 +4001,7 @@ static int vega10_read_sensor(struct pp_
- static int vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
- 		bool has_disp)
- {
--	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	return smum_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_SetUclkFastSwitch,
- 			has_disp ? 0 : 1);
- }
-@@ -4090,7 +4036,7 @@ int vega10_display_clock_voltage_request
- 
- 	if (!result) {
- 		clk_request = (clk_freq << 16) | clk_select;
--		result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		result = smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_RequestDisplayClockByFreq,
- 				clk_request);
- 	}
-@@ -4160,7 +4106,7 @@ static int vega10_notify_smc_display_con
- 		clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value;
- 		if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
- 			PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
--					hwmgr->smumgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
-+					hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
- 					min_clocks.dcefClockInSR /100),
- 					"Attempt to set divider for DCEFCLK Failed!",);
- 		} else {
-@@ -4172,7 +4118,7 @@ static int vega10_notify_smc_display_con
- 
- 	if (min_clocks.memoryClock != 0) {
- 		idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx);
-+		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx);
- 		data->dpm_table.mem_table.dpm_state.soft_min_level= idx;
- 	}
- 
-@@ -4275,28 +4221,23 @@ static int vega10_get_profiling_clk_mask
- 	return 0;
- }
- 
--static int vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
-+static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
- {
--	int result = 0;
--
- 	switch (mode) {
- 	case AMD_FAN_CTRL_NONE:
--		result = vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
-+		vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
- 		break;
- 	case AMD_FAN_CTRL_MANUAL:
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_MicrocodeFanControl))
--			result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
-+		if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
-+			vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
- 		break;
- 	case AMD_FAN_CTRL_AUTO:
--		result = vega10_fan_ctrl_set_static_mode(hwmgr, mode);
--		if (!result)
--			result = vega10_fan_ctrl_start_smc_fan_control(hwmgr);
-+		if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
-+			vega10_fan_ctrl_start_smc_fan_control(hwmgr);
- 		break;
- 	default:
- 		break;
- 	}
--	return result;
- }
- 
- static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
-@@ -4306,51 +4247,16 @@ static int vega10_dpm_force_dpm_level(st
- 	uint32_t sclk_mask = 0;
- 	uint32_t mclk_mask = 0;
- 	uint32_t soc_mask = 0;
--	uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
--					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
--					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
--					AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
--
--	if (level == hwmgr->dpm_level)
--		return ret;
--
--	if (!(hwmgr->dpm_level & profile_mode_mask)) {
--		/* enter profile mode, save current level, disable gfx cg*/
--		if (level & profile_mode_mask) {
--			hwmgr->saved_dpm_level = hwmgr->dpm_level;
--			cgs_set_clockgating_state(hwmgr->device,
--						AMD_IP_BLOCK_TYPE_GFX,
--						AMD_CG_STATE_UNGATE);
--		}
--	} else {
--		/* exit profile mode, restore level, enable gfx cg*/
--		if (!(level & profile_mode_mask)) {
--			if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
--				level = hwmgr->saved_dpm_level;
--			cgs_set_clockgating_state(hwmgr->device,
--					AMD_IP_BLOCK_TYPE_GFX,
--					AMD_CG_STATE_GATE);
--		}
--	}
- 
- 	switch (level) {
- 	case AMD_DPM_FORCED_LEVEL_HIGH:
- 		ret = vega10_force_dpm_highest(hwmgr);
--		if (ret)
--			return ret;
--		hwmgr->dpm_level = level;
- 		break;
- 	case AMD_DPM_FORCED_LEVEL_LOW:
- 		ret = vega10_force_dpm_lowest(hwmgr);
--		if (ret)
--			return ret;
--		hwmgr->dpm_level = level;
- 		break;
- 	case AMD_DPM_FORCED_LEVEL_AUTO:
- 		ret = vega10_unforce_dpm_levels(hwmgr);
--		if (ret)
--			return ret;
--		hwmgr->dpm_level = level;
- 		break;
- 	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
- 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
-@@ -4359,27 +4265,25 @@ static int vega10_dpm_force_dpm_level(st
- 		ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
- 		if (ret)
- 			return ret;
--		hwmgr->dpm_level = level;
- 		vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
- 		vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
- 		break;
- 	case AMD_DPM_FORCED_LEVEL_MANUAL:
--		hwmgr->dpm_level = level;
--		break;
- 	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
- 	default:
- 		break;
- 	}
- 
--	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->saved_dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
--		vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
--	else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->saved_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
--		vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
--
--	return 0;
-+	if (!ret) {
-+		if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
-+			vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
-+		else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
-+			vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
-+	}
-+	return ret;
- }
- 
--static int vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
-+static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
- {
- 	struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
- 
-@@ -4624,7 +4528,7 @@ static int vega10_force_clock_level(stru
- 	struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
- 	int i;
- 
--	if (hwmgr->dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
-+	if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
- 				AMD_DPM_FORCED_LEVEL_LOW |
- 				AMD_DPM_FORCED_LEVEL_HIGH))
- 		return -EINVAL;
-@@ -4697,11 +4601,11 @@ static int vega10_print_clock_levels(str
- 		if (data->registry_data.sclk_dpm_key_disabled)
- 			break;
- 
--		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_GetCurrentGfxclkIndex),
- 				"Attempt to get current sclk index Failed!",
- 				return -1);
--		PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
- 				&now),
- 				"Attempt to read sclk index Failed!",
- 				return -1);
-@@ -4715,11 +4619,11 @@ static int vega10_print_clock_levels(str
- 		if (data->registry_data.mclk_dpm_key_disabled)
- 			break;
- 
--		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_GetCurrentUclkIndex),
- 				"Attempt to get current mclk index Failed!",
- 				return -1);
--		PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
- 				&now),
- 				"Attempt to read mclk index Failed!",
- 				return -1);
-@@ -4730,20 +4634,20 @@ static int vega10_print_clock_levels(str
- 					(i == now) ? "*" : "");
- 		break;
- 	case PP_PCIE:
--		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_GetCurrentLinkIndex),
- 				"Attempt to get current mclk index Failed!",
- 				return -1);
--		PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
- 				&now),
- 				"Attempt to read mclk index Failed!",
- 				return -1);
- 
- 		for (i = 0; i < pcie_table->count; i++)
- 			size += sprintf(buf + size, "%d: %s %s\n", i,
--					(pcie_table->pcie_gen[i] == 0) ? "2.5GB, x1" :
--					(pcie_table->pcie_gen[i] == 1) ? "5.0GB, x16" :
--					(pcie_table->pcie_gen[i] == 2) ? "8.0GB, x16" : "",
-+					(pcie_table->pcie_gen[i] == 0) ? "2.5GT/s, x1" :
-+					(pcie_table->pcie_gen[i] == 1) ? "5.0GT/s, x16" :
-+					(pcie_table->pcie_gen[i] == 2) ? "8.0GT/s, x16" : "",
- 					(i == now) ? "*" : "");
- 		break;
- 	default:
-@@ -4762,7 +4666,7 @@ static int vega10_display_configuration_
- 
- 	if ((data->water_marks_bitmap & WaterMarksExist) &&
- 			!(data->water_marks_bitmap & WaterMarksLoaded)) {
--		result = vega10_copy_table_to_smc(hwmgr->smumgr,
-+		result = vega10_copy_table_to_smc(hwmgr,
- 			(uint8_t *)wm_table, WMTABLE);
- 		PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
- 		data->water_marks_bitmap |= WaterMarksLoaded;
-@@ -4771,7 +4675,7 @@ static int vega10_display_configuration_
- 	if (data->water_marks_bitmap & WaterMarksLoaded) {
- 		cgs_get_active_displays_info(hwmgr->device, &info);
- 		num_turned_on_displays = info.display_count;
--		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_NumOfDisplays, num_turned_on_displays);
- 	}
- 
-@@ -4784,7 +4688,7 @@ int vega10_enable_disable_uvd_dpm(struct
- 			(struct vega10_hwmgr *)(hwmgr->backend);
- 
- 	if (data->smu_features[GNLD_DPM_UVD].supported) {
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				enable,
- 				data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
- 				"Attempt to Enable/Disable DPM UVD Failed!",
-@@ -4794,20 +4698,20 @@ int vega10_enable_disable_uvd_dpm(struct
- 	return 0;
- }
- 
--static int vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
-+static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
- {
- 	struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
- 
- 	data->vce_power_gated = bgate;
--	return vega10_enable_disable_vce_dpm(hwmgr, !bgate);
-+	vega10_enable_disable_vce_dpm(hwmgr, !bgate);
- }
- 
--static int vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
-+static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
- {
- 	struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
- 
- 	data->uvd_power_gated = bgate;
--	return vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
-+	vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
- }
- 
- static inline bool vega10_are_power_levels_equal(
-@@ -4866,7 +4770,7 @@ vega10_check_smc_update_required_for_dis
- 	if (data->display_timing.num_existing_displays != info.display_count)
- 		is_update_required = true;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
-+	if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
- 		if (data->display_timing.min_clock_in_sr != hwmgr->display_config.min_core_set_clock_in_sr)
- 			is_update_required = true;
- 	}
-@@ -4883,8 +4787,7 @@ static int vega10_disable_dpm_tasks(stru
- 			"DPM is not running right now, no need to disable DPM!",
- 			return 0);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_ThermalController))
-+	if (PP_CAP(PHM_PlatformCaps_ThermalController))
- 		vega10_disable_thermal_protection(hwmgr);
- 
- 	tmp_result = vega10_disable_power_containment(hwmgr);
-@@ -4972,7 +4875,7 @@ static int vega10_set_power_profile_stat
- 		if (!data->registry_data.sclk_dpm_key_disabled)
- 			PP_ASSERT_WITH_CODE(
- 					!smum_send_msg_to_smc_with_parameter(
--					hwmgr->smumgr,
-+					hwmgr,
- 					PPSMC_MSG_SetSoftMinGfxclkByIndex,
- 					sclk_idx),
- 					"Failed to set soft min sclk index!",
-@@ -4983,7 +4886,7 @@ static int vega10_set_power_profile_stat
- 		if (!data->registry_data.mclk_dpm_key_disabled)
- 			PP_ASSERT_WITH_CODE(
- 					!smum_send_msg_to_smc_with_parameter(
--					hwmgr->smumgr,
-+					hwmgr,
- 					PPSMC_MSG_SetSoftMinUclkByIndex,
- 					mclk_idx),
- 					"Failed to set soft min mclk index!",
-@@ -5096,6 +4999,65 @@ static int vega10_set_mclk_od(struct pp_
- 	return 0;
- }
- 
-+static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
-+					uint32_t virtual_addr_low,
-+					uint32_t virtual_addr_hi,
-+					uint32_t mc_addr_low,
-+					uint32_t mc_addr_hi,
-+					uint32_t size)
-+{
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
-+					PPSMC_MSG_SetSystemVirtualDramAddrHigh,
-+					virtual_addr_hi);
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
-+					PPSMC_MSG_SetSystemVirtualDramAddrLow,
-+					virtual_addr_low);
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
-+					PPSMC_MSG_DramLogSetDramAddrHigh,
-+					mc_addr_hi);
-+
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
-+					PPSMC_MSG_DramLogSetDramAddrLow,
-+					mc_addr_low);
-+
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
-+					PPSMC_MSG_DramLogSetDramSize,
-+					size);
-+	return 0;
-+}
-+
-+static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
-+		const void *info)
-+{
-+	struct cgs_irq_src_funcs *irq_src =
-+			(struct cgs_irq_src_funcs *)info;
-+
-+	if (hwmgr->thermal_controller.ucType ==
-+			ATOM_VEGA10_PP_THERMALCONTROLLER_VEGA10 ||
-+		hwmgr->thermal_controller.ucType ==
-+			ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
-+		PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
-+				0xf, /* AMDGPU_IH_CLIENTID_THM */
-+				0, 0, irq_src[0].set, irq_src[0].handler, hwmgr),
-+				"Failed to register high thermal interrupt!",
-+				return -EINVAL);
-+		PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
-+				0xf, /* AMDGPU_IH_CLIENTID_THM */
-+				1, 0, irq_src[1].set, irq_src[1].handler, hwmgr),
-+				"Failed to register low thermal interrupt!",
-+				return -EINVAL);
-+	}
-+
-+	/* Register CTF(GPIO_19) interrupt */
-+	PP_ASSERT_WITH_CODE(!cgs_add_irq_source(hwmgr->device,
-+			0x16, /* AMDGPU_IH_CLIENTID_ROM_SMUIO, */
-+			83, 0, irq_src[2].set, irq_src[2].handler, hwmgr),
-+			"Failed to register CTF thermal interrupt!",
-+			return -EINVAL);
-+
-+	return 0;
-+}
-+
- static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
- 	.backend_init = vega10_hwmgr_backend_init,
- 	.backend_fini = vega10_hwmgr_backend_fini,
-@@ -5149,12 +5111,15 @@ static const struct pp_hwmgr_func vega10
- 	.get_mclk_od = vega10_get_mclk_od,
- 	.set_mclk_od = vega10_set_mclk_od,
- 	.avfs_control = vega10_avfs_enable,
-+	.notify_cac_buffer_info = vega10_notify_cac_buffer_info,
-+	.register_internal_thermal_interrupt = vega10_register_thermal_interrupt,
-+	.start_thermal_controller = vega10_start_thermal_controller,
- };
- 
- int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
- {
- 	hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
- 	hwmgr->pptable_func = &vega10_pptable_funcs;
--	pp_vega10_thermal_initialize(hwmgr);
-+
- 	return 0;
- }
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h	2017-12-14 06:39:58.474903609 +0100
-@@ -31,7 +31,6 @@
- #include "vega10_ppsmc.h"
- #include "vega10_powertune.h"
- 
--extern const uint32_t PhwVega10_Magic;
- #define VEGA10_MAX_HARDWARE_POWERLEVELS 2
- 
- #define WaterMarksExist  1
-@@ -390,6 +389,7 @@ struct vega10_hwmgr {
- 	uint32_t                       config_telemetry;
- 	uint32_t                       smu_version;
- 	uint32_t                       acg_loop_state;
-+	uint32_t                       mem_channels;
- };
- 
- #define VEGA10_DPM2_NEAR_TDP_DEC                      10
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c	2017-12-14 06:39:58.474903609 +0100
-@@ -854,99 +854,79 @@ static void vega10_didt_set_mask(struct
- 	uint32_t en = (enable ? 1 : 0);
- 	uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) {
--		data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0);
--		data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
--		data |= ((en << DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0, data);
-+	if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
-+		CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
-+				     DIDT_SQ_CTRL0, DIDT_CTRL_EN, en);
- 		didt_block_info &= ~SQ_Enable_MASK;
- 		didt_block_info |= en << SQ_Enable_SHIFT;
- 	}
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) {
--		data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0);
--		data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
--		data |= ((en << DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0, data);
-+	if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
-+		CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
-+				     DIDT_DB_CTRL0, DIDT_CTRL_EN, en);
- 		didt_block_info &= ~DB_Enable_MASK;
- 		didt_block_info |= en << DB_Enable_SHIFT;
- 	}
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) {
--		data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0);
--		data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
--		data |= ((en << DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0, data);
-+	if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
-+		CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
-+				     DIDT_TD_CTRL0, DIDT_CTRL_EN, en);
- 		didt_block_info &= ~TD_Enable_MASK;
- 		didt_block_info |= en << TD_Enable_SHIFT;
- 	}
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
--		data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0);
--		data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
--		data |= ((en << DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0, data);
-+	if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
-+		CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
-+				     DIDT_TCP_CTRL0, DIDT_CTRL_EN, en);
- 		didt_block_info &= ~TCP_Enable_MASK;
- 		didt_block_info |= en << TCP_Enable_SHIFT;
- 	}
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) {
--		data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_CTRL0);
--		data &= ~DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK;
--		data |= ((en << DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK);
--		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_CTRL0, data);
-+	if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
-+		CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
-+				     DIDT_DBR_CTRL0, DIDT_CTRL_EN, en);
- 	}
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable)) {
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) {
-+	if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) {
-+		if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
- 			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL);
--			data &= ~DIDT_SQ_EDC_CTRL__EDC_EN_MASK;
--			data |= ((en << DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT) & DIDT_SQ_EDC_CTRL__EDC_EN_MASK);
--			data &= ~DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK;
--			data |= ((~en << DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK);
-+			data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);
-+			data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);
- 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data);
- 		}
- 
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) {
-+		if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
- 			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL);
--			data &= ~DIDT_DB_EDC_CTRL__EDC_EN_MASK;
--			data |= ((en << DIDT_DB_EDC_CTRL__EDC_EN__SHIFT) & DIDT_DB_EDC_CTRL__EDC_EN_MASK);
--			data &= ~DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK;
--			data |= ((~en << DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK);
-+			data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);
-+			data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);
- 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data);
- 		}
- 
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) {
-+		if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
- 			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL);
--			data &= ~DIDT_TD_EDC_CTRL__EDC_EN_MASK;
--			data |= ((en << DIDT_TD_EDC_CTRL__EDC_EN__SHIFT) & DIDT_TD_EDC_CTRL__EDC_EN_MASK);
--			data &= ~DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK;
--			data |= ((~en << DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK);
-+			data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);
-+			data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);
- 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data);
- 		}
- 
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
-+		if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
- 			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL);
--			data &= ~DIDT_TCP_EDC_CTRL__EDC_EN_MASK;
--			data |= ((en << DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT) & DIDT_TCP_EDC_CTRL__EDC_EN_MASK);
--			data &= ~DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK;
--			data |= ((~en << DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK);
-+			data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);
-+			data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);
- 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data);
- 		}
- 
--		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) {
-+		if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
- 			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL);
--			data &= ~DIDT_DBR_EDC_CTRL__EDC_EN_MASK;
--			data |= ((en << DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT) & DIDT_DBR_EDC_CTRL__EDC_EN_MASK);
--			data &= ~DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK;
--			data |= ((~en << DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT) & DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK);
-+			data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);
-+			data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);
- 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data);
- 		}
- 	}
- 
- 	if (enable) {
- 		/* For Vega10, SMC does not support any mask yet. */
--		result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
-+		result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
- 		PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure Gfx Didt Failed!");
- 	}
- }
-@@ -1040,10 +1020,10 @@ static int vega10_enable_psm_gc_didt_con
- 	cgs_enter_safe_mode(hwmgr->device, false);
- 
- 	vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10);
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC))
-+	if (PP_CAP(PHM_PlatformCaps_GCEDC))
- 		vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM))
-+	if (PP_CAP(PHM_PlatformCaps_PSM))
- 		vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMInitConfig_vega10);
- 
- 	return 0;
-@@ -1059,12 +1039,12 @@ static int vega10_disable_psm_gc_didt_co
- 
- 	cgs_enter_safe_mode(hwmgr->device, false);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) {
-+	if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
- 		data = 0x00000000;
- 		cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data);
- 	}
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM))
-+	if (PP_CAP(PHM_PlatformCaps_PSM))
- 		vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMResetConfig_vega10);
- 
- 	return 0;
-@@ -1159,12 +1139,12 @@ static int vega10_enable_psm_gc_edc_conf
- 
- 	vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) {
-+	if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
- 		vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega10);
- 		vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega10);
- 	}
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM))
-+	if (PP_CAP(PHM_PlatformCaps_PSM))
- 		vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMInitConfig_vega10);
- 
- 	return 0;
-@@ -1180,12 +1160,12 @@ static int vega10_disable_psm_gc_edc_con
- 
- 	cgs_enter_safe_mode(hwmgr->device, false);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) {
-+	if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
- 		data = 0x00000000;
- 		cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data);
- 	}
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM))
-+	if (PP_CAP(PHM_PlatformCaps_PSM))
- 		vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMResetConfig_vega10);
- 
- 	return 0;
-@@ -1263,8 +1243,8 @@ int vega10_enable_didt_config(struct pp_
- 		}
- 
- 		if (0 == result) {
--			PP_ASSERT_WITH_CODE((!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap)),
--				"[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
-+			result = vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
-+			PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
- 			data->smu_features[GNLD_DIDT].enabled = true;
- 		}
- 	}
-@@ -1310,8 +1290,8 @@ int vega10_disable_didt_config(struct pp
- 		}
- 
- 		if (0 == result) {
--			PP_ASSERT_WITH_CODE((0 != vega10_enable_smc_features(hwmgr->smumgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap)),
--					"[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
-+			result = vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
-+			PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
- 			data->smu_features[GNLD_DIDT].enabled = false;
- 		}
- 	}
-@@ -1364,7 +1344,7 @@ int vega10_set_power_limit(struct pp_hwm
- 			(struct vega10_hwmgr *)(hwmgr->backend);
- 
- 	if (data->registry_data.enable_pkg_pwr_tracking_feature)
--		return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+		return smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetPptLimit, n);
- 
- 	return 0;
-@@ -1381,16 +1361,15 @@ int vega10_enable_power_containment(stru
- 			(uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
- 	int result = 0;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_PowerContainment)) {
-+	if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
- 		if (data->smu_features[GNLD_PPT].supported)
--			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 					true, data->smu_features[GNLD_PPT].smu_feature_bitmap),
- 					"Attempt to enable PPT feature Failed!",
- 					data->smu_features[GNLD_PPT].supported = false);
- 
- 		if (data->smu_features[GNLD_TDC].supported)
--			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 					true, data->smu_features[GNLD_TDC].smu_feature_bitmap),
- 					"Attempt to enable PPT feature Failed!",
- 					data->smu_features[GNLD_TDC].supported = false);
-@@ -1409,16 +1388,15 @@ int vega10_disable_power_containment(str
- 	struct vega10_hwmgr *data =
- 			(struct vega10_hwmgr *)(hwmgr->backend);
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_PowerContainment)) {
-+	if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
- 		if (data->smu_features[GNLD_PPT].supported)
--			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 					false, data->smu_features[GNLD_PPT].smu_feature_bitmap),
- 					"Attempt to disable PPT feature Failed!",
- 					data->smu_features[GNLD_PPT].supported = false);
- 
- 		if (data->smu_features[GNLD_TDC].supported)
--			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 					false, data->smu_features[GNLD_TDC].smu_feature_bitmap),
- 					"Attempt to disable PPT feature Failed!",
- 					data->smu_features[GNLD_TDC].supported = false);
-@@ -1430,7 +1408,7 @@ int vega10_disable_power_containment(str
- static int vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
- 		uint32_t adjust_percent)
- {
--	return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	return smum_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
- }
- 
-@@ -1438,8 +1416,7 @@ int vega10_power_control_set_level(struc
- {
- 	int adjust_percent, result = 0;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_PowerContainment)) {
-+	if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
- 		adjust_percent =
- 				hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
- 				hwmgr->platform_descriptor.TDPAdjustment :
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c	2017-12-14 06:39:58.474903609 +0100
-@@ -291,8 +291,7 @@ static int get_mm_clock_voltage_table(
- 	table_size = sizeof(uint32_t) +
- 			sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record) *
- 			mm_dependency_table->ucNumEntries;
--	mm_table = (phm_ppt_v1_mm_clock_voltage_dependency_table *)
--			kzalloc(table_size, GFP_KERNEL);
-+	mm_table = kzalloc(table_size, GFP_KERNEL);
- 
- 	if (!mm_table)
- 		return -ENOMEM;
-@@ -519,8 +518,7 @@ static int get_socclk_voltage_dependency
- 			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
- 			clk_dep_table->ucNumEntries;
- 
--	clk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
--			kzalloc(table_size, GFP_KERNEL);
-+	clk_table = kzalloc(table_size, GFP_KERNEL);
- 
- 	if (!clk_table)
- 		return -ENOMEM;
-@@ -554,8 +552,7 @@ static int get_mclk_voltage_dependency_t
- 			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
- 			mclk_dep_table->ucNumEntries;
- 
--	mclk_table = (phm_ppt_v1_clock_voltage_dependency_table *)
--			kzalloc(table_size, GFP_KERNEL);
-+	mclk_table = kzalloc(table_size, GFP_KERNEL);
- 
- 	if (!mclk_table)
- 		return -ENOMEM;
-@@ -596,8 +593,7 @@ static int get_gfxclk_voltage_dependency
- 			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
- 			clk_dep_table->ucNumEntries;
- 
--	clk_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)
--			kzalloc(table_size, GFP_KERNEL);
-+	clk_table = kzalloc(table_size, GFP_KERNEL);
- 
- 	if (!clk_table)
- 		return -ENOMEM;
-@@ -663,8 +659,7 @@ static int get_pix_clk_voltage_dependenc
- 			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
- 			clk_dep_table->ucNumEntries;
- 
--	clk_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)
--			kzalloc(table_size, GFP_KERNEL);
-+	clk_table = kzalloc(table_size, GFP_KERNEL);
- 
- 	if (!clk_table)
- 		return -ENOMEM;
-@@ -728,8 +723,7 @@ static int get_dcefclk_voltage_dependenc
- 			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
- 			num_entries;
- 
--	clk_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)
--			kzalloc(table_size, GFP_KERNEL);
-+	clk_table = kzalloc(table_size, GFP_KERNEL);
- 
- 	if (!clk_table)
- 		return -ENOMEM;
-@@ -772,8 +766,7 @@ static int get_pcie_table(struct pp_hwmg
- 			sizeof(struct phm_ppt_v1_pcie_record) *
- 			atom_pcie_table->ucNumEntries;
- 
--	pcie_table = (struct phm_ppt_v1_pcie_table *)
--			kzalloc(table_size, GFP_KERNEL);
-+	pcie_table = kzalloc(table_size, GFP_KERNEL);
- 
- 	if (!pcie_table)
- 		return -ENOMEM;
-@@ -1026,10 +1019,9 @@ static int get_vddc_lookup_table(
- 	table_size = sizeof(uint32_t) +
- 			sizeof(phm_ppt_v1_voltage_lookup_record) * max_levels;
- 
--	table = (phm_ppt_v1_voltage_lookup_table *)
--			kzalloc(table_size, GFP_KERNEL);
-+	table = kzalloc(table_size, GFP_KERNEL);
- 
--	if (NULL == table)
-+	if (table == NULL)
- 		return -ENOMEM;
- 
- 	table->count = vddc_lookup_pp_tables->ucNumEntries;
-@@ -1138,12 +1130,12 @@ int vega10_pp_tables_initialize(struct p
- 
- 	hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v2_information), GFP_KERNEL);
- 
--	PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable),
-+	PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
- 			    "Failed to allocate hwmgr->pptable!", return -ENOMEM);
- 
- 	powerplay_table = get_powerplay_table(hwmgr);
- 
--	PP_ASSERT_WITH_CODE((NULL != powerplay_table),
-+	PP_ASSERT_WITH_CODE((powerplay_table != NULL),
- 		"Missing PowerPlay Table!", return -1);
- 
- 	result = check_powerplay_tables(hwmgr, powerplay_table);
-@@ -1182,7 +1174,6 @@ int vega10_pp_tables_initialize(struct p
- 
- static int vega10_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
- {
--	int result = 0;
- 	struct phm_ppt_v2_information *pp_table_info =
- 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
- 
-@@ -1225,7 +1216,7 @@ static int vega10_pp_tables_uninitialize
- 	kfree(hwmgr->pptable);
- 	hwmgr->pptable = NULL;
- 
--	return result;
-+	return 0;
- }
- 
- const struct pp_table_func vega10_pptable_funcs = {
-@@ -1238,7 +1229,7 @@ int vega10_get_number_of_powerplay_table
- 	const ATOM_Vega10_State_Array *state_arrays;
- 	const ATOM_Vega10_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
- 
--	PP_ASSERT_WITH_CODE((NULL != pp_table),
-+	PP_ASSERT_WITH_CODE((pp_table != NULL),
- 			"Missing PowerPlay Table!", return -1);
- 	PP_ASSERT_WITH_CODE((pp_table->sHeader.format_revision >=
- 			ATOM_Vega10_TABLE_REVISION_VEGA10),
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c	2017-12-14 06:39:58.475903609 +0100
-@@ -31,11 +31,11 @@
- 
- static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
- {
--	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
-+	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
- 				PPSMC_MSG_GetCurrentRpm),
- 			"Attempt to get current RPM from SMC Failed!",
- 			return -1);
--	PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
-+	PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
- 			current_rpm),
- 			"Attempt to read current RPM from SMC Failed!",
- 			return -1);
-@@ -54,8 +54,7 @@ int vega10_fan_ctrl_get_fan_speed_info(s
- 	fan_speed_info->min_percent = 0;
- 	fan_speed_info->max_percent = 100;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
-+	if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
- 		hwmgr->thermal_controller.fanInfo.
- 		ucTachometerPulsesPerRevolution) {
- 		fan_speed_info->supports_rpm_read = true;
-@@ -105,14 +104,15 @@ int vega10_fan_ctrl_get_fan_speed_rpm(st
- 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
- 		return -1;
- 
--	if (data->smu_features[GNLD_FAN_CONTROL].supported)
-+	if (data->smu_features[GNLD_FAN_CONTROL].supported) {
- 		result = vega10_get_current_rpm(hwmgr, speed);
--	else {
-+	} else {
- 		uint32_t reg = soc15_get_register_offset(THM_HWID, 0,
- 				mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
--		tach_period = (cgs_read_register(hwmgr->device,
--				reg) & CG_TACH_STATUS__TACH_PERIOD_MASK) >>
--				CG_TACH_STATUS__TACH_PERIOD__SHIFT;
-+		tach_period =
-+			CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
-+					  CG_TACH_STATUS,
-+					  TACH_PERIOD);
- 
- 		if (tach_period == 0)
- 			return -EINVAL;
-@@ -141,23 +141,20 @@ int vega10_fan_ctrl_set_static_mode(stru
- 
- 	if (hwmgr->fan_ctrl_is_in_default_mode) {
- 		hwmgr->fan_ctrl_default_mode =
--				(cgs_read_register(hwmgr->device, reg) &
--				CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >>
--				CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
--		hwmgr->tmin = (cgs_read_register(hwmgr->device, reg) &
--				CG_FDO_CTRL2__TMIN_MASK) >>
--				CG_FDO_CTRL2__TMIN__SHIFT;
-+			CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
-+				CG_FDO_CTRL2, FDO_PWM_MODE);
-+		hwmgr->tmin =
-+			CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
-+				CG_FDO_CTRL2, TMIN);
- 		hwmgr->fan_ctrl_is_in_default_mode = false;
- 	}
- 
- 	cgs_write_register(hwmgr->device, reg,
--			(cgs_read_register(hwmgr->device, reg) &
--			~CG_FDO_CTRL2__TMIN_MASK) |
--			(0 << CG_FDO_CTRL2__TMIN__SHIFT));
-+			CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
-+				CG_FDO_CTRL2, TMIN, 0));
- 	cgs_write_register(hwmgr->device, reg,
--			(cgs_read_register(hwmgr->device, reg) &
--			~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
--			(mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
-+			CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
-+				CG_FDO_CTRL2, FDO_PWM_MODE, mode));
- 
- 	return 0;
- }
-@@ -176,14 +173,13 @@ int vega10_fan_ctrl_set_default_mode(str
- 
- 	if (!hwmgr->fan_ctrl_is_in_default_mode) {
- 		cgs_write_register(hwmgr->device, reg,
--				(cgs_read_register(hwmgr->device, reg) &
--				~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
--				(hwmgr->fan_ctrl_default_mode <<
--				CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
-+			CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
-+				CG_FDO_CTRL2, FDO_PWM_MODE,
-+				hwmgr->fan_ctrl_default_mode));
- 		cgs_write_register(hwmgr->device, reg,
--				(cgs_read_register(hwmgr->device, reg) &
--				~CG_FDO_CTRL2__TMIN_MASK) |
--				(hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
-+			CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
-+				CG_FDO_CTRL2, TMIN,
-+				hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
- 		hwmgr->fan_ctrl_is_in_default_mode = true;
- 	}
- 
-@@ -203,7 +199,7 @@ static int vega10_enable_fan_control_fea
- 
- 	if (data->smu_features[GNLD_FAN_CONTROL].supported) {
- 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
--				hwmgr->smumgr, true,
-+				hwmgr, true,
- 				data->smu_features[GNLD_FAN_CONTROL].
- 				smu_feature_bitmap),
- 				"Attempt to Enable FAN CONTROL feature Failed!",
-@@ -220,7 +216,7 @@ static int vega10_disable_fan_control_fe
- 
- 	if (data->smu_features[GNLD_FAN_CONTROL].supported) {
- 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
--				hwmgr->smumgr, false,
-+				hwmgr, false,
- 				data->smu_features[GNLD_FAN_CONTROL].
- 				smu_feature_bitmap),
- 				"Attempt to Enable FAN CONTROL feature Failed!",
-@@ -279,16 +275,14 @@ int vega10_fan_ctrl_set_fan_speed_percen
- 	if (speed > 100)
- 		speed = 100;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_MicrocodeFanControl))
-+	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
- 		vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
- 
- 	reg = soc15_get_register_offset(THM_HWID, 0,
- 			mmCG_FDO_CTRL1_BASE_IDX, mmCG_FDO_CTRL1);
- 
--	duty100 = (cgs_read_register(hwmgr->device, reg) &
--			CG_FDO_CTRL1__FMAX_DUTY100_MASK) >>
--			CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
-+	duty100 = CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),
-+				    CG_FDO_CTRL1, FMAX_DUTY100);
- 
- 	if (duty100 == 0)
- 		return -EINVAL;
-@@ -300,9 +294,8 @@ int vega10_fan_ctrl_set_fan_speed_percen
- 	reg = soc15_get_register_offset(THM_HWID, 0,
- 			mmCG_FDO_CTRL0_BASE_IDX, mmCG_FDO_CTRL0);
- 	cgs_write_register(hwmgr->device, reg,
--			(cgs_read_register(hwmgr->device, reg) &
--			~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK) |
--			(duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT));
-+		CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
-+			CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
- 
- 	return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
- }
-@@ -314,18 +307,13 @@ int vega10_fan_ctrl_set_fan_speed_percen
- */
- int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
- {
--	int result;
--
- 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
- 		return 0;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_MicrocodeFanControl)) {
--		result = vega10_fan_ctrl_start_smc_fan_control(hwmgr);
--	} else
--		result = vega10_fan_ctrl_set_default_mode(hwmgr);
--
--	return result;
-+	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
-+		return vega10_fan_ctrl_start_smc_fan_control(hwmgr);
-+	else
-+		return vega10_fan_ctrl_set_default_mode(hwmgr);
- }
- 
- /**
-@@ -342,12 +330,11 @@ int vega10_fan_ctrl_set_fan_speed_rpm(st
- 	uint32_t reg;
- 
- 	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
--			(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
--			(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
-+	    (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
-+	    (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
- 		return -1;
- 
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_MicrocodeFanControl))
-+	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
- 		result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
- 
- 	if (!result) {
-@@ -356,9 +343,9 @@ int vega10_fan_ctrl_set_fan_speed_rpm(st
- 		reg = soc15_get_register_offset(THM_HWID, 0,
- 				mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
- 		cgs_write_register(hwmgr->device, reg,
--				(cgs_read_register(hwmgr->device, reg) &
--				~CG_TACH_STATUS__TACH_PERIOD_MASK) |
--				(tach_period << CG_TACH_STATUS__TACH_PERIOD__SHIFT));
-+				CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
-+					CG_TACH_STATUS, TACH_PERIOD,
-+					tach_period));
- 	}
- 	return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
- }
-@@ -374,12 +361,12 @@ int vega10_thermal_get_temperature(struc
- 	uint32_t reg;
- 
- 	reg = soc15_get_register_offset(THM_HWID, 0,
--			mmCG_TACH_STATUS_BASE_IDX,  mmCG_MULT_THERMAL_STATUS);
-+			mmCG_MULT_THERMAL_STATUS_BASE_IDX,  mmCG_MULT_THERMAL_STATUS);
- 
- 	temp = cgs_read_register(hwmgr->device, reg);
- 
--	temp = (temp & CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK) >>
--			CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT;
-+	temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
-+			CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
- 
- 	temp = temp & 0x1ff;
- 
-@@ -418,20 +405,10 @@ static int vega10_thermal_set_temperatur
- 
- 	val = cgs_read_register(hwmgr->device, reg);
- 
--	val &= (~THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK);
--	val |=  (5 << THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT);
--
--	val &= (~THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK);
--	val |= (1 << THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT);
--
--	val &= (~THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK);
--	val |= ((high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
--			<< THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT);
--
--	val &= (~THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
--	val |= ((low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
--			<< THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT);
--
-+	val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
-+	val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
-+	val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-+	val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
- 	val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
- 
- 	cgs_write_register(hwmgr->device, reg, val);
-@@ -452,19 +429,16 @@ static int vega10_thermal_initialize(str
- 		reg = soc15_get_register_offset(THM_HWID, 0,
- 				mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL);
- 		cgs_write_register(hwmgr->device, reg,
--				(cgs_read_register(hwmgr->device, reg) &
--				~CG_TACH_CTRL__EDGE_PER_REV_MASK) |
--				((hwmgr->thermal_controller.fanInfo.
--				ucTachometerPulsesPerRevolution - 1) <<
--				CG_TACH_CTRL__EDGE_PER_REV__SHIFT));
-+			CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
-+				CG_TACH_CTRL, EDGE_PER_REV,
-+				hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1));
- 	}
- 
- 	reg = soc15_get_register_offset(THM_HWID, 0,
- 			mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
- 	cgs_write_register(hwmgr->device, reg,
--			(cgs_read_register(hwmgr->device, reg) &
--			~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK) |
--			(0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT));
-+		CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),
-+			CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28));
- 
- 	return 0;
- }
-@@ -484,7 +458,7 @@ static int vega10_thermal_enable_alert(s
- 		if (data->smu_features[GNLD_FW_CTF].enabled)
- 			printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
- 
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 				true,
- 				data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
- 				"Attempt to Enable FW CTF feature Failed!",
-@@ -516,7 +490,7 @@ int vega10_thermal_disable_alert(struct
- 			printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
- 
- 
--		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
-+		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
- 			false,
- 			data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
- 			"Attempt to disable FW CTF feature Failed!",
-@@ -554,8 +528,7 @@ int vega10_thermal_stop_thermal_controll
- * @param    Result the last failure code
- * @return   result from set temperature range routine
- */
--int tf_vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
-+int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
- {
- 	int ret;
- 	struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
-@@ -573,7 +546,7 @@ int tf_vega10_thermal_setup_fan_table(st
- 	table->FanTargetTemperature = hwmgr->thermal_controller.
- 			advanceFanControlParameters.usTMax;
- 
--	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-+	smum_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetFanTemperatureTarget,
- 				(uint32_t)table->FanTargetTemperature);
- 
-@@ -602,7 +575,7 @@ int tf_vega10_thermal_setup_fan_table(st
- 	table->FanStartTemp = hwmgr->thermal_controller.
- 			advanceFanControlParameters.usZeroRPMStartTemperature;
- 
--	ret = vega10_copy_table_to_smc(hwmgr->smumgr,
-+	ret = vega10_copy_table_to_smc(hwmgr,
- 			(uint8_t *)(&(data->smc_state_table.pp_table)), PPTABLE);
- 	if (ret)
- 		pr_info("Failed to update Fan Control Table in PPTable!");
-@@ -619,123 +592,50 @@ int tf_vega10_thermal_setup_fan_table(st
- * @param    Result the last failure code
- * @return   result from set temperature range routine
- */
--int tf_vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
-+int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
- {
- /* If the fantable setup has failed we could have disabled
-  * PHM_PlatformCaps_MicrocodeFanControl even after
-  * this function was included in the table.
-  * Make sure that we still think controlling the fan is OK.
- */
--	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
--			PHM_PlatformCaps_MicrocodeFanControl)) {
-+	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
- 		vega10_fan_ctrl_start_smc_fan_control(hwmgr);
--	}
- 
- 	return 0;
- }
- 
--/**
--* Set temperature range for high and low alerts
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    pInput the pointer to input data
--* @param    pOutput the pointer to output data
--* @param    pStorage the pointer to temporary storage
--* @param    Result the last failure code
--* @return   result from set temperature range routine
--*/
--int tf_vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
-+
-+int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
-+				struct PP_TemperatureRange *range)
- {
--	struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input;
-+	int ret = 0;
- 
- 	if (range == NULL)
- 		return -EINVAL;
- 
--	return vega10_thermal_set_temperature_range(hwmgr, range);
--}
--
--/**
--* Programs one-time setting registers
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    pInput the pointer to input data
--* @param    pOutput the pointer to output data
--* @param    pStorage the pointer to temporary storage
--* @param    Result the last failure code
--* @return   result from initialize thermal controller routine
--*/
--int tf_vega10_thermal_initialize(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
--{
--	return vega10_thermal_initialize(hwmgr);
--}
--
--/**
--* Enable high and low alerts
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    pInput the pointer to input data
--* @param    pOutput the pointer to output data
--* @param    pStorage the pointer to temporary storage
--* @param    Result the last failure code
--* @return   result from enable alert routine
--*/
--int tf_vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
--{
--	return vega10_thermal_enable_alert(hwmgr);
--}
--
--/**
--* Disable high and low alerts
--* @param    hwmgr  the address of the powerplay hardware manager.
--* @param    pInput the pointer to input data
--* @param    pOutput the pointer to output data
--* @param    pStorage the pointer to temporary storage
--* @param    Result the last failure code
--* @return   result from disable alert routine
--*/
--static int tf_vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
--{
--	return vega10_thermal_disable_alert(hwmgr);
--}
-+	vega10_thermal_initialize(hwmgr);
-+	ret = vega10_thermal_set_temperature_range(hwmgr, range);
-+	if (ret)
-+		return -EINVAL;
- 
--static struct phm_master_table_item
--vega10_thermal_start_thermal_controller_master_list[] = {
--	{ .tableFunction = tf_vega10_thermal_initialize },
--	{ .tableFunction = tf_vega10_thermal_set_temperature_range },
--	{ .tableFunction = tf_vega10_thermal_enable_alert },
-+	vega10_thermal_enable_alert(hwmgr);
- /* We should restrict performance levels to low before we halt the SMC.
-  * On the other hand we are still in boot state when we do this
-  * so it would be pointless.
-  * If this assumption changes we have to revisit this table.
-  */
--	{ .tableFunction = tf_vega10_thermal_setup_fan_table },
--	{ .tableFunction = tf_vega10_thermal_start_smc_fan_control },
--	{ }
--};
-+	ret = vega10_thermal_setup_fan_table(hwmgr);
-+	if (ret)
-+		return -EINVAL;
- 
--static struct phm_master_table_header
--vega10_thermal_start_thermal_controller_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	vega10_thermal_start_thermal_controller_master_list
--};
-+	vega10_thermal_start_smc_fan_control(hwmgr);
- 
--static struct phm_master_table_item
--vega10_thermal_set_temperature_range_master_list[] = {
--	{ .tableFunction = tf_vega10_thermal_disable_alert },
--	{ .tableFunction = tf_vega10_thermal_set_temperature_range },
--	{ .tableFunction = tf_vega10_thermal_enable_alert },
--	{ }
-+	return 0;
- };
- 
--struct phm_master_table_header
--vega10_thermal_set_temperature_range_master = {
--	0,
--	PHM_MasterTableFlag_None,
--	vega10_thermal_set_temperature_range_master_list
--};
-+
-+
- 
- int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
- {
-@@ -745,32 +645,3 @@ int vega10_thermal_ctrl_uninitialize_the
- 	}
- 	return 0;
- }
--
--/**
--* Initializes the thermal controller related functions
--* in the Hardware Manager structure.
--* @param    hwmgr The address of the hardware manager.
--* @exception Any error code from the low-level communication.
--*/
--int pp_vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
--{
--	int result;
--
--	result = phm_construct_table(hwmgr,
--			&vega10_thermal_set_temperature_range_master,
--			&(hwmgr->set_temperature_range));
--
--	if (!result) {
--		result = phm_construct_table(hwmgr,
--				&vega10_thermal_start_thermal_controller_master,
--				&(hwmgr->start_thermal_controller));
--		if (result)
--			phm_destroy_table(hwmgr,
--					&(hwmgr->set_temperature_range));
--	}
--
--	if (!result)
--		hwmgr->fan_ctrl_is_in_default_mode = true;
--	return result;
--}
--
---- linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h	2017-12-14 06:39:58.475903609 +0100
-@@ -50,13 +50,6 @@ struct vega10_temperature {
- #define FDO_PWM_MODE_STATIC_RPM 5
- 
- 
--extern int tf_vega10_thermal_initialize(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result);
--extern int tf_vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result);
--extern int tf_vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result);
--
- extern int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr);
- extern int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
- extern int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
-@@ -69,7 +62,6 @@ extern int vega10_fan_ctrl_set_static_mo
- extern int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
- 		uint32_t speed);
- extern int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
--extern int pp_vega10_thermal_initialize(struct pp_hwmgr *hwmgr);
- extern int vega10_thermal_ctrl_uninitialize_thermal_controller(
- 		struct pp_hwmgr *hwmgr);
- extern int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr,
-@@ -77,9 +69,11 @@ extern int vega10_fan_ctrl_set_fan_speed
- extern int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr,
- 		uint32_t *speed);
- extern int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
--extern uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr);
- extern int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr);
--int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
-+extern int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
-+extern int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
-+				struct PP_TemperatureRange *range);
-+extern uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr);
- 
- #endif
- 
---- linux-4.14/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h	2017-12-14 06:39:58.475903609 +0100
-@@ -29,414 +29,7 @@
- #include "amd_shared.h"
- #include "cgs_common.h"
- #include "dm_pp_interface.h"
-+#include "kgd_pp_interface.h"
- 
--extern const struct amd_ip_funcs pp_ip_funcs;
--extern const struct amd_powerplay_funcs pp_dpm_funcs;
--
--#define PP_DPM_DISABLED 0xCCCC
--
--enum amd_pp_sensors {
--	AMDGPU_PP_SENSOR_GFX_SCLK = 0,
--	AMDGPU_PP_SENSOR_VDDNB,
--	AMDGPU_PP_SENSOR_VDDGFX,
--	AMDGPU_PP_SENSOR_UVD_VCLK,
--	AMDGPU_PP_SENSOR_UVD_DCLK,
--	AMDGPU_PP_SENSOR_VCE_ECCLK,
--	AMDGPU_PP_SENSOR_GPU_LOAD,
--	AMDGPU_PP_SENSOR_GFX_MCLK,
--	AMDGPU_PP_SENSOR_GPU_TEMP,
--	AMDGPU_PP_SENSOR_VCE_POWER,
--	AMDGPU_PP_SENSOR_UVD_POWER,
--	AMDGPU_PP_SENSOR_GPU_POWER,
--};
--
--enum amd_pp_event {
--	AMD_PP_EVENT_INITIALIZE = 0,
--	AMD_PP_EVENT_UNINITIALIZE,
--	AMD_PP_EVENT_POWER_SOURCE_CHANGE,
--	AMD_PP_EVENT_SUSPEND,
--	AMD_PP_EVENT_RESUME,
--	AMD_PP_EVENT_ENTER_REST_STATE,
--	AMD_PP_EVENT_EXIT_REST_STATE,
--	AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE,
--	AMD_PP_EVENT_THERMAL_NOTIFICATION,
--	AMD_PP_EVENT_VBIOS_NOTIFICATION,
--	AMD_PP_EVENT_ENTER_THERMAL_STATE,
--	AMD_PP_EVENT_EXIT_THERMAL_STATE,
--	AMD_PP_EVENT_ENTER_FORCED_STATE,
--	AMD_PP_EVENT_EXIT_FORCED_STATE,
--	AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE,
--	AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE,
--	AMD_PP_EVENT_ENTER_SCREEN_SAVER,
--	AMD_PP_EVENT_EXIT_SCREEN_SAVER,
--	AMD_PP_EVENT_VPU_RECOVERY_BEGIN,
--	AMD_PP_EVENT_VPU_RECOVERY_END,
--	AMD_PP_EVENT_ENABLE_POWER_PLAY,
--	AMD_PP_EVENT_DISABLE_POWER_PLAY,
--	AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL,
--	AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE,
--	AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE,
--	AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE,
--	AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE,
--	AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST,
--	AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST,
--	AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE,
--	AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE,
--	AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING,
--	AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING,
--	AMD_PP_EVENT_ENABLE_CGPG,
--	AMD_PP_EVENT_DISABLE_CGPG,
--	AMD_PP_EVENT_ENTER_TEXT_MODE,
--	AMD_PP_EVENT_EXIT_TEXT_MODE,
--	AMD_PP_EVENT_VIDEO_START,
--	AMD_PP_EVENT_VIDEO_STOP,
--	AMD_PP_EVENT_ENABLE_USER_STATE,
--	AMD_PP_EVENT_DISABLE_USER_STATE,
--	AMD_PP_EVENT_READJUST_POWER_STATE,
--	AMD_PP_EVENT_START_INACTIVITY,
--	AMD_PP_EVENT_STOP_INACTIVITY,
--	AMD_PP_EVENT_LINKED_ADAPTERS_READY,
--	AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE,
--	AMD_PP_EVENT_COMPLETE_INIT,
--	AMD_PP_EVENT_CRITICAL_THERMAL_FAULT,
--	AMD_PP_EVENT_BACKLIGHT_CHANGED,
--	AMD_PP_EVENT_ENABLE_VARI_BRIGHT,
--	AMD_PP_EVENT_DISABLE_VARI_BRIGHT,
--	AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS,
--	AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS,
--	AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL,
--	AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT,
--	AMD_PP_EVENT_SCREEN_ON,
--	AMD_PP_EVENT_SCREEN_OFF,
--	AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE,
--	AMD_PP_EVENT_ENTER_ULP_STATE,
--	AMD_PP_EVENT_EXIT_ULP_STATE,
--	AMD_PP_EVENT_REGISTER_IP_STATE,
--	AMD_PP_EVENT_UNREGISTER_IP_STATE,
--	AMD_PP_EVENT_ENTER_MGPU_MODE,
--	AMD_PP_EVENT_EXIT_MGPU_MODE,
--	AMD_PP_EVENT_ENTER_MULTI_GPU_MODE,
--	AMD_PP_EVENT_PRE_SUSPEND,
--	AMD_PP_EVENT_PRE_RESUME,
--	AMD_PP_EVENT_ENTER_BACOS,
--	AMD_PP_EVENT_EXIT_BACOS,
--	AMD_PP_EVENT_RESUME_BACO,
--	AMD_PP_EVENT_RESET_BACO,
--	AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS,
--	AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS,
--	AMD_PP_EVENT_START_COMPUTE_APPLICATION,
--	AMD_PP_EVENT_STOP_COMPUTE_APPLICATION,
--	AMD_PP_EVENT_REDUCE_POWER_LIMIT,
--	AMD_PP_EVENT_ENTER_FRAME_LOCK,
--	AMD_PP_EVENT_EXIT_FRAME_LOOCK,
--	AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO,
--	AMD_PP_EVENT_LONG_IDLE_ENTER_BACO,
--	AMD_PP_EVENT_LONG_IDLE_EXIT_BACO,
--	AMD_PP_EVENT_HIBERNATE,
--	AMD_PP_EVENT_CONNECTED_STANDBY,
--	AMD_PP_EVENT_ENTER_SELF_REFRESH,
--	AMD_PP_EVENT_EXIT_SELF_REFRESH,
--	AMD_PP_EVENT_START_AVFS_BTC,
--	AMD_PP_EVENT_MAX
--};
--
--struct amd_pp_init {
--	struct cgs_device *device;
--	uint32_t chip_family;
--	uint32_t chip_id;
--	bool pm_en;
--	uint32_t feature_mask;
--};
--
--enum amd_pp_display_config_type{
--	AMD_PP_DisplayConfigType_None = 0,
--	AMD_PP_DisplayConfigType_DP54 ,
--	AMD_PP_DisplayConfigType_DP432 ,
--	AMD_PP_DisplayConfigType_DP324 ,
--	AMD_PP_DisplayConfigType_DP27,
--	AMD_PP_DisplayConfigType_DP243,
--	AMD_PP_DisplayConfigType_DP216,
--	AMD_PP_DisplayConfigType_DP162,
--	AMD_PP_DisplayConfigType_HDMI6G ,
--	AMD_PP_DisplayConfigType_HDMI297 ,
--	AMD_PP_DisplayConfigType_HDMI162,
--	AMD_PP_DisplayConfigType_LVDS,
--	AMD_PP_DisplayConfigType_DVI,
--	AMD_PP_DisplayConfigType_WIRELESS,
--	AMD_PP_DisplayConfigType_VGA
--};
--
--struct single_display_configuration
--{
--	uint32_t controller_index;
--	uint32_t controller_id;
--	uint32_t signal_type;
--	uint32_t display_state;
--	/* phy id for the primary internal transmitter */
--	uint8_t primary_transmitter_phyi_d;
--	/* bitmap with the active lanes */
--	uint8_t primary_transmitter_active_lanemap;
--	/* phy id for the secondary internal transmitter (for dual-link dvi) */
--	uint8_t secondary_transmitter_phy_id;
--	/* bitmap with the active lanes */
--	uint8_t secondary_transmitter_active_lanemap;
--	/* misc phy settings for SMU. */
--	uint32_t config_flags;
--	uint32_t display_type;
--	uint32_t view_resolution_cx;
--	uint32_t view_resolution_cy;
--	enum amd_pp_display_config_type displayconfigtype;
--	uint32_t vertical_refresh; /* for active display */
--};
--
--#define MAX_NUM_DISPLAY 32
--
--struct amd_pp_display_configuration {
--	bool nb_pstate_switch_disable;/* controls NB PState switch */
--	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
--	bool cpu_pstate_disable;
--	uint32_t cpu_pstate_separation_time;
--
--	uint32_t num_display;  /* total number of display*/
--	uint32_t num_path_including_non_display;
--	uint32_t crossfire_display_index;
--	uint32_t min_mem_set_clock;
--	uint32_t min_core_set_clock;
--	/* unit 10KHz x bit*/
--	uint32_t min_bus_bandwidth;
--	/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
--	uint32_t min_core_set_clock_in_sr;
--
--	struct single_display_configuration displays[MAX_NUM_DISPLAY];
--
--	uint32_t vrefresh; /* for active display*/
--
--	uint32_t min_vblank_time; /* for active display*/
--	bool multi_monitor_in_sync;
--	/* Controller Index of primary display - used in MCLK SMC switching hang
--	 * SW Workaround*/
--	uint32_t crtc_index;
--	/* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
--	uint32_t line_time_in_us;
--	bool invalid_vblank_time;
--
--	uint32_t display_clk;
--	/*
--	 * for given display configuration if multimonitormnsync == false then
--	 * Memory clock DPMS with this latency or below is allowed, DPMS with
--	 * higher latency not allowed.
--	 */
--	uint32_t dce_tolerable_mclk_in_active_latency;
--	uint32_t min_dcef_set_clk;
--	uint32_t min_dcef_deep_sleep_set_clk;
--};
--
--struct amd_pp_simple_clock_info {
--	uint32_t	engine_max_clock;
--	uint32_t	memory_max_clock;
--	uint32_t	level;
--};
--
--enum PP_DAL_POWERLEVEL {
--	PP_DAL_POWERLEVEL_INVALID = 0,
--	PP_DAL_POWERLEVEL_ULTRALOW,
--	PP_DAL_POWERLEVEL_LOW,
--	PP_DAL_POWERLEVEL_NOMINAL,
--	PP_DAL_POWERLEVEL_PERFORMANCE,
--
--	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
--	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
--	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
--	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
--	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
--	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
--	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
--	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
--};
--
--struct amd_pp_clock_info {
--	uint32_t min_engine_clock;
--	uint32_t max_engine_clock;
--	uint32_t min_memory_clock;
--	uint32_t max_memory_clock;
--	uint32_t min_bus_bandwidth;
--	uint32_t max_bus_bandwidth;
--	uint32_t max_engine_clock_in_sr;
--	uint32_t min_engine_clock_in_sr;
--	enum PP_DAL_POWERLEVEL max_clocks_state;
--};
--
--enum amd_pp_clock_type {
--	amd_pp_disp_clock = 1,
--	amd_pp_sys_clock,
--	amd_pp_mem_clock,
--	amd_pp_dcef_clock,
--	amd_pp_soc_clock,
--	amd_pp_pixel_clock,
--	amd_pp_phy_clock,
--	amd_pp_dcf_clock,
--	amd_pp_dpp_clock,
--	amd_pp_f_clock = amd_pp_dcef_clock,
--};
--
--#define MAX_NUM_CLOCKS 16
--
--struct amd_pp_clocks {
--	uint32_t count;
--	uint32_t clock[MAX_NUM_CLOCKS];
--	uint32_t latency[MAX_NUM_CLOCKS];
--};
--
--
--enum {
--	PP_GROUP_UNKNOWN = 0,
--	PP_GROUP_GFX = 1,
--	PP_GROUP_SYS,
--	PP_GROUP_MAX
--};
--
--enum pp_clock_type {
--	PP_SCLK,
--	PP_MCLK,
--	PP_PCIE,
--};
--
--struct pp_states_info {
--	uint32_t nums;
--	uint32_t states[16];
--};
--
--struct pp_gpu_power {
--	uint32_t vddc_power;
--	uint32_t vddci_power;
--	uint32_t max_gpu_power;
--	uint32_t average_gpu_power;
--};
--
--struct pp_display_clock_request {
--	enum amd_pp_clock_type clock_type;
--	uint32_t clock_freq_in_khz;
--};
--
--#define PP_GROUP_MASK        0xF0000000
--#define PP_GROUP_SHIFT       28
--
--#define PP_BLOCK_MASK        0x0FFFFF00
--#define PP_BLOCK_SHIFT       8
--
--#define PP_BLOCK_GFX_CG         0x01
--#define PP_BLOCK_GFX_MG         0x02
--#define PP_BLOCK_GFX_3D         0x04
--#define PP_BLOCK_GFX_RLC        0x08
--#define PP_BLOCK_GFX_CP         0x10
--#define PP_BLOCK_SYS_BIF        0x01
--#define PP_BLOCK_SYS_MC         0x02
--#define PP_BLOCK_SYS_ROM        0x04
--#define PP_BLOCK_SYS_DRM        0x08
--#define PP_BLOCK_SYS_HDP        0x10
--#define PP_BLOCK_SYS_SDMA       0x20
--
--#define PP_STATE_MASK           0x0000000F
--#define PP_STATE_SHIFT          0
--#define PP_STATE_SUPPORT_MASK   0x000000F0
--#define PP_STATE_SUPPORT_SHIFT  0
--
--#define PP_STATE_CG             0x01
--#define PP_STATE_LS             0x02
--#define PP_STATE_DS             0x04
--#define PP_STATE_SD             0x08
--#define PP_STATE_SUPPORT_CG     0x10
--#define PP_STATE_SUPPORT_LS     0x20
--#define PP_STATE_SUPPORT_DS     0x40
--#define PP_STATE_SUPPORT_SD     0x80
--
--#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
--								block << PP_BLOCK_SHIFT |\
--								support << PP_STATE_SUPPORT_SHIFT |\
--								state << PP_STATE_SHIFT)
--
--struct amd_powerplay_funcs {
--	int (*get_temperature)(void *handle);
--	int (*load_firmware)(void *handle);
--	int (*wait_for_fw_loading_complete)(void *handle);
--	int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
--	enum amd_dpm_forced_level (*get_performance_level)(void *handle);
--	enum amd_pm_state_type (*get_current_power_state)(void *handle);
--	int (*get_sclk)(void *handle, bool low);
--	int (*get_mclk)(void *handle, bool low);
--	int (*powergate_vce)(void *handle, bool gate);
--	int (*powergate_uvd)(void *handle, bool gate);
--	int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id,
--				   void *input, void *output);
--	int (*set_fan_control_mode)(void *handle, uint32_t mode);
--	int (*get_fan_control_mode)(void *handle);
--	int (*set_fan_speed_percent)(void *handle, uint32_t percent);
--	int (*get_fan_speed_percent)(void *handle, uint32_t *speed);
--	int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
--	int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
--	int (*get_pp_table)(void *handle, char **table);
--	int (*set_pp_table)(void *handle, const char *buf, size_t size);
--	int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
--	int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
--	int (*get_sclk_od)(void *handle);
--	int (*set_sclk_od)(void *handle, uint32_t value);
--	int (*get_mclk_od)(void *handle);
--	int (*set_mclk_od)(void *handle, uint32_t value);
--	int (*read_sensor)(void *handle, int idx, void *value, int *size);
--	struct amd_vce_state* (*get_vce_clock_state)(void *handle, unsigned idx);
--	int (*reset_power_profile_state)(void *handle,
--			struct amd_pp_profile *request);
--	int (*get_power_profile_state)(void *handle,
--			struct amd_pp_profile *query);
--	int (*set_power_profile_state)(void *handle,
--			struct amd_pp_profile *request);
--	int (*switch_power_profile)(void *handle,
--			enum amd_pp_profile_type type);
--};
--
--struct amd_powerplay {
--	void *pp_handle;
--	const struct amd_ip_funcs *ip_funcs;
--	const struct amd_powerplay_funcs *pp_funcs;
--};
--
--int amd_powerplay_create(struct amd_pp_init *pp_init,
--				void **handle);
--
--int amd_powerplay_destroy(void *handle);
--
--int amd_powerplay_reset(void *handle);
--
--int amd_powerplay_display_configuration_change(void *handle,
--		const struct amd_pp_display_configuration *input);
--
--int amd_powerplay_get_display_power_level(void *handle,
--		struct amd_pp_simple_clock_info *output);
--
--int amd_powerplay_get_current_clocks(void *handle,
--		struct amd_pp_clock_info *output);
--
--int amd_powerplay_get_clock_by_type(void *handle,
--		enum amd_pp_clock_type type,
--		struct amd_pp_clocks *clocks);
--
--int amd_powerplay_get_clock_by_type_with_latency(void *handle,
--		enum amd_pp_clock_type type,
--		struct pp_clock_levels_with_latency *clocks);
--
--int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
--		enum amd_pp_clock_type type,
--		struct pp_clock_levels_with_voltage *clocks);
--
--int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
--		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
--
--int amd_powerplay_display_clock_voltage_request(void *handle,
--		struct pp_display_clock_request *clock);
--
--int amd_powerplay_get_display_mode_validation_clocks(void *handle,
--		struct amd_pp_simple_clock_info *output);
--
--int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id);
- 
- #endif /* _AMD_POWERPLAY_H_ */
---- linux-4.14/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h	2017-12-14 06:39:58.475903609 +0100
-@@ -283,6 +283,8 @@ static inline bool phm_cap_enabled(const
- 		  (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
- }
- 
-+#define PP_CAP(c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c))
-+
- #define PP_PCIEGenInvalid  0xffff
- enum PP_PCIEGen {
-     PP_PCIEGen1 = 0,                /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
-@@ -295,7 +297,7 @@ typedef enum PP_PCIEGen PP_PCIEGen;
- #define PP_Min_PCIEGen     PP_PCIEGen1
- #define PP_Max_PCIEGen     PP_PCIEGen3
- #define PP_Min_PCIELane    1
--#define PP_Max_PCIELane    32
-+#define PP_Max_PCIELane    16
- 
- enum phm_clock_Type {
- 	PHM_DispClock = 1,
-@@ -373,8 +375,6 @@ struct phm_odn_clock_levels {
- 
- extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
- extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
--extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
--extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
- extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
- extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
- extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
---- linux-4.14/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h	2017-12-14 06:39:58.475903609 +0100
-@@ -32,6 +32,7 @@
- #include "ppatomctrl.h"
- #include "hwmgr_ppt.h"
- #include "power_state.h"
-+#include "cgs_linux.h"
- 
- struct pp_instance;
- struct pp_hwmgr;
-@@ -61,10 +62,6 @@ struct vi_dpm_table {
- 	struct vi_dpm_level dpm_level[1];
- };
- 
--enum PP_Result {
--	PP_Result_TableImmediateExit = 0x13,
--};
--
- #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
- #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
- #define PCIE_PERF_REQ_GEN1         2
-@@ -103,17 +100,6 @@ enum PHM_BackEnd_Magic {
- 	PHM_Rv_Magic          = 0x20161121
- };
- 
--
--#define PHM_PCIE_POWERGATING_TARGET_GFX            0
--#define PHM_PCIE_POWERGATING_TARGET_DDI            1
--#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE     2
--#define PHM_PCIE_POWERGATING_TARGET_PHY            3
--
--typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
--				  void *output, void *storage, int result);
--
--typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
--
- struct phm_set_power_state_input {
- 	const struct pp_hw_power_state *pcurrent_state;
- 	const struct pp_hw_power_state *pnew_state;
-@@ -149,30 +135,6 @@ struct phm_gfx_arbiter {
- 	uint32_t fclk;
- };
- 
--/* Entries in the master tables */
--struct phm_master_table_item {
--	phm_check_function isFunctionNeededInRuntimeTable;
--	phm_table_function tableFunction;
--};
--
--enum phm_master_table_flag {
--	PHM_MasterTableFlag_None         = 0,
--	PHM_MasterTableFlag_ExitOnError  = 1,
--};
--
--/* The header of the master tables */
--struct phm_master_table_header {
--	uint32_t storage_size;
--	uint32_t flags;
--	const struct phm_master_table_item *master_list;
--};
--
--struct phm_runtime_table_header {
--	uint32_t storage_size;
--	bool exit_error;
--	phm_table_function *function_list;
--};
--
- struct phm_clock_array {
- 	uint32_t count;
- 	uint32_t values[1];
-@@ -216,19 +178,6 @@ struct phm_phase_shedding_limits_record
- 	uint32_t    Mclk;
- };
- 
--
--extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
--			      struct phm_runtime_table_header *rt_table,
--			      void *input, void *output);
--
--extern int phm_construct_table(struct pp_hwmgr *hwmgr,
--			       const struct phm_master_table_header *master_table,
--			       struct phm_runtime_table_header *rt_table);
--
--extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
--			     struct phm_runtime_table_header *rt_table);
--
--
- struct phm_uvd_clock_voltage_dependency_record {
- 	uint32_t vclk;
- 	uint32_t dclk;
-@@ -286,6 +235,39 @@ struct phm_vce_clock_voltage_dependency_
- 	struct phm_vce_clock_voltage_dependency_record entries[1];
- };
- 
-+struct pp_smumgr_func {
-+	int (*smu_init)(struct pp_hwmgr  *hwmgr);
-+	int (*smu_fini)(struct pp_hwmgr  *hwmgr);
-+	int (*start_smu)(struct pp_hwmgr  *hwmgr);
-+	int (*check_fw_load_finish)(struct pp_hwmgr  *hwmgr,
-+				    uint32_t firmware);
-+	int (*request_smu_load_fw)(struct pp_hwmgr  *hwmgr);
-+	int (*request_smu_load_specific_fw)(struct pp_hwmgr  *hwmgr,
-+					    uint32_t firmware);
-+	int (*get_argument)(struct pp_hwmgr  *hwmgr);
-+	int (*send_msg_to_smc)(struct pp_hwmgr  *hwmgr, uint16_t msg);
-+	int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr  *hwmgr,
-+					  uint16_t msg, uint32_t parameter);
-+	int (*download_pptable_settings)(struct pp_hwmgr  *hwmgr,
-+					 void **table);
-+	int (*upload_pptable_settings)(struct pp_hwmgr  *hwmgr);
-+	int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
-+	int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
-+	int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
-+	int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
-+	int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
-+	int (*init_smc_table)(struct pp_hwmgr *hwmgr);
-+	int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
-+	int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
-+	int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
-+	uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
-+	uint32_t (*get_mac_definition)(uint32_t value);
-+	bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
-+	int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
-+			struct amd_pp_profile *request);
-+	bool (*is_hw_avfs_present)(struct pp_hwmgr  *hwmgr);
-+};
-+
- struct pp_hwmgr_func {
- 	int (*backend_init)(struct pp_hwmgr *hw_mgr);
- 	int (*backend_fini)(struct pp_hwmgr *hw_mgr);
-@@ -311,10 +293,10 @@ struct pp_hwmgr_func {
- 			    unsigned long, struct pp_power_state *);
- 	int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
- 	int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
--	int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
--	int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
--	int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
--	int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
-+	void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
-+	void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
-+	uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
-+	uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
- 	int (*power_state_set)(struct pp_hwmgr *hwmgr,
- 						const void *state);
- 	int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
-@@ -328,8 +310,8 @@ struct pp_hwmgr_func {
- 	int (*get_temperature)(struct pp_hwmgr *hwmgr);
- 	int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
- 	int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
--	int (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
--	int (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
-+	void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
-+	uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
- 	int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
- 	int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
- 	int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
-@@ -378,6 +360,15 @@ struct pp_hwmgr_func {
- 			struct amd_pp_profile *request);
- 	int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
- 	int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
-+	int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
-+	int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
-+	int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
-+	int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
-+					uint32_t virtual_addr_low,
-+					uint32_t virtual_addr_hi,
-+					uint32_t mc_addr_low,
-+					uint32_t mc_addr_hi,
-+					uint32_t size);
- };
- 
- struct pp_table_func {
-@@ -745,7 +736,7 @@ struct pp_hwmgr {
- 
- 	enum amd_dpm_forced_level dpm_level;
- 	enum amd_dpm_forced_level saved_dpm_level;
--	bool block_hw_access;
-+	enum amd_dpm_forced_level request_dpm_level;
- 	struct phm_gfx_arbiter gfx_arbiter;
- 	struct phm_acp_arbiter acp_arbiter;
- 	struct phm_uvd_arbiter uvd_arbiter;
-@@ -754,19 +745,17 @@ struct pp_hwmgr {
- 	void *pptable;
- 	struct phm_platform_descriptor platform_descriptor;
- 	void *backend;
-+
-+	void *smu_backend;
-+	const struct pp_smumgr_func *smumgr_funcs;
-+	bool is_kicker;
-+	bool reload_fw;
-+
- 	enum PP_DAL_POWERLEVEL dal_power_level;
- 	struct phm_dynamic_state_info dyn_state;
--	struct phm_runtime_table_header setup_asic;
--	struct phm_runtime_table_header power_down_asic;
--	struct phm_runtime_table_header disable_dynamic_state_management;
--	struct phm_runtime_table_header enable_dynamic_state_management;
--	struct phm_runtime_table_header set_power_state;
--	struct phm_runtime_table_header enable_clock_power_gatings;
--	struct phm_runtime_table_header display_configuration_changed;
--	struct phm_runtime_table_header start_thermal_controller;
--	struct phm_runtime_table_header set_temperature_range;
- 	const struct pp_hwmgr_func *hwmgr_func;
- 	const struct pp_table_func *pptable_func;
-+
- 	struct pp_power_state    *ps;
- 	enum pp_power_source  power_source;
- 	uint32_t num_ps;
-@@ -784,26 +773,44 @@ struct pp_hwmgr {
- 	struct amd_pp_display_configuration display_config;
- 	uint32_t feature_mask;
- 
--	/* power profile */
-+	/* UMD Pstate */
- 	struct amd_pp_profile gfx_power_profile;
- 	struct amd_pp_profile compute_power_profile;
- 	struct amd_pp_profile default_gfx_power_profile;
- 	struct amd_pp_profile default_compute_power_profile;
- 	enum amd_pp_profile_type current_power_profile;
-+	bool en_umd_pstate;
-+};
-+
-+struct cgs_irq_src_funcs {
-+	cgs_irq_source_set_func_t set;
-+	cgs_irq_handler_func_t handler;
- };
- 
- extern int hwmgr_early_init(struct pp_instance *handle);
- extern int hwmgr_hw_init(struct pp_instance *handle);
- extern int hwmgr_hw_fini(struct pp_instance *handle);
-+extern int hwmgr_hw_suspend(struct pp_instance *handle);
-+extern int hwmgr_hw_resume(struct pp_instance *handle);
-+extern int hwmgr_handle_task(struct pp_instance *handle,
-+				enum amd_pp_task task_id,
-+				void *input, void *output);
- extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
- 				uint32_t value, uint32_t mask);
- 
--extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
-+extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
- 				uint32_t indirect_port,
- 				uint32_t index,
- 				uint32_t value,
- 				uint32_t mask);
- 
-+extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
-+					uint32_t index,
-+					uint32_t value, uint32_t mask);
-+extern int phm_wait_for_indirect_register_unequal(
-+				struct pp_hwmgr *hwmgr,
-+				uint32_t indirect_port, uint32_t index,
-+				uint32_t value, uint32_t mask);
- 
- 
- extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
-@@ -888,5 +895,58 @@ extern int phm_get_voltage_evv_on_sclk(s
- 	PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval)	\
- 			<< PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
- 
-+#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask)    \
-+		phm_wait_for_indirect_register_unequal(hwmgr,                   \
-+				mm##port##_INDEX, index, value, mask)
-+
-+#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)    \
-+		PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-+
-+#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval)                          \
-+		PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
-+				(fieldval) << PHM_FIELD_SHIFT(reg, field), \
-+					PHM_FIELD_MASK(reg, field) )
-+
-+
-+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,	\
-+				port, index, value, mask)		\
-+	phm_wait_for_indirect_register_unequal(hwmgr,			\
-+		mm##port##_INDEX_11, index, value, mask)
-+
-+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)     \
-+		PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-+
-+#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
-+	PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg,	\
-+		(fieldval) << PHM_FIELD_SHIFT(reg, field),		\
-+		PHM_FIELD_MASK(reg, field))
-+
-+
-+#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr,		\
-+				port, index, value, mask)		\
-+	phm_wait_on_indirect_register(hwmgr,				\
-+		mm##port##_INDEX_11, index, value, mask)
-+
-+#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
-+	PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
-+
-+#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
-+	PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg,		\
-+		(fieldval) << PHM_FIELD_SHIFT(reg, field),		\
-+		PHM_FIELD_MASK(reg, field))
-+
-+#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,         \
-+							index, value, mask) \
-+		phm_wait_for_register_unequal(hwmgr,            \
-+					index, value, mask)
-+
-+#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask)		\
-+	PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,			\
-+				mm##reg, value, mask)
-+
-+#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval)		\
-+	PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg,				\
-+		(fieldval) << PHM_FIELD_SHIFT(reg, field),		\
-+		PHM_FIELD_MASK(reg, field))
- 
- #endif /* _HWMGR_H_ */
---- linux-4.14/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h	2017-12-14 06:39:58.480903613 +0100
-@@ -29,10058 +29,1764 @@
- #define mmCP_HYP_MEC2_UCODE_ADDR	0xf81c
- #define mmCP_HYP_MEC2_UCODE_DATA	0xf81d
- 
--enum PWR_Command {
--	PwrCmdNull = 0,
--	PwrCmdWrite,
--	PwrCmdEnd,
--	PwrCmdMax
--};
--
--typedef enum PWR_Command PWR_Command;
--
- struct PWR_Command_Table {
--	PWR_Command        command;
- 	uint32_t              data;
- 	uint32_t reg;
- };
- 
- typedef struct PWR_Command_Table PWR_Command_Table;
- 
-+struct PWR_DFY_Section {
-+	uint32_t dfy_cntl;
-+	uint32_t dfy_addr_hi, dfy_addr_lo;
-+	uint32_t dfy_size;
-+	uint32_t dfy_data[];
-+};
-+
-+typedef struct PWR_DFY_Section PWR_DFY_Section;
-+
-+static const PWR_Command_Table pwr_virus_table_pre[] = {
-+	{ 0x00000000, mmRLC_CNTL                                 },
-+	{ 0x00000002, mmRLC_SRM_CNTL                             },
-+	{ 0x15000000, mmCP_ME_CNTL                               },
-+	{ 0x50000000, mmCP_MEC_CNTL                              },
-+	{ 0x80000004, mmCP_DFY_CNTL                              },
-+	{ 0x0840800a, mmCP_RB0_CNTL                              },
-+	{ 0xf30fff0f, mmTCC_CTRL                                 },
-+	{ 0x00000002, mmTCC_EXE_DISABLE                          },
-+	{ 0x000000ff, mmTCP_ADDR_CONFIG                          },
-+	{ 0x540ff000, mmCP_CPC_IC_BASE_LO                        },
-+	{ 0x000000b4, mmCP_CPC_IC_BASE_HI                        },
-+	{ 0x00010000, mmCP_HYP_MEC1_UCODE_ADDR                   },
-+	{ 0x00041b75, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000710e8, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000910dd, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000a1081, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000b016f, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000c0e3c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000d10ec, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000e0188, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00101b5d, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00150a6c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00170c5e, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x001d0c8c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x001e0cfe, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00221408, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00370d7b, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00390dcb, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x003c142f, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x003f0b27, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00400e63, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00500f62, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00460fa7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00490fa7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x005811d4, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00680ad6, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00760b00, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00780b0c, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00790af7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x007d1aba, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x007e1abe, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00591260, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x005a12fb, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00861ac7, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x008c1b01, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x008d1b34, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00a014b9, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00a1152e, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00a216fb, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00a41890, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00a31906, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00a50b14, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00621387, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x005c0b27, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00160a75, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
-+	{ 0x00010000, mmCP_HYP_MEC2_UCODE_ADDR                   },
-+	{ 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00150a6c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00170c5e, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x001d0c8c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x001e0cfe, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00221408, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00370d7b, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00390dcb, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x003c142f, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x003f0b27, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00400e63, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00500f62, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00460fa7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00490fa7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x005811d4, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00680ad6, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00760b00, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00780b0c, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00790af7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x007d1aba, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x007e1abe, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00591260, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x005a12fb, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00861ac7, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x008c1b01, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x008d1b34, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00a014b9, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00a1152e, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00a216fb, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00a41890, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00a31906, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00a50b14, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00621387, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x005c0b27, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00160a75, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
-+	{ 0x00000000, 0xFFFFFFFF                                 },
-+};
-+
-+static const PWR_DFY_Section pwr_virus_section1 = {
-+	.dfy_cntl = 0x80000004,
-+	.dfy_addr_hi = 0x000000b4,
-+	.dfy_addr_lo = 0x540fe800,
-+	.dfy_data = {
-+	0x7e000200, 0x7e020201, 0x7e040204, 0x7e060205, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0x0a080102, 0x0a0a0701, 0x0a080102, 0x0a0a0701,
-+	0x0a080500, 0x0a0a0303, 0x0a080500, 0x0a0a0303, 0xbf810000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000005, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x54106f00, 0x000400b4, 0x00004000, 0x00804fac, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	},
-+	.dfy_size = 416
-+};
-+
-+static const PWR_DFY_Section pwr_virus_section2 = {
-+	.dfy_cntl = 0x80000004,
-+	.dfy_addr_hi = 0x000000b4,
-+	.dfy_addr_lo = 0x540fef00,
-+	.dfy_data = {
-+	0xc0031502, 0x00001e00, 0x00000001, 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	},
-+	.dfy_size = 16
-+};
- 
--#define PWR_VIRUS_TABLE_SIZE  10031
-+static const PWR_DFY_Section pwr_virus_section3 = {
-+	.dfy_cntl = 0x80000004,
-+	.dfy_addr_hi = 0x000000b4,
-+	.dfy_addr_lo = 0x540ff000,
-+	.dfy_data = {
-+	0xc424000b, 0x80000145, 0x94800001, 0x94c00001, 0x95000001, 0x95400001, 0x95800001, 0xdc810000,
-+	0xdcc10000, 0xdd010000, 0xdd410000, 0xdd810000, 0xc4080061, 0xd8400013, 0xd8000003, 0xc40c0001,
-+	0x24ccffff, 0x3cd08000, 0x9500fffd, 0x1cd0ffcf, 0x7d018001, 0xc4140004, 0x050c0019, 0xd8400008,
-+	0x84c00000, 0x80000023, 0x80000067, 0x8000006a, 0x8000006d, 0x80000079, 0x80000084, 0x8000008f,
-+	0x80000099, 0x800000a0, 0x800000af, 0xd8400053, 0xc4080007, 0x388c0001, 0x08880002, 0x04100003,
-+	0x94c00005, 0x98800003, 0x04100004, 0x8000002d, 0x04100005, 0x8c00003f, 0x8c000043, 0x28cc0000,
-+	0xccc00050, 0x8c000055, 0x28080001, 0xcc000004, 0x7d808001, 0xd8400013, 0xd88130b8, 0xcd400008,
-+	0xdc180000, 0xdc140000, 0xdc100000, 0xdc0c0000, 0xcc800005, 0xdc080000, 0x80000168, 0xc40c000e,
-+	0x28cc0008, 0xccc00013, 0x90000000, 0xcd013278, 0xc4113278, 0x95000001, 0x24cc0700, 0xd8400029,
-+	0xc4113255, 0xcd01324f, 0xc4113254, 0x1d10ffdf, 0xcd013254, 0x10cc0014, 0x1d10c017, 0x7d0d000a,
-+	0xd8400013, 0xd8400008, 0xcd0130b7, 0x14cc0010, 0x90000000, 0xd9c00036, 0x8000005d, 0xd8400013,
-+	0xc00c4000, 0xccc130b5, 0xc40c000e, 0x28cc0008, 0xccc00013, 0xc40c0021, 0x14d00011, 0x9500fffe,
-+	0xdc030000, 0xd800000c, 0xd800000d, 0xc40c005e, 0x94c01b10, 0xd8400013, 0x90000000, 0xc00e0080,
-+	0xccc130b5, 0x8000013b, 0xc00e0800, 0xccc130b5, 0x8000013b, 0xd8400053, 0x04100006, 0x8c00003f,
-+	0x8c000043, 0x28cc0000, 0xccc00050, 0x8c000055, 0x280c0008, 0xccc00052, 0xd8000021, 0x28180039,
-+	0x80000034, 0xd8400053, 0x04100007, 0x8c00003f, 0x8c000043, 0x28cc0001, 0xccc00050, 0x8c000055,
-+	0x280c0010, 0xccc00052, 0x28180039, 0x80000034, 0xd8400053, 0x04100008, 0x8c00003f, 0x8c000043,
-+	0x28cc0003, 0xccc00050, 0x8c000055, 0x280c0020, 0xccc00052, 0x28180039, 0x80000034, 0xdc030000,
-+	0xd8000069, 0x28080001, 0xc428000d, 0x7ca88004, 0xcc800079, 0x04280001, 0xcc00006f, 0x8000013b,
-+	0x80000034, 0x04100010, 0x8c00003f, 0x8c000043, 0xccc00078, 0x8c000055, 0x28180080, 0x80000034,
-+	0x04100001, 0xc40c000e, 0x28cc0008, 0xccc00013, 0xcd013278, 0xc4113278, 0x95000001, 0xc00c4000,
-+	0xc4113254, 0x1d10c017, 0xd8400013, 0xd8400008, 0xccc130b5, 0xcd0130b7, 0x8000013b, 0x95c00001,
-+	0x96000001, 0x96400001, 0x96800001, 0x96c00001, 0x97000001, 0x97400001, 0x97800001, 0x97c00001,
-+	0xdc810000, 0xc40c000c, 0xcd4c0380, 0xcdcc0388, 0x55dc0020, 0xcdcc038c, 0xce0c0390, 0x56200020,
-+	0xce0c0394, 0xce4c0398, 0x56640020, 0xce4c039c, 0xce8c03a0, 0x56a80020, 0xce8c03a4, 0xcecc03a8,
-+	0x56ec0020, 0xcecc03ac, 0xcf0c03b0, 0x57300020, 0xcf0c03b4, 0xcf4c03b8, 0x57740020, 0xcf4c03bc,
-+	0xcf8c03c0, 0x57b80020, 0xcf8c03c4, 0xcfcc03c8, 0x57fc0020, 0xcfcc03cc, 0xd9000033, 0xc41c0009,
-+	0x25dc0010, 0x95c0fffe, 0xd8400013, 0xc41c000c, 0x05dc002f, 0xcdc12009, 0xc41d200a, 0xd8400013,
-+	0xcc012009, 0xd9000034, 0x25e01c00, 0x12200013, 0x25e40300, 0x12640008, 0x25e800c0, 0x12a80002,
-+	0x25ec003f, 0x7e25c00a, 0x7eae400a, 0x7de5c00a, 0xddc10000, 0xc02ee000, 0xcec1c200, 0xc40c005f,
-+	0xccc00037, 0x24d000ff, 0x31100006, 0x9500007b, 0x8c000190, 0xdc1c0000, 0xd8400013, 0xcdc1c200,
-+	0xc40c000c, 0xc4df0388, 0xc4d7038c, 0x51540020, 0x7d5dc01a, 0xc4e30390, 0xc4d70394, 0x51540020,
-+	0x7d62001a, 0xc4e70398, 0xc4d7039c, 0x51540020, 0x7d66401a, 0xc4eb03a0, 0xc4d703a4, 0x51540020,
-+	0x7d6a801a, 0xc4ef03a8, 0xc4d703ac, 0x51540020, 0x7d6ec01a, 0xc4f303b0, 0xc4d703b4, 0x51540020,
-+	0x7d73001a, 0xc4f703b8, 0xc4d703bc, 0x51540020, 0x7d77401a, 0xc4fb03c0, 0xc4d703c4, 0x51540020,
-+	0x7d7b801a, 0xc4ff03c8, 0xc4d703cc, 0x51540020, 0x7d7fc01a, 0xdc080000, 0xcc800013, 0xc4d70380,
-+	0xc4080001, 0x1c88001c, 0xcd400008, 0xc40c0083, 0x94c00010, 0xdc0e0000, 0x94c0000e, 0xc40c0082,
-+	0x24d00001, 0x9900000b, 0x18cc01e3, 0x3cd00004, 0x95000008, 0xc40c0085, 0x18cc006a, 0x98c00005,
-+	0xc40c0082, 0x18cc01e3, 0x3cd00004, 0x9900fffa, 0xdc180000, 0xdc140000, 0xdc100000, 0xdc0c0000,
-+	0xcc800004, 0xdc080000, 0x90000000, 0xc4080001, 0x1c88001c, 0xcd400008, 0xdc180000, 0xdc140000,
-+	0xdc100000, 0xdc0c0000, 0xcc800004, 0xdc080000, 0x90000000, 0xd8400051, 0xc428000c, 0x04180018,
-+	0x32640002, 0x9a80001f, 0x9a40001e, 0xcd800013, 0xc4293265, 0x040c0000, 0x1aac0027, 0x2aa80080,
-+	0xce813265, 0x9ac00017, 0xd80002f1, 0x04080002, 0x08880001, 0xd8080250, 0xd8080258, 0xd8080230,
-+	0xd8080238, 0xd8080240, 0xd8080248, 0xd8080268, 0xd8080270, 0xd8080278, 0xd8080280, 0xd8080228,
-+	0xd8000367, 0x9880fff3, 0x04080010, 0x08880001, 0xd80c0309, 0xd80c0319, 0x04cc0001, 0x9880fffc,
-+	0x7c408001, 0x88000000, 0xc00e0100, 0xd8400013, 0xd8400008, 0xccc130b5, 0x8000016e, 0xc4180032,
-+	0x29980008, 0xcd800013, 0x95800001, 0x7c40c001, 0x18d0003f, 0x24d4001f, 0x24d80001, 0x155c0001,
-+	0x05e80180, 0x9900000b, 0x202c003d, 0xcd800010, 0xcec1325b, 0xc42d325b, 0x96c00001, 0x86800000,
-+	0x80000168, 0x80000aa7, 0x80000bfc, 0x800012e9, 0xc4200007, 0x0a200001, 0xce000010, 0x80001b70,
-+	0x7c40c001, 0x8c000190, 0xc410001b, 0xd8000032, 0xd8000031, 0x9900091a, 0x7c408001, 0x88000000,
-+	0x24d000ff, 0x05280196, 0x18d4fe04, 0x29540008, 0xcd400013, 0x86800000, 0x800001b4, 0x8000032b,
-+	0x80000350, 0x80000352, 0x8000035f, 0x80000701, 0x8000047c, 0x8000019f, 0x80000800, 0xc419325b,
-+	0x1d98001f, 0xcd81325b, 0x8c00003f, 0xc4140004, 0xd8400008, 0x04100002, 0x8c000043, 0x28cc0002,
-+	0xccc00050, 0xc43c0044, 0x27fc0003, 0x9bc00002, 0x97c00006, 0xc00c4000, 0xccc130b5, 0x8c000055,
-+	0xd8400013, 0xd88130b8, 0xcd400008, 0x90000000, 0xd8400008, 0xcd400013, 0x7d40c001, 0xd8400028,
-+	0xd8400029, 0xd9400036, 0xc4193256, 0xc41d3254, 0x15540008, 0xcd400009, 0xcd40005b, 0xcd40005e,
-+	0xcd40005d, 0xd840006d, 0xc421325a, 0xc42d3249, 0x11540015, 0x19a4003c, 0x1998003f, 0x1af0007d,
-+	0x11dc000b, 0x1264001f, 0x15dc000d, 0x7d65400a, 0x13300018, 0x1a38003f, 0x7dd5c00a, 0x7df1c00a,
-+	0xcd800045, 0xcdc00100, 0xc411326a, 0xc415326b, 0xc419326c, 0xc41d326d, 0xc425326e, 0xc4293279,
-+	0xce800077, 0xcd000056, 0xcd400057, 0xcd800058, 0xcdc00059, 0xc4193265, 0x259c8000, 0x99c00004,
-+	0xce40005a, 0x29988000, 0xcd813265, 0xc4113248, 0x2510000f, 0xcd000073, 0xc418000d, 0xc411326f,
-+	0x17300019, 0x97000009, 0x25140fff, 0x95400007, 0xd800003a, 0x8c001b6d, 0xc4153279, 0xcd400077,
-+	0xcd00005f, 0xd8000075, 0x26f00001, 0x15100010, 0x7d190004, 0xcd000035, 0x97000035, 0x1af07fe8,
-+	0xd8800013, 0xd8400010, 0xd8400008, 0xcf00000d, 0xcf00000a, 0x8c001427, 0x04340022, 0x07740001,
-+	0x04300010, 0xdf430000, 0x7c434001, 0x7c408001, 0xd4412e01, 0x0434001e, 0xdf430000, 0xd4400078,
-+	0xdf030000, 0xd4412e40, 0xd8400013, 0xcc41c030, 0xcc41c031, 0xc43dc031, 0xccc00013, 0x04343000,
-+	0xc4113246, 0xc41d3245, 0xcf413267, 0x51100020, 0x7dd1c01a, 0xc4353267, 0x45dc0160, 0xc810001f,
-+	0x1b4c0057, 0x1b700213, 0x1b740199, 0x7f4f400a, 0x7f73400a, 0x55180020, 0x2198003f, 0xd1c00025,
-+	0xcf400024, 0xcd000026, 0xcd800026, 0xd8400027, 0x9bc00001, 0x248dfffe, 0xd8800013, 0xccc12e00,
-+	0x7c434001, 0x7c434001, 0x8c00142b, 0xc43c000e, 0x1af4007d, 0x2bfc0008, 0x33740003, 0x26d80001,
-+	0xcfc00013, 0x1ae8003e, 0x9680000c, 0xc4253277, 0x26680001, 0x96800009, 0x2a640002, 0xce413277,
-+	0xd8400013, 0xc4253348, 0xce413348, 0xc4253348, 0x96400001, 0xcfc00013, 0x9b400003, 0x958000d8,
-+	0x80000315, 0xc4253277, 0x04303000, 0x26680001, 0xcf013267, 0xc4193246, 0xc41d3245, 0xc4313267,
-+	0x96800041, 0x51980020, 0x1b342010, 0x7d9d801a, 0x1714000c, 0x25540800, 0x1b30c012, 0x459801b0,
-+	0x7d77400a, 0x7f37000a, 0x2b300000, 0xcf00001c, 0xd180001e, 0xd8400021, 0x04240010, 0x199c01e2,
-+	0x7e5e4002, 0x3e5c0004, 0x3e540002, 0xc428000f, 0x9a80ffff, 0x95c00006, 0xc80c0011, 0xc8140011,
-+	0x54d00020, 0x55580020, 0x80000282, 0x95400015, 0xc80c0011, 0x0a640002, 0x041c0001, 0x45980008,
-+	0x54d00020, 0x96400004, 0xc8140011, 0x45980004, 0x041c0000, 0xcf00001c, 0xd180001e, 0xd8400021,
-+	0xc428000f, 0x9a80ffff, 0x99c00003, 0xc8180011, 0x80000282, 0xc8140011, 0x55580020, 0x80000282,
-+	0x45980004, 0xc80c0011, 0xcf00001c, 0xd180001e, 0xd8400021, 0xc428000f, 0x9a80ffff, 0xc8100011,
-+	0xc8140011, 0x55580020, 0xd8400013, 0xccc1334e, 0xcd01334f, 0xcd413350, 0xcd813351, 0xd881334d,
-+	0xcfc00013, 0xc4193273, 0xc41d3275, 0xc40d3271, 0xc4113270, 0xc4153274, 0x50cc0020, 0x7cd0c01a,
-+	0x7cdcc011, 0x05900008, 0xcd00006a, 0xcdc0006b, 0xc41d3272, 0x7d594002, 0x54d00020, 0xd8800013,
-+	0xccc12e23, 0xcd012e24, 0xcdc12e25, 0xcfc00013, 0xc4193246, 0xc41d3245, 0xc4313267, 0x15540002,
-+	0x51980020, 0x7d9d801a, 0xc81c001f, 0x1b340057, 0x1b280213, 0x1b300199, 0x45980198, 0x7f37000a,
-+	0x7f2b000a, 0x55e40020, 0xcf000024, 0xd1800025, 0xcdc00026, 0xce400026, 0xd8400027, 0xcd40000d,
-+	0xcd40000a, 0xc40d3249, 0x20cc003c, 0xccc13249, 0xc4113274, 0xdd430000, 0xc01e0001, 0x29dc0002,
-+	0x04280000, 0xd8000036, 0xcc400078, 0xcc400078, 0x2d540002, 0x95400022, 0x078c0000, 0x07d40000,
-+	0x8c00120d, 0x8c001239, 0x8c001232, 0x04f80000, 0x057c0000, 0xcdc00013, 0xc414000d, 0xc41c0019,
-+	0x7dd5c005, 0x25dc0001, 0xd840007c, 0xd8400074, 0xd8400069, 0xc40c005e, 0x94c018a6, 0xd4412e22,
-+	0xd800007c, 0xc40c005e, 0x94c018a2, 0x95c00007, 0xc40c0019, 0x7cd4c005, 0x24cc0001, 0x94c00008,
-+	0x9680fffc, 0x800002e3, 0xc40c0057, 0x7cd0c002, 0x94c00003, 0x9680fffd, 0x800002e3, 0xd8000069,
-+	0xcfc00013, 0xcd013273, 0xcd013275, 0xd8000074, 0xc414005e, 0x9540188f, 0xcfc00013, 0xc40d3249,
-+	0xc013cfff, 0x7cd0c009, 0xccc13249, 0x9680000b, 0xc40c0077, 0x38d00001, 0x99000006, 0x04cc0002,
-+	0xdcc30000, 0xc40c005e, 0x94c01882, 0xd4400078, 0xd800000d, 0x80000304, 0x7c41c001, 0x7c41c001,
-+	0xd840002f, 0xc41c0015, 0x95c0ffff, 0xd8400030, 0xc41c0016, 0x95c0ffff, 0xd8000030, 0xc41c0016,
-+	0x99c0ffff, 0xd800002f, 0xc41c0015, 0x99c0ffff, 0xc81c001f, 0x49980198, 0x55e40020, 0x459801a0,
-+	0xcf000024, 0xd1800025, 0xcdc00026, 0xce400026, 0xd8400027, 0x04302000, 0xcfc00013, 0xcf013267,
-+	0xc4313267, 0x96800004, 0x97000001, 0xd8000036, 0x80000329, 0xd8800013, 0xcc812e00, 0x04302000,
-+	0xcfc00013, 0xcf013267, 0xc4313267, 0x97000001, 0xc4193256, 0xc42d3249, 0x16ec001f, 0xd8000028,
-+	0xd800002b, 0x1998003e, 0xcec00031, 0xd8000036, 0xd8000010, 0x97800004, 0xd8400010, 0xce00000a,
-+	0x1a18003e, 0xcd800008, 0x90000000, 0xc4380004, 0xd8400008, 0xd8400013, 0xd88130b8, 0x04100000,
-+	0x7d43c001, 0xcd400013, 0xc4093249, 0x1888003e, 0x94800015, 0xd8400074, 0x8c000671, 0xcd400013,
-+	0x9a400006, 0xc419324c, 0x259c0001, 0x1598001f, 0x95c0000d, 0x9580000c, 0x99000003, 0xd8400036,
-+	0x04100001, 0xc40c0021, 0x14d80011, 0x24dc00ff, 0x31e00002, 0x31dc0003, 0x9580fff0, 0x9a000003,
-+	0x99c00002, 0xd9c00036, 0x94800004, 0xd8000074, 0xc418005e, 0x95801827, 0xcf800008, 0x90000000,
-+	0xd8800036, 0x90000000, 0xd8c00036, 0xc424000b, 0x32640002, 0x9a400004, 0xc4180014, 0x9580ffff,
-+	0xd840002f, 0xc40c0021, 0x14dc0011, 0x95c0fffe, 0xccc00037, 0x8c000190, 0x90000000, 0xd8400008,
-+	0xd800006d, 0xc41d3246, 0xc4193245, 0x51dc0020, 0x7d9d801a, 0xd8400028, 0xd8400029, 0xc420000b,
-+	0x32200002, 0x9a0000ad, 0x04200032, 0xd9000010, 0xde030000, 0xd8400033, 0x04080000, 0xc43c0009,
-+	0x27fc0002, 0x97c0fffe, 0xc42c0015, 0x96c0ffff, 0xd800002e, 0xc42d3249, 0x1af4003e, 0x9740004d,
-+	0xc428000d, 0xc4080060, 0x7ca88005, 0x24880001, 0x7f4b4009, 0x97400046, 0xc4313274, 0xc4100057,
-+	0x7d33400c, 0x97400009, 0x28240100, 0x7e6a4004, 0xce400079, 0x1eecffdd, 0xcec13249, 0xcf013273,
-+	0xcf013275, 0x800003c3, 0xc429326f, 0x1aa80030, 0x96800006, 0x28240001, 0xc428000d, 0x06a80008,
-+	0x7e6a8004, 0xce800035, 0xc41d3272, 0x25cc0001, 0x10cc0004, 0x19e80042, 0x25dc0006, 0x11dc0001,
-+	0x7e8e800a, 0x7de9c00a, 0xc40d3271, 0xc4293270, 0x50cc0020, 0x7ce8c01a, 0x7cd30011, 0x11e80007,
-+	0x2aa80000, 0xce80001c, 0xd300001e, 0xd8400021, 0xc428000f, 0x9a80ffff, 0xc4300011, 0x1b30003f,
-+	0x33300000, 0xc4240059, 0x1660001f, 0x7e320009, 0xc0328000, 0x7e72400a, 0x0430000c, 0x9a000002,
-+	0x04300008, 0xc02ac000, 0x7d310002, 0x17300002, 0x2aa87600, 0x7cd0c011, 0xcdc00024, 0xd0c00025,
-+	0xce800026, 0x04280222, 0xce800026, 0x96000002, 0xce400026, 0xd8400027, 0xc4280058, 0x22ec003d,
-+	0xcec13249, 0xcd013273, 0xce813275, 0xd800007b, 0xc8380018, 0x57b00020, 0x04343108, 0xc429325d,
-+	0x040c3000, 0x13740008, 0x2374007e, 0x32a80003, 0xccc13267, 0xc40d3267, 0x18ec0057, 0x18e40213,
-+	0x18cc0199, 0x7cecc00a, 0x7ce4c00a, 0x94800003, 0xd4400078, 0x800003e7, 0x04200022, 0xde030000,
-+	0xccc00024, 0xd1800025, 0xcf400026, 0xd4400026, 0xd8400027, 0x04200010, 0xde030000, 0xccc00024,
-+	0x45980104, 0xd1800025, 0xd4400026, 0xcf800026, 0xcf000026, 0xd8400027, 0x49980104, 0x9a80000a,
-+	0xc81c001f, 0x45980168, 0x55e00020, 0xccc00024, 0xd1800025, 0xcdc00026, 0xce000026, 0xd8400027,
-+	0x800003f2, 0x8c000448, 0xcd400013, 0x040c2000, 0xccc13267, 0xc40d3267, 0x94c00001, 0xc40d3249,
-+	0x18cc003e, 0xd8400030, 0xc42c0016, 0x96c0ffff, 0xd8000030, 0xc42c0016, 0x9ac0ffff, 0xd800002f,
-+	0xc42c0015, 0x9ac0ffff, 0xd8400034, 0xc4300025, 0xc4340024, 0xc4380081, 0xcf813279, 0xcf41326e,
-+	0xcf01326d, 0x94c0000d, 0x254c0700, 0xc424001e, 0x10cc0010, 0x1a641fe8, 0x28cc0726, 0x2a640200,
-+	0xd8400013, 0xccc1237b, 0x2264003f, 0xcd400013, 0xd8813260, 0xce41325b, 0xc4240033, 0xc4280034,
-+	0xd9000036, 0xd8000010, 0x8c001427, 0x96400006, 0xde430000, 0xce40000c, 0xc40c005e, 0x94c01755,
-+	0xd4400078, 0x9680000a, 0xce80000a, 0x06a80002, 0xd8400010, 0xde830000, 0xce80000d, 0xc40c005e,
-+	0x94c0174c, 0xd4400078, 0xd8000010, 0x8c00142b, 0xc4393265, 0x2bb80040, 0xd8400032, 0xcf813265,
-+	0xc4200012, 0x9a00ffff, 0xc4100044, 0x19180024, 0xc8100072, 0x551c003f, 0x99c00003, 0x95800010,
-+	0x8000043d, 0xc00c8000, 0xd840006c, 0x28200000, 0x8000043f, 0xc00c4000, 0x282000f0, 0xcd400013,
-+	0xd8400008, 0xc4113255, 0xcd01324f, 0xd8400013, 0xd88130b8, 0xccc130b5, 0xce000053, 0x90000000,
-+	0x195c00e8, 0xc4100004, 0x2555fff0, 0xc0360001, 0x042c0000, 0x29540001, 0xd8400008, 0x04240000,
-+	0x04280004, 0xc420000b, 0x32200002, 0x9a000009, 0xcd400013, 0xcec1c200, 0xc5e124dc, 0x0aa80001,
-+	0x7ef6c001, 0x7e624001, 0x96000001, 0x9a80fff9, 0xc02ee000, 0xcd400013, 0x2555fff0, 0xcec1c200,
-+	0x29540008, 0xc81c001f, 0xcd400013, 0x55e00020, 0xc42d3255, 0xc4353259, 0xd8013260, 0x45980158,
-+	0xccc00024, 0xd1800025, 0xcdc00026, 0xce000026, 0xd8400027, 0x49980158, 0x45980170, 0xc4200012,
-+	0x16200010, 0x9a00fffe, 0xccc00024, 0xd1800025, 0xc429324f, 0xce400026, 0xce800026, 0xcec00026,
-+	0xcf400026, 0xd8400027, 0xcd000008, 0x90000000, 0xc40d325b, 0x7d43c001, 0x195400e8, 0x1154000a,
-+	0x18dc00e8, 0x05e80488, 0x18d0006c, 0x18f807f0, 0x18e40077, 0x18ec0199, 0x7e6e400a, 0x86800000,
-+	0x8000048e, 0x80000494, 0x800004de, 0x80000685, 0x80000686, 0x800006ac, 0x1ccc001f, 0xccc1325b,
-+	0xc411325d, 0x251001ef, 0xcd01325d, 0x90000000, 0xc4293254, 0x1264000a, 0xc4300004, 0x7d79400a,
-+	0x7e7a400a, 0x52a8001e, 0x15180001, 0x7d69401a, 0x202c007d, 0xcec1325b, 0x95000008, 0x95800028,
-+	0xc42d3267, 0xc4193246, 0xc41d3245, 0x1aec0028, 0xc40d325c, 0x800004cc, 0xc42d3256, 0xc419324e,
-+	0x26e8003f, 0x1aec003e, 0x12f4000e, 0xc41d324d, 0xc40d324f, 0x7d75401a, 0x04100002, 0x7d290004,
-+	0x7f8f4001, 0x7f52800f, 0x51980020, 0x7d9d801a, 0x50e00002, 0x51980008, 0x9a800002, 0x800004d1,
-+	0x7d0dc002, 0x6665fc00, 0x7e5e401a, 0xcec00008, 0x7da1c011, 0xd140000b, 0xd1c00002, 0x2a644000,
-+	0xce400002, 0x7f534002, 0x6665fc00, 0x7e76401a, 0xd1800002, 0xce400002, 0x800004d7, 0xc42d325a,
-+	0xc4193258, 0x1aec003e, 0xc41d3257, 0xc4213259, 0x12f4000e, 0x7d75401a, 0x51980020, 0x52200002,
-+	0x7d9d801a, 0xcec00008, 0x7da1c011, 0xd140000b, 0xd1c00002, 0x2a644000, 0xce400002, 0x202c003d,
-+	0xcf000008, 0xcfc00013, 0xcec1325b, 0xc42d325b, 0x96c00001, 0x90000000, 0xc4193260, 0x259c0007,
-+	0x15980004, 0x05e804e3, 0x86800000, 0x800004e7, 0x800004f0, 0x80000505, 0x8000016a, 0xc4380004,
-+	0xcfc00013, 0xd8400008, 0xc435325d, 0xd801325b, 0x277401ef, 0xcf41325d, 0xcf800008, 0x90000000,
-+	0xc4380004, 0xd8400008, 0x8c000671, 0x9640fff4, 0x17e00008, 0xc418000d, 0xce000009, 0xd84131db,
-+	0xcf800008, 0xcd800009, 0xc430001e, 0xcfc00013, 0xc42d325b, 0x1b301ff8, 0x2b300400, 0x2330003f,
-+	0x26edf000, 0x7ef2c00a, 0xd8413260, 0xcec1325b, 0x90000000, 0x05a80507, 0x86800000, 0x8000050c,
-+	0x80000528, 0x8000057d, 0x800005c2, 0x800005f3, 0xc4380004, 0xd8400008, 0x8c000671, 0xcfc00013,
-+	0x9a400012, 0x1bd400e8, 0xc42c004a, 0xcd40005e, 0xc41c004d, 0xcec0005e, 0x99c0000c, 0xc4100019,
-+	0x7d150005, 0x25100001, 0x99000008, 0x8c00063b, 0xcfc00013, 0xc4113277, 0x2511fffd, 0xcd013277,
-+	0xd801326f, 0x80000624, 0x04240012, 0x1be00fe4, 0xce413260, 0xce000066, 0xcf800008, 0x90000000,
-+	0xd8400068, 0xc4380004, 0xd8400008, 0x8c000671, 0xcfc00013, 0x9a400013, 0x1bd400e8, 0xc42c004a,
-+	0xcd40005e, 0xc41c004d, 0xcec0005e, 0x99c0000d, 0xc4100019, 0x7d150005, 0x25100001, 0x99000009,
-+	0xd8400067, 0x8c00063b, 0xcfc00013, 0xc4113277, 0x2511fffd, 0xcd013277, 0xd801326f, 0x80000624,
-+	0x1bd400e8, 0xc42c0060, 0x7ed6c005, 0x26ec0001, 0xc4113271, 0xc4153270, 0xc4193272, 0xc41d3273,
-+	0x04280022, 0x51100020, 0x7d51401a, 0xc4113274, 0xc4213275, 0xc4253276, 0xc4313248, 0xd1400061,
-+	0x2730000f, 0x13300010, 0x7db1800a, 0xcd800060, 0x96c00002, 0x05dc0008, 0xcdc00062, 0x042c3000,
-+	0xcd000063, 0xce000064, 0xce400065, 0xcec13267, 0xc42d3246, 0xc4313245, 0xc4353267, 0xce813260,
-+	0x52ec0020, 0x7ef2c01a, 0xc820001f, 0x1b700057, 0x1b680213, 0x1b740199, 0x46ec0188, 0x7f73400a,
-+	0x7f6b400a, 0x56240020, 0xcf400024, 0xd2c00025, 0xce000026, 0xce400026, 0x042c2000, 0xd8400027,
-+	0xc418000d, 0x17e00008, 0xce000009, 0xcec13267, 0xc42d3267, 0x26e01000, 0x9a00fffe, 0xd8400013,
-+	0xd9c131fc, 0xcd800009, 0xcf800008, 0x96c00001, 0x90000000, 0xc4380004, 0xd8400008, 0xc4113277,
-+	0xc41c000b, 0xc420000c, 0x11dc0002, 0x7de1c001, 0x11dc0008, 0x29dc0001, 0x25140001, 0x191807e4,
-+	0x192007ec, 0x95400004, 0xd8400013, 0xcdc1334a, 0xcfc00013, 0x9580000e, 0x09980001, 0x041c0001,
-+	0x95800005, 0x09980001, 0x51dc0001, 0x69dc0001, 0x9980fffd, 0x7de20014, 0x561c0020, 0xd8400013,
-+	0xce013344, 0xcdc13345, 0xcfc00013, 0x95400022, 0x042c3000, 0xcec13267, 0xc42d3246, 0xc4313245,
-+	0xc4353267, 0xd8400013, 0xc425334d, 0x26640001, 0x9640fffe, 0xc419334e, 0xc41d334f, 0xc4213350,
-+	0xc4253351, 0x52ec0020, 0x1b680057, 0x7ef2c01a, 0x1b700213, 0x1b740199, 0x46ec01b0, 0x7f6b400a,
-+	0x7f73400a, 0xcfc00013, 0xcf400024, 0xd2c00025, 0xcd800026, 0xcdc00026, 0xce000026, 0xce400026,
-+	0x042c2000, 0xd8400027, 0xcec13267, 0xc42d3267, 0x96c00001, 0x04280032, 0xce813260, 0xd8800068,
-+	0xcf800008, 0x90000000, 0xc4380004, 0xd8400008, 0x2010007d, 0xcd01325b, 0xc411325b, 0x1910003e,
-+	0x9500fffe, 0x04100040, 0xcd00001b, 0xd8400021, 0xc410000f, 0x9900ffff, 0x04100060, 0xcd00001b,
-+	0xd8400021, 0xc410000f, 0x9900ffff, 0xcfc00013, 0x2010003d, 0xcd01325b, 0xc4113277, 0x25140001,
-+	0x191807e4, 0x9540000b, 0x2511fffd, 0xcd013277, 0xc41c000b, 0xc420000c, 0x11dc0002, 0x7de1c001,
-+	0x11dc0008, 0xd8400013, 0xcdc1334a, 0xcfc00013, 0x95800005, 0xd8400013, 0xd8013344, 0xd8013345,
-+	0xcfc00013, 0xc4180050, 0xc41c0052, 0x04280042, 0xcd813273, 0xcdc13275, 0xce813260, 0xd9000068,
-+	0xd8400067, 0xcf800008, 0x90000000, 0x07d40000, 0x8c00120d, 0x8c00124f, 0x8c001232, 0x057c0000,
-+	0x042c3000, 0xc4380004, 0xcfc00013, 0xd8400008, 0xcec13267, 0xc42d3246, 0xc4313245, 0xc4353267,
-+	0x52ec0020, 0x7ef2c01a, 0x1b680057, 0x1b700213, 0x1b740199, 0xc820001f, 0x46ec0190, 0x7f6b400a,
-+	0x7f73400a, 0x56240020, 0xcf400024, 0xd2c00025, 0xce000026, 0xce400026, 0x042c2000, 0xd8400027,
-+	0xcfc00013, 0xcec13267, 0xc4153249, 0x2154003d, 0xc41c0019, 0x1bd800e8, 0x7dd9c005, 0x25dc0001,
-+	0xc42c004a, 0xcd80005e, 0xc420004d, 0xcec0005e, 0x11dc0010, 0x7e1e000a, 0xcd413249, 0xce01326f,
-+	0x28340001, 0x05980008, 0x7f598004, 0xcd800035, 0x1be800e8, 0xc42c004a, 0xce80005e, 0xd801327a,
-+	0xd800005f, 0xd8000075, 0xd800007f, 0xc424004c, 0xce41326e, 0xcec0005e, 0x28240100, 0x7e6a4004,
-+	0xce400079, 0xc435325d, 0x277401ef, 0x04240020, 0xce41325e, 0xd801325b, 0xd8013260, 0xcf41325d,
-+	0xda000068, 0xcf800008, 0x90000000, 0xc4113277, 0xc41c000b, 0xc420000c, 0x11dc0002, 0x7de1c001,
-+	0x11dc0008, 0x29dc0001, 0x25140001, 0x9540002d, 0xd8400013, 0xcdc1334a, 0xcfc00013, 0x042c3000,
-+	0xcec13267, 0xc42d3246, 0xc4313245, 0xc4353267, 0xd8400013, 0xc425334d, 0x26640001, 0x9640fffe,
-+	0xc419334e, 0xc41d334f, 0xc4213350, 0xc4253351, 0x52ec0020, 0x1b680057, 0x7ef2c01a, 0x1b700213,
-+	0x1b740199, 0x46ec01b0, 0x7f6b400a, 0x7f73400a, 0xcfc00013, 0xcf400024, 0xd2c00025, 0xcd800026,
-+	0xcdc00026, 0xce000026, 0xce400026, 0x042c2000, 0xd8400027, 0xcec13267, 0xc42d3267, 0x96c00001,
-+	0xc41c000b, 0xc420000c, 0x11dc0002, 0x7de1c001, 0x11dc0008, 0xd8400013, 0xcdc1334a, 0xcfc00013,
-+	0x90000000, 0xc430000b, 0x33300002, 0x04240000, 0x9b000010, 0x1be000e8, 0x042c0000, 0xc0360001,
-+	0x04280004, 0xd8400013, 0xcec1c200, 0xc63124dc, 0x0aa80001, 0x7ef6c001, 0x7e724001, 0x97000001,
-+	0x9a80fff9, 0xc02ee000, 0xd8400013, 0xcec1c200, 0x90000000, 0x90000000, 0xc4253260, 0x7fc14001,
-+	0xc40d3249, 0x18cc003e, 0x98c00005, 0x194c1c03, 0xccc0003b, 0xc40c002d, 0x80000697, 0xc420004a,
-+	0x194c00e8, 0xccc0005e, 0xc40c004c, 0xc431326d, 0x27301fff, 0xce00005e, 0x7cf0c00d, 0x98c00003,
-+	0x8c0007e0, 0x95c00008, 0xc430001e, 0x1b301ff8, 0x2b300400, 0x2330003f, 0xcd400013, 0xcf01325b,
-+	0x90000000, 0xcd400013, 0xd801325b, 0xc411325d, 0x251001ef, 0xcd01325d, 0x25100007, 0x31100005,
-+	0x9900008e, 0xc40c0007, 0xd9000010, 0x8000075e, 0x202c007d, 0xcec1325b, 0xc4293265, 0xc4353254,
-+	0x26a9feff, 0xc4380004, 0xd8400008, 0x1374000b, 0xc40c000d, 0xd8000009, 0x1774000d, 0xd8400013,
-+	0xc41d30b8, 0xcfc00013, 0x95c00008, 0xc411325d, 0xd801325b, 0xccc00009, 0xcf800008, 0x251001ef,
-+	0xcd01325d, 0x90000000, 0xce813265, 0xcf400100, 0xc00ac006, 0xc00e0000, 0x28880700, 0x28cc0014,
-+	0x8c0006de, 0x14cc0010, 0x30d4000f, 0x04cc0001, 0x10cc0010, 0x28cc0014, 0x99400009, 0xd8400013,
-+	0xc41530b8, 0xcfc00013, 0xc4193265, 0x19980028, 0x99400003, 0x99800002, 0x800006c8, 0xcfc00013,
-+	0xc411325d, 0xd801325b, 0xcf800008, 0x251001ef, 0xcd01325d, 0x90000000, 0x15600008, 0xce000009,
-+	0xc8380023, 0xc4180081, 0x11a00002, 0x7fa38011, 0xc4100026, 0x05980008, 0x7d1a0002, 0x282c2002,
-+	0x3e280008, 0xcec00013, 0xc4300027, 0x042c0008, 0xd3800025, 0xcf000024, 0x202400d0, 0x7ca48001,
-+	0xcc800026, 0xccc00026, 0x28240006, 0xcc000026, 0x0a640001, 0x9a40fffe, 0x9a800004, 0x32280000,
-+	0x9a800002, 0x9a000000, 0xd8400027, 0x24d8003f, 0xd840003c, 0xcec0003a, 0xd8800013, 0xcd81a2a4,
-+	0x90000000, 0xc41d325d, 0x25dc0007, 0xc40d3249, 0x18cc003e, 0x94c0000a, 0xc420004a, 0x194c00e8,
-+	0xccc0005e, 0xc40c004c, 0xc431326d, 0x27301fff, 0xce00005e, 0x7cf0c00d, 0x80000712, 0x194c1c03,
-+	0xccc0003b, 0xc40c002d, 0x05e80714, 0x86800000, 0x8000071c, 0x80000720, 0x80000747, 0x8000071d,
-+	0x800007c4, 0x80000732, 0x80000745, 0x80000744, 0x90000000, 0x98c00006, 0x8000072e, 0x90000000,
-+	0x98c00003, 0x8c0007e0, 0x95c0000c, 0xcd400013, 0xc4253265, 0x2a64008c, 0xce413265, 0xc430001e,
-+	0x1b301fe8, 0x2b300400, 0x2330003f, 0xd8013260, 0xcf01325b, 0x90000000, 0xc40c0007, 0xd9000010,
-+	0x04240000, 0x8000075e, 0x98c0fff1, 0x8c0007e0, 0x95c00002, 0x80000723, 0xcd400013, 0xc41f02f1,
-+	0x95c00004, 0xd8013247, 0xd801325d, 0x80000743, 0xd8813247, 0xd801325d, 0xc4100004, 0xd8400008,
-+	0xd8400013, 0xd88130b8, 0xcd000008, 0x90000000, 0x04100001, 0x98c0ffde, 0x8000072e, 0x98c00003,
-+	0x8c0007e0, 0x95c00012, 0xc4340004, 0xd8400008, 0x15600008, 0xc418000d, 0xce000009, 0xd8400013,
-+	0xd84131db, 0xcf400008, 0xcd800009, 0xc430001e, 0x1b301ff8, 0x2b300400, 0x2330003f, 0xcd400013,
-+	0xd8413260, 0xcf01325b, 0x90000000, 0xc40c0007, 0xd9000010, 0x04240000, 0xcd400013, 0x041c3000,
-+	0xcdc13267, 0xc41d3267, 0xc41d3265, 0x25dc8000, 0x95c00007, 0xc41c004a, 0x195800e8, 0xcd80005e,
-+	0xc418004c, 0xcd81326e, 0xcdc0005e, 0xc41d3265, 0x25dd7fff, 0xcdc13265, 0xc41d3246, 0xc4193245,
-+	0xc42d3267, 0x51e00020, 0x7e1a001a, 0x46200200, 0x04283247, 0x04300033, 0x1af80057, 0x1af40213,
-+	0x042c000c, 0x7f7b400a, 0x7f6f400a, 0xcf400024, 0xd2000025, 0xcd800026, 0xcdc00026, 0xc6990000,
-+	0x329c325d, 0x99c00008, 0x329c3269, 0x99c00006, 0x329c3267, 0x95c00005, 0xc01defff, 0x7d9d8009,
-+	0x8000078a, 0x25980000, 0x0b300001, 0x06a80001, 0xcd800026, 0x9b00fff2, 0xd8400027, 0xc43c0012,
-+	0x9bc0ffff, 0xcd400013, 0xd801325b, 0xc431325a, 0xc03e7ff0, 0x7f3f0009, 0xcf01325a, 0xc4313249,
-+	0x1f30001f, 0xcf013249, 0xc03e4000, 0xcfc13254, 0xcd400013, 0xd8013254, 0xc431325d, 0xd801324f,
-+	0xd8013255, 0xd8013247, 0xd801325d, 0x1b300028, 0x8c00120d, 0x8c001219, 0x8c001232, 0xc4380004,
-+	0xd8400008, 0xd8400013, 0x9900000d, 0xd88130b8, 0x9700000b, 0xc43d30b5, 0x1bf0003a, 0x9b000b80,
-+	0x203c003a, 0xc430000e, 0x27300700, 0x13300014, 0x2b300001, 0xcf0130b7, 0xcfc130b5, 0x46200008,
-+	0xcf400024, 0xd2000025, 0xd8000026, 0xd8400027, 0x043c2000, 0xcd400013, 0xcfc13267, 0xc43d3267,
-+	0x9bc00001, 0xccc00010, 0xcf800008, 0x90000000, 0xc4080007, 0xd9000010, 0xc4193260, 0x259c0003,
-+	0x31dc0003, 0x95c00014, 0x040c3000, 0xd8400008, 0xccc13267, 0xc40d3267, 0x18ec0057, 0x18e40213,
-+	0x18cc0199, 0x7cecc00a, 0x7ce4c00a, 0xc4193246, 0xc41d3245, 0x51980020, 0x7d9d801a, 0x8c000448,
-+	0xcd400013, 0x040c2000, 0xccc13267, 0xc40d3267, 0x94c00001, 0xcc800010, 0xd801325d, 0x90000000,
-+	0xc418000b, 0x31980002, 0x041c0000, 0x9980001c, 0x19580066, 0x15600008, 0x040c0000, 0xc0120001,
-+	0x11980003, 0x04240004, 0x7da18001, 0xc4200007, 0xc4340004, 0xd9000010, 0xd8400008, 0xd8400013,
-+	0xccc1c200, 0xc41d24db, 0x7cd0c001, 0x0a640001, 0x7dd9c005, 0x25dc0001, 0x99c00002, 0x9a40fff8,
-+	0xc418005e, 0x9580137b, 0xc00ee000, 0xd8400013, 0xccc1c200, 0xce000010, 0xcf400008, 0x90000000,
-+	0xd840004f, 0xc4113269, 0x19080070, 0x190c00e8, 0x2510003f, 0x2518000f, 0xcd813268, 0x05a80809,
-+	0x86800000, 0x8000080e, 0x8000080f, 0x80000898, 0x80000946, 0x800009e1, 0x80000a5a, 0x04a80811,
-+	0x86800000, 0x80000815, 0x80000834, 0x8000085e, 0x8000085e, 0x04341001, 0xcf400013, 0xc4380004,
-+	0xd8400008, 0xc42d3045, 0xcec1c091, 0x31300021, 0x9700000b, 0xd84002f1, 0xd8400013, 0xc43130b8,
-+	0x27300001, 0xc4293059, 0x56a8001f, 0x7f2b000a, 0xcf800008, 0x9b000241, 0x8000084a, 0xcf400013,
-+	0xd8400008, 0xc43130b6, 0x9b000003, 0xc02f0001, 0xcec130b6, 0xc4252087, 0x5668001a, 0x26a80005,
-+	0x9a80fffd, 0xcf400013, 0xd80130b6, 0x8000084a, 0xc4380004, 0xd8400008, 0x04341001, 0xcf400013,
-+	0xc431ecaa, 0x27300080, 0x9b000010, 0xc02e0001, 0xcec130b6, 0xcf400013, 0xd80130b6, 0x31300021,
-+	0x9700000a, 0xd84002f1, 0xd8400013, 0xc43130b8, 0x27300001, 0xc4293059, 0x56a8001f, 0x7f2b000a,
-+	0xcf800008, 0x9b00021d, 0xdd410000, 0x040c0005, 0xd84802e9, 0x8c001a41, 0xc43b02f1, 0x9b800006,
-+	0xc4380004, 0xd8400008, 0xd8400013, 0xd88130b8, 0xcf800008, 0xcec80278, 0x56f00020, 0xcf080280,
-+	0x8c001608, 0xdc140000, 0xcd400013, 0xd8813247, 0xd80802e9, 0x8000085e, 0xcd400013, 0x31100011,
-+	0x950001fa, 0xc02e0001, 0x2aec0008, 0xc01c0020, 0xc0180001, 0xc00c0007, 0x11a40006, 0x7de6000a,
-+	0x10e40008, 0x7e26000a, 0x7e2e000a, 0xce000013, 0xc4113254, 0x1d10ffdf, 0x2110003e, 0xcd013254,
-+	0xd801324f, 0xd8013255, 0x1d10ff9e, 0xcd013254, 0xd8013247, 0xd801325d, 0xd801325e, 0xc0245301,
-+	0xce413249, 0xd801325f, 0xc425326c, 0xc0121fff, 0x29108eff, 0x7e524009, 0xce41326c, 0xc425325a,
-+	0xc0127ff0, 0x7e524009, 0xce41325a, 0xc425325b, 0xc0131fff, 0x7e524009, 0xce41325b, 0xd801326d,
-+	0xd801326e, 0xd8013279, 0x94c00003, 0x08cc0001, 0x80000866, 0xc00c0007, 0x95800003, 0x09980001,
-+	0x80000866, 0xc0100010, 0x7dd2400c, 0x9a400004, 0xc0180003, 0x7dd1c002, 0x80000866, 0x80000a5a,
-+	0x04a8089a, 0x86800000, 0x8000089e, 0x800008fa, 0x80000945, 0x80000945, 0x31300022, 0x97000007,
-+	0xc4380004, 0xd8400008, 0xd8400013, 0xc43130b8, 0x27300001, 0xcf800008, 0xcd400013, 0x04183000,
-+	0xcd813267, 0xc4113246, 0xc4193245, 0x51100020, 0x7d91801a, 0x459801e0, 0xc4313267, 0x2738000f,
-+	0x1b342010, 0x172c000c, 0x26ec0800, 0x1b30c012, 0x7ef7400a, 0x7f37000a, 0x2b300000, 0xcf00001c,
-+	0xd180001e, 0xd8400021, 0xc42c000f, 0x9ac0ffff, 0xc8300011, 0x97000036, 0x45980008, 0xd180001e,
-+	0xd8400021, 0xc42c000f, 0x9ac0ffff, 0xc8340011, 0x9740002f, 0xc43c0004, 0xd8400008, 0xd8400013,
-+	0x13b80001, 0xc79d3300, 0xc7a13301, 0x96000001, 0xd8393300, 0xc0260001, 0xce793301, 0xc424005e,
-+	0x964012a4, 0x7c028009, 0x9740001c, 0x27580001, 0x99800004, 0x57740001, 0x06a80400, 0x800008d2,
-+	0xc4180006, 0x9980ffff, 0x29640001, 0xce40001a, 0x242c0000, 0x06ec0400, 0x57740001, 0x27580001,
-+	0x9980fffd, 0xc02620c0, 0xce41c078, 0xce81c080, 0xcc01c081, 0xcf01c082, 0x57240020, 0xce41c083,
-+	0xc0260400, 0x7e6e400a, 0xce41c084, 0x7eae8001, 0x7f2f0011, 0x800008d2, 0xc4180006, 0x9980ffff,
-+	0xcdf93300, 0xce393301, 0xcfc00008, 0xcd400013, 0xc43c0004, 0xd8400008, 0x04182000, 0xcd813267,
-+	0xcfc00008, 0x80000903, 0x31240022, 0x96400008, 0x04100001, 0xc4380004, 0xd8400008, 0xd8400013,
-+	0xc43130b8, 0x27300001, 0xcf800008, 0xc4af0280, 0xc4b30278, 0x52ec0020, 0x7ef2c01a, 0x7ec30011,
-+	0x32f80000, 0x9b800011, 0x043c0020, 0x04280000, 0x67180001, 0x0bfc0001, 0x57300001, 0x95800006,
-+	0x8c001628, 0x9a400003, 0xd981325d, 0x80000915, 0xd9c1325d, 0x06a80001, 0x9bc0fff6, 0x7f818001,
-+	0x8c001606, 0x7d838001, 0x94800010, 0xcd400013, 0xc41d3259, 0xc421325a, 0x16240014, 0x12640014,
-+	0x1a2801f0, 0x12a80010, 0x2620ffff, 0x7e2a000a, 0x7de1c001, 0x7e5e400a, 0x9b800002, 0x2264003f,
-+	0xce41325a, 0xd8013259, 0xc40c0007, 0xd9000010, 0x8c00075e, 0xc4af0228, 0x043c0000, 0x66d80001,
-+	0x95800010, 0x04300002, 0x1330000d, 0x13f40014, 0x7f73400a, 0xcf400013, 0x04380040, 0xcf80001b,
-+	0xd8400021, 0xc438000f, 0x9b80ffff, 0x04380060, 0xcf80001b, 0xd8400021, 0xc438000f, 0x9b80ffff,
-+	0x07fc0001, 0x56ec0001, 0x33e80010, 0x9680ffec, 0x80000a5a, 0x80000a5a, 0x04a80948, 0x86800000,
-+	0x8000094c, 0x8000099b, 0x800009e0, 0x800009e0, 0xc43c0004, 0xd8400008, 0xcd400013, 0x04183000,
-+	0xcd813267, 0xc4113246, 0xc4193245, 0x51100020, 0x7d91801a, 0x459801e0, 0xc4313267, 0x2738000f,
-+	0x1b342010, 0x172c000c, 0x26ec0800, 0x1b30c012, 0x7ef7400a, 0x7f37000a, 0x2b300000, 0xcf00001c,
-+	0xd180001e, 0xd8400021, 0xc42c000f, 0x9ac0ffff, 0xc8300011, 0x97000033, 0x45980008, 0xd180001e,
-+	0xd8400021, 0xc42c000f, 0x9ac0ffff, 0xc8340011, 0x9740002c, 0xd8400013, 0x13b80001, 0xc79d3300,
-+	0xc7a13301, 0x96000001, 0xd8393300, 0xc0260001, 0xce793301, 0xc424005e, 0x964011fe, 0x7c028009,
-+	0x9740001c, 0x27580001, 0x99800004, 0x57740001, 0x06a80400, 0x80000978, 0xc4180006, 0x9980ffff,
-+	0x29640001, 0xce40001a, 0x242c0000, 0x06ec0400, 0x57740001, 0x27580001, 0x9980fffd, 0xc0260010,
-+	0xce41c078, 0xcf01c080, 0x57240020, 0xce41c081, 0xce81c082, 0xcc01c083, 0xc0260800, 0x7e6e400a,
-+	0xce41c084, 0x7eae8001, 0x7f2f0011, 0x80000978, 0xc4180006, 0x9980ffff, 0xcdf93300, 0xce393301,
-+	0x04182000, 0xcd813267, 0xcfc00008, 0xcd400013, 0xc4193246, 0xc41d3245, 0x51980020, 0x7dda801a,
-+	0x7d41c001, 0x7e838011, 0xd84802e9, 0x8c001802, 0x469c0390, 0xc4313267, 0x04183000, 0xcd813267,
-+	0x1b342010, 0x172c000c, 0x26ec0800, 0x1b30c012, 0x7ef7400a, 0x7f37000a, 0x2b300000, 0xcf00001c,
-+	0x45dc0004, 0xd1c0001e, 0xd8400021, 0xc418000f, 0x9980ffff, 0xc4200011, 0x45dc0004, 0xd1c0001e,
-+	0xd8400021, 0xc418000f, 0x9980ffff, 0xc4240011, 0x45dc0004, 0xd1c0001e, 0xd8400021, 0xc418000f,
-+	0x9980ffff, 0xc4280011, 0x45dc0004, 0xd1c0001e, 0xd8400021, 0xc418000f, 0x9980ffff, 0xc42c0011,
-+	0x45dc0004, 0xd1c0001e, 0xd8400021, 0xc418000f, 0x9980ffff, 0xc4300011, 0x45dc0004, 0xd1c0001e,
-+	0xd8400021, 0xc418000f, 0x9980ffff, 0xc4340011, 0x45dc0004, 0xd1c0001e, 0xd8400021, 0xc418000f,
-+	0x9980ffff, 0xc4380011, 0xcd400013, 0x04182000, 0xcd813267, 0x043c0001, 0x8c0014df, 0x80000a5a,
-+	0x80000a5a, 0x31280014, 0xce8802ef, 0x9a800062, 0x31280034, 0x9a800060, 0x04a809e8, 0x86800000,
-+	0x800009ec, 0x80000a45, 0x80000a59, 0x80000a59, 0xcd400013, 0xc4113246, 0xc4193245, 0x51100020,
-+	0x7d91801a, 0x45980400, 0xc4b30258, 0xc4a70250, 0x53300020, 0x7e72401a, 0xc4313267, 0x1b342010,
-+	0x172c000c, 0x26ec0800, 0x1b30c012, 0x7ef7400a, 0x7f37000a, 0x2b300000, 0xcf00001c, 0x042c0020,
-+	0x66740001, 0x97400041, 0xcd400013, 0x04383000, 0xcf813267, 0xc4393267, 0x9b800001, 0xd180001e,
-+	0xd8400021, 0xc438000f, 0x9b80ffff, 0xc4300011, 0x1b38007e, 0x33b40003, 0x9b400003, 0x4598001c,
-+	0x9740002f, 0x45980004, 0xd180001e, 0xd8400021, 0xc438000f, 0x9b80ffff, 0xc40c0011, 0x45980004,
-+	0xd180001e, 0xd8400021, 0xc438000f, 0x9b80ffff, 0xc4100011, 0x45980004, 0xd180001e, 0xd8400021,
-+	0xc438000f, 0x9b80ffff, 0xc4340011, 0xcf4002eb, 0x45980004, 0xd180001e, 0xd8400021, 0xc438000f,
-+	0x9b80ffff, 0xc4340011, 0xcf4002ec, 0x45980004, 0xd180001e, 0xd8400021, 0xc438000f, 0x9b80ffff,
-+	0xc4340011, 0xcf4002ed, 0x45980004, 0xd180001e, 0xd8400021, 0xc438000f, 0x9b80ffff, 0xc4340011,
-+	0xcf4002ee, 0x45980004, 0xcd400013, 0x04382000, 0xcf813267, 0xd84802e9, 0x8c001715, 0xcd400013,
-+	0x04382000, 0xcf813267, 0x56640001, 0x0aec0001, 0x9ac0ffbc, 0xc4380004, 0xd8400008, 0x04341001,
-+	0xcf400013, 0x94800005, 0xc431ecaa, 0x27300080, 0x97000002, 0x80000a55, 0xc43130b6, 0x233c0032,
-+	0xcfc130b6, 0xcf400013, 0xcf0130b6, 0xc49302ef, 0x99000003, 0xcd400013, 0xd8413247, 0xcf800008,
-+	0x80000a5a, 0x80000a5a, 0xcd400013, 0x04180001, 0x5198001f, 0xcd813268, 0xc4193269, 0x2598000f,
-+	0x9980fffe, 0xd80002f1, 0xcd400013, 0xd8013268, 0xd800004f, 0x90000000, 0xcd400013, 0x04380001,
-+	0x53b8001f, 0x7db9801a, 0xcd813268, 0x80000a5e, 0xd8400029, 0xc40c005e, 0x94c01106, 0xd8800013,
-+	0xcc412e01, 0xcc412e02, 0xcc412e03, 0xcc412e00, 0x80000aa7, 0xd8400029, 0xc40c005e, 0x94c010fd,
-+	0x7c40c001, 0x50640020, 0x7ce4c01a, 0xd0c00072, 0xc80c0072, 0x58e801fc, 0x12a80009, 0x2aa80000,
-+	0xd0c0001e, 0xce80001c, 0xd8400021, 0xc424000f, 0x9a40ffff, 0x04240010, 0x18dc01e2, 0x7e5e4002,
-+	0x3e5c0003, 0x3e540002, 0x95c00006, 0xc8180011, 0xc8100011, 0xc8100011, 0x55140020, 0x80000aa2,
-+	0x9540000a, 0xc8180011, 0x44cc0008, 0x55900020, 0xd0c0001e, 0xd8400021, 0xc424000f, 0x9a40ffff,
-+	0xc4140011, 0x80000aa2, 0x44cc0004, 0xc4180011, 0xd0c0001e, 0xd8400021, 0xc424000f, 0x9a40ffff,
-+	0xc8100011, 0x55140020, 0xd8800013, 0xcd812e01, 0xcd012e02, 0xcd412e03, 0xcc412e00, 0xc428000e,
-+	0x2aa80008, 0xce800013, 0xc4253249, 0x2264003f, 0xce413249, 0xce800013, 0xc4253249, 0x96400001,
-+	0xd800002a, 0xc410001a, 0xc40c0021, 0xc4140028, 0x95000005, 0x1e64001f, 0xce800013, 0xce413249,
-+	0x80001b70, 0x14d00010, 0xc4180030, 0xc41c0007, 0x99000004, 0x99400009, 0x9980000c, 0x80000ab1,
-+	0xccc00037, 0x8c000190, 0xc420001c, 0xd8000032, 0x9a0010ac, 0x80000aa7, 0xd880003f, 0x95c00002,
-+	0xd8c0003f, 0x80001082, 0xd8800040, 0x95c00002, 0xd8c00040, 0x800010de, 0xc010ffff, 0x18d403f7,
-+	0x7d0cc009, 0xc41b0367, 0x7d958004, 0x7d85800a, 0xdc1e0000, 0x90000000, 0xc424000b, 0x32640002,
-+	0x7c40c001, 0x18d001fc, 0x05280adc, 0x86800000, 0x80000af1, 0x80000adf, 0x80000ae7, 0x8c000ace,
-+	0xd8c00013, 0x96400002, 0xd8400013, 0xcd8d2000, 0x99c00010, 0x7c408001, 0x88000000, 0x18d803f7,
-+	0xc010ffff, 0x7d0cc009, 0x04140000, 0x11940014, 0x29544001, 0x9a400002, 0x29544003, 0xcd400013,
-+	0x80000af4, 0xd8c00013, 0x96400002, 0xd8400013, 0xd44d2000, 0x7c408001, 0x88000000, 0xc424000b,
-+	0x32640002, 0x7c40c001, 0xd8c00013, 0x96400002, 0xd8400013, 0xd44dc000, 0x7c408001, 0x88000000,
-+	0x7c40c001, 0x18d0003c, 0x95000006, 0x8c000ace, 0xd8800013, 0xcd8d2c00, 0x99c00003, 0x80000b0a,
-+	0xd8800013, 0xd44d2c00, 0x7c408001, 0x88000000, 0x7c40c001, 0x28148004, 0x24d800ff, 0xccc00019,
-+	0xcd400013, 0xd4593240, 0x7c408001, 0x88000000, 0xd8400029, 0xc40c005e, 0x94c0105e, 0x7c410001,
-+	0x50540020, 0x7c418001, 0x2198003f, 0x199c0034, 0xc40c0007, 0x95c00028, 0xc428000e, 0x2aa80008,
-+	0xce800013, 0xc42d324f, 0xc4313255, 0x7ef3400c, 0x9b400021, 0xd800002a, 0x80001b70, 0xc40c0007,
-+	0x14e80001, 0x9a8000af, 0xd9000010, 0x041c0002, 0x042c01c8, 0x8c000d61, 0xccc00010, 0xd8400029,
-+	0xc40c005e, 0x94c01043, 0x7c410001, 0x50540020, 0x7c418001, 0x18a01fe8, 0x3620005c, 0x9a00000e,
-+	0x2464003f, 0xd8400013, 0xc6290ce7, 0x16ac001f, 0x96c00004, 0x26ac003f, 0x7ee6c00d, 0x96c00005,
-+	0x06200001, 0x2620000f, 0x9a00fff8, 0x8000016a, 0xce000367, 0xc424005e, 0x9640102e, 0xc428000e,
-+	0x199c0037, 0x19a00035, 0x2aa80008, 0xce800013, 0x95c0005d, 0xd800002a, 0xc42d3256, 0xc431325a,
-+	0x2330003f, 0x16f8001f, 0x9780000d, 0xc4253248, 0xc035f0ff, 0x7e764009, 0x19b401f8, 0x13740008,
-+	0x7e76400a, 0xce800013, 0xce413248, 0xcf01325a, 0xce800013, 0xc431325a, 0x97000001, 0x7d15001a,
-+	0xd1000072, 0xc8100072, 0x55140020, 0x199c0034, 0xd8400010, 0xd8400029, 0x9b800004, 0x1ae4003e,
-+	0xce400008, 0x80000b7c, 0xc4353254, 0x16a80008, 0x1aec003c, 0x19a4003f, 0x12a80015, 0x12ec001f,
-+	0x1374000b, 0x7eae800a, 0xc02e4000, 0x1774000d, 0x7eae800a, 0xce400008, 0x7f6b400a, 0x95c00005,
-+	0xc43d3248, 0x1bfc01e8, 0x13fc0018, 0x7dbd800a, 0x1d98ff15, 0x592c00fc, 0xcd80000a, 0x12e00016,
-+	0x7da1800a, 0x592c007e, 0x12e00015, 0x7da1800a, 0xd1000001, 0xcd800001, 0x11a0000c, 0x1264001e,
-+	0x1620000c, 0x7e26000a, 0x7e32000a, 0x12e4001b, 0x7e26000a, 0x5924007e, 0x12640017, 0x7e26000a,
-+	0x19a4003c, 0x12640018, 0x7e26000a, 0xd800002a, 0xce01325a, 0xcd013257, 0xcd413258, 0xc429325a,
-+	0xc40c005e, 0x94c00fdb, 0x96800001, 0x95c00003, 0x7c40c001, 0x7c410001, 0x9780f5ca, 0xcf400100,
-+	0xc40c0007, 0xd9000010, 0x8c00120d, 0x8c001219, 0x8c001232, 0xccc00010, 0x8c001b6d, 0x7c408001,
-+	0x88000000, 0xc42d324e, 0xc431324d, 0x52ec0020, 0x7ef2c01a, 0xc435324f, 0xc4293256, 0x52ec0008,
-+	0x07740003, 0x04240002, 0x269c003f, 0x7e5e4004, 0x7f67000f, 0x97000003, 0x7f674002, 0x0b740001,
-+	0x53740002, 0x7ef6c011, 0x1ab42010, 0x1ab8c006, 0x16a8000c, 0x26a80800, 0x2b740000, 0x7f7b400a,
-+	0x7f6b400a, 0xcf40001c, 0xd2c0001e, 0xd8400021, 0xc438000f, 0x9b80ffff, 0xc4180011, 0x9a000003,
-+	0x8c000bec, 0x80000b47, 0xc42c001d, 0xc4313256, 0x1b34060b, 0x1b300077, 0x7f370009, 0x13300017,
-+	0x04340100, 0x26ec00ff, 0xc03a8004, 0x7ef6c00a, 0x7f3b000a, 0x7ef2c00a, 0xcec1325b, 0x80000c16,
-+	0xc40c0032, 0xc410001d, 0x28cc0008, 0xccc00013, 0xc415325b, 0x7c418001, 0x7c418001, 0x18580037,
-+	0x251000ff, 0xc421325d, 0x262001ef, 0xce01325d, 0x99800004, 0x7d15400a, 0xcd41325b, 0x80000168,
-+	0x1d54001f, 0xcd41325b, 0x7c408001, 0x88000000, 0xc428000b, 0xc42c000c, 0x12a80001, 0x26a80004,
-+	0x7eae800a, 0xc40c0021, 0xc4340028, 0x14f00010, 0xc4380030, 0xc43c0007, 0xcd280200, 0xcd680208,
-+	0xcda80210, 0x9b00000c, 0x9b400014, 0x9b800017, 0xc428000b, 0xc42c000c, 0x12a80001, 0x26a80004,
-+	0x7eae800a, 0xc6930200, 0xc6970208, 0xc69b0210, 0x90000000, 0x17300001, 0x9b000005, 0xccc00037,
-+	0x8c000190, 0xd8000032, 0x90000000, 0xd8000028, 0xd800002b, 0x80000168, 0xd900003f, 0x97c00002,
-+	0xd940003f, 0x80001082, 0xd9000040, 0x97c00002, 0xd9400040, 0x800010de, 0xc40c0021, 0x14fc0011,
-+	0x24f800ff, 0x33b80001, 0x97c0fffc, 0x9b800007, 0xccc00037, 0x8c000190, 0xd8000032, 0xd8000028,
-+	0xd800002b, 0x80001b70, 0xc4380004, 0xd8400008, 0xd8400013, 0xd88130b8, 0x04100000, 0x04140000,
-+	0xc418000e, 0x29980008, 0x7d83c001, 0xcd800013, 0xc4093249, 0x1888003e, 0x94800020, 0xd8400074,
-+	0x8c000671, 0x9a400009, 0xc418000e, 0x29980008, 0xcd800013, 0xc419324c, 0x259c0001, 0x1598001f,
-+	0x95c00016, 0x95800015, 0x99000003, 0xd8400036, 0x04100001, 0xc40c0021, 0x14d80011, 0x24e000ff,
-+	0x321c0002, 0x32200001, 0x9580ffee, 0x99c00014, 0x96000004, 0xccc00037, 0x04140001, 0x80000c30,
-+	0x9480000a, 0xd8000074, 0xc418005e, 0x95800f29, 0xcf800008, 0x80000c16, 0x94800004, 0xd8000074,
-+	0xc418005e, 0x95800f23, 0xd9c00036, 0x99400002, 0xccc00037, 0xcf800008, 0x80000c16, 0x94800004,
-+	0xd8000074, 0xc418005e, 0x95800f1a, 0xccc00037, 0xd8800036, 0x80001b70, 0x041c0003, 0x042c01c8,
-+	0x8c000d61, 0xc4200007, 0xc40c0077, 0x94c00001, 0x7c418001, 0xc428000e, 0x9600f502, 0x0a200001,
-+	0x98c0f500, 0x2aa80008, 0xce000010, 0x9a000f05, 0xce800013, 0xc431325a, 0xc42d3256, 0x1f30001f,
-+	0x16e4001f, 0xcf01325a, 0xc431325a, 0x97000001, 0x9640f4f4, 0xc434000b, 0x33740002, 0x9b40f4f1,
-+	0xc4353254, 0x16a80008, 0x1aec003c, 0x12a80015, 0x12ec001f, 0x1374000b, 0x7eae800a, 0xc02e4000,
-+	0x1774000d, 0x7eae800a, 0x7f6b400a, 0xcf400100, 0x12780001, 0x2bb80001, 0xc00ac005, 0xc00e0002,
-+	0x28cc8000, 0x28884900, 0x28cc0014, 0x80000ff3, 0xc43c0007, 0x7c40c001, 0x17fc0001, 0xd8400013,
-+	0x9bc00004, 0xd8400029, 0xc424005e, 0x96400ee1, 0xcc41c40a, 0xcc41c40c, 0xcc41c40d, 0x7c414001,
-+	0x24d0007f, 0x15580010, 0x255400ff, 0xcd01c411, 0xcd81c40f, 0xcd41c40e, 0xcc41c410, 0x7c414001,
-+	0x7c418001, 0x04200000, 0x18e80033, 0x18ec0034, 0xcc41c414, 0xcc41c415, 0xcd81c413, 0xcd41c412,
-+	0x18dc0032, 0x7c030011, 0x7c038011, 0x95c00027, 0x96c00002, 0xc431c417, 0xc435c416, 0x96800004,
-+	0x96c00002, 0xc439c419, 0xc43dc418, 0xc41c000e, 0x29dc0008, 0xcdc00013, 0xcf413261, 0x96c00002,
-+	0xcf013262, 0x96800004, 0xcfc13263, 0x96c00002, 0xcf813264, 0x18dc0030, 0xc43c0007, 0x95c00017,
-+	0x17fc0001, 0x9ac00005, 0x7d77000c, 0x9bc00015, 0x9700000a, 0x80000cd6, 0x51b80020, 0x53300020,
-+	0x7f97801a, 0x7f37001a, 0x7f3b000c, 0x9bc0000d, 0x97800002, 0x80000cd6, 0x9a000018, 0xd8400013,
-+	0x28200001, 0x80000ca7, 0x18dc0031, 0x95c00003, 0xc435c40b, 0x9740fffd, 0xd800002a, 0x80001b70,
-+	0xc4280032, 0x2aa80008, 0xce800013, 0xc40d325b, 0x97000002, 0x800012c2, 0xc438001d, 0x1bb81ff0,
-+	0x7f8cc00a, 0xccc1325b, 0xc411325d, 0x251001ef, 0xcd01325d, 0x80001b70, 0xc428000e, 0xc43c0007,
-+	0x2aa80008, 0xc438001d, 0xce800013, 0x13f4000c, 0x9bc00006, 0xc43d3256, 0x1bf0060b, 0x1bfc0077,
-+	0x7ff3c00a, 0x80000cf4, 0xc43d325a, 0x1bfc0677, 0x13fc0017, 0x04300100, 0x1bb81fe8, 0x7f73400a,
-+	0xc032800b, 0x7fb7800a, 0x7ff3c00a, 0x7ffbc00a, 0xcfc1325b, 0x80000c16, 0xc43c0007, 0x7c40c001,
-+	0x18d42011, 0x17fc0001, 0x18d001e8, 0x24cc007f, 0x7cd4c00a, 0x9bc00004, 0xd8400029, 0xc428005e,
-+	0x96800e6c, 0x7c414001, 0x50580020, 0x7d59401a, 0xd1400072, 0xc8140072, 0x596001fc, 0x12200009,
-+	0x7ce0c00a, 0x7c418001, 0x505c0020, 0x7d9d801a, 0x7c41c001, 0x50600020, 0x7de1c01a, 0x7c420001,
-+	0xccc0001b, 0xd140001d, 0xd180001f, 0xd1c00020, 0xd8400021, 0x95000010, 0x04300000, 0xc428000f,
-+	0x9a80ffff, 0xc8240010, 0x7e5e800c, 0x9bc00015, 0x9a80000c, 0x9b000024, 0x28300001, 0x122c0004,
-+	0x06ec0001, 0x0aec0001, 0x9ac0ffff, 0xd8400021, 0x80000d1f, 0xc428000f, 0x9a80ffff, 0xc8240010,
-+	0x566c0020, 0xc428000e, 0x2aa80008, 0xce800013, 0xce413261, 0xcec13262, 0xd800002a, 0x80001b70,
-+	0xc4340032, 0x2b740008, 0xcf400013, 0xc40d325b, 0x96800005, 0x566c0020, 0xce413261, 0xcec13262,
-+	0x800012c2, 0xc438001d, 0x1bb81fe8, 0x7f8cc00a, 0xccc1325b, 0xc411325d, 0x251001ef, 0xcd01325d,
-+	0x80001b70, 0xc43c0007, 0xc438001d, 0xc428000e, 0x2aa80008, 0xce800013, 0x13f4000c, 0x9bc00006,
-+	0xc43d3256, 0x1bf0060b, 0x1bfc0077, 0x7ff3c00a, 0x80000d57, 0xc43d325a, 0x1bfc0677, 0x13fc0017,
-+	0x04300100, 0x1bb81fe8, 0x7f73400a, 0xc0328009, 0x7fb7800a, 0x7ff3c00a, 0x7ffbc00a, 0xcfc1325b,
-+	0x80000c16, 0xc43c000e, 0x2bfc0008, 0xcfc00013, 0xc4253246, 0xc4113245, 0x04143000, 0xcd413267,
-+	0x52640020, 0x7e51001a, 0xc4153267, 0x7d2d0011, 0x19640057, 0x19580213, 0x19600199, 0x7da6400a,
-+	0x7e26400a, 0xd1000025, 0xce400024, 0xcdc00026, 0xd8400027, 0x04142000, 0xcfc00013, 0xcd413267,
-+	0xc4153267, 0x99400001, 0x90000000, 0x7c40c001, 0x18d001e8, 0x18d40030, 0x18d80034, 0x05280d83,
-+	0x7c420001, 0x7c424001, 0x86800000, 0x80000d8a, 0x8000016a, 0x80000d95, 0x80000db1, 0x8000016a,
-+	0x80000d95, 0x80000dbc, 0x11540010, 0x7e010001, 0x8c00187c, 0x7d75400a, 0xcd400013, 0xd4610000,
-+	0x9580f3d8, 0xc439c040, 0x97800001, 0x7c408001, 0x88000000, 0xd8000016, 0x526c0020, 0x18e80058,
-+	0x7e2ec01a, 0xd2c00072, 0xc82c0072, 0x5ae0073a, 0x7ea2800a, 0x9940000a, 0xce800024, 0xd2c00025,
-+	0xd4400026, 0xd8400027, 0x9580f3c6, 0xc4380012, 0x9b80ffff, 0x7c408001, 0x88000000, 0xdc3a0000,
-+	0x0bb80001, 0xce800024, 0xd2c00025, 0xcc400026, 0xd8400027, 0x9b80fffb, 0x9980fff5, 0x7c408001,
-+	0x88000000, 0xc02a0001, 0x2aa80001, 0x16200002, 0xce800013, 0xce01c405, 0xd441c406, 0x9580f3b1,
-+	0xc439c409, 0x97800001, 0x7c408001, 0x88000000, 0xc424000b, 0x32640002, 0x9a40000b, 0x11540010,
-+	0x29540002, 0xcd400013, 0xd4610000, 0x9580f3a5, 0xd8400013, 0xc439c040, 0x97800001, 0x7c408001,
-+	0x88000000, 0xd4400078, 0x80000168, 0xd8400029, 0xc40c005e, 0x94c00da7, 0x7c40c001, 0x50500020,
-+	0x7cd0c01a, 0xd0c00072, 0xc8280072, 0x5aac007e, 0x12d80017, 0x7c41c001, 0x7d9d800a, 0x56a00020,
-+	0x2620ffff, 0x7da1800a, 0x51980020, 0x7e82400a, 0x7e58c01a, 0x19d4003d, 0x28182002, 0x99400030,
-+	0x8c00104f, 0xc430000d, 0xc4340035, 0xd800002a, 0xcd800013, 0xc8140023, 0xc4180081, 0x13300005,
-+	0xc011000f, 0xc4240004, 0x11a00002, 0x7c908009, 0x12640004, 0x7d614011, 0xc4100026, 0x05980008,
-+	0x7ca4800a, 0x7d1a0002, 0x7cb0800a, 0x3e280008, 0x20880188, 0x54ec0020, 0x7cb4800a, 0xc4300027,
-+	0x04380008, 0xd1400025, 0xcf000024, 0x20240090, 0x7ca48001, 0xcc800026, 0xccc00026, 0xcec00026,
-+	0xcec00026, 0x28240004, 0xcc000026, 0x0a640001, 0x9a40fffe, 0x9a800005, 0x32280000, 0x9a800002,
-+	0x9a000000, 0x7c018001, 0xd8400027, 0xd8000016, 0xcf80003a, 0xd901a2a4, 0x80001037, 0xc418000e,
-+	0x29980008, 0xcd800013, 0xc421326c, 0x1624001f, 0x9a40fffe, 0xd841325f, 0xd8800033, 0xc43c0009,
-+	0x27fc0004, 0x97c0fffe, 0xd8000039, 0xd0c00038, 0xc43c0022, 0x9bc0ffff, 0xd8800034, 0xc429325f,
-+	0x26ac0001, 0x9ac0fffe, 0x26ac0002, 0x96c00003, 0xd800002a, 0x80001b70, 0xc43c0007, 0xc430001e,
-+	0xd8800033, 0x13f4000c, 0x1b301ff0, 0x2b300300, 0x2330003f, 0x7f37000a, 0x9680000b, 0xc43c0009,
-+	0x27fc0004, 0x97c0fffe, 0xd8400039, 0xd0c00038, 0xc43c0022, 0x9bc0ffff, 0xcf01325b, 0xd8800034,
-+	0x80000c16, 0xd8800034, 0x8c0001a2, 0x80001b70, 0xcc80003b, 0x24b00008, 0xc418000e, 0x1330000a,
-+	0x18ac0024, 0x2b304000, 0x7c40c001, 0xcec00008, 0x18a800e5, 0x1d980008, 0x12a80008, 0x7da9800a,
-+	0x29980008, 0xcd800013, 0xc4113249, 0x1910003e, 0x99000002, 0xd840003d, 0x7c410001, 0xd4400078,
-+	0x51100020, 0xcf01326c, 0x7cd0c01a, 0xc421326c, 0x12a80014, 0x2220003f, 0x7e2a000a, 0xcd800013,
-+	0xce01326c, 0xd8800033, 0xc43c0009, 0x27fc0004, 0x97c0fffe, 0xd8000039, 0xd0c00038, 0xc43c0022,
-+	0x9bc0ffff, 0xd8800034, 0x80001190, 0x7c40c001, 0x18dc003d, 0x95c00004, 0x041c0001, 0x042c01c8,
-+	0x8c000d61, 0x18d40030, 0x18d001e8, 0x18fc0034, 0x24e8000f, 0x06a80e71, 0x7c418001, 0x7c41c001,
-+	0x86800000, 0x80000edd, 0x80000e91, 0x80000e91, 0x80000ea1, 0x80000eaa, 0x80000e7c, 0x80000e7f,
-+	0x80000e7f, 0x80000e87, 0x80000e8f, 0x8000016a, 0x51dc0020, 0x7d9e001a, 0x80000ee6, 0xc420000e,
-+	0x2a200008, 0xce000013, 0xc4213262, 0xc4253261, 0x52200020, 0x7e26001a, 0x80000ee6, 0xc420000e,
-+	0x2a200008, 0xce000013, 0xc4213264, 0xc4253263, 0x52200020, 0x7e26001a, 0x80000ee6, 0xc820001f,
-+	0x80000ee6, 0x18e82005, 0x51e00020, 0x2aa80000, 0x7da1801a, 0xd1800072, 0xc8180072, 0x59a001fc,
-+	0x12200009, 0x7ea2800a, 0xce80001c, 0xd180001e, 0xd8400021, 0xc428000f, 0x9a80ffff, 0xc8200011,
-+	0x80000ee6, 0x15980002, 0xd8400013, 0xcd81c400, 0xc421c401, 0x95400041, 0xc425c401, 0x52640020,
-+	0x7e26001a, 0x80000ee6, 0x31ac2580, 0x9ac00011, 0x31ac260c, 0x9ac0000f, 0x31ac0800, 0x9ac0000d,
-+	0x31ac0828, 0x9ac0000b, 0x31ac2440, 0x9ac00009, 0x31ac2390, 0x9ac00007, 0x31ac0093, 0x9ac00005,
-+	0x31ac31dc, 0x9ac00003, 0x31ac31e6, 0x96c00004, 0xc4340004, 0xd8400008, 0x80000ede, 0x39ac7c06,
-+	0x3db07c00, 0x9ac00003, 0x97000002, 0x80000ebc, 0x39acc337, 0x3db0c330, 0x9ac00003, 0x97000002,
-+	0x80000ebc, 0x39acc335, 0x3db0c336, 0x9ac00003, 0x97000002, 0x80000ebc, 0x39ac9002, 0x3db09001,
-+	0x9ac00003, 0x97000002, 0x80000ebc, 0x39ac9012, 0x3db09011, 0x9ac00003, 0x97000002, 0x80000ebc,
-+	0x39acec70, 0x3db0ec6f, 0x9ac00003, 0x97000002, 0x80000ebc, 0xc4340004, 0xd8400013, 0xc5a10000,
-+	0x95400005, 0x05980001, 0xc5a50000, 0x52640020, 0x7e26001a, 0xcf400008, 0x05280eea, 0x7c418001,
-+	0x7c41c001, 0x86800000, 0x80000ef1, 0x8000016a, 0x80000efe, 0x80000f11, 0x80000f2e, 0x80000efe,
-+	0x80000f1f, 0xc4340004, 0xd8400013, 0xce190000, 0x95400005, 0x05980001, 0x56200020, 0xce190000,
-+	0xcf400008, 0x97c0f26f, 0xc439c040, 0x97800001, 0x7c408001, 0x88000000, 0x51ec0020, 0x18e80058,
-+	0x7daec01a, 0xd2c00072, 0xc82c0072, 0x5af8073a, 0x7eba800a, 0xd2c00025, 0xce800024, 0xce000026,
-+	0x95400003, 0x56240020, 0xce400026, 0xd8400027, 0x97c0f25c, 0xc4380012, 0x9b80ffff, 0x7c408001,
-+	0x88000000, 0xc02a0001, 0x2aa80001, 0x15980002, 0xce800013, 0xcd81c405, 0xce01c406, 0x95400003,
-+	0x56240020, 0xce41c406, 0x97c0f24e, 0xc439c409, 0x97800001, 0x7c408001, 0x88000000, 0xc424000b,
-+	0x32640002, 0x9a40f247, 0xd8800013, 0xce190000, 0x95400004, 0x05980001, 0x56200020, 0xce190000,
-+	0x97c0f240, 0xd8400013, 0xc439c040, 0x97800001, 0x7c408001, 0x88000000, 0x31ac2580, 0x9ac00011,
-+	0x31ac260c, 0x9ac0000f, 0x31ac0800, 0x9ac0000d, 0x31ac0828, 0x9ac0000b, 0x31ac2440, 0x9ac00009,
-+	0x31ac2390, 0x9ac00007, 0x31ac0093, 0x9ac00005, 0x31ac31dc, 0x9ac00003, 0x31ac31e6, 0x96c00004,
-+	0xc4340004, 0xd8400008, 0x80000ef2, 0x39ac7c06, 0x3db07c00, 0x9ac00003, 0x97000002, 0x80000f40,
-+	0x39acc337, 0x3db0c330, 0x9ac00003, 0x97000002, 0x80000f40, 0x39acc335, 0x3db0c336, 0x9ac00003,
-+	0x97000002, 0x80000f40, 0x39acec70, 0x3db0ec6f, 0x9ac00003, 0x97000002, 0x80000f40, 0x39ac9002,
-+	0x3db09002, 0x9ac00003, 0x97000002, 0x80000f40, 0x39ac9012, 0x3db09012, 0x9ac00003, 0x97000002,
-+	0x80000f40, 0x80000ef1, 0xc40c0006, 0x98c0ffff, 0x7c40c001, 0x7c410001, 0x7c414001, 0x7c418001,
-+	0x7c41c001, 0x7c43c001, 0x95c00001, 0xc434000e, 0x2b740008, 0x2b780001, 0xcf400013, 0xd8c1325e,
-+	0xcf80001a, 0xd8400013, 0x7c034001, 0x7c038001, 0x18e0007d, 0x32240003, 0x9a400006, 0x32240000,
-+	0x9a400004, 0xcd01c080, 0xcd41c081, 0x80000f88, 0x51640020, 0x7e52401a, 0xd2400072, 0xc8280072,
-+	0xce81c080, 0x56ac0020, 0x26f0ffff, 0xcf01c081, 0x1af000fc, 0x1334000a, 0x24e02000, 0x7f63400a,
-+	0x18e00074, 0x32240003, 0x9a400006, 0x32240000, 0x9a400004, 0xcd81c082, 0xcdc1c083, 0x80000f9d,
-+	0x51e40020, 0x7e5a401a, 0xd2400072, 0xc8280072, 0xce81c082, 0x56ac0020, 0x26f0ffff, 0xcf01c083,
-+	0x1af000fc, 0x13380016, 0x18e00039, 0x12200019, 0x7fa3800a, 0x7fb7800a, 0x18e0007d, 0x1220001d,
-+	0x7fa3800a, 0x18e00074, 0x12200014, 0x7fa3800a, 0xcf81c078, 0xcfc1c084, 0x80000c16, 0x7c40c001,
-+	0x18dc003d, 0x95c00004, 0x041c0000, 0x042c01c8, 0x8c000d61, 0x18d001e8, 0x31140005, 0x99400003,
-+	0x31140006, 0x95400002, 0x8c00104f, 0x05280fb7, 0x28140002, 0xcd400013, 0x86800000, 0x80000fbe,
-+	0x80000fbe, 0x80000fc2, 0x80000fbe, 0x80000fd1, 0x80000ff2, 0x80000ff2, 0x24cc003f, 0xccc1a2a4,
-+	0x7c408001, 0x88000000, 0x7c414001, 0x18e80039, 0x52a8003b, 0x50580020, 0x24cc003f, 0x7d59401a,
-+	0xd1400072, 0xc8140072, 0x7d69401a, 0xc41c0017, 0x99c0ffff, 0xd140004b, 0xccc1a2a4, 0x7c408001,
-+	0x88000000, 0xc414000d, 0x04180001, 0x24cc003f, 0x7d958004, 0xcd800035, 0xccc1a2a4, 0xc43c000e,
-+	0x2bfc0008, 0xcfc00013, 0xc43d3249, 0x1bfc003e, 0x97c00002, 0xd8400074, 0xc4100019, 0x7d150005,
-+	0x25100001, 0x9500000b, 0x97c0fffc, 0xc4180021, 0x159c0011, 0x259800ff, 0x31a00003, 0x31a40001,
-+	0x7e25800a, 0x95c0fff5, 0x9580fff4, 0x80000fef, 0xc411326f, 0x1d100010, 0xcd01326f, 0x97c00002,
-+	0xd8000074, 0x80001b70, 0x04380000, 0xc430000d, 0xc8140023, 0xc4180081, 0x13300005, 0xc011000f,
-+	0xc4240004, 0x33b40003, 0x97400003, 0xc0340008, 0x80000ffe, 0xc4340035, 0x11a00002, 0x7c908009,
-+	0x12640004, 0x7d614011, 0xc4100026, 0x05980008, 0x7ca4800a, 0x7d1a0002, 0x7cb0800a, 0x282c2002,
-+	0x208801a8, 0x3e280008, 0x7cb4800a, 0xcec00013, 0xc4300027, 0x042c0008, 0xd1400025, 0xcf000024,
-+	0x20240030, 0x7ca48001, 0xcc800026, 0xccc00026, 0x9b800013, 0xcc400026, 0x7c414001, 0x28340000,
-+	0xcf400013, 0x507c0020, 0x7d7d401a, 0xd1400072, 0xc8140072, 0x557c0020, 0x28342002, 0xcf400013,
-+	0xcd400026, 0xcfc00026, 0xd4400026, 0x9a80000e, 0x32280000, 0x9a80000b, 0x8000102f, 0xcc000026,
-+	0xcc000026, 0xcc000026, 0xcc000026, 0xcc000026, 0x9a800005, 0x32280000, 0x9a800002, 0x9a000000,
-+	0x7c018001, 0xcc000026, 0xd8400027, 0x1cccfe08, 0xd8800013, 0xcec0003a, 0xccc1a2a4, 0xc43c000e,
-+	0x2bfc0008, 0xcfc00013, 0xc43d3249, 0x1bfc003e, 0x9bc00007, 0xc428000e, 0x16a80008, 0xce800009,
-+	0xc42c005e, 0x96c00b33, 0xd840003c, 0xc4200025, 0x7da2400f, 0x7da28002, 0x7e1ac002, 0x0aec0001,
-+	0x96400002, 0x7d2ac002, 0x3ef40010, 0x9b40f11d, 0x04380030, 0xcf81325e, 0x80000c16, 0xde410000,
-+	0xdcc10000, 0xdd010000, 0xdd410000, 0xdd810000, 0xddc10000, 0xde010000, 0xc40c000e, 0x7c024001,
-+	0x28cc0008, 0xccc00013, 0xc8100086, 0x5510003f, 0xc40d3249, 0x18cc003e, 0x98c00003, 0x99000011,
-+	0x80001075, 0x9900000c, 0xc40c0026, 0xc4100081, 0xc4140025, 0x7d15800f, 0x7d15c002, 0x7d520002,
-+	0x0a200001, 0x95800002, 0x7cde0002, 0x3e20001a, 0x9a000009, 0x040c0030, 0xccc1325e, 0x80001071,
-+	0xd9c00036, 0xd8400029, 0xc40c005e, 0x94c00b01, 0x04240001, 0xdc200000, 0xdc1c0000, 0xdc180000,
-+	0xdc140000, 0xdc100000, 0xdc0c0000, 0x96400004, 0xdc240000, 0xdc0c0000, 0x80000c16, 0xdc240000,
-+	0x90000000, 0xcc40003f, 0xd8c00010, 0xc4080029, 0xcc80003b, 0xc418000e, 0x18a800e5, 0x1d980008,
-+	0x12a80008, 0x7da9800a, 0x29980008, 0xcd800013, 0x18a400e5, 0x12500009, 0x248c0008, 0x94c00006,
-+	0x200c006d, 0x7cd0c00a, 0xccc1326c, 0xc421326c, 0x96000001, 0xcd800013, 0x200c0228, 0x7cd0c00a,
-+	0xccc1326c, 0xc421326c, 0x96000001, 0xc40c002a, 0xc410002b, 0x18881fe8, 0x18d4072c, 0x18cc00d1,
-+	0x7cd4c00a, 0x3094000d, 0x38d80000, 0x311c0003, 0x99400006, 0x30940007, 0x1620001f, 0x9940001d,
-+	0x9a000023, 0x800010c4, 0x9580001a, 0x99c00019, 0xccc00041, 0x25140001, 0xc418002c, 0x9940000d,
-+	0x259c007f, 0x95c00013, 0x19a00030, 0xcdc0001b, 0xd8400021, 0xd8400022, 0xc430000f, 0x17300001,
-+	0x9b00fffe, 0x9a000012, 0xd8400023, 0x800010cb, 0x199c0fe8, 0xcdc0001b, 0xd8400021, 0xd8400023,
-+	0xc430000f, 0x17300001, 0x9b00fffe, 0x800010cb, 0xd8c00010, 0xd8000022, 0xd8000023, 0xc430005e,
-+	0x97000aac, 0x7c408001, 0x88000000, 0xc43c000e, 0xc434002e, 0x2bfc0008, 0x2020002c, 0xcfc00013,
-+	0xce01326c, 0x17780001, 0x27740001, 0x07a810d8, 0xcf400010, 0xc421326c, 0x96000001, 0x86800000,
-+	0x80000168, 0x80000aa7, 0x80000bfc, 0x800012e9, 0x8000104c, 0xcc400040, 0xd8800010, 0xc4180032,
-+	0x29980008, 0xcd800013, 0x200c007d, 0xccc1325b, 0xc411325b, 0x95000001, 0x7c408001, 0x88000000,
-+	0x28240007, 0xde430000, 0xd4400078, 0x80001190, 0xcc80003b, 0x24b00008, 0xc418000e, 0x1330000a,
-+	0x18a800e5, 0x1d980008, 0x12a80008, 0x7da9800a, 0x29980008, 0xcd800013, 0xc40d3249, 0x18cc003e,
-+	0x98c00002, 0xd840003d, 0x2b304000, 0xcf01326c, 0xc431326c, 0x7c40c001, 0x7c410001, 0x7c414001,
-+	0x192400fd, 0x50580020, 0x7d59401a, 0x7c41c001, 0x06681110, 0x7c420001, 0xcc400078, 0x18ac0024,
-+	0x19180070, 0x19100078, 0xcec00008, 0x18f40058, 0x5978073a, 0x7f7b400a, 0x97000001, 0x86800000,
-+	0x80001117, 0x80001118, 0x80001122, 0x8000112d, 0x80001130, 0x80001133, 0x8000016a, 0x8000117b,
-+	0x24ec0f00, 0x32ec0600, 0x96c00003, 0xc4300006, 0x9b00ffff, 0xd1400025, 0xcf400024, 0xcdc00026,
-+	0xd8400027, 0x8000117b, 0x24ec0f00, 0x32ec0600, 0x96c00003, 0xc4300006, 0x9b00ffff, 0xd1400025,
-+	0xcf400024, 0xcdc00026, 0xce000026, 0xd8400027, 0x8000117b, 0xc81c001f, 0x55e00020, 0x80001122,
-+	0xc81c0020, 0x55e00020, 0x80001122, 0x8c00116b, 0xd8400013, 0xc02a0200, 0x7e8e8009, 0x22a8003d,
-+	0x22a80074, 0x2774001c, 0x13740014, 0x7eb6800a, 0x25ecffff, 0x55700020, 0x15f40010, 0x13740002,
-+	0x275c001f, 0x95c00027, 0x7c018001, 0x7f41c001, 0x15dc0002, 0x39e00008, 0x25dc0007, 0x7dc1c01e,
-+	0x05dc0001, 0x96000004, 0x05e40008, 0x8c00116e, 0x80001168, 0x7dc2001e, 0x06200001, 0x05e40008,
-+	0x7e62000e, 0x9a000004, 0x7da58001, 0x8c00116e, 0x80001165, 0x7dc2001e, 0x06200001, 0x7e1a0001,
-+	0x05cc0008, 0x7e0d000e, 0x95000007, 0x7e02401e, 0x06640001, 0x06640008, 0x05d80008, 0x8c00116e,
-+	0x80001168, 0x7dc2401e, 0x06640001, 0x7da58001, 0x8c00116e, 0x05e00008, 0x7da2000c, 0x9600ffe6,
-+	0x17640002, 0x8c00116e, 0x80001190, 0xc4200006, 0x9a00ffff, 0x90000000, 0x8c00116b, 0xc420000e,
-+	0x2a200001, 0xce00001a, 0xce81c078, 0xcec1c080, 0xcc01c081, 0xcd41c082, 0xcf01c083, 0x12640002,
-+	0x22640435, 0xce41c084, 0x90000000, 0x0528117e, 0x312c0003, 0x86800000, 0x80001190, 0x80001185,
-+	0x80001182, 0x80001182, 0xc4300012, 0x9b00ffff, 0x9ac0000c, 0xc03a0400, 0xc4340004, 0xd8400013,
-+	0xd8400008, 0xc418000e, 0x15980008, 0x1198001c, 0x7d81c00a, 0xcdc130b7, 0xcf8130b5, 0xcf400008,
-+	0x04240008, 0xc418000e, 0xc41c0049, 0x19a000e8, 0x29a80008, 0x7de2c00c, 0xce800013, 0xc421325e,
-+	0x26200010, 0xc415326d, 0x9a000006, 0xc420007d, 0x96000004, 0x96c00003, 0xce40003e, 0x800011a3,
-+	0x7d654001, 0xcd41326d, 0x7c020001, 0x96000005, 0xc4100026, 0xc4240081, 0xc4140025, 0x800011b6,
-+	0xc4253279, 0xc415326d, 0xc431326c, 0x2730003f, 0x3b380006, 0x97800004, 0x3f38000b, 0x9b800004,
-+	0x800011b4, 0x04300006, 0x800011b4, 0x0430000b, 0x04380002, 0x7fb10004, 0x7e57000f, 0x7e578002,
-+	0x7d67c002, 0x0be40001, 0x97000002, 0x7d3a4002, 0x202c002c, 0xc421325e, 0x04280020, 0xcec1326c,
-+	0x26200010, 0x3e640010, 0x96000003, 0x96400002, 0xce81325e, 0xc4300028, 0xc434002e, 0x17780001,
-+	0x27740001, 0x07a811cf, 0x9b00feb8, 0xcf400010, 0xc414005e, 0x954009a7, 0x86800000, 0x80000168,
-+	0x80000aa7, 0x80000bfc, 0x800012e9, 0x80000168, 0x8c00120d, 0x7c40c001, 0xccc1c07c, 0xcc41c07d,
-+	0xcc41c08c, 0x7c410001, 0xcc41c079, 0xcd01c07e, 0x7c414001, 0x18f0012f, 0x18f40612, 0x18cc00c1,
-+	0x7f73400a, 0x7cf7400a, 0x39600004, 0x9a000002, 0xc0140004, 0x11600001, 0x18fc003e, 0x9740001c,
-+	0xcf400041, 0xc425c07f, 0x97c00003, 0x166c001f, 0x800011ee, 0x1a6c003e, 0x96c00006, 0x04200002,
-+	0x0a200001, 0x9a00ffff, 0xd8400013, 0x800011e8, 0xc428002c, 0x96800010, 0x26ac007f, 0xcec0001b,
-+	0xd8400021, 0x1ab00030, 0x1aac0fe8, 0xc434000f, 0x9b40ffff, 0x97000008, 0xcec0001b, 0xd8400021,
-+	0xc434000f, 0x9b40ffff, 0x80001205, 0x0a200001, 0x9a00ffff, 0xd8400013, 0xc425c07f, 0x166c001f,
-+	0x11600001, 0x9ac0fffa, 0x8c001232, 0x7c408001, 0x88000000, 0xd8000033, 0xc438000b, 0xc43c0009,
-+	0x27fc0001, 0x97c0fffe, 0xd8400013, 0xd841c07f, 0xc43dc07f, 0x1bfc0078, 0x7ffbc00c, 0x97c0fffd,
-+	0x90000000, 0xc03a2800, 0xcf81c07c, 0xcc01c07d, 0xcc01c08c, 0xcc01c079, 0xcc01c07e, 0x04380040,
-+	0xcf80001b, 0xd8400021, 0xc438000f, 0x9b80ffff, 0x04380060, 0xcf80001b, 0xd8400021, 0xc438000f,
-+	0x9b80ffff, 0x04380002, 0x0bb80001, 0x9b80ffff, 0xd8400013, 0xc43dc07f, 0x17fc001f, 0x04380010,
-+	0x9bc0fffa, 0x90000000, 0xd8400013, 0xd801c07f, 0xd8400013, 0xc43dc07f, 0xcfc00078, 0xd8000034,
-+	0x90000000, 0xc03ae000, 0xcf81c200, 0xc03a0800, 0xcf81c07c, 0xcc01c07d, 0xcc01c08c, 0xcc01c079,
-+	0xcc01c07e, 0x04380040, 0xcf80001b, 0xd8400021, 0xc438000f, 0x9b80ffff, 0x04380002, 0x0bb80001,
-+	0x9b80ffff, 0xd8400013, 0xc43dc07f, 0x17fc001f, 0x04380010, 0x9bc0fffa, 0x90000000, 0xc03ae000,
-+	0xcf81c200, 0xc03a4000, 0xcf81c07c, 0xcc01c07d, 0xcc01c08c, 0xcc01c079, 0xcc01c07e, 0x04380002,
-+	0x0bb80001, 0x9b80ffff, 0xd8400013, 0xc43dc07f, 0x17fc001f, 0x04380010, 0x9bc0fffa, 0x90000000,
-+	0xc40c0007, 0x30d00002, 0x99000052, 0xd8400029, 0xc424005e, 0x9640090f, 0x7c410001, 0xc428000e,
-+	0x1514001f, 0x19180038, 0x2aa80008, 0x99400030, 0x30dc0001, 0xce800013, 0x99c0000a, 0xc42d324e,
-+	0xc431324d, 0x52ec0020, 0x7ef2c01a, 0xc435324f, 0xc4293256, 0x1ab0c006, 0x52ec0008, 0x8000127f,
-+	0xc42d3258, 0xc4313257, 0x52ec0020, 0x7ef2c01a, 0xc4353259, 0xc429325a, 0x1ab0c012, 0x07740001,
-+	0x04240002, 0x26a0003f, 0x7e624004, 0x7f67800f, 0x97800002, 0x04340000, 0x53740002, 0x7ef6c011,
-+	0x1ab42010, 0x16a8000c, 0x26a80800, 0x2b740000, 0x7f73400a, 0x7f6b400a, 0xcf40001c, 0xd2c0001e,
-+	0xd8400021, 0xc438000f, 0x9b80ffff, 0xc4100011, 0x1514001f, 0x99400006, 0x9980000a, 0x8c0012e1,
-+	0xc40c0007, 0x04100000, 0x80001267, 0xd800002a, 0xc424005e, 0x964008d7, 0xd9800036, 0x80000c16,
-+	0xc42c001d, 0x95c00005, 0xc431325a, 0x1b300677, 0x11dc000c, 0x800012aa, 0xc4313256, 0x1b34060b,
-+	0x1b300077, 0x7f37000a, 0x13300017, 0x04340100, 0x26ec00ff, 0xc03a8002, 0x7ef6c00a, 0x7edec00a,
-+	0x7f3b000a, 0x7ef2c00a, 0xcec1325b, 0x80000c16, 0xc4140032, 0xc410001d, 0x29540008, 0xcd400013,
-+	0xc40d325b, 0x1858003f, 0x251000ff, 0x99800007, 0x7d0cc00a, 0xccc1325b, 0xc411325d, 0x251001ef,
-+	0xcd01325d, 0x80000168, 0x18d0006c, 0x18d407f0, 0x9900000e, 0x04100002, 0xc4193256, 0xc41d324f,
-+	0x2598003f, 0x7d190004, 0x7d5d4001, 0x7d52000f, 0x9a000003, 0xcd41324f, 0x800012d8, 0x7d514002,
-+	0xcd41324f, 0x800012d8, 0xc4193259, 0xc41d325a, 0x7d958001, 0x7dd5c002, 0xcd813259, 0xcdc1325a,
-+	0xc411325d, 0x251001ef, 0xcd01325d, 0x1ccc001e, 0xccc1325b, 0xc40d325b, 0x94c00001, 0x7c408001,
-+	0x88000000, 0xc40c0021, 0xc4340028, 0x14f00010, 0xc4380030, 0xc43c0007, 0x9b000004, 0x9b40000c,
-+	0x9b80000f, 0x90000000, 0x17300001, 0x9b000005, 0xccc00037, 0x8c000190, 0xd8000032, 0x90000000,
-+	0xd8000028, 0xd800002b, 0x80000168, 0xd980003f, 0x97c00002, 0xd9c0003f, 0x80001082, 0xd9800040,
-+	0x97c00002, 0xd9c00040, 0x800010de, 0xc43c0007, 0x33f80003, 0x97800051, 0xcc80003b, 0x24b00008,
-+	0xc418000e, 0x1330000a, 0x18a800e5, 0x1d980008, 0x12a80008, 0x7da9800a, 0x29980008, 0xcd800013,
-+	0xc4353249, 0x1b74003e, 0x9b400002, 0xd840003d, 0x2b304000, 0xcf01326c, 0xc431326c, 0x97000001,
-+	0x7c434001, 0x1b4c00f8, 0x7c410001, 0x7c414001, 0x50700020, 0x04e81324, 0x18ac0024, 0x7c41c001,
-+	0x50600020, 0xcc400078, 0x30e40004, 0x9a400007, 0x7d71401a, 0x596401fc, 0x12640009, 0x1b74008d,
-+	0x7e76400a, 0x2a640000, 0xcec00008, 0x86800000, 0x8000016a, 0x8000016a, 0x8000016a, 0x8000016a,
-+	0x8000132c, 0x8000133b, 0x80001344, 0x8000016a, 0xc4340004, 0xd8400013, 0xd8400008, 0xc42530b5,
-+	0x1a68003a, 0x9a80fffe, 0x2024003a, 0xc418000e, 0x25980700, 0x11980014, 0x7d19000a, 0xcd0130b7,
-+	0xce4130b5, 0xcf400008, 0x80001190, 0xce40001c, 0xd140001e, 0xd8400021, 0xc428000f, 0x9a80ffff,
-+	0xc4240011, 0x7de6800f, 0x9a80ffea, 0x80001190, 0xce40001c, 0xd140001e, 0xd8400021, 0xc428000f,
-+	0x9a80ffff, 0xc8240011, 0x7de1c01a, 0x7de6800f, 0x9a80ffe0, 0x80001190, 0x8c00104f, 0x28182002,
-+	0xc430000d, 0xc4340035, 0xcd800013, 0xc8140023, 0xc4180081, 0x13300005, 0xc4240004, 0x11a00002,
-+	0x12640004, 0x7d614011, 0xc4100026, 0x05980008, 0x7ca4800a, 0x7d1a0002, 0x7cb0800a, 0x3e280008,
-+	0x7cb4800a, 0xc4300027, 0x042c0008, 0xd1400025, 0xcf000024, 0x20240030, 0x7ca48001, 0xcc800026,
-+	0x7c434001, 0x1b4c00f8, 0xcf400026, 0xcc400026, 0x28340000, 0xcf400013, 0x7c414001, 0x507c0020,
-+	0x30e40004, 0x9a400005, 0x7d7d401a, 0xd1400072, 0xc8140072, 0x557c0020, 0x28342002, 0xcf400013,
-+	0xcd400026, 0xcfc00026, 0xd4400026, 0xcc000026, 0x9a800005, 0x32280000, 0x9a800002, 0x9a000000,
-+	0x7c018001, 0xd8400027, 0xd8800013, 0x04380028, 0xcec0003a, 0xcf81a2a4, 0x80001037, 0xd8400029,
-+	0xc40c005e, 0x94c007eb, 0x7c40c001, 0x50500020, 0x7d0d001a, 0xd1000072, 0xc8100072, 0x591c01fc,
-+	0x11dc0009, 0x45140210, 0x595801fc, 0x11980009, 0x29dc0000, 0xcdc0001c, 0xd140001e, 0xd8400021,
-+	0xc418000f, 0x9980ffff, 0xc4200011, 0x1624001f, 0x96400069, 0xc40c000e, 0x28cc0008, 0xccc00013,
-+	0xce013249, 0x1a307fe8, 0xcf00000a, 0x23304076, 0xd1000001, 0xcf000001, 0xc41d3254, 0xc4253256,
-+	0x18cc00e8, 0x10cc0015, 0x4514020c, 0xd140001e, 0xd8400021, 0xc418000f, 0x9980ffff, 0xc4200011,
-+	0xce013248, 0x1a2001e8, 0x12200014, 0x2a204001, 0xce000013, 0x1a64003c, 0x1264001f, 0x11dc0009,
-+	0x15dc000b, 0x7dcdc00a, 0x7e5dc00a, 0xcdc00100, 0xd8800013, 0xd8400010, 0xd800002a, 0xd8400008,
-+	0xcf00000d, 0xcf00000a, 0x8c001427, 0x04340022, 0x07740001, 0x04300010, 0xdf430000, 0x7c434001,
-+	0x7c408001, 0xd4412e01, 0x0434001e, 0xdf430000, 0xd4400078, 0xdf030000, 0xd4412e40, 0xd8400013,
-+	0xcc41c030, 0xcc41c031, 0x248dfffe, 0xccc12e00, 0xd8800013, 0xcc812e00, 0x7c434001, 0x7c434001,
-+	0x8c00142b, 0xd8000010, 0xc40c000e, 0x28cc0008, 0xccc00013, 0x45140248, 0xd140001e, 0xd8400021,
-+	0xc418000f, 0x9980ffff, 0xc8200011, 0xce013257, 0x56200020, 0xce013258, 0x0434000c, 0xdb000024,
-+	0xd1400025, 0xd8000026, 0xd8000026, 0xd8400027, 0x45540008, 0xd140001e, 0xd8400021, 0xc418000f,
-+	0x9980ffff, 0xc8200011, 0xce013259, 0x56200020, 0xc0337fff, 0x7f220009, 0xce01325a, 0x55300020,
-+	0x7d01c001, 0x042c01d0, 0x8c000d61, 0x06ec0004, 0x7f01c001, 0x8c000d61, 0x041c0002, 0x042c01c8,
-+	0x8c000d61, 0xc4380012, 0x9b80ffff, 0xd800002a, 0x80000aa7, 0xd800002a, 0x7c408001, 0x88000000,
-+	0xd8400029, 0x7c40c001, 0x50500020, 0x8c001427, 0x7cd0c01a, 0xc4200007, 0xd0c00072, 0xc8240072,
-+	0xd240001e, 0x7c414001, 0x19682011, 0x5a6c01fc, 0x12ec0009, 0x7eeac00a, 0x2aec0000, 0xcec0001c,
-+	0xd8400021, 0xc430000f, 0x9b00ffff, 0xc4180011, 0x7c438001, 0x99800007, 0xdf830000, 0xcfa0000c,
-+	0x8c00142b, 0xd4400078, 0xd800002a, 0x80001b70, 0x8c00142b, 0xd800002a, 0x80001b70, 0xd8000012,
-+	0xc43c0008, 0x9bc0ffff, 0x90000000, 0xd8400012, 0xc43c0008, 0x97c0ffff, 0x90000000, 0xc4380007,
-+	0x7c40c001, 0x17b80001, 0x18d40038, 0x7c410001, 0x9b800004, 0xd8400029, 0xc414005e, 0x9540073d,
-+	0x18c80066, 0x7c414001, 0x30880001, 0x7c418001, 0x94800008, 0x8c00187c, 0xcf400013, 0xc42c0004,
-+	0xd8400008, 0xcd910000, 0xcec00008, 0x7d410001, 0x043c0000, 0x7c41c001, 0x7c420001, 0x04240001,
-+	0x06200001, 0x4220000c, 0x0a640001, 0xcc000078, 0x9a40fffe, 0x24e80007, 0x24ec0010, 0xd8400013,
-+	0x9ac00006, 0xc42c0004, 0xd8400008, 0xc5310000, 0xcec00008, 0x80001465, 0x51540020, 0x7d15001a,
-+	0xd1000072, 0xc82c0072, 0xd2c0001e, 0x18f02011, 0x5aec01fc, 0x12ec0009, 0x7ef2c00a, 0x2aec0000,
-+	0xcec0001c, 0xd8400021, 0xc42c000f, 0x9ac0ffff, 0xc4300011, 0x96800012, 0x12a80001, 0x0aa80001,
-+	0x06a8146a, 0x7f1f0009, 0x86800000, 0x7f1b400f, 0x80001478, 0x7f1b400e, 0x80001478, 0x7f1b400c,
-+	0x8000147a, 0x7f1b400d, 0x8000147a, 0x7f1b400f, 0x8000147a, 0x7f1b400e, 0x8000147a, 0x7f334002,
-+	0x97400014, 0x8000147b, 0x9b400012, 0x9b800005, 0x9bc0001f, 0x7e024001, 0x043c0001, 0x8000144a,
-+	0xc40c0032, 0xc438001d, 0x28cc0008, 0xccc00013, 0xc43d325b, 0x1bb81ff0, 0x7fbfc00a, 0xcfc1325b,
-+	0xc411325d, 0x251001ef, 0xcd01325d, 0x80001b70, 0x94800007, 0x8c00187c, 0xcf400013, 0xc42c0004,
-+	0xd8400008, 0xcd910000, 0xcec00008, 0x9b800003, 0xd800002a, 0x80001b70, 0xc40c0032, 0x28cc0008,
-+	0xccc00013, 0xc40d325b, 0x800012c2, 0xc40c000e, 0xc43c0007, 0xc438001d, 0x28cc0008, 0xccc00013,
-+	0x13f4000c, 0x9bc00006, 0xc43d3256, 0x1bf0060b, 0x1bfc0077, 0x7ff3c00a, 0x800014a9, 0xc43d325a,
-+	0x1bfc0677, 0x04300100, 0x1bb81ff0, 0x7f73400a, 0xc0328007, 0x7fb7800a, 0x13fc0017, 0x7ff3c00a,
-+	0x7ffbc00a, 0xcfc1325b, 0xc03a0002, 0xc4340004, 0xd8400013, 0xd8400008, 0xcf8130b5, 0xcf400008,
-+	0x80000c16, 0x043c0000, 0xc414000e, 0x29540008, 0xcd400013, 0xc4193246, 0xc41d3245, 0x51980020,
-+	0x7dd9c01a, 0x45dc0390, 0xc4313267, 0x04183000, 0xcd813267, 0x1b380057, 0x1b340213, 0x1b300199,
-+	0x7f7b400a, 0x7f73400a, 0xcf400024, 0xd1c00025, 0xcc800026, 0x7c420001, 0xce000026, 0x7c424001,
-+	0xce400026, 0x7c428001, 0xce800026, 0x7c42c001, 0xcec00026, 0x7c430001, 0xcf000026, 0x7c434001,
-+	0xcf400026, 0x7c438001, 0xcf800026, 0xd8400027, 0xcd400013, 0x04182000, 0xcd813267, 0xd840004f,
-+	0x1a0800fd, 0x109c000a, 0xc4193265, 0x7dd9c00a, 0xcdc13265, 0x2620ffff, 0xce080228, 0x9880000e,
-+	0xce480250, 0xce880258, 0xd8080230, 0xd8080238, 0xd8080240, 0xd8080248, 0xd8080268, 0xd8080270,
-+	0xd8080278, 0xd8080280, 0xd800004f, 0x97c0ec75, 0x90000000, 0x040c0000, 0x041c0010, 0x26180001,
-+	0x09dc0001, 0x16200001, 0x95800002, 0x04cc0001, 0x99c0fffb, 0xccc80230, 0xd8080238, 0xd8080240,
-+	0xd8080248, 0x040c0000, 0xce480250, 0xce880258, 0x52a80020, 0x7e6a401a, 0x041c0020, 0x66580001,
-+	0x09dc0001, 0x56640001, 0x95800002, 0x04cc0001, 0x99c0fffb, 0xccc80260, 0xd8080268, 0xd8080270,
-+	0xd8080278, 0xd8080280, 0x040c0000, 0xcec80288, 0xcf080290, 0xcec80298, 0xcf0802a0, 0x040c0000,
-+	0x041c0010, 0xcf4802a8, 0x27580001, 0x09dc0001, 0x17740001, 0x95800002, 0x04cc0001, 0x99c0fffb,
-+	0xccc802b0, 0xd80802b8, 0x178c000b, 0x27b8003f, 0x7cf8c001, 0xcf8802c0, 0xccc802c8, 0xcf8802d0,
-+	0xcf8802d8, 0xd800004f, 0x97c00002, 0x90000000, 0x7c408001, 0x88000000, 0xc40c000e, 0x28cc0008,
-+	0xccc00013, 0xc43d3265, 0x1bc800ea, 0x7c418001, 0x25b8ffff, 0xc4930240, 0xc48f0238, 0x04cc0001,
-+	0x24cc000f, 0x7cd2800c, 0x9a80000b, 0xc5230309, 0x2620ffff, 0x7e3a400c, 0x9a400004, 0x05100001,
-+	0x2510000f, 0x80001539, 0xcd08034b, 0xd4400078, 0x80000168, 0xc48f0230, 0xc4930240, 0x98c00004,
-+	0xcd880353, 0x8c00163f, 0xc49b0353, 0xc4930238, 0xc48f0228, 0x05100001, 0x2510000f, 0x7cd14005,
-+	0x25540001, 0x99400004, 0x05100001, 0x2510000f, 0x8000154f, 0xc48f0230, 0x7c41c001, 0xcd080238,
-+	0xcd08034b, 0x08cc0001, 0x2598ffff, 0x3d200008, 0xccc80230, 0xcd900309, 0xd8100319, 0x04340801,
-+	0x2198003f, 0xcf400013, 0xcd910ce7, 0xc4190ce6, 0x7d918005, 0x25980001, 0x9580fffd, 0x7d918004,
-+	0xcd810ce6, 0x9a000003, 0xcdd1054f, 0x8000156e, 0x090c0008, 0xcdcd050e, 0x040c0000, 0x110c0014,
-+	0x28cc4001, 0xccc00013, 0xcc41230a, 0xcc41230b, 0xcc41230c, 0xcc41230d, 0xcc480329, 0xcc48032a,
-+	0xcc4802e0, 0xd8000055, 0xc48f02e0, 0x24d8003f, 0x09940001, 0x44100001, 0x9580002c, 0x95400005,
-+	0x09540001, 0x51100001, 0x69100001, 0x8000157f, 0x24cc003f, 0xc4970290, 0xc49b0288, 0x51540020,
-+	0x7d59401a, 0xc49b02a0, 0xc49f0298, 0x51980020, 0x7d9d801a, 0x041c0040, 0x04200000, 0x7dcdc002,
-+	0x7d924019, 0x7d26400c, 0x09dc0001, 0x9a400008, 0x51100001, 0x06200001, 0x99c0fffa, 0xc48f0230,
-+	0xc4930240, 0x8c00163f, 0x80001579, 0x7d010021, 0x7d914019, 0xc4930238, 0x55580020, 0xcd480298,
-+	0xcd8802a0, 0x10d40010, 0x12180016, 0xc51f0309, 0x7d95800a, 0x7d62000a, 0x7dd9c00a, 0xd8400013,
-+	0xcdd00309, 0xce113320, 0xc48f02e0, 0xc49b02b0, 0x18dc01e8, 0x7dd9400e, 0xc48f0230, 0xc4930240,
-+	0x95c0001d, 0x95400003, 0x8c00163f, 0x800015aa, 0xc48f0238, 0xc4a302b8, 0x12240004, 0x7e5e400a,
-+	0xc4ab02a8, 0x04100000, 0xce4c0319, 0x7d9d8002, 0x7ea14005, 0x25540001, 0x99400004, 0x06200001,
-+	0x2620000f, 0x800015bc, 0x09dc0001, 0x04240001, 0x7e624004, 0x06200001, 0x7d25000a, 0x2620000f,
-+	0x99c0fff4, 0xd8400013, 0xcd0d3330, 0xce0802b8, 0xcd8802b0, 0xc4ab02e0, 0x1aa807f0, 0xc48f02d0,
-+	0xc49702d8, 0xc49b02c8, 0xc49f02c0, 0x96800028, 0x7d4e000f, 0x9600000b, 0x7d964002, 0x7e6a000f,
-+	0x96000003, 0x7d694001, 0x800015e9, 0x7cde4002, 0x7e6a000f, 0x96000008, 0x7de94001, 0x800015e9,
-+	0x7cd64002, 0x7e6a000e, 0x96000003, 0x7d694001, 0x800015e9, 0xc48f0230, 0xc4930240, 0x8c00163f,
-+	0x800015cd, 0xc4930238, 0x7d698002, 0xcd4802d8, 0x129c0008, 0xc50f0319, 0x11a0000e, 0x11140001,
-+	0xc4340004, 0xd8400008, 0xd8400013, 0x7e1e000a, 0x1198000a, 0xcd953300, 0x7e0e000a, 0x12a8000a,
-+	0xce953301, 0xce100319, 0xcf400008, 0xc4b70280, 0xc4b30278, 0x7f73800a, 0x536c0020, 0x7ef2c01a,
-+	0x9780eb68, 0x8c001608, 0xd8080278, 0xd8080280, 0x7c408001, 0x88000000, 0x043c0003, 0x80001609,
-+	0x043c0001, 0x30b40000, 0x9b400011, 0xc4b70258, 0xc4b30250, 0x53780020, 0x7fb3801a, 0x7faf8019,
-+	0x04300020, 0x04280000, 0x67b40001, 0x0b300001, 0x57b80001, 0x97400002, 0x06a80001, 0x9b00fffb,
-+	0xc4bb0260, 0x7fab8001, 0xcf880260, 0x04300020, 0x04280000, 0x66f40001, 0x0b300001, 0x56ec0001,
-+	0x97400005, 0x8c001628, 0xc4353247, 0x7f7f4009, 0x9b40fffe, 0x06a80001, 0x9b00fff7, 0x90000000,
-+	0x269c0007, 0x11dc0008, 0x29dc0008, 0x26a00018, 0x12200003, 0x7de1c00a, 0x26a00060, 0x06200020,
-+	0x16200001, 0x7de1c00a, 0xcdc00013, 0x90000000, 0x269c0018, 0x26a00007, 0x26a40060, 0x11dc0006,
-+	0x12200006, 0x16640001, 0x29dc0008, 0x7de1c00a, 0x7de5c00a, 0xcdc00013, 0x90000000, 0xc4b70228,
-+	0x05100001, 0x04cc0001, 0x2510000f, 0xccc80230, 0x7f514005, 0x25540001, 0x99400004, 0x05100001,
-+	0x2510000f, 0x80001644, 0xc4b30248, 0xcd080240, 0x7f130005, 0x27300001, 0x9b000002, 0x8c001688,
-+	0x8c00120d, 0x8c001219, 0x8c001232, 0x04300001, 0x04340801, 0x7f130004, 0xcf400013, 0xcf01051e,
-+	0xc42d051f, 0x7ed2c005, 0x26ec0001, 0x96c0fffd, 0xcf01051f, 0xd8000055, 0xc5170309, 0x195c07f0,
-+	0x196007f6, 0x04340000, 0x95c00008, 0x09dc0001, 0x04340001, 0x95c00005, 0x09dc0001, 0x53740001,
-+	0x6b740001, 0x80001665, 0xc4a702a0, 0xc4ab0298, 0x52640020, 0x7e6a401a, 0x7f634014, 0x7e76401a,
-+	0xc4300004, 0xd8400008, 0xd8400013, 0x56680020, 0xd8113320, 0xce480298, 0xce8802a0, 0xc5170319,
-+	0xc4b702b0, 0x255c000f, 0x7f5f4001, 0xd8113330, 0xcf4802b0, 0x11340001, 0x195c07e8, 0x196007ee,
-+	0xd8353300, 0x7e1e4001, 0xd8353301, 0xce4802d0, 0xd8100309, 0xd8100319, 0xcf000008, 0x90000000,
-+	0xc4970258, 0xc48f0250, 0x51540020, 0x7cd4c01a, 0xc4af0280, 0xc4b30278, 0x52ec0020, 0x7ef2c01a,
-+	0x04140020, 0x04280000, 0x64d80001, 0x09540001, 0x54cc0001, 0x95800060, 0x8c001628, 0xc4193247,
-+	0x25980001, 0x9580005c, 0x7dc24001, 0xc41d3248, 0x25dc000f, 0x7dd2000c, 0x96000057, 0xc41d3255,
-+	0xc435324f, 0x7df5c00c, 0x99c00004, 0xc4193265, 0x25980040, 0x9580fffe, 0xc439325b, 0x1bb0003f,
-+	0x97000049, 0x1bb000e8, 0x33380003, 0x9b800046, 0x33300002, 0x9700000a, 0xc4393260, 0x1bb000e4,
-+	0x33300004, 0x97000040, 0xc431325d, 0x27300010, 0x9b00fffe, 0x800016f1, 0xce400013, 0xc033ffff,
-+	0x2f3000ff, 0xc439325b, 0x7f3b0009, 0xcf01325b, 0xc439325b, 0x27b800ff, 0x9b80fffe, 0xd8c00033,
-+	0xc4300009, 0x27300008, 0x9700fffe, 0x1a7003e6, 0x27380003, 0x13b80004, 0x27300003, 0x13300003,
-+	0x7fb38001, 0x1a7000e8, 0x7fb38001, 0x13300001, 0x7fb38001, 0x07b80002, 0xd8400013, 0x1a700064,
-+	0x33300002, 0x97000009, 0x17b00005, 0x07300003, 0xcf012082, 0xcc01203f, 0xd8400013, 0xcc01203f,
-+	0x0b300003, 0x800016df, 0x17b00005, 0xcf012082, 0xcc01203f, 0xd8400013, 0xcc01203f, 0x13300005,
-+	0x7fb30002, 0xc4392083, 0x7fb38005, 0x27b80001, 0x9b80ffdf, 0xd8c00034, 0xce400013, 0xc431325d,
-+	0x27300010, 0x9b00fffe, 0xc439325b, 0x27b000ff, 0x9b00ffca, 0xd841325d, 0x2030007b, 0xcf01325b,
-+	0x800016f2, 0xd841325d, 0x04300001, 0x7f2b0014, 0x7ef2c01a, 0x06a80001, 0x9940ff9c, 0x8c001608,
-+	0xd8080278, 0xd8080280, 0x90000000, 0xd840004f, 0xc414000e, 0x29540008, 0xcd400013, 0xc43d3265,
-+	0x1bc800ea, 0xd80802e9, 0x7c40c001, 0x18fc0064, 0x9bc00042, 0xc4193246, 0xc41d3245, 0x51980020,
-+	0x7dd9801a, 0x45980400, 0xc4313267, 0x043c3000, 0xcfc13267, 0xc43d3267, 0x9bc00001, 0x1b380057,
-+	0x1b340213, 0x1b300199, 0x7f7b400a, 0x7f73400a, 0xcf400024, 0x14f4001d, 0xc4bf02e9, 0x9bc0001c,
-+	0x7c410001, 0x192807fa, 0xc4bf0258, 0xc4a70250, 0x53fc0020, 0x7e7e401a, 0x042c0000, 0x04300000,
-+	0x667c0001, 0x56640001, 0x06ec0001, 0x97c0fffd, 0x07300001, 0x0aec0001, 0x7eebc00c, 0x06ec0001,
-+	0x97c0fff8, 0x0b300001, 0x43300007, 0x53300002, 0x7db30011, 0xd3000025, 0xc03ec005, 0x2bfca200,
-+	0xcfc00026, 0xccc00026, 0xcd000026, 0x192807fa, 0xc01f007f, 0x7d1d0009, 0x2110007d, 0x8c001628,
-+	0x203c003f, 0xcfc13256, 0x8c0017f5, 0xcd013254, 0x18fc01e8, 0xcfc13248, 0x8c00185b, 0xd8413247,
-+	0x0b740001, 0x9b40ffd5, 0xd800004f, 0xc4bf02e9, 0x97c0ea24, 0x90000000, 0x14d4001d, 0xc4930260,
-+	0x7d52400e, 0xc49f0258, 0xc4a30250, 0x51dc0020, 0x7de1801a, 0x96400017, 0x7d534002, 0xc4af0270,
-+	0x7dae4005, 0x26640001, 0x32e0001f, 0x9a400006, 0x06ec0001, 0x96000002, 0x042c0000, 0xcec80270,
-+	0x8000174f, 0x0b740001, 0x8c00178a, 0x05100001, 0x9b40fff3, 0xc4af0280, 0xc4b30278, 0x52ec0020,
-+	0x7ef2c01a, 0x8c001608, 0xd8080278, 0xd8080280, 0xc4ab0268, 0x7daa4005, 0x26640001, 0x32a0001f,
-+	0x9a400005, 0x06a80001, 0x96000002, 0x24280000, 0x80001765, 0x7c410001, 0xc01f007f, 0x09540001,
-+	0x7d1d0009, 0x2110007d, 0x8c001628, 0xd8013256, 0x8c0017f2, 0xcd013254, 0xc4113248, 0x15100004,
-+	0x11100004, 0xc4b3034b, 0x7f13000a, 0xcf013248, 0xc4930260, 0x8c001855, 0x32a4001f, 0xd8413247,
-+	0xd800004f, 0x09100001, 0x06a80001, 0x96400002, 0x24280000, 0xcd080260, 0xce880268, 0x9940ffc0,
-+	0x7c408001, 0x88000000, 0x7ec28001, 0x8c001628, 0x32e0001f, 0xc4253247, 0x26640001, 0x9640005e,
-+	0xc4293265, 0xc4253255, 0xc431324f, 0x7e72400c, 0x26a80040, 0x9a400002, 0x9680fff7, 0xc429325b,
-+	0x1aa4003f, 0x96400049, 0x1aa400e8, 0x32680003, 0x9a800046, 0x32640002, 0x9640000a, 0xc4293260,
-+	0x1aa400e4, 0x32640004, 0x96400040, 0xc425325d, 0x26640010, 0x9a40fffe, 0x800017e2, 0xcdc00013,
-+	0xc027ffff, 0x2e6400ff, 0xc429325b, 0x7e6a4009, 0xce41325b, 0xc429325b, 0x26a800ff, 0x9a80fffe,
-+	0xd8c00033, 0xc4240009, 0x26640008, 0x9640fffe, 0x19e403e6, 0x26680003, 0x12a80004, 0x26640003,
-+	0x12640003, 0x7ea68001, 0x19e400e8, 0x7ea68001, 0x12640001, 0x7ea68001, 0x06a80002, 0xd8400013,
-+	0x19e40064, 0x32640002, 0x96400009, 0x16a40005, 0x06640003, 0xce412082, 0xcc01203f, 0xd8400013,
-+	0xcc01203f, 0x0a640003, 0x800017d0, 0x16a40005, 0xce412082, 0xcc01203f, 0xd8400013, 0xcc01203f,
-+	0x12640005, 0x7ea64002, 0xc4292083, 0x7ea68005, 0x26a80001, 0x9a80ffdf, 0xd8c00034, 0xcdc00013,
-+	0xc425325d, 0x26640010, 0x9a40fffe, 0xc429325b, 0x26a400ff, 0x9a40ffca, 0xd841325d, 0x2024007b,
-+	0xce41325b, 0x800017e3, 0xd841325d, 0xc4a70280, 0xc4ab0278, 0x52640020, 0x7e6a401a, 0x04280001,
-+	0x7eae8014, 0x7e6a401a, 0x56680020, 0xce480278, 0xce880280, 0x06ec0001, 0x96000002, 0x042c0000,
-+	0xcec80270, 0x90000000, 0x7c438001, 0x7c420001, 0x800017fe, 0xc4bf02e9, 0x9bc00006, 0x7c438001,
-+	0x7c420001, 0xcf800026, 0xce000026, 0x800017fe, 0xc43b02eb, 0xc42302ec, 0xcf813245, 0xce013246,
-+	0x52200020, 0x7fa3801a, 0x47b8020c, 0x15e00008, 0x1220000a, 0x2a206032, 0x513c001e, 0x7e3e001a,
-+	0xc4bf02e9, 0x9bc00005, 0xc43c000e, 0x2bfc0008, 0xcfc00013, 0x8000180f, 0xcd400013, 0xc4313267,
-+	0x1b3c0077, 0x1b300199, 0x7ff3000a, 0x1330000a, 0x2b300032, 0x043c3000, 0xcfc13267, 0xc43d3267,
-+	0xd200000b, 0xc4200007, 0xd3800002, 0xcf000002, 0xd8000040, 0x96000002, 0xd8400040, 0xd8400018,
-+	0x043c2000, 0xcfc13267, 0xd8000018, 0xd8800010, 0xcdc00013, 0x7dc30001, 0xdc1e0000, 0x04380032,
-+	0xcf80000e, 0x8c001427, 0xcc413248, 0xc43d3269, 0x27fc000f, 0x33fc0003, 0x97c00011, 0x043c001f,
-+	0xdfc30000, 0xd4413249, 0x7c43c001, 0x7c43c001, 0x043c0024, 0x0bfc0021, 0xdfc30000, 0xd441326a,
-+	0x173c0008, 0x1b300303, 0x7f3f0001, 0x043c0001, 0x7ff3c004, 0xcfc13084, 0x80001842, 0x043c0024,
-+	0xdfc30000, 0xd4413249, 0x7c43c001, 0x23fc003f, 0xcfc1326d, 0x0bb80026, 0xdf830000, 0xd441326e,
-+	0x7c438001, 0x7c438001, 0xc4393265, 0x1fb8ffc6, 0xddc30000, 0xcf813265, 0x9a000003, 0xcdc0000c,
-+	0x80001852, 0xcdc0000d, 0xce000010, 0x8c00142b, 0x90000000, 0x7c41c001, 0x7c420001, 0xcdc13252,
-+	0xce013253, 0x8c001628, 0x80001878, 0xc49f02e9, 0x99c00018, 0x7c41c001, 0x7c420001, 0xcdc13252,
-+	0xce013253, 0xc43c000e, 0x2bfc0008, 0xcfc00013, 0x043c3000, 0xcfc13267, 0xc43d3267, 0x97c0ffff,
-+	0xcdc00026, 0xce000026, 0xd8400027, 0xc41c0012, 0x99c0ffff, 0xc43c000e, 0x2bfc0008, 0xcfc00013,
-+	0x043c2000, 0xcfc13267, 0x8c001628, 0x80001878, 0xc41f02ed, 0xc42302ee, 0xcdc13252, 0xce013253,
-+	0x04200001, 0x7e2a0004, 0xce013084, 0x90000000, 0x28340001, 0x313c0bcc, 0x9bc00010, 0x393c051f,
-+	0x9bc00004, 0x3d3c050e, 0x9bc0000c, 0x97c0000c, 0x393c0560, 0x9bc00004, 0x3d3c054f, 0x9bc00007,
-+	0x97c00007, 0x393c1538, 0x9bc00005, 0x3d3c1537, 0x9bc00002, 0x97c00002, 0x2b740800, 0x90000000,
-+	0xc40c000e, 0x28cc0008, 0xccc00013, 0xc43d3265, 0x1bc800ea, 0x7c40c001, 0x18e8007c, 0x7c42c001,
-+	0x06a8189a, 0x86800000, 0x8000189e, 0x800018c5, 0x800018f2, 0x8000016a, 0x7c414001, 0x18d0007e,
-+	0x50580020, 0x09200001, 0x7d59401a, 0xd1400072, 0xc8140072, 0x09240002, 0x7c418001, 0x7c41c001,
-+	0x99000011, 0xc4340004, 0xd8400013, 0xd8400008, 0xc42130b5, 0x1a24002c, 0x9a40fffe, 0x2020002c,
-+	0xc418000d, 0x1198001c, 0x10cc0004, 0x14cc0004, 0x7cd8c00a, 0xccc130b7, 0xce0130b5, 0xcf400008,
-+	0x80000168, 0xd1400025, 0x5978073a, 0x2bb80002, 0xcf800024, 0xcd800026, 0xcdc00026, 0xd8400027,
-+	0x9600e8a8, 0xc4300012, 0x9b00ffff, 0x9640e8a5, 0x800018a9, 0x04140000, 0xc55b0309, 0x3d5c0010,
-+	0x05540001, 0x2598ffff, 0x09780001, 0x7dad800c, 0x99c0ffd2, 0x9580fff9, 0xc4970258, 0xc4930250,
-+	0x51540020, 0x7d15001a, 0x04140020, 0x04280000, 0x442c0000, 0x65180001, 0x09540001, 0x55100001,
-+	0x9580000b, 0x8c001628, 0xc41d3248, 0x04300001, 0x7f2b0014, 0x25dc000f, 0x7df9c00c, 0x95c00004,
-+	0x7ef2c01a, 0xd8c13260, 0xd901325d, 0x06a80001, 0x9940fff1, 0x04140020, 0x04280000, 0x66d80001,
-+	0x09540001, 0x56ec0001, 0x95800005, 0x8c001628, 0xc421325d, 0x26240007, 0x9a40fffe, 0x06a80001,
-+	0x9940fff7, 0x8000189e, 0x04140020, 0x04280000, 0x09540001, 0x8c001628, 0xc41d3254, 0xc023007f,
-+	0x19e4003e, 0x7de1c009, 0x7dee000c, 0x96400008, 0x96000007, 0xd8c13260, 0xd901325d, 0xc421325d,
-+	0x261c0007, 0x99c0fffe, 0x8000189e, 0x06a80001, 0x9940fff0, 0x8000189e, 0xc40c000e, 0x28cc0008,
-+	0xccc00013, 0xc43d3265, 0x1bc800ea, 0x7c40c001, 0x18e00064, 0x06281911, 0x14f4001d, 0x24cc0003,
-+	0x86800000, 0x80001915, 0x800019af, 0x80001a2b, 0x8000016a, 0xcc48032b, 0xcc480333, 0xcc48033b,
-+	0xcc480343, 0x98800011, 0xc4213246, 0xc4253245, 0x52200020, 0x7e26401a, 0x46640400, 0xc4313267,
-+	0x04203000, 0xce013267, 0xc4213267, 0x9a000001, 0x1b3c0057, 0x1b200213, 0x1b300199, 0x7e3e000a,
-+	0x7e32000a, 0xce000024, 0xc4970258, 0xc4930250, 0x51540020, 0x7d15001a, 0xc4af0280, 0xc4b30278,
-+	0x52ec0020, 0x7ef2c01a, 0x04180000, 0x04140020, 0x04280000, 0x7f438001, 0x8c001628, 0xc41d3247,
-+	0x25dc0001, 0x95c00068, 0xc4213254, 0x1a1c003e, 0x95c00065, 0xc01f007f, 0x7e1e0009, 0x97800062,
-+	0x0bb80001, 0x43bc0008, 0x7fcbc001, 0xc7df032b, 0x7e1fc00c, 0x97c0fffa, 0x043c0101, 0x94c00002,
-+	0x043c0102, 0xc439325b, 0x1bb0003f, 0x97000049, 0x1bb000e8, 0x33380003, 0x9b800046, 0x33300002,
-+	0x97000009, 0xc4393260, 0x1bb000e4, 0x33300004, 0x97000040, 0xc431325d, 0x27300010, 0x9b00fffe,
-+	0x80001994, 0x8c001628, 0xc033ffff, 0x2f3000ff, 0xc439325b, 0x7f3b0009, 0xcf01325b, 0xc439325b,
-+	0x27b800ff, 0x9b80fffe, 0xd8c00033, 0xc4300009, 0x27300008, 0x9700fffe, 0x19f003e6, 0x27380003,
-+	0x13b80004, 0x27300003, 0x13300003, 0x7fb38001, 0x19f000e8, 0x7fb38001, 0x13300001, 0x7fb38001,
-+	0x07b80002, 0xd8400013, 0x19f00064, 0x33300002, 0x97000009, 0x17b00005, 0x07300003, 0xcf012082,
-+	0xcc01203f, 0xd8400013, 0xcc01203f, 0x0b300003, 0x80001982, 0x17b00005, 0xcf012082, 0xcc01203f,
-+	0xd8400013, 0xcc01203f, 0x13300005, 0x7fb30002, 0xc4392083, 0x7fb38005, 0x27b80001, 0x9b80ffdf,
-+	0xd8c00034, 0xcdc00013, 0xc431325d, 0x27300010, 0x9b00fffe, 0xc439325b, 0x27b000ff, 0x9b00ffcb,
-+	0xcfc1325d, 0x2030007b, 0xcf01325b, 0x80001995, 0xcfc1325d, 0x04300001, 0x7f2b0014, 0x7ef2c01a,
-+	0x98800009, 0x41bc0007, 0x53fc0002, 0x7e7fc011, 0xd3c00025, 0xd8000026, 0xd8400027, 0xc43c0012,
-+	0x9bc0ffff, 0x653c0001, 0x7dbd8001, 0x06a80001, 0x09540001, 0x55100001, 0x9940ff8f, 0xc43c000e,
-+	0x2bfc0008, 0xcfc00013, 0x043c2000, 0xcfc13267, 0xd8080278, 0xd8080280, 0x80000168, 0x7c410001,
-+	0x04140000, 0xc55b0309, 0x3d5c0010, 0x2598ffff, 0x05540001, 0x7d91800c, 0x95c00003, 0xd4400078,
-+	0x80000168, 0x9580fff8, 0x09780001, 0xc4970258, 0xc4930250, 0x51540020, 0x7d15001a, 0xc4af0280,
-+	0xc4b30278, 0x52ec0020, 0x7ef2c01a, 0x04140020, 0x04280000, 0x65180001, 0x09540001, 0x55100001,
-+	0x9580005d, 0x8c001628, 0xc4253247, 0x26640001, 0x04200101, 0x96400058, 0x7dc24001, 0xc41d3248,
-+	0x25dc000f, 0x7df9c00c, 0x95c00053, 0x94c00002, 0x04200102, 0x7e41c001, 0xc425325b, 0x1a70003f,
-+	0x97000049, 0x1a7000e8, 0x33240003, 0x9a400046, 0x33300002, 0x9700000a, 0xc4253260, 0x1a7000e4,
-+	0x33300004, 0x97000040, 0xc431325d, 0x27300010, 0x9b00fffe, 0x80001a21, 0xcdc00013, 0xc033ffff,
-+	0x2f3000ff, 0xc425325b, 0x7f270009, 0xcf01325b, 0xc425325b, 0x266400ff, 0x9a40fffe, 0xd8c00033,
-+	0xc4300009, 0x27300008, 0x9700fffe, 0x19f003e6, 0x27240003, 0x12640004, 0x27300003, 0x13300003,
-+	0x7e724001, 0x19f000e8, 0x7e724001, 0x13300001, 0x7e724001, 0x06640002, 0xd8400013, 0x19f00064,
-+	0x33300002, 0x97000009, 0x16700005, 0x07300003, 0xcf012082, 0xcc01203f, 0xd8400013, 0xcc01203f,
-+	0x0b300003, 0x80001a0f, 0x16700005, 0xcf012082, 0xcc01203f, 0xd8400013, 0xcc01203f, 0x13300005,
-+	0x7e730002, 0xc4252083, 0x7e724005, 0x26640001, 0x9a40ffdf, 0xd8c00034, 0xcdc00013, 0xc431325d,
-+	0x27300010, 0x9b00fffe, 0xc425325b, 0x267000ff, 0x9b00ffca, 0xce01325d, 0x2030007b, 0xcf01325b,
-+	0x80001a22, 0xce01325d, 0x04300001, 0x7f2b0014, 0x7ef2c01a, 0x06a80001, 0x9940ff9f, 0xd4400078,
-+	0xd8080278, 0xd8080280, 0x80000168, 0x8c001a31, 0xd4400078, 0xd8080278, 0xd8080280, 0x7c408001,
-+	0x88000000, 0xc4213246, 0xc4253245, 0x52200020, 0x7e26401a, 0x46640400, 0xc4313267, 0x04203000,
-+	0xce013267, 0xc4213267, 0x9a000001, 0x1b180057, 0x1b200213, 0x1b300199, 0x7e1a000a, 0x7e32000a,
-+	0xce000024, 0xc4970258, 0xc4930250, 0x51540020, 0x7d15001a, 0xc4af0280, 0xc4b30278, 0x52ec0020,
-+	0x7ef2c01a, 0x04140020, 0x04280000, 0x65180001, 0x95800060, 0x8c001628, 0xc4193247, 0x25980001,
-+	0x04200101, 0x94c00005, 0x30f00005, 0x04200005, 0x9b000002, 0x04200102, 0x95800056, 0xc439325b,
-+	0x1bb0003f, 0x97000049, 0x1bb000e8, 0x33380003, 0x9b800046, 0x33300002, 0x9700000a, 0xc4393260,
-+	0x1bb000e4, 0x33300004, 0x97000040, 0xc431325d, 0x27300010, 0x9b00fffe, 0x80001aa2, 0xcdc00013,
-+	0xc033ffff, 0x2f3000ff, 0xc439325b, 0x7f3b0009, 0xcf01325b, 0xc439325b, 0x27b800ff, 0x9b80fffe,
-+	0xd8c00033, 0xc4300009, 0x27300008, 0x9700fffe, 0x19f003e6, 0x27380003, 0x13b80004, 0x27300003,
-+	0x13300003, 0x7fb38001, 0x19f000e8, 0x7fb38001, 0x13300001, 0x7fb38001, 0x07b80002, 0xd8400013,
-+	0x19f00064, 0x33300002, 0x97000009, 0x17b00005, 0x07300003, 0xcf012082, 0xcc01203f, 0xd8400013,
-+	0xcc01203f, 0x0b300003, 0x80001a90, 0x17b00005, 0xcf012082, 0xcc01203f, 0xd8400013, 0xcc01203f,
-+	0x13300005, 0x7fb30002, 0xc4392083, 0x7fb38005, 0x27b80001, 0x9b80ffdf, 0xd8c00034, 0xcdc00013,
-+	0xc431325d, 0x27300010, 0x9b00fffe, 0xc439325b, 0x27b000ff, 0x9b00ffca, 0xce01325d, 0x2030007b,
-+	0xcf00325b, 0x80001aa3, 0xce01325d, 0x04300001, 0x7f2b0014, 0x7ef2c01a, 0xc49b02e9, 0x99800005,
-+	0xd2400025, 0x4664001c, 0xd8000026, 0xd8400027, 0x06a80001, 0x09540001, 0x55100001, 0x9940ff9c,
-+	0xc49b02e9, 0x99800008, 0xc430000e, 0x2b300008, 0xcf000013, 0x04302000, 0xcf013267, 0xc4313267,
-+	0x97000001, 0x90000000, 0x244c00ff, 0xcc4c0200, 0x7c408001, 0x88000000, 0xc44f0200, 0xc410000b,
-+	0xc414000c, 0x7d158010, 0x059cc000, 0xd8400013, 0xccdd0000, 0x7c408001, 0x88000000, 0xc40c0037,
-+	0x94c0ffff, 0xcc000049, 0xc40c003a, 0x94c0ffff, 0x7c40c001, 0x24d00001, 0x9500e69a, 0x18d0003b,
-+	0x18d40021, 0x99400006, 0xd840004a, 0xc40c003c, 0x94c0ffff, 0x14cc0001, 0x94c00028, 0xd8000033,
-+	0xc438000b, 0xc43c0009, 0x27fc0001, 0x97c0fffe, 0xd8400013, 0xd841c07f, 0xc43dc07f, 0x1bfc0078,
-+	0x7ffbc00c, 0x97c0fffd, 0x99000004, 0xc0120840, 0x282c0040, 0x80001ae8, 0xc0121841, 0x282c001a,
-+	0xcd01c07c, 0xcc01c07d, 0xcc01c08c, 0xcc01c079, 0xcc01c07e, 0x04200004, 0xcec0001b, 0xd8400021,
-+	0x0a200001, 0x9a00ffff, 0xc425c07f, 0x166c001f, 0x04200004, 0x9ac0fffb, 0xc434000f, 0x9b40ffff,
-+	0xd801c07f, 0xd8400013, 0xc425c07f, 0xce400078, 0xd8000034, 0x9940e66b, 0xd800004a, 0x7c408001,
-+	0x88000000, 0xc40c0036, 0x24d00001, 0x9900fffe, 0x18cc0021, 0xccc00047, 0xcc000046, 0xc40c0039,
-+	0x94c0ffff, 0xc40c003d, 0x98c0ffff, 0x7c40c001, 0x24d003ff, 0x18d47fea, 0x18d87ff4, 0xcd00004c,
-+	0xcd40004e, 0xcd80004d, 0xd8400013, 0xcd41c405, 0xc02a0001, 0x2aa80001, 0xce800013, 0xcd01c406,
-+	0xcc01c406, 0xcc01c406, 0xc40c0006, 0x98c0ffff, 0xc414000e, 0x29540008, 0x295c0001, 0xcd400013,
-+	0xd8c1325e, 0xcdc0001a, 0x11980002, 0x4110000c, 0xc0160800, 0x7d15000a, 0xc0164010, 0xd8400013,
-+	0xcd41c078, 0xcc01c080, 0xcc01c081, 0xcd81c082, 0xcc01c083, 0xcd01c084, 0xc40c0006, 0x98c0ffff,
-+	0xd8400048, 0xc40c003b, 0x94c0ffff, 0x80000c16, 0xd8400013, 0xd801c40a, 0xd901c40d, 0xd801c410,
-+	0xd801c40e, 0xd801c40f, 0xc40c0040, 0x04140001, 0x09540001, 0x9940ffff, 0x04140096, 0xd8400013,
-+	0xccc1c400, 0xc411c401, 0x9500fffa, 0xc424003e, 0x04d00001, 0x11100002, 0xcd01c40c, 0xc0180034,
-+	0xcd81c411, 0xd841c414, 0x0a540001, 0xcd41c412, 0x2468000f, 0xc419c416, 0x41980003, 0xc41c003f,
-+	0x7dda0001, 0x12200002, 0x10cc0002, 0xccc1c40c, 0xd901c411, 0xce41c412, 0xd8800013, 0xce292e40,
-+	0xcc412e01, 0xcc412e02, 0xcc412e03, 0xcc412e00, 0x80000aa7, 0xc43c0007, 0xdc120000, 0x31144000,
-+	0x95400005, 0xdc030000, 0xd800002a, 0xcc3c000c, 0x80001b70, 0x33f80003, 0xd4400078, 0x9780e601,
-+	0x188cfff0, 0x04e40002, 0x80001190, 0x7c408001, 0x88000000, 0xc424005e, 0x96400006, 0x90000000,
-+	0xc424005e, 0x96400003, 0x7c408001, 0x88000000, 0x80001b74, 0x80000168, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0x92100004, 0x92110501, 0x92120206, 0x92130703, 0x92100400, 0x92110105, 0x92120602, 0x92130307,
-+	0xbf810000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	},
-+	.dfy_size = 7440
-+};
-+
-+static const PWR_DFY_Section pwr_virus_section4 = {
-+	.dfy_cntl = 0x80000004,
-+	.dfy_addr_hi = 0x000000b4,
-+	.dfy_addr_lo = 0x54106500,
-+	.dfy_data = {
-+	0x7e000200, 0x7e020204, 0xc00a0505, 0x00000000, 0xbf8c007f, 0xb8900904, 0xb8911a04, 0xb8920304,
-+	0xb8930b44, 0x921c0d0c, 0x921c1c13, 0x921d0c12, 0x811c1d1c, 0x811c111c, 0x921cff1c, 0x00000400,
-+	0x921dff10, 0x00000100, 0x81181d1c, 0x7e040218, 0xe0701000, 0x80050002, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0701000, 0x80050102,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0701000, 0x80050002, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0701000, 0x80050102, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0701000, 0x80050002, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0701000, 0x80050102,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302, 0xe0501000, 0x80050302,
-+	0xbf810000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	},
-+	.dfy_size = 240
-+};
-+
-+static const PWR_DFY_Section pwr_virus_section5 = {
-+	.dfy_cntl = 0x80000004,
-+	.dfy_addr_hi = 0x000000b4,
-+	.dfy_addr_lo = 0x54106900,
-+	.dfy_data = {
-+	0x7e080200, 0x7e100204, 0xbefc00ff, 0x00010000, 0x24200087, 0x262200ff, 0x000001f0, 0x20222282,
-+	0x28182111, 0xd81a0000, 0x0000040c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000,
-+	0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000,
-+	0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000,
-+	0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000,
-+	0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000, 0x0000040c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd81a0000,
-+	0x0000080c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000, 0x1100000c, 0xd86c0000,
-+	0x1100000c, 0xbf810000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	},
-+	.dfy_size = 384
-+};
-+
-+static const PWR_DFY_Section pwr_virus_section6 = {
-+	.dfy_cntl = 0x80000004,
-+	.dfy_addr_hi = 0x000000b4,
-+	.dfy_addr_lo = 0x54116f00,
-+	.dfy_data = {
-+	0xc0310800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000040, 0x00000001, 0x00000001, 0x00000001, 0x00000000, 0xb4540fe8, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000041, 0x0000000c, 0x00000000, 0x07808000, 0xffffffff,
-+	0xffffffff, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555, 0x55555555,
-+	0x55555555, 0x00000000, 0x00000000, 0x540fee40, 0x000000b4, 0x00000010, 0x00000001, 0x00000004,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x54116f00, 0x000000b4, 0x00000000, 0x00000000, 0x00005301, 0x00000000, 0x00000000, 0x00000000,
-+	0xb4540fef, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x540fee20, 0x000000b4, 0x00000000,
-+	0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0xc0310800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000040, 0x00000001, 0x00000001, 0x00000001, 0x00000000, 0xb454105e, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x000000c0, 0x00000010, 0x00000000, 0x07808000, 0xffffffff,
-+	0xffffffff, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555, 0x55555555,
-+	0x55555555, 0x00000000, 0x00000000, 0x540fee40, 0x000000b4, 0x00000010, 0x00000001, 0x00000004,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x54117300, 0x000000b4, 0x00000000, 0x00000000, 0x00005301, 0x00000000, 0x00000000, 0x00000000,
-+	0xb4540fef, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x540fee20, 0x000000b4, 0x00000000,
-+	0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0xc0310800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000040, 0x00000001, 0x00000001, 0x00000001, 0x00000000, 0xb4541065, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000500, 0x0000001c, 0x00000000, 0x07808000, 0xffffffff,
-+	0xffffffff, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555, 0x55555555,
-+	0x55555555, 0x00000000, 0x00000000, 0x540fee40, 0x000000b4, 0x00000010, 0x00000001, 0x00000004,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x54117700, 0x000000b4, 0x00000000, 0x00000000, 0x00005301, 0x00000000, 0x00000000, 0x00000000,
-+	0xb4540fef, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x540fee20, 0x000000b4, 0x00000000,
-+	0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0xc0310800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000040, 0x00000001, 0x00000001, 0x00000001, 0x00000000, 0xb4541069, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000444, 0x0000008a, 0x00000000, 0x07808000, 0xffffffff,
-+	0xffffffff, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0x55555555, 0x55555555, 0x55555555,
-+	0x55555555, 0x00000000, 0x00000000, 0x540fee40, 0x000000b4, 0x00000010, 0x00000001, 0x00000004,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x54117b00, 0x000000b4, 0x00000000, 0x00000000, 0x00005301, 0x00000000, 0x00000000, 0x00000000,
-+	0xb4540fef, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x540fee20, 0x000000b4, 0x00000000,
-+	0x00000000, 0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-+	},
-+	.dfy_size = 1024
-+};
- 
--static const PWR_Command_Table pwr_virus_table[PWR_VIRUS_TABLE_SIZE] = {
--	{ PwrCmdWrite, 0x00000000, mmRLC_CNTL                                 },
--	{ PwrCmdWrite, 0x00000002, mmRLC_SRM_CNTL                             },
--	{ PwrCmdWrite, 0x15000000, mmCP_ME_CNTL                               },
--	{ PwrCmdWrite, 0x50000000, mmCP_MEC_CNTL                              },
--	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
--	{ PwrCmdWrite, 0x0840800a, mmCP_RB0_CNTL                              },
--	{ PwrCmdWrite, 0xf30fff0f, mmTCC_CTRL                                 },
--	{ PwrCmdWrite, 0x00000002, mmTCC_EXE_DISABLE                          },
--	{ PwrCmdWrite, 0x000000ff, mmTCP_ADDR_CONFIG                          },
--	{ PwrCmdWrite, 0x540ff000, mmCP_CPC_IC_BASE_LO                        },
--	{ PwrCmdWrite, 0x000000b4, mmCP_CPC_IC_BASE_HI                        },
--	{ PwrCmdWrite, 0x00010000, mmCP_HYP_MEC1_UCODE_ADDR                   },
--	{ PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00221408, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00591260, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00621387, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC1_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00010000, mmCP_HYP_MEC2_UCODE_ADDR                   },
--	{ PwrCmdWrite, 0x00041b75, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000710e8, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000910dd, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000a1081, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000b016f, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000c0e3c, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000d10ec, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000e0188, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00101b5d, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00150a6c, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00170c5e, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x001d0c8c, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x001e0cfe, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00221408, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00370d7b, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00390dcb, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x003c142f, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x003f0b27, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00400e63, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00500f62, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00460fa7, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00490fa7, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x005811d4, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00680ad6, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00760b00, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00780b0c, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00790af7, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x007d1aba, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x007e1abe, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00591260, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x005a12fb, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00861ac7, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x008c1b01, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x008d1b34, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a014b9, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a1152e, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a216fb, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a41890, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a31906, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00a50b14, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00621387, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x005c0b27, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x00160a75, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x000f016a, mmCP_HYP_MEC2_UCODE_DATA                   },
--	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
--	{ PwrCmdWrite, 0x540fe800, mmCP_DFY_ADDR_LO                           },
--	{ PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e020201, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e040204, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e060205, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a080500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a0a0303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54106f00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000400b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00004000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00804fac, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
--	{ PwrCmdWrite, 0x540fef00, mmCP_DFY_ADDR_LO                           },
--	{ PwrCmdWrite, 0xc0031502, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00001e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
--	{ PwrCmdWrite, 0x540ff000, mmCP_DFY_ADDR_LO                           },
--	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000145, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4080061, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24ccffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3cd08000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9500fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1cd0ffcf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d018001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x050c0019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x84c00000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000067, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000006a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000006d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000008f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000099, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800000a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800000af, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x388c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08880002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98800003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000002d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d808001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc0700, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10cc0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d0d000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000005d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14d00011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c01b10, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00e0080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00e0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x280c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x280c0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400053, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x280c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00052, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28180039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28080001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca88004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc00006f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28180080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d10c017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000013b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd4c0380, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdcc0388, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55dc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdcc038c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce0c0390, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce0c0394, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce4c0398, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce4c039c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce8c03a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56a80020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce8c03a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcecc03a8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcecc03ac, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf0c03b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57300020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf0c03b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4c03b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57740020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4c03bc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf8c03c0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57b80020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf8c03c4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfcc03c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57fc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfcc03cc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05dc002f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc12009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d200a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc012009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25e01c00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25e40300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25e800c0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25ec003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e25c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31100006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9500007b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4df0388, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d7038c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d5dc01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4e30390, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d70394, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d62001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4e70398, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d7039c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d66401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4eb03a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d703a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d6a801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4ef03a8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d703ac, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d6ec01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4f303b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d703b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d73001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4f703b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d703bc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d77401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4fb03c0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d703c4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d7b801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4ff03c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d703cc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d7fc01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4d70380, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc0e0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0085, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc006a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc01e3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3cd00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4080001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1c88001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc080000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400051, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04180018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aac0027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04080002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080228, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000367, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9880fff3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04080010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08880001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80c0309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80c0319, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9880fffc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00e0100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d0003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d4001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x155c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05e80180, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000031, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900091a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05280196, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d4fe04, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800001b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000032b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000350, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000352, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000035f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000701, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000047c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000019f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d98001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4140004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000043, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00050, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0044, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9400036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40005b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40005d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840006d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11540015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1998003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af0007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15dc000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d65400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a38003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd5c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7df1c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800045, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411326a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc415326b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425326e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293279, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000056, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800058, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00059, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x259c8000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce40005a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29988000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000073, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17300019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25140fff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4153279, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd00005f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26f00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15100010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af07fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc031, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04343000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf413267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd1c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0160, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc810001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b4c0057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f4f400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55180020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af4007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33740003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26d80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ae8003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413348, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253348, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x958000d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000315, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04303000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26680001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800041, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1714000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25540800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x459801b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d77400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x199c01e2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e5c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000282, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc80c0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1334e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01334f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd413350, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813351, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd881334d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193273, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3275, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4153274, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cdcc011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05900008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd00006a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0006b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d594002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54d00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc12e23, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd012e24, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc12e25, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15540002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b340057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b280213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980198, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x20cc003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd430000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc01e0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29dc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2d540002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x078c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001239, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04f80000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd5c005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840007c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400069, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c018a6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4412e22, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800007c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c018a2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd4c005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680fffc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800002e3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000069, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013275, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9540188f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc013cfff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc13249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x38d00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdcc30000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c01882, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000304, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x49980198, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55e40020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x459801a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000329, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16ec001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1998003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00031, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce00000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a18003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24dc00ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31e00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580fff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95801827, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840002f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14dc0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800006d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a0000ad, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04080000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af4003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740004d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4080060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca88005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24880001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f4b4009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400046, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313274, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d33400c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1eecffdd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013273, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013275, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800003c3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429326f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aa80030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28240001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a8004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3272, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19e80042, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e8e800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de9c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3271, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50cc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ce8c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd30011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11e80007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd300001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b30003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240059, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1660001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e320009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0328000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e72400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0430000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02ac000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d310002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa87600, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280222, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4280058, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x22ec003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013273, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce813275, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800007b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8380018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57b00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04343108, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2374007e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32a80003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800003e7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980104, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x49980104, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800003f2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813279, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf41326e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x254c0700, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a641fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0726, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a640200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1237b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8813260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4280034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce40000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c01755, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce80000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde830000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce80000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0174c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bb80040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100044, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19180024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x551c003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000043d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00c8000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840006c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28200000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000043f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00c4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x282000f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000053, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x195c00e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32200002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc5e124dc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e624001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2555fff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980158, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x49980158, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980170, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16200010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d43c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x195400e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1154000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc00e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05e80488, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18f807f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e40077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18ec0199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000048e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000494, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800004de, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000685, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000686, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800006ac, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ccc001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1264000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d79400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e7a400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52a8001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aec0028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d325c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800004cc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419324e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26e8003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d324d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d290004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f8f4001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f52800f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50e00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800004d1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d0dc002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5e401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f534002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x6665fc00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800004d7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aec003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3257, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12f4000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d75401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52200002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da1c011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a644000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x202c003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x259c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05e804e3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800004e7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800004f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000505, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640fff4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26edf000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05a80507, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000050c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000528, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000057d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800005c2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800005f3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1be00fe4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000066, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400068, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c004d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00063b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801326f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000624, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bd400e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ed6c005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113271, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4153270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193272, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3273, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d51401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113274, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213275, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253276, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400061, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2730000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7db1800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00062, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000063, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400065, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b700057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b680213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46ec0188, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17e00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26e01000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c131fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x192007ec, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x69dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de20014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x561c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013344, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13345, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800068, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2010007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9500fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd00001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2010003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x191807e4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9540000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2511fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013344, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013345, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180050, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0052, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280042, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813273, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13275, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce813260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000068, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400067, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07d40000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00124f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x057c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46ec0190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4153249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2154003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bd800e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420004d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd413249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01326f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f598004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1be800e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce80005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801327a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800005f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000075, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424004c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41326e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28240100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a4004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc435325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x277401ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf41325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xda000068, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113277, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9540002d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425334d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419334e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d334f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213350, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253351, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b680057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b700213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b740199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46ec01b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc1334a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1be000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0360001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc63124dc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef6c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80fff9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02ee000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fc14001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000697, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25100007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31100005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900008e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x202c007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a9feff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d30b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce813265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00ac006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00e0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28880700, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0006de, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14cc0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30d4000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10cc0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41530b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19980028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800006c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8380023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fa38011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd3800025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x202400d0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28240006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81a2a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x194c00e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc0005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c004c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27301fff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce00005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cf0c00d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000712, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x194c1c03, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc0003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c002d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05e80714, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000071c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000720, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000747, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000071d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800007c4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000732, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000745, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000744, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a64008c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b301fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000075e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c0fff1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000723, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41f02f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000743, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c0ffde, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000072e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0007e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd84131db, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b301ff8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8413260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc8000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x195800e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd80005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418004c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81326e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dd7fff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1a001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46200200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04283247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af80057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af40213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6f400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc6990000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x329c325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x329c3269, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x329c3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc01defff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d8009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000078a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25980000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fff2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03e7ff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3f0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03e4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d30b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bf0003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000b80, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x203c003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300700, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf0130b7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46200008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2000025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4080007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x259c0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31dc0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18ec0057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e40213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc0199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cecc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ce4c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000448, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31980002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19580066, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15600008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0120001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11980003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da18001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d24db, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd9c005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fff8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580137b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00ee000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113269, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19080070, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x190c00e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2510003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2518000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05a80809, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000080e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000080f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000898, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000946, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800009e1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04a80811, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000815, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000834, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3045, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1c091, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000241, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02f0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4252087, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5668001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a80005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000084a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31300021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd84002f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293059, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56a8001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00021d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001a41, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43b02f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec80278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56f00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8813247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000085e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31100011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x950001fa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02e0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aec0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc01c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11a40006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de6000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10e40008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e2e000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d10ffdf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2110003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d10ff9e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0245301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801325f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0121fff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29108eff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0127ff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0131fff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e524009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801326e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013279, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0100010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd2400c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0180003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd1c002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000866, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04a8089a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000089e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800008fa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000945, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31300022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x964012a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02620c0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01c082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0260400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800008d2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000903, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31240022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ec30011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32f80000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x67180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bfc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd981325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000915, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c1325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0fff6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f818001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001606, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d838001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16240014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a2801f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00075e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0228, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1330000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13f40014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07fc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33e80010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680ffec, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04a80948, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000094c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000099b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800009e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x459801e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2738000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8300011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8340011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc79d3300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc7a13301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8393300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0260001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce793301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x964011fe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c028009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce40001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x242c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0260010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01c080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57240020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0260800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6e400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae8001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2f0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000978, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdf93300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce393301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dda801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e838011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001802, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x469c0390, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4280011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0014df, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31280014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce8802ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800062, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31280034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04a809e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800009ec, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a45, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a59, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d91801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e72401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b342010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x172c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b30c012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef7400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x66740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400041, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04383000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4393267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b38007e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x4598001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740002f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4002eb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4002ec, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4002ed, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4002ee, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd84802e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001715, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04382000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffbc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04341001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431ecaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a55, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x233c0032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf0130b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49302ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5198001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193269, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2598000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80002f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53b8001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7db9801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000a5e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c01106, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c010fd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ce4c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc80c0072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x58e801fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc01e2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5e4002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e5c0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e540002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9540000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8180011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x44cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55900020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4140011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x44cc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd812e01, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd012e02, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd412e03, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2264003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4140028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1e64001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14d00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ab1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a0010ac, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd880003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c0003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d403f7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41b0367, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d85800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d001fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05280adc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000af1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000adf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ae7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd8d2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d803f7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc010ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d0cc009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11940014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29544001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29544003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000af4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd44d2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd44dc000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d0003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000ace, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd8d2c00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000b0a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd44d2c00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28148004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d800ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4593240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0105e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef3400c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14e80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a8000af, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c01043, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18a01fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3620005c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2464003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc6290ce7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16ac001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ac003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ee6c00d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00fff8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000367, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640102e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x199c0037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19a00035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0005d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16f8001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9780000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc035f0ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e764009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19b401f8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13740008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x199c0034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ae4003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000b7c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19a4003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc01e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13fc0018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dbd800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d98ff15, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x592c00fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd80000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12e00016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x592c007e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12e00015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11a0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1264001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1620000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12e4001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5924007e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19a4003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013257, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd413258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00fdb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9780f5ca, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001b6d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07740003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x269c003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5e4004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f67000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f674002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ab8c006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000bec, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000b47, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03a8004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc415325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18580037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x262001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d54001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd280200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd680208, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcda80210, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b400014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a80004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc6930200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc6970208, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc69b0210, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd900003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd940003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9400040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14fc0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24f800ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd88130b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d83c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4093249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1888003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000671, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419324c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x259c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1598001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14d80011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24e000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x321c0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580ffee, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c30, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9480000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800f29, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800f23, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800f1a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9600f502, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c0f500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000f05, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1f30001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16e4001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640f4f4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc434000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33740002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40f4f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aec003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12ec001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1374000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02e4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1774000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12780001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bb80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00ac005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00e0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc8000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28884900, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ff3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400ee1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c40a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c40c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c40d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d0007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15580010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x255400ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01c411, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81c40f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41c40e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c410, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e80033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18ec0034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c414, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c415, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81c413, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc0032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c030011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c038011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431c417, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc435c416, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439c419, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc418, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf413261, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013262, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13263, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813264, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc0030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d77000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51b80020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53300020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f97801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3b000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000cd6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ca7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc0031, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc435c40b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4280032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000cf4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc032800b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d42011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17fc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800e6c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x596001fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ce0c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x505c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc0001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5e800c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x122c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000d1f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8240010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x566c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce413261, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec13262, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f8cc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000d57, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb81fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0328009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04143000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e51001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d2d0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19640057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19580213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19600199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da6400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1000025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04142000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd413267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4153267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d80034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05280d83, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000d8a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000db1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000d95, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000dbc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e010001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d75400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580f3d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x526c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e2ec01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5ae0073a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580f3c6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc3a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80fffb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980fff5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16200002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01c405, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd441c406, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580f3b1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11540010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4610000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580f3a5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00da7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5aac007e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12d80017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56a00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da1800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e82400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e58c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19d4003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x20880188, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x20240090, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28240004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd901a2a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841325f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ac0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ac0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b301ff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2330003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0001a2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1910003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2220003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e2a000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c00038, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d40030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18fc0034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24e8000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80e71, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000edd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000e91, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ea1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000eaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000e7c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000e7f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000e87, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000e8f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9e001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213262, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253261, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a200008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213264, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253263, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc820001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e82005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51e00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da1801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1800072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8180072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x59a001fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea2800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce80001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd180001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81c400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421c401, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400041, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425c401, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ee6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ede, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db09001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db09011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ebc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc5a10000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc5a50000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05280eea, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f11, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f2e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000efe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f1f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0f26f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e80058, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7daec01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5af8073a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eba800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0f25c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15980002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81c405, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01c406, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56240020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c406, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0f24e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439c409, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40f247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce190000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0f240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439c040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac2580, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac260c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac0828, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac2440, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac2390, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac0093, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac31dc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31ac31e6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ef2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39ac7c06, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db07c00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39acc337, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db0c330, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39acc335, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db0c336, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39acec70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db0ec6f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39ac9002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db09002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39ac9012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3db09012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ef1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc434000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b740008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b780001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c034001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c038001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01c080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41c081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f88, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e52401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce81c080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01c081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1334000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24e02000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f63400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32240003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc1c083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000f9d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51e40020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5a401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2400072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8280072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce81c082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56ac0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26f0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1af000fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13380016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e00039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e0007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1220001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e00074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fa3800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81c078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1c084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d001e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31140005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31140006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05280fb7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28140002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000fc2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000fbe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000fd1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ff2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e80039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52a8003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d69401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140004b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d958004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d150005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9500000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x159c0011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x259800ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31a00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31a40001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e25800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0fff5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580fff4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000fef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411326f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d100010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01326f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc011000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33b40003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0340008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000ffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c908009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x282c2002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x208801a8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000102f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1cccfe08, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1a2a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00b33, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da2400f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da28002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1ac002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d2ac002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3ef40010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40f11d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde410000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdcc10000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd010000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd410000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdd810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xddc10000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde010000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c024001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100086, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5510003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001075, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15800f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15c002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d520002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cde0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e20001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001071, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c00036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00b01, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc200000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc1c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc180000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc0c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc240000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc40003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4080029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18a400e5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12500009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x248c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x200c006d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x200c0228, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410002b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18881fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d4072c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc00d1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd4c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3094000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x38d80000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x311c0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30940007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1620001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800010c4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00041, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25140001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x259c007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19a00030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x199c0fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800010cb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000aac, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07a810d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000104c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x200c007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28240007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xde430000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d3249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x192400fd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06681110, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19180070, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19100078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18f40058, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001117, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001118, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000112d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001130, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001133, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24ec0f00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32ec0600, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000117b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc81c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc81c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55e00020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001122, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02a0200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e8e8009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x22a8003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x22a80074, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2774001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13740014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eb6800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25ecffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55700020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15f40010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13740002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x275c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15dc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39e00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dc1c01e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05e40008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e62000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001165, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dc2001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1a0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e0d000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95000007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e02401e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06640008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05d80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dc2401e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da58001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05e00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da2000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9600ffe6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00116e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00116b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce00001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce81c078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1c080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41c082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01c083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x22640435, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0528117e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x312c0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001185, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001182, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03a0400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d81c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc130b7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0049, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19a000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de2c00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc420007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce40003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800011a3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d654001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c020001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4140025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800011b6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253279, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc415326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2730003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3b380006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3f38000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800011b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0430000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb10004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e57000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e578002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d67c002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0be40001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d3a4002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x202c002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26200010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e640010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce81325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc434002e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17780001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07a811cf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00feb8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x954009a7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000bfc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1c07c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c07d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c08c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01c07e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18f0012f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18f40612, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc00c1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cf7400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x39600004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0140004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18fc003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9740001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400041, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800011ee, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a6c003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800011e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ac007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ab00030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aac0fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001205, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11600001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03a2800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03a0800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03ae000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81c200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03a4000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81c07c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17fc001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30d00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000052, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640090f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19180038, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d324e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431324d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ab0c006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000127f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d3258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313257, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ab0c012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a0003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f67800f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53740002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef6c011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ab42010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16a8000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a80800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b740000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f6b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf40001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1514001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0012e1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x964008d7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9800036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300677, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012aa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b34060b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f37000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec00ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03a8002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef6c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7edec00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3b000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4140032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1858003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d0cc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d0006c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d407f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2598003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d190004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d5d4001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d52000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d514002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d958001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd5c002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc1325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1ccc001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14f00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd980003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c0003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9800040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd9c00040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800010de, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800051, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc80003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24b00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18a800e5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1d980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7da9800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b74003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b304000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431326c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50700020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04e81324, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18ac0024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50600020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d71401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x596401fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b74008d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e76400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a640000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000132c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000133b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001344, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42530b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a68003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2024003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25980700, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11980014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d19000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd0130b7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce4130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffea, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce40001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc428000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8240011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de6800f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffe0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00104f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28182002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340035, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140023, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11a00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d614011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4100026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05980008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca4800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d1a0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cb0800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3e280008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cb4800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x20240030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ca48001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b4c00f8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28340000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x507c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30e40004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d7d401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x557c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28342002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c018001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf81a2a4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c007eb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d0d001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8100072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x591c01fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45140210, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x595801fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11980009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29dc0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1624001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400069, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a307fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x23304076, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc00e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10cc0015, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x4514020c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a2001e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a204001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a64003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1264001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15dc000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dcdc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5dc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340022, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4412e01, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0434001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf430000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4412e40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c030, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41c031, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x248dfffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc12e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc812e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45140248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013257, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0434000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdb000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd140001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9980ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8200011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013259, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0337fff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f220009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55300020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d01c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c01d0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f01c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c01c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c000d61, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50500020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd0c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd0c00072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8240072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd240001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19682011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5a6c01fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eeac00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4180011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfa0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4380007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d40038, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400029, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9540073d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18c80066, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30880001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x4220000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24e80007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24ec0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc5310000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001465, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1000072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc82c0072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2c0001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18f02011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5aec01fc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12ec0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aec0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0aa80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a8146a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f1f0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001478, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f1b400c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f1b400d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f1b400f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f1b400e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000147a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f334002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000147b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b400012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e024001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000144a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fbfc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x251001ef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94800007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00187c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42c0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd910000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40d325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800012c2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13f4000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bf0060b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800014a9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d325a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0677, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb81ff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0328007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb7800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13fc0017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ffbc00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03a0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf8130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd9c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45dc0390, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04183000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c424001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c428001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c430001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c434001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04182000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd813267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a0800fd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x109c000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce080228, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9880000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0ec75, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce480250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce880258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52a80020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x66580001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc80260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec80288, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf080290, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec80298, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf0802a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4802a8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27580001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0fffb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc802b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80802b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x178c000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b8003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cf8c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf8802c0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc802c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf8802d0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf8802d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25b8ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd2800c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc5230309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2620ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e3a400c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001539, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd880353, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49b0353, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0228, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd14005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000154f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd080238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd08034b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3d200008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd900309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2198003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd910ce7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4190ce6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d918005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d918004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd810ce6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdd1054f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000156e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x090c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdcd050e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x040c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x110c0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc4001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41230a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41230b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41230c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc41230d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc480329, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc48032a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc4802e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d8003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09940001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x44100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x69100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000157f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4970290, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49b0288, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49b02a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49f0298, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x041c0040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dcdc002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d924019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d26400c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001579, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d010021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d914019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd480298, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd8802a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10d40010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12180016, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc51f0309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d95800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d62000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd9c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdd00309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce113320, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f02e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49b02b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18dc01e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd9400e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c0001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800015aa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4a302b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12240004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e5e400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4ab02a8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04100000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce4c0319, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d9d8002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea14005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800015bc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04240001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e624004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d25000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2620000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0fff4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd0d3330, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce0802b8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd8802b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4ab02e0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aa807f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f02d0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49702d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49b02c8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49f02c0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96800028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d4e000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9600000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d964002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cde4002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de94001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd64002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d694001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800015e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00163f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800015cd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930238, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d698002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd4802d8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x129c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc50f0319, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11a0000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11140001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1e000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1198000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd953300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e0e000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a8000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce953301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce100319, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b70280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73800a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x536c0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9780eb68, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001609, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30b40000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b400011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b70258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53780020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb3801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7faf8019, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x67b40001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x57b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4bb0260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fab8001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf880260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x66f40001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97400005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4353247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f7f4009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fff7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x269c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a00018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a00060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x269c0018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a40060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11dc0006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29dc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de5c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b70228, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc80230, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f514005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2510000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001644, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd080240, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f130005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001688, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00120d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001219, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001232, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340801, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f130004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01051e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42d051f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ed2c005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96c0fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01051f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000055, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc5170309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x195c07f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x196007f6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04340001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x6b740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001665, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4a702a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4ab0298, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f634014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e76401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8113320, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce480298, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce8802a0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc5170319, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b702b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x255c000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f5f4001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8113330, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf4802b0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11340001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x195c07e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x196007ee, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8353300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1e4001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8353301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce4802d0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8100309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8100319, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc48f0250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd4c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x64d80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580005c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd2000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc435324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7df5c00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25980040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800016f1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a7003e6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a700064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800016df, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800016f2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd80802e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18fc0064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00042, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51980020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dd9801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x45980400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b380057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b340213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f7b400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f73400a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4bf0258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4a70250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53fc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e7e401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x667c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0aec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eebc00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fff8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x43300007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7db30011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd3000025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc03ec005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfca200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x192807fa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x203c003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0017f5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18fc01e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00185b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40ffd5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0ea24, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14d4001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d52400e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49f0258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4a30250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51dc0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400017, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d534002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dae4005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000174f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b740001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00178a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40fff3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001608, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4ab0268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7daa4005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32a0001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001765, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d1d0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2110007d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8013256, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c0017f2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd013254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4113248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b3034b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f13000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001855, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32a4001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8413247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800004f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd080260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce880268, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940ffc0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ec28001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32e0001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253255, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431324f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e72400c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a80040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9680fff7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aa4003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400049, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aa400e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32680003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a800046, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4293260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1aa400e4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800017e2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc027ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2e6400ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a4009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a800ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4240009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19e403e6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26680003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12a80004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19e400e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea68001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19e40064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x32640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06640003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a640003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800017d0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16a40005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce412082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea64002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4292083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ea68005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a80ffdf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc429325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26a400ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40ffca, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2024007b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800017e3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4a70280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4ab0278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52640020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7eae8014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e6a401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56680020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce480278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce880280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x042c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec80270, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800017fe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43b02eb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42302ec, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fa3801a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x47b8020c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x15e00008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1220000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2a206032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x513c001e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e3e001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4bf02e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000180f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b3c0077, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1330000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd200000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4200007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd3800002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dc30001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc1e0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04380032, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf80000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001427, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc413248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3269, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33fc0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bfc0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd441326a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x173c0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300303, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3f0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ff3c004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001842, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdfc30000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4413249, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c43c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x23fc003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1326d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bb80026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdf830000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd441326e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c438001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4393265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1fb8ffc6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xddc30000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf813265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001852, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c00142b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49f02e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c00018, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c420001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c3000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c0012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001878, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41f02ed, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42302ee, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc13252, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013253, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e2a0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28340001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x313c0bcc, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x393c051f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3d3c050e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x393c0560, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3d3c054f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x393c1538, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3d3c1537, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b740800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e8007c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c42c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a8189a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800018c5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800018f2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c414001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d0007e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x50580020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d59401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc8140072, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09240002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c418001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4340004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc42130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a24002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2020002c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc418000d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1198001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10cc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14cc0004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7cd8c00a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc130b7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce0130b5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd1400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x5978073a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bb80002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf800024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd800026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9600e8a8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9640e8a5, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800018a9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dad800c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0ffd2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580fff9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x442c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940fff1, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x66d80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x56ec0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26240007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940fff7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc023007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19e4003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7de1c009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dee000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96000007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c13260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd901325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc421325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x261c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940fff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000189e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28cc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43d3265, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bc800ea, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18e00064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06281911, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14f4001d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24cc0003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x86800000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001915, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x800019af, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001a2b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8000016a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc48032b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc480333, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc48033b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc480343, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98800011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b3c0057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e3e000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04180000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f438001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00068, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213254, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a1c003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00065, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc01f007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1e0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97800062, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0bb80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x43bc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fcbc001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc7df032b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1fc00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0101, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c0102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001994, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001982, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffcb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001995, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc1325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98800009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x41bc0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x53fc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e7fc011, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd3c00025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0012, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9bc0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x653c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dbd8001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940ff8f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2bfc0008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x043c2000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcfc13267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c410001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc55b0309, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x3d5c0010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2598ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x05540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d91800c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580fff8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09780001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9580005d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400058, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dc24001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41d3248, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25dc000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7df9c00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95c00053, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e41c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a70003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a7000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33240003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a400046, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1a7000e4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001a21, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f270009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x266400ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27240003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12640004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e724001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06640002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001a0f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x16700005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e730002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4252083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e724005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x26640001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a40ffdf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x267000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001a22, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940ff9f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001a31, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8080280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213246, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4253245, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52200020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e26401a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x46640400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04203000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce013267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4213267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b180057, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b200213, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1b300199, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e1a000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e32000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce000024, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4970258, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4930250, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x51540020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4af0280, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4b30278, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x52ec0020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140020, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04280000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x65180001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800060, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x8c001628, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4193247, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x25980001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200101, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x30f00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95800056, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb0003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000049, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33380003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b800046, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4393260, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bb000e4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001aa2, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc033ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2f3000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f3b0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf01325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b800ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4300009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9700fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f003e6, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27380003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13b80004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f000e8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07b80002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x19f00064, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33300002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0b300003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001a90, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x17b00005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf012082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01203f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x13300005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb30002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4392083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7fb38005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b80ffdf, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c00034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc00013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc431325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27300010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc439325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27b000ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b00ffca, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2030007b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf00325b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001aa3, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce01325d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04300001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7f2b0014, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ef2c01a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd2400025, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x4664001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000026, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400027, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x06a80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55100001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940ff9c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc49b02e9, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99800008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc430000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2b300008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf000013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04302000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcf013267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc4313267, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x244c00ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc4c0200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc44f0200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc410000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d158010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x059cc000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccdd0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0037, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000049, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c003a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9500e69a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d0003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d40021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd840004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c003c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x14cc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c00028, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000033, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc438000b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0009, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x27fc0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43dc07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1bfc0078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7ffbc00c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x97c0fffd, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x99000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0120840, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x282c0040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001ae8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0121841, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x282c001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01c07c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c08c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c079, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c07e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcec0001b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a200001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9a00ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x166c001f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04200004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9ac0fffb, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc434000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9b40ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc425c07f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8000034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940e66b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800004a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0036, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9900fffe, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18cc0021, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc00047, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc000046, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0039, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c003d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c40c001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24d003ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d47fea, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x18d87ff4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd00004c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd40004e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd80004d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41c405, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc02a0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2aa80001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01c406, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c406, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc414000e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x29540008, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x295c0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8c1325e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcdc0001a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11980002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x4110000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0160800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7d15000a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0164010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41c078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c080, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c081, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81c082, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc01c083, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01c084, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x98c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400048, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c003b, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x94c0ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000c16, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801c40a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd901c40d, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801c410, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801c40e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd801c40f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc40c0040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x09540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9940ffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04140096, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8400013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1c400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc411c401, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9500fffa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424003e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04d00001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x11100002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd01c40c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0180034, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd81c411, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd841c414, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0a540001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcd41c412, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x2468000f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc419c416, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x41980003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc41c003f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7dda0001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x12200002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x10cc0002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xccc1c40c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd901c411, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce41c412, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd8800013, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xce292e40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e01, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e02, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e03, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc412e00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000aa7, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc43c0007, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc120000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x31144000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x95400005, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xdc030000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd800002a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xcc3c000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b70, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x33f80003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd4400078, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x9780e601, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x188cfff0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x04e40002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001190, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400006, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x90000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc424005e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x96400003, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7c408001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x88000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80001b74, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000168, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110501, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120206, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130703, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92100400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92110105, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92120602, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x92130307, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
--	{ PwrCmdWrite, 0x54106500, mmCP_DFY_ADDR_LO                           },
--	{ PwrCmdWrite, 0x7e000200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e020204, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc00a0505, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xbf8c007f, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb8900904, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb8911a04, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb8920304, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb8930b44, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x921c0d0c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x921c1c13, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x921d0c12, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x811c1d1c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x811c111c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x921cff1c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000400, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x921dff10, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000100, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x81181d1c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e040218, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0701000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050102, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xe0501000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80050302, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
--	{ PwrCmdWrite, 0x54106900, mmCP_DFY_ADDR_LO                           },
--	{ PwrCmdWrite, 0x7e080200, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x7e100204, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xbefc00ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00010000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x24200087, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x262200ff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000001f0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x20222282, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x28182111, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000040c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd81a0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000080c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xd86c0000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x1100000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xbf810000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x80000004, mmCP_DFY_CNTL                              },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_ADDR_HI                           },
--	{ PwrCmdWrite, 0x54116f00, mmCP_DFY_ADDR_LO                           },
--	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb4540fe8, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000041, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000000c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54116f00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb454105e, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000c0, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54117300, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb4541065, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000500, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000001c, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54117700, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xc0310800, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000040, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb4541069, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000444, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x0000008a, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x07808000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xffffffff, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000002, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xaaaaaaaa, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x55555555, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee40, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000010, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000001, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000004, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x54117b00, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00005301, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x540fee20, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x000000b4, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x08000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_DFY_DATA_0                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL                              },
--	{ PwrCmdWrite, 0x00000000, mmCP_MEC_CNTL                              },
--	{ PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x54116f00, mmCP_MQD_BASE_ADDR                         },
--	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
--	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
--	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
--	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
--	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
--	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
--	{ PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x54117300, mmCP_MQD_BASE_ADDR                         },
--	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
--	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
--	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
--	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
--	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
--	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
--	{ PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x54117700, mmCP_MQD_BASE_ADDR                         },
--	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
--	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
--	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
--	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
--	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
--	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
--	{ PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x54117b00, mmCP_MQD_BASE_ADDR                         },
--	{ PwrCmdWrite, 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
--	{ PwrCmdWrite, 0xb4540fef, mmCP_HQD_PQ_BASE                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
--	{ PwrCmdWrite, 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
--	{ PwrCmdWrite, 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
--	{ PwrCmdWrite, 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
--	{ PwrCmdWrite, 0x00010000, mmCP_HQD_VMID                              },
--	{ PwrCmdWrite, 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
--	{ PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000104, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000204, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000304, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000404, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000504, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000604, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000704, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000005, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000105, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000205, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000305, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000405, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000505, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000605, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000705, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000006, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000106, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000206, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000306, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000406, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000506, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000606, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000706, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000007, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000107, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000207, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000307, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000407, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000507, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000607, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000707, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000008, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000108, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000208, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000308, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000408, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000508, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000608, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000708, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000009, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000109, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000209, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000309, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000409, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000509, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000609, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000709, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_RPTR                           },
--	{ PwrCmdWrite, 0x00000000, mmCP_HQD_PQ_WPTR                           },
--	{ PwrCmdWrite, 0x00000001, mmCP_HQD_ACTIVE                            },
--	{ PwrCmdWrite, 0x00000004, mmSRBM_GFX_CNTL                            },
--	{ PwrCmdWrite, 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1                    },
--	{ PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
--	{ PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
--	{ PwrCmdWrite, 0x00000000, mmGRBM_STATUS                              },
--	{ PwrCmdEnd,   0x00000000, 0x00000000                                 },
-+static const PWR_Command_Table pwr_virus_table_post[] = {
-+	{ 0x00000000, mmCP_MEC_CNTL                              },
-+	{ 0x00000000, mmCP_MEC_CNTL                              },
-+	{ 0x00000004, mmSRBM_GFX_CNTL                            },
-+	{ 0x54116f00, mmCP_MQD_BASE_ADDR                         },
-+	{ 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+	{ 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+	{ 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+	{ 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+	{ 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+	{ 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+	{ 0x00010000, mmCP_HQD_VMID                              },
-+	{ 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+	{ 0x00000005, mmSRBM_GFX_CNTL                            },
-+	{ 0x54117300, mmCP_MQD_BASE_ADDR                         },
-+	{ 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+	{ 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+	{ 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+	{ 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+	{ 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+	{ 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+	{ 0x00010000, mmCP_HQD_VMID                              },
-+	{ 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+	{ 0x00000006, mmSRBM_GFX_CNTL                            },
-+	{ 0x54117700, mmCP_MQD_BASE_ADDR                         },
-+	{ 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+	{ 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+	{ 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+	{ 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+	{ 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+	{ 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+	{ 0x00010000, mmCP_HQD_VMID                              },
-+	{ 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+	{ 0x00000007, mmSRBM_GFX_CNTL                            },
-+	{ 0x54117b00, mmCP_MQD_BASE_ADDR                         },
-+	{ 0x000000b4, mmCP_MQD_BASE_ADDR_HI                      },
-+	{ 0xb4540fef, mmCP_HQD_PQ_BASE                           },
-+	{ 0x00000000, mmCP_HQD_PQ_BASE_HI                        },
-+	{ 0x540fee20, mmCP_HQD_PQ_WPTR_POLL_ADDR                 },
-+	{ 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI              },
-+	{ 0x00005301, mmCP_HQD_PERSISTENT_STATE                  },
-+	{ 0x00010000, mmCP_HQD_VMID                              },
-+	{ 0xc8318509, mmCP_HQD_PQ_CONTROL                        },
-+	{ 0x00000004, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000104, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000204, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000304, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000404, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000504, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000604, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000704, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000005, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000105, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000205, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000305, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000405, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000505, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000605, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000705, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000006, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000106, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000206, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000306, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000406, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000506, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000606, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000706, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000007, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000107, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000207, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000307, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000407, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000507, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000607, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000707, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000008, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000108, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000208, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000308, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000408, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000508, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000608, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000708, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000009, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000109, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000209, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000309, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000409, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000509, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000609, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000709, mmSRBM_GFX_CNTL                            },
-+	{ 0x00000000, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000000, mmCP_HQD_PQ_RPTR                           },
-+	{ 0x00000000, mmCP_HQD_PQ_WPTR                           },
-+	{ 0x00000001, mmCP_HQD_ACTIVE                            },
-+	{ 0x00000004, mmSRBM_GFX_CNTL                            },
-+	{ 0x01010101, mmCP_PQ_WPTR_POLL_CNTL1                    },
-+	{ 0x00000000, mmGRBM_STATUS                              },
-+	{ 0x00000000, mmGRBM_STATUS                              },
-+	{ 0x00000000, mmGRBM_STATUS                              },
-+	{ 0x00000000, 0xFFFFFFFF                                 },
- };
- 
- 
---- linux-4.14/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h	2017-12-14 06:39:58.480903613 +0100
-@@ -23,22 +23,15 @@
- #ifndef _PP_INSTANCE_H_
- #define _PP_INSTANCE_H_
- 
--#include "smumgr.h"
- #include "hwmgr.h"
--#include "eventmgr.h"
--
--#define PP_VALID  0x1F1F1F1F
- 
- struct pp_instance {
--	uint32_t pp_valid;
- 	uint32_t chip_family;
- 	uint32_t chip_id;
- 	bool pm_en;
- 	uint32_t feature_mask;
- 	void *device;
--	struct pp_smumgr *smu_mgr;
- 	struct pp_hwmgr *hwmgr;
--	struct pp_eventmgr *eventmgr;
- 	struct mutex pp_lock;
- };
- 
---- linux-4.14/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h	2017-12-14 06:39:58.480903613 +0100
-@@ -70,7 +70,12 @@
- #define PPSMC_MSG_SetPhyclkVoltageByFreq        0x26
- #define PPSMC_MSG_SetDppclkVoltageByFreq        0x27
- #define PPSMC_MSG_SetSoftMinVcn                 0x28
--#define PPSMC_Message_Count                     0x29
-+#define PPSMC_MSG_GetGfxclkFrequency            0x2A
-+#define PPSMC_MSG_GetFclkFrequency              0x2B
-+#define PPSMC_MSG_GetMinGfxclkFrequency         0x2C
-+#define PPSMC_MSG_GetMaxGfxclkFrequency         0x2D
-+#define PPSMC_MSG_SoftReset                     0x2E
-+#define PPSMC_Message_Count                     0x2F
- 
- 
- typedef uint16_t PPSMC_Result;
---- linux-4.14/drivers/gpu/drm/amd/powerplay/inc/smumgr.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/inc/smumgr.h	2017-12-14 06:39:58.480903613 +0100
-@@ -23,23 +23,13 @@
- #ifndef _SMUMGR_H_
- #define _SMUMGR_H_
- #include <linux/types.h>
--#include "pp_instance.h"
- #include "amd_powerplay.h"
--
--struct pp_smumgr;
--struct pp_instance;
--struct pp_hwmgr;
-+#include "hwmgr.h"
- 
- #define smu_lower_32_bits(n) ((uint32_t)(n))
- #define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16))
- 
--extern const struct pp_smumgr_func cz_smu_funcs;
--extern const struct pp_smumgr_func iceland_smu_funcs;
--extern const struct pp_smumgr_func tonga_smu_funcs;
--extern const struct pp_smumgr_func fiji_smu_funcs;
--extern const struct pp_smumgr_func polaris10_smu_funcs;
--extern const struct pp_smumgr_func vega10_smu_funcs;
--extern const struct pp_smumgr_func rv_smu_funcs;
-+
- 
- enum AVFS_BTC_STATUS {
- 	AVFS_BTC_BOOT = 0,
-@@ -85,6 +75,11 @@ enum SMU_MEMBER {
- 	VceBootLevel,
- 	SamuBootLevel,
- 	LowSclkInterruptThreshold,
-+	DRAM_LOG_ADDR_H,
-+	DRAM_LOG_ADDR_L,
-+	DRAM_LOG_PHY_ADDR_H,
-+	DRAM_LOG_PHY_ADDR_L,
-+	DRAM_LOG_BUFF_SIZE,
- };
- 
- 
-@@ -100,216 +95,44 @@ enum SMU_MAC_DEFINITION {
- 	SMU_UVD_MCLK_HANDSHAKE_DISABLE,
- };
- 
-+extern int smum_get_argument(struct pp_hwmgr *hwmgr);
- 
--struct pp_smumgr_func {
--	int (*smu_init)(struct pp_smumgr *smumgr);
--	int (*smu_fini)(struct pp_smumgr *smumgr);
--	int (*start_smu)(struct pp_smumgr *smumgr);
--	int (*check_fw_load_finish)(struct pp_smumgr *smumgr,
--				    uint32_t firmware);
--	int (*request_smu_load_fw)(struct pp_smumgr *smumgr);
--	int (*request_smu_load_specific_fw)(struct pp_smumgr *smumgr,
--					    uint32_t firmware);
--	int (*get_argument)(struct pp_smumgr *smumgr);
--	int (*send_msg_to_smc)(struct pp_smumgr *smumgr, uint16_t msg);
--	int (*send_msg_to_smc_with_parameter)(struct pp_smumgr *smumgr,
--					  uint16_t msg, uint32_t parameter);
--	int (*download_pptable_settings)(struct pp_smumgr *smumgr,
--					 void **table);
--	int (*upload_pptable_settings)(struct pp_smumgr *smumgr);
--	int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
--	int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
--	int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
--	int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
--	int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
--	int (*init_smc_table)(struct pp_hwmgr *hwmgr);
--	int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
--	int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
--	int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
--	uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
--	uint32_t (*get_mac_definition)(uint32_t value);
--	bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
--	int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
--			struct amd_pp_profile *request);
--	bool (*is_hw_avfs_present)(struct pp_smumgr *smumgr);
--};
--
--struct pp_smumgr {
--	uint32_t chip_family;
--	uint32_t chip_id;
--	void *device;
--	void *backend;
--	uint32_t usec_timeout;
--	bool reload_fw;
--	const struct pp_smumgr_func *smumgr_funcs;
--	bool is_kicker;
--};
--
--extern int smum_early_init(struct pp_instance *handle);
-+extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table);
- 
--extern int smum_get_argument(struct pp_smumgr *smumgr);
-+extern int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr);
- 
--extern int smum_download_powerplay_table(struct pp_smumgr *smumgr, void **table);
-+extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
- 
--extern int smum_upload_powerplay_table(struct pp_smumgr *smumgr);
--
--extern int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg);
--
--extern int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
-+extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
- 					uint16_t msg, uint32_t parameter);
- 
--extern int smum_wait_on_register(struct pp_smumgr *smumgr,
--				uint32_t index, uint32_t value, uint32_t mask);
--
--extern int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
--				uint32_t index, uint32_t value, uint32_t mask);
--
--extern int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
--				uint32_t indirect_port, uint32_t index,
--				uint32_t value, uint32_t mask);
--
--
--extern void smum_wait_for_indirect_register_unequal(
--				struct pp_smumgr *smumgr,
--				uint32_t indirect_port, uint32_t index,
--				uint32_t value, uint32_t mask);
--
- extern int smu_allocate_memory(void *device, uint32_t size,
- 			 enum cgs_gpu_mem_type type,
- 			 uint32_t byte_align, uint64_t *mc_addr,
- 			 void **kptr, void *handle);
- 
- extern int smu_free_memory(void *device, void *handle);
--extern int vega10_smum_init(struct pp_smumgr *smumgr);
- 
- extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
- 
- extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
- extern int smum_process_firmware_header(struct pp_hwmgr *hwmgr);
--extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result);
--extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result);
-+extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr);
-+extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
- extern int smum_init_smc_table(struct pp_hwmgr *hwmgr);
- extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
- extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
- extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
--extern uint32_t smum_get_offsetof(struct pp_smumgr *smumgr,
-+extern uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr,
- 				uint32_t type, uint32_t member);
--extern uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value);
-+extern uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value);
- 
- extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr);
- 
- extern int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
- 		struct amd_pp_profile *request);
- 
--extern bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr);
--
--#define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
--
--#define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK
--
--#define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr,			\
--					port, index, value, mask)	\
--	smum_wait_on_indirect_register(smumgr,				\
--				mm##port##_INDEX, index, value, mask)
--
--#define SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, value, mask)    \
--	    SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
--
--#define SMUM_WAIT_INDIRECT_FIELD(smumgr, port, reg, field, fieldval)                          \
--	    SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
--			            SMUM_FIELD_MASK(reg, field) )
--
--#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr,         \
--							index, value, mask) \
--		smum_wait_for_register_unequal(smumgr,            \
--					index, value, mask)
--
--#define SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, value, mask)		\
--	SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr,			\
--				mm##reg, value, mask)
--
--#define SMUM_WAIT_FIELD_UNEQUAL(smumgr, reg, field, fieldval)		\
--	SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg,				\
--		(fieldval) << SMUM_FIELD_SHIFT(reg, field),		\
--		SMUM_FIELD_MASK(reg, field))
--
--#define SMUM_GET_FIELD(value, reg, field)				\
--		(((value) & SMUM_FIELD_MASK(reg, field))		\
--		>> SMUM_FIELD_SHIFT(reg, field))
--
--#define SMUM_READ_FIELD(device, reg, field)                           \
--		SMUM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
--
--#define SMUM_SET_FIELD(value, reg, field, field_val)                  \
--		(((value) & ~SMUM_FIELD_MASK(reg, field)) |                    \
--		(SMUM_FIELD_MASK(reg, field) & ((field_val) <<                 \
--			SMUM_FIELD_SHIFT(reg, field))))
--
--#define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \
--	    SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
--			   reg, field)
--
--#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr,		\
--				port, index, value, mask)		\
--	smum_wait_on_indirect_register(smumgr,				\
--		mm##port##_INDEX_0, index, value, mask)
--
--#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr,	\
--				port, index, value, mask)		\
--	smum_wait_for_indirect_register_unequal(smumgr,			\
--		mm##port##_INDEX_0, index, value, mask)
--
--
--#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \
--	SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
--
--#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask)     \
--		SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
--
--
--/*Operations on named fields.*/
--
--#define SMUM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
--		SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
--			reg, field)
--
--#define SMUM_WRITE_FIELD(device, reg, field, fieldval)            \
--		cgs_write_register(device, mm##reg, \
--		SMUM_SET_FIELD(cgs_read_register(device, mm##reg), reg, field, fieldval))
--
--#define SMUM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)    \
--		cgs_write_ind_register(device, port, ix##reg, \
--			SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
--			reg, field, fieldval))
--
--
--#define SMUM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)    		\
--		cgs_write_ind_register(device, port, ix##reg, 				\
--			SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), 	\
--				       reg, field, fieldval))
--
--
--#define SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
--	SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg,		\
--		(fieldval) << SMUM_FIELD_SHIFT(reg, field),		\
--		SMUM_FIELD_MASK(reg, field))
--
--#define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \
--	SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg,	\
--		(fieldval) << SMUM_FIELD_SHIFT(reg, field),		\
--		SMUM_FIELD_MASK(reg, field))
--
--#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, index, value, mask)    \
--	smum_wait_for_indirect_register_unequal(smumgr,			\
--		mm##port##_INDEX, index, value, mask)
--
--#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask)    \
--	    SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
-+extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
- 
--#define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval)                          \
--	    SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
--			            SMUM_FIELD_MASK(reg, field) )
- 
- #endif
---- linux-4.14/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h	2017-12-14 06:39:58.480903613 +0100
-@@ -124,12 +124,15 @@ typedef uint16_t PPSMC_Result;
- #define PPSMC_MSG_NumOfDisplays                  0x56
- #define PPSMC_MSG_ReadSerialNumTop32             0x58
- #define PPSMC_MSG_ReadSerialNumBottom32          0x59
-+#define PPSMC_MSG_SetSystemVirtualDramAddrHigh   0x5A
-+#define PPSMC_MSG_SetSystemVirtualDramAddrLow    0x5B
- #define PPSMC_MSG_RunAcgBtc                      0x5C
- #define PPSMC_MSG_RunAcgInClosedLoop             0x5D
- #define PPSMC_MSG_RunAcgInOpenLoop               0x5E
- #define PPSMC_MSG_InitializeAcg                  0x5F
- #define PPSMC_MSG_GetCurrPkgPwr                  0x61
--#define PPSMC_Message_Count                      0x62
-+#define PPSMC_MSG_UpdatePkgPwrPidAlpha           0x68
-+#define PPSMC_Message_Count                      0x69
- 
- 
- typedef int PPSMC_Msg;
---- linux-4.14/drivers/gpu/drm/amd/powerplay/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/Makefile	2017-12-14 06:39:58.480903613 +0100
-@@ -5,12 +5,11 @@ subdir-ccflags-y += \
- 		-I$(FULL_AMD_PATH)/include/asic_reg  \
- 		-I$(FULL_AMD_PATH)/include  \
- 		-I$(FULL_AMD_PATH)/powerplay/smumgr\
--		-I$(FULL_AMD_PATH)/powerplay/hwmgr \
--		-I$(FULL_AMD_PATH)/powerplay/eventmgr
-+		-I$(FULL_AMD_PATH)/powerplay/hwmgr
- 
- AMD_PP_PATH = ../powerplay
- 
--PP_LIBS = smumgr hwmgr eventmgr
-+PP_LIBS = smumgr hwmgr
- 
- AMD_POWERPLAY = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/powerplay/,$(PP_LIBS)))
- 
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c.0130~	2017-12-14 06:39:58.481903613 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c	2017-12-14 06:39:58.481903613 +0100
-@@ -0,0 +1,2816 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/fb.h>
-+#include "linux/delay.h"
-+#include <linux/types.h>
-+
-+#include "smumgr.h"
-+#include "pp_debug.h"
-+#include "ci_smumgr.h"
-+#include "ppsmc.h"
-+#include "smu7_hwmgr.h"
-+#include "hardwaremanager.h"
-+#include "ppatomctrl.h"
-+#include "cgs_common.h"
-+#include "atombios.h"
-+#include "pppcielanes.h"
-+
-+#include "smu/smu_7_0_1_d.h"
-+#include "smu/smu_7_0_1_sh_mask.h"
-+
-+#include "dce/dce_8_0_d.h"
-+#include "dce/dce_8_0_sh_mask.h"
-+
-+#include "bif/bif_4_1_d.h"
-+#include "bif/bif_4_1_sh_mask.h"
-+
-+#include "gca/gfx_7_2_d.h"
-+#include "gca/gfx_7_2_sh_mask.h"
-+
-+#include "gmc/gmc_7_1_d.h"
-+#include "gmc/gmc_7_1_sh_mask.h"
-+
-+#include "processpptables.h"
-+
-+#define MC_CG_ARB_FREQ_F0           0x0a
-+#define MC_CG_ARB_FREQ_F1           0x0b
-+#define MC_CG_ARB_FREQ_F2           0x0c
-+#define MC_CG_ARB_FREQ_F3           0x0d
-+
-+#define SMC_RAM_END 0x40000
-+
-+#define VOLTAGE_SCALE               4
-+#define VOLTAGE_VID_OFFSET_SCALE1    625
-+#define VOLTAGE_VID_OFFSET_SCALE2    100
-+#define CISLAND_MINIMUM_ENGINE_CLOCK 800
-+#define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5
-+
-+static const struct ci_pt_defaults defaults_hawaii_xt = {
-+	1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
-+	{ 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
-+	{ 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
-+};
-+
-+static const struct ci_pt_defaults defaults_hawaii_pro = {
-+	1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
-+	{ 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
-+	{ 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
-+};
-+
-+static const struct ci_pt_defaults defaults_bonaire_xt = {
-+	1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
-+	{ 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
-+	{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
-+};
-+
-+
-+static const struct ci_pt_defaults defaults_saturn_xt = {
-+	1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
-+	{ 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
-+	{ 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
-+};
-+
-+
-+static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr,
-+					uint32_t smc_addr, uint32_t limit)
-+{
-+	if ((0 != (3 & smc_addr))
-+		|| ((smc_addr + 3) >= limit)) {
-+		pr_err("smc_addr invalid \n");
-+		return -EINVAL;
-+	}
-+
-+	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr);
-+	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
-+	return 0;
-+}
-+
-+static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
-+				const uint8_t *src, uint32_t byte_count, uint32_t limit)
-+{
-+	int result;
-+	uint32_t data = 0;
-+	uint32_t original_data;
-+	uint32_t addr = 0;
-+	uint32_t extra_shift;
-+
-+	if ((3 & smc_start_address)
-+		|| ((smc_start_address + byte_count) >= limit)) {
-+		pr_err("smc_start_address invalid \n");
-+		return -EINVAL;
-+	}
-+
-+	addr = smc_start_address;
-+
-+	while (byte_count >= 4) {
-+	/* Bytes are written into the SMC address space with the MSB first. */
-+		data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
-+
-+		result = ci_set_smc_sram_address(hwmgr, addr, limit);
-+
-+		if (0 != result)
-+			return result;
-+
-+		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
-+
-+		src += 4;
-+		byte_count -= 4;
-+		addr += 4;
-+	}
-+
-+	if (0 != byte_count) {
-+
-+		data = 0;
-+
-+		result = ci_set_smc_sram_address(hwmgr, addr, limit);
-+
-+		if (0 != result)
-+			return result;
-+
-+
-+		original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
-+
-+		extra_shift = 8 * (4 - byte_count);
-+
-+		while (byte_count > 0) {
-+			/* Bytes are written into the SMC addres space with the MSB first. */
-+			data = (0x100 * data) + *src++;
-+			byte_count--;
-+		}
-+
-+		data <<= extra_shift;
-+
-+		data |= (original_data & ~((~0UL) << extra_shift));
-+
-+		result = ci_set_smc_sram_address(hwmgr, addr, limit);
-+
-+		if (0 != result)
-+			return result;
-+
-+		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static int ci_program_jump_on_start(struct pp_hwmgr *hwmgr)
-+{
-+	static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
-+
-+	ci_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);
-+
-+	return 0;
-+}
-+
-+bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr)
-+{
-+	return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
-+			CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
-+	&& (0x20100 <= cgs_read_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, ixSMC_PC_C)));
-+}
-+
-+static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
-+				uint32_t *value, uint32_t limit)
-+{
-+	int result;
-+
-+	result = ci_set_smc_sram_address(hwmgr, smc_addr, limit);
-+
-+	if (result)
-+		return result;
-+
-+	*value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
-+	return 0;
-+}
-+
-+static int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
-+{
-+	int ret;
-+
-+	if (!ci_is_smc_ram_running(hwmgr))
-+		return -EINVAL;
-+
-+	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
-+
-+	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
-+
-+	ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
-+
-+	if (ret != 1)
-+		pr_info("\n failed to send message %x ret is %d\n",  msg, ret);
-+
-+	return 0;
-+}
-+
-+static int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
-+					uint16_t msg, uint32_t parameter)
-+{
-+	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
-+	return ci_send_msg_to_smc(hwmgr, msg);
-+}
-+
-+static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
-+{
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	struct cgs_system_info sys_info = {0};
-+	uint32_t dev_id;
-+
-+	sys_info.size = sizeof(struct cgs_system_info);
-+	sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
-+	cgs_query_system_info(hwmgr->device, &sys_info);
-+	dev_id = (uint32_t)sys_info.value;
-+
-+	switch (dev_id) {
-+	case 0x67BA:
-+	case 0x66B1:
-+		smu_data->power_tune_defaults = &defaults_hawaii_pro;
-+		break;
-+	case 0x67B8:
-+	case 0x66B0:
-+		smu_data->power_tune_defaults = &defaults_hawaii_xt;
-+		break;
-+	case 0x6640:
-+	case 0x6641:
-+	case 0x6646:
-+	case 0x6647:
-+		smu_data->power_tune_defaults = &defaults_saturn_xt;
-+		break;
-+	case 0x6649:
-+	case 0x6650:
-+	case 0x6651:
-+	case 0x6658:
-+	case 0x665C:
-+	case 0x665D:
-+	case 0x67A0:
-+	case 0x67A1:
-+	case 0x67A2:
-+	case 0x67A8:
-+	case 0x67A9:
-+	case 0x67AA:
-+	case 0x67B9:
-+	case 0x67BE:
-+	default:
-+		smu_data->power_tune_defaults = &defaults_bonaire_xt;
-+		break;
-+	}
-+}
-+
-+static int ci_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
-+	struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,
-+	uint32_t clock, uint32_t *vol)
-+{
-+	uint32_t i = 0;
-+
-+	if (allowed_clock_voltage_table->count == 0)
-+		return -EINVAL;
-+
-+	for (i = 0; i < allowed_clock_voltage_table->count; i++) {
-+		if (allowed_clock_voltage_table->entries[i].clk >= clock) {
-+			*vol = allowed_clock_voltage_table->entries[i].v;
-+			return 0;
-+		}
-+	}
-+
-+	*vol = allowed_clock_voltage_table->entries[i - 1].v;
-+	return 0;
-+}
-+
-+static int ci_calculate_sclk_params(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, struct SMU7_Discrete_GraphicsLevel *sclk)
-+{
-+	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
-+	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
-+	uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
-+	uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
-+	uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
-+	uint32_t ref_clock;
-+	uint32_t ref_divider;
-+	uint32_t fbdiv;
-+	int result;
-+
-+	/* get the engine clock dividers for this clock value */
-+	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock,  &dividers);
-+
-+	PP_ASSERT_WITH_CODE(result == 0,
-+			"Error retrieving Engine Clock dividers from VBIOS.",
-+			return result);
-+
-+	/* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
-+	ref_clock = atomctrl_get_reference_clock(hwmgr);
-+	ref_divider = 1 + dividers.uc_pll_ref_div;
-+
-+	/* low 14 bits is fraction and high 12 bits is divider */
-+	fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
-+
-+	/* SPLL_FUNC_CNTL setup */
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
-+			SPLL_REF_DIV, dividers.uc_pll_ref_div);
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
-+			SPLL_PDIV_A,  dividers.uc_pll_post_div);
-+
-+	/* SPLL_FUNC_CNTL_3 setup*/
-+	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
-+			SPLL_FB_DIV, fbdiv);
-+
-+	/* set to use fractional accumulation*/
-+	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
-+			SPLL_DITHEN, 1);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
-+		struct pp_atomctrl_internal_ss_info ss_info;
-+		uint32_t vco_freq = clock * dividers.uc_pll_post_div;
-+
-+		if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
-+				vco_freq, &ss_info)) {
-+			uint32_t clk_s = ref_clock * 5 /
-+					(ref_divider * ss_info.speed_spectrum_rate);
-+			uint32_t clk_v = 4 * ss_info.speed_spectrum_percentage *
-+					fbdiv / (clk_s * 10000);
-+
-+			cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
-+					CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
-+			cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
-+					CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
-+			cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
-+					CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
-+		}
-+	}
-+
-+	sclk->SclkFrequency        = clock;
-+	sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
-+	sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
-+	sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
-+	sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
-+	sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
-+
-+	return 0;
-+}
-+
-+static void ci_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
-+				const struct phm_phase_shedding_limits_table *pl,
-+					uint32_t sclk, uint32_t *p_shed)
-+{
-+	unsigned int i;
-+
-+	/* use the minimum phase shedding */
-+	*p_shed = 1;
-+
-+	for (i = 0; i < pl->count; i++) {
-+		if (sclk < pl->entries[i].Sclk) {
-+			*p_shed = i;
-+			break;
-+		}
-+	}
-+}
-+
-+static uint8_t ci_get_sleep_divider_id_from_clock(uint32_t clock,
-+			uint32_t clock_insr)
-+{
-+	uint8_t i;
-+	uint32_t temp;
-+	uint32_t min = min_t(uint32_t, clock_insr, CISLAND_MINIMUM_ENGINE_CLOCK);
-+
-+	if (clock < min) {
-+		pr_info("Engine clock can't satisfy stutter requirement!\n");
-+		return 0;
-+	}
-+	for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
-+		temp = clock >> i;
-+
-+		if (temp >= min || i == 0)
-+			break;
-+	}
-+	return i;
-+}
-+
-+static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, uint16_t sclk_al_threshold,
-+		struct SMU7_Discrete_GraphicsLevel *level)
-+{
-+	int result;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+
-+	result = ci_calculate_sclk_params(hwmgr, clock, level);
-+
-+	/* populate graphics levels */
-+	result = ci_get_dependency_volt_by_clk(hwmgr,
-+			hwmgr->dyn_state.vddc_dependency_on_sclk, clock,
-+			(uint32_t *)(&level->MinVddc));
-+	if (result) {
-+		pr_err("vdd_dep_on_sclk table is NULL\n");
-+		return result;
-+	}
-+
-+	level->SclkFrequency = clock;
-+	level->MinVddcPhases = 1;
-+
-+	if (data->vddc_phase_shed_control)
-+		ci_populate_phase_value_based_on_sclk(hwmgr,
-+				hwmgr->dyn_state.vddc_phase_shed_limits_table,
-+				clock,
-+				&level->MinVddcPhases);
-+
-+	level->ActivityLevel = sclk_al_threshold;
-+	level->CcPwrDynRm = 0;
-+	level->CcPwrDynRm1 = 0;
-+	level->EnabledForActivity = 0;
-+	/* this level can be used for throttling.*/
-+	level->EnabledForThrottle = 1;
-+	level->UpH = 0;
-+	level->DownH = 0;
-+	level->VoltageDownH = 0;
-+	level->PowerThrottle = 0;
-+
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkDeepSleep))
-+		level->DeepSleepDivId =
-+				ci_get_sleep_divider_id_from_clock(clock,
-+						CISLAND_MINIMUM_ENGINE_CLOCK);
-+
-+	/* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
-+	level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	if (0 == result) {
-+		level->MinVddc = PP_HOST_TO_SMC_UL(level->MinVddc * VOLTAGE_SCALE);
-+		CONVERT_FROM_HOST_TO_SMC_UL(level->MinVddcPhases);
-+		CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
-+		CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
-+		CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
-+		CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
-+		CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
-+		CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
-+		CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
-+	}
-+
-+	return result;
-+}
-+
-+static int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_dpm_table *dpm_table = &data->dpm_table;
-+	int result = 0;
-+	uint32_t array = smu_data->dpm_table_start +
-+			offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
-+	uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) *
-+			SMU7_MAX_LEVELS_GRAPHICS;
-+	struct SMU7_Discrete_GraphicsLevel *levels =
-+			smu_data->smc_state_table.GraphicsLevel;
-+	uint32_t i;
-+
-+	for (i = 0; i < dpm_table->sclk_table.count; i++) {
-+		result = ci_populate_single_graphic_level(hwmgr,
-+				dpm_table->sclk_table.dpm_levels[i].value,
-+				(uint16_t)smu_data->activity_target[i],
-+				&levels[i]);
-+		if (result)
-+			return result;
-+		if (i > 1)
-+			smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
-+		if (i == (dpm_table->sclk_table.count - 1))
-+			smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark =
-+				PPSMC_DISPLAY_WATERMARK_HIGH;
-+	}
-+
-+	smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
-+
-+	smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
-+	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
-+		phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
-+
-+	result = ci_copy_bytes_to_smc(hwmgr, array,
-+				   (u8 *)levels, array_size,
-+				   SMC_RAM_END);
-+
-+	return result;
-+
-+}
-+
-+static int ci_populate_svi_load_line(struct pp_hwmgr *hwmgr)
-+{
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
-+
-+	smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
-+	smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddc;
-+	smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
-+	smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
-+
-+	return 0;
-+}
-+
-+static int ci_populate_tdc_limit(struct pp_hwmgr *hwmgr)
-+{
-+	uint16_t tdc_limit;
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
-+
-+	tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
-+	smu_data->power_tune_table.TDC_VDDC_PkgLimit =
-+			CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
-+	smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
-+			defaults->tdc_vddc_throttle_release_limit_perc;
-+	smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
-+
-+	return 0;
-+}
-+
-+static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
-+{
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
-+	uint32_t temp;
-+
-+	if (ci_read_smc_sram_dword(hwmgr,
-+			fuse_table_offset +
-+			offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
-+			(uint32_t *)&temp, SMC_RAM_END))
-+		PP_ASSERT_WITH_CODE(false,
-+				"Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
-+				return -EINVAL);
-+	else
-+		smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
-+
-+	return 0;
-+}
-+
-+static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
-+{
-+	uint16_t tmp;
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+
-+	if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
-+		|| 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
-+		tmp = hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity;
-+	else
-+		tmp = hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
-+
-+	smu_data->power_tune_table.FuzzyFan_PwmSetDelta = CONVERT_FROM_HOST_TO_SMC_US(tmp);
-+
-+	return 0;
-+}
-+
-+static int ci_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
-+	uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
-+	uint8_t *hi2_vid = smu_data->power_tune_table.BapmVddCVidHiSidd2;
-+
-+	PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
-+			    "The CAC Leakage table does not exist!", return -EINVAL);
-+	PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
-+			    "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL);
-+	PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
-+			    "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL);
-+
-+	for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) {
-+			lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
-+			hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2);
-+			hi2_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc3);
-+		} else {
-+			lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc);
-+			hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Leakage);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int ci_populate_vddc_vid(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	uint8_t *vid = smu_data->power_tune_table.VddCVid;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
-+		"There should never be more than 8 entries for VddcVid!!!",
-+		return -EINVAL);
-+
-+	for (i = 0; i < (int)data->vddc_voltage_table.count; i++)
-+		vid[i] = convert_to_vid(data->vddc_voltage_table.entries[i].value);
-+
-+	return 0;
-+}
-+
-+static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr)
-+{
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	u8 *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
-+	u8 *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
-+	int i, min, max;
-+
-+	min = max = hi_vid[0];
-+	for (i = 0; i < 8; i++) {
-+		if (0 != hi_vid[i]) {
-+			if (min > hi_vid[i])
-+				min = hi_vid[i];
-+			if (max < hi_vid[i])
-+				max = hi_vid[i];
-+		}
-+
-+		if (0 != lo_vid[i]) {
-+			if (min > lo_vid[i])
-+				min = lo_vid[i];
-+			if (max < lo_vid[i])
-+				max = lo_vid[i];
-+		}
-+	}
-+
-+	if ((min == 0) || (max == 0))
-+		return -EINVAL;
-+	smu_data->power_tune_table.GnbLPMLMaxVid = (u8)max;
-+	smu_data->power_tune_table.GnbLPMLMinVid = (u8)min;
-+
-+	return 0;
-+}
-+
-+static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
-+{
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
-+	uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
-+	struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
-+
-+	HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
-+	LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
-+
-+	smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
-+	smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
-+
-+	return 0;
-+}
-+
-+static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr)
-+{
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	uint32_t pm_fuse_table_offset;
-+	int ret = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment)) {
-+		if (ci_read_smc_sram_dword(hwmgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU7_Firmware_Header, PmFuseTable),
-+				&pm_fuse_table_offset, SMC_RAM_END)) {
-+			pr_err("Attempt to get pm_fuse_table_offset Failed!\n");
-+			return -EINVAL;
-+		}
-+
-+		/* DW0 - DW3 */
-+		ret = ci_populate_bapm_vddc_vid_sidd(hwmgr);
-+		/* DW4 - DW5 */
-+		ret |= ci_populate_vddc_vid(hwmgr);
-+		/* DW6 */
-+		ret |= ci_populate_svi_load_line(hwmgr);
-+		/* DW7 */
-+		ret |= ci_populate_tdc_limit(hwmgr);
-+		/* DW8 */
-+		ret |= ci_populate_dw8(hwmgr, pm_fuse_table_offset);
-+
-+		ret |= ci_populate_fuzzy_fan(hwmgr, pm_fuse_table_offset);
-+
-+		ret |= ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(hwmgr);
-+
-+		ret |= ci_populate_bapm_vddc_base_leakage_sidd(hwmgr);
-+		if (ret)
-+			return ret;
-+
-+		ret = ci_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
-+				(uint8_t *)&smu_data->power_tune_table,
-+				sizeof(struct SMU7_Discrete_PmFuses), SMC_RAM_END);
-+	}
-+	return ret;
-+}
-+
-+static int ci_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
-+	SMU7_Discrete_DpmTable  *dpm_table = &(smu_data->smc_state_table);
-+	struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table;
-+	struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table;
-+	const uint16_t *def1, *def2;
-+	int i, j, k;
-+
-+	dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256));
-+	dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
-+
-+	dpm_table->DTETjOffset = 0;
-+	dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES);
-+	dpm_table->GpuTjHyst = 8;
-+
-+	dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
-+
-+	if (ppm) {
-+		dpm_table->PPM_PkgPwrLimit = (uint16_t)ppm->dgpu_tdp * 256 / 1000;
-+		dpm_table->PPM_TemperatureLimit = (uint16_t)ppm->tj_max * 256;
-+	} else {
-+		dpm_table->PPM_PkgPwrLimit = 0;
-+		dpm_table->PPM_TemperatureLimit = 0;
-+	}
-+
-+	CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit);
-+	CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit);
-+
-+	dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
-+	def1 = defaults->bapmti_r;
-+	def2 = defaults->bapmti_rc;
-+
-+	for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
-+		for (j = 0; j < SMU7_DTE_SOURCES; j++) {
-+			for (k = 0; k < SMU7_DTE_SINKS; k++) {
-+				dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
-+				dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
-+				def1++;
-+				def2++;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int ci_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
-+		pp_atomctrl_voltage_table_entry *tab, uint16_t *hi,
-+		uint16_t *lo)
-+{
-+	uint16_t v_index;
-+	bool vol_found = false;
-+	*hi = tab->value * VOLTAGE_SCALE;
-+	*lo = tab->value * VOLTAGE_SCALE;
-+
-+	PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
-+			"The SCLK/VDDC Dependency Table does not exist.\n",
-+			return -EINVAL);
-+
-+	if (NULL == hwmgr->dyn_state.cac_leakage_table) {
-+		pr_warn("CAC Leakage Table does not exist, using vddc.\n");
-+		return 0;
-+	}
-+
-+	for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
-+		if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
-+			vol_found = true;
-+			if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
-+				*lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
-+				*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE);
-+			} else {
-+				pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
-+				*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
-+				*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
-+			}
-+			break;
-+		}
-+	}
-+
-+	if (!vol_found) {
-+		for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
-+			if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
-+				vol_found = true;
-+				if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
-+					*lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
-+					*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE;
-+				} else {
-+					pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.");
-+					*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
-+					*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
-+				}
-+				break;
-+			}
-+		}
-+
-+		if (!vol_found)
-+			pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n");
-+	}
-+
-+	return 0;
-+}
-+
-+static int ci_populate_smc_voltage_table(struct pp_hwmgr *hwmgr,
-+		pp_atomctrl_voltage_table_entry *tab,
-+		SMU7_Discrete_VoltageLevel *smc_voltage_tab)
-+{
-+	int result;
-+
-+	result = ci_get_std_voltage_value_sidd(hwmgr, tab,
-+			&smc_voltage_tab->StdVoltageHiSidd,
-+			&smc_voltage_tab->StdVoltageLoSidd);
-+	if (result) {
-+		smc_voltage_tab->StdVoltageHiSidd = tab->value * VOLTAGE_SCALE;
-+		smc_voltage_tab->StdVoltageLoSidd = tab->value * VOLTAGE_SCALE;
-+	}
-+
-+	smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE);
-+	CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
-+	CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageLoSidd);
-+
-+	return 0;
-+}
-+
-+static int ci_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
-+			SMU7_Discrete_DpmTable *table)
-+{
-+	unsigned int count;
-+	int result;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	table->VddcLevelCount = data->vddc_voltage_table.count;
-+	for (count = 0; count < table->VddcLevelCount; count++) {
-+		result = ci_populate_smc_voltage_table(hwmgr,
-+				&(data->vddc_voltage_table.entries[count]),
-+				&(table->VddcLevel[count]));
-+		PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
-+
-+		/* GPIO voltage control */
-+		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control)
-+			table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low;
-+		else
-+			table->VddcLevel[count].Smio = 0;
-+	}
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
-+
-+	return 0;
-+}
-+
-+static int ci_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
-+			SMU7_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t count;
-+	int result;
-+
-+	table->VddciLevelCount = data->vddci_voltage_table.count;
-+
-+	for (count = 0; count < table->VddciLevelCount; count++) {
-+		result = ci_populate_smc_voltage_table(hwmgr,
-+				&(data->vddci_voltage_table.entries[count]),
-+				&(table->VddciLevel[count]));
-+		PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
-+		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
-+			table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low;
-+		else
-+			table->VddciLevel[count].Smio |= 0;
-+	}
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
-+
-+	return 0;
-+}
-+
-+static int ci_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
-+			SMU7_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t count;
-+	int result;
-+
-+	table->MvddLevelCount = data->mvdd_voltage_table.count;
-+
-+	for (count = 0; count < table->MvddLevelCount; count++) {
-+		result = ci_populate_smc_voltage_table(hwmgr,
-+				&(data->mvdd_voltage_table.entries[count]),
-+				&table->MvddLevel[count]);
-+		PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);
-+		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control)
-+			table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low;
-+		else
-+			table->MvddLevel[count].Smio |= 0;
-+	}
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
-+
-+	return 0;
-+}
-+
-+
-+static int ci_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
-+	SMU7_Discrete_DpmTable *table)
-+{
-+	int result;
-+
-+	result = ci_populate_smc_vddc_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"can not populate VDDC voltage table to SMC", return -EINVAL);
-+
-+	result = ci_populate_smc_vdd_ci_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"can not populate VDDCI voltage table to SMC", return -EINVAL);
-+
-+	result = ci_populate_smc_mvdd_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"can not populate MVDD voltage table to SMC", return -EINVAL);
-+
-+	return 0;
-+}
-+
-+static int ci_populate_ulv_level(struct pp_hwmgr *hwmgr,
-+		struct SMU7_Discrete_Ulv *state)
-+{
-+	uint32_t voltage_response_time, ulv_voltage;
-+	int result;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	state->CcPwrDynRm = 0;
-+	state->CcPwrDynRm1 = 0;
-+
-+	result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage);
-+	PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);
-+
-+	if (ulv_voltage == 0) {
-+		data->ulv_supported = false;
-+		return 0;
-+	}
-+
-+	if (data->voltage_control != SMU7_VOLTAGE_CONTROL_BY_SVID2) {
-+		/* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
-+		if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
-+			state->VddcOffset = 0;
-+		else
-+			/* used in SMIO Mode. not implemented for now. this is backup only for CI. */
-+			state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
-+	} else {
-+		/* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
-+		if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
-+			state->VddcOffsetVid = 0;
-+		else  /* used in SVI2 Mode */
-+			state->VddcOffsetVid = (uint8_t)(
-+					(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage)
-+						* VOLTAGE_VID_OFFSET_SCALE2
-+						/ VOLTAGE_VID_OFFSET_SCALE1);
-+	}
-+	state->VddcPhase = 1;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
-+	CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
-+
-+	return 0;
-+}
-+
-+static int ci_populate_ulv_state(struct pp_hwmgr *hwmgr,
-+		 SMU7_Discrete_Ulv *ulv_level)
-+{
-+	return ci_populate_ulv_level(hwmgr, ulv_level);
-+}
-+
-+static int ci_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct smu7_dpm_table *dpm_table = &data->dpm_table;
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	uint32_t i;
-+
-+/* Index dpm_table->pcie_speed_table.count is reserved for PCIE boot level.*/
-+	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
-+		table->LinkLevel[i].PcieGenSpeed  =
-+			(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
-+		table->LinkLevel[i].PcieLaneCount =
-+			(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
-+		table->LinkLevel[i].EnabledForActivity = 1;
-+		table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5);
-+		table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30);
-+	}
-+
-+	smu_data->smc_state_table.LinkLevelCount =
-+		(uint8_t)dpm_table->pcie_speed_table.count;
-+	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
-+		phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
-+
-+	return 0;
-+}
-+
-+static int ci_calculate_mclk_params(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t memory_clock,
-+		SMU7_Discrete_MemoryLevel *mclk,
-+		bool strobe_mode,
-+		bool dllStateOn
-+		)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t  dll_cntl = data->clock_registers.vDLL_CNTL;
-+	uint32_t  mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
-+	uint32_t  mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
-+	uint32_t  mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
-+	uint32_t  mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
-+	uint32_t  mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
-+	uint32_t  mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
-+	uint32_t  mpll_ss1 = data->clock_registers.vMPLL_SS1;
-+	uint32_t  mpll_ss2 = data->clock_registers.vMPLL_SS2;
-+
-+	pp_atomctrl_memory_clock_param mpll_param;
-+	int result;
-+
-+	result = atomctrl_get_memory_pll_dividers_si(hwmgr,
-+				memory_clock, &mpll_param, strobe_mode);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Error retrieving Memory Clock Parameters from VBIOS.", return result);
-+
-+	mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
-+
-+	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
-+							MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
-+	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
-+							MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
-+	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
-+							MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
-+
-+	mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
-+							MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
-+
-+	if (data->is_memory_gddr5) {
-+		mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
-+								MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
-+		mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
-+								MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
-+		pp_atomctrl_internal_ss_info ss_info;
-+		uint32_t freq_nom;
-+		uint32_t tmp;
-+		uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
-+
-+		/* for GDDR5 for all modes and DDR3 */
-+		if (1 == mpll_param.qdr)
-+			freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
-+		else
-+			freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
-+
-+		/* tmp = (freq_nom / reference_clock * reference_divider) ^ 2  Note: S.I. reference_divider = 1*/
-+		tmp = (freq_nom / reference_clock);
-+		tmp = tmp * tmp;
-+
-+		if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
-+			uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
-+			uint32_t clkv =
-+				(uint32_t)((((131 * ss_info.speed_spectrum_percentage *
-+							ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
-+
-+			mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
-+			mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
-+		}
-+	}
-+
-+	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
-+	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
-+	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
-+
-+
-+	mclk->MclkFrequency   = memory_clock;
-+	mclk->MpllFuncCntl    = mpll_func_cntl;
-+	mclk->MpllFuncCntl_1  = mpll_func_cntl_1;
-+	mclk->MpllFuncCntl_2  = mpll_func_cntl_2;
-+	mclk->MpllAdFuncCntl  = mpll_ad_func_cntl;
-+	mclk->MpllDqFuncCntl  = mpll_dq_func_cntl;
-+	mclk->MclkPwrmgtCntl  = mclk_pwrmgt_cntl;
-+	mclk->DllCntl         = dll_cntl;
-+	mclk->MpllSs1         = mpll_ss1;
-+	mclk->MpllSs2         = mpll_ss2;
-+
-+	return 0;
-+}
-+
-+static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock,
-+		bool strobe_mode)
-+{
-+	uint8_t mc_para_index;
-+
-+	if (strobe_mode) {
-+		if (memory_clock < 12500)
-+			mc_para_index = 0x00;
-+		else if (memory_clock > 47500)
-+			mc_para_index = 0x0f;
-+		else
-+			mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
-+	} else {
-+		if (memory_clock < 65000)
-+			mc_para_index = 0x00;
-+		else if (memory_clock > 135000)
-+			mc_para_index = 0x0f;
-+		else
-+			mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
-+	}
-+
-+	return mc_para_index;
-+}
-+
-+static uint8_t ci_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
-+{
-+	uint8_t mc_para_index;
-+
-+	if (memory_clock < 10000)
-+		mc_para_index = 0;
-+	else if (memory_clock >= 80000)
-+		mc_para_index = 0x0f;
-+	else
-+		mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
-+
-+	return mc_para_index;
-+}
-+
-+static int ci_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
-+					uint32_t memory_clock, uint32_t *p_shed)
-+{
-+	unsigned int i;
-+
-+	*p_shed = 1;
-+
-+	for (i = 0; i < pl->count; i++) {
-+		if (memory_clock < pl->entries[i].Mclk) {
-+			*p_shed = i;
-+			break;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int ci_populate_single_memory_level(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t memory_clock,
-+		SMU7_Discrete_MemoryLevel *memory_level
-+		)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	int result = 0;
-+	bool dll_state_on;
-+	struct cgs_display_info info = {0};
-+	uint32_t mclk_edc_wr_enable_threshold = 40000;
-+	uint32_t mclk_edc_enable_threshold = 40000;
-+	uint32_t mclk_strobe_mode_threshold = 40000;
-+
-+	if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
-+		result = ci_get_dependency_volt_by_clk(hwmgr,
-+			hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+			"can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
-+		result = ci_get_dependency_volt_by_clk(hwmgr,
-+				hwmgr->dyn_state.vddci_dependency_on_mclk,
-+				memory_clock,
-+				&memory_level->MinVddci);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+			"can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result);
-+	}
-+
-+	if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) {
-+		result = ci_get_dependency_volt_by_clk(hwmgr,
-+				hwmgr->dyn_state.mvdd_dependency_on_mclk,
-+				memory_clock,
-+				&memory_level->MinMvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+			"can not find MinVddci voltage value from memory MVDD voltage dependency table", return result);
-+	}
-+
-+	memory_level->MinVddcPhases = 1;
-+
-+	if (data->vddc_phase_shed_control) {
-+		ci_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,
-+				memory_clock, &memory_level->MinVddcPhases);
-+	}
-+
-+	memory_level->EnabledForThrottle = 1;
-+	memory_level->EnabledForActivity = 1;
-+	memory_level->UpH = 0;
-+	memory_level->DownH = 100;
-+	memory_level->VoltageDownH = 0;
-+
-+	/* Indicates maximum activity level for this performance level.*/
-+	memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
-+	memory_level->StutterEnable = 0;
-+	memory_level->StrobeEnable = 0;
-+	memory_level->EdcReadEnable = 0;
-+	memory_level->EdcWriteEnable = 0;
-+	memory_level->RttEnable = 0;
-+
-+	/* default set to low watermark. Highest level will be set to high later.*/
-+	memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+	data->display_timing.num_existing_displays = info.display_count;
-+
-+	/* stutter mode not support on ci */
-+
-+	/* decide strobe mode*/
-+	memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
-+		(memory_clock <= mclk_strobe_mode_threshold);
-+
-+	/* decide EDC mode and memory clock ratio*/
-+	if (data->is_memory_gddr5) {
-+		memory_level->StrobeRatio = ci_get_mclk_frequency_ratio(memory_clock,
-+					memory_level->StrobeEnable);
-+
-+		if ((mclk_edc_enable_threshold != 0) &&
-+				(memory_clock > mclk_edc_enable_threshold)) {
-+			memory_level->EdcReadEnable = 1;
-+		}
-+
-+		if ((mclk_edc_wr_enable_threshold != 0) &&
-+				(memory_clock > mclk_edc_wr_enable_threshold)) {
-+			memory_level->EdcWriteEnable = 1;
-+		}
-+
-+		if (memory_level->StrobeEnable) {
-+			if (ci_get_mclk_frequency_ratio(memory_clock, 1) >=
-+					((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf))
-+				dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
-+			else
-+				dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
-+		} else
-+			dll_state_on = data->dll_default_on;
-+	} else {
-+		memory_level->StrobeRatio =
-+			ci_get_ddr3_mclk_frequency_ratio(memory_clock);
-+		dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
-+	}
-+
-+	result = ci_calculate_mclk_params(hwmgr,
-+		memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
-+
-+	if (0 == result) {
-+		memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases);
-+		memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);
-+		memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);
-+		/* MCLK frequency in units of 10KHz*/
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
-+		/* Indicates maximum activity level for this performance level.*/
-+		CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
-+	}
-+
-+	return result;
-+}
-+
-+static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_dpm_table *dpm_table = &data->dpm_table;
-+	int result;
-+	struct cgs_system_info sys_info = {0};
-+	uint32_t dev_id;
-+
-+	uint32_t level_array_address = smu_data->dpm_table_start + offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
-+	uint32_t level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * SMU7_MAX_LEVELS_MEMORY;
-+	SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
-+	uint32_t i;
-+
-+	memset(levels, 0x00, level_array_size);
-+
-+	for (i = 0; i < dpm_table->mclk_table.count; i++) {
-+		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
-+			"can not populate memory level as memory clock is zero", return -EINVAL);
-+		result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
-+			&(smu_data->smc_state_table.MemoryLevel[i]));
-+		if (0 != result)
-+			return result;
-+	}
-+
-+	smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
-+
-+	sys_info.size = sizeof(struct cgs_system_info);
-+	sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
-+	cgs_query_system_info(hwmgr->device, &sys_info);
-+	dev_id = (uint32_t)sys_info.value;
-+
-+	if ((dpm_table->mclk_table.count >= 2)
-+		&& ((dev_id == 0x67B0) ||  (dev_id == 0x67B1))) {
-+		smu_data->smc_state_table.MemoryLevel[1].MinVddci =
-+				smu_data->smc_state_table.MemoryLevel[0].MinVddci;
-+		smu_data->smc_state_table.MemoryLevel[1].MinMvdd =
-+				smu_data->smc_state_table.MemoryLevel[0].MinMvdd;
-+	}
-+	smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
-+	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
-+
-+	smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
-+	data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
-+	smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
-+
-+	result = ci_copy_bytes_to_smc(hwmgr,
-+		level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
-+		SMC_RAM_END);
-+
-+	return result;
-+}
-+
-+static int ci_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
-+					SMU7_Discrete_VoltageLevel *voltage)
-+{
-+	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	uint32_t i = 0;
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
-+		/* find mvdd value which clock is more than request */
-+		for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
-+			if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
-+				/* Always round to higher voltage. */
-+				voltage->Voltage = data->mvdd_voltage_table.entries[i].value;
-+				break;
-+			}
-+		}
-+
-+		PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
-+			"MVDD Voltage is outside the supported range.", return -EINVAL);
-+
-+	} else {
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int ci_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
-+	SMU7_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+
-+	SMU7_Discrete_VoltageLevel voltage_level;
-+	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
-+	uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
-+	uint32_t dll_cntl          = data->clock_registers.vDLL_CNTL;
-+	uint32_t mclk_pwrmgt_cntl  = data->clock_registers.vMCLK_PWRMGT_CNTL;
-+
-+
-+	/* The ACPI state should not do DPM on DC (or ever).*/
-+	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
-+
-+	if (data->acpi_vddc)
-+		table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
-+	else
-+		table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
-+
-+	table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1;
-+	/* assign zero for now*/
-+	table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
-+
-+	/* get the engine clock dividers for this clock value*/
-+	result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
-+		table->ACPILevel.SclkFrequency,  &dividers);
-+
-+	PP_ASSERT_WITH_CODE(result == 0,
-+		"Error retrieving Engine Clock dividers from VBIOS.", return result);
-+
-+	/* divider ID for required SCLK*/
-+	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
-+	table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+	table->ACPILevel.DeepSleepDivId = 0;
-+
-+	spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
-+							CG_SPLL_FUNC_CNTL,   SPLL_PWRON,     0);
-+	spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
-+							CG_SPLL_FUNC_CNTL,   SPLL_RESET,     1);
-+	spll_func_cntl_2    = PHM_SET_FIELD(spll_func_cntl_2,
-+							CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL,   4);
-+
-+	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
-+	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
-+	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
-+	table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
-+	table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
-+	table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
-+	table->ACPILevel.CcPwrDynRm = 0;
-+	table->ACPILevel.CcPwrDynRm1 = 0;
-+
-+	/* For various features to be enabled/disabled while this level is active.*/
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
-+	/* SCLK frequency in units of 10KHz*/
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
-+
-+
-+	/* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
-+	table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
-+	table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
-+		table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc;
-+	else {
-+		if (data->acpi_vddci != 0)
-+			table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);
-+		else
-+			table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);
-+	}
-+
-+	if (0 == ci_populate_mvdd_value(hwmgr, 0, &voltage_level))
-+		table->MemoryACPILevel.MinMvdd =
-+			PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
-+	else
-+		table->MemoryACPILevel.MinMvdd = 0;
-+
-+	/* Force reset on DLL*/
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
-+
-+	/* Disable DLL in ACPIState*/
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
-+
-+	/* Enable DLL bypass signal*/
-+	dll_cntl            = PHM_SET_FIELD(dll_cntl,
-+		DLL_CNTL, MRDCK0_BYPASS, 0);
-+	dll_cntl            = PHM_SET_FIELD(dll_cntl,
-+		DLL_CNTL, MRDCK1_BYPASS, 0);
-+
-+	table->MemoryACPILevel.DllCntl            =
-+		PP_HOST_TO_SMC_UL(dll_cntl);
-+	table->MemoryACPILevel.MclkPwrmgtCntl     =
-+		PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
-+	table->MemoryACPILevel.MpllAdFuncCntl     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
-+	table->MemoryACPILevel.MpllDqFuncCntl     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
-+	table->MemoryACPILevel.MpllFuncCntl       =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
-+	table->MemoryACPILevel.MpllFuncCntl_1     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
-+	table->MemoryACPILevel.MpllFuncCntl_2     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
-+	table->MemoryACPILevel.MpllSs1            =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
-+	table->MemoryACPILevel.MpllSs2            =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
-+
-+	table->MemoryACPILevel.EnabledForThrottle = 0;
-+	table->MemoryACPILevel.EnabledForActivity = 0;
-+	table->MemoryACPILevel.UpH = 0;
-+	table->MemoryACPILevel.DownH = 100;
-+	table->MemoryACPILevel.VoltageDownH = 0;
-+	/* Indicates maximum activity level for this performance level.*/
-+	table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
-+
-+	table->MemoryACPILevel.StutterEnable = 0;
-+	table->MemoryACPILevel.StrobeEnable = 0;
-+	table->MemoryACPILevel.EdcReadEnable = 0;
-+	table->MemoryACPILevel.EdcWriteEnable = 0;
-+	table->MemoryACPILevel.RttEnable = 0;
-+
-+	return result;
-+}
-+
-+static int ci_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
-+					SMU7_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_uvd_clock_voltage_dependency_table *uvd_table =
-+		hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
-+
-+	table->UvdLevelCount = (uint8_t)(uvd_table->count);
-+
-+	for (count = 0; count < table->UvdLevelCount; count++) {
-+		table->UvdLevel[count].VclkFrequency =
-+					uvd_table->entries[count].vclk;
-+		table->UvdLevel[count].DclkFrequency =
-+					uvd_table->entries[count].dclk;
-+		table->UvdLevel[count].MinVddc =
-+					uvd_table->entries[count].v * VOLTAGE_SCALE;
-+		table->UvdLevel[count].MinVddcPhases = 1;
-+
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->UvdLevel[count].VclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for Vclk clock", return result);
-+
-+		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
-+
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->UvdLevel[count].DclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for Dclk clock", return result);
-+
-+		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_US(table->UvdLevel[count].MinVddc);
-+	}
-+
-+	return result;
-+}
-+
-+static int ci_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
-+		SMU7_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_vce_clock_voltage_dependency_table *vce_table =
-+				hwmgr->dyn_state.vce_clock_voltage_dependency_table;
-+
-+	table->VceLevelCount = (uint8_t)(vce_table->count);
-+	table->VceBootLevel = 0;
-+
-+	for (count = 0; count < table->VceLevelCount; count++) {
-+		table->VceLevel[count].Frequency = vce_table->entries[count].evclk;
-+		table->VceLevel[count].MinVoltage =
-+				vce_table->entries[count].v * VOLTAGE_SCALE;
-+		table->VceLevel[count].MinPhases = 1;
-+
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->VceLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for VCE engine clock",
-+				return result);
-+
-+		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_US(table->VceLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int ci_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
-+					SMU7_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_acp_clock_voltage_dependency_table *acp_table =
-+				hwmgr->dyn_state.acp_clock_voltage_dependency_table;
-+
-+	table->AcpLevelCount = (uint8_t)(acp_table->count);
-+	table->AcpBootLevel = 0;
-+
-+	for (count = 0; count < table->AcpLevelCount; count++) {
-+		table->AcpLevel[count].Frequency = acp_table->entries[count].acpclk;
-+		table->AcpLevel[count].MinVoltage = acp_table->entries[count].v;
-+		table->AcpLevel[count].MinPhases = 1;
-+
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->AcpLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for engine clock", return result);
-+
-+		table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_US(table->AcpLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int ci_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-+					SMU7_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_samu_clock_voltage_dependency_table *samu_table =
-+				hwmgr->dyn_state.samu_clock_voltage_dependency_table;
-+
-+	table->SamuBootLevel = 0;
-+	table->SamuLevelCount = (uint8_t)(samu_table->count);
-+
-+	for (count = 0; count < table->SamuLevelCount; count++) {
-+		table->SamuLevel[count].Frequency = samu_table->entries[count].samclk;
-+		table->SamuLevel[count].MinVoltage = samu_table->entries[count].v * VOLTAGE_SCALE;
-+		table->SamuLevel[count].MinPhases = 1;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->SamuLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for samu clock", return result);
-+
-+		table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_US(table->SamuLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int ci_populate_memory_timing_parameters(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t engine_clock,
-+		uint32_t memory_clock,
-+		struct SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs
-+		)
-+{
-+	uint32_t dramTiming;
-+	uint32_t dramTiming2;
-+	uint32_t burstTime;
-+	int result;
-+
-+	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
-+				engine_clock, memory_clock);
-+
-+	PP_ASSERT_WITH_CODE(result == 0,
-+		"Error calling VBIOS to set DRAM_TIMING.", return result);
-+
-+	dramTiming  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
-+	dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
-+	burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
-+
-+	arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dramTiming);
-+	arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
-+	arb_regs->McArbBurstTime = (uint8_t)burstTime;
-+
-+	return 0;
-+}
-+
-+static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	int result = 0;
-+	SMU7_Discrete_MCArbDramTimingTable  arb_regs;
-+	uint32_t i, j;
-+
-+	memset(&arb_regs, 0x00, sizeof(SMU7_Discrete_MCArbDramTimingTable));
-+
-+	for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
-+		for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
-+			result = ci_populate_memory_timing_parameters
-+				(hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
-+				 data->dpm_table.mclk_table.dpm_levels[j].value,
-+				 &arb_regs.entries[i][j]);
-+
-+			if (0 != result)
-+				break;
-+		}
-+	}
-+
-+	if (0 == result) {
-+		result = ci_copy_bytes_to_smc(
-+				hwmgr,
-+				smu_data->arb_table_start,
-+				(uint8_t *)&arb_regs,
-+				sizeof(SMU7_Discrete_MCArbDramTimingTable),
-+				SMC_RAM_END
-+				);
-+	}
-+
-+	return result;
-+}
-+
-+static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
-+			SMU7_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+
-+	table->GraphicsBootLevel = 0;
-+	table->MemoryBootLevel = 0;
-+
-+	/* find boot level from dpm table*/
-+	result = phm_find_boot_level(&(data->dpm_table.sclk_table),
-+			data->vbios_boot_state.sclk_bootup_value,
-+			(uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
-+
-+	if (0 != result) {
-+		smu_data->smc_state_table.GraphicsBootLevel = 0;
-+		pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n");
-+		result = 0;
-+	}
-+
-+	result = phm_find_boot_level(&(data->dpm_table.mclk_table),
-+		data->vbios_boot_state.mclk_bootup_value,
-+		(uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
-+
-+	if (0 != result) {
-+		smu_data->smc_state_table.MemoryBootLevel = 0;
-+		pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n");
-+		result = 0;
-+	}
-+
-+	table->BootVddc = data->vbios_boot_state.vddc_bootup_value;
-+	table->BootVddci = data->vbios_boot_state.vddci_bootup_value;
-+	table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
-+
-+	return result;
-+}
-+
-+static int ci_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
-+				 SMU7_Discrete_MCRegisters *mc_reg_table)
-+{
-+	const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smu_backend;
-+
-+	uint32_t i, j;
-+
-+	for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
-+		if (smu_data->mc_reg_table.validflag & 1<<j) {
-+			PP_ASSERT_WITH_CODE(i < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE,
-+				"Index of mc_reg_table->address[] array out of boundary", return -EINVAL);
-+			mc_reg_table->address[i].s0 =
-+				PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
-+			mc_reg_table->address[i].s1 =
-+				PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
-+			i++;
-+		}
-+	}
-+
-+	mc_reg_table->last = (uint8_t)i;
-+
-+	return 0;
-+}
-+
-+static void ci_convert_mc_registers(
-+	const struct ci_mc_reg_entry *entry,
-+	SMU7_Discrete_MCRegisterSet *data,
-+	uint32_t num_entries, uint32_t valid_flag)
-+{
-+	uint32_t i, j;
-+
-+	for (i = 0, j = 0; j < num_entries; j++) {
-+		if (valid_flag & 1<<j) {
-+			data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
-+			i++;
-+		}
-+	}
-+}
-+
-+static int ci_convert_mc_reg_table_entry_to_smc(
-+		struct pp_hwmgr *hwmgr,
-+		const uint32_t memory_clock,
-+		SMU7_Discrete_MCRegisterSet *mc_reg_table_data
-+		)
-+{
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	uint32_t i = 0;
-+
-+	for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
-+		if (memory_clock <=
-+			smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
-+			break;
-+		}
-+	}
-+
-+	if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
-+		--i;
-+
-+	ci_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
-+				mc_reg_table_data, smu_data->mc_reg_table.last,
-+				smu_data->mc_reg_table.validflag);
-+
-+	return 0;
-+}
-+
-+static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
-+		SMU7_Discrete_MCRegisters *mc_regs)
-+{
-+	int result = 0;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	int res;
-+	uint32_t i;
-+
-+	for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
-+		res = ci_convert_mc_reg_table_entry_to_smc(
-+				hwmgr,
-+				data->dpm_table.mclk_table.dpm_levels[i].value,
-+				&mc_regs->data[i]
-+				);
-+
-+		if (0 != res)
-+			result = res;
-+	}
-+
-+	return result;
-+}
-+
-+static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t address;
-+	int32_t result;
-+
-+	if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
-+		return 0;
-+
-+
-+	memset(&smu_data->mc_regs, 0, sizeof(SMU7_Discrete_MCRegisters));
-+
-+	result = ci_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
-+
-+	if (result != 0)
-+		return result;
-+
-+	address = smu_data->mc_reg_table_start + (uint32_t)offsetof(SMU7_Discrete_MCRegisters, data[0]);
-+
-+	return  ci_copy_bytes_to_smc(hwmgr, address,
-+				 (uint8_t *)&smu_data->mc_regs.data[0],
-+				sizeof(SMU7_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
-+				SMC_RAM_END);
-+}
-+
-+static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+
-+	memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters));
-+	result = ci_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize MCRegTable for the MC register addresses!", return result;);
-+
-+	result = ci_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize MCRegTable for driver state!", return result;);
-+
-+	return ci_copy_bytes_to_smc(hwmgr, smu_data->mc_reg_table_start,
-+			(uint8_t *)&smu_data->mc_regs, sizeof(SMU7_Discrete_MCRegisters), SMC_RAM_END);
-+}
-+
-+static int ci_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	uint8_t count, level;
-+
-+	count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
-+
-+	for (level = 0; level < count; level++) {
-+		if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk
-+			 >= data->vbios_boot_state.sclk_bootup_value) {
-+			smu_data->smc_state_table.GraphicsBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
-+
-+	for (level = 0; level < count; level++) {
-+		if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
-+			>= data->vbios_boot_state.mclk_bootup_value) {
-+			smu_data->smc_state_table.MemoryBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int ci_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
-+					    SMU7_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
-+		table->SVI2Enable = 1;
-+	else
-+		table->SVI2Enable = 0;
-+	return 0;
-+}
-+
-+static int ci_start_smc(struct pp_hwmgr *hwmgr)
-+{
-+	/* set smc instruct start point at 0x0 */
-+	ci_program_jump_on_start(hwmgr);
-+
-+	/* enable smc clock */
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
-+
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
-+
-+	PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
-+				 INTERRUPTS_ENABLED, 1);
-+
-+	return 0;
-+}
-+
-+static int ci_init_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	SMU7_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
-+	struct pp_atomctrl_gpio_pin_assignment gpio_pin;
-+	u32 i;
-+
-+	ci_initialize_power_tune_defaults(hwmgr);
-+	memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control)
-+		ci_populate_smc_voltage_tables(hwmgr, table);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-+
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StepVddc))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
-+
-+	if (data->is_memory_gddr5)
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
-+
-+	if (data->ulv_supported) {
-+		result = ci_populate_ulv_state(hwmgr, &(table->Ulv));
-+		PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize ULV state!", return result);
-+
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_ULV_PARAMETER, 0x40035);
-+	}
-+
-+	result = ci_populate_all_graphic_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize Graphics Level!", return result);
-+
-+	result = ci_populate_all_memory_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize Memory Level!", return result);
-+
-+	result = ci_populate_smc_link_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize Link Level!", return result);
-+
-+	result = ci_populate_smc_acpi_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize ACPI Level!", return result);
-+
-+	result = ci_populate_smc_vce_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize VCE Level!", return result);
-+
-+	result = ci_populate_smc_acp_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize ACP Level!", return result);
-+
-+	result = ci_populate_smc_samu_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize SAMU Level!", return result);
-+
-+	/* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
-+	/* need to populate the  ARB settings for the initial state. */
-+	result = ci_program_memory_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to Write ARB settings for the initial state.", return result);
-+
-+	result = ci_populate_smc_uvd_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize UVD Level!", return result);
-+
-+	table->UvdBootLevel  = 0;
-+	table->VceBootLevel  = 0;
-+	table->AcpBootLevel  = 0;
-+	table->SamuBootLevel  = 0;
-+
-+	table->GraphicsBootLevel = 0;
-+	table->MemoryBootLevel = 0;
-+
-+	result = ci_populate_smc_boot_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize Boot Level!", return result);
-+
-+	result = ci_populate_smc_initial_state(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);
-+
-+	result = ci_populate_bapm_parameters_in_dpm_table(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);
-+
-+	table->UVDInterval = 1;
-+	table->VCEInterval = 1;
-+	table->ACPInterval = 1;
-+	table->SAMUInterval = 1;
-+	table->GraphicsVoltageChangeEnable  = 1;
-+	table->GraphicsThermThrottleEnable  = 1;
-+	table->GraphicsInterval = 1;
-+	table->VoltageInterval  = 1;
-+	table->ThermalInterval  = 1;
-+
-+	table->TemperatureLimitHigh =
-+		(data->thermal_temp_setting.temperature_high *
-+		 SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+	table->TemperatureLimitLow =
-+		(data->thermal_temp_setting.temperature_low *
-+		SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+
-+	table->MemoryVoltageChangeEnable  = 1;
-+	table->MemoryInterval  = 1;
-+	table->VoltageResponseTime  = 0;
-+	table->VddcVddciDelta = 4000;
-+	table->PhaseResponseTime  = 0;
-+	table->MemoryThermThrottleEnable  = 1;
-+
-+	PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
-+			"There must be 1 or more PCIE levels defined in PPTable.",
-+			return -EINVAL);
-+
-+	table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count;
-+	table->PCIeGenInterval = 1;
-+
-+	ci_populate_smc_svi2_config(hwmgr, table);
-+
-+	for (i = 0; i < SMU7_MAX_ENTRIES_SMIO; i++)
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->Smio[i]);
-+
-+	table->ThermGpio  = 17;
-+	table->SclkStepSize = 0x4000;
-+	if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
-+		table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_RegulatorHot);
-+	} else {
-+		table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_RegulatorHot);
-+	}
-+
-+	table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
-+	table->VddcVddciDelta = PP_HOST_TO_SMC_US(table->VddcVddciDelta);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
-+
-+	table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE);
-+	table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE);
-+	table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
-+
-+	/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
-+	result = ci_copy_bytes_to_smc(hwmgr, smu_data->dpm_table_start +
-+					offsetof(SMU7_Discrete_DpmTable, SystemFlags),
-+					(uint8_t *)&(table->SystemFlags),
-+					sizeof(SMU7_Discrete_DpmTable)-3 * sizeof(SMU7_PIDController),
-+					SMC_RAM_END);
-+
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to upload dpm data to SMC memory!", return result;);
-+
-+	result = ci_populate_initial_mc_reg_table(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+		"Failed to populate initialize MC Reg table!", return result);
-+
-+	result = ci_populate_pm_fuses(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to  populate PM fuses to SMC memory!", return result);
-+
-+	ci_start_smc(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
-+	uint32_t duty100;
-+	uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
-+	uint16_t fdo_min, slope1, slope2;
-+	uint32_t reference_clock;
-+	int res;
-+	uint64_t tmp64;
-+
-+	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
-+		return 0;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	if (0 == ci_data->fan_table_start) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
-+
-+	if (0 == duty100) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
-+	do_div(tmp64, 10000);
-+	fdo_min = (uint16_t)tmp64;
-+
-+	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
-+	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
-+
-+	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
-+	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
-+
-+	slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
-+	slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
-+
-+	fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
-+	fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
-+	fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
-+
-+	fan_table.Slope1 = cpu_to_be16(slope1);
-+	fan_table.Slope2 = cpu_to_be16(slope2);
-+
-+	fan_table.FdoMin = cpu_to_be16(fdo_min);
-+
-+	fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
-+
-+	fan_table.HystUp = cpu_to_be16(1);
-+
-+	fan_table.HystSlope = cpu_to_be16(1);
-+
-+	fan_table.TempRespLim = cpu_to_be16(5);
-+
-+	reference_clock = smu7_get_xclk(hwmgr);
-+
-+	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
-+
-+	fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
-+
-+	fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
-+
-+	res = ci_copy_bytes_to_smc(hwmgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
-+
-+	return 0;
-+}
-+
-+static int ci_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	if (data->need_update_smu7_dpm_table &
-+			(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
-+		return ci_program_memory_timing_parameters(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+
-+	int result = 0;
-+	uint32_t low_sclk_interrupt_threshold = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkThrottleLowNotification)
-+		&& (hwmgr->gfx_arbiter.sclk_threshold !=
-+				data->low_sclk_interrupt_threshold)) {
-+		data->low_sclk_interrupt_threshold =
-+				hwmgr->gfx_arbiter.sclk_threshold;
-+		low_sclk_interrupt_threshold =
-+				data->low_sclk_interrupt_threshold;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
-+
-+		result = ci_copy_bytes_to_smc(
-+				hwmgr,
-+				smu_data->dpm_table_start +
-+				offsetof(SMU7_Discrete_DpmTable,
-+					LowSclkInterruptT),
-+				(uint8_t *)&low_sclk_interrupt_threshold,
-+				sizeof(uint32_t),
-+				SMC_RAM_END);
-+	}
-+
-+	result = ci_update_and_upload_mc_reg_table(hwmgr);
-+
-+	PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);
-+
-+	result = ci_program_mem_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			"Failed to program memory timing parameters!",
-+			);
-+
-+	return result;
-+}
-+
-+static uint32_t ci_get_offsetof(uint32_t type, uint32_t member)
-+{
-+	switch (type) {
-+	case SMU_SoftRegisters:
-+		switch (member) {
-+		case HandshakeDisables:
-+			return offsetof(SMU7_SoftRegisters, HandshakeDisables);
-+		case VoltageChangeTimeout:
-+			return offsetof(SMU7_SoftRegisters, VoltageChangeTimeout);
-+		case AverageGraphicsActivity:
-+			return offsetof(SMU7_SoftRegisters, AverageGraphicsA);
-+		case PreVBlankGap:
-+			return offsetof(SMU7_SoftRegisters, PreVBlankGap);
-+		case VBlankTimeout:
-+			return offsetof(SMU7_SoftRegisters, VBlankTimeout);
-+		case DRAM_LOG_ADDR_H:
-+			return offsetof(SMU7_SoftRegisters, DRAM_LOG_ADDR_H);
-+		case DRAM_LOG_ADDR_L:
-+			return offsetof(SMU7_SoftRegisters, DRAM_LOG_ADDR_L);
-+		case DRAM_LOG_PHY_ADDR_H:
-+			return offsetof(SMU7_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
-+		case DRAM_LOG_PHY_ADDR_L:
-+			return offsetof(SMU7_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
-+		case DRAM_LOG_BUFF_SIZE:
-+			return offsetof(SMU7_SoftRegisters, DRAM_LOG_BUFF_SIZE);
-+		}
-+	case SMU_Discrete_DpmTable:
-+		switch (member) {
-+		case LowSclkInterruptThreshold:
-+			return offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT);
-+		}
-+	}
-+	pr_debug("can't get the offset of type %x member %x\n", type, member);
-+	return 0;
-+}
-+
-+static uint32_t ci_get_mac_definition(uint32_t value)
-+{
-+	switch (value) {
-+	case SMU_MAX_LEVELS_GRAPHICS:
-+		return SMU7_MAX_LEVELS_GRAPHICS;
-+	case SMU_MAX_LEVELS_MEMORY:
-+		return SMU7_MAX_LEVELS_MEMORY;
-+	case SMU_MAX_LEVELS_LINK:
-+		return SMU7_MAX_LEVELS_LINK;
-+	case SMU_MAX_ENTRIES_SMIO:
-+		return SMU7_MAX_ENTRIES_SMIO;
-+	case SMU_MAX_LEVELS_VDDC:
-+		return SMU7_MAX_LEVELS_VDDC;
-+	case SMU_MAX_LEVELS_VDDCI:
-+		return SMU7_MAX_LEVELS_VDDCI;
-+	case SMU_MAX_LEVELS_MVDD:
-+		return SMU7_MAX_LEVELS_MVDD;
-+	}
-+
-+	pr_debug("can't get the mac of %x\n", value);
-+	return 0;
-+}
-+
-+static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t byte_count, start_addr;
-+	uint8_t *src;
-+	uint32_t data;
-+
-+	struct cgs_firmware_info info = {0};
-+
-+	cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
-+
-+	hwmgr->is_kicker = info.is_kicker;
-+	byte_count = info.image_size;
-+	src = (uint8_t *)info.kptr;
-+	start_addr = info.ucode_start_address;
-+
-+	if  (byte_count > SMC_RAM_END) {
-+		pr_err("SMC address is beyond the SMC RAM area.\n");
-+		return -EINVAL;
-+	}
-+
-+	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
-+	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
-+
-+	for (; byte_count >= 4; byte_count -= 4) {
-+		data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
-+		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
-+		src += 4;
-+	}
-+	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
-+
-+	if (0 != byte_count) {
-+		pr_err("SMC size must be divisible by 4\n");
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int ci_upload_firmware(struct pp_hwmgr *hwmgr)
-+{
-+	if (ci_is_smc_ram_running(hwmgr)) {
-+		pr_info("smc is running, no need to load smc firmware\n");
-+		return 0;
-+	}
-+	PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
-+			boot_seq_done, 1);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_MISC_CNTL,
-+			pre_fetcher_en, 1);
-+
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
-+	return ci_load_smc_ucode(hwmgr);
-+}
-+
-+static int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+
-+	uint32_t tmp = 0;
-+	int result;
-+	bool error = false;
-+
-+	if (ci_upload_firmware(hwmgr))
-+		return -EINVAL;
-+
-+	result = ci_read_smc_sram_dword(hwmgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU7_Firmware_Header, DpmTable),
-+				&tmp, SMC_RAM_END);
-+
-+	if (0 == result)
-+		ci_data->dpm_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = ci_read_smc_sram_dword(hwmgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU7_Firmware_Header, SoftRegisters),
-+				&tmp, SMC_RAM_END);
-+
-+	if (0 == result) {
-+		data->soft_regs_start = tmp;
-+		ci_data->soft_regs_start = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+	result = ci_read_smc_sram_dword(hwmgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU7_Firmware_Header, mcRegisterTable),
-+				&tmp, SMC_RAM_END);
-+
-+	if (0 == result)
-+		ci_data->mc_reg_table_start = tmp;
-+
-+	result = ci_read_smc_sram_dword(hwmgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU7_Firmware_Header, FanTable),
-+				&tmp, SMC_RAM_END);
-+
-+	if (0 == result)
-+		ci_data->fan_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = ci_read_smc_sram_dword(hwmgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
-+				&tmp, SMC_RAM_END);
-+
-+	if (0 == result)
-+		ci_data->arb_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = ci_read_smc_sram_dword(hwmgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU7_Firmware_Header, Version),
-+				&tmp, SMC_RAM_END);
-+
-+	if (0 == result)
-+		hwmgr->microcode_version_info.SMC = tmp;
-+
-+	error |= (0 != result);
-+
-+	return error ? 1 : 0;
-+}
-+
-+static uint8_t ci_get_memory_modile_index(struct pp_hwmgr *hwmgr)
-+{
-+	return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
-+}
-+
-+static bool ci_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
-+{
-+	bool result = true;
-+
-+	switch (in_reg) {
-+	case  mmMC_SEQ_RAS_TIMING:
-+		*out_reg = mmMC_SEQ_RAS_TIMING_LP;
-+		break;
-+
-+	case  mmMC_SEQ_DLL_STBY:
-+		*out_reg = mmMC_SEQ_DLL_STBY_LP;
-+		break;
-+
-+	case  mmMC_SEQ_G5PDX_CMD0:
-+		*out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
-+		break;
-+
-+	case  mmMC_SEQ_G5PDX_CMD1:
-+		*out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
-+		break;
-+
-+	case  mmMC_SEQ_G5PDX_CTRL:
-+		*out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
-+		break;
-+
-+	case mmMC_SEQ_CAS_TIMING:
-+		*out_reg = mmMC_SEQ_CAS_TIMING_LP;
-+		break;
-+
-+	case mmMC_SEQ_MISC_TIMING:
-+		*out_reg = mmMC_SEQ_MISC_TIMING_LP;
-+		break;
-+
-+	case mmMC_SEQ_MISC_TIMING2:
-+		*out_reg = mmMC_SEQ_MISC_TIMING2_LP;
-+		break;
-+
-+	case mmMC_SEQ_PMG_DVS_CMD:
-+		*out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
-+		break;
-+
-+	case mmMC_SEQ_PMG_DVS_CTL:
-+		*out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
-+		break;
-+
-+	case mmMC_SEQ_RD_CTL_D0:
-+		*out_reg = mmMC_SEQ_RD_CTL_D0_LP;
-+		break;
-+
-+	case mmMC_SEQ_RD_CTL_D1:
-+		*out_reg = mmMC_SEQ_RD_CTL_D1_LP;
-+		break;
-+
-+	case mmMC_SEQ_WR_CTL_D0:
-+		*out_reg = mmMC_SEQ_WR_CTL_D0_LP;
-+		break;
-+
-+	case mmMC_SEQ_WR_CTL_D1:
-+		*out_reg = mmMC_SEQ_WR_CTL_D1_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_EMRS:
-+		*out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_MRS:
-+		*out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_MRS1:
-+		*out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
-+		break;
-+
-+	case mmMC_SEQ_PMG_TIMING:
-+		*out_reg = mmMC_SEQ_PMG_TIMING_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_MRS2:
-+		*out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
-+		break;
-+
-+	case mmMC_SEQ_WR_CTL_2:
-+		*out_reg = mmMC_SEQ_WR_CTL_2_LP;
-+		break;
-+
-+	default:
-+		result = false;
-+		break;
-+	}
-+
-+	return result;
-+}
-+
-+static int ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
-+{
-+	uint32_t i;
-+	uint16_t address;
-+
-+	for (i = 0; i < table->last; i++) {
-+		table->mc_reg_address[i].s0 =
-+			ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
-+			? address : table->mc_reg_address[i].s1;
-+	}
-+	return 0;
-+}
-+
-+static int ci_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
-+					struct ci_mc_reg_table *ni_table)
-+{
-+	uint8_t i, j;
-+
-+	PP_ASSERT_WITH_CODE((table->last <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+		"Invalid VramInfo table.", return -EINVAL);
-+	PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
-+		"Invalid VramInfo table.", return -EINVAL);
-+
-+	for (i = 0; i < table->last; i++)
-+		ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
-+
-+	ni_table->last = table->last;
-+
-+	for (i = 0; i < table->num_entries; i++) {
-+		ni_table->mc_reg_table_entry[i].mclk_max =
-+			table->mc_reg_table_entry[i].mclk_max;
-+		for (j = 0; j < table->last; j++) {
-+			ni_table->mc_reg_table_entry[i].mc_data[j] =
-+				table->mc_reg_table_entry[i].mc_data[j];
-+		}
-+	}
-+
-+	ni_table->num_entries = table->num_entries;
-+
-+	return 0;
-+}
-+
-+static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr,
-+					struct ci_mc_reg_table *table)
-+{
-+	uint8_t i, j, k;
-+	uint32_t temp_reg;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	for (i = 0, j = table->last; i < table->last; i++) {
-+		PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+			"Invalid VramInfo table.", return -EINVAL);
-+
-+		switch (table->mc_reg_address[i].s1) {
-+
-+		case mmMC_SEQ_MISC1:
-+			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
-+			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
-+			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
-+			for (k = 0; k < table->num_entries; k++) {
-+				table->mc_reg_table_entry[k].mc_data[j] =
-+					((temp_reg & 0xffff0000)) |
-+					((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
-+			}
-+			j++;
-+			PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+				"Invalid VramInfo table.", return -EINVAL);
-+
-+			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
-+			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
-+			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
-+			for (k = 0; k < table->num_entries; k++) {
-+				table->mc_reg_table_entry[k].mc_data[j] =
-+					(temp_reg & 0xffff0000) |
-+					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
-+
-+				if (!data->is_memory_gddr5)
-+					table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
-+			}
-+			j++;
-+			PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+				"Invalid VramInfo table.", return -EINVAL);
-+
-+			if (!data->is_memory_gddr5 && j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) {
-+				table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
-+				table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
-+				for (k = 0; k < table->num_entries; k++) {
-+					table->mc_reg_table_entry[k].mc_data[j] =
-+						(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
-+				}
-+				j++;
-+				PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+					"Invalid VramInfo table.", return -EINVAL);
-+			}
-+
-+			break;
-+
-+		case mmMC_SEQ_RESERVE_M:
-+			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
-+			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
-+			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
-+			for (k = 0; k < table->num_entries; k++) {
-+				table->mc_reg_table_entry[k].mc_data[j] =
-+					(temp_reg & 0xffff0000) |
-+					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
-+			}
-+			j++;
-+			PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+				"Invalid VramInfo table.", return -EINVAL);
-+			break;
-+
-+		default:
-+			break;
-+		}
-+
-+	}
-+
-+	table->last = j;
-+
-+	return 0;
-+}
-+
-+static int ci_set_valid_flag(struct ci_mc_reg_table *table)
-+{
-+	uint8_t i, j;
-+
-+	for (i = 0; i < table->last; i++) {
-+		for (j = 1; j < table->num_entries; j++) {
-+			if (table->mc_reg_table_entry[j-1].mc_data[i] !=
-+				table->mc_reg_table_entry[j].mc_data[i]) {
-+				table->validflag |= (1 << i);
-+				break;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
-+	pp_atomctrl_mc_reg_table *table;
-+	struct ci_mc_reg_table *ni_table = &smu_data->mc_reg_table;
-+	uint8_t module_index = ci_get_memory_modile_index(hwmgr);
-+
-+	table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
-+
-+	if (NULL == table)
-+		return -ENOMEM;
-+
-+	/* Program additional LP registers that are no longer programmed by VBIOS */
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
-+
-+	memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
-+
-+	result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
-+
-+	if (0 == result)
-+		result = ci_copy_vbios_smc_reg_table(table, ni_table);
-+
-+	if (0 == result) {
-+		ci_set_s0_mc_reg_index(ni_table);
-+		result = ci_set_mc_special_registers(hwmgr, ni_table);
-+	}
-+
-+	if (0 == result)
-+		ci_set_valid_flag(ni_table);
-+
-+	kfree(table);
-+
-+	return result;
-+}
-+
-+static bool ci_is_dpm_running(struct pp_hwmgr *hwmgr)
-+{
-+	return ci_is_smc_ram_running(hwmgr);
-+}
-+
-+static int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
-+						struct amd_pp_profile *request)
-+{
-+	struct ci_smumgr *smu_data = (struct ci_smumgr *)
-+			(hwmgr->smu_backend);
-+	struct SMU7_Discrete_GraphicsLevel *levels =
-+			smu_data->smc_state_table.GraphicsLevel;
-+	uint32_t array = smu_data->dpm_table_start +
-+			offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
-+	uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) *
-+			SMU7_MAX_LEVELS_GRAPHICS;
-+	uint32_t i;
-+
-+	for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
-+		levels[i].ActivityLevel =
-+				cpu_to_be16(request->activity_threshold);
-+		levels[i].EnabledForActivity = 1;
-+		levels[i].UpH = request->up_hyst;
-+		levels[i].DownH = request->down_hyst;
-+	}
-+
-+	return ci_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
-+				array_size, SMC_RAM_END);
-+}
-+
-+
-+static int ci_smu_init(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct ci_smumgr *ci_priv = NULL;
-+
-+	ci_priv = kzalloc(sizeof(struct ci_smumgr), GFP_KERNEL);
-+
-+	if (ci_priv == NULL)
-+		return -ENOMEM;
-+
-+	for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
-+		ci_priv->activity_target[i] = 30;
-+
-+	hwmgr->smu_backend = ci_priv;
-+
-+	return 0;
-+}
-+
-+static int ci_smu_fini(struct pp_hwmgr *hwmgr)
-+{
-+	kfree(hwmgr->smu_backend);
-+	hwmgr->smu_backend = NULL;
-+	cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
-+	return 0;
-+}
-+
-+static int ci_start_smu(struct pp_hwmgr *hwmgr)
-+{
-+	return 0;
-+}
-+
-+const struct pp_smumgr_func ci_smu_funcs = {
-+	.smu_init = ci_smu_init,
-+	.smu_fini = ci_smu_fini,
-+	.start_smu = ci_start_smu,
-+	.check_fw_load_finish = NULL,
-+	.request_smu_load_fw = NULL,
-+	.request_smu_load_specific_fw = NULL,
-+	.send_msg_to_smc = ci_send_msg_to_smc,
-+	.send_msg_to_smc_with_parameter = ci_send_msg_to_smc_with_parameter,
-+	.download_pptable_settings = NULL,
-+	.upload_pptable_settings = NULL,
-+	.get_offsetof = ci_get_offsetof,
-+	.process_firmware_header = ci_process_firmware_header,
-+	.init_smc_table = ci_init_smc_table,
-+	.update_sclk_threshold = ci_update_sclk_threshold,
-+	.thermal_setup_fan_table = ci_thermal_setup_fan_table,
-+	.populate_all_graphic_levels = ci_populate_all_graphic_levels,
-+	.populate_all_memory_levels = ci_populate_all_memory_levels,
-+	.get_mac_definition = ci_get_mac_definition,
-+	.initialize_mc_reg_table = ci_initialize_mc_reg_table,
-+	.is_dpm_running = ci_is_dpm_running,
-+	.populate_requested_graphic_levels = ci_populate_requested_graphic_levels,
-+};
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h.0130~	2017-12-14 06:39:58.481903613 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.h	2017-12-14 06:39:58.481903613 +0100
-@@ -0,0 +1,78 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifndef _CI_SMUMANAGER_H_
-+#define _CI_SMUMANAGER_H_
-+
-+#define SMU__NUM_SCLK_DPM_STATE  8
-+#define SMU__NUM_MCLK_DPM_LEVELS 6
-+#define SMU__NUM_LCLK_DPM_LEVELS 8
-+#define SMU__NUM_PCIE_DPM_LEVELS 8
-+
-+#include "smu7_discrete.h"
-+#include <pp_endian.h>
-+#include "ppatomctrl.h"
-+
-+struct ci_pt_defaults {
-+	u8 svi_load_line_en;
-+	u8 svi_load_line_vddc;
-+	u8 tdc_vddc_throttle_release_limit_perc;
-+	u8 tdc_mawt;
-+	u8 tdc_waterfall_ctl;
-+	u8 dte_ambient_temp_base;
-+	u32 display_cac;
-+	u32 bapm_temp_gradient;
-+	u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
-+	u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
-+};
-+
-+struct ci_mc_reg_entry {
-+	uint32_t mclk_max;
-+	uint32_t mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
-+};
-+
-+struct ci_mc_reg_table {
-+	uint8_t   last;
-+	uint8_t   num_entries;
-+	uint16_t  validflag;
-+	struct ci_mc_reg_entry    mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
-+	SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
-+};
-+
-+struct ci_smumgr {
-+	uint32_t                             soft_regs_start;
-+	uint32_t                             dpm_table_start;
-+	uint32_t                             mc_reg_table_start;
-+	uint32_t                             fan_table_start;
-+	uint32_t                             arb_table_start;
-+	uint32_t                             ulv_setting_starts;
-+	struct SMU7_Discrete_DpmTable       smc_state_table;
-+	struct SMU7_Discrete_PmFuses  power_tune_table;
-+	const struct ci_pt_defaults  *power_tune_defaults;
-+	SMU7_Discrete_MCRegisters      mc_regs;
-+	struct ci_mc_reg_table mc_reg_table;
-+	uint32_t        activity_target[SMU7_MAX_LEVELS_GRAPHICS];
-+
-+};
-+
-+#endif
-+
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c	2017-12-14 06:39:58.481903613 +0100
-@@ -52,53 +52,52 @@ static const enum cz_scratch_entry firmw
- 	CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
- };
- 
--static int cz_smum_get_argument(struct pp_smumgr *smumgr)
-+static int cz_smum_get_argument(struct pp_hwmgr *hwmgr)
- {
--	if (smumgr == NULL || smumgr->device == NULL)
-+	if (hwmgr == NULL || hwmgr->device == NULL)
- 		return -EINVAL;
- 
--	return cgs_read_register(smumgr->device,
-+	return cgs_read_register(hwmgr->device,
- 					mmSMU_MP1_SRBM2P_ARG_0);
- }
- 
--static int cz_send_msg_to_smc_async(struct pp_smumgr *smumgr,
--								uint16_t msg)
-+static int cz_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg)
- {
- 	int result = 0;
- 
--	if (smumgr == NULL || smumgr->device == NULL)
-+	if (hwmgr == NULL || hwmgr->device == NULL)
- 		return -EINVAL;
- 
--	result = SMUM_WAIT_FIELD_UNEQUAL(smumgr,
-+	result = PHM_WAIT_FIELD_UNEQUAL(hwmgr,
- 					SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
- 	if (result != 0) {
- 		pr_err("cz_send_msg_to_smc_async (0x%04x) failed\n", msg);
- 		return result;
- 	}
- 
--	cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0);
--	cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg);
-+	cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0);
-+	cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg);
- 
- 	return 0;
- }
- 
- /* Send a message to the SMC, and wait for its response.*/
--static int cz_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
-+static int cz_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
- {
- 	int result = 0;
- 
--	result = cz_send_msg_to_smc_async(smumgr, msg);
-+	result = cz_send_msg_to_smc_async(hwmgr, msg);
- 	if (result != 0)
- 		return result;
- 
--	return SMUM_WAIT_FIELD_UNEQUAL(smumgr,
-+	return PHM_WAIT_FIELD_UNEQUAL(hwmgr,
- 					SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
- }
- 
--static int cz_set_smc_sram_address(struct pp_smumgr *smumgr,
-+static int cz_set_smc_sram_address(struct pp_hwmgr *hwmgr,
- 				     uint32_t smc_address, uint32_t limit)
- {
--	if (smumgr == NULL || smumgr->device == NULL)
-+	if (hwmgr == NULL || hwmgr->device == NULL)
- 		return -EINVAL;
- 
- 	if (0 != (3 & smc_address)) {
-@@ -111,39 +110,39 @@ static int cz_set_smc_sram_address(struc
- 		return -EINVAL;
- 	}
- 
--	cgs_write_register(smumgr->device, mmMP0PUB_IND_INDEX_0,
-+	cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX_0,
- 				SMN_MP1_SRAM_START_ADDR + smc_address);
- 
- 	return 0;
- }
- 
--static int cz_write_smc_sram_dword(struct pp_smumgr *smumgr,
-+static int cz_write_smc_sram_dword(struct pp_hwmgr *hwmgr,
- 		uint32_t smc_address, uint32_t value, uint32_t limit)
- {
- 	int result;
- 
--	if (smumgr == NULL || smumgr->device == NULL)
-+	if (hwmgr == NULL || hwmgr->device == NULL)
- 		return -EINVAL;
- 
--	result = cz_set_smc_sram_address(smumgr, smc_address, limit);
-+	result = cz_set_smc_sram_address(hwmgr, smc_address, limit);
- 	if (!result)
--		cgs_write_register(smumgr->device, mmMP0PUB_IND_DATA_0, value);
-+		cgs_write_register(hwmgr->device, mmMP0PUB_IND_DATA_0, value);
- 
- 	return result;
- }
- 
--static int cz_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
-+static int cz_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
- 					  uint16_t msg, uint32_t parameter)
- {
--	if (smumgr == NULL || smumgr->device == NULL)
-+	if (hwmgr == NULL || hwmgr->device == NULL)
- 		return -EINVAL;
- 
--	cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
-+	cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
- 
--	return cz_send_msg_to_smc(smumgr, msg);
-+	return cz_send_msg_to_smc(hwmgr, msg);
- }
- 
--static int cz_check_fw_load_finish(struct pp_smumgr *smumgr,
-+static int cz_check_fw_load_finish(struct pp_hwmgr *hwmgr,
- 				   uint32_t firmware)
- {
- 	int i;
-@@ -151,19 +150,19 @@ static int cz_check_fw_load_finish(struc
- 			 SMU8_FIRMWARE_HEADER_LOCATION +
- 			 offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
- 
--	if (smumgr == NULL || smumgr->device == NULL)
-+	if (hwmgr == NULL || hwmgr->device == NULL)
- 		return -EINVAL;
- 
--	cgs_write_register(smumgr->device, mmMP0PUB_IND_INDEX, index);
-+	cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
- 
--	for (i = 0; i < smumgr->usec_timeout; i++) {
-+	for (i = 0; i < hwmgr->usec_timeout; i++) {
- 		if (firmware ==
--			(cgs_read_register(smumgr->device, mmMP0PUB_IND_DATA) & firmware))
-+			(cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA) & firmware))
- 			break;
- 		udelay(1);
- 	}
- 
--	if (i >= smumgr->usec_timeout) {
-+	if (i >= hwmgr->usec_timeout) {
- 		pr_err("SMU check loaded firmware failed.\n");
- 		return -EINVAL;
- 	}
-@@ -171,7 +170,7 @@ static int cz_check_fw_load_finish(struc
- 	return 0;
- }
- 
--static int cz_load_mec_firmware(struct pp_smumgr *smumgr)
-+static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr)
- {
- 	uint32_t reg_data;
- 	uint32_t tmp;
-@@ -179,44 +178,44 @@ static int cz_load_mec_firmware(struct p
- 	struct cgs_firmware_info info = {0};
- 	struct cz_smumgr *cz_smu;
- 
--	if (smumgr == NULL || smumgr->device == NULL)
-+	if (hwmgr == NULL || hwmgr->device == NULL)
- 		return -EINVAL;
- 
--	cz_smu = (struct cz_smumgr *)smumgr->backend;
--	ret = cgs_get_firmware_info(smumgr->device,
-+	cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
-+	ret = cgs_get_firmware_info(hwmgr->device,
- 						CGS_UCODE_ID_CP_MEC, &info);
- 
- 	if (ret)
- 		return -EINVAL;
- 
- 	/* Disable MEC parsing/prefetching */
--	tmp = cgs_read_register(smumgr->device,
-+	tmp = cgs_read_register(hwmgr->device,
- 					mmCP_MEC_CNTL);
--	tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
--	tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
--	cgs_write_register(smumgr->device, mmCP_MEC_CNTL, tmp);
-+	tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
-+	tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
-+	cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp);
- 
--	tmp = cgs_read_register(smumgr->device,
-+	tmp = cgs_read_register(hwmgr->device,
- 					mmCP_CPC_IC_BASE_CNTL);
- 
--	tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
--	tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
--	tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
--	tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
--	cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
-+	tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
-+	tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);
-+	tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
-+	tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);
-+	cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
- 
- 	reg_data = smu_lower_32_bits(info.mc_addr) &
--			SMUM_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO);
--	cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
-+			PHM_FIELD_MASK(CP_CPC_IC_BASE_LO, IC_BASE_LO);
-+	cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
- 
- 	reg_data = smu_upper_32_bits(info.mc_addr) &
--			SMUM_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI);
--	cgs_write_register(smumgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
-+			PHM_FIELD_MASK(CP_CPC_IC_BASE_HI, IC_BASE_HI);
-+	cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
- 
- 	return 0;
- }
- 
--static uint8_t cz_translate_firmware_enum_to_arg(struct pp_smumgr *smumgr,
-+static uint8_t cz_translate_firmware_enum_to_arg(struct pp_hwmgr *hwmgr,
- 			enum cz_scratch_entry firmware_enum)
- {
- 	uint8_t ret = 0;
-@@ -226,7 +225,7 @@ static uint8_t cz_translate_firmware_enu
- 		ret = UCODE_ID_SDMA0;
- 		break;
- 	case CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1:
--		if (smumgr->chip_id == CHIP_STONEY)
-+		if (hwmgr->chip_id == CHIP_STONEY)
- 			ret = UCODE_ID_SDMA0;
- 		else
- 			ret = UCODE_ID_SDMA1;
-@@ -244,7 +243,7 @@ static uint8_t cz_translate_firmware_enu
- 		ret = UCODE_ID_CP_MEC_JT1;
- 		break;
- 	case CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2:
--		if (smumgr->chip_id == CHIP_STONEY)
-+		if (hwmgr->chip_id == CHIP_STONEY)
- 			ret = UCODE_ID_CP_MEC_JT1;
- 		else
- 			ret = UCODE_ID_CP_MEC_JT2;
-@@ -326,17 +325,17 @@ static enum cgs_ucode_id cz_convert_fw_t
- }
- 
- static int cz_smu_populate_single_scratch_task(
--			struct pp_smumgr *smumgr,
-+			struct pp_hwmgr *hwmgr,
- 			enum cz_scratch_entry fw_enum,
- 			uint8_t type, bool is_last)
- {
- 	uint8_t i;
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 	struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
- 	struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
- 
- 	task->type = type;
--	task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum);
-+	task->arg = cz_translate_firmware_enum_to_arg(hwmgr, fw_enum);
- 	task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
- 
- 	for (i = 0; i < cz_smu->scratch_buffer_length; i++)
-@@ -363,17 +362,17 @@ static int cz_smu_populate_single_scratc
- }
- 
- static int cz_smu_populate_single_ucode_load_task(
--					struct pp_smumgr *smumgr,
-+					struct pp_hwmgr *hwmgr,
- 					enum cz_scratch_entry fw_enum,
- 					bool is_last)
- {
- 	uint8_t i;
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 	struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
- 	struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
- 
- 	task->type = TASK_TYPE_UCODE_LOAD;
--	task->arg = cz_translate_firmware_enum_to_arg(smumgr, fw_enum);
-+	task->arg = cz_translate_firmware_enum_to_arg(hwmgr, fw_enum);
- 	task->next = is_last ? END_OF_TASK_LIST : cz_smu->toc_entry_used_count;
- 
- 	for (i = 0; i < cz_smu->driver_buffer_length; i++)
-@@ -392,22 +391,22 @@ static int cz_smu_populate_single_ucode_
- 	return 0;
- }
- 
--static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_smumgr *smumgr)
-+static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr)
- {
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 
- 	cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count;
--	cz_smu_populate_single_scratch_task(smumgr,
-+	cz_smu_populate_single_scratch_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
- 				TASK_TYPE_UCODE_SAVE, true);
- 
- 	return 0;
- }
- 
--static int cz_smu_initialize_toc_empty_job_list(struct pp_smumgr *smumgr)
-+static int cz_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr)
- {
- 	int i;
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 	struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
- 
- 	for (i = 0; i < NUM_JOBLIST_ENTRIES; i++)
-@@ -416,17 +415,17 @@ static int cz_smu_initialize_toc_empty_j
- 	return 0;
- }
- 
--static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_smumgr *smumgr)
-+static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr)
- {
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 	struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
- 
- 	toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count;
--	cz_smu_populate_single_scratch_task(smumgr,
-+	cz_smu_populate_single_scratch_task(hwmgr,
- 				    CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
- 				    TASK_TYPE_UCODE_SAVE, false);
- 
--	cz_smu_populate_single_scratch_task(smumgr,
-+	cz_smu_populate_single_scratch_task(hwmgr,
- 				    CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
- 				    TASK_TYPE_UCODE_SAVE, true);
- 
-@@ -434,121 +433,120 @@ static int cz_smu_construct_toc_for_vddg
- }
- 
- 
--static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_smumgr *smumgr)
-+static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr)
- {
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 	struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
- 
- 	toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count;
- 
--	cz_smu_populate_single_ucode_load_task(smumgr,
-+	cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
--	cz_smu_populate_single_ucode_load_task(smumgr,
-+	cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
--	cz_smu_populate_single_ucode_load_task(smumgr,
-+	cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
--	cz_smu_populate_single_ucode_load_task(smumgr,
-+	cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
- 
--	if (smumgr->chip_id == CHIP_STONEY)
--		cz_smu_populate_single_ucode_load_task(smumgr,
-+	if (hwmgr->chip_id == CHIP_STONEY)
-+		cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
- 	else
--		cz_smu_populate_single_ucode_load_task(smumgr,
-+		cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
- 
--	cz_smu_populate_single_ucode_load_task(smumgr,
-+	cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
- 
- 	/* populate scratch */
--	cz_smu_populate_single_scratch_task(smumgr,
-+	cz_smu_populate_single_scratch_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
- 				TASK_TYPE_UCODE_LOAD, false);
- 
--	cz_smu_populate_single_scratch_task(smumgr,
-+	cz_smu_populate_single_scratch_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
- 				TASK_TYPE_UCODE_LOAD, false);
- 
--	cz_smu_populate_single_scratch_task(smumgr,
-+	cz_smu_populate_single_scratch_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
- 				TASK_TYPE_UCODE_LOAD, true);
- 
- 	return 0;
- }
- 
--static int cz_smu_construct_toc_for_power_profiling(
--						 struct pp_smumgr *smumgr)
-+static int cz_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr)
- {
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 
- 	cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count;
- 
--	cz_smu_populate_single_scratch_task(smumgr,
-+	cz_smu_populate_single_scratch_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
- 				TASK_TYPE_INITIALIZE, true);
- 	return 0;
- }
- 
--static int cz_smu_construct_toc_for_bootup(struct pp_smumgr *smumgr)
-+static int cz_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr)
- {
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 
- 	cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count;
- 
--	cz_smu_populate_single_ucode_load_task(smumgr,
-+	cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
--	if (smumgr->chip_id != CHIP_STONEY)
--		cz_smu_populate_single_ucode_load_task(smumgr,
-+	if (hwmgr->chip_id != CHIP_STONEY)
-+		cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
--	cz_smu_populate_single_ucode_load_task(smumgr,
-+	cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
--	cz_smu_populate_single_ucode_load_task(smumgr,
-+	cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP, false);
--	cz_smu_populate_single_ucode_load_task(smumgr,
-+	cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
--	cz_smu_populate_single_ucode_load_task(smumgr,
-+	cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
--	if (smumgr->chip_id != CHIP_STONEY)
--		cz_smu_populate_single_ucode_load_task(smumgr,
-+	if (hwmgr->chip_id != CHIP_STONEY)
-+		cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
--	cz_smu_populate_single_ucode_load_task(smumgr,
-+	cz_smu_populate_single_ucode_load_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
- 
- 	return 0;
- }
- 
--static int cz_smu_construct_toc_for_clock_table(struct pp_smumgr *smumgr)
-+static int cz_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr)
- {
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 
- 	cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count;
- 
--	cz_smu_populate_single_scratch_task(smumgr,
-+	cz_smu_populate_single_scratch_task(hwmgr,
- 				CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
- 				TASK_TYPE_INITIALIZE, true);
- 
- 	return 0;
- }
- 
--static int cz_smu_construct_toc(struct pp_smumgr *smumgr)
-+static int cz_smu_construct_toc(struct pp_hwmgr *hwmgr)
- {
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 
- 	cz_smu->toc_entry_used_count = 0;
--	cz_smu_initialize_toc_empty_job_list(smumgr);
--	cz_smu_construct_toc_for_rlc_aram_save(smumgr);
--	cz_smu_construct_toc_for_vddgfx_enter(smumgr);
--	cz_smu_construct_toc_for_vddgfx_exit(smumgr);
--	cz_smu_construct_toc_for_power_profiling(smumgr);
--	cz_smu_construct_toc_for_bootup(smumgr);
--	cz_smu_construct_toc_for_clock_table(smumgr);
-+	cz_smu_initialize_toc_empty_job_list(hwmgr);
-+	cz_smu_construct_toc_for_rlc_aram_save(hwmgr);
-+	cz_smu_construct_toc_for_vddgfx_enter(hwmgr);
-+	cz_smu_construct_toc_for_vddgfx_exit(hwmgr);
-+	cz_smu_construct_toc_for_power_profiling(hwmgr);
-+	cz_smu_construct_toc_for_bootup(hwmgr);
-+	cz_smu_construct_toc_for_clock_table(hwmgr);
- 
- 	return 0;
- }
- 
--static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr)
-+static int cz_smu_populate_firmware_entries(struct pp_hwmgr *hwmgr)
- {
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 	uint32_t firmware_type;
- 	uint32_t i;
- 	int ret;
-@@ -559,12 +557,12 @@ static int cz_smu_populate_firmware_entr
- 
- 	for (i = 0; i < ARRAY_SIZE(firmware_list); i++) {
- 
--		firmware_type = cz_translate_firmware_enum_to_arg(smumgr,
-+		firmware_type = cz_translate_firmware_enum_to_arg(hwmgr,
- 					firmware_list[i]);
- 
- 		ucode_id = cz_convert_fw_type_to_cgs(firmware_type);
- 
--		ret = cgs_get_firmware_info(smumgr->device,
-+		ret = cgs_get_firmware_info(hwmgr->device,
- 							ucode_id, &info);
- 
- 		if (ret == 0) {
-@@ -585,12 +583,12 @@ static int cz_smu_populate_firmware_entr
- }
- 
- static int cz_smu_populate_single_scratch_entry(
--				struct pp_smumgr *smumgr,
-+				struct pp_hwmgr *hwmgr,
- 				enum cz_scratch_entry scratch_type,
- 				uint32_t ulsize_byte,
- 				struct cz_buffer_entry *entry)
- {
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 	long long mc_addr =
- 			((long long)(cz_smu->smu_buffer.mc_addr_high) << 32)
- 			| cz_smu->smu_buffer.mc_addr_low;
-@@ -611,9 +609,9 @@ static int cz_smu_populate_single_scratc
- 	return 0;
- }
- 
--static int cz_download_pptable_settings(struct pp_smumgr *smumgr, void **table)
-+static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table)
- {
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 	unsigned long i;
- 
- 	for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
-@@ -624,25 +622,25 @@ static int cz_download_pptable_settings(
- 
- 	*table = (struct SMU8_Fusion_ClkTable *)cz_smu->scratch_buffer[i].kaddr;
- 
--	cz_send_msg_to_smc_with_parameter(smumgr,
-+	cz_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetClkTableAddrHi,
- 				cz_smu->scratch_buffer[i].mc_addr_high);
- 
--	cz_send_msg_to_smc_with_parameter(smumgr,
-+	cz_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetClkTableAddrLo,
- 				cz_smu->scratch_buffer[i].mc_addr_low);
- 
--	cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob,
-+	cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
- 				cz_smu->toc_entry_clock_table);
- 
--	cz_send_msg_to_smc(smumgr, PPSMC_MSG_ClkTableXferToDram);
-+	cz_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToDram);
- 
- 	return 0;
- }
- 
--static int cz_upload_pptable_settings(struct pp_smumgr *smumgr)
-+static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr)
- {
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 	unsigned long i;
- 
- 	for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
-@@ -651,63 +649,63 @@ static int cz_upload_pptable_settings(st
- 			break;
- 	}
- 
--	cz_send_msg_to_smc_with_parameter(smumgr,
-+	cz_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetClkTableAddrHi,
- 				cz_smu->scratch_buffer[i].mc_addr_high);
- 
--	cz_send_msg_to_smc_with_parameter(smumgr,
-+	cz_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetClkTableAddrLo,
- 				cz_smu->scratch_buffer[i].mc_addr_low);
- 
--	cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob,
-+	cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
- 				cz_smu->toc_entry_clock_table);
- 
--	cz_send_msg_to_smc(smumgr, PPSMC_MSG_ClkTableXferToSmu);
-+	cz_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToSmu);
- 
- 	return 0;
- }
- 
--static int cz_request_smu_load_fw(struct pp_smumgr *smumgr)
-+static int cz_request_smu_load_fw(struct pp_hwmgr *hwmgr)
- {
--	struct cz_smumgr *cz_smu = (struct cz_smumgr *)(smumgr->backend);
-+	struct cz_smumgr *cz_smu = (struct cz_smumgr *)(hwmgr->smu_backend);
- 	uint32_t smc_address;
- 
--	if (!smumgr->reload_fw) {
-+	if (!hwmgr->reload_fw) {
- 		pr_info("skip reloading...\n");
- 		return 0;
- 	}
- 
--	cz_smu_populate_firmware_entries(smumgr);
-+	cz_smu_populate_firmware_entries(hwmgr);
- 
--	cz_smu_construct_toc(smumgr);
-+	cz_smu_construct_toc(hwmgr);
- 
- 	smc_address = SMU8_FIRMWARE_HEADER_LOCATION +
- 		offsetof(struct SMU8_Firmware_Header, UcodeLoadStatus);
- 
--	cz_write_smc_sram_dword(smumgr, smc_address, 0, smc_address+4);
-+	cz_write_smc_sram_dword(hwmgr, smc_address, 0, smc_address+4);
- 
--	cz_send_msg_to_smc_with_parameter(smumgr,
-+	cz_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_DriverDramAddrHi,
- 					cz_smu->toc_buffer.mc_addr_high);
- 
--	cz_send_msg_to_smc_with_parameter(smumgr,
-+	cz_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_DriverDramAddrLo,
- 					cz_smu->toc_buffer.mc_addr_low);
- 
--	cz_send_msg_to_smc(smumgr, PPSMC_MSG_InitJobs);
-+	cz_send_msg_to_smc(hwmgr, PPSMC_MSG_InitJobs);
- 
--	cz_send_msg_to_smc_with_parameter(smumgr,
-+	cz_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_ExecuteJob,
- 					cz_smu->toc_entry_aram);
--	cz_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_ExecuteJob,
-+	cz_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
- 				cz_smu->toc_entry_power_profiling_index);
- 
--	return cz_send_msg_to_smc_with_parameter(smumgr,
-+	return cz_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_ExecuteJob,
- 					cz_smu->toc_entry_initialize_index);
- }
- 
--static int cz_start_smu(struct pp_smumgr *smumgr)
-+static int cz_start_smu(struct pp_hwmgr *hwmgr)
- {
- 	int ret = 0;
- 	uint32_t fw_to_check = 0;
-@@ -721,23 +719,23 @@ static int cz_start_smu(struct pp_smumgr
- 			UCODE_ID_CP_MEC_JT1_MASK |
- 			UCODE_ID_CP_MEC_JT2_MASK;
- 
--	if (smumgr->chip_id == CHIP_STONEY)
-+	if (hwmgr->chip_id == CHIP_STONEY)
- 		fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
- 
--	ret = cz_request_smu_load_fw(smumgr);
-+	ret = cz_request_smu_load_fw(hwmgr);
- 	if (ret)
- 		pr_err("SMU firmware load failed\n");
- 
--	cz_check_fw_load_finish(smumgr, fw_to_check);
-+	cz_check_fw_load_finish(hwmgr, fw_to_check);
- 
--	ret = cz_load_mec_firmware(smumgr);
-+	ret = cz_load_mec_firmware(hwmgr);
- 	if (ret)
- 		pr_err("Mec Firmware load failed\n");
- 
- 	return ret;
- }
- 
--static int cz_smu_init(struct pp_smumgr *smumgr)
-+static int cz_smu_init(struct pp_hwmgr *hwmgr)
- {
- 	uint64_t mc_addr = 0;
- 	int ret = 0;
-@@ -747,7 +745,7 @@ static int cz_smu_init(struct pp_smumgr
- 	if (cz_smu == NULL)
- 		return -ENOMEM;
- 
--	smumgr->backend = cz_smu;
-+	hwmgr->smu_backend = cz_smu;
- 
- 	cz_smu->toc_buffer.data_size = 4096;
- 	cz_smu->smu_buffer.data_size =
-@@ -757,7 +755,7 @@ static int cz_smu_init(struct pp_smumgr
- 		ALIGN(sizeof(struct SMU8_MultimediaPowerLogData), 32) +
- 		ALIGN(sizeof(struct SMU8_Fusion_ClkTable), 32);
- 
--	ret = smu_allocate_memory(smumgr->device,
-+	ret = smu_allocate_memory(hwmgr->device,
- 				cz_smu->toc_buffer.data_size,
- 				CGS_GPU_MEM_TYPE__GART_CACHEABLE,
- 				PAGE_SIZE,
-@@ -770,7 +768,7 @@ static int cz_smu_init(struct pp_smumgr
- 	cz_smu->toc_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
- 	cz_smu->toc_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
- 
--	ret = smu_allocate_memory(smumgr->device,
-+	ret = smu_allocate_memory(hwmgr->device,
- 				cz_smu->smu_buffer.data_size,
- 				CGS_GPU_MEM_TYPE__GART_CACHEABLE,
- 				PAGE_SIZE,
-@@ -783,7 +781,7 @@ static int cz_smu_init(struct pp_smumgr
- 	cz_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
- 	cz_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
- 
--	if (0 != cz_smu_populate_single_scratch_entry(smumgr,
-+	if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
- 		CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
- 		UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
- 		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
-@@ -791,14 +789,14 @@ static int cz_smu_init(struct pp_smumgr
- 		return -1;
- 	}
- 
--	if (0 != cz_smu_populate_single_scratch_entry(smumgr,
-+	if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
- 		CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
- 		UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
- 		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
- 		pr_err("Error when Populate Firmware Entry.\n");
- 		return -1;
- 	}
--	if (0 != cz_smu_populate_single_scratch_entry(smumgr,
-+	if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
- 		CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
- 		UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
- 		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
-@@ -806,7 +804,7 @@ static int cz_smu_init(struct pp_smumgr
- 		return -1;
- 	}
- 
--	if (0 != cz_smu_populate_single_scratch_entry(smumgr,
-+	if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
- 		CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
- 		sizeof(struct SMU8_MultimediaPowerLogData),
- 		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
-@@ -814,7 +812,7 @@ static int cz_smu_init(struct pp_smumgr
- 		return -1;
- 	}
- 
--	if (0 != cz_smu_populate_single_scratch_entry(smumgr,
-+	if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
- 		CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE,
- 		sizeof(struct SMU8_Fusion_ClkTable),
- 		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
-@@ -825,18 +823,18 @@ static int cz_smu_init(struct pp_smumgr
- 	return 0;
- }
- 
--static int cz_smu_fini(struct pp_smumgr *smumgr)
-+static int cz_smu_fini(struct pp_hwmgr *hwmgr)
- {
- 	struct cz_smumgr *cz_smu;
- 
--	if (smumgr == NULL || smumgr->device == NULL)
-+	if (hwmgr == NULL || hwmgr->device == NULL)
- 		return -EINVAL;
- 
--	cz_smu = (struct cz_smumgr *)smumgr->backend;
-+	cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
- 	if (cz_smu) {
--		cgs_free_gpu_mem(smumgr->device,
-+		cgs_free_gpu_mem(hwmgr->device,
- 				cz_smu->toc_buffer.handle);
--		cgs_free_gpu_mem(smumgr->device,
-+		cgs_free_gpu_mem(hwmgr->device,
- 				cz_smu->smu_buffer.handle);
- 		kfree(cz_smu);
- 	}
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c	2017-12-14 06:39:58.482903614 +0100
-@@ -23,6 +23,7 @@
- 
- #include "pp_debug.h"
- #include "smumgr.h"
-+#include "smu7_dyn_defaults.h"
- #include "smu73.h"
- #include "smu_ucode_xfer_vi.h"
- #include "fiji_smumgr.h"
-@@ -37,14 +38,54 @@
- #include "gca/gfx_8_0_d.h"
- #include "bif/bif_5_0_d.h"
- #include "bif/bif_5_0_sh_mask.h"
--#include "fiji_pwrvirus.h"
--#include "fiji_smc.h"
-+#include "dce/dce_10_0_d.h"
-+#include "dce/dce_10_0_sh_mask.h"
-+#include "hardwaremanager.h"
-+#include "cgs_common.h"
-+#include "atombios.h"
-+#include "pppcielanes.h"
-+#include "hwmgr.h"
-+#include "smu7_hwmgr.h"
-+
- 
- #define AVFS_EN_MSB                                        1568
- #define AVFS_EN_LSB                                        1568
- 
- #define FIJI_SMC_SIZE 0x20000
- 
-+#define VOLTAGE_SCALE 4
-+#define POWERTUNE_DEFAULT_SET_MAX    1
-+#define VOLTAGE_VID_OFFSET_SCALE1   625
-+#define VOLTAGE_VID_OFFSET_SCALE2   100
-+#define VDDC_VDDCI_DELTA            300
-+#define MC_CG_ARB_FREQ_F1           0x0b
-+
-+/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
-+ * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
-+ */
-+static const uint16_t fiji_clock_stretcher_lookup_table[2][4] = {
-+				{600, 1050, 3, 0}, {600, 1050, 6, 1} };
-+
-+/* [FF, SS] type, [] 4 voltage ranges, and
-+ * [Floor Freq, Boundary Freq, VID min , VID max]
-+ */
-+static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] = {
-+	{ {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
-+	{ {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
-+
-+/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
-+ * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
-+ */
-+static const uint8_t fiji_clock_stretch_amount_conversion[2][6] = {
-+				{0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
-+
-+static const struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
-+		/*sviLoadLIneEn,  SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc */
-+		{1,               0xF,             0xFD,
-+		/* TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase */
-+		0x19,        5,               45}
-+};
-+
- static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
- 		/*  Min        Sclk       pcie     DeepSleep Activity  CgSpll      CgSpll    spllSpread  SpllSpread   CcPwr  CcPwr  Sclk   Display     Enabled     Enabled                       Voltage    Power */
- 		/* Voltage,  Frequency,  DpmLevel,  DivId,    Level,  FuncCntl3,  FuncCntl4,  Spectrum,   Spectrum2,  DynRm, DynRm1  Did, Watermark, ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
-@@ -58,147 +99,114 @@ static const struct SMU73_Discrete_Graph
- 		{ 0xf811d047, 0x80380100,   0x01,     0x00,   0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000,   0,      0,   0x0c,   0x01,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 }
- };
- 
--static int fiji_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
-+static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
- {
- 	int result = 0;
- 
- 	/* Wait for smc boot up */
--	/* SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
-+	/* PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
- 		RCU_UC_EVENTS, boot_seq_done, 0); */
- 
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 			SMC_SYSCON_RESET_CNTL, rst_reg, 1);
- 
--	result = smu7_upload_smu_firmware_image(smumgr);
-+	result = smu7_upload_smu_firmware_image(hwmgr);
- 	if (result)
- 		return result;
- 
- 	/* Clear status */
--	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- 			ixSMU_STATUS, 0);
- 
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 			SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
- 
- 	/* De-assert reset */
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 			SMC_SYSCON_RESET_CNTL, rst_reg, 0);
- 
- 	/* Wait for ROM firmware to initialize interrupt hendler */
--	/*SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, SMC_IND,
-+	/*SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, SMC_IND,
- 			SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */
- 
- 	/* Set SMU Auto Start */
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 			SMU_INPUT_DATA, AUTO_START, 1);
- 
- 	/* Clear firmware interrupt enable flag */
--	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- 			ixFIRMWARE_FLAGS, 0);
- 
--	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS,
-+	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
- 			INTERRUPTS_ENABLED, 1);
- 
--	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
--	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
--	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
-+	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
-+	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
- 
- 	/* Wait for done bit to be set */
--	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
-+	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
- 			SMU_STATUS, SMU_DONE, 0);
- 
- 	/* Check pass/failed indicator */
--	if (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 			SMU_STATUS, SMU_PASS) != 1) {
- 		PP_ASSERT_WITH_CODE(false,
- 				"SMU Firmware start failed!", return -1);
- 	}
- 
- 	/* Wait for firmware to initialize */
--	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
-+	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
- 			FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
- 
- 	return result;
- }
- 
--static int fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
-+static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
- {
- 	int result = 0;
- 
- 	/* wait for smc boot up */
--	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
-+	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
- 			RCU_UC_EVENTS, boot_seq_done, 0);
- 
- 	/* Clear firmware interrupt enable flag */
--	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- 			ixFIRMWARE_FLAGS, 0);
- 
- 	/* Assert reset */
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 			SMC_SYSCON_RESET_CNTL, rst_reg, 1);
- 
--	result = smu7_upload_smu_firmware_image(smumgr);
-+	result = smu7_upload_smu_firmware_image(hwmgr);
- 	if (result)
- 		return result;
- 
- 	/* Set smc instruct start point at 0x0 */
--	smu7_program_jump_on_start(smumgr);
-+	smu7_program_jump_on_start(hwmgr);
- 
- 	/* Enable clock */
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 			SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
- 
- 	/* De-assert reset */
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 			SMC_SYSCON_RESET_CNTL, rst_reg, 0);
- 
- 	/* Wait for firmware to initialize */
--	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
-+	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
- 			FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
- 
- 	return result;
- }
- 
--static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
--{
--	int i;
--	int result = -EINVAL;
--	uint32_t reg, data;
--
--	const PWR_Command_Table *pvirus = PwrVirusTable;
--	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
--
--	for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
--		switch (pvirus->command) {
--		case PwrCmdWrite:
--			reg  = pvirus->reg;
--			data = pvirus->data;
--			cgs_write_register(smumgr->device, reg, data);
--			break;
--
--		case PwrCmdEnd:
--			result = 0;
--			break;
--
--		default:
--			pr_info("Table Exit with Invalid Command!");
--			smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
--			result = -EINVAL;
--			break;
--		}
--		pvirus++;
--	}
--
--	return result;
--}
--
--static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
-+static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr)
- {
- 	int result = 0;
--	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
-+	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
- 
- 	if (0 != smu_data->avfs.avfs_btc_param) {
--		if (0 != smu7_send_msg_to_smc_with_parameter(smumgr,
-+		if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
- 			pr_info("[AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed");
- 			result = -EINVAL;
-@@ -206,23 +214,23 @@ static int fiji_start_avfs_btc(struct pp
- 	}
- 	/* Soft-Reset to reset the engine before loading uCode */
- 	 /* halt */
--	cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000);
-+	cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
- 	/* reset everything */
--	cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
-+	cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
- 	/* clear reset */
--	cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
-+	cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
- 
- 	return result;
- }
- 
--static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
-+static int fiji_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
- {
- 	int32_t vr_config;
- 	uint32_t table_start;
- 	uint32_t level_addr, vr_config_addr;
- 	uint32_t level_size = sizeof(avfs_graphics_level);
- 
--	PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr,
-+	PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
- 			SMU7_FIRMWARE_HEADER_LOCATION +
- 			offsetof(SMU73_Firmware_Header, DpmTable),
- 			&table_start, 0x40000),
-@@ -237,7 +245,7 @@ static int fiji_setup_graphics_level_str
- 	vr_config_addr = table_start +
- 			offsetof(SMU73_Discrete_DpmTable, VRConfig);
- 
--	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_addr,
-+	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr,
- 			(uint8_t *)&vr_config, sizeof(int32_t), 0x40000),
- 			"[AVFS][Fiji_SetupGfxLvlStruct] Problems copying "
- 			"vr_config value over to SMC",
-@@ -245,7 +253,7 @@ static int fiji_setup_graphics_level_str
- 
- 	level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
- 
--	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, level_addr,
-+	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr,
- 			(uint8_t *)(&avfs_graphics_level), level_size, 0x40000),
- 			"[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed!",
- 			return -1;);
-@@ -253,9 +261,9 @@ static int fiji_setup_graphics_level_str
- 	return 0;
- }
- 
--static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
-+static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool smu_started)
- {
--	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
-+	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
- 
- 	switch (smu_data->avfs.avfs_btc_status) {
- 	case AVFS_BTC_COMPLETED_PREVIOUSLY:
-@@ -265,17 +273,17 @@ static int fiji_avfs_event_mgr(struct pp
- 		if (!smu_started)
- 			break;
- 		smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
--		PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(smumgr),
-+		PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr),
- 				"[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics Level"
- 				" table over to SMU",
- 				return -EINVAL;);
- 		smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
--		PP_ASSERT_WITH_CODE(0 == fiji_setup_pwr_virus(smumgr),
-+		PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
- 				"[AVFS][fiji_avfs_event_mgr] Could not setup "
- 				"Pwr Virus for AVFS ",
- 				return -EINVAL;);
- 		smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
--		PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(smumgr),
-+		PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr),
- 				"[AVFS][fiji_avfs_event_mgr] Failure at "
- 				"fiji_start_avfs_btc. AVFS Disabled",
- 				return -EINVAL;);
-@@ -293,64 +301,64 @@ static int fiji_avfs_event_mgr(struct pp
- 	return 0;
- }
- 
--static int fiji_start_smu(struct pp_smumgr *smumgr)
-+static int fiji_start_smu(struct pp_hwmgr *hwmgr)
- {
- 	int result = 0;
--	struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
-+	struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smu_backend);
- 
- 	/* Only start SMC if SMC RAM is not running */
--	if (!(smu7_is_smc_ram_running(smumgr)
--		|| cgs_is_virtualization_enabled(smumgr->device))) {
--		fiji_avfs_event_mgr(smumgr, false);
-+	if (!(smu7_is_smc_ram_running(hwmgr)
-+		|| cgs_is_virtualization_enabled(hwmgr->device))) {
-+		fiji_avfs_event_mgr(hwmgr, false);
- 
- 		/* Check if SMU is running in protected mode */
--		if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
-+		if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
- 				CGS_IND_REG__SMC,
- 				SMU_FIRMWARE, SMU_MODE)) {
--			result = fiji_start_smu_in_non_protection_mode(smumgr);
-+			result = fiji_start_smu_in_non_protection_mode(hwmgr);
- 			if (result)
- 				return result;
- 		} else {
--			result = fiji_start_smu_in_protection_mode(smumgr);
-+			result = fiji_start_smu_in_protection_mode(hwmgr);
- 			if (result)
- 				return result;
- 		}
--		fiji_avfs_event_mgr(smumgr, true);
-+		fiji_avfs_event_mgr(hwmgr, true);
- 	}
- 
- 	/* To initialize all clock gating before RLC loaded and running.*/
--	cgs_set_clockgating_state(smumgr->device,
-+	cgs_set_clockgating_state(hwmgr->device,
- 			AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
--	cgs_set_clockgating_state(smumgr->device,
-+	cgs_set_clockgating_state(hwmgr->device,
- 			AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
--	cgs_set_clockgating_state(smumgr->device,
-+	cgs_set_clockgating_state(hwmgr->device,
- 			AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
--	cgs_set_clockgating_state(smumgr->device,
-+	cgs_set_clockgating_state(hwmgr->device,
- 			AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
- 
- 	/* Setup SoftRegsStart here for register lookup in case
- 	 * DummyBackEnd is used and ProcessFirmwareHeader is not executed
- 	 */
--	smu7_read_smc_sram_dword(smumgr,
-+	smu7_read_smc_sram_dword(hwmgr,
- 			SMU7_FIRMWARE_HEADER_LOCATION +
- 			offsetof(SMU73_Firmware_Header, SoftRegisters),
- 			&(priv->smu7_data.soft_regs_start), 0x40000);
- 
--	result = smu7_request_smu_load_fw(smumgr);
-+	result = smu7_request_smu_load_fw(hwmgr);
- 
- 	return result;
- }
- 
--static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr)
-+static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
- {
- 
- 	uint32_t efuse = 0;
- 	uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1;
- 
--	if (cgs_is_virtualization_enabled(smumgr->device))
-+	if (cgs_is_virtualization_enabled(hwmgr->device))
- 		return 0;
- 
--	if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
-+	if (!atomctrl_read_efuse(hwmgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
- 			mask, &efuse)) {
- 		if (efuse)
- 			return true;
-@@ -358,14 +366,7 @@ static bool fiji_is_hw_avfs_present(stru
- 	return false;
- }
- 
--/**
--* Write a 32bit value to the SMC SRAM space.
--* ALL PARAMETERS ARE IN HOST BYTE ORDER.
--* @param    smumgr  the address of the powerplay hardware manager.
--* @param    smc_addr the address in the SMC RAM to access.
--* @param    value to write to the SMC SRAM.
--*/
--static int fiji_smu_init(struct pp_smumgr *smumgr)
-+static int fiji_smu_init(struct pp_hwmgr *hwmgr)
- {
- 	int i;
- 	struct fiji_smumgr *fiji_priv = NULL;
-@@ -375,9 +376,9 @@ static int fiji_smu_init(struct pp_smumg
- 	if (fiji_priv == NULL)
- 		return -ENOMEM;
- 
--	smumgr->backend = fiji_priv;
-+	hwmgr->smu_backend = fiji_priv;
- 
--	if (smu7_init(smumgr))
-+	if (smu7_init(hwmgr))
- 		return -EINVAL;
- 
- 	for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
-@@ -386,6 +387,2334 @@ static int fiji_smu_init(struct pp_smumg
- 	return 0;
- }
- 
-+static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
-+		struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
-+		uint32_t clock, uint32_t *voltage, uint32_t *mvdd)
-+{
-+	uint32_t i;
-+	uint16_t vddci;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	*voltage = *mvdd = 0;
-+
-+
-+	/* clock - voltage dependency table is empty table */
-+	if (dep_table->count == 0)
-+		return -EINVAL;
-+
-+	for (i = 0; i < dep_table->count; i++) {
-+		/* find first sclk bigger than request */
-+		if (dep_table->entries[i].clk >= clock) {
-+			*voltage |= (dep_table->entries[i].vddc *
-+					VOLTAGE_SCALE) << VDDC_SHIFT;
-+			if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
-+				*voltage |= (data->vbios_boot_state.vddci_bootup_value *
-+						VOLTAGE_SCALE) << VDDCI_SHIFT;
-+			else if (dep_table->entries[i].vddci)
-+				*voltage |= (dep_table->entries[i].vddci *
-+						VOLTAGE_SCALE) << VDDCI_SHIFT;
-+			else {
-+				vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
-+						(dep_table->entries[i].vddc -
-+								VDDC_VDDCI_DELTA));
-+				*voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+			}
-+
-+			if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
-+				*mvdd = data->vbios_boot_state.mvdd_bootup_value *
-+					VOLTAGE_SCALE;
-+			else if (dep_table->entries[i].mvdd)
-+				*mvdd = (uint32_t) dep_table->entries[i].mvdd *
-+					VOLTAGE_SCALE;
-+
-+			*voltage |= 1 << PHASES_SHIFT;
-+			return 0;
-+		}
-+	}
-+
-+	/* sclk is bigger than max sclk in the dependence table */
-+	*voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
-+		*voltage |= (data->vbios_boot_state.vddci_bootup_value *
-+				VOLTAGE_SCALE) << VDDCI_SHIFT;
-+	else if (dep_table->entries[i-1].vddci) {
-+		vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
-+				(dep_table->entries[i].vddc -
-+						VDDC_VDDCI_DELTA));
-+		*voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+	}
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
-+		*mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
-+	else if (dep_table->entries[i].mvdd)
-+		*mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
-+
-+	return 0;
-+}
-+
-+
-+static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
-+{
-+	uint32_t tmp;
-+	tmp = raw_setting * 4096 / 100;
-+	return (uint16_t)tmp;
-+}
-+
-+static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t *sda)
-+{
-+	switch (line) {
-+	case SMU7_I2CLineID_DDC1:
-+		*scl = SMU7_I2C_DDC1CLK;
-+		*sda = SMU7_I2C_DDC1DATA;
-+		break;
-+	case SMU7_I2CLineID_DDC2:
-+		*scl = SMU7_I2C_DDC2CLK;
-+		*sda = SMU7_I2C_DDC2DATA;
-+		break;
-+	case SMU7_I2CLineID_DDC3:
-+		*scl = SMU7_I2C_DDC3CLK;
-+		*sda = SMU7_I2C_DDC3DATA;
-+		break;
-+	case SMU7_I2CLineID_DDC4:
-+		*scl = SMU7_I2C_DDC4CLK;
-+		*sda = SMU7_I2C_DDC4DATA;
-+		break;
-+	case SMU7_I2CLineID_DDC5:
-+		*scl = SMU7_I2C_DDC5CLK;
-+		*sda = SMU7_I2C_DDC5DATA;
-+		break;
-+	case SMU7_I2CLineID_DDC6:
-+		*scl = SMU7_I2C_DDC6CLK;
-+		*sda = SMU7_I2C_DDC6DATA;
-+		break;
-+	case SMU7_I2CLineID_SCLSDA:
-+		*scl = SMU7_I2C_SCL;
-+		*sda = SMU7_I2C_SDA;
-+		break;
-+	case SMU7_I2CLineID_DDCVGA:
-+		*scl = SMU7_I2C_DDCVGACLK;
-+		*sda = SMU7_I2C_DDCVGADATA;
-+		break;
-+	default:
-+		*scl = 0;
-+		*sda = 0;
-+		break;
-+	}
-+}
-+
-+static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct  phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (table_info &&
-+			table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
-+			table_info->cac_dtp_table->usPowerTuneDataSetID)
-+		smu_data->power_tune_defaults =
-+				&fiji_power_tune_data_set_array
-+				[table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
-+	else
-+		smu_data->power_tune_defaults = &fiji_power_tune_data_set_array[0];
-+
-+}
-+
-+static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
-+{
-+
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
-+
-+	SMU73_Discrete_DpmTable  *dpm_table = &(smu_data->smc_state_table);
-+
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
-+	struct pp_advance_fan_control_parameters *fan_table =
-+			&hwmgr->thermal_controller.advanceFanControlParameters;
-+	uint8_t uc_scl, uc_sda;
-+
-+	/* TDP number of fraction bits are changed from 8 to 7 for Fiji
-+	 * as requested by SMC team
-+	 */
-+	dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
-+			(uint16_t)(cac_dtp_table->usTDP * 128));
-+	dpm_table->TargetTdp = PP_HOST_TO_SMC_US(
-+			(uint16_t)(cac_dtp_table->usTDP * 128));
-+
-+	PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
-+			"Target Operating Temp is out of Range!",
-+			);
-+
-+	dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
-+	dpm_table->GpuTjHyst = 8;
-+
-+	dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase;
-+
-+	/* The following are for new Fiji Multi-input fan/thermal control */
-+	dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTargetOperatingTemp * 256);
-+	dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTemperatureLimitHotspot * 256);
-+	dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTemperatureLimitLiquid1 * 256);
-+	dpm_table->TemperatureLimitLiquid2 = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTemperatureLimitLiquid2 * 256);
-+	dpm_table->TemperatureLimitVrVddc = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTemperatureLimitVrVddc * 256);
-+	dpm_table->TemperatureLimitVrMvdd = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTemperatureLimitVrMvdd * 256);
-+	dpm_table->TemperatureLimitPlx = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTemperatureLimitPlx * 256);
-+
-+	dpm_table->FanGainEdge = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainEdge));
-+	dpm_table->FanGainHotspot = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainHotspot));
-+	dpm_table->FanGainLiquid = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainLiquid));
-+	dpm_table->FanGainVrVddc = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainVrVddc));
-+	dpm_table->FanGainVrMvdd = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainVrMvdd));
-+	dpm_table->FanGainPlx = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainPlx));
-+	dpm_table->FanGainHbm = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainHbm));
-+
-+	dpm_table->Liquid1_I2C_address = cac_dtp_table->ucLiquid1_I2C_address;
-+	dpm_table->Liquid2_I2C_address = cac_dtp_table->ucLiquid2_I2C_address;
-+	dpm_table->Vr_I2C_address = cac_dtp_table->ucVr_I2C_address;
-+	dpm_table->Plx_I2C_address = cac_dtp_table->ucPlx_I2C_address;
-+
-+	get_scl_sda_value(cac_dtp_table->ucLiquid_I2C_Line, &uc_scl, &uc_sda);
-+	dpm_table->Liquid_I2C_LineSCL = uc_scl;
-+	dpm_table->Liquid_I2C_LineSDA = uc_sda;
-+
-+	get_scl_sda_value(cac_dtp_table->ucVr_I2C_Line, &uc_scl, &uc_sda);
-+	dpm_table->Vr_I2C_LineSCL = uc_scl;
-+	dpm_table->Vr_I2C_LineSDA = uc_sda;
-+
-+	get_scl_sda_value(cac_dtp_table->ucPlx_I2C_Line, &uc_scl, &uc_sda);
-+	dpm_table->Plx_I2C_LineSCL = uc_scl;
-+	dpm_table->Plx_I2C_LineSDA = uc_sda;
-+
-+	return 0;
-+}
-+
-+
-+static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
-+
-+	smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
-+	smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
-+	smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
-+	smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
-+
-+	return 0;
-+}
-+
-+
-+static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
-+{
-+	uint16_t tdc_limit;
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
-+
-+	/* TDC number of fraction bits are changed from 8 to 7
-+	 * for Fiji as requested by SMC team
-+	 */
-+	tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
-+	smu_data->power_tune_table.TDC_VDDC_PkgLimit =
-+			CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
-+	smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
-+			defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
-+	smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
-+{
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
-+	uint32_t temp;
-+
-+	if (smu7_read_smc_sram_dword(hwmgr,
-+			fuse_table_offset +
-+			offsetof(SMU73_Discrete_PmFuses, TdcWaterfallCtl),
-+			(uint32_t *)&temp, SMC_RAM_END))
-+		PP_ASSERT_WITH_CODE(false,
-+				"Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
-+				return -EINVAL);
-+	else {
-+		smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
-+		smu_data->power_tune_table.LPMLTemperatureMin =
-+				(uint8_t)((temp >> 16) & 0xff);
-+		smu_data->power_tune_table.LPMLTemperatureMax =
-+				(uint8_t)((temp >> 8) & 0xff);
-+		smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
-+	}
-+	return 0;
-+}
-+
-+static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+
-+	/* Currently not used. Set all to zero. */
-+	for (i = 0; i < 16; i++)
-+		smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+
-+	if ((hwmgr->thermal_controller.advanceFanControlParameters.
-+			usFanOutputSensitivity & (1 << 15)) ||
-+			0 == hwmgr->thermal_controller.advanceFanControlParameters.
-+			usFanOutputSensitivity)
-+		hwmgr->thermal_controller.advanceFanControlParameters.
-+		usFanOutputSensitivity = hwmgr->thermal_controller.
-+			advanceFanControlParameters.usDefaultFanOutputSensitivity;
-+
-+	smu_data->power_tune_table.FuzzyFan_PwmSetDelta =
-+			PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
-+					advanceFanControlParameters.usFanOutputSensitivity);
-+	return 0;
-+}
-+
-+static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+
-+	/* Currently not used. Set all to zero. */
-+	for (i = 0; i < 16; i++)
-+		smu_data->power_tune_table.GnbLPML[i] = 0;
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
-+	uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
-+	struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
-+
-+	HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
-+	LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
-+
-+	smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
-+	smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t pm_fuse_table_offset;
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment)) {
-+		if (smu7_read_smc_sram_dword(hwmgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU73_Firmware_Header, PmFuseTable),
-+				&pm_fuse_table_offset, SMC_RAM_END))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to get pm_fuse_table_offset Failed!",
-+					return -EINVAL);
-+
-+		/* DW6 */
-+		if (fiji_populate_svi_load_line(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate SviLoadLine Failed!",
-+					return -EINVAL);
-+		/* DW7 */
-+		if (fiji_populate_tdc_limit(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate TDCLimit Failed!", return -EINVAL);
-+		/* DW8 */
-+		if (fiji_populate_dw8(hwmgr, pm_fuse_table_offset))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate TdcWaterfallCtl, "
-+					"LPMLTemperature Min and Max Failed!",
-+					return -EINVAL);
-+
-+		/* DW9-DW12 */
-+		if (0 != fiji_populate_temperature_scaler(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate LPMLTemperatureScaler Failed!",
-+					return -EINVAL);
-+
-+		/* DW13-DW14 */
-+		if (fiji_populate_fuzzy_fan(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate Fuzzy Fan Control parameters Failed!",
-+					return -EINVAL);
-+
-+		/* DW15-DW18 */
-+		if (fiji_populate_gnb_lpml(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate GnbLPML Failed!",
-+					return -EINVAL);
-+
-+		/* DW20 */
-+		if (fiji_populate_bapm_vddc_base_leakage_sidd(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate BapmVddCBaseLeakage Hi and Lo "
-+					"Sidd Failed!", return -EINVAL);
-+
-+		if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
-+				(uint8_t *)&smu_data->power_tune_table,
-+				sizeof(struct SMU73_Discrete_PmFuses), SMC_RAM_END))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to download PmFuseTable Failed!",
-+					return -EINVAL);
-+	}
-+	return 0;
-+}
-+
-+static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_DpmTable *table)
-+{
-+	uint32_t count;
-+	uint8_t index;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_voltage_lookup_table *lookup_table =
-+			table_info->vddc_lookup_table;
-+	/* tables is already swapped, so in order to use the value from it,
-+	 * we need to swap it back.
-+	 * We are populating vddc CAC data to BapmVddc table
-+	 * in split and merged mode
-+	 */
-+
-+	for (count = 0; count < lookup_table->count; count++) {
-+		index = phm_get_voltage_index(lookup_table,
-+				data->vddc_voltage_table.entries[count].value);
-+		table->BapmVddcVidLoSidd[count] =
-+			convert_to_vid(lookup_table->entries[index].us_cac_low);
-+		table->BapmVddcVidHiSidd[count] =
-+			convert_to_vid(lookup_table->entries[index].us_cac_high);
-+	}
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_DpmTable *table)
-+{
-+	int result;
-+
-+	result = fiji_populate_cac_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"can not populate CAC voltage tables to SMC",
-+			return -EINVAL);
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_Ulv *state)
-+{
-+	int result = 0;
-+
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	state->CcPwrDynRm = 0;
-+	state->CcPwrDynRm1 = 0;
-+
-+	state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
-+	state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
-+			VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
-+
-+	state->VddcPhase = 1;
-+
-+	if (!result) {
-+		CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
-+		CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
-+		CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
-+	}
-+	return result;
-+}
-+
-+static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_DpmTable *table)
-+{
-+	return fiji_populate_ulv_level(hwmgr, &table->Ulv);
-+}
-+
-+static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct smu7_dpm_table *dpm_table = &data->dpm_table;
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	int i;
-+
-+	/* Index (dpm_table->pcie_speed_table.count)
-+	 * is reserved for PCIE boot level. */
-+	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
-+		table->LinkLevel[i].PcieGenSpeed  =
-+				(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
-+		table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
-+				dpm_table->pcie_speed_table.dpm_levels[i].param1);
-+		table->LinkLevel[i].EnabledForActivity = 1;
-+		table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
-+		table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
-+		table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
-+	}
-+
-+	smu_data->smc_state_table.LinkLevelCount =
-+			(uint8_t)dpm_table->pcie_speed_table.count;
-+	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
-+
-+	return 0;
-+}
-+
-+static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
-+{
-+	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
-+	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
-+	uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
-+	uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
-+	uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
-+	uint32_t ref_clock;
-+	uint32_t ref_divider;
-+	uint32_t fbdiv;
-+	int result;
-+
-+	/* get the engine clock dividers for this clock value */
-+	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock,  &dividers);
-+
-+	PP_ASSERT_WITH_CODE(result == 0,
-+			"Error retrieving Engine Clock dividers from VBIOS.",
-+			return result);
-+
-+	/* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
-+	ref_clock = atomctrl_get_reference_clock(hwmgr);
-+	ref_divider = 1 + dividers.uc_pll_ref_div;
-+
-+	/* low 14 bits is fraction and high 12 bits is divider */
-+	fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
-+
-+	/* SPLL_FUNC_CNTL setup */
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
-+			SPLL_REF_DIV, dividers.uc_pll_ref_div);
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
-+			SPLL_PDIV_A,  dividers.uc_pll_post_div);
-+
-+	/* SPLL_FUNC_CNTL_3 setup*/
-+	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
-+			SPLL_FB_DIV, fbdiv);
-+
-+	/* set to use fractional accumulation*/
-+	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
-+			SPLL_DITHEN, 1);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
-+		struct pp_atomctrl_internal_ss_info ssInfo;
-+
-+		uint32_t vco_freq = clock * dividers.uc_pll_post_div;
-+		if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
-+				vco_freq, &ssInfo)) {
-+			/*
-+			 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
-+			 * ss_info.speed_spectrum_rate -- in unit of khz
-+			 *
-+			 * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
-+			 */
-+			uint32_t clk_s = ref_clock * 5 /
-+					(ref_divider * ssInfo.speed_spectrum_rate);
-+			/* clkv = 2 * D * fbdiv / NS */
-+			uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
-+					fbdiv / (clk_s * 10000);
-+
-+			cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
-+					CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
-+			cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
-+					CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
-+			cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
-+					CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
-+		}
-+	}
-+
-+	sclk->SclkFrequency        = clock;
-+	sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
-+	sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
-+	sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
-+	sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
-+	sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, uint16_t sclk_al_threshold,
-+		struct SMU73_Discrete_GraphicsLevel *level)
-+{
-+	int result;
-+	/* PP_Clocks minClocks; */
-+	uint32_t threshold, mvdd;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	result = fiji_calculate_sclk_params(hwmgr, clock, level);
-+
-+	/* populate graphics levels */
-+	result = fiji_get_dependency_volt_by_clk(hwmgr,
-+			table_info->vdd_dep_on_sclk, clock,
-+			(uint32_t *)(&level->MinVoltage), &mvdd);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+			"can not find VDDC voltage value for "
-+			"VDDC engine clock dependency table",
-+			return result);
-+
-+	level->SclkFrequency = clock;
-+	level->ActivityLevel = sclk_al_threshold;
-+	level->CcPwrDynRm = 0;
-+	level->CcPwrDynRm1 = 0;
-+	level->EnabledForActivity = 0;
-+	level->EnabledForThrottle = 1;
-+	level->UpHyst = 10;
-+	level->DownHyst = 0;
-+	level->VoltageDownHyst = 0;
-+	level->PowerThrottle = 0;
-+
-+	threshold = clock * data->fast_watermark_threshold / 100;
-+
-+	data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
-+		level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
-+								hwmgr->display_config.min_core_set_clock_in_sr);
-+
-+
-+	/* Default to slow, highest DPM level will be
-+	 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
-+	 */
-+	level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+
-+	struct smu7_dpm_table *dpm_table = &data->dpm_table;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
-+	uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
-+	int result = 0;
-+	uint32_t array = smu_data->smu7_data.dpm_table_start +
-+			offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
-+	uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
-+			SMU73_MAX_LEVELS_GRAPHICS;
-+	struct SMU73_Discrete_GraphicsLevel *levels =
-+			smu_data->smc_state_table.GraphicsLevel;
-+	uint32_t i, max_entry;
-+	uint8_t hightest_pcie_level_enabled = 0,
-+			lowest_pcie_level_enabled = 0,
-+			mid_pcie_level_enabled = 0,
-+			count = 0;
-+
-+	for (i = 0; i < dpm_table->sclk_table.count; i++) {
-+		result = fiji_populate_single_graphic_level(hwmgr,
-+				dpm_table->sclk_table.dpm_levels[i].value,
-+				(uint16_t)smu_data->activity_target[i],
-+				&levels[i]);
-+		if (result)
-+			return result;
-+
-+		/* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
-+		if (i > 1)
-+			levels[i].DeepSleepDivId = 0;
-+	}
-+
-+	/* Only enable level 0 for now.*/
-+	levels[0].EnabledForActivity = 1;
-+
-+	/* set highest level watermark to high */
-+	levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
-+			PPSMC_DISPLAY_WATERMARK_HIGH;
-+
-+	smu_data->smc_state_table.GraphicsDpmLevelCount =
-+			(uint8_t)dpm_table->sclk_table.count;
-+	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
-+
-+	if (pcie_table != NULL) {
-+		PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
-+				"There must be 1 or more PCIE levels defined in PPTable.",
-+				return -EINVAL);
-+		max_entry = pcie_entry_cnt - 1;
-+		for (i = 0; i < dpm_table->sclk_table.count; i++)
-+			levels[i].pcieDpmLevel =
-+					(uint8_t) ((i < max_entry) ? i : max_entry);
-+	} else {
-+		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << (hightest_pcie_level_enabled + 1))) != 0))
-+			hightest_pcie_level_enabled++;
-+
-+		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << lowest_pcie_level_enabled)) == 0))
-+			lowest_pcie_level_enabled++;
-+
-+		while ((count < hightest_pcie_level_enabled) &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
-+			count++;
-+
-+		mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
-+				hightest_pcie_level_enabled ?
-+						(lowest_pcie_level_enabled + 1 + count) :
-+						hightest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to hightest_pcie_level_enabled */
-+		for (i = 2; i < dpm_table->sclk_table.count; i++)
-+			levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to lowest_pcie_level_enabled */
-+		levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to mid_pcie_level_enabled */
-+		levels[1].pcieDpmLevel = mid_pcie_level_enabled;
-+	}
-+	/* level count will send to smc once at init smc table and never change */
-+	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
-+			(uint32_t)array_size, SMC_RAM_END);
-+
-+	return result;
-+}
-+
-+
-+/**
-+ * MCLK Frequency Ratio
-+ * SEQ_CG_RESP  Bit[31:24] - 0x0
-+ * Bit[27:24] \96 DDR3 Frequency ratio
-+ * 0x0 <= 100MHz,       450 < 0x8 <= 500MHz
-+ * 100 < 0x1 <= 150MHz,       500 < 0x9 <= 550MHz
-+ * 150 < 0x2 <= 200MHz,       550 < 0xA <= 600MHz
-+ * 200 < 0x3 <= 250MHz,       600 < 0xB <= 650MHz
-+ * 250 < 0x4 <= 300MHz,       650 < 0xC <= 700MHz
-+ * 300 < 0x5 <= 350MHz,       700 < 0xD <= 750MHz
-+ * 350 < 0x6 <= 400MHz,       750 < 0xE <= 800MHz
-+ * 400 < 0x7 <= 450MHz,       800 < 0xF
-+ */
-+static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
-+{
-+	if (mem_clock <= 10000)
-+		return 0x0;
-+	if (mem_clock <= 15000)
-+		return 0x1;
-+	if (mem_clock <= 20000)
-+		return 0x2;
-+	if (mem_clock <= 25000)
-+		return 0x3;
-+	if (mem_clock <= 30000)
-+		return 0x4;
-+	if (mem_clock <= 35000)
-+		return 0x5;
-+	if (mem_clock <= 40000)
-+		return 0x6;
-+	if (mem_clock <= 45000)
-+		return 0x7;
-+	if (mem_clock <= 50000)
-+		return 0x8;
-+	if (mem_clock <= 55000)
-+		return 0x9;
-+	if (mem_clock <= 60000)
-+		return 0xa;
-+	if (mem_clock <= 65000)
-+		return 0xb;
-+	if (mem_clock <= 70000)
-+		return 0xc;
-+	if (mem_clock <= 75000)
-+		return 0xd;
-+	if (mem_clock <= 80000)
-+		return 0xe;
-+	/* mem_clock > 800MHz */
-+	return 0xf;
-+}
-+
-+static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
-+    uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
-+{
-+	struct pp_atomctrl_memory_clock_param mem_param;
-+	int result;
-+
-+	result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+			"Failed to get Memory PLL Dividers.",
-+			);
-+
-+	/* Save the result data to outpupt memory level structure */
-+	mclk->MclkFrequency   = clock;
-+	mclk->MclkDivider     = (uint8_t)mem_param.mpll_post_divider;
-+	mclk->FreqRange       = fiji_get_mclk_frequency_ratio(clock);
-+
-+	return result;
-+}
-+
-+static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	int result = 0;
-+	uint32_t mclk_stutter_mode_threshold = 60000;
-+
-+	if (table_info->vdd_dep_on_mclk) {
-+		result = fiji_get_dependency_volt_by_clk(hwmgr,
-+				table_info->vdd_dep_on_mclk, clock,
-+				(uint32_t *)(&mem_level->MinVoltage), &mem_level->MinMvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find MinVddc voltage value from memory "
-+				"VDDC voltage dependency table", return result);
-+	}
-+
-+	mem_level->EnabledForThrottle = 1;
-+	mem_level->EnabledForActivity = 0;
-+	mem_level->UpHyst = 0;
-+	mem_level->DownHyst = 100;
-+	mem_level->VoltageDownHyst = 0;
-+	mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
-+	mem_level->StutterEnable = false;
-+
-+	mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	/* enable stutter mode if all the follow condition applied
-+	 * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
-+	 * &(data->DisplayTiming.numExistingDisplays));
-+	 */
-+	data->display_timing.num_existing_displays = 1;
-+
-+	if (mclk_stutter_mode_threshold &&
-+		(clock <= mclk_stutter_mode_threshold) &&
-+		(!data->is_uvd_enabled) &&
-+		(PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
-+				STUTTER_ENABLE) & 0x1))
-+		mem_level->StutterEnable = true;
-+
-+	result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
-+	if (!result) {
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_dpm_table *dpm_table = &data->dpm_table;
-+	int result;
-+	/* populate MCLK dpm table to SMU7 */
-+	uint32_t array = smu_data->smu7_data.dpm_table_start +
-+			offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
-+	uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
-+			SMU73_MAX_LEVELS_MEMORY;
-+	struct SMU73_Discrete_MemoryLevel *levels =
-+			smu_data->smc_state_table.MemoryLevel;
-+	uint32_t i;
-+
-+	for (i = 0; i < dpm_table->mclk_table.count; i++) {
-+		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
-+				"can not populate memory level as memory clock is zero",
-+				return -EINVAL);
-+		result = fiji_populate_single_memory_level(hwmgr,
-+				dpm_table->mclk_table.dpm_levels[i].value,
-+				&levels[i]);
-+		if (result)
-+			return result;
-+	}
-+
-+	/* Only enable level 0 for now. */
-+	levels[0].EnabledForActivity = 1;
-+
-+	/* in order to prevent MC activity from stutter mode to push DPM up.
-+	 * the UVD change complements this by putting the MCLK in
-+	 * a higher state by default such that we are not effected by
-+	 * up threshold or and MCLK DPM latency.
-+	 */
-+	levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
-+	CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
-+
-+	smu_data->smc_state_table.MemoryDpmLevelCount =
-+			(uint8_t)dpm_table->mclk_table.count;
-+	data->dpm_level_enable_mask.mclk_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
-+	/* set highest level watermark to high */
-+	levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
-+			PPSMC_DISPLAY_WATERMARK_HIGH;
-+
-+	/* level count will send to smc once at init smc table and never change */
-+	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
-+			(uint32_t)array_size, SMC_RAM_END);
-+
-+	return result;
-+}
-+
-+static int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
-+		uint32_t mclk, SMIO_Pattern *smio_pat)
-+{
-+	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint32_t i = 0;
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
-+		/* find mvdd value which clock is more than request */
-+		for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
-+			if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
-+				smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
-+				break;
-+			}
-+		}
-+		PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
-+				"MVDD Voltage is outside the supported range.",
-+				return -EINVAL);
-+	} else
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
-+		SMU73_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	SMIO_Pattern vol_level;
-+	uint32_t mvdd;
-+	uint16_t us_mvdd;
-+	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
-+	uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
-+
-+	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
-+
-+	if (!data->sclk_dpm_key_disabled) {
-+		/* Get MinVoltage and Frequency from DPM0,
-+		 * already converted to SMC_UL */
-+		table->ACPILevel.SclkFrequency =
-+				data->dpm_table.sclk_table.dpm_levels[0].value;
-+		result = fiji_get_dependency_volt_by_clk(hwmgr,
-+				table_info->vdd_dep_on_sclk,
-+				table->ACPILevel.SclkFrequency,
-+				(uint32_t *)(&table->ACPILevel.MinVoltage), &mvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Cannot find ACPI VDDC voltage value " \
-+				"in Clock Dependency Table",
-+				);
-+	} else {
-+		table->ACPILevel.SclkFrequency =
-+				data->vbios_boot_state.sclk_bootup_value;
-+		table->ACPILevel.MinVoltage =
-+				data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
-+	}
-+
-+	/* get the engine clock dividers for this clock value */
-+	result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
-+			table->ACPILevel.SclkFrequency,  &dividers);
-+	PP_ASSERT_WITH_CODE(result == 0,
-+			"Error retrieving Engine Clock dividers from VBIOS.",
-+			return result);
-+
-+	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
-+	table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+	table->ACPILevel.DeepSleepDivId = 0;
-+
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
-+			SPLL_PWRON, 0);
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
-+			SPLL_RESET, 1);
-+	spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
-+			SCLK_MUX_SEL, 4);
-+
-+	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
-+	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
-+	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
-+	table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
-+	table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
-+	table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
-+	table->ACPILevel.CcPwrDynRm = 0;
-+	table->ACPILevel.CcPwrDynRm1 = 0;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
-+
-+	if (!data->mclk_dpm_key_disabled) {
-+		/* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
-+		table->MemoryACPILevel.MclkFrequency =
-+				data->dpm_table.mclk_table.dpm_levels[0].value;
-+		result = fiji_get_dependency_volt_by_clk(hwmgr,
-+				table_info->vdd_dep_on_mclk,
-+				table->MemoryACPILevel.MclkFrequency,
-+			(uint32_t *)(&table->MemoryACPILevel.MinVoltage), &mvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"Cannot find ACPI VDDCI voltage value in Clock Dependency Table",
-+				);
-+	} else {
-+		table->MemoryACPILevel.MclkFrequency =
-+				data->vbios_boot_state.mclk_bootup_value;
-+		table->MemoryACPILevel.MinVoltage =
-+				data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
-+	}
-+
-+	us_mvdd = 0;
-+	if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
-+			(data->mclk_dpm_key_disabled))
-+		us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
-+	else {
-+		if (!fiji_populate_mvdd_value(hwmgr,
-+				data->dpm_table.mclk_table.dpm_levels[0].value,
-+				&vol_level))
-+			us_mvdd = vol_level.Voltage;
-+	}
-+
-+	table->MemoryACPILevel.MinMvdd =
-+			PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
-+
-+	table->MemoryACPILevel.EnabledForThrottle = 0;
-+	table->MemoryACPILevel.EnabledForActivity = 0;
-+	table->MemoryACPILevel.UpHyst = 0;
-+	table->MemoryACPILevel.DownHyst = 100;
-+	table->MemoryACPILevel.VoltageDownHyst = 0;
-+	table->MemoryACPILevel.ActivityLevel =
-+			PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
-+
-+	table->MemoryACPILevel.StutterEnable = false;
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
-+
-+	return result;
-+}
-+
-+static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
-+		SMU73_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+
-+	table->VceLevelCount = (uint8_t)(mm_table->count);
-+	table->VceBootLevel = 0;
-+
-+	for (count = 0; count < table->VceLevelCount; count++) {
-+		table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
-+		table->VceLevel[count].MinVoltage = 0;
-+		table->VceLevel[count].MinVoltage |=
-+				(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
-+		table->VceLevel[count].MinVoltage |=
-+				((mm_table->entries[count].vddc - VDDC_VDDCI_DELTA) *
-+						VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/*retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->VceLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for VCE engine clock",
-+				return result);
-+
-+		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
-+		SMU73_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+
-+	table->AcpLevelCount = (uint8_t)(mm_table->count);
-+	table->AcpBootLevel = 0;
-+
-+	for (count = 0; count < table->AcpLevelCount; count++) {
-+		table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
-+		table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-+				VOLTAGE_SCALE) << VDDC_SHIFT;
-+		table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
-+				VDDC_VDDCI_DELTA) * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->AcpLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for engine clock", return result);
-+
-+		table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-+		SMU73_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+
-+	table->SamuBootLevel = 0;
-+	table->SamuLevelCount = (uint8_t)(mm_table->count);
-+
-+	for (count = 0; count < table->SamuLevelCount; count++) {
-+		/* not sure whether we need evclk or not */
-+		table->SamuLevel[count].MinVoltage = 0;
-+		table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
-+		table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-+				VOLTAGE_SCALE) << VDDC_SHIFT;
-+		table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
-+				VDDC_VDDCI_DELTA) * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->SamuLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for samu clock", return result);
-+
-+		table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
-+		int32_t eng_clock, int32_t mem_clock,
-+		struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
-+{
-+	uint32_t dram_timing;
-+	uint32_t dram_timing2;
-+	uint32_t burstTime;
-+	ULONG state, trrds, trrdl;
-+	int result;
-+
-+	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
-+			eng_clock, mem_clock);
-+	PP_ASSERT_WITH_CODE(result == 0,
-+			"Error calling VBIOS to set DRAM_TIMING.", return result);
-+
-+	dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
-+	dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
-+	burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
-+
-+	state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
-+	trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
-+	trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
-+
-+	arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
-+	arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
-+	arb_regs->McArbBurstTime   = (uint8_t)burstTime;
-+	arb_regs->TRRDS            = (uint8_t)trrds;
-+	arb_regs->TRRDL            = (uint8_t)trrdl;
-+
-+	return 0;
-+}
-+
-+static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
-+	uint32_t i, j;
-+	int result = 0;
-+
-+	for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
-+		for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
-+			result = fiji_populate_memory_timing_parameters(hwmgr,
-+					data->dpm_table.sclk_table.dpm_levels[i].value,
-+					data->dpm_table.mclk_table.dpm_levels[j].value,
-+					&arb_regs.entries[i][j]);
-+			if (result)
-+				break;
-+		}
-+	}
-+
-+	if (!result)
-+		result = smu7_copy_bytes_to_smc(
-+				hwmgr,
-+				smu_data->smu7_data.arb_table_start,
-+				(uint8_t *)&arb_regs,
-+				sizeof(SMU73_Discrete_MCArbDramTimingTable),
-+				SMC_RAM_END);
-+	return result;
-+}
-+
-+static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+
-+	table->UvdLevelCount = (uint8_t)(mm_table->count);
-+	table->UvdBootLevel = 0;
-+
-+	for (count = 0; count < table->UvdLevelCount; count++) {
-+		table->UvdLevel[count].MinVoltage = 0;
-+		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
-+		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
-+		table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-+				VOLTAGE_SCALE) << VDDC_SHIFT;
-+		table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
-+				VDDC_VDDCI_DELTA) * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->UvdLevel[count].VclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for Vclk clock", return result);
-+
-+		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
-+
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->UvdLevel[count].DclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for Dclk clock", return result);
-+
-+		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
-+
-+	}
-+	return result;
-+}
-+
-+static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	table->GraphicsBootLevel = 0;
-+	table->MemoryBootLevel = 0;
-+
-+	/* find boot level from dpm table */
-+	result = phm_find_boot_level(&(data->dpm_table.sclk_table),
-+			data->vbios_boot_state.sclk_bootup_value,
-+			(uint32_t *)&(table->GraphicsBootLevel));
-+
-+	result = phm_find_boot_level(&(data->dpm_table.mclk_table),
-+			data->vbios_boot_state.mclk_bootup_value,
-+			(uint32_t *)&(table->MemoryBootLevel));
-+
-+	table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
-+			VOLTAGE_SCALE;
-+	table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
-+			VOLTAGE_SCALE;
-+	table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
-+			VOLTAGE_SCALE;
-+
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint8_t count, level;
-+
-+	count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
-+	for (level = 0; level < count; level++) {
-+		if (table_info->vdd_dep_on_sclk->entries[level].clk >=
-+				data->vbios_boot_state.sclk_bootup_value) {
-+			smu_data->smc_state_table.GraphicsBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
-+	for (level = 0; level < count; level++) {
-+		if (table_info->vdd_dep_on_mclk->entries[level].clk >=
-+				data->vbios_boot_state.mclk_bootup_value) {
-+			smu_data->smc_state_table.MemoryBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
-+			volt_with_cks, value;
-+	uint16_t clock_freq_u16;
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
-+			volt_offset = 0;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+
-+	stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
-+
-+	/* Read SMU_Eefuse to read and calculate RO and determine
-+	 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
-+	 */
-+	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixSMU_EFUSE_0 + (146 * 4));
-+	efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixSMU_EFUSE_0 + (148 * 4));
-+	efuse &= 0xFF000000;
-+	efuse = efuse >> 24;
-+	efuse2 &= 0xF;
-+
-+	if (efuse2 == 1)
-+		ro = (2300 - 1350) * efuse / 255 + 1350;
-+	else
-+		ro = (2500 - 1000) * efuse / 255 + 1000;
-+
-+	if (ro >= 1660)
-+		type = 0;
-+	else
-+		type = 1;
-+
-+	/* Populate Stretch amount */
-+	smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
-+
-+	/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
-+	for (i = 0; i < sclk_table->count; i++) {
-+		smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
-+				sclk_table->entries[i].cks_enable << i;
-+		volt_without_cks = (uint32_t)((14041 *
-+			(sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
-+			(4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
-+		volt_with_cks = (uint32_t)((13946 *
-+			(sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
-+			(3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
-+		if (volt_without_cks >= volt_with_cks)
-+			volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
-+					sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
-+		smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
-+	}
-+
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			STRETCH_ENABLE, 0x0);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			masterReset, 0x1);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			staticEnable, 0x1);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			masterReset, 0x0);
-+
-+	/* Populate CKS Lookup Table */
-+	if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
-+		stretch_amount2 = 0;
-+	else if (stretch_amount == 3 || stretch_amount == 4)
-+		stretch_amount2 = 1;
-+	else {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ClockStretcher);
-+		PP_ASSERT_WITH_CODE(false,
-+				"Stretch Amount in PPTable not supported\n",
-+				return -EINVAL);
-+	}
-+
-+	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixPWR_CKS_CNTL);
-+	value &= 0xFFC2FF87;
-+	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
-+			fiji_clock_stretcher_lookup_table[stretch_amount2][0];
-+	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
-+			fiji_clock_stretcher_lookup_table[stretch_amount2][1];
-+	clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table.
-+			GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
-+			SclkFrequency) / 100);
-+	if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
-+			clock_freq_u16 &&
-+	    fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
-+			clock_freq_u16) {
-+		/* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
-+		value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
-+		/* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
-+		value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
-+		/* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
-+		value |= (fiji_clock_stretch_amount_conversion
-+				[fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
-+				 [stretch_amount]) << 3;
-+	}
-+	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
-+			CKS_LOOKUPTableEntry[0].minFreq);
-+	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
-+			CKS_LOOKUPTableEntry[0].maxFreq);
-+	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
-+			fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
-+	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
-+			(fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixPWR_CKS_CNTL, value);
-+
-+	/* Populate DDT Lookup Table */
-+	for (i = 0; i < 4; i++) {
-+		/* Assign the minimum and maximum VID stored
-+		 * in the last row of Clock Stretcher Voltage Table.
-+		 */
-+		smu_data->smc_state_table.ClockStretcherDataTable.
-+		ClockStretcherDataTableEntry[i].minVID =
-+				(uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
-+		smu_data->smc_state_table.ClockStretcherDataTable.
-+		ClockStretcherDataTableEntry[i].maxVID =
-+				(uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
-+		/* Loop through each SCLK and check the frequency
-+		 * to see if it lies within the frequency for clock stretcher.
-+		 */
-+		for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) {
-+			cks_setting = 0;
-+			clock_freq = PP_SMC_TO_HOST_UL(
-+					smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
-+			/* Check the allowed frequency against the sclk level[j].
-+			 *  Sclk's endianness has already been converted,
-+			 *  and it's in 10Khz unit,
-+			 *  as opposed to Data table, which is in Mhz unit.
-+			 */
-+			if (clock_freq >=
-+					(fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
-+				cks_setting |= 0x2;
-+				if (clock_freq <
-+						(fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
-+					cks_setting |= 0x1;
-+			}
-+			smu_data->smc_state_table.ClockStretcherDataTable.
-+			ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
-+		}
-+		CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.
-+				ClockStretcherDataTable.
-+				ClockStretcherDataTableEntry[i].setting);
-+	}
-+
-+	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
-+	value &= 0xFFFFFFFE;
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
-+
-+	return 0;
-+}
-+
-+static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
-+		struct SMU73_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint16_t config;
-+
-+	config = VR_MERGED_WITH_VDDC;
-+	table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
-+
-+	/* Set Vddc Voltage Controller */
-+	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+		config = VR_SVI2_PLANE_1;
-+		table->VRConfig |= config;
-+	} else {
-+		PP_ASSERT_WITH_CODE(false,
-+				"VDDC should be on SVI2 control in merged mode!",
-+				);
-+	}
-+	/* Set Vddci Voltage Controller */
-+	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
-+		config = VR_SVI2_PLANE_2;  /* only in merged mode */
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	} else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
-+		config = VR_SMIO_PATTERN_1;
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	} else {
-+		config = VR_STATIC_VOLTAGE;
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	}
-+	/* Set Mvdd Voltage Controller */
-+	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
-+		config = VR_SVI2_PLANE_2;
-+		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
-+	} else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		config = VR_SMIO_PATTERN_2;
-+		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
-+	} else {
-+		config = VR_STATIC_VOLTAGE;
-+		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
-+	}
-+
-+	return 0;
-+}
-+
-+static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	uint32_t tmp;
-+	int result;
-+
-+	/* This is a read-modify-write on the first byte of the ARB table.
-+	 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
-+	 * is the field 'current'.
-+	 * This solution is ugly, but we never write the whole table only
-+	 * individual fields in it.
-+	 * In reality this field should not be in that structure
-+	 * but in a soft register.
-+	 */
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+			smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
-+
-+	if (result)
-+		return result;
-+
-+	tmp &= 0x00FFFFFF;
-+	tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
-+
-+	return smu7_write_smc_sram_dword(hwmgr,
-+			smu_data->smu7_data.arb_table_start,  tmp, SMC_RAM_END);
-+}
-+
-+static int fiji_save_default_power_profile(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_smumgr *data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	struct SMU73_Discrete_GraphicsLevel *levels =
-+				data->smc_state_table.GraphicsLevel;
-+	unsigned min_level = 1;
-+
-+	hwmgr->default_gfx_power_profile.activity_threshold =
-+			be16_to_cpu(levels[0].ActivityLevel);
-+	hwmgr->default_gfx_power_profile.up_hyst = levels[0].UpHyst;
-+	hwmgr->default_gfx_power_profile.down_hyst = levels[0].DownHyst;
-+	hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
-+
-+	hwmgr->default_compute_power_profile = hwmgr->default_gfx_power_profile;
-+	hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
-+
-+	/* Workaround compute SDMA instability: disable lowest SCLK
-+	 * DPM level. Optimize compute power profile: Use only highest
-+	 * 2 power levels (if more than 2 are available), Hysteresis:
-+	 * 0ms up, 5ms down
-+	 */
-+	if (data->smc_state_table.GraphicsDpmLevelCount > 2)
-+		min_level = data->smc_state_table.GraphicsDpmLevelCount - 2;
-+	else if (data->smc_state_table.GraphicsDpmLevelCount == 2)
-+		min_level = 1;
-+	else
-+		min_level = 0;
-+	hwmgr->default_compute_power_profile.min_sclk =
-+			be32_to_cpu(levels[min_level].SclkFrequency);
-+	hwmgr->default_compute_power_profile.up_hyst = 0;
-+	hwmgr->default_compute_power_profile.down_hyst = 5;
-+
-+	hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
-+	hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
-+
-+	return 0;
-+}
-+
-+static int fiji_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
-+{
-+	pp_atomctrl_voltage_table param_led_dpm;
-+	int result = 0;
-+	u32 mask = 0;
-+
-+	result = atomctrl_get_voltage_table_v3(hwmgr,
-+					       VOLTAGE_TYPE_LEDDPM, VOLTAGE_OBJ_GPIO_LUT,
-+					       &param_led_dpm);
-+	if (result == 0) {
-+		int i, j;
-+		u32 tmp = param_led_dpm.mask_low;
-+
-+		for (i = 0, j = 0; i < 32; i++) {
-+			if (tmp & 1) {
-+				mask |= (i << (8 * j));
-+				if (++j >= 3)
-+					break;
-+			}
-+			tmp >>= 1;
-+		}
-+	}
-+	if (mask)
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
-+						    PPSMC_MSG_LedConfig,
-+						    mask);
-+	return 0;
-+}
-+
-+static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct SMU73_Discrete_DpmTable *table = &(smu_data->smc_state_table);
-+	uint8_t i;
-+	struct pp_atomctrl_gpio_pin_assignment gpio_pin;
-+
-+	fiji_initialize_power_tune_defaults(hwmgr);
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control)
-+		fiji_populate_smc_voltage_tables(hwmgr, table);
-+
-+	table->SystemFlags = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StepVddc))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
-+
-+	if (data->is_memory_gddr5)
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
-+
-+	if (data->ulv_supported && table_info->us_ulv_voltage_offset) {
-+		result = fiji_populate_ulv_state(hwmgr, table);
-+		PP_ASSERT_WITH_CODE(0 == result,
-+				"Failed to initialize ULV state!", return result);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixCG_ULV_PARAMETER, 0x40035);
-+	}
-+
-+	result = fiji_populate_smc_link_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Link Level!", return result);
-+
-+	result = fiji_populate_all_graphic_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Graphics Level!", return result);
-+
-+	result = fiji_populate_all_memory_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Memory Level!", return result);
-+
-+	result = fiji_populate_smc_acpi_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize ACPI Level!", return result);
-+
-+	result = fiji_populate_smc_vce_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize VCE Level!", return result);
-+
-+	result = fiji_populate_smc_acp_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize ACP Level!", return result);
-+
-+	result = fiji_populate_smc_samu_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize SAMU Level!", return result);
-+
-+	/* Since only the initial state is completely set up at this point
-+	 * (the other states are just copies of the boot state) we only
-+	 * need to populate the  ARB settings for the initial state.
-+	 */
-+	result = fiji_program_memory_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to Write ARB settings for the initial state.", return result);
-+
-+	result = fiji_populate_smc_uvd_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize UVD Level!", return result);
-+
-+	result = fiji_populate_smc_boot_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Boot Level!", return result);
-+
-+	result = fiji_populate_smc_initailial_state(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Boot State!", return result);
-+
-+	result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to populate BAPM Parameters!", return result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ClockStretcher)) {
-+		result = fiji_populate_clock_stretcher_data_table(hwmgr);
-+		PP_ASSERT_WITH_CODE(0 == result,
-+				"Failed to populate Clock Stretcher Data Table!",
-+				return result);
-+	}
-+
-+	table->GraphicsVoltageChangeEnable  = 1;
-+	table->GraphicsThermThrottleEnable  = 1;
-+	table->GraphicsInterval = 1;
-+	table->VoltageInterval  = 1;
-+	table->ThermalInterval  = 1;
-+	table->TemperatureLimitHigh =
-+			table_info->cac_dtp_table->usTargetOperatingTemp *
-+			SMU7_Q88_FORMAT_CONVERSION_UNIT;
-+	table->TemperatureLimitLow  =
-+			(table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
-+			SMU7_Q88_FORMAT_CONVERSION_UNIT;
-+	table->MemoryVoltageChangeEnable = 1;
-+	table->MemoryInterval = 1;
-+	table->VoltageResponseTime = 0;
-+	table->PhaseResponseTime = 0;
-+	table->MemoryThermThrottleEnable = 1;
-+	table->PCIeBootLinkLevel = 0;      /* 0:Gen1 1:Gen2 2:Gen3*/
-+	table->PCIeGenInterval = 1;
-+	table->VRConfig = 0;
-+
-+	result = fiji_populate_vr_config(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to populate VRConfig setting!", return result);
-+
-+	table->ThermGpio = 17;
-+	table->SclkStepSize = 0x4000;
-+
-+	if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
-+		table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_RegulatorHot);
-+	} else {
-+		table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_RegulatorHot);
-+	}
-+
-+	if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
-+			&gpio_pin)) {
-+		table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_AutomaticDCTransition);
-+	} else {
-+		table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_AutomaticDCTransition);
-+	}
-+
-+	/* Thermal Output GPIO */
-+	if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
-+			&gpio_pin)) {
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ThermalOutGPIO);
-+
-+		table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+
-+		/* For porlarity read GPIOPAD_A with assigned Gpio pin
-+		 * since VBIOS will program this register to set 'inactive state',
-+		 * driver can then determine 'active state' from this and
-+		 * program SMU with correct polarity
-+		 */
-+		table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
-+				(1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
-+		table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
-+
-+		/* if required, combine VRHot/PCC with thermal out GPIO */
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_RegulatorHot) &&
-+			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_CombinePCCWithThermalSignal))
-+			table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
-+	} else {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ThermalOutGPIO);
-+		table->ThermOutGpio = 17;
-+		table->ThermOutPolarity = 1;
-+		table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
-+	}
-+
-+	for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++)
-+		table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
-+
-+	/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
-+	result = smu7_copy_bytes_to_smc(hwmgr,
-+			smu_data->smu7_data.dpm_table_start +
-+			offsetof(SMU73_Discrete_DpmTable, SystemFlags),
-+			(uint8_t *)&(table->SystemFlags),
-+			sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
-+			SMC_RAM_END);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to upload dpm data to SMC memory!", return result);
-+
-+	result = fiji_init_arb_table_index(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to upload arb data to SMC memory!", return result);
-+
-+	result = fiji_populate_pm_fuses(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to  populate PM fuses to SMC memory!", return result);
-+
-+	result = fiji_setup_dpm_led_config(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			    "Failed to setup dpm led config", return result);
-+
-+	fiji_save_default_power_profile(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+
-+	SMU73_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
-+	uint32_t duty100;
-+	uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
-+	uint16_t fdo_min, slope1, slope2;
-+	uint32_t reference_clock;
-+	int res;
-+	uint64_t tmp64;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	if (smu_data->smu7_data.fan_table_start == 0) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL1, FMAX_DUTY100);
-+
-+	if (duty100 == 0) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
-+			usPWMMin * duty100;
-+	do_div(tmp64, 10000);
-+	fdo_min = (uint16_t)tmp64;
-+
-+	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
-+	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
-+
-+	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
-+	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
-+
-+	slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
-+	slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
-+
-+	fan_table.TempMin = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMin) / 100);
-+	fan_table.TempMed = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMed) / 100);
-+	fan_table.TempMax = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMax) / 100);
-+
-+	fan_table.Slope1 = cpu_to_be16(slope1);
-+	fan_table.Slope2 = cpu_to_be16(slope2);
-+
-+	fan_table.FdoMin = cpu_to_be16(fdo_min);
-+
-+	fan_table.HystDown = cpu_to_be16(hwmgr->
-+			thermal_controller.advanceFanControlParameters.ucTHyst);
-+
-+	fan_table.HystUp = cpu_to_be16(1);
-+
-+	fan_table.HystSlope = cpu_to_be16(1);
-+
-+	fan_table.TempRespLim = cpu_to_be16(5);
-+
-+	reference_clock = smu7_get_xclk(hwmgr);
-+
-+	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
-+			thermal_controller.advanceFanControlParameters.ulCycleDelay *
-+			reference_clock) / 1600);
-+
-+	fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
-+
-+	fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
-+			hwmgr->device, CGS_IND_REG__SMC,
-+			CG_MULT_THERMAL_CTRL, TEMP_SEL);
-+
-+	res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
-+			(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
-+			SMC_RAM_END);
-+
-+	if (!res && hwmgr->thermal_controller.
-+			advanceFanControlParameters.ucMinimumPWMLimit)
-+		res = smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_SetFanMinPwm,
-+				hwmgr->thermal_controller.
-+				advanceFanControlParameters.ucMinimumPWMLimit);
-+
-+	if (!res && hwmgr->thermal_controller.
-+			advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
-+		res = smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_SetFanSclkTarget,
-+				hwmgr->thermal_controller.
-+				advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
-+
-+	if (res)
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+
-+	return 0;
-+}
-+
-+
-+static int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
-+{
-+	int ret;
-+	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
-+
-+	if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS)
-+		return 0;
-+
-+	ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
-+
-+	if (!ret)
-+		/* If this param is not changed, this function could fire unnecessarily */
-+		smu_data->avfs.avfs_btc_status = AVFS_BTC_COMPLETED_PREVIOUSLY;
-+
-+	return ret;
-+}
-+
-+static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	if (data->need_update_smu7_dpm_table &
-+		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
-+		return fiji_program_memory_timing_parameters(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+
-+	int result = 0;
-+	uint32_t low_sclk_interrupt_threshold = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkThrottleLowNotification)
-+		&& (hwmgr->gfx_arbiter.sclk_threshold !=
-+				data->low_sclk_interrupt_threshold)) {
-+		data->low_sclk_interrupt_threshold =
-+				hwmgr->gfx_arbiter.sclk_threshold;
-+		low_sclk_interrupt_threshold =
-+				data->low_sclk_interrupt_threshold;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
-+
-+		result = smu7_copy_bytes_to_smc(
-+				hwmgr,
-+				smu_data->smu7_data.dpm_table_start +
-+				offsetof(SMU73_Discrete_DpmTable,
-+					LowSclkInterruptThreshold),
-+				(uint8_t *)&low_sclk_interrupt_threshold,
-+				sizeof(uint32_t),
-+				SMC_RAM_END);
-+	}
-+	result = fiji_program_mem_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			"Failed to program memory timing parameters!",
-+			);
-+	return result;
-+}
-+
-+static uint32_t fiji_get_offsetof(uint32_t type, uint32_t member)
-+{
-+	switch (type) {
-+	case SMU_SoftRegisters:
-+		switch (member) {
-+		case HandshakeDisables:
-+			return offsetof(SMU73_SoftRegisters, HandshakeDisables);
-+		case VoltageChangeTimeout:
-+			return offsetof(SMU73_SoftRegisters, VoltageChangeTimeout);
-+		case AverageGraphicsActivity:
-+			return offsetof(SMU73_SoftRegisters, AverageGraphicsActivity);
-+		case PreVBlankGap:
-+			return offsetof(SMU73_SoftRegisters, PreVBlankGap);
-+		case VBlankTimeout:
-+			return offsetof(SMU73_SoftRegisters, VBlankTimeout);
-+		case UcodeLoadStatus:
-+			return offsetof(SMU73_SoftRegisters, UcodeLoadStatus);
-+		case DRAM_LOG_ADDR_H:
-+			return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_H);
-+		case DRAM_LOG_ADDR_L:
-+			return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_L);
-+		case DRAM_LOG_PHY_ADDR_H:
-+			return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
-+		case DRAM_LOG_PHY_ADDR_L:
-+			return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
-+		case DRAM_LOG_BUFF_SIZE:
-+			return offsetof(SMU73_SoftRegisters, DRAM_LOG_BUFF_SIZE);
-+		}
-+	case SMU_Discrete_DpmTable:
-+		switch (member) {
-+		case UvdBootLevel:
-+			return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
-+		case VceBootLevel:
-+			return offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
-+		case SamuBootLevel:
-+			return offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
-+		case LowSclkInterruptThreshold:
-+			return offsetof(SMU73_Discrete_DpmTable, LowSclkInterruptThreshold);
-+		}
-+	}
-+	pr_warn("can't get the offset of type %x member %x\n", type, member);
-+	return 0;
-+}
-+
-+static uint32_t fiji_get_mac_definition(uint32_t value)
-+{
-+	switch (value) {
-+	case SMU_MAX_LEVELS_GRAPHICS:
-+		return SMU73_MAX_LEVELS_GRAPHICS;
-+	case SMU_MAX_LEVELS_MEMORY:
-+		return SMU73_MAX_LEVELS_MEMORY;
-+	case SMU_MAX_LEVELS_LINK:
-+		return SMU73_MAX_LEVELS_LINK;
-+	case SMU_MAX_ENTRIES_SMIO:
-+		return SMU73_MAX_ENTRIES_SMIO;
-+	case SMU_MAX_LEVELS_VDDC:
-+		return SMU73_MAX_LEVELS_VDDC;
-+	case SMU_MAX_LEVELS_VDDGFX:
-+		return SMU73_MAX_LEVELS_VDDGFX;
-+	case SMU_MAX_LEVELS_VDDCI:
-+		return SMU73_MAX_LEVELS_VDDCI;
-+	case SMU_MAX_LEVELS_MVDD:
-+		return SMU73_MAX_LEVELS_MVDD;
-+	}
-+
-+	pr_warn("can't get the mac of %x\n", value);
-+	return 0;
-+}
-+
-+
-+static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	smu_data->smc_state_table.UvdBootLevel = 0;
-+	if (table_info->mm_dep_table->count > 0)
-+		smu_data->smc_state_table.UvdBootLevel =
-+				(uint8_t) (table_info->mm_dep_table->count - 1);
-+	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable,
-+						UvdBootLevel);
-+	mm_boot_level_offset /= 4;
-+	mm_boot_level_offset *= 4;
-+	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset);
-+	mm_boot_level_value &= 0x00FFFFFF;
-+	mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
-+	cgs_write_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_UVDDPM) ||
-+		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StablePState))
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_UVDDPM_SetEnabledMask,
-+				(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
-+	return 0;
-+}
-+
-+static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_StablePState))
-+		smu_data->smc_state_table.VceBootLevel =
-+			(uint8_t) (table_info->mm_dep_table->count - 1);
-+	else
-+		smu_data->smc_state_table.VceBootLevel = 0;
-+
-+	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
-+					offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
-+	mm_boot_level_offset /= 4;
-+	mm_boot_level_offset *= 4;
-+	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset);
-+	mm_boot_level_value &= 0xFF00FFFF;
-+	mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
-+	cgs_write_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_VCEDPM_SetEnabledMask,
-+				(uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
-+	return 0;
-+}
-+
-+static int fiji_update_samu_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+
-+
-+	smu_data->smc_state_table.SamuBootLevel = 0;
-+	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
-+				offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
-+
-+	mm_boot_level_offset /= 4;
-+	mm_boot_level_offset *= 4;
-+	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset);
-+	mm_boot_level_value &= 0xFFFFFF00;
-+	mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
-+	cgs_write_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StablePState))
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_SAMUDPM_SetEnabledMask,
-+				(uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
-+	return 0;
-+}
-+
-+static int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
-+{
-+	switch (type) {
-+	case SMU_UVD_TABLE:
-+		fiji_update_uvd_smc_table(hwmgr);
-+		break;
-+	case SMU_VCE_TABLE:
-+		fiji_update_vce_smc_table(hwmgr);
-+		break;
-+	case SMU_SAMU_TABLE:
-+		fiji_update_samu_smc_table(hwmgr);
-+		break;
-+	default:
-+		break;
-+	}
-+	return 0;
-+}
-+
-+static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
-+	uint32_t tmp;
-+	int result;
-+	bool error = false;
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU73_Firmware_Header, DpmTable),
-+			&tmp, SMC_RAM_END);
-+
-+	if (0 == result)
-+		smu_data->smu7_data.dpm_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU73_Firmware_Header, SoftRegisters),
-+			&tmp, SMC_RAM_END);
-+
-+	if (!result) {
-+		data->soft_regs_start = tmp;
-+		smu_data->smu7_data.soft_regs_start = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU73_Firmware_Header, mcRegisterTable),
-+			&tmp, SMC_RAM_END);
-+
-+	if (!result)
-+		smu_data->smu7_data.mc_reg_table_start = tmp;
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU73_Firmware_Header, FanTable),
-+			&tmp, SMC_RAM_END);
-+
-+	if (!result)
-+		smu_data->smu7_data.fan_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
-+			&tmp, SMC_RAM_END);
-+
-+	if (!result)
-+		smu_data->smu7_data.arb_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU73_Firmware_Header, Version),
-+			&tmp, SMC_RAM_END);
-+
-+	if (!result)
-+		hwmgr->microcode_version_info.SMC = tmp;
-+
-+	error |= (0 != result);
-+
-+	return error ? -1 : 0;
-+}
-+
-+static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
-+{
-+
-+	/* Program additional LP registers
-+	 * that are no longer programmed by VBIOS
-+	 */
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
-+
-+	return 0;
-+}
-+
-+static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
-+{
-+	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
-+			CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
-+			? true : false;
-+}
-+
-+static int fiji_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
-+		struct amd_pp_profile *request)
-+{
-+	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)
-+			(hwmgr->smu_backend);
-+	struct SMU73_Discrete_GraphicsLevel *levels =
-+			smu_data->smc_state_table.GraphicsLevel;
-+	uint32_t array = smu_data->smu7_data.dpm_table_start +
-+			offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
-+	uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
-+			SMU73_MAX_LEVELS_GRAPHICS;
-+	uint32_t i;
-+
-+	for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
-+		levels[i].ActivityLevel =
-+				cpu_to_be16(request->activity_threshold);
-+		levels[i].EnabledForActivity = 1;
-+		levels[i].UpHyst = request->up_hyst;
-+		levels[i].DownHyst = request->down_hyst;
-+	}
-+
-+	return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
-+				array_size, SMC_RAM_END);
-+}
- 
- const struct pp_smumgr_func fiji_smu_funcs = {
- 	.smu_init = &fiji_smu_init,
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.h	2017-12-14 06:39:58.482903614 +0100
-@@ -28,6 +28,15 @@
- #include "smu7_smumgr.h"
- 
- 
-+struct fiji_pt_defaults {
-+	uint8_t   SviLoadLineEn;
-+	uint8_t   SviLoadLineVddC;
-+	uint8_t   TDC_VDDC_ThrottleReleaseLimitPerc;
-+	uint8_t   TDC_MAWt;
-+	uint8_t   TdcWaterfallCtl;
-+	uint8_t   DTEAmbientTempBase;
-+};
-+
- struct fiji_smumgr {
- 	struct smu7_smumgr                   smu7_data;
- 	struct SMU73_Discrete_DpmTable       smc_state_table;
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c	2017-12-14 06:39:58.483903615 +0100
-@@ -30,64 +30,133 @@
- 
- #include "smumgr.h"
- #include "iceland_smumgr.h"
--#include "smu_ucode_xfer_vi.h"
-+
- #include "ppsmc.h"
-+
-+#include "cgs_common.h"
-+
-+#include "smu7_dyn_defaults.h"
-+#include "smu7_hwmgr.h"
-+#include "hardwaremanager.h"
-+#include "ppatomctrl.h"
-+#include "atombios.h"
-+#include "pppcielanes.h"
-+#include "pp_endian.h"
-+#include "processpptables.h"
-+
-+
- #include "smu/smu_7_1_1_d.h"
- #include "smu/smu_7_1_1_sh_mask.h"
--#include "cgs_common.h"
--#include "iceland_smc.h"
-+#include "smu71_discrete.h"
-+
-+#include "smu_ucode_xfer_vi.h"
-+#include "gmc/gmc_8_1_d.h"
-+#include "gmc/gmc_8_1_sh_mask.h"
-+#include "bif/bif_5_0_d.h"
-+#include "bif/bif_5_0_sh_mask.h"
-+#include "dce/dce_10_0_d.h"
-+#include "dce/dce_10_0_sh_mask.h"
-+
- 
- #define ICELAND_SMC_SIZE               0x20000
- 
--static int iceland_start_smc(struct pp_smumgr *smumgr)
-+#define VOLTAGE_SCALE 4
-+#define POWERTUNE_DEFAULT_SET_MAX    1
-+#define VOLTAGE_VID_OFFSET_SCALE1   625
-+#define VOLTAGE_VID_OFFSET_SCALE2   100
-+#define MC_CG_ARB_FREQ_F1           0x0b
-+#define VDDC_VDDCI_DELTA            200
-+
-+#define DEVICE_ID_VI_ICELAND_M_6900	0x6900
-+#define DEVICE_ID_VI_ICELAND_M_6901	0x6901
-+#define DEVICE_ID_VI_ICELAND_M_6902	0x6902
-+#define DEVICE_ID_VI_ICELAND_M_6903	0x6903
-+
-+static const struct iceland_pt_defaults defaults_iceland = {
-+	/*
-+	 * sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc,
-+	 * TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT
-+	 */
-+	1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
-+	{ 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
-+	{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
-+};
-+
-+/* 35W - XT, XTL */
-+static const struct iceland_pt_defaults defaults_icelandxt = {
-+	/*
-+	 * sviLoadLIneEn, SviLoadLineVddC,
-+	 * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
-+	 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
-+	 * BAPM_TEMP_GRADIENT
-+	 */
-+	1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
-+	{ 0xA7,  0x0, 0x0, 0xB5,  0x0, 0x0, 0x9F,  0x0, 0x0, 0xD6,  0x0, 0x0, 0xD7,  0x0, 0x0},
-+	{ 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
-+};
-+
-+/* 25W - PRO, LE */
-+static const struct iceland_pt_defaults defaults_icelandpro = {
-+	/*
-+	 * sviLoadLIneEn, SviLoadLineVddC,
-+	 * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
-+	 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
-+	 * BAPM_TEMP_GRADIENT
-+	 */
-+	1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
-+	{ 0xB7,  0x0, 0x0, 0xC3,  0x0, 0x0, 0xB5,  0x0, 0x0, 0xEA,  0x0, 0x0, 0xE6,  0x0, 0x0},
-+	{ 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
-+};
-+
-+static int iceland_start_smc(struct pp_hwmgr *hwmgr)
- {
--	SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 				  SMC_SYSCON_RESET_CNTL, rst_reg, 0);
- 
- 	return 0;
- }
- 
--static void iceland_reset_smc(struct pp_smumgr *smumgr)
-+static void iceland_reset_smc(struct pp_hwmgr *hwmgr)
- {
--	SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 				  SMC_SYSCON_RESET_CNTL,
- 				  rst_reg, 1);
- }
- 
- 
--static void iceland_stop_smc_clock(struct pp_smumgr *smumgr)
-+static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr)
- {
--	SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 				  SMC_SYSCON_CLOCK_CNTL_0,
- 				  ck_disable, 1);
- }
- 
--static void iceland_start_smc_clock(struct pp_smumgr *smumgr)
-+static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr)
- {
--	SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 				  SMC_SYSCON_CLOCK_CNTL_0,
- 				  ck_disable, 0);
- }
- 
--static int iceland_smu_start_smc(struct pp_smumgr *smumgr)
-+static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr)
- {
- 	/* set smc instruct start point at 0x0 */
--	smu7_program_jump_on_start(smumgr);
-+	smu7_program_jump_on_start(hwmgr);
- 
- 	/* enable smc clock */
--	iceland_start_smc_clock(smumgr);
-+	iceland_start_smc_clock(hwmgr);
- 
- 	/* de-assert reset */
--	iceland_start_smc(smumgr);
-+	iceland_start_smc(hwmgr);
- 
--	SMUM_WAIT_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS,
-+	PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
- 				 INTERRUPTS_ENABLED, 1);
- 
- 	return 0;
- }
- 
- 
--static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr,
-+static int iceland_upload_smc_firmware_data(struct pp_hwmgr *hwmgr,
- 					uint32_t length, const uint8_t *src,
- 					uint32_t limit, uint32_t start_addr)
- {
-@@ -96,34 +165,34 @@ static int iceland_upload_smc_firmware_d
- 
- 	PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
- 
--	cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, start_addr);
--	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
-+	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
-+	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
- 
- 	while (byte_count >= 4) {
- 		data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
--		cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
-+		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
- 		src += 4;
- 		byte_count -= 4;
- 	}
- 
--	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
-+	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
- 
--	PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL);
-+	PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL);
- 
- 	return 0;
- }
- 
- 
--static int iceland_smu_upload_firmware_image(struct pp_smumgr *smumgr)
-+static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr)
- {
- 	uint32_t val;
- 	struct cgs_firmware_info info = {0};
- 
--	if (smumgr == NULL || smumgr->device == NULL)
-+	if (hwmgr == NULL || hwmgr->device == NULL)
- 		return -EINVAL;
- 
- 	/* load SMC firmware */
--	cgs_get_firmware_info(smumgr->device,
-+	cgs_get_firmware_info(hwmgr->device,
- 		smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
- 
- 	if (info.image_size & 3) {
-@@ -137,68 +206,61 @@ static int iceland_smu_upload_firmware_i
- 	}
- 
- 	/* wait for smc boot up */
--	SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
-+	PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
- 					 RCU_UC_EVENTS, boot_seq_done, 0);
- 
- 	/* clear firmware interrupt enable flag */
--	val = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+	val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- 				    ixSMC_SYSCON_MISC_CNTL);
--	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- 			       ixSMC_SYSCON_MISC_CNTL, val | 1);
- 
- 	/* stop smc clock */
--	iceland_stop_smc_clock(smumgr);
-+	iceland_stop_smc_clock(hwmgr);
- 
- 	/* reset smc */
--	iceland_reset_smc(smumgr);
--	iceland_upload_smc_firmware_data(smumgr, info.image_size,
-+	iceland_reset_smc(hwmgr);
-+	iceland_upload_smc_firmware_data(hwmgr, info.image_size,
- 				(uint8_t *)info.kptr, ICELAND_SMC_SIZE,
- 				info.ucode_start_address);
- 
- 	return 0;
- }
- 
--static int iceland_request_smu_load_specific_fw(struct pp_smumgr *smumgr,
-+static int iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
- 						uint32_t firmwareType)
- {
- 	return 0;
- }
- 
--static int iceland_start_smu(struct pp_smumgr *smumgr)
-+static int iceland_start_smu(struct pp_hwmgr *hwmgr)
- {
- 	int result;
- 
--	result = iceland_smu_upload_firmware_image(smumgr);
-+	result = iceland_smu_upload_firmware_image(hwmgr);
- 	if (result)
- 		return result;
--	result = iceland_smu_start_smc(smumgr);
-+	result = iceland_smu_start_smc(hwmgr);
- 	if (result)
- 		return result;
- 
--	if (!smu7_is_smc_ram_running(smumgr)) {
-+	if (!smu7_is_smc_ram_running(hwmgr)) {
- 		pr_info("smu not running, upload firmware again \n");
--		result = iceland_smu_upload_firmware_image(smumgr);
-+		result = iceland_smu_upload_firmware_image(hwmgr);
- 		if (result)
- 			return result;
- 
--		result = iceland_smu_start_smc(smumgr);
-+		result = iceland_smu_start_smc(hwmgr);
- 		if (result)
- 			return result;
- 	}
- 
--	result = smu7_request_smu_load_fw(smumgr);
-+	result = smu7_request_smu_load_fw(hwmgr);
- 
- 	return result;
- }
- 
--/**
-- * Write a 32bit value to the SMC SRAM space.
-- * ALL PARAMETERS ARE IN HOST BYTE ORDER.
-- * @param    smumgr  the address of the powerplay hardware manager.
-- * @param    smcAddress the address in the SMC RAM to access.
-- * @param    value to write to the SMC SRAM.
-- */
--static int iceland_smu_init(struct pp_smumgr *smumgr)
-+static int iceland_smu_init(struct pp_hwmgr *hwmgr)
- {
- 	int i;
- 	struct iceland_smumgr *iceland_priv = NULL;
-@@ -208,9 +270,9 @@ static int iceland_smu_init(struct pp_sm
- 	if (iceland_priv == NULL)
- 		return -ENOMEM;
- 
--	smumgr->backend = iceland_priv;
-+	hwmgr->smu_backend = iceland_priv;
- 
--	if (smu7_init(smumgr))
-+	if (smu7_init(hwmgr))
- 		return -EINVAL;
- 
- 	for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++)
-@@ -219,6 +281,2410 @@ static int iceland_smu_init(struct pp_sm
- 	return 0;
- }
- 
-+
-+static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
-+{
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	struct cgs_system_info sys_info = {0};
-+	uint32_t dev_id;
-+
-+	sys_info.size = sizeof(struct cgs_system_info);
-+	sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
-+	cgs_query_system_info(hwmgr->device, &sys_info);
-+	dev_id = (uint32_t)sys_info.value;
-+
-+	switch (dev_id) {
-+	case DEVICE_ID_VI_ICELAND_M_6900:
-+	case DEVICE_ID_VI_ICELAND_M_6903:
-+		smu_data->power_tune_defaults = &defaults_icelandxt;
-+		break;
-+
-+	case DEVICE_ID_VI_ICELAND_M_6901:
-+	case DEVICE_ID_VI_ICELAND_M_6902:
-+		smu_data->power_tune_defaults = &defaults_icelandpro;
-+		break;
-+	default:
-+		smu_data->power_tune_defaults = &defaults_iceland;
-+		pr_warn("Unknown V.I. Device ID.\n");
-+		break;
-+	}
-+	return;
-+}
-+
-+static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr)
-+{
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
-+
-+	smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
-+	smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddc;
-+	smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
-+	smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr)
-+{
-+	uint16_t tdc_limit;
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
-+
-+	tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
-+	smu_data->power_tune_table.TDC_VDDC_PkgLimit =
-+			CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
-+	smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
-+			defaults->tdc_vddc_throttle_release_limit_perc;
-+	smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
-+{
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
-+	uint32_t temp;
-+
-+	if (smu7_read_smc_sram_dword(hwmgr,
-+			fuse_table_offset +
-+			offsetof(SMU71_Discrete_PmFuses, TdcWaterfallCtl),
-+			(uint32_t *)&temp, SMC_RAM_END))
-+		PP_ASSERT_WITH_CODE(false,
-+				"Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
-+				return -EINVAL);
-+	else
-+		smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
-+{
-+	return 0;
-+}
-+
-+static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+
-+	/* Currently not used. Set all to zero. */
-+	for (i = 0; i < 8; i++)
-+		smu_data->power_tune_table.GnbLPML[i] = 0;
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
-+{
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
-+	uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
-+	struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
-+
-+	HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
-+	LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
-+
-+	smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
-+	smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
-+	uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
-+
-+	PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
-+			    "The CAC Leakage table does not exist!", return -EINVAL);
-+	PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
-+			    "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL);
-+	PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
-+			    "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) {
-+		for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
-+			lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
-+			hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2);
-+		}
-+	} else {
-+		PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL);
-+	}
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	uint8_t *vid = smu_data->power_tune_table.VddCVid;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
-+		"There should never be more than 8 entries for VddcVid!!!",
-+		return -EINVAL);
-+
-+	for (i = 0; i < (int)data->vddc_voltage_table.count; i++) {
-+		vid[i] = convert_to_vid(data->vddc_voltage_table.entries[i].value);
-+	}
-+
-+	return 0;
-+}
-+
-+
-+
-+static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
-+{
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	uint32_t pm_fuse_table_offset;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment)) {
-+		if (smu7_read_smc_sram_dword(hwmgr,
-+				SMU71_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU71_Firmware_Header, PmFuseTable),
-+				&pm_fuse_table_offset, SMC_RAM_END))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to get pm_fuse_table_offset Failed!",
-+					return -EINVAL);
-+
-+		/* DW0 - DW3 */
-+		if (iceland_populate_bapm_vddc_vid_sidd(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate bapm vddc vid Failed!",
-+					return -EINVAL);
-+
-+		/* DW4 - DW5 */
-+		if (iceland_populate_vddc_vid(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate vddc vid Failed!",
-+					return -EINVAL);
-+
-+		/* DW6 */
-+		if (iceland_populate_svi_load_line(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate SviLoadLine Failed!",
-+					return -EINVAL);
-+		/* DW7 */
-+		if (iceland_populate_tdc_limit(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate TDCLimit Failed!", return -EINVAL);
-+		/* DW8 */
-+		if (iceland_populate_dw8(hwmgr, pm_fuse_table_offset))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate TdcWaterfallCtl, "
-+					"LPMLTemperature Min and Max Failed!",
-+					return -EINVAL);
-+
-+		/* DW9-DW12 */
-+		if (0 != iceland_populate_temperature_scaler(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate LPMLTemperatureScaler Failed!",
-+					return -EINVAL);
-+
-+		/* DW13-DW16 */
-+		if (iceland_populate_gnb_lpml(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate GnbLPML Failed!",
-+					return -EINVAL);
-+
-+		/* DW18 */
-+		if (iceland_populate_bapm_vddc_base_leakage_sidd(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!",
-+					return -EINVAL);
-+
-+		if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
-+				(uint8_t *)&smu_data->power_tune_table,
-+				sizeof(struct SMU71_Discrete_PmFuses), SMC_RAM_END))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to download PmFuseTable Failed!",
-+					return -EINVAL);
-+	}
-+	return 0;
-+}
-+
-+static int iceland_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
-+	struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,
-+	uint32_t clock, uint32_t *vol)
-+{
-+	uint32_t i = 0;
-+
-+	/* clock - voltage dependency table is empty table */
-+	if (allowed_clock_voltage_table->count == 0)
-+		return -EINVAL;
-+
-+	for (i = 0; i < allowed_clock_voltage_table->count; i++) {
-+		/* find first sclk bigger than request */
-+		if (allowed_clock_voltage_table->entries[i].clk >= clock) {
-+			*vol = allowed_clock_voltage_table->entries[i].v;
-+			return 0;
-+		}
-+	}
-+
-+	/* sclk is bigger than max sclk in the dependence table */
-+	*vol = allowed_clock_voltage_table->entries[i - 1].v;
-+
-+	return 0;
-+}
-+
-+static int iceland_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
-+		pp_atomctrl_voltage_table_entry *tab, uint16_t *hi,
-+		uint16_t *lo)
-+{
-+	uint16_t v_index;
-+	bool vol_found = false;
-+	*hi = tab->value * VOLTAGE_SCALE;
-+	*lo = tab->value * VOLTAGE_SCALE;
-+
-+	/* SCLK/VDDC Dependency Table has to exist. */
-+	PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
-+			"The SCLK/VDDC Dependency Table does not exist.\n",
-+			return -EINVAL);
-+
-+	if (NULL == hwmgr->dyn_state.cac_leakage_table) {
-+		pr_warn("CAC Leakage Table does not exist, using vddc.\n");
-+		return 0;
-+	}
-+
-+	/*
-+	 * Since voltage in the sclk/vddc dependency table is not
-+	 * necessarily in ascending order because of ELB voltage
-+	 * patching, loop through entire list to find exact voltage.
-+	 */
-+	for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
-+		if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
-+			vol_found = true;
-+			if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
-+				*lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
-+				*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE);
-+			} else {
-+				pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
-+				*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
-+				*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
-+			}
-+			break;
-+		}
-+	}
-+
-+	/*
-+	 * If voltage is not found in the first pass, loop again to
-+	 * find the best match, equal or higher value.
-+	 */
-+	if (!vol_found) {
-+		for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
-+			if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
-+				vol_found = true;
-+				if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
-+					*lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
-+					*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE;
-+				} else {
-+					pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.");
-+					*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
-+					*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
-+				}
-+				break;
-+			}
-+		}
-+
-+		if (!vol_found)
-+			pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n");
-+	}
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_smc_voltage_table(struct pp_hwmgr *hwmgr,
-+		pp_atomctrl_voltage_table_entry *tab,
-+		SMU71_Discrete_VoltageLevel *smc_voltage_tab)
-+{
-+	int result;
-+
-+	result = iceland_get_std_voltage_value_sidd(hwmgr, tab,
-+			&smc_voltage_tab->StdVoltageHiSidd,
-+			&smc_voltage_tab->StdVoltageLoSidd);
-+	if (0 != result) {
-+		smc_voltage_tab->StdVoltageHiSidd = tab->value * VOLTAGE_SCALE;
-+		smc_voltage_tab->StdVoltageLoSidd = tab->value * VOLTAGE_SCALE;
-+	}
-+
-+	smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE);
-+	CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
-+	CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
-+			SMU71_Discrete_DpmTable *table)
-+{
-+	unsigned int count;
-+	int result;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	table->VddcLevelCount = data->vddc_voltage_table.count;
-+	for (count = 0; count < table->VddcLevelCount; count++) {
-+		result = iceland_populate_smc_voltage_table(hwmgr,
-+				&(data->vddc_voltage_table.entries[count]),
-+				&(table->VddcLevel[count]));
-+		PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
-+
-+		/* GPIO voltage control */
-+		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control)
-+			table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low;
-+		else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
-+			table->VddcLevel[count].Smio = 0;
-+	}
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
-+			SMU71_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t count;
-+	int result;
-+
-+	table->VddciLevelCount = data->vddci_voltage_table.count;
-+
-+	for (count = 0; count < table->VddciLevelCount; count++) {
-+		result = iceland_populate_smc_voltage_table(hwmgr,
-+				&(data->vddci_voltage_table.entries[count]),
-+				&(table->VddciLevel[count]));
-+		PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
-+		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
-+			table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low;
-+		else
-+			table->VddciLevel[count].Smio |= 0;
-+	}
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
-+			SMU71_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t count;
-+	int result;
-+
-+	table->MvddLevelCount = data->mvdd_voltage_table.count;
-+
-+	for (count = 0; count < table->VddciLevelCount; count++) {
-+		result = iceland_populate_smc_voltage_table(hwmgr,
-+				&(data->mvdd_voltage_table.entries[count]),
-+				&table->MvddLevel[count]);
-+		PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);
-+		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control)
-+			table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low;
-+		else
-+			table->MvddLevel[count].Smio |= 0;
-+	}
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
-+
-+	return 0;
-+}
-+
-+
-+static int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
-+	SMU71_Discrete_DpmTable *table)
-+{
-+	int result;
-+
-+	result = iceland_populate_smc_vddc_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"can not populate VDDC voltage table to SMC", return -EINVAL);
-+
-+	result = iceland_populate_smc_vdd_ci_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"can not populate VDDCI voltage table to SMC", return -EINVAL);
-+
-+	result = iceland_populate_smc_mvdd_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"can not populate MVDD voltage table to SMC", return -EINVAL);
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_ulv_level(struct pp_hwmgr *hwmgr,
-+		struct SMU71_Discrete_Ulv *state)
-+{
-+	uint32_t voltage_response_time, ulv_voltage;
-+	int result;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	state->CcPwrDynRm = 0;
-+	state->CcPwrDynRm1 = 0;
-+
-+	result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage);
-+	PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);
-+
-+	if (ulv_voltage == 0) {
-+		data->ulv_supported = false;
-+		return 0;
-+	}
-+
-+	if (data->voltage_control != SMU7_VOLTAGE_CONTROL_BY_SVID2) {
-+		/* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
-+		if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
-+			state->VddcOffset = 0;
-+		else
-+			/* used in SMIO Mode. not implemented for now. this is backup only for CI. */
-+			state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
-+	} else {
-+		/* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
-+		if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
-+			state->VddcOffsetVid = 0;
-+		else  /* used in SVI2 Mode */
-+			state->VddcOffsetVid = (uint8_t)(
-+					(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage)
-+						* VOLTAGE_VID_OFFSET_SCALE2
-+						/ VOLTAGE_VID_OFFSET_SCALE1);
-+	}
-+	state->VddcPhase = 1;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
-+	CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_ulv_state(struct pp_hwmgr *hwmgr,
-+		 SMU71_Discrete_Ulv *ulv_level)
-+{
-+	return iceland_populate_ulv_level(hwmgr, ulv_level);
-+}
-+
-+static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct smu7_dpm_table *dpm_table = &data->dpm_table;
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	uint32_t i;
-+
-+	/* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
-+	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
-+		table->LinkLevel[i].PcieGenSpeed  =
-+			(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
-+		table->LinkLevel[i].PcieLaneCount =
-+			(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
-+		table->LinkLevel[i].EnabledForActivity =
-+			1;
-+		table->LinkLevel[i].SPC =
-+			(uint8_t)(data->pcie_spc_cap & 0xff);
-+		table->LinkLevel[i].DownThreshold =
-+			PP_HOST_TO_SMC_UL(5);
-+		table->LinkLevel[i].UpThreshold =
-+			PP_HOST_TO_SMC_UL(30);
-+	}
-+
-+	smu_data->smc_state_table.LinkLevelCount =
-+		(uint8_t)dpm_table->pcie_speed_table.count;
-+	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
-+		phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
-+
-+	return 0;
-+}
-+
-+static int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr,
-+		uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk)
-+{
-+	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	pp_atomctrl_clock_dividers_vi dividers;
-+	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
-+	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
-+	uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
-+	uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
-+	uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
-+	uint32_t    reference_clock;
-+	uint32_t reference_divider;
-+	uint32_t fbdiv;
-+	int result;
-+
-+	/* get the engine clock dividers for this clock value*/
-+	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock,  &dividers);
-+
-+	PP_ASSERT_WITH_CODE(result == 0,
-+		"Error retrieving Engine Clock dividers from VBIOS.", return result);
-+
-+	/* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
-+	reference_clock = atomctrl_get_reference_clock(hwmgr);
-+
-+	reference_divider = 1 + dividers.uc_pll_ref_div;
-+
-+	/* low 14 bits is fraction and high 12 bits is divider*/
-+	fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
-+
-+	/* SPLL_FUNC_CNTL setup*/
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
-+		CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
-+		CG_SPLL_FUNC_CNTL, SPLL_PDIV_A,  dividers.uc_pll_post_div);
-+
-+	/* SPLL_FUNC_CNTL_3 setup*/
-+	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
-+		CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
-+
-+	/* set to use fractional accumulation*/
-+	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
-+		CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
-+		pp_atomctrl_internal_ss_info ss_info;
-+
-+		uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
-+		if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
-+			/*
-+			* ss_info.speed_spectrum_percentage -- in unit of 0.01%
-+			* ss_info.speed_spectrum_rate -- in unit of khz
-+			*/
-+			/* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
-+			uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
-+
-+			/* clkv = 2 * D * fbdiv / NS */
-+			uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
-+
-+			cg_spll_spread_spectrum =
-+				PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
-+			cg_spll_spread_spectrum =
-+				PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
-+			cg_spll_spread_spectrum_2 =
-+				PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
-+		}
-+	}
-+
-+	sclk->SclkFrequency        = engine_clock;
-+	sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
-+	sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
-+	sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
-+	sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
-+	sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
-+				const struct phm_phase_shedding_limits_table *pl,
-+					uint32_t sclk, uint32_t *p_shed)
-+{
-+	unsigned int i;
-+
-+	/* use the minimum phase shedding */
-+	*p_shed = 1;
-+
-+	for (i = 0; i < pl->count; i++) {
-+		if (sclk < pl->entries[i].Sclk) {
-+			*p_shed = i;
-+			break;
-+		}
-+	}
-+	return 0;
-+}
-+
-+static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
-+						uint32_t engine_clock,
-+				uint16_t sclk_activity_level_threshold,
-+				SMU71_Discrete_GraphicsLevel *graphic_level)
-+{
-+	int result;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
-+
-+	/* populate graphics levels*/
-+	result = iceland_get_dependency_volt_by_clk(hwmgr,
-+		hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,
-+		&graphic_level->MinVddc);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+		"can not find VDDC voltage value for VDDC engine clock dependency table", return result);
-+
-+	/* SCLK frequency in units of 10KHz*/
-+	graphic_level->SclkFrequency = engine_clock;
-+	graphic_level->MinVddcPhases = 1;
-+
-+	if (data->vddc_phase_shed_control)
-+		iceland_populate_phase_value_based_on_sclk(hwmgr,
-+				hwmgr->dyn_state.vddc_phase_shed_limits_table,
-+				engine_clock,
-+				&graphic_level->MinVddcPhases);
-+
-+	/* Indicates maximum activity level for this performance level. 50% for now*/
-+	graphic_level->ActivityLevel = sclk_activity_level_threshold;
-+
-+	graphic_level->CcPwrDynRm = 0;
-+	graphic_level->CcPwrDynRm1 = 0;
-+	/* this level can be used if activity is high enough.*/
-+	graphic_level->EnabledForActivity = 0;
-+	/* this level can be used for throttling.*/
-+	graphic_level->EnabledForThrottle = 1;
-+	graphic_level->UpHyst = 0;
-+	graphic_level->DownHyst = 100;
-+	graphic_level->VoltageDownHyst = 0;
-+	graphic_level->PowerThrottle = 0;
-+
-+	data->display_timing.min_clock_in_sr =
-+			hwmgr->display_config.min_core_set_clock_in_sr;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkDeepSleep))
-+		graphic_level->DeepSleepDivId =
-+				smu7_get_sleep_divider_id_from_clock(engine_clock,
-+						data->display_timing.min_clock_in_sr);
-+
-+	/* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
-+	graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	if (0 == result) {
-+		graphic_level->MinVddc = PP_HOST_TO_SMC_UL(graphic_level->MinVddc * VOLTAGE_SCALE);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
-+	}
-+
-+	return result;
-+}
-+
-+static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_dpm_table *dpm_table = &data->dpm_table;
-+	uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start +
-+				offsetof(SMU71_Discrete_DpmTable, GraphicsLevel);
-+
-+	uint32_t level_array_size = sizeof(SMU71_Discrete_GraphicsLevel) *
-+						SMU71_MAX_LEVELS_GRAPHICS;
-+
-+	SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
-+
-+	uint32_t i;
-+	uint8_t highest_pcie_level_enabled = 0;
-+	uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0;
-+	uint8_t count = 0;
-+	int result = 0;
-+
-+	memset(levels, 0x00, level_array_size);
-+
-+	for (i = 0; i < dpm_table->sclk_table.count; i++) {
-+		result = iceland_populate_single_graphic_level(hwmgr,
-+					dpm_table->sclk_table.dpm_levels[i].value,
-+					(uint16_t)smu_data->activity_target[i],
-+					&(smu_data->smc_state_table.GraphicsLevel[i]));
-+		if (result != 0)
-+			return result;
-+
-+		/* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
-+		if (i > 1)
-+			smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
-+	}
-+
-+	/* Only enable level 0 for now. */
-+	smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
-+
-+	/* set highest level watermark to high */
-+	if (dpm_table->sclk_table.count > 1)
-+		smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
-+			PPSMC_DISPLAY_WATERMARK_HIGH;
-+
-+	smu_data->smc_state_table.GraphicsDpmLevelCount =
-+		(uint8_t)dpm_table->sclk_table.count;
-+	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
-+		phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
-+
-+	while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+				(1 << (highest_pcie_level_enabled + 1))) != 0) {
-+		highest_pcie_level_enabled++;
-+	}
-+
-+	while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+		(1 << lowest_pcie_level_enabled)) == 0) {
-+		lowest_pcie_level_enabled++;
-+	}
-+
-+	while ((count < highest_pcie_level_enabled) &&
-+			((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+				(1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) {
-+		count++;
-+	}
-+
-+	mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
-+		(lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
-+
-+
-+	/* set pcieDpmLevel to highest_pcie_level_enabled*/
-+	for (i = 2; i < dpm_table->sclk_table.count; i++) {
-+		smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
-+	}
-+
-+	/* set pcieDpmLevel to lowest_pcie_level_enabled*/
-+	smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
-+
-+	/* set pcieDpmLevel to mid_pcie_level_enabled*/
-+	smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
-+
-+	/* level count will send to smc once at init smc table and never change*/
-+	result = smu7_copy_bytes_to_smc(hwmgr, level_array_adress,
-+				(uint8_t *)levels, (uint32_t)level_array_size,
-+								SMC_RAM_END);
-+
-+	return result;
-+}
-+
-+static int iceland_calculate_mclk_params(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t memory_clock,
-+		SMU71_Discrete_MemoryLevel *mclk,
-+		bool strobe_mode,
-+		bool dllStateOn
-+		)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	uint32_t  dll_cntl = data->clock_registers.vDLL_CNTL;
-+	uint32_t  mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
-+	uint32_t  mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
-+	uint32_t  mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
-+	uint32_t  mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
-+	uint32_t  mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
-+	uint32_t  mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
-+	uint32_t  mpll_ss1 = data->clock_registers.vMPLL_SS1;
-+	uint32_t  mpll_ss2 = data->clock_registers.vMPLL_SS2;
-+
-+	pp_atomctrl_memory_clock_param mpll_param;
-+	int result;
-+
-+	result = atomctrl_get_memory_pll_dividers_si(hwmgr,
-+				memory_clock, &mpll_param, strobe_mode);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Error retrieving Memory Clock Parameters from VBIOS.", return result);
-+
-+	/* MPLL_FUNC_CNTL setup*/
-+	mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
-+
-+	/* MPLL_FUNC_CNTL_1 setup*/
-+	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
-+							MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
-+	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
-+							MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
-+	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
-+							MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
-+
-+	/* MPLL_AD_FUNC_CNTL setup*/
-+	mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
-+							MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
-+
-+	if (data->is_memory_gddr5) {
-+		/* MPLL_DQ_FUNC_CNTL setup*/
-+		mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
-+								MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
-+		mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
-+								MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
-+		/*
-+		 ************************************
-+		 Fref = Reference Frequency
-+		 NF = Feedback divider ratio
-+		 NR = Reference divider ratio
-+		 Fnom = Nominal VCO output frequency = Fref * NF / NR
-+		 Fs = Spreading Rate
-+		 D = Percentage down-spread / 2
-+		 Fint = Reference input frequency to PFD = Fref / NR
-+		 NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
-+		 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
-+		 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
-+		 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
-+		 *************************************
-+		 */
-+		pp_atomctrl_internal_ss_info ss_info;
-+		uint32_t freq_nom;
-+		uint32_t tmp;
-+		uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
-+
-+		/* for GDDR5 for all modes and DDR3 */
-+		if (1 == mpll_param.qdr)
-+			freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
-+		else
-+			freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
-+
-+		/* tmp = (freq_nom / reference_clock * reference_divider) ^ 2  Note: S.I. reference_divider = 1*/
-+		tmp = (freq_nom / reference_clock);
-+		tmp = tmp * tmp;
-+
-+		if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
-+			/* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
-+			/* ss.Info.speed_spectrum_rate -- in unit of khz */
-+			/* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
-+			/*     = reference_clock * 5 / speed_spectrum_rate */
-+			uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
-+
-+			/* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
-+			/*     = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
-+			uint32_t clkv =
-+				(uint32_t)((((131 * ss_info.speed_spectrum_percentage *
-+							ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
-+
-+			mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
-+			mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
-+		}
-+	}
-+
-+	/* MCLK_PWRMGT_CNTL setup */
-+	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
-+	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
-+	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
-+
-+
-+	/* Save the result data to outpupt memory level structure */
-+	mclk->MclkFrequency   = memory_clock;
-+	mclk->MpllFuncCntl    = mpll_func_cntl;
-+	mclk->MpllFuncCntl_1  = mpll_func_cntl_1;
-+	mclk->MpllFuncCntl_2  = mpll_func_cntl_2;
-+	mclk->MpllAdFuncCntl  = mpll_ad_func_cntl;
-+	mclk->MpllDqFuncCntl  = mpll_dq_func_cntl;
-+	mclk->MclkPwrmgtCntl  = mclk_pwrmgt_cntl;
-+	mclk->DllCntl         = dll_cntl;
-+	mclk->MpllSs1         = mpll_ss1;
-+	mclk->MpllSs2         = mpll_ss2;
-+
-+	return 0;
-+}
-+
-+static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock,
-+		bool strobe_mode)
-+{
-+	uint8_t mc_para_index;
-+
-+	if (strobe_mode) {
-+		if (memory_clock < 12500) {
-+			mc_para_index = 0x00;
-+		} else if (memory_clock > 47500) {
-+			mc_para_index = 0x0f;
-+		} else {
-+			mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
-+		}
-+	} else {
-+		if (memory_clock < 65000) {
-+			mc_para_index = 0x00;
-+		} else if (memory_clock > 135000) {
-+			mc_para_index = 0x0f;
-+		} else {
-+			mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
-+		}
-+	}
-+
-+	return mc_para_index;
-+}
-+
-+static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
-+{
-+	uint8_t mc_para_index;
-+
-+	if (memory_clock < 10000) {
-+		mc_para_index = 0;
-+	} else if (memory_clock >= 80000) {
-+		mc_para_index = 0x0f;
-+	} else {
-+		mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
-+	}
-+
-+	return mc_para_index;
-+}
-+
-+static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
-+					uint32_t memory_clock, uint32_t *p_shed)
-+{
-+	unsigned int i;
-+
-+	*p_shed = 1;
-+
-+	for (i = 0; i < pl->count; i++) {
-+		if (memory_clock < pl->entries[i].Mclk) {
-+			*p_shed = i;
-+			break;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_single_memory_level(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t memory_clock,
-+		SMU71_Discrete_MemoryLevel *memory_level
-+		)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	int result = 0;
-+	bool dll_state_on;
-+	struct cgs_display_info info = {0};
-+	uint32_t mclk_edc_wr_enable_threshold = 40000;
-+	uint32_t mclk_edc_enable_threshold = 40000;
-+	uint32_t mclk_strobe_mode_threshold = 40000;
-+
-+	if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
-+		result = iceland_get_dependency_volt_by_clk(hwmgr,
-+			hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+			"can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
-+	}
-+
-+	if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) {
-+		memory_level->MinVddci = memory_level->MinVddc;
-+	} else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
-+		result = iceland_get_dependency_volt_by_clk(hwmgr,
-+				hwmgr->dyn_state.vddci_dependency_on_mclk,
-+				memory_clock,
-+				&memory_level->MinVddci);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+			"can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result);
-+	}
-+
-+	memory_level->MinVddcPhases = 1;
-+
-+	if (data->vddc_phase_shed_control) {
-+		iceland_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,
-+				memory_clock, &memory_level->MinVddcPhases);
-+	}
-+
-+	memory_level->EnabledForThrottle = 1;
-+	memory_level->EnabledForActivity = 0;
-+	memory_level->UpHyst = 0;
-+	memory_level->DownHyst = 100;
-+	memory_level->VoltageDownHyst = 0;
-+
-+	/* Indicates maximum activity level for this performance level.*/
-+	memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
-+	memory_level->StutterEnable = 0;
-+	memory_level->StrobeEnable = 0;
-+	memory_level->EdcReadEnable = 0;
-+	memory_level->EdcWriteEnable = 0;
-+	memory_level->RttEnable = 0;
-+
-+	/* default set to low watermark. Highest level will be set to high later.*/
-+	memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+	data->display_timing.num_existing_displays = info.display_count;
-+
-+	/* stutter mode not support on iceland */
-+
-+	/* decide strobe mode*/
-+	memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
-+		(memory_clock <= mclk_strobe_mode_threshold);
-+
-+	/* decide EDC mode and memory clock ratio*/
-+	if (data->is_memory_gddr5) {
-+		memory_level->StrobeRatio = iceland_get_mclk_frequency_ratio(memory_clock,
-+					memory_level->StrobeEnable);
-+
-+		if ((mclk_edc_enable_threshold != 0) &&
-+				(memory_clock > mclk_edc_enable_threshold)) {
-+			memory_level->EdcReadEnable = 1;
-+		}
-+
-+		if ((mclk_edc_wr_enable_threshold != 0) &&
-+				(memory_clock > mclk_edc_wr_enable_threshold)) {
-+			memory_level->EdcWriteEnable = 1;
-+		}
-+
-+		if (memory_level->StrobeEnable) {
-+			if (iceland_get_mclk_frequency_ratio(memory_clock, 1) >=
-+					((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf))
-+				dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
-+			else
-+				dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
-+		} else
-+			dll_state_on = data->dll_default_on;
-+	} else {
-+		memory_level->StrobeRatio =
-+			iceland_get_ddr3_mclk_frequency_ratio(memory_clock);
-+		dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
-+	}
-+
-+	result = iceland_calculate_mclk_params(hwmgr,
-+		memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
-+
-+	if (0 == result) {
-+		memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases);
-+		memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);
-+		memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);
-+		/* MCLK frequency in units of 10KHz*/
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
-+		/* Indicates maximum activity level for this performance level.*/
-+		CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
-+	}
-+
-+	return result;
-+}
-+
-+static int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_dpm_table *dpm_table = &data->dpm_table;
-+	int result;
-+
-+	/* populate MCLK dpm table to SMU7 */
-+	uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel);
-+	uint32_t level_array_size = sizeof(SMU71_Discrete_MemoryLevel) * SMU71_MAX_LEVELS_MEMORY;
-+	SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
-+	uint32_t i;
-+
-+	memset(levels, 0x00, level_array_size);
-+
-+	for (i = 0; i < dpm_table->mclk_table.count; i++) {
-+		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
-+			"can not populate memory level as memory clock is zero", return -EINVAL);
-+		result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
-+			&(smu_data->smc_state_table.MemoryLevel[i]));
-+		if (0 != result) {
-+			return result;
-+		}
-+	}
-+
-+	/* Only enable level 0 for now.*/
-+	smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
-+
-+	/*
-+	* in order to prevent MC activity from stutter mode to push DPM up.
-+	* the UVD change complements this by putting the MCLK in a higher state
-+	* by default such that we are not effected by up threshold or and MCLK DPM latency.
-+	*/
-+	smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
-+	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
-+
-+	smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
-+	data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
-+	/* set highest level watermark to high*/
-+	smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
-+
-+	/* level count will send to smc once at init smc table and never change*/
-+	result = smu7_copy_bytes_to_smc(hwmgr,
-+		level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size,
-+		SMC_RAM_END);
-+
-+	return result;
-+}
-+
-+static int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
-+					SMU71_Discrete_VoltageLevel *voltage)
-+{
-+	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	uint32_t i = 0;
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
-+		/* find mvdd value which clock is more than request */
-+		for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
-+			if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
-+				/* Always round to higher voltage. */
-+				voltage->Voltage = data->mvdd_voltage_table.entries[i].value;
-+				break;
-+			}
-+		}
-+
-+		PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
-+			"MVDD Voltage is outside the supported range.", return -EINVAL);
-+
-+	} else {
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
-+	SMU71_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	uint32_t vddc_phase_shed_control = 0;
-+
-+	SMU71_Discrete_VoltageLevel voltage_level;
-+	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
-+	uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
-+	uint32_t dll_cntl          = data->clock_registers.vDLL_CNTL;
-+	uint32_t mclk_pwrmgt_cntl  = data->clock_registers.vMCLK_PWRMGT_CNTL;
-+
-+
-+	/* The ACPI state should not do DPM on DC (or ever).*/
-+	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
-+
-+	if (data->acpi_vddc)
-+		table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
-+	else
-+		table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
-+
-+	table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1;
-+	/* assign zero for now*/
-+	table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
-+
-+	/* get the engine clock dividers for this clock value*/
-+	result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
-+		table->ACPILevel.SclkFrequency,  &dividers);
-+
-+	PP_ASSERT_WITH_CODE(result == 0,
-+		"Error retrieving Engine Clock dividers from VBIOS.", return result);
-+
-+	/* divider ID for required SCLK*/
-+	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
-+	table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+	table->ACPILevel.DeepSleepDivId = 0;
-+
-+	spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
-+							CG_SPLL_FUNC_CNTL,   SPLL_PWRON,     0);
-+	spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
-+							CG_SPLL_FUNC_CNTL,   SPLL_RESET,     1);
-+	spll_func_cntl_2    = PHM_SET_FIELD(spll_func_cntl_2,
-+							CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL,   4);
-+
-+	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
-+	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
-+	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
-+	table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
-+	table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
-+	table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
-+	table->ACPILevel.CcPwrDynRm = 0;
-+	table->ACPILevel.CcPwrDynRm1 = 0;
-+
-+
-+	/* For various features to be enabled/disabled while this level is active.*/
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
-+	/* SCLK frequency in units of 10KHz*/
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
-+
-+	/* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
-+	table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
-+	table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
-+		table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc;
-+	else {
-+		if (data->acpi_vddci != 0)
-+			table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);
-+		else
-+			table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);
-+	}
-+
-+	if (0 == iceland_populate_mvdd_value(hwmgr, 0, &voltage_level))
-+		table->MemoryACPILevel.MinMvdd =
-+			PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
-+	else
-+		table->MemoryACPILevel.MinMvdd = 0;
-+
-+	/* Force reset on DLL*/
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
-+
-+	/* Disable DLL in ACPIState*/
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
-+
-+	/* Enable DLL bypass signal*/
-+	dll_cntl            = PHM_SET_FIELD(dll_cntl,
-+		DLL_CNTL, MRDCK0_BYPASS, 0);
-+	dll_cntl            = PHM_SET_FIELD(dll_cntl,
-+		DLL_CNTL, MRDCK1_BYPASS, 0);
-+
-+	table->MemoryACPILevel.DllCntl            =
-+		PP_HOST_TO_SMC_UL(dll_cntl);
-+	table->MemoryACPILevel.MclkPwrmgtCntl     =
-+		PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
-+	table->MemoryACPILevel.MpllAdFuncCntl     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
-+	table->MemoryACPILevel.MpllDqFuncCntl     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
-+	table->MemoryACPILevel.MpllFuncCntl       =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
-+	table->MemoryACPILevel.MpllFuncCntl_1     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
-+	table->MemoryACPILevel.MpllFuncCntl_2     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
-+	table->MemoryACPILevel.MpllSs1            =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
-+	table->MemoryACPILevel.MpllSs2            =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
-+
-+	table->MemoryACPILevel.EnabledForThrottle = 0;
-+	table->MemoryACPILevel.EnabledForActivity = 0;
-+	table->MemoryACPILevel.UpHyst = 0;
-+	table->MemoryACPILevel.DownHyst = 100;
-+	table->MemoryACPILevel.VoltageDownHyst = 0;
-+	/* Indicates maximum activity level for this performance level.*/
-+	table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
-+
-+	table->MemoryACPILevel.StutterEnable = 0;
-+	table->MemoryACPILevel.StrobeEnable = 0;
-+	table->MemoryACPILevel.EdcReadEnable = 0;
-+	table->MemoryACPILevel.EdcWriteEnable = 0;
-+	table->MemoryACPILevel.RttEnable = 0;
-+
-+	return result;
-+}
-+
-+static int iceland_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
-+					SMU71_Discrete_DpmTable *table)
-+{
-+	return 0;
-+}
-+
-+static int iceland_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
-+		SMU71_Discrete_DpmTable *table)
-+{
-+	return 0;
-+}
-+
-+static int iceland_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
-+		SMU71_Discrete_DpmTable *table)
-+{
-+	return 0;
-+}
-+
-+static int iceland_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-+	SMU71_Discrete_DpmTable *table)
-+{
-+	return 0;
-+}
-+
-+static int iceland_populate_memory_timing_parameters(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t engine_clock,
-+		uint32_t memory_clock,
-+		struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs
-+		)
-+{
-+	uint32_t dramTiming;
-+	uint32_t dramTiming2;
-+	uint32_t burstTime;
-+	int result;
-+
-+	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
-+				engine_clock, memory_clock);
-+
-+	PP_ASSERT_WITH_CODE(result == 0,
-+		"Error calling VBIOS to set DRAM_TIMING.", return result);
-+
-+	dramTiming  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
-+	dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
-+	burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
-+
-+	arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dramTiming);
-+	arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
-+	arb_regs->McArbBurstTime = (uint8_t)burstTime;
-+
-+	return 0;
-+}
-+
-+static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	int result = 0;
-+	SMU71_Discrete_MCArbDramTimingTable  arb_regs;
-+	uint32_t i, j;
-+
-+	memset(&arb_regs, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable));
-+
-+	for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
-+		for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
-+			result = iceland_populate_memory_timing_parameters
-+				(hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
-+				 data->dpm_table.mclk_table.dpm_levels[j].value,
-+				 &arb_regs.entries[i][j]);
-+
-+			if (0 != result) {
-+				break;
-+			}
-+		}
-+	}
-+
-+	if (0 == result) {
-+		result = smu7_copy_bytes_to_smc(
-+				hwmgr,
-+				smu_data->smu7_data.arb_table_start,
-+				(uint8_t *)&arb_regs,
-+				sizeof(SMU71_Discrete_MCArbDramTimingTable),
-+				SMC_RAM_END
-+				);
-+	}
-+
-+	return result;
-+}
-+
-+static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
-+			SMU71_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	table->GraphicsBootLevel = 0;
-+	table->MemoryBootLevel = 0;
-+
-+	/* find boot level from dpm table*/
-+	result = phm_find_boot_level(&(data->dpm_table.sclk_table),
-+			data->vbios_boot_state.sclk_bootup_value,
-+			(uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
-+
-+	if (0 != result) {
-+		smu_data->smc_state_table.GraphicsBootLevel = 0;
-+		pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n");
-+		result = 0;
-+	}
-+
-+	result = phm_find_boot_level(&(data->dpm_table.mclk_table),
-+		data->vbios_boot_state.mclk_bootup_value,
-+		(uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
-+
-+	if (0 != result) {
-+		smu_data->smc_state_table.MemoryBootLevel = 0;
-+		pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n");
-+		result = 0;
-+	}
-+
-+	table->BootVddc = data->vbios_boot_state.vddc_bootup_value;
-+	if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
-+		table->BootVddci = table->BootVddc;
-+	else
-+		table->BootVddci = data->vbios_boot_state.vddci_bootup_value;
-+
-+	table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
-+
-+	return result;
-+}
-+
-+static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
-+				 SMU71_Discrete_MCRegisters *mc_reg_table)
-+{
-+	const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smu_backend;
-+
-+	uint32_t i, j;
-+
-+	for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
-+		if (smu_data->mc_reg_table.validflag & 1<<j) {
-+			PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE,
-+				"Index of mc_reg_table->address[] array out of boundary", return -EINVAL);
-+			mc_reg_table->address[i].s0 =
-+				PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
-+			mc_reg_table->address[i].s1 =
-+				PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
-+			i++;
-+		}
-+	}
-+
-+	mc_reg_table->last = (uint8_t)i;
-+
-+	return 0;
-+}
-+
-+/*convert register values from driver to SMC format */
-+static void iceland_convert_mc_registers(
-+	const struct iceland_mc_reg_entry *entry,
-+	SMU71_Discrete_MCRegisterSet *data,
-+	uint32_t num_entries, uint32_t valid_flag)
-+{
-+	uint32_t i, j;
-+
-+	for (i = 0, j = 0; j < num_entries; j++) {
-+		if (valid_flag & 1<<j) {
-+			data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
-+			i++;
-+		}
-+	}
-+}
-+
-+static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr,
-+		const uint32_t memory_clock,
-+		SMU71_Discrete_MCRegisterSet *mc_reg_table_data
-+		)
-+{
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	uint32_t i = 0;
-+
-+	for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
-+		if (memory_clock <=
-+			smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
-+			break;
-+		}
-+	}
-+
-+	if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
-+		--i;
-+
-+	iceland_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
-+				mc_reg_table_data, smu_data->mc_reg_table.last,
-+				smu_data->mc_reg_table.validflag);
-+
-+	return 0;
-+}
-+
-+static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
-+		SMU71_Discrete_MCRegisters *mc_regs)
-+{
-+	int result = 0;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	int res;
-+	uint32_t i;
-+
-+	for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
-+		res = iceland_convert_mc_reg_table_entry_to_smc(
-+				hwmgr,
-+				data->dpm_table.mclk_table.dpm_levels[i].value,
-+				&mc_regs->data[i]
-+				);
-+
-+		if (0 != res)
-+			result = res;
-+	}
-+
-+	return result;
-+}
-+
-+static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t address;
-+	int32_t result;
-+
-+	if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
-+		return 0;
-+
-+
-+	memset(&smu_data->mc_regs, 0, sizeof(SMU71_Discrete_MCRegisters));
-+
-+	result = iceland_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
-+
-+	if (result != 0)
-+		return result;
-+
-+
-+	address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);
-+
-+	return  smu7_copy_bytes_to_smc(hwmgr, address,
-+				 (uint8_t *)&smu_data->mc_regs.data[0],
-+				sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
-+				SMC_RAM_END);
-+}
-+
-+static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+
-+	memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters));
-+	result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize MCRegTable for the MC register addresses!", return result;);
-+
-+	result = iceland_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize MCRegTable for driver state!", return result;);
-+
-+	return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
-+			(uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END);
-+}
-+
-+static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	uint8_t count, level;
-+
-+	count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
-+
-+	for (level = 0; level < count; level++) {
-+		if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk
-+			 >= data->vbios_boot_state.sclk_bootup_value) {
-+			smu_data->smc_state_table.GraphicsBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
-+
-+	for (level = 0; level < count; level++) {
-+		if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
-+			>= data->vbios_boot_state.mclk_bootup_value) {
-+			smu_data->smc_state_table.MemoryBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
-+	SMU71_Discrete_DpmTable  *dpm_table = &(smu_data->smc_state_table);
-+	struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table;
-+	struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table;
-+	const uint16_t *def1, *def2;
-+	int i, j, k;
-+
-+
-+	/*
-+	 * TDP number of fraction bits are changed from 8 to 7 for Iceland
-+	 * as requested by SMC team
-+	 */
-+
-+	dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256));
-+	dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
-+
-+
-+	dpm_table->DTETjOffset = 0;
-+
-+	dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES);
-+	dpm_table->GpuTjHyst = 8;
-+
-+	dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
-+
-+	/* The following are for new Iceland Multi-input fan/thermal control */
-+	if (NULL != ppm) {
-+		dpm_table->PPM_PkgPwrLimit = (uint16_t)ppm->dgpu_tdp * 256 / 1000;
-+		dpm_table->PPM_TemperatureLimit = (uint16_t)ppm->tj_max * 256;
-+	} else {
-+		dpm_table->PPM_PkgPwrLimit = 0;
-+		dpm_table->PPM_TemperatureLimit = 0;
-+	}
-+
-+	CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit);
-+	CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit);
-+
-+	dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
-+	def1 = defaults->bapmti_r;
-+	def2 = defaults->bapmti_rc;
-+
-+	for (i = 0; i < SMU71_DTE_ITERATIONS; i++) {
-+		for (j = 0; j < SMU71_DTE_SOURCES; j++) {
-+			for (k = 0; k < SMU71_DTE_SINKS; k++) {
-+				dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
-+				dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
-+				def1++;
-+				def2++;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int iceland_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
-+					    SMU71_Discrete_DpmTable *tab)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
-+		tab->SVI2Enable |= VDDC_ON_SVI2;
-+
-+	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
-+		tab->SVI2Enable |= VDDCI_ON_SVI2;
-+	else
-+		tab->MergedVddci = 1;
-+
-+	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control)
-+		tab->SVI2Enable |= MVDD_ON_SVI2;
-+
-+	PP_ASSERT_WITH_CODE(tab->SVI2Enable != (VDDC_ON_SVI2 | VDDCI_ON_SVI2 | MVDD_ON_SVI2) &&
-+		(tab->SVI2Enable & VDDC_ON_SVI2), "SVI2 domain configuration is incorrect!", return -EINVAL);
-+
-+	return 0;
-+}
-+
-+static int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	SMU71_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
-+
-+
-+	iceland_initialize_power_tune_defaults(hwmgr);
-+	memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control) {
-+		iceland_populate_smc_voltage_tables(hwmgr, table);
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-+
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StepVddc))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
-+
-+	if (data->is_memory_gddr5)
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
-+
-+
-+	if (data->ulv_supported) {
-+		result = iceland_populate_ulv_state(hwmgr, &(smu_data->ulv_setting));
-+		PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize ULV state!", return result;);
-+
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_ULV_PARAMETER, 0x40035);
-+	}
-+
-+	result = iceland_populate_smc_link_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize Link Level!", return result;);
-+
-+	result = iceland_populate_all_graphic_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize Graphics Level!", return result;);
-+
-+	result = iceland_populate_all_memory_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize Memory Level!", return result;);
-+
-+	result = iceland_populate_smc_acpi_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize ACPI Level!", return result;);
-+
-+	result = iceland_populate_smc_vce_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize VCE Level!", return result;);
-+
-+	result = iceland_populate_smc_acp_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize ACP Level!", return result;);
-+
-+	result = iceland_populate_smc_samu_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize SAMU Level!", return result;);
-+
-+	/* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
-+	/* need to populate the  ARB settings for the initial state. */
-+	result = iceland_program_memory_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to Write ARB settings for the initial state.", return result;);
-+
-+	result = iceland_populate_smc_uvd_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize UVD Level!", return result;);
-+
-+	table->GraphicsBootLevel = 0;
-+	table->MemoryBootLevel = 0;
-+
-+	result = iceland_populate_smc_boot_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to initialize Boot Level!", return result;);
-+
-+	result = iceland_populate_smc_initial_state(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);
-+
-+	result = iceland_populate_bapm_parameters_in_dpm_table(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);
-+
-+	table->GraphicsVoltageChangeEnable  = 1;
-+	table->GraphicsThermThrottleEnable  = 1;
-+	table->GraphicsInterval = 1;
-+	table->VoltageInterval  = 1;
-+	table->ThermalInterval  = 1;
-+
-+	table->TemperatureLimitHigh =
-+		(data->thermal_temp_setting.temperature_high *
-+		 SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+	table->TemperatureLimitLow =
-+		(data->thermal_temp_setting.temperature_low *
-+		SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-+
-+	table->MemoryVoltageChangeEnable  = 1;
-+	table->MemoryInterval  = 1;
-+	table->VoltageResponseTime  = 0;
-+	table->PhaseResponseTime  = 0;
-+	table->MemoryThermThrottleEnable  = 1;
-+	table->PCIeBootLinkLevel = 0;
-+	table->PCIeGenInterval = 1;
-+
-+	result = iceland_populate_smc_svi2_config(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to populate SVI2 setting!", return result);
-+
-+	table->ThermGpio  = 17;
-+	table->SclkStepSize = 0x4000;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
-+
-+	table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE);
-+	table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE);
-+	table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
-+
-+	/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
-+	result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start +
-+										offsetof(SMU71_Discrete_DpmTable, SystemFlags),
-+										(uint8_t *)&(table->SystemFlags),
-+										sizeof(SMU71_Discrete_DpmTable)-3 * sizeof(SMU71_PIDController),
-+										SMC_RAM_END);
-+
-+	PP_ASSERT_WITH_CODE(0 == result,
-+		"Failed to upload dpm data to SMC memory!", return result;);
-+
-+	/* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */
-+	result = smu7_copy_bytes_to_smc(hwmgr,
-+			smu_data->smu7_data.ulv_setting_starts,
-+			(uint8_t *)&(smu_data->ulv_setting),
-+			sizeof(SMU71_Discrete_Ulv),
-+			SMC_RAM_END);
-+
-+
-+	result = iceland_populate_initial_mc_reg_table(hwmgr);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+		"Failed to populate initialize MC Reg table!", return result);
-+
-+	result = iceland_populate_pm_fuses(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to  populate PM fuses to SMC memory!", return result);
-+
-+	return 0;
-+}
-+
-+int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
-+	SMU71_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
-+	uint32_t duty100;
-+	uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
-+	uint16_t fdo_min, slope1, slope2;
-+	uint32_t reference_clock;
-+	int res;
-+	uint64_t tmp64;
-+
-+	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
-+		return 0;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	if (0 == smu7_data->fan_table_start) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
-+
-+	if (0 == duty100) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
-+	do_div(tmp64, 10000);
-+	fdo_min = (uint16_t)tmp64;
-+
-+	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
-+	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
-+
-+	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
-+	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
-+
-+	slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
-+	slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
-+
-+	fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
-+	fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
-+	fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
-+
-+	fan_table.Slope1 = cpu_to_be16(slope1);
-+	fan_table.Slope2 = cpu_to_be16(slope2);
-+
-+	fan_table.FdoMin = cpu_to_be16(fdo_min);
-+
-+	fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
-+
-+	fan_table.HystUp = cpu_to_be16(1);
-+
-+	fan_table.HystSlope = cpu_to_be16(1);
-+
-+	fan_table.TempRespLim = cpu_to_be16(5);
-+
-+	reference_clock = smu7_get_xclk(hwmgr);
-+
-+	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
-+
-+	fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
-+
-+	fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
-+
-+	/* fan_table.FanControl_GL_Flag = 1; */
-+
-+	res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
-+
-+	return 0;
-+}
-+
-+
-+static int iceland_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	if (data->need_update_smu7_dpm_table &
-+		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
-+		return iceland_program_memory_timing_parameters(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+
-+	int result = 0;
-+	uint32_t low_sclk_interrupt_threshold = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkThrottleLowNotification)
-+		&& (hwmgr->gfx_arbiter.sclk_threshold !=
-+				data->low_sclk_interrupt_threshold)) {
-+		data->low_sclk_interrupt_threshold =
-+				hwmgr->gfx_arbiter.sclk_threshold;
-+		low_sclk_interrupt_threshold =
-+				data->low_sclk_interrupt_threshold;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
-+
-+		result = smu7_copy_bytes_to_smc(
-+				hwmgr,
-+				smu_data->smu7_data.dpm_table_start +
-+				offsetof(SMU71_Discrete_DpmTable,
-+					LowSclkInterruptThreshold),
-+				(uint8_t *)&low_sclk_interrupt_threshold,
-+				sizeof(uint32_t),
-+				SMC_RAM_END);
-+	}
-+
-+	result = iceland_update_and_upload_mc_reg_table(hwmgr);
-+
-+	PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);
-+
-+	result = iceland_program_mem_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			"Failed to program memory timing parameters!",
-+			);
-+
-+	return result;
-+}
-+
-+static uint32_t iceland_get_offsetof(uint32_t type, uint32_t member)
-+{
-+	switch (type) {
-+	case SMU_SoftRegisters:
-+		switch (member) {
-+		case HandshakeDisables:
-+			return offsetof(SMU71_SoftRegisters, HandshakeDisables);
-+		case VoltageChangeTimeout:
-+			return offsetof(SMU71_SoftRegisters, VoltageChangeTimeout);
-+		case AverageGraphicsActivity:
-+			return offsetof(SMU71_SoftRegisters, AverageGraphicsActivity);
-+		case PreVBlankGap:
-+			return offsetof(SMU71_SoftRegisters, PreVBlankGap);
-+		case VBlankTimeout:
-+			return offsetof(SMU71_SoftRegisters, VBlankTimeout);
-+		case UcodeLoadStatus:
-+			return offsetof(SMU71_SoftRegisters, UcodeLoadStatus);
-+		case DRAM_LOG_ADDR_H:
-+			return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_H);
-+		case DRAM_LOG_ADDR_L:
-+			return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_L);
-+		case DRAM_LOG_PHY_ADDR_H:
-+			return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
-+		case DRAM_LOG_PHY_ADDR_L:
-+			return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
-+		case DRAM_LOG_BUFF_SIZE:
-+			return offsetof(SMU71_SoftRegisters, DRAM_LOG_BUFF_SIZE);
-+		}
-+	case SMU_Discrete_DpmTable:
-+		switch (member) {
-+		case LowSclkInterruptThreshold:
-+			return offsetof(SMU71_Discrete_DpmTable, LowSclkInterruptThreshold);
-+		}
-+	}
-+	pr_warn("can't get the offset of type %x member %x\n", type, member);
-+	return 0;
-+}
-+
-+static uint32_t iceland_get_mac_definition(uint32_t value)
-+{
-+	switch (value) {
-+	case SMU_MAX_LEVELS_GRAPHICS:
-+		return SMU71_MAX_LEVELS_GRAPHICS;
-+	case SMU_MAX_LEVELS_MEMORY:
-+		return SMU71_MAX_LEVELS_MEMORY;
-+	case SMU_MAX_LEVELS_LINK:
-+		return SMU71_MAX_LEVELS_LINK;
-+	case SMU_MAX_ENTRIES_SMIO:
-+		return SMU71_MAX_ENTRIES_SMIO;
-+	case SMU_MAX_LEVELS_VDDC:
-+		return SMU71_MAX_LEVELS_VDDC;
-+	case SMU_MAX_LEVELS_VDDCI:
-+		return SMU71_MAX_LEVELS_VDDCI;
-+	case SMU_MAX_LEVELS_MVDD:
-+		return SMU71_MAX_LEVELS_MVDD;
-+	}
-+
-+	pr_warn("can't get the mac of %x\n", value);
-+	return 0;
-+}
-+
-+static int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
-+
-+	uint32_t tmp;
-+	int result;
-+	bool error = false;
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU71_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU71_Firmware_Header, DpmTable),
-+				&tmp, SMC_RAM_END);
-+
-+	if (0 == result) {
-+		smu7_data->dpm_table_start = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU71_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU71_Firmware_Header, SoftRegisters),
-+				&tmp, SMC_RAM_END);
-+
-+	if (0 == result) {
-+		data->soft_regs_start = tmp;
-+		smu7_data->soft_regs_start = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU71_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU71_Firmware_Header, mcRegisterTable),
-+				&tmp, SMC_RAM_END);
-+
-+	if (0 == result) {
-+		smu7_data->mc_reg_table_start = tmp;
-+	}
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU71_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU71_Firmware_Header, FanTable),
-+				&tmp, SMC_RAM_END);
-+
-+	if (0 == result) {
-+		smu7_data->fan_table_start = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU71_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU71_Firmware_Header, mcArbDramTimingTable),
-+				&tmp, SMC_RAM_END);
-+
-+	if (0 == result) {
-+		smu7_data->arb_table_start = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU71_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU71_Firmware_Header, Version),
-+				&tmp, SMC_RAM_END);
-+
-+	if (0 == result) {
-+		hwmgr->microcode_version_info.SMC = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU71_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU71_Firmware_Header, UlvSettings),
-+				&tmp, SMC_RAM_END);
-+
-+	if (0 == result) {
-+		smu7_data->ulv_setting_starts = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+	return error ? 1 : 0;
-+}
-+
-+/*---------------------------MC----------------------------*/
-+
-+static uint8_t iceland_get_memory_modile_index(struct pp_hwmgr *hwmgr)
-+{
-+	return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
-+}
-+
-+static bool iceland_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
-+{
-+	bool result = true;
-+
-+	switch (in_reg) {
-+	case  mmMC_SEQ_RAS_TIMING:
-+		*out_reg = mmMC_SEQ_RAS_TIMING_LP;
-+		break;
-+
-+	case  mmMC_SEQ_DLL_STBY:
-+		*out_reg = mmMC_SEQ_DLL_STBY_LP;
-+		break;
-+
-+	case  mmMC_SEQ_G5PDX_CMD0:
-+		*out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
-+		break;
-+
-+	case  mmMC_SEQ_G5PDX_CMD1:
-+		*out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
-+		break;
-+
-+	case  mmMC_SEQ_G5PDX_CTRL:
-+		*out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
-+		break;
-+
-+	case mmMC_SEQ_CAS_TIMING:
-+		*out_reg = mmMC_SEQ_CAS_TIMING_LP;
-+		break;
-+
-+	case mmMC_SEQ_MISC_TIMING:
-+		*out_reg = mmMC_SEQ_MISC_TIMING_LP;
-+		break;
-+
-+	case mmMC_SEQ_MISC_TIMING2:
-+		*out_reg = mmMC_SEQ_MISC_TIMING2_LP;
-+		break;
-+
-+	case mmMC_SEQ_PMG_DVS_CMD:
-+		*out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
-+		break;
-+
-+	case mmMC_SEQ_PMG_DVS_CTL:
-+		*out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
-+		break;
-+
-+	case mmMC_SEQ_RD_CTL_D0:
-+		*out_reg = mmMC_SEQ_RD_CTL_D0_LP;
-+		break;
-+
-+	case mmMC_SEQ_RD_CTL_D1:
-+		*out_reg = mmMC_SEQ_RD_CTL_D1_LP;
-+		break;
-+
-+	case mmMC_SEQ_WR_CTL_D0:
-+		*out_reg = mmMC_SEQ_WR_CTL_D0_LP;
-+		break;
-+
-+	case mmMC_SEQ_WR_CTL_D1:
-+		*out_reg = mmMC_SEQ_WR_CTL_D1_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_EMRS:
-+		*out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_MRS:
-+		*out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_MRS1:
-+		*out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
-+		break;
-+
-+	case mmMC_SEQ_PMG_TIMING:
-+		*out_reg = mmMC_SEQ_PMG_TIMING_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_MRS2:
-+		*out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
-+		break;
-+
-+	case mmMC_SEQ_WR_CTL_2:
-+		*out_reg = mmMC_SEQ_WR_CTL_2_LP;
-+		break;
-+
-+	default:
-+		result = false;
-+		break;
-+	}
-+
-+	return result;
-+}
-+
-+static int iceland_set_s0_mc_reg_index(struct iceland_mc_reg_table *table)
-+{
-+	uint32_t i;
-+	uint16_t address;
-+
-+	for (i = 0; i < table->last; i++) {
-+		table->mc_reg_address[i].s0 =
-+			iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
-+			? address : table->mc_reg_address[i].s1;
-+	}
-+	return 0;
-+}
-+
-+static int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
-+					struct iceland_mc_reg_table *ni_table)
-+{
-+	uint8_t i, j;
-+
-+	PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+		"Invalid VramInfo table.", return -EINVAL);
-+	PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
-+		"Invalid VramInfo table.", return -EINVAL);
-+
-+	for (i = 0; i < table->last; i++) {
-+		ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
-+	}
-+	ni_table->last = table->last;
-+
-+	for (i = 0; i < table->num_entries; i++) {
-+		ni_table->mc_reg_table_entry[i].mclk_max =
-+			table->mc_reg_table_entry[i].mclk_max;
-+		for (j = 0; j < table->last; j++) {
-+			ni_table->mc_reg_table_entry[i].mc_data[j] =
-+				table->mc_reg_table_entry[i].mc_data[j];
-+		}
-+	}
-+
-+	ni_table->num_entries = table->num_entries;
-+
-+	return 0;
-+}
-+
-+static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
-+					struct iceland_mc_reg_table *table)
-+{
-+	uint8_t i, j, k;
-+	uint32_t temp_reg;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	for (i = 0, j = table->last; i < table->last; i++) {
-+		PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+			"Invalid VramInfo table.", return -EINVAL);
-+
-+		switch (table->mc_reg_address[i].s1) {
-+
-+		case mmMC_SEQ_MISC1:
-+			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
-+			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
-+			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
-+			for (k = 0; k < table->num_entries; k++) {
-+				table->mc_reg_table_entry[k].mc_data[j] =
-+					((temp_reg & 0xffff0000)) |
-+					((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
-+			}
-+			j++;
-+			PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+				"Invalid VramInfo table.", return -EINVAL);
-+
-+			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
-+			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
-+			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
-+			for (k = 0; k < table->num_entries; k++) {
-+				table->mc_reg_table_entry[k].mc_data[j] =
-+					(temp_reg & 0xffff0000) |
-+					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
-+
-+				if (!data->is_memory_gddr5) {
-+					table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
-+				}
-+			}
-+			j++;
-+			PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+				"Invalid VramInfo table.", return -EINVAL);
-+
-+			if (!data->is_memory_gddr5 && j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE) {
-+				table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
-+				table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
-+				for (k = 0; k < table->num_entries; k++) {
-+					table->mc_reg_table_entry[k].mc_data[j] =
-+						(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
-+				}
-+				j++;
-+				PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+					"Invalid VramInfo table.", return -EINVAL);
-+			}
-+
-+			break;
-+
-+		case mmMC_SEQ_RESERVE_M:
-+			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
-+			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
-+			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
-+			for (k = 0; k < table->num_entries; k++) {
-+				table->mc_reg_table_entry[k].mc_data[j] =
-+					(temp_reg & 0xffff0000) |
-+					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
-+			}
-+			j++;
-+			PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+				"Invalid VramInfo table.", return -EINVAL);
-+			break;
-+
-+		default:
-+			break;
-+		}
-+
-+	}
-+
-+	table->last = j;
-+
-+	return 0;
-+}
-+
-+static int iceland_set_valid_flag(struct iceland_mc_reg_table *table)
-+{
-+	uint8_t i, j;
-+	for (i = 0; i < table->last; i++) {
-+		for (j = 1; j < table->num_entries; j++) {
-+			if (table->mc_reg_table_entry[j-1].mc_data[i] !=
-+				table->mc_reg_table_entry[j].mc_data[i]) {
-+				table->validflag |= (1<<i);
-+				break;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
-+	pp_atomctrl_mc_reg_table *table;
-+	struct iceland_mc_reg_table *ni_table = &smu_data->mc_reg_table;
-+	uint8_t module_index = iceland_get_memory_modile_index(hwmgr);
-+
-+	table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
-+
-+	if (NULL == table)
-+		return -ENOMEM;
-+
-+	/* Program additional LP registers that are no longer programmed by VBIOS */
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
-+
-+	memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
-+
-+	result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
-+
-+	if (0 == result)
-+		result = iceland_copy_vbios_smc_reg_table(table, ni_table);
-+
-+	if (0 == result) {
-+		iceland_set_s0_mc_reg_index(ni_table);
-+		result = iceland_set_mc_special_registers(hwmgr, ni_table);
-+	}
-+
-+	if (0 == result)
-+		iceland_set_valid_flag(ni_table);
-+
-+	kfree(table);
-+
-+	return result;
-+}
-+
-+static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr)
-+{
-+	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
-+			CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
-+			? true : false;
-+}
-+
- const struct pp_smumgr_func iceland_smu_funcs = {
- 	.smu_init = &iceland_smu_init,
- 	.smu_fini = &smu7_smu_fini,
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h	2017-12-14 06:39:58.483903615 +0100
-@@ -39,7 +39,7 @@ struct iceland_pt_defaults {
- 	uint8_t   tdc_waterfall_ctl;
- 	uint8_t   dte_ambient_temp_base;
- 	uint32_t  display_cac;
--	uint32_t  bamp_temp_gradient;
-+	uint32_t  bapm_temp_gradient;
- 	uint16_t  bapmti_r[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS];
- 	uint16_t  bapmti_rc[SMU71_DTE_ITERATIONS * SMU71_DTE_SOURCES * SMU71_DTE_SINKS];
- };
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/Makefile	2017-12-14 06:39:58.483903615 +0100
-@@ -3,9 +3,9 @@
- # Makefile for the 'smu manager' sub-component of powerplay.
- # It provides the smu management services for the driver.
- 
--SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \
--	  polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \
--	  smu7_smumgr.o iceland_smc.o vega10_smumgr.o rv_smumgr.o
-+SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o \
-+	  polaris10_smumgr.o iceland_smumgr.o \
-+	  smu7_smumgr.o vega10_smumgr.o rv_smumgr.o ci_smumgr.o
- 
- AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
- 
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c	2017-12-14 06:39:58.484903615 +0100
-@@ -35,13 +35,47 @@
- #include "gca/gfx_8_0_d.h"
- #include "bif/bif_5_0_d.h"
- #include "bif/bif_5_0_sh_mask.h"
--#include "polaris10_pwrvirus.h"
- #include "ppatomctrl.h"
- #include "cgs_common.h"
--#include "polaris10_smc.h"
- #include "smu7_ppsmc.h"
- #include "smu7_smumgr.h"
- 
-+#include "smu7_dyn_defaults.h"
-+
-+#include "smu7_hwmgr.h"
-+#include "hardwaremanager.h"
-+#include "ppatomctrl.h"
-+#include "atombios.h"
-+#include "pppcielanes.h"
-+
-+#include "dce/dce_10_0_d.h"
-+#include "dce/dce_10_0_sh_mask.h"
-+
-+#define POLARIS10_SMC_SIZE 0x20000
-+#define VOLTAGE_VID_OFFSET_SCALE1   625
-+#define VOLTAGE_VID_OFFSET_SCALE2   100
-+#define POWERTUNE_DEFAULT_SET_MAX    1
-+#define VDDC_VDDCI_DELTA            200
-+#define MC_CG_ARB_FREQ_F1           0x0b
-+
-+static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
-+	/* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
-+	 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
-+	{ 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
-+	{ 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
-+	{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
-+};
-+
-+static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
-+			{VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
-+			{VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
-+			{VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
-+			{VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
-+			{VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
-+			{VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
-+			{VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
-+			{VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
-+
- #define PPPOLARIS10_TARGETACTIVITY_DFLT                     50
- 
- static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
-@@ -60,46 +94,13 @@ static const SMU74_Discrete_GraphicsLeve
- static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
- 	0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
- 
--static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr)
--{
--	int i;
--	int result = -EINVAL;
--	uint32_t reg, data;
--
--	const PWR_Command_Table *pvirus = pwr_virus_table;
--	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
--
--	for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
--		switch (pvirus->command) {
--		case PwrCmdWrite:
--			reg  = pvirus->reg;
--			data = pvirus->data;
--			cgs_write_register(smumgr->device, reg, data);
--			break;
--
--		case PwrCmdEnd:
--			result = 0;
--			break;
--
--		default:
--			pr_info("Table Exit with Invalid Command!");
--			smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
--			result = -EINVAL;
--			break;
--		}
--		pvirus++;
--	}
--
--	return result;
--}
--
--static int polaris10_perform_btc(struct pp_smumgr *smumgr)
-+static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
- {
- 	int result = 0;
--	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
-+	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
- 
- 	if (0 != smu_data->avfs.avfs_btc_param) {
--		if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
-+		if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
- 			pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
- 			result = -1;
- 		}
-@@ -107,16 +108,16 @@ static int polaris10_perform_btc(struct
- 	if (smu_data->avfs.avfs_btc_param > 1) {
- 		/* Soft-Reset to reset the engine before loading uCode */
- 		/* halt */
--		cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000);
-+		cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
- 		/* reset everything */
--		cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
--		cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
-+		cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
-+		cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
- 	}
- 	return result;
- }
- 
- 
--static int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr)
-+static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
- {
- 	uint32_t vr_config;
- 	uint32_t dpm_table_start;
-@@ -127,7 +128,7 @@ static int polaris10_setup_graphics_leve
- 	graphics_level_size = sizeof(avfs_graphics_level_polaris10);
- 	u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
- 
--	PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr,
-+	PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
- 				SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
- 				&dpm_table_start, 0x40000),
- 			"[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
-@@ -138,14 +139,14 @@ static int polaris10_setup_graphics_leve
- 
- 	vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
- 
--	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_address,
-+	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
- 				(uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
- 			"[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
- 			return -1);
- 
- 	graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
- 
--	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
-+	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
- 				(uint8_t *)(&avfs_graphics_level_polaris10),
- 				graphics_level_size, 0x40000),
- 			"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
-@@ -153,7 +154,7 @@ static int polaris10_setup_graphics_leve
- 
- 	graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
- 
--	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
-+	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
- 				(uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
- 				"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
- 			return -1);
-@@ -162,7 +163,7 @@ static int polaris10_setup_graphics_leve
- 
- 	graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
- 
--	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, graphics_level_address,
-+	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
- 			(uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
- 			"[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
- 			return -1);
-@@ -172,9 +173,9 @@ static int polaris10_setup_graphics_leve
- 
- 
- static int
--polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT)
-+polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool SMU_VFT_INTACT)
- {
--	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
-+	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
- 
- 	switch (smu_data->avfs.avfs_btc_status) {
- 	case AVFS_BTC_COMPLETED_PREVIOUSLY:
-@@ -183,20 +184,20 @@ polaris10_avfs_event_mgr(struct pp_smumg
- 	case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
- 
- 		smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
--		PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(smumgr),
-+		PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
- 			"[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
- 			return -EINVAL);
- 
- 		if (smu_data->avfs.avfs_btc_param > 1) {
- 			pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
- 			smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
--			PP_ASSERT_WITH_CODE(0 == polaris10_setup_pwr_virus(smumgr),
-+			PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
- 			"[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
- 			return -EINVAL);
- 		}
- 
- 		smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
--		PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(smumgr),
-+		PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
- 					"[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
- 				 return -EINVAL);
- 		smu_data->avfs.avfs_btc_status = AVFS_BTC_ENABLEAVFS;
-@@ -215,146 +216,146 @@ polaris10_avfs_event_mgr(struct pp_smumg
- 	return 0;
- }
- 
--static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
-+static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
- {
- 	int result = 0;
- 
- 	/* Wait for smc boot up */
--	/* SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
-+	/* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
- 
- 	/* Assert reset */
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
- 
--	result = smu7_upload_smu_firmware_image(smumgr);
-+	result = smu7_upload_smu_firmware_image(hwmgr);
- 	if (result != 0)
- 		return result;
- 
- 	/* Clear status */
--	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
- 
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 					SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
- 
- 	/* De-assert reset */
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
- 
- 
--	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
-+	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
- 
- 
- 	/* Call Test SMU message with 0x20000 offset to trigger SMU start */
--	smu7_send_msg_to_smc_offset(smumgr);
-+	smu7_send_msg_to_smc_offset(hwmgr);
- 
- 	/* Wait done bit to be set */
- 	/* Check pass/failed indicator */
- 
--	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
-+	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
- 
--	if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 						SMU_STATUS, SMU_PASS))
- 		PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
- 
--	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
- 
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 					SMC_SYSCON_RESET_CNTL, rst_reg, 1);
- 
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
- 
- 	/* Wait for firmware to initialize */
--	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
-+	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
- 
- 	return result;
- }
- 
--static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
-+static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
- {
- 	int result = 0;
- 
- 	/* wait for smc boot up */
--	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
-+	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
- 
- 	/* Clear firmware interrupt enable flag */
--	/* SMUM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
--	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+	/* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- 				ixFIRMWARE_FLAGS, 0);
- 
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 					SMC_SYSCON_RESET_CNTL,
- 					rst_reg, 1);
- 
--	result = smu7_upload_smu_firmware_image(smumgr);
-+	result = smu7_upload_smu_firmware_image(hwmgr);
- 	if (result != 0)
- 		return result;
- 
- 	/* Set smc instruct start point at 0x0 */
--	smu7_program_jump_on_start(smumgr);
-+	smu7_program_jump_on_start(hwmgr);
- 
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 					SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
- 
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 					SMC_SYSCON_RESET_CNTL, rst_reg, 0);
- 
- 	/* Wait for firmware to initialize */
- 
--	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
-+	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
- 					FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
- 
- 	return result;
- }
- 
--static int polaris10_start_smu(struct pp_smumgr *smumgr)
-+static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
- {
- 	int result = 0;
--	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
- 	bool SMU_VFT_INTACT;
- 
- 	/* Only start SMC if SMC RAM is not running */
--	if (!smu7_is_smc_ram_running(smumgr)) {
-+	if (!smu7_is_smc_ram_running(hwmgr)) {
- 		SMU_VFT_INTACT = false;
--		smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
--		smu_data->smu7_data.security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
-+		smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
-+		smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
- 
- 		/* Check if SMU is running in protected mode */
- 		if (smu_data->protected_mode == 0) {
--			result = polaris10_start_smu_in_non_protection_mode(smumgr);
-+			result = polaris10_start_smu_in_non_protection_mode(hwmgr);
- 		} else {
--			result = polaris10_start_smu_in_protection_mode(smumgr);
-+			result = polaris10_start_smu_in_protection_mode(hwmgr);
- 
- 			/* If failed, try with different security Key. */
- 			if (result != 0) {
- 				smu_data->smu7_data.security_hard_key ^= 1;
--				cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
--				result = polaris10_start_smu_in_protection_mode(smumgr);
-+				cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
-+				result = polaris10_start_smu_in_protection_mode(hwmgr);
- 			}
- 		}
- 
- 		if (result != 0)
- 			PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
- 
--		polaris10_avfs_event_mgr(smumgr, true);
-+		polaris10_avfs_event_mgr(hwmgr, true);
- 	} else
- 		SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
- 
--	polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT);
-+	polaris10_avfs_event_mgr(hwmgr, SMU_VFT_INTACT);
- 	/* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
--	smu7_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
-+	smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
- 					&(smu_data->smu7_data.soft_regs_start), 0x40000);
- 
--	result = smu7_request_smu_load_fw(smumgr);
-+	result = smu7_request_smu_load_fw(hwmgr);
- 
- 	return result;
- }
- 
--static bool polaris10_is_hw_avfs_present(struct pp_smumgr *smumgr)
-+static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
- {
- 	uint32_t efuse;
- 
--	efuse = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
-+	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
- 	efuse &= 0x00000001;
- 	if (efuse)
- 		return true;
-@@ -362,7 +363,7 @@ static bool polaris10_is_hw_avfs_present
- 	return false;
- }
- 
--static int polaris10_smu_init(struct pp_smumgr *smumgr)
-+static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
- {
- 	struct polaris10_smumgr *smu_data;
- 	int i;
-@@ -371,9 +372,9 @@ static int polaris10_smu_init(struct pp_
- 	if (smu_data == NULL)
- 		return -ENOMEM;
- 
--	smumgr->backend = smu_data;
-+	hwmgr->smu_backend = smu_data;
- 
--	if (smu7_init(smumgr))
-+	if (smu7_init(hwmgr))
- 		return -EINVAL;
- 
- 	for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++)
-@@ -382,6 +383,2195 @@ static int polaris10_smu_init(struct pp_
- 	return 0;
- }
- 
-+static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
-+		struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
-+		uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
-+{
-+	uint32_t i;
-+	uint16_t vddci;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	*voltage = *mvdd = 0;
-+
-+	/* clock - voltage dependency table is empty table */
-+	if (dep_table->count == 0)
-+		return -EINVAL;
-+
-+	for (i = 0; i < dep_table->count; i++) {
-+		/* find first sclk bigger than request */
-+		if (dep_table->entries[i].clk >= clock) {
-+			*voltage |= (dep_table->entries[i].vddc *
-+					VOLTAGE_SCALE) << VDDC_SHIFT;
-+			if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
-+				*voltage |= (data->vbios_boot_state.vddci_bootup_value *
-+						VOLTAGE_SCALE) << VDDCI_SHIFT;
-+			else if (dep_table->entries[i].vddci)
-+				*voltage |= (dep_table->entries[i].vddci *
-+						VOLTAGE_SCALE) << VDDCI_SHIFT;
-+			else {
-+				vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
-+						(dep_table->entries[i].vddc -
-+								(uint16_t)VDDC_VDDCI_DELTA));
-+				*voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+			}
-+
-+			if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
-+				*mvdd = data->vbios_boot_state.mvdd_bootup_value *
-+					VOLTAGE_SCALE;
-+			else if (dep_table->entries[i].mvdd)
-+				*mvdd = (uint32_t) dep_table->entries[i].mvdd *
-+					VOLTAGE_SCALE;
-+
-+			*voltage |= 1 << PHASES_SHIFT;
-+			return 0;
-+		}
-+	}
-+
-+	/* sclk is bigger than max sclk in the dependence table */
-+	*voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
-+		*voltage |= (data->vbios_boot_state.vddci_bootup_value *
-+				VOLTAGE_SCALE) << VDDCI_SHIFT;
-+	else if (dep_table->entries[i-1].vddci) {
-+		vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
-+				(dep_table->entries[i].vddc -
-+						(uint16_t)VDDC_VDDCI_DELTA));
-+		*voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+	}
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
-+		*mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
-+	else if (dep_table->entries[i].mvdd)
-+		*mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
-+
-+	return 0;
-+}
-+
-+static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
-+{
-+	uint32_t tmp;
-+	tmp = raw_setting * 4096 / 100;
-+	return (uint16_t)tmp;
-+}
-+
-+static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+
-+	const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
-+	SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
-+	struct pp_advance_fan_control_parameters *fan_table =
-+			&hwmgr->thermal_controller.advanceFanControlParameters;
-+	int i, j, k;
-+	const uint16_t *pdef1;
-+	const uint16_t *pdef2;
-+
-+	table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
-+	table->TargetTdp  = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
-+
-+	PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
-+				"Target Operating Temp is out of Range!",
-+				);
-+
-+	table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTargetOperatingTemp * 256);
-+	table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
-+			cac_dtp_table->usTemperatureLimitHotspot * 256);
-+	table->FanGainEdge = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainEdge));
-+	table->FanGainHotspot = PP_HOST_TO_SMC_US(
-+			scale_fan_gain_settings(fan_table->usFanGainHotspot));
-+
-+	pdef1 = defaults->BAPMTI_R;
-+	pdef2 = defaults->BAPMTI_RC;
-+
-+	for (i = 0; i < SMU74_DTE_ITERATIONS; i++) {
-+		for (j = 0; j < SMU74_DTE_SOURCES; j++) {
-+			for (k = 0; k < SMU74_DTE_SINKS; k++) {
-+				table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
-+				table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
-+				pdef1++;
-+				pdef2++;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
-+
-+	smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
-+	smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
-+	smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
-+	smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
-+{
-+	uint16_t tdc_limit;
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
-+
-+	tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
-+	smu_data->power_tune_table.TDC_VDDC_PkgLimit =
-+			CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
-+	smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
-+			defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
-+	smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
-+	uint32_t temp;
-+
-+	if (smu7_read_smc_sram_dword(hwmgr,
-+			fuse_table_offset +
-+			offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
-+			(uint32_t *)&temp, SMC_RAM_END))
-+		PP_ASSERT_WITH_CODE(false,
-+				"Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
-+				return -EINVAL);
-+	else {
-+		smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
-+		smu_data->power_tune_table.LPMLTemperatureMin =
-+				(uint8_t)((temp >> 16) & 0xff);
-+		smu_data->power_tune_table.LPMLTemperatureMax =
-+				(uint8_t)((temp >> 8) & 0xff);
-+		smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
-+	}
-+	return 0;
-+}
-+
-+static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+
-+	/* Currently not used. Set all to zero. */
-+	for (i = 0; i < 16; i++)
-+		smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+
-+/* TO DO move to hwmgr */
-+	if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
-+		|| 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
-+		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
-+			hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
-+
-+	smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
-+				hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
-+	return 0;
-+}
-+
-+static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+
-+	/* Currently not used. Set all to zero. */
-+	for (i = 0; i < 16; i++)
-+		smu_data->power_tune_table.GnbLPML[i] = 0;
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
-+	uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
-+	struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
-+
-+	hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
-+	lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
-+
-+	smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
-+	smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	uint32_t pm_fuse_table_offset;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment)) {
-+		if (smu7_read_smc_sram_dword(hwmgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU74_Firmware_Header, PmFuseTable),
-+				&pm_fuse_table_offset, SMC_RAM_END))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to get pm_fuse_table_offset Failed!",
-+					return -EINVAL);
-+
-+		if (polaris10_populate_svi_load_line(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate SviLoadLine Failed!",
-+					return -EINVAL);
-+
-+		if (polaris10_populate_tdc_limit(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate TDCLimit Failed!", return -EINVAL);
-+
-+		if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate TdcWaterfallCtl, "
-+					"LPMLTemperature Min and Max Failed!",
-+					return -EINVAL);
-+
-+		if (0 != polaris10_populate_temperature_scaler(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate LPMLTemperatureScaler Failed!",
-+					return -EINVAL);
-+
-+		if (polaris10_populate_fuzzy_fan(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate Fuzzy Fan Control parameters Failed!",
-+					return -EINVAL);
-+
-+		if (polaris10_populate_gnb_lpml(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate GnbLPML Failed!",
-+					return -EINVAL);
-+
-+		if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate BapmVddCBaseLeakage Hi and Lo "
-+					"Sidd Failed!", return -EINVAL);
-+
-+		if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
-+				(uint8_t *)&smu_data->power_tune_table,
-+				(sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to download PmFuseTable Failed!",
-+					return -EINVAL);
-+	}
-+	return 0;
-+}
-+
-+static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
-+			SMU74_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t count, level;
-+
-+	if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		count = data->mvdd_voltage_table.count;
-+		if (count > SMU_MAX_SMIO_LEVELS)
-+			count = SMU_MAX_SMIO_LEVELS;
-+		for (level = 0; level < count; level++) {
-+			table->SmioTable2.Pattern[level].Voltage =
-+				PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+			/* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
-+			table->SmioTable2.Pattern[level].Smio =
-+				(uint8_t) level;
-+			table->Smio[level] |=
-+				data->mvdd_voltage_table.entries[level].smio_low;
-+		}
-+		table->SmioMask2 = data->mvdd_voltage_table.mask_low;
-+
-+		table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
-+					struct SMU74_Discrete_DpmTable *table)
-+{
-+	uint32_t count, level;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	count = data->vddci_voltage_table.count;
-+
-+	if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
-+		if (count > SMU_MAX_SMIO_LEVELS)
-+			count = SMU_MAX_SMIO_LEVELS;
-+		for (level = 0; level < count; ++level) {
-+			table->SmioTable1.Pattern[level].Voltage =
-+				PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
-+			table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
-+
-+			table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
-+		}
-+	}
-+
-+	table->SmioMask1 = data->vddci_voltage_table.mask_low;
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	uint32_t count;
-+	uint8_t index;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_voltage_lookup_table *lookup_table =
-+			table_info->vddc_lookup_table;
-+	/* tables is already swapped, so in order to use the value from it,
-+	 * we need to swap it back.
-+	 * We are populating vddc CAC data to BapmVddc table
-+	 * in split and merged mode
-+	 */
-+	for (count = 0; count < lookup_table->count; count++) {
-+		index = phm_get_voltage_index(lookup_table,
-+				data->vddc_voltage_table.entries[count].value);
-+		table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
-+		table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
-+		table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	polaris10_populate_smc_vddci_table(hwmgr, table);
-+	polaris10_populate_smc_mvdd_table(hwmgr, table);
-+	polaris10_populate_cac_table(hwmgr, table);
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_Ulv *state)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	state->CcPwrDynRm = 0;
-+	state->CcPwrDynRm1 = 0;
-+
-+	state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
-+	state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
-+			VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
-+
-+	if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker)
-+		state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
-+	else
-+		state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
-+	CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
-+}
-+
-+static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_dpm_table *dpm_table = &data->dpm_table;
-+	int i;
-+
-+	/* Index (dpm_table->pcie_speed_table.count)
-+	 * is reserved for PCIE boot level. */
-+	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
-+		table->LinkLevel[i].PcieGenSpeed  =
-+				(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
-+		table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
-+				dpm_table->pcie_speed_table.dpm_levels[i].param1);
-+		table->LinkLevel[i].EnabledForActivity = 1;
-+		table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
-+		table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
-+		table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
-+	}
-+
-+	smu_data->smc_state_table.LinkLevelCount =
-+			(uint8_t)dpm_table->pcie_speed_table.count;
-+
-+/* To Do move to hwmgr */
-+	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
-+
-+	return 0;
-+}
-+
-+
-+static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
-+				   SMU74_Discrete_DpmTable  *table)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	uint32_t i, ref_clk;
-+
-+	struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
-+
-+	ref_clk = smu7_get_xclk(hwmgr);
-+
-+	if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
-+		for (i = 0; i < NUM_SCLK_RANGE; i++) {
-+			table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
-+			table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
-+			table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
-+
-+			table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
-+			table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
-+
-+			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
-+			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
-+			CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
-+		}
-+		return;
-+	}
-+
-+	for (i = 0; i < NUM_SCLK_RANGE; i++) {
-+		smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
-+		smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
-+
-+		table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
-+		table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
-+		table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
-+
-+		table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
-+		table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
-+
-+		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
-+		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
-+		CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
-+	}
-+}
-+
-+static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, SMU_SclkSetting *sclk_setting)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
-+	struct pp_atomctrl_clock_dividers_ai dividers;
-+	uint32_t ref_clock;
-+	uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
-+	uint8_t i;
-+	int result;
-+	uint64_t temp;
-+
-+	sclk_setting->SclkFrequency = clock;
-+	/* get the engine clock dividers for this clock value */
-+	result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
-+	if (result == 0) {
-+		sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
-+		sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
-+		sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
-+		sclk_setting->PllRange = dividers.ucSclkPllRange;
-+		sclk_setting->Sclk_slew_rate = 0x400;
-+		sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
-+		sclk_setting->Pcc_down_slew_rate = 0xffff;
-+		sclk_setting->SSc_En = dividers.ucSscEnable;
-+		sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
-+		sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
-+		sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
-+		return result;
-+	}
-+
-+	ref_clock = smu7_get_xclk(hwmgr);
-+
-+	for (i = 0; i < NUM_SCLK_RANGE; i++) {
-+		if (clock > smu_data->range_table[i].trans_lower_frequency
-+		&& clock <= smu_data->range_table[i].trans_upper_frequency) {
-+			sclk_setting->PllRange = i;
-+			break;
-+		}
-+	}
-+
-+	sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
-+	temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
-+	temp <<= 0x10;
-+	do_div(temp, ref_clock);
-+	sclk_setting->Fcw_frac = temp & 0xffff;
-+
-+	pcc_target_percent = 10; /*  Hardcode 10% for now. */
-+	pcc_target_freq = clock - (clock * pcc_target_percent / 100);
-+	sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
-+
-+	ss_target_percent = 2; /*  Hardcode 2% for now. */
-+	sclk_setting->SSc_En = 0;
-+	if (ss_target_percent) {
-+		sclk_setting->SSc_En = 1;
-+		ss_target_freq = clock - (clock * ss_target_percent / 100);
-+		sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
-+		temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
-+		temp <<= 0x10;
-+		do_div(temp, ref_clock);
-+		sclk_setting->Fcw1_frac = temp & 0xffff;
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, uint16_t sclk_al_threshold,
-+		struct SMU74_Discrete_GraphicsLevel *level)
-+{
-+	int result;
-+	/* PP_Clocks minClocks; */
-+	uint32_t mvdd;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	SMU_SclkSetting curr_sclk_setting = { 0 };
-+
-+	result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
-+
-+	/* populate graphics levels */
-+	result = polaris10_get_dependency_volt_by_clk(hwmgr,
-+			table_info->vdd_dep_on_sclk, clock,
-+			&level->MinVoltage, &mvdd);
-+
-+	PP_ASSERT_WITH_CODE((0 == result),
-+			"can not find VDDC voltage value for "
-+			"VDDC engine clock dependency table",
-+			return result);
-+	level->ActivityLevel = sclk_al_threshold;
-+
-+	level->CcPwrDynRm = 0;
-+	level->CcPwrDynRm1 = 0;
-+	level->EnabledForActivity = 0;
-+	level->EnabledForThrottle = 1;
-+	level->UpHyst = 10;
-+	level->DownHyst = 0;
-+	level->VoltageDownHyst = 0;
-+	level->PowerThrottle = 0;
-+	data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
-+		level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
-+								hwmgr->display_config.min_core_set_clock_in_sr);
-+
-+	/* Default to slow, highest DPM level will be
-+	 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
-+	 */
-+	if (data->update_up_hyst)
-+		level->UpHyst = (uint8_t)data->up_hyst;
-+	if (data->update_down_hyst)
-+		level->DownHyst = (uint8_t)data->down_hyst;
-+
-+	level->SclkSetting = curr_sclk_setting;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
-+	CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
-+	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
-+	return 0;
-+}
-+
-+static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
-+	uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
-+	int result = 0;
-+	uint32_t array = smu_data->smu7_data.dpm_table_start +
-+			offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
-+	uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
-+			SMU74_MAX_LEVELS_GRAPHICS;
-+	struct SMU74_Discrete_GraphicsLevel *levels =
-+			smu_data->smc_state_table.GraphicsLevel;
-+	uint32_t i, max_entry;
-+	uint8_t hightest_pcie_level_enabled = 0,
-+		lowest_pcie_level_enabled = 0,
-+		mid_pcie_level_enabled = 0,
-+		count = 0;
-+
-+	polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
-+
-+	for (i = 0; i < dpm_table->sclk_table.count; i++) {
-+
-+		result = polaris10_populate_single_graphic_level(hwmgr,
-+				dpm_table->sclk_table.dpm_levels[i].value,
-+				(uint16_t)smu_data->activity_target[i],
-+				&(smu_data->smc_state_table.GraphicsLevel[i]));
-+		if (result)
-+			return result;
-+
-+		/* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
-+		if (i > 1)
-+			levels[i].DeepSleepDivId = 0;
-+	}
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_SPLLShutdownSupport))
-+		smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
-+
-+	smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
-+	smu_data->smc_state_table.GraphicsDpmLevelCount =
-+			(uint8_t)dpm_table->sclk_table.count;
-+	hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
-+
-+
-+	if (pcie_table != NULL) {
-+		PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
-+				"There must be 1 or more PCIE levels defined in PPTable.",
-+				return -EINVAL);
-+		max_entry = pcie_entry_cnt - 1;
-+		for (i = 0; i < dpm_table->sclk_table.count; i++)
-+			levels[i].pcieDpmLevel =
-+					(uint8_t) ((i < max_entry) ? i : max_entry);
-+	} else {
-+		while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
-+				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << (hightest_pcie_level_enabled + 1))) != 0))
-+			hightest_pcie_level_enabled++;
-+
-+		while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
-+				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << lowest_pcie_level_enabled)) == 0))
-+			lowest_pcie_level_enabled++;
-+
-+		while ((count < hightest_pcie_level_enabled) &&
-+				((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+						(1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
-+			count++;
-+
-+		mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
-+				hightest_pcie_level_enabled ?
-+						(lowest_pcie_level_enabled + 1 + count) :
-+						hightest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to hightest_pcie_level_enabled */
-+		for (i = 2; i < dpm_table->sclk_table.count; i++)
-+			levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to lowest_pcie_level_enabled */
-+		levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to mid_pcie_level_enabled */
-+		levels[1].pcieDpmLevel = mid_pcie_level_enabled;
-+	}
-+	/* level count will send to smc once at init smc table and never change */
-+	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
-+			(uint32_t)array_size, SMC_RAM_END);
-+
-+	return result;
-+}
-+
-+
-+static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
-+		uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	int result = 0;
-+	struct cgs_display_info info = {0, 0, NULL};
-+	uint32_t mclk_stutter_mode_threshold = 40000;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+
-+	if (table_info->vdd_dep_on_mclk) {
-+		result = polaris10_get_dependency_volt_by_clk(hwmgr,
-+				table_info->vdd_dep_on_mclk, clock,
-+				&mem_level->MinVoltage, &mem_level->MinMvdd);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find MinVddc voltage value from memory "
-+				"VDDC voltage dependency table", return result);
-+	}
-+
-+	mem_level->MclkFrequency = clock;
-+	mem_level->EnabledForThrottle = 1;
-+	mem_level->EnabledForActivity = 0;
-+	mem_level->UpHyst = 0;
-+	mem_level->DownHyst = 100;
-+	mem_level->VoltageDownHyst = 0;
-+	mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
-+	mem_level->StutterEnable = false;
-+	mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	data->display_timing.num_existing_displays = info.display_count;
-+
-+	if (mclk_stutter_mode_threshold &&
-+		(clock <= mclk_stutter_mode_threshold) &&
-+		(PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
-+				STUTTER_ENABLE) & 0x1))
-+		mem_level->StutterEnable = true;
-+
-+	if (!result) {
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
-+		CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
-+	int result;
-+	/* populate MCLK dpm table to SMU7 */
-+	uint32_t array = smu_data->smu7_data.dpm_table_start +
-+			offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
-+	uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
-+			SMU74_MAX_LEVELS_MEMORY;
-+	struct SMU74_Discrete_MemoryLevel *levels =
-+			smu_data->smc_state_table.MemoryLevel;
-+	uint32_t i;
-+
-+	for (i = 0; i < dpm_table->mclk_table.count; i++) {
-+		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
-+				"can not populate memory level as memory clock is zero",
-+				return -EINVAL);
-+		result = polaris10_populate_single_memory_level(hwmgr,
-+				dpm_table->mclk_table.dpm_levels[i].value,
-+				&levels[i]);
-+		if (i == dpm_table->mclk_table.count - 1) {
-+			levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
-+			levels[i].EnabledForActivity = 1;
-+		}
-+		if (result)
-+			return result;
-+	}
-+
-+	/* In order to prevent MC activity from stutter mode to push DPM up,
-+	 * the UVD change complements this by putting the MCLK in
-+	 * a higher state by default such that we are not affected by
-+	 * up threshold or and MCLK DPM latency.
-+	 */
-+	levels[0].ActivityLevel = 0x1f;
-+	CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
-+
-+	smu_data->smc_state_table.MemoryDpmLevelCount =
-+			(uint8_t)dpm_table->mclk_table.count;
-+	hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
-+			phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
-+
-+	/* level count will send to smc once at init smc table and never change */
-+	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
-+			(uint32_t)array_size, SMC_RAM_END);
-+
-+	return result;
-+}
-+
-+static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
-+		uint32_t mclk, SMIO_Pattern *smio_pat)
-+{
-+	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint32_t i = 0;
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
-+		/* find mvdd value which clock is more than request */
-+		for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
-+			if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
-+				smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
-+				break;
-+			}
-+		}
-+		PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
-+				"MVDD Voltage is outside the supported range.",
-+				return -EINVAL);
-+	} else
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
-+		SMU74_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	uint32_t sclk_frequency;
-+	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	SMIO_Pattern vol_level;
-+	uint32_t mvdd;
-+	uint16_t us_mvdd;
-+
-+	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
-+
-+	/* Get MinVoltage and Frequency from DPM0,
-+	 * already converted to SMC_UL */
-+	sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
-+	result = polaris10_get_dependency_volt_by_clk(hwmgr,
-+			table_info->vdd_dep_on_sclk,
-+			sclk_frequency,
-+			&table->ACPILevel.MinVoltage, &mvdd);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+			"Cannot find ACPI VDDC voltage value "
-+			"in Clock Dependency Table",
-+			);
-+
-+	result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
-+	PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
-+
-+	table->ACPILevel.DeepSleepDivId = 0;
-+	table->ACPILevel.CcPwrDynRm = 0;
-+	table->ACPILevel.CcPwrDynRm1 = 0;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
-+
-+
-+	/* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
-+	table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
-+	result = polaris10_get_dependency_volt_by_clk(hwmgr,
-+			table_info->vdd_dep_on_mclk,
-+			table->MemoryACPILevel.MclkFrequency,
-+			&table->MemoryACPILevel.MinVoltage, &mvdd);
-+	PP_ASSERT_WITH_CODE((0 == result),
-+			"Cannot find ACPI VDDCI voltage value "
-+			"in Clock Dependency Table",
-+			);
-+
-+	us_mvdd = 0;
-+	if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
-+			(data->mclk_dpm_key_disabled))
-+		us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
-+	else {
-+		if (!polaris10_populate_mvdd_value(hwmgr,
-+				data->dpm_table.mclk_table.dpm_levels[0].value,
-+				&vol_level))
-+			us_mvdd = vol_level.Voltage;
-+	}
-+
-+	if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
-+		table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
-+	else
-+		table->MemoryACPILevel.MinMvdd = 0;
-+
-+	table->MemoryACPILevel.StutterEnable = false;
-+
-+	table->MemoryACPILevel.EnabledForThrottle = 0;
-+	table->MemoryACPILevel.EnabledForActivity = 0;
-+	table->MemoryACPILevel.UpHyst = 0;
-+	table->MemoryACPILevel.DownHyst = 100;
-+	table->MemoryACPILevel.VoltageDownHyst = 0;
-+	table->MemoryACPILevel.ActivityLevel =
-+			PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
-+
-+	return result;
-+}
-+
-+static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
-+		SMU74_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t vddci;
-+
-+	table->VceLevelCount = (uint8_t)(mm_table->count);
-+	table->VceBootLevel = 0;
-+
-+	for (count = 0; count < table->VceLevelCount; count++) {
-+		table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
-+		table->VceLevel[count].MinVoltage = 0;
-+		table->VceLevel[count].MinVoltage |=
-+				(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
-+
-+		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
-+			vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
-+						mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
-+		else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
-+			vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
-+		else
-+			vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+
-+
-+		table->VceLevel[count].MinVoltage |=
-+				(vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/*retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->VceLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for VCE engine clock",
-+				return result);
-+
-+		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+
-+static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-+		SMU74_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t vddci;
-+
-+	table->SamuBootLevel = 0;
-+	table->SamuLevelCount = (uint8_t)(mm_table->count);
-+
-+	for (count = 0; count < table->SamuLevelCount; count++) {
-+		/* not sure whether we need evclk or not */
-+		table->SamuLevel[count].MinVoltage = 0;
-+		table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
-+		table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-+				VOLTAGE_SCALE) << VDDC_SHIFT;
-+
-+		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
-+			vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
-+						mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
-+		else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
-+			vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
-+		else
-+			vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+
-+		table->SamuLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->SamuLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for samu clock", return result);
-+
-+		table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
-+	}
-+	return result;
-+}
-+
-+static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
-+		int32_t eng_clock, int32_t mem_clock,
-+		SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
-+{
-+	uint32_t dram_timing;
-+	uint32_t dram_timing2;
-+	uint32_t burst_time;
-+	int result;
-+
-+	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
-+			eng_clock, mem_clock);
-+	PP_ASSERT_WITH_CODE(result == 0,
-+			"Error calling VBIOS to set DRAM_TIMING.", return result);
-+
-+	dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
-+	dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
-+	burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
-+
-+
-+	arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
-+	arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
-+	arb_regs->McArbBurstTime   = (uint8_t)burst_time;
-+
-+	return 0;
-+}
-+
-+static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
-+	uint32_t i, j;
-+	int result = 0;
-+
-+	for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
-+		for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
-+			result = polaris10_populate_memory_timing_parameters(hwmgr,
-+					hw_data->dpm_table.sclk_table.dpm_levels[i].value,
-+					hw_data->dpm_table.mclk_table.dpm_levels[j].value,
-+					&arb_regs.entries[i][j]);
-+			if (result == 0)
-+				result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
-+			if (result != 0)
-+				return result;
-+		}
-+	}
-+
-+	result = smu7_copy_bytes_to_smc(
-+			hwmgr,
-+			smu_data->smu7_data.arb_table_start,
-+			(uint8_t *)&arb_regs,
-+			sizeof(SMU74_Discrete_MCArbDramTimingTable),
-+			SMC_RAM_END);
-+	return result;
-+}
-+
-+static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	int result = -EINVAL;
-+	uint8_t count;
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+			table_info->mm_dep_table;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t vddci;
-+
-+	table->UvdLevelCount = (uint8_t)(mm_table->count);
-+	table->UvdBootLevel = 0;
-+
-+	for (count = 0; count < table->UvdLevelCount; count++) {
-+		table->UvdLevel[count].MinVoltage = 0;
-+		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
-+		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
-+		table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
-+				VOLTAGE_SCALE) << VDDC_SHIFT;
-+
-+		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
-+			vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
-+						mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
-+		else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
-+			vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
-+		else
-+			vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+
-+		table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
-+		table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->UvdLevel[count].VclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for Vclk clock", return result);
-+
-+		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
-+
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+				table->UvdLevel[count].DclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((0 == result),
-+				"can not find divide id for Dclk clock", return result);
-+
-+		table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
-+	}
-+
-+	return result;
-+}
-+
-+static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	table->GraphicsBootLevel = 0;
-+	table->MemoryBootLevel = 0;
-+
-+	/* find boot level from dpm table */
-+	result = phm_find_boot_level(&(data->dpm_table.sclk_table),
-+			data->vbios_boot_state.sclk_bootup_value,
-+			(uint32_t *)&(table->GraphicsBootLevel));
-+
-+	result = phm_find_boot_level(&(data->dpm_table.mclk_table),
-+			data->vbios_boot_state.mclk_bootup_value,
-+			(uint32_t *)&(table->MemoryBootLevel));
-+
-+	table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
-+			VOLTAGE_SCALE;
-+	table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
-+			VOLTAGE_SCALE;
-+	table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
-+			VOLTAGE_SCALE;
-+
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint8_t count, level;
-+
-+	count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
-+
-+	for (level = 0; level < count; level++) {
-+		if (table_info->vdd_dep_on_sclk->entries[level].clk >=
-+				hw_data->vbios_boot_state.sclk_bootup_value) {
-+			smu_data->smc_state_table.GraphicsBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
-+	for (level = 0; level < count; level++) {
-+		if (table_info->vdd_dep_on_mclk->entries[level].clk >=
-+				hw_data->vbios_boot_state.mclk_bootup_value) {
-+			smu_data->smc_state_table.MemoryBootLevel = level;
-+			break;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+
-+	uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+
-+	stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
-+
-+	/* Read SMU_Eefuse to read and calculate RO and determine
-+	 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
-+	 */
-+	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixSMU_EFUSE_0 + (67 * 4));
-+	efuse &= 0xFF000000;
-+	efuse = efuse >> 24;
-+
-+	if (hwmgr->chip_id == CHIP_POLARIS10) {
-+		min = 1000;
-+		max = 2300;
-+	} else {
-+		min = 1100;
-+		max = 2100;
-+	}
-+
-+	ro = efuse * (max - min) / 255 + min;
-+
-+	/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
-+	for (i = 0; i < sclk_table->count; i++) {
-+		smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
-+				sclk_table->entries[i].cks_enable << i;
-+		if (hwmgr->chip_id == CHIP_POLARIS10) {
-+			volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \
-+						(2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
-+			volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
-+					(2522480 - sclk_table->entries[i].clk/100 * 115764/100));
-+		} else {
-+			volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \
-+						(2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
-+			volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
-+					(3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
-+		}
-+
-+		if (volt_without_cks >= volt_with_cks)
-+			volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
-+					sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
-+
-+		smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
-+	}
-+
-+	smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
-+	/* Populate CKS Lookup Table */
-+	if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
-+		stretch_amount2 = 0;
-+	else if (stretch_amount == 3 || stretch_amount == 4)
-+		stretch_amount2 = 1;
-+	else {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ClockStretcher);
-+		PP_ASSERT_WITH_CODE(false,
-+				"Stretch Amount in PPTable not supported\n",
-+				return -EINVAL);
-+	}
-+
-+	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
-+	value &= 0xFFFFFFFE;
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
-+
-+	return 0;
-+}
-+
-+static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
-+		struct SMU74_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	uint16_t config;
-+
-+	config = VR_MERGED_WITH_VDDC;
-+	table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
-+
-+	/* Set Vddc Voltage Controller */
-+	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+		config = VR_SVI2_PLANE_1;
-+		table->VRConfig |= config;
-+	} else {
-+		PP_ASSERT_WITH_CODE(false,
-+				"VDDC should be on SVI2 control in merged mode!",
-+				);
-+	}
-+	/* Set Vddci Voltage Controller */
-+	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
-+		config = VR_SVI2_PLANE_2;  /* only in merged mode */
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	} else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
-+		config = VR_SMIO_PATTERN_1;
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	} else {
-+		config = VR_STATIC_VOLTAGE;
-+		table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
-+	}
-+	/* Set Mvdd Voltage Controller */
-+	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
-+		config = VR_SVI2_PLANE_2;
-+		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
-+			offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
-+	} else {
-+		config = VR_STATIC_VOLTAGE;
-+		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+
-+	SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
-+	int result = 0;
-+	struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
-+	AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
-+	AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
-+	uint32_t tmp, i;
-+
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)hwmgr->pptable;
-+	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+
-+
-+	if (((struct smu7_smumgr *)smu_data)->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
-+		return result;
-+
-+	result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
-+
-+	if (0 == result) {
-+		table->BTCGB_VDROOP_TABLE[0].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
-+		table->BTCGB_VDROOP_TABLE[0].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
-+		table->BTCGB_VDROOP_TABLE[0].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
-+		table->BTCGB_VDROOP_TABLE[1].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
-+		table->BTCGB_VDROOP_TABLE[1].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
-+		table->BTCGB_VDROOP_TABLE[1].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
-+		table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
-+		table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
-+		table->AVFSGB_VDROOP_TABLE[0].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
-+		table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
-+		table->AVFSGB_VDROOP_TABLE[0].m2_shift  = 12;
-+		table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
-+		table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
-+		table->AVFSGB_VDROOP_TABLE[1].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
-+		table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
-+		table->AVFSGB_VDROOP_TABLE[1].m2_shift  = 12;
-+		table->MaxVoltage                = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
-+		AVFS_meanNsigma.Aconstant[0]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
-+		AVFS_meanNsigma.Aconstant[1]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
-+		AVFS_meanNsigma.Aconstant[2]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
-+		AVFS_meanNsigma.DC_tol_sigma      = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
-+		AVFS_meanNsigma.Platform_mean     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
-+		AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
-+		AVFS_meanNsigma.Platform_sigma     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
-+
-+		for (i = 0; i < NUM_VFT_COLUMNS; i++) {
-+			AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
-+			AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
-+		}
-+
-+		result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
-+				&tmp, SMC_RAM_END);
-+
-+		smu7_copy_bytes_to_smc(hwmgr,
-+					tmp,
-+					(uint8_t *)&AVFS_meanNsigma,
-+					sizeof(AVFS_meanNsigma_t),
-+					SMC_RAM_END);
-+
-+		result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
-+				&tmp, SMC_RAM_END);
-+		smu7_copy_bytes_to_smc(hwmgr,
-+					tmp,
-+					(uint8_t *)&AVFS_SclkOffset,
-+					sizeof(AVFS_Sclk_Offset_t),
-+					SMC_RAM_END);
-+
-+		data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
-+						(avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
-+						(avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
-+						(avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
-+		data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
-+	}
-+	return result;
-+}
-+
-+static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	uint32_t tmp;
-+	int result;
-+
-+	/* This is a read-modify-write on the first byte of the ARB table.
-+	 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
-+	 * is the field 'current'.
-+	 * This solution is ugly, but we never write the whole table only
-+	 * individual fields in it.
-+	 * In reality this field should not be in that structure
-+	 * but in a soft register.
-+	 */
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+			smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
-+
-+	if (result)
-+		return result;
-+
-+	tmp &= 0x00FFFFFF;
-+	tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
-+
-+	return smu7_write_smc_sram_dword(hwmgr,
-+			smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
-+}
-+
-+static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	struct  phm_ppt_v1_information *table_info =
-+			(struct  phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (table_info &&
-+			table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
-+			table_info->cac_dtp_table->usPowerTuneDataSetID)
-+		smu_data->power_tune_defaults =
-+				&polaris10_power_tune_data_set_array
-+				[table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
-+	else
-+		smu_data->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
-+
-+}
-+
-+static void polaris10_save_default_power_profile(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_smumgr *data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	struct SMU74_Discrete_GraphicsLevel *levels =
-+				data->smc_state_table.GraphicsLevel;
-+	unsigned min_level = 1;
-+
-+	hwmgr->default_gfx_power_profile.activity_threshold =
-+			be16_to_cpu(levels[0].ActivityLevel);
-+	hwmgr->default_gfx_power_profile.up_hyst = levels[0].UpHyst;
-+	hwmgr->default_gfx_power_profile.down_hyst = levels[0].DownHyst;
-+	hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
-+
-+	hwmgr->default_compute_power_profile = hwmgr->default_gfx_power_profile;
-+	hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
-+
-+	/* Workaround compute SDMA instability: disable lowest SCLK
-+	 * DPM level. Optimize compute power profile: Use only highest
-+	 * 2 power levels (if more than 2 are available), Hysteresis:
-+	 * 0ms up, 5ms down
-+	 */
-+	if (data->smc_state_table.GraphicsDpmLevelCount > 2)
-+		min_level = data->smc_state_table.GraphicsDpmLevelCount - 2;
-+	else if (data->smc_state_table.GraphicsDpmLevelCount == 2)
-+		min_level = 1;
-+	else
-+		min_level = 0;
-+	hwmgr->default_compute_power_profile.min_sclk =
-+		be32_to_cpu(levels[min_level].SclkSetting.SclkFrequency);
-+	hwmgr->default_compute_power_profile.up_hyst = 0;
-+	hwmgr->default_compute_power_profile.down_hyst = 5;
-+
-+	hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
-+	hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
-+}
-+
-+static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
-+	uint8_t i;
-+	struct pp_atomctrl_gpio_pin_assignment gpio_pin;
-+	pp_atomctrl_clock_dividers_vi dividers;
-+
-+	polaris10_initialize_power_tune_defaults(hwmgr);
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
-+		polaris10_populate_smc_voltage_tables(hwmgr, table);
-+
-+	table->SystemFlags = 0;
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StepVddc))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
-+
-+	if (hw_data->is_memory_gddr5)
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
-+
-+	if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
-+		result = polaris10_populate_ulv_state(hwmgr, table);
-+		PP_ASSERT_WITH_CODE(0 == result,
-+				"Failed to initialize ULV state!", return result);
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+				ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
-+	}
-+
-+	result = polaris10_populate_smc_link_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Link Level!", return result);
-+
-+	result = polaris10_populate_all_graphic_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Graphics Level!", return result);
-+
-+	result = polaris10_populate_all_memory_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Memory Level!", return result);
-+
-+	result = polaris10_populate_smc_acpi_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize ACPI Level!", return result);
-+
-+	result = polaris10_populate_smc_vce_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize VCE Level!", return result);
-+
-+	result = polaris10_populate_smc_samu_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize SAMU Level!", return result);
-+
-+	/* Since only the initial state is completely set up at this point
-+	 * (the other states are just copies of the boot state) we only
-+	 * need to populate the  ARB settings for the initial state.
-+	 */
-+	result = polaris10_program_memory_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to Write ARB settings for the initial state.", return result);
-+
-+	result = polaris10_populate_smc_uvd_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize UVD Level!", return result);
-+
-+	result = polaris10_populate_smc_boot_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Boot Level!", return result);
-+
-+	result = polaris10_populate_smc_initailial_state(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to initialize Boot State!", return result);
-+
-+	result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to populate BAPM Parameters!", return result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ClockStretcher)) {
-+		result = polaris10_populate_clock_stretcher_data_table(hwmgr);
-+		PP_ASSERT_WITH_CODE(0 == result,
-+				"Failed to populate Clock Stretcher Data Table!",
-+				return result);
-+	}
-+
-+	result = polaris10_populate_avfs_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
-+
-+	table->CurrSclkPllRange = 0xff;
-+	table->GraphicsVoltageChangeEnable  = 1;
-+	table->GraphicsThermThrottleEnable  = 1;
-+	table->GraphicsInterval = 1;
-+	table->VoltageInterval  = 1;
-+	table->ThermalInterval  = 1;
-+	table->TemperatureLimitHigh =
-+			table_info->cac_dtp_table->usTargetOperatingTemp *
-+			SMU7_Q88_FORMAT_CONVERSION_UNIT;
-+	table->TemperatureLimitLow  =
-+			(table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
-+			SMU7_Q88_FORMAT_CONVERSION_UNIT;
-+	table->MemoryVoltageChangeEnable = 1;
-+	table->MemoryInterval = 1;
-+	table->VoltageResponseTime = 0;
-+	table->PhaseResponseTime = 0;
-+	table->MemoryThermThrottleEnable = 1;
-+	table->PCIeBootLinkLevel = 0;
-+	table->PCIeGenInterval = 1;
-+	table->VRConfig = 0;
-+
-+	result = polaris10_populate_vr_config(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to populate VRConfig setting!", return result);
-+
-+	table->ThermGpio = 17;
-+	table->SclkStepSize = 0x4000;
-+
-+	if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
-+		table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+	} else {
-+		table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_RegulatorHot);
-+	}
-+
-+	if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
-+			&gpio_pin)) {
-+		table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_AutomaticDCTransition);
-+	} else {
-+		table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_AutomaticDCTransition);
-+	}
-+
-+	/* Thermal Output GPIO */
-+	if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
-+			&gpio_pin)) {
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ThermalOutGPIO);
-+
-+		table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
-+
-+		/* For porlarity read GPIOPAD_A with assigned Gpio pin
-+		 * since VBIOS will program this register to set 'inactive state',
-+		 * driver can then determine 'active state' from this and
-+		 * program SMU with correct polarity
-+		 */
-+		table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
-+					& (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
-+		table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
-+
-+		/* if required, combine VRHot/PCC with thermal out GPIO */
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
-+		&& phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
-+			table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
-+	} else {
-+		table->ThermOutGpio = 17;
-+		table->ThermOutPolarity = 1;
-+		table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
-+	}
-+
-+	/* Populate BIF_SCLK levels into SMC DPM table */
-+	for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], &dividers);
-+		PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
-+
-+		if (i == 0)
-+			table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
-+		else
-+			table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
-+	}
-+
-+	for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
-+		table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
-+
-+	/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
-+	result = smu7_copy_bytes_to_smc(hwmgr,
-+			smu_data->smu7_data.dpm_table_start +
-+			offsetof(SMU74_Discrete_DpmTable, SystemFlags),
-+			(uint8_t *)&(table->SystemFlags),
-+			sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
-+			SMC_RAM_END);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to upload dpm data to SMC memory!", return result);
-+
-+	result = polaris10_init_arb_table_index(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to upload arb data to SMC memory!", return result);
-+
-+	result = polaris10_populate_pm_fuses(hwmgr);
-+	PP_ASSERT_WITH_CODE(0 == result,
-+			"Failed to  populate PM fuses to SMC memory!", return result);
-+
-+	polaris10_save_default_power_profile(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	if (data->need_update_smu7_dpm_table &
-+		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
-+		return polaris10_program_memory_timing_parameters(hwmgr);
-+
-+	return 0;
-+}
-+
-+int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
-+{
-+	int ret;
-+	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
-+		return 0;
-+
-+	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
-+			PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting);
-+
-+	ret = (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs) == 0) ?
-+			0 : -1;
-+
-+	if (!ret)
-+		/* If this param is not changed, this function could fire unnecessarily */
-+		smu_data->avfs.avfs_btc_status = AVFS_BTC_COMPLETED_PREVIOUSLY;
-+
-+	return ret;
-+}
-+
-+static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
-+	uint32_t duty100;
-+	uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
-+	uint16_t fdo_min, slope1, slope2;
-+	uint32_t reference_clock;
-+	int res;
-+	uint64_t tmp64;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	if (smu_data->smu7_data.fan_table_start == 0) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
-+			CG_FDO_CTRL1, FMAX_DUTY100);
-+
-+	if (duty100 == 0) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
-+			usPWMMin * duty100;
-+	do_div(tmp64, 10000);
-+	fdo_min = (uint16_t)tmp64;
-+
-+	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
-+	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
-+
-+	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
-+	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
-+			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
-+
-+	slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
-+	slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
-+
-+	fan_table.TempMin = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMin) / 100);
-+	fan_table.TempMed = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMed) / 100);
-+	fan_table.TempMax = cpu_to_be16((50 + hwmgr->
-+			thermal_controller.advanceFanControlParameters.usTMax) / 100);
-+
-+	fan_table.Slope1 = cpu_to_be16(slope1);
-+	fan_table.Slope2 = cpu_to_be16(slope2);
-+
-+	fan_table.FdoMin = cpu_to_be16(fdo_min);
-+
-+	fan_table.HystDown = cpu_to_be16(hwmgr->
-+			thermal_controller.advanceFanControlParameters.ucTHyst);
-+
-+	fan_table.HystUp = cpu_to_be16(1);
-+
-+	fan_table.HystSlope = cpu_to_be16(1);
-+
-+	fan_table.TempRespLim = cpu_to_be16(5);
-+
-+	reference_clock = smu7_get_xclk(hwmgr);
-+
-+	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
-+			thermal_controller.advanceFanControlParameters.ulCycleDelay *
-+			reference_clock) / 1600);
-+
-+	fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
-+
-+	fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
-+			hwmgr->device, CGS_IND_REG__SMC,
-+			CG_MULT_THERMAL_CTRL, TEMP_SEL);
-+
-+	res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
-+			(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
-+			SMC_RAM_END);
-+
-+	if (!res && hwmgr->thermal_controller.
-+			advanceFanControlParameters.ucMinimumPWMLimit)
-+		res = smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_SetFanMinPwm,
-+				hwmgr->thermal_controller.
-+				advanceFanControlParameters.ucMinimumPWMLimit);
-+
-+	if (!res && hwmgr->thermal_controller.
-+			advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
-+		res = smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_SetFanSclkTarget,
-+				hwmgr->thermal_controller.
-+				advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
-+
-+	if (res)
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+
-+	return 0;
-+}
-+
-+static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	smu_data->smc_state_table.UvdBootLevel = 0;
-+	if (table_info->mm_dep_table->count > 0)
-+		smu_data->smc_state_table.UvdBootLevel =
-+				(uint8_t) (table_info->mm_dep_table->count - 1);
-+	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
-+						UvdBootLevel);
-+	mm_boot_level_offset /= 4;
-+	mm_boot_level_offset *= 4;
-+	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset);
-+	mm_boot_level_value &= 0x00FFFFFF;
-+	mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
-+	cgs_write_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_UVDDPM) ||
-+		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StablePState))
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_UVDDPM_SetEnabledMask,
-+				(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
-+	return 0;
-+}
-+
-+static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_StablePState))
-+		smu_data->smc_state_table.VceBootLevel =
-+			(uint8_t) (table_info->mm_dep_table->count - 1);
-+	else
-+		smu_data->smc_state_table.VceBootLevel = 0;
-+
-+	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
-+					offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
-+	mm_boot_level_offset /= 4;
-+	mm_boot_level_offset *= 4;
-+	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset);
-+	mm_boot_level_value &= 0xFF00FFFF;
-+	mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
-+	cgs_write_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_VCEDPM_SetEnabledMask,
-+				(uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
-+	return 0;
-+}
-+
-+static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+
-+
-+	smu_data->smc_state_table.SamuBootLevel = 0;
-+	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
-+				offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
-+
-+	mm_boot_level_offset /= 4;
-+	mm_boot_level_offset *= 4;
-+	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset);
-+	mm_boot_level_value &= 0xFFFFFF00;
-+	mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
-+	cgs_write_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StablePState))
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_SAMUDPM_SetEnabledMask,
-+				(uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
-+	return 0;
-+}
-+
-+
-+static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
-+	int max_entry, i;
-+
-+	max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
-+						SMU74_MAX_LEVELS_LINK :
-+						pcie_table->count;
-+	/* Setup BIF_SCLK levels */
-+	for (i = 0; i < max_entry; i++)
-+		smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
-+	return 0;
-+}
-+
-+static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
-+{
-+	switch (type) {
-+	case SMU_UVD_TABLE:
-+		polaris10_update_uvd_smc_table(hwmgr);
-+		break;
-+	case SMU_VCE_TABLE:
-+		polaris10_update_vce_smc_table(hwmgr);
-+		break;
-+	case SMU_SAMU_TABLE:
-+		polaris10_update_samu_smc_table(hwmgr);
-+		break;
-+	case SMU_BIF_TABLE:
-+		polaris10_update_bif_smc_table(hwmgr);
-+	default:
-+		break;
-+	}
-+	return 0;
-+}
-+
-+static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+
-+	int result = 0;
-+	uint32_t low_sclk_interrupt_threshold = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkThrottleLowNotification)
-+		&& (hwmgr->gfx_arbiter.sclk_threshold !=
-+				data->low_sclk_interrupt_threshold)) {
-+		data->low_sclk_interrupt_threshold =
-+				hwmgr->gfx_arbiter.sclk_threshold;
-+		low_sclk_interrupt_threshold =
-+				data->low_sclk_interrupt_threshold;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
-+
-+		result = smu7_copy_bytes_to_smc(
-+				hwmgr,
-+				smu_data->smu7_data.dpm_table_start +
-+				offsetof(SMU74_Discrete_DpmTable,
-+					LowSclkInterruptThreshold),
-+				(uint8_t *)&low_sclk_interrupt_threshold,
-+				sizeof(uint32_t),
-+				SMC_RAM_END);
-+	}
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			"Failed to update SCLK threshold!", return result);
-+
-+	result = polaris10_program_mem_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			"Failed to program memory timing parameters!",
-+			);
-+
-+	return result;
-+}
-+
-+static uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
-+{
-+	switch (type) {
-+	case SMU_SoftRegisters:
-+		switch (member) {
-+		case HandshakeDisables:
-+			return offsetof(SMU74_SoftRegisters, HandshakeDisables);
-+		case VoltageChangeTimeout:
-+			return offsetof(SMU74_SoftRegisters, VoltageChangeTimeout);
-+		case AverageGraphicsActivity:
-+			return offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
-+		case PreVBlankGap:
-+			return offsetof(SMU74_SoftRegisters, PreVBlankGap);
-+		case VBlankTimeout:
-+			return offsetof(SMU74_SoftRegisters, VBlankTimeout);
-+		case UcodeLoadStatus:
-+			return offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
-+		case DRAM_LOG_ADDR_H:
-+			return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H);
-+		case DRAM_LOG_ADDR_L:
-+			return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L);
-+		case DRAM_LOG_PHY_ADDR_H:
-+			return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
-+		case DRAM_LOG_PHY_ADDR_L:
-+			return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
-+		case DRAM_LOG_BUFF_SIZE:
-+			return offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE);
-+		}
-+	case SMU_Discrete_DpmTable:
-+		switch (member) {
-+		case UvdBootLevel:
-+			return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
-+		case VceBootLevel:
-+			return offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
-+		case SamuBootLevel:
-+			return offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
-+		case LowSclkInterruptThreshold:
-+			return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold);
-+		}
-+	}
-+	pr_warn("can't get the offset of type %x member %x\n", type, member);
-+	return 0;
-+}
-+
-+static uint32_t polaris10_get_mac_definition(uint32_t value)
-+{
-+	switch (value) {
-+	case SMU_MAX_LEVELS_GRAPHICS:
-+		return SMU74_MAX_LEVELS_GRAPHICS;
-+	case SMU_MAX_LEVELS_MEMORY:
-+		return SMU74_MAX_LEVELS_MEMORY;
-+	case SMU_MAX_LEVELS_LINK:
-+		return SMU74_MAX_LEVELS_LINK;
-+	case SMU_MAX_ENTRIES_SMIO:
-+		return SMU74_MAX_ENTRIES_SMIO;
-+	case SMU_MAX_LEVELS_VDDC:
-+		return SMU74_MAX_LEVELS_VDDC;
-+	case SMU_MAX_LEVELS_VDDGFX:
-+		return SMU74_MAX_LEVELS_VDDGFX;
-+	case SMU_MAX_LEVELS_VDDCI:
-+		return SMU74_MAX_LEVELS_VDDCI;
-+	case SMU_MAX_LEVELS_MVDD:
-+		return SMU74_MAX_LEVELS_MVDD;
-+	case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
-+		return SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
-+	}
-+
-+	pr_warn("can't get the mac of %x\n", value);
-+	return 0;
-+}
-+
-+static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t tmp;
-+	int result;
-+	bool error = false;
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, DpmTable),
-+			&tmp, SMC_RAM_END);
-+
-+	if (0 == result)
-+		smu_data->smu7_data.dpm_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, SoftRegisters),
-+			&tmp, SMC_RAM_END);
-+
-+	if (!result) {
-+		data->soft_regs_start = tmp;
-+		smu_data->smu7_data.soft_regs_start = tmp;
-+	}
-+
-+	error |= (0 != result);
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, mcRegisterTable),
-+			&tmp, SMC_RAM_END);
-+
-+	if (!result)
-+		smu_data->smu7_data.mc_reg_table_start = tmp;
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, FanTable),
-+			&tmp, SMC_RAM_END);
-+
-+	if (!result)
-+		smu_data->smu7_data.fan_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
-+			&tmp, SMC_RAM_END);
-+
-+	if (!result)
-+		smu_data->smu7_data.arb_table_start = tmp;
-+
-+	error |= (0 != result);
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+			SMU7_FIRMWARE_HEADER_LOCATION +
-+			offsetof(SMU74_Firmware_Header, Version),
-+			&tmp, SMC_RAM_END);
-+
-+	if (!result)
-+		hwmgr->microcode_version_info.SMC = tmp;
-+
-+	error |= (0 != result);
-+
-+	return error ? -1 : 0;
-+}
-+
-+static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
-+{
-+	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
-+			CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
-+			? true : false;
-+}
-+
-+static int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
-+		struct amd_pp_profile *request)
-+{
-+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
-+			(hwmgr->smu_backend);
-+	struct SMU74_Discrete_GraphicsLevel *levels =
-+			smu_data->smc_state_table.GraphicsLevel;
-+	uint32_t array = smu_data->smu7_data.dpm_table_start +
-+			offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
-+	uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
-+			SMU74_MAX_LEVELS_GRAPHICS;
-+	uint32_t i;
-+
-+	for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
-+		levels[i].ActivityLevel =
-+				cpu_to_be16(request->activity_threshold);
-+		levels[i].EnabledForActivity = 1;
-+		levels[i].UpHyst = request->up_hyst;
-+		levels[i].DownHyst = request->down_hyst;
-+	}
-+
-+	return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
-+				array_size, SMC_RAM_END);
-+}
-+
- const struct pp_smumgr_func polaris10_smu_funcs = {
- 	.smu_init = polaris10_smu_init,
- 	.smu_fini = smu7_smu_fini,
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c	2017-12-14 06:39:58.484903615 +0100
-@@ -48,20 +48,20 @@
- #define smnMP1_FIRMWARE_FLAGS       0x3010028
- 
- 
--bool rv_is_smc_ram_running(struct pp_smumgr *smumgr)
-+bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr)
- {
- 	uint32_t mp1_fw_flags, reg;
- 
- 	reg = soc15_get_register_offset(NBIF_HWID, 0,
- 			mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
- 
--	cgs_write_register(smumgr->device, reg,
-+	cgs_write_register(hwmgr->device, reg,
- 			(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
- 
- 	reg = soc15_get_register_offset(NBIF_HWID, 0,
- 			mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
- 
--	mp1_fw_flags = cgs_read_register(smumgr->device, reg);
-+	mp1_fw_flags = cgs_read_register(hwmgr->device, reg);
- 
- 	if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
- 		return true;
-@@ -69,97 +69,97 @@ bool rv_is_smc_ram_running(struct pp_smu
- 	return false;
- }
- 
--static uint32_t rv_wait_for_response(struct pp_smumgr *smumgr)
-+static uint32_t rv_wait_for_response(struct pp_hwmgr *hwmgr)
- {
- 	uint32_t reg;
- 
--	if (!rv_is_smc_ram_running(smumgr))
-+	if (!rv_is_smc_ram_running(hwmgr))
- 		return -EINVAL;
- 
- 	reg = soc15_get_register_offset(MP1_HWID, 0,
- 			mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
- 
--	smum_wait_for_register_unequal(smumgr, reg,
-+	phm_wait_for_register_unequal(hwmgr, reg,
- 			0, MP1_C2PMSG_90__CONTENT_MASK);
- 
--	return cgs_read_register(smumgr->device, reg);
-+	return cgs_read_register(hwmgr->device, reg);
- }
- 
--int rv_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr,
-+int rv_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
- 		uint16_t msg)
- {
- 	uint32_t reg;
- 
--	if (!rv_is_smc_ram_running(smumgr))
-+	if (!rv_is_smc_ram_running(hwmgr))
- 		return -EINVAL;
- 
- 	reg = soc15_get_register_offset(MP1_HWID, 0,
- 			mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
--	cgs_write_register(smumgr->device, reg, msg);
-+	cgs_write_register(hwmgr->device, reg, msg);
- 
- 	return 0;
- }
- 
--int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg)
-+int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg)
- {
- 	uint32_t reg;
- 
- 	reg = soc15_get_register_offset(MP1_HWID, 0,
- 			mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
- 
--	*arg = cgs_read_register(smumgr->device, reg);
-+	*arg = cgs_read_register(hwmgr->device, reg);
- 
- 	return 0;
- }
- 
--int rv_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
-+int rv_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
- {
- 	uint32_t reg;
- 
--	rv_wait_for_response(smumgr);
-+	rv_wait_for_response(hwmgr);
- 
- 	reg = soc15_get_register_offset(MP1_HWID, 0,
- 			mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
--	cgs_write_register(smumgr->device, reg, 0);
-+	cgs_write_register(hwmgr->device, reg, 0);
- 
--	rv_send_msg_to_smc_without_waiting(smumgr, msg);
-+	rv_send_msg_to_smc_without_waiting(hwmgr, msg);
- 
--	if (rv_wait_for_response(smumgr) == 0)
-+	if (rv_wait_for_response(hwmgr) == 0)
- 		printk("Failed to send Message %x.\n", msg);
- 
- 	return 0;
- }
- 
- 
--int rv_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
-+int rv_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
- 		uint16_t msg, uint32_t parameter)
- {
- 	uint32_t reg;
- 
--	rv_wait_for_response(smumgr);
-+	rv_wait_for_response(hwmgr);
- 
- 	reg = soc15_get_register_offset(MP1_HWID, 0,
- 			mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
--	cgs_write_register(smumgr->device, reg, 0);
-+	cgs_write_register(hwmgr->device, reg, 0);
- 
- 	reg = soc15_get_register_offset(MP1_HWID, 0,
- 			mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
--	cgs_write_register(smumgr->device, reg, parameter);
-+	cgs_write_register(hwmgr->device, reg, parameter);
- 
--	rv_send_msg_to_smc_without_waiting(smumgr, msg);
-+	rv_send_msg_to_smc_without_waiting(hwmgr, msg);
- 
- 
--	if (rv_wait_for_response(smumgr) == 0)
-+	if (rv_wait_for_response(hwmgr) == 0)
- 		printk("Failed to send Message %x.\n", msg);
- 
- 	return 0;
- }
- 
--int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
-+int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
- 		uint8_t *table, int16_t table_id)
- {
- 	struct rv_smumgr *priv =
--			(struct rv_smumgr *)(smumgr->backend);
-+			(struct rv_smumgr *)(hwmgr->smu_backend);
- 
- 	PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
- 			"Invalid SMU Table ID!", return -EINVAL;);
-@@ -167,16 +167,16 @@ int rv_copy_table_from_smc(struct pp_smu
- 			"Invalid SMU Table version!", return -EINVAL;);
- 	PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
- 			"Invalid SMU Table Length!", return -EINVAL;);
--	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
-+	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_SetDriverDramAddrHigh,
- 			priv->smu_tables.entry[table_id].table_addr_high) == 0,
- 			"[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;);
--	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
-+	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_SetDriverDramAddrLow,
- 			priv->smu_tables.entry[table_id].table_addr_low) == 0,
- 			"[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
- 			return -EINVAL;);
--	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
-+	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_TransferTableSmu2Dram,
- 			priv->smu_tables.entry[table_id].table_id) == 0,
- 			"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
-@@ -188,11 +188,11 @@ int rv_copy_table_from_smc(struct pp_smu
- 	return 0;
- }
- 
--int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
-+int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
- 		uint8_t *table, int16_t table_id)
- {
- 	struct rv_smumgr *priv =
--			(struct rv_smumgr *)(smumgr->backend);
-+			(struct rv_smumgr *)(hwmgr->smu_backend);
- 
- 	PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
- 			"Invalid SMU Table ID!", return -EINVAL;);
-@@ -204,17 +204,17 @@ int rv_copy_table_to_smc(struct pp_smumg
- 	memcpy(priv->smu_tables.entry[table_id].table, table,
- 			priv->smu_tables.entry[table_id].size);
- 
--	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
-+	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_SetDriverDramAddrHigh,
- 			priv->smu_tables.entry[table_id].table_addr_high) == 0,
- 			"[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
- 			return -EINVAL;);
--	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
-+	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_SetDriverDramAddrLow,
- 			priv->smu_tables.entry[table_id].table_addr_low) == 0,
- 			"[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
- 			return -EINVAL;);
--	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
-+	PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_TransferTableDram2Smu,
- 			priv->smu_tables.entry[table_id].table_id) == 0,
- 			"[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
-@@ -223,15 +223,15 @@ int rv_copy_table_to_smc(struct pp_smumg
- 	return 0;
- }
- 
--static int rv_verify_smc_interface(struct pp_smumgr *smumgr)
-+static int rv_verify_smc_interface(struct pp_hwmgr *hwmgr)
- {
- 	uint32_t smc_driver_if_version;
- 
--	PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr,
-+	PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
- 			PPSMC_MSG_GetDriverIfVersion),
- 			"Attempt to get SMC IF Version Number Failed!",
- 			return -EINVAL);
--	PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(smumgr,
-+	PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr,
- 			&smc_driver_if_version),
- 			"Attempt to read SMC IF Version Number Failed!",
- 			return -EINVAL);
-@@ -243,9 +243,9 @@ static int rv_verify_smc_interface(struc
- }
- 
- /* sdma is disabled by default in vbios, need to re-enable in driver */
--static int rv_smc_enable_sdma(struct pp_smumgr *smumgr)
-+static int rv_smc_enable_sdma(struct pp_hwmgr *hwmgr)
- {
--	PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr,
-+	PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
- 			PPSMC_MSG_PowerUpSdma),
- 			"Attempt to power up sdma Failed!",
- 			return -EINVAL);
-@@ -253,9 +253,9 @@ static int rv_smc_enable_sdma(struct pp_
- 	return 0;
- }
- 
--static int rv_smc_disable_sdma(struct pp_smumgr *smumgr)
-+static int rv_smc_disable_sdma(struct pp_hwmgr *hwmgr)
- {
--	PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr,
-+	PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(hwmgr,
- 			PPSMC_MSG_PowerDownSdma),
- 			"Attempt to power down sdma Failed!",
- 			return -EINVAL);
-@@ -264,9 +264,9 @@ static int rv_smc_disable_sdma(struct pp
- }
- 
- /* vcn is disabled by default in vbios, need to re-enable in driver */
--static int rv_smc_enable_vcn(struct pp_smumgr *smumgr)
-+static int rv_smc_enable_vcn(struct pp_hwmgr *hwmgr)
- {
--	PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr,
-+	PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_PowerUpVcn, 0),
- 			"Attempt to power up vcn Failed!",
- 			return -EINVAL);
-@@ -274,9 +274,9 @@ static int rv_smc_enable_vcn(struct pp_s
- 	return 0;
- }
- 
--static int rv_smc_disable_vcn(struct pp_smumgr *smumgr)
-+static int rv_smc_disable_vcn(struct pp_hwmgr *hwmgr)
- {
--	PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr,
-+	PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_PowerDownVcn, 0),
- 			"Attempt to power down vcn Failed!",
- 			return -EINVAL);
-@@ -284,38 +284,38 @@ static int rv_smc_disable_vcn(struct pp_
- 	return 0;
- }
- 
--static int rv_smu_fini(struct pp_smumgr *smumgr)
-+static int rv_smu_fini(struct pp_hwmgr *hwmgr)
- {
- 	struct rv_smumgr *priv =
--			(struct rv_smumgr *)(smumgr->backend);
-+			(struct rv_smumgr *)(hwmgr->smu_backend);
- 
- 	if (priv) {
--		rv_smc_disable_sdma(smumgr);
--		rv_smc_disable_vcn(smumgr);
--		cgs_free_gpu_mem(smumgr->device,
-+		rv_smc_disable_sdma(hwmgr);
-+		rv_smc_disable_vcn(hwmgr);
-+		cgs_free_gpu_mem(hwmgr->device,
- 				priv->smu_tables.entry[WMTABLE].handle);
--		cgs_free_gpu_mem(smumgr->device,
-+		cgs_free_gpu_mem(hwmgr->device,
- 				priv->smu_tables.entry[CLOCKTABLE].handle);
--		kfree(smumgr->backend);
--		smumgr->backend = NULL;
-+		kfree(hwmgr->smu_backend);
-+		hwmgr->smu_backend = NULL;
- 	}
- 
- 	return 0;
- }
- 
--static int rv_start_smu(struct pp_smumgr *smumgr)
-+static int rv_start_smu(struct pp_hwmgr *hwmgr)
- {
--	if (rv_verify_smc_interface(smumgr))
-+	if (rv_verify_smc_interface(hwmgr))
- 		return -EINVAL;
--	if (rv_smc_enable_sdma(smumgr))
-+	if (rv_smc_enable_sdma(hwmgr))
- 		return -EINVAL;
--	if (rv_smc_enable_vcn(smumgr))
-+	if (rv_smc_enable_vcn(hwmgr))
- 		return -EINVAL;
- 
- 	return 0;
- }
- 
--static int rv_smu_init(struct pp_smumgr *smumgr)
-+static int rv_smu_init(struct pp_hwmgr *hwmgr)
- {
- 	struct rv_smumgr *priv;
- 	uint64_t mc_addr;
-@@ -327,10 +327,10 @@ static int rv_smu_init(struct pp_smumgr
- 	if (!priv)
- 		return -ENOMEM;
- 
--	smumgr->backend = priv;
-+	hwmgr->smu_backend = priv;
- 
- 	/* allocate space for watermarks table */
--	smu_allocate_memory(smumgr->device,
-+	smu_allocate_memory(hwmgr->device,
- 			sizeof(Watermarks_t),
- 			CGS_GPU_MEM_TYPE__GART_CACHEABLE,
- 			PAGE_SIZE,
-@@ -340,8 +340,8 @@ static int rv_smu_init(struct pp_smumgr
- 
- 	PP_ASSERT_WITH_CODE(kaddr,
- 			"[rv_smu_init] Out of memory for wmtable.",
--			kfree(smumgr->backend);
--			smumgr->backend = NULL;
-+			kfree(hwmgr->smu_backend);
-+			hwmgr->smu_backend = NULL;
- 			return -EINVAL);
- 
- 	priv->smu_tables.entry[WMTABLE].version = 0x01;
-@@ -355,7 +355,7 @@ static int rv_smu_init(struct pp_smumgr
- 	priv->smu_tables.entry[WMTABLE].handle = handle;
- 
- 	/* allocate space for watermarks table */
--	smu_allocate_memory(smumgr->device,
-+	smu_allocate_memory(hwmgr->device,
- 			sizeof(DpmClocks_t),
- 			CGS_GPU_MEM_TYPE__GART_CACHEABLE,
- 			PAGE_SIZE,
-@@ -365,10 +365,10 @@ static int rv_smu_init(struct pp_smumgr
- 
- 	PP_ASSERT_WITH_CODE(kaddr,
- 			"[rv_smu_init] Out of memory for CLOCKTABLE.",
--			cgs_free_gpu_mem(smumgr->device,
-+			cgs_free_gpu_mem(hwmgr->device,
- 			(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
--			kfree(smumgr->backend);
--			smumgr->backend = NULL;
-+			kfree(hwmgr->smu_backend);
-+			hwmgr->smu_backend = NULL;
- 			return -EINVAL);
- 
- 	priv->smu_tables.entry[CLOCKTABLE].version = 0x01;
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h	2017-12-14 06:39:58.484903615 +0100
-@@ -51,11 +51,11 @@ struct rv_smumgr {
- 	struct smu_table_array            smu_tables;
- };
- 
--int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg);
--bool rv_is_smc_ram_running(struct pp_smumgr *smumgr);
--int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
-+int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
-+bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr);
-+int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
- 		uint8_t *table, int16_t table_id);
--int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
-+int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
- 		uint8_t *table, int16_t table_id);
- 
- 
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c	2017-12-14 06:39:58.484903615 +0100
-@@ -25,27 +25,28 @@
- #include "pp_debug.h"
- #include "smumgr.h"
- #include "smu_ucode_xfer_vi.h"
--#include "smu/smu_7_1_3_d.h"
--#include "smu/smu_7_1_3_sh_mask.h"
- #include "ppatomctrl.h"
- #include "cgs_common.h"
- #include "smu7_ppsmc.h"
- #include "smu7_smumgr.h"
-+#include "smu7_common.h"
-+
-+#include "polaris10_pwrvirus.h"
- 
- #define SMU7_SMC_SIZE 0x20000
- 
--static int smu7_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit)
-+static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit)
- {
- 	PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
- 	PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
- 
--	cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr);
--	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */
-+	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr);
-+	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */
- 	return 0;
- }
- 
- 
--int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
-+int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
- {
- 	uint32_t data;
- 	uint32_t addr;
-@@ -59,7 +60,7 @@ int smu7_copy_bytes_from_smc(struct pp_s
- 	addr = smc_start_address;
- 
- 	while (byte_count >= 4) {
--		smu7_read_smc_sram_dword(smumgr, addr, &data, limit);
-+		smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);
- 
- 		*dest = PP_SMC_TO_HOST_UL(data);
- 
-@@ -69,7 +70,7 @@ int smu7_copy_bytes_from_smc(struct pp_s
- 	}
- 
- 	if (byte_count) {
--		smu7_read_smc_sram_dword(smumgr, addr, &data, limit);
-+		smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);
- 		*pdata = PP_SMC_TO_HOST_UL(data);
- 	/* Cast dest into byte type in dest_byte.  This way, we don't overflow if the allocated memory is not 4-byte aligned. */
- 		dest_byte = (uint8_t *)dest;
-@@ -81,7 +82,7 @@ int smu7_copy_bytes_from_smc(struct pp_s
- }
- 
- 
--int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
-+int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
- 				const uint8_t *src, uint32_t byte_count, uint32_t limit)
- {
- 	int result;
-@@ -99,12 +100,12 @@ int smu7_copy_bytes_to_smc(struct pp_smu
- 	/* Bytes are written into the SMC addres space with the MSB first. */
- 		data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
- 
--		result = smu7_set_smc_sram_address(smumgr, addr, limit);
-+		result = smu7_set_smc_sram_address(hwmgr, addr, limit);
- 
- 		if (0 != result)
- 			return result;
- 
--		cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
-+		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
- 
- 		src += 4;
- 		byte_count -= 4;
-@@ -115,13 +116,13 @@ int smu7_copy_bytes_to_smc(struct pp_smu
- 
- 		data = 0;
- 
--		result = smu7_set_smc_sram_address(smumgr, addr, limit);
-+		result = smu7_set_smc_sram_address(hwmgr, addr, limit);
- 
- 		if (0 != result)
- 			return result;
- 
- 
--		original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
-+		original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
- 
- 		extra_shift = 8 * (4 - byte_count);
- 
-@@ -135,53 +136,53 @@ int smu7_copy_bytes_to_smc(struct pp_smu
- 
- 		data |= (original_data & ~((~0UL) << extra_shift));
- 
--		result = smu7_set_smc_sram_address(smumgr, addr, limit);
-+		result = smu7_set_smc_sram_address(hwmgr, addr, limit);
- 
- 		if (0 != result)
- 			return result;
- 
--		cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data);
-+		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
- 	}
- 
- 	return 0;
- }
- 
- 
--int smu7_program_jump_on_start(struct pp_smumgr *smumgr)
-+int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr)
- {
- 	static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
- 
--	smu7_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
-+	smu7_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);
- 
- 	return 0;
- }
- 
--bool smu7_is_smc_ram_running(struct pp_smumgr *smumgr)
-+bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr)
- {
--	return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
--	&& (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
-+	return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
-+	&& (0x20100 <= cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
- }
- 
--int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
-+int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
- {
- 	int ret;
- 
--	if (!smu7_is_smc_ram_running(smumgr))
-+	if (!smu7_is_smc_ram_running(hwmgr))
- 		return -EINVAL;
- 
- 
--	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
- 
--	ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
-+	ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
- 
- 	if (ret != 1)
- 		pr_info("\n failed to send pre message %x ret is %d \n",  msg, ret);
- 
--	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
-+	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
- 
--	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
- 
--	ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
-+	ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
- 
- 	if (ret != 1)
- 		pr_info("\n failed to send message %x ret is %d \n",  msg, ret);
-@@ -189,53 +190,53 @@ int smu7_send_msg_to_smc(struct pp_smumg
- 	return 0;
- }
- 
--int smu7_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg)
-+int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg)
- {
--	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
-+	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
- 
- 	return 0;
- }
- 
--int smu7_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
-+int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
- {
--	if (!smu7_is_smc_ram_running(smumgr)) {
-+	if (!smu7_is_smc_ram_running(hwmgr)) {
- 		return -EINVAL;
- 	}
- 
--	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
- 
--	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
-+	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
- 
--	return smu7_send_msg_to_smc(smumgr, msg);
-+	return smu7_send_msg_to_smc(hwmgr, msg);
- }
- 
--int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
-+int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
- {
--	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
-+	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
- 
--	return smu7_send_msg_to_smc_without_waiting(smumgr, msg);
-+	return smu7_send_msg_to_smc_without_waiting(hwmgr, msg);
- }
- 
--int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
-+int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr)
- {
--	cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
-+	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
- 
--	cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
-+	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
- 
--	SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
-+	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
- 
--	if (1 != SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP))
-+	if (1 != PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP))
- 		pr_info("Failed to send Message.\n");
- 
- 	return 0;
- }
- 
--int smu7_wait_for_smc_inactive(struct pp_smumgr *smumgr)
-+int smu7_wait_for_smc_inactive(struct pp_hwmgr *hwmgr)
- {
--	if (!smu7_is_smc_ram_running(smumgr))
-+	if (!smu7_is_smc_ram_running(hwmgr))
- 		return -EINVAL;
- 
--	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
-+	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0);
- 	return 0;
- }
- 
-@@ -289,29 +290,29 @@ enum cgs_ucode_id smu7_convert_fw_type_t
- }
- 
- 
--int smu7_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
-+int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
- {
- 	int result;
- 
--	result = smu7_set_smc_sram_address(smumgr, smc_addr, limit);
-+	result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
- 
- 	if (result)
- 		return result;
- 
--	*value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_11);
-+	*value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
- 	return 0;
- }
- 
--int smu7_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
-+int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
- {
- 	int result;
- 
--	result = smu7_set_smc_sram_address(smumgr, smc_addr, limit);
-+	result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
- 
- 	if (result)
- 		return result;
- 
--	cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, value);
-+	cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, value);
- 
- 	return 0;
- }
-@@ -354,14 +355,14 @@ static uint32_t smu7_get_mask_for_firmwa
- 	return result;
- }
- 
--static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr,
-+static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,
- 						uint32_t fw_type,
- 						struct SMU_Entry *entry)
- {
- 	int result = 0;
- 	struct cgs_firmware_info info = {0};
- 
--	result = cgs_get_firmware_info(smumgr->device,
-+	result = cgs_get_firmware_info(hwmgr->device,
- 				smu7_convert_fw_type_to_cgs(fw_type),
- 				&info);
- 
-@@ -374,7 +375,7 @@ static int smu7_populate_single_firmware
- 		entry->meta_data_addr_low = 0;
- 
- 		/* digest need be excluded out */
--		if (cgs_is_virtualization_enabled(smumgr->device))
-+		if (cgs_is_virtualization_enabled(hwmgr->device))
- 			info.image_size -= 20;
- 		entry->data_size_byte = info.image_size;
- 		entry->num_register_entries = 0;
-@@ -389,30 +390,30 @@ static int smu7_populate_single_firmware
- 	return 0;
- }
- 
--int smu7_request_smu_load_fw(struct pp_smumgr *smumgr)
-+int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
- {
--	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
-+	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
- 	uint32_t fw_to_load;
- 	int result = 0;
- 	struct SMU_DRAMData_TOC *toc;
- 
--	if (!smumgr->reload_fw) {
-+	if (!hwmgr->reload_fw) {
- 		pr_info("skip reloading...\n");
- 		return 0;
- 	}
- 
- 	if (smu_data->soft_regs_start)
--		cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
--					smu_data->soft_regs_start + smum_get_offsetof(smumgr,
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
- 					SMU_SoftRegisters, UcodeLoadStatus),
- 					0x0);
- 
--	if (smumgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
--		if (!cgs_is_virtualization_enabled(smumgr->device)) {
--			smu7_send_msg_to_smc_with_parameter(smumgr,
-+	if (hwmgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
-+		if (!cgs_is_virtualization_enabled(hwmgr->device)) {
-+			smu7_send_msg_to_smc_with_parameter(hwmgr,
- 						PPSMC_MSG_SMU_DRAM_ADDR_HI,
- 						smu_data->smu_buffer.mc_addr_high);
--			smu7_send_msg_to_smc_with_parameter(smumgr,
-+			smu7_send_msg_to_smc_with_parameter(hwmgr,
- 						PPSMC_MSG_SMU_DRAM_ADDR_LO,
- 						smu_data->smu_buffer.mc_addr_low);
- 		}
-@@ -439,122 +440,162 @@ int smu7_request_smu_load_fw(struct pp_s
- 	toc->num_entries = 0;
- 	toc->structure_version = 1;
- 
--	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
-+	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
- 				UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]),
- 				"Failed to Get Firmware Entry.", return -EINVAL);
--	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
-+	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
- 				UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]),
- 				"Failed to Get Firmware Entry.", return -EINVAL);
--	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
-+	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
- 				UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]),
- 				"Failed to Get Firmware Entry.", return -EINVAL);
--	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
-+	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
- 				UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]),
- 				"Failed to Get Firmware Entry.", return -EINVAL);
--	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
-+	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
- 				UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]),
- 				"Failed to Get Firmware Entry.", return -EINVAL);
--	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
-+	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
- 				UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]),
- 				"Failed to Get Firmware Entry.", return -EINVAL);
--	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
-+	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
- 				UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]),
- 				"Failed to Get Firmware Entry.", return -EINVAL);
--	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
-+	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
- 				UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]),
- 				"Failed to Get Firmware Entry.", return -EINVAL);
--	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
-+	PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
- 				UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
- 				"Failed to Get Firmware Entry.", return -EINVAL);
--	if (cgs_is_virtualization_enabled(smumgr->device))
--		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(smumgr,
-+	if (cgs_is_virtualization_enabled(hwmgr->device))
-+		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
- 				UCODE_ID_MEC_STORAGE, &toc->entry[toc->num_entries++]),
- 				"Failed to Get Firmware Entry.", return -EINVAL);
- 
--	smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
--	smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
-+	smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high);
-+	smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low);
- 
--	if (smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load))
-+	if (smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load))
- 		pr_err("Fail to Request SMU Load uCode");
- 
- 	return result;
- }
- 
- /* Check if the FW has been loaded, SMU will not return if loading has not finished. */
--int smu7_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type)
-+int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type)
- {
--	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
-+	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
- 	uint32_t fw_mask = smu7_get_mask_for_firmware_type(fw_type);
- 	uint32_t ret;
- 
--	ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11,
--					smu_data->soft_regs_start + smum_get_offsetof(smumgr,
-+	ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,
-+					smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
- 					SMU_SoftRegisters, UcodeLoadStatus),
- 					fw_mask, fw_mask);
--
- 	return ret;
- }
- 
--int smu7_reload_firmware(struct pp_smumgr *smumgr)
-+int smu7_reload_firmware(struct pp_hwmgr *hwmgr)
- {
--	return smumgr->smumgr_funcs->start_smu(smumgr);
-+	return hwmgr->smumgr_funcs->start_smu(hwmgr);
- }
- 
--static int smu7_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit)
-+static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit)
- {
- 	uint32_t byte_count = length;
- 
- 	PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
- 
--	cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, 0x20000);
--	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
-+	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, 0x20000);
-+	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
- 
- 	for (; byte_count >= 4; byte_count -= 4)
--		cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, *src++);
-+		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, *src++);
- 
--	SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
-+	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
- 
--	PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL);
-+	PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL);
- 
- 	return 0;
- }
- 
- 
--int smu7_upload_smu_firmware_image(struct pp_smumgr *smumgr)
-+int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr)
- {
- 	int result = 0;
--	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
-+	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
- 
- 	struct cgs_firmware_info info = {0};
- 
- 	if (smu_data->security_hard_key == 1)
--		cgs_get_firmware_info(smumgr->device,
-+		cgs_get_firmware_info(hwmgr->device,
- 			smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
- 	else
--		cgs_get_firmware_info(smumgr->device,
-+		cgs_get_firmware_info(hwmgr->device,
- 			smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
- 
--	smumgr->is_kicker = info.is_kicker;
-+	hwmgr->is_kicker = info.is_kicker;
- 
--	result = smu7_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
-+	result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
- 
- 	return result;
- }
- 
--int smu7_init(struct pp_smumgr *smumgr)
-+static void execute_pwr_table(struct pp_hwmgr *hwmgr, const PWR_Command_Table *pvirus, int size)
-+{
-+	int i;
-+	uint32_t reg, data;
-+
-+	for (i = 0; i < size; i++) {
-+		reg  = pvirus->reg;
-+		data = pvirus->data;
-+		if (reg != 0xffffffff)
-+			cgs_write_register(hwmgr->device, reg, data);
-+		else
-+			break;
-+		pvirus++;
-+	}
-+}
-+
-+static void execute_pwr_dfy_table(struct pp_hwmgr *hwmgr, const PWR_DFY_Section *section)
-+{
-+	int i;
-+
-+	cgs_write_register(hwmgr->device, mmCP_DFY_CNTL, section->dfy_cntl);
-+	cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_HI, section->dfy_addr_hi);
-+	cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_LO, section->dfy_addr_lo);
-+	for (i = 0; i < section->dfy_size; i++)
-+		cgs_write_register(hwmgr->device, mmCP_DFY_DATA_0, section->dfy_data[i]);
-+}
-+
-+int smu7_setup_pwr_virus(struct pp_hwmgr *hwmgr)
-+{
-+	execute_pwr_table(hwmgr, pwr_virus_table_pre, ARRAY_SIZE(pwr_virus_table_pre));
-+	execute_pwr_dfy_table(hwmgr, &pwr_virus_section1);
-+	execute_pwr_dfy_table(hwmgr, &pwr_virus_section2);
-+	execute_pwr_dfy_table(hwmgr, &pwr_virus_section3);
-+	execute_pwr_dfy_table(hwmgr, &pwr_virus_section4);
-+	execute_pwr_dfy_table(hwmgr, &pwr_virus_section5);
-+	execute_pwr_dfy_table(hwmgr, &pwr_virus_section6);
-+	execute_pwr_table(hwmgr, pwr_virus_table_post, ARRAY_SIZE(pwr_virus_table_post));
-+
-+	return 0;
-+}
-+
-+int smu7_init(struct pp_hwmgr *hwmgr)
- {
- 	struct smu7_smumgr *smu_data;
- 	uint8_t *internal_buf;
- 	uint64_t mc_addr = 0;
- 
- 	/* Allocate memory for backend private data */
--	smu_data = (struct smu7_smumgr *)(smumgr->backend);
-+	smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
- 	smu_data->header_buffer.data_size =
- 			((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
- 
- /* Allocate FW image data structure and header buffer and
-  * send the header buffer address to SMU */
--	smu_allocate_memory(smumgr->device,
-+	smu_allocate_memory(hwmgr->device,
- 		smu_data->header_buffer.data_size,
- 		CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
- 		PAGE_SIZE,
-@@ -568,16 +609,16 @@ int smu7_init(struct pp_smumgr *smumgr)
- 
- 	PP_ASSERT_WITH_CODE((NULL != smu_data->header),
- 		"Out of memory.",
--		kfree(smumgr->backend);
--		cgs_free_gpu_mem(smumgr->device,
-+		kfree(hwmgr->smu_backend);
-+		cgs_free_gpu_mem(hwmgr->device,
- 		(cgs_handle_t)smu_data->header_buffer.handle);
- 		return -EINVAL);
- 
--	if (cgs_is_virtualization_enabled(smumgr->device))
-+	if (cgs_is_virtualization_enabled(hwmgr->device))
- 		return 0;
- 
- 	smu_data->smu_buffer.data_size = 200*4096;
--	smu_allocate_memory(smumgr->device,
-+	smu_allocate_memory(hwmgr->device,
- 		smu_data->smu_buffer.data_size,
- 		CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
- 		PAGE_SIZE,
-@@ -591,12 +632,12 @@ int smu7_init(struct pp_smumgr *smumgr)
- 
- 	PP_ASSERT_WITH_CODE((NULL != internal_buf),
- 		"Out of memory.",
--		kfree(smumgr->backend);
--		cgs_free_gpu_mem(smumgr->device,
-+		kfree(hwmgr->smu_backend);
-+		cgs_free_gpu_mem(hwmgr->device,
- 		(cgs_handle_t)smu_data->smu_buffer.handle);
- 		return -EINVAL);
- 
--	if (smum_is_hw_avfs_present(smumgr))
-+	if (smum_is_hw_avfs_present(hwmgr))
- 		smu_data->avfs.avfs_btc_status = AVFS_BTC_BOOT;
- 	else
- 		smu_data->avfs.avfs_btc_status = AVFS_BTC_NOTSUPPORTED;
-@@ -605,12 +646,10 @@ int smu7_init(struct pp_smumgr *smumgr)
- }
- 
- 
--int smu7_smu_fini(struct pp_smumgr *smumgr)
-+int smu7_smu_fini(struct pp_hwmgr *hwmgr)
- {
--	if (smumgr->backend) {
--		kfree(smumgr->backend);
--		smumgr->backend = NULL;
--	}
--	cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
-+	kfree(hwmgr->smu_backend);
-+	hwmgr->smu_backend = NULL;
-+	cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
- 	return 0;
- }
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h	2017-12-14 06:39:58.484903615 +0100
-@@ -60,32 +60,34 @@ struct smu7_smumgr {
- };
- 
- 
--int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
-+int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
- 				uint32_t *dest, uint32_t byte_count, uint32_t limit);
--int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
-+int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
- 			const uint8_t *src, uint32_t byte_count, uint32_t limit);
--int smu7_program_jump_on_start(struct pp_smumgr *smumgr);
--bool smu7_is_smc_ram_running(struct pp_smumgr *smumgr);
--int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg);
--int smu7_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg);
--int smu7_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg,
-+int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr);
-+bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr);
-+int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
-+int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg);
-+int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg,
- 						uint32_t parameter);
--int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr,
-+int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr,
- 						uint16_t msg, uint32_t parameter);
--int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr);
--int smu7_wait_for_smc_inactive(struct pp_smumgr *smumgr);
-+int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr);
-+int smu7_wait_for_smc_inactive(struct pp_hwmgr *hwmgr);
- 
- enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type);
--int smu7_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
-+int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
- 						uint32_t *value, uint32_t limit);
--int smu7_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
-+int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
- 						uint32_t value, uint32_t limit);
- 
--int smu7_request_smu_load_fw(struct pp_smumgr *smumgr);
--int smu7_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type);
--int smu7_reload_firmware(struct pp_smumgr *smumgr);
--int smu7_upload_smu_firmware_image(struct pp_smumgr *smumgr);
--int smu7_init(struct pp_smumgr *smumgr);
--int smu7_smu_fini(struct pp_smumgr *smumgr);
-+int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
-+int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type);
-+int smu7_reload_firmware(struct pp_hwmgr *hwmgr);
-+int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr);
-+int smu7_init(struct pp_hwmgr *hwmgr);
-+int smu7_smu_fini(struct pp_hwmgr *hwmgr);
- 
--#endif
-\ No newline at end of file
-+int smu7_setup_pwr_virus(struct pp_hwmgr *hwmgr);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c	2017-12-14 06:39:58.484903615 +0100
-@@ -27,7 +27,6 @@
- #include <linux/slab.h>
- #include <linux/types.h>
- #include <drm/amdgpu_drm.h>
--#include "pp_instance.h"
- #include "smumgr.h"
- #include "cgs_common.h"
- 
-@@ -46,88 +45,18 @@ MODULE_FIRMWARE("amdgpu/polaris12_smc.bi
- MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
- MODULE_FIRMWARE("amdgpu/vega10_acg_smc.bin");
- 
--int smum_early_init(struct pp_instance *handle)
-+int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
- {
--	struct pp_smumgr *smumgr;
--
--	if (handle == NULL)
--		return -EINVAL;
--
--	smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL);
--	if (smumgr == NULL)
--		return -ENOMEM;
--
--	smumgr->device = handle->device;
--	smumgr->chip_family = handle->chip_family;
--	smumgr->chip_id = handle->chip_id;
--	smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
--	smumgr->reload_fw = 1;
--	handle->smu_mgr = smumgr;
--
--	switch (smumgr->chip_family) {
--	case AMDGPU_FAMILY_CZ:
--		smumgr->smumgr_funcs = &cz_smu_funcs;
--		break;
--	case AMDGPU_FAMILY_VI:
--		switch (smumgr->chip_id) {
--		case CHIP_TOPAZ:
--			smumgr->smumgr_funcs = &iceland_smu_funcs;
--			break;
--		case CHIP_TONGA:
--			smumgr->smumgr_funcs = &tonga_smu_funcs;
--			break;
--		case CHIP_FIJI:
--			smumgr->smumgr_funcs = &fiji_smu_funcs;
--			break;
--		case CHIP_POLARIS11:
--		case CHIP_POLARIS10:
--		case CHIP_POLARIS12:
--			smumgr->smumgr_funcs = &polaris10_smu_funcs;
--			break;
--		default:
--			return -EINVAL;
--		}
--		break;
--	case AMDGPU_FAMILY_AI:
--		switch (smumgr->chip_id) {
--		case CHIP_VEGA10:
--			smumgr->smumgr_funcs = &vega10_smu_funcs;
--			break;
--		default:
--			return -EINVAL;
--		}
--		break;
--	case AMDGPU_FAMILY_RV:
--		switch (smumgr->chip_id) {
--		case CHIP_RAVEN:
--			smumgr->smumgr_funcs = &rv_smu_funcs;
--			break;
--		default:
--			return -EINVAL;
--		}
--		break;
--	default:
--		kfree(smumgr);
--		return -EINVAL;
--	}
-+	if (NULL != hwmgr->smumgr_funcs->thermal_avfs_enable)
-+		return hwmgr->smumgr_funcs->thermal_avfs_enable(hwmgr);
- 
- 	return 0;
- }
- 
--int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
-+int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
- {
--	if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable)
--		return hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable(hwmgr);
--
--	return 0;
--}
--
--int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
--		void *input, void *output, void *storage, int result)
--{
--	if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table)
--		return hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table(hwmgr);
-+	if (NULL != hwmgr->smumgr_funcs->thermal_setup_fan_table)
-+		return hwmgr->smumgr_funcs->thermal_setup_fan_table(hwmgr);
- 
- 	return 0;
- }
-@@ -135,8 +64,8 @@ int smum_thermal_setup_fan_table(struct
- int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr)
- {
- 
--	if (NULL != hwmgr->smumgr->smumgr_funcs->update_sclk_threshold)
--		return hwmgr->smumgr->smumgr_funcs->update_sclk_threshold(hwmgr);
-+	if (NULL != hwmgr->smumgr_funcs->update_sclk_threshold)
-+		return hwmgr->smumgr_funcs->update_sclk_threshold(hwmgr);
- 
- 	return 0;
- }
-@@ -144,163 +73,75 @@ int smum_update_sclk_threshold(struct pp
- int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
- {
- 
--	if (NULL != hwmgr->smumgr->smumgr_funcs->update_smc_table)
--		return hwmgr->smumgr->smumgr_funcs->update_smc_table(hwmgr, type);
-+	if (NULL != hwmgr->smumgr_funcs->update_smc_table)
-+		return hwmgr->smumgr_funcs->update_smc_table(hwmgr, type);
- 
- 	return 0;
- }
- 
--uint32_t smum_get_offsetof(struct pp_smumgr *smumgr, uint32_t type, uint32_t member)
-+uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t type, uint32_t member)
- {
--	if (NULL != smumgr->smumgr_funcs->get_offsetof)
--		return smumgr->smumgr_funcs->get_offsetof(type, member);
-+	if (NULL != hwmgr->smumgr_funcs->get_offsetof)
-+		return hwmgr->smumgr_funcs->get_offsetof(type, member);
- 
- 	return 0;
- }
- 
- int smum_process_firmware_header(struct pp_hwmgr *hwmgr)
- {
--	if (NULL != hwmgr->smumgr->smumgr_funcs->process_firmware_header)
--		return hwmgr->smumgr->smumgr_funcs->process_firmware_header(hwmgr);
-+	if (NULL != hwmgr->smumgr_funcs->process_firmware_header)
-+		return hwmgr->smumgr_funcs->process_firmware_header(hwmgr);
- 	return 0;
- }
- 
--int smum_get_argument(struct pp_smumgr *smumgr)
-+int smum_get_argument(struct pp_hwmgr *hwmgr)
- {
--	if (NULL != smumgr->smumgr_funcs->get_argument)
--		return smumgr->smumgr_funcs->get_argument(smumgr);
-+	if (NULL != hwmgr->smumgr_funcs->get_argument)
-+		return hwmgr->smumgr_funcs->get_argument(hwmgr);
- 
- 	return 0;
- }
- 
--uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value)
-+uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value)
- {
--	if (NULL != smumgr->smumgr_funcs->get_mac_definition)
--		return smumgr->smumgr_funcs->get_mac_definition(value);
-+	if (NULL != hwmgr->smumgr_funcs->get_mac_definition)
-+		return hwmgr->smumgr_funcs->get_mac_definition(value);
- 
- 	return 0;
- }
- 
--int smum_download_powerplay_table(struct pp_smumgr *smumgr,
--								void **table)
-+int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table)
- {
--	if (NULL != smumgr->smumgr_funcs->download_pptable_settings)
--		return smumgr->smumgr_funcs->download_pptable_settings(smumgr,
-+	if (NULL != hwmgr->smumgr_funcs->download_pptable_settings)
-+		return hwmgr->smumgr_funcs->download_pptable_settings(hwmgr,
- 									table);
- 	return 0;
- }
- 
--int smum_upload_powerplay_table(struct pp_smumgr *smumgr)
-+int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr)
- {
--	if (NULL != smumgr->smumgr_funcs->upload_pptable_settings)
--		return smumgr->smumgr_funcs->upload_pptable_settings(smumgr);
-+	if (NULL != hwmgr->smumgr_funcs->upload_pptable_settings)
-+		return hwmgr->smumgr_funcs->upload_pptable_settings(hwmgr);
- 
- 	return 0;
- }
- 
--int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
-+int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
- {
--	if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL)
-+	if (hwmgr == NULL || hwmgr->smumgr_funcs->send_msg_to_smc == NULL)
- 		return -EINVAL;
- 
--	return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg);
-+	return hwmgr->smumgr_funcs->send_msg_to_smc(hwmgr, msg);
- }
- 
--int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
-+int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
- 					uint16_t msg, uint32_t parameter)
- {
--	if (smumgr == NULL ||
--		smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
--		return -EINVAL;
--	return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter(
--						smumgr, msg, parameter);
--}
--
--/*
-- * Returns once the part of the register indicated by the mask has
-- * reached the given value.
-- */
--int smum_wait_on_register(struct pp_smumgr *smumgr,
--				uint32_t index,
--				uint32_t value, uint32_t mask)
--{
--	uint32_t i;
--	uint32_t cur_value;
--
--	if (smumgr == NULL || smumgr->device == NULL)
--		return -EINVAL;
--
--	for (i = 0; i < smumgr->usec_timeout; i++) {
--		cur_value = cgs_read_register(smumgr->device, index);
--		if ((cur_value & mask) == (value & mask))
--			break;
--		udelay(1);
--	}
--
--	/* timeout means wrong logic*/
--	if (i == smumgr->usec_timeout)
--		return -1;
--
--	return 0;
--}
--
--int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
--					uint32_t index,
--					uint32_t value, uint32_t mask)
--{
--	uint32_t i;
--	uint32_t cur_value;
--
--	if (smumgr == NULL)
-+	if (hwmgr == NULL ||
-+		hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
- 		return -EINVAL;
--
--	for (i = 0; i < smumgr->usec_timeout; i++) {
--		cur_value = cgs_read_register(smumgr->device,
--									index);
--		if ((cur_value & mask) != (value & mask))
--			break;
--		udelay(1);
--	}
--
--	/* timeout means wrong logic */
--	if (i == smumgr->usec_timeout)
--		return -1;
--
--	return 0;
--}
--
--
--/*
-- * Returns once the part of the register indicated by the mask
-- * has reached the given value.The indirect space is described by
-- * giving the memory-mapped index of the indirect index register.
-- */
--int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
--					uint32_t indirect_port,
--					uint32_t index,
--					uint32_t value,
--					uint32_t mask)
--{
--	if (smumgr == NULL || smumgr->device == NULL)
--		return -EINVAL;
--
--	cgs_write_register(smumgr->device, indirect_port, index);
--	return smum_wait_on_register(smumgr, indirect_port + 1,
--						mask, value);
--}
--
--void smum_wait_for_indirect_register_unequal(
--						struct pp_smumgr *smumgr,
--						uint32_t indirect_port,
--						uint32_t index,
--						uint32_t value,
--						uint32_t mask)
--{
--	if (smumgr == NULL || smumgr->device == NULL)
--		return;
--	cgs_write_register(smumgr->device, indirect_port, index);
--	smum_wait_for_register_unequal(smumgr, indirect_port + 1,
--						value, mask);
-+	return hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter(
-+						hwmgr, msg, parameter);
- }
- 
- int smu_allocate_memory(void *device, uint32_t size,
-@@ -316,7 +157,7 @@ int smu_allocate_memory(void *device, ui
- 		return -EINVAL;
- 
- 	ret = cgs_alloc_gpu_mem(device, type, size, byte_align,
--				0, 0, (cgs_handle_t *)handle);
-+				(cgs_handle_t *)handle);
- 	if (ret)
- 		return -ENOMEM;
- 
-@@ -356,24 +197,24 @@ int smu_free_memory(void *device, void *
- 
- int smum_init_smc_table(struct pp_hwmgr *hwmgr)
- {
--	if (NULL != hwmgr->smumgr->smumgr_funcs->init_smc_table)
--		return hwmgr->smumgr->smumgr_funcs->init_smc_table(hwmgr);
-+	if (NULL != hwmgr->smumgr_funcs->init_smc_table)
-+		return hwmgr->smumgr_funcs->init_smc_table(hwmgr);
- 
- 	return 0;
- }
- 
- int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
- {
--	if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels)
--		return hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels(hwmgr);
-+	if (NULL != hwmgr->smumgr_funcs->populate_all_graphic_levels)
-+		return hwmgr->smumgr_funcs->populate_all_graphic_levels(hwmgr);
- 
- 	return 0;
- }
- 
- int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
- {
--	if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels)
--		return hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels(hwmgr);
-+	if (NULL != hwmgr->smumgr_funcs->populate_all_memory_levels)
-+		return hwmgr->smumgr_funcs->populate_all_memory_levels(hwmgr);
- 
- 	return 0;
- }
-@@ -381,16 +222,16 @@ int smum_populate_all_memory_levels(stru
- /*this interface is needed by island ci/vi */
- int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
- {
--	if (NULL != hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table)
--		return hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table(hwmgr);
-+	if (NULL != hwmgr->smumgr_funcs->initialize_mc_reg_table)
-+		return hwmgr->smumgr_funcs->initialize_mc_reg_table(hwmgr);
- 
- 	return 0;
- }
- 
- bool smum_is_dpm_running(struct pp_hwmgr *hwmgr)
- {
--	if (NULL != hwmgr->smumgr->smumgr_funcs->is_dpm_running)
--		return hwmgr->smumgr->smumgr_funcs->is_dpm_running(hwmgr);
-+	if (NULL != hwmgr->smumgr_funcs->is_dpm_running)
-+		return hwmgr->smumgr_funcs->is_dpm_running(hwmgr);
- 
- 	return true;
- }
-@@ -398,17 +239,17 @@ bool smum_is_dpm_running(struct pp_hwmgr
- int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
- 		struct amd_pp_profile *request)
- {
--	if (hwmgr->smumgr->smumgr_funcs->populate_requested_graphic_levels)
--		return hwmgr->smumgr->smumgr_funcs->populate_requested_graphic_levels(
-+	if (hwmgr->smumgr_funcs->populate_requested_graphic_levels)
-+		return hwmgr->smumgr_funcs->populate_requested_graphic_levels(
- 				hwmgr, request);
- 
- 	return 0;
- }
- 
--bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr)
-+bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
- {
--	if (smumgr->smumgr_funcs->is_hw_avfs_present)
--		return smumgr->smumgr_funcs->is_hw_avfs_present(smumgr);
-+	if (hwmgr->smumgr_funcs->is_hw_avfs_present)
-+		return hwmgr->smumgr_funcs->is_hw_avfs_present(hwmgr);
- 
- 	return false;
- }
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c	2017-12-14 06:39:58.485903616 +0100
-@@ -33,141 +33,193 @@
- #include "smu/smu_7_1_2_d.h"
- #include "smu/smu_7_1_2_sh_mask.h"
- #include "cgs_common.h"
--#include "tonga_smc.h"
- #include "smu7_smumgr.h"
- 
-+#include "smu7_dyn_defaults.h"
- 
--static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr)
-+#include "smu7_hwmgr.h"
-+#include "hardwaremanager.h"
-+#include "ppatomctrl.h"
-+
-+#include "atombios.h"
-+
-+#include "pppcielanes.h"
-+#include "pp_endian.h"
-+
-+#include "gmc/gmc_8_1_d.h"
-+#include "gmc/gmc_8_1_sh_mask.h"
-+
-+#include "bif/bif_5_0_d.h"
-+#include "bif/bif_5_0_sh_mask.h"
-+
-+#include "dce/dce_10_0_d.h"
-+#include "dce/dce_10_0_sh_mask.h"
-+
-+
-+#define VOLTAGE_SCALE 4
-+#define POWERTUNE_DEFAULT_SET_MAX    1
-+#define VOLTAGE_VID_OFFSET_SCALE1   625
-+#define VOLTAGE_VID_OFFSET_SCALE2   100
-+#define MC_CG_ARB_FREQ_F1           0x0b
-+#define VDDC_VDDCI_DELTA            200
-+
-+
-+static const struct tonga_pt_defaults tonga_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
-+/* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc,  TDC_MAWt,
-+ * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,        BAPM_TEMP_GRADIENT
-+ */
-+	{1,               0xF,             0xFD,                0x19,
-+	 5,               45,                 0,              0xB0000,
-+	 {0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8,
-+		0xC9, 0xC9, 0x2F, 0x4D, 0x61},
-+	 {0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203,
-+		0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4}
-+	},
-+};
-+
-+/* [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
-+static const uint16_t tonga_clock_stretcher_lookup_table[2][4] = {
-+	{600, 1050, 3, 0},
-+	{600, 1050, 6, 1}
-+};
-+
-+/* [FF, SS] type, [] 4 voltage ranges,
-+ * and [Floor Freq, Boundary Freq, VID min , VID max]
-+ */
-+static const uint32_t tonga_clock_stretcher_ddt_table[2][4][4] = {
-+	{ {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
-+	{ {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} }
-+};
-+
-+/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] */
-+static const uint8_t tonga_clock_stretch_amount_conversion[2][6] = {
-+	{0, 1, 3, 2, 4, 5},
-+	{0, 2, 4, 5, 6, 5}
-+};
-+
-+static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr)
- {
- 	int result;
- 
- 	/* Assert reset */
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 		SMC_SYSCON_RESET_CNTL, rst_reg, 1);
- 
--	result = smu7_upload_smu_firmware_image(smumgr);
-+	result = smu7_upload_smu_firmware_image(hwmgr);
- 	if (result)
- 		return result;
- 
- 	/* Clear status */
--	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- 		ixSMU_STATUS, 0);
- 
- 	/* Enable clock */
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 		SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
- 
- 	/* De-assert reset */
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 		SMC_SYSCON_RESET_CNTL, rst_reg, 0);
- 
- 	/* Set SMU Auto Start */
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 		SMU_INPUT_DATA, AUTO_START, 1);
- 
- 	/* Clear firmware interrupt enable flag */
--	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- 		ixFIRMWARE_FLAGS, 0);
- 
--	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
-+	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
- 		RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
- 
- 	/**
- 	 * Call Test SMU message with 0x20000 offset to trigger SMU start
- 	 */
--	smu7_send_msg_to_smc_offset(smumgr);
-+	smu7_send_msg_to_smc_offset(hwmgr);
- 
- 	/* Wait for done bit to be set */
--	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
-+	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
- 		SMU_STATUS, SMU_DONE, 0);
- 
- 	/* Check pass/failed indicator */
--	if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
-+	if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
- 				CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) {
- 		pr_err("SMU Firmware start failed\n");
- 		return -EINVAL;
- 	}
- 
- 	/* Wait for firmware to initialize */
--	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
-+	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
- 		FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
- 
- 	return 0;
- }
- 
--
--static int tonga_start_in_non_protection_mode(struct pp_smumgr *smumgr)
-+static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
- {
- 	int result = 0;
- 
- 	/* wait for smc boot up */
--	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
-+	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
- 		RCU_UC_EVENTS, boot_seq_done, 0);
- 
- 	/*Clear firmware interrupt enable flag*/
--	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
- 		ixFIRMWARE_FLAGS, 0);
- 
- 
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 		SMC_SYSCON_RESET_CNTL, rst_reg, 1);
- 
--	result = smu7_upload_smu_firmware_image(smumgr);
-+	result = smu7_upload_smu_firmware_image(hwmgr);
- 
- 	if (result != 0)
- 		return result;
- 
- 	/* Set smc instruct start point at 0x0 */
--	smu7_program_jump_on_start(smumgr);
-+	smu7_program_jump_on_start(hwmgr);
- 
- 
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 		SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
- 
- 	/*De-assert reset*/
--	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 		SMC_SYSCON_RESET_CNTL, rst_reg, 0);
- 
- 	/* Wait for firmware to initialize */
--	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
-+	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
- 		FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
- 
- 	return result;
- }
- 
--static int tonga_start_smu(struct pp_smumgr *smumgr)
-+static int tonga_start_smu(struct pp_hwmgr *hwmgr)
- {
- 	int result;
- 
- 	/* Only start SMC if SMC RAM is not running */
--	if (!(smu7_is_smc_ram_running(smumgr) ||
--		cgs_is_virtualization_enabled(smumgr->device))) {
-+	if (!(smu7_is_smc_ram_running(hwmgr) ||
-+		cgs_is_virtualization_enabled(hwmgr->device))) {
- 		/*Check if SMU is running in protected mode*/
--		if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
-+		if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
- 					SMU_FIRMWARE, SMU_MODE)) {
--			result = tonga_start_in_non_protection_mode(smumgr);
-+			result = tonga_start_in_non_protection_mode(hwmgr);
- 			if (result)
- 				return result;
- 		} else {
--			result = tonga_start_in_protection_mode(smumgr);
-+			result = tonga_start_in_protection_mode(hwmgr);
- 			if (result)
- 				return result;
- 		}
- 	}
- 
--	result = smu7_request_smu_load_fw(smumgr);
-+	result = smu7_request_smu_load_fw(hwmgr);
- 
- 	return result;
- }
- 
--/**
-- * Write a 32bit value to the SMC SRAM space.
-- * ALL PARAMETERS ARE IN HOST BYTE ORDER.
-- * @param    smumgr  the address of the powerplay hardware manager.
-- * @param    smcAddress the address in the SMC RAM to access.
-- * @param    value to write to the SMC SRAM.
-- */
--static int tonga_smu_init(struct pp_smumgr *smumgr)
-+static int tonga_smu_init(struct pp_hwmgr *hwmgr)
- {
- 	struct tonga_smumgr *tonga_priv = NULL;
- 	int  i;
-@@ -176,9 +228,9 @@ static int tonga_smu_init(struct pp_smum
- 	if (tonga_priv == NULL)
- 		return -ENOMEM;
- 
--	smumgr->backend = tonga_priv;
-+	hwmgr->smu_backend = tonga_priv;
- 
--	if (smu7_init(smumgr))
-+	if (smu7_init(hwmgr))
- 		return -EINVAL;
- 
- 	for (i = 0; i < SMU72_MAX_LEVELS_GRAPHICS; i++)
-@@ -187,6 +239,3053 @@ static int tonga_smu_init(struct pp_smum
- 	return 0;
- }
- 
-+
-+static int tonga_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
-+	phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
-+	uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
-+{
-+	uint32_t i = 0;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info =
-+			   (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	/* clock - voltage dependency table is empty table */
-+	if (allowed_clock_voltage_table->count == 0)
-+		return -EINVAL;
-+
-+	for (i = 0; i < allowed_clock_voltage_table->count; i++) {
-+		/* find first sclk bigger than request */
-+		if (allowed_clock_voltage_table->entries[i].clk >= clock) {
-+			voltage->VddGfx = phm_get_voltage_index(
-+					pptable_info->vddgfx_lookup_table,
-+				allowed_clock_voltage_table->entries[i].vddgfx);
-+			voltage->Vddc = phm_get_voltage_index(
-+						pptable_info->vddc_lookup_table,
-+				  allowed_clock_voltage_table->entries[i].vddc);
-+
-+			if (allowed_clock_voltage_table->entries[i].vddci)
-+				voltage->Vddci =
-+					phm_get_voltage_id(&data->vddci_voltage_table, allowed_clock_voltage_table->entries[i].vddci);
-+			else
-+				voltage->Vddci =
-+					phm_get_voltage_id(&data->vddci_voltage_table,
-+						allowed_clock_voltage_table->entries[i].vddc - VDDC_VDDCI_DELTA);
-+
-+
-+			if (allowed_clock_voltage_table->entries[i].mvdd)
-+				*mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;
-+
-+			voltage->Phases = 1;
-+			return 0;
-+		}
-+	}
-+
-+	/* sclk is bigger than max sclk in the dependence table */
-+	voltage->VddGfx = phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
-+		allowed_clock_voltage_table->entries[i-1].vddgfx);
-+	voltage->Vddc = phm_get_voltage_index(pptable_info->vddc_lookup_table,
-+		allowed_clock_voltage_table->entries[i-1].vddc);
-+
-+	if (allowed_clock_voltage_table->entries[i-1].vddci)
-+		voltage->Vddci = phm_get_voltage_id(&data->vddci_voltage_table,
-+			allowed_clock_voltage_table->entries[i-1].vddci);
-+
-+	if (allowed_clock_voltage_table->entries[i-1].mvdd)
-+		*mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
-+			SMU72_Discrete_DpmTable *table)
-+{
-+	unsigned int count;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+		table->VddcLevelCount = data->vddc_voltage_table.count;
-+		for (count = 0; count < table->VddcLevelCount; count++) {
-+			table->VddcTable[count] =
-+				PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+		}
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
-+	}
-+	return 0;
-+}
-+
-+static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
-+			SMU72_Discrete_DpmTable *table)
-+{
-+	unsigned int count;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
-+		table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
-+		for (count = 0; count < data->vddgfx_voltage_table.count; count++) {
-+			table->VddGfxTable[count] =
-+				PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+		}
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
-+	}
-+	return 0;
-+}
-+
-+static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
-+			SMU72_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t count;
-+
-+	table->VddciLevelCount = data->vddci_voltage_table.count;
-+	for (count = 0; count < table->VddciLevelCount; count++) {
-+		if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
-+			table->VddciTable[count] =
-+				PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+		} else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
-+			table->SmioTable1.Pattern[count].Voltage =
-+				PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+			/* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
-+			table->SmioTable1.Pattern[count].Smio =
-+				(uint8_t) count;
-+			table->Smio[count] |=
-+				data->vddci_voltage_table.entries[count].smio_low;
-+			table->VddciTable[count] =
-+				PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+		}
-+	}
-+
-+	table->SmioMask1 = data->vddci_voltage_table.mask_low;
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
-+			SMU72_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t count;
-+
-+	if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		table->MvddLevelCount = data->mvdd_voltage_table.count;
-+		for (count = 0; count < table->MvddLevelCount; count++) {
-+			table->SmioTable2.Pattern[count].Voltage =
-+				PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
-+			/* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
-+			table->SmioTable2.Pattern[count].Smio =
-+				(uint8_t) count;
-+			table->Smio[count] |=
-+				data->mvdd_voltage_table.entries[count].smio_low;
-+		}
-+		table->SmioMask2 = data->mvdd_voltage_table.mask_low;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
-+			SMU72_Discrete_DpmTable *table)
-+{
-+	uint32_t count;
-+	uint8_t index = 0;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table =
-+					   pptable_info->vddgfx_lookup_table;
-+	struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table =
-+						pptable_info->vddc_lookup_table;
-+
-+	/* table is already swapped, so in order to use the value from it
-+	 * we need to swap it back.
-+	 */
-+	uint32_t vddc_level_count = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
-+	uint32_t vddgfx_level_count = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
-+
-+	for (count = 0; count < vddc_level_count; count++) {
-+		/* We are populating vddc CAC data to BapmVddc table in split and merged mode */
-+		index = phm_get_voltage_index(vddc_lookup_table,
-+			data->vddc_voltage_table.entries[count].value);
-+		table->BapmVddcVidLoSidd[count] =
-+			convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
-+		table->BapmVddcVidHiSidd[count] =
-+			convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
-+		table->BapmVddcVidHiSidd2[count] =
-+			convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
-+	}
-+
-+	if ((data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2)) {
-+		/* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
-+		for (count = 0; count < vddgfx_level_count; count++) {
-+			index = phm_get_voltage_index(vddgfx_lookup_table,
-+				convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid));
-+			table->BapmVddGfxVidHiSidd2[count] =
-+				convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high);
-+		}
-+	} else {
-+		for (count = 0; count < vddc_level_count; count++) {
-+			index = phm_get_voltage_index(vddc_lookup_table,
-+				data->vddc_voltage_table.entries[count].value);
-+			table->BapmVddGfxVidLoSidd[count] =
-+				convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
-+			table->BapmVddGfxVidHiSidd[count] =
-+				convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
-+			table->BapmVddGfxVidHiSidd2[count] =
-+				convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
-+	SMU72_Discrete_DpmTable *table)
-+{
-+	int result;
-+
-+	result = tonga_populate_smc_vddc_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(!result,
-+			"can not populate VDDC voltage table to SMC",
-+			return -EINVAL);
-+
-+	result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(!result,
-+			"can not populate VDDCI voltage table to SMC",
-+			return -EINVAL);
-+
-+	result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(!result,
-+			"can not populate VDDGFX voltage table to SMC",
-+			return -EINVAL);
-+
-+	result = tonga_populate_smc_mvdd_table(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(!result,
-+			"can not populate MVDD voltage table to SMC",
-+			return -EINVAL);
-+
-+	result = tonga_populate_cac_tables(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(!result,
-+			"can not populate CAC voltage tables to SMC",
-+			return -EINVAL);
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_ulv_level(struct pp_hwmgr *hwmgr,
-+		struct SMU72_Discrete_Ulv *state)
-+{
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	state->CcPwrDynRm = 0;
-+	state->CcPwrDynRm1 = 0;
-+
-+	state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
-+	state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
-+			VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
-+
-+	state->VddcPhase = 1;
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
-+	CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_ulv_state(struct pp_hwmgr *hwmgr,
-+		struct SMU72_Discrete_DpmTable *table)
-+{
-+	return tonga_populate_ulv_level(hwmgr, &table->Ulv);
-+}
-+
-+static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct smu7_dpm_table *dpm_table = &data->dpm_table;
-+	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
-+	uint32_t i;
-+
-+	/* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
-+	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
-+		table->LinkLevel[i].PcieGenSpeed  =
-+			(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
-+		table->LinkLevel[i].PcieLaneCount =
-+			(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
-+		table->LinkLevel[i].EnabledForActivity =
-+			1;
-+		table->LinkLevel[i].SPC =
-+			(uint8_t)(data->pcie_spc_cap & 0xff);
-+		table->LinkLevel[i].DownThreshold =
-+			PP_HOST_TO_SMC_UL(5);
-+		table->LinkLevel[i].UpThreshold =
-+			PP_HOST_TO_SMC_UL(30);
-+	}
-+
-+	smu_data->smc_state_table.LinkLevelCount =
-+		(uint8_t)dpm_table->pcie_speed_table.count;
-+	data->dpm_level_enable_mask.pcie_dpm_enable_mask =
-+		phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
-+
-+	return 0;
-+}
-+
-+static int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
-+		uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
-+{
-+	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	pp_atomctrl_clock_dividers_vi dividers;
-+	uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
-+	uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
-+	uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
-+	uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
-+	uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
-+	uint32_t    reference_clock;
-+	uint32_t reference_divider;
-+	uint32_t fbdiv;
-+	int result;
-+
-+	/* get the engine clock dividers for this clock value*/
-+	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock,  &dividers);
-+
-+	PP_ASSERT_WITH_CODE(result == 0,
-+		"Error retrieving Engine Clock dividers from VBIOS.", return result);
-+
-+	/* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
-+	reference_clock = atomctrl_get_reference_clock(hwmgr);
-+
-+	reference_divider = 1 + dividers.uc_pll_ref_div;
-+
-+	/* low 14 bits is fraction and high 12 bits is divider*/
-+	fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
-+
-+	/* SPLL_FUNC_CNTL setup*/
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
-+		CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
-+		CG_SPLL_FUNC_CNTL, SPLL_PDIV_A,  dividers.uc_pll_post_div);
-+
-+	/* SPLL_FUNC_CNTL_3 setup*/
-+	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
-+		CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
-+
-+	/* set to use fractional accumulation*/
-+	spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
-+		CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
-+		pp_atomctrl_internal_ss_info ss_info;
-+
-+		uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
-+		if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
-+			/*
-+			* ss_info.speed_spectrum_percentage -- in unit of 0.01%
-+			* ss_info.speed_spectrum_rate -- in unit of khz
-+			*/
-+			/* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
-+			uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
-+
-+			/* clkv = 2 * D * fbdiv / NS */
-+			uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
-+
-+			cg_spll_spread_spectrum =
-+				PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
-+			cg_spll_spread_spectrum =
-+				PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
-+			cg_spll_spread_spectrum_2 =
-+				PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
-+		}
-+	}
-+
-+	sclk->SclkFrequency        = engine_clock;
-+	sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
-+	sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
-+	sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
-+	sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
-+	sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
-+						uint32_t engine_clock,
-+				uint16_t sclk_activity_level_threshold,
-+				SMU72_Discrete_GraphicsLevel *graphic_level)
-+{
-+	int result;
-+	uint32_t mvdd;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info =
-+			    (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
-+
-+	/* populate graphics levels*/
-+	result = tonga_get_dependency_volt_by_clk(hwmgr,
-+		pptable_info->vdd_dep_on_sclk, engine_clock,
-+		&graphic_level->MinVoltage, &mvdd);
-+	PP_ASSERT_WITH_CODE((!result),
-+		"can not find VDDC voltage value for VDDC "
-+		"engine clock dependency table", return result);
-+
-+	/* SCLK frequency in units of 10KHz*/
-+	graphic_level->SclkFrequency = engine_clock;
-+	/* Indicates maximum activity level for this performance level. 50% for now*/
-+	graphic_level->ActivityLevel = sclk_activity_level_threshold;
-+
-+	graphic_level->CcPwrDynRm = 0;
-+	graphic_level->CcPwrDynRm1 = 0;
-+	/* this level can be used if activity is high enough.*/
-+	graphic_level->EnabledForActivity = 0;
-+	/* this level can be used for throttling.*/
-+	graphic_level->EnabledForThrottle = 1;
-+	graphic_level->UpHyst = 0;
-+	graphic_level->DownHyst = 0;
-+	graphic_level->VoltageDownHyst = 0;
-+	graphic_level->PowerThrottle = 0;
-+
-+	data->display_timing.min_clock_in_sr =
-+			hwmgr->display_config.min_core_set_clock_in_sr;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkDeepSleep))
-+		graphic_level->DeepSleepDivId =
-+				smu7_get_sleep_divider_id_from_clock(engine_clock,
-+						data->display_timing.min_clock_in_sr);
-+
-+	/* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
-+	graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	if (!result) {
-+		/* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
-+		/* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
-+		CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
-+	}
-+
-+	return result;
-+}
-+
-+static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
-+	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct smu7_dpm_table *dpm_table = &data->dpm_table;
-+	struct phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
-+	uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
-+	uint32_t level_array_address = smu_data->smu7_data.dpm_table_start +
-+				offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
-+
-+	uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *
-+						SMU72_MAX_LEVELS_GRAPHICS;
-+
-+	SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
-+
-+	uint32_t i, max_entry;
-+	uint8_t highest_pcie_level_enabled = 0;
-+	uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0;
-+	uint8_t count = 0;
-+	int result = 0;
-+
-+	memset(levels, 0x00, level_array_size);
-+
-+	for (i = 0; i < dpm_table->sclk_table.count; i++) {
-+		result = tonga_populate_single_graphic_level(hwmgr,
-+					dpm_table->sclk_table.dpm_levels[i].value,
-+					(uint16_t)smu_data->activity_target[i],
-+					&(smu_data->smc_state_table.GraphicsLevel[i]));
-+		if (result != 0)
-+			return result;
-+
-+		/* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
-+		if (i > 1)
-+			smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
-+	}
-+
-+	/* Only enable level 0 for now. */
-+	smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
-+
-+	/* set highest level watermark to high */
-+	if (dpm_table->sclk_table.count > 1)
-+		smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
-+			PPSMC_DISPLAY_WATERMARK_HIGH;
-+
-+	smu_data->smc_state_table.GraphicsDpmLevelCount =
-+		(uint8_t)dpm_table->sclk_table.count;
-+	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
-+		phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
-+
-+	if (pcie_table != NULL) {
-+		PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
-+			"There must be 1 or more PCIE levels defined in PPTable.",
-+			return -EINVAL);
-+		max_entry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/
-+		for (i = 0; i < dpm_table->sclk_table.count; i++) {
-+			smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
-+				(uint8_t) ((i < max_entry) ? i : max_entry);
-+		}
-+	} else {
-+		if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
-+			pr_err("Pcie Dpm Enablemask is 0 !");
-+
-+		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+					(1<<(highest_pcie_level_enabled+1))) != 0)) {
-+			highest_pcie_level_enabled++;
-+		}
-+
-+		while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+					(1<<lowest_pcie_level_enabled)) == 0)) {
-+			lowest_pcie_level_enabled++;
-+		}
-+
-+		while ((count < highest_pcie_level_enabled) &&
-+				((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
-+					(1<<(lowest_pcie_level_enabled+1+count))) == 0)) {
-+			count++;
-+		}
-+		mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
-+			(lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
-+
-+
-+		/* set pcieDpmLevel to highest_pcie_level_enabled*/
-+		for (i = 2; i < dpm_table->sclk_table.count; i++)
-+			smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to lowest_pcie_level_enabled*/
-+		smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
-+
-+		/* set pcieDpmLevel to mid_pcie_level_enabled*/
-+		smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
-+	}
-+	/* level count will send to smc once at init smc table and never change*/
-+	result = smu7_copy_bytes_to_smc(hwmgr, level_array_address,
-+				(uint8_t *)levels, (uint32_t)level_array_size,
-+								SMC_RAM_END);
-+
-+	return result;
-+}
-+
-+static int tonga_calculate_mclk_params(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t memory_clock,
-+		SMU72_Discrete_MemoryLevel *mclk,
-+		bool strobe_mode,
-+		bool dllStateOn
-+		)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
-+	uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
-+	uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
-+	uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
-+	uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
-+	uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
-+	uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
-+	uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
-+	uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
-+
-+	pp_atomctrl_memory_clock_param mpll_param;
-+	int result;
-+
-+	result = atomctrl_get_memory_pll_dividers_si(hwmgr,
-+				memory_clock, &mpll_param, strobe_mode);
-+	PP_ASSERT_WITH_CODE(
-+			!result,
-+			"Error retrieving Memory Clock Parameters from VBIOS.",
-+			return result);
-+
-+	/* MPLL_FUNC_CNTL setup*/
-+	mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL,
-+					mpll_param.bw_ctrl);
-+
-+	/* MPLL_FUNC_CNTL_1 setup*/
-+	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
-+					MPLL_FUNC_CNTL_1, CLKF,
-+					mpll_param.mpll_fb_divider.cl_kf);
-+	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
-+					MPLL_FUNC_CNTL_1, CLKFRAC,
-+					mpll_param.mpll_fb_divider.clk_frac);
-+	mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
-+						MPLL_FUNC_CNTL_1, VCO_MODE,
-+						mpll_param.vco_mode);
-+
-+	/* MPLL_AD_FUNC_CNTL setup*/
-+	mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
-+					MPLL_AD_FUNC_CNTL, YCLK_POST_DIV,
-+					mpll_param.mpll_post_divider);
-+
-+	if (data->is_memory_gddr5) {
-+		/* MPLL_DQ_FUNC_CNTL setup*/
-+		mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
-+						MPLL_DQ_FUNC_CNTL, YCLK_SEL,
-+						mpll_param.yclk_sel);
-+		mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
-+						MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV,
-+						mpll_param.mpll_post_divider);
-+	}
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
-+		/*
-+		 ************************************
-+		 Fref = Reference Frequency
-+		 NF = Feedback divider ratio
-+		 NR = Reference divider ratio
-+		 Fnom = Nominal VCO output frequency = Fref * NF / NR
-+		 Fs = Spreading Rate
-+		 D = Percentage down-spread / 2
-+		 Fint = Reference input frequency to PFD = Fref / NR
-+		 NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
-+		 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
-+		 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
-+		 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
-+		 *************************************
-+		 */
-+		pp_atomctrl_internal_ss_info ss_info;
-+		uint32_t freq_nom;
-+		uint32_t tmp;
-+		uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
-+
-+		/* for GDDR5 for all modes and DDR3 */
-+		if (1 == mpll_param.qdr)
-+			freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
-+		else
-+			freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
-+
-+		/* tmp = (freq_nom / reference_clock * reference_divider) ^ 2  Note: S.I. reference_divider = 1*/
-+		tmp = (freq_nom / reference_clock);
-+		tmp = tmp * tmp;
-+
-+		if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
-+			/* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
-+			/* ss.Info.speed_spectrum_rate -- in unit of khz */
-+			/* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
-+			/*     = reference_clock * 5 / speed_spectrum_rate */
-+			uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
-+
-+			/* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
-+			/*     = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
-+			uint32_t clkv =
-+				(uint32_t)((((131 * ss_info.speed_spectrum_percentage *
-+							ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
-+
-+			mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
-+			mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
-+		}
-+	}
-+
-+	/* MCLK_PWRMGT_CNTL setup */
-+	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
-+	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
-+	mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
-+
-+	/* Save the result data to outpupt memory level structure */
-+	mclk->MclkFrequency   = memory_clock;
-+	mclk->MpllFuncCntl    = mpll_func_cntl;
-+	mclk->MpllFuncCntl_1  = mpll_func_cntl_1;
-+	mclk->MpllFuncCntl_2  = mpll_func_cntl_2;
-+	mclk->MpllAdFuncCntl  = mpll_ad_func_cntl;
-+	mclk->MpllDqFuncCntl  = mpll_dq_func_cntl;
-+	mclk->MclkPwrmgtCntl  = mclk_pwrmgt_cntl;
-+	mclk->DllCntl         = dll_cntl;
-+	mclk->MpllSs1         = mpll_ss1;
-+	mclk->MpllSs2         = mpll_ss2;
-+
-+	return 0;
-+}
-+
-+static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,
-+		bool strobe_mode)
-+{
-+	uint8_t mc_para_index;
-+
-+	if (strobe_mode) {
-+		if (memory_clock < 12500)
-+			mc_para_index = 0x00;
-+		else if (memory_clock > 47500)
-+			mc_para_index = 0x0f;
-+		else
-+			mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
-+	} else {
-+		if (memory_clock < 65000)
-+			mc_para_index = 0x00;
-+		else if (memory_clock > 135000)
-+			mc_para_index = 0x0f;
-+		else
-+			mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
-+	}
-+
-+	return mc_para_index;
-+}
-+
-+static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
-+{
-+	uint8_t mc_para_index;
-+
-+	if (memory_clock < 10000)
-+		mc_para_index = 0;
-+	else if (memory_clock >= 80000)
-+		mc_para_index = 0x0f;
-+	else
-+		mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
-+
-+	return mc_para_index;
-+}
-+
-+
-+static int tonga_populate_single_memory_level(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t memory_clock,
-+		SMU72_Discrete_MemoryLevel *memory_level
-+		)
-+{
-+	uint32_t mvdd = 0;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info =
-+			  (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	int result = 0;
-+	bool dll_state_on;
-+	struct cgs_display_info info = {0};
-+	uint32_t mclk_edc_wr_enable_threshold = 40000;
-+	uint32_t mclk_stutter_mode_threshold = 30000;
-+	uint32_t mclk_edc_enable_threshold = 40000;
-+	uint32_t mclk_strobe_mode_threshold = 40000;
-+
-+	if (NULL != pptable_info->vdd_dep_on_mclk) {
-+		result = tonga_get_dependency_volt_by_clk(hwmgr,
-+				pptable_info->vdd_dep_on_mclk,
-+				memory_clock,
-+				&memory_level->MinVoltage, &mvdd);
-+		PP_ASSERT_WITH_CODE(
-+			!result,
-+			"can not find MinVddc voltage value from memory VDDC "
-+			"voltage dependency table",
-+			return result);
-+	}
-+
-+	if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
-+		memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value;
-+	else
-+		memory_level->MinMvdd = mvdd;
-+
-+	memory_level->EnabledForThrottle = 1;
-+	memory_level->EnabledForActivity = 0;
-+	memory_level->UpHyst = 0;
-+	memory_level->DownHyst = 100;
-+	memory_level->VoltageDownHyst = 0;
-+
-+	/* Indicates maximum activity level for this performance level.*/
-+	memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
-+	memory_level->StutterEnable = 0;
-+	memory_level->StrobeEnable = 0;
-+	memory_level->EdcReadEnable = 0;
-+	memory_level->EdcWriteEnable = 0;
-+	memory_level->RttEnable = 0;
-+
-+	/* default set to low watermark. Highest level will be set to high later.*/
-+	memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+
-+	cgs_get_active_displays_info(hwmgr->device, &info);
-+	data->display_timing.num_existing_displays = info.display_count;
-+
-+	if ((mclk_stutter_mode_threshold != 0) &&
-+	    (memory_clock <= mclk_stutter_mode_threshold) &&
-+	    (!data->is_uvd_enabled)
-+	    && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
-+	    && (data->display_timing.num_existing_displays <= 2)
-+	    && (data->display_timing.num_existing_displays != 0))
-+		memory_level->StutterEnable = 1;
-+
-+	/* decide strobe mode*/
-+	memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
-+		(memory_clock <= mclk_strobe_mode_threshold);
-+
-+	/* decide EDC mode and memory clock ratio*/
-+	if (data->is_memory_gddr5) {
-+		memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock,
-+					memory_level->StrobeEnable);
-+
-+		if ((mclk_edc_enable_threshold != 0) &&
-+				(memory_clock > mclk_edc_enable_threshold)) {
-+			memory_level->EdcReadEnable = 1;
-+		}
-+
-+		if ((mclk_edc_wr_enable_threshold != 0) &&
-+				(memory_clock > mclk_edc_wr_enable_threshold)) {
-+			memory_level->EdcWriteEnable = 1;
-+		}
-+
-+		if (memory_level->StrobeEnable) {
-+			if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >=
-+					((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
-+				dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
-+			} else {
-+				dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
-+			}
-+
-+		} else {
-+			dll_state_on = data->dll_default_on;
-+		}
-+	} else {
-+		memory_level->StrobeRatio =
-+			tonga_get_ddr3_mclk_frequency_ratio(memory_clock);
-+		dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
-+	}
-+
-+	result = tonga_calculate_mclk_params(hwmgr,
-+		memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
-+
-+	if (!result) {
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd);
-+		/* MCLK frequency in units of 10KHz*/
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
-+		/* Indicates maximum activity level for this performance level.*/
-+		CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
-+		CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
-+	}
-+
-+	return result;
-+}
-+
-+int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct tonga_smumgr *smu_data =
-+			(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_dpm_table *dpm_table = &data->dpm_table;
-+	int result;
-+
-+	/* populate MCLK dpm table to SMU7 */
-+	uint32_t level_array_address =
-+				smu_data->smu7_data.dpm_table_start +
-+				offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
-+	uint32_t level_array_size =
-+				sizeof(SMU72_Discrete_MemoryLevel) *
-+				SMU72_MAX_LEVELS_MEMORY;
-+	SMU72_Discrete_MemoryLevel *levels =
-+				smu_data->smc_state_table.MemoryLevel;
-+	uint32_t i;
-+
-+	memset(levels, 0x00, level_array_size);
-+
-+	for (i = 0; i < dpm_table->mclk_table.count; i++) {
-+		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
-+			"can not populate memory level as memory clock is zero",
-+			return -EINVAL);
-+		result = tonga_populate_single_memory_level(
-+				hwmgr,
-+				dpm_table->mclk_table.dpm_levels[i].value,
-+				&(smu_data->smc_state_table.MemoryLevel[i]));
-+		if (result)
-+			return result;
-+	}
-+
-+	/* Only enable level 0 for now.*/
-+	smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
-+
-+	/*
-+	* in order to prevent MC activity from stutter mode to push DPM up.
-+	* the UVD change complements this by putting the MCLK in a higher state
-+	* by default such that we are not effected by up threshold or and MCLK DPM latency.
-+	*/
-+	smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
-+	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
-+
-+	smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
-+	data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
-+	/* set highest level watermark to high*/
-+	smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
-+
-+	/* level count will send to smc once at init smc table and never change*/
-+	result = smu7_copy_bytes_to_smc(hwmgr,
-+		level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
-+		SMC_RAM_END);
-+
-+	return result;
-+}
-+
-+static int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr,
-+				uint32_t mclk, SMIO_Pattern *smio_pattern)
-+{
-+	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint32_t i = 0;
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
-+		/* find mvdd value which clock is more than request */
-+		for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
-+			if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
-+				/* Always round to higher voltage. */
-+				smio_pattern->Voltage =
-+				      data->mvdd_voltage_table.entries[i].value;
-+				break;
-+			}
-+		}
-+
-+		PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
-+			"MVDD Voltage is outside the supported range.",
-+			return -EINVAL);
-+	} else {
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static int tonga_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
-+	SMU72_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	struct tonga_smumgr *smu_data =
-+				(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct pp_atomctrl_clock_dividers_vi dividers;
-+
-+	SMIO_Pattern voltage_level;
-+	uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
-+	uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
-+	uint32_t dll_cntl          = data->clock_registers.vDLL_CNTL;
-+	uint32_t mclk_pwrmgt_cntl  = data->clock_registers.vMCLK_PWRMGT_CNTL;
-+
-+	/* The ACPI state should not do DPM on DC (or ever).*/
-+	table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
-+
-+	table->ACPILevel.MinVoltage =
-+			smu_data->smc_state_table.GraphicsLevel[0].MinVoltage;
-+
-+	/* assign zero for now*/
-+	table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
-+
-+	/* get the engine clock dividers for this clock value*/
-+	result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
-+		table->ACPILevel.SclkFrequency,  &dividers);
-+
-+	PP_ASSERT_WITH_CODE(result == 0,
-+		"Error retrieving Engine Clock dividers from VBIOS.",
-+		return result);
-+
-+	/* divider ID for required SCLK*/
-+	table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
-+	table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-+	table->ACPILevel.DeepSleepDivId = 0;
-+
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
-+					SPLL_PWRON, 0);
-+	spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
-+						SPLL_RESET, 1);
-+	spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
-+						SCLK_MUX_SEL, 4);
-+
-+	table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
-+	table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
-+	table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
-+	table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
-+	table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
-+	table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
-+	table->ACPILevel.CcPwrDynRm = 0;
-+	table->ACPILevel.CcPwrDynRm1 = 0;
-+
-+
-+	/* For various features to be enabled/disabled while this level is active.*/
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
-+	/* SCLK frequency in units of 10KHz*/
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
-+
-+	/* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
-+	table->MemoryACPILevel.MinVoltage =
-+			    smu_data->smc_state_table.MemoryLevel[0].MinVoltage;
-+
-+	/*  CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
-+
-+	if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
-+		table->MemoryACPILevel.MinMvdd =
-+			PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
-+	else
-+		table->MemoryACPILevel.MinMvdd = 0;
-+
-+	/* Force reset on DLL*/
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
-+
-+	/* Disable DLL in ACPIState*/
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
-+	mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
-+		MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
-+
-+	/* Enable DLL bypass signal*/
-+	dll_cntl            = PHM_SET_FIELD(dll_cntl,
-+		DLL_CNTL, MRDCK0_BYPASS, 0);
-+	dll_cntl            = PHM_SET_FIELD(dll_cntl,
-+		DLL_CNTL, MRDCK1_BYPASS, 0);
-+
-+	table->MemoryACPILevel.DllCntl            =
-+		PP_HOST_TO_SMC_UL(dll_cntl);
-+	table->MemoryACPILevel.MclkPwrmgtCntl     =
-+		PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
-+	table->MemoryACPILevel.MpllAdFuncCntl     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
-+	table->MemoryACPILevel.MpllDqFuncCntl     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
-+	table->MemoryACPILevel.MpllFuncCntl       =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
-+	table->MemoryACPILevel.MpllFuncCntl_1     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
-+	table->MemoryACPILevel.MpllFuncCntl_2     =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
-+	table->MemoryACPILevel.MpllSs1            =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
-+	table->MemoryACPILevel.MpllSs2            =
-+		PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
-+
-+	table->MemoryACPILevel.EnabledForThrottle = 0;
-+	table->MemoryACPILevel.EnabledForActivity = 0;
-+	table->MemoryACPILevel.UpHyst = 0;
-+	table->MemoryACPILevel.DownHyst = 100;
-+	table->MemoryACPILevel.VoltageDownHyst = 0;
-+	/* Indicates maximum activity level for this performance level.*/
-+	table->MemoryACPILevel.ActivityLevel =
-+			PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
-+
-+	table->MemoryACPILevel.StutterEnable = 0;
-+	table->MemoryACPILevel.StrobeEnable = 0;
-+	table->MemoryACPILevel.EdcReadEnable = 0;
-+	table->MemoryACPILevel.EdcWriteEnable = 0;
-+	table->MemoryACPILevel.RttEnable = 0;
-+
-+	return result;
-+}
-+
-+static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
-+					SMU72_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+
-+	uint8_t count;
-+	pp_atomctrl_clock_dividers_vi dividers;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info =
-+				(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+						pptable_info->mm_dep_table;
-+
-+	table->UvdLevelCount = (uint8_t) (mm_table->count);
-+	table->UvdBootLevel = 0;
-+
-+	for (count = 0; count < table->UvdLevelCount; count++) {
-+		table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
-+		table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
-+		table->UvdLevel[count].MinVoltage.Vddc =
-+			phm_get_voltage_index(pptable_info->vddc_lookup_table,
-+						mm_table->entries[count].vddc);
-+		table->UvdLevel[count].MinVoltage.VddGfx =
-+			(data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
-+			phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
-+						mm_table->entries[count].vddgfx) : 0;
-+		table->UvdLevel[count].MinVoltage.Vddci =
-+			phm_get_voltage_id(&data->vddci_voltage_table,
-+					     mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
-+		table->UvdLevel[count].MinVoltage.Phases = 1;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(
-+					hwmgr,
-+					table->UvdLevel[count].VclkFrequency,
-+					&dividers);
-+
-+		PP_ASSERT_WITH_CODE((!result),
-+				    "can not find divide id for Vclk clock",
-+					return result);
-+
-+		table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
-+
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+							  table->UvdLevel[count].DclkFrequency, &dividers);
-+		PP_ASSERT_WITH_CODE((!result),
-+				    "can not find divide id for Dclk clock",
-+					return result);
-+
-+		table->UvdLevel[count].DclkDivider =
-+					(uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
-+	}
-+
-+	return result;
-+
-+}
-+
-+static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
-+		SMU72_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+
-+	uint8_t count;
-+	pp_atomctrl_clock_dividers_vi dividers;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info =
-+			      (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+						     pptable_info->mm_dep_table;
-+
-+	table->VceLevelCount = (uint8_t) (mm_table->count);
-+	table->VceBootLevel = 0;
-+
-+	for (count = 0; count < table->VceLevelCount; count++) {
-+		table->VceLevel[count].Frequency =
-+			mm_table->entries[count].eclk;
-+		table->VceLevel[count].MinVoltage.Vddc =
-+			phm_get_voltage_index(pptable_info->vddc_lookup_table,
-+				mm_table->entries[count].vddc);
-+		table->VceLevel[count].MinVoltage.VddGfx =
-+			(data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
-+			phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
-+				mm_table->entries[count].vddgfx) : 0;
-+		table->VceLevel[count].MinVoltage.Vddci =
-+			phm_get_voltage_id(&data->vddci_voltage_table,
-+				mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
-+		table->VceLevel[count].MinVoltage.Phases = 1;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+					table->VceLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((!result),
-+				"can not find divide id for VCE engine clock",
-+				return result);
-+
-+		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
-+	}
-+
-+	return result;
-+}
-+
-+static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
-+		SMU72_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	uint8_t count;
-+	pp_atomctrl_clock_dividers_vi dividers;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info =
-+			     (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+						    pptable_info->mm_dep_table;
-+
-+	table->AcpLevelCount = (uint8_t) (mm_table->count);
-+	table->AcpBootLevel = 0;
-+
-+	for (count = 0; count < table->AcpLevelCount; count++) {
-+		table->AcpLevel[count].Frequency =
-+			pptable_info->mm_dep_table->entries[count].aclk;
-+		table->AcpLevel[count].MinVoltage.Vddc =
-+			phm_get_voltage_index(pptable_info->vddc_lookup_table,
-+			mm_table->entries[count].vddc);
-+		table->AcpLevel[count].MinVoltage.VddGfx =
-+			(data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
-+			phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
-+				mm_table->entries[count].vddgfx) : 0;
-+		table->AcpLevel[count].MinVoltage.Vddci =
-+			phm_get_voltage_id(&data->vddci_voltage_table,
-+				mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
-+		table->AcpLevel[count].MinVoltage.Phases = 1;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+			table->AcpLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((!result),
-+			"can not find divide id for engine clock", return result);
-+
-+		table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
-+	}
-+
-+	return result;
-+}
-+
-+static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
-+		SMU72_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	uint8_t count;
-+	pp_atomctrl_clock_dividers_vi dividers;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct phm_ppt_v1_information *pptable_info =
-+			     (struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
-+						    pptable_info->mm_dep_table;
-+
-+	table->SamuBootLevel = 0;
-+	table->SamuLevelCount = (uint8_t) (mm_table->count);
-+
-+	for (count = 0; count < table->SamuLevelCount; count++) {
-+		/* not sure whether we need evclk or not */
-+		table->SamuLevel[count].Frequency =
-+			pptable_info->mm_dep_table->entries[count].samclock;
-+		table->SamuLevel[count].MinVoltage.Vddc =
-+			phm_get_voltage_index(pptable_info->vddc_lookup_table,
-+				mm_table->entries[count].vddc);
-+		table->SamuLevel[count].MinVoltage.VddGfx =
-+			(data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ?
-+			phm_get_voltage_index(pptable_info->vddgfx_lookup_table,
-+				mm_table->entries[count].vddgfx) : 0;
-+		table->SamuLevel[count].MinVoltage.Vddci =
-+			phm_get_voltage_id(&data->vddci_voltage_table,
-+				mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
-+		table->SamuLevel[count].MinVoltage.Phases = 1;
-+
-+		/* retrieve divider value for VBIOS */
-+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
-+					table->SamuLevel[count].Frequency, &dividers);
-+		PP_ASSERT_WITH_CODE((!result),
-+			"can not find divide id for samu clock", return result);
-+
-+		table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
-+	}
-+
-+	return result;
-+}
-+
-+static int tonga_populate_memory_timing_parameters(
-+		struct pp_hwmgr *hwmgr,
-+		uint32_t engine_clock,
-+		uint32_t memory_clock,
-+		struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
-+		)
-+{
-+	uint32_t dramTiming;
-+	uint32_t dramTiming2;
-+	uint32_t burstTime;
-+	int result;
-+
-+	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
-+				engine_clock, memory_clock);
-+
-+	PP_ASSERT_WITH_CODE(result == 0,
-+		"Error calling VBIOS to set DRAM_TIMING.", return result);
-+
-+	dramTiming  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
-+	dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
-+	burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
-+
-+	arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dramTiming);
-+	arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
-+	arb_regs->McArbBurstTime = (uint8_t)burstTime;
-+
-+	return 0;
-+}
-+
-+static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct tonga_smumgr *smu_data =
-+				(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	int result = 0;
-+	SMU72_Discrete_MCArbDramTimingTable  arb_regs;
-+	uint32_t i, j;
-+
-+	memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
-+
-+	for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
-+		for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
-+			result = tonga_populate_memory_timing_parameters
-+				(hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
-+				 data->dpm_table.mclk_table.dpm_levels[j].value,
-+				 &arb_regs.entries[i][j]);
-+
-+			if (result)
-+				break;
-+		}
-+	}
-+
-+	if (!result) {
-+		result = smu7_copy_bytes_to_smc(
-+				hwmgr,
-+				smu_data->smu7_data.arb_table_start,
-+				(uint8_t *)&arb_regs,
-+				sizeof(SMU72_Discrete_MCArbDramTimingTable),
-+				SMC_RAM_END
-+				);
-+	}
-+
-+	return result;
-+}
-+
-+static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
-+			SMU72_Discrete_DpmTable *table)
-+{
-+	int result = 0;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct tonga_smumgr *smu_data =
-+				(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	table->GraphicsBootLevel = 0;
-+	table->MemoryBootLevel = 0;
-+
-+	/* find boot level from dpm table*/
-+	result = phm_find_boot_level(&(data->dpm_table.sclk_table),
-+	data->vbios_boot_state.sclk_bootup_value,
-+	(uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
-+
-+	if (result != 0) {
-+		smu_data->smc_state_table.GraphicsBootLevel = 0;
-+		pr_err("[powerplay] VBIOS did not find boot engine "
-+				"clock value in dependency table. "
-+				"Using Graphics DPM level 0 !");
-+		result = 0;
-+	}
-+
-+	result = phm_find_boot_level(&(data->dpm_table.mclk_table),
-+		data->vbios_boot_state.mclk_bootup_value,
-+		(uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
-+
-+	if (result != 0) {
-+		smu_data->smc_state_table.MemoryBootLevel = 0;
-+		pr_err("[powerplay] VBIOS did not find boot "
-+				"engine clock value in dependency table."
-+				"Using Memory DPM level 0 !");
-+		result = 0;
-+	}
-+
-+	table->BootVoltage.Vddc =
-+		phm_get_voltage_id(&(data->vddc_voltage_table),
-+			data->vbios_boot_state.vddc_bootup_value);
-+	table->BootVoltage.VddGfx =
-+		phm_get_voltage_id(&(data->vddgfx_voltage_table),
-+			data->vbios_boot_state.vddgfx_bootup_value);
-+	table->BootVoltage.Vddci =
-+		phm_get_voltage_id(&(data->vddci_voltage_table),
-+			data->vbios_boot_state.vddci_bootup_value);
-+	table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
-+
-+	CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
-+
-+	return result;
-+}
-+
-+static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
-+{
-+	uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
-+			volt_with_cks, value;
-+	uint16_t clock_freq_u16;
-+	struct tonga_smumgr *smu_data =
-+				(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
-+			volt_offset = 0;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
-+			table_info->vdd_dep_on_sclk;
-+	uint32_t hw_revision, dev_id;
-+	struct cgs_system_info sys_info = {0};
-+
-+	stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
-+
-+	sys_info.size = sizeof(struct cgs_system_info);
-+
-+	sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
-+	cgs_query_system_info(hwmgr->device, &sys_info);
-+	hw_revision = (uint32_t)sys_info.value;
-+
-+	sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
-+	cgs_query_system_info(hwmgr->device, &sys_info);
-+	dev_id = (uint32_t)sys_info.value;
-+
-+	/* Read SMU_Eefuse to read and calculate RO and determine
-+	 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
-+	 */
-+	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixSMU_EFUSE_0 + (146 * 4));
-+	efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixSMU_EFUSE_0 + (148 * 4));
-+	efuse &= 0xFF000000;
-+	efuse = efuse >> 24;
-+	efuse2 &= 0xF;
-+
-+	if (efuse2 == 1)
-+		ro = (2300 - 1350) * efuse / 255 + 1350;
-+	else
-+		ro = (2500 - 1000) * efuse / 255 + 1000;
-+
-+	if (ro >= 1660)
-+		type = 0;
-+	else
-+		type = 1;
-+
-+	/* Populate Stretch amount */
-+	smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
-+
-+
-+	/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
-+	for (i = 0; i < sclk_table->count; i++) {
-+		smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
-+				sclk_table->entries[i].cks_enable << i;
-+		if (ASICID_IS_TONGA_P(dev_id, hw_revision)) {
-+			volt_without_cks = (uint32_t)((7732 + 60 - ro - 20838 *
-+				(sclk_table->entries[i].clk/100) / 10000) * 1000 /
-+				(8730 - (5301 * (sclk_table->entries[i].clk/100) / 1000)));
-+			volt_with_cks = (uint32_t)((5250 + 51 - ro - 2404 *
-+				(sclk_table->entries[i].clk/100) / 100000) * 1000 /
-+				(6146 - (3193 * (sclk_table->entries[i].clk/100) / 1000)));
-+		} else {
-+			volt_without_cks = (uint32_t)((14041 *
-+				(sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
-+				(4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
-+			volt_with_cks = (uint32_t)((13946 *
-+				(sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
-+				(3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
-+		}
-+		if (volt_without_cks >= volt_with_cks)
-+			volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
-+					sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
-+		smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
-+	}
-+
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			STRETCH_ENABLE, 0x0);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			masterReset, 0x1);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			staticEnable, 0x1);
-+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
-+			masterReset, 0x0);
-+
-+	/* Populate CKS Lookup Table */
-+	if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
-+		stretch_amount2 = 0;
-+	else if (stretch_amount == 3 || stretch_amount == 4)
-+		stretch_amount2 = 1;
-+	else {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_ClockStretcher);
-+		PP_ASSERT_WITH_CODE(false,
-+				"Stretch Amount in PPTable not supported\n",
-+				return -EINVAL);
-+	}
-+
-+	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixPWR_CKS_CNTL);
-+	value &= 0xFFC2FF87;
-+	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
-+			tonga_clock_stretcher_lookup_table[stretch_amount2][0];
-+	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
-+			tonga_clock_stretcher_lookup_table[stretch_amount2][1];
-+	clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table.
-+			GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
-+			SclkFrequency) / 100);
-+	if (tonga_clock_stretcher_lookup_table[stretch_amount2][0] <
-+			clock_freq_u16 &&
-+	    tonga_clock_stretcher_lookup_table[stretch_amount2][1] >
-+			clock_freq_u16) {
-+		/* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
-+		value |= (tonga_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
-+		/* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
-+		value |= (tonga_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
-+		/* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
-+		value |= (tonga_clock_stretch_amount_conversion
-+				[tonga_clock_stretcher_lookup_table[stretch_amount2][3]]
-+				 [stretch_amount]) << 3;
-+	}
-+	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
-+			CKS_LOOKUPTableEntry[0].minFreq);
-+	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
-+			CKS_LOOKUPTableEntry[0].maxFreq);
-+	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
-+			tonga_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
-+	smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
-+			(tonga_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
-+
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixPWR_CKS_CNTL, value);
-+
-+	/* Populate DDT Lookup Table */
-+	for (i = 0; i < 4; i++) {
-+		/* Assign the minimum and maximum VID stored
-+		 * in the last row of Clock Stretcher Voltage Table.
-+		 */
-+		smu_data->smc_state_table.ClockStretcherDataTable.
-+		ClockStretcherDataTableEntry[i].minVID =
-+				(uint8_t) tonga_clock_stretcher_ddt_table[type][i][2];
-+		smu_data->smc_state_table.ClockStretcherDataTable.
-+		ClockStretcherDataTableEntry[i].maxVID =
-+				(uint8_t) tonga_clock_stretcher_ddt_table[type][i][3];
-+		/* Loop through each SCLK and check the frequency
-+		 * to see if it lies within the frequency for clock stretcher.
-+		 */
-+		for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) {
-+			cks_setting = 0;
-+			clock_freq = PP_SMC_TO_HOST_UL(
-+					smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
-+			/* Check the allowed frequency against the sclk level[j].
-+			 *  Sclk's endianness has already been converted,
-+			 *  and it's in 10Khz unit,
-+			 *  as opposed to Data table, which is in Mhz unit.
-+			 */
-+			if (clock_freq >= tonga_clock_stretcher_ddt_table[type][i][0] * 100) {
-+				cks_setting |= 0x2;
-+				if (clock_freq < tonga_clock_stretcher_ddt_table[type][i][1] * 100)
-+					cks_setting |= 0x1;
-+			}
-+			smu_data->smc_state_table.ClockStretcherDataTable.
-+			ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
-+		}
-+		CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.
-+				ClockStretcherDataTable.
-+				ClockStretcherDataTableEntry[i].setting);
-+	}
-+
-+	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixPWR_CKS_CNTL);
-+	value &= 0xFFFFFFFE;
-+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+					ixPWR_CKS_CNTL, value);
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
-+			SMU72_Discrete_DpmTable *table)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint16_t config;
-+
-+	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
-+		/*  Splitted mode */
-+		config = VR_SVI2_PLANE_1;
-+		table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
-+
-+		if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+			config = VR_SVI2_PLANE_2;
-+			table->VRConfig |= config;
-+		} else {
-+			pr_err("VDDC and VDDGFX should "
-+				"be both on SVI2 control in splitted mode !\n");
-+		}
-+	} else {
-+		/* Merged mode  */
-+		config = VR_MERGED_WITH_VDDC;
-+		table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
-+
-+		/* Set Vddc Voltage Controller  */
-+		if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
-+			config = VR_SVI2_PLANE_1;
-+			table->VRConfig |= config;
-+		} else {
-+			pr_err("VDDC should be on "
-+					"SVI2 control in merged mode !\n");
-+		}
-+	}
-+
-+	/* Set Vddci Voltage Controller  */
-+	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
-+		config = VR_SVI2_PLANE_2;  /* only in merged mode */
-+		table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
-+	} else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
-+		config = VR_SMIO_PATTERN_1;
-+		table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
-+	}
-+
-+	/* Set Mvdd Voltage Controller */
-+	if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
-+		config = VR_SMIO_PATTERN_2;
-+		table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
-+	uint32_t tmp;
-+	int result;
-+
-+	/*
-+	* This is a read-modify-write on the first byte of the ARB table.
-+	* The first byte in the SMU72_Discrete_MCArbDramTimingTable structure
-+	* is the field 'current'.
-+	* This solution is ugly, but we never write the whole table only
-+	* individual fields in it.
-+	* In reality this field should not be in that structure
-+	* but in a soft register.
-+	*/
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+				smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
-+
-+	if (result != 0)
-+		return result;
-+
-+	tmp &= 0x00FFFFFF;
-+	tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
-+
-+	return smu7_write_smc_sram_dword(hwmgr,
-+			smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
-+}
-+
-+
-+static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_smumgr *smu_data =
-+				(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
-+	SMU72_Discrete_DpmTable  *dpm_table = &(smu_data->smc_state_table);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
-+	int  i, j, k;
-+	const uint16_t *pdef1, *pdef2;
-+
-+	dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
-+			(uint16_t)(cac_dtp_table->usTDP * 256));
-+	dpm_table->TargetTdp = PP_HOST_TO_SMC_US(
-+			(uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
-+
-+	PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
-+			"Target Operating Temp is out of Range !",
-+			);
-+
-+	dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
-+	dpm_table->GpuTjHyst = 8;
-+
-+	dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
-+
-+	dpm_table->BAPM_TEMP_GRADIENT =
-+				PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
-+	pdef1 = defaults->bapmti_r;
-+	pdef2 = defaults->bapmti_rc;
-+
-+	for (i = 0; i < SMU72_DTE_ITERATIONS; i++) {
-+		for (j = 0; j < SMU72_DTE_SOURCES; j++) {
-+			for (k = 0; k < SMU72_DTE_SINKS; k++) {
-+				dpm_table->BAPMTI_R[i][j][k] =
-+						PP_HOST_TO_SMC_US(*pdef1);
-+				dpm_table->BAPMTI_RC[i][j][k] =
-+						PP_HOST_TO_SMC_US(*pdef2);
-+				pdef1++;
-+				pdef2++;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_svi_load_line(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_smumgr *smu_data =
-+				(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
-+
-+	smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
-+	smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddC;
-+	smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
-+	smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr)
-+{
-+	uint16_t tdc_limit;
-+	struct tonga_smumgr *smu_data =
-+				(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	/* TDC number of fraction bits are changed from 8 to 7
-+	 * for Fiji as requested by SMC team
-+	 */
-+	tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 256);
-+	smu_data->power_tune_table.TDC_VDDC_PkgLimit =
-+			CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
-+	smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
-+			defaults->tdc_vddc_throttle_release_limit_perc;
-+	smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
-+{
-+	struct tonga_smumgr *smu_data =
-+			(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults;
-+	uint32_t temp;
-+
-+	if (smu7_read_smc_sram_dword(hwmgr,
-+			fuse_table_offset +
-+			offsetof(SMU72_Discrete_PmFuses, TdcWaterfallCtl),
-+			(uint32_t *)&temp, SMC_RAM_END))
-+		PP_ASSERT_WITH_CODE(false,
-+				"Attempt to read PmFuses.DW6 "
-+				"(SviLoadLineEn) from SMC Failed !",
-+				return -EINVAL);
-+	else
-+		smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct tonga_smumgr *smu_data =
-+				(struct tonga_smumgr *)(hwmgr->smu_backend);
-+
-+	/* Currently not used. Set all to zero. */
-+	for (i = 0; i < 16; i++)
-+		smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
-+
-+	if ((hwmgr->thermal_controller.advanceFanControlParameters.
-+			usFanOutputSensitivity & (1 << 15)) ||
-+		(hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity == 0))
-+		hwmgr->thermal_controller.advanceFanControlParameters.
-+		usFanOutputSensitivity = hwmgr->thermal_controller.
-+			advanceFanControlParameters.usDefaultFanOutputSensitivity;
-+
-+	smu_data->power_tune_table.FuzzyFan_PwmSetDelta =
-+			PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
-+					advanceFanControlParameters.usFanOutputSensitivity);
-+	return 0;
-+}
-+
-+static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
-+{
-+	int i;
-+	struct tonga_smumgr *smu_data =
-+				(struct tonga_smumgr *)(hwmgr->smu_backend);
-+
-+	/* Currently not used. Set all to zero. */
-+	for (i = 0; i < 16; i++)
-+		smu_data->power_tune_table.GnbLPML[i] = 0;
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_smumgr *smu_data =
-+				(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+	uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
-+	uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
-+	struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
-+
-+	hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
-+	lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
-+
-+	smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
-+	smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
-+			CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
-+
-+	return 0;
-+}
-+
-+static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_smumgr *smu_data =
-+				(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	uint32_t pm_fuse_table_offset;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_PowerContainment)) {
-+		if (smu7_read_smc_sram_dword(hwmgr,
-+				SMU72_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU72_Firmware_Header, PmFuseTable),
-+				&pm_fuse_table_offset, SMC_RAM_END))
-+			PP_ASSERT_WITH_CODE(false,
-+				"Attempt to get pm_fuse_table_offset Failed !",
-+				return -EINVAL);
-+
-+		/* DW6 */
-+		if (tonga_populate_svi_load_line(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+				"Attempt to populate SviLoadLine Failed !",
-+				return -EINVAL);
-+		/* DW7 */
-+		if (tonga_populate_tdc_limit(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to populate TDCLimit Failed !",
-+					return -EINVAL);
-+		/* DW8 */
-+		if (tonga_populate_dw8(hwmgr, pm_fuse_table_offset))
-+			PP_ASSERT_WITH_CODE(false,
-+				"Attempt to populate TdcWaterfallCtl Failed !",
-+				return -EINVAL);
-+
-+		/* DW9-DW12 */
-+		if (tonga_populate_temperature_scaler(hwmgr) != 0)
-+			PP_ASSERT_WITH_CODE(false,
-+				"Attempt to populate LPMLTemperatureScaler Failed !",
-+				return -EINVAL);
-+
-+		/* DW13-DW14 */
-+		if (tonga_populate_fuzzy_fan(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+				"Attempt to populate Fuzzy Fan "
-+				"Control parameters Failed !",
-+				return -EINVAL);
-+
-+		/* DW15-DW18 */
-+		if (tonga_populate_gnb_lpml(hwmgr))
-+			PP_ASSERT_WITH_CODE(false,
-+				"Attempt to populate GnbLPML Failed !",
-+				return -EINVAL);
-+
-+		/* DW20 */
-+		if (tonga_populate_bapm_vddc_base_leakage_sidd(hwmgr))
-+			PP_ASSERT_WITH_CODE(
-+				false,
-+				"Attempt to populate BapmVddCBaseLeakage "
-+				"Hi and Lo Sidd Failed !",
-+				return -EINVAL);
-+
-+		if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
-+				(uint8_t *)&smu_data->power_tune_table,
-+				sizeof(struct SMU72_Discrete_PmFuses), SMC_RAM_END))
-+			PP_ASSERT_WITH_CODE(false,
-+					"Attempt to download PmFuseTable Failed !",
-+					return -EINVAL);
-+	}
-+	return 0;
-+}
-+
-+static int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
-+				 SMU72_Discrete_MCRegisters *mc_reg_table)
-+{
-+	const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)hwmgr->smu_backend;
-+
-+	uint32_t i, j;
-+
-+	for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
-+		if (smu_data->mc_reg_table.validflag & 1<<j) {
-+			PP_ASSERT_WITH_CODE(
-+				i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE,
-+				"Index of mc_reg_table->address[] array "
-+				"out of boundary",
-+				return -EINVAL);
-+			mc_reg_table->address[i].s0 =
-+				PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
-+			mc_reg_table->address[i].s1 =
-+				PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
-+			i++;
-+		}
-+	}
-+
-+	mc_reg_table->last = (uint8_t)i;
-+
-+	return 0;
-+}
-+
-+/*convert register values from driver to SMC format */
-+static void tonga_convert_mc_registers(
-+	const struct tonga_mc_reg_entry *entry,
-+	SMU72_Discrete_MCRegisterSet *data,
-+	uint32_t num_entries, uint32_t valid_flag)
-+{
-+	uint32_t i, j;
-+
-+	for (i = 0, j = 0; j < num_entries; j++) {
-+		if (valid_flag & 1<<j) {
-+			data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
-+			i++;
-+		}
-+	}
-+}
-+
-+static int tonga_convert_mc_reg_table_entry_to_smc(
-+		struct pp_hwmgr *hwmgr,
-+		const uint32_t memory_clock,
-+		SMU72_Discrete_MCRegisterSet *mc_reg_table_data
-+		)
-+{
-+	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
-+	uint32_t i = 0;
-+
-+	for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
-+		if (memory_clock <=
-+			smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
-+			break;
-+		}
-+	}
-+
-+	if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
-+		--i;
-+
-+	tonga_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
-+				mc_reg_table_data, smu_data->mc_reg_table.last,
-+				smu_data->mc_reg_table.validflag);
-+
-+	return 0;
-+}
-+
-+static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
-+		SMU72_Discrete_MCRegisters *mc_regs)
-+{
-+	int result = 0;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	int res;
-+	uint32_t i;
-+
-+	for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
-+		res = tonga_convert_mc_reg_table_entry_to_smc(
-+				hwmgr,
-+				data->dpm_table.mclk_table.dpm_levels[i].value,
-+				&mc_regs->data[i]
-+				);
-+
-+		if (0 != res)
-+			result = res;
-+	}
-+
-+	return result;
-+}
-+
-+static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	uint32_t address;
-+	int32_t result;
-+
-+	if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
-+		return 0;
-+
-+
-+	memset(&smu_data->mc_regs, 0, sizeof(SMU72_Discrete_MCRegisters));
-+
-+	result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
-+
-+	if (result != 0)
-+		return result;
-+
-+
-+	address = smu_data->smu7_data.mc_reg_table_start +
-+			(uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
-+
-+	return  smu7_copy_bytes_to_smc(
-+			hwmgr, address,
-+			(uint8_t *)&smu_data->mc_regs.data[0],
-+			sizeof(SMU72_Discrete_MCRegisterSet) *
-+			data->dpm_table.mclk_table.count,
-+			SMC_RAM_END);
-+}
-+
-+static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
-+
-+	memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters));
-+	result = tonga_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to initialize MCRegTable for the MC register addresses !",
-+		return result;);
-+
-+	result = tonga_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to initialize MCRegTable for driver state !",
-+		return result;);
-+
-+	return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
-+			(uint8_t *)&smu_data->mc_regs, sizeof(SMU72_Discrete_MCRegisters), SMC_RAM_END);
-+}
-+
-+static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
-+	struct  phm_ppt_v1_information *table_info =
-+			(struct  phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	if (table_info &&
-+			table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
-+			table_info->cac_dtp_table->usPowerTuneDataSetID)
-+		smu_data->power_tune_defaults =
-+				&tonga_power_tune_data_set_array
-+				[table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
-+	else
-+		smu_data->power_tune_defaults = &tonga_power_tune_data_set_array[0];
-+}
-+
-+static void tonga_save_default_power_profile(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_smumgr *data = (struct tonga_smumgr *)(hwmgr->smu_backend);
-+	struct SMU72_Discrete_GraphicsLevel *levels =
-+				data->smc_state_table.GraphicsLevel;
-+	unsigned min_level = 1;
-+
-+	hwmgr->default_gfx_power_profile.activity_threshold =
-+			be16_to_cpu(levels[0].ActivityLevel);
-+	hwmgr->default_gfx_power_profile.up_hyst = levels[0].UpHyst;
-+	hwmgr->default_gfx_power_profile.down_hyst = levels[0].DownHyst;
-+	hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
-+
-+	hwmgr->default_compute_power_profile = hwmgr->default_gfx_power_profile;
-+	hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
-+
-+	/* Workaround compute SDMA instability: disable lowest SCLK
-+	 * DPM level. Optimize compute power profile: Use only highest
-+	 * 2 power levels (if more than 2 are available), Hysteresis:
-+	 * 0ms up, 5ms down
-+	 */
-+	if (data->smc_state_table.GraphicsDpmLevelCount > 2)
-+		min_level = data->smc_state_table.GraphicsDpmLevelCount - 2;
-+	else if (data->smc_state_table.GraphicsDpmLevelCount == 2)
-+		min_level = 1;
-+	else
-+		min_level = 0;
-+	hwmgr->default_compute_power_profile.min_sclk =
-+			be32_to_cpu(levels[min_level].SclkFrequency);
-+	hwmgr->default_compute_power_profile.up_hyst = 0;
-+	hwmgr->default_compute_power_profile.down_hyst = 5;
-+
-+	hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
-+	hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
-+}
-+
-+static int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct tonga_smumgr *smu_data =
-+			(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table);
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	uint8_t i;
-+	pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
-+
-+
-+	memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
-+
-+	tonga_initialize_power_tune_defaults(hwmgr);
-+
-+	if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control)
-+		tonga_populate_smc_voltage_tables(hwmgr, table);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-+
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StepVddc))
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
-+
-+	if (data->is_memory_gddr5)
-+		table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
-+
-+	i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
-+
-+	if (i == 1 || i == 0)
-+		table->SystemFlags |= 0x40;
-+
-+	if (data->ulv_supported && table_info->us_ulv_voltage_offset) {
-+		result = tonga_populate_ulv_state(hwmgr, table);
-+		PP_ASSERT_WITH_CODE(!result,
-+			"Failed to initialize ULV state !",
-+			return result;);
-+
-+		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-+			ixCG_ULV_PARAMETER, 0x40035);
-+	}
-+
-+	result = tonga_populate_smc_link_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to initialize Link Level !", return result);
-+
-+	result = tonga_populate_all_graphic_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to initialize Graphics Level !", return result);
-+
-+	result = tonga_populate_all_memory_levels(hwmgr);
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to initialize Memory Level !", return result);
-+
-+	result = tonga_populate_smc_acpi_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to initialize ACPI Level !", return result);
-+
-+	result = tonga_populate_smc_vce_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to initialize VCE Level !", return result);
-+
-+	result = tonga_populate_smc_acp_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to initialize ACP Level !", return result);
-+
-+	result = tonga_populate_smc_samu_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to initialize SAMU Level !", return result);
-+
-+	/* Since only the initial state is completely set up at this
-+	* point (the other states are just copies of the boot state) we only
-+	* need to populate the  ARB settings for the initial state.
-+	*/
-+	result = tonga_program_memory_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to Write ARB settings for the initial state.",
-+		return result;);
-+
-+	result = tonga_populate_smc_uvd_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to initialize UVD Level !", return result);
-+
-+	result = tonga_populate_smc_boot_level(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to initialize Boot Level !", return result);
-+
-+	tonga_populate_bapm_parameters_in_dpm_table(hwmgr);
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to populate BAPM Parameters !", return result);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ClockStretcher)) {
-+		result = tonga_populate_clock_stretcher_data_table(hwmgr);
-+		PP_ASSERT_WITH_CODE(!result,
-+			"Failed to populate Clock Stretcher Data Table !",
-+			return result;);
-+	}
-+	table->GraphicsVoltageChangeEnable  = 1;
-+	table->GraphicsThermThrottleEnable  = 1;
-+	table->GraphicsInterval = 1;
-+	table->VoltageInterval  = 1;
-+	table->ThermalInterval  = 1;
-+	table->TemperatureLimitHigh =
-+		table_info->cac_dtp_table->usTargetOperatingTemp *
-+		SMU7_Q88_FORMAT_CONVERSION_UNIT;
-+	table->TemperatureLimitLow =
-+		(table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
-+		SMU7_Q88_FORMAT_CONVERSION_UNIT;
-+	table->MemoryVoltageChangeEnable  = 1;
-+	table->MemoryInterval  = 1;
-+	table->VoltageResponseTime  = 0;
-+	table->PhaseResponseTime  = 0;
-+	table->MemoryThermThrottleEnable  = 1;
-+
-+	/*
-+	* Cail reads current link status and reports it as cap (we cannot
-+	* change this due to some previous issues we had)
-+	* SMC drops the link status to lowest level after enabling
-+	* DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again
-+	* but this time Cail reads current link status which was set to low by
-+	* SMC and reports it as cap to powerplay
-+	* To avoid it, we set PCIeBootLinkLevel to highest dpm level
-+	*/
-+	PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
-+			"There must be 1 or more PCIE levels defined in PPTable.",
-+			return -EINVAL);
-+
-+	table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
-+
-+	table->PCIeGenInterval  = 1;
-+
-+	result = tonga_populate_vr_config(hwmgr, table);
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to populate VRConfig setting !", return result);
-+
-+	table->ThermGpio  = 17;
-+	table->SclkStepSize = 0x4000;
-+
-+	if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID,
-+						&gpio_pin_assignment)) {
-+		table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_RegulatorHot);
-+	} else {
-+		table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_RegulatorHot);
-+	}
-+
-+	if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
-+						&gpio_pin_assignment)) {
-+		table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition);
-+	} else {
-+		table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition);
-+	}
-+
-+	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+		PHM_PlatformCaps_Falcon_QuickTransition);
-+
-+	if (0) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_AutomaticDCTransition);
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_Falcon_QuickTransition);
-+	}
-+
-+	if (atomctrl_get_pp_assign_pin(hwmgr,
-+			THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment)) {
-+		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ThermalOutGPIO);
-+
-+		table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
-+
-+		table->ThermOutPolarity =
-+			(0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
-+			(1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1 : 0;
-+
-+		table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
-+
-+		/* if required, combine VRHot/PCC with thermal out GPIO*/
-+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_RegulatorHot) &&
-+			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_CombinePCCWithThermalSignal)){
-+			table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
-+		}
-+	} else {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_ThermalOutGPIO);
-+
-+		table->ThermOutGpio = 17;
-+		table->ThermOutPolarity = 1;
-+		table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
-+	}
-+
-+	for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++)
-+		table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
-+
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
-+	CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
-+	CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
-+
-+	/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
-+	result = smu7_copy_bytes_to_smc(
-+			hwmgr,
-+			smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags),
-+			(uint8_t *)&(table->SystemFlags),
-+			sizeof(SMU72_Discrete_DpmTable) - 3 * sizeof(SMU72_PIDController),
-+			SMC_RAM_END);
-+
-+	PP_ASSERT_WITH_CODE(!result,
-+		"Failed to upload dpm data to SMC memory !", return result;);
-+
-+	result = tonga_init_arb_table_index(hwmgr);
-+	PP_ASSERT_WITH_CODE(!result,
-+			"Failed to upload arb data to SMC memory !", return result);
-+
-+	tonga_populate_pm_fuses(hwmgr);
-+	PP_ASSERT_WITH_CODE((!result),
-+		"Failed to populate initialize pm fuses !", return result);
-+
-+	result = tonga_populate_initial_mc_reg_table(hwmgr);
-+	PP_ASSERT_WITH_CODE((!result),
-+		"Failed to populate initialize MC Reg table !", return result);
-+
-+	tonga_save_default_power_profile(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_smumgr *smu_data =
-+			(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	SMU72_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
-+	uint32_t duty100;
-+	uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
-+	uint16_t fdo_min, slope1, slope2;
-+	uint32_t reference_clock;
-+	int res;
-+	uint64_t tmp64;
-+
-+	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_MicrocodeFanControl))
-+		return 0;
-+
-+	if (hwmgr->thermal_controller.fanInfo.bNoFan) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	if (0 == smu_data->smu7_data.fan_table_start) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
-+						CGS_IND_REG__SMC,
-+						CG_FDO_CTRL1, FMAX_DUTY100);
-+
-+	if (0 == duty100) {
-+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-+				PHM_PlatformCaps_MicrocodeFanControl);
-+		return 0;
-+	}
-+
-+	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
-+	do_div(tmp64, 10000);
-+	fdo_min = (uint16_t)tmp64;
-+
-+	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
-+		   hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
-+	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
-+		  hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
-+
-+	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
-+		    hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
-+	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
-+		    hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
-+
-+	slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
-+	slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
-+
-+	fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
-+	fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
-+	fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
-+
-+	fan_table.Slope1 = cpu_to_be16(slope1);
-+	fan_table.Slope2 = cpu_to_be16(slope2);
-+
-+	fan_table.FdoMin = cpu_to_be16(fdo_min);
-+
-+	fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
-+
-+	fan_table.HystUp = cpu_to_be16(1);
-+
-+	fan_table.HystSlope = cpu_to_be16(1);
-+
-+	fan_table.TempRespLim = cpu_to_be16(5);
-+
-+	reference_clock = smu7_get_xclk(hwmgr);
-+
-+	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
-+
-+	fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
-+
-+	fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
-+
-+	fan_table.FanControl_GL_Flag = 1;
-+
-+	res = smu7_copy_bytes_to_smc(hwmgr,
-+					smu_data->smu7_data.fan_table_start,
-+					(uint8_t *)&fan_table,
-+					(uint32_t)sizeof(fan_table),
-+					SMC_RAM_END);
-+
-+	return 0;
-+}
-+
-+
-+static int tonga_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	if (data->need_update_smu7_dpm_table &
-+		(DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
-+		return tonga_program_memory_timing_parameters(hwmgr);
-+
-+	return 0;
-+}
-+
-+static int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct tonga_smumgr *smu_data =
-+			(struct tonga_smumgr *)(hwmgr->smu_backend);
-+
-+	int result = 0;
-+	uint32_t low_sclk_interrupt_threshold = 0;
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_SclkThrottleLowNotification)
-+		&& (hwmgr->gfx_arbiter.sclk_threshold !=
-+				data->low_sclk_interrupt_threshold)) {
-+		data->low_sclk_interrupt_threshold =
-+				hwmgr->gfx_arbiter.sclk_threshold;
-+		low_sclk_interrupt_threshold =
-+				data->low_sclk_interrupt_threshold;
-+
-+		CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
-+
-+		result = smu7_copy_bytes_to_smc(
-+				hwmgr,
-+				smu_data->smu7_data.dpm_table_start +
-+				offsetof(SMU72_Discrete_DpmTable,
-+					LowSclkInterruptThreshold),
-+				(uint8_t *)&low_sclk_interrupt_threshold,
-+				sizeof(uint32_t),
-+				SMC_RAM_END);
-+	}
-+
-+	result = tonga_update_and_upload_mc_reg_table(hwmgr);
-+
-+	PP_ASSERT_WITH_CODE((!result),
-+				"Failed to upload MC reg table !",
-+				return result);
-+
-+	result = tonga_program_mem_timing_parameters(hwmgr);
-+	PP_ASSERT_WITH_CODE((result == 0),
-+			"Failed to program memory timing parameters !",
-+			);
-+
-+	return result;
-+}
-+
-+static uint32_t tonga_get_offsetof(uint32_t type, uint32_t member)
-+{
-+	switch (type) {
-+	case SMU_SoftRegisters:
-+		switch (member) {
-+		case HandshakeDisables:
-+			return offsetof(SMU72_SoftRegisters, HandshakeDisables);
-+		case VoltageChangeTimeout:
-+			return offsetof(SMU72_SoftRegisters, VoltageChangeTimeout);
-+		case AverageGraphicsActivity:
-+			return offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
-+		case PreVBlankGap:
-+			return offsetof(SMU72_SoftRegisters, PreVBlankGap);
-+		case VBlankTimeout:
-+			return offsetof(SMU72_SoftRegisters, VBlankTimeout);
-+		case UcodeLoadStatus:
-+			return offsetof(SMU72_SoftRegisters, UcodeLoadStatus);
-+		case DRAM_LOG_ADDR_H:
-+			return offsetof(SMU72_SoftRegisters, DRAM_LOG_ADDR_H);
-+		case DRAM_LOG_ADDR_L:
-+			return offsetof(SMU72_SoftRegisters, DRAM_LOG_ADDR_L);
-+		case DRAM_LOG_PHY_ADDR_H:
-+			return offsetof(SMU72_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
-+		case DRAM_LOG_PHY_ADDR_L:
-+			return offsetof(SMU72_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
-+		case DRAM_LOG_BUFF_SIZE:
-+			return offsetof(SMU72_SoftRegisters, DRAM_LOG_BUFF_SIZE);
-+		}
-+	case SMU_Discrete_DpmTable:
-+		switch (member) {
-+		case UvdBootLevel:
-+			return offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
-+		case VceBootLevel:
-+			return offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
-+		case SamuBootLevel:
-+			return offsetof(SMU72_Discrete_DpmTable, SamuBootLevel);
-+		case LowSclkInterruptThreshold:
-+			return offsetof(SMU72_Discrete_DpmTable, LowSclkInterruptThreshold);
-+		}
-+	}
-+	pr_warn("can't get the offset of type %x member %x\n", type, member);
-+	return 0;
-+}
-+
-+static uint32_t tonga_get_mac_definition(uint32_t value)
-+{
-+	switch (value) {
-+	case SMU_MAX_LEVELS_GRAPHICS:
-+		return SMU72_MAX_LEVELS_GRAPHICS;
-+	case SMU_MAX_LEVELS_MEMORY:
-+		return SMU72_MAX_LEVELS_MEMORY;
-+	case SMU_MAX_LEVELS_LINK:
-+		return SMU72_MAX_LEVELS_LINK;
-+	case SMU_MAX_ENTRIES_SMIO:
-+		return SMU72_MAX_ENTRIES_SMIO;
-+	case SMU_MAX_LEVELS_VDDC:
-+		return SMU72_MAX_LEVELS_VDDC;
-+	case SMU_MAX_LEVELS_VDDGFX:
-+		return SMU72_MAX_LEVELS_VDDGFX;
-+	case SMU_MAX_LEVELS_VDDCI:
-+		return SMU72_MAX_LEVELS_VDDCI;
-+	case SMU_MAX_LEVELS_MVDD:
-+		return SMU72_MAX_LEVELS_MVDD;
-+	}
-+	pr_warn("can't get the mac value %x\n", value);
-+
-+	return 0;
-+}
-+
-+static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_smumgr *smu_data =
-+				(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+	smu_data->smc_state_table.UvdBootLevel = 0;
-+	if (table_info->mm_dep_table->count > 0)
-+		smu_data->smc_state_table.UvdBootLevel =
-+				(uint8_t) (table_info->mm_dep_table->count - 1);
-+	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
-+				offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
-+	mm_boot_level_offset /= 4;
-+	mm_boot_level_offset *= 4;
-+	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset);
-+	mm_boot_level_value &= 0x00FFFFFF;
-+	mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
-+	cgs_write_ind_register(hwmgr->device,
-+				CGS_IND_REG__SMC,
-+				mm_boot_level_offset, mm_boot_level_value);
-+
-+	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_UVDDPM) ||
-+		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StablePState))
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_UVDDPM_SetEnabledMask,
-+				(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
-+	return 0;
-+}
-+
-+static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_smumgr *smu_data =
-+				(struct tonga_smumgr *)(hwmgr->smu_backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+	struct phm_ppt_v1_information *table_info =
-+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-+
-+
-+	smu_data->smc_state_table.VceBootLevel =
-+		(uint8_t) (table_info->mm_dep_table->count - 1);
-+
-+	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
-+					offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
-+	mm_boot_level_offset /= 4;
-+	mm_boot_level_offset *= 4;
-+	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset);
-+	mm_boot_level_value &= 0xFF00FFFF;
-+	mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
-+	cgs_write_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+					PHM_PlatformCaps_StablePState))
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_VCEDPM_SetEnabledMask,
-+				(uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
-+	return 0;
-+}
-+
-+static int tonga_update_samu_smc_table(struct pp_hwmgr *hwmgr)
-+{
-+	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
-+	uint32_t mm_boot_level_offset, mm_boot_level_value;
-+
-+	smu_data->smc_state_table.SamuBootLevel = 0;
-+	mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
-+				offsetof(SMU72_Discrete_DpmTable, SamuBootLevel);
-+
-+	mm_boot_level_offset /= 4;
-+	mm_boot_level_offset *= 4;
-+	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset);
-+	mm_boot_level_value &= 0xFFFFFF00;
-+	mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
-+	cgs_write_ind_register(hwmgr->device,
-+			CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
-+
-+	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-+			PHM_PlatformCaps_StablePState))
-+		smum_send_msg_to_smc_with_parameter(hwmgr,
-+				PPSMC_MSG_SAMUDPM_SetEnabledMask,
-+				(uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
-+	return 0;
-+}
-+
-+static int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
-+{
-+	switch (type) {
-+	case SMU_UVD_TABLE:
-+		tonga_update_uvd_smc_table(hwmgr);
-+		break;
-+	case SMU_VCE_TABLE:
-+		tonga_update_vce_smc_table(hwmgr);
-+		break;
-+	case SMU_SAMU_TABLE:
-+		tonga_update_samu_smc_table(hwmgr);
-+		break;
-+	default:
-+		break;
-+	}
-+	return 0;
-+}
-+
-+static int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
-+{
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
-+
-+	uint32_t tmp;
-+	int result;
-+	bool error = false;
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU72_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU72_Firmware_Header, DpmTable),
-+				&tmp, SMC_RAM_END);
-+
-+	if (!result)
-+		smu_data->smu7_data.dpm_table_start = tmp;
-+
-+	error |= (result != 0);
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU72_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU72_Firmware_Header, SoftRegisters),
-+				&tmp, SMC_RAM_END);
-+
-+	if (!result) {
-+		data->soft_regs_start = tmp;
-+		smu_data->smu7_data.soft_regs_start = tmp;
-+	}
-+
-+	error |= (result != 0);
-+
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU72_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU72_Firmware_Header, mcRegisterTable),
-+				&tmp, SMC_RAM_END);
-+
-+	if (!result)
-+		smu_data->smu7_data.mc_reg_table_start = tmp;
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU72_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU72_Firmware_Header, FanTable),
-+				&tmp, SMC_RAM_END);
-+
-+	if (!result)
-+		smu_data->smu7_data.fan_table_start = tmp;
-+
-+	error |= (result != 0);
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU72_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
-+				&tmp, SMC_RAM_END);
-+
-+	if (!result)
-+		smu_data->smu7_data.arb_table_start = tmp;
-+
-+	error |= (result != 0);
-+
-+	result = smu7_read_smc_sram_dword(hwmgr,
-+				SMU72_FIRMWARE_HEADER_LOCATION +
-+				offsetof(SMU72_Firmware_Header, Version),
-+				&tmp, SMC_RAM_END);
-+
-+	if (!result)
-+		hwmgr->microcode_version_info.SMC = tmp;
-+
-+	error |= (result != 0);
-+
-+	return error ? 1 : 0;
-+}
-+
-+/*---------------------------MC----------------------------*/
-+
-+static uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
-+{
-+	return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
-+}
-+
-+static bool tonga_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
-+{
-+	bool result = true;
-+
-+	switch (in_reg) {
-+	case  mmMC_SEQ_RAS_TIMING:
-+		*out_reg = mmMC_SEQ_RAS_TIMING_LP;
-+		break;
-+
-+	case  mmMC_SEQ_DLL_STBY:
-+		*out_reg = mmMC_SEQ_DLL_STBY_LP;
-+		break;
-+
-+	case  mmMC_SEQ_G5PDX_CMD0:
-+		*out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
-+		break;
-+
-+	case  mmMC_SEQ_G5PDX_CMD1:
-+		*out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
-+		break;
-+
-+	case  mmMC_SEQ_G5PDX_CTRL:
-+		*out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
-+		break;
-+
-+	case mmMC_SEQ_CAS_TIMING:
-+		*out_reg = mmMC_SEQ_CAS_TIMING_LP;
-+		break;
-+
-+	case mmMC_SEQ_MISC_TIMING:
-+		*out_reg = mmMC_SEQ_MISC_TIMING_LP;
-+		break;
-+
-+	case mmMC_SEQ_MISC_TIMING2:
-+		*out_reg = mmMC_SEQ_MISC_TIMING2_LP;
-+		break;
-+
-+	case mmMC_SEQ_PMG_DVS_CMD:
-+		*out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
-+		break;
-+
-+	case mmMC_SEQ_PMG_DVS_CTL:
-+		*out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
-+		break;
-+
-+	case mmMC_SEQ_RD_CTL_D0:
-+		*out_reg = mmMC_SEQ_RD_CTL_D0_LP;
-+		break;
-+
-+	case mmMC_SEQ_RD_CTL_D1:
-+		*out_reg = mmMC_SEQ_RD_CTL_D1_LP;
-+		break;
-+
-+	case mmMC_SEQ_WR_CTL_D0:
-+		*out_reg = mmMC_SEQ_WR_CTL_D0_LP;
-+		break;
-+
-+	case mmMC_SEQ_WR_CTL_D1:
-+		*out_reg = mmMC_SEQ_WR_CTL_D1_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_EMRS:
-+		*out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_MRS:
-+		*out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_MRS1:
-+		*out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
-+		break;
-+
-+	case mmMC_SEQ_PMG_TIMING:
-+		*out_reg = mmMC_SEQ_PMG_TIMING_LP;
-+		break;
-+
-+	case mmMC_PMG_CMD_MRS2:
-+		*out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
-+		break;
-+
-+	case mmMC_SEQ_WR_CTL_2:
-+		*out_reg = mmMC_SEQ_WR_CTL_2_LP;
-+		break;
-+
-+	default:
-+		result = false;
-+		break;
-+	}
-+
-+	return result;
-+}
-+
-+static int tonga_set_s0_mc_reg_index(struct tonga_mc_reg_table *table)
-+{
-+	uint32_t i;
-+	uint16_t address;
-+
-+	for (i = 0; i < table->last; i++) {
-+		table->mc_reg_address[i].s0 =
-+			tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1,
-+							&address) ?
-+							address :
-+						 table->mc_reg_address[i].s1;
-+	}
-+	return 0;
-+}
-+
-+static int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
-+					struct tonga_mc_reg_table *ni_table)
-+{
-+	uint8_t i, j;
-+
-+	PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+		"Invalid VramInfo table.", return -EINVAL);
-+	PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
-+		"Invalid VramInfo table.", return -EINVAL);
-+
-+	for (i = 0; i < table->last; i++)
-+		ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
-+
-+	ni_table->last = table->last;
-+
-+	for (i = 0; i < table->num_entries; i++) {
-+		ni_table->mc_reg_table_entry[i].mclk_max =
-+			table->mc_reg_table_entry[i].mclk_max;
-+		for (j = 0; j < table->last; j++) {
-+			ni_table->mc_reg_table_entry[i].mc_data[j] =
-+				table->mc_reg_table_entry[i].mc_data[j];
-+		}
-+	}
-+
-+	ni_table->num_entries = table->num_entries;
-+
-+	return 0;
-+}
-+
-+static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr,
-+					struct tonga_mc_reg_table *table)
-+{
-+	uint8_t i, j, k;
-+	uint32_t temp_reg;
-+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-+
-+	for (i = 0, j = table->last; i < table->last; i++) {
-+		PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+			"Invalid VramInfo table.", return -EINVAL);
-+
-+		switch (table->mc_reg_address[i].s1) {
-+
-+		case mmMC_SEQ_MISC1:
-+			temp_reg = cgs_read_register(hwmgr->device,
-+							mmMC_PMG_CMD_EMRS);
-+			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
-+			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
-+			for (k = 0; k < table->num_entries; k++) {
-+				table->mc_reg_table_entry[k].mc_data[j] =
-+					((temp_reg & 0xffff0000)) |
-+					((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
-+			}
-+			j++;
-+			PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+				"Invalid VramInfo table.", return -EINVAL);
-+
-+			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
-+			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
-+			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
-+			for (k = 0; k < table->num_entries; k++) {
-+				table->mc_reg_table_entry[k].mc_data[j] =
-+					(temp_reg & 0xffff0000) |
-+					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
-+
-+				if (!data->is_memory_gddr5)
-+					table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
-+			}
-+			j++;
-+			PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+				"Invalid VramInfo table.", return -EINVAL);
-+
-+			if (!data->is_memory_gddr5) {
-+				table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
-+				table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
-+				for (k = 0; k < table->num_entries; k++)
-+					table->mc_reg_table_entry[k].mc_data[j] =
-+						(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
-+				j++;
-+				PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+					"Invalid VramInfo table.", return -EINVAL);
-+			}
-+
-+			break;
-+
-+		case mmMC_SEQ_RESERVE_M:
-+			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
-+			table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
-+			table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
-+			for (k = 0; k < table->num_entries; k++) {
-+				table->mc_reg_table_entry[k].mc_data[j] =
-+					(temp_reg & 0xffff0000) |
-+					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
-+			}
-+			j++;
-+			PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
-+				"Invalid VramInfo table.", return -EINVAL);
-+			break;
-+
-+		default:
-+			break;
-+		}
-+
-+	}
-+
-+	table->last = j;
-+
-+	return 0;
-+}
-+
-+static int tonga_set_valid_flag(struct tonga_mc_reg_table *table)
-+{
-+	uint8_t i, j;
-+
-+	for (i = 0; i < table->last; i++) {
-+		for (j = 1; j < table->num_entries; j++) {
-+			if (table->mc_reg_table_entry[j-1].mc_data[i] !=
-+				table->mc_reg_table_entry[j].mc_data[i]) {
-+				table->validflag |= (1<<i);
-+				break;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
-+{
-+	int result;
-+	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
-+	pp_atomctrl_mc_reg_table *table;
-+	struct tonga_mc_reg_table *ni_table = &smu_data->mc_reg_table;
-+	uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
-+
-+	table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
-+
-+	if (table == NULL)
-+		return -ENOMEM;
-+
-+	/* Program additional LP registers that are no longer programmed by VBIOS */
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP,
-+			cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP,
-+			cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP,
-+			cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP,
-+			cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
-+	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP,
-+			cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
-+
-+	memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
-+
-+	result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
-+
-+	if (!result)
-+		result = tonga_copy_vbios_smc_reg_table(table, ni_table);
-+
-+	if (!result) {
-+		tonga_set_s0_mc_reg_index(ni_table);
-+		result = tonga_set_mc_special_registers(hwmgr, ni_table);
-+	}
-+
-+	if (!result)
-+		tonga_set_valid_flag(ni_table);
-+
-+	kfree(table);
-+
-+	return result;
-+}
-+
-+static bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
-+{
-+	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
-+			CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
-+			? true : false;
-+}
-+
-+static int tonga_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
-+		struct amd_pp_profile *request)
-+{
-+	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)
-+			(hwmgr->smu_backend);
-+	struct SMU72_Discrete_GraphicsLevel *levels =
-+			smu_data->smc_state_table.GraphicsLevel;
-+	uint32_t array = smu_data->smu7_data.dpm_table_start +
-+			offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
-+	uint32_t array_size = sizeof(struct SMU72_Discrete_GraphicsLevel) *
-+			SMU72_MAX_LEVELS_GRAPHICS;
-+	uint32_t i;
-+
-+	for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
-+		levels[i].ActivityLevel =
-+				cpu_to_be16(request->activity_threshold);
-+		levels[i].EnabledForActivity = 1;
-+		levels[i].UpHyst = request->up_hyst;
-+		levels[i].DownHyst = request->down_hyst;
-+	}
-+
-+	return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
-+				array_size, SMC_RAM_END);
-+}
-+
- const struct pp_smumgr_func tonga_smu_funcs = {
- 	.smu_init = &tonga_smu_init,
- 	.smu_fini = &smu7_smu_fini,
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h	2017-12-14 06:39:58.485903616 +0100
-@@ -25,8 +25,26 @@
- #define _TONGA_SMUMGR_H_
- 
- #include "smu72_discrete.h"
--
- #include "smu7_smumgr.h"
-+#include "smu72.h"
-+
-+
-+#define ASICID_IS_TONGA_P(wDID, bRID)	 \
-+	(((wDID == 0x6930) && ((bRID == 0xF0) || (bRID == 0xF1) || (bRID == 0xFF))) \
-+	|| ((wDID == 0x6920) && ((bRID == 0) || (bRID == 1))))
-+
-+struct tonga_pt_defaults {
-+	uint8_t   svi_load_line_en;
-+	uint8_t   svi_load_line_vddC;
-+	uint8_t   tdc_vddc_throttle_release_limit_perc;
-+	uint8_t   tdc_mawt;
-+	uint8_t   tdc_waterfall_ctl;
-+	uint8_t   dte_ambient_temp_base;
-+	uint32_t  display_cac;
-+	uint32_t  bapm_temp_gradient;
-+	uint16_t  bapmti_r[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
-+	uint16_t  bapmti_rc[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
-+};
- 
- struct tonga_mc_reg_entry {
- 	uint32_t mclk_max;
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c	2017-12-14 06:39:58.485903616 +0100
-@@ -53,20 +53,20 @@
- #define smnMP0_FW_INTF                                                                                  0x3010104
- #define smnMP1_PUB_CTRL                                                                                 0x3010b14
- 
--static bool vega10_is_smc_ram_running(struct pp_smumgr *smumgr)
-+static bool vega10_is_smc_ram_running(struct pp_hwmgr *hwmgr)
- {
- 	uint32_t mp1_fw_flags, reg;
- 
- 	reg = soc15_get_register_offset(NBIF_HWID, 0,
- 			mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
- 
--	cgs_write_register(smumgr->device, reg,
-+	cgs_write_register(hwmgr->device, reg,
- 			(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
- 
- 	reg = soc15_get_register_offset(NBIF_HWID, 0,
- 			mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
- 
--	mp1_fw_flags = cgs_read_register(smumgr->device, reg);
-+	mp1_fw_flags = cgs_read_register(hwmgr->device, reg);
- 
- 	if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
- 		return true;
-@@ -80,20 +80,20 @@ static bool vega10_is_smc_ram_running(st
-  * @param    smumgr  the address of the powerplay hardware manager.
-  * @return   TRUE    SMC has responded, FALSE otherwise.
-  */
--static uint32_t vega10_wait_for_response(struct pp_smumgr *smumgr)
-+static uint32_t vega10_wait_for_response(struct pp_hwmgr *hwmgr)
- {
- 	uint32_t reg;
- 
--	if (!vega10_is_smc_ram_running(smumgr))
-+	if (!vega10_is_smc_ram_running(hwmgr))
- 		return -EINVAL;
- 
- 	reg = soc15_get_register_offset(MP1_HWID, 0,
- 			mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
- 
--	smum_wait_for_register_unequal(smumgr, reg,
-+	phm_wait_for_register_unequal(hwmgr, reg,
- 			0, MP1_C2PMSG_90__CONTENT_MASK);
- 
--	return cgs_read_register(smumgr->device, reg);
-+	return cgs_read_register(hwmgr->device, reg);
- }
- 
- /*
-@@ -102,43 +102,43 @@ static uint32_t vega10_wait_for_response
-  * @param    msg the message to send.
-  * @return   Always return 0.
-  */
--int vega10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr,
-+int vega10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
- 		uint16_t msg)
- {
- 	uint32_t reg;
- 
--	if (!vega10_is_smc_ram_running(smumgr))
-+	if (!vega10_is_smc_ram_running(hwmgr))
- 		return -EINVAL;
- 
- 	reg = soc15_get_register_offset(MP1_HWID, 0,
- 			mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
--	cgs_write_register(smumgr->device, reg, msg);
-+	cgs_write_register(hwmgr->device, reg, msg);
- 
- 	return 0;
- }
- 
- /*
-  * Send a message to the SMC, and wait for its response.
-- * @param    smumgr  the address of the powerplay hardware manager.
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-  * @param    msg the message to send.
-  * @return   Always return 0.
-  */
--int vega10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
-+int vega10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
- {
- 	uint32_t reg;
- 
--	if (!vega10_is_smc_ram_running(smumgr))
-+	if (!vega10_is_smc_ram_running(hwmgr))
- 		return -EINVAL;
- 
--	vega10_wait_for_response(smumgr);
-+	vega10_wait_for_response(hwmgr);
- 
- 	reg = soc15_get_register_offset(MP1_HWID, 0,
- 			mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
--	cgs_write_register(smumgr->device, reg, 0);
-+	cgs_write_register(hwmgr->device, reg, 0);
- 
--	vega10_send_msg_to_smc_without_waiting(smumgr, msg);
-+	vega10_send_msg_to_smc_without_waiting(hwmgr, msg);
- 
--	if (vega10_wait_for_response(smumgr) != 1)
-+	if (vega10_wait_for_response(hwmgr) != 1)
- 		pr_err("Failed to send message: 0x%x\n", msg);
- 
- 	return 0;
-@@ -146,32 +146,32 @@ int vega10_send_msg_to_smc(struct pp_smu
- 
- /*
-  * Send a message to the SMC with parameter
-- * @param    smumgr:  the address of the powerplay hardware manager.
-+ * @param    hwmgr:  the address of the powerplay hardware manager.
-  * @param    msg: the message to send.
-  * @param    parameter: the parameter to send
-  * @return   Always return 0.
-  */
--int vega10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
-+int vega10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
- 		uint16_t msg, uint32_t parameter)
- {
- 	uint32_t reg;
- 
--	if (!vega10_is_smc_ram_running(smumgr))
-+	if (!vega10_is_smc_ram_running(hwmgr))
- 		return -EINVAL;
- 
--	vega10_wait_for_response(smumgr);
-+	vega10_wait_for_response(hwmgr);
- 
- 	reg = soc15_get_register_offset(MP1_HWID, 0,
- 			mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
--	cgs_write_register(smumgr->device, reg, 0);
-+	cgs_write_register(hwmgr->device, reg, 0);
- 
- 	reg = soc15_get_register_offset(MP1_HWID, 0,
- 			mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
--	cgs_write_register(smumgr->device, reg, parameter);
-+	cgs_write_register(hwmgr->device, reg, parameter);
- 
--	vega10_send_msg_to_smc_without_waiting(smumgr, msg);
-+	vega10_send_msg_to_smc_without_waiting(hwmgr, msg);
- 
--	if (vega10_wait_for_response(smumgr) != 1)
-+	if (vega10_wait_for_response(hwmgr) != 1)
- 		pr_err("Failed to send message: 0x%x\n", msg);
- 
- 	return 0;
-@@ -180,51 +180,51 @@ int vega10_send_msg_to_smc_with_paramete
- 
- /*
-  * Send a message to the SMC with parameter, do not wait for response
-- * @param    smumgr:  the address of the powerplay hardware manager.
-+ * @param    hwmgr:  the address of the powerplay hardware manager.
-  * @param    msg: the message to send.
-  * @param    parameter: the parameter to send
-  * @return   The response that came from the SMC.
-  */
- int vega10_send_msg_to_smc_with_parameter_without_waiting(
--		struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
-+		struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
- {
- 	uint32_t reg;
- 
- 	reg = soc15_get_register_offset(MP1_HWID, 0,
- 			mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
--	cgs_write_register(smumgr->device, reg, parameter);
-+	cgs_write_register(hwmgr->device, reg, parameter);
- 
--	return vega10_send_msg_to_smc_without_waiting(smumgr, msg);
-+	return vega10_send_msg_to_smc_without_waiting(hwmgr, msg);
- }
- 
- /*
-  * Retrieve an argument from SMC.
-- * @param    smumgr  the address of the powerplay hardware manager.
-+ * @param    hwmgr  the address of the powerplay hardware manager.
-  * @param    arg     pointer to store the argument from SMC.
-  * @return   Always return 0.
-  */
--int vega10_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg)
-+int vega10_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg)
- {
- 	uint32_t reg;
- 
- 	reg = soc15_get_register_offset(MP1_HWID, 0,
- 			mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
- 
--	*arg = cgs_read_register(smumgr->device, reg);
-+	*arg = cgs_read_register(hwmgr->device, reg);
- 
- 	return 0;
- }
- 
- /*
-  * Copy table from SMC into driver FB
-- * @param   smumgr    the address of the SMC manager
-+ * @param   hwmgr    the address of the HW manager
-  * @param   table_id    the driver's table ID to copy from
-  */
--int vega10_copy_table_from_smc(struct pp_smumgr *smumgr,
-+int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
- 		uint8_t *table, int16_t table_id)
- {
- 	struct vega10_smumgr *priv =
--			(struct vega10_smumgr *)(smumgr->backend);
-+			(struct vega10_smumgr *)(hwmgr->smu_backend);
- 
- 	PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
- 			"Invalid SMU Table ID!", return -EINVAL);
-@@ -232,16 +232,16 @@ int vega10_copy_table_from_smc(struct pp
- 			"Invalid SMU Table version!", return -EINVAL);
- 	PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
- 			"Invalid SMU Table Length!", return -EINVAL);
--	PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
-+	PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_SetDriverDramAddrHigh,
- 			priv->smu_tables.entry[table_id].table_addr_high) == 0,
- 			"[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL);
--	PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
-+	PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_SetDriverDramAddrLow,
- 			priv->smu_tables.entry[table_id].table_addr_low) == 0,
- 			"[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
- 			return -EINVAL);
--	PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
-+	PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_TransferTableSmu2Dram,
- 			priv->smu_tables.entry[table_id].table_id) == 0,
- 			"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
-@@ -255,14 +255,14 @@ int vega10_copy_table_from_smc(struct pp
- 
- /*
-  * Copy table from Driver FB into SMC
-- * @param   smumgr    the address of the SMC manager
-+ * @param   hwmgr    the address of the HW manager
-  * @param   table_id    the table to copy from
-  */
--int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
-+int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
- 		uint8_t *table, int16_t table_id)
- {
- 	struct vega10_smumgr *priv =
--			(struct vega10_smumgr *)(smumgr->backend);
-+			(struct vega10_smumgr *)(hwmgr->smu_backend);
- 
- 	PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
- 			"Invalid SMU Table ID!", return -EINVAL);
-@@ -274,17 +274,17 @@ int vega10_copy_table_to_smc(struct pp_s
- 	memcpy(priv->smu_tables.entry[table_id].table, table,
- 			priv->smu_tables.entry[table_id].size);
- 
--	PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
-+	PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_SetDriverDramAddrHigh,
- 			priv->smu_tables.entry[table_id].table_addr_high) == 0,
- 			"[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
- 			return -EINVAL;);
--	PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
-+	PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_SetDriverDramAddrLow,
- 			priv->smu_tables.entry[table_id].table_addr_low) == 0,
- 			"[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
- 			return -EINVAL);
--	PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
-+	PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(hwmgr,
- 			PPSMC_MSG_TransferTableDram2Smu,
- 			priv->smu_tables.entry[table_id].table_id) == 0,
- 			"[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
-@@ -293,87 +293,87 @@ int vega10_copy_table_to_smc(struct pp_s
- 	return 0;
- }
- 
--int vega10_save_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table)
-+int vega10_save_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table)
- {
- 	PP_ASSERT_WITH_CODE(avfs_table,
- 			"No access to SMC AVFS Table",
- 			return -EINVAL);
- 
--	return vega10_copy_table_from_smc(smumgr, avfs_table, AVFSTABLE);
-+	return vega10_copy_table_from_smc(hwmgr, avfs_table, AVFSTABLE);
- }
- 
--int vega10_restore_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table)
-+int vega10_restore_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table)
- {
- 	PP_ASSERT_WITH_CODE(avfs_table,
- 			"No access to SMC AVFS Table",
- 			return -EINVAL);
- 
--	return vega10_copy_table_to_smc(smumgr, avfs_table, AVFSTABLE);
-+	return vega10_copy_table_to_smc(hwmgr, avfs_table, AVFSTABLE);
- }
- 
--int vega10_enable_smc_features(struct pp_smumgr *smumgr,
-+int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
- 		bool enable, uint32_t feature_mask)
- {
- 	int msg = enable ? PPSMC_MSG_EnableSmuFeatures :
- 			PPSMC_MSG_DisableSmuFeatures;
- 
--	return vega10_send_msg_to_smc_with_parameter(smumgr,
-+	return vega10_send_msg_to_smc_with_parameter(hwmgr,
- 			msg, feature_mask);
- }
- 
--int vega10_get_smc_features(struct pp_smumgr *smumgr,
-+int vega10_get_smc_features(struct pp_hwmgr *hwmgr,
- 		uint32_t *features_enabled)
- {
- 	if (features_enabled == NULL)
- 		return -EINVAL;
- 
--	if (!vega10_send_msg_to_smc(smumgr,
-+	if (!vega10_send_msg_to_smc(hwmgr,
- 			PPSMC_MSG_GetEnabledSmuFeatures)) {
--		vega10_read_arg_from_smc(smumgr, features_enabled);
-+		vega10_read_arg_from_smc(hwmgr, features_enabled);
- 		return 0;
- 	}
- 
- 	return -EINVAL;
- }
- 
--int vega10_set_tools_address(struct pp_smumgr *smumgr)
-+int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
- {
- 	struct vega10_smumgr *priv =
--			(struct vega10_smumgr *)(smumgr->backend);
-+			(struct vega10_smumgr *)(hwmgr->smu_backend);
- 
- 	if (priv->smu_tables.entry[TOOLSTABLE].table_addr_high ||
- 			priv->smu_tables.entry[TOOLSTABLE].table_addr_low) {
--		if (!vega10_send_msg_to_smc_with_parameter(smumgr,
-+		if (!vega10_send_msg_to_smc_with_parameter(hwmgr,
- 				PPSMC_MSG_SetToolsDramAddrHigh,
- 				priv->smu_tables.entry[TOOLSTABLE].table_addr_high))
--			vega10_send_msg_to_smc_with_parameter(smumgr,
-+			vega10_send_msg_to_smc_with_parameter(hwmgr,
- 					PPSMC_MSG_SetToolsDramAddrLow,
- 					priv->smu_tables.entry[TOOLSTABLE].table_addr_low);
- 	}
- 	return 0;
- }
- 
--static int vega10_verify_smc_interface(struct pp_smumgr *smumgr)
-+static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr)
- {
- 	uint32_t smc_driver_if_version;
- 	struct cgs_system_info sys_info = {0};
- 	uint32_t dev_id;
- 	uint32_t rev_id;
- 
--	PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc(smumgr,
-+	PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc(hwmgr,
- 			PPSMC_MSG_GetDriverIfVersion),
- 			"Attempt to get SMC IF Version Number Failed!",
- 			return -EINVAL);
--	vega10_read_arg_from_smc(smumgr, &smc_driver_if_version);
-+	vega10_read_arg_from_smc(hwmgr, &smc_driver_if_version);
- 
- 	sys_info.size = sizeof(struct cgs_system_info);
- 	sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;
--	cgs_query_system_info(smumgr->device, &sys_info);
-+	cgs_query_system_info(hwmgr->device, &sys_info);
- 	dev_id = (uint32_t)sys_info.value;
- 
- 	sys_info.size = sizeof(struct cgs_system_info);
- 	sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;
--	cgs_query_system_info(smumgr->device, &sys_info);
-+	cgs_query_system_info(hwmgr->device, &sys_info);
- 	rev_id = (uint32_t)sys_info.value;
- 
- 	if (!((dev_id == 0x687f) &&
-@@ -381,10 +381,8 @@ static int vega10_verify_smc_interface(s
- 		(rev_id == 0xc1) ||
- 		(rev_id == 0xc3)))) {
- 		if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION) {
--			pr_err("Your firmware(0x%x) doesn't match \
--				SMU9_DRIVER_IF_VERSION(0x%x). \
--				Please update your firmware!\n",
--				smc_driver_if_version, SMU9_DRIVER_IF_VERSION);
-+			pr_err("Your firmware(0x%x) doesn't match SMU9_DRIVER_IF_VERSION(0x%x). Please update your firmware!\n",
-+			       smc_driver_if_version, SMU9_DRIVER_IF_VERSION);
- 			return -EINVAL;
- 		}
- 	}
-@@ -392,7 +390,7 @@ static int vega10_verify_smc_interface(s
- 	return 0;
- }
- 
--static int vega10_smu_init(struct pp_smumgr *smumgr)
-+static int vega10_smu_init(struct pp_hwmgr *hwmgr)
- {
- 	struct vega10_smumgr *priv;
- 	uint64_t mc_addr;
-@@ -401,7 +399,7 @@ static int vega10_smu_init(struct pp_smu
- 	int ret;
- 	struct cgs_firmware_info info = {0};
- 
--	ret = cgs_get_firmware_info(smumgr->device,
-+	ret = cgs_get_firmware_info(hwmgr->device,
- 				    smu7_convert_fw_type_to_cgs(UCODE_ID_SMU),
- 				    &info);
- 	if (ret || !info.kptr)
-@@ -412,10 +410,10 @@ static int vega10_smu_init(struct pp_smu
- 	if (!priv)
- 		return -ENOMEM;
- 
--	smumgr->backend = priv;
-+	hwmgr->smu_backend = priv;
- 
- 	/* allocate space for pptable */
--	smu_allocate_memory(smumgr->device,
-+	smu_allocate_memory(hwmgr->device,
- 			sizeof(PPTable_t),
- 			CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
- 			PAGE_SIZE,
-@@ -425,8 +423,8 @@ static int vega10_smu_init(struct pp_smu
- 
- 	PP_ASSERT_WITH_CODE(kaddr,
- 			"[vega10_smu_init] Out of memory for pptable.",
--			kfree(smumgr->backend);
--			cgs_free_gpu_mem(smumgr->device,
-+			kfree(hwmgr->smu_backend);
-+			cgs_free_gpu_mem(hwmgr->device,
- 			(cgs_handle_t)handle);
- 			return -EINVAL);
- 
-@@ -441,7 +439,7 @@ static int vega10_smu_init(struct pp_smu
- 	priv->smu_tables.entry[PPTABLE].handle = handle;
- 
- 	/* allocate space for watermarks table */
--	smu_allocate_memory(smumgr->device,
-+	smu_allocate_memory(hwmgr->device,
- 			sizeof(Watermarks_t),
- 			CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
- 			PAGE_SIZE,
-@@ -451,10 +449,10 @@ static int vega10_smu_init(struct pp_smu
- 
- 	PP_ASSERT_WITH_CODE(kaddr,
- 			"[vega10_smu_init] Out of memory for wmtable.",
--			kfree(smumgr->backend);
--			cgs_free_gpu_mem(smumgr->device,
-+			kfree(hwmgr->smu_backend);
-+			cgs_free_gpu_mem(hwmgr->device,
- 			(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
--			cgs_free_gpu_mem(smumgr->device,
-+			cgs_free_gpu_mem(hwmgr->device,
- 			(cgs_handle_t)handle);
- 			return -EINVAL);
- 
-@@ -469,7 +467,7 @@ static int vega10_smu_init(struct pp_smu
- 	priv->smu_tables.entry[WMTABLE].handle = handle;
- 
- 	/* allocate space for AVFS table */
--	smu_allocate_memory(smumgr->device,
-+	smu_allocate_memory(hwmgr->device,
- 			sizeof(AvfsTable_t),
- 			CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
- 			PAGE_SIZE,
-@@ -479,12 +477,12 @@ static int vega10_smu_init(struct pp_smu
- 
- 	PP_ASSERT_WITH_CODE(kaddr,
- 			"[vega10_smu_init] Out of memory for avfs table.",
--			kfree(smumgr->backend);
--			cgs_free_gpu_mem(smumgr->device,
-+			kfree(hwmgr->smu_backend);
-+			cgs_free_gpu_mem(hwmgr->device,
- 			(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
--			cgs_free_gpu_mem(smumgr->device,
-+			cgs_free_gpu_mem(hwmgr->device,
- 			(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
--			cgs_free_gpu_mem(smumgr->device,
-+			cgs_free_gpu_mem(hwmgr->device,
- 			(cgs_handle_t)handle);
- 			return -EINVAL);
- 
-@@ -500,7 +498,7 @@ static int vega10_smu_init(struct pp_smu
- 
- 	tools_size = 0x19000;
- 	if (tools_size) {
--		smu_allocate_memory(smumgr->device,
-+		smu_allocate_memory(hwmgr->device,
- 				tools_size,
- 				CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
- 				PAGE_SIZE,
-@@ -522,7 +520,7 @@ static int vega10_smu_init(struct pp_smu
- 	}
- 
- 	/* allocate space for AVFS Fuse table */
--	smu_allocate_memory(smumgr->device,
-+	smu_allocate_memory(hwmgr->device,
- 			sizeof(AvfsFuseOverride_t),
- 			CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
- 			PAGE_SIZE,
-@@ -532,16 +530,16 @@ static int vega10_smu_init(struct pp_smu
- 
- 	PP_ASSERT_WITH_CODE(kaddr,
- 			"[vega10_smu_init] Out of memory for avfs fuse table.",
--			kfree(smumgr->backend);
--			cgs_free_gpu_mem(smumgr->device,
-+			kfree(hwmgr->smu_backend);
-+			cgs_free_gpu_mem(hwmgr->device,
- 			(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
--			cgs_free_gpu_mem(smumgr->device,
-+			cgs_free_gpu_mem(hwmgr->device,
- 			(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
--			cgs_free_gpu_mem(smumgr->device,
-+			cgs_free_gpu_mem(hwmgr->device,
- 			(cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle);
--			cgs_free_gpu_mem(smumgr->device,
-+			cgs_free_gpu_mem(hwmgr->device,
- 			(cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle);
--			cgs_free_gpu_mem(smumgr->device,
-+			cgs_free_gpu_mem(hwmgr->device,
- 			(cgs_handle_t)handle);
- 			return -EINVAL);
- 
-@@ -558,36 +556,36 @@ static int vega10_smu_init(struct pp_smu
- 	return 0;
- }
- 
--static int vega10_smu_fini(struct pp_smumgr *smumgr)
-+static int vega10_smu_fini(struct pp_hwmgr *hwmgr)
- {
- 	struct vega10_smumgr *priv =
--			(struct vega10_smumgr *)(smumgr->backend);
-+			(struct vega10_smumgr *)(hwmgr->smu_backend);
- 
- 	if (priv) {
--		cgs_free_gpu_mem(smumgr->device,
-+		cgs_free_gpu_mem(hwmgr->device,
- 				(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
--		cgs_free_gpu_mem(smumgr->device,
-+		cgs_free_gpu_mem(hwmgr->device,
- 				(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
--		cgs_free_gpu_mem(smumgr->device,
-+		cgs_free_gpu_mem(hwmgr->device,
- 				(cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle);
- 		if (priv->smu_tables.entry[TOOLSTABLE].table)
--			cgs_free_gpu_mem(smumgr->device,
-+			cgs_free_gpu_mem(hwmgr->device,
- 					(cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle);
--		cgs_free_gpu_mem(smumgr->device,
-+		cgs_free_gpu_mem(hwmgr->device,
- 				(cgs_handle_t)priv->smu_tables.entry[AVFSFUSETABLE].handle);
--		kfree(smumgr->backend);
--		smumgr->backend = NULL;
-+		kfree(hwmgr->smu_backend);
-+		hwmgr->smu_backend = NULL;
- 	}
- 	return 0;
- }
- 
--static int vega10_start_smu(struct pp_smumgr *smumgr)
-+static int vega10_start_smu(struct pp_hwmgr *hwmgr)
- {
--	PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(smumgr),
-+	PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr),
- 			"Failed to verify SMC interface!",
- 			return -EINVAL);
- 
--	vega10_set_tools_address(smumgr);
-+	vega10_set_tools_address(hwmgr);
- 
- 	return 0;
- }
---- linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h	2017-12-14 06:39:58.486903617 +0100
-@@ -52,19 +52,19 @@ struct vega10_smumgr {
- 	struct smu_table_array            smu_tables;
- };
- 
--int vega10_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg);
--int vega10_copy_table_from_smc(struct pp_smumgr *smumgr,
-+int vega10_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
-+int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
- 		uint8_t *table, int16_t table_id);
--int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
-+int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
- 		uint8_t *table, int16_t table_id);
--int vega10_enable_smc_features(struct pp_smumgr *smumgr,
-+int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
- 		bool enable, uint32_t feature_mask);
--int vega10_get_smc_features(struct pp_smumgr *smumgr,
-+int vega10_get_smc_features(struct pp_hwmgr *hwmgr,
- 		uint32_t *features_enabled);
--int vega10_save_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table);
--int vega10_restore_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table);
-+int vega10_save_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table);
-+int vega10_restore_vft_table(struct pp_hwmgr *hwmgr, uint8_t *avfs_table);
- 
--int vega10_set_tools_address(struct pp_smumgr *smumgr);
-+int vega10_set_tools_address(struct pp_hwmgr *hwmgr);
- 
- #endif
- 
---- linux-4.14/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h	2017-12-14 06:39:58.486903617 +0100
-@@ -13,8 +13,8 @@
- #define TRACE_INCLUDE_FILE gpu_sched_trace
- 
- TRACE_EVENT(amd_sched_job,
--	    TP_PROTO(struct amd_sched_job *sched_job),
--	    TP_ARGS(sched_job),
-+	    TP_PROTO(struct amd_sched_job *sched_job, struct amd_sched_entity *entity),
-+	    TP_ARGS(sched_job, entity),
- 	    TP_STRUCT__entry(
- 			     __field(struct amd_sched_entity *, entity)
- 			     __field(struct dma_fence *, fence)
-@@ -25,12 +25,11 @@ TRACE_EVENT(amd_sched_job,
- 			     ),
- 
- 	    TP_fast_assign(
--			   __entry->entity = sched_job->s_entity;
-+			   __entry->entity = entity;
- 			   __entry->id = sched_job->id;
- 			   __entry->fence = &sched_job->s_fence->finished;
- 			   __entry->name = sched_job->sched->name;
--			   __entry->job_count = kfifo_len(
--				   &sched_job->s_entity->job_queue) / sizeof(sched_job);
-+			   __entry->job_count = spsc_queue_count(&entity->job_queue);
- 			   __entry->hw_job_count = atomic_read(
- 				   &sched_job->sched->hw_rq_count);
- 			   ),
---- linux-4.14/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c	2017-12-14 06:39:58.486903617 +0100
-@@ -28,9 +28,14 @@
- #include <drm/drmP.h>
- #include "gpu_scheduler.h"
- 
-+#include "spsc_queue.h"
-+
- #define CREATE_TRACE_POINTS
- #include "gpu_sched_trace.h"
- 
-+#define to_amd_sched_job(sched_job)		\
-+		container_of((sched_job), struct amd_sched_job, queue_node)
-+
- static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity);
- static void amd_sched_wakeup(struct amd_gpu_scheduler *sched);
- static void amd_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb);
-@@ -121,10 +126,8 @@ amd_sched_rq_select_entity(struct amd_sc
- int amd_sched_entity_init(struct amd_gpu_scheduler *sched,
- 			  struct amd_sched_entity *entity,
- 			  struct amd_sched_rq *rq,
--			  uint32_t jobs)
-+			  uint32_t jobs, atomic_t *guilty)
- {
--	int r;
--
- 	if (!(sched && entity && rq))
- 		return -EINVAL;
- 
-@@ -132,11 +135,11 @@ int amd_sched_entity_init(struct amd_gpu
- 	INIT_LIST_HEAD(&entity->list);
- 	entity->rq = rq;
- 	entity->sched = sched;
-+	entity->guilty = guilty;
- 
-+	spin_lock_init(&entity->rq_lock);
- 	spin_lock_init(&entity->queue_lock);
--	r = kfifo_alloc(&entity->job_queue, jobs * sizeof(void *), GFP_KERNEL);
--	if (r)
--		return r;
-+	spsc_queue_init(&entity->job_queue);
- 
- 	atomic_set(&entity->fence_seq, 0);
- 	entity->fence_context = dma_fence_context_alloc(2);
-@@ -169,7 +172,7 @@ static bool amd_sched_entity_is_initiali
- static bool amd_sched_entity_is_idle(struct amd_sched_entity *entity)
- {
- 	rmb();
--	if (kfifo_is_empty(&entity->job_queue))
-+	if (spsc_queue_peek(&entity->job_queue) == NULL)
- 		return true;
- 
- 	return false;
-@@ -184,7 +187,7 @@ static bool amd_sched_entity_is_idle(str
-  */
- static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity)
- {
--	if (kfifo_is_empty(&entity->job_queue))
-+	if (spsc_queue_peek(&entity->job_queue) == NULL)
- 		return false;
- 
- 	if (ACCESS_ONCE(entity->dependency))
-@@ -204,19 +207,45 @@ static bool amd_sched_entity_is_ready(st
- void amd_sched_entity_fini(struct amd_gpu_scheduler *sched,
- 			   struct amd_sched_entity *entity)
- {
--	struct amd_sched_rq *rq = entity->rq;
-+	int r;
- 
- 	if (!amd_sched_entity_is_initialized(sched, entity))
- 		return;
--
- 	/**
- 	 * The client will not queue more IBs during this fini, consume existing
--	 * queued IBs
-+	 * queued IBs or discard them on SIGKILL
- 	*/
--	wait_event(sched->job_scheduled, amd_sched_entity_is_idle(entity));
-+	if ((current->flags & PF_SIGNALED) && current->exit_code == SIGKILL)
-+		r = -ERESTARTSYS;
-+	else
-+		r = wait_event_killable(sched->job_scheduled,
-+					amd_sched_entity_is_idle(entity));
-+	amd_sched_entity_set_rq(entity, NULL);
-+	if (r) {
-+		struct amd_sched_job *job;
- 
--	amd_sched_rq_remove_entity(rq, entity);
--	kfifo_free(&entity->job_queue);
-+		/* Park the kernel for a moment to make sure it isn't processing
-+		 * our enity.
-+		 */
-+		kthread_park(sched->thread);
-+		kthread_unpark(sched->thread);
-+		if (entity->dependency) {
-+			dma_fence_remove_callback(entity->dependency,
-+						  &entity->cb);
-+			dma_fence_put(entity->dependency);
-+			entity->dependency = NULL;
-+		}
-+
-+		while ((job = to_amd_sched_job(spsc_queue_pop(&entity->job_queue)))) {
-+			struct amd_sched_fence *s_fence = job->s_fence;
-+			amd_sched_fence_scheduled(s_fence);
-+			dma_fence_set_error(&s_fence->finished, -ESRCH);
-+			amd_sched_fence_finished(s_fence);
-+			WARN_ON(s_fence->parent);
-+			dma_fence_put(&s_fence->finished);
-+			sched->ops->free_job(job);
-+		}
-+	}
- }
- 
- static void amd_sched_entity_wakeup(struct dma_fence *f, struct dma_fence_cb *cb)
-@@ -236,6 +265,24 @@ static void amd_sched_entity_clear_dep(s
- 	dma_fence_put(f);
- }
- 
-+void amd_sched_entity_set_rq(struct amd_sched_entity *entity,
-+			     struct amd_sched_rq *rq)
-+{
-+	if (entity->rq == rq)
-+		return;
-+
-+	spin_lock(&entity->rq_lock);
-+
-+	if (entity->rq)
-+		amd_sched_rq_remove_entity(entity->rq, entity);
-+
-+	entity->rq = rq;
-+	if (rq)
-+		amd_sched_rq_add_entity(rq, entity);
-+
-+	spin_unlock(&entity->rq_lock);
-+}
-+
- bool amd_sched_dependency_optimized(struct dma_fence* fence,
- 				    struct amd_sched_entity *entity)
- {
-@@ -296,51 +343,55 @@ static struct amd_sched_job *
- amd_sched_entity_pop_job(struct amd_sched_entity *entity)
- {
- 	struct amd_gpu_scheduler *sched = entity->sched;
--	struct amd_sched_job *sched_job;
-+	struct amd_sched_job *sched_job = to_amd_sched_job(
-+						spsc_queue_peek(&entity->job_queue));
- 
--	if (!kfifo_out_peek(&entity->job_queue, &sched_job, sizeof(sched_job)))
-+	if (!sched_job)
- 		return NULL;
- 
--	while ((entity->dependency = sched->ops->dependency(sched_job)))
-+	while ((entity->dependency = sched->ops->dependency(sched_job, entity)))
- 		if (amd_sched_entity_add_dependency_cb(entity))
- 			return NULL;
- 
-+	/* skip jobs from entity that marked guilty */
-+	if (entity->guilty && atomic_read(entity->guilty))
-+		dma_fence_set_error(&sched_job->s_fence->finished, -ECANCELED);
-+
-+	spsc_queue_pop(&entity->job_queue);
- 	return sched_job;
- }
- 
- /**
-- * Helper to submit a job to the job queue
-+ * Submit a job to the job queue
-  *
-  * @sched_job		The pointer to job required to submit
-  *
-- * Returns true if we could submit the job.
-+ * Returns 0 for success, negative error code otherwise.
-  */
--static bool amd_sched_entity_in(struct amd_sched_job *sched_job)
-+void amd_sched_entity_push_job(struct amd_sched_job *sched_job,
-+			       struct amd_sched_entity *entity)
- {
- 	struct amd_gpu_scheduler *sched = sched_job->sched;
--	struct amd_sched_entity *entity = sched_job->s_entity;
--	bool added, first = false;
-+	bool first = false;
- 
--	spin_lock(&entity->queue_lock);
--	added = kfifo_in(&entity->job_queue, &sched_job,
--			sizeof(sched_job)) == sizeof(sched_job);
-+	trace_amd_sched_job(sched_job, entity);
- 
--	if (added && kfifo_len(&entity->job_queue) == sizeof(sched_job))
--		first = true;
-+	spin_lock(&entity->queue_lock);
-+	first = spsc_queue_push(&entity->job_queue, &sched_job->queue_node);
- 
- 	spin_unlock(&entity->queue_lock);
- 
- 	/* first job wakes up scheduler */
- 	if (first) {
- 		/* Add the entity to the run queue */
-+		spin_lock(&entity->rq_lock);
- 		amd_sched_rq_add_entity(entity->rq, entity);
-+		spin_unlock(&entity->rq_lock);
- 		amd_sched_wakeup(sched);
- 	}
--	return added;
- }
- 
--/* job_finish is called after hw fence signaled, and
-- * the job had already been deleted from ring_mirror_list
-+/* job_finish is called after hw fence signaled
-  */
- static void amd_sched_job_finish(struct work_struct *work)
- {
-@@ -366,6 +417,7 @@ static void amd_sched_job_finish(struct
- 			schedule_delayed_work(&next->work_tdr, sched->timeout);
- 	}
- 	spin_unlock(&sched->job_list_lock);
-+	dma_fence_put(&s_job->s_fence->finished);
- 	sched->ops->free_job(s_job);
- }
- 
-@@ -381,6 +433,9 @@ static void amd_sched_job_begin(struct a
- {
- 	struct amd_gpu_scheduler *sched = s_job->sched;
- 
-+	dma_fence_add_callback(&s_job->s_fence->finished, &s_job->finish_cb,
-+			       amd_sched_job_finish_cb);
-+
- 	spin_lock(&sched->job_list_lock);
- 	list_add_tail(&s_job->node, &sched->ring_mirror_list);
- 	if (sched->timeout != MAX_SCHEDULE_TIMEOUT &&
-@@ -398,9 +453,11 @@ static void amd_sched_job_timedout(struc
- 	job->sched->ops->timedout_job(job);
- }
- 
--void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched)
-+void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_job *bad)
- {
- 	struct amd_sched_job *s_job;
-+	struct amd_sched_entity *entity, *tmp;
-+	int i;;
- 
- 	spin_lock(&sched->job_list_lock);
- 	list_for_each_entry_reverse(s_job, &sched->ring_mirror_list, node) {
-@@ -413,6 +470,30 @@ void amd_sched_hw_job_reset(struct amd_g
- 		}
- 	}
- 	spin_unlock(&sched->job_list_lock);
-+
-+	if (bad && bad->s_priority != AMD_SCHED_PRIORITY_KERNEL) {
-+		atomic_inc(&bad->karma);
-+		/* don't increase @bad's karma if it's from KERNEL RQ,
-+		 * becuase sometimes GPU hang would cause kernel jobs (like VM updating jobs)
-+		 * corrupt but keep in mind that kernel jobs always considered good.
-+		 */
-+		for (i = AMD_SCHED_PRIORITY_MIN; i < AMD_SCHED_PRIORITY_KERNEL; i++ ) {
-+			struct amd_sched_rq *rq = &sched->sched_rq[i];
-+
-+			spin_lock(&rq->lock);
-+			list_for_each_entry_safe(entity, tmp, &rq->entities, list) {
-+				if (bad->s_fence->scheduled.context == entity->fence_context) {
-+				    if (atomic_read(&bad->karma) > bad->sched->hang_limit)
-+						if (entity->guilty)
-+							atomic_set(entity->guilty, 1);
-+					break;
-+				}
-+			}
-+			spin_unlock(&rq->lock);
-+			if (&entity->list != &rq->entities)
-+				break;
-+		}
-+	}
- }
- 
- void amd_sched_job_kickout(struct amd_sched_job *s_job)
-@@ -427,6 +508,7 @@ void amd_sched_job_kickout(struct amd_sc
- void amd_sched_job_recovery(struct amd_gpu_scheduler *sched)
- {
- 	struct amd_sched_job *s_job, *tmp;
-+	bool found_guilty = false;
- 	int r;
- 
- 	spin_lock(&sched->job_list_lock);
-@@ -438,6 +520,15 @@ void amd_sched_job_recovery(struct amd_g
- 	list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) {
- 		struct amd_sched_fence *s_fence = s_job->s_fence;
- 		struct dma_fence *fence;
-+		uint64_t guilty_context;
-+
-+		if (!found_guilty && atomic_read(&s_job->karma) > sched->hang_limit) {
-+			found_guilty = true;
-+			guilty_context = s_job->s_fence->scheduled.context;
-+		}
-+
-+		if (found_guilty && s_job->s_fence->scheduled.context == guilty_context)
-+			dma_fence_set_error(&s_fence->finished, -ECANCELED);
- 
- 		spin_unlock(&sched->job_list_lock);
- 		fence = sched->ops->run_job(s_job);
-@@ -453,7 +544,6 @@ void amd_sched_job_recovery(struct amd_g
- 					  r);
- 			dma_fence_put(fence);
- 		} else {
--			DRM_ERROR("Failed to run job!\n");
- 			amd_sched_process_job(NULL, &s_fence->cb);
- 		}
- 		spin_lock(&sched->job_list_lock);
-@@ -461,24 +551,6 @@ void amd_sched_job_recovery(struct amd_g
- 	spin_unlock(&sched->job_list_lock);
- }
- 
--/**
-- * Submit a job to the job queue
-- *
-- * @sched_job		The pointer to job required to submit
-- *
-- * Returns 0 for success, negative error code otherwise.
-- */
--void amd_sched_entity_push_job(struct amd_sched_job *sched_job)
--{
--	struct amd_sched_entity *entity = sched_job->s_entity;
--
--	trace_amd_sched_job(sched_job);
--	dma_fence_add_callback(&sched_job->s_fence->finished, &sched_job->finish_cb,
--			       amd_sched_job_finish_cb);
--	wait_event(entity->sched->job_scheduled,
--		   amd_sched_entity_in(sched_job));
--}
--
- /* init a sched_job with basic field */
- int amd_sched_job_init(struct amd_sched_job *job,
- 		       struct amd_gpu_scheduler *sched,
-@@ -486,7 +558,7 @@ int amd_sched_job_init(struct amd_sched_
- 		       void *owner)
- {
- 	job->sched = sched;
--	job->s_entity = entity;
-+	job->s_priority = entity->rq - sched->sched_rq;
- 	job->s_fence = amd_sched_fence_create(entity, owner);
- 	if (!job->s_fence)
- 		return -ENOMEM;
-@@ -545,6 +617,7 @@ static void amd_sched_process_job(struct
- 		container_of(cb, struct amd_sched_fence, cb);
- 	struct amd_gpu_scheduler *sched = s_fence->sched;
- 
-+	dma_fence_get(&s_fence->finished);
- 	atomic_dec(&sched->hw_rq_count);
- 	amd_sched_fence_finished(s_fence);
- 
-@@ -567,7 +640,7 @@ static int amd_sched_main(void *param)
- {
- 	struct sched_param sparam = {.sched_priority = 1};
- 	struct amd_gpu_scheduler *sched = (struct amd_gpu_scheduler *)param;
--	int r, count;
-+	int r;
- 
- 	sched_setscheduler(current, SCHED_FIFO, &sparam);
- 
-@@ -596,6 +669,7 @@ static int amd_sched_main(void *param)
- 
- 		fence = sched->ops->run_job(sched_job);
- 		amd_sched_fence_scheduled(s_fence);
-+
- 		if (fence) {
- 			s_fence->parent = dma_fence_get(fence);
- 			r = dma_fence_add_callback(fence, &s_fence->cb,
-@@ -607,13 +681,9 @@ static int amd_sched_main(void *param)
- 					  r);
- 			dma_fence_put(fence);
- 		} else {
--			DRM_ERROR("Failed to run job!\n");
- 			amd_sched_process_job(NULL, &s_fence->cb);
- 		}
- 
--		count = kfifo_out(&entity->job_queue, &sched_job,
--				sizeof(sched_job));
--		WARN_ON(count != sizeof(sched_job));
- 		wake_up(&sched->job_scheduled);
- 	}
- 	return 0;
-@@ -631,13 +701,17 @@ static int amd_sched_main(void *param)
- */
- int amd_sched_init(struct amd_gpu_scheduler *sched,
- 		   const struct amd_sched_backend_ops *ops,
--		   unsigned hw_submission, long timeout, const char *name)
-+		   unsigned hw_submission,
-+		   unsigned hang_limit,
-+		   long timeout,
-+		   const char *name)
- {
- 	int i;
- 	sched->ops = ops;
- 	sched->hw_submission_limit = hw_submission;
- 	sched->name = name;
- 	sched->timeout = timeout;
-+	sched->hang_limit = hang_limit;
- 	for (i = AMD_SCHED_PRIORITY_MIN; i < AMD_SCHED_PRIORITY_MAX; i++)
- 		amd_sched_rq_init(&sched->sched_rq[i]);
- 
---- linux-4.14/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h	2017-12-14 06:39:58.486903617 +0100
-@@ -26,10 +26,24 @@
- 
- #include <linux/kfifo.h>
- #include <linux/dma-fence.h>
-+#include "spsc_queue.h"
- 
- struct amd_gpu_scheduler;
- struct amd_sched_rq;
- 
-+enum amd_sched_priority {
-+	AMD_SCHED_PRIORITY_MIN,
-+	AMD_SCHED_PRIORITY_LOW = AMD_SCHED_PRIORITY_MIN,
-+	AMD_SCHED_PRIORITY_NORMAL,
-+	AMD_SCHED_PRIORITY_HIGH_SW,
-+	AMD_SCHED_PRIORITY_HIGH_HW,
-+	AMD_SCHED_PRIORITY_KERNEL,
-+	AMD_SCHED_PRIORITY_MAX,
-+	AMD_SCHED_PRIORITY_INVALID = -1,
-+	AMD_SCHED_PRIORITY_UNSET = -2
-+};
-+
-+
- /**
-  * A scheduler entity is a wrapper around a job queue or a group
-  * of other entities. Entities take turns emitting jobs from their
-@@ -39,16 +53,18 @@ struct amd_sched_rq;
- struct amd_sched_entity {
- 	struct list_head		list;
- 	struct amd_sched_rq		*rq;
-+	spinlock_t			rq_lock;
- 	struct amd_gpu_scheduler	*sched;
- 
- 	spinlock_t			queue_lock;
--	struct kfifo                    job_queue;
-+	struct spsc_queue	job_queue;
- 
- 	atomic_t			fence_seq;
- 	uint64_t                        fence_context;
- 
- 	struct dma_fence		*dependency;
- 	struct dma_fence_cb		cb;
-+	atomic_t	*guilty; /* points to ctx's guilty */
- };
- 
- /**
-@@ -73,8 +89,8 @@ struct amd_sched_fence {
- };
- 
- struct amd_sched_job {
-+	struct spsc_node queue_node;
- 	struct amd_gpu_scheduler        *sched;
--	struct amd_sched_entity         *s_entity;
- 	struct amd_sched_fence          *s_fence;
- 	struct dma_fence_cb		finish_cb;
- 	struct work_struct		finish_work;
-@@ -82,6 +98,7 @@ struct amd_sched_job {
- 	struct delayed_work		work_tdr;
- 	uint64_t			id;
- 	atomic_t karma;
-+	enum amd_sched_priority s_priority;
- };
- 
- extern const struct dma_fence_ops amd_sched_fence_ops_scheduled;
-@@ -107,19 +124,13 @@ static inline bool amd_sched_invalidate_
-  * these functions should be implemented in driver side
- */
- struct amd_sched_backend_ops {
--	struct dma_fence *(*dependency)(struct amd_sched_job *sched_job);
-+	struct dma_fence *(*dependency)(struct amd_sched_job *sched_job,
-+					struct amd_sched_entity *s_entity);
- 	struct dma_fence *(*run_job)(struct amd_sched_job *sched_job);
- 	void (*timedout_job)(struct amd_sched_job *sched_job);
- 	void (*free_job)(struct amd_sched_job *sched_job);
- };
- 
--enum amd_sched_priority {
--	AMD_SCHED_PRIORITY_MIN,
--	AMD_SCHED_PRIORITY_NORMAL = AMD_SCHED_PRIORITY_MIN,
--	AMD_SCHED_PRIORITY_KERNEL,
--	AMD_SCHED_PRIORITY_MAX
--};
--
- /**
-  * One scheduler is implemented for each hardware ring
- */
-@@ -136,20 +147,24 @@ struct amd_gpu_scheduler {
- 	struct task_struct		*thread;
- 	struct list_head	ring_mirror_list;
- 	spinlock_t			job_list_lock;
-+	int hang_limit;
- };
- 
- int amd_sched_init(struct amd_gpu_scheduler *sched,
- 		   const struct amd_sched_backend_ops *ops,
--		   uint32_t hw_submission, long timeout, const char *name);
-+		   uint32_t hw_submission, unsigned hang_limit, long timeout, const char *name);
- void amd_sched_fini(struct amd_gpu_scheduler *sched);
- 
- int amd_sched_entity_init(struct amd_gpu_scheduler *sched,
- 			  struct amd_sched_entity *entity,
- 			  struct amd_sched_rq *rq,
--			  uint32_t jobs);
-+			  uint32_t jobs, atomic_t* guilty);
- void amd_sched_entity_fini(struct amd_gpu_scheduler *sched,
- 			   struct amd_sched_entity *entity);
--void amd_sched_entity_push_job(struct amd_sched_job *sched_job);
-+void amd_sched_entity_push_job(struct amd_sched_job *sched_job,
-+			       struct amd_sched_entity *entity);
-+void amd_sched_entity_set_rq(struct amd_sched_entity *entity,
-+			     struct amd_sched_rq *rq);
- 
- int amd_sched_fence_slab_init(void);
- void amd_sched_fence_slab_fini(void);
-@@ -162,9 +177,10 @@ int amd_sched_job_init(struct amd_sched_
- 		       struct amd_gpu_scheduler *sched,
- 		       struct amd_sched_entity *entity,
- 		       void *owner);
--void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched);
-+void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_job *job);
- void amd_sched_job_recovery(struct amd_gpu_scheduler *sched);
- bool amd_sched_dependency_optimized(struct dma_fence* fence,
- 				    struct amd_sched_entity *entity);
- void amd_sched_job_kickout(struct amd_sched_job *s_job);
-+
- #endif
---- linux-4.14/drivers/gpu/drm/amd/scheduler/spsc_queue.h.0130~	2017-12-14 06:39:58.486903617 +0100
-+++ linux-4.14/drivers/gpu/drm/amd/scheduler/spsc_queue.h	2017-12-14 06:39:58.486903617 +0100
-@@ -0,0 +1,121 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef AMD_SCHEDULER_SPSC_QUEUE_H_
-+#define AMD_SCHEDULER_SPSC_QUEUE_H_
-+
-+#include <linux/atomic.h>
-+
-+/** SPSC lockless queue */
-+
-+struct spsc_node {
-+
-+	/* Stores spsc_node* */
-+	struct spsc_node *next;
-+};
-+
-+struct spsc_queue {
-+
-+	 struct spsc_node *head;
-+
-+	/* atomic pointer to struct spsc_node* */
-+	atomic_long_t tail;
-+
-+	atomic_t job_count;
-+};
-+
-+static inline void spsc_queue_init(struct spsc_queue *queue)
-+{
-+	queue->head = NULL;
-+	atomic_long_set(&queue->tail, (long)&queue->head);
-+	atomic_set(&queue->job_count, 0);
-+}
-+
-+static inline struct spsc_node *spsc_queue_peek(struct spsc_queue *queue)
-+{
-+	return queue->head;
-+}
-+
-+static inline int spsc_queue_count(struct spsc_queue *queue)
-+{
-+	return atomic_read(&queue->job_count);
-+}
-+
-+static inline bool spsc_queue_push(struct spsc_queue *queue, struct spsc_node *node)
-+{
-+	struct spsc_node **tail;
-+
-+	node->next = NULL;
-+
-+	preempt_disable();
-+
-+	tail = (struct spsc_node **)atomic_long_xchg(&queue->tail, (long)&node->next);
-+	WRITE_ONCE(*tail, node);
-+	atomic_inc(&queue->job_count);
-+
-+	/*
-+	 * In case of first element verify new node will be visible to the consumer
-+	 * thread when we ping the kernel thread that there is new work to do.
-+	 */
-+	smp_wmb();
-+
-+	preempt_enable();
-+
-+	return tail == &queue->head;
-+}
-+
-+
-+static inline struct spsc_node *spsc_queue_pop(struct spsc_queue *queue)
-+{
-+	struct spsc_node *next, *node;
-+
-+	/* Verify reading from memory and not the cache */
-+	smp_rmb();
-+
-+	node = READ_ONCE(queue->head);
-+
-+	if (!node)
-+		return NULL;
-+
-+	next = READ_ONCE(node->next);
-+	WRITE_ONCE(queue->head, next);
-+
-+	if (unlikely(!next)) {
-+		/* slowpath for the last element in the queue */
-+
-+		if (atomic_long_cmpxchg(&queue->tail,
-+				(long)&node->next, (long) &queue->head) != (long)&node->next) {
-+			/* Updating tail failed wait for new next to appear */
-+			do {
-+				smp_rmb();
-+			} while (unlikely(!(queue->head = READ_ONCE(node->next))));
-+		}
-+	}
-+
-+	atomic_dec(&queue->job_count);
-+	return node;
-+}
-+
-+
-+
-+#endif /* AMD_SCHEDULER_SPSC_QUEUE_H_ */
---- linux-4.14/drivers/gpu/drm/arc/arcpgu_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/arc/arcpgu_drv.c	2017-12-14 06:39:58.486903617 +0100
-@@ -18,6 +18,7 @@
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_fb_cma_helper.h>
- #include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drm_atomic_helper.h>
- #include <linux/of_reserved_mem.h>
- 
-@@ -32,7 +33,7 @@ static void arcpgu_fb_output_poll_change
- }
- 
- static const struct drm_mode_config_funcs arcpgu_drm_modecfg_funcs = {
--	.fb_create  = drm_fb_cma_create,
-+	.fb_create  = drm_gem_fb_create,
- 	.output_poll_changed = arcpgu_fb_output_poll_changed,
- 	.atomic_check = drm_atomic_helper_check,
- 	.atomic_commit = drm_atomic_helper_commit,
---- linux-4.14/drivers/gpu/drm/armada/armada_510.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/armada/armada_510.c	2017-12-14 06:39:58.486903617 +0100
-@@ -9,7 +9,6 @@
-  */
- #include <linux/clk.h>
- #include <linux/io.h>
--#include <drm/drmP.h>
- #include <drm/drm_crtc_helper.h>
- #include "armada_crtc.h"
- #include "armada_drm.h"
---- linux-4.14/drivers/gpu/drm/armada/armada_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/armada/armada_drv.c	2017-12-14 06:39:58.486903617 +0100
-@@ -9,7 +9,6 @@
- #include <linux/component.h>
- #include <linux/module.h>
- #include <linux/of_graph.h>
--#include <drm/drmP.h>
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_of.h>
- #include "armada_crtc.h"
-@@ -70,8 +69,6 @@ static struct drm_driver armada_drm_driv
- 	.gem_prime_export	= armada_gem_prime_export,
- 	.gem_prime_import	= armada_gem_prime_import,
- 	.dumb_create		= armada_gem_dumb_create,
--	.dumb_map_offset	= armada_gem_dumb_map_offset,
--	.dumb_destroy		= armada_gem_dumb_destroy,
- 	.gem_vm_ops		= &armada_gem_vm_ops,
- 	.major			= 1,
- 	.minor			= 0,
---- linux-4.14/drivers/gpu/drm/armada/armada_fb.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/armada/armada_fb.c	2017-12-14 06:39:58.486903617 +0100
-@@ -5,7 +5,6 @@
-  * it under the terms of the GNU General Public License version 2 as
-  * published by the Free Software Foundation.
-  */
--#include <drm/drmP.h>
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_fb_helper.h>
- #include "armada_drm.h"
---- linux-4.14/drivers/gpu/drm/armada/armada_fbdev.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/armada/armada_fbdev.c	2017-12-14 06:39:58.486903617 +0100
-@@ -10,7 +10,6 @@
- #include <linux/kernel.h>
- #include <linux/module.h>
- 
--#include <drm/drmP.h>
- #include <drm/drm_fb_helper.h>
- #include "armada_crtc.h"
- #include "armada_drm.h"
---- linux-4.14/drivers/gpu/drm/armada/armada_gem.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/armada/armada_gem.c	2017-12-14 06:39:58.486903617 +0100
-@@ -8,7 +8,6 @@
- #include <linux/dma-buf.h>
- #include <linux/dma-mapping.h>
- #include <linux/shmem_fs.h>
--#include <drm/drmP.h>
- #include "armada_drm.h"
- #include "armada_gem.h"
- #include <drm/armada_drm.h>
-@@ -270,42 +269,6 @@ int armada_gem_dumb_create(struct drm_fi
- 	return ret;
- }
- 
--int armada_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
--	uint32_t handle, uint64_t *offset)
--{
--	struct armada_gem_object *obj;
--	int ret = 0;
--
--	obj = armada_gem_object_lookup(file, handle);
--	if (!obj) {
--		DRM_ERROR("failed to lookup gem object\n");
--		return -EINVAL;
--	}
--
--	/* Don't allow imported objects to be mapped */
--	if (obj->obj.import_attach) {
--		ret = -EINVAL;
--		goto err_unref;
--	}
--
--	ret = drm_gem_create_mmap_offset(&obj->obj);
--	if (ret == 0) {
--		*offset = drm_vma_node_offset_addr(&obj->obj.vma_node);
--		DRM_DEBUG_DRIVER("handle %#x offset %llx\n", handle, *offset);
--	}
--
-- err_unref:
--	drm_gem_object_unreference_unlocked(&obj->obj);
--
--	return ret;
--}
--
--int armada_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
--	uint32_t handle)
--{
--	return drm_gem_handle_delete(file, handle);
--}
--
- /* Private driver gem ioctls */
- int armada_gem_create_ioctl(struct drm_device *dev, void *data,
- 	struct drm_file *file)
---- linux-4.14/drivers/gpu/drm/armada/armada_gem.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/armada/armada_gem.h	2017-12-14 06:39:58.486903617 +0100
-@@ -35,10 +35,6 @@ struct armada_gem_object *armada_gem_all
- 	size_t);
- int armada_gem_dumb_create(struct drm_file *, struct drm_device *,
- 	struct drm_mode_create_dumb *);
--int armada_gem_dumb_map_offset(struct drm_file *, struct drm_device *,
--	uint32_t, uint64_t *);
--int armada_gem_dumb_destroy(struct drm_file *, struct drm_device *,
--	uint32_t);
- struct dma_buf *armada_gem_prime_export(struct drm_device *dev,
- 	struct drm_gem_object *obj, int flags);
- struct drm_gem_object *armada_gem_prime_import(struct drm_device *,
---- linux-4.14/drivers/gpu/drm/armada/armada_trace.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/armada/armada_trace.h	2017-12-14 06:39:58.486903617 +0100
-@@ -63,5 +63,5 @@ TRACE_EVENT(armada_ovl_plane_work,
- 
- /* This part must be outside protection */
- #undef TRACE_INCLUDE_PATH
--#define TRACE_INCLUDE_PATH .
-+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/armada
- #include <trace/define_trace.h>
---- linux-4.14/drivers/gpu/drm/armada/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/armada/Makefile	2017-12-14 06:39:58.487903618 +0100
-@@ -5,5 +5,3 @@ armada-y	+= armada_510.o
- armada-$(CONFIG_DEBUG_FS) += armada_debugfs.o
- 
- obj-$(CONFIG_DRM_ARMADA) := armada.o
--
--CFLAGS_armada_trace.o := -I$(src)
---- linux-4.14/drivers/gpu/drm/arm/hdlcd_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/arm/hdlcd_drv.c	2017-12-14 06:39:58.487903618 +0100
-@@ -25,6 +25,7 @@
- #include <drm/drm_fb_helper.h>
- #include <drm/drm_fb_cma_helper.h>
- #include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drm_of.h>
- 
- #include "hdlcd_drv.h"
-@@ -106,7 +107,7 @@ static void hdlcd_fb_output_poll_changed
- }
- 
- static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
--	.fb_create = drm_fb_cma_create,
-+	.fb_create = drm_gem_fb_create,
- 	.output_poll_changed = hdlcd_fb_output_poll_changed,
- 	.atomic_check = drm_atomic_helper_check,
- 	.atomic_commit = drm_atomic_helper_commit,
---- linux-4.14/drivers/gpu/drm/arm/malidp_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/arm/malidp_drv.c	2017-12-14 06:39:58.487903618 +0100
-@@ -26,6 +26,7 @@
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_fb_cma_helper.h>
- #include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drm_of.h>
- 
- #include "malidp_drv.h"
-@@ -249,7 +250,7 @@ static const struct drm_mode_config_help
- };
- 
- static const struct drm_mode_config_funcs malidp_mode_config_funcs = {
--	.fb_create = drm_fb_cma_create,
-+	.fb_create = drm_gem_fb_create,
- 	.output_poll_changed = malidp_output_poll_changed,
- 	.atomic_check = drm_atomic_helper_check,
- 	.atomic_commit = drm_atomic_helper_commit,
---- linux-4.14/drivers/gpu/drm/ast/ast_mode.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/ast/ast_mode.c	2017-12-14 06:39:58.487903618 +0100
-@@ -713,7 +713,7 @@ static struct drm_encoder *ast_best_sing
- 	int enc_id = connector->encoder_ids[0];
- 	/* pick the encoder ids */
- 	if (enc_id)
--		return drm_encoder_find(connector->dev, enc_id);
-+		return drm_encoder_find(connector->dev, NULL, enc_id);
- 	return NULL;
- }
- 
---- linux-4.14/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c	2017-12-14 06:39:58.487903618 +0100
-@@ -458,7 +458,7 @@ static irqreturn_t atmel_hlcdc_dc_irq_ha
- static struct drm_framebuffer *atmel_hlcdc_fb_create(struct drm_device *dev,
- 		struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
- {
--	return drm_fb_cma_create(dev, file_priv, mode_cmd);
-+	return drm_gem_fb_create(dev, file_priv, mode_cmd);
- }
- 
- static void atmel_hlcdc_fb_output_poll_changed(struct drm_device *dev)
---- linux-4.14/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h	2017-12-14 06:39:58.487903618 +0100
-@@ -34,6 +34,7 @@
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_fb_cma_helper.h>
- #include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drm_panel.h>
- #include <drm/drm_plane_helper.h>
- #include <drm/drmP.h>
---- linux-4.14/drivers/gpu/drm/bochs/bochs_kms.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/bochs/bochs_kms.c	2017-12-14 06:39:58.487903618 +0100
-@@ -213,7 +213,7 @@ bochs_connector_best_encoder(struct drm_
- 	int enc_id = connector->encoder_ids[0];
- 	/* pick the encoder ids */
- 	if (enc_id)
--		return drm_encoder_find(connector->dev, enc_id);
-+		return drm_encoder_find(connector->dev, NULL, enc_id);
- 	return NULL;
- }
- 
---- linux-4.14/drivers/gpu/drm/bridge/adv7511/adv7511_audio.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/bridge/adv7511/adv7511_audio.c	2017-12-14 06:39:58.487903618 +0100
-@@ -210,7 +210,7 @@ static const struct hdmi_codec_ops adv75
- 	.get_dai_id	= adv7511_hdmi_i2s_get_dai_id,
- };
- 
--static struct hdmi_codec_pdata codec_data = {
-+static const struct hdmi_codec_pdata codec_data = {
- 	.ops = &adv7511_codec_ops,
- 	.max_i2s_channels = 2,
- 	.i2s = 1,
---- linux-4.14/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c.0130~	2017-12-14 06:39:58.487903618 +0100
-+++ linux-4.14/drivers/gpu/drm/bridge/adv7511/adv7511_cec.c	2017-12-14 06:39:58.487903618 +0100
-@@ -0,0 +1,337 @@
-+/*
-+ * adv7511_cec.c - Analog Devices ADV7511/33 cec driver
-+ *
-+ * Copyright 2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
-+ *
-+ * This program is free software; you may redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
-+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-+ * SOFTWARE.
-+ *
-+ */
-+
-+#include <linux/device.h>
-+#include <linux/module.h>
-+#include <linux/of_device.h>
-+#include <linux/slab.h>
-+#include <linux/clk.h>
-+
-+#include <media/cec.h>
-+
-+#include "adv7511.h"
-+
-+#define ADV7511_INT1_CEC_MASK \
-+	(ADV7511_INT1_CEC_TX_READY | ADV7511_INT1_CEC_TX_ARBIT_LOST | \
-+	 ADV7511_INT1_CEC_TX_RETRY_TIMEOUT | ADV7511_INT1_CEC_RX_READY1)
-+
-+static void adv_cec_tx_raw_status(struct adv7511 *adv7511, u8 tx_raw_status)
-+{
-+	unsigned int offset = adv7511->type == ADV7533 ?
-+					ADV7533_REG_CEC_OFFSET : 0;
-+	unsigned int val;
-+
-+	if (regmap_read(adv7511->regmap_cec,
-+			ADV7511_REG_CEC_TX_ENABLE + offset, &val))
-+		return;
-+
-+	if ((val & 0x01) == 0)
-+		return;
-+
-+	if (tx_raw_status & ADV7511_INT1_CEC_TX_ARBIT_LOST) {
-+		cec_transmit_attempt_done(adv7511->cec_adap,
-+					  CEC_TX_STATUS_ARB_LOST);
-+		return;
-+	}
-+	if (tx_raw_status & ADV7511_INT1_CEC_TX_RETRY_TIMEOUT) {
-+		u8 status;
-+		u8 err_cnt = 0;
-+		u8 nack_cnt = 0;
-+		u8 low_drive_cnt = 0;
-+		unsigned int cnt;
-+
-+		/*
-+		 * We set this status bit since this hardware performs
-+		 * retransmissions.
-+		 */
-+		status = CEC_TX_STATUS_MAX_RETRIES;
-+		if (regmap_read(adv7511->regmap_cec,
-+			    ADV7511_REG_CEC_TX_LOW_DRV_CNT + offset, &cnt)) {
-+			err_cnt = 1;
-+			status |= CEC_TX_STATUS_ERROR;
-+		} else {
-+			nack_cnt = cnt & 0xf;
-+			if (nack_cnt)
-+				status |= CEC_TX_STATUS_NACK;
-+			low_drive_cnt = cnt >> 4;
-+			if (low_drive_cnt)
-+				status |= CEC_TX_STATUS_LOW_DRIVE;
-+		}
-+		cec_transmit_done(adv7511->cec_adap, status,
-+				  0, nack_cnt, low_drive_cnt, err_cnt);
-+		return;
-+	}
-+	if (tx_raw_status & ADV7511_INT1_CEC_TX_READY) {
-+		cec_transmit_attempt_done(adv7511->cec_adap, CEC_TX_STATUS_OK);
-+		return;
-+	}
-+}
-+
-+void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1)
-+{
-+	unsigned int offset = adv7511->type == ADV7533 ?
-+					ADV7533_REG_CEC_OFFSET : 0;
-+	const u32 irq_tx_mask = ADV7511_INT1_CEC_TX_READY |
-+				ADV7511_INT1_CEC_TX_ARBIT_LOST |
-+				ADV7511_INT1_CEC_TX_RETRY_TIMEOUT;
-+	struct cec_msg msg = {};
-+	unsigned int len;
-+	unsigned int val;
-+	u8 i;
-+
-+	if (irq1 & irq_tx_mask)
-+		adv_cec_tx_raw_status(adv7511, irq1);
-+
-+	if (!(irq1 & ADV7511_INT1_CEC_RX_READY1))
-+		return;
-+
-+	if (regmap_read(adv7511->regmap_cec,
-+			ADV7511_REG_CEC_RX_FRAME_LEN + offset, &len))
-+		return;
-+
-+	msg.len = len & 0x1f;
-+
-+	if (msg.len > 16)
-+		msg.len = 16;
-+
-+	if (!msg.len)
-+		return;
-+
-+	for (i = 0; i < msg.len; i++) {
-+		regmap_read(adv7511->regmap_cec,
-+			    i + ADV7511_REG_CEC_RX_FRAME_HDR + offset, &val);
-+		msg.msg[i] = val;
-+	}
-+
-+	/* toggle to re-enable rx 1 */
-+	regmap_write(adv7511->regmap_cec,
-+		     ADV7511_REG_CEC_RX_BUFFERS + offset, 1);
-+	regmap_write(adv7511->regmap_cec,
-+		     ADV7511_REG_CEC_RX_BUFFERS + offset, 0);
-+	cec_received_msg(adv7511->cec_adap, &msg);
-+}
-+
-+static int adv7511_cec_adap_enable(struct cec_adapter *adap, bool enable)
-+{
-+	struct adv7511 *adv7511 = cec_get_drvdata(adap);
-+	unsigned int offset = adv7511->type == ADV7533 ?
-+					ADV7533_REG_CEC_OFFSET : 0;
-+
-+	if (adv7511->i2c_cec == NULL)
-+		return -EIO;
-+
-+	if (!adv7511->cec_enabled_adap && enable) {
-+		/* power up cec section */
-+		regmap_update_bits(adv7511->regmap_cec,
-+				   ADV7511_REG_CEC_CLK_DIV + offset,
-+				   0x03, 0x01);
-+		/* legacy mode and clear all rx buffers */
-+		regmap_write(adv7511->regmap_cec,
-+			     ADV7511_REG_CEC_RX_BUFFERS + offset, 0x07);
-+		regmap_write(adv7511->regmap_cec,
-+			     ADV7511_REG_CEC_RX_BUFFERS + offset, 0);
-+		/* initially disable tx */
-+		regmap_update_bits(adv7511->regmap_cec,
-+				   ADV7511_REG_CEC_TX_ENABLE + offset, 1, 0);
-+		/* enabled irqs: */
-+		/* tx: ready */
-+		/* tx: arbitration lost */
-+		/* tx: retry timeout */
-+		/* rx: ready 1 */
-+		regmap_update_bits(adv7511->regmap,
-+				   ADV7511_REG_INT_ENABLE(1), 0x3f,
-+				   ADV7511_INT1_CEC_MASK);
-+	} else if (adv7511->cec_enabled_adap && !enable) {
-+		regmap_update_bits(adv7511->regmap,
-+				   ADV7511_REG_INT_ENABLE(1), 0x3f, 0);
-+		/* disable address mask 1-3 */
-+		regmap_update_bits(adv7511->regmap_cec,
-+				   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
-+				   0x70, 0x00);
-+		/* power down cec section */
-+		regmap_update_bits(adv7511->regmap_cec,
-+				   ADV7511_REG_CEC_CLK_DIV + offset,
-+				   0x03, 0x00);
-+		adv7511->cec_valid_addrs = 0;
-+	}
-+	adv7511->cec_enabled_adap = enable;
-+	return 0;
-+}
-+
-+static int adv7511_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
-+{
-+	struct adv7511 *adv7511 = cec_get_drvdata(adap);
-+	unsigned int offset = adv7511->type == ADV7533 ?
-+					ADV7533_REG_CEC_OFFSET : 0;
-+	unsigned int i, free_idx = ADV7511_MAX_ADDRS;
-+
-+	if (!adv7511->cec_enabled_adap)
-+		return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
-+
-+	if (addr == CEC_LOG_ADDR_INVALID) {
-+		regmap_update_bits(adv7511->regmap_cec,
-+				   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
-+				   0x70, 0);
-+		adv7511->cec_valid_addrs = 0;
-+		return 0;
-+	}
-+
-+	for (i = 0; i < ADV7511_MAX_ADDRS; i++) {
-+		bool is_valid = adv7511->cec_valid_addrs & (1 << i);
-+
-+		if (free_idx == ADV7511_MAX_ADDRS && !is_valid)
-+			free_idx = i;
-+		if (is_valid && adv7511->cec_addr[i] == addr)
-+			return 0;
-+	}
-+	if (i == ADV7511_MAX_ADDRS) {
-+		i = free_idx;
-+		if (i == ADV7511_MAX_ADDRS)
-+			return -ENXIO;
-+	}
-+	adv7511->cec_addr[i] = addr;
-+	adv7511->cec_valid_addrs |= 1 << i;
-+
-+	switch (i) {
-+	case 0:
-+		/* enable address mask 0 */
-+		regmap_update_bits(adv7511->regmap_cec,
-+				   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
-+				   0x10, 0x10);
-+		/* set address for mask 0 */
-+		regmap_update_bits(adv7511->regmap_cec,
-+				   ADV7511_REG_CEC_LOG_ADDR_0_1 + offset,
-+				   0x0f, addr);
-+		break;
-+	case 1:
-+		/* enable address mask 1 */
-+		regmap_update_bits(adv7511->regmap_cec,
-+				   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
-+				   0x20, 0x20);
-+		/* set address for mask 1 */
-+		regmap_update_bits(adv7511->regmap_cec,
-+				   ADV7511_REG_CEC_LOG_ADDR_0_1 + offset,
-+				   0xf0, addr << 4);
-+		break;
-+	case 2:
-+		/* enable address mask 2 */
-+		regmap_update_bits(adv7511->regmap_cec,
-+				   ADV7511_REG_CEC_LOG_ADDR_MASK + offset,
-+				   0x40, 0x40);
-+		/* set address for mask 1 */
-+		regmap_update_bits(adv7511->regmap_cec,
-+				   ADV7511_REG_CEC_LOG_ADDR_2 + offset,
-+				   0x0f, addr);
-+		break;
-+	}
-+	return 0;
-+}
-+
-+static int adv7511_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
-+				     u32 signal_free_time, struct cec_msg *msg)
-+{
-+	struct adv7511 *adv7511 = cec_get_drvdata(adap);
-+	unsigned int offset = adv7511->type == ADV7533 ?
-+					ADV7533_REG_CEC_OFFSET : 0;
-+	u8 len = msg->len;
-+	unsigned int i;
-+
-+	/*
-+	 * The number of retries is the number of attempts - 1, but retry
-+	 * at least once. It's not clear if a value of 0 is allowed, so
-+	 * let's do at least one retry.
-+	 */
-+	regmap_update_bits(adv7511->regmap_cec,
-+			   ADV7511_REG_CEC_TX_RETRY + offset,
-+			   0x70, max(1, attempts - 1) << 4);
-+
-+	/* blocking, clear cec tx irq status */
-+	regmap_update_bits(adv7511->regmap, ADV7511_REG_INT(1), 0x38, 0x38);
-+
-+	/* write data */
-+	for (i = 0; i < len; i++)
-+		regmap_write(adv7511->regmap_cec,
-+			     i + ADV7511_REG_CEC_TX_FRAME_HDR + offset,
-+			     msg->msg[i]);
-+
-+	/* set length (data + header) */
-+	regmap_write(adv7511->regmap_cec,
-+		     ADV7511_REG_CEC_TX_FRAME_LEN + offset, len);
-+	/* start transmit, enable tx */
-+	regmap_write(adv7511->regmap_cec,
-+		     ADV7511_REG_CEC_TX_ENABLE + offset, 0x01);
-+	return 0;
-+}
-+
-+static const struct cec_adap_ops adv7511_cec_adap_ops = {
-+	.adap_enable = adv7511_cec_adap_enable,
-+	.adap_log_addr = adv7511_cec_adap_log_addr,
-+	.adap_transmit = adv7511_cec_adap_transmit,
-+};
-+
-+static int adv7511_cec_parse_dt(struct device *dev, struct adv7511 *adv7511)
-+{
-+	adv7511->cec_clk = devm_clk_get(dev, "cec");
-+	if (IS_ERR(adv7511->cec_clk)) {
-+		int ret = PTR_ERR(adv7511->cec_clk);
-+
-+		adv7511->cec_clk = NULL;
-+		return ret;
-+	}
-+	clk_prepare_enable(adv7511->cec_clk);
-+	adv7511->cec_clk_freq = clk_get_rate(adv7511->cec_clk);
-+	return 0;
-+}
-+
-+int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511,
-+		     unsigned int offset)
-+{
-+	int ret = adv7511_cec_parse_dt(dev, adv7511);
-+
-+	if (ret)
-+		return ret;
-+
-+	adv7511->cec_adap = cec_allocate_adapter(&adv7511_cec_adap_ops,
-+		adv7511, dev_name(dev), CEC_CAP_DEFAULTS, ADV7511_MAX_ADDRS);
-+	if (IS_ERR(adv7511->cec_adap))
-+		return PTR_ERR(adv7511->cec_adap);
-+
-+	regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset, 0);
-+	/* cec soft reset */
-+	regmap_write(adv7511->regmap_cec,
-+		     ADV7511_REG_CEC_SOFT_RESET + offset, 0x01);
-+	regmap_write(adv7511->regmap_cec,
-+		     ADV7511_REG_CEC_SOFT_RESET + offset, 0x00);
-+
-+	/* legacy mode */
-+	regmap_write(adv7511->regmap_cec,
-+		     ADV7511_REG_CEC_RX_BUFFERS + offset, 0x00);
-+
-+	regmap_write(adv7511->regmap_cec,
-+		     ADV7511_REG_CEC_CLK_DIV + offset,
-+		     ((adv7511->cec_clk_freq / 750000) - 1) << 2);
-+
-+	ret = cec_register_adapter(adv7511->cec_adap, dev);
-+	if (ret) {
-+		cec_delete_adapter(adv7511->cec_adap);
-+		adv7511->cec_adap = NULL;
-+	}
-+	return ret;
-+}
---- linux-4.14/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c	2017-12-14 06:39:58.487903618 +0100
-@@ -11,12 +11,15 @@
- #include <linux/module.h>
- #include <linux/of_device.h>
- #include <linux/slab.h>
-+#include <linux/clk.h>
- 
- #include <drm/drmP.h>
- #include <drm/drm_atomic.h>
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_edid.h>
- 
-+#include <media/cec.h>
-+
- #include "adv7511.h"
- 
- /* ADI recommended values for proper operation. */
-@@ -199,17 +202,14 @@ static const uint16_t adv7511_csc_ycbcr_
- 
- static void adv7511_set_config_csc(struct adv7511 *adv7511,
- 				   struct drm_connector *connector,
--				   bool rgb)
-+				   bool rgb, bool hdmi_mode)
- {
- 	struct adv7511_video_config config;
- 	bool output_format_422, output_format_ycbcr;
- 	unsigned int mode;
- 	uint8_t infoframe[17];
- 
--	if (adv7511->edid)
--		config.hdmi_mode = drm_detect_hdmi_monitor(adv7511->edid);
--	else
--		config.hdmi_mode = false;
-+	config.hdmi_mode = hdmi_mode;
- 
- 	hdmi_avi_infoframe_init(&config.avi_infoframe);
- 
-@@ -339,8 +339,10 @@ static void __adv7511_power_on(struct ad
- 		 */
- 		regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(0),
- 			     ADV7511_INT0_EDID_READY | ADV7511_INT0_HPD);
--		regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(1),
--			     ADV7511_INT1_DDC_ERROR);
-+		regmap_update_bits(adv7511->regmap,
-+				   ADV7511_REG_INT_ENABLE(1),
-+				   ADV7511_INT1_DDC_ERROR,
-+				   ADV7511_INT1_DDC_ERROR);
- 	}
- 
- 	/*
-@@ -376,6 +378,9 @@ static void __adv7511_power_off(struct a
- 	regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER,
- 			   ADV7511_POWER_POWER_DOWN,
- 			   ADV7511_POWER_POWER_DOWN);
-+	regmap_update_bits(adv7511->regmap,
-+			   ADV7511_REG_INT_ENABLE(1),
-+			   ADV7511_INT1_DDC_ERROR, 0);
- 	regcache_mark_dirty(adv7511->regmap);
- }
- 
-@@ -426,6 +431,8 @@ static void adv7511_hpd_work(struct work
- 
- 	if (adv7511->connector.status != status) {
- 		adv7511->connector.status = status;
-+		if (status == connector_status_disconnected)
-+			cec_phys_addr_invalidate(adv7511->cec_adap);
- 		drm_kms_helper_hotplug_event(adv7511->connector.dev);
- 	}
- }
-@@ -456,6 +463,10 @@ static int adv7511_irq_process(struct ad
- 			wake_up_all(&adv7511->wq);
- 	}
- 
-+#ifdef CONFIG_DRM_I2C_ADV7511_CEC
-+	adv7511_cec_irq_process(adv7511, irq1);
-+#endif
-+
- 	return 0;
- }
- 
-@@ -589,15 +600,16 @@ static int adv7511_get_modes(struct adv7
- 	if (!adv7511->powered)
- 		__adv7511_power_off(adv7511);
- 
--	kfree(adv7511->edid);
--	adv7511->edid = edid;
--	if (!edid)
--		return 0;
- 
- 	drm_mode_connector_update_edid_property(connector, edid);
- 	count = drm_add_edid_modes(connector, edid);
- 
--	adv7511_set_config_csc(adv7511, connector, adv7511->rgb);
-+	adv7511_set_config_csc(adv7511, connector, adv7511->rgb,
-+			       drm_detect_hdmi_monitor(edid));
-+
-+	kfree(edid);
-+
-+	cec_s_phys_addr_from_edid(adv7511->cec_adap, edid);
- 
- 	return count;
- }
-@@ -833,7 +845,11 @@ static int adv7511_bridge_attach(struct
- 		return -ENODEV;
- 	}
- 
--	adv->connector.polled = DRM_CONNECTOR_POLL_HPD;
-+	if (adv->i2c_main->irq)
-+		adv->connector.polled = DRM_CONNECTOR_POLL_HPD;
-+	else
-+		adv->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
-+				DRM_CONNECTOR_POLL_DISCONNECT;
- 
- 	ret = drm_connector_init(bridge->dev, &adv->connector,
- 				 &adv7511_connector_funcs,
-@@ -919,6 +935,65 @@ static void adv7511_uninit_regulators(st
- 	regulator_bulk_disable(adv->num_supplies, adv->supplies);
- }
- 
-+static bool adv7511_cec_register_volatile(struct device *dev, unsigned int reg)
-+{
-+	struct i2c_client *i2c = to_i2c_client(dev);
-+	struct adv7511 *adv7511 = i2c_get_clientdata(i2c);
-+
-+	if (adv7511->type == ADV7533)
-+		reg -= ADV7533_REG_CEC_OFFSET;
-+
-+	switch (reg) {
-+	case ADV7511_REG_CEC_RX_FRAME_HDR:
-+	case ADV7511_REG_CEC_RX_FRAME_DATA0...
-+		ADV7511_REG_CEC_RX_FRAME_DATA0 + 14:
-+	case ADV7511_REG_CEC_RX_FRAME_LEN:
-+	case ADV7511_REG_CEC_RX_BUFFERS:
-+	case ADV7511_REG_CEC_TX_LOW_DRV_CNT:
-+		return true;
-+	}
-+
-+	return false;
-+}
-+
-+static const struct regmap_config adv7511_cec_regmap_config = {
-+	.reg_bits = 8,
-+	.val_bits = 8,
-+
-+	.max_register = 0xff,
-+	.cache_type = REGCACHE_RBTREE,
-+	.volatile_reg = adv7511_cec_register_volatile,
-+};
-+
-+static int adv7511_init_cec_regmap(struct adv7511 *adv)
-+{
-+	int ret;
-+
-+	adv->i2c_cec = i2c_new_dummy(adv->i2c_main->adapter,
-+				     adv->i2c_main->addr - 1);
-+	if (!adv->i2c_cec)
-+		return -ENOMEM;
-+	i2c_set_clientdata(adv->i2c_cec, adv);
-+
-+	adv->regmap_cec = devm_regmap_init_i2c(adv->i2c_cec,
-+					&adv7511_cec_regmap_config);
-+	if (IS_ERR(adv->regmap_cec)) {
-+		ret = PTR_ERR(adv->regmap_cec);
-+		goto err;
-+	}
-+
-+	if (adv->type == ADV7533) {
-+		ret = adv7533_patch_cec_registers(adv);
-+		if (ret)
-+			goto err;
-+	}
-+
-+	return 0;
-+err:
-+	i2c_unregister_device(adv->i2c_cec);
-+	return ret;
-+}
-+
- static int adv7511_parse_dt(struct device_node *np,
- 			    struct adv7511_link_config *config)
- {
-@@ -1009,6 +1084,7 @@ static int adv7511_probe(struct i2c_clie
- 	struct device *dev = &i2c->dev;
- 	unsigned int main_i2c_addr = i2c->addr << 1;
- 	unsigned int edid_i2c_addr = main_i2c_addr + 4;
-+	unsigned int offset;
- 	unsigned int val;
- 	int ret;
- 
-@@ -1092,11 +1168,9 @@ static int adv7511_probe(struct i2c_clie
- 		goto uninit_regulators;
- 	}
- 
--	if (adv7511->type == ADV7533) {
--		ret = adv7533_init_cec(adv7511);
--		if (ret)
--			goto err_i2c_unregister_edid;
--	}
-+	ret = adv7511_init_cec_regmap(adv7511);
-+	if (ret)
-+		goto err_i2c_unregister_edid;
- 
- 	INIT_WORK(&adv7511->hpd_work, adv7511_hpd_work);
- 
-@@ -1111,10 +1185,6 @@ static int adv7511_probe(struct i2c_clie
- 			goto err_unregister_cec;
- 	}
- 
--	/* CEC is unused for now */
--	regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL,
--		     ADV7511_CEC_CTRL_POWER_DOWN);
--
- 	adv7511_power_off(adv7511);
- 
- 	i2c_set_clientdata(i2c, adv7511);
-@@ -1129,10 +1199,23 @@ static int adv7511_probe(struct i2c_clie
- 
- 	adv7511_audio_init(dev, adv7511);
- 
-+	offset = adv7511->type == ADV7533 ? ADV7533_REG_CEC_OFFSET : 0;
-+
-+#ifdef CONFIG_DRM_I2C_ADV7511_CEC
-+	ret = adv7511_cec_init(dev, adv7511, offset);
-+	if (ret)
-+		goto err_unregister_cec;
-+#else
-+	regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL + offset,
-+		     ADV7511_CEC_CTRL_POWER_DOWN);
-+#endif
-+
- 	return 0;
- 
- err_unregister_cec:
--	adv7533_uninit_cec(adv7511);
-+	i2c_unregister_device(adv7511->i2c_cec);
-+	if (adv7511->cec_clk)
-+		clk_disable_unprepare(adv7511->cec_clk);
- err_i2c_unregister_edid:
- 	i2c_unregister_device(adv7511->i2c_edid);
- uninit_regulators:
-@@ -1145,10 +1228,11 @@ static int adv7511_remove(struct i2c_cli
- {
- 	struct adv7511 *adv7511 = i2c_get_clientdata(i2c);
- 
--	if (adv7511->type == ADV7533) {
-+	if (adv7511->type == ADV7533)
- 		adv7533_detach_dsi(adv7511);
--		adv7533_uninit_cec(adv7511);
--	}
-+	i2c_unregister_device(adv7511->i2c_cec);
-+	if (adv7511->cec_clk)
-+		clk_disable_unprepare(adv7511->cec_clk);
- 
- 	adv7511_uninit_regulators(adv7511);
- 
-@@ -1156,9 +1240,9 @@ static int adv7511_remove(struct i2c_cli
- 
- 	adv7511_audio_exit(adv7511);
- 
--	i2c_unregister_device(adv7511->i2c_edid);
-+	cec_unregister_adapter(adv7511->cec_adap);
- 
--	kfree(adv7511->edid);
-+	i2c_unregister_device(adv7511->i2c_edid);
- 
- 	return 0;
- }
---- linux-4.14/drivers/gpu/drm/bridge/adv7511/adv7511.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/bridge/adv7511/adv7511.h	2017-12-14 06:39:58.488903618 +0100
-@@ -195,6 +195,25 @@
- #define ADV7511_PACKET_GM(x)	    ADV7511_PACKET(5, x)
- #define ADV7511_PACKET_SPARE(x)	    ADV7511_PACKET(6, x)
- 
-+#define ADV7511_REG_CEC_TX_FRAME_HDR	0x00
-+#define ADV7511_REG_CEC_TX_FRAME_DATA0	0x01
-+#define ADV7511_REG_CEC_TX_FRAME_LEN	0x10
-+#define ADV7511_REG_CEC_TX_ENABLE	0x11
-+#define ADV7511_REG_CEC_TX_RETRY	0x12
-+#define ADV7511_REG_CEC_TX_LOW_DRV_CNT	0x14
-+#define ADV7511_REG_CEC_RX_FRAME_HDR	0x15
-+#define ADV7511_REG_CEC_RX_FRAME_DATA0	0x16
-+#define ADV7511_REG_CEC_RX_FRAME_LEN	0x25
-+#define ADV7511_REG_CEC_RX_ENABLE	0x26
-+#define ADV7511_REG_CEC_RX_BUFFERS	0x4a
-+#define ADV7511_REG_CEC_LOG_ADDR_MASK	0x4b
-+#define ADV7511_REG_CEC_LOG_ADDR_0_1	0x4c
-+#define ADV7511_REG_CEC_LOG_ADDR_2	0x4d
-+#define ADV7511_REG_CEC_CLK_DIV		0x4e
-+#define ADV7511_REG_CEC_SOFT_RESET	0x50
-+
-+#define ADV7533_REG_CEC_OFFSET		0x70
-+
- enum adv7511_input_clock {
- 	ADV7511_INPUT_CLOCK_1X,
- 	ADV7511_INPUT_CLOCK_2X,
-@@ -297,6 +316,8 @@ enum adv7511_type {
- 	ADV7533,
- };
- 
-+#define ADV7511_MAX_ADDRS 3
-+
- struct adv7511 {
- 	struct i2c_client *i2c_main;
- 	struct i2c_client *i2c_edid;
-@@ -328,8 +349,6 @@ struct adv7511 {
- 	enum adv7511_sync_polarity hsync_polarity;
- 	bool rgb;
- 
--	struct edid *edid;
--
- 	struct gpio_desc *gpio_pd;
- 
- 	struct regulator_bulk_data *supplies;
-@@ -343,15 +362,27 @@ struct adv7511 {
- 
- 	enum adv7511_type type;
- 	struct platform_device *audio_pdev;
-+
-+	struct cec_adapter *cec_adap;
-+	u8   cec_addr[ADV7511_MAX_ADDRS];
-+	u8   cec_valid_addrs;
-+	bool cec_enabled_adap;
-+	struct clk *cec_clk;
-+	u32 cec_clk_freq;
- };
- 
-+#ifdef CONFIG_DRM_I2C_ADV7511_CEC
-+int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511,
-+		     unsigned int offset);
-+void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1);
-+#endif
-+
- #ifdef CONFIG_DRM_I2C_ADV7533
- void adv7533_dsi_power_on(struct adv7511 *adv);
- void adv7533_dsi_power_off(struct adv7511 *adv);
- void adv7533_mode_set(struct adv7511 *adv, struct drm_display_mode *mode);
- int adv7533_patch_registers(struct adv7511 *adv);
--void adv7533_uninit_cec(struct adv7511 *adv);
--int adv7533_init_cec(struct adv7511 *adv);
-+int adv7533_patch_cec_registers(struct adv7511 *adv);
- int adv7533_attach_dsi(struct adv7511 *adv);
- void adv7533_detach_dsi(struct adv7511 *adv);
- int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv);
-@@ -374,11 +405,7 @@ static inline int adv7533_patch_register
- 	return -ENODEV;
- }
- 
--static inline void adv7533_uninit_cec(struct adv7511 *adv)
--{
--}
--
--static inline int adv7533_init_cec(struct adv7511 *adv)
-+static inline int adv7533_patch_cec_registers(struct adv7511 *adv)
- {
- 	return -ENODEV;
- }
---- linux-4.14/drivers/gpu/drm/bridge/adv7511/adv7533.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/bridge/adv7511/adv7533.c	2017-12-14 06:39:58.488903618 +0100
-@@ -32,14 +32,6 @@ static const struct reg_sequence adv7533
- 	{ 0x05, 0xc8 },
- };
- 
--static const struct regmap_config adv7533_cec_regmap_config = {
--	.reg_bits = 8,
--	.val_bits = 8,
--
--	.max_register = 0xff,
--	.cache_type = REGCACHE_RBTREE,
--};
--
- static void adv7511_dsi_config_timing_gen(struct adv7511 *adv)
- {
- 	struct mipi_dsi_device *dsi = adv->dsi;
-@@ -145,37 +137,11 @@ int adv7533_patch_registers(struct adv75
- 				     ARRAY_SIZE(adv7533_fixed_registers));
- }
- 
--void adv7533_uninit_cec(struct adv7511 *adv)
--{
--	i2c_unregister_device(adv->i2c_cec);
--}
--
--int adv7533_init_cec(struct adv7511 *adv)
-+int adv7533_patch_cec_registers(struct adv7511 *adv)
- {
--	int ret;
--
--	adv->i2c_cec = i2c_new_dummy(adv->i2c_main->adapter,
--				     adv->i2c_main->addr - 1);
--	if (!adv->i2c_cec)
--		return -ENOMEM;
--
--	adv->regmap_cec = devm_regmap_init_i2c(adv->i2c_cec,
--					&adv7533_cec_regmap_config);
--	if (IS_ERR(adv->regmap_cec)) {
--		ret = PTR_ERR(adv->regmap_cec);
--		goto err;
--	}
--
--	ret = regmap_register_patch(adv->regmap_cec,
-+	return regmap_register_patch(adv->regmap_cec,
- 				    adv7533_cec_fixed_registers,
- 				    ARRAY_SIZE(adv7533_cec_fixed_registers));
--	if (ret)
--		goto err;
--
--	return 0;
--err:
--	adv7533_uninit_cec(adv);
--	return ret;
- }
- 
- int adv7533_attach_dsi(struct adv7511 *adv)
---- linux-4.14/drivers/gpu/drm/bridge/adv7511/Kconfig.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/bridge/adv7511/Kconfig	2017-12-14 06:39:58.488903618 +0100
-@@ -21,3 +21,11 @@ config DRM_I2C_ADV7533
- 	default y
- 	help
- 	  Support for the Analog Devices ADV7533 DSI to HDMI encoder.
-+
-+config DRM_I2C_ADV7511_CEC
-+	bool "ADV7511/33 HDMI CEC driver"
-+	depends on DRM_I2C_ADV7511
-+	select CEC_CORE
-+	default y
-+	help
-+	  When selected the HDMI transmitter will support the CEC feature.
---- linux-4.14/drivers/gpu/drm/bridge/adv7511/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/bridge/adv7511/Makefile	2017-12-14 06:39:58.488903618 +0100
-@@ -1,4 +1,5 @@
- adv7511-y := adv7511_drv.o
- adv7511-$(CONFIG_DRM_I2C_ADV7511_AUDIO) += adv7511_audio.o
-+adv7511-$(CONFIG_DRM_I2C_ADV7511_CEC) += adv7511_cec.o
- adv7511-$(CONFIG_DRM_I2C_ADV7533) += adv7533.o
- obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511.o
---- linux-4.14/drivers/gpu/drm/bridge/Kconfig.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/bridge/Kconfig	2017-12-14 06:39:58.488903618 +0100
-@@ -71,7 +71,7 @@ config DRM_PARADE_PS8622
- 
- config DRM_SIL_SII8620
- 	tristate "Silicon Image SII8620 HDMI/MHL bridge"
--	depends on OF
-+	depends on OF && RC_CORE
- 	select DRM_KMS_HELPER
- 	help
- 	  Silicon Image SII8620 HDMI/MHL bridge chip driver.
-@@ -84,6 +84,14 @@ config DRM_SII902X
- 	---help---
- 	  Silicon Image sii902x bridge chip driver.
- 
-+config DRM_SII9234
-+	tristate "Silicon Image SII9234 HDMI/MHL bridge"
-+	depends on OF
-+	---help---
-+	  Say Y here if you want support for the MHL interface.
-+	  It is an I2C driver, that detects connection of MHL bridge
-+	  and starts encapsulation of HDMI signal.
-+
- config DRM_TOSHIBA_TC358767
- 	tristate "Toshiba TC358767 eDP bridge"
- 	depends on OF
---- linux-4.14/drivers/gpu/drm/bridge/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/bridge/Makefile	2017-12-14 06:39:58.488903618 +0100
-@@ -7,6 +7,7 @@ obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn
- obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
- obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o
- obj-$(CONFIG_DRM_SII902X) += sii902x.o
-+obj-$(CONFIG_DRM_SII9234) += sii9234.o
- obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
- obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
- obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
---- linux-4.14/drivers/gpu/drm/bridge/panel.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/bridge/panel.c	2017-12-14 06:39:58.488903618 +0100
-@@ -188,7 +188,15 @@ EXPORT_SYMBOL(drm_panel_bridge_add);
-  */
- void drm_panel_bridge_remove(struct drm_bridge *bridge)
- {
--	struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
-+	struct panel_bridge *panel_bridge;
-+
-+	if (!bridge)
-+		return;
-+
-+	if (bridge->funcs != &panel_bridge_bridge_funcs)
-+		return;
-+
-+	panel_bridge = drm_bridge_to_panel_bridge(bridge);
- 
- 	drm_bridge_remove(bridge);
- 	devm_kfree(panel_bridge->panel->dev, bridge);
---- linux-4.14/drivers/gpu/drm/bridge/sii9234.c.0130~	2017-12-14 06:39:58.488903618 +0100
-+++ linux-4.14/drivers/gpu/drm/bridge/sii9234.c	2017-12-14 06:39:58.488903618 +0100
-@@ -0,0 +1,994 @@
-+/*
-+ * Copyright (C) 2017 Samsung Electronics
-+ *
-+ * Authors:
-+ *    Tomasz Stanislawski <t.stanislaws@samsung.com>
-+ *    Maciej Purski <m.purski@samsung.com>
-+ *
-+ * Based on sii9234 driver created by:
-+ *    Adam Hampson <ahampson@sta.samsung.com>
-+ *    Erik Gilling <konkers@android.com>
-+ *    Shankar Bandal <shankar.b@samsung.com>
-+ *    Dharam Kumar <dharam.kr@samsung.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program
-+ *
-+ */
-+#include <drm/bridge/mhl.h>
-+#include <drm/drm_crtc.h>
-+#include <drm/drm_edid.h>
-+
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/i2c.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/slab.h>
-+
-+#define CBUS_DEVCAP_OFFSET		0x80
-+
-+#define SII9234_MHL_VERSION		0x11
-+#define SII9234_SCRATCHPAD_SIZE		0x10
-+#define SII9234_INT_STAT_SIZE		0x33
-+
-+#define BIT_TMDS_CCTRL_TMDS_OE		BIT(4)
-+#define MHL_HPD_OUT_OVR_EN		BIT(4)
-+#define MHL_HPD_OUT_OVR_VAL		BIT(5)
-+#define MHL_INIT_TIMEOUT		0x0C
-+
-+/* MHL Tx registers and bits */
-+#define MHL_TX_SRST			0x05
-+#define MHL_TX_SYSSTAT_REG		0x09
-+#define MHL_TX_INTR1_REG		0x71
-+#define MHL_TX_INTR4_REG		0x74
-+#define MHL_TX_INTR1_ENABLE_REG		0x75
-+#define MHL_TX_INTR4_ENABLE_REG		0x78
-+#define MHL_TX_INT_CTRL_REG		0x79
-+#define MHL_TX_TMDS_CCTRL		0x80
-+#define MHL_TX_DISC_CTRL1_REG		0x90
-+#define MHL_TX_DISC_CTRL2_REG		0x91
-+#define MHL_TX_DISC_CTRL3_REG		0x92
-+#define MHL_TX_DISC_CTRL4_REG		0x93
-+#define MHL_TX_DISC_CTRL5_REG		0x94
-+#define MHL_TX_DISC_CTRL6_REG		0x95
-+#define MHL_TX_DISC_CTRL7_REG		0x96
-+#define MHL_TX_DISC_CTRL8_REG		0x97
-+#define MHL_TX_STAT2_REG		0x99
-+#define MHL_TX_MHLTX_CTL1_REG		0xA0
-+#define MHL_TX_MHLTX_CTL2_REG		0xA1
-+#define MHL_TX_MHLTX_CTL4_REG		0xA3
-+#define MHL_TX_MHLTX_CTL6_REG		0xA5
-+#define MHL_TX_MHLTX_CTL7_REG		0xA6
-+
-+#define RSEN_STATUS			BIT(2)
-+#define HPD_CHANGE_INT			BIT(6)
-+#define RSEN_CHANGE_INT			BIT(5)
-+#define RGND_READY_INT			BIT(6)
-+#define VBUS_LOW_INT			BIT(5)
-+#define CBUS_LKOUT_INT			BIT(4)
-+#define MHL_DISC_FAIL_INT		BIT(3)
-+#define MHL_EST_INT			BIT(2)
-+#define HPD_CHANGE_INT_MASK		BIT(6)
-+#define RSEN_CHANGE_INT_MASK		BIT(5)
-+
-+#define RGND_READY_MASK			BIT(6)
-+#define CBUS_LKOUT_MASK			BIT(4)
-+#define MHL_DISC_FAIL_MASK		BIT(3)
-+#define MHL_EST_MASK			BIT(2)
-+
-+#define SKIP_GND			BIT(6)
-+
-+#define ATT_THRESH_SHIFT		0x04
-+#define ATT_THRESH_MASK			(0x03 << ATT_THRESH_SHIFT)
-+#define USB_D_OEN			BIT(3)
-+#define DEGLITCH_TIME_MASK		0x07
-+#define DEGLITCH_TIME_2MS		0
-+#define DEGLITCH_TIME_4MS		1
-+#define DEGLITCH_TIME_8MS		2
-+#define DEGLITCH_TIME_16MS		3
-+#define DEGLITCH_TIME_40MS		4
-+#define DEGLITCH_TIME_50MS		5
-+#define DEGLITCH_TIME_60MS		6
-+#define DEGLITCH_TIME_128MS		7
-+
-+#define USB_D_OVR			BIT(7)
-+#define USB_ID_OVR			BIT(6)
-+#define DVRFLT_SEL			BIT(5)
-+#define BLOCK_RGND_INT			BIT(4)
-+#define SKIP_DEG			BIT(3)
-+#define CI2CA_POL			BIT(2)
-+#define CI2CA_WKUP			BIT(1)
-+#define SINGLE_ATT			BIT(0)
-+
-+#define USB_D_ODN			BIT(5)
-+#define VBUS_CHECK			BIT(2)
-+#define RGND_INTP_MASK			0x03
-+#define RGND_INTP_OPEN			0
-+#define RGND_INTP_2K			1
-+#define RGND_INTP_1K			2
-+#define RGND_INTP_SHORT			3
-+
-+/* HDMI registers */
-+#define HDMI_RX_TMDS0_CCTRL1_REG	0x10
-+#define HDMI_RX_TMDS_CLK_EN_REG		0x11
-+#define HDMI_RX_TMDS_CH_EN_REG		0x12
-+#define HDMI_RX_PLL_CALREFSEL_REG	0x17
-+#define HDMI_RX_PLL_VCOCAL_REG		0x1A
-+#define HDMI_RX_EQ_DATA0_REG		0x22
-+#define HDMI_RX_EQ_DATA1_REG		0x23
-+#define HDMI_RX_EQ_DATA2_REG		0x24
-+#define HDMI_RX_EQ_DATA3_REG		0x25
-+#define HDMI_RX_EQ_DATA4_REG		0x26
-+#define HDMI_RX_TMDS_ZONE_CTRL_REG	0x4C
-+#define HDMI_RX_TMDS_MODE_CTRL_REG	0x4D
-+
-+/* CBUS registers */
-+#define CBUS_INT_STATUS_1_REG		0x08
-+#define CBUS_INTR1_ENABLE_REG		0x09
-+#define CBUS_MSC_REQ_ABORT_REASON_REG	0x0D
-+#define CBUS_INT_STATUS_2_REG		0x1E
-+#define CBUS_INTR2_ENABLE_REG		0x1F
-+#define CBUS_LINK_CONTROL_2_REG		0x31
-+#define CBUS_MHL_STATUS_REG_0		0xB0
-+#define CBUS_MHL_STATUS_REG_1		0xB1
-+
-+#define BIT_CBUS_RESET			BIT(3)
-+#define SET_HPD_DOWNSTREAM		BIT(6)
-+
-+/* TPI registers */
-+#define TPI_DPD_REG			0x3D
-+
-+/* Timeouts in msec */
-+#define T_SRC_VBUS_CBUS_TO_STABLE	200
-+#define T_SRC_CBUS_FLOAT		100
-+#define T_SRC_CBUS_DEGLITCH		2
-+#define T_SRC_RXSENSE_DEGLITCH		110
-+
-+#define MHL1_MAX_CLK			75000 /* in kHz */
-+
-+#define I2C_TPI_ADDR			0x3D
-+#define I2C_HDMI_ADDR			0x49
-+#define I2C_CBUS_ADDR			0x64
-+
-+enum sii9234_state {
-+	ST_OFF,
-+	ST_D3,
-+	ST_RGND_INIT,
-+	ST_RGND_1K,
-+	ST_RSEN_HIGH,
-+	ST_MHL_ESTABLISHED,
-+	ST_FAILURE_DISCOVERY,
-+	ST_FAILURE,
-+};
-+
-+struct sii9234 {
-+	struct i2c_client *client[4];
-+	struct drm_bridge bridge;
-+	struct device *dev;
-+	struct gpio_desc *gpio_reset;
-+	int i2c_error;
-+	struct regulator_bulk_data supplies[4];
-+
-+	struct mutex lock; /* Protects fields below and device registers */
-+	enum sii9234_state state;
-+};
-+
-+enum sii9234_client_id {
-+	I2C_MHL,
-+	I2C_TPI,
-+	I2C_HDMI,
-+	I2C_CBUS,
-+};
-+
-+static const char * const sii9234_client_name[] = {
-+	[I2C_MHL] = "MHL",
-+	[I2C_TPI] = "TPI",
-+	[I2C_HDMI] = "HDMI",
-+	[I2C_CBUS] = "CBUS",
-+};
-+
-+static int sii9234_writeb(struct sii9234 *ctx, int id, int offset,
-+			  int value)
-+{
-+	int ret;
-+	struct i2c_client *client = ctx->client[id];
-+
-+	if (ctx->i2c_error)
-+		return ctx->i2c_error;
-+
-+	ret = i2c_smbus_write_byte_data(client, offset, value);
-+	if (ret < 0)
-+		dev_err(ctx->dev, "writeb: %4s[0x%02x] <- 0x%02x\n",
-+			sii9234_client_name[id], offset, value);
-+	ctx->i2c_error = ret;
-+
-+	return ret;
-+}
-+
-+static int sii9234_writebm(struct sii9234 *ctx, int id, int offset,
-+			   int value, int mask)
-+{
-+	int ret;
-+	struct i2c_client *client = ctx->client[id];
-+
-+	if (ctx->i2c_error)
-+		return ctx->i2c_error;
-+
-+	ret = i2c_smbus_write_byte(client, offset);
-+	if (ret < 0) {
-+		dev_err(ctx->dev, "writebm: %4s[0x%02x] <- 0x%02x\n",
-+			sii9234_client_name[id], offset, value);
-+		ctx->i2c_error = ret;
-+		return ret;
-+	}
-+
-+	ret = i2c_smbus_read_byte(client);
-+	if (ret < 0) {
-+		dev_err(ctx->dev, "writebm: %4s[0x%02x] <- 0x%02x\n",
-+			sii9234_client_name[id], offset, value);
-+		ctx->i2c_error = ret;
-+		return ret;
-+	}
-+
-+	value = (value & mask) | (ret & ~mask);
-+
-+	ret = i2c_smbus_write_byte_data(client, offset, value);
-+	if (ret < 0) {
-+		dev_err(ctx->dev, "writebm: %4s[0x%02x] <- 0x%02x\n",
-+			sii9234_client_name[id], offset, value);
-+		ctx->i2c_error = ret;
-+	}
-+
-+	return ret;
-+}
-+
-+static int sii9234_readb(struct sii9234 *ctx, int id, int offset)
-+{
-+	int ret;
-+	struct i2c_client *client = ctx->client[id];
-+
-+	if (ctx->i2c_error)
-+		return ctx->i2c_error;
-+
-+	ret = i2c_smbus_write_byte(client, offset);
-+	if (ret < 0) {
-+		dev_err(ctx->dev, "readb: %4s[0x%02x]\n",
-+			sii9234_client_name[id], offset);
-+		ctx->i2c_error = ret;
-+		return ret;
-+	}
-+
-+	ret = i2c_smbus_read_byte(client);
-+	if (ret < 0) {
-+		dev_err(ctx->dev, "readb: %4s[0x%02x]\n",
-+			sii9234_client_name[id], offset);
-+		ctx->i2c_error = ret;
-+	}
-+
-+	return ret;
-+}
-+
-+static int sii9234_clear_error(struct sii9234 *ctx)
-+{
-+	int ret = ctx->i2c_error;
-+
-+	ctx->i2c_error = 0;
-+
-+	return ret;
-+}
-+
-+#define mhl_tx_writeb(sii9234, offset, value) \
-+	sii9234_writeb(sii9234, I2C_MHL, offset, value)
-+#define mhl_tx_writebm(sii9234, offset, value, mask) \
-+	sii9234_writebm(sii9234, I2C_MHL, offset, value, mask)
-+#define mhl_tx_readb(sii9234, offset) \
-+	sii9234_readb(sii9234, I2C_MHL, offset)
-+#define cbus_writeb(sii9234, offset, value) \
-+	sii9234_writeb(sii9234, I2C_CBUS, offset, value)
-+#define cbus_writebm(sii9234, offset, value, mask) \
-+	sii9234_writebm(sii9234, I2C_CBUS, offset, value, mask)
-+#define cbus_readb(sii9234, offset) \
-+	sii9234_readb(sii9234, I2C_CBUS, offset)
-+#define hdmi_writeb(sii9234, offset, value) \
-+	sii9234_writeb(sii9234, I2C_HDMI, offset, value)
-+#define hdmi_writebm(sii9234, offset, value, mask) \
-+	sii9234_writebm(sii9234, I2C_HDMI, offset, value, mask)
-+#define hdmi_readb(sii9234, offset) \
-+	sii9234_readb(sii9234, I2C_HDMI, offset)
-+#define tpi_writeb(sii9234, offset, value) \
-+	sii9234_writeb(sii9234, I2C_TPI, offset, value)
-+#define tpi_writebm(sii9234, offset, value, mask) \
-+	sii9234_writebm(sii9234, I2C_TPI, offset, value, mask)
-+#define tpi_readb(sii9234, offset) \
-+	sii9234_readb(sii9234, I2C_TPI, offset)
-+
-+static u8 sii9234_tmds_control(struct sii9234 *ctx, bool enable)
-+{
-+	mhl_tx_writebm(ctx, MHL_TX_TMDS_CCTRL, enable ? ~0 : 0,
-+		       BIT_TMDS_CCTRL_TMDS_OE);
-+	mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, enable ? ~0 : 0,
-+		       MHL_HPD_OUT_OVR_EN | MHL_HPD_OUT_OVR_VAL);
-+	return sii9234_clear_error(ctx);
-+}
-+
-+static int sii9234_cbus_reset(struct sii9234 *ctx)
-+{
-+	int i;
-+
-+	mhl_tx_writebm(ctx, MHL_TX_SRST, ~0, BIT_CBUS_RESET);
-+	msleep(T_SRC_CBUS_DEGLITCH);
-+	mhl_tx_writebm(ctx, MHL_TX_SRST, 0, BIT_CBUS_RESET);
-+
-+	for (i = 0; i < 4; i++) {
-+		/*
-+		 * Enable WRITE_STAT interrupt for writes to all
-+		 * 4 MSC Status registers.
-+		 */
-+		cbus_writeb(ctx, 0xE0 + i, 0xF2);
-+		/*
-+		 * Enable SET_INT interrupt for writes to all
-+		 * 4 MSC Interrupt registers.
-+		 */
-+		cbus_writeb(ctx, 0xF0 + i, 0xF2);
-+	}
-+
-+	return sii9234_clear_error(ctx);
-+}
-+
-+/* Require to chek mhl imformation of samsung in cbus_init_register */
-+static int sii9234_cbus_init(struct sii9234 *ctx)
-+{
-+	cbus_writeb(ctx, 0x07, 0xF2);
-+	cbus_writeb(ctx, 0x40, 0x03);
-+	cbus_writeb(ctx, 0x42, 0x06);
-+	cbus_writeb(ctx, 0x36, 0x0C);
-+	cbus_writeb(ctx, 0x3D, 0xFD);
-+	cbus_writeb(ctx, 0x1C, 0x01);
-+	cbus_writeb(ctx, 0x1D, 0x0F);
-+	cbus_writeb(ctx, 0x44, 0x02);
-+	/* Setup our devcap */
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEV_STATE, 0x00);
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_MHL_VERSION,
-+		    SII9234_MHL_VERSION);
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_CAT,
-+		    MHL_DCAP_CAT_SOURCE);
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_H, 0x01);
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_L, 0x41);
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VID_LINK_MODE,
-+		    MHL_DCAP_VID_LINK_RGB444 | MHL_DCAP_VID_LINK_YCBCR444);
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VIDEO_TYPE,
-+		    MHL_DCAP_VT_GRAPHICS);
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_LOG_DEV_MAP,
-+		    MHL_DCAP_LD_GUI);
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_BANDWIDTH, 0x0F);
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_FEATURE_FLAG,
-+		    MHL_DCAP_FEATURE_RCP_SUPPORT | MHL_DCAP_FEATURE_RAP_SUPPORT
-+			| MHL_DCAP_FEATURE_SP_SUPPORT);
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_H, 0x0);
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_L, 0x0);
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_SCRATCHPAD_SIZE,
-+		    SII9234_SCRATCHPAD_SIZE);
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_INT_STAT_SIZE,
-+		    SII9234_INT_STAT_SIZE);
-+	cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_RESERVED, 0);
-+	cbus_writebm(ctx, 0x31, 0x0C, 0x0C);
-+	cbus_writeb(ctx, 0x30, 0x01);
-+	cbus_writebm(ctx, 0x3C, 0x30, 0x38);
-+	cbus_writebm(ctx, 0x22, 0x0D, 0x0F);
-+	cbus_writebm(ctx, 0x2E, 0x15, 0x15);
-+	cbus_writeb(ctx, CBUS_INTR1_ENABLE_REG, 0);
-+	cbus_writeb(ctx, CBUS_INTR2_ENABLE_REG, 0);
-+
-+	return sii9234_clear_error(ctx);
-+}
-+
-+static void force_usb_id_switch_open(struct sii9234 *ctx)
-+{
-+	/* Disable CBUS discovery */
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, 0, 0x01);
-+	/* Force USB ID switch to open */
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, ~0, USB_ID_OVR);
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL3_REG, ~0, 0x86);
-+	/* Force upstream HPD to 0 when not in MHL mode. */
-+	mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 0x30);
-+}
-+
-+static void release_usb_id_switch_open(struct sii9234 *ctx)
-+{
-+	msleep(T_SRC_CBUS_FLOAT);
-+	/* Clear USB ID switch to open */
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, 0, USB_ID_OVR);
-+	/* Enable CBUS discovery */
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, ~0, 0x01);
-+}
-+
-+static int sii9234_power_init(struct sii9234 *ctx)
-+{
-+	/* Force the SiI9234 into the D0 state. */
-+	tpi_writeb(ctx, TPI_DPD_REG, 0x3F);
-+	/* Enable TxPLL Clock */
-+	hdmi_writeb(ctx, HDMI_RX_TMDS_CLK_EN_REG, 0x01);
-+	/* Enable Tx Clock Path & Equalizer */
-+	hdmi_writeb(ctx, HDMI_RX_TMDS_CH_EN_REG, 0x15);
-+	/* Power Up TMDS */
-+	mhl_tx_writeb(ctx, 0x08, 0x35);
-+	return sii9234_clear_error(ctx);
-+}
-+
-+static int sii9234_hdmi_init(struct sii9234 *ctx)
-+{
-+	hdmi_writeb(ctx, HDMI_RX_TMDS0_CCTRL1_REG, 0xC1);
-+	hdmi_writeb(ctx, HDMI_RX_PLL_CALREFSEL_REG, 0x03);
-+	hdmi_writeb(ctx, HDMI_RX_PLL_VCOCAL_REG, 0x20);
-+	hdmi_writeb(ctx, HDMI_RX_EQ_DATA0_REG, 0x8A);
-+	hdmi_writeb(ctx, HDMI_RX_EQ_DATA1_REG, 0x6A);
-+	hdmi_writeb(ctx, HDMI_RX_EQ_DATA2_REG, 0xAA);
-+	hdmi_writeb(ctx, HDMI_RX_EQ_DATA3_REG, 0xCA);
-+	hdmi_writeb(ctx, HDMI_RX_EQ_DATA4_REG, 0xEA);
-+	hdmi_writeb(ctx, HDMI_RX_TMDS_ZONE_CTRL_REG, 0xA0);
-+	hdmi_writeb(ctx, HDMI_RX_TMDS_MODE_CTRL_REG, 0x00);
-+	mhl_tx_writeb(ctx, MHL_TX_TMDS_CCTRL, 0x34);
-+	hdmi_writeb(ctx, 0x45, 0x44);
-+	hdmi_writeb(ctx, 0x31, 0x0A);
-+	hdmi_writeb(ctx, HDMI_RX_TMDS0_CCTRL1_REG, 0xC1);
-+
-+	return sii9234_clear_error(ctx);
-+}
-+
-+static int sii9234_mhl_tx_ctl_int(struct sii9234 *ctx)
-+{
-+	mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL1_REG, 0xD0);
-+	mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL2_REG, 0xFC);
-+	mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL4_REG, 0xEB);
-+	mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL7_REG, 0x0C);
-+
-+	return sii9234_clear_error(ctx);
-+}
-+
-+static int sii9234_reset(struct sii9234 *ctx)
-+{
-+	int ret;
-+
-+	sii9234_clear_error(ctx);
-+
-+	ret = sii9234_power_init(ctx);
-+	if (ret < 0)
-+		return ret;
-+	ret = sii9234_cbus_reset(ctx);
-+	if (ret < 0)
-+		return ret;
-+	ret = sii9234_hdmi_init(ctx);
-+	if (ret < 0)
-+		return ret;
-+	ret = sii9234_mhl_tx_ctl_int(ctx);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* Enable HDCP Compliance safety */
-+	mhl_tx_writeb(ctx, 0x2B, 0x01);
-+	/* CBUS discovery cycle time for each drive and float = 150us */
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, 0x04, 0x06);
-+	/* Clear bit 6 (reg_skip_rgnd) */
-+	mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL2_REG, (1 << 7) /* Reserved */
-+		      | 2 << ATT_THRESH_SHIFT | DEGLITCH_TIME_50MS);
-+	/*
-+	 * Changed from 66 to 65 for 94[1:0] = 01 = 5k reg_cbusmhl_pup_sel
-+	 * 1.8V CBUS VTH & GND threshold
-+	 * to meet CTS 3.3.7.2 spec
-+	 */
-+	mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL5_REG, 0x77);
-+	cbus_writebm(ctx, CBUS_LINK_CONTROL_2_REG, ~0, MHL_INIT_TIMEOUT);
-+	mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL6_REG, 0xA0);
-+	/* RGND & single discovery attempt (RGND blocking) */
-+	mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL6_REG, BLOCK_RGND_INT |
-+		      DVRFLT_SEL | SINGLE_ATT);
-+	/* Use VBUS path of discovery state machine */
-+	mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL8_REG, 0);
-+	/* 0x92[3] sets the CBUS / ID switch */
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, ~0, USB_ID_OVR);
-+	/*
-+	 * To allow RGND engine to operate correctly.
-+	 * When moving the chip from D2 to D0 (power up, init regs)
-+	 * the values should be
-+	 * 94[1:0] = 01  reg_cbusmhl_pup_sel[1:0] should be set for 5k
-+	 * 93[7:6] = 10  reg_cbusdisc_pup_sel[1:0] should be
-+	 * set for 10k (default)
-+	 * 93[5:4] = 00  reg_cbusidle_pup_sel[1:0] = open (default)
-+	 */
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL3_REG, ~0, 0x86);
-+	/*
-+	 * Change from CC to 8C to match 5K
-+	 * to meet CTS 3.3.72 spec
-+	 */
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL4_REG, ~0, 0x8C);
-+	/* Configure the interrupt as active high */
-+	mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 0x06);
-+
-+	msleep(25);
-+
-+	/* Release usb_id switch */
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, 0,  USB_ID_OVR);
-+	mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL1_REG, 0x27);
-+
-+	ret = sii9234_clear_error(ctx);
-+	if (ret < 0)
-+		return ret;
-+	ret = sii9234_cbus_init(ctx);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* Enable Auto soft reset on SCDT = 0 */
-+	mhl_tx_writeb(ctx, 0x05, 0x04);
-+	/* HDMI Transcode mode enable */
-+	mhl_tx_writeb(ctx, 0x0D, 0x1C);
-+	mhl_tx_writeb(ctx, MHL_TX_INTR4_ENABLE_REG,
-+		      RGND_READY_MASK | CBUS_LKOUT_MASK
-+			| MHL_DISC_FAIL_MASK | MHL_EST_MASK);
-+	mhl_tx_writeb(ctx, MHL_TX_INTR1_ENABLE_REG, 0x60);
-+
-+	/* This point is very important before measure RGND impedance */
-+	force_usb_id_switch_open(ctx);
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL4_REG, 0, 0xF0);
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL5_REG, 0, 0x03);
-+	release_usb_id_switch_open(ctx);
-+
-+	/* Force upstream HPD to 0 when not in MHL mode */
-+	mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 1 << 5);
-+	mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, ~0, 1 << 4);
-+
-+	return sii9234_clear_error(ctx);
-+}
-+
-+static int sii9234_goto_d3(struct sii9234 *ctx)
-+{
-+	int ret;
-+
-+	dev_dbg(ctx->dev, "sii9234: detection started d3\n");
-+
-+	ret = sii9234_reset(ctx);
-+	if (ret < 0)
-+		goto exit;
-+
-+	hdmi_writeb(ctx, 0x01, 0x03);
-+	tpi_writebm(ctx, TPI_DPD_REG, 0, 1);
-+	/* I2C above is expected to fail because power goes down */
-+	sii9234_clear_error(ctx);
-+
-+	ctx->state = ST_D3;
-+
-+	return 0;
-+ exit:
-+	dev_err(ctx->dev, "%s failed\n", __func__);
-+	return -1;
-+}
-+
-+static int sii9234_hw_on(struct sii9234 *ctx)
-+{
-+	return regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
-+}
-+
-+static void sii9234_hw_off(struct sii9234 *ctx)
-+{
-+	gpiod_set_value(ctx->gpio_reset, 1);
-+	msleep(20);
-+	regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
-+}
-+
-+static void sii9234_hw_reset(struct sii9234 *ctx)
-+{
-+	gpiod_set_value(ctx->gpio_reset, 1);
-+	msleep(20);
-+	gpiod_set_value(ctx->gpio_reset, 0);
-+}
-+
-+static void sii9234_cable_in(struct sii9234 *ctx)
-+{
-+	int ret;
-+
-+	mutex_lock(&ctx->lock);
-+	if (ctx->state != ST_OFF)
-+		goto unlock;
-+	ret = sii9234_hw_on(ctx);
-+	if (ret < 0)
-+		goto unlock;
-+
-+	sii9234_hw_reset(ctx);
-+	sii9234_goto_d3(ctx);
-+	/* To avoid irq storm, when hw is in meta state */
-+	enable_irq(to_i2c_client(ctx->dev)->irq);
-+
-+unlock:
-+	mutex_unlock(&ctx->lock);
-+}
-+
-+static void sii9234_cable_out(struct sii9234 *ctx)
-+{
-+	mutex_lock(&ctx->lock);
-+
-+	if (ctx->state == ST_OFF)
-+		goto unlock;
-+
-+	disable_irq(to_i2c_client(ctx->dev)->irq);
-+	tpi_writeb(ctx, TPI_DPD_REG, 0);
-+	/* Turn on&off hpd festure for only QCT HDMI */
-+	sii9234_hw_off(ctx);
-+
-+	ctx->state = ST_OFF;
-+
-+unlock:
-+	mutex_unlock(&ctx->lock);
-+}
-+
-+static enum sii9234_state sii9234_rgnd_ready_irq(struct sii9234 *ctx)
-+{
-+	int value;
-+
-+	if (ctx->state == ST_D3) {
-+		int ret;
-+
-+		dev_dbg(ctx->dev, "RGND_READY_INT\n");
-+		sii9234_hw_reset(ctx);
-+
-+		ret = sii9234_reset(ctx);
-+		if (ret < 0) {
-+			dev_err(ctx->dev, "sii9234_reset() failed\n");
-+			return ST_FAILURE;
-+		}
-+
-+		return ST_RGND_INIT;
-+	}
-+
-+	/* Got interrupt in inappropriate state */
-+	if (ctx->state != ST_RGND_INIT)
-+		return ST_FAILURE;
-+
-+	value = mhl_tx_readb(ctx, MHL_TX_STAT2_REG);
-+	if (sii9234_clear_error(ctx))
-+		return ST_FAILURE;
-+
-+	if ((value & RGND_INTP_MASK) != RGND_INTP_1K) {
-+		dev_warn(ctx->dev, "RGND is not 1k\n");
-+		return ST_RGND_INIT;
-+	}
-+	dev_dbg(ctx->dev, "RGND 1K!!\n");
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL4_REG, ~0, 0x8C);
-+	mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL5_REG, 0x77);
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, ~0, 0x05);
-+	if (sii9234_clear_error(ctx))
-+		return ST_FAILURE;
-+
-+	msleep(T_SRC_VBUS_CBUS_TO_STABLE);
-+	return ST_RGND_1K;
-+}
-+
-+static enum sii9234_state sii9234_mhl_established(struct sii9234 *ctx)
-+{
-+	dev_dbg(ctx->dev, "mhl est interrupt\n");
-+
-+	/* Discovery override */
-+	mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL1_REG, 0x10);
-+	/* Increase DDC translation layer timer (byte mode) */
-+	cbus_writeb(ctx, 0x07, 0x32);
-+	cbus_writebm(ctx, 0x44, ~0, 1 << 1);
-+	/* Keep the discovery enabled. Need RGND interrupt */
-+	mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, ~0, 1);
-+	mhl_tx_writeb(ctx, MHL_TX_INTR1_ENABLE_REG,
-+		      RSEN_CHANGE_INT_MASK | HPD_CHANGE_INT_MASK);
-+
-+	if (sii9234_clear_error(ctx))
-+		return ST_FAILURE;
-+
-+	return ST_MHL_ESTABLISHED;
-+}
-+
-+static enum sii9234_state sii9234_hpd_change(struct sii9234 *ctx)
-+{
-+	int value;
-+
-+	value = cbus_readb(ctx, CBUS_MSC_REQ_ABORT_REASON_REG);
-+	if (sii9234_clear_error(ctx))
-+		return ST_FAILURE;
-+
-+	if (value & SET_HPD_DOWNSTREAM) {
-+		/* Downstream HPD High, Enable TMDS */
-+		sii9234_tmds_control(ctx, true);
-+	} else {
-+		/* Downstream HPD Low, Disable TMDS */
-+		sii9234_tmds_control(ctx, false);
-+	}
-+
-+	return ctx->state;
-+}
-+
-+static enum sii9234_state sii9234_rsen_change(struct sii9234 *ctx)
-+{
-+	int value;
-+
-+	/* Work_around code to handle wrong interrupt */
-+	if (ctx->state != ST_RGND_1K) {
-+		dev_err(ctx->dev, "RSEN_HIGH without RGND_1K\n");
-+		return ST_FAILURE;
-+	}
-+	value = mhl_tx_readb(ctx, MHL_TX_SYSSTAT_REG);
-+	if (value < 0)
-+		return ST_FAILURE;
-+
-+	if (value & RSEN_STATUS) {
-+		dev_dbg(ctx->dev, "MHL cable connected.. RSEN High\n");
-+		return ST_RSEN_HIGH;
-+	}
-+	dev_dbg(ctx->dev, "RSEN lost\n");
-+	/*
-+	 * Once RSEN loss is confirmed,we need to check
-+	 * based on cable status and chip power status,whether
-+	 * it is SINK Loss(HDMI cable not connected, TV Off)
-+	 * or MHL cable disconnection
-+	 * TODO: Define the below mhl_disconnection()
-+	 */
-+	msleep(T_SRC_RXSENSE_DEGLITCH);
-+	value = mhl_tx_readb(ctx, MHL_TX_SYSSTAT_REG);
-+	if (value < 0)
-+		return ST_FAILURE;
-+	dev_dbg(ctx->dev, "sys_stat: %x\n", value);
-+
-+	if (value & RSEN_STATUS) {
-+		dev_dbg(ctx->dev, "RSEN recovery\n");
-+		return ST_RSEN_HIGH;
-+	}
-+	dev_dbg(ctx->dev, "RSEN Really LOW\n");
-+	/* To meet CTS 3.3.22.2 spec */
-+	sii9234_tmds_control(ctx, false);
-+	force_usb_id_switch_open(ctx);
-+	release_usb_id_switch_open(ctx);
-+
-+	return ST_FAILURE;
-+}
-+
-+static irqreturn_t sii9234_irq_thread(int irq, void *data)
-+{
-+	struct sii9234 *ctx = data;
-+	int intr1, intr4;
-+	int intr1_en, intr4_en;
-+	int cbus_intr1, cbus_intr2;
-+
-+	dev_dbg(ctx->dev, "%s\n", __func__);
-+
-+	mutex_lock(&ctx->lock);
-+
-+	intr1 = mhl_tx_readb(ctx, MHL_TX_INTR1_REG);
-+	intr4 = mhl_tx_readb(ctx, MHL_TX_INTR4_REG);
-+	intr1_en = mhl_tx_readb(ctx, MHL_TX_INTR1_ENABLE_REG);
-+	intr4_en = mhl_tx_readb(ctx, MHL_TX_INTR4_ENABLE_REG);
-+	cbus_intr1 = cbus_readb(ctx, CBUS_INT_STATUS_1_REG);
-+	cbus_intr2 = cbus_readb(ctx, CBUS_INT_STATUS_2_REG);
-+
-+	if (sii9234_clear_error(ctx))
-+		goto done;
-+
-+	dev_dbg(ctx->dev, "irq %02x/%02x %02x/%02x %02x/%02x\n",
-+		intr1, intr1_en, intr4, intr4_en, cbus_intr1, cbus_intr2);
-+
-+	if (intr4 & RGND_READY_INT)
-+		ctx->state = sii9234_rgnd_ready_irq(ctx);
-+	if (intr1 & RSEN_CHANGE_INT)
-+		ctx->state = sii9234_rsen_change(ctx);
-+	if (intr4 & MHL_EST_INT)
-+		ctx->state = sii9234_mhl_established(ctx);
-+	if (intr1 & HPD_CHANGE_INT)
-+		ctx->state = sii9234_hpd_change(ctx);
-+	if (intr4 & CBUS_LKOUT_INT)
-+		ctx->state = ST_FAILURE;
-+	if (intr4 & MHL_DISC_FAIL_INT)
-+		ctx->state = ST_FAILURE_DISCOVERY;
-+
-+ done:
-+	/* Clean interrupt status and pending flags */
-+	mhl_tx_writeb(ctx, MHL_TX_INTR1_REG, intr1);
-+	mhl_tx_writeb(ctx, MHL_TX_INTR4_REG, intr4);
-+	cbus_writeb(ctx, CBUS_MHL_STATUS_REG_0, 0xFF);
-+	cbus_writeb(ctx, CBUS_MHL_STATUS_REG_1, 0xFF);
-+	cbus_writeb(ctx, CBUS_INT_STATUS_1_REG, cbus_intr1);
-+	cbus_writeb(ctx, CBUS_INT_STATUS_2_REG, cbus_intr2);
-+
-+	sii9234_clear_error(ctx);
-+
-+	if (ctx->state == ST_FAILURE) {
-+		dev_dbg(ctx->dev, "try to reset after failure\n");
-+		sii9234_hw_reset(ctx);
-+		sii9234_goto_d3(ctx);
-+	}
-+
-+	if (ctx->state == ST_FAILURE_DISCOVERY) {
-+		dev_err(ctx->dev, "discovery failed, no power for MHL?\n");
-+		tpi_writebm(ctx, TPI_DPD_REG, 0, 1);
-+		ctx->state = ST_D3;
-+	}
-+
-+	mutex_unlock(&ctx->lock);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int sii9234_init_resources(struct sii9234 *ctx,
-+				  struct i2c_client *client)
-+{
-+	struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
-+	int ret;
-+
-+	if (!ctx->dev->of_node) {
-+		dev_err(ctx->dev, "not DT device\n");
-+		return -ENODEV;
-+	}
-+
-+	ctx->gpio_reset = devm_gpiod_get(ctx->dev, "reset", GPIOD_OUT_LOW);
-+	if (IS_ERR(ctx->gpio_reset)) {
-+		dev_err(ctx->dev, "failed to get reset gpio from DT\n");
-+		return PTR_ERR(ctx->gpio_reset);
-+	}
-+
-+	ctx->supplies[0].supply = "avcc12";
-+	ctx->supplies[1].supply = "avcc33";
-+	ctx->supplies[2].supply = "iovcc18";
-+	ctx->supplies[3].supply = "cvcc12";
-+	ret = devm_regulator_bulk_get(ctx->dev, 4, ctx->supplies);
-+	if (ret) {
-+		dev_err(ctx->dev, "regulator_bulk failed\n");
-+		return ret;
-+	}
-+
-+	ctx->client[I2C_MHL] = client;
-+
-+	ctx->client[I2C_TPI] = i2c_new_dummy(adapter, I2C_TPI_ADDR);
-+	if (!ctx->client[I2C_TPI]) {
-+		dev_err(ctx->dev, "failed to create TPI client\n");
-+		return -ENODEV;
-+	}
-+
-+	ctx->client[I2C_HDMI] = i2c_new_dummy(adapter, I2C_HDMI_ADDR);
-+	if (!ctx->client[I2C_HDMI]) {
-+		dev_err(ctx->dev, "failed to create HDMI RX client\n");
-+		goto fail_tpi;
-+	}
-+
-+	ctx->client[I2C_CBUS] = i2c_new_dummy(adapter, I2C_CBUS_ADDR);
-+	if (!ctx->client[I2C_CBUS]) {
-+		dev_err(ctx->dev, "failed to create CBUS client\n");
-+		goto fail_hdmi;
-+	}
-+
-+	return 0;
-+
-+fail_hdmi:
-+	i2c_unregister_device(ctx->client[I2C_HDMI]);
-+fail_tpi:
-+	i2c_unregister_device(ctx->client[I2C_TPI]);
-+
-+	return -ENODEV;
-+}
-+
-+static void sii9234_deinit_resources(struct sii9234 *ctx)
-+{
-+	i2c_unregister_device(ctx->client[I2C_CBUS]);
-+	i2c_unregister_device(ctx->client[I2C_HDMI]);
-+	i2c_unregister_device(ctx->client[I2C_TPI]);
-+}
-+
-+static inline struct sii9234 *bridge_to_sii9234(struct drm_bridge *bridge)
-+{
-+	return container_of(bridge, struct sii9234, bridge);
-+}
-+
-+static enum drm_mode_status sii9234_mode_valid(struct drm_bridge *bridge,
-+					 const struct drm_display_mode *mode)
-+{
-+	if (mode->clock > MHL1_MAX_CLK)
-+		return MODE_CLOCK_HIGH;
-+
-+	return MODE_OK;
-+}
-+
-+static const struct drm_bridge_funcs sii9234_bridge_funcs = {
-+	.mode_valid = sii9234_mode_valid,
-+};
-+
-+static int sii9234_probe(struct i2c_client *client,
-+			 const struct i2c_device_id *id)
-+{
-+	struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
-+	struct sii9234 *ctx;
-+	struct device *dev = &client->dev;
-+	int ret;
-+
-+	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
-+	if (!ctx)
-+		return -ENOMEM;
-+
-+	ctx->dev = dev;
-+	mutex_init(&ctx->lock);
-+
-+	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
-+		dev_err(dev, "I2C adapter lacks SMBUS feature\n");
-+		return -EIO;
-+	}
-+
-+	if (!client->irq) {
-+		dev_err(dev, "no irq provided\n");
-+		return -EINVAL;
-+	}
-+
-+	irq_set_status_flags(client->irq, IRQ_NOAUTOEN);
-+	ret = devm_request_threaded_irq(dev, client->irq, NULL,
-+					sii9234_irq_thread,
-+					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
-+					"sii9234", ctx);
-+	if (ret < 0) {
-+		dev_err(dev, "failed to install IRQ handler\n");
-+		return ret;
-+	}
-+
-+	ret = sii9234_init_resources(ctx, client);
-+	if (ret < 0)
-+		return ret;
-+
-+	i2c_set_clientdata(client, ctx);
-+
-+	ctx->bridge.funcs = &sii9234_bridge_funcs;
-+	ctx->bridge.of_node = dev->of_node;
-+	drm_bridge_add(&ctx->bridge);
-+
-+	sii9234_cable_in(ctx);
-+
-+	return 0;
-+}
-+
-+static int sii9234_remove(struct i2c_client *client)
-+{
-+	struct sii9234 *ctx = i2c_get_clientdata(client);
-+
-+	sii9234_cable_out(ctx);
-+	drm_bridge_remove(&ctx->bridge);
-+	sii9234_deinit_resources(ctx);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id sii9234_dt_match[] = {
-+	{ .compatible = "sil,sii9234" },
-+	{ },
-+};
-+MODULE_DEVICE_TABLE(of, sii9234_dt_match);
-+
-+static const struct i2c_device_id sii9234_id[] = {
-+	{ "SII9234", 0 },
-+	{ },
-+};
-+MODULE_DEVICE_TABLE(i2c, sii9234_id);
-+
-+static struct i2c_driver sii9234_driver = {
-+	.driver = {
-+		.name	= "sii9234",
-+		.of_match_table = sii9234_dt_match,
-+	},
-+	.probe = sii9234_probe,
-+	.remove = sii9234_remove,
-+	.id_table = sii9234_id,
-+};
-+
-+module_i2c_driver(sii9234_driver);
-+MODULE_LICENSE("GPL");
---- linux-4.14/drivers/gpu/drm/bridge/sil-sii8620.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/bridge/sil-sii8620.c	2017-12-14 06:39:58.488903618 +0100
-@@ -28,6 +28,8 @@
- #include <linux/regulator/consumer.h>
- #include <linux/slab.h>
- 
-+#include <media/rc-core.h>
-+
- #include "sil-sii8620.h"
- 
- #define SII8620_BURST_BUF_LEN 288
-@@ -58,6 +60,7 @@ enum sii8620_mt_state {
- struct sii8620 {
- 	struct drm_bridge bridge;
- 	struct device *dev;
-+	struct rc_dev *rc_dev;
- 	struct clk *clk_xtal;
- 	struct gpio_desc *gpio_reset;
- 	struct gpio_desc *gpio_int;
-@@ -431,6 +434,16 @@ static void sii8620_mt_rap(struct sii862
- 	sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code);
- }
- 
-+static void sii8620_mt_rcpk(struct sii8620 *ctx, u8 code)
-+{
-+	sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPK, code);
-+}
-+
-+static void sii8620_mt_rcpe(struct sii8620 *ctx, u8 code)
-+{
-+	sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPE, code);
-+}
-+
- static void sii8620_mt_read_devcap_send(struct sii8620 *ctx,
- 					struct sii8620_mt_msg *msg)
- {
-@@ -1753,6 +1766,25 @@ static void sii8620_send_features(struct
- 	sii8620_write_buf(ctx, REG_MDT_XMIT_WRITE_PORT, buf, ARRAY_SIZE(buf));
- }
- 
-+static bool sii8620_rcp_consume(struct sii8620 *ctx, u8 scancode)
-+{
-+	bool pressed = !(scancode & MHL_RCP_KEY_RELEASED_MASK);
-+
-+	scancode &= MHL_RCP_KEY_ID_MASK;
-+
-+	if (!ctx->rc_dev) {
-+		dev_dbg(ctx->dev, "RCP input device not initialized\n");
-+		return false;
-+	}
-+
-+	if (pressed)
-+		rc_keydown(ctx->rc_dev, RC_PROTO_CEC, scancode, 0);
-+	else
-+		rc_keyup(ctx->rc_dev);
-+
-+	return true;
-+}
-+
- static void sii8620_msc_mr_set_int(struct sii8620 *ctx)
- {
- 	u8 ints[MHL_INT_SIZE];
-@@ -1804,19 +1836,25 @@ static void sii8620_msc_mt_done(struct s
- 
- static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx)
- {
--	struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx);
-+	struct sii8620_mt_msg *msg;
- 	u8 buf[2];
- 
--	if (!msg)
--		return;
--
- 	sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2);
- 
- 	switch (buf[0]) {
- 	case MHL_MSC_MSG_RAPK:
-+		msg = sii8620_msc_msg_first(ctx);
-+		if (!msg)
-+			return;
- 		msg->ret = buf[1];
- 		ctx->mt_state = MT_STATE_DONE;
- 		break;
-+	case MHL_MSC_MSG_RCP:
-+		if (!sii8620_rcp_consume(ctx, buf[1]))
-+			sii8620_mt_rcpe(ctx,
-+					MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE);
-+		sii8620_mt_rcpk(ctx, buf[1]);
-+		break;
- 	default:
- 		dev_err(ctx->dev, "%s message type %d,%d not supported",
- 			__func__, buf[0], buf[1]);
-@@ -2102,11 +2140,57 @@ static void sii8620_cable_in(struct sii8
- 	enable_irq(to_i2c_client(ctx->dev)->irq);
- }
- 
-+static void sii8620_init_rcp_input_dev(struct sii8620 *ctx)
-+{
-+	struct rc_dev *rc_dev;
-+	int ret;
-+
-+	rc_dev = rc_allocate_device(RC_DRIVER_SCANCODE);
-+	if (!rc_dev) {
-+		dev_err(ctx->dev, "Failed to allocate RC device\n");
-+		ctx->error = -ENOMEM;
-+		return;
-+	}
-+
-+	rc_dev->input_phys = "sii8620/input0";
-+	rc_dev->input_id.bustype = BUS_VIRTUAL;
-+	rc_dev->map_name = RC_MAP_CEC;
-+	rc_dev->allowed_protocols = RC_PROTO_BIT_CEC;
-+	rc_dev->driver_name = "sii8620";
-+	rc_dev->device_name = "sii8620";
-+
-+	ret = rc_register_device(rc_dev);
-+
-+	if (ret) {
-+		dev_err(ctx->dev, "Failed to register RC device\n");
-+		ctx->error = ret;
-+		rc_free_device(ctx->rc_dev);
-+		return;
-+	}
-+	ctx->rc_dev = rc_dev;
-+}
-+
- static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge)
- {
- 	return container_of(bridge, struct sii8620, bridge);
- }
- 
-+static int sii8620_attach(struct drm_bridge *bridge)
-+{
-+	struct sii8620 *ctx = bridge_to_sii8620(bridge);
-+
-+	sii8620_init_rcp_input_dev(ctx);
-+
-+	return sii8620_clear_error(ctx);
-+}
-+
-+static void sii8620_detach(struct drm_bridge *bridge)
-+{
-+	struct sii8620 *ctx = bridge_to_sii8620(bridge);
-+
-+	rc_unregister_device(ctx->rc_dev);
-+}
-+
- static bool sii8620_mode_fixup(struct drm_bridge *bridge,
- 			       const struct drm_display_mode *mode,
- 			       struct drm_display_mode *adjusted_mode)
-@@ -2151,6 +2235,8 @@ end:
- }
- 
- static const struct drm_bridge_funcs sii8620_bridge_funcs = {
-+	.attach = sii8620_attach,
-+	.detach = sii8620_detach,
- 	.mode_fixup = sii8620_mode_fixup,
- };
- 
-@@ -2217,8 +2303,8 @@ static int sii8620_remove(struct i2c_cli
- 	struct sii8620 *ctx = i2c_get_clientdata(client);
- 
- 	disable_irq(to_i2c_client(ctx->dev)->irq);
--	drm_bridge_remove(&ctx->bridge);
- 	sii8620_hw_off(ctx);
-+	drm_bridge_remove(&ctx->bridge);
- 
- 	return 0;
- }
---- linux-4.14/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c	2017-12-14 06:39:58.489903619 +0100
-@@ -30,19 +30,20 @@
- #include <video/mipi_display.h>
- 
- #define DSI_VERSION			0x00
-+
- #define DSI_PWR_UP			0x04
- #define RESET				0
- #define POWERUP				BIT(0)
- 
- #define DSI_CLKMGR_CFG			0x08
--#define TO_CLK_DIVIDSION(div)		(((div) & 0xff) << 8)
--#define TX_ESC_CLK_DIVIDSION(div)	(((div) & 0xff) << 0)
-+#define TO_CLK_DIVISION(div)		(((div) & 0xff) << 8)
-+#define TX_ESC_CLK_DIVISION(div)	((div) & 0xff)
- 
- #define DSI_DPI_VCID			0x0c
--#define DPI_VID(vid)			(((vid) & 0x3) << 0)
-+#define DPI_VCID(vcid)			((vcid) & 0x3)
- 
- #define DSI_DPI_COLOR_CODING		0x10
--#define EN18_LOOSELY			BIT(8)
-+#define LOOSELY18_EN			BIT(8)
- #define DPI_COLOR_CODING_16BIT_1	0x0
- #define DPI_COLOR_CODING_16BIT_2	0x1
- #define DPI_COLOR_CODING_16BIT_3	0x2
-@@ -61,22 +62,25 @@
- #define OUTVACT_LPCMD_TIME(p)		(((p) & 0xff) << 16)
- #define INVACT_LPCMD_TIME(p)		((p) & 0xff)
- 
-+#define DSI_DBI_VCID			0x1c
- #define DSI_DBI_CFG			0x20
-+#define DSI_DBI_PARTITIONING_EN		0x24
- #define DSI_DBI_CMDSIZE			0x28
- 
- #define DSI_PCKHDL_CFG			0x2c
--#define EN_CRC_RX			BIT(4)
--#define EN_ECC_RX			BIT(3)
--#define EN_BTA				BIT(2)
--#define EN_EOTP_RX			BIT(1)
--#define EN_EOTP_TX			BIT(0)
-+#define CRC_RX_EN			BIT(4)
-+#define ECC_RX_EN			BIT(3)
-+#define BTA_EN				BIT(2)
-+#define EOTP_RX_EN			BIT(1)
-+#define EOTP_TX_EN			BIT(0)
-+
-+#define DSI_GEN_VCID			0x30
- 
- #define DSI_MODE_CFG			0x34
- #define ENABLE_VIDEO_MODE		0
- #define ENABLE_CMD_MODE			BIT(0)
- 
- #define DSI_VID_MODE_CFG		0x38
--#define FRAME_BTA_ACK			BIT(14)
- #define ENABLE_LOW_POWER		(0x3f << 8)
- #define ENABLE_LOW_POWER_MASK		(0x3f << 8)
- #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES	0x0
-@@ -85,8 +89,13 @@
- #define VID_MODE_TYPE_MASK			0x3
- 
- #define DSI_VID_PKT_SIZE		0x3c
--#define VID_PKT_SIZE(p)			(((p) & 0x3fff) << 0)
--#define VID_PKT_MAX_SIZE		0x3fff
-+#define VID_PKT_SIZE(p)			((p) & 0x3fff)
-+
-+#define DSI_VID_NUM_CHUNKS		0x40
-+#define VID_NUM_CHUNKS(c)		((c) & 0x1fff)
-+
-+#define DSI_VID_NULL_SIZE		0x44
-+#define VID_NULL_SIZE(b)		((b) & 0x1fff)
- 
- #define DSI_VID_HSA_TIME		0x48
- #define DSI_VID_HBP_TIME		0x4c
-@@ -95,6 +104,8 @@
- #define DSI_VID_VBP_LINES		0x58
- #define DSI_VID_VFP_LINES		0x5c
- #define DSI_VID_VACTIVE_LINES		0x60
-+#define DSI_EDPI_CMD_SIZE		0x64
-+
- #define DSI_CMD_MODE_CFG		0x68
- #define MAX_RD_PKT_SIZE_LP		BIT(24)
- #define DCS_LW_TX_LP			BIT(19)
-@@ -108,8 +119,8 @@
- #define GEN_SW_2P_TX_LP			BIT(10)
- #define GEN_SW_1P_TX_LP			BIT(9)
- #define GEN_SW_0P_TX_LP			BIT(8)
--#define EN_ACK_RQST			BIT(1)
--#define EN_TEAR_FX			BIT(0)
-+#define ACK_RQST_EN			BIT(1)
-+#define TEAR_FX_EN			BIT(0)
- 
- #define CMD_MODE_ALL_LP			(MAX_RD_PKT_SIZE_LP | \
- 					 DCS_LW_TX_LP | \
-@@ -125,27 +136,31 @@
- 					 GEN_SW_0P_TX_LP)
- 
- #define DSI_GEN_HDR			0x6c
-+/* TODO These 2 defines will be reworked thanks to mipi_dsi_create_packet() */
- #define GEN_HDATA(data)			(((data) & 0xffff) << 8)
--#define GEN_HDATA_MASK			(0xffff << 8)
- #define GEN_HTYPE(type)			(((type) & 0xff) << 0)
--#define GEN_HTYPE_MASK			0xff
- 
- #define DSI_GEN_PLD_DATA		0x70
- 
- #define DSI_CMD_PKT_STATUS		0x74
--#define GEN_CMD_EMPTY			BIT(0)
--#define GEN_CMD_FULL			BIT(1)
--#define GEN_PLD_W_EMPTY			BIT(2)
--#define GEN_PLD_W_FULL			BIT(3)
--#define GEN_PLD_R_EMPTY			BIT(4)
--#define GEN_PLD_R_FULL			BIT(5)
- #define GEN_RD_CMD_BUSY			BIT(6)
-+#define GEN_PLD_R_FULL			BIT(5)
-+#define GEN_PLD_R_EMPTY			BIT(4)
-+#define GEN_PLD_W_FULL			BIT(3)
-+#define GEN_PLD_W_EMPTY			BIT(2)
-+#define GEN_CMD_FULL			BIT(1)
-+#define GEN_CMD_EMPTY			BIT(0)
- 
- #define DSI_TO_CNT_CFG			0x78
- #define HSTX_TO_CNT(p)			(((p) & 0xffff) << 16)
- #define LPRX_TO_CNT(p)			((p) & 0xffff)
- 
-+#define DSI_HS_RD_TO_CNT		0x7c
-+#define DSI_LP_RD_TO_CNT		0x80
-+#define DSI_HS_WR_TO_CNT		0x84
-+#define DSI_LP_WR_TO_CNT		0x88
- #define DSI_BTA_TO_CNT			0x8c
-+
- #define DSI_LPCLK_CTRL			0x94
- #define AUTO_CLKLANE_CTRL		BIT(1)
- #define PHY_TXREQUESTCLKHS		BIT(0)
-@@ -154,6 +169,7 @@
- #define PHY_CLKHS2LP_TIME(lbcc)		(((lbcc) & 0x3ff) << 16)
- #define PHY_CLKLP2HS_TIME(lbcc)		((lbcc) & 0x3ff)
- 
-+/* TODO Next register is slightly different between 1.30 & 1.31 IP version */
- #define DSI_PHY_TMR_CFG			0x9c
- #define PHY_HS2LP_TIME(lbcc)		(((lbcc) & 0xff) << 24)
- #define PHY_LP2HS_TIME(lbcc)		(((lbcc) & 0xff) << 16)
-@@ -170,12 +186,15 @@
- #define PHY_UNSHUTDOWNZ			BIT(0)
- 
- #define DSI_PHY_IF_CFG			0xa4
--#define N_LANES(n)			((((n) - 1) & 0x3) << 0)
- #define PHY_STOP_WAIT_TIME(cycle)	(((cycle) & 0xff) << 8)
-+#define N_LANES(n)			(((n) - 1) & 0x3)
-+
-+#define DSI_PHY_ULPS_CTRL		0xa8
-+#define DSI_PHY_TX_TRIGGERS		0xac
- 
- #define DSI_PHY_STATUS			0xb0
--#define LOCK				BIT(0)
--#define STOP_STATE_CLK_LANE		BIT(2)
-+#define PHY_STOP_STATE_CLK_LANE		BIT(2)
-+#define PHY_LOCK			BIT(0)
- 
- #define DSI_PHY_TST_CTRL0		0xb4
- #define PHY_TESTCLK			BIT(1)
-@@ -187,12 +206,13 @@
- #define PHY_TESTEN			BIT(16)
- #define PHY_UNTESTEN			0
- #define PHY_TESTDOUT(n)			(((n) & 0xff) << 8)
--#define PHY_TESTDIN(n)			(((n) & 0xff) << 0)
-+#define PHY_TESTDIN(n)			((n) & 0xff)
- 
- #define DSI_INT_ST0			0xbc
- #define DSI_INT_ST1			0xc0
- #define DSI_INT_MSK0			0xc4
- #define DSI_INT_MSK1			0xc8
-+#define DSI_PHY_TMR_RD_CFG		0xf4
- 
- #define PHY_STATUS_TIMEOUT_US		10000
- #define CMD_PKT_STATUS_TIMEOUT_US	20000
-@@ -201,7 +221,6 @@ struct dw_mipi_dsi {
- 	struct drm_bridge bridge;
- 	struct mipi_dsi_host dsi_host;
- 	struct drm_bridge *panel_bridge;
--	bool is_panel_bridge;
- 	struct device *dev;
- 	void __iomem *base;
- 
-@@ -277,7 +296,6 @@ static int dw_mipi_dsi_host_attach(struc
- 		bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI);
- 		if (IS_ERR(bridge))
- 			return PTR_ERR(bridge);
--		dsi->is_panel_bridge = true;
- 	}
- 
- 	dsi->panel_bridge = bridge;
-@@ -292,8 +310,7 @@ static int dw_mipi_dsi_host_detach(struc
- {
- 	struct dw_mipi_dsi *dsi = host_to_dsi(host);
- 
--	if (dsi->is_panel_bridge)
--		drm_panel_bridge_remove(dsi->panel_bridge);
-+	drm_of_panel_bridge_remove(host->dev->of_node, 1, 0);
- 
- 	drm_bridge_remove(&dsi->bridge);
- 
-@@ -307,7 +324,7 @@ static void dw_mipi_message_config(struc
- 	u32 val = 0;
- 
- 	if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
--		val |= EN_ACK_RQST;
-+		val |= ACK_RQST_EN;
- 	if (lpm)
- 		val |= CMD_MODE_ALL_LP;
- 
-@@ -506,8 +523,8 @@ static void dw_mipi_dsi_init(struct dw_m
- 	 * timeout clock division should be computed with the
- 	 * high speed transmission counter timeout and byte lane...
- 	 */
--	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
--		  TX_ESC_CLK_DIVIDSION(esc_clk_division));
-+	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
-+		  TX_ESC_CLK_DIVISION(esc_clk_division));
- }
- 
- static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
-@@ -520,7 +537,7 @@ static void dw_mipi_dsi_dpi_config(struc
- 		color = DPI_COLOR_CODING_24BIT;
- 		break;
- 	case MIPI_DSI_FMT_RGB666:
--		color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
-+		color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
- 		break;
- 	case MIPI_DSI_FMT_RGB666_PACKED:
- 		color = DPI_COLOR_CODING_18BIT_1;
-@@ -535,7 +552,7 @@ static void dw_mipi_dsi_dpi_config(struc
- 	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
- 		val |= HSYNC_ACTIVE_LOW;
- 
--	dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
-+	dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
- 	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
- 	dsi_write(dsi, DSI_DPI_CFG_POL, val);
- 	/*
-@@ -550,7 +567,7 @@ static void dw_mipi_dsi_dpi_config(struc
- 
- static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
- {
--	dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
-+	dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
- }
- 
- static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
-@@ -571,7 +588,7 @@ static void dw_mipi_dsi_command_mode_con
- 	/*
- 	 * TODO dw drv improvements
- 	 * compute high speed transmission counter timeout according
--	 * to the timeout clock division (TO_CLK_DIVIDSION) and byte lane...
-+	 * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
- 	 */
- 	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
- 	/*
-@@ -684,13 +701,13 @@ static void dw_mipi_dsi_dphy_enable(stru
- 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
- 		  PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
- 
--	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
--				 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
-+	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
-+				 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
- 	if (ret < 0)
- 		DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
- 
- 	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
--				 val, val & STOP_STATE_CLK_LANE, 1000,
-+				 val, val & PHY_STOP_STATE_CLK_LANE, 1000,
- 				 PHY_STATUS_TIMEOUT_US);
- 	if (ret < 0)
- 		DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
-@@ -865,15 +882,14 @@ __dw_mipi_dsi_probe(struct platform_devi
- 	 * Note that the reset was not defined in the initial device tree, so
- 	 * we have to be prepared for it not being found.
- 	 */
--	apb_rst = devm_reset_control_get(dev, "apb");
-+	apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb");
- 	if (IS_ERR(apb_rst)) {
- 		ret = PTR_ERR(apb_rst);
--		if (ret == -ENOENT) {
--			apb_rst = NULL;
--		} else {
-+
-+		if (ret != -EPROBE_DEFER)
- 			dev_err(dev, "Unable to get reset control: %d\n", ret);
--			return ERR_PTR(ret);
--		}
-+
-+		return ERR_PTR(ret);
- 	}
- 
- 	if (apb_rst) {
---- linux-4.14/drivers/gpu/drm/cirrus/cirrus_mode.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/cirrus/cirrus_mode.c	2017-12-14 06:39:58.489903619 +0100
-@@ -457,7 +457,7 @@ static struct drm_encoder *cirrus_connec
- 	int enc_id = connector->encoder_ids[0];
- 	/* pick the encoder ids */
- 	if (enc_id)
--		return drm_encoder_find(connector->dev, enc_id);
-+		return drm_encoder_find(connector->dev, NULL, enc_id);
- 	return NULL;
- }
- 
---- linux-4.14/drivers/gpu/drm/drm_agpsupport.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_agpsupport.c	2017-12-14 06:39:58.489903619 +0100
-@@ -70,7 +70,6 @@ int drm_agp_info(struct drm_device *dev,
- 
- 	return 0;
- }
--
- EXPORT_SYMBOL(drm_agp_info);
- 
- int drm_agp_info_ioctl(struct drm_device *dev, void *data,
-@@ -95,18 +94,18 @@ int drm_agp_info_ioctl(struct drm_device
-  * Verifies the AGP device hasn't been acquired before and calls
-  * \c agp_backend_acquire.
-  */
--int drm_agp_acquire(struct drm_device * dev)
-+int drm_agp_acquire(struct drm_device *dev)
- {
- 	if (!dev->agp)
- 		return -ENODEV;
- 	if (dev->agp->acquired)
- 		return -EBUSY;
--	if (!(dev->agp->bridge = agp_backend_acquire(dev->pdev)))
-+	dev->agp->bridge = agp_backend_acquire(dev->pdev);
-+	if (!dev->agp->bridge)
- 		return -ENODEV;
- 	dev->agp->acquired = 1;
- 	return 0;
- }
--
- EXPORT_SYMBOL(drm_agp_acquire);
- 
- /**
-@@ -135,7 +134,7 @@ int drm_agp_acquire_ioctl(struct drm_dev
-  *
-  * Verifies the AGP device has been acquired and calls \c agp_backend_release.
-  */
--int drm_agp_release(struct drm_device * dev)
-+int drm_agp_release(struct drm_device *dev)
- {
- 	if (!dev->agp || !dev->agp->acquired)
- 		return -EINVAL;
-@@ -161,7 +160,7 @@ int drm_agp_release_ioctl(struct drm_dev
-  * Verifies the AGP device has been acquired but not enabled, and calls
-  * \c agp_enable.
-  */
--int drm_agp_enable(struct drm_device * dev, struct drm_agp_mode mode)
-+int drm_agp_enable(struct drm_device *dev, struct drm_agp_mode mode)
- {
- 	if (!dev->agp || !dev->agp->acquired)
- 		return -EINVAL;
-@@ -171,7 +170,6 @@ int drm_agp_enable(struct drm_device * d
- 	dev->agp->enabled = 1;
- 	return 0;
- }
--
- EXPORT_SYMBOL(drm_agp_enable);
- 
- int drm_agp_enable_ioctl(struct drm_device *dev, void *data,
-@@ -203,12 +201,14 @@ int drm_agp_alloc(struct drm_device *dev
- 
- 	if (!dev->agp || !dev->agp->acquired)
- 		return -EINVAL;
--	if (!(entry = kzalloc(sizeof(*entry), GFP_KERNEL)))
-+	entry = kzalloc(sizeof(*entry), GFP_KERNEL);
-+	if (!entry)
- 		return -ENOMEM;
- 
- 	pages = (request->size + PAGE_SIZE - 1) / PAGE_SIZE;
- 	type = (u32) request->type;
--	if (!(memory = agp_allocate_memory(dev->agp->bridge, pages, type))) {
-+	memory = agp_allocate_memory(dev->agp->bridge, pages, type);
-+	if (!memory) {
- 		kfree(entry);
- 		return -ENOMEM;
- 	}
-@@ -244,8 +244,8 @@ int drm_agp_alloc_ioctl(struct drm_devic
-  *
-  * Walks through drm_agp_head::memory until finding a matching handle.
-  */
--static struct drm_agp_mem *drm_agp_lookup_entry(struct drm_device * dev,
--					   unsigned long handle)
-+static struct drm_agp_mem *drm_agp_lookup_entry(struct drm_device *dev,
-+						unsigned long handle)
- {
- 	struct drm_agp_mem *entry;
- 
-@@ -275,9 +275,8 @@ int drm_agp_unbind(struct drm_device *de
- 
- 	if (!dev->agp || !dev->agp->acquired)
- 		return -EINVAL;
--	if (!(entry = drm_agp_lookup_entry(dev, request->handle)))
--		return -EINVAL;
--	if (!entry->bound)
-+	entry = drm_agp_lookup_entry(dev, request->handle);
-+	if (!entry || !entry->bound)
- 		return -EINVAL;
- 	ret = drm_unbind_agp(entry->memory);
- 	if (ret == 0)
-@@ -316,12 +315,12 @@ int drm_agp_bind(struct drm_device *dev,
- 
- 	if (!dev->agp || !dev->agp->acquired)
- 		return -EINVAL;
--	if (!(entry = drm_agp_lookup_entry(dev, request->handle)))
--		return -EINVAL;
--	if (entry->bound)
-+	entry = drm_agp_lookup_entry(dev, request->handle);
-+	if (!entry || entry->bound)
- 		return -EINVAL;
- 	page = (request->offset + PAGE_SIZE - 1) / PAGE_SIZE;
--	if ((retcode = drm_bind_agp(entry->memory, page)))
-+	retcode = drm_bind_agp(entry->memory, page);
-+	if (retcode)
- 		return retcode;
- 	entry->bound = dev->agp->base + (page << PAGE_SHIFT);
- 	DRM_DEBUG("base = 0x%lx entry->bound = 0x%lx\n",
-@@ -359,7 +358,8 @@ int drm_agp_free(struct drm_device *dev,
- 
- 	if (!dev->agp || !dev->agp->acquired)
- 		return -EINVAL;
--	if (!(entry = drm_agp_lookup_entry(dev, request->handle)))
-+	entry = drm_agp_lookup_entry(dev, request->handle);
-+	if (!entry)
- 		return -EINVAL;
- 	if (entry->bound)
- 		drm_unbind_agp(entry->memory);
-@@ -373,7 +373,6 @@ int drm_agp_free(struct drm_device *dev,
- EXPORT_SYMBOL(drm_agp_free);
- 
- 
--
- int drm_agp_free_ioctl(struct drm_device *dev, void *data,
- 		       struct drm_file *file_priv)
- {
-@@ -398,11 +397,13 @@ struct drm_agp_head *drm_agp_init(struct
- {
- 	struct drm_agp_head *head = NULL;
- 
--	if (!(head = kzalloc(sizeof(*head), GFP_KERNEL)))
-+	head = kzalloc(sizeof(*head), GFP_KERNEL);
-+	if (!head)
- 		return NULL;
- 	head->bridge = agp_find_bridge(dev->pdev);
- 	if (!head->bridge) {
--		if (!(head->bridge = agp_backend_acquire(dev->pdev))) {
-+		head->bridge = agp_backend_acquire(dev->pdev);
-+		if (!head->bridge) {
- 			kfree(head);
- 			return NULL;
- 		}
---- linux-4.14/drivers/gpu/drm/drm_atomic.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_atomic.c	2017-12-14 06:39:58.489903619 +0100
-@@ -163,13 +163,6 @@ void drm_atomic_state_default_clear(stru
- 		crtc->funcs->atomic_destroy_state(crtc,
- 						  state->crtcs[i].state);
- 
--		if (state->crtcs[i].commit) {
--			kfree(state->crtcs[i].commit->event);
--			state->crtcs[i].commit->event = NULL;
--			drm_crtc_commit_put(state->crtcs[i].commit);
--		}
--
--		state->crtcs[i].commit = NULL;
- 		state->crtcs[i].ptr = NULL;
- 		state->crtcs[i].state = NULL;
- 	}
-@@ -189,9 +182,6 @@ void drm_atomic_state_default_clear(stru
- 	for (i = 0; i < state->num_private_objs; i++) {
- 		struct drm_private_obj *obj = state->private_objs[i].ptr;
- 
--		if (!obj)
--			continue;
--
- 		obj->funcs->atomic_destroy_state(obj,
- 						 state->private_objs[i].state);
- 		state->private_objs[i].ptr = NULL;
-@@ -199,6 +189,10 @@ void drm_atomic_state_default_clear(stru
- 	}
- 	state->num_private_objs = 0;
- 
-+	if (state->fake_commit) {
-+		drm_crtc_commit_put(state->fake_commit);
-+		state->fake_commit = NULL;
-+	}
- }
- EXPORT_SYMBOL(drm_atomic_state_default_clear);
- 
-@@ -721,7 +715,7 @@ static int drm_atomic_plane_set_property
- 	struct drm_mode_config *config = &dev->mode_config;
- 
- 	if (property == config->prop_fb_id) {
--		struct drm_framebuffer *fb = drm_framebuffer_lookup(dev, val);
-+		struct drm_framebuffer *fb = drm_framebuffer_lookup(dev, NULL, val);
- 		drm_atomic_set_fb_for_plane(state, fb);
- 		if (fb)
- 			drm_framebuffer_put(fb);
-@@ -737,7 +731,7 @@ static int drm_atomic_plane_set_property
- 			return -EINVAL;
- 
- 	} else if (property == config->prop_crtc_id) {
--		struct drm_crtc *crtc = drm_crtc_find(dev, val);
-+		struct drm_crtc *crtc = drm_crtc_find(dev, NULL, val);
- 		return drm_atomic_set_crtc_for_plane(state, crtc);
- 	} else if (property == config->prop_crtc_x) {
- 		state->crtc_x = U642I64(val);
-@@ -1152,7 +1146,7 @@ static int drm_atomic_connector_set_prop
- 	struct drm_mode_config *config = &dev->mode_config;
- 
- 	if (property == config->prop_crtc_id) {
--		struct drm_crtc *crtc = drm_crtc_find(dev, val);
-+		struct drm_crtc *crtc = drm_crtc_find(dev, NULL, val);
- 		return drm_atomic_set_crtc_for_connector(state, crtc);
- 	} else if (property == config->dpms_property) {
- 		/* setting DPMS property requires special handling, which
-@@ -2237,7 +2231,7 @@ int drm_mode_atomic_ioctl(struct drm_dev
- 			(arg->flags & DRM_MODE_PAGE_FLIP_EVENT))
- 		return -EINVAL;
- 
--	drm_modeset_acquire_init(&ctx, 0);
-+	drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
- 
- 	state = drm_atomic_state_alloc(dev);
- 	if (!state)
-@@ -2262,7 +2256,7 @@ retry:
- 			goto out;
- 		}
- 
--		obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_ANY);
-+		obj = drm_mode_object_find(dev, file_priv, obj_id, DRM_MODE_OBJECT_ANY);
- 		if (!obj) {
- 			ret = -ENOENT;
- 			goto out;
-@@ -2350,8 +2344,9 @@ out:
- 
- 	if (ret == -EDEADLK) {
- 		drm_atomic_state_clear(state);
--		drm_modeset_backoff(&ctx);
--		goto retry;
-+		ret = drm_modeset_backoff(&ctx);
-+		if (!ret)
-+			goto retry;
- 	}
- 
- 	drm_atomic_state_put(state);
---- linux-4.14/drivers/gpu/drm/drm_atomic_helper.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_atomic_helper.c	2017-12-14 06:39:58.489903619 +0100
-@@ -1262,12 +1262,12 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for
- void drm_atomic_helper_wait_for_flip_done(struct drm_device *dev,
- 					  struct drm_atomic_state *old_state)
- {
--	struct drm_crtc_state *unused;
-+	struct drm_crtc_state *new_crtc_state;
- 	struct drm_crtc *crtc;
- 	int i;
- 
--	for_each_new_crtc_in_state(old_state, crtc, unused, i) {
--		struct drm_crtc_commit *commit = old_state->crtcs[i].commit;
-+	for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
-+		struct drm_crtc_commit *commit = new_crtc_state->commit;
- 		int ret;
- 
- 		if (!commit)
-@@ -1388,35 +1388,31 @@ int drm_atomic_helper_async_check(struct
- {
- 	struct drm_crtc *crtc;
- 	struct drm_crtc_state *crtc_state;
--	struct drm_crtc_commit *commit;
--	struct drm_plane *__plane, *plane = NULL;
--	struct drm_plane_state *__plane_state, *plane_state = NULL;
-+	struct drm_plane *plane;
-+	struct drm_plane_state *old_plane_state, *new_plane_state;
- 	const struct drm_plane_helper_funcs *funcs;
--	int i, j, n_planes = 0;
-+	int i, n_planes = 0;
- 
- 	for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
- 		if (drm_atomic_crtc_needs_modeset(crtc_state))
- 			return -EINVAL;
- 	}
- 
--	for_each_new_plane_in_state(state, __plane, __plane_state, i) {
-+	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
- 		n_planes++;
--		plane = __plane;
--		plane_state = __plane_state;
--	}
- 
- 	/* FIXME: we support only single plane updates for now */
--	if (!plane || n_planes != 1)
-+	if (n_planes != 1)
- 		return -EINVAL;
- 
--	if (!plane_state->crtc)
-+	if (!new_plane_state->crtc)
- 		return -EINVAL;
- 
- 	funcs = plane->helper_private;
- 	if (!funcs->atomic_async_update)
- 		return -EINVAL;
- 
--	if (plane_state->fence)
-+	if (new_plane_state->fence)
- 		return -EINVAL;
- 
- 	/*
-@@ -1424,31 +1420,11 @@ int drm_atomic_helper_async_check(struct
- 	 * the plane.  This prevents our async update's changes from getting
- 	 * overridden by a previous synchronous update's state.
- 	 */
--	for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
--		if (plane->crtc != crtc)
--			continue;
--
--		spin_lock(&crtc->commit_lock);
--		commit = list_first_entry_or_null(&crtc->commit_list,
--						  struct drm_crtc_commit,
--						  commit_entry);
--		if (!commit) {
--			spin_unlock(&crtc->commit_lock);
--			continue;
--		}
--		spin_unlock(&crtc->commit_lock);
-+	if (old_plane_state->commit &&
-+	    !try_wait_for_completion(&old_plane_state->commit->hw_done))
-+		return -EBUSY;
- 
--		if (!crtc->state->state)
--			continue;
--
--		for_each_plane_in_state(crtc->state->state, __plane,
--					__plane_state, j) {
--			if (__plane == plane)
--				return -EINVAL;
--		}
--	}
--
--	return funcs->atomic_async_check(plane, plane_state);
-+	return funcs->atomic_async_check(plane, new_plane_state);
- }
- EXPORT_SYMBOL(drm_atomic_helper_async_check);
- 
-@@ -1633,8 +1609,7 @@ static int stall_checks(struct drm_crtc
- 				return -EBUSY;
- 			}
- 		} else if (i == 1) {
--			stall_commit = commit;
--			drm_crtc_commit_get(stall_commit);
-+			stall_commit = drm_crtc_commit_get(commit);
- 			break;
- 		}
- 
-@@ -1668,6 +1643,38 @@ static void release_crtc_commit(struct c
- 	drm_crtc_commit_put(commit);
- }
- 
-+static void init_commit(struct drm_crtc_commit *commit, struct drm_crtc *crtc)
-+{
-+	init_completion(&commit->flip_done);
-+	init_completion(&commit->hw_done);
-+	init_completion(&commit->cleanup_done);
-+	INIT_LIST_HEAD(&commit->commit_entry);
-+	kref_init(&commit->ref);
-+	commit->crtc = crtc;
-+}
-+
-+static struct drm_crtc_commit *
-+crtc_or_fake_commit(struct drm_atomic_state *state, struct drm_crtc *crtc)
-+{
-+	if (crtc) {
-+		struct drm_crtc_state *new_crtc_state;
-+
-+		new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
-+
-+		return new_crtc_state->commit;
-+	}
-+
-+	if (!state->fake_commit) {
-+		state->fake_commit = kzalloc(sizeof(*state->fake_commit), GFP_KERNEL);
-+		if (!state->fake_commit)
-+			return NULL;
-+
-+		init_commit(state->fake_commit, NULL);
-+	}
-+
-+	return state->fake_commit;
-+}
-+
- /**
-  * drm_atomic_helper_setup_commit - setup possibly nonblocking commit
-  * @state: new modeset state to be committed
-@@ -1697,7 +1704,7 @@ static void release_crtc_commit(struct c
-  * drm_atomic_helper_commit_cleanup_done().
-  *
-  * This is all implemented by in drm_atomic_helper_commit(), giving drivers a
-- * complete and esay-to-use default implementation of the atomic_commit() hook.
-+ * complete and easy-to-use default implementation of the atomic_commit() hook.
-  *
-  * The tracking of asynchronously executed and still pending commits is done
-  * using the core structure &drm_crtc_commit.
-@@ -1716,6 +1723,10 @@ int drm_atomic_helper_setup_commit(struc
- {
- 	struct drm_crtc *crtc;
- 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
-+	struct drm_connector *conn;
-+	struct drm_connector_state *old_conn_state, *new_conn_state;
-+	struct drm_plane *plane;
-+	struct drm_plane_state *old_plane_state, *new_plane_state;
- 	struct drm_crtc_commit *commit;
- 	int i, ret;
- 
-@@ -1724,14 +1735,9 @@ int drm_atomic_helper_setup_commit(struc
- 		if (!commit)
- 			return -ENOMEM;
- 
--		init_completion(&commit->flip_done);
--		init_completion(&commit->hw_done);
--		init_completion(&commit->cleanup_done);
--		INIT_LIST_HEAD(&commit->commit_entry);
--		kref_init(&commit->ref);
--		commit->crtc = crtc;
-+		init_commit(commit, crtc);
- 
--		state->crtcs[i].commit = commit;
-+		new_crtc_state->commit = commit;
- 
- 		ret = stall_checks(crtc, nonblock);
- 		if (ret)
-@@ -1765,25 +1771,46 @@ int drm_atomic_helper_setup_commit(struc
- 		drm_crtc_commit_get(commit);
- 	}
- 
--	return 0;
--}
--EXPORT_SYMBOL(drm_atomic_helper_setup_commit);
-+	for_each_oldnew_connector_in_state(state, conn, old_conn_state, new_conn_state, i) {
-+		/* commit tracked through new_crtc_state->commit, no need to do it explicitly */
-+		if (new_conn_state->crtc)
-+			continue;
- 
-+		/* Userspace is not allowed to get ahead of the previous
-+		 * commit with nonblocking ones. */
-+		if (nonblock && old_conn_state->commit &&
-+		    !try_wait_for_completion(&old_conn_state->commit->flip_done))
-+			return -EBUSY;
- 
--static struct drm_crtc_commit *preceeding_commit(struct drm_crtc *crtc)
--{
--	struct drm_crtc_commit *commit;
--	int i = 0;
-+		commit = crtc_or_fake_commit(state, old_conn_state->crtc);
-+		if (!commit)
-+			return -ENOMEM;
- 
--	list_for_each_entry(commit, &crtc->commit_list, commit_entry) {
--		/* skip the first entry, that's the current commit */
--		if (i == 1)
--			return commit;
--		i++;
-+		new_conn_state->commit = drm_crtc_commit_get(commit);
- 	}
- 
--	return NULL;
-+	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
-+		/*
-+		 * Unlike connectors, always track planes explicitly for
-+		 * async pageflip support.
-+		 */
-+
-+		/* Userspace is not allowed to get ahead of the previous
-+		 * commit with nonblocking ones. */
-+		if (nonblock && old_plane_state->commit &&
-+		    !try_wait_for_completion(&old_plane_state->commit->flip_done))
-+			return -EBUSY;
-+
-+		commit = crtc_or_fake_commit(state, old_plane_state->crtc);
-+		if (!commit)
-+			return -ENOMEM;
-+
-+		new_plane_state->commit = drm_crtc_commit_get(commit);
-+	}
-+
-+	return 0;
- }
-+EXPORT_SYMBOL(drm_atomic_helper_setup_commit);
- 
- /**
-  * drm_atomic_helper_wait_for_dependencies - wait for required preceeding commits
-@@ -1792,7 +1819,7 @@ static struct drm_crtc_commit *preceedin
-  * This function waits for all preceeding commits that touch the same CRTC as
-  * @old_state to both be committed to the hardware (as signalled by
-  * drm_atomic_helper_commit_hw_done) and executed by the hardware (as signalled
-- * by calling drm_crtc_vblank_send_event() on the &drm_crtc_state.event).
-+ * by calling drm_crtc_send_vblank_event() on the &drm_crtc_state.event).
-  *
-  * This is part of the atomic helper support for nonblocking commits, see
-  * drm_atomic_helper_setup_commit() for an overview.
-@@ -1800,17 +1827,17 @@ static struct drm_crtc_commit *preceedin
- void drm_atomic_helper_wait_for_dependencies(struct drm_atomic_state *old_state)
- {
- 	struct drm_crtc *crtc;
--	struct drm_crtc_state *new_crtc_state;
-+	struct drm_crtc_state *old_crtc_state;
-+	struct drm_plane *plane;
-+	struct drm_plane_state *old_plane_state;
-+	struct drm_connector *conn;
-+	struct drm_connector_state *old_conn_state;
- 	struct drm_crtc_commit *commit;
- 	int i;
- 	long ret;
- 
--	for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
--		spin_lock(&crtc->commit_lock);
--		commit = preceeding_commit(crtc);
--		if (commit)
--			drm_crtc_commit_get(commit);
--		spin_unlock(&crtc->commit_lock);
-+	for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
-+		commit = old_crtc_state->commit;
- 
- 		if (!commit)
- 			continue;
-@@ -1828,8 +1855,48 @@ void drm_atomic_helper_wait_for_dependen
- 		if (ret == 0)
- 			DRM_ERROR("[CRTC:%d:%s] flip_done timed out\n",
- 				  crtc->base.id, crtc->name);
-+	}
-+
-+	for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
-+		commit = old_conn_state->commit;
- 
--		drm_crtc_commit_put(commit);
-+		if (!commit)
-+			continue;
-+
-+		ret = wait_for_completion_timeout(&commit->hw_done,
-+						  10*HZ);
-+		if (ret == 0)
-+			DRM_ERROR("[CONNECTOR:%d:%s] hw_done timed out\n",
-+				  conn->base.id, conn->name);
-+
-+		/* Currently no support for overwriting flips, hence
-+		 * stall for previous one to execute completely. */
-+		ret = wait_for_completion_timeout(&commit->flip_done,
-+						  10*HZ);
-+		if (ret == 0)
-+			DRM_ERROR("[CONNECTOR:%d:%s] flip_done timed out\n",
-+				  conn->base.id, conn->name);
-+	}
-+
-+	for_each_old_plane_in_state(old_state, plane, old_plane_state, i) {
-+		commit = old_plane_state->commit;
-+
-+		if (!commit)
-+			continue;
-+
-+		ret = wait_for_completion_timeout(&commit->hw_done,
-+						  10*HZ);
-+		if (ret == 0)
-+			DRM_ERROR("[PLANE:%d:%s] hw_done timed out\n",
-+				  plane->base.id, plane->name);
-+
-+		/* Currently no support for overwriting flips, hence
-+		 * stall for previous one to execute completely. */
-+		ret = wait_for_completion_timeout(&commit->flip_done,
-+						  10*HZ);
-+		if (ret == 0)
-+			DRM_ERROR("[PLANE:%d:%s] flip_done timed out\n",
-+				  plane->base.id, plane->name);
- 	}
- }
- EXPORT_SYMBOL(drm_atomic_helper_wait_for_dependencies);
-@@ -1852,19 +1919,34 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for
- void drm_atomic_helper_commit_hw_done(struct drm_atomic_state *old_state)
- {
- 	struct drm_crtc *crtc;
--	struct drm_crtc_state *new_crtc_state;
-+	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
- 	struct drm_crtc_commit *commit;
- 	int i;
- 
--	for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
--		commit = old_state->crtcs[i].commit;
-+	for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state, new_crtc_state, i) {
-+		commit = new_crtc_state->commit;
- 		if (!commit)
- 			continue;
- 
-+		/*
-+		 * copy new_crtc_state->commit to old_crtc_state->commit,
-+		 * it's unsafe to touch new_crtc_state after hw_done,
-+		 * but we still need to do so in cleanup_done().
-+		 */
-+		if (old_crtc_state->commit)
-+			drm_crtc_commit_put(old_crtc_state->commit);
-+
-+		old_crtc_state->commit = drm_crtc_commit_get(commit);
-+
- 		/* backend must have consumed any event by now */
- 		WARN_ON(new_crtc_state->event);
- 		complete_all(&commit->hw_done);
- 	}
-+
-+	if (old_state->fake_commit) {
-+		complete_all(&old_state->fake_commit->hw_done);
-+		complete_all(&old_state->fake_commit->flip_done);
-+	}
- }
- EXPORT_SYMBOL(drm_atomic_helper_commit_hw_done);
- 
-@@ -1882,39 +1964,25 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_h
- void drm_atomic_helper_commit_cleanup_done(struct drm_atomic_state *old_state)
- {
- 	struct drm_crtc *crtc;
--	struct drm_crtc_state *new_crtc_state;
-+	struct drm_crtc_state *old_crtc_state;
- 	struct drm_crtc_commit *commit;
- 	int i;
--	long ret;
- 
--	for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
--		commit = old_state->crtcs[i].commit;
-+	for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
-+		commit = old_crtc_state->commit;
- 		if (WARN_ON(!commit))
- 			continue;
- 
- 		complete_all(&commit->cleanup_done);
- 		WARN_ON(!try_wait_for_completion(&commit->hw_done));
- 
--		/* commit_list borrows our reference, need to remove before we
--		 * clean up our drm_atomic_state. But only after it actually
--		 * completed, otherwise subsequent commits won't stall properly. */
--		if (try_wait_for_completion(&commit->flip_done))
--			goto del_commit;
--
--		/* We must wait for the vblank event to signal our completion
--		 * before releasing our reference, since the vblank work does
--		 * not hold a reference of its own. */
--		ret = wait_for_completion_timeout(&commit->flip_done,
--						  10*HZ);
--		if (ret == 0)
--			DRM_ERROR("[CRTC:%d:%s] flip_done timed out\n",
--				  crtc->base.id, crtc->name);
--
--del_commit:
- 		spin_lock(&crtc->commit_lock);
- 		list_del(&commit->commit_entry);
- 		spin_unlock(&crtc->commit_lock);
- 	}
-+
-+	if (old_state->fake_commit)
-+		complete_all(&old_state->fake_commit->cleanup_done);
- }
- EXPORT_SYMBOL(drm_atomic_helper_commit_cleanup_done);
- 
-@@ -2294,20 +2362,44 @@ int drm_atomic_helper_swap_state(struct
- 	struct drm_private_state *old_obj_state, *new_obj_state;
- 
- 	if (stall) {
--		for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
--			spin_lock(&crtc->commit_lock);
--			commit = list_first_entry_or_null(&crtc->commit_list,
--					struct drm_crtc_commit, commit_entry);
--			if (commit)
--				drm_crtc_commit_get(commit);
--			spin_unlock(&crtc->commit_lock);
-+		/*
-+		 * We have to stall for hw_done here before
-+		 * drm_atomic_helper_wait_for_dependencies() because flip
-+		 * depth > 1 is not yet supported by all drivers. As long as
-+		 * obj->state is directly dereferenced anywhere in the drivers
-+		 * atomic_commit_tail function, then it's unsafe to swap state
-+		 * before drm_atomic_helper_commit_hw_done() is called.
-+		 */
-+
-+		for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
-+			commit = old_crtc_state->commit;
-+
-+			if (!commit)
-+				continue;
-+
-+			ret = wait_for_completion_interruptible(&commit->hw_done);
-+			if (ret)
-+				return ret;
-+		}
-+
-+		for_each_old_connector_in_state(state, connector, old_conn_state, i) {
-+			commit = old_conn_state->commit;
- 
- 			if (!commit)
- 				continue;
- 
- 			ret = wait_for_completion_interruptible(&commit->hw_done);
--			drm_crtc_commit_put(commit);
-+			if (ret)
-+				return ret;
-+		}
-+
-+		for_each_old_plane_in_state(state, plane, old_plane_state, i) {
-+			commit = old_plane_state->commit;
- 
-+			if (!commit)
-+				continue;
-+
-+			ret = wait_for_completion_interruptible(&commit->hw_done);
- 			if (ret)
- 				return ret;
- 		}
-@@ -2332,13 +2424,13 @@ int drm_atomic_helper_swap_state(struct
- 		state->crtcs[i].state = old_crtc_state;
- 		crtc->state = new_crtc_state;
- 
--		if (state->crtcs[i].commit) {
-+		if (new_crtc_state->commit) {
- 			spin_lock(&crtc->commit_lock);
--			list_add(&state->crtcs[i].commit->commit_entry,
-+			list_add(&new_crtc_state->commit->commit_entry,
- 				 &crtc->commit_list);
- 			spin_unlock(&crtc->commit_lock);
- 
--			state->crtcs[i].commit->event = NULL;
-+			new_crtc_state->commit->event = NULL;
- 		}
- 	}
- 
-@@ -3115,7 +3207,7 @@ struct drm_encoder *
- drm_atomic_helper_best_encoder(struct drm_connector *connector)
- {
- 	WARN_ON(connector->encoder_ids[1]);
--	return drm_encoder_find(connector->dev, connector->encoder_ids[0]);
-+	return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
- }
- EXPORT_SYMBOL(drm_atomic_helper_best_encoder);
- 
-@@ -3187,6 +3279,7 @@ void __drm_atomic_helper_crtc_duplicate_
- 	state->connectors_changed = false;
- 	state->color_mgmt_changed = false;
- 	state->zpos_changed = false;
-+	state->commit = NULL;
- 	state->event = NULL;
- 	state->pageflip_flags = 0;
- }
-@@ -3225,6 +3318,12 @@ EXPORT_SYMBOL(drm_atomic_helper_crtc_dup
-  */
- void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc_state *state)
- {
-+	if (state->commit) {
-+		kfree(state->commit->event);
-+		state->commit->event = NULL;
-+		drm_crtc_commit_put(state->commit);
-+	}
-+
- 	drm_property_blob_put(state->mode_blob);
- 	drm_property_blob_put(state->degamma_lut);
- 	drm_property_blob_put(state->ctm);
-@@ -3287,6 +3386,7 @@ void __drm_atomic_helper_plane_duplicate
- 		drm_framebuffer_get(state->fb);
- 
- 	state->fence = NULL;
-+	state->commit = NULL;
- }
- EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state);
- 
-@@ -3328,6 +3428,9 @@ void __drm_atomic_helper_plane_destroy_s
- 
- 	if (state->fence)
- 		dma_fence_put(state->fence);
-+
-+	if (state->commit)
-+		drm_crtc_commit_put(state->commit);
- }
- EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);
- 
-@@ -3406,6 +3509,7 @@ __drm_atomic_helper_connector_duplicate_
- 	memcpy(state, connector->state, sizeof(*state));
- 	if (state->crtc)
- 		drm_connector_get(connector);
-+	state->commit = NULL;
- }
- EXPORT_SYMBOL(__drm_atomic_helper_connector_duplicate_state);
- 
-@@ -3532,6 +3636,9 @@ __drm_atomic_helper_connector_destroy_st
- {
- 	if (state->crtc)
- 		drm_connector_put(state->connector);
-+
-+	if (state->commit)
-+		drm_crtc_commit_put(state->commit);
- }
- EXPORT_SYMBOL(__drm_atomic_helper_connector_destroy_state);
- 
---- linux-4.14/drivers/gpu/drm/drm_bridge.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_bridge.c	2017-12-14 06:39:58.490903620 +0100
-@@ -67,17 +67,12 @@ static LIST_HEAD(bridge_list);
-  * drm_bridge_add - add the given bridge to the global bridge list
-  *
-  * @bridge: bridge control structure
-- *
-- * RETURNS:
-- * Unconditionally returns Zero.
-  */
--int drm_bridge_add(struct drm_bridge *bridge)
-+void drm_bridge_add(struct drm_bridge *bridge)
- {
- 	mutex_lock(&bridge_lock);
- 	list_add_tail(&bridge->list, &bridge_list);
- 	mutex_unlock(&bridge_lock);
--
--	return 0;
- }
- EXPORT_SYMBOL(drm_bridge_add);
- 
---- linux-4.14/drivers/gpu/drm/drm_color_mgmt.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_color_mgmt.c	2017-12-14 06:39:58.490903620 +0100
-@@ -230,7 +230,7 @@ int drm_mode_gamma_set_ioctl(struct drm_
- 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
- 		return -EINVAL;
- 
--	crtc = drm_crtc_find(dev, crtc_lut->crtc_id);
-+	crtc = drm_crtc_find(dev, file_priv, crtc_lut->crtc_id);
- 	if (!crtc)
- 		return -ENOENT;
- 
-@@ -308,7 +308,7 @@ int drm_mode_gamma_get_ioctl(struct drm_
- 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
- 		return -EINVAL;
- 
--	crtc = drm_crtc_find(dev, crtc_lut->crtc_id);
-+	crtc = drm_crtc_find(dev, file_priv, crtc_lut->crtc_id);
- 	if (!crtc)
- 		return -ENOENT;
- 
---- linux-4.14/drivers/gpu/drm/drm_connector.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_connector.c	2017-12-14 06:39:58.490903620 +0100
-@@ -615,7 +615,6 @@ static const struct drm_prop_enum_list d
- 	{ DRM_MODE_LINK_STATUS_GOOD, "Good" },
- 	{ DRM_MODE_LINK_STATUS_BAD, "Bad" },
- };
--DRM_ENUM_NAME_FN(drm_get_link_status_name, drm_link_status_enum_list)
- 
- /**
-  * drm_display_info_set_bus_formats - set the supported bus formats
-@@ -720,6 +719,29 @@ DRM_ENUM_NAME_FN(drm_get_tv_subconnector
-  * 	callback. For atomic drivers the remapping to the "ACTIVE" property is
-  * 	implemented in the DRM core.  This is the only standard connector
-  * 	property that userspace can change.
-+ *
-+ * 	Note that this property cannot be set through the MODE_ATOMIC ioctl,
-+ * 	userspace must use "ACTIVE" on the CRTC instead.
-+ *
-+ * 	WARNING:
-+ *
-+ * 	For userspace also running on legacy drivers the "DPMS" semantics are a
-+ * 	lot more complicated. First, userspace cannot rely on the "DPMS" value
-+ * 	returned by the GETCONNECTOR actually reflecting reality, because many
-+ * 	drivers fail to update it. For atomic drivers this is taken care of in
-+ * 	drm_atomic_helper_update_legacy_modeset_state().
-+ *
-+ * 	The second issue is that the DPMS state is only well-defined when the
-+ * 	connector is connected to a CRTC. In atomic the DRM core enforces that
-+ * 	"ACTIVE" is off in such a case, no such checks exists for "DPMS".
-+ *
-+ * 	Finally, when enabling an output using the legacy SETCONFIG ioctl then
-+ * 	"DPMS" is forced to ON. But see above, that might not be reflected in
-+ * 	the software value on legacy drivers.
-+ *
-+ * 	Summarizing: Only set "DPMS" when the connector is known to be enabled,
-+ * 	assume that a successful SETCONFIG call also sets "DPMS" to on, and
-+ * 	never read back the value of "DPMS" because it can be incorrect.
-  * PATH:
-  * 	Connector path property to identify how this sink is physically
-  * 	connected. Used by DP MST. This should be set by calling
-@@ -1288,7 +1310,7 @@ int drm_mode_getconnector(struct drm_dev
- 
- 	memset(&u_mode, 0, sizeof(struct drm_mode_modeinfo));
- 
--	connector = drm_connector_lookup(dev, out_resp->connector_id);
-+	connector = drm_connector_lookup(dev, file_priv, out_resp->connector_id);
- 	if (!connector)
- 		return -ENOENT;
- 
---- linux-4.14/drivers/gpu/drm/drm_crtc.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_crtc.c	2017-12-14 06:39:58.490903620 +0100
-@@ -402,7 +402,7 @@ int drm_mode_getcrtc(struct drm_device *
- 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
- 		return -EINVAL;
- 
--	crtc = drm_crtc_find(dev, crtc_resp->crtc_id);
-+	crtc = drm_crtc_find(dev, file_priv, crtc_resp->crtc_id);
- 	if (!crtc)
- 		return -ENOENT;
- 
-@@ -569,7 +569,7 @@ int drm_mode_setcrtc(struct drm_device *
- 	if (crtc_req->x & 0xffff0000 || crtc_req->y & 0xffff0000)
- 		return -ERANGE;
- 
--	crtc = drm_crtc_find(dev, crtc_req->crtc_id);
-+	crtc = drm_crtc_find(dev, file_priv, crtc_req->crtc_id);
- 	if (!crtc) {
- 		DRM_DEBUG_KMS("Unknown CRTC ID %d\n", crtc_req->crtc_id);
- 		return -ENOENT;
-@@ -577,7 +577,7 @@ int drm_mode_setcrtc(struct drm_device *
- 	DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
- 
- 	mutex_lock(&crtc->dev->mode_config.mutex);
--	drm_modeset_acquire_init(&ctx, 0);
-+	drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
- retry:
- 	ret = drm_modeset_lock_all_ctx(crtc->dev, &ctx);
- 	if (ret)
-@@ -595,7 +595,7 @@ retry:
- 			/* Make refcounting symmetric with the lookup path. */
- 			drm_framebuffer_get(fb);
- 		} else {
--			fb = drm_framebuffer_lookup(dev, crtc_req->fb_id);
-+			fb = drm_framebuffer_lookup(dev, file_priv, crtc_req->fb_id);
- 			if (!fb) {
- 				DRM_DEBUG_KMS("Unknown FB ID%d\n",
- 						crtc_req->fb_id);
-@@ -680,7 +680,7 @@ retry:
- 				goto out;
- 			}
- 
--			connector = drm_connector_lookup(dev, out_id);
-+			connector = drm_connector_lookup(dev, file_priv, out_id);
- 			if (!connector) {
- 				DRM_DEBUG_KMS("Connector id %d unknown\n",
- 						out_id);
-@@ -717,8 +717,9 @@ out:
- 	kfree(connector_set);
- 	drm_mode_destroy(dev, mode);
- 	if (ret == -EDEADLK) {
--		drm_modeset_backoff(&ctx);
--		goto retry;
-+		ret = drm_modeset_backoff(&ctx);
-+		if (!ret)
-+			goto retry;
- 	}
- 	drm_modeset_drop_locks(&ctx);
- 	drm_modeset_acquire_fini(&ctx);
---- linux-4.14/drivers/gpu/drm/drm_crtc_helper.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_crtc_helper.c	2017-12-14 06:39:58.490903620 +0100
-@@ -562,12 +562,12 @@ int drm_crtc_helper_set_config(struct dr
- 	 * Allocate space for the backup of all (non-pointer) encoder and
- 	 * connector data.
- 	 */
--	save_encoder_crtcs = kzalloc(dev->mode_config.num_encoder *
-+	save_encoder_crtcs = kcalloc(dev->mode_config.num_encoder,
- 				sizeof(struct drm_crtc *), GFP_KERNEL);
- 	if (!save_encoder_crtcs)
- 		return -ENOMEM;
- 
--	save_connector_encoders = kzalloc(dev->mode_config.num_connector *
-+	save_connector_encoders = kcalloc(dev->mode_config.num_connector,
- 				sizeof(struct drm_encoder *), GFP_KERNEL);
- 	if (!save_connector_encoders) {
- 		kfree(save_encoder_crtcs);
---- linux-4.14/drivers/gpu/drm/drm_crtc_internal.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_crtc_internal.h	2017-12-14 06:39:58.490903620 +0100
-@@ -106,6 +106,7 @@ int drm_mode_object_add(struct drm_devic
- void drm_mode_object_register(struct drm_device *dev,
- 			      struct drm_mode_object *obj);
- struct drm_mode_object *__drm_mode_object_find(struct drm_device *dev,
-+					       struct drm_file *file_priv,
- 					       uint32_t id, uint32_t type);
- void drm_mode_object_unregister(struct drm_device *dev,
- 				struct drm_mode_object *object);
---- linux-4.14/drivers/gpu/drm/drm_debugfs_crc.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_debugfs_crc.c	2017-12-14 06:39:58.490903620 +0100
-@@ -155,7 +155,7 @@ static int crtc_crc_open(struct inode *i
- 	int ret = 0;
- 
- 	if (drm_drv_uses_atomic_modeset(crtc->dev)) {
--		ret = drm_modeset_lock_interruptible(&crtc->mutex, NULL);
-+		ret = drm_modeset_lock_single_interruptible(&crtc->mutex);
- 		if (ret)
- 			return ret;
- 
---- linux-4.14/drivers/gpu/drm/drm_dp_helper.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_dp_helper.c	2017-12-14 06:39:58.490903620 +0100
-@@ -137,8 +137,10 @@ EXPORT_SYMBOL(drm_dp_link_train_channel_
- u8 drm_dp_link_rate_to_bw_code(int link_rate)
- {
- 	switch (link_rate) {
--	case 162000:
- 	default:
-+		WARN(1, "unknown DP link rate %d, using %x\n", link_rate,
-+		     DP_LINK_BW_1_62);
-+	case 162000:
- 		return DP_LINK_BW_1_62;
- 	case 270000:
- 		return DP_LINK_BW_2_7;
-@@ -151,8 +153,9 @@ EXPORT_SYMBOL(drm_dp_link_rate_to_bw_cod
- int drm_dp_bw_code_to_link_rate(u8 link_bw)
- {
- 	switch (link_bw) {
--	case DP_LINK_BW_1_62:
- 	default:
-+		WARN(1, "unknown DP link BW code %x, using 162000\n", link_bw);
-+	case DP_LINK_BW_1_62:
- 		return 162000;
- 	case DP_LINK_BW_2_7:
- 		return 270000;
---- linux-4.14/drivers/gpu/drm/drm_dp_mst_topology.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_dp_mst_topology.c	2017-12-14 06:39:58.491903620 +0100
-@@ -294,6 +294,12 @@ static void drm_dp_encode_sideband_req(s
- 		memcpy(&buf[idx], req->u.i2c_write.bytes, req->u.i2c_write.num_bytes);
- 		idx += req->u.i2c_write.num_bytes;
- 		break;
-+
-+	case DP_POWER_DOWN_PHY:
-+	case DP_POWER_UP_PHY:
-+		buf[idx] = (req->u.port_num.port_number & 0xf) << 4;
-+		idx++;
-+		break;
- 	}
- 	raw->cur_len = idx;
- }
-@@ -538,6 +544,21 @@ fail_len:
- 	return false;
- }
- 
-+static bool drm_dp_sideband_parse_power_updown_phy_ack(struct drm_dp_sideband_msg_rx *raw,
-+						       struct drm_dp_sideband_msg_reply_body *repmsg)
-+{
-+	int idx = 1;
-+
-+	repmsg->u.port_number.port_number = (raw->msg[idx] >> 4) & 0xf;
-+	idx++;
-+	if (idx > raw->curlen) {
-+		DRM_DEBUG_KMS("power up/down phy parse length fail %d %d\n",
-+			      idx, raw->curlen);
-+		return false;
-+	}
-+	return true;
-+}
-+
- static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw,
- 					struct drm_dp_sideband_msg_reply_body *msg)
- {
-@@ -567,6 +588,9 @@ static bool drm_dp_sideband_parse_reply(
- 		return drm_dp_sideband_parse_enum_path_resources_ack(raw, msg);
- 	case DP_ALLOCATE_PAYLOAD:
- 		return drm_dp_sideband_parse_allocate_payload_ack(raw, msg);
-+	case DP_POWER_DOWN_PHY:
-+	case DP_POWER_UP_PHY:
-+		return drm_dp_sideband_parse_power_updown_phy_ack(raw, msg);
- 	default:
- 		DRM_ERROR("Got unknown reply 0x%02x\n", msg->req_type);
- 		return false;
-@@ -693,6 +717,22 @@ static int build_allocate_payload(struct
- 	return 0;
- }
- 
-+static int build_power_updown_phy(struct drm_dp_sideband_msg_tx *msg,
-+				  int port_num, bool power_up)
-+{
-+	struct drm_dp_sideband_msg_req_body req;
-+
-+	if (power_up)
-+		req.req_type = DP_POWER_UP_PHY;
-+	else
-+		req.req_type = DP_POWER_DOWN_PHY;
-+
-+	req.u.port_num.port_number = port_num;
-+	drm_dp_encode_sideband_req(&req, msg);
-+	msg->path_msg = true;
-+	return 0;
-+}
-+
- static int drm_dp_mst_assign_payload_id(struct drm_dp_mst_topology_mgr *mgr,
- 					struct drm_dp_vcpi *vcpi)
- {
-@@ -1724,6 +1764,40 @@ fail_put:
- 	return ret;
- }
- 
-+int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr,
-+				 struct drm_dp_mst_port *port, bool power_up)
-+{
-+	struct drm_dp_sideband_msg_tx *txmsg;
-+	int len, ret;
-+
-+	port = drm_dp_get_validated_port_ref(mgr, port);
-+	if (!port)
-+		return -EINVAL;
-+
-+	txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
-+	if (!txmsg) {
-+		drm_dp_put_port(port);
-+		return -ENOMEM;
-+	}
-+
-+	txmsg->dst = port->parent;
-+	len = build_power_updown_phy(txmsg, port->port_num, power_up);
-+	drm_dp_queue_down_tx(mgr, txmsg);
-+
-+	ret = drm_dp_mst_wait_tx_reply(port->parent, txmsg);
-+	if (ret > 0) {
-+		if (txmsg->reply.reply_type == 1)
-+			ret = -EINVAL;
-+		else
-+			ret = 0;
-+	}
-+	kfree(txmsg);
-+	drm_dp_put_port(port);
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL(drm_dp_send_power_updown_phy);
-+
- static int drm_dp_create_payload_step1(struct drm_dp_mst_topology_mgr *mgr,
- 				       int id,
- 				       struct drm_dp_payload *payload)
---- linux-4.14/drivers/gpu/drm/drm_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_drv.c	2017-12-14 06:39:58.491903620 +0100
-@@ -286,13 +286,13 @@ struct drm_minor *drm_minor_acquire(unsi
- 	spin_lock_irqsave(&drm_minor_lock, flags);
- 	minor = idr_find(&drm_minors_idr, minor_id);
- 	if (minor)
--		drm_dev_ref(minor->dev);
-+		drm_dev_get(minor->dev);
- 	spin_unlock_irqrestore(&drm_minor_lock, flags);
- 
- 	if (!minor) {
- 		return ERR_PTR(-ENODEV);
- 	} else if (drm_dev_is_unplugged(minor->dev)) {
--		drm_dev_unref(minor->dev);
-+		drm_dev_put(minor->dev);
- 		return ERR_PTR(-ENODEV);
- 	}
- 
-@@ -301,7 +301,7 @@ struct drm_minor *drm_minor_acquire(unsi
- 
- void drm_minor_release(struct drm_minor *minor)
- {
--	drm_dev_unref(minor->dev);
-+	drm_dev_put(minor->dev);
- }
- 
- /**
-@@ -326,11 +326,11 @@ void drm_minor_release(struct drm_minor
-  * When cleaning up a device instance everything needs to be done in reverse:
-  * First unpublish the device instance with drm_dev_unregister(). Then clean up
-  * any other resources allocated at device initialization and drop the driver's
-- * reference to &drm_device using drm_dev_unref().
-+ * reference to &drm_device using drm_dev_put().
-  *
-  * Note that the lifetime rules for &drm_device instance has still a lot of
-  * historical baggage. Hence use the reference counting provided by
-- * drm_dev_ref() and drm_dev_unref() only carefully.
-+ * drm_dev_get() and drm_dev_put() only carefully.
-  *
-  * It is recommended that drivers embed &struct drm_device into their own device
-  * structure, which is supported through drm_dev_init().
-@@ -345,7 +345,7 @@ void drm_minor_release(struct drm_minor
-  * Cleans up all DRM device, calling drm_lastclose().
-  *
-  * Note: Use of this function is deprecated. It will eventually go away
-- * completely.  Please use drm_dev_unregister() and drm_dev_unref() explicitly
-+ * completely.  Please use drm_dev_unregister() and drm_dev_put() explicitly
-  * instead to make sure that the device isn't userspace accessible any more
-  * while teardown is in progress, ensuring that userspace can't access an
-  * inconsistent state.
-@@ -360,7 +360,7 @@ void drm_put_dev(struct drm_device *dev)
- 	}
- 
- 	drm_dev_unregister(dev);
--	drm_dev_unref(dev);
-+	drm_dev_put(dev);
- }
- EXPORT_SYMBOL(drm_put_dev);
- 
-@@ -386,7 +386,7 @@ void drm_dev_unplug(struct drm_device *d
- 	mutex_lock(&drm_global_mutex);
- 	drm_device_set_unplugged(dev);
- 	if (dev->open_count == 0)
--		drm_dev_unref(dev);
-+		drm_dev_put(dev);
- 	mutex_unlock(&drm_global_mutex);
- }
- EXPORT_SYMBOL(drm_dev_unplug);
-@@ -475,8 +475,8 @@ static void drm_fs_inode_free(struct ino
-  * initialization sequence to make sure userspace can't access an inconsistent
-  * state.
-  *
-- * The initial ref-count of the object is 1. Use drm_dev_ref() and
-- * drm_dev_unref() to take and drop further ref-counts.
-+ * The initial ref-count of the object is 1. Use drm_dev_get() and
-+ * drm_dev_put() to take and drop further ref-counts.
-  *
-  * Note that for purely virtual devices @parent can be NULL.
-  *
-@@ -626,8 +626,8 @@ EXPORT_SYMBOL(drm_dev_fini);
-  * initialization sequence to make sure userspace can't access an inconsistent
-  * state.
-  *
-- * The initial ref-count of the object is 1. Use drm_dev_ref() and
-- * drm_dev_unref() to take and drop further ref-counts.
-+ * The initial ref-count of the object is 1. Use drm_dev_get() and
-+ * drm_dev_put() to take and drop further ref-counts.
-  *
-  * Note that for purely virtual devices @parent can be NULL.
-  *
-@@ -670,36 +670,49 @@ static void drm_dev_release(struct kref
- }
- 
- /**
-- * drm_dev_ref - Take reference of a DRM device
-+ * drm_dev_get - Take reference of a DRM device
-  * @dev: device to take reference of or NULL
-  *
-  * This increases the ref-count of @dev by one. You *must* already own a
-- * reference when calling this. Use drm_dev_unref() to drop this reference
-+ * reference when calling this. Use drm_dev_put() to drop this reference
-  * again.
-  *
-  * This function never fails. However, this function does not provide *any*
-  * guarantee whether the device is alive or running. It only provides a
-  * reference to the object and the memory associated with it.
-  */
--void drm_dev_ref(struct drm_device *dev)
-+void drm_dev_get(struct drm_device *dev)
- {
- 	if (dev)
- 		kref_get(&dev->ref);
- }
--EXPORT_SYMBOL(drm_dev_ref);
-+EXPORT_SYMBOL(drm_dev_get);
- 
- /**
-- * drm_dev_unref - Drop reference of a DRM device
-+ * drm_dev_put - Drop reference of a DRM device
-  * @dev: device to drop reference of or NULL
-  *
-  * This decreases the ref-count of @dev by one. The device is destroyed if the
-  * ref-count drops to zero.
-  */
--void drm_dev_unref(struct drm_device *dev)
-+void drm_dev_put(struct drm_device *dev)
- {
- 	if (dev)
- 		kref_put(&dev->ref, drm_dev_release);
- }
-+EXPORT_SYMBOL(drm_dev_put);
-+
-+/**
-+ * drm_dev_unref - Drop reference of a DRM device
-+ * @dev: device to drop reference of or NULL
-+ *
-+ * This is a compatibility alias for drm_dev_put() and should not be used by new
-+ * code.
-+ */
-+void drm_dev_unref(struct drm_device *dev)
-+{
-+	drm_dev_put(dev);
-+}
- EXPORT_SYMBOL(drm_dev_unref);
- 
- static int create_compat_control_link(struct drm_device *dev)
-@@ -839,7 +852,7 @@ EXPORT_SYMBOL(drm_dev_register);
-  *
-  * Unregister the DRM device from the system. This does the reverse of
-  * drm_dev_register() but does not deallocate the device. The caller must call
-- * drm_dev_unref() to drop their final reference.
-+ * drm_dev_put() to drop their final reference.
-  *
-  * A special form of unregistering for hotpluggable devices is drm_dev_unplug(),
-  * which can be called while there are still open users of @dev.
---- linux-4.14/drivers/gpu/drm/drm_edid.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_edid.c	2017-12-14 06:39:58.491903620 +0100
-@@ -1533,6 +1533,10 @@ static void connector_bad_edid(struct dr
-  * level, drivers must make all reasonable efforts to expose it as an I2C
-  * adapter and use drm_get_edid() instead of abusing this function.
-  *
-+ * The EDID may be overridden using debugfs override_edid or firmare EDID
-+ * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
-+ * order. Having either of them bypasses actual EDID reads.
-+ *
-  * Return: Pointer to valid EDID or NULL if we couldn't find any.
-  */
- struct edid *drm_do_get_edid(struct drm_connector *connector,
-@@ -1542,6 +1546,17 @@ struct edid *drm_do_get_edid(struct drm_
- {
- 	int i, j = 0, valid_extensions = 0;
- 	u8 *edid, *new;
-+	struct edid *override = NULL;
-+
-+	if (connector->override_edid)
-+		override = drm_edid_duplicate((const struct edid *)
-+					      connector->edid_blob_ptr->data);
-+
-+	if (!override)
-+		override = drm_load_edid_firmware(connector);
-+
-+	if (!IS_ERR_OR_NULL(override))
-+		return override;
- 
- 	if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
- 		return NULL;
---- linux-4.14/drivers/gpu/drm/drm_edid_load.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_edid_load.c	2017-12-14 06:39:58.491903620 +0100
-@@ -31,6 +31,22 @@ module_param_string(edid_firmware, edid_
- MODULE_PARM_DESC(edid_firmware, "Do not probe monitor, use specified EDID blob "
- 	"from built-in data or /lib/firmware instead. ");
- 
-+/* Use only for backward compatibility with drm_kms_helper.edid_firmware */
-+int __drm_set_edid_firmware_path(const char *path)
-+{
-+	scnprintf(edid_firmware, sizeof(edid_firmware), "%s", path);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(__drm_set_edid_firmware_path);
-+
-+/* Use only for backward compatibility with drm_kms_helper.edid_firmware */
-+int __drm_get_edid_firmware_path(char *buf, size_t bufsize)
-+{
-+	return scnprintf(buf, bufsize, "%s", edid_firmware);
-+}
-+EXPORT_SYMBOL(__drm_get_edid_firmware_path);
-+
- #define GENERIC_EDIDS 6
- static const char * const generic_edid_name[GENERIC_EDIDS] = {
- 	"edid/800x600.bin",
---- linux-4.14/drivers/gpu/drm/drm_encoder.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_encoder.c	2017-12-14 06:39:58.491903620 +0100
-@@ -220,7 +220,7 @@ int drm_mode_getencoder(struct drm_devic
- 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
- 		return -EINVAL;
- 
--	encoder = drm_encoder_find(dev, enc_resp->encoder_id);
-+	encoder = drm_encoder_find(dev, file_priv, enc_resp->encoder_id);
- 	if (!encoder)
- 		return -ENOENT;
- 
---- linux-4.14/drivers/gpu/drm/drm_fb_cma_helper.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_fb_cma_helper.c	2017-12-14 06:39:58.491903620 +0100
-@@ -38,7 +38,7 @@ struct drm_fbdev_cma {
-  * Provides helper functions for creating a cma (contiguous memory allocator)
-  * backed framebuffer.
-  *
-- * drm_fb_cma_create() is used in the &drm_mode_config_funcs.fb_create
-+ * drm_gem_fb_create() is used in the &drm_mode_config_funcs.fb_create
-  * callback function to create a cma backed framebuffer.
-  *
-  * An fbdev framebuffer backed by cma is also available by calling
-@@ -61,8 +61,8 @@ struct drm_fbdev_cma {
-  *     }
-  *
-  *     static struct drm_framebuffer_funcs driver_fb_funcs = {
-- *         .destroy       = drm_fb_cma_destroy,
-- *         .create_handle = drm_fb_cma_create_handle,
-+ *         .destroy       = drm_gem_fb_destroy,
-+ *         .create_handle = drm_gem_fb_create_handle,
-  *         .dirty         = driver_fb_dirty,
-  *     };
-  *
-@@ -80,57 +80,6 @@ static inline struct drm_fbdev_cma *to_f
- 	return container_of(helper, struct drm_fbdev_cma, fb_helper);
- }
- 
--void drm_fb_cma_destroy(struct drm_framebuffer *fb)
--{
--	drm_gem_fb_destroy(fb);
--}
--EXPORT_SYMBOL(drm_fb_cma_destroy);
--
--int drm_fb_cma_create_handle(struct drm_framebuffer *fb,
--	struct drm_file *file_priv, unsigned int *handle)
--{
--	return drm_gem_fb_create_handle(fb, file_priv, handle);
--}
--EXPORT_SYMBOL(drm_fb_cma_create_handle);
--
--/**
-- * drm_fb_cma_create_with_funcs() - helper function for the
-- *                                  &drm_mode_config_funcs.fb_create
-- *                                  callback
-- * @dev: DRM device
-- * @file_priv: drm file for the ioctl call
-- * @mode_cmd: metadata from the userspace fb creation request
-- * @funcs: vtable to be used for the new framebuffer object
-- *
-- * This can be used to set &drm_framebuffer_funcs for drivers that need the
-- * &drm_framebuffer_funcs.dirty callback. Use drm_fb_cma_create() if you don't
-- * need to change &drm_framebuffer_funcs.
-- */
--struct drm_framebuffer *drm_fb_cma_create_with_funcs(struct drm_device *dev,
--	struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd,
--	const struct drm_framebuffer_funcs *funcs)
--{
--	return drm_gem_fb_create_with_funcs(dev, file_priv, mode_cmd, funcs);
--}
--EXPORT_SYMBOL_GPL(drm_fb_cma_create_with_funcs);
--
--/**
-- * drm_fb_cma_create() - &drm_mode_config_funcs.fb_create callback function
-- * @dev: DRM device
-- * @file_priv: drm file for the ioctl call
-- * @mode_cmd: metadata from the userspace fb creation request
-- *
-- * If your hardware has special alignment or pitch requirements these should be
-- * checked before calling this function. Use drm_fb_cma_create_with_funcs() if
-- * you need to set &drm_framebuffer_funcs.dirty.
-- */
--struct drm_framebuffer *drm_fb_cma_create(struct drm_device *dev,
--	struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
--{
--	return drm_gem_fb_create(dev, file_priv, mode_cmd);
--}
--EXPORT_SYMBOL_GPL(drm_fb_cma_create);
--
- /**
-  * drm_fb_cma_get_gem_obj() - Get CMA GEM object for framebuffer
-  * @fb: The framebuffer
-@@ -181,26 +130,6 @@ dma_addr_t drm_fb_cma_get_gem_addr(struc
- }
- EXPORT_SYMBOL_GPL(drm_fb_cma_get_gem_addr);
- 
--/**
-- * drm_fb_cma_prepare_fb() - Prepare CMA framebuffer
-- * @plane: Which plane
-- * @state: Plane state attach fence to
-- *
-- * This should be set as the &struct drm_plane_helper_funcs.prepare_fb hook.
-- *
-- * This function checks if the plane FB has an dma-buf attached, extracts
-- * the exclusive fence and attaches it to plane state for the atomic helper
-- * to wait on.
-- *
-- * There is no need for cleanup_fb for CMA based framebuffer drivers.
-- */
--int drm_fb_cma_prepare_fb(struct drm_plane *plane,
--			  struct drm_plane_state *state)
--{
--	return drm_gem_fb_prepare_fb(plane, state);
--}
--EXPORT_SYMBOL_GPL(drm_fb_cma_prepare_fb);
--
- #ifdef CONFIG_DEBUG_FS
- static void drm_fb_cma_describe(struct drm_framebuffer *fb, struct seq_file *m)
- {
---- linux-4.14/drivers/gpu/drm/drm_fb_helper.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_fb_helper.c	2017-12-14 06:39:58.492903621 +0100
-@@ -910,6 +910,9 @@ void drm_fb_helper_fini(struct drm_fb_he
- 	if (!drm_fbdev_emulation || !fb_helper)
- 		return;
- 
-+	cancel_work_sync(&fb_helper->resume_work);
-+	cancel_work_sync(&fb_helper->dirty_work);
-+
- 	info = fb_helper->fbdev;
- 	if (info) {
- 		if (info->cmap.len)
-@@ -918,9 +921,6 @@ void drm_fb_helper_fini(struct drm_fb_he
- 	}
- 	fb_helper->fbdev = NULL;
- 
--	cancel_work_sync(&fb_helper->resume_work);
--	cancel_work_sync(&fb_helper->dirty_work);
--
- 	mutex_lock(&kernel_fb_helper_lock);
- 	if (!list_empty(&fb_helper->kernel_fb_list)) {
- 		list_del(&fb_helper->kernel_fb_list);
-@@ -2270,7 +2270,7 @@ static int drm_pick_crtcs(struct drm_fb_
- 	if (modes[n] == NULL)
- 		return best_score;
- 
--	crtcs = kzalloc(fb_helper->connector_count *
-+	crtcs = kcalloc(fb_helper->connector_count,
- 			sizeof(struct drm_fb_helper_crtc *), GFP_KERNEL);
- 	if (!crtcs)
- 		return best_score;
---- linux-4.14/drivers/gpu/drm/drm_framebuffer.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_framebuffer.c	2017-12-14 06:39:58.492903621 +0100
-@@ -381,7 +381,7 @@ int drm_mode_rmfb(struct drm_device *dev
- 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
- 		return -EINVAL;
- 
--	fb = drm_framebuffer_lookup(dev, *id);
-+	fb = drm_framebuffer_lookup(dev, file_priv, *id);
- 	if (!fb)
- 		return -ENOENT;
- 
-@@ -450,7 +450,7 @@ int drm_mode_getfb(struct drm_device *de
- 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
- 		return -EINVAL;
- 
--	fb = drm_framebuffer_lookup(dev, r->fb_id);
-+	fb = drm_framebuffer_lookup(dev, file_priv, r->fb_id);
- 	if (!fb)
- 		return -ENOENT;
- 
-@@ -515,7 +515,7 @@ int drm_mode_dirtyfb_ioctl(struct drm_de
- 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
- 		return -EINVAL;
- 
--	fb = drm_framebuffer_lookup(dev, r->fb_id);
-+	fb = drm_framebuffer_lookup(dev, file_priv, r->fb_id);
- 	if (!fb)
- 		return -ENOENT;
- 
-@@ -688,12 +688,13 @@ EXPORT_SYMBOL(drm_framebuffer_init);
-  * again, using drm_framebuffer_put().
-  */
- struct drm_framebuffer *drm_framebuffer_lookup(struct drm_device *dev,
-+					       struct drm_file *file_priv,
- 					       uint32_t id)
- {
- 	struct drm_mode_object *obj;
- 	struct drm_framebuffer *fb = NULL;
- 
--	obj = __drm_mode_object_find(dev, id, DRM_MODE_OBJECT_FB);
-+	obj = __drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_FB);
- 	if (obj)
- 		fb = obj_to_fb(obj);
- 	return fb;
---- linux-4.14/drivers/gpu/drm/drm_gem.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_gem.c	2017-12-14 06:39:58.492903621 +0100
-@@ -282,15 +282,6 @@ drm_gem_handle_delete(struct drm_file *f
- {
- 	struct drm_gem_object *obj;
- 
--	/* This is gross. The idr system doesn't let us try a delete and
--	 * return an error code.  It just spews if you fail at deleting.
--	 * So, we have to grab a lock around finding the object and then
--	 * doing the delete on it and dropping the refcount, or the user
--	 * could race us to double-decrement the refcount and cause a
--	 * use-after-free later.  Given the frequency of our handle lookups,
--	 * we may want to use ida for number allocation and a hash table
--	 * for the pointers, anyway.
--	 */
- 	spin_lock(&filp->table_lock);
- 
- 	/* Check if we currently have a reference on the object */
-@@ -334,6 +325,12 @@ int drm_gem_dumb_map_offset(struct drm_f
- 	if (!obj)
- 		return -ENOENT;
- 
-+	/* Don't allow imported objects to be mapped */
-+	if (obj->import_attach) {
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
- 	ret = drm_gem_create_mmap_offset(obj);
- 	if (ret)
- 		goto out;
-@@ -537,7 +534,7 @@ EXPORT_SYMBOL(drm_gem_create_mmap_offset
-  * Note that you are not allowed to change gfp-zones during runtime. That is,
-  * shmem_read_mapping_page_gfp() must be called with the same gfp_zone(gfp) as
-  * set during initialization. If you have special zone constraints, set them
-- * after drm_gem_init_object() via mapping_set_gfp_mask(). shmem-core takes care
-+ * after drm_gem_object_init() via mapping_set_gfp_mask(). shmem-core takes care
-  * to keep pages in the required zone during swap-in.
-  */
- struct page **drm_gem_get_pages(struct drm_gem_object *obj)
---- linux-4.14/drivers/gpu/drm/drm_gem_framebuffer_helper.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_gem_framebuffer_helper.c	2017-12-14 06:39:58.492903621 +0100
-@@ -27,19 +27,24 @@
-  * DOC: overview
-  *
-  * This library provides helpers for drivers that don't subclass
-- * &drm_framebuffer and and use &drm_gem_object for their backing storage.
-+ * &drm_framebuffer and use &drm_gem_object for their backing storage.
-  *
-  * Drivers without additional needs to validate framebuffers can simply use
-- * drm_gem_fb_create() and everything is wired up automatically. But all
-- * parts can be used individually.
-+ * drm_gem_fb_create() and everything is wired up automatically. Other drivers
-+ * can use all parts independently.
-  */
- 
- /**
-- * drm_gem_fb_get_obj() - Get GEM object for framebuffer
-- * @fb: The framebuffer
-- * @plane: Which plane
-+ * drm_gem_fb_get_obj() - Get GEM object backing the framebuffer
-+ * @fb: Framebuffer
-+ * @plane: Plane index
-  *
-- * Returns the GEM object for given framebuffer.
-+ * No additional reference is taken beyond the one that the &drm_frambuffer
-+ * already holds.
-+ *
-+ * Returns:
-+ * Pointer to &drm_gem_object for the given framebuffer and plane index or NULL
-+ * if it does not exist.
-  */
- struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb,
- 					  unsigned int plane)
-@@ -82,7 +87,7 @@ drm_gem_fb_alloc(struct drm_device *dev,
- 
- /**
-  * drm_gem_fb_destroy - Free GEM backed framebuffer
-- * @fb: DRM framebuffer
-+ * @fb: Framebuffer
-  *
-  * Frees a GEM backed framebuffer with its backing buffer(s) and the structure
-  * itself. Drivers can use this as their &drm_framebuffer_funcs->destroy
-@@ -102,12 +107,13 @@ EXPORT_SYMBOL(drm_gem_fb_destroy);
- 
- /**
-  * drm_gem_fb_create_handle - Create handle for GEM backed framebuffer
-- * @fb: DRM framebuffer
-- * @file: drm file
-- * @handle: handle created
-+ * @fb: Framebuffer
-+ * @file: DRM file to register the handle for
-+ * @handle: Pointer to return the created handle
-  *
-+ * This function creates a handle for the GEM object backing the framebuffer.
-  * Drivers can use this as their &drm_framebuffer_funcs->create_handle
-- * callback.
-+ * callback. The GETFB IOCTL calls into this callback.
-  *
-  * Returns:
-  * 0 on success or a negative error code on failure.
-@@ -120,18 +126,21 @@ int drm_gem_fb_create_handle(struct drm_
- EXPORT_SYMBOL(drm_gem_fb_create_handle);
- 
- /**
-- * drm_gem_fb_create_with_funcs() - helper function for the
-+ * drm_gem_fb_create_with_funcs() - Helper function for the
-  *                                  &drm_mode_config_funcs.fb_create
-  *                                  callback
-  * @dev: DRM device
-- * @file: drm file for the ioctl call
-- * @mode_cmd: metadata from the userspace fb creation request
-+ * @file: DRM file that holds the GEM handle(s) backing the framebuffer
-+ * @mode_cmd: Metadata from the userspace framebuffer creation request
-  * @funcs: vtable to be used for the new framebuffer object
-  *
-  * This can be used to set &drm_framebuffer_funcs for drivers that need the
-  * &drm_framebuffer_funcs.dirty callback. Use drm_gem_fb_create() if you don't
-  * need to change &drm_framebuffer_funcs.
-  * The function does buffer size validation.
-+ *
-+ * Returns:
-+ * Pointer to a &drm_framebuffer on success or an error pointer on failure.
-  */
- struct drm_framebuffer *
- drm_gem_fb_create_with_funcs(struct drm_device *dev, struct drm_file *file,
-@@ -154,7 +163,7 @@ drm_gem_fb_create_with_funcs(struct drm_
- 
- 		objs[i] = drm_gem_object_lookup(file, mode_cmd->handles[i]);
- 		if (!objs[i]) {
--			DRM_DEV_ERROR(dev->dev, "Failed to lookup GEM\n");
-+			DRM_DEBUG_KMS("Failed to lookup GEM object\n");
- 			ret = -ENOENT;
- 			goto err_gem_object_put;
- 		}
-@@ -192,15 +201,26 @@ static const struct drm_framebuffer_func
- };
- 
- /**
-- * drm_gem_fb_create() - &drm_mode_config_funcs.fb_create callback function
-+ * drm_gem_fb_create() - Helper function for the
-+ *                       &drm_mode_config_funcs.fb_create callback
-  * @dev: DRM device
-- * @file: drm file for the ioctl call
-- * @mode_cmd: metadata from the userspace fb creation request
-+ * @file: DRM file that holds the GEM handle(s) backing the framebuffer
-+ * @mode_cmd: Metadata from the userspace framebuffer creation request
-+ *
-+ * This function creates a new framebuffer object described by
-+ * &drm_mode_fb_cmd2. This description includes handles for the buffer(s)
-+ * backing the framebuffer.
-  *
-  * If your hardware has special alignment or pitch requirements these should be
-  * checked before calling this function. The function does buffer size
-  * validation. Use drm_gem_fb_create_with_funcs() if you need to set
-  * &drm_framebuffer_funcs.dirty.
-+ *
-+ * Drivers can use this as their &drm_mode_config_funcs.fb_create callback.
-+ * The ADDFB2 IOCTL calls into this callback.
-+ *
-+ * Returns:
-+ * Pointer to a &drm_framebuffer on success or an error pointer on failure.
-  */
- struct drm_framebuffer *
- drm_gem_fb_create(struct drm_device *dev, struct drm_file *file,
-@@ -212,15 +232,15 @@ drm_gem_fb_create(struct drm_device *dev
- EXPORT_SYMBOL_GPL(drm_gem_fb_create);
- 
- /**
-- * drm_gem_fb_prepare_fb() - Prepare gem framebuffer
-- * @plane: Which plane
-- * @state: Plane state attach fence to
-- *
-- * This can be used as the &drm_plane_helper_funcs.prepare_fb hook.
-- *
-- * This function checks if the plane FB has an dma-buf attached, extracts
-- * the exclusive fence and attaches it to plane state for the atomic helper
-- * to wait on.
-+ * drm_gem_fb_prepare_fb() - Prepare a GEM backed framebuffer
-+ * @plane: Plane
-+ * @state: Plane state the fence will be attached to
-+ *
-+ * This function prepares a GEM backed framebuffer for scanout by checking if
-+ * the plane framebuffer has a DMA-BUF attached. If it does, it extracts the
-+ * exclusive fence and attaches it to the plane state for the atomic helper to
-+ * wait on. This function can be used as the &drm_plane_helper_funcs.prepare_fb
-+ * callback.
-  *
-  * There is no need for &drm_plane_helper_funcs.cleanup_fb hook for simple
-  * gem based framebuffer drivers which have their buffers always pinned in
-@@ -232,7 +252,7 @@ int drm_gem_fb_prepare_fb(struct drm_pla
- 	struct dma_buf *dma_buf;
- 	struct dma_fence *fence;
- 
--	if ((plane->state->fb == state->fb) || !state->fb)
-+	if (plane->state->fb == state->fb || !state->fb)
- 		return 0;
- 
- 	dma_buf = drm_gem_fb_get_obj(state->fb, 0)->dma_buf;
-@@ -246,17 +266,19 @@ int drm_gem_fb_prepare_fb(struct drm_pla
- EXPORT_SYMBOL_GPL(drm_gem_fb_prepare_fb);
- 
- /**
-- * drm_gem_fbdev_fb_create - Create a drm_framebuffer for fbdev emulation
-+ * drm_gem_fbdev_fb_create - Create a GEM backed &drm_framebuffer for fbdev
-+ *                           emulation
-  * @dev: DRM device
-  * @sizes: fbdev size description
-- * @pitch_align: optional pitch alignment
-+ * @pitch_align: Optional pitch alignment
-  * @obj: GEM object backing the framebuffer
-  * @funcs: vtable to be used for the new framebuffer object
-  *
-- * This function creates a framebuffer for use with fbdev emulation.
-+ * This function creates a framebuffer from a &drm_fb_helper_surface_size
-+ * description for use in the &drm_fb_helper_funcs.fb_probe callback.
-  *
-  * Returns:
-- * Pointer to a drm_framebuffer on success or an error pointer on failure.
-+ * Pointer to a &drm_framebuffer on success or an error pointer on failure.
-  */
- struct drm_framebuffer *
- drm_gem_fbdev_fb_create(struct drm_device *dev,
---- linux-4.14/drivers/gpu/drm/drm_internal.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_internal.h	2017-12-14 06:39:58.492903621 +0100
-@@ -55,7 +55,6 @@ int drm_clients_info(struct seq_file *m,
- int drm_gem_name_info(struct seq_file *m, void *data);
- 
- /* drm_vblank.c */
--extern unsigned int drm_timestamp_monotonic;
- void drm_vblank_disable_and_save(struct drm_device *dev, unsigned int pipe);
- void drm_vblank_cleanup(struct drm_device *dev);
- 
---- linux-4.14/drivers/gpu/drm/drm_ioctl.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_ioctl.c	2017-12-14 06:39:58.492903621 +0100
-@@ -235,7 +235,7 @@ static int drm_getcap(struct drm_device
- 	/* Only some caps make sense with UMS/render-only drivers. */
- 	switch (req->capability) {
- 	case DRM_CAP_TIMESTAMP_MONOTONIC:
--		req->value = drm_timestamp_monotonic;
-+		req->value = 1;
- 		return 0;
- 	case DRM_CAP_PRIME:
- 		req->value |= dev->driver->prime_fd_to_handle ? DRM_PRIME_CAP_IMPORT : 0;
---- linux-4.14/drivers/gpu/drm/drm_kms_helper_common.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_kms_helper_common.c	2017-12-14 06:39:58.492903621 +0100
-@@ -26,6 +26,7 @@
-  */
- 
- #include <linux/module.h>
-+#include <drm/drmP.h>
- 
- #include "drm_crtc_helper_internal.h"
- 
-@@ -33,6 +34,33 @@ MODULE_AUTHOR("David Airlie, Jesse Barne
- MODULE_DESCRIPTION("DRM KMS helper");
- MODULE_LICENSE("GPL and additional rights");
- 
-+#if IS_ENABLED(CONFIG_DRM_LOAD_EDID_FIRMWARE)
-+
-+/* Backward compatibility for drm_kms_helper.edid_firmware */
-+static int edid_firmware_set(const char *val, const struct kernel_param *kp)
-+{
-+	DRM_NOTE("drm_kms_firmware.edid_firmware is deprecated, please use drm.edid_firmware intead.\n");
-+
-+	return __drm_set_edid_firmware_path(val);
-+}
-+
-+static int edid_firmware_get(char *buffer, const struct kernel_param *kp)
-+{
-+	return __drm_get_edid_firmware_path(buffer, PAGE_SIZE);
-+}
-+
-+static const struct kernel_param_ops edid_firmware_ops = {
-+	.set = edid_firmware_set,
-+	.get = edid_firmware_get,
-+};
-+
-+module_param_cb(edid_firmware, &edid_firmware_ops, NULL, 0644);
-+__MODULE_PARM_TYPE(edid_firmware, "charp");
-+MODULE_PARM_DESC(edid_firmware,
-+		 "DEPRECATED. Use drm.edid_firmware module parameter instead.");
-+
-+#endif
-+
- static int __init drm_kms_helper_init(void)
- {
- 	int ret;
---- linux-4.14/drivers/gpu/drm/drm_mode_object.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_mode_object.c	2017-12-14 06:39:58.492903621 +0100
-@@ -105,6 +105,7 @@ void drm_mode_object_unregister(struct d
- }
- 
- struct drm_mode_object *__drm_mode_object_find(struct drm_device *dev,
-+					       struct drm_file *file_priv,
- 					       uint32_t id, uint32_t type)
- {
- 	struct drm_mode_object *obj = NULL;
-@@ -127,7 +128,7 @@ struct drm_mode_object *__drm_mode_objec
- 
- /**
-  * drm_mode_object_find - look up a drm object with static lifetime
-- * @dev: drm device
-+ * @file_priv: drm file
-  * @id: id of the mode object
-  * @type: type of the mode object
-  *
-@@ -136,11 +137,12 @@ struct drm_mode_object *__drm_mode_objec
-  * by callind drm_mode_object_put().
-  */
- struct drm_mode_object *drm_mode_object_find(struct drm_device *dev,
-+		struct drm_file *file_priv,
- 		uint32_t id, uint32_t type)
- {
- 	struct drm_mode_object *obj = NULL;
- 
--	obj = __drm_mode_object_find(dev, id, type);
-+	obj = __drm_mode_object_find(dev, file_priv, id, type);
- 	return obj;
- }
- EXPORT_SYMBOL(drm_mode_object_find);
-@@ -247,8 +249,9 @@ int drm_object_property_set_value(struct
- }
- EXPORT_SYMBOL(drm_object_property_set_value);
- 
--int __drm_object_property_get_value(struct drm_mode_object *obj,
--				  struct drm_property *property, uint64_t *val)
-+static int __drm_object_property_get_value(struct drm_mode_object *obj,
-+					   struct drm_property *property,
-+					   uint64_t *val)
- {
- 	int i;
- 
-@@ -358,7 +361,7 @@ int drm_mode_obj_get_properties_ioctl(st
- 
- 	drm_modeset_lock_all(dev);
- 
--	obj = drm_mode_object_find(dev, arg->obj_id, arg->obj_type);
-+	obj = drm_mode_object_find(dev, file_priv, arg->obj_id, arg->obj_type);
- 	if (!obj) {
- 		ret = -ENOENT;
- 		goto out;
-@@ -480,7 +483,7 @@ int drm_mode_obj_set_property_ioctl(stru
- 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
- 		return -EINVAL;
- 
--	arg_obj = drm_mode_object_find(dev, arg->obj_id, arg->obj_type);
-+	arg_obj = drm_mode_object_find(dev, file_priv, arg->obj_id, arg->obj_type);
- 	if (!arg_obj)
- 		return -ENOENT;
- 
---- linux-4.14/drivers/gpu/drm/drm_modeset_lock.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_modeset_lock.c	2017-12-14 06:39:58.492903621 +0100
-@@ -39,23 +39,28 @@
-  *
-  * The basic usage pattern is to::
-  *
-- *     drm_modeset_acquire_init(&ctx)
-+ *     drm_modeset_acquire_init(ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE)
-  *     retry:
-  *     foreach (lock in random_ordered_set_of_locks) {
-- *         ret = drm_modeset_lock(lock, &ctx)
-+ *         ret = drm_modeset_lock(lock, ctx)
-  *         if (ret == -EDEADLK) {
-- *             drm_modeset_backoff(&ctx);
-- *             goto retry;
-+ *             ret = drm_modeset_backoff(ctx);
-+ *             if (!ret)
-+ *                 goto retry;
-  *         }
-+ *         if (ret)
-+ *             goto out;
-  *     }
-  *     ... do stuff ...
-- *     drm_modeset_drop_locks(&ctx);
-- *     drm_modeset_acquire_fini(&ctx);
-+ *     out:
-+ *     drm_modeset_drop_locks(ctx);
-+ *     drm_modeset_acquire_fini(ctx);
-  *
-  * If all that is needed is a single modeset lock, then the &struct
-  * drm_modeset_acquire_ctx is not needed and the locking can be simplified
-- * by passing a NULL instead of ctx in the drm_modeset_lock()
-- * call and, when done, by calling drm_modeset_unlock().
-+ * by passing a NULL instead of ctx in the drm_modeset_lock() call or
-+ * calling  drm_modeset_lock_single_interruptible(). To unlock afterwards
-+ * call drm_modeset_unlock().
-  *
-  * On top of these per-object locks using &ww_mutex there's also an overall
-  * &drm_mode_config.mutex, for protecting everything else. Mostly this means
-@@ -178,7 +183,11 @@ EXPORT_SYMBOL(drm_warn_on_modeset_not_al
- /**
-  * drm_modeset_acquire_init - initialize acquire context
-  * @ctx: the acquire context
-- * @flags: for future
-+ * @flags: 0 or %DRM_MODESET_ACQUIRE_INTERRUPTIBLE
-+ *
-+ * When passing %DRM_MODESET_ACQUIRE_INTERRUPTIBLE to @flags,
-+ * all calls to drm_modeset_lock() will perform an interruptible
-+ * wait.
-  */
- void drm_modeset_acquire_init(struct drm_modeset_acquire_ctx *ctx,
- 		uint32_t flags)
-@@ -186,6 +195,9 @@ void drm_modeset_acquire_init(struct drm
- 	memset(ctx, 0, sizeof(*ctx));
- 	ww_acquire_init(&ctx->ww_ctx, &crtc_ww_class);
- 	INIT_LIST_HEAD(&ctx->locked);
-+
-+	if (flags & DRM_MODESET_ACQUIRE_INTERRUPTIBLE)
-+		ctx->interruptible = true;
- }
- EXPORT_SYMBOL(drm_modeset_acquire_init);
- 
-@@ -261,8 +273,19 @@ static inline int modeset_lock(struct dr
- 	return ret;
- }
- 
--static int modeset_backoff(struct drm_modeset_acquire_ctx *ctx,
--		bool interruptible)
-+/**
-+ * drm_modeset_backoff - deadlock avoidance backoff
-+ * @ctx: the acquire context
-+ *
-+ * If deadlock is detected (ie. drm_modeset_lock() returns -EDEADLK),
-+ * you must call this function to drop all currently held locks and
-+ * block until the contended lock becomes available.
-+ *
-+ * This function returns 0 on success, or -ERESTARTSYS if this context
-+ * is initialized with %DRM_MODESET_ACQUIRE_INTERRUPTIBLE and the
-+ * wait has been interrupted.
-+ */
-+int drm_modeset_backoff(struct drm_modeset_acquire_ctx *ctx)
- {
- 	struct drm_modeset_lock *contended = ctx->contended;
- 
-@@ -273,36 +296,11 @@ static int modeset_backoff(struct drm_mo
- 
- 	drm_modeset_drop_locks(ctx);
- 
--	return modeset_lock(contended, ctx, interruptible, true);
--}
--
--/**
-- * drm_modeset_backoff - deadlock avoidance backoff
-- * @ctx: the acquire context
-- *
-- * If deadlock is detected (ie. drm_modeset_lock() returns -EDEADLK),
-- * you must call this function to drop all currently held locks and
-- * block until the contended lock becomes available.
-- */
--void drm_modeset_backoff(struct drm_modeset_acquire_ctx *ctx)
--{
--	modeset_backoff(ctx, false);
-+	return modeset_lock(contended, ctx, ctx->interruptible, true);
- }
- EXPORT_SYMBOL(drm_modeset_backoff);
- 
- /**
-- * drm_modeset_backoff_interruptible - deadlock avoidance backoff
-- * @ctx: the acquire context
-- *
-- * Interruptible version of drm_modeset_backoff()
-- */
--int drm_modeset_backoff_interruptible(struct drm_modeset_acquire_ctx *ctx)
--{
--	return modeset_backoff(ctx, true);
--}
--EXPORT_SYMBOL(drm_modeset_backoff_interruptible);
--
--/**
-  * drm_modeset_lock_init - initialize lock
-  * @lock: lock to init
-  */
-@@ -324,14 +322,18 @@ EXPORT_SYMBOL(drm_modeset_lock_init);
-  * deadlock scenario has been detected and it is an error to attempt
-  * to take any more locks without first calling drm_modeset_backoff().
-  *
-+ * If the @ctx is not NULL and initialized with
-+ * %DRM_MODESET_ACQUIRE_INTERRUPTIBLE, this function will fail with
-+ * -ERESTARTSYS when interrupted.
-+ *
-  * If @ctx is NULL then the function call behaves like a normal,
-- * non-nesting mutex_lock() call.
-+ * uninterruptible non-nesting mutex_lock() call.
-  */
- int drm_modeset_lock(struct drm_modeset_lock *lock,
- 		struct drm_modeset_acquire_ctx *ctx)
- {
- 	if (ctx)
--		return modeset_lock(lock, ctx, false, false);
-+		return modeset_lock(lock, ctx, ctx->interruptible, false);
- 
- 	ww_mutex_lock(&lock->mutex, NULL);
- 	return 0;
-@@ -339,21 +341,19 @@ int drm_modeset_lock(struct drm_modeset_
- EXPORT_SYMBOL(drm_modeset_lock);
- 
- /**
-- * drm_modeset_lock_interruptible - take modeset lock
-+ * drm_modeset_lock_single_interruptible - take a single modeset lock
-  * @lock: lock to take
-- * @ctx: acquire ctx
-  *
-- * Interruptible version of drm_modeset_lock()
-+ * This function behaves as drm_modeset_lock() with a NULL context,
-+ * but performs interruptible waits.
-+ *
-+ * This function returns 0 on success, or -ERESTARTSYS when interrupted.
-  */
--int drm_modeset_lock_interruptible(struct drm_modeset_lock *lock,
--		struct drm_modeset_acquire_ctx *ctx)
-+int drm_modeset_lock_single_interruptible(struct drm_modeset_lock *lock)
- {
--	if (ctx)
--		return modeset_lock(lock, ctx, true, false);
--
- 	return ww_mutex_lock_interruptible(&lock->mutex, NULL);
- }
--EXPORT_SYMBOL(drm_modeset_lock_interruptible);
-+EXPORT_SYMBOL(drm_modeset_lock_single_interruptible);
- 
- /**
-  * drm_modeset_unlock - drop modeset lock
---- linux-4.14/drivers/gpu/drm/drm_of.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_of.c	2017-12-14 06:39:58.492903621 +0100
-@@ -233,6 +233,8 @@ int drm_of_find_panel_or_bridge(const st
- 
- 	if (!panel && !bridge)
- 		return -EINVAL;
-+	if (panel)
-+		*panel = NULL;
- 
- 	remote = of_graph_get_remote_node(np, port, endpoint);
- 	if (!remote)
---- linux-4.14/drivers/gpu/drm/drm_pci.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_pci.c	2017-12-14 06:39:58.493903622 +0100
-@@ -274,7 +274,7 @@ err_agp:
- 	drm_pci_agp_destroy(dev);
- 	pci_disable_device(pdev);
- err_free:
--	drm_dev_unref(dev);
-+	drm_dev_put(dev);
- 	return ret;
- }
- EXPORT_SYMBOL(drm_get_pci_dev);
---- linux-4.14/drivers/gpu/drm/drm_plane.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_plane.c	2017-12-14 06:39:58.493903622 +0100
-@@ -513,7 +513,7 @@ int drm_mode_getplane(struct drm_device
- 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
- 		return -EINVAL;
- 
--	plane = drm_plane_find(dev, plane_resp->plane_id);
-+	plane = drm_plane_find(dev, file_priv, plane_resp->plane_id);
- 	if (!plane)
- 		return -ENOENT;
- 
-@@ -667,7 +667,7 @@ static int setplane_internal(struct drm_
- 	struct drm_modeset_acquire_ctx ctx;
- 	int ret;
- 
--	drm_modeset_acquire_init(&ctx, 0);
-+	drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
- retry:
- 	ret = drm_modeset_lock_all_ctx(plane->dev, &ctx);
- 	if (ret)
-@@ -678,8 +678,9 @@ retry:
- 
- fail:
- 	if (ret == -EDEADLK) {
--		drm_modeset_backoff(&ctx);
--		goto retry;
-+		ret = drm_modeset_backoff(&ctx);
-+		if (!ret)
-+			goto retry;
- 	}
- 	drm_modeset_drop_locks(&ctx);
- 	drm_modeset_acquire_fini(&ctx);
-@@ -702,7 +703,7 @@ int drm_mode_setplane(struct drm_device
- 	 * First, find the plane, crtc, and fb objects.  If not available,
- 	 * we don't bother to call the driver.
- 	 */
--	plane = drm_plane_find(dev, plane_req->plane_id);
-+	plane = drm_plane_find(dev, file_priv, plane_req->plane_id);
- 	if (!plane) {
- 		DRM_DEBUG_KMS("Unknown plane ID %d\n",
- 			      plane_req->plane_id);
-@@ -710,14 +711,14 @@ int drm_mode_setplane(struct drm_device
- 	}
- 
- 	if (plane_req->fb_id) {
--		fb = drm_framebuffer_lookup(dev, plane_req->fb_id);
-+		fb = drm_framebuffer_lookup(dev, file_priv, plane_req->fb_id);
- 		if (!fb) {
- 			DRM_DEBUG_KMS("Unknown framebuffer ID %d\n",
- 				      plane_req->fb_id);
- 			return -ENOENT;
- 		}
- 
--		crtc = drm_crtc_find(dev, plane_req->crtc_id);
-+		crtc = drm_crtc_find(dev, file_priv, plane_req->crtc_id);
- 		if (!crtc) {
- 			drm_framebuffer_put(fb);
- 			DRM_DEBUG_KMS("Unknown crtc ID %d\n",
-@@ -828,13 +829,13 @@ static int drm_mode_cursor_common(struct
- 	if (!req->flags || (~DRM_MODE_CURSOR_FLAGS & req->flags))
- 		return -EINVAL;
- 
--	crtc = drm_crtc_find(dev, req->crtc_id);
-+	crtc = drm_crtc_find(dev, file_priv, req->crtc_id);
- 	if (!crtc) {
- 		DRM_DEBUG_KMS("Unknown CRTC ID %d\n", req->crtc_id);
- 		return -ENOENT;
- 	}
- 
--	drm_modeset_acquire_init(&ctx, 0);
-+	drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
- retry:
- 	ret = drm_modeset_lock(&crtc->mutex, &ctx);
- 	if (ret)
-@@ -876,8 +877,9 @@ retry:
- 	}
- out:
- 	if (ret == -EDEADLK) {
--		drm_modeset_backoff(&ctx);
--		goto retry;
-+		ret = drm_modeset_backoff(&ctx);
-+		if (!ret)
-+			goto retry;
- 	}
- 
- 	drm_modeset_drop_locks(&ctx);
-@@ -942,7 +944,7 @@ int drm_mode_page_flip_ioctl(struct drm_
- 	if ((page_flip->flags & DRM_MODE_PAGE_FLIP_ASYNC) && !dev->mode_config.async_page_flip)
- 		return -EINVAL;
- 
--	crtc = drm_crtc_find(dev, page_flip->crtc_id);
-+	crtc = drm_crtc_find(dev, file_priv, page_flip->crtc_id);
- 	if (!crtc)
- 		return -ENOENT;
- 
-@@ -985,7 +987,7 @@ int drm_mode_page_flip_ioctl(struct drm_
- 		return -EINVAL;
- 	}
- 
--	drm_modeset_acquire_init(&ctx, 0);
-+	drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
- retry:
- 	ret = drm_modeset_lock(&crtc->mutex, &ctx);
- 	if (ret)
-@@ -1003,7 +1005,7 @@ retry:
- 		goto out;
- 	}
- 
--	fb = drm_framebuffer_lookup(dev, page_flip->fb_id);
-+	fb = drm_framebuffer_lookup(dev, file_priv, page_flip->fb_id);
- 	if (!fb) {
- 		ret = -ENOENT;
- 		goto out;
-@@ -1074,8 +1076,9 @@ out:
- 	crtc->primary->old_fb = NULL;
- 
- 	if (ret == -EDEADLK) {
--		drm_modeset_backoff(&ctx);
--		goto retry;
-+		ret = drm_modeset_backoff(&ctx);
-+		if (!ret)
-+			goto retry;
- 	}
- 
- 	drm_modeset_drop_locks(&ctx);
---- linux-4.14/drivers/gpu/drm/drm_plane_helper.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_plane_helper.c	2017-12-14 06:39:58.493903622 +0100
-@@ -354,7 +354,7 @@ int drm_primary_helper_update(struct drm
- 	/* Find current connectors for CRTC */
- 	num_connectors = get_connectors_for_crtc(crtc, NULL, 0);
- 	BUG_ON(num_connectors == 0);
--	connector_list = kzalloc(num_connectors * sizeof(*connector_list),
-+	connector_list = kcalloc(num_connectors, sizeof(*connector_list),
- 				 GFP_KERNEL);
- 	if (!connector_list)
- 		return -ENOMEM;
---- linux-4.14/drivers/gpu/drm/drm_prime.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_prime.c	2017-12-14 06:39:58.493903622 +0100
-@@ -318,7 +318,7 @@ struct dma_buf *drm_gem_dmabuf_export(st
- 	if (IS_ERR(dma_buf))
- 		return dma_buf;
- 
--	drm_dev_ref(dev);
-+	drm_dev_get(dev);
- 	drm_gem_object_get(exp_info->priv);
- 
- 	return dma_buf;
-@@ -342,7 +342,7 @@ void drm_gem_dmabuf_release(struct dma_b
- 	/* drop the reference on the export fd holds */
- 	drm_gem_object_put_unlocked(obj);
- 
--	drm_dev_unref(dev);
-+	drm_dev_put(dev);
- }
- EXPORT_SYMBOL(drm_gem_dmabuf_release);
- 
---- linux-4.14/drivers/gpu/drm/drm_probe_helper.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_probe_helper.c	2017-12-14 06:39:58.493903622 +0100
-@@ -99,7 +99,7 @@ drm_mode_validate_pipeline(struct drm_di
- 
- 	/* Step 2: Validate against encoders and crtcs */
- 	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
--		struct drm_encoder *encoder = drm_encoder_find(dev, ids[i]);
-+		struct drm_encoder *encoder = drm_encoder_find(dev, NULL, ids[i]);
- 		struct drm_crtc *crtc;
- 
- 		if (!encoder)
-@@ -353,8 +353,6 @@ EXPORT_SYMBOL(drm_helper_probe_detect);
-  *    drm_mode_probed_add(). New modes start their life with status as OK.
-  *    Modes are added from a single source using the following priority order.
-  *
-- *    - debugfs 'override_edid' (used for testing only)
-- *    - firmware EDID (drm_load_edid_firmware())
-  *    - &drm_connector_helper_funcs.get_modes vfunc
-  *    - if the connector status is connector_status_connected, standard
-  *      VESA DMT modes up to 1024x768 are automatically added
-@@ -483,22 +481,7 @@ retry:
- 		goto prune;
- 	}
- 
--	if (connector->override_edid) {
--		struct edid *edid = (struct edid *) connector->edid_blob_ptr->data;
--
--		count = drm_add_edid_modes(connector, edid);
--		drm_edid_to_eld(connector, edid);
--	} else {
--		struct edid *edid = drm_load_edid_firmware(connector);
--		if (!IS_ERR_OR_NULL(edid)) {
--			drm_mode_connector_update_edid_property(connector, edid);
--			count = drm_add_edid_modes(connector, edid);
--			drm_edid_to_eld(connector, edid);
--			kfree(edid);
--		}
--		if (count == 0)
--			count = (*connector_funcs->get_modes)(connector);
--	}
-+	count = (*connector_funcs->get_modes)(connector);
- 
- 	if (count == 0 && connector->status == connector_status_connected)
- 		count = drm_add_modes_noedid(connector, 1024, 768);
---- linux-4.14/drivers/gpu/drm/drm_property.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_property.c	2017-12-14 06:39:58.493903622 +0100
-@@ -450,7 +450,7 @@ int drm_mode_getproperty_ioctl(struct dr
- 	if (!drm_core_check_feature(dev, DRIVER_MODESET))
- 		return -EINVAL;
- 
--	property = drm_property_find(dev, out_resp->prop_id);
-+	property = drm_property_find(dev, file_priv, out_resp->prop_id);
- 	if (!property)
- 		return -ENOENT;
- 
-@@ -634,7 +634,7 @@ struct drm_property_blob *drm_property_l
- 	struct drm_mode_object *obj;
- 	struct drm_property_blob *blob = NULL;
- 
--	obj = __drm_mode_object_find(dev, id, DRM_MODE_OBJECT_BLOB);
-+	obj = __drm_mode_object_find(dev, NULL, id, DRM_MODE_OBJECT_BLOB);
- 	if (obj)
- 		blob = obj_to_blob(obj);
- 	return blob;
-@@ -897,7 +897,7 @@ bool drm_property_change_valid_get(struc
- 		if (value == 0)
- 			return true;
- 
--		*ref = __drm_mode_object_find(property->dev, value,
-+		*ref = __drm_mode_object_find(property->dev, NULL, value,
- 					      property->values[0]);
- 		return *ref != NULL;
- 	}
---- linux-4.14/drivers/gpu/drm/drm_scdc_helper.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_scdc_helper.c	2017-12-14 06:39:58.493903622 +0100
-@@ -134,7 +134,6 @@ EXPORT_SYMBOL(drm_scdc_write);
-  * Returns:
-  * True if the scrambling is enabled, false otherwise.
-  */
--
- bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter)
- {
- 	u8 status;
-@@ -142,7 +141,7 @@ bool drm_scdc_get_scrambling_status(stru
- 
- 	ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status);
- 	if (ret < 0) {
--		DRM_ERROR("Failed to read scrambling status, error %d\n", ret);
-+		DRM_ERROR("Failed to read scrambling status: %d\n", ret);
- 		return false;
- 	}
- 
-@@ -162,7 +161,6 @@ EXPORT_SYMBOL(drm_scdc_get_scrambling_st
-  * Returns:
-  * True if scrambling is set/reset successfully, false otherwise.
-  */
--
- bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable)
- {
- 	u8 config;
-@@ -170,7 +168,7 @@ bool drm_scdc_set_scrambling(struct i2c_
- 
- 	ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
- 	if (ret < 0) {
--		DRM_ERROR("Failed to read tmds config, err=%d\n", ret);
-+		DRM_ERROR("Failed to read TMDS config: %d\n", ret);
- 		return false;
- 	}
- 
-@@ -181,7 +179,7 @@ bool drm_scdc_set_scrambling(struct i2c_
- 
- 	ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
- 	if (ret < 0) {
--		DRM_ERROR("Failed to enable scrambling, error %d\n", ret);
-+		DRM_ERROR("Failed to enable scrambling: %d\n", ret);
- 		return false;
- 	}
- 
-@@ -225,7 +223,7 @@ bool drm_scdc_set_high_tmds_clock_ratio(
- 
- 	ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
- 	if (ret < 0) {
--		DRM_ERROR("Failed to read tmds config, err=%d\n", ret);
-+		DRM_ERROR("Failed to read TMDS config: %d\n", ret);
- 		return false;
- 	}
- 
-@@ -236,7 +234,7 @@ bool drm_scdc_set_high_tmds_clock_ratio(
- 
- 	ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
- 	if (ret < 0) {
--		DRM_ERROR("Failed to set TMDS clock ratio, error %d\n", ret);
-+		DRM_ERROR("Failed to set TMDS clock ratio: %d\n", ret);
- 		return false;
- 	}
- 
---- linux-4.14/drivers/gpu/drm/drm_syncobj.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_syncobj.c	2017-12-14 06:39:58.493903622 +0100
-@@ -262,8 +262,14 @@ void drm_syncobj_free(struct kref *kref)
- }
- EXPORT_SYMBOL(drm_syncobj_free);
- 
--static int drm_syncobj_create(struct drm_file *file_private,
--			      u32 *handle, uint32_t flags)
-+/**
-+ * drm_syncobj_create - create a new syncobj
-+ * @out_syncobj: returned syncobj
-+ * @flags: DRM_SYNCOBJ_* flags
-+ * @fence: if non-NULL, the syncobj will represent this fence
-+ */
-+int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,
-+		       struct dma_fence *fence)
- {
- 	int ret;
- 	struct drm_syncobj *syncobj;
-@@ -284,6 +290,25 @@ static int drm_syncobj_create(struct drm
- 		}
- 	}
- 
-+	if (fence)
-+		drm_syncobj_replace_fence(syncobj, fence);
-+
-+	*out_syncobj = syncobj;
-+	return 0;
-+}
-+EXPORT_SYMBOL(drm_syncobj_create);
-+
-+/**
-+ * drm_syncobj_get_handle - get a handle from a syncobj
-+ */
-+int drm_syncobj_get_handle(struct drm_file *file_private,
-+			   struct drm_syncobj *syncobj, u32 *handle)
-+{
-+	int ret;
-+
-+	/* take a reference to put in the idr */
-+	drm_syncobj_get(syncobj);
-+
- 	idr_preload(GFP_KERNEL);
- 	spin_lock(&file_private->syncobj_table_lock);
- 	ret = idr_alloc(&file_private->syncobj_idr, syncobj, 1, 0, GFP_NOWAIT);
-@@ -299,6 +324,22 @@ static int drm_syncobj_create(struct drm
- 	*handle = ret;
- 	return 0;
- }
-+EXPORT_SYMBOL(drm_syncobj_get_handle);
-+
-+static int drm_syncobj_create_as_handle(struct drm_file *file_private,
-+					u32 *handle, uint32_t flags)
-+{
-+	int ret;
-+	struct drm_syncobj *syncobj;
-+
-+	ret = drm_syncobj_create(&syncobj, flags, NULL);
-+	if (ret)
-+		return ret;
-+
-+	ret = drm_syncobj_get_handle(file_private, syncobj, handle);
-+	drm_syncobj_put(syncobj);
-+	return ret;
-+}
- 
- static int drm_syncobj_destroy(struct drm_file *file_private,
- 			       u32 handle)
-@@ -345,33 +386,38 @@ static int drm_syncobj_alloc_file(struct
- 	return 0;
- }
- 
--static int drm_syncobj_handle_to_fd(struct drm_file *file_private,
--				    u32 handle, int *p_fd)
-+int drm_syncobj_get_fd(struct drm_syncobj *syncobj, int *p_fd)
- {
--	struct drm_syncobj *syncobj = drm_syncobj_find(file_private, handle);
- 	int ret;
- 	int fd;
- 
--	if (!syncobj)
--		return -EINVAL;
--
- 	fd = get_unused_fd_flags(O_CLOEXEC);
--	if (fd < 0) {
--		drm_syncobj_put(syncobj);
-+	if (fd < 0)
- 		return fd;
--	}
- 
- 	if (!syncobj->file) {
- 		ret = drm_syncobj_alloc_file(syncobj);
--		if (ret)
--			goto out_put_fd;
-+		if (ret) {
-+			put_unused_fd(fd);
-+			return ret;
-+		}
- 	}
- 	fd_install(fd, syncobj->file);
--	drm_syncobj_put(syncobj);
- 	*p_fd = fd;
- 	return 0;
--out_put_fd:
--	put_unused_fd(fd);
-+}
-+EXPORT_SYMBOL(drm_syncobj_get_fd);
-+
-+static int drm_syncobj_handle_to_fd(struct drm_file *file_private,
-+				    u32 handle, int *p_fd)
-+{
-+	struct drm_syncobj *syncobj = drm_syncobj_find(file_private, handle);
-+	int ret;
-+
-+	if (!syncobj)
-+		return -EINVAL;
-+
-+	ret = drm_syncobj_get_fd(syncobj, p_fd);
- 	drm_syncobj_put(syncobj);
- 	return ret;
- }
-@@ -417,8 +463,8 @@ static int drm_syncobj_fd_to_handle(stru
- 	return 0;
- }
- 
--int drm_syncobj_import_sync_file_fence(struct drm_file *file_private,
--				       int fd, int handle)
-+static int drm_syncobj_import_sync_file_fence(struct drm_file *file_private,
-+					      int fd, int handle)
- {
- 	struct dma_fence *fence = sync_file_get_fence(fd);
- 	struct drm_syncobj *syncobj;
-@@ -438,8 +484,8 @@ int drm_syncobj_import_sync_file_fence(s
- 	return 0;
- }
- 
--int drm_syncobj_export_sync_file(struct drm_file *file_private,
--				 int handle, int *p_fd)
-+static int drm_syncobj_export_sync_file(struct drm_file *file_private,
-+					int handle, int *p_fd)
- {
- 	int ret;
- 	struct dma_fence *fence;
-@@ -522,8 +568,8 @@ drm_syncobj_create_ioctl(struct drm_devi
- 	if (args->flags & ~DRM_SYNCOBJ_CREATE_SIGNALED)
- 		return -EINVAL;
- 
--	return drm_syncobj_create(file_private,
--				  &args->handle, args->flags);
-+	return drm_syncobj_create_as_handle(file_private,
-+					    &args->handle, args->flags);
- }
- 
- int
-@@ -799,7 +845,8 @@ static int drm_syncobj_array_wait(struct
- }
- 
- static int drm_syncobj_array_find(struct drm_file *file_private,
--				  void *user_handles, uint32_t count_handles,
-+				  void __user *user_handles,
-+				  uint32_t count_handles,
- 				  struct drm_syncobj ***syncobjs_out)
- {
- 	uint32_t i, *handles;
---- linux-4.14/drivers/gpu/drm/drm_trace.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_trace.h	2017-12-14 06:39:58.493903622 +0100
-@@ -62,5 +62,5 @@ TRACE_EVENT(drm_vblank_event_delivered,
- 
- /* This part must be outside protection */
- #undef TRACE_INCLUDE_PATH
--#define TRACE_INCLUDE_PATH .
-+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm
- #include <trace/define_trace.h>
---- linux-4.14/drivers/gpu/drm/drm_vblank.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/drm_vblank.c	2017-12-14 06:39:58.494903623 +0100
-@@ -78,28 +78,20 @@
- 
- static bool
- drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,
--			  struct timeval *tvblank, bool in_vblank_irq);
-+			  ktime_t *tvblank, bool in_vblank_irq);
- 
- static unsigned int drm_timestamp_precision = 20;  /* Default to 20 usecs. */
- 
--/*
-- * Default to use monotonic timestamps for wait-for-vblank and page-flip
-- * complete events.
-- */
--unsigned int drm_timestamp_monotonic = 1;
--
- static int drm_vblank_offdelay = 5000;    /* Default to 5000 msecs. */
- 
- module_param_named(vblankoffdelay, drm_vblank_offdelay, int, 0600);
- module_param_named(timestamp_precision_usec, drm_timestamp_precision, int, 0600);
--module_param_named(timestamp_monotonic, drm_timestamp_monotonic, int, 0600);
- MODULE_PARM_DESC(vblankoffdelay, "Delay until vblank irq auto-disable [msecs] (0: never disable, <0: disable immediately)");
- MODULE_PARM_DESC(timestamp_precision_usec, "Max. error on timestamps [usecs]");
--MODULE_PARM_DESC(timestamp_monotonic, "Use monotonic timestamps");
- 
- static void store_vblank(struct drm_device *dev, unsigned int pipe,
- 			 u32 vblank_count_inc,
--			 struct timeval *t_vblank, u32 last)
-+			 ktime_t t_vblank, u32 last)
- {
- 	struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
- 
-@@ -108,7 +100,7 @@ static void store_vblank(struct drm_devi
- 	vblank->last = last;
- 
- 	write_seqlock(&vblank->seqlock);
--	vblank->time = *t_vblank;
-+	vblank->time = t_vblank;
- 	vblank->count += vblank_count_inc;
- 	write_sequnlock(&vblank->seqlock);
- }
-@@ -151,7 +143,7 @@ static void drm_reset_vblank_timestamp(s
- {
- 	u32 cur_vblank;
- 	bool rc;
--	struct timeval t_vblank;
-+	ktime_t t_vblank;
- 	int count = DRM_TIMESTAMP_MAXRETRIES;
- 
- 	spin_lock(&dev->vblank_time_lock);
-@@ -171,13 +163,13 @@ static void drm_reset_vblank_timestamp(s
- 	 * interrupt and assign 0 for now, to mark the vblanktimestamp as invalid.
- 	 */
- 	if (!rc)
--		t_vblank = (struct timeval) {0, 0};
-+		t_vblank = 0;
- 
- 	/*
- 	 * +1 to make sure user will never see the same
- 	 * vblank counter value before and after a modeset
- 	 */
--	store_vblank(dev, pipe, 1, &t_vblank, cur_vblank);
-+	store_vblank(dev, pipe, 1, t_vblank, cur_vblank);
- 
- 	spin_unlock(&dev->vblank_time_lock);
- }
-@@ -200,7 +192,7 @@ static void drm_update_vblank_count(stru
- 	struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
- 	u32 cur_vblank, diff;
- 	bool rc;
--	struct timeval t_vblank;
-+	ktime_t t_vblank;
- 	int count = DRM_TIMESTAMP_MAXRETRIES;
- 	int framedur_ns = vblank->framedur_ns;
- 
-@@ -225,11 +217,7 @@ static void drm_update_vblank_count(stru
- 		/* trust the hw counter when it's around */
- 		diff = (cur_vblank - vblank->last) & dev->max_vblank_count;
- 	} else if (rc && framedur_ns) {
--		const struct timeval *t_old;
--		u64 diff_ns;
--
--		t_old = &vblank->time;
--		diff_ns = timeval_to_ns(&t_vblank) - timeval_to_ns(t_old);
-+		u64 diff_ns = ktime_to_ns(ktime_sub(t_vblank, vblank->time));
- 
- 		/*
- 		 * Figure out how many vblanks we've missed based
-@@ -278,9 +266,9 @@ static void drm_update_vblank_count(stru
- 	 * for now, to mark the vblanktimestamp as invalid.
- 	 */
- 	if (!rc && !in_vblank_irq)
--		t_vblank = (struct timeval) {0, 0};
-+		t_vblank = 0;
- 
--	store_vblank(dev, pipe, diff, &t_vblank, cur_vblank);
-+	store_vblank(dev, pipe, diff, t_vblank, cur_vblank);
- }
- 
- static u32 drm_vblank_count(struct drm_device *dev, unsigned int pipe)
-@@ -556,7 +544,7 @@ EXPORT_SYMBOL(drm_calc_timestamping_cons
-  * @pipe: index of CRTC whose vblank timestamp to retrieve
-  * @max_error: Desired maximum allowable error in timestamps (nanosecs)
-  *             On return contains true maximum error of timestamp
-- * @vblank_time: Pointer to struct timeval which should receive the timestamp
-+ * @vblank_time: Pointer to time which should receive the timestamp
-  * @in_vblank_irq:
-  *     True when called from drm_crtc_handle_vblank().  Some drivers
-  *     need to apply some workarounds for gpu-specific vblank irq quirks
-@@ -584,10 +572,10 @@ EXPORT_SYMBOL(drm_calc_timestamping_cons
- bool drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
- 					   unsigned int pipe,
- 					   int *max_error,
--					   struct timeval *vblank_time,
-+					   ktime_t *vblank_time,
- 					   bool in_vblank_irq)
- {
--	struct timeval tv_etime;
-+	struct timespec64 ts_etime, ts_vblank_time;
- 	ktime_t stime, etime;
- 	bool vbl_status;
- 	struct drm_crtc *crtc;
-@@ -676,41 +664,31 @@ bool drm_calc_vbltimestamp_from_scanoutp
- 	delta_ns = div_s64(1000000LL * (vpos * mode->crtc_htotal + hpos),
- 			   mode->crtc_clock);
- 
--	if (!drm_timestamp_monotonic)
--		etime = ktime_mono_to_real(etime);
--
- 	/* save this only for debugging purposes */
--	tv_etime = ktime_to_timeval(etime);
-+	ts_etime = ktime_to_timespec64(etime);
-+	ts_vblank_time = ktime_to_timespec64(*vblank_time);
- 	/* Subtract time delta from raw timestamp to get final
- 	 * vblank_time timestamp for end of vblank.
- 	 */
- 	etime = ktime_sub_ns(etime, delta_ns);
--	*vblank_time = ktime_to_timeval(etime);
-+	*vblank_time = etime;
- 
--	DRM_DEBUG_VBL("crtc %u : v p(%d,%d)@ %ld.%ld -> %ld.%ld [e %d us, %d rep]\n",
-+	DRM_DEBUG_VBL("crtc %u : v p(%d,%d)@ %lld.%06ld -> %lld.%06ld [e %d us, %d rep]\n",
- 		      pipe, hpos, vpos,
--		      (long)tv_etime.tv_sec, (long)tv_etime.tv_usec,
--		      (long)vblank_time->tv_sec, (long)vblank_time->tv_usec,
--		      duration_ns/1000, i);
-+		      (u64)ts_etime.tv_sec, ts_etime.tv_nsec / 1000,
-+		      (u64)ts_vblank_time.tv_sec, ts_vblank_time.tv_nsec / 1000,
-+		      duration_ns / 1000, i);
- 
- 	return true;
- }
- EXPORT_SYMBOL(drm_calc_vbltimestamp_from_scanoutpos);
- 
--static struct timeval get_drm_timestamp(void)
--{
--	ktime_t now;
--
--	now = drm_timestamp_monotonic ? ktime_get() : ktime_get_real();
--	return ktime_to_timeval(now);
--}
--
- /**
-  * drm_get_last_vbltimestamp - retrieve raw timestamp for the most recent
-  *                             vblank interval
-  * @dev: DRM device
-  * @pipe: index of CRTC whose vblank timestamp to retrieve
-- * @tvblank: Pointer to target struct timeval which should receive the timestamp
-+ * @tvblank: Pointer to target time which should receive the timestamp
-  * @in_vblank_irq:
-  *     True when called from drm_crtc_handle_vblank().  Some drivers
-  *     need to apply some workarounds for gpu-specific vblank irq quirks
-@@ -728,7 +706,7 @@ static struct timeval get_drm_timestamp(
-  */
- static bool
- drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,
--			  struct timeval *tvblank, bool in_vblank_irq)
-+			  ktime_t *tvblank, bool in_vblank_irq)
- {
- 	bool ret = false;
- 
-@@ -744,7 +722,7 @@ drm_get_last_vbltimestamp(struct drm_dev
- 	 * Return current monotonic/gettimeofday timestamp as best estimate.
- 	 */
- 	if (!ret)
--		*tvblank = get_drm_timestamp();
-+		*tvblank = ktime_get();
- 
- 	return ret;
- }
-@@ -769,14 +747,14 @@ u32 drm_crtc_vblank_count(struct drm_crt
- EXPORT_SYMBOL(drm_crtc_vblank_count);
- 
- static u32 drm_vblank_count_and_time(struct drm_device *dev, unsigned int pipe,
--				     struct timeval *vblanktime)
-+				     ktime_t *vblanktime)
- {
- 	struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
- 	u32 vblank_count;
- 	unsigned int seq;
- 
- 	if (WARN_ON(pipe >= dev->num_crtcs)) {
--		*vblanktime = (struct timeval) { 0 };
-+		*vblanktime = 0;
- 		return 0;
- 	}
- 
-@@ -793,7 +771,7 @@ static u32 drm_vblank_count_and_time(str
-  * drm_crtc_vblank_count_and_time - retrieve "cooked" vblank counter value
-  *     and the system timestamp corresponding to that vblank counter value
-  * @crtc: which counter to retrieve
-- * @vblanktime: Pointer to struct timeval to receive the vblank timestamp.
-+ * @vblanktime: Pointer to time to receive the vblank timestamp.
-  *
-  * Fetches the "cooked" vblank count value that represents the number of
-  * vblank events since the system was booted, including lost events due to
-@@ -801,7 +779,7 @@ static u32 drm_vblank_count_and_time(str
-  * of the vblank interval that corresponds to the current vblank counter value.
-  */
- u32 drm_crtc_vblank_count_and_time(struct drm_crtc *crtc,
--				   struct timeval *vblanktime)
-+				   ktime_t *vblanktime)
- {
- 	return drm_vblank_count_and_time(crtc->dev, drm_crtc_index(crtc),
- 					 vblanktime);
-@@ -810,11 +788,18 @@ EXPORT_SYMBOL(drm_crtc_vblank_count_and_
- 
- static void send_vblank_event(struct drm_device *dev,
- 		struct drm_pending_vblank_event *e,
--		unsigned long seq, struct timeval *now)
-+		unsigned long seq, ktime_t now)
- {
-+	struct timespec64 tv = ktime_to_timespec64(now);
-+
- 	e->event.sequence = seq;
--	e->event.tv_sec = now->tv_sec;
--	e->event.tv_usec = now->tv_usec;
-+	/*
-+	 * e->event is a user space structure, with hardcoded unsigned
-+	 * 32-bit seconds/microseconds. This is safe as we always use
-+	 * monotonic timestamps since linux-4.15
-+	 */
-+	e->event.tv_sec = tv.tv_sec;
-+	e->event.tv_usec = tv.tv_nsec / 1000;
- 
- 	trace_drm_vblank_event_delivered(e->base.file_priv, e->pipe,
- 					 e->event.sequence);
-@@ -891,18 +876,18 @@ void drm_crtc_send_vblank_event(struct d
- {
- 	struct drm_device *dev = crtc->dev;
- 	unsigned int seq, pipe = drm_crtc_index(crtc);
--	struct timeval now;
-+	ktime_t now;
- 
- 	if (dev->num_crtcs > 0) {
- 		seq = drm_vblank_count_and_time(dev, pipe, &now);
- 	} else {
- 		seq = 0;
- 
--		now = get_drm_timestamp();
-+		now = ktime_get();
- 	}
- 	e->pipe = pipe;
- 	e->event.crtc_id = crtc->base.id;
--	send_vblank_event(dev, e, seq, &now);
-+	send_vblank_event(dev, e, seq, now);
- }
- EXPORT_SYMBOL(drm_crtc_send_vblank_event);
- 
-@@ -1100,7 +1085,8 @@ void drm_crtc_vblank_off(struct drm_crtc
- 	unsigned int pipe = drm_crtc_index(crtc);
- 	struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
- 	struct drm_pending_vblank_event *e, *t;
--	struct timeval now;
-+
-+	ktime_t now;
- 	unsigned long irqflags;
- 	unsigned int seq;
- 
-@@ -1141,7 +1127,7 @@ void drm_crtc_vblank_off(struct drm_crtc
- 			  e->event.sequence, seq);
- 		list_del(&e->base.link);
- 		drm_vblank_put(dev, pipe);
--		send_vblank_event(dev, e, seq, &now);
-+		send_vblank_event(dev, e, seq, now);
- 	}
- 	spin_unlock_irqrestore(&dev->event_lock, irqflags);
- 
-@@ -1321,7 +1307,7 @@ static int drm_queue_vblank_event(struct
- {
- 	struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
- 	struct drm_pending_vblank_event *e;
--	struct timeval now;
-+	ktime_t now;
- 	unsigned long flags;
- 	unsigned int seq;
- 	int ret;
-@@ -1367,7 +1353,7 @@ static int drm_queue_vblank_event(struct
- 	e->event.sequence = vblwait->request.sequence;
- 	if (vblank_passed(seq, vblwait->request.sequence)) {
- 		drm_vblank_put(dev, pipe);
--		send_vblank_event(dev, e, seq, &now);
-+		send_vblank_event(dev, e, seq, now);
- 		vblwait->reply.sequence = seq;
- 	} else {
- 		/* drm_handle_vblank_events will call drm_vblank_put */
-@@ -1398,6 +1384,23 @@ static bool drm_wait_vblank_is_query(uni
- 					  _DRM_VBLANK_NEXTONMISS));
- }
- 
-+static void drm_wait_vblank_reply(struct drm_device *dev, unsigned int pipe,
-+				  struct drm_wait_vblank_reply *reply)
-+{
-+	ktime_t now;
-+	struct timespec64 ts;
-+
-+	/*
-+	 * drm_wait_vblank_reply is a UAPI structure that uses 'long'
-+	 * to store the seconds. This is safe as we always use monotonic
-+	 * timestamps since linux-4.15.
-+	 */
-+	reply->sequence = drm_vblank_count_and_time(dev, pipe, &now);
-+	ts = ktime_to_timespec64(now);
-+	reply->tval_sec = (u32)ts.tv_sec;
-+	reply->tval_usec = ts.tv_nsec / 1000;
-+}
-+
- int drm_wait_vblank_ioctl(struct drm_device *dev, void *data,
- 			  struct drm_file *file_priv)
- {
-@@ -1439,12 +1442,7 @@ int drm_wait_vblank_ioctl(struct drm_dev
- 	if (dev->vblank_disable_immediate &&
- 	    drm_wait_vblank_is_query(vblwait) &&
- 	    READ_ONCE(vblank->enabled)) {
--		struct timeval now;
--
--		vblwait->reply.sequence =
--			drm_vblank_count_and_time(dev, pipe, &now);
--		vblwait->reply.tval_sec = now.tv_sec;
--		vblwait->reply.tval_usec = now.tv_usec;
-+		drm_wait_vblank_reply(dev, pipe, &vblwait->reply);
- 		return 0;
- 	}
- 
-@@ -1487,11 +1485,7 @@ int drm_wait_vblank_ioctl(struct drm_dev
- 	}
- 
- 	if (ret != -EINTR) {
--		struct timeval now;
--
--		vblwait->reply.sequence = drm_vblank_count_and_time(dev, pipe, &now);
--		vblwait->reply.tval_sec = now.tv_sec;
--		vblwait->reply.tval_usec = now.tv_usec;
-+		drm_wait_vblank_reply(dev, pipe, &vblwait->reply);
- 
- 		DRM_DEBUG("crtc %d returning %u to client\n",
- 			  pipe, vblwait->reply.sequence);
-@@ -1507,7 +1501,7 @@ done:
- static void drm_handle_vblank_events(struct drm_device *dev, unsigned int pipe)
- {
- 	struct drm_pending_vblank_event *e, *t;
--	struct timeval now;
-+	ktime_t now;
- 	unsigned int seq;
- 
- 	assert_spin_locked(&dev->event_lock);
-@@ -1525,7 +1519,7 @@ static void drm_handle_vblank_events(str
- 
- 		list_del(&e->base.link);
- 		drm_vblank_put(dev, pipe);
--		send_vblank_event(dev, e, seq, &now);
-+		send_vblank_event(dev, e, seq, now);
- 	}
- 
- 	trace_drm_vblank_event(pipe, seq);
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_buffer.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_buffer.c	2017-12-14 06:39:58.494903623 +0100
-@@ -250,6 +250,42 @@ void etnaviv_buffer_end(struct etnaviv_g
- 	}
- }
- 
-+/* Append a 'sync point' to the ring buffer. */
-+void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event)
-+{
-+	struct etnaviv_cmdbuf *buffer = gpu->buffer;
-+	unsigned int waitlink_offset = buffer->user_size - 16;
-+	u32 dwords, target;
-+
-+	/*
-+	 * We need at most 3 dwords in the return target:
-+	 * 1 event + 1 end + 1 wait + 1 link.
-+	 */
-+	dwords = 4;
-+	target = etnaviv_buffer_reserve(gpu, buffer, dwords);
-+
-+	/* Signal sync point event */
-+	CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) |
-+		       VIVS_GL_EVENT_FROM_PE);
-+
-+	/* Stop the FE to 'pause' the GPU */
-+	CMD_END(buffer);
-+
-+	/* Append waitlink */
-+	CMD_WAIT(buffer);
-+	CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer) +
-+			    buffer->user_size - 4);
-+
-+	/*
-+	 * Kick off the 'sync point' command by replacing the previous
-+	 * WAIT with a link to the address in the ring buffer.
-+	 */
-+	etnaviv_buffer_replace_wait(buffer, waitlink_offset,
-+				    VIV_FE_LINK_HEADER_OP_LINK |
-+				    VIV_FE_LINK_HEADER_PREFETCH(dwords),
-+				    target);
-+}
-+
- /* Append a command buffer to the ring buffer. */
- void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event,
- 	struct etnaviv_cmdbuf *cmdbuf)
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.c	2017-12-14 06:39:58.494903623 +0100
-@@ -19,6 +19,7 @@
- #include "etnaviv_cmdbuf.h"
- #include "etnaviv_gpu.h"
- #include "etnaviv_mmu.h"
-+#include "etnaviv_perfmon.h"
- 
- #define SUBALLOC_SIZE		SZ_256K
- #define SUBALLOC_GRANULE	SZ_4K
-@@ -87,9 +88,10 @@ void etnaviv_cmdbuf_suballoc_destroy(str
- 
- struct etnaviv_cmdbuf *
- etnaviv_cmdbuf_new(struct etnaviv_cmdbuf_suballoc *suballoc, u32 size,
--		   size_t nr_bos)
-+		   size_t nr_bos, size_t nr_pmrs)
- {
- 	struct etnaviv_cmdbuf *cmdbuf;
-+	struct etnaviv_perfmon_request *pmrs;
- 	size_t sz = size_vstruct(nr_bos, sizeof(cmdbuf->bo_map[0]),
- 				 sizeof(*cmdbuf));
- 	int granule_offs, order, ret;
-@@ -98,6 +100,12 @@ etnaviv_cmdbuf_new(struct etnaviv_cmdbuf
- 	if (!cmdbuf)
- 		return NULL;
- 
-+	sz = sizeof(*pmrs) * nr_pmrs;
-+	pmrs = kzalloc(sz, GFP_KERNEL);
-+	if (!pmrs)
-+		goto out_free_cmdbuf;
-+
-+	cmdbuf->pmrs = pmrs;
- 	cmdbuf->suballoc = suballoc;
- 	cmdbuf->size = size;
- 
-@@ -124,6 +132,10 @@ retry:
- 	cmdbuf->vaddr = suballoc->vaddr + cmdbuf->suballoc_offset;
- 
- 	return cmdbuf;
-+
-+out_free_cmdbuf:
-+	kfree(cmdbuf);
-+	return NULL;
- }
- 
- void etnaviv_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf)
-@@ -139,6 +151,7 @@ void etnaviv_cmdbuf_free(struct etnaviv_
- 	suballoc->free_space = 1;
- 	mutex_unlock(&suballoc->lock);
- 	wake_up_all(&suballoc->free_event);
-+	kfree(cmdbuf->pmrs);
- 	kfree(cmdbuf);
- }
- 
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.h	2017-12-14 06:39:58.494903623 +0100
-@@ -21,6 +21,7 @@
- 
- struct etnaviv_gpu;
- struct etnaviv_cmdbuf_suballoc;
-+struct etnaviv_perfmon_request;
- 
- struct etnaviv_cmdbuf {
- 	/* suballocator this cmdbuf is allocated from */
-@@ -38,6 +39,9 @@ struct etnaviv_cmdbuf {
- 	u32 exec_state;
- 	/* per GPU in-flight list */
- 	struct list_head node;
-+	/* perfmon requests */
-+	unsigned int nr_pmrs;
-+	struct etnaviv_perfmon_request *pmrs;
- 	/* BOs attached to this command buffer */
- 	unsigned int nr_bos;
- 	struct etnaviv_vram_mapping *bo_map[0];
-@@ -49,7 +53,7 @@ void etnaviv_cmdbuf_suballoc_destroy(str
- 
- struct etnaviv_cmdbuf *
- etnaviv_cmdbuf_new(struct etnaviv_cmdbuf_suballoc *suballoc, u32 size,
--		   size_t nr_bos);
-+		   size_t nr_bos, size_t nr_pmrs);
- void etnaviv_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf);
- 
- u32 etnaviv_cmdbuf_get_va(struct etnaviv_cmdbuf *buf);
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_drv.c	2017-12-14 06:39:58.494903623 +0100
-@@ -23,6 +23,7 @@
- #include "etnaviv_gpu.h"
- #include "etnaviv_gem.h"
- #include "etnaviv_mmu.h"
-+#include "etnaviv_perfmon.h"
- 
- #ifdef CONFIG_DRM_ETNAVIV_REGISTER_LOGGING
- static bool reglog;
-@@ -451,6 +452,40 @@ static int etnaviv_ioctl_gem_wait(struct
- 	return ret;
- }
- 
-+static int etnaviv_ioctl_pm_query_dom(struct drm_device *dev, void *data,
-+	struct drm_file *file)
-+{
-+	struct etnaviv_drm_private *priv = dev->dev_private;
-+	struct drm_etnaviv_pm_domain *args = data;
-+	struct etnaviv_gpu *gpu;
-+
-+	if (args->pipe >= ETNA_MAX_PIPES)
-+		return -EINVAL;
-+
-+	gpu = priv->gpu[args->pipe];
-+	if (!gpu)
-+		return -ENXIO;
-+
-+	return etnaviv_pm_query_dom(gpu, args);
-+}
-+
-+static int etnaviv_ioctl_pm_query_sig(struct drm_device *dev, void *data,
-+	struct drm_file *file)
-+{
-+	struct etnaviv_drm_private *priv = dev->dev_private;
-+	struct drm_etnaviv_pm_signal *args = data;
-+	struct etnaviv_gpu *gpu;
-+
-+	if (args->pipe >= ETNA_MAX_PIPES)
-+		return -EINVAL;
-+
-+	gpu = priv->gpu[args->pipe];
-+	if (!gpu)
-+		return -ENXIO;
-+
-+	return etnaviv_pm_query_sig(gpu, args);
-+}
-+
- static const struct drm_ioctl_desc etnaviv_ioctls[] = {
- #define ETNA_IOCTL(n, func, flags) \
- 	DRM_IOCTL_DEF_DRV(ETNAVIV_##n, etnaviv_ioctl_##func, flags)
-@@ -463,6 +498,8 @@ static const struct drm_ioctl_desc etnav
- 	ETNA_IOCTL(WAIT_FENCE,   wait_fence,   DRM_AUTH|DRM_RENDER_ALLOW),
- 	ETNA_IOCTL(GEM_USERPTR,  gem_userptr,  DRM_AUTH|DRM_RENDER_ALLOW),
- 	ETNA_IOCTL(GEM_WAIT,     gem_wait,     DRM_AUTH|DRM_RENDER_ALLOW),
-+	ETNA_IOCTL(PM_QUERY_DOM, pm_query_dom, DRM_AUTH|DRM_RENDER_ALLOW),
-+	ETNA_IOCTL(PM_QUERY_SIG, pm_query_sig, DRM_AUTH|DRM_RENDER_ALLOW),
- };
- 
- static const struct vm_operations_struct vm_ops = {
-@@ -513,7 +550,7 @@ static struct drm_driver etnaviv_drm_dri
- 	.desc               = "etnaviv DRM",
- 	.date               = "20151214",
- 	.major              = 1,
--	.minor              = 1,
-+	.minor              = 2,
- };
- 
- /*
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_drv.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_drv.h	2017-12-14 06:39:58.494903623 +0100
-@@ -26,7 +26,6 @@
- #include <linux/pm_runtime.h>
- #include <linux/slab.h>
- #include <linux/list.h>
--#include <linux/iommu.h>
- #include <linux/types.h>
- #include <linux/sizes.h>
- 
-@@ -92,15 +91,12 @@ int etnaviv_gem_cpu_fini(struct drm_gem_
- void etnaviv_gem_free_object(struct drm_gem_object *obj);
- int etnaviv_gem_new_handle(struct drm_device *dev, struct drm_file *file,
- 		u32 size, u32 flags, u32 *handle);
--struct drm_gem_object *etnaviv_gem_new_locked(struct drm_device *dev,
--		u32 size, u32 flags);
--struct drm_gem_object *etnaviv_gem_new(struct drm_device *dev,
--		u32 size, u32 flags);
- int etnaviv_gem_new_userptr(struct drm_device *dev, struct drm_file *file,
- 	uintptr_t ptr, u32 size, u32 flags, u32 *handle);
- u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu);
- u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr);
- void etnaviv_buffer_end(struct etnaviv_gpu *gpu);
-+void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event);
- void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event,
- 	struct etnaviv_cmdbuf *cmdbuf);
- void etnaviv_validate_init(void);
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_gem.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_gem.c	2017-12-14 06:39:58.494903623 +0100
-@@ -704,25 +704,6 @@ int etnaviv_gem_new_handle(struct drm_de
- 	return ret;
- }
- 
--struct drm_gem_object *etnaviv_gem_new(struct drm_device *dev,
--		u32 size, u32 flags)
--{
--	struct drm_gem_object *obj;
--	int ret;
--
--	obj = __etnaviv_gem_new(dev, size, flags);
--	if (IS_ERR(obj))
--		return obj;
--
--	ret = etnaviv_gem_obj_add(dev, obj);
--	if (ret < 0) {
--		drm_gem_object_put_unlocked(obj);
--		return ERR_PTR(ret);
--	}
--
--	return obj;
--}
--
- int etnaviv_gem_new_private(struct drm_device *dev, size_t size, u32 flags,
- 	struct reservation_object *robj, const struct etnaviv_gem_ops *ops,
- 	struct etnaviv_gem_object **res)
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c	2017-12-14 06:39:58.494903623 +0100
-@@ -21,6 +21,7 @@
- #include "etnaviv_drv.h"
- #include "etnaviv_gpu.h"
- #include "etnaviv_gem.h"
-+#include "etnaviv_perfmon.h"
- 
- /*
-  * Cmdstream submission:
-@@ -283,6 +284,54 @@ static int submit_reloc(struct etnaviv_g
- 	return 0;
- }
- 
-+static int submit_perfmon_validate(struct etnaviv_gem_submit *submit,
-+		struct etnaviv_cmdbuf *cmdbuf,
-+		const struct drm_etnaviv_gem_submit_pmr *pmrs,
-+		u32 nr_pms)
-+{
-+	u32 i;
-+
-+	for (i = 0; i < nr_pms; i++) {
-+		const struct drm_etnaviv_gem_submit_pmr *r = pmrs + i;
-+		struct etnaviv_gem_submit_bo *bo;
-+		int ret;
-+
-+		ret = submit_bo(submit, r->read_idx, &bo);
-+		if (ret)
-+			return ret;
-+
-+		/* at offset 0 a sequence number gets stored used for userspace sync */
-+		if (r->read_offset == 0) {
-+			DRM_ERROR("perfmon request: offset is 0");
-+			return -EINVAL;
-+		}
-+
-+		if (r->read_offset >= bo->obj->base.size - sizeof(u32)) {
-+			DRM_ERROR("perfmon request: offset %u outside object", i);
-+			return -EINVAL;
-+		}
-+
-+		if (r->flags & ~(ETNA_PM_PROCESS_PRE | ETNA_PM_PROCESS_POST)) {
-+			DRM_ERROR("perfmon request: flags are not valid");
-+			return -EINVAL;
-+		}
-+
-+		if (etnaviv_pm_req_validate(r, cmdbuf->exec_state)) {
-+			DRM_ERROR("perfmon request: domain or signal not valid");
-+			return -EINVAL;
-+		}
-+
-+		cmdbuf->pmrs[i].flags = r->flags;
-+		cmdbuf->pmrs[i].domain = r->domain;
-+		cmdbuf->pmrs[i].signal = r->signal;
-+		cmdbuf->pmrs[i].sequence = r->sequence;
-+		cmdbuf->pmrs[i].offset = r->read_offset;
-+		cmdbuf->pmrs[i].bo_vma = etnaviv_gem_vmap(&bo->obj->base);
-+	}
-+
-+	return 0;
-+}
-+
- static void submit_cleanup(struct etnaviv_gem_submit *submit)
- {
- 	unsigned i;
-@@ -306,6 +355,7 @@ int etnaviv_ioctl_gem_submit(struct drm_
- 	struct etnaviv_drm_private *priv = dev->dev_private;
- 	struct drm_etnaviv_gem_submit *args = data;
- 	struct drm_etnaviv_gem_submit_reloc *relocs;
-+	struct drm_etnaviv_gem_submit_pmr *pmrs;
- 	struct drm_etnaviv_gem_submit_bo *bos;
- 	struct etnaviv_gem_submit *submit;
- 	struct etnaviv_cmdbuf *cmdbuf;
-@@ -347,11 +397,12 @@ int etnaviv_ioctl_gem_submit(struct drm_
- 	 */
- 	bos = kvmalloc_array(args->nr_bos, sizeof(*bos), GFP_KERNEL);
- 	relocs = kvmalloc_array(args->nr_relocs, sizeof(*relocs), GFP_KERNEL);
-+	pmrs = kvmalloc_array(args->nr_pmrs, sizeof(*pmrs), GFP_KERNEL);
- 	stream = kvmalloc_array(1, args->stream_size, GFP_KERNEL);
- 	cmdbuf = etnaviv_cmdbuf_new(gpu->cmdbuf_suballoc,
- 				    ALIGN(args->stream_size, 8) + 8,
--				    args->nr_bos);
--	if (!bos || !relocs || !stream || !cmdbuf) {
-+				    args->nr_bos, args->nr_pmrs);
-+	if (!bos || !relocs || !pmrs || !stream || !cmdbuf) {
- 		ret = -ENOMEM;
- 		goto err_submit_cmds;
- 	}
-@@ -373,6 +424,14 @@ int etnaviv_ioctl_gem_submit(struct drm_
- 		goto err_submit_cmds;
- 	}
- 
-+	ret = copy_from_user(pmrs, u64_to_user_ptr(args->pmrs),
-+			     args->nr_pmrs * sizeof(*pmrs));
-+	if (ret) {
-+		ret = -EFAULT;
-+		goto err_submit_cmds;
-+	}
-+	cmdbuf->nr_pmrs = args->nr_pmrs;
-+
- 	ret = copy_from_user(stream, u64_to_user_ptr(args->stream),
- 			     args->stream_size);
- 	if (ret) {
-@@ -441,6 +500,10 @@ int etnaviv_ioctl_gem_submit(struct drm_
- 	if (ret)
- 		goto out;
- 
-+	ret = submit_perfmon_validate(submit, cmdbuf, pmrs, args->nr_pmrs);
-+	if (ret)
-+		goto out;
-+
- 	memcpy(cmdbuf->vaddr, stream, args->stream_size);
- 	cmdbuf->user_size = ALIGN(args->stream_size, 8);
- 
-@@ -496,6 +559,8 @@ err_submit_cmds:
- 		kvfree(bos);
- 	if (relocs)
- 		kvfree(relocs);
-+	if (pmrs)
-+		kvfree(pmrs);
- 
- 	return ret;
- }
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_gpu.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_gpu.c	2017-12-14 06:39:58.494903623 +0100
-@@ -25,6 +25,7 @@
- #include "etnaviv_gpu.h"
- #include "etnaviv_gem.h"
- #include "etnaviv_mmu.h"
-+#include "etnaviv_perfmon.h"
- #include "common.xml.h"
- #include "state.xml.h"
- #include "state_hi.xml.h"
-@@ -420,9 +421,10 @@ static void etnaviv_gpu_update_clock(str
- 			     gpu->base_rate_shader >> gpu->freq_scale);
- 	} else {
- 		unsigned int fscale = 1 << (6 - gpu->freq_scale);
--		u32 clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
--			    VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
-+		u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
- 
-+		clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
-+		clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
- 		etnaviv_gpu_load_clock(gpu, clock);
- 	}
- }
-@@ -433,24 +435,14 @@ static int etnaviv_hw_reset(struct etnav
- 	unsigned long timeout;
- 	bool failed = true;
- 
--	/* TODO
--	 *
--	 * - clock gating
--	 * - puls eater
--	 * - what about VG?
--	 */
--
- 	/* We hope that the GPU resets in under one second */
- 	timeout = jiffies + msecs_to_jiffies(1000);
- 
- 	while (time_is_after_jiffies(timeout)) {
- 		/* enable clock */
--		etnaviv_gpu_update_clock(gpu);
--
--		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
--
--		/* Wait for stable clock.  Vivante's code waited for 1ms */
--		usleep_range(1000, 10000);
-+		unsigned int fscale = 1 << (6 - gpu->freq_scale);
-+		control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
-+		etnaviv_gpu_load_clock(gpu, control);
- 
- 		/* isolate the GPU. */
- 		control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
-@@ -461,7 +453,7 @@ static int etnaviv_hw_reset(struct etnav
- 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
- 
- 		/* wait for reset. */
--		msleep(1);
-+		usleep_range(10, 20);
- 
- 		/* reset soft reset bit. */
- 		control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
-@@ -490,6 +482,10 @@ static int etnaviv_hw_reset(struct etnav
- 			continue;
- 		}
- 
-+		/* disable debug registers, as they are not normally needed */
-+		control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
-+		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
-+
- 		failed = false;
- 		break;
- 	}
-@@ -721,7 +717,7 @@ int etnaviv_gpu_init(struct etnaviv_gpu
- 	}
- 
- 	/* Create buffer: */
--	gpu->buffer = etnaviv_cmdbuf_new(gpu->cmdbuf_suballoc, PAGE_SIZE, 0);
-+	gpu->buffer = etnaviv_cmdbuf_new(gpu->cmdbuf_suballoc, PAGE_SIZE, 0, 0);
- 	if (!gpu->buffer) {
- 		ret = -ENOMEM;
- 		dev_err(gpu->dev, "could not create command buffer\n");
-@@ -739,10 +735,9 @@ int etnaviv_gpu_init(struct etnaviv_gpu
- 	/* Setup event management */
- 	spin_lock_init(&gpu->event_spinlock);
- 	init_completion(&gpu->event_free);
--	for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
--		gpu->event[i].used = false;
-+	bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
-+	for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
- 		complete(&gpu->event_free);
--	}
- 
- 	/* Now program the hardware */
- 	mutex_lock(&gpu->lock);
-@@ -926,7 +921,7 @@ static void recover_worker(struct work_s
- 	struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
- 					       recover_work);
- 	unsigned long flags;
--	unsigned int i;
-+	unsigned int i = 0;
- 
- 	dev_err(gpu->dev, "hangcheck recover!\n");
- 
-@@ -945,14 +940,12 @@ static void recover_worker(struct work_s
- 
- 	/* complete all events, the GPU won't do it after the reset */
- 	spin_lock_irqsave(&gpu->event_spinlock, flags);
--	for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
--		if (!gpu->event[i].used)
--			continue;
-+	for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS) {
- 		dma_fence_signal(gpu->event[i].fence);
- 		gpu->event[i].fence = NULL;
--		gpu->event[i].used = false;
- 		complete(&gpu->event_free);
- 	}
-+	bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
- 	spin_unlock_irqrestore(&gpu->event_spinlock, flags);
- 	gpu->completed_fence = gpu->active_fence;
- 
-@@ -1140,30 +1133,45 @@ int etnaviv_gpu_fence_sync_obj(struct et
-  * event management:
-  */
- 
--static unsigned int event_alloc(struct etnaviv_gpu *gpu)
-+static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
-+	unsigned int *events)
- {
--	unsigned long ret, flags;
--	unsigned int i, event = ~0U;
-+	unsigned long flags, timeout = msecs_to_jiffies(10 * 10000);
-+	unsigned i, acquired = 0;
- 
--	ret = wait_for_completion_timeout(&gpu->event_free,
--					  msecs_to_jiffies(10 * 10000));
--	if (!ret)
--		dev_err(gpu->dev, "wait_for_completion_timeout failed");
-+	for (i = 0; i < nr_events; i++) {
-+		unsigned long ret;
- 
--	spin_lock_irqsave(&gpu->event_spinlock, flags);
-+		ret = wait_for_completion_timeout(&gpu->event_free, timeout);
- 
--	/* find first free event */
--	for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
--		if (gpu->event[i].used == false) {
--			gpu->event[i].used = true;
--			event = i;
--			break;
-+		if (!ret) {
-+			dev_err(gpu->dev, "wait_for_completion_timeout failed");
-+			goto out;
- 		}
-+
-+		acquired++;
-+		timeout = ret;
-+	}
-+
-+	spin_lock_irqsave(&gpu->event_spinlock, flags);
-+
-+	for (i = 0; i < nr_events; i++) {
-+		int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
-+
-+		events[i] = event;
-+		memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
-+		set_bit(event, gpu->event_bitmap);
- 	}
- 
- 	spin_unlock_irqrestore(&gpu->event_spinlock, flags);
- 
--	return event;
-+	return 0;
-+
-+out:
-+	for (i = 0; i < acquired; i++)
-+		complete(&gpu->event_free);
-+
-+	return -EBUSY;
- }
- 
- static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
-@@ -1172,12 +1180,12 @@ static void event_free(struct etnaviv_gp
- 
- 	spin_lock_irqsave(&gpu->event_spinlock, flags);
- 
--	if (gpu->event[event].used == false) {
-+	if (!test_bit(event, gpu->event_bitmap)) {
- 		dev_warn(gpu->dev, "event %u is already marked as free",
- 			 event);
- 		spin_unlock_irqrestore(&gpu->event_spinlock, flags);
- 	} else {
--		gpu->event[event].used = false;
-+		clear_bit(event, gpu->event_bitmap);
- 		spin_unlock_irqrestore(&gpu->event_spinlock, flags);
- 
- 		complete(&gpu->event_free);
-@@ -1311,12 +1319,71 @@ void etnaviv_gpu_pm_put(struct etnaviv_g
- 	pm_runtime_put_autosuspend(gpu->dev);
- }
- 
-+static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
-+	struct etnaviv_event *event, unsigned int flags)
-+{
-+	const struct etnaviv_cmdbuf *cmdbuf = event->cmdbuf;
-+	unsigned int i;
-+
-+	for (i = 0; i < cmdbuf->nr_pmrs; i++) {
-+		const struct etnaviv_perfmon_request *pmr = cmdbuf->pmrs + i;
-+
-+		if (pmr->flags == flags)
-+			etnaviv_perfmon_process(gpu, pmr);
-+	}
-+}
-+
-+static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
-+	struct etnaviv_event *event)
-+{
-+	u32 val;
-+
-+	/* disable clock gating */
-+	val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
-+	val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
-+	gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
-+
-+	/* enable debug register */
-+	val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
-+	val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
-+	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
-+
-+	sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
-+}
-+
-+static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
-+	struct etnaviv_event *event)
-+{
-+	const struct etnaviv_cmdbuf *cmdbuf = event->cmdbuf;
-+	unsigned int i;
-+	u32 val;
-+
-+	sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
-+
-+	for (i = 0; i < cmdbuf->nr_pmrs; i++) {
-+		const struct etnaviv_perfmon_request *pmr = cmdbuf->pmrs + i;
-+
-+		*pmr->bo_vma = pmr->sequence;
-+	}
-+
-+	/* disable debug register */
-+	val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
-+	val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
-+	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
-+
-+	/* enable clock gating */
-+	val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
-+	val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
-+	gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
-+}
-+
-+
- /* add bo's to gpu's ring, and kick gpu: */
- int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
- 	struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf)
- {
- 	struct dma_fence *fence;
--	unsigned int event, i;
-+	unsigned int i, nr_events = 1, event[3];
- 	int ret;
- 
- 	ret = etnaviv_gpu_pm_get_sync(gpu);
-@@ -1332,10 +1399,19 @@ int etnaviv_gpu_submit(struct etnaviv_gp
- 	 *
- 	 */
- 
--	event = event_alloc(gpu);
--	if (unlikely(event == ~0U)) {
--		DRM_ERROR("no free event\n");
--		ret = -EBUSY;
-+	/*
-+	 * if there are performance monitor requests we need to have
-+	 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
-+	 *   requests.
-+	 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
-+	 *   and update the sequence number for userspace.
-+	 */
-+	if (cmdbuf->nr_pmrs)
-+		nr_events = 3;
-+
-+	ret = event_alloc(gpu, nr_events, event);
-+	if (ret) {
-+		DRM_ERROR("no free events\n");
- 		goto out_pm_put;
- 	}
- 
-@@ -1343,12 +1419,14 @@ int etnaviv_gpu_submit(struct etnaviv_gp
- 
- 	fence = etnaviv_gpu_fence_alloc(gpu);
- 	if (!fence) {
--		event_free(gpu, event);
-+		for (i = 0; i < nr_events; i++)
-+			event_free(gpu, event[i]);
-+
- 		ret = -ENOMEM;
- 		goto out_unlock;
- 	}
- 
--	gpu->event[event].fence = fence;
-+	gpu->event[event[0]].fence = fence;
- 	submit->fence = dma_fence_get(fence);
- 	gpu->active_fence = submit->fence->seqno;
- 
-@@ -1358,7 +1436,19 @@ int etnaviv_gpu_submit(struct etnaviv_gp
- 		gpu->lastctx = cmdbuf->ctx;
- 	}
- 
--	etnaviv_buffer_queue(gpu, event, cmdbuf);
-+	if (cmdbuf->nr_pmrs) {
-+		gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
-+		gpu->event[event[1]].cmdbuf = cmdbuf;
-+		etnaviv_sync_point_queue(gpu, event[1]);
-+	}
-+
-+	etnaviv_buffer_queue(gpu, event[0], cmdbuf);
-+
-+	if (cmdbuf->nr_pmrs) {
-+		gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
-+		gpu->event[event[2]].cmdbuf = cmdbuf;
-+		etnaviv_sync_point_queue(gpu, event[2]);
-+	}
- 
- 	cmdbuf->fence = fence;
- 	list_add_tail(&cmdbuf->node, &gpu->active_cmd_list);
-@@ -1394,6 +1484,24 @@ out_pm_put:
- 	return ret;
- }
- 
-+static void etnaviv_process_sync_point(struct etnaviv_gpu *gpu,
-+	struct etnaviv_event *event)
-+{
-+	u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
-+
-+	event->sync_point(gpu, event);
-+	etnaviv_gpu_start_fe(gpu, addr + 2, 2);
-+}
-+
-+static void sync_point_worker(struct work_struct *work)
-+{
-+	struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
-+					       sync_point_work);
-+
-+	etnaviv_process_sync_point(gpu, &gpu->event[gpu->sync_point_event]);
-+	event_free(gpu, gpu->sync_point_event);
-+}
-+
- /*
-  * Init/Cleanup:
-  */
-@@ -1440,7 +1548,15 @@ static irqreturn_t irq_handler(int irq,
- 
- 			dev_dbg(gpu->dev, "event %u\n", event);
- 
-+			if (gpu->event[event].sync_point) {
-+				gpu->sync_point_event = event;
-+				etnaviv_queue_work(gpu->drm, &gpu->sync_point_work);
-+			}
-+
- 			fence = gpu->event[event].fence;
-+			if (!fence)
-+				continue;
-+
- 			gpu->event[event].fence = NULL;
- 			dma_fence_signal(fence);
- 
-@@ -1645,6 +1761,7 @@ static int etnaviv_gpu_bind(struct devic
- 
- 	INIT_LIST_HEAD(&gpu->active_cmd_list);
- 	INIT_WORK(&gpu->retire_work, retire_worker);
-+	INIT_WORK(&gpu->sync_point_work, sync_point_worker);
- 	INIT_WORK(&gpu->recover_work, recover_worker);
- 	init_waitqueue_head(&gpu->fence_event);
- 
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_gpu.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_gpu.h	2017-12-14 06:39:58.495903623 +0100
-@@ -88,13 +88,17 @@ struct etnaviv_chip_identity {
- };
- 
- struct etnaviv_event {
--	bool used;
- 	struct dma_fence *fence;
-+	struct etnaviv_cmdbuf *cmdbuf;
-+
-+	void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
- };
- 
- struct etnaviv_cmdbuf_suballoc;
- struct etnaviv_cmdbuf;
- 
-+#define ETNA_NR_EVENTS 30
-+
- struct etnaviv_gpu {
- 	struct drm_device *drm;
- 	struct thermal_cooling_device *cooling;
-@@ -112,7 +116,8 @@ struct etnaviv_gpu {
- 	u32 memory_base;
- 
- 	/* event management: */
--	struct etnaviv_event event[30];
-+	DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS);
-+	struct etnaviv_event event[ETNA_NR_EVENTS];
- 	struct completion event_free;
- 	spinlock_t event_spinlock;
- 
-@@ -133,6 +138,10 @@ struct etnaviv_gpu {
- 	/* worker for handling active-list retiring: */
- 	struct work_struct retire_work;
- 
-+	/* worker for handling 'sync' points: */
-+	struct work_struct sync_point_work;
-+	int sync_point_event;
-+
- 	void __iomem *mmio;
- 	int irq;
- 
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_iommu.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_iommu.c	2017-12-14 06:39:58.495903623 +0100
-@@ -14,7 +14,6 @@
-  * this program.  If not, see <http://www.gnu.org/licenses/>.
-  */
- 
--#include <linux/iommu.h>
- #include <linux/platform_device.h>
- #include <linux/sizes.h>
- #include <linux/slab.h>
-@@ -31,174 +30,115 @@
- 
- #define GPU_MEM_START	0x80000000
- 
--struct etnaviv_iommu_domain_pgtable {
--	u32 *pgtable;
--	dma_addr_t paddr;
-+struct etnaviv_iommuv1_domain {
-+	struct etnaviv_iommu_domain base;
-+	u32 *pgtable_cpu;
-+	dma_addr_t pgtable_dma;
- };
- 
--struct etnaviv_iommu_domain {
--	struct iommu_domain domain;
--	struct device *dev;
--	void *bad_page_cpu;
--	dma_addr_t bad_page_dma;
--	struct etnaviv_iommu_domain_pgtable pgtable;
--	spinlock_t map_lock;
--};
--
--static struct etnaviv_iommu_domain *to_etnaviv_domain(struct iommu_domain *domain)
--{
--	return container_of(domain, struct etnaviv_iommu_domain, domain);
--}
--
--static int pgtable_alloc(struct etnaviv_iommu_domain_pgtable *pgtable,
--			 size_t size)
--{
--	pgtable->pgtable = dma_alloc_coherent(NULL, size, &pgtable->paddr, GFP_KERNEL);
--	if (!pgtable->pgtable)
--		return -ENOMEM;
--
--	return 0;
--}
--
--static void pgtable_free(struct etnaviv_iommu_domain_pgtable *pgtable,
--			 size_t size)
-+static struct etnaviv_iommuv1_domain *
-+to_etnaviv_domain(struct etnaviv_iommu_domain *domain)
- {
--	dma_free_coherent(NULL, size, pgtable->pgtable, pgtable->paddr);
--}
--
--static u32 pgtable_read(struct etnaviv_iommu_domain_pgtable *pgtable,
--			   unsigned long iova)
--{
--	/* calcuate index into page table */
--	unsigned int index = (iova - GPU_MEM_START) / SZ_4K;
--	phys_addr_t paddr;
--
--	paddr = pgtable->pgtable[index];
--
--	return paddr;
-+	return container_of(domain, struct etnaviv_iommuv1_domain, base);
- }
- 
--static void pgtable_write(struct etnaviv_iommu_domain_pgtable *pgtable,
--			  unsigned long iova, phys_addr_t paddr)
--{
--	/* calcuate index into page table */
--	unsigned int index = (iova - GPU_MEM_START) / SZ_4K;
--
--	pgtable->pgtable[index] = paddr;
--}
--
--static int __etnaviv_iommu_init(struct etnaviv_iommu_domain *etnaviv_domain)
-+static int __etnaviv_iommu_init(struct etnaviv_iommuv1_domain *etnaviv_domain)
- {
- 	u32 *p;
--	int ret, i;
-+	int i;
- 
--	etnaviv_domain->bad_page_cpu = dma_alloc_coherent(etnaviv_domain->dev,
--						  SZ_4K,
--						  &etnaviv_domain->bad_page_dma,
--						  GFP_KERNEL);
--	if (!etnaviv_domain->bad_page_cpu)
-+	etnaviv_domain->base.bad_page_cpu = dma_alloc_coherent(
-+						etnaviv_domain->base.dev,
-+						SZ_4K,
-+						&etnaviv_domain->base.bad_page_dma,
-+						GFP_KERNEL);
-+	if (!etnaviv_domain->base.bad_page_cpu)
- 		return -ENOMEM;
- 
--	p = etnaviv_domain->bad_page_cpu;
-+	p = etnaviv_domain->base.bad_page_cpu;
- 	for (i = 0; i < SZ_4K / 4; i++)
- 		*p++ = 0xdead55aa;
- 
--	ret = pgtable_alloc(&etnaviv_domain->pgtable, PT_SIZE);
--	if (ret < 0) {
--		dma_free_coherent(etnaviv_domain->dev, SZ_4K,
--				  etnaviv_domain->bad_page_cpu,
--				  etnaviv_domain->bad_page_dma);
--		return ret;
-+	etnaviv_domain->pgtable_cpu =
-+			dma_alloc_coherent(etnaviv_domain->base.dev, PT_SIZE,
-+					   &etnaviv_domain->pgtable_dma,
-+					   GFP_KERNEL);
-+	if (!etnaviv_domain->pgtable_cpu) {
-+		dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
-+				  etnaviv_domain->base.bad_page_cpu,
-+				  etnaviv_domain->base.bad_page_dma);
-+		return -ENOMEM;
- 	}
- 
- 	for (i = 0; i < PT_ENTRIES; i++)
--		etnaviv_domain->pgtable.pgtable[i] =
--			etnaviv_domain->bad_page_dma;
--
--	spin_lock_init(&etnaviv_domain->map_lock);
-+		etnaviv_domain->pgtable_cpu[i] =
-+				etnaviv_domain->base.bad_page_dma;
- 
- 	return 0;
- }
- 
--static void etnaviv_domain_free(struct iommu_domain *domain)
-+static void etnaviv_iommuv1_domain_free(struct etnaviv_iommu_domain *domain)
- {
--	struct etnaviv_iommu_domain *etnaviv_domain = to_etnaviv_domain(domain);
--
--	pgtable_free(&etnaviv_domain->pgtable, PT_SIZE);
-+	struct etnaviv_iommuv1_domain *etnaviv_domain =
-+			to_etnaviv_domain(domain);
- 
--	dma_free_coherent(etnaviv_domain->dev, SZ_4K,
--			  etnaviv_domain->bad_page_cpu,
--			  etnaviv_domain->bad_page_dma);
-+	dma_free_coherent(etnaviv_domain->base.dev, PT_SIZE,
-+			  etnaviv_domain->pgtable_cpu,
-+			  etnaviv_domain->pgtable_dma);
-+
-+	dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
-+			  etnaviv_domain->base.bad_page_cpu,
-+			  etnaviv_domain->base.bad_page_dma);
- 
- 	kfree(etnaviv_domain);
- }
- 
--static int etnaviv_iommuv1_map(struct iommu_domain *domain, unsigned long iova,
--	   phys_addr_t paddr, size_t size, int prot)
-+static int etnaviv_iommuv1_map(struct etnaviv_iommu_domain *domain,
-+			       unsigned long iova, phys_addr_t paddr,
-+			       size_t size, int prot)
- {
--	struct etnaviv_iommu_domain *etnaviv_domain = to_etnaviv_domain(domain);
-+	struct etnaviv_iommuv1_domain *etnaviv_domain = to_etnaviv_domain(domain);
-+	unsigned int index = (iova - GPU_MEM_START) / SZ_4K;
- 
- 	if (size != SZ_4K)
- 		return -EINVAL;
- 
--	spin_lock(&etnaviv_domain->map_lock);
--	pgtable_write(&etnaviv_domain->pgtable, iova, paddr);
--	spin_unlock(&etnaviv_domain->map_lock);
-+	etnaviv_domain->pgtable_cpu[index] = paddr;
- 
- 	return 0;
- }
- 
--static size_t etnaviv_iommuv1_unmap(struct iommu_domain *domain,
-+static size_t etnaviv_iommuv1_unmap(struct etnaviv_iommu_domain *domain,
- 	unsigned long iova, size_t size)
- {
--	struct etnaviv_iommu_domain *etnaviv_domain = to_etnaviv_domain(domain);
-+	struct etnaviv_iommuv1_domain *etnaviv_domain =
-+			to_etnaviv_domain(domain);
-+	unsigned int index = (iova - GPU_MEM_START) / SZ_4K;
- 
- 	if (size != SZ_4K)
- 		return -EINVAL;
- 
--	spin_lock(&etnaviv_domain->map_lock);
--	pgtable_write(&etnaviv_domain->pgtable, iova,
--		      etnaviv_domain->bad_page_dma);
--	spin_unlock(&etnaviv_domain->map_lock);
-+	etnaviv_domain->pgtable_cpu[index] = etnaviv_domain->base.bad_page_dma;
- 
- 	return SZ_4K;
- }
- 
--static phys_addr_t etnaviv_iommu_iova_to_phys(struct iommu_domain *domain,
--	dma_addr_t iova)
--{
--	struct etnaviv_iommu_domain *etnaviv_domain = to_etnaviv_domain(domain);
--
--	return pgtable_read(&etnaviv_domain->pgtable, iova);
--}
--
--static size_t etnaviv_iommuv1_dump_size(struct iommu_domain *domain)
-+static size_t etnaviv_iommuv1_dump_size(struct etnaviv_iommu_domain *domain)
- {
- 	return PT_SIZE;
- }
- 
--static void etnaviv_iommuv1_dump(struct iommu_domain *domain, void *buf)
-+static void etnaviv_iommuv1_dump(struct etnaviv_iommu_domain *domain, void *buf)
- {
--	struct etnaviv_iommu_domain *etnaviv_domain = to_etnaviv_domain(domain);
-+	struct etnaviv_iommuv1_domain *etnaviv_domain =
-+			to_etnaviv_domain(domain);
- 
--	memcpy(buf, etnaviv_domain->pgtable.pgtable, PT_SIZE);
-+	memcpy(buf, etnaviv_domain->pgtable_cpu, PT_SIZE);
- }
- 
--static const struct etnaviv_iommu_ops etnaviv_iommu_ops = {
--	.ops = {
--		.domain_free = etnaviv_domain_free,
--		.map = etnaviv_iommuv1_map,
--		.unmap = etnaviv_iommuv1_unmap,
--		.iova_to_phys = etnaviv_iommu_iova_to_phys,
--		.pgsize_bitmap = SZ_4K,
--	},
--	.dump_size = etnaviv_iommuv1_dump_size,
--	.dump = etnaviv_iommuv1_dump,
--};
--
- void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu)
- {
--	struct etnaviv_iommu_domain *etnaviv_domain =
-+	struct etnaviv_iommuv1_domain *etnaviv_domain =
- 			to_etnaviv_domain(gpu->mmu->domain);
- 	u32 pgtable;
- 
-@@ -210,7 +150,7 @@ void etnaviv_iommuv1_restore(struct etna
- 	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
- 
- 	/* set page table address in MC */
--	pgtable = (u32)etnaviv_domain->pgtable.paddr;
-+	pgtable = (u32)etnaviv_domain->pgtable_dma;
- 
- 	gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable);
- 	gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable);
-@@ -219,28 +159,37 @@ void etnaviv_iommuv1_restore(struct etna
- 	gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable);
- }
- 
--struct iommu_domain *etnaviv_iommuv1_domain_alloc(struct etnaviv_gpu *gpu)
-+const struct etnaviv_iommu_domain_ops etnaviv_iommuv1_ops = {
-+	.free = etnaviv_iommuv1_domain_free,
-+	.map = etnaviv_iommuv1_map,
-+	.unmap = etnaviv_iommuv1_unmap,
-+	.dump_size = etnaviv_iommuv1_dump_size,
-+	.dump = etnaviv_iommuv1_dump,
-+};
-+
-+struct etnaviv_iommu_domain *
-+etnaviv_iommuv1_domain_alloc(struct etnaviv_gpu *gpu)
- {
--	struct etnaviv_iommu_domain *etnaviv_domain;
-+	struct etnaviv_iommuv1_domain *etnaviv_domain;
-+	struct etnaviv_iommu_domain *domain;
- 	int ret;
- 
- 	etnaviv_domain = kzalloc(sizeof(*etnaviv_domain), GFP_KERNEL);
- 	if (!etnaviv_domain)
- 		return NULL;
- 
--	etnaviv_domain->dev = gpu->dev;
-+	domain = &etnaviv_domain->base;
- 
--	etnaviv_domain->domain.type = __IOMMU_DOMAIN_PAGING;
--	etnaviv_domain->domain.ops = &etnaviv_iommu_ops.ops;
--	etnaviv_domain->domain.pgsize_bitmap = SZ_4K;
--	etnaviv_domain->domain.geometry.aperture_start = GPU_MEM_START;
--	etnaviv_domain->domain.geometry.aperture_end = GPU_MEM_START + PT_ENTRIES * SZ_4K - 1;
-+	domain->dev = gpu->dev;
-+	domain->base = GPU_MEM_START;
-+	domain->size = PT_ENTRIES * SZ_4K;
-+	domain->ops = &etnaviv_iommuv1_ops;
- 
- 	ret = __etnaviv_iommu_init(etnaviv_domain);
- 	if (ret)
- 		goto out_free;
- 
--	return &etnaviv_domain->domain;
-+	return &etnaviv_domain->base;
- 
- out_free:
- 	kfree(etnaviv_domain);
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_iommu.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_iommu.h	2017-12-14 06:39:58.495903623 +0100
-@@ -18,11 +18,14 @@
- #define __ETNAVIV_IOMMU_H__
- 
- struct etnaviv_gpu;
-+struct etnaviv_iommu_domain;
- 
--struct iommu_domain *etnaviv_iommuv1_domain_alloc(struct etnaviv_gpu *gpu);
-+struct etnaviv_iommu_domain *
-+etnaviv_iommuv1_domain_alloc(struct etnaviv_gpu *gpu);
- void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu);
- 
--struct iommu_domain *etnaviv_iommuv2_domain_alloc(struct etnaviv_gpu *gpu);
-+struct etnaviv_iommu_domain *
-+etnaviv_iommuv2_domain_alloc(struct etnaviv_gpu *gpu);
- void etnaviv_iommuv2_restore(struct etnaviv_gpu *gpu);
- 
- #endif /* __ETNAVIV_IOMMU_H__ */
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c	2017-12-14 06:39:58.495903623 +0100
-@@ -14,7 +14,6 @@
-  * this program.  If not, see <http://www.gnu.org/licenses/>.
-  */
- 
--#include <linux/iommu.h>
- #include <linux/platform_device.h>
- #include <linux/sizes.h>
- #include <linux/slab.h>
-@@ -40,10 +39,7 @@
- #define MMUv2_MAX_STLB_ENTRIES		1024
- 
- struct etnaviv_iommuv2_domain {
--	struct iommu_domain domain;
--	struct device *dev;
--	void *bad_page_cpu;
--	dma_addr_t bad_page_dma;
-+	struct etnaviv_iommu_domain base;
- 	/* M(aster) TLB aka first level pagetable */
- 	u32 *mtlb_cpu;
- 	dma_addr_t mtlb_dma;
-@@ -52,13 +48,15 @@ struct etnaviv_iommuv2_domain {
- 	dma_addr_t stlb_dma[1024];
- };
- 
--static struct etnaviv_iommuv2_domain *to_etnaviv_domain(struct iommu_domain *domain)
-+static struct etnaviv_iommuv2_domain *
-+to_etnaviv_domain(struct etnaviv_iommu_domain *domain)
- {
--	return container_of(domain, struct etnaviv_iommuv2_domain, domain);
-+	return container_of(domain, struct etnaviv_iommuv2_domain, base);
- }
- 
--static int etnaviv_iommuv2_map(struct iommu_domain *domain, unsigned long iova,
--	   phys_addr_t paddr, size_t size, int prot)
-+static int etnaviv_iommuv2_map(struct etnaviv_iommu_domain *domain,
-+			       unsigned long iova, phys_addr_t paddr,
-+			       size_t size, int prot)
- {
- 	struct etnaviv_iommuv2_domain *etnaviv_domain =
- 			to_etnaviv_domain(domain);
-@@ -68,7 +66,7 @@ static int etnaviv_iommuv2_map(struct io
- 	if (size != SZ_4K)
- 		return -EINVAL;
- 
--	if (prot & IOMMU_WRITE)
-+	if (prot & ETNAVIV_PROT_WRITE)
- 		entry |= MMUv2_PTE_WRITEABLE;
- 
- 	mtlb_entry = (iova & MMUv2_MTLB_MASK) >> MMUv2_MTLB_SHIFT;
-@@ -79,8 +77,8 @@ static int etnaviv_iommuv2_map(struct io
- 	return 0;
- }
- 
--static size_t etnaviv_iommuv2_unmap(struct iommu_domain *domain,
--	unsigned long iova, size_t size)
-+static size_t etnaviv_iommuv2_unmap(struct etnaviv_iommu_domain *domain,
-+				    unsigned long iova, size_t size)
- {
- 	struct etnaviv_iommuv2_domain *etnaviv_domain =
- 			to_etnaviv_domain(domain);
-@@ -97,38 +95,26 @@ static size_t etnaviv_iommuv2_unmap(stru
- 	return SZ_4K;
- }
- 
--static phys_addr_t etnaviv_iommuv2_iova_to_phys(struct iommu_domain *domain,
--	dma_addr_t iova)
--{
--	struct etnaviv_iommuv2_domain *etnaviv_domain =
--			to_etnaviv_domain(domain);
--	int mtlb_entry, stlb_entry;
--
--	mtlb_entry = (iova & MMUv2_MTLB_MASK) >> MMUv2_MTLB_SHIFT;
--	stlb_entry = (iova & MMUv2_STLB_MASK) >> MMUv2_STLB_SHIFT;
--
--	return etnaviv_domain->stlb_cpu[mtlb_entry][stlb_entry] & ~(SZ_4K - 1);
--}
--
- static int etnaviv_iommuv2_init(struct etnaviv_iommuv2_domain *etnaviv_domain)
- {
- 	u32 *p;
- 	int ret, i, j;
- 
- 	/* allocate scratch page */
--	etnaviv_domain->bad_page_cpu = dma_alloc_coherent(etnaviv_domain->dev,
--						  SZ_4K,
--						  &etnaviv_domain->bad_page_dma,
--						  GFP_KERNEL);
--	if (!etnaviv_domain->bad_page_cpu) {
-+	etnaviv_domain->base.bad_page_cpu = dma_alloc_coherent(
-+						etnaviv_domain->base.dev,
-+						SZ_4K,
-+						&etnaviv_domain->base.bad_page_dma,
-+						GFP_KERNEL);
-+	if (!etnaviv_domain->base.bad_page_cpu) {
- 		ret = -ENOMEM;
- 		goto fail_mem;
- 	}
--	p = etnaviv_domain->bad_page_cpu;
-+	p = etnaviv_domain->base.bad_page_cpu;
- 	for (i = 0; i < SZ_4K / 4; i++)
- 		*p++ = 0xdead55aa;
- 
--	etnaviv_domain->mtlb_cpu = dma_alloc_coherent(etnaviv_domain->dev,
-+	etnaviv_domain->mtlb_cpu = dma_alloc_coherent(etnaviv_domain->base.dev,
- 						  SZ_4K,
- 						  &etnaviv_domain->mtlb_dma,
- 						  GFP_KERNEL);
-@@ -140,7 +126,7 @@ static int etnaviv_iommuv2_init(struct e
- 	/* pre-populate STLB pages (may want to switch to on-demand later) */
- 	for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++) {
- 		etnaviv_domain->stlb_cpu[i] =
--				dma_alloc_coherent(etnaviv_domain->dev,
-+				dma_alloc_coherent(etnaviv_domain->base.dev,
- 						   SZ_4K,
- 						   &etnaviv_domain->stlb_dma[i],
- 						   GFP_KERNEL);
-@@ -159,19 +145,19 @@ static int etnaviv_iommuv2_init(struct e
- 	return 0;
- 
- fail_mem:
--	if (etnaviv_domain->bad_page_cpu)
--		dma_free_coherent(etnaviv_domain->dev, SZ_4K,
--				  etnaviv_domain->bad_page_cpu,
--				  etnaviv_domain->bad_page_dma);
-+	if (etnaviv_domain->base.bad_page_cpu)
-+		dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
-+				  etnaviv_domain->base.bad_page_cpu,
-+				  etnaviv_domain->base.bad_page_dma);
- 
- 	if (etnaviv_domain->mtlb_cpu)
--		dma_free_coherent(etnaviv_domain->dev, SZ_4K,
-+		dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
- 				  etnaviv_domain->mtlb_cpu,
- 				  etnaviv_domain->mtlb_dma);
- 
- 	for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++) {
- 		if (etnaviv_domain->stlb_cpu[i])
--			dma_free_coherent(etnaviv_domain->dev, SZ_4K,
-+			dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
- 					  etnaviv_domain->stlb_cpu[i],
- 					  etnaviv_domain->stlb_dma[i]);
- 	}
-@@ -179,23 +165,23 @@ fail_mem:
- 	return ret;
- }
- 
--static void etnaviv_iommuv2_domain_free(struct iommu_domain *domain)
-+static void etnaviv_iommuv2_domain_free(struct etnaviv_iommu_domain *domain)
- {
- 	struct etnaviv_iommuv2_domain *etnaviv_domain =
- 			to_etnaviv_domain(domain);
- 	int i;
- 
--	dma_free_coherent(etnaviv_domain->dev, SZ_4K,
--			  etnaviv_domain->bad_page_cpu,
--			  etnaviv_domain->bad_page_dma);
-+	dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
-+			  etnaviv_domain->base.bad_page_cpu,
-+			  etnaviv_domain->base.bad_page_dma);
- 
--	dma_free_coherent(etnaviv_domain->dev, SZ_4K,
-+	dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
- 			  etnaviv_domain->mtlb_cpu,
- 			  etnaviv_domain->mtlb_dma);
- 
- 	for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++) {
- 		if (etnaviv_domain->stlb_cpu[i])
--			dma_free_coherent(etnaviv_domain->dev, SZ_4K,
-+			dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
- 					  etnaviv_domain->stlb_cpu[i],
- 					  etnaviv_domain->stlb_dma[i]);
- 	}
-@@ -203,7 +189,7 @@ static void etnaviv_iommuv2_domain_free(
- 	vfree(etnaviv_domain);
- }
- 
--static size_t etnaviv_iommuv2_dump_size(struct iommu_domain *domain)
-+static size_t etnaviv_iommuv2_dump_size(struct etnaviv_iommu_domain *domain)
- {
- 	struct etnaviv_iommuv2_domain *etnaviv_domain =
- 			to_etnaviv_domain(domain);
-@@ -217,7 +203,7 @@ static size_t etnaviv_iommuv2_dump_size(
- 	return dump_size;
- }
- 
--static void etnaviv_iommuv2_dump(struct iommu_domain *domain, void *buf)
-+static void etnaviv_iommuv2_dump(struct etnaviv_iommu_domain *domain, void *buf)
- {
- 	struct etnaviv_iommuv2_domain *etnaviv_domain =
- 			to_etnaviv_domain(domain);
-@@ -230,18 +216,6 @@ static void etnaviv_iommuv2_dump(struct
- 			memcpy(buf, etnaviv_domain->stlb_cpu[i], SZ_4K);
- }
- 
--static const struct etnaviv_iommu_ops etnaviv_iommu_ops = {
--	.ops = {
--		.domain_free = etnaviv_iommuv2_domain_free,
--		.map = etnaviv_iommuv2_map,
--		.unmap = etnaviv_iommuv2_unmap,
--		.iova_to_phys = etnaviv_iommuv2_iova_to_phys,
--		.pgsize_bitmap = SZ_4K,
--	},
--	.dump_size = etnaviv_iommuv2_dump_size,
--	.dump = etnaviv_iommuv2_dump,
--};
--
- void etnaviv_iommuv2_restore(struct etnaviv_gpu *gpu)
- {
- 	struct etnaviv_iommuv2_domain *etnaviv_domain =
-@@ -254,35 +228,45 @@ void etnaviv_iommuv2_restore(struct etna
- 
- 	prefetch = etnaviv_buffer_config_mmuv2(gpu,
- 				(u32)etnaviv_domain->mtlb_dma,
--				(u32)etnaviv_domain->bad_page_dma);
-+				(u32)etnaviv_domain->base.bad_page_dma);
- 	etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(gpu->buffer),
- 			     prefetch);
- 	etnaviv_gpu_wait_idle(gpu, 100);
- 
- 	gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE);
- }
--struct iommu_domain *etnaviv_iommuv2_domain_alloc(struct etnaviv_gpu *gpu)
-+
-+const struct etnaviv_iommu_domain_ops etnaviv_iommuv2_ops = {
-+	.free = etnaviv_iommuv2_domain_free,
-+	.map = etnaviv_iommuv2_map,
-+	.unmap = etnaviv_iommuv2_unmap,
-+	.dump_size = etnaviv_iommuv2_dump_size,
-+	.dump = etnaviv_iommuv2_dump,
-+};
-+
-+struct etnaviv_iommu_domain *
-+etnaviv_iommuv2_domain_alloc(struct etnaviv_gpu *gpu)
- {
- 	struct etnaviv_iommuv2_domain *etnaviv_domain;
-+	struct etnaviv_iommu_domain *domain;
- 	int ret;
- 
- 	etnaviv_domain = vzalloc(sizeof(*etnaviv_domain));
- 	if (!etnaviv_domain)
- 		return NULL;
- 
--	etnaviv_domain->dev = gpu->dev;
-+	domain = &etnaviv_domain->base;
- 
--	etnaviv_domain->domain.type = __IOMMU_DOMAIN_PAGING;
--	etnaviv_domain->domain.ops = &etnaviv_iommu_ops.ops;
--	etnaviv_domain->domain.pgsize_bitmap = SZ_4K;
--	etnaviv_domain->domain.geometry.aperture_start = 0;
--	etnaviv_domain->domain.geometry.aperture_end = ~0UL & ~(SZ_4K - 1);
-+	domain->dev = gpu->dev;
-+	domain->base = 0;
-+	domain->size = (u64)SZ_1G * 4;
-+	domain->ops = &etnaviv_iommuv2_ops;
- 
- 	ret = etnaviv_iommuv2_init(etnaviv_domain);
- 	if (ret)
- 		goto out_free;
- 
--	return &etnaviv_domain->domain;
-+	return &etnaviv_domain->base;
- 
- out_free:
- 	vfree(etnaviv_domain);
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_mmu.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_mmu.c	2017-12-14 06:39:58.495903623 +0100
-@@ -22,17 +22,64 @@
- #include "etnaviv_iommu.h"
- #include "etnaviv_mmu.h"
- 
--static int etnaviv_fault_handler(struct iommu_domain *iommu, struct device *dev,
--		unsigned long iova, int flags, void *arg)
-+static void etnaviv_domain_unmap(struct etnaviv_iommu_domain *domain,
-+				 unsigned long iova, size_t size)
- {
--	DBG("*** fault: iova=%08lx, flags=%d", iova, flags);
--	return 0;
-+	size_t unmapped_page, unmapped = 0;
-+	size_t pgsize = SZ_4K;
-+
-+	if (!IS_ALIGNED(iova | size, pgsize)) {
-+		pr_err("unaligned: iova 0x%lx size 0x%zx min_pagesz 0x%x\n",
-+		       iova, size, pgsize);
-+		return;
-+	}
-+
-+	while (unmapped < size) {
-+		unmapped_page = domain->ops->unmap(domain, iova, pgsize);
-+		if (!unmapped_page)
-+			break;
-+
-+		iova += unmapped_page;
-+		unmapped += unmapped_page;
-+	}
-+}
-+
-+static int etnaviv_domain_map(struct etnaviv_iommu_domain *domain,
-+			      unsigned long iova, phys_addr_t paddr,
-+			      size_t size, int prot)
-+{
-+	unsigned long orig_iova = iova;
-+	size_t pgsize = SZ_4K;
-+	size_t orig_size = size;
-+	int ret = 0;
-+
-+	if (!IS_ALIGNED(iova | paddr | size, pgsize)) {
-+		pr_err("unaligned: iova 0x%lx pa %pa size 0x%zx min_pagesz 0x%x\n",
-+		       iova, &paddr, size, pgsize);
-+		return -EINVAL;
-+	}
-+
-+	while (size) {
-+		ret = domain->ops->map(domain, iova, paddr, pgsize, prot);
-+		if (ret)
-+			break;
-+
-+		iova += pgsize;
-+		paddr += pgsize;
-+		size -= pgsize;
-+	}
-+
-+	/* unroll mapping in case something went wrong */
-+	if (ret)
-+		etnaviv_domain_unmap(domain, orig_iova, orig_size - size);
-+
-+	return ret;
- }
- 
--int etnaviv_iommu_map(struct etnaviv_iommu *iommu, u32 iova,
--		struct sg_table *sgt, unsigned len, int prot)
-+static int etnaviv_iommu_map(struct etnaviv_iommu *iommu, u32 iova,
-+			     struct sg_table *sgt, unsigned len, int prot)
- {
--	struct iommu_domain *domain = iommu->domain;
-+	struct etnaviv_iommu_domain *domain = iommu->domain;
- 	struct scatterlist *sg;
- 	unsigned int da = iova;
- 	unsigned int i, j;
-@@ -47,7 +94,7 @@ int etnaviv_iommu_map(struct etnaviv_iom
- 
- 		VERB("map[%d]: %08x %08x(%zx)", i, iova, pa, bytes);
- 
--		ret = iommu_map(domain, da, pa, bytes, prot);
-+		ret = etnaviv_domain_map(domain, da, pa, bytes, prot);
- 		if (ret)
- 			goto fail;
- 
-@@ -62,27 +109,24 @@ fail:
- 	for_each_sg(sgt->sgl, sg, i, j) {
- 		size_t bytes = sg_dma_len(sg) + sg->offset;
- 
--		iommu_unmap(domain, da, bytes);
-+		etnaviv_domain_unmap(domain, da, bytes);
- 		da += bytes;
- 	}
- 	return ret;
- }
- 
--int etnaviv_iommu_unmap(struct etnaviv_iommu *iommu, u32 iova,
--		struct sg_table *sgt, unsigned len)
-+static void etnaviv_iommu_unmap(struct etnaviv_iommu *iommu, u32 iova,
-+				struct sg_table *sgt, unsigned len)
- {
--	struct iommu_domain *domain = iommu->domain;
-+	struct etnaviv_iommu_domain *domain = iommu->domain;
- 	struct scatterlist *sg;
- 	unsigned int da = iova;
- 	int i;
- 
- 	for_each_sg(sgt->sgl, sg, sgt->nents, i) {
- 		size_t bytes = sg_dma_len(sg) + sg->offset;
--		size_t unmapped;
- 
--		unmapped = iommu_unmap(domain, da, bytes);
--		if (unmapped < bytes)
--			return unmapped;
-+		etnaviv_domain_unmap(domain, da, bytes);
- 
- 		VERB("unmap[%d]: %08x(%zx)", i, iova, bytes);
- 
-@@ -90,8 +134,6 @@ int etnaviv_iommu_unmap(struct etnaviv_i
- 
- 		da += bytes;
- 	}
--
--	return 0;
- }
- 
- static void etnaviv_iommu_remove_mapping(struct etnaviv_iommu *mmu,
-@@ -237,7 +279,7 @@ int etnaviv_iommu_map_gem(struct etnaviv
- 	mmu->last_iova = node->start + etnaviv_obj->base.size;
- 	mapping->iova = node->start;
- 	ret = etnaviv_iommu_map(mmu, node->start, sgt, etnaviv_obj->base.size,
--				IOMMU_READ | IOMMU_WRITE);
-+				ETNAVIV_PROT_READ | ETNAVIV_PROT_WRITE);
- 
- 	if (ret < 0) {
- 		drm_mm_remove_node(node);
-@@ -271,7 +313,7 @@ void etnaviv_iommu_unmap_gem(struct etna
- void etnaviv_iommu_destroy(struct etnaviv_iommu *mmu)
- {
- 	drm_mm_takedown(&mmu->mm);
--	iommu_domain_free(mmu->domain);
-+	mmu->domain->ops->free(mmu->domain);
- 	kfree(mmu);
- }
- 
-@@ -303,11 +345,7 @@ struct etnaviv_iommu *etnaviv_iommu_new(
- 	mutex_init(&mmu->lock);
- 	INIT_LIST_HEAD(&mmu->mappings);
- 
--	drm_mm_init(&mmu->mm, mmu->domain->geometry.aperture_start,
--		    mmu->domain->geometry.aperture_end -
--		    mmu->domain->geometry.aperture_start + 1);
--
--	iommu_set_fault_handler(mmu->domain, etnaviv_fault_handler, gpu->dev);
-+	drm_mm_init(&mmu->mm, mmu->domain->base, mmu->domain->size);
- 
- 	return mmu;
- }
-@@ -338,8 +376,8 @@ int etnaviv_iommu_get_suballoc_va(struct
- 			mutex_unlock(&mmu->lock);
- 			return ret;
- 		}
--		ret = iommu_map(mmu->domain, vram_node->start, paddr, size,
--				IOMMU_READ);
-+		ret = etnaviv_domain_map(mmu->domain, vram_node->start, paddr,
-+					 size, ETNAVIV_PROT_READ);
- 		if (ret < 0) {
- 			drm_mm_remove_node(vram_node);
- 			mutex_unlock(&mmu->lock);
-@@ -362,25 +400,17 @@ void etnaviv_iommu_put_suballoc_va(struc
- 
- 	if (mmu->version == ETNAVIV_IOMMU_V2) {
- 		mutex_lock(&mmu->lock);
--		iommu_unmap(mmu->domain,iova, size);
-+		etnaviv_domain_unmap(mmu->domain, iova, size);
- 		drm_mm_remove_node(vram_node);
- 		mutex_unlock(&mmu->lock);
- 	}
- }
- size_t etnaviv_iommu_dump_size(struct etnaviv_iommu *iommu)
- {
--	struct etnaviv_iommu_ops *ops;
--
--	ops = container_of(iommu->domain->ops, struct etnaviv_iommu_ops, ops);
--
--	return ops->dump_size(iommu->domain);
-+	return iommu->domain->ops->dump_size(iommu->domain);
- }
- 
- void etnaviv_iommu_dump(struct etnaviv_iommu *iommu, void *buf)
- {
--	struct etnaviv_iommu_ops *ops;
--
--	ops = container_of(iommu->domain->ops, struct etnaviv_iommu_ops, ops);
--
--	ops->dump(iommu->domain, buf);
-+	iommu->domain->ops->dump(iommu->domain, buf);
- }
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_mmu.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_mmu.h	2017-12-14 06:39:58.495903623 +0100
-@@ -17,7 +17,8 @@
- #ifndef __ETNAVIV_MMU_H__
- #define __ETNAVIV_MMU_H__
- 
--#include <linux/iommu.h>
-+#define ETNAVIV_PROT_READ	(1 << 0)
-+#define ETNAVIV_PROT_WRITE	(1 << 1)
- 
- enum etnaviv_iommu_version {
- 	ETNAVIV_IOMMU_V1 = 0,
-@@ -26,16 +27,31 @@ enum etnaviv_iommu_version {
- 
- struct etnaviv_gpu;
- struct etnaviv_vram_mapping;
-+struct etnaviv_iommu_domain;
- 
--struct etnaviv_iommu_ops {
--	struct iommu_ops ops;
--	size_t (*dump_size)(struct iommu_domain *);
--	void (*dump)(struct iommu_domain *, void *);
-+struct etnaviv_iommu_domain_ops {
-+	void (*free)(struct etnaviv_iommu_domain *);
-+	int (*map)(struct etnaviv_iommu_domain *domain, unsigned long iova,
-+		   phys_addr_t paddr, size_t size, int prot);
-+	size_t (*unmap)(struct etnaviv_iommu_domain *domain, unsigned long iova,
-+			size_t size);
-+	size_t (*dump_size)(struct etnaviv_iommu_domain *);
-+	void (*dump)(struct etnaviv_iommu_domain *, void *);
-+};
-+
-+struct etnaviv_iommu_domain {
-+	struct device *dev;
-+	void *bad_page_cpu;
-+	dma_addr_t bad_page_dma;
-+	u64 base;
-+	u64 size;
-+
-+	const struct etnaviv_iommu_domain_ops *ops;
- };
- 
- struct etnaviv_iommu {
- 	struct etnaviv_gpu *gpu;
--	struct iommu_domain *domain;
-+	struct etnaviv_iommu_domain *domain;
- 
- 	enum etnaviv_iommu_version version;
- 
-@@ -49,18 +65,11 @@ struct etnaviv_iommu {
- 
- struct etnaviv_gem_object;
- 
--int etnaviv_iommu_attach(struct etnaviv_iommu *iommu, const char **names,
--	int cnt);
--int etnaviv_iommu_map(struct etnaviv_iommu *iommu, u32 iova,
--	struct sg_table *sgt, unsigned len, int prot);
--int etnaviv_iommu_unmap(struct etnaviv_iommu *iommu, u32 iova,
--	struct sg_table *sgt, unsigned len);
- int etnaviv_iommu_map_gem(struct etnaviv_iommu *mmu,
- 	struct etnaviv_gem_object *etnaviv_obj, u32 memory_base,
- 	struct etnaviv_vram_mapping *mapping);
- void etnaviv_iommu_unmap_gem(struct etnaviv_iommu *mmu,
- 	struct etnaviv_vram_mapping *mapping);
--void etnaviv_iommu_destroy(struct etnaviv_iommu *iommu);
- 
- int etnaviv_iommu_get_suballoc_va(struct etnaviv_gpu *gpu, dma_addr_t paddr,
- 				  struct drm_mm_node *vram_node, size_t size,
-@@ -73,6 +82,7 @@ size_t etnaviv_iommu_dump_size(struct et
- void etnaviv_iommu_dump(struct etnaviv_iommu *iommu, void *buf);
- 
- struct etnaviv_iommu *etnaviv_iommu_new(struct etnaviv_gpu *gpu);
-+void etnaviv_iommu_destroy(struct etnaviv_iommu *iommu);
- void etnaviv_iommu_restore(struct etnaviv_gpu *gpu);
- 
- #endif /* __ETNAVIV_MMU_H__ */
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c.0130~	2017-12-14 06:39:58.495903623 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c	2017-12-14 06:39:58.495903623 +0100
-@@ -0,0 +1,495 @@
-+/*
-+ * Copyright (C) 2017 Etnaviv Project
-+ * Copyright (C) 2017 Zodiac Inflight Innovations
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include "etnaviv_gpu.h"
-+#include "etnaviv_perfmon.h"
-+#include "state_hi.xml.h"
-+
-+struct etnaviv_pm_domain;
-+
-+struct etnaviv_pm_signal {
-+	char name[64];
-+	u32 data;
-+
-+	u32 (*sample)(struct etnaviv_gpu *gpu,
-+	              const struct etnaviv_pm_domain *domain,
-+	              const struct etnaviv_pm_signal *signal);
-+};
-+
-+struct etnaviv_pm_domain {
-+	char name[64];
-+
-+	/* profile register */
-+	u32 profile_read;
-+	u32 profile_config;
-+
-+	u8 nr_signals;
-+	const struct etnaviv_pm_signal *signal;
-+};
-+
-+struct etnaviv_pm_domain_meta {
-+	const struct etnaviv_pm_domain *domains;
-+	u32 nr_domains;
-+};
-+
-+static u32 simple_reg_read(struct etnaviv_gpu *gpu,
-+	const struct etnaviv_pm_domain *domain,
-+	const struct etnaviv_pm_signal *signal)
-+{
-+	return gpu_read(gpu, signal->data);
-+}
-+
-+static u32 perf_reg_read(struct etnaviv_gpu *gpu,
-+	const struct etnaviv_pm_domain *domain,
-+	const struct etnaviv_pm_signal *signal)
-+{
-+	gpu_write(gpu, domain->profile_config, signal->data);
-+
-+	return gpu_read(gpu, domain->profile_read);
-+}
-+
-+static u32 pipe_reg_read(struct etnaviv_gpu *gpu,
-+	const struct etnaviv_pm_domain *domain,
-+	const struct etnaviv_pm_signal *signal)
-+{
-+	u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
-+	u32 value = 0;
-+	unsigned i;
-+
-+	for (i = 0; i < gpu->identity.pixel_pipes; i++) {
-+		clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
-+		clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(i);
-+		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
-+		gpu_write(gpu, domain->profile_config, signal->data);
-+		value += gpu_read(gpu, domain->profile_read);
-+	}
-+
-+	/* switch back to pixel pipe 0 to prevent GPU hang */
-+	clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
-+	clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(0);
-+	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
-+
-+	return value;
-+}
-+
-+static const struct etnaviv_pm_domain doms_3d[] = {
-+	{
-+		.name = "HI",
-+		.profile_read = VIVS_MC_PROFILE_HI_READ,
-+		.profile_config = VIVS_MC_PROFILE_CONFIG2,
-+		.nr_signals = 5,
-+		.signal = (const struct etnaviv_pm_signal[]) {
-+			{
-+				"TOTAL_CYCLES",
-+				VIVS_HI_PROFILE_TOTAL_CYCLES,
-+				&simple_reg_read
-+			},
-+			{
-+				"IDLE_CYCLES",
-+				VIVS_HI_PROFILE_IDLE_CYCLES,
-+				&simple_reg_read
-+			},
-+			{
-+				"AXI_CYCLES_READ_REQUEST_STALLED",
-+				VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED,
-+				&perf_reg_read
-+			},
-+			{
-+				"AXI_CYCLES_WRITE_REQUEST_STALLED",
-+				VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED,
-+				&perf_reg_read
-+			},
-+			{
-+				"AXI_CYCLES_WRITE_DATA_STALLED",
-+				VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED,
-+				&perf_reg_read
-+			}
-+		}
-+	},
-+	{
-+		.name = "PE",
-+		.profile_read = VIVS_MC_PROFILE_PE_READ,
-+		.profile_config = VIVS_MC_PROFILE_CONFIG0,
-+		.nr_signals = 5,
-+		.signal = (const struct etnaviv_pm_signal[]) {
-+			{
-+				"PIXEL_COUNT_KILLED_BY_COLOR_PIPE",
-+				VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE,
-+				&pipe_reg_read
-+			},
-+			{
-+				"PIXEL_COUNT_KILLED_BY_DEPTH_PIPE",
-+				VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE,
-+				&pipe_reg_read
-+			},
-+			{
-+				"PIXEL_COUNT_DRAWN_BY_COLOR_PIPE",
-+				VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE,
-+				&pipe_reg_read
-+			},
-+			{
-+				"PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE",
-+				VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE,
-+				&pipe_reg_read
-+			}
-+		}
-+	},
-+	{
-+		.name = "SH",
-+		.profile_read = VIVS_MC_PROFILE_SH_READ,
-+		.profile_config = VIVS_MC_PROFILE_CONFIG0,
-+		.nr_signals = 9,
-+		.signal = (const struct etnaviv_pm_signal[]) {
-+			{
-+				"SHADER_CYCLES",
-+				VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES,
-+				&perf_reg_read
-+			},
-+			{
-+				"PS_INST_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER,
-+				&perf_reg_read
-+			},
-+			{
-+				"RENDERED_PIXEL_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER,
-+				&perf_reg_read
-+			},
-+			{
-+				"VS_INST_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER,
-+				&pipe_reg_read
-+			},
-+			{
-+				"RENDERED_VERTICE_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER,
-+				&pipe_reg_read
-+			},
-+			{
-+				"VTX_BRANCH_INST_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER,
-+				&pipe_reg_read
-+			},
-+			{
-+				"VTX_TEXLD_INST_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER,
-+				&pipe_reg_read
-+			},
-+			{
-+				"PXL_BRANCH_INST_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER,
-+				&pipe_reg_read
-+			},
-+			{
-+				"PXL_TEXLD_INST_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER,
-+				&pipe_reg_read
-+			}
-+		}
-+	},
-+	{
-+		.name = "PA",
-+		.profile_read = VIVS_MC_PROFILE_PA_READ,
-+		.profile_config = VIVS_MC_PROFILE_CONFIG1,
-+		.nr_signals = 6,
-+		.signal = (const struct etnaviv_pm_signal[]) {
-+			{
-+				"INPUT_VTX_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER,
-+				&perf_reg_read
-+			},
-+			{
-+				"INPUT_PRIM_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER,
-+				&perf_reg_read
-+			},
-+			{
-+				"OUTPUT_PRIM_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER,
-+				&perf_reg_read
-+			},
-+			{
-+				"DEPTH_CLIPPED_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER,
-+				&pipe_reg_read
-+			},
-+			{
-+				"TRIVIAL_REJECTED_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER,
-+				&pipe_reg_read
-+			},
-+			{
-+				"CULLED_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER,
-+				&pipe_reg_read
-+			}
-+		}
-+	},
-+	{
-+		.name = "SE",
-+		.profile_read = VIVS_MC_PROFILE_SE_READ,
-+		.profile_config = VIVS_MC_PROFILE_CONFIG1,
-+		.nr_signals = 2,
-+		.signal = (const struct etnaviv_pm_signal[]) {
-+			{
-+				"CULLED_TRIANGLE_COUNT",
-+				VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT,
-+				&perf_reg_read
-+			},
-+			{
-+				"CULLED_LINES_COUNT",
-+				VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT,
-+				&perf_reg_read
-+			}
-+		}
-+	},
-+	{
-+		.name = "RA",
-+		.profile_read = VIVS_MC_PROFILE_RA_READ,
-+		.profile_config = VIVS_MC_PROFILE_CONFIG1,
-+		.nr_signals = 7,
-+		.signal = (const struct etnaviv_pm_signal[]) {
-+			{
-+				"VALID_PIXEL_COUNT",
-+				VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT,
-+				&perf_reg_read
-+			},
-+			{
-+				"TOTAL_QUAD_COUNT",
-+				VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT,
-+				&perf_reg_read
-+			},
-+			{
-+				"VALID_QUAD_COUNT_AFTER_EARLY_Z",
-+				VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z,
-+				&perf_reg_read
-+			},
-+			{
-+				"TOTAL_PRIMITIVE_COUNT",
-+				VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT,
-+				&perf_reg_read
-+			},
-+			{
-+				"PIPE_CACHE_MISS_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER,
-+				&perf_reg_read
-+			},
-+			{
-+				"PREFETCH_CACHE_MISS_COUNTER",
-+				VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER,
-+				&perf_reg_read
-+			},
-+			{
-+				"CULLED_QUAD_COUNT",
-+				VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT,
-+				&perf_reg_read
-+			}
-+		}
-+	},
-+	{
-+		.name = "TX",
-+		.profile_read = VIVS_MC_PROFILE_TX_READ,
-+		.profile_config = VIVS_MC_PROFILE_CONFIG1,
-+		.nr_signals = 9,
-+		.signal = (const struct etnaviv_pm_signal[]) {
-+			{
-+				"TOTAL_BILINEAR_REQUESTS",
-+				VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS,
-+				&perf_reg_read
-+			},
-+			{
-+				"TOTAL_TRILINEAR_REQUESTS",
-+				VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS,
-+				&perf_reg_read
-+			},
-+			{
-+				"TOTAL_DISCARDED_TEXTURE_REQUESTS",
-+				VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS,
-+				&perf_reg_read
-+			},
-+			{
-+				"TOTAL_TEXTURE_REQUESTS",
-+				VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS,
-+				&perf_reg_read
-+			},
-+			{
-+				"MEM_READ_COUNT",
-+				VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT,
-+				&perf_reg_read
-+			},
-+			{
-+				"MEM_READ_IN_8B_COUNT",
-+				VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT,
-+				&perf_reg_read
-+			},
-+			{
-+				"CACHE_MISS_COUNT",
-+				VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT,
-+				&perf_reg_read
-+			},
-+			{
-+				"CACHE_HIT_TEXEL_COUNT",
-+				VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT,
-+				&perf_reg_read
-+			},
-+			{
-+				"CACHE_MISS_TEXEL_COUNT",
-+				VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT,
-+				&perf_reg_read
-+			}
-+		}
-+	},
-+	{
-+		.name = "MC",
-+		.profile_read = VIVS_MC_PROFILE_MC_READ,
-+		.profile_config = VIVS_MC_PROFILE_CONFIG2,
-+		.nr_signals = 3,
-+		.signal = (const struct etnaviv_pm_signal[]) {
-+			{
-+				"TOTAL_READ_REQ_8B_FROM_PIPELINE",
-+				VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE,
-+				&perf_reg_read
-+			},
-+			{
-+				"TOTAL_READ_REQ_8B_FROM_IP",
-+				VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP,
-+				&perf_reg_read
-+			},
-+			{
-+				"TOTAL_WRITE_REQ_8B_FROM_PIPELINE",
-+				VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE,
-+				&perf_reg_read
-+			}
-+		}
-+	}
-+};
-+
-+static const struct etnaviv_pm_domain doms_2d[] = {
-+	{
-+		.name = "PE",
-+		.profile_read = VIVS_MC_PROFILE_PE_READ,
-+		.profile_config = VIVS_MC_PROFILE_CONFIG0,
-+		.nr_signals = 1,
-+		.signal = (const struct etnaviv_pm_signal[]) {
-+			{
-+				"PIXELS_RENDERED_2D",
-+				VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D,
-+				&pipe_reg_read
-+			}
-+		}
-+	}
-+};
-+
-+static const struct etnaviv_pm_domain doms_vg[] = {
-+};
-+
-+static const struct etnaviv_pm_domain_meta doms_meta[] = {
-+	{
-+		.nr_domains = ARRAY_SIZE(doms_3d),
-+		.domains = &doms_3d[0]
-+	},
-+	{
-+		.nr_domains = ARRAY_SIZE(doms_2d),
-+		.domains = &doms_2d[0]
-+	},
-+	{
-+		.nr_domains = ARRAY_SIZE(doms_vg),
-+		.domains = &doms_vg[0]
-+	}
-+};
-+
-+int etnaviv_pm_query_dom(struct etnaviv_gpu *gpu,
-+	struct drm_etnaviv_pm_domain *domain)
-+{
-+	const struct etnaviv_pm_domain_meta *meta = &doms_meta[domain->pipe];
-+	const struct etnaviv_pm_domain *dom;
-+
-+	if (domain->iter >= meta->nr_domains)
-+		return -EINVAL;
-+
-+	dom = meta->domains + domain->iter;
-+
-+	domain->id = domain->iter;
-+	domain->nr_signals = dom->nr_signals;
-+	strncpy(domain->name, dom->name, sizeof(domain->name));
-+
-+	domain->iter++;
-+	if (domain->iter == meta->nr_domains)
-+		domain->iter = 0xff;
-+
-+	return 0;
-+}
-+
-+int etnaviv_pm_query_sig(struct etnaviv_gpu *gpu,
-+	struct drm_etnaviv_pm_signal *signal)
-+{
-+	const struct etnaviv_pm_domain_meta *meta = &doms_meta[signal->pipe];
-+	const struct etnaviv_pm_domain *dom;
-+	const struct etnaviv_pm_signal *sig;
-+
-+	if (signal->domain >= meta->nr_domains)
-+		return -EINVAL;
-+
-+	dom = meta->domains + signal->domain;
-+
-+	if (signal->iter > dom->nr_signals)
-+		return -EINVAL;
-+
-+	sig = &dom->signal[signal->iter];
-+
-+	signal->id = signal->iter;
-+	strncpy(signal->name, sig->name, sizeof(signal->name));
-+
-+	signal->iter++;
-+	if (signal->iter == dom->nr_signals)
-+		signal->iter = 0xffff;
-+
-+	return 0;
-+}
-+
-+int etnaviv_pm_req_validate(const struct drm_etnaviv_gem_submit_pmr *r,
-+	u32 exec_state)
-+{
-+	const struct etnaviv_pm_domain_meta *meta = &doms_meta[exec_state];
-+	const struct etnaviv_pm_domain *dom;
-+
-+	if (r->domain >= meta->nr_domains)
-+		return -EINVAL;
-+
-+	dom = meta->domains + r->domain;
-+
-+	if (r->signal > dom->nr_signals)
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+
-+void etnaviv_perfmon_process(struct etnaviv_gpu *gpu,
-+	const struct etnaviv_perfmon_request *pmr)
-+{
-+	const struct etnaviv_pm_domain_meta *meta = &doms_meta[gpu->exec_state];
-+	const struct etnaviv_pm_domain *dom;
-+	const struct etnaviv_pm_signal *sig;
-+	u32 *bo = pmr->bo_vma;
-+	u32 val;
-+
-+	dom = meta->domains + pmr->domain;
-+	sig = &dom->signal[pmr->signal];
-+	val = sig->sample(gpu, dom, sig);
-+
-+	*(bo + pmr->offset) = val;
-+}
---- linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_perfmon.h.0130~	2017-12-14 06:39:58.495903623 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/etnaviv_perfmon.h	2017-12-14 06:39:58.495903623 +0100
-@@ -0,0 +1,49 @@
-+/*
-+ * Copyright (C) 2017 Etnaviv Project
-+ * Copyright (C) 2017 Zodiac Inflight Innovations
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License along with
-+ * this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#ifndef __ETNAVIV_PERFMON_H__
-+#define __ETNAVIV_PERFMON_H__
-+
-+struct etnaviv_gpu;
-+struct drm_etnaviv_pm_domain;
-+struct drm_etnaviv_pm_signal;
-+
-+struct etnaviv_perfmon_request
-+{
-+	u32 flags;
-+	u8 domain;
-+	u8 signal;
-+	u32 sequence;
-+
-+	/* bo to store a value */
-+	u32 *bo_vma;
-+	u32 offset;
-+};
-+
-+int etnaviv_pm_query_dom(struct etnaviv_gpu *gpu,
-+	struct drm_etnaviv_pm_domain *domain);
-+
-+int etnaviv_pm_query_sig(struct etnaviv_gpu *gpu,
-+	struct drm_etnaviv_pm_signal *signal);
-+
-+int etnaviv_pm_req_validate(const struct drm_etnaviv_gem_submit_pmr *r,
-+	u32 exec_state);
-+
-+void etnaviv_perfmon_process(struct etnaviv_gpu *gpu,
-+	const struct etnaviv_perfmon_request *pmr);
-+
-+#endif /* __ETNAVIV_PERFMON_H__ */
---- linux-4.14/drivers/gpu/drm/etnaviv/Kconfig.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/Kconfig	2017-12-14 06:39:58.495903623 +0100
-@@ -7,8 +7,6 @@ config DRM_ETNAVIV
- 	select SHMEM
- 	select SYNC_FILE
- 	select TMPFS
--	select IOMMU_API
--	select IOMMU_SUPPORT
- 	select WANT_DEV_COREDUMP
- 	select CMA if HAVE_DMA_CONTIGUOUS
- 	select DMA_CMA if HAVE_DMA_CONTIGUOUS
---- linux-4.14/drivers/gpu/drm/etnaviv/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/etnaviv/Makefile	2017-12-14 06:39:58.495903623 +0100
-@@ -11,6 +11,7 @@ etnaviv-y := \
- 	etnaviv_gpu.o \
- 	etnaviv_iommu_v2.o \
- 	etnaviv_iommu.o \
--	etnaviv_mmu.o
-+	etnaviv_mmu.o \
-+	etnaviv_perfmon.o
- 
- obj-$(CONFIG_DRM_ETNAVIV)	+= etnaviv.o
---- linux-4.14/drivers/gpu/drm/exynos/exynos_drm_mic.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/exynos/exynos_drm_mic.c	2017-12-14 06:39:58.495903623 +0100
-@@ -420,11 +420,7 @@ static int exynos_mic_probe(struct platf
- 	mic->bridge.funcs = &mic_bridge_funcs;
- 	mic->bridge.of_node = dev->of_node;
- 
--	ret = drm_bridge_add(&mic->bridge);
--	if (ret) {
--		DRM_ERROR("mic: Failed to add MIC to the global bridge list\n");
--		return ret;
--	}
-+	drm_bridge_add(&mic->bridge);
- 
- 	pm_runtime_enable(dev);
- 
---- linux-4.14/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c	2017-12-14 06:39:58.495903623 +0100
-@@ -13,6 +13,7 @@
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_fb_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- 
- #include "fsl_dcu_drm_crtc.h"
- #include "fsl_dcu_drm_drv.h"
-@@ -20,7 +21,7 @@
- static const struct drm_mode_config_funcs fsl_dcu_drm_mode_config_funcs = {
- 	.atomic_check = drm_atomic_helper_check,
- 	.atomic_commit = drm_atomic_helper_commit,
--	.fb_create = drm_fb_cma_create,
-+	.fb_create = drm_gem_fb_create,
- };
- 
- int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev)
---- linux-4.14/drivers/gpu/drm/gma500/cdv_intel_dp.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/gma500/cdv_intel_dp.c	2017-12-14 06:39:58.496903624 +0100
-@@ -1901,10 +1901,8 @@ cdv_intel_dp_destroy(struct drm_connecto
- 
- 	if (is_edp(gma_encoder)) {
- 	/*	cdv_intel_panel_destroy_backlight(connector->dev); */
--		if (intel_dp->panel_fixed_mode) {
--			kfree(intel_dp->panel_fixed_mode);
--			intel_dp->panel_fixed_mode = NULL;
--		}
-+		kfree(intel_dp->panel_fixed_mode);
-+		intel_dp->panel_fixed_mode = NULL;
- 	}
- 	i2c_del_adapter(&intel_dp->adapter);
- 	drm_connector_unregister(connector);
---- linux-4.14/drivers/gpu/drm/gma500/mdfld_intel_display.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/gma500/mdfld_intel_display.c	2017-12-14 06:39:58.496903624 +0100
-@@ -99,7 +99,7 @@ void mdfldWaitForPipeEnable(struct drm_d
- 	/* Wait for for the pipe enable to take effect. */
- 	for (count = 0; count < COUNT_MAX; count++) {
- 		temp = REG_READ(map->conf);
--		if ((temp & PIPEACONF_PIPE_STATE) == 1)
-+		if (temp & PIPEACONF_PIPE_STATE)
- 			break;
- 	}
- }
---- linux-4.14/drivers/gpu/drm/gma500/mid_bios.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/gma500/mid_bios.c	2017-12-14 06:39:58.496903624 +0100
-@@ -237,7 +237,7 @@ static int mid_get_vbt_data_r10(struct d
- 
- 	gct = kmalloc(sizeof(*gct) * vbt.panel_count, GFP_KERNEL);
- 	if (!gct)
--		return -1;
-+		return -ENOMEM;
- 
- 	gct_virtual = ioremap(addr + sizeof(vbt),
- 			sizeof(*gct) * vbt.panel_count);
---- linux-4.14/drivers/gpu/drm/gma500/psb_intel_sdvo.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/gma500/psb_intel_sdvo.c	2017-12-14 06:39:58.496903624 +0100
-@@ -37,6 +37,7 @@
- #include "psb_drv.h"
- #include "psb_intel_sdvo_regs.h"
- #include "psb_intel_reg.h"
-+#include <linux/kernel.h>
- 
- #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
- #define SDVO_RGB_MASK  (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
-@@ -62,8 +63,6 @@ static const char *tv_format_names[] = {
- 	"SECAM_60"
- };
- 
--#define TV_FORMAT_NUM  (sizeof(tv_format_names) / sizeof(*tv_format_names))
--
- struct psb_intel_sdvo {
- 	struct gma_encoder base;
- 
-@@ -148,7 +147,7 @@ struct psb_intel_sdvo_connector {
- 	int force_audio;
- 
- 	/* This contains all current supported TV format */
--	u8 tv_format_supported[TV_FORMAT_NUM];
-+	u8 tv_format_supported[ARRAY_SIZE(tv_format_names)];
- 	int   format_supported_num;
- 	struct drm_property *tv_format;
- 
-@@ -1709,7 +1708,7 @@ psb_intel_sdvo_set_property(struct drm_c
- 	}
- 
- 	if (property == psb_intel_sdvo_connector->tv_format) {
--		if (val >= TV_FORMAT_NUM)
-+		if (val >= ARRAY_SIZE(tv_format_names))
- 			return -EINVAL;
- 
- 		if (psb_intel_sdvo->tv_format_index ==
-@@ -2269,7 +2268,7 @@ static bool psb_intel_sdvo_tv_create_pro
- 		return false;
- 
- 	psb_intel_sdvo_connector->format_supported_num = 0;
--	for (i = 0 ; i < TV_FORMAT_NUM; i++)
-+	for (i = 0 ; i < ARRAY_SIZE(tv_format_names); i++)
- 		if (format_map & (1 << i))
- 			psb_intel_sdvo_connector->tv_format_supported[psb_intel_sdvo_connector->format_supported_num++] = i;
- 
---- linux-4.14/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c	2017-12-14 06:39:58.496903624 +0100
-@@ -36,7 +36,7 @@ static int hibmc_connector_mode_valid(st
- static struct drm_encoder *
- hibmc_connector_best_encoder(struct drm_connector *connector)
- {
--	return drm_encoder_find(connector->dev, connector->encoder_ids[0]);
-+	return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
- }
- 
- static const struct drm_connector_helper_funcs
---- linux-4.14/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c	2017-12-14 06:39:58.496903624 +0100
-@@ -22,6 +22,7 @@
- #include <drm/drmP.h>
- #include <drm/drm_gem_cma_helper.h>
- #include <drm/drm_fb_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_of.h>
-@@ -56,7 +57,7 @@ static void kirin_fbdev_output_poll_chan
- }
- 
- static const struct drm_mode_config_funcs kirin_drm_mode_config_funcs = {
--	.fb_create = drm_fb_cma_create,
-+	.fb_create = drm_gem_fb_create,
- 	.output_poll_changed = kirin_fbdev_output_poll_changed,
- 	.atomic_check = drm_atomic_helper_check,
- 	.atomic_commit = drm_atomic_helper_commit,
-@@ -236,8 +237,8 @@ static int kirin_drm_platform_probe(stru
- 	}
- 
- 	remote = of_graph_get_remote_node(np, 0, 0);
--	if (IS_ERR(remote))
--		return PTR_ERR(remote);
-+	if (!remote)
-+		return -ENODEV;
- 
- 	drm_of_component_match_add(dev, &match, compare_of, remote);
- 	of_node_put(remote);
---- linux-4.14/drivers/gpu/drm/i2c/ch7006_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i2c/ch7006_drv.c	2017-12-14 06:39:58.496903624 +0100
-@@ -485,7 +485,7 @@ static int ch7006_encoder_init(struct i2
- 	return 0;
- }
- 
--static struct i2c_device_id ch7006_ids[] = {
-+static const struct i2c_device_id ch7006_ids[] = {
- 	{ "ch7006", 0 },
- 	{ }
- };
---- linux-4.14/drivers/gpu/drm/i2c/sil164_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i2c/sil164_drv.c	2017-12-14 06:39:58.496903624 +0100
-@@ -415,7 +415,7 @@ sil164_encoder_init(struct i2c_client *c
- 	return 0;
- }
- 
--static struct i2c_device_id sil164_ids[] = {
-+static const struct i2c_device_id sil164_ids[] = {
- 	{ "sil164", 0 },
- 	{ }
- };
---- linux-4.14/drivers/gpu/drm/i2c/tda998x_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i2c/tda998x_drv.c	2017-12-14 06:39:58.496903624 +0100
-@@ -1746,7 +1746,7 @@ static const struct of_device_id tda998x
- MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
- #endif
- 
--static struct i2c_device_id tda998x_ids[] = {
-+static const struct i2c_device_id tda998x_ids[] = {
- 	{ "tda998x", 0 },
- 	{ }
- };
---- linux-4.14/drivers/gpu/drm/i915/gvt/aperture_gm.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/gvt/aperture_gm.c	2017-12-14 06:39:58.497903625 +0100
-@@ -173,8 +173,8 @@ static void free_vgpu_fence(struct intel
- 	_clear_vgpu_fence(vgpu);
- 	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
- 		reg = vgpu->fence.regs[i];
--		list_add_tail(&reg->link,
--			      &dev_priv->mm.fence_list);
-+		i915_unreserve_fence(reg);
-+		vgpu->fence.regs[i] = NULL;
- 	}
- 	mutex_unlock(&dev_priv->drm.struct_mutex);
- 
-@@ -187,24 +187,19 @@ static int alloc_vgpu_fence(struct intel
- 	struct drm_i915_private *dev_priv = gvt->dev_priv;
- 	struct drm_i915_fence_reg *reg;
- 	int i;
--	struct list_head *pos, *q;
- 
- 	intel_runtime_pm_get(dev_priv);
- 
- 	/* Request fences from host */
- 	mutex_lock(&dev_priv->drm.struct_mutex);
--	i = 0;
--	list_for_each_safe(pos, q, &dev_priv->mm.fence_list) {
--		reg = list_entry(pos, struct drm_i915_fence_reg, link);
--		if (reg->pin_count || reg->vma)
--			continue;
--		list_del(pos);
-+
-+	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
-+		reg = i915_reserve_fence(dev_priv);
-+		if (IS_ERR(reg))
-+			goto out_free_fence;
-+
- 		vgpu->fence.regs[i] = reg;
--		if (++i == vgpu_fence_sz(vgpu))
--			break;
- 	}
--	if (i != vgpu_fence_sz(vgpu))
--		goto out_free_fence;
- 
- 	_clear_vgpu_fence(vgpu);
- 
-@@ -212,13 +207,14 @@ static int alloc_vgpu_fence(struct intel
- 	intel_runtime_pm_put(dev_priv);
- 	return 0;
- out_free_fence:
-+	gvt_vgpu_err("Failed to alloc fences\n");
- 	/* Return fences to host, if fail */
- 	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
- 		reg = vgpu->fence.regs[i];
- 		if (!reg)
- 			continue;
--		list_add_tail(&reg->link,
--			      &dev_priv->mm.fence_list);
-+		i915_unreserve_fence(reg);
-+		vgpu->fence.regs[i] = NULL;
- 	}
- 	mutex_unlock(&dev_priv->drm.struct_mutex);
- 	intel_runtime_pm_put(dev_priv);
---- linux-4.14/drivers/gpu/drm/i915/gvt/cfg_space.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/gvt/cfg_space.c	2017-12-14 06:39:58.497903625 +0100
-@@ -101,7 +101,7 @@ int intel_vgpu_emulate_cfg_read(struct i
- 	if (WARN_ON(bytes > 4))
- 		return -EINVAL;
- 
--	if (WARN_ON(offset + bytes > INTEL_GVT_MAX_CFG_SPACE_SZ))
-+	if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
- 		return -EINVAL;
- 
- 	memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
-@@ -110,13 +110,25 @@ int intel_vgpu_emulate_cfg_read(struct i
- 
- static int map_aperture(struct intel_vgpu *vgpu, bool map)
- {
--	u64 first_gfn, first_mfn;
-+	phys_addr_t aperture_pa = vgpu_aperture_pa_base(vgpu);
-+	unsigned long aperture_sz = vgpu_aperture_sz(vgpu);
-+	u64 first_gfn;
- 	u64 val;
- 	int ret;
- 
- 	if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)
- 		return 0;
- 
-+	if (map) {
-+		vgpu->gm.aperture_va = memremap(aperture_pa, aperture_sz,
-+						MEMREMAP_WC);
-+		if (!vgpu->gm.aperture_va)
-+			return -ENOMEM;
-+	} else {
-+		memunmap(vgpu->gm.aperture_va);
-+		vgpu->gm.aperture_va = NULL;
-+	}
-+
- 	val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2];
- 	if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
- 		val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
-@@ -124,14 +136,16 @@ static int map_aperture(struct intel_vgp
- 		val = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
- 
- 	first_gfn = (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT;
--	first_mfn = vgpu_aperture_pa_base(vgpu) >> PAGE_SHIFT;
- 
- 	ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn,
--						  first_mfn,
--						  vgpu_aperture_sz(vgpu) >>
--						  PAGE_SHIFT, map);
--	if (ret)
-+						  aperture_pa >> PAGE_SHIFT,
-+						  aperture_sz >> PAGE_SHIFT,
-+						  map);
-+	if (ret) {
-+		memunmap(vgpu->gm.aperture_va);
-+		vgpu->gm.aperture_va = NULL;
- 		return ret;
-+	}
- 
- 	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;
- 	return 0;
-@@ -275,7 +289,7 @@ int intel_vgpu_emulate_cfg_write(struct
- 	if (WARN_ON(bytes > 4))
- 		return -EINVAL;
- 
--	if (WARN_ON(offset + bytes > INTEL_GVT_MAX_CFG_SPACE_SZ))
-+	if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
- 		return -EINVAL;
- 
- 	/* First check if it's PCI_COMMAND */
---- linux-4.14/drivers/gpu/drm/i915/gvt/cmd_parser.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/gvt/cmd_parser.c	2017-12-14 06:39:58.497903625 +0100
-@@ -1576,11 +1576,11 @@ static int batch_buffer_needs_scan(struc
- 	return 1;
- }
- 
--static uint32_t find_bb_size(struct parser_exec_state *s)
-+static int find_bb_size(struct parser_exec_state *s)
- {
- 	unsigned long gma = 0;
- 	struct cmd_info *info;
--	uint32_t bb_size = 0;
-+	int bb_size = 0;
- 	uint32_t cmd_len = 0;
- 	bool met_bb_end = false;
- 	struct intel_vgpu *vgpu = s->vgpu;
-@@ -1637,6 +1637,8 @@ static int perform_bb_shadow(struct pars
- 
- 	/* get the size of the batch buffer */
- 	bb_size = find_bb_size(s);
-+	if (bb_size < 0)
-+		return -EINVAL;
- 
- 	/* allocate shadow batch buffer */
- 	entry_obj = kmalloc(sizeof(*entry_obj), GFP_KERNEL);
-@@ -2603,7 +2605,8 @@ static int shadow_workload_ring_buffer(s
- {
- 	struct intel_vgpu *vgpu = workload->vgpu;
- 	unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
--	u32 *cs;
-+	void *shadow_ring_buffer_va;
-+	int ring_id = workload->ring_id;
- 	int ret;
- 
- 	guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
-@@ -2616,34 +2619,42 @@ static int shadow_workload_ring_buffer(s
- 	gma_tail = workload->rb_start + workload->rb_tail;
- 	gma_top = workload->rb_start + guest_rb_size;
- 
--	/* allocate shadow ring buffer */
--	cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
--	if (IS_ERR(cs))
--		return PTR_ERR(cs);
-+	if (workload->rb_len > vgpu->reserve_ring_buffer_size[ring_id]) {
-+		void *va = vgpu->reserve_ring_buffer_va[ring_id];
-+		/* realloc the new ring buffer if needed */
-+		vgpu->reserve_ring_buffer_va[ring_id] =
-+			krealloc(va, workload->rb_len, GFP_KERNEL);
-+		if (!vgpu->reserve_ring_buffer_va[ring_id]) {
-+			gvt_vgpu_err("fail to alloc reserve ring buffer\n");
-+			return -ENOMEM;
-+		}
-+		vgpu->reserve_ring_buffer_size[ring_id] = workload->rb_len;
-+	}
-+
-+	shadow_ring_buffer_va = vgpu->reserve_ring_buffer_va[ring_id];
- 
- 	/* get shadow ring buffer va */
--	workload->shadow_ring_buffer_va = cs;
-+	workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
- 
- 	/* head > tail --> copy head <-> top */
- 	if (gma_head > gma_tail) {
- 		ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
--				      gma_head, gma_top, cs);
-+				      gma_head, gma_top, shadow_ring_buffer_va);
- 		if (ret < 0) {
- 			gvt_vgpu_err("fail to copy guest ring buffer\n");
- 			return ret;
- 		}
--		cs += ret / sizeof(u32);
-+		shadow_ring_buffer_va += ret;
- 		gma_head = workload->rb_start;
- 	}
- 
- 	/* copy head or start <-> tail */
--	ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail, cs);
-+	ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
-+				shadow_ring_buffer_va);
- 	if (ret < 0) {
- 		gvt_vgpu_err("fail to copy guest ring buffer\n");
- 		return ret;
- 	}
--	cs += ret / sizeof(u32);
--	intel_ring_advance(workload->req, cs);
- 	return 0;
- }
- 
---- linux-4.14/drivers/gpu/drm/i915/gvt/execlist.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/gvt/execlist.c	2017-12-14 06:39:58.497903625 +0100
-@@ -368,7 +368,7 @@ static void free_workload(struct intel_v
- #define get_desc_from_elsp_dwords(ed, i) \
- 	((struct execlist_ctx_descriptor_format *)&((ed)->data[i * 2]))
- 
--static void prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
-+static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
- {
- 	const int gmadr_bytes = workload->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
- 	struct intel_shadow_bb_entry *entry_obj;
-@@ -379,7 +379,7 @@ static void prepare_shadow_batch_buffer(
- 
- 		vma = i915_gem_object_ggtt_pin(entry_obj->obj, NULL, 0, 4, 0);
- 		if (IS_ERR(vma)) {
--			return;
-+			return PTR_ERR(vma);
- 		}
- 
- 		/* FIXME: we are not tracking our pinned VMA leaving it
-@@ -392,6 +392,7 @@ static void prepare_shadow_batch_buffer(
- 		if (gmadr_bytes == 8)
- 			entry_obj->bb_start_cmd_va[2] = 0;
- 	}
-+	return 0;
- }
- 
- static int update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
-@@ -420,7 +421,7 @@ static int update_wa_ctx_2_shadow_ctx(st
- 	return 0;
- }
- 
--static void prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
-+static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
- {
- 	struct i915_vma *vma;
- 	unsigned char *per_ctx_va =
-@@ -428,12 +429,12 @@ static void prepare_shadow_wa_ctx(struct
- 		wa_ctx->indirect_ctx.size;
- 
- 	if (wa_ctx->indirect_ctx.size == 0)
--		return;
-+		return 0;
- 
- 	vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
- 				       0, CACHELINE_BYTES, 0);
- 	if (IS_ERR(vma)) {
--		return;
-+		return PTR_ERR(vma);
- 	}
- 
- 	/* FIXME: we are not tracking our pinned VMA leaving it
-@@ -447,26 +448,7 @@ static void prepare_shadow_wa_ctx(struct
- 	memset(per_ctx_va, 0, CACHELINE_BYTES);
- 
- 	update_wa_ctx_2_shadow_ctx(wa_ctx);
--}
--
--static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
--{
--	struct intel_vgpu *vgpu = workload->vgpu;
--	struct execlist_ctx_descriptor_format ctx[2];
--	int ring_id = workload->ring_id;
--
--	intel_vgpu_pin_mm(workload->shadow_mm);
--	intel_vgpu_sync_oos_pages(workload->vgpu);
--	intel_vgpu_flush_post_shadow(workload->vgpu);
--	prepare_shadow_batch_buffer(workload);
--	prepare_shadow_wa_ctx(&workload->wa_ctx);
--	if (!workload->emulate_schedule_in)
--		return 0;
--
--	ctx[0] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 1);
--	ctx[1] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 0);
--
--	return emulate_execlist_schedule_in(&vgpu->execlist[ring_id], ctx);
-+	return 0;
- }
- 
- static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
-@@ -489,13 +471,62 @@ static void release_shadow_batch_buffer(
- 	}
- }
- 
--static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
-+static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
- {
--	if (!wa_ctx->indirect_ctx.obj)
--		return;
-+	struct intel_vgpu *vgpu = workload->vgpu;
-+	struct execlist_ctx_descriptor_format ctx[2];
-+	int ring_id = workload->ring_id;
-+	int ret;
-+
-+	ret = intel_vgpu_pin_mm(workload->shadow_mm);
-+	if (ret) {
-+		gvt_vgpu_err("fail to vgpu pin mm\n");
-+		goto out;
-+	}
- 
--	i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
--	i915_gem_object_put(wa_ctx->indirect_ctx.obj);
-+	ret = intel_vgpu_sync_oos_pages(workload->vgpu);
-+	if (ret) {
-+		gvt_vgpu_err("fail to vgpu sync oos pages\n");
-+		goto err_unpin_mm;
-+	}
-+
-+	ret = intel_vgpu_flush_post_shadow(workload->vgpu);
-+	if (ret) {
-+		gvt_vgpu_err("fail to flush post shadow\n");
-+		goto err_unpin_mm;
-+	}
-+
-+	ret = prepare_shadow_batch_buffer(workload);
-+	if (ret) {
-+		gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
-+		goto err_unpin_mm;
-+	}
-+
-+	ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
-+	if (ret) {
-+		gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
-+		goto err_shadow_batch;
-+	}
-+
-+	if (!workload->emulate_schedule_in)
-+		return 0;
-+
-+	ctx[0] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 1);
-+	ctx[1] = *get_desc_from_elsp_dwords(&workload->elsp_dwords, 0);
-+
-+	ret = emulate_execlist_schedule_in(&vgpu->execlist[ring_id], ctx);
-+	if (!ret)
-+		goto out;
-+	else
-+		gvt_vgpu_err("fail to emulate execlist schedule in\n");
-+
-+	release_shadow_wa_ctx(&workload->wa_ctx);
-+err_shadow_batch:
-+	release_shadow_batch_buffer(workload);
-+err_unpin_mm:
-+	intel_vgpu_unpin_mm(workload->shadow_mm);
-+out:
-+	return ret;
- }
- 
- static int complete_execlist_workload(struct intel_vgpu_workload *workload)
-@@ -511,8 +542,10 @@ static int complete_execlist_workload(st
- 	gvt_dbg_el("complete workload %p status %d\n", workload,
- 			workload->status);
- 
--	release_shadow_batch_buffer(workload);
--	release_shadow_wa_ctx(&workload->wa_ctx);
-+	if (!workload->status) {
-+		release_shadow_batch_buffer(workload);
-+		release_shadow_wa_ctx(&workload->wa_ctx);
-+	}
- 
- 	if (workload->status || (vgpu->resetting_eng & ENGINE_MASK(ring_id))) {
- 		/* if workload->status is not successful means HW GPU
-@@ -819,10 +852,21 @@ static void clean_workloads(struct intel
- 
- void intel_vgpu_clean_execlist(struct intel_vgpu *vgpu)
- {
-+	enum intel_engine_id i;
-+	struct intel_engine_cs *engine;
-+
- 	clean_workloads(vgpu, ALL_ENGINES);
- 	kmem_cache_destroy(vgpu->workloads);
-+
-+	for_each_engine(engine, vgpu->gvt->dev_priv, i) {
-+		kfree(vgpu->reserve_ring_buffer_va[i]);
-+		vgpu->reserve_ring_buffer_va[i] = NULL;
-+		vgpu->reserve_ring_buffer_size[i] = 0;
-+	}
-+
- }
- 
-+#define RESERVE_RING_BUFFER_SIZE		((1 * PAGE_SIZE)/8)
- int intel_vgpu_init_execlist(struct intel_vgpu *vgpu)
- {
- 	enum intel_engine_id i;
-@@ -842,7 +886,26 @@ int intel_vgpu_init_execlist(struct inte
- 	if (!vgpu->workloads)
- 		return -ENOMEM;
- 
-+	/* each ring has a shadow ring buffer until vgpu destroyed */
-+	for_each_engine(engine, vgpu->gvt->dev_priv, i) {
-+		vgpu->reserve_ring_buffer_va[i] =
-+			kmalloc(RESERVE_RING_BUFFER_SIZE, GFP_KERNEL);
-+		if (!vgpu->reserve_ring_buffer_va[i]) {
-+			gvt_vgpu_err("fail to alloc reserve ring buffer\n");
-+			goto out;
-+		}
-+		vgpu->reserve_ring_buffer_size[i] = RESERVE_RING_BUFFER_SIZE;
-+	}
- 	return 0;
-+out:
-+	for_each_engine(engine, vgpu->gvt->dev_priv, i) {
-+		if (vgpu->reserve_ring_buffer_size[i]) {
-+			kfree(vgpu->reserve_ring_buffer_va[i]);
-+			vgpu->reserve_ring_buffer_va[i] = NULL;
-+			vgpu->reserve_ring_buffer_size[i] = 0;
-+		}
-+	}
-+	return -ENOMEM;
- }
- 
- void intel_vgpu_reset_execlist(struct intel_vgpu *vgpu,
---- linux-4.14/drivers/gpu/drm/i915/gvt/gtt.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/gvt/gtt.c	2017-12-14 06:39:58.497903625 +0100
-@@ -1647,14 +1647,13 @@ int intel_vgpu_pin_mm(struct intel_vgpu_
- 	if (WARN_ON(mm->type != INTEL_GVT_MM_PPGTT))
- 		return 0;
- 
--	atomic_inc(&mm->pincount);
--
- 	if (!mm->shadowed) {
- 		ret = shadow_mm(mm);
- 		if (ret)
- 			return ret;
- 	}
- 
-+	atomic_inc(&mm->pincount);
- 	list_del_init(&mm->lru_list);
- 	list_add_tail(&mm->lru_list, &mm->vgpu->gvt->gtt.mm_lru_list_head);
- 	return 0;
-@@ -1972,7 +1971,7 @@ static int alloc_scratch_pages(struct in
- 		 */
- 		se.val64 |= _PAGE_PRESENT | _PAGE_RW;
- 		if (type == GTT_TYPE_PPGTT_PDE_PT)
--			se.val64 |= PPAT_CACHED_INDEX;
-+			se.val64 |= PPAT_CACHED;
- 
- 		for (i = 0; i < page_entry_num; i++)
- 			ops->set_entry(scratch_pt, &se, i, false, 0, vgpu);
---- linux-4.14/drivers/gpu/drm/i915/gvt/gvt.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/gvt/gvt.c	2017-12-14 06:39:58.497903625 +0100
-@@ -111,7 +111,7 @@ static void init_device_info(struct inte
- 	if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
- 		|| IS_KABYLAKE(gvt->dev_priv)) {
- 		info->max_support_vgpus = 8;
--		info->cfg_space_size = 256;
-+		info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE;
- 		info->mmio_size = 2 * 1024 * 1024;
- 		info->mmio_bar = 0;
- 		info->gtt_start_offset = 8 * 1024 * 1024;
---- linux-4.14/drivers/gpu/drm/i915/gvt/gvt.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/gvt/gvt.h	2017-12-14 06:39:58.497903625 +0100
-@@ -80,6 +80,7 @@ struct intel_gvt_device_info {
- struct intel_vgpu_gm {
- 	u64 aperture_sz;
- 	u64 hidden_sz;
-+	void *aperture_va;
- 	struct drm_mm_node low_gm_node;
- 	struct drm_mm_node high_gm_node;
- };
-@@ -99,7 +100,6 @@ struct intel_vgpu_mmio {
- 	bool disable_warn_untrack;
- };
- 
--#define INTEL_GVT_MAX_CFG_SPACE_SZ 256
- #define INTEL_GVT_MAX_BAR_NUM 4
- 
- struct intel_vgpu_pci_bar {
-@@ -108,7 +108,7 @@ struct intel_vgpu_pci_bar {
- };
- 
- struct intel_vgpu_cfg_space {
--	unsigned char virtual_cfg_space[INTEL_GVT_MAX_CFG_SPACE_SZ];
-+	unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE];
- 	struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
- };
- 
-@@ -165,6 +165,9 @@ struct intel_vgpu {
- 	struct list_head workload_q_head[I915_NUM_ENGINES];
- 	struct kmem_cache *workloads;
- 	atomic_t running_workload_num;
-+	/* 1/2K for each reserve ring buffer */
-+	void *reserve_ring_buffer_va[I915_NUM_ENGINES];
-+	int reserve_ring_buffer_size[I915_NUM_ENGINES];
- 	DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
- 	struct i915_gem_context *shadow_ctx;
- 	DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
-@@ -474,6 +477,13 @@ int intel_vgpu_emulate_cfg_read(struct i
- int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
- 		void *p_data, unsigned int bytes);
- 
-+static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)
-+{
-+	/* We are 64bit bar. */
-+	return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &
-+			PCI_BASE_ADDRESS_MEM_MASK;
-+}
-+
- void intel_gvt_clean_opregion(struct intel_gvt *gvt);
- int intel_gvt_init_opregion(struct intel_gvt *gvt);
- 
---- linux-4.14/drivers/gpu/drm/i915/gvt/kvmgt.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/gvt/kvmgt.c	2017-12-14 06:39:58.498903625 +0100
-@@ -609,21 +609,20 @@ static void intel_vgpu_release_work(stru
- 	__intel_vgpu_release(vgpu);
- }
- 
--static uint64_t intel_vgpu_get_bar0_addr(struct intel_vgpu *vgpu)
-+static uint64_t intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar)
- {
- 	u32 start_lo, start_hi;
- 	u32 mem_type;
--	int pos = PCI_BASE_ADDRESS_0;
- 
--	start_lo = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + pos)) &
-+	start_lo = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &
- 			PCI_BASE_ADDRESS_MEM_MASK;
--	mem_type = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + pos)) &
-+	mem_type = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &
- 			PCI_BASE_ADDRESS_MEM_TYPE_MASK;
- 
- 	switch (mem_type) {
- 	case PCI_BASE_ADDRESS_MEM_TYPE_64:
- 		start_hi = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space
--						+ pos + 4));
-+						+ bar + 4));
- 		break;
- 	case PCI_BASE_ADDRESS_MEM_TYPE_32:
- 	case PCI_BASE_ADDRESS_MEM_TYPE_1M:
-@@ -637,6 +636,21 @@ static uint64_t intel_vgpu_get_bar0_addr
- 	return ((u64)start_hi << 32) | start_lo;
- }
- 
-+static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, uint64_t off,
-+			     void *buf, unsigned int count, bool is_write)
-+{
-+	uint64_t bar_start = intel_vgpu_get_bar_addr(vgpu, bar);
-+	int ret;
-+
-+	if (is_write)
-+		ret = intel_gvt_ops->emulate_mmio_write(vgpu,
-+					bar_start + off, buf, count);
-+	else
-+		ret = intel_gvt_ops->emulate_mmio_read(vgpu,
-+					bar_start + off, buf, count);
-+	return ret;
-+}
-+
- static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf,
- 			size_t count, loff_t *ppos, bool is_write)
- {
-@@ -661,20 +675,14 @@ static ssize_t intel_vgpu_rw(struct mdev
- 						buf, count);
- 		break;
- 	case VFIO_PCI_BAR0_REGION_INDEX:
--	case VFIO_PCI_BAR1_REGION_INDEX:
--		if (is_write) {
--			uint64_t bar0_start = intel_vgpu_get_bar0_addr(vgpu);
--
--			ret = intel_gvt_ops->emulate_mmio_write(vgpu,
--						bar0_start + pos, buf, count);
--		} else {
--			uint64_t bar0_start = intel_vgpu_get_bar0_addr(vgpu);
--
--			ret = intel_gvt_ops->emulate_mmio_read(vgpu,
--						bar0_start + pos, buf, count);
--		}
-+		ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_0, pos,
-+					buf, count, is_write);
- 		break;
- 	case VFIO_PCI_BAR2_REGION_INDEX:
-+		ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_2, pos,
-+					buf, count, is_write);
-+		break;
-+	case VFIO_PCI_BAR1_REGION_INDEX:
- 	case VFIO_PCI_BAR3_REGION_INDEX:
- 	case VFIO_PCI_BAR4_REGION_INDEX:
- 	case VFIO_PCI_BAR5_REGION_INDEX:
-@@ -970,7 +978,7 @@ static long intel_vgpu_ioctl(struct mdev
- 		switch (info.index) {
- 		case VFIO_PCI_CONFIG_REGION_INDEX:
- 			info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index);
--			info.size = INTEL_GVT_MAX_CFG_SPACE_SZ;
-+			info.size = vgpu->gvt->device_info.cfg_space_size;
- 			info.flags = VFIO_REGION_INFO_FLAG_READ |
- 				     VFIO_REGION_INFO_FLAG_WRITE;
- 			break;
---- linux-4.14/drivers/gpu/drm/i915/gvt/mmio.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/gvt/mmio.c	2017-12-14 06:39:58.498903625 +0100
-@@ -45,8 +45,7 @@
-  */
- int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
- {
--	u64 gttmmio_gpa = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0) &
--			  ~GENMASK(3, 0);
-+	u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
- 	return gpa - gttmmio_gpa;
- }
- 
-@@ -57,6 +56,38 @@ int intel_vgpu_gpa_to_mmio_offset(struct
- 	(reg >= gvt->device_info.gtt_start_offset \
- 	 && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
- 
-+static bool vgpu_gpa_is_aperture(struct intel_vgpu *vgpu, uint64_t gpa)
-+{
-+	u64 aperture_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_2);
-+	u64 aperture_sz = vgpu_aperture_sz(vgpu);
-+
-+	return gpa >= aperture_gpa && gpa < aperture_gpa + aperture_sz;
-+}
-+
-+static int vgpu_aperture_rw(struct intel_vgpu *vgpu, uint64_t gpa,
-+			    void *pdata, unsigned int size, bool is_read)
-+{
-+	u64 aperture_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_2);
-+	u64 offset = gpa - aperture_gpa;
-+
-+	if (!vgpu_gpa_is_aperture(vgpu, gpa + size - 1)) {
-+		gvt_vgpu_err("Aperture rw out of range, offset %llx, size %d\n",
-+			     offset, size);
-+		return -EINVAL;
-+	}
-+
-+	if (!vgpu->gm.aperture_va) {
-+		gvt_vgpu_err("BAR is not enabled\n");
-+		return -ENXIO;
-+	}
-+
-+	if (is_read)
-+		memcpy(pdata, vgpu->gm.aperture_va + offset, size);
-+	else
-+		memcpy(vgpu->gm.aperture_va + offset, pdata, size);
-+	return 0;
-+}
-+
- static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
- 		void *p_data, unsigned int bytes, bool read)
- {
-@@ -133,6 +164,12 @@ int intel_vgpu_emulate_mmio_read(struct
- 	}
- 	mutex_lock(&gvt->lock);
- 
-+	if (vgpu_gpa_is_aperture(vgpu, pa)) {
-+		ret = vgpu_aperture_rw(vgpu, pa, p_data, bytes, true);
-+		mutex_unlock(&gvt->lock);
-+		return ret;
-+	}
-+
- 	if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
- 		struct intel_vgpu_guest_page *gp;
- 
-@@ -224,6 +261,12 @@ int intel_vgpu_emulate_mmio_write(struct
- 
- 	mutex_lock(&gvt->lock);
- 
-+	if (vgpu_gpa_is_aperture(vgpu, pa)) {
-+		ret = vgpu_aperture_rw(vgpu, pa, p_data, bytes, false);
-+		mutex_unlock(&gvt->lock);
-+		return ret;
-+	}
-+
- 	if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
- 		struct intel_vgpu_guest_page *gp;
- 
---- linux-4.14/drivers/gpu/drm/i915/gvt/render.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/gvt/render.c	2017-12-14 06:39:58.498903625 +0100
-@@ -293,7 +293,7 @@ static void switch_mmio_to_vgpu(struct i
- 		 */
- 		if (mmio->in_context &&
- 				((ctx_ctrl & inhibit_mask) != inhibit_mask) &&
--				i915.enable_execlists)
-+				i915_modparams.enable_execlists)
- 			continue;
- 
- 		if (mmio->mask)
---- linux-4.14/drivers/gpu/drm/i915/gvt/scheduler.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/gvt/scheduler.c	2017-12-14 06:39:58.498903625 +0100
-@@ -87,7 +87,7 @@ static int populate_shadow_context(struc
- 			return -EINVAL;
- 		}
- 
--		page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i);
-+		page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
- 		dst = kmap(page);
- 		intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
- 				GTT_PAGE_SIZE);
-@@ -201,6 +201,43 @@ static void shadow_context_descriptor_up
- 	ce->lrc_desc = desc;
- }
- 
-+static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
-+{
-+	struct intel_vgpu *vgpu = workload->vgpu;
-+	void *shadow_ring_buffer_va;
-+	u32 *cs;
-+
-+	/* allocate shadow ring buffer */
-+	cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
-+	if (IS_ERR(cs)) {
-+		gvt_vgpu_err("fail to alloc size =%ld shadow  ring buffer\n",
-+			workload->rb_len);
-+		return PTR_ERR(cs);
-+	}
-+
-+	shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
-+
-+	/* get shadow ring buffer va */
-+	workload->shadow_ring_buffer_va = cs;
-+
-+	memcpy(cs, shadow_ring_buffer_va,
-+			workload->rb_len);
-+
-+	cs += workload->rb_len / sizeof(u32);
-+	intel_ring_advance(workload->req, cs);
-+
-+	return 0;
-+}
-+
-+void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
-+{
-+	if (!wa_ctx->indirect_ctx.obj)
-+		return;
-+
-+	i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
-+	i915_gem_object_put(wa_ctx->indirect_ctx.obj);
-+}
-+
- /**
-  * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
-  * shadow it as well, include ringbuffer,wa_ctx and ctx.
-@@ -214,8 +251,10 @@ int intel_gvt_scan_and_shadow_workload(s
- 	int ring_id = workload->ring_id;
- 	struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
- 	struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
-+	struct intel_engine_cs *engine = dev_priv->engine[ring_id];
- 	struct drm_i915_gem_request *rq;
- 	struct intel_vgpu *vgpu = workload->vgpu;
-+	struct intel_ring *ring;
- 	int ret;
- 
- 	lockdep_assert_held(&dev_priv->drm.struct_mutex);
-@@ -231,35 +270,56 @@ int intel_gvt_scan_and_shadow_workload(s
- 		shadow_context_descriptor_update(shadow_ctx,
- 					dev_priv->engine[ring_id]);
- 
--	rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx);
--	if (IS_ERR(rq)) {
--		gvt_vgpu_err("fail to allocate gem request\n");
--		ret = PTR_ERR(rq);
--		goto out;
--	}
--
--	gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id, rq);
--
--	workload->req = i915_gem_request_get(rq);
--
- 	ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
- 	if (ret)
--		goto out;
-+		goto err_scan;
- 
- 	if ((workload->ring_id == RCS) &&
- 	    (workload->wa_ctx.indirect_ctx.size != 0)) {
- 		ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
- 		if (ret)
--			goto out;
-+			goto err_scan;
-+	}
-+
-+	/* pin shadow context by gvt even the shadow context will be pinned
-+	 * when i915 alloc request. That is because gvt will update the guest
-+	 * context from shadow context when workload is completed, and at that
-+	 * moment, i915 may already unpined the shadow context to make the
-+	 * shadow_ctx pages invalid. So gvt need to pin itself. After update
-+	 * the guest context, gvt can unpin the shadow_ctx safely.
-+	 */
-+	ring = engine->context_pin(engine, shadow_ctx);
-+	if (IS_ERR(ring)) {
-+		ret = PTR_ERR(ring);
-+		gvt_vgpu_err("fail to pin shadow context\n");
-+		goto err_shadow;
- 	}
- 
- 	ret = populate_shadow_context(workload);
- 	if (ret)
--		goto out;
-+		goto err_unpin;
- 
-+	rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx);
-+	if (IS_ERR(rq)) {
-+		gvt_vgpu_err("fail to allocate gem request\n");
-+		ret = PTR_ERR(rq);
-+		goto err_unpin;
-+	}
-+
-+	gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id, rq);
-+
-+	workload->req = i915_gem_request_get(rq);
-+	ret = copy_workload_to_ring_buffer(workload);
-+	if (ret)
-+		goto err_unpin;
- 	workload->shadowed = true;
-+	return 0;
- 
--out:
-+err_unpin:
-+	engine->context_unpin(engine, shadow_ctx);
-+err_shadow:
-+	release_shadow_wa_ctx(&workload->wa_ctx);
-+err_scan:
- 	return ret;
- }
- 
-@@ -269,8 +329,6 @@ static int dispatch_workload(struct inte
- 	struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
- 	struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
- 	struct intel_engine_cs *engine = dev_priv->engine[ring_id];
--	struct intel_vgpu *vgpu = workload->vgpu;
--	struct intel_ring *ring;
- 	int ret = 0;
- 
- 	gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
-@@ -284,22 +342,10 @@ static int dispatch_workload(struct inte
- 
- 	if (workload->prepare) {
- 		ret = workload->prepare(workload);
--		if (ret)
-+		if (ret) {
-+			engine->context_unpin(engine, shadow_ctx);
- 			goto out;
--	}
--
--	/* pin shadow context by gvt even the shadow context will be pinned
--	 * when i915 alloc request. That is because gvt will update the guest
--	 * context from shadow context when workload is completed, and at that
--	 * moment, i915 may already unpined the shadow context to make the
--	 * shadow_ctx pages invalid. So gvt need to pin itself. After update
--	 * the guest context, gvt can unpin the shadow_ctx safely.
--	 */
--	ring = engine->context_pin(engine, shadow_ctx);
--	if (IS_ERR(ring)) {
--		ret = PTR_ERR(ring);
--		gvt_vgpu_err("fail to pin shadow context\n");
--		goto out;
-+		}
- 	}
- 
- out:
-@@ -408,7 +454,7 @@ static void update_guest_context(struct
- 			return;
- 		}
- 
--		page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i);
-+		page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
- 		src = kmap(page);
- 		intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
- 				GTT_PAGE_SIZE);
---- linux-4.14/drivers/gpu/drm/i915/gvt/scheduler.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/gvt/scheduler.h	2017-12-14 06:39:58.498903625 +0100
-@@ -141,4 +141,5 @@ int intel_vgpu_init_gvt_context(struct i
- 
- void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu);
- 
-+void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx);
- #endif
---- linux-4.14/drivers/gpu/drm/i915/i915_debugfs.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_debugfs.c	2017-12-14 06:39:58.498903625 +0100
-@@ -67,7 +67,7 @@ static int i915_capabilities(struct seq_
- #undef PRINT_FLAG
- 
- 	kernel_param_lock(THIS_MODULE);
--#define PRINT_PARAM(T, x) seq_print_param(m, #x, #T, &i915.x);
-+#define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x);
- 	I915_PARAMS_FOR_EACH(PRINT_PARAM);
- #undef PRINT_PARAM
- 	kernel_param_unlock(THIS_MODULE);
-@@ -1267,7 +1267,7 @@ static int i915_hangcheck_info(struct se
- 	if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
- 		seq_puts(m, "struct_mutex blocked for reset\n");
- 
--	if (!i915.enable_hangcheck) {
-+	if (!i915_modparams.enable_hangcheck) {
- 		seq_puts(m, "Hangcheck disabled\n");
- 		return 0;
- 	}
-@@ -1422,6 +1422,9 @@ static int i915_forcewake_domains(struct
- 	struct intel_uncore_forcewake_domain *fw_domain;
- 	unsigned int tmp;
- 
-+	seq_printf(m, "user.bypass_count = %u\n",
-+		   i915->uncore.user_forcewake.count);
-+
- 	for_each_fw_domain(fw_domain, i915, tmp)
- 		seq_printf(m, "%s.wake_count = %u\n",
- 			   intel_uncore_forcewake_domain_to_str(fw_domain->id),
-@@ -1699,7 +1702,7 @@ static int i915_ips_status(struct seq_fi
- 	intel_runtime_pm_get(dev_priv);
- 
- 	seq_printf(m, "Enabled by kernel parameter: %s\n",
--		   yesno(i915.enable_ips));
-+		   yesno(i915_modparams.enable_ips));
- 
- 	if (INTEL_GEN(dev_priv) >= 8) {
- 		seq_puts(m, "Currently: unknown\n");
-@@ -2014,7 +2017,7 @@ static int i915_dump_lrc(struct seq_file
- 	enum intel_engine_id id;
- 	int ret;
- 
--	if (!i915.enable_execlists) {
-+	if (!i915_modparams.enable_execlists) {
- 		seq_printf(m, "Logical Ring Contexts are disabled\n");
- 		return 0;
- 	}
-@@ -2443,12 +2446,8 @@ static void i915_guc_client_info(struct
- 
- 	seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
- 		client->priority, client->stage_id, client->proc_desc_offset);
--	seq_printf(m, "\tDoorbell id %d, offset: 0x%lx, cookie 0x%x\n",
--		client->doorbell_id, client->doorbell_offset, client->doorbell_cookie);
--	seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
--		client->wq_size, client->wq_offset, client->wq_tail);
--
--	seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
-+	seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
-+		client->doorbell_id, client->doorbell_offset);
- 
- 	for_each_engine(engine, dev_priv, id) {
- 		u64 submissions = client->submissions[id];
-@@ -2594,7 +2593,7 @@ static int i915_guc_log_control_get(void
- 	if (!dev_priv->guc.log.vma)
- 		return -EINVAL;
- 
--	*val = i915.guc_log_level;
-+	*val = i915_modparams.guc_log_level;
- 
- 	return 0;
- }
-@@ -3312,7 +3311,9 @@ static int i915_engine_info(struct seq_f
- 		seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
- 			   upper_32_bits(addr), lower_32_bits(addr));
- 
--		if (i915.enable_execlists) {
-+		if (i915_modparams.enable_execlists) {
-+			const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
-+			struct intel_engine_execlists * const execlists = &engine->execlists;
- 			u32 ptr, read, write;
- 			unsigned int idx;
- 
-@@ -3323,8 +3324,10 @@ static int i915_engine_info(struct seq_f
- 			ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
- 			read = GEN8_CSB_READ_PTR(ptr);
- 			write = GEN8_CSB_WRITE_PTR(ptr);
--			seq_printf(m, "\tExeclist CSB read %d, write %d, interrupt posted? %s\n",
--				   read, write,
-+			seq_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d from hws], interrupt posted? %s\n",
-+				   read, execlists->csb_head,
-+				   write,
-+				   intel_read_status_page(engine, intel_hws_csb_write_index(engine->i915)),
- 				   yesno(test_bit(ENGINE_IRQ_EXECLIST,
- 						  &engine->irq_posted)));
- 			if (read >= GEN8_CSB_ENTRIES)
-@@ -3335,18 +3338,19 @@ static int i915_engine_info(struct seq_f
- 				write += GEN8_CSB_ENTRIES;
- 			while (read < write) {
- 				idx = ++read % GEN8_CSB_ENTRIES;
--				seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
-+				seq_printf(m, "\tExeclist CSB[%d]: 0x%08x [0x%08x in hwsp], context: %d [%d in hwsp]\n",
- 					   idx,
- 					   I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
--					   I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
-+					   hws[idx * 2],
-+					   I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)),
-+					   hws[idx * 2 + 1]);
- 			}
- 
- 			rcu_read_lock();
--			for (idx = 0; idx < ARRAY_SIZE(engine->execlist_port); idx++) {
-+			for (idx = 0; idx < execlists_num_ports(execlists); idx++) {
- 				unsigned int count;
- 
--				rq = port_unpack(&engine->execlist_port[idx],
--						 &count);
-+				rq = port_unpack(&execlists->port[idx], &count);
- 				if (rq) {
- 					seq_printf(m, "\t\tELSP[%d] count=%d, ",
- 						   idx, count);
-@@ -3359,7 +3363,7 @@ static int i915_engine_info(struct seq_f
- 			rcu_read_unlock();
- 
- 			spin_lock_irq(&engine->timeline->lock);
--			for (rb = engine->execlist_first; rb; rb = rb_next(rb)){
-+			for (rb = execlists->first; rb; rb = rb_next(rb)) {
- 				struct i915_priolist *p =
- 					rb_entry(rb, typeof(*p), node);
- 
-@@ -3403,7 +3407,7 @@ static int i915_semaphore_status(struct
- 	enum intel_engine_id id;
- 	int j, ret;
- 
--	if (!i915.semaphores) {
-+	if (!i915_modparams.semaphores) {
- 		seq_puts(m, "Semaphores are disabled\n");
- 		return 0;
- 	}
-@@ -3523,6 +3527,57 @@ static int i915_wa_registers(struct seq_
- 	return 0;
- }
- 
-+static int i915_ipc_status_show(struct seq_file *m, void *data)
-+{
-+	struct drm_i915_private *dev_priv = m->private;
-+
-+	seq_printf(m, "Isochronous Priority Control: %s\n",
-+			yesno(dev_priv->ipc_enabled));
-+	return 0;
-+}
-+
-+static int i915_ipc_status_open(struct inode *inode, struct file *file)
-+{
-+	struct drm_i915_private *dev_priv = inode->i_private;
-+
-+	if (!HAS_IPC(dev_priv))
-+		return -ENODEV;
-+
-+	return single_open(file, i915_ipc_status_show, dev_priv);
-+}
-+
-+static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
-+				     size_t len, loff_t *offp)
-+{
-+	struct seq_file *m = file->private_data;
-+	struct drm_i915_private *dev_priv = m->private;
-+	int ret;
-+	bool enable;
-+
-+	ret = kstrtobool_from_user(ubuf, len, &enable);
-+	if (ret < 0)
-+		return ret;
-+
-+	intel_runtime_pm_get(dev_priv);
-+	if (!dev_priv->ipc_enabled && enable)
-+		DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
-+	dev_priv->wm.distrust_bios_wm = true;
-+	dev_priv->ipc_enabled = enable;
-+	intel_enable_ipc(dev_priv);
-+	intel_runtime_pm_put(dev_priv);
-+
-+	return len;
-+}
-+
-+static const struct file_operations i915_ipc_status_fops = {
-+	.owner = THIS_MODULE,
-+	.open = i915_ipc_status_open,
-+	.read = seq_read,
-+	.llseek = seq_lseek,
-+	.release = single_release,
-+	.write = i915_ipc_status_write
-+};
-+
- static int i915_ddb_info(struct seq_file *m, void *unused)
- {
- 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
-@@ -4674,26 +4729,26 @@ static int i915_sseu_status(struct seq_f
- 
- static int i915_forcewake_open(struct inode *inode, struct file *file)
- {
--	struct drm_i915_private *dev_priv = inode->i_private;
-+	struct drm_i915_private *i915 = inode->i_private;
- 
--	if (INTEL_GEN(dev_priv) < 6)
-+	if (INTEL_GEN(i915) < 6)
- 		return 0;
- 
--	intel_runtime_pm_get(dev_priv);
--	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
-+	intel_runtime_pm_get(i915);
-+	intel_uncore_forcewake_user_get(i915);
- 
- 	return 0;
- }
- 
- static int i915_forcewake_release(struct inode *inode, struct file *file)
- {
--	struct drm_i915_private *dev_priv = inode->i_private;
-+	struct drm_i915_private *i915 = inode->i_private;
- 
--	if (INTEL_GEN(dev_priv) < 6)
-+	if (INTEL_GEN(i915) < 6)
- 		return 0;
- 
--	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
--	intel_runtime_pm_put(dev_priv);
-+	intel_uncore_forcewake_user_put(i915);
-+	intel_runtime_pm_put(i915);
- 
- 	return 0;
- }
-@@ -4859,7 +4914,8 @@ static const struct i915_debugfs_files {
- 	{"i915_dp_test_type", &i915_displayport_test_type_fops},
- 	{"i915_dp_test_active", &i915_displayport_test_active_fops},
- 	{"i915_guc_log_control", &i915_guc_log_control_fops},
--	{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}
-+	{"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
-+	{"i915_ipc_status", &i915_ipc_status_fops}
- };
- 
- int i915_debugfs_register(struct drm_i915_private *dev_priv)
---- linux-4.14/drivers/gpu/drm/i915/i915_drv.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_drv.c	2017-12-14 06:39:58.499903626 +0100
-@@ -58,12 +58,12 @@ static unsigned int i915_load_fail_count
- 
- bool __i915_inject_load_failure(const char *func, int line)
- {
--	if (i915_load_fail_count >= i915.inject_load_failure)
-+	if (i915_load_fail_count >= i915_modparams.inject_load_failure)
- 		return false;
- 
--	if (++i915_load_fail_count == i915.inject_load_failure) {
-+	if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
- 		DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
--			 i915.inject_load_failure, func, line);
-+			 i915_modparams.inject_load_failure, func, line);
- 		return true;
- 	}
- 
-@@ -106,8 +106,8 @@ __i915_printk(struct drm_i915_private *d
- 
- static bool i915_error_injected(struct drm_i915_private *dev_priv)
- {
--	return i915.inject_load_failure &&
--	       i915_load_fail_count == i915.inject_load_failure;
-+	return i915_modparams.inject_load_failure &&
-+	       i915_load_fail_count == i915_modparams.inject_load_failure;
- }
- 
- #define i915_load_error(dev_priv, fmt, ...)				     \
-@@ -239,7 +239,8 @@ static void intel_detect_pch(struct drm_
- 				dev_priv->pch_type = PCH_KBP;
- 				DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
- 				WARN_ON(!IS_SKYLAKE(dev_priv) &&
--					!IS_KABYLAKE(dev_priv));
-+					!IS_KABYLAKE(dev_priv) &&
-+					!IS_COFFEELAKE(dev_priv));
- 			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
- 				dev_priv->pch_type = PCH_CNP;
- 				DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
-@@ -320,7 +321,7 @@ static int i915_getparam(struct drm_devi
- 		value = USES_PPGTT(dev_priv);
- 		break;
- 	case I915_PARAM_HAS_SEMAPHORES:
--		value = i915.semaphores;
-+		value = i915_modparams.semaphores;
- 		break;
- 	case I915_PARAM_HAS_SECURE_BATCHES:
- 		value = capable(CAP_SYS_ADMIN);
-@@ -339,7 +340,8 @@ static int i915_getparam(struct drm_devi
- 			return -ENODEV;
- 		break;
- 	case I915_PARAM_HAS_GPU_RESET:
--		value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
-+		value = i915_modparams.enable_hangcheck &&
-+			intel_has_gpu_reset(dev_priv);
- 		if (value && intel_has_reset_engine(dev_priv))
- 			value = 2;
- 		break;
-@@ -868,6 +870,10 @@ static int i915_driver_init_early(struct
- 	memcpy(device_info, match_info, sizeof(*device_info));
- 	device_info->device_id = dev_priv->drm.pdev->device;
- 
-+	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
-+		     sizeof(device_info->platform_mask) * BITS_PER_BYTE);
-+	device_info->platform_mask = BIT(device_info->platform);
-+
- 	BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
- 	device_info->gen_mask = BIT(device_info->gen - 1);
- 
-@@ -1030,9 +1036,9 @@ static void i915_driver_cleanup_mmio(str
- 
- static void intel_sanitize_options(struct drm_i915_private *dev_priv)
- {
--	i915.enable_execlists =
-+	i915_modparams.enable_execlists =
- 		intel_sanitize_enable_execlists(dev_priv,
--						i915.enable_execlists);
-+						i915_modparams.enable_execlists);
- 
- 	/*
- 	 * i915.enable_ppgtt is read-only, so do an early pass to validate the
-@@ -1040,12 +1046,15 @@ static void intel_sanitize_options(struc
- 	 * do this now so that we can print out any log messages once rather
- 	 * than every time we check intel_enable_ppgtt().
- 	 */
--	i915.enable_ppgtt =
--		intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
--	DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
--
--	i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
--	DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
-+	i915_modparams.enable_ppgtt =
-+		intel_sanitize_enable_ppgtt(dev_priv,
-+					    i915_modparams.enable_ppgtt);
-+	DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
-+
-+	i915_modparams.semaphores =
-+		intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores);
-+	DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
-+			 yesno(i915_modparams.semaphores));
- 
- 	intel_uc_sanitize_options(dev_priv);
- 
-@@ -1276,7 +1285,7 @@ int i915_driver_load(struct pci_dev *pde
- 	int ret;
- 
- 	/* Enable nuclear pageflip on ILK+ */
--	if (!i915.nuclear_pageflip && match_info->gen < 5)
-+	if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
- 		driver.driver_features &= ~DRIVER_ATOMIC;
- 
- 	ret = -ENOMEM;
-@@ -1340,7 +1349,7 @@ int i915_driver_load(struct pci_dev *pde
- 
- 	intel_runtime_pm_enable(dev_priv);
- 
--	dev_priv->ipc_enabled = false;
-+	intel_init_ipc(dev_priv);
- 
- 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
- 		DRM_INFO("DRM_I915_DEBUG enabled\n");
-@@ -2610,6 +2619,8 @@ static int intel_runtime_resume(struct d
- 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
- 		intel_hpd_init(dev_priv);
- 
-+	intel_enable_ipc(dev_priv);
-+
- 	enable_rpm_wakeref_asserts(dev_priv);
- 
- 	if (ret)
---- linux-4.14/drivers/gpu/drm/i915/i915_drv.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_drv.h	2017-12-14 06:39:58.499903626 +0100
-@@ -80,8 +80,8 @@
- 
- #define DRIVER_NAME		"i915"
- #define DRIVER_DESC		"Intel Graphics"
--#define DRIVER_DATE		"20170818"
--#define DRIVER_TIMESTAMP	1503088845
-+#define DRIVER_DATE		"20170929"
-+#define DRIVER_TIMESTAMP	1506682238
- 
- /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
-  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
-@@ -93,7 +93,7 @@
- #define I915_STATE_WARN(condition, format...) ({			\
- 	int __ret_warn_on = !!(condition);				\
- 	if (unlikely(__ret_warn_on))					\
--		if (!WARN(i915.verbose_state_checks, format))		\
-+		if (!WARN(i915_modparams.verbose_state_checks, format))	\
- 			DRM_ERROR(format);				\
- 	unlikely(__ret_warn_on);					\
- })
-@@ -126,7 +126,7 @@ static inline uint_fixed_16_16_t u32_to_
- {
- 	uint_fixed_16_16_t fp;
- 
--	WARN_ON(val >> 16);
-+	WARN_ON(val > U16_MAX);
- 
- 	fp.val = val << 16;
- 	return fp;
-@@ -163,8 +163,8 @@ static inline uint_fixed_16_16_t max_fix
- static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
- {
- 	uint_fixed_16_16_t fp;
--	WARN_ON(val >> 32);
--	fp.val = clamp_t(uint32_t, val, 0, ~0);
-+	WARN_ON(val > U32_MAX);
-+	fp.val = (uint32_t) val;
- 	return fp;
- }
- 
-@@ -181,8 +181,8 @@ static inline uint32_t mul_round_up_u32_
- 
- 	intermediate_val = (uint64_t) val * mul.val;
- 	intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
--	WARN_ON(intermediate_val >> 32);
--	return clamp_t(uint32_t, intermediate_val, 0, ~0);
-+	WARN_ON(intermediate_val > U32_MAX);
-+	return (uint32_t) intermediate_val;
- }
- 
- static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
-@@ -211,8 +211,8 @@ static inline uint32_t div_round_up_u32_
- 
- 	interm_val = (uint64_t)val << 16;
- 	interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
--	WARN_ON(interm_val >> 32);
--	return clamp_t(uint32_t, interm_val, 0, ~0);
-+	WARN_ON(interm_val > U32_MAX);
-+	return (uint32_t) interm_val;
- }
- 
- static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
-@@ -569,6 +569,24 @@ struct i915_hotplug {
- 	     (__i)++) \
- 		for_each_if (plane_state)
- 
-+#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
-+	for ((__i) = 0; \
-+	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
-+		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
-+		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
-+	     (__i)++) \
-+		for_each_if (crtc)
-+
-+
-+#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
-+	for ((__i) = 0; \
-+	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
-+		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
-+		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
-+		      (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
-+	     (__i)++) \
-+		for_each_if (plane)
-+
- struct drm_i915_private;
- struct i915_mm_struct;
- struct i915_mmu_object;
-@@ -707,8 +725,7 @@ struct drm_i915_display_funcs {
- 			    struct drm_atomic_state *old_state);
- 	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
- 			     struct drm_atomic_state *old_state);
--	void (*update_crtcs)(struct drm_atomic_state *state,
--			     unsigned int *crtc_vblank_mask);
-+	void (*update_crtcs)(struct drm_atomic_state *state);
- 	void (*audio_codec_enable)(struct drm_connector *connector,
- 				   struct intel_encoder *encoder,
- 				   const struct drm_display_mode *adjusted_mode);
-@@ -759,7 +776,6 @@ struct intel_csr {
- 	func(has_fpga_dbg); \
- 	func(has_full_ppgtt); \
- 	func(has_full_48bit_ppgtt); \
--	func(has_gmbus_irq); \
- 	func(has_gmch_display); \
- 	func(has_guc); \
- 	func(has_guc_ct); \
-@@ -780,7 +796,8 @@ struct intel_csr {
- 	func(cursor_needs_physical); \
- 	func(hws_needs_physical); \
- 	func(overlay_needs_physical); \
--	func(supports_tv);
-+	func(supports_tv); \
-+	func(has_ipc);
- 
- struct sseu_dev_info {
- 	u8 slice_mask;
-@@ -834,20 +851,28 @@ enum intel_platform {
- };
- 
- struct intel_device_info {
--	u32 display_mmio_offset;
- 	u16 device_id;
-+	u16 gen_mask;
-+
-+	u8 gen;
-+	u8 gt; /* GT number, 0 if undefined */
-+	u8 num_rings;
-+	u8 ring_mask; /* Rings supported by the HW */
-+
-+	enum intel_platform platform;
-+	u32 platform_mask;
-+
-+	u32 display_mmio_offset;
-+
- 	u8 num_pipes;
- 	u8 num_sprites[I915_MAX_PIPES];
- 	u8 num_scalers[I915_MAX_PIPES];
--	u8 gen;
--	u16 gen_mask;
--	enum intel_platform platform;
--	u8 ring_mask; /* Rings supported by the HW */
--	u8 num_rings;
-+
- #define DEFINE_FLAG(name) u8 name:1
- 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
- #undef DEFINE_FLAG
- 	u16 ddb_size; /* in blocks */
-+
- 	/* Register offsets for the various display pipes and transcoders */
- 	int pipe_offsets[I915_MAX_TRANSCODERS];
- 	int trans_offsets[I915_MAX_TRANSCODERS];
-@@ -982,7 +1007,8 @@ struct i915_gpu_state {
- 			u32 seqno;
- 			u32 head;
- 			u32 tail;
--		} *requests, execlist[2];
-+		} *requests, execlist[EXECLIST_MAX_PORTS];
-+		unsigned int num_ports;
- 
- 		struct drm_i915_error_waiter {
- 			char comm[TASK_COMM_LEN];
-@@ -1107,6 +1133,7 @@ struct intel_fbc {
- 		} fb;
- 
- 		int cfb_size;
-+		unsigned int gen9_wa_cfb_stride;
- 	} params;
- 
- 	struct intel_fbc_work {
-@@ -1159,6 +1186,14 @@ struct i915_psr {
- 	bool y_cord_support;
- 	bool colorimetry_support;
- 	bool alpm;
-+
-+	void (*enable_source)(struct intel_dp *,
-+			      const struct intel_crtc_state *);
-+	void (*disable_source)(struct intel_dp *,
-+			       const struct intel_crtc_state *);
-+	void (*enable_sink)(struct intel_dp *);
-+	void (*activate)(struct intel_dp *);
-+	void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
- };
- 
- enum intel_pch {
-@@ -1465,6 +1500,11 @@ struct i915_gem_mm {
- 	struct llist_head free_list;
- 	struct work_struct free_work;
- 
-+	/**
-+	 * Small stash of WC pages
-+	 */
-+	struct pagevec wc_stash;
-+
- 	/** Usable portion of the GTT for GEM */
- 	dma_addr_t stolen_base; /* limited to low memory (32-bit) */
- 
-@@ -1718,7 +1758,7 @@ struct intel_vbt_data {
- 	int crt_ddc_pin;
- 
- 	int child_dev_num;
--	union child_device_config *child_dev;
-+	struct child_device_config *child_dev;
- 
- 	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
- 	struct sdvo_device_mapping sdvo_mappings[2];
-@@ -1812,6 +1852,20 @@ struct skl_wm_level {
- 	uint8_t plane_res_l;
- };
- 
-+/* Stores plane specific WM parameters */
-+struct skl_wm_params {
-+	bool x_tiled, y_tiled;
-+	bool rc_surface;
-+	uint32_t width;
-+	uint8_t cpp;
-+	uint32_t plane_pixel_rate;
-+	uint32_t y_min_scanlines;
-+	uint32_t plane_bytes_per_line;
-+	uint_fixed_16_16_t plane_blocks_per_line;
-+	uint_fixed_16_16_t y_tile_minimum;
-+	uint32_t linetime_us;
-+};
-+
- /*
-  * This struct helps tracking the state needed for runtime PM, which puts the
-  * device in PCI D3 state. Notice that when this happens, nothing on the
-@@ -2307,6 +2361,8 @@ struct drm_i915_private {
- 	DECLARE_HASHTABLE(mm_structs, 7);
- 	struct mutex mm_lock;
- 
-+	struct intel_ppat ppat;
-+
- 	/* Kernel Modesetting */
- 
- 	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
-@@ -2329,7 +2385,8 @@ struct drm_i915_private {
- 	struct mutex dpll_lock;
- 
- 	unsigned int active_crtcs;
--	unsigned int min_pixclk[I915_MAX_PIPES];
-+	/* minimum acceptable cdclk for each pipe */
-+	int min_cdclk[I915_MAX_PIPES];
- 
- 	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
- 
-@@ -2786,8 +2843,8 @@ static inline struct scatterlist *__sg_n
- #define for_each_sgt_dma(__dmap, __iter, __sgt)				\
- 	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
- 	     ((__dmap) = (__iter).dma + (__iter).curr);			\
--	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
--	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
-+	     (((__iter).curr += PAGE_SIZE) >= (__iter).max) ?		\
-+	     (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
- 
- /**
-  * for_each_sgt_page - iterate over the pages of the given sg_table
-@@ -2799,8 +2856,23 @@ static inline struct scatterlist *__sg_n
- 	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
- 	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
- 	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
--	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
--	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
-+	     (((__iter).curr += PAGE_SIZE) >= (__iter).max) ?		\
-+	     (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
-+
-+static inline unsigned int i915_sg_segment_size(void)
-+{
-+	unsigned int size = swiotlb_max_segment();
-+
-+	if (size == 0)
-+		return SCATTERLIST_MAX_SEGMENT;
-+
-+	size = rounddown(size, PAGE_SIZE);
-+	/* swiotlb_max_segment_size can return 1 byte when it means one page. */
-+	if (size < PAGE_SIZE)
-+		size = PAGE_SIZE;
-+
-+	return size;
-+}
- 
- static inline const struct intel_device_info *
- intel_info(const struct drm_i915_private *dev_priv)
-@@ -2817,23 +2889,21 @@ intel_info(const struct drm_i915_private
- #define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
- 
- #define GEN_FOREVER (0)
-+
-+#define INTEL_GEN_MASK(s, e) ( \
-+	BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
-+	BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
-+	GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
-+		(s) != GEN_FOREVER ? (s) - 1 : 0) \
-+)
-+
- /*
-  * Returns true if Gen is in inclusive range [Start, End].
-  *
-  * Use GEN_FOREVER for unbound start and or end.
-  */
--#define IS_GEN(dev_priv, s, e) ({ \
--	unsigned int __s = (s), __e = (e); \
--	BUILD_BUG_ON(!__builtin_constant_p(s)); \
--	BUILD_BUG_ON(!__builtin_constant_p(e)); \
--	if ((__s) != GEN_FOREVER) \
--		__s = (s) - 1; \
--	if ((__e) == GEN_FOREVER) \
--		__e = BITS_PER_LONG - 1; \
--	else \
--		__e = (e) - 1; \
--	!!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
--})
-+#define IS_GEN(dev_priv, s, e) \
-+	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
- 
- /*
-  * Return true if revision is in range [since,until] inclusive.
-@@ -2843,38 +2913,39 @@ intel_info(const struct drm_i915_private
- #define IS_REVID(p, since, until) \
- 	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
- 
--#define IS_I830(dev_priv)	((dev_priv)->info.platform == INTEL_I830)
--#define IS_I845G(dev_priv)	((dev_priv)->info.platform == INTEL_I845G)
--#define IS_I85X(dev_priv)	((dev_priv)->info.platform == INTEL_I85X)
--#define IS_I865G(dev_priv)	((dev_priv)->info.platform == INTEL_I865G)
--#define IS_I915G(dev_priv)	((dev_priv)->info.platform == INTEL_I915G)
--#define IS_I915GM(dev_priv)	((dev_priv)->info.platform == INTEL_I915GM)
--#define IS_I945G(dev_priv)	((dev_priv)->info.platform == INTEL_I945G)
--#define IS_I945GM(dev_priv)	((dev_priv)->info.platform == INTEL_I945GM)
--#define IS_I965G(dev_priv)	((dev_priv)->info.platform == INTEL_I965G)
--#define IS_I965GM(dev_priv)	((dev_priv)->info.platform == INTEL_I965GM)
--#define IS_G45(dev_priv)	((dev_priv)->info.platform == INTEL_G45)
--#define IS_GM45(dev_priv)	((dev_priv)->info.platform == INTEL_GM45)
-+#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
-+
-+#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
-+#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
-+#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
-+#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
-+#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
-+#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
-+#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
-+#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
-+#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
-+#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
-+#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
-+#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
- #define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
- #define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
- #define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
--#define IS_PINEVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_PINEVIEW)
--#define IS_G33(dev_priv)	((dev_priv)->info.platform == INTEL_G33)
-+#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
-+#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
- #define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
--#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.platform == INTEL_IVYBRIDGE)
--#define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \
--				 INTEL_DEVID(dev_priv) == 0x0152 || \
--				 INTEL_DEVID(dev_priv) == 0x015a)
--#define IS_VALLEYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_VALLEYVIEW)
--#define IS_CHERRYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_CHERRYVIEW)
--#define IS_HASWELL(dev_priv)	((dev_priv)->info.platform == INTEL_HASWELL)
--#define IS_BROADWELL(dev_priv)	((dev_priv)->info.platform == INTEL_BROADWELL)
--#define IS_SKYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_SKYLAKE)
--#define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
--#define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
--#define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform == INTEL_GEMINILAKE)
--#define IS_COFFEELAKE(dev_priv)	((dev_priv)->info.platform == INTEL_COFFEELAKE)
--#define IS_CANNONLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_CANNONLAKE)
-+#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
-+#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
-+				 (dev_priv)->info.gt == 1)
-+#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
-+#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
-+#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
-+#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
-+#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
-+#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
-+#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
-+#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
-+#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
-+#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
- #define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
- #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
- 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
-@@ -2886,11 +2957,11 @@ intel_info(const struct drm_i915_private
- #define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
- 				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
- #define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
--				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
-+				 (dev_priv)->info.gt == 3)
- #define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
- 				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
- #define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
--				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
-+				 (dev_priv)->info.gt == 3)
- /* ULX machines are also considered ULT. */
- #define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
- 				 INTEL_DEVID(dev_priv) == 0x0A1E)
-@@ -2911,17 +2982,19 @@ intel_info(const struct drm_i915_private
- 				 INTEL_DEVID(dev_priv) == 0x5915 || \
- 				 INTEL_DEVID(dev_priv) == 0x591E)
- #define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
--				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
-+				 (dev_priv)->info.gt == 2)
- #define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
--				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
-+				 (dev_priv)->info.gt == 3)
- #define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
--				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
-+				 (dev_priv)->info.gt == 4)
- #define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
--				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
-+				 (dev_priv)->info.gt == 2)
- #define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
--				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
-+				 (dev_priv)->info.gt == 3)
- #define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
- 				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
-+#define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
-+				 (dev_priv)->info.gt == 2)
- 
- #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
- 
-@@ -3012,9 +3085,9 @@ intel_info(const struct drm_i915_private
- 
- #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
- 		((dev_priv)->info.has_logical_ring_contexts)
--#define USES_PPGTT(dev_priv)		(i915.enable_ppgtt)
--#define USES_FULL_PPGTT(dev_priv)	(i915.enable_ppgtt >= 2)
--#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915.enable_ppgtt == 3)
-+#define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
-+#define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
-+#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
- 
- #define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
- #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
-@@ -3032,9 +3105,12 @@ intel_info(const struct drm_i915_private
-  * even when in MSI mode. This results in spurious interrupt warnings if the
-  * legacy irq no. is shared with another device. The kernel then disables that
-  * interrupt source and so prevents the other device from working properly.
-+ *
-+ * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
-+ * interrupts.
-  */
--#define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
--#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
-+#define HAS_AUX_IRQ(dev_priv)   true
-+#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
- 
- /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
-  * rows, which changed the alignment requirements and fence programming.
-@@ -3065,6 +3141,8 @@ intel_info(const struct drm_i915_private
- #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
- #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
- 
-+#define HAS_IPC(dev_priv)		 ((dev_priv)->info.has_ipc)
-+
- /*
-  * For now, anything with a GuC requires uCode loading, and then supports
-  * command submission once loaded. But these are logically independent
-@@ -3210,7 +3288,7 @@ static inline void i915_queue_hangcheck(
- {
- 	unsigned long delay;
- 
--	if (unlikely(!i915.enable_hangcheck))
-+	if (unlikely(!i915_modparams.enable_hangcheck))
- 		return;
- 
- 	/* Don't continually defer the hangcheck so that it is always run at
-@@ -3243,6 +3321,8 @@ static inline bool intel_vgpu_active(str
- 	return dev_priv->vgpu.active;
- }
- 
-+u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
-+			      enum pipe pipe);
- void
- i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
- 		     u32 status_mask);
-@@ -3648,6 +3728,9 @@ i915_vm_to_ppgtt(struct i915_address_spa
- /* i915_gem_fence_reg.c */
- int __must_check i915_vma_get_fence(struct i915_vma *vma);
- int __must_check i915_vma_put_fence(struct i915_vma *vma);
-+struct drm_i915_fence_reg *
-+i915_reserve_fence(struct drm_i915_private *dev_priv);
-+void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
- 
- void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
- void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
-@@ -4333,11 +4416,12 @@ int remap_io_mapping(struct vm_area_stru
- 		     unsigned long addr, unsigned long pfn, unsigned long size,
- 		     struct io_mapping *iomap);
- 
--static inline bool
--intel_engine_can_store_dword(struct intel_engine_cs *engine)
-+static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
- {
--	return __intel_engine_can_store_dword(INTEL_GEN(engine->i915),
--					      engine->class);
-+	if (INTEL_GEN(i915) >= 10)
-+		return CNL_HWS_CSB_WRITE_INDEX;
-+	else
-+		return I915_HWS_CSB_WRITE_INDEX;
- }
- 
- #endif
---- linux-4.14/drivers/gpu/drm/i915/i915_gem.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_gem.c	2017-12-14 06:39:58.500903627 +0100
-@@ -179,7 +179,7 @@ i915_gem_object_get_pages_phys(struct dr
- 	 * the alignment of the buddy allocation will naturally match.
- 	 */
- 	phys = drm_pci_alloc(obj->base.dev,
--			     obj->base.size,
-+			     roundup_pow_of_two(obj->base.size),
- 			     roundup_pow_of_two(obj->base.size));
- 	if (!phys)
- 		return ERR_PTR(-ENOMEM);
-@@ -694,10 +694,10 @@ flush_write_domain(struct drm_i915_gem_o
- 
- 	switch (obj->base.write_domain) {
- 	case I915_GEM_DOMAIN_GTT:
--		if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
-+		if (!HAS_LLC(dev_priv)) {
- 			intel_runtime_pm_get(dev_priv);
- 			spin_lock_irq(&dev_priv->uncore.lock);
--			POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
-+			POSTING_READ_FW(RING_HEAD(dev_priv->engine[RCS]->mmio_base));
- 			spin_unlock_irq(&dev_priv->uncore.lock);
- 			intel_runtime_pm_put(dev_priv);
- 		}
-@@ -1013,17 +1013,20 @@ gtt_user_read(struct io_mapping *mapping
- 	      loff_t base, int offset,
- 	      char __user *user_data, int length)
- {
--	void *vaddr;
-+	void __iomem *vaddr;
- 	unsigned long unwritten;
- 
- 	/* We can use the cpu mem copy function because this is X86. */
--	vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
--	unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
-+	vaddr = io_mapping_map_atomic_wc(mapping, base);
-+	unwritten = __copy_to_user_inatomic(user_data,
-+					    (void __force *)vaddr + offset,
-+					    length);
- 	io_mapping_unmap_atomic(vaddr);
- 	if (unwritten) {
--		vaddr = (void __force *)
--			io_mapping_map_wc(mapping, base, PAGE_SIZE);
--		unwritten = copy_to_user(user_data, vaddr + offset, length);
-+		vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
-+		unwritten = copy_to_user(user_data,
-+					 (void __force *)vaddr + offset,
-+					 length);
- 		io_mapping_unmap(vaddr);
- 	}
- 	return unwritten;
-@@ -1189,18 +1192,18 @@ ggtt_write(struct io_mapping *mapping,
- 	   loff_t base, int offset,
- 	   char __user *user_data, int length)
- {
--	void *vaddr;
-+	void __iomem *vaddr;
- 	unsigned long unwritten;
- 
- 	/* We can use the cpu mem copy function because this is X86. */
--	vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
--	unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
-+	vaddr = io_mapping_map_atomic_wc(mapping, base);
-+	unwritten = __copy_from_user_inatomic_nocache((void __force *)vaddr + offset,
- 						      user_data, length);
- 	io_mapping_unmap_atomic(vaddr);
- 	if (unwritten) {
--		vaddr = (void __force *)
--			io_mapping_map_wc(mapping, base, PAGE_SIZE);
--		unwritten = copy_from_user(vaddr + offset, user_data, length);
-+		vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
-+		unwritten = copy_from_user((void __force *)vaddr + offset,
-+					   user_data, length);
- 		io_mapping_unmap(vaddr);
- 	}
- 
-@@ -2302,7 +2305,7 @@ i915_gem_object_get_pages_gtt(struct drm
- 	struct sgt_iter sgt_iter;
- 	struct page *page;
- 	unsigned long last_pfn = 0;	/* suppress gcc warning */
--	unsigned int max_segment;
-+	unsigned int max_segment = i915_sg_segment_size();
- 	gfp_t noreclaim;
- 	int ret;
- 
-@@ -2313,10 +2316,6 @@ i915_gem_object_get_pages_gtt(struct drm
- 	GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
- 	GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
- 
--	max_segment = swiotlb_max_segment();
--	if (!max_segment)
--		max_segment = rounddown(UINT_MAX, PAGE_SIZE);
--
- 	st = kmalloc(sizeof(*st), GFP_KERNEL);
- 	if (st == NULL)
- 		return ERR_PTR(-ENOMEM);
-@@ -2478,8 +2477,6 @@ static int ____i915_gem_object_get_pages
- {
- 	struct sg_table *pages;
- 
--	GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
--
- 	if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
- 		DRM_DEBUG("Attempting to obtain a purgeable object\n");
- 		return -EFAULT;
-@@ -2509,6 +2506,8 @@ int __i915_gem_object_get_pages(struct d
- 		return err;
- 
- 	if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
-+		GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
-+
- 		err = ____i915_gem_object_get_pages(obj);
- 		if (err)
- 			goto unlock;
-@@ -2592,6 +2591,8 @@ void *i915_gem_object_pin_map(struct drm
- 
- 	if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
- 		if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
-+			GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
-+
- 			ret = ____i915_gem_object_get_pages(obj);
- 			if (ret)
- 				goto err_unlock;
-@@ -2819,8 +2820,8 @@ i915_gem_reset_prepare_engine(struct int
- 	 * Turning off the engine->irq_tasklet until the reset is over
- 	 * prevents the race.
- 	 */
--	tasklet_kill(&engine->irq_tasklet);
--	tasklet_disable(&engine->irq_tasklet);
-+	tasklet_kill(&engine->execlists.irq_tasklet);
-+	tasklet_disable(&engine->execlists.irq_tasklet);
- 
- 	if (engine->irq_seqno_barrier)
- 		engine->irq_seqno_barrier(engine);
-@@ -2999,7 +3000,7 @@ void i915_gem_reset(struct drm_i915_priv
- 
- void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
- {
--	tasklet_enable(&engine->irq_tasklet);
-+	tasklet_enable(&engine->execlists.irq_tasklet);
- 	kthread_unpark(engine->breadcrumbs.signaler);
- }
- 
-@@ -3031,9 +3032,6 @@ static void nop_submit_request(struct dr
- 
- static void engine_set_wedged(struct intel_engine_cs *engine)
- {
--	struct drm_i915_gem_request *request;
--	unsigned long flags;
--
- 	/* We need to be sure that no thread is running the old callback as
- 	 * we install the nop handler (otherwise we would submit a request
- 	 * to hardware that will never complete). In order to prevent this
-@@ -3043,40 +3041,7 @@ static void engine_set_wedged(struct int
- 	engine->submit_request = nop_submit_request;
- 
- 	/* Mark all executing requests as skipped */
--	spin_lock_irqsave(&engine->timeline->lock, flags);
--	list_for_each_entry(request, &engine->timeline->requests, link)
--		if (!i915_gem_request_completed(request))
--			dma_fence_set_error(&request->fence, -EIO);
--	spin_unlock_irqrestore(&engine->timeline->lock, flags);
--
--	/*
--	 * Clear the execlists queue up before freeing the requests, as those
--	 * are the ones that keep the context and ringbuffer backing objects
--	 * pinned in place.
--	 */
--
--	if (i915.enable_execlists) {
--		struct execlist_port *port = engine->execlist_port;
--		unsigned long flags;
--		unsigned int n;
--
--		spin_lock_irqsave(&engine->timeline->lock, flags);
--
--		for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
--			i915_gem_request_put(port_request(&port[n]));
--		memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
--		engine->execlist_queue = RB_ROOT;
--		engine->execlist_first = NULL;
--
--		spin_unlock_irqrestore(&engine->timeline->lock, flags);
--
--		/* The port is checked prior to scheduling a tasklet, but
--		 * just in case we have suspended the tasklet to do the
--		 * wedging make sure that when it wakes, it decides there
--		 * is no work to do by clearing the irq_posted bit.
--		 */
--		clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
--	}
-+	engine->cancel_requests(engine);
- 
- 	/* Mark all pending requests as complete so that any concurrent
- 	 * (lockless) lookup doesn't try and wait upon the request as we
-@@ -3267,11 +3232,11 @@ void i915_gem_close_object(struct drm_ge
- 		struct i915_gem_context *ctx = lut->ctx;
- 		struct i915_vma *vma;
- 
-+		GEM_BUG_ON(ctx->file_priv == ERR_PTR(-EBADF));
- 		if (ctx->file_priv != fpriv)
- 			continue;
- 
- 		vma = radix_tree_delete(&ctx->handles_vma, lut->handle);
--
- 		GEM_BUG_ON(vma->obj != obj);
- 
- 		/* We allow the process to have multiple handles to the same
-@@ -3385,24 +3350,12 @@ static int wait_for_timeline(struct i915
- 	return 0;
- }
- 
--static int wait_for_engine(struct intel_engine_cs *engine, int timeout_ms)
--{
--	return wait_for(intel_engine_is_idle(engine), timeout_ms);
--}
--
- static int wait_for_engines(struct drm_i915_private *i915)
- {
--	struct intel_engine_cs *engine;
--	enum intel_engine_id id;
--
--	for_each_engine(engine, i915, id) {
--		if (GEM_WARN_ON(wait_for_engine(engine, 50))) {
--			i915_gem_set_wedged(i915);
--			return -EIO;
--		}
--
--		GEM_BUG_ON(intel_engine_get_seqno(engine) !=
--			   intel_engine_last_submit(engine));
-+	if (wait_for(intel_engines_are_idle(i915), 50)) {
-+		DRM_ERROR("Failed to idle engines, declaring wedged!\n");
-+		i915_gem_set_wedged(i915);
-+		return -EIO;
- 	}
- 
- 	return 0;
-@@ -4436,6 +4389,7 @@ static void __i915_gem_free_objects(stru
- 	llist_for_each_entry_safe(obj, on, freed, freed) {
- 		GEM_BUG_ON(obj->bind_count);
- 		GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
-+		GEM_BUG_ON(!list_empty(&obj->lut_list));
- 
- 		if (obj->ops->release)
- 			obj->ops->release(obj);
-@@ -4543,6 +4497,12 @@ static void assert_kernel_context_is_cur
- 
- void i915_gem_sanitize(struct drm_i915_private *i915)
- {
-+	if (i915_terminally_wedged(&i915->gpu_error)) {
-+		mutex_lock(&i915->drm.struct_mutex);
-+		i915_gem_unset_wedged(i915);
-+		mutex_unlock(&i915->drm.struct_mutex);
-+	}
-+
- 	/*
- 	 * If we inherit context state from the BIOS or earlier occupants
- 	 * of the GPU, the GPU may be in an inconsistent state when we
-@@ -4582,7 +4542,7 @@ int i915_gem_suspend(struct drm_i915_pri
- 	ret = i915_gem_wait_for_idle(dev_priv,
- 				     I915_WAIT_INTERRUPTIBLE |
- 				     I915_WAIT_LOCKED);
--	if (ret)
-+	if (ret && ret != -EIO)
- 		goto err_unlock;
- 
- 	assert_kernel_context_is_current(dev_priv);
-@@ -4604,7 +4564,8 @@ int i915_gem_suspend(struct drm_i915_pri
- 	 * reset the GPU back to its idle, low power state.
- 	 */
- 	WARN_ON(dev_priv->gt.awake);
--	WARN_ON(!intel_engines_are_idle(dev_priv));
-+	if (WARN_ON(!intel_engines_are_idle(dev_priv)))
-+		i915_gem_set_wedged(dev_priv); /* no hope, discard everything */
- 
- 	/*
- 	 * Neither the BIOS, ourselves or any other kernel
-@@ -4626,11 +4587,12 @@ int i915_gem_suspend(struct drm_i915_pri
- 	 * machine in an unusable condition.
- 	 */
- 	i915_gem_sanitize(dev_priv);
--	goto out_rpm_put;
-+
-+	intel_runtime_pm_put(dev_priv);
-+	return 0;
- 
- err_unlock:
- 	mutex_unlock(&dev->struct_mutex);
--out_rpm_put:
- 	intel_runtime_pm_put(dev_priv);
- 	return ret;
- }
-@@ -4786,7 +4748,7 @@ bool intel_sanitize_semaphores(struct dr
- 		return false;
- 
- 	/* TODO: make semaphores and Execlists play nicely together */
--	if (i915.enable_execlists)
-+	if (i915_modparams.enable_execlists)
- 		return false;
- 
- 	if (value >= 0)
-@@ -4807,7 +4769,7 @@ int i915_gem_init(struct drm_i915_privat
- 
- 	dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
- 
--	if (!i915.enable_execlists) {
-+	if (!i915_modparams.enable_execlists) {
- 		dev_priv->gt.resume = intel_legacy_submission_resume;
- 		dev_priv->gt.cleanup_engine = intel_engine_cleanup;
- 	} else {
---- linux-4.14/drivers/gpu/drm/i915/i915_gem_context.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_gem_context.c	2017-12-14 06:39:58.500903627 +0100
-@@ -316,7 +316,7 @@ __create_hw_context(struct drm_i915_priv
- 	 * present or not in use we still need a small bias as ring wraparound
- 	 * at offset 0 sometimes hangs. No idea why.
- 	 */
--	if (HAS_GUC(dev_priv) && i915.enable_guc_loading)
-+	if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading)
- 		ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
- 	else
- 		ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
-@@ -409,7 +409,7 @@ i915_gem_context_create_gvt(struct drm_d
- 	i915_gem_context_set_closed(ctx); /* not user accessible */
- 	i915_gem_context_clear_bannable(ctx);
- 	i915_gem_context_set_force_single_submission(ctx);
--	if (!i915.enable_guc_submission)
-+	if (!i915_modparams.enable_guc_submission)
- 		ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
- 
- 	GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
-@@ -433,7 +433,7 @@ int i915_gem_contexts_init(struct drm_i9
- 
- 	if (intel_vgpu_active(dev_priv) &&
- 	    HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
--		if (!i915.enable_execlists) {
-+		if (!i915_modparams.enable_execlists) {
- 			DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
- 			return -EINVAL;
- 		}
-@@ -485,7 +485,7 @@ void i915_gem_contexts_lost(struct drm_i
- 	}
- 
- 	/* Force the GPU state to be restored on enabling */
--	if (!i915.enable_execlists) {
-+	if (!i915_modparams.enable_execlists) {
- 		struct i915_gem_context *ctx;
- 
- 		list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
-@@ -570,7 +570,7 @@ mi_set_context(struct drm_i915_gem_reque
- 	enum intel_engine_id id;
- 	const int num_rings =
- 		/* Use an extended w/a on gen7 if signalling from other rings */
--		(i915.semaphores && INTEL_GEN(dev_priv) == 7) ?
-+		(i915_modparams.semaphores && INTEL_GEN(dev_priv) == 7) ?
- 		INTEL_INFO(dev_priv)->num_rings - 1 :
- 		0;
- 	int len;
-@@ -839,7 +839,7 @@ int i915_switch_context(struct drm_i915_
- 	struct intel_engine_cs *engine = req->engine;
- 
- 	lockdep_assert_held(&req->i915->drm.struct_mutex);
--	if (i915.enable_execlists)
-+	if (i915_modparams.enable_execlists)
- 		return 0;
- 
- 	if (!req->ctx->engine[engine->id].state) {
---- linux-4.14/drivers/gpu/drm/i915/i915_gem_execbuffer.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_gem_execbuffer.c	2017-12-14 06:39:58.500903627 +0100
-@@ -58,6 +58,7 @@ enum {
- 
- #define __EXEC_HAS_RELOC	BIT(31)
- #define __EXEC_VALIDATED	BIT(30)
-+#define __EXEC_INTERNAL_FLAGS	(~0u << 30)
- #define UPDATE			PIN_OFFSET_FIXED
- 
- #define BATCH_OFFSET_BIAS (256*1024)
-@@ -268,6 +269,11 @@ static inline u64 gen8_noncanonical_addr
- 	return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);
- }
- 
-+static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
-+{
-+	return eb->engine->needs_cmd_parser && eb->batch_len;
-+}
-+
- static int eb_create(struct i915_execbuffer *eb)
- {
- 	if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
-@@ -678,7 +684,7 @@ static int eb_select_context(struct i915
- static int eb_lookup_vmas(struct i915_execbuffer *eb)
- {
- 	struct radix_tree_root *handles_vma = &eb->ctx->handles_vma;
--	struct drm_i915_gem_object *uninitialized_var(obj);
-+	struct drm_i915_gem_object *obj;
- 	unsigned int i;
- 	int err;
- 
-@@ -724,19 +730,17 @@ static int eb_lookup_vmas(struct i915_ex
- 			goto err_obj;
- 		}
- 
-+		/* transfer ref to ctx */
- 		vma->open_count++;
- 		list_add(&lut->obj_link, &obj->lut_list);
- 		list_add(&lut->ctx_link, &eb->ctx->handles_list);
- 		lut->ctx = eb->ctx;
- 		lut->handle = handle;
- 
--		/* transfer ref to ctx */
--		obj = NULL;
--
- add_vma:
- 		err = eb_add_vma(eb, i, vma);
- 		if (unlikely(err))
--			goto err_obj;
-+			goto err_vma;
- 
- 		GEM_BUG_ON(vma != eb->vma[i]);
- 		GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
-@@ -765,8 +769,7 @@ add_vma:
- 	return eb_reserve(eb);
- 
- err_obj:
--	if (obj)
--		i915_gem_object_put(obj);
-+	i915_gem_object_put(obj);
- err_vma:
- 	eb->vma[i] = NULL;
- 	return err;
-@@ -1163,6 +1166,13 @@ static u32 *reloc_gpu(struct i915_execbu
- 	if (unlikely(!cache->rq)) {
- 		int err;
- 
-+		/* If we need to copy for the cmdparser, we will stall anyway */
-+		if (eb_use_cmdparser(eb))
-+			return ERR_PTR(-EWOULDBLOCK);
-+
-+		if (!intel_engine_can_store_dword(eb->engine))
-+			return ERR_PTR(-ENODEV);
-+
- 		err = __reloc_gpu_alloc(eb, vma, len);
- 		if (unlikely(err))
- 			return ERR_PTR(err);
-@@ -1187,9 +1197,7 @@ relocate_entry(struct i915_vma *vma,
- 
- 	if (!eb->reloc_cache.vaddr &&
- 	    (DBG_FORCE_RELOC == FORCE_GPU_RELOC ||
--	     !reservation_object_test_signaled_rcu(vma->resv, true)) &&
--	    __intel_engine_can_store_dword(eb->reloc_cache.gen,
--					   eb->engine->class)) {
-+	     !reservation_object_test_signaled_rcu(vma->resv, true))) {
- 		const unsigned int gen = eb->reloc_cache.gen;
- 		unsigned int len;
- 		u32 *batch;
-@@ -1581,7 +1589,7 @@ static int eb_prefault_relocations(const
- 	const unsigned int count = eb->buffer_count;
- 	unsigned int i;
- 
--	if (unlikely(i915.prefault_disable))
-+	if (unlikely(i915_modparams.prefault_disable))
- 		return 0;
- 
- 	for (i = 0; i < count; i++) {
-@@ -2190,6 +2198,7 @@ i915_gem_do_execbuffer(struct drm_device
- 	int out_fence_fd = -1;
- 	int err;
- 
-+	BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
- 	BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
- 		     ~__EXEC_OBJECT_UNKNOWN_FLAGS);
- 
-@@ -2303,7 +2312,7 @@ i915_gem_do_execbuffer(struct drm_device
- 		goto err_vma;
- 	}
- 
--	if (eb.engine->needs_cmd_parser && eb.batch_len) {
-+	if (eb_use_cmdparser(&eb)) {
- 		struct i915_vma *vma;
- 
- 		vma = eb_parse(&eb, drm_is_current_master(file));
---- linux-4.14/drivers/gpu/drm/i915/i915_gem_fence_reg.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_gem_fence_reg.c	2017-12-14 06:39:58.500903627 +0100
-@@ -360,6 +360,57 @@ i915_vma_get_fence(struct i915_vma *vma)
- }
- 
- /**
-+ * i915_reserve_fence - Reserve a fence for vGPU
-+ * @dev_priv: i915 device private
-+ *
-+ * This function walks the fence regs looking for a free one and remove
-+ * it from the fence_list. It is used to reserve fence for vGPU to use.
-+ */
-+struct drm_i915_fence_reg *
-+i915_reserve_fence(struct drm_i915_private *dev_priv)
-+{
-+	struct drm_i915_fence_reg *fence;
-+	int count;
-+	int ret;
-+
-+	lockdep_assert_held(&dev_priv->drm.struct_mutex);
-+
-+	/* Keep at least one fence available for the display engine. */
-+	count = 0;
-+	list_for_each_entry(fence, &dev_priv->mm.fence_list, link)
-+		count += !fence->pin_count;
-+	if (count <= 1)
-+		return ERR_PTR(-ENOSPC);
-+
-+	fence = fence_find(dev_priv);
-+	if (IS_ERR(fence))
-+		return fence;
-+
-+	if (fence->vma) {
-+		/* Force-remove fence from VMA */
-+		ret = fence_update(fence, NULL);
-+		if (ret)
-+			return ERR_PTR(ret);
-+	}
-+
-+	list_del(&fence->link);
-+	return fence;
-+}
-+
-+/**
-+ * i915_unreserve_fence - Reclaim a reserved fence
-+ * @fence: the fence reg
-+ *
-+ * This function add a reserved fence register from vGPU to the fence_list.
-+ */
-+void i915_unreserve_fence(struct drm_i915_fence_reg *fence)
-+{
-+	lockdep_assert_held(&fence->i915->drm.struct_mutex);
-+
-+	list_add(&fence->link, &fence->i915->mm.fence_list);
-+}
-+
-+/**
-  * i915_gem_revoke_fences - revoke fence state
-  * @dev_priv: i915 device private
-  *
---- linux-4.14/drivers/gpu/drm/i915/i915_gem_gtt.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_gem_gtt.c	2017-12-14 06:39:58.501903627 +0100
-@@ -180,7 +180,7 @@ int intel_sanitize_enable_ppgtt(struct d
- 		return 0;
- 	}
- 
--	if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) {
-+	if (INTEL_GEN(dev_priv) >= 8 && i915_modparams.enable_execlists) {
- 		if (has_full_48bit_ppgtt)
- 			return 3;
- 
-@@ -230,13 +230,13 @@ static gen8_pte_t gen8_pte_encode(dma_ad
- 
- 	switch (level) {
- 	case I915_CACHE_NONE:
--		pte |= PPAT_UNCACHED_INDEX;
-+		pte |= PPAT_UNCACHED;
- 		break;
- 	case I915_CACHE_WT:
--		pte |= PPAT_DISPLAY_ELLC_INDEX;
-+		pte |= PPAT_DISPLAY_ELLC;
- 		break;
- 	default:
--		pte |= PPAT_CACHED_INDEX;
-+		pte |= PPAT_CACHED;
- 		break;
- 	}
- 
-@@ -249,9 +249,9 @@ static gen8_pde_t gen8_pde_encode(const
- 	gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
- 	pde |= addr;
- 	if (level != I915_CACHE_NONE)
--		pde |= PPAT_CACHED_PDE_INDEX;
-+		pde |= PPAT_CACHED_PDE;
- 	else
--		pde |= PPAT_UNCACHED_INDEX;
-+		pde |= PPAT_UNCACHED;
- 	return pde;
- }
- 
-@@ -356,39 +356,86 @@ static gen6_pte_t iris_pte_encode(dma_ad
- 
- static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp)
- {
--	struct page *page;
-+	struct pagevec *pvec = &vm->free_pages;
- 
- 	if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1)))
- 		i915_gem_shrink_all(vm->i915);
- 
--	if (vm->free_pages.nr)
--		return vm->free_pages.pages[--vm->free_pages.nr];
-+	if (likely(pvec->nr))
-+		return pvec->pages[--pvec->nr];
-+
-+	if (!vm->pt_kmap_wc)
-+		return alloc_page(gfp);
-+
-+	/* A placeholder for a specific mutex to guard the WC stash */
-+	lockdep_assert_held(&vm->i915->drm.struct_mutex);
- 
--	page = alloc_page(gfp);
--	if (!page)
-+	/* Look in our global stash of WC pages... */
-+	pvec = &vm->i915->mm.wc_stash;
-+	if (likely(pvec->nr))
-+		return pvec->pages[--pvec->nr];
-+
-+	/* Otherwise batch allocate pages to amoritize cost of set_pages_wc. */
-+	do {
-+		struct page *page;
-+
-+		page = alloc_page(gfp);
-+		if (unlikely(!page))
-+			break;
-+
-+		pvec->pages[pvec->nr++] = page;
-+	} while (pagevec_space(pvec));
-+
-+	if (unlikely(!pvec->nr))
- 		return NULL;
- 
--	if (vm->pt_kmap_wc)
--		set_pages_array_wc(&page, 1);
-+	set_pages_array_wc(pvec->pages, pvec->nr);
- 
--	return page;
-+	return pvec->pages[--pvec->nr];
- }
- 
--static void vm_free_pages_release(struct i915_address_space *vm)
-+static void vm_free_pages_release(struct i915_address_space *vm,
-+				  bool immediate)
- {
--	GEM_BUG_ON(!pagevec_count(&vm->free_pages));
-+	struct pagevec *pvec = &vm->free_pages;
-+
-+	GEM_BUG_ON(!pagevec_count(pvec));
- 
--	if (vm->pt_kmap_wc)
--		set_pages_array_wb(vm->free_pages.pages,
--				   pagevec_count(&vm->free_pages));
-+	if (vm->pt_kmap_wc) {
-+		struct pagevec *stash = &vm->i915->mm.wc_stash;
- 
--	__pagevec_release(&vm->free_pages);
-+		/* When we use WC, first fill up the global stash and then
-+		 * only if full immediately free the overflow.
-+		 */
-+
-+		lockdep_assert_held(&vm->i915->drm.struct_mutex);
-+		if (pagevec_space(stash)) {
-+			do {
-+				stash->pages[stash->nr++] =
-+					pvec->pages[--pvec->nr];
-+				if (!pvec->nr)
-+					return;
-+			} while (pagevec_space(stash));
-+
-+			/* As we have made some room in the VM's free_pages,
-+			 * we can wait for it to fill again. Unless we are
-+			 * inside i915_address_space_fini() and must
-+			 * immediately release the pages!
-+			 */
-+			if (!immediate)
-+				return;
-+		}
-+
-+		set_pages_array_wb(pvec->pages, pvec->nr);
-+	}
-+
-+	__pagevec_release(pvec);
- }
- 
- static void vm_free_page(struct i915_address_space *vm, struct page *page)
- {
- 	if (!pagevec_add(&vm->free_pages, page))
--		vm_free_pages_release(vm);
-+		vm_free_pages_release(vm, false);
- }
- 
- static int __setup_page_dma(struct i915_address_space *vm,
-@@ -434,10 +481,8 @@ static void fill_page_dma(struct i915_ad
- 			  const u64 val)
- {
- 	u64 * const vaddr = kmap_atomic(p->page);
--	int i;
- 
--	for (i = 0; i < 512; i++)
--		vaddr[i] = val;
-+	memset64(vaddr, val, PAGE_SIZE / sizeof(val));
- 
- 	kunmap_atomic(vaddr);
- }
-@@ -452,12 +497,31 @@ static void fill_page_dma_32(struct i915
- static int
- setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
- {
--	return __setup_page_dma(vm, &vm->scratch_page, gfp | __GFP_ZERO);
-+	struct page *page;
-+	dma_addr_t addr;
-+
-+	page = alloc_page(gfp | __GFP_ZERO);
-+	if (unlikely(!page))
-+		return -ENOMEM;
-+
-+	addr = dma_map_page(vm->dma, page, 0, PAGE_SIZE,
-+			    PCI_DMA_BIDIRECTIONAL);
-+	if (unlikely(dma_mapping_error(vm->dma, addr))) {
-+		__free_page(page);
-+		return -ENOMEM;
-+	}
-+
-+	vm->scratch_page.page = page;
-+	vm->scratch_page.daddr = addr;
-+	return 0;
- }
- 
- static void cleanup_scratch_page(struct i915_address_space *vm)
- {
--	cleanup_page_dma(vm, &vm->scratch_page);
-+	struct i915_page_dma *p = &vm->scratch_page;
-+
-+	dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
-+	__free_page(p->page);
- }
- 
- static struct i915_page_table *alloc_pt(struct i915_address_space *vm)
-@@ -1098,19 +1162,22 @@ static int gen8_ppgtt_alloc_pd(struct i9
- 	unsigned int pde;
- 
- 	gen8_for_each_pde(pt, pd, start, length, pde) {
-+		int count = gen8_pte_count(start, length);
-+
- 		if (pt == vm->scratch_pt) {
- 			pt = alloc_pt(vm);
- 			if (IS_ERR(pt))
- 				goto unwind;
- 
--			gen8_initialize_pt(vm, pt);
-+			if (count < GEN8_PTES)
-+				gen8_initialize_pt(vm, pt);
- 
- 			gen8_ppgtt_set_pde(vm, pd, pt, pde);
- 			pd->used_pdes++;
- 			GEM_BUG_ON(pd->used_pdes > I915_PDES);
- 		}
- 
--		pt->used_ptes += gen8_pte_count(start, length);
-+		pt->used_ptes += count;
- 	}
- 	return 0;
- 
-@@ -1333,18 +1400,18 @@ static int gen8_ppgtt_init(struct i915_h
- 		1ULL << 48 :
- 		1ULL << 32;
- 
--	ret = gen8_init_scratch(&ppgtt->base);
--	if (ret) {
--		ppgtt->base.total = 0;
--		return ret;
--	}
--
- 	/* There are only few exceptions for gen >=6. chv and bxt.
- 	 * And we are not sure about the latter so play safe for now.
- 	 */
- 	if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
- 		ppgtt->base.pt_kmap_wc = true;
- 
-+	ret = gen8_init_scratch(&ppgtt->base);
-+	if (ret) {
-+		ppgtt->base.total = 0;
-+		return ret;
-+	}
-+
- 	if (use_4lvl(vm)) {
- 		ret = setup_px(&ppgtt->base, &ppgtt->pml4);
- 		if (ret)
-@@ -1865,7 +1932,7 @@ static void i915_address_space_init(stru
- static void i915_address_space_fini(struct i915_address_space *vm)
- {
- 	if (pagevec_count(&vm->free_pages))
--		vm_free_pages_release(vm);
-+		vm_free_pages_release(vm, true);
- 
- 	i915_gem_timeline_fini(&vm->timeline);
- 	drm_mm_takedown(&vm->mm);
-@@ -1878,12 +1945,12 @@ static void gtt_write_workarounds(struct
- 	 * called on driver load and after a GPU reset, so you can place
- 	 * workarounds here even if they get overwritten by GPU reset.
- 	 */
--	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl */
-+	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
- 	if (IS_BROADWELL(dev_priv))
- 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
- 	else if (IS_CHERRYVIEW(dev_priv))
- 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
--	else if (IS_GEN9_BC(dev_priv))
-+	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
- 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
- 	else if (IS_GEN9_LP(dev_priv))
- 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
-@@ -1896,7 +1963,7 @@ int i915_ppgtt_init_hw(struct drm_i915_p
- 	/* In the case of execlists, PPGTT is enabled by the context descriptor
- 	 * and the PDPs are contained within the context itself.  We don't
- 	 * need to do anything here. */
--	if (i915.enable_execlists)
-+	if (i915_modparams.enable_execlists)
- 		return 0;
- 
- 	if (!USES_PPGTT(dev_priv))
-@@ -2591,6 +2658,7 @@ void i915_ggtt_cleanup_hw(struct drm_i91
- {
- 	struct i915_ggtt *ggtt = &dev_priv->ggtt;
- 	struct i915_vma *vma, *vn;
-+	struct pagevec *pvec;
- 
- 	ggtt->base.closed = true;
- 
-@@ -2614,6 +2682,13 @@ void i915_ggtt_cleanup_hw(struct drm_i91
- 	}
- 
- 	ggtt->base.cleanup(&ggtt->base);
-+
-+	pvec = &dev_priv->mm.wc_stash;
-+	if (pvec->nr) {
-+		set_pages_array_wb(pvec->pages, pvec->nr);
-+		__pagevec_release(pvec);
-+	}
-+
- 	mutex_unlock(&dev_priv->drm.struct_mutex);
- 
- 	arch_phys_wc_del(ggtt->mtrr);
-@@ -2709,13 +2784,13 @@ static int ggtt_probe_common(struct i915
- 	phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
- 
- 	/*
--	 * On BXT writes larger than 64 bit to the GTT pagetable range will be
--	 * dropped. For WC mappings in general we have 64 byte burst writes
--	 * when the WC buffer is flushed, so we can't use it, but have to
-+	 * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
-+	 * will be dropped. For WC mappings in general we have 64 byte burst
-+	 * writes when the WC buffer is flushed, so we can't use it, but have to
- 	 * resort to an uncached mapping. The WC issue is easily caught by the
- 	 * readback check when writing GTT PTE entries.
- 	 */
--	if (IS_GEN9_LP(dev_priv))
-+	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
- 		ggtt->gsm = ioremap_nocache(phys_addr, size);
- 	else
- 		ggtt->gsm = ioremap_wc(phys_addr, size);
-@@ -2735,41 +2810,209 @@ static int ggtt_probe_common(struct i915
- 	return 0;
- }
- 
--static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
-+static struct intel_ppat_entry *
-+__alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8 value)
-+{
-+	struct intel_ppat_entry *entry = &ppat->entries[index];
-+
-+	GEM_BUG_ON(index >= ppat->max_entries);
-+	GEM_BUG_ON(test_bit(index, ppat->used));
-+
-+	entry->ppat = ppat;
-+	entry->value = value;
-+	kref_init(&entry->ref);
-+	set_bit(index, ppat->used);
-+	set_bit(index, ppat->dirty);
-+
-+	return entry;
-+}
-+
-+static void __free_ppat_entry(struct intel_ppat_entry *entry)
-+{
-+	struct intel_ppat *ppat = entry->ppat;
-+	unsigned int index = entry - ppat->entries;
-+
-+	GEM_BUG_ON(index >= ppat->max_entries);
-+	GEM_BUG_ON(!test_bit(index, ppat->used));
-+
-+	entry->value = ppat->clear_value;
-+	clear_bit(index, ppat->used);
-+	set_bit(index, ppat->dirty);
-+}
-+
-+/**
-+ * intel_ppat_get - get a usable PPAT entry
-+ * @i915: i915 device instance
-+ * @value: the PPAT value required by the caller
-+ *
-+ * The function tries to search if there is an existing PPAT entry which
-+ * matches with the required value. If perfectly matched, the existing PPAT
-+ * entry will be used. If only partially matched, it will try to check if
-+ * there is any available PPAT index. If yes, it will allocate a new PPAT
-+ * index for the required entry and update the HW. If not, the partially
-+ * matched entry will be used.
-+ */
-+const struct intel_ppat_entry *
-+intel_ppat_get(struct drm_i915_private *i915, u8 value)
-+{
-+	struct intel_ppat *ppat = &i915->ppat;
-+	struct intel_ppat_entry *entry;
-+	unsigned int scanned, best_score;
-+	int i;
-+
-+	GEM_BUG_ON(!ppat->max_entries);
-+
-+	scanned = best_score = 0;
-+	for_each_set_bit(i, ppat->used, ppat->max_entries) {
-+		unsigned int score;
-+
-+		score = ppat->match(ppat->entries[i].value, value);
-+		if (score > best_score) {
-+			entry = &ppat->entries[i];
-+			if (score == INTEL_PPAT_PERFECT_MATCH) {
-+				kref_get(&entry->ref);
-+				return entry;
-+			}
-+			best_score = score;
-+		}
-+		scanned++;
-+	}
-+
-+	if (scanned == ppat->max_entries) {
-+		if (!best_score)
-+			return ERR_PTR(-ENOSPC);
-+
-+		kref_get(&entry->ref);
-+		return entry;
-+	}
-+
-+	i = find_first_zero_bit(ppat->used, ppat->max_entries);
-+	entry = __alloc_ppat_entry(ppat, i, value);
-+	ppat->update_hw(i915);
-+	return entry;
-+}
-+
-+static void release_ppat(struct kref *kref)
-+{
-+	struct intel_ppat_entry *entry =
-+		container_of(kref, struct intel_ppat_entry, ref);
-+	struct drm_i915_private *i915 = entry->ppat->i915;
-+
-+	__free_ppat_entry(entry);
-+	entry->ppat->update_hw(i915);
-+}
-+
-+/**
-+ * intel_ppat_put - put back the PPAT entry got from intel_ppat_get()
-+ * @entry: an intel PPAT entry
-+ *
-+ * Put back the PPAT entry got from intel_ppat_get(). If the PPAT index of the
-+ * entry is dynamically allocated, its reference count will be decreased. Once
-+ * the reference count becomes into zero, the PPAT index becomes free again.
-+ */
-+void intel_ppat_put(const struct intel_ppat_entry *entry)
-+{
-+	struct intel_ppat *ppat = entry->ppat;
-+	unsigned int index = entry - ppat->entries;
-+
-+	GEM_BUG_ON(!ppat->max_entries);
-+
-+	kref_put(&ppat->entries[index].ref, release_ppat);
-+}
-+
-+static void cnl_private_pat_update_hw(struct drm_i915_private *dev_priv)
-+{
-+	struct intel_ppat *ppat = &dev_priv->ppat;
-+	int i;
-+
-+	for_each_set_bit(i, ppat->dirty, ppat->max_entries) {
-+		I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value);
-+		clear_bit(i, ppat->dirty);
-+	}
-+}
-+
-+static void bdw_private_pat_update_hw(struct drm_i915_private *dev_priv)
-+{
-+	struct intel_ppat *ppat = &dev_priv->ppat;
-+	u64 pat = 0;
-+	int i;
-+
-+	for (i = 0; i < ppat->max_entries; i++)
-+		pat |= GEN8_PPAT(i, ppat->entries[i].value);
-+
-+	bitmap_clear(ppat->dirty, 0, ppat->max_entries);
-+
-+	I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
-+	I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
-+}
-+
-+static unsigned int bdw_private_pat_match(u8 src, u8 dst)
-+{
-+	unsigned int score = 0;
-+	enum {
-+		AGE_MATCH = BIT(0),
-+		TC_MATCH = BIT(1),
-+		CA_MATCH = BIT(2),
-+	};
-+
-+	/* Cache attribute has to be matched. */
-+	if (GEN8_PPAT_GET_CA(src) != GEN8_PPAT_GET_CA(dst))
-+		return 0;
-+
-+	score |= CA_MATCH;
-+
-+	if (GEN8_PPAT_GET_TC(src) == GEN8_PPAT_GET_TC(dst))
-+		score |= TC_MATCH;
-+
-+	if (GEN8_PPAT_GET_AGE(src) == GEN8_PPAT_GET_AGE(dst))
-+		score |= AGE_MATCH;
-+
-+	if (score == (AGE_MATCH | TC_MATCH | CA_MATCH))
-+		return INTEL_PPAT_PERFECT_MATCH;
-+
-+	return score;
-+}
-+
-+static unsigned int chv_private_pat_match(u8 src, u8 dst)
- {
-+	return (CHV_PPAT_GET_SNOOP(src) == CHV_PPAT_GET_SNOOP(dst)) ?
-+		INTEL_PPAT_PERFECT_MATCH : 0;
-+}
-+
-+static void cnl_setup_private_ppat(struct intel_ppat *ppat)
-+{
-+	ppat->max_entries = 8;
-+	ppat->update_hw = cnl_private_pat_update_hw;
-+	ppat->match = bdw_private_pat_match;
-+	ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
-+
- 	/* XXX: spec is unclear if this is still needed for CNL+ */
--	if (!USES_PPGTT(dev_priv)) {
--		I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_UC);
-+	if (!USES_PPGTT(ppat->i915)) {
-+		__alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
- 		return;
- 	}
- 
--	I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC);
--	I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
--	I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
--	I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC);
--	I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
--	I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
--	I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
--	I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
-+	__alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);
-+	__alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
-+	__alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
-+	__alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);
-+	__alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
-+	__alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
-+	__alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
-+	__alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
- }
- 
- /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
-  * bits. When using advanced contexts each context stores its own PAT, but
-  * writing this data shouldn't be harmful even in those cases. */
--static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
-+static void bdw_setup_private_ppat(struct intel_ppat *ppat)
- {
--	u64 pat;
--
--	pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
--	      GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
--	      GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
--	      GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
--	      GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
--	      GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
--	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
--	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
-+	ppat->max_entries = 8;
-+	ppat->update_hw = bdw_private_pat_update_hw;
-+	ppat->match = bdw_private_pat_match;
-+	ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
- 
--	if (!USES_PPGTT(dev_priv))
-+	if (!USES_PPGTT(ppat->i915)) {
- 		/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
- 		 * so RTL will always use the value corresponding to
- 		 * pat_sel = 000".
-@@ -2783,17 +3026,26 @@ static void bdw_setup_private_ppat(struc
- 		 * So we can still hold onto all our assumptions wrt cpu
- 		 * clflushing on LLC machines.
- 		 */
--		pat = GEN8_PPAT(0, GEN8_PPAT_UC);
--
--	/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
--	 * write would work. */
--	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
--	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
--}
-+		__alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
-+		return;
-+	}
- 
--static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
--{
--	u64 pat;
-+	__alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);      /* for normal objects, no eLLC */
-+	__alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);  /* for something pointing to ptes? */
-+	__alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);  /* for scanout with eLLC */
-+	__alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);                      /* Uncached objects, mostly for scanout */
-+	__alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
-+	__alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
-+	__alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
-+	__alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
-+}
-+
-+static void chv_setup_private_ppat(struct intel_ppat *ppat)
-+{
-+	ppat->max_entries = 8;
-+	ppat->update_hw = bdw_private_pat_update_hw;
-+	ppat->match = chv_private_pat_match;
-+	ppat->clear_value = CHV_PPAT_SNOOP;
- 
- 	/*
- 	 * Map WB on BDW to snooped on CHV.
-@@ -2813,17 +3065,15 @@ static void chv_setup_private_ppat(struc
- 	 * Which means we must set the snoop bit in PAT entry 0
- 	 * in order to keep the global status page working.
- 	 */
--	pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
--	      GEN8_PPAT(1, 0) |
--	      GEN8_PPAT(2, 0) |
--	      GEN8_PPAT(3, 0) |
--	      GEN8_PPAT(4, CHV_PPAT_SNOOP) |
--	      GEN8_PPAT(5, CHV_PPAT_SNOOP) |
--	      GEN8_PPAT(6, CHV_PPAT_SNOOP) |
--	      GEN8_PPAT(7, CHV_PPAT_SNOOP);
- 
--	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
--	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
-+	__alloc_ppat_entry(ppat, 0, CHV_PPAT_SNOOP);
-+	__alloc_ppat_entry(ppat, 1, 0);
-+	__alloc_ppat_entry(ppat, 2, 0);
-+	__alloc_ppat_entry(ppat, 3, 0);
-+	__alloc_ppat_entry(ppat, 4, CHV_PPAT_SNOOP);
-+	__alloc_ppat_entry(ppat, 5, CHV_PPAT_SNOOP);
-+	__alloc_ppat_entry(ppat, 6, CHV_PPAT_SNOOP);
-+	__alloc_ppat_entry(ppat, 7, CHV_PPAT_SNOOP);
- }
- 
- static void gen6_gmch_remove(struct i915_address_space *vm)
-@@ -2834,6 +3084,31 @@ static void gen6_gmch_remove(struct i915
- 	cleanup_scratch_page(vm);
- }
- 
-+static void setup_private_pat(struct drm_i915_private *dev_priv)
-+{
-+	struct intel_ppat *ppat = &dev_priv->ppat;
-+	int i;
-+
-+	ppat->i915 = dev_priv;
-+
-+	if (INTEL_GEN(dev_priv) >= 10)
-+		cnl_setup_private_ppat(ppat);
-+	else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
-+		chv_setup_private_ppat(ppat);
-+	else
-+		bdw_setup_private_ppat(ppat);
-+
-+	GEM_BUG_ON(ppat->max_entries > INTEL_MAX_PPAT_ENTRIES);
-+
-+	for_each_clear_bit(i, ppat->used, ppat->max_entries) {
-+		ppat->entries[i].value = ppat->clear_value;
-+		ppat->entries[i].ppat = ppat;
-+		set_bit(i, ppat->dirty);
-+	}
-+
-+	ppat->update_hw(dev_priv);
-+}
-+
- static int gen8_gmch_probe(struct i915_ggtt *ggtt)
- {
- 	struct drm_i915_private *dev_priv = ggtt->base.i915;
-@@ -2866,14 +3141,6 @@ static int gen8_gmch_probe(struct i915_g
- 	}
- 
- 	ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
--
--	if (INTEL_GEN(dev_priv) >= 10)
--		cnl_setup_private_ppat(dev_priv);
--	else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
--		chv_setup_private_ppat(dev_priv);
--	else
--		bdw_setup_private_ppat(dev_priv);
--
- 	ggtt->base.cleanup = gen6_gmch_remove;
- 	ggtt->base.bind_vma = ggtt_bind_vma;
- 	ggtt->base.unbind_vma = ggtt_unbind_vma;
-@@ -2894,6 +3161,8 @@ static int gen8_gmch_probe(struct i915_g
- 
- 	ggtt->invalidate = gen6_ggtt_invalidate;
- 
-+	setup_private_pat(dev_priv);
-+
- 	return ggtt_probe_common(ggtt, size);
- }
- 
-@@ -3014,7 +3283,7 @@ int i915_ggtt_probe_hw(struct drm_i915_p
- 	 * currently don't have any bits spare to pass in this upper
- 	 * restriction!
- 	 */
--	if (HAS_GUC(dev_priv) && i915.enable_guc_loading) {
-+	if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading) {
- 		ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP);
- 		ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
- 	}
-@@ -3151,13 +3420,10 @@ void i915_gem_restore_gtt_mappings(struc
- 	ggtt->base.closed = false;
- 
- 	if (INTEL_GEN(dev_priv) >= 8) {
--		if (INTEL_GEN(dev_priv) >= 10)
--			cnl_setup_private_ppat(dev_priv);
--		else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
--			chv_setup_private_ppat(dev_priv);
--		else
--			bdw_setup_private_ppat(dev_priv);
-+		struct intel_ppat *ppat = &dev_priv->ppat;
- 
-+		bitmap_set(ppat->dirty, 0, ppat->max_entries);
-+		dev_priv->ppat.update_hw(dev_priv);
- 		return;
- 	}
- 
---- linux-4.14/drivers/gpu/drm/i915/i915_gem_gtt.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_gem_gtt.h	2017-12-14 06:39:58.501903627 +0100
-@@ -126,13 +126,13 @@ typedef u64 gen8_ppgtt_pml4e_t;
-  * tables */
- #define GEN8_PDPE_MASK			0x1ff
- 
--#define PPAT_UNCACHED_INDEX		(_PAGE_PWT | _PAGE_PCD)
--#define PPAT_CACHED_PDE_INDEX		0 /* WB LLC */
--#define PPAT_CACHED_INDEX		_PAGE_PAT /* WB LLCeLLC */
--#define PPAT_DISPLAY_ELLC_INDEX		_PAGE_PCD /* WT eLLC */
-+#define PPAT_UNCACHED			(_PAGE_PWT | _PAGE_PCD)
-+#define PPAT_CACHED_PDE			0 /* WB LLC */
-+#define PPAT_CACHED			_PAGE_PAT /* WB LLCeLLC */
-+#define PPAT_DISPLAY_ELLC		_PAGE_PCD /* WT eLLC */
- 
- #define CHV_PPAT_SNOOP			(1<<6)
--#define GEN8_PPAT_AGE(x)		(x<<4)
-+#define GEN8_PPAT_AGE(x)		((x)<<4)
- #define GEN8_PPAT_LLCeLLC		(3<<2)
- #define GEN8_PPAT_LLCELLC		(2<<2)
- #define GEN8_PPAT_LLC			(1<<2)
-@@ -143,6 +143,11 @@ typedef u64 gen8_ppgtt_pml4e_t;
- #define GEN8_PPAT_ELLC_OVERRIDE		(0<<2)
- #define GEN8_PPAT(i, x)			((u64)(x) << ((i) * 8))
- 
-+#define GEN8_PPAT_GET_CA(x) ((x) & 3)
-+#define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2))
-+#define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4))
-+#define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6))
-+
- struct sg_table;
- 
- struct intel_rotation_info {
-@@ -536,6 +541,37 @@ i915_vm_to_ggtt(struct i915_address_spac
- 	return container_of(vm, struct i915_ggtt, base);
- }
- 
-+#define INTEL_MAX_PPAT_ENTRIES 8
-+#define INTEL_PPAT_PERFECT_MATCH (~0U)
-+
-+struct intel_ppat;
-+
-+struct intel_ppat_entry {
-+	struct intel_ppat *ppat;
-+	struct kref ref;
-+	u8 value;
-+};
-+
-+struct intel_ppat {
-+	struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES];
-+	DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES);
-+	DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES);
-+	unsigned int max_entries;
-+	u8 clear_value;
-+	/*
-+	 * Return a score to show how two PPAT values match,
-+	 * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match
-+	 */
-+	unsigned int (*match)(u8 src, u8 dst);
-+	void (*update_hw)(struct drm_i915_private *i915);
-+
-+	struct drm_i915_private *i915;
-+};
-+
-+const struct intel_ppat_entry *
-+intel_ppat_get(struct drm_i915_private *i915, u8 value);
-+void intel_ppat_put(const struct intel_ppat_entry *entry);
-+
- int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915);
- void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915);
- 
---- linux-4.14/drivers/gpu/drm/i915/i915_gem_request.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_gem_request.c	2017-12-14 06:39:58.501903627 +0100
-@@ -1021,12 +1021,28 @@ static bool busywait_stop(unsigned long
- 	return this_cpu != cpu;
- }
- 
--bool __i915_spin_request(const struct drm_i915_gem_request *req,
--			 u32 seqno, int state, unsigned long timeout_us)
-+static bool __i915_spin_request(const struct drm_i915_gem_request *req,
-+				u32 seqno, int state, unsigned long timeout_us)
- {
- 	struct intel_engine_cs *engine = req->engine;
- 	unsigned int irq, cpu;
- 
-+	GEM_BUG_ON(!seqno);
-+
-+	/*
-+	 * Only wait for the request if we know it is likely to complete.
-+	 *
-+	 * We don't track the timestamps around requests, nor the average
-+	 * request length, so we do not have a good indicator that this
-+	 * request will complete within the timeout. What we do know is the
-+	 * order in which requests are executed by the engine and so we can
-+	 * tell if the request has started. If the request hasn't started yet,
-+	 * it is a fair assumption that it will not complete within our
-+	 * relatively short timeout.
-+	 */
-+	if (!i915_seqno_passed(intel_engine_get_seqno(engine), seqno - 1))
-+		return false;
-+
- 	/* When waiting for high frequency requests, e.g. during synchronous
- 	 * rendering split between the CPU and GPU, the finite amount of time
- 	 * required to set up the irq and wait upon it limits the response
-@@ -1040,12 +1056,8 @@ bool __i915_spin_request(const struct dr
- 	irq = atomic_read(&engine->irq_count);
- 	timeout_us += local_clock_us(&cpu);
- 	do {
--		if (seqno != i915_gem_request_global_seqno(req))
--			break;
--
--		if (i915_seqno_passed(intel_engine_get_seqno(req->engine),
--				      seqno))
--			return true;
-+		if (i915_seqno_passed(intel_engine_get_seqno(engine), seqno))
-+			return seqno == i915_gem_request_global_seqno(req);
- 
- 		/* Seqno are meant to be ordered *before* the interrupt. If
- 		 * we see an interrupt without a corresponding seqno advance,
-@@ -1156,7 +1168,7 @@ restart:
- 	GEM_BUG_ON(!i915_sw_fence_signaled(&req->submit));
- 
- 	/* Optimistic short spin before touching IRQs */
--	if (i915_spin_request(req, state, 5))
-+	if (__i915_spin_request(req, wait.seqno, state, 5))
- 		goto complete;
- 
- 	set_current_state(state);
-@@ -1213,7 +1225,7 @@ wakeup:
- 			continue;
- 
- 		/* Only spin if we know the GPU is processing this request */
--		if (i915_spin_request(req, state, 2))
-+		if (__i915_spin_request(req, wait.seqno, state, 2))
- 			break;
- 
- 		if (!intel_wait_check_request(&wait, req)) {
---- linux-4.14/drivers/gpu/drm/i915/i915_gem_request.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_gem_request.h	2017-12-14 06:39:58.501903627 +0100
-@@ -313,26 +313,6 @@ static inline bool i915_seqno_passed(u32
- }
- 
- static inline bool
--__i915_gem_request_started(const struct drm_i915_gem_request *req, u32 seqno)
--{
--	GEM_BUG_ON(!seqno);
--	return i915_seqno_passed(intel_engine_get_seqno(req->engine),
--				 seqno - 1);
--}
--
--static inline bool
--i915_gem_request_started(const struct drm_i915_gem_request *req)
--{
--	u32 seqno;
--
--	seqno = i915_gem_request_global_seqno(req);
--	if (!seqno)
--		return false;
--
--	return __i915_gem_request_started(req, seqno);
--}
--
--static inline bool
- __i915_gem_request_completed(const struct drm_i915_gem_request *req, u32 seqno)
- {
- 	GEM_BUG_ON(!seqno);
-@@ -352,21 +332,6 @@ i915_gem_request_completed(const struct
- 	return __i915_gem_request_completed(req, seqno);
- }
- 
--bool __i915_spin_request(const struct drm_i915_gem_request *request,
--			 u32 seqno, int state, unsigned long timeout_us);
--static inline bool i915_spin_request(const struct drm_i915_gem_request *request,
--				     int state, unsigned long timeout_us)
--{
--	u32 seqno;
--
--	seqno = i915_gem_request_global_seqno(request);
--	if (!seqno)
--		return 0;
--
--	return (__i915_gem_request_started(request, seqno) &&
--		__i915_spin_request(request, seqno, state, timeout_us));
--}
--
- /* We treat requests as fences. This is not be to confused with our
-  * "fence registers" but pipeline synchronisation objects ala GL_ARB_sync.
-  * We use the fences to synchronize access from the CPU with activity on the
---- linux-4.14/drivers/gpu/drm/i915/i915_gem_userptr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_gem_userptr.c	2017-12-14 06:39:58.501903627 +0100
-@@ -399,64 +399,42 @@ struct get_pages_work {
- 	struct task_struct *task;
- };
- 
--#if IS_ENABLED(CONFIG_SWIOTLB)
--#define swiotlb_active() swiotlb_nr_tbl()
--#else
--#define swiotlb_active() 0
--#endif
--
--static int
--st_set_pages(struct sg_table **st, struct page **pvec, int num_pages)
--{
--	struct scatterlist *sg;
--	int ret, n;
--
--	*st = kmalloc(sizeof(**st), GFP_KERNEL);
--	if (*st == NULL)
--		return -ENOMEM;
--
--	if (swiotlb_active()) {
--		ret = sg_alloc_table(*st, num_pages, GFP_KERNEL);
--		if (ret)
--			goto err;
--
--		for_each_sg((*st)->sgl, sg, num_pages, n)
--			sg_set_page(sg, pvec[n], PAGE_SIZE, 0);
--	} else {
--		ret = sg_alloc_table_from_pages(*st, pvec, num_pages,
--						0, num_pages << PAGE_SHIFT,
--						GFP_KERNEL);
--		if (ret)
--			goto err;
--	}
--
--	return 0;
--
--err:
--	kfree(*st);
--	*st = NULL;
--	return ret;
--}
--
- static struct sg_table *
--__i915_gem_userptr_set_pages(struct drm_i915_gem_object *obj,
--			     struct page **pvec, int num_pages)
-+__i915_gem_userptr_alloc_pages(struct drm_i915_gem_object *obj,
-+			       struct page **pvec, int num_pages)
- {
--	struct sg_table *pages;
-+	unsigned int max_segment = i915_sg_segment_size();
-+	struct sg_table *st;
- 	int ret;
- 
--	ret = st_set_pages(&pages, pvec, num_pages);
--	if (ret)
-+	st = kmalloc(sizeof(*st), GFP_KERNEL);
-+	if (!st)
-+		return ERR_PTR(-ENOMEM);
-+
-+alloc_table:
-+	ret = __sg_alloc_table_from_pages(st, pvec, num_pages,
-+					  0, num_pages << PAGE_SHIFT,
-+					  max_segment,
-+					  GFP_KERNEL);
-+	if (ret) {
-+		kfree(st);
- 		return ERR_PTR(ret);
-+	}
- 
--	ret = i915_gem_gtt_prepare_pages(obj, pages);
-+	ret = i915_gem_gtt_prepare_pages(obj, st);
- 	if (ret) {
--		sg_free_table(pages);
--		kfree(pages);
-+		sg_free_table(st);
-+
-+		if (max_segment > PAGE_SIZE) {
-+			max_segment = PAGE_SIZE;
-+			goto alloc_table;
-+		}
-+
-+		kfree(st);
- 		return ERR_PTR(ret);
- 	}
- 
--	return pages;
-+	return st;
- }
- 
- static int
-@@ -540,7 +518,8 @@ __i915_gem_userptr_get_pages_worker(stru
- 		struct sg_table *pages = ERR_PTR(ret);
- 
- 		if (pinned == npages) {
--			pages = __i915_gem_userptr_set_pages(obj, pvec, npages);
-+			pages = __i915_gem_userptr_alloc_pages(obj, pvec,
-+							       npages);
- 			if (!IS_ERR(pages)) {
- 				__i915_gem_object_set_pages(obj, pages);
- 				pinned = 0;
-@@ -661,7 +640,7 @@ i915_gem_userptr_get_pages(struct drm_i9
- 		pages = __i915_gem_userptr_get_pages_schedule(obj);
- 		active = pages == ERR_PTR(-EAGAIN);
- 	} else {
--		pages = __i915_gem_userptr_set_pages(obj, pvec, num_pages);
-+		pages = __i915_gem_userptr_alloc_pages(obj, pvec, num_pages);
- 		active = !IS_ERR(pages);
- 	}
- 	if (active)
-@@ -834,7 +813,9 @@ int i915_gem_init_userptr(struct drm_i91
- 	hash_init(dev_priv->mm_structs);
- 
- 	dev_priv->mm.userptr_wq =
--		alloc_workqueue("i915-userptr-acquire", WQ_HIGHPRI, 0);
-+		alloc_workqueue("i915-userptr-acquire",
-+				WQ_HIGHPRI | WQ_MEM_RECLAIM,
-+				0);
- 	if (!dev_priv->mm.userptr_wq)
- 		return -ENOMEM;
- 
---- linux-4.14/drivers/gpu/drm/i915/i915_gpu_error.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_gpu_error.c	2017-12-14 06:39:58.501903627 +0100
-@@ -396,6 +396,8 @@ static void error_print_context(struct d
- static void error_print_engine(struct drm_i915_error_state_buf *m,
- 			       const struct drm_i915_error_engine *ee)
- {
-+	int n;
-+
- 	err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
- 	err_printf(m, "  START: 0x%08x\n", ee->start);
- 	err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
-@@ -465,8 +467,11 @@ static void error_print_engine(struct dr
- 		   jiffies_to_msecs(jiffies - ee->hangcheck_timestamp));
- 	err_printf(m, "  engine reset count: %u\n", ee->reset_count);
- 
--	error_print_request(m, "  ELSP[0]: ", &ee->execlist[0]);
--	error_print_request(m, "  ELSP[1]: ", &ee->execlist[1]);
-+	for (n = 0; n < ee->num_ports; n++) {
-+		err_printf(m, "  ELSP[%d]:", n);
-+		error_print_request(m, " ", &ee->execlist[n]);
-+	}
-+
- 	error_print_context(m, "  Active context: ", &ee->context);
- }
- 
-@@ -567,7 +572,7 @@ static __always_inline void err_print_pa
- static void err_print_params(struct drm_i915_error_state_buf *m,
- 			     const struct i915_params *p)
- {
--#define PRINT(T, x) err_print_param(m, #x, #T, &p->x);
-+#define PRINT(T, x, ...) err_print_param(m, #x, #T, &p->x);
- 	I915_PARAMS_FOR_EACH(PRINT);
- #undef PRINT
- }
-@@ -861,7 +866,7 @@ void __i915_gpu_state_free(struct kref *
- 	kfree(error->overlay);
- 	kfree(error->display);
- 
--#define FREE(T, x) free_param(#T, &error->params.x);
-+#define FREE(T, x, ...) free_param(#T, &error->params.x);
- 	I915_PARAMS_FOR_EACH(FREE);
- #undef FREE
- 
-@@ -1327,17 +1332,19 @@ static void engine_record_requests(struc
- static void error_record_engine_execlists(struct intel_engine_cs *engine,
- 					  struct drm_i915_error_engine *ee)
- {
--	const struct execlist_port *port = engine->execlist_port;
-+	const struct intel_engine_execlists * const execlists = &engine->execlists;
- 	unsigned int n;
- 
--	for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
--		struct drm_i915_gem_request *rq = port_request(&port[n]);
-+	for (n = 0; n < execlists_num_ports(execlists); n++) {
-+		struct drm_i915_gem_request *rq = port_request(&execlists->port[n]);
- 
- 		if (!rq)
- 			break;
- 
- 		record_request(rq, &ee->execlist[n]);
- 	}
-+
-+	ee->num_ports = n;
- }
- 
- static void record_context(struct drm_i915_error_context *e,
-@@ -1554,7 +1561,7 @@ static void i915_gem_capture_guc_log_buf
- 					    struct i915_gpu_state *error)
- {
- 	/* Capturing log buf contents won't be useful if logging was disabled */
--	if (!dev_priv->guc.log.vma || (i915.guc_log_level < 0))
-+	if (!dev_priv->guc.log.vma || (i915_modparams.guc_log_level < 0))
- 		return;
- 
- 	error->guc_log = i915_error_object_create(dev_priv,
-@@ -1696,8 +1703,8 @@ static int capture(void *data)
- 		ktime_to_timeval(ktime_sub(ktime_get(),
- 					   error->i915->gt.last_init_time));
- 
--	error->params = i915;
--#define DUP(T, x) dup_param(#T, &error->params.x);
-+	error->params = i915_modparams;
-+#define DUP(T, x, ...) dup_param(#T, &error->params.x);
- 	I915_PARAMS_FOR_EACH(DUP);
- #undef DUP
- 
-@@ -1751,7 +1758,7 @@ void i915_capture_error_state(struct drm
- 	struct i915_gpu_state *error;
- 	unsigned long flags;
- 
--	if (!i915.error_capture)
-+	if (!i915_modparams.error_capture)
- 		return;
- 
- 	if (READ_ONCE(dev_priv->gpu_error.first_error))
---- linux-4.14/drivers/gpu/drm/i915/i915_guc_submission.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_guc_submission.c	2017-12-14 06:39:58.501903627 +0100
-@@ -192,13 +192,12 @@ static int __create_doorbell(struct i915
- 
- 	doorbell = __get_doorbell(client);
- 	doorbell->db_status = GUC_DOORBELL_ENABLED;
--	doorbell->cookie = client->doorbell_cookie;
-+	doorbell->cookie = 0;
- 
- 	err = __guc_allocate_doorbell(client->guc, client->stage_id);
--	if (err) {
-+	if (err)
- 		doorbell->db_status = GUC_DOORBELL_DISABLED;
--		doorbell->cookie = 0;
--	}
-+
- 	return err;
- }
- 
-@@ -306,7 +305,7 @@ static void guc_proc_desc_init(struct in
- 	desc->db_base_addr = 0;
- 
- 	desc->stage_id = client->stage_id;
--	desc->wq_size_bytes = client->wq_size;
-+	desc->wq_size_bytes = GUC_WQ_SIZE;
- 	desc->wq_status = WQ_STATUS_ACTIVE;
- 	desc->priority = client->priority;
- }
-@@ -391,8 +390,8 @@ static void guc_stage_desc_init(struct i
- 	desc->db_trigger_cpu = (uintptr_t)__get_doorbell(client);
- 	desc->db_trigger_uk = gfx_addr + client->doorbell_offset;
- 	desc->process_desc = gfx_addr + client->proc_desc_offset;
--	desc->wq_addr = gfx_addr + client->wq_offset;
--	desc->wq_size = client->wq_size;
-+	desc->wq_addr = gfx_addr + GUC_DB_SIZE;
-+	desc->wq_size = GUC_WQ_SIZE;
- 
- 	desc->desc_private = (uintptr_t)client;
- }
-@@ -406,82 +405,23 @@ static void guc_stage_desc_fini(struct i
- 	memset(desc, 0, sizeof(*desc));
- }
- 
--/**
-- * i915_guc_wq_reserve() - reserve space in the GuC's workqueue
-- * @request:	request associated with the commands
-- *
-- * Return:	0 if space is available
-- *		-EAGAIN if space is not currently available
-- *
-- * This function must be called (and must return 0) before a request
-- * is submitted to the GuC via i915_guc_submit() below. Once a result
-- * of 0 has been returned, it must be balanced by a corresponding
-- * call to submit().
-- *
-- * Reservation allows the caller to determine in advance that space
-- * will be available for the next submission before committing resources
-- * to it, and helps avoid late failures with complicated recovery paths.
-- */
--int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
--{
--	const size_t wqi_size = sizeof(struct guc_wq_item);
--	struct i915_guc_client *client = request->i915->guc.execbuf_client;
--	struct guc_process_desc *desc = __get_process_desc(client);
--	u32 freespace;
--	int ret;
--
--	spin_lock_irq(&client->wq_lock);
--	freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
--	freespace -= client->wq_rsvd;
--	if (likely(freespace >= wqi_size)) {
--		client->wq_rsvd += wqi_size;
--		ret = 0;
--	} else {
--		client->no_wq_space++;
--		ret = -EAGAIN;
--	}
--	spin_unlock_irq(&client->wq_lock);
--
--	return ret;
--}
--
--static void guc_client_update_wq_rsvd(struct i915_guc_client *client, int size)
--{
--	unsigned long flags;
--
--	spin_lock_irqsave(&client->wq_lock, flags);
--	client->wq_rsvd += size;
--	spin_unlock_irqrestore(&client->wq_lock, flags);
--}
--
--void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
--{
--	const int wqi_size = sizeof(struct guc_wq_item);
--	struct i915_guc_client *client = request->i915->guc.execbuf_client;
--
--	GEM_BUG_ON(READ_ONCE(client->wq_rsvd) < wqi_size);
--	guc_client_update_wq_rsvd(client, -wqi_size);
--}
--
- /* Construct a Work Item and append it to the GuC's Work Queue */
- static void guc_wq_item_append(struct i915_guc_client *client,
- 			       struct drm_i915_gem_request *rq)
- {
- 	/* wqi_len is in DWords, and does not include the one-word header */
- 	const size_t wqi_size = sizeof(struct guc_wq_item);
--	const u32 wqi_len = wqi_size/sizeof(u32) - 1;
-+	const u32 wqi_len = wqi_size / sizeof(u32) - 1;
- 	struct intel_engine_cs *engine = rq->engine;
-+	struct i915_gem_context *ctx = rq->ctx;
- 	struct guc_process_desc *desc = __get_process_desc(client);
- 	struct guc_wq_item *wqi;
--	u32 freespace, tail, wq_off;
-+	u32 ring_tail, wq_off;
- 
--	/* Free space is guaranteed, see i915_guc_wq_reserve() above */
--	freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
--	GEM_BUG_ON(freespace < wqi_size);
--
--	/* The GuC firmware wants the tail index in QWords, not bytes */
--	tail = intel_ring_set_tail(rq->ring, rq->tail) >> 3;
--	GEM_BUG_ON(tail > WQ_RING_TAIL_MAX);
-+	lockdep_assert_held(&client->wq_lock);
-+
-+	ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);
-+	GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
- 
- 	/* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
- 	 * should not have the case where structure wqi is across page, neither
-@@ -491,29 +431,29 @@ static void guc_wq_item_append(struct i9
- 	 * workqueue buffer dw by dw.
- 	 */
- 	BUILD_BUG_ON(wqi_size != 16);
--	GEM_BUG_ON(client->wq_rsvd < wqi_size);
- 
--	/* postincrement WQ tail for next time */
--	wq_off = client->wq_tail;
-+	/* Free space is guaranteed. */
-+	wq_off = READ_ONCE(desc->tail);
-+	GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
-+			      GUC_WQ_SIZE) < wqi_size);
- 	GEM_BUG_ON(wq_off & (wqi_size - 1));
--	client->wq_tail += wqi_size;
--	client->wq_tail &= client->wq_size - 1;
--	client->wq_rsvd -= wqi_size;
- 
- 	/* WQ starts from the page after doorbell / process_desc */
- 	wqi = client->vaddr + wq_off + GUC_DB_SIZE;
- 
- 	/* Now fill in the 4-word work queue item */
- 	wqi->header = WQ_TYPE_INORDER |
--			(wqi_len << WQ_LEN_SHIFT) |
--			(engine->guc_id << WQ_TARGET_SHIFT) |
--			WQ_NO_WCFLUSH_WAIT;
-+		      (wqi_len << WQ_LEN_SHIFT) |
-+		      (engine->guc_id << WQ_TARGET_SHIFT) |
-+		      WQ_NO_WCFLUSH_WAIT;
- 
--	/* The GuC wants only the low-order word of the context descriptor */
--	wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine);
-+	wqi->context_desc = lower_32_bits(intel_lr_context_descriptor(ctx, engine));
- 
--	wqi->submit_element_info = tail << WQ_RING_TAIL_SHIFT;
-+	wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
- 	wqi->fence_id = rq->global_seqno;
-+
-+	/* Postincrement WQ tail for next time. */
-+	WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
- }
- 
- static void guc_reset_wq(struct i915_guc_client *client)
-@@ -522,106 +462,64 @@ static void guc_reset_wq(struct i915_guc
- 
- 	desc->head = 0;
- 	desc->tail = 0;
--
--	client->wq_tail = 0;
- }
- 
--static int guc_ring_doorbell(struct i915_guc_client *client)
-+static void guc_ring_doorbell(struct i915_guc_client *client)
- {
--	struct guc_process_desc *desc = __get_process_desc(client);
--	union guc_doorbell_qw db_cmp, db_exc, db_ret;
--	union guc_doorbell_qw *db;
--	int attempt = 2, ret = -EAGAIN;
--
--	/* Update the tail so it is visible to GuC */
--	desc->tail = client->wq_tail;
--
--	/* current cookie */
--	db_cmp.db_status = GUC_DOORBELL_ENABLED;
--	db_cmp.cookie = client->doorbell_cookie;
--
--	/* cookie to be updated */
--	db_exc.db_status = GUC_DOORBELL_ENABLED;
--	db_exc.cookie = client->doorbell_cookie + 1;
--	if (db_exc.cookie == 0)
--		db_exc.cookie = 1;
-+	struct guc_doorbell_info *db;
-+	u32 cookie;
- 
--	/* pointer of current doorbell cacheline */
--	db = (union guc_doorbell_qw *)__get_doorbell(client);
-+	lockdep_assert_held(&client->wq_lock);
- 
--	while (attempt--) {
--		/* lets ring the doorbell */
--		db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
--			db_cmp.value_qw, db_exc.value_qw);
--
--		/* if the exchange was successfully executed */
--		if (db_ret.value_qw == db_cmp.value_qw) {
--			/* db was successfully rung */
--			client->doorbell_cookie = db_exc.cookie;
--			ret = 0;
--			break;
--		}
-+	/* pointer of current doorbell cacheline */
-+	db = __get_doorbell(client);
- 
--		/* XXX: doorbell was lost and need to acquire it again */
--		if (db_ret.db_status == GUC_DOORBELL_DISABLED)
--			break;
--
--		DRM_WARN("Cookie mismatch. Expected %d, found %d\n",
--			 db_cmp.cookie, db_ret.cookie);
--
--		/* update the cookie to newly read cookie from GuC */
--		db_cmp.cookie = db_ret.cookie;
--		db_exc.cookie = db_ret.cookie + 1;
--		if (db_exc.cookie == 0)
--			db_exc.cookie = 1;
--	}
-+	/* we're not expecting the doorbell cookie to change behind our back */
-+	cookie = READ_ONCE(db->cookie);
-+	WARN_ON_ONCE(xchg(&db->cookie, cookie + 1) != cookie);
- 
--	return ret;
-+	/* XXX: doorbell was lost and need to acquire it again */
-+	GEM_BUG_ON(db->db_status != GUC_DOORBELL_ENABLED);
- }
- 
- /**
-- * __i915_guc_submit() - Submit commands through GuC
-- * @rq:		request associated with the commands
-- *
-- * The caller must have already called i915_guc_wq_reserve() above with
-- * a result of 0 (success), guaranteeing that there is space in the work
-- * queue for the new request, so enqueuing the item cannot fail.
-- *
-- * Bad Things Will Happen if the caller violates this protocol e.g. calls
-- * submit() when _reserve() says there's no space, or calls _submit()
-- * a different number of times from (successful) calls to _reserve().
-+ * i915_guc_submit() - Submit commands through GuC
-+ * @engine: engine associated with the commands
-  *
-  * The only error here arises if the doorbell hardware isn't functioning
-  * as expected, which really shouln't happen.
-  */
--static void __i915_guc_submit(struct drm_i915_gem_request *rq)
-+static void i915_guc_submit(struct intel_engine_cs *engine)
- {
--	struct drm_i915_private *dev_priv = rq->i915;
--	struct intel_engine_cs *engine = rq->engine;
--	unsigned int engine_id = engine->id;
--	struct intel_guc *guc = &rq->i915->guc;
-+	struct drm_i915_private *dev_priv = engine->i915;
-+	struct intel_guc *guc = &dev_priv->guc;
- 	struct i915_guc_client *client = guc->execbuf_client;
--	unsigned long flags;
--	int b_ret;
-+	struct intel_engine_execlists * const execlists = &engine->execlists;
-+	struct execlist_port *port = execlists->port;
-+	const unsigned int engine_id = engine->id;
-+	unsigned int n;
- 
--	/* WA to flush out the pending GMADR writes to ring buffer. */
--	if (i915_vma_is_map_and_fenceable(rq->ring->vma))
--		POSTING_READ_FW(GUC_STATUS);
-+	for (n = 0; n < ARRAY_SIZE(execlists->port); n++) {
-+		struct drm_i915_gem_request *rq;
-+		unsigned int count;
- 
--	spin_lock_irqsave(&client->wq_lock, flags);
-+		rq = port_unpack(&port[n], &count);
-+		if (rq && count == 0) {
-+			port_set(&port[n], port_pack(rq, ++count));
- 
--	guc_wq_item_append(client, rq);
--	b_ret = guc_ring_doorbell(client);
-+			if (i915_vma_is_map_and_fenceable(rq->ring->vma))
-+				POSTING_READ_FW(GUC_STATUS);
- 
--	client->submissions[engine_id] += 1;
-+			spin_lock(&client->wq_lock);
- 
--	spin_unlock_irqrestore(&client->wq_lock, flags);
--}
-+			guc_wq_item_append(client, rq);
-+			guc_ring_doorbell(client);
- 
--static void i915_guc_submit(struct drm_i915_gem_request *rq)
--{
--	__i915_gem_request_submit(rq);
--	__i915_guc_submit(rq);
-+			client->submissions[engine_id] += 1;
-+
-+			spin_unlock(&client->wq_lock);
-+		}
-+	}
- }
- 
- static void nested_enable_signaling(struct drm_i915_gem_request *rq)
-@@ -655,27 +553,33 @@ static void port_assign(struct execlist_
- 	if (port_isset(port))
- 		i915_gem_request_put(port_request(port));
- 
--	port_set(port, i915_gem_request_get(rq));
-+	port_set(port, port_pack(i915_gem_request_get(rq), port_count(port)));
- 	nested_enable_signaling(rq);
- }
- 
--static bool i915_guc_dequeue(struct intel_engine_cs *engine)
-+static void i915_guc_dequeue(struct intel_engine_cs *engine)
- {
--	struct execlist_port *port = engine->execlist_port;
--	struct drm_i915_gem_request *last = port_request(port);
--	struct rb_node *rb;
-+	struct intel_engine_execlists * const execlists = &engine->execlists;
-+	struct execlist_port *port = execlists->port;
-+	struct drm_i915_gem_request *last = NULL;
-+	const struct execlist_port * const last_port =
-+		&execlists->port[execlists->port_mask];
- 	bool submit = false;
-+	struct rb_node *rb;
-+
-+	if (port_isset(port))
-+		port++;
- 
- 	spin_lock_irq(&engine->timeline->lock);
--	rb = engine->execlist_first;
--	GEM_BUG_ON(rb_first(&engine->execlist_queue) != rb);
-+	rb = execlists->first;
-+	GEM_BUG_ON(rb_first(&execlists->queue) != rb);
- 	while (rb) {
- 		struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
- 		struct drm_i915_gem_request *rq, *rn;
- 
- 		list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
- 			if (last && rq->ctx != last->ctx) {
--				if (port != engine->execlist_port) {
-+				if (port == last_port) {
- 					__list_del_many(&p->requests,
- 							&rq->priotree.link);
- 					goto done;
-@@ -689,50 +593,48 @@ static bool i915_guc_dequeue(struct inte
- 			INIT_LIST_HEAD(&rq->priotree.link);
- 			rq->priotree.priority = INT_MAX;
- 
--			i915_guc_submit(rq);
--			trace_i915_gem_request_in(rq, port_index(port, engine));
-+			__i915_gem_request_submit(rq);
-+			trace_i915_gem_request_in(rq, port_index(port, execlists));
- 			last = rq;
- 			submit = true;
- 		}
- 
- 		rb = rb_next(rb);
--		rb_erase(&p->node, &engine->execlist_queue);
-+		rb_erase(&p->node, &execlists->queue);
- 		INIT_LIST_HEAD(&p->requests);
- 		if (p->priority != I915_PRIORITY_NORMAL)
- 			kmem_cache_free(engine->i915->priorities, p);
- 	}
- done:
--	engine->execlist_first = rb;
--	if (submit)
-+	execlists->first = rb;
-+	if (submit) {
- 		port_assign(port, last);
-+		i915_guc_submit(engine);
-+	}
- 	spin_unlock_irq(&engine->timeline->lock);
--
--	return submit;
- }
- 
- static void i915_guc_irq_handler(unsigned long data)
- {
--	struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
--	struct execlist_port *port = engine->execlist_port;
-+	struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
-+	struct intel_engine_execlists * const execlists = &engine->execlists;
-+	struct execlist_port *port = execlists->port;
-+	const struct execlist_port * const last_port =
-+		&execlists->port[execlists->port_mask];
- 	struct drm_i915_gem_request *rq;
--	bool submit;
- 
--	do {
--		rq = port_request(&port[0]);
--		while (rq && i915_gem_request_completed(rq)) {
--			trace_i915_gem_request_out(rq);
--			i915_gem_request_put(rq);
-+	rq = port_request(&port[0]);
-+	while (rq && i915_gem_request_completed(rq)) {
-+		trace_i915_gem_request_out(rq);
-+		i915_gem_request_put(rq);
- 
--			port[0] = port[1];
--			memset(&port[1], 0, sizeof(port[1]));
-+		execlists_port_complete(execlists, port);
- 
--			rq = port_request(&port[0]);
--		}
-+		rq = port_request(&port[0]);
-+	}
- 
--		submit = false;
--		if (!port_count(&port[1]))
--			submit = i915_guc_dequeue(engine);
--	} while (submit);
-+	if (!port_isset(last_port))
-+		i915_guc_dequeue(engine);
- }
- 
- /*
-@@ -913,8 +815,6 @@ guc_client_alloc(struct drm_i915_private
- 	client->engines = engines;
- 	client->priority = priority;
- 	client->doorbell_id = GUC_DOORBELL_INVALID;
--	client->wq_offset = GUC_DB_SIZE;
--	client->wq_size = GUC_WQ_SIZE;
- 	spin_lock_init(&client->wq_lock);
- 
- 	ret = ida_simple_get(&guc->stage_ids, 0, GUC_MAX_STAGE_DESCRIPTORS,
-@@ -996,28 +896,39 @@ static void guc_client_free(struct i915_
- 	kfree(client);
- }
- 
-+static void guc_policy_init(struct guc_policy *policy)
-+{
-+	policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;
-+	policy->preemption_time = POLICY_DEFAULT_PREEMPTION_TIME_US;
-+	policy->fault_time = POLICY_DEFAULT_FAULT_TIME_US;
-+	policy->policy_flags = 0;
-+}
-+
- static void guc_policies_init(struct guc_policies *policies)
- {
- 	struct guc_policy *policy;
- 	u32 p, i;
- 
--	policies->dpc_promote_time = 500000;
-+	policies->dpc_promote_time = POLICY_DEFAULT_DPC_PROMOTE_TIME_US;
- 	policies->max_num_work_items = POLICY_MAX_NUM_WI;
- 
- 	for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {
- 		for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
- 			policy = &policies->policy[p][i];
- 
--			policy->execution_quantum = 1000000;
--			policy->preemption_time = 500000;
--			policy->fault_time = 250000;
--			policy->policy_flags = 0;
-+			guc_policy_init(policy);
- 		}
- 	}
- 
- 	policies->is_valid = 1;
- }
- 
-+/*
-+ * The first 80 dwords of the register state context, containing the
-+ * execlists and ppgtt registers.
-+ */
-+#define LR_HW_CONTEXT_SIZE	(80 * sizeof(u32))
-+
- static int guc_ads_create(struct intel_guc *guc)
- {
- 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
-@@ -1032,6 +943,8 @@ static int guc_ads_create(struct intel_g
- 	} __packed *blob;
- 	struct intel_engine_cs *engine;
- 	enum intel_engine_id id;
-+	const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE;
-+	const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
- 	u32 base;
- 
- 	GEM_BUG_ON(guc->ads_vma);
-@@ -1062,13 +975,20 @@ static int guc_ads_create(struct intel_g
- 	 * engines after a reset. Here we use the Render ring default
- 	 * context, which must already exist and be pinned in the GGTT,
- 	 * so its address won't change after we've told the GuC where
--	 * to find it.
-+	 * to find it. Note that we have to skip our header (1 page),
-+	 * because our GuC shared data is there.
- 	 */
- 	blob->ads.golden_context_lrca =
--		dev_priv->engine[RCS]->status_page.ggtt_offset;
-+		guc_ggtt_offset(dev_priv->kernel_context->engine[RCS].state) + skipped_offset;
- 
-+	/*
-+	 * The GuC expects us to exclude the portion of the context image that
-+	 * it skips from the size it is to read. It starts reading from after
-+	 * the execlist context (so skipping the first page [PPHWSP] and 80
-+	 * dwords). Weird guc is weird.
-+	 */
- 	for_each_engine(engine, dev_priv, id)
--		blob->ads.eng_state_size[engine->guc_id] = engine->context_size;
-+		blob->ads.eng_state_size[engine->guc_id] = engine->context_size - skipped_size;
- 
- 	base = guc_ggtt_offset(vma);
- 	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
-@@ -1221,6 +1141,19 @@ int i915_guc_submission_enable(struct dr
- 	enum intel_engine_id id;
- 	int err;
- 
-+	/*
-+	 * We're using GuC work items for submitting work through GuC. Since
-+	 * we're coalescing multiple requests from a single context into a
-+	 * single work item prior to assigning it to execlist_port, we can
-+	 * never have more work items than the total number of ports (for all
-+	 * engines). The GuC firmware is controlling the HEAD of work queue,
-+	 * and it is guaranteed that it will remove the work item from the
-+	 * queue before our request is completed.
-+	 */
-+	BUILD_BUG_ON(ARRAY_SIZE(engine->execlists.port) *
-+		     sizeof(struct guc_wq_item) *
-+		     I915_NUM_ENGINES > GUC_WQ_SIZE);
-+
- 	if (!client) {
- 		client = guc_client_alloc(dev_priv,
- 					  INTEL_INFO(dev_priv)->ring_mask,
-@@ -1248,24 +1181,15 @@ int i915_guc_submission_enable(struct dr
- 	guc_interrupts_capture(dev_priv);
- 
- 	for_each_engine(engine, dev_priv, id) {
--		const int wqi_size = sizeof(struct guc_wq_item);
--		struct drm_i915_gem_request *rq;
--
-+		struct intel_engine_execlists * const execlists = &engine->execlists;
- 		/* The tasklet was initialised by execlists, and may be in
- 		 * a state of flux (across a reset) and so we just want to
- 		 * take over the callback without changing any other state
- 		 * in the tasklet.
- 		 */
--		engine->irq_tasklet.func = i915_guc_irq_handler;
-+		execlists->irq_tasklet.func = i915_guc_irq_handler;
- 		clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
--
--		/* Replay the current set of previously submitted requests */
--		spin_lock_irq(&engine->timeline->lock);
--		list_for_each_entry(rq, &engine->timeline->requests, link) {
--			guc_client_update_wq_rsvd(client, wqi_size);
--			__i915_guc_submit(rq);
--		}
--		spin_unlock_irq(&engine->timeline->lock);
-+		tasklet_schedule(&execlists->irq_tasklet);
- 	}
- 
- 	return 0;
-@@ -1310,7 +1234,7 @@ int intel_guc_suspend(struct drm_i915_pr
- 	/* any value greater than GUC_POWER_D0 */
- 	data[1] = GUC_POWER_D1;
- 	/* first page is shared data with GuC */
--	data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
-+	data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN * PAGE_SIZE;
- 
- 	return intel_guc_send(guc, data, ARRAY_SIZE(data));
- }
-@@ -1328,7 +1252,7 @@ int intel_guc_resume(struct drm_i915_pri
- 	if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- 		return 0;
- 
--	if (i915.guc_log_level >= 0)
-+	if (i915_modparams.guc_log_level >= 0)
- 		gen9_enable_guc_interrupts(dev_priv);
- 
- 	ctx = dev_priv->kernel_context;
-@@ -1336,7 +1260,7 @@ int intel_guc_resume(struct drm_i915_pri
- 	data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
- 	data[1] = GUC_POWER_D0;
- 	/* first page is shared data with GuC */
--	data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
-+	data[2] = guc_ggtt_offset(ctx->engine[RCS].state) + LRC_GUCSHR_PN * PAGE_SIZE;
- 
- 	return intel_guc_send(guc, data, ARRAY_SIZE(data));
- }
---- linux-4.14/drivers/gpu/drm/i915/i915_irq.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_irq.c	2017-12-14 06:39:58.502903628 +0100
-@@ -126,7 +126,7 @@ static const u32 hpd_bxt[HPD_NUM_PINS] =
- 	POSTING_READ(GEN8_##type##_IIR(which)); \
- } while (0)
- 
--#define GEN5_IRQ_RESET(type) do { \
-+#define GEN3_IRQ_RESET(type) do { \
- 	I915_WRITE(type##IMR, 0xffffffff); \
- 	POSTING_READ(type##IMR); \
- 	I915_WRITE(type##IER, 0); \
-@@ -136,10 +136,20 @@ static const u32 hpd_bxt[HPD_NUM_PINS] =
- 	POSTING_READ(type##IIR); \
- } while (0)
- 
-+#define GEN2_IRQ_RESET(type) do { \
-+	I915_WRITE16(type##IMR, 0xffff); \
-+	POSTING_READ16(type##IMR); \
-+	I915_WRITE16(type##IER, 0); \
-+	I915_WRITE16(type##IIR, 0xffff); \
-+	POSTING_READ16(type##IIR); \
-+	I915_WRITE16(type##IIR, 0xffff); \
-+	POSTING_READ16(type##IIR); \
-+} while (0)
-+
- /*
-  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
-  */
--static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
-+static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
- 				    i915_reg_t reg)
- {
- 	u32 val = I915_READ(reg);
-@@ -155,20 +165,43 @@ static void gen5_assert_iir_is_zero(stru
- 	POSTING_READ(reg);
- }
- 
-+static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv,
-+				    i915_reg_t reg)
-+{
-+	u16 val = I915_READ16(reg);
-+
-+	if (val == 0)
-+		return;
-+
-+	WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
-+	     i915_mmio_reg_offset(reg), val);
-+	I915_WRITE16(reg, 0xffff);
-+	POSTING_READ16(reg);
-+	I915_WRITE16(reg, 0xffff);
-+	POSTING_READ16(reg);
-+}
-+
- #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
--	gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
-+	gen3_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
- 	I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
- 	I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
- 	POSTING_READ(GEN8_##type##_IMR(which)); \
- } while (0)
- 
--#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
--	gen5_assert_iir_is_zero(dev_priv, type##IIR); \
-+#define GEN3_IRQ_INIT(type, imr_val, ier_val) do { \
-+	gen3_assert_iir_is_zero(dev_priv, type##IIR); \
- 	I915_WRITE(type##IER, (ier_val)); \
- 	I915_WRITE(type##IMR, (imr_val)); \
- 	POSTING_READ(type##IMR); \
- } while (0)
- 
-+#define GEN2_IRQ_INIT(type, imr_val, ier_val) do { \
-+	gen2_assert_iir_is_zero(dev_priv, type##IIR); \
-+	I915_WRITE16(type##IER, (ier_val)); \
-+	I915_WRITE16(type##IMR, (imr_val)); \
-+	POSTING_READ16(type##IMR); \
-+} while (0)
-+
- static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
- static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
- 
-@@ -336,7 +369,7 @@ void gen6_mask_pm_irq(struct drm_i915_pr
- 	__gen6_mask_pm_irq(dev_priv, mask);
- }
- 
--void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
-+static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
- {
- 	i915_reg_t reg = gen6_pm_iir(dev_priv);
- 
-@@ -347,7 +380,7 @@ void gen6_reset_pm_iir(struct drm_i915_p
- 	POSTING_READ(reg);
- }
- 
--void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
-+static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
- {
- 	lockdep_assert_held(&dev_priv->irq_lock);
- 
-@@ -357,7 +390,7 @@ void gen6_enable_pm_irq(struct drm_i915_
- 	/* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
- }
- 
--void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
-+static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
- {
- 	lockdep_assert_held(&dev_priv->irq_lock);
- 
-@@ -405,7 +438,7 @@ void gen6_disable_rps_interrupts(struct
- 	synchronize_irq(dev_priv->drm.irq);
- 
- 	/* Now that we will not be generating any more work, flush any
--	 * outsanding tasks. As we are called on the RPS idle path,
-+	 * outstanding tasks. As we are called on the RPS idle path,
- 	 * we will reset the GPU to minimum frequencies, so the current
- 	 * state of the worker can be discarded.
- 	 */
-@@ -534,62 +567,16 @@ void ibx_display_interrupt_update(struct
- 	POSTING_READ(SDEIMR);
- }
- 
--static void
--__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
--		       u32 enable_mask, u32 status_mask)
--{
--	i915_reg_t reg = PIPESTAT(pipe);
--	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
--
--	lockdep_assert_held(&dev_priv->irq_lock);
--	WARN_ON(!intel_irqs_enabled(dev_priv));
--
--	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
--		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
--		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
--		      pipe_name(pipe), enable_mask, status_mask))
--		return;
--
--	if ((pipestat & enable_mask) == enable_mask)
--		return;
--
--	dev_priv->pipestat_irq_mask[pipe] |= status_mask;
--
--	/* Enable the interrupt, clear any pending status */
--	pipestat |= enable_mask | status_mask;
--	I915_WRITE(reg, pipestat);
--	POSTING_READ(reg);
--}
--
--static void
--__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
--		        u32 enable_mask, u32 status_mask)
-+u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
-+			      enum pipe pipe)
- {
--	i915_reg_t reg = PIPESTAT(pipe);
--	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
-+	u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
-+	u32 enable_mask = status_mask << 16;
- 
- 	lockdep_assert_held(&dev_priv->irq_lock);
--	WARN_ON(!intel_irqs_enabled(dev_priv));
--
--	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
--		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
--		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
--		      pipe_name(pipe), enable_mask, status_mask))
--		return;
--
--	if ((pipestat & enable_mask) == 0)
--		return;
--
--	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
--
--	pipestat &= ~enable_mask;
--	I915_WRITE(reg, pipestat);
--	POSTING_READ(reg);
--}
- 
--static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
--{
--	u32 enable_mask = status_mask << 16;
-+	if (INTEL_GEN(dev_priv) < 5)
-+		goto out;
- 
- 	/*
- 	 * On pipe A we don't support the PSR interrupt yet,
-@@ -612,35 +599,59 @@ static u32 vlv_get_pipestat_enable_mask(
- 	if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
- 		enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
- 
-+out:
-+	WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
-+		  status_mask & ~PIPESTAT_INT_STATUS_MASK,
-+		  "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
-+		  pipe_name(pipe), enable_mask, status_mask);
-+
- 	return enable_mask;
- }
- 
--void
--i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
--		     u32 status_mask)
-+void i915_enable_pipestat(struct drm_i915_private *dev_priv,
-+			  enum pipe pipe, u32 status_mask)
- {
-+	i915_reg_t reg = PIPESTAT(pipe);
- 	u32 enable_mask;
- 
--	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
--		enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
--							   status_mask);
--	else
--		enable_mask = status_mask << 16;
--	__i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
-+	WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
-+		  "pipe %c: status_mask=0x%x\n",
-+		  pipe_name(pipe), status_mask);
-+
-+	lockdep_assert_held(&dev_priv->irq_lock);
-+	WARN_ON(!intel_irqs_enabled(dev_priv));
-+
-+	if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
-+		return;
-+
-+	dev_priv->pipestat_irq_mask[pipe] |= status_mask;
-+	enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
-+
-+	I915_WRITE(reg, enable_mask | status_mask);
-+	POSTING_READ(reg);
- }
- 
--void
--i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
--		      u32 status_mask)
-+void i915_disable_pipestat(struct drm_i915_private *dev_priv,
-+			   enum pipe pipe, u32 status_mask)
- {
-+	i915_reg_t reg = PIPESTAT(pipe);
- 	u32 enable_mask;
- 
--	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
--		enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
--							   status_mask);
--	else
--		enable_mask = status_mask << 16;
--	__i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
-+	WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
-+		  "pipe %c: status_mask=0x%x\n",
-+		  pipe_name(pipe), status_mask);
-+
-+	lockdep_assert_held(&dev_priv->irq_lock);
-+	WARN_ON(!intel_irqs_enabled(dev_priv));
-+
-+	if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
-+		return;
-+
-+	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
-+	enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
-+
-+	I915_WRITE(reg, enable_mask | status_mask);
-+	POSTING_READ(reg);
- }
- 
- /**
-@@ -772,6 +783,57 @@ static u32 g4x_get_vblank_counter(struct
- 	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
- }
- 
-+/*
-+ * On certain encoders on certain platforms, pipe
-+ * scanline register will not work to get the scanline,
-+ * since the timings are driven from the PORT or issues
-+ * with scanline register updates.
-+ * This function will use Framestamp and current
-+ * timestamp registers to calculate the scanline.
-+ */
-+static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
-+{
-+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-+	struct drm_vblank_crtc *vblank =
-+		&crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
-+	const struct drm_display_mode *mode = &vblank->hwmode;
-+	u32 vblank_start = mode->crtc_vblank_start;
-+	u32 vtotal = mode->crtc_vtotal;
-+	u32 htotal = mode->crtc_htotal;
-+	u32 clock = mode->crtc_clock;
-+	u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
-+
-+	/*
-+	 * To avoid the race condition where we might cross into the
-+	 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
-+	 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
-+	 * during the same frame.
-+	 */
-+	do {
-+		/*
-+		 * This field provides read back of the display
-+		 * pipe frame time stamp. The time stamp value
-+		 * is sampled at every start of vertical blank.
-+		 */
-+		scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
-+
-+		/*
-+		 * The TIMESTAMP_CTR register has the current
-+		 * time stamp value.
-+		 */
-+		scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);
-+
-+		scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
-+	} while (scan_post_time != scan_prev_time);
-+
-+	scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
-+					clock), 1000 * htotal);
-+	scanline = min(scanline, vtotal - 1);
-+	scanline = (scanline + vblank_start) % vtotal;
-+
-+	return scanline;
-+}
-+
- /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
- static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
- {
-@@ -788,6 +850,9 @@ static int __intel_get_crtc_scanline(str
- 	vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
- 	mode = &vblank->hwmode;
- 
-+	if (mode->private_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
-+		return __intel_get_crtc_scanline_from_timestamp(crtc);
-+
- 	vtotal = mode->crtc_vtotal;
- 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
- 		vtotal /= 2;
-@@ -1005,6 +1070,8 @@ static void notify_ring(struct intel_eng
- 	spin_lock(&engine->breadcrumbs.irq_lock);
- 	wait = engine->breadcrumbs.irq_wait;
- 	if (wait) {
-+		bool wakeup = engine->irq_seqno_barrier;
-+
- 		/* We use a callback from the dma-fence to submit
- 		 * requests after waiting on our own requests. To
- 		 * ensure minimum delay in queuing the next request to
-@@ -1017,12 +1084,18 @@ static void notify_ring(struct intel_eng
- 		 * and many waiters.
- 		 */
- 		if (i915_seqno_passed(intel_engine_get_seqno(engine),
--				      wait->seqno) &&
--		    !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
--			      &wait->request->fence.flags))
--			rq = i915_gem_request_get(wait->request);
-+				      wait->seqno)) {
-+			struct drm_i915_gem_request *waiter = wait->request;
-+
-+			wakeup = true;
-+			if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
-+				      &waiter->fence.flags) &&
-+			    intel_wait_check_request(wait, waiter))
-+				rq = i915_gem_request_get(waiter);
-+		}
- 
--		wake_up_process(wait->tsk);
-+		if (wakeup)
-+			wake_up_process(wait->tsk);
- 	} else {
- 		__intel_engine_disarm_breadcrumbs(engine);
- 	}
-@@ -1305,10 +1378,11 @@ static void snb_gt_irq_handler(struct dr
- static void
- gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
- {
-+	struct intel_engine_execlists * const execlists = &engine->execlists;
- 	bool tasklet = false;
- 
- 	if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
--		if (port_count(&engine->execlist_port[0])) {
-+		if (port_count(&execlists->port[0])) {
- 			__set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
- 			tasklet = true;
- 		}
-@@ -1316,11 +1390,11 @@ gen8_cs_irq_handler(struct intel_engine_
- 
- 	if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) {
- 		notify_ring(engine);
--		tasklet |= i915.enable_guc_submission;
-+		tasklet |= i915_modparams.enable_guc_submission;
- 	}
- 
- 	if (tasklet)
--		tasklet_hi_schedule(&engine->irq_tasklet);
-+		tasklet_hi_schedule(&execlists->irq_tasklet);
- }
- 
- static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
-@@ -1573,11 +1647,11 @@ static void display_pipe_crc_irq_handler
- 		 * bonkers. So let's just wait for the next vblank and read
- 		 * out the buggy result.
- 		 *
--		 * On CHV sometimes the second CRC is bonkers as well, so
-+		 * On GEN8+ sometimes the second CRC is bonkers as well, so
- 		 * don't trust that one either.
- 		 */
- 		if (pipe_crc->skipped == 0 ||
--		    (IS_CHERRYVIEW(dev_priv) && pipe_crc->skipped == 1)) {
-+		    (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
- 			pipe_crc->skipped++;
- 			spin_unlock(&pipe_crc->lock);
- 			return;
-@@ -1706,8 +1780,21 @@ static void gen9_guc_irq_handler(struct
- 	}
- }
- 
--static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
--					u32 iir, u32 pipe_stats[I915_MAX_PIPES])
-+static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
-+{
-+	enum pipe pipe;
-+
-+	for_each_pipe(dev_priv, pipe) {
-+		I915_WRITE(PIPESTAT(pipe),
-+			   PIPESTAT_INT_STATUS_MASK |
-+			   PIPE_FIFO_UNDERRUN_STATUS);
-+
-+		dev_priv->pipestat_irq_mask[pipe] = 0;
-+	}
-+}
-+
-+static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
-+				  u32 iir, u32 pipe_stats[I915_MAX_PIPES])
- {
- 	int pipe;
- 
-@@ -1720,7 +1807,7 @@ static void valleyview_pipestat_irq_ack(
- 
- 	for_each_pipe(dev_priv, pipe) {
- 		i915_reg_t reg;
--		u32 mask, iir_bit = 0;
-+		u32 status_mask, enable_mask, iir_bit = 0;
- 
- 		/*
- 		 * PIPESTAT bits get signalled even when the interrupt is
-@@ -1731,7 +1818,7 @@ static void valleyview_pipestat_irq_ack(
- 		 */
- 
- 		/* fifo underruns are filterered in the underrun handler. */
--		mask = PIPE_FIFO_UNDERRUN_STATUS;
-+		status_mask = PIPE_FIFO_UNDERRUN_STATUS;
- 
- 		switch (pipe) {
- 		case PIPE_A:
-@@ -1745,25 +1832,92 @@ static void valleyview_pipestat_irq_ack(
- 			break;
- 		}
- 		if (iir & iir_bit)
--			mask |= dev_priv->pipestat_irq_mask[pipe];
-+			status_mask |= dev_priv->pipestat_irq_mask[pipe];
- 
--		if (!mask)
-+		if (!status_mask)
- 			continue;
- 
- 		reg = PIPESTAT(pipe);
--		mask |= PIPESTAT_INT_ENABLE_MASK;
--		pipe_stats[pipe] = I915_READ(reg) & mask;
-+		pipe_stats[pipe] = I915_READ(reg) & status_mask;
-+		enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
- 
- 		/*
- 		 * Clear the PIPE*STAT regs before the IIR
- 		 */
--		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
--					PIPESTAT_INT_STATUS_MASK))
--			I915_WRITE(reg, pipe_stats[pipe]);
-+		if (pipe_stats[pipe])
-+			I915_WRITE(reg, enable_mask | pipe_stats[pipe]);
- 	}
- 	spin_unlock(&dev_priv->irq_lock);
- }
- 
-+static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
-+				      u16 iir, u32 pipe_stats[I915_MAX_PIPES])
-+{
-+	enum pipe pipe;
-+
-+	for_each_pipe(dev_priv, pipe) {
-+		if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
-+			drm_handle_vblank(&dev_priv->drm, pipe);
-+
-+		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
-+			i9xx_pipe_crc_irq_handler(dev_priv, pipe);
-+
-+		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
-+			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
-+	}
-+}
-+
-+static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
-+				      u32 iir, u32 pipe_stats[I915_MAX_PIPES])
-+{
-+	bool blc_event = false;
-+	enum pipe pipe;
-+
-+	for_each_pipe(dev_priv, pipe) {
-+		if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
-+			drm_handle_vblank(&dev_priv->drm, pipe);
-+
-+		if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
-+			blc_event = true;
-+
-+		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
-+			i9xx_pipe_crc_irq_handler(dev_priv, pipe);
-+
-+		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
-+			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
-+	}
-+
-+	if (blc_event || (iir & I915_ASLE_INTERRUPT))
-+		intel_opregion_asle_intr(dev_priv);
-+}
-+
-+static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
-+				      u32 iir, u32 pipe_stats[I915_MAX_PIPES])
-+{
-+	bool blc_event = false;
-+	enum pipe pipe;
-+
-+	for_each_pipe(dev_priv, pipe) {
-+		if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
-+			drm_handle_vblank(&dev_priv->drm, pipe);
-+
-+		if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
-+			blc_event = true;
-+
-+		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
-+			i9xx_pipe_crc_irq_handler(dev_priv, pipe);
-+
-+		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
-+			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
-+	}
-+
-+	if (blc_event || (iir & I915_ASLE_INTERRUPT))
-+		intel_opregion_asle_intr(dev_priv);
-+
-+	if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
-+		gmbus_irq_handler(dev_priv);
-+}
-+
- static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
- 					    u32 pipe_stats[I915_MAX_PIPES])
- {
-@@ -1879,7 +2033,7 @@ static irqreturn_t valleyview_irq_handle
- 
- 		/* Call regardless, as some status bits might not be
- 		 * signalled in iir */
--		valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
-+		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
- 
- 		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
- 			   I915_LPE_PIPE_B_INTERRUPT))
-@@ -1963,7 +2117,7 @@ static irqreturn_t cherryview_irq_handle
- 
- 		/* Call regardless, as some status bits might not be
- 		 * signalled in iir */
--		valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
-+		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
- 
- 		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
- 			   I915_LPE_PIPE_B_INTERRUPT |
-@@ -2860,7 +3014,7 @@ static void ibx_irq_reset(struct drm_i91
- 	if (HAS_PCH_NOP(dev_priv))
- 		return;
- 
--	GEN5_IRQ_RESET(SDE);
-+	GEN3_IRQ_RESET(SDE);
- 
- 	if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
- 		I915_WRITE(SERR_INT, 0xffffffff);
-@@ -2888,15 +3042,13 @@ static void ibx_irq_pre_postinstall(stru
- 
- static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
- {
--	GEN5_IRQ_RESET(GT);
-+	GEN3_IRQ_RESET(GT);
- 	if (INTEL_GEN(dev_priv) >= 6)
--		GEN5_IRQ_RESET(GEN6_PM);
-+		GEN3_IRQ_RESET(GEN6_PM);
- }
- 
- static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
- {
--	enum pipe pipe;
--
- 	if (IS_CHERRYVIEW(dev_priv))
- 		I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
- 	else
-@@ -2905,14 +3057,9 @@ static void vlv_display_irq_reset(struct
- 	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
- 	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
- 
--	for_each_pipe(dev_priv, pipe) {
--		I915_WRITE(PIPESTAT(pipe),
--			   PIPE_FIFO_UNDERRUN_STATUS |
--			   PIPESTAT_INT_STATUS_MASK);
--		dev_priv->pipestat_irq_mask[pipe] = 0;
--	}
-+	i9xx_pipestat_irq_reset(dev_priv);
- 
--	GEN5_IRQ_RESET(VLV_);
-+	GEN3_IRQ_RESET(VLV_);
- 	dev_priv->irq_mask = ~0;
- }
- 
-@@ -2922,8 +3069,7 @@ static void vlv_display_irq_postinstall(
- 	u32 enable_mask;
- 	enum pipe pipe;
- 
--	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
--			PIPE_CRC_DONE_INTERRUPT_STATUS;
-+	pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
- 
- 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
- 	for_each_pipe(dev_priv, pipe)
-@@ -2943,7 +3089,7 @@ static void vlv_display_irq_postinstall(
- 
- 	dev_priv->irq_mask = ~enable_mask;
- 
--	GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
-+	GEN3_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
- }
- 
- /* drm_dma.h hooks
-@@ -2952,9 +3098,10 @@ static void ironlake_irq_reset(struct dr
- {
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 
--	I915_WRITE(HWSTAM, 0xffffffff);
-+	if (IS_GEN5(dev_priv))
-+		I915_WRITE(HWSTAM, 0xffffffff);
- 
--	GEN5_IRQ_RESET(DE);
-+	GEN3_IRQ_RESET(DE);
- 	if (IS_GEN7(dev_priv))
- 		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
- 
-@@ -2963,7 +3110,7 @@ static void ironlake_irq_reset(struct dr
- 	ibx_irq_reset(dev_priv);
- }
- 
--static void valleyview_irq_preinstall(struct drm_device *dev)
-+static void valleyview_irq_reset(struct drm_device *dev)
- {
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 
-@@ -3001,9 +3148,9 @@ static void gen8_irq_reset(struct drm_de
- 						   POWER_DOMAIN_PIPE(pipe)))
- 			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
- 
--	GEN5_IRQ_RESET(GEN8_DE_PORT_);
--	GEN5_IRQ_RESET(GEN8_DE_MISC_);
--	GEN5_IRQ_RESET(GEN8_PCU_);
-+	GEN3_IRQ_RESET(GEN8_DE_PORT_);
-+	GEN3_IRQ_RESET(GEN8_DE_MISC_);
-+	GEN3_IRQ_RESET(GEN8_PCU_);
- 
- 	if (HAS_PCH_SPLIT(dev_priv))
- 		ibx_irq_reset(dev_priv);
-@@ -3037,7 +3184,7 @@ void gen8_irq_power_well_pre_disable(str
- 	synchronize_irq(dev_priv->drm.irq);
- }
- 
--static void cherryview_irq_preinstall(struct drm_device *dev)
-+static void cherryview_irq_reset(struct drm_device *dev)
- {
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 
-@@ -3046,7 +3193,7 @@ static void cherryview_irq_preinstall(st
- 
- 	gen8_gt_irq_reset(dev_priv);
- 
--	GEN5_IRQ_RESET(GEN8_PCU_);
-+	GEN3_IRQ_RESET(GEN8_PCU_);
- 
- 	spin_lock_irq(&dev_priv->irq_lock);
- 	if (dev_priv->display_irqs_enabled)
-@@ -3111,7 +3258,15 @@ static void ibx_hpd_irq_setup(struct drm
- 
- static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
- {
--	u32 hotplug;
-+	u32 val, hotplug;
-+
-+	/* Display WA #1179 WaHardHangonHotPlug: cnp */
-+	if (HAS_PCH_CNP(dev_priv)) {
-+		val = I915_READ(SOUTH_CHICKEN1);
-+		val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
-+		val |= CHASSIS_CLK_REQ_DURATION(0xf);
-+		I915_WRITE(SOUTH_CHICKEN1, val);
-+	}
- 
- 	/* Enable digital hotplug on the PCH */
- 	hotplug = I915_READ(PCH_PORT_HOTPLUG);
-@@ -3238,10 +3393,12 @@ static void ibx_irq_postinstall(struct d
- 
- 	if (HAS_PCH_IBX(dev_priv))
- 		mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
--	else
-+	else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
- 		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
-+	else
-+		mask = SDE_GMBUS_CPT;
- 
--	gen5_assert_iir_is_zero(dev_priv, SDEIIR);
-+	gen3_assert_iir_is_zero(dev_priv, SDEIIR);
- 	I915_WRITE(SDEIMR, ~mask);
- 
- 	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
-@@ -3272,7 +3429,7 @@ static void gen5_gt_irq_postinstall(stru
- 		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
- 	}
- 
--	GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
-+	GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
- 
- 	if (INTEL_GEN(dev_priv) >= 6) {
- 		/*
-@@ -3285,7 +3442,7 @@ static void gen5_gt_irq_postinstall(stru
- 		}
- 
- 		dev_priv->pm_imr = 0xffffffff;
--		GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
-+		GEN3_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
- 	}
- }
- 
-@@ -3296,18 +3453,14 @@ static int ironlake_irq_postinstall(stru
- 
- 	if (INTEL_GEN(dev_priv) >= 7) {
- 		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
--				DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
--				DE_PLANEB_FLIP_DONE_IVB |
--				DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
-+				DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
- 		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
- 			      DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
- 			      DE_DP_A_HOTPLUG_IVB);
- 	} else {
- 		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
--				DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
--				DE_AUX_CHANNEL_A |
--				DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
--				DE_POISON);
-+				DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
-+				DE_PIPEA_CRC_DONE | DE_POISON);
- 		extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
- 			      DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
- 			      DE_DP_A_HOTPLUG);
-@@ -3315,11 +3468,9 @@ static int ironlake_irq_postinstall(stru
- 
- 	dev_priv->irq_mask = ~display_mask;
- 
--	I915_WRITE(HWSTAM, 0xeffe);
--
- 	ibx_irq_pre_postinstall(dev);
- 
--	GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
-+	GEN3_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
- 
- 	gen5_gt_irq_postinstall(dev);
- 
-@@ -3429,15 +3580,13 @@ static void gen8_de_irq_postinstall(stru
- 	enum pipe pipe;
- 
- 	if (INTEL_GEN(dev_priv) >= 9) {
--		de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
--				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
-+		de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
- 		de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
- 				  GEN9_AUX_CHANNEL_D;
- 		if (IS_GEN9_LP(dev_priv))
- 			de_port_masked |= BXT_DE_PORT_GMBUS;
- 	} else {
--		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
--				  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
-+		de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
- 	}
- 
- 	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
-@@ -3460,8 +3609,8 @@ static void gen8_de_irq_postinstall(stru
- 					  dev_priv->de_irq_mask[pipe],
- 					  de_pipe_enables);
- 
--	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
--	GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
-+	GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
-+	GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
- 
- 	if (IS_GEN9_LP(dev_priv))
- 		bxt_hpd_detection_setup(dev_priv);
-@@ -3505,98 +3654,36 @@ static int cherryview_irq_postinstall(st
- 	return 0;
- }
- 
--static void gen8_irq_uninstall(struct drm_device *dev)
--{
--	struct drm_i915_private *dev_priv = to_i915(dev);
--
--	if (!dev_priv)
--		return;
--
--	gen8_irq_reset(dev);
--}
--
--static void valleyview_irq_uninstall(struct drm_device *dev)
--{
--	struct drm_i915_private *dev_priv = to_i915(dev);
--
--	if (!dev_priv)
--		return;
--
--	I915_WRITE(VLV_MASTER_IER, 0);
--	POSTING_READ(VLV_MASTER_IER);
--
--	gen5_gt_irq_reset(dev_priv);
--
--	I915_WRITE(HWSTAM, 0xffffffff);
--
--	spin_lock_irq(&dev_priv->irq_lock);
--	if (dev_priv->display_irqs_enabled)
--		vlv_display_irq_reset(dev_priv);
--	spin_unlock_irq(&dev_priv->irq_lock);
--}
--
--static void cherryview_irq_uninstall(struct drm_device *dev)
--{
--	struct drm_i915_private *dev_priv = to_i915(dev);
--
--	if (!dev_priv)
--		return;
--
--	I915_WRITE(GEN8_MASTER_IRQ, 0);
--	POSTING_READ(GEN8_MASTER_IRQ);
--
--	gen8_gt_irq_reset(dev_priv);
--
--	GEN5_IRQ_RESET(GEN8_PCU_);
--
--	spin_lock_irq(&dev_priv->irq_lock);
--	if (dev_priv->display_irqs_enabled)
--		vlv_display_irq_reset(dev_priv);
--	spin_unlock_irq(&dev_priv->irq_lock);
--}
--
--static void ironlake_irq_uninstall(struct drm_device *dev)
-+static void i8xx_irq_reset(struct drm_device *dev)
- {
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 
--	if (!dev_priv)
--		return;
-+	i9xx_pipestat_irq_reset(dev_priv);
- 
--	ironlake_irq_reset(dev);
--}
--
--static void i8xx_irq_preinstall(struct drm_device * dev)
--{
--	struct drm_i915_private *dev_priv = to_i915(dev);
--	int pipe;
-+	I915_WRITE16(HWSTAM, 0xffff);
- 
--	for_each_pipe(dev_priv, pipe)
--		I915_WRITE(PIPESTAT(pipe), 0);
--	I915_WRITE16(IMR, 0xffff);
--	I915_WRITE16(IER, 0x0);
--	POSTING_READ16(IER);
-+	GEN2_IRQ_RESET();
- }
- 
- static int i8xx_irq_postinstall(struct drm_device *dev)
- {
- 	struct drm_i915_private *dev_priv = to_i915(dev);
-+	u16 enable_mask;
- 
--	I915_WRITE16(EMR,
--		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
-+	I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE |
-+			    I915_ERROR_MEMORY_REFRESH));
- 
- 	/* Unmask the interrupts that we always want on. */
- 	dev_priv->irq_mask =
- 		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
--		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
--		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
--		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
--	I915_WRITE16(IMR, dev_priv->irq_mask);
--
--	I915_WRITE16(IER,
--		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
--		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
--		     I915_USER_INTERRUPT);
--	POSTING_READ16(IER);
-+		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
-+
-+	enable_mask =
-+		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-+		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
-+		I915_USER_INTERRUPT;
-+
-+	GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
- 
- 	/* Interrupt setup is already guaranteed to be single-threaded, this is
- 	 * just to make the assert_spin_locked check happy. */
-@@ -3608,17 +3695,11 @@ static int i8xx_irq_postinstall(struct d
- 	return 0;
- }
- 
--/*
-- * Returns true when a page flip has completed.
-- */
- static irqreturn_t i8xx_irq_handler(int irq, void *arg)
- {
- 	struct drm_device *dev = arg;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
--	u16 iir, new_iir;
--	u32 pipe_stats[2];
--	int pipe;
--	irqreturn_t ret;
-+	irqreturn_t ret = IRQ_NONE;
- 
- 	if (!intel_irqs_enabled(dev_priv))
- 		return IRQ_NONE;
-@@ -3626,96 +3707,50 @@ static irqreturn_t i8xx_irq_handler(int
- 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
- 	disable_rpm_wakeref_asserts(dev_priv);
- 
--	ret = IRQ_NONE;
--	iir = I915_READ16(IIR);
--	if (iir == 0)
--		goto out;
-+	do {
-+		u32 pipe_stats[I915_MAX_PIPES] = {};
-+		u16 iir;
- 
--	while (iir) {
--		/* Can't rely on pipestat interrupt bit in iir as it might
--		 * have been cleared after the pipestat interrupt was received.
--		 * It doesn't set the bit in iir again, but it still produces
--		 * interrupts (for non-MSI).
--		 */
--		spin_lock(&dev_priv->irq_lock);
--		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
--			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
-+		iir = I915_READ16(IIR);
-+		if (iir == 0)
-+			break;
- 
--		for_each_pipe(dev_priv, pipe) {
--			i915_reg_t reg = PIPESTAT(pipe);
--			pipe_stats[pipe] = I915_READ(reg);
-+		ret = IRQ_HANDLED;
- 
--			/*
--			 * Clear the PIPE*STAT regs before the IIR
--			 */
--			if (pipe_stats[pipe] & 0x8000ffff)
--				I915_WRITE(reg, pipe_stats[pipe]);
--		}
--		spin_unlock(&dev_priv->irq_lock);
-+		/* Call regardless, as some status bits might not be
-+		 * signalled in iir */
-+		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
- 
- 		I915_WRITE16(IIR, iir);
--		new_iir = I915_READ16(IIR); /* Flush posted writes */
- 
- 		if (iir & I915_USER_INTERRUPT)
- 			notify_ring(dev_priv->engine[RCS]);
- 
--		for_each_pipe(dev_priv, pipe) {
--			int plane = pipe;
--			if (HAS_FBC(dev_priv))
--				plane = !plane;
--
--			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
--				drm_handle_vblank(&dev_priv->drm, pipe);
--
--			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
--				i9xx_pipe_crc_irq_handler(dev_priv, pipe);
--
--			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
--				intel_cpu_fifo_underrun_irq_handler(dev_priv,
--								    pipe);
--		}
-+		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
-+			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
- 
--		iir = new_iir;
--	}
--	ret = IRQ_HANDLED;
-+		i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
-+	} while (0);
- 
--out:
- 	enable_rpm_wakeref_asserts(dev_priv);
- 
- 	return ret;
- }
- 
--static void i8xx_irq_uninstall(struct drm_device * dev)
-+static void i915_irq_reset(struct drm_device *dev)
- {
- 	struct drm_i915_private *dev_priv = to_i915(dev);
--	int pipe;
--
--	for_each_pipe(dev_priv, pipe) {
--		/* Clear enable bits; then clear status bits */
--		I915_WRITE(PIPESTAT(pipe), 0);
--		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
--	}
--	I915_WRITE16(IMR, 0xffff);
--	I915_WRITE16(IER, 0x0);
--	I915_WRITE16(IIR, I915_READ16(IIR));
--}
--
--static void i915_irq_preinstall(struct drm_device * dev)
--{
--	struct drm_i915_private *dev_priv = to_i915(dev);
--	int pipe;
- 
- 	if (I915_HAS_HOTPLUG(dev_priv)) {
- 		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
- 		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
- 	}
- 
--	I915_WRITE16(HWSTAM, 0xeffe);
--	for_each_pipe(dev_priv, pipe)
--		I915_WRITE(PIPESTAT(pipe), 0);
--	I915_WRITE(IMR, 0xffffffff);
--	I915_WRITE(IER, 0x0);
--	POSTING_READ(IER);
-+	i9xx_pipestat_irq_reset(dev_priv);
-+
-+	I915_WRITE(HWSTAM, 0xffffffff);
-+
-+	GEN3_IRQ_RESET();
- }
- 
- static int i915_irq_postinstall(struct drm_device *dev)
-@@ -3723,15 +3758,14 @@ static int i915_irq_postinstall(struct d
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 	u32 enable_mask;
- 
--	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
-+	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
-+			  I915_ERROR_MEMORY_REFRESH));
- 
- 	/* Unmask the interrupts that we always want on. */
- 	dev_priv->irq_mask =
- 		~(I915_ASLE_INTERRUPT |
- 		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
--		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
--		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
--		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
-+		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
- 
- 	enable_mask =
- 		I915_ASLE_INTERRUPT |
-@@ -3740,20 +3774,13 @@ static int i915_irq_postinstall(struct d
- 		I915_USER_INTERRUPT;
- 
- 	if (I915_HAS_HOTPLUG(dev_priv)) {
--		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
--		POSTING_READ(PORT_HOTPLUG_EN);
--
- 		/* Enable in IER... */
- 		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
- 		/* and unmask in IMR */
- 		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
- 	}
- 
--	I915_WRITE(IMR, dev_priv->irq_mask);
--	I915_WRITE(IER, enable_mask);
--	POSTING_READ(IER);
--
--	i915_enable_asle_pipestat(dev_priv);
-+	GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
- 
- 	/* Interrupt setup is already guaranteed to be single-threaded, this is
- 	 * just to make the assert_spin_locked check happy. */
-@@ -3762,6 +3789,8 @@ static int i915_irq_postinstall(struct d
- 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
- 	spin_unlock_irq(&dev_priv->irq_lock);
- 
-+	i915_enable_asle_pipestat(dev_priv);
-+
- 	return 0;
- }
- 
-@@ -3769,8 +3798,7 @@ static irqreturn_t i915_irq_handler(int
- {
- 	struct drm_device *dev = arg;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
--	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
--	int pipe, ret = IRQ_NONE;
-+	irqreturn_t ret = IRQ_NONE;
- 
- 	if (!intel_irqs_enabled(dev_priv))
- 		return IRQ_NONE;
-@@ -3778,131 +3806,56 @@ static irqreturn_t i915_irq_handler(int
- 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
- 	disable_rpm_wakeref_asserts(dev_priv);
- 
--	iir = I915_READ(IIR);
- 	do {
--		bool irq_received = (iir) != 0;
--		bool blc_event = false;
--
--		/* Can't rely on pipestat interrupt bit in iir as it might
--		 * have been cleared after the pipestat interrupt was received.
--		 * It doesn't set the bit in iir again, but it still produces
--		 * interrupts (for non-MSI).
--		 */
--		spin_lock(&dev_priv->irq_lock);
--		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
--			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
--
--		for_each_pipe(dev_priv, pipe) {
--			i915_reg_t reg = PIPESTAT(pipe);
--			pipe_stats[pipe] = I915_READ(reg);
--
--			/* Clear the PIPE*STAT regs before the IIR */
--			if (pipe_stats[pipe] & 0x8000ffff) {
--				I915_WRITE(reg, pipe_stats[pipe]);
--				irq_received = true;
--			}
--		}
--		spin_unlock(&dev_priv->irq_lock);
-+		u32 pipe_stats[I915_MAX_PIPES] = {};
-+		u32 hotplug_status = 0;
-+		u32 iir;
- 
--		if (!irq_received)
-+		iir = I915_READ(IIR);
-+		if (iir == 0)
- 			break;
- 
--		/* Consume port.  Then clear IIR or we'll miss events */
-+		ret = IRQ_HANDLED;
-+
- 		if (I915_HAS_HOTPLUG(dev_priv) &&
--		    iir & I915_DISPLAY_PORT_INTERRUPT) {
--			u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
--			if (hotplug_status)
--				i9xx_hpd_irq_handler(dev_priv, hotplug_status);
--		}
-+		    iir & I915_DISPLAY_PORT_INTERRUPT)
-+			hotplug_status = i9xx_hpd_irq_ack(dev_priv);
-+
-+		/* Call regardless, as some status bits might not be
-+		 * signalled in iir */
-+		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
- 
- 		I915_WRITE(IIR, iir);
--		new_iir = I915_READ(IIR); /* Flush posted writes */
- 
- 		if (iir & I915_USER_INTERRUPT)
- 			notify_ring(dev_priv->engine[RCS]);
- 
--		for_each_pipe(dev_priv, pipe) {
--			int plane = pipe;
--			if (HAS_FBC(dev_priv))
--				plane = !plane;
--
--			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
--				drm_handle_vblank(&dev_priv->drm, pipe);
--
--			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
--				blc_event = true;
--
--			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
--				i9xx_pipe_crc_irq_handler(dev_priv, pipe);
--
--			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
--				intel_cpu_fifo_underrun_irq_handler(dev_priv,
--								    pipe);
--		}
-+		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
-+			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
- 
--		if (blc_event || (iir & I915_ASLE_INTERRUPT))
--			intel_opregion_asle_intr(dev_priv);
-+		if (hotplug_status)
-+			i9xx_hpd_irq_handler(dev_priv, hotplug_status);
- 
--		/* With MSI, interrupts are only generated when iir
--		 * transitions from zero to nonzero.  If another bit got
--		 * set while we were handling the existing iir bits, then
--		 * we would never get another interrupt.
--		 *
--		 * This is fine on non-MSI as well, as if we hit this path
--		 * we avoid exiting the interrupt handler only to generate
--		 * another one.
--		 *
--		 * Note that for MSI this could cause a stray interrupt report
--		 * if an interrupt landed in the time between writing IIR and
--		 * the posting read.  This should be rare enough to never
--		 * trigger the 99% of 100,000 interrupts test for disabling
--		 * stray interrupts.
--		 */
--		ret = IRQ_HANDLED;
--		iir = new_iir;
--	} while (iir);
-+		i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
-+	} while (0);
- 
- 	enable_rpm_wakeref_asserts(dev_priv);
- 
- 	return ret;
- }
- 
--static void i915_irq_uninstall(struct drm_device * dev)
-+static void i965_irq_reset(struct drm_device *dev)
- {
- 	struct drm_i915_private *dev_priv = to_i915(dev);
--	int pipe;
--
--	if (I915_HAS_HOTPLUG(dev_priv)) {
--		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
--		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
--	}
--
--	I915_WRITE16(HWSTAM, 0xffff);
--	for_each_pipe(dev_priv, pipe) {
--		/* Clear enable bits; then clear status bits */
--		I915_WRITE(PIPESTAT(pipe), 0);
--		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
--	}
--	I915_WRITE(IMR, 0xffffffff);
--	I915_WRITE(IER, 0x0);
--
--	I915_WRITE(IIR, I915_READ(IIR));
--}
--
--static void i965_irq_preinstall(struct drm_device * dev)
--{
--	struct drm_i915_private *dev_priv = to_i915(dev);
--	int pipe;
- 
- 	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
- 	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
- 
--	I915_WRITE(HWSTAM, 0xeffe);
--	for_each_pipe(dev_priv, pipe)
--		I915_WRITE(PIPESTAT(pipe), 0);
--	I915_WRITE(IMR, 0xffffffff);
--	I915_WRITE(IER, 0x0);
--	POSTING_READ(IER);
-+	i9xx_pipestat_irq_reset(dev_priv);
-+
-+	I915_WRITE(HWSTAM, 0xffffffff);
-+
-+	GEN3_IRQ_RESET();
- }
- 
- static int i965_irq_postinstall(struct drm_device *dev)
-@@ -3911,31 +3864,6 @@ static int i965_irq_postinstall(struct d
- 	u32 enable_mask;
- 	u32 error_mask;
- 
--	/* Unmask the interrupts that we always want on. */
--	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
--			       I915_DISPLAY_PORT_INTERRUPT |
--			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
--			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
--			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
--			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
--			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
--
--	enable_mask = ~dev_priv->irq_mask;
--	enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
--			 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
--	enable_mask |= I915_USER_INTERRUPT;
--
--	if (IS_G4X(dev_priv))
--		enable_mask |= I915_BSD_USER_INTERRUPT;
--
--	/* Interrupt setup is already guaranteed to be single-threaded, this is
--	 * just to make the assert_spin_locked check happy. */
--	spin_lock_irq(&dev_priv->irq_lock);
--	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
--	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
--	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
--	spin_unlock_irq(&dev_priv->irq_lock);
--
- 	/*
- 	 * Enable some error detection, note the instruction error mask
- 	 * bit is reserved, so we leave it masked.
-@@ -3951,12 +3879,34 @@ static int i965_irq_postinstall(struct d
- 	}
- 	I915_WRITE(EMR, error_mask);
- 
--	I915_WRITE(IMR, dev_priv->irq_mask);
--	I915_WRITE(IER, enable_mask);
--	POSTING_READ(IER);
-+	/* Unmask the interrupts that we always want on. */
-+	dev_priv->irq_mask =
-+		~(I915_ASLE_INTERRUPT |
-+		  I915_DISPLAY_PORT_INTERRUPT |
-+		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-+		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
-+		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
- 
--	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
--	POSTING_READ(PORT_HOTPLUG_EN);
-+	enable_mask =
-+		I915_ASLE_INTERRUPT |
-+		I915_DISPLAY_PORT_INTERRUPT |
-+		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-+		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
-+		I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
-+		I915_USER_INTERRUPT;
-+
-+	if (IS_G4X(dev_priv))
-+		enable_mask |= I915_BSD_USER_INTERRUPT;
-+
-+	GEN3_IRQ_INIT(, dev_priv->irq_mask, enable_mask);
-+
-+	/* Interrupt setup is already guaranteed to be single-threaded, this is
-+	 * just to make the assert_spin_locked check happy. */
-+	spin_lock_irq(&dev_priv->irq_lock);
-+	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
-+	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
-+	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
-+	spin_unlock_irq(&dev_priv->irq_lock);
- 
- 	i915_enable_asle_pipestat(dev_priv);
- 
-@@ -3992,9 +3942,7 @@ static irqreturn_t i965_irq_handler(int
- {
- 	struct drm_device *dev = arg;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
--	u32 iir, new_iir;
--	u32 pipe_stats[I915_MAX_PIPES];
--	int ret = IRQ_NONE, pipe;
-+	irqreturn_t ret = IRQ_NONE;
- 
- 	if (!intel_irqs_enabled(dev_priv))
- 		return IRQ_NONE;
-@@ -4002,121 +3950,46 @@ static irqreturn_t i965_irq_handler(int
- 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
- 	disable_rpm_wakeref_asserts(dev_priv);
- 
--	iir = I915_READ(IIR);
--
--	for (;;) {
--		bool irq_received = (iir) != 0;
--		bool blc_event = false;
--
--		/* Can't rely on pipestat interrupt bit in iir as it might
--		 * have been cleared after the pipestat interrupt was received.
--		 * It doesn't set the bit in iir again, but it still produces
--		 * interrupts (for non-MSI).
--		 */
--		spin_lock(&dev_priv->irq_lock);
--		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
--			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
--
--		for_each_pipe(dev_priv, pipe) {
--			i915_reg_t reg = PIPESTAT(pipe);
--			pipe_stats[pipe] = I915_READ(reg);
--
--			/*
--			 * Clear the PIPE*STAT regs before the IIR
--			 */
--			if (pipe_stats[pipe] & 0x8000ffff) {
--				I915_WRITE(reg, pipe_stats[pipe]);
--				irq_received = true;
--			}
--		}
--		spin_unlock(&dev_priv->irq_lock);
-+	do {
-+		u32 pipe_stats[I915_MAX_PIPES] = {};
-+		u32 hotplug_status = 0;
-+		u32 iir;
- 
--		if (!irq_received)
-+		iir = I915_READ(IIR);
-+		if (iir == 0)
- 			break;
- 
- 		ret = IRQ_HANDLED;
- 
--		/* Consume port.  Then clear IIR or we'll miss events */
--		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
--			u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
--			if (hotplug_status)
--				i9xx_hpd_irq_handler(dev_priv, hotplug_status);
--		}
-+		if (iir & I915_DISPLAY_PORT_INTERRUPT)
-+			hotplug_status = i9xx_hpd_irq_ack(dev_priv);
-+
-+		/* Call regardless, as some status bits might not be
-+		 * signalled in iir */
-+		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
- 
- 		I915_WRITE(IIR, iir);
--		new_iir = I915_READ(IIR); /* Flush posted writes */
- 
- 		if (iir & I915_USER_INTERRUPT)
- 			notify_ring(dev_priv->engine[RCS]);
-+
- 		if (iir & I915_BSD_USER_INTERRUPT)
- 			notify_ring(dev_priv->engine[VCS]);
- 
--		for_each_pipe(dev_priv, pipe) {
--			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
--				drm_handle_vblank(&dev_priv->drm, pipe);
--
--			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
--				blc_event = true;
--
--			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
--				i9xx_pipe_crc_irq_handler(dev_priv, pipe);
--
--			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
--				intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
--		}
--
--		if (blc_event || (iir & I915_ASLE_INTERRUPT))
--			intel_opregion_asle_intr(dev_priv);
-+		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
-+			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
- 
--		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
--			gmbus_irq_handler(dev_priv);
-+		if (hotplug_status)
-+			i9xx_hpd_irq_handler(dev_priv, hotplug_status);
- 
--		/* With MSI, interrupts are only generated when iir
--		 * transitions from zero to nonzero.  If another bit got
--		 * set while we were handling the existing iir bits, then
--		 * we would never get another interrupt.
--		 *
--		 * This is fine on non-MSI as well, as if we hit this path
--		 * we avoid exiting the interrupt handler only to generate
--		 * another one.
--		 *
--		 * Note that for MSI this could cause a stray interrupt report
--		 * if an interrupt landed in the time between writing IIR and
--		 * the posting read.  This should be rare enough to never
--		 * trigger the 99% of 100,000 interrupts test for disabling
--		 * stray interrupts.
--		 */
--		iir = new_iir;
--	}
-+		i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
-+	} while (0);
- 
- 	enable_rpm_wakeref_asserts(dev_priv);
- 
- 	return ret;
- }
- 
--static void i965_irq_uninstall(struct drm_device * dev)
--{
--	struct drm_i915_private *dev_priv = to_i915(dev);
--	int pipe;
--
--	if (!dev_priv)
--		return;
--
--	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
--	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
--
--	I915_WRITE(HWSTAM, 0xffffffff);
--	for_each_pipe(dev_priv, pipe)
--		I915_WRITE(PIPESTAT(pipe), 0);
--	I915_WRITE(IMR, 0xffffffff);
--	I915_WRITE(IER, 0x0);
--
--	for_each_pipe(dev_priv, pipe)
--		I915_WRITE(PIPESTAT(pipe),
--			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
--	I915_WRITE(IIR, I915_READ(IIR));
--}
--
- /**
-  * intel_irq_init - initializes irq support
-  * @dev_priv: i915 device instance
-@@ -4197,17 +4070,17 @@ void intel_irq_init(struct drm_i915_priv
- 
- 	if (IS_CHERRYVIEW(dev_priv)) {
- 		dev->driver->irq_handler = cherryview_irq_handler;
--		dev->driver->irq_preinstall = cherryview_irq_preinstall;
-+		dev->driver->irq_preinstall = cherryview_irq_reset;
- 		dev->driver->irq_postinstall = cherryview_irq_postinstall;
--		dev->driver->irq_uninstall = cherryview_irq_uninstall;
-+		dev->driver->irq_uninstall = cherryview_irq_reset;
- 		dev->driver->enable_vblank = i965_enable_vblank;
- 		dev->driver->disable_vblank = i965_disable_vblank;
- 		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
- 	} else if (IS_VALLEYVIEW(dev_priv)) {
- 		dev->driver->irq_handler = valleyview_irq_handler;
--		dev->driver->irq_preinstall = valleyview_irq_preinstall;
-+		dev->driver->irq_preinstall = valleyview_irq_reset;
- 		dev->driver->irq_postinstall = valleyview_irq_postinstall;
--		dev->driver->irq_uninstall = valleyview_irq_uninstall;
-+		dev->driver->irq_uninstall = valleyview_irq_reset;
- 		dev->driver->enable_vblank = i965_enable_vblank;
- 		dev->driver->disable_vblank = i965_disable_vblank;
- 		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
-@@ -4215,7 +4088,7 @@ void intel_irq_init(struct drm_i915_priv
- 		dev->driver->irq_handler = gen8_irq_handler;
- 		dev->driver->irq_preinstall = gen8_irq_reset;
- 		dev->driver->irq_postinstall = gen8_irq_postinstall;
--		dev->driver->irq_uninstall = gen8_irq_uninstall;
-+		dev->driver->irq_uninstall = gen8_irq_reset;
- 		dev->driver->enable_vblank = gen8_enable_vblank;
- 		dev->driver->disable_vblank = gen8_disable_vblank;
- 		if (IS_GEN9_LP(dev_priv))
-@@ -4229,29 +4102,29 @@ void intel_irq_init(struct drm_i915_priv
- 		dev->driver->irq_handler = ironlake_irq_handler;
- 		dev->driver->irq_preinstall = ironlake_irq_reset;
- 		dev->driver->irq_postinstall = ironlake_irq_postinstall;
--		dev->driver->irq_uninstall = ironlake_irq_uninstall;
-+		dev->driver->irq_uninstall = ironlake_irq_reset;
- 		dev->driver->enable_vblank = ironlake_enable_vblank;
- 		dev->driver->disable_vblank = ironlake_disable_vblank;
- 		dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
- 	} else {
- 		if (IS_GEN2(dev_priv)) {
--			dev->driver->irq_preinstall = i8xx_irq_preinstall;
-+			dev->driver->irq_preinstall = i8xx_irq_reset;
- 			dev->driver->irq_postinstall = i8xx_irq_postinstall;
- 			dev->driver->irq_handler = i8xx_irq_handler;
--			dev->driver->irq_uninstall = i8xx_irq_uninstall;
-+			dev->driver->irq_uninstall = i8xx_irq_reset;
- 			dev->driver->enable_vblank = i8xx_enable_vblank;
- 			dev->driver->disable_vblank = i8xx_disable_vblank;
- 		} else if (IS_GEN3(dev_priv)) {
--			dev->driver->irq_preinstall = i915_irq_preinstall;
-+			dev->driver->irq_preinstall = i915_irq_reset;
- 			dev->driver->irq_postinstall = i915_irq_postinstall;
--			dev->driver->irq_uninstall = i915_irq_uninstall;
-+			dev->driver->irq_uninstall = i915_irq_reset;
- 			dev->driver->irq_handler = i915_irq_handler;
- 			dev->driver->enable_vblank = i8xx_enable_vblank;
- 			dev->driver->disable_vblank = i8xx_disable_vblank;
- 		} else {
--			dev->driver->irq_preinstall = i965_irq_preinstall;
-+			dev->driver->irq_preinstall = i965_irq_reset;
- 			dev->driver->irq_postinstall = i965_irq_postinstall;
--			dev->driver->irq_uninstall = i965_irq_uninstall;
-+			dev->driver->irq_uninstall = i965_irq_reset;
- 			dev->driver->irq_handler = i965_irq_handler;
- 			dev->driver->enable_vblank = i965_enable_vblank;
- 			dev->driver->disable_vblank = i965_disable_vblank;
---- linux-4.14/drivers/gpu/drm/i915/i915_oa_cflgt2.c.0130~	2017-12-14 06:39:58.502903628 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_oa_cflgt2.c	2017-12-14 06:39:58.502903628 +0100
-@@ -0,0 +1,109 @@
-+/*
-+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
-+ * DO NOT EDIT manually!
-+ *
-+ *
-+ * Copyright (c) 2015 Intel Corporation
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice (including the next
-+ * paragraph) shall be included in all copies or substantial portions of the
-+ * Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-+ * IN THE SOFTWARE.
-+ *
-+ */
-+
-+#include <linux/sysfs.h>
-+
-+#include "i915_drv.h"
-+#include "i915_oa_cflgt2.h"
-+
-+static const struct i915_oa_reg b_counter_config_test_oa[] = {
-+	{ _MMIO(0x2740), 0x00000000 },
-+	{ _MMIO(0x2744), 0x00800000 },
-+	{ _MMIO(0x2714), 0xf0800000 },
-+	{ _MMIO(0x2710), 0x00000000 },
-+	{ _MMIO(0x2724), 0xf0800000 },
-+	{ _MMIO(0x2720), 0x00000000 },
-+	{ _MMIO(0x2770), 0x00000004 },
-+	{ _MMIO(0x2774), 0x00000000 },
-+	{ _MMIO(0x2778), 0x00000003 },
-+	{ _MMIO(0x277c), 0x00000000 },
-+	{ _MMIO(0x2780), 0x00000007 },
-+	{ _MMIO(0x2784), 0x00000000 },
-+	{ _MMIO(0x2788), 0x00100002 },
-+	{ _MMIO(0x278c), 0x0000fff7 },
-+	{ _MMIO(0x2790), 0x00100002 },
-+	{ _MMIO(0x2794), 0x0000ffcf },
-+	{ _MMIO(0x2798), 0x00100082 },
-+	{ _MMIO(0x279c), 0x0000ffef },
-+	{ _MMIO(0x27a0), 0x001000c2 },
-+	{ _MMIO(0x27a4), 0x0000ffe7 },
-+	{ _MMIO(0x27a8), 0x00100001 },
-+	{ _MMIO(0x27ac), 0x0000ffe7 },
-+};
-+
-+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
-+};
-+
-+static const struct i915_oa_reg mux_config_test_oa[] = {
-+	{ _MMIO(0x9840), 0x00000080 },
-+	{ _MMIO(0x9888), 0x11810000 },
-+	{ _MMIO(0x9888), 0x07810013 },
-+	{ _MMIO(0x9888), 0x1f810000 },
-+	{ _MMIO(0x9888), 0x1d810000 },
-+	{ _MMIO(0x9888), 0x1b930040 },
-+	{ _MMIO(0x9888), 0x07e54000 },
-+	{ _MMIO(0x9888), 0x1f908000 },
-+	{ _MMIO(0x9888), 0x11900000 },
-+	{ _MMIO(0x9888), 0x37900000 },
-+	{ _MMIO(0x9888), 0x53900000 },
-+	{ _MMIO(0x9888), 0x45900000 },
-+	{ _MMIO(0x9888), 0x33900000 },
-+};
-+
-+static ssize_t
-+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "1\n");
-+}
-+
-+void
-+i915_perf_load_test_config_cflgt2(struct drm_i915_private *dev_priv)
-+{
-+	strncpy(dev_priv->perf.oa.test_config.uuid,
-+		"74fb4902-d3d3-4237-9e90-cbdc68d0a446",
-+		UUID_STRING_LEN);
-+	dev_priv->perf.oa.test_config.id = 1;
-+
-+	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
-+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
-+
-+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
-+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
-+
-+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
-+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
-+
-+	dev_priv->perf.oa.test_config.sysfs_metric.name = "74fb4902-d3d3-4237-9e90-cbdc68d0a446";
-+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
-+
-+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
-+
-+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
-+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
-+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
-+}
---- linux-4.14/drivers/gpu/drm/i915/i915_oa_cflgt2.h.0130~	2017-12-14 06:39:58.502903628 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_oa_cflgt2.h	2017-12-14 06:39:58.502903628 +0100
-@@ -0,0 +1,34 @@
-+/*
-+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
-+ * DO NOT EDIT manually!
-+ *
-+ *
-+ * Copyright (c) 2015 Intel Corporation
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice (including the next
-+ * paragraph) shall be included in all copies or substantial portions of the
-+ * Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-+ * IN THE SOFTWARE.
-+ *
-+ */
-+
-+#ifndef __I915_OA_CFLGT2_H__
-+#define __I915_OA_CFLGT2_H__
-+
-+extern void i915_perf_load_test_config_cflgt2(struct drm_i915_private *dev_priv);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/i915/i915_params.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_params.c	2017-12-14 06:39:58.502903628 +0100
-@@ -25,235 +25,171 @@
- #include "i915_params.h"
- #include "i915_drv.h"
- 
--struct i915_params i915 __read_mostly = {
--	.modeset = -1,
--	.panel_ignore_lid = 1,
--	.semaphores = -1,
--	.lvds_channel_mode = 0,
--	.panel_use_ssc = -1,
--	.vbt_sdvo_panel_type = -1,
--	.enable_rc6 = -1,
--	.enable_dc = -1,
--	.enable_fbc = -1,
--	.enable_execlists = -1,
--	.enable_hangcheck = true,
--	.enable_ppgtt = -1,
--	.enable_psr = -1,
--	.alpha_support = IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT),
--	.disable_power_well = -1,
--	.enable_ips = 1,
--	.fastboot = 0,
--	.prefault_disable = 0,
--	.load_detect_test = 0,
--	.force_reset_modeset_test = 0,
--	.reset = 2,
--	.error_capture = true,
--	.invert_brightness = 0,
--	.disable_display = 0,
--	.enable_cmd_parser = true,
--	.use_mmio_flip = 0,
--	.mmio_debug = 0,
--	.verbose_state_checks = 1,
--	.nuclear_pageflip = 0,
--	.edp_vswing = 0,
--	.enable_guc_loading = 0,
--	.enable_guc_submission = 0,
--	.guc_log_level = -1,
--	.guc_firmware_path = NULL,
--	.huc_firmware_path = NULL,
--	.enable_dp_mst = true,
--	.inject_load_failure = 0,
--	.enable_dpcd_backlight = false,
--	.enable_gvt = false,
-+#define i915_param_named(name, T, perm, desc) \
-+	module_param_named(name, i915_modparams.name, T, perm); \
-+	MODULE_PARM_DESC(name, desc)
-+#define i915_param_named_unsafe(name, T, perm, desc) \
-+	module_param_named_unsafe(name, i915_modparams.name, T, perm); \
-+	MODULE_PARM_DESC(name, desc)
-+
-+struct i915_params i915_modparams __read_mostly = {
-+#define MEMBER(T, member, value) .member = (value),
-+	I915_PARAMS_FOR_EACH(MEMBER)
-+#undef MEMBER
- };
- 
--module_param_named(modeset, i915.modeset, int, 0400);
--MODULE_PARM_DESC(modeset,
-+i915_param_named(modeset, int, 0400,
- 	"Use kernel modesetting [KMS] (0=disable, "
- 	"1=on, -1=force vga console preference [default])");
- 
--module_param_named_unsafe(panel_ignore_lid, i915.panel_ignore_lid, int, 0600);
--MODULE_PARM_DESC(panel_ignore_lid,
-+i915_param_named_unsafe(panel_ignore_lid, int, 0600,
- 	"Override lid status (0=autodetect, 1=autodetect disabled [default], "
- 	"-1=force lid closed, -2=force lid open)");
- 
--module_param_named_unsafe(semaphores, i915.semaphores, int, 0400);
--MODULE_PARM_DESC(semaphores,
-+i915_param_named_unsafe(semaphores, int, 0400,
- 	"Use semaphores for inter-ring sync "
- 	"(default: -1 (use per-chip defaults))");
- 
--module_param_named_unsafe(enable_rc6, i915.enable_rc6, int, 0400);
--MODULE_PARM_DESC(enable_rc6,
-+i915_param_named_unsafe(enable_rc6, int, 0400,
- 	"Enable power-saving render C-state 6. "
- 	"Different stages can be selected via bitmask values "
- 	"(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
- 	"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
- 	"default: -1 (use per-chip default)");
- 
--module_param_named_unsafe(enable_dc, i915.enable_dc, int, 0400);
--MODULE_PARM_DESC(enable_dc,
-+i915_param_named_unsafe(enable_dc, int, 0400,
- 	"Enable power-saving display C-states. "
- 	"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
- 
--module_param_named_unsafe(enable_fbc, i915.enable_fbc, int, 0600);
--MODULE_PARM_DESC(enable_fbc,
-+i915_param_named_unsafe(enable_fbc, int, 0600,
- 	"Enable frame buffer compression for power savings "
- 	"(default: -1 (use per-chip default))");
- 
--module_param_named_unsafe(lvds_channel_mode, i915.lvds_channel_mode, int, 0400);
--MODULE_PARM_DESC(lvds_channel_mode,
-+i915_param_named_unsafe(lvds_channel_mode, int, 0400,
- 	 "Specify LVDS channel mode "
- 	 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
- 
--module_param_named_unsafe(lvds_use_ssc, i915.panel_use_ssc, int, 0600);
--MODULE_PARM_DESC(lvds_use_ssc,
-+i915_param_named_unsafe(panel_use_ssc, int, 0600,
- 	"Use Spread Spectrum Clock with panels [LVDS/eDP] "
- 	"(default: auto from VBT)");
- 
--module_param_named_unsafe(vbt_sdvo_panel_type, i915.vbt_sdvo_panel_type, int, 0400);
--MODULE_PARM_DESC(vbt_sdvo_panel_type,
-+i915_param_named_unsafe(vbt_sdvo_panel_type, int, 0400,
- 	"Override/Ignore selection of SDVO panel mode in the VBT "
- 	"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
- 
--module_param_named_unsafe(reset, i915.reset, int, 0600);
--MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])");
-+i915_param_named_unsafe(reset, int, 0600,
-+	"Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])");
- 
--module_param_named_unsafe(vbt_firmware, i915.vbt_firmware, charp, 0400);
--MODULE_PARM_DESC(vbt_firmware,
--		 "Load VBT from specified file under /lib/firmware");
-+i915_param_named_unsafe(vbt_firmware, charp, 0400,
-+	"Load VBT from specified file under /lib/firmware");
- 
- #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
--module_param_named(error_capture, i915.error_capture, bool, 0600);
--MODULE_PARM_DESC(error_capture,
-+i915_param_named(error_capture, bool, 0600,
- 	"Record the GPU state following a hang. "
- 	"This information in /sys/class/drm/card<N>/error is vital for "
- 	"triaging and debugging hangs.");
- #endif
- 
--module_param_named_unsafe(enable_hangcheck, i915.enable_hangcheck, bool, 0644);
--MODULE_PARM_DESC(enable_hangcheck,
-+i915_param_named_unsafe(enable_hangcheck, bool, 0644,
- 	"Periodically check GPU activity for detecting hangs. "
- 	"WARNING: Disabling this can cause system wide hangs. "
- 	"(default: true)");
- 
--module_param_named_unsafe(enable_ppgtt, i915.enable_ppgtt, int, 0400);
--MODULE_PARM_DESC(enable_ppgtt,
-+i915_param_named_unsafe(enable_ppgtt, int, 0400,
- 	"Override PPGTT usage. "
- 	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)");
- 
--module_param_named_unsafe(enable_execlists, i915.enable_execlists, int, 0400);
--MODULE_PARM_DESC(enable_execlists,
-+i915_param_named_unsafe(enable_execlists, int, 0400,
- 	"Override execlists usage. "
- 	"(-1=auto [default], 0=disabled, 1=enabled)");
- 
--module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
--MODULE_PARM_DESC(enable_psr, "Enable PSR "
--		 "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
--		 "Default: -1 (use per-chip default)");
-+i915_param_named_unsafe(enable_psr, int, 0600,
-+	"Enable PSR "
-+	"(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
-+	"Default: -1 (use per-chip default)");
- 
--module_param_named_unsafe(alpha_support, i915.alpha_support, bool, 0400);
--MODULE_PARM_DESC(alpha_support,
-+i915_param_named_unsafe(alpha_support, bool, 0400,
- 	"Enable alpha quality driver support for latest hardware. "
- 	"See also CONFIG_DRM_I915_ALPHA_SUPPORT.");
- 
--module_param_named_unsafe(disable_power_well, i915.disable_power_well, int, 0400);
--MODULE_PARM_DESC(disable_power_well,
-+i915_param_named_unsafe(disable_power_well, int, 0400,
- 	"Disable display power wells when possible "
- 	"(-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)");
- 
--module_param_named_unsafe(enable_ips, i915.enable_ips, int, 0600);
--MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
-+i915_param_named_unsafe(enable_ips, int, 0600, "Enable IPS (default: true)");
- 
--module_param_named(fastboot, i915.fastboot, bool, 0600);
--MODULE_PARM_DESC(fastboot,
-+i915_param_named(fastboot, bool, 0600,
- 	"Try to skip unnecessary mode sets at boot time (default: false)");
- 
--module_param_named_unsafe(prefault_disable, i915.prefault_disable, bool, 0600);
--MODULE_PARM_DESC(prefault_disable,
-+i915_param_named_unsafe(prefault_disable, bool, 0600,
- 	"Disable page prefaulting for pread/pwrite/reloc (default:false). "
- 	"For developers only.");
- 
--module_param_named_unsafe(load_detect_test, i915.load_detect_test, bool, 0600);
--MODULE_PARM_DESC(load_detect_test,
-+i915_param_named_unsafe(load_detect_test, bool, 0600,
- 	"Force-enable the VGA load detect code for testing (default:false). "
- 	"For developers only.");
- 
--module_param_named_unsafe(force_reset_modeset_test, i915.force_reset_modeset_test, bool, 0600);
--MODULE_PARM_DESC(force_reset_modeset_test,
-+i915_param_named_unsafe(force_reset_modeset_test, bool, 0600,
- 	"Force a modeset during gpu reset for testing (default:false). "
- 	"For developers only.");
- 
--module_param_named_unsafe(invert_brightness, i915.invert_brightness, int, 0600);
--MODULE_PARM_DESC(invert_brightness,
-+i915_param_named_unsafe(invert_brightness, int, 0600,
- 	"Invert backlight brightness "
- 	"(-1 force normal, 0 machine defaults, 1 force inversion), please "
- 	"report PCI device ID, subsystem vendor and subsystem device ID "
- 	"to dri-devel@lists.freedesktop.org, if your machine needs it. "
- 	"It will then be included in an upcoming module version.");
- 
--module_param_named(disable_display, i915.disable_display, bool, 0400);
--MODULE_PARM_DESC(disable_display, "Disable display (default: false)");
-+i915_param_named(disable_display, bool, 0400,
-+	"Disable display (default: false)");
- 
--module_param_named_unsafe(enable_cmd_parser, i915.enable_cmd_parser, bool, 0400);
--MODULE_PARM_DESC(enable_cmd_parser,
--		 "Enable command parsing (true=enabled [default], false=disabled)");
--
--module_param_named_unsafe(use_mmio_flip, i915.use_mmio_flip, int, 0600);
--MODULE_PARM_DESC(use_mmio_flip,
--		 "use MMIO flips (-1=never, 0=driver discretion [default], 1=always)");
-+i915_param_named_unsafe(enable_cmd_parser, bool, 0400,
-+	"Enable command parsing (true=enabled [default], false=disabled)");
- 
--module_param_named(mmio_debug, i915.mmio_debug, int, 0600);
--MODULE_PARM_DESC(mmio_debug,
-+i915_param_named_unsafe(use_mmio_flip, int, 0600,
-+	"use MMIO flips (-1=never, 0=driver discretion [default], 1=always)");
-+
-+i915_param_named(mmio_debug, int, 0600,
- 	"Enable the MMIO debug code for the first N failures (default: off). "
- 	"This may negatively affect performance.");
- 
--module_param_named(verbose_state_checks, i915.verbose_state_checks, bool, 0600);
--MODULE_PARM_DESC(verbose_state_checks,
-+i915_param_named(verbose_state_checks, bool, 0600,
- 	"Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions.");
- 
--module_param_named_unsafe(nuclear_pageflip, i915.nuclear_pageflip, bool, 0400);
--MODULE_PARM_DESC(nuclear_pageflip,
--		 "Force enable atomic functionality on platforms that don't have full support yet.");
-+i915_param_named_unsafe(nuclear_pageflip, bool, 0400,
-+	"Force enable atomic functionality on platforms that don't have full support yet.");
- 
- /* WA to get away with the default setting in VBT for early platforms.Will be removed */
--module_param_named_unsafe(edp_vswing, i915.edp_vswing, int, 0400);
--MODULE_PARM_DESC(edp_vswing,
--		 "Ignore/Override vswing pre-emph table selection from VBT "
--		 "(0=use value from vbt [default], 1=low power swing(200mV),"
--		 "2=default swing(400mV))");
--
--module_param_named_unsafe(enable_guc_loading, i915.enable_guc_loading, int, 0400);
--MODULE_PARM_DESC(enable_guc_loading,
--		"Enable GuC firmware loading "
--		"(-1=auto, 0=never [default], 1=if available, 2=required)");
--
--module_param_named_unsafe(enable_guc_submission, i915.enable_guc_submission, int, 0400);
--MODULE_PARM_DESC(enable_guc_submission,
--		"Enable GuC submission "
--		"(-1=auto, 0=never [default], 1=if available, 2=required)");
-+i915_param_named_unsafe(edp_vswing, int, 0400,
-+	"Ignore/Override vswing pre-emph table selection from VBT "
-+	"(0=use value from vbt [default], 1=low power swing(200mV),"
-+	"2=default swing(400mV))");
-+
-+i915_param_named_unsafe(enable_guc_loading, int, 0400,
-+	"Enable GuC firmware loading "
-+	"(-1=auto, 0=never [default], 1=if available, 2=required)");
-+
-+i915_param_named_unsafe(enable_guc_submission, int, 0400,
-+	"Enable GuC submission "
-+	"(-1=auto, 0=never [default], 1=if available, 2=required)");
- 
--module_param_named(guc_log_level, i915.guc_log_level, int, 0400);
--MODULE_PARM_DESC(guc_log_level,
-+i915_param_named(guc_log_level, int, 0400,
- 	"GuC firmware logging level (-1:disabled (default), 0-3:enabled)");
- 
--module_param_named_unsafe(guc_firmware_path, i915.guc_firmware_path, charp, 0400);
--MODULE_PARM_DESC(guc_firmware_path,
-+i915_param_named_unsafe(guc_firmware_path, charp, 0400,
- 	"GuC firmware path to use instead of the default one");
- 
--module_param_named_unsafe(huc_firmware_path, i915.huc_firmware_path, charp, 0400);
--MODULE_PARM_DESC(huc_firmware_path,
-+i915_param_named_unsafe(huc_firmware_path, charp, 0400,
- 	"HuC firmware path to use instead of the default one");
- 
--module_param_named_unsafe(enable_dp_mst, i915.enable_dp_mst, bool, 0600);
--MODULE_PARM_DESC(enable_dp_mst,
-+i915_param_named_unsafe(enable_dp_mst, bool, 0600,
- 	"Enable multi-stream transport (MST) for new DisplayPort sinks. (default: true)");
--module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400);
--MODULE_PARM_DESC(inject_load_failure,
-+
-+i915_param_named_unsafe(inject_load_failure, uint, 0400,
- 	"Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)");
--module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 0600);
--MODULE_PARM_DESC(enable_dpcd_backlight,
-+
-+i915_param_named(enable_dpcd_backlight, bool, 0600,
- 	"Enable support for DPCD backlight control (default:false)");
- 
--module_param_named(enable_gvt, i915.enable_gvt, bool, 0400);
--MODULE_PARM_DESC(enable_gvt,
-+i915_param_named(enable_gvt, bool, 0400,
- 	"Enable support for Intel GVT-g graphics virtualization host support(default:false)");
---- linux-4.14/drivers/gpu/drm/i915/i915_params.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_params.h	2017-12-14 06:39:58.502903628 +0100
-@@ -27,56 +27,56 @@
- 
- #include <linux/cache.h> /* for __read_mostly */
- 
--#define I915_PARAMS_FOR_EACH(func) \
--	func(char *, vbt_firmware); \
--	func(int, modeset); \
--	func(int, panel_ignore_lid); \
--	func(int, semaphores); \
--	func(int, lvds_channel_mode); \
--	func(int, panel_use_ssc); \
--	func(int, vbt_sdvo_panel_type); \
--	func(int, enable_rc6); \
--	func(int, enable_dc); \
--	func(int, enable_fbc); \
--	func(int, enable_ppgtt); \
--	func(int, enable_execlists); \
--	func(int, enable_psr); \
--	func(int, disable_power_well); \
--	func(int, enable_ips); \
--	func(int, invert_brightness); \
--	func(int, enable_guc_loading); \
--	func(int, enable_guc_submission); \
--	func(int, guc_log_level); \
--	func(char *, guc_firmware_path); \
--	func(char *, huc_firmware_path); \
--	func(int, use_mmio_flip); \
--	func(int, mmio_debug); \
--	func(int, edp_vswing); \
--	func(int, reset); \
--	func(unsigned int, inject_load_failure); \
-+#define I915_PARAMS_FOR_EACH(param) \
-+	param(char *, vbt_firmware, NULL) \
-+	param(int, modeset, -1) \
-+	param(int, panel_ignore_lid, 1) \
-+	param(int, semaphores, -1) \
-+	param(int, lvds_channel_mode, 0) \
-+	param(int, panel_use_ssc, -1) \
-+	param(int, vbt_sdvo_panel_type, -1) \
-+	param(int, enable_rc6, -1) \
-+	param(int, enable_dc, -1) \
-+	param(int, enable_fbc, -1) \
-+	param(int, enable_ppgtt, -1) \
-+	param(int, enable_execlists, -1) \
-+	param(int, enable_psr, -1) \
-+	param(int, disable_power_well, -1) \
-+	param(int, enable_ips, 1) \
-+	param(int, invert_brightness, 0) \
-+	param(int, enable_guc_loading, 0) \
-+	param(int, enable_guc_submission, 0) \
-+	param(int, guc_log_level, -1) \
-+	param(char *, guc_firmware_path, NULL) \
-+	param(char *, huc_firmware_path, NULL) \
-+	param(int, use_mmio_flip, 0) \
-+	param(int, mmio_debug, 0) \
-+	param(int, edp_vswing, 0) \
-+	param(int, reset, 2) \
-+	param(unsigned int, inject_load_failure, 0) \
- 	/* leave bools at the end to not create holes */ \
--	func(bool, alpha_support); \
--	func(bool, enable_cmd_parser); \
--	func(bool, enable_hangcheck); \
--	func(bool, fastboot); \
--	func(bool, prefault_disable); \
--	func(bool, load_detect_test); \
--	func(bool, force_reset_modeset_test); \
--	func(bool, error_capture); \
--	func(bool, disable_display); \
--	func(bool, verbose_state_checks); \
--	func(bool, nuclear_pageflip); \
--	func(bool, enable_dp_mst); \
--	func(bool, enable_dpcd_backlight); \
--	func(bool, enable_gvt)
-+	param(bool, alpha_support, IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT)) \
-+	param(bool, enable_cmd_parser, true) \
-+	param(bool, enable_hangcheck, true) \
-+	param(bool, fastboot, false) \
-+	param(bool, prefault_disable, false) \
-+	param(bool, load_detect_test, false) \
-+	param(bool, force_reset_modeset_test, false) \
-+	param(bool, error_capture, true) \
-+	param(bool, disable_display, false) \
-+	param(bool, verbose_state_checks, true) \
-+	param(bool, nuclear_pageflip, false) \
-+	param(bool, enable_dp_mst, true) \
-+	param(bool, enable_dpcd_backlight, false) \
-+	param(bool, enable_gvt, false)
- 
--#define MEMBER(T, member) T member
-+#define MEMBER(T, member, ...) T member;
- struct i915_params {
- 	I915_PARAMS_FOR_EACH(MEMBER);
- };
- #undef MEMBER
- 
--extern struct i915_params i915 __read_mostly;
-+extern struct i915_params i915_modparams __read_mostly;
- 
- #endif
- 
---- linux-4.14/drivers/gpu/drm/i915/i915_pci.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_pci.c	2017-12-14 06:39:58.503903629 +0100
-@@ -63,22 +63,23 @@
- 	.hws_needs_physical = 1, \
- 	.unfenced_needs_alignment = 1, \
- 	.ring_mask = RENDER_RING, \
-+	.has_snoop = true, \
- 	GEN_DEFAULT_PIPEOFFSETS, \
- 	CURSOR_OFFSETS
- 
--static const struct intel_device_info intel_i830_info = {
-+static const struct intel_device_info intel_i830_info __initconst = {
- 	GEN2_FEATURES,
- 	.platform = INTEL_I830,
- 	.is_mobile = 1, .cursor_needs_physical = 1,
- 	.num_pipes = 2, /* legal, last one wins */
- };
- 
--static const struct intel_device_info intel_i845g_info = {
-+static const struct intel_device_info intel_i845g_info __initconst = {
- 	GEN2_FEATURES,
- 	.platform = INTEL_I845G,
- };
- 
--static const struct intel_device_info intel_i85x_info = {
-+static const struct intel_device_info intel_i85x_info __initconst = {
- 	GEN2_FEATURES,
- 	.platform = INTEL_I85X, .is_mobile = 1,
- 	.num_pipes = 2, /* legal, last one wins */
-@@ -86,7 +87,7 @@ static const struct intel_device_info in
- 	.has_fbc = 1,
- };
- 
--static const struct intel_device_info intel_i865g_info = {
-+static const struct intel_device_info intel_i865g_info __initconst = {
- 	GEN2_FEATURES,
- 	.platform = INTEL_I865G,
- };
-@@ -95,10 +96,11 @@ static const struct intel_device_info in
- 	.gen = 3, .num_pipes = 2, \
- 	.has_gmch_display = 1, \
- 	.ring_mask = RENDER_RING, \
-+	.has_snoop = true, \
- 	GEN_DEFAULT_PIPEOFFSETS, \
- 	CURSOR_OFFSETS
- 
--static const struct intel_device_info intel_i915g_info = {
-+static const struct intel_device_info intel_i915g_info __initconst = {
- 	GEN3_FEATURES,
- 	.platform = INTEL_I915G, .cursor_needs_physical = 1,
- 	.has_overlay = 1, .overlay_needs_physical = 1,
-@@ -106,7 +108,7 @@ static const struct intel_device_info in
- 	.unfenced_needs_alignment = 1,
- };
- 
--static const struct intel_device_info intel_i915gm_info = {
-+static const struct intel_device_info intel_i915gm_info __initconst = {
- 	GEN3_FEATURES,
- 	.platform = INTEL_I915GM,
- 	.is_mobile = 1,
-@@ -118,7 +120,7 @@ static const struct intel_device_info in
- 	.unfenced_needs_alignment = 1,
- };
- 
--static const struct intel_device_info intel_i945g_info = {
-+static const struct intel_device_info intel_i945g_info __initconst = {
- 	GEN3_FEATURES,
- 	.platform = INTEL_I945G,
- 	.has_hotplug = 1, .cursor_needs_physical = 1,
-@@ -127,7 +129,7 @@ static const struct intel_device_info in
- 	.unfenced_needs_alignment = 1,
- };
- 
--static const struct intel_device_info intel_i945gm_info = {
-+static const struct intel_device_info intel_i945gm_info __initconst = {
- 	GEN3_FEATURES,
- 	.platform = INTEL_I945GM, .is_mobile = 1,
- 	.has_hotplug = 1, .cursor_needs_physical = 1,
-@@ -138,14 +140,14 @@ static const struct intel_device_info in
- 	.unfenced_needs_alignment = 1,
- };
- 
--static const struct intel_device_info intel_g33_info = {
-+static const struct intel_device_info intel_g33_info __initconst = {
- 	GEN3_FEATURES,
- 	.platform = INTEL_G33,
- 	.has_hotplug = 1,
- 	.has_overlay = 1,
- };
- 
--static const struct intel_device_info intel_pineview_info = {
-+static const struct intel_device_info intel_pineview_info __initconst = {
- 	GEN3_FEATURES,
- 	.platform = INTEL_PINEVIEW, .is_mobile = 1,
- 	.has_hotplug = 1,
-@@ -157,33 +159,36 @@ static const struct intel_device_info in
- 	.has_hotplug = 1, \
- 	.has_gmch_display = 1, \
- 	.ring_mask = RENDER_RING, \
-+	.has_snoop = true, \
- 	GEN_DEFAULT_PIPEOFFSETS, \
- 	CURSOR_OFFSETS
- 
--static const struct intel_device_info intel_i965g_info = {
-+static const struct intel_device_info intel_i965g_info __initconst = {
- 	GEN4_FEATURES,
- 	.platform = INTEL_I965G,
- 	.has_overlay = 1,
- 	.hws_needs_physical = 1,
-+	.has_snoop = false,
- };
- 
--static const struct intel_device_info intel_i965gm_info = {
-+static const struct intel_device_info intel_i965gm_info __initconst = {
- 	GEN4_FEATURES,
- 	.platform = INTEL_I965GM,
- 	.is_mobile = 1, .has_fbc = 1,
- 	.has_overlay = 1,
- 	.supports_tv = 1,
- 	.hws_needs_physical = 1,
-+	.has_snoop = false,
- };
- 
--static const struct intel_device_info intel_g45_info = {
-+static const struct intel_device_info intel_g45_info __initconst = {
- 	GEN4_FEATURES,
- 	.platform = INTEL_G45,
- 	.has_pipe_cxsr = 1,
- 	.ring_mask = RENDER_RING | BSD_RING,
- };
- 
--static const struct intel_device_info intel_gm45_info = {
-+static const struct intel_device_info intel_gm45_info __initconst = {
- 	GEN4_FEATURES,
- 	.platform = INTEL_GM45,
- 	.is_mobile = 1, .has_fbc = 1,
-@@ -195,17 +200,17 @@ static const struct intel_device_info in
- #define GEN5_FEATURES \
- 	.gen = 5, .num_pipes = 2, \
- 	.has_hotplug = 1, \
--	.has_gmbus_irq = 1, \
- 	.ring_mask = RENDER_RING | BSD_RING, \
-+	.has_snoop = true, \
- 	GEN_DEFAULT_PIPEOFFSETS, \
- 	CURSOR_OFFSETS
- 
--static const struct intel_device_info intel_ironlake_d_info = {
-+static const struct intel_device_info intel_ironlake_d_info __initconst = {
- 	GEN5_FEATURES,
- 	.platform = INTEL_IRONLAKE,
- };
- 
--static const struct intel_device_info intel_ironlake_m_info = {
-+static const struct intel_device_info intel_ironlake_m_info __initconst = {
- 	GEN5_FEATURES,
- 	.platform = INTEL_IRONLAKE,
- 	.is_mobile = 1, .has_fbc = 1,
-@@ -219,20 +224,38 @@ static const struct intel_device_info in
- 	.has_llc = 1, \
- 	.has_rc6 = 1, \
- 	.has_rc6p = 1, \
--	.has_gmbus_irq = 1, \
- 	.has_aliasing_ppgtt = 1, \
- 	GEN_DEFAULT_PIPEOFFSETS, \
- 	CURSOR_OFFSETS
- 
--static const struct intel_device_info intel_sandybridge_d_info = {
--	GEN6_FEATURES,
--	.platform = INTEL_SANDYBRIDGE,
-+#define SNB_D_PLATFORM \
-+	GEN6_FEATURES, \
-+	.platform = INTEL_SANDYBRIDGE
-+
-+static const struct intel_device_info intel_sandybridge_d_gt1_info __initconst = {
-+	SNB_D_PLATFORM,
-+	.gt = 1,
- };
- 
--static const struct intel_device_info intel_sandybridge_m_info = {
--	GEN6_FEATURES,
--	.platform = INTEL_SANDYBRIDGE,
--	.is_mobile = 1,
-+static const struct intel_device_info intel_sandybridge_d_gt2_info __initconst = {
-+	SNB_D_PLATFORM,
-+	.gt = 2,
-+};
-+
-+#define SNB_M_PLATFORM \
-+	GEN6_FEATURES, \
-+	.platform = INTEL_SANDYBRIDGE, \
-+	.is_mobile = 1
-+
-+
-+static const struct intel_device_info intel_sandybridge_m_gt1_info __initconst = {
-+	SNB_M_PLATFORM,
-+	.gt = 1,
-+};
-+
-+static const struct intel_device_info intel_sandybridge_m_gt2_info __initconst = {
-+	SNB_M_PLATFORM,
-+	.gt = 2,
- };
- 
- #define GEN7_FEATURES  \
-@@ -243,33 +266,51 @@ static const struct intel_device_info in
- 	.has_llc = 1, \
- 	.has_rc6 = 1, \
- 	.has_rc6p = 1, \
--	.has_gmbus_irq = 1, \
- 	.has_aliasing_ppgtt = 1, \
- 	.has_full_ppgtt = 1, \
- 	GEN_DEFAULT_PIPEOFFSETS, \
- 	IVB_CURSOR_OFFSETS
- 
--static const struct intel_device_info intel_ivybridge_d_info = {
--	GEN7_FEATURES,
--	.platform = INTEL_IVYBRIDGE,
--	.has_l3_dpf = 1,
-+#define IVB_D_PLATFORM \
-+	GEN7_FEATURES, \
-+	.platform = INTEL_IVYBRIDGE, \
-+	.has_l3_dpf = 1
-+
-+static const struct intel_device_info intel_ivybridge_d_gt1_info __initconst = {
-+	IVB_D_PLATFORM,
-+	.gt = 1,
- };
- 
--static const struct intel_device_info intel_ivybridge_m_info = {
--	GEN7_FEATURES,
--	.platform = INTEL_IVYBRIDGE,
--	.is_mobile = 1,
--	.has_l3_dpf = 1,
-+static const struct intel_device_info intel_ivybridge_d_gt2_info __initconst = {
-+	IVB_D_PLATFORM,
-+	.gt = 2,
-+};
-+
-+#define IVB_M_PLATFORM \
-+	GEN7_FEATURES, \
-+	.platform = INTEL_IVYBRIDGE, \
-+	.is_mobile = 1, \
-+	.has_l3_dpf = 1
-+
-+static const struct intel_device_info intel_ivybridge_m_gt1_info __initconst = {
-+	IVB_M_PLATFORM,
-+	.gt = 1,
-+};
-+
-+static const struct intel_device_info intel_ivybridge_m_gt2_info __initconst = {
-+	IVB_M_PLATFORM,
-+	.gt = 2,
- };
- 
--static const struct intel_device_info intel_ivybridge_q_info = {
-+static const struct intel_device_info intel_ivybridge_q_info __initconst = {
- 	GEN7_FEATURES,
- 	.platform = INTEL_IVYBRIDGE,
-+	.gt = 2,
- 	.num_pipes = 0, /* legal, last one wins */
- 	.has_l3_dpf = 1,
- };
- 
--static const struct intel_device_info intel_valleyview_info = {
-+static const struct intel_device_info intel_valleyview_info __initconst = {
- 	.platform = INTEL_VALLEYVIEW,
- 	.gen = 7,
- 	.is_lp = 1,
-@@ -277,11 +318,11 @@ static const struct intel_device_info in
- 	.has_psr = 1,
- 	.has_runtime_pm = 1,
- 	.has_rc6 = 1,
--	.has_gmbus_irq = 1,
- 	.has_gmch_display = 1,
- 	.has_hotplug = 1,
- 	.has_aliasing_ppgtt = 1,
- 	.has_full_ppgtt = 1,
-+	.has_snoop = true,
- 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
- 	.display_mmio_offset = VLV_DISPLAY_BASE,
- 	GEN_DEFAULT_PIPEOFFSETS,
-@@ -299,10 +340,24 @@ static const struct intel_device_info in
- 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
- 	.has_runtime_pm = 1
- 
--static const struct intel_device_info intel_haswell_info = {
--	HSW_FEATURES,
--	.platform = INTEL_HASWELL,
--	.has_l3_dpf = 1,
-+#define HSW_PLATFORM \
-+	HSW_FEATURES, \
-+	.platform = INTEL_HASWELL, \
-+	.has_l3_dpf = 1
-+
-+static const struct intel_device_info intel_haswell_gt1_info __initconst = {
-+	HSW_PLATFORM,
-+	.gt = 1,
-+};
-+
-+static const struct intel_device_info intel_haswell_gt2_info __initconst = {
-+	HSW_PLATFORM,
-+	.gt = 2,
-+};
-+
-+static const struct intel_device_info intel_haswell_gt3_info __initconst = {
-+	HSW_PLATFORM,
-+	.gt = 3,
- };
- 
- #define BDW_FEATURES \
-@@ -318,16 +373,31 @@ static const struct intel_device_info in
- 	.gen = 8, \
- 	.platform = INTEL_BROADWELL
- 
--static const struct intel_device_info intel_broadwell_info = {
-+static const struct intel_device_info intel_broadwell_gt1_info __initconst = {
- 	BDW_PLATFORM,
-+	.gt = 1,
- };
- 
--static const struct intel_device_info intel_broadwell_gt3_info = {
-+static const struct intel_device_info intel_broadwell_gt2_info __initconst = {
- 	BDW_PLATFORM,
-+	.gt = 2,
-+};
-+
-+static const struct intel_device_info intel_broadwell_rsvd_info __initconst = {
-+	BDW_PLATFORM,
-+	.gt = 3,
-+	/* According to the device ID those devices are GT3, they were
-+	 * previously treated as not GT3, keep it like that.
-+	 */
-+};
-+
-+static const struct intel_device_info intel_broadwell_gt3_info __initconst = {
-+	BDW_PLATFORM,
-+	.gt = 3,
- 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
- };
- 
--static const struct intel_device_info intel_cherryview_info = {
-+static const struct intel_device_info intel_cherryview_info __initconst = {
- 	.gen = 8, .num_pipes = 3,
- 	.has_hotplug = 1,
- 	.is_lp = 1,
-@@ -338,12 +408,12 @@ static const struct intel_device_info in
- 	.has_runtime_pm = 1,
- 	.has_resource_streamer = 1,
- 	.has_rc6 = 1,
--	.has_gmbus_irq = 1,
- 	.has_logical_ring_contexts = 1,
- 	.has_gmch_display = 1,
- 	.has_aliasing_ppgtt = 1,
- 	.has_full_ppgtt = 1,
- 	.has_reset_engine = 1,
-+	.has_snoop = true,
- 	.display_mmio_offset = VLV_DISPLAY_BASE,
- 	GEN_CHV_PIPEOFFSETS,
- 	CURSOR_OFFSETS,
-@@ -358,13 +428,29 @@ static const struct intel_device_info in
- 	.has_guc = 1, \
- 	.ddb_size = 896
- 
--static const struct intel_device_info intel_skylake_info = {
-+static const struct intel_device_info intel_skylake_gt1_info __initconst = {
- 	SKL_PLATFORM,
-+	.gt = 1,
- };
- 
--static const struct intel_device_info intel_skylake_gt3_info = {
-+static const struct intel_device_info intel_skylake_gt2_info __initconst = {
- 	SKL_PLATFORM,
--	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
-+	.gt = 2,
-+};
-+
-+#define SKL_GT3_PLUS_PLATFORM \
-+	SKL_PLATFORM, \
-+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
-+
-+
-+static const struct intel_device_info intel_skylake_gt3_info __initconst = {
-+	SKL_GT3_PLUS_PLATFORM,
-+	.gt = 3,
-+};
-+
-+static const struct intel_device_info intel_skylake_gt4_info __initconst = {
-+	SKL_GT3_PLUS_PLATFORM,
-+	.gt = 4,
- };
- 
- #define GEN9_LP_FEATURES \
-@@ -383,25 +469,25 @@ static const struct intel_device_info in
- 	.has_resource_streamer = 1, \
- 	.has_rc6 = 1, \
- 	.has_dp_mst = 1, \
--	.has_gmbus_irq = 1, \
- 	.has_logical_ring_contexts = 1, \
- 	.has_guc = 1, \
- 	.has_aliasing_ppgtt = 1, \
- 	.has_full_ppgtt = 1, \
- 	.has_full_48bit_ppgtt = 1, \
- 	.has_reset_engine = 1, \
-+	.has_snoop = true, \
-+	.has_ipc = 1, \
- 	GEN_DEFAULT_PIPEOFFSETS, \
- 	IVB_CURSOR_OFFSETS, \
- 	BDW_COLORS
- 
--static const struct intel_device_info intel_broxton_info = {
-+static const struct intel_device_info intel_broxton_info __initconst = {
- 	GEN9_LP_FEATURES,
- 	.platform = INTEL_BROXTON,
- 	.ddb_size = 512,
--	.has_reset_engine = false,
- };
- 
--static const struct intel_device_info intel_geminilake_info = {
-+static const struct intel_device_info intel_geminilake_info __initconst = {
- 	GEN9_LP_FEATURES,
- 	.platform = INTEL_GEMINILAKE,
- 	.ddb_size = 1024,
-@@ -414,42 +500,59 @@ static const struct intel_device_info in
- 	.platform = INTEL_KABYLAKE, \
- 	.has_csr = 1, \
- 	.has_guc = 1, \
-+	.has_ipc = 1, \
- 	.ddb_size = 896
- 
--static const struct intel_device_info intel_kabylake_info = {
-+static const struct intel_device_info intel_kabylake_gt1_info __initconst = {
- 	KBL_PLATFORM,
-+	.gt = 1,
- };
- 
--static const struct intel_device_info intel_kabylake_gt3_info = {
-+static const struct intel_device_info intel_kabylake_gt2_info __initconst = {
- 	KBL_PLATFORM,
-+	.gt = 2,
-+};
-+
-+static const struct intel_device_info intel_kabylake_gt3_info __initconst = {
-+	KBL_PLATFORM,
-+	.gt = 3,
- 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
- };
- 
- #define CFL_PLATFORM \
--	.is_alpha_support = 1, \
- 	BDW_FEATURES, \
- 	.gen = 9, \
- 	.platform = INTEL_COFFEELAKE, \
- 	.has_csr = 1, \
- 	.has_guc = 1, \
-+	.has_ipc = 1, \
- 	.ddb_size = 896
- 
--static const struct intel_device_info intel_coffeelake_info = {
-+static const struct intel_device_info intel_coffeelake_gt1_info __initconst = {
-+	CFL_PLATFORM,
-+	.gt = 1,
-+};
-+
-+static const struct intel_device_info intel_coffeelake_gt2_info __initconst = {
- 	CFL_PLATFORM,
-+	.gt = 2,
- };
- 
--static const struct intel_device_info intel_coffeelake_gt3_info = {
-+static const struct intel_device_info intel_coffeelake_gt3_info __initconst = {
- 	CFL_PLATFORM,
-+	.gt = 3,
- 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
- };
- 
--static const struct intel_device_info intel_cannonlake_info = {
-+static const struct intel_device_info intel_cannonlake_gt2_info __initconst = {
- 	BDW_FEATURES,
- 	.is_alpha_support = 1,
- 	.platform = INTEL_CANNONLAKE,
- 	.gen = 10,
-+	.gt = 2,
- 	.ddb_size = 1024,
- 	.has_csr = 1,
-+	.has_ipc = 1,
- 	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
- };
- 
-@@ -476,31 +579,40 @@ static const struct pci_device_id pciidl
- 	INTEL_PINEVIEW_IDS(&intel_pineview_info),
- 	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
- 	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
--	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
--	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
-+	INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
-+	INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
-+	INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
-+	INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
- 	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
--	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
--	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
--	INTEL_HSW_IDS(&intel_haswell_info),
-+	INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
-+	INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
-+	INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
-+	INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
-+	INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
-+	INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
-+	INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
- 	INTEL_VLV_IDS(&intel_valleyview_info),
--	INTEL_BDW_GT12_IDS(&intel_broadwell_info),
-+	INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
-+	INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
- 	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
--	INTEL_BDW_RSVD_IDS(&intel_broadwell_info),
-+	INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
- 	INTEL_CHV_IDS(&intel_cherryview_info),
--	INTEL_SKL_GT1_IDS(&intel_skylake_info),
--	INTEL_SKL_GT2_IDS(&intel_skylake_info),
-+	INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
-+	INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
- 	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
--	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
-+	INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
- 	INTEL_BXT_IDS(&intel_broxton_info),
- 	INTEL_GLK_IDS(&intel_geminilake_info),
--	INTEL_KBL_GT1_IDS(&intel_kabylake_info),
--	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
-+	INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
-+	INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
- 	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
- 	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
--	INTEL_CFL_S_IDS(&intel_coffeelake_info),
--	INTEL_CFL_H_IDS(&intel_coffeelake_info),
--	INTEL_CFL_U_IDS(&intel_coffeelake_gt3_info),
--	INTEL_CNL_IDS(&intel_cannonlake_info),
-+	INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
-+	INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
-+	INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
-+	INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
-+	INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
-+	INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
- 	{0, 0, 0}
- };
- MODULE_DEVICE_TABLE(pci, pciidlist);
-@@ -519,7 +631,7 @@ static int i915_pci_probe(struct pci_dev
- 		(struct intel_device_info *) ent->driver_data;
- 	int err;
- 
--	if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
-+	if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
- 		DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
- 			 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
- 			 "to enable support in this kernel version, or check for kernel updates.\n");
-@@ -577,10 +689,10 @@ static int __init i915_init(void)
- 	 * vga_text_mode_force boot option.
- 	 */
- 
--	if (i915.modeset == 0)
-+	if (i915_modparams.modeset == 0)
- 		use_kms = false;
- 
--	if (vgacon_text_force() && i915.modeset == -1)
-+	if (vgacon_text_force() && i915_modparams.modeset == -1)
- 		use_kms = false;
- 
- 	if (!use_kms) {
---- linux-4.14/drivers/gpu/drm/i915/i915_perf.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_perf.c	2017-12-14 06:39:58.503903629 +0100
-@@ -206,6 +206,7 @@
- #include "i915_oa_kblgt2.h"
- #include "i915_oa_kblgt3.h"
- #include "i915_oa_glk.h"
-+#include "i915_oa_cflgt2.h"
- 
- /* HW requires this to be a power of two, between 128k and 16M, though driver
-  * is currently generally designed assuming the largest 16M size is used such
-@@ -1213,7 +1214,7 @@ static int oa_get_render_ctx_id(struct i
- {
- 	struct drm_i915_private *dev_priv = stream->dev_priv;
- 
--	if (i915.enable_execlists)
-+	if (i915_modparams.enable_execlists)
- 		dev_priv->perf.oa.specific_ctx_id = stream->ctx->hw_id;
- 	else {
- 		struct intel_engine_cs *engine = dev_priv->engine[RCS];
-@@ -1259,7 +1260,7 @@ static void oa_put_render_ctx_id(struct
- {
- 	struct drm_i915_private *dev_priv = stream->dev_priv;
- 
--	if (i915.enable_execlists) {
-+	if (i915_modparams.enable_execlists) {
- 		dev_priv->perf.oa.specific_ctx_id = INVALID_CTX_ID;
- 	} else {
- 		struct intel_engine_cs *engine = dev_priv->engine[RCS];
-@@ -1850,8 +1851,7 @@ static int gen8_enable_metric_set(struct
- 	 * be read back from automatically triggered reports, as part of the
- 	 * RPT_ID field.
- 	 */
--	if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
--	    IS_KABYLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
-+	if (IS_GEN9(dev_priv)) {
- 		I915_WRITE(GEN8_OA_DEBUG,
- 			   _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
- 					      GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
-@@ -2931,6 +2931,9 @@ void i915_perf_register(struct drm_i915_
- 			i915_perf_load_test_config_kblgt3(dev_priv);
- 	} else if (IS_GEMINILAKE(dev_priv)) {
- 		i915_perf_load_test_config_glk(dev_priv);
-+	} else if (IS_COFFEELAKE(dev_priv)) {
-+		if (IS_CFL_GT2(dev_priv))
-+			i915_perf_load_test_config_cflgt2(dev_priv);
- 	}
- 
- 	if (dev_priv->perf.oa.test_config.id == 0)
-@@ -3409,7 +3412,7 @@ void i915_perf_init(struct drm_i915_priv
- 		dev_priv->perf.oa.timestamp_frequency = 12500000;
- 
- 		dev_priv->perf.oa.oa_formats = hsw_oa_formats;
--	} else if (i915.enable_execlists) {
-+	} else if (i915_modparams.enable_execlists) {
- 		/* Note: that although we could theoretically also support the
- 		 * legacy ringbuffer mode on BDW (and earlier iterations of
- 		 * this driver, before upstreaming did this) it didn't seem
-@@ -3457,6 +3460,7 @@ void i915_perf_init(struct drm_i915_priv
- 				break;
- 			case INTEL_SKYLAKE:
- 			case INTEL_KABYLAKE:
-+			case INTEL_COFFEELAKE:
- 				dev_priv->perf.oa.timestamp_frequency = 12000000;
- 				break;
- 			default:
---- linux-4.14/drivers/gpu/drm/i915/i915_reg.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_reg.h	2017-12-14 06:39:58.504903629 +0100
-@@ -2336,7 +2336,7 @@ enum i915_power_well_id {
- #define DONE_REG		_MMIO(0x40b0)
- #define GEN8_PRIVATE_PAT_LO	_MMIO(0x40e0)
- #define GEN8_PRIVATE_PAT_HI	_MMIO(0x40e0 + 4)
--#define GEN10_PAT_INDEX(index)	_MMIO(0x40e0 + index*4)
-+#define GEN10_PAT_INDEX(index)	_MMIO(0x40e0 + (index)*4)
- #define BSD_HWS_PGA_GEN7	_MMIO(0x04180)
- #define BLT_HWS_PGA_GEN7	_MMIO(0x04280)
- #define VEBOX_HWS_PGA_GEN7	_MMIO(0x04380)
-@@ -2373,6 +2373,7 @@ enum i915_power_well_id {
- 
- #define GAMT_CHKN_BIT_REG	_MMIO(0x4ab8)
- #define   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING	(1<<28)
-+#define   GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT	(1<<24)
- 
- #if 0
- #define PRB0_TAIL	_MMIO(0x2030)
-@@ -2491,6 +2492,7 @@ enum i915_power_well_id {
- # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
- #define _3D_CHICKEN3	_MMIO(0x2090)
- #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL		(1 << 10)
-+#define  _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE	(1 << 5)
- #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
- #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)	((x)<<1) /* gen8+ */
- #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH	(1 << 1) /* gen6 */
-@@ -2728,6 +2730,11 @@ enum i915_power_well_id {
- #define   GEN9_F2_SS_DIS_SHIFT		20
- #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
- 
-+#define   GEN10_F2_S_ENA_SHIFT		22
-+#define   GEN10_F2_S_ENA_MASK		(0x3f << GEN10_F2_S_ENA_SHIFT)
-+#define   GEN10_F2_SS_DIS_SHIFT		18
-+#define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
-+
- #define GEN8_EU_DISABLE0		_MMIO(0x9134)
- #define   GEN8_EU_DIS0_S0_MASK		0xffffff
- #define   GEN8_EU_DIS0_S1_SHIFT		24
-@@ -2743,6 +2750,9 @@ enum i915_power_well_id {
- 
- #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice)*0x4)
- 
-+#define GEN10_EU_DISABLE3		_MMIO(0x9140)
-+#define   GEN10_EU_DIS_SS_MASK		0xff
-+
- #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
- #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
- #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
-@@ -2938,6 +2948,9 @@ enum i915_power_well_id {
- #define ILK_DPFC_CHICKEN	_MMIO(0x43224)
- #define   ILK_DPFC_DISABLE_DUMMY0 (1<<8)
- #define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION	(1<<23)
-+#define   GLK_SKIP_SEG_EN		(1<<12)
-+#define   GLK_SKIP_SEG_COUNT_MASK	(3<<10)
-+#define   GLK_SKIP_SEG_COUNT(x)		((x)<<10)
- #define ILK_FBC_RT_BASE		_MMIO(0x2128)
- #define   ILK_FBC_RT_VALID	(1<<0)
- #define   SNB_FBC_FRONT_BUFFER	(1<<1)
-@@ -3807,6 +3820,12 @@ enum {
- #define   PWM1_GATING_DIS		(1 << 13)
- 
- /*
-+ * GEN10 clock gating regs
-+ */
-+#define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
-+#define  SARBUNIT_CLKGATE_DIS		(1 << 5)
-+
-+/*
-  * Display engine regs
-  */
- 
-@@ -4036,7 +4055,7 @@ enum {
- #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
- #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
- #define   EDP_PSR2_IDLE_MASK		0xf
--#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
-+#define   EDP_PSR2_FRAME_BEFORE_SU(a)	((a)<<4)
- 
- #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
- #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
-@@ -6902,7 +6921,7 @@ enum {
- # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
- 
- #define CHICKEN_PAR1_1		_MMIO(0x42080)
--#define  SKL_RC_HASH_OUTSIDE	(1 << 15)
-+#define  SKL_DE_COMPRESSED_HASH_MODE	(1 << 15)
- #define  DPA_MASK_VBLANK_SRD	(1 << 15)
- #define  FORCE_ARB_IDLE_PLANES	(1 << 14)
- #define  SKL_EDP_PSR_FIX_RDWRAP	(1 << 3)
-@@ -6916,6 +6935,10 @@ enum {
- #define  GLK_CL1_PWR_DOWN	(1 << 11)
- #define  GLK_CL0_PWR_DOWN	(1 << 10)
- 
-+#define CHICKEN_MISC_4		_MMIO(0x4208c)
-+#define   FBC_STRIDE_OVERRIDE	(1 << 13)
-+#define   FBC_STRIDE_MASK	0x1FFF
-+
- #define _CHICKEN_PIPESL_1_A	0x420b0
- #define _CHICKEN_PIPESL_1_B	0x420b4
- #define  HSW_FBCQ_DIS			(1 << 22)
-@@ -6934,6 +6957,7 @@ enum {
- #define  DISP_FBC_WM_DIS		(1<<15)
- #define DISP_ARB_CTL2	_MMIO(0x45004)
- #define  DISP_DATA_PARTITION_5_6	(1<<6)
-+#define  DISP_IPC_ENABLE		(1<<3)
- #define DBUF_CTL	_MMIO(0x45008)
- #define  DBUF_POWER_REQUEST		(1<<31)
- #define  DBUF_POWER_STATE		(1<<30)
-@@ -6975,6 +6999,7 @@ enum {
- # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
- # define GEN9_RHWO_OPTIMIZATION_DISABLE		(1<<14)
- #define COMMON_SLICE_CHICKEN2			_MMIO(0x7014)
-+# define GEN9_PBE_COMPRESSED_HASH_SELECTION	(1<<13)
- # define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
- # define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
- # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
-@@ -7018,6 +7043,7 @@ enum {
- 
- /* GEN8 chicken */
- #define HDC_CHICKEN0				_MMIO(0x7300)
-+#define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
- #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
- #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
- #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
-@@ -7454,6 +7480,8 @@ enum {
- #define  FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
- #define  FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
- #define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
-+#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
-+#define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
- #define  SPT_PWM_GRANULARITY		(1<<0)
- #define SOUTH_CHICKEN2		_MMIO(0xc2004)
- #define  FDI_MPHY_IOSFSB_RESET_STATUS	(1<<13)
-@@ -7471,6 +7499,7 @@ enum {
- #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
- #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
- #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
-+#define  CNP_PWM_CGE_GATING_DISABLE (1<<13)
- #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
- 
- /* CPU: FDI_TX */
-@@ -7937,8 +7966,8 @@ enum {
- #define     GEN7_PCODE_TIMEOUT			0x2
- #define     GEN7_PCODE_ILLEGAL_DATA		0x3
- #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
--#define	  GEN6_PCODE_WRITE_RC6VIDS		0x4
--#define	  GEN6_PCODE_READ_RC6VIDS		0x5
-+#define   GEN6_PCODE_WRITE_RC6VIDS		0x4
-+#define   GEN6_PCODE_READ_RC6VIDS		0x5
- #define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
- #define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
- #define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
-@@ -7957,7 +7986,9 @@ enum {
- #define   GEN6_PCODE_WRITE_D_COMP		0x11
- #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
- #define   DISPLAY_IPS_CONTROL			0x19
--#define	  HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
-+            /* See also IPS_CTL */
-+#define     IPS_PCODE_CONTROL			(1 << 30)
-+#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
- #define   GEN9_PCODE_SAGV_CONTROL		0x21
- #define     GEN9_SAGV_DISABLE			0x0
- #define     GEN9_SAGV_IS_DISABLED		0x1
-@@ -8045,10 +8076,12 @@ enum {
- #define   FLOW_CONTROL_ENABLE		(1<<15)
- #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
- #define   STALL_DOP_GATING_DISABLE		(1<<5)
-+#define   THROTTLE_12_5				(7<<2)
- 
- #define GEN7_ROW_CHICKEN2		_MMIO(0xe4f4)
- #define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
- #define   DOP_CLOCK_GATING_DISABLE	(1<<0)
-+#define   PUSH_CONSTANT_DEREF_DISABLE	(1<<8)
- 
- #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
- #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
-@@ -8060,9 +8093,11 @@ enum {
- #define   HSW_SAMPLE_C_PERFORMANCE	(1<<9)
- #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
- #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC	(1<<5)
-+#define   CNL_FAST_ANISO_L1_BANKING_FIX	(1<<4)
- #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
- 
- #define GEN9_HALF_SLICE_CHICKEN7	_MMIO(0xe194)
-+#define   GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR	(1<<8)
- #define   GEN9_ENABLE_YV12_BUGFIX	(1<<4)
- #define   GEN9_ENABLE_GPGPU_PREEMPTION	(1<<2)
- 
-@@ -8575,7 +8610,7 @@ enum skl_power_gate {
- #define  DPLL_CFGCR0_LINK_RATE_3240	(6 << 25)
- #define  DPLL_CFGCR0_LINK_RATE_4050	(7 << 25)
- #define  DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
--#define  DPLL_CFGCR0_DCO_FRAC_SHIFT	(10)
-+#define  DPLL_CFGCR0_DCO_FRACTION_SHIFT	(10)
- #define  DPLL_CFGCR0_DCO_FRACTION(x)	((x) << 10)
- #define  DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
- #define CNL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
-@@ -8782,6 +8817,15 @@ enum skl_power_gate {
- #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
- #define  GLK_TX_ESC_CLK_DIV2_MASK			0x3FF
- 
-+/* Gen4+ Timestamp and Pipe Frame time stamp registers */
-+#define GEN4_TIMESTAMP		_MMIO(0x2358)
-+#define ILK_TIMESTAMP_HI	_MMIO(0x70070)
-+#define IVB_TIMESTAMP_CTR	_MMIO(0x44070)
-+
-+#define _PIPE_FRMTMSTMP_A		0x70048
-+#define PIPE_FRMTMSTMP(pipe)		\
-+			_MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
-+
- /* BXT MIPI clock controls */
- #define BXT_MAX_VAR_OUTPUT_KHZ			39500
- 
-@@ -9363,4 +9407,8 @@ enum skl_power_gate {
- #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL  0x67F1427F /*    "        " */
- #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT  0x5FF101FF /*    "        " */
- 
-+#define MMCD_MISC_CTRL		_MMIO(0x4ddc) /* skl+ */
-+#define  MMCD_PCLA		(1 << 31)
-+#define  MMCD_HOTSPOT_EN	(1 << 27)
-+
- #endif /* _I915_REG_H_ */
---- linux-4.14/drivers/gpu/drm/i915/i915_sw_fence.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_sw_fence.c	2017-12-14 06:39:58.504903629 +0100
-@@ -9,6 +9,7 @@
- 
- #include <linux/slab.h>
- #include <linux/dma-fence.h>
-+#include <linux/irq_work.h>
- #include <linux/reservation.h>
- 
- #include "i915_sw_fence.h"
-@@ -356,31 +357,44 @@ struct i915_sw_dma_fence_cb {
- 	struct i915_sw_fence *fence;
- 	struct dma_fence *dma;
- 	struct timer_list timer;
-+	struct irq_work work;
- };
- 
- static void timer_i915_sw_fence_wake(unsigned long data)
- {
- 	struct i915_sw_dma_fence_cb *cb = (struct i915_sw_dma_fence_cb *)data;
-+	struct i915_sw_fence *fence;
-+
-+	fence = xchg(&cb->fence, NULL);
-+	if (!fence)
-+		return;
- 
- 	pr_warn("asynchronous wait on fence %s:%s:%x timed out\n",
- 		cb->dma->ops->get_driver_name(cb->dma),
- 		cb->dma->ops->get_timeline_name(cb->dma),
- 		cb->dma->seqno);
--	dma_fence_put(cb->dma);
--	cb->dma = NULL;
- 
--	i915_sw_fence_complete(cb->fence);
--	cb->timer.function = NULL;
-+	i915_sw_fence_complete(fence);
- }
- 
- static void dma_i915_sw_fence_wake(struct dma_fence *dma,
- 				   struct dma_fence_cb *data)
- {
- 	struct i915_sw_dma_fence_cb *cb = container_of(data, typeof(*cb), base);
-+	struct i915_sw_fence *fence;
-+
-+	fence = xchg(&cb->fence, NULL);
-+	if (fence)
-+		i915_sw_fence_complete(fence);
-+
-+	irq_work_queue(&cb->work);
-+}
-+
-+static void irq_i915_sw_fence_work(struct irq_work *wrk)
-+{
-+	struct i915_sw_dma_fence_cb *cb = container_of(wrk, typeof(*cb), work);
- 
- 	del_timer_sync(&cb->timer);
--	if (cb->timer.function)
--		i915_sw_fence_complete(cb->fence);
- 	dma_fence_put(cb->dma);
- 
- 	kfree(cb);
-@@ -414,6 +428,7 @@ int i915_sw_fence_await_dma_fence(struct
- 	__setup_timer(&cb->timer,
- 		      timer_i915_sw_fence_wake, (unsigned long)cb,
- 		      TIMER_IRQSAFE);
-+	init_irq_work(&cb->work, irq_i915_sw_fence_work);
- 	if (timeout) {
- 		cb->dma = dma_fence_get(dma);
- 		mod_timer(&cb->timer, round_jiffies_up(jiffies + timeout));
---- linux-4.14/drivers/gpu/drm/i915/i915_trace.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/i915_trace.h	2017-12-14 06:39:58.504903629 +0100
-@@ -1032,5 +1032,5 @@ TRACE_EVENT(switch_mm,
- 
- /* This part must be outside protection */
- #undef TRACE_INCLUDE_PATH
--#define TRACE_INCLUDE_PATH .
-+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915
- #include <trace/define_trace.h>
---- linux-4.14/drivers/gpu/drm/i915/intel_atomic_plane.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_atomic_plane.c	2017-12-14 06:39:58.504903629 +0100
-@@ -107,7 +107,9 @@ intel_plane_destroy_state(struct drm_pla
- 	drm_atomic_helper_plane_destroy_state(plane, state);
- }
- 
--int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
-+int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
-+					struct intel_crtc_state *crtc_state,
-+					const struct intel_plane_state *old_plane_state,
- 					struct intel_plane_state *intel_state)
- {
- 	struct drm_plane *plane = intel_state->base.plane;
-@@ -124,7 +126,7 @@ int intel_plane_atomic_check_with_state(
- 	 * anything driver-specific we need to test in that case, so
- 	 * just return success.
- 	 */
--	if (!intel_state->base.crtc && !plane->state->crtc)
-+	if (!intel_state->base.crtc && !old_plane_state->base.crtc)
- 		return 0;
- 
- 	/* Clip all planes to CRTC size, or 0x0 if CRTC is disabled */
-@@ -194,16 +196,21 @@ int intel_plane_atomic_check_with_state(
- 	else
- 		crtc_state->active_planes &= ~BIT(intel_plane->id);
- 
--	return intel_plane_atomic_calc_changes(&crtc_state->base, state);
-+	return intel_plane_atomic_calc_changes(old_crtc_state,
-+					       &crtc_state->base,
-+					       old_plane_state,
-+					       state);
- }
- 
- static int intel_plane_atomic_check(struct drm_plane *plane,
--				    struct drm_plane_state *state)
-+				    struct drm_plane_state *new_plane_state)
- {
--	struct drm_crtc *crtc = state->crtc;
--	struct drm_crtc_state *drm_crtc_state;
--
--	crtc = crtc ? crtc : plane->state->crtc;
-+	struct drm_atomic_state *state = new_plane_state->state;
-+	const struct drm_plane_state *old_plane_state =
-+		drm_atomic_get_old_plane_state(state, plane);
-+	struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc;
-+	const struct drm_crtc_state *old_crtc_state;
-+	struct drm_crtc_state *new_crtc_state;
- 
- 	/*
- 	 * Both crtc and plane->crtc could be NULL if we're updating a
-@@ -214,29 +221,33 @@ static int intel_plane_atomic_check(stru
- 	if (!crtc)
- 		return 0;
- 
--	drm_crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
--	if (WARN_ON(!drm_crtc_state))
--		return -EINVAL;
-+	old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
-+	new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
- 
--	return intel_plane_atomic_check_with_state(to_intel_crtc_state(drm_crtc_state),
--						   to_intel_plane_state(state));
-+	return intel_plane_atomic_check_with_state(to_intel_crtc_state(old_crtc_state),
-+						   to_intel_crtc_state(new_crtc_state),
-+						   to_intel_plane_state(old_plane_state),
-+						   to_intel_plane_state(new_plane_state));
- }
- 
- static void intel_plane_atomic_update(struct drm_plane *plane,
- 				      struct drm_plane_state *old_state)
- {
-+	struct intel_atomic_state *state = to_intel_atomic_state(old_state->state);
- 	struct intel_plane *intel_plane = to_intel_plane(plane);
--	struct intel_plane_state *intel_state =
--		to_intel_plane_state(plane->state);
--	struct drm_crtc *crtc = plane->state->crtc ?: old_state->crtc;
-+	const struct intel_plane_state *new_plane_state =
-+		intel_atomic_get_new_plane_state(state, intel_plane);
-+	struct drm_crtc *crtc = new_plane_state->base.crtc ?: old_state->crtc;
-+
-+	if (new_plane_state->base.visible) {
-+		const struct intel_crtc_state *new_crtc_state =
-+			intel_atomic_get_new_crtc_state(state, to_intel_crtc(crtc));
- 
--	if (intel_state->base.visible) {
- 		trace_intel_update_plane(plane,
- 					 to_intel_crtc(crtc));
- 
- 		intel_plane->update_plane(intel_plane,
--					  to_intel_crtc_state(crtc->state),
--					  intel_state);
-+					  new_crtc_state, new_plane_state);
- 	} else {
- 		trace_intel_disable_plane(plane,
- 					  to_intel_crtc(crtc));
---- linux-4.14/drivers/gpu/drm/i915/intel_bios.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_bios.c	2017-12-14 06:39:58.504903629 +0100
-@@ -356,7 +356,7 @@ parse_sdvo_panel_data(struct drm_i915_pr
- 	struct drm_display_mode *panel_fixed_mode;
- 	int index;
- 
--	index = i915.vbt_sdvo_panel_type;
-+	index = i915_modparams.vbt_sdvo_panel_type;
- 	if (index == -2) {
- 		DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n");
- 		return;
-@@ -452,24 +452,24 @@ parse_general_definitions(struct drm_i91
- 	}
- }
- 
--static const union child_device_config *
--child_device_ptr(const struct bdb_general_definitions *p_defs, int i)
-+static const struct child_device_config *
-+child_device_ptr(const struct bdb_general_definitions *defs, int i)
- {
--	return (const void *) &p_defs->devices[i * p_defs->child_dev_size];
-+	return (const void *) &defs->devices[i * defs->child_dev_size];
- }
- 
- static void
- parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
- 			  const struct bdb_header *bdb)
- {
--	struct sdvo_device_mapping *p_mapping;
--	const struct bdb_general_definitions *p_defs;
--	const struct old_child_dev_config *child; /* legacy */
-+	struct sdvo_device_mapping *mapping;
-+	const struct bdb_general_definitions *defs;
-+	const struct child_device_config *child;
- 	int i, child_device_num, count;
- 	u16	block_size;
- 
--	p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
--	if (!p_defs) {
-+	defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
-+	if (!defs) {
- 		DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n");
- 		return;
- 	}
-@@ -479,18 +479,17 @@ parse_sdvo_device_mapping(struct drm_i91
- 	 * device size matches that of the *legacy* child device config
- 	 * struct. Thus, SDVO mapping will be skipped for newer VBT.
- 	 */
--	if (p_defs->child_dev_size != sizeof(*child)) {
-+	if (defs->child_dev_size != LEGACY_CHILD_DEVICE_CONFIG_SIZE) {
- 		DRM_DEBUG_KMS("Unsupported child device size for SDVO mapping.\n");
- 		return;
- 	}
- 	/* get the block size of general definitions */
--	block_size = get_blocksize(p_defs);
-+	block_size = get_blocksize(defs);
- 	/* get the number of child device */
--	child_device_num = (block_size - sizeof(*p_defs)) /
--		p_defs->child_dev_size;
-+	child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size;
- 	count = 0;
- 	for (i = 0; i < child_device_num; i++) {
--		child = &child_device_ptr(p_defs, i)->old;
-+		child = child_device_ptr(defs, i);
- 		if (!child->device_type) {
- 			/* skip the device block if device type is invalid */
- 			continue;
-@@ -514,20 +513,20 @@ parse_sdvo_device_mapping(struct drm_i91
- 			      child->slave_addr,
- 			      (child->dvo_port == DEVICE_PORT_DVOB) ?
- 			      "SDVOB" : "SDVOC");
--		p_mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1];
--		if (!p_mapping->initialized) {
--			p_mapping->dvo_port = child->dvo_port;
--			p_mapping->slave_addr = child->slave_addr;
--			p_mapping->dvo_wiring = child->dvo_wiring;
--			p_mapping->ddc_pin = child->ddc_pin;
--			p_mapping->i2c_pin = child->i2c_pin;
--			p_mapping->initialized = 1;
-+		mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1];
-+		if (!mapping->initialized) {
-+			mapping->dvo_port = child->dvo_port;
-+			mapping->slave_addr = child->slave_addr;
-+			mapping->dvo_wiring = child->dvo_wiring;
-+			mapping->ddc_pin = child->ddc_pin;
-+			mapping->i2c_pin = child->i2c_pin;
-+			mapping->initialized = 1;
- 			DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n",
--				      p_mapping->dvo_port,
--				      p_mapping->slave_addr,
--				      p_mapping->dvo_wiring,
--				      p_mapping->ddc_pin,
--				      p_mapping->i2c_pin);
-+				      mapping->dvo_port,
-+				      mapping->slave_addr,
-+				      mapping->dvo_wiring,
-+				      mapping->ddc_pin,
-+				      mapping->i2c_pin);
- 		} else {
- 			DRM_DEBUG_KMS("Maybe one SDVO port is shared by "
- 					 "two SDVO device.\n");
-@@ -577,7 +576,7 @@ parse_edp(struct drm_i915_private *dev_p
- {
- 	const struct bdb_edp *edp;
- 	const struct edp_power_seq *edp_pps;
--	const struct edp_link_params *edp_link_params;
-+	const struct edp_fast_link_params *edp_link_params;
- 	int panel_type = dev_priv->vbt.panel_type;
- 
- 	edp = find_section(bdb, BDB_EDP);
-@@ -601,7 +600,7 @@ parse_edp(struct drm_i915_private *dev_p
- 
- 	/* Get the eDP sequencing and link info */
- 	edp_pps = &edp->power_seqs[panel_type];
--	edp_link_params = &edp->link_params[panel_type];
-+	edp_link_params = &edp->fast_link_params[panel_type];
- 
- 	dev_priv->vbt.edp.pps = *edp_pps;
- 
-@@ -676,8 +675,9 @@ parse_edp(struct drm_i915_private *dev_p
- 		uint8_t vswing;
- 
- 		/* Don't read from VBT if module parameter has valid value*/
--		if (i915.edp_vswing) {
--			dev_priv->vbt.edp.low_vswing = i915.edp_vswing == 1;
-+		if (i915_modparams.edp_vswing) {
-+			dev_priv->vbt.edp.low_vswing =
-+				i915_modparams.edp_vswing == 1;
- 		} else {
- 			vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF;
- 			dev_priv->vbt.edp.low_vswing = vswing == 0;
-@@ -1113,7 +1113,7 @@ static void sanitize_aux_ch(struct drm_i
- static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
- 			   const struct bdb_header *bdb)
- {
--	union child_device_config *it, *child = NULL;
-+	struct child_device_config *it, *child = NULL;
- 	struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
- 	uint8_t hdmi_level_shift;
- 	int i, j;
-@@ -1141,7 +1141,7 @@ static void parse_ddi_port(struct drm_i9
- 			if (dvo_ports[port][j] == -1)
- 				break;
- 
--			if (it->common.dvo_port == dvo_ports[port][j]) {
-+			if (it->dvo_port == dvo_ports[port][j]) {
- 				if (child) {
- 					DRM_DEBUG_KMS("More than one child device for port %c in VBT, using the first.\n",
- 						      port_name(port));
-@@ -1154,14 +1154,14 @@ static void parse_ddi_port(struct drm_i9
- 	if (!child)
- 		return;
- 
--	aux_channel = child->common.aux_channel;
--	ddc_pin = child->common.ddc_pin;
-+	aux_channel = child->aux_channel;
-+	ddc_pin = child->ddc_pin;
- 
--	is_dvi = child->common.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
--	is_dp = child->common.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
--	is_crt = child->common.device_type & DEVICE_TYPE_ANALOG_OUTPUT;
--	is_hdmi = is_dvi && (child->common.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
--	is_edp = is_dp && (child->common.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);
-+	is_dvi = child->device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
-+	is_dp = child->device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
-+	is_crt = child->device_type & DEVICE_TYPE_ANALOG_OUTPUT;
-+	is_hdmi = is_dvi && (child->device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
-+	is_edp = is_dp && (child->device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);
- 
- 	if (port == PORT_A && is_dvi) {
- 		DRM_DEBUG_KMS("VBT claims port A supports DVI%s, ignoring\n",
-@@ -1217,7 +1217,7 @@ static void parse_ddi_port(struct drm_i9
- 
- 	if (bdb->version >= 158) {
- 		/* The VBT HDMI level shift values match the table we have. */
--		hdmi_level_shift = child->raw[7] & 0xF;
-+		hdmi_level_shift = child->hdmi_level_shifter_value;
- 		DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n",
- 			      port_name(port),
- 			      hdmi_level_shift);
-@@ -1225,11 +1225,11 @@ static void parse_ddi_port(struct drm_i9
- 	}
- 
- 	/* Parse the I_boost config for SKL and above */
--	if (bdb->version >= 196 && child->common.iboost) {
--		info->dp_boost_level = translate_iboost(child->common.iboost_level & 0xF);
-+	if (bdb->version >= 196 && child->iboost) {
-+		info->dp_boost_level = translate_iboost(child->dp_iboost_level);
- 		DRM_DEBUG_KMS("VBT (e)DP boost level for port %c: %d\n",
- 			      port_name(port), info->dp_boost_level);
--		info->hdmi_boost_level = translate_iboost(child->common.iboost_level >> 4);
-+		info->hdmi_boost_level = translate_iboost(child->hdmi_iboost_level);
- 		DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n",
- 			      port_name(port), info->hdmi_boost_level);
- 	}
-@@ -1257,15 +1257,15 @@ static void
- parse_device_mapping(struct drm_i915_private *dev_priv,
- 		     const struct bdb_header *bdb)
- {
--	const struct bdb_general_definitions *p_defs;
--	const union child_device_config *p_child;
--	union child_device_config *child_dev_ptr;
-+	const struct bdb_general_definitions *defs;
-+	const struct child_device_config *child;
-+	struct child_device_config *child_dev_ptr;
- 	int i, child_device_num, count;
- 	u8 expected_size;
- 	u16 block_size;
- 
--	p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
--	if (!p_defs) {
-+	defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
-+	if (!defs) {
- 		DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
- 		return;
- 	}
-@@ -1274,41 +1274,39 @@ parse_device_mapping(struct drm_i915_pri
- 	} else if (bdb->version < 111) {
- 		expected_size = 27;
- 	} else if (bdb->version < 195) {
--		BUILD_BUG_ON(sizeof(struct old_child_dev_config) != 33);
--		expected_size = sizeof(struct old_child_dev_config);
-+		expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE;
- 	} else if (bdb->version == 195) {
- 		expected_size = 37;
- 	} else if (bdb->version <= 197) {
- 		expected_size = 38;
- 	} else {
- 		expected_size = 38;
--		BUILD_BUG_ON(sizeof(*p_child) < 38);
-+		BUILD_BUG_ON(sizeof(*child) < 38);
- 		DRM_DEBUG_DRIVER("Expected child device config size for VBT version %u not known; assuming %u\n",
- 				 bdb->version, expected_size);
- 	}
- 
- 	/* Flag an error for unexpected size, but continue anyway. */
--	if (p_defs->child_dev_size != expected_size)
-+	if (defs->child_dev_size != expected_size)
- 		DRM_ERROR("Unexpected child device config size %u (expected %u for VBT version %u)\n",
--			  p_defs->child_dev_size, expected_size, bdb->version);
-+			  defs->child_dev_size, expected_size, bdb->version);
- 
- 	/* The legacy sized child device config is the minimum we need. */
--	if (p_defs->child_dev_size < sizeof(struct old_child_dev_config)) {
-+	if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) {
- 		DRM_DEBUG_KMS("Child device config size %u is too small.\n",
--			      p_defs->child_dev_size);
-+			      defs->child_dev_size);
- 		return;
- 	}
- 
- 	/* get the block size of general definitions */
--	block_size = get_blocksize(p_defs);
-+	block_size = get_blocksize(defs);
- 	/* get the number of child device */
--	child_device_num = (block_size - sizeof(*p_defs)) /
--				p_defs->child_dev_size;
-+	child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size;
- 	count = 0;
- 	/* get the number of child device that is present */
- 	for (i = 0; i < child_device_num; i++) {
--		p_child = child_device_ptr(p_defs, i);
--		if (!p_child->common.device_type) {
-+		child = child_device_ptr(defs, i);
-+		if (!child->device_type) {
- 			/* skip the device block if device type is invalid */
- 			continue;
- 		}
-@@ -1318,7 +1316,7 @@ parse_device_mapping(struct drm_i915_pri
- 		DRM_DEBUG_KMS("no child dev is parsed from VBT\n");
- 		return;
- 	}
--	dev_priv->vbt.child_dev = kcalloc(count, sizeof(*p_child), GFP_KERNEL);
-+	dev_priv->vbt.child_dev = kcalloc(count, sizeof(*child), GFP_KERNEL);
- 	if (!dev_priv->vbt.child_dev) {
- 		DRM_DEBUG_KMS("No memory space for child device\n");
- 		return;
-@@ -1327,8 +1325,8 @@ parse_device_mapping(struct drm_i915_pri
- 	dev_priv->vbt.child_dev_num = count;
- 	count = 0;
- 	for (i = 0; i < child_device_num; i++) {
--		p_child = child_device_ptr(p_defs, i);
--		if (!p_child->common.device_type) {
-+		child = child_device_ptr(defs, i);
-+		if (!child->device_type) {
- 			/* skip the device block if device type is invalid */
- 			continue;
- 		}
-@@ -1341,8 +1339,8 @@ parse_device_mapping(struct drm_i915_pri
- 		 * (child_dev_size) of the child device. Accessing the data must
- 		 * depend on VBT version.
- 		 */
--		memcpy(child_dev_ptr, p_child,
--		       min_t(size_t, p_defs->child_dev_size, sizeof(*p_child)));
-+		memcpy(child_dev_ptr, child,
-+		       min_t(size_t, defs->child_dev_size, sizeof(*child)));
- 
- 		/*
- 		 * copied full block, now init values when they are not
-@@ -1350,12 +1348,12 @@ parse_device_mapping(struct drm_i915_pri
- 		 */
- 		if (bdb->version < 196) {
- 			/* Set default values for bits added from v196 */
--			child_dev_ptr->common.iboost = 0;
--			child_dev_ptr->common.hpd_invert = 0;
-+			child_dev_ptr->iboost = 0;
-+			child_dev_ptr->hpd_invert = 0;
- 		}
- 
- 		if (bdb->version < 192)
--			child_dev_ptr->common.lspcon = 0;
-+			child_dev_ptr->lspcon = 0;
- 	}
- 	return;
- }
-@@ -1566,7 +1564,7 @@ out:
-  */
- bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv)
- {
--	union child_device_config *p_child;
-+	const struct child_device_config *child;
- 	int i;
- 
- 	if (!dev_priv->vbt.int_tv_support)
-@@ -1576,11 +1574,11 @@ bool intel_bios_is_tv_present(struct drm
- 		return true;
- 
- 	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
--		p_child = dev_priv->vbt.child_dev + i;
-+		child = dev_priv->vbt.child_dev + i;
- 		/*
- 		 * If the device type is not TV, continue.
- 		 */
--		switch (p_child->old.device_type) {
-+		switch (child->device_type) {
- 		case DEVICE_TYPE_INT_TV:
- 		case DEVICE_TYPE_TV:
- 		case DEVICE_TYPE_TV_SVIDEO_COMPOSITE:
-@@ -1591,7 +1589,7 @@ bool intel_bios_is_tv_present(struct drm
- 		/* Only when the addin_offset is non-zero, it is regarded
- 		 * as present.
- 		 */
--		if (p_child->old.addin_offset)
-+		if (child->addin_offset)
- 			return true;
- 	}
- 
-@@ -1608,14 +1606,14 @@ bool intel_bios_is_tv_present(struct drm
-  */
- bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin)
- {
-+	const struct child_device_config *child;
- 	int i;
- 
- 	if (!dev_priv->vbt.child_dev_num)
- 		return true;
- 
- 	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
--		union child_device_config *uchild = dev_priv->vbt.child_dev + i;
--		struct old_child_dev_config *child = &uchild->old;
-+		child = dev_priv->vbt.child_dev + i;
- 
- 		/* If the device type is not LFP, continue.
- 		 * We have to check both the new identifiers as well as the
-@@ -1657,6 +1655,7 @@ bool intel_bios_is_lvds_present(struct d
-  */
- bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port)
- {
-+	const struct child_device_config *child;
- 	static const struct {
- 		u16 dp, hdmi;
- 	} port_mapping[] = {
-@@ -1675,12 +1674,12 @@ bool intel_bios_is_port_present(struct d
- 		return false;
- 
- 	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
--		const union child_device_config *p_child =
--			&dev_priv->vbt.child_dev[i];
--		if ((p_child->common.dvo_port == port_mapping[port].dp ||
--		     p_child->common.dvo_port == port_mapping[port].hdmi) &&
--		    (p_child->common.device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING |
--						    DEVICE_TYPE_DISPLAYPORT_OUTPUT)))
-+		child = dev_priv->vbt.child_dev + i;
-+
-+		if ((child->dvo_port == port_mapping[port].dp ||
-+		     child->dvo_port == port_mapping[port].hdmi) &&
-+		    (child->device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING |
-+					   DEVICE_TYPE_DISPLAYPORT_OUTPUT)))
- 			return true;
- 	}
- 
-@@ -1696,7 +1695,7 @@ bool intel_bios_is_port_present(struct d
-  */
- bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
- {
--	union child_device_config *p_child;
-+	const struct child_device_config *child;
- 	static const short port_mapping[] = {
- 		[PORT_B] = DVO_PORT_DPB,
- 		[PORT_C] = DVO_PORT_DPC,
-@@ -1712,10 +1711,10 @@ bool intel_bios_is_port_edp(struct drm_i
- 		return false;
- 
- 	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
--		p_child = dev_priv->vbt.child_dev + i;
-+		child = dev_priv->vbt.child_dev + i;
- 
--		if (p_child->common.dvo_port == port_mapping[port] &&
--		    (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
-+		if (child->dvo_port == port_mapping[port] &&
-+		    (child->device_type & DEVICE_TYPE_eDP_BITS) ==
- 		    (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
- 			return true;
- 	}
-@@ -1723,7 +1722,7 @@ bool intel_bios_is_port_edp(struct drm_i
- 	return false;
- }
- 
--static bool child_dev_is_dp_dual_mode(const union child_device_config *p_child,
-+static bool child_dev_is_dp_dual_mode(const struct child_device_config *child,
- 				      enum port port)
- {
- 	static const struct {
-@@ -1742,16 +1741,16 @@ static bool child_dev_is_dp_dual_mode(co
- 	if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
- 		return false;
- 
--	if ((p_child->common.device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) !=
-+	if ((child->device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) !=
- 	    (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS))
- 		return false;
- 
--	if (p_child->common.dvo_port == port_mapping[port].dp)
-+	if (child->dvo_port == port_mapping[port].dp)
- 		return true;
- 
- 	/* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */
--	if (p_child->common.dvo_port == port_mapping[port].hdmi &&
--	    p_child->common.aux_channel != 0)
-+	if (child->dvo_port == port_mapping[port].hdmi &&
-+	    child->aux_channel != 0)
- 		return true;
- 
- 	return false;
-@@ -1760,13 +1759,13 @@ static bool child_dev_is_dp_dual_mode(co
- bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv,
- 				     enum port port)
- {
-+	const struct child_device_config *child;
- 	int i;
- 
- 	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
--		const union child_device_config *p_child =
--			&dev_priv->vbt.child_dev[i];
-+		child = dev_priv->vbt.child_dev + i;
- 
--		if (child_dev_is_dp_dual_mode(p_child, port))
-+		if (child_dev_is_dp_dual_mode(child, port))
- 			return true;
- 	}
- 
-@@ -1783,17 +1782,17 @@ bool intel_bios_is_port_dp_dual_mode(str
- bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
- 			       enum port *port)
- {
--	union child_device_config *p_child;
-+	const struct child_device_config *child;
- 	u8 dvo_port;
- 	int i;
- 
- 	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
--		p_child = dev_priv->vbt.child_dev + i;
-+		child = dev_priv->vbt.child_dev + i;
- 
--		if (!(p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT))
-+		if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
- 			continue;
- 
--		dvo_port = p_child->common.dvo_port;
-+		dvo_port = child->dvo_port;
- 
- 		switch (dvo_port) {
- 		case DVO_PORT_MIPIA:
-@@ -1823,16 +1822,19 @@ bool
- intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
- 				enum port port)
- {
-+	const struct child_device_config *child;
- 	int i;
- 
- 	if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
- 		return false;
- 
- 	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
--		if (!dev_priv->vbt.child_dev[i].common.hpd_invert)
-+		child = dev_priv->vbt.child_dev + i;
-+
-+		if (!child->hpd_invert)
- 			continue;
- 
--		switch (dev_priv->vbt.child_dev[i].common.dvo_port) {
-+		switch (child->dvo_port) {
- 		case DVO_PORT_DPA:
- 		case DVO_PORT_HDMIA:
- 			if (port == PORT_A)
-@@ -1867,16 +1869,19 @@ bool
- intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
- 				enum port port)
- {
-+	const struct child_device_config *child;
- 	int i;
- 
- 	if (!HAS_LSPCON(dev_priv))
- 		return false;
- 
- 	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
--		if (!dev_priv->vbt.child_dev[i].common.lspcon)
-+		child = dev_priv->vbt.child_dev + i;
-+
-+		if (!child->lspcon)
- 			continue;
- 
--		switch (dev_priv->vbt.child_dev[i].common.dvo_port) {
-+		switch (child->dvo_port) {
- 		case DVO_PORT_DPA:
- 		case DVO_PORT_HDMIA:
- 			if (port == PORT_A)
---- linux-4.14/drivers/gpu/drm/i915/intel_breadcrumbs.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_breadcrumbs.c	2017-12-14 06:39:58.504903629 +0100
-@@ -64,7 +64,7 @@ static unsigned long wait_timeout(void)
- 
- static noinline void missed_breadcrumb(struct intel_engine_cs *engine)
- {
--	DRM_DEBUG_DRIVER("%s missed breadcrumb at %pF, irq posted? %s, current seqno=%x, last=%x\n",
-+	DRM_DEBUG_DRIVER("%s missed breadcrumb at %pS, irq posted? %s, current seqno=%x, last=%x\n",
- 			 engine->name, __builtin_return_address(0),
- 			 yesno(test_bit(ENGINE_IRQ_BREADCRUMB,
- 					&engine->irq_posted)),
---- linux-4.14/drivers/gpu/drm/i915/intel_cdclk.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_cdclk.c	2017-12-14 06:39:58.505903630 +0100
-@@ -417,24 +417,21 @@ static void hsw_get_cdclk(struct drm_i91
- 		cdclk_state->cdclk = 540000;
- }
- 
--static int vlv_calc_cdclk(struct drm_i915_private *dev_priv,
--			  int max_pixclk)
-+static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
- {
- 	int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
- 		333333 : 320000;
--	int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
- 
- 	/*
- 	 * We seem to get an unstable or solid color picture at 200MHz.
- 	 * Not sure what's wrong. For now use 200MHz only when all pipes
- 	 * are off.
- 	 */
--	if (!IS_CHERRYVIEW(dev_priv) &&
--	    max_pixclk > freq_320*limit/100)
-+	if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
- 		return 400000;
--	else if (max_pixclk > 266667*limit/100)
-+	else if (min_cdclk > 266667)
- 		return freq_320;
--	else if (max_pixclk > 0)
-+	else if (min_cdclk > 0)
- 		return 266667;
- 	else
- 		return 200000;
-@@ -612,13 +609,13 @@ static void chv_set_cdclk(struct drm_i91
- 	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
- }
- 
--static int bdw_calc_cdclk(int max_pixclk)
-+static int bdw_calc_cdclk(int min_cdclk)
- {
--	if (max_pixclk > 540000)
-+	if (min_cdclk > 540000)
- 		return 675000;
--	else if (max_pixclk > 450000)
-+	else if (min_cdclk > 450000)
- 		return 540000;
--	else if (max_pixclk > 337500)
-+	else if (min_cdclk > 337500)
- 		return 450000;
- 	else
- 		return 337500;
-@@ -672,8 +669,12 @@ static void bdw_set_cdclk(struct drm_i91
- 	val |= LCPLL_CD_SOURCE_FCLK;
- 	I915_WRITE(LCPLL_CTL, val);
- 
-+	/*
-+	 * According to the spec, it should be enough to poll for this 1 us.
-+	 * However, extensive testing shows that this can take longer.
-+	 */
- 	if (wait_for_us(I915_READ(LCPLL_CTL) &
--			LCPLL_CD_SOURCE_FCLK_DONE, 1))
-+			LCPLL_CD_SOURCE_FCLK_DONE, 100))
- 		DRM_ERROR("Switching to FCLK failed\n");
- 
- 	val = I915_READ(LCPLL_CTL);
-@@ -724,23 +725,23 @@ static void bdw_set_cdclk(struct drm_i91
- 	     cdclk, dev_priv->cdclk.hw.cdclk);
- }
- 
--static int skl_calc_cdclk(int max_pixclk, int vco)
-+static int skl_calc_cdclk(int min_cdclk, int vco)
- {
- 	if (vco == 8640000) {
--		if (max_pixclk > 540000)
-+		if (min_cdclk > 540000)
- 			return 617143;
--		else if (max_pixclk > 432000)
-+		else if (min_cdclk > 432000)
- 			return 540000;
--		else if (max_pixclk > 308571)
-+		else if (min_cdclk > 308571)
- 			return 432000;
- 		else
- 			return 308571;
- 	} else {
--		if (max_pixclk > 540000)
-+		if (min_cdclk > 540000)
- 			return 675000;
--		else if (max_pixclk > 450000)
-+		else if (min_cdclk > 450000)
- 			return 540000;
--		else if (max_pixclk > 337500)
-+		else if (min_cdclk > 337500)
- 			return 450000;
- 		else
- 			return 337500;
-@@ -1075,31 +1076,25 @@ void skl_uninit_cdclk(struct drm_i915_pr
- 	skl_set_cdclk(dev_priv, &cdclk_state);
- }
- 
--static int bxt_calc_cdclk(int max_pixclk)
-+static int bxt_calc_cdclk(int min_cdclk)
- {
--	if (max_pixclk > 576000)
-+	if (min_cdclk > 576000)
- 		return 624000;
--	else if (max_pixclk > 384000)
-+	else if (min_cdclk > 384000)
- 		return 576000;
--	else if (max_pixclk > 288000)
-+	else if (min_cdclk > 288000)
- 		return 384000;
--	else if (max_pixclk > 144000)
-+	else if (min_cdclk > 144000)
- 		return 288000;
- 	else
- 		return 144000;
- }
- 
--static int glk_calc_cdclk(int max_pixclk)
-+static int glk_calc_cdclk(int min_cdclk)
- {
--	/*
--	 * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
--	 * as a temporary workaround. Use a higher cdclk instead. (Note that
--	 * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
--	 * cdclk.)
--	 */
--	if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
-+	if (min_cdclk > 158400)
- 		return 316800;
--	else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
-+	else if (min_cdclk > 79200)
- 		return 158400;
- 	else
- 		return 79200;
-@@ -1420,11 +1415,11 @@ void bxt_uninit_cdclk(struct drm_i915_pr
- 	bxt_set_cdclk(dev_priv, &cdclk_state);
- }
- 
--static int cnl_calc_cdclk(int max_pixclk)
-+static int cnl_calc_cdclk(int min_cdclk)
- {
--	if (max_pixclk > 336000)
-+	if (min_cdclk > 336000)
- 		return 528000;
--	else if (max_pixclk > 168000)
-+	else if (min_cdclk > 168000)
- 		return 336000;
- 	else
- 		return 168000;
-@@ -1732,104 +1727,119 @@ void intel_set_cdclk(struct drm_i915_pri
- 	dev_priv->display.set_cdclk(dev_priv, cdclk_state);
- }
- 
--static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
--					  int pixel_rate)
-+static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
-+				     int pixel_rate)
-+{
-+	if (INTEL_GEN(dev_priv) >= 10)
-+		/*
-+		 * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2)
-+		 * once DDI clock voltage requirements are
-+		 * handled correctly.
-+		 */
-+		return pixel_rate;
-+	else if (IS_GEMINILAKE(dev_priv))
-+		/*
-+		 * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
-+		 * as a temporary workaround. Use a higher cdclk instead. (Note that
-+		 * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
-+		 * cdclk.)
-+		 */
-+		return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
-+	else if (IS_GEN9(dev_priv) ||
-+		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
-+		return pixel_rate;
-+	else if (IS_CHERRYVIEW(dev_priv))
-+		return DIV_ROUND_UP(pixel_rate * 100, 95);
-+	else
-+		return DIV_ROUND_UP(pixel_rate * 100, 90);
-+}
-+
-+int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
- {
- 	struct drm_i915_private *dev_priv =
- 		to_i915(crtc_state->base.crtc->dev);
-+	int min_cdclk;
-+
-+	if (!crtc_state->base.enable)
-+		return 0;
-+
-+	min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
- 
- 	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
- 	if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
--		pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
-+		min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
- 
- 	/* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
- 	 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
- 	 * there may be audio corruption or screen corruption." This cdclk
--	 * restriction for GLK is 316.8 MHz and since GLK can output two
--	 * pixels per clock, the pixel rate becomes 2 * 316.8 MHz.
-+	 * restriction for GLK is 316.8 MHz.
- 	 */
- 	if (intel_crtc_has_dp_encoder(crtc_state) &&
- 	    crtc_state->has_audio &&
- 	    crtc_state->port_clock >= 540000 &&
- 	    crtc_state->lane_count == 4) {
--		if (IS_CANNONLAKE(dev_priv))
--			pixel_rate = max(316800, pixel_rate);
--		else if (IS_GEMINILAKE(dev_priv))
--			pixel_rate = max(2 * 316800, pixel_rate);
--		else
--			pixel_rate = max(432000, pixel_rate);
-+		if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
-+			/* Display WA #1145: glk,cnl */
-+			min_cdclk = max(316800, min_cdclk);
-+		} else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
-+			/* Display WA #1144: skl,bxt */
-+			min_cdclk = max(432000, min_cdclk);
-+		}
- 	}
- 
- 	/* According to BSpec, "The CD clock frequency must be at least twice
- 	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
--	 * The check for GLK has to be adjusted as the platform can output
--	 * two pixels per clock.
- 	 */
--	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
--		if (IS_GEMINILAKE(dev_priv))
--			pixel_rate = max(2 * 2 * 96000, pixel_rate);
--		else
--			pixel_rate = max(2 * 96000, pixel_rate);
-+	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
-+		min_cdclk = max(2 * 96000, min_cdclk);
-+
-+	if (min_cdclk > dev_priv->max_cdclk_freq) {
-+		DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
-+			      min_cdclk, dev_priv->max_cdclk_freq);
-+		return -EINVAL;
- 	}
- 
--	return pixel_rate;
-+	return min_cdclk;
- }
- 
--/* compute the max rate for new configuration */
--static int intel_max_pixel_rate(struct drm_atomic_state *state)
-+static int intel_compute_min_cdclk(struct drm_atomic_state *state)
- {
- 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- 	struct drm_i915_private *dev_priv = to_i915(state->dev);
--	struct drm_crtc *crtc;
--	struct drm_crtc_state *cstate;
-+	struct intel_crtc *crtc;
- 	struct intel_crtc_state *crtc_state;
--	unsigned int max_pixel_rate = 0, i;
-+	int min_cdclk, i;
- 	enum pipe pipe;
- 
--	memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
--	       sizeof(intel_state->min_pixclk));
-+	memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
-+	       sizeof(intel_state->min_cdclk));
- 
--	for_each_new_crtc_in_state(state, crtc, cstate, i) {
--		int pixel_rate;
-+	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
-+		min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
-+		if (min_cdclk < 0)
-+			return min_cdclk;
- 
--		crtc_state = to_intel_crtc_state(cstate);
--		if (!crtc_state->base.enable) {
--			intel_state->min_pixclk[i] = 0;
--			continue;
--		}
--
--		pixel_rate = crtc_state->pixel_rate;
--
--		if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
--			pixel_rate =
--				bdw_adjust_min_pipe_pixel_rate(crtc_state,
--							       pixel_rate);
--
--		intel_state->min_pixclk[i] = pixel_rate;
-+		intel_state->min_cdclk[i] = min_cdclk;
- 	}
- 
-+	min_cdclk = 0;
- 	for_each_pipe(dev_priv, pipe)
--		max_pixel_rate = max(intel_state->min_pixclk[pipe],
--				     max_pixel_rate);
-+		min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
- 
--	return max_pixel_rate;
-+	return min_cdclk;
- }
- 
- static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
- {
- 	struct drm_i915_private *dev_priv = to_i915(state->dev);
--	int max_pixclk = intel_max_pixel_rate(state);
--	struct intel_atomic_state *intel_state =
--		to_intel_atomic_state(state);
--	int cdclk;
--
--	cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
--
--	if (cdclk > dev_priv->max_cdclk_freq) {
--		DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
--			      cdclk, dev_priv->max_cdclk_freq);
--		return -EINVAL;
--	}
-+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-+	int min_cdclk, cdclk;
-+
-+	min_cdclk = intel_compute_min_cdclk(state);
-+	if (min_cdclk < 0)
-+		return min_cdclk;
-+
-+	cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
- 
- 	intel_state->cdclk.logical.cdclk = cdclk;
- 
-@@ -1847,22 +1857,18 @@ static int vlv_modeset_calc_cdclk(struct
- 
- static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
- {
--	struct drm_i915_private *dev_priv = to_i915(state->dev);
- 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
--	int max_pixclk = intel_max_pixel_rate(state);
--	int cdclk;
-+	int min_cdclk, cdclk;
-+
-+	min_cdclk = intel_compute_min_cdclk(state);
-+	if (min_cdclk < 0)
-+		return min_cdclk;
- 
- 	/*
- 	 * FIXME should also account for plane ratio
- 	 * once 64bpp pixel formats are supported.
- 	 */
--	cdclk = bdw_calc_cdclk(max_pixclk);
--
--	if (cdclk > dev_priv->max_cdclk_freq) {
--		DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
--			      cdclk, dev_priv->max_cdclk_freq);
--		return -EINVAL;
--	}
-+	cdclk = bdw_calc_cdclk(min_cdclk);
- 
- 	intel_state->cdclk.logical.cdclk = cdclk;
- 
-@@ -1880,10 +1886,13 @@ static int bdw_modeset_calc_cdclk(struct
- 
- static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
- {
--	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- 	struct drm_i915_private *dev_priv = to_i915(state->dev);
--	const int max_pixclk = intel_max_pixel_rate(state);
--	int cdclk, vco;
-+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-+	int min_cdclk, cdclk, vco;
-+
-+	min_cdclk = intel_compute_min_cdclk(state);
-+	if (min_cdclk < 0)
-+		return min_cdclk;
- 
- 	vco = intel_state->cdclk.logical.vco;
- 	if (!vco)
-@@ -1893,13 +1902,7 @@ static int skl_modeset_calc_cdclk(struct
- 	 * FIXME should also account for plane ratio
- 	 * once 64bpp pixel formats are supported.
- 	 */
--	cdclk = skl_calc_cdclk(max_pixclk, vco);
--
--	if (cdclk > dev_priv->max_cdclk_freq) {
--		DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
--			      cdclk, dev_priv->max_cdclk_freq);
--		return -EINVAL;
--	}
-+	cdclk = skl_calc_cdclk(min_cdclk, vco);
- 
- 	intel_state->cdclk.logical.vco = vco;
- 	intel_state->cdclk.logical.cdclk = cdclk;
-@@ -1920,25 +1923,21 @@ static int skl_modeset_calc_cdclk(struct
- static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
- {
- 	struct drm_i915_private *dev_priv = to_i915(state->dev);
--	int max_pixclk = intel_max_pixel_rate(state);
--	struct intel_atomic_state *intel_state =
--		to_intel_atomic_state(state);
--	int cdclk, vco;
-+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-+	int min_cdclk, cdclk, vco;
-+
-+	min_cdclk = intel_compute_min_cdclk(state);
-+	if (min_cdclk < 0)
-+		return min_cdclk;
- 
- 	if (IS_GEMINILAKE(dev_priv)) {
--		cdclk = glk_calc_cdclk(max_pixclk);
-+		cdclk = glk_calc_cdclk(min_cdclk);
- 		vco = glk_de_pll_vco(dev_priv, cdclk);
- 	} else {
--		cdclk = bxt_calc_cdclk(max_pixclk);
-+		cdclk = bxt_calc_cdclk(min_cdclk);
- 		vco = bxt_de_pll_vco(dev_priv, cdclk);
- 	}
- 
--	if (cdclk > dev_priv->max_cdclk_freq) {
--		DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
--			      cdclk, dev_priv->max_cdclk_freq);
--		return -EINVAL;
--	}
--
- 	intel_state->cdclk.logical.vco = vco;
- 	intel_state->cdclk.logical.cdclk = cdclk;
- 
-@@ -1964,19 +1963,15 @@ static int bxt_modeset_calc_cdclk(struct
- static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
- {
- 	struct drm_i915_private *dev_priv = to_i915(state->dev);
--	struct intel_atomic_state *intel_state =
--		to_intel_atomic_state(state);
--	int max_pixclk = intel_max_pixel_rate(state);
--	int cdclk, vco;
-+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-+	int min_cdclk, cdclk, vco;
- 
--	cdclk = cnl_calc_cdclk(max_pixclk);
--	vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
-+	min_cdclk = intel_compute_min_cdclk(state);
-+	if (min_cdclk < 0)
-+		return min_cdclk;
- 
--	if (cdclk > dev_priv->max_cdclk_freq) {
--		DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
--			      cdclk, dev_priv->max_cdclk_freq);
--		return -EINVAL;
--	}
-+	cdclk = cnl_calc_cdclk(min_cdclk);
-+	vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
- 
- 	intel_state->cdclk.logical.vco = vco;
- 	intel_state->cdclk.logical.cdclk = cdclk;
-@@ -1999,14 +1994,21 @@ static int intel_compute_max_dotclk(stru
- {
- 	int max_cdclk_freq = dev_priv->max_cdclk_freq;
- 
--	if (IS_GEMINILAKE(dev_priv))
-+	if (INTEL_GEN(dev_priv) >= 10)
-+		/*
-+		 * FIXME: Allow '2 * max_cdclk_freq'
-+		 * once DDI clock voltage requirements are
-+		 * handled correctly.
-+		 */
-+		return max_cdclk_freq;
-+	else if (IS_GEMINILAKE(dev_priv))
- 		/*
- 		 * FIXME: Limiting to 99% as a temporary workaround. See
--		 * glk_calc_cdclk() for details.
-+		 * intel_min_cdclk() for details.
- 		 */
- 		return 2 * max_cdclk_freq * 99 / 100;
--	else if (INTEL_INFO(dev_priv)->gen >= 9 ||
--		 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
-+	else if (IS_GEN9(dev_priv) ||
-+		 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
- 		return max_cdclk_freq;
- 	else if (IS_CHERRYVIEW(dev_priv))
- 		return max_cdclk_freq*95/100;
---- linux-4.14/drivers/gpu/drm/i915/intel_crt.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_crt.c	2017-12-14 06:39:58.505903630 +0100
-@@ -143,7 +143,7 @@ static void hsw_crt_get_config(struct in
- /* Note: The caller is required to filter out dpms modes not supported by the
-  * platform. */
- static void intel_crt_set_dpms(struct intel_encoder *encoder,
--			       struct intel_crtc_state *crtc_state,
-+			       const struct intel_crtc_state *crtc_state,
- 			       int mode)
- {
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-@@ -194,28 +194,28 @@ static void intel_crt_set_dpms(struct in
- }
- 
- static void intel_disable_crt(struct intel_encoder *encoder,
--			      struct intel_crtc_state *old_crtc_state,
--			      struct drm_connector_state *old_conn_state)
-+			      const struct intel_crtc_state *old_crtc_state,
-+			      const struct drm_connector_state *old_conn_state)
- {
- 	intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
- }
- 
- static void pch_disable_crt(struct intel_encoder *encoder,
--			    struct intel_crtc_state *old_crtc_state,
--			    struct drm_connector_state *old_conn_state)
-+			    const struct intel_crtc_state *old_crtc_state,
-+			    const struct drm_connector_state *old_conn_state)
- {
- }
- 
- static void pch_post_disable_crt(struct intel_encoder *encoder,
--				 struct intel_crtc_state *old_crtc_state,
--				 struct drm_connector_state *old_conn_state)
-+				 const struct intel_crtc_state *old_crtc_state,
-+				 const struct drm_connector_state *old_conn_state)
- {
- 	intel_disable_crt(encoder, old_crtc_state, old_conn_state);
- }
- 
- static void hsw_post_disable_crt(struct intel_encoder *encoder,
--				 struct intel_crtc_state *old_crtc_state,
--				 struct drm_connector_state *old_conn_state)
-+				 const struct intel_crtc_state *old_crtc_state,
-+				 const struct drm_connector_state *old_conn_state)
- {
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- 
-@@ -228,8 +228,8 @@ static void hsw_post_disable_crt(struct
- }
- 
- static void intel_enable_crt(struct intel_encoder *encoder,
--			     struct intel_crtc_state *pipe_config,
--			     struct drm_connector_state *conn_state)
-+			     const struct intel_crtc_state *pipe_config,
-+			     const struct drm_connector_state *conn_state)
- {
- 	intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON);
- }
-@@ -712,7 +712,7 @@ intel_crt_detect(struct drm_connector *c
- 	 * broken monitor (without edid) to work behind a broken kvm (that fails
- 	 * to have the right resistors for HP detection) needs to fix this up.
- 	 * For now just bail out. */
--	if (I915_HAS_HOTPLUG(dev_priv) && !i915.load_detect_test) {
-+	if (I915_HAS_HOTPLUG(dev_priv) && !i915_modparams.load_detect_test) {
- 		status = connector_status_disconnected;
- 		goto out;
- 	}
-@@ -730,7 +730,7 @@ intel_crt_detect(struct drm_connector *c
- 		else if (INTEL_GEN(dev_priv) < 4)
- 			status = intel_crt_load_detect(crt,
- 				to_intel_crtc(connector->state->crtc)->pipe);
--		else if (i915.load_detect_test)
-+		else if (i915_modparams.load_detect_test)
- 			status = connector_status_disconnected;
- 		else
- 			status = connector_status_unknown;
---- linux-4.14/drivers/gpu/drm/i915/intel_csr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_csr.c	2017-12-14 06:39:58.505903630 +0100
-@@ -252,8 +252,14 @@ void intel_csr_load_program(struct drm_i
- 	}
- 
- 	fw_size = dev_priv->csr.dmc_fw_size;
-+	assert_rpm_wakelock_held(dev_priv);
-+
-+	preempt_disable();
-+
- 	for (i = 0; i < fw_size; i++)
--		I915_WRITE(CSR_PROGRAM(i), payload[i]);
-+		I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
-+
-+	preempt_enable();
- 
- 	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
- 		I915_WRITE(dev_priv->csr.mmioaddr[i],
---- linux-4.14/drivers/gpu/drm/i915/intel_ddi.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_ddi.c	2017-12-14 06:39:58.505903630 +0100
-@@ -301,10 +301,10 @@ static const struct ddi_buf_trans skl_y_
- };
- 
- struct bxt_ddi_buf_trans {
--	u32 margin;	/* swing value */
--	u32 scale;	/* scale value */
--	u32 enable;	/* scale enable */
--	u32 deemphasis;
-+	u8 margin;	/* swing value */
-+	u8 scale;	/* scale value */
-+	u8 enable;	/* scale enable */
-+	u8 deemphasis;
- 	bool default_index; /* true if the entry represents default value */
- };
- 
-@@ -354,11 +354,11 @@ static const struct bxt_ddi_buf_trans bx
- };
- 
- struct cnl_ddi_buf_trans {
--	u32 dw2_swing_sel;
--	u32 dw7_n_scalar;
--	u32 dw4_cursor_coeff;
--	u32 dw4_post_cursor_2;
--	u32 dw4_post_cursor_1;
-+	u8 dw2_swing_sel;
-+	u8 dw7_n_scalar;
-+	u8 dw4_cursor_coeff;
-+	u8 dw4_post_cursor_2;
-+	u8 dw4_post_cursor_1;
- };
- 
- /* Voltage Swing Programming for VccIO 0.85V for DP */
-@@ -588,6 +588,67 @@ skl_get_buf_trans_hdmi(struct drm_i915_p
- 	}
- }
- 
-+static const struct cnl_ddi_buf_trans *
-+cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
-+{
-+	u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
-+
-+	if (voltage == VOLTAGE_INFO_0_85V) {
-+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
-+		return cnl_ddi_translations_hdmi_0_85V;
-+	} else if (voltage == VOLTAGE_INFO_0_95V) {
-+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
-+		return cnl_ddi_translations_hdmi_0_95V;
-+	} else if (voltage == VOLTAGE_INFO_1_05V) {
-+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
-+		return cnl_ddi_translations_hdmi_1_05V;
-+	} else
-+		MISSING_CASE(voltage);
-+	return NULL;
-+}
-+
-+static const struct cnl_ddi_buf_trans *
-+cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
-+{
-+	u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
-+
-+	if (voltage == VOLTAGE_INFO_0_85V) {
-+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
-+		return cnl_ddi_translations_dp_0_85V;
-+	} else if (voltage == VOLTAGE_INFO_0_95V) {
-+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
-+		return cnl_ddi_translations_dp_0_95V;
-+	} else if (voltage == VOLTAGE_INFO_1_05V) {
-+		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
-+		return cnl_ddi_translations_dp_1_05V;
-+	} else
-+		MISSING_CASE(voltage);
-+	return NULL;
-+}
-+
-+static const struct cnl_ddi_buf_trans *
-+cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
-+{
-+	u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
-+
-+	if (dev_priv->vbt.edp.low_vswing) {
-+		if (voltage == VOLTAGE_INFO_0_85V) {
-+			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
-+			return cnl_ddi_translations_edp_0_85V;
-+		} else if (voltage == VOLTAGE_INFO_0_95V) {
-+			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
-+			return cnl_ddi_translations_edp_0_95V;
-+		} else if (voltage == VOLTAGE_INFO_1_05V) {
-+			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
-+			return cnl_ddi_translations_edp_1_05V;
-+		} else
-+			MISSING_CASE(voltage);
-+		return NULL;
-+	} else {
-+		return cnl_get_buf_trans_dp(dev_priv, n_entries);
-+	}
-+}
-+
- static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
- {
- 	int n_hdmi_entries;
-@@ -599,7 +660,10 @@ static int intel_ddi_hdmi_level(struct d
- 	if (IS_GEN9_LP(dev_priv))
- 		return hdmi_level;
- 
--	if (IS_GEN9_BC(dev_priv)) {
-+	if (IS_CANNONLAKE(dev_priv)) {
-+		cnl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
-+		hdmi_default_entry = n_hdmi_entries - 1;
-+	} else if (IS_GEN9_BC(dev_priv)) {
- 		skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
- 		hdmi_default_entry = 8;
- 	} else if (IS_BROADWELL(dev_priv)) {
-@@ -688,9 +752,6 @@ static void intel_prepare_dp_ddi_buffers
- 	enum port port = intel_ddi_get_encoder_port(encoder);
- 	const struct ddi_buf_trans *ddi_translations;
- 
--	if (IS_GEN9_LP(dev_priv))
--		return;
--
- 	switch (encoder->type) {
- 	case INTEL_OUTPUT_EDP:
- 		ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
-@@ -741,9 +802,6 @@ static void intel_prepare_hdmi_ddi_buffe
- 	enum port port = intel_ddi_get_encoder_port(encoder);
- 	const struct ddi_buf_trans *ddi_translations_hdmi;
- 
--	if (IS_GEN9_LP(dev_priv))
--		return;
--
- 	hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
- 
- 	if (IS_GEN9_BC(dev_priv)) {
-@@ -785,7 +843,7 @@ static void intel_wait_ddi_buf_idle(stru
- 	DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
- }
- 
--static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
-+static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
- {
- 	switch (pll->id) {
- 	case DPLL_ID_WRPLL1:
-@@ -1154,7 +1212,7 @@ static int cnl_calc_wrpll_link(struct dr
- 	dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
- 
- 	dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
--		      DPLL_CFGCR0_DCO_FRAC_SHIFT) * ref_clock) / 0x8000;
-+		      DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
- 
- 	return dco_freq / (p0 * p1 * p2 * 5);
- }
-@@ -1822,10 +1880,17 @@ u8 intel_ddi_dp_voltage_max(struct intel
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- 	int n_entries;
- 
--	if (encoder->type == INTEL_OUTPUT_EDP)
--		intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
--	else
--		intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
-+	if (IS_CANNONLAKE(dev_priv)) {
-+		if (encoder->type == INTEL_OUTPUT_EDP)
-+			cnl_get_buf_trans_edp(dev_priv, &n_entries);
-+		else
-+			cnl_get_buf_trans_dp(dev_priv, &n_entries);
-+	} else {
-+		if (encoder->type == INTEL_OUTPUT_EDP)
-+			intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
-+		else
-+			intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);
-+	}
- 
- 	if (WARN_ON(n_entries < 1))
- 		n_entries = 1;
-@@ -1836,90 +1901,23 @@ u8 intel_ddi_dp_voltage_max(struct intel
- 		DP_TRAIN_VOLTAGE_SWING_MASK;
- }
- 
--static const struct cnl_ddi_buf_trans *
--cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
--		       u32 voltage, int *n_entries)
--{
--	if (voltage == VOLTAGE_INFO_0_85V) {
--		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
--		return cnl_ddi_translations_hdmi_0_85V;
--	} else if (voltage == VOLTAGE_INFO_0_95V) {
--		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
--		return cnl_ddi_translations_hdmi_0_95V;
--	} else if (voltage == VOLTAGE_INFO_1_05V) {
--		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
--		return cnl_ddi_translations_hdmi_1_05V;
--	}
--	return NULL;
--}
--
--static const struct cnl_ddi_buf_trans *
--cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
--		     u32 voltage, int *n_entries)
--{
--	if (voltage == VOLTAGE_INFO_0_85V) {
--		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
--		return cnl_ddi_translations_dp_0_85V;
--	} else if (voltage == VOLTAGE_INFO_0_95V) {
--		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
--		return cnl_ddi_translations_dp_0_95V;
--	} else if (voltage == VOLTAGE_INFO_1_05V) {
--		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
--		return cnl_ddi_translations_dp_1_05V;
--	}
--	return NULL;
--}
--
--static const struct cnl_ddi_buf_trans *
--cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
--		      u32 voltage, int *n_entries)
--{
--	if (dev_priv->vbt.edp.low_vswing) {
--		if (voltage == VOLTAGE_INFO_0_85V) {
--			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
--			return cnl_ddi_translations_edp_0_85V;
--		} else if (voltage == VOLTAGE_INFO_0_95V) {
--			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
--			return cnl_ddi_translations_edp_0_95V;
--		} else if (voltage == VOLTAGE_INFO_1_05V) {
--			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
--			return cnl_ddi_translations_edp_1_05V;
--		}
--		return NULL;
--	} else {
--		return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
--	}
--}
--
- static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
- 				    u32 level, enum port port, int type)
- {
- 	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
--	u32 n_entries, val, voltage;
-+	u32 n_entries, val;
- 	int ln;
- 
--	/*
--	 * Values for each port type are listed in
--	 * voltage swing programming tables.
--	 * Vccio voltage found in PORT_COMP_DW3.
--	 */
--	voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
--
- 	if (type == INTEL_OUTPUT_HDMI) {
--		ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
--							  voltage, &n_entries);
-+		ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
- 	} else if (type == INTEL_OUTPUT_DP) {
--		ddi_translations = cnl_get_buf_trans_dp(dev_priv,
--							voltage, &n_entries);
-+		ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
- 	} else if (type == INTEL_OUTPUT_EDP) {
--		ddi_translations = cnl_get_buf_trans_edp(dev_priv,
--							 voltage, &n_entries);
-+		ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
- 	}
- 
--	if (ddi_translations == NULL) {
--		MISSING_CASE(voltage);
-+	if (WARN_ON(ddi_translations == NULL))
- 		return;
--	}
- 
- 	if (level >= n_entries) {
- 		DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
-@@ -1942,7 +1940,7 @@ static void cnl_ddi_vswing_program(struc
- 	val |= RCOMP_SCALAR(0x98);
- 	I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
- 
--        /* Program PORT_TX_DW4 */
-+	/* Program PORT_TX_DW4 */
- 	/* We cannot write to GRP. It would overrite individual loadgen */
- 	for (ln = 0; ln < 4; ln++) {
- 		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
-@@ -1954,7 +1952,7 @@ static void cnl_ddi_vswing_program(struc
- 		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
- 	}
- 
--        /* Program PORT_TX_DW5 */
-+	/* Program PORT_TX_DW5 */
- 	/* All DW5 values are fixed for every table entry */
- 	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
- 	val &= ~RTERM_SELECT_MASK;
-@@ -1962,7 +1960,7 @@ static void cnl_ddi_vswing_program(struc
- 	val |= TAP3_DISABLE;
- 	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
- 
--        /* Program PORT_TX_DW7 */
-+	/* Program PORT_TX_DW7 */
- 	val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
- 	val &= ~N_SCALAR_MASK;
- 	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
-@@ -2055,33 +2053,46 @@ static uint32_t translate_signal_level(i
- 	return 0;
- }
- 
--uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
-+static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
- {
--	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
--	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
--	struct intel_encoder *encoder = &dport->base;
- 	uint8_t train_set = intel_dp->train_set[0];
- 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
- 					 DP_TRAIN_PRE_EMPHASIS_MASK);
-+
-+	return translate_signal_level(signal_levels);
-+}
-+
-+u32 bxt_signal_levels(struct intel_dp *intel_dp)
-+{
-+	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
-+	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
-+	struct intel_encoder *encoder = &dport->base;
- 	enum port port = dport->port;
--	uint32_t level;
-+	u32 level = intel_ddi_dp_level(intel_dp);
- 
--	level = translate_signal_level(signal_levels);
-+	if (IS_CANNONLAKE(dev_priv))
-+		cnl_ddi_vswing_sequence(encoder, level);
-+	else
-+		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
-+
-+	return 0;
-+}
-+
-+uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
-+{
-+	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
-+	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
-+	struct intel_encoder *encoder = &dport->base;
-+	uint32_t level = intel_ddi_dp_level(intel_dp);
- 
- 	if (IS_GEN9_BC(dev_priv))
--		skl_ddi_set_iboost(encoder, level);
--	else if (IS_GEN9_LP(dev_priv))
--		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
--	else if (IS_CANNONLAKE(dev_priv)) {
--		cnl_ddi_vswing_sequence(encoder, level);
--		/* DDI_BUF_CTL bits 27:24 are reserved on CNL */
--		return 0;
--	}
-+	    skl_ddi_set_iboost(encoder, level);
-+
- 	return DDI_BUF_TRANS_SELECT(level);
- }
- 
- static void intel_ddi_clk_select(struct intel_encoder *encoder,
--				 struct intel_shared_dpll *pll)
-+				 const struct intel_shared_dpll *pll)
- {
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- 	enum port port = intel_ddi_get_encoder_port(encoder);
-@@ -2129,6 +2140,7 @@ static void intel_ddi_pre_enable_dp(stru
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- 	enum port port = intel_ddi_get_encoder_port(encoder);
- 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
-+	uint32_t level = intel_ddi_dp_level(intel_dp);
- 
- 	WARN_ON(link_mst && (port == PORT_A || port == PORT_E));
- 
-@@ -2141,7 +2153,13 @@ static void intel_ddi_pre_enable_dp(stru
- 
- 	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
- 
--	intel_prepare_dp_ddi_buffers(encoder);
-+	if (IS_CANNONLAKE(dev_priv))
-+		cnl_ddi_vswing_sequence(encoder, level);
-+	else if (IS_GEN9_LP(dev_priv))
-+		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
-+	else
-+		intel_prepare_dp_ddi_buffers(encoder);
-+
- 	intel_ddi_init_dp_buf_reg(encoder);
- 	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
- 	intel_dp_start_link_train(intel_dp);
-@@ -2150,14 +2168,14 @@ static void intel_ddi_pre_enable_dp(stru
- }
- 
- static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
--				      bool has_hdmi_sink,
-+				      bool has_infoframe,
- 				      const struct intel_crtc_state *crtc_state,
- 				      const struct drm_connector_state *conn_state,
--				      struct intel_shared_dpll *pll)
-+				      const struct intel_shared_dpll *pll)
- {
--	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
-+	struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
-+	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
--	struct drm_encoder *drm_encoder = &encoder->base;
- 	enum port port = intel_ddi_get_encoder_port(encoder);
- 	int level = intel_ddi_hdmi_level(dev_priv, port);
- 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
-@@ -2167,23 +2185,25 @@ static void intel_ddi_pre_enable_hdmi(st
- 
- 	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
- 
--	intel_prepare_hdmi_ddi_buffers(encoder);
--	if (IS_GEN9_BC(dev_priv))
--		skl_ddi_set_iboost(encoder, level);
-+	if (IS_CANNONLAKE(dev_priv))
-+		cnl_ddi_vswing_sequence(encoder, level);
- 	else if (IS_GEN9_LP(dev_priv))
- 		bxt_ddi_vswing_sequence(dev_priv, level, port,
- 					INTEL_OUTPUT_HDMI);
--	else if (IS_CANNONLAKE(dev_priv))
--		cnl_ddi_vswing_sequence(encoder, level);
-+	else
-+		intel_prepare_hdmi_ddi_buffers(encoder);
-+
-+	if (IS_GEN9_BC(dev_priv))
-+		skl_ddi_set_iboost(encoder, level);
- 
--	intel_hdmi->set_infoframes(drm_encoder,
--				   has_hdmi_sink,
--				   crtc_state, conn_state);
-+	intel_dig_port->set_infoframes(&encoder->base,
-+				       has_infoframe,
-+				       crtc_state, conn_state);
- }
- 
- static void intel_ddi_pre_enable(struct intel_encoder *encoder,
--				 struct intel_crtc_state *pipe_config,
--				 struct drm_connector_state *conn_state)
-+				 const struct intel_crtc_state *pipe_config,
-+				 const struct drm_connector_state *conn_state)
- {
- 	int type = encoder->type;
- 
-@@ -2197,21 +2217,20 @@ static void intel_ddi_pre_enable(struct
- 	}
- 	if (type == INTEL_OUTPUT_HDMI) {
- 		intel_ddi_pre_enable_hdmi(encoder,
--					  pipe_config->has_hdmi_sink,
-+					  pipe_config->has_infoframe,
- 					  pipe_config, conn_state,
- 					  pipe_config->shared_dpll);
- 	}
- }
- 
- static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
--				   struct intel_crtc_state *old_crtc_state,
--				   struct drm_connector_state *old_conn_state)
-+				   const struct intel_crtc_state *old_crtc_state,
-+				   const struct drm_connector_state *old_conn_state)
- {
- 	struct drm_encoder *encoder = &intel_encoder->base;
- 	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
- 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
- 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
--	struct intel_dp *intel_dp = NULL;
- 	int type = intel_encoder->type;
- 	uint32_t val;
- 	bool wait = false;
-@@ -2219,7 +2238,8 @@ static void intel_ddi_post_disable(struc
- 	/* old_crtc_state and old_conn_state are NULL when called from DP_MST */
- 
- 	if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
--		intel_dp = enc_to_intel_dp(encoder);
-+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-+
- 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
- 	}
- 
-@@ -2238,7 +2258,14 @@ static void intel_ddi_post_disable(struc
- 	if (wait)
- 		intel_wait_ddi_buf_idle(dev_priv, port);
- 
--	if (intel_dp) {
-+	if (type == INTEL_OUTPUT_HDMI) {
-+		dig_port->set_infoframes(encoder, false,
-+					 old_crtc_state, old_conn_state);
-+	}
-+
-+	if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
-+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-+
- 		intel_edp_panel_vdd_on(intel_dp);
- 		intel_edp_panel_off(intel_dp);
- 	}
-@@ -2263,8 +2290,8 @@ static void intel_ddi_post_disable(struc
- }
- 
- void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
--				struct intel_crtc_state *old_crtc_state,
--				struct drm_connector_state *old_conn_state)
-+				const struct intel_crtc_state *old_crtc_state,
-+				const struct drm_connector_state *old_conn_state)
- {
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- 	uint32_t val;
-@@ -2296,8 +2323,8 @@ void intel_ddi_fdi_post_disable(struct i
- }
- 
- static void intel_enable_ddi(struct intel_encoder *intel_encoder,
--			     struct intel_crtc_state *pipe_config,
--			     struct drm_connector_state *conn_state)
-+			     const struct intel_crtc_state *pipe_config,
-+			     const struct drm_connector_state *conn_state)
- {
- 	struct drm_encoder *encoder = &intel_encoder->base;
- 	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
-@@ -2328,7 +2355,7 @@ static void intel_enable_ddi(struct inte
- 			intel_dp_stop_link_train(intel_dp);
- 
- 		intel_edp_backlight_on(pipe_config, conn_state);
--		intel_psr_enable(intel_dp);
-+		intel_psr_enable(intel_dp, pipe_config);
- 		intel_edp_drrs_enable(intel_dp, pipe_config);
- 	}
- 
-@@ -2337,8 +2364,8 @@ static void intel_enable_ddi(struct inte
- }
- 
- static void intel_disable_ddi(struct intel_encoder *intel_encoder,
--			      struct intel_crtc_state *old_crtc_state,
--			      struct drm_connector_state *old_conn_state)
-+			      const struct intel_crtc_state *old_crtc_state,
-+			      const struct drm_connector_state *old_conn_state)
- {
- 	struct drm_encoder *encoder = &intel_encoder->base;
- 	int type = intel_encoder->type;
-@@ -2356,14 +2383,14 @@ static void intel_disable_ddi(struct int
- 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- 
- 		intel_edp_drrs_disable(intel_dp, old_crtc_state);
--		intel_psr_disable(intel_dp);
-+		intel_psr_disable(intel_dp, old_crtc_state);
- 		intel_edp_backlight_off(old_conn_state);
- 	}
- }
- 
- static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
--				   struct intel_crtc_state *pipe_config,
--				   struct drm_connector_state *conn_state)
-+				   const struct intel_crtc_state *pipe_config,
-+				   const struct drm_connector_state *conn_state)
- {
- 	uint8_t mask = pipe_config->lane_lat_optim_mask;
- 
-@@ -2435,7 +2462,7 @@ void intel_ddi_get_config(struct intel_e
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
- 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
--	struct intel_hdmi *intel_hdmi;
-+	struct intel_digital_port *intel_dig_port;
- 	u32 temp, flags = 0;
- 
- 	/* XXX: DSI transcoder paranoia */
-@@ -2474,9 +2501,9 @@ void intel_ddi_get_config(struct intel_e
- 	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
- 	case TRANS_DDI_MODE_SELECT_HDMI:
- 		pipe_config->has_hdmi_sink = true;
--		intel_hdmi = enc_to_intel_hdmi(&encoder->base);
-+		intel_dig_port = enc_to_dig_port(&encoder->base);
- 
--		if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
-+		if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
- 			pipe_config->has_infoframe = true;
- 
- 		if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
-@@ -2729,6 +2756,8 @@ void intel_ddi_init(struct drm_i915_priv
- 	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
- 	intel_encoder->cloneable = 0;
- 
-+	intel_infoframe_init(intel_dig_port);
-+
- 	if (init_dp) {
- 		if (!intel_ddi_init_dp_connector(intel_dig_port))
- 			goto err;
---- linux-4.14/drivers/gpu/drm/i915/intel_device_info.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_device_info.c	2017-12-14 06:39:58.505903630 +0100
-@@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i
- #undef PRINT_FLAG
- }
- 
-+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
-+{
-+	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
-+	const u32 fuse2 = I915_READ(GEN8_FUSE2);
-+
-+	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
-+			    GEN10_F2_S_ENA_SHIFT;
-+	sseu->subslice_mask = (1 << 4) - 1;
-+	sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
-+				 GEN10_F2_SS_DIS_SHIFT);
-+
-+	sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
-+	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
-+	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
-+	sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
-+				     GEN10_EU_DIS_SS_MASK));
-+
-+	/*
-+	 * CNL is expected to always have a uniform distribution
-+	 * of EU across subslices with the exception that any one
-+	 * EU in any one subslice may be fused off for die
-+	 * recovery.
-+	 */
-+	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
-+				DIV_ROUND_UP(sseu->eu_total,
-+					     sseu_subslice_total(sseu)) : 0;
-+
-+	/* No restrictions on Power Gating */
-+	sseu->has_slice_pg = 1;
-+	sseu->has_subslice_pg = 1;
-+	sseu->has_eu_pg = 1;
-+}
-+
- static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
- {
- 	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
-@@ -343,7 +376,7 @@ void intel_device_info_runtime_init(stru
- 			info->num_sprites[pipe] = 1;
- 	}
- 
--	if (i915.disable_display) {
-+	if (i915_modparams.disable_display) {
- 		DRM_INFO("Display disabled (module parameter)\n");
- 		info->num_pipes = 0;
- 	} else if (info->num_pipes > 0 &&
-@@ -409,10 +442,10 @@ void intel_device_info_runtime_init(stru
- 		cherryview_sseu_info_init(dev_priv);
- 	else if (IS_BROADWELL(dev_priv))
- 		broadwell_sseu_info_init(dev_priv);
--	else if (INTEL_INFO(dev_priv)->gen >= 9)
-+	else if (INTEL_GEN(dev_priv) == 9)
- 		gen9_sseu_info_init(dev_priv);
--
--	info->has_snoop = !info->has_llc;
-+	else if (INTEL_GEN(dev_priv) >= 10)
-+		gen10_sseu_info_init(dev_priv);
- 
- 	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
- 	DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
---- linux-4.14/drivers/gpu/drm/i915/intel_display.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_display.c	2017-12-14 06:39:58.507903631 +0100
-@@ -3701,7 +3701,7 @@ void intel_prepare_reset(struct drm_i915
- 
- 
- 	/* reset doesn't touch the display */
--	if (!i915.force_reset_modeset_test &&
-+	if (!i915_modparams.force_reset_modeset_test &&
- 	    !gpu_reset_clobbers_display(dev_priv))
- 		return;
- 
-@@ -3757,7 +3757,7 @@ void intel_finish_reset(struct drm_i915_
- 	int ret;
- 
- 	/* reset doesn't touch the display */
--	if (!i915.force_reset_modeset_test &&
-+	if (!i915_modparams.force_reset_modeset_test &&
- 	    !gpu_reset_clobbers_display(dev_priv))
- 		return;
- 
-@@ -3770,8 +3770,8 @@ void intel_finish_reset(struct drm_i915_
- 	if (!gpu_reset_clobbers_display(dev_priv)) {
- 		/* for testing only restore the display */
- 		ret = __intel_display_resume(dev, state, ctx);
--			if (ret)
--				DRM_ERROR("Restoring old state failed with %i\n", ret);
-+		if (ret)
-+			DRM_ERROR("Restoring old state failed with %i\n", ret);
- 	} else {
- 		/*
- 		 * The display has been reset as well,
-@@ -3804,15 +3804,14 @@ unlock:
- 	clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
- }
- 
--static void intel_update_pipe_config(struct intel_crtc *crtc,
--				     struct intel_crtc_state *old_crtc_state)
-+static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
-+				     const struct intel_crtc_state *new_crtc_state)
- {
-+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
- 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
--	struct intel_crtc_state *pipe_config =
--		to_intel_crtc_state(crtc->base.state);
- 
- 	/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
--	crtc->base.mode = crtc->base.state->mode;
-+	crtc->base.mode = new_crtc_state->base.mode;
- 
- 	/*
- 	 * Update pipe size and adjust fitter if needed: the reason for this is
-@@ -3824,17 +3823,17 @@ static void intel_update_pipe_config(str
- 	 */
- 
- 	I915_WRITE(PIPESRC(crtc->pipe),
--		   ((pipe_config->pipe_src_w - 1) << 16) |
--		   (pipe_config->pipe_src_h - 1));
-+		   ((new_crtc_state->pipe_src_w - 1) << 16) |
-+		   (new_crtc_state->pipe_src_h - 1));
- 
- 	/* on skylake this is done by detaching scalers */
- 	if (INTEL_GEN(dev_priv) >= 9) {
- 		skl_detach_scalers(crtc);
- 
--		if (pipe_config->pch_pfit.enabled)
-+		if (new_crtc_state->pch_pfit.enabled)
- 			skylake_pfit_enable(crtc);
- 	} else if (HAS_PCH_SPLIT(dev_priv)) {
--		if (pipe_config->pch_pfit.enabled)
-+		if (new_crtc_state->pch_pfit.enabled)
- 			ironlake_pfit_enable(crtc);
- 		else if (old_crtc_state->pch_pfit.enabled)
- 			ironlake_pfit_disable(crtc, true);
-@@ -4957,7 +4956,8 @@ void hsw_enable_ips(struct intel_crtc *c
- 	assert_plane_enabled(dev_priv, crtc->plane);
- 	if (IS_BROADWELL(dev_priv)) {
- 		mutex_lock(&dev_priv->rps.hw_lock);
--		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
-+		WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
-+						IPS_ENABLE | IPS_PCODE_CONTROL));
- 		mutex_unlock(&dev_priv->rps.hw_lock);
- 		/* Quoting Art Runyan: "its not safe to expect any particular
- 		 * value in IPS_CTL bit 31 after enabling IPS through the
-@@ -5118,7 +5118,8 @@ static void intel_post_plane_update(stru
- 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
- 	struct drm_atomic_state *old_state = old_crtc_state->base.state;
- 	struct intel_crtc_state *pipe_config =
--		to_intel_crtc_state(crtc->base.state);
-+		intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
-+						crtc);
- 	struct drm_plane *primary = crtc->base.primary;
- 	struct drm_plane_state *old_pri_state =
- 		drm_atomic_get_existing_plane_state(old_state, primary);
-@@ -5130,7 +5131,8 @@ static void intel_post_plane_update(stru
- 
- 	if (old_pri_state) {
- 		struct intel_plane_state *primary_state =
--			to_intel_plane_state(primary->state);
-+			intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
-+							 to_intel_plane(primary));
- 		struct intel_plane_state *old_primary_state =
- 			to_intel_plane_state(old_pri_state);
- 
-@@ -5159,7 +5161,8 @@ static void intel_pre_plane_update(struc
- 
- 	if (old_pri_state) {
- 		struct intel_plane_state *primary_state =
--			to_intel_plane_state(primary->state);
-+			intel_atomic_get_new_plane_state(old_intel_state,
-+							 to_intel_plane(primary));
- 		struct intel_plane_state *old_primary_state =
- 			to_intel_plane_state(old_pri_state);
- 
-@@ -6038,7 +6041,7 @@ static void intel_crtc_disable_noatomic(
- 	intel_crtc->enabled_power_domains = 0;
- 
- 	dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
--	dev_priv->min_pixclk[intel_crtc->pipe] = 0;
-+	dev_priv->min_cdclk[intel_crtc->pipe] = 0;
- }
- 
- /*
-@@ -6283,6 +6286,9 @@ retry:
- static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
- 				     struct intel_crtc_state *pipe_config)
- {
-+	if (pipe_config->ips_force_disable)
-+		return false;
-+
- 	if (pipe_config->pipe_bpp > 24)
- 		return false;
- 
-@@ -6307,7 +6313,7 @@ static void hsw_compute_ips_config(struc
- 	struct drm_device *dev = crtc->base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 
--	pipe_config->ips_enabled = i915.enable_ips &&
-+	pipe_config->ips_enabled = i915_modparams.enable_ips &&
- 		hsw_crtc_supports_ips(crtc) &&
- 		pipe_config_supports_ips(dev_priv, pipe_config);
- }
-@@ -6488,8 +6494,8 @@ intel_link_compute_m_n(int bits_per_pixe
- 
- static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
- {
--	if (i915.panel_use_ssc >= 0)
--		return i915.panel_use_ssc != 0;
-+	if (i915_modparams.panel_use_ssc >= 0)
-+		return i915_modparams.panel_use_ssc != 0;
- 	return dev_priv->vbt.lvds_use_ssc
- 		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
- }
-@@ -9039,7 +9045,7 @@ static void cannonlake_get_ddi_pll(struc
- 	u32 temp;
- 
- 	temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
--	id = temp >> (port * 2);
-+	id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
- 
- 	if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
- 		return;
-@@ -9304,11 +9310,11 @@ static bool haswell_get_pipe_config(stru
- 	pipe_config->gamma_mode =
- 		I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
- 
--	if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) {
-+	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
- 		u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
- 		bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
- 
--		if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >= 10) {
-+		if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
- 			bool blend_mode_420 = tmp &
- 					      PIPEMISC_YUV420_MODE_FULL_BLEND;
- 
-@@ -9753,7 +9759,7 @@ static void i9xx_disable_cursor(struct i
- 
- 
- /* VESA 640x480x72Hz mode to set on the pipe */
--static struct drm_display_mode load_detect_mode = {
-+static const struct drm_display_mode load_detect_mode = {
- 	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
- 		 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
- };
-@@ -9788,7 +9794,7 @@ intel_framebuffer_pitch_for_width(int wi
- }
- 
- static u32
--intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
-+intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp)
- {
- 	u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
- 	return PAGE_ALIGN(pitch * mode->vdisplay);
-@@ -9796,7 +9802,7 @@ intel_framebuffer_size_for_mode(struct d
- 
- static struct drm_framebuffer *
- intel_framebuffer_create_for_mode(struct drm_device *dev,
--				  struct drm_display_mode *mode,
-+				  const struct drm_display_mode *mode,
- 				  int depth, int bpp)
- {
- 	struct drm_framebuffer *fb;
-@@ -9823,7 +9829,7 @@ intel_framebuffer_create_for_mode(struct
- 
- static struct drm_framebuffer *
- mode_fits_in_fbdev(struct drm_device *dev,
--		   struct drm_display_mode *mode)
-+		   const struct drm_display_mode *mode)
- {
- #ifdef CONFIG_DRM_FBDEV_EMULATION
- 	struct drm_i915_private *dev_priv = to_i915(dev);
-@@ -9856,7 +9862,7 @@ mode_fits_in_fbdev(struct drm_device *de
- 
- static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
- 					   struct drm_crtc *crtc,
--					   struct drm_display_mode *mode,
-+					   const struct drm_display_mode *mode,
- 					   struct drm_framebuffer *fb,
- 					   int x, int y)
- {
-@@ -9890,7 +9896,7 @@ static int intel_modeset_setup_plane_sta
- }
- 
- int intel_get_load_detect_pipe(struct drm_connector *connector,
--			       struct drm_display_mode *mode,
-+			       const struct drm_display_mode *mode,
- 			       struct intel_load_detect_pipe *old,
- 			       struct drm_modeset_acquire_ctx *ctx)
- {
-@@ -10218,7 +10224,7 @@ int intel_dotclock_calculate(int link_fr
- 	if (!m_n->link_n)
- 		return 0;
- 
--	return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
-+	return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
- }
- 
- static void ironlake_pch_clock_get(struct intel_crtc *crtc,
-@@ -10341,7 +10347,7 @@ static bool intel_wm_need_update(struct
- 	return false;
- }
- 
--static bool needs_scaling(struct intel_plane_state *state)
-+static bool needs_scaling(const struct intel_plane_state *state)
- {
- 	int src_w = drm_rect_width(&state->base.src) >> 16;
- 	int src_h = drm_rect_height(&state->base.src) >> 16;
-@@ -10351,7 +10357,9 @@ static bool needs_scaling(struct intel_p
- 	return (src_w != dst_w || src_h != dst_h);
- }
- 
--int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
-+int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
-+				    struct drm_crtc_state *crtc_state,
-+				    const struct intel_plane_state *old_plane_state,
- 				    struct drm_plane_state *plane_state)
- {
- 	struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
-@@ -10360,10 +10368,8 @@ int intel_plane_atomic_calc_changes(stru
- 	struct intel_plane *plane = to_intel_plane(plane_state->plane);
- 	struct drm_device *dev = crtc->dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
--	struct intel_plane_state *old_plane_state =
--		to_intel_plane_state(plane->base.state);
- 	bool mode_changed = needs_modeset(crtc_state);
--	bool was_crtc_enabled = crtc->state->active;
-+	bool was_crtc_enabled = old_crtc_state->base.active;
- 	bool is_crtc_enabled = crtc_state->active;
- 	bool turn_off, turn_on, visible, was_visible;
- 	struct drm_framebuffer *fb = plane_state->fb;
-@@ -10854,7 +10860,7 @@ clear_intel_crtc_state(struct intel_crtc
- 	struct intel_dpll_hw_state dpll_hw_state;
- 	struct intel_shared_dpll *shared_dpll;
- 	struct intel_crtc_wm_state wm_state;
--	bool force_thru;
-+	bool force_thru, ips_force_disable;
- 
- 	/* FIXME: before the switch to atomic started, a new pipe_config was
- 	 * kzalloc'd. Code that depends on any field being zero should be
-@@ -10865,6 +10871,7 @@ clear_intel_crtc_state(struct intel_crtc
- 	shared_dpll = crtc_state->shared_dpll;
- 	dpll_hw_state = crtc_state->dpll_hw_state;
- 	force_thru = crtc_state->pch_pfit.force_thru;
-+	ips_force_disable = crtc_state->ips_force_disable;
- 	if (IS_G4X(dev_priv) ||
- 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- 		wm_state = crtc_state->wm;
-@@ -10878,6 +10885,7 @@ clear_intel_crtc_state(struct intel_crtc
- 	crtc_state->shared_dpll = shared_dpll;
- 	crtc_state->dpll_hw_state = dpll_hw_state;
- 	crtc_state->pch_pfit.force_thru = force_thru;
-+	crtc_state->ips_force_disable = ips_force_disable;
- 	if (IS_G4X(dev_priv) ||
- 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- 		crtc_state->wm = wm_state;
-@@ -12080,7 +12088,7 @@ static int intel_atomic_check(struct drm
- 			return ret;
- 		}
- 
--		if (i915.fastboot &&
-+		if (i915_modparams.fastboot &&
- 		    intel_pipe_config_compare(dev_priv,
- 					to_intel_crtc_state(old_crtc_state),
- 					pipe_config, true)) {
-@@ -12133,73 +12141,10 @@ u32 intel_crtc_get_vblank_counter(struct
- 	return dev->driver->get_vblank_counter(dev, crtc->pipe);
- }
- 
--static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
--					  struct drm_i915_private *dev_priv,
--					  unsigned crtc_mask)
--{
--	unsigned last_vblank_count[I915_MAX_PIPES];
--	enum pipe pipe;
--	int ret;
--
--	if (!crtc_mask)
--		return;
--
--	for_each_pipe(dev_priv, pipe) {
--		struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
--								  pipe);
--
--		if (!((1 << pipe) & crtc_mask))
--			continue;
--
--		ret = drm_crtc_vblank_get(&crtc->base);
--		if (WARN_ON(ret != 0)) {
--			crtc_mask &= ~(1 << pipe);
--			continue;
--		}
--
--		last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
--	}
--
--	for_each_pipe(dev_priv, pipe) {
--		struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
--								  pipe);
--		long lret;
--
--		if (!((1 << pipe) & crtc_mask))
--			continue;
--
--		lret = wait_event_timeout(dev->vblank[pipe].queue,
--				last_vblank_count[pipe] !=
--					drm_crtc_vblank_count(&crtc->base),
--				msecs_to_jiffies(50));
--
--		WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
--
--		drm_crtc_vblank_put(&crtc->base);
--	}
--}
--
--static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
--{
--	/* fb updated, need to unpin old fb */
--	if (crtc_state->fb_changed)
--		return true;
--
--	/* wm changes, need vblank before final wm's */
--	if (crtc_state->update_wm_post)
--		return true;
--
--	if (crtc_state->wm.need_postvbl_update)
--		return true;
--
--	return false;
--}
--
- static void intel_update_crtc(struct drm_crtc *crtc,
- 			      struct drm_atomic_state *state,
- 			      struct drm_crtc_state *old_crtc_state,
--			      struct drm_crtc_state *new_crtc_state,
--			      unsigned int *crtc_vblank_mask)
-+			      struct drm_crtc_state *new_crtc_state)
- {
- 	struct drm_device *dev = crtc->dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
-@@ -12222,13 +12167,9 @@ static void intel_update_crtc(struct drm
- 	}
- 
- 	drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
--
--	if (needs_vblank_wait(pipe_config))
--		*crtc_vblank_mask |= drm_crtc_mask(crtc);
- }
- 
--static void intel_update_crtcs(struct drm_atomic_state *state,
--			       unsigned int *crtc_vblank_mask)
-+static void intel_update_crtcs(struct drm_atomic_state *state)
- {
- 	struct drm_crtc *crtc;
- 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
-@@ -12239,12 +12180,11 @@ static void intel_update_crtcs(struct dr
- 			continue;
- 
- 		intel_update_crtc(crtc, state, old_crtc_state,
--				  new_crtc_state, crtc_vblank_mask);
-+				  new_crtc_state);
- 	}
- }
- 
--static void skl_update_crtcs(struct drm_atomic_state *state,
--			     unsigned int *crtc_vblank_mask)
-+static void skl_update_crtcs(struct drm_atomic_state *state)
- {
- 	struct drm_i915_private *dev_priv = to_i915(state->dev);
- 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-@@ -12278,7 +12218,7 @@ static void skl_update_crtcs(struct drm_
- 			unsigned int cmask = drm_crtc_mask(crtc);
- 
- 			intel_crtc = to_intel_crtc(crtc);
--			cstate = to_intel_crtc_state(crtc->state);
-+			cstate = to_intel_crtc_state(new_crtc_state);
- 			pipe = intel_crtc->pipe;
- 
- 			if (updated & cmask || !cstate->base.active)
-@@ -12303,7 +12243,7 @@ static void skl_update_crtcs(struct drm_
- 				vbl_wait = true;
- 
- 			intel_update_crtc(crtc, state, old_crtc_state,
--					  new_crtc_state, crtc_vblank_mask);
-+					  new_crtc_state);
- 
- 			if (vbl_wait)
- 				intel_wait_for_vblank(dev_priv, pipe);
-@@ -12364,7 +12304,6 @@ static void intel_atomic_commit_tail(str
- 	struct drm_crtc *crtc;
- 	struct intel_crtc_state *intel_cstate;
- 	u64 put_domains[I915_MAX_PIPES] = {};
--	unsigned crtc_vblank_mask = 0;
- 	int i;
- 
- 	intel_atomic_commit_fence_wait(intel_state);
-@@ -12405,7 +12344,7 @@ static void intel_atomic_commit_tail(str
- 			intel_check_cpu_fifo_underruns(dev_priv);
- 			intel_check_pch_fifo_underruns(dev_priv);
- 
--			if (!crtc->state->active) {
-+			if (!new_crtc_state->active) {
- 				/*
- 				 * Make sure we don't call initial_watermarks
- 				 * for ILK-style watermark updates.
-@@ -12414,7 +12353,7 @@ static void intel_atomic_commit_tail(str
- 				 */
- 				if (INTEL_GEN(dev_priv) >= 9)
- 					dev_priv->display.initial_watermarks(intel_state,
--									     to_intel_crtc_state(crtc->state));
-+									     to_intel_crtc_state(new_crtc_state));
- 			}
- 		}
- 	}
-@@ -12453,7 +12392,7 @@ static void intel_atomic_commit_tail(str
- 	}
- 
- 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
--	dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
-+	dev_priv->display.update_crtcs(state);
- 
- 	/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
- 	 * already, but still need the state for the delayed optimization. To
-@@ -12464,8 +12403,7 @@ static void intel_atomic_commit_tail(str
- 	 * - switch over to the vblank wait helper in the core after that since
- 	 *   we don't need out special handling any more.
- 	 */
--	if (!state->legacy_cursor_update)
--		intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
-+	drm_atomic_helper_wait_for_flip_done(dev, state);
- 
- 	/*
- 	 * Now that the vblank has passed, we can go ahead and program the
-@@ -12628,8 +12566,8 @@ static int intel_atomic_commit(struct dr
- 	intel_atomic_track_fbs(state);
- 
- 	if (intel_state->modeset) {
--		memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
--		       sizeof(intel_state->min_pixclk));
-+		memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
-+		       sizeof(intel_state->min_cdclk));
- 		dev_priv->active_crtcs = intel_state->active_crtcs;
- 		dev_priv->cdclk.logical = intel_state->cdclk.logical;
- 		dev_priv->cdclk.actual = intel_state->cdclk.actual;
-@@ -12658,6 +12596,58 @@ static const struct drm_crtc_funcs intel
- 	.set_crc_source = intel_crtc_set_crc_source,
- };
- 
-+struct wait_rps_boost {
-+	struct wait_queue_entry wait;
-+
-+	struct drm_crtc *crtc;
-+	struct drm_i915_gem_request *request;
-+};
-+
-+static int do_rps_boost(struct wait_queue_entry *_wait,
-+			unsigned mode, int sync, void *key)
-+{
-+	struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
-+	struct drm_i915_gem_request *rq = wait->request;
-+
-+	gen6_rps_boost(rq, NULL);
-+	i915_gem_request_put(rq);
-+
-+	drm_crtc_vblank_put(wait->crtc);
-+
-+	list_del(&wait->wait.entry);
-+	kfree(wait);
-+	return 1;
-+}
-+
-+static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
-+				       struct dma_fence *fence)
-+{
-+	struct wait_rps_boost *wait;
-+
-+	if (!dma_fence_is_i915(fence))
-+		return;
-+
-+	if (INTEL_GEN(to_i915(crtc->dev)) < 6)
-+		return;
-+
-+	if (drm_crtc_vblank_get(crtc))
-+		return;
-+
-+	wait = kmalloc(sizeof(*wait), GFP_KERNEL);
-+	if (!wait) {
-+		drm_crtc_vblank_put(crtc);
-+		return;
-+	}
-+
-+	wait->request = to_request(dma_fence_get(fence));
-+	wait->crtc = crtc;
-+
-+	wait->wait.func = do_rps_boost;
-+	wait->wait.flags = 0;
-+
-+	add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
-+}
-+
- /**
-  * intel_prepare_plane_fb - Prepare fb for usage on plane
-  * @plane: drm plane to prepare for
-@@ -12755,12 +12745,22 @@ intel_prepare_plane_fb(struct drm_plane
- 		return ret;
- 
- 	if (!new_state->fence) { /* implicit fencing */
-+		struct dma_fence *fence;
-+
- 		ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
- 						      obj->resv, NULL,
- 						      false, I915_FENCE_TIMEOUT,
- 						      GFP_KERNEL);
- 		if (ret < 0)
- 			return ret;
-+
-+		fence = reservation_object_get_excl_rcu(obj->resv);
-+		if (fence) {
-+			add_rps_boost_after_vblank(new_state->crtc, fence);
-+			dma_fence_put(fence);
-+		}
-+	} else {
-+		add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
- 	}
- 
- 	return 0;
-@@ -12877,29 +12877,29 @@ static void intel_begin_crtc_commit(stru
- 	struct drm_device *dev = crtc->dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
--	struct intel_crtc_state *intel_cstate =
--		to_intel_crtc_state(crtc->state);
- 	struct intel_crtc_state *old_intel_cstate =
- 		to_intel_crtc_state(old_crtc_state);
- 	struct intel_atomic_state *old_intel_state =
- 		to_intel_atomic_state(old_crtc_state->state);
--	bool modeset = needs_modeset(crtc->state);
-+	struct intel_crtc_state *intel_cstate =
-+		intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
-+	bool modeset = needs_modeset(&intel_cstate->base);
- 
- 	if (!modeset &&
- 	    (intel_cstate->base.color_mgmt_changed ||
- 	     intel_cstate->update_pipe)) {
--		intel_color_set_csc(crtc->state);
--		intel_color_load_luts(crtc->state);
-+		intel_color_set_csc(&intel_cstate->base);
-+		intel_color_load_luts(&intel_cstate->base);
- 	}
- 
- 	/* Perform vblank evasion around commit operation */
--	intel_pipe_update_start(intel_crtc);
-+	intel_pipe_update_start(intel_cstate);
- 
- 	if (modeset)
- 		goto out;
- 
- 	if (intel_cstate->update_pipe)
--		intel_update_pipe_config(intel_crtc, old_intel_cstate);
-+		intel_update_pipe_config(old_intel_cstate, intel_cstate);
- 	else if (INTEL_GEN(dev_priv) >= 9)
- 		skl_detach_scalers(intel_crtc);
- 
-@@ -12913,8 +12913,12 @@ static void intel_finish_crtc_commit(str
- 				     struct drm_crtc_state *old_crtc_state)
- {
- 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-+	struct intel_atomic_state *old_intel_state =
-+		to_intel_atomic_state(old_crtc_state->state);
-+	struct intel_crtc_state *new_crtc_state =
-+		intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
- 
--	intel_pipe_update_end(intel_crtc);
-+	intel_pipe_update_end(new_crtc_state);
- }
- 
- /**
-@@ -13063,6 +13067,14 @@ intel_legacy_cursor_update(struct drm_pl
- 		goto slow;
- 
- 	old_plane_state = plane->state;
-+	/*
-+	 * Don't do an async update if there is an outstanding commit modifying
-+	 * the plane.  This prevents our async update's changes from getting
-+	 * overridden by a previous synchronous update's state.
-+	 */
-+	if (old_plane_state->commit &&
-+	    !try_wait_for_completion(&old_plane_state->commit->hw_done))
-+		goto slow;
- 
- 	/*
- 	 * If any parameters change that may affect watermarks,
-@@ -13093,6 +13105,8 @@ intel_legacy_cursor_update(struct drm_pl
- 	new_plane_state->crtc_h = crtc_h;
- 
- 	ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
-+						  to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
-+						  to_intel_plane_state(plane->state),
- 						  to_intel_plane_state(new_plane_state));
- 	if (ret)
- 		goto out_free;
-@@ -13122,17 +13136,12 @@ intel_legacy_cursor_update(struct drm_pl
- 	}
- 
- 	old_fb = old_plane_state->fb;
--	old_vma = to_intel_plane_state(old_plane_state)->vma;
- 
- 	i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
- 			  intel_plane->frontbuffer_bit);
- 
- 	/* Swap plane state */
--	new_plane_state->fence = old_plane_state->fence;
--	*to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
--	new_plane_state->fence = NULL;
--	new_plane_state->fb = old_fb;
--	to_intel_plane_state(new_plane_state)->vma = NULL;
-+	plane->state = new_plane_state;
- 
- 	if (plane->state->visible) {
- 		trace_intel_update_plane(plane, to_intel_crtc(crtc));
-@@ -13144,13 +13153,17 @@ intel_legacy_cursor_update(struct drm_pl
- 		intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
- 	}
- 
-+	old_vma = fetch_and_zero(&to_intel_plane_state(old_plane_state)->vma);
- 	if (old_vma)
- 		intel_unpin_fb_vma(old_vma);
- 
- out_unlock:
- 	mutex_unlock(&dev_priv->drm.struct_mutex);
- out_free:
--	intel_plane_destroy_state(plane, new_plane_state);
-+	if (ret)
-+		intel_plane_destroy_state(plane, new_plane_state);
-+	else
-+		intel_plane_destroy_state(plane, old_plane_state);
- 	return ret;
- 
- slow:
-@@ -13501,7 +13514,7 @@ int intel_get_pipe_from_crtc_id(struct d
- 	struct drm_crtc *drmmode_crtc;
- 	struct intel_crtc *crtc;
- 
--	drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
-+	drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
- 	if (!drmmode_crtc)
- 		return -ENOENT;
- 
-@@ -13665,7 +13678,7 @@ static void intel_setup_outputs(struct d
- 
- 	} else if (HAS_PCH_SPLIT(dev_priv)) {
- 		int found;
--		dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
-+		dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
- 
- 		if (has_edp_a(dev_priv))
- 			intel_dp_init(dev_priv, DP_A, PORT_A);
-@@ -13708,14 +13721,14 @@ static void intel_setup_outputs(struct d
- 		 * trust the port type the VBT declares as we've seen at least
- 		 * HDMI ports that the VBT claim are DP or eDP.
- 		 */
--		has_edp = intel_dp_is_edp(dev_priv, PORT_B);
-+		has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
- 		has_port = intel_bios_is_port_present(dev_priv, PORT_B);
- 		if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
- 			has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
- 		if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
- 			intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
- 
--		has_edp = intel_dp_is_edp(dev_priv, PORT_C);
-+		has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
- 		has_port = intel_bios_is_port_present(dev_priv, PORT_C);
- 		if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
- 			has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
-@@ -14208,7 +14221,7 @@ void intel_init_display_hooks(struct drm
- 		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
- 	}
- 
--	if (dev_priv->info.gen >= 9)
-+	if (INTEL_GEN(dev_priv) >= 9)
- 		dev_priv->display.update_crtcs = skl_update_crtcs;
- 	else
- 		dev_priv->display.update_crtcs = intel_update_crtcs;
-@@ -15032,7 +15045,7 @@ static void intel_modeset_readout_hw_sta
- 	for_each_intel_crtc(dev, crtc) {
- 		struct intel_crtc_state *crtc_state =
- 			to_intel_crtc_state(crtc->base.state);
--		int pixclk = 0;
-+		int min_cdclk = 0;
- 
- 		memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
- 		if (crtc_state->base.active) {
-@@ -15053,22 +15066,18 @@ static void intel_modeset_readout_hw_sta
- 
- 			intel_crtc_compute_pixel_rate(crtc_state);
- 
--			if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
--			    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
--				pixclk = crtc_state->pixel_rate;
--			else
--				WARN_ON(dev_priv->display.modeset_calc_cdclk);
--
--			/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
--			if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
--				pixclk = DIV_ROUND_UP(pixclk * 100, 95);
-+			if (dev_priv->display.modeset_calc_cdclk) {
-+				min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
-+				if (WARN_ON(min_cdclk < 0))
-+					min_cdclk = 0;
-+			}
- 
- 			drm_calc_timestamping_constants(&crtc->base,
- 							&crtc_state->base.adjusted_mode);
- 			update_scanline_offset(crtc);
- 		}
- 
--		dev_priv->min_pixclk[crtc->pipe] = pixclk;
-+		dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
- 
- 		intel_pipe_config_sanity_check(dev_priv, crtc_state);
- 	}
-@@ -15186,6 +15195,7 @@ void intel_display_resume(struct drm_dev
- 	if (!ret)
- 		ret = __intel_display_resume(dev, state, &ctx);
- 
-+	intel_enable_ipc(dev_priv);
- 	drm_modeset_drop_locks(&ctx);
- 	drm_modeset_acquire_fini(&ctx);
- 
---- linux-4.14/drivers/gpu/drm/i915/intel_dp_aux_backlight.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_dp_aux_backlight.c	2017-12-14 06:39:58.507903631 +0100
-@@ -264,7 +264,7 @@ int intel_dp_aux_init_backlight_funcs(st
- {
- 	struct intel_panel *panel = &intel_connector->panel;
- 
--	if (!i915.enable_dpcd_backlight)
-+	if (!i915_modparams.enable_dpcd_backlight)
- 		return -ENODEV;
- 
- 	if (!intel_dp_aux_display_control_capable(intel_connector))
---- linux-4.14/drivers/gpu/drm/i915/intel_dp.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_dp.c	2017-12-14 06:39:58.507903631 +0100
-@@ -42,6 +42,7 @@
- #include "i915_drv.h"
- 
- #define DP_LINK_CHECK_TIMEOUT	(10 * 1000)
-+#define DP_DPRX_ESI_LEN 14
- 
- /* Compliance test status bits  */
- #define INTEL_DP_RESOLUTION_SHIFT_MASK	0
-@@ -103,13 +104,13 @@ static const int cnl_rates[] = { 162000,
- static const int default_rates[] = { 162000, 270000, 540000 };
- 
- /**
-- * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
-+ * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
-  * @intel_dp: DP struct
-  *
-  * If a CPU or PCH DP output is attached to an eDP panel, this function
-  * will return true, and false otherwise.
-  */
--static bool is_edp(struct intel_dp *intel_dp)
-+bool intel_dp_is_edp(struct intel_dp *intel_dp)
- {
- 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- 
-@@ -388,7 +389,7 @@ intel_dp_mode_valid(struct drm_connector
- 
- 	max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
- 
--	if (is_edp(intel_dp) && fixed_mode) {
-+	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
- 		if (mode->hdisplay > fixed_mode->hdisplay)
- 			return MODE_PANEL;
- 
-@@ -597,7 +598,7 @@ vlv_power_sequencer_pipe(struct intel_dp
- 	lockdep_assert_held(&dev_priv->pps_mutex);
- 
- 	/* We should never land here with regular DP ports */
--	WARN_ON(!is_edp(intel_dp));
-+	WARN_ON(!intel_dp_is_edp(intel_dp));
- 
- 	WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
- 		intel_dp->active_pipe != intel_dp->pps_pipe);
-@@ -644,7 +645,7 @@ bxt_power_sequencer_idx(struct intel_dp
- 	lockdep_assert_held(&dev_priv->pps_mutex);
- 
- 	/* We should never land here with regular DP ports */
--	WARN_ON(!is_edp(intel_dp));
-+	WARN_ON(!intel_dp_is_edp(intel_dp));
- 
- 	/*
- 	 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
-@@ -847,7 +848,7 @@ static int edp_notify_handler(struct not
- 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 
--	if (!is_edp(intel_dp) || code != SYS_RESTART)
-+	if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
- 		return 0;
- 
- 	pps_lock(intel_dp);
-@@ -907,7 +908,7 @@ intel_dp_check_edp(struct intel_dp *inte
- 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 
--	if (!is_edp(intel_dp))
-+	if (!intel_dp_is_edp(intel_dp))
- 		return;
- 
- 	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
-@@ -1681,7 +1682,7 @@ intel_dp_compute_config(struct intel_enc
- 	else
- 		pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
- 
--	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
-+	if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
- 		struct drm_display_mode *panel_mode =
- 			intel_connector->panel.alt_fixed_mode;
- 		struct drm_display_mode *req_mode = &pipe_config->base.mode;
-@@ -1736,7 +1737,7 @@ intel_dp_compute_config(struct intel_enc
- 	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
- 	 * bpc in between. */
- 	bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
--	if (is_edp(intel_dp)) {
-+	if (intel_dp_is_edp(intel_dp)) {
- 
- 		/* Get bpp from vbt only for panels that dont have bpp in edid */
- 		if (intel_connector->base.display_info.bpc == 0 &&
-@@ -1829,7 +1830,7 @@ found:
- 	 * DPLL0 VCO may need to be adjusted to get the correct
- 	 * clock for eDP. This will affect cdclk as well.
- 	 */
--	if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
-+	if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
- 		int vco;
- 
- 		switch (pipe_config->port_clock / 2) {
-@@ -1861,7 +1862,7 @@ void intel_dp_set_link_params(struct int
- }
- 
- static void intel_dp_prepare(struct intel_encoder *encoder,
--			     struct intel_crtc_state *pipe_config)
-+			     const struct intel_crtc_state *pipe_config)
- {
- 	struct drm_device *dev = encoder->base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
-@@ -2069,7 +2070,7 @@ static bool edp_panel_vdd_on(struct inte
- 
- 	lockdep_assert_held(&dev_priv->pps_mutex);
- 
--	if (!is_edp(intel_dp))
-+	if (!intel_dp_is_edp(intel_dp))
- 		return false;
- 
- 	cancel_delayed_work(&intel_dp->panel_vdd_work);
-@@ -2119,7 +2120,7 @@ void intel_edp_panel_vdd_on(struct intel
- {
- 	bool vdd;
- 
--	if (!is_edp(intel_dp))
-+	if (!intel_dp_is_edp(intel_dp))
- 		return;
- 
- 	pps_lock(intel_dp);
-@@ -2203,7 +2204,7 @@ static void edp_panel_vdd_off(struct int
- 
- 	lockdep_assert_held(&dev_priv->pps_mutex);
- 
--	if (!is_edp(intel_dp))
-+	if (!intel_dp_is_edp(intel_dp))
- 		return;
- 
- 	I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
-@@ -2226,7 +2227,7 @@ static void edp_panel_on(struct intel_dp
- 
- 	lockdep_assert_held(&dev_priv->pps_mutex);
- 
--	if (!is_edp(intel_dp))
-+	if (!intel_dp_is_edp(intel_dp))
- 		return;
- 
- 	DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
-@@ -2267,7 +2268,7 @@ static void edp_panel_on(struct intel_dp
- 
- void intel_edp_panel_on(struct intel_dp *intel_dp)
- {
--	if (!is_edp(intel_dp))
-+	if (!intel_dp_is_edp(intel_dp))
- 		return;
- 
- 	pps_lock(intel_dp);
-@@ -2285,7 +2286,7 @@ static void edp_panel_off(struct intel_d
- 
- 	lockdep_assert_held(&dev_priv->pps_mutex);
- 
--	if (!is_edp(intel_dp))
-+	if (!intel_dp_is_edp(intel_dp))
- 		return;
- 
- 	DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
-@@ -2316,7 +2317,7 @@ static void edp_panel_off(struct intel_d
- 
- void intel_edp_panel_off(struct intel_dp *intel_dp)
- {
--	if (!is_edp(intel_dp))
-+	if (!intel_dp_is_edp(intel_dp))
- 		return;
- 
- 	pps_lock(intel_dp);
-@@ -2360,7 +2361,7 @@ void intel_edp_backlight_on(const struct
- {
- 	struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
- 
--	if (!is_edp(intel_dp))
-+	if (!intel_dp_is_edp(intel_dp))
- 		return;
- 
- 	DRM_DEBUG_KMS("\n");
-@@ -2377,7 +2378,7 @@ static void _intel_edp_backlight_off(str
- 	u32 pp;
- 	i915_reg_t pp_ctrl_reg;
- 
--	if (!is_edp(intel_dp))
-+	if (!intel_dp_is_edp(intel_dp))
- 		return;
- 
- 	pps_lock(intel_dp);
-@@ -2401,7 +2402,7 @@ void intel_edp_backlight_off(const struc
- {
- 	struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
- 
--	if (!is_edp(intel_dp))
-+	if (!intel_dp_is_edp(intel_dp))
- 		return;
- 
- 	DRM_DEBUG_KMS("\n");
-@@ -2461,7 +2462,7 @@ static void assert_edp_pll(struct drm_i9
- #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
- 
- static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
--				struct intel_crtc_state *pipe_config)
-+				const struct intel_crtc_state *pipe_config)
- {
- 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
- 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-@@ -2666,7 +2667,7 @@ static void intel_dp_get_config(struct i
- 		intel_dotclock_calculate(pipe_config->port_clock,
- 					 &pipe_config->dp_m_n);
- 
--	if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
-+	if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
- 	    pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
- 		/*
- 		 * This is a big fat ugly hack.
-@@ -2688,33 +2689,55 @@ static void intel_dp_get_config(struct i
- }
- 
- static void intel_disable_dp(struct intel_encoder *encoder,
--			     struct intel_crtc_state *old_crtc_state,
--			     struct drm_connector_state *old_conn_state)
-+			     const struct intel_crtc_state *old_crtc_state,
-+			     const struct drm_connector_state *old_conn_state)
- {
- 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
--	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- 
- 	if (old_crtc_state->has_audio)
- 		intel_audio_codec_disable(encoder);
- 
--	if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
--		intel_psr_disable(intel_dp);
--
- 	/* Make sure the panel is off before trying to change the mode. But also
- 	 * ensure that we have vdd while we switch off the panel. */
- 	intel_edp_panel_vdd_on(intel_dp);
- 	intel_edp_backlight_off(old_conn_state);
- 	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
- 	intel_edp_panel_off(intel_dp);
-+}
-+
-+static void g4x_disable_dp(struct intel_encoder *encoder,
-+			   const struct intel_crtc_state *old_crtc_state,
-+			   const struct drm_connector_state *old_conn_state)
-+{
-+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-+
-+	intel_disable_dp(encoder, old_crtc_state, old_conn_state);
- 
- 	/* disable the port before the pipe on g4x */
--	if (INTEL_GEN(dev_priv) < 5)
--		intel_dp_link_down(intel_dp);
-+	intel_dp_link_down(intel_dp);
-+}
-+
-+static void ilk_disable_dp(struct intel_encoder *encoder,
-+			   const struct intel_crtc_state *old_crtc_state,
-+			   const struct drm_connector_state *old_conn_state)
-+{
-+	intel_disable_dp(encoder, old_crtc_state, old_conn_state);
-+}
-+
-+static void vlv_disable_dp(struct intel_encoder *encoder,
-+			   const struct intel_crtc_state *old_crtc_state,
-+			   const struct drm_connector_state *old_conn_state)
-+{
-+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-+
-+	intel_psr_disable(intel_dp, old_crtc_state);
-+
-+	intel_disable_dp(encoder, old_crtc_state, old_conn_state);
- }
- 
- static void ilk_post_disable_dp(struct intel_encoder *encoder,
--				struct intel_crtc_state *old_crtc_state,
--				struct drm_connector_state *old_conn_state)
-+				const struct intel_crtc_state *old_crtc_state,
-+				const struct drm_connector_state *old_conn_state)
- {
- 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- 	enum port port = dp_to_dig_port(intel_dp)->port;
-@@ -2727,8 +2750,8 @@ static void ilk_post_disable_dp(struct i
- }
- 
- static void vlv_post_disable_dp(struct intel_encoder *encoder,
--				struct intel_crtc_state *old_crtc_state,
--				struct drm_connector_state *old_conn_state)
-+				const struct intel_crtc_state *old_crtc_state,
-+				const struct drm_connector_state *old_conn_state)
- {
- 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- 
-@@ -2736,8 +2759,8 @@ static void vlv_post_disable_dp(struct i
- }
- 
- static void chv_post_disable_dp(struct intel_encoder *encoder,
--				struct intel_crtc_state *old_crtc_state,
--				struct drm_connector_state *old_conn_state)
-+				const struct intel_crtc_state *old_crtc_state,
-+				const struct drm_connector_state *old_conn_state)
- {
- 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- 	struct drm_device *dev = encoder->base.dev;
-@@ -2842,7 +2865,7 @@ _intel_dp_set_link_train(struct intel_dp
- }
- 
- static void intel_dp_enable_port(struct intel_dp *intel_dp,
--				 struct intel_crtc_state *old_crtc_state)
-+				 const struct intel_crtc_state *old_crtc_state)
- {
- 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
- 	struct drm_i915_private *dev_priv = to_i915(dev);
-@@ -2866,8 +2889,8 @@ static void intel_dp_enable_port(struct
- }
- 
- static void intel_enable_dp(struct intel_encoder *encoder,
--			    struct intel_crtc_state *pipe_config,
--			    struct drm_connector_state *conn_state)
-+			    const struct intel_crtc_state *pipe_config,
-+			    const struct drm_connector_state *conn_state)
- {
- 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- 	struct drm_device *dev = encoder->base.dev;
-@@ -2914,26 +2937,26 @@ static void intel_enable_dp(struct intel
- }
- 
- static void g4x_enable_dp(struct intel_encoder *encoder,
--			  struct intel_crtc_state *pipe_config,
--			  struct drm_connector_state *conn_state)
-+			  const struct intel_crtc_state *pipe_config,
-+			  const struct drm_connector_state *conn_state)
- {
- 	intel_enable_dp(encoder, pipe_config, conn_state);
- 	intel_edp_backlight_on(pipe_config, conn_state);
- }
- 
- static void vlv_enable_dp(struct intel_encoder *encoder,
--			  struct intel_crtc_state *pipe_config,
--			  struct drm_connector_state *conn_state)
-+			  const struct intel_crtc_state *pipe_config,
-+			  const struct drm_connector_state *conn_state)
- {
- 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- 
- 	intel_edp_backlight_on(pipe_config, conn_state);
--	intel_psr_enable(intel_dp);
-+	intel_psr_enable(intel_dp, pipe_config);
- }
- 
- static void g4x_pre_enable_dp(struct intel_encoder *encoder,
--			      struct intel_crtc_state *pipe_config,
--			      struct drm_connector_state *conn_state)
-+			      const struct intel_crtc_state *pipe_config,
-+			      const struct drm_connector_state *conn_state)
- {
- 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- 	enum port port = dp_to_dig_port(intel_dp)->port;
-@@ -3040,7 +3063,7 @@ static void vlv_init_panel_power_sequenc
- 
- 	intel_dp->active_pipe = crtc->pipe;
- 
--	if (!is_edp(intel_dp))
-+	if (!intel_dp_is_edp(intel_dp))
- 		return;
- 
- 	/* now it's all ours */
-@@ -3055,8 +3078,8 @@ static void vlv_init_panel_power_sequenc
- }
- 
- static void vlv_pre_enable_dp(struct intel_encoder *encoder,
--			      struct intel_crtc_state *pipe_config,
--			      struct drm_connector_state *conn_state)
-+			      const struct intel_crtc_state *pipe_config,
-+			      const struct drm_connector_state *conn_state)
- {
- 	vlv_phy_pre_encoder_enable(encoder);
- 
-@@ -3064,8 +3087,8 @@ static void vlv_pre_enable_dp(struct int
- }
- 
- static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
--				  struct intel_crtc_state *pipe_config,
--				  struct drm_connector_state *conn_state)
-+				  const struct intel_crtc_state *pipe_config,
-+				  const struct drm_connector_state *conn_state)
- {
- 	intel_dp_prepare(encoder, pipe_config);
- 
-@@ -3073,8 +3096,8 @@ static void vlv_dp_pre_pll_enable(struct
- }
- 
- static void chv_pre_enable_dp(struct intel_encoder *encoder,
--			      struct intel_crtc_state *pipe_config,
--			      struct drm_connector_state *conn_state)
-+			      const struct intel_crtc_state *pipe_config,
-+			      const struct drm_connector_state *conn_state)
- {
- 	chv_phy_pre_encoder_enable(encoder);
- 
-@@ -3085,8 +3108,8 @@ static void chv_pre_enable_dp(struct int
- }
- 
- static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
--				  struct intel_crtc_state *pipe_config,
--				  struct drm_connector_state *conn_state)
-+				  const struct intel_crtc_state *pipe_config,
-+				  const struct drm_connector_state *conn_state)
- {
- 	intel_dp_prepare(encoder, pipe_config);
- 
-@@ -3094,8 +3117,8 @@ static void chv_dp_pre_pll_enable(struct
- }
- 
- static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
--				    struct intel_crtc_state *pipe_config,
--				    struct drm_connector_state *conn_state)
-+				    const struct intel_crtc_state *pipe_config,
-+				    const struct drm_connector_state *conn_state)
- {
- 	chv_phy_post_pll_disable(encoder);
- }
-@@ -3506,13 +3529,11 @@ intel_dp_set_signal_levels(struct intel_
- 	uint32_t signal_levels, mask = 0;
- 	uint8_t train_set = intel_dp->train_set[0];
- 
--	if (HAS_DDI(dev_priv)) {
-+	if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-+		signal_levels = bxt_signal_levels(intel_dp);
-+	} else if (HAS_DDI(dev_priv)) {
- 		signal_levels = ddi_signal_levels(intel_dp);
--
--		if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
--			signal_levels = 0;
--		else
--			mask = DDI_BUF_EMP_MASK;
-+		mask = DDI_BUF_EMP_MASK;
- 	} else if (IS_CHERRYVIEW(dev_priv)) {
- 		signal_levels = chv_signal_levels(intel_dp);
- 	} else if (IS_VALLEYVIEW(dev_priv)) {
-@@ -3791,7 +3812,7 @@ intel_dp_get_dpcd(struct intel_dp *intel
- 		return false;
- 
- 	/* Don't clobber cached eDP rates. */
--	if (!is_edp(intel_dp)) {
-+	if (!intel_dp_is_edp(intel_dp)) {
- 		intel_dp_set_sink_rates(intel_dp);
- 		intel_dp_set_common_rates(intel_dp);
- 	}
-@@ -3813,7 +3834,7 @@ intel_dp_get_dpcd(struct intel_dp *intel
- 	 * downstream port information. So, an early return here saves
- 	 * time from performing other operations which are not required.
- 	 */
--	if (!is_edp(intel_dp) && !intel_dp->sink_count)
-+	if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
- 		return false;
- 
- 	if (!drm_dp_is_branch(intel_dp->dpcd))
-@@ -3835,7 +3856,7 @@ intel_dp_can_mst(struct intel_dp *intel_
- {
- 	u8 mstm_cap;
- 
--	if (!i915.enable_dp_mst)
-+	if (!i915_modparams.enable_dp_mst)
- 		return false;
- 
- 	if (!intel_dp->can_mst)
-@@ -3853,7 +3874,7 @@ intel_dp_can_mst(struct intel_dp *intel_
- static void
- intel_dp_configure_mst(struct intel_dp *intel_dp)
- {
--	if (!i915.enable_dp_mst)
-+	if (!i915_modparams.enable_dp_mst)
- 		return;
- 
- 	if (!intel_dp->can_mst)
-@@ -4000,15 +4021,9 @@ intel_dp_get_sink_irq(struct intel_dp *i
- static bool
- intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
- {
--	int ret;
--
--	ret = drm_dp_dpcd_read(&intel_dp->aux,
--					     DP_SINK_COUNT_ESI,
--					     sink_irq_vector, 14);
--	if (ret != 14)
--		return false;
--
--	return true;
-+	return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
-+				sink_irq_vector, DP_DPRX_ESI_LEN) ==
-+		DP_DPRX_ESI_LEN;
- }
- 
- static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
-@@ -4208,7 +4223,7 @@ intel_dp_check_mst_status(struct intel_d
- 	bool bret;
- 
- 	if (intel_dp->is_mst) {
--		u8 esi[16] = { 0 };
-+		u8 esi[DP_DPRX_ESI_LEN] = { 0 };
- 		int ret = 0;
- 		int retry;
- 		bool handled;
-@@ -4403,7 +4418,7 @@ intel_dp_detect_dpcd(struct intel_dp *in
- 	if (!intel_dp_get_dpcd(intel_dp))
- 		return connector_status_disconnected;
- 
--	if (is_edp(intel_dp))
-+	if (intel_dp_is_edp(intel_dp))
- 		return connector_status_connected;
- 
- 	/* if there's no downstream port, we're done */
-@@ -4719,7 +4734,7 @@ intel_dp_long_pulse(struct intel_connect
- 	intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain);
- 
- 	/* Can't disconnect eDP, but you can close the lid... */
--	if (is_edp(intel_dp))
-+	if (intel_dp_is_edp(intel_dp))
- 		status = edp_detect(intel_dp);
- 	else if (intel_digital_port_connected(to_i915(dev),
- 					      dp_to_dig_port(intel_dp)))
-@@ -4745,10 +4760,6 @@ intel_dp_long_pulse(struct intel_connect
- 	if (intel_encoder->type != INTEL_OUTPUT_EDP)
- 		intel_encoder->type = INTEL_OUTPUT_DP;
- 
--	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
--		      yesno(intel_dp_source_supports_hbr2(intel_dp)),
--		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
--
- 	if (intel_dp->reset_link_params) {
- 		/* Initial max link lane count */
- 		intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
-@@ -4799,7 +4810,7 @@ intel_dp_long_pulse(struct intel_connect
- 	intel_dp->aux.i2c_defer_count = 0;
- 
- 	intel_dp_set_edid(intel_dp);
--	if (is_edp(intel_dp) || intel_connector->detect_edid)
-+	if (intel_dp_is_edp(intel_dp) || intel_connector->detect_edid)
- 		status = connector_status_connected;
- 	intel_dp->detect_done = true;
- 
-@@ -4883,7 +4894,7 @@ static int intel_dp_get_modes(struct drm
- 	}
- 
- 	/* if eDP has no EDID, fall back to fixed mode */
--	if (is_edp(intel_attached_dp(connector)) &&
-+	if (intel_dp_is_edp(intel_attached_dp(connector)) &&
- 	    intel_connector->panel.fixed_mode) {
- 		struct drm_display_mode *mode;
- 
-@@ -4934,8 +4945,10 @@ intel_dp_connector_destroy(struct drm_co
- 	if (!IS_ERR_OR_NULL(intel_connector->edid))
- 		kfree(intel_connector->edid);
- 
--	/* Can't call is_edp() since the encoder may have been destroyed
--	 * already. */
-+	/*
-+	 * Can't call intel_dp_is_edp() since the encoder may have been
-+	 * destroyed already.
-+	 */
- 	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
- 		intel_panel_fini(&intel_connector->panel);
- 
-@@ -4949,7 +4962,7 @@ void intel_dp_encoder_destroy(struct drm
- 	struct intel_dp *intel_dp = &intel_dig_port->dp;
- 
- 	intel_dp_mst_encoder_cleanup(intel_dig_port);
--	if (is_edp(intel_dp)) {
-+	if (intel_dp_is_edp(intel_dp)) {
- 		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
- 		/*
- 		 * vdd might still be enabled do to the delayed vdd off.
-@@ -4975,7 +4988,7 @@ void intel_dp_encoder_suspend(struct int
- {
- 	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
- 
--	if (!is_edp(intel_dp))
-+	if (!intel_dp_is_edp(intel_dp))
- 		return;
- 
- 	/*
-@@ -5043,7 +5056,7 @@ void intel_dp_encoder_reset(struct drm_e
- 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- 		intel_dp->active_pipe = vlv_active_pipe(intel_dp);
- 
--	if (is_edp(intel_dp)) {
-+	if (intel_dp_is_edp(intel_dp)) {
- 		/* Reinit the power sequencer, in case BIOS did something with it. */
- 		intel_dp_pps_init(encoder->dev, intel_dp);
- 		intel_edp_panel_vdd_sanitize(intel_dp);
-@@ -5144,7 +5157,7 @@ put_power:
- }
- 
- /* check the VBT to see whether the eDP is on another port */
--bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
-+bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
- {
- 	/*
- 	 * eDP not supported on g4x. so bail out early just
-@@ -5167,7 +5180,7 @@ intel_dp_add_properties(struct intel_dp
- 	intel_attach_force_audio_property(connector);
- 	intel_attach_broadcast_rgb_property(connector);
- 
--	if (is_edp(intel_dp)) {
-+	if (intel_dp_is_edp(intel_dp)) {
- 		u32 allowed_scalers;
- 
- 		allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
-@@ -5455,7 +5468,7 @@ static void intel_dp_pps_init(struct drm
-  * The caller of this function needs to take a lock on dev_priv->drrs.
-  */
- static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
--				    struct intel_crtc_state *crtc_state,
-+				    const struct intel_crtc_state *crtc_state,
- 				    int refresh_rate)
- {
- 	struct intel_encoder *encoder;
-@@ -5474,11 +5487,6 @@ static void intel_dp_set_drrs_state(stru
- 		return;
- 	}
- 
--	/*
--	 * FIXME: This needs proper synchronization with psr state for some
--	 * platforms that cannot have PSR and DRRS enabled at the same time.
--	 */
--
- 	dig_port = dp_to_dig_port(intel_dp);
- 	encoder = &dig_port->base;
- 	intel_crtc = to_intel_crtc(encoder->base.crtc);
-@@ -5552,7 +5560,7 @@ static void intel_dp_set_drrs_state(stru
-  * Initializes frontbuffer_bits and drrs.dp
-  */
- void intel_edp_drrs_enable(struct intel_dp *intel_dp,
--			   struct intel_crtc_state *crtc_state)
-+			   const struct intel_crtc_state *crtc_state)
- {
- 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
- 	struct drm_i915_private *dev_priv = to_i915(dev);
-@@ -5562,6 +5570,11 @@ void intel_edp_drrs_enable(struct intel_
- 		return;
- 	}
- 
-+	if (dev_priv->psr.enabled) {
-+		DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
-+		return;
-+	}
-+
- 	mutex_lock(&dev_priv->drrs.mutex);
- 	if (WARN_ON(dev_priv->drrs.dp)) {
- 		DRM_ERROR("DRRS already enabled\n");
-@@ -5583,7 +5596,7 @@ unlock:
-  *
-  */
- void intel_edp_drrs_disable(struct intel_dp *intel_dp,
--			    struct intel_crtc_state *old_crtc_state)
-+			    const struct intel_crtc_state *old_crtc_state)
- {
- 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
- 	struct drm_i915_private *dev_priv = to_i915(dev);
-@@ -5833,7 +5846,7 @@ static bool intel_edp_init_connector(str
- 	struct edid *edid;
- 	enum pipe pipe = INVALID_PIPE;
- 
--	if (!is_edp(intel_dp))
-+	if (!intel_dp_is_edp(intel_dp))
- 		return true;
- 
- 	/*
-@@ -6049,7 +6062,7 @@ intel_dp_init_connector(struct intel_dig
- 	intel_dp->DP = I915_READ(intel_dp->output_reg);
- 	intel_dp->attached_connector = intel_connector;
- 
--	if (intel_dp_is_edp(dev_priv, port))
-+	if (intel_dp_is_port_edp(dev_priv, port))
- 		type = DRM_MODE_CONNECTOR_eDP;
- 	else
- 		type = DRM_MODE_CONNECTOR_DisplayPort;
-@@ -6067,7 +6080,8 @@ intel_dp_init_connector(struct intel_dig
- 
- 	/* eDP only on port B and/or C on vlv/chv */
- 	if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
--		    is_edp(intel_dp) && port != PORT_B && port != PORT_C))
-+		    intel_dp_is_edp(intel_dp) &&
-+		    port != PORT_B && port != PORT_C))
- 		return false;
- 
- 	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
-@@ -6095,7 +6109,7 @@ intel_dp_init_connector(struct intel_dig
- 		intel_connector->get_hw_state = intel_connector_get_hw_state;
- 
- 	/* init MST on ports that can support it */
--	if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
-+	if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
- 	    (port == PORT_B || port == PORT_C || port == PORT_D))
- 		intel_dp_mst_encoder_init(intel_dig_port,
- 					  intel_connector->base.base.id);
-@@ -6151,7 +6165,6 @@ bool intel_dp_init(struct drm_i915_priva
- 		goto err_encoder_init;
- 
- 	intel_encoder->compute_config = intel_dp_compute_config;
--	intel_encoder->disable = intel_disable_dp;
- 	intel_encoder->get_hw_state = intel_dp_get_hw_state;
- 	intel_encoder->get_config = intel_dp_get_config;
- 	intel_encoder->suspend = intel_dp_encoder_suspend;
-@@ -6159,18 +6172,24 @@ bool intel_dp_init(struct drm_i915_priva
- 		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
- 		intel_encoder->pre_enable = chv_pre_enable_dp;
- 		intel_encoder->enable = vlv_enable_dp;
-+		intel_encoder->disable = vlv_disable_dp;
- 		intel_encoder->post_disable = chv_post_disable_dp;
- 		intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
- 	} else if (IS_VALLEYVIEW(dev_priv)) {
- 		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
- 		intel_encoder->pre_enable = vlv_pre_enable_dp;
- 		intel_encoder->enable = vlv_enable_dp;
-+		intel_encoder->disable = vlv_disable_dp;
- 		intel_encoder->post_disable = vlv_post_disable_dp;
-+	} else if (INTEL_GEN(dev_priv) >= 5) {
-+		intel_encoder->pre_enable = g4x_pre_enable_dp;
-+		intel_encoder->enable = g4x_enable_dp;
-+		intel_encoder->disable = ilk_disable_dp;
-+		intel_encoder->post_disable = ilk_post_disable_dp;
- 	} else {
- 		intel_encoder->pre_enable = g4x_pre_enable_dp;
- 		intel_encoder->enable = g4x_enable_dp;
--		if (INTEL_GEN(dev_priv) >= 5)
--			intel_encoder->post_disable = ilk_post_disable_dp;
-+		intel_encoder->disable = g4x_disable_dp;
- 	}
- 
- 	intel_dig_port->port = port;
-@@ -6193,6 +6212,9 @@ bool intel_dp_init(struct drm_i915_priva
- 	intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
- 	dev_priv->hotplug.irq_port[port] = intel_dig_port;
- 
-+	if (port != PORT_A)
-+		intel_infoframe_init(intel_dig_port);
-+
- 	if (!intel_dp_init_connector(intel_dig_port, intel_connector))
- 		goto err_init_connector;
- 
---- linux-4.14/drivers/gpu/drm/i915/intel_dp_mst.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_dp_mst.c	2017-12-14 06:39:58.508903632 +0100
-@@ -123,8 +123,8 @@ static int intel_dp_mst_atomic_check(str
- }
- 
- static void intel_mst_disable_dp(struct intel_encoder *encoder,
--				 struct intel_crtc_state *old_crtc_state,
--				 struct drm_connector_state *old_conn_state)
-+				 const struct intel_crtc_state *old_crtc_state,
-+				 const struct drm_connector_state *old_conn_state)
- {
- 	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
- 	struct intel_digital_port *intel_dig_port = intel_mst->primary;
-@@ -133,7 +133,7 @@ static void intel_mst_disable_dp(struct
- 		to_intel_connector(old_conn_state->connector);
- 	int ret;
- 
--	DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
-+	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
- 
- 	drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port);
- 
-@@ -146,8 +146,8 @@ static void intel_mst_disable_dp(struct
- }
- 
- static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
--				      struct intel_crtc_state *old_crtc_state,
--				      struct drm_connector_state *old_conn_state)
-+				      const struct intel_crtc_state *old_crtc_state,
-+				      const struct drm_connector_state *old_conn_state)
- {
- 	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
- 	struct intel_digital_port *intel_dig_port = intel_mst->primary;
-@@ -155,8 +155,6 @@ static void intel_mst_post_disable_dp(st
- 	struct intel_connector *connector =
- 		to_intel_connector(old_conn_state->connector);
- 
--	DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
--
- 	/* this can fail */
- 	drm_dp_check_act_status(&intel_dp->mst_mgr);
- 	/* and this can also fail */
-@@ -173,11 +171,12 @@ static void intel_mst_post_disable_dp(st
- 
- 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
- 	}
-+	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
- }
- 
- static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
--				    struct intel_crtc_state *pipe_config,
--				    struct drm_connector_state *conn_state)
-+				    const struct intel_crtc_state *pipe_config,
-+				    const struct drm_connector_state *conn_state)
- {
- 	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
- 	struct intel_digital_port *intel_dig_port = intel_mst->primary;
-@@ -195,7 +194,7 @@ static void intel_mst_pre_enable_dp(stru
- 	connector->encoder = encoder;
- 	intel_mst->connector = connector;
- 
--	DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
-+	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
- 
- 	if (intel_dp->active_mst_links == 0)
- 		intel_dig_port->base.pre_enable(&intel_dig_port->base,
-@@ -219,8 +218,8 @@ static void intel_mst_pre_enable_dp(stru
- }
- 
- static void intel_mst_enable_dp(struct intel_encoder *encoder,
--				struct intel_crtc_state *pipe_config,
--				struct drm_connector_state *conn_state)
-+				const struct intel_crtc_state *pipe_config,
-+				const struct drm_connector_state *conn_state)
- {
- 	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
- 	struct intel_digital_port *intel_dig_port = intel_mst->primary;
-@@ -229,7 +228,7 @@ static void intel_mst_enable_dp(struct i
- 	enum port port = intel_dig_port->port;
- 	int ret;
- 
--	DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
-+	DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
- 
- 	if (intel_wait_for_register(dev_priv,
- 				    DP_TP_STATUS(port),
-@@ -494,6 +493,7 @@ static void intel_dp_destroy_mst_connect
- 	struct intel_connector *intel_connector = to_intel_connector(connector);
- 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
- 
-+	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, connector->name);
- 	drm_connector_unregister(connector);
- 
- 	if (dev_priv->fbdev)
-@@ -505,7 +505,6 @@ static void intel_dp_destroy_mst_connect
- 	drm_modeset_unlock(&connector->dev->mode_config.connection_mutex);
- 
- 	drm_connector_unreference(connector);
--	DRM_DEBUG_KMS("\n");
- }
- 
- static void intel_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
---- linux-4.14/drivers/gpu/drm/i915/intel_drv.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_drv.h	2017-12-14 06:39:58.508903632 +0100
-@@ -220,23 +220,23 @@ struct intel_encoder {
- 			       struct intel_crtc_state *,
- 			       struct drm_connector_state *);
- 	void (*pre_pll_enable)(struct intel_encoder *,
--			       struct intel_crtc_state *,
--			       struct drm_connector_state *);
-+			       const struct intel_crtc_state *,
-+			       const struct drm_connector_state *);
- 	void (*pre_enable)(struct intel_encoder *,
--			   struct intel_crtc_state *,
--			   struct drm_connector_state *);
-+			   const struct intel_crtc_state *,
-+			   const struct drm_connector_state *);
- 	void (*enable)(struct intel_encoder *,
--		       struct intel_crtc_state *,
--		       struct drm_connector_state *);
-+		       const struct intel_crtc_state *,
-+		       const struct drm_connector_state *);
- 	void (*disable)(struct intel_encoder *,
--			struct intel_crtc_state *,
--			struct drm_connector_state *);
-+			const struct intel_crtc_state *,
-+			const struct drm_connector_state *);
- 	void (*post_disable)(struct intel_encoder *,
--			     struct intel_crtc_state *,
--			     struct drm_connector_state *);
-+			     const struct intel_crtc_state *,
-+			     const struct drm_connector_state *);
- 	void (*post_pll_disable)(struct intel_encoder *,
--				 struct intel_crtc_state *,
--				 struct drm_connector_state *);
-+				 const struct intel_crtc_state *,
-+				 const struct drm_connector_state *);
- 	/* Read out the current hw state of this connector, returning true if
- 	 * the encoder is active. If the encoder is enabled it also set the pipe
- 	 * it is connected to in the pipe parameter. */
-@@ -384,7 +384,8 @@ struct intel_atomic_state {
- 	unsigned int active_pipe_changes;
- 
- 	unsigned int active_crtcs;
--	unsigned int min_pixclk[I915_MAX_PIPES];
-+	/* minimum acceptable cdclk for each pipe */
-+	int min_cdclk[I915_MAX_PIPES];
- 
- 	struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
- 
-@@ -493,6 +494,8 @@ struct intel_crtc_scaler_state {
- 
- /* drm_mode->private_flags */
- #define I915_MODE_FLAG_INHERITED 1
-+/* Flag to get scanline using frame time stamps */
-+#define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
- 
- struct intel_pipe_wm {
- 	struct intel_wm_level wm[5];
-@@ -752,6 +755,7 @@ struct intel_crtc_state {
- 	struct intel_link_m_n fdi_m_n;
- 
- 	bool ips_enabled;
-+	bool ips_force_disable;
- 
- 	bool enable_fbc;
- 
-@@ -908,16 +912,6 @@ struct intel_hdmi {
- 	bool has_audio;
- 	bool rgb_quant_range_selectable;
- 	struct intel_connector *attached_connector;
--	void (*write_infoframe)(struct drm_encoder *encoder,
--				const struct intel_crtc_state *crtc_state,
--				enum hdmi_infoframe_type type,
--				const void *frame, ssize_t len);
--	void (*set_infoframes)(struct drm_encoder *encoder,
--			       bool enable,
--			       const struct intel_crtc_state *crtc_state,
--			       const struct drm_connector_state *conn_state);
--	bool (*infoframe_enabled)(struct drm_encoder *encoder,
--				  const struct intel_crtc_state *pipe_config);
- };
- 
- struct intel_dp_mst_encoder;
-@@ -1068,6 +1062,17 @@ struct intel_digital_port {
- 	bool release_cl2_override;
- 	uint8_t max_lanes;
- 	enum intel_display_power_domain ddi_io_power_domain;
-+
-+	void (*write_infoframe)(struct drm_encoder *encoder,
-+				const struct intel_crtc_state *crtc_state,
-+				enum hdmi_infoframe_type type,
-+				const void *frame, ssize_t len);
-+	void (*set_infoframes)(struct drm_encoder *encoder,
-+			       bool enable,
-+			       const struct intel_crtc_state *crtc_state,
-+			       const struct drm_connector_state *conn_state);
-+	bool (*infoframe_enabled)(struct drm_encoder *encoder,
-+				  const struct intel_crtc_state *pipe_config);
- };
- 
- struct intel_dp_mst_encoder {
-@@ -1188,6 +1193,30 @@ hdmi_to_dig_port(struct intel_hdmi *inte
- 	return container_of(intel_hdmi, struct intel_digital_port, hdmi);
- }
- 
-+static inline struct intel_plane_state *
-+intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
-+				 struct intel_plane *plane)
-+{
-+	return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
-+								   &plane->base));
-+}
-+
-+static inline struct intel_crtc_state *
-+intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
-+				struct intel_crtc *crtc)
-+{
-+	return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
-+								 &crtc->base));
-+}
-+
-+static inline struct intel_crtc_state *
-+intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
-+				struct intel_crtc *crtc)
-+{
-+	return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
-+								 &crtc->base));
-+}
-+
- /* intel_fifo_underrun.c */
- bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
- 					   enum pipe pipe, bool enable);
-@@ -1204,11 +1233,8 @@ void intel_check_pch_fifo_underruns(stru
- /* i915_irq.c */
- void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
- void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
--void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
- void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
- void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
--void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
--void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
- void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
- void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
- void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
-@@ -1245,8 +1271,8 @@ void intel_crt_reset(struct drm_encoder
- 
- /* intel_ddi.c */
- void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
--				struct intel_crtc_state *old_crtc_state,
--				struct drm_connector_state *old_conn_state);
-+				const struct intel_crtc_state *old_crtc_state,
-+				const struct drm_connector_state *old_conn_state);
- void hsw_fdi_link_train(struct intel_crtc *crtc,
- 			const struct intel_crtc_state *crtc_state);
- void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
-@@ -1271,6 +1297,7 @@ void intel_ddi_clock_get(struct intel_en
- 			 struct intel_crtc_state *pipe_config);
- void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
- 				    bool state);
-+u32 bxt_signal_levels(struct intel_dp *intel_dp);
- uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
- u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
- 
-@@ -1289,6 +1316,7 @@ void intel_audio_init(struct drm_i915_pr
- void intel_audio_deinit(struct drm_i915_private *dev_priv);
- 
- /* intel_cdclk.c */
-+int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
- void skl_init_cdclk(struct drm_i915_private *dev_priv);
- void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
- void cnl_init_cdclk(struct drm_i915_private *dev_priv);
-@@ -1376,7 +1404,7 @@ void vlv_wait_port_ready(struct drm_i915
- 			 struct intel_digital_port *dport,
- 			 unsigned int expected_mask);
- int intel_get_load_detect_pipe(struct drm_connector *connector,
--			       struct drm_display_mode *mode,
-+			       const struct drm_display_mode *mode,
- 			       struct intel_load_detect_pipe *old,
- 			       struct drm_modeset_acquire_ctx *ctx);
- void intel_release_load_detect_pipe(struct drm_connector *connector,
-@@ -1400,7 +1428,9 @@ int intel_plane_atomic_set_property(stru
- 				    struct drm_plane_state *state,
- 				    struct drm_property *property,
- 				    uint64_t val);
--int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
-+int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
-+				    struct drm_crtc_state *crtc_state,
-+				    const struct intel_plane_state *old_plane_state,
- 				    struct drm_plane_state *plane_state);
- 
- void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
-@@ -1498,7 +1528,8 @@ int intel_dp_sink_crc(struct intel_dp *i
- bool intel_dp_compute_config(struct intel_encoder *encoder,
- 			     struct intel_crtc_state *pipe_config,
- 			     struct drm_connector_state *conn_state);
--bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
-+bool intel_dp_is_edp(struct intel_dp *intel_dp);
-+bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
- enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
- 				  bool long_hpd);
- void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
-@@ -1517,9 +1548,9 @@ void intel_power_sequencer_reset(struct
- uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
- void intel_plane_destroy(struct drm_plane *plane);
- void intel_edp_drrs_enable(struct intel_dp *intel_dp,
--			   struct intel_crtc_state *crtc_state);
-+			   const struct intel_crtc_state *crtc_state);
- void intel_edp_drrs_disable(struct intel_dp *intel_dp,
--			   struct intel_crtc_state *crtc_state);
-+			    const struct intel_crtc_state *crtc_state);
- void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
- 			       unsigned int frontbuffer_bits);
- void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
-@@ -1647,6 +1678,7 @@ void intel_hdmi_handle_sink_scrambling(s
- 				       bool high_tmds_clock_ratio,
- 				       bool scrambling);
- void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
-+void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
- 
- 
- /* intel_lvds.c */
-@@ -1718,8 +1750,10 @@ static inline void intel_backlight_devic
- 
- 
- /* intel_psr.c */
--void intel_psr_enable(struct intel_dp *intel_dp);
--void intel_psr_disable(struct intel_dp *intel_dp);
-+void intel_psr_enable(struct intel_dp *intel_dp,
-+		      const struct intel_crtc_state *crtc_state);
-+void intel_psr_disable(struct intel_dp *intel_dp,
-+		      const struct intel_crtc_state *old_crtc_state);
- void intel_psr_invalidate(struct drm_i915_private *dev_priv,
- 			  unsigned frontbuffer_bits);
- void intel_psr_flush(struct drm_i915_private *dev_priv,
-@@ -1843,7 +1877,6 @@ void gen6_rps_reset_ei(struct drm_i915_p
- void gen6_rps_idle(struct drm_i915_private *dev_priv);
- void gen6_rps_boost(struct drm_i915_gem_request *rq,
- 		    struct intel_rps_client *rps);
--void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
- void g4x_wm_get_hw_state(struct drm_device *dev);
- void vlv_wm_get_hw_state(struct drm_device *dev);
- void ilk_wm_get_hw_state(struct drm_device *dev);
-@@ -1866,9 +1899,11 @@ bool ilk_disable_lp_wm(struct drm_device
- int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
- int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
- 				  struct intel_crtc_state *cstate);
-+void intel_init_ipc(struct drm_i915_private *dev_priv);
-+void intel_enable_ipc(struct drm_i915_private *dev_priv);
- static inline int intel_enable_rc6(void)
- {
--	return i915.enable_rc6;
-+	return i915_modparams.enable_rc6;
- }
- 
- /* intel_sdvo.c */
-@@ -1883,8 +1918,8 @@ struct intel_plane *intel_sprite_plane_c
- 					      enum pipe pipe, int plane);
- int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
- 			      struct drm_file *file_priv);
--void intel_pipe_update_start(struct intel_crtc *crtc);
--void intel_pipe_update_end(struct intel_crtc *crtc);
-+void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
-+void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
- 
- /* intel_tv.c */
- void intel_tv_init(struct drm_i915_private *dev_priv);
-@@ -1956,7 +1991,9 @@ struct drm_plane_state *intel_plane_dupl
- void intel_plane_destroy_state(struct drm_plane *plane,
- 			       struct drm_plane_state *state);
- extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
--int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
-+int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
-+					struct intel_crtc_state *crtc_state,
-+					const struct intel_plane_state *old_plane_state,
- 					struct intel_plane_state *intel_state);
- 
- /* intel_color.c */
---- linux-4.14/drivers/gpu/drm/i915/intel_dsi.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_dsi.c	2017-12-14 06:39:58.508903632 +0100
-@@ -263,7 +263,7 @@ static int dpi_send_cmd(struct intel_dsi
- 
- 	/* XXX: old code skips write if control unchanged */
- 	if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
--		DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
-+		DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd);
- 
- 	I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
- 
-@@ -330,6 +330,10 @@ static bool intel_dsi_compute_config(str
- 	adjusted_mode->flags = 0;
- 
- 	if (IS_GEN9_LP(dev_priv)) {
-+		/* Enable Frame time stamp based scanline reporting */
-+		adjusted_mode->private_flags |=
-+			I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
-+
- 		/* Dual link goes to DSI transcoder A. */
- 		if (intel_dsi->ports == BIT(PORT_C))
- 			pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
-@@ -731,7 +735,7 @@ static void intel_dsi_port_disable(struc
- }
- 
- static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
--			      struct intel_crtc_state *pipe_config);
-+			      const struct intel_crtc_state *pipe_config);
- static void intel_dsi_unprepare(struct intel_encoder *encoder);
- 
- static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
-@@ -783,8 +787,8 @@ static void intel_dsi_msleep(struct inte
-  */
- 
- static void intel_dsi_pre_enable(struct intel_encoder *encoder,
--				 struct intel_crtc_state *pipe_config,
--				 struct drm_connector_state *conn_state)
-+				 const struct intel_crtc_state *pipe_config,
-+				 const struct drm_connector_state *conn_state)
- {
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-@@ -878,8 +882,8 @@ static void intel_dsi_pre_enable(struct
-  * the pre_enable hook.
-  */
- static void intel_dsi_enable_nop(struct intel_encoder *encoder,
--				 struct intel_crtc_state *pipe_config,
--				 struct drm_connector_state *conn_state)
-+				 const struct intel_crtc_state *pipe_config,
-+				 const struct drm_connector_state *conn_state)
- {
- 	DRM_DEBUG_KMS("\n");
- }
-@@ -889,8 +893,8 @@ static void intel_dsi_enable_nop(struct
-  * the post_disable hook.
-  */
- static void intel_dsi_disable(struct intel_encoder *encoder,
--			      struct intel_crtc_state *old_crtc_state,
--			      struct drm_connector_state *old_conn_state)
-+			      const struct intel_crtc_state *old_crtc_state,
-+			      const struct drm_connector_state *old_conn_state)
- {
- 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
- 	enum port port;
-@@ -925,8 +929,8 @@ static void intel_dsi_clear_device_ready
- }
- 
- static void intel_dsi_post_disable(struct intel_encoder *encoder,
--				   struct intel_crtc_state *pipe_config,
--				   struct drm_connector_state *conn_state)
-+				   const struct intel_crtc_state *pipe_config,
-+				   const struct drm_connector_state *conn_state)
- {
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-@@ -1066,7 +1070,7 @@ out_put_power:
- }
- 
- static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
--				 struct intel_crtc_state *pipe_config)
-+				    struct intel_crtc_state *pipe_config)
- {
- 	struct drm_device *dev = encoder->base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
-@@ -1102,6 +1106,10 @@ static void bxt_dsi_get_pipe_config(stru
- 				pixel_format_from_register_bits(fmt));
- 	bpp = pipe_config->pipe_bpp;
- 
-+	/* Enable Frame time stamo based scanline reporting */
-+	adjusted_mode->private_flags |=
-+			I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
-+
- 	/* In terms of pixels */
- 	adjusted_mode->crtc_hdisplay =
- 				I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
-@@ -1370,7 +1378,7 @@ static u32 pixel_format_to_reg(enum mipi
- }
- 
- static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
--			      struct intel_crtc_state *pipe_config)
-+			      const struct intel_crtc_state *pipe_config)
- {
- 	struct drm_encoder *encoder = &intel_encoder->base;
- 	struct drm_device *dev = encoder->dev;
---- linux-4.14/drivers/gpu/drm/i915/intel_dvo.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_dvo.c	2017-12-14 06:39:58.508903632 +0100
-@@ -175,8 +175,8 @@ static void intel_dvo_get_config(struct
- }
- 
- static void intel_disable_dvo(struct intel_encoder *encoder,
--			      struct intel_crtc_state *old_crtc_state,
--			      struct drm_connector_state *old_conn_state)
-+			      const struct intel_crtc_state *old_crtc_state,
-+			      const struct drm_connector_state *old_conn_state)
- {
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
-@@ -189,8 +189,8 @@ static void intel_disable_dvo(struct int
- }
- 
- static void intel_enable_dvo(struct intel_encoder *encoder,
--			     struct intel_crtc_state *pipe_config,
--			     struct drm_connector_state *conn_state)
-+			     const struct intel_crtc_state *pipe_config,
-+			     const struct drm_connector_state *conn_state)
- {
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
-@@ -258,8 +258,8 @@ static bool intel_dvo_compute_config(str
- }
- 
- static void intel_dvo_pre_enable(struct intel_encoder *encoder,
--				 struct intel_crtc_state *pipe_config,
--				 struct drm_connector_state *conn_state)
-+				 const struct intel_crtc_state *pipe_config,
-+				 const struct drm_connector_state *conn_state)
- {
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
---- linux-4.14/drivers/gpu/drm/i915/intel_engine_cs.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_engine_cs.c	2017-12-14 06:39:58.508903632 +0100
-@@ -39,6 +39,7 @@
- 
- #define GEN8_LR_CONTEXT_RENDER_SIZE	(20 * PAGE_SIZE)
- #define GEN9_LR_CONTEXT_RENDER_SIZE	(22 * PAGE_SIZE)
-+#define GEN10_LR_CONTEXT_RENDER_SIZE	(19 * PAGE_SIZE)
- 
- #define GEN8_LR_CONTEXT_OTHER_SIZE	( 2 * PAGE_SIZE)
- 
-@@ -150,10 +151,11 @@ __intel_engine_context_size(struct drm_i
- 		default:
- 			MISSING_CASE(INTEL_GEN(dev_priv));
- 		case 10:
-+			return GEN10_LR_CONTEXT_RENDER_SIZE;
- 		case 9:
- 			return GEN9_LR_CONTEXT_RENDER_SIZE;
- 		case 8:
--			return i915.enable_execlists ?
-+			return i915_modparams.enable_execlists ?
- 			       GEN8_LR_CONTEXT_RENDER_SIZE :
- 			       GEN8_CXT_TOTAL_SIZE;
- 		case 7:
-@@ -301,7 +303,7 @@ int intel_engines_init(struct drm_i915_p
- 			&intel_engine_classes[engine->class];
- 		int (*init)(struct intel_engine_cs *engine);
- 
--		if (i915.enable_execlists)
-+		if (i915_modparams.enable_execlists)
- 			init = class_info->init_execlists;
- 		else
- 			init = class_info->init_legacy;
-@@ -380,6 +382,37 @@ static void intel_engine_init_timeline(s
- 	engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];
- }
- 
-+static bool csb_force_mmio(struct drm_i915_private *i915)
-+{
-+	/* GVT emulation depends upon intercepting CSB mmio */
-+	if (intel_vgpu_active(i915))
-+		return true;
-+
-+	/*
-+	 * IOMMU adds unpredictable latency causing the CSB write (from the
-+	 * GPU into the HWSP) to only be visible some time after the interrupt
-+	 * (missed breadcrumb syndrome).
-+	 */
-+	if (intel_vtd_active())
-+		return true;
-+
-+	return false;
-+}
-+
-+static void intel_engine_init_execlist(struct intel_engine_cs *engine)
-+{
-+	struct intel_engine_execlists * const execlists = &engine->execlists;
-+
-+	execlists->csb_use_mmio = csb_force_mmio(engine->i915);
-+
-+	execlists->port_mask = 1;
-+	BUILD_BUG_ON_NOT_POWER_OF_2(execlists_num_ports(execlists));
-+	GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
-+
-+	execlists->queue = RB_ROOT;
-+	execlists->first = NULL;
-+}
-+
- /**
-  * intel_engines_setup_common - setup engine state not requiring hw access
-  * @engine: Engine to setup.
-@@ -391,8 +424,7 @@ static void intel_engine_init_timeline(s
-  */
- void intel_engine_setup_common(struct intel_engine_cs *engine)
- {
--	engine->execlist_queue = RB_ROOT;
--	engine->execlist_first = NULL;
-+	intel_engine_init_execlist(engine);
- 
- 	intel_engine_init_timeline(engine);
- 	intel_engine_init_hangcheck(engine);
-@@ -442,6 +474,116 @@ static void intel_engine_cleanup_scratch
- 	i915_vma_unpin_and_release(&engine->scratch);
- }
- 
-+static void cleanup_phys_status_page(struct intel_engine_cs *engine)
-+{
-+	struct drm_i915_private *dev_priv = engine->i915;
-+
-+	if (!dev_priv->status_page_dmah)
-+		return;
-+
-+	drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah);
-+	engine->status_page.page_addr = NULL;
-+}
-+
-+static void cleanup_status_page(struct intel_engine_cs *engine)
-+{
-+	struct i915_vma *vma;
-+	struct drm_i915_gem_object *obj;
-+
-+	vma = fetch_and_zero(&engine->status_page.vma);
-+	if (!vma)
-+		return;
-+
-+	obj = vma->obj;
-+
-+	i915_vma_unpin(vma);
-+	i915_vma_close(vma);
-+
-+	i915_gem_object_unpin_map(obj);
-+	__i915_gem_object_release_unless_active(obj);
-+}
-+
-+static int init_status_page(struct intel_engine_cs *engine)
-+{
-+	struct drm_i915_gem_object *obj;
-+	struct i915_vma *vma;
-+	unsigned int flags;
-+	void *vaddr;
-+	int ret;
-+
-+	obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
-+	if (IS_ERR(obj)) {
-+		DRM_ERROR("Failed to allocate status page\n");
-+		return PTR_ERR(obj);
-+	}
-+
-+	ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
-+	if (ret)
-+		goto err;
-+
-+	vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
-+	if (IS_ERR(vma)) {
-+		ret = PTR_ERR(vma);
-+		goto err;
-+	}
-+
-+	flags = PIN_GLOBAL;
-+	if (!HAS_LLC(engine->i915))
-+		/* On g33, we cannot place HWS above 256MiB, so
-+		 * restrict its pinning to the low mappable arena.
-+		 * Though this restriction is not documented for
-+		 * gen4, gen5, or byt, they also behave similarly
-+		 * and hang if the HWS is placed at the top of the
-+		 * GTT. To generalise, it appears that all !llc
-+		 * platforms have issues with us placing the HWS
-+		 * above the mappable region (even though we never
-+		 * actually map it).
-+		 */
-+		flags |= PIN_MAPPABLE;
-+	else
-+		flags |= PIN_HIGH;
-+	ret = i915_vma_pin(vma, 0, 4096, flags);
-+	if (ret)
-+		goto err;
-+
-+	vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
-+	if (IS_ERR(vaddr)) {
-+		ret = PTR_ERR(vaddr);
-+		goto err_unpin;
-+	}
-+
-+	engine->status_page.vma = vma;
-+	engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
-+	engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE);
-+
-+	DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
-+			 engine->name, i915_ggtt_offset(vma));
-+	return 0;
-+
-+err_unpin:
-+	i915_vma_unpin(vma);
-+err:
-+	i915_gem_object_put(obj);
-+	return ret;
-+}
-+
-+static int init_phys_status_page(struct intel_engine_cs *engine)
-+{
-+	struct drm_i915_private *dev_priv = engine->i915;
-+
-+	GEM_BUG_ON(engine->id != RCS);
-+
-+	dev_priv->status_page_dmah =
-+		drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE);
-+	if (!dev_priv->status_page_dmah)
-+		return -ENOMEM;
-+
-+	engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
-+	memset(engine->status_page.page_addr, 0, PAGE_SIZE);
-+
-+	return 0;
-+}
-+
- /**
-  * intel_engines_init_common - initialize cengine state which might require hw access
-  * @engine: Engine to initialize.
-@@ -477,10 +619,21 @@ int intel_engine_init_common(struct inte
- 
- 	ret = i915_gem_render_state_init(engine);
- 	if (ret)
--		goto err_unpin;
-+		goto err_breadcrumbs;
-+
-+	if (HWS_NEEDS_PHYSICAL(engine->i915))
-+		ret = init_phys_status_page(engine);
-+	else
-+		ret = init_status_page(engine);
-+	if (ret)
-+		goto err_rs_fini;
- 
- 	return 0;
- 
-+err_rs_fini:
-+	i915_gem_render_state_fini(engine);
-+err_breadcrumbs:
-+	intel_engine_fini_breadcrumbs(engine);
- err_unpin:
- 	engine->context_unpin(engine, engine->i915->kernel_context);
- 	return ret;
-@@ -497,6 +650,11 @@ void intel_engine_cleanup_common(struct
- {
- 	intel_engine_cleanup_scratch(engine);
- 
-+	if (HWS_NEEDS_PHYSICAL(engine->i915))
-+		cleanup_phys_status_page(engine);
-+	else
-+		cleanup_status_page(engine);
-+
- 	i915_gem_render_state_fini(engine);
- 	intel_engine_fini_breadcrumbs(engine);
- 	intel_engine_cleanup_cmd_parser(engine);
-@@ -812,6 +970,19 @@ static int gen9_init_workarounds(struct
- 		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
- 			   ECOCHK_DIS_TLB);
- 
-+	if (HAS_LLC(dev_priv)) {
-+		/* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
-+		 *
-+		 * Must match Display Engine. See
-+		 * WaCompressedResourceDisplayNewHashMode.
-+		 */
-+		WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
-+				  GEN9_PBE_COMPRESSED_HASH_SELECTION);
-+		WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
-+				  GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
-+		WA_SET_BIT(MMCD_MISC_CTRL, MMCD_PCLA | MMCD_HOTSPOT_EN);
-+	}
-+
- 	/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
- 	/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
- 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
-@@ -981,12 +1152,14 @@ static int skl_init_workarounds(struct i
- 				   GEN9_GAPS_TSV_CREDIT_DISABLE));
- 
- 	/* WaDisableGafsUnitClkGating:skl */
--	WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
-+	I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
-+				  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
- 
- 	/* WaInPlaceDecompressionHang:skl */
- 	if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
--		WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
--			   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
-+		I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
-+			   (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
-+			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
- 
- 	/* WaDisableLSQCROPERFforOCL:skl */
- 	ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
-@@ -1022,8 +1195,8 @@ static int bxt_init_workarounds(struct i
- 
- 	/* WaDisablePooledEuLoadBalancingFix:bxt */
- 	if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
--		WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
--				  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
-+		I915_WRITE(FF_SLICE_CS_CHICKEN2,
-+			   _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
- 	}
- 
- 	/* WaDisableSbeCacheDispatchPortSharing:bxt */
-@@ -1062,8 +1235,56 @@ static int bxt_init_workarounds(struct i
- 
- 	/* WaInPlaceDecompressionHang:bxt */
- 	if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
--		WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
--			   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
-+		I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
-+			   (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
-+			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
-+
-+	return 0;
-+}
-+
-+static int cnl_init_workarounds(struct intel_engine_cs *engine)
-+{
-+	struct drm_i915_private *dev_priv = engine->i915;
-+	int ret;
-+
-+	/* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
-+	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
-+		I915_WRITE(GAMT_CHKN_BIT_REG,
-+			   (I915_READ(GAMT_CHKN_BIT_REG) |
-+			    GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT));
-+
-+	/* WaForceContextSaveRestoreNonCoherent:cnl */
-+	WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
-+			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
-+
-+	/* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */
-+	if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
-+		WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5);
-+
-+	/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
-+	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
-+			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
-+
-+	/* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */
-+	if (IS_CNL_REVID(dev_priv, 0, CNL_REVID_B0))
-+		WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
-+				  GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
-+
-+	/* WaInPlaceDecompressionHang:cnl */
-+	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
-+		   (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
-+		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
-+
-+	/* WaPushConstantDereferenceHoldDisable:cnl */
-+	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
-+
-+	/* FtrEnableFastAnisoL1BankingFix: cnl */
-+	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
-+
-+	/* WaEnablePreemptionGranularityControlByUMD:cnl */
-+	ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
-+	if (ret)
-+		return ret;
- 
- 	return 0;
- }
-@@ -1083,8 +1304,9 @@ static int kbl_init_workarounds(struct i
- 
- 	/* WaDisableDynamicCreditSharing:kbl */
- 	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
--		WA_SET_BIT(GAMT_CHKN_BIT_REG,
--			   GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
-+		I915_WRITE(GAMT_CHKN_BIT_REG,
-+			   (I915_READ(GAMT_CHKN_BIT_REG) |
-+			    GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING));
- 
- 	/* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
- 	if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
-@@ -1097,7 +1319,8 @@ static int kbl_init_workarounds(struct i
- 				  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
- 
- 	/* WaDisableGafsUnitClkGating:kbl */
--	WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
-+	I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
-+				  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
- 
- 	/* WaDisableSbeCacheDispatchPortSharing:kbl */
- 	WA_SET_BIT_MASKED(
-@@ -1105,8 +1328,9 @@ static int kbl_init_workarounds(struct i
- 		GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
- 
- 	/* WaInPlaceDecompressionHang:kbl */
--	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
--		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
-+	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
-+		   (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
-+		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
- 
- 	/* WaDisableLSQCROPERFforOCL:kbl */
- 	ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
-@@ -1150,7 +1374,8 @@ static int cfl_init_workarounds(struct i
- 			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
- 
- 	/* WaDisableGafsUnitClkGating:cfl */
--	WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
-+	I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |
-+				  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));
- 
- 	/* WaDisableSbeCacheDispatchPortSharing:cfl */
- 	WA_SET_BIT_MASKED(
-@@ -1158,8 +1383,9 @@ static int cfl_init_workarounds(struct i
- 		GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
- 
- 	/* WaInPlaceDecompressionHang:cfl */
--	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
--		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
-+	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
-+		   (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
-+		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
- 
- 	return 0;
- }
-@@ -1188,6 +1414,8 @@ int init_workarounds_ring(struct intel_e
- 		err =  glk_init_workarounds(engine);
- 	else if (IS_COFFEELAKE(dev_priv))
- 		err = cfl_init_workarounds(engine);
-+	else if (IS_CANNONLAKE(dev_priv))
-+		err = cnl_init_workarounds(engine);
- 	else
- 		err = 0;
- 	if (err)
-@@ -1280,11 +1508,11 @@ bool intel_engine_is_idle(struct intel_e
- 		return false;
- 
- 	/* Both ports drained, no more ELSP submission? */
--	if (port_request(&engine->execlist_port[0]))
-+	if (port_request(&engine->execlists.port[0]))
- 		return false;
- 
- 	/* ELSP is empty, but there are ready requests? */
--	if (READ_ONCE(engine->execlist_first))
-+	if (READ_ONCE(engine->execlists.first))
- 		return false;
- 
- 	/* Ring stopped? */
-@@ -1333,8 +1561,23 @@ void intel_engines_mark_idle(struct drm_
- 	for_each_engine(engine, i915, id) {
- 		intel_engine_disarm_breadcrumbs(engine);
- 		i915_gem_batch_pool_fini(&engine->batch_pool);
--		tasklet_kill(&engine->irq_tasklet);
--		engine->no_priolist = false;
-+		tasklet_kill(&engine->execlists.irq_tasklet);
-+		engine->execlists.no_priolist = false;
-+	}
-+}
-+
-+bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
-+{
-+	switch (INTEL_GEN(engine->i915)) {
-+	case 2:
-+		return false; /* uses physical not virtual addresses */
-+	case 3:
-+		/* maybe only uses physical not virtual addresses */
-+		return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
-+	case 6:
-+		return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
-+	default:
-+		return true;
- 	}
- }
- 
---- linux-4.14/drivers/gpu/drm/i915/intel_fbc.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_fbc.c	2017-12-14 06:39:58.509903633 +0100
-@@ -291,6 +291,19 @@ static void gen7_fbc_activate(struct drm
- 	u32 dpfc_ctl;
- 	int threshold = dev_priv->fbc.threshold;
- 
-+	/* Display WA #0529: skl, kbl, bxt. */
-+	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
-+		u32 val = I915_READ(CHICKEN_MISC_4);
-+
-+		val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
-+
-+		if (i915_gem_object_get_tiling(params->vma->obj) !=
-+		    I915_TILING_X)
-+			val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
-+
-+		I915_WRITE(CHICKEN_MISC_4, val);
-+	}
-+
- 	dpfc_ctl = 0;
- 	if (IS_IVYBRIDGE(dev_priv))
- 		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
-@@ -846,7 +859,7 @@ static bool intel_fbc_can_enable(struct
- 		return false;
- 	}
- 
--	if (!i915.enable_fbc) {
-+	if (!i915_modparams.enable_fbc) {
- 		fbc->no_fbc_reason = "disabled per module param or by default";
- 		return false;
- 	}
-@@ -881,6 +894,10 @@ static void intel_fbc_get_reg_params(str
- 	params->fb.stride = cache->fb.stride;
- 
- 	params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
-+
-+	if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
-+		params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
-+						32 * fbc->threshold) * 8;
- }
- 
- static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
-@@ -1293,8 +1310,8 @@ void intel_fbc_init_pipe_state(struct dr
-  */
- static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
- {
--	if (i915.enable_fbc >= 0)
--		return !!i915.enable_fbc;
-+	if (i915_modparams.enable_fbc >= 0)
-+		return !!i915_modparams.enable_fbc;
- 
- 	if (!HAS_FBC(dev_priv))
- 		return 0;
-@@ -1338,8 +1355,9 @@ void intel_fbc_init(struct drm_i915_priv
- 	if (need_fbc_vtd_wa(dev_priv))
- 		mkwrite_device_info(dev_priv)->has_fbc = false;
- 
--	i915.enable_fbc = intel_sanitize_fbc_option(dev_priv);
--	DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc);
-+	i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
-+	DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
-+		      i915_modparams.enable_fbc);
- 
- 	if (!HAS_FBC(dev_priv)) {
- 		fbc->no_fbc_reason = "unsupported by this chipset";
---- linux-4.14/drivers/gpu/drm/i915/intel_fbdev.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_fbdev.c	2017-12-14 06:39:58.509903633 +0100
-@@ -206,6 +206,7 @@ static int intelfb_create(struct drm_fb_
- 	}
- 
- 	mutex_lock(&dev->struct_mutex);
-+	intel_runtime_pm_get(dev_priv);
- 
- 	/* Pin the GGTT vma for our access via info->screen_base.
- 	 * This also validates that any existing fb inherited from the
-@@ -269,6 +270,7 @@ static int intelfb_create(struct drm_fb_
- 		      fb->width, fb->height, i915_ggtt_offset(vma));
- 	ifbdev->vma = vma;
- 
-+	intel_runtime_pm_put(dev_priv);
- 	mutex_unlock(&dev->struct_mutex);
- 	vga_switcheroo_client_fb_set(pdev, info);
- 	return 0;
-@@ -276,6 +278,7 @@ static int intelfb_create(struct drm_fb_
- out_unpin:
- 	intel_unpin_fb_vma(vma);
- out_unlock:
-+	intel_runtime_pm_put(dev_priv);
- 	mutex_unlock(&dev->struct_mutex);
- 	return ret;
- }
---- linux-4.14/drivers/gpu/drm/i915/intel_fifo_underrun.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_fifo_underrun.c	2017-12-14 06:39:58.509903633 +0100
-@@ -88,14 +88,15 @@ static void i9xx_check_fifo_underruns(st
- {
- 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- 	i915_reg_t reg = PIPESTAT(crtc->pipe);
--	u32 pipestat = I915_READ(reg) & 0xffff0000;
-+	u32 enable_mask;
- 
- 	lockdep_assert_held(&dev_priv->irq_lock);
- 
--	if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
-+	if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
- 		return;
- 
--	I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
-+	enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
-+	I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
- 	POSTING_READ(reg);
- 
- 	trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);
-@@ -108,15 +109,16 @@ static void i9xx_set_fifo_underrun_repor
- {
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 	i915_reg_t reg = PIPESTAT(pipe);
--	u32 pipestat = I915_READ(reg) & 0xffff0000;
- 
- 	lockdep_assert_held(&dev_priv->irq_lock);
- 
- 	if (enable) {
--		I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
-+		u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
-+
-+		I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
- 		POSTING_READ(reg);
- 	} else {
--		if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
-+		if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS)
- 			DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
- 	}
- }
---- linux-4.14/drivers/gpu/drm/i915/intel_guc_fwif.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_guc_fwif.h	2017-12-14 06:39:58.509903633 +0100
-@@ -56,10 +56,6 @@
- #define WQ_LEN_SHIFT			16
- #define WQ_NO_WCFLUSH_WAIT		(1 << 27)
- #define WQ_PRESENT_WORKLOAD		(1 << 28)
--#define WQ_WORKLOAD_SHIFT		29
--#define   WQ_WORKLOAD_GENERAL		(0 << WQ_WORKLOAD_SHIFT)
--#define   WQ_WORKLOAD_GPGPU		(1 << WQ_WORKLOAD_SHIFT)
--#define   WQ_WORKLOAD_TOUCH		(2 << WQ_WORKLOAD_SHIFT)
- 
- #define WQ_RING_TAIL_SHIFT		20
- #define WQ_RING_TAIL_MAX		0x7FF	/* 2^11 QWords */
-@@ -388,7 +384,11 @@ struct guc_ct_buffer_desc {
- /* Preempt to idle on quantum expiry */
- #define POLICY_PREEMPT_TO_IDLE		(1<<1)
- 
--#define POLICY_MAX_NUM_WI		15
-+#define POLICY_MAX_NUM_WI 15
-+#define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
-+#define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
-+#define POLICY_DEFAULT_PREEMPTION_TIME_US 500000
-+#define POLICY_DEFAULT_FAULT_TIME_US 250000
- 
- struct guc_policy {
- 	/* Time for one workload to execute. (in micro seconds) */
---- linux-4.14/drivers/gpu/drm/i915/intel_guc_loader.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_guc_loader.c	2017-12-14 06:39:58.509903633 +0100
-@@ -131,14 +131,14 @@ static void guc_params_init(struct drm_i
- 
- 	params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
- 
--	if (i915.guc_log_level >= 0) {
-+	if (i915_modparams.guc_log_level >= 0) {
- 		params[GUC_CTL_DEBUG] =
--			i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
-+			i915_modparams.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
- 	} else
- 		params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
- 
- 	/* If GuC submission is enabled, set up additional parameters here */
--	if (i915.enable_guc_submission) {
-+	if (i915_modparams.enable_guc_submission) {
- 		u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
- 		u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
- 		u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
-@@ -368,7 +368,8 @@ int intel_guc_init_hw(struct intel_guc *
- 	guc->fw.load_status = INTEL_UC_FIRMWARE_SUCCESS;
- 
- 	DRM_INFO("GuC %s (firmware %s [version %u.%u])\n",
--		 i915.enable_guc_submission ? "submission enabled" : "loaded",
-+		 i915_modparams.enable_guc_submission ? "submission enabled" :
-+							"loaded",
- 		 guc->fw.path,
- 		 guc->fw.major_ver_found, guc->fw.minor_ver_found);
- 
-@@ -390,8 +391,8 @@ int intel_guc_select_fw(struct intel_guc
- 	guc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
- 	guc->fw.type = INTEL_UC_FW_TYPE_GUC;
- 
--	if (i915.guc_firmware_path) {
--		guc->fw.path = i915.guc_firmware_path;
-+	if (i915_modparams.guc_firmware_path) {
-+		guc->fw.path = i915_modparams.guc_firmware_path;
- 		guc->fw.major_ver_wanted = 0;
- 		guc->fw.minor_ver_wanted = 0;
- 	} else if (IS_SKYLAKE(dev_priv)) {
---- linux-4.14/drivers/gpu/drm/i915/intel_guc_log.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_guc_log.c	2017-12-14 06:39:58.509903633 +0100
-@@ -144,7 +144,7 @@ static int guc_log_relay_file_create(str
- 	struct dentry *log_dir;
- 	int ret;
- 
--	if (i915.guc_log_level < 0)
-+	if (i915_modparams.guc_log_level < 0)
- 		return 0;
- 
- 	/* For now create the log file in /sys/kernel/debug/dri/0 dir */
-@@ -480,7 +480,7 @@ err_runtime:
- 	guc_log_runtime_destroy(guc);
- err:
- 	/* logging will remain off */
--	i915.guc_log_level = -1;
-+	i915_modparams.guc_log_level = -1;
- 	return ret;
- }
- 
-@@ -502,7 +502,8 @@ static void guc_flush_logs(struct intel_
- {
- 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
- 
--	if (!i915.enable_guc_submission || (i915.guc_log_level < 0))
-+	if (!i915_modparams.enable_guc_submission ||
-+	    (i915_modparams.guc_log_level < 0))
- 		return;
- 
- 	/* First disable the interrupts, will be renabled afterwards */
-@@ -529,8 +530,8 @@ int intel_guc_log_create(struct intel_gu
- 
- 	GEM_BUG_ON(guc->log.vma);
- 
--	if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX)
--		i915.guc_log_level = GUC_LOG_VERBOSITY_MAX;
-+	if (i915_modparams.guc_log_level > GUC_LOG_VERBOSITY_MAX)
-+		i915_modparams.guc_log_level = GUC_LOG_VERBOSITY_MAX;
- 
- 	/* The first page is to save log buffer state. Allocate one
- 	 * extra page for others in case for overlap */
-@@ -555,7 +556,7 @@ int intel_guc_log_create(struct intel_gu
- 
- 	guc->log.vma = vma;
- 
--	if (i915.guc_log_level >= 0) {
-+	if (i915_modparams.guc_log_level >= 0) {
- 		ret = guc_log_runtime_create(guc);
- 		if (ret < 0)
- 			goto err_vma;
-@@ -576,7 +577,7 @@ err_vma:
- 	i915_vma_unpin_and_release(&guc->log.vma);
- err:
- 	/* logging will be off */
--	i915.guc_log_level = -1;
-+	i915_modparams.guc_log_level = -1;
- 	return ret;
- }
- 
-@@ -600,7 +601,7 @@ int i915_guc_log_control(struct drm_i915
- 		return -EINVAL;
- 
- 	/* This combination doesn't make sense & won't have any effect */
--	if (!log_param.logging_enabled && (i915.guc_log_level < 0))
-+	if (!log_param.logging_enabled && (i915_modparams.guc_log_level < 0))
- 		return 0;
- 
- 	ret = guc_log_control(guc, log_param.value);
-@@ -610,7 +611,7 @@ int i915_guc_log_control(struct drm_i915
- 	}
- 
- 	if (log_param.logging_enabled) {
--		i915.guc_log_level = log_param.verbosity;
-+		i915_modparams.guc_log_level = log_param.verbosity;
- 
- 		/* If log_level was set as -1 at boot time, then the relay channel file
- 		 * wouldn't have been created by now and interrupts also would not have
-@@ -633,7 +634,7 @@ int i915_guc_log_control(struct drm_i915
- 		guc_flush_logs(guc);
- 
- 		/* As logging is disabled, update log level to reflect that */
--		i915.guc_log_level = -1;
-+		i915_modparams.guc_log_level = -1;
- 	}
- 
- 	return ret;
-@@ -641,7 +642,8 @@ int i915_guc_log_control(struct drm_i915
- 
- void i915_guc_log_register(struct drm_i915_private *dev_priv)
- {
--	if (!i915.enable_guc_submission || i915.guc_log_level < 0)
-+	if (!i915_modparams.enable_guc_submission ||
-+	    (i915_modparams.guc_log_level < 0))
- 		return;
- 
- 	mutex_lock(&dev_priv->drm.struct_mutex);
-@@ -651,7 +653,7 @@ void i915_guc_log_register(struct drm_i9
- 
- void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
- {
--	if (!i915.enable_guc_submission)
-+	if (!i915_modparams.enable_guc_submission)
- 		return;
- 
- 	mutex_lock(&dev_priv->drm.struct_mutex);
---- linux-4.14/drivers/gpu/drm/i915/intel_gvt.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_gvt.c	2017-12-14 06:39:58.509903633 +0100
-@@ -58,7 +58,7 @@ static bool is_supported_device(struct d
-  */
- void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
- {
--	if (!i915.enable_gvt)
-+	if (!i915_modparams.enable_gvt)
- 		return;
- 
- 	if (intel_vgpu_active(dev_priv)) {
-@@ -73,7 +73,7 @@ void intel_gvt_sanitize_options(struct d
- 
- 	return;
- bail:
--	i915.enable_gvt = 0;
-+	i915_modparams.enable_gvt = 0;
- }
- 
- /**
-@@ -90,17 +90,17 @@ int intel_gvt_init(struct drm_i915_priva
- {
- 	int ret;
- 
--	if (!i915.enable_gvt) {
-+	if (!i915_modparams.enable_gvt) {
- 		DRM_DEBUG_DRIVER("GVT-g is disabled by kernel params\n");
- 		return 0;
- 	}
- 
--	if (!i915.enable_execlists) {
-+	if (!i915_modparams.enable_execlists) {
- 		DRM_ERROR("i915 GVT-g loading failed due to disabled execlists mode\n");
- 		return -EIO;
- 	}
- 
--	if (i915.enable_guc_submission) {
-+	if (i915_modparams.enable_guc_submission) {
- 		DRM_ERROR("i915 GVT-g loading failed due to Graphics virtualization is not yet supported with GuC submission\n");
- 		return -EIO;
- 	}
-@@ -123,7 +123,7 @@ int intel_gvt_init(struct drm_i915_priva
- 	return 0;
- 
- bail:
--	i915.enable_gvt = 0;
-+	i915_modparams.enable_gvt = 0;
- 	return 0;
- }
- 
---- linux-4.14/drivers/gpu/drm/i915/intel_hangcheck.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_hangcheck.c	2017-12-14 06:39:58.509903633 +0100
-@@ -428,7 +428,7 @@ static void i915_hangcheck_elapsed(struc
- 	unsigned int hung = 0, stuck = 0;
- 	int busy_count = 0;
- 
--	if (!i915.enable_hangcheck)
-+	if (!i915_modparams.enable_hangcheck)
- 		return;
- 
- 	if (!READ_ONCE(dev_priv->gt.awake))
---- linux-4.14/drivers/gpu/drm/i915/intel_hdmi.c.0130~	2017-12-14 06:39:58.300903487 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_hdmi.c	2017-12-14 06:39:58.509903633 +0100
-@@ -434,7 +434,7 @@ static void intel_write_infoframe(struct
- 				  const struct intel_crtc_state *crtc_state,
- 				  union hdmi_infoframe *frame)
- {
--	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
-+	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
- 	uint8_t buffer[VIDEO_DIP_DATA_SIZE];
- 	ssize_t len;
- 
-@@ -450,7 +450,7 @@ static void intel_write_infoframe(struct
- 	buffer[3] = 0;
- 	len++;
- 
--	intel_hdmi->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
-+	intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
- }
- 
- static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
-@@ -946,6 +946,7 @@ static void intel_hdmi_get_config(struct
- 				  struct intel_crtc_state *pipe_config)
- {
- 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
-+	struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
- 	struct drm_device *dev = encoder->base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 	u32 tmp, flags = 0;
-@@ -966,7 +967,7 @@ static void intel_hdmi_get_config(struct
- 	if (tmp & HDMI_MODE_SELECT_HDMI)
- 		pipe_config->has_hdmi_sink = true;
- 
--	if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
-+	if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
- 		pipe_config->has_infoframe = true;
- 
- 	if (tmp & SDVO_AUDIO_ENABLE)
-@@ -992,8 +993,8 @@ static void intel_hdmi_get_config(struct
- }
- 
- static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
--				    struct intel_crtc_state *pipe_config,
--				    struct drm_connector_state *conn_state)
-+				    const struct intel_crtc_state *pipe_config,
-+				    const struct drm_connector_state *conn_state)
- {
- 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
- 
-@@ -1004,8 +1005,8 @@ static void intel_enable_hdmi_audio(stru
- }
- 
- static void g4x_enable_hdmi(struct intel_encoder *encoder,
--			    struct intel_crtc_state *pipe_config,
--			    struct drm_connector_state *conn_state)
-+			    const struct intel_crtc_state *pipe_config,
-+			    const struct drm_connector_state *conn_state)
- {
- 	struct drm_device *dev = encoder->base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
-@@ -1026,8 +1027,8 @@ static void g4x_enable_hdmi(struct intel
- }
- 
- static void ibx_enable_hdmi(struct intel_encoder *encoder,
--			    struct intel_crtc_state *pipe_config,
--			    struct drm_connector_state *conn_state)
-+			    const struct intel_crtc_state *pipe_config,
-+			    const struct drm_connector_state *conn_state)
- {
- 	struct drm_device *dev = encoder->base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
-@@ -1076,8 +1077,8 @@ static void ibx_enable_hdmi(struct intel
- }
- 
- static void cpt_enable_hdmi(struct intel_encoder *encoder,
--			    struct intel_crtc_state *pipe_config,
--			    struct drm_connector_state *conn_state)
-+			    const struct intel_crtc_state *pipe_config,
-+			    const struct drm_connector_state *conn_state)
- {
- 	struct drm_device *dev = encoder->base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
-@@ -1131,18 +1132,20 @@ static void cpt_enable_hdmi(struct intel
- }
- 
- static void vlv_enable_hdmi(struct intel_encoder *encoder,
--			    struct intel_crtc_state *pipe_config,
--			    struct drm_connector_state *conn_state)
-+			    const struct intel_crtc_state *pipe_config,
-+			    const struct drm_connector_state *conn_state)
- {
- }
- 
- static void intel_disable_hdmi(struct intel_encoder *encoder,
--			       struct intel_crtc_state *old_crtc_state,
--			       struct drm_connector_state *old_conn_state)
-+			       const struct intel_crtc_state *old_crtc_state,
-+			       const struct drm_connector_state *old_conn_state)
- {
- 	struct drm_device *dev = encoder->base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
-+	struct intel_digital_port *intel_dig_port =
-+		hdmi_to_dig_port(intel_hdmi);
- 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
- 	u32 temp;
- 
-@@ -1185,14 +1188,15 @@ static void intel_disable_hdmi(struct in
- 		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
- 	}
- 
--	intel_hdmi->set_infoframes(&encoder->base, false, old_crtc_state, old_conn_state);
-+	intel_dig_port->set_infoframes(&encoder->base, false,
-+				       old_crtc_state, old_conn_state);
- 
- 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
- }
- 
- static void g4x_disable_hdmi(struct intel_encoder *encoder,
--			     struct intel_crtc_state *old_crtc_state,
--			     struct drm_connector_state *old_conn_state)
-+			     const struct intel_crtc_state *old_crtc_state,
-+			     const struct drm_connector_state *old_conn_state)
- {
- 	if (old_crtc_state->has_audio)
- 		intel_audio_codec_disable(encoder);
-@@ -1201,16 +1205,16 @@ static void g4x_disable_hdmi(struct inte
- }
- 
- static void pch_disable_hdmi(struct intel_encoder *encoder,
--			     struct intel_crtc_state *old_crtc_state,
--			     struct drm_connector_state *old_conn_state)
-+			     const struct intel_crtc_state *old_crtc_state,
-+			     const struct drm_connector_state *old_conn_state)
- {
- 	if (old_crtc_state->has_audio)
- 		intel_audio_codec_disable(encoder);
- }
- 
- static void pch_post_disable_hdmi(struct intel_encoder *encoder,
--				  struct intel_crtc_state *old_crtc_state,
--				  struct drm_connector_state *old_conn_state)
-+				  const struct intel_crtc_state *old_crtc_state,
-+				  const struct drm_connector_state *old_conn_state)
- {
- 	intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
- }
-@@ -1315,7 +1319,7 @@ intel_hdmi_mode_valid(struct drm_connect
- 	return status;
- }
- 
--static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
-+static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
- {
- 	struct drm_i915_private *dev_priv =
- 		to_i915(crtc_state->base.crtc->dev);
-@@ -1643,24 +1647,24 @@ static int intel_hdmi_get_modes(struct d
- }
- 
- static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
--				  struct intel_crtc_state *pipe_config,
--				  struct drm_connector_state *conn_state)
-+				  const struct intel_crtc_state *pipe_config,
-+				  const struct drm_connector_state *conn_state)
- {
--	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
-+	struct intel_digital_port *intel_dig_port =
-+		enc_to_dig_port(&encoder->base);
- 
- 	intel_hdmi_prepare(encoder, pipe_config);
- 
--	intel_hdmi->set_infoframes(&encoder->base,
--				   pipe_config->has_hdmi_sink,
--				   pipe_config, conn_state);
-+	intel_dig_port->set_infoframes(&encoder->base,
-+				       pipe_config->has_infoframe,
-+				       pipe_config, conn_state);
- }
- 
- static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
--				struct intel_crtc_state *pipe_config,
--				struct drm_connector_state *conn_state)
-+				const struct intel_crtc_state *pipe_config,
-+				const struct drm_connector_state *conn_state)
- {
- 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
--	struct intel_hdmi *intel_hdmi = &dport->hdmi;
- 	struct drm_device *dev = encoder->base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 
-@@ -1670,9 +1674,9 @@ static void vlv_hdmi_pre_enable(struct i
- 	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
- 				 0x2b247878);
- 
--	intel_hdmi->set_infoframes(&encoder->base,
--				   pipe_config->has_hdmi_sink,
--				   pipe_config, conn_state);
-+	dport->set_infoframes(&encoder->base,
-+			      pipe_config->has_infoframe,
-+			      pipe_config, conn_state);
- 
- 	g4x_enable_hdmi(encoder, pipe_config, conn_state);
- 
-@@ -1680,8 +1684,8 @@ static void vlv_hdmi_pre_enable(struct i
- }
- 
- static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
--				    struct intel_crtc_state *pipe_config,
--				    struct drm_connector_state *conn_state)
-+				    const struct intel_crtc_state *pipe_config,
-+				    const struct drm_connector_state *conn_state)
- {
- 	intel_hdmi_prepare(encoder, pipe_config);
- 
-@@ -1689,8 +1693,8 @@ static void vlv_hdmi_pre_pll_enable(stru
- }
- 
- static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
--				    struct intel_crtc_state *pipe_config,
--				    struct drm_connector_state *conn_state)
-+				    const struct intel_crtc_state *pipe_config,
-+				    const struct drm_connector_state *conn_state)
- {
- 	intel_hdmi_prepare(encoder, pipe_config);
- 
-@@ -1698,23 +1702,23 @@ static void chv_hdmi_pre_pll_enable(stru
- }
- 
- static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
--				      struct intel_crtc_state *old_crtc_state,
--				      struct drm_connector_state *old_conn_state)
-+				      const struct intel_crtc_state *old_crtc_state,
-+				      const struct drm_connector_state *old_conn_state)
- {
- 	chv_phy_post_pll_disable(encoder);
- }
- 
- static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
--				  struct intel_crtc_state *old_crtc_state,
--				  struct drm_connector_state *old_conn_state)
-+				  const struct intel_crtc_state *old_crtc_state,
-+				  const struct drm_connector_state *old_conn_state)
- {
- 	/* Reset lanes to avoid HDMI flicker (VLV w/a) */
- 	vlv_phy_reset_lanes(encoder);
- }
- 
- static void chv_hdmi_post_disable(struct intel_encoder *encoder,
--				  struct intel_crtc_state *old_crtc_state,
--				  struct drm_connector_state *old_conn_state)
-+				  const struct intel_crtc_state *old_crtc_state,
-+				  const struct drm_connector_state *old_conn_state)
- {
- 	struct drm_device *dev = encoder->base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
-@@ -1728,11 +1732,10 @@ static void chv_hdmi_post_disable(struct
- }
- 
- static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
--				struct intel_crtc_state *pipe_config,
--				struct drm_connector_state *conn_state)
-+				const struct intel_crtc_state *pipe_config,
-+				const struct drm_connector_state *conn_state)
- {
- 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
--	struct intel_hdmi *intel_hdmi = &dport->hdmi;
- 	struct drm_device *dev = encoder->base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 
-@@ -1742,9 +1745,9 @@ static void chv_hdmi_pre_enable(struct i
- 	/* Use 800mV-0dB */
- 	chv_set_phy_signal_level(encoder, 128, 102, false);
- 
--	intel_hdmi->set_infoframes(&encoder->base,
--				   pipe_config->has_hdmi_sink,
--				   pipe_config, conn_state);
-+	dport->set_infoframes(&encoder->base,
-+			      pipe_config->has_infoframe,
-+			      pipe_config, conn_state);
- 
- 	g4x_enable_hdmi(encoder, pipe_config, conn_state);
- 
-@@ -1959,6 +1962,34 @@ static u8 intel_hdmi_ddc_pin(struct drm_
- 	return ddc_pin;
- }
- 
-+void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
-+{
-+	struct drm_i915_private *dev_priv =
-+		to_i915(intel_dig_port->base.base.dev);
-+
-+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-+		intel_dig_port->write_infoframe = vlv_write_infoframe;
-+		intel_dig_port->set_infoframes = vlv_set_infoframes;
-+		intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
-+	} else if (IS_G4X(dev_priv)) {
-+		intel_dig_port->write_infoframe = g4x_write_infoframe;
-+		intel_dig_port->set_infoframes = g4x_set_infoframes;
-+		intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
-+	} else if (HAS_DDI(dev_priv)) {
-+		intel_dig_port->write_infoframe = hsw_write_infoframe;
-+		intel_dig_port->set_infoframes = hsw_set_infoframes;
-+		intel_dig_port->infoframe_enabled = hsw_infoframe_enabled;
-+	} else if (HAS_PCH_IBX(dev_priv)) {
-+		intel_dig_port->write_infoframe = ibx_write_infoframe;
-+		intel_dig_port->set_infoframes = ibx_set_infoframes;
-+		intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
-+	} else {
-+		intel_dig_port->write_infoframe = cpt_write_infoframe;
-+		intel_dig_port->set_infoframes = cpt_set_infoframes;
-+		intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
-+	}
-+}
-+
- void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
- 			       struct intel_connector *intel_connector)
- {
-@@ -1994,28 +2025,6 @@ void intel_hdmi_init_connector(struct in
- 		return;
- 	intel_encoder->hpd_pin = intel_hpd_pin(port);
- 
--	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
--		intel_hdmi->write_infoframe = vlv_write_infoframe;
--		intel_hdmi->set_infoframes = vlv_set_infoframes;
--		intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
--	} else if (IS_G4X(dev_priv)) {
--		intel_hdmi->write_infoframe = g4x_write_infoframe;
--		intel_hdmi->set_infoframes = g4x_set_infoframes;
--		intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
--	} else if (HAS_DDI(dev_priv)) {
--		intel_hdmi->write_infoframe = hsw_write_infoframe;
--		intel_hdmi->set_infoframes = hsw_set_infoframes;
--		intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
--	} else if (HAS_PCH_IBX(dev_priv)) {
--		intel_hdmi->write_infoframe = ibx_write_infoframe;
--		intel_hdmi->set_infoframes = ibx_set_infoframes;
--		intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
--	} else {
--		intel_hdmi->write_infoframe = cpt_write_infoframe;
--		intel_hdmi->set_infoframes = cpt_set_infoframes;
--		intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
--	}
--
- 	if (HAS_DDI(dev_priv))
- 		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
- 	else
-@@ -2114,5 +2123,7 @@ void intel_hdmi_init(struct drm_i915_pri
- 	intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
- 	intel_dig_port->max_lanes = 4;
- 
-+	intel_infoframe_init(intel_dig_port);
-+
- 	intel_hdmi_init_connector(intel_dig_port, intel_connector);
- }
---- linux-4.14/drivers/gpu/drm/i915/intel_huc.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_huc.c	2017-12-14 06:39:58.510903634 +0100
-@@ -155,8 +155,8 @@ void intel_huc_select_fw(struct intel_hu
- 	huc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
- 	huc->fw.type = INTEL_UC_FW_TYPE_HUC;
- 
--	if (i915.huc_firmware_path) {
--		huc->fw.path = i915.huc_firmware_path;
-+	if (i915_modparams.huc_firmware_path) {
-+		huc->fw.path = i915_modparams.huc_firmware_path;
- 		huc->fw.major_ver_wanted = 0;
- 		huc->fw.minor_ver_wanted = 0;
- 	} else if (IS_SKYLAKE(dev_priv)) {
-@@ -225,19 +225,22 @@ void intel_huc_init_hw(struct intel_huc
- }
- 
- /**
-- * intel_guc_auth_huc() - authenticate ucode
-- * @dev_priv: the drm_i915_device
-+ * intel_huc_auth() - Authenticate HuC uCode
-+ * @huc: intel_huc structure
-+ *
-+ * Called after HuC and GuC firmware loading during intel_uc_init_hw().
-  *
-- * Triggers a HuC fw authentication request to the GuC via intel_guc_action_
-- * authenticate_huc interface.
-+ * This function pins HuC firmware image object into GGTT.
-+ * Then it invokes GuC action to authenticate passing the offset to RSA
-+ * signature through intel_guc_auth_huc(). It then waits for 50ms for
-+ * firmware verification ACK and unpins the object.
-  */
--void intel_guc_auth_huc(struct drm_i915_private *dev_priv)
-+void intel_huc_auth(struct intel_huc *huc)
- {
--	struct intel_guc *guc = &dev_priv->guc;
--	struct intel_huc *huc = &dev_priv->huc;
-+	struct drm_i915_private *i915 = huc_to_i915(huc);
-+	struct intel_guc *guc = &i915->guc;
- 	struct i915_vma *vma;
- 	int ret;
--	u32 data[2];
- 
- 	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- 		return;
-@@ -250,23 +253,19 @@ void intel_guc_auth_huc(struct drm_i915_
- 		return;
- 	}
- 
--	/* Specify auth action and where public signature is. */
--	data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC;
--	data[1] = guc_ggtt_offset(vma) + huc->fw.rsa_offset;
--
--	ret = intel_guc_send(guc, data, ARRAY_SIZE(data));
-+	ret = intel_guc_auth_huc(guc,
-+				 guc_ggtt_offset(vma) + huc->fw.rsa_offset);
- 	if (ret) {
- 		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
- 		goto out;
- 	}
- 
- 	/* Check authentication status, it should be done by now */
--	ret = intel_wait_for_register(dev_priv,
--				HUC_STATUS2,
--				HUC_FW_VERIFIED,
--				HUC_FW_VERIFIED,
--				50);
--
-+	ret = intel_wait_for_register(i915,
-+				      HUC_STATUS2,
-+				      HUC_FW_VERIFIED,
-+				      HUC_FW_VERIFIED,
-+				      50);
- 	if (ret) {
- 		DRM_ERROR("HuC: Authentication failed %d\n", ret);
- 		goto out;
-@@ -275,4 +274,3 @@ void intel_guc_auth_huc(struct drm_i915_
- out:
- 	i915_vma_unpin(vma);
- }
--
---- linux-4.14/drivers/gpu/drm/i915/intel_lrc.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_lrc.c	2017-12-14 06:39:58.510903634 +0100
-@@ -244,7 +244,7 @@ int intel_sanitize_enable_execlists(stru
- 
- 	if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
- 	    USES_PPGTT(dev_priv) &&
--	    i915.use_mmio_flip >= 0)
-+	    i915_modparams.use_mmio_flip >= 0)
- 		return 1;
- 
- 	return 0;
-@@ -279,17 +279,73 @@ intel_lr_context_descriptor_update(struc
- 	BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
- 
- 	desc = ctx->desc_template;				/* bits  0-11 */
--	desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE;
-+	desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
- 								/* bits 12-31 */
- 	desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT;		/* bits 32-52 */
- 
- 	ce->lrc_desc = desc;
- }
- 
--uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
--				     struct intel_engine_cs *engine)
-+static struct i915_priolist *
-+lookup_priolist(struct intel_engine_cs *engine,
-+		struct i915_priotree *pt,
-+		int prio)
- {
--	return ctx->engine[engine->id].lrc_desc;
-+	struct intel_engine_execlists * const execlists = &engine->execlists;
-+	struct i915_priolist *p;
-+	struct rb_node **parent, *rb;
-+	bool first = true;
-+
-+	if (unlikely(execlists->no_priolist))
-+		prio = I915_PRIORITY_NORMAL;
-+
-+find_priolist:
-+	/* most positive priority is scheduled first, equal priorities fifo */
-+	rb = NULL;
-+	parent = &execlists->queue.rb_node;
-+	while (*parent) {
-+		rb = *parent;
-+		p = rb_entry(rb, typeof(*p), node);
-+		if (prio > p->priority) {
-+			parent = &rb->rb_left;
-+		} else if (prio < p->priority) {
-+			parent = &rb->rb_right;
-+			first = false;
-+		} else {
-+			return p;
-+		}
-+	}
-+
-+	if (prio == I915_PRIORITY_NORMAL) {
-+		p = &execlists->default_priolist;
-+	} else {
-+		p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
-+		/* Convert an allocation failure to a priority bump */
-+		if (unlikely(!p)) {
-+			prio = I915_PRIORITY_NORMAL; /* recurses just once */
-+
-+			/* To maintain ordering with all rendering, after an
-+			 * allocation failure we have to disable all scheduling.
-+			 * Requests will then be executed in fifo, and schedule
-+			 * will ensure that dependencies are emitted in fifo.
-+			 * There will be still some reordering with existing
-+			 * requests, so if userspace lied about their
-+			 * dependencies that reordering may be visible.
-+			 */
-+			execlists->no_priolist = true;
-+			goto find_priolist;
-+		}
-+	}
-+
-+	p->priority = prio;
-+	INIT_LIST_HEAD(&p->requests);
-+	rb_link_node(&p->node, rb, parent);
-+	rb_insert_color(&p->node, &execlists->queue);
-+
-+	if (first)
-+		execlists->first = &p->node;
-+
-+	return ptr_pack_bits(p, first, 1);
- }
- 
- static inline void
-@@ -338,12 +394,12 @@ static u64 execlists_update_context(stru
- 
- static void execlists_submit_ports(struct intel_engine_cs *engine)
- {
--	struct execlist_port *port = engine->execlist_port;
-+	struct execlist_port *port = engine->execlists.port;
- 	u32 __iomem *elsp =
- 		engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
- 	unsigned int n;
- 
--	for (n = ARRAY_SIZE(engine->execlist_port); n--; ) {
-+	for (n = execlists_num_ports(&engine->execlists); n--; ) {
- 		struct drm_i915_gem_request *rq;
- 		unsigned int count;
- 		u64 desc;
-@@ -398,7 +454,10 @@ static void port_assign(struct execlist_
- static void execlists_dequeue(struct intel_engine_cs *engine)
- {
- 	struct drm_i915_gem_request *last;
--	struct execlist_port *port = engine->execlist_port;
-+	struct intel_engine_execlists * const execlists = &engine->execlists;
-+	struct execlist_port *port = execlists->port;
-+	const struct execlist_port * const last_port =
-+		&execlists->port[execlists->port_mask];
- 	struct rb_node *rb;
- 	bool submit = false;
- 
-@@ -412,8 +471,6 @@ static void execlists_dequeue(struct int
- 		 */
- 		last->tail = last->wa_tail;
- 
--	GEM_BUG_ON(port_isset(&port[1]));
--
- 	/* Hardware submission is through 2 ports. Conceptually each port
- 	 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
- 	 * static for a context, and unique to each, so we only execute
-@@ -436,8 +493,8 @@ static void execlists_dequeue(struct int
- 	 */
- 
- 	spin_lock_irq(&engine->timeline->lock);
--	rb = engine->execlist_first;
--	GEM_BUG_ON(rb_first(&engine->execlist_queue) != rb);
-+	rb = execlists->first;
-+	GEM_BUG_ON(rb_first(&execlists->queue) != rb);
- 	while (rb) {
- 		struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
- 		struct drm_i915_gem_request *rq, *rn;
-@@ -460,7 +517,7 @@ static void execlists_dequeue(struct int
- 				 * combine this request with the last, then we
- 				 * are done.
- 				 */
--				if (port != engine->execlist_port) {
-+				if (port == last_port) {
- 					__list_del_many(&p->requests,
- 							&rq->priotree.link);
- 					goto done;
-@@ -485,25 +542,27 @@ static void execlists_dequeue(struct int
- 				if (submit)
- 					port_assign(port, last);
- 				port++;
-+
-+				GEM_BUG_ON(port_isset(port));
- 			}
- 
- 			INIT_LIST_HEAD(&rq->priotree.link);
- 			rq->priotree.priority = INT_MAX;
- 
- 			__i915_gem_request_submit(rq);
--			trace_i915_gem_request_in(rq, port_index(port, engine));
-+			trace_i915_gem_request_in(rq, port_index(port, execlists));
- 			last = rq;
- 			submit = true;
- 		}
- 
- 		rb = rb_next(rb);
--		rb_erase(&p->node, &engine->execlist_queue);
-+		rb_erase(&p->node, &execlists->queue);
- 		INIT_LIST_HEAD(&p->requests);
- 		if (p->priority != I915_PRIORITY_NORMAL)
- 			kmem_cache_free(engine->i915->priorities, p);
- 	}
- done:
--	engine->execlist_first = rb;
-+	execlists->first = rb;
- 	if (submit)
- 		port_assign(port, last);
- 	spin_unlock_irq(&engine->timeline->lock);
-@@ -512,9 +571,83 @@ done:
- 		execlists_submit_ports(engine);
- }
- 
-+static void
-+execlist_cancel_port_requests(struct intel_engine_execlists *execlists)
-+{
-+	struct execlist_port *port = execlists->port;
-+	unsigned int num_ports = ARRAY_SIZE(execlists->port);
-+
-+	while (num_ports-- && port_isset(port)) {
-+		struct drm_i915_gem_request *rq = port_request(port);
-+
-+		execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
-+		i915_gem_request_put(rq);
-+
-+		memset(port, 0, sizeof(*port));
-+		port++;
-+	}
-+}
-+
-+static void execlists_cancel_requests(struct intel_engine_cs *engine)
-+{
-+	struct intel_engine_execlists * const execlists = &engine->execlists;
-+	struct drm_i915_gem_request *rq, *rn;
-+	struct rb_node *rb;
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&engine->timeline->lock, flags);
-+
-+	/* Cancel the requests on the HW and clear the ELSP tracker. */
-+	execlist_cancel_port_requests(execlists);
-+
-+	/* Mark all executing requests as skipped. */
-+	list_for_each_entry(rq, &engine->timeline->requests, link) {
-+		GEM_BUG_ON(!rq->global_seqno);
-+		if (!i915_gem_request_completed(rq))
-+			dma_fence_set_error(&rq->fence, -EIO);
-+	}
-+
-+	/* Flush the queued requests to the timeline list (for retiring). */
-+	rb = execlists->first;
-+	while (rb) {
-+		struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
-+
-+		list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
-+			INIT_LIST_HEAD(&rq->priotree.link);
-+			rq->priotree.priority = INT_MAX;
-+
-+			dma_fence_set_error(&rq->fence, -EIO);
-+			__i915_gem_request_submit(rq);
-+		}
-+
-+		rb = rb_next(rb);
-+		rb_erase(&p->node, &execlists->queue);
-+		INIT_LIST_HEAD(&p->requests);
-+		if (p->priority != I915_PRIORITY_NORMAL)
-+			kmem_cache_free(engine->i915->priorities, p);
-+	}
-+
-+	/* Remaining _unready_ requests will be nop'ed when submitted */
-+
-+
-+	execlists->queue = RB_ROOT;
-+	execlists->first = NULL;
-+	GEM_BUG_ON(port_isset(execlists->port));
-+
-+	/*
-+	 * The port is checked prior to scheduling a tasklet, but
-+	 * just in case we have suspended the tasklet to do the
-+	 * wedging make sure that when it wakes, it decides there
-+	 * is no work to do by clearing the irq_posted bit.
-+	 */
-+	clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
-+
-+	spin_unlock_irqrestore(&engine->timeline->lock, flags);
-+}
-+
- static bool execlists_elsp_ready(const struct intel_engine_cs *engine)
- {
--	const struct execlist_port *port = engine->execlist_port;
-+	const struct execlist_port *port = engine->execlists.port;
- 
- 	return port_count(&port[0]) + port_count(&port[1]) < 2;
- }
-@@ -525,8 +658,9 @@ static bool execlists_elsp_ready(const s
-  */
- static void intel_lrc_irq_handler(unsigned long data)
- {
--	struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
--	struct execlist_port *port = engine->execlist_port;
-+	struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
-+	struct intel_engine_execlists * const execlists = &engine->execlists;
-+	struct execlist_port *port = execlists->port;
- 	struct drm_i915_private *dev_priv = engine->i915;
- 
- 	/* We can skip acquiring intel_runtime_pm_get() here as it was taken
-@@ -538,19 +672,25 @@ static void intel_lrc_irq_handler(unsign
- 	 */
- 	GEM_BUG_ON(!dev_priv->gt.awake);
- 
--	intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
-+	intel_uncore_forcewake_get(dev_priv, execlists->fw_domains);
- 
- 	/* Prefer doing test_and_clear_bit() as a two stage operation to avoid
- 	 * imposing the cost of a locked atomic transaction when submitting a
- 	 * new request (outside of the context-switch interrupt).
- 	 */
- 	while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
--		u32 __iomem *csb_mmio =
--			dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
--		u32 __iomem *buf =
--			dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));
-+		/* The HWSP contains a (cacheable) mirror of the CSB */
-+		const u32 *buf =
-+			&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
- 		unsigned int head, tail;
- 
-+		/* However GVT emulation depends upon intercepting CSB mmio */
-+		if (unlikely(execlists->csb_use_mmio)) {
-+			buf = (u32 * __force)
-+				(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
-+			execlists->csb_head = -1; /* force mmio read of CSB ptrs */
-+		}
-+
- 		/* The write will be ordered by the uncached read (itself
- 		 * a memory barrier), so we do not need another in the form
- 		 * of a locked instruction. The race between the interrupt
-@@ -562,9 +702,20 @@ static void intel_lrc_irq_handler(unsign
- 		 * is set and we do a new loop.
- 		 */
- 		__clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
--		head = readl(csb_mmio);
--		tail = GEN8_CSB_WRITE_PTR(head);
--		head = GEN8_CSB_READ_PTR(head);
-+		if (unlikely(execlists->csb_head == -1)) { /* following a reset */
-+			head = readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
-+			tail = GEN8_CSB_WRITE_PTR(head);
-+			head = GEN8_CSB_READ_PTR(head);
-+			execlists->csb_head = head;
-+		} else {
-+			const int write_idx =
-+				intel_hws_csb_write_index(dev_priv) -
-+				I915_HWS_CSB_BUF0_INDEX;
-+
-+			head = execlists->csb_head;
-+			tail = READ_ONCE(buf[write_idx]);
-+		}
-+
- 		while (head != tail) {
- 			struct drm_i915_gem_request *rq;
- 			unsigned int status;
-@@ -590,13 +741,12 @@ static void intel_lrc_irq_handler(unsign
- 			 * status notifier.
- 			 */
- 
--			status = readl(buf + 2 * head);
-+			status = READ_ONCE(buf[2 * head]); /* maybe mmio! */
- 			if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
- 				continue;
- 
- 			/* Check the context/desc id for this event matches */
--			GEM_DEBUG_BUG_ON(readl(buf + 2 * head + 1) !=
--					 port->context_id);
-+			GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id);
- 
- 			rq = port_unpack(port, &count);
- 			GEM_BUG_ON(count == 0);
-@@ -608,8 +758,7 @@ static void intel_lrc_irq_handler(unsign
- 				trace_i915_gem_request_out(rq);
- 				i915_gem_request_put(rq);
- 
--				port[0] = port[1];
--				memset(&port[1], 0, sizeof(port[1]));
-+				execlists_port_complete(execlists, port);
- 			} else {
- 				port_set(port, port_pack(rq, count));
- 			}
-@@ -619,78 +768,28 @@ static void intel_lrc_irq_handler(unsign
- 				   !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
- 		}
- 
--		writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
--		       csb_mmio);
-+		if (head != execlists->csb_head) {
-+			execlists->csb_head = head;
-+			writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
-+			       dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
-+		}
- 	}
- 
- 	if (execlists_elsp_ready(engine))
- 		execlists_dequeue(engine);
- 
--	intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
-+	intel_uncore_forcewake_put(dev_priv, execlists->fw_domains);
- }
- 
--static bool
--insert_request(struct intel_engine_cs *engine,
--	       struct i915_priotree *pt,
--	       int prio)
-+static void insert_request(struct intel_engine_cs *engine,
-+			   struct i915_priotree *pt,
-+			   int prio)
- {
--	struct i915_priolist *p;
--	struct rb_node **parent, *rb;
--	bool first = true;
--
--	if (unlikely(engine->no_priolist))
--		prio = I915_PRIORITY_NORMAL;
--
--find_priolist:
--	/* most positive priority is scheduled first, equal priorities fifo */
--	rb = NULL;
--	parent = &engine->execlist_queue.rb_node;
--	while (*parent) {
--		rb = *parent;
--		p = rb_entry(rb, typeof(*p), node);
--		if (prio > p->priority) {
--			parent = &rb->rb_left;
--		} else if (prio < p->priority) {
--			parent = &rb->rb_right;
--			first = false;
--		} else {
--			list_add_tail(&pt->link, &p->requests);
--			return false;
--		}
--	}
--
--	if (prio == I915_PRIORITY_NORMAL) {
--		p = &engine->default_priolist;
--	} else {
--		p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
--		/* Convert an allocation failure to a priority bump */
--		if (unlikely(!p)) {
--			prio = I915_PRIORITY_NORMAL; /* recurses just once */
--
--			/* To maintain ordering with all rendering, after an
--			 * allocation failure we have to disable all scheduling.
--			 * Requests will then be executed in fifo, and schedule
--			 * will ensure that dependencies are emitted in fifo.
--			 * There will be still some reordering with existing
--			 * requests, so if userspace lied about their
--			 * dependencies that reordering may be visible.
--			 */
--			engine->no_priolist = true;
--			goto find_priolist;
--		}
--	}
--
--	p->priority = prio;
--	rb_link_node(&p->node, rb, parent);
--	rb_insert_color(&p->node, &engine->execlist_queue);
--
--	INIT_LIST_HEAD(&p->requests);
--	list_add_tail(&pt->link, &p->requests);
--
--	if (first)
--		engine->execlist_first = &p->node;
-+	struct i915_priolist *p = lookup_priolist(engine, pt, prio);
- 
--	return first;
-+	list_add_tail(&pt->link, &ptr_mask_bits(p, 1)->requests);
-+	if (ptr_unmask_bits(p, 1) && execlists_elsp_ready(engine))
-+		tasklet_hi_schedule(&engine->execlists.irq_tasklet);
- }
- 
- static void execlists_submit_request(struct drm_i915_gem_request *request)
-@@ -701,14 +800,9 @@ static void execlists_submit_request(str
- 	/* Will be called from irq-context when using foreign fences. */
- 	spin_lock_irqsave(&engine->timeline->lock, flags);
- 
--	if (insert_request(engine,
--			   &request->priotree,
--			   request->priotree.priority)) {
--		if (execlists_elsp_ready(engine))
--			tasklet_hi_schedule(&engine->irq_tasklet);
--	}
-+	insert_request(engine, &request->priotree, request->priotree.priority);
- 
--	GEM_BUG_ON(!engine->execlist_first);
-+	GEM_BUG_ON(!engine->execlists.first);
- 	GEM_BUG_ON(list_empty(&request->priotree.link));
- 
- 	spin_unlock_irqrestore(&engine->timeline->lock, flags);
-@@ -914,27 +1008,14 @@ static int execlists_request_alloc(struc
- 	 */
- 	request->reserved_space += EXECLISTS_REQUEST_SIZE;
- 
--	if (i915.enable_guc_submission) {
--		/*
--		 * Check that the GuC has space for the request before
--		 * going any further, as the i915_add_request() call
--		 * later on mustn't fail ...
--		 */
--		ret = i915_guc_wq_reserve(request);
--		if (ret)
--			goto err;
--	}
--
- 	cs = intel_ring_begin(request, 0);
--	if (IS_ERR(cs)) {
--		ret = PTR_ERR(cs);
--		goto err_unreserve;
--	}
-+	if (IS_ERR(cs))
-+		return PTR_ERR(cs);
- 
- 	if (!ce->initialised) {
- 		ret = engine->init_context(request);
- 		if (ret)
--			goto err_unreserve;
-+			return ret;
- 
- 		ce->initialised = true;
- 	}
-@@ -948,12 +1029,6 @@ static int execlists_request_alloc(struc
- 
- 	request->reserved_space -= EXECLISTS_REQUEST_SIZE;
- 	return 0;
--
--err_unreserve:
--	if (i915.enable_guc_submission)
--		i915_guc_wq_unreserve(request);
--err:
--	return ret;
- }
- 
- /*
-@@ -1116,13 +1191,6 @@ static u32 *gen9_init_indirectctx_bb(str
- 	return batch;
- }
- 
--static u32 *gen9_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
--{
--	*batch++ = MI_BATCH_BUFFER_END;
--
--	return batch;
--}
--
- #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
- 
- static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
-@@ -1175,9 +1243,11 @@ static int intel_init_workaround_bb(stru
- 		return -EINVAL;
- 
- 	switch (INTEL_GEN(engine->i915)) {
-+	case 10:
-+		return 0;
- 	case 9:
- 		wa_bb_fn[0] = gen9_init_indirectctx_bb;
--		wa_bb_fn[1] = gen9_init_perctx_bb;
-+		wa_bb_fn[1] = NULL;
- 		break;
- 	case 8:
- 		wa_bb_fn[0] = gen8_init_indirectctx_bb;
-@@ -1208,7 +1278,8 @@ static int intel_init_workaround_bb(stru
- 			ret = -EINVAL;
- 			break;
- 		}
--		batch_ptr = wa_bb_fn[i](engine, batch_ptr);
-+		if (wa_bb_fn[i])
-+			batch_ptr = wa_bb_fn[i](engine, batch_ptr);
- 		wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
- 	}
- 
-@@ -1232,9 +1303,7 @@ static u8 gtiir[] = {
- static int gen8_init_common_ring(struct intel_engine_cs *engine)
- {
- 	struct drm_i915_private *dev_priv = engine->i915;
--	struct execlist_port *port = engine->execlist_port;
--	unsigned int n;
--	bool submit;
-+	struct intel_engine_execlists * const execlists = &engine->execlists;
- 	int ret;
- 
- 	ret = intel_mocs_init_engine(engine);
-@@ -1267,24 +1336,11 @@ static int gen8_init_common_ring(struct
- 	I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
- 		   GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
- 	clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
-+	execlists->csb_head = -1;
- 
- 	/* After a GPU reset, we may have requests to replay */
--	submit = false;
--	for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
--		if (!port_isset(&port[n]))
--			break;
--
--		DRM_DEBUG_DRIVER("Restarting %s:%d from 0x%x\n",
--				 engine->name, n,
--				 port_request(&port[n])->global_seqno);
--
--		/* Discard the current inflight count */
--		port_set(&port[n], port_request(&port[n]));
--		submit = true;
--	}
--
--	if (submit && !i915.enable_guc_submission)
--		execlists_submit_ports(engine);
-+	if (!i915_modparams.enable_guc_submission && execlists->first)
-+		tasklet_schedule(&execlists->irq_tasklet);
- 
- 	return 0;
- }
-@@ -1325,9 +1381,12 @@ static int gen9_init_render_ring(struct
- static void reset_common_ring(struct intel_engine_cs *engine,
- 			      struct drm_i915_gem_request *request)
- {
--	struct execlist_port *port = engine->execlist_port;
-+	struct intel_engine_execlists * const execlists = &engine->execlists;
-+	struct drm_i915_gem_request *rq, *rn;
- 	struct intel_context *ce;
--	unsigned int n;
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&engine->timeline->lock, flags);
- 
- 	/*
- 	 * Catch up with any missed context-switch interrupts.
-@@ -1338,20 +1397,26 @@ static void reset_common_ring(struct int
- 	 * guessing the missed context-switch events by looking at what
- 	 * requests were completed.
- 	 */
--	if (!request) {
--		for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
--			i915_gem_request_put(port_request(&port[n]));
--		memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
--		return;
--	}
-+	execlist_cancel_port_requests(execlists);
- 
--	if (request->ctx != port_request(port)->ctx) {
--		i915_gem_request_put(port_request(port));
--		port[0] = port[1];
--		memset(&port[1], 0, sizeof(port[1]));
-+	/* Push back any incomplete requests for replay after the reset. */
-+	list_for_each_entry_safe_reverse(rq, rn,
-+					 &engine->timeline->requests, link) {
-+		struct i915_priolist *p;
-+
-+		if (i915_gem_request_completed(rq))
-+			break;
-+
-+		__i915_gem_request_unsubmit(rq);
-+
-+		p = lookup_priolist(engine,
-+				    &rq->priotree,
-+				    rq->priotree.priority);
-+		list_add(&rq->priotree.link,
-+			 &ptr_mask_bits(p, 1)->requests);
- 	}
- 
--	GEM_BUG_ON(request->ctx != port_request(port)->ctx);
-+	spin_unlock_irqrestore(&engine->timeline->lock, flags);
- 
- 	/* If the request was innocent, we leave the request in the ELSP
- 	 * and will try to replay it on restarting. The context image may
-@@ -1363,7 +1428,7 @@ static void reset_common_ring(struct int
- 	 * and have to at least restore the RING register in the context
- 	 * image back to the expected values to skip over the guilty request.
- 	 */
--	if (request->fence.error != -EIO)
-+	if (!request || request->fence.error != -EIO)
- 		return;
- 
- 	/* We want a simple context + ring to execute the breadcrumb update.
-@@ -1666,8 +1731,8 @@ void intel_logical_ring_cleanup(struct i
- 	 * Tasklet cannot be active at this point due intel_mark_active/idle
- 	 * so this is just for documentation.
- 	 */
--	if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
--		tasklet_kill(&engine->irq_tasklet);
-+	if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->execlists.irq_tasklet.state)))
-+		tasklet_kill(&engine->execlists.irq_tasklet);
- 
- 	dev_priv = engine->i915;
- 
-@@ -1678,11 +1743,6 @@ void intel_logical_ring_cleanup(struct i
- 	if (engine->cleanup)
- 		engine->cleanup(engine);
- 
--	if (engine->status_page.vma) {
--		i915_gem_object_unpin_map(engine->status_page.vma->obj);
--		engine->status_page.vma = NULL;
--	}
--
- 	intel_engine_cleanup_common(engine);
- 
- 	lrc_destroy_wa_ctx(engine);
-@@ -1694,8 +1754,9 @@ void intel_logical_ring_cleanup(struct i
- static void execlists_set_default_submission(struct intel_engine_cs *engine)
- {
- 	engine->submit_request = execlists_submit_request;
-+	engine->cancel_requests = execlists_cancel_requests;
- 	engine->schedule = execlists_schedule;
--	engine->irq_tasklet.func = intel_lrc_irq_handler;
-+	engine->execlists.irq_tasklet.func = intel_lrc_irq_handler;
- }
- 
- static void
-@@ -1729,24 +1790,6 @@ logical_ring_default_irqs(struct intel_e
- 	engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
- }
- 
--static int
--lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma)
--{
--	const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE;
--	void *hws;
--
--	/* The HWSP is part of the default context object in LRC mode. */
--	hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
--	if (IS_ERR(hws))
--		return PTR_ERR(hws);
--
--	engine->status_page.page_addr = hws + hws_offset;
--	engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset;
--	engine->status_page.vma = vma;
--
--	return 0;
--}
--
- static void
- logical_ring_setup(struct intel_engine_cs *engine)
- {
-@@ -1770,32 +1813,23 @@ logical_ring_setup(struct intel_engine_c
- 						     RING_CONTEXT_STATUS_BUF_BASE(engine),
- 						     FW_REG_READ);
- 
--	engine->fw_domains = fw_domains;
-+	engine->execlists.fw_domains = fw_domains;
- 
--	tasklet_init(&engine->irq_tasklet,
-+	tasklet_init(&engine->execlists.irq_tasklet,
- 		     intel_lrc_irq_handler, (unsigned long)engine);
- 
- 	logical_ring_default_vfuncs(engine);
- 	logical_ring_default_irqs(engine);
- }
- 
--static int
--logical_ring_init(struct intel_engine_cs *engine)
-+static int logical_ring_init(struct intel_engine_cs *engine)
- {
--	struct i915_gem_context *dctx = engine->i915->kernel_context;
- 	int ret;
- 
- 	ret = intel_engine_init_common(engine);
- 	if (ret)
- 		goto error;
- 
--	/* And setup the hardware status page. */
--	ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
--	if (ret) {
--		DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
--		goto error;
--	}
--
- 	return 0;
- 
- error:
-@@ -1953,13 +1987,12 @@ static void execlists_init_reg_state(u32
- 	CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
- 	CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
- 	if (rcs) {
--		CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
-+		struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
-+
- 		CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
- 		CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
- 			RING_INDIRECT_CTX_OFFSET(base), 0);
--
--		if (engine->wa_ctx.vma) {
--			struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
-+		if (wa_ctx->indirect_ctx.size) {
- 			u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
- 
- 			regs[CTX_RCS_INDIRECT_CTX + 1] =
-@@ -1968,6 +2001,11 @@ static void execlists_init_reg_state(u32
- 
- 			regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
- 				intel_lr_indirect_ctx_offset(engine) << 6;
-+		}
-+
-+		CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
-+		if (wa_ctx->per_ctx.size) {
-+			u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
- 
- 			regs[CTX_BB_PER_CTX_PTR + 1] =
- 				(ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
-@@ -2052,8 +2090,11 @@ static int execlists_context_deferred_al
- 
- 	context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
- 
--	/* One extra page as the sharing data between driver and GuC */
--	context_size += PAGE_SIZE * LRC_PPHWSP_PN;
-+	/*
-+	 * Before the actual start of the context image, we insert a few pages
-+	 * for our own use and for sharing with the GuC.
-+	 */
-+	context_size += LRC_HEADER_PAGES * PAGE_SIZE;
- 
- 	ctx_obj = i915_gem_object_create(ctx->i915, context_size);
- 	if (IS_ERR(ctx_obj)) {
---- linux-4.14/drivers/gpu/drm/i915/intel_lrc.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_lrc.h	2017-12-14 06:39:58.510903634 +0100
-@@ -25,6 +25,7 @@
- #define _INTEL_LRC_H_
- 
- #include "intel_ringbuffer.h"
-+#include "i915_gem_context.h"
- 
- #define GEN8_LR_CONTEXT_ALIGN I915_GTT_MIN_ALIGNMENT
- 
-@@ -69,17 +70,42 @@ int logical_xcs_ring_init(struct intel_e
- 
- /* Logical Ring Contexts */
- 
--/* One extra page is added before LRC for GuC as shared data */
-+/*
-+ * We allocate a header at the start of the context image for our own
-+ * use, therefore the actual location of the logical state is offset
-+ * from the start of the VMA. The layout is
-+ *
-+ * | [guc]          | [hwsp] [logical state] |
-+ * |<- our header ->|<- context image      ->|
-+ *
-+ */
-+/* The first page is used for sharing data with the GuC */
- #define LRC_GUCSHR_PN	(0)
--#define LRC_PPHWSP_PN	(LRC_GUCSHR_PN + 1)
--#define LRC_STATE_PN	(LRC_PPHWSP_PN + 1)
-+#define LRC_GUCSHR_SZ	(1)
-+/* At the start of the context image is its per-process HWS page */
-+#define LRC_PPHWSP_PN	(LRC_GUCSHR_PN + LRC_GUCSHR_SZ)
-+#define LRC_PPHWSP_SZ	(1)
-+/* Finally we have the logical state for the context */
-+#define LRC_STATE_PN	(LRC_PPHWSP_PN + LRC_PPHWSP_SZ)
-+
-+/*
-+ * Currently we include the PPHWSP in __intel_engine_context_size() so
-+ * the size of the header is synonymous with the start of the PPHWSP.
-+ */
-+#define LRC_HEADER_PAGES LRC_PPHWSP_PN
- 
- struct drm_i915_private;
- struct i915_gem_context;
- 
- void intel_lr_context_resume(struct drm_i915_private *dev_priv);
--uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
--				     struct intel_engine_cs *engine);
-+
-+static inline uint64_t
-+intel_lr_context_descriptor(struct i915_gem_context *ctx,
-+			    struct intel_engine_cs *engine)
-+{
-+	return ctx->engine[engine->id].lrc_desc;
-+}
-+
- 
- /* Execlists */
- int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
---- linux-4.14/drivers/gpu/drm/i915/intel_lvds.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_lvds.c	2017-12-14 06:39:58.510903634 +0100
-@@ -229,8 +229,8 @@ static void intel_lvds_pps_init_hw(struc
- }
- 
- static void intel_pre_enable_lvds(struct intel_encoder *encoder,
--				  struct intel_crtc_state *pipe_config,
--				  struct drm_connector_state *conn_state)
-+				  const struct intel_crtc_state *pipe_config,
-+				  const struct drm_connector_state *conn_state)
- {
- 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-@@ -306,8 +306,8 @@ static void intel_pre_enable_lvds(struct
-  * Sets the power state for the panel.
-  */
- static void intel_enable_lvds(struct intel_encoder *encoder,
--			      struct intel_crtc_state *pipe_config,
--			      struct drm_connector_state *conn_state)
-+			      const struct intel_crtc_state *pipe_config,
-+			      const struct drm_connector_state *conn_state)
- {
- 	struct drm_device *dev = encoder->base.dev;
- 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
-@@ -324,8 +324,8 @@ static void intel_enable_lvds(struct int
- }
- 
- static void intel_disable_lvds(struct intel_encoder *encoder,
--			       struct intel_crtc_state *old_crtc_state,
--			       struct drm_connector_state *old_conn_state)
-+			       const struct intel_crtc_state *old_crtc_state,
-+			       const struct drm_connector_state *old_conn_state)
- {
- 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-@@ -339,8 +339,8 @@ static void intel_disable_lvds(struct in
- }
- 
- static void gmch_disable_lvds(struct intel_encoder *encoder,
--			      struct intel_crtc_state *old_crtc_state,
--			      struct drm_connector_state *old_conn_state)
-+			      const struct intel_crtc_state *old_crtc_state,
-+			      const struct drm_connector_state *old_conn_state)
- 
- {
- 	intel_panel_disable_backlight(old_conn_state);
-@@ -349,15 +349,15 @@ static void gmch_disable_lvds(struct int
- }
- 
- static void pch_disable_lvds(struct intel_encoder *encoder,
--			     struct intel_crtc_state *old_crtc_state,
--			     struct drm_connector_state *old_conn_state)
-+			     const struct intel_crtc_state *old_crtc_state,
-+			     const struct drm_connector_state *old_conn_state)
- {
- 	intel_panel_disable_backlight(old_conn_state);
- }
- 
- static void pch_post_disable_lvds(struct intel_encoder *encoder,
--				  struct intel_crtc_state *old_crtc_state,
--				  struct drm_connector_state *old_conn_state)
-+				  const struct intel_crtc_state *old_crtc_state,
-+				  const struct drm_connector_state *old_conn_state)
- {
- 	intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
- }
-@@ -880,8 +880,8 @@ static bool compute_is_dual_link_lvds(st
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 
- 	/* use the module option value if specified */
--	if (i915.lvds_channel_mode > 0)
--		return i915.lvds_channel_mode == 2;
-+	if (i915_modparams.lvds_channel_mode > 0)
-+		return i915_modparams.lvds_channel_mode == 2;
- 
- 	/* single channel LVDS is limited to 112 MHz */
- 	if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
---- linux-4.14/drivers/gpu/drm/i915/intel_opregion.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_opregion.c	2017-12-14 06:39:58.510903634 +0100
-@@ -921,7 +921,7 @@ static int intel_load_vbt_firmware(struc
- {
- 	struct intel_opregion *opregion = &dev_priv->opregion;
- 	const struct firmware *fw = NULL;
--	const char *name = i915.vbt_firmware;
-+	const char *name = i915_modparams.vbt_firmware;
- 	int ret;
- 
- 	if (!name || !*name)
---- linux-4.14/drivers/gpu/drm/i915/intel_overlay.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_overlay.c	2017-12-14 06:39:58.510903634 +0100
-@@ -1134,7 +1134,7 @@ int intel_overlay_put_image_ioctl(struct
- 	if (!params)
- 		return -ENOMEM;
- 
--	drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id);
-+	drmmode_crtc = drm_crtc_find(dev, file_priv, put_image_rec->crtc_id);
- 	if (!drmmode_crtc) {
- 		ret = -ENOENT;
- 		goto out_free;
---- linux-4.14/drivers/gpu/drm/i915/intel_panel.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_panel.c	2017-12-14 06:39:58.511903634 +0100
-@@ -379,13 +379,13 @@ enum drm_connector_status
- intel_panel_detect(struct drm_i915_private *dev_priv)
- {
- 	/* Assume that the BIOS does not lie through the OpRegion... */
--	if (!i915.panel_ignore_lid && dev_priv->opregion.lid_state) {
-+	if (!i915_modparams.panel_ignore_lid && dev_priv->opregion.lid_state) {
- 		return *dev_priv->opregion.lid_state & 0x1 ?
- 			connector_status_connected :
- 			connector_status_disconnected;
- 	}
- 
--	switch (i915.panel_ignore_lid) {
-+	switch (i915_modparams.panel_ignore_lid) {
- 	case -2:
- 		return connector_status_connected;
- 	case -1:
-@@ -465,10 +465,10 @@ static u32 intel_panel_compute_brightnes
- 
- 	WARN_ON(panel->backlight.max == 0);
- 
--	if (i915.invert_brightness < 0)
-+	if (i915_modparams.invert_brightness < 0)
- 		return val;
- 
--	if (i915.invert_brightness > 0 ||
-+	if (i915_modparams.invert_brightness > 0 ||
- 	    dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
- 		return panel->backlight.max - val + panel->backlight.min;
- 	}
---- linux-4.14/drivers/gpu/drm/i915/intel_pipe_crc.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_pipe_crc.c	2017-12-14 06:39:58.511903634 +0100
-@@ -506,8 +506,8 @@ static int ilk_pipe_crc_ctl_reg(enum int
- 	return 0;
- }
- 
--static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
--					bool enable)
-+static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
-+			      bool enable)
- {
- 	struct drm_device *dev = &dev_priv->drm;
- 	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
-@@ -533,10 +533,24 @@ retry:
- 		goto put_state;
- 	}
- 
--	pipe_config->pch_pfit.force_thru = enable;
--	if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
--	    pipe_config->pch_pfit.enabled != enable)
--		pipe_config->base.connectors_changed = true;
-+	if (HAS_IPS(dev_priv)) {
-+		/*
-+		 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
-+		 * enabled and disabled dynamically based on package C states,
-+		 * user space can't make reliable use of the CRCs, so let's just
-+		 * completely disable it.
-+		 */
-+		pipe_config->ips_force_disable = enable;
-+		if (pipe_config->ips_enabled == enable)
-+			pipe_config->base.connectors_changed = true;
-+	}
-+
-+	if (IS_HASWELL(dev_priv)) {
-+		pipe_config->pch_pfit.force_thru = enable;
-+		if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
-+		    pipe_config->pch_pfit.enabled != enable)
-+			pipe_config->base.connectors_changed = true;
-+	}
- 
- 	ret = drm_atomic_commit(state);
- 
-@@ -570,8 +584,9 @@ static int ivb_pipe_crc_ctl_reg(struct d
- 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
- 		break;
- 	case INTEL_PIPE_CRC_SOURCE_PF:
--		if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
--			hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
-+		if ((IS_HASWELL(dev_priv) ||
-+		     IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
-+			hsw_pipe_A_crc_wa(dev_priv, true);
- 
- 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
- 		break;
-@@ -606,7 +621,6 @@ static int pipe_crc_set_source(struct dr
- 			       enum intel_pipe_crc_source source)
- {
- 	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
--	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
- 	enum intel_display_power_domain power_domain;
- 	u32 val = 0; /* shut up gcc */
- 	int ret;
-@@ -643,14 +657,6 @@ static int pipe_crc_set_source(struct dr
- 			goto out;
- 		}
- 
--		/*
--		 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
--		 * enabled and disabled dynamically based on package C states,
--		 * user space can't make reliable use of the CRCs, so let's just
--		 * completely disable it.
--		 */
--		hsw_disable_ips(crtc);
--
- 		spin_lock_irq(&pipe_crc->lock);
- 		kfree(pipe_crc->entries);
- 		pipe_crc->entries = entries;
-@@ -691,10 +697,9 @@ static int pipe_crc_set_source(struct dr
- 			g4x_undo_pipe_scramble_reset(dev_priv, pipe);
- 		else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- 			vlv_undo_pipe_scramble_reset(dev_priv, pipe);
--		else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
--			hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
--
--		hsw_enable_ips(crtc);
-+		else if ((IS_HASWELL(dev_priv) ||
-+			  IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
-+			hsw_pipe_A_crc_wa(dev_priv, false);
- 	}
- 
- 	ret = 0;
-@@ -914,7 +919,6 @@ int intel_crtc_set_crc_source(struct drm
- {
- 	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
- 	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
--	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- 	enum intel_display_power_domain power_domain;
- 	enum intel_pipe_crc_source source;
- 	u32 val = 0; /* shut up gcc */
-@@ -935,16 +939,6 @@ int intel_crtc_set_crc_source(struct drm
- 	if (ret != 0)
- 		goto out;
- 
--	if (source) {
--		/*
--		 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
--		 * enabled and disabled dynamically based on package C states,
--		 * user space can't make reliable use of the CRCs, so let's just
--		 * completely disable it.
--		 */
--		hsw_disable_ips(intel_crtc);
--	}
--
- 	I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
- 	POSTING_READ(PIPE_CRC_CTL(crtc->index));
- 
-@@ -953,10 +947,9 @@ int intel_crtc_set_crc_source(struct drm
- 			g4x_undo_pipe_scramble_reset(dev_priv, crtc->index);
- 		else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- 			vlv_undo_pipe_scramble_reset(dev_priv, crtc->index);
--		else if (IS_HASWELL(dev_priv) && crtc->index == PIPE_A)
--			hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
--
--		hsw_enable_ips(intel_crtc);
-+		else if ((IS_HASWELL(dev_priv) ||
-+			  IS_BROADWELL(dev_priv)) && crtc->index == PIPE_A)
-+			hsw_pipe_A_crc_wa(dev_priv, false);
- 	}
- 
- 	pipe_crc->skipped = 0;
---- linux-4.14/drivers/gpu/drm/i915/intel_pm.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_pm.c	2017-12-14 06:39:58.512903635 +0100
-@@ -58,24 +58,23 @@
- 
- static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
- {
-+	if (HAS_LLC(dev_priv)) {
-+		/*
-+		 * WaCompressedResourceDisplayNewHashMode:skl,kbl
-+		 * Display WA#0390: skl,kbl
-+		 *
-+		 * Must match Sampler, Pixel Back End, and Media. See
-+		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
-+		 */
-+		I915_WRITE(CHICKEN_PAR1_1,
-+			   I915_READ(CHICKEN_PAR1_1) |
-+			   SKL_DE_COMPRESSED_HASH_MODE);
-+	}
-+
- 	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
- 	I915_WRITE(CHICKEN_PAR1_1,
- 		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
- 
--	/*
--	 * Display WA#0390: skl,bxt,kbl,glk
--	 *
--	 * Must match Sampler, Pixel Back End, and Media
--	 * (0xE194 bit 8, 0x7014 bit 13, 0x4DDC bits 27 and 31).
--	 *
--	 * Including bits outside the page in the hash would
--	 * require 2 (or 4?) MiB alignment of resources. Just
--	 * assume the defaul hashing mode which only uses bits
--	 * within the page.
--	 */
--	I915_WRITE(CHICKEN_PAR1_1,
--		   I915_READ(CHICKEN_PAR1_1) & ~SKL_RC_HASH_OUTSIDE);
--
- 	I915_WRITE(GEN8_CONFIG0,
- 		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
- 
-@@ -125,6 +124,7 @@ static void bxt_init_clock_gating(struct
- 
- static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
- {
-+	u32 val;
- 	gen9_init_clock_gating(dev_priv);
- 
- 	/*
-@@ -144,6 +144,11 @@ static void glk_init_clock_gating(struct
- 		I915_WRITE(CHICKEN_MISC_2, val);
- 	}
- 
-+	/* Display WA #1133: WaFbcSkipSegments:glk */
-+	val = I915_READ(ILK_DPFC_CHICKEN);
-+	val &= ~GLK_SKIP_SEG_COUNT_MASK;
-+	val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
-+	I915_WRITE(ILK_DPFC_CHICKEN, val);
- }
- 
- static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
-@@ -1322,21 +1327,21 @@ static int g4x_compute_pipe_wm(struct in
- 	int num_active_planes = hweight32(crtc_state->active_planes &
- 					  ~BIT(PLANE_CURSOR));
- 	const struct g4x_pipe_wm *raw;
--	struct intel_plane_state *plane_state;
-+	const struct intel_plane_state *old_plane_state;
-+	const struct intel_plane_state *new_plane_state;
- 	struct intel_plane *plane;
- 	enum plane_id plane_id;
- 	int i, level;
- 	unsigned int dirty = 0;
- 
--	for_each_intel_plane_in_state(state, plane, plane_state, i) {
--		const struct intel_plane_state *old_plane_state =
--			to_intel_plane_state(plane->base.state);
--
--		if (plane_state->base.crtc != &crtc->base &&
-+	for_each_oldnew_intel_plane_in_state(state, plane,
-+					     old_plane_state,
-+					     new_plane_state, i) {
-+		if (new_plane_state->base.crtc != &crtc->base &&
- 		    old_plane_state->base.crtc != &crtc->base)
- 			continue;
- 
--		if (g4x_raw_plane_wm_compute(crtc_state, plane_state))
-+		if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
- 			dirty |= BIT(plane->id);
- 	}
- 
-@@ -1831,21 +1836,21 @@ static int vlv_compute_pipe_wm(struct in
- 	int num_active_planes = hweight32(crtc_state->active_planes &
- 					  ~BIT(PLANE_CURSOR));
- 	bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
--	struct intel_plane_state *plane_state;
-+	const struct intel_plane_state *old_plane_state;
-+	const struct intel_plane_state *new_plane_state;
- 	struct intel_plane *plane;
- 	enum plane_id plane_id;
- 	int level, ret, i;
- 	unsigned int dirty = 0;
- 
--	for_each_intel_plane_in_state(state, plane, plane_state, i) {
--		const struct intel_plane_state *old_plane_state =
--			to_intel_plane_state(plane->base.state);
--
--		if (plane_state->base.crtc != &crtc->base &&
-+	for_each_oldnew_intel_plane_in_state(state, plane,
-+					     old_plane_state,
-+					     new_plane_state, i) {
-+		if (new_plane_state->base.crtc != &crtc->base &&
- 		    old_plane_state->base.crtc != &crtc->base)
- 			continue;
- 
--		if (vlv_raw_plane_wm_compute(crtc_state, plane_state))
-+		if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
- 			dirty |= BIT(plane->id);
- 	}
- 
-@@ -1864,7 +1869,7 @@ static int vlv_compute_pipe_wm(struct in
- 	/* cursor changes don't warrant a FIFO recompute */
- 	if (dirty & ~BIT(PLANE_CURSOR)) {
- 		const struct intel_crtc_state *old_crtc_state =
--			to_intel_crtc_state(crtc->base.state);
-+			intel_atomic_get_old_crtc_state(state, crtc);
- 		const struct vlv_fifo_state *old_fifo_state =
- 			&old_crtc_state->wm.vlv.fifo_state;
- 
-@@ -4361,134 +4366,147 @@ skl_adjusted_plane_pixel_rate(const stru
- 					    downscale_amount);
- }
- 
--static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
--				struct intel_crtc_state *cstate,
--				const struct intel_plane_state *intel_pstate,
--				uint16_t ddb_allocation,
--				int level,
--				uint16_t *out_blocks, /* out */
--				uint8_t *out_lines, /* out */
--				bool *enabled /* out */)
-+static int
-+skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
-+			    struct intel_crtc_state *cstate,
-+			    const struct intel_plane_state *intel_pstate,
-+			    struct skl_wm_params *wp)
- {
- 	struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
- 	const struct drm_plane_state *pstate = &intel_pstate->base;
- 	const struct drm_framebuffer *fb = pstate->fb;
--	uint32_t latency = dev_priv->wm.skl_latency[level];
--	uint_fixed_16_16_t method1, method2;
--	uint_fixed_16_16_t plane_blocks_per_line;
--	uint_fixed_16_16_t selected_result;
- 	uint32_t interm_pbpl;
--	uint32_t plane_bytes_per_line;
--	uint32_t res_blocks, res_lines;
--	uint8_t cpp;
--	uint32_t width = 0;
--	uint32_t plane_pixel_rate;
--	uint_fixed_16_16_t y_tile_minimum;
--	uint32_t y_min_scanlines;
- 	struct intel_atomic_state *state =
- 		to_intel_atomic_state(cstate->base.state);
- 	bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
--	bool y_tiled, x_tiled;
- 
--	if (latency == 0 ||
--	    !intel_wm_plane_visible(cstate, intel_pstate)) {
--		*enabled = false;
-+	if (!intel_wm_plane_visible(cstate, intel_pstate))
- 		return 0;
--	}
- 
--	y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
--		  fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
--		  fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
--		  fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
--	x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
--
--	/* Display WA #1141: kbl,cfl */
--	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
--	    dev_priv->ipc_enabled)
--		latency += 4;
--
--	if (apply_memory_bw_wa && x_tiled)
--		latency += 15;
-+	wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
-+		      fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
-+		      fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-+		      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
-+	wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
-+	wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
-+			 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
- 
- 	if (plane->id == PLANE_CURSOR) {
--		width = intel_pstate->base.crtc_w;
-+		wp->width = intel_pstate->base.crtc_w;
- 	} else {
- 		/*
- 		 * Src coordinates are already rotated by 270 degrees for
- 		 * the 90/270 degree plane rotation cases (to match the
- 		 * GTT mapping), hence no need to account for rotation here.
- 		 */
--		width = drm_rect_width(&intel_pstate->base.src) >> 16;
-+		wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
- 	}
- 
--	cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
--							fb->format->cpp[0];
--	plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
-+	wp->cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
-+							    fb->format->cpp[0];
-+	wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
-+							     intel_pstate);
- 
- 	if (drm_rotation_90_or_270(pstate->rotation)) {
- 
--		switch (cpp) {
-+		switch (wp->cpp) {
- 		case 1:
--			y_min_scanlines = 16;
-+			wp->y_min_scanlines = 16;
- 			break;
- 		case 2:
--			y_min_scanlines = 8;
-+			wp->y_min_scanlines = 8;
- 			break;
- 		case 4:
--			y_min_scanlines = 4;
-+			wp->y_min_scanlines = 4;
- 			break;
- 		default:
--			MISSING_CASE(cpp);
-+			MISSING_CASE(wp->cpp);
- 			return -EINVAL;
- 		}
- 	} else {
--		y_min_scanlines = 4;
-+		wp->y_min_scanlines = 4;
- 	}
- 
- 	if (apply_memory_bw_wa)
--		y_min_scanlines *= 2;
-+		wp->y_min_scanlines *= 2;
- 
--	plane_bytes_per_line = width * cpp;
--	if (y_tiled) {
--		interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
--					   y_min_scanlines, 512);
-+	wp->plane_bytes_per_line = wp->width * wp->cpp;
-+	if (wp->y_tiled) {
-+		interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
-+					   wp->y_min_scanlines, 512);
- 
- 		if (INTEL_GEN(dev_priv) >= 10)
- 			interm_pbpl++;
- 
--		plane_blocks_per_line = div_fixed16(interm_pbpl,
--							y_min_scanlines);
--	} else if (x_tiled && INTEL_GEN(dev_priv) == 9) {
--		interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
--		plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
-+		wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
-+							wp->y_min_scanlines);
-+	} else if (wp->x_tiled && IS_GEN9(dev_priv)) {
-+		interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512);
-+		wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
- 	} else {
--		interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
--		plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
-+		interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512) + 1;
-+		wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
-+	}
-+
-+	wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,
-+					     wp->plane_blocks_per_line);
-+	wp->linetime_us = fixed16_to_u32_round_up(
-+					intel_get_linetime_us(cstate));
-+
-+	return 0;
-+}
-+
-+static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
-+				struct intel_crtc_state *cstate,
-+				const struct intel_plane_state *intel_pstate,
-+				uint16_t ddb_allocation,
-+				int level,
-+				const struct skl_wm_params *wp,
-+				uint16_t *out_blocks, /* out */
-+				uint8_t *out_lines, /* out */
-+				bool *enabled /* out */)
-+{
-+	const struct drm_plane_state *pstate = &intel_pstate->base;
-+	uint32_t latency = dev_priv->wm.skl_latency[level];
-+	uint_fixed_16_16_t method1, method2;
-+	uint_fixed_16_16_t selected_result;
-+	uint32_t res_blocks, res_lines;
-+	struct intel_atomic_state *state =
-+		to_intel_atomic_state(cstate->base.state);
-+	bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
-+
-+	if (latency == 0 ||
-+	    !intel_wm_plane_visible(cstate, intel_pstate)) {
-+		*enabled = false;
-+		return 0;
- 	}
- 
--	method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency);
--	method2 = skl_wm_method2(plane_pixel_rate,
-+	/* Display WA #1141: kbl,cfl */
-+	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
-+	    IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) &&
-+	    dev_priv->ipc_enabled)
-+		latency += 4;
-+
-+	if (apply_memory_bw_wa && wp->x_tiled)
-+		latency += 15;
-+
-+	method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
-+				 wp->cpp, latency);
-+	method2 = skl_wm_method2(wp->plane_pixel_rate,
- 				 cstate->base.adjusted_mode.crtc_htotal,
- 				 latency,
--				 plane_blocks_per_line);
-+				 wp->plane_blocks_per_line);
- 
--	y_tile_minimum = mul_u32_fixed16(y_min_scanlines,
--					 plane_blocks_per_line);
--
--	if (y_tiled) {
--		selected_result = max_fixed16(method2, y_tile_minimum);
-+	if (wp->y_tiled) {
-+		selected_result = max_fixed16(method2, wp->y_tile_minimum);
- 	} else {
--		uint32_t linetime_us;
--
--		linetime_us = fixed16_to_u32_round_up(
--				intel_get_linetime_us(cstate));
--		if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
--		    (plane_bytes_per_line / 512 < 1))
-+		if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
-+		     512 < 1) && (wp->plane_bytes_per_line / 512 < 1))
- 			selected_result = method2;
- 		else if (ddb_allocation >=
--			 fixed16_to_u32_round_up(plane_blocks_per_line))
-+			 fixed16_to_u32_round_up(wp->plane_blocks_per_line))
- 			selected_result = min_fixed16(method1, method2);
--		else if (latency >= linetime_us)
-+		else if (latency >= wp->linetime_us)
- 			selected_result = min_fixed16(method1, method2);
- 		else
- 			selected_result = method1;
-@@ -4496,19 +4514,18 @@ static int skl_compute_plane_wm(const st
- 
- 	res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
- 	res_lines = div_round_up_fixed16(selected_result,
--					 plane_blocks_per_line);
-+					 wp->plane_blocks_per_line);
- 
- 	/* Display WA #1125: skl,bxt,kbl,glk */
--	if (level == 0 &&
--	    (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
--	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
--		res_blocks += fixed16_to_u32_round_up(y_tile_minimum);
-+	if (level == 0 && wp->rc_surface)
-+		res_blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
- 
- 	/* Display WA #1126: skl,bxt,kbl,glk */
- 	if (level >= 1 && level <= 7) {
--		if (y_tiled) {
--			res_blocks += fixed16_to_u32_round_up(y_tile_minimum);
--			res_lines += y_min_scanlines;
-+		if (wp->y_tiled) {
-+			res_blocks += fixed16_to_u32_round_up(
-+							wp->y_tile_minimum);
-+			res_lines += wp->y_min_scanlines;
- 		} else {
- 			res_blocks++;
- 		}
-@@ -4546,6 +4563,7 @@ skl_compute_wm_levels(const struct drm_i
- 		      struct skl_ddb_allocation *ddb,
- 		      struct intel_crtc_state *cstate,
- 		      const struct intel_plane_state *intel_pstate,
-+		      const struct skl_wm_params *wm_params,
- 		      struct skl_plane_wm *wm)
- {
- 	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
-@@ -4569,6 +4587,7 @@ skl_compute_wm_levels(const struct drm_i
- 					   intel_pstate,
- 					   ddb_blocks,
- 					   level,
-+					   wm_params,
- 					   &result->plane_res_b,
- 					   &result->plane_res_l,
- 					   &result->plane_en);
-@@ -4594,20 +4613,65 @@ skl_compute_linetime_wm(struct intel_crt
- 
- 	linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
- 
--	/* Display WA #1135: bxt. */
--	if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
--		linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
-+	/* Display WA #1135: bxt:ALL GLK:ALL */
-+	if ((IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) &&
-+	    dev_priv->ipc_enabled)
-+		linetime_wm /= 2;
- 
- 	return linetime_wm;
- }
- 
- static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
-+				      struct skl_wm_params *wp,
-+				      struct skl_wm_level *wm_l0,
-+				      uint16_t ddb_allocation,
- 				      struct skl_wm_level *trans_wm /* out */)
- {
-+	struct drm_device *dev = cstate->base.crtc->dev;
-+	const struct drm_i915_private *dev_priv = to_i915(dev);
-+	uint16_t trans_min, trans_y_tile_min;
-+	const uint16_t trans_amount = 10; /* This is configurable amount */
-+	uint16_t trans_offset_b, res_blocks;
-+
- 	if (!cstate->base.active)
-+		goto exit;
-+
-+	/* Transition WM are not recommended by HW team for GEN9 */
-+	if (INTEL_GEN(dev_priv) <= 9)
-+		goto exit;
-+
-+	/* Transition WM don't make any sense if ipc is disabled */
-+	if (!dev_priv->ipc_enabled)
-+		goto exit;
-+
-+	if (INTEL_GEN(dev_priv) >= 10)
-+		trans_min = 4;
-+
-+	trans_offset_b = trans_min + trans_amount;
-+
-+	if (wp->y_tiled) {
-+		trans_y_tile_min = (uint16_t) mul_round_up_u32_fixed16(2,
-+							wp->y_tile_minimum);
-+		res_blocks = max(wm_l0->plane_res_b, trans_y_tile_min) +
-+				trans_offset_b;
-+	} else {
-+		res_blocks = wm_l0->plane_res_b + trans_offset_b;
-+
-+		/* WA BUG:1938466 add one block for non y-tile planes */
-+		if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
-+			res_blocks += 1;
-+
-+	}
-+
-+	res_blocks += 1;
-+
-+	if (res_blocks < ddb_allocation) {
-+		trans_wm->plane_res_b = res_blocks;
-+		trans_wm->plane_en = true;
- 		return;
-+	}
- 
--	/* Until we know more, just disable transition WMs */
-+exit:
- 	trans_wm->plane_en = false;
- }
- 
-@@ -4633,14 +4697,25 @@ static int skl_build_pipe_wm(struct inte
- 		const struct intel_plane_state *intel_pstate =
- 						to_intel_plane_state(pstate);
- 		enum plane_id plane_id = to_intel_plane(plane)->id;
-+		struct skl_wm_params wm_params;
-+		enum pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe;
-+		uint16_t ddb_blocks;
- 
- 		wm = &pipe_wm->planes[plane_id];
-+		ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
-+		memset(&wm_params, 0, sizeof(struct skl_wm_params));
-+
-+		ret = skl_compute_plane_wm_params(dev_priv, cstate,
-+						  intel_pstate, &wm_params);
-+		if (ret)
-+			return ret;
- 
- 		ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
--					    intel_pstate, wm);
-+					    intel_pstate, &wm_params, wm);
- 		if (ret)
- 			return ret;
--		skl_compute_transition_wm(cstate, &wm->trans_wm);
-+		skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
-+					  ddb_blocks, &wm->trans_wm);
- 	}
- 	pipe_wm->linetime = skl_compute_linetime_wm(cstate);
- 
-@@ -5739,6 +5814,30 @@ void intel_update_watermarks(struct inte
- 		dev_priv->display.update_wm(crtc);
- }
- 
-+void intel_enable_ipc(struct drm_i915_private *dev_priv)
-+{
-+	u32 val;
-+
-+	val = I915_READ(DISP_ARB_CTL2);
-+
-+	if (dev_priv->ipc_enabled)
-+		val |= DISP_IPC_ENABLE;
-+	else
-+		val &= ~DISP_IPC_ENABLE;
-+
-+	I915_WRITE(DISP_ARB_CTL2, val);
-+}
-+
-+void intel_init_ipc(struct drm_i915_private *dev_priv)
-+{
-+	dev_priv->ipc_enabled = false;
-+	if (!HAS_IPC(dev_priv))
-+		return;
-+
-+	dev_priv->ipc_enabled = true;
-+	intel_enable_ipc(dev_priv);
-+}
-+
- /*
-  * Lock protecting IPS related data structures
-  */
-@@ -6160,6 +6259,7 @@ void gen6_rps_boost(struct drm_i915_gem_
- 		    struct intel_rps_client *rps)
- {
- 	struct drm_i915_private *i915 = rq->i915;
-+	unsigned long flags;
- 	bool boost;
- 
- 	/* This is intentionally racy! We peek at the state here, then
-@@ -6169,13 +6269,13 @@ void gen6_rps_boost(struct drm_i915_gem_
- 		return;
- 
- 	boost = false;
--	spin_lock_irq(&rq->lock);
-+	spin_lock_irqsave(&rq->lock, flags);
- 	if (!rq->waitboost && !i915_gem_request_completed(rq)) {
- 		atomic_inc(&i915->rps.num_waiters);
- 		rq->waitboost = true;
- 		boost = true;
- 	}
--	spin_unlock_irq(&rq->lock);
-+	spin_unlock_irqrestore(&rq->lock, flags);
- 	if (!boost)
- 		return;
- 
-@@ -7716,7 +7816,7 @@ void intel_init_gt_powersave(struct drm_
- 	 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
- 	 * requirement.
- 	 */
--	if (!i915.enable_rc6) {
-+	if (!i915_modparams.enable_rc6) {
- 		DRM_INFO("RC6 disabled, disabling runtime PM support\n");
- 		intel_runtime_pm_get(dev_priv);
- 	}
-@@ -7773,7 +7873,7 @@ void intel_cleanup_gt_powersave(struct d
- 	if (IS_VALLEYVIEW(dev_priv))
- 		valleyview_cleanup_gt_powersave(dev_priv);
- 
--	if (!i915.enable_rc6)
-+	if (!i915_modparams.enable_rc6)
- 		intel_runtime_pm_put(dev_priv);
- }
- 
-@@ -7895,7 +7995,7 @@ static void __intel_autoenable_gt_powers
- 	if (IS_ERR(req))
- 		goto unlock;
- 
--	if (!i915.enable_execlists && i915_switch_context(req) == 0)
-+	if (!i915_modparams.enable_execlists && i915_switch_context(req) == 0)
- 		rcs->init_context(req);
- 
- 	/* Mark the device busy, calling intel_enable_gt_powersave() */
-@@ -7971,7 +8071,7 @@ static void ilk_init_lp_watermarks(struc
- 	 */
- }
- 
--static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
-+static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
- {
- 	uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
- 
-@@ -8257,7 +8357,57 @@ static void gen8_set_l3sqc_credits(struc
- 	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
- }
- 
--static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
-+static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
-+{
-+	if (!HAS_PCH_CNP(dev_priv))
-+		return;
-+
-+	/* Wa #1181 */
-+	I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
-+		   CNP_PWM_CGE_GATING_DISABLE);
-+}
-+
-+static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-+{
-+	u32 val;
-+	cnp_init_clock_gating(dev_priv);
-+
-+	/* This is not an Wa. Enable for better image quality */
-+	I915_WRITE(_3D_CHICKEN3,
-+		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
-+
-+	/* WaEnableChickenDCPR:cnl */
-+	I915_WRITE(GEN8_CHICKEN_DCPR_1,
-+		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
-+
-+	/* WaFbcWakeMemOn:cnl */
-+	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
-+		   DISP_FBC_MEMORY_WAKE);
-+
-+	/* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
-+	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
-+		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
-+			   I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
-+			   SARBUNIT_CLKGATE_DIS);
-+
-+	/* Display WA #1133: WaFbcSkipSegments:cnl */
-+	val = I915_READ(ILK_DPFC_CHICKEN);
-+	val &= ~GLK_SKIP_SEG_COUNT_MASK;
-+	val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
-+	I915_WRITE(ILK_DPFC_CHICKEN, val);
-+}
-+
-+static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
-+{
-+	cnp_init_clock_gating(dev_priv);
-+	gen9_init_clock_gating(dev_priv);
-+
-+	/* WaFbcNukeOnHostModify:cfl */
-+	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
-+		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
-+}
-+
-+static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
- {
- 	gen9_init_clock_gating(dev_priv);
- 
-@@ -8271,12 +8421,12 @@ static void kabylake_init_clock_gating(s
- 		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
- 			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
- 
--	/* WaFbcNukeOnHostModify:kbl,cfl */
-+	/* WaFbcNukeOnHostModify:kbl */
- 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
- 		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
- }
- 
--static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
-+static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
- {
- 	gen9_init_clock_gating(dev_priv);
- 
-@@ -8289,7 +8439,7 @@ static void skylake_init_clock_gating(st
- 		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
- }
- 
--static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
-+static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
- {
- 	enum pipe pipe;
- 
-@@ -8347,7 +8497,7 @@ static void broadwell_init_clock_gating(
- 		   I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
- }
- 
--static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
-+static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
- {
- 	ilk_init_lp_watermarks(dev_priv);
- 
-@@ -8401,7 +8551,7 @@ static void haswell_init_clock_gating(st
- 	lpt_init_clock_gating(dev_priv);
- }
- 
--static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
-+static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
- {
- 	uint32_t snpcr;
- 
-@@ -8498,7 +8648,7 @@ static void ivybridge_init_clock_gating(
- 	gen6_check_mch_setup(dev_priv);
- }
- 
--static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
-+static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
- {
- 	/* WaDisableEarlyCull:vlv */
- 	I915_WRITE(_3D_CHICKEN3,
-@@ -8578,7 +8728,7 @@ static void valleyview_init_clock_gating
- 	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
- }
- 
--static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
-+static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
- {
- 	/* WaVSRefCountFullforceMissDisable:chv */
- 	/* WaDSRefCountFullforceMissDisable:chv */
-@@ -8638,7 +8788,7 @@ static void g4x_init_clock_gating(struct
- 	g4x_disable_trickle_feed(dev_priv);
- }
- 
--static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
-+static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
- {
- 	I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
- 	I915_WRITE(RENCLK_GATE_D2, 0);
-@@ -8652,7 +8802,7 @@ static void crestline_init_clock_gating(
- 	I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
- }
- 
--static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
-+static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
- {
- 	I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
- 		   I965_RCC_CLOCK_GATE_DISABLE |
-@@ -8737,34 +8887,38 @@ static void nop_init_clock_gating(struct
-  */
- void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
- {
--	if (IS_SKYLAKE(dev_priv))
--		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
--	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
--		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
-+	if (IS_CANNONLAKE(dev_priv))
-+		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
-+	else if (IS_COFFEELAKE(dev_priv))
-+		dev_priv->display.init_clock_gating = cfl_init_clock_gating;
-+	else if (IS_SKYLAKE(dev_priv))
-+		dev_priv->display.init_clock_gating = skl_init_clock_gating;
-+	else if (IS_KABYLAKE(dev_priv))
-+		dev_priv->display.init_clock_gating = kbl_init_clock_gating;
- 	else if (IS_BROXTON(dev_priv))
- 		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
- 	else if (IS_GEMINILAKE(dev_priv))
- 		dev_priv->display.init_clock_gating = glk_init_clock_gating;
- 	else if (IS_BROADWELL(dev_priv))
--		dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
-+		dev_priv->display.init_clock_gating = bdw_init_clock_gating;
- 	else if (IS_CHERRYVIEW(dev_priv))
--		dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
-+		dev_priv->display.init_clock_gating = chv_init_clock_gating;
- 	else if (IS_HASWELL(dev_priv))
--		dev_priv->display.init_clock_gating = haswell_init_clock_gating;
-+		dev_priv->display.init_clock_gating = hsw_init_clock_gating;
- 	else if (IS_IVYBRIDGE(dev_priv))
--		dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
-+		dev_priv->display.init_clock_gating = ivb_init_clock_gating;
- 	else if (IS_VALLEYVIEW(dev_priv))
--		dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
-+		dev_priv->display.init_clock_gating = vlv_init_clock_gating;
- 	else if (IS_GEN6(dev_priv))
- 		dev_priv->display.init_clock_gating = gen6_init_clock_gating;
- 	else if (IS_GEN5(dev_priv))
--		dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
-+		dev_priv->display.init_clock_gating = ilk_init_clock_gating;
- 	else if (IS_G4X(dev_priv))
- 		dev_priv->display.init_clock_gating = g4x_init_clock_gating;
- 	else if (IS_I965GM(dev_priv))
--		dev_priv->display.init_clock_gating = crestline_init_clock_gating;
-+		dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
- 	else if (IS_I965G(dev_priv))
--		dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
-+		dev_priv->display.init_clock_gating = i965g_init_clock_gating;
- 	else if (IS_GEN3(dev_priv))
- 		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
- 	else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
-@@ -9126,43 +9280,6 @@ int intel_freq_opcode(struct drm_i915_pr
- 		return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
- }
- 
--struct request_boost {
--	struct work_struct work;
--	struct drm_i915_gem_request *req;
--};
--
--static void __intel_rps_boost_work(struct work_struct *work)
--{
--	struct request_boost *boost = container_of(work, struct request_boost, work);
--	struct drm_i915_gem_request *req = boost->req;
--
--	if (!i915_gem_request_completed(req))
--		gen6_rps_boost(req, NULL);
--
--	i915_gem_request_put(req);
--	kfree(boost);
--}
--
--void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
--{
--	struct request_boost *boost;
--
--	if (req == NULL || INTEL_GEN(req->i915) < 6)
--		return;
--
--	if (i915_gem_request_completed(req))
--		return;
--
--	boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
--	if (boost == NULL)
--		return;
--
--	boost->req = i915_gem_request_get(req);
--
--	INIT_WORK(&boost->work, __intel_rps_boost_work);
--	queue_work(req->i915->wq, &boost->work);
--}
--
- void intel_pm_setup(struct drm_i915_private *dev_priv)
- {
- 	mutex_init(&dev_priv->rps.hw_lock);
---- linux-4.14/drivers/gpu/drm/i915/intel_psr.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_psr.c	2017-12-14 06:39:58.512903635 +0100
-@@ -103,61 +103,55 @@ static void intel_psr_write_vsc(struct i
- 	POSTING_READ(ctl_reg);
- }
- 
--static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
-+static void vlv_psr_setup_vsc(struct intel_dp *intel_dp,
-+			      const struct intel_crtc_state *crtc_state)
- {
--	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
--	struct drm_device *dev = intel_dig_port->base.base.dev;
--	struct drm_i915_private *dev_priv = to_i915(dev);
--	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
--	enum pipe pipe = to_intel_crtc(crtc)->pipe;
-+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- 	uint32_t val;
- 
- 	/* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
--	val  = I915_READ(VLV_VSCSDP(pipe));
-+	val  = I915_READ(VLV_VSCSDP(crtc->pipe));
- 	val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
- 	val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
--	I915_WRITE(VLV_VSCSDP(pipe), val);
-+	I915_WRITE(VLV_VSCSDP(crtc->pipe), val);
- }
- 
--static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
-+static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
-+			      const struct intel_crtc_state *crtc_state)
- {
--	struct edp_vsc_psr psr_vsc;
- 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
--	struct drm_device *dev = intel_dig_port->base.base.dev;
--	struct drm_i915_private *dev_priv = to_i915(dev);
-+	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
-+	struct edp_vsc_psr psr_vsc;
- 
--	/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
--	memset(&psr_vsc, 0, sizeof(psr_vsc));
--	psr_vsc.sdp_header.HB0 = 0;
--	psr_vsc.sdp_header.HB1 = 0x7;
--	if (dev_priv->psr.colorimetry_support &&
--		dev_priv->psr.y_cord_support) {
--		psr_vsc.sdp_header.HB2 = 0x5;
--		psr_vsc.sdp_header.HB3 = 0x13;
--	} else if (dev_priv->psr.y_cord_support) {
--		psr_vsc.sdp_header.HB2 = 0x4;
--		psr_vsc.sdp_header.HB3 = 0xe;
-+	if (dev_priv->psr.psr2_support) {
-+		/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
-+		memset(&psr_vsc, 0, sizeof(psr_vsc));
-+		psr_vsc.sdp_header.HB0 = 0;
-+		psr_vsc.sdp_header.HB1 = 0x7;
-+		if (dev_priv->psr.colorimetry_support &&
-+		    dev_priv->psr.y_cord_support) {
-+			psr_vsc.sdp_header.HB2 = 0x5;
-+			psr_vsc.sdp_header.HB3 = 0x13;
-+		} else if (dev_priv->psr.y_cord_support) {
-+			psr_vsc.sdp_header.HB2 = 0x4;
-+			psr_vsc.sdp_header.HB3 = 0xe;
-+		} else {
-+			psr_vsc.sdp_header.HB2 = 0x3;
-+			psr_vsc.sdp_header.HB3 = 0xc;
-+		}
- 	} else {
--		psr_vsc.sdp_header.HB2 = 0x3;
--		psr_vsc.sdp_header.HB3 = 0xc;
-+		/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
-+		memset(&psr_vsc, 0, sizeof(psr_vsc));
-+		psr_vsc.sdp_header.HB0 = 0;
-+		psr_vsc.sdp_header.HB1 = 0x7;
-+		psr_vsc.sdp_header.HB2 = 0x2;
-+		psr_vsc.sdp_header.HB3 = 0x8;
- 	}
- 
- 	intel_psr_write_vsc(intel_dp, &psr_vsc);
- }
- 
--static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
--{
--	struct edp_vsc_psr psr_vsc;
--
--	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
--	memset(&psr_vsc, 0, sizeof(psr_vsc));
--	psr_vsc.sdp_header.HB0 = 0;
--	psr_vsc.sdp_header.HB1 = 0x7;
--	psr_vsc.sdp_header.HB2 = 0x2;
--	psr_vsc.sdp_header.HB3 = 0x8;
--	intel_psr_write_vsc(intel_dp, &psr_vsc);
--}
--
- static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
- {
- 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
-@@ -233,16 +227,15 @@ static void hsw_psr_enable_sink(struct i
- 	I915_WRITE(aux_ctl_reg, aux_ctl);
- }
- 
--static void vlv_psr_enable_source(struct intel_dp *intel_dp)
-+static void vlv_psr_enable_source(struct intel_dp *intel_dp,
-+				  const struct intel_crtc_state *crtc_state)
- {
- 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
--	struct drm_device *dev = dig_port->base.base.dev;
--	struct drm_i915_private *dev_priv = to_i915(dev);
--	struct drm_crtc *crtc = dig_port->base.base.crtc;
--	enum pipe pipe = to_intel_crtc(crtc)->pipe;
-+	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
-+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- 
--	/* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
--	I915_WRITE(VLV_PSRCTL(pipe),
-+	/* Transition from PSR_state 0 (disabled) to PSR_state 1 (inactive) */
-+	I915_WRITE(VLV_PSRCTL(crtc->pipe),
- 		   VLV_EDP_PSR_MODE_SW_TIMER |
- 		   VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
- 		   VLV_EDP_PSR_ENABLE);
-@@ -256,16 +249,17 @@ static void vlv_psr_activate(struct inte
- 	struct drm_crtc *crtc = dig_port->base.base.crtc;
- 	enum pipe pipe = to_intel_crtc(crtc)->pipe;
- 
--	/* Let's do the transition from PSR_state 1 to PSR_state 2
--	 * that is PSR transition to active - static frame transmission.
--	 * Then Hardware is responsible for the transition to PSR_state 3
--	 * that is PSR active - no Remote Frame Buffer (RFB) update.
-+	/*
-+	 * Let's do the transition from PSR_state 1 (inactive) to
-+	 * PSR_state 2 (transition to active - static frame transmission).
-+	 * Then Hardware is responsible for the transition to
-+	 * PSR_state 3 (active - no Remote Frame Buffer (RFB) update).
- 	 */
- 	I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
- 		   VLV_EDP_PSR_ACTIVE_ENTRY);
- }
- 
--static void intel_enable_source_psr1(struct intel_dp *intel_dp)
-+static void hsw_activate_psr1(struct intel_dp *intel_dp)
- {
- 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- 	struct drm_device *dev = dig_port->base.base.dev;
-@@ -319,7 +313,7 @@ static void intel_enable_source_psr1(str
- 	I915_WRITE(EDP_PSR_CTL, val);
- }
- 
--static void intel_enable_source_psr2(struct intel_dp *intel_dp)
-+static void hsw_activate_psr2(struct intel_dp *intel_dp)
- {
- 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- 	struct drm_device *dev = dig_port->base.base.dev;
-@@ -333,6 +327,7 @@ static void intel_enable_source_psr2(str
- 	 */
- 	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
- 	uint32_t val;
-+	uint8_t sink_latency;
- 
- 	val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
- 
-@@ -340,8 +335,16 @@ static void intel_enable_source_psr2(str
- 	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
- 	 * good enough. */
- 	val |= EDP_PSR2_ENABLE |
--		EDP_SU_TRACK_ENABLE |
--		EDP_FRAMES_BEFORE_SU_ENTRY;
-+		EDP_SU_TRACK_ENABLE;
-+
-+	if (drm_dp_dpcd_readb(&intel_dp->aux,
-+				DP_SYNCHRONIZATION_LATENCY_IN_SINK,
-+				&sink_latency) == 1) {
-+		sink_latency &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
-+	} else {
-+		sink_latency = 0;
-+	}
-+	val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
- 
- 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
- 		val |= EDP_PSR2_TP2_TIME_2500;
-@@ -355,17 +358,22 @@ static void intel_enable_source_psr2(str
- 	I915_WRITE(EDP_PSR2_CTL, val);
- }
- 
--static void hsw_psr_enable_source(struct intel_dp *intel_dp)
-+static void hsw_psr_activate(struct intel_dp *intel_dp)
- {
- 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- 	struct drm_device *dev = dig_port->base.base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 
-+	/* On HSW+ after we enable PSR on source it will activate it
-+	 * as soon as it match configure idle_frame count. So
-+	 * we just actually enable it here on activation time.
-+	 */
-+
- 	/* psr1 and psr2 are mutually exclusive.*/
- 	if (dev_priv->psr.psr2_support)
--		intel_enable_source_psr2(intel_dp);
-+		hsw_activate_psr2(intel_dp);
- 	else
--		intel_enable_source_psr1(intel_dp);
-+		hsw_activate_psr1(intel_dp);
- }
- 
- static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
-@@ -397,7 +405,7 @@ static bool intel_psr_match_conditions(s
- 		return false;
- 	}
- 
--	if (!i915.enable_psr) {
-+	if (!i915_modparams.enable_psr) {
- 		DRM_DEBUG_KMS("PSR disable by flag\n");
- 		return false;
- 	}
-@@ -469,44 +477,69 @@ static void intel_psr_activate(struct in
- 	WARN_ON(dev_priv->psr.active);
- 	lockdep_assert_held(&dev_priv->psr.lock);
- 
--	/* Enable/Re-enable PSR on the host */
--	if (HAS_DDI(dev_priv))
--		/* On HSW+ after we enable PSR on source it will activate it
--		 * as soon as it match configure idle_frame count. So
--		 * we just actually enable it here on activation time.
--		 */
--		hsw_psr_enable_source(intel_dp);
--	else
--		vlv_psr_activate(intel_dp);
--
-+	dev_priv->psr.activate(intel_dp);
- 	dev_priv->psr.active = true;
- }
- 
-+static void hsw_psr_enable_source(struct intel_dp *intel_dp,
-+				  const struct intel_crtc_state *crtc_state)
-+{
-+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-+	struct drm_device *dev = dig_port->base.base.dev;
-+	struct drm_i915_private *dev_priv = to_i915(dev);
-+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-+	u32 chicken;
-+
-+	if (dev_priv->psr.psr2_support) {
-+		chicken = PSR2_VSC_ENABLE_PROG_HEADER;
-+		if (dev_priv->psr.y_cord_support)
-+			chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
-+		I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
-+
-+		I915_WRITE(EDP_PSR_DEBUG_CTL,
-+			   EDP_PSR_DEBUG_MASK_MEMUP |
-+			   EDP_PSR_DEBUG_MASK_HPD |
-+			   EDP_PSR_DEBUG_MASK_LPSP |
-+			   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
-+			   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
-+	} else {
-+		/*
-+		 * Per Spec: Avoid continuous PSR exit by masking MEMUP
-+		 * and HPD. also mask LPSP to avoid dependency on other
-+		 * drivers that might block runtime_pm besides
-+		 * preventing  other hw tracking issues now we can rely
-+		 * on frontbuffer tracking.
-+		 */
-+		I915_WRITE(EDP_PSR_DEBUG_CTL,
-+			   EDP_PSR_DEBUG_MASK_MEMUP |
-+			   EDP_PSR_DEBUG_MASK_HPD |
-+			   EDP_PSR_DEBUG_MASK_LPSP);
-+	}
-+}
-+
- /**
-  * intel_psr_enable - Enable PSR
-  * @intel_dp: Intel DP
-+ * @crtc_state: new CRTC state
-  *
-  * This function can only be called after the pipe is fully trained and enabled.
-  */
--void intel_psr_enable(struct intel_dp *intel_dp)
-+void intel_psr_enable(struct intel_dp *intel_dp,
-+		      const struct intel_crtc_state *crtc_state)
- {
- 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- 	struct drm_device *dev = intel_dig_port->base.base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
--	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
--	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
--	u32 chicken;
- 
--	if (!HAS_PSR(dev_priv)) {
--		DRM_DEBUG_KMS("PSR not supported on this platform\n");
-+	if (!HAS_PSR(dev_priv))
- 		return;
--	}
- 
- 	if (!is_edp_psr(intel_dp)) {
- 		DRM_DEBUG_KMS("PSR not supported by this panel\n");
- 		return;
- 	}
- 
-+	WARN_ON(dev_priv->drrs.dp);
- 	mutex_lock(&dev_priv->psr.lock);
- 	if (dev_priv->psr.enabled) {
- 		DRM_DEBUG_KMS("PSR already in use\n");
-@@ -518,104 +551,64 @@ void intel_psr_enable(struct intel_dp *i
- 
- 	dev_priv->psr.busy_frontbuffer_bits = 0;
- 
--	if (HAS_DDI(dev_priv)) {
--		if (dev_priv->psr.psr2_support) {
--			skl_psr_setup_su_vsc(intel_dp);
--			chicken = PSR2_VSC_ENABLE_PROG_HEADER;
--			if (dev_priv->psr.y_cord_support)
--				chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
--			I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
--			I915_WRITE(EDP_PSR_DEBUG_CTL,
--				   EDP_PSR_DEBUG_MASK_MEMUP |
--				   EDP_PSR_DEBUG_MASK_HPD |
--				   EDP_PSR_DEBUG_MASK_LPSP |
--				   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
--				   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
--		} else {
--			/* set up vsc header for psr1 */
--			hsw_psr_setup_vsc(intel_dp);
--			/*
--			 * Per Spec: Avoid continuous PSR exit by masking MEMUP
--			 * and HPD. also mask LPSP to avoid dependency on other
--			 * drivers that might block runtime_pm besides
--			 * preventing  other hw tracking issues now we can rely
--			 * on frontbuffer tracking.
--			 */
--			I915_WRITE(EDP_PSR_DEBUG_CTL,
--				   EDP_PSR_DEBUG_MASK_MEMUP |
--				   EDP_PSR_DEBUG_MASK_HPD |
--				   EDP_PSR_DEBUG_MASK_LPSP);
--		}
--
--		/* Enable PSR on the panel */
--		hsw_psr_enable_sink(intel_dp);
-+	dev_priv->psr.setup_vsc(intel_dp, crtc_state);
-+	dev_priv->psr.enable_sink(intel_dp);
-+	dev_priv->psr.enable_source(intel_dp, crtc_state);
-+	dev_priv->psr.enabled = intel_dp;
- 
--		if (INTEL_GEN(dev_priv) >= 9)
--			intel_psr_activate(intel_dp);
-+	if (INTEL_GEN(dev_priv) >= 9) {
-+		intel_psr_activate(intel_dp);
- 	} else {
--		vlv_psr_setup_vsc(intel_dp);
--
--		/* Enable PSR on the panel */
--		vlv_psr_enable_sink(intel_dp);
--
--		/* On HSW+ enable_source also means go to PSR entry/active
--		 * state as soon as idle_frame achieved and here would be
--		 * to soon. However on VLV enable_source just enable PSR
--		 * but let it on inactive state. So we might do this prior
--		 * to active transition, i.e. here.
-+		/*
-+		 * FIXME: Activation should happen immediately since this
-+		 * function is just called after pipe is fully trained and
-+		 * enabled.
-+		 * However on some platforms we face issues when first
-+		 * activation follows a modeset so quickly.
-+		 *     - On VLV/CHV we get bank screen on first activation
-+		 *     - On HSW/BDW we get a recoverable frozen screen until
-+		 *       next exit-activate sequence.
- 		 */
--		vlv_psr_enable_source(intel_dp);
--	}
--
--	/*
--	 * FIXME: Activation should happen immediately since this function
--	 * is just called after pipe is fully trained and enabled.
--	 * However on every platform we face issues when first activation
--	 * follows a modeset so quickly.
--	 *     - On VLV/CHV we get bank screen on first activation
--	 *     - On HSW/BDW we get a recoverable frozen screen until next
--	 *       exit-activate sequence.
--	 */
--	if (INTEL_GEN(dev_priv) < 9)
- 		schedule_delayed_work(&dev_priv->psr.work,
- 				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
-+	}
- 
--	dev_priv->psr.enabled = intel_dp;
- unlock:
- 	mutex_unlock(&dev_priv->psr.lock);
- }
- 
--static void vlv_psr_disable(struct intel_dp *intel_dp)
-+static void vlv_psr_disable(struct intel_dp *intel_dp,
-+			    const struct intel_crtc_state *old_crtc_state)
- {
- 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- 	struct drm_device *dev = intel_dig_port->base.base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
--	struct intel_crtc *intel_crtc =
--		to_intel_crtc(intel_dig_port->base.base.crtc);
-+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
- 	uint32_t val;
- 
- 	if (dev_priv->psr.active) {
--		/* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
-+		/* Put VLV PSR back to PSR_state 0 (disabled). */
- 		if (intel_wait_for_register(dev_priv,
--					    VLV_PSRSTAT(intel_crtc->pipe),
-+					    VLV_PSRSTAT(crtc->pipe),
- 					    VLV_EDP_PSR_IN_TRANS,
- 					    0,
- 					    1))
- 			WARN(1, "PSR transition took longer than expected\n");
- 
--		val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
-+		val = I915_READ(VLV_PSRCTL(crtc->pipe));
- 		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
- 		val &= ~VLV_EDP_PSR_ENABLE;
- 		val &= ~VLV_EDP_PSR_MODE_MASK;
--		I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
-+		I915_WRITE(VLV_PSRCTL(crtc->pipe), val);
- 
- 		dev_priv->psr.active = false;
- 	} else {
--		WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
-+		WARN_ON(vlv_is_psr_active_on_pipe(dev, crtc->pipe));
- 	}
- }
- 
--static void hsw_psr_disable(struct intel_dp *intel_dp)
-+static void hsw_psr_disable(struct intel_dp *intel_dp,
-+			    const struct intel_crtc_state *old_crtc_state)
- {
- 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- 	struct drm_device *dev = intel_dig_port->base.base.dev;
-@@ -664,26 +657,27 @@ static void hsw_psr_disable(struct intel
- /**
-  * intel_psr_disable - Disable PSR
-  * @intel_dp: Intel DP
-+ * @old_crtc_state: old CRTC state
-  *
-  * This function needs to be called before disabling pipe.
-  */
--void intel_psr_disable(struct intel_dp *intel_dp)
-+void intel_psr_disable(struct intel_dp *intel_dp,
-+		       const struct intel_crtc_state *old_crtc_state)
- {
- 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- 	struct drm_device *dev = intel_dig_port->base.base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 
-+	if (!HAS_PSR(dev_priv))
-+		return;
-+
- 	mutex_lock(&dev_priv->psr.lock);
- 	if (!dev_priv->psr.enabled) {
- 		mutex_unlock(&dev_priv->psr.lock);
- 		return;
- 	}
- 
--	/* Disable PSR on Source */
--	if (HAS_DDI(dev_priv))
--		hsw_psr_disable(intel_dp);
--	else
--		vlv_psr_disable(intel_dp);
-+	dev_priv->psr.disable_source(intel_dp, old_crtc_state);
- 
- 	/* Disable PSR on Sink */
- 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
-@@ -783,17 +777,20 @@ static void intel_psr_exit(struct drm_i9
- 	} else {
- 		val = I915_READ(VLV_PSRCTL(pipe));
- 
--		/* Here we do the transition from PSR_state 3 to PSR_state 5
--		 * directly once PSR State 4 that is active with single frame
--		 * update can be skipped. PSR_state 5 that is PSR exit then
--		 * Hardware is responsible to transition back to PSR_state 1
--		 * that is PSR inactive. Same state after
--		 * vlv_edp_psr_enable_source.
-+		/*
-+		 * Here we do the transition drirectly from
-+		 * PSR_state 3 (active - no Remote Frame Buffer (RFB) update) to
-+		 * PSR_state 5 (exit).
-+		 * PSR State 4 (active with single frame update) can be skipped.
-+		 * On PSR_state 5 (exit) Hardware is responsible to transition
-+		 * back to PSR_state 1 (inactive).
-+		 * Now we are at Same state after vlv_psr_enable_source.
- 		 */
- 		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
- 		I915_WRITE(VLV_PSRCTL(pipe), val);
- 
--		/* Send AUX wake up - Spec says after transitioning to PSR
-+		/*
-+		 * Send AUX wake up - Spec says after transitioning to PSR
- 		 * active we have to send AUX wake up by writing 01h in DPCD
- 		 * 600h of sink device.
- 		 * XXX: This might slow down the transition, but without this
-@@ -824,6 +821,9 @@ void intel_psr_single_frame_update(struc
- 	enum pipe pipe;
- 	u32 val;
- 
-+	if (!HAS_PSR(dev_priv))
-+		return;
-+
- 	/*
- 	 * Single frame update is already supported on BDW+ but it requires
- 	 * many W/A and it isn't really needed.
-@@ -870,6 +870,9 @@ void intel_psr_invalidate(struct drm_i91
- 	struct drm_crtc *crtc;
- 	enum pipe pipe;
- 
-+	if (!HAS_PSR(dev_priv))
-+		return;
-+
- 	mutex_lock(&dev_priv->psr.lock);
- 	if (!dev_priv->psr.enabled) {
- 		mutex_unlock(&dev_priv->psr.lock);
-@@ -907,6 +910,9 @@ void intel_psr_flush(struct drm_i915_pri
- 	struct drm_crtc *crtc;
- 	enum pipe pipe;
- 
-+	if (!HAS_PSR(dev_priv))
-+		return;
-+
- 	mutex_lock(&dev_priv->psr.lock);
- 	if (!dev_priv->psr.enabled) {
- 		mutex_unlock(&dev_priv->psr.lock);
-@@ -939,12 +945,15 @@ void intel_psr_flush(struct drm_i915_pri
-  */
- void intel_psr_init(struct drm_i915_private *dev_priv)
- {
-+	if (!HAS_PSR(dev_priv))
-+		return;
-+
- 	dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
- 		HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
- 
- 	/* Per platform default: all disabled. */
--	if (i915.enable_psr == -1)
--		i915.enable_psr = 0;
-+	if (i915_modparams.enable_psr == -1)
-+		i915_modparams.enable_psr = 0;
- 
- 	/* Set link_standby x link_off defaults */
- 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
-@@ -958,15 +967,29 @@ void intel_psr_init(struct drm_i915_priv
- 		dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
- 
- 	/* Override link_standby x link_off defaults */
--	if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) {
-+	if (i915_modparams.enable_psr == 2 && !dev_priv->psr.link_standby) {
- 		DRM_DEBUG_KMS("PSR: Forcing link standby\n");
- 		dev_priv->psr.link_standby = true;
- 	}
--	if (i915.enable_psr == 3 && dev_priv->psr.link_standby) {
-+	if (i915_modparams.enable_psr == 3 && dev_priv->psr.link_standby) {
- 		DRM_DEBUG_KMS("PSR: Forcing main link off\n");
- 		dev_priv->psr.link_standby = false;
- 	}
- 
- 	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
- 	mutex_init(&dev_priv->psr.lock);
-+
-+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-+		dev_priv->psr.enable_source = vlv_psr_enable_source;
-+		dev_priv->psr.disable_source = vlv_psr_disable;
-+		dev_priv->psr.enable_sink = vlv_psr_enable_sink;
-+		dev_priv->psr.activate = vlv_psr_activate;
-+		dev_priv->psr.setup_vsc = vlv_psr_setup_vsc;
-+	} else {
-+		dev_priv->psr.enable_source = hsw_psr_enable_source;
-+		dev_priv->psr.disable_source = hsw_psr_disable;
-+		dev_priv->psr.enable_sink = hsw_psr_enable_sink;
-+		dev_priv->psr.activate = hsw_psr_activate;
-+		dev_priv->psr.setup_vsc = hsw_psr_setup_vsc;
-+	}
- }
---- linux-4.14/drivers/gpu/drm/i915/intel_ringbuffer.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_ringbuffer.c	2017-12-14 06:39:58.512903635 +0100
-@@ -402,17 +402,18 @@ static void intel_ring_setup_status_page
- 	 */
- 	if (IS_GEN7(dev_priv)) {
- 		switch (engine->id) {
-+		/*
-+		 * No more rings exist on Gen7. Default case is only to shut up
-+		 * gcc switch check warning.
-+		 */
-+		default:
-+			GEM_BUG_ON(engine->id);
- 		case RCS:
- 			mmio = RENDER_HWS_PGA_GEN7;
- 			break;
- 		case BCS:
- 			mmio = BLT_HWS_PGA_GEN7;
- 			break;
--		/*
--		 * VCS2 actually doesn't exist on Gen7. Only shut up
--		 * gcc switch check warning
--		 */
--		case VCS2:
- 		case VCS:
- 			mmio = BSD_HWS_PGA_GEN7;
- 			break;
-@@ -427,6 +428,9 @@ static void intel_ring_setup_status_page
- 		mmio = RING_HWS_PGA(engine->mmio_base);
- 	}
- 
-+	if (INTEL_GEN(dev_priv) >= 6)
-+		I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
-+
- 	I915_WRITE(mmio, engine->status_page.ggtt_offset);
- 	POSTING_READ(mmio);
- 
-@@ -778,6 +782,24 @@ static u32 *gen6_signal(struct drm_i915_
- 	return cs;
- }
- 
-+static void cancel_requests(struct intel_engine_cs *engine)
-+{
-+	struct drm_i915_gem_request *request;
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&engine->timeline->lock, flags);
-+
-+	/* Mark all submitted requests as skipped. */
-+	list_for_each_entry(request, &engine->timeline->requests, link) {
-+		GEM_BUG_ON(!request->global_seqno);
-+		if (!i915_gem_request_completed(request))
-+			dma_fence_set_error(&request->fence, -EIO);
-+	}
-+	/* Remaining _unready_ requests will be nop'ed when submitted */
-+
-+	spin_unlock_irqrestore(&engine->timeline->lock, flags);
-+}
-+
- static void i9xx_submit_request(struct drm_i915_gem_request *request)
- {
- 	struct drm_i915_private *dev_priv = request->i915;
-@@ -1174,113 +1196,7 @@ i915_emit_bb_start(struct drm_i915_gem_r
- 	return 0;
- }
- 
--static void cleanup_phys_status_page(struct intel_engine_cs *engine)
--{
--	struct drm_i915_private *dev_priv = engine->i915;
--
--	if (!dev_priv->status_page_dmah)
--		return;
--
--	drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah);
--	engine->status_page.page_addr = NULL;
--}
--
--static void cleanup_status_page(struct intel_engine_cs *engine)
--{
--	struct i915_vma *vma;
--	struct drm_i915_gem_object *obj;
--
--	vma = fetch_and_zero(&engine->status_page.vma);
--	if (!vma)
--		return;
--
--	obj = vma->obj;
--
--	i915_vma_unpin(vma);
--	i915_vma_close(vma);
--
--	i915_gem_object_unpin_map(obj);
--	__i915_gem_object_release_unless_active(obj);
--}
--
--static int init_status_page(struct intel_engine_cs *engine)
--{
--	struct drm_i915_gem_object *obj;
--	struct i915_vma *vma;
--	unsigned int flags;
--	void *vaddr;
--	int ret;
--
--	obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
--	if (IS_ERR(obj)) {
--		DRM_ERROR("Failed to allocate status page\n");
--		return PTR_ERR(obj);
--	}
- 
--	ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
--	if (ret)
--		goto err;
--
--	vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
--	if (IS_ERR(vma)) {
--		ret = PTR_ERR(vma);
--		goto err;
--	}
--
--	flags = PIN_GLOBAL;
--	if (!HAS_LLC(engine->i915))
--		/* On g33, we cannot place HWS above 256MiB, so
--		 * restrict its pinning to the low mappable arena.
--		 * Though this restriction is not documented for
--		 * gen4, gen5, or byt, they also behave similarly
--		 * and hang if the HWS is placed at the top of the
--		 * GTT. To generalise, it appears that all !llc
--		 * platforms have issues with us placing the HWS
--		 * above the mappable region (even though we never
--		 * actualy map it).
--		 */
--		flags |= PIN_MAPPABLE;
--	ret = i915_vma_pin(vma, 0, 4096, flags);
--	if (ret)
--		goto err;
--
--	vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
--	if (IS_ERR(vaddr)) {
--		ret = PTR_ERR(vaddr);
--		goto err_unpin;
--	}
--
--	engine->status_page.vma = vma;
--	engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
--	engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE);
--
--	DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
--			 engine->name, i915_ggtt_offset(vma));
--	return 0;
--
--err_unpin:
--	i915_vma_unpin(vma);
--err:
--	i915_gem_object_put(obj);
--	return ret;
--}
--
--static int init_phys_status_page(struct intel_engine_cs *engine)
--{
--	struct drm_i915_private *dev_priv = engine->i915;
--
--	GEM_BUG_ON(engine->id != RCS);
--
--	dev_priv->status_page_dmah =
--		drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE);
--	if (!dev_priv->status_page_dmah)
--		return -ENOMEM;
--
--	engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
--	memset(engine->status_page.page_addr, 0, PAGE_SIZE);
--
--	return 0;
--}
- 
- int intel_ring_pin(struct intel_ring *ring,
- 		   struct drm_i915_private *i915,
-@@ -1567,17 +1483,10 @@ static int intel_init_ring_buffer(struct
- 	if (err)
- 		goto err;
- 
--	if (HWS_NEEDS_PHYSICAL(engine->i915))
--		err = init_phys_status_page(engine);
--	else
--		err = init_status_page(engine);
--	if (err)
--		goto err;
--
- 	ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE);
- 	if (IS_ERR(ring)) {
- 		err = PTR_ERR(ring);
--		goto err_hws;
-+		goto err;
- 	}
- 
- 	/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
-@@ -1592,11 +1501,6 @@ static int intel_init_ring_buffer(struct
- 
- err_ring:
- 	intel_ring_free(ring);
--err_hws:
--	if (HWS_NEEDS_PHYSICAL(engine->i915))
--		cleanup_phys_status_page(engine);
--	else
--		cleanup_status_page(engine);
- err:
- 	intel_engine_cleanup_common(engine);
- 	return err;
-@@ -1615,11 +1519,6 @@ void intel_engine_cleanup(struct intel_e
- 	if (engine->cleanup)
- 		engine->cleanup(engine);
- 
--	if (HWS_NEEDS_PHYSICAL(dev_priv))
--		cleanup_phys_status_page(engine);
--	else
--		cleanup_status_page(engine);
--
- 	intel_engine_cleanup_common(engine);
- 
- 	dev_priv->engine[engine->id] = NULL;
-@@ -1983,7 +1882,7 @@ static void intel_ring_init_semaphores(s
- 	struct drm_i915_gem_object *obj;
- 	int ret, i;
- 
--	if (!i915.semaphores)
-+	if (!i915_modparams.semaphores)
- 		return;
- 
- 	if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) {
-@@ -2083,7 +1982,7 @@ err_obj:
- 	i915_gem_object_put(obj);
- err:
- 	DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n");
--	i915.semaphores = 0;
-+	i915_modparams.semaphores = 0;
- }
- 
- static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
-@@ -2115,11 +2014,13 @@ static void intel_ring_init_irq(struct d
- static void i9xx_set_default_submission(struct intel_engine_cs *engine)
- {
- 	engine->submit_request = i9xx_submit_request;
-+	engine->cancel_requests = cancel_requests;
- }
- 
- static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
- {
- 	engine->submit_request = gen6_bsd_submit_request;
-+	engine->cancel_requests = cancel_requests;
- }
- 
- static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
-@@ -2138,7 +2039,7 @@ static void intel_ring_default_vfuncs(st
- 
- 	engine->emit_breadcrumb = i9xx_emit_breadcrumb;
- 	engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
--	if (i915.semaphores) {
-+	if (i915_modparams.semaphores) {
- 		int num_rings;
- 
- 		engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
-@@ -2182,7 +2083,7 @@ int intel_init_render_ring_buffer(struct
- 		engine->emit_breadcrumb = gen8_render_emit_breadcrumb;
- 		engine->emit_breadcrumb_sz = gen8_render_emit_breadcrumb_sz;
- 		engine->emit_flush = gen8_render_ring_flush;
--		if (i915.semaphores) {
-+		if (i915_modparams.semaphores) {
- 			int num_rings;
- 
- 			engine->semaphore.signal = gen8_rcs_signal;
---- linux-4.14/drivers/gpu/drm/i915/intel_ringbuffer.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_ringbuffer.h	2017-12-14 06:39:58.512903635 +0100
-@@ -185,6 +185,91 @@ struct i915_priolist {
- 	int priority;
- };
- 
-+/**
-+ * struct intel_engine_execlists - execlist submission queue and port state
-+ *
-+ * The struct intel_engine_execlists represents the combined logical state of
-+ * driver and the hardware state for execlist mode of submission.
-+ */
-+struct intel_engine_execlists {
-+	/**
-+	 * @irq_tasklet: softirq tasklet for bottom handler
-+	 */
-+	struct tasklet_struct irq_tasklet;
-+
-+	/**
-+	 * @default_priolist: priority list for I915_PRIORITY_NORMAL
-+	 */
-+	struct i915_priolist default_priolist;
-+
-+	/**
-+	 * @no_priolist: priority lists disabled
-+	 */
-+	bool no_priolist;
-+
-+	/**
-+	 * @port: execlist port states
-+	 *
-+	 * For each hardware ELSP (ExecList Submission Port) we keep
-+	 * track of the last request and the number of times we submitted
-+	 * that port to hw. We then count the number of times the hw reports
-+	 * a context completion or preemption. As only one context can
-+	 * be active on hw, we limit resubmission of context to port[0]. This
-+	 * is called Lite Restore, of the context.
-+	 */
-+	struct execlist_port {
-+		/**
-+		 * @request_count: combined request and submission count
-+		 */
-+		struct drm_i915_gem_request *request_count;
-+#define EXECLIST_COUNT_BITS 2
-+#define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
-+#define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
-+#define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
-+#define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
-+#define port_set(p, packed) ((p)->request_count = (packed))
-+#define port_isset(p) ((p)->request_count)
-+#define port_index(p, execlists) ((p) - (execlists)->port)
-+
-+		/**
-+		 * @context_id: context ID for port
-+		 */
-+		GEM_DEBUG_DECL(u32 context_id);
-+
-+#define EXECLIST_MAX_PORTS 2
-+	} port[EXECLIST_MAX_PORTS];
-+
-+	/**
-+	 * @port_mask: number of execlist ports - 1
-+	 */
-+	unsigned int port_mask;
-+
-+	/**
-+	 * @queue: queue of requests, in priority lists
-+	 */
-+	struct rb_root queue;
-+
-+	/**
-+	 * @first: leftmost level in priority @queue
-+	 */
-+	struct rb_node *first;
-+
-+	/**
-+	 * @fw_domains: forcewake domains for irq tasklet
-+	 */
-+	unsigned int fw_domains;
-+
-+	/**
-+	 * @csb_head: context status buffer head
-+	 */
-+	unsigned int csb_head;
-+
-+	/**
-+	 * @csb_use_mmio: access csb through mmio, instead of hwsp
-+	 */
-+	bool csb_use_mmio;
-+};
-+
- #define INTEL_ENGINE_CS_MAX_NAME 8
- 
- struct intel_engine_cs {
-@@ -307,6 +392,14 @@ struct intel_engine_cs {
- 	void		(*schedule)(struct drm_i915_gem_request *request,
- 				    int priority);
- 
-+	/*
-+	 * Cancel all requests on the hardware, or queued for execution.
-+	 * This should only cancel the ready requests that have been
-+	 * submitted to the engine (via the engine->submit_request callback).
-+	 * This is called when marking the device as wedged.
-+	 */
-+	void		(*cancel_requests)(struct intel_engine_cs *engine);
-+
- 	/* Some chipsets are not quite as coherent as advertised and need
- 	 * an expensive kick to force a true read of the up-to-date seqno.
- 	 * However, the up-to-date seqno is not always required and the last
-@@ -373,25 +466,7 @@ struct intel_engine_cs {
- 		u32	*(*signal)(struct drm_i915_gem_request *req, u32 *cs);
- 	} semaphore;
- 
--	/* Execlists */
--	struct tasklet_struct irq_tasklet;
--	struct i915_priolist default_priolist;
--	bool no_priolist;
--	struct execlist_port {
--		struct drm_i915_gem_request *request_count;
--#define EXECLIST_COUNT_BITS 2
--#define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
--#define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
--#define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
--#define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
--#define port_set(p, packed) ((p)->request_count = (packed))
--#define port_isset(p) ((p)->request_count)
--#define port_index(p, e) ((p) - (e)->execlist_port)
--		GEM_DEBUG_DECL(u32 context_id);
--	} execlist_port[2];
--	struct rb_root execlist_queue;
--	struct rb_node *execlist_first;
--	unsigned int fw_domains;
-+	struct intel_engine_execlists execlists;
- 
- 	/* Contexts are pinned whilst they are active on the GPU. The last
- 	 * context executed remains active whilst the GPU is idle - the
-@@ -445,6 +520,24 @@ struct intel_engine_cs {
- };
- 
- static inline unsigned int
-+execlists_num_ports(const struct intel_engine_execlists * const execlists)
-+{
-+	return execlists->port_mask + 1;
-+}
-+
-+static inline void
-+execlists_port_complete(struct intel_engine_execlists * const execlists,
-+			struct execlist_port * const port)
-+{
-+	const unsigned int m = execlists->port_mask;
-+
-+	GEM_BUG_ON(port_index(port, execlists) != 0);
-+
-+	memmove(port, port + 1, m * sizeof(struct execlist_port));
-+	memset(port + m, 0, sizeof(struct execlist_port));
-+}
-+
-+static inline unsigned int
- intel_engine_flag(const struct intel_engine_cs *engine)
- {
- 	return BIT(engine->id);
-@@ -497,6 +590,10 @@ intel_write_status_page(struct intel_eng
- #define I915_GEM_HWS_SCRATCH_INDEX	0x40
- #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
- 
-+#define I915_HWS_CSB_BUF0_INDEX		0x10
-+#define I915_HWS_CSB_WRITE_INDEX	0x1f
-+#define CNL_HWS_CSB_WRITE_INDEX		0x2f
-+
- struct intel_ring *
- intel_engine_create_ring(struct intel_engine_cs *engine, int size);
- int intel_ring_pin(struct intel_ring *ring,
-@@ -736,16 +833,6 @@ bool intel_engines_are_idle(struct drm_i
- void intel_engines_mark_idle(struct drm_i915_private *i915);
- void intel_engines_reset_default_submission(struct drm_i915_private *i915);
- 
--static inline bool
--__intel_engine_can_store_dword(unsigned int gen, unsigned int class)
--{
--	if (gen <= 2)
--		return false; /* uses physical not virtual addresses */
--
--	if (gen == 6 && class == VIDEO_DECODE_CLASS)
--		return false; /* b0rked */
--
--	return true;
--}
-+bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
- 
- #endif /* _INTEL_RINGBUFFER_H_ */
---- linux-4.14/drivers/gpu/drm/i915/intel_runtime_pm.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_runtime_pm.c	2017-12-14 06:39:58.513903636 +0100
-@@ -2413,7 +2413,7 @@ static uint32_t get_allowed_dc_mask(cons
- 		mask = 0;
- 	}
- 
--	if (!i915.disable_power_well)
-+	if (!i915_modparams.disable_power_well)
- 		max_dc = 0;
- 
- 	if (enable_dc >= 0 && enable_dc <= max_dc) {
-@@ -2471,10 +2471,11 @@ int intel_power_domains_init(struct drm_
- {
- 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
- 
--	i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
--						     i915.disable_power_well);
--	dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
--							    i915.enable_dc);
-+	i915_modparams.disable_power_well =
-+		sanitize_disable_power_well_option(dev_priv,
-+						   i915_modparams.disable_power_well);
-+	dev_priv->csr.allowed_dc_mask =
-+		get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc);
- 
- 	BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
- 
-@@ -2535,7 +2536,7 @@ void intel_power_domains_fini(struct drm
- 	intel_display_set_init_power(dev_priv, true);
- 
- 	/* Remove the refcount we took to keep power well support disabled. */
--	if (!i915.disable_power_well)
-+	if (!i915_modparams.disable_power_well)
- 		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
- 
- 	/*
-@@ -2707,30 +2708,67 @@ void bxt_display_core_uninit(struct drm_
- 	usleep_range(10, 30);		/* 10 us delay per Bspec */
- }
- 
--#define CNL_PROCMON_IDX(val) \
--	(((val) & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) >> VOLTAGE_INFO_SHIFT)
--#define NUM_CNL_PROCMON \
--	(CNL_PROCMON_IDX(VOLTAGE_INFO_MASK | PROCESS_INFO_MASK) + 1)
-+enum {
-+	PROCMON_0_85V_DOT_0,
-+	PROCMON_0_95V_DOT_0,
-+	PROCMON_0_95V_DOT_1,
-+	PROCMON_1_05V_DOT_0,
-+	PROCMON_1_05V_DOT_1,
-+};
- 
- static const struct cnl_procmon {
- 	u32 dw1, dw9, dw10;
--} cnl_procmon_values[NUM_CNL_PROCMON] = {
--	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0)] =
--		{ .dw1 = 0x00 << 16, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
--	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0)] =
--		{ .dw1 = 0x00 << 16, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
--	[CNL_PROCMON_IDX(VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1)] =
--		{ .dw1 = 0x00 << 16, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
--	[CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0)] =
--		{ .dw1 = 0x00 << 16, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
--	[CNL_PROCMON_IDX(VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1)] =
--		{ .dw1 = 0x44 << 16, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
-+} cnl_procmon_values[] = {
-+	[PROCMON_0_85V_DOT_0] =
-+		{ .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
-+	[PROCMON_0_95V_DOT_0] =
-+		{ .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, },
-+	[PROCMON_0_95V_DOT_1] =
-+		{ .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, },
-+	[PROCMON_1_05V_DOT_0] =
-+		{ .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, },
-+	[PROCMON_1_05V_DOT_1] =
-+		{ .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
- };
- 
-+static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
-+{
-+	const struct cnl_procmon *procmon;
-+	u32 val;
-+
-+	val = I915_READ(CNL_PORT_COMP_DW3);
-+	switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
-+	default:
-+		MISSING_CASE(val);
-+	case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
-+		procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
-+		break;
-+	case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
-+		procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
-+		break;
-+	case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
-+		procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
-+		break;
-+	case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
-+		procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
-+		break;
-+	case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
-+		procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
-+		break;
-+	}
-+
-+	val = I915_READ(CNL_PORT_COMP_DW1);
-+	val &= ~((0xff << 16) | 0xff);
-+	val |= procmon->dw1;
-+	I915_WRITE(CNL_PORT_COMP_DW1, val);
-+
-+	I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
-+	I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
-+}
-+
- static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
- {
- 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
--	const struct cnl_procmon *procmon;
- 	struct i915_power_well *well;
- 	u32 val;
- 
-@@ -2746,18 +2784,7 @@ static void cnl_display_core_init(struct
- 	val &= ~CNL_COMP_PWR_DOWN;
- 	I915_WRITE(CHICKEN_MISC_2, val);
- 
--	val = I915_READ(CNL_PORT_COMP_DW3);
--	procmon = &cnl_procmon_values[CNL_PROCMON_IDX(val)];
--
--	WARN_ON(procmon->dw10 == 0);
--
--	val = I915_READ(CNL_PORT_COMP_DW1);
--	val &= ~((0xff << 16) | 0xff);
--	val |= procmon->dw1;
--	I915_WRITE(CNL_PORT_COMP_DW1, val);
--
--	I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
--	I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
-+	cnl_set_procmon_ref_values(dev_priv);
- 
- 	val = I915_READ(CNL_PORT_COMP_DW0);
- 	val |= COMP_INIT;
-@@ -2787,9 +2814,6 @@ static void cnl_display_core_init(struct
- 		intel_csr_load_program(dev_priv);
- }
- 
--#undef CNL_PROCMON_IDX
--#undef NUM_CNL_PROCMON
--
- static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
- {
- 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
-@@ -2975,7 +2999,7 @@ void intel_power_domains_init_hw(struct
- 	/* For now, we need the power well to be always enabled. */
- 	intel_display_set_init_power(dev_priv, true);
- 	/* Disable power support if the user asked so. */
--	if (!i915.disable_power_well)
-+	if (!i915_modparams.disable_power_well)
- 		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
- 	intel_power_domains_sync_hw(dev_priv);
- 	power_domains->initializing = false;
-@@ -2994,7 +3018,7 @@ void intel_power_domains_suspend(struct
- 	 * Even if power well support was disabled we still want to disable
- 	 * power wells while we are system suspended.
- 	 */
--	if (!i915.disable_power_well)
-+	if (!i915_modparams.disable_power_well)
- 		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
- 
- 	if (IS_CANNONLAKE(dev_priv))
---- linux-4.14/drivers/gpu/drm/i915/intel_sdvo.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_sdvo.c	2017-12-14 06:39:58.513903636 +0100
-@@ -201,11 +201,8 @@ to_intel_sdvo_connector(struct drm_conne
- 	return container_of(connector, struct intel_sdvo_connector, base.base);
- }
- 
--static struct intel_sdvo_connector_state *
--to_intel_sdvo_connector_state(struct drm_connector_state *conn_state)
--{
--	return container_of(conn_state, struct intel_sdvo_connector_state, base.base);
--}
-+#define to_intel_sdvo_connector_state(conn_state) \
-+	container_of((conn_state), struct intel_sdvo_connector_state, base.base)
- 
- static bool
- intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
-@@ -998,7 +995,7 @@ static bool intel_sdvo_write_infoframe(s
- }
- 
- static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
--					 struct intel_crtc_state *pipe_config)
-+					 const struct intel_crtc_state *pipe_config)
- {
- 	uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
- 	union hdmi_infoframe frame;
-@@ -1032,7 +1029,7 @@ static bool intel_sdvo_set_avi_infoframe
- }
- 
- static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
--				     struct drm_connector_state *conn_state)
-+				     const struct drm_connector_state *conn_state)
- {
- 	struct intel_sdvo_tv_format format;
- 	uint32_t format_map;
-@@ -1202,9 +1199,9 @@ static bool intel_sdvo_compute_config(st
- 	} while (0)
- 
- static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
--				    struct intel_sdvo_connector_state *sdvo_state)
-+				    const struct intel_sdvo_connector_state *sdvo_state)
- {
--	struct drm_connector_state *conn_state = &sdvo_state->base.base;
-+	const struct drm_connector_state *conn_state = &sdvo_state->base.base;
- 	struct intel_sdvo_connector *intel_sdvo_conn =
- 		to_intel_sdvo_connector(conn_state->connector);
- 	uint16_t val;
-@@ -1258,14 +1255,15 @@ static void intel_sdvo_update_props(stru
- }
- 
- static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
--				  struct intel_crtc_state *crtc_state,
--				  struct drm_connector_state *conn_state)
-+				  const struct intel_crtc_state *crtc_state,
-+				  const struct drm_connector_state *conn_state)
- {
- 	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
- 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- 	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
--	struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(conn_state);
--	struct drm_display_mode *mode = &crtc_state->base.mode;
-+	const struct intel_sdvo_connector_state *sdvo_state =
-+		to_intel_sdvo_connector_state(conn_state);
-+	const struct drm_display_mode *mode = &crtc_state->base.mode;
- 	struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
- 	u32 sdvox;
- 	struct intel_sdvo_in_out_map in_out;
-@@ -1507,8 +1505,8 @@ static void intel_sdvo_get_config(struct
- }
- 
- static void intel_disable_sdvo(struct intel_encoder *encoder,
--			       struct intel_crtc_state *old_crtc_state,
--			       struct drm_connector_state *conn_state)
-+			       const struct intel_crtc_state *old_crtc_state,
-+			       const struct drm_connector_state *conn_state)
- {
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
-@@ -1552,21 +1550,21 @@ static void intel_disable_sdvo(struct in
- }
- 
- static void pch_disable_sdvo(struct intel_encoder *encoder,
--			     struct intel_crtc_state *old_crtc_state,
--			     struct drm_connector_state *old_conn_state)
-+			     const struct intel_crtc_state *old_crtc_state,
-+			     const struct drm_connector_state *old_conn_state)
- {
- }
- 
- static void pch_post_disable_sdvo(struct intel_encoder *encoder,
--				  struct intel_crtc_state *old_crtc_state,
--				  struct drm_connector_state *old_conn_state)
-+				  const struct intel_crtc_state *old_crtc_state,
-+				  const struct drm_connector_state *old_conn_state)
- {
- 	intel_disable_sdvo(encoder, old_crtc_state, old_conn_state);
- }
- 
- static void intel_enable_sdvo(struct intel_encoder *encoder,
--			      struct intel_crtc_state *pipe_config,
--			      struct drm_connector_state *conn_state)
-+			      const struct intel_crtc_state *pipe_config,
-+			      const struct drm_connector_state *conn_state)
- {
- 	struct drm_device *dev = encoder->base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
---- linux-4.14/drivers/gpu/drm/i915/intel_sprite.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_sprite.c	2017-12-14 06:39:58.513903636 +0100
-@@ -70,8 +70,7 @@ int intel_usecs_to_scanlines(const struc
- 
- /**
-  * intel_pipe_update_start() - start update of a set of display registers
-- * @crtc: the crtc of which the registers are going to be updated
-- * @start_vbl_count: vblank counter return pointer used for error checking
-+ * @new_crtc_state: the new crtc state
-  *
-  * Mark the start of an update to pipe registers that should be updated
-  * atomically regarding vblank. If the next vblank will happens within
-@@ -79,18 +78,18 @@ int intel_usecs_to_scanlines(const struc
-  *
-  * After a successful call to this function, interrupts will be disabled
-  * until a subsequent call to intel_pipe_update_end(). That is done to
-- * avoid random delays. The value written to @start_vbl_count should be
-- * supplied to intel_pipe_update_end() for error checking.
-+ * avoid random delays.
-  */
--void intel_pipe_update_start(struct intel_crtc *crtc)
-+void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
- {
-+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
- 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
--	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
-+	const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
- 	long timeout = msecs_to_jiffies_timeout(1);
- 	int scanline, min, max, vblank_start;
- 	wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
- 	bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
--		intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI);
-+		intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
- 	DEFINE_WAIT(wait);
- 
- 	vblank_start = adjusted_mode->crtc_vblank_start;
-@@ -170,15 +169,15 @@ void intel_pipe_update_start(struct inte
- 
- /**
-  * intel_pipe_update_end() - end update of a set of display registers
-- * @crtc: the crtc of which the registers were updated
-- * @start_vbl_count: start vblank counter (used for error checking)
-+ * @new_crtc_state: the new crtc state
-  *
-  * Mark the end of an update started with intel_pipe_update_start(). This
-  * re-enables interrupts and verifies the update was actually completed
-- * before a vblank using the value of @start_vbl_count.
-+ * before a vblank.
-  */
--void intel_pipe_update_end(struct intel_crtc *crtc)
-+void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
- {
-+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
- 	enum pipe pipe = crtc->pipe;
- 	int scanline_end = intel_get_crtc_scanline(crtc);
- 	u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
-@@ -191,14 +190,14 @@ void intel_pipe_update_end(struct intel_
- 	 * Would be slightly nice to just grab the vblank count and arm the
- 	 * event outside of the critical section - the spinlock might spin for a
- 	 * while ... */
--	if (crtc->base.state->event) {
-+	if (new_crtc_state->base.event) {
- 		WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
- 
- 		spin_lock(&crtc->base.dev->event_lock);
--		drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
-+		drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
- 		spin_unlock(&crtc->base.dev->event_lock);
- 
--		crtc->base.state->event = NULL;
-+		new_crtc_state->base.event = NULL;
- 	}
- 
- 	local_irq_enable();
-@@ -995,7 +994,7 @@ int intel_sprite_set_colorkey(struct drm
- 	    set->flags & I915_SET_COLORKEY_DESTINATION)
- 		return -EINVAL;
- 
--	plane = drm_plane_find(dev, set->plane_id);
-+	plane = drm_plane_find(dev, file_priv, set->plane_id);
- 	if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
- 		return -ENOENT;
- 
---- linux-4.14/drivers/gpu/drm/i915/intel_tv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_tv.c	2017-12-14 06:39:58.513903636 +0100
-@@ -814,8 +814,8 @@ intel_tv_get_hw_state(struct intel_encod
- 
- static void
- intel_enable_tv(struct intel_encoder *encoder,
--		struct intel_crtc_state *pipe_config,
--		struct drm_connector_state *conn_state)
-+		const struct intel_crtc_state *pipe_config,
-+		const struct drm_connector_state *conn_state)
- {
- 	struct drm_device *dev = encoder->base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
-@@ -829,8 +829,8 @@ intel_enable_tv(struct intel_encoder *en
- 
- static void
- intel_disable_tv(struct intel_encoder *encoder,
--		 struct intel_crtc_state *old_crtc_state,
--		 struct drm_connector_state *old_conn_state)
-+		 const struct intel_crtc_state *old_crtc_state,
-+		 const struct drm_connector_state *old_conn_state)
- {
- 	struct drm_device *dev = encoder->base.dev;
- 	struct drm_i915_private *dev_priv = to_i915(dev);
-@@ -838,7 +838,7 @@ intel_disable_tv(struct intel_encoder *e
- 	I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
- }
- 
--static const struct tv_mode *intel_tv_mode_find(struct drm_connector_state *conn_state)
-+static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state)
- {
- 	int format = conn_state->tv.mode;
- 
-@@ -976,8 +976,8 @@ static void set_color_conversion(struct
- }
- 
- static void intel_tv_pre_enable(struct intel_encoder *encoder,
--				struct intel_crtc_state *pipe_config,
--				struct drm_connector_state *conn_state)
-+				const struct intel_crtc_state *pipe_config,
-+				const struct drm_connector_state *conn_state)
- {
- 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
-@@ -1385,7 +1385,7 @@ intel_tv_get_modes(struct drm_connector
- 			mode_ptr->vsync_end = mode_ptr->vsync_start  + 1;
- 		mode_ptr->vtotal = vactive_s + 33;
- 
--		tmp = (u64) tv_mode->refresh * mode_ptr->vtotal;
-+		tmp = mul_u32_u32(tv_mode->refresh, mode_ptr->vtotal);
- 		tmp *= mode_ptr->htotal;
- 		tmp = div_u64(tmp, 1000000);
- 		mode_ptr->clock = (int) tmp;
---- linux-4.14/drivers/gpu/drm/i915/intel_uc.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_uc.c	2017-12-14 06:39:58.513903636 +0100
-@@ -63,35 +63,35 @@ static int __intel_uc_reset_hw(struct dr
- void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
- {
- 	if (!HAS_GUC(dev_priv)) {
--		if (i915.enable_guc_loading > 0 ||
--		    i915.enable_guc_submission > 0)
-+		if (i915_modparams.enable_guc_loading > 0 ||
-+		    i915_modparams.enable_guc_submission > 0)
- 			DRM_INFO("Ignoring GuC options, no hardware\n");
- 
--		i915.enable_guc_loading = 0;
--		i915.enable_guc_submission = 0;
-+		i915_modparams.enable_guc_loading = 0;
-+		i915_modparams.enable_guc_submission = 0;
- 		return;
- 	}
- 
- 	/* A negative value means "use platform default" */
--	if (i915.enable_guc_loading < 0)
--		i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
-+	if (i915_modparams.enable_guc_loading < 0)
-+		i915_modparams.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
- 
- 	/* Verify firmware version */
--	if (i915.enable_guc_loading) {
-+	if (i915_modparams.enable_guc_loading) {
- 		if (HAS_HUC_UCODE(dev_priv))
- 			intel_huc_select_fw(&dev_priv->huc);
- 
- 		if (intel_guc_select_fw(&dev_priv->guc))
--			i915.enable_guc_loading = 0;
-+			i915_modparams.enable_guc_loading = 0;
- 	}
- 
- 	/* Can't enable guc submission without guc loaded */
--	if (!i915.enable_guc_loading)
--		i915.enable_guc_submission = 0;
-+	if (!i915_modparams.enable_guc_loading)
-+		i915_modparams.enable_guc_submission = 0;
- 
- 	/* A negative value means "use platform default" */
--	if (i915.enable_guc_submission < 0)
--		i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
-+	if (i915_modparams.enable_guc_submission < 0)
-+		i915_modparams.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
- }
- 
- static void gen8_guc_raise_irq(struct intel_guc *guc)
-@@ -290,7 +290,7 @@ static void guc_init_send_regs(struct in
- 
- static void guc_capture_load_err_log(struct intel_guc *guc)
- {
--	if (!guc->log.vma || i915.guc_log_level < 0)
-+	if (!guc->log.vma || i915_modparams.guc_log_level < 0)
- 		return;
- 
- 	if (!guc->load_err_log)
-@@ -328,12 +328,33 @@ static void guc_disable_communication(st
- 	guc->send = intel_guc_send_nop;
- }
- 
-+/**
-+ * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
-+ * @guc: intel_guc structure
-+ * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
-+ *
-+ * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
-+ * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
-+ * intel_huc_auth().
-+ *
-+ * Return:	non-zero code on error
-+ */
-+int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
-+{
-+	u32 action[] = {
-+		INTEL_GUC_ACTION_AUTHENTICATE_HUC,
-+		rsa_offset
-+	};
-+
-+	return intel_guc_send(guc, action, ARRAY_SIZE(action));
-+}
-+
- int intel_uc_init_hw(struct drm_i915_private *dev_priv)
- {
- 	struct intel_guc *guc = &dev_priv->guc;
- 	int ret, attempts;
- 
--	if (!i915.enable_guc_loading)
-+	if (!i915_modparams.enable_guc_loading)
- 		return 0;
- 
- 	guc_disable_communication(guc);
-@@ -342,7 +363,7 @@ int intel_uc_init_hw(struct drm_i915_pri
- 	/* We need to notify the guc whenever we change the GGTT */
- 	i915_ggtt_enable_guc(dev_priv);
- 
--	if (i915.enable_guc_submission) {
-+	if (i915_modparams.enable_guc_submission) {
- 		/*
- 		 * This is stuff we need to have available at fw load time
- 		 * if we are planning to enable submission later
-@@ -390,9 +411,9 @@ int intel_uc_init_hw(struct drm_i915_pri
- 	if (ret)
- 		goto err_log_capture;
- 
--	intel_guc_auth_huc(dev_priv);
--	if (i915.enable_guc_submission) {
--		if (i915.guc_log_level >= 0)
-+	intel_huc_auth(&dev_priv->huc);
-+	if (i915_modparams.enable_guc_submission) {
-+		if (i915_modparams.guc_log_level >= 0)
- 			gen9_enable_guc_interrupts(dev_priv);
- 
- 		ret = i915_guc_submission_enable(dev_priv);
-@@ -417,23 +438,24 @@ err_interrupts:
- err_log_capture:
- 	guc_capture_load_err_log(guc);
- err_submission:
--	if (i915.enable_guc_submission)
-+	if (i915_modparams.enable_guc_submission)
- 		i915_guc_submission_fini(dev_priv);
- err_guc:
- 	i915_ggtt_disable_guc(dev_priv);
- 
- 	DRM_ERROR("GuC init failed\n");
--	if (i915.enable_guc_loading > 1 || i915.enable_guc_submission > 1)
-+	if (i915_modparams.enable_guc_loading > 1 ||
-+	    i915_modparams.enable_guc_submission > 1)
- 		ret = -EIO;
- 	else
- 		ret = 0;
- 
--	if (i915.enable_guc_submission) {
--		i915.enable_guc_submission = 0;
-+	if (i915_modparams.enable_guc_submission) {
-+		i915_modparams.enable_guc_submission = 0;
- 		DRM_NOTE("Falling back from GuC submission to execlist mode\n");
- 	}
- 
--	i915.enable_guc_loading = 0;
-+	i915_modparams.enable_guc_loading = 0;
- 	DRM_NOTE("GuC firmware loading disabled\n");
- 
- 	return ret;
-@@ -443,15 +465,15 @@ void intel_uc_fini_hw(struct drm_i915_pr
- {
- 	guc_free_load_err_log(&dev_priv->guc);
- 
--	if (!i915.enable_guc_loading)
-+	if (!i915_modparams.enable_guc_loading)
- 		return;
- 
--	if (i915.enable_guc_submission)
-+	if (i915_modparams.enable_guc_submission)
- 		i915_guc_submission_disable(dev_priv);
- 
- 	guc_disable_communication(&dev_priv->guc);
- 
--	if (i915.enable_guc_submission) {
-+	if (i915_modparams.enable_guc_submission) {
- 		gen9_disable_guc_interrupts(dev_priv);
- 		i915_guc_submission_fini(dev_priv);
- 	}
---- linux-4.14/drivers/gpu/drm/i915/intel_uc.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_uc.h	2017-12-14 06:39:58.513903636 +0100
-@@ -52,17 +52,6 @@ struct drm_i915_gem_request;
-  * GuC). The subsequent  pages of the client object constitute the work
-  * queue (a circular array of work items), again described in the process
-  * descriptor. Work queue pages are mapped momentarily as required.
-- *
-- * We also keep a few statistics on failures. Ideally, these should all
-- * be zero!
-- *   no_wq_space: times that the submission pre-check found no space was
-- *                available in the work queue (note, the queue is shared,
-- *                not per-engine). It is OK for this to be nonzero, but
-- *                it should not be huge!
-- *   b_fail: failed to ring the doorbell. This should never happen, unless
-- *           somehow the hardware misbehaves, or maybe if the GuC firmware
-- *           crashes? We probably need to reset the GPU to recover.
-- *   retcode: errno from last guc_submit()
-  */
- struct i915_guc_client {
- 	struct i915_vma *vma;
-@@ -77,15 +66,8 @@ struct i915_guc_client {
- 
- 	u16 doorbell_id;
- 	unsigned long doorbell_offset;
--	u32 doorbell_cookie;
- 
- 	spinlock_t wq_lock;
--	uint32_t wq_offset;
--	uint32_t wq_size;
--	uint32_t wq_tail;
--	uint32_t wq_rsvd;
--	uint32_t no_wq_space;
--
- 	/* Per-engine counts of GuC submissions */
- 	uint64_t submissions[I915_NUM_ENGINES];
- };
-@@ -229,6 +211,7 @@ void intel_uc_fini_hw(struct drm_i915_pr
- int intel_guc_sample_forcewake(struct intel_guc *guc);
- int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
- int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
-+int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
- 
- static inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
- {
-@@ -250,8 +233,6 @@ u32 intel_guc_wopcm_size(struct drm_i915
- /* i915_guc_submission.c */
- int i915_guc_submission_init(struct drm_i915_private *dev_priv);
- int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
--int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
--void i915_guc_wq_unreserve(struct drm_i915_gem_request *request);
- void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
- void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
- struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
-@@ -274,6 +255,6 @@ static inline u32 guc_ggtt_offset(struct
- /* intel_huc.c */
- void intel_huc_select_fw(struct intel_huc *huc);
- void intel_huc_init_hw(struct intel_huc *huc);
--void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
-+void intel_huc_auth(struct intel_huc *huc);
- 
- #endif
---- linux-4.14/drivers/gpu/drm/i915/intel_uncore.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_uncore.c	2017-12-14 06:39:58.514903636 +0100
-@@ -442,7 +442,8 @@ void intel_uncore_runtime_resume(struct
- 
- void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
- {
--	i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6);
-+	i915_modparams.enable_rc6 =
-+		sanitize_rc6_option(dev_priv, i915_modparams.enable_rc6);
- 
- 	/* BIOS often leaves RC6 enabled, but disable it for hw init */
- 	intel_sanitize_gt_powersave(dev_priv);
-@@ -496,6 +497,57 @@ void intel_uncore_forcewake_get(struct d
- }
- 
- /**
-+ * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
-+ * @dev_priv: i915 device instance
-+ *
-+ * This function is a wrapper around intel_uncore_forcewake_get() to acquire
-+ * the GT powerwell and in the process disable our debugging for the
-+ * duration of userspace's bypass.
-+ */
-+void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
-+{
-+	spin_lock_irq(&dev_priv->uncore.lock);
-+	if (!dev_priv->uncore.user_forcewake.count++) {
-+		intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
-+
-+		/* Save and disable mmio debugging for the user bypass */
-+		dev_priv->uncore.user_forcewake.saved_mmio_check =
-+			dev_priv->uncore.unclaimed_mmio_check;
-+		dev_priv->uncore.user_forcewake.saved_mmio_debug =
-+			i915_modparams.mmio_debug;
-+
-+		dev_priv->uncore.unclaimed_mmio_check = 0;
-+		i915_modparams.mmio_debug = 0;
-+	}
-+	spin_unlock_irq(&dev_priv->uncore.lock);
-+}
-+
-+/**
-+ * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
-+ * @dev_priv: i915 device instance
-+ *
-+ * This function complements intel_uncore_forcewake_user_get() and releases
-+ * the GT powerwell taken on behalf of the userspace bypass.
-+ */
-+void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
-+{
-+	spin_lock_irq(&dev_priv->uncore.lock);
-+	if (!--dev_priv->uncore.user_forcewake.count) {
-+		if (intel_uncore_unclaimed_mmio(dev_priv))
-+			dev_info(dev_priv->drm.dev,
-+				 "Invalid mmio detected during user access\n");
-+
-+		dev_priv->uncore.unclaimed_mmio_check =
-+			dev_priv->uncore.user_forcewake.saved_mmio_check;
-+		i915_modparams.mmio_debug =
-+			dev_priv->uncore.user_forcewake.saved_mmio_debug;
-+
-+		intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
-+	}
-+	spin_unlock_irq(&dev_priv->uncore.lock);
-+}
-+
-+/**
-  * intel_uncore_forcewake_get__locked - grab forcewake domain references
-  * @dev_priv: i915 device instance
-  * @fw_domains: forcewake domains to get reference on
-@@ -796,7 +848,8 @@ __unclaimed_reg_debug(struct drm_i915_pr
- 		 "Unclaimed %s register 0x%x\n",
- 		 read ? "read from" : "write to",
- 		 i915_mmio_reg_offset(reg)))
--		i915.mmio_debug--; /* Only report the first N failures */
-+		/* Only report the first N failures */
-+		i915_modparams.mmio_debug--;
- }
- 
- static inline void
-@@ -805,7 +858,7 @@ unclaimed_reg_debug(struct drm_i915_priv
- 		    const bool read,
- 		    const bool before)
- {
--	if (likely(!i915.mmio_debug))
-+	if (likely(!i915_modparams.mmio_debug))
- 		return;
- 
- 	__unclaimed_reg_debug(dev_priv, reg, read, before);
-@@ -1254,102 +1307,101 @@ void intel_uncore_fini(struct drm_i915_p
- 	intel_uncore_forcewake_reset(dev_priv, false);
- }
- 
--#define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
--
--static const struct register_whitelist {
--	i915_reg_t offset_ldw, offset_udw;
--	uint32_t size;
--	/* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
--	uint32_t gen_bitmask;
--} whitelist[] = {
--	{ .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
--	  .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
--	  .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
--};
-+static const struct reg_whitelist {
-+	i915_reg_t offset_ldw;
-+	i915_reg_t offset_udw;
-+	u16 gen_mask;
-+	u8 size;
-+} reg_read_whitelist[] = { {
-+	.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
-+	.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
-+	.gen_mask = INTEL_GEN_MASK(4, 10),
-+	.size = 8
-+} };
- 
- int i915_reg_read_ioctl(struct drm_device *dev,
- 			void *data, struct drm_file *file)
- {
- 	struct drm_i915_private *dev_priv = to_i915(dev);
- 	struct drm_i915_reg_read *reg = data;
--	struct register_whitelist const *entry = whitelist;
--	unsigned size;
--	i915_reg_t offset_ldw, offset_udw;
--	int i, ret = 0;
--
--	for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
--		if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
--		    (INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask))
-+	struct reg_whitelist const *entry;
-+	unsigned int flags;
-+	int remain;
-+	int ret = 0;
-+
-+	entry = reg_read_whitelist;
-+	remain = ARRAY_SIZE(reg_read_whitelist);
-+	while (remain) {
-+		u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
-+
-+		GEM_BUG_ON(!is_power_of_2(entry->size));
-+		GEM_BUG_ON(entry->size > 8);
-+		GEM_BUG_ON(entry_offset & (entry->size - 1));
-+
-+		if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&
-+		    entry_offset == (reg->offset & -entry->size))
- 			break;
-+		entry++;
-+		remain--;
- 	}
- 
--	if (i == ARRAY_SIZE(whitelist))
-+	if (!remain)
- 		return -EINVAL;
- 
--	/* We use the low bits to encode extra flags as the register should
--	 * be naturally aligned (and those that are not so aligned merely
--	 * limit the available flags for that register).
--	 */
--	offset_ldw = entry->offset_ldw;
--	offset_udw = entry->offset_udw;
--	size = entry->size;
--	size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
-+	flags = reg->offset & (entry->size - 1);
- 
- 	intel_runtime_pm_get(dev_priv);
--
--	switch (size) {
--	case 8 | 1:
--		reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
--		break;
--	case 8:
--		reg->val = I915_READ64(offset_ldw);
--		break;
--	case 4:
--		reg->val = I915_READ(offset_ldw);
--		break;
--	case 2:
--		reg->val = I915_READ16(offset_ldw);
--		break;
--	case 1:
--		reg->val = I915_READ8(offset_ldw);
--		break;
--	default:
-+	if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
-+		reg->val = I915_READ64_2x32(entry->offset_ldw,
-+					    entry->offset_udw);
-+	else if (entry->size == 8 && flags == 0)
-+		reg->val = I915_READ64(entry->offset_ldw);
-+	else if (entry->size == 4 && flags == 0)
-+		reg->val = I915_READ(entry->offset_ldw);
-+	else if (entry->size == 2 && flags == 0)
-+		reg->val = I915_READ16(entry->offset_ldw);
-+	else if (entry->size == 1 && flags == 0)
-+		reg->val = I915_READ8(entry->offset_ldw);
-+	else
- 		ret = -EINVAL;
--		goto out;
--	}
--
--out:
- 	intel_runtime_pm_put(dev_priv);
-+
- 	return ret;
- }
- 
--static void gen3_stop_rings(struct drm_i915_private *dev_priv)
-+static void gen3_stop_engine(struct intel_engine_cs *engine)
-+{
-+	struct drm_i915_private *dev_priv = engine->i915;
-+	const u32 base = engine->mmio_base;
-+	const i915_reg_t mode = RING_MI_MODE(base);
-+
-+	I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING));
-+	if (intel_wait_for_register_fw(dev_priv,
-+				       mode,
-+				       MODE_IDLE,
-+				       MODE_IDLE,
-+				       500))
-+		DRM_DEBUG_DRIVER("%s: timed out on STOP_RING\n",
-+				 engine->name);
-+
-+	I915_WRITE_FW(RING_CTL(base), 0);
-+	I915_WRITE_FW(RING_HEAD(base), 0);
-+	I915_WRITE_FW(RING_TAIL(base), 0);
-+
-+	/* Check acts as a post */
-+	if (I915_READ_FW(RING_HEAD(base)) != 0)
-+		DRM_DEBUG_DRIVER("%s: ring head not parked\n",
-+				 engine->name);
-+}
-+
-+static void i915_stop_engines(struct drm_i915_private *dev_priv,
-+			      unsigned engine_mask)
- {
- 	struct intel_engine_cs *engine;
- 	enum intel_engine_id id;
- 
--	for_each_engine(engine, dev_priv, id) {
--		const u32 base = engine->mmio_base;
--		const i915_reg_t mode = RING_MI_MODE(base);
--
--		I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING));
--		if (intel_wait_for_register_fw(dev_priv,
--					       mode,
--					       MODE_IDLE,
--					       MODE_IDLE,
--					       500))
--			DRM_DEBUG_DRIVER("%s: timed out on STOP_RING\n",
--					 engine->name);
--
--		I915_WRITE_FW(RING_CTL(base), 0);
--		I915_WRITE_FW(RING_HEAD(base), 0);
--		I915_WRITE_FW(RING_TAIL(base), 0);
--
--		/* Check acts as a post */
--		if (I915_READ_FW(RING_HEAD(base)) != 0)
--			DRM_DEBUG_DRIVER("%s: ring head not parked\n",
--					 engine->name);
--	}
-+	for_each_engine_masked(engine, dev_priv, engine_mask, id)
-+		gen3_stop_engine(engine);
- }
- 
- static bool i915_reset_complete(struct pci_dev *pdev)
-@@ -1384,9 +1436,6 @@ static int g33_do_reset(struct drm_i915_
- {
- 	struct pci_dev *pdev = dev_priv->drm.pdev;
- 
--	/* Stop engines before we reset; see g4x_do_reset() below for why. */
--	gen3_stop_rings(dev_priv);
--
- 	pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
- 	return wait_for(g4x_reset_complete(pdev), 500);
- }
-@@ -1401,12 +1450,6 @@ static int g4x_do_reset(struct drm_i915_
- 		   I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
- 	POSTING_READ(VDECCLK_GATE_D);
- 
--	/* We stop engines, otherwise we might get failed reset and a
--	 * dead gpu (on elk).
--	 * WaMediaResetMainRingCleanup:ctg,elk (presumably)
--	 */
--	gen3_stop_rings(dev_priv);
--
- 	pci_write_config_byte(pdev, I915_GDRST,
- 			      GRDOM_MEDIA | GRDOM_RESET_ENABLE);
- 	ret =  wait_for(g4x_reset_complete(pdev), 500);
-@@ -1675,7 +1718,7 @@ typedef int (*reset_func)(struct drm_i91
- 
- static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
- {
--	if (!i915.reset)
-+	if (!i915_modparams.reset)
- 		return NULL;
- 
- 	if (INTEL_INFO(dev_priv)->gen >= 8)
-@@ -1711,6 +1754,20 @@ int intel_gpu_reset(struct drm_i915_priv
- 	 */
- 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
- 	for (retry = 0; retry < 3; retry++) {
-+
-+		/* We stop engines, otherwise we might get failed reset and a
-+		 * dead gpu (on elk). Also as modern gpu as kbl can suffer
-+		 * from system hang if batchbuffer is progressing when
-+		 * the reset is issued, regardless of READY_TO_RESET ack.
-+		 * Thus assume it is best to stop engines on all gens
-+		 * where we have a gpu reset.
-+		 *
-+		 * WaMediaResetMainRingCleanup:ctg,elk (presumably)
-+		 *
-+		 * FIXME: Wa for more modern gens needs to be validated
-+		 */
-+		i915_stop_engines(dev_priv, engine_mask);
-+
- 		ret = reset(dev_priv, engine_mask);
- 		if (ret != -ETIMEDOUT)
- 			break;
-@@ -1735,7 +1792,7 @@ bool intel_has_reset_engine(struct drm_i
- {
- 	return (dev_priv->info.has_reset_engine &&
- 		!dev_priv->guc.execbuf_client &&
--		i915.reset >= 2);
-+		i915_modparams.reset >= 2);
- }
- 
- int intel_guc_reset(struct drm_i915_private *dev_priv)
-@@ -1760,7 +1817,7 @@ bool intel_uncore_unclaimed_mmio(struct
- bool
- intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
- {
--	if (unlikely(i915.mmio_debug ||
-+	if (unlikely(i915_modparams.mmio_debug ||
- 		     dev_priv->uncore.unclaimed_mmio_check <= 0))
- 		return false;
- 
-@@ -1768,7 +1825,7 @@ intel_uncore_arm_unclaimed_mmio_detectio
- 		DRM_DEBUG("Unclaimed register detected, "
- 			  "enabling oneshot unclaimed register reporting. "
- 			  "Please use i915.mmio_debug=N for more information.\n");
--		i915.mmio_debug++;
-+		i915_modparams.mmio_debug++;
- 		dev_priv->uncore.unclaimed_mmio_check--;
- 		return true;
- 	}
---- linux-4.14/drivers/gpu/drm/i915/intel_uncore.h.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_uncore.h	2017-12-14 06:39:58.514903636 +0100
-@@ -102,6 +102,13 @@ struct intel_uncore {
- 		i915_reg_t reg_ack;
- 	} fw_domain[FW_DOMAIN_ID_COUNT];
- 
-+	struct {
-+		unsigned int count;
-+
-+		int saved_mmio_check;
-+		int saved_mmio_debug;
-+	} user_forcewake;
-+
- 	int unclaimed_mmio_check;
- };
- 
-@@ -145,6 +152,9 @@ void intel_uncore_forcewake_get__locked(
- void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
- 					enum forcewake_domains domains);
- 
-+void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv);
-+void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv);
-+
- int intel_wait_for_register(struct drm_i915_private *dev_priv,
- 			    i915_reg_t reg,
- 			    u32 mask,
---- linux-4.14/drivers/gpu/drm/i915/intel_vbt_defs.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/intel_vbt_defs.h	2017-12-14 06:39:58.514903636 +0100
-@@ -149,16 +149,19 @@ struct bdb_general_features {
- 	u8 ssc_freq:1;
- 	u8 enable_lfp_on_override:1;
- 	u8 disable_ssc_ddt:1;
--	u8 rsvd7:1;
-+	u8 underscan_vga_timings:1;
- 	u8 display_clock_mode:1;
--	u8 rsvd8:1; /* finish byte */
-+	u8 vbios_hotplug_support:1;
- 
-         /* bits 3 */
- 	u8 disable_smooth_vision:1;
- 	u8 single_dvi:1;
--	u8 rsvd9:1;
-+	u8 rotate_180:1;					/* 181 */
- 	u8 fdi_rx_polarity_inverted:1;
--	u8 rsvd10:4; /* finish byte */
-+	u8 vbios_extended_mode:1;				/* 160 */
-+	u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1;			/* 160 */
-+	u8 panel_best_fit_timing:1;				/* 160 */
-+	u8 ignore_strap_state:1;				/* 160 */
- 
-         /* bits 4 */
- 	u8 legacy_monitor_detect;
-@@ -167,9 +170,10 @@ struct bdb_general_features {
- 	u8 int_crt_support:1;
- 	u8 int_tv_support:1;
- 	u8 int_efp_support:1;
--	u8 dp_ssc_enb:1;	/* PCH attached eDP supports SSC */
-+	u8 dp_ssc_enable:1;	/* PCH attached eDP supports SSC */
- 	u8 dp_ssc_freq:1;	/* SSC freq for PCH attached eDP */
--	u8 rsvd11:3; /* finish byte */
-+	u8 dp_ssc_dongle_supported:1;
-+	u8 rsvd11:2; /* finish byte */
- } __packed;
- 
- /* pre-915 */
-@@ -206,6 +210,56 @@ struct bdb_general_features {
- #define DEVICE_TYPE_LFP_LVDS_DUAL	0x5162
- #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP	0x51e2
- 
-+/* Add the device class for LFP, TV, HDMI */
-+#define DEVICE_TYPE_INT_LFP		0x1022
-+#define DEVICE_TYPE_INT_TV		0x1009
-+#define DEVICE_TYPE_HDMI		0x60D2
-+#define DEVICE_TYPE_DP			0x68C6
-+#define DEVICE_TYPE_DP_DUAL_MODE	0x60D6
-+#define DEVICE_TYPE_eDP			0x78C6
-+
-+#define DEVICE_TYPE_CLASS_EXTENSION	(1 << 15)
-+#define DEVICE_TYPE_POWER_MANAGEMENT	(1 << 14)
-+#define DEVICE_TYPE_HOTPLUG_SIGNALING	(1 << 13)
-+#define DEVICE_TYPE_INTERNAL_CONNECTOR	(1 << 12)
-+#define DEVICE_TYPE_NOT_HDMI_OUTPUT	(1 << 11)
-+#define DEVICE_TYPE_MIPI_OUTPUT		(1 << 10)
-+#define DEVICE_TYPE_COMPOSITE_OUTPUT	(1 << 9)
-+#define DEVICE_TYPE_DUAL_CHANNEL	(1 << 8)
-+#define DEVICE_TYPE_HIGH_SPEED_LINK	(1 << 6)
-+#define DEVICE_TYPE_LVDS_SINGALING	(1 << 5)
-+#define DEVICE_TYPE_TMDS_DVI_SIGNALING	(1 << 4)
-+#define DEVICE_TYPE_VIDEO_SIGNALING	(1 << 3)
-+#define DEVICE_TYPE_DISPLAYPORT_OUTPUT	(1 << 2)
-+#define DEVICE_TYPE_DIGITAL_OUTPUT	(1 << 1)
-+#define DEVICE_TYPE_ANALOG_OUTPUT	(1 << 0)
-+
-+/*
-+ * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the
-+ * system, the other bits may or may not be set for eDP outputs.
-+ */
-+#define DEVICE_TYPE_eDP_BITS \
-+	(DEVICE_TYPE_INTERNAL_CONNECTOR |	\
-+	 DEVICE_TYPE_MIPI_OUTPUT |		\
-+	 DEVICE_TYPE_COMPOSITE_OUTPUT |		\
-+	 DEVICE_TYPE_DUAL_CHANNEL |		\
-+	 DEVICE_TYPE_LVDS_SINGALING |		\
-+	 DEVICE_TYPE_TMDS_DVI_SIGNALING |	\
-+	 DEVICE_TYPE_VIDEO_SIGNALING |		\
-+	 DEVICE_TYPE_DISPLAYPORT_OUTPUT |	\
-+	 DEVICE_TYPE_ANALOG_OUTPUT)
-+
-+#define DEVICE_TYPE_DP_DUAL_MODE_BITS \
-+	(DEVICE_TYPE_INTERNAL_CONNECTOR |	\
-+	 DEVICE_TYPE_MIPI_OUTPUT |		\
-+	 DEVICE_TYPE_COMPOSITE_OUTPUT |		\
-+	 DEVICE_TYPE_LVDS_SINGALING |		\
-+	 DEVICE_TYPE_TMDS_DVI_SIGNALING |	\
-+	 DEVICE_TYPE_VIDEO_SIGNALING |		\
-+	 DEVICE_TYPE_DISPLAYPORT_OUTPUT |	\
-+	 DEVICE_TYPE_DIGITAL_OUTPUT |		\
-+	 DEVICE_TYPE_ANALOG_OUTPUT)
-+
- #define DEVICE_CFG_NONE		0x00
- #define DEVICE_CFG_12BIT_DVOB	0x01
- #define DEVICE_CFG_12BIT_DVOC	0x02
-@@ -226,77 +280,126 @@ struct bdb_general_features {
- #define DEVICE_WIRE_DVOB_MASTER 0x0d
- #define DEVICE_WIRE_DVOC_MASTER 0x0e
- 
-+/* dvo_port pre BDB 155 */
- #define DEVICE_PORT_DVOA	0x00 /* none on 845+ */
- #define DEVICE_PORT_DVOB	0x01
- #define DEVICE_PORT_DVOC	0x02
- 
-+/* dvo_port BDB 155+ */
-+#define DVO_PORT_HDMIA		0
-+#define DVO_PORT_HDMIB		1
-+#define DVO_PORT_HDMIC		2
-+#define DVO_PORT_HDMID		3
-+#define DVO_PORT_LVDS		4
-+#define DVO_PORT_TV		5
-+#define DVO_PORT_CRT		6
-+#define DVO_PORT_DPB		7
-+#define DVO_PORT_DPC		8
-+#define DVO_PORT_DPD		9
-+#define DVO_PORT_DPA		10
-+#define DVO_PORT_DPE		11				/* 193 */
-+#define DVO_PORT_HDMIE		12				/* 193 */
-+#define DVO_PORT_MIPIA		21				/* 171 */
-+#define DVO_PORT_MIPIB		22				/* 171 */
-+#define DVO_PORT_MIPIC		23				/* 171 */
-+#define DVO_PORT_MIPID		24				/* 171 */
-+
-+#define LEGACY_CHILD_DEVICE_CONFIG_SIZE		33
-+
- /*
-- * We used to keep this struct but without any version control. We should avoid
-- * using it in the future, but it should be safe to keep using it in the old
-- * code. Do not change; we rely on its size.
-+ * The child device config, aka the display device data structure, provides a
-+ * description of a port and its configuration on the platform.
-+ *
-+ * The child device config size has been increased, and fields have been added
-+ * and their meaning has changed over time. Care must be taken when accessing
-+ * basically any of the fields to ensure the correct interpretation for the BDB
-+ * version in question.
-+ *
-+ * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve
-+ * space for the full structure below, and initialize the tail not actually
-+ * present in VBT to zeros. Accessing those fields is fine, as long as the
-+ * default zero is taken into account, again according to the BDB version.
-+ *
-+ * BDB versions 155 and below are considered legacy, and version 155 seems to be
-+ * a baseline for some of the VBT documentation. When adding new fields, please
-+ * include the BDB version when the field was added, if it's above that.
-  */
--struct old_child_dev_config {
-+struct child_device_config {
- 	u16 handle;
--	u16 device_type;
--	u8  device_id[10]; /* ascii string */
--	u16 addin_offset;
--	u8  dvo_port; /* See Device_PORT_* above */
--	u8  i2c_pin;
--	u8  slave_addr;
--	u8  ddc_pin;
--	u16 edid_ptr;
--	u8  dvo_cfg; /* See DEVICE_CFG_* above */
--	u8  dvo2_port;
--	u8  i2c2_pin;
--	u8  slave2_addr;
--	u8  ddc2_pin;
--	u8  capabilities;
--	u8  dvo_wiring;/* See DEVICE_WIRE_* above */
--	u8  dvo2_wiring;
--	u16 extended_type;
--	u8  dvo_function;
--} __packed;
-+	u16 device_type; /* See DEVICE_TYPE_* above */
- 
--/* This one contains field offsets that are known to be common for all BDB
-- * versions. Notice that the meaning of the contents contents may still change,
-- * but at least the offsets are consistent. */
-+	union {
-+		u8  device_id[10]; /* ascii string */
-+		struct {
-+			u8 i2c_speed;
-+			u8 dp_onboard_redriver;			/* 158 */
-+			u8 dp_ondock_redriver;			/* 158 */
-+			u8 hdmi_level_shifter_value:4;		/* 169 */
-+			u8 hdmi_max_data_rate:4;		/* 204 */
-+			u16 dtd_buf_ptr;			/* 161 */
-+			u8 edidless_efp:1;			/* 161 */
-+			u8 compression_enable:1;		/* 198 */
-+			u8 compression_method:1;		/* 198 */
-+			u8 ganged_edp:1;			/* 202 */
-+			u8 reserved0:4;
-+			u8 compression_structure_index:4;	/* 198 */
-+			u8 reserved1:4;
-+			u8 slave_port;				/* 202 */
-+			u8 reserved2;
-+		} __packed;
-+	} __packed;
- 
--struct common_child_dev_config {
--	u16 handle;
--	u16 device_type;
--	u8 not_common1[12];
--	u8 dvo_port;
--	u8 not_common2[2];
-+	u16 addin_offset;
-+	u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */
-+	u8 i2c_pin;
-+	u8 slave_addr;
- 	u8 ddc_pin;
- 	u16 edid_ptr;
- 	u8 dvo_cfg; /* See DEVICE_CFG_* above */
--	u8 efp_routed:1;
--	u8 lane_reversal:1;
--	u8 lspcon:1;
--	u8 iboost:1;
--	u8 hpd_invert:1;
--	u8 flag_reserved:3;
--	u8 hdmi_support:1;
--	u8 dp_support:1;
--	u8 tmds_support:1;
--	u8 support_reserved:5;
--	u8 aux_channel;
--	u8 not_common3[11];
--	u8 iboost_level;
--} __packed;
- 
-+	union {
-+		struct {
-+			u8 dvo2_port;
-+			u8 i2c2_pin;
-+			u8 slave2_addr;
-+			u8 ddc2_pin;
-+		} __packed;
-+		struct {
-+			u8 efp_routed:1;			/* 158 */
-+			u8 lane_reversal:1;			/* 184 */
-+			u8 lspcon:1;				/* 192 */
-+			u8 iboost:1;				/* 196 */
-+			u8 hpd_invert:1;			/* 196 */
-+			u8 flag_reserved:3;
-+			u8 hdmi_support:1;			/* 158 */
-+			u8 dp_support:1;			/* 158 */
-+			u8 tmds_support:1;			/* 158 */
-+			u8 support_reserved:5;
-+			u8 aux_channel;
-+			u8 dongle_detect;
-+		} __packed;
-+	} __packed;
-+
-+	u8 pipe_cap:2;
-+	u8 sdvo_stall:1;					/* 158 */
-+	u8 hpd_status:2;
-+	u8 integrated_encoder:1;
-+	u8 capabilities_reserved:2;
-+	u8 dvo_wiring; /* See DEVICE_WIRE_* above */
-+
-+	union {
-+		u8 dvo2_wiring;
-+		u8 mipi_bridge_type;				/* 171 */
-+	} __packed;
- 
--/* This field changes depending on the BDB version, so the most reliable way to
-- * read it is by checking the BDB version and reading the raw pointer. */
--union child_device_config {
--	/* This one is safe to be used anywhere, but the code should still check
--	 * the BDB version. */
--	u8 raw[33];
--	/* This one should only be kept for legacy code. */
--	struct old_child_dev_config old;
--	/* This one should also be safe to use anywhere, even without version
--	 * checks. */
--	struct common_child_dev_config common;
-+	u16 extended_type;
-+	u8 dvo_function;
-+	u8 dp_usb_type_c:1;					/* 195 */
-+	u8 flags2_reserved:7;					/* 195 */
-+	u8 dp_gpio_index;					/* 195 */
-+	u16 dp_gpio_pin_num;					/* 195 */
-+	u8 dp_iboost_level:4;					/* 196 */
-+	u8 hdmi_iboost_level:4;					/* 196 */
- } __packed;
- 
- struct bdb_general_definitions {
-@@ -585,23 +688,38 @@ struct bdb_driver_features {
- #define EDP_VSWING_1_2V		3
- 
- 
--struct edp_link_params {
-+struct edp_fast_link_params {
- 	u8 rate:4;
- 	u8 lanes:4;
- 	u8 preemphasis:4;
- 	u8 vswing:4;
- } __packed;
- 
-+struct edp_pwm_delays {
-+	u16 pwm_on_to_backlight_enable;
-+	u16 backlight_disable_to_pwm_off;
-+} __packed;
-+
-+struct edp_full_link_params {
-+	u8 preemphasis:4;
-+	u8 vswing:4;
-+} __packed;
-+
- struct bdb_edp {
- 	struct edp_power_seq power_seqs[16];
- 	u32 color_depth;
--	struct edp_link_params link_params[16];
-+	struct edp_fast_link_params fast_link_params[16];
- 	u32 sdrrs_msa_timing_delay;
- 
- 	/* ith bit indicates enabled/disabled for (i+1)th panel */
--	u16 edp_s3d_feature;
--	u16 edp_t3_optimization;
--	u64 edp_vswing_preemph;		/* v173 */
-+	u16 edp_s3d_feature;					/* 162 */
-+	u16 edp_t3_optimization;				/* 165 */
-+	u64 edp_vswing_preemph;					/* 173 */
-+	u16 fast_link_training;					/* 182 */
-+	u16 dpcd_600h_write_required;				/* 185 */
-+	struct edp_pwm_delays pwm_delays[16];			/* 186 */
-+	u16 full_link_params_provided;				/* 199 */
-+	struct edp_full_link_params full_link_params[16];	/* 199 */
- } __packed;
- 
- struct psr_table {
-@@ -745,81 +863,6 @@ struct bdb_psr {
- #define   SWF14_APM_STANDBY	0x1
- #define   SWF14_APM_RESTORE	0x0
- 
--/* Add the device class for LFP, TV, HDMI */
--#define	 DEVICE_TYPE_INT_LFP	0x1022
--#define	 DEVICE_TYPE_INT_TV	0x1009
--#define	 DEVICE_TYPE_HDMI	0x60D2
--#define	 DEVICE_TYPE_DP		0x68C6
--#define	 DEVICE_TYPE_DP_DUAL_MODE	0x60D6
--#define	 DEVICE_TYPE_eDP	0x78C6
--
--#define  DEVICE_TYPE_CLASS_EXTENSION	(1 << 15)
--#define  DEVICE_TYPE_POWER_MANAGEMENT	(1 << 14)
--#define  DEVICE_TYPE_HOTPLUG_SIGNALING	(1 << 13)
--#define  DEVICE_TYPE_INTERNAL_CONNECTOR	(1 << 12)
--#define  DEVICE_TYPE_NOT_HDMI_OUTPUT	(1 << 11)
--#define  DEVICE_TYPE_MIPI_OUTPUT	(1 << 10)
--#define  DEVICE_TYPE_COMPOSITE_OUTPUT	(1 << 9)
--#define  DEVICE_TYPE_DUAL_CHANNEL	(1 << 8)
--#define  DEVICE_TYPE_HIGH_SPEED_LINK	(1 << 6)
--#define  DEVICE_TYPE_LVDS_SINGALING	(1 << 5)
--#define  DEVICE_TYPE_TMDS_DVI_SIGNALING	(1 << 4)
--#define  DEVICE_TYPE_VIDEO_SIGNALING	(1 << 3)
--#define  DEVICE_TYPE_DISPLAYPORT_OUTPUT	(1 << 2)
--#define  DEVICE_TYPE_DIGITAL_OUTPUT	(1 << 1)
--#define  DEVICE_TYPE_ANALOG_OUTPUT	(1 << 0)
--
--/*
-- * Bits we care about when checking for DEVICE_TYPE_eDP
-- * Depending on the system, the other bits may or may not
-- * be set for eDP outputs.
-- */
--#define DEVICE_TYPE_eDP_BITS \
--	(DEVICE_TYPE_INTERNAL_CONNECTOR | \
--	 DEVICE_TYPE_MIPI_OUTPUT | \
--	 DEVICE_TYPE_COMPOSITE_OUTPUT | \
--	 DEVICE_TYPE_DUAL_CHANNEL | \
--	 DEVICE_TYPE_LVDS_SINGALING | \
--	 DEVICE_TYPE_TMDS_DVI_SIGNALING | \
--	 DEVICE_TYPE_VIDEO_SIGNALING | \
--	 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
--	 DEVICE_TYPE_ANALOG_OUTPUT)
--
--#define DEVICE_TYPE_DP_DUAL_MODE_BITS \
--	(DEVICE_TYPE_INTERNAL_CONNECTOR | \
--	 DEVICE_TYPE_MIPI_OUTPUT | \
--	 DEVICE_TYPE_COMPOSITE_OUTPUT | \
--	 DEVICE_TYPE_LVDS_SINGALING | \
--	 DEVICE_TYPE_TMDS_DVI_SIGNALING | \
--	 DEVICE_TYPE_VIDEO_SIGNALING | \
--	 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
--	 DEVICE_TYPE_DIGITAL_OUTPUT | \
--	 DEVICE_TYPE_ANALOG_OUTPUT)
--
--/* define the DVO port for HDMI output type */
--#define		DVO_B		1
--#define		DVO_C		2
--#define		DVO_D		3
--
--/* Possible values for the "DVO Port" field for versions >= 155: */
--#define DVO_PORT_HDMIA	0
--#define DVO_PORT_HDMIB	1
--#define DVO_PORT_HDMIC	2
--#define DVO_PORT_HDMID	3
--#define DVO_PORT_LVDS	4
--#define DVO_PORT_TV	5
--#define DVO_PORT_CRT	6
--#define DVO_PORT_DPB	7
--#define DVO_PORT_DPC	8
--#define DVO_PORT_DPD	9
--#define DVO_PORT_DPA	10
--#define DVO_PORT_DPE	11
--#define DVO_PORT_HDMIE	12
--#define DVO_PORT_MIPIA	21
--#define DVO_PORT_MIPIB	22
--#define DVO_PORT_MIPIC	23
--#define DVO_PORT_MIPID	24
--
- /* Block 52 contains MIPI configuration block
-  * 6 * bdb_mipi_config, followed by 6 pps data block
-  * block below
---- linux-4.14/drivers/gpu/drm/i915/Kconfig.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/Kconfig	2017-12-14 06:39:58.514903636 +0100
-@@ -12,6 +12,7 @@ config DRM_I915
- 	select DRM_PANEL
- 	select DRM_MIPI_DSI
- 	select RELAY
-+	select IRQ_WORK
- 	# i915 depends on ACPI_VIDEO when ACPI is enabled
- 	# but for select to work, need to select ACPI_VIDEO's dependencies, ick
- 	select BACKLIGHT_LCD_SUPPORT if ACPI
---- linux-4.14/drivers/gpu/drm/i915/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/Makefile	2017-12-14 06:39:58.514903636 +0100
-@@ -140,7 +140,8 @@ i915-y += i915_perf.o \
- 	  i915_oa_bxt.o \
- 	  i915_oa_kblgt2.o \
- 	  i915_oa_kblgt3.o \
--	  i915_oa_glk.o
-+	  i915_oa_glk.o \
-+	  i915_oa_cflgt2.o
- 
- ifeq ($(CONFIG_DRM_I915_GVT),y)
- i915-y += intel_gvt.o
-@@ -151,5 +152,3 @@ endif
- i915-y += intel_lpe_audio.o
- 
- obj-$(CONFIG_DRM_I915) += i915.o
--
--CFLAGS_i915_trace_points.o := -I$(src)
---- linux-4.14/drivers/gpu/drm/i915/selftests/i915_gem_timeline.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/selftests/i915_gem_timeline.c	2017-12-14 06:39:58.514903636 +0100
-@@ -121,7 +121,7 @@ out:
- 
- static unsigned int random_engine(struct rnd_state *rnd)
- {
--	return ((u64)prandom_u32_state(rnd) * I915_NUM_ENGINES) >> 32;
-+	return i915_prandom_u32_max_state(I915_NUM_ENGINES, rnd);
- }
- 
- static int bench_sync(void *arg)
---- linux-4.14/drivers/gpu/drm/i915/selftests/i915_random.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/selftests/i915_random.c	2017-12-14 06:39:58.514903636 +0100
-@@ -41,11 +41,6 @@ u64 i915_prandom_u64_state(struct rnd_st
- 	return x;
- }
- 
--static inline u32 i915_prandom_u32_max_state(u32 ep_ro, struct rnd_state *state)
--{
--	return upper_32_bits((u64)prandom_u32_state(state) * ep_ro);
--}
--
- void i915_random_reorder(unsigned int *order, unsigned int count,
- 			 struct rnd_state *state)
- {
---- linux-4.14/drivers/gpu/drm/i915/selftests/i915_random.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/selftests/i915_random.h	2017-12-14 06:39:58.514903636 +0100
-@@ -43,6 +43,11 @@
- 
- u64 i915_prandom_u64_state(struct rnd_state *rnd);
- 
-+static inline u32 i915_prandom_u32_max_state(u32 ep_ro, struct rnd_state *state)
-+{
-+	return upper_32_bits(mul_u32_u32(prandom_u32_state(state), ep_ro));
-+}
-+
- unsigned int *i915_random_order(unsigned int count,
- 				struct rnd_state *state);
- void i915_random_reorder(unsigned int *order,
---- linux-4.14/drivers/gpu/drm/i915/selftests/intel_hangcheck.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/selftests/intel_hangcheck.c	2017-12-14 06:39:58.514903636 +0100
-@@ -621,7 +621,12 @@ static int igt_wait_reset(void *arg)
- 	__i915_add_request(rq, true);
- 
- 	if (!wait_for_hang(&h, rq)) {
--		pr_err("Failed to start request %x\n", rq->fence.seqno);
-+		pr_err("Failed to start request %x, at %x\n",
-+		       rq->fence.seqno, hws_seqno(&h, rq));
-+
-+		i915_reset(i915, 0);
-+		i915_gem_set_wedged(i915);
-+
- 		err = -EIO;
- 		goto out_rq;
- 	}
-@@ -708,10 +713,14 @@ static int igt_reset_queue(void *arg)
- 			__i915_add_request(rq, true);
- 
- 			if (!wait_for_hang(&h, prev)) {
--				pr_err("Failed to start request %x\n",
--				       prev->fence.seqno);
-+				pr_err("Failed to start request %x, at %x\n",
-+				       prev->fence.seqno, hws_seqno(&h, prev));
- 				i915_gem_request_put(rq);
- 				i915_gem_request_put(prev);
-+
-+				i915_reset(i915, 0);
-+				i915_gem_set_wedged(i915);
-+
- 				err = -EIO;
- 				goto fini;
- 			}
-@@ -806,7 +815,12 @@ static int igt_handle_error(void *arg)
- 	__i915_add_request(rq, true);
- 
- 	if (!wait_for_hang(&h, rq)) {
--		pr_err("Failed to start request %x\n", rq->fence.seqno);
-+		pr_err("Failed to start request %x, at %x\n",
-+		       rq->fence.seqno, hws_seqno(&h, rq));
-+
-+		i915_reset(i915, 0);
-+		i915_gem_set_wedged(i915);
-+
- 		err = -EIO;
- 		goto err_request;
- 	}
-@@ -843,8 +857,8 @@ err_unlock:
- int intel_hangcheck_live_selftests(struct drm_i915_private *i915)
- {
- 	static const struct i915_subtest tests[] = {
-+		SUBTEST(igt_global_reset), /* attempt to recover GPU first */
- 		SUBTEST(igt_hang_sanitycheck),
--		SUBTEST(igt_global_reset),
- 		SUBTEST(igt_reset_engine),
- 		SUBTEST(igt_reset_active_engines),
- 		SUBTEST(igt_wait_reset),
---- linux-4.14/drivers/gpu/drm/i915/selftests/mock_gem_device.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/i915/selftests/mock_gem_device.c	2017-12-14 06:39:58.514903636 +0100
-@@ -146,6 +146,11 @@ struct drm_i915_private *mock_gem_device
- 	dev_set_name(&pdev->dev, "mock");
- 	dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
- 
-+#if IS_ENABLED(CONFIG_IOMMU_API)
-+	/* hack to disable iommu for the fake device; force identity mapping */
-+	pdev->dev.archdata.iommu = (void *)-1;
-+#endif
-+
- 	dev_pm_domain_set(&pdev->dev, &pm_domain);
- 	pm_runtime_enable(&pdev->dev);
- 	pm_runtime_dont_use_autosuspend(&pdev->dev);
---- linux-4.14/drivers/gpu/drm/imx/imx-drm-core.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/imx/imx-drm-core.c	2017-12-14 06:39:58.514903636 +0100
-@@ -24,6 +24,7 @@
- #include <drm/drm_fb_helper.h>
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drm_fb_cma_helper.h>
- #include <drm/drm_plane_helper.h>
- #include <drm/drm_of.h>
-@@ -105,7 +106,7 @@ static int imx_drm_atomic_check(struct d
- }
- 
- static const struct drm_mode_config_funcs imx_drm_mode_config_funcs = {
--	.fb_create = drm_fb_cma_create,
-+	.fb_create = drm_gem_fb_create,
- 	.output_poll_changed = imx_drm_output_poll_changed,
- 	.atomic_check = imx_drm_atomic_check,
- 	.atomic_commit = drm_atomic_helper_commit,
---- linux-4.14/drivers/gpu/drm/imx/ipuv3-plane.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/imx/ipuv3-plane.c	2017-12-14 06:39:58.514903636 +0100
-@@ -18,6 +18,7 @@
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_fb_cma_helper.h>
- #include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drm_plane_helper.h>
- 
- #include "video/imx-ipu-v3.h"
-@@ -690,7 +691,7 @@ static void ipu_plane_atomic_update(stru
- }
- 
- static const struct drm_plane_helper_funcs ipu_plane_helper_funcs = {
--	.prepare_fb = drm_fb_cma_prepare_fb,
-+	.prepare_fb = drm_gem_fb_prepare_fb,
- 	.atomic_check = ipu_plane_atomic_check,
- 	.atomic_disable = ipu_plane_atomic_disable,
- 	.atomic_update = ipu_plane_atomic_update,
---- linux-4.14/drivers/gpu/drm/Kconfig.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/Kconfig	2017-12-14 06:39:58.515903637 +0100
-@@ -110,7 +110,7 @@ config DRM_FBDEV_OVERALLOC
- 
- config DRM_LOAD_EDID_FIRMWARE
- 	bool "Allow to specify an EDID data set instead of probing for it"
--	depends on DRM_KMS_HELPER
-+	depends on DRM
- 	help
- 	  Say Y here, if you want to use EDID data to be loaded from the
- 	  /lib/firmware directory or one of the provided built-in
-@@ -184,6 +184,7 @@ config DRM_AMDGPU
- 	select BACKLIGHT_CLASS_DEVICE
- 	select BACKLIGHT_LCD_SUPPORT
- 	select INTERVAL_TREE
-+	select CHASH
- 	help
- 	  Choose this option if you have a recent AMD Radeon graphics card.
- 
-@@ -191,6 +192,8 @@ config DRM_AMDGPU
- 
- source "drivers/gpu/drm/amd/amdgpu/Kconfig"
- 
-+source "drivers/gpu/drm/amd/lib/Kconfig"
-+
- source "drivers/gpu/drm/nouveau/Kconfig"
- 
- source "drivers/gpu/drm/i915/Kconfig"
-@@ -278,6 +281,8 @@ source "drivers/gpu/drm/tinydrm/Kconfig"
- 
- source "drivers/gpu/drm/pl111/Kconfig"
- 
-+source "drivers/gpu/drm/tve200/Kconfig"
-+
- # Keep legacy drivers last
- 
- menuconfig DRM_LEGACY
---- linux-4.14/drivers/gpu/drm/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/Makefile	2017-12-14 06:39:58.515903637 +0100
-@@ -29,6 +29,7 @@ drm-$(CONFIG_DRM_PANEL) += drm_panel.o
- drm-$(CONFIG_OF) += drm_of.o
- drm-$(CONFIG_AGP) += drm_agpsupport.o
- drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
-+drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
- 
- drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
- 		drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
-@@ -37,7 +38,6 @@ drm_kms_helper-y := drm_crtc_helper.o dr
- 		drm_scdc_helper.o drm_gem_framebuffer_helper.o
- 
- drm_kms_helper-$(CONFIG_DRM_PANEL_BRIDGE) += bridge/panel.o
--drm_kms_helper-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
- drm_kms_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fb_helper.o
- drm_kms_helper-$(CONFIG_DRM_KMS_CMA_HELPER) += drm_fb_cma_helper.o
- drm_kms_helper-$(CONFIG_DRM_DP_AUX_CHARDEV) += drm_dp_aux_dev.o
-@@ -45,14 +45,13 @@ drm_kms_helper-$(CONFIG_DRM_DP_AUX_CHARD
- obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o
- obj-$(CONFIG_DRM_DEBUG_MM_SELFTEST) += selftests/
- 
--CFLAGS_drm_trace_points.o := -I$(src)
--
- obj-$(CONFIG_DRM)	+= drm.o
- obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o
- obj-$(CONFIG_DRM_ARM)	+= arm/
- obj-$(CONFIG_DRM_TTM)	+= ttm/
- obj-$(CONFIG_DRM_TDFX)	+= tdfx/
- obj-$(CONFIG_DRM_R128)	+= r128/
-+obj-y			+= amd/lib/
- obj-$(CONFIG_HSA_AMD) += amd/amdkfd/
- obj-$(CONFIG_DRM_RADEON)+= radeon/
- obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/
-@@ -101,3 +100,4 @@ obj-$(CONFIG_DRM_ZTE)	+= zte/
- obj-$(CONFIG_DRM_MXSFB)	+= mxsfb/
- obj-$(CONFIG_DRM_TINYDRM) += tinydrm/
- obj-$(CONFIG_DRM_PL111) += pl111/
-+obj-$(CONFIG_DRM_TVE200) += tve200/
---- linux-4.14/drivers/gpu/drm/mediatek/mtk_hdmi.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/mediatek/mtk_hdmi.c	2017-12-14 06:39:58.515903637 +0100
-@@ -1696,11 +1696,7 @@ static int mtk_drm_hdmi_probe(struct pla
- 
- 	hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
- 	hdmi->bridge.of_node = pdev->dev.of_node;
--	ret = drm_bridge_add(&hdmi->bridge);
--	if (ret) {
--		dev_err(dev, "failed to add bridge, ret = %d\n", ret);
--		return ret;
--	}
-+	drm_bridge_add(&hdmi->bridge);
- 
- 	ret = mtk_hdmi_clk_enable_audio(hdmi);
- 	if (ret) {
---- linux-4.14/drivers/gpu/drm/meson/meson_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/meson/meson_drv.c	2017-12-14 06:39:58.515903637 +0100
-@@ -34,6 +34,7 @@
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_plane_helper.h>
- #include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drm_fb_cma_helper.h>
- #include <drm/drm_rect.h>
- #include <drm/drm_fb_helper.h>
-@@ -78,7 +79,7 @@ static const struct drm_mode_config_func
- 	.output_poll_changed = meson_fb_output_poll_changed,
- 	.atomic_check        = drm_atomic_helper_check,
- 	.atomic_commit       = drm_atomic_helper_commit,
--	.fb_create           = drm_fb_cma_create,
-+	.fb_create           = drm_gem_fb_create,
- };
- 
- static irqreturn_t meson_irq(int irq, void *arg)
---- linux-4.14/drivers/gpu/drm/mgag200/mgag200_mode.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/mgag200/mgag200_mode.c	2017-12-14 06:39:58.515903637 +0100
-@@ -1670,7 +1670,7 @@ static struct drm_encoder *mga_connector
- 	int enc_id = connector->encoder_ids[0];
- 	/* pick the encoder ids */
- 	if (enc_id)
--		return drm_encoder_find(connector->dev, enc_id);
-+		return drm_encoder_find(connector->dev, NULL, enc_id);
- 	return NULL;
- }
- 
---- linux-4.14/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c	2017-12-14 06:39:58.515903637 +0100
-@@ -599,7 +599,7 @@ static u32 mdp5_get_vblank_counter(struc
- 	struct drm_crtc *crtc;
- 	struct drm_encoder *encoder;
- 
--	if (pipe < 0 || pipe >= priv->num_crtcs)
-+	if (pipe >= priv->num_crtcs)
- 		return 0;
- 
- 	crtc = priv->crtcs[pipe];
---- linux-4.14/drivers/gpu/drm/mxsfb/mxsfb_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/mxsfb/mxsfb_drv.c	2017-12-14 06:39:58.515903637 +0100
-@@ -35,6 +35,7 @@
- #include <drm/drm_fb_helper.h>
- #include <drm/drm_fb_cma_helper.h>
- #include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drm_of.h>
- #include <drm/drm_panel.h>
- #include <drm/drm_simple_kms_helper.h>
-@@ -92,7 +93,7 @@ void mxsfb_disable_axi_clk(struct mxsfb_
- }
- 
- static const struct drm_mode_config_funcs mxsfb_mode_config_funcs = {
--	.fb_create		= drm_fb_cma_create,
-+	.fb_create		= drm_gem_fb_create,
- 	.atomic_check		= drm_atomic_helper_check,
- 	.atomic_commit		= drm_atomic_helper_commit,
- };
-@@ -127,7 +128,7 @@ static void mxsfb_pipe_update(struct drm
- static int mxsfb_pipe_prepare_fb(struct drm_simple_display_pipe *pipe,
- 				 struct drm_plane_state *plane_state)
- {
--	return drm_fb_cma_prepare_fb(&pipe->plane, plane_state);
-+	return drm_gem_fb_prepare_fb(&pipe->plane, plane_state);
- }
- 
- static struct drm_simple_display_pipe_funcs mxsfb_funcs = {
---- linux-4.14/drivers/gpu/drm/nouveau/nouveau_connector.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/nouveau/nouveau_connector.c	2017-12-14 06:39:58.515903637 +0100
-@@ -373,7 +373,7 @@ find_encoder(struct drm_connector *conne
- 		if (!id)
- 			break;
- 
--		enc = drm_encoder_find(dev, id);
-+		enc = drm_encoder_find(dev, NULL, id);
- 		if (!enc)
- 			continue;
- 		nv_encoder = nouveau_encoder(enc);
-@@ -441,7 +441,7 @@ nouveau_connector_ddc_detect(struct drm_
- 		if (id == 0)
- 			break;
- 
--		encoder = drm_encoder_find(dev, id);
-+		encoder = drm_encoder_find(dev, NULL, id);
- 		if (!encoder)
- 			continue;
- 		nv_encoder = nouveau_encoder(encoder);
---- linux-4.14/drivers/gpu/drm/nouveau/nouveau_gem.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/nouveau/nouveau_gem.c	2017-12-14 06:39:58.515903637 +0100
-@@ -349,7 +349,7 @@ validate_fini_no_ticket(struct validate_
- 
- 		list_del(&nvbo->entry);
- 		nvbo->reserved_by = NULL;
--		ttm_bo_unreserve_ticket(&nvbo->bo, &op->ticket);
-+		ttm_bo_unreserve(&nvbo->bo);
- 		drm_gem_object_unreference_unlocked(&nvbo->gem);
- 	}
- }
---- linux-4.14/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c	2017-12-14 06:39:58.516903638 +0100
-@@ -165,11 +165,15 @@ static bool hdmic_detect(struct omap_dss
- {
- 	struct panel_drv_data *ddata = to_panel_data(dssdev);
- 	struct omap_dss_device *in = ddata->in;
-+	bool connected;
- 
- 	if (gpio_is_valid(ddata->hpd_gpio))
--		return gpio_get_value_cansleep(ddata->hpd_gpio);
-+		connected = gpio_get_value_cansleep(ddata->hpd_gpio);
- 	else
--		return in->ops.hdmi->detect(in);
-+		connected = in->ops.hdmi->detect(in);
-+	if (!connected && in->ops.hdmi->lost_hotplug)
-+		in->ops.hdmi->lost_hotplug(in);
-+	return connected;
- }
- 
- static int hdmic_register_hpd_cb(struct omap_dss_device *dssdev,
---- linux-4.14/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c	2017-12-14 06:39:58.516903638 +0100
-@@ -51,6 +51,8 @@ static int tpd_connect(struct omap_dss_d
- 	dssdev->dst = dst;
- 
- 	gpiod_set_value_cansleep(ddata->ct_cp_hpd_gpio, 1);
-+	gpiod_set_value_cansleep(ddata->ls_oe_gpio, 1);
-+
- 	/* DC-DC converter needs at max 300us to get to 90% of 5V */
- 	udelay(300);
- 
-@@ -69,6 +71,7 @@ static void tpd_disconnect(struct omap_d
- 		return;
- 
- 	gpiod_set_value_cansleep(ddata->ct_cp_hpd_gpio, 0);
-+	gpiod_set_value_cansleep(ddata->ls_oe_gpio, 0);
- 
- 	dst->src = NULL;
- 	dssdev->dst = NULL;
-@@ -146,25 +149,22 @@ static int tpd_read_edid(struct omap_dss
- {
- 	struct panel_drv_data *ddata = to_panel_data(dssdev);
- 	struct omap_dss_device *in = ddata->in;
--	int r;
- 
- 	if (!gpiod_get_value_cansleep(ddata->hpd_gpio))
- 		return -ENODEV;
- 
--	gpiod_set_value_cansleep(ddata->ls_oe_gpio, 1);
--
--	r = in->ops.hdmi->read_edid(in, edid, len);
--
--	gpiod_set_value_cansleep(ddata->ls_oe_gpio, 0);
--
--	return r;
-+	return in->ops.hdmi->read_edid(in, edid, len);
- }
- 
- static bool tpd_detect(struct omap_dss_device *dssdev)
- {
- 	struct panel_drv_data *ddata = to_panel_data(dssdev);
-+	struct omap_dss_device *in = ddata->in;
-+	bool connected = gpiod_get_value_cansleep(ddata->hpd_gpio);
- 
--	return gpiod_get_value_cansleep(ddata->hpd_gpio);
-+	if (!connected && in->ops.hdmi->lost_hotplug)
-+		in->ops.hdmi->lost_hotplug(in);
-+	return connected;
- }
- 
- static int tpd_register_hpd_cb(struct omap_dss_device *dssdev,
---- linux-4.14/drivers/gpu/drm/omapdrm/dss/hdmi4.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/omapdrm/dss/hdmi4.c	2017-12-14 06:39:58.516903638 +0100
-@@ -36,9 +36,11 @@
- #include <linux/of.h>
- #include <linux/of_graph.h>
- #include <sound/omap-hdmi-audio.h>
-+#include <media/cec.h>
- 
- #include "omapdss.h"
- #include "hdmi4_core.h"
-+#include "hdmi4_cec.h"
- #include "dss.h"
- #include "hdmi.h"
- 
-@@ -70,7 +72,8 @@ static void hdmi_runtime_put(void)
- 
- static irqreturn_t hdmi_irq_handler(int irq, void *data)
- {
--	struct hdmi_wp_data *wp = data;
-+	struct omap_hdmi *hdmi = data;
-+	struct hdmi_wp_data *wp = &hdmi->wp;
- 	u32 irqstatus;
- 
- 	irqstatus = hdmi_wp_get_irqstatus(wp);
-@@ -95,6 +98,13 @@ static irqreturn_t hdmi_irq_handler(int
- 	} else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
- 		hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
- 	}
-+	if (irqstatus & HDMI_IRQ_CORE) {
-+		u32 intr4 = hdmi_read_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4);
-+
-+		hdmi_write_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4, intr4);
-+		if (intr4 & 8)
-+			hdmi4_cec_irq(&hdmi->core);
-+	}
- 
- 	return IRQ_HANDLED;
- }
-@@ -123,14 +133,19 @@ static int hdmi_power_on_core(struct oma
- {
- 	int r;
- 
-+	if (hdmi.core.core_pwr_cnt++)
-+		return 0;
-+
- 	r = regulator_enable(hdmi.vdda_reg);
- 	if (r)
--		return r;
-+		goto err_reg_enable;
- 
- 	r = hdmi_runtime_get();
- 	if (r)
- 		goto err_runtime_get;
- 
-+	hdmi4_core_powerdown_disable(&hdmi.core);
-+
- 	/* Make selection of HDMI in DSS */
- 	dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
- 
-@@ -140,12 +155,17 @@ static int hdmi_power_on_core(struct oma
- 
- err_runtime_get:
- 	regulator_disable(hdmi.vdda_reg);
-+err_reg_enable:
-+	hdmi.core.core_pwr_cnt--;
- 
- 	return r;
- }
- 
- static void hdmi_power_off_core(struct omap_dss_device *dssdev)
- {
-+	if (--hdmi.core.core_pwr_cnt)
-+		return;
-+
- 	hdmi.core_enabled = false;
- 
- 	hdmi_runtime_put();
-@@ -166,8 +186,8 @@ static int hdmi_power_on_full(struct oma
- 		return r;
- 
- 	/* disable and clear irqs */
--	hdmi_wp_clear_irqenable(wp, 0xffffffff);
--	hdmi_wp_set_irqstatus(wp, 0xffffffff);
-+	hdmi_wp_clear_irqenable(wp, ~HDMI_IRQ_CORE);
-+	hdmi_wp_set_irqstatus(wp, ~HDMI_IRQ_CORE);
- 
- 	vm = &hdmi.cfg.vm;
- 
-@@ -242,7 +262,7 @@ static void hdmi_power_off_full(struct o
- {
- 	enum omap_channel channel = dssdev->dispc_channel;
- 
--	hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
-+	hdmi_wp_clear_irqenable(&hdmi.wp, ~HDMI_IRQ_CORE);
- 
- 	hdmi_wp_video_stop(&hdmi.wp);
- 
-@@ -393,11 +413,11 @@ static void hdmi_display_disable(struct
- 	mutex_unlock(&hdmi.lock);
- }
- 
--static int hdmi_core_enable(struct omap_dss_device *dssdev)
-+int hdmi4_core_enable(struct omap_dss_device *dssdev)
- {
- 	int r = 0;
- 
--	DSSDBG("ENTER omapdss_hdmi_core_enable\n");
-+	DSSDBG("ENTER omapdss_hdmi4_core_enable\n");
- 
- 	mutex_lock(&hdmi.lock);
- 
-@@ -415,9 +435,9 @@ err0:
- 	return r;
- }
- 
--static void hdmi_core_disable(struct omap_dss_device *dssdev)
-+void hdmi4_core_disable(struct omap_dss_device *dssdev)
- {
--	DSSDBG("Enter omapdss_hdmi_core_disable\n");
-+	DSSDBG("Enter omapdss_hdmi4_core_disable\n");
- 
- 	mutex_lock(&hdmi.lock);
- 
-@@ -475,19 +495,28 @@ static int hdmi_read_edid(struct omap_ds
- 	need_enable = hdmi.core_enabled == false;
- 
- 	if (need_enable) {
--		r = hdmi_core_enable(dssdev);
-+		r = hdmi4_core_enable(dssdev);
- 		if (r)
- 			return r;
- 	}
- 
- 	r = read_edid(edid, len);
--
-+	if (r >= 256)
-+		hdmi4_cec_set_phys_addr(&hdmi.core,
-+					cec_get_edid_phys_addr(edid, r, NULL));
-+	else
-+		hdmi4_cec_set_phys_addr(&hdmi.core, CEC_PHYS_ADDR_INVALID);
- 	if (need_enable)
--		hdmi_core_disable(dssdev);
-+		hdmi4_core_disable(dssdev);
- 
- 	return r;
- }
- 
-+static void hdmi_lost_hotplug(struct omap_dss_device *dssdev)
-+{
-+	hdmi4_cec_set_phys_addr(&hdmi.core, CEC_PHYS_ADDR_INVALID);
-+}
-+
- static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
- 		const struct hdmi_avi_infoframe *avi)
- {
-@@ -514,6 +543,7 @@ static const struct omapdss_hdmi_ops hdm
- 	.get_timings		= hdmi_display_get_timings,
- 
- 	.read_edid		= hdmi_read_edid,
-+	.lost_hotplug		= hdmi_lost_hotplug,
- 	.set_infoframe		= hdmi_set_infoframe,
- 	.set_hdmi_mode		= hdmi_set_hdmi_mode,
- };
-@@ -715,6 +745,10 @@ static int hdmi4_bind(struct device *dev
- 	if (r)
- 		goto err;
- 
-+	r = hdmi4_cec_init(pdev, &hdmi.core, &hdmi.wp);
-+	if (r)
-+		goto err;
-+
- 	irq = platform_get_irq(pdev, 0);
- 	if (irq < 0) {
- 		DSSERR("platform_get_irq failed\n");
-@@ -724,7 +758,7 @@ static int hdmi4_bind(struct device *dev
- 
- 	r = devm_request_threaded_irq(&pdev->dev, irq,
- 			NULL, hdmi_irq_handler,
--			IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
-+			IRQF_ONESHOT, "OMAP HDMI", &hdmi);
- 	if (r) {
- 		DSSERR("HDMI IRQ request failed\n");
- 		goto err;
-@@ -759,6 +793,8 @@ static void hdmi4_unbind(struct device *
- 
- 	hdmi_uninit_output(pdev);
- 
-+	hdmi4_cec_uninit(&hdmi.core);
-+
- 	hdmi_pll_uninit(&hdmi.pll);
- 
- 	pm_runtime_disable(&pdev->dev);
---- linux-4.14/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c.0130~	2017-12-14 06:39:58.516903638 +0100
-+++ linux-4.14/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c	2017-12-14 06:39:58.516903638 +0100
-@@ -0,0 +1,381 @@
-+/*
-+ * HDMI CEC
-+ *
-+ * Based on the CEC code from hdmi_ti_4xxx_ip.c from Android.
-+ *
-+ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
-+ * Authors: Yong Zhi
-+ *	Mythri pk <mythripk@ti.com>
-+ *
-+ * Heavily modified to use the linux CEC framework:
-+ *
-+ * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
-+ *
-+ * This program is free software; you may redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
-+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-+ * SOFTWARE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+
-+#include "dss.h"
-+#include "hdmi.h"
-+#include "hdmi4_core.h"
-+#include "hdmi4_cec.h"
-+
-+/* HDMI CEC */
-+#define HDMI_CEC_DEV_ID                         0x900
-+#define HDMI_CEC_SPEC                           0x904
-+
-+/* Not really a debug register, more a low-level control register */
-+#define HDMI_CEC_DBG_3                          0x91C
-+#define HDMI_CEC_TX_INIT                        0x920
-+#define HDMI_CEC_TX_DEST                        0x924
-+#define HDMI_CEC_SETUP                          0x938
-+#define HDMI_CEC_TX_COMMAND                     0x93C
-+#define HDMI_CEC_TX_OPERAND                     0x940
-+#define HDMI_CEC_TRANSMIT_DATA                  0x97C
-+#define HDMI_CEC_CA_7_0                         0x988
-+#define HDMI_CEC_CA_15_8                        0x98C
-+#define HDMI_CEC_INT_STATUS_0                   0x998
-+#define HDMI_CEC_INT_STATUS_1                   0x99C
-+#define HDMI_CEC_INT_ENABLE_0                   0x990
-+#define HDMI_CEC_INT_ENABLE_1                   0x994
-+#define HDMI_CEC_RX_CONTROL                     0x9B0
-+#define HDMI_CEC_RX_COUNT                       0x9B4
-+#define HDMI_CEC_RX_CMD_HEADER                  0x9B8
-+#define HDMI_CEC_RX_COMMAND                     0x9BC
-+#define HDMI_CEC_RX_OPERAND                     0x9C0
-+
-+#define HDMI_CEC_TX_FIFO_INT_MASK		0x64
-+#define HDMI_CEC_RETRANSMIT_CNT_INT_MASK	0x2
-+
-+#define HDMI_CORE_CEC_RETRY    200
-+
-+static void hdmi_cec_received_msg(struct hdmi_core_data *core)
-+{
-+	u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
-+
-+	/* While there are CEC frames in the FIFO */
-+	while (cnt & 0x70) {
-+		/* and the frame doesn't have an error */
-+		if (!(cnt & 0x80)) {
-+			struct cec_msg msg = {};
-+			unsigned int i;
-+
-+			/* then read the message */
-+			msg.len = cnt & 0xf;
-+			msg.msg[0] = hdmi_read_reg(core->base,
-+						   HDMI_CEC_RX_CMD_HEADER);
-+			msg.msg[1] = hdmi_read_reg(core->base,
-+						   HDMI_CEC_RX_COMMAND);
-+			for (i = 0; i < msg.len; i++) {
-+				unsigned int reg = HDMI_CEC_RX_OPERAND + i * 4;
-+
-+				msg.msg[2 + i] =
-+					hdmi_read_reg(core->base, reg);
-+			}
-+			msg.len += 2;
-+			cec_received_msg(core->adap, &msg);
-+		}
-+		/* Clear the current frame from the FIFO */
-+		hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 1);
-+		/* Wait until the current frame is cleared */
-+		while (hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL) & 1)
-+			udelay(1);
-+		/*
-+		 * Re-read the count register and loop to see if there are
-+		 * more messages in the FIFO.
-+		 */
-+		cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
-+	}
-+}
-+
-+static void hdmi_cec_transmit_fifo_empty(struct hdmi_core_data *core, u32 stat1)
-+{
-+	if (stat1 & 2) {
-+		u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
-+
-+		cec_transmit_done(core->adap,
-+				  CEC_TX_STATUS_NACK |
-+				  CEC_TX_STATUS_MAX_RETRIES,
-+				  0, (dbg3 >> 4) & 7, 0, 0);
-+	} else if (stat1 & 1) {
-+		cec_transmit_done(core->adap,
-+				  CEC_TX_STATUS_ARB_LOST |
-+				  CEC_TX_STATUS_MAX_RETRIES,
-+				  0, 0, 0, 0);
-+	} else if (stat1 == 0) {
-+		cec_transmit_done(core->adap, CEC_TX_STATUS_OK,
-+				  0, 0, 0, 0);
-+	}
-+}
-+
-+void hdmi4_cec_irq(struct hdmi_core_data *core)
-+{
-+	u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0);
-+	u32 stat1 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
-+
-+	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, stat0);
-+	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, stat1);
-+
-+	if (stat0 & 0x40)
-+		REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
-+	else if (stat0 & 0x24)
-+		hdmi_cec_transmit_fifo_empty(core, stat1);
-+	if (stat1 & 2) {
-+		u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
-+
-+		cec_transmit_done(core->adap,
-+				  CEC_TX_STATUS_NACK |
-+				  CEC_TX_STATUS_MAX_RETRIES,
-+				  0, (dbg3 >> 4) & 7, 0, 0);
-+	} else if (stat1 & 1) {
-+		cec_transmit_done(core->adap,
-+				  CEC_TX_STATUS_ARB_LOST |
-+				  CEC_TX_STATUS_MAX_RETRIES,
-+				  0, 0, 0, 0);
-+	}
-+	if (stat0 & 0x02)
-+		hdmi_cec_received_msg(core);
-+	if (stat1 & 0x3)
-+		REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
-+}
-+
-+static bool hdmi_cec_clear_tx_fifo(struct cec_adapter *adap)
-+{
-+	struct hdmi_core_data *core = cec_get_drvdata(adap);
-+	int retry = HDMI_CORE_CEC_RETRY;
-+	int temp;
-+
-+	REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
-+	while (retry) {
-+		temp = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
-+		if (FLD_GET(temp, 7, 7) == 0)
-+			break;
-+		retry--;
-+	}
-+	return retry != 0;
-+}
-+
-+static bool hdmi_cec_clear_rx_fifo(struct cec_adapter *adap)
-+{
-+	struct hdmi_core_data *core = cec_get_drvdata(adap);
-+	int retry = HDMI_CORE_CEC_RETRY;
-+	int temp;
-+
-+	hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 0x3);
-+	retry = HDMI_CORE_CEC_RETRY;
-+	while (retry) {
-+		temp = hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL);
-+		if (FLD_GET(temp, 1, 0) == 0)
-+			break;
-+		retry--;
-+	}
-+	return retry != 0;
-+}
-+
-+static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
-+{
-+	struct hdmi_core_data *core = cec_get_drvdata(adap);
-+	int temp, err;
-+
-+	if (!enable) {
-+		hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0);
-+		hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0);
-+		REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3);
-+		hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE);
-+		hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE);
-+		hdmi4_core_disable(NULL);
-+		return 0;
-+	}
-+	err = hdmi4_core_enable(NULL);
-+	if (err)
-+		return err;
-+
-+	/* Clear TX FIFO */
-+	if (!hdmi_cec_clear_tx_fifo(adap)) {
-+		pr_err("cec-%s: could not clear TX FIFO\n", adap->name);
-+		return -EIO;
-+	}
-+
-+	/* Clear RX FIFO */
-+	if (!hdmi_cec_clear_rx_fifo(adap)) {
-+		pr_err("cec-%s: could not clear RX FIFO\n", adap->name);
-+		return -EIO;
-+	}
-+
-+	/* Clear CEC interrupts */
-+	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
-+		hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1));
-+	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
-+		hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0));
-+
-+	/* Enable HDMI core interrupts */
-+	hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE);
-+	/* Unmask CEC interrupt */
-+	REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0x1, 3, 3);
-+	/*
-+	 * Enable CEC interrupts:
-+	 * Transmit Buffer Full/Empty Change event
-+	 * Transmitter FIFO Empty event
-+	 * Receiver FIFO Not Empty event
-+	 */
-+	hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0x26);
-+	/*
-+	 * Enable CEC interrupts:
-+	 * RX FIFO Overrun Error event
-+	 * Short Pulse Detected event
-+	 * Frame Retransmit Count Exceeded event
-+	 * Start Bit Irregularity event
-+	 */
-+	hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0x0f);
-+
-+	/* cec calibration enable (self clearing) */
-+	hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x03);
-+	msleep(20);
-+	hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x04);
-+
-+	temp = hdmi_read_reg(core->base, HDMI_CEC_SETUP);
-+	if (FLD_GET(temp, 4, 4) != 0) {
-+		temp = FLD_MOD(temp, 0, 4, 4);
-+		hdmi_write_reg(core->base, HDMI_CEC_SETUP, temp);
-+
-+		/*
-+		 * If we enabled CEC in middle of a CEC message on the bus,
-+		 * we could have start bit irregularity and/or short
-+		 * pulse event. Clear them now.
-+		 */
-+		temp = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
-+		temp = FLD_MOD(0x0, 0x5, 2, 0);
-+		hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, temp);
-+	}
-+	return 0;
-+}
-+
-+static int hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
-+{
-+	struct hdmi_core_data *core = cec_get_drvdata(adap);
-+	u32 v;
-+
-+	if (log_addr == CEC_LOG_ADDR_INVALID) {
-+		hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, 0);
-+		hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, 0);
-+		return 0;
-+	}
-+	if (log_addr <= 7) {
-+		v = hdmi_read_reg(core->base, HDMI_CEC_CA_7_0);
-+		v |= 1 << log_addr;
-+		hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, v);
-+	} else {
-+		v = hdmi_read_reg(core->base, HDMI_CEC_CA_15_8);
-+		v |= 1 << (log_addr - 8);
-+		hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, v);
-+	}
-+	return 0;
-+}
-+
-+static int hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
-+				   u32 signal_free_time, struct cec_msg *msg)
-+{
-+	struct hdmi_core_data *core = cec_get_drvdata(adap);
-+	int temp;
-+	u32 i;
-+
-+	/* Clear TX FIFO */
-+	if (!hdmi_cec_clear_tx_fifo(adap)) {
-+		pr_err("cec-%s: could not clear TX FIFO for transmit\n",
-+		       adap->name);
-+		return -EIO;
-+	}
-+
-+	/* Clear TX interrupts */
-+	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
-+		       HDMI_CEC_TX_FIFO_INT_MASK);
-+
-+	hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
-+		       HDMI_CEC_RETRANSMIT_CNT_INT_MASK);
-+
-+	/* Set the retry count */
-+	REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4);
-+
-+	/* Set the initiator addresses */
-+	hdmi_write_reg(core->base, HDMI_CEC_TX_INIT, cec_msg_initiator(msg));
-+
-+	/* Set destination id */
-+	temp = cec_msg_destination(msg);
-+	if (msg->len == 1)
-+		temp |= 0x80;
-+	hdmi_write_reg(core->base, HDMI_CEC_TX_DEST, temp);
-+	if (msg->len == 1)
-+		return 0;
-+
-+	/* Setup command and arguments for the command */
-+	hdmi_write_reg(core->base, HDMI_CEC_TX_COMMAND, msg->msg[1]);
-+
-+	for (i = 0; i < msg->len - 2; i++)
-+		hdmi_write_reg(core->base, HDMI_CEC_TX_OPERAND + i * 4,
-+			       msg->msg[2 + i]);
-+
-+	/* Operand count */
-+	hdmi_write_reg(core->base, HDMI_CEC_TRANSMIT_DATA,
-+		       (msg->len - 2) | 0x10);
-+	return 0;
-+}
-+
-+static const struct cec_adap_ops hdmi_cec_adap_ops = {
-+	.adap_enable = hdmi_cec_adap_enable,
-+	.adap_log_addr = hdmi_cec_adap_log_addr,
-+	.adap_transmit = hdmi_cec_adap_transmit,
-+};
-+
-+void hdmi4_cec_set_phys_addr(struct hdmi_core_data *core, u16 pa)
-+{
-+	cec_s_phys_addr(core->adap, pa, false);
-+}
-+
-+int hdmi4_cec_init(struct platform_device *pdev, struct hdmi_core_data *core,
-+		  struct hdmi_wp_data *wp)
-+{
-+	const u32 caps = CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
-+			 CEC_CAP_PASSTHROUGH | CEC_CAP_RC;
-+	unsigned int ret;
-+
-+	core->adap = cec_allocate_adapter(&hdmi_cec_adap_ops, core,
-+		"omap4", caps, CEC_MAX_LOG_ADDRS);
-+	ret = PTR_ERR_OR_ZERO(core->adap);
-+	if (ret < 0)
-+		return ret;
-+	core->wp = wp;
-+
-+	/*
-+	 * Initialize CEC clock divider: CEC needs 2MHz clock hence
-+	 * set the devider to 24 to get 48/24=2MHz clock
-+	 */
-+	REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0);
-+
-+	ret = cec_register_adapter(core->adap, &pdev->dev);
-+	if (ret < 0) {
-+		cec_delete_adapter(core->adap);
-+		return ret;
-+	}
-+	return 0;
-+}
-+
-+void hdmi4_cec_uninit(struct hdmi_core_data *core)
-+{
-+	cec_unregister_adapter(core->adap);
-+}
---- linux-4.14/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.h.0130~	2017-12-14 06:39:58.516903638 +0100
-+++ linux-4.14/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.h	2017-12-14 06:39:58.516903638 +0100
-@@ -0,0 +1,55 @@
-+/*
-+ * HDMI header definition for OMAP4 HDMI CEC IP
-+ *
-+ * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
-+ *
-+ * This program is free software; you may redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
-+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-+ * SOFTWARE.
-+ */
-+
-+#ifndef _HDMI4_CEC_H_
-+#define _HDMI4_CEC_H_
-+
-+struct hdmi_core_data;
-+struct hdmi_wp_data;
-+struct platform_device;
-+
-+/* HDMI CEC funcs */
-+#ifdef CONFIG_OMAP4_DSS_HDMI_CEC
-+void hdmi4_cec_set_phys_addr(struct hdmi_core_data *core, u16 pa);
-+void hdmi4_cec_irq(struct hdmi_core_data *core);
-+int hdmi4_cec_init(struct platform_device *pdev, struct hdmi_core_data *core,
-+		  struct hdmi_wp_data *wp);
-+void hdmi4_cec_uninit(struct hdmi_core_data *core);
-+#else
-+static inline void hdmi4_cec_set_phys_addr(struct hdmi_core_data *core, u16 pa)
-+{
-+}
-+
-+static inline void hdmi4_cec_irq(struct hdmi_core_data *core)
-+{
-+}
-+
-+static inline int hdmi4_cec_init(struct platform_device *pdev,
-+				struct hdmi_core_data *core,
-+				struct hdmi_wp_data *wp)
-+{
-+	return 0;
-+}
-+
-+static inline void hdmi4_cec_uninit(struct hdmi_core_data *core)
-+{
-+}
-+#endif
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c	2017-12-14 06:39:58.516903638 +0100
-@@ -208,9 +208,9 @@ static void hdmi_core_init(struct hdmi_c
- 	video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
- }
- 
--static void hdmi_core_powerdown_disable(struct hdmi_core_data *core)
-+void hdmi4_core_powerdown_disable(struct hdmi_core_data *core)
- {
--	DSSDBG("Enter hdmi_core_powerdown_disable\n");
-+	DSSDBG("Enter hdmi4_core_powerdown_disable\n");
- 	REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x1, 0, 0);
- }
- 
-@@ -335,9 +335,6 @@ void hdmi4_configure(struct hdmi_core_da
- 	 */
- 	hdmi_core_swreset_assert(core);
- 
--	/* power down off */
--	hdmi_core_powerdown_disable(core);
--
- 	v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
- 	v_core_cfg.hdmi_dvi = cfg->hdmi_dvi_mode;
- 
---- linux-4.14/drivers/gpu/drm/omapdrm/dss/hdmi4_core.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/omapdrm/dss/hdmi4_core.h	2017-12-14 06:39:58.516903638 +0100
-@@ -266,6 +266,10 @@ void hdmi4_configure(struct hdmi_core_da
- void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s);
- int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core);
- 
-+int hdmi4_core_enable(struct omap_dss_device *dssdev);
-+void hdmi4_core_disable(struct omap_dss_device *dssdev);
-+void hdmi4_core_powerdown_disable(struct hdmi_core_data *core);
-+
- int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
- void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
- int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
---- linux-4.14/drivers/gpu/drm/omapdrm/dss/hdmi.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/omapdrm/dss/hdmi.h	2017-12-14 06:39:58.516903638 +0100
-@@ -24,6 +24,7 @@
- #include <linux/platform_device.h>
- #include <linux/hdmi.h>
- #include <sound/omap-hdmi-audio.h>
-+#include <media/cec.h>
- 
- #include "omapdss.h"
- #include "dss.h"
-@@ -264,6 +265,10 @@ struct hdmi_core_data {
- 	void __iomem *base;
- 	bool cts_swmode;
- 	bool audio_use_mclk;
-+
-+	struct hdmi_wp_data *wp;
-+	unsigned int core_pwr_cnt;
-+	struct cec_adapter *adap;
- };
- 
- static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
-@@ -373,7 +378,7 @@ struct omap_hdmi {
- 	bool audio_configured;
- 	struct omap_dss_audio audio_config;
- 
--	/* This lock should be taken when booleans bellow are touched. */
-+	/* This lock should be taken when booleans below are touched. */
- 	spinlock_t audio_playing_lock;
- 	bool audio_playing;
- 	bool display_enabled;
---- linux-4.14/drivers/gpu/drm/omapdrm/dss/Kconfig.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/omapdrm/dss/Kconfig	2017-12-14 06:39:58.516903638 +0100
-@@ -65,6 +65,14 @@ config OMAP4_DSS_HDMI
- 	help
- 	  HDMI support for OMAP4 based SoCs.
- 
-+config OMAP4_DSS_HDMI_CEC
-+	bool "Enable HDMI CEC support for OMAP4"
-+	depends on OMAP4_DSS_HDMI
-+	select CEC_CORE
-+	default y
-+	---help---
-+	  When selected the HDMI transmitter will support the CEC feature.
-+
- config OMAP5_DSS_HDMI
- 	bool "HDMI support for OMAP5"
- 	default n
---- linux-4.14/drivers/gpu/drm/omapdrm/dss/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/omapdrm/dss/Makefile	2017-12-14 06:39:58.516903638 +0100
-@@ -15,5 +15,6 @@ omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
- omapdss-$(CONFIG_OMAP2_DSS_HDMI_COMMON) += hdmi_common.o hdmi_wp.o hdmi_pll.o \
- 	hdmi_phy.o
- omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi4.o hdmi4_core.o
-+omapdss-$(CONFIG_OMAP4_DSS_HDMI_CEC) += hdmi4_cec.o
- omapdss-$(CONFIG_OMAP5_DSS_HDMI) += hdmi5.o hdmi5_core.o
- ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG
---- linux-4.14/drivers/gpu/drm/omapdrm/dss/omapdss.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/omapdrm/dss/omapdss.h	2017-12-14 06:39:58.516903638 +0100
-@@ -395,6 +395,7 @@ struct omapdss_hdmi_ops {
- 			    struct videomode *vm);
- 
- 	int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
-+	void (*lost_hotplug)(struct omap_dss_device *dssdev);
- 	bool (*detect)(struct omap_dss_device *dssdev);
- 
- 	int (*register_hpd_cb)(struct omap_dss_device *dssdev,
---- linux-4.14/drivers/gpu/drm/panel/Kconfig.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/panel/Kconfig	2017-12-14 06:39:58.516903638 +0100
-@@ -63,6 +63,15 @@ config DRM_PANEL_LG_LG4573
- 	  Say Y here if you want to enable support for LG4573 RGB panel.
- 	  To compile this driver as a module, choose M here.
- 
-+config DRM_PANEL_ORISETECH_OTM8009A
-+	tristate "Orise Technology otm8009a 480x800 dsi 2dl panel"
-+	depends on OF
-+	depends on DRM_MIPI_DSI
-+	depends on BACKLIGHT_CLASS_DEVICE
-+	help
-+	  Say Y here if you want to enable support for Orise Technology
-+	  otm8009a 480x800 dsi 2dl panel.
-+
- config DRM_PANEL_PANASONIC_VVX10F034N00
- 	tristate "Panasonic VVX10F034N00 1920x1200 video mode panel"
- 	depends on OF
-@@ -73,6 +82,14 @@ config DRM_PANEL_PANASONIC_VVX10F034N00
- 	  WUXGA (1920x1200) Novatek NT1397-based DSI panel as found in some
- 	  Xperia Z2 tablets
- 
-+config DRM_PANEL_RASPBERRYPI_TOUCHSCREEN
-+	tristate "Raspberry Pi 7-inch touchscreen panel"
-+	depends on DRM_MIPI_DSI
-+	help
-+	  Say Y here if you want to enable support for the Raspberry
-+	  Pi 7" Touchscreen.  To compile this driver as a module,
-+	  choose M here.
-+
- config DRM_PANEL_SAMSUNG_S6E3HA2
- 	tristate "Samsung S6E3HA2 DSI video mode panel"
- 	depends on OF
-@@ -80,12 +97,28 @@ config DRM_PANEL_SAMSUNG_S6E3HA2
- 	depends on BACKLIGHT_CLASS_DEVICE
- 	select VIDEOMODE_HELPERS
- 
-+config DRM_PANEL_SAMSUNG_S6E63J0X03
-+	tristate "Samsung S6E63J0X03 DSI command mode panel"
-+	depends on OF
-+	depends on DRM_MIPI_DSI
-+	depends on BACKLIGHT_CLASS_DEVICE
-+	select VIDEOMODE_HELPERS
-+
- config DRM_PANEL_SAMSUNG_S6E8AA0
- 	tristate "Samsung S6E8AA0 DSI video mode panel"
- 	depends on OF
- 	select DRM_MIPI_DSI
- 	select VIDEOMODE_HELPERS
- 
-+config DRM_PANEL_SEIKO_43WVF1G
-+	tristate "Seiko 43WVF1G panel"
-+	depends on OF
-+	depends on BACKLIGHT_CLASS_DEVICE
-+	select VIDEOMODE_HELPERS
-+	help
-+	  Say Y here if you want to enable support for the Seiko
-+	  43WVF1G controller for 800x480 LCD panels
-+
- config DRM_PANEL_SHARP_LQ101R1SX01
- 	tristate "Sharp LQ101R1SX01 panel"
- 	depends on OF
---- linux-4.14/drivers/gpu/drm/panel/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/panel/Makefile	2017-12-14 06:39:58.517903639 +0100
-@@ -4,10 +4,14 @@ obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-
- obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o
- obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
- obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
-+obj-$(CONFIG_DRM_PANEL_ORISETECH_OTM8009A) += panel-orisetech-otm8009a.o
- obj-$(CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00) += panel-panasonic-vvx10f034n00.o
-+obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) += panel-raspberrypi-touchscreen.o
- obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
- obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o
-+obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) += panel-samsung-s6e63j0x03.o
- obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0) += panel-samsung-s6e8aa0.o
-+obj-$(CONFIG_DRM_PANEL_SEIKO_43WVF1G) += panel-seiko-43wvf1g.o
- obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o
- obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043t1le01.o
- obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o
---- linux-4.14/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c.0130~	2017-12-14 06:39:58.517903639 +0100
-+++ linux-4.14/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c	2017-12-14 06:39:58.517903639 +0100
-@@ -0,0 +1,491 @@
-+/*
-+ * Copyright (C) STMicroelectronics SA 2017
-+ *
-+ * Authors: Philippe Cornu <philippe.cornu@st.com>
-+ *          Yannick Fertre <yannick.fertre@st.com>
-+ *
-+ * License terms:  GNU General Public License (GPL), version 2
-+ */
-+#include <drm/drmP.h>
-+#include <drm/drm_mipi_dsi.h>
-+#include <drm/drm_panel.h>
-+#include <linux/backlight.h>
-+#include <linux/gpio/consumer.h>
-+#include <video/mipi_display.h>
-+
-+#define DRV_NAME "orisetech_otm8009a"
-+
-+#define OTM8009A_BACKLIGHT_DEFAULT	240
-+#define OTM8009A_BACKLIGHT_MAX		255
-+
-+/* Manufacturer Command Set */
-+#define MCS_ADRSFT	0x0000	/* Address Shift Function */
-+#define MCS_PANSET	0xB3A6	/* Panel Type Setting */
-+#define MCS_SD_CTRL	0xC0A2	/* Source Driver Timing Setting */
-+#define MCS_P_DRV_M	0xC0B4	/* Panel Driving Mode */
-+#define MCS_OSC_ADJ	0xC181	/* Oscillator Adjustment for Idle/Normal mode */
-+#define MCS_RGB_VID_SET	0xC1A1	/* RGB Video Mode Setting */
-+#define MCS_SD_PCH_CTRL	0xC480	/* Source Driver Precharge Control */
-+#define MCS_NO_DOC1	0xC48A	/* Command not documented */
-+#define MCS_PWR_CTRL1	0xC580	/* Power Control Setting 1 */
-+#define MCS_PWR_CTRL2	0xC590	/* Power Control Setting 2 for Normal Mode */
-+#define MCS_PWR_CTRL4	0xC5B0	/* Power Control Setting 4 for DC Voltage */
-+#define MCS_PANCTRLSET1	0xCB80	/* Panel Control Setting 1 */
-+#define MCS_PANCTRLSET2	0xCB90	/* Panel Control Setting 2 */
-+#define MCS_PANCTRLSET3	0xCBA0	/* Panel Control Setting 3 */
-+#define MCS_PANCTRLSET4	0xCBB0	/* Panel Control Setting 4 */
-+#define MCS_PANCTRLSET5	0xCBC0	/* Panel Control Setting 5 */
-+#define MCS_PANCTRLSET6	0xCBD0	/* Panel Control Setting 6 */
-+#define MCS_PANCTRLSET7	0xCBE0	/* Panel Control Setting 7 */
-+#define MCS_PANCTRLSET8	0xCBF0	/* Panel Control Setting 8 */
-+#define MCS_PANU2D1	0xCC80	/* Panel U2D Setting 1 */
-+#define MCS_PANU2D2	0xCC90	/* Panel U2D Setting 2 */
-+#define MCS_PANU2D3	0xCCA0	/* Panel U2D Setting 3 */
-+#define MCS_PAND2U1	0xCCB0	/* Panel D2U Setting 1 */
-+#define MCS_PAND2U2	0xCCC0	/* Panel D2U Setting 2 */
-+#define MCS_PAND2U3	0xCCD0	/* Panel D2U Setting 3 */
-+#define MCS_GOAVST	0xCE80	/* GOA VST Setting */
-+#define MCS_GOACLKA1	0xCEA0	/* GOA CLKA1 Setting */
-+#define MCS_GOACLKA3	0xCEB0	/* GOA CLKA3 Setting */
-+#define MCS_GOAECLK	0xCFC0	/* GOA ECLK Setting */
-+#define MCS_NO_DOC2	0xCFD0	/* Command not documented */
-+#define MCS_GVDDSET	0xD800	/* GVDD/NGVDD */
-+#define MCS_VCOMDC	0xD900	/* VCOM Voltage Setting */
-+#define MCS_GMCT2_2P	0xE100	/* Gamma Correction 2.2+ Setting */
-+#define MCS_GMCT2_2N	0xE200	/* Gamma Correction 2.2- Setting */
-+#define MCS_NO_DOC3	0xF5B6	/* Command not documented */
-+#define MCS_CMD2_ENA1	0xFF00	/* Enable Access Command2 "CMD2" */
-+#define MCS_CMD2_ENA2	0xFF80	/* Enable Access Orise Command2 */
-+
-+struct otm8009a {
-+	struct device *dev;
-+	struct drm_panel panel;
-+	struct backlight_device *bl_dev;
-+	struct gpio_desc *reset_gpio;
-+	bool prepared;
-+	bool enabled;
-+};
-+
-+static const struct drm_display_mode default_mode = {
-+	.clock = 32729,
-+	.hdisplay = 480,
-+	.hsync_start = 480 + 120,
-+	.hsync_end = 480 + 120 + 63,
-+	.htotal = 480 + 120 + 63 + 120,
-+	.vdisplay = 800,
-+	.vsync_start = 800 + 12,
-+	.vsync_end = 800 + 12 + 12,
-+	.vtotal = 800 + 12 + 12 + 12,
-+	.vrefresh = 50,
-+	.flags = 0,
-+	.width_mm = 52,
-+	.height_mm = 86,
-+};
-+
-+static inline struct otm8009a *panel_to_otm8009a(struct drm_panel *panel)
-+{
-+	return container_of(panel, struct otm8009a, panel);
-+}
-+
-+static void otm8009a_dcs_write_buf(struct otm8009a *ctx, const void *data,
-+				   size_t len)
-+{
-+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-+
-+	if (mipi_dsi_dcs_write_buffer(dsi, data, len) < 0)
-+		DRM_WARN("mipi dsi dcs write buffer failed\n");
-+}
-+
-+#define dcs_write_seq(ctx, seq...)			\
-+({							\
-+	static const u8 d[] = { seq };			\
-+	otm8009a_dcs_write_buf(ctx, d, ARRAY_SIZE(d));	\
-+})
-+
-+#define dcs_write_cmd_at(ctx, cmd, seq...)		\
-+({							\
-+	dcs_write_seq(ctx, MCS_ADRSFT, (cmd) & 0xFF);	\
-+	dcs_write_seq(ctx, (cmd) >> 8, seq);		\
-+})
-+
-+static int otm8009a_init_sequence(struct otm8009a *ctx)
-+{
-+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-+	int ret;
-+
-+	/* Enter CMD2 */
-+	dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01);
-+
-+	/* Enter Orise Command2 */
-+	dcs_write_cmd_at(ctx, MCS_CMD2_ENA2, 0x80, 0x09);
-+
-+	dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL, 0x30);
-+	mdelay(10);
-+
-+	dcs_write_cmd_at(ctx, MCS_NO_DOC1, 0x40);
-+	mdelay(10);
-+
-+	dcs_write_cmd_at(ctx, MCS_PWR_CTRL4 + 1, 0xA9);
-+	dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 1, 0x34);
-+	dcs_write_cmd_at(ctx, MCS_P_DRV_M, 0x50);
-+	dcs_write_cmd_at(ctx, MCS_VCOMDC, 0x4E);
-+	dcs_write_cmd_at(ctx, MCS_OSC_ADJ, 0x66); /* 65Hz */
-+	dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 2, 0x01);
-+	dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 5, 0x34);
-+	dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 4, 0x33);
-+	dcs_write_cmd_at(ctx, MCS_GVDDSET, 0x79, 0x79);
-+	dcs_write_cmd_at(ctx, MCS_SD_CTRL + 1, 0x1B);
-+	dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 2, 0x83);
-+	dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL + 1, 0x83);
-+	dcs_write_cmd_at(ctx, MCS_RGB_VID_SET, 0x0E);
-+	dcs_write_cmd_at(ctx, MCS_PANSET, 0x00, 0x01);
-+
-+	dcs_write_cmd_at(ctx, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00);
-+	dcs_write_cmd_at(ctx, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00,
-+			 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00);
-+	dcs_write_cmd_at(ctx, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00,
-+			 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00);
-+	dcs_write_cmd_at(ctx, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00,
-+			 0x01, 0x02, 0x00, 0x00);
-+
-+	dcs_write_cmd_at(ctx, MCS_NO_DOC2, 0x00);
-+
-+	dcs_write_cmd_at(ctx, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
-+	dcs_write_cmd_at(ctx, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-+			 0, 0, 0, 0, 0);
-+	dcs_write_cmd_at(ctx, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-+			 0, 0, 0, 0, 0);
-+	dcs_write_cmd_at(ctx, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
-+	dcs_write_cmd_at(ctx, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0,
-+			 0, 0, 0, 0, 0);
-+	dcs_write_cmd_at(ctx, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4,
-+			 4, 0, 0, 0, 0);
-+	dcs_write_cmd_at(ctx, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
-+	dcs_write_cmd_at(ctx, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-+			 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
-+
-+	dcs_write_cmd_at(ctx, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25,
-+			 0x00, 0x00, 0x00, 0x00);
-+	dcs_write_cmd_at(ctx, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+			 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02);
-+	dcs_write_cmd_at(ctx, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00,
-+			 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
-+	dcs_write_cmd_at(ctx, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26,
-+			 0x00, 0x00, 0x00, 0x00);
-+	dcs_write_cmd_at(ctx, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+			 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01);
-+	dcs_write_cmd_at(ctx, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00,
-+			 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
-+
-+	dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 1, 0x66);
-+
-+	dcs_write_cmd_at(ctx, MCS_NO_DOC3, 0x06);
-+
-+	dcs_write_cmd_at(ctx, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
-+			 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
-+			 0x01);
-+	dcs_write_cmd_at(ctx, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
-+			 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
-+			 0x01);
-+
-+	/* Exit CMD2 */
-+	dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF);
-+
-+	ret = mipi_dsi_dcs_nop(dsi);
-+	if (ret)
-+		return ret;
-+
-+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
-+	if (ret)
-+		return ret;
-+
-+	/* Wait for sleep out exit */
-+	mdelay(120);
-+
-+	/* Default portrait 480x800 rgb24 */
-+	dcs_write_seq(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
-+
-+	ret = mipi_dsi_dcs_set_column_address(dsi, 0,
-+					      default_mode.hdisplay - 1);
-+	if (ret)
-+		return ret;
-+
-+	ret = mipi_dsi_dcs_set_page_address(dsi, 0, default_mode.vdisplay - 1);
-+	if (ret)
-+		return ret;
-+
-+	/* See otm8009a driver documentation for pixel format descriptions */
-+	ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT |
-+					    MIPI_DCS_PIXEL_FMT_24BIT << 4);
-+	if (ret)
-+		return ret;
-+
-+	/* Disable CABC feature */
-+	dcs_write_seq(ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
-+
-+	ret = mipi_dsi_dcs_set_display_on(dsi);
-+	if (ret)
-+		return ret;
-+
-+	ret = mipi_dsi_dcs_nop(dsi);
-+	if (ret)
-+		return ret;
-+
-+	/* Send Command GRAM memory write (no parameters) */
-+	dcs_write_seq(ctx, MIPI_DCS_WRITE_MEMORY_START);
-+
-+	return 0;
-+}
-+
-+static int otm8009a_disable(struct drm_panel *panel)
-+{
-+	struct otm8009a *ctx = panel_to_otm8009a(panel);
-+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-+	int ret;
-+
-+	if (!ctx->enabled)
-+		return 0; /* This is not an issue so we return 0 here */
-+
-+	/* Power off the backlight. Note: end-user still controls brightness */
-+	ctx->bl_dev->props.power = FB_BLANK_POWERDOWN;
-+	ret = backlight_update_status(ctx->bl_dev);
-+	if (ret)
-+		return ret;
-+
-+	ret = mipi_dsi_dcs_set_display_off(dsi);
-+	if (ret)
-+		return ret;
-+
-+	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
-+	if (ret)
-+		return ret;
-+
-+	msleep(120);
-+
-+	ctx->enabled = false;
-+
-+	return 0;
-+}
-+
-+static int otm8009a_unprepare(struct drm_panel *panel)
-+{
-+	struct otm8009a *ctx = panel_to_otm8009a(panel);
-+
-+	if (!ctx->prepared)
-+		return 0;
-+
-+	if (ctx->reset_gpio) {
-+		gpiod_set_value_cansleep(ctx->reset_gpio, 1);
-+		msleep(20);
-+	}
-+
-+	ctx->prepared = false;
-+
-+	return 0;
-+}
-+
-+static int otm8009a_prepare(struct drm_panel *panel)
-+{
-+	struct otm8009a *ctx = panel_to_otm8009a(panel);
-+	int ret;
-+
-+	if (ctx->prepared)
-+		return 0;
-+
-+	if (ctx->reset_gpio) {
-+		gpiod_set_value_cansleep(ctx->reset_gpio, 0);
-+		gpiod_set_value_cansleep(ctx->reset_gpio, 1);
-+		msleep(20);
-+		gpiod_set_value_cansleep(ctx->reset_gpio, 0);
-+		msleep(100);
-+	}
-+
-+	ret = otm8009a_init_sequence(ctx);
-+	if (ret)
-+		return ret;
-+
-+	ctx->prepared = true;
-+
-+	/*
-+	 * Power on the backlight. Note: end-user still controls brightness
-+	 * Note: ctx->prepared must be true before updating the backlight.
-+	 */
-+	ctx->bl_dev->props.power = FB_BLANK_UNBLANK;
-+	backlight_update_status(ctx->bl_dev);
-+
-+	return 0;
-+}
-+
-+static int otm8009a_enable(struct drm_panel *panel)
-+{
-+	struct otm8009a *ctx = panel_to_otm8009a(panel);
-+
-+	ctx->enabled = true;
-+
-+	return 0;
-+}
-+
-+static int otm8009a_get_modes(struct drm_panel *panel)
-+{
-+	struct drm_display_mode *mode;
-+
-+	mode = drm_mode_duplicate(panel->drm, &default_mode);
-+	if (!mode) {
-+		DRM_ERROR("failed to add mode %ux%ux@%u\n",
-+			  default_mode.hdisplay, default_mode.vdisplay,
-+			  default_mode.vrefresh);
-+		return -ENOMEM;
-+	}
-+
-+	drm_mode_set_name(mode);
-+
-+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-+	drm_mode_probed_add(panel->connector, mode);
-+
-+	panel->connector->display_info.width_mm = mode->width_mm;
-+	panel->connector->display_info.height_mm = mode->height_mm;
-+
-+	return 1;
-+}
-+
-+static const struct drm_panel_funcs otm8009a_drm_funcs = {
-+	.disable   = otm8009a_disable,
-+	.unprepare = otm8009a_unprepare,
-+	.prepare   = otm8009a_prepare,
-+	.enable    = otm8009a_enable,
-+	.get_modes = otm8009a_get_modes,
-+};
-+
-+/*
-+ * DSI-BASED BACKLIGHT
-+ */
-+
-+static int otm8009a_backlight_update_status(struct backlight_device *bd)
-+{
-+	struct otm8009a *ctx = bl_get_data(bd);
-+	u8 data[2];
-+
-+	if (!ctx->prepared) {
-+		DRM_DEBUG("lcd not ready yet for setting its backlight!\n");
-+		return -ENXIO;
-+	}
-+
-+	if (bd->props.power <= FB_BLANK_NORMAL) {
-+		/* Power on the backlight with the requested brightness
-+		 * Note We can not use mipi_dsi_dcs_set_display_brightness()
-+		 * as otm8009a driver support only 8-bit brightness (1 param).
-+		 */
-+		data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS;
-+		data[1] = bd->props.brightness;
-+		otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data));
-+
-+		/* set Brightness Control & Backlight on */
-+		data[1] = 0x24;
-+
-+	} else {
-+		/* Power off the backlight: set Brightness Control & Bl off */
-+		data[1] = 0;
-+	}
-+
-+	/* Update Brightness Control & Backlight */
-+	data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY;
-+	otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data));
-+
-+	return 0;
-+}
-+
-+static const struct backlight_ops otm8009a_backlight_ops = {
-+	.update_status = otm8009a_backlight_update_status,
-+};
-+
-+static int otm8009a_probe(struct mipi_dsi_device *dsi)
-+{
-+	struct device *dev = &dsi->dev;
-+	struct otm8009a *ctx;
-+	int ret;
-+
-+	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
-+	if (!ctx)
-+		return -ENOMEM;
-+
-+	ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
-+	if (IS_ERR(ctx->reset_gpio)) {
-+		dev_err(dev, "cannot get reset-gpio\n");
-+		return PTR_ERR(ctx->reset_gpio);
-+	}
-+
-+	mipi_dsi_set_drvdata(dsi, ctx);
-+
-+	ctx->dev = dev;
-+
-+	dsi->lanes = 2;
-+	dsi->format = MIPI_DSI_FMT_RGB888;
-+	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
-+			  MIPI_DSI_MODE_LPM;
-+
-+	drm_panel_init(&ctx->panel);
-+	ctx->panel.dev = dev;
-+	ctx->panel.funcs = &otm8009a_drm_funcs;
-+
-+	ctx->bl_dev = backlight_device_register(DRV_NAME "_backlight", dev, ctx,
-+						&otm8009a_backlight_ops, NULL);
-+	if (IS_ERR(ctx->bl_dev)) {
-+		dev_err(dev, "failed to register backlight device\n");
-+		return PTR_ERR(ctx->bl_dev);
-+	}
-+
-+	ctx->bl_dev->props.max_brightness = OTM8009A_BACKLIGHT_MAX;
-+	ctx->bl_dev->props.brightness = OTM8009A_BACKLIGHT_DEFAULT;
-+	ctx->bl_dev->props.power = FB_BLANK_POWERDOWN;
-+	ctx->bl_dev->props.type = BACKLIGHT_RAW;
-+
-+	drm_panel_add(&ctx->panel);
-+
-+	ret = mipi_dsi_attach(dsi);
-+	if (ret < 0) {
-+		dev_err(dev, "mipi_dsi_attach failed. Is host ready?\n");
-+		drm_panel_remove(&ctx->panel);
-+		backlight_device_unregister(ctx->bl_dev);
-+		return ret;
-+	}
-+
-+	DRM_INFO(DRV_NAME "_panel %ux%u@%u %ubpp dsi %udl - ready\n",
-+		 default_mode.hdisplay, default_mode.vdisplay,
-+		 default_mode.vrefresh,
-+		 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes);
-+
-+	return 0;
-+}
-+
-+static int otm8009a_remove(struct mipi_dsi_device *dsi)
-+{
-+	struct otm8009a *ctx = mipi_dsi_get_drvdata(dsi);
-+
-+	mipi_dsi_detach(dsi);
-+	drm_panel_remove(&ctx->panel);
-+
-+	backlight_device_unregister(ctx->bl_dev);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id orisetech_otm8009a_of_match[] = {
-+	{ .compatible = "orisetech,otm8009a" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, orisetech_otm8009a_of_match);
-+
-+static struct mipi_dsi_driver orisetech_otm8009a_driver = {
-+	.probe  = otm8009a_probe,
-+	.remove = otm8009a_remove,
-+	.driver = {
-+		.name = DRV_NAME "_panel",
-+		.of_match_table = orisetech_otm8009a_of_match,
-+	},
-+};
-+module_mipi_dsi_driver(orisetech_otm8009a_driver);
-+
-+MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
-+MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
-+MODULE_DESCRIPTION("DRM driver for Orise Tech OTM8009A MIPI DSI panel");
-+MODULE_LICENSE("GPL v2");
---- linux-4.14/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c.0130~	2017-12-14 06:39:58.517903639 +0100
-+++ linux-4.14/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c	2017-12-14 06:39:58.517903639 +0100
-@@ -0,0 +1,514 @@
-+/*
-+ * Copyright © 2016-2017 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * Portions of this file (derived from panel-simple.c) are:
-+ *
-+ * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice (including the
-+ * next paragraph) shall be included in all copies or substantial portions
-+ * of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-+ * DEALINGS IN THE SOFTWARE.
-+ */
-+
-+/**
-+ * Raspberry Pi 7" touchscreen panel driver.
-+ *
-+ * The 7" touchscreen consists of a DPI LCD panel, a Toshiba
-+ * TC358762XBG DSI-DPI bridge, and an I2C-connected Atmel ATTINY88-MUR
-+ * controlling power management, the LCD PWM, and initial register
-+ * setup of the Tohsiba.
-+ *
-+ * This driver controls the TC358762 and ATTINY88, presenting a DSI
-+ * device with a drm_panel.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/fb.h>
-+#include <linux/gpio.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/i2c.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_graph.h>
-+#include <linux/pm.h>
-+
-+#include <drm/drm_panel.h>
-+#include <drm/drmP.h>
-+#include <drm/drm_crtc.h>
-+#include <drm/drm_mipi_dsi.h>
-+#include <drm/drm_panel.h>
-+
-+#define RPI_DSI_DRIVER_NAME "rpi-ts-dsi"
-+
-+/* I2C registers of the Atmel microcontroller. */
-+enum REG_ADDR {
-+	REG_ID = 0x80,
-+	REG_PORTA, /* BIT(2) for horizontal flip, BIT(3) for vertical flip */
-+	REG_PORTB,
-+	REG_PORTC,
-+	REG_PORTD,
-+	REG_POWERON,
-+	REG_PWM,
-+	REG_DDRA,
-+	REG_DDRB,
-+	REG_DDRC,
-+	REG_DDRD,
-+	REG_TEST,
-+	REG_WR_ADDRL,
-+	REG_WR_ADDRH,
-+	REG_READH,
-+	REG_READL,
-+	REG_WRITEH,
-+	REG_WRITEL,
-+	REG_ID2,
-+};
-+
-+/* DSI D-PHY Layer Registers */
-+#define D0W_DPHYCONTTX		0x0004
-+#define CLW_DPHYCONTRX		0x0020
-+#define D0W_DPHYCONTRX		0x0024
-+#define D1W_DPHYCONTRX		0x0028
-+#define COM_DPHYCONTRX		0x0038
-+#define CLW_CNTRL		0x0040
-+#define D0W_CNTRL		0x0044
-+#define D1W_CNTRL		0x0048
-+#define DFTMODE_CNTRL		0x0054
-+
-+/* DSI PPI Layer Registers */
-+#define PPI_STARTPPI		0x0104
-+#define PPI_BUSYPPI		0x0108
-+#define PPI_LINEINITCNT		0x0110
-+#define PPI_LPTXTIMECNT		0x0114
-+#define PPI_CLS_ATMR		0x0140
-+#define PPI_D0S_ATMR		0x0144
-+#define PPI_D1S_ATMR		0x0148
-+#define PPI_D0S_CLRSIPOCOUNT	0x0164
-+#define PPI_D1S_CLRSIPOCOUNT	0x0168
-+#define CLS_PRE			0x0180
-+#define D0S_PRE			0x0184
-+#define D1S_PRE			0x0188
-+#define CLS_PREP		0x01A0
-+#define D0S_PREP		0x01A4
-+#define D1S_PREP		0x01A8
-+#define CLS_ZERO		0x01C0
-+#define D0S_ZERO		0x01C4
-+#define D1S_ZERO		0x01C8
-+#define PPI_CLRFLG		0x01E0
-+#define PPI_CLRSIPO		0x01E4
-+#define HSTIMEOUT		0x01F0
-+#define HSTIMEOUTENABLE		0x01F4
-+
-+/* DSI Protocol Layer Registers */
-+#define DSI_STARTDSI		0x0204
-+#define DSI_BUSYDSI		0x0208
-+#define DSI_LANEENABLE		0x0210
-+# define DSI_LANEENABLE_CLOCK		BIT(0)
-+# define DSI_LANEENABLE_D0		BIT(1)
-+# define DSI_LANEENABLE_D1		BIT(2)
-+
-+#define DSI_LANESTATUS0		0x0214
-+#define DSI_LANESTATUS1		0x0218
-+#define DSI_INTSTATUS		0x0220
-+#define DSI_INTMASK		0x0224
-+#define DSI_INTCLR		0x0228
-+#define DSI_LPTXTO		0x0230
-+#define DSI_MODE		0x0260
-+#define DSI_PAYLOAD0		0x0268
-+#define DSI_PAYLOAD1		0x026C
-+#define DSI_SHORTPKTDAT		0x0270
-+#define DSI_SHORTPKTREQ		0x0274
-+#define DSI_BTASTA		0x0278
-+#define DSI_BTACLR		0x027C
-+
-+/* DSI General Registers */
-+#define DSIERRCNT		0x0300
-+#define DSISIGMOD		0x0304
-+
-+/* DSI Application Layer Registers */
-+#define APLCTRL			0x0400
-+#define APLSTAT			0x0404
-+#define APLERR			0x0408
-+#define PWRMOD			0x040C
-+#define RDPKTLN			0x0410
-+#define PXLFMT			0x0414
-+#define MEMWRCMD		0x0418
-+
-+/* LCDC/DPI Host Registers */
-+#define LCDCTRL			0x0420
-+#define HSR			0x0424
-+#define HDISPR			0x0428
-+#define VSR			0x042C
-+#define VDISPR			0x0430
-+#define VFUEN			0x0434
-+
-+/* DBI-B Host Registers */
-+#define DBIBCTRL		0x0440
-+
-+/* SPI Master Registers */
-+#define SPICMR			0x0450
-+#define SPITCR			0x0454
-+
-+/* System Controller Registers */
-+#define SYSSTAT			0x0460
-+#define SYSCTRL			0x0464
-+#define SYSPLL1			0x0468
-+#define SYSPLL2			0x046C
-+#define SYSPLL3			0x0470
-+#define SYSPMCTRL		0x047C
-+
-+/* GPIO Registers */
-+#define GPIOC			0x0480
-+#define GPIOO			0x0484
-+#define GPIOI			0x0488
-+
-+/* I2C Registers */
-+#define I2CCLKCTRL		0x0490
-+
-+/* Chip/Rev Registers */
-+#define IDREG			0x04A0
-+
-+/* Debug Registers */
-+#define WCMDQUEUE		0x0500
-+#define RCMDQUEUE		0x0504
-+
-+struct rpi_touchscreen {
-+	struct drm_panel base;
-+	struct mipi_dsi_device *dsi;
-+	struct i2c_client *i2c;
-+};
-+
-+static const struct drm_display_mode rpi_touchscreen_modes[] = {
-+	{
-+		/* Modeline comes from the Raspberry Pi firmware, with HFP=1
-+		 * plugged in and clock re-computed from that.
-+		 */
-+		.clock = 25979400 / 1000,
-+		.hdisplay = 800,
-+		.hsync_start = 800 + 1,
-+		.hsync_end = 800 + 1 + 2,
-+		.htotal = 800 + 1 + 2 + 46,
-+		.vdisplay = 480,
-+		.vsync_start = 480 + 7,
-+		.vsync_end = 480 + 7 + 2,
-+		.vtotal = 480 + 7 + 2 + 21,
-+		.vrefresh = 60,
-+	},
-+};
-+
-+static struct rpi_touchscreen *panel_to_ts(struct drm_panel *panel)
-+{
-+	return container_of(panel, struct rpi_touchscreen, base);
-+}
-+
-+static u8 rpi_touchscreen_i2c_read(struct rpi_touchscreen *ts, u8 reg)
-+{
-+	return i2c_smbus_read_byte_data(ts->i2c, reg);
-+}
-+
-+static void rpi_touchscreen_i2c_write(struct rpi_touchscreen *ts,
-+				      u8 reg, u8 val)
-+{
-+	int ret;
-+
-+	ret = i2c_smbus_write_byte_data(ts->i2c, reg, val);
-+	if (ret)
-+		dev_err(&ts->dsi->dev, "I2C write failed: %d\n", ret);
-+}
-+
-+static int rpi_touchscreen_write(struct rpi_touchscreen *ts, u16 reg, u32 val)
-+{
-+#if 0
-+	/* The firmware uses LP DSI transactions like this to bring up
-+	 * the hardware, which should be faster than using I2C to then
-+	 * pass to the Toshiba.  However, I was unable to get it to
-+	 * work.
-+	 */
-+	u8 msg[] = {
-+		reg,
-+		reg >> 8,
-+		val,
-+		val >> 8,
-+		val >> 16,
-+		val >> 24,
-+	};
-+
-+	mipi_dsi_dcs_write_buffer(ts->dsi, msg, sizeof(msg));
-+#else
-+	rpi_touchscreen_i2c_write(ts, REG_WR_ADDRH, reg >> 8);
-+	rpi_touchscreen_i2c_write(ts, REG_WR_ADDRL, reg);
-+	rpi_touchscreen_i2c_write(ts, REG_WRITEH, val >> 8);
-+	rpi_touchscreen_i2c_write(ts, REG_WRITEL, val);
-+#endif
-+
-+	return 0;
-+}
-+
-+static int rpi_touchscreen_disable(struct drm_panel *panel)
-+{
-+	struct rpi_touchscreen *ts = panel_to_ts(panel);
-+
-+	rpi_touchscreen_i2c_write(ts, REG_PWM, 0);
-+
-+	rpi_touchscreen_i2c_write(ts, REG_POWERON, 0);
-+	udelay(1);
-+
-+	return 0;
-+}
-+
-+static int rpi_touchscreen_noop(struct drm_panel *panel)
-+{
-+	return 0;
-+}
-+
-+static int rpi_touchscreen_enable(struct drm_panel *panel)
-+{
-+	struct rpi_touchscreen *ts = panel_to_ts(panel);
-+	int i;
-+
-+	rpi_touchscreen_i2c_write(ts, REG_POWERON, 1);
-+	/* Wait for nPWRDWN to go low to indicate poweron is done. */
-+	for (i = 0; i < 100; i++) {
-+		if (rpi_touchscreen_i2c_read(ts, REG_PORTB) & 1)
-+			break;
-+	}
-+
-+	rpi_touchscreen_write(ts, DSI_LANEENABLE,
-+			      DSI_LANEENABLE_CLOCK |
-+			      DSI_LANEENABLE_D0);
-+	rpi_touchscreen_write(ts, PPI_D0S_CLRSIPOCOUNT, 0x05);
-+	rpi_touchscreen_write(ts, PPI_D1S_CLRSIPOCOUNT, 0x05);
-+	rpi_touchscreen_write(ts, PPI_D0S_ATMR, 0x00);
-+	rpi_touchscreen_write(ts, PPI_D1S_ATMR, 0x00);
-+	rpi_touchscreen_write(ts, PPI_LPTXTIMECNT, 0x03);
-+
-+	rpi_touchscreen_write(ts, SPICMR, 0x00);
-+	rpi_touchscreen_write(ts, LCDCTRL, 0x00100150);
-+	rpi_touchscreen_write(ts, SYSCTRL, 0x040f);
-+	msleep(100);
-+
-+	rpi_touchscreen_write(ts, PPI_STARTPPI, 0x01);
-+	rpi_touchscreen_write(ts, DSI_STARTDSI, 0x01);
-+	msleep(100);
-+
-+	/* Turn on the backlight. */
-+	rpi_touchscreen_i2c_write(ts, REG_PWM, 255);
-+
-+	/* Default to the same orientation as the closed source
-+	 * firmware used for the panel.  Runtime rotation
-+	 * configuration will be supported using VC4's plane
-+	 * orientation bits.
-+	 */
-+	rpi_touchscreen_i2c_write(ts, REG_PORTA, BIT(2));
-+
-+	return 0;
-+}
-+
-+static int rpi_touchscreen_get_modes(struct drm_panel *panel)
-+{
-+	struct drm_connector *connector = panel->connector;
-+	struct drm_device *drm = panel->drm;
-+	unsigned int i, num = 0;
-+	static const u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
-+
-+	for (i = 0; i < ARRAY_SIZE(rpi_touchscreen_modes); i++) {
-+		const struct drm_display_mode *m = &rpi_touchscreen_modes[i];
-+		struct drm_display_mode *mode;
-+
-+		mode = drm_mode_duplicate(drm, m);
-+		if (!mode) {
-+			dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
-+				m->hdisplay, m->vdisplay, m->vrefresh);
-+			continue;
-+		}
-+
-+		mode->type |= DRM_MODE_TYPE_DRIVER;
-+
-+		if (i == 0)
-+			mode->type |= DRM_MODE_TYPE_PREFERRED;
-+
-+		drm_mode_set_name(mode);
-+
-+		drm_mode_probed_add(connector, mode);
-+		num++;
-+	}
-+
-+	connector->display_info.bpc = 8;
-+	connector->display_info.width_mm = 154;
-+	connector->display_info.height_mm = 86;
-+	drm_display_info_set_bus_formats(&connector->display_info,
-+					 &bus_format, 1);
-+
-+	return num;
-+}
-+
-+static const struct drm_panel_funcs rpi_touchscreen_funcs = {
-+	.disable = rpi_touchscreen_disable,
-+	.unprepare = rpi_touchscreen_noop,
-+	.prepare = rpi_touchscreen_noop,
-+	.enable = rpi_touchscreen_enable,
-+	.get_modes = rpi_touchscreen_get_modes,
-+};
-+
-+static int rpi_touchscreen_probe(struct i2c_client *i2c,
-+				 const struct i2c_device_id *id)
-+{
-+	struct device *dev = &i2c->dev;
-+	struct rpi_touchscreen *ts;
-+	struct device_node *endpoint, *dsi_host_node;
-+	struct mipi_dsi_host *host;
-+	int ret, ver;
-+	struct mipi_dsi_device_info info = {
-+		.type = RPI_DSI_DRIVER_NAME,
-+		.channel = 0,
-+		.node = NULL,
-+	};
-+
-+	ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL);
-+	if (!ts)
-+		return -ENOMEM;
-+
-+	i2c_set_clientdata(i2c, ts);
-+
-+	ts->i2c = i2c;
-+
-+	ver = rpi_touchscreen_i2c_read(ts, REG_ID);
-+	if (ver < 0) {
-+		dev_err(dev, "Atmel I2C read failed: %d\n", ver);
-+		return -ENODEV;
-+	}
-+
-+	switch (ver) {
-+	case 0xde: /* ver 1 */
-+	case 0xc3: /* ver 2 */
-+		break;
-+	default:
-+		dev_err(dev, "Unknown Atmel firmware revision: 0x%02x\n", ver);
-+		return -ENODEV;
-+	}
-+
-+	/* Turn off at boot, so we can cleanly sequence powering on. */
-+	rpi_touchscreen_i2c_write(ts, REG_POWERON, 0);
-+
-+	/* Look up the DSI host.  It needs to probe before we do. */
-+	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
-+	dsi_host_node = of_graph_get_remote_port_parent(endpoint);
-+	host = of_find_mipi_dsi_host_by_node(dsi_host_node);
-+	of_node_put(dsi_host_node);
-+	if (!host) {
-+		of_node_put(endpoint);
-+		return -EPROBE_DEFER;
-+	}
-+
-+	info.node = of_graph_get_remote_port(endpoint);
-+	of_node_put(endpoint);
-+
-+	ts->dsi = mipi_dsi_device_register_full(host, &info);
-+	if (IS_ERR(ts->dsi)) {
-+		dev_err(dev, "DSI device registration failed: %ld\n",
-+			PTR_ERR(ts->dsi));
-+		return PTR_ERR(ts->dsi);
-+	}
-+
-+	ts->base.dev = dev;
-+	ts->base.funcs = &rpi_touchscreen_funcs;
-+
-+	/* This appears last, as it's what will unblock the DSI host
-+	 * driver's component bind function.
-+	 */
-+	ret = drm_panel_add(&ts->base);
-+	if (ret)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static int rpi_touchscreen_remove(struct i2c_client *i2c)
-+{
-+	struct rpi_touchscreen *ts = i2c_get_clientdata(i2c);
-+
-+	mipi_dsi_detach(ts->dsi);
-+
-+	drm_panel_remove(&ts->base);
-+
-+	mipi_dsi_device_unregister(ts->dsi);
-+	kfree(ts->dsi);
-+
-+	return 0;
-+}
-+
-+static int rpi_touchscreen_dsi_probe(struct mipi_dsi_device *dsi)
-+{
-+	int ret;
-+
-+	dsi->mode_flags = (MIPI_DSI_MODE_VIDEO |
-+			   MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
-+			   MIPI_DSI_MODE_LPM);
-+	dsi->format = MIPI_DSI_FMT_RGB888;
-+	dsi->lanes = 1;
-+
-+	ret = mipi_dsi_attach(dsi);
-+
-+	if (ret)
-+		dev_err(&dsi->dev, "failed to attach dsi to host: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static struct mipi_dsi_driver rpi_touchscreen_dsi_driver = {
-+	.driver.name = RPI_DSI_DRIVER_NAME,
-+	.probe = rpi_touchscreen_dsi_probe,
-+};
-+
-+static const struct of_device_id rpi_touchscreen_of_ids[] = {
-+	{ .compatible = "raspberrypi,7inch-touchscreen-panel" },
-+	{ } /* sentinel */
-+};
-+MODULE_DEVICE_TABLE(of, rpi_touchscreen_of_ids);
-+
-+static struct i2c_driver rpi_touchscreen_driver = {
-+	.driver = {
-+		.name = "rpi_touchscreen",
-+		.of_match_table = rpi_touchscreen_of_ids,
-+	},
-+	.probe = rpi_touchscreen_probe,
-+	.remove = rpi_touchscreen_remove,
-+};
-+
-+static int __init rpi_touchscreen_init(void)
-+{
-+	mipi_dsi_driver_register(&rpi_touchscreen_dsi_driver);
-+	return i2c_add_driver(&rpi_touchscreen_driver);
-+}
-+module_init(rpi_touchscreen_init);
-+
-+static void __exit rpi_touchscreen_exit(void)
-+{
-+	i2c_del_driver(&rpi_touchscreen_driver);
-+	mipi_dsi_driver_unregister(&rpi_touchscreen_dsi_driver);
-+}
-+module_exit(rpi_touchscreen_exit);
-+
-+MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
-+MODULE_DESCRIPTION("Raspberry Pi 7-inch touchscreen driver");
-+MODULE_LICENSE("GPL v2");
---- linux-4.14/drivers/gpu/drm/panel/panel-samsung-s6e63j0x03.c.0130~	2017-12-14 06:39:58.517903639 +0100
-+++ linux-4.14/drivers/gpu/drm/panel/panel-samsung-s6e63j0x03.c	2017-12-14 06:39:58.517903639 +0100
-@@ -0,0 +1,532 @@
-+/*
-+ * MIPI-DSI based S6E63J0X03 AMOLED lcd 1.63 inch panel driver.
-+ *
-+ * Copyright (c) 2014-2017 Samsung Electronics Co., Ltd
-+ *
-+ * Inki Dae <inki.dae@samsung.com>
-+ * Hoegeun Kwon <hoegeun.kwon@samsung.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <drm/drmP.h>
-+#include <drm/drm_mipi_dsi.h>
-+#include <drm/drm_panel.h>
-+#include <linux/backlight.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/regulator/consumer.h>
-+#include <video/mipi_display.h>
-+
-+#define MCS_LEVEL2_KEY		0xf0
-+#define MCS_MTP_KEY		0xf1
-+#define MCS_MTP_SET3		0xd4
-+
-+#define MAX_BRIGHTNESS		100
-+#define DEFAULT_BRIGHTNESS	80
-+
-+#define NUM_GAMMA_STEPS		9
-+#define GAMMA_CMD_CNT		28
-+
-+#define FIRST_COLUMN 20
-+
-+struct s6e63j0x03 {
-+	struct device *dev;
-+	struct drm_panel panel;
-+	struct backlight_device *bl_dev;
-+
-+	struct regulator_bulk_data supplies[2];
-+	struct gpio_desc *reset_gpio;
-+};
-+
-+static const struct drm_display_mode default_mode = {
-+	.clock = 4649,
-+	.hdisplay = 320,
-+	.hsync_start = 320 + 1,
-+	.hsync_end = 320 + 1 + 1,
-+	.htotal = 320 + 1 + 1 + 1,
-+	.vdisplay = 320,
-+	.vsync_start = 320 + 150,
-+	.vsync_end = 320 + 150 + 1,
-+	.vtotal = 320 + 150 + 1 + 2,
-+	.vrefresh = 30,
-+	.flags = 0,
-+};
-+
-+static const unsigned char gamma_tbl[NUM_GAMMA_STEPS][GAMMA_CMD_CNT] = {
-+	{	/* Gamma 10 */
-+		MCS_MTP_SET3,
-+		0x00, 0x00, 0x00, 0x7f, 0x7f, 0x7f, 0x52, 0x6b, 0x6f, 0x26,
-+		0x28, 0x2d, 0x28, 0x26, 0x27, 0x33, 0x34, 0x32, 0x36, 0x36,
-+		0x35, 0x00, 0xab, 0x00, 0xae, 0x00, 0xbf
-+	},
-+	{	/* gamma 30 */
-+		MCS_MTP_SET3,
-+		0x00, 0x00, 0x00, 0x70, 0x7f, 0x7f, 0x4e, 0x64, 0x69, 0x26,
-+		0x27, 0x2a, 0x28, 0x29, 0x27, 0x31, 0x32, 0x31, 0x35, 0x34,
-+		0x35, 0x00, 0xc4, 0x00, 0xca, 0x00, 0xdc
-+	},
-+	{	/* gamma 60 */
-+		MCS_MTP_SET3,
-+		0x00, 0x00, 0x00, 0x65, 0x7b, 0x7d, 0x5f, 0x67, 0x68, 0x2a,
-+		0x28, 0x29, 0x28, 0x2a, 0x27, 0x31, 0x2f, 0x30, 0x34, 0x33,
-+		0x34, 0x00, 0xd9, 0x00, 0xe4, 0x00, 0xf5
-+	},
-+	{	/* gamma 90 */
-+		MCS_MTP_SET3,
-+		0x00, 0x00, 0x00, 0x4d, 0x6f, 0x71, 0x67, 0x6a, 0x6c, 0x29,
-+		0x28, 0x28, 0x28, 0x29, 0x27, 0x30, 0x2e, 0x30, 0x32, 0x31,
-+		0x31, 0x00, 0xea, 0x00, 0xf6, 0x01, 0x09
-+	},
-+	{	/* gamma 120 */
-+		MCS_MTP_SET3,
-+		0x00, 0x00, 0x00, 0x3d, 0x66, 0x68, 0x69, 0x69, 0x69, 0x28,
-+		0x28, 0x27, 0x28, 0x28, 0x27, 0x30, 0x2e, 0x2f, 0x31, 0x31,
-+		0x30, 0x00, 0xf9, 0x01, 0x05, 0x01, 0x1b
-+	},
-+	{	/* gamma 150 */
-+		MCS_MTP_SET3,
-+		0x00, 0x00, 0x00, 0x31, 0x51, 0x53, 0x66, 0x66, 0x67, 0x28,
-+		0x29, 0x27, 0x28, 0x27, 0x27, 0x2e, 0x2d, 0x2e, 0x31, 0x31,
-+		0x30, 0x01, 0x04, 0x01, 0x11, 0x01, 0x29
-+	},
-+	{	/* gamma 200 */
-+		MCS_MTP_SET3,
-+		0x00, 0x00, 0x00, 0x2f, 0x4f, 0x51, 0x67, 0x65, 0x65, 0x29,
-+		0x2a, 0x28, 0x27, 0x25, 0x26, 0x2d, 0x2c, 0x2c, 0x30, 0x30,
-+		0x30, 0x01, 0x14, 0x01, 0x23, 0x01, 0x3b
-+	},
-+	{	/* gamma 240 */
-+		MCS_MTP_SET3,
-+		0x00, 0x00, 0x00, 0x2c, 0x4d, 0x50, 0x65, 0x63, 0x64, 0x2a,
-+		0x2c, 0x29, 0x26, 0x24, 0x25, 0x2c, 0x2b, 0x2b, 0x30, 0x30,
-+		0x30, 0x01, 0x1e, 0x01, 0x2f, 0x01, 0x47
-+	},
-+	{	/* gamma 300 */
-+		MCS_MTP_SET3,
-+		0x00, 0x00, 0x00, 0x38, 0x61, 0x64, 0x65, 0x63, 0x64, 0x28,
-+		0x2a, 0x27, 0x26, 0x23, 0x25, 0x2b, 0x2b, 0x2a, 0x30, 0x2f,
-+		0x30, 0x01, 0x2d, 0x01, 0x3f, 0x01, 0x57
-+	}
-+};
-+
-+static inline struct s6e63j0x03 *panel_to_s6e63j0x03(struct drm_panel *panel)
-+{
-+	return container_of(panel, struct s6e63j0x03, panel);
-+}
-+
-+static inline ssize_t s6e63j0x03_dcs_write_seq(struct s6e63j0x03 *ctx,
-+					const void *seq, size_t len)
-+{
-+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-+
-+	return mipi_dsi_dcs_write_buffer(dsi, seq, len);
-+}
-+
-+#define s6e63j0x03_dcs_write_seq_static(ctx, seq...)			\
-+	({								\
-+		static const u8 d[] = { seq };				\
-+		s6e63j0x03_dcs_write_seq(ctx, d, ARRAY_SIZE(d));	\
-+	})
-+
-+static inline int s6e63j0x03_enable_lv2_command(struct s6e63j0x03 *ctx)
-+{
-+	return s6e63j0x03_dcs_write_seq_static(ctx, MCS_LEVEL2_KEY, 0x5a, 0x5a);
-+}
-+
-+static inline int s6e63j0x03_apply_mtp_key(struct s6e63j0x03 *ctx, bool on)
-+{
-+	if (on)
-+		return s6e63j0x03_dcs_write_seq_static(ctx,
-+				MCS_MTP_KEY, 0x5a, 0x5a);
-+
-+	return s6e63j0x03_dcs_write_seq_static(ctx, MCS_MTP_KEY, 0xa5, 0xa5);
-+}
-+
-+static int s6e63j0x03_power_on(struct s6e63j0x03 *ctx)
-+{
-+	int ret;
-+
-+	ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
-+	if (ret < 0)
-+		return ret;
-+
-+	msleep(30);
-+
-+	gpiod_set_value(ctx->reset_gpio, 1);
-+	usleep_range(1000, 2000);
-+	gpiod_set_value(ctx->reset_gpio, 0);
-+	usleep_range(5000, 6000);
-+
-+	return 0;
-+}
-+
-+static int s6e63j0x03_power_off(struct s6e63j0x03 *ctx)
-+{
-+	return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
-+}
-+
-+static unsigned int s6e63j0x03_get_brightness_index(unsigned int brightness)
-+{
-+	unsigned int index;
-+
-+	index = brightness / (MAX_BRIGHTNESS / NUM_GAMMA_STEPS);
-+
-+	if (index >= NUM_GAMMA_STEPS)
-+		index = NUM_GAMMA_STEPS - 1;
-+
-+	return index;
-+}
-+
-+static int s6e63j0x03_update_gamma(struct s6e63j0x03 *ctx,
-+					unsigned int brightness)
-+{
-+	struct backlight_device *bl_dev = ctx->bl_dev;
-+	unsigned int index = s6e63j0x03_get_brightness_index(brightness);
-+	int ret;
-+
-+	ret = s6e63j0x03_apply_mtp_key(ctx, true);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = s6e63j0x03_dcs_write_seq(ctx, gamma_tbl[index], GAMMA_CMD_CNT);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = s6e63j0x03_apply_mtp_key(ctx, false);
-+	if (ret < 0)
-+		return ret;
-+
-+	bl_dev->props.brightness = brightness;
-+
-+	return 0;
-+}
-+
-+static int s6e63j0x03_set_brightness(struct backlight_device *bl_dev)
-+{
-+	struct s6e63j0x03 *ctx = bl_get_data(bl_dev);
-+	unsigned int brightness = bl_dev->props.brightness;
-+
-+	return s6e63j0x03_update_gamma(ctx, brightness);
-+}
-+
-+static const struct backlight_ops s6e63j0x03_bl_ops = {
-+	.update_status = s6e63j0x03_set_brightness,
-+};
-+
-+static int s6e63j0x03_disable(struct drm_panel *panel)
-+{
-+	struct s6e63j0x03 *ctx = panel_to_s6e63j0x03(panel);
-+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-+	int ret;
-+
-+	ret = mipi_dsi_dcs_set_display_off(dsi);
-+	if (ret < 0)
-+		return ret;
-+
-+	ctx->bl_dev->props.power = FB_BLANK_NORMAL;
-+
-+	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
-+	if (ret < 0)
-+		return ret;
-+
-+	msleep(120);
-+
-+	return 0;
-+}
-+
-+static int s6e63j0x03_unprepare(struct drm_panel *panel)
-+{
-+	struct s6e63j0x03 *ctx = panel_to_s6e63j0x03(panel);
-+	int ret;
-+
-+	ret = s6e63j0x03_power_off(ctx);
-+	if (ret < 0)
-+		return ret;
-+
-+	ctx->bl_dev->props.power = FB_BLANK_POWERDOWN;
-+
-+	return 0;
-+}
-+
-+static int s6e63j0x03_panel_init(struct s6e63j0x03 *ctx)
-+{
-+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-+	int ret;
-+
-+	ret = s6e63j0x03_enable_lv2_command(ctx);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = s6e63j0x03_apply_mtp_key(ctx, true);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* set porch adjustment */
-+	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xf2, 0x1c, 0x28);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* set frame freq */
-+	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xb5, 0x00, 0x02, 0x00);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* set caset, paset */
-+	ret = mipi_dsi_dcs_set_column_address(dsi, FIRST_COLUMN,
-+		default_mode.hdisplay - 1 + FIRST_COLUMN);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = mipi_dsi_dcs_set_page_address(dsi, 0, default_mode.vdisplay - 1);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* set ltps timming 0, 1 */
-+	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xf8, 0x08, 0x08, 0x08, 0x17,
-+		0x00, 0x2a, 0x02, 0x26, 0x00, 0x00, 0x02, 0x00, 0x00);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xf7, 0x02);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* set param pos te_edge */
-+	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xb0, 0x01);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* set te rising edge */
-+	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xe2, 0x0f);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* set param pos default */
-+	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xb0, 0x00);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = s6e63j0x03_apply_mtp_key(ctx, false);
-+	if (ret < 0)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static int s6e63j0x03_prepare(struct drm_panel *panel)
-+{
-+	struct s6e63j0x03 *ctx = panel_to_s6e63j0x03(panel);
-+	int ret;
-+
-+	ret = s6e63j0x03_power_on(ctx);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = s6e63j0x03_panel_init(ctx);
-+	if (ret < 0)
-+		goto err;
-+
-+	ctx->bl_dev->props.power = FB_BLANK_NORMAL;
-+
-+	return 0;
-+
-+err:
-+	s6e63j0x03_power_off(ctx);
-+	return ret;
-+}
-+
-+static int s6e63j0x03_enable(struct drm_panel *panel)
-+{
-+	struct s6e63j0x03 *ctx = panel_to_s6e63j0x03(panel);
-+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-+	int ret;
-+
-+	msleep(120);
-+
-+	ret = s6e63j0x03_apply_mtp_key(ctx, true);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* set elvss_cond */
-+	ret = s6e63j0x03_dcs_write_seq_static(ctx, 0xb1, 0x00, 0x09);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* set pos */
-+	ret = s6e63j0x03_dcs_write_seq_static(ctx,
-+		MIPI_DCS_SET_ADDRESS_MODE, 0x40);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* set default white brightness */
-+	ret = mipi_dsi_dcs_set_display_brightness(dsi, 0x00ff);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* set white ctrl */
-+	ret = s6e63j0x03_dcs_write_seq_static(ctx,
-+		MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20);
-+	if (ret < 0)
-+		return ret;
-+
-+	/* set acl off */
-+	ret = s6e63j0x03_dcs_write_seq_static(ctx,
-+		MIPI_DCS_WRITE_POWER_SAVE, 0x00);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = s6e63j0x03_apply_mtp_key(ctx, false);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = mipi_dsi_dcs_set_display_on(dsi);
-+	if (ret < 0)
-+		return ret;
-+
-+	ctx->bl_dev->props.power = FB_BLANK_UNBLANK;
-+
-+	return 0;
-+}
-+
-+static int s6e63j0x03_get_modes(struct drm_panel *panel)
-+{
-+	struct drm_connector *connector = panel->connector;
-+	struct drm_display_mode *mode;
-+
-+	mode = drm_mode_duplicate(panel->drm, &default_mode);
-+	if (!mode) {
-+		DRM_ERROR("failed to add mode %ux%ux@%u\n",
-+			default_mode.hdisplay, default_mode.vdisplay,
-+			default_mode.vrefresh);
-+		return -ENOMEM;
-+	}
-+
-+	drm_mode_set_name(mode);
-+
-+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-+	drm_mode_probed_add(connector, mode);
-+
-+	connector->display_info.width_mm = 29;
-+	connector->display_info.height_mm = 29;
-+
-+	return 1;
-+}
-+
-+static const struct drm_panel_funcs s6e63j0x03_funcs = {
-+	.disable = s6e63j0x03_disable,
-+	.unprepare = s6e63j0x03_unprepare,
-+	.prepare = s6e63j0x03_prepare,
-+	.enable = s6e63j0x03_enable,
-+	.get_modes = s6e63j0x03_get_modes,
-+};
-+
-+static int s6e63j0x03_probe(struct mipi_dsi_device *dsi)
-+{
-+	struct device *dev = &dsi->dev;
-+	struct s6e63j0x03 *ctx;
-+	int ret;
-+
-+	ctx = devm_kzalloc(dev, sizeof(struct s6e63j0x03), GFP_KERNEL);
-+	if (!ctx)
-+		return -ENOMEM;
-+
-+	mipi_dsi_set_drvdata(dsi, ctx);
-+
-+	ctx->dev = dev;
-+
-+	dsi->lanes = 1;
-+	dsi->format = MIPI_DSI_FMT_RGB888;
-+	dsi->mode_flags = MIPI_DSI_MODE_EOT_PACKET;
-+
-+	ctx->supplies[0].supply = "vdd3";
-+	ctx->supplies[1].supply = "vci";
-+	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
-+				      ctx->supplies);
-+	if (ret < 0) {
-+		dev_err(dev, "failed to get regulators: %d\n", ret);
-+		return ret;
-+	}
-+
-+	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
-+	if (IS_ERR(ctx->reset_gpio)) {
-+		dev_err(dev, "cannot get reset-gpio: %ld\n",
-+				PTR_ERR(ctx->reset_gpio));
-+		return PTR_ERR(ctx->reset_gpio);
-+	}
-+
-+	drm_panel_init(&ctx->panel);
-+	ctx->panel.dev = dev;
-+	ctx->panel.funcs = &s6e63j0x03_funcs;
-+
-+	ctx->bl_dev = backlight_device_register("s6e63j0x03", dev, ctx,
-+						&s6e63j0x03_bl_ops, NULL);
-+	if (IS_ERR(ctx->bl_dev)) {
-+		dev_err(dev, "failed to register backlight device\n");
-+		return PTR_ERR(ctx->bl_dev);
-+	}
-+
-+	ctx->bl_dev->props.max_brightness = MAX_BRIGHTNESS;
-+	ctx->bl_dev->props.brightness = DEFAULT_BRIGHTNESS;
-+	ctx->bl_dev->props.power = FB_BLANK_POWERDOWN;
-+
-+	ret = drm_panel_add(&ctx->panel);
-+	if (ret < 0)
-+		goto unregister_backlight;
-+
-+	ret = mipi_dsi_attach(dsi);
-+	if (ret < 0)
-+		goto remove_panel;
-+
-+	return ret;
-+
-+remove_panel:
-+	drm_panel_remove(&ctx->panel);
-+
-+unregister_backlight:
-+	backlight_device_unregister(ctx->bl_dev);
-+
-+	return ret;
-+}
-+
-+static int s6e63j0x03_remove(struct mipi_dsi_device *dsi)
-+{
-+	struct s6e63j0x03 *ctx = mipi_dsi_get_drvdata(dsi);
-+
-+	mipi_dsi_detach(dsi);
-+	drm_panel_remove(&ctx->panel);
-+
-+	backlight_device_unregister(ctx->bl_dev);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id s6e63j0x03_of_match[] = {
-+	{ .compatible = "samsung,s6e63j0x03" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, s6e63j0x03_of_match);
-+
-+static struct mipi_dsi_driver s6e63j0x03_driver = {
-+	.probe = s6e63j0x03_probe,
-+	.remove = s6e63j0x03_remove,
-+	.driver = {
-+		.name = "panel_samsung_s6e63j0x03",
-+		.of_match_table = s6e63j0x03_of_match,
-+	},
-+};
-+module_mipi_dsi_driver(s6e63j0x03_driver);
-+
-+MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>");
-+MODULE_AUTHOR("Hoegeun Kwon <hoegeun.kwon@samsung.com>");
-+MODULE_DESCRIPTION("MIPI-DSI based s6e63j0x03 AMOLED LCD Panel Driver");
-+MODULE_LICENSE("GPL v2");
---- linux-4.14/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c.0130~	2017-12-14 06:39:58.517903639 +0100
-+++ linux-4.14/drivers/gpu/drm/panel/panel-seiko-43wvf1g.c	2017-12-14 06:39:58.517903639 +0100
-@@ -0,0 +1,372 @@
-+/*
-+ * Copyright (C) 2017 NXP Semiconductors.
-+ * Author: Marco Franchi <marco.franchi@nxp.com>
-+ *
-+ * Based on Panel Simple driver by Thierry Reding <treding@nvidia.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License version
-+ * 2 as published by the Free Software Foundation.
-+ */
-+
-+#include <linux/backlight.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/regulator/consumer.h>
-+
-+#include <drm/drmP.h>
-+#include <drm/drm_crtc.h>
-+#include <drm/drm_panel.h>
-+
-+#include <video/display_timing.h>
-+#include <video/videomode.h>
-+
-+struct seiko_panel_desc {
-+	const struct drm_display_mode *modes;
-+	unsigned int num_modes;
-+	const struct display_timing *timings;
-+	unsigned int num_timings;
-+
-+	unsigned int bpc;
-+
-+	/**
-+	 * @width: width (in millimeters) of the panel's active display area
-+	 * @height: height (in millimeters) of the panel's active display area
-+	 */
-+	struct {
-+		unsigned int width;
-+		unsigned int height;
-+	} size;
-+
-+	u32 bus_format;
-+	u32 bus_flags;
-+};
-+
-+struct seiko_panel {
-+	struct drm_panel base;
-+	bool prepared;
-+	bool enabled;
-+	const struct seiko_panel_desc *desc;
-+	struct backlight_device *backlight;
-+	struct regulator *dvdd;
-+	struct regulator *avdd;
-+};
-+
-+static inline struct seiko_panel *to_seiko_panel(struct drm_panel *panel)
-+{
-+	return container_of(panel, struct seiko_panel, base);
-+}
-+
-+static int seiko_panel_get_fixed_modes(struct seiko_panel *panel)
-+{
-+	struct drm_connector *connector = panel->base.connector;
-+	struct drm_device *drm = panel->base.drm;
-+	struct drm_display_mode *mode;
-+	unsigned int i, num = 0;
-+
-+	if (!panel->desc)
-+		return 0;
-+
-+	for (i = 0; i < panel->desc->num_timings; i++) {
-+		const struct display_timing *dt = &panel->desc->timings[i];
-+		struct videomode vm;
-+
-+		videomode_from_timing(dt, &vm);
-+		mode = drm_mode_create(drm);
-+		if (!mode) {
-+			dev_err(drm->dev, "failed to add mode %ux%u\n",
-+				dt->hactive.typ, dt->vactive.typ);
-+			continue;
-+		}
-+
-+		drm_display_mode_from_videomode(&vm, mode);
-+
-+		mode->type |= DRM_MODE_TYPE_DRIVER;
-+
-+		if (panel->desc->num_timings == 1)
-+			mode->type |= DRM_MODE_TYPE_PREFERRED;
-+
-+		drm_mode_probed_add(connector, mode);
-+		num++;
-+	}
-+
-+	for (i = 0; i < panel->desc->num_modes; i++) {
-+		const struct drm_display_mode *m = &panel->desc->modes[i];
-+
-+		mode = drm_mode_duplicate(drm, m);
-+		if (!mode) {
-+			dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
-+				m->hdisplay, m->vdisplay, m->vrefresh);
-+			continue;
-+		}
-+
-+		mode->type |= DRM_MODE_TYPE_DRIVER;
-+
-+		if (panel->desc->num_modes == 1)
-+			mode->type |= DRM_MODE_TYPE_PREFERRED;
-+
-+		drm_mode_set_name(mode);
-+
-+		drm_mode_probed_add(connector, mode);
-+		num++;
-+	}
-+
-+	connector->display_info.bpc = panel->desc->bpc;
-+	connector->display_info.width_mm = panel->desc->size.width;
-+	connector->display_info.height_mm = panel->desc->size.height;
-+	if (panel->desc->bus_format)
-+		drm_display_info_set_bus_formats(&connector->display_info,
-+						 &panel->desc->bus_format, 1);
-+	connector->display_info.bus_flags = panel->desc->bus_flags;
-+
-+	return num;
-+}
-+
-+static int seiko_panel_disable(struct drm_panel *panel)
-+{
-+	struct seiko_panel *p = to_seiko_panel(panel);
-+
-+	if (!p->enabled)
-+		return 0;
-+
-+	if (p->backlight) {
-+		p->backlight->props.power = FB_BLANK_POWERDOWN;
-+		p->backlight->props.state |= BL_CORE_FBBLANK;
-+		backlight_update_status(p->backlight);
-+	}
-+
-+	p->enabled = false;
-+
-+	return 0;
-+}
-+
-+static int seiko_panel_unprepare(struct drm_panel *panel)
-+{
-+	struct seiko_panel *p = to_seiko_panel(panel);
-+
-+	if (!p->prepared)
-+		return 0;
-+
-+	regulator_disable(p->avdd);
-+
-+	/* Add a 100ms delay as per the panel datasheet */
-+	msleep(100);
-+
-+	regulator_disable(p->dvdd);
-+
-+	p->prepared = false;
-+
-+	return 0;
-+}
-+
-+static int seiko_panel_prepare(struct drm_panel *panel)
-+{
-+	struct seiko_panel *p = to_seiko_panel(panel);
-+	int err;
-+
-+	if (p->prepared)
-+		return 0;
-+
-+	err = regulator_enable(p->dvdd);
-+	if (err < 0) {
-+		dev_err(panel->dev, "failed to enable dvdd: %d\n", err);
-+		return err;
-+	}
-+
-+	/* Add a 100ms delay as per the panel datasheet */
-+	msleep(100);
-+
-+	err = regulator_enable(p->avdd);
-+	if (err < 0) {
-+		dev_err(panel->dev, "failed to enable avdd: %d\n", err);
-+		goto disable_dvdd;
-+	}
-+
-+	p->prepared = true;
-+
-+	return 0;
-+
-+disable_dvdd:
-+	regulator_disable(p->dvdd);
-+	return err;
-+}
-+
-+static int seiko_panel_enable(struct drm_panel *panel)
-+{
-+	struct seiko_panel *p = to_seiko_panel(panel);
-+
-+	if (p->enabled)
-+		return 0;
-+
-+	if (p->backlight) {
-+		p->backlight->props.state &= ~BL_CORE_FBBLANK;
-+		p->backlight->props.power = FB_BLANK_UNBLANK;
-+		backlight_update_status(p->backlight);
-+	}
-+
-+	p->enabled = true;
-+
-+	return 0;
-+}
-+
-+static int seiko_panel_get_modes(struct drm_panel *panel)
-+{
-+	struct seiko_panel *p = to_seiko_panel(panel);
-+
-+	/* add hard-coded panel modes */
-+	return seiko_panel_get_fixed_modes(p);
-+}
-+
-+static int seiko_panel_get_timings(struct drm_panel *panel,
-+				    unsigned int num_timings,
-+				    struct display_timing *timings)
-+{
-+	struct seiko_panel *p = to_seiko_panel(panel);
-+	unsigned int i;
-+
-+	if (p->desc->num_timings < num_timings)
-+		num_timings = p->desc->num_timings;
-+
-+	if (timings)
-+		for (i = 0; i < num_timings; i++)
-+			timings[i] = p->desc->timings[i];
-+
-+	return p->desc->num_timings;
-+}
-+
-+static const struct drm_panel_funcs seiko_panel_funcs = {
-+	.disable = seiko_panel_disable,
-+	.unprepare = seiko_panel_unprepare,
-+	.prepare = seiko_panel_prepare,
-+	.enable = seiko_panel_enable,
-+	.get_modes = seiko_panel_get_modes,
-+	.get_timings = seiko_panel_get_timings,
-+};
-+
-+static int seiko_panel_probe(struct device *dev,
-+					const struct seiko_panel_desc *desc)
-+{
-+	struct device_node *backlight;
-+	struct seiko_panel *panel;
-+	int err;
-+
-+	panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
-+	if (!panel)
-+		return -ENOMEM;
-+
-+	panel->enabled = false;
-+	panel->prepared = false;
-+	panel->desc = desc;
-+
-+	panel->dvdd = devm_regulator_get(dev, "dvdd");
-+	if (IS_ERR(panel->dvdd))
-+		return PTR_ERR(panel->dvdd);
-+
-+	panel->avdd = devm_regulator_get(dev, "avdd");
-+	if (IS_ERR(panel->avdd))
-+		return PTR_ERR(panel->avdd);
-+
-+	backlight = of_parse_phandle(dev->of_node, "backlight", 0);
-+	if (backlight) {
-+		panel->backlight = of_find_backlight_by_node(backlight);
-+		of_node_put(backlight);
-+
-+		if (!panel->backlight)
-+			return -EPROBE_DEFER;
-+	}
-+
-+	drm_panel_init(&panel->base);
-+	panel->base.dev = dev;
-+	panel->base.funcs = &seiko_panel_funcs;
-+
-+	err = drm_panel_add(&panel->base);
-+	if (err < 0)
-+		return err;
-+
-+	dev_set_drvdata(dev, panel);
-+
-+	return 0;
-+}
-+
-+static int seiko_panel_remove(struct platform_device *pdev)
-+{
-+	struct seiko_panel *panel = dev_get_drvdata(&pdev->dev);
-+
-+	drm_panel_detach(&panel->base);
-+	drm_panel_remove(&panel->base);
-+
-+	seiko_panel_disable(&panel->base);
-+
-+	if (panel->backlight)
-+		put_device(&panel->backlight->dev);
-+
-+	return 0;
-+}
-+
-+static void seiko_panel_shutdown(struct platform_device *pdev)
-+{
-+	struct seiko_panel *panel = dev_get_drvdata(&pdev->dev);
-+
-+	seiko_panel_disable(&panel->base);
-+}
-+
-+static const struct display_timing seiko_43wvf1g_timing = {
-+	.pixelclock = { 33500000, 33500000, 33500000 },
-+	.hactive = { 800, 800, 800 },
-+	.hfront_porch = {  164, 164, 164 },
-+	.hback_porch = { 89, 89, 89 },
-+	.hsync_len = { 10, 10, 10 },
-+	.vactive = { 480, 480, 480 },
-+	.vfront_porch = { 10, 10, 10 },
-+	.vback_porch = { 23, 23, 23 },
-+	.vsync_len = { 10, 10, 10 },
-+	.flags = DISPLAY_FLAGS_DE_LOW,
-+};
-+
-+static const struct seiko_panel_desc seiko_43wvf1g = {
-+	.timings = &seiko_43wvf1g_timing,
-+	.num_timings = 1,
-+	.bpc = 8,
-+	.size = {
-+		.width = 93,
-+		.height = 57,
-+	},
-+	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
-+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
-+};
-+
-+static const struct of_device_id platform_of_match[] = {
-+	{
-+		.compatible = "sii,43wvf1g",
-+		.data = &seiko_43wvf1g,
-+	}, {
-+		/* sentinel */
-+	}
-+};
-+MODULE_DEVICE_TABLE(of, platform_of_match);
-+
-+static int seiko_panel_platform_probe(struct platform_device *pdev)
-+{
-+	const struct of_device_id *id;
-+
-+	id = of_match_node(platform_of_match, pdev->dev.of_node);
-+	if (!id)
-+		return -ENODEV;
-+
-+	return seiko_panel_probe(&pdev->dev, id->data);
-+}
-+
-+static struct platform_driver seiko_panel_platform_driver = {
-+	.driver = {
-+		.name = "seiko_panel",
-+		.of_match_table = platform_of_match,
-+	},
-+	.probe = seiko_panel_platform_probe,
-+	.remove = seiko_panel_remove,
-+	.shutdown = seiko_panel_shutdown,
-+};
-+module_platform_driver(seiko_panel_platform_driver);
-+
-+MODULE_AUTHOR("Marco Franchi <marco.franchi@nxp.com");
-+MODULE_DESCRIPTION("Seiko 43WVF1G panel driver");
-+MODULE_LICENSE("GPL v2");
---- linux-4.14/drivers/gpu/drm/panel/panel-simple.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/panel/panel-simple.c	2017-12-14 06:39:58.517903639 +0100
-@@ -187,8 +187,7 @@ static int panel_simple_unprepare(struct
- 	if (!p->prepared)
- 		return 0;
- 
--	if (p->enable_gpio)
--		gpiod_set_value_cansleep(p->enable_gpio, 0);
-+	gpiod_set_value_cansleep(p->enable_gpio, 0);
- 
- 	regulator_disable(p->supply);
- 
-@@ -214,8 +213,7 @@ static int panel_simple_prepare(struct d
- 		return err;
- 	}
- 
--	if (p->enable_gpio)
--		gpiod_set_value_cansleep(p->enable_gpio, 1);
-+	gpiod_set_value_cansleep(p->enable_gpio, 1);
- 
- 	if (p->desc->delay.prepare)
- 		msleep(p->desc->delay.prepare);
-@@ -315,7 +313,8 @@ static int panel_simple_probe(struct dev
- 						     GPIOD_OUT_LOW);
- 	if (IS_ERR(panel->enable_gpio)) {
- 		err = PTR_ERR(panel->enable_gpio);
--		dev_err(dev, "failed to request GPIO: %d\n", err);
-+		if (err != -EPROBE_DEFER)
-+			dev_err(dev, "failed to request GPIO: %d\n", err);
- 		return err;
- 	}
- 
-@@ -1524,8 +1523,8 @@ static const struct panel_desc olimex_lc
- 	.modes = &olimex_lcd_olinuxino_43ts_mode,
- 	.num_modes = 1,
- 	.size = {
--		.width = 105,
--		.height = 67,
-+		.width = 95,
-+		.height = 54,
- 	},
- 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
- };
---- linux-4.14/drivers/gpu/drm/pl111/Kconfig.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/pl111/Kconfig	2017-12-14 06:39:58.517903639 +0100
-@@ -6,7 +6,8 @@ config DRM_PL111
- 	select DRM_KMS_HELPER
- 	select DRM_KMS_CMA_HELPER
- 	select DRM_GEM_CMA_HELPER
--	select DRM_PANEL
-+	select DRM_BRIDGE
-+	select DRM_PANEL_BRIDGE
- 	select VT_HW_CONSOLE_BINDING if FRAMEBUFFER_CONSOLE
- 	help
- 	  Choose this option for DRM support for the PL111 CLCD controller.
---- linux-4.14/drivers/gpu/drm/pl111/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/pl111/Makefile	2017-12-14 06:39:58.517903639 +0100
-@@ -1,6 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0
--pl111_drm-y +=	pl111_connector.o \
--		pl111_display.o \
-+pl111_drm-y +=	pl111_display.o \
-+		pl111_versatile.o \
- 		pl111_drv.o
- 
- pl111_drm-$(CONFIG_DEBUG_FS) += pl111_debugfs.o
---- linux-4.14/drivers/gpu/drm/pl111/pl111_debugfs.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/pl111/pl111_debugfs.c	2017-12-14 06:39:58.517903639 +0100
-@@ -22,8 +22,14 @@ static const struct {
- 	REGDEF(CLCD_TIM2),
- 	REGDEF(CLCD_TIM3),
- 	REGDEF(CLCD_UBAS),
-+	REGDEF(CLCD_LBAS),
- 	REGDEF(CLCD_PL111_CNTL),
- 	REGDEF(CLCD_PL111_IENB),
-+	REGDEF(CLCD_PL111_RIS),
-+	REGDEF(CLCD_PL111_MIS),
-+	REGDEF(CLCD_PL111_ICR),
-+	REGDEF(CLCD_PL111_UCUR),
-+	REGDEF(CLCD_PL111_LCUR),
- };
- 
- int pl111_debugfs_regs(struct seq_file *m, void *unused)
---- linux-4.14/drivers/gpu/drm/pl111/pl111_display.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/pl111/pl111_display.c	2017-12-14 06:39:58.518903639 +0100
-@@ -21,7 +21,6 @@
- #include <linux/of_graph.h>
- 
- #include <drm/drmP.h>
--#include <drm/drm_panel.h>
- #include <drm/drm_gem_cma_helper.h>
- #include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drm_fb_cma_helper.h>
-@@ -94,7 +93,7 @@ static void pl111_display_enable(struct
- 	struct pl111_drm_dev_private *priv = drm->dev_private;
- 	const struct drm_display_mode *mode = &cstate->mode;
- 	struct drm_framebuffer *fb = plane->state->fb;
--	struct drm_connector *connector = &priv->connector.connector;
-+	struct drm_connector *connector = priv->connector;
- 	u32 cntl;
- 	u32 ppl, hsw, hfp, hbp;
- 	u32 lpp, vsw, vfp, vbp;
-@@ -156,10 +155,8 @@ static void pl111_display_enable(struct
- 
- 	writel(0, priv->regs + CLCD_TIM3);
- 
--	drm_panel_prepare(priv->connector.panel);
--
--	/* Enable and Power Up */
--	cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDPWR | CNTL_LCDVCOMP(1);
-+	/* Hard-code TFT panel */
-+	cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1);
- 
- 	/* Note that the the hardware's format reader takes 'r' from
- 	 * the low bit, while DRM formats list channels from high bit
-@@ -202,9 +199,21 @@ static void pl111_display_enable(struct
- 		break;
- 	}
- 
--	writel(cntl, priv->regs + CLCD_PL111_CNTL);
-+	/* Power sequence: first enable and chill */
-+	writel(cntl, priv->regs + priv->ctrl);
-+
-+	/*
-+	 * We expect this delay to stabilize the contrast
-+	 * voltage Vee as stipulated by the manual
-+	 */
-+	msleep(20);
-+
-+	if (priv->variant_display_enable)
-+		priv->variant_display_enable(drm, fb->format->format);
- 
--	drm_panel_enable(priv->connector.panel);
-+	/* Power Up */
-+	cntl |= CNTL_LCDPWR;
-+	writel(cntl, priv->regs + priv->ctrl);
- 
- 	drm_crtc_vblank_on(crtc);
- }
-@@ -214,15 +223,28 @@ void pl111_display_disable(struct drm_si
- 	struct drm_crtc *crtc = &pipe->crtc;
- 	struct drm_device *drm = crtc->dev;
- 	struct pl111_drm_dev_private *priv = drm->dev_private;
-+	u32 cntl;
- 
- 	drm_crtc_vblank_off(crtc);
- 
--	drm_panel_disable(priv->connector.panel);
-+	/* Power Down */
-+	cntl = readl(priv->regs + priv->ctrl);
-+	if (cntl & CNTL_LCDPWR) {
-+		cntl &= ~CNTL_LCDPWR;
-+		writel(cntl, priv->regs + priv->ctrl);
-+	}
-+
-+	/*
-+	 * We expect this delay to stabilize the contrast voltage Vee as
-+	 * stipulated by the manual
-+	 */
-+	msleep(20);
- 
--	/* Disable and Power Down */
--	writel(0, priv->regs + CLCD_PL111_CNTL);
-+	if (priv->variant_display_disable)
-+		priv->variant_display_disable(drm);
- 
--	drm_panel_unprepare(priv->connector.panel);
-+	/* Disable */
-+	writel(0, priv->regs + priv->ctrl);
- 
- 	clk_disable_unprepare(priv->clk);
- }
-@@ -260,7 +282,7 @@ int pl111_enable_vblank(struct drm_devic
- {
- 	struct pl111_drm_dev_private *priv = drm->dev_private;
- 
--	writel(CLCD_IRQ_NEXTBASE_UPDATE, priv->regs + CLCD_PL111_IENB);
-+	writel(CLCD_IRQ_NEXTBASE_UPDATE, priv->regs + priv->ienb);
- 
- 	return 0;
- }
-@@ -269,7 +291,7 @@ void pl111_disable_vblank(struct drm_dev
- {
- 	struct pl111_drm_dev_private *priv = drm->dev_private;
- 
--	writel(0, priv->regs + CLCD_PL111_IENB);
-+	writel(0, priv->regs + priv->ienb);
- }
- 
- static int pl111_display_prepare_fb(struct drm_simple_display_pipe *pipe,
-@@ -413,22 +435,6 @@ int pl111_display_init(struct drm_device
- 	struct device_node *endpoint;
- 	u32 tft_r0b0g0[3];
- 	int ret;
--	static const u32 formats[] = {
--		DRM_FORMAT_ABGR8888,
--		DRM_FORMAT_XBGR8888,
--		DRM_FORMAT_ARGB8888,
--		DRM_FORMAT_XRGB8888,
--		DRM_FORMAT_BGR565,
--		DRM_FORMAT_RGB565,
--		DRM_FORMAT_ABGR1555,
--		DRM_FORMAT_XBGR1555,
--		DRM_FORMAT_ARGB1555,
--		DRM_FORMAT_XRGB1555,
--		DRM_FORMAT_ABGR4444,
--		DRM_FORMAT_XBGR4444,
--		DRM_FORMAT_ARGB4444,
--		DRM_FORMAT_XRGB4444,
--	};
- 
- 	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
- 	if (!endpoint)
-@@ -444,21 +450,16 @@ int pl111_display_init(struct drm_device
- 	}
- 	of_node_put(endpoint);
- 
--	if (tft_r0b0g0[0] != 0 ||
--	    tft_r0b0g0[1] != 8 ||
--	    tft_r0b0g0[2] != 16) {
--		dev_err(dev, "arm,pl11x,tft-r0g0b0-pads != [0,8,16] not yet supported\n");
--		return -EINVAL;
--	}
--
- 	ret = pl111_init_clock_divider(drm);
- 	if (ret)
- 		return ret;
- 
- 	ret = drm_simple_display_pipe_init(drm, &priv->pipe,
- 					   &pl111_display_funcs,
--					   formats, ARRAY_SIZE(formats),
--					   NULL, &priv->connector.connector);
-+					   priv->variant->formats,
-+					   priv->variant->nformats,
-+					   NULL,
-+					   priv->connector);
- 	if (ret)
- 		return ret;
- 
---- linux-4.14/drivers/gpu/drm/pl111/pl111_drm.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/pl111/pl111_drm.h	2017-12-14 06:39:58.518903639 +0100
-@@ -21,25 +21,43 @@
- 
- #include <drm/drm_gem.h>
- #include <drm/drm_simple_kms_helper.h>
-+#include <drm/drm_connector.h>
-+#include <drm/drm_encoder.h>
-+#include <drm/drm_panel.h>
-+#include <drm/drm_bridge.h>
- #include <linux/clk-provider.h>
-+#include <linux/interrupt.h>
- 
- #define CLCD_IRQ_NEXTBASE_UPDATE BIT(2)
- 
- struct drm_minor;
- 
--struct pl111_drm_connector {
--	struct drm_connector connector;
--	struct drm_panel *panel;
-+/**
-+ * struct pl111_variant_data - encodes IP differences
-+ * @name: the name of this variant
-+ * @is_pl110: this is the early PL110 variant
-+ * @formats: array of supported pixel formats on this variant
-+ * @nformats: the length of the array of supported pixel formats
-+ */
-+struct pl111_variant_data {
-+	const char *name;
-+	bool is_pl110;
-+	const u32 *formats;
-+	unsigned int nformats;
- };
- 
- struct pl111_drm_dev_private {
- 	struct drm_device *drm;
- 
--	struct pl111_drm_connector connector;
-+	struct drm_connector *connector;
-+	struct drm_panel *panel;
-+	struct drm_bridge *bridge;
- 	struct drm_simple_display_pipe pipe;
- 	struct drm_fbdev_cma *fbdev;
- 
- 	void *regs;
-+	u32 ienb;
-+	u32 ctrl;
- 	/* The pixel clock (a reference to our clock divider off of CLCDCLK). */
- 	struct clk *clk;
- 	/* pl111's internal clock divider. */
-@@ -48,20 +66,15 @@ struct pl111_drm_dev_private {
- 	 * subsystem and pl111_display_enable().
- 	 */
- 	spinlock_t tim2_lock;
-+	const struct pl111_variant_data *variant;
-+	void (*variant_display_enable) (struct drm_device *drm, u32 format);
-+	void (*variant_display_disable) (struct drm_device *drm);
- };
- 
--#define to_pl111_connector(x) \
--	container_of(x, struct pl111_drm_connector, connector)
--
- int pl111_display_init(struct drm_device *dev);
- int pl111_enable_vblank(struct drm_device *drm, unsigned int crtc);
- void pl111_disable_vblank(struct drm_device *drm, unsigned int crtc);
- irqreturn_t pl111_irq(int irq, void *data);
--int pl111_connector_init(struct drm_device *dev);
--int pl111_encoder_init(struct drm_device *dev);
--int pl111_dumb_create(struct drm_file *file_priv,
--		      struct drm_device *dev,
--		      struct drm_mode_create_dumb *args);
- int pl111_debugfs_init(struct drm_minor *minor);
- 
- #endif /* _PL111_DRM_H_ */
---- linux-4.14/drivers/gpu/drm/pl111/pl111_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/pl111/pl111_drv.c	2017-12-14 06:39:58.518903639 +0100
-@@ -41,9 +41,6 @@
-  * - Fix race between setting plane base address and getting IRQ for
-  *   vsync firing the pageflip completion.
-  *
-- * - Expose the correct set of formats we can support based on the
-- *   "arm,pl11x,tft-r0g0b0-pads" DT property.
-- *
-  * - Use the "max-memory-bandwidth" DT property to filter the
-  *   supported formats.
-  *
-@@ -68,8 +65,12 @@
- #include <drm/drm_gem_cma_helper.h>
- #include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drm_fb_cma_helper.h>
-+#include <drm/drm_of.h>
-+#include <drm/drm_bridge.h>
-+#include <drm/drm_panel.h>
- 
- #include "pl111_drm.h"
-+#include "pl111_versatile.h"
- 
- #define DRIVER_DESC      "DRM module for PL111"
- 
-@@ -83,6 +84,8 @@ static int pl111_modeset_init(struct drm
- {
- 	struct drm_mode_config *mode_config;
- 	struct pl111_drm_dev_private *priv = dev->dev_private;
-+	struct drm_panel *panel;
-+	struct drm_bridge *bridge;
- 	int ret = 0;
- 
- 	drm_mode_config_init(dev);
-@@ -93,34 +96,43 @@ static int pl111_modeset_init(struct drm
- 	mode_config->min_height = 1;
- 	mode_config->max_height = 768;
- 
--	ret = pl111_connector_init(dev);
--	if (ret) {
--		dev_err(dev->dev, "Failed to create pl111_drm_connector\n");
--		goto out_config;
--	}
--
--	/* Don't actually attach if we didn't find a drm_panel
--	 * attached to us.  This will allow a kernel to include both
--	 * the fbdev pl111 driver and this one, and choose between
--	 * them based on which subsystem has support for the panel.
--	 */
--	if (!priv->connector.panel) {
--		dev_info(dev->dev,
--			 "Disabling due to lack of DRM panel device.\n");
--		ret = -ENODEV;
--		goto out_config;
-+	ret = drm_of_find_panel_or_bridge(dev->dev->of_node,
-+					  0, 0, &panel, &bridge);
-+	if (ret && ret != -ENODEV)
-+		return ret;
-+	if (panel) {
-+		bridge = drm_panel_bridge_add(panel,
-+					      DRM_MODE_CONNECTOR_Unknown);
-+		if (IS_ERR(bridge)) {
-+			ret = PTR_ERR(bridge);
-+			goto out_config;
-+		}
-+		/*
-+		 * TODO: when we are using a different bridge than a panel
-+		 * (such as a dumb VGA connector) we need to devise a different
-+		 * method to get the connector out of the bridge.
-+		 */
- 	}
- 
- 	ret = pl111_display_init(dev);
- 	if (ret != 0) {
- 		dev_err(dev->dev, "Failed to init display\n");
--		goto out_config;
-+		goto out_bridge;
- 	}
- 
-+	ret = drm_simple_display_pipe_attach_bridge(&priv->pipe,
-+						    bridge);
-+	if (ret)
-+		return ret;
-+
-+	priv->bridge = bridge;
-+	priv->panel = panel;
-+	priv->connector = panel->connector;
-+
- 	ret = drm_vblank_init(dev, 1);
- 	if (ret != 0) {
- 		dev_err(dev->dev, "Failed to init vblank\n");
--		goto out_config;
-+		goto out_bridge;
- 	}
- 
- 	drm_mode_config_reset(dev);
-@@ -132,6 +144,9 @@ static int pl111_modeset_init(struct drm
- 
- 	goto finish;
- 
-+out_bridge:
-+	if (panel)
-+		drm_panel_bridge_remove(bridge);
- out_config:
- 	drm_mode_config_cleanup(dev);
- finish:
-@@ -183,6 +198,7 @@ static int pl111_amba_probe(struct amba_
- {
- 	struct device *dev = &amba_dev->dev;
- 	struct pl111_drm_dev_private *priv;
-+	struct pl111_variant_data *variant = id->data;
- 	struct drm_device *drm;
- 	int ret;
- 
-@@ -196,6 +212,33 @@ static int pl111_amba_probe(struct amba_
- 	amba_set_drvdata(amba_dev, drm);
- 	priv->drm = drm;
- 	drm->dev_private = priv;
-+	priv->variant = variant;
-+
-+	/*
-+	 * The PL110 and PL111 variants have two registers
-+	 * swapped: interrupt enable and control. For this reason
-+	 * we use offsets that we can change per variant.
-+	 */
-+	if (variant->is_pl110) {
-+		/*
-+		 * The ARM Versatile boards are even more special:
-+		 * their PrimeCell ID say they are PL110 but the
-+		 * control and interrupt enable registers are anyway
-+		 * swapped to the PL111 order so they are not following
-+		 * the PL110 datasheet.
-+		 */
-+		if (of_machine_is_compatible("arm,versatile-ab") ||
-+		    of_machine_is_compatible("arm,versatile-pb")) {
-+			priv->ienb = CLCD_PL111_IENB;
-+			priv->ctrl = CLCD_PL111_CNTL;
-+		} else {
-+			priv->ienb = CLCD_PL110_IENB;
-+			priv->ctrl = CLCD_PL110_CNTL;
-+		}
-+	} else {
-+		priv->ienb = CLCD_PL111_IENB;
-+		priv->ctrl = CLCD_PL111_CNTL;
-+	}
- 
- 	priv->regs = devm_ioremap_resource(dev, &amba_dev->res);
- 	if (IS_ERR(priv->regs)) {
-@@ -204,15 +247,19 @@ static int pl111_amba_probe(struct amba_
- 	}
- 
- 	/* turn off interrupts before requesting the irq */
--	writel(0, priv->regs + CLCD_PL111_IENB);
-+	writel(0, priv->regs + priv->ienb);
- 
- 	ret = devm_request_irq(dev, amba_dev->irq[0], pl111_irq, 0,
--			       "pl111", priv);
-+			       variant->name, priv);
- 	if (ret != 0) {
- 		dev_err(dev, "%s failed irq %d\n", __func__, ret);
- 		return ret;
- 	}
- 
-+	ret = pl111_versatile_init(dev, priv);
-+	if (ret)
-+		goto dev_unref;
-+
- 	ret = pl111_modeset_init(drm);
- 	if (ret != 0)
- 		goto dev_unref;
-@@ -236,16 +283,70 @@ static int pl111_amba_remove(struct amba
- 	drm_dev_unregister(drm);
- 	if (priv->fbdev)
- 		drm_fbdev_cma_fini(priv->fbdev);
-+	if (priv->panel)
-+		drm_panel_bridge_remove(priv->bridge);
- 	drm_mode_config_cleanup(drm);
- 	drm_dev_unref(drm);
- 
- 	return 0;
- }
- 
--static struct amba_id pl111_id_table[] = {
-+/*
-+ * This variant exist in early versions like the ARM Integrator
-+ * and this version lacks the 565 and 444 pixel formats.
-+ */
-+static const u32 pl110_pixel_formats[] = {
-+	DRM_FORMAT_ABGR8888,
-+	DRM_FORMAT_XBGR8888,
-+	DRM_FORMAT_ARGB8888,
-+	DRM_FORMAT_XRGB8888,
-+	DRM_FORMAT_ABGR1555,
-+	DRM_FORMAT_XBGR1555,
-+	DRM_FORMAT_ARGB1555,
-+	DRM_FORMAT_XRGB1555,
-+};
-+
-+static const struct pl111_variant_data pl110_variant = {
-+	.name = "PL110",
-+	.is_pl110 = true,
-+	.formats = pl110_pixel_formats,
-+	.nformats = ARRAY_SIZE(pl110_pixel_formats),
-+};
-+
-+/* RealView, Versatile Express etc use this modern variant */
-+static const u32 pl111_pixel_formats[] = {
-+	DRM_FORMAT_ABGR8888,
-+	DRM_FORMAT_XBGR8888,
-+	DRM_FORMAT_ARGB8888,
-+	DRM_FORMAT_XRGB8888,
-+	DRM_FORMAT_BGR565,
-+	DRM_FORMAT_RGB565,
-+	DRM_FORMAT_ABGR1555,
-+	DRM_FORMAT_XBGR1555,
-+	DRM_FORMAT_ARGB1555,
-+	DRM_FORMAT_XRGB1555,
-+	DRM_FORMAT_ABGR4444,
-+	DRM_FORMAT_XBGR4444,
-+	DRM_FORMAT_ARGB4444,
-+	DRM_FORMAT_XRGB4444,
-+};
-+
-+static const struct pl111_variant_data pl111_variant = {
-+	.name = "PL111",
-+	.formats = pl111_pixel_formats,
-+	.nformats = ARRAY_SIZE(pl111_pixel_formats),
-+};
-+
-+static const struct amba_id pl111_id_table[] = {
-+	{
-+		.id = 0x00041110,
-+		.mask = 0x000fffff,
-+		.data = (void*)&pl110_variant,
-+	},
- 	{
- 		.id = 0x00041111,
- 		.mask = 0x000fffff,
-+		.data = (void*)&pl111_variant,
- 	},
- 	{0, 0},
- };
---- linux-4.14/drivers/gpu/drm/pl111/pl111_versatile.c.0130~	2017-12-14 06:39:58.518903639 +0100
-+++ linux-4.14/drivers/gpu/drm/pl111/pl111_versatile.c	2017-12-14 06:39:58.518903639 +0100
-@@ -0,0 +1,270 @@
-+#include <linux/device.h>
-+#include <linux/of.h>
-+#include <linux/regmap.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/bitops.h>
-+#include <linux/module.h>
-+#include <drm/drmP.h>
-+#include "pl111_versatile.h"
-+#include "pl111_drm.h"
-+
-+static struct regmap *versatile_syscon_map;
-+
-+/*
-+ * We detect the different syscon types from the compatible strings.
-+ */
-+enum versatile_clcd {
-+	INTEGRATOR_CLCD_CM,
-+	VERSATILE_CLCD,
-+	REALVIEW_CLCD_EB,
-+	REALVIEW_CLCD_PB1176,
-+	REALVIEW_CLCD_PB11MP,
-+	REALVIEW_CLCD_PBA8,
-+	REALVIEW_CLCD_PBX,
-+};
-+
-+static const struct of_device_id versatile_clcd_of_match[] = {
-+	{
-+		.compatible = "arm,core-module-integrator",
-+		.data = (void *)INTEGRATOR_CLCD_CM,
-+	},
-+	{
-+		.compatible = "arm,versatile-sysreg",
-+		.data = (void *)VERSATILE_CLCD,
-+	},
-+	{
-+		.compatible = "arm,realview-eb-syscon",
-+		.data = (void *)REALVIEW_CLCD_EB,
-+	},
-+	{
-+		.compatible = "arm,realview-pb1176-syscon",
-+		.data = (void *)REALVIEW_CLCD_PB1176,
-+	},
-+	{
-+		.compatible = "arm,realview-pb11mp-syscon",
-+		.data = (void *)REALVIEW_CLCD_PB11MP,
-+	},
-+	{
-+		.compatible = "arm,realview-pba8-syscon",
-+		.data = (void *)REALVIEW_CLCD_PBA8,
-+	},
-+	{
-+		.compatible = "arm,realview-pbx-syscon",
-+		.data = (void *)REALVIEW_CLCD_PBX,
-+	},
-+	{},
-+};
-+
-+/*
-+ * Core module CLCD control on the Integrator/CP, bits
-+ * 8 thru 19 of the CM_CONTROL register controls a bunch
-+ * of CLCD settings.
-+ */
-+#define INTEGRATOR_HDR_CTRL_OFFSET	0x0C
-+#define INTEGRATOR_CLCD_LCDBIASEN	BIT(8)
-+#define INTEGRATOR_CLCD_LCDBIASUP	BIT(9)
-+#define INTEGRATOR_CLCD_LCDBIASDN	BIT(10)
-+/* Bits 11,12,13 controls the LCD type */
-+#define INTEGRATOR_CLCD_LCDMUX_MASK	(BIT(11)|BIT(12)|BIT(13))
-+#define INTEGRATOR_CLCD_LCDMUX_LCD24	BIT(11)
-+#define INTEGRATOR_CLCD_LCDMUX_VGA565	BIT(12)
-+#define INTEGRATOR_CLCD_LCDMUX_SHARP	(BIT(11)|BIT(12))
-+#define INTEGRATOR_CLCD_LCDMUX_VGA555	BIT(13)
-+#define INTEGRATOR_CLCD_LCDMUX_VGA24	(BIT(11)|BIT(12)|BIT(13))
-+#define INTEGRATOR_CLCD_LCD0_EN		BIT(14)
-+#define INTEGRATOR_CLCD_LCD1_EN		BIT(15)
-+/* R/L flip on Sharp */
-+#define INTEGRATOR_CLCD_LCD_STATIC1	BIT(16)
-+/* U/D flip on Sharp */
-+#define INTEGRATOR_CLCD_LCD_STATIC2	BIT(17)
-+/* No connection on Sharp */
-+#define INTEGRATOR_CLCD_LCD_STATIC	BIT(18)
-+/* 0 = 24bit VGA, 1 = 18bit VGA */
-+#define INTEGRATOR_CLCD_LCD_N24BITEN	BIT(19)
-+
-+#define INTEGRATOR_CLCD_MASK		(INTEGRATOR_CLCD_LCDBIASEN | \
-+					 INTEGRATOR_CLCD_LCDBIASUP | \
-+					 INTEGRATOR_CLCD_LCDBIASDN | \
-+					 INTEGRATOR_CLCD_LCDMUX_MASK | \
-+					 INTEGRATOR_CLCD_LCD0_EN | \
-+					 INTEGRATOR_CLCD_LCD1_EN | \
-+					 INTEGRATOR_CLCD_LCD_STATIC1 | \
-+					 INTEGRATOR_CLCD_LCD_STATIC2 | \
-+					 INTEGRATOR_CLCD_LCD_STATIC | \
-+					 INTEGRATOR_CLCD_LCD_N24BITEN)
-+
-+static void pl111_integrator_enable(struct drm_device *drm, u32 format)
-+{
-+	u32 val;
-+
-+	dev_info(drm->dev, "enable Integrator CLCD connectors\n");
-+
-+	/* FIXME: really needed? */
-+	val = INTEGRATOR_CLCD_LCD_STATIC1 | INTEGRATOR_CLCD_LCD_STATIC2 |
-+		INTEGRATOR_CLCD_LCD0_EN | INTEGRATOR_CLCD_LCD1_EN;
-+
-+	switch (format) {
-+	case DRM_FORMAT_XBGR8888:
-+	case DRM_FORMAT_XRGB8888:
-+		break;
-+	case DRM_FORMAT_BGR565:
-+	case DRM_FORMAT_RGB565:
-+		/* truecolor RGB565 */
-+		val |= INTEGRATOR_CLCD_LCDMUX_VGA565;
-+		break;
-+	case DRM_FORMAT_XBGR1555:
-+	case DRM_FORMAT_XRGB1555:
-+		/* Pseudocolor, RGB555, BGR555 */
-+		val |= INTEGRATOR_CLCD_LCDMUX_VGA555;
-+		break;
-+	default:
-+		dev_err(drm->dev, "unhandled format on Integrator 0x%08x\n",
-+			format);
-+		break;
-+	}
-+
-+	regmap_update_bits(versatile_syscon_map,
-+			   INTEGRATOR_HDR_CTRL_OFFSET,
-+			   INTEGRATOR_CLCD_MASK,
-+			   val);
-+}
-+
-+/*
-+ * This configuration register in the Versatile and RealView
-+ * family is uniformly present but appears more and more
-+ * unutilized starting with the RealView series.
-+ */
-+#define SYS_CLCD			0x50
-+#define SYS_CLCD_MODE_MASK		(BIT(0)|BIT(1))
-+#define SYS_CLCD_MODE_888		0
-+#define SYS_CLCD_MODE_5551		BIT(0)
-+#define SYS_CLCD_MODE_565_R_LSB		BIT(1)
-+#define SYS_CLCD_MODE_565_B_LSB		(BIT(0)|BIT(1))
-+#define SYS_CLCD_CONNECTOR_MASK		(BIT(2)|BIT(3)|BIT(4)|BIT(5))
-+#define SYS_CLCD_NLCDIOON		BIT(2)
-+#define SYS_CLCD_VDDPOSSWITCH		BIT(3)
-+#define SYS_CLCD_PWR3V5SWITCH		BIT(4)
-+#define SYS_CLCD_VDDNEGSWITCH		BIT(5)
-+
-+static void pl111_versatile_disable(struct drm_device *drm)
-+{
-+	dev_info(drm->dev, "disable Versatile CLCD connectors\n");
-+	regmap_update_bits(versatile_syscon_map,
-+			   SYS_CLCD,
-+			   SYS_CLCD_CONNECTOR_MASK,
-+			   0);
-+}
-+
-+static void pl111_versatile_enable(struct drm_device *drm, u32 format)
-+{
-+	u32 val = 0;
-+
-+	dev_info(drm->dev, "enable Versatile CLCD connectors\n");
-+
-+	switch (format) {
-+	case DRM_FORMAT_ABGR8888:
-+	case DRM_FORMAT_XBGR8888:
-+	case DRM_FORMAT_ARGB8888:
-+	case DRM_FORMAT_XRGB8888:
-+		val |= SYS_CLCD_MODE_888;
-+		break;
-+	case DRM_FORMAT_BGR565:
-+		val |= SYS_CLCD_MODE_565_R_LSB;
-+		break;
-+	case DRM_FORMAT_RGB565:
-+		val |= SYS_CLCD_MODE_565_B_LSB;
-+		break;
-+	case DRM_FORMAT_ABGR1555:
-+	case DRM_FORMAT_XBGR1555:
-+	case DRM_FORMAT_ARGB1555:
-+	case DRM_FORMAT_XRGB1555:
-+		val |= SYS_CLCD_MODE_5551;
-+		break;
-+	default:
-+		dev_err(drm->dev, "unhandled format on Versatile 0x%08x\n",
-+			format);
-+		break;
-+	}
-+
-+	/* Set up the MUX */
-+	regmap_update_bits(versatile_syscon_map,
-+			   SYS_CLCD,
-+			   SYS_CLCD_MODE_MASK,
-+			   val);
-+
-+	/* Then enable the display */
-+	regmap_update_bits(versatile_syscon_map,
-+			   SYS_CLCD,
-+			   SYS_CLCD_CONNECTOR_MASK,
-+			   SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH);
-+}
-+
-+static void pl111_realview_clcd_disable(struct drm_device *drm)
-+{
-+	dev_info(drm->dev, "disable RealView CLCD connectors\n");
-+	regmap_update_bits(versatile_syscon_map,
-+			   SYS_CLCD,
-+			   SYS_CLCD_CONNECTOR_MASK,
-+			   0);
-+}
-+
-+static void pl111_realview_clcd_enable(struct drm_device *drm, u32 format)
-+{
-+	dev_info(drm->dev, "enable RealView CLCD connectors\n");
-+	regmap_update_bits(versatile_syscon_map,
-+			   SYS_CLCD,
-+			   SYS_CLCD_CONNECTOR_MASK,
-+			   SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH);
-+}
-+
-+int pl111_versatile_init(struct device *dev, struct pl111_drm_dev_private *priv)
-+{
-+	const struct of_device_id *clcd_id;
-+	enum versatile_clcd versatile_clcd_type;
-+	struct device_node *np;
-+	struct regmap *map;
-+
-+	np = of_find_matching_node_and_match(NULL, versatile_clcd_of_match,
-+					     &clcd_id);
-+	if (!np) {
-+		/* Non-ARM reference designs, just bail out */
-+		return 0;
-+	}
-+	versatile_clcd_type = (enum versatile_clcd)clcd_id->data;
-+
-+	map = syscon_node_to_regmap(np);
-+	if (IS_ERR(map)) {
-+		dev_err(dev, "no Versatile syscon regmap\n");
-+		return PTR_ERR(map);
-+	}
-+
-+	switch (versatile_clcd_type) {
-+	case INTEGRATOR_CLCD_CM:
-+		versatile_syscon_map = map;
-+		priv->variant_display_enable = pl111_integrator_enable;
-+		dev_info(dev, "set up callbacks for Integrator PL110\n");
-+		break;
-+	case VERSATILE_CLCD:
-+		versatile_syscon_map = map;
-+		priv->variant_display_enable = pl111_versatile_enable;
-+		priv->variant_display_disable = pl111_versatile_disable;
-+		dev_info(dev, "set up callbacks for Versatile PL110+\n");
-+		break;
-+	case REALVIEW_CLCD_EB:
-+	case REALVIEW_CLCD_PB1176:
-+	case REALVIEW_CLCD_PB11MP:
-+	case REALVIEW_CLCD_PBA8:
-+	case REALVIEW_CLCD_PBX:
-+		versatile_syscon_map = map;
-+		priv->variant_display_enable = pl111_realview_clcd_enable;
-+		priv->variant_display_disable = pl111_realview_clcd_disable;
-+		dev_info(dev, "set up callbacks for RealView PL111\n");
-+		break;
-+	default:
-+		dev_info(dev, "unknown Versatile system controller\n");
-+		break;
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(pl111_versatile_init);
---- linux-4.14/drivers/gpu/drm/pl111/pl111_versatile.h.0130~	2017-12-14 06:39:58.518903639 +0100
-+++ linux-4.14/drivers/gpu/drm/pl111/pl111_versatile.h	2017-12-14 06:39:58.518903639 +0100
-@@ -0,0 +1,9 @@
-+#include <linux/device.h>
-+#include "pl111_drm.h"
-+
-+#ifndef PL111_VERSATILE_H
-+#define PL111_VERSATILE_H
-+
-+int pl111_versatile_init(struct device *dev, struct pl111_drm_dev_private *priv);
-+
-+#endif
---- linux-4.14/drivers/gpu/drm/qxl/qxl_release.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/qxl/qxl_release.c	2017-12-14 06:39:58.518903639 +0100
-@@ -469,7 +469,7 @@ void qxl_release_fence_buffer_objects(st
- 
- 		reservation_object_add_shared_fence(bo->resv, &release->base);
- 		ttm_bo_add_to_lru(bo);
--		__ttm_bo_unreserve(bo);
-+		reservation_object_unlock(bo->resv);
- 	}
- 	spin_unlock(&glob->lru_lock);
- 	ww_acquire_fini(&release->ticket);
---- linux-4.14/drivers/gpu/drm/radeon/ci_dpm.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/radeon/ci_dpm.c	2017-12-14 06:39:58.518903639 +0100
-@@ -184,6 +184,7 @@ static int ci_set_overdrive_target_tdp(s
- 				       u32 target_tdp);
- static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
- 
-+static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
- static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
- 						      PPSMC_Msg msg, u32 parameter);
- 
-@@ -1651,6 +1652,27 @@ static int ci_notify_hw_of_power_source(
- }
- #endif
- 
-+static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
-+{
-+	u32 tmp;
-+	int i;
-+
-+	if (!ci_is_smc_running(rdev))
-+		return PPSMC_Result_Failed;
-+
-+	WREG32(SMC_MESSAGE_0, msg);
-+
-+	for (i = 0; i < rdev->usec_timeout; i++) {
-+		tmp = RREG32(SMC_RESP_0);
-+		if (tmp != 0)
-+			break;
-+		udelay(1);
-+	}
-+	tmp = RREG32(SMC_RESP_0);
-+
-+	return (PPSMC_Result)tmp;
-+}
-+
- static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
- 						      PPSMC_Msg msg, u32 parameter)
- {
---- linux-4.14/drivers/gpu/drm/radeon/ci_dpm.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/radeon/ci_dpm.h	2017-12-14 06:39:58.518903639 +0100
-@@ -330,7 +330,6 @@ int ci_program_jump_on_start(struct rade
- void ci_stop_smc_clock(struct radeon_device *rdev);
- void ci_start_smc_clock(struct radeon_device *rdev);
- bool ci_is_smc_running(struct radeon_device *rdev);
--PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
- PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev);
- int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit);
- int ci_read_smc_sram_dword(struct radeon_device *rdev,
---- linux-4.14/drivers/gpu/drm/radeon/ci_smc.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/radeon/ci_smc.c	2017-12-14 06:39:58.518903639 +0100
-@@ -163,27 +163,6 @@ bool ci_is_smc_running(struct radeon_dev
- 	return false;
- }
- 
--PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
--{
--	u32 tmp;
--	int i;
--
--	if (!ci_is_smc_running(rdev))
--		return PPSMC_Result_Failed;
--
--	WREG32(SMC_MESSAGE_0, msg);
--
--	for (i = 0; i < rdev->usec_timeout; i++) {
--		tmp = RREG32(SMC_RESP_0);
--		if (tmp != 0)
--			break;
--		udelay(1);
--	}
--	tmp = RREG32(SMC_RESP_0);
--
--	return (PPSMC_Result)tmp;
--}
--
- #if 0
- PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev)
- {
---- linux-4.14/drivers/gpu/drm/radeon/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/radeon/Makefile	2017-12-14 06:39:58.519903640 +0100
-@@ -110,5 +110,3 @@ radeon-$(CONFIG_VGA_SWITCHEROO) += radeo
- radeon-$(CONFIG_ACPI) += radeon_acpi.o
- 
- obj-$(CONFIG_DRM_RADEON)+= radeon.o
--
--CFLAGS_radeon_trace_points.o := -I$(src)
---- linux-4.14/drivers/gpu/drm/radeon/r100.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/radeon/r100.c	2017-12-14 06:39:58.519903640 +0100
-@@ -1456,7 +1456,7 @@ int r100_cs_packet_parse_vline(struct ra
- 	header = radeon_get_ib_value(p, h_idx);
- 	crtc_id = radeon_get_ib_value(p, h_idx + 5);
- 	reg = R100_CP_PACKET0_GET_REG(header);
--	crtc = drm_crtc_find(p->rdev->ddev, crtc_id);
-+	crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
- 	if (!crtc) {
- 		DRM_ERROR("cannot find crtc %d\n", crtc_id);
- 		return -ENOENT;
---- linux-4.14/drivers/gpu/drm/radeon/r600_cs.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/radeon/r600_cs.c	2017-12-14 06:39:58.519903640 +0100
-@@ -887,7 +887,7 @@ int r600_cs_common_vline_parse(struct ra
- 	crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
- 	reg = R600_CP_PACKET0_GET_REG(header);
- 
--	crtc = drm_crtc_find(p->rdev->ddev, crtc_id);
-+	crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
- 	if (!crtc) {
- 		DRM_ERROR("cannot find crtc %d\n", crtc_id);
- 		return -ENOENT;
---- linux-4.14/drivers/gpu/drm/radeon/r600_hdmi.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/radeon/r600_hdmi.c	2017-12-14 06:39:58.519903640 +0100
-@@ -58,7 +58,7 @@ enum r600_hdmi_iec_status_bits {
- 
- static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev)
- {
--	struct r600_audio_pin status;
-+	struct r600_audio_pin status = {};
- 	uint32_t value;
- 
- 	value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
---- linux-4.14/drivers/gpu/drm/radeon/radeon_connectors.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/radeon/radeon_connectors.c	2017-12-14 06:39:58.519903640 +0100
-@@ -263,7 +263,7 @@ radeon_connector_update_scratch_regs(str
- 		if (connector->encoder_ids[i] == 0)
- 			break;
- 
--		encoder = drm_encoder_find(connector->dev,
-+		encoder = drm_encoder_find(connector->dev, NULL,
- 					   connector->encoder_ids[i]);
- 		if (!encoder)
- 			continue;
-@@ -290,7 +290,7 @@ static struct drm_encoder *radeon_find_e
- 		if (connector->encoder_ids[i] == 0)
- 			break;
- 
--		encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
-+		encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
- 		if (!encoder)
- 			continue;
- 
-@@ -404,7 +404,7 @@ static struct drm_encoder *radeon_best_s
- 	int enc_id = connector->encoder_ids[0];
- 	/* pick the encoder ids */
- 	if (enc_id)
--		return drm_encoder_find(connector->dev, enc_id);
-+		return drm_encoder_find(connector->dev, NULL, enc_id);
- 	return NULL;
- }
- 
-@@ -1368,7 +1368,7 @@ radeon_dvi_detect(struct drm_connector *
- 			if (connector->encoder_ids[i] == 0)
- 				break;
- 
--			encoder = drm_encoder_find(connector->dev,
-+			encoder = drm_encoder_find(connector->dev, NULL,
- 						   connector->encoder_ids[i]);
- 			if (!encoder)
- 				continue;
-@@ -1454,7 +1454,7 @@ static struct drm_encoder *radeon_dvi_en
- 		if (connector->encoder_ids[i] == 0)
- 			break;
- 
--		encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
-+		encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
- 		if (!encoder)
- 			continue;
- 
-@@ -1473,7 +1473,7 @@ static struct drm_encoder *radeon_dvi_en
- 	/* then check use digitial */
- 	/* pick the first one */
- 	if (enc_id)
--		return drm_encoder_find(connector->dev, enc_id);
-+		return drm_encoder_find(connector->dev, NULL, enc_id);
- 	return NULL;
- }
- 
-@@ -1620,7 +1620,7 @@ u16 radeon_connector_encoder_get_dp_brid
- 		if (connector->encoder_ids[i] == 0)
- 			break;
- 
--		encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
-+		encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
- 		if (!encoder)
- 			continue;
- 
-@@ -1649,7 +1649,7 @@ static bool radeon_connector_encoder_is_
- 		if (connector->encoder_ids[i] == 0)
- 			break;
- 
--		encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
-+		encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
- 		if (!encoder)
- 			continue;
- 
---- linux-4.14/drivers/gpu/drm/radeon/radeon_kfd.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/radeon/radeon_kfd.c	2017-12-14 06:39:58.520903641 +0100
-@@ -58,6 +58,10 @@ static uint64_t get_vmem_size(struct kgd
- static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
- 
- static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
-+
-+static int alloc_pasid(unsigned int bits);
-+static void free_pasid(unsigned int pasid);
-+
- static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
- 
- /*
-@@ -112,6 +116,8 @@ static const struct kfd2kgd_calls kfd2kg
- 	.get_vmem_size = get_vmem_size,
- 	.get_gpu_clock_counter = get_gpu_clock_counter,
- 	.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
-+	.alloc_pasid = alloc_pasid,
-+	.free_pasid = free_pasid,
- 	.program_sh_mem_settings = kgd_program_sh_mem_settings,
- 	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
- 	.init_pipeline = kgd_init_pipeline,
-@@ -341,6 +347,31 @@ static uint32_t get_max_engine_clock_in_
- 	return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;
- }
- 
-+/*
-+ * PASID manager
-+ */
-+static DEFINE_IDA(pasid_ida);
-+
-+static int alloc_pasid(unsigned int bits)
-+{
-+	int pasid = -EINVAL;
-+
-+	for (bits = min(bits, 31U); bits > 0; bits--) {
-+		pasid = ida_simple_get(&pasid_ida,
-+				       1U << (bits - 1), 1U << bits,
-+				       GFP_KERNEL);
-+		if (pasid != -ENOSPC)
-+			break;
-+	}
-+
-+	return pasid;
-+}
-+
-+static void free_pasid(unsigned int pasid)
-+{
-+	ida_simple_remove(&pasid_ida, pasid);
-+}
-+
- static inline struct radeon_device *get_radeon_device(struct kgd_dev *kgd)
- {
- 	return (struct radeon_device *)kgd;
---- linux-4.14/drivers/gpu/drm/radeon/radeon_mode.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/radeon/radeon_mode.h	2017-12-14 06:39:58.520903641 +0100
-@@ -762,10 +762,6 @@ extern u8 radeon_dp_getsinktype(struct r
- extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
- extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
- 				    struct drm_connector *connector);
--extern int radeon_dp_get_dp_link_config(struct drm_connector *connector,
--					const u8 *dpcd,
--					unsigned pix_clock,
--					unsigned *dp_lanes, unsigned *dp_rate);
- extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
- 					 u8 power_state);
- extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
---- linux-4.14/drivers/gpu/drm/radeon/radeon_trace.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/radeon/radeon_trace.h	2017-12-14 06:39:58.520903641 +0100
-@@ -205,5 +205,5 @@ DEFINE_EVENT(radeon_semaphore_request, r
- 
- /* This part must be outside protection */
- #undef TRACE_INCLUDE_PATH
--#define TRACE_INCLUDE_PATH .
-+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/radeon
- #include <trace/define_trace.h>
---- linux-4.14/drivers/gpu/drm/radeon/radeon_ttm.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/radeon/radeon_ttm.c	2017-12-14 06:39:58.520903641 +0100
-@@ -725,8 +725,6 @@ static int radeon_ttm_tt_populate(struct
- {
- 	struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
- 	struct radeon_device *rdev;
--	unsigned i;
--	int r;
- 	bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
- 
- 	if (ttm->state != tt_unpopulated)
-@@ -762,33 +760,13 @@ static int radeon_ttm_tt_populate(struct
- 	}
- #endif
- 
--	r = ttm_pool_populate(ttm);
--	if (r) {
--		return r;
--	}
--
--	for (i = 0; i < ttm->num_pages; i++) {
--		gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
--						       0, PAGE_SIZE,
--						       PCI_DMA_BIDIRECTIONAL);
--		if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
--			while (i--) {
--				pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
--					       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
--				gtt->ttm.dma_address[i] = 0;
--			}
--			ttm_pool_unpopulate(ttm);
--			return -EFAULT;
--		}
--	}
--	return 0;
-+	return ttm_populate_and_map_pages(rdev->dev, &gtt->ttm);
- }
- 
- static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
- {
- 	struct radeon_device *rdev;
- 	struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
--	unsigned i;
- 	bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
- 
- 	if (gtt && gtt->userptr) {
-@@ -815,14 +793,7 @@ static void radeon_ttm_tt_unpopulate(str
- 	}
- #endif
- 
--	for (i = 0; i < ttm->num_pages; i++) {
--		if (gtt->ttm.dma_address[i]) {
--			pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
--				       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
--		}
--	}
--
--	ttm_pool_unpopulate(ttm);
-+	ttm_unmap_and_unpopulate_pages(rdev->dev, &gtt->ttm);
- }
- 
- int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
---- linux-4.14/drivers/gpu/drm/rcar-du/rcar_du_kms.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rcar-du/rcar_du_kms.c	2017-12-14 06:39:58.520903641 +0100
-@@ -18,6 +18,7 @@
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_fb_cma_helper.h>
- #include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- 
- #include <linux/of_graph.h>
- #include <linux/wait.h>
-@@ -213,7 +214,7 @@ rcar_du_fb_create(struct drm_device *dev
- 		}
- 	}
- 
--	return drm_fb_cma_create(dev, file_priv, mode_cmd);
-+	return drm_gem_fb_create(dev, file_priv, mode_cmd);
- }
- 
- static void rcar_du_output_poll_changed(struct drm_device *dev)
---- linux-4.14/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c	2017-12-14 06:39:58.520903641 +0100
-@@ -88,7 +88,7 @@ static void analogix_dp_psr_set(struct d
- 	if (!analogix_dp_psr_supported(dp->dev))
- 		return;
- 
--	dev_dbg(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
-+	DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
- 
- 	spin_lock_irqsave(&dp->psr_lock, flags);
- 	if (enabled)
-@@ -110,7 +110,7 @@ static void analogix_dp_psr_work(struct
- 	ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
- 					 PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
- 	if (ret) {
--		dev_err(dp->dev, "line flag interrupt did not arrive\n");
-+		DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n");
- 		return;
- 	}
- 
-@@ -140,13 +140,13 @@ static int rockchip_dp_poweron(struct an
- 
- 	ret = clk_prepare_enable(dp->pclk);
- 	if (ret < 0) {
--		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
-+		DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
- 		return ret;
- 	}
- 
- 	ret = rockchip_dp_pre_init(dp);
- 	if (ret < 0) {
--		dev_err(dp->dev, "failed to dp pre init %d\n", ret);
-+		DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
- 		clk_disable_unprepare(dp->pclk);
- 		return ret;
- 	}
-@@ -211,17 +211,17 @@ static void rockchip_dp_drm_encoder_enab
- 	else
- 		val = dp->data->lcdsel_big;
- 
--	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
-+	DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
- 
- 	ret = clk_prepare_enable(dp->grfclk);
- 	if (ret < 0) {
--		dev_err(dp->dev, "failed to enable grfclk %d\n", ret);
-+		DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
- 		return;
- 	}
- 
- 	ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
- 	if (ret != 0)
--		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
-+		DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
- 
- 	clk_disable_unprepare(dp->grfclk);
- }
-@@ -277,7 +277,7 @@ static int rockchip_dp_init(struct rockc
- 
- 	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
- 	if (IS_ERR(dp->grf)) {
--		dev_err(dev, "failed to get rockchip,grf property\n");
-+		DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
- 		return PTR_ERR(dp->grf);
- 	}
- 
-@@ -287,31 +287,31 @@ static int rockchip_dp_init(struct rockc
- 	} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
- 		return -EPROBE_DEFER;
- 	} else if (IS_ERR(dp->grfclk)) {
--		dev_err(dev, "failed to get grf clock\n");
-+		DRM_DEV_ERROR(dev, "failed to get grf clock\n");
- 		return PTR_ERR(dp->grfclk);
- 	}
- 
- 	dp->pclk = devm_clk_get(dev, "pclk");
- 	if (IS_ERR(dp->pclk)) {
--		dev_err(dev, "failed to get pclk property\n");
-+		DRM_DEV_ERROR(dev, "failed to get pclk property\n");
- 		return PTR_ERR(dp->pclk);
- 	}
- 
- 	dp->rst = devm_reset_control_get(dev, "dp");
- 	if (IS_ERR(dp->rst)) {
--		dev_err(dev, "failed to get dp reset control\n");
-+		DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
- 		return PTR_ERR(dp->rst);
- 	}
- 
- 	ret = clk_prepare_enable(dp->pclk);
- 	if (ret < 0) {
--		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
-+		DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
- 		return ret;
- 	}
- 
- 	ret = rockchip_dp_pre_init(dp);
- 	if (ret < 0) {
--		dev_err(dp->dev, "failed to pre init %d\n", ret);
-+		DRM_DEV_ERROR(dp->dev, "failed to pre init %d\n", ret);
- 		clk_disable_unprepare(dp->pclk);
- 		return ret;
- 	}
---- linux-4.14/drivers/gpu/drm/rockchip/cdn-dp-core.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/cdn-dp-core.c	2017-12-14 06:39:58.520903641 +0100
-@@ -287,14 +287,6 @@ static int cdn_dp_connector_get_modes(st
- 	return ret;
- }
- 
--static struct drm_encoder *
--cdn_dp_connector_best_encoder(struct drm_connector *connector)
--{
--	struct cdn_dp_device *dp = connector_to_dp(connector);
--
--	return &dp->encoder;
--}
--
- static int cdn_dp_connector_mode_valid(struct drm_connector *connector,
- 				       struct drm_display_mode *mode)
- {
-@@ -346,7 +338,6 @@ static int cdn_dp_connector_mode_valid(s
- 
- static struct drm_connector_helper_funcs cdn_dp_connector_helper_funcs = {
- 	.get_modes = cdn_dp_connector_get_modes,
--	.best_encoder = cdn_dp_connector_best_encoder,
- 	.mode_valid = cdn_dp_connector_mode_valid,
- };
- 
---- linux-4.14/drivers/gpu/drm/rockchip/cdn-dp-reg.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/cdn-dp-reg.c	2017-12-14 06:39:58.520903641 +0100
-@@ -323,7 +323,7 @@ int cdn_dp_load_firmware(struct cdn_dp_d
- 	reg = readl(dp->regs + VER_LIB_H_ADDR) & 0xff;
- 	dp->fw_version |= reg << 24;
- 
--	dev_dbg(dp->dev, "firmware version: %x\n", dp->fw_version);
-+	DRM_DEV_DEBUG(dp->dev, "firmware version: %x\n", dp->fw_version);
- 
- 	return 0;
- }
---- linux-4.14/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c	2017-12-14 06:39:58.520903641 +0100
-@@ -168,7 +168,7 @@ static int rockchip_hdmi_parse_dt(struct
- 
- 	hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
- 	if (IS_ERR(hdmi->regmap)) {
--		dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
-+		DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n");
- 		return PTR_ERR(hdmi->regmap);
- 	}
- 
-@@ -178,7 +178,7 @@ static int rockchip_hdmi_parse_dt(struct
- 	} else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
- 		return -EPROBE_DEFER;
- 	} else if (IS_ERR(hdmi->vpll_clk)) {
--		dev_err(hdmi->dev, "failed to get grf clock\n");
-+		DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
- 		return PTR_ERR(hdmi->vpll_clk);
- 	}
- 
-@@ -188,13 +188,14 @@ static int rockchip_hdmi_parse_dt(struct
- 	} else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
- 		return -EPROBE_DEFER;
- 	} else if (IS_ERR(hdmi->grf_clk)) {
--		dev_err(hdmi->dev, "failed to get grf clock\n");
-+		DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
- 		return PTR_ERR(hdmi->grf_clk);
- 	}
- 
- 	ret = clk_prepare_enable(hdmi->vpll_clk);
- 	if (ret) {
--		dev_err(hdmi->dev, "Failed to enable HDMI vpll: %d\n", ret);
-+		DRM_DEV_ERROR(hdmi->dev,
-+			      "Failed to enable HDMI vpll: %d\n", ret);
- 		return ret;
- 	}
- 
-@@ -259,17 +260,17 @@ static void dw_hdmi_rockchip_encoder_ena
- 
- 	ret = clk_prepare_enable(hdmi->grf_clk);
- 	if (ret < 0) {
--		dev_err(hdmi->dev, "failed to enable grfclk %d\n", ret);
-+		DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret);
- 		return;
- 	}
- 
- 	ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);
- 	if (ret != 0)
--		dev_err(hdmi->dev, "Could not write to GRF: %d\n", ret);
-+		DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret);
- 
- 	clk_disable_unprepare(hdmi->grf_clk);
--	dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
--		ret ? "LIT" : "BIG");
-+	DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n",
-+		      ret ? "LIT" : "BIG");
- }
- 
- static int
-@@ -368,7 +369,7 @@ static int dw_hdmi_rockchip_bind(struct
- 
- 	ret = rockchip_hdmi_parse_dt(hdmi);
- 	if (ret) {
--		dev_err(hdmi->dev, "Unable to parse OF data\n");
-+		DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n");
- 		return ret;
- 	}
- 
---- linux-4.14/drivers/gpu/drm/rockchip/dw-mipi-dsi.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/dw-mipi-dsi.c	2017-12-14 06:39:58.521903641 +0100
-@@ -430,9 +430,9 @@ static int dw_mipi_dsi_phy_init(struct d
- 
- 	testdin = max_mbps_to_testdin(dsi->lane_mbps);
- 	if (testdin < 0) {
--		dev_err(dsi->dev,
--			"failed to get testdin for %dmbps lane clock\n",
--			dsi->lane_mbps);
-+		DRM_DEV_ERROR(dsi->dev,
-+			      "failed to get testdin for %dmbps lane clock\n",
-+			      dsi->lane_mbps);
- 		return testdin;
- 	}
- 
-@@ -443,7 +443,7 @@ static int dw_mipi_dsi_phy_init(struct d
- 
- 	ret = clk_prepare_enable(dsi->phy_cfg_clk);
- 	if (ret) {
--		dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
-+		DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
- 		return ret;
- 	}
- 
-@@ -501,7 +501,7 @@ static int dw_mipi_dsi_phy_init(struct d
- 	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
- 				 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
- 	if (ret < 0) {
--		dev_err(dsi->dev, "failed to wait for phy lock state\n");
-+		DRM_DEV_ERROR(dsi->dev, "failed to wait for phy lock state\n");
- 		goto phy_init_end;
- 	}
- 
-@@ -509,8 +509,8 @@ static int dw_mipi_dsi_phy_init(struct d
- 				 val, val & STOP_STATE_CLK_LANE, 1000,
- 				 PHY_STATUS_TIMEOUT_US);
- 	if (ret < 0)
--		dev_err(dsi->dev,
--			"failed to wait for phy clk lane stop state\n");
-+		DRM_DEV_ERROR(dsi->dev,
-+			      "failed to wait for phy clk lane stop state\n");
- 
- phy_init_end:
- 	clk_disable_unprepare(dsi->phy_cfg_clk);
-@@ -529,8 +529,9 @@ static int dw_mipi_dsi_get_lane_bps(stru
- 
- 	bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
- 	if (bpp < 0) {
--		dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
--			dsi->format);
-+		DRM_DEV_ERROR(dsi->dev,
-+			      "failed to get bpp for pixel format %d\n",
-+			      dsi->format);
- 		return bpp;
- 	}
- 
-@@ -541,7 +542,8 @@ static int dw_mipi_dsi_get_lane_bps(stru
- 		if (tmp < max_mbps)
- 			target_mbps = tmp;
- 		else
--			dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
-+			DRM_DEV_ERROR(dsi->dev,
-+				      "DPHY clock frequency is out of range\n");
- 	}
- 
- 	pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
-@@ -582,8 +584,9 @@ static int dw_mipi_dsi_host_attach(struc
- 	struct dw_mipi_dsi *dsi = host_to_dsi(host);
- 
- 	if (device->lanes > dsi->pdata->max_data_lanes) {
--		dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
--			device->lanes);
-+		DRM_DEV_ERROR(dsi->dev,
-+			      "the number of data lanes(%u) is too many\n",
-+			      device->lanes);
- 		return -EINVAL;
- 	}
- 
-@@ -632,7 +635,8 @@ static int dw_mipi_dsi_gen_pkt_hdr_write
- 				 val, !(val & GEN_CMD_FULL), 1000,
- 				 CMD_PKT_STATUS_TIMEOUT_US);
- 	if (ret < 0) {
--		dev_err(dsi->dev, "failed to get available command FIFO\n");
-+		DRM_DEV_ERROR(dsi->dev,
-+			      "failed to get available command FIFO\n");
- 		return ret;
- 	}
- 
-@@ -643,7 +647,7 @@ static int dw_mipi_dsi_gen_pkt_hdr_write
- 				 val, (val & mask) == mask,
- 				 1000, CMD_PKT_STATUS_TIMEOUT_US);
- 	if (ret < 0) {
--		dev_err(dsi->dev, "failed to write command FIFO\n");
-+		DRM_DEV_ERROR(dsi->dev, "failed to write command FIFO\n");
- 		return ret;
- 	}
- 
-@@ -663,8 +667,9 @@ static int dw_mipi_dsi_dcs_short_write(s
- 		data |= tx_buf[1] << 8;
- 
- 	if (msg->tx_len > 2) {
--		dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
--			msg->tx_len);
-+		DRM_DEV_ERROR(dsi->dev,
-+			      "too long tx buf length %zu for short write\n",
-+			      msg->tx_len);
- 		return -EINVAL;
- 	}
- 
-@@ -682,8 +687,9 @@ static int dw_mipi_dsi_dcs_long_write(st
- 	u32 val;
- 
- 	if (msg->tx_len < 3) {
--		dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
--			msg->tx_len);
-+		DRM_DEV_ERROR(dsi->dev,
-+			      "wrong tx buf length %zu for long write\n",
-+			      msg->tx_len);
- 		return -EINVAL;
- 	}
- 
-@@ -704,8 +710,8 @@ static int dw_mipi_dsi_dcs_long_write(st
- 					 val, !(val & GEN_PLD_W_FULL), 1000,
- 					 CMD_PKT_STATUS_TIMEOUT_US);
- 		if (ret < 0) {
--			dev_err(dsi->dev,
--				"failed to get available write payload FIFO\n");
-+			DRM_DEV_ERROR(dsi->dev,
-+				      "failed to get available write payload FIFO\n");
- 			return ret;
- 		}
- 	}
-@@ -731,8 +737,8 @@ static ssize_t dw_mipi_dsi_host_transfer
- 		ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
- 		break;
- 	default:
--		dev_err(dsi->dev, "unsupported message type 0x%02x\n",
--			msg->type);
-+		DRM_DEV_ERROR(dsi->dev, "unsupported message type 0x%02x\n",
-+			      msg->type);
- 		ret = -EINVAL;
- 	}
- 
-@@ -935,7 +941,7 @@ static void dw_mipi_dsi_encoder_disable(
- 		return;
- 
- 	if (clk_prepare_enable(dsi->pclk)) {
--		dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
-+		DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk\n");
- 		return;
- 	}
- 
-@@ -967,7 +973,7 @@ static void dw_mipi_dsi_encoder_enable(s
- 		return;
- 
- 	if (clk_prepare_enable(dsi->pclk)) {
--		dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
-+		DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk\n");
- 		return;
- 	}
- 
-@@ -991,7 +997,7 @@ static void dw_mipi_dsi_encoder_enable(s
- 	 */
- 	ret = clk_prepare_enable(dsi->grf_clk);
- 	if (ret) {
--		dev_err(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
-+		DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
- 		return;
- 	}
- 
-@@ -1004,7 +1010,7 @@ static void dw_mipi_dsi_encoder_enable(s
- 
- 	dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
- 	if (drm_panel_prepare(dsi->panel))
--		dev_err(dsi->dev, "failed to prepare panel\n");
-+		DRM_DEV_ERROR(dsi->dev, "failed to prepare panel\n");
- 
- 	dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
- 	drm_panel_enable(dsi->panel);
-@@ -1017,7 +1023,8 @@ static void dw_mipi_dsi_encoder_enable(s
- 		val = pdata->dsi0_en_bit << 16;
- 
- 	regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
--	dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
-+	DRM_DEV_DEBUG(dsi->dev,
-+		      "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
- 	dsi->dpms_mode = DRM_MODE_DPMS_ON;
- 
- 	clk_disable_unprepare(dsi->grf_clk);
-@@ -1111,7 +1118,7 @@ static int dw_mipi_dsi_register(struct d
- 	ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
- 			       DRM_MODE_ENCODER_DSI, NULL);
- 	if (ret) {
--		dev_err(dev, "Failed to initialize encoder with drm\n");
-+		DRM_DEV_ERROR(dev, "Failed to initialize encoder with drm\n");
- 		return ret;
- 	}
- 
-@@ -1133,7 +1140,7 @@ static int rockchip_mipi_parse_dt(struct
- 
- 	dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
- 	if (IS_ERR(dsi->grf_regmap)) {
--		dev_err(dsi->dev, "Unable to get rockchip,grf\n");
-+		DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");
- 		return PTR_ERR(dsi->grf_regmap);
- 	}
- 
-@@ -1205,14 +1212,15 @@ static int dw_mipi_dsi_bind(struct devic
- 	dsi->pllref_clk = devm_clk_get(dev, "ref");
- 	if (IS_ERR(dsi->pllref_clk)) {
- 		ret = PTR_ERR(dsi->pllref_clk);
--		dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
-+		DRM_DEV_ERROR(dev,
-+			      "Unable to get pll reference clock: %d\n", ret);
- 		return ret;
- 	}
- 
- 	dsi->pclk = devm_clk_get(dev, "pclk");
- 	if (IS_ERR(dsi->pclk)) {
- 		ret = PTR_ERR(dsi->pclk);
--		dev_err(dev, "Unable to get pclk: %d\n", ret);
-+		DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret);
- 		return ret;
- 	}
- 
-@@ -1226,7 +1234,8 @@ static int dw_mipi_dsi_bind(struct devic
- 		if (ret == -ENOENT) {
- 			apb_rst = NULL;
- 		} else {
--			dev_err(dev, "Unable to get reset control: %d\n", ret);
-+			DRM_DEV_ERROR(dev,
-+				      "Unable to get reset control: %d\n", ret);
- 			return ret;
- 		}
- 	}
-@@ -1234,7 +1243,7 @@ static int dw_mipi_dsi_bind(struct devic
- 	if (apb_rst) {
- 		ret = clk_prepare_enable(dsi->pclk);
- 		if (ret) {
--			dev_err(dev, "%s: Failed to enable pclk\n", __func__);
-+			DRM_DEV_ERROR(dev, "Failed to enable pclk\n");
- 			return ret;
- 		}
- 
-@@ -1249,7 +1258,8 @@ static int dw_mipi_dsi_bind(struct devic
- 		dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
- 		if (IS_ERR(dsi->phy_cfg_clk)) {
- 			ret = PTR_ERR(dsi->phy_cfg_clk);
--			dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret);
-+			DRM_DEV_ERROR(dev,
-+				      "Unable to get phy_cfg_clk: %d\n", ret);
- 			return ret;
- 		}
- 	}
-@@ -1258,20 +1268,20 @@ static int dw_mipi_dsi_bind(struct devic
- 		dsi->grf_clk = devm_clk_get(dev, "grf");
- 		if (IS_ERR(dsi->grf_clk)) {
- 			ret = PTR_ERR(dsi->grf_clk);
--			dev_err(dev, "Unable to get grf_clk: %d\n", ret);
-+			DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
- 			return ret;
- 		}
- 	}
- 
- 	ret = clk_prepare_enable(dsi->pllref_clk);
- 	if (ret) {
--		dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
-+		DRM_DEV_ERROR(dev, "Failed to enable pllref_clk\n");
- 		return ret;
- 	}
- 
- 	ret = dw_mipi_dsi_register(drm, dsi);
- 	if (ret) {
--		dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
-+		DRM_DEV_ERROR(dev, "Failed to register mipi_dsi: %d\n", ret);
- 		goto err_pllref;
- 	}
- 
-@@ -1281,7 +1291,7 @@ static int dw_mipi_dsi_bind(struct devic
- 	dsi->dsi_host.dev = dev;
- 	ret = mipi_dsi_host_register(&dsi->dsi_host);
- 	if (ret) {
--		dev_err(dev, "Failed to register MIPI host: %d\n", ret);
-+		DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);
- 		goto err_cleanup;
- 	}
- 
---- linux-4.14/drivers/gpu/drm/rockchip/inno_hdmi.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/inno_hdmi.c	2017-12-14 06:39:58.521903641 +0100
-@@ -224,7 +224,7 @@ static void inno_hdmi_set_pwr_mode(struc
- 		break;
- 
- 	default:
--		dev_err(hdmi->dev, "Unknown power mode %d\n", mode);
-+		DRM_DEV_ERROR(hdmi->dev, "Unknown power mode %d\n", mode);
- 	}
- }
- 
-@@ -742,8 +742,9 @@ static int inno_hdmi_i2c_xfer(struct i2c
- 	hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
- 
- 	for (i = 0; i < num; i++) {
--		dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
--			i + 1, num, msgs[i].len, msgs[i].flags);
-+		DRM_DEV_DEBUG(hdmi->dev,
-+			      "xfer: num: %d/%d, len: %d, flags: %#x\n",
-+			      i + 1, num, msgs[i].len, msgs[i].flags);
- 
- 		if (msgs[i].flags & I2C_M_RD)
- 			ret = inno_hdmi_i2c_read(hdmi, &msgs[i]);
-@@ -806,7 +807,7 @@ static struct i2c_adapter *inno_hdmi_i2c
- 
- 	hdmi->i2c = i2c;
- 
--	dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
-+	DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
- 
- 	return adap;
- }
-@@ -838,13 +839,14 @@ static int inno_hdmi_bind(struct device
- 
- 	hdmi->pclk = devm_clk_get(hdmi->dev, "pclk");
- 	if (IS_ERR(hdmi->pclk)) {
--		dev_err(hdmi->dev, "Unable to get HDMI pclk clk\n");
-+		DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI pclk clk\n");
- 		return PTR_ERR(hdmi->pclk);
- 	}
- 
- 	ret = clk_prepare_enable(hdmi->pclk);
- 	if (ret) {
--		dev_err(hdmi->dev, "Cannot enable HDMI pclk clock: %d\n", ret);
-+		DRM_DEV_ERROR(hdmi->dev,
-+			      "Cannot enable HDMI pclk clock: %d\n", ret);
- 		return ret;
- 	}
- 
---- linux-4.14/drivers/gpu/drm/rockchip/Kconfig.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/Kconfig	2017-12-14 06:39:58.521903641 +0100
-@@ -57,4 +57,13 @@ config ROCKCHIP_INNO_HDMI
- 	  for the Innosilicon HDMI driver. If you want to enable
- 	  HDMI on RK3036 based SoC, you should select this option.
- 
-+config ROCKCHIP_LVDS
-+	bool "Rockchip LVDS support"
-+	depends on DRM_ROCKCHIP
-+	depends on PINCTRL
-+	help
-+	  Choose this option to enable support for Rockchip LVDS controllers.
-+	  Rockchip rk3288 SoC has LVDS TX Controller can be used, and it
-+	  support LVDS, rgb, dual LVDS output mode. say Y to enable its
-+	  driver.
- endif
---- linux-4.14/drivers/gpu/drm/rockchip/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/Makefile	2017-12-14 06:39:58.521903641 +0100
-@@ -13,5 +13,6 @@ rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) +=
- rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
- rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
- rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
-+rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
- 
- obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o
---- linux-4.14/drivers/gpu/drm/rockchip/rockchip_drm_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/rockchip_drm_drv.c	2017-12-14 06:39:58.521903641 +0100
-@@ -58,7 +58,7 @@ int rockchip_drm_dma_attach_device(struc
- 
- 	ret = iommu_attach_device(private->domain, dev);
- 	if (ret) {
--		dev_err(dev, "Failed to attach iommu device\n");
-+		DRM_DEV_ERROR(dev, "Failed to attach iommu device\n");
- 		return ret;
- 	}
- 
-@@ -373,8 +373,9 @@ static int rockchip_drm_platform_of_prob
- 
- 		iommu = of_parse_phandle(port->parent, "iommus", 0);
- 		if (!iommu || !of_device_is_available(iommu->parent)) {
--			dev_dbg(dev, "no iommu attached for %pOF, using non-iommu buffers\n",
--				port->parent);
-+			DRM_DEV_DEBUG(dev,
-+				      "no iommu attached for %pOF, using non-iommu buffers\n",
-+				      port->parent);
- 			/*
- 			 * if there is a crtc not support iommu, force set all
- 			 * crtc use non-iommu buffer.
-@@ -389,12 +390,13 @@ static int rockchip_drm_platform_of_prob
- 	}
- 
- 	if (i == 0) {
--		dev_err(dev, "missing 'ports' property\n");
-+		DRM_DEV_ERROR(dev, "missing 'ports' property\n");
- 		return -ENODEV;
- 	}
- 
- 	if (!found) {
--		dev_err(dev, "No available vop found for display-subsystem.\n");
-+		DRM_DEV_ERROR(dev,
-+			      "No available vop found for display-subsystem.\n");
- 		return -ENODEV;
- 	}
- 
-@@ -453,6 +455,8 @@ static int __init rockchip_drm_init(void
- 
- 	num_rockchip_sub_drivers = 0;
- 	ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_DRM_ROCKCHIP);
-+	ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver,
-+				CONFIG_ROCKCHIP_LVDS);
- 	ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver,
- 				CONFIG_ROCKCHIP_ANALOGIX_DP);
- 	ADD_ROCKCHIP_SUB_DRIVER(cdn_dp_driver, CONFIG_ROCKCHIP_CDN_DP);
---- linux-4.14/drivers/gpu/drm/rockchip/rockchip_drm_drv.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/rockchip_drm_drv.h	2017-12-14 06:39:58.521903641 +0100
-@@ -69,5 +69,6 @@ extern struct platform_driver dw_hdmi_ro
- extern struct platform_driver dw_mipi_dsi_driver;
- extern struct platform_driver inno_hdmi_driver;
- extern struct platform_driver rockchip_dp_driver;
-+extern struct platform_driver rockchip_lvds_driver;
- extern struct platform_driver vop_platform_driver;
- #endif /* _ROCKCHIP_DRM_DRV_H_ */
---- linux-4.14/drivers/gpu/drm/rockchip/rockchip_drm_fb.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/rockchip_drm_fb.c	2017-12-14 06:39:58.521903641 +0100
-@@ -100,8 +100,9 @@ rockchip_fb_alloc(struct drm_device *dev
- 	ret = drm_framebuffer_init(dev, &rockchip_fb->fb,
- 				   &rockchip_drm_fb_funcs);
- 	if (ret) {
--		dev_err(dev->dev, "Failed to initialize framebuffer: %d\n",
--			ret);
-+		DRM_DEV_ERROR(dev->dev,
-+			      "Failed to initialize framebuffer: %d\n",
-+			      ret);
- 		kfree(rockchip_fb);
- 		return ERR_PTR(ret);
- 	}
-@@ -134,7 +135,8 @@ rockchip_user_fb_create(struct drm_devic
- 
- 		obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[i]);
- 		if (!obj) {
--			dev_err(dev->dev, "Failed to lookup GEM object\n");
-+			DRM_DEV_ERROR(dev->dev,
-+				      "Failed to lookup GEM object\n");
- 			ret = -ENXIO;
- 			goto err_gem_object_unreference;
- 		}
---- linux-4.14/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c	2017-12-14 06:39:58.521903641 +0100
-@@ -76,7 +76,7 @@ static int rockchip_drm_fbdev_create(str
- 
- 	fbi = drm_fb_helper_alloc_fbi(helper);
- 	if (IS_ERR(fbi)) {
--		dev_err(dev->dev, "Failed to create framebuffer info.\n");
-+		DRM_DEV_ERROR(dev->dev, "Failed to create framebuffer info.\n");
- 		ret = PTR_ERR(fbi);
- 		goto out;
- 	}
-@@ -84,7 +84,8 @@ static int rockchip_drm_fbdev_create(str
- 	helper->fb = rockchip_drm_framebuffer_init(dev, &mode_cmd,
- 						   private->fbdev_bo);
- 	if (IS_ERR(helper->fb)) {
--		dev_err(dev->dev, "Failed to allocate DRM framebuffer.\n");
-+		DRM_DEV_ERROR(dev->dev,
-+			      "Failed to allocate DRM framebuffer.\n");
- 		ret = PTR_ERR(helper->fb);
- 		goto out;
- 	}
-@@ -138,21 +139,24 @@ int rockchip_drm_fbdev_init(struct drm_d
- 
- 	ret = drm_fb_helper_init(dev, helper, ROCKCHIP_MAX_CONNECTOR);
- 	if (ret < 0) {
--		dev_err(dev->dev, "Failed to initialize drm fb helper - %d.\n",
--			ret);
-+		DRM_DEV_ERROR(dev->dev,
-+			      "Failed to initialize drm fb helper - %d.\n",
-+			      ret);
- 		return ret;
- 	}
- 
- 	ret = drm_fb_helper_single_add_all_connectors(helper);
- 	if (ret < 0) {
--		dev_err(dev->dev, "Failed to add connectors - %d.\n", ret);
-+		DRM_DEV_ERROR(dev->dev,
-+			      "Failed to add connectors - %d.\n", ret);
- 		goto err_drm_fb_helper_fini;
- 	}
- 
- 	ret = drm_fb_helper_initial_config(helper, PREFERRED_BPP);
- 	if (ret < 0) {
--		dev_err(dev->dev, "Failed to set initial hw config - %d.\n",
--			ret);
-+		DRM_DEV_ERROR(dev->dev,
-+			      "Failed to set initial hw config - %d.\n",
-+			      ret);
- 		goto err_drm_fb_helper_fini;
- 	}
- 
---- linux-4.14/drivers/gpu/drm/rockchip/rockchip_drm_gem.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/rockchip_drm_gem.c	2017-12-14 06:39:58.521903641 +0100
-@@ -220,7 +220,7 @@ static int rockchip_drm_gem_object_mmap_
- {
- 	struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj);
- 	unsigned int i, count = obj->size >> PAGE_SHIFT;
--	unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
-+	unsigned long user_count = vma_pages(vma);
- 	unsigned long uaddr = vma->vm_start;
- 	unsigned long offset = vma->vm_pgoff;
- 	unsigned long end = user_count + offset;
---- linux-4.14/drivers/gpu/drm/rockchip/rockchip_drm_vop.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/rockchip_drm_vop.c	2017-12-14 06:39:58.521903641 +0100
-@@ -160,7 +160,7 @@ static void vop_reg_set(struct vop *vop,
- 	int offset, mask, shift;
- 
- 	if (!reg || !reg->mask) {
--		dev_dbg(vop->dev, "Warning: not support %s\n", reg_name);
-+		DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
- 		return;
- 	}
- 
-@@ -499,7 +499,7 @@ static int vop_enable(struct drm_crtc *c
- 
- 	ret = pm_runtime_get_sync(vop->dev);
- 	if (ret < 0) {
--		dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
-+		DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
- 		return ret;
- 	}
- 
-@@ -523,7 +523,8 @@ static int vop_enable(struct drm_crtc *c
- 	 */
- 	ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
- 	if (ret) {
--		dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
-+		DRM_DEV_ERROR(vop->dev,
-+			      "failed to attach dma mapping, %d\n", ret);
- 		goto err_disable_aclk;
- 	}
- 
-@@ -1361,42 +1362,42 @@ static int vop_initial(struct vop *vop)
- 
- 	vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
- 	if (IS_ERR(vop->hclk)) {
--		dev_err(vop->dev, "failed to get hclk source\n");
-+		DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
- 		return PTR_ERR(vop->hclk);
- 	}
- 	vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
- 	if (IS_ERR(vop->aclk)) {
--		dev_err(vop->dev, "failed to get aclk source\n");
-+		DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
- 		return PTR_ERR(vop->aclk);
- 	}
- 	vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
- 	if (IS_ERR(vop->dclk)) {
--		dev_err(vop->dev, "failed to get dclk source\n");
-+		DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
- 		return PTR_ERR(vop->dclk);
- 	}
- 
- 	ret = pm_runtime_get_sync(vop->dev);
- 	if (ret < 0) {
--		dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
-+		DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
- 		return ret;
- 	}
- 
- 	ret = clk_prepare(vop->dclk);
- 	if (ret < 0) {
--		dev_err(vop->dev, "failed to prepare dclk\n");
-+		DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
- 		goto err_put_pm_runtime;
- 	}
- 
- 	/* Enable both the hclk and aclk to setup the vop */
- 	ret = clk_prepare_enable(vop->hclk);
- 	if (ret < 0) {
--		dev_err(vop->dev, "failed to prepare/enable hclk\n");
-+		DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
- 		goto err_unprepare_dclk;
- 	}
- 
- 	ret = clk_prepare_enable(vop->aclk);
- 	if (ret < 0) {
--		dev_err(vop->dev, "failed to prepare/enable aclk\n");
-+		DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
- 		goto err_disable_hclk;
- 	}
- 
-@@ -1405,7 +1406,7 @@ static int vop_initial(struct vop *vop)
- 	 */
- 	ahb_rst = devm_reset_control_get(vop->dev, "ahb");
- 	if (IS_ERR(ahb_rst)) {
--		dev_err(vop->dev, "failed to get ahb reset\n");
-+		DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
- 		ret = PTR_ERR(ahb_rst);
- 		goto err_disable_aclk;
- 	}
-@@ -1434,7 +1435,7 @@ static int vop_initial(struct vop *vop)
- 	 */
- 	vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
- 	if (IS_ERR(vop->dclk_rst)) {
--		dev_err(vop->dev, "failed to get dclk reset\n");
-+		DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
- 		ret = PTR_ERR(vop->dclk_rst);
- 		goto err_disable_aclk;
- 	}
-@@ -1511,7 +1512,7 @@ int rockchip_drm_wait_vact_end(struct dr
- 	vop_line_flag_irq_disable(vop);
- 
- 	if (jiffies_left == 0) {
--		dev_err(vop->dev, "Timeout waiting for IRQ\n");
-+		DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
- 		return -ETIMEDOUT;
- 	}
- 
-@@ -1558,7 +1559,7 @@ static int vop_bind(struct device *dev,
- 
- 	irq = platform_get_irq(pdev, 0);
- 	if (irq < 0) {
--		dev_err(dev, "cannot find irq for vop\n");
-+		DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
- 		return irq;
- 	}
- 	vop->irq = (unsigned int)irq;
-@@ -1584,7 +1585,8 @@ static int vop_bind(struct device *dev,
- 
- 	ret = vop_initial(vop);
- 	if (ret < 0) {
--		dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
-+		DRM_DEV_ERROR(&pdev->dev,
-+			      "cannot initial vop dev - err %d\n", ret);
- 		goto err_disable_pm_runtime;
- 	}
- 
---- linux-4.14/drivers/gpu/drm/rockchip/rockchip_lvds.c.0130~	2017-12-14 06:39:58.522903642 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/rockchip_lvds.c	2017-12-14 06:39:58.522903642 +0100
-@@ -0,0 +1,586 @@
-+/*
-+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
-+ * Author:
-+ *      Mark Yao <mark.yao@rock-chips.com>
-+ *      Sandy Huang <hjc@rock-chips.com>
-+ *
-+ * This software is licensed under the terms of the GNU General Public
-+ * License version 2, as published by the Free Software Foundation, and
-+ * may be copied, distributed, and modified under those terms.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <drm/drmP.h>
-+#include <drm/drm_atomic_helper.h>
-+#include <drm/drm_crtc_helper.h>
-+#include <drm/drm_dp_helper.h>
-+#include <drm/drm_panel.h>
-+#include <drm/drm_of.h>
-+
-+#include <linux/component.h>
-+#include <linux/clk.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/of_graph.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/regmap.h>
-+#include <linux/reset.h>
-+
-+#include "rockchip_drm_drv.h"
-+#include "rockchip_drm_vop.h"
-+#include "rockchip_lvds.h"
-+
-+#define DISPLAY_OUTPUT_RGB		0
-+#define DISPLAY_OUTPUT_LVDS		1
-+#define DISPLAY_OUTPUT_DUAL_LVDS	2
-+
-+#define connector_to_lvds(c) \
-+		container_of(c, struct rockchip_lvds, connector)
-+
-+#define encoder_to_lvds(c) \
-+		container_of(c, struct rockchip_lvds, encoder)
-+
-+/**
-+ * rockchip_lvds_soc_data - rockchip lvds Soc private data
-+ * @ch1_offset: lvds channel 1 registe offset
-+ * grf_soc_con6: general registe offset for LVDS contrl
-+ * grf_soc_con7: general registe offset for LVDS contrl
-+ * has_vop_sel: to indicate whether need to choose from different VOP.
-+ */
-+struct rockchip_lvds_soc_data {
-+	u32 ch1_offset;
-+	int grf_soc_con6;
-+	int grf_soc_con7;
-+	bool has_vop_sel;
-+};
-+
-+struct rockchip_lvds {
-+	struct device *dev;
-+	void __iomem *regs;
-+	struct regmap *grf;
-+	struct clk *pclk;
-+	const struct rockchip_lvds_soc_data *soc_data;
-+	int output; /* rgb lvds or dual lvds output */
-+	int format; /* vesa or jeida format */
-+	struct drm_device *drm_dev;
-+	struct drm_panel *panel;
-+	struct drm_bridge *bridge;
-+	struct drm_connector connector;
-+	struct drm_encoder encoder;
-+	struct dev_pin_info *pins;
-+};
-+
-+static inline void lvds_writel(struct rockchip_lvds *lvds, u32 offset, u32 val)
-+{
-+	writel_relaxed(val, lvds->regs + offset);
-+	if (lvds->output == DISPLAY_OUTPUT_LVDS)
-+		return;
-+	writel_relaxed(val, lvds->regs + offset + lvds->soc_data->ch1_offset);
-+}
-+
-+static inline int lvds_name_to_format(const char *s)
-+{
-+	if (strncmp(s, "jeida-18", 8) == 0)
-+		return LVDS_JEIDA_18;
-+	else if (strncmp(s, "jeida-24", 8) == 0)
-+		return LVDS_JEIDA_24;
-+	else if (strncmp(s, "vesa-24", 7) == 0)
-+		return LVDS_VESA_24;
-+
-+	return -EINVAL;
-+}
-+
-+static inline int lvds_name_to_output(const char *s)
-+{
-+	if (strncmp(s, "rgb", 3) == 0)
-+		return DISPLAY_OUTPUT_RGB;
-+	else if (strncmp(s, "lvds", 4) == 0)
-+		return DISPLAY_OUTPUT_LVDS;
-+	else if (strncmp(s, "duallvds", 8) == 0)
-+		return DISPLAY_OUTPUT_DUAL_LVDS;
-+
-+	return -EINVAL;
-+}
-+
-+static int rockchip_lvds_poweron(struct rockchip_lvds *lvds)
-+{
-+	int ret;
-+	u32 val;
-+
-+	ret = clk_enable(lvds->pclk);
-+	if (ret < 0) {
-+		DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret);
-+		return ret;
-+	}
-+	ret = pm_runtime_get_sync(lvds->dev);
-+	if (ret < 0) {
-+		DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret);
-+		clk_disable(lvds->pclk);
-+		return ret;
-+	}
-+	val = RK3288_LVDS_CH0_REG0_LANE4_EN | RK3288_LVDS_CH0_REG0_LANE3_EN |
-+		RK3288_LVDS_CH0_REG0_LANE2_EN | RK3288_LVDS_CH0_REG0_LANE1_EN |
-+		RK3288_LVDS_CH0_REG0_LANE0_EN;
-+	if (lvds->output == DISPLAY_OUTPUT_RGB) {
-+		val |= RK3288_LVDS_CH0_REG0_TTL_EN |
-+			RK3288_LVDS_CH0_REG0_LANECK_EN;
-+		lvds_writel(lvds, RK3288_LVDS_CH0_REG0, val);
-+		lvds_writel(lvds, RK3288_LVDS_CH0_REG2,
-+			    RK3288_LVDS_PLL_FBDIV_REG2(0x46));
-+		lvds_writel(lvds, RK3288_LVDS_CH0_REG4,
-+			    RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE |
-+			    RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE |
-+			    RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE |
-+			    RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE |
-+			    RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE |
-+			    RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE);
-+		lvds_writel(lvds, RK3288_LVDS_CH0_REG5,
-+			    RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA |
-+			    RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA |
-+			    RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA |
-+			    RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA |
-+			    RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA |
-+			    RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA);
-+	} else {
-+		val |= RK3288_LVDS_CH0_REG0_LVDS_EN |
-+			    RK3288_LVDS_CH0_REG0_LANECK_EN;
-+		lvds_writel(lvds, RK3288_LVDS_CH0_REG0, val);
-+		lvds_writel(lvds, RK3288_LVDS_CH0_REG1,
-+			    RK3288_LVDS_CH0_REG1_LANECK_BIAS |
-+			    RK3288_LVDS_CH0_REG1_LANE4_BIAS |
-+			    RK3288_LVDS_CH0_REG1_LANE3_BIAS |
-+			    RK3288_LVDS_CH0_REG1_LANE2_BIAS |
-+			    RK3288_LVDS_CH0_REG1_LANE1_BIAS |
-+			    RK3288_LVDS_CH0_REG1_LANE0_BIAS);
-+		lvds_writel(lvds, RK3288_LVDS_CH0_REG2,
-+			    RK3288_LVDS_CH0_REG2_RESERVE_ON |
-+			    RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE |
-+			    RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE |
-+			    RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE |
-+			    RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE |
-+			    RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE |
-+			    RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE |
-+			    RK3288_LVDS_PLL_FBDIV_REG2(0x46));
-+		lvds_writel(lvds, RK3288_LVDS_CH0_REG4, 0x00);
-+		lvds_writel(lvds, RK3288_LVDS_CH0_REG5, 0x00);
-+	}
-+	lvds_writel(lvds, RK3288_LVDS_CH0_REG3, RK3288_LVDS_PLL_FBDIV_REG3(0x46));
-+	lvds_writel(lvds, RK3288_LVDS_CH0_REGD, RK3288_LVDS_PLL_PREDIV_REGD(0x0a));
-+	lvds_writel(lvds, RK3288_LVDS_CH0_REG20, RK3288_LVDS_CH0_REG20_LSB);
-+
-+	lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_ENABLE);
-+	lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_ENABLE);
-+
-+	return 0;
-+}
-+
-+static void rockchip_lvds_poweroff(struct rockchip_lvds *lvds)
-+{
-+	int ret;
-+	u32 val;
-+
-+	lvds_writel(lvds, RK3288_LVDS_CFG_REG21, RK3288_LVDS_CFG_REG21_TX_ENABLE);
-+	lvds_writel(lvds, RK3288_LVDS_CFG_REGC, RK3288_LVDS_CFG_REGC_PLL_ENABLE);
-+	val = LVDS_DUAL | LVDS_TTL_EN | LVDS_CH0_EN | LVDS_CH1_EN | LVDS_PWRDN;
-+	val |= val << 16;
-+	ret = regmap_write(lvds->grf, lvds->soc_data->grf_soc_con7, val);
-+	if (ret != 0)
-+		DRM_DEV_ERROR(lvds->dev, "Could not write to GRF: %d\n", ret);
-+
-+	pm_runtime_put(lvds->dev);
-+	clk_disable(lvds->pclk);
-+}
-+
-+static const struct drm_connector_funcs rockchip_lvds_connector_funcs = {
-+	.fill_modes = drm_helper_probe_single_connector_modes,
-+	.destroy = drm_connector_cleanup,
-+	.reset = drm_atomic_helper_connector_reset,
-+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-+};
-+
-+static int rockchip_lvds_connector_get_modes(struct drm_connector *connector)
-+{
-+	struct rockchip_lvds *lvds = connector_to_lvds(connector);
-+	struct drm_panel *panel = lvds->panel;
-+
-+	return drm_panel_get_modes(panel);
-+}
-+
-+static const
-+struct drm_connector_helper_funcs rockchip_lvds_connector_helper_funcs = {
-+	.get_modes = rockchip_lvds_connector_get_modes,
-+};
-+
-+static void rockchip_lvds_grf_config(struct drm_encoder *encoder,
-+				     struct drm_display_mode *mode)
-+{
-+	struct rockchip_lvds *lvds = encoder_to_lvds(encoder);
-+	u8 pin_hsync = (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1 : 0;
-+	u8 pin_dclk = (mode->flags & DRM_MODE_FLAG_PCSYNC) ? 1 : 0;
-+	u32 val;
-+	int ret;
-+
-+	/* iomux to LCD data/sync mode */
-+	if (lvds->output == DISPLAY_OUTPUT_RGB)
-+		if (lvds->pins && !IS_ERR(lvds->pins->default_state))
-+			pinctrl_select_state(lvds->pins->p,
-+					     lvds->pins->default_state);
-+	val = lvds->format | LVDS_CH0_EN;
-+	if (lvds->output == DISPLAY_OUTPUT_RGB)
-+		val |= LVDS_TTL_EN | LVDS_CH1_EN;
-+	else if (lvds->output == DISPLAY_OUTPUT_DUAL_LVDS)
-+		val |= LVDS_DUAL | LVDS_CH1_EN;
-+
-+	if ((mode->htotal - mode->hsync_start) & 0x01)
-+		val |= LVDS_START_PHASE_RST_1;
-+
-+	val |= (pin_dclk << 8) | (pin_hsync << 9);
-+	val |= (0xffff << 16);
-+	ret = regmap_write(lvds->grf, lvds->soc_data->grf_soc_con7, val);
-+	if (ret != 0) {
-+		DRM_DEV_ERROR(lvds->dev, "Could not write to GRF: %d\n", ret);
-+		return;
-+	}
-+}
-+
-+static int rockchip_lvds_set_vop_source(struct rockchip_lvds *lvds,
-+					struct drm_encoder *encoder)
-+{
-+	u32 val;
-+	int ret;
-+
-+	if (!lvds->soc_data->has_vop_sel)
-+		return 0;
-+
-+	ret = drm_of_encoder_active_endpoint_id(lvds->dev->of_node, encoder);
-+	if (ret < 0)
-+		return ret;
-+
-+	val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16;
-+	if (ret)
-+		val |= RK3288_LVDS_SOC_CON6_SEL_VOP_LIT;
-+
-+	ret = regmap_write(lvds->grf, lvds->soc_data->grf_soc_con6, val);
-+	if (ret < 0)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static int
-+rockchip_lvds_encoder_atomic_check(struct drm_encoder *encoder,
-+				   struct drm_crtc_state *crtc_state,
-+				   struct drm_connector_state *conn_state)
-+{
-+	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
-+
-+	s->output_mode = ROCKCHIP_OUT_MODE_P888;
-+	s->output_type = DRM_MODE_CONNECTOR_LVDS;
-+
-+	return 0;
-+}
-+
-+static void rockchip_lvds_encoder_enable(struct drm_encoder *encoder)
-+{
-+	struct rockchip_lvds *lvds = encoder_to_lvds(encoder);
-+	struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
-+	int ret;
-+
-+	drm_panel_prepare(lvds->panel);
-+	ret = rockchip_lvds_poweron(lvds);
-+	if (ret < 0) {
-+		DRM_DEV_ERROR(lvds->dev, "failed to power on lvds: %d\n", ret);
-+		drm_panel_unprepare(lvds->panel);
-+	}
-+	rockchip_lvds_grf_config(encoder, mode);
-+	rockchip_lvds_set_vop_source(lvds, encoder);
-+	drm_panel_enable(lvds->panel);
-+}
-+
-+static void rockchip_lvds_encoder_disable(struct drm_encoder *encoder)
-+{
-+	struct rockchip_lvds *lvds = encoder_to_lvds(encoder);
-+
-+	drm_panel_disable(lvds->panel);
-+	rockchip_lvds_poweroff(lvds);
-+	drm_panel_unprepare(lvds->panel);
-+}
-+
-+static const
-+struct drm_encoder_helper_funcs rockchip_lvds_encoder_helper_funcs = {
-+	.enable = rockchip_lvds_encoder_enable,
-+	.disable = rockchip_lvds_encoder_disable,
-+	.atomic_check = rockchip_lvds_encoder_atomic_check,
-+};
-+
-+static const struct drm_encoder_funcs rockchip_lvds_encoder_funcs = {
-+	.destroy = drm_encoder_cleanup,
-+};
-+
-+static const struct rockchip_lvds_soc_data rk3288_lvds_data = {
-+	.ch1_offset = 0x100,
-+	.grf_soc_con6 = 0x025c,
-+	.grf_soc_con7 = 0x0260,
-+	.has_vop_sel = true,
-+};
-+
-+static const struct of_device_id rockchip_lvds_dt_ids[] = {
-+	{
-+		.compatible = "rockchip,rk3288-lvds",
-+		.data = &rk3288_lvds_data
-+	},
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, rockchip_lvds_dt_ids);
-+
-+static int rockchip_lvds_bind(struct device *dev, struct device *master,
-+			      void *data)
-+{
-+	struct rockchip_lvds *lvds = dev_get_drvdata(dev);
-+	struct drm_device *drm_dev = data;
-+	struct drm_encoder *encoder;
-+	struct drm_connector *connector;
-+	struct device_node *remote = NULL;
-+	struct device_node  *port, *endpoint;
-+	int ret = 0, child_count = 0;
-+	const char *name;
-+	u32 endpoint_id;
-+
-+	lvds->drm_dev = drm_dev;
-+	port = of_graph_get_port_by_id(dev->of_node, 1);
-+	if (!port) {
-+		DRM_DEV_ERROR(dev,
-+			      "can't found port point, please init lvds panel port!\n");
-+		return -EINVAL;
-+	}
-+	for_each_child_of_node(port, endpoint) {
-+		child_count++;
-+		of_property_read_u32(endpoint, "reg", &endpoint_id);
-+		ret = drm_of_find_panel_or_bridge(dev->of_node, 1, endpoint_id,
-+						  &lvds->panel, &lvds->bridge);
-+		if (!ret)
-+			break;
-+	}
-+	if (!child_count) {
-+		DRM_DEV_ERROR(dev, "lvds port does not have any children\n");
-+		ret = -EINVAL;
-+		goto err_put_port;
-+	} else if (ret) {
-+		DRM_DEV_ERROR(dev, "failed to find panel and bridge node\n");
-+		ret = -EPROBE_DEFER;
-+		goto err_put_port;
-+	}
-+	if (lvds->panel)
-+		remote = lvds->panel->dev->of_node;
-+	else
-+		remote = lvds->bridge->of_node;
-+	if (of_property_read_string(dev->of_node, "rockchip,output", &name))
-+		/* default set it as output rgb */
-+		lvds->output = DISPLAY_OUTPUT_RGB;
-+	else
-+		lvds->output = lvds_name_to_output(name);
-+
-+	if (lvds->output < 0) {
-+		DRM_DEV_ERROR(dev, "invalid output type [%s]\n", name);
-+		ret = lvds->output;
-+		goto err_put_remote;
-+	}
-+
-+	if (of_property_read_string(remote, "data-mapping", &name))
-+		/* default set it as format vesa 18 */
-+		lvds->format = LVDS_VESA_18;
-+	else
-+		lvds->format = lvds_name_to_format(name);
-+
-+	if (lvds->format < 0) {
-+		DRM_DEV_ERROR(dev, "invalid data-mapping format [%s]\n", name);
-+		ret = lvds->format;
-+		goto err_put_remote;
-+	}
-+
-+	encoder = &lvds->encoder;
-+	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
-+							     dev->of_node);
-+
-+	ret = drm_encoder_init(drm_dev, encoder, &rockchip_lvds_encoder_funcs,
-+			       DRM_MODE_ENCODER_LVDS, NULL);
-+	if (ret < 0) {
-+		DRM_DEV_ERROR(drm_dev->dev,
-+			      "failed to initialize encoder: %d\n", ret);
-+		goto err_put_remote;
-+	}
-+
-+	drm_encoder_helper_add(encoder, &rockchip_lvds_encoder_helper_funcs);
-+
-+	if (lvds->panel) {
-+		connector = &lvds->connector;
-+		connector->dpms = DRM_MODE_DPMS_OFF;
-+		ret = drm_connector_init(drm_dev, connector,
-+					 &rockchip_lvds_connector_funcs,
-+					 DRM_MODE_CONNECTOR_LVDS);
-+		if (ret < 0) {
-+			DRM_DEV_ERROR(drm_dev->dev,
-+				      "failed to initialize connector: %d\n", ret);
-+			goto err_free_encoder;
-+		}
-+
-+		drm_connector_helper_add(connector,
-+					 &rockchip_lvds_connector_helper_funcs);
-+
-+		ret = drm_mode_connector_attach_encoder(connector, encoder);
-+		if (ret < 0) {
-+			DRM_DEV_ERROR(drm_dev->dev,
-+				      "failed to attach encoder: %d\n", ret);
-+			goto err_free_connector;
-+		}
-+
-+		ret = drm_panel_attach(lvds->panel, connector);
-+		if (ret < 0) {
-+			DRM_DEV_ERROR(drm_dev->dev,
-+				      "failed to attach panel: %d\n", ret);
-+			goto err_free_connector;
-+		}
-+	} else {
-+		lvds->bridge->encoder = encoder;
-+		ret = drm_bridge_attach(encoder, lvds->bridge, NULL);
-+		if (ret) {
-+			DRM_DEV_ERROR(drm_dev->dev,
-+				      "failed to attach bridge: %d\n", ret);
-+			goto err_free_encoder;
-+		}
-+		encoder->bridge = lvds->bridge;
-+	}
-+
-+	pm_runtime_enable(dev);
-+	of_node_put(remote);
-+	of_node_put(port);
-+
-+	return 0;
-+
-+err_free_connector:
-+	drm_connector_cleanup(connector);
-+err_free_encoder:
-+	drm_encoder_cleanup(encoder);
-+err_put_remote:
-+	of_node_put(remote);
-+err_put_port:
-+	of_node_put(port);
-+
-+	return ret;
-+}
-+
-+static void rockchip_lvds_unbind(struct device *dev, struct device *master,
-+				void *data)
-+{
-+	struct rockchip_lvds *lvds = dev_get_drvdata(dev);
-+
-+	rockchip_lvds_encoder_disable(&lvds->encoder);
-+	if (lvds->panel)
-+		drm_panel_detach(lvds->panel);
-+	pm_runtime_disable(dev);
-+	drm_connector_cleanup(&lvds->connector);
-+	drm_encoder_cleanup(&lvds->encoder);
-+}
-+
-+static const struct component_ops rockchip_lvds_component_ops = {
-+	.bind = rockchip_lvds_bind,
-+	.unbind = rockchip_lvds_unbind,
-+};
-+
-+static int rockchip_lvds_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct rockchip_lvds *lvds;
-+	const struct of_device_id *match;
-+	struct resource *res;
-+	int ret;
-+
-+	if (!dev->of_node)
-+		return -ENODEV;
-+
-+	lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
-+	if (!lvds)
-+		return -ENOMEM;
-+
-+	lvds->dev = dev;
-+	match = of_match_node(rockchip_lvds_dt_ids, dev->of_node);
-+	if (!match)
-+		return -ENODEV;
-+	lvds->soc_data = match->data;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	lvds->regs = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(lvds->regs))
-+		return PTR_ERR(lvds->regs);
-+
-+	lvds->pclk = devm_clk_get(&pdev->dev, "pclk_lvds");
-+	if (IS_ERR(lvds->pclk)) {
-+		DRM_DEV_ERROR(dev, "could not get pclk_lvds\n");
-+		return PTR_ERR(lvds->pclk);
-+	}
-+
-+	lvds->pins = devm_kzalloc(lvds->dev, sizeof(*lvds->pins),
-+				  GFP_KERNEL);
-+	if (!lvds->pins)
-+		return -ENOMEM;
-+
-+	lvds->pins->p = devm_pinctrl_get(lvds->dev);
-+	if (IS_ERR(lvds->pins->p)) {
-+		DRM_DEV_ERROR(dev, "no pinctrl handle\n");
-+		devm_kfree(lvds->dev, lvds->pins);
-+		lvds->pins = NULL;
-+	} else {
-+		lvds->pins->default_state =
-+			pinctrl_lookup_state(lvds->pins->p, "lcdc");
-+		if (IS_ERR(lvds->pins->default_state)) {
-+			DRM_DEV_ERROR(dev, "no default pinctrl state\n");
-+			devm_kfree(lvds->dev, lvds->pins);
-+			lvds->pins = NULL;
-+		}
-+	}
-+
-+	lvds->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
-+						    "rockchip,grf");
-+	if (IS_ERR(lvds->grf)) {
-+		DRM_DEV_ERROR(dev, "missing rockchip,grf property\n");
-+		return PTR_ERR(lvds->grf);
-+	}
-+
-+	dev_set_drvdata(dev, lvds);
-+
-+	ret = clk_prepare(lvds->pclk);
-+	if (ret < 0) {
-+		DRM_DEV_ERROR(dev, "failed to prepare pclk_lvds\n");
-+		return ret;
-+	}
-+	ret = component_add(&pdev->dev, &rockchip_lvds_component_ops);
-+	if (ret < 0) {
-+		DRM_DEV_ERROR(dev, "failed to add component\n");
-+		clk_unprepare(lvds->pclk);
-+	}
-+
-+	return ret;
-+}
-+
-+static int rockchip_lvds_remove(struct platform_device *pdev)
-+{
-+	struct rockchip_lvds *lvds = dev_get_drvdata(&pdev->dev);
-+
-+	component_del(&pdev->dev, &rockchip_lvds_component_ops);
-+	clk_unprepare(lvds->pclk);
-+
-+	return 0;
-+}
-+
-+struct platform_driver rockchip_lvds_driver = {
-+	.probe = rockchip_lvds_probe,
-+	.remove = rockchip_lvds_remove,
-+	.driver = {
-+		   .name = "rockchip-lvds",
-+		   .of_match_table = of_match_ptr(rockchip_lvds_dt_ids),
-+	},
-+};
---- linux-4.14/drivers/gpu/drm/rockchip/rockchip_lvds.h.0130~	2017-12-14 06:39:58.522903642 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/rockchip_lvds.h	2017-12-14 06:39:58.522903642 +0100
-@@ -0,0 +1,114 @@
-+/*
-+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
-+ * Author:
-+ *      Sandy Huang <hjc@rock-chips.com>
-+ *      Mark Yao <mark.yao@rock-chips.com>
-+ *
-+ * This software is licensed under the terms of the GNU General Public
-+ * License version 2, as published by the Free Software Foundation, and
-+ * may be copied, distributed, and modified under those terms.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef _ROCKCHIP_LVDS_
-+#define _ROCKCHIP_LVDS_
-+
-+#define RK3288_LVDS_CH0_REG0			0x00
-+#define RK3288_LVDS_CH0_REG0_LVDS_EN		BIT(7)
-+#define RK3288_LVDS_CH0_REG0_TTL_EN		BIT(6)
-+#define RK3288_LVDS_CH0_REG0_LANECK_EN		BIT(5)
-+#define RK3288_LVDS_CH0_REG0_LANE4_EN		BIT(4)
-+#define RK3288_LVDS_CH0_REG0_LANE3_EN		BIT(3)
-+#define RK3288_LVDS_CH0_REG0_LANE2_EN		BIT(2)
-+#define RK3288_LVDS_CH0_REG0_LANE1_EN		BIT(1)
-+#define RK3288_LVDS_CH0_REG0_LANE0_EN		BIT(0)
-+
-+#define RK3288_LVDS_CH0_REG1			0x04
-+#define RK3288_LVDS_CH0_REG1_LANECK_BIAS	BIT(5)
-+#define RK3288_LVDS_CH0_REG1_LANE4_BIAS		BIT(4)
-+#define RK3288_LVDS_CH0_REG1_LANE3_BIAS		BIT(3)
-+#define RK3288_LVDS_CH0_REG1_LANE2_BIAS		BIT(2)
-+#define RK3288_LVDS_CH0_REG1_LANE1_BIAS		BIT(1)
-+#define RK3288_LVDS_CH0_REG1_LANE0_BIAS		BIT(0)
-+
-+#define RK3288_LVDS_CH0_REG2			0x08
-+#define RK3288_LVDS_CH0_REG2_RESERVE_ON		BIT(7)
-+#define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE	BIT(6)
-+#define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE	BIT(5)
-+#define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE	BIT(4)
-+#define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE	BIT(3)
-+#define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE	BIT(2)
-+#define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE	BIT(1)
-+#define RK3288_LVDS_CH0_REG2_PLL_FBDIV8		BIT(0)
-+
-+#define RK3288_LVDS_CH0_REG3			0x0c
-+#define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK	0xff
-+
-+#define RK3288_LVDS_CH0_REG4			0x10
-+#define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE	BIT(5)
-+#define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE	BIT(4)
-+#define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE	BIT(3)
-+#define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE	BIT(2)
-+#define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE	BIT(1)
-+#define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE	BIT(0)
-+
-+#define RK3288_LVDS_CH0_REG5			0x14
-+#define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA	BIT(5)
-+#define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA	BIT(4)
-+#define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA	BIT(3)
-+#define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA	BIT(2)
-+#define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA	BIT(1)
-+#define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA	BIT(0)
-+
-+#define RK3288_LVDS_CFG_REGC			0x30
-+#define RK3288_LVDS_CFG_REGC_PLL_ENABLE		0x00
-+#define RK3288_LVDS_CFG_REGC_PLL_DISABLE	0xff
-+
-+#define RK3288_LVDS_CH0_REGD			0x34
-+#define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK	0x1f
-+
-+#define RK3288_LVDS_CH0_REG20			0x80
-+#define RK3288_LVDS_CH0_REG20_MSB		0x45
-+#define RK3288_LVDS_CH0_REG20_LSB		0x44
-+
-+#define RK3288_LVDS_CFG_REG21			0x84
-+#define RK3288_LVDS_CFG_REG21_TX_ENABLE		0x92
-+#define RK3288_LVDS_CFG_REG21_TX_DISABLE	0x00
-+#define RK3288_LVDS_CH1_OFFSET                 0x100
-+
-+/* fbdiv value is split over 2 registers, with bit8 in reg2 */
-+#define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \
-+		(_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0)
-+#define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \
-+		(_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK)
-+#define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \
-+		(_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK)
-+
-+#define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT	BIT(3)
-+
-+#define LVDS_FMT_MASK				(0x07 << 16)
-+#define LVDS_MSB				BIT(3)
-+#define LVDS_DUAL				BIT(4)
-+#define LVDS_FMT_1				BIT(5)
-+#define LVDS_TTL_EN				BIT(6)
-+#define LVDS_START_PHASE_RST_1			BIT(7)
-+#define LVDS_DCLK_INV				BIT(8)
-+#define LVDS_CH0_EN				BIT(11)
-+#define LVDS_CH1_EN				BIT(12)
-+#define LVDS_PWRDN				BIT(15)
-+
-+#define LVDS_24BIT				(0 << 1)
-+#define LVDS_18BIT				(1 << 1)
-+#define LVDS_FORMAT_VESA			(0 << 0)
-+#define LVDS_FORMAT_JEIDA			(1 << 0)
-+
-+#define LVDS_VESA_24				0
-+#define LVDS_JEIDA_24				1
-+#define LVDS_VESA_18				2
-+#define LVDS_JEIDA_18				3
-+
-+#endif /* _ROCKCHIP_LVDS_ */
---- linux-4.14/drivers/gpu/drm/rockchip/rockchip_vop_reg.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/rockchip/rockchip_vop_reg.c	2017-12-14 06:39:58.522903642 +0100
-@@ -533,7 +533,7 @@ static int vop_probe(struct platform_dev
- 	struct device *dev = &pdev->dev;
- 
- 	if (!dev->of_node) {
--		dev_err(dev, "can't find vop devices\n");
-+		DRM_DEV_ERROR(dev, "can't find vop devices\n");
- 		return -ENODEV;
- 	}
- 
---- linux-4.14/drivers/gpu/drm/shmobile/shmob_drm_kms.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/shmobile/shmob_drm_kms.c	2017-12-14 06:39:58.522903642 +0100
-@@ -16,6 +16,7 @@
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_fb_cma_helper.h>
- #include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- 
- #include <video/sh_mobile_meram.h>
- 
-@@ -131,7 +132,7 @@ shmob_drm_fb_create(struct drm_device *d
- 		}
- 	}
- 
--	return drm_fb_cma_create(dev, file_priv, mode_cmd);
-+	return drm_gem_fb_create(dev, file_priv, mode_cmd);
- }
- 
- static const struct drm_mode_config_funcs shmob_drm_mode_config_funcs = {
---- linux-4.14/drivers/gpu/drm/sti/sti_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/sti/sti_drv.c	2017-12-14 06:39:58.522903642 +0100
-@@ -16,6 +16,7 @@
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drm_fb_cma_helper.h>
- #include <drm/drm_of.h>
- 
-@@ -145,7 +146,7 @@ static void sti_output_poll_changed(stru
- }
- 
- static const struct drm_mode_config_funcs sti_mode_config_funcs = {
--	.fb_create = drm_fb_cma_create,
-+	.fb_create = drm_gem_fb_create,
- 	.output_poll_changed = sti_output_poll_changed,
- 	.atomic_check = sti_atomic_check,
- 	.atomic_commit = drm_atomic_helper_commit,
---- linux-4.14/drivers/gpu/drm/sti/sti_dvo.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/sti/sti_dvo.c	2017-12-14 06:39:58.522903642 +0100
-@@ -463,11 +463,7 @@ static int sti_dvo_bind(struct device *d
- 	bridge->driver_private = dvo;
- 	bridge->funcs = &sti_dvo_bridge_funcs;
- 	bridge->of_node = dvo->dev.of_node;
--	err = drm_bridge_add(bridge);
--	if (err) {
--		DRM_ERROR("Failed to add bridge\n");
--		return err;
--	}
-+	drm_bridge_add(bridge);
- 
- 	err = drm_bridge_attach(encoder, bridge, NULL);
- 	if (err) {
---- linux-4.14/drivers/gpu/drm/stm/drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/stm/drv.c	2017-12-14 06:39:58.522903642 +0100
-@@ -17,6 +17,7 @@
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_fb_cma_helper.h>
- #include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- 
- #include "ltdc.h"
- 
-@@ -31,7 +32,7 @@ static void drv_output_poll_changed(stru
- }
- 
- static const struct drm_mode_config_funcs drv_mode_config_funcs = {
--	.fb_create = drm_fb_cma_create,
-+	.fb_create = drm_gem_fb_create,
- 	.output_poll_changed = drv_output_poll_changed,
- 	.atomic_check = drm_atomic_helper_check,
- 	.atomic_commit = drm_atomic_helper_commit,
---- linux-4.14/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c	2017-12-14 06:39:58.522903642 +0100
-@@ -113,11 +113,13 @@ static enum dsi_color dsi_color_from_mip
- 
- static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
- {
-+	int divisor = idf * odf;
-+
- 	/* prevent from division by 0 */
--	if (idf * odf)
--		return DIV_ROUND_CLOSEST(clkin_khz * ndiv, idf * odf);
-+	if (!divisor)
-+		return 0;
- 
--	return 0;
-+	return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor);
- }
- 
- static int dsi_pll_get_params(int clkin_khz, int clkout_khz,
---- linux-4.14/drivers/gpu/drm/stm/ltdc.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/stm/ltdc.c	2017-12-14 06:39:58.522903642 +0100
-@@ -791,9 +791,8 @@ static const struct drm_encoder_funcs lt
- 	.destroy = drm_encoder_cleanup,
- };
- 
--static int ltdc_encoder_init(struct drm_device *ddev)
-+static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge)
- {
--	struct ltdc_device *ldev = ddev->dev_private;
- 	struct drm_encoder *encoder;
- 	int ret;
- 
-@@ -807,7 +806,7 @@ static int ltdc_encoder_init(struct drm_
- 	drm_encoder_init(ddev, encoder, &ltdc_encoder_funcs,
- 			 DRM_MODE_ENCODER_DPI, NULL);
- 
--	ret = drm_bridge_attach(encoder, ldev->bridge, NULL);
-+	ret = drm_bridge_attach(encoder, bridge, NULL);
- 	if (ret) {
- 		drm_encoder_cleanup(encoder);
- 		return -EINVAL;
-@@ -936,12 +935,9 @@ int ltdc_load(struct drm_device *ddev)
- 			ret = PTR_ERR(bridge);
- 			goto err;
- 		}
--		ldev->is_panel_bridge = true;
- 	}
- 
--	ldev->bridge = bridge;
--
--	ret = ltdc_encoder_init(ddev);
-+	ret = ltdc_encoder_init(ddev, bridge);
- 	if (ret) {
- 		DRM_ERROR("Failed to init encoder\n");
- 		goto err;
-@@ -972,8 +968,7 @@ int ltdc_load(struct drm_device *ddev)
- 	return 0;
- 
- err:
--	if (ldev->is_panel_bridge)
--		drm_panel_bridge_remove(bridge);
-+	drm_panel_bridge_remove(bridge);
- 
- 	clk_disable_unprepare(ldev->pixel_clk);
- 
-@@ -986,8 +981,7 @@ void ltdc_unload(struct drm_device *ddev
- 
- 	DRM_DEBUG_DRIVER("\n");
- 
--	if (ldev->is_panel_bridge)
--		drm_panel_bridge_remove(ldev->bridge);
-+	drm_of_panel_bridge_remove(ddev->dev->of_node, 0, 0);
- 
- 	clk_disable_unprepare(ldev->pixel_clk);
- }
---- linux-4.14/drivers/gpu/drm/stm/ltdc.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/stm/ltdc.h	2017-12-14 06:39:58.522903642 +0100
-@@ -24,8 +24,6 @@ struct ltdc_device {
- 	struct drm_fbdev_cma *fbdev;
- 	void __iomem *regs;
- 	struct clk *pixel_clk;	/* lcd pixel clock */
--	struct drm_bridge *bridge;
--	bool is_panel_bridge;
- 	struct mutex err_lock;	/* protecting error_status */
- 	struct ltdc_caps caps;
- 	u32 error_status;
---- linux-4.14/drivers/gpu/drm/sun4i/sun4i_backend.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/sun4i/sun4i_backend.c	2017-12-14 06:39:58.522903642 +0100
-@@ -209,22 +209,11 @@ int sun4i_backend_update_layer_buffer(st
- {
- 	struct drm_plane_state *state = plane->state;
- 	struct drm_framebuffer *fb = state->fb;
--	struct drm_gem_cma_object *gem;
- 	u32 lo_paddr, hi_paddr;
- 	dma_addr_t paddr;
--	int bpp;
--
--	/* Get the physical address of the buffer in memory */
--	gem = drm_fb_cma_get_gem_obj(fb, 0);
--
--	DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
--
--	/* Compute the start of the displayed memory */
--	bpp = fb->format->cpp[0];
--	paddr = gem->paddr + fb->offsets[0];
--	paddr += (state->src_x >> 16) * bpp;
--	paddr += (state->src_y >> 16) * fb->pitches[0];
- 
-+	/* Get the start of the displayed memory */
-+	paddr = drm_fb_cma_get_gem_addr(fb, state, 0);
- 	DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
- 
- 	/* Write the 32 lower bits of the address (in bits) */
-@@ -369,13 +358,6 @@ static int sun4i_backend_bind(struct dev
- 	if (IS_ERR(regs))
- 		return PTR_ERR(regs);
- 
--	backend->engine.regs = devm_regmap_init_mmio(dev, regs,
--						     &sun4i_backend_regmap_config);
--	if (IS_ERR(backend->engine.regs)) {
--		dev_err(dev, "Couldn't create the backend regmap\n");
--		return PTR_ERR(backend->engine.regs);
--	}
--
- 	backend->reset = devm_reset_control_get(dev, NULL);
- 	if (IS_ERR(backend->reset)) {
- 		dev_err(dev, "Couldn't get our reset line\n");
-@@ -421,9 +403,23 @@ static int sun4i_backend_bind(struct dev
- 		}
- 	}
- 
-+	backend->engine.regs = devm_regmap_init_mmio(dev, regs,
-+						     &sun4i_backend_regmap_config);
-+	if (IS_ERR(backend->engine.regs)) {
-+		dev_err(dev, "Couldn't create the backend regmap\n");
-+		return PTR_ERR(backend->engine.regs);
-+	}
-+
- 	list_add_tail(&backend->engine.list, &drv->engine_list);
- 
--	/* Reset the registers */
-+	/*
-+	 * Many of the backend's layer configuration registers have
-+	 * undefined default values. This poses a risk as we use
-+	 * regmap_update_bits in some places, and don't overwrite
-+	 * the whole register.
-+	 *
-+	 * Clear the registers here to have something predictable.
-+	 */
- 	for (i = 0x800; i < 0x1000; i += 4)
- 		regmap_write(backend->engine.regs, i, 0);
- 
---- linux-4.14/drivers/gpu/drm/sun4i/sun4i_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/sun4i/sun4i_drv.c	2017-12-14 06:39:58.522903642 +0100
-@@ -106,11 +106,6 @@ static int sun4i_drv_bind(struct device
- 		goto free_drm;
- 	}
- 
--	/* drm_vblank_init calls kcalloc, which can fail */
--	ret = drm_vblank_init(drm, 1);
--	if (ret)
--		goto free_mem_region;
--
- 	drm_mode_config_init(drm);
- 
- 	ret = component_bind_all(drm->dev, drm);
-@@ -119,6 +114,11 @@ static int sun4i_drv_bind(struct device
- 		goto cleanup_mode_config;
- 	}
- 
-+	/* drm_vblank_init calls kcalloc, which can fail */
-+	ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
-+	if (ret)
-+		goto free_mem_region;
-+
- 	drm->irq_enabled = true;
- 
- 	/* Remove early framebuffers (ie. simplefb) */
-@@ -200,11 +200,51 @@ static int compare_of(struct device *dev
- 	return dev->of_node == data;
- }
- 
-+/*
-+ * The encoder drivers use drm_of_find_possible_crtcs to get upstream
-+ * crtcs from the device tree using of_graph. For the results to be
-+ * correct, encoders must be probed/bound after _all_ crtcs have been
-+ * created. The existing code uses a depth first recursive traversal
-+ * of the of_graph, which means the encoders downstream of the TCON
-+ * get add right after the first TCON. The second TCON or CRTC will
-+ * never be properly associated with encoders connected to it.
-+ *
-+ * Also, in a dual display pipeline setup, both frontends can feed
-+ * either backend, and both backends can feed either TCON, we want
-+ * all components of the same type to be added before the next type
-+ * in the pipeline. Fortunately, the pipelines are perfectly symmetric,
-+ * i.e. components of the same type are at the same depth when counted
-+ * from the frontend. The only exception is the third pipeline in
-+ * the A80 SoC, which we do not support anyway.
-+ *
-+ * Hence we can use a breadth first search traversal order to add
-+ * components. We do not need to check for duplicates. The component
-+ * matching system handles this for us.
-+ */
-+struct endpoint_list {
-+	struct device_node *node;
-+	struct list_head list;
-+};
-+
-+static bool node_is_in_list(struct list_head *endpoints,
-+			    struct device_node *node)
-+{
-+	struct endpoint_list *endpoint;
-+
-+	list_for_each_entry(endpoint, endpoints, list)
-+		if (endpoint->node == node)
-+			return true;
-+
-+	return false;
-+}
-+
- static int sun4i_drv_add_endpoints(struct device *dev,
-+				   struct list_head *endpoints,
- 				   struct component_match **match,
- 				   struct device_node *node)
- {
- 	struct device_node *port, *ep, *remote;
-+	struct endpoint_list *endpoint;
- 	int count = 0;
- 
- 	/*
-@@ -264,10 +304,19 @@ static int sun4i_drv_add_endpoints(struc
- 			}
- 		}
- 
--		/* Walk down our tree */
--		count += sun4i_drv_add_endpoints(dev, match, remote);
-+		/* skip downstream node if it is already in the queue */
-+		if (node_is_in_list(endpoints, remote))
-+			continue;
- 
--		of_node_put(remote);
-+		/* Add downstream nodes to the queue */
-+		endpoint = kzalloc(sizeof(*endpoint), GFP_KERNEL);
-+		if (!endpoint) {
-+			of_node_put(remote);
-+			return -ENOMEM;
-+		}
-+
-+		endpoint->node = remote;
-+		list_add_tail(&endpoint->list, endpoints);
- 	}
- 
- 	return count;
-@@ -277,7 +326,9 @@ static int sun4i_drv_probe(struct platfo
- {
- 	struct component_match *match = NULL;
- 	struct device_node *np = pdev->dev.of_node;
--	int i, count = 0;
-+	struct endpoint_list *endpoint, *endpoint_temp;
-+	int i, ret, count = 0;
-+	LIST_HEAD(endpoints);
- 
- 	for (i = 0;; i++) {
- 		struct device_node *pipeline = of_parse_phandle(np,
-@@ -286,12 +337,31 @@ static int sun4i_drv_probe(struct platfo
- 		if (!pipeline)
- 			break;
- 
--		count += sun4i_drv_add_endpoints(&pdev->dev, &match,
--						pipeline);
--		of_node_put(pipeline);
-+		endpoint = kzalloc(sizeof(*endpoint), GFP_KERNEL);
-+		if (!endpoint) {
-+			ret = -ENOMEM;
-+			goto err_free_endpoints;
-+		}
- 
--		DRM_DEBUG_DRIVER("Queued %d outputs on pipeline %d\n",
--				 count, i);
-+		endpoint->node = pipeline;
-+		list_add_tail(&endpoint->list, &endpoints);
-+	}
-+
-+	list_for_each_entry_safe(endpoint, endpoint_temp, &endpoints, list) {
-+		/* process this endpoint */
-+		ret = sun4i_drv_add_endpoints(&pdev->dev, &endpoints, &match,
-+					      endpoint->node);
-+
-+		/* sun4i_drv_add_endpoints can fail to allocate memory */
-+		if (ret < 0)
-+			goto err_free_endpoints;
-+
-+		count += ret;
-+
-+		/* delete and cleanup the current entry */
-+		list_del(&endpoint->list);
-+		of_node_put(endpoint->node);
-+		kfree(endpoint);
- 	}
- 
- 	if (count)
-@@ -300,6 +370,15 @@ static int sun4i_drv_probe(struct platfo
- 						       match);
- 	else
- 		return 0;
-+
-+err_free_endpoints:
-+	list_for_each_entry_safe(endpoint, endpoint_temp, &endpoints, list) {
-+		list_del(&endpoint->list);
-+		of_node_put(endpoint->node);
-+		kfree(endpoint);
-+	}
-+
-+	return ret;
- }
- 
- static int sun4i_drv_remove(struct platform_device *pdev)
---- linux-4.14/drivers/gpu/drm/sun4i/sun4i_framebuffer.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/sun4i/sun4i_framebuffer.c	2017-12-14 06:39:58.522903642 +0100
-@@ -12,6 +12,7 @@
- 
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_fb_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drmP.h>
- 
- #include "sun4i_drv.h"
-@@ -28,7 +29,7 @@ static const struct drm_mode_config_func
- 	.output_poll_changed	= sun4i_de_output_poll_changed,
- 	.atomic_check		= drm_atomic_helper_check,
- 	.atomic_commit		= drm_atomic_helper_commit,
--	.fb_create		= drm_fb_cma_create,
-+	.fb_create		= drm_gem_fb_create,
- };
- 
- struct drm_fbdev_cma *sun4i_framebuffer_init(struct drm_device *drm)
---- linux-4.14/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c	2017-12-14 06:39:58.523903643 +0100
-@@ -11,6 +11,7 @@
-  */
- 
- #include <linux/clk-provider.h>
-+#include <linux/regmap.h>
- 
- #include "sun4i_tcon.h"
- #include "sun4i_hdmi.h"
-@@ -18,6 +19,9 @@
- struct sun4i_ddc {
- 	struct clk_hw		hw;
- 	struct sun4i_hdmi	*hdmi;
-+	struct regmap_field	*reg;
-+	u8			pre_div;
-+	u8			m_offset;
- };
- 
- static inline struct sun4i_ddc *hw_to_ddc(struct clk_hw *hw)
-@@ -27,6 +31,8 @@ static inline struct sun4i_ddc *hw_to_dd
- 
- static unsigned long sun4i_ddc_calc_divider(unsigned long rate,
- 					    unsigned long parent_rate,
-+					    const u8 pre_div,
-+					    const u8 m_offset,
- 					    u8 *m, u8 *n)
- {
- 	unsigned long best_rate = 0;
-@@ -36,7 +42,8 @@ static unsigned long sun4i_ddc_calc_divi
- 		for (_n = 0; _n < 8; _n++) {
- 			unsigned long tmp_rate;
- 
--			tmp_rate = (((parent_rate / 2) / 10) >> _n) / (_m + 1);
-+			tmp_rate = (((parent_rate / pre_div) / 10) >> _n) /
-+				(_m + m_offset);
- 
- 			if (tmp_rate > rate)
- 				continue;
-@@ -60,21 +67,25 @@ static unsigned long sun4i_ddc_calc_divi
- static long sun4i_ddc_round_rate(struct clk_hw *hw, unsigned long rate,
- 				 unsigned long *prate)
- {
--	return sun4i_ddc_calc_divider(rate, *prate, NULL, NULL);
-+	struct sun4i_ddc *ddc = hw_to_ddc(hw);
-+
-+	return sun4i_ddc_calc_divider(rate, *prate, ddc->pre_div,
-+				      ddc->m_offset, NULL, NULL);
- }
- 
- static unsigned long sun4i_ddc_recalc_rate(struct clk_hw *hw,
- 					    unsigned long parent_rate)
- {
- 	struct sun4i_ddc *ddc = hw_to_ddc(hw);
--	u32 reg;
-+	unsigned int reg;
- 	u8 m, n;
- 
--	reg = readl(ddc->hdmi->base + SUN4I_HDMI_DDC_CLK_REG);
--	m = (reg >> 3) & 0x7;
-+	regmap_field_read(ddc->reg, &reg);
-+	m = (reg >> 3) & 0xf;
- 	n = reg & 0x7;
- 
--	return (((parent_rate / 2) / 10) >> n) / (m + 1);
-+	return (((parent_rate / ddc->pre_div) / 10) >> n) /
-+	       (m + ddc->m_offset);
- }
- 
- static int sun4i_ddc_set_rate(struct clk_hw *hw, unsigned long rate,
-@@ -83,10 +94,12 @@ static int sun4i_ddc_set_rate(struct clk
- 	struct sun4i_ddc *ddc = hw_to_ddc(hw);
- 	u8 div_m, div_n;
- 
--	sun4i_ddc_calc_divider(rate, parent_rate, &div_m, &div_n);
-+	sun4i_ddc_calc_divider(rate, parent_rate, ddc->pre_div,
-+			       ddc->m_offset, &div_m, &div_n);
- 
--	writel(SUN4I_HDMI_DDC_CLK_M(div_m) | SUN4I_HDMI_DDC_CLK_N(div_n),
--	       ddc->hdmi->base + SUN4I_HDMI_DDC_CLK_REG);
-+	regmap_field_write(ddc->reg,
-+			   SUN4I_HDMI_DDC_CLK_M(div_m) |
-+			   SUN4I_HDMI_DDC_CLK_N(div_n));
- 
- 	return 0;
- }
-@@ -111,6 +124,11 @@ int sun4i_ddc_create(struct sun4i_hdmi *
- 	if (!ddc)
- 		return -ENOMEM;
- 
-+	ddc->reg = devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					   hdmi->variant->ddc_clk_reg);
-+	if (IS_ERR(ddc->reg))
-+		return PTR_ERR(ddc->reg);
-+
- 	init.name = "hdmi-ddc";
- 	init.ops = &sun4i_ddc_ops;
- 	init.parent_names = &parent_name;
-@@ -118,6 +136,8 @@ int sun4i_ddc_create(struct sun4i_hdmi *
- 
- 	ddc->hdmi = hdmi;
- 	ddc->hw.init = &init;
-+	ddc->pre_div = hdmi->variant->ddc_clk_pre_divider;
-+	ddc->m_offset = hdmi->variant->ddc_clk_m_offset;
- 
- 	hdmi->ddc_clk = devm_clk_register(hdmi->dev, &ddc->hw);
- 	if (IS_ERR(hdmi->ddc_clk))
---- linux-4.14/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c	2017-12-14 06:39:58.523903643 +0100
-@@ -20,8 +20,11 @@
- #include <linux/clk.h>
- #include <linux/component.h>
- #include <linux/iopoll.h>
-+#include <linux/of_device.h>
- #include <linux/platform_device.h>
- #include <linux/pm_runtime.h>
-+#include <linux/regmap.h>
-+#include <linux/reset.h>
- 
- #include "sun4i_backend.h"
- #include "sun4i_crtc.h"
-@@ -141,6 +144,22 @@ static void sun4i_hdmi_mode_set(struct d
- 	writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC,
- 	       hdmi->base + SUN4I_HDMI_UNKNOWN_REG);
- 
-+	/*
-+	 * Setup output pad (?) controls
-+	 *
-+	 * This is done here instead of at probe/bind time because
-+	 * the controller seems to toggle some of the bits on its own.
-+	 *
-+	 * We can't just initialize the register there, we need to
-+	 * protect the clock bits that have already been read out and
-+	 * cached by the clock framework.
-+	 */
-+	val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
-+	val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
-+	val |= hdmi->variant->pad_ctrl1_init_val;
-+	writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
-+	val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
-+
- 	/* Setup timing registers */
- 	writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) |
- 	       SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay),
-@@ -267,6 +286,124 @@ static const struct cec_pin_ops sun4i_hd
- };
- #endif
- 
-+#define SUN4I_HDMI_PAD_CTRL1_MASK	(GENMASK(24, 7) | GENMASK(5, 0))
-+#define SUN4I_HDMI_PLL_CTRL_MASK	(GENMASK(31, 8) | GENMASK(3, 0))
-+
-+static const struct sun4i_hdmi_variant sun5i_variant = {
-+	.pad_ctrl0_init_val	= SUN4I_HDMI_PAD_CTRL0_TXEN |
-+				  SUN4I_HDMI_PAD_CTRL0_CKEN |
-+				  SUN4I_HDMI_PAD_CTRL0_PWENG |
-+				  SUN4I_HDMI_PAD_CTRL0_PWEND |
-+				  SUN4I_HDMI_PAD_CTRL0_PWENC |
-+				  SUN4I_HDMI_PAD_CTRL0_LDODEN |
-+				  SUN4I_HDMI_PAD_CTRL0_LDOCEN |
-+				  SUN4I_HDMI_PAD_CTRL0_BIASEN,
-+	.pad_ctrl1_init_val	= SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
-+				  SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
-+				  SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
-+				  SUN4I_HDMI_PAD_CTRL1_REG_DEN |
-+				  SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
-+				  SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
-+				  SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
-+				  SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
-+	.pll_ctrl_init_val	= SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
-+				  SUN4I_HDMI_PLL_CTRL_CS(7) |
-+				  SUN4I_HDMI_PLL_CTRL_CP_S(15) |
-+				  SUN4I_HDMI_PLL_CTRL_S(7) |
-+				  SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
-+				  SUN4I_HDMI_PLL_CTRL_SDIV2 |
-+				  SUN4I_HDMI_PLL_CTRL_LDO2_EN |
-+				  SUN4I_HDMI_PLL_CTRL_LDO1_EN |
-+				  SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
-+				  SUN4I_HDMI_PLL_CTRL_BWS |
-+				  SUN4I_HDMI_PLL_CTRL_PLL_EN,
-+
-+	.ddc_clk_reg		= REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
-+	.ddc_clk_pre_divider	= 2,
-+	.ddc_clk_m_offset	= 1,
-+
-+	.field_ddc_en		= REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
-+	.field_ddc_start	= REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
-+	.field_ddc_reset	= REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
-+	.field_ddc_addr_reg	= REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
-+	.field_ddc_slave_addr	= REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
-+	.field_ddc_int_status	= REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
-+	.field_ddc_fifo_clear	= REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
-+	.field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
-+	.field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
-+	.field_ddc_byte_count	= REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
-+	.field_ddc_cmd		= REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
-+	.field_ddc_sda_en	= REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
-+	.field_ddc_sck_en	= REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
-+
-+	.ddc_fifo_reg		= SUN4I_HDMI_DDC_FIFO_DATA_REG,
-+	.ddc_fifo_has_dir	= true,
-+};
-+
-+static const struct sun4i_hdmi_variant sun6i_variant = {
-+	.has_ddc_parent_clk	= true,
-+	.has_reset_control	= true,
-+	.pad_ctrl0_init_val	= 0xff |
-+				  SUN4I_HDMI_PAD_CTRL0_TXEN |
-+				  SUN4I_HDMI_PAD_CTRL0_CKEN |
-+				  SUN4I_HDMI_PAD_CTRL0_PWENG |
-+				  SUN4I_HDMI_PAD_CTRL0_PWEND |
-+				  SUN4I_HDMI_PAD_CTRL0_PWENC |
-+				  SUN4I_HDMI_PAD_CTRL0_LDODEN |
-+				  SUN4I_HDMI_PAD_CTRL0_LDOCEN,
-+	.pad_ctrl1_init_val	= SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
-+				  SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) |
-+				  SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
-+				  SUN4I_HDMI_PAD_CTRL1_REG_DEN |
-+				  SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
-+				  SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
-+				  SUN4I_HDMI_PAD_CTRL1_PWSDT |
-+				  SUN4I_HDMI_PAD_CTRL1_PWSCK |
-+				  SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
-+				  SUN4I_HDMI_PAD_CTRL1_AMP_OPT |
-+				  SUN4I_HDMI_PAD_CTRL1_UNKNOWN,
-+	.pll_ctrl_init_val	= SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
-+				  SUN4I_HDMI_PLL_CTRL_CS(3) |
-+				  SUN4I_HDMI_PLL_CTRL_CP_S(10) |
-+				  SUN4I_HDMI_PLL_CTRL_S(4) |
-+				  SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
-+				  SUN4I_HDMI_PLL_CTRL_SDIV2 |
-+				  SUN4I_HDMI_PLL_CTRL_LDO2_EN |
-+				  SUN4I_HDMI_PLL_CTRL_LDO1_EN |
-+				  SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
-+				  SUN4I_HDMI_PLL_CTRL_PLL_EN,
-+
-+	.ddc_clk_reg		= REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6),
-+	.ddc_clk_pre_divider	= 1,
-+	.ddc_clk_m_offset	= 2,
-+
-+	.tmds_clk_div_offset	= 1,
-+
-+	.field_ddc_en		= REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0),
-+	.field_ddc_start	= REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27),
-+	.field_ddc_reset	= REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31),
-+	.field_ddc_addr_reg	= REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31),
-+	.field_ddc_slave_addr	= REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7),
-+	.field_ddc_int_status	= REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8),
-+	.field_ddc_fifo_clear	= REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18),
-+	.field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
-+	.field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
-+	.field_ddc_byte_count	= REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25),
-+	.field_ddc_cmd		= REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2),
-+	.field_ddc_sda_en	= REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6),
-+	.field_ddc_sck_en	= REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4),
-+
-+	.ddc_fifo_reg		= SUN6I_HDMI_DDC_FIFO_DATA_REG,
-+	.ddc_fifo_thres_incl	= true,
-+};
-+
-+static const struct regmap_config sun4i_hdmi_regmap_config = {
-+	.reg_bits	= 32,
-+	.val_bits	= 32,
-+	.reg_stride	= 4,
-+	.max_register	= 0x580,
-+};
-+
- static int sun4i_hdmi_bind(struct device *dev, struct device *master,
- 			   void *data)
- {
-@@ -285,6 +422,10 @@ static int sun4i_hdmi_bind(struct device
- 	hdmi->dev = dev;
- 	hdmi->drv = drv;
- 
-+	hdmi->variant = of_device_get_match_data(dev);
-+	if (!hdmi->variant)
-+		return -EINVAL;
-+
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	hdmi->base = devm_ioremap_resource(dev, res);
- 	if (IS_ERR(hdmi->base)) {
-@@ -292,10 +433,25 @@ static int sun4i_hdmi_bind(struct device
- 		return PTR_ERR(hdmi->base);
- 	}
- 
-+	if (hdmi->variant->has_reset_control) {
-+		hdmi->reset = devm_reset_control_get(dev, NULL);
-+		if (IS_ERR(hdmi->reset)) {
-+			dev_err(dev, "Couldn't get the HDMI reset control\n");
-+			return PTR_ERR(hdmi->reset);
-+		}
-+
-+		ret = reset_control_deassert(hdmi->reset);
-+		if (ret) {
-+			dev_err(dev, "Couldn't deassert HDMI reset\n");
-+			return ret;
-+		}
-+	}
-+
- 	hdmi->bus_clk = devm_clk_get(dev, "ahb");
- 	if (IS_ERR(hdmi->bus_clk)) {
- 		dev_err(dev, "Couldn't get the HDMI bus clock\n");
--		return PTR_ERR(hdmi->bus_clk);
-+		ret = PTR_ERR(hdmi->bus_clk);
-+		goto err_assert_reset;
- 	}
- 	clk_prepare_enable(hdmi->bus_clk);
- 
-@@ -321,45 +477,37 @@ static int sun4i_hdmi_bind(struct device
- 		goto err_disable_mod_clk;
- 	}
- 
-+	hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base,
-+					     &sun4i_hdmi_regmap_config);
-+	if (IS_ERR(hdmi->regmap)) {
-+		dev_err(dev, "Couldn't create HDMI encoder regmap\n");
-+		return PTR_ERR(hdmi->regmap);
-+	}
-+
- 	ret = sun4i_tmds_create(hdmi);
- 	if (ret) {
- 		dev_err(dev, "Couldn't create the TMDS clock\n");
- 		goto err_disable_mod_clk;
- 	}
- 
-+	if (hdmi->variant->has_ddc_parent_clk) {
-+		hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc");
-+		if (IS_ERR(hdmi->ddc_parent_clk)) {
-+			dev_err(dev, "Couldn't get the HDMI DDC clock\n");
-+			return PTR_ERR(hdmi->ddc_parent_clk);
-+		}
-+	} else {
-+		hdmi->ddc_parent_clk = hdmi->tmds_clk;
-+	}
-+
- 	writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
- 
--	writel(SUN4I_HDMI_PAD_CTRL0_TXEN | SUN4I_HDMI_PAD_CTRL0_CKEN |
--	       SUN4I_HDMI_PAD_CTRL0_PWENG | SUN4I_HDMI_PAD_CTRL0_PWEND |
--	       SUN4I_HDMI_PAD_CTRL0_PWENC | SUN4I_HDMI_PAD_CTRL0_LDODEN |
--	       SUN4I_HDMI_PAD_CTRL0_LDOCEN | SUN4I_HDMI_PAD_CTRL0_BIASEN,
-+	writel(hdmi->variant->pad_ctrl0_init_val,
- 	       hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG);
- 
--	/*
--	 * We can't just initialize the register there, we need to
--	 * protect the clock bits that have already been read out and
--	 * cached by the clock framework.
--	 */
--	reg = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
--	reg &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
--	reg |= SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
--		SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
--		SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
--		SUN4I_HDMI_PAD_CTRL1_REG_DEN |
--		SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
--		SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
--		SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
--		SUN4I_HDMI_PAD_CTRL1_AMP_OPT;
--	writel(reg, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
--
- 	reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
- 	reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK;
--	reg |= SUN4I_HDMI_PLL_CTRL_VCO_S(8) | SUN4I_HDMI_PLL_CTRL_CS(7) |
--		SUN4I_HDMI_PLL_CTRL_CP_S(15) | SUN4I_HDMI_PLL_CTRL_S(7) |
--		SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | SUN4I_HDMI_PLL_CTRL_SDIV2 |
--		SUN4I_HDMI_PLL_CTRL_LDO2_EN | SUN4I_HDMI_PLL_CTRL_LDO1_EN |
--		SUN4I_HDMI_PLL_CTRL_HV_IS_33 | SUN4I_HDMI_PLL_CTRL_BWS |
--		SUN4I_HDMI_PLL_CTRL_PLL_EN;
-+	reg |= hdmi->variant->pll_ctrl_init_val;
- 	writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
- 
- 	ret = sun4i_hdmi_i2c_create(dev, hdmi);
-@@ -429,6 +577,8 @@ err_disable_mod_clk:
- 	clk_disable_unprepare(hdmi->mod_clk);
- err_disable_bus_clk:
- 	clk_disable_unprepare(hdmi->bus_clk);
-+err_assert_reset:
-+	reset_control_assert(hdmi->reset);
- 	return ret;
- }
- 
-@@ -463,7 +613,8 @@ static int sun4i_hdmi_remove(struct plat
- }
- 
- static const struct of_device_id sun4i_hdmi_of_table[] = {
--	{ .compatible = "allwinner,sun5i-a10s-hdmi" },
-+	{ .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, },
-+	{ .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, },
- 	{ }
- };
- MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table);
---- linux-4.14/drivers/gpu/drm/sun4i/sun4i_hdmi.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/sun4i/sun4i_hdmi.h	2017-12-14 06:39:58.523903643 +0100
-@@ -14,6 +14,7 @@
- 
- #include <drm/drm_connector.h>
- #include <drm/drm_encoder.h>
-+#include <linux/regmap.h>
- 
- #include <media/cec-pin.h>
- 
-@@ -58,16 +59,24 @@
- #define SUN4I_HDMI_PAD_CTRL0_TXEN		BIT(23)
- 
- #define SUN4I_HDMI_PAD_CTRL1_REG	0x204
-+#define SUN4I_HDMI_PAD_CTRL1_UNKNOWN		BIT(24)	/* set on A31 */
- #define SUN4I_HDMI_PAD_CTRL1_AMP_OPT		BIT(23)
- #define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT		BIT(22)
- #define SUN4I_HDMI_PAD_CTRL1_EMP_OPT		BIT(20)
- #define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT		BIT(19)
-+#define SUN4I_HDMI_PAD_CTRL1_PWSCK		BIT(18)
-+#define SUN4I_HDMI_PAD_CTRL1_PWSDT		BIT(17)
- #define SUN4I_HDMI_PAD_CTRL1_REG_DEN		BIT(15)
- #define SUN4I_HDMI_PAD_CTRL1_REG_DENCK		BIT(14)
- #define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n)		(((n) & 7) << 10)
- #define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK		BIT(6)
- #define SUN4I_HDMI_PAD_CTRL1_REG_AMP(n)		(((n) & 7) << 3)
- 
-+/* These bits seem to invert the TMDS data channels */
-+#define SUN4I_HDMI_PAD_CTRL1_INVERT_R		BIT(2)
-+#define SUN4I_HDMI_PAD_CTRL1_INVERT_G		BIT(1)
-+#define SUN4I_HDMI_PAD_CTRL1_INVERT_B		BIT(0)
-+
- #define SUN4I_HDMI_PLL_CTRL_REG		0x208
- #define SUN4I_HDMI_PLL_CTRL_PLL_EN		BIT(31)
- #define SUN4I_HDMI_PLL_CTRL_BWS			BIT(30)
-@@ -152,21 +161,106 @@
- 
- #define SUN4I_HDMI_DDC_FIFO_SIZE	16
- 
-+/* A31 specific */
-+#define SUN6I_HDMI_DDC_CTRL_REG		0x500
-+#define SUN6I_HDMI_DDC_CTRL_RESET		BIT(31)
-+#define SUN6I_HDMI_DDC_CTRL_START_CMD		BIT(27)
-+#define SUN6I_HDMI_DDC_CTRL_SDA_ENABLE		BIT(6)
-+#define SUN6I_HDMI_DDC_CTRL_SCL_ENABLE		BIT(4)
-+#define SUN6I_HDMI_DDC_CTRL_ENABLE		BIT(0)
-+
-+#define SUN6I_HDMI_DDC_CMD_REG		0x508
-+#define SUN6I_HDMI_DDC_CMD_BYTE_COUNT(count)	((count) << 16)
-+/* command types in lower 3 bits are the same as sun4i */
-+
-+#define SUN6I_HDMI_DDC_ADDR_REG		0x50c
-+#define SUN6I_HDMI_DDC_ADDR_SEGMENT(seg)	(((seg) & 0xff) << 24)
-+#define SUN6I_HDMI_DDC_ADDR_EDDC(addr)		(((addr) & 0xff) << 16)
-+#define SUN6I_HDMI_DDC_ADDR_OFFSET(off)		(((off) & 0xff) << 8)
-+#define SUN6I_HDMI_DDC_ADDR_SLAVE(addr)		(((addr) & 0xff) << 1)
-+
-+#define SUN6I_HDMI_DDC_INT_STATUS_REG	0x514
-+#define SUN6I_HDMI_DDC_INT_STATUS_TIMEOUT	BIT(8)
-+/* lower 8 bits are the same as sun4i */
-+
-+#define SUN6I_HDMI_DDC_FIFO_CTRL_REG	0x518
-+#define SUN6I_HDMI_DDC_FIFO_CTRL_CLEAR		BIT(15)
-+/* lower 9 bits are the same as sun4i */
-+
-+#define SUN6I_HDMI_DDC_CLK_REG		0x520
-+/* DDC CLK bit fields are the same, but the formula is not */
-+
-+#define SUN6I_HDMI_DDC_FIFO_DATA_REG	0x580
-+
- enum sun4i_hdmi_pkt_type {
- 	SUN4I_HDMI_PKT_AVI = 2,
- 	SUN4I_HDMI_PKT_END = 15,
- };
- 
-+struct sun4i_hdmi_variant {
-+	bool has_ddc_parent_clk;
-+	bool has_reset_control;
-+
-+	u32 pad_ctrl0_init_val;
-+	u32 pad_ctrl1_init_val;
-+	u32 pll_ctrl_init_val;
-+
-+	struct reg_field ddc_clk_reg;
-+	u8 ddc_clk_pre_divider;
-+	u8 ddc_clk_m_offset;
-+
-+	u8 tmds_clk_div_offset;
-+
-+	/* Register fields for I2C adapter */
-+	struct reg_field	field_ddc_en;
-+	struct reg_field	field_ddc_start;
-+	struct reg_field	field_ddc_reset;
-+	struct reg_field	field_ddc_addr_reg;
-+	struct reg_field	field_ddc_slave_addr;
-+	struct reg_field	field_ddc_int_mask;
-+	struct reg_field	field_ddc_int_status;
-+	struct reg_field	field_ddc_fifo_clear;
-+	struct reg_field	field_ddc_fifo_rx_thres;
-+	struct reg_field	field_ddc_fifo_tx_thres;
-+	struct reg_field	field_ddc_byte_count;
-+	struct reg_field	field_ddc_cmd;
-+	struct reg_field	field_ddc_sda_en;
-+	struct reg_field	field_ddc_sck_en;
-+
-+	/* DDC FIFO register offset */
-+	u32			ddc_fifo_reg;
-+
-+	/*
-+	 * DDC FIFO threshold boundary conditions
-+	 *
-+	 * This is used to cope with the threshold boundary condition
-+	 * being slightly different on sun5i and sun6i.
-+	 *
-+	 * On sun5i the threshold is exclusive, i.e. does not include,
-+	 * the value of the threshold. ( > for RX; < for TX )
-+	 * On sun6i the threshold is inclusive, i.e. includes, the
-+	 * value of the threshold. ( >= for RX; <= for TX )
-+	 */
-+	bool			ddc_fifo_thres_incl;
-+
-+	bool			ddc_fifo_has_dir;
-+};
-+
- struct sun4i_hdmi {
- 	struct drm_connector	connector;
- 	struct drm_encoder	encoder;
- 	struct device		*dev;
- 
- 	void __iomem		*base;
-+	struct regmap		*regmap;
-+
-+	/* Reset control */
-+	struct reset_control	*reset;
- 
- 	/* Parent clocks */
- 	struct clk		*bus_clk;
- 	struct clk		*mod_clk;
-+	struct clk		*ddc_parent_clk;
- 	struct clk		*pll0_clk;
- 	struct clk		*pll1_clk;
- 
-@@ -176,10 +270,28 @@ struct sun4i_hdmi {
- 
- 	struct i2c_adapter	*i2c;
- 
-+	/* Regmap fields for I2C adapter */
-+	struct regmap_field	*field_ddc_en;
-+	struct regmap_field	*field_ddc_start;
-+	struct regmap_field	*field_ddc_reset;
-+	struct regmap_field	*field_ddc_addr_reg;
-+	struct regmap_field	*field_ddc_slave_addr;
-+	struct regmap_field	*field_ddc_int_mask;
-+	struct regmap_field	*field_ddc_int_status;
-+	struct regmap_field	*field_ddc_fifo_clear;
-+	struct regmap_field	*field_ddc_fifo_rx_thres;
-+	struct regmap_field	*field_ddc_fifo_tx_thres;
-+	struct regmap_field	*field_ddc_byte_count;
-+	struct regmap_field	*field_ddc_cmd;
-+	struct regmap_field	*field_ddc_sda_en;
-+	struct regmap_field	*field_ddc_sck_en;
-+
- 	struct sun4i_drv	*drv;
- 
- 	bool			hdmi_monitor;
- 	struct cec_adapter	*cec_adap;
-+
-+	const struct sun4i_hdmi_variant	*variant;
- };
- 
- int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
---- linux-4.14/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c	2017-12-14 06:39:58.523903643 +0100
-@@ -25,8 +25,6 @@
- 
- /* FIFO request bit is set when FIFO level is above RX_THRESHOLD during read */
- #define RX_THRESHOLD SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX
--/* FIFO request bit is set when FIFO level is below TX_THRESHOLD during write */
--#define TX_THRESHOLD 1
- 
- static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read)
- {
-@@ -39,27 +37,36 @@ static int fifo_transfer(struct sun4i_hd
- 			 SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST |
- 			 SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE;
- 	u32 reg;
-+	/*
-+	 * If threshold is inclusive, then the FIFO may only have
-+	 * RX_THRESHOLD number of bytes, instead of RX_THRESHOLD + 1.
-+	 */
-+	int read_len = RX_THRESHOLD +
-+		(hdmi->variant->ddc_fifo_thres_incl ? 0 : 1);
- 
--	/* Limit transfer length by FIFO threshold */
--	len = min_t(int, len, read ? (RX_THRESHOLD + 1) :
--			      (SUN4I_HDMI_DDC_FIFO_SIZE - TX_THRESHOLD + 1));
-+	/*
-+	 * Limit transfer length by FIFO threshold or FIFO size.
-+	 * For TX the threshold is for an empty FIFO.
-+	 */
-+	len = min_t(int, len, read ? read_len : SUN4I_HDMI_DDC_FIFO_SIZE);
- 
- 	/* Wait until error, FIFO request bit set or transfer complete */
--	if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG, reg,
--			       reg & mask, len * byte_time_ns, 100000))
-+	if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg,
-+					   reg & mask, len * byte_time_ns,
-+					   100000))
- 		return -ETIMEDOUT;
- 
- 	if (reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK)
- 		return -EIO;
- 
- 	if (read)
--		readsb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG, buf, len);
-+		readsb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len);
- 	else
--		writesb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG, buf, len);
-+		writesb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len);
- 
--	/* Clear FIFO request bit */
--	writel(SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST,
--	       hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG);
-+	/* Clear FIFO request bit by forcing a write to that bit */
-+	regmap_field_force_write(hdmi->field_ddc_int_status,
-+				 SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST);
- 
- 	return len;
- }
-@@ -70,50 +77,52 @@ static int xfer_msg(struct sun4i_hdmi *h
- 	u32 reg;
- 
- 	/* Set FIFO direction */
--	reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
--	reg &= ~SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK;
--	reg |= (msg->flags & I2C_M_RD) ?
--	       SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ :
--	       SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE;
--	writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
-+	if (hdmi->variant->ddc_fifo_has_dir) {
-+		reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
-+		reg &= ~SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK;
-+		reg |= (msg->flags & I2C_M_RD) ?
-+		       SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ :
-+		       SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE;
-+		writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
-+	}
-+
-+	/* Clear address register (not cleared by soft reset) */
-+	regmap_field_write(hdmi->field_ddc_addr_reg, 0);
- 
- 	/* Set I2C address */
--	writel(SUN4I_HDMI_DDC_ADDR_SLAVE(msg->addr),
--	       hdmi->base + SUN4I_HDMI_DDC_ADDR_REG);
-+	regmap_field_write(hdmi->field_ddc_slave_addr, msg->addr);
- 
--	/* Set FIFO RX/TX thresholds and clear FIFO */
--	reg = readl(hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG);
--	reg |= SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR;
--	reg &= ~SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK;
--	reg |= SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(RX_THRESHOLD);
--	reg &= ~SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK;
--	reg |= SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(TX_THRESHOLD);
--	writel(reg, hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG);
--	if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG,
--			       reg,
--			       !(reg & SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR),
--			       100, 2000))
-+	/*
-+	 * Set FIFO RX/TX thresholds and clear FIFO
-+	 *
-+	 * If threshold is inclusive, we can set the TX threshold to
-+	 * 0 instead of 1.
-+	 */
-+	regmap_field_write(hdmi->field_ddc_fifo_tx_thres,
-+			   hdmi->variant->ddc_fifo_thres_incl ? 0 : 1);
-+	regmap_field_write(hdmi->field_ddc_fifo_rx_thres, RX_THRESHOLD);
-+	regmap_field_write(hdmi->field_ddc_fifo_clear, 1);
-+	if (regmap_field_read_poll_timeout(hdmi->field_ddc_fifo_clear,
-+					   reg, !reg, 100, 2000))
- 		return -EIO;
- 
- 	/* Set transfer length */
--	writel(msg->len, hdmi->base + SUN4I_HDMI_DDC_BYTE_COUNT_REG);
-+	regmap_field_write(hdmi->field_ddc_byte_count, msg->len);
- 
- 	/* Set command */
--	writel(msg->flags & I2C_M_RD ?
--	       SUN4I_HDMI_DDC_CMD_IMPLICIT_READ :
--	       SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE,
--	       hdmi->base + SUN4I_HDMI_DDC_CMD_REG);
--
--	/* Clear interrupt status bits */
--	writel(SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK |
--	       SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST |
--	       SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE,
--	       hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG);
-+	regmap_field_write(hdmi->field_ddc_cmd,
-+			   msg->flags & I2C_M_RD ?
-+			   SUN4I_HDMI_DDC_CMD_IMPLICIT_READ :
-+			   SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE);
-+
-+	/* Clear interrupt status bits by forcing a write */
-+	regmap_field_force_write(hdmi->field_ddc_int_status,
-+				 SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK |
-+				 SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST |
-+				 SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE);
- 
- 	/* Start command */
--	reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
--	writel(reg | SUN4I_HDMI_DDC_CTRL_START_CMD,
--	       hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
-+	regmap_field_write(hdmi->field_ddc_start, 1);
- 
- 	/* Transfer bytes */
- 	for (i = 0; i < msg->len; i += len) {
-@@ -124,14 +133,12 @@ static int xfer_msg(struct sun4i_hdmi *h
- 	}
- 
- 	/* Wait for command to finish */
--	if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG,
--			       reg,
--			       !(reg & SUN4I_HDMI_DDC_CTRL_START_CMD),
--			       100, 100000))
-+	if (regmap_field_read_poll_timeout(hdmi->field_ddc_start,
-+					   reg, !reg, 100, 100000))
- 		return -EIO;
- 
- 	/* Check for errors */
--	reg = readl(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG);
-+	regmap_field_read(hdmi->field_ddc_int_status, &reg);
- 	if ((reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK) ||
- 	    !(reg & SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE)) {
- 		return -EIO;
-@@ -154,20 +161,21 @@ static int sun4i_hdmi_i2c_xfer(struct i2
- 			return -EINVAL;
- 	}
- 
-+	/* DDC clock needs to be enabled for the module to work */
-+	clk_prepare_enable(hdmi->ddc_clk);
-+	clk_set_rate(hdmi->ddc_clk, 100000);
-+
- 	/* Reset I2C controller */
--	writel(SUN4I_HDMI_DDC_CTRL_ENABLE | SUN4I_HDMI_DDC_CTRL_RESET,
--	       hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
--	if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG, reg,
--			       !(reg & SUN4I_HDMI_DDC_CTRL_RESET),
--			       100, 2000))
-+	regmap_field_write(hdmi->field_ddc_en, 1);
-+	regmap_field_write(hdmi->field_ddc_reset, 1);
-+	if (regmap_field_read_poll_timeout(hdmi->field_ddc_reset,
-+					   reg, !reg, 100, 2000)) {
-+		clk_disable_unprepare(hdmi->ddc_clk);
- 		return -EIO;
-+	}
- 
--	writel(SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE |
--	       SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE,
--	       hdmi->base + SUN4I_HDMI_DDC_LINE_CTRL_REG);
--
--	clk_prepare_enable(hdmi->ddc_clk);
--	clk_set_rate(hdmi->ddc_clk, 100000);
-+	regmap_field_write(hdmi->field_ddc_sck_en, 1);
-+	regmap_field_write(hdmi->field_ddc_sda_en, 1);
- 
- 	for (i = 0; i < num; i++) {
- 		err = xfer_msg(hdmi, &msgs[i]);
-@@ -191,12 +199,105 @@ static const struct i2c_algorithm sun4i_
- 	.functionality	= sun4i_hdmi_i2c_func,
- };
- 
-+static int sun4i_hdmi_init_regmap_fields(struct sun4i_hdmi *hdmi)
-+{
-+	hdmi->field_ddc_en =
-+		devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					hdmi->variant->field_ddc_en);
-+	if (IS_ERR(hdmi->field_ddc_en))
-+		return PTR_ERR(hdmi->field_ddc_en);
-+
-+	hdmi->field_ddc_start =
-+		devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					hdmi->variant->field_ddc_start);
-+	if (IS_ERR(hdmi->field_ddc_start))
-+		return PTR_ERR(hdmi->field_ddc_start);
-+
-+	hdmi->field_ddc_reset =
-+		devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					hdmi->variant->field_ddc_reset);
-+	if (IS_ERR(hdmi->field_ddc_reset))
-+		return PTR_ERR(hdmi->field_ddc_reset);
-+
-+	hdmi->field_ddc_addr_reg =
-+		devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					hdmi->variant->field_ddc_addr_reg);
-+	if (IS_ERR(hdmi->field_ddc_addr_reg))
-+		return PTR_ERR(hdmi->field_ddc_addr_reg);
-+
-+	hdmi->field_ddc_slave_addr =
-+		devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					hdmi->variant->field_ddc_slave_addr);
-+	if (IS_ERR(hdmi->field_ddc_slave_addr))
-+		return PTR_ERR(hdmi->field_ddc_slave_addr);
-+
-+	hdmi->field_ddc_int_mask =
-+		devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					hdmi->variant->field_ddc_int_mask);
-+	if (IS_ERR(hdmi->field_ddc_int_mask))
-+		return PTR_ERR(hdmi->field_ddc_int_mask);
-+
-+	hdmi->field_ddc_int_status =
-+		devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					hdmi->variant->field_ddc_int_status);
-+	if (IS_ERR(hdmi->field_ddc_int_status))
-+		return PTR_ERR(hdmi->field_ddc_int_status);
-+
-+	hdmi->field_ddc_fifo_clear =
-+		devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					hdmi->variant->field_ddc_fifo_clear);
-+	if (IS_ERR(hdmi->field_ddc_fifo_clear))
-+		return PTR_ERR(hdmi->field_ddc_fifo_clear);
-+
-+	hdmi->field_ddc_fifo_rx_thres =
-+		devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					hdmi->variant->field_ddc_fifo_rx_thres);
-+	if (IS_ERR(hdmi->field_ddc_fifo_rx_thres))
-+		return PTR_ERR(hdmi->field_ddc_fifo_rx_thres);
-+
-+	hdmi->field_ddc_fifo_tx_thres =
-+		devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					hdmi->variant->field_ddc_fifo_tx_thres);
-+	if (IS_ERR(hdmi->field_ddc_fifo_tx_thres))
-+		return PTR_ERR(hdmi->field_ddc_fifo_tx_thres);
-+
-+	hdmi->field_ddc_byte_count =
-+		devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					hdmi->variant->field_ddc_byte_count);
-+	if (IS_ERR(hdmi->field_ddc_byte_count))
-+		return PTR_ERR(hdmi->field_ddc_byte_count);
-+
-+	hdmi->field_ddc_cmd =
-+		devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					hdmi->variant->field_ddc_cmd);
-+	if (IS_ERR(hdmi->field_ddc_cmd))
-+		return PTR_ERR(hdmi->field_ddc_cmd);
-+
-+	hdmi->field_ddc_sda_en =
-+		devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					hdmi->variant->field_ddc_sda_en);
-+	if (IS_ERR(hdmi->field_ddc_sda_en))
-+		return PTR_ERR(hdmi->field_ddc_sda_en);
-+
-+	hdmi->field_ddc_sck_en =
-+		devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
-+					hdmi->variant->field_ddc_sck_en);
-+	if (IS_ERR(hdmi->field_ddc_sck_en))
-+		return PTR_ERR(hdmi->field_ddc_sck_en);
-+
-+	return 0;
-+}
-+
- int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi)
- {
- 	struct i2c_adapter *adap;
- 	int ret = 0;
- 
--	ret = sun4i_ddc_create(hdmi, hdmi->tmds_clk);
-+	ret = sun4i_ddc_create(hdmi, hdmi->ddc_parent_clk);
-+	if (ret)
-+		return ret;
-+
-+	ret = sun4i_hdmi_init_regmap_fields(hdmi);
- 	if (ret)
- 		return ret;
- 
---- linux-4.14/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c	2017-12-14 06:39:58.523903643 +0100
-@@ -18,6 +18,8 @@
- struct sun4i_tmds {
- 	struct clk_hw		hw;
- 	struct sun4i_hdmi	*hdmi;
-+
-+	u8			div_offset;
- };
- 
- static inline struct sun4i_tmds *hw_to_tmds(struct clk_hw *hw)
-@@ -28,6 +30,7 @@ static inline struct sun4i_tmds *hw_to_t
- 
- static unsigned long sun4i_tmds_calc_divider(unsigned long rate,
- 					     unsigned long parent_rate,
-+					     u8 div_offset,
- 					     u8 *div,
- 					     bool *half)
- {
-@@ -35,7 +38,7 @@ static unsigned long sun4i_tmds_calc_div
- 	u8 best_m = 0, m;
- 	bool is_double;
- 
--	for (m = 1; m < 16; m++) {
-+	for (m = div_offset ?: 1; m < (16 + div_offset); m++) {
- 		u8 d;
- 
- 		for (d = 1; d < 3; d++) {
-@@ -67,11 +70,12 @@ static unsigned long sun4i_tmds_calc_div
- static int sun4i_tmds_determine_rate(struct clk_hw *hw,
- 				     struct clk_rate_request *req)
- {
--	struct clk_hw *parent;
-+	struct sun4i_tmds *tmds = hw_to_tmds(hw);
-+	struct clk_hw *parent = NULL;
- 	unsigned long best_parent = 0;
- 	unsigned long rate = req->rate;
- 	int best_div = 1, best_half = 1;
--	int i, j;
-+	int i, j, p;
- 
- 	/*
- 	 * We only consider PLL3, since the TCON is very likely to be
-@@ -79,32 +83,38 @@ static int sun4i_tmds_determine_rate(str
- 	 * clock, so we should not need to do anything.
- 	 */
- 
--	parent = clk_hw_get_parent_by_index(hw, 0);
--	if (!parent)
--		return -EINVAL;
--
--	for (i = 1; i < 3; i++) {
--		for (j = 1; j < 16; j++) {
--			unsigned long ideal = rate * i * j;
--			unsigned long rounded;
--
--			rounded = clk_hw_round_rate(parent, ideal);
--
--			if (rounded == ideal) {
--				best_parent = rounded;
--				best_half = i;
--				best_div = j;
--				goto out;
--			}
--
--			if (abs(rate - rounded / i) <
--			    abs(rate - best_parent / best_div)) {
--				best_parent = rounded;
--				best_div = i;
-+	for (p = 0; p < clk_hw_get_num_parents(hw); p++) {
-+		parent = clk_hw_get_parent_by_index(hw, p);
-+		if (!parent)
-+			continue;
-+
-+		for (i = 1; i < 3; i++) {
-+			for (j = tmds->div_offset ?: 1;
-+			     j < (16 + tmds->div_offset); j++) {
-+				unsigned long ideal = rate * i * j;
-+				unsigned long rounded;
-+
-+				rounded = clk_hw_round_rate(parent, ideal);
-+
-+				if (rounded == ideal) {
-+					best_parent = rounded;
-+					best_half = i;
-+					best_div = j;
-+					goto out;
-+				}
-+
-+				if (abs(rate - rounded / i) <
-+				    abs(rate - best_parent / best_div)) {
-+					best_parent = rounded;
-+					best_div = i;
-+				}
- 			}
- 		}
- 	}
- 
-+	if (!parent)
-+		return -EINVAL;
-+
- out:
- 	req->rate = best_parent / best_half / best_div;
- 	req->best_parent_rate = best_parent;
-@@ -124,7 +134,7 @@ static unsigned long sun4i_tmds_recalc_r
- 		parent_rate /= 2;
- 
- 	reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
--	reg = (reg >> 4) & 0xf;
-+	reg = ((reg >> 4) & 0xf) + tmds->div_offset;
- 	if (!reg)
- 		reg = 1;
- 
-@@ -139,7 +149,8 @@ static int sun4i_tmds_set_rate(struct cl
- 	u32 reg;
- 	u8 div;
- 
--	sun4i_tmds_calc_divider(rate, parent_rate, &div, &half);
-+	sun4i_tmds_calc_divider(rate, parent_rate, tmds->div_offset,
-+				&div, &half);
- 
- 	reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
- 	reg &= ~SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
-@@ -149,7 +160,7 @@ static int sun4i_tmds_set_rate(struct cl
- 
- 	reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
- 	reg &= ~SUN4I_HDMI_PLL_CTRL_DIV_MASK;
--	writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div),
-+	writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div - tmds->div_offset),
- 	       tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
- 
- 	return 0;
-@@ -216,6 +227,7 @@ int sun4i_tmds_create(struct sun4i_hdmi
- 
- 	tmds->hdmi = hdmi;
- 	tmds->hw.init = &init;
-+	tmds->div_offset = hdmi->variant->tmds_clk_div_offset;
- 
- 	hdmi->tmds_clk = devm_clk_register(hdmi->dev, &tmds->hw);
- 	if (IS_ERR(hdmi->tmds_clk))
---- linux-4.14/drivers/gpu/drm/sun4i/sun4i_tcon.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/sun4i/sun4i_tcon.c	2017-12-14 06:39:58.523903643 +0100
-@@ -14,9 +14,12 @@
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_crtc.h>
- #include <drm/drm_crtc_helper.h>
-+#include <drm/drm_encoder.h>
- #include <drm/drm_modes.h>
- #include <drm/drm_of.h>
- 
-+#include <uapi/drm/drm_mode.h>
-+
- #include <linux/component.h>
- #include <linux/ioport.h>
- #include <linux/of_address.h>
-@@ -109,26 +112,37 @@ void sun4i_tcon_enable_vblank(struct sun
- }
- EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
- 
--void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
--			struct drm_encoder *encoder)
-+/*
-+ * This function is a helper for TCON output muxing. The TCON output
-+ * muxing control register in earlier SoCs (without the TCON TOP block)
-+ * are located in TCON0. This helper returns a pointer to TCON0's
-+ * sun4i_tcon structure, or NULL if not found.
-+ */
-+static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm)
- {
--	u32 val;
-+	struct sun4i_drv *drv = drm->dev_private;
-+	struct sun4i_tcon *tcon;
- 
--	if (!tcon->quirks->has_unknown_mux)
--		return;
-+	list_for_each_entry(tcon, &drv->tcon_list, list)
-+		if (tcon->id == 0)
-+			return tcon;
- 
--	if (channel != 1)
--		return;
-+	dev_warn(drm->dev,
-+		 "TCON0 not found, display output muxing may not work\n");
- 
--	if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
--		val = 1;
--	else
--		val = 0;
-+	return NULL;
-+}
- 
--	/*
--	 * FIXME: Undocumented bits
--	 */
--	regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
-+void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
-+			struct drm_encoder *encoder)
-+{
-+	int ret = -ENOTSUPP;
-+
-+	if (tcon->quirks->set_mux)
-+		ret = tcon->quirks->set_mux(tcon, encoder);
-+
-+	DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n",
-+			 encoder->name, encoder->crtc->name, ret);
- }
- EXPORT_SYMBOL(sun4i_tcon_set_mux);
- 
-@@ -463,42 +477,170 @@ static int sun4i_tcon_init_regmap(struct
-  * function in fact searches the corresponding engine, and the ID is
-  * requested via the get_id function of the engine.
-  */
--static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
--						   struct device_node *node)
-+static struct sunxi_engine *
-+sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv,
-+				struct device_node *node)
- {
- 	struct device_node *port, *ep, *remote;
--	struct sunxi_engine *engine;
-+	struct sunxi_engine *engine = ERR_PTR(-EINVAL);
- 
- 	port = of_graph_get_port_by_id(node, 0);
- 	if (!port)
- 		return ERR_PTR(-EINVAL);
- 
-+	/*
-+	 * This only works if there is only one path from the TCON
-+	 * to any display engine. Otherwise the probe order of the
-+	 * TCONs and display engines is not guaranteed. They may
-+	 * either bind to the wrong one, or worse, bind to the same
-+	 * one if additional checks are not done.
-+	 *
-+	 * Bail out if there are multiple input connections.
-+	 */
-+	if (of_get_available_child_count(port) != 1)
-+		goto out_put_port;
-+
-+	/* Get the first connection without specifying an ID */
-+	ep = of_get_next_available_child(port, NULL);
-+	if (!ep)
-+		goto out_put_port;
-+
-+	remote = of_graph_get_remote_port_parent(ep);
-+	if (!remote)
-+		goto out_put_ep;
-+
-+	/* does this node match any registered engines? */
-+	list_for_each_entry(engine, &drv->engine_list, list)
-+		if (remote == engine->node)
-+			goto out_put_remote;
-+
-+	/* keep looking through upstream ports */
-+	engine = sun4i_tcon_find_engine_traverse(drv, remote);
-+
-+out_put_remote:
-+	of_node_put(remote);
-+out_put_ep:
-+	of_node_put(ep);
-+out_put_port:
-+	of_node_put(port);
-+
-+	return engine;
-+}
-+
-+/*
-+ * The device tree binding says that the remote endpoint ID of any
-+ * connection between components, up to and including the TCON, of
-+ * the display pipeline should be equal to the actual ID of the local
-+ * component. Thus we can look at any one of the input connections of
-+ * the TCONs, and use that connection's remote endpoint ID as our own.
-+ *
-+ * Since the user of this function already finds the input port,
-+ * the port is passed in directly without further checks.
-+ */
-+static int sun4i_tcon_of_get_id_from_port(struct device_node *port)
-+{
-+	struct device_node *ep;
-+	int ret = -EINVAL;
-+
-+	/* try finding an upstream endpoint */
- 	for_each_available_child_of_node(port, ep) {
--		remote = of_graph_get_remote_port_parent(ep);
-+		struct device_node *remote;
-+		u32 reg;
-+
-+		remote = of_graph_get_remote_endpoint(ep);
- 		if (!remote)
- 			continue;
- 
--		/* does this node match any registered engines? */
--		list_for_each_entry(engine, &drv->engine_list, list) {
--			if (remote == engine->node) {
--				of_node_put(remote);
--				of_node_put(port);
--				return engine;
--			}
--		}
-+		ret = of_property_read_u32(remote, "reg", &reg);
-+		if (ret)
-+			continue;
- 
--		/* keep looking through upstream ports */
--		engine = sun4i_tcon_find_engine(drv, remote);
--		if (!IS_ERR(engine)) {
--			of_node_put(remote);
--			of_node_put(port);
--			return engine;
--		}
-+		ret = reg;
- 	}
- 
-+	return ret;
-+}
-+
-+/*
-+ * Once we know the TCON's id, we can look through the list of
-+ * engines to find a matching one. We assume all engines have
-+ * been probed and added to the list.
-+ */
-+static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv,
-+							int id)
-+{
-+	struct sunxi_engine *engine;
-+
-+	list_for_each_entry(engine, &drv->engine_list, list)
-+		if (engine->id == id)
-+			return engine;
-+
- 	return ERR_PTR(-EINVAL);
- }
- 
-+/*
-+ * On SoCs with the old display pipeline design (Display Engine 1.0),
-+ * we assumed the TCON was always tied to just one backend. However
-+ * this proved not to be the case. On the A31, the TCON can select
-+ * either backend as its source. On the A20 (and likely on the A10),
-+ * the backend can choose which TCON to output to.
-+ *
-+ * The device tree binding says that the remote endpoint ID of any
-+ * connection between components, up to and including the TCON, of
-+ * the display pipeline should be equal to the actual ID of the local
-+ * component. Thus we should be able to look at any one of the input
-+ * connections of the TCONs, and use that connection's remote endpoint
-+ * ID as our own.
-+ *
-+ * However  the connections between the backend and TCON were assumed
-+ * to be always singular, and their endpoit IDs were all incorrectly
-+ * set to 0. This means for these old device trees, we cannot just look
-+ * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
-+ * incorrectly identified as TCON0.
-+ *
-+ * This function first checks if the TCON node has 2 input endpoints.
-+ * If so, then the device tree is a corrected version, and it will use
-+ * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above
-+ * to fetch the ID and engine directly. If not, then it is likely an
-+ * old device trees, where the endpoint IDs were incorrect, but did not
-+ * have endpoint connections between the backend and TCON across
-+ * different display pipelines. It will fall back to the old method of
-+ * traversing the  of_graph to try and find a matching engine by device
-+ * node.
-+ *
-+ * In the case of single display pipeline device trees, either method
-+ * works.
-+ */
-+static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
-+						   struct device_node *node)
-+{
-+	struct device_node *port;
-+	struct sunxi_engine *engine;
-+
-+	port = of_graph_get_port_by_id(node, 0);
-+	if (!port)
-+		return ERR_PTR(-EINVAL);
-+
-+	/*
-+	 * Is this a corrected device tree with cross pipeline
-+	 * connections between the backend and TCON?
-+	 */
-+	if (of_get_child_count(port) > 1) {
-+		/* Get our ID directly from an upstream endpoint */
-+		int id = sun4i_tcon_of_get_id_from_port(port);
-+
-+		/* Get our engine by matching our ID */
-+		engine = sun4i_tcon_get_engine_by_id(drv, id);
-+
-+		of_node_put(port);
-+		return engine;
-+	}
-+
-+	/* Fallback to old method by traversing input endpoints */
-+	of_node_put(port);
-+	return sun4i_tcon_find_engine_traverse(drv, node);
-+}
-+
- static int sun4i_tcon_bind(struct device *dev, struct device *master,
- 			   void *data)
- {
-@@ -530,10 +672,7 @@ static int sun4i_tcon_bind(struct device
- 	}
- 
- 	/* Make sure our TCON is reset */
--	if (!reset_control_status(tcon->lcd_rst))
--		reset_control_assert(tcon->lcd_rst);
--
--	ret = reset_control_deassert(tcon->lcd_rst);
-+	ret = reset_control_reset(tcon->lcd_rst);
- 	if (ret) {
- 		dev_err(dev, "Couldn't deassert our reset line\n");
- 		return ret;
-@@ -574,6 +713,25 @@ static int sun4i_tcon_bind(struct device
- 	if (ret < 0)
- 		goto err_free_clocks;
- 
-+	if (tcon->quirks->needs_de_be_mux) {
-+		/*
-+		 * We assume there is no dynamic muxing of backends
-+		 * and TCONs, so we select the backend with same ID.
-+		 *
-+		 * While dynamic selection might be interesting, since
-+		 * the CRTC is tied to the TCON, while the layers are
-+		 * tied to the backends, this means, we will need to
-+		 * switch between groups of layers. There might not be
-+		 * a way to represent this constraint in DRM.
-+		 */
-+		regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
-+				   SUN4I_TCON0_CTL_SRC_SEL_MASK,
-+				   tcon->id);
-+		regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
-+				   SUN4I_TCON1_CTL_SRC_SEL_MASK,
-+				   tcon->id);
-+	}
-+
- 	list_add_tail(&tcon->list, &drv->tcon_list);
- 
- 	return 0;
-@@ -623,17 +781,62 @@ static int sun4i_tcon_remove(struct plat
- 	return 0;
- }
- 
-+/* platform specific TCON muxing callbacks */
-+static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,
-+				  struct drm_encoder *encoder)
-+{
-+	u32 val;
-+
-+	if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
-+		val = 1;
-+	else
-+		val = 0;
-+
-+	/*
-+	 * FIXME: Undocumented bits
-+	 */
-+	return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
-+}
-+
-+static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
-+			      struct drm_encoder *encoder)
-+{
-+	struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
-+	u32 shift;
-+
-+	if (!tcon0)
-+		return -EINVAL;
-+
-+	switch (encoder->encoder_type) {
-+	case DRM_MODE_ENCODER_TMDS:
-+		/* HDMI */
-+		shift = 8;
-+		break;
-+	default:
-+		/* TODO A31 has MIPI DSI but A31s does not */
-+		return -EINVAL;
-+	}
-+
-+	regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
-+			   0x3 << shift, tcon->id << shift);
-+
-+	return 0;
-+}
-+
- static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
--	.has_unknown_mux = true,
--	.has_channel_1	= true,
-+	.has_channel_1		= true,
-+	.set_mux		= sun5i_a13_tcon_set_mux,
- };
- 
- static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
--	.has_channel_1	= true,
-+	.has_channel_1		= true,
-+	.needs_de_be_mux	= true,
-+	.set_mux		= sun6i_tcon_set_mux,
- };
- 
- static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
--	.has_channel_1	= true,
-+	.has_channel_1		= true,
-+	.needs_de_be_mux	= true,
- };
- 
- static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
---- linux-4.14/drivers/gpu/drm/sun4i/sun4i_tcon.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/sun4i/sun4i_tcon.h	2017-12-14 06:39:58.523903643 +0100
-@@ -37,6 +37,7 @@
- #define SUN4I_TCON0_CTL_TCON_ENABLE			BIT(31)
- #define SUN4I_TCON0_CTL_CLK_DELAY_MASK			GENMASK(8, 4)
- #define SUN4I_TCON0_CTL_CLK_DELAY(delay)		((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK)
-+#define SUN4I_TCON0_CTL_SRC_SEL_MASK			GENMASK(2, 0)
- 
- #define SUN4I_TCON0_DCLK_REG			0x44
- #define SUN4I_TCON0_DCLK_GATE_BIT			(31)
-@@ -85,6 +86,7 @@
- #define SUN4I_TCON1_CTL_INTERLACE_ENABLE		BIT(20)
- #define SUN4I_TCON1_CTL_CLK_DELAY_MASK			GENMASK(8, 4)
- #define SUN4I_TCON1_CTL_CLK_DELAY(delay)		((delay << 4) & SUN4I_TCON1_CTL_CLK_DELAY_MASK)
-+#define SUN4I_TCON1_CTL_SRC_SEL_MASK			GENMASK(1, 0)
- 
- #define SUN4I_TCON1_BASIC0_REG			0x94
- #define SUN4I_TCON1_BASIC0_X(width)			((((width) - 1) & 0xfff) << 16)
-@@ -143,9 +145,14 @@
- 
- #define SUN4I_TCON_MAX_CHANNELS		2
- 
-+struct sun4i_tcon;
-+
- struct sun4i_tcon_quirks {
--	bool	has_unknown_mux; /* sun5i has undocumented mux */
- 	bool	has_channel_1;	/* a33 does not have channel 1 */
-+	bool	needs_de_be_mux; /* sun6i needs mux to select backend */
-+
-+	/* callback to handle tcon muxing options */
-+	int	(*set_mux)(struct sun4i_tcon *, struct drm_encoder *);
- };
- 
- struct sun4i_tcon {
---- linux-4.14/drivers/gpu/drm/tilcdc/tilcdc_crtc.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/tilcdc/tilcdc_crtc.c	2017-12-14 06:39:58.523903643 +0100
-@@ -77,7 +77,7 @@ static void unref_worker(struct drm_flip
- 	struct drm_device *dev = tilcdc_crtc->base.dev;
- 
- 	mutex_lock(&dev->mode_config.mutex);
--	drm_framebuffer_unreference(val);
-+	drm_framebuffer_put(val);
- 	mutex_unlock(&dev->mode_config.mutex);
- }
- 
-@@ -464,7 +464,7 @@ static void tilcdc_crtc_set_mode(struct
- 
- 	set_scanout(crtc, fb);
- 
--	drm_framebuffer_reference(fb);
-+	drm_framebuffer_get(fb);
- 
- 	crtc->hwmode = crtc->state->adjusted_mode;
- 
-@@ -644,7 +644,7 @@ int tilcdc_crtc_update_fb(struct drm_crt
- 		return -EBUSY;
- 	}
- 
--	drm_framebuffer_reference(fb);
-+	drm_framebuffer_get(fb);
- 
- 	crtc->primary->fb = fb;
- 	tilcdc_crtc->event = event;
---- linux-4.14/drivers/gpu/drm/tilcdc/tilcdc_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/tilcdc/tilcdc_drv.c	2017-12-14 06:39:58.523903643 +0100
-@@ -23,6 +23,7 @@
- #include <drm/drm_atomic.h>
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_fb_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- 
- #include "tilcdc_drv.h"
- #include "tilcdc_regs.h"
-@@ -65,7 +66,7 @@ static struct of_device_id tilcdc_of_mat
- static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
- 		struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
- {
--	return drm_fb_cma_create(dev, file_priv, mode_cmd);
-+	return drm_gem_fb_create(dev, file_priv, mode_cmd);
- }
- 
- static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
-@@ -225,7 +226,7 @@ static void tilcdc_fini(struct drm_devic
- 
- 	pm_runtime_disable(dev->dev);
- 
--	drm_dev_unref(dev);
-+	drm_dev_put(dev);
- }
- 
- static int tilcdc_init(struct drm_driver *ddrv, struct device *dev)
---- linux-4.14/drivers/gpu/drm/tinydrm/core/tinydrm-core.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/tinydrm/core/tinydrm-core.c	2017-12-14 06:39:58.524903643 +0100
-@@ -10,6 +10,7 @@
- #include <drm/drm_atomic.h>
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_crtc_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/tinydrm/tinydrm.h>
- #include <linux/device.h>
- #include <linux/dma-buf.h>
-@@ -128,7 +129,7 @@ tinydrm_fb_create(struct drm_device *drm
- {
- 	struct tinydrm_device *tdev = drm->dev_private;
- 
--	return drm_fb_cma_create_with_funcs(drm, file_priv, mode_cmd,
-+	return drm_gem_fb_create_with_funcs(drm, file_priv, mode_cmd,
- 					    tdev->fb_funcs);
- }
- 
---- linux-4.14/drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c	2017-12-14 06:39:58.524903643 +0100
-@@ -9,6 +9,7 @@
- 
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_crtc_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drm_modes.h>
- #include <drm/tinydrm/tinydrm.h>
- 
-@@ -50,7 +51,6 @@ static int tinydrm_connector_get_modes(s
- 
- static const struct drm_connector_helper_funcs tinydrm_connector_hfuncs = {
- 	.get_modes = tinydrm_connector_get_modes,
--	.best_encoder = drm_atomic_helper_best_encoder,
- };
- 
- static enum drm_connector_status
-@@ -144,7 +144,7 @@ EXPORT_SYMBOL(tinydrm_display_pipe_updat
-  * @pipe: Simple display pipe
-  * @plane_state: Plane state
-  *
-- * This function uses drm_fb_cma_prepare_fb() to check if the plane FB has an
-+ * This function uses drm_gem_fb_prepare_fb() to check if the plane FB has an
-  * dma-buf attached, extracts the exclusive fence and attaches it to plane
-  * state for the atomic helper to wait on. Drivers can use this as their
-  * &drm_simple_display_pipe_funcs->prepare_fb callback.
-@@ -152,7 +152,7 @@ EXPORT_SYMBOL(tinydrm_display_pipe_updat
- int tinydrm_display_pipe_prepare_fb(struct drm_simple_display_pipe *pipe,
- 				    struct drm_plane_state *plane_state)
- {
--	return drm_fb_cma_prepare_fb(&pipe->plane, plane_state);
-+	return drm_gem_fb_prepare_fb(&pipe->plane, plane_state);
- }
- EXPORT_SYMBOL(tinydrm_display_pipe_prepare_fb);
- 
---- linux-4.14/drivers/gpu/drm/tinydrm/mi0283qt.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/tinydrm/mi0283qt.c	2017-12-14 06:39:58.524903643 +0100
-@@ -31,7 +31,7 @@ static int mi0283qt_init(struct mipi_dbi
- 
- 	ret = regulator_enable(mipi->regulator);
- 	if (ret) {
--		dev_err(dev, "Failed to enable regulator %d\n", ret);
-+		DRM_DEV_ERROR(dev, "Failed to enable regulator %d\n", ret);
- 		return ret;
- 	}
- 
-@@ -42,7 +42,7 @@ static int mi0283qt_init(struct mipi_dbi
- 	mipi_dbi_hw_reset(mipi);
- 	ret = mipi_dbi_command(mipi, MIPI_DCS_SOFT_RESET);
- 	if (ret) {
--		dev_err(dev, "Error sending command %d\n", ret);
-+		DRM_DEV_ERROR(dev, "Error sending command %d\n", ret);
- 		regulator_disable(mipi->regulator);
- 		return ret;
- 	}
-@@ -163,7 +163,6 @@ MODULE_DEVICE_TABLE(spi, mi0283qt_id);
- static int mi0283qt_probe(struct spi_device *spi)
- {
- 	struct device *dev = &spi->dev;
--	struct tinydrm_device *tdev;
- 	struct mipi_dbi *mipi;
- 	struct gpio_desc *dc;
- 	u32 rotation = 0;
-@@ -175,13 +174,13 @@ static int mi0283qt_probe(struct spi_dev
- 
- 	mipi->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
- 	if (IS_ERR(mipi->reset)) {
--		dev_err(dev, "Failed to get gpio 'reset'\n");
-+		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
- 		return PTR_ERR(mipi->reset);
- 	}
- 
- 	dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
- 	if (IS_ERR(dc)) {
--		dev_err(dev, "Failed to get gpio 'dc'\n");
-+		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
- 		return PTR_ERR(dc);
- 	}
- 
-@@ -215,20 +214,9 @@ static int mi0283qt_probe(struct spi_dev
- 		return ret;
- 	}
- 
--	tdev = &mipi->tinydrm;
--
--	ret = devm_tinydrm_register(tdev);
--	if (ret)
--		return ret;
--
- 	spi_set_drvdata(spi, mipi);
- 
--	DRM_DEBUG_DRIVER("Initialized %s:%s @%uMHz on minor %d\n",
--			 tdev->drm->driver->name, dev_name(dev),
--			 spi->max_speed_hz / 1000000,
--			 tdev->drm->primary->index);
--
--	return 0;
-+	return devm_tinydrm_register(&mipi->tinydrm);
- }
- 
- static void mi0283qt_shutdown(struct spi_device *spi)
---- linux-4.14/drivers/gpu/drm/tinydrm/mipi-dbi.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/tinydrm/mipi-dbi.c	2017-12-14 06:39:58.524903643 +0100
-@@ -9,6 +9,7 @@
-  * (at your option) any later version.
-  */
- 
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/tinydrm/mipi-dbi.h>
- #include <drm/tinydrm/tinydrm-helpers.h>
- #include <linux/debugfs.h>
-@@ -253,8 +254,8 @@ out_unlock:
- }
- 
- static const struct drm_framebuffer_funcs mipi_dbi_fb_funcs = {
--	.destroy	= drm_fb_cma_destroy,
--	.create_handle	= drm_fb_cma_create_handle,
-+	.destroy	= drm_gem_fb_destroy,
-+	.create_handle	= drm_gem_fb_create_handle,
- 	.dirty		= mipi_dbi_fb_dirty,
- };
- 
-@@ -842,6 +843,8 @@ int mipi_dbi_spi_init(struct spi_device
- 			return -ENOMEM;
- 	}
- 
-+	DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
-+
- 	return 0;
- }
- EXPORT_SYMBOL(mipi_dbi_spi_init);
---- linux-4.14/drivers/gpu/drm/tinydrm/repaper.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/tinydrm/repaper.c	2017-12-14 06:39:58.524903643 +0100
-@@ -26,6 +26,7 @@
- #include <linux/spi/spi.h>
- #include <linux/thermal.h>
- 
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/tinydrm/tinydrm.h>
- #include <drm/tinydrm/tinydrm-helpers.h>
- 
-@@ -473,8 +474,7 @@ static void repaper_get_temperature(stru
- 
- 	ret = thermal_zone_get_temp(epd->thermal, &temperature);
- 	if (ret) {
--		dev_err(&epd->spi->dev, "Failed to get temperature (%d)\n",
--			ret);
-+		DRM_DEV_ERROR(&epd->spi->dev, "Failed to get temperature (%d)\n", ret);
- 		return;
- 	}
- 
-@@ -629,15 +629,15 @@ out_unlock:
- 	mutex_unlock(&tdev->dirty_lock);
- 
- 	if (ret)
--		dev_err(fb->dev->dev, "Failed to update display (%d)\n", ret);
-+		DRM_DEV_ERROR(fb->dev->dev, "Failed to update display (%d)\n", ret);
- 	kfree(buf);
- 
- 	return ret;
- }
- 
- static const struct drm_framebuffer_funcs repaper_fb_funcs = {
--	.destroy	= drm_fb_cma_destroy,
--	.create_handle	= drm_fb_cma_create_handle,
-+	.destroy	= drm_gem_fb_destroy,
-+	.create_handle	= drm_gem_fb_create_handle,
- 	.dirty		= repaper_fb_dirty,
- };
- 
-@@ -703,7 +703,7 @@ static void repaper_pipe_enable(struct d
- 	}
- 
- 	if (!i) {
--		dev_err(dev, "timeout waiting for panel to become ready.\n");
-+		DRM_DEV_ERROR(dev, "timeout waiting for panel to become ready.\n");
- 		power_off(epd);
- 		return;
- 	}
-@@ -725,9 +725,9 @@ static void repaper_pipe_enable(struct d
- 	ret = repaper_read_val(spi, 0x0f);
- 	if (ret < 0 || !(ret & 0x80)) {
- 		if (ret < 0)
--			dev_err(dev, "failed to read chip (%d)\n", ret);
-+			DRM_DEV_ERROR(dev, "failed to read chip (%d)\n", ret);
- 		else
--			dev_err(dev, "panel is reported broken\n");
-+			DRM_DEV_ERROR(dev, "panel is reported broken\n");
- 		power_off(epd);
- 		return;
- 	}
-@@ -767,7 +767,7 @@ static void repaper_pipe_enable(struct d
- 		/* check DC/DC */
- 		ret = repaper_read_val(spi, 0x0f);
- 		if (ret < 0) {
--			dev_err(dev, "failed to read chip (%d)\n", ret);
-+			DRM_DEV_ERROR(dev, "failed to read chip (%d)\n", ret);
- 			power_off(epd);
- 			return;
- 		}
-@@ -779,7 +779,7 @@ static void repaper_pipe_enable(struct d
- 	}
- 
- 	if (!dc_ok) {
--		dev_err(dev, "dc/dc failed\n");
-+		DRM_DEV_ERROR(dev, "dc/dc failed\n");
- 		power_off(epd);
- 		return;
- 	}
-@@ -959,7 +959,7 @@ static int repaper_probe(struct spi_devi
- 	if (IS_ERR(epd->panel_on)) {
- 		ret = PTR_ERR(epd->panel_on);
- 		if (ret != -EPROBE_DEFER)
--			dev_err(dev, "Failed to get gpio 'panel-on'\n");
-+			DRM_DEV_ERROR(dev, "Failed to get gpio 'panel-on'\n");
- 		return ret;
- 	}
- 
-@@ -967,7 +967,7 @@ static int repaper_probe(struct spi_devi
- 	if (IS_ERR(epd->discharge)) {
- 		ret = PTR_ERR(epd->discharge);
- 		if (ret != -EPROBE_DEFER)
--			dev_err(dev, "Failed to get gpio 'discharge'\n");
-+			DRM_DEV_ERROR(dev, "Failed to get gpio 'discharge'\n");
- 		return ret;
- 	}
- 
-@@ -975,7 +975,7 @@ static int repaper_probe(struct spi_devi
- 	if (IS_ERR(epd->reset)) {
- 		ret = PTR_ERR(epd->reset);
- 		if (ret != -EPROBE_DEFER)
--			dev_err(dev, "Failed to get gpio 'reset'\n");
-+			DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
- 		return ret;
- 	}
- 
-@@ -983,7 +983,7 @@ static int repaper_probe(struct spi_devi
- 	if (IS_ERR(epd->busy)) {
- 		ret = PTR_ERR(epd->busy);
- 		if (ret != -EPROBE_DEFER)
--			dev_err(dev, "Failed to get gpio 'busy'\n");
-+			DRM_DEV_ERROR(dev, "Failed to get gpio 'busy'\n");
- 		return ret;
- 	}
- 
-@@ -991,8 +991,7 @@ static int repaper_probe(struct spi_devi
- 					 &thermal_zone)) {
- 		epd->thermal = thermal_zone_get_zone_by_name(thermal_zone);
- 		if (IS_ERR(epd->thermal)) {
--			dev_err(dev, "Failed to get thermal zone: %s\n",
--				thermal_zone);
-+			DRM_DEV_ERROR(dev, "Failed to get thermal zone: %s\n", thermal_zone);
- 			return PTR_ERR(epd->thermal);
- 		}
- 	}
-@@ -1033,7 +1032,7 @@ static int repaper_probe(struct spi_devi
- 		if (IS_ERR(epd->border)) {
- 			ret = PTR_ERR(epd->border);
- 			if (ret != -EPROBE_DEFER)
--				dev_err(dev, "Failed to get gpio 'border'\n");
-+				DRM_DEV_ERROR(dev, "Failed to get gpio 'border'\n");
- 			return ret;
- 		}
- 
-@@ -1078,19 +1077,11 @@ static int repaper_probe(struct spi_devi
- 		return ret;
- 
- 	drm_mode_config_reset(tdev->drm);
--
--	ret = devm_tinydrm_register(tdev);
--	if (ret)
--		return ret;
--
- 	spi_set_drvdata(spi, tdev);
- 
--	DRM_DEBUG_DRIVER("Initialized %s:%s @%uMHz on minor %d\n",
--			 tdev->drm->driver->name, dev_name(dev),
--			 spi->max_speed_hz / 1000000,
--			 tdev->drm->primary->index);
-+	DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
- 
--	return 0;
-+	return devm_tinydrm_register(tdev);
- }
- 
- static void repaper_shutdown(struct spi_device *spi)
---- linux-4.14/drivers/gpu/drm/tinydrm/st7586.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/tinydrm/st7586.c	2017-12-14 06:39:58.524903643 +0100
-@@ -17,6 +17,7 @@
- #include <linux/spi/spi.h>
- #include <video/mipi_display.h>
- 
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/tinydrm/mipi-dbi.h>
- #include <drm/tinydrm/tinydrm-helpers.h>
- 
-@@ -167,8 +168,8 @@ out_unlock:
- }
- 
- static const struct drm_framebuffer_funcs st7586_fb_funcs = {
--	.destroy	= drm_fb_cma_destroy,
--	.create_handle	= drm_fb_cma_create_handle,
-+	.destroy	= drm_gem_fb_destroy,
-+	.create_handle	= drm_gem_fb_create_handle,
- 	.dirty		= st7586_fb_dirty,
- };
- 
-@@ -187,7 +188,7 @@ static void st7586_pipe_enable(struct dr
- 	mipi_dbi_hw_reset(mipi);
- 	ret = mipi_dbi_command(mipi, ST7586_AUTO_READ_CTRL, 0x9f);
- 	if (ret) {
--		dev_err(dev, "Error sending command %d\n", ret);
-+		DRM_DEV_ERROR(dev, "Error sending command %d\n", ret);
- 		return;
- 	}
- 
-@@ -343,7 +344,6 @@ MODULE_DEVICE_TABLE(spi, st7586_id);
- static int st7586_probe(struct spi_device *spi)
- {
- 	struct device *dev = &spi->dev;
--	struct tinydrm_device *tdev;
- 	struct mipi_dbi *mipi;
- 	struct gpio_desc *a0;
- 	u32 rotation = 0;
-@@ -355,13 +355,13 @@ static int st7586_probe(struct spi_devic
- 
- 	mipi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
- 	if (IS_ERR(mipi->reset)) {
--		dev_err(dev, "Failed to get gpio 'reset'\n");
-+		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
- 		return PTR_ERR(mipi->reset);
- 	}
- 
- 	a0 = devm_gpiod_get(dev, "a0", GPIOD_OUT_LOW);
- 	if (IS_ERR(a0)) {
--		dev_err(dev, "Failed to get gpio 'a0'\n");
-+		DRM_DEV_ERROR(dev, "Failed to get gpio 'a0'\n");
- 		return PTR_ERR(a0);
- 	}
- 
-@@ -388,20 +388,9 @@ static int st7586_probe(struct spi_devic
- 	if (ret)
- 		return ret;
- 
--	tdev = &mipi->tinydrm;
--
--	ret = devm_tinydrm_register(tdev);
--	if (ret)
--		return ret;
--
- 	spi_set_drvdata(spi, mipi);
- 
--	DRM_DEBUG_DRIVER("Initialized %s:%s @%uMHz on minor %d\n",
--			 tdev->drm->driver->name, dev_name(dev),
--			 spi->max_speed_hz / 1000000,
--			 tdev->drm->primary->index);
--
--	return 0;
-+	return devm_tinydrm_register(&mipi->tinydrm);
- }
- 
- static void st7586_shutdown(struct spi_device *spi)
---- linux-4.14/drivers/gpu/drm/ttm/ttm_execbuf_util.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/ttm/ttm_execbuf_util.c	2017-12-14 06:39:58.524903643 +0100
-@@ -38,7 +38,7 @@ static void ttm_eu_backoff_reservation_r
- 	list_for_each_entry_continue_reverse(entry, list, head) {
- 		struct ttm_buffer_object *bo = entry->bo;
- 
--		__ttm_bo_unreserve(bo);
-+		reservation_object_unlock(bo->resv);
- 	}
- }
- 
-@@ -69,7 +69,7 @@ void ttm_eu_backoff_reservation(struct w
- 		struct ttm_buffer_object *bo = entry->bo;
- 
- 		ttm_bo_add_to_lru(bo);
--		__ttm_bo_unreserve(bo);
-+		reservation_object_unlock(bo->resv);
- 	}
- 	spin_unlock(&glob->lru_lock);
- 
-@@ -112,7 +112,7 @@ int ttm_eu_reserve_buffers(struct ww_acq
- 
- 		ret = __ttm_bo_reserve(bo, intr, (ticket == NULL), ticket);
- 		if (!ret && unlikely(atomic_read(&bo->cpu_writers) > 0)) {
--			__ttm_bo_unreserve(bo);
-+			reservation_object_unlock(bo->resv);
- 
- 			ret = -EBUSY;
- 
-@@ -203,7 +203,7 @@ void ttm_eu_fence_buffer_objects(struct
- 		else
- 			reservation_object_add_excl_fence(bo->resv, fence);
- 		ttm_bo_add_to_lru(bo);
--		__ttm_bo_unreserve(bo);
-+		reservation_object_unlock(bo->resv);
- 	}
- 	spin_unlock(&glob->lru_lock);
- 	if (ticket)
---- linux-4.14/drivers/gpu/drm/ttm/ttm_memory.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/ttm/ttm_memory.c	2017-12-14 06:39:58.524903643 +0100
-@@ -546,8 +546,7 @@ int ttm_mem_global_alloc(struct ttm_mem_
- EXPORT_SYMBOL(ttm_mem_global_alloc);
- 
- int ttm_mem_global_alloc_page(struct ttm_mem_global *glob,
--			      struct page *page,
--			      bool no_wait, bool interruptible)
-+			      struct page *page, uint64_t size)
- {
- 
- 	struct ttm_mem_zone *zone = NULL;
-@@ -564,11 +563,11 @@ int ttm_mem_global_alloc_page(struct ttm
- 	if (glob->zone_dma32 && page_to_pfn(page) > 0x00100000UL)
- 		zone = glob->zone_kernel;
- #endif
--	return ttm_mem_global_alloc_zone(glob, zone, PAGE_SIZE, no_wait,
--					 interruptible);
-+	return ttm_mem_global_alloc_zone(glob, zone, size, false, false);
- }
- 
--void ttm_mem_global_free_page(struct ttm_mem_global *glob, struct page *page)
-+void ttm_mem_global_free_page(struct ttm_mem_global *glob, struct page *page,
-+			      uint64_t size)
- {
- 	struct ttm_mem_zone *zone = NULL;
- 
-@@ -579,10 +578,9 @@ void ttm_mem_global_free_page(struct ttm
- 	if (glob->zone_dma32 && page_to_pfn(page) > 0x00100000UL)
- 		zone = glob->zone_kernel;
- #endif
--	ttm_mem_global_free_zone(glob, zone, PAGE_SIZE);
-+	ttm_mem_global_free_zone(glob, zone, size);
- }
- 
--
- size_t ttm_round_pot(size_t size)
- {
- 	if ((size & (size - 1)) == 0)
---- linux-4.14/drivers/gpu/drm/ttm/ttm_page_alloc.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/ttm/ttm_page_alloc.c	2017-12-14 06:39:58.524903643 +0100
-@@ -95,7 +95,7 @@ struct ttm_pool_opts {
- 	unsigned	small;
- };
- 
--#define NUM_POOLS 4
-+#define NUM_POOLS 6
- 
- /**
-  * struct ttm_pool_manager - Holds memory pools for fst allocation
-@@ -122,6 +122,8 @@ struct ttm_pool_manager {
- 			struct ttm_page_pool	uc_pool;
- 			struct ttm_page_pool	wc_pool_dma32;
- 			struct ttm_page_pool	uc_pool_dma32;
-+			struct ttm_page_pool	wc_pool_huge;
-+			struct ttm_page_pool	uc_pool_huge;
- 		} ;
- 	};
- };
-@@ -256,8 +258,8 @@ static int set_pages_array_uc(struct pag
- 
- /**
-  * Select the right pool or requested caching state and ttm flags. */
--static struct ttm_page_pool *ttm_get_pool(int flags,
--		enum ttm_caching_state cstate)
-+static struct ttm_page_pool *ttm_get_pool(int flags, bool huge,
-+					  enum ttm_caching_state cstate)
- {
- 	int pool_index;
- 
-@@ -269,9 +271,15 @@ static struct ttm_page_pool *ttm_get_poo
- 	else
- 		pool_index = 0x1;
- 
--	if (flags & TTM_PAGE_FLAG_DMA32)
-+	if (flags & TTM_PAGE_FLAG_DMA32) {
-+		if (huge)
-+			return NULL;
- 		pool_index |= 0x2;
- 
-+	} else if (huge) {
-+		pool_index |= 0x4;
-+	}
-+
- 	return &_manager->pools[pool_index];
- }
- 
-@@ -321,7 +329,7 @@ static int ttm_page_pool_free(struct ttm
- 		pages_to_free = kmalloc(npages_to_free * sizeof(struct page *),
- 					GFP_KERNEL);
- 	if (!pages_to_free) {
--		pr_err("Failed to allocate memory for pool free operation\n");
-+		pr_debug("Failed to allocate memory for pool free operation\n");
- 		return 0;
- 	}
- 
-@@ -494,12 +502,14 @@ static void ttm_handle_caching_state_fai
-  * pages returned in pages array.
-  */
- static int ttm_alloc_new_pages(struct list_head *pages, gfp_t gfp_flags,
--		int ttm_flags, enum ttm_caching_state cstate, unsigned count)
-+			       int ttm_flags, enum ttm_caching_state cstate,
-+			       unsigned count, unsigned order)
- {
- 	struct page **caching_array;
- 	struct page *p;
- 	int r = 0;
--	unsigned i, cpages;
-+	unsigned i, j, cpages;
-+	unsigned npages = 1 << order;
- 	unsigned max_cpages = min(count,
- 			(unsigned)(PAGE_SIZE/sizeof(struct page *)));
- 
-@@ -507,15 +517,15 @@ static int ttm_alloc_new_pages(struct li
- 	caching_array = kmalloc(max_cpages*sizeof(struct page *), GFP_KERNEL);
- 
- 	if (!caching_array) {
--		pr_err("Unable to allocate table for new pages\n");
-+		pr_debug("Unable to allocate table for new pages\n");
- 		return -ENOMEM;
- 	}
- 
- 	for (i = 0, cpages = 0; i < count; ++i) {
--		p = alloc_page(gfp_flags);
-+		p = alloc_pages(gfp_flags, order);
- 
- 		if (!p) {
--			pr_err("Unable to get page %u\n", i);
-+			pr_debug("Unable to get page %u\n", i);
- 
- 			/* store already allocated pages in the pool after
- 			 * setting the caching state */
-@@ -531,14 +541,18 @@ static int ttm_alloc_new_pages(struct li
- 			goto out;
- 		}
- 
-+		list_add(&p->lru, pages);
-+
- #ifdef CONFIG_HIGHMEM
- 		/* gfp flags of highmem page should never be dma32 so we
- 		 * we should be fine in such case
- 		 */
--		if (!PageHighMem(p))
-+		if (PageHighMem(p))
-+			continue;
-+
- #endif
--		{
--			caching_array[cpages++] = p;
-+		for (j = 0; j < npages; ++j) {
-+			caching_array[cpages++] = p++;
- 			if (cpages == max_cpages) {
- 
- 				r = ttm_set_pages_caching(caching_array,
-@@ -552,8 +566,6 @@ static int ttm_alloc_new_pages(struct li
- 				cpages = 0;
- 			}
- 		}
--
--		list_add(&p->lru, pages);
- 	}
- 
- 	if (cpages) {
-@@ -573,9 +585,9 @@ out:
-  * Fill the given pool if there aren't enough pages and the requested number of
-  * pages is small.
-  */
--static void ttm_page_pool_fill_locked(struct ttm_page_pool *pool,
--		int ttm_flags, enum ttm_caching_state cstate, unsigned count,
--		unsigned long *irq_flags)
-+static void ttm_page_pool_fill_locked(struct ttm_page_pool *pool, int ttm_flags,
-+				      enum ttm_caching_state cstate,
-+				      unsigned count, unsigned long *irq_flags)
- {
- 	struct page *p;
- 	int r;
-@@ -605,7 +617,7 @@ static void ttm_page_pool_fill_locked(st
- 
- 		INIT_LIST_HEAD(&new_pages);
- 		r = ttm_alloc_new_pages(&new_pages, pool->gfp_flags, ttm_flags,
--				cstate,	alloc_size);
-+					cstate, alloc_size, 0);
- 		spin_lock_irqsave(&pool->lock, *irq_flags);
- 
- 		if (!r) {
-@@ -613,7 +625,7 @@ static void ttm_page_pool_fill_locked(st
- 			++pool->nrefills;
- 			pool->npages += alloc_size;
- 		} else {
--			pr_err("Failed to fill pool (%p)\n", pool);
-+			pr_debug("Failed to fill pool (%p)\n", pool);
- 			/* If we have any pages left put them to the pool. */
- 			list_for_each_entry(p, &new_pages, lru) {
- 				++cpages;
-@@ -627,22 +639,25 @@ static void ttm_page_pool_fill_locked(st
- }
- 
- /**
-- * Cut 'count' number of pages from the pool and put them on the return list.
-+ * Allocate pages from the pool and put them on the return list.
-  *
-- * @return count of pages still required to fulfill the request.
-+ * @return zero for success or negative error code.
-  */
--static unsigned ttm_page_pool_get_pages(struct ttm_page_pool *pool,
--					struct list_head *pages,
--					int ttm_flags,
--					enum ttm_caching_state cstate,
--					unsigned count)
-+static int ttm_page_pool_get_pages(struct ttm_page_pool *pool,
-+				   struct list_head *pages,
-+				   int ttm_flags,
-+				   enum ttm_caching_state cstate,
-+				   unsigned count, unsigned order)
- {
- 	unsigned long irq_flags;
- 	struct list_head *p;
- 	unsigned i;
-+	int r = 0;
- 
- 	spin_lock_irqsave(&pool->lock, irq_flags);
--	ttm_page_pool_fill_locked(pool, ttm_flags, cstate, count, &irq_flags);
-+	if (!order)
-+		ttm_page_pool_fill_locked(pool, ttm_flags, cstate, count,
-+					  &irq_flags);
- 
- 	if (count >= pool->npages) {
- 		/* take all pages from the pool */
-@@ -672,32 +687,126 @@ static unsigned ttm_page_pool_get_pages(
- 	count = 0;
- out:
- 	spin_unlock_irqrestore(&pool->lock, irq_flags);
--	return count;
-+
-+	/* clear the pages coming from the pool if requested */
-+	if (ttm_flags & TTM_PAGE_FLAG_ZERO_ALLOC) {
-+		struct page *page;
-+
-+		list_for_each_entry(page, pages, lru) {
-+			if (PageHighMem(page))
-+				clear_highpage(page);
-+			else
-+				clear_page(page_address(page));
-+		}
-+	}
-+
-+	/* If pool didn't have enough pages allocate new one. */
-+	if (count) {
-+		gfp_t gfp_flags = pool->gfp_flags;
-+
-+		/* set zero flag for page allocation if required */
-+		if (ttm_flags & TTM_PAGE_FLAG_ZERO_ALLOC)
-+			gfp_flags |= __GFP_ZERO;
-+
-+		/* ttm_alloc_new_pages doesn't reference pool so we can run
-+		 * multiple requests in parallel.
-+		 **/
-+		r = ttm_alloc_new_pages(pages, gfp_flags, ttm_flags, cstate,
-+					count, order);
-+	}
-+
-+	return r;
- }
- 
- /* Put all pages in pages list to correct pool to wait for reuse */
- static void ttm_put_pages(struct page **pages, unsigned npages, int flags,
- 			  enum ttm_caching_state cstate)
- {
-+	struct ttm_page_pool *pool = ttm_get_pool(flags, false, cstate);
-+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
-+	struct ttm_page_pool *huge = ttm_get_pool(flags, true, cstate);
-+#endif
- 	unsigned long irq_flags;
--	struct ttm_page_pool *pool = ttm_get_pool(flags, cstate);
- 	unsigned i;
- 
- 	if (pool == NULL) {
- 		/* No pool for this memory type so free the pages */
--		for (i = 0; i < npages; i++) {
--			if (pages[i]) {
--				if (page_count(pages[i]) != 1)
--					pr_err("Erroneous page count. Leaking pages.\n");
--				__free_page(pages[i]);
--				pages[i] = NULL;
-+		i = 0;
-+		while (i < npages) {
-+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
-+			struct page *p = pages[i];
-+#endif
-+			unsigned order = 0, j;
-+
-+			if (!pages[i]) {
-+				++i;
-+				continue;
-+			}
-+
-+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
-+			for (j = 0; j < HPAGE_PMD_NR; ++j)
-+				if (p++ != pages[i + j])
-+				    break;
-+
-+			if (j == HPAGE_PMD_NR)
-+				order = HPAGE_PMD_ORDER;
-+#endif
-+
-+			if (page_count(pages[i]) != 1)
-+				pr_err("Erroneous page count. Leaking pages.\n");
-+			__free_pages(pages[i], order);
-+
-+			j = 1 << order;
-+			while (j) {
-+				pages[i++] = NULL;
-+				--j;
- 			}
- 		}
- 		return;
- 	}
- 
-+	i = 0;
-+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
-+	if (huge) {
-+		unsigned max_size, n2free;
-+
-+		spin_lock_irqsave(&huge->lock, irq_flags);
-+		while (i < npages) {
-+			struct page *p = pages[i];
-+			unsigned j;
-+
-+			if (!p)
-+				break;
-+
-+			for (j = 0; j < HPAGE_PMD_NR; ++j)
-+				if (p++ != pages[i + j])
-+				    break;
-+
-+			if (j != HPAGE_PMD_NR)
-+				break;
-+
-+			list_add_tail(&pages[i]->lru, &huge->list);
-+
-+			for (j = 0; j < HPAGE_PMD_NR; ++j)
-+				pages[i++] = NULL;
-+			huge->npages++;
-+		}
-+
-+		/* Check that we don't go over the pool limit */
-+		max_size = _manager->options.max_size;
-+		max_size /= HPAGE_PMD_NR;
-+		if (huge->npages > max_size)
-+			n2free = huge->npages - max_size;
-+		else
-+			n2free = 0;
-+		spin_unlock_irqrestore(&huge->lock, irq_flags);
-+		if (n2free)
-+			ttm_page_pool_free(huge, n2free, false);
-+	}
-+#endif
-+
- 	spin_lock_irqsave(&pool->lock, irq_flags);
--	for (i = 0; i < npages; i++) {
-+	while (i < npages) {
- 		if (pages[i]) {
- 			if (page_count(pages[i]) != 1)
- 				pr_err("Erroneous page count. Leaking pages.\n");
-@@ -705,6 +814,7 @@ static void ttm_put_pages(struct page **
- 			pages[i] = NULL;
- 			pool->npages++;
- 		}
-+		++i;
- 	}
- 	/* Check that we don't go over the pool limit */
- 	npages = 0;
-@@ -727,75 +837,96 @@ static void ttm_put_pages(struct page **
- static int ttm_get_pages(struct page **pages, unsigned npages, int flags,
- 			 enum ttm_caching_state cstate)
- {
--	struct ttm_page_pool *pool = ttm_get_pool(flags, cstate);
-+	struct ttm_page_pool *pool = ttm_get_pool(flags, false, cstate);
-+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
-+	struct ttm_page_pool *huge = ttm_get_pool(flags, true, cstate);
-+#endif
- 	struct list_head plist;
- 	struct page *p = NULL;
--	gfp_t gfp_flags = GFP_USER;
- 	unsigned count;
- 	int r;
- 
--	/* set zero flag for page allocation if required */
--	if (flags & TTM_PAGE_FLAG_ZERO_ALLOC)
--		gfp_flags |= __GFP_ZERO;
--
- 	/* No pool for cached pages */
- 	if (pool == NULL) {
-+		gfp_t gfp_flags = GFP_USER;
-+		unsigned i;
-+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
-+		unsigned j;
-+#endif
-+
-+		/* set zero flag for page allocation if required */
-+		if (flags & TTM_PAGE_FLAG_ZERO_ALLOC)
-+			gfp_flags |= __GFP_ZERO;
-+
- 		if (flags & TTM_PAGE_FLAG_DMA32)
- 			gfp_flags |= GFP_DMA32;
- 		else
- 			gfp_flags |= GFP_HIGHUSER;
- 
--		for (r = 0; r < npages; ++r) {
-+		i = 0;
-+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
-+		while (npages >= HPAGE_PMD_NR) {
-+			gfp_t huge_flags = gfp_flags;
-+
-+			huge_flags |= GFP_TRANSHUGE;
-+			huge_flags &= ~__GFP_MOVABLE;
-+			huge_flags &= ~__GFP_COMP;
-+			p = alloc_pages(huge_flags, HPAGE_PMD_ORDER);
-+			if (!p)
-+				break;
-+
-+			for (j = 0; j < HPAGE_PMD_NR; ++j)
-+				pages[i++] = p++;
-+
-+			npages -= HPAGE_PMD_NR;
-+		}
-+#endif
-+
-+		while (npages) {
- 			p = alloc_page(gfp_flags);
- 			if (!p) {
--
--				pr_err("Unable to allocate page\n");
-+				pr_debug("Unable to allocate page\n");
- 				return -ENOMEM;
- 			}
- 
--			pages[r] = p;
-+			pages[i++] = p;
-+			--npages;
- 		}
- 		return 0;
- 	}
- 
--	/* combine zero flag to pool flags */
--	gfp_flags |= pool->gfp_flags;
--
--	/* First we take pages from the pool */
--	INIT_LIST_HEAD(&plist);
--	npages = ttm_page_pool_get_pages(pool, &plist, flags, cstate, npages);
- 	count = 0;
--	list_for_each_entry(p, &plist, lru) {
--		pages[count++] = p;
--	}
- 
--	/* clear the pages coming from the pool if requested */
--	if (flags & TTM_PAGE_FLAG_ZERO_ALLOC) {
-+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
-+	if (huge && npages >= HPAGE_PMD_NR) {
-+		INIT_LIST_HEAD(&plist);
-+		ttm_page_pool_get_pages(huge, &plist, flags, cstate,
-+					npages / HPAGE_PMD_NR,
-+					HPAGE_PMD_ORDER);
-+
- 		list_for_each_entry(p, &plist, lru) {
--			if (PageHighMem(p))
--				clear_highpage(p);
--			else
--				clear_page(page_address(p));
-+			unsigned j;
-+
-+			for (j = 0; j < HPAGE_PMD_NR; ++j)
-+				pages[count++] = &p[j];
- 		}
- 	}
-+#endif
- 
--	/* If pool didn't have enough pages allocate new one. */
--	if (npages > 0) {
--		/* ttm_alloc_new_pages doesn't reference pool so we can run
--		 * multiple requests in parallel.
--		 **/
--		INIT_LIST_HEAD(&plist);
--		r = ttm_alloc_new_pages(&plist, gfp_flags, flags, cstate, npages);
--		list_for_each_entry(p, &plist, lru) {
--			pages[count++] = p;
--		}
--		if (r) {
--			/* If there is any pages in the list put them back to
--			 * the pool. */
--			pr_err("Failed to allocate extra pages for large request\n");
--			ttm_put_pages(pages, count, flags, cstate);
--			return r;
--		}
-+	INIT_LIST_HEAD(&plist);
-+	r = ttm_page_pool_get_pages(pool, &plist, flags, cstate,
-+				    npages - count, 0);
-+
-+	list_for_each_entry(p, &plist, lru)
-+		pages[count++] = p;
-+
-+	if (r) {
-+		/* If there is any pages in the list put them back to
-+		 * the pool.
-+		 */
-+		pr_debug("Failed to allocate extra pages for large request\n");
-+		ttm_put_pages(pages, count, flags, cstate);
-+		return r;
- 	}
- 
- 	return 0;
-@@ -832,6 +963,14 @@ int ttm_page_alloc_init(struct ttm_mem_g
- 	ttm_page_pool_init_locked(&_manager->uc_pool_dma32,
- 				  GFP_USER | GFP_DMA32, "uc dma");
- 
-+	ttm_page_pool_init_locked(&_manager->wc_pool_huge,
-+				  GFP_TRANSHUGE	& ~(__GFP_MOVABLE | __GFP_COMP),
-+				  "wc huge");
-+
-+	ttm_page_pool_init_locked(&_manager->uc_pool_huge,
-+				  GFP_TRANSHUGE	& ~(__GFP_MOVABLE | __GFP_COMP)
-+				  , "uc huge");
-+
- 	_manager->options.max_size = max_pages;
- 	_manager->options.small = SMALL_ALLOCATION;
- 	_manager->options.alloc_size = NUM_PAGES_TO_ALLOC;
-@@ -873,17 +1012,16 @@ int ttm_pool_populate(struct ttm_tt *ttm
- 	if (ttm->state != tt_unpopulated)
- 		return 0;
- 
--	for (i = 0; i < ttm->num_pages; ++i) {
--		ret = ttm_get_pages(&ttm->pages[i], 1,
--				    ttm->page_flags,
--				    ttm->caching_state);
--		if (ret != 0) {
--			ttm_pool_unpopulate(ttm);
--			return -ENOMEM;
--		}
-+	ret = ttm_get_pages(ttm->pages, ttm->num_pages, ttm->page_flags,
-+			    ttm->caching_state);
-+	if (unlikely(ret != 0)) {
-+		ttm_pool_unpopulate(ttm);
-+		return ret;
-+	}
- 
-+	for (i = 0; i < ttm->num_pages; ++i) {
- 		ret = ttm_mem_global_alloc_page(mem_glob, ttm->pages[i],
--						false, false);
-+						PAGE_SIZE);
- 		if (unlikely(ret != 0)) {
- 			ttm_pool_unpopulate(ttm);
- 			return -ENOMEM;
-@@ -908,18 +1046,91 @@ void ttm_pool_unpopulate(struct ttm_tt *
- 	unsigned i;
- 
- 	for (i = 0; i < ttm->num_pages; ++i) {
--		if (ttm->pages[i]) {
--			ttm_mem_global_free_page(ttm->glob->mem_glob,
--						 ttm->pages[i]);
--			ttm_put_pages(&ttm->pages[i], 1,
--				      ttm->page_flags,
--				      ttm->caching_state);
--		}
-+		if (!ttm->pages[i])
-+			continue;
-+
-+		ttm_mem_global_free_page(ttm->glob->mem_glob, ttm->pages[i],
-+					 PAGE_SIZE);
- 	}
-+	ttm_put_pages(ttm->pages, ttm->num_pages, ttm->page_flags,
-+		      ttm->caching_state);
- 	ttm->state = tt_unpopulated;
- }
- EXPORT_SYMBOL(ttm_pool_unpopulate);
- 
-+#if defined(CONFIG_SWIOTLB) || defined(CONFIG_INTEL_IOMMU)
-+int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt)
-+{
-+	unsigned i, j;
-+	int r;
-+
-+	r = ttm_pool_populate(&tt->ttm);
-+	if (r)
-+		return r;
-+
-+	for (i = 0; i < tt->ttm.num_pages; ++i) {
-+		struct page *p = tt->ttm.pages[i];
-+		size_t num_pages = 1;
-+
-+		for (j = i + 1; j < tt->ttm.num_pages; ++j) {
-+			if (++p != tt->ttm.pages[j])
-+				break;
-+
-+			++num_pages;
-+		}
-+
-+		tt->dma_address[i] = dma_map_page(dev, tt->ttm.pages[i],
-+						  0, num_pages * PAGE_SIZE,
-+						  DMA_BIDIRECTIONAL);
-+		if (dma_mapping_error(dev, tt->dma_address[i])) {
-+			while (i--) {
-+				dma_unmap_page(dev, tt->dma_address[i],
-+					       PAGE_SIZE, DMA_BIDIRECTIONAL);
-+				tt->dma_address[i] = 0;
-+			}
-+			ttm_pool_unpopulate(&tt->ttm);
-+			return -EFAULT;
-+		}
-+
-+		for (j = 1; j < num_pages; ++j) {
-+			tt->dma_address[i + 1] = tt->dma_address[i] + PAGE_SIZE;
-+			++i;
-+		}
-+	}
-+	return 0;
-+}
-+EXPORT_SYMBOL(ttm_populate_and_map_pages);
-+
-+void ttm_unmap_and_unpopulate_pages(struct device *dev, struct ttm_dma_tt *tt)
-+{
-+	unsigned i, j;
-+
-+	for (i = 0; i < tt->ttm.num_pages;) {
-+		struct page *p = tt->ttm.pages[i];
-+		size_t num_pages = 1;
-+
-+		if (!tt->dma_address[i] || !tt->ttm.pages[i]) {
-+			++i;
-+			continue;
-+		}
-+
-+		for (j = i + 1; j < tt->ttm.num_pages; ++j) {
-+			if (++p != tt->ttm.pages[j])
-+				break;
-+
-+			++num_pages;
-+		}
-+
-+		dma_unmap_page(dev, tt->dma_address[i], num_pages * PAGE_SIZE,
-+			       DMA_BIDIRECTIONAL);
-+
-+		i += num_pages;
-+	}
-+	ttm_pool_unpopulate(&tt->ttm);
-+}
-+EXPORT_SYMBOL(ttm_unmap_and_unpopulate_pages);
-+#endif
-+
- int ttm_page_alloc_debugfs(struct seq_file *m, void *data)
- {
- 	struct ttm_page_pool *p;
-@@ -929,12 +1140,12 @@ int ttm_page_alloc_debugfs(struct seq_fi
- 		seq_printf(m, "No pool allocator running.\n");
- 		return 0;
- 	}
--	seq_printf(m, "%6s %12s %13s %8s\n",
-+	seq_printf(m, "%7s %12s %13s %8s\n",
- 			h[0], h[1], h[2], h[3]);
- 	for (i = 0; i < NUM_POOLS; ++i) {
- 		p = &_manager->pools[i];
- 
--		seq_printf(m, "%6s %12ld %13ld %8d\n",
-+		seq_printf(m, "%7s %12ld %13ld %8d\n",
- 				p->name, p->nrefills,
- 				p->nfrees, p->npages);
- 	}
---- linux-4.14/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c	2017-12-14 06:39:58.525903644 +0100
-@@ -60,37 +60,32 @@
- #define NUM_PAGES_TO_ALLOC		(PAGE_SIZE/sizeof(struct page *))
- #define SMALL_ALLOCATION		4
- #define FREE_ALL_PAGES			(~0U)
--/* times are in msecs */
--#define IS_UNDEFINED			(0)
--#define IS_WC				(1<<1)
--#define IS_UC				(1<<2)
--#define IS_CACHED			(1<<3)
--#define IS_DMA32			(1<<4)
-+#define VADDR_FLAG_HUGE_POOL		1UL
- 
- enum pool_type {
--	POOL_IS_UNDEFINED,
--	POOL_IS_WC = IS_WC,
--	POOL_IS_UC = IS_UC,
--	POOL_IS_CACHED = IS_CACHED,
--	POOL_IS_WC_DMA32 = IS_WC | IS_DMA32,
--	POOL_IS_UC_DMA32 = IS_UC | IS_DMA32,
--	POOL_IS_CACHED_DMA32 = IS_CACHED | IS_DMA32,
-+	IS_UNDEFINED	= 0,
-+	IS_WC		= 1 << 1,
-+	IS_UC		= 1 << 2,
-+	IS_CACHED	= 1 << 3,
-+	IS_DMA32	= 1 << 4,
-+	IS_HUGE		= 1 << 5
- };
-+
- /*
-- * The pool structure. There are usually six pools:
-+ * The pool structure. There are up to nine pools:
-  *  - generic (not restricted to DMA32):
-  *      - write combined, uncached, cached.
-  *  - dma32 (up to 2^32 - so up 4GB):
-  *      - write combined, uncached, cached.
-+ *  - huge (not restricted to DMA32):
-+ *      - write combined, uncached, cached.
-  * for each 'struct device'. The 'cached' is for pages that are actively used.
-  * The other ones can be shrunk by the shrinker API if neccessary.
-  * @pools: The 'struct device->dma_pools' link.
-  * @type: Type of the pool
-- * @lock: Protects the inuse_list and free_list from concurrnet access. Must be
-+ * @lock: Protects the free_list from concurrnet access. Must be
-  * used with irqsave/irqrestore variants because pool allocator maybe called
-  * from delayed work.
-- * @inuse_list: Pool of pages that are in use. The order is very important and
-- *   it is in the order that the TTM pages that are put back are in.
-  * @free_list: Pool of pages that are free to be used. No order requirements.
-  * @dev: The device that is associated with these pools.
-  * @size: Size used during DMA allocation.
-@@ -107,7 +102,6 @@ struct dma_pool {
- 	struct list_head pools; /* The 'struct device->dma_pools link */
- 	enum pool_type type;
- 	spinlock_t lock;
--	struct list_head inuse_list;
- 	struct list_head free_list;
- 	struct device *dev;
- 	unsigned size;
-@@ -124,13 +118,14 @@ struct dma_pool {
-  * The accounting page keeping track of the allocated page along with
-  * the DMA address.
-  * @page_list: The link to the 'page_list' in 'struct dma_pool'.
-- * @vaddr: The virtual address of the page
-+ * @vaddr: The virtual address of the page and a flag if the page belongs to a
-+ * huge pool
-  * @dma: The bus address of the page. If the page is not allocated
-  *   via the DMA API, it will be -1.
-  */
- struct dma_page {
- 	struct list_head page_list;
--	void *vaddr;
-+	unsigned long vaddr;
- 	struct page *p;
- 	dma_addr_t dma;
- };
-@@ -329,7 +324,8 @@ static int ttm_set_pages_caching(struct
- static void __ttm_dma_free_page(struct dma_pool *pool, struct dma_page *d_page)
- {
- 	dma_addr_t dma = d_page->dma;
--	dma_free_coherent(pool->dev, pool->size, d_page->vaddr, dma);
-+	d_page->vaddr &= ~VADDR_FLAG_HUGE_POOL;
-+	dma_free_coherent(pool->dev, pool->size, (void *)d_page->vaddr, dma);
- 
- 	kfree(d_page);
- 	d_page = NULL;
-@@ -337,19 +333,22 @@ static void __ttm_dma_free_page(struct d
- static struct dma_page *__ttm_dma_alloc_page(struct dma_pool *pool)
- {
- 	struct dma_page *d_page;
-+	void *vaddr;
- 
- 	d_page = kmalloc(sizeof(struct dma_page), GFP_KERNEL);
- 	if (!d_page)
- 		return NULL;
- 
--	d_page->vaddr = dma_alloc_coherent(pool->dev, pool->size,
--					   &d_page->dma,
--					   pool->gfp_flags);
--	if (d_page->vaddr) {
--		if (is_vmalloc_addr(d_page->vaddr))
--			d_page->p = vmalloc_to_page(d_page->vaddr);
-+	vaddr = dma_alloc_coherent(pool->dev, pool->size, &d_page->dma,
-+				   pool->gfp_flags);
-+	if (vaddr) {
-+		if (is_vmalloc_addr(vaddr))
-+			d_page->p = vmalloc_to_page(vaddr);
- 		else
--			d_page->p = virt_to_page(d_page->vaddr);
-+			d_page->p = virt_to_page(vaddr);
-+		d_page->vaddr = (unsigned long)vaddr;
-+		if (pool->type & IS_HUGE)
-+			d_page->vaddr |= VADDR_FLAG_HUGE_POOL;
- 	} else {
- 		kfree(d_page);
- 		d_page = NULL;
-@@ -381,11 +380,40 @@ static void ttm_pool_update_free_locked(
- }
- 
- /* set memory back to wb and free the pages. */
-+static void ttm_dma_page_put(struct dma_pool *pool, struct dma_page *d_page)
-+{
-+	struct page *page = d_page->p;
-+	unsigned i, num_pages;
-+	int ret;
-+
-+	/* Don't set WB on WB page pool. */
-+	if (!(pool->type & IS_CACHED)) {
-+		num_pages = pool->size / PAGE_SIZE;
-+		for (i = 0; i < num_pages; ++i, ++page) {
-+			ret = set_pages_array_wb(&page, 1);
-+			if (ret) {
-+				pr_err("%s: Failed to set %d pages to wb!\n",
-+				       pool->dev_name, 1);
-+			}
-+		}
-+	}
-+
-+	list_del(&d_page->page_list);
-+	__ttm_dma_free_page(pool, d_page);
-+}
-+
- static void ttm_dma_pages_put(struct dma_pool *pool, struct list_head *d_pages,
- 			      struct page *pages[], unsigned npages)
- {
- 	struct dma_page *d_page, *tmp;
- 
-+	if (pool->type & IS_HUGE) {
-+		list_for_each_entry_safe(d_page, tmp, d_pages, page_list)
-+			ttm_dma_page_put(pool, d_page);
-+
-+		return;
-+	}
-+
- 	/* Don't set WB on WB page pool. */
- 	if (npages && !(pool->type & IS_CACHED) &&
- 	    set_pages_array_wb(pages, npages))
-@@ -398,17 +426,6 @@ static void ttm_dma_pages_put(struct dma
- 	}
- }
- 
--static void ttm_dma_page_put(struct dma_pool *pool, struct dma_page *d_page)
--{
--	/* Don't set WB on WB page pool. */
--	if (!(pool->type & IS_CACHED) && set_pages_array_wb(&d_page->p, 1))
--		pr_err("%s: Failed to set %d pages to wb!\n",
--		       pool->dev_name, 1);
--
--	list_del(&d_page->page_list);
--	__ttm_dma_free_page(pool, d_page);
--}
--
- /*
-  * Free pages from pool.
-  *
-@@ -446,7 +463,7 @@ static unsigned ttm_dma_page_pool_free(s
- 					GFP_KERNEL);
- 
- 	if (!pages_to_free) {
--		pr_err("%s: Failed to allocate memory for pool free operation\n",
-+		pr_debug("%s: Failed to allocate memory for pool free operation\n",
- 		       pool->dev_name);
- 		return 0;
- 	}
-@@ -577,8 +594,8 @@ static int ttm_dma_pool_match(struct dev
- static struct dma_pool *ttm_dma_pool_init(struct device *dev, gfp_t flags,
- 					  enum pool_type type)
- {
--	char *n[] = {"wc", "uc", "cached", " dma32", "unknown",};
--	enum pool_type t[] = {IS_WC, IS_UC, IS_CACHED, IS_DMA32, IS_UNDEFINED};
-+	const char *n[] = {"wc", "uc", "cached", " dma32", "huge"};
-+	enum pool_type t[] = {IS_WC, IS_UC, IS_CACHED, IS_DMA32, IS_HUGE};
- 	struct device_pools *sec_pool = NULL;
- 	struct dma_pool *pool = NULL, **ptr;
- 	unsigned i;
-@@ -609,18 +626,24 @@ static struct dma_pool *ttm_dma_pool_ini
- 	sec_pool->pool =  pool;
- 
- 	INIT_LIST_HEAD(&pool->free_list);
--	INIT_LIST_HEAD(&pool->inuse_list);
- 	INIT_LIST_HEAD(&pool->pools);
- 	spin_lock_init(&pool->lock);
- 	pool->dev = dev;
- 	pool->npages_free = pool->npages_in_use = 0;
- 	pool->nfrees = 0;
- 	pool->gfp_flags = flags;
--	pool->size = PAGE_SIZE;
-+	if (type & IS_HUGE)
-+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
-+		pool->size = HPAGE_PMD_SIZE;
-+#else
-+		BUG();
-+#endif
-+	else
-+		pool->size = PAGE_SIZE;
- 	pool->type = type;
- 	pool->nrefills = 0;
- 	p = pool->name;
--	for (i = 0; i < 5; i++) {
-+	for (i = 0; i < ARRAY_SIZE(t); i++) {
- 		if (type & t[i]) {
- 			p += snprintf(p, sizeof(pool->name) - (p - pool->name),
- 				      "%s", n[i]);
-@@ -724,7 +747,7 @@ static int ttm_dma_pool_alloc_new_pages(
- 	struct dma_page *dma_p;
- 	struct page *p;
- 	int r = 0;
--	unsigned i, cpages;
-+	unsigned i, j, npages, cpages;
- 	unsigned max_cpages = min(count,
- 			(unsigned)(PAGE_SIZE/sizeof(struct page *)));
- 
-@@ -732,7 +755,7 @@ static int ttm_dma_pool_alloc_new_pages(
- 	caching_array = kmalloc(max_cpages*sizeof(struct page *), GFP_KERNEL);
- 
- 	if (!caching_array) {
--		pr_err("%s: Unable to allocate table for new pages\n",
-+		pr_debug("%s: Unable to allocate table for new pages\n",
- 		       pool->dev_name);
- 		return -ENOMEM;
- 	}
-@@ -745,8 +768,8 @@ static int ttm_dma_pool_alloc_new_pages(
- 	for (i = 0, cpages = 0; i < count; ++i) {
- 		dma_p = __ttm_dma_alloc_page(pool);
- 		if (!dma_p) {
--			pr_err("%s: Unable to get page %u\n",
--			       pool->dev_name, i);
-+			pr_debug("%s: Unable to get page %u\n",
-+				 pool->dev_name, i);
- 
- 			/* store already allocated pages in the pool after
- 			 * setting the caching state */
-@@ -762,28 +785,32 @@ static int ttm_dma_pool_alloc_new_pages(
- 			goto out;
- 		}
- 		p = dma_p->p;
-+		list_add(&dma_p->page_list, d_pages);
-+
- #ifdef CONFIG_HIGHMEM
- 		/* gfp flags of highmem page should never be dma32 so we
- 		 * we should be fine in such case
- 		 */
--		if (!PageHighMem(p))
-+		if (PageHighMem(p))
-+			continue;
- #endif
--		{
--			caching_array[cpages++] = p;
-+
-+		npages = pool->size / PAGE_SIZE;
-+		for (j = 0; j < npages; ++j) {
-+			caching_array[cpages++] = p + j;
- 			if (cpages == max_cpages) {
- 				/* Note: Cannot hold the spinlock */
- 				r = ttm_set_pages_caching(pool, caching_array,
--						 cpages);
-+							  cpages);
- 				if (r) {
- 					ttm_dma_handle_caching_state_failure(
--						pool, d_pages, caching_array,
--						cpages);
-+					     pool, d_pages, caching_array,
-+					     cpages);
- 					goto out;
- 				}
- 				cpages = 0;
- 			}
- 		}
--		list_add(&dma_p->page_list, d_pages);
- 	}
- 
- 	if (cpages) {
-@@ -828,8 +855,8 @@ static int ttm_dma_page_pool_fill_locked
- 			struct dma_page *d_page;
- 			unsigned cpages = 0;
- 
--			pr_err("%s: Failed to fill %s pool (r:%d)!\n",
--			       pool->dev_name, pool->name, r);
-+			pr_debug("%s: Failed to fill %s pool (r:%d)!\n",
-+				 pool->dev_name, pool->name, r);
- 
- 			list_for_each_entry(d_page, &d_pages, page_list) {
- 				cpages++;
-@@ -871,6 +898,27 @@ static int ttm_dma_pool_get_pages(struct
- 	return r;
- }
- 
-+static gfp_t ttm_dma_pool_gfp_flags(struct ttm_dma_tt *ttm_dma, bool huge)
-+{
-+	struct ttm_tt *ttm = &ttm_dma->ttm;
-+	gfp_t gfp_flags;
-+
-+	if (ttm->page_flags & TTM_PAGE_FLAG_DMA32)
-+		gfp_flags = GFP_USER | GFP_DMA32;
-+	else
-+		gfp_flags = GFP_HIGHUSER;
-+	if (ttm->page_flags & TTM_PAGE_FLAG_ZERO_ALLOC)
-+		gfp_flags |= __GFP_ZERO;
-+
-+	if (huge) {
-+		gfp_flags |= GFP_TRANSHUGE;
-+		gfp_flags &= ~__GFP_MOVABLE;
-+		gfp_flags &= ~__GFP_COMP;
-+	}
-+
-+	return gfp_flags;
-+}
-+
- /*
-  * On success pages list will hold count number of correctly
-  * cached pages. On failure will hold the negative return value (-ENOMEM, etc).
-@@ -879,33 +927,70 @@ int ttm_dma_populate(struct ttm_dma_tt *
- {
- 	struct ttm_tt *ttm = &ttm_dma->ttm;
- 	struct ttm_mem_global *mem_glob = ttm->glob->mem_glob;
-+	unsigned long num_pages = ttm->num_pages;
- 	struct dma_pool *pool;
- 	enum pool_type type;
- 	unsigned i;
--	gfp_t gfp_flags;
- 	int ret;
- 
- 	if (ttm->state != tt_unpopulated)
- 		return 0;
- 
-+	INIT_LIST_HEAD(&ttm_dma->pages_list);
-+	i = 0;
-+
- 	type = ttm_to_type(ttm->page_flags, ttm->caching_state);
-+
-+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
- 	if (ttm->page_flags & TTM_PAGE_FLAG_DMA32)
--		gfp_flags = GFP_USER | GFP_DMA32;
--	else
--		gfp_flags = GFP_HIGHUSER;
--	if (ttm->page_flags & TTM_PAGE_FLAG_ZERO_ALLOC)
--		gfp_flags |= __GFP_ZERO;
-+		goto skip_huge;
-+
-+	pool = ttm_dma_find_pool(dev, type | IS_HUGE);
-+	if (!pool) {
-+		gfp_t gfp_flags = ttm_dma_pool_gfp_flags(ttm_dma, true);
-+
-+		pool = ttm_dma_pool_init(dev, gfp_flags, type | IS_HUGE);
-+		if (IS_ERR_OR_NULL(pool))
-+			goto skip_huge;
-+	}
-+
-+	while (num_pages >= HPAGE_PMD_NR) {
-+		unsigned j;
-+
-+		ret = ttm_dma_pool_get_pages(pool, ttm_dma, i);
-+		if (ret != 0)
-+			break;
-+
-+		ret = ttm_mem_global_alloc_page(mem_glob, ttm->pages[i],
-+						pool->size);
-+		if (unlikely(ret != 0)) {
-+			ttm_dma_unpopulate(ttm_dma, dev);
-+			return -ENOMEM;
-+		}
-+
-+		for (j = i + 1; j < (i + HPAGE_PMD_NR); ++j) {
-+			ttm->pages[j] = ttm->pages[j - 1] + 1;
-+			ttm_dma->dma_address[j] = ttm_dma->dma_address[j - 1] +
-+				PAGE_SIZE;
-+		}
-+
-+		i += HPAGE_PMD_NR;
-+		num_pages -= HPAGE_PMD_NR;
-+	}
-+
-+skip_huge:
-+#endif
- 
- 	pool = ttm_dma_find_pool(dev, type);
- 	if (!pool) {
-+		gfp_t gfp_flags = ttm_dma_pool_gfp_flags(ttm_dma, false);
-+
- 		pool = ttm_dma_pool_init(dev, gfp_flags, type);
--		if (IS_ERR_OR_NULL(pool)) {
-+		if (IS_ERR_OR_NULL(pool))
- 			return -ENOMEM;
--		}
- 	}
- 
--	INIT_LIST_HEAD(&ttm_dma->pages_list);
--	for (i = 0; i < ttm->num_pages; ++i) {
-+	while (num_pages) {
- 		ret = ttm_dma_pool_get_pages(pool, ttm_dma, i);
- 		if (ret != 0) {
- 			ttm_dma_unpopulate(ttm_dma, dev);
-@@ -913,11 +998,14 @@ int ttm_dma_populate(struct ttm_dma_tt *
- 		}
- 
- 		ret = ttm_mem_global_alloc_page(mem_glob, ttm->pages[i],
--						false, false);
-+						pool->size);
- 		if (unlikely(ret != 0)) {
- 			ttm_dma_unpopulate(ttm_dma, dev);
- 			return -ENOMEM;
- 		}
-+
-+		++i;
-+		--num_pages;
- 	}
- 
- 	if (unlikely(ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)) {
-@@ -941,10 +1029,33 @@ void ttm_dma_unpopulate(struct ttm_dma_t
- 	struct dma_page *d_page, *next;
- 	enum pool_type type;
- 	bool is_cached = false;
--	unsigned count = 0, i, npages = 0;
-+	unsigned count, i, npages = 0;
- 	unsigned long irq_flags;
- 
- 	type = ttm_to_type(ttm->page_flags, ttm->caching_state);
-+
-+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
-+	pool = ttm_dma_find_pool(dev, type | IS_HUGE);
-+	if (pool) {
-+		count = 0;
-+		list_for_each_entry_safe(d_page, next, &ttm_dma->pages_list,
-+					 page_list) {
-+			if (!(d_page->vaddr & VADDR_FLAG_HUGE_POOL))
-+				continue;
-+
-+			count++;
-+			ttm_mem_global_free_page(ttm->glob->mem_glob,
-+						 d_page->p, pool->size);
-+			ttm_dma_page_put(pool, d_page);
-+		}
-+
-+		spin_lock_irqsave(&pool->lock, irq_flags);
-+		pool->npages_in_use -= count;
-+		pool->nfrees += count;
-+		spin_unlock_irqrestore(&pool->lock, irq_flags);
-+	}
-+#endif
-+
- 	pool = ttm_dma_find_pool(dev, type);
- 	if (!pool)
- 		return;
-@@ -953,6 +1064,7 @@ void ttm_dma_unpopulate(struct ttm_dma_t
- 		     ttm_to_type(ttm->page_flags, tt_cached)) == pool);
- 
- 	/* make sure pages array match list and count number of pages */
-+	count = 0;
- 	list_for_each_entry(d_page, &ttm_dma->pages_list, page_list) {
- 		ttm->pages[count] = d_page->p;
- 		count++;
-@@ -978,13 +1090,13 @@ void ttm_dma_unpopulate(struct ttm_dma_t
- 	if (is_cached) {
- 		list_for_each_entry_safe(d_page, next, &ttm_dma->pages_list, page_list) {
- 			ttm_mem_global_free_page(ttm->glob->mem_glob,
--						 d_page->p);
-+						 d_page->p, pool->size);
- 			ttm_dma_page_put(pool, d_page);
- 		}
- 	} else {
- 		for (i = 0; i < count; i++) {
- 			ttm_mem_global_free_page(ttm->glob->mem_glob,
--						 ttm->pages[i]);
-+						 ttm->pages[i], pool->size);
- 		}
- 	}
- 
---- linux-4.14/drivers/gpu/drm/tve200/Kconfig.0130~	2017-12-14 06:39:58.525903644 +0100
-+++ linux-4.14/drivers/gpu/drm/tve200/Kconfig	2017-12-14 06:39:58.525903644 +0100
-@@ -0,0 +1,16 @@
-+config DRM_TVE200
-+	tristate "DRM Support for Faraday TV Encoder TVE200"
-+	depends on DRM
-+	depends on CMA
-+	depends on ARM || COMPILE_TEST
-+	depends on OF
-+	select DRM_BRIDGE
-+	select DRM_PANEL_BRIDGE
-+	select DRM_KMS_HELPER
-+	select DRM_KMS_CMA_HELPER
-+	select DRM_GEM_CMA_HELPER
-+	select VT_HW_CONSOLE_BINDING if FRAMEBUFFER_CONSOLE
-+	help
-+	  Choose this option for DRM support for the Faraday TV Encoder
-+	  TVE200 Controller.
-+	  If M is selected the module will be called tve200_drm.
---- linux-4.14/drivers/gpu/drm/tve200/Makefile.0130~	2017-12-14 06:39:58.525903644 +0100
-+++ linux-4.14/drivers/gpu/drm/tve200/Makefile	2017-12-14 06:39:58.525903644 +0100
-@@ -0,0 +1,4 @@
-+tve200_drm-y +=	tve200_display.o \
-+		tve200_drv.o
-+
-+obj-$(CONFIG_DRM_TVE200) += tve200_drm.o
---- linux-4.14/drivers/gpu/drm/tve200/tve200_display.c.0130~	2017-12-14 06:39:58.525903644 +0100
-+++ linux-4.14/drivers/gpu/drm/tve200/tve200_display.c	2017-12-14 06:39:58.525903644 +0100
-@@ -0,0 +1,338 @@
-+/*
-+ * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
-+ * Parts of this file were based on sources as follows:
-+ *
-+ * Copyright (C) 2006-2008 Intel Corporation
-+ * Copyright (C) 2007 Amos Lee <amos_lee@storlinksemi.com>
-+ * Copyright (C) 2007 Dave Airlie <airlied@linux.ie>
-+ * Copyright (C) 2011 Texas Instruments
-+ * Copyright (C) 2017 Eric Anholt
-+ *
-+ * This program is free software and is provided to you under the terms of the
-+ * GNU General Public License version 2 as published by the Free Software
-+ * Foundation, and any use by you of this program is subject to the terms of
-+ * such GNU licence.
-+ */
-+#include <linux/clk.h>
-+#include <linux/version.h>
-+#include <linux/dma-buf.h>
-+#include <linux/of_graph.h>
-+
-+#include <drm/drmP.h>
-+#include <drm/drm_panel.h>
-+#include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
-+#include <drm/drm_fb_cma_helper.h>
-+
-+#include "tve200_drm.h"
-+
-+irqreturn_t tve200_irq(int irq, void *data)
-+{
-+	struct tve200_drm_dev_private *priv = data;
-+	u32 stat;
-+	u32 val;
-+
-+	stat = readl(priv->regs + TVE200_INT_STAT);
-+
-+	if (!stat)
-+		return IRQ_NONE;
-+
-+	/*
-+	 * Vblank IRQ
-+	 *
-+	 * The hardware is a bit tilted: the line stays high after clearing
-+	 * the vblank IRQ, firing many more interrupts. We counter this
-+	 * by toggling the IRQ back and forth from firing at vblank and
-+	 * firing at start of active image, which works around the problem
-+	 * since those occur strictly in sequence, and we get two IRQs for each
-+	 * frame, one at start of Vblank (that we make call into the CRTC) and
-+	 * another one at the start of the image (that we discard).
-+	 */
-+	if (stat & TVE200_INT_V_STATUS) {
-+		val = readl(priv->regs + TVE200_CTRL);
-+		/* We have an actual start of vsync */
-+		if (!(val & TVE200_VSTSTYPE_BITS)) {
-+			drm_crtc_handle_vblank(&priv->pipe.crtc);
-+			/* Toggle trigger to start of active image */
-+			val |= TVE200_VSTSTYPE_VAI;
-+		} else {
-+			/* Toggle trigger back to start of vsync */
-+			val &= ~TVE200_VSTSTYPE_BITS;
-+		}
-+		writel(val, priv->regs + TVE200_CTRL);
-+	} else
-+		dev_err(priv->drm->dev, "stray IRQ %08x\n", stat);
-+
-+	/* Clear the interrupt once done */
-+	writel(stat, priv->regs + TVE200_INT_CLR);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int tve200_display_check(struct drm_simple_display_pipe *pipe,
-+			       struct drm_plane_state *pstate,
-+			       struct drm_crtc_state *cstate)
-+{
-+	const struct drm_display_mode *mode = &cstate->mode;
-+	struct drm_framebuffer *old_fb = pipe->plane.state->fb;
-+	struct drm_framebuffer *fb = pstate->fb;
-+
-+	/*
-+	 * We support these specific resolutions and nothing else.
-+	 */
-+	if (!(mode->hdisplay == 352 && mode->vdisplay == 240) && /* SIF(525) */
-+	    !(mode->hdisplay == 352 && mode->vdisplay == 288) && /* CIF(625) */
-+	    !(mode->hdisplay == 640 && mode->vdisplay == 480) && /* VGA */
-+	    !(mode->hdisplay == 720 && mode->vdisplay == 480) && /* D1 */
-+	    !(mode->hdisplay == 720 && mode->vdisplay == 576)) { /* D1 */
-+		DRM_DEBUG_KMS("unsupported display mode (%u x %u)\n",
-+			mode->hdisplay, mode->vdisplay);
-+		return -EINVAL;
-+	}
-+
-+	if (fb) {
-+		u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0);
-+
-+		/* FB base address must be dword aligned. */
-+		if (offset & 3) {
-+			DRM_DEBUG_KMS("FB not 32-bit aligned\n");
-+			return -EINVAL;
-+		}
-+
-+		/*
-+		 * There's no pitch register, the mode's hdisplay
-+		 * controls this.
-+		 */
-+		if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) {
-+			DRM_DEBUG_KMS("can't handle pitches\n");
-+			return -EINVAL;
-+		}
-+
-+		/*
-+		 * We can't change the FB format in a flicker-free
-+		 * manner (and only update it during CRTC enable).
-+		 */
-+		if (old_fb && old_fb->format != fb->format)
-+			cstate->mode_changed = true;
-+	}
-+
-+	return 0;
-+}
-+
-+static void tve200_display_enable(struct drm_simple_display_pipe *pipe,
-+				 struct drm_crtc_state *cstate)
-+{
-+	struct drm_crtc *crtc = &pipe->crtc;
-+	struct drm_plane *plane = &pipe->plane;
-+	struct drm_device *drm = crtc->dev;
-+	struct tve200_drm_dev_private *priv = drm->dev_private;
-+	const struct drm_display_mode *mode = &cstate->mode;
-+	struct drm_framebuffer *fb = plane->state->fb;
-+	struct drm_connector *connector = priv->connector;
-+	u32 format = fb->format->format;
-+	u32 ctrl1 = 0;
-+
-+	clk_prepare_enable(priv->clk);
-+
-+	/* Function 1 */
-+	ctrl1 |= TVE200_CTRL_CSMODE;
-+	/* Interlace mode for CCIR656: parameterize? */
-+	ctrl1 |= TVE200_CTRL_NONINTERLACE;
-+	/* 32 words per burst */
-+	ctrl1 |= TVE200_CTRL_BURST_32_WORDS;
-+	/* 16 retries */
-+	ctrl1 |= TVE200_CTRL_RETRYCNT_16;
-+	/* NTSC mode: parametrize? */
-+	ctrl1 |= TVE200_CTRL_NTSC;
-+
-+	/* Vsync IRQ at start of Vsync at first */
-+	ctrl1 |= TVE200_VSTSTYPE_VSYNC;
-+
-+	if (connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
-+		ctrl1 |= TVE200_CTRL_TVCLKP;
-+
-+	if ((mode->hdisplay == 352 && mode->vdisplay == 240) || /* SIF(525) */
-+	    (mode->hdisplay == 352 && mode->vdisplay == 288)) { /* CIF(625) */
-+		ctrl1 |= TVE200_CTRL_IPRESOL_CIF;
-+		dev_info(drm->dev, "CIF mode\n");
-+	} else if (mode->hdisplay == 640 && mode->vdisplay == 480) {
-+		ctrl1 |= TVE200_CTRL_IPRESOL_VGA;
-+		dev_info(drm->dev, "VGA mode\n");
-+	} else if ((mode->hdisplay == 720 && mode->vdisplay == 480) ||
-+		   (mode->hdisplay == 720 && mode->vdisplay == 576)) {
-+		ctrl1 |= TVE200_CTRL_IPRESOL_D1;
-+		dev_info(drm->dev, "D1 mode\n");
-+	}
-+
-+	if (format & DRM_FORMAT_BIG_ENDIAN) {
-+		ctrl1 |= TVE200_CTRL_BBBP;
-+		format &= ~DRM_FORMAT_BIG_ENDIAN;
-+	}
-+
-+	switch (format) {
-+	case DRM_FORMAT_XRGB8888:
-+		ctrl1 |= TVE200_IPDMOD_RGB888;
-+		break;
-+	case DRM_FORMAT_RGB565:
-+		ctrl1 |= TVE200_IPDMOD_RGB565;
-+		break;
-+	case DRM_FORMAT_XRGB1555:
-+		ctrl1 |= TVE200_IPDMOD_RGB555;
-+		break;
-+	case DRM_FORMAT_XBGR8888:
-+		ctrl1 |= TVE200_IPDMOD_RGB888 | TVE200_BGR;
-+		break;
-+	case DRM_FORMAT_BGR565:
-+		ctrl1 |= TVE200_IPDMOD_RGB565 | TVE200_BGR;
-+		break;
-+	case DRM_FORMAT_XBGR1555:
-+		ctrl1 |= TVE200_IPDMOD_RGB555 | TVE200_BGR;
-+		break;
-+	case DRM_FORMAT_YUYV:
-+		ctrl1 |= TVE200_IPDMOD_YUV422;
-+		ctrl1 |= TVE200_CTRL_YCBCRODR_CR0Y1CB0Y0;
-+		break;
-+	case DRM_FORMAT_YVYU:
-+		ctrl1 |= TVE200_IPDMOD_YUV422;
-+		ctrl1 |= TVE200_CTRL_YCBCRODR_CB0Y1CR0Y0;
-+		break;
-+	case DRM_FORMAT_UYVY:
-+		ctrl1 |= TVE200_IPDMOD_YUV422;
-+		ctrl1 |= TVE200_CTRL_YCBCRODR_Y1CR0Y0CB0;
-+		break;
-+	case DRM_FORMAT_VYUY:
-+		ctrl1 |= TVE200_IPDMOD_YUV422;
-+		ctrl1 |= TVE200_CTRL_YCBCRODR_Y1CB0Y0CR0;
-+		break;
-+	case DRM_FORMAT_YUV420:
-+		ctrl1 |= TVE200_CTRL_YUV420;
-+		ctrl1 |= TVE200_IPDMOD_YUV420;
-+		break;
-+	default:
-+		dev_err(drm->dev, "Unknown FB format 0x%08x\n",
-+			fb->format->format);
-+		break;
-+	}
-+
-+	ctrl1 |= TVE200_TVEEN;
-+
-+	/* Turn it on */
-+	writel(ctrl1, priv->regs + TVE200_CTRL);
-+
-+	drm_crtc_vblank_on(crtc);
-+}
-+
-+static void tve200_display_disable(struct drm_simple_display_pipe *pipe)
-+{
-+	struct drm_crtc *crtc = &pipe->crtc;
-+	struct drm_device *drm = crtc->dev;
-+	struct tve200_drm_dev_private *priv = drm->dev_private;
-+
-+	drm_crtc_vblank_off(crtc);
-+
-+	/* Disable and Power Down */
-+	writel(0, priv->regs + TVE200_CTRL);
-+
-+	clk_disable_unprepare(priv->clk);
-+}
-+
-+static void tve200_display_update(struct drm_simple_display_pipe *pipe,
-+				 struct drm_plane_state *old_pstate)
-+{
-+	struct drm_crtc *crtc = &pipe->crtc;
-+	struct drm_device *drm = crtc->dev;
-+	struct tve200_drm_dev_private *priv = drm->dev_private;
-+	struct drm_pending_vblank_event *event = crtc->state->event;
-+	struct drm_plane *plane = &pipe->plane;
-+	struct drm_plane_state *pstate = plane->state;
-+	struct drm_framebuffer *fb = pstate->fb;
-+
-+	if (fb) {
-+		/* For RGB, the Y component is used as base address */
-+		writel(drm_fb_cma_get_gem_addr(fb, pstate, 0),
-+		       priv->regs + TVE200_Y_FRAME_BASE_ADDR);
-+
-+		/* For three plane YUV we need two more addresses */
-+		if (fb->format->format == DRM_FORMAT_YUV420) {
-+			writel(drm_fb_cma_get_gem_addr(fb, pstate, 1),
-+			       priv->regs + TVE200_U_FRAME_BASE_ADDR);
-+			writel(drm_fb_cma_get_gem_addr(fb, pstate, 2),
-+			       priv->regs + TVE200_V_FRAME_BASE_ADDR);
-+		}
-+	}
-+
-+	if (event) {
-+		crtc->state->event = NULL;
-+
-+		spin_lock_irq(&crtc->dev->event_lock);
-+		if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0)
-+			drm_crtc_arm_vblank_event(crtc, event);
-+		else
-+			drm_crtc_send_vblank_event(crtc, event);
-+		spin_unlock_irq(&crtc->dev->event_lock);
-+	}
-+}
-+
-+int tve200_enable_vblank(struct drm_device *drm, unsigned int crtc)
-+{
-+	struct tve200_drm_dev_private *priv = drm->dev_private;
-+
-+	writel(TVE200_INT_V_STATUS, priv->regs + TVE200_INT_EN);
-+	return 0;
-+}
-+
-+void tve200_disable_vblank(struct drm_device *drm, unsigned int crtc)
-+{
-+	struct tve200_drm_dev_private *priv = drm->dev_private;
-+
-+	writel(0, priv->regs + TVE200_INT_EN);
-+}
-+
-+static int tve200_display_prepare_fb(struct drm_simple_display_pipe *pipe,
-+				    struct drm_plane_state *plane_state)
-+{
-+	return drm_gem_fb_prepare_fb(&pipe->plane, plane_state);
-+}
-+
-+static const struct drm_simple_display_pipe_funcs tve200_display_funcs = {
-+	.check = tve200_display_check,
-+	.enable = tve200_display_enable,
-+	.disable = tve200_display_disable,
-+	.update = tve200_display_update,
-+	.prepare_fb = tve200_display_prepare_fb,
-+};
-+
-+int tve200_display_init(struct drm_device *drm)
-+{
-+	struct tve200_drm_dev_private *priv = drm->dev_private;
-+	int ret;
-+	static const u32 formats[] = {
-+		DRM_FORMAT_XRGB8888,
-+		DRM_FORMAT_XBGR8888,
-+		DRM_FORMAT_RGB565,
-+		DRM_FORMAT_BGR565,
-+		DRM_FORMAT_XRGB1555,
-+		DRM_FORMAT_XBGR1555,
-+		/*
-+		 * The controller actually supports any YCbCr ordering,
-+		 * for packed YCbCr. This just lists the orderings that
-+		 * DRM supports.
-+		 */
-+		DRM_FORMAT_YUYV,
-+		DRM_FORMAT_YVYU,
-+		DRM_FORMAT_UYVY,
-+		DRM_FORMAT_VYUY,
-+		/* This uses three planes */
-+		DRM_FORMAT_YUV420,
-+	};
-+
-+	ret = drm_simple_display_pipe_init(drm, &priv->pipe,
-+					   &tve200_display_funcs,
-+					   formats, ARRAY_SIZE(formats),
-+					   NULL,
-+					   priv->connector);
-+	if (ret)
-+		return ret;
-+
-+	return 0;
-+}
---- linux-4.14/drivers/gpu/drm/tve200/tve200_drm.h.0130~	2017-12-14 06:39:58.525903644 +0100
-+++ linux-4.14/drivers/gpu/drm/tve200/tve200_drm.h	2017-12-14 06:39:58.525903644 +0100
-@@ -0,0 +1,126 @@
-+/*
-+ * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
-+ * Parts of this file were based on sources as follows:
-+ *
-+ * Copyright (C) 2006-2008 Intel Corporation
-+ * Copyright (C) 2007 Amos Lee <amos_lee@storlinksemi.com>
-+ * Copyright (C) 2007 Dave Airlie <airlied@linux.ie>
-+ * Copyright (C) 2011 Texas Instruments
-+ * Copyright (C) 2017 Eric Anholt
-+ *
-+ * This program is free software and is provided to you under the terms of the
-+ * GNU General Public License version 2 as published by the Free Software
-+ * Foundation, and any use by you of this program is subject to the terms of
-+ * such GNU licence.
-+ */
-+
-+#ifndef _TVE200_DRM_H_
-+#define _TVE200_DRM_H_
-+
-+/* Bits 2-31 are valid physical base addresses */
-+#define TVE200_Y_FRAME_BASE_ADDR	0x00
-+#define TVE200_U_FRAME_BASE_ADDR	0x04
-+#define TVE200_V_FRAME_BASE_ADDR	0x08
-+
-+#define TVE200_INT_EN			0x0C
-+#define TVE200_INT_CLR			0x10
-+#define TVE200_INT_STAT			0x14
-+#define TVE200_INT_BUS_ERR		BIT(7)
-+#define TVE200_INT_V_STATUS		BIT(6) /* vertical blank */
-+#define TVE200_INT_V_NEXT_FRAME		BIT(5)
-+#define TVE200_INT_U_NEXT_FRAME		BIT(4)
-+#define TVE200_INT_Y_NEXT_FRAME		BIT(3)
-+#define TVE200_INT_V_FIFO_UNDERRUN	BIT(2)
-+#define TVE200_INT_U_FIFO_UNDERRUN	BIT(1)
-+#define TVE200_INT_Y_FIFO_UNDERRUN	BIT(0)
-+#define TVE200_FIFO_UNDERRUNS		(TVE200_INT_V_FIFO_UNDERRUN | \
-+					 TVE200_INT_U_FIFO_UNDERRUN | \
-+					 TVE200_INT_Y_FIFO_UNDERRUN)
-+
-+#define TVE200_CTRL			0x18
-+#define TVE200_CTRL_YUV420		BIT(31)
-+#define TVE200_CTRL_CSMODE		BIT(30)
-+#define TVE200_CTRL_NONINTERLACE	BIT(28) /* 0 = non-interlace CCIR656 */
-+#define TVE200_CTRL_TVCLKP		BIT(27) /* Inverted clock phase */
-+/* Bits 24..26 define the burst size after arbitration on the bus */
-+#define TVE200_CTRL_BURST_4_WORDS	(0 << 24)
-+#define TVE200_CTRL_BURST_8_WORDS	(1 << 24)
-+#define TVE200_CTRL_BURST_16_WORDS	(2 << 24)
-+#define TVE200_CTRL_BURST_32_WORDS	(3 << 24)
-+#define TVE200_CTRL_BURST_64_WORDS	(4 << 24)
-+#define TVE200_CTRL_BURST_128_WORDS	(5 << 24)
-+#define TVE200_CTRL_BURST_256_WORDS	(6 << 24)
-+#define TVE200_CTRL_BURST_0_WORDS	(7 << 24) /* ? */
-+/*
-+ * Bits 16..23 is the retry count*16 before issueing a new AHB transfer
-+ * on the AHB bus.
-+ */
-+#define TVE200_CTRL_RETRYCNT_MASK	GENMASK(23, 16)
-+#define TVE200_CTRL_RETRYCNT_16		(1 << 16)
-+#define TVE200_CTRL_BBBP		BIT(15) /* 0 = little-endian */
-+/* Bits 12..14 define the YCbCr ordering */
-+#define TVE200_CTRL_YCBCRODR_CB0Y0CR0Y1	(0 << 12)
-+#define TVE200_CTRL_YCBCRODR_Y0CB0Y1CR0	(1 << 12)
-+#define TVE200_CTRL_YCBCRODR_CR0Y0CB0Y1	(2 << 12)
-+#define TVE200_CTRL_YCBCRODR_Y1CB0Y0CR0	(3 << 12)
-+#define TVE200_CTRL_YCBCRODR_CR0Y1CB0Y0	(4 << 12)
-+#define TVE200_CTRL_YCBCRODR_Y1CR0Y0CB0	(5 << 12)
-+#define TVE200_CTRL_YCBCRODR_CB0Y1CR0Y0	(6 << 12)
-+#define TVE200_CTRL_YCBCRODR_Y0CR0Y1CB0	(7 << 12)
-+/* Bits 10..11 define the input resolution (framebuffer size) */
-+#define TVE200_CTRL_IPRESOL_CIF		(0 << 10)
-+#define TVE200_CTRL_IPRESOL_VGA		(1 << 10)
-+#define TVE200_CTRL_IPRESOL_D1		(2 << 10)
-+#define TVE200_CTRL_NTSC		BIT(9) /* 0 = PAL, 1 = NTSC */
-+#define TVE200_CTRL_INTERLACE		BIT(8) /* 1 = interlace, only for D1 */
-+#define TVE200_IPDMOD_RGB555		(0 << 6) /* TVE200_CTRL_YUV420 = 0 */
-+#define TVE200_IPDMOD_RGB565		(1 << 6)
-+#define TVE200_IPDMOD_RGB888		(2 << 6)
-+#define TVE200_IPDMOD_YUV420		(2 << 6) /* TVE200_CTRL_YUV420 = 1 */
-+#define TVE200_IPDMOD_YUV422		(3 << 6)
-+/* Bits 4 & 5 define when to fire the vblank IRQ */
-+#define TVE200_VSTSTYPE_VSYNC		(0 << 4) /* start of vsync */
-+#define TVE200_VSTSTYPE_VBP		(1 << 4) /* start of v back porch */
-+#define TVE200_VSTSTYPE_VAI		(2 << 4) /* start of v active image */
-+#define TVE200_VSTSTYPE_VFP		(3 << 4) /* start of v front porch */
-+#define TVE200_VSTSTYPE_BITS		(BIT(4) | BIT(5))
-+#define TVE200_BGR			BIT(1) /* 0 = RGB, 1 = BGR */
-+#define TVE200_TVEEN			BIT(0) /* Enable TVE block */
-+
-+#define TVE200_CTRL_2			0x1c
-+#define TVE200_CTRL_3			0x20
-+
-+#define TVE200_CTRL_4			0x24
-+#define TVE200_CTRL_4_RESET		BIT(0) /* triggers reset of TVE200 */
-+
-+#include <drm/drm_gem.h>
-+#include <drm/drm_simple_kms_helper.h>
-+
-+struct tve200_drm_dev_private {
-+	struct drm_device *drm;
-+
-+	struct drm_connector *connector;
-+	struct drm_panel *panel;
-+	struct drm_bridge *bridge;
-+	struct drm_simple_display_pipe pipe;
-+	struct drm_fbdev_cma *fbdev;
-+
-+	void *regs;
-+	struct clk *pclk;
-+	struct clk *clk;
-+};
-+
-+#define to_tve200_connector(x) \
-+	container_of(x, struct tve200_drm_connector, connector)
-+
-+int tve200_display_init(struct drm_device *dev);
-+int tve200_enable_vblank(struct drm_device *drm, unsigned int crtc);
-+void tve200_disable_vblank(struct drm_device *drm, unsigned int crtc);
-+irqreturn_t tve200_irq(int irq, void *data);
-+int tve200_connector_init(struct drm_device *dev);
-+int tve200_encoder_init(struct drm_device *dev);
-+int tve200_dumb_create(struct drm_file *file_priv,
-+		      struct drm_device *dev,
-+		      struct drm_mode_create_dumb *args);
-+
-+#endif /* _TVE200_DRM_H_ */
---- linux-4.14/drivers/gpu/drm/tve200/tve200_drv.c.0130~	2017-12-14 06:39:58.525903644 +0100
-+++ linux-4.14/drivers/gpu/drm/tve200/tve200_drv.c	2017-12-14 06:39:58.525903644 +0100
-@@ -0,0 +1,303 @@
-+/*
-+ * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
-+ * Parts of this file were based on sources as follows:
-+ *
-+ * Copyright (C) 2006-2008 Intel Corporation
-+ * Copyright (C) 2007 Amos Lee <amos_lee@storlinksemi.com>
-+ * Copyright (C) 2007 Dave Airlie <airlied@linux.ie>
-+ * Copyright (C) 2011 Texas Instruments
-+ * Copyright (C) 2017 Eric Anholt
-+ *
-+ * This program is free software and is provided to you under the terms of the
-+ * GNU General Public License version 2 as published by the Free Software
-+ * Foundation, and any use by you of this program is subject to the terms of
-+ * such GNU licence.
-+ */
-+
-+/**
-+ * DOC: Faraday TV Encoder TVE200 DRM Driver
-+ *
-+ * The Faraday TV Encoder TVE200 is also known as the Gemini TV Interface
-+ * Controller (TVC) and is found in the Gemini Chipset from Storlink
-+ * Semiconductor (later Storm Semiconductor, later Cortina Systems)
-+ * but also in the Grain Media GM8180 chipset. On the Gemini the module
-+ * is connected to 8 data lines and a single clock line, comprising an
-+ * 8-bit BT.656 interface.
-+ *
-+ * This is a very basic YUV display driver. The datasheet specifies that
-+ * it supports the ITU BT.656 standard. It requires a 27 MHz clock which is
-+ * the hallmark of any TV encoder supporting both PAL and NTSC.
-+ *
-+ * This driver exposes a standard KMS interface for this TV encoder.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/dma-buf.h>
-+#include <linux/irq.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/shmem_fs.h>
-+#include <linux/slab.h>
-+#include <linux/version.h>
-+
-+#include <drm/drmP.h>
-+#include <drm/drm_atomic_helper.h>
-+#include <drm/drm_crtc_helper.h>
-+#include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
-+#include <drm/drm_fb_cma_helper.h>
-+#include <drm/drm_panel.h>
-+#include <drm/drm_of.h>
-+#include <drm/drm_bridge.h>
-+
-+#include "tve200_drm.h"
-+
-+#define DRIVER_DESC      "DRM module for Faraday TVE200"
-+
-+static const struct drm_mode_config_funcs mode_config_funcs = {
-+	.fb_create = drm_gem_fb_create,
-+	.atomic_check = drm_atomic_helper_check,
-+	.atomic_commit = drm_atomic_helper_commit,
-+};
-+
-+static int tve200_modeset_init(struct drm_device *dev)
-+{
-+	struct drm_mode_config *mode_config;
-+	struct tve200_drm_dev_private *priv = dev->dev_private;
-+	struct drm_panel *panel;
-+	struct drm_bridge *bridge;
-+	int ret = 0;
-+
-+	drm_mode_config_init(dev);
-+	mode_config = &dev->mode_config;
-+	mode_config->funcs = &mode_config_funcs;
-+	mode_config->min_width = 352;
-+	mode_config->max_width = 720;
-+	mode_config->min_height = 240;
-+	mode_config->max_height = 576;
-+
-+	ret = drm_of_find_panel_or_bridge(dev->dev->of_node,
-+					  0, 0, &panel, &bridge);
-+	if (ret && ret != -ENODEV)
-+		return ret;
-+	if (panel) {
-+		bridge = drm_panel_bridge_add(panel,
-+					      DRM_MODE_CONNECTOR_Unknown);
-+		if (IS_ERR(bridge)) {
-+			ret = PTR_ERR(bridge);
-+			goto out_bridge;
-+		}
-+	} else {
-+		/*
-+		 * TODO: when we are using a different bridge than a panel
-+		 * (such as a dumb VGA connector) we need to devise a different
-+		 * method to get the connector out of the bridge.
-+		 */
-+		dev_err(dev->dev, "the bridge is not a panel\n");
-+		goto out_bridge;
-+	}
-+
-+	ret = tve200_display_init(dev);
-+	if (ret) {
-+		dev_err(dev->dev, "failed to init display\n");
-+		goto out_bridge;
-+	}
-+
-+	ret = drm_simple_display_pipe_attach_bridge(&priv->pipe,
-+						    bridge);
-+	if (ret) {
-+		dev_err(dev->dev, "failed to attach bridge\n");
-+		goto out_bridge;
-+	}
-+
-+	priv->panel = panel;
-+	priv->connector = panel->connector;
-+	priv->bridge = bridge;
-+
-+	dev_info(dev->dev, "attached to panel %s\n",
-+		 dev_name(panel->dev));
-+
-+	ret = drm_vblank_init(dev, 1);
-+	if (ret) {
-+		dev_err(dev->dev, "failed to init vblank\n");
-+		goto out_bridge;
-+	}
-+
-+	drm_mode_config_reset(dev);
-+
-+	/*
-+	 * Passing in 16 here will make the RGB656 mode the default
-+	 * Passing in 32 will use XRGB8888 mode
-+	 */
-+	priv->fbdev = drm_fbdev_cma_init(dev, 16,
-+					 dev->mode_config.num_connector);
-+	drm_kms_helper_poll_init(dev);
-+
-+	goto finish;
-+
-+out_bridge:
-+	if (panel)
-+		drm_panel_bridge_remove(bridge);
-+	drm_mode_config_cleanup(dev);
-+finish:
-+	return ret;
-+}
-+
-+DEFINE_DRM_GEM_CMA_FOPS(drm_fops);
-+
-+static void tve200_lastclose(struct drm_device *dev)
-+{
-+	struct tve200_drm_dev_private *priv = dev->dev_private;
-+
-+	drm_fbdev_cma_restore_mode(priv->fbdev);
-+}
-+
-+static struct drm_driver tve200_drm_driver = {
-+	.driver_features =
-+		DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | DRIVER_ATOMIC,
-+	.lastclose = tve200_lastclose,
-+	.ioctls = NULL,
-+	.fops = &drm_fops,
-+	.name = "tve200",
-+	.desc = DRIVER_DESC,
-+	.date = "20170703",
-+	.major = 1,
-+	.minor = 0,
-+	.patchlevel = 0,
-+	.dumb_create = drm_gem_cma_dumb_create,
-+	.gem_free_object_unlocked = drm_gem_cma_free_object,
-+	.gem_vm_ops = &drm_gem_cma_vm_ops,
-+
-+	.enable_vblank = tve200_enable_vblank,
-+	.disable_vblank = tve200_disable_vblank,
-+
-+	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
-+	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
-+	.gem_prime_import = drm_gem_prime_import,
-+	.gem_prime_export = drm_gem_prime_export,
-+	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
-+	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
-+	.gem_prime_vmap = drm_gem_cma_prime_vmap,
-+	.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
-+	.gem_prime_mmap = drm_gem_cma_prime_mmap,
-+};
-+
-+static int tve200_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct tve200_drm_dev_private *priv;
-+	struct drm_device *drm;
-+	struct resource *res;
-+	int irq;
-+	int ret;
-+
-+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	drm = drm_dev_alloc(&tve200_drm_driver, dev);
-+	if (IS_ERR(drm))
-+		return PTR_ERR(drm);
-+	platform_set_drvdata(pdev, drm);
-+	priv->drm = drm;
-+	drm->dev_private = priv;
-+
-+	/* Clock the silicon so we can access the registers */
-+	priv->pclk = devm_clk_get(dev, "PCLK");
-+	if (IS_ERR(priv->pclk)) {
-+		dev_err(dev, "unable to get PCLK\n");
-+		ret = PTR_ERR(priv->pclk);
-+		goto dev_unref;
-+	}
-+	ret = clk_prepare_enable(priv->pclk);
-+	if (ret) {
-+		dev_err(dev, "failed to enable PCLK\n");
-+		goto dev_unref;
-+	}
-+
-+	/* This clock is for the pixels (27MHz) */
-+	priv->clk = devm_clk_get(dev, "TVE");
-+	if (IS_ERR(priv->clk)) {
-+		dev_err(dev, "unable to get TVE clock\n");
-+		ret = PTR_ERR(priv->clk);
-+		goto clk_disable;
-+	}
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	priv->regs = devm_ioremap_resource(dev, res);
-+	if (IS_ERR(priv->regs)) {
-+		dev_err(dev, "%s failed mmio\n", __func__);
-+		ret = -EINVAL;
-+		goto clk_disable;
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (!irq) {
-+		ret = -EINVAL;
-+		goto clk_disable;
-+	}
-+
-+	/* turn off interrupts before requesting the irq */
-+	writel(0, priv->regs + TVE200_INT_EN);
-+
-+	ret = devm_request_irq(dev, irq, tve200_irq, 0, "tve200", priv);
-+	if (ret) {
-+		dev_err(dev, "failed to request irq %d\n", ret);
-+		goto clk_disable;
-+	}
-+
-+	ret = tve200_modeset_init(drm);
-+	if (ret)
-+		goto clk_disable;
-+
-+	ret = drm_dev_register(drm, 0);
-+	if (ret < 0)
-+		goto clk_disable;
-+
-+	return 0;
-+
-+clk_disable:
-+	clk_disable_unprepare(priv->pclk);
-+dev_unref:
-+	drm_dev_unref(drm);
-+	return ret;
-+}
-+
-+static int tve200_remove(struct platform_device *pdev)
-+{
-+	struct drm_device *drm = platform_get_drvdata(pdev);
-+	struct tve200_drm_dev_private *priv = drm->dev_private;
-+
-+	drm_dev_unregister(drm);
-+	if (priv->fbdev)
-+		drm_fbdev_cma_fini(priv->fbdev);
-+	if (priv->panel)
-+		drm_panel_bridge_remove(priv->bridge);
-+	drm_mode_config_cleanup(drm);
-+	clk_disable_unprepare(priv->pclk);
-+	drm_dev_unref(drm);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id tve200_of_match[] = {
-+	{
-+		.compatible = "faraday,tve200",
-+	},
-+	{},
-+};
-+
-+static struct platform_driver tve200_driver = {
-+	.driver = {
-+		.name           = "tve200",
-+		.of_match_table = of_match_ptr(tve200_of_match),
-+	},
-+	.probe = tve200_probe,
-+	.remove = tve200_remove,
-+};
-+module_platform_driver(tve200_driver);
-+
-+MODULE_DESCRIPTION(DRIVER_DESC);
-+MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
-+MODULE_LICENSE("GPL");
---- linux-4.14/drivers/gpu/drm/udl/udl_connector.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/udl/udl_connector.c	2017-12-14 06:39:58.525903644 +0100
-@@ -105,7 +105,7 @@ static struct drm_encoder*
- udl_best_single_encoder(struct drm_connector *connector)
- {
- 	int enc_id = connector->encoder_ids[0];
--	return drm_encoder_find(connector->dev, enc_id);
-+	return drm_encoder_find(connector->dev, NULL, enc_id);
- }
- 
- static int udl_connector_set_property(struct drm_connector *connector,
---- linux-4.14/drivers/gpu/drm/vc4/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/vc4/Makefile	2017-12-14 06:39:58.525903644 +0100
-@@ -25,5 +25,3 @@ vc4-y := \
- vc4-$(CONFIG_DEBUG_FS) += vc4_debugfs.o
- 
- obj-$(CONFIG_DRM_VC4)  += vc4.o
--
--CFLAGS_vc4_trace_points.o := -I$(src)
---- linux-4.14/drivers/gpu/drm/vc4/vc4_dpi.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/vc4/vc4_dpi.c	2017-12-14 06:39:58.525903644 +0100
-@@ -97,8 +97,6 @@ struct vc4_dpi {
- 
- 	struct drm_encoder *encoder;
- 	struct drm_connector *connector;
--	struct drm_bridge *bridge;
--	bool is_panel_bridge;
- 
- 	void __iomem *regs;
- 
-@@ -251,10 +249,11 @@ static int vc4_dpi_init_bridge(struct vc
- {
- 	struct device *dev = &dpi->pdev->dev;
- 	struct drm_panel *panel;
-+	struct drm_bridge *bridge;
- 	int ret;
- 
- 	ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
--					  &panel, &dpi->bridge);
-+					  &panel, &bridge);
- 	if (ret) {
- 		/* If nothing was connected in the DT, that's not an
- 		 * error.
-@@ -265,13 +264,10 @@ static int vc4_dpi_init_bridge(struct vc
- 			return ret;
- 	}
- 
--	if (panel) {
--		dpi->bridge = drm_panel_bridge_add(panel,
--						   DRM_MODE_CONNECTOR_DPI);
--		dpi->is_panel_bridge = true;
--	}
-+	if (panel)
-+		bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DPI);
- 
--	return drm_bridge_attach(dpi->encoder, dpi->bridge, NULL);
-+	return drm_bridge_attach(dpi->encoder, bridge, NULL);
- }
- 
- static int vc4_dpi_bind(struct device *dev, struct device *master, void *data)
-@@ -352,8 +348,7 @@ static void vc4_dpi_unbind(struct device
- 	struct vc4_dev *vc4 = to_vc4_dev(drm);
- 	struct vc4_dpi *dpi = dev_get_drvdata(dev);
- 
--	if (dpi->is_panel_bridge)
--		drm_panel_bridge_remove(dpi->bridge);
-+	drm_of_panel_bridge_remove(dev->of_node, 0, 0);
- 
- 	drm_encoder_cleanup(dpi->encoder);
- 
---- linux-4.14/drivers/gpu/drm/vc4/vc4_dsi.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/vc4/vc4_dsi.c	2017-12-14 06:39:58.526903645 +0100
-@@ -33,6 +33,7 @@
- #include <drm/drm_crtc_helper.h>
- #include <drm/drm_edid.h>
- #include <drm/drm_mipi_dsi.h>
-+#include <drm/drm_of.h>
- #include <drm/drm_panel.h>
- #include <linux/clk.h>
- #include <linux/clk-provider.h>
-@@ -504,7 +505,6 @@ struct vc4_dsi {
- 	struct mipi_dsi_host dsi_host;
- 	struct drm_encoder *encoder;
- 	struct drm_bridge *bridge;
--	bool is_panel_bridge;
- 
- 	void __iomem *regs;
- 
-@@ -859,14 +859,11 @@ static bool vc4_dsi_encoder_mode_fixup(s
- 	pll_clock = parent_rate / divider;
- 	pixel_clock_hz = pll_clock / dsi->divider;
- 
--	/* Round up the clk_set_rate() request slightly, since
--	 * PLLD_DSI1 is an integer divider and its rate selection will
--	 * never round up.
--	 */
--	adjusted_mode->clock = pixel_clock_hz / 1000 + 1;
-+	adjusted_mode->clock = pixel_clock_hz / 1000;
- 
- 	/* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
--	adjusted_mode->htotal = pixel_clock_hz / (mode->vrefresh * mode->vtotal);
-+	adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
-+				mode->clock;
- 	adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal;
- 	adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal;
- 
-@@ -900,7 +897,11 @@ static void vc4_dsi_encoder_enable(struc
- 		vc4_dsi_dump_regs(dsi);
- 	}
- 
--	phy_clock = pixel_clock_hz * dsi->divider;
-+	/* Round up the clk_set_rate() request slightly, since
-+	 * PLLD_DSI1 is an integer divider and its rate selection will
-+	 * never round up.
-+	 */
-+	phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
- 	ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
- 	if (ret) {
- 		dev_err(&dsi->pdev->dev,
-@@ -1288,7 +1289,6 @@ static int vc4_dsi_host_attach(struct mi
- 			       struct mipi_dsi_device *device)
- {
- 	struct vc4_dsi *dsi = host_to_dsi(host);
--	int ret = 0;
- 
- 	dsi->lanes = device->lanes;
- 	dsi->channel = device->channel;
-@@ -1323,34 +1323,12 @@ static int vc4_dsi_host_attach(struct mi
- 		return 0;
- 	}
- 
--	dsi->bridge = of_drm_find_bridge(device->dev.of_node);
--	if (!dsi->bridge) {
--		struct drm_panel *panel =
--			of_drm_find_panel(device->dev.of_node);
--
--		dsi->bridge = drm_panel_bridge_add(panel,
--						   DRM_MODE_CONNECTOR_DSI);
--		if (IS_ERR(dsi->bridge)) {
--			ret = PTR_ERR(dsi->bridge);
--			dsi->bridge = NULL;
--			return ret;
--		}
--		dsi->is_panel_bridge = true;
--	}
--
--	return drm_bridge_attach(dsi->encoder, dsi->bridge, NULL);
-+	return 0;
- }
- 
- static int vc4_dsi_host_detach(struct mipi_dsi_host *host,
- 			       struct mipi_dsi_device *device)
- {
--	struct vc4_dsi *dsi = host_to_dsi(host);
--
--	if (dsi->is_panel_bridge) {
--		drm_panel_bridge_remove(dsi->bridge);
--		dsi->bridge = NULL;
--	}
--
- 	return 0;
- }
- 
-@@ -1492,16 +1470,13 @@ static int vc4_dsi_bind(struct device *d
- 	struct platform_device *pdev = to_platform_device(dev);
- 	struct drm_device *drm = dev_get_drvdata(master);
- 	struct vc4_dev *vc4 = to_vc4_dev(drm);
--	struct vc4_dsi *dsi;
-+	struct vc4_dsi *dsi = dev_get_drvdata(dev);
- 	struct vc4_dsi_encoder *vc4_dsi_encoder;
-+	struct drm_panel *panel;
- 	const struct of_device_id *match;
- 	dma_cap_mask_t dma_mask;
- 	int ret;
- 
--	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
--	if (!dsi)
--		return -ENOMEM;
--
- 	match = of_match_device(vc4_dsi_dt_match, dev);
- 	if (!match)
- 		return -ENODEV;
-@@ -1516,7 +1491,6 @@ static int vc4_dsi_bind(struct device *d
- 	vc4_dsi_encoder->dsi = dsi;
- 	dsi->encoder = &vc4_dsi_encoder->base.base;
- 
--	dsi->pdev = pdev;
- 	dsi->regs = vc4_ioremap_regs(pdev, 0);
- 	if (IS_ERR(dsi->regs))
- 		return PTR_ERR(dsi->regs);
-@@ -1597,6 +1571,18 @@ static int vc4_dsi_bind(struct device *d
- 		return ret;
- 	}
- 
-+	ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
-+					  &panel, &dsi->bridge);
-+	if (ret)
-+		return ret;
-+
-+	if (panel) {
-+		dsi->bridge = devm_drm_panel_bridge_add(dev, panel,
-+							DRM_MODE_CONNECTOR_DSI);
-+		if (IS_ERR(dsi->bridge))
-+			return PTR_ERR(dsi->bridge);
-+	}
-+
- 	/* The esc clock rate is supposed to always be 100Mhz. */
- 	ret = clk_set_rate(dsi->escape_clock, 100 * 1000000);
- 	if (ret) {
-@@ -1615,12 +1601,11 @@ static int vc4_dsi_bind(struct device *d
- 			 DRM_MODE_ENCODER_DSI, NULL);
- 	drm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs);
- 
--	dsi->dsi_host.ops = &vc4_dsi_host_ops;
--	dsi->dsi_host.dev = dev;
--
--	mipi_dsi_host_register(&dsi->dsi_host);
--
--	dev_set_drvdata(dev, dsi);
-+	ret = drm_bridge_attach(dsi->encoder, dsi->bridge, NULL);
-+	if (ret) {
-+		dev_err(dev, "bridge attach failed: %d\n", ret);
-+		return ret;
-+	}
- 
- 	pm_runtime_enable(dev);
- 
-@@ -1638,8 +1623,6 @@ static void vc4_dsi_unbind(struct device
- 
- 	vc4_dsi_encoder_destroy(dsi->encoder);
- 
--	mipi_dsi_host_unregister(&dsi->dsi_host);
--
- 	if (dsi->port == 1)
- 		vc4->dsi1 = NULL;
- }
-@@ -1651,12 +1634,47 @@ static const struct component_ops vc4_ds
- 
- static int vc4_dsi_dev_probe(struct platform_device *pdev)
- {
--	return component_add(&pdev->dev, &vc4_dsi_ops);
-+	struct device *dev = &pdev->dev;
-+	struct vc4_dsi *dsi;
-+	int ret;
-+
-+	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
-+	if (!dsi)
-+		return -ENOMEM;
-+	dev_set_drvdata(dev, dsi);
-+
-+	dsi->pdev = pdev;
-+
-+	/* Note, the initialization sequence for DSI and panels is
-+	 * tricky.  The component bind above won't get past its
-+	 * -EPROBE_DEFER until the panel/bridge probes.  The
-+	 * panel/bridge will return -EPROBE_DEFER until it has a
-+	 * mipi_dsi_host to register its device to.  So, we register
-+	 * the host during pdev probe time, so vc4 as a whole can then
-+	 * -EPROBE_DEFER its component bind process until the panel
-+	 * successfully attaches.
-+	 */
-+	dsi->dsi_host.ops = &vc4_dsi_host_ops;
-+	dsi->dsi_host.dev = dev;
-+	mipi_dsi_host_register(&dsi->dsi_host);
-+
-+	ret = component_add(&pdev->dev, &vc4_dsi_ops);
-+	if (ret) {
-+		mipi_dsi_host_unregister(&dsi->dsi_host);
-+		return ret;
-+	}
-+
-+	return 0;
- }
- 
- static int vc4_dsi_dev_remove(struct platform_device *pdev)
- {
-+	struct device *dev = &pdev->dev;
-+	struct vc4_dsi *dsi = dev_get_drvdata(dev);
-+
- 	component_del(&pdev->dev, &vc4_dsi_ops);
-+	mipi_dsi_host_unregister(&dsi->dsi_host);
-+
- 	return 0;
- }
- 
---- linux-4.14/drivers/gpu/drm/vc4/vc4_hdmi.c.0130~	2017-12-14 06:39:58.284903476 +0100
-+++ linux-4.14/drivers/gpu/drm/vc4/vc4_hdmi.c	2017-12-14 06:39:58.526903645 +0100
-@@ -309,16 +309,13 @@ static const struct drm_connector_helper
- static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
- 						     struct drm_encoder *encoder)
- {
--	struct drm_connector *connector = NULL;
-+	struct drm_connector *connector;
- 	struct vc4_hdmi_connector *hdmi_connector;
--	int ret = 0;
- 
- 	hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
- 				      GFP_KERNEL);
--	if (!hdmi_connector) {
--		ret = -ENOMEM;
--		goto fail;
--	}
-+	if (!hdmi_connector)
-+		return ERR_PTR(-ENOMEM);
- 	connector = &hdmi_connector->base;
- 
- 	hdmi_connector->encoder = encoder;
-@@ -336,12 +333,6 @@ static struct drm_connector *vc4_hdmi_co
- 	drm_mode_connector_attach_encoder(connector, encoder);
- 
- 	return connector;
--
-- fail:
--	if (connector)
--		vc4_hdmi_connector_destroy(connector);
--
--	return ERR_PTR(ret);
- }
- 
- static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
---- linux-4.14/drivers/gpu/drm/vc4/vc4_plane.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/vc4/vc4_plane.c	2017-12-14 06:39:58.526903645 +0100
-@@ -547,14 +547,24 @@ static int vc4_plane_mode_set(struct drm
- 		tiling = SCALER_CTL0_TILING_LINEAR;
- 		pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
- 		break;
--	case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
-+
-+	case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
-+		/* For T-tiled, the FB pitch is "how many bytes from
-+		 * one row to the next, such that pitch * tile_h ==
-+		 * tile_size * tiles_per_row."
-+		 */
-+		u32 tile_size_shift = 12; /* T tiles are 4kb */
-+		u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
-+		u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
-+
- 		tiling = SCALER_CTL0_TILING_256B_OR_T;
- 
--		pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET),
--			  VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L),
--			  VC4_SET_FIELD((vc4_state->src_w[0] + 31) >> 5,
--					SCALER_PITCH0_TILE_WIDTH_R));
-+		pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) |
-+			  VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) |
-+			  VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R));
- 		break;
-+	}
-+
- 	default:
- 		DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
- 			      (long long)fb->modifier);
---- linux-4.14/drivers/gpu/drm/vc4/vc4_trace.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/vc4/vc4_trace.h	2017-12-14 06:39:58.526903645 +0100
-@@ -59,5 +59,5 @@ TRACE_EVENT(vc4_wait_for_seqno_end,
- 
- /* This part must be outside protection */
- #undef TRACE_INCLUDE_PATH
--#define TRACE_INCLUDE_PATH .
-+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/vc4
- #include <trace/define_trace.h>
---- linux-4.14/drivers/gpu/drm/via/via_verifier.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/via/via_verifier.c	2017-12-14 06:39:58.526903645 +0100
-@@ -34,6 +34,7 @@
- #include <drm/drm_legacy.h>
- #include "via_verifier.h"
- #include "via_drv.h"
-+#include <linux/kernel.h>
- 
- typedef enum {
- 	state_command,
-@@ -1102,10 +1103,7 @@ setup_hazard_table(hz_init_t init_table[
- 
- void via_init_command_verifier(void)
- {
--	setup_hazard_table(init_table1, table1,
--			   sizeof(init_table1) / sizeof(hz_init_t));
--	setup_hazard_table(init_table2, table2,
--			   sizeof(init_table2) / sizeof(hz_init_t));
--	setup_hazard_table(init_table3, table3,
--			   sizeof(init_table3) / sizeof(hz_init_t));
-+	setup_hazard_table(init_table1, table1, ARRAY_SIZE(init_table1));
-+	setup_hazard_table(init_table2, table2, ARRAY_SIZE(init_table2));
-+	setup_hazard_table(init_table3, table3, ARRAY_SIZE(init_table3));
- }
---- linux-4.14/drivers/gpu/drm/virtio/virtgpu_display.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/virtio/virtgpu_display.c	2017-12-14 06:39:58.526903645 +0100
-@@ -53,7 +53,7 @@ static void virtio_gpu_user_framebuffer_
- 	struct virtio_gpu_framebuffer *virtio_gpu_fb
- 		= to_virtio_gpu_framebuffer(fb);
- 
--	drm_gem_object_unreference_unlocked(virtio_gpu_fb->obj);
-+	drm_gem_object_put_unlocked(virtio_gpu_fb->obj);
- 	drm_framebuffer_cleanup(fb);
- 	kfree(virtio_gpu_fb);
- }
-@@ -327,7 +327,7 @@ virtio_gpu_user_framebuffer_create(struc
- 	ret = virtio_gpu_framebuffer_init(dev, virtio_gpu_fb, mode_cmd, obj);
- 	if (ret) {
- 		kfree(virtio_gpu_fb);
--		drm_gem_object_unreference_unlocked(obj);
-+		drm_gem_object_put_unlocked(obj);
- 		return NULL;
- 	}
- 
---- linux-4.14/drivers/gpu/drm/virtio/virtgpu_gem.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/virtio/virtgpu_gem.c	2017-12-14 06:39:58.526903645 +0100
-@@ -72,7 +72,7 @@ int virtio_gpu_gem_create(struct drm_fil
- 	*obj_p = &obj->gem_base;
- 
- 	/* drop reference from allocate - handle holds it now */
--	drm_gem_object_unreference_unlocked(&obj->gem_base);
-+	drm_gem_object_put_unlocked(&obj->gem_base);
- 
- 	*handle_p = handle;
- 	return 0;
-@@ -130,7 +130,7 @@ int virtio_gpu_mode_dumb_mmap(struct drm
- 		return -ENOENT;
- 	obj = gem_to_virtio_gpu_obj(gobj);
- 	*offset_p = virtio_gpu_object_mmap_offset(obj);
--	drm_gem_object_unreference_unlocked(gobj);
-+	drm_gem_object_put_unlocked(gobj);
- 	return 0;
- }
- 
---- linux-4.14/drivers/gpu/drm/virtio/virtgpu_ioctl.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/virtio/virtgpu_ioctl.c	2017-12-14 06:39:58.526903645 +0100
-@@ -86,7 +86,7 @@ static void virtio_gpu_unref_list(struct
- 		bo = buf->bo;
- 		qobj = container_of(bo, struct virtio_gpu_object, tbo);
- 
--		drm_gem_object_unreference_unlocked(&qobj->gem_base);
-+		drm_gem_object_put_unlocked(&qobj->gem_base);
- 	}
- }
- 
-@@ -304,7 +304,7 @@ static int virtio_gpu_resource_create_io
- 		}
- 		return ret;
- 	}
--	drm_gem_object_unreference_unlocked(obj);
-+	drm_gem_object_put_unlocked(obj);
- 
- 	rc->res_handle = res_id; /* similiar to a VM address */
- 	rc->bo_handle = handle;
-@@ -341,7 +341,7 @@ static int virtio_gpu_resource_info_ioct
- 
- 	ri->size = qobj->gem_base.size;
- 	ri->res_handle = qobj->hw_res_handle;
--	drm_gem_object_unreference_unlocked(gobj);
-+	drm_gem_object_put_unlocked(gobj);
- 	return 0;
- }
- 
-@@ -389,7 +389,7 @@ static int virtio_gpu_transfer_from_host
- out_unres:
- 	virtio_gpu_object_unreserve(qobj);
- out:
--	drm_gem_object_unreference_unlocked(gobj);
-+	drm_gem_object_put_unlocked(gobj);
- 	return ret;
- }
- 
-@@ -439,7 +439,7 @@ static int virtio_gpu_transfer_to_host_i
- out_unres:
- 	virtio_gpu_object_unreserve(qobj);
- out:
--	drm_gem_object_unreference_unlocked(gobj);
-+	drm_gem_object_put_unlocked(gobj);
- 	return ret;
- }
- 
-@@ -462,7 +462,7 @@ static int virtio_gpu_wait_ioctl(struct
- 		nowait = true;
- 	ret = virtio_gpu_object_wait(qobj, nowait);
- 
--	drm_gem_object_unreference_unlocked(gobj);
-+	drm_gem_object_put_unlocked(gobj);
- 	return ret;
- }
- 
---- linux-4.14/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c	2017-12-14 06:39:58.526903645 +0100
-@@ -286,7 +286,7 @@ int vmw_present_ioctl(struct drm_device
- 
- 	drm_modeset_lock_all(dev);
- 
--	fb = drm_framebuffer_lookup(dev, arg->fb_id);
-+	fb = drm_framebuffer_lookup(dev, file_priv, arg->fb_id);
- 	if (!fb) {
- 		DRM_ERROR("Invalid framebuffer id.\n");
- 		ret = -ENOENT;
-@@ -369,7 +369,7 @@ int vmw_present_readback_ioctl(struct dr
- 
- 	drm_modeset_lock_all(dev);
- 
--	fb = drm_framebuffer_lookup(dev, arg->fb_id);
-+	fb = drm_framebuffer_lookup(dev, file_priv, arg->fb_id);
- 	if (!fb) {
- 		DRM_ERROR("Invalid framebuffer id.\n");
- 		ret = -ENOENT;
---- linux-4.14/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c	2017-12-14 06:39:58.526903645 +0100
-@@ -1726,7 +1726,7 @@ int vmw_kms_cursor_bypass_ioctl(struct d
- 		return 0;
- 	}
- 
--	crtc = drm_crtc_find(dev, arg->crtc_id);
-+	crtc = drm_crtc_find(dev, file_priv, arg->crtc_id);
- 	if (!crtc) {
- 		ret = -ENOENT;
- 		goto out;
---- linux-4.14/drivers/gpu/drm/zte/zx_drm_drv.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/gpu/drm/zte/zx_drm_drv.c	2017-12-14 06:39:58.527903645 +0100
-@@ -22,6 +22,7 @@
- #include <drm/drm_fb_cma_helper.h>
- #include <drm/drm_fb_helper.h>
- #include <drm/drm_gem_cma_helper.h>
-+#include <drm/drm_gem_framebuffer_helper.h>
- #include <drm/drm_of.h>
- #include <drm/drmP.h>
- 
-@@ -40,7 +41,7 @@ static void zx_drm_fb_output_poll_change
- }
- 
- static const struct drm_mode_config_funcs zx_drm_mode_config_funcs = {
--	.fb_create = drm_fb_cma_create,
-+	.fb_create = drm_gem_fb_create,
- 	.output_poll_changed = zx_drm_fb_output_poll_changed,
- 	.atomic_check = drm_atomic_helper_check,
- 	.atomic_commit = drm_atomic_helper_commit,
---- linux-4.14/drivers/media/v4l2-core/videobuf2-dma-contig.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/media/v4l2-core/videobuf2-dma-contig.c	2017-12-14 06:39:58.527903645 +0100
-@@ -479,7 +479,7 @@ static void *vb2_dc_get_userptr(struct d
- {
- 	struct vb2_dc_buf *buf;
- 	struct frame_vector *vec;
--	unsigned long offset;
-+	unsigned int offset;
- 	int n_pages, i;
- 	int ret = 0;
- 	struct sg_table *sgt;
-@@ -507,7 +507,7 @@ static void *vb2_dc_get_userptr(struct d
- 	buf->dev = dev;
- 	buf->dma_dir = dma_dir;
- 
--	offset = vaddr & ~PAGE_MASK;
-+	offset = lower_32_bits(offset_in_page(vaddr));
- 	vec = vb2_create_framevec(vaddr, size, dma_dir == DMA_FROM_DEVICE ||
- 					       dma_dir == DMA_BIDIRECTIONAL);
- 	if (IS_ERR(vec)) {
---- linux-4.14/drivers/pci/pci.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/pci/pci.c	2017-12-14 06:39:58.527903645 +0100
-@@ -2966,6 +2966,107 @@ bool pci_acs_path_enabled(struct pci_dev
- }
- 
- /**
-+ * pci_rebar_find_pos - find position of resize ctrl reg for BAR
-+ * @pdev: PCI device
-+ * @bar: BAR to find
-+ *
-+ * Helper to find the position of the ctrl register for a BAR.
-+ * Returns -ENOTSUPP if resizable BARs are not supported at all.
-+ * Returns -ENOENT if no ctrl register for the BAR could be found.
-+ */
-+static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
-+{
-+	unsigned int pos, nbars, i;
-+	u32 ctrl;
-+
-+	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
-+	if (!pos)
-+		return -ENOTSUPP;
-+
-+	pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
-+	nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
-+		    PCI_REBAR_CTRL_NBAR_SHIFT;
-+
-+	for (i = 0; i < nbars; i++, pos += 8) {
-+		int bar_idx;
-+
-+		pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
-+		bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
-+		if (bar_idx == bar)
-+			return pos;
-+	}
-+
-+	return -ENOENT;
-+}
-+
-+/**
-+ * pci_rebar_get_possible_sizes - get possible sizes for BAR
-+ * @pdev: PCI device
-+ * @bar: BAR to query
-+ *
-+ * Get the possible sizes of a resizable BAR as bitmask defined in the spec
-+ * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
-+ */
-+u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
-+{
-+	int pos;
-+	u32 cap;
-+
-+	pos = pci_rebar_find_pos(pdev, bar);
-+	if (pos < 0)
-+		return 0;
-+
-+	pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
-+	return (cap & PCI_REBAR_CAP_SIZES) >> 4;
-+}
-+
-+/**
-+ * pci_rebar_get_current_size - get the current size of a BAR
-+ * @pdev: PCI device
-+ * @bar: BAR to set size to
-+ *
-+ * Read the size of a BAR from the resizable BAR config.
-+ * Returns size if found or negative error code.
-+ */
-+int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
-+{
-+	int pos;
-+	u32 ctrl;
-+
-+	pos = pci_rebar_find_pos(pdev, bar);
-+	if (pos < 0)
-+		return pos;
-+
-+	pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
-+	return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> 8;
-+}
-+
-+/**
-+ * pci_rebar_set_size - set a new size for a BAR
-+ * @pdev: PCI device
-+ * @bar: BAR to set size to
-+ * @size: new size as defined in the spec (0=1MB, 19=512GB)
-+ *
-+ * Set the new size of a BAR as defined in the spec.
-+ * Returns zero if resizing was successful, error code otherwise.
-+ */
-+int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
-+{
-+	int pos;
-+	u32 ctrl;
-+
-+	pos = pci_rebar_find_pos(pdev, bar);
-+	if (pos < 0)
-+		return pos;
-+
-+	pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
-+	ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
-+	ctrl |= size << 8;
-+	pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
-+	return 0;
-+}
-+
-+/**
-  * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
-  * @dev: the PCI device
-  * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
---- linux-4.14/drivers/pci/pci.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/pci/pci.h	2017-12-14 06:39:58.527903645 +0100
-@@ -367,4 +367,12 @@ int acpi_get_rc_resources(struct device
- 			  struct resource *res);
- #endif
- 
-+u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
-+int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
-+int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
-+static inline u64 pci_rebar_size_to_bytes(int size)
-+{
-+	return 1ULL << (size + 20);
-+}
-+
- #endif /* DRIVERS_PCI_H */
---- linux-4.14/drivers/pci/setup-bus.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/pci/setup-bus.c	2017-12-14 06:39:58.527903645 +0100
-@@ -1518,13 +1518,16 @@ static void __pci_bridge_assign_resource
- 		break;
- 	}
- }
-+
-+#define PCI_RES_TYPE_MASK \
-+	(IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
-+	 IORESOURCE_MEM_64)
-+
- static void pci_bridge_release_resources(struct pci_bus *bus,
- 					  unsigned long type)
- {
- 	struct pci_dev *dev = bus->self;
- 	struct resource *r;
--	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
--				  IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
- 	unsigned old_flags = 0;
- 	struct resource *b_res;
- 	int idx = 1;
-@@ -1567,7 +1570,7 @@ static void pci_bridge_release_resources
- 	 */
- 	release_child_resources(r);
- 	if (!release_resource(r)) {
--		type = old_flags = r->flags & type_mask;
-+		type = old_flags = r->flags & PCI_RES_TYPE_MASK;
- 		dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n",
- 					PCI_BRIDGE_RESOURCES + idx, r);
- 		/* keep the old size */
-@@ -1758,8 +1761,6 @@ void pci_assign_unassigned_root_bus_reso
- 	enum release_type rel_type = leaf_only;
- 	LIST_HEAD(fail_head);
- 	struct pci_dev_resource *fail_res;
--	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
--				  IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
- 	int pci_try_num = 1;
- 	enum enable_type enable_local;
- 
-@@ -1818,7 +1819,7 @@ again:
- 	 */
- 	list_for_each_entry(fail_res, &fail_head, list)
- 		pci_bus_release_bridge_resources(fail_res->dev->bus,
--						 fail_res->flags & type_mask,
-+						 fail_res->flags & PCI_RES_TYPE_MASK,
- 						 rel_type);
- 
- 	/* restore size and flags */
-@@ -1862,8 +1863,6 @@ void pci_assign_unassigned_bridge_resour
- 	LIST_HEAD(fail_head);
- 	struct pci_dev_resource *fail_res;
- 	int retval;
--	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
--				  IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
- 
- again:
- 	__pci_bus_size_bridges(parent, &add_list);
-@@ -1889,7 +1888,7 @@ again:
- 	 */
- 	list_for_each_entry(fail_res, &fail_head, list)
- 		pci_bus_release_bridge_resources(fail_res->dev->bus,
--						 fail_res->flags & type_mask,
-+						 fail_res->flags & PCI_RES_TYPE_MASK,
- 						 whole_subtree);
- 
- 	/* restore size and flags */
-@@ -1914,6 +1913,104 @@ enable_all:
- }
- EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
- 
-+int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
-+{
-+	struct pci_dev_resource *dev_res;
-+	struct pci_dev *next;
-+	LIST_HEAD(saved);
-+	LIST_HEAD(added);
-+	LIST_HEAD(failed);
-+	unsigned int i;
-+	int ret;
-+
-+	/* Walk to the root hub, releasing bridge BARs when possible */
-+	next = bridge;
-+	do {
-+		bridge = next;
-+		for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
-+		     i++) {
-+			struct resource *res = &bridge->resource[i];
-+
-+			if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
-+				continue;
-+
-+			/* Ignore BARs which are still in use */
-+			if (res->child)
-+				continue;
-+
-+			ret = add_to_list(&saved, bridge, res, 0, 0);
-+			if (ret)
-+				goto cleanup;
-+
-+			dev_info(&bridge->dev, "BAR %d: releasing %pR\n",
-+				 i, res);
-+
-+			if (res->parent)
-+				release_resource(res);
-+			res->start = 0;
-+			res->end = 0;
-+			break;
-+		}
-+		if (i == PCI_BRIDGE_RESOURCE_END)
-+			break;
-+
-+		next = bridge->bus ? bridge->bus->self : NULL;
-+	} while (next);
-+
-+	if (list_empty(&saved))
-+		return -ENOENT;
-+
-+	__pci_bus_size_bridges(bridge->subordinate, &added);
-+	__pci_bridge_assign_resources(bridge, &added, &failed);
-+	BUG_ON(!list_empty(&added));
-+
-+	if (!list_empty(&failed)) {
-+		ret = -ENOSPC;
-+		goto cleanup;
-+	}
-+
-+	list_for_each_entry(dev_res, &saved, list) {
-+		/* Skip the bridge we just assigned resources for. */
-+		if (bridge == dev_res->dev)
-+			continue;
-+
-+		bridge = dev_res->dev;
-+		pci_setup_bridge(bridge->subordinate);
-+	}
-+
-+	free_list(&saved);
-+	return 0;
-+
-+cleanup:
-+	/* restore size and flags */
-+	list_for_each_entry(dev_res, &failed, list) {
-+		struct resource *res = dev_res->res;
-+
-+		res->start = dev_res->start;
-+		res->end = dev_res->end;
-+		res->flags = dev_res->flags;
-+	}
-+	free_list(&failed);
-+
-+	/* Revert to the old configuration */
-+	list_for_each_entry(dev_res, &saved, list) {
-+		struct resource *res = dev_res->res;
-+
-+		bridge = dev_res->dev;
-+		i = res - bridge->resource;
-+
-+		res->start = dev_res->start;
-+		res->end = dev_res->end;
-+		res->flags = dev_res->flags;
-+
-+		pci_claim_resource(bridge, i);
-+		pci_setup_bridge(bridge->subordinate);
-+	}
-+	free_list(&saved);
-+
-+	return ret;
-+}
-+
- void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
- {
- 	struct pci_dev *dev;
---- linux-4.14/drivers/pci/setup-res.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/pci/setup-res.c	2017-12-14 06:39:58.527903645 +0100
-@@ -397,6 +397,64 @@ int pci_reassign_resource(struct pci_dev
- 	return 0;
- }
- 
-+void pci_release_resource(struct pci_dev *dev, int resno)
-+{
-+	struct resource *res = dev->resource + resno;
-+
-+	dev_info(&dev->dev, "BAR %d: releasing %pR\n", resno, res);
-+	release_resource(res);
-+	res->end = resource_size(res) - 1;
-+	res->start = 0;
-+	res->flags |= IORESOURCE_UNSET;
-+}
-+EXPORT_SYMBOL(pci_release_resource);
-+
-+int pci_resize_resource(struct pci_dev *dev, int resno, int size)
-+{
-+	struct resource *res = dev->resource + resno;
-+	int old, ret;
-+	u32 sizes;
-+	u16 cmd;
-+
-+	/* Make sure the resource isn't assigned before resizing it. */
-+	if (!(res->flags & IORESOURCE_UNSET))
-+		return -EBUSY;
-+
-+	pci_read_config_word(dev, PCI_COMMAND, &cmd);
-+	if (cmd & PCI_COMMAND_MEMORY)
-+		return -EBUSY;
-+
-+	sizes = pci_rebar_get_possible_sizes(dev, resno);
-+	if (!sizes)
-+		return -ENOTSUPP;
-+
-+	if (!(sizes & BIT(size)))
-+		return -EINVAL;
-+
-+	old = pci_rebar_get_current_size(dev, resno);
-+	if (old < 0)
-+		return old;
-+
-+	ret = pci_rebar_set_size(dev, resno, size);
-+	if (ret)
-+		return ret;
-+
-+	res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
-+
-+	/* Check if the new config works by trying to assign everything. */
-+	ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
-+	if (ret)
-+		goto error_resize;
-+
-+	return 0;
-+
-+error_resize:
-+	pci_rebar_set_size(dev, resno, old);
-+	res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
-+	return ret;
-+}
-+EXPORT_SYMBOL(pci_resize_resource);
-+
- int pci_enable_resources(struct pci_dev *dev, int mask)
- {
- 	u16 cmd, old_cmd;
---- linux-4.14/drivers/rapidio/devices/rio_mport_cdev.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/drivers/rapidio/devices/rio_mport_cdev.c	2017-12-14 06:39:58.528903646 +0100
-@@ -876,10 +876,10 @@ rio_dma_transfer(struct file *filp, u32
- 	 * offset within the internal buffer specified by handle parameter.
- 	 */
- 	if (xfer->loc_addr) {
--		unsigned long offset;
-+		unsigned int offset;
- 		long pinned;
- 
--		offset = (unsigned long)(uintptr_t)xfer->loc_addr & ~PAGE_MASK;
-+		offset = lower_32_bits(offset_in_page(xfer->loc_addr));
- 		nr_pages = PAGE_ALIGN(xfer->length + offset) >> PAGE_SHIFT;
- 
- 		page_list = kmalloc_array(nr_pages,
---- linux-4.14/drivers/staging/vboxvideo/vbox_mode.c.0130~	2017-12-14 06:39:58.289903480 +0100
-+++ linux-4.14/drivers/staging/vboxvideo/vbox_mode.c	2017-12-14 06:39:58.528903646 +0100
-@@ -377,7 +377,7 @@ static struct drm_encoder *vbox_best_sin
- 
- 	/* pick the encoder ids */
- 	if (enc_id)
--		return drm_encoder_find(connector->dev, enc_id);
-+		return drm_encoder_find(connector->dev, NULL, enc_id);
- 
- 	return NULL;
- }
---- linux-4.14/include/drm/amd_asic_type.h.0130~	2017-12-14 06:39:58.528903646 +0100
-+++ linux-4.14/include/drm/amd_asic_type.h	2017-12-14 06:39:58.528903646 +0100
-@@ -0,0 +1,52 @@
-+/*
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#ifndef __AMD_ASIC_TYPE_H__
-+#define __AMD_ASIC_TYPE_H__
-+/*
-+ * Supported ASIC types
-+ */
-+enum amd_asic_type {
-+	CHIP_TAHITI = 0,
-+	CHIP_PITCAIRN,
-+	CHIP_VERDE,
-+	CHIP_OLAND,
-+	CHIP_HAINAN,
-+	CHIP_BONAIRE,
-+	CHIP_KAVERI,
-+	CHIP_KABINI,
-+	CHIP_HAWAII,
-+	CHIP_MULLINS,
-+	CHIP_TOPAZ,
-+	CHIP_TONGA,
-+	CHIP_FIJI,
-+	CHIP_CARRIZO,
-+	CHIP_STONEY,
-+	CHIP_POLARIS10,
-+	CHIP_POLARIS11,
-+	CHIP_POLARIS12,
-+	CHIP_VEGA10,
-+	CHIP_RAVEN,
-+	CHIP_LAST,
-+};
-+
-+#endif /*__AMD_ASIC_TYPE_H__ */
---- linux-4.14/include/drm/bridge/mhl.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/bridge/mhl.h	2017-12-14 06:39:58.528903646 +0100
-@@ -262,6 +262,10 @@ enum {
- #define MHL_RAPK_UNSUPPORTED	0x02	/* Rcvd RAP action code not supported */
- #define MHL_RAPK_BUSY		0x03	/* Responder too busy to respond */
- 
-+/* Bit masks for RCP messages */
-+#define MHL_RCP_KEY_RELEASED_MASK	0x80
-+#define MHL_RCP_KEY_ID_MASK		0x7F
-+
- /*
-  * Error status codes for RCPE messages
-  */
---- linux-4.14/include/drm/drm_atomic.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_atomic.h	2017-12-14 06:39:58.528903646 +0100
-@@ -144,7 +144,6 @@ struct __drm_planes_state {
- struct __drm_crtcs_state {
- 	struct drm_crtc *ptr;
- 	struct drm_crtc_state *state, *old_state, *new_state;
--	struct drm_crtc_commit *commit;
- 	s32 __user *out_fence_ptr;
- 	unsigned last_vblank_count;
- };
-@@ -237,6 +236,18 @@ struct drm_atomic_state {
- 	struct drm_modeset_acquire_ctx *acquire_ctx;
- 
- 	/**
-+	 * @fake_commit:
-+	 *
-+	 * Used for signaling unbound planes/connectors.
-+	 * When a connector or plane is not bound to any CRTC, it's still important
-+	 * to preserve linearity to prevent the atomic states from being freed to early.
-+	 *
-+	 * This commit (if set) is not bound to any crtc, but will be completed when
-+	 * drm_atomic_helper_commit_hw_done() is called.
-+	 */
-+	struct drm_crtc_commit *fake_commit;
-+
-+	/**
- 	 * @commit_work:
- 	 *
- 	 * Work item which can be used by the driver or helpers to execute the
-@@ -252,10 +263,14 @@ void __drm_crtc_commit_free(struct kref
-  * @commit: CRTC commit
-  *
-  * Increases the reference of @commit.
-+ *
-+ * Returns:
-+ * The pointer to @commit, with reference increased.
-  */
--static inline void drm_crtc_commit_get(struct drm_crtc_commit *commit)
-+static inline struct drm_crtc_commit *drm_crtc_commit_get(struct drm_crtc_commit *commit)
- {
- 	kref_get(&commit->ref);
-+	return commit;
- }
- 
- /**
-@@ -555,31 +570,6 @@ int __must_check drm_atomic_nonblocking_
- void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
- 
- /**
-- * for_each_connector_in_state - iterate over all connectors in an atomic update
-- * @__state: &struct drm_atomic_state pointer
-- * @connector: &struct drm_connector iteration cursor
-- * @connector_state: &struct drm_connector_state iteration cursor
-- * @__i: int iteration cursor, for macro-internal use
-- *
-- * This iterates over all connectors in an atomic update. Note that before the
-- * software state is committed (by calling drm_atomic_helper_swap_state(), this
-- * points to the new state, while afterwards it points to the old state. Due to
-- * this tricky confusion this macro is deprecated.
-- *
-- * FIXME:
-- *
-- * Replace all usage of this with one of the explicit iterators below and then
-- * remove this macro.
-- */
--#define for_each_connector_in_state(__state, connector, connector_state, __i) \
--	for ((__i) = 0;							\
--	     (__i) < (__state)->num_connector &&				\
--	     ((connector) = (__state)->connectors[__i].ptr,			\
--	     (connector_state) = (__state)->connectors[__i].state, 1); 	\
--	     (__i)++)							\
--		for_each_if (connector)
--
--/**
-  * for_each_oldnew_connector_in_state - iterate over all connectors in an atomic update
-  * @__state: &struct drm_atomic_state pointer
-  * @connector: &struct drm_connector iteration cursor
-@@ -595,12 +585,12 @@ void drm_state_dump(struct drm_device *d
-  */
- #define for_each_oldnew_connector_in_state(__state, connector, old_connector_state, new_connector_state, __i) \
- 	for ((__i) = 0;								\
--	     (__i) < (__state)->num_connector &&				\
--	     ((connector) = (__state)->connectors[__i].ptr,			\
--	     (old_connector_state) = (__state)->connectors[__i].old_state,	\
--	     (new_connector_state) = (__state)->connectors[__i].new_state, 1); 	\
--	     (__i)++)							\
--		for_each_if (connector)
-+	     (__i) < (__state)->num_connector;					\
-+	     (__i)++)								\
-+		for_each_if ((__state)->connectors[__i].ptr &&			\
-+			     ((connector) = (__state)->connectors[__i].ptr,	\
-+			     (old_connector_state) = (__state)->connectors[__i].old_state,	\
-+			     (new_connector_state) = (__state)->connectors[__i].new_state, 1))
- 
- /**
-  * for_each_old_connector_in_state - iterate over all connectors in an atomic update
-@@ -616,11 +606,11 @@ void drm_state_dump(struct drm_device *d
-  */
- #define for_each_old_connector_in_state(__state, connector, old_connector_state, __i) \
- 	for ((__i) = 0;								\
--	     (__i) < (__state)->num_connector &&				\
--	     ((connector) = (__state)->connectors[__i].ptr,			\
--	     (old_connector_state) = (__state)->connectors[__i].old_state, 1); 	\
--	     (__i)++)							\
--		for_each_if (connector)
-+	     (__i) < (__state)->num_connector;					\
-+	     (__i)++)								\
-+		for_each_if ((__state)->connectors[__i].ptr &&			\
-+			     ((connector) = (__state)->connectors[__i].ptr,	\
-+			     (old_connector_state) = (__state)->connectors[__i].old_state, 1))
- 
- /**
-  * for_each_new_connector_in_state - iterate over all connectors in an atomic update
-@@ -636,36 +626,11 @@ void drm_state_dump(struct drm_device *d
-  */
- #define for_each_new_connector_in_state(__state, connector, new_connector_state, __i) \
- 	for ((__i) = 0;								\
--	     (__i) < (__state)->num_connector &&				\
--	     ((connector) = (__state)->connectors[__i].ptr,			\
--	     (new_connector_state) = (__state)->connectors[__i].new_state, 1); 	\
--	     (__i)++)							\
--		for_each_if (connector)
--
--/**
-- * for_each_crtc_in_state - iterate over all connectors in an atomic update
-- * @__state: &struct drm_atomic_state pointer
-- * @crtc: &struct drm_crtc iteration cursor
-- * @crtc_state: &struct drm_crtc_state iteration cursor
-- * @__i: int iteration cursor, for macro-internal use
-- *
-- * This iterates over all CRTCs in an atomic update. Note that before the
-- * software state is committed (by calling drm_atomic_helper_swap_state(), this
-- * points to the new state, while afterwards it points to the old state. Due to
-- * this tricky confusion this macro is deprecated.
-- *
-- * FIXME:
-- *
-- * Replace all usage of this with one of the explicit iterators below and then
-- * remove this macro.
-- */
--#define for_each_crtc_in_state(__state, crtc, crtc_state, __i)	\
--	for ((__i) = 0;						\
--	     (__i) < (__state)->dev->mode_config.num_crtc &&	\
--	     ((crtc) = (__state)->crtcs[__i].ptr,			\
--	     (crtc_state) = (__state)->crtcs[__i].state, 1);	\
--	     (__i)++)						\
--		for_each_if (crtc_state)
-+	     (__i) < (__state)->num_connector;					\
-+	     (__i)++)								\
-+		for_each_if ((__state)->connectors[__i].ptr &&			\
-+			     ((connector) = (__state)->connectors[__i].ptr,	\
-+			     (new_connector_state) = (__state)->connectors[__i].new_state, 1))
- 
- /**
-  * for_each_oldnew_crtc_in_state - iterate over all CRTCs in an atomic update
-@@ -681,12 +646,12 @@ void drm_state_dump(struct drm_device *d
-  */
- #define for_each_oldnew_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
- 	for ((__i) = 0;							\
--	     (__i) < (__state)->dev->mode_config.num_crtc &&		\
--	     ((crtc) = (__state)->crtcs[__i].ptr,			\
--	     (old_crtc_state) = (__state)->crtcs[__i].old_state,	\
--	     (new_crtc_state) = (__state)->crtcs[__i].new_state, 1);	\
-+	     (__i) < (__state)->dev->mode_config.num_crtc;		\
- 	     (__i)++)							\
--		for_each_if (crtc)
-+		for_each_if ((__state)->crtcs[__i].ptr &&		\
-+			     ((crtc) = (__state)->crtcs[__i].ptr,	\
-+			     (old_crtc_state) = (__state)->crtcs[__i].old_state, \
-+			     (new_crtc_state) = (__state)->crtcs[__i].new_state, 1))
- 
- /**
-  * for_each_old_crtc_in_state - iterate over all CRTCs in an atomic update
-@@ -701,11 +666,11 @@ void drm_state_dump(struct drm_device *d
-  */
- #define for_each_old_crtc_in_state(__state, crtc, old_crtc_state, __i)	\
- 	for ((__i) = 0;							\
--	     (__i) < (__state)->dev->mode_config.num_crtc &&		\
--	     ((crtc) = (__state)->crtcs[__i].ptr,			\
--	     (old_crtc_state) = (__state)->crtcs[__i].old_state, 1);	\
-+	     (__i) < (__state)->dev->mode_config.num_crtc;		\
- 	     (__i)++)							\
--		for_each_if (crtc)
-+		for_each_if ((__state)->crtcs[__i].ptr &&		\
-+			     ((crtc) = (__state)->crtcs[__i].ptr,	\
-+			     (old_crtc_state) = (__state)->crtcs[__i].old_state, 1))
- 
- /**
-  * for_each_new_crtc_in_state - iterate over all CRTCs in an atomic update
-@@ -720,36 +685,11 @@ void drm_state_dump(struct drm_device *d
-  */
- #define for_each_new_crtc_in_state(__state, crtc, new_crtc_state, __i)	\
- 	for ((__i) = 0;							\
--	     (__i) < (__state)->dev->mode_config.num_crtc &&		\
--	     ((crtc) = (__state)->crtcs[__i].ptr,			\
--	     (new_crtc_state) = (__state)->crtcs[__i].new_state, 1);	\
-+	     (__i) < (__state)->dev->mode_config.num_crtc;		\
- 	     (__i)++)							\
--		for_each_if (crtc)
--
--/**
-- * for_each_plane_in_state - iterate over all planes in an atomic update
-- * @__state: &struct drm_atomic_state pointer
-- * @plane: &struct drm_plane iteration cursor
-- * @plane_state: &struct drm_plane_state iteration cursor
-- * @__i: int iteration cursor, for macro-internal use
-- *
-- * This iterates over all planes in an atomic update. Note that before the
-- * software state is committed (by calling drm_atomic_helper_swap_state(), this
-- * points to the new state, while afterwards it points to the old state. Due to
-- * this tricky confusion this macro is deprecated.
-- *
-- * FIXME:
-- *
-- * Replace all usage of this with one of the explicit iterators below and then
-- * remove this macro.
-- */
--#define for_each_plane_in_state(__state, plane, plane_state, __i)		\
--	for ((__i) = 0;							\
--	     (__i) < (__state)->dev->mode_config.num_total_plane &&	\
--	     ((plane) = (__state)->planes[__i].ptr,				\
--	     (plane_state) = (__state)->planes[__i].state, 1);		\
--	     (__i)++)							\
--		for_each_if (plane_state)
-+		for_each_if ((__state)->crtcs[__i].ptr &&		\
-+			     ((crtc) = (__state)->crtcs[__i].ptr,	\
-+			     (new_crtc_state) = (__state)->crtcs[__i].new_state, 1))
- 
- /**
-  * for_each_oldnew_plane_in_state - iterate over all planes in an atomic update
-@@ -765,12 +705,12 @@ void drm_state_dump(struct drm_device *d
-  */
- #define for_each_oldnew_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
- 	for ((__i) = 0;							\
--	     (__i) < (__state)->dev->mode_config.num_total_plane &&	\
--	     ((plane) = (__state)->planes[__i].ptr,			\
--	     (old_plane_state) = (__state)->planes[__i].old_state,	\
--	     (new_plane_state) = (__state)->planes[__i].new_state, 1);	\
-+	     (__i) < (__state)->dev->mode_config.num_total_plane;	\
- 	     (__i)++)							\
--		for_each_if (plane)
-+		for_each_if ((__state)->planes[__i].ptr &&		\
-+			     ((plane) = (__state)->planes[__i].ptr,	\
-+			      (old_plane_state) = (__state)->planes[__i].old_state,\
-+			      (new_plane_state) = (__state)->planes[__i].new_state, 1))
- 
- /**
-  * for_each_old_plane_in_state - iterate over all planes in an atomic update
-@@ -785,12 +725,11 @@ void drm_state_dump(struct drm_device *d
-  */
- #define for_each_old_plane_in_state(__state, plane, old_plane_state, __i) \
- 	for ((__i) = 0;							\
--	     (__i) < (__state)->dev->mode_config.num_total_plane &&	\
--	     ((plane) = (__state)->planes[__i].ptr,			\
--	     (old_plane_state) = (__state)->planes[__i].old_state, 1);	\
-+	     (__i) < (__state)->dev->mode_config.num_total_plane;	\
- 	     (__i)++)							\
--		for_each_if (plane)
--
-+		for_each_if ((__state)->planes[__i].ptr &&		\
-+			     ((plane) = (__state)->planes[__i].ptr,	\
-+			      (old_plane_state) = (__state)->planes[__i].old_state, 1))
- /**
-  * for_each_new_plane_in_state - iterate over all planes in an atomic update
-  * @__state: &struct drm_atomic_state pointer
-@@ -804,11 +743,11 @@ void drm_state_dump(struct drm_device *d
-  */
- #define for_each_new_plane_in_state(__state, plane, new_plane_state, __i) \
- 	for ((__i) = 0;							\
--	     (__i) < (__state)->dev->mode_config.num_total_plane &&	\
--	     ((plane) = (__state)->planes[__i].ptr,			\
--	     (new_plane_state) = (__state)->planes[__i].new_state, 1);	\
-+	     (__i) < (__state)->dev->mode_config.num_total_plane;	\
- 	     (__i)++)							\
--		for_each_if (plane)
-+		for_each_if ((__state)->planes[__i].ptr &&		\
-+			     ((plane) = (__state)->planes[__i].ptr,	\
-+			      (new_plane_state) = (__state)->planes[__i].new_state, 1))
- 
- /**
-  * for_each_oldnew_private_obj_in_state - iterate over all private objects in an atomic update
-@@ -828,8 +767,7 @@ void drm_state_dump(struct drm_device *d
- 		     ((obj) = (__state)->private_objs[__i].ptr, \
- 		      (old_obj_state) = (__state)->private_objs[__i].old_state,	\
- 		      (new_obj_state) = (__state)->private_objs[__i].new_state, 1); \
--	     (__i)++) \
--		for_each_if (obj)
-+	     (__i)++)
- 
- /**
-  * for_each_old_private_obj_in_state - iterate over all private objects in an atomic update
-@@ -847,8 +785,7 @@ void drm_state_dump(struct drm_device *d
- 	     (__i) < (__state)->num_private_objs && \
- 		     ((obj) = (__state)->private_objs[__i].ptr, \
- 		      (old_obj_state) = (__state)->private_objs[__i].old_state, 1); \
--	     (__i)++) \
--		for_each_if (obj)
-+	     (__i)++)
- 
- /**
-  * for_each_new_private_obj_in_state - iterate over all private objects in an atomic update
-@@ -866,8 +803,7 @@ void drm_state_dump(struct drm_device *d
- 	     (__i) < (__state)->num_private_objs && \
- 		     ((obj) = (__state)->private_objs[__i].ptr, \
- 		      (new_obj_state) = (__state)->private_objs[__i].new_state, 1); \
--	     (__i)++) \
--		for_each_if (obj)
-+	     (__i)++)
- 
- /**
-  * drm_atomic_crtc_needs_modeset - compute combined modeset need
---- linux-4.14/include/drm/drm_bridge.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_bridge.h	2017-12-14 06:39:58.528903646 +0100
-@@ -245,7 +245,7 @@ struct drm_bridge {
- 	void *driver_private;
- };
- 
--int drm_bridge_add(struct drm_bridge *bridge);
-+void drm_bridge_add(struct drm_bridge *bridge);
- void drm_bridge_remove(struct drm_bridge *bridge);
- struct drm_bridge *of_drm_find_bridge(struct device_node *np);
- int drm_bridge_attach(struct drm_encoder *encoder, struct drm_bridge *bridge,
---- linux-4.14/include/drm/drm_connector.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_connector.h	2017-12-14 06:39:58.528903646 +0100
-@@ -347,6 +347,13 @@ struct drm_connector_state {
- 
- 	struct drm_atomic_state *state;
- 
-+	/**
-+	 * @commit: Tracks the pending commit to prevent use-after-free conditions.
-+	 *
-+	 * Is only set when @crtc is NULL.
-+	 */
-+	struct drm_crtc_commit *commit;
-+
- 	struct drm_tv_connector_state tv;
- 
- 	/**
-@@ -888,8 +895,7 @@ struct drm_connector {
- 	 * This is protected by @drm_mode_config.connection_mutex. Note that
- 	 * nonblocking atomic commits access the current connector state without
- 	 * taking locks. Either by going through the &struct drm_atomic_state
--	 * pointers, see for_each_connector_in_state(),
--	 * for_each_oldnew_connector_in_state(),
-+	 * pointers, see for_each_oldnew_connector_in_state(),
- 	 * for_each_old_connector_in_state() and
- 	 * for_each_new_connector_in_state(). Or through careful ordering of
- 	 * atomic commit operations as implemented in the atomic helpers, see
-@@ -933,10 +939,11 @@ static inline unsigned drm_connector_ind
-  * add takes a reference to it.
-  */
- static inline struct drm_connector *drm_connector_lookup(struct drm_device *dev,
-+		struct drm_file *file_priv,
- 		uint32_t id)
- {
- 	struct drm_mode_object *mo;
--	mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_CONNECTOR);
-+	mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_CONNECTOR);
- 	return mo ? obj_to_connector(mo) : NULL;
- }
- 
---- linux-4.14/include/drm/drm_crtc.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_crtc.h	2017-12-14 06:39:58.528903646 +0100
-@@ -253,6 +253,15 @@ struct drm_crtc_state {
- 	 */
- 	struct drm_pending_vblank_event *event;
- 
-+	/**
-+	 * @commit:
-+	 *
-+	 * This tracks how the commit for this update proceeds through the
-+	 * various phases. This is never cleared, except when we destroy the
-+	 * state, so that subsequent commits can synchronize with previous ones.
-+	 */
-+	struct drm_crtc_commit *commit;
-+
- 	struct drm_atomic_state *state;
- };
- 
-@@ -797,10 +806,10 @@ struct drm_crtc {
- 	 * This is protected by @mutex. Note that nonblocking atomic commits
- 	 * access the current CRTC state without taking locks. Either by going
- 	 * through the &struct drm_atomic_state pointers, see
--	 * for_each_crtc_in_state(), for_each_oldnew_crtc_in_state(),
--	 * for_each_old_crtc_in_state() and for_each_new_crtc_in_state(). Or
--	 * through careful ordering of atomic commit operations as implemented
--	 * in the atomic helpers, see &struct drm_crtc_commit.
-+	 * for_each_oldnew_crtc_in_state(), for_each_old_crtc_in_state() and
-+	 * for_each_new_crtc_in_state(). Or through careful ordering of atomic
-+	 * commit operations as implemented in the atomic helpers, see
-+	 * &struct drm_crtc_commit.
- 	 */
- 	struct drm_crtc_state *state;
- 
-@@ -808,10 +817,16 @@ struct drm_crtc {
- 	 * @commit_list:
- 	 *
- 	 * List of &drm_crtc_commit structures tracking pending commits.
--	 * Protected by @commit_lock. This list doesn't hold its own full
--	 * reference, but burrows it from the ongoing commit. Commit entries
--	 * must be removed from this list once the commit is fully completed,
--	 * but before it's correspoding &drm_atomic_state gets destroyed.
-+	 * Protected by @commit_lock. This list holds its own full reference,
-+	 * as does the ongoing commit.
-+	 *
-+	 * "Note that the commit for a state change is also tracked in
-+	 * &drm_crtc_state.commit. For accessing the immediately preceding
-+	 * commit in an atomic update it is recommended to just use that
-+	 * pointer in the old CRTC state, since accessing that doesn't need
-+	 * any locking or list-walking. @commit_list should only be used to
-+	 * stall for framebuffer cleanup that's signalled through
-+	 * &drm_crtc_commit.cleanup_done."
- 	 */
- 	struct list_head commit_list;
- 
-@@ -944,10 +959,11 @@ struct drm_crtc *drm_crtc_from_index(str
-  * userspace interface should be done using &drm_property.
-  */
- static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev,
--	uint32_t id)
-+		struct drm_file *file_priv,
-+		uint32_t id)
- {
- 	struct drm_mode_object *mo;
--	mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_CRTC);
-+	mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_CRTC);
- 	return mo ? obj_to_crtc(mo) : NULL;
- }
- 
---- linux-4.14/include/drm/drm_dp_helper.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_dp_helper.h	2017-12-14 06:39:58.529903647 +0100
-@@ -510,6 +510,8 @@
- # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK   0xc0
- # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
- 
-+#define DP_ADJUST_REQUEST_POST_CURSOR2      0x20c
-+
- #define DP_TEST_REQUEST			    0x218
- # define DP_TEST_LINK_TRAINING		    (1 << 0)
- # define DP_TEST_LINK_VIDEO_PATTERN	    (1 << 1)
-@@ -582,6 +584,8 @@
- 
- #define DP_TEST_REFRESH_RATE_NUMERATOR      0x234
- 
-+#define DP_TEST_MISC0                       0x232
-+
- #define DP_TEST_CRC_R_CR		    0x240
- #define DP_TEST_CRC_G_Y			    0x242
- #define DP_TEST_CRC_B_CB		    0x244
-@@ -590,6 +594,18 @@
- # define DP_TEST_CRC_SUPPORTED		    (1 << 5)
- # define DP_TEST_COUNT_MASK		    0xf
- 
-+#define DP_TEST_PHY_PATTERN                 0x248
-+#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
-+#define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
-+#define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
-+#define	DP_TEST_80BIT_CUSTOM_PATTERN_31_24  0x253
-+#define	DP_TEST_80BIT_CUSTOM_PATTERN_39_32  0x254
-+#define	DP_TEST_80BIT_CUSTOM_PATTERN_47_40  0x255
-+#define	DP_TEST_80BIT_CUSTOM_PATTERN_55_48  0x256
-+#define	DP_TEST_80BIT_CUSTOM_PATTERN_63_56  0x257
-+#define	DP_TEST_80BIT_CUSTOM_PATTERN_71_64  0x258
-+#define	DP_TEST_80BIT_CUSTOM_PATTERN_79_72  0x259
-+
- #define DP_TEST_RESPONSE		    0x260
- # define DP_TEST_ACK			    (1 << 0)
- # define DP_TEST_NAK			    (1 << 1)
-@@ -611,6 +627,7 @@
- #define DP_SINK_OUI			    0x400
- #define DP_BRANCH_OUI			    0x500
- #define DP_BRANCH_ID                        0x503
-+#define DP_BRANCH_REVISION_START            0x509
- #define DP_BRANCH_HW_REV                    0x509
- #define DP_BRANCH_SW_REV                    0x50A
- 
-@@ -735,9 +752,23 @@
- # define DP_PSR_SINK_INTERNAL_ERROR         7
- # define DP_PSR_SINK_STATE_MASK             0x07
- 
-+#define DP_SYNCHRONIZATION_LATENCY_IN_SINK		0x2009 /* edp 1.4 */
-+# define DP_MAX_RESYNC_FRAME_COUNT_MASK			(0xf << 0)
-+# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT		0
-+# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK	(0xf << 4)
-+# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT	4
-+
- #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
- # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)
- 
-+#define DP_LANE0_1_STATUS_ESI                  0x200c /* status same as 0x202 */
-+#define DP_LANE2_3_STATUS_ESI                  0x200d /* status same as 0x203 */
-+#define DP_LANE_ALIGN_STATUS_UPDATED_ESI       0x200e /* status same as 0x204 */
-+#define DP_SINK_STATUS_ESI                     0x200f /* status same as 0x205 */
-+
-+#define DP_DP13_DPCD_REV                    0x2200
-+#define DP_DP13_MAX_LINK_RATE               0x2201
-+
- #define DP_DPRX_FEATURE_ENUMERATION_LIST    0x2210  /* DP 1.3 */
- # define DP_GTC_CAP					(1 << 0)  /* DP 1.3 */
- # define DP_SST_SPLIT_SDP_CAP				(1 << 1)  /* DP 1.4 */
-@@ -871,6 +902,18 @@ void drm_dp_link_train_channel_eq_delay(
- u8 drm_dp_link_rate_to_bw_code(int link_rate);
- int drm_dp_bw_code_to_link_rate(u8 link_bw);
- 
-+#define DP_SDP_AUDIO_TIMESTAMP		0x01
-+#define DP_SDP_AUDIO_STREAM		0x02
-+#define DP_SDP_EXTENSION		0x04 /* DP 1.1 */
-+#define DP_SDP_AUDIO_COPYMANAGEMENT	0x05 /* DP 1.2 */
-+#define DP_SDP_ISRC			0x06 /* DP 1.2 */
-+#define DP_SDP_VSC			0x07 /* DP 1.2 */
-+#define DP_SDP_CAMERA_GENERIC(i)	(0x08 + (i)) /* 0-7, DP 1.3 */
-+#define DP_SDP_PPS			0x10 /* DP 1.4 */
-+#define DP_SDP_VSC_EXT_VESA		0x20 /* DP 1.4 */
-+#define DP_SDP_VSC_EXT_CEA		0x21 /* DP 1.4 */
-+/* 0x80+ CEA-861 infoframe types */
-+
- struct edp_sdp_header {
- 	u8 HB0; /* Secondary Data Packet ID */
- 	u8 HB1; /* Secondary Data Packet Type */
---- linux-4.14/include/drm/drm_dp_mst_helper.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_dp_mst_helper.h	2017-12-14 06:39:58.529903647 +0100
-@@ -631,5 +631,7 @@ int drm_dp_atomic_find_vcpi_slots(struct
- int drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state,
- 				     struct drm_dp_mst_topology_mgr *mgr,
- 				     int slots);
-+int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr,
-+				 struct drm_dp_mst_port *port, bool power_up);
- 
- #endif
---- linux-4.14/include/drm/drm_drv.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_drv.h	2017-12-14 06:39:58.529903647 +0100
-@@ -155,7 +155,7 @@ struct drm_driver {
- 	 * reverse order of the initialization.  Similarly to the load
- 	 * hook, this handler is deprecated and its usage should be
- 	 * dropped in favor of an open-coded teardown function at the
--	 * driver layer.  See drm_dev_unregister() and drm_dev_unref()
-+	 * driver layer.  See drm_dev_unregister() and drm_dev_put()
- 	 * for the proper way to remove a &struct drm_device.
- 	 *
- 	 * The unload() hook is called right after unregistering
-@@ -324,7 +324,7 @@ struct drm_driver {
- 	 */
- 	bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe,
- 				     int *max_error,
--				     struct timeval *vblank_time,
-+				     ktime_t *vblank_time,
- 				     bool in_vblank_irq);
- 
- 	/**
-@@ -611,7 +611,8 @@ struct drm_device *drm_dev_alloc(struct
- int drm_dev_register(struct drm_device *dev, unsigned long flags);
- void drm_dev_unregister(struct drm_device *dev);
- 
--void drm_dev_ref(struct drm_device *dev);
-+void drm_dev_get(struct drm_device *dev);
-+void drm_dev_put(struct drm_device *dev);
- void drm_dev_unref(struct drm_device *dev);
- void drm_put_dev(struct drm_device *dev);
- void drm_dev_unplug(struct drm_device *dev);
---- linux-4.14/include/drm/drm_edid.h.0130~	2017-12-14 06:39:58.290903480 +0100
-+++ linux-4.14/include/drm/drm_edid.h	2017-12-14 06:39:58.529903647 +0100
-@@ -341,6 +341,8 @@ int drm_av_sync_delay(struct drm_connect
- 
- #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
- struct edid *drm_load_edid_firmware(struct drm_connector *connector);
-+int __drm_set_edid_firmware_path(const char *path);
-+int __drm_get_edid_firmware_path(char *buf, size_t bufsize);
- #else
- static inline struct edid *
- drm_load_edid_firmware(struct drm_connector *connector)
---- linux-4.14/include/drm/drm_encoder.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_encoder.h	2017-12-14 06:39:58.529903647 +0100
-@@ -214,11 +214,12 @@ static inline bool drm_encoder_crtc_ok(s
-  * drm_mode_object_find().
-  */
- static inline struct drm_encoder *drm_encoder_find(struct drm_device *dev,
-+						   struct drm_file *file_priv,
- 						   uint32_t id)
- {
- 	struct drm_mode_object *mo;
- 
--	mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_ENCODER);
-+	mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_ENCODER);
- 
- 	return mo ? obj_to_encoder(mo) : NULL;
- }
---- linux-4.14/include/drm/drm_fb_cma_helper.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_fb_cma_helper.h	2017-12-14 06:39:58.529903647 +0100
-@@ -29,16 +29,6 @@ void drm_fbdev_cma_set_suspend(struct dr
- void drm_fbdev_cma_set_suspend_unlocked(struct drm_fbdev_cma *fbdev_cma,
- 					bool state);
- 
--void drm_fb_cma_destroy(struct drm_framebuffer *fb);
--int drm_fb_cma_create_handle(struct drm_framebuffer *fb,
--	struct drm_file *file_priv, unsigned int *handle);
--
--struct drm_framebuffer *drm_fb_cma_create_with_funcs(struct drm_device *dev,
--	struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd,
--	const struct drm_framebuffer_funcs *funcs);
--struct drm_framebuffer *drm_fb_cma_create(struct drm_device *dev,
--	struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd);
--
- struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct drm_framebuffer *fb,
- 	unsigned int plane);
- 
-@@ -46,9 +36,6 @@ dma_addr_t drm_fb_cma_get_gem_addr(struc
- 				   struct drm_plane_state *state,
- 				   unsigned int plane);
- 
--int drm_fb_cma_prepare_fb(struct drm_plane *plane,
--			  struct drm_plane_state *state);
--
- #ifdef CONFIG_DEBUG_FS
- struct seq_file;
- 
---- linux-4.14/include/drm/drm_framebuffer.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_framebuffer.h	2017-12-14 06:39:58.529903647 +0100
-@@ -205,6 +205,7 @@ int drm_framebuffer_init(struct drm_devi
- 			 struct drm_framebuffer *fb,
- 			 const struct drm_framebuffer_funcs *funcs);
- struct drm_framebuffer *drm_framebuffer_lookup(struct drm_device *dev,
-+					       struct drm_file *file_priv,
- 					       uint32_t id);
- void drm_framebuffer_remove(struct drm_framebuffer *fb);
- void drm_framebuffer_cleanup(struct drm_framebuffer *fb);
---- linux-4.14/include/drm/drm_gem_framebuffer_helper.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_gem_framebuffer_helper.h	2017-12-14 06:39:58.529903647 +0100
-@@ -2,8 +2,8 @@
- #define __DRM_GEM_FB_HELPER_H__
- 
- struct drm_device;
--struct drm_file;
- struct drm_fb_helper_surface_size;
-+struct drm_file;
- struct drm_framebuffer;
- struct drm_framebuffer_funcs;
- struct drm_gem_object;
---- linux-4.14/include/drm/drm_mode_object.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_mode_object.h	2017-12-14 06:39:58.529903647 +0100
-@@ -27,6 +27,7 @@
- struct drm_object_properties;
- struct drm_property;
- struct drm_device;
-+struct drm_file;
- 
- /**
-  * struct drm_mode_object - base structure for modeset objects
-@@ -113,6 +114,7 @@ struct drm_object_properties {
- 	}
- 
- struct drm_mode_object *drm_mode_object_find(struct drm_device *dev,
-+					     struct drm_file *file_priv,
- 					     uint32_t id, uint32_t type);
- void drm_mode_object_get(struct drm_mode_object *obj);
- void drm_mode_object_put(struct drm_mode_object *obj);
---- linux-4.14/include/drm/drm_modeset_helper_vtables.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_modeset_helper_vtables.h	2017-12-14 06:39:58.529903647 +0100
-@@ -314,7 +314,7 @@ struct drm_crtc_helper_funcs {
- 	 * implementation in drm_atomic_helper_check().
- 	 *
- 	 * When using drm_atomic_helper_check_planes() this hook is called
--	 * after the &drm_plane_helper_funcs.atomc_check hook for planes, which
-+	 * after the &drm_plane_helper_funcs.atomic_check hook for planes, which
- 	 * allows drivers to assign shared resources requested by planes in this
- 	 * callback here. For more complicated dependencies the driver can call
- 	 * the provided check helpers multiple times until the computed state
---- linux-4.14/include/drm/drm_modeset_lock.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_modeset_lock.h	2017-12-14 06:39:58.529903647 +0100
-@@ -34,6 +34,7 @@ struct drm_modeset_lock;
-  * @contended: used internally for -EDEADLK handling
-  * @locked: list of held locks
-  * @trylock_only: trylock mode used in atomic contexts/panic notifiers
-+ * @interruptible: whether interruptible locking should be used.
-  *
-  * Each thread competing for a set of locks must use one acquire
-  * ctx.  And if any lock fxn returns -EDEADLK, it must backoff and
-@@ -59,6 +60,9 @@ struct drm_modeset_acquire_ctx {
- 	 * Trylock mode, use only for panic handlers!
- 	 */
- 	bool trylock_only;
-+
-+	/* Perform interruptible waits on this context. */
-+	bool interruptible;
- };
- 
- /**
-@@ -82,12 +86,13 @@ struct drm_modeset_lock {
- 	struct list_head head;
- };
- 
-+#define DRM_MODESET_ACQUIRE_INTERRUPTIBLE BIT(0)
-+
- void drm_modeset_acquire_init(struct drm_modeset_acquire_ctx *ctx,
- 		uint32_t flags);
- void drm_modeset_acquire_fini(struct drm_modeset_acquire_ctx *ctx);
- void drm_modeset_drop_locks(struct drm_modeset_acquire_ctx *ctx);
--void drm_modeset_backoff(struct drm_modeset_acquire_ctx *ctx);
--int drm_modeset_backoff_interruptible(struct drm_modeset_acquire_ctx *ctx);
-+int drm_modeset_backoff(struct drm_modeset_acquire_ctx *ctx);
- 
- void drm_modeset_lock_init(struct drm_modeset_lock *lock);
- 
-@@ -111,8 +116,7 @@ static inline bool drm_modeset_is_locked
- 
- int drm_modeset_lock(struct drm_modeset_lock *lock,
- 		struct drm_modeset_acquire_ctx *ctx);
--int drm_modeset_lock_interruptible(struct drm_modeset_lock *lock,
--		struct drm_modeset_acquire_ctx *ctx);
-+int __must_check drm_modeset_lock_single_interruptible(struct drm_modeset_lock *lock);
- void drm_modeset_unlock(struct drm_modeset_lock *lock);
- 
- struct drm_device;
---- linux-4.14/include/drm/drm_of.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_of.h	2017-12-14 06:39:58.529903647 +0100
-@@ -3,6 +3,9 @@
- #define __DRM_OF_H__
- 
- #include <linux/of_graph.h>
-+#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DRM_PANEL_BRIDGE)
-+#include <drm/drm_bridge.h>
-+#endif
- 
- struct component_master_ops;
- struct component_match;
-@@ -68,6 +71,34 @@ static inline int drm_of_find_panel_or_b
- }
- #endif
- 
-+/*
-+ * drm_of_panel_bridge_remove - remove panel bridge
-+ * @np: device tree node containing panel bridge output ports
-+ *
-+ * Remove the panel bridge of a given DT node's port and endpoint number
-+ *
-+ * Returns zero if successful, or one of the standard error codes if it fails.
-+ */
-+static inline int drm_of_panel_bridge_remove(const struct device_node *np,
-+					     int port, int endpoint)
-+{
-+#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DRM_PANEL_BRIDGE)
-+	struct drm_bridge *bridge;
-+	struct device_node *remote;
-+
-+	remote = of_graph_get_remote_node(np, port, endpoint);
-+	if (!remote)
-+		return -ENODEV;
-+
-+	bridge = of_drm_find_bridge(remote);
-+	drm_panel_bridge_remove(bridge);
-+
-+	return 0;
-+#else
-+	return -EINVAL;
-+#endif
-+}
-+
- static inline int drm_of_encoder_active_endpoint_id(struct device_node *node,
- 						    struct drm_encoder *encoder)
- {
---- linux-4.14/include/drm/drm_plane.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_plane.h	2017-12-14 06:39:58.529903647 +0100
-@@ -123,6 +123,14 @@ struct drm_plane_state {
- 	 */
- 	bool visible;
- 
-+	/**
-+	 * @commit: Tracks the pending commit to prevent use-after-free conditions,
-+	 * and for async plane updates.
-+	 *
-+	 * May be NULL.
-+	 */
-+	struct drm_crtc_commit *commit;
-+
- 	struct drm_atomic_state *state;
- };
- 
-@@ -531,10 +539,10 @@ struct drm_plane {
- 	 * This is protected by @mutex. Note that nonblocking atomic commits
- 	 * access the current plane state without taking locks. Either by going
- 	 * through the &struct drm_atomic_state pointers, see
--	 * for_each_plane_in_state(), for_each_oldnew_plane_in_state(),
--	 * for_each_old_plane_in_state() and for_each_new_plane_in_state(). Or
--	 * through careful ordering of atomic commit operations as implemented
--	 * in the atomic helpers, see &struct drm_crtc_commit.
-+	 * for_each_oldnew_plane_in_state(), for_each_old_plane_in_state() and
-+	 * for_each_new_plane_in_state(). Or through careful ordering of atomic
-+	 * commit operations as implemented in the atomic helpers, see
-+	 * &struct drm_crtc_commit.
- 	 */
- 	struct drm_plane_state *state;
- 
-@@ -589,10 +597,11 @@ int drm_mode_plane_set_obj_prop(struct d
-  * drm_mode_object_find().
-  */
- static inline struct drm_plane *drm_plane_find(struct drm_device *dev,
-+		struct drm_file *file_priv,
- 		uint32_t id)
- {
- 	struct drm_mode_object *mo;
--	mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_PLANE);
-+	mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_PLANE);
- 	return mo ? obj_to_plane(mo) : NULL;
- }
- 
---- linux-4.14/include/drm/drm_property.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_property.h	2017-12-14 06:39:58.530903647 +0100
-@@ -312,10 +312,11 @@ drm_property_unreference_blob(struct drm
-  * This function looks up the property object specified by id and returns it.
-  */
- static inline struct drm_property *drm_property_find(struct drm_device *dev,
-+						     struct drm_file *file_priv,
- 						     uint32_t id)
- {
- 	struct drm_mode_object *mo;
--	mo = drm_mode_object_find(dev, id, DRM_MODE_OBJECT_PROPERTY);
-+	mo = drm_mode_object_find(dev, file_priv, id, DRM_MODE_OBJECT_PROPERTY);
- 	return mo ? obj_to_property(mo) : NULL;
- }
- 
---- linux-4.14/include/drm/drm_syncobj.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_syncobj.h	2017-12-14 06:39:58.530903647 +0100
-@@ -136,5 +136,10 @@ int drm_syncobj_find_fence(struct drm_fi
- 			   u32 handle,
- 			   struct dma_fence **fence);
- void drm_syncobj_free(struct kref *kref);
-+int drm_syncobj_create(struct drm_syncobj **out_syncobj, uint32_t flags,
-+		       struct dma_fence *fence);
-+int drm_syncobj_get_handle(struct drm_file *file_private,
-+			   struct drm_syncobj *syncobj, u32 *handle);
-+int drm_syncobj_get_fd(struct drm_syncobj *syncobj, int *p_fd);
- 
- #endif
---- linux-4.14/include/drm/drm_vblank.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/drm_vblank.h	2017-12-14 06:39:58.530903647 +0100
-@@ -92,7 +92,7 @@ struct drm_vblank_crtc {
- 	/**
- 	 * @time: Vblank timestamp corresponding to @count.
- 	 */
--	struct timeval time;
-+	ktime_t time;
- 
- 	/**
- 	 * @refcount: Number of users/waiters of the vblank interrupt. Only when
-@@ -154,7 +154,7 @@ struct drm_vblank_crtc {
- int drm_vblank_init(struct drm_device *dev, unsigned int num_crtcs);
- u32 drm_crtc_vblank_count(struct drm_crtc *crtc);
- u32 drm_crtc_vblank_count_and_time(struct drm_crtc *crtc,
--				   struct timeval *vblanktime);
-+				   ktime_t *vblanktime);
- void drm_crtc_send_vblank_event(struct drm_crtc *crtc,
- 			       struct drm_pending_vblank_event *e);
- void drm_crtc_arm_vblank_event(struct drm_crtc *crtc,
-@@ -172,7 +172,7 @@ u32 drm_crtc_accurate_vblank_count(struc
- 
- bool drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev,
- 					   unsigned int pipe, int *max_error,
--					   struct timeval *vblank_time,
-+					   ktime_t *vblank_time,
- 					   bool in_vblank_irq);
- void drm_calc_timestamping_constants(struct drm_crtc *crtc,
- 				     const struct drm_display_mode *mode);
---- linux-4.14/include/drm/i915_pciids.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/i915_pciids.h	2017-12-14 06:39:58.530903647 +0100
-@@ -118,92 +118,125 @@
- #define INTEL_IRONLAKE_M_IDS(info) \
- 	INTEL_VGA_DEVICE(0x0046, info)
- 
--#define INTEL_SNB_D_IDS(info) \
-+#define INTEL_SNB_D_GT1_IDS(info) \
- 	INTEL_VGA_DEVICE(0x0102, info), \
--	INTEL_VGA_DEVICE(0x0112, info), \
--	INTEL_VGA_DEVICE(0x0122, info), \
- 	INTEL_VGA_DEVICE(0x010A, info)
- 
--#define INTEL_SNB_M_IDS(info) \
--	INTEL_VGA_DEVICE(0x0106, info), \
-+#define INTEL_SNB_D_GT2_IDS(info) \
-+	INTEL_VGA_DEVICE(0x0112, info), \
-+	INTEL_VGA_DEVICE(0x0122, info)
-+
-+#define INTEL_SNB_D_IDS(info) \
-+	INTEL_SNB_D_GT1_IDS(info), \
-+	INTEL_SNB_D_GT2_IDS(info)
-+
-+#define INTEL_SNB_M_GT1_IDS(info) \
-+	INTEL_VGA_DEVICE(0x0106, info)
-+
-+#define INTEL_SNB_M_GT2_IDS(info) \
- 	INTEL_VGA_DEVICE(0x0116, info), \
- 	INTEL_VGA_DEVICE(0x0126, info)
- 
-+#define INTEL_SNB_M_IDS(info) \
-+	INTEL_SNB_M_GT1_IDS(info), \
-+	INTEL_SNB_M_GT2_IDS(info)
-+
-+#define INTEL_IVB_M_GT1_IDS(info) \
-+	INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
-+
-+#define INTEL_IVB_M_GT2_IDS(info) \
-+	INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
-+
- #define INTEL_IVB_M_IDS(info) \
--	INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \
--	INTEL_VGA_DEVICE(0x0166, info)  /* GT2 mobile */
-+	INTEL_IVB_M_GT1_IDS(info), \
-+	INTEL_IVB_M_GT2_IDS(info)
- 
--#define INTEL_IVB_D_IDS(info) \
-+#define INTEL_IVB_D_GT1_IDS(info) \
- 	INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
-+	INTEL_VGA_DEVICE(0x015a, info)  /* GT1 server */
-+
-+#define INTEL_IVB_D_GT2_IDS(info) \
- 	INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
--	INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
- 	INTEL_VGA_DEVICE(0x016a, info)  /* GT2 server */
- 
-+#define INTEL_IVB_D_IDS(info) \
-+	INTEL_IVB_D_GT1_IDS(info), \
-+	INTEL_IVB_D_GT2_IDS(info)
-+
- #define INTEL_IVB_Q_IDS(info) \
- 	INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
- 
--#define INTEL_HSW_IDS(info) \
-+#define INTEL_HSW_GT1_IDS(info) \
- 	INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
--	INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
--	INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
- 	INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
--	INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
--	INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
- 	INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
--	INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
--	INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
- 	INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
--	INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
--	INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
- 	INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
--	INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
--	INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
- 	INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
--	INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
--	INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
- 	INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
--	INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
--	INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
- 	INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
--	INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
--	INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
- 	INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
--	INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
--	INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
- 	INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
--	INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
--	INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
- 	INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
--	INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
--	INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
- 	INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
--	INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
--	INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
- 	INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
--	INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
--	INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
- 	INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
--	INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
--	INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
- 	INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
--	INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
--	INTEL_VGA_DEVICE(0x0D2E, info),  /* CRW GT3 reserved */ \
- 	INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
-+	INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
-+	INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
-+	INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
-+	INTEL_VGA_DEVICE(0x0D06, info)  /* CRW GT1 mobile */
-+
-+#define INTEL_HSW_GT2_IDS(info) \
-+	INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
-+	INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
-+	INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
-+	INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
-+	INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
-+	INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
-+	INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
-+	INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
-+	INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
-+	INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
-+	INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
-+	INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
-+	INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
-+	INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
-+	INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
- 	INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
- 	INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
--	INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
- 	INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
--	INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
--	INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
- 	INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
--	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
--	INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
- 	INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
-+	INTEL_VGA_DEVICE(0x0D16, info)  /* CRW GT2 mobile */
-+
-+#define INTEL_HSW_GT3_IDS(info) \
-+	INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
-+	INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
-+	INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
-+	INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
-+	INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
-+	INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
-+	INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
-+	INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
-+	INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
-+	INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
-+	INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
-+	INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
-+	INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
-+	INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
-+	INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
-+	INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
-+	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
- 	INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
--	INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
--	INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
- 	INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
- 
-+#define INTEL_HSW_IDS(info) \
-+	INTEL_HSW_GT1_IDS(info), \
-+	INTEL_HSW_GT2_IDS(info), \
-+	INTEL_HSW_GT3_IDS(info)
-+
- #define INTEL_VLV_IDS(info) \
- 	INTEL_VGA_DEVICE(0x0f30, info), \
- 	INTEL_VGA_DEVICE(0x0f31, info), \
-@@ -212,17 +245,19 @@
- 	INTEL_VGA_DEVICE(0x0157, info), \
- 	INTEL_VGA_DEVICE(0x0155, info)
- 
--#define INTEL_BDW_GT12_IDS(info)  \
-+#define INTEL_BDW_GT1_IDS(info)  \
- 	INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
- 	INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
- 	INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
- 	INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
--	INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
-+	INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
-+	INTEL_VGA_DEVICE(0x160D, info)  /* GT1 Workstation */
-+
-+#define INTEL_BDW_GT2_IDS(info)  \
-+	INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */	\
- 	INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
- 	INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
--	INTEL_VGA_DEVICE(0x161E, info),  /* GT2 ULX */ \
--	INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
--	INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
-+	INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \
- 	INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
- 	INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */
- 
-@@ -243,7 +278,8 @@
- 	INTEL_VGA_DEVICE(0x163D, info)  /* Workstation */
- 
- #define INTEL_BDW_IDS(info) \
--	INTEL_BDW_GT12_IDS(info), \
-+	INTEL_BDW_GT1_IDS(info), \
-+	INTEL_BDW_GT2_IDS(info), \
- 	INTEL_BDW_GT3_IDS(info), \
- 	INTEL_BDW_RSVD_IDS(info)
- 
-@@ -303,7 +339,6 @@
- #define INTEL_KBL_GT1_IDS(info)	\
- 	INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
- 	INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
--	INTEL_VGA_DEVICE(0x5917, info), /* DT  GT1.5 */ \
- 	INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
- 	INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
- 	INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
-@@ -313,6 +348,7 @@
- 
- #define INTEL_KBL_GT2_IDS(info)	\
- 	INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
-+	INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
- 	INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
- 	INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
- 	INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
-@@ -335,20 +371,22 @@
- 	INTEL_KBL_GT4_IDS(info)
- 
- /* CFL S */
--#define INTEL_CFL_S_IDS(info) \
-+#define INTEL_CFL_S_GT1_IDS(info) \
- 	INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
--	INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
-+	INTEL_VGA_DEVICE(0x3E93, info)  /* SRV GT1 */
-+
-+#define INTEL_CFL_S_GT2_IDS(info) \
- 	INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
- 	INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
- 	INTEL_VGA_DEVICE(0x3E96, info)  /* SRV GT2 */
- 
- /* CFL H */
--#define INTEL_CFL_H_IDS(info) \
-+#define INTEL_CFL_H_GT2_IDS(info) \
- 	INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
- 	INTEL_VGA_DEVICE(0x3E94, info)  /* Halo GT2 */
- 
- /* CFL U */
--#define INTEL_CFL_U_IDS(info) \
-+#define INTEL_CFL_U_GT3_IDS(info) \
- 	INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
- 	INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
- 	INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \
---- linux-4.14/include/drm/ttm/ttm_bo_api.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/ttm/ttm_bo_api.h	2017-12-14 06:39:58.530903647 +0100
-@@ -224,7 +224,6 @@ struct ttm_buffer_object {
- 	 */
- 
- 	uint64_t offset; /* GPU address space is independent of CPU word size */
--	uint32_t cur_placement;
- 
- 	struct sg_table *sg;
- 
-@@ -288,8 +287,7 @@ ttm_bo_reference(struct ttm_buffer_objec
-  * Returns -EBUSY if no_wait is true and the buffer is busy.
-  * Returns -ERESTARTSYS if interrupted by a signal.
-  */
--extern int ttm_bo_wait(struct ttm_buffer_object *bo,
--		       bool interruptible, bool no_wait);
-+int ttm_bo_wait(struct ttm_buffer_object *bo, bool interruptible, bool no_wait);
- 
- /**
-  * ttm_bo_mem_compat - Check if proposed placement is compatible with a bo
-@@ -300,9 +298,8 @@ extern int ttm_bo_wait(struct ttm_buffer
-  *
-  * Returns true if the placement is compatible
-  */
--extern bool ttm_bo_mem_compat(struct ttm_placement *placement,
--			      struct ttm_mem_reg *mem,
--			      uint32_t *new_flags);
-+bool ttm_bo_mem_compat(struct ttm_placement *placement, struct ttm_mem_reg *mem,
-+		       uint32_t *new_flags);
- 
- /**
-  * ttm_bo_validate
-@@ -320,10 +317,10 @@ extern bool ttm_bo_mem_compat(struct ttm
-  * -EBUSY if no_wait is true and buffer busy.
-  * -ERESTARTSYS if interrupted by a signal.
-  */
--extern int ttm_bo_validate(struct ttm_buffer_object *bo,
--				struct ttm_placement *placement,
--				bool interruptible,
--				bool no_wait_gpu);
-+int ttm_bo_validate(struct ttm_buffer_object *bo,
-+		    struct ttm_placement *placement,
-+		    bool interruptible,
-+		    bool no_wait_gpu);
- 
- /**
-  * ttm_bo_unref
-@@ -332,7 +329,7 @@ extern int ttm_bo_validate(struct ttm_bu
-  *
-  * Unreference and clear a pointer to a buffer object.
-  */
--extern void ttm_bo_unref(struct ttm_buffer_object **bo);
-+void ttm_bo_unref(struct ttm_buffer_object **bo);
- 
- /**
-  * ttm_bo_add_to_lru
-@@ -344,7 +341,7 @@ extern void ttm_bo_unref(struct ttm_buff
-  * This function must be called with struct ttm_bo_global::lru_lock held, and
-  * is typically called immediately prior to unreserving a bo.
-  */
--extern void ttm_bo_add_to_lru(struct ttm_buffer_object *bo);
-+void ttm_bo_add_to_lru(struct ttm_buffer_object *bo);
- 
- /**
-  * ttm_bo_del_from_lru
-@@ -356,7 +353,7 @@ extern void ttm_bo_add_to_lru(struct ttm
-  * and is usually called just immediately after the bo has been reserved to
-  * avoid recursive reservation from lru lists.
-  */
--extern void ttm_bo_del_from_lru(struct ttm_buffer_object *bo);
-+void ttm_bo_del_from_lru(struct ttm_buffer_object *bo);
- 
- /**
-  * ttm_bo_move_to_lru_tail
-@@ -367,7 +364,7 @@ extern void ttm_bo_del_from_lru(struct t
-  * object. This function must be called with struct ttm_bo_global::lru_lock
-  * held, and is used to make a BO less likely to be considered for eviction.
-  */
--extern void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo);
-+void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo);
- 
- /**
-  * ttm_bo_lock_delayed_workqueue
-@@ -376,15 +373,14 @@ extern void ttm_bo_move_to_lru_tail(stru
-  * Returns
-  * True if the workqueue was queued at the time
-  */
--extern int ttm_bo_lock_delayed_workqueue(struct ttm_bo_device *bdev);
-+int ttm_bo_lock_delayed_workqueue(struct ttm_bo_device *bdev);
- 
- /**
-  * ttm_bo_unlock_delayed_workqueue
-  *
-  * Allows the delayed workqueue to run.
-  */
--extern void ttm_bo_unlock_delayed_workqueue(struct ttm_bo_device *bdev,
--					    int resched);
-+void ttm_bo_unlock_delayed_workqueue(struct ttm_bo_device *bdev, int resched);
- 
- /**
-  * ttm_bo_eviction_valuable
-@@ -411,8 +407,7 @@ bool ttm_bo_eviction_valuable(struct ttm
-  * -EBUSY if the buffer is busy and no_wait is true.
-  * -ERESTARTSYS if interrupted by a signal.
-  */
--extern int
--ttm_bo_synccpu_write_grab(struct ttm_buffer_object *bo, bool no_wait);
-+int ttm_bo_synccpu_write_grab(struct ttm_buffer_object *bo, bool no_wait);
- 
- /**
-  * ttm_bo_synccpu_write_release:
-@@ -421,7 +416,7 @@ ttm_bo_synccpu_write_grab(struct ttm_buf
-  *
-  * Releases a synccpu lock.
-  */
--extern void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo);
-+void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo);
- 
- /**
-  * ttm_bo_acc_size
-@@ -480,18 +475,18 @@ size_t ttm_bo_dma_acc_size(struct ttm_bo
-  * -ERESTARTSYS: Interrupted by signal while sleeping waiting for resources.
-  */
- 
--extern int ttm_bo_init_reserved(struct ttm_bo_device *bdev,
--				struct ttm_buffer_object *bo,
--				unsigned long size,
--				enum ttm_bo_type type,
--				struct ttm_placement *placement,
--				uint32_t page_alignment,
--				bool interrubtible,
--				struct file *persistent_swap_storage,
--				size_t acc_size,
--				struct sg_table *sg,
--				struct reservation_object *resv,
--				void (*destroy) (struct ttm_buffer_object *));
-+int ttm_bo_init_reserved(struct ttm_bo_device *bdev,
-+			 struct ttm_buffer_object *bo,
-+			 unsigned long size,
-+			 enum ttm_bo_type type,
-+			 struct ttm_placement *placement,
-+			 uint32_t page_alignment,
-+			 bool interrubtible,
-+			 struct file *persistent_swap_storage,
-+			 size_t acc_size,
-+			 struct sg_table *sg,
-+			 struct reservation_object *resv,
-+			 void (*destroy) (struct ttm_buffer_object *));
- 
- /**
-  * ttm_bo_init
-@@ -531,19 +526,13 @@ extern int ttm_bo_init_reserved(struct t
-  * -EINVAL: Invalid placement flags.
-  * -ERESTARTSYS: Interrupted by signal while sleeping waiting for resources.
-  */
--
--extern int ttm_bo_init(struct ttm_bo_device *bdev,
--			struct ttm_buffer_object *bo,
--			unsigned long size,
--			enum ttm_bo_type type,
--			struct ttm_placement *placement,
--			uint32_t page_alignment,
--			bool interrubtible,
--			struct file *persistent_swap_storage,
--			size_t acc_size,
--			struct sg_table *sg,
--			struct reservation_object *resv,
--			void (*destroy) (struct ttm_buffer_object *));
-+int ttm_bo_init(struct ttm_bo_device *bdev, struct ttm_buffer_object *bo,
-+		unsigned long size, enum ttm_bo_type type,
-+		struct ttm_placement *placement,
-+		uint32_t page_alignment, bool interrubtible,
-+		struct file *persistent_swap_storage, size_t acc_size,
-+		struct sg_table *sg, struct reservation_object *resv,
-+		void (*destroy) (struct ttm_buffer_object *));
- 
- /**
-  * ttm_bo_create
-@@ -569,15 +558,11 @@ extern int ttm_bo_init(struct ttm_bo_dev
-  * -EINVAL: Invalid placement flags.
-  * -ERESTARTSYS: Interrupted by signal while waiting for resources.
-  */
--
--extern int ttm_bo_create(struct ttm_bo_device *bdev,
--				unsigned long size,
--				enum ttm_bo_type type,
--				struct ttm_placement *placement,
--				uint32_t page_alignment,
--				bool interruptible,
--				struct file *persistent_swap_storage,
--				struct ttm_buffer_object **p_bo);
-+int ttm_bo_create(struct ttm_bo_device *bdev, unsigned long size,
-+		  enum ttm_bo_type type, struct ttm_placement *placement,
-+		  uint32_t page_alignment, bool interruptible,
-+		  struct file *persistent_swap_storage,
-+		  struct ttm_buffer_object **p_bo);
- 
- /**
-  * ttm_bo_init_mm
-@@ -594,9 +579,9 @@ extern int ttm_bo_create(struct ttm_bo_d
-  * -ENOMEM: Not enough memory.
-  * May also return driver-specified errors.
-  */
-+int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type,
-+		   unsigned long p_size);
- 
--extern int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type,
--				unsigned long p_size);
- /**
-  * ttm_bo_clean_mm
-  *
-@@ -623,8 +608,7 @@ extern int ttm_bo_init_mm(struct ttm_bo_
-  * -EINVAL: invalid or uninitialized memory type.
-  * -EBUSY: There are still buffers left in this memory type.
-  */
--
--extern int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type);
-+int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type);
- 
- /**
-  * ttm_bo_evict_mm
-@@ -644,8 +628,7 @@ extern int ttm_bo_clean_mm(struct ttm_bo
-  * -ERESTARTSYS: The call was interrupted by a signal while waiting to
-  * evict a buffer.
-  */
--
--extern int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned mem_type);
-+int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned mem_type);
- 
- /**
-  * ttm_kmap_obj_virtual
-@@ -658,7 +641,6 @@ extern int ttm_bo_evict_mm(struct ttm_bo
-  * If *is_iomem is 1 on return, the virtual address points to an io memory area,
-  * that should strictly be accessed by the iowriteXX() and similar functions.
-  */
--
- static inline void *ttm_kmap_obj_virtual(struct ttm_bo_kmap_obj *map,
- 					 bool *is_iomem)
- {
-@@ -682,9 +664,8 @@ static inline void *ttm_kmap_obj_virtual
-  * -ENOMEM: Out of memory.
-  * -EINVAL: Invalid range.
-  */
--
--extern int ttm_bo_kmap(struct ttm_buffer_object *bo, unsigned long start_page,
--		       unsigned long num_pages, struct ttm_bo_kmap_obj *map);
-+int ttm_bo_kmap(struct ttm_buffer_object *bo, unsigned long start_page,
-+		unsigned long num_pages, struct ttm_bo_kmap_obj *map);
- 
- /**
-  * ttm_bo_kunmap
-@@ -693,8 +674,7 @@ extern int ttm_bo_kmap(struct ttm_buffer
-  *
-  * Unmaps a kernel map set up by ttm_bo_kmap.
-  */
--
--extern void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map);
-+void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map);
- 
- /**
-  * ttm_fbdev_mmap - mmap fbdev memory backed by a ttm buffer object.
-@@ -706,9 +686,7 @@ extern void ttm_bo_kunmap(struct ttm_bo_
-  * This function is intended to be called by the fbdev mmap method
-  * if the fbdev address space is to be backed by a bo.
-  */
--
--extern int ttm_fbdev_mmap(struct vm_area_struct *vma,
--			  struct ttm_buffer_object *bo);
-+int ttm_fbdev_mmap(struct vm_area_struct *vma, struct ttm_buffer_object *bo);
- 
- /**
-  * ttm_bo_default_iomem_pfn - get a pfn for a page offset
-@@ -731,9 +709,8 @@ unsigned long ttm_bo_default_io_mem_pfn(
-  * This function is intended to be called by the device mmap method.
-  * if the device address space is to be backed by the bo manager.
-  */
--
--extern int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma,
--		       struct ttm_bo_device *bdev);
-+int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma,
-+		struct ttm_bo_device *bdev);
- 
- /**
-  * ttm_bo_io
-@@ -755,11 +732,10 @@ extern int ttm_bo_mmap(struct file *filp
-  * the function may return -ERESTARTSYS if
-  * interrupted by a signal.
-  */
-+ssize_t ttm_bo_io(struct ttm_bo_device *bdev, struct file *filp,
-+		  const char __user *wbuf, char __user *rbuf,
-+		  size_t count, loff_t *f_pos, bool write);
- 
--extern ssize_t ttm_bo_io(struct ttm_bo_device *bdev, struct file *filp,
--			 const char __user *wbuf, char __user *rbuf,
--			 size_t count, loff_t *f_pos, bool write);
--
--extern void ttm_bo_swapout_all(struct ttm_bo_device *bdev);
--extern int ttm_bo_wait_unreserved(struct ttm_buffer_object *bo);
-+void ttm_bo_swapout_all(struct ttm_bo_device *bdev);
-+int ttm_bo_wait_unreserved(struct ttm_buffer_object *bo);
- #endif
---- linux-4.14/include/drm/ttm/ttm_bo_driver.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/ttm/ttm_bo_driver.h	2017-12-14 06:39:58.530903647 +0100
-@@ -627,12 +627,12 @@ ttm_flag_masked(uint32_t *old, uint32_t
-  * Returns:
-  * NULL: Out of memory.
-  */
--extern int ttm_tt_init(struct ttm_tt *ttm, struct ttm_bo_device *bdev,
--			unsigned long size, uint32_t page_flags,
--			struct page *dummy_read_page);
--extern int ttm_dma_tt_init(struct ttm_dma_tt *ttm_dma, struct ttm_bo_device *bdev,
--			   unsigned long size, uint32_t page_flags,
--			   struct page *dummy_read_page);
-+int ttm_tt_init(struct ttm_tt *ttm, struct ttm_bo_device *bdev,
-+		unsigned long size, uint32_t page_flags,
-+		struct page *dummy_read_page);
-+int ttm_dma_tt_init(struct ttm_dma_tt *ttm_dma, struct ttm_bo_device *bdev,
-+		    unsigned long size, uint32_t page_flags,
-+		    struct page *dummy_read_page);
- 
- /**
-  * ttm_tt_fini
-@@ -641,8 +641,8 @@ extern int ttm_dma_tt_init(struct ttm_dm
-  *
-  * Free memory of ttm_tt structure
-  */
--extern void ttm_tt_fini(struct ttm_tt *ttm);
--extern void ttm_dma_tt_fini(struct ttm_dma_tt *ttm_dma);
-+void ttm_tt_fini(struct ttm_tt *ttm);
-+void ttm_dma_tt_fini(struct ttm_dma_tt *ttm_dma);
- 
- /**
-  * ttm_ttm_bind:
-@@ -652,7 +652,7 @@ extern void ttm_dma_tt_fini(struct ttm_d
-  *
-  * Bind the pages of @ttm to an aperture location identified by @bo_mem
-  */
--extern int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem);
-+int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem);
- 
- /**
-  * ttm_ttm_destroy:
-@@ -661,7 +661,7 @@ extern int ttm_tt_bind(struct ttm_tt *tt
-  *
-  * Unbind, unpopulate and destroy common struct ttm_tt.
-  */
--extern void ttm_tt_destroy(struct ttm_tt *ttm);
-+void ttm_tt_destroy(struct ttm_tt *ttm);
- 
- /**
-  * ttm_ttm_unbind:
-@@ -670,7 +670,7 @@ extern void ttm_tt_destroy(struct ttm_tt
-  *
-  * Unbind a struct ttm_tt.
-  */
--extern void ttm_tt_unbind(struct ttm_tt *ttm);
-+void ttm_tt_unbind(struct ttm_tt *ttm);
- 
- /**
-  * ttm_tt_swapin:
-@@ -679,7 +679,7 @@ extern void ttm_tt_unbind(struct ttm_tt
-  *
-  * Swap in a previously swap out ttm_tt.
-  */
--extern int ttm_tt_swapin(struct ttm_tt *ttm);
-+int ttm_tt_swapin(struct ttm_tt *ttm);
- 
- /**
-  * ttm_tt_set_placement_caching:
-@@ -694,9 +694,8 @@ extern int ttm_tt_swapin(struct ttm_tt *
-  * hit RAM. This function may be very costly as it involves global TLB
-  * and cache flushes and potential page splitting / combining.
-  */
--extern int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement);
--extern int ttm_tt_swapout(struct ttm_tt *ttm,
--			  struct file *persistent_swap_storage);
-+int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement);
-+int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistent_swap_storage);
- 
- /**
-  * ttm_tt_unpopulate - free pages from a ttm
-@@ -705,7 +704,7 @@ extern int ttm_tt_swapout(struct ttm_tt
-  *
-  * Calls the driver method to free all pages from a ttm
-  */
--extern void ttm_tt_unpopulate(struct ttm_tt *ttm);
-+void ttm_tt_unpopulate(struct ttm_tt *ttm);
- 
- /*
-  * ttm_bo.c
-@@ -720,8 +719,7 @@ extern void ttm_tt_unpopulate(struct ttm
-  * Returns true if the memory described by @mem is PCI memory,
-  * false otherwise.
-  */
--extern bool ttm_mem_reg_is_pci(struct ttm_bo_device *bdev,
--				   struct ttm_mem_reg *mem);
-+bool ttm_mem_reg_is_pci(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem);
- 
- /**
-  * ttm_bo_mem_space
-@@ -742,21 +740,20 @@ extern bool ttm_mem_reg_is_pci(struct tt
-  * fragmentation or concurrent allocators.
-  * -ERESTARTSYS: An interruptible sleep was interrupted by a signal.
-  */
--extern int ttm_bo_mem_space(struct ttm_buffer_object *bo,
--				struct ttm_placement *placement,
--				struct ttm_mem_reg *mem,
--				bool interruptible,
--				bool no_wait_gpu);
-+int ttm_bo_mem_space(struct ttm_buffer_object *bo,
-+		     struct ttm_placement *placement,
-+		     struct ttm_mem_reg *mem,
-+		     bool interruptible,
-+		     bool no_wait_gpu);
- 
--extern void ttm_bo_mem_put(struct ttm_buffer_object *bo,
-+void ttm_bo_mem_put(struct ttm_buffer_object *bo, struct ttm_mem_reg *mem);
-+void ttm_bo_mem_put_locked(struct ttm_buffer_object *bo,
- 			   struct ttm_mem_reg *mem);
--extern void ttm_bo_mem_put_locked(struct ttm_buffer_object *bo,
--				  struct ttm_mem_reg *mem);
- 
--extern void ttm_bo_global_release(struct drm_global_reference *ref);
--extern int ttm_bo_global_init(struct drm_global_reference *ref);
-+void ttm_bo_global_release(struct drm_global_reference *ref);
-+int ttm_bo_global_init(struct drm_global_reference *ref);
- 
--extern int ttm_bo_device_release(struct ttm_bo_device *bdev);
-+int ttm_bo_device_release(struct ttm_bo_device *bdev);
- 
- /**
-  * ttm_bo_device_init
-@@ -773,18 +770,17 @@ extern int ttm_bo_device_release(struct
-  * Returns:
-  * !0: Failure.
-  */
--extern int ttm_bo_device_init(struct ttm_bo_device *bdev,
--			      struct ttm_bo_global *glob,
--			      struct ttm_bo_driver *driver,
--			      struct address_space *mapping,
--			      uint64_t file_page_offset, bool need_dma32);
-+int ttm_bo_device_init(struct ttm_bo_device *bdev, struct ttm_bo_global *glob,
-+		       struct ttm_bo_driver *driver,
-+		       struct address_space *mapping,
-+		       uint64_t file_page_offset, bool need_dma32);
- 
- /**
-  * ttm_bo_unmap_virtual
-  *
-  * @bo: tear down the virtual mappings for this BO
-  */
--extern void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo);
-+void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo);
- 
- /**
-  * ttm_bo_unmap_virtual
-@@ -793,16 +789,15 @@ extern void ttm_bo_unmap_virtual(struct
-  *
-  * The caller must take ttm_mem_io_lock before calling this function.
-  */
--extern void ttm_bo_unmap_virtual_locked(struct ttm_buffer_object *bo);
-+void ttm_bo_unmap_virtual_locked(struct ttm_buffer_object *bo);
- 
--extern int ttm_mem_io_reserve_vm(struct ttm_buffer_object *bo);
--extern void ttm_mem_io_free_vm(struct ttm_buffer_object *bo);
--extern int ttm_mem_io_lock(struct ttm_mem_type_manager *man,
--			   bool interruptible);
--extern void ttm_mem_io_unlock(struct ttm_mem_type_manager *man);
-+int ttm_mem_io_reserve_vm(struct ttm_buffer_object *bo);
-+void ttm_mem_io_free_vm(struct ttm_buffer_object *bo);
-+int ttm_mem_io_lock(struct ttm_mem_type_manager *man, bool interruptible);
-+void ttm_mem_io_unlock(struct ttm_mem_type_manager *man);
- 
--extern void ttm_bo_del_sub_from_lru(struct ttm_buffer_object *bo);
--extern void ttm_bo_add_to_lru(struct ttm_buffer_object *bo);
-+void ttm_bo_del_sub_from_lru(struct ttm_buffer_object *bo);
-+void ttm_bo_add_to_lru(struct ttm_buffer_object *bo);
- 
- /**
-  * __ttm_bo_reserve:
-@@ -836,14 +831,14 @@ static inline int __ttm_bo_reserve(struc
- 		if (WARN_ON(ticket))
- 			return -EBUSY;
- 
--		success = ww_mutex_trylock(&bo->resv->lock);
-+		success = reservation_object_trylock(bo->resv);
- 		return success ? 0 : -EBUSY;
- 	}
- 
- 	if (interruptible)
--		ret = ww_mutex_lock_interruptible(&bo->resv->lock, ticket);
-+		ret = reservation_object_lock_interruptible(bo->resv, ticket);
- 	else
--		ret = ww_mutex_lock(&bo->resv->lock, ticket);
-+		ret = reservation_object_lock(bo->resv, ticket);
- 	if (ret == -EINTR)
- 		return -ERESTARTSYS;
- 	return ret;
-@@ -941,18 +936,6 @@ static inline int ttm_bo_reserve_slowpat
- }
- 
- /**
-- * __ttm_bo_unreserve
-- * @bo: A pointer to a struct ttm_buffer_object.
-- *
-- * Unreserve a previous reservation of @bo where the buffer object is
-- * already on lru lists.
-- */
--static inline void __ttm_bo_unreserve(struct ttm_buffer_object *bo)
--{
--	ww_mutex_unlock(&bo->resv->lock);
--}
--
--/**
-  * ttm_bo_unreserve
-  *
-  * @bo: A pointer to a struct ttm_buffer_object.
-@@ -966,20 +949,7 @@ static inline void ttm_bo_unreserve(stru
- 		ttm_bo_add_to_lru(bo);
- 		spin_unlock(&bo->glob->lru_lock);
- 	}
--	__ttm_bo_unreserve(bo);
--}
--
--/**
-- * ttm_bo_unreserve_ticket
-- * @bo: A pointer to a struct ttm_buffer_object.
-- * @ticket: ww_acquire_ctx used for reserving
-- *
-- * Unreserve a previous reservation of @bo made with @ticket.
-- */
--static inline void ttm_bo_unreserve_ticket(struct ttm_buffer_object *bo,
--					   struct ww_acquire_ctx *t)
--{
--	ttm_bo_unreserve(bo);
-+	reservation_object_unlock(bo->resv);
- }
- 
- /*
-@@ -1008,9 +978,9 @@ void ttm_mem_io_free(struct ttm_bo_devic
-  * !0: Failure.
-  */
- 
--extern int ttm_bo_move_ttm(struct ttm_buffer_object *bo,
--			   bool interruptible, bool no_wait_gpu,
--			   struct ttm_mem_reg *new_mem);
-+int ttm_bo_move_ttm(struct ttm_buffer_object *bo,
-+		    bool interruptible, bool no_wait_gpu,
-+		    struct ttm_mem_reg *new_mem);
- 
- /**
-  * ttm_bo_move_memcpy
-@@ -1030,9 +1000,9 @@ extern int ttm_bo_move_ttm(struct ttm_bu
-  * !0: Failure.
-  */
- 
--extern int ttm_bo_move_memcpy(struct ttm_buffer_object *bo,
--			      bool interruptible, bool no_wait_gpu,
--			      struct ttm_mem_reg *new_mem);
-+int ttm_bo_move_memcpy(struct ttm_buffer_object *bo,
-+		       bool interruptible, bool no_wait_gpu,
-+		       struct ttm_mem_reg *new_mem);
- 
- /**
-  * ttm_bo_free_old_node
-@@ -1041,7 +1011,7 @@ extern int ttm_bo_move_memcpy(struct ttm
-  *
-  * Utility function to free an old placement after a successful move.
-  */
--extern void ttm_bo_free_old_node(struct ttm_buffer_object *bo);
-+void ttm_bo_free_old_node(struct ttm_buffer_object *bo);
- 
- /**
-  * ttm_bo_move_accel_cleanup.
-@@ -1058,10 +1028,9 @@ extern void ttm_bo_free_old_node(struct
-  * destroyed when the move is complete. This will help pipeline
-  * buffer moves.
-  */
--
--extern int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
--				     struct dma_fence *fence, bool evict,
--				     struct ttm_mem_reg *new_mem);
-+int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
-+			      struct dma_fence *fence, bool evict,
-+			      struct ttm_mem_reg *new_mem);
- 
- /**
-  * ttm_bo_pipeline_move.
-@@ -1087,7 +1056,7 @@ int ttm_bo_pipeline_move(struct ttm_buff
-  * Utility function that returns the pgprot_t that should be used for
-  * setting up a PTE with the caching model indicated by @c_state.
-  */
--extern pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp);
-+pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp);
- 
- extern const struct ttm_mem_type_manager_func ttm_bo_manager_func;
- 
-@@ -1108,10 +1077,10 @@ extern const struct ttm_mem_type_manager
-  * for TT memory. This function uses the linux agpgart interface to
-  * bind and unbind memory backing a ttm_tt.
-  */
--extern struct ttm_tt *ttm_agp_tt_create(struct ttm_bo_device *bdev,
--					struct agp_bridge_data *bridge,
--					unsigned long size, uint32_t page_flags,
--					struct page *dummy_read_page);
-+struct ttm_tt *ttm_agp_tt_create(struct ttm_bo_device *bdev,
-+				 struct agp_bridge_data *bridge,
-+				 unsigned long size, uint32_t page_flags,
-+				 struct page *dummy_read_page);
- int ttm_agp_tt_populate(struct ttm_tt *ttm);
- void ttm_agp_tt_unpopulate(struct ttm_tt *ttm);
- #endif
---- linux-4.14/include/drm/ttm/ttm_debug.h.0130~	2017-12-14 06:39:58.530903647 +0100
-+++ linux-4.14/include/drm/ttm/ttm_debug.h	2017-12-14 06:39:58.530903647 +0100
-@@ -0,0 +1,31 @@
-+/**************************************************************************
-+ *
-+ * Copyright (c) 2017 Advanced Micro Devices, Inc.
-+ * All Rights Reserved.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the
-+ * "Software"), to deal in the Software without restriction, including
-+ * without limitation the rights to use, copy, modify, merge, publish,
-+ * distribute, sub license, and/or sell copies of the Software, and to
-+ * permit persons to whom the Software is furnished to do so, subject to
-+ * the following conditions:
-+ *
-+ * The above copyright notice and this permission notice (including the
-+ * next paragraph) shall be included in all copies or substantial portions
-+ * of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
-+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ **************************************************************************/
-+/*
-+ * Authors: Tom St Denis <tom.stdenis@amd.com>
-+ */
-+extern void ttm_trace_dma_map(struct device *dev, struct ttm_dma_tt *tt);
-+extern void ttm_trace_dma_unmap(struct device *dev, struct ttm_dma_tt *tt);
---- linux-4.14/include/drm/ttm/ttm_memory.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/ttm/ttm_memory.h	2017-12-14 06:39:58.530903647 +0100
-@@ -150,10 +150,9 @@ extern int ttm_mem_global_alloc(struct t
- extern void ttm_mem_global_free(struct ttm_mem_global *glob,
- 				uint64_t amount);
- extern int ttm_mem_global_alloc_page(struct ttm_mem_global *glob,
--				     struct page *page,
--				     bool no_wait, bool interruptible);
-+				     struct page *page, uint64_t size);
- extern void ttm_mem_global_free_page(struct ttm_mem_global *glob,
--				     struct page *page);
-+				     struct page *page, uint64_t size);
- extern size_t ttm_round_pot(size_t size);
- extern uint64_t ttm_get_kernel_zone_memory_size(struct ttm_mem_global *glob);
- #endif
---- linux-4.14/include/drm/ttm/ttm_page_alloc.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/drm/ttm/ttm_page_alloc.h	2017-12-14 06:39:58.530903647 +0100
-@@ -47,7 +47,7 @@ void ttm_page_alloc_fini(void);
-  *
-  * Add backing pages to all of @ttm
-  */
--extern int ttm_pool_populate(struct ttm_tt *ttm);
-+int ttm_pool_populate(struct ttm_tt *ttm);
- 
- /**
-  * ttm_pool_unpopulate:
-@@ -56,12 +56,12 @@ extern int ttm_pool_populate(struct ttm_
-  *
-  * Free all pages of @ttm
-  */
--extern void ttm_pool_unpopulate(struct ttm_tt *ttm);
-+void ttm_pool_unpopulate(struct ttm_tt *ttm);
- 
- /**
-  * Output the state of pools to debugfs file
-  */
--extern int ttm_page_alloc_debugfs(struct seq_file *m, void *data);
-+int ttm_page_alloc_debugfs(struct seq_file *m, void *data);
- 
- 
- #if defined(CONFIG_SWIOTLB) || defined(CONFIG_INTEL_IOMMU)
-@@ -78,10 +78,21 @@ void ttm_dma_page_alloc_fini(void);
- /**
-  * Output the state of pools to debugfs file
-  */
--extern int ttm_dma_page_alloc_debugfs(struct seq_file *m, void *data);
-+int ttm_dma_page_alloc_debugfs(struct seq_file *m, void *data);
- 
--extern int ttm_dma_populate(struct ttm_dma_tt *ttm_dma, struct device *dev);
--extern void ttm_dma_unpopulate(struct ttm_dma_tt *ttm_dma, struct device *dev);
-+int ttm_dma_populate(struct ttm_dma_tt *ttm_dma, struct device *dev);
-+void ttm_dma_unpopulate(struct ttm_dma_tt *ttm_dma, struct device *dev);
-+
-+
-+/**
-+ * Populates and DMA maps pages to fullfil a ttm_dma_populate() request
-+ */
-+int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt);
-+
-+/**
-+ * Unpopulates and DMA unmaps pages as part of a
-+ * ttm_dma_unpopulate() request */
-+void ttm_unmap_and_unpopulate_pages(struct device *dev, struct ttm_dma_tt *tt);
- 
- #else
- static inline int ttm_dma_page_alloc_init(struct ttm_mem_global *glob,
-@@ -105,6 +116,16 @@ static inline void ttm_dma_unpopulate(st
- 				      struct device *dev)
- {
- }
-+
-+static inline int ttm_populate_and_map_pages(struct device *dev, struct ttm_dma_tt *tt)
-+{
-+	return -ENOMEM;
-+}
-+
-+static inline void ttm_unmap_and_unpopulate_pages(struct device *dev, struct ttm_dma_tt *tt)
-+{
-+}
-+
- #endif
- 
- #endif
---- linux-4.14/include/linux/dma-fence.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/linux/dma-fence.h	2017-12-14 06:39:58.530903647 +0100
-@@ -248,9 +248,12 @@ dma_fence_get_rcu_safe(struct dma_fence
- 		struct dma_fence *fence;
- 
- 		fence = rcu_dereference(*fencep);
--		if (!fence || !dma_fence_get_rcu(fence))
-+		if (!fence)
- 			return NULL;
- 
-+		if (!dma_fence_get_rcu(fence))
-+			continue;
-+
- 		/* The atomic_inc_not_zero() inside dma_fence_get_rcu()
- 		 * provides a full memory barrier upon success (such as now).
- 		 * This is paired with the write barrier from assigning
---- linux-4.14/include/linux/pci.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/linux/pci.h	2017-12-14 06:39:58.531903648 +0100
-@@ -1107,6 +1107,8 @@ void pci_reset_bridge_secondary_bus(stru
- void pci_update_resource(struct pci_dev *dev, int resno);
- int __must_check pci_assign_resource(struct pci_dev *dev, int i);
- int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
-+void pci_release_resource(struct pci_dev *dev, int resno);
-+int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
- int pci_select_bars(struct pci_dev *dev, unsigned long flags);
- bool pci_device_is_present(struct pci_dev *pdev);
- void pci_ignore_hotplug(struct pci_dev *dev);
-@@ -1186,6 +1188,7 @@ void pci_assign_unassigned_resources(voi
- void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
- void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
- void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
-+int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
- void pdev_enable_device(struct pci_dev *);
- int pci_enable_resources(struct pci_dev *, int mask);
- void pci_assign_irq(struct pci_dev *dev);
---- linux-4.14/include/linux/regmap.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/linux/regmap.h	2017-12-14 06:39:58.531903648 +0100
-@@ -139,6 +139,45 @@ struct reg_sequence {
- 	pollret ?: ((cond) ? 0 : -ETIMEDOUT); \
- })
- 
-+/**
-+ * regmap_field_read_poll_timeout - Poll until a condition is met or timeout
-+ *
-+ * @field: Regmap field to read from
-+ * @val: Unsigned integer variable to read the value into
-+ * @cond: Break condition (usually involving @val)
-+ * @sleep_us: Maximum time to sleep between reads in us (0
-+ *            tight-loops).  Should be less than ~20ms since usleep_range
-+ *            is used (see Documentation/timers/timers-howto.txt).
-+ * @timeout_us: Timeout in us, 0 means never timeout
-+ *
-+ * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_field_read
-+ * error return value in case of a error read. In the two former cases,
-+ * the last read value at @addr is stored in @val. Must not be called
-+ * from atomic context if sleep_us or timeout_us are used.
-+ *
-+ * This is modelled after the readx_poll_timeout macros in linux/iopoll.h.
-+ */
-+#define regmap_field_read_poll_timeout(field, val, cond, sleep_us, timeout_us) \
-+({ \
-+	ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); \
-+	int pollret; \
-+	might_sleep_if(sleep_us); \
-+	for (;;) { \
-+		pollret = regmap_field_read((field), &(val)); \
-+		if (pollret) \
-+			break; \
-+		if (cond) \
-+			break; \
-+		if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { \
-+			pollret = regmap_field_read((field), &(val)); \
-+			break; \
-+		} \
-+		if (sleep_us) \
-+			usleep_range((sleep_us >> 2) + 1, sleep_us); \
-+	} \
-+	pollret ?: ((cond) ? 0 : -ETIMEDOUT); \
-+})
-+
- #ifdef CONFIG_REGMAP
- 
- enum regmap_endian {
---- linux-4.14/include/linux/reservation.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/linux/reservation.h	2017-12-14 06:39:58.531903648 +0100
-@@ -167,6 +167,29 @@ reservation_object_lock(struct reservati
- }
- 
- /**
-+ * reservation_object_lock_interruptible - lock the reservation object
-+ * @obj: the reservation object
-+ * @ctx: the locking context
-+ *
-+ * Locks the reservation object interruptible for exclusive access and
-+ * modification. Note, that the lock is only against other writers, readers
-+ * will run concurrently with a writer under RCU. The seqlock is used to
-+ * notify readers if they overlap with a writer.
-+ *
-+ * As the reservation object may be locked by multiple parties in an
-+ * undefined order, a #ww_acquire_ctx is passed to unwind if a cycle
-+ * is detected. See ww_mutex_lock() and ww_acquire_init(). A reservation
-+ * object may be locked by itself by passing NULL as @ctx.
-+ */
-+static inline int
-+reservation_object_lock_interruptible(struct reservation_object *obj,
-+				      struct ww_acquire_ctx *ctx)
-+{
-+	return ww_mutex_lock_interruptible(&obj->lock, ctx);
-+}
-+
-+
-+/**
-  * reservation_object_trylock - trylock the reservation object
-  * @obj: the reservation object
-  *
---- linux-4.14/include/linux/scatterlist.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/linux/scatterlist.h	2017-12-14 06:39:58.531903648 +0100
-@@ -22,6 +22,12 @@ struct scatterlist {
- };
- 
- /*
-+ * Since the above length field is an unsigned int, below we define the maximum
-+ * length in bytes that can be stored in one scatterlist entry.
-+ */
-+#define SCATTERLIST_MAX_SEGMENT (UINT_MAX & PAGE_MASK)
-+
-+/*
-  * These macros should be used after a dma_map_sg call has been done
-  * to get bus addresses of each of the SG entries and their lengths.
-  * You should only work with the number of sg entries dma_map_sg
-@@ -262,10 +268,13 @@ void sg_free_table(struct sg_table *);
- int __sg_alloc_table(struct sg_table *, unsigned int, unsigned int,
- 		     struct scatterlist *, gfp_t, sg_alloc_fn *);
- int sg_alloc_table(struct sg_table *, unsigned int, gfp_t);
--int sg_alloc_table_from_pages(struct sg_table *sgt,
--	struct page **pages, unsigned int n_pages,
--	unsigned long offset, unsigned long size,
--	gfp_t gfp_mask);
-+int __sg_alloc_table_from_pages(struct sg_table *sgt, struct page **pages,
-+				unsigned int n_pages, unsigned int offset,
-+				unsigned long size, unsigned int max_segment,
-+				gfp_t gfp_mask);
-+int sg_alloc_table_from_pages(struct sg_table *sgt, struct page **pages,
-+			      unsigned int n_pages, unsigned int offset,
-+			      unsigned long size, gfp_t gfp_mask);
- 
- size_t sg_copy_buffer(struct scatterlist *sgl, unsigned int nents, void *buf,
- 		      size_t buflen, off_t skip, bool to_buffer);
---- linux-4.14/include/linux/sync_file.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/linux/sync_file.h	2017-12-14 06:39:58.531903648 +0100
-@@ -25,8 +25,12 @@
-  * @file:		file representing this fence
-  * @sync_file_list:	membership in global file list
-  * @wq:			wait queue for fence signaling
-+ * @flags:		flags for the sync_file
-  * @fence:		fence with the fences in the sync_file
-  * @cb:			fence callback information
-+ *
-+ * flags:
-+ * POLL_ENABLED: whether userspace is currently poll()'ing or not
-  */
- struct sync_file {
- 	struct file		*file;
---- linux-4.14/include/uapi/drm/amdgpu_drm.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/uapi/drm/amdgpu_drm.h	2017-12-14 06:39:58.531903648 +0100
-@@ -52,6 +52,10 @@ extern "C" {
- #define DRM_AMDGPU_GEM_USERPTR		0x11
- #define DRM_AMDGPU_WAIT_FENCES		0x12
- #define DRM_AMDGPU_VM			0x13
-+#define DRM_AMDGPU_FENCE_TO_HANDLE	0x14
-+#define DRM_AMDGPU_SCHED		0x15
-+/* not upstream */
-+#define DRM_AMDGPU_FREESYNC	        0x5d
- 
- #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
- #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
-@@ -67,6 +71,9 @@ extern "C" {
- #define DRM_IOCTL_AMDGPU_GEM_USERPTR	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
- #define DRM_IOCTL_AMDGPU_WAIT_FENCES	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
- #define DRM_IOCTL_AMDGPU_VM		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
-+#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
-+#define DRM_IOCTL_AMDGPU_SCHED		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
-+#define DRM_IOCTL_AMDGPU_FREESYNC	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync)
- 
- #define AMDGPU_GEM_DOMAIN_CPU		0x1
- #define AMDGPU_GEM_DOMAIN_GTT		0x2
-@@ -87,6 +94,10 @@ extern "C" {
- #define AMDGPU_GEM_CREATE_SHADOW		(1 << 4)
- /* Flag that allocating the BO should use linear VRAM */
- #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS	(1 << 5)
-+/* Flag that BO is always valid in this VM */
-+#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID	(1 << 6)
-+/* Flag that BO sharing will be explicitly synchronized */
-+#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC		(1 << 7)
- 
- struct drm_amdgpu_gem_create_in  {
- 	/** the requested memory size */
-@@ -152,6 +163,7 @@ union drm_amdgpu_bo_list {
- #define AMDGPU_CTX_OP_ALLOC_CTX	1
- #define AMDGPU_CTX_OP_FREE_CTX	2
- #define AMDGPU_CTX_OP_QUERY_STATE	3
-+#define AMDGPU_CTX_OP_QUERY_STATE2	4
- 
- /* GPU reset status */
- #define AMDGPU_CTX_NO_RESET		0
-@@ -162,13 +174,29 @@ union drm_amdgpu_bo_list {
- /* unknown cause */
- #define AMDGPU_CTX_UNKNOWN_RESET	3
- 
-+/* indicate gpu reset occured after ctx created */
-+#define AMDGPU_CTX_QUERY2_FLAGS_RESET    (1<<0)
-+/* indicate vram lost occured after ctx created */
-+#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
-+/* indicate some job from this context once cause gpu hang */
-+#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY   (1<<2)
-+
-+/* Context priority level */
-+#define AMDGPU_CTX_PRIORITY_UNSET       -2048
-+#define AMDGPU_CTX_PRIORITY_VERY_LOW    -1023
-+#define AMDGPU_CTX_PRIORITY_LOW         -512
-+#define AMDGPU_CTX_PRIORITY_NORMAL      0
-+/* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
-+#define AMDGPU_CTX_PRIORITY_HIGH        512
-+#define AMDGPU_CTX_PRIORITY_VERY_HIGH   1023
-+
- struct drm_amdgpu_ctx_in {
- 	/** AMDGPU_CTX_OP_* */
- 	__u32	op;
- 	/** For future use, no flags defined so far */
- 	__u32	flags;
- 	__u32	ctx_id;
--	__u32	_pad;
-+	__s32	priority;
- };
- 
- union drm_amdgpu_ctx_out {
-@@ -212,6 +240,21 @@ union drm_amdgpu_vm {
- 	struct drm_amdgpu_vm_out out;
- };
- 
-+/* sched ioctl */
-+#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE	1
-+
-+struct drm_amdgpu_sched_in {
-+	/* AMDGPU_SCHED_OP_* */
-+	__u32	op;
-+	__u32	fd;
-+	__s32	priority;
-+	__u32	flags;
-+};
-+
-+union drm_amdgpu_sched {
-+	struct drm_amdgpu_sched_in in;
-+};
-+
- /*
-  * This is not a reliable API and you should expect it to fail for any
-  * number of reasons and have fallback path that do not use userptr to
-@@ -513,6 +556,21 @@ struct drm_amdgpu_cs_chunk_sem {
- 	__u32 handle;
- };
- 
-+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ	0
-+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD	1
-+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD	2
-+
-+union drm_amdgpu_fence_to_handle {
-+	struct {
-+		struct drm_amdgpu_fence fence;
-+		__u32 what;
-+		__u32 pad;
-+	} in;
-+	struct {
-+		__u32 handle;
-+	} out;
-+};
-+
- struct drm_amdgpu_cs_chunk_data {
- 	union {
- 		struct drm_amdgpu_cs_chunk_ib		ib_data;
-@@ -611,6 +669,7 @@ struct drm_amdgpu_cs_chunk_data {
- 	#define AMDGPU_INFO_SENSOR_VDDGFX		0x7
- /* Number of VRAM page faults on CPU access. */
- #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS	0x1E
-+#define AMDGPU_INFO_VRAM_LOST_COUNTER		0x1F
- 
- #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0
- #define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff
-@@ -875,6 +934,19 @@ struct drm_amdgpu_info_vce_clock_table {
- #define AMDGPU_FAMILY_AI			141 /* Vega10 */
- #define AMDGPU_FAMILY_RV			142 /* Raven */
- 
-+/*
-+ * Definition of free sync enter and exit signals
-+ * We may have more options in the future
-+ */
-+#define AMDGPU_FREESYNC_FULLSCREEN_ENTER		1
-+#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 		2
-+
-+struct drm_amdgpu_freesync {
-+	__u32 op;			/* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */
-+				        /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */
-+	__u32 spare[7];
-+};
-+
- #if defined(__cplusplus)
- }
- #endif
---- linux-4.14/include/uapi/drm/drm_mode.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/uapi/drm/drm_mode.h	2017-12-14 06:39:58.531903648 +0100
-@@ -749,9 +749,9 @@ struct drm_format_modifier {
- 	 * If the number formats grew to 128, and formats 98-102 are
- 	 * supported with the modifier:
- 	 *
--	 * 0x0000003c00000000 0000000000000000
-+	 * 0x0000007c00000000 0000000000000000
- 	 *		  ^
--	 *		  |__offset = 64, formats = 0x3c00000000
-+	 *		  |__offset = 64, formats = 0x7c00000000
- 	 *
- 	 */
- 	__u64 formats;
---- linux-4.14/include/uapi/drm/etnaviv_drm.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/uapi/drm/etnaviv_drm.h	2017-12-14 06:39:58.531903648 +0100
-@@ -151,6 +151,19 @@ struct drm_etnaviv_gem_submit_bo {
- 	__u64 presumed;       /* in/out, presumed buffer address */
- };
- 
-+/* performance monitor request (pmr) */
-+#define ETNA_PM_PROCESS_PRE             0x0001
-+#define ETNA_PM_PROCESS_POST            0x0002
-+struct drm_etnaviv_gem_submit_pmr {
-+	__u32 flags;          /* in, when to process request (ETNA_PM_PROCESS_x) */
-+	__u8  domain;         /* in, pm domain */
-+	__u8  pad;
-+	__u16 signal;         /* in, pm signal */
-+	__u32 sequence;       /* in, sequence number */
-+	__u32 read_offset;    /* in, offset from read_bo */
-+	__u32 read_idx;       /* in, index of read_bo buffer */
-+};
-+
- /* Each cmdstream submit consists of a table of buffers involved, and
-  * one or more cmdstream buffers.  This allows for conditional execution
-  * (context-restore), and IB buffers needed for per tile/bin draw cmds.
-@@ -176,6 +189,9 @@ struct drm_etnaviv_gem_submit {
- 	__u64 stream;         /* in, ptr to cmdstream */
- 	__u32 flags;          /* in, mask of ETNA_SUBMIT_x */
- 	__s32 fence_fd;       /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
-+	__u64 pmrs;           /* in, ptr to array of submit_pmr's */
-+	__u32 nr_pmrs;        /* in, number of submit_pmr's */
-+	__u32 pad;
- };
- 
- /* The normal way to synchronize with the GPU is just to CPU_PREP on
-@@ -211,6 +227,27 @@ struct drm_etnaviv_gem_wait {
- 	struct drm_etnaviv_timespec timeout;	/* in */
- };
- 
-+/*
-+ * Performance Monitor (PM):
-+ */
-+
-+struct drm_etnaviv_pm_domain {
-+	__u32 pipe;       /* in */
-+	__u8  iter;       /* in/out, select pm domain at index iter */
-+	__u8  id;         /* out, id of domain */
-+	__u16 nr_signals; /* out, how many signals does this domain provide */
-+	char  name[64];   /* out, name of domain */
-+};
-+
-+struct drm_etnaviv_pm_signal {
-+	__u32 pipe;       /* in */
-+	__u8  domain;     /* in, pm domain index */
-+	__u8  pad;
-+	__u16 iter;       /* in/out, select pm source at index iter */
-+	__u16 id;         /* out, id of signal */
-+	char  name[64];   /* out, name of domain */
-+};
-+
- #define DRM_ETNAVIV_GET_PARAM          0x00
- /* placeholder:
- #define DRM_ETNAVIV_SET_PARAM          0x01
-@@ -223,7 +260,9 @@ struct drm_etnaviv_gem_wait {
- #define DRM_ETNAVIV_WAIT_FENCE         0x07
- #define DRM_ETNAVIV_GEM_USERPTR        0x08
- #define DRM_ETNAVIV_GEM_WAIT           0x09
--#define DRM_ETNAVIV_NUM_IOCTLS         0x0a
-+#define DRM_ETNAVIV_PM_QUERY_DOM       0x0a
-+#define DRM_ETNAVIV_PM_QUERY_SIG       0x0b
-+#define DRM_ETNAVIV_NUM_IOCTLS         0x0c
- 
- #define DRM_IOCTL_ETNAVIV_GET_PARAM    DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
- #define DRM_IOCTL_ETNAVIV_GEM_NEW      DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
-@@ -234,6 +273,8 @@ struct drm_etnaviv_gem_wait {
- #define DRM_IOCTL_ETNAVIV_WAIT_FENCE   DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
- #define DRM_IOCTL_ETNAVIV_GEM_USERPTR  DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
- #define DRM_IOCTL_ETNAVIV_GEM_WAIT     DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
-+#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
-+#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
- 
- #if defined(__cplusplus)
- }
---- linux-4.14/include/uapi/drm/i915_drm.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/uapi/drm/i915_drm.h	2017-12-14 06:39:58.531903648 +0100
-@@ -1309,14 +1309,16 @@ struct drm_i915_reg_read {
- 	 * be specified
- 	 */
- 	__u64 offset;
-+#define I915_REG_READ_8B_WA BIT(0)
-+
- 	__u64 val; /* Return value */
- };
- /* Known registers:
-  *
-  * Render engine timestamp - 0x2358 + 64bit - gen7+
-  * - Note this register returns an invalid value if using the default
-- *   single instruction 8byte read, in order to workaround that use
-- *   offset (0x2538 | 1) instead.
-+ *   single instruction 8byte read, in order to workaround that pass
-+ *   flag I915_REG_READ_8B_WA in offset field.
-  *
-  */
- 
-@@ -1510,9 +1512,14 @@ struct drm_i915_perf_oa_config {
- 	__u32 n_boolean_regs;
- 	__u32 n_flex_regs;
- 
--	__u64 __user mux_regs_ptr;
--	__u64 __user boolean_regs_ptr;
--	__u64 __user flex_regs_ptr;
-+	/*
-+	 * These fields are pointers to tuples of u32 values (register
-+	 * address, value). For example the expected length of the buffer
-+	 * pointed by mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
-+	 */
-+	__u64 mux_regs_ptr;
-+	__u64 boolean_regs_ptr;
-+	__u64 flex_regs_ptr;
- };
- 
- #if defined(__cplusplus)
---- linux-4.14/include/uapi/linux/pci_regs.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/include/uapi/linux/pci_regs.h	2017-12-14 06:39:58.531903648 +0100
-@@ -940,9 +940,13 @@
- #define PCI_SATA_SIZEOF_LONG	16
- 
- /* Resizable BARs */
-+#define PCI_REBAR_CAP		4	/* capability register */
-+#define  PCI_REBAR_CAP_SIZES		0x00FFFFF0  /* supported BAR sizes */
- #define PCI_REBAR_CTRL		8	/* control register */
--#define  PCI_REBAR_CTRL_NBAR_MASK	(7 << 5)	/* mask for # bars */
--#define  PCI_REBAR_CTRL_NBAR_SHIFT	5	/* shift for # bars */
-+#define  PCI_REBAR_CTRL_BAR_IDX		0x00000007  /* BAR index */
-+#define  PCI_REBAR_CTRL_NBAR_MASK	0x000000E0  /* # of resizable BARs */
-+#define  PCI_REBAR_CTRL_NBAR_SHIFT	5  	    /* shift for # of BARs */
-+#define  PCI_REBAR_CTRL_BAR_SIZE	0x00001F00  /* BAR size */
- 
- /* Dynamic Power Allocation */
- #define PCI_DPA_CAP		4	/* capability register */
---- linux-4.14/lib/scatterlist.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/lib/scatterlist.c	2017-12-14 06:39:58.532903649 +0100
-@@ -370,41 +370,49 @@ int sg_alloc_table(struct sg_table *tabl
- EXPORT_SYMBOL(sg_alloc_table);
- 
- /**
-- * sg_alloc_table_from_pages - Allocate and initialize an sg table from
-- *			       an array of pages
-- * @sgt:	The sg table header to use
-- * @pages:	Pointer to an array of page pointers
-- * @n_pages:	Number of pages in the pages array
-- * @offset:     Offset from start of the first page to the start of a buffer
-- * @size:       Number of valid bytes in the buffer (after offset)
-- * @gfp_mask:	GFP allocation mask
-+ * __sg_alloc_table_from_pages - Allocate and initialize an sg table from
-+ *			         an array of pages
-+ * @sgt:	 The sg table header to use
-+ * @pages:	 Pointer to an array of page pointers
-+ * @n_pages:	 Number of pages in the pages array
-+ * @offset:      Offset from start of the first page to the start of a buffer
-+ * @size:        Number of valid bytes in the buffer (after offset)
-+ * @max_segment: Maximum size of a scatterlist node in bytes (page aligned)
-+ * @gfp_mask:	 GFP allocation mask
-  *
-  *  Description:
-  *    Allocate and initialize an sg table from a list of pages. Contiguous
-- *    ranges of the pages are squashed into a single scatterlist node. A user
-- *    may provide an offset at a start and a size of valid data in a buffer
-- *    specified by the page array. The returned sg table is released by
-- *    sg_free_table.
-+ *    ranges of the pages are squashed into a single scatterlist node up to the
-+ *    maximum size specified in @max_segment. An user may provide an offset at a
-+ *    start and a size of valid data in a buffer specified by the page array.
-+ *    The returned sg table is released by sg_free_table.
-  *
-  * Returns:
-  *   0 on success, negative error on failure
-  */
--int sg_alloc_table_from_pages(struct sg_table *sgt,
--	struct page **pages, unsigned int n_pages,
--	unsigned long offset, unsigned long size,
--	gfp_t gfp_mask)
-+int __sg_alloc_table_from_pages(struct sg_table *sgt, struct page **pages,
-+				unsigned int n_pages, unsigned int offset,
-+				unsigned long size, unsigned int max_segment,
-+				gfp_t gfp_mask)
- {
--	unsigned int chunks;
--	unsigned int i;
--	unsigned int cur_page;
-+	unsigned int chunks, cur_page, seg_len, i;
- 	int ret;
- 	struct scatterlist *s;
- 
-+	if (WARN_ON(!max_segment || offset_in_page(max_segment)))
-+		return -EINVAL;
-+
- 	/* compute number of contiguous chunks */
- 	chunks = 1;
--	for (i = 1; i < n_pages; ++i)
--		if (page_to_pfn(pages[i]) != page_to_pfn(pages[i - 1]) + 1)
--			++chunks;
-+	seg_len = 0;
-+	for (i = 1; i < n_pages; i++) {
-+		seg_len += PAGE_SIZE;
-+		if (seg_len >= max_segment ||
-+		    page_to_pfn(pages[i]) != page_to_pfn(pages[i - 1]) + 1) {
-+			chunks++;
-+			seg_len = 0;
-+		}
-+	}
- 
- 	ret = sg_alloc_table(sgt, chunks, gfp_mask);
- 	if (unlikely(ret))
-@@ -413,17 +421,21 @@ int sg_alloc_table_from_pages(struct sg_
- 	/* merging chunks and putting them into the scatterlist */
- 	cur_page = 0;
- 	for_each_sg(sgt->sgl, s, sgt->orig_nents, i) {
--		unsigned long chunk_size;
--		unsigned int j;
-+		unsigned int j, chunk_size;
- 
- 		/* look for the end of the current chunk */
--		for (j = cur_page + 1; j < n_pages; ++j)
--			if (page_to_pfn(pages[j]) !=
-+		seg_len = 0;
-+		for (j = cur_page + 1; j < n_pages; j++) {
-+			seg_len += PAGE_SIZE;
-+			if (seg_len >= max_segment ||
-+			    page_to_pfn(pages[j]) !=
- 			    page_to_pfn(pages[j - 1]) + 1)
- 				break;
-+		}
- 
- 		chunk_size = ((j - cur_page) << PAGE_SHIFT) - offset;
--		sg_set_page(s, pages[cur_page], min(size, chunk_size), offset);
-+		sg_set_page(s, pages[cur_page],
-+			    min_t(unsigned long, size, chunk_size), offset);
- 		size -= chunk_size;
- 		offset = 0;
- 		cur_page = j;
-@@ -431,6 +443,35 @@ int sg_alloc_table_from_pages(struct sg_
- 
- 	return 0;
- }
-+EXPORT_SYMBOL(__sg_alloc_table_from_pages);
-+
-+/**
-+ * sg_alloc_table_from_pages - Allocate and initialize an sg table from
-+ *			       an array of pages
-+ * @sgt:	 The sg table header to use
-+ * @pages:	 Pointer to an array of page pointers
-+ * @n_pages:	 Number of pages in the pages array
-+ * @offset:      Offset from start of the first page to the start of a buffer
-+ * @size:        Number of valid bytes in the buffer (after offset)
-+ * @gfp_mask:	 GFP allocation mask
-+ *
-+ *  Description:
-+ *    Allocate and initialize an sg table from a list of pages. Contiguous
-+ *    ranges of the pages are squashed into a single scatterlist node. A user
-+ *    may provide an offset at a start and a size of valid data in a buffer
-+ *    specified by the page array. The returned sg table is released by
-+ *    sg_free_table.
-+ *
-+ * Returns:
-+ *   0 on success, negative error on failure
-+ */
-+int sg_alloc_table_from_pages(struct sg_table *sgt, struct page **pages,
-+			      unsigned int n_pages, unsigned int offset,
-+			      unsigned long size, gfp_t gfp_mask)
-+{
-+	return __sg_alloc_table_from_pages(sgt, pages, n_pages, offset, size,
-+					   SCATTERLIST_MAX_SEGMENT, gfp_mask);
-+}
- EXPORT_SYMBOL(sg_alloc_table_from_pages);
- 
- void __sg_page_iter_start(struct sg_page_iter *piter,
---- linux-4.14/MAINTAINERS.0130~	2017-12-14 06:39:58.357903527 +0100
-+++ linux-4.14/MAINTAINERS	2017-12-14 06:39:58.533903650 +0100
-@@ -4375,6 +4375,12 @@ T:	git git://anongit.freedesktop.org/drm
- S:	Maintained
- F:	drivers/gpu/drm/bochs/
- 
-+DRM DRIVER FOR FARADAY TVE200 TV ENCODER
-+M:	Linus Walleij <linus.walleij@linaro.org>
-+T:	git git://anongit.freedesktop.org/drm/drm-misc
-+S:	Maintained
-+F:	drivers/gpu/drm/tve200/
-+
- DRM DRIVER FOR INTEL I810 VIDEO CARDS
- S:	Orphan / Obsolete
- F:	drivers/gpu/drm/i810/
-@@ -4518,7 +4524,7 @@ L:	dri-devel@lists.freedesktop.org
- S:	Supported
- F:	drivers/gpu/drm/sun4i/
- F:	Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
--T:	git git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git
-+T:	git git://anongit.freedesktop.org/drm/drm-misc
- 
- DRM DRIVERS FOR AMLOGIC SOCS
- M:	Neil Armstrong <narmstrong@baylibre.com>
-@@ -4702,7 +4708,7 @@ T:	git git://anongit.freedesktop.org/drm
- DRM PANEL DRIVERS
- M:	Thierry Reding <thierry.reding@gmail.com>
- L:	dri-devel@lists.freedesktop.org
--T:	git git://anongit.freedesktop.org/tegra/linux.git
-+T:	git git://anongit.freedesktop.org/drm/drm-misc
- S:	Maintained
- F:	drivers/gpu/drm/drm_panel.c
- F:	drivers/gpu/drm/panel/
-@@ -5465,6 +5471,7 @@ F:	drivers/net/wan/sdla.c
- 
- FRAMEBUFFER LAYER
- M:	Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
-+L:	dri-devel@lists.freedesktop.org
- L:	linux-fbdev@vger.kernel.org
- T:	git git://github.com/bzolnier/linux.git
- Q:	http://patchwork.kernel.org/project/linux-fbdev/list/
---- linux-4.14/scripts/coccinelle/api/drm-get-put.cocci.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/scripts/coccinelle/api/drm-get-put.cocci	2017-12-14 06:39:58.533903650 +0100
-@@ -51,6 +51,9 @@ expression object;
- |
- - drm_property_unreference_blob(object)
- + drm_property_blob_put(object)
-+|
-+- drm_dev_unref(object)
-++ drm_dev_put(object)
- )
- 
- @r depends on report@
-@@ -82,6 +85,8 @@ drm_gem_object_unreference_unlocked(obje
- drm_property_unreference_blob@p(object)
- |
- drm_property_reference_blob@p(object)
-+|
-+drm_dev_unref@p(object)
- )
- 
- @script:python depends on report@
---- linux-4.14/sound/soc/amd/acp.h.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/sound/soc/amd/acp.h	2017-12-14 06:39:58.533903650 +0100
-@@ -20,6 +20,7 @@
- 
- /* Capture SRAM address (as a source in dma descriptor) */
- #define ACP_SHARED_RAM_BANK_5_ADDRESS		0x400A000
-+#define ACP_SHARED_RAM_BANK_3_ADDRESS		0x4006000
- 
- #define ACP_DMA_RESET_TIME			10000
- #define ACP_CLOCK_EN_TIME_OUT_VALUE		0x000000FF
-@@ -68,6 +69,7 @@
- #define CAPTURE_START_DMA_DESCR_CH15 6
- #define CAPTURE_END_DMA_DESCR_CH15 7
- 
-+#define mmACP_I2S_16BIT_RESOLUTION_EN       0x5209
- enum acp_dma_priority_level {
- 	/* 0x0 Specifies the DMA channel is given normal priority */
- 	ACP_DMA_PRIORITY_LEVEL_NORMAL = 0x0,
-@@ -82,9 +84,26 @@ struct audio_substream_data {
- 	u16 num_of_pages;
- 	u16 direction;
- 	uint64_t size;
-+	u64 renderbytescount;
-+	u64 capturebytescount;
- 	void __iomem *acp_mmio;
- };
- 
-+struct audio_drv_data {
-+	struct snd_pcm_substream *play_stream;
-+	struct snd_pcm_substream *capture_stream;
-+	void __iomem *acp_mmio;
-+	u32 asic_type;
-+};
-+
-+union acp_dma_count {
-+	struct {
-+	u32 low;
-+	u32 high;
-+	} bcount;
-+	u64 bytescount;
-+};
-+
- enum {
- 	ACP_TILE_P1 = 0,
- 	ACP_TILE_P2,
---- linux-4.14/sound/soc/amd/acp-pcm-dma.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/sound/soc/amd/acp-pcm-dma.c	2017-12-14 06:39:58.533903650 +0100
-@@ -20,7 +20,7 @@
- #include <linux/pm_runtime.h>
- 
- #include <sound/soc.h>
--
-+#include <drm/amd_asic_type.h>
- #include "acp.h"
- 
- #define PLAYBACK_MIN_NUM_PERIODS    2
-@@ -35,6 +35,13 @@
- #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
- #define MIN_BUFFER MAX_BUFFER
- 
-+#define ST_PLAYBACK_MAX_PERIOD_SIZE 8192
-+#define ST_CAPTURE_MAX_PERIOD_SIZE  ST_PLAYBACK_MAX_PERIOD_SIZE
-+#define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
-+#define ST_MIN_BUFFER ST_MAX_BUFFER
-+
-+#define DRV_NAME "acp_audio_dma"
-+
- static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
- 	.info = SNDRV_PCM_INFO_INTERLEAVED |
- 		SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
-@@ -73,10 +80,42 @@ static const struct snd_pcm_hardware acp
- 	.periods_max = CAPTURE_MAX_NUM_PERIODS,
- };
- 
--struct audio_drv_data {
--	struct snd_pcm_substream *play_stream;
--	struct snd_pcm_substream *capture_stream;
--	void __iomem *acp_mmio;
-+static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = {
-+	.info = SNDRV_PCM_INFO_INTERLEAVED |
-+		SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
-+		SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
-+		SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
-+	.formats = SNDRV_PCM_FMTBIT_S16_LE |
-+		SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
-+	.channels_min = 1,
-+	.channels_max = 8,
-+	.rates = SNDRV_PCM_RATE_8000_96000,
-+	.rate_min = 8000,
-+	.rate_max = 96000,
-+	.buffer_bytes_max = ST_MAX_BUFFER,
-+	.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
-+	.period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE,
-+	.periods_min = PLAYBACK_MIN_NUM_PERIODS,
-+	.periods_max = PLAYBACK_MAX_NUM_PERIODS,
-+};
-+
-+static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = {
-+	.info = SNDRV_PCM_INFO_INTERLEAVED |
-+		SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
-+		SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
-+		SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
-+	.formats = SNDRV_PCM_FMTBIT_S16_LE |
-+		SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
-+	.channels_min = 1,
-+	.channels_max = 2,
-+	.rates = SNDRV_PCM_RATE_8000_48000,
-+	.rate_min = 8000,
-+	.rate_max = 48000,
-+	.buffer_bytes_max = ST_MAX_BUFFER,
-+	.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
-+	.period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE,
-+	.periods_min = CAPTURE_MIN_NUM_PERIODS,
-+	.periods_max = CAPTURE_MAX_NUM_PERIODS,
- };
- 
- static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
-@@ -143,8 +182,8 @@ static void config_dma_descriptor_in_sra
-  * system memory <-> ACP SRAM
-  */
- static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
--					   u32 size, int direction,
--					   u32 pte_offset)
-+					u32 size, int direction,
-+					u32 pte_offset, u32 asic_type)
- {
- 	u16 i;
- 	u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
-@@ -154,24 +193,46 @@ static void set_acp_sysmem_dma_descripto
- 		dmadscr[i].xfer_val = 0;
- 		if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
- 			dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12 + i;
--			dmadscr[i].dest = ACP_SHARED_RAM_BANK_1_ADDRESS +
--					(size / 2) - (i * (size/2));
-+			dmadscr[i].dest = ACP_SHARED_RAM_BANK_1_ADDRESS
-+					+ (i * (size/2));
- 			dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
- 				+ (pte_offset * SZ_4K) + (i * (size/2));
--			dmadscr[i].xfer_val |=
--			(ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM << 16) |
--			(size / 2);
-+			switch (asic_type) {
-+			case CHIP_STONEY:
-+				dmadscr[i].xfer_val |=
-+				(ACP_DMA_ATTRIBUTES_DAGB_GARLIC_TO_SHAREDMEM  << 16) |
-+				(size / 2);
-+				break;
-+			default:
-+				dmadscr[i].xfer_val |=
-+				(ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM  << 16) |
-+				(size / 2);
-+			}
- 		} else {
- 			dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14 + i;
--			dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS +
--					(i * (size/2));
--			dmadscr[i].dest = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
--						+ (pte_offset * SZ_4K) +
--						(i * (size/2));
--			dmadscr[i].xfer_val |=
--			BIT(22) |
--			(ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) |
--			(size / 2);
-+			switch (asic_type) {
-+			case CHIP_STONEY:
-+				dmadscr[i].src = ACP_SHARED_RAM_BANK_3_ADDRESS +
-+				(i * (size/2));
-+				dmadscr[i].dest =
-+				ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
-+				(pte_offset * SZ_4K) + (i * (size/2));
-+				dmadscr[i].xfer_val |=
-+				BIT(22) |
-+				(ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC << 16) |
-+				(size / 2);
-+				break;
-+			default:
-+				dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS +
-+				(i * (size/2));
-+				dmadscr[i].dest =
-+				ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
-+				(pte_offset * SZ_4K) + (i * (size/2));
-+				dmadscr[i].xfer_val |=
-+				BIT(22) |
-+				(ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) |
-+				(size / 2);
-+			}
- 		}
- 		config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
- 						&dmadscr[i]);
-@@ -192,7 +253,8 @@ static void set_acp_sysmem_dma_descripto
-  * ACP SRAM <-> I2S
-  */
- static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio,
--					   u32 size, int direction)
-+					u32 size, int direction,
-+					u32 asic_type)
- {
- 
- 	u16 i;
-@@ -213,8 +275,17 @@ static void set_acp_to_i2s_dma_descripto
- 			dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15 + i;
- 			/* dmadscr[i].src is unused by hardware. */
- 			dmadscr[i].src = 0;
--			dmadscr[i].dest = ACP_SHARED_RAM_BANK_5_ADDRESS +
-+			switch (asic_type) {
-+			case CHIP_STONEY:
-+				dmadscr[i].dest =
-+					 ACP_SHARED_RAM_BANK_3_ADDRESS +
- 					(i * (size / 2));
-+				break;
-+			default:
-+				dmadscr[i].dest =
-+					 ACP_SHARED_RAM_BANK_5_ADDRESS +
-+					(i * (size / 2));
-+			}
- 			dmadscr[i].xfer_val |= BIT(22) |
- 					(FROM_ACP_I2S_1 << 16) | (size / 2);
- 		}
-@@ -270,7 +341,8 @@ static void acp_pte_config(void __iomem
- }
- 
- static void config_acp_dma(void __iomem *acp_mmio,
--			   struct audio_substream_data *audio_config)
-+			struct audio_substream_data *audio_config,
-+			u32 asic_type)
- {
- 	u32 pte_offset;
- 
-@@ -284,11 +356,11 @@ static void config_acp_dma(void __iomem
- 
- 	/* Configure System memory <-> ACP SRAM DMA descriptors */
- 	set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size,
--				       audio_config->direction, pte_offset);
-+				audio_config->direction, pte_offset, asic_type);
- 
- 	/* Configure ACP SRAM <-> I2S DMA descriptors */
- 	set_acp_to_i2s_dma_descriptors(acp_mmio, audio_config->size,
--					audio_config->direction);
-+				audio_config->direction, asic_type);
- }
- 
- /* Start a given DMA channel transfer */
-@@ -425,7 +497,7 @@ static void acp_set_sram_bank_state(void
- }
- 
- /* Initialize and bring ACP hardware to default state. */
--static int acp_init(void __iomem *acp_mmio)
-+static int acp_init(void __iomem *acp_mmio, u32 asic_type)
- {
- 	u16 bank;
- 	u32 val, count, sram_pte_offset;
-@@ -499,10 +571,21 @@ static int acp_init(void __iomem *acp_mm
-        /* When ACP_TILE_P1 is turned on, all SRAM banks get turned on.
- 	* Now, turn off all of them. This can't be done in 'poweron' of
- 	* ACP pm domain, as this requires ACP to be initialized.
-+	* For Stoney, Memory gating is disabled,i.e SRAM Banks
-+	* won't be turned off. The default state for SRAM banks is ON.
-+	* Setting SRAM bank state code skipped for STONEY platform.
- 	*/
--	for (bank = 1; bank < 48; bank++)
--		acp_set_sram_bank_state(acp_mmio, bank, false);
-+	if (asic_type != CHIP_STONEY) {
-+		for (bank = 1; bank < 48; bank++)
-+			acp_set_sram_bank_state(acp_mmio, bank, false);
-+	}
- 
-+	/* Stoney supports 16bit resolution */
-+	if (asic_type == CHIP_STONEY) {
-+		val = acp_reg_read(acp_mmio, mmACP_I2S_16BIT_RESOLUTION_EN);
-+		val |= 0x03;
-+		acp_reg_write(val, acp_mmio, mmACP_I2S_16BIT_RESOLUTION_EN);
-+	}
- 	return 0;
- }
- 
-@@ -572,9 +655,9 @@ static irqreturn_t dma_irq_handler(int i
- 		valid_irq = true;
- 		if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_13) ==
- 				PLAYBACK_START_DMA_DESCR_CH13)
--			dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
--		else
- 			dscr_idx = PLAYBACK_END_DMA_DESCR_CH12;
-+		else
-+			dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
- 		config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, dscr_idx,
- 				       1, 0);
- 		acp_dma_start(acp_mmio, SYSRAM_TO_ACP_CH_NUM, false);
-@@ -626,10 +709,23 @@ static int acp_dma_open(struct snd_pcm_s
- 	if (adata == NULL)
- 		return -ENOMEM;
- 
--	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
--		runtime->hw = acp_pcm_hardware_playback;
--	else
--		runtime->hw = acp_pcm_hardware_capture;
-+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-+		switch (intr_data->asic_type) {
-+		case CHIP_STONEY:
-+			runtime->hw = acp_st_pcm_hardware_playback;
-+			break;
-+		default:
-+			runtime->hw = acp_pcm_hardware_playback;
-+		}
-+	} else {
-+		switch (intr_data->asic_type) {
-+		case CHIP_STONEY:
-+			runtime->hw = acp_st_pcm_hardware_capture;
-+			break;
-+		default:
-+			runtime->hw = acp_pcm_hardware_capture;
-+		}
-+	}
- 
- 	ret = snd_pcm_hw_constraint_integer(runtime,
- 					    SNDRV_PCM_HW_PARAM_PERIODS);
-@@ -652,14 +748,22 @@ static int acp_dma_open(struct snd_pcm_s
- 
- 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- 		intr_data->play_stream = substream;
--		for (bank = 1; bank <= 4; bank++)
--			acp_set_sram_bank_state(intr_data->acp_mmio, bank,
--						true);
-+		/* For Stoney, Memory gating is disabled,i.e SRAM Banks
-+		 * won't be turned off. The default state for SRAM banks is ON.
-+		 * Setting SRAM bank state code skipped for STONEY platform.
-+		 */
-+		if (intr_data->asic_type != CHIP_STONEY) {
-+			for (bank = 1; bank <= 4; bank++)
-+				acp_set_sram_bank_state(intr_data->acp_mmio,
-+							bank, true);
-+		}
- 	} else {
- 		intr_data->capture_stream = substream;
--		for (bank = 5; bank <= 8; bank++)
--			acp_set_sram_bank_state(intr_data->acp_mmio, bank,
--						true);
-+		if (intr_data->asic_type != CHIP_STONEY) {
-+			for (bank = 5; bank <= 8; bank++)
-+				acp_set_sram_bank_state(intr_data->acp_mmio,
-+							bank, true);
-+		}
- 	}
- 
- 	return 0;
-@@ -673,6 +777,8 @@ static int acp_dma_hw_params(struct snd_
- 	struct page *pg;
- 	struct snd_pcm_runtime *runtime;
- 	struct audio_substream_data *rtd;
-+	struct snd_soc_pcm_runtime *prtd = substream->private_data;
-+	struct audio_drv_data *adata = dev_get_drvdata(prtd->platform->dev);
- 
- 	runtime = substream->runtime;
- 	rtd = runtime->private_data;
-@@ -700,7 +806,7 @@ static int acp_dma_hw_params(struct snd_
- 		rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
- 		rtd->direction = substream->stream;
- 
--		config_acp_dma(rtd->acp_mmio, rtd);
-+		config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type);
- 		status = 0;
- 	} else {
- 		status = -ENOMEM;
-@@ -713,40 +819,48 @@ static int acp_dma_hw_free(struct snd_pc
- 	return snd_pcm_lib_free_pages(substream);
- }
- 
-+static u64 acp_get_byte_count(void __iomem *acp_mmio, int stream)
-+{
-+	union acp_dma_count playback_dma_count;
-+	union acp_dma_count capture_dma_count;
-+	u64 bytescount = 0;
-+
-+	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
-+		playback_dma_count.bcount.high = acp_reg_read(acp_mmio,
-+					mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH);
-+		playback_dma_count.bcount.low  = acp_reg_read(acp_mmio,
-+					mmACP_I2S_TRANSMIT_BYTE_CNT_LOW);
-+		bytescount = playback_dma_count.bytescount;
-+	} else {
-+		capture_dma_count.bcount.high = acp_reg_read(acp_mmio,
-+					mmACP_I2S_RECEIVED_BYTE_CNT_HIGH);
-+		capture_dma_count.bcount.low  = acp_reg_read(acp_mmio,
-+					mmACP_I2S_RECEIVED_BYTE_CNT_LOW);
-+		bytescount = capture_dma_count.bytescount;
-+	}
-+	return bytescount;
-+}
-+
- static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream)
- {
--	u16 dscr;
--	u32 mul, dma_config, period_bytes;
-+	u32 buffersize;
- 	u32 pos = 0;
-+	u64 bytescount = 0;
- 
- 	struct snd_pcm_runtime *runtime = substream->runtime;
- 	struct audio_substream_data *rtd = runtime->private_data;
- 
--	period_bytes = frames_to_bytes(runtime, runtime->period_size);
--	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
--		dscr = acp_reg_read(rtd->acp_mmio, mmACP_DMA_CUR_DSCR_13);
-+	buffersize = frames_to_bytes(runtime, runtime->buffer_size);
-+	bytescount = acp_get_byte_count(rtd->acp_mmio, substream->stream);
- 
--		if (dscr == PLAYBACK_START_DMA_DESCR_CH13)
--			mul = 0;
--		else
--			mul = 1;
--		pos =  (mul * period_bytes);
-+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-+		if (bytescount > rtd->renderbytescount)
-+			bytescount = bytescount - rtd->renderbytescount;
- 	} else {
--		dma_config = acp_reg_read(rtd->acp_mmio, mmACP_DMA_CNTL_14);
--		if (dma_config != 0) {
--			dscr = acp_reg_read(rtd->acp_mmio,
--						mmACP_DMA_CUR_DSCR_14);
--			if (dscr == CAPTURE_START_DMA_DESCR_CH14)
--				mul = 1;
--			else
--				mul = 2;
--			pos = (mul * period_bytes);
--		}
--
--		if (pos >= (2 * period_bytes))
--			pos = 0;
--
-+		if (bytescount > rtd->capturebytescount)
-+			bytescount = bytescount - rtd->capturebytescount;
- 	}
-+	pos = do_div(bytescount, buffersize);
- 	return bytes_to_frames(runtime, pos);
- }
- 
-@@ -768,23 +882,6 @@ static int acp_dma_prepare(struct snd_pc
- 		config_acp_dma_channel(rtd->acp_mmio, ACP_TO_I2S_DMA_CH_NUM,
- 					PLAYBACK_START_DMA_DESCR_CH13,
- 					NUM_DSCRS_PER_CHANNEL, 0);
--		/* Fill ACP SRAM (2 periods) with zeros from System RAM
--		 * which is zero-ed in hw_params
--		*/
--		acp_dma_start(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, false);
--
--		/* ACP SRAM (2 periods of buffer size) is intially filled with
--		 * zeros. Before rendering starts, 2nd half of SRAM will be
--		 * filled with valid audio data DMA'ed from first half of system
--		 * RAM and 1st half of SRAM will be filled with Zeros. This is
--		 * the initial scenario when redering starts from SRAM. Later
--		 * on, 2nd half of system memory will be DMA'ed to 1st half of
--		 * SRAM, 1st half of system memory will be DMA'ed to 2nd half of
--		 * SRAM in ping-pong way till rendering stops.
--		*/
--		config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM,
--					PLAYBACK_START_DMA_DESCR_CH12,
--					1, 0);
- 	} else {
- 		config_acp_dma_channel(rtd->acp_mmio, ACP_TO_SYSRAM_CH_NUM,
- 					CAPTURE_START_DMA_DESCR_CH14,
-@@ -799,7 +896,8 @@ static int acp_dma_prepare(struct snd_pc
- static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
- {
- 	int ret;
--	u32 loops = 1000;
-+	u32 loops = 4000;
-+	u64 bytescount = 0;
- 
- 	struct snd_pcm_runtime *runtime = substream->runtime;
- 	struct snd_soc_pcm_runtime *prtd = substream->private_data;
-@@ -811,7 +909,11 @@ static int acp_dma_trigger(struct snd_pc
- 	case SNDRV_PCM_TRIGGER_START:
- 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
- 	case SNDRV_PCM_TRIGGER_RESUME:
-+		bytescount = acp_get_byte_count(rtd->acp_mmio,
-+						substream->stream);
- 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-+			if (rtd->renderbytescount == 0)
-+				rtd->renderbytescount = bytescount;
- 			acp_dma_start(rtd->acp_mmio,
- 						SYSRAM_TO_ACP_CH_NUM, false);
- 			while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) &
-@@ -828,6 +930,8 @@ static int acp_dma_trigger(struct snd_pc
- 					ACP_TO_I2S_DMA_CH_NUM, true);
- 
- 		} else {
-+			if (rtd->capturebytescount == 0)
-+				rtd->capturebytescount = bytescount;
- 			acp_dma_start(rtd->acp_mmio,
- 					    I2S_TO_ACP_DMA_CH_NUM, true);
- 		}
-@@ -841,12 +945,15 @@ static int acp_dma_trigger(struct snd_pc
- 		 * channels will stopped automatically after its transfer
- 		 * completes : SYSRAM_TO_ACP_CH_NUM / ACP_TO_SYSRAM_CH_NUM
- 		 */
--		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- 			ret = acp_dma_stop(rtd->acp_mmio,
- 					ACP_TO_I2S_DMA_CH_NUM);
--		else
-+			rtd->renderbytescount = 0;
-+		} else {
- 			ret = acp_dma_stop(rtd->acp_mmio,
- 					I2S_TO_ACP_DMA_CH_NUM);
-+			rtd->capturebytescount = 0;
-+		}
- 		break;
- 	default:
- 		ret = -EINVAL;
-@@ -857,10 +964,27 @@ static int acp_dma_trigger(struct snd_pc
- 
- static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)
- {
--	return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
-+	int ret;
-+	struct audio_drv_data *adata = dev_get_drvdata(rtd->platform->dev);
-+
-+	switch (adata->asic_type) {
-+	case CHIP_STONEY:
-+		ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
-+							SNDRV_DMA_TYPE_DEV,
-+							NULL, ST_MIN_BUFFER,
-+							ST_MAX_BUFFER);
-+		break;
-+	default:
-+		ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
- 							SNDRV_DMA_TYPE_DEV,
- 							NULL, MIN_BUFFER,
- 							MAX_BUFFER);
-+		break;
-+	}
-+	if (ret < 0)
-+		dev_err(rtd->platform->dev,
-+				"buffer preallocation failer error:%d\n", ret);
-+	return ret;
- }
- 
- static int acp_dma_close(struct snd_pcm_substream *substream)
-@@ -875,14 +999,23 @@ static int acp_dma_close(struct snd_pcm_
- 
- 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- 		adata->play_stream = NULL;
--		for (bank = 1; bank <= 4; bank++)
--			acp_set_sram_bank_state(adata->acp_mmio, bank,
--						false);
--	} else {
-+		/* For Stoney, Memory gating is disabled,i.e SRAM Banks
-+		 * won't be turned off. The default state for SRAM banks is ON.
-+		 * Setting SRAM bank state code skipped for STONEY platform.
-+		 * added condition checks for Carrizo platform only
-+		 */
-+		if (adata->asic_type != CHIP_STONEY) {
-+			for (bank = 1; bank <= 4; bank++)
-+				acp_set_sram_bank_state(adata->acp_mmio, bank,
-+				false);
-+		}
-+	} else  {
- 		adata->capture_stream = NULL;
--		for (bank = 5; bank <= 8; bank++)
--			acp_set_sram_bank_state(adata->acp_mmio, bank,
--						false);
-+		if (adata->asic_type != CHIP_STONEY) {
-+			for (bank = 5; bank <= 8; bank++)
-+				acp_set_sram_bank_state(adata->acp_mmio, bank,
-+						     false);
-+		}
- 	}
- 
- 	/* Disable ACP irq, when the current stream is being closed and
-@@ -916,6 +1049,7 @@ static int acp_audio_probe(struct platfo
- 	int status;
- 	struct audio_drv_data *audio_drv_data;
- 	struct resource *res;
-+	const u32 *pdata = pdev->dev.platform_data;
- 
- 	audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),
- 					GFP_KERNEL);
-@@ -932,6 +1066,7 @@ static int acp_audio_probe(struct platfo
- 
- 	audio_drv_data->play_stream = NULL;
- 	audio_drv_data->capture_stream = NULL;
-+	audio_drv_data->asic_type =  *pdata;
- 
- 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- 	if (!res) {
-@@ -949,7 +1084,7 @@ static int acp_audio_probe(struct platfo
- 	dev_set_drvdata(&pdev->dev, audio_drv_data);
- 
- 	/* Initialize the ACP */
--	acp_init(audio_drv_data->acp_mmio);
-+	acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);
- 
- 	status = snd_soc_register_platform(&pdev->dev, &acp_asoc_platform);
- 	if (status != 0) {
-@@ -980,21 +1115,31 @@ static int acp_pcm_resume(struct device
- 	u16 bank;
- 	struct audio_drv_data *adata = dev_get_drvdata(dev);
- 
--	acp_init(adata->acp_mmio);
-+	acp_init(adata->acp_mmio, adata->asic_type);
- 
- 	if (adata->play_stream && adata->play_stream->runtime) {
--		for (bank = 1; bank <= 4; bank++)
--			acp_set_sram_bank_state(adata->acp_mmio, bank,
-+		/* For Stoney, Memory gating is disabled,i.e SRAM Banks
-+		 * won't be turned off. The default state for SRAM banks is ON.
-+		 * Setting SRAM bank state code skipped for STONEY platform.
-+		 */
-+		if (adata->asic_type != CHIP_STONEY) {
-+			for (bank = 1; bank <= 4; bank++)
-+				acp_set_sram_bank_state(adata->acp_mmio, bank,
- 						true);
-+		}
- 		config_acp_dma(adata->acp_mmio,
--				adata->play_stream->runtime->private_data);
-+			adata->play_stream->runtime->private_data,
-+			adata->asic_type);
- 	}
- 	if (adata->capture_stream && adata->capture_stream->runtime) {
--		for (bank = 5; bank <= 8; bank++)
--			acp_set_sram_bank_state(adata->acp_mmio, bank,
-+		if (adata->asic_type != CHIP_STONEY) {
-+			for (bank = 5; bank <= 8; bank++)
-+				acp_set_sram_bank_state(adata->acp_mmio, bank,
- 						true);
-+		}
- 		config_acp_dma(adata->acp_mmio,
--				adata->capture_stream->runtime->private_data);
-+			adata->capture_stream->runtime->private_data,
-+			adata->asic_type);
- 	}
- 	acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
- 	return 0;
-@@ -1013,7 +1158,7 @@ static int acp_pcm_runtime_resume(struct
- {
- 	struct audio_drv_data *adata = dev_get_drvdata(dev);
- 
--	acp_init(adata->acp_mmio);
-+	acp_init(adata->acp_mmio, adata->asic_type);
- 	acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
- 	return 0;
- }
-@@ -1028,14 +1173,15 @@ static struct platform_driver acp_dma_dr
- 	.probe = acp_audio_probe,
- 	.remove = acp_audio_remove,
- 	.driver = {
--		.name = "acp_audio_dma",
-+		.name = DRV_NAME,
- 		.pm = &acp_pm_ops,
- 	},
- };
- 
- module_platform_driver(acp_dma_driver);
- 
-+MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
- MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
- MODULE_DESCRIPTION("AMD ACP PCM Driver");
- MODULE_LICENSE("GPL v2");
--MODULE_ALIAS("platform:acp-dma-audio");
-+MODULE_ALIAS("platform:"DRV_NAME);
---- linux-4.14/sound/soc/amd/acp-rt5645.c.0130~	2017-12-14 06:39:58.533903650 +0100
-+++ linux-4.14/sound/soc/amd/acp-rt5645.c	2017-12-14 06:39:58.533903650 +0100
-@@ -0,0 +1,199 @@
-+/*
-+ * Machine driver for AMD ACP Audio engine using Realtek RT5645 codec
-+ *
-+ * Copyright 2017 Advanced Micro Devices, Inc.
-+ *
-+ * This file is modified from rt288 machine driver
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ *
-+ */
-+
-+#include <sound/core.h>
-+#include <sound/soc.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc-dapm.h>
-+#include <sound/jack.h>
-+#include <linux/gpio.h>
-+#include <linux/module.h>
-+#include <linux/i2c.h>
-+#include <linux/acpi.h>
-+
-+#include "../codecs/rt5645.h"
-+
-+#define CZ_PLAT_CLK 24000000
-+
-+static struct snd_soc_jack cz_jack;
-+
-+static int cz_aif1_hw_params(struct snd_pcm_substream *substream,
-+			     struct snd_pcm_hw_params *params)
-+{
-+	int ret = 0;
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+
-+	ret = snd_soc_dai_set_pll(codec_dai, 0, RT5645_PLL1_S_MCLK,
-+				  CZ_PLAT_CLK, params_rate(params) * 512);
-+	if (ret < 0) {
-+		dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
-+		return ret;
-+	}
-+
-+	ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_PLL1,
-+				params_rate(params) * 512, SND_SOC_CLOCK_OUT);
-+	if (ret < 0) {
-+		dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret);
-+		return ret;
-+	}
-+
-+	return ret;
-+}
-+
-+static int cz_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	int ret;
-+	struct snd_soc_card *card;
-+	struct snd_soc_codec *codec;
-+
-+	codec = rtd->codec;
-+	card = rtd->card;
-+
-+	ret = snd_soc_card_jack_new(card, "Headset Jack",
-+				SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
-+				SND_JACK_BTN_0 | SND_JACK_BTN_1 |
-+				SND_JACK_BTN_2 | SND_JACK_BTN_3,
-+				&cz_jack, NULL, 0);
-+	if (ret) {
-+		dev_err(card->dev, "HP jack creation failed %d\n", ret);
-+		return ret;
-+	}
-+
-+	rt5645_set_jack_detect(codec, &cz_jack, &cz_jack, &cz_jack);
-+
-+	return 0;
-+}
-+
-+static struct snd_soc_ops cz_aif1_ops = {
-+	.hw_params = cz_aif1_hw_params,
-+};
-+
-+static struct snd_soc_dai_link cz_dai_rt5650[] = {
-+	{
-+		.name = "amd-rt5645-play",
-+		.stream_name = "RT5645_AIF1",
-+		.platform_name = "acp_audio_dma.0.auto",
-+		.cpu_dai_name = "designware-i2s.1.auto",
-+		.codec_dai_name = "rt5645-aif1",
-+		.codec_name = "i2c-10EC5650:00",
-+		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
-+				| SND_SOC_DAIFMT_CBM_CFM,
-+		.init = cz_init,
-+		.ops = &cz_aif1_ops,
-+	},
-+	{
-+		.name = "amd-rt5645-cap",
-+		.stream_name = "RT5645_AIF1",
-+		.platform_name = "acp_audio_dma.0.auto",
-+		.cpu_dai_name = "designware-i2s.2.auto",
-+		.codec_dai_name = "rt5645-aif1",
-+		.codec_name = "i2c-10EC5650:00",
-+		.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
-+				| SND_SOC_DAIFMT_CBM_CFM,
-+		.ops = &cz_aif1_ops,
-+	},
-+};
-+
-+static const struct snd_soc_dapm_widget cz_widgets[] = {
-+	SND_SOC_DAPM_HP("Headphones", NULL),
-+	SND_SOC_DAPM_SPK("Speakers", NULL),
-+	SND_SOC_DAPM_MIC("Headset Mic", NULL),
-+	SND_SOC_DAPM_MIC("Int Mic", NULL),
-+};
-+
-+static const struct snd_soc_dapm_route cz_audio_route[] = {
-+	{"Headphones", NULL, "HPOL"},
-+	{"Headphones", NULL, "HPOR"},
-+	{"RECMIXL", NULL, "Headset Mic"},
-+	{"RECMIXR", NULL, "Headset Mic"},
-+	{"Speakers", NULL, "SPOL"},
-+	{"Speakers", NULL, "SPOR"},
-+	{"DMIC L2", NULL, "Int Mic"},
-+	{"DMIC R2", NULL, "Int Mic"},
-+};
-+
-+static const struct snd_kcontrol_new cz_mc_controls[] = {
-+	SOC_DAPM_PIN_SWITCH("Headphones"),
-+	SOC_DAPM_PIN_SWITCH("Speakers"),
-+	SOC_DAPM_PIN_SWITCH("Headset Mic"),
-+	SOC_DAPM_PIN_SWITCH("Int Mic"),
-+};
-+
-+static struct snd_soc_card cz_card = {
-+	.name = "acprt5650",
-+	.owner = THIS_MODULE,
-+	.dai_link = cz_dai_rt5650,
-+	.num_links = ARRAY_SIZE(cz_dai_rt5650),
-+	.dapm_widgets = cz_widgets,
-+	.num_dapm_widgets = ARRAY_SIZE(cz_widgets),
-+	.dapm_routes = cz_audio_route,
-+	.num_dapm_routes = ARRAY_SIZE(cz_audio_route),
-+	.controls = cz_mc_controls,
-+	.num_controls = ARRAY_SIZE(cz_mc_controls),
-+};
-+
-+static int cz_probe(struct platform_device *pdev)
-+{
-+	int ret;
-+	struct snd_soc_card *card;
-+
-+	card = &cz_card;
-+	cz_card.dev = &pdev->dev;
-+	platform_set_drvdata(pdev, card);
-+	ret = devm_snd_soc_register_card(&pdev->dev, &cz_card);
-+	if (ret) {
-+		dev_err(&pdev->dev,
-+				"devm_snd_soc_register_card(%s) failed: %d\n",
-+				cz_card.name, ret);
-+		return ret;
-+	}
-+	return 0;
-+}
-+
-+static const struct acpi_device_id cz_audio_acpi_match[] = {
-+	{ "AMDI1002", 0 },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(acpi, cz_audio_acpi_match);
-+
-+static struct platform_driver cz_pcm_driver = {
-+	.driver = {
-+		.name = "cz-rt5645",
-+		.acpi_match_table = ACPI_PTR(cz_audio_acpi_match),
-+		.pm = &snd_soc_pm_ops,
-+	},
-+	.probe = cz_probe,
-+};
-+
-+module_platform_driver(cz_pcm_driver);
-+
-+MODULE_AUTHOR("akshu.agrawal@amd.com");
-+MODULE_DESCRIPTION("cz-rt5645 audio support");
-+MODULE_LICENSE("GPL v2");
---- linux-4.14/sound/soc/amd/Kconfig.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/sound/soc/amd/Kconfig	2017-12-14 06:39:58.533903650 +0100
-@@ -2,3 +2,15 @@ config SND_SOC_AMD_ACP
- 	tristate "AMD Audio Coprocessor support"
- 	help
- 	 This option enables ACP DMA support on AMD platform.
-+
-+config SND_SOC_AMD_CZ_RT5645_MACH
-+	tristate "AMD CZ support for RT5645"
-+	select SND_SOC_RT5645
-+	depends on SND_SOC_AMD_ACP && I2C
-+	help
-+	 This option enables machine driver for rt5645.
-+
-+config SND_SOC_AMD_ACP3x
-+	tristate "AMD Audio Coprocessor-v3.x support"
-+	help
-+	 This option enables ACP v3.x I2S support on AMD platform.
---- linux-4.14/sound/soc/amd/Makefile.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/sound/soc/amd/Makefile	2017-12-14 06:39:58.533903650 +0100
-@@ -1,3 +1,6 @@
--snd-soc-acp-pcm-objs	:= acp-pcm-dma.o
-+acp_audio_dma-objs := acp-pcm-dma.o
-+snd-soc-acp-rt5645-mach-objs := acp-rt5645.o
- 
--obj-$(CONFIG_SND_SOC_AMD_ACP) += snd-soc-acp-pcm.o
-+obj-$(CONFIG_SND_SOC_AMD_ACP) += acp_audio_dma.o
-+obj-$(CONFIG_SND_SOC_AMD_CZ_RT5645_MACH) += snd-soc-acp-rt5645-mach.o
-+obj-$(CONFIG_SND_SOC_AMD_ACP3x) += raven/
---- linux-4.14/sound/soc/amd/raven/acp3x-dummy5102.c.0130~	2017-12-14 06:39:58.533903650 +0100
-+++ linux-4.14/sound/soc/amd/raven/acp3x-dummy5102.c	2017-12-14 06:39:58.533903650 +0100
-@@ -0,0 +1,172 @@
-+/*
-+ * Machine driver for AMD ACP Audio engine using dummy codec
-+ *
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ *
-+ */
-+
-+#include <sound/soc.h>
-+#include <sound/soc-dapm.h>
-+#include <linux/module.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+
-+static int acp3x_hw_params(struct snd_pcm_substream *substream,
-+				struct snd_pcm_hw_params *params)
-+
-+{
-+      struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+      struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+      unsigned int fmt;
-+      unsigned int slot_width;
-+      unsigned int channels;
-+      int ret = 0;
-+
-+      fmt = params_format(params);
-+      switch (fmt) {
-+	case SNDRV_PCM_FORMAT_S16_LE:
-+		slot_width = 16;
-+		break;
-+	case SNDRV_PCM_FORMAT_S24_LE:
-+		slot_width = 32;
-+		break;
-+	case SNDRV_PCM_FORMAT_S32_LE:
-+                slot_width = 32;
-+		break;
-+	default:
-+		printk(KERN_WARNING "acp3x: unsupported PCM format");
-+		return -EINVAL;
-+      }
-+
-+      channels = params_channels(params);
-+
-+      if (channels == 0x04) {
-+                ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0x3, 0x3, 4, slot_width);
-+                if (ret < 0)
-+                       return ret;
-+      } else {
-+               ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0x3, 0x3, 2, slot_width);
-+               if (ret < 0)
-+                       return ret;
-+      }
-+      return 0;
-+}
-+
-+static struct snd_soc_ops acp3x_wm5102_ops = {
-+	.hw_params = acp3x_hw_params,
-+};
-+
-+static int acp3x_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	return 0;
-+}
-+
-+static struct snd_soc_dai_link acp3x_dai_w5102[] = {
-+	{
-+		.name = "RV-W5102-PLAY",
-+		.stream_name = "Playback",
-+		.platform_name = "acp3x_rv_i2s.0",
-+		.cpu_dai_name = "acp3x_rv_i2s.0",
-+		.codec_dai_name = "dummy_w5102_dai",
-+		.codec_name = "dummy_w5102.0",
-+                .dai_fmt = SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_NB_NF
-+				| SND_SOC_DAIFMT_CBM_CFM,
-+		.ops = &acp3x_wm5102_ops,
-+		.init = acp3x_init,
-+	},
-+};
-+
-+static const struct snd_soc_dapm_widget acp3x_widgets[] = {
-+	SND_SOC_DAPM_HP("Headphones", NULL),
-+	SND_SOC_DAPM_MIC("Analog Mic", NULL),
-+};
-+
-+static const struct snd_soc_dapm_route acp3x_audio_route[] = {
-+	{"Headphones", NULL, "HPO L"},
-+	{"Headphones", NULL, "HPO R"},
-+	{"MIC1", NULL, "Analog Mic"},
-+};
-+
-+static struct snd_soc_card acp3x_card = {
-+	.name = "acp3x",
-+	.owner = THIS_MODULE,
-+	.dai_link = acp3x_dai_w5102,
-+	.num_links = 1,
-+};
-+
-+static int acp3x_probe(struct platform_device *pdev)
-+{
-+	int ret;
-+	struct acp_wm5102 *machine = NULL;
-+	struct snd_soc_card *card;
-+
-+	card = &acp3x_card;
-+	acp3x_card.dev = &pdev->dev;
-+
-+	platform_set_drvdata(pdev, card);
-+	snd_soc_card_set_drvdata(card, machine);
-+
-+	ret = snd_soc_register_card(card);
-+	if (ret) {
-+		dev_err(&pdev->dev,
-+				"snd_soc_register_card(%s) failed: %d\n",
-+				acp3x_card.name, ret);
-+		return ret;
-+	}
-+	return 0;
-+}
-+
-+static int acp3x_remove(struct platform_device *pdev)
-+{
-+	struct snd_soc_card *card;
-+
-+	card = platform_get_drvdata(pdev);
-+	snd_soc_unregister_card(card);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver acp3x_mach_driver = {
-+	.driver = {
-+		.name = "acp3x_w5102_mach",
-+		.pm = &snd_soc_pm_ops,
-+	},
-+	.probe = acp3x_probe,
-+	.remove = acp3x_remove,
-+};
-+
-+static int __init acp3x_audio_init(void)
-+{
-+	platform_driver_register(&acp3x_mach_driver);
-+	return 0;
-+}
-+
-+static void __exit acp3x_audio_exit(void)
-+{
-+	platform_driver_unregister(&acp3x_mach_driver);
-+}
-+
-+module_init(acp3x_audio_init);
-+module_exit(acp3x_audio_exit);
-+
-+MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
-+MODULE_LICENSE("GPL v2");
---- linux-4.14/sound/soc/amd/raven/acp3x.h.0130~	2017-12-14 06:39:58.533903650 +0100
-+++ linux-4.14/sound/soc/amd/raven/acp3x.h	2017-12-14 06:39:58.533903650 +0100
-@@ -0,0 +1,34 @@
-+#include "chip_offset_byte.h"
-+
-+#define ACP3x_PHY_BASE_ADDRESS 0x1240000
-+#define	ACP3x_I2S_MODE	0
-+#define	ACP3x_REG_START	0x1240000
-+#define	ACP3x_REG_END	0x1250200
-+#define	BT_TX_THRESHOLD 26
-+#define	BT_RX_THRESHOLD 25
-+#define ACP_SRAM_PTE_OFFSET	0x02050000
-+#define PAGE_SIZE_4K_ENABLE 0x2
-+#define MEM_WINDOW_START	0x4000000
-+#define FRM_LEN 256
-+
-+#define PLAYBACK_MIN_NUM_PERIODS    2
-+#define PLAYBACK_MAX_NUM_PERIODS    2
-+#define PLAYBACK_MAX_PERIOD_SIZE    8192
-+#define PLAYBACK_MIN_PERIOD_SIZE    8192
-+#define CAPTURE_MIN_NUM_PERIODS     2
-+#define CAPTURE_MAX_NUM_PERIODS     2
-+#define CAPTURE_MAX_PERIOD_SIZE     8192
-+#define CAPTURE_MIN_PERIOD_SIZE     8192
-+
-+#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
-+#define MIN_BUFFER MAX_BUFFER
-+
-+static inline u32 rv_readl(void __iomem *base_addr)
-+{
-+	return readl(base_addr - ACP3x_PHY_BASE_ADDRESS);
-+}
-+
-+static inline void rv_writel(u32 val, void __iomem *base_addr)
-+{
-+	writel(val, base_addr - ACP3x_PHY_BASE_ADDRESS);
-+}
---- linux-4.14/sound/soc/amd/raven/acp3x-pcm-dma.c.0130~	2017-12-14 06:39:58.534903650 +0100
-+++ linux-4.14/sound/soc/amd/raven/acp3x-pcm-dma.c	2017-12-14 06:39:58.534903650 +0100
-@@ -0,0 +1,806 @@
-+/*
-+ * AMD ALSA SoC PCM Driver
-+ *
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <linux/module.h>
-+#include <linux/err.h>
-+#include <linux/pm_runtime.h>
-+
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/soc-dai.h>
-+
-+#include "acp3x.h"
-+
-+struct i2s_dev_data {
-+	bool tdm_mode;
-+	unsigned int i2s_irq;
-+	u32 tdm_fmt;
-+	void __iomem *acp3x_base;
-+	struct snd_pcm_substream *play_stream;
-+	struct snd_pcm_substream *capture_stream;
-+};
-+
-+struct i2s_stream_instance {
-+	u16 num_pages;
-+	u16 channels;
-+	u32 xfer_resolution;
-+	u32 val;
-+	struct page *pg;
-+	void __iomem *acp3x_base;
-+};
-+
-+static const struct snd_pcm_hardware acp3x_pcm_hardware_playback = {
-+	.info = SNDRV_PCM_INFO_INTERLEAVED |
-+		SNDRV_PCM_INFO_BLOCK_TRANSFER |
-+		SNDRV_PCM_INFO_BATCH |
-+		SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
-+	.formats = SNDRV_PCM_FMTBIT_S16_LE |  SNDRV_PCM_FMTBIT_S8 |
-+		   SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE |
-+		   SNDRV_PCM_FMTBIT_S32_LE,
-+	.channels_min = 2,
-+	.channels_max = 6,
-+	.rates = SNDRV_PCM_RATE_8000_96000,
-+	.rate_min = 8000,
-+	.rate_max = 96000,
-+	.buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
-+	.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
-+	.period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
-+	.periods_min = PLAYBACK_MIN_NUM_PERIODS,
-+	.periods_max = PLAYBACK_MAX_NUM_PERIODS,
-+};
-+
-+static const struct snd_pcm_hardware acp3x_pcm_hardware_capture = {
-+	.info = SNDRV_PCM_INFO_INTERLEAVED |
-+		SNDRV_PCM_INFO_BLOCK_TRANSFER |
-+		SNDRV_PCM_INFO_BATCH |
-+	    SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
-+	.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
-+		   SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE |
-+		   SNDRV_PCM_FMTBIT_S32_LE,
-+	.channels_min = 2,
-+	.channels_max = 2,
-+	.rates = SNDRV_PCM_RATE_8000_48000,
-+	.rate_min = 8000,
-+	.rate_max = 48000,
-+	.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
-+	.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
-+	.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
-+	.periods_min = CAPTURE_MIN_NUM_PERIODS,
-+	.periods_max = CAPTURE_MAX_NUM_PERIODS,
-+};
-+
-+static int acp3x_power_on(void __iomem *acp3x_base, bool on)
-+{
-+	u16 val, mask;
-+	u32 timeout;
-+
-+	if (on == true) {
-+		val = 1;
-+		mask = 0;
-+	} else {
-+		val = 0;
-+		mask = 2;
-+	}
-+
-+	rv_writel(val, acp3x_base + mmACP_PGFSM_CONTROL);
-+	timeout = 0;
-+	while (true) {
-+		val = rv_readl(acp3x_base + mmACP_PGFSM_STATUS);
-+		if ((val & 0x3) == mask)
-+			break;
-+		if (timeout > 100) {
-+			pr_err("ACP3x power state change failure\n");
-+			return -ENODEV;
-+		}
-+		timeout++;
-+		cpu_relax();
-+	}
-+	return 0;
-+}
-+
-+static int acp3x_reset(void __iomem *acp3x_base)
-+{
-+	u32 val, timeout;
-+
-+	rv_writel(1, acp3x_base + mmACP_SOFT_RESET);
-+	timeout = 0;
-+	while (true) {
-+		val = rv_readl(acp3x_base + mmACP_SOFT_RESET);
-+		if ((val & 0x00010001) || timeout > 100) {
-+			if (val & 0x00010001)
-+				break;
-+			return -ENODEV;
-+		}
-+		timeout++;
-+		cpu_relax();
-+	}
-+
-+	rv_writel(0, acp3x_base + mmACP_SOFT_RESET);
-+	timeout = 0;
-+	while (true) {
-+		val = rv_readl(acp3x_base + mmACP_SOFT_RESET);
-+		if (!val || timeout > 100) {
-+			if (!val)
-+				break;
-+			return -ENODEV;
-+		}
-+		timeout++;
-+		cpu_relax();
-+	}
-+	return 0;
-+}
-+
-+static int acp3x_init(void __iomem *acp3x_base)
-+{
-+	int ret;
-+
-+	/* power on */
-+	ret = acp3x_power_on(acp3x_base, true);
-+	if (ret) {
-+		pr_err("ACP3x power on failed\n");
-+		return ret;
-+	}
-+
-+	/* Reset */
-+	ret = acp3x_reset(acp3x_base);
-+	if (ret) {
-+		pr_err("ACP3x reset failed\n");
-+		return ret;
-+	}
-+
-+	pr_info("ACP Initialized\n");
-+	return 0;
-+}
-+
-+static int acp3x_deinit(void __iomem *acp3x_base)
-+{
-+	int ret;
-+
-+	/* Reset */
-+	ret = acp3x_reset(acp3x_base);
-+	if (ret) {
-+		pr_err("ACP3x reset failed\n");
-+		return ret;
-+	}
-+
-+	/* power off */
-+	ret = acp3x_power_on(acp3x_base, false);
-+	if (ret) {
-+		pr_err("ACP3x power off failed\n");
-+		return ret;
-+	}
-+
-+	pr_info("ACP De-Initialized\n");
-+	return 0;
-+}
-+
-+static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
-+{
-+	u16 play_flag, cap_flag;
-+	u32 val;
-+	struct i2s_dev_data *rv_i2s_data = dev_id;
-+
-+	if (rv_i2s_data == NULL)
-+		return IRQ_NONE;
-+
-+	play_flag = cap_flag = 0;
-+
-+	val = rv_readl(rv_i2s_data->acp3x_base + mmACP_EXTERNAL_INTR_STAT);
-+	if ((val & BIT(BT_TX_THRESHOLD)) && (rv_i2s_data->play_stream)) {
-+		rv_writel(BIT(BT_TX_THRESHOLD), rv_i2s_data->acp3x_base +
-+			mmACP_EXTERNAL_INTR_STAT);
-+		snd_pcm_period_elapsed(rv_i2s_data->play_stream);
-+		play_flag = 1;
-+	}
-+
-+	if ((val & BIT(BT_RX_THRESHOLD)) && rv_i2s_data->capture_stream) {
-+		rv_writel(BIT(BT_RX_THRESHOLD), rv_i2s_data->acp3x_base +
-+			mmACP_EXTERNAL_INTR_STAT);
-+		snd_pcm_period_elapsed(rv_i2s_data->capture_stream);
-+		cap_flag = 1;
-+	}
-+
-+	if (play_flag | cap_flag)
-+		return IRQ_HANDLED;
-+	else
-+		return IRQ_NONE;
-+}
-+
-+static void config_acp3x_dma(struct i2s_stream_instance *rtd, int direction)
-+{
-+	u16 page_idx;
-+	u64 addr;
-+	u32 low, high, val, acp_fifo_addr;
-+	struct page *pg = rtd->pg;
-+
-+	/* 8 scratch registers used to map one 64 bit address.
-+	 * For 2 pages (8192 * 2 bytes), it will be 16 registers.
-+	 */
-+	if (direction == SNDRV_PCM_STREAM_PLAYBACK)
-+		val = 0;
-+	else
-+		val = 32;
-+
-+	/* Group Enable */
-+	rv_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp3x_base +
-+					mmACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
-+	rv_writel(PAGE_SIZE_4K_ENABLE, rtd->acp3x_base +
-+			mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
-+
-+	for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
-+		/* Load the low address of page int ACP SRAM through SRBM */
-+		addr = page_to_phys(pg);
-+		low = lower_32_bits(addr);
-+		high = upper_32_bits(addr);
-+
-+		rv_writel(low, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val);
-+		high |= BIT(31);
-+		rv_writel(high, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val
-+				+ 4);
-+		/* Move to next physically contiguos page */
-+		val += 8;
-+		pg++;
-+	}
-+
-+	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
-+		/* Config ringbuffer */
-+		rv_writel(MEM_WINDOW_START, rtd->acp3x_base +
-+				mmACP_BT_TX_RINGBUFADDR);
-+		rv_writel(MAX_BUFFER, rtd->acp3x_base +
-+				mmACP_BT_TX_RINGBUFSIZE);
-+		rv_writel(0x40, rtd->acp3x_base + mmACP_BT_TX_DMA_SIZE);
-+
-+		/* Config audio fifo */
-+		acp_fifo_addr = ACP_SRAM_PTE_OFFSET + (rtd->num_pages * 8)
-+				+ 1024;
-+		rv_writel(acp_fifo_addr, rtd->acp3x_base +
-+				mmACP_BT_TX_FIFOADDR);
-+		rv_writel(256, rtd->acp3x_base + mmACP_BT_TX_FIFOSIZE);
-+		rv_writel(PLAYBACK_MIN_PERIOD_SIZE, rtd->acp3x_base +
-+				mmACP_BT_TX_INTR_WATERMARK_SIZE);
-+	} else {
-+		/* Config ringbuffer */
-+		rv_writel(MEM_WINDOW_START + MAX_BUFFER, rtd->acp3x_base +
-+				mmACP_BT_RX_RINGBUFADDR);
-+		rv_writel(MAX_BUFFER, rtd->acp3x_base +
-+				mmACP_BT_RX_RINGBUFSIZE);
-+		rv_writel(0x40, rtd->acp3x_base + mmACP_BT_RX_DMA_SIZE);
-+
-+		/* Config audio fifo */
-+		acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
-+				(rtd->num_pages * 8) + 1024 + 256;
-+		rv_writel(acp_fifo_addr, rtd->acp3x_base +
-+				mmACP_BT_RX_FIFOADDR);
-+		rv_writel(256, rtd->acp3x_base + mmACP_BT_RX_FIFOSIZE);
-+		rv_writel(CAPTURE_MIN_PERIOD_SIZE, rtd->acp3x_base +
-+				mmACP_BT_RX_INTR_WATERMARK_SIZE);
-+	}
-+
-+	/* Enable  watermark/period interrupt to host */
-+	rv_writel(BIT(BT_TX_THRESHOLD) | BIT(BT_RX_THRESHOLD),
-+			rtd->acp3x_base + mmACP_EXTERNAL_INTR_CNTL);
-+}
-+
-+static int acp3x_dma_open(struct snd_pcm_substream *substream)
-+{
-+	int ret = 0;
-+
-+	struct snd_pcm_runtime *runtime = substream->runtime;
-+	struct snd_soc_pcm_runtime *prtd = substream->private_data;
-+	struct i2s_dev_data *adata = dev_get_drvdata(prtd->platform->dev);
-+
-+	struct i2s_stream_instance *i2s_data = kzalloc(sizeof(
-+				struct i2s_stream_instance), GFP_KERNEL);
-+	if (i2s_data == NULL)
-+		return -EINVAL;
-+
-+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-+		runtime->hw = acp3x_pcm_hardware_playback;
-+	else
-+		runtime->hw = acp3x_pcm_hardware_capture;
-+
-+	ret = snd_pcm_hw_constraint_integer(runtime,
-+					    SNDRV_PCM_HW_PARAM_PERIODS);
-+	if (ret < 0) {
-+		dev_err(prtd->platform->dev, "set integer constraint failed\n");
-+		return ret;
-+	}
-+
-+	if (!adata->play_stream && !adata->capture_stream)
-+		rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
-+
-+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-+		adata->play_stream = substream;
-+	else
-+		adata->capture_stream = substream;
-+
-+	i2s_data->acp3x_base = adata->acp3x_base;
-+	runtime->private_data = i2s_data;
-+	return 0;
-+}
-+
-+static int acp3x_dma_hw_params(struct snd_pcm_substream *substream,
-+			     struct snd_pcm_hw_params *params)
-+{
-+	int status;
-+	uint64_t size;
-+	struct snd_dma_buffer *dma_buffer;
-+	struct page *pg;
-+	struct i2s_stream_instance *rtd = substream->runtime->private_data;
-+
-+	if (rtd == NULL)
-+		return -EINVAL;
-+
-+	dma_buffer = &substream->dma_buffer;
-+	size = params_buffer_bytes(params);
-+	status = snd_pcm_lib_malloc_pages(substream, size);
-+	if (status < 0)
-+		return status;
-+
-+	memset(substream->runtime->dma_area, 0, params_buffer_bytes(params));
-+	pg = virt_to_page(substream->dma_buffer.area);
-+	if (pg != NULL) {
-+		rtd->pg = pg;
-+		rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
-+		config_acp3x_dma(rtd, substream->stream);
-+		status = 0;
-+	} else {
-+		status = -ENOMEM;
-+	}
-+	return status;
-+}
-+
-+static snd_pcm_uframes_t acp3x_dma_pointer(struct snd_pcm_substream *substream)
-+{
-+	u32 pos = 0;
-+	struct i2s_stream_instance *rtd = substream->runtime->private_data;
-+
-+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-+		pos = rv_readl(rtd->acp3x_base +
-+				mmACP_BT_TX_LINKPOSITIONCNTR);
-+	else
-+		pos = rv_readl(rtd->acp3x_base +
-+				mmACP_BT_RX_LINKPOSITIONCNTR);
-+
-+	if (pos >= MAX_BUFFER)
-+		pos = 0;
-+
-+	return bytes_to_frames(substream->runtime, pos);
-+}
-+
-+static int acp3x_dma_new(struct snd_soc_pcm_runtime *rtd)
-+{
-+	return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
-+							SNDRV_DMA_TYPE_DEV,
-+							NULL, MIN_BUFFER,
-+							MAX_BUFFER);
-+}
-+
-+static int acp3x_dma_hw_free(struct snd_pcm_substream *substream)
-+{
-+	return snd_pcm_lib_free_pages(substream);
-+}
-+
-+static int acp3x_dma_mmap(struct snd_pcm_substream *substream,
-+			struct vm_area_struct *vma)
-+{
-+	return snd_pcm_lib_default_mmap(substream, vma);
-+}
-+
-+static int acp3x_dma_close(struct snd_pcm_substream *substream)
-+{
-+	struct snd_soc_pcm_runtime *prtd = substream->private_data;
-+	struct i2s_dev_data *adata = dev_get_drvdata(prtd->platform->dev);
-+	struct i2s_stream_instance *rtd = substream->runtime->private_data;
-+
-+	kfree(rtd);
-+
-+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-+		adata->play_stream = NULL;
-+	else
-+		adata->capture_stream = NULL;
-+
-+	/* Disable ACP irq, when the current stream is being closed and
-+	 * another stream is also not active.
-+	 */
-+	if (!adata->play_stream && !adata->capture_stream)
-+		rv_writel(0, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
-+
-+	return 0;
-+}
-+
-+static struct snd_pcm_ops acp3x_dma_ops = {
-+	.open = acp3x_dma_open,
-+	.close = acp3x_dma_close,
-+	.ioctl = snd_pcm_lib_ioctl,
-+	.hw_params = acp3x_dma_hw_params,
-+	.hw_free = acp3x_dma_hw_free,
-+	.pointer = acp3x_dma_pointer,
-+	.mmap = acp3x_dma_mmap,
-+};
-+
-+static struct snd_soc_platform_driver acp3x_asoc_platform = {
-+	.ops = &acp3x_dma_ops,
-+	.pcm_new = acp3x_dma_new,
-+};
-+
-+static int acp3x_dai_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
-+{
-+
-+	struct i2s_dev_data *adata = snd_soc_dai_get_drvdata(cpu_dai);
-+
-+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
-+	case SND_SOC_DAIFMT_I2S:
-+		adata->tdm_mode = false;
-+	break;
-+	case SND_SOC_DAIFMT_DSP_A:
-+		adata->tdm_mode = true;
-+	break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int acp3x_dai_set_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
-+				u32 rx_mask, int slots, int slot_width)
-+{
-+	u32 val = 0;
-+	u16 slot_len;
-+
-+	struct i2s_dev_data *adata = snd_soc_dai_get_drvdata(cpu_dai);
-+
-+	switch (slot_width) {
-+	case 8:
-+		slot_len = 8;
-+	break;
-+	case 16:
-+		slot_len = 16;
-+	break;
-+	case 24:
-+		slot_len = 24;
-+	break;
-+	case 32:
-+		slot_len = 0;
-+	break;
-+	default:
-+		return -EINVAL;
-+	break;
-+	}
-+
-+	val = rv_readl(adata->acp3x_base + mmACP_BTTDM_ITER);
-+	rv_writel((val | 0x2), adata->acp3x_base + mmACP_BTTDM_ITER);
-+	val = rv_readl(adata->acp3x_base + mmACP_BTTDM_IRER);
-+	rv_writel((val | 0x2), adata->acp3x_base + mmACP_BTTDM_IRER);
-+
-+	val = (FRM_LEN | ((slots) << 15) | (slot_len << 18));
-+	rv_writel(val, adata->acp3x_base + mmACP_BTTDM_TXFRMT);
-+	rv_writel(val, adata->acp3x_base + mmACP_BTTDM_RXFRMT);
-+
-+	adata->tdm_fmt = val;
-+	return 0;
-+}
-+
-+static int acp3x_dai_i2s_hwparams(struct snd_pcm_substream *substream,
-+				struct snd_pcm_hw_params *params,
-+				struct snd_soc_dai *dai)
-+{
-+	u32 val = 0;
-+	struct i2s_stream_instance *rtd = substream->runtime->private_data;
-+
-+	switch (params_format(params)) {
-+	case SNDRV_PCM_FORMAT_U8:
-+	case SNDRV_PCM_FORMAT_S8:
-+		rtd->xfer_resolution = 0x0;
-+	break;
-+	case SNDRV_PCM_FORMAT_S16_LE:
-+		rtd->xfer_resolution = 0x02;
-+	break;
-+
-+	case SNDRV_PCM_FORMAT_S24_LE:
-+		rtd->xfer_resolution = 0x04;
-+	break;
-+	case SNDRV_PCM_FORMAT_S32_LE:
-+		rtd->xfer_resolution = 0x05;
-+	break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER);
-+	val = val | (rtd->xfer_resolution  << 3);
-+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-+		rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_ITER);
-+	else
-+		rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_IRER);
-+
-+	return 0;
-+}
-+
-+static int acp3x_dai_i2s_trigger(struct snd_pcm_substream *substream,
-+				int cmd, struct snd_soc_dai *dai)
-+{
-+	int ret = 0;
-+	struct i2s_stream_instance *rtd = substream->runtime->private_data;
-+	u32 val;
-+
-+	switch (cmd) {
-+	case SNDRV_PCM_TRIGGER_START:
-+	case SNDRV_PCM_TRIGGER_RESUME:
-+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-+			val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER);
-+			val = val | BIT(0);
-+			rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_ITER);
-+		} else {
-+			val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_IRER);
-+			val = val | BIT(0);
-+			rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_IRER);
-+		}
-+		rv_writel(1, rtd->acp3x_base + mmACP_BTTDM_IER);
-+	break;
-+
-+	case SNDRV_PCM_TRIGGER_STOP:
-+	case SNDRV_PCM_TRIGGER_SUSPEND:
-+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-+			val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER);
-+			val = val & ~BIT(0);
-+			rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_ITER);
-+		} else {
-+			val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_IRER);
-+			val = val & ~BIT(0);
-+			rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_IRER);
-+		}
-+		rv_writel(0, rtd->acp3x_base + mmACP_BTTDM_IER);
-+	break;
-+	default:
-+		ret = -EINVAL;
-+	break;
-+	}
-+
-+	return ret;
-+}
-+
-+struct snd_soc_dai_ops acp3x_dai_i2s_ops = {
-+	.hw_params = acp3x_dai_i2s_hwparams,
-+	.trigger   = acp3x_dai_i2s_trigger,
-+	.set_fmt = acp3x_dai_i2s_set_fmt,
-+	.set_tdm_slot = acp3x_dai_set_tdm_slot,
-+};
-+
-+static struct snd_soc_dai_driver acp3x_i2s_dai_driver = {
-+	.playback = {
-+		.rates = SNDRV_PCM_RATE_8000_96000,
-+		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
-+					SNDRV_PCM_FMTBIT_U8 |
-+					SNDRV_PCM_FMTBIT_S24_LE |
-+					SNDRV_PCM_FMTBIT_S32_LE,
-+		.channels_min = 2,
-+		.channels_max = 8,
-+
-+		.rate_min = 8000,
-+		.rate_max = 96000,
-+	},
-+	.capture = {
-+		.rates = SNDRV_PCM_RATE_8000_48000,
-+		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
-+					SNDRV_PCM_FMTBIT_U8 |
-+					SNDRV_PCM_FMTBIT_S24_LE |
-+					SNDRV_PCM_FMTBIT_S32_LE,
-+		.channels_min = 2,
-+		.channels_max = 2,
-+		.rate_min = 8000,
-+		.rate_max = 48000,
-+	},
-+	.ops = &acp3x_dai_i2s_ops,
-+};
-+
-+static const struct snd_soc_component_driver acp3x_i2s_component = {
-+	.name           = "acp3x_i2s",
-+};
-+
-+static int acp3x_audio_probe(struct platform_device *pdev)
-+{
-+	int status;
-+	struct resource *res;
-+	struct i2s_dev_data *adata;
-+	unsigned int irqflags;
-+
-+	if (pdev->dev.platform_data == NULL) {
-+		dev_err(&pdev->dev, "platform_data not retrieved\n");
-+		return -ENODEV;
-+	}
-+	irqflags = *((unsigned int *)(pdev->dev.platform_data));
-+
-+	adata = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dev_data),
-+				GFP_KERNEL);
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!res) {
-+		dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
-+			return -ENODEV;
-+	}
-+
-+	adata->acp3x_base = devm_ioremap(&pdev->dev, res->start,
-+			resource_size(res));
-+
-+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-+	if (!res) {
-+		dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
-+		return -ENODEV;
-+	}
-+
-+	adata->i2s_irq = res->start;
-+	adata->play_stream = NULL;
-+	adata->capture_stream = NULL;
-+
-+	dev_set_drvdata(&pdev->dev, adata);
-+	/* Initialize ACP */
-+	status = acp3x_init(adata->acp3x_base);
-+	if (status)
-+		return -ENODEV;
-+
-+	status = snd_soc_register_platform(&pdev->dev, &acp3x_asoc_platform);
-+	if (status != 0) {
-+		dev_err(&pdev->dev, "Fail to register ALSA platform device\n");
-+		goto dev_err;
-+	}
-+
-+	status = devm_snd_soc_register_component(&pdev->dev,
-+			&acp3x_i2s_component, &acp3x_i2s_dai_driver, 1);
-+	if (status != 0) {
-+		dev_err(&pdev->dev, "Fail to register acp i2s dai\n");
-+		snd_soc_unregister_platform(&pdev->dev);
-+		goto dev_err;
-+	}
-+
-+	status = devm_request_irq(&pdev->dev, adata->i2s_irq, i2s_irq_handler,
-+					irqflags, "ACP3x_I2S_IRQ", adata);
-+	if (status) {
-+		dev_err(&pdev->dev, "ACP3x I2S IRQ request failed\n");
-+		snd_soc_unregister_platform(&pdev->dev);
-+		snd_soc_unregister_component(&pdev->dev);
-+		goto dev_err;
-+	}
-+
-+	pm_runtime_set_autosuspend_delay(&pdev->dev, 10000);
-+	pm_runtime_use_autosuspend(&pdev->dev);
-+	pm_runtime_enable(&pdev->dev);
-+	return 0;
-+dev_err:
-+	status = acp3x_deinit(adata->acp3x_base);
-+	if (status)
-+		dev_err(&pdev->dev, "ACP de-init failed\n");
-+	else
-+		dev_info(&pdev->dev, "ACP de-initialized\n");
-+	/*ignore device status and return driver probe error*/
-+	return -ENODEV;
-+}
-+
-+static int acp3x_audio_remove(struct platform_device *pdev)
-+{
-+	int ret;
-+	struct i2s_dev_data *adata = dev_get_drvdata(&pdev->dev);
-+
-+	snd_soc_unregister_component(&pdev->dev);
-+	snd_soc_unregister_platform(&pdev->dev);
-+
-+	ret = acp3x_deinit(adata->acp3x_base);
-+	if (ret)
-+		dev_err(&pdev->dev, "ACP de-init failed\n");
-+	else
-+		dev_info(&pdev->dev, "ACP de-initialized\n");
-+
-+	pm_runtime_disable(&pdev->dev);
-+	return 0;
-+}
-+
-+static int acp3x_resume(struct device *dev)
-+{
-+	int status;
-+	u32 val;
-+	struct i2s_dev_data *adata = dev_get_drvdata(dev);
-+
-+	status = acp3x_init(adata->acp3x_base);
-+	if (status)
-+		return -ENODEV;
-+
-+	if (adata->play_stream && adata->play_stream->runtime) {
-+		struct i2s_stream_instance *rtd =
-+			adata->play_stream->runtime->private_data;
-+		config_acp3x_dma(rtd, SNDRV_PCM_STREAM_PLAYBACK);
-+		rv_writel((rtd->xfer_resolution  << 3),
-+			rtd->acp3x_base + mmACP_BTTDM_ITER);
-+		if (adata->tdm_mode == true) {
-+			rv_writel(adata->tdm_fmt, adata->acp3x_base +
-+					mmACP_BTTDM_TXFRMT);
-+			val = rv_readl(adata->acp3x_base + mmACP_BTTDM_ITER);
-+			rv_writel((val | 0x2), adata->acp3x_base +
-+					mmACP_BTTDM_ITER);
-+		}
-+	}
-+
-+	if (adata->capture_stream && adata->capture_stream->runtime) {
-+		struct i2s_stream_instance *rtd =
-+			adata->capture_stream->runtime->private_data;
-+		config_acp3x_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
-+		rv_writel((rtd->xfer_resolution  << 3),
-+			rtd->acp3x_base + mmACP_BTTDM_IRER);
-+		if (adata->tdm_mode == true) {
-+			rv_writel(adata->tdm_fmt, adata->acp3x_base +
-+					mmACP_BTTDM_RXFRMT);
-+			val = rv_readl(adata->acp3x_base + mmACP_BTTDM_IRER);
-+			rv_writel((val | 0x2), adata->acp3x_base +
-+					mmACP_BTTDM_IRER);
-+		}
-+	}
-+
-+	rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
-+	return 0;
-+}
-+
-+
-+static int acp3x_pcm_runtime_suspend(struct device *dev)
-+{
-+	int status;
-+	struct i2s_dev_data *adata = dev_get_drvdata(dev);
-+
-+	status = acp3x_deinit(adata->acp3x_base);
-+	if (status)
-+		dev_err(dev, "ACP de-init failed\n");
-+	else
-+		dev_info(dev, "ACP de-initialized\n");
-+
-+	rv_writel(0, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
-+
-+	return 0;
-+}
-+
-+static int acp3x_pcm_runtime_resume(struct device *dev)
-+{
-+	int status;
-+	struct i2s_dev_data *adata = dev_get_drvdata(dev);
-+
-+	status = acp3x_init(adata->acp3x_base);
-+	if (status)
-+		return -ENODEV;
-+	rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
-+	return 0;
-+}
-+
-+static const struct dev_pm_ops acp3x_pm_ops = {
-+	.runtime_suspend = acp3x_pcm_runtime_suspend,
-+	.runtime_resume = acp3x_pcm_runtime_resume,
-+	.resume = acp3x_resume,
-+};
-+
-+static struct platform_driver acp3x_dma_driver = {
-+	.probe = acp3x_audio_probe,
-+	.remove = acp3x_audio_remove,
-+	.driver = {
-+		.name = "acp3x_rv_i2s",
-+		.pm = &acp3x_pm_ops,
-+	},
-+};
-+
-+module_platform_driver(acp3x_dma_driver);
-+
-+MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
-+MODULE_DESCRIPTION("AMD ACP 3.x PCM Driver");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:acp3x-i2s-audio");
---- linux-4.14/sound/soc/amd/raven/chip_offset_byte.h.0130~	2017-12-14 06:39:58.534903650 +0100
-+++ linux-4.14/sound/soc/amd/raven/chip_offset_byte.h	2017-12-14 06:39:58.534903650 +0100
-@@ -0,0 +1,655 @@
-+/*
-+ * ACP 3.0 Register documentation
-+ *
-+ * Copyright (C) 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included
-+ * in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
-+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
-+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#ifndef _acp_ip_OFFSET_HEADER
-+#define _acp_ip_OFFSET_HEADER
-+// Registers from ACP_DMA block
-+
-+#define mmACP_DMA_CNTL_0                                0x1240000
-+#define mmACP_DMA_CNTL_1                                0x1240004
-+#define mmACP_DMA_CNTL_2                                0x1240008
-+#define mmACP_DMA_CNTL_3                                0x124000C
-+#define mmACP_DMA_CNTL_4                                0x1240010
-+#define mmACP_DMA_CNTL_5                                0x1240014
-+#define mmACP_DMA_CNTL_6                                0x1240018
-+#define mmACP_DMA_CNTL_7                                0x124001C
-+#define mmACP_DMA_DSCR_STRT_IDX_0                       0x1240020
-+#define mmACP_DMA_DSCR_STRT_IDX_1                       0x1240024
-+#define mmACP_DMA_DSCR_STRT_IDX_2                       0x1240028
-+#define mmACP_DMA_DSCR_STRT_IDX_3                       0x124002C
-+#define mmACP_DMA_DSCR_STRT_IDX_4                       0x1240030
-+#define mmACP_DMA_DSCR_STRT_IDX_5                       0x1240034
-+#define mmACP_DMA_DSCR_STRT_IDX_6                       0x1240038
-+#define mmACP_DMA_DSCR_STRT_IDX_7                       0x124003C
-+#define mmACP_DMA_DSCR_CNT_0                            0x1240040
-+#define mmACP_DMA_DSCR_CNT_1                            0x1240044
-+#define mmACP_DMA_DSCR_CNT_2                            0x1240048
-+#define mmACP_DMA_DSCR_CNT_3                            0x124004C
-+#define mmACP_DMA_DSCR_CNT_4                            0x1240050
-+#define mmACP_DMA_DSCR_CNT_5                            0x1240054
-+#define mmACP_DMA_DSCR_CNT_6                            0x1240058
-+#define mmACP_DMA_DSCR_CNT_7                            0x124005C
-+#define mmACP_DMA_PRIO_0                                0x1240060
-+#define mmACP_DMA_PRIO_1                                0x1240064
-+#define mmACP_DMA_PRIO_2                                0x1240068
-+#define mmACP_DMA_PRIO_3                                0x124006C
-+#define mmACP_DMA_PRIO_4                                0x1240070
-+#define mmACP_DMA_PRIO_5                                0x1240074
-+#define mmACP_DMA_PRIO_6                                0x1240078
-+#define mmACP_DMA_PRIO_7                                0x124007C
-+#define mmACP_DMA_CUR_DSCR_0                            0x1240080
-+#define mmACP_DMA_CUR_DSCR_1                            0x1240084
-+#define mmACP_DMA_CUR_DSCR_2                            0x1240088
-+#define mmACP_DMA_CUR_DSCR_3                            0x124008C
-+#define mmACP_DMA_CUR_DSCR_4                            0x1240090
-+#define mmACP_DMA_CUR_DSCR_5                            0x1240094
-+#define mmACP_DMA_CUR_DSCR_6                            0x1240098
-+#define mmACP_DMA_CUR_DSCR_7                            0x124009C
-+#define mmACP_DMA_CUR_TRANS_CNT_0                       0x12400A0
-+#define mmACP_DMA_CUR_TRANS_CNT_1                       0x12400A4
-+#define mmACP_DMA_CUR_TRANS_CNT_2                       0x12400A8
-+#define mmACP_DMA_CUR_TRANS_CNT_3                       0x12400AC
-+#define mmACP_DMA_CUR_TRANS_CNT_4                       0x12400B0
-+#define mmACP_DMA_CUR_TRANS_CNT_5                       0x12400B4
-+#define mmACP_DMA_CUR_TRANS_CNT_6                       0x12400B8
-+#define mmACP_DMA_CUR_TRANS_CNT_7                       0x12400BC
-+#define mmACP_DMA_ERR_STS_0                             0x12400C0
-+#define mmACP_DMA_ERR_STS_1                             0x12400C4
-+#define mmACP_DMA_ERR_STS_2                             0x12400C8
-+#define mmACP_DMA_ERR_STS_3                             0x12400CC
-+#define mmACP_DMA_ERR_STS_4                             0x12400D0
-+#define mmACP_DMA_ERR_STS_5                             0x12400D4
-+#define mmACP_DMA_ERR_STS_6                             0x12400D8
-+#define mmACP_DMA_ERR_STS_7                             0x12400DC
-+#define mmACP_DMA_DESC_BASE_ADDR                        0x12400E0
-+#define mmACP_DMA_DESC_MAX_NUM_DSCR                     0x12400E4
-+#define mmACP_DMA_CH_STS                                0x12400E8
-+#define mmACP_DMA_CH_GROUP                              0x12400EC
-+#define mmACP_DMA_CH_RST_STS                            0x12400F0
-+
-+
-+// Registers from ACP_AXI2AXIATU block
-+
-+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_1                0x1240C00
-+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_1                0x1240C04
-+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_2                0x1240C08
-+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_2                0x1240C0C
-+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_3                0x1240C10
-+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_3                0x1240C14
-+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_4                0x1240C18
-+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_4                0x1240C1C
-+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_5                0x1240C20
-+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_5                0x1240C24
-+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_6                0x1240C28
-+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_6                0x1240C2C
-+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_7                0x1240C30
-+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_7                0x1240C34
-+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_8                0x1240C38
-+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_8                0x1240C3C
-+#define mmACPAXI2AXI_ATU_CTRL                           0x1240C40
-+
-+
-+// Registers from ACP_CLKRST block
-+
-+#define mmACP_SOFT_RESET                                0x1241000
-+#define mmACP_CONTROL                                   0x1241004
-+#define mmACP_STATUS                                    0x1241008
-+#define mmACP_DSP0_OCD_HALT_ON_RST                      0x124100C
-+#define mmACP_DYNAMIC_CG_MASTER_CONTROL                 0x1241010
-+
-+
-+// Registers from ACP_MISC block
-+
-+#define mmACP_EXTERNAL_INTR_ENB                         0x1241800
-+#define mmACP_EXTERNAL_INTR_CNTL                        0x1241804
-+#define mmACP_EXTERNAL_INTR_STAT                        0x1241808
-+#define mmACP_DSP0_INTR_CNTL                            0x124180C
-+#define mmACP_DSP0_INTR_STAT                            0x1241810
-+#define mmACP_DSP_SW_INTR_CNTL                          0x1241814
-+#define mmACP_DSP_SW_INTR_STAT                          0x1241818
-+#define mmACP_SW_INTR_TRIG                              0x124181C
-+#define mmACP_SMU_MAILBOX                               0x1241820
-+#define mmDSP_INTERRUPT_ROUTING_CTRL                    0x1241824
-+#define mmACP_DSP0_WATCHDOG_TIMER_CNTL                  0x1241828
-+#define mmACP_DSP0_EXT_TIMER1_CNTL                      0x124182C
-+#define mmACP_DSP0_EXT_TIMER2_CNTL                      0x1241830
-+#define mmACP_DSP0_EXT_TIMER3_CNTL                      0x1241834
-+#define mmACP_DSP0_EXT_TIMER4_CNTL                      0x1241838
-+#define mmACP_DSP0_EXT_TIMER5_CNTL                      0x124183C
-+#define mmACP_DSP0_EXT_TIMER6_CNTL                      0x1241840
-+#define mmACP_DSP0_EXT_TIMER1_CURR_VALUE                0x1241844
-+#define mmACP_DSP0_EXT_TIMER2_CURR_VALUE                0x1241848
-+#define mmACP_DSP0_EXT_TIMER3_CURR_VALUE                0x124184C
-+#define mmACP_DSP0_EXT_TIMER4_CURR_VALUE                0x1241850
-+#define mmACP_DSP0_EXT_TIMER5_CURR_VALUE                0x1241854
-+#define mmACP_DSP0_EXT_TIMER6_CURR_VALUE                0x1241858
-+#define mmACP_FW_STATUS                                 0x124185C
-+#define mmACP_TIMER                                     0x1241874
-+#define mmACP_TIMER_CNTL                                0x1241878
-+#define mmACP_PGMEM_CTRL                                0x12418C0
-+#define mmACP_ERROR_STATUS                              0x12418C4
-+#define mmACP_SW_I2S_ERROR_REASON                       0x12418C8
-+#define mmACP_MEM_PG_STS                                0x12418CC
-+
-+
-+// Registers from ACP_PGFSM block
-+
-+#define mmACP_I2S_PIN_CONFIG                            0x1241400
-+#define mmACP_PAD_PULLUP_PULLDOWN_CTRL                  0x1241404
-+#define mmACP_PAD_DRIVE_STRENGTH_CTRL                   0x1241408
-+#define mmACP_SW_PAD_KEEPER_EN                          0x124140C
-+#define mmACP_SW_WAKE_EN                                0x1241410
-+#define mmACP_I2S_WAKE_EN                               0x1241414
-+#define mmACP_PME_EN                                    0x1241418
-+#define mmACP_PGFSM_CONTROL                             0x124141C
-+#define mmACP_PGFSM_STATUS                              0x1241420
-+
-+
-+// Registers from ACP_SCRATCH block
-+
-+#define mmACP_SCRATCH_REG_0                             0x1250000
-+#define mmACP_SCRATCH_REG_1                             0x1250004
-+#define mmACP_SCRATCH_REG_2                             0x1250008
-+#define mmACP_SCRATCH_REG_3                             0x125000C
-+#define mmACP_SCRATCH_REG_4                             0x1250010
-+#define mmACP_SCRATCH_REG_5                             0x1250014
-+#define mmACP_SCRATCH_REG_6                             0x1250018
-+#define mmACP_SCRATCH_REG_7                             0x125001C
-+#define mmACP_SCRATCH_REG_8                             0x1250020
-+#define mmACP_SCRATCH_REG_9                             0x1250024
-+#define mmACP_SCRATCH_REG_10                            0x1250028
-+#define mmACP_SCRATCH_REG_11                            0x125002C
-+#define mmACP_SCRATCH_REG_12                            0x1250030
-+#define mmACP_SCRATCH_REG_13                            0x1250034
-+#define mmACP_SCRATCH_REG_14                            0x1250038
-+#define mmACP_SCRATCH_REG_15                            0x125003C
-+#define mmACP_SCRATCH_REG_16                            0x1250040
-+#define mmACP_SCRATCH_REG_17                            0x1250044
-+#define mmACP_SCRATCH_REG_18                            0x1250048
-+#define mmACP_SCRATCH_REG_19                            0x125004C
-+#define mmACP_SCRATCH_REG_20                            0x1250050
-+#define mmACP_SCRATCH_REG_21                            0x1250054
-+#define mmACP_SCRATCH_REG_22                            0x1250058
-+#define mmACP_SCRATCH_REG_23                            0x125005C
-+#define mmACP_SCRATCH_REG_24                            0x1250060
-+#define mmACP_SCRATCH_REG_25                            0x1250064
-+#define mmACP_SCRATCH_REG_26                            0x1250068
-+#define mmACP_SCRATCH_REG_27                            0x125006C
-+#define mmACP_SCRATCH_REG_28                            0x1250070
-+#define mmACP_SCRATCH_REG_29                            0x1250074
-+#define mmACP_SCRATCH_REG_30                            0x1250078
-+#define mmACP_SCRATCH_REG_31                            0x125007C
-+#define mmACP_SCRATCH_REG_32                            0x1250080
-+#define mmACP_SCRATCH_REG_33                            0x1250084
-+#define mmACP_SCRATCH_REG_34                            0x1250088
-+#define mmACP_SCRATCH_REG_35                            0x125008C
-+#define mmACP_SCRATCH_REG_36                            0x1250090
-+#define mmACP_SCRATCH_REG_37                            0x1250094
-+#define mmACP_SCRATCH_REG_38                            0x1250098
-+#define mmACP_SCRATCH_REG_39                            0x125009C
-+#define mmACP_SCRATCH_REG_40                            0x12500A0
-+#define mmACP_SCRATCH_REG_41                            0x12500A4
-+#define mmACP_SCRATCH_REG_42                            0x12500A8
-+#define mmACP_SCRATCH_REG_43                            0x12500AC
-+#define mmACP_SCRATCH_REG_44                            0x12500B0
-+#define mmACP_SCRATCH_REG_45                            0x12500B4
-+#define mmACP_SCRATCH_REG_46                            0x12500B8
-+#define mmACP_SCRATCH_REG_47                            0x12500BC
-+#define mmACP_SCRATCH_REG_48                            0x12500C0
-+#define mmACP_SCRATCH_REG_49                            0x12500C4
-+#define mmACP_SCRATCH_REG_50                            0x12500C8
-+#define mmACP_SCRATCH_REG_51                            0x12500CC
-+#define mmACP_SCRATCH_REG_52                            0x12500D0
-+#define mmACP_SCRATCH_REG_53                            0x12500D4
-+#define mmACP_SCRATCH_REG_54                            0x12500D8
-+#define mmACP_SCRATCH_REG_55                            0x12500DC
-+#define mmACP_SCRATCH_REG_56                            0x12500E0
-+#define mmACP_SCRATCH_REG_57                            0x12500E4
-+#define mmACP_SCRATCH_REG_58                            0x12500E8
-+#define mmACP_SCRATCH_REG_59                            0x12500EC
-+#define mmACP_SCRATCH_REG_60                            0x12500F0
-+#define mmACP_SCRATCH_REG_61                            0x12500F4
-+#define mmACP_SCRATCH_REG_62                            0x12500F8
-+#define mmACP_SCRATCH_REG_63                            0x12500FC
-+#define mmACP_SCRATCH_REG_64                            0x1250100
-+#define mmACP_SCRATCH_REG_65                            0x1250104
-+#define mmACP_SCRATCH_REG_66                            0x1250108
-+#define mmACP_SCRATCH_REG_67                            0x125010C
-+#define mmACP_SCRATCH_REG_68                            0x1250110
-+#define mmACP_SCRATCH_REG_69                            0x1250114
-+#define mmACP_SCRATCH_REG_70                            0x1250118
-+#define mmACP_SCRATCH_REG_71                            0x125011C
-+#define mmACP_SCRATCH_REG_72                            0x1250120
-+#define mmACP_SCRATCH_REG_73                            0x1250124
-+#define mmACP_SCRATCH_REG_74                            0x1250128
-+#define mmACP_SCRATCH_REG_75                            0x125012C
-+#define mmACP_SCRATCH_REG_76                            0x1250130
-+#define mmACP_SCRATCH_REG_77                            0x1250134
-+#define mmACP_SCRATCH_REG_78                            0x1250138
-+#define mmACP_SCRATCH_REG_79                            0x125013C
-+#define mmACP_SCRATCH_REG_80                            0x1250140
-+#define mmACP_SCRATCH_REG_81                            0x1250144
-+#define mmACP_SCRATCH_REG_82                            0x1250148
-+#define mmACP_SCRATCH_REG_83                            0x125014C
-+#define mmACP_SCRATCH_REG_84                            0x1250150
-+#define mmACP_SCRATCH_REG_85                            0x1250154
-+#define mmACP_SCRATCH_REG_86                            0x1250158
-+#define mmACP_SCRATCH_REG_87                            0x125015C
-+#define mmACP_SCRATCH_REG_88                            0x1250160
-+#define mmACP_SCRATCH_REG_89                            0x1250164
-+#define mmACP_SCRATCH_REG_90                            0x1250168
-+#define mmACP_SCRATCH_REG_91                            0x125016C
-+#define mmACP_SCRATCH_REG_92                            0x1250170
-+#define mmACP_SCRATCH_REG_93                            0x1250174
-+#define mmACP_SCRATCH_REG_94                            0x1250178
-+#define mmACP_SCRATCH_REG_95                            0x125017C
-+#define mmACP_SCRATCH_REG_96                            0x1250180
-+#define mmACP_SCRATCH_REG_97                            0x1250184
-+#define mmACP_SCRATCH_REG_98                            0x1250188
-+#define mmACP_SCRATCH_REG_99                            0x125018C
-+#define mmACP_SCRATCH_REG_100                           0x1250190
-+#define mmACP_SCRATCH_REG_101                           0x1250194
-+#define mmACP_SCRATCH_REG_102                           0x1250198
-+#define mmACP_SCRATCH_REG_103                           0x125019C
-+#define mmACP_SCRATCH_REG_104                           0x12501A0
-+#define mmACP_SCRATCH_REG_105                           0x12501A4
-+#define mmACP_SCRATCH_REG_106                           0x12501A8
-+#define mmACP_SCRATCH_REG_107                           0x12501AC
-+#define mmACP_SCRATCH_REG_108                           0x12501B0
-+#define mmACP_SCRATCH_REG_109                           0x12501B4
-+#define mmACP_SCRATCH_REG_110                           0x12501B8
-+#define mmACP_SCRATCH_REG_111                           0x12501BC
-+#define mmACP_SCRATCH_REG_112                           0x12501C0
-+#define mmACP_SCRATCH_REG_113                           0x12501C4
-+#define mmACP_SCRATCH_REG_114                           0x12501C8
-+#define mmACP_SCRATCH_REG_115                           0x12501CC
-+#define mmACP_SCRATCH_REG_116                           0x12501D0
-+#define mmACP_SCRATCH_REG_117                           0x12501D4
-+#define mmACP_SCRATCH_REG_118                           0x12501D8
-+#define mmACP_SCRATCH_REG_119                           0x12501DC
-+#define mmACP_SCRATCH_REG_120                           0x12501E0
-+#define mmACP_SCRATCH_REG_121                           0x12501E4
-+#define mmACP_SCRATCH_REG_122                           0x12501E8
-+#define mmACP_SCRATCH_REG_123                           0x12501EC
-+#define mmACP_SCRATCH_REG_124                           0x12501F0
-+#define mmACP_SCRATCH_REG_125                           0x12501F4
-+#define mmACP_SCRATCH_REG_126                           0x12501F8
-+#define mmACP_SCRATCH_REG_127                           0x12501FC
-+#define mmACP_SCRATCH_REG_128                           0x1250200
-+
-+
-+// Registers from ACP_SW_ACLK block
-+
-+#define mmSW_CORB_Base_Address                          0x1243200
-+#define mmSW_CORB_Write_Pointer                         0x1243204
-+#define mmSW_CORB_Read_Pointer                          0x1243208
-+#define mmSW_CORB_Control                               0x124320C
-+#define mmSW_CORB_Size                                  0x1243214
-+#define mmSW_RIRB_Base_Address                          0x1243218
-+#define mmSW_RIRB_Write_Pointer                         0x124321C
-+#define mmSW_RIRB_Response_Interrupt_Count              0x1243220
-+#define mmSW_RIRB_Control                               0x1243224
-+#define mmSW_RIRB_Size                                  0x1243228
-+#define mmSW_RIRB_FIFO_MIN_THDL                         0x124322C
-+#define mmSW_imm_cmd_UPPER_WORD                         0x1243230
-+#define mmSW_imm_cmd_LOWER_QWORD                        0x1243234
-+#define mmSW_imm_resp_UPPER_WORD                        0x1243238
-+#define mmSW_imm_resp_LOWER_QWORD                       0x124323C
-+#define mmSW_imm_cmd_sts                                0x1243240
-+#define mmSW_BRA_BASE_ADDRESS                           0x1243244
-+#define mmSW_BRA_TRANSFER_SIZE                          0x1243248
-+#define mmSW_BRA_DMA_BUSY                               0x124324C
-+#define mmSW_BRA_RESP                                   0x1243250
-+#define mmSW_BRA_RESP_FRAME_ADDR                        0x1243254
-+#define mmSW_BRA_CURRENT_TRANSFER_SIZE                  0x1243258
-+#define mmSW_STATE_CHANGE_STATUS_0TO7                   0x124325C
-+#define mmSW_STATE_CHANGE_STATUS_8TO11                  0x1243260
-+#define mmSW_STATE_CHANGE_STATUS_MASK_0to7              0x1243264
-+#define mmSW_STATE_CHANGE_STATUS_MASK_8to11             0x1243268
-+#define mmSW_CLK_FREQUENCY_CTRL                         0x124326C
-+#define mmSW_ERROR_INTR_MASK                            0x1243270
-+#define mmSW_PHY_TEST_MODE_DATA_OFF                     0x1243274
-+
-+
-+// Registers from ACP_SW_SWCLK block
-+
-+#define mmACP_SW_EN                                     0x1243000
-+#define mmACP_SW_EN_STATUS                              0x1243004
-+#define mmACP_SW_FRAMESIZE                              0x1243008
-+#define mmACP_SW_SSP_Counter                            0x124300C
-+#define mmACP_SW_Audio_TX_EN                            0x1243010
-+#define mmACP_SW_Audio_TX_EN_STATUS                     0x1243014
-+#define mmACP_SW_Audio_TX_Frame_Format                  0x1243018
-+#define mmACP_SW_Audio_TX_SampleInterval                0x124301C
-+#define mmACP_SW_Audio_TX_Hctrl_DP0                     0x1243020
-+#define mmACP_SW_Audio_TX_Hctrl_DP1                     0x1243024
-+#define mmACP_SW_Audio_TX_Hctrl_DP2                     0x1243028
-+#define mmACP_SW_Audio_TX_Hctrl_DP3                     0x124302C
-+#define mmACP_SW_Audio_TX_offset_DP0                    0x1243030
-+#define mmACP_SW_Audio_TX_offset_DP1                    0x1243034
-+#define mmACP_SW_Audio_TX_offset_DP2                    0x1243038
-+#define mmACP_SW_Audio_TX_offset_DP3                    0x124303C
-+#define mmACP_SW_Audio_TX_Channel_Enable_DP0            0x1243040
-+#define mmACP_SW_Audio_TX_Channel_Enable_DP1            0x1243044
-+#define mmACP_SW_Audio_TX_Channel_Enable_DP2            0x1243048
-+#define mmACP_SW_Audio_TX_Channel_Enable_DP3            0x124304C
-+#define mmACP_SW_BT_TX_EN                               0x1243050
-+#define mmACP_SW_BT_TX_EN_STATUS                        0x1243054
-+#define mmACP_SW_BT_TX_Frame_Format                     0x1243058
-+#define mmACP_SW_BT_TX_SampleInterval                   0x124305C
-+#define mmACP_SW_BT_TX_Hctrl                            0x1243060
-+#define mmACP_SW_BT_TX_offset                           0x1243064
-+#define mmACP_SW_BT_TX_Channel_Enable_DP0               0x1243068
-+#define mmACP_SW_Headset_TX_EN                          0x124306C
-+#define mmACP_SW_Headset_TX_EN_STATUS                   0x1243070
-+#define mmACP_SW_Headset_TX_Frame_Format                0x1243074
-+#define mmACP_SW_Headset_TX_SampleInterval              0x1243078
-+#define mmACP_SW_Headset_TX_Hctrl                       0x124307C
-+#define mmACP_SW_Headset_TX_offset                      0x1243080
-+#define mmACP_SW_Headset_TX_Channel_Enable_DP0          0x1243084
-+#define mmACP_SW_Audio_RX_EN                            0x1243088
-+#define mmACP_SW_Audio_RX_EN_STATUS                     0x124308C
-+#define mmACP_SW_Audio_RX_Frame_Format                  0x1243090
-+#define mmACP_SW_Audio_RX_SampleInterval                0x1243094
-+#define mmACP_SW_Audio_RX_Hctrl_DP0                     0x1243098
-+#define mmACP_SW_Audio_RX_Hctrl_DP1                     0x124309C
-+#define mmACP_SW_Audio_RX_Hctrl_DP2                     0x1243100
-+#define mmACP_SW_Audio_RX_Hctrl_DP3                     0x1243104
-+#define mmACP_SW_Audio_RX_offset_DP0                    0x1243108
-+#define mmACP_SW_Audio_RX_offset_DP1                    0x124310C
-+#define mmACP_SW_Audio_RX_offset_DP2                    0x1243110
-+#define mmACP_SW_Audio_RX_offset_DP3                    0x1243114
-+#define mmACP_SW_Audio_RX_Channel_Enable_DP0            0x1243118
-+#define mmACP_SW_Audio_RX_Channel_Enable_DP1            0x124311C
-+#define mmACP_SW_Audio_RX_Channel_Enable_DP2            0x1243120
-+#define mmACP_SW_Audio_RX_Channel_Enable_DP3            0x1243124
-+#define mmACP_SW_BT_RX_EN                               0x1243128
-+#define mmACP_SW_BT_RX_EN_STATUS                        0x124312C
-+#define mmACP_SW_BT_RX_Frame_Format                     0x1243130
-+#define mmACP_SW_BT_RX_SampleInterval                   0x1243134
-+#define mmACP_SW_BT_RX_Hctrl                            0x1243138
-+#define mmACP_SW_BT_RX_offset                           0x124313C
-+#define mmACP_SW_BT_RX_Channel_Enable_DP0               0x1243140
-+#define mmACP_SW_Headset_RX_EN                          0x1243144
-+#define mmACP_SW_Headset_RX_EN_STATUS                   0x1243148
-+#define mmACP_SW_Headset_RX_Frame_Format                0x124314C
-+#define mmACP_SW_Headset_RX_SampleInterval              0x1243150
-+#define mmACP_SW_Headset_RX_Hctrl                       0x1243154
-+#define mmACP_SW_Headset_RX_offset                      0x1243158
-+#define mmACP_SW_Headset_RX_Channel_Enable_DP0          0x124315C
-+#define mmACP_SW_BPT_PORT_EN                            0x1243160
-+#define mmACP_SW_BPT_PORT_EN_STATUS                     0x1243164
-+#define mmACP_SW_BPT_PORT_Frame_Format                  0x1243168
-+#define mmACP_SW_BPT_PORT_SampleInterval                0x124316C
-+#define mmACP_SW_BPT_PORT_Hctrl                         0x1243170
-+#define mmACP_SW_BPT_PORT_offset                        0x1243174
-+#define mmACP_SW_BPT_PORT_Channel_Enable                0x1243178
-+#define mmACP_SW_BPT_PORT_First_byte_addr               0x124317C
-+#define mmACP_SW_CLK_RESUME_CTRL                        0x1243180
-+#define mmACP_SW_CLK_RESUME_Delay_Cntr                  0x1243184
-+#define mmACP_SW_BUS_RESET_CTRL                         0x1243188
-+#define mmACP_SW_PRBS_ERR_STATUS                        0x124318C
-+
-+
-+// Registers from ACP_AUDIO_BUFFERS block
-+
-+#define mmACP_I2S_RX_RINGBUFADDR                        0x1242000
-+#define mmACP_I2S_RX_RINGBUFSIZE                        0x1242004
-+#define mmACP_I2S_RX_LINKPOSITIONCNTR                   0x1242008
-+#define mmACP_I2S_RX_FIFOADDR                           0x124200C
-+#define mmACP_I2S_RX_FIFOSIZE                           0x1242010
-+#define mmACP_I2S_RX_DMA_SIZE                           0x1242014
-+#define mmACP_I2S_RX_LINEARPOSITIONCNTR_HIGH            0x1242018
-+#define mmACP_I2S_RX_LINEARPOSITIONCNTR_LOW             0x124201C
-+#define mmACP_I2S_RX_INTR_WATERMARK_SIZE                0x1242020
-+#define mmACP_I2S_TX_RINGBUFADDR                        0x1242024
-+#define mmACP_I2S_TX_RINGBUFSIZE                        0x1242028
-+#define mmACP_I2S_TX_LINKPOSITIONCNTR                   0x124202C
-+#define mmACP_I2S_TX_FIFOADDR                           0x1242030
-+#define mmACP_I2S_TX_FIFOSIZE                           0x1242034
-+#define mmACP_I2S_TX_DMA_SIZE                           0x1242038
-+#define mmACP_I2S_TX_LINEARPOSITIONCNTR_HIGH            0x124203C
-+#define mmACP_I2S_TX_LINEARPOSITIONCNTR_LOW             0x1242040
-+#define mmACP_I2S_TX_INTR_WATERMARK_SIZE                0x1242044
-+#define mmACP_BT_RX_RINGBUFADDR                         0x1242048
-+#define mmACP_BT_RX_RINGBUFSIZE                         0x124204C
-+#define mmACP_BT_RX_LINKPOSITIONCNTR                    0x1242050
-+#define mmACP_BT_RX_FIFOADDR                            0x1242054
-+#define mmACP_BT_RX_FIFOSIZE                            0x1242058
-+#define mmACP_BT_RX_DMA_SIZE                            0x124205C
-+#define mmACP_BT_RX_LINEARPOSITIONCNTR_HIGH             0x1242060
-+#define mmACP_BT_RX_LINEARPOSITIONCNTR_LOW              0x1242064
-+#define mmACP_BT_RX_INTR_WATERMARK_SIZE                 0x1242068
-+#define mmACP_BT_TX_RINGBUFADDR                         0x124206C
-+#define mmACP_BT_TX_RINGBUFSIZE                         0x1242070
-+#define mmACP_BT_TX_LINKPOSITIONCNTR                    0x1242074
-+#define mmACP_BT_TX_FIFOADDR                            0x1242078
-+#define mmACP_BT_TX_FIFOSIZE                            0x124207C
-+#define mmACP_BT_TX_DMA_SIZE                            0x1242080
-+#define mmACP_BT_TX_LINEARPOSITIONCNTR_HIGH             0x1242084
-+#define mmACP_BT_TX_LINEARPOSITIONCNTR_LOW              0x1242088
-+#define mmACP_BT_TX_INTR_WATERMARK_SIZE                 0x124208C
-+#define mmACP_HS_RX_RINGBUFADDR                         0x1242090
-+#define mmACP_HS_RX_RINGBUFSIZE                         0x1242094
-+#define mmACP_HS_RX_LINKPOSITIONCNTR                    0x1242098
-+#define mmACP_HS_RX_FIFOADDR                            0x124209C
-+#define mmACP_HS_RX_FIFOSIZE                            0x12420A0
-+#define mmACP_HS_RX_DMA_SIZE                            0x12420A4
-+#define mmACP_HS_RX_LINEARPOSITIONCNTR_HIGH             0x12420A8
-+#define mmACP_HS_RX_LINEARPOSITIONCNTR_LOW              0x12420AC
-+#define mmACP_HS_RX_INTR_WATERMARK_SIZE                 0x12420B0
-+#define mmACP_HS_TX_RINGBUFADDR                         0x12420B4
-+#define mmACP_HS_TX_RINGBUFSIZE                         0x12420B8
-+#define mmACP_HS_TX_LINKPOSITIONCNTR                    0x12420BC
-+#define mmACP_HS_TX_FIFOADDR                            0x12420C0
-+#define mmACP_HS_TX_FIFOSIZE                            0x12420C4
-+#define mmACP_HS_TX_DMA_SIZE                            0x12420C8
-+#define mmACP_HS_TX_LINEARPOSITIONCNTR_HIGH             0x12420CC
-+#define mmACP_HS_TX_LINEARPOSITIONCNTR_LOW              0x12420D0
-+#define mmACP_HS_TX_INTR_WATERMARK_SIZE                 0x12420D4
-+
-+
-+// Registers from ACP_I2S_TDM block
-+
-+#define mmACP_I2STDM_IER                                0x1242400
-+#define mmACP_I2STDM_IRER                               0x1242404
-+#define mmACP_I2STDM_RXFRMT                             0x1242408
-+#define mmACP_I2STDM_ITER                               0x124240C
-+#define mmACP_I2STDM_TXFRMT                             0x1242410
-+
-+
-+// Registers from ACP_BT_TDM block
-+
-+#define mmACP_BTTDM_IER                                 0x1242800
-+#define mmACP_BTTDM_IRER                                0x1242804
-+#define mmACP_BTTDM_RXFRMT                              0x1242808
-+#define mmACP_BTTDM_ITER                                0x124280C
-+#define mmACP_BTTDM_TXFRMT                              0x1242810
-+
-+
-+// Registers from AZALIA_IP block
-+
-+#define mmAudio_Az_Global_Capabilities                  0x1200000
-+#define mmAudio_Az_Minor_Version                        0x1200002
-+#define mmAudio_Az_Major_Version                        0x1200003
-+#define mmAudio_Az_Output_Payload_Capability            0x1200004
-+#define mmAudio_Az_Input_Payload_Capability             0x1200006
-+#define mmAudio_Az_Global_Control                       0x1200008
-+#define mmAudio_Az_Wake_Enable                          0x120000C
-+#define mmAudio_Az_State_Change_Status                  0x120000E
-+#define mmAudio_Az_Global_Status                        0x1200010
-+#define mmAudio_Az_Linked_List_Capability_Header        0x1200014
-+#define mmAudio_Az_Output_Stream_Payload_Capability     0x1200018
-+#define mmAudio_Az_Input_Stream_Payload_Capability      0x120001A
-+#define mmAudio_Az_Interrupt_Control                    0x1200020
-+#define mmAudio_Az_Interrupt_Status                     0x1200024
-+#define mmAudio_Az_Wall_Clock_Counter                   0x1200030
-+#define mmAudio_Az_Stream_Synchronization               0x1200038
-+#define mmAudio_Az_CORB_Lower_Base_Address              0x1200040
-+#define mmAudio_Az_CORB_Upper_Base_Address              0x1200044
-+#define mmAudio_Az_CORB_Write_Pointer                   0x1200048
-+#define mmAudio_Az_CORB_Read_Pointer                    0x120004A
-+#define mmAudio_Az_CORB_Control                         0x120004C
-+#define mmAudio_Az_CORB_Status                          0x120004D
-+#define mmAudio_Az_CORB_Size                            0x120004E
-+#define mmAudio_Az_RIRB_Lower_Base_Address              0x1200050
-+#define mmAudio_Az_RIRB_Upper_Base_Address              0x1200054
-+#define mmAudio_Az_RIRB_Write_Pointer                   0x1200058
-+#define mmAudio_Az_RIRB_Response_Interrupt_Count        0x120005A
-+#define mmAudio_Az_RIRB_Control                         0x120005C
-+#define mmAudio_Az_RIRB_Status                          0x120005D
-+#define mmAudio_Az_RIRB_Size                            0x120005E
-+#define mmAudio_Az_Immediate_Command_Output_Interface   0x1200060
-+#define mmAudio_Az_Immediate_Response_Input_Interface   0x1200064
-+#define mmAudio_Az_Immediate_Command_Status             0x1200068
-+#define mmAudio_Az_DPLBASE                              0x1200070
-+#define mmAudio_Az_DPUBASE                              0x1200074
-+#define mmAudio_Az_Input_SD0CTL_and_STS                 0x1200080
-+#define mmAudio_Az_Input_SD0LPIB                        0x1200084
-+#define mmAudio_Az_Input_SD0CBL                         0x1200088
-+#define mmAudio_Az_Input_SD0LVI                         0x120008C
-+#define mmAudio_Az_Input_SD0FIFOS                       0x1200090
-+#define mmAudio_Az_Input_SD0FMT                         0x1200092
-+#define mmAudio_Az_Input_SD0BDPL                        0x1200098
-+#define mmAudio_Az_Input_SD0BDPU                        0x120009C
-+#define mmAudio_Az_Input_SD1CTL_and_STS                 0x12000A0
-+#define mmAudio_Az_Input_SD1LPIB                        0x12000A4
-+#define mmAudio_Az_Input_SD1CBL                         0x12000A8
-+#define mmAudio_Az_Input_SD1LVI                         0x12000AC
-+#define mmAudio_Az_Input_SD1FIFOS                       0x12000B0
-+#define mmAudio_Az_Input_SD1FMT                         0x12000B2
-+#define mmAudio_Az_Input_SD1BDPL                        0x12000B8
-+#define mmAudio_Az_Input_SD1BDPU                        0x12000BC
-+#define mmAudio_Az_Input_SD2CTL_and_STS                 0x12000C0
-+#define mmAudio_Az_Input_SD2LPIB                        0x12000C4
-+#define mmAudio_Az_Input_SD2CBL                         0x12000C8
-+#define mmAudio_Az_Input_SD2LVI                         0x12000CC
-+#define mmAudio_Az_Input_SD2FIFOS                       0x12000D0
-+#define mmAudio_Az_Input_SD2FMT                         0x12000D2
-+#define mmAudio_Az_Input_SD2BDPL                        0x12000D8
-+#define mmAudio_Az_Input_SD2BDPU                        0x12000DC
-+#define mmAudio_Az_Input_SD3CTL_and_STS                 0x12000E0
-+#define mmAudio_Az_Input_SD3LPIB                        0x12000E4
-+#define mmAudio_Az_Input_SD3CBL                         0x12000E8
-+#define mmAudio_Az_Input_SD3LVI                         0x12000EC
-+#define mmAudio_Az_Input_SD3FIFOS                       0x12000F0
-+#define mmAudio_Az_Input_SD3FMT                         0x12000F2
-+#define mmAudio_Az_Input_SD3BDPL                        0x12000F8
-+#define mmAudio_Az_Input_SD3BDPU                        0x12000FC
-+#define mmAudio_Az_Output_SD0CTL_and_STS                0x1200100
-+#define mmAudio_Az_Output_SD0LPIB                       0x1200104
-+#define mmAudio_Az_Output_SD0CBL                        0x1200108
-+#define mmAudio_Az_Output_SD0LVI                        0x120010C
-+#define mmAudio_Az_Output_SD0FIFOS                      0x1200110
-+#define mmAudio_Az_Output_SD0FMT                        0x1200112
-+#define mmAudio_Az_Output_SD0BDPL                       0x1200118
-+#define mmAudio_Az_Output_SD0BDPU                       0x120011C
-+#define mmAudio_Az_Output_SD1CTL_and_STS                0x1200120
-+#define mmAudio_Az_Output_SD1LPIB                       0x1200124
-+#define mmAudio_Az_Output_SD1CBL                        0x1200128
-+#define mmAudio_Az_Output_SD1LVI                        0x120012C
-+#define mmAudio_Az_Output_SD1FIFOS                      0x1200130
-+#define mmAudio_Az_Output_SD1FMT                        0x1200132
-+#define mmAudio_Az_Output_SD1BDPL                       0x1200138
-+#define mmAudio_Az_Output_SD1BDPU                       0x120013C
-+#define mmAudio_Az_Output_SD2CTL_and_STS                0x1200140
-+#define mmAudio_Az_Output_SD2LPIB                       0x1200144
-+#define mmAudio_Az_Output_SD2CBL                        0x1200148
-+#define mmAudio_Az_Output_SD2LVI                        0x120014C
-+#define mmAudio_Az_Output_SD2FIFOS                      0x1200150
-+#define mmAudio_Az_Output_SD2FMT                        0x1200152
-+#define mmAudio_Az_Output_SD2BDPL                       0x1200158
-+#define mmAudio_Az_Output_SD2BDPU                       0x120015C
-+#define mmAudio_Az_Output_SD3CTL_and_STS                0x1200160
-+#define mmAudio_Az_Output_SD3LPIB                       0x1200164
-+#define mmAudio_Az_Output_SD3CBL                        0x1200168
-+#define mmAudio_Az_Output_SD3LVI                        0x120016C
-+#define mmAudio_Az_Output_SD3FIFOS                      0x1200170
-+#define mmAudio_Az_Output_SD3FMT                        0x1200172
-+#define mmAudio_Az_Output_SD3BDPL                       0x1200178
-+#define mmAudio_Az_Output_SD3BDPU                       0x120017C
-+#define mmAudioAZ_Misc_Control_Register_1               0x1200180
-+#define mmAudioAZ_Misc_Control_Register_2               0x1200182
-+#define mmAudioAZ_Misc_Control_Register_3               0x1200183
-+#define mmAudio_AZ_Multiple_Links_Capability_Header     0x1200200
-+#define mmAudio_AZ_Multiple_Links_Capability_Declaration 0x1200204
-+#define mmAudio_AZ_Link0_Capabilities                   0x1200240
-+#define mmAudio_AZ_Link0_Control                        0x1200244
-+#define mmAudio_AZ_Link0_Output_Stream_ID               0x1200248
-+#define mmAudio_AZ_Link0_SDI_Identifier                 0x120024C
-+#define mmAudio_AZ_Link0_Per_Stream_Overhead            0x1200250
-+#define mmAudio_AZ_Link0_Wall_Frame_Counter             0x1200258
-+#define mmAudio_AZ_Link0_Output_Payload_Capability_L    0x1200260
-+#define mmAudio_AZ_Link0_Output_Payload_Capability_U    0x1200264
-+#define mmAudio_AZ_Link0_Input_Payload_Capability_L     0x1200270
-+#define mmAudio_AZ_Link0_Input_Payload_Capability_U     0x1200274
-+#define mmAudio_Az_Input_SD0LICBA                       0x1202084
-+#define mmAudio_Az_Input_SD1LICBA                       0x12020A4
-+#define mmAudio_Az_Input_SD2LICBA                       0x12020C4
-+#define mmAudio_Az_Input_SD3LICBA                       0x12020E4
-+#define mmAudio_Az_Output_SD0LICBA                      0x1202104
-+#define mmAudio_Az_Output_SD1LICBA                      0x1202124
-+#define mmAudio_Az_Output_SD2LICBA                      0x1202144
-+#define mmAudio_Az_Output_SD3LICBA                      0x1202164
-+#define mmAUDIO_AZ_POWER_MANAGEMENT_CONTROL             0x1204000
-+#define mmAUDIO_AZ_IOC_SOFTRST_CONTROL                  0x1204004
-+#define mmAUDIO_AZ_IOC_CLKGATE_CONTROL                  0x1204008
-+
-+
-+// Registers from ACP_AZALIA block
-+
-+#define mmACP_AZ_PAGE0_LBASE_ADDR                       0x1243800
-+#define mmACP_AZ_PAGE0_UBASE_ADDR                       0x1243804
-+#define mmACP_AZ_PAGE0_PGEN_SIZE                        0x1243808
-+#define mmACP_AZ_PAGE0_OFFSET                           0x124380C
-+#define mmACP_AZ_PAGE1_LBASE_ADDR                       0x1243810
-+#define mmACP_AZ_PAGE1_UBASE_ADDR                       0x1243814
-+#define mmACP_AZ_PAGE1_PGEN_SIZE                        0x1243818
-+#define mmACP_AZ_PAGE1_OFFSET                           0x124381C
-+#define mmACP_AZ_PAGE2_LBASE_ADDR                       0x1243820
-+#define mmACP_AZ_PAGE2_UBASE_ADDR                       0x1243824
-+#define mmACP_AZ_PAGE2_PGEN_SIZE                        0x1243828
-+#define mmACP_AZ_PAGE2_OFFSET                           0x124382C
-+#define mmACP_AZ_PAGE3_LBASE_ADDR                       0x1243830
-+#define mmACP_AZ_PAGE3_UBASE_ADDR                       0x1243834
-+#define mmACP_AZ_PAGE3_PGEN_SIZE                        0x1243838
-+#define mmACP_AZ_PAGE3_OFFSET                           0x124383C
-+#define mmACP_AZ_PAGE4_LBASE_ADDR                       0x1243840
-+#define mmACP_AZ_PAGE4_UBASE_ADDR                       0x1243844
-+#define mmACP_AZ_PAGE4_PGEN_SIZE                        0x1243848
-+#define mmACP_AZ_PAGE4_OFFSET                           0x124384C
-+#define mmACP_AZ_PAGE5_LBASE_ADDR                       0x1243850
-+#define mmACP_AZ_PAGE5_UBASE_ADDR                       0x1243854
-+#define mmACP_AZ_PAGE5_PGEN_SIZE                        0x1243858
-+#define mmACP_AZ_PAGE5_OFFSET                           0x124385C
-+#define mmACP_AZ_PAGE6_LBASE_ADDR                       0x1243860
-+#define mmACP_AZ_PAGE6_UBASE_ADDR                       0x1243864
-+#define mmACP_AZ_PAGE6_PGEN_SIZE                        0x1243868
-+#define mmACP_AZ_PAGE6_OFFSET                           0x124386C
-+#define mmACP_AZ_PAGE7_LBASE_ADDR                       0x1243870
-+#define mmACP_AZ_PAGE7_UBASE_ADDR                       0x1243874
-+#define mmACP_AZ_PAGE7_PGEN_SIZE                        0x1243878
-+#define mmACP_AZ_PAGE7_OFFSET                           0x124387C
-+
-+
-+#endif
---- linux-4.14/sound/soc/amd/raven/dummy-w5102.c.0130~	2017-12-14 06:39:58.534903650 +0100
-+++ linux-4.14/sound/soc/amd/raven/dummy-w5102.c	2017-12-14 06:39:58.534903650 +0100
-@@ -0,0 +1,102 @@
-+/*
-+ * dummy audio codec driver
-+ *
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be included in
-+ * all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ *
-+ */
-+
-+#include <linux/module.h>
-+#include <sound/soc.h>
-+
-+#define W5102_RATES	SNDRV_PCM_RATE_8000_96000
-+#define W5102_FORMATS	(SNDRV_PCM_FMTBIT_S16_LE | \
-+			SNDRV_PCM_FMTBIT_S32_LE | \
-+			SNDRV_PCM_FMTBIT_S24_LE)
-+
-+static const struct snd_soc_dapm_widget w5102_widgets[] = {
-+	SND_SOC_DAPM_OUTPUT("dummy-w5102-out"),
-+	SND_SOC_DAPM_INPUT("dummy-w5102-in"),
-+};
-+
-+static const struct snd_soc_dapm_route w5102_routes[] = {
-+	{ "dummy-w5102-out", NULL, "Playback" },
-+	{ "Capture", NULL, "dummy-w5102-in" },
-+};
-+
-+static struct snd_soc_codec_driver soc_codec_w5102_dummy = {
-+	.component_driver = {
-+		.dapm_widgets = w5102_widgets,
-+		.num_dapm_widgets = ARRAY_SIZE(w5102_widgets),
-+		.dapm_routes = w5102_routes,
-+		.num_dapm_routes = ARRAY_SIZE(w5102_routes),
-+	},
-+};
-+
-+static struct snd_soc_dai_driver w5102_stub_dai = {
-+	.name		= "dummy_w5102_dai",
-+	.playback	= {
-+		.stream_name	= "Playback",
-+		.channels_min	= 2,
-+		.channels_max	= 6,
-+		.rates		= W5102_RATES,
-+		.formats	= W5102_FORMATS,
-+	},
-+	.capture	= {
-+		.stream_name	= "Capture",
-+		.channels_min	= 2,
-+		.channels_max	= 2,
-+		.rates		= W5102_RATES,
-+		.formats	= W5102_FORMATS,
-+	},
-+
-+};
-+
-+static int dummy_w5102_probe(struct platform_device *pdev)
-+{
-+	int ret;
-+
-+	ret = snd_soc_register_codec(&pdev->dev, &soc_codec_w5102_dummy,
-+			&w5102_stub_dai, 1);
-+	return ret;
-+}
-+
-+static int dummy_w5102_remove(struct platform_device *pdev)
-+{
-+	snd_soc_unregister_codec(&pdev->dev);
-+	return 0;
-+}
-+
-+
-+static struct platform_driver dummy_w5102_driver = {
-+	.probe		= dummy_w5102_probe,
-+	.remove		= dummy_w5102_remove,
-+	.driver		= {
-+		.name	= "dummy_w5102",
-+		.owner	= THIS_MODULE,
-+	},
-+};
-+
-+module_platform_driver(dummy_w5102_driver);
-+
-+MODULE_DESCRIPTION("dummy-w5102 dummy codec driver");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform: dummy_w5102");
---- linux-4.14/sound/soc/amd/raven/Makefile.0130~	2017-12-14 06:39:58.534903650 +0100
-+++ linux-4.14/sound/soc/amd/raven/Makefile	2017-12-14 06:39:58.534903650 +0100
-@@ -0,0 +1,8 @@
-+snd-pci-acp3x-objs	:= pci-acp3x.o
-+snd-acp3x-pcm-dma-objs	:= acp3x-pcm-dma.o
-+snd-soc-dummy-w5102-objs := dummy-w5102.o
-+snd-soc-acp3x-mach-objs := acp3x-dummy5102.o
-+obj-$(CONFIG_SND_SOC_AMD_ACP3x)	 += snd-pci-acp3x.o
-+obj-$(CONFIG_SND_SOC_AMD_ACP3x)	 += snd-acp3x-pcm-dma.o
-+obj-$(CONFIG_SND_SOC_AMD_ACP3x)	+= snd-soc-dummy-w5102.o
-+obj-$(CONFIG_SND_SOC_AMD_ACP3x)	+= snd-soc-acp3x-mach.o
---- linux-4.14/sound/soc/amd/raven/pci-acp3x.c.0130~	2017-12-14 06:39:58.534903650 +0100
-+++ linux-4.14/sound/soc/amd/raven/pci-acp3x.c	2017-12-14 06:39:58.534903650 +0100
-@@ -0,0 +1,189 @@
-+/*
-+ * AMD ALSA SoC PCM Driver
-+ *
-+ * Copyright 2016 Advanced Micro Devices, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ */
-+
-+#include <linux/pci.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/interrupt.h>
-+
-+#include "acp3x.h"
-+
-+struct acp3x_dev_data {
-+	void __iomem *acp3x_base;
-+	bool acp3x_audio_mode;
-+	struct resource *res;
-+	struct platform_device *pdev[3];
-+};
-+
-+static int snd_acp3x_probe(struct pci_dev *pci,
-+			   const struct pci_device_id *pci_id)
-+{
-+	int ret;
-+	u32 addr, val;
-+	struct acp3x_dev_data *adata;
-+	struct platform_device_info pdevinfo;
-+	unsigned int irqflags;
-+
-+	if (pci_enable_device(pci)) {
-+		dev_err(&pci->dev, "pci_enable_device failed\n");
-+		return -ENODEV;
-+	}
-+
-+	ret = pci_request_regions(pci, "AMD ACP3x audio");
-+	if (ret < 0) {
-+		dev_err(&pci->dev, "pci_request_regions failed\n");
-+		goto disable_pci;
-+	}
-+
-+	adata = devm_kzalloc(&pci->dev, sizeof(struct acp3x_dev_data),
-+				GFP_KERNEL);
-+	if (adata == NULL) {
-+		ret = -ENOMEM;
-+		goto release_regions;
-+	}
-+
-+	/* check for msi interrupt support */
-+	ret = pci_enable_msi(pci);
-+	if (ret)
-+		/* msi is not enabled */
-+		irqflags = IRQF_SHARED;
-+	else
-+		/* msi is enabled */
-+		irqflags = 0;
-+
-+	addr = pci_resource_start(pci, 0);
-+	adata->acp3x_base = ioremap(addr, pci_resource_len(pci, 0));
-+	if (adata->acp3x_base == NULL) {
-+		ret = -ENOMEM;
-+		goto release_regions;
-+	}
-+
-+	pci_set_drvdata(pci, adata);
-+
-+	val = rv_readl(adata->acp3x_base + mmACP_I2S_PIN_CONFIG);
-+	if (val == 0x4) {
-+		adata->res = devm_kzalloc(&pci->dev,
-+				sizeof(struct resource) * 2,
-+				GFP_KERNEL);
-+		if (adata->res == NULL) {
-+			ret = -ENOMEM;
-+			goto unmap_mmio;
-+		}
-+
-+		adata->res[0].name = "acp3x_i2s_iomem";
-+		adata->res[0].flags = IORESOURCE_MEM;
-+		adata->res[0].start = addr;
-+		adata->res[0].end = addr + (ACP3x_REG_END - ACP3x_REG_START);
-+
-+		adata->res[1].name = "acp3x_i2s_irq";
-+		adata->res[1].flags = IORESOURCE_IRQ;
-+		adata->res[1].start = pci->irq;
-+		adata->res[1].end = pci->irq;
-+
-+		adata->acp3x_audio_mode = ACP3x_I2S_MODE;
-+
-+		memset(&pdevinfo, 0, sizeof(pdevinfo));
-+		pdevinfo.name = "acp3x_rv_i2s";
-+		pdevinfo.id = 0;
-+		pdevinfo.parent = &pci->dev;
-+		pdevinfo.num_res = 2;
-+		pdevinfo.res = adata->res;
-+		pdevinfo.data = &irqflags;
-+		pdevinfo.size_data = sizeof(irqflags);
-+
-+		adata->pdev[0] = platform_device_register_full(&pdevinfo);
-+		if (adata->pdev[0] == NULL) {
-+			dev_err(&pci->dev, "cannot register %s device\n",
-+				pdevinfo.name);
-+			ret = -ENODEV;
-+			goto unmap_mmio;
-+		}
-+
-+		/* create dummy codec device */
-+		adata->pdev[1] = platform_device_register_simple("dummy_w5102",
-+					0, NULL, 0);
-+		if (IS_ERR(adata->pdev[1])) {
-+			dev_err(&pci->dev, "Cannot register dummy_w5102\n");
-+			ret = -ENODEV;
-+			goto unregister_pdev0;
-+		}
-+		/* create dummy mach device */
-+		adata->pdev[2] = platform_device_register_simple(
-+					"acp3x_w5102_mach", 0, NULL, 0);
-+		if (IS_ERR(adata->pdev[2])) {
-+			dev_err(&pci->dev, "Cannot register acp3x_w5102_mach\n");
-+			ret = -ENODEV;
-+			goto unregister_pdev1;
-+		}
-+	} else {
-+		dev_err(&pci->dev, "Inavlid ACP audio mode : %d\n", val);
-+		ret = -ENODEV;
-+		goto unmap_mmio;
-+	}
-+
-+	return 0;
-+
-+unregister_pdev1:
-+	platform_device_unregister(adata->pdev[1]);
-+unregister_pdev0:
-+	platform_device_unregister(adata->pdev[0]);
-+unmap_mmio:
-+	pci_disable_msi(pci);
-+	iounmap(adata->acp3x_base);
-+release_regions:
-+	pci_release_regions(pci);
-+disable_pci:
-+	pci_disable_device(pci);
-+
-+	return ret;
-+}
-+
-+static void snd_acp3x_remove(struct pci_dev *pci)
-+{
-+	int i;
-+	struct acp3x_dev_data *adata = pci_get_drvdata(pci);
-+
-+	if (adata->acp3x_audio_mode == ACP3x_I2S_MODE) {
-+		for (i = 2; i >= 0; i--)
-+			platform_device_unregister(adata->pdev[i]);
-+	}
-+
-+	iounmap(adata->acp3x_base);
-+
-+	pci_disable_msi(pci);
-+	pci_release_regions(pci);
-+	pci_disable_device(pci);
-+}
-+
-+static const struct pci_device_id snd_acp3x_ids[] = {
-+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x15e2),
-+	.class = PCI_CLASS_MULTIMEDIA_OTHER << 8,
-+	.class_mask = 0xffffff },
-+	{ 0, },
-+};
-+MODULE_DEVICE_TABLE(pci, snd_acp3x_ids);
-+
-+static struct pci_driver acp3x_driver  = {
-+	.name = KBUILD_MODNAME,
-+	.id_table = snd_acp3x_ids,
-+	.probe = snd_acp3x_probe,
-+	.remove = snd_acp3x_remove,
-+};
-+
-+module_pci_driver(acp3x_driver);
-+
-+MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
-+MODULE_DESCRIPTION("AMD ACP3x PCI driver");
-+MODULE_LICENSE("GPL v2");
---- linux-4.14/sound/soc/codecs/rt5645.c.0130~	2017-11-12 19:46:13.000000000 +0100
-+++ linux-4.14/sound/soc/codecs/rt5645.c	2017-12-14 06:39:58.534903650 +0100
-@@ -55,6 +55,8 @@ MODULE_PARM_DESC(quirk, "RT5645 pdata qu
- 
- #define RT5645_HWEQ_NUM 57
- 
-+#define TIME_TO_POWER_MS 400
-+
- static const struct regmap_range_cfg rt5645_ranges[] = {
- 	{
- 		.name = "PR",
-@@ -3703,6 +3705,7 @@ static int rt5645_i2c_probe(struct i2c_c
- 	int ret, i;
- 	unsigned int val;
- 	struct regmap *regmap;
-+	int timeout = TIME_TO_POWER_MS;
- 
- 	rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
- 				GFP_KERNEL);
-@@ -3777,6 +3780,15 @@ static int rt5645_i2c_probe(struct i2c_c
- 	}
- 	regmap_read(regmap, RT5645_VENDOR_ID2, &val);
- 
-+	/*
-+	 * Read for 400msec, as it is the interval required between
-+	 * read and power On.
-+	 */
-+	while (val != RT5645_DEVICE_ID && val != RT5650_DEVICE_ID && --timeout) {
-+		msleep(1);
-+		regmap_read(regmap, RT5645_VENDOR_ID2, &val);
-+	}
-+
- 	switch (val) {
- 	case RT5645_DEVICE_ID:
- 		rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
---- linux-4.14/tools/testing/scatterlist/linux/mm.h.0130~	2017-12-14 06:39:58.534903650 +0100
-+++ linux-4.14/tools/testing/scatterlist/linux/mm.h	2017-12-14 06:39:58.534903650 +0100
-@@ -0,0 +1,125 @@
-+#ifndef _LINUX_MM_H
-+#define _LINUX_MM_H
-+
-+#include <assert.h>
-+#include <string.h>
-+#include <stdlib.h>
-+#include <errno.h>
-+#include <limits.h>
-+#include <stdio.h>
-+
-+typedef unsigned long dma_addr_t;
-+
-+#define unlikely
-+
-+#define BUG_ON(x) assert(!(x))
-+
-+#define WARN_ON(condition) ({                                           \
-+	int __ret_warn_on = !!(condition);                              \
-+	unlikely(__ret_warn_on);                                        \
-+})
-+
-+#define WARN_ON_ONCE(condition) ({                              \
-+	int __ret_warn_on = !!(condition);                      \
-+	if (unlikely(__ret_warn_on))                            \
-+		assert(0);                                      \
-+	unlikely(__ret_warn_on);                                \
-+})
-+
-+#define PAGE_SIZE	(4096)
-+#define PAGE_SHIFT	(12)
-+#define PAGE_MASK	(~(PAGE_SIZE-1))
-+
-+#define __ALIGN_KERNEL(x, a)		__ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1)
-+#define __ALIGN_KERNEL_MASK(x, mask)	(((x) + (mask)) & ~(mask))
-+#define ALIGN(x, a)			__ALIGN_KERNEL((x), (a))
-+
-+#define PAGE_ALIGN(addr) ALIGN(addr, PAGE_SIZE)
-+
-+#define offset_in_page(p)	((unsigned long)(p) & ~PAGE_MASK)
-+
-+#define virt_to_page(x)	((void *)x)
-+#define page_address(x)	((void *)x)
-+
-+static inline unsigned long page_to_phys(struct page *page)
-+{
-+	assert(0);
-+
-+	return 0;
-+}
-+
-+#define page_to_pfn(page) ((unsigned long)(page) / PAGE_SIZE)
-+#define pfn_to_page(pfn) (void *)((pfn) * PAGE_SIZE)
-+#define nth_page(page,n) pfn_to_page(page_to_pfn((page)) + (n))
-+
-+#define __min(t1, t2, min1, min2, x, y) ({              \
-+	t1 min1 = (x);                                  \
-+	t2 min2 = (y);                                  \
-+	(void) (&min1 == &min2);                        \
-+	min1 < min2 ? min1 : min2; })
-+
-+#define ___PASTE(a,b) a##b
-+#define __PASTE(a,b) ___PASTE(a,b)
-+
-+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
-+
-+#define min(x, y)                                       \
-+	__min(typeof(x), typeof(y),                     \
-+	      __UNIQUE_ID(min1_), __UNIQUE_ID(min2_),   \
-+	      x, y)
-+
-+#define min_t(type, x, y)                               \
-+	__min(type, type,                               \
-+	      __UNIQUE_ID(min1_), __UNIQUE_ID(min2_),   \
-+	      x, y)
-+
-+#define preemptible() (1)
-+
-+static inline void *kmap(struct page *page)
-+{
-+	assert(0);
-+
-+	return NULL;
-+}
-+
-+static inline void *kmap_atomic(struct page *page)
-+{
-+	assert(0);
-+
-+	return NULL;
-+}
-+
-+static inline void kunmap(void *addr)
-+{
-+	assert(0);
-+}
-+
-+static inline void kunmap_atomic(void *addr)
-+{
-+	assert(0);
-+}
-+
-+static inline unsigned long __get_free_page(unsigned int flags)
-+{
-+	return (unsigned long)malloc(PAGE_SIZE);
-+}
-+
-+static inline void free_page(unsigned long page)
-+{
-+	free((void *)page);
-+}
-+
-+static inline void *kmalloc(unsigned int size, unsigned int flags)
-+{
-+	return malloc(size);
-+}
-+
-+#define kfree(x) free(x)
-+
-+#define kmemleak_alloc(a, b, c, d)
-+#define kmemleak_free(a)
-+
-+#define PageSlab(p) (0)
-+#define flush_kernel_dcache_page(p)
-+
-+#endif
---- linux-4.14/tools/testing/scatterlist/main.c.0130~	2017-12-14 06:39:58.534903650 +0100
-+++ linux-4.14/tools/testing/scatterlist/main.c	2017-12-14 06:39:58.534903650 +0100
-@@ -0,0 +1,79 @@
-+#include <stdio.h>
-+#include <assert.h>
-+
-+#include <linux/scatterlist.h>
-+
-+#define MAX_PAGES (64)
-+
-+static void set_pages(struct page **pages, const unsigned *array, unsigned num)
-+{
-+	unsigned int i;
-+
-+	assert(num < MAX_PAGES);
-+	for (i = 0; i < num; i++)
-+		pages[i] = (struct page *)(unsigned long)
-+			   ((1 + array[i]) * PAGE_SIZE);
-+}
-+
-+#define pfn(...) (unsigned []){ __VA_ARGS__ }
-+
-+int main(void)
-+{
-+	const unsigned int sgmax = SCATTERLIST_MAX_SEGMENT;
-+	struct test {
-+		int alloc_ret;
-+		unsigned num_pages;
-+		unsigned *pfn;
-+		unsigned size;
-+		unsigned int max_seg;
-+		unsigned int expected_segments;
-+	} *test, tests[] = {
-+		{ -EINVAL, 1, pfn(0), PAGE_SIZE, PAGE_SIZE + 1, 1 },
-+		{ -EINVAL, 1, pfn(0), PAGE_SIZE, 0, 1 },
-+		{ -EINVAL, 1, pfn(0), PAGE_SIZE, sgmax + 1, 1 },
-+		{ 0, 1, pfn(0), PAGE_SIZE, sgmax, 1 },
-+		{ 0, 1, pfn(0), 1, sgmax, 1 },
-+		{ 0, 2, pfn(0, 1), 2 * PAGE_SIZE, sgmax, 1 },
-+		{ 0, 2, pfn(1, 0), 2 * PAGE_SIZE, sgmax, 2 },
-+		{ 0, 3, pfn(0, 1, 2), 3 * PAGE_SIZE, sgmax, 1 },
-+		{ 0, 3, pfn(0, 2, 1), 3 * PAGE_SIZE, sgmax, 3 },
-+		{ 0, 3, pfn(0, 1, 3), 3 * PAGE_SIZE, sgmax, 2 },
-+		{ 0, 3, pfn(1, 2, 4), 3 * PAGE_SIZE, sgmax, 2 },
-+		{ 0, 3, pfn(1, 3, 4), 3 * PAGE_SIZE, sgmax, 2 },
-+		{ 0, 4, pfn(0, 1, 3, 4), 4 * PAGE_SIZE, sgmax, 2 },
-+		{ 0, 5, pfn(0, 1, 3, 4, 5), 5 * PAGE_SIZE, sgmax, 2 },
-+		{ 0, 5, pfn(0, 1, 3, 4, 6), 5 * PAGE_SIZE, sgmax, 3 },
-+		{ 0, 5, pfn(0, 1, 2, 3, 4), 5 * PAGE_SIZE, sgmax, 1 },
-+		{ 0, 5, pfn(0, 1, 2, 3, 4), 5 * PAGE_SIZE, 2 * PAGE_SIZE, 3 },
-+		{ 0, 6, pfn(0, 1, 2, 3, 4, 5), 6 * PAGE_SIZE, 2 * PAGE_SIZE, 3 },
-+		{ 0, 6, pfn(0, 2, 3, 4, 5, 6), 6 * PAGE_SIZE, 2 * PAGE_SIZE, 4 },
-+		{ 0, 6, pfn(0, 1, 3, 4, 5, 6), 6 * PAGE_SIZE, 2 * PAGE_SIZE, 3 },
-+		{ 0, 0, NULL, 0, 0, 0 },
-+	};
-+	unsigned int i;
-+
-+	for (i = 0, test = tests; test->expected_segments; test++, i++) {
-+		struct page *pages[MAX_PAGES];
-+		struct sg_table st;
-+		int ret;
-+
-+		set_pages(pages, test->pfn, test->num_pages);
-+
-+		ret = __sg_alloc_table_from_pages(&st, pages, test->num_pages,
-+						  0, test->size, test->max_seg,
-+						  GFP_KERNEL);
-+		assert(ret == test->alloc_ret);
-+
-+		if (test->alloc_ret)
-+			continue;
-+
-+		assert(st.nents == test->expected_segments);
-+		assert(st.orig_nents == test->expected_segments);
-+
-+		sg_free_table(&st);
-+	}
-+
-+	assert(i == (sizeof(tests) / sizeof(tests[0])) - 1);
-+
-+	return 0;
-+}
---- linux-4.14/tools/testing/scatterlist/Makefile.0130~	2017-12-14 06:39:58.534903650 +0100
-+++ linux-4.14/tools/testing/scatterlist/Makefile	2017-12-14 06:39:58.534903650 +0100
-@@ -0,0 +1,30 @@
-+CFLAGS += -I. -I../../include -g -O2 -Wall -fsanitize=address
-+LDFLAGS += -fsanitize=address -fsanitize=undefined
-+TARGETS = main
-+OFILES = main.o scatterlist.o
-+
-+ifeq ($(BUILD), 32)
-+        CFLAGS += -m32
-+        LDFLAGS += -m32
-+endif
-+
-+targets: include $(TARGETS)
-+
-+main: $(OFILES)
-+
-+clean:
-+	$(RM) $(TARGETS) $(OFILES) scatterlist.c linux/scatterlist.h linux/highmem.h linux/kmemleak.h asm/io.h
-+	@rmdir asm
-+
-+scatterlist.c: ../../../lib/scatterlist.c
-+	@sed -e 's/^static //' -e 's/__always_inline //' -e 's/inline //' < $< > $@
-+
-+.PHONY: include
-+
-+include: ../../../include/linux/scatterlist.h
-+	@mkdir -p linux
-+	@mkdir -p asm
-+	@touch asm/io.h
-+	@touch linux/highmem.h
-+	@touch linux/kmemleak.h
-+	@cp $< linux/scatterlist.h
diff --git a/disabled/4.18-bfq-sq-mq-v8r12-2K180817.patch b/disabled/4.18-bfq-sq-mq-v8r12-2K180817.patch
deleted file mode 100644
index 3f5f7f4..0000000
--- a/disabled/4.18-bfq-sq-mq-v8r12-2K180817.patch
+++ /dev/null
@@ -1,17959 +0,0 @@
-diff --git a/Documentation/block/bfq-iosched.txt b/Documentation/block/bfq-iosched.txt
-index 8d8d8f06cab2..30ef2dba85ad 100644
---- a/Documentation/block/bfq-iosched.txt
-+++ b/Documentation/block/bfq-iosched.txt
-@@ -11,6 +11,15 @@ controllers), BFQ's main features are:
-   groups (switching back to time distribution when needed to keep
-   throughput high).
- 
-+If bfq-mq patches have been applied, then the following three
-+instances of BFQ are available (otherwise only the first instance):
-+- bfq: mainline version of BFQ, for blk-mq
-+- bfq-mq: development version of BFQ for blk-mq; this version contains
-+   also all latest features and fixes not yet landed in mainline, plus many
-+   safety checks
-+- bfq-sq: BFQ for legacy blk; also this version contains latest features
-+   and fixes, as well as safety checks
-+
- In its default configuration, BFQ privileges latency over
- throughput. So, when needed for achieving a lower latency, BFQ builds
- schedules that may lead to a lower throughput. If your main or only
-@@ -22,27 +31,42 @@ latency and throughput, or on how to maximize throughput.
- 
- BFQ has a non-null overhead, which limits the maximum IOPS that a CPU
- can process for a device scheduled with BFQ. To give an idea of the
--limits on slow or average CPUs, here are, first, the limits of BFQ for
--three different CPUs, on, respectively, an average laptop, an old
--desktop, and a cheap embedded system, in case full hierarchical
--support is enabled (i.e., CONFIG_BFQ_GROUP_IOSCHED is set), but
-+limits on slow or average CPUs, here are, first, the limits of bfq-mq
-+and bfq for three different CPUs, on, respectively, an average laptop,
-+an old desktop, and a cheap embedded system, in case full hierarchical
-+support is enabled (i.e., CONFIG_MQ_BFQ_GROUP_IOSCHED is set for
-+bfq-mq, or CONFIG_BFQ_GROUP_IOSCHED is set for bfq), but
- CONFIG_DEBUG_BLK_CGROUP is not set (Section 4-2):
- - Intel i7-4850HQ: 400 KIOPS
- - AMD A8-3850: 250 KIOPS
- - ARM CortexTM-A53 Octa-core: 80 KIOPS
- 
--If CONFIG_DEBUG_BLK_CGROUP is set (and of course full hierarchical
--support is enabled), then the sustainable throughput with BFQ
--decreases, because all blkio.bfq* statistics are created and updated
--(Section 4-2). For BFQ, this leads to the following maximum
--sustainable throughputs, on the same systems as above:
-+As for bfq-sq, it cannot reach the above IOPS, because of the
-+inherent, lower parallelism of legacy blk and of the components within
-+it (including bfq-sq itself). In particular, results with
-+CONFIG_DEBUG_BLK_CGROUP unset are rather fluctuating. The limits
-+reported below for the case CONFIG_DEBUG_BLK_CGROUP set will however
-+provide a lower bound to the limits of bfq-sq.
-+
-+Turning back to bfq-mq and bfq, If CONFIG_DEBUG_BLK_CGROUP is set (and
-+of course full hierarchical support is enabled), then the sustainable
-+throughput with bfq-mq and bfq decreases, because all blkio.bfq*
-+statistics are created and updated (Section 4-2).  For bfq-mq and bfq,
-+this leads to the following maximum sustainable throughputs, on the
-+same systems as above:
- - Intel i7-4850HQ: 310 KIOPS
- - AMD A8-3850: 200 KIOPS
- - ARM CortexTM-A53 Octa-core: 56 KIOPS
- 
--BFQ works for multi-queue devices too.
-+Finally, if CONFIG_DEBUG_BLK_CGROUP is set (and full hierarchical
-+support is enabled), then bfq-sq exhibits the following limits:
-+- Intel i7-4850HQ: 250 KIOPS
-+- AMD A8-3850: 170 KIOPS
-+- ARM CortexTM-A53 Octa-core: 45 KIOPS
-+
-+BFQ works for multi-queue devices too (bfq and bfq-mq instances).
- 
--The table of contents follow. Impatients can just jump to Section 3.
-+The table of contents follows. Impatients can just jump to Section 3.
- 
- CONTENTS
- 
-@@ -509,25 +533,27 @@ To get proportional sharing of bandwidth with BFQ for a given device,
- BFQ must of course be the active scheduler for that device.
- 
- Within each group directory, the names of the files associated with
--BFQ-specific cgroup parameters and stats begin with the "bfq."
--prefix. So, with cgroups-v1 or cgroups-v2, the full prefix for
--BFQ-specific files is "blkio.bfq." or "io.bfq." For example, the group
--parameter to set the weight of a group with BFQ is blkio.bfq.weight
-+BFQ-specific cgroup parameters and stats begin with the "bfq.",
-+"bfq-sq." or "bfq-mq." prefix, depending on which instance of bfq you
-+want to use. So, with cgroups-v1 or cgroups-v2, the full prefix for
-+BFQ-specific files is "blkio.bfqX." or "io.bfqX.", where X can be ""
-+(i.e., null string), "-sq" or "-mq". For example, the group parameter
-+to set the weight of a group with the mainline BFQ is blkio.bfq.weight
- or io.bfq.weight.
- 
- As for cgroups-v1 (blkio controller), the exact set of stat files
--created, and kept up-to-date by bfq, depends on whether
--CONFIG_DEBUG_BLK_CGROUP is set. If it is set, then bfq creates all
-+created, and kept up-to-date by bfq*, depends on whether
-+CONFIG_DEBUG_BLK_CGROUP is set. If it is set, then bfq* creates all
- the stat files documented in
- Documentation/cgroup-v1/blkio-controller.txt. If, instead,
--CONFIG_DEBUG_BLK_CGROUP is not set, then bfq creates only the files
--blkio.bfq.io_service_bytes
--blkio.bfq.io_service_bytes_recursive
--blkio.bfq.io_serviced
--blkio.bfq.io_serviced_recursive
-+CONFIG_DEBUG_BLK_CGROUP is not set, then bfq* creates only the files
-+blkio.bfq*.io_service_bytes
-+blkio.bfq*.io_service_bytes_recursive
-+blkio.bfq*.io_serviced
-+blkio.bfq*.io_serviced_recursive
- 
- The value of CONFIG_DEBUG_BLK_CGROUP greatly influences the maximum
--throughput sustainable with bfq, because updating the blkio.bfq.*
-+throughput sustainable with bfq*, because updating the blkio.bfq*
- stats is rather costly, especially for some of the stats enabled by
- CONFIG_DEBUG_BLK_CGROUP.
- 
-@@ -536,7 +562,7 @@ Parameters to set
- 
- For each group, there is only the following parameter to set.
- 
--weight (namely blkio.bfq.weight or io.bfq-weight): the weight of the
-+weight (namely blkio.bfqX.weight or io.bfqX.weight): the weight of the
- group inside its parent. Available values: 1..10000 (default 100). The
- linear mapping between ioprio and weights, described at the beginning
- of the tunable section, is still valid, but all weights higher than
-diff --git a/block/Kconfig.iosched b/block/Kconfig.iosched
-index a4a8914bf7a4..299a6861fb90 100644
---- a/block/Kconfig.iosched
-+++ b/block/Kconfig.iosched
-@@ -40,6 +40,26 @@ config CFQ_GROUP_IOSCHED
- 	---help---
- 	  Enable group IO scheduling in CFQ.
- 
-+config IOSCHED_BFQ_SQ
-+	tristate "BFQ-SQ I/O scheduler"
-+	default n
-+	---help---
-+	The BFQ-SQ I/O scheduler (for legacy blk: SQ stands for
-+	SingleQueue) distributes bandwidth among all processes
-+	according to their weights, regardless of the device
-+	parameters and with any workload. It also guarantees a low
-+	latency to interactive and soft real-time applications.
-+	Details in Documentation/block/bfq-iosched.txt
-+
-+config BFQ_SQ_GROUP_IOSCHED
-+	bool "BFQ-SQ hierarchical scheduling support"
-+	depends on IOSCHED_BFQ_SQ && BLK_CGROUP
-+	default n
-+	---help---
-+
-+	Enable hierarchical scheduling in BFQ-SQ, using the blkio
-+	(cgroups-v1) or io (cgroups-v2) controller.
-+
- choice
- 
- 	prompt "Default I/O scheduler"
-@@ -54,6 +74,16 @@ choice
- 	config DEFAULT_CFQ
- 		bool "CFQ" if IOSCHED_CFQ=y
- 
-+	config DEFAULT_BFQ_SQ
-+		bool "BFQ-SQ" if IOSCHED_BFQ_SQ=y
-+		help
-+		  Selects BFQ-SQ as the default I/O scheduler which will be
-+		  used by default for all block devices.
-+		  The BFQ-SQ I/O scheduler aims at distributing the bandwidth
-+		  as desired, independently of the disk parameters and with
-+		  any workload. It also tries to guarantee low latency to
-+		  interactive and soft real-time applications.
-+
- 	config DEFAULT_NOOP
- 		bool "No-op"
- 
-@@ -63,8 +93,28 @@ config DEFAULT_IOSCHED
- 	string
- 	default "deadline" if DEFAULT_DEADLINE
- 	default "cfq" if DEFAULT_CFQ
-+	default "bfq-sq" if DEFAULT_BFQ_SQ
- 	default "noop" if DEFAULT_NOOP
- 
-+config MQ_IOSCHED_BFQ
-+	tristate "BFQ-MQ I/O Scheduler"
-+	default y
-+	---help---
-+	BFQ I/O scheduler for BLK-MQ. BFQ-MQ distributes bandwidth
-+	among all processes according to their weights, regardless of
-+	the device parameters and with any workload. It also
-+	guarantees a low latency to interactive and soft real-time
-+	applications.  Details in Documentation/block/bfq-iosched.txt
-+
-+config MQ_BFQ_GROUP_IOSCHED
-+	bool "BFQ-MQ hierarchical scheduling support"
-+	depends on MQ_IOSCHED_BFQ && BLK_CGROUP
-+	default n
-+	---help---
-+
-+	Enable hierarchical scheduling in BFQ-MQ, using the blkio
-+	(cgroups-v1) or io (cgroups-v2) controller.
-+
- config MQ_IOSCHED_DEADLINE
- 	tristate "MQ deadline I/O scheduler"
- 	default y
-diff --git a/block/Makefile b/block/Makefile
-index 6a56303b9925..a571329c23f0 100644
---- a/block/Makefile
-+++ b/block/Makefile
-@@ -24,6 +24,8 @@ obj-$(CONFIG_MQ_IOSCHED_DEADLINE)	+= mq-deadline.o
- obj-$(CONFIG_MQ_IOSCHED_KYBER)	+= kyber-iosched.o
- bfq-y				:= bfq-iosched.o bfq-wf2q.o bfq-cgroup.o
- obj-$(CONFIG_IOSCHED_BFQ)	+= bfq.o
-+obj-$(CONFIG_IOSCHED_BFQ_SQ)	+= bfq-sq-iosched.o
-+obj-$(CONFIG_MQ_IOSCHED_BFQ)	+= bfq-mq-iosched.o
- 
- obj-$(CONFIG_BLOCK_COMPAT)	+= compat_ioctl.o
- obj-$(CONFIG_BLK_CMDLINE_PARSER)	+= cmdline-parser.o
-diff --git a/block/bfq-cgroup-included.c b/block/bfq-cgroup-included.c
-new file mode 100644
-index 000000000000..613f154e9da5
---- /dev/null
-+++ b/block/bfq-cgroup-included.c
-@@ -0,0 +1,1354 @@
-+/*
-+ * BFQ: CGROUPS support.
-+ *
-+ * Based on ideas and code from CFQ:
-+ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
-+ *
-+ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
-+ *		      Paolo Valente <paolo.valente@unimore.it>
-+ *
-+ * Copyright (C) 2015 Paolo Valente <paolo.valente@unimore.it>
-+ *
-+ * Copyright (C) 2016 Paolo Valente <paolo.valente@linaro.org>
-+ *
-+ * Licensed under the GPL-2 as detailed in the accompanying COPYING.BFQ
-+ * file.
-+ */
-+
-+#if defined(BFQ_GROUP_IOSCHED_ENABLED) && defined(CONFIG_DEBUG_BLK_CGROUP)
-+
-+/* bfqg stats flags */
-+enum bfqg_stats_flags {
-+	BFQG_stats_waiting = 0,
-+	BFQG_stats_idling,
-+	BFQG_stats_empty,
-+};
-+
-+#define BFQG_FLAG_FNS(name)						\
-+static void bfqg_stats_mark_##name(struct bfqg_stats *stats)	\
-+{									\
-+	stats->flags |= (1 << BFQG_stats_##name);			\
-+}									\
-+static void bfqg_stats_clear_##name(struct bfqg_stats *stats)	\
-+{									\
-+	stats->flags &= ~(1 << BFQG_stats_##name);			\
-+}									\
-+static int bfqg_stats_##name(struct bfqg_stats *stats)		\
-+{									\
-+	return (stats->flags & (1 << BFQG_stats_##name)) != 0;		\
-+}									\
-+
-+BFQG_FLAG_FNS(waiting)
-+BFQG_FLAG_FNS(idling)
-+BFQG_FLAG_FNS(empty)
-+#undef BFQG_FLAG_FNS
-+
-+#ifdef BFQ_MQ
-+/* This should be called with the scheduler lock held. */
-+#else
-+/* This should be called with the queue_lock held. */
-+#endif
-+static void bfqg_stats_update_group_wait_time(struct bfqg_stats *stats)
-+{
-+	unsigned long long now;
-+
-+	if (!bfqg_stats_waiting(stats))
-+		return;
-+
-+	now = sched_clock();
-+	if (time_after64(now, stats->start_group_wait_time))
-+		blkg_stat_add(&stats->group_wait_time,
-+			      now - stats->start_group_wait_time);
-+	bfqg_stats_clear_waiting(stats);
-+}
-+
-+#ifdef BFQ_MQ
-+/* This should be called with the scheduler lock held. */
-+#else
-+/* This should be called with the queue_lock held. */
-+#endif
-+static void bfqg_stats_set_start_group_wait_time(struct bfq_group *bfqg,
-+						 struct bfq_group *curr_bfqg)
-+{
-+	struct bfqg_stats *stats = &bfqg->stats;
-+
-+	if (bfqg_stats_waiting(stats))
-+		return;
-+	if (bfqg == curr_bfqg)
-+		return;
-+	stats->start_group_wait_time = sched_clock();
-+	bfqg_stats_mark_waiting(stats);
-+}
-+
-+#ifdef BFQ_MQ
-+/* This should be called with the scheduler lock held. */
-+#else
-+/* This should be called with the queue_lock held. */
-+#endif
-+static void bfqg_stats_end_empty_time(struct bfqg_stats *stats)
-+{
-+	unsigned long long now;
-+
-+	if (!bfqg_stats_empty(stats))
-+		return;
-+
-+	now = sched_clock();
-+	if (time_after64(now, stats->start_empty_time))
-+		blkg_stat_add(&stats->empty_time,
-+			      now - stats->start_empty_time);
-+	bfqg_stats_clear_empty(stats);
-+}
-+
-+static void bfqg_stats_update_dequeue(struct bfq_group *bfqg)
-+{
-+	blkg_stat_add(&bfqg->stats.dequeue, 1);
-+}
-+
-+static void bfqg_stats_set_start_empty_time(struct bfq_group *bfqg)
-+{
-+	struct bfqg_stats *stats = &bfqg->stats;
-+
-+	if (blkg_rwstat_total(&stats->queued))
-+		return;
-+
-+	/*
-+	 * group is already marked empty. This can happen if bfqq got new
-+	 * request in parent group and moved to this group while being added
-+	 * to service tree. Just ignore the event and move on.
-+	 */
-+	if (bfqg_stats_empty(stats))
-+		return;
-+
-+	stats->start_empty_time = sched_clock();
-+	bfqg_stats_mark_empty(stats);
-+}
-+
-+static void bfqg_stats_update_idle_time(struct bfq_group *bfqg)
-+{
-+	struct bfqg_stats *stats = &bfqg->stats;
-+
-+	if (bfqg_stats_idling(stats)) {
-+		unsigned long long now = sched_clock();
-+
-+		if (time_after64(now, stats->start_idle_time))
-+			blkg_stat_add(&stats->idle_time,
-+				      now - stats->start_idle_time);
-+		bfqg_stats_clear_idling(stats);
-+	}
-+}
-+
-+static void bfqg_stats_set_start_idle_time(struct bfq_group *bfqg)
-+{
-+	struct bfqg_stats *stats = &bfqg->stats;
-+
-+	stats->start_idle_time = sched_clock();
-+	bfqg_stats_mark_idling(stats);
-+}
-+
-+static void bfqg_stats_update_avg_queue_size(struct bfq_group *bfqg)
-+{
-+	struct bfqg_stats *stats = &bfqg->stats;
-+
-+	blkg_stat_add(&stats->avg_queue_size_sum,
-+		      blkg_rwstat_total(&stats->queued));
-+	blkg_stat_add(&stats->avg_queue_size_samples, 1);
-+	bfqg_stats_update_group_wait_time(stats);
-+}
-+
-+static void bfqg_stats_update_io_add(struct bfq_group *bfqg,
-+				struct bfq_queue *bfqq, unsigned int op)
-+{
-+	blkg_rwstat_add(&bfqg->stats.queued, op, 1);
-+	bfqg_stats_end_empty_time(&bfqg->stats);
-+	if (!(bfqq == ((struct bfq_data *)bfqg->bfqd)->in_service_queue))
-+		bfqg_stats_set_start_group_wait_time(bfqg, bfqq_group(bfqq));
-+}
-+
-+static void bfqg_stats_update_io_remove(struct bfq_group *bfqg, unsigned int op)
-+{
-+	blkg_rwstat_add(&bfqg->stats.queued, op, -1);
-+}
-+
-+static void bfqg_stats_update_io_merged(struct bfq_group *bfqg, unsigned int op)
-+{
-+	blkg_rwstat_add(&bfqg->stats.merged, op, 1);
-+}
-+
-+static void bfqg_stats_update_completion(struct bfq_group *bfqg,
-+		uint64_t start_time, uint64_t io_start_time, unsigned int op)
-+{
-+	struct bfqg_stats *stats = &bfqg->stats;
-+	unsigned long long now = sched_clock();
-+
-+	if (time_after64(now, io_start_time))
-+		blkg_rwstat_add(&stats->service_time, op,
-+				now - io_start_time);
-+	if (time_after64(io_start_time, start_time))
-+		blkg_rwstat_add(&stats->wait_time, op,
-+				io_start_time - start_time);
-+}
-+
-+#else /* BFQ_GROUP_IOSCHED_ENABLED && CONFIG_DEBUG_BLK_CGROUP */
-+
-+static inline void bfqg_stats_update_io_add(struct bfq_group *bfqg,
-+			struct bfq_queue *bfqq, unsigned int op) { }
-+static inline void
-+bfqg_stats_update_io_remove(struct bfq_group *bfqg, unsigned int op) { }
-+static inline void
-+bfqg_stats_update_io_merged(struct bfq_group *bfqg, unsigned int op) { }
-+static inline void bfqg_stats_update_completion(struct bfq_group *bfqg,
-+		uint64_t start_time, uint64_t io_start_time,
-+		unsigned int op) { }
-+static inline void
-+bfqg_stats_set_start_group_wait_time(struct bfq_group *bfqg,
-+		struct bfq_group *curr_bfqg) { }
-+static inline void bfqg_stats_end_empty_time(struct bfqg_stats *stats) { }
-+static inline void bfqg_stats_update_dequeue(struct bfq_group *bfqg) { }
-+static inline void bfqg_stats_set_start_empty_time(struct bfq_group *bfqg) { }
-+static inline void bfqg_stats_update_idle_time(struct bfq_group *bfqg) { }
-+static inline void bfqg_stats_set_start_idle_time(struct bfq_group *bfqg) { }
-+static inline void bfqg_stats_update_avg_queue_size(struct bfq_group *bfqg) { }
-+
-+#endif /* BFQ_GROUP_IOSCHED_ENABLED && CONFIG_DEBUG_BLK_CGROUP */
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+static struct blkcg_policy blkcg_policy_bfq;
-+
-+/*
-+ * blk-cgroup policy-related handlers
-+ * The following functions help in converting between blk-cgroup
-+ * internal structures and BFQ-specific structures.
-+ */
-+
-+static struct bfq_group *pd_to_bfqg(struct blkg_policy_data *pd)
-+{
-+	return pd ? container_of(pd, struct bfq_group, pd) : NULL;
-+}
-+
-+static struct blkcg_gq *bfqg_to_blkg(struct bfq_group *bfqg)
-+{
-+	return pd_to_blkg(&bfqg->pd);
-+}
-+
-+static struct bfq_group *blkg_to_bfqg(struct blkcg_gq *blkg)
-+{
-+	struct blkg_policy_data *pd = blkg_to_pd(blkg, &blkcg_policy_bfq);
-+
-+	return pd_to_bfqg(pd);
-+}
-+
-+/*
-+ * bfq_group handlers
-+ * The following functions help in navigating the bfq_group hierarchy
-+ * by allowing to find the parent of a bfq_group or the bfq_group
-+ * associated to a bfq_queue.
-+ */
-+
-+static struct bfq_group *bfqg_parent(struct bfq_group *bfqg)
-+{
-+	struct blkcg_gq *pblkg = bfqg_to_blkg(bfqg)->parent;
-+
-+	return pblkg ? blkg_to_bfqg(pblkg) : NULL;
-+}
-+
-+static struct bfq_group *bfqq_group(struct bfq_queue *bfqq)
-+{
-+	struct bfq_entity *group_entity = bfqq->entity.parent;
-+
-+	return group_entity ? container_of(group_entity, struct bfq_group,
-+					   entity) :
-+			      bfqq->bfqd->root_group;
-+}
-+
-+/*
-+ * The following two functions handle get and put of a bfq_group by
-+ * wrapping the related blk-cgroup hooks.
-+ */
-+
-+static void bfqg_get(struct bfq_group *bfqg)
-+{
-+#ifdef BFQ_MQ
-+	bfqg->ref++;
-+#else
-+	blkg_get(bfqg_to_blkg(bfqg));
-+#endif
-+}
-+
-+static void bfqg_put(struct bfq_group *bfqg)
-+{
-+#ifdef BFQ_MQ
-+	bfqg->ref--;
-+
-+	BUG_ON(bfqg->ref < 0);
-+	if (bfqg->ref == 0)
-+		kfree(bfqg);
-+#else
-+	blkg_put(bfqg_to_blkg(bfqg));
-+#endif
-+}
-+
-+#ifdef BFQ_MQ
-+static void bfqg_and_blkg_get(struct bfq_group *bfqg)
-+{
-+	/* see comments in bfq_bic_update_cgroup for why refcounting bfqg */
-+	bfqg_get(bfqg);
-+
-+	blkg_get(bfqg_to_blkg(bfqg));
-+}
-+
-+static void bfqg_and_blkg_put(struct bfq_group *bfqg)
-+{
-+	bfqg_put(bfqg);
-+
-+	blkg_put(bfqg_to_blkg(bfqg));
-+}
-+#endif
-+
-+/* @stats = 0 */
-+static void bfqg_stats_reset(struct bfqg_stats *stats)
-+{
-+#ifdef CONFIG_DEBUG_BLK_CGROUP
-+	/* queued stats shouldn't be cleared */
-+	blkg_rwstat_reset(&stats->merged);
-+	blkg_rwstat_reset(&stats->service_time);
-+	blkg_rwstat_reset(&stats->wait_time);
-+	blkg_stat_reset(&stats->time);
-+	blkg_stat_reset(&stats->avg_queue_size_sum);
-+	blkg_stat_reset(&stats->avg_queue_size_samples);
-+	blkg_stat_reset(&stats->dequeue);
-+	blkg_stat_reset(&stats->group_wait_time);
-+	blkg_stat_reset(&stats->idle_time);
-+	blkg_stat_reset(&stats->empty_time);
-+#endif
-+}
-+
-+/* @to += @from */
-+static void bfqg_stats_add_aux(struct bfqg_stats *to, struct bfqg_stats *from)
-+{
-+	if (!to || !from)
-+		return;
-+
-+#ifdef CONFIG_DEBUG_BLK_CGROUP
-+	/* queued stats shouldn't be cleared */
-+	blkg_rwstat_add_aux(&to->merged, &from->merged);
-+	blkg_rwstat_add_aux(&to->service_time, &from->service_time);
-+	blkg_rwstat_add_aux(&to->wait_time, &from->wait_time);
-+	blkg_stat_add_aux(&from->time, &from->time);
-+	blkg_stat_add_aux(&to->avg_queue_size_sum, &from->avg_queue_size_sum);
-+	blkg_stat_add_aux(&to->avg_queue_size_samples,
-+			  &from->avg_queue_size_samples);
-+	blkg_stat_add_aux(&to->dequeue, &from->dequeue);
-+	blkg_stat_add_aux(&to->group_wait_time, &from->group_wait_time);
-+	blkg_stat_add_aux(&to->idle_time, &from->idle_time);
-+	blkg_stat_add_aux(&to->empty_time, &from->empty_time);
-+#endif
-+}
-+
-+/*
-+ * Transfer @bfqg's stats to its parent's dead_stats so that the ancestors'
-+ * recursive stats can still account for the amount used by this bfqg after
-+ * it's gone.
-+ */
-+static void bfqg_stats_xfer_dead(struct bfq_group *bfqg)
-+{
-+	struct bfq_group *parent;
-+
-+	if (!bfqg) /* root_group */
-+		return;
-+
-+	parent = bfqg_parent(bfqg);
-+
-+	lockdep_assert_held(bfqg_to_blkg(bfqg)->q->queue_lock);
-+
-+	if (unlikely(!parent))
-+		return;
-+
-+	bfqg_stats_add_aux(&parent->stats, &bfqg->stats);
-+	bfqg_stats_reset(&bfqg->stats);
-+}
-+
-+static void bfq_init_entity(struct bfq_entity *entity,
-+			    struct bfq_group *bfqg)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+
-+	entity->weight = entity->new_weight;
-+	entity->orig_weight = entity->new_weight;
-+	if (bfqq) {
-+		bfqq->ioprio = bfqq->new_ioprio;
-+		bfqq->ioprio_class = bfqq->new_ioprio_class;
-+#ifdef BFQ_MQ
-+		/*
-+		 * Make sure that bfqg and its associated blkg do not
-+		 * disappear before entity.
-+		 */
-+		bfq_log_bfqq(bfqq->bfqd, bfqq, "getting bfqg %p and blkg\n",
-+		bfqg);
-+
-+		bfqg_and_blkg_get(bfqg);
-+#else
-+		bfqg_get(bfqg);
-+#endif
-+	}
-+	entity->parent = bfqg->my_entity; /* NULL for root group */
-+	entity->sched_data = &bfqg->sched_data;
-+}
-+
-+static void bfqg_stats_exit(struct bfqg_stats *stats)
-+{
-+#ifdef CONFIG_DEBUG_BLK_CGROUP
-+	blkg_rwstat_exit(&stats->merged);
-+	blkg_rwstat_exit(&stats->service_time);
-+	blkg_rwstat_exit(&stats->wait_time);
-+	blkg_rwstat_exit(&stats->queued);
-+	blkg_stat_exit(&stats->time);
-+	blkg_stat_exit(&stats->avg_queue_size_sum);
-+	blkg_stat_exit(&stats->avg_queue_size_samples);
-+	blkg_stat_exit(&stats->dequeue);
-+	blkg_stat_exit(&stats->group_wait_time);
-+	blkg_stat_exit(&stats->idle_time);
-+	blkg_stat_exit(&stats->empty_time);
-+#endif
-+}
-+
-+static int bfqg_stats_init(struct bfqg_stats *stats, gfp_t gfp)
-+{
-+#ifdef CONFIG_DEBUG_BLK_CGROUP
-+	if (blkg_rwstat_init(&stats->merged, gfp) ||
-+	    blkg_rwstat_init(&stats->service_time, gfp) ||
-+	    blkg_rwstat_init(&stats->wait_time, gfp) ||
-+	    blkg_rwstat_init(&stats->queued, gfp) ||
-+	    blkg_stat_init(&stats->time, gfp) ||
-+	    blkg_stat_init(&stats->avg_queue_size_sum, gfp) ||
-+	    blkg_stat_init(&stats->avg_queue_size_samples, gfp) ||
-+	    blkg_stat_init(&stats->dequeue, gfp) ||
-+	    blkg_stat_init(&stats->group_wait_time, gfp) ||
-+	    blkg_stat_init(&stats->idle_time, gfp) ||
-+	    blkg_stat_init(&stats->empty_time, gfp)) {
-+		bfqg_stats_exit(stats);
-+		return -ENOMEM;
-+	}
-+#endif
-+
-+	return 0;
-+}
-+
-+static struct bfq_group_data *cpd_to_bfqgd(struct blkcg_policy_data *cpd)
-+{
-+	return cpd ? container_of(cpd, struct bfq_group_data, pd) : NULL;
-+}
-+
-+static struct bfq_group_data *blkcg_to_bfqgd(struct blkcg *blkcg)
-+{
-+	return cpd_to_bfqgd(blkcg_to_cpd(blkcg, &blkcg_policy_bfq));
-+}
-+
-+static struct blkcg_policy_data *bfq_cpd_alloc(gfp_t gfp)
-+{
-+	struct bfq_group_data *bgd;
-+
-+	bgd = kzalloc(sizeof(*bgd), gfp);
-+	if (!bgd)
-+		return NULL;
-+	return &bgd->pd;
-+}
-+
-+static void bfq_cpd_init(struct blkcg_policy_data *cpd)
-+{
-+	struct bfq_group_data *d = cpd_to_bfqgd(cpd);
-+
-+	d->weight = cgroup_subsys_on_dfl(io_cgrp_subsys) ?
-+		CGROUP_WEIGHT_DFL : BFQ_WEIGHT_LEGACY_DFL;
-+}
-+
-+static void bfq_cpd_free(struct blkcg_policy_data *cpd)
-+{
-+	kfree(cpd_to_bfqgd(cpd));
-+}
-+
-+static struct blkg_policy_data *bfq_pd_alloc(gfp_t gfp, int node)
-+{
-+	struct bfq_group *bfqg;
-+
-+	bfqg = kzalloc_node(sizeof(*bfqg), gfp, node);
-+	if (!bfqg)
-+		return NULL;
-+
-+	if (bfqg_stats_init(&bfqg->stats, gfp)) {
-+		kfree(bfqg);
-+		return NULL;
-+	}
-+#ifdef BFQ_MQ
-+	/* see comments in bfq_bic_update_cgroup for why refcounting */
-+	bfqg_get(bfqg);
-+#endif
-+	return &bfqg->pd;
-+}
-+
-+static void bfq_pd_init(struct blkg_policy_data *pd)
-+{
-+	struct blkcg_gq *blkg;
-+	struct bfq_group *bfqg;
-+	struct bfq_data *bfqd;
-+	struct bfq_entity *entity;
-+	struct bfq_group_data *d;
-+
-+	blkg = pd_to_blkg(pd);
-+	BUG_ON(!blkg);
-+	bfqg = blkg_to_bfqg(blkg);
-+	bfqd = blkg->q->elevator->elevator_data;
-+	BUG_ON(bfqg == bfqd->root_group);
-+	entity = &bfqg->entity;
-+	d = blkcg_to_bfqgd(blkg->blkcg);
-+
-+	entity->orig_weight = entity->weight = entity->new_weight = d->weight;
-+	entity->my_sched_data = &bfqg->sched_data;
-+	bfqg->my_entity = entity; /*
-+				   * the root_group's will be set to NULL
-+				   * in bfq_init_queue()
-+				   */
-+	bfqg->bfqd = bfqd;
-+	bfqg->active_entities = 0;
-+	bfqg->rq_pos_tree = RB_ROOT;
-+}
-+
-+static void bfq_pd_free(struct blkg_policy_data *pd)
-+{
-+	struct bfq_group *bfqg = pd_to_bfqg(pd);
-+
-+	bfqg_stats_exit(&bfqg->stats);
-+#ifdef BFQ_MQ
-+	bfqg_put(bfqg);
-+#else
-+	kfree(bfqg);
-+#endif
-+}
-+
-+static void bfq_pd_reset_stats(struct blkg_policy_data *pd)
-+{
-+	struct bfq_group *bfqg = pd_to_bfqg(pd);
-+
-+	bfqg_stats_reset(&bfqg->stats);
-+}
-+
-+static void bfq_group_set_parent(struct bfq_group *bfqg,
-+					struct bfq_group *parent)
-+{
-+	struct bfq_entity *entity;
-+
-+	BUG_ON(!parent);
-+	BUG_ON(!bfqg);
-+	BUG_ON(bfqg == parent);
-+
-+	entity = &bfqg->entity;
-+	entity->parent = parent->my_entity;
-+	entity->sched_data = &parent->sched_data;
-+}
-+
-+static struct bfq_group *bfq_lookup_bfqg(struct bfq_data *bfqd,
-+					 struct blkcg *blkcg)
-+{
-+	struct blkcg_gq *blkg;
-+
-+	blkg = blkg_lookup(blkcg, bfqd->queue);
-+	if (likely(blkg))
-+		return blkg_to_bfqg(blkg);
-+	return NULL;
-+}
-+
-+static struct bfq_group *bfq_find_set_group(struct bfq_data *bfqd,
-+					    struct blkcg *blkcg)
-+{
-+	struct bfq_group *bfqg, *parent;
-+	struct bfq_entity *entity;
-+
-+	bfqg = bfq_lookup_bfqg(bfqd, blkcg);
-+
-+	if (unlikely(!bfqg))
-+		return NULL;
-+
-+	/*
-+	 * Update chain of bfq_groups as we might be handling a leaf group
-+	 * which, along with some of its relatives, has not been hooked yet
-+	 * to the private hierarchy of BFQ.
-+	 */
-+	entity = &bfqg->entity;
-+	for_each_entity(entity) {
-+		bfqg = container_of(entity, struct bfq_group, entity);
-+		BUG_ON(!bfqg);
-+		if (bfqg != bfqd->root_group) {
-+			parent = bfqg_parent(bfqg);
-+			if (!parent)
-+				parent = bfqd->root_group;
-+			BUG_ON(!parent);
-+			bfq_group_set_parent(bfqg, parent);
-+		}
-+	}
-+
-+	return bfqg;
-+}
-+
-+static void bfq_pos_tree_add_move(struct bfq_data *bfqd,
-+				  struct bfq_queue *bfqq);
-+
-+static void bfq_bfqq_expire(struct bfq_data *bfqd,
-+			    struct bfq_queue *bfqq,
-+			    bool compensate,
-+			    enum bfqq_expiration reason);
-+
-+/**
-+ * bfq_bfqq_move - migrate @bfqq to @bfqg.
-+ * @bfqd: queue descriptor.
-+ * @bfqq: the queue to move.
-+ * @bfqg: the group to move to.
-+ *
-+ * Move @bfqq to @bfqg, deactivating it from its old group and reactivating
-+ * it on the new one.  Avoid putting the entity on the old group idle tree.
-+ *
-+#ifdef BFQ_MQ
-+ * Must be called under the scheduler lock, to make sure that the blkg
-+ * owning @bfqg does not disappear (see comments in
-+ * bfq_bic_update_cgroup on guaranteeing the consistency of blkg
-+ * objects).
-+#else
-+ * Must be called under the queue lock; the cgroup owning @bfqg must
-+ * not disappear (by now this just means that we are called under
-+ * rcu_read_lock()).
-+#endif
-+ */
-+static void bfq_bfqq_move(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+			  struct bfq_group *bfqg)
-+{
-+	struct bfq_entity *entity = &bfqq->entity;
-+
-+	BUG_ON(!bfq_bfqq_busy(bfqq) && !RB_EMPTY_ROOT(&bfqq->sort_list));
-+	BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list) && !entity->on_st);
-+	BUG_ON(bfq_bfqq_busy(bfqq) && RB_EMPTY_ROOT(&bfqq->sort_list)
-+	       && entity->on_st &&
-+	       bfqq != bfqd->in_service_queue);
-+	BUG_ON(!bfq_bfqq_busy(bfqq) && bfqq == bfqd->in_service_queue);
-+
-+	/* If bfqq is empty, then bfq_bfqq_expire also invokes
-+	 * bfq_del_bfqq_busy, thereby removing bfqq and its entity
-+	 * from data structures related to current group. Otherwise we
-+	 * need to remove bfqq explicitly with bfq_deactivate_bfqq, as
-+	 * we do below.
-+	 */
-+	if (bfqq == bfqd->in_service_queue)
-+		bfq_bfqq_expire(bfqd, bfqd->in_service_queue,
-+				false, BFQ_BFQQ_PREEMPTED);
-+
-+	BUG_ON(entity->on_st && !bfq_bfqq_busy(bfqq)
-+	    && &bfq_entity_service_tree(entity)->idle !=
-+	       entity->tree);
-+
-+	BUG_ON(RB_EMPTY_ROOT(&bfqq->sort_list) && bfq_bfqq_busy(bfqq));
-+
-+	if (bfq_bfqq_busy(bfqq))
-+		bfq_deactivate_bfqq(bfqd, bfqq, false, false);
-+	else if (entity->on_st) {
-+		BUG_ON(&bfq_entity_service_tree(entity)->idle !=
-+		       entity->tree);
-+		bfq_put_idle_entity(bfq_entity_service_tree(entity), entity);
-+	}
-+#ifdef BFQ_MQ
-+	bfq_log_bfqq(bfqq->bfqd, bfqq, "putting blkg and bfqg %p\n", bfqg);
-+
-+	bfqg_and_blkg_put(bfqq_group(bfqq));
-+#else
-+	bfqg_put(bfqq_group(bfqq));
-+#endif
-+
-+	entity->parent = bfqg->my_entity;
-+	entity->sched_data = &bfqg->sched_data;
-+#ifdef BFQ_MQ
-+	bfq_log_bfqq(bfqq->bfqd, bfqq, "getting blkg and bfqg %p\n", bfqg);
-+
-+	/* pin down bfqg and its associated blkg  */
-+	bfqg_and_blkg_get(bfqg);
-+#else
-+	bfqg_get(bfqg);
-+#endif
-+
-+	BUG_ON(RB_EMPTY_ROOT(&bfqq->sort_list) && bfq_bfqq_busy(bfqq));
-+	if (bfq_bfqq_busy(bfqq)) {
-+		bfq_pos_tree_add_move(bfqd, bfqq);
-+		bfq_activate_bfqq(bfqd, bfqq);
-+	}
-+
-+	if (!bfqd->in_service_queue && !bfqd->rq_in_driver)
-+		bfq_schedule_dispatch(bfqd);
-+	BUG_ON(entity->on_st && !bfq_bfqq_busy(bfqq)
-+	       && &bfq_entity_service_tree(entity)->idle !=
-+	       entity->tree);
-+}
-+
-+/**
-+ * __bfq_bic_change_cgroup - move @bic to @cgroup.
-+ * @bfqd: the queue descriptor.
-+ * @bic: the bic to move.
-+ * @blkcg: the blk-cgroup to move to.
-+ *
-+#ifdef BFQ_MQ
-+ * Move bic to blkcg, assuming that bfqd->lock is held; which makes
-+ * sure that the reference to cgroup is valid across the call (see
-+ * comments in bfq_bic_update_cgroup on this issue)
-+#else
-+ * Move bic to blkcg, assuming that bfqd->queue is locked; the caller
-+ * has to make sure that the reference to cgroup is valid across the call.
-+#endif
-+ *
-+ * NOTE: an alternative approach might have been to store the current
-+ * cgroup in bfqq and getting a reference to it, reducing the lookup
-+ * time here, at the price of slightly more complex code.
-+ */
-+static struct bfq_group *__bfq_bic_change_cgroup(struct bfq_data *bfqd,
-+						struct bfq_io_cq *bic,
-+						struct blkcg *blkcg)
-+{
-+	struct bfq_queue *async_bfqq = bic_to_bfqq(bic, 0);
-+	struct bfq_queue *sync_bfqq = bic_to_bfqq(bic, 1);
-+	struct bfq_group *bfqg;
-+	struct bfq_entity *entity;
-+
-+	bfqg = bfq_find_set_group(bfqd, blkcg);
-+
-+	if (unlikely(!bfqg))
-+		bfqg = bfqd->root_group;
-+
-+	if (async_bfqq) {
-+		entity = &async_bfqq->entity;
-+
-+		if (entity->sched_data != &bfqg->sched_data) {
-+			bic_set_bfqq(bic, NULL, 0);
-+			bfq_log_bfqq(bfqd, async_bfqq,
-+				     "%p %d",
-+				     async_bfqq,
-+				     async_bfqq->ref);
-+			bfq_put_queue(async_bfqq);
-+		}
-+	}
-+
-+	if (sync_bfqq) {
-+		entity = &sync_bfqq->entity;
-+		if (entity->sched_data != &bfqg->sched_data)
-+			bfq_bfqq_move(bfqd, sync_bfqq, bfqg);
-+	}
-+
-+	return bfqg;
-+}
-+
-+static void bfq_bic_update_cgroup(struct bfq_io_cq *bic, struct bio *bio)
-+{
-+	struct bfq_data *bfqd = bic_to_bfqd(bic);
-+	struct bfq_group *bfqg = NULL;
-+	uint64_t serial_nr;
-+
-+	rcu_read_lock();
-+	serial_nr = bio_blkcg(bio)->css.serial_nr;
-+
-+	/*
-+	 * Check whether blkcg has changed.  The condition may trigger
-+	 * spuriously on a newly created cic but there's no harm.
-+	 */
-+	if (unlikely(!bfqd) || likely(bic->blkcg_serial_nr == serial_nr))
-+		goto out;
-+
-+	bfqg = __bfq_bic_change_cgroup(bfqd, bic, bio_blkcg(bio));
-+#ifdef BFQ_MQ
-+	/*
-+	 * Update blkg_path for bfq_log_* functions. We cache this
-+	 * path, and update it here, for the following
-+	 * reasons. Operations on blkg objects in blk-cgroup are
-+	 * protected with the request_queue lock, and not with the
-+	 * lock that protects the instances of this scheduler
-+	 * (bfqd->lock). This exposes BFQ to the following sort of
-+	 * race.
-+	 *
-+	 * The blkg_lookup performed in bfq_get_queue, protected
-+	 * through rcu, may happen to return the address of a copy of
-+	 * the original blkg. If this is the case, then the
-+	 * bfqg_and_blkg_get performed in bfq_get_queue, to pin down
-+	 * the blkg, is useless: it does not prevent blk-cgroup code
-+	 * from destroying both the original blkg and all objects
-+	 * directly or indirectly referred by the copy of the
-+	 * blkg.
-+	 *
-+	 * On the bright side, destroy operations on a blkg invoke, as
-+	 * a first step, hooks of the scheduler associated with the
-+	 * blkg. And these hooks are executed with bfqd->lock held for
-+	 * BFQ. As a consequence, for any blkg associated with the
-+	 * request queue this instance of the scheduler is attached
-+	 * to, we are guaranteed that such a blkg is not destroyed, and
-+	 * that all the pointers it contains are consistent, while we
-+	 * are holding bfqd->lock. A blkg_lookup performed with
-+	 * bfqd->lock held then returns a fully consistent blkg, which
-+	 * remains consistent until this lock is held.
-+	 *
-+	 * Thanks to the last fact, and to the fact that: (1) bfqg has
-+	 * been obtained through a blkg_lookup in the above
-+	 * assignment, and (2) bfqd->lock is being held, here we can
-+	 * safely use the policy data for the involved blkg (i.e., the
-+	 * field bfqg->pd) to get to the blkg associated with bfqg,
-+	 * and then we can safely use any field of blkg. After we
-+	 * release bfqd->lock, even just getting blkg through this
-+	 * bfqg may cause dangling references to be traversed, as
-+	 * bfqg->pd may not exist any more.
-+	 *
-+	 * In view of the above facts, here we cache, in the bfqg, any
-+	 * blkg data we may need for this bic, and for its associated
-+	 * bfq_queue. As of now, we need to cache only the path of the
-+	 * blkg, which is used in the bfq_log_* functions.
-+	 *
-+	 * Finally, note that bfqg itself needs to be protected from
-+	 * destruction on the blkg_free of the original blkg (which
-+	 * invokes bfq_pd_free). We use an additional private
-+	 * refcounter for bfqg, to let it disappear only after no
-+	 * bfq_queue refers to it any longer.
-+	 */
-+	blkg_path(bfqg_to_blkg(bfqg), bfqg->blkg_path, sizeof(bfqg->blkg_path));
-+#endif
-+	bic->blkcg_serial_nr = serial_nr;
-+out:
-+	rcu_read_unlock();
-+}
-+
-+/**
-+ * bfq_flush_idle_tree - deactivate any entity on the idle tree of @st.
-+ * @st: the service tree being flushed.
-+ */
-+static void bfq_flush_idle_tree(struct bfq_service_tree *st)
-+{
-+	struct bfq_entity *entity = st->first_idle;
-+
-+	for (; entity ; entity = st->first_idle)
-+		__bfq_deactivate_entity(entity, false);
-+}
-+
-+/**
-+ * bfq_reparent_leaf_entity - move leaf entity to the root_group.
-+ * @bfqd: the device data structure with the root group.
-+ * @entity: the entity to move.
-+ */
-+static void bfq_reparent_leaf_entity(struct bfq_data *bfqd,
-+				     struct bfq_entity *entity)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+
-+	BUG_ON(!bfqq);
-+	bfq_bfqq_move(bfqd, bfqq, bfqd->root_group);
-+}
-+
-+/**
-+ * bfq_reparent_active_entities - move to the root group all active
-+ *                                entities.
-+ * @bfqd: the device data structure with the root group.
-+ * @bfqg: the group to move from.
-+ * @st: the service tree with the entities.
-+ */
-+static void bfq_reparent_active_entities(struct bfq_data *bfqd,
-+					 struct bfq_group *bfqg,
-+					 struct bfq_service_tree *st)
-+{
-+	struct rb_root *active = &st->active;
-+	struct bfq_entity *entity = NULL;
-+
-+	if (!RB_EMPTY_ROOT(&st->active))
-+		entity = bfq_entity_of(rb_first(active));
-+
-+	for (; entity ; entity = bfq_entity_of(rb_first(active)))
-+		bfq_reparent_leaf_entity(bfqd, entity);
-+
-+	if (bfqg->sched_data.in_service_entity)
-+		bfq_reparent_leaf_entity(bfqd,
-+			bfqg->sched_data.in_service_entity);
-+}
-+
-+/**
-+ * bfq_pd_offline - deactivate the entity associated with @pd,
-+ *		    and reparent its children entities.
-+ * @pd: descriptor of the policy going offline.
-+ *
-+ * blkio already grabs the queue_lock for us, so no need to use
-+ * RCU-based magic
-+ */
-+static void bfq_pd_offline(struct blkg_policy_data *pd)
-+{
-+	struct bfq_service_tree *st;
-+	struct bfq_group *bfqg;
-+	struct bfq_data *bfqd;
-+	struct bfq_entity *entity;
-+#ifdef BFQ_MQ
-+	unsigned long flags;
-+#endif
-+	int i;
-+
-+	BUG_ON(!pd);
-+	bfqg = pd_to_bfqg(pd);
-+	BUG_ON(!bfqg);
-+	bfqd = bfqg->bfqd;
-+	BUG_ON(bfqd && !bfqd->root_group);
-+
-+	entity = bfqg->my_entity;
-+
-+#ifdef BFQ_MQ
-+	spin_lock_irqsave(&bfqd->lock, flags);
-+#endif
-+
-+	if (!entity) /* root group */
-+		goto put_async_queues;
-+
-+	/*
-+	 * Empty all service_trees belonging to this group before
-+	 * deactivating the group itself.
-+	 */
-+	for (i = 0; i < BFQ_IOPRIO_CLASSES; i++) {
-+		BUG_ON(!bfqg->sched_data.service_tree);
-+		st = bfqg->sched_data.service_tree + i;
-+		/*
-+		 * The idle tree may still contain bfq_queues belonging
-+		 * to exited task because they never migrated to a different
-+		 * cgroup from the one being destroyed now.
-+		 */
-+		bfq_flush_idle_tree(st);
-+
-+		/*
-+		 * It may happen that some queues are still active
-+		 * (busy) upon group destruction (if the corresponding
-+		 * processes have been forced to terminate). We move
-+		 * all the leaf entities corresponding to these queues
-+		 * to the root_group.
-+		 * Also, it may happen that the group has an entity
-+		 * in service, which is disconnected from the active
-+		 * tree: it must be moved, too.
-+		 * There is no need to put the sync queues, as the
-+		 * scheduler has taken no reference.
-+		 */
-+		bfq_reparent_active_entities(bfqd, bfqg, st);
-+		BUG_ON(!RB_EMPTY_ROOT(&st->active));
-+		BUG_ON(!RB_EMPTY_ROOT(&st->idle));
-+	}
-+	BUG_ON(bfqg->sched_data.next_in_service);
-+	BUG_ON(bfqg->sched_data.in_service_entity);
-+
-+	__bfq_deactivate_entity(entity, false);
-+
-+put_async_queues:
-+	bfq_put_async_queues(bfqd, bfqg);
-+
-+#ifdef BFQ_MQ
-+	spin_unlock_irqrestore(&bfqd->lock, flags);
-+#endif
-+	/*
-+	 * @blkg is going offline and will be ignored by
-+	 * blkg_[rw]stat_recursive_sum().  Transfer stats to the parent so
-+	 * that they don't get lost.  If IOs complete after this point, the
-+	 * stats for them will be lost.  Oh well...
-+	 */
-+	bfqg_stats_xfer_dead(bfqg);
-+}
-+
-+static void bfq_end_wr_async(struct bfq_data *bfqd)
-+{
-+	struct blkcg_gq *blkg;
-+
-+	list_for_each_entry(blkg, &bfqd->queue->blkg_list, q_node) {
-+		struct bfq_group *bfqg = blkg_to_bfqg(blkg);
-+		BUG_ON(!bfqg);
-+
-+		bfq_end_wr_async_queues(bfqd, bfqg);
-+	}
-+	bfq_end_wr_async_queues(bfqd, bfqd->root_group);
-+}
-+
-+static int bfq_io_show_weight(struct seq_file *sf, void *v)
-+{
-+	struct blkcg *blkcg = css_to_blkcg(seq_css(sf));
-+	struct bfq_group_data *bfqgd = blkcg_to_bfqgd(blkcg);
-+	unsigned int val = 0;
-+
-+	if (bfqgd)
-+		val = bfqgd->weight;
-+
-+	seq_printf(sf, "%u\n", val);
-+
-+	return 0;
-+}
-+
-+static int bfq_io_set_weight_legacy(struct cgroup_subsys_state *css,
-+				    struct cftype *cftype,
-+				    u64 val)
-+{
-+	struct blkcg *blkcg = css_to_blkcg(css);
-+	struct bfq_group_data *bfqgd = blkcg_to_bfqgd(blkcg);
-+	struct blkcg_gq *blkg;
-+	int ret = -ERANGE;
-+
-+	if (val < BFQ_MIN_WEIGHT || val > BFQ_MAX_WEIGHT)
-+		return ret;
-+
-+	ret = 0;
-+	spin_lock_irq(&blkcg->lock);
-+	bfqgd->weight = (unsigned short)val;
-+	hlist_for_each_entry(blkg, &blkcg->blkg_list, blkcg_node) {
-+		struct bfq_group *bfqg = blkg_to_bfqg(blkg);
-+
-+		if (!bfqg)
-+			continue;
-+		/*
-+		 * Setting the prio_changed flag of the entity
-+		 * to 1 with new_weight == weight would re-set
-+		 * the value of the weight to its ioprio mapping.
-+		 * Set the flag only if necessary.
-+		 */
-+		if ((unsigned short)val != bfqg->entity.new_weight) {
-+			bfqg->entity.new_weight = (unsigned short)val;
-+			/*
-+			 * Make sure that the above new value has been
-+			 * stored in bfqg->entity.new_weight before
-+			 * setting the prio_changed flag. In fact,
-+			 * this flag may be read asynchronously (in
-+			 * critical sections protected by a different
-+			 * lock than that held here), and finding this
-+			 * flag set may cause the execution of the code
-+			 * for updating parameters whose value may
-+			 * depend also on bfqg->entity.new_weight (in
-+			 * __bfq_entity_update_weight_prio).
-+			 * This barrier makes sure that the new value
-+			 * of bfqg->entity.new_weight is correctly
-+			 * seen in that code.
-+			 */
-+			smp_wmb();
-+			bfqg->entity.prio_changed = 1;
-+		}
-+	}
-+	spin_unlock_irq(&blkcg->lock);
-+
-+	return ret;
-+}
-+
-+static ssize_t bfq_io_set_weight(struct kernfs_open_file *of,
-+				 char *buf, size_t nbytes,
-+				 loff_t off)
-+{
-+	u64 weight;
-+	/* First unsigned long found in the file is used */
-+	int ret = kstrtoull(strim(buf), 0, &weight);
-+
-+	if (ret)
-+		return ret;
-+
-+	return bfq_io_set_weight_legacy(of_css(of), NULL, weight);
-+}
-+
-+#ifdef CONFIG_DEBUG_BLK_CGROUP
-+static int bfqg_print_stat(struct seq_file *sf, void *v)
-+{
-+	blkcg_print_blkgs(sf, css_to_blkcg(seq_css(sf)), blkg_prfill_stat,
-+			  &blkcg_policy_bfq, seq_cft(sf)->private, false);
-+	return 0;
-+}
-+
-+static int bfqg_print_rwstat(struct seq_file *sf, void *v)
-+{
-+	blkcg_print_blkgs(sf, css_to_blkcg(seq_css(sf)), blkg_prfill_rwstat,
-+			  &blkcg_policy_bfq, seq_cft(sf)->private, true);
-+	return 0;
-+}
-+
-+static u64 bfqg_prfill_stat_recursive(struct seq_file *sf,
-+				      struct blkg_policy_data *pd, int off)
-+{
-+	u64 sum = blkg_stat_recursive_sum(pd_to_blkg(pd),
-+					  &blkcg_policy_bfq, off);
-+	return __blkg_prfill_u64(sf, pd, sum);
-+}
-+
-+static u64 bfqg_prfill_rwstat_recursive(struct seq_file *sf,
-+					struct blkg_policy_data *pd, int off)
-+{
-+	struct blkg_rwstat sum = blkg_rwstat_recursive_sum(pd_to_blkg(pd),
-+							   &blkcg_policy_bfq,
-+							   off);
-+	return __blkg_prfill_rwstat(sf, pd, &sum);
-+}
-+
-+static int bfqg_print_stat_recursive(struct seq_file *sf, void *v)
-+{
-+	blkcg_print_blkgs(sf, css_to_blkcg(seq_css(sf)),
-+			  bfqg_prfill_stat_recursive, &blkcg_policy_bfq,
-+			  seq_cft(sf)->private, false);
-+	return 0;
-+}
-+
-+static int bfqg_print_rwstat_recursive(struct seq_file *sf, void *v)
-+{
-+	blkcg_print_blkgs(sf, css_to_blkcg(seq_css(sf)),
-+			  bfqg_prfill_rwstat_recursive, &blkcg_policy_bfq,
-+			  seq_cft(sf)->private, true);
-+	return 0;
-+}
-+
-+static u64 bfqg_prfill_sectors(struct seq_file *sf, struct blkg_policy_data *pd,
-+			       int off)
-+{
-+	u64 sum = blkg_rwstat_total(&pd->blkg->stat_bytes);
-+
-+	return __blkg_prfill_u64(sf, pd, sum >> 9);
-+}
-+
-+static int bfqg_print_stat_sectors(struct seq_file *sf, void *v)
-+{
-+	blkcg_print_blkgs(sf, css_to_blkcg(seq_css(sf)),
-+			  bfqg_prfill_sectors, &blkcg_policy_bfq, 0, false);
-+	return 0;
-+}
-+
-+static u64 bfqg_prfill_sectors_recursive(struct seq_file *sf,
-+					 struct blkg_policy_data *pd, int off)
-+{
-+	struct blkg_rwstat tmp = blkg_rwstat_recursive_sum(pd->blkg, NULL,
-+					offsetof(struct blkcg_gq, stat_bytes));
-+	u64 sum = atomic64_read(&tmp.aux_cnt[BLKG_RWSTAT_READ]) +
-+		atomic64_read(&tmp.aux_cnt[BLKG_RWSTAT_WRITE]);
-+
-+	return __blkg_prfill_u64(sf, pd, sum >> 9);
-+}
-+
-+static int bfqg_print_stat_sectors_recursive(struct seq_file *sf, void *v)
-+{
-+	blkcg_print_blkgs(sf, css_to_blkcg(seq_css(sf)),
-+			  bfqg_prfill_sectors_recursive, &blkcg_policy_bfq, 0,
-+			  false);
-+	return 0;
-+}
-+
-+
-+static u64 bfqg_prfill_avg_queue_size(struct seq_file *sf,
-+				      struct blkg_policy_data *pd, int off)
-+{
-+	struct bfq_group *bfqg = pd_to_bfqg(pd);
-+	u64 samples = blkg_stat_read(&bfqg->stats.avg_queue_size_samples);
-+	u64 v = 0;
-+
-+	if (samples) {
-+		v = blkg_stat_read(&bfqg->stats.avg_queue_size_sum);
-+		v = div64_u64(v, samples);
-+	}
-+	__blkg_prfill_u64(sf, pd, v);
-+	return 0;
-+}
-+
-+/* print avg_queue_size */
-+static int bfqg_print_avg_queue_size(struct seq_file *sf, void *v)
-+{
-+	blkcg_print_blkgs(sf, css_to_blkcg(seq_css(sf)),
-+			  bfqg_prfill_avg_queue_size, &blkcg_policy_bfq,
-+			  0, false);
-+	return 0;
-+}
-+#endif /* CONFIG_DEBUG_BLK_CGROUP */
-+
-+static struct bfq_group *
-+bfq_create_group_hierarchy(struct bfq_data *bfqd, int node)
-+{
-+	int ret;
-+
-+	ret = blkcg_activate_policy(bfqd->queue, &blkcg_policy_bfq);
-+	if (ret)
-+		return NULL;
-+
-+	return blkg_to_bfqg(bfqd->queue->root_blkg);
-+}
-+
-+#ifdef BFQ_MQ
-+#define BFQ_CGROUP_FNAME(param) "bfq-mq."#param
-+#else
-+#define BFQ_CGROUP_FNAME(param) "bfq-sq."#param
-+#endif
-+
-+static struct cftype bfq_blkcg_legacy_files[] = {
-+	{
-+		.name = BFQ_CGROUP_FNAME(weight),
-+		.flags = CFTYPE_NOT_ON_ROOT,
-+		.seq_show = bfq_io_show_weight,
-+		.write_u64 = bfq_io_set_weight_legacy,
-+	},
-+
-+	/* statistics, covers only the tasks in the bfqg */
-+	{
-+		.name = BFQ_CGROUP_FNAME(io_service_bytes),
-+		.private = (unsigned long)&blkcg_policy_bfq,
-+		.seq_show = blkg_print_stat_bytes,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(io_serviced),
-+		.private = (unsigned long)&blkcg_policy_bfq,
-+		.seq_show = blkg_print_stat_ios,
-+	},
-+#ifdef CONFIG_DEBUG_BLK_CGROUP
-+	{
-+		.name = BFQ_CGROUP_FNAME(time),
-+		.private = offsetof(struct bfq_group, stats.time),
-+		.seq_show = bfqg_print_stat,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(sectors),
-+		.seq_show = bfqg_print_stat_sectors,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(io_service_time),
-+		.private = offsetof(struct bfq_group, stats.service_time),
-+		.seq_show = bfqg_print_rwstat,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(io_wait_time),
-+		.private = offsetof(struct bfq_group, stats.wait_time),
-+		.seq_show = bfqg_print_rwstat,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(io_merged),
-+		.private = offsetof(struct bfq_group, stats.merged),
-+		.seq_show = bfqg_print_rwstat,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(io_queued),
-+		.private = offsetof(struct bfq_group, stats.queued),
-+		.seq_show = bfqg_print_rwstat,
-+	},
-+#endif /* CONFIG_DEBUG_BLK_CGROUP */
-+
-+	/* the same statictics which cover the bfqg and its descendants */
-+	{
-+		.name = BFQ_CGROUP_FNAME(io_service_bytes_recursive),
-+		.private = (unsigned long)&blkcg_policy_bfq,
-+		.seq_show = blkg_print_stat_bytes_recursive,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(io_serviced_recursive),
-+		.private = (unsigned long)&blkcg_policy_bfq,
-+		.seq_show = blkg_print_stat_ios_recursive,
-+	},
-+#ifdef CONFIG_DEBUG_BLK_CGROUP
-+	{
-+		.name = BFQ_CGROUP_FNAME(time_recursive),
-+		.private = offsetof(struct bfq_group, stats.time),
-+		.seq_show = bfqg_print_stat_recursive,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(sectors_recursive),
-+		.seq_show = bfqg_print_stat_sectors_recursive,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(io_service_time_recursive),
-+		.private = offsetof(struct bfq_group, stats.service_time),
-+		.seq_show = bfqg_print_rwstat_recursive,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(io_wait_time_recursive),
-+		.private = offsetof(struct bfq_group, stats.wait_time),
-+		.seq_show = bfqg_print_rwstat_recursive,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(io_merged_recursive),
-+		.private = offsetof(struct bfq_group, stats.merged),
-+		.seq_show = bfqg_print_rwstat_recursive,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(io_queued_recursive),
-+		.private = offsetof(struct bfq_group, stats.queued),
-+		.seq_show = bfqg_print_rwstat_recursive,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(avg_queue_size),
-+		.seq_show = bfqg_print_avg_queue_size,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(group_wait_time),
-+		.private = offsetof(struct bfq_group, stats.group_wait_time),
-+		.seq_show = bfqg_print_stat,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(idle_time),
-+		.private = offsetof(struct bfq_group, stats.idle_time),
-+		.seq_show = bfqg_print_stat,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(empty_time),
-+		.private = offsetof(struct bfq_group, stats.empty_time),
-+		.seq_show = bfqg_print_stat,
-+	},
-+	{
-+		.name = BFQ_CGROUP_FNAME(dequeue),
-+		.private = offsetof(struct bfq_group, stats.dequeue),
-+		.seq_show = bfqg_print_stat,
-+	},
-+#endif	/* CONFIG_DEBUG_BLK_CGROUP */
-+	{ }	/* terminate */
-+};
-+
-+static struct cftype bfq_blkg_files[] = {
-+	{
-+		.name = BFQ_CGROUP_FNAME(weight),
-+		.flags = CFTYPE_NOT_ON_ROOT,
-+		.seq_show = bfq_io_show_weight,
-+		.write = bfq_io_set_weight,
-+	},
-+	{} /* terminate */
-+};
-+
-+#undef BFQ_CGROUP_FNAME
-+
-+#else /* BFQ_GROUP_IOSCHED_ENABLED */
-+
-+static void bfq_bfqq_move(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+			  struct bfq_group *bfqg) {}
-+
-+static void bfq_init_entity(struct bfq_entity *entity,
-+			    struct bfq_group *bfqg)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+
-+	entity->weight = entity->new_weight;
-+	entity->orig_weight = entity->new_weight;
-+	if (bfqq) {
-+		bfqq->ioprio = bfqq->new_ioprio;
-+		bfqq->ioprio_class = bfqq->new_ioprio_class;
-+	}
-+	entity->sched_data = &bfqg->sched_data;
-+}
-+
-+static void bfq_bic_update_cgroup(struct bfq_io_cq *bic, struct bio *bio) {}
-+
-+static void bfq_end_wr_async(struct bfq_data *bfqd)
-+{
-+	bfq_end_wr_async_queues(bfqd, bfqd->root_group);
-+}
-+
-+static struct bfq_group *bfq_find_set_group(struct bfq_data *bfqd,
-+					    struct blkcg *blkcg)
-+{
-+	return bfqd->root_group;
-+}
-+
-+static struct bfq_group *bfqq_group(struct bfq_queue *bfqq)
-+{
-+	return bfqq->bfqd->root_group;
-+}
-+
-+static struct bfq_group *
-+bfq_create_group_hierarchy(struct bfq_data *bfqd, int node)
-+{
-+	struct bfq_group *bfqg;
-+	int i;
-+
-+	bfqg = kmalloc_node(sizeof(*bfqg), GFP_KERNEL | __GFP_ZERO, node);
-+	if (!bfqg)
-+		return NULL;
-+
-+	for (i = 0; i < BFQ_IOPRIO_CLASSES; i++)
-+		bfqg->sched_data.service_tree[i] = BFQ_SERVICE_TREE_INIT;
-+
-+	return bfqg;
-+}
-+#endif
-diff --git a/block/bfq-ioc.c b/block/bfq-ioc.c
-new file mode 100644
-index 000000000000..fb7bb8f08b75
---- /dev/null
-+++ b/block/bfq-ioc.c
-@@ -0,0 +1,36 @@
-+/*
-+ * BFQ: I/O context handling.
-+ *
-+ * Based on ideas and code from CFQ:
-+ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
-+ *
-+ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
-+ *		      Paolo Valente <paolo.valente@unimore.it>
-+ *
-+ * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it>
-+ */
-+
-+/**
-+ * icq_to_bic - convert iocontext queue structure to bfq_io_cq.
-+ * @icq: the iocontext queue.
-+ */
-+static struct bfq_io_cq *icq_to_bic(struct io_cq *icq)
-+{
-+	/* bic->icq is the first member, %NULL will convert to %NULL */
-+	return container_of(icq, struct bfq_io_cq, icq);
-+}
-+
-+/**
-+ * bfq_bic_lookup - search into @ioc a bic associated to @bfqd.
-+ * @bfqd: the lookup key.
-+ * @ioc: the io_context of the process doing I/O.
-+ *
-+ * Queue lock must be held.
-+ */
-+static struct bfq_io_cq *bfq_bic_lookup(struct bfq_data *bfqd,
-+					struct io_context *ioc)
-+{
-+	if (ioc)
-+		return icq_to_bic(ioc_lookup_icq(ioc, bfqd->queue));
-+	return NULL;
-+}
-diff --git a/block/bfq-mq-iosched.c b/block/bfq-mq-iosched.c
-new file mode 100644
-index 000000000000..cd6d5a2f838f
---- /dev/null
-+++ b/block/bfq-mq-iosched.c
-@@ -0,0 +1,6426 @@
-+/*
-+ * Budget Fair Queueing (BFQ) I/O scheduler.
-+ *
-+ * Based on ideas and code from CFQ:
-+ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
-+ *
-+ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
-+ *		      Paolo Valente <paolo.valente@unimore.it>
-+ *
-+ * Copyright (C) 2015 Paolo Valente <paolo.valente@unimore.it>
-+ *
-+ * Copyright (C) 2017 Paolo Valente <paolo.valente@linaro.org>
-+ *
-+ * Licensed under the GPL-2 as detailed in the accompanying COPYING.BFQ
-+ * file.
-+ *
-+ * BFQ is a proportional-share I/O scheduler, with some extra
-+ * low-latency capabilities. BFQ also supports full hierarchical
-+ * scheduling through cgroups. Next paragraphs provide an introduction
-+ * on BFQ inner workings. Details on BFQ benefits and usage can be
-+ * found in Documentation/block/bfq-iosched.txt.
-+ *
-+ * BFQ is a proportional-share storage-I/O scheduling algorithm based
-+ * on the slice-by-slice service scheme of CFQ. But BFQ assigns
-+ * budgets, measured in number of sectors, to processes instead of
-+ * time slices. The device is not granted to the in-service process
-+ * for a given time slice, but until it has exhausted its assigned
-+ * budget. This change from the time to the service domain enables BFQ
-+ * to distribute the device throughput among processes as desired,
-+ * without any distortion due to throughput fluctuations, or to device
-+ * internal queueing. BFQ uses an ad hoc internal scheduler, called
-+ * B-WF2Q+, to schedule processes according to their budgets. More
-+ * precisely, BFQ schedules queues associated with processes. Thanks to
-+ * the accurate policy of B-WF2Q+, BFQ can afford to assign high
-+ * budgets to I/O-bound processes issuing sequential requests (to
-+ * boost the throughput), and yet guarantee a low latency to
-+ * interactive and soft real-time applications.
-+ *
-+ * In particular, BFQ schedules I/O so as to achieve the latter goal--
-+ * low latency for interactive and soft real-time applications--if the
-+ * low_latency parameter is set (default configuration). To this
-+ * purpose, BFQ constantly tries to detect whether the I/O requests in
-+ * a bfq_queue come from an interactive or a soft real-time
-+ * application. For brevity, in these cases, the queue is said to be
-+ * interactive or soft real-time. In both cases, BFQ privileges the
-+ * service of the queue, over that of non-interactive and
-+ * non-soft-real-time queues. This privileging is performed, mainly,
-+ * by raising the weight of the queue. So, for brevity, we call just
-+ * weight-raising periods the time periods during which a queue is
-+ * privileged, because deemed interactive or soft real-time.
-+ *
-+ * The detection of soft real-time queues/applications is described in
-+ * detail in the comments on the function
-+ * bfq_bfqq_softrt_next_start. On the other hand, the detection of an
-+ * interactive queue works as follows: a queue is deemed interactive
-+ * if it is constantly non empty only for a limited time interval,
-+ * after which it does become empty. The queue may be deemed
-+ * interactive again (for a limited time), if it restarts being
-+ * constantly non empty, provided that this happens only after the
-+ * queue has remained empty for a given minimum idle time.
-+ *
-+ * By default, BFQ computes automatically the above maximum time
-+ * interval, i.e., the time interval after which a constantly
-+ * non-empty queue stops being deemed interactive. Since a queue is
-+ * weight-raised while it is deemed interactive, this maximum time
-+ * interval happens to coincide with the (maximum) duration of the
-+ * weight-raising for interactive queues.
-+ *
-+ * NOTE: if the main or only goal, with a given device, is to achieve
-+ * the maximum-possible throughput at all times, then do switch off
-+ * all low-latency heuristics for that device, by setting low_latency
-+ * to 0.
-+ *
-+ * BFQ is described in [1], where also a reference to the initial,
-+ * more theoretical paper on BFQ can be found. The interested reader
-+ * can find in the latter paper full details on the main algorithm, as
-+ * well as formulas of the guarantees and formal proofs of all the
-+ * properties.  With respect to the version of BFQ presented in these
-+ * papers, this implementation adds a few more heuristics, such as the
-+ * one that guarantees a low latency to soft real-time applications,
-+ * and a hierarchical extension based on H-WF2Q+.
-+ *
-+ * B-WF2Q+ is based on WF2Q+, that is described in [2], together with
-+ * H-WF2Q+, while the augmented tree used to implement B-WF2Q+ with O(log N)
-+ * complexity derives from the one introduced with EEVDF in [3].
-+ *
-+ * [1] P. Valente, A. Avanzini, "Evolution of the BFQ Storage I/O
-+ *   Scheduler", Proceedings of the First Workshop on Mobile System
-+ *   Technologies (MST-2015), May 2015.
-+ *   http://algogroup.unimore.it/people/paolo/disk_sched/mst-2015.pdf
-+ *
-+ * http://algogroup.unimo.it/people/paolo/disk_sched/bf1-v1-suite-results.pdf
-+ *
-+ * [2] Jon C.R. Bennett and H. Zhang, ``Hierarchical Packet Fair Queueing
-+ *     Algorithms,'' IEEE/ACM Transactions on Networking, 5(5):675-689,
-+ *     Oct 1997.
-+ *
-+ * http://www.cs.cmu.edu/~hzhang/papers/TON-97-Oct.ps.gz
-+ *
-+ * [3] I. Stoica and H. Abdel-Wahab, ``Earliest Eligible Virtual Deadline
-+ *     First: A Flexible and Accurate Mechanism for Proportional Share
-+ *     Resource Allocation,'' technical report.
-+ *
-+ * http://www.cs.berkeley.edu/~istoica/papers/eevdf-tr-95.pdf
-+ */
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/blkdev.h>
-+#include <linux/cgroup.h>
-+#include <linux/elevator.h>
-+#include <linux/jiffies.h>
-+#include <linux/rbtree.h>
-+#include <linux/ioprio.h>
-+#include <linux/sbitmap.h>
-+#include <linux/delay.h>
-+
-+#include "blk.h"
-+#include "blk-mq.h"
-+#include "blk-mq-tag.h"
-+#include "blk-mq-sched.h"
-+#include "bfq-mq.h"
-+#include "blk-wbt.h"
-+
-+/* Expiration time of sync (0) and async (1) requests, in ns. */
-+static const u64 bfq_fifo_expire[2] = { NSEC_PER_SEC / 4, NSEC_PER_SEC / 8 };
-+
-+/* Maximum backwards seek, in KiB. */
-+static const int bfq_back_max = (16 * 1024);
-+
-+/* Penalty of a backwards seek, in number of sectors. */
-+static const int bfq_back_penalty = 2;
-+
-+/* Idling period duration, in ns. */
-+static u32 bfq_slice_idle = (NSEC_PER_SEC / 125);
-+
-+/* Minimum number of assigned budgets for which stats are safe to compute. */
-+static const int bfq_stats_min_budgets = 194;
-+
-+/* Default maximum budget values, in sectors and number of requests. */
-+static const int bfq_default_max_budget = (16 * 1024);
-+
-+/*
-+ * When a sync request is dispatched, the queue that contains that
-+ * request, and all the ancestor entities of that queue, are charged
-+ * with the number of sectors of the request. In constrast, if the
-+ * request is async, then the queue and its ancestor entities are
-+ * charged with the number of sectors of the request, multiplied by
-+ * the factor below. This throttles the bandwidth for async I/O,
-+ * w.r.t. to sync I/O, and it is done to counter the tendency of async
-+ * writes to steal I/O throughput to reads.
-+ *
-+ * The current value of this parameter is the result of a tuning with
-+ * several hardware and software configurations. We tried to find the
-+ * lowest value for which writes do not cause noticeable problems to
-+ * reads. In fact, the lower this parameter, the stabler I/O control,
-+ * in the following respect.  The lower this parameter is, the less
-+ * the bandwidth enjoyed by a group decreases
-+ * - when the group does writes, w.r.t. to when it does reads;
-+ * - when other groups do reads, w.r.t. to when they do writes.
-+ */
-+static const int bfq_async_charge_factor = 3;
-+
-+/* Default timeout values, in jiffies, approximating CFQ defaults. */
-+static const int bfq_timeout = (HZ / 8);
-+
-+/*
-+ * Time limit for merging (see comments in bfq_setup_cooperator). Set
-+ * to the slowest value that, in our tests, proved to be effective in
-+ * removing false positives, while not causing true positives to miss
-+ * queue merging.
-+ *
-+ * As can be deduced from the low time limit below, queue merging, if
-+ * successful, happens at the very beggining of the I/O of the involved
-+ * cooperating processes, as a consequence of the arrival of the very
-+ * first requests from each cooperator.  After that, there is very
-+ * little chance to find cooperators.
-+ */
-+static const unsigned long bfq_merge_time_limit = HZ/10;
-+
-+#define MAX_LENGTH_REASON_NAME 25
-+
-+static const char reason_name[][MAX_LENGTH_REASON_NAME] = {"TOO_IDLE",
-+"BUDGET_TIMEOUT", "BUDGET_EXHAUSTED", "NO_MORE_REQUESTS",
-+"PREEMPTED"};
-+
-+static struct kmem_cache *bfq_pool;
-+
-+/* Below this threshold (in ns), we consider thinktime immediate. */
-+#define BFQ_MIN_TT		(2 * NSEC_PER_MSEC)
-+
-+/* hw_tag detection: parallel requests threshold and min samples needed. */
-+#define BFQ_HW_QUEUE_THRESHOLD	4
-+#define BFQ_HW_QUEUE_SAMPLES	32
-+
-+#define BFQQ_SEEK_THR		(sector_t)(8 * 100)
-+#define BFQQ_SECT_THR_NONROT	(sector_t)(2 * 32)
-+#define BFQQ_CLOSE_THR		(sector_t)(8 * 1024)
-+#define BFQQ_SEEKY(bfqq)	(hweight32(bfqq->seek_history) > 19)
-+
-+/* Min number of samples required to perform peak-rate update */
-+#define BFQ_RATE_MIN_SAMPLES	32
-+/* Min observation time interval required to perform a peak-rate update (ns) */
-+#define BFQ_RATE_MIN_INTERVAL	(300*NSEC_PER_MSEC)
-+/* Target observation time interval for a peak-rate update (ns) */
-+#define BFQ_RATE_REF_INTERVAL	NSEC_PER_SEC
-+
-+/*
-+ * Shift used for peak-rate fixed precision calculations.
-+ * With
-+ * - the current shift: 16 positions
-+ * - the current type used to store rate: u32
-+ * - the current unit of measure for rate: [sectors/usec], or, more precisely,
-+ *   [(sectors/usec) / 2^BFQ_RATE_SHIFT] to take into account the shift,
-+ * the range of rates that can be stored is
-+ * [1 / 2^BFQ_RATE_SHIFT, 2^(32 - BFQ_RATE_SHIFT)] sectors/usec =
-+ * [1 / 2^16, 2^16] sectors/usec = [15e-6, 65536] sectors/usec =
-+ * [15, 65G] sectors/sec
-+ * Which, assuming a sector size of 512B, corresponds to a range of
-+ * [7.5K, 33T] B/sec
-+ */
-+#define BFQ_RATE_SHIFT		16
-+
-+/*
-+ * When configured for computing the duration of the weight-raising
-+ * for interactive queues automatically (see the comments at the
-+ * beginning of this file), BFQ does it using the following formula:
-+ * duration = (ref_rate / r) * ref_wr_duration,
-+ * where r is the peak rate of the device, and ref_rate and
-+ * ref_wr_duration are two reference parameters.  In particular,
-+ * ref_rate is the peak rate of the reference storage device (see
-+ * below), and ref_wr_duration is about the maximum time needed, with
-+ * BFQ and while reading two files in parallel, to load typical large
-+ * applications on the reference device (see the comments on
-+ * max_service_from_wr below, for more details on how ref_wr_duration
-+ * is obtained).  In practice, the slower/faster the device at hand
-+ * is, the more/less it takes to load applications with respect to the
-+ * reference device.  Accordingly, the longer/shorter BFQ grants
-+ * weight raising to interactive applications.
-+ *
-+ * BFQ uses two different reference pairs (ref_rate, ref_wr_duration),
-+ * depending on whether the device is rotational or non-rotational.
-+ *
-+ * In the following definitions, ref_rate[0] and ref_wr_duration[0]
-+ * are the reference values for a rotational device, whereas
-+ * ref_rate[1] and ref_wr_duration[1] are the reference values for a
-+ * non-rotational device. The reference rates are not the actual peak
-+ * rates of the devices used as a reference, but slightly lower
-+ * values. The reason for using slightly lower values is that the
-+ * peak-rate estimator tends to yield slightly lower values than the
-+ * actual peak rate (it can yield the actual peak rate only if there
-+ * is only one process doing I/O, and the process does sequential
-+ * I/O).
-+ *
-+ * The reference peak rates are measured in sectors/usec, left-shifted
-+ * by BFQ_RATE_SHIFT.
-+ */
-+static int ref_rate[2] = {14000, 33000};
-+/*
-+ * To improve readability, a conversion function is used to initialize
-+ * the following array, which entails that the array can be
-+ * initialized only in a function.
-+ */
-+static int ref_wr_duration[2];
-+
-+/*
-+ * BFQ uses the above-detailed, time-based weight-raising mechanism to
-+ * privilege interactive tasks. This mechanism is vulnerable to the
-+ * following false positives: I/O-bound applications that will go on
-+ * doing I/O for much longer than the duration of weight
-+ * raising. These applications have basically no benefit from being
-+ * weight-raised at the beginning of their I/O. On the opposite end,
-+ * while being weight-raised, these applications
-+ * a) unjustly steal throughput to applications that may actually need
-+ * low latency;
-+ * b) make BFQ uselessly perform device idling; device idling results
-+ * in loss of device throughput with most flash-based storage, and may
-+ * increase latencies when used purposelessly.
-+ *
-+ * BFQ tries to reduce these problems, by adopting the following
-+ * countermeasure. To introduce this countermeasure, we need first to
-+ * finish explaining how the duration of weight-raising for
-+ * interactive tasks is computed.
-+ *
-+ * For a bfq_queue deemed as interactive, the duration of weight
-+ * raising is dynamically adjusted, as a function of the estimated
-+ * peak rate of the device, so as to be equal to the time needed to
-+ * execute the 'largest' interactive task we benchmarked so far. By
-+ * largest task, we mean the task for which each involved process has
-+ * to do more I/O than for any of the other tasks we benchmarked. This
-+ * reference interactive task is the start-up of LibreOffice Writer,
-+ * and in this task each process/bfq_queue needs to have at most ~110K
-+ * sectors transferred.
-+ *
-+ * This last piece of information enables BFQ to reduce the actual
-+ * duration of weight-raising for at least one class of I/O-bound
-+ * applications: those doing sequential or quasi-sequential I/O. An
-+ * example is file copy. In fact, once started, the main I/O-bound
-+ * processes of these applications usually consume the above 110K
-+ * sectors in much less time than the processes of an application that
-+ * is starting, because these I/O-bound processes will greedily devote
-+ * almost all their CPU cycles only to their target,
-+ * throughput-friendly I/O operations. This is even more true if BFQ
-+ * happens to be underestimating the device peak rate, and thus
-+ * overestimating the duration of weight raising. But, according to
-+ * our measurements, once transferred 110K sectors, these processes
-+ * have no right to be weight-raised any longer.
-+ *
-+ * Basing on the last consideration, BFQ ends weight-raising for a
-+ * bfq_queue if the latter happens to have received an amount of
-+ * service at least equal to the following constant. The constant is
-+ * set to slightly more than 110K, to have a minimum safety margin.
-+ *
-+ * This early ending of weight-raising reduces the amount of time
-+ * during which interactive false positives cause the two problems
-+ * described at the beginning of these comments.
-+ */
-+static const unsigned long max_service_from_wr = 120000;
-+
-+#define BFQ_SERVICE_TREE_INIT	((struct bfq_service_tree)		\
-+				{ RB_ROOT, RB_ROOT, NULL, NULL, 0, 0 })
-+
-+#define RQ_BIC(rq)		icq_to_bic((rq)->elv.priv[0])
-+#define RQ_BFQQ(rq)		((rq)->elv.priv[1])
-+
-+/**
-+ * icq_to_bic - convert iocontext queue structure to bfq_io_cq.
-+ * @icq: the iocontext queue.
-+ */
-+static struct bfq_io_cq *icq_to_bic(struct io_cq *icq)
-+{
-+	/* bic->icq is the first member, %NULL will convert to %NULL */
-+	return container_of(icq, struct bfq_io_cq, icq);
-+}
-+
-+/**
-+ * bfq_bic_lookup - search into @ioc a bic associated to @bfqd.
-+ * @bfqd: the lookup key.
-+ * @ioc: the io_context of the process doing I/O.
-+ * @q: the request queue.
-+ */
-+static struct bfq_io_cq *bfq_bic_lookup(struct bfq_data *bfqd,
-+					struct io_context *ioc,
-+					struct request_queue *q)
-+{
-+	if (ioc) {
-+		unsigned long flags;
-+		struct bfq_io_cq *icq;
-+
-+		spin_lock_irqsave(q->queue_lock, flags);
-+		icq = icq_to_bic(ioc_lookup_icq(ioc, q));
-+		spin_unlock_irqrestore(q->queue_lock, flags);
-+
-+		return icq;
-+	}
-+
-+	return NULL;
-+}
-+
-+/*
-+ * Scheduler run of queue, if there are requests pending and no one in the
-+ * driver that will restart queueing.
-+ */
-+static void bfq_schedule_dispatch(struct bfq_data *bfqd)
-+{
-+	if (bfqd->queued != 0) {
-+		bfq_log(bfqd, "");
-+		blk_mq_run_hw_queues(bfqd->queue, true);
-+	}
-+}
-+
-+#define BFQ_MQ
-+#include "bfq-sched.c"
-+#include "bfq-cgroup-included.c"
-+
-+#define bfq_class_idle(bfqq)	((bfqq)->ioprio_class == IOPRIO_CLASS_IDLE)
-+#define bfq_class_rt(bfqq)	((bfqq)->ioprio_class == IOPRIO_CLASS_RT)
-+
-+#define bfq_sample_valid(samples)	((samples) > 80)
-+
-+/*
-+ * Lifted from AS - choose which of rq1 and rq2 that is best served now.
-+ * We choose the request that is closesr to the head right now.  Distance
-+ * behind the head is penalized and only allowed to a certain extent.
-+ */
-+static struct request *bfq_choose_req(struct bfq_data *bfqd,
-+				      struct request *rq1,
-+				      struct request *rq2,
-+				      sector_t last)
-+{
-+	sector_t s1, s2, d1 = 0, d2 = 0;
-+	unsigned long back_max;
-+#define BFQ_RQ1_WRAP	0x01 /* request 1 wraps */
-+#define BFQ_RQ2_WRAP	0x02 /* request 2 wraps */
-+	unsigned int wrap = 0; /* bit mask: requests behind the disk head? */
-+
-+	if (!rq1 || rq1 == rq2)
-+		return rq2;
-+	if (!rq2)
-+		return rq1;
-+
-+	if (rq_is_sync(rq1) && !rq_is_sync(rq2))
-+		return rq1;
-+	else if (rq_is_sync(rq2) && !rq_is_sync(rq1))
-+		return rq2;
-+	if ((rq1->cmd_flags & REQ_META) && !(rq2->cmd_flags & REQ_META))
-+		return rq1;
-+	else if ((rq2->cmd_flags & REQ_META) && !(rq1->cmd_flags & REQ_META))
-+		return rq2;
-+
-+	s1 = blk_rq_pos(rq1);
-+	s2 = blk_rq_pos(rq2);
-+
-+	/*
-+	 * By definition, 1KiB is 2 sectors.
-+	 */
-+	back_max = bfqd->bfq_back_max * 2;
-+
-+	/*
-+	 * Strict one way elevator _except_ in the case where we allow
-+	 * short backward seeks which are biased as twice the cost of a
-+	 * similar forward seek.
-+	 */
-+	if (s1 >= last)
-+		d1 = s1 - last;
-+	else if (s1 + back_max >= last)
-+		d1 = (last - s1) * bfqd->bfq_back_penalty;
-+	else
-+		wrap |= BFQ_RQ1_WRAP;
-+
-+	if (s2 >= last)
-+		d2 = s2 - last;
-+	else if (s2 + back_max >= last)
-+		d2 = (last - s2) * bfqd->bfq_back_penalty;
-+	else
-+		wrap |= BFQ_RQ2_WRAP;
-+
-+	/* Found required data */
-+
-+	/*
-+	 * By doing switch() on the bit mask "wrap" we avoid having to
-+	 * check two variables for all permutations: --> faster!
-+	 */
-+	switch (wrap) {
-+	case 0: /* common case for CFQ: rq1 and rq2 not wrapped */
-+		if (d1 < d2)
-+			return rq1;
-+		else if (d2 < d1)
-+			return rq2;
-+
-+		if (s1 >= s2)
-+			return rq1;
-+		else
-+			return rq2;
-+
-+	case BFQ_RQ2_WRAP:
-+		return rq1;
-+	case BFQ_RQ1_WRAP:
-+		return rq2;
-+	case (BFQ_RQ1_WRAP|BFQ_RQ2_WRAP): /* both rqs wrapped */
-+	default:
-+		/*
-+		 * Since both rqs are wrapped,
-+		 * start with the one that's further behind head
-+		 * (--> only *one* back seek required),
-+		 * since back seek takes more time than forward.
-+		 */
-+		if (s1 <= s2)
-+			return rq1;
-+		else
-+			return rq2;
-+	}
-+}
-+
-+/*
-+ * See the comments on bfq_limit_depth for the purpose of
-+ * the depths set in the function.
-+ */
-+static void bfq_update_depths(struct bfq_data *bfqd, struct sbitmap_queue *bt)
-+{
-+	bfqd->sb_shift = bt->sb.shift;
-+
-+	/*
-+	 * In-word depths if no bfq_queue is being weight-raised:
-+	 * leaving 25% of tags only for sync reads.
-+	 *
-+	 * In next formulas, right-shift the value
-+	 * (1U<<bfqd->sb_shift), instead of computing directly
-+	 * (1U<<(bfqd->sb_shift - something)), to be robust against
-+	 * any possible value of bfqd->sb_shift, without having to
-+	 * limit 'something'.
-+	 */
-+	/* no more than 50% of tags for async I/O */
-+	bfqd->word_depths[0][0] = max((1U<<bfqd->sb_shift)>>1, 1U);
-+	/*
-+	 * no more than 75% of tags for sync writes (25% extra tags
-+	 * w.r.t. async I/O, to prevent async I/O from starving sync
-+	 * writes)
-+	 */
-+	bfqd->word_depths[0][1] = max(((1U<<bfqd->sb_shift) * 3)>>2, 1U);
-+
-+	/*
-+	 * In-word depths in case some bfq_queue is being weight-
-+	 * raised: leaving ~63% of tags for sync reads. This is the
-+	 * highest percentage for which, in our tests, application
-+	 * start-up times didn't suffer from any regression due to tag
-+	 * shortage.
-+	 */
-+	/* no more than ~18% of tags for async I/O */
-+	bfqd->word_depths[1][0] = max(((1U<<bfqd->sb_shift) * 3)>>4, 1U);
-+	/* no more than ~37% of tags for sync writes (~20% extra tags) */
-+	bfqd->word_depths[1][1] = max(((1U<<bfqd->sb_shift) * 6)>>4, 1U);
-+}
-+
-+/*
-+ * Async I/O can easily starve sync I/O (both sync reads and sync
-+ * writes), by consuming all tags. Similarly, storms of sync writes,
-+ * such as those that sync(2) may trigger, can starve sync reads.
-+ * Limit depths of async I/O and sync writes so as to counter both
-+ * problems.
-+ */
-+static void bfq_limit_depth(unsigned int op, struct blk_mq_alloc_data *data)
-+{
-+	struct blk_mq_tags *tags = blk_mq_tags_from_data(data);
-+	struct bfq_data *bfqd = data->q->elevator->elevator_data;
-+	struct sbitmap_queue *bt;
-+
-+	if (op_is_sync(op) && !op_is_write(op))
-+		return;
-+
-+	if (data->flags & BLK_MQ_REQ_RESERVED) {
-+		if (unlikely(!tags->nr_reserved_tags)) {
-+			WARN_ON_ONCE(1);
-+			return;
-+		}
-+		bt = &tags->breserved_tags;
-+	} else
-+		bt = &tags->bitmap_tags;
-+
-+	if (unlikely(bfqd->sb_shift != bt->sb.shift))
-+		bfq_update_depths(bfqd, bt);
-+
-+	data->shallow_depth =
-+		bfqd->word_depths[!!bfqd->wr_busy_queues][op_is_sync(op)];
-+
-+	bfq_log(bfqd, "wr_busy %d sync %d depth %u",
-+			bfqd->wr_busy_queues, op_is_sync(op),
-+			data->shallow_depth);
-+}
-+
-+static struct bfq_queue *
-+bfq_rq_pos_tree_lookup(struct bfq_data *bfqd, struct rb_root *root,
-+		     sector_t sector, struct rb_node **ret_parent,
-+		     struct rb_node ***rb_link)
-+{
-+	struct rb_node **p, *parent;
-+	struct bfq_queue *bfqq = NULL;
-+
-+	parent = NULL;
-+	p = &root->rb_node;
-+	while (*p) {
-+		struct rb_node **n;
-+
-+		parent = *p;
-+		bfqq = rb_entry(parent, struct bfq_queue, pos_node);
-+
-+		/*
-+		 * Sort strictly based on sector. Smallest to the left,
-+		 * largest to the right.
-+		 */
-+		if (sector > blk_rq_pos(bfqq->next_rq))
-+			n = &(*p)->rb_right;
-+		else if (sector < blk_rq_pos(bfqq->next_rq))
-+			n = &(*p)->rb_left;
-+		else
-+			break;
-+		p = n;
-+		bfqq = NULL;
-+	}
-+
-+	*ret_parent = parent;
-+	if (rb_link)
-+		*rb_link = p;
-+
-+	bfq_log(bfqd, "%llu: returning %d",
-+		(unsigned long long) sector,
-+		bfqq ? bfqq->pid : 0);
-+
-+	return bfqq;
-+}
-+
-+static bool bfq_too_late_for_merging(struct bfq_queue *bfqq)
-+{
-+	return bfqq->service_from_backlogged > 0 &&
-+		time_is_before_jiffies(bfqq->first_IO_time +
-+				       bfq_merge_time_limit);
-+}
-+
-+static void bfq_pos_tree_add_move(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	struct rb_node **p, *parent;
-+	struct bfq_queue *__bfqq;
-+
-+	if (bfqq->pos_root) {
-+		rb_erase(&bfqq->pos_node, bfqq->pos_root);
-+		bfqq->pos_root = NULL;
-+	}
-+
-+	/*
-+	 * bfqq cannot be merged any longer (see comments in
-+	 * bfq_setup_cooperator): no point in adding bfqq into the
-+	 * position tree.
-+	 */
-+	if (bfq_too_late_for_merging(bfqq))
-+		return;
-+
-+	if (bfq_class_idle(bfqq))
-+		return;
-+	if (!bfqq->next_rq)
-+		return;
-+
-+	bfqq->pos_root = &bfq_bfqq_to_bfqg(bfqq)->rq_pos_tree;
-+	__bfqq = bfq_rq_pos_tree_lookup(bfqd, bfqq->pos_root,
-+			blk_rq_pos(bfqq->next_rq), &parent, &p);
-+	if (!__bfqq) {
-+		rb_link_node(&bfqq->pos_node, parent, p);
-+		rb_insert_color(&bfqq->pos_node, bfqq->pos_root);
-+	} else
-+		bfqq->pos_root = NULL;
-+}
-+
-+/*
-+ * Tell whether there are active queues or groups with differentiated weights.
-+ */
-+static bool bfq_differentiated_weights(struct bfq_data *bfqd)
-+{
-+	/*
-+	 * For weights to differ, at least one of the trees must contain
-+	 * at least two nodes.
-+	 */
-+	return (!RB_EMPTY_ROOT(&bfqd->queue_weights_tree) &&
-+		(bfqd->queue_weights_tree.rb_node->rb_left ||
-+		 bfqd->queue_weights_tree.rb_node->rb_right)
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	       ) ||
-+	       (!RB_EMPTY_ROOT(&bfqd->group_weights_tree) &&
-+		(bfqd->group_weights_tree.rb_node->rb_left ||
-+		 bfqd->group_weights_tree.rb_node->rb_right)
-+#endif
-+	       );
-+}
-+
-+/*
-+ * The following function returns true if every queue must receive the
-+ * same share of the throughput (this condition is used when deciding
-+ * whether idling may be disabled, see the comments in the function
-+ * bfq_better_to_idle()).
-+ *
-+ * Such a scenario occurs when:
-+ * 1) all active queues have the same weight,
-+ * 2) all active groups at the same level in the groups tree have the same
-+ *    weight,
-+ * 3) all active groups at the same level in the groups tree have the same
-+ *    number of children.
-+ *
-+ * Unfortunately, keeping the necessary state for evaluating exactly the
-+ * above symmetry conditions would be quite complex and time-consuming.
-+ * Therefore this function evaluates, instead, the following stronger
-+ * sub-conditions, for which it is much easier to maintain the needed
-+ * state:
-+ * 1) all active queues have the same weight,
-+ * 2) all active groups have the same weight,
-+ * 3) all active groups have at most one active child each.
-+ * In particular, the last two conditions are always true if hierarchical
-+ * support and the cgroups interface are not enabled, thus no state needs
-+ * to be maintained in this case.
-+ */
-+static bool bfq_symmetric_scenario(struct bfq_data *bfqd)
-+{
-+	return !bfq_differentiated_weights(bfqd);
-+}
-+
-+/*
-+ * If the weight-counter tree passed as input contains no counter for
-+ * the weight of the input entity, then add that counter; otherwise just
-+ * increment the existing counter.
-+ *
-+ * Note that weight-counter trees contain few nodes in mostly symmetric
-+ * scenarios. For example, if all queues have the same weight, then the
-+ * weight-counter tree for the queues may contain at most one node.
-+ * This holds even if low_latency is on, because weight-raised queues
-+ * are not inserted in the tree.
-+ * In most scenarios, the rate at which nodes are created/destroyed
-+ * should be low too.
-+ */
-+static void bfq_weights_tree_add(struct bfq_data *bfqd,
-+				 struct bfq_entity *entity,
-+				 struct rb_root *root)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+	struct rb_node **new = &(root->rb_node), *parent = NULL;
-+
-+	/*
-+	 * Do not insert if the entity is already associated with a
-+	 * counter, which happens if:
-+	 *   1) the entity is associated with a queue,
-+	 *   2) a request arrival has caused the queue to become both
-+	 *      non-weight-raised, and hence change its weight, and
-+	 *      backlogged; in this respect, each of the two events
-+	 *      causes an invocation of this function,
-+	 *   3) this is the invocation of this function caused by the
-+	 *      second event. This second invocation is actually useless,
-+	 *      and we handle this fact by exiting immediately. More
-+	 *      efficient or clearer solutions might possibly be adopted.
-+	 */
-+	if (entity->weight_counter)
-+		return;
-+
-+	while (*new) {
-+		struct bfq_weight_counter *__counter = container_of(*new,
-+						struct bfq_weight_counter,
-+						weights_node);
-+		parent = *new;
-+
-+		if (entity->weight == __counter->weight) {
-+			entity->weight_counter = __counter;
-+			goto inc_counter;
-+		}
-+		if (entity->weight < __counter->weight)
-+			new = &((*new)->rb_left);
-+		else
-+			new = &((*new)->rb_right);
-+	}
-+
-+	entity->weight_counter = kzalloc(sizeof(struct bfq_weight_counter),
-+					 GFP_ATOMIC);
-+
-+	/*
-+	 * In the unlucky event of an allocation failure, we just
-+	 * exit. This will cause the weight of entity to not be
-+	 * considered in bfq_differentiated_weights, which, in its
-+	 * turn, causes the scenario to be deemed wrongly symmetric in
-+	 * case entity's weight would have been the only weight making
-+	 * the scenario asymmetric. On the bright side, no unbalance
-+	 * will however occur when entity becomes inactive again (the
-+	 * invocation of this function is triggered by an activation
-+	 * of entity). In fact, bfq_weights_tree_remove does nothing
-+	 * if !entity->weight_counter.
-+	 */
-+	if (unlikely(!entity->weight_counter))
-+		return;
-+
-+	entity->weight_counter->weight = entity->weight;
-+	rb_link_node(&entity->weight_counter->weights_node, parent, new);
-+	rb_insert_color(&entity->weight_counter->weights_node, root);
-+
-+inc_counter:
-+	entity->weight_counter->num_active++;
-+
-+	if (bfqq) {
-+		bfq_log_bfqq(bfqq->bfqd, bfqq, "[%s] weight %d symmetric %d",
-+			     __func__, entity->weight,
-+			     bfq_symmetric_scenario(bfqd));
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	} else {
-+		struct bfq_group *bfqg =
-+			container_of(entity, struct bfq_group, entity);
-+
-+		bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+			     "[%s] weight %d symmetric %d",
-+			     __func__, entity->weight,
-+			     bfq_symmetric_scenario(bfqd));
-+#endif
-+	}
-+}
-+
-+/*
-+ * Decrement the weight counter associated with the entity, and, if the
-+ * counter reaches 0, remove the counter from the tree.
-+ * See the comments to the function bfq_weights_tree_add() for considerations
-+ * about overhead.
-+ */
-+static void __bfq_weights_tree_remove(struct bfq_data *bfqd,
-+				      struct bfq_entity *entity,
-+				      struct rb_root *root)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+
-+	if (!entity->weight_counter)
-+		return;
-+
-+	BUG_ON(RB_EMPTY_ROOT(root));
-+	BUG_ON(entity->weight_counter->weight != entity->weight);
-+
-+	BUG_ON(!entity->weight_counter->num_active);
-+	entity->weight_counter->num_active--;
-+
-+	if (entity->weight_counter->num_active > 0)
-+		goto reset_entity_pointer;
-+
-+	rb_erase(&entity->weight_counter->weights_node, root);
-+	kfree(entity->weight_counter);
-+
-+reset_entity_pointer:
-+	entity->weight_counter = NULL;
-+	if (bfqq) {
-+		bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			     "[%s] weight %d symmetric %d",
-+			     __func__, entity->weight,
-+			     bfq_symmetric_scenario(bfqd));
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	} else {
-+		struct bfq_group *bfqg =
-+			container_of(entity, struct bfq_group, entity);
-+
-+		bfq_log_bfqg(bfqd, bfqg,
-+			     "[%s] weight %d symmetric %d",
-+			     __func__, entity->weight,
-+			     bfq_symmetric_scenario(bfqd));
-+#endif
-+	}
-+}
-+
-+/*
-+ * Invoke __bfq_weights_tree_remove on bfqq and all its inactive
-+ * parent entities.
-+ */
-+static void bfq_weights_tree_remove(struct bfq_data *bfqd,
-+				    struct bfq_queue *bfqq)
-+{
-+	struct bfq_entity *entity = bfqq->entity.parent;
-+
-+	__bfq_weights_tree_remove(bfqd, &bfqq->entity,
-+				  &bfqd->queue_weights_tree);
-+
-+	for_each_entity(entity) {
-+		struct bfq_sched_data *sd = entity->my_sched_data;
-+
-+		BUG_ON(entity->sched_data == NULL); /*
-+						     * It would mean
-+						     * that this is
-+						     * the root group.
-+						     */
-+
-+		if (sd->next_in_service || sd->in_service_entity) {
-+			/*
-+			 * entity is still active, because either
-+			 * next_in_service or in_service_entity is not
-+			 * NULL (see the comments on the definition of
-+			 * next_in_service for details on why
-+			 * in_service_entity must be checked too).
-+			 *
-+			 * As a consequence, the weight of entity is
-+			 * not to be removed. In addition, if entity
-+			 * is active, then its parent entities are
-+			 * active as well, and thus their weights are
-+			 * not to be removed either. In the end, this
-+			 * loop must stop here.
-+			 */
-+			break;
-+		}
-+		__bfq_weights_tree_remove(bfqd, entity,
-+					  &bfqd->group_weights_tree);
-+	}
-+}
-+
-+/*
-+ * Return expired entry, or NULL to just start from scratch in rbtree.
-+ */
-+static struct request *bfq_check_fifo(struct bfq_queue *bfqq,
-+				      struct request *last)
-+{
-+	struct request *rq;
-+
-+	if (bfq_bfqq_fifo_expire(bfqq))
-+		return NULL;
-+
-+	bfq_mark_bfqq_fifo_expire(bfqq);
-+
-+	rq = rq_entry_fifo(bfqq->fifo.next);
-+
-+	if (rq == last || ktime_get_ns() < rq->fifo_time)
-+		return NULL;
-+
-+	bfq_log_bfqq(bfqq->bfqd, bfqq, "returned %p", rq);
-+	BUG_ON(RB_EMPTY_NODE(&rq->rb_node));
-+	return rq;
-+}
-+
-+static struct request *bfq_find_next_rq(struct bfq_data *bfqd,
-+					struct bfq_queue *bfqq,
-+					struct request *last)
-+{
-+	struct rb_node *rbnext = rb_next(&last->rb_node);
-+	struct rb_node *rbprev = rb_prev(&last->rb_node);
-+	struct request *next, *prev = NULL;
-+
-+	BUG_ON(list_empty(&bfqq->fifo));
-+
-+	/* Follow expired path, else get first next available. */
-+	next = bfq_check_fifo(bfqq, last);
-+	if (next) {
-+		BUG_ON(next == last);
-+		return next;
-+	}
-+
-+	BUG_ON(RB_EMPTY_NODE(&last->rb_node));
-+
-+	if (rbprev)
-+		prev = rb_entry_rq(rbprev);
-+
-+	if (rbnext)
-+		next = rb_entry_rq(rbnext);
-+	else {
-+		rbnext = rb_first(&bfqq->sort_list);
-+		if (rbnext && rbnext != &last->rb_node)
-+			next = rb_entry_rq(rbnext);
-+	}
-+
-+	return bfq_choose_req(bfqd, next, prev, blk_rq_pos(last));
-+}
-+
-+/* see the definition of bfq_async_charge_factor for details */
-+static unsigned long bfq_serv_to_charge(struct request *rq,
-+					struct bfq_queue *bfqq)
-+{
-+	if (bfq_bfqq_sync(bfqq) || bfqq->wr_coeff > 1)
-+		return blk_rq_sectors(rq);
-+
-+	return blk_rq_sectors(rq) * bfq_async_charge_factor;
-+}
-+
-+/**
-+ * bfq_updated_next_req - update the queue after a new next_rq selection.
-+ * @bfqd: the device data the queue belongs to.
-+ * @bfqq: the queue to update.
-+ *
-+ * If the first request of a queue changes we make sure that the queue
-+ * has enough budget to serve at least its first request (if the
-+ * request has grown).  We do this because if the queue has not enough
-+ * budget for its first request, it has to go through two dispatch
-+ * rounds to actually get it dispatched.
-+ */
-+static void bfq_updated_next_req(struct bfq_data *bfqd,
-+				 struct bfq_queue *bfqq)
-+{
-+	struct bfq_entity *entity = &bfqq->entity;
-+	struct bfq_service_tree *st = bfq_entity_service_tree(entity);
-+	struct request *next_rq = bfqq->next_rq;
-+	unsigned long new_budget;
-+
-+	if (!next_rq)
-+		return;
-+
-+	if (bfqq == bfqd->in_service_queue)
-+		/*
-+		 * In order not to break guarantees, budgets cannot be
-+		 * changed after an entity has been selected.
-+		 */
-+		return;
-+
-+	BUG_ON(entity->tree != &st->active);
-+	BUG_ON(entity == entity->sched_data->in_service_entity);
-+
-+	new_budget = max_t(unsigned long, bfqq->max_budget,
-+			   bfq_serv_to_charge(next_rq, bfqq));
-+	if (entity->budget != new_budget) {
-+		entity->budget = new_budget;
-+		bfq_log_bfqq(bfqd, bfqq, "new budget %lu",
-+					 new_budget);
-+		bfq_requeue_bfqq(bfqd, bfqq, false);
-+	}
-+}
-+
-+static unsigned int bfq_wr_duration(struct bfq_data *bfqd)
-+{
-+	u64 dur;
-+
-+	if (bfqd->bfq_wr_max_time > 0)
-+		return bfqd->bfq_wr_max_time;
-+
-+	dur = bfqd->rate_dur_prod;
-+	do_div(dur, bfqd->peak_rate);
-+
-+	/*
-+	 * Limit duration between 3 and 25 seconds. The upper limit
-+	 * has been conservatively set after the following worst case:
-+	 * on a QEMU/KVM virtual machine
-+	 * - running in a slow PC
-+	 * - with a virtual disk stacked on a slow low-end 5400rpm HDD
-+	 * - serving a heavy I/O workload, such as the sequential reading
-+	 *   of several files
-+	 * mplayer took 23 seconds to start, if constantly weight-raised.
-+	 *
-+	 * As for higher values than that accomodating the above bad
-+	 * scenario, tests show that higher values would often yield
-+	 * the opposite of the desired result, i.e., would worsen
-+	 * responsiveness by allowing non-interactive applications to
-+	 * preserve weight raising for too long.
-+	 *
-+	 * On the other end, lower values than 3 seconds make it
-+	 * difficult for most interactive tasks to complete their jobs
-+	 * before weight-raising finishes.
-+	 */
-+	return clamp_val(dur, msecs_to_jiffies(3000), msecs_to_jiffies(25000));
-+}
-+
-+/* switch back from soft real-time to interactive weight raising */
-+static void switch_back_to_interactive_wr(struct bfq_queue *bfqq,
-+					  struct bfq_data *bfqd)
-+{
-+	bfqq->wr_coeff = bfqd->bfq_wr_coeff;
-+	bfqq->wr_cur_max_time = bfq_wr_duration(bfqd);
-+	bfqq->last_wr_start_finish = bfqq->wr_start_at_switch_to_srt;
-+}
-+
-+static void
-+bfq_bfqq_resume_state(struct bfq_queue *bfqq, struct bfq_data *bfqd,
-+		      struct bfq_io_cq *bic, bool bfq_already_existing)
-+{
-+	unsigned int old_wr_coeff;
-+	bool busy = bfq_already_existing && bfq_bfqq_busy(bfqq);
-+
-+	if (bic->saved_has_short_ttime)
-+		bfq_mark_bfqq_has_short_ttime(bfqq);
-+	else
-+		bfq_clear_bfqq_has_short_ttime(bfqq);
-+
-+	if (bic->saved_IO_bound)
-+		bfq_mark_bfqq_IO_bound(bfqq);
-+	else
-+		bfq_clear_bfqq_IO_bound(bfqq);
-+
-+	if (unlikely(busy))
-+		old_wr_coeff = bfqq->wr_coeff;
-+
-+	bfqq->ttime = bic->saved_ttime;
-+	bfqq->wr_coeff = bic->saved_wr_coeff;
-+	bfqq->wr_start_at_switch_to_srt = bic->saved_wr_start_at_switch_to_srt;
-+	BUG_ON(time_is_after_jiffies(bfqq->wr_start_at_switch_to_srt));
-+	bfqq->last_wr_start_finish = bic->saved_last_wr_start_finish;
-+	bfqq->wr_cur_max_time = bic->saved_wr_cur_max_time;
-+	BUG_ON(time_is_after_jiffies(bfqq->last_wr_start_finish));
-+
-+	bfq_log_bfqq(bfqq->bfqd, bfqq,
-+		     "bic %p wr_coeff %d start_finish %lu max_time %lu",
-+		     bic, bfqq->wr_coeff, bfqq->last_wr_start_finish,
-+		     bfqq->wr_cur_max_time);
-+
-+	if (bfqq->wr_coeff > 1 && (bfq_bfqq_in_large_burst(bfqq) ||
-+				   time_is_before_jiffies(bfqq->last_wr_start_finish +
-+							  bfqq->wr_cur_max_time))) {
-+		if (bfqq->wr_cur_max_time == bfqd->bfq_wr_rt_max_time &&
-+		    !bfq_bfqq_in_large_burst(bfqq) &&
-+		    time_is_after_eq_jiffies(bfqq->wr_start_at_switch_to_srt +
-+					     bfq_wr_duration(bfqd))) {
-+			switch_back_to_interactive_wr(bfqq, bfqd);
-+			bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			     "switching back to interactive");
-+		} else {
-+			bfqq->wr_coeff = 1;
-+			bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			     "switching off wr (%lu + %lu < %lu)",
-+			     bfqq->last_wr_start_finish, bfqq->wr_cur_max_time,
-+			     jiffies);
-+		}
-+	}
-+
-+	/* make sure weight will be updated, however we got here */
-+	bfqq->entity.prio_changed = 1;
-+
-+	if (likely(!busy))
-+		return;
-+
-+	if (old_wr_coeff == 1 && bfqq->wr_coeff > 1) {
-+		bfqd->wr_busy_queues++;
-+		BUG_ON(bfqd->wr_busy_queues > bfqd->busy_queues);
-+	} else if (old_wr_coeff > 1 && bfqq->wr_coeff == 1) {
-+		bfqd->wr_busy_queues--;
-+		BUG_ON(bfqd->wr_busy_queues < 0);
-+	}
-+}
-+
-+static int bfqq_process_refs(struct bfq_queue *bfqq)
-+{
-+	int process_refs, io_refs;
-+
-+	lockdep_assert_held(&bfqq->bfqd->lock);
-+
-+	io_refs = bfqq->allocated;
-+	process_refs = bfqq->ref - io_refs - bfqq->entity.on_st;
-+	BUG_ON(process_refs < 0);
-+	return process_refs;
-+}
-+
-+/* Empty burst list and add just bfqq (see comments to bfq_handle_burst) */
-+static void bfq_reset_burst_list(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	struct bfq_queue *item;
-+	struct hlist_node *n;
-+
-+	hlist_for_each_entry_safe(item, n, &bfqd->burst_list, burst_list_node)
-+		hlist_del_init(&item->burst_list_node);
-+	hlist_add_head(&bfqq->burst_list_node, &bfqd->burst_list);
-+	bfqd->burst_size = 1;
-+	bfqd->burst_parent_entity = bfqq->entity.parent;
-+}
-+
-+/* Add bfqq to the list of queues in current burst (see bfq_handle_burst) */
-+static void bfq_add_to_burst(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	/* Increment burst size to take into account also bfqq */
-+	bfqd->burst_size++;
-+
-+	bfq_log_bfqq(bfqd, bfqq, "%d", bfqd->burst_size);
-+
-+	BUG_ON(bfqd->burst_size > bfqd->bfq_large_burst_thresh);
-+
-+	if (bfqd->burst_size == bfqd->bfq_large_burst_thresh) {
-+		struct bfq_queue *pos, *bfqq_item;
-+		struct hlist_node *n;
-+
-+		/*
-+		 * Enough queues have been activated shortly after each
-+		 * other to consider this burst as large.
-+		 */
-+		bfqd->large_burst = true;
-+		bfq_log_bfqq(bfqd, bfqq, "large burst started");
-+
-+		/*
-+		 * We can now mark all queues in the burst list as
-+		 * belonging to a large burst.
-+		 */
-+		hlist_for_each_entry(bfqq_item, &bfqd->burst_list,
-+				     burst_list_node) {
-+			bfq_mark_bfqq_in_large_burst(bfqq_item);
-+			bfq_log_bfqq(bfqd, bfqq_item, "marked in large burst");
-+		}
-+		bfq_mark_bfqq_in_large_burst(bfqq);
-+		bfq_log_bfqq(bfqd, bfqq, "marked in large burst");
-+
-+		/*
-+		 * From now on, and until the current burst finishes, any
-+		 * new queue being activated shortly after the last queue
-+		 * was inserted in the burst can be immediately marked as
-+		 * belonging to a large burst. So the burst list is not
-+		 * needed any more. Remove it.
-+		 */
-+		hlist_for_each_entry_safe(pos, n, &bfqd->burst_list,
-+					  burst_list_node)
-+			hlist_del_init(&pos->burst_list_node);
-+	} else /*
-+		* Burst not yet large: add bfqq to the burst list. Do
-+		* not increment the ref counter for bfqq, because bfqq
-+		* is removed from the burst list before freeing bfqq
-+		* in put_queue.
-+		*/
-+		hlist_add_head(&bfqq->burst_list_node, &bfqd->burst_list);
-+}
-+
-+/*
-+ * If many queues belonging to the same group happen to be created
-+ * shortly after each other, then the processes associated with these
-+ * queues have typically a common goal. In particular, bursts of queue
-+ * creations are usually caused by services or applications that spawn
-+ * many parallel threads/processes. Examples are systemd during boot,
-+ * or git grep. To help these processes get their job done as soon as
-+ * possible, it is usually better to not grant either weight-raising
-+ * or device idling to their queues.
-+ *
-+ * In this comment we describe, firstly, the reasons why this fact
-+ * holds, and, secondly, the next function, which implements the main
-+ * steps needed to properly mark these queues so that they can then be
-+ * treated in a different way.
-+ *
-+ * The above services or applications benefit mostly from a high
-+ * throughput: the quicker the requests of the activated queues are
-+ * cumulatively served, the sooner the target job of these queues gets
-+ * completed. As a consequence, weight-raising any of these queues,
-+ * which also implies idling the device for it, is almost always
-+ * counterproductive. In most cases it just lowers throughput.
-+ *
-+ * On the other hand, a burst of queue creations may be caused also by
-+ * the start of an application that does not consist of a lot of
-+ * parallel I/O-bound threads. In fact, with a complex application,
-+ * several short processes may need to be executed to start-up the
-+ * application. In this respect, to start an application as quickly as
-+ * possible, the best thing to do is in any case to privilege the I/O
-+ * related to the application with respect to all other
-+ * I/O. Therefore, the best strategy to start as quickly as possible
-+ * an application that causes a burst of queue creations is to
-+ * weight-raise all the queues created during the burst. This is the
-+ * exact opposite of the best strategy for the other type of bursts.
-+ *
-+ * In the end, to take the best action for each of the two cases, the
-+ * two types of bursts need to be distinguished. Fortunately, this
-+ * seems relatively easy, by looking at the sizes of the bursts. In
-+ * particular, we found a threshold such that only bursts with a
-+ * larger size than that threshold are apparently caused by
-+ * services or commands such as systemd or git grep. For brevity,
-+ * hereafter we call just 'large' these bursts. BFQ *does not*
-+ * weight-raise queues whose creation occurs in a large burst. In
-+ * addition, for each of these queues BFQ performs or does not perform
-+ * idling depending on which choice boosts the throughput more. The
-+ * exact choice depends on the device and request pattern at
-+ * hand.
-+ *
-+ * Unfortunately, false positives may occur while an interactive task
-+ * is starting (e.g., an application is being started). The
-+ * consequence is that the queues associated with the task do not
-+ * enjoy weight raising as expected. Fortunately these false positives
-+ * are very rare. They typically occur if some service happens to
-+ * start doing I/O exactly when the interactive task starts.
-+ *
-+ * Turning back to the next function, it implements all the steps
-+ * needed to detect the occurrence of a large burst and to properly
-+ * mark all the queues belonging to it (so that they can then be
-+ * treated in a different way). This goal is achieved by maintaining a
-+ * "burst list" that holds, temporarily, the queues that belong to the
-+ * burst in progress. The list is then used to mark these queues as
-+ * belonging to a large burst if the burst does become large. The main
-+ * steps are the following.
-+ *
-+ * . when the very first queue is created, the queue is inserted into the
-+ *   list (as it could be the first queue in a possible burst)
-+ *
-+ * . if the current burst has not yet become large, and a queue Q that does
-+ *   not yet belong to the burst is activated shortly after the last time
-+ *   at which a new queue entered the burst list, then the function appends
-+ *   Q to the burst list
-+ *
-+ * . if, as a consequence of the previous step, the burst size reaches
-+ *   the large-burst threshold, then
-+ *
-+ *     . all the queues in the burst list are marked as belonging to a
-+ *       large burst
-+ *
-+ *     . the burst list is deleted; in fact, the burst list already served
-+ *       its purpose (keeping temporarily track of the queues in a burst,
-+ *       so as to be able to mark them as belonging to a large burst in the
-+ *       previous sub-step), and now is not needed any more
-+ *
-+ *     . the device enters a large-burst mode
-+ *
-+ * . if a queue Q that does not belong to the burst is created while
-+ *   the device is in large-burst mode and shortly after the last time
-+ *   at which a queue either entered the burst list or was marked as
-+ *   belonging to the current large burst, then Q is immediately marked
-+ *   as belonging to a large burst.
-+ *
-+ * . if a queue Q that does not belong to the burst is created a while
-+ *   later, i.e., not shortly after, than the last time at which a queue
-+ *   either entered the burst list or was marked as belonging to the
-+ *   current large burst, then the current burst is deemed as finished and:
-+ *
-+ *        . the large-burst mode is reset if set
-+ *
-+ *        . the burst list is emptied
-+ *
-+ *        . Q is inserted in the burst list, as Q may be the first queue
-+ *          in a possible new burst (then the burst list contains just Q
-+ *          after this step).
-+ */
-+static void bfq_handle_burst(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	/*
-+	 * If bfqq is already in the burst list or is part of a large
-+	 * burst, or finally has just been split, then there is
-+	 * nothing else to do.
-+	 */
-+	if (!hlist_unhashed(&bfqq->burst_list_node) ||
-+	    bfq_bfqq_in_large_burst(bfqq) ||
-+	    time_is_after_eq_jiffies(bfqq->split_time +
-+				     msecs_to_jiffies(10)))
-+		return;
-+
-+	/*
-+	 * If bfqq's creation happens late enough, or bfqq belongs to
-+	 * a different group than the burst group, then the current
-+	 * burst is finished, and related data structures must be
-+	 * reset.
-+	 *
-+	 * In this respect, consider the special case where bfqq is
-+	 * the very first queue created after BFQ is selected for this
-+	 * device. In this case, last_ins_in_burst and
-+	 * burst_parent_entity are not yet significant when we get
-+	 * here. But it is easy to verify that, whether or not the
-+	 * following condition is true, bfqq will end up being
-+	 * inserted into the burst list. In particular the list will
-+	 * happen to contain only bfqq. And this is exactly what has
-+	 * to happen, as bfqq may be the first queue of the first
-+	 * burst.
-+	 */
-+	if (time_is_before_jiffies(bfqd->last_ins_in_burst +
-+	    bfqd->bfq_burst_interval) ||
-+	    bfqq->entity.parent != bfqd->burst_parent_entity) {
-+		bfqd->large_burst = false;
-+		bfq_reset_burst_list(bfqd, bfqq);
-+		bfq_log_bfqq(bfqd, bfqq,
-+			"late activation or different group");
-+		goto end;
-+	}
-+
-+	/*
-+	 * If we get here, then bfqq is being activated shortly after the
-+	 * last queue. So, if the current burst is also large, we can mark
-+	 * bfqq as belonging to this large burst immediately.
-+	 */
-+	if (bfqd->large_burst) {
-+		bfq_log_bfqq(bfqd, bfqq, "marked in burst");
-+		bfq_mark_bfqq_in_large_burst(bfqq);
-+		goto end;
-+	}
-+
-+	/*
-+	 * If we get here, then a large-burst state has not yet been
-+	 * reached, but bfqq is being activated shortly after the last
-+	 * queue. Then we add bfqq to the burst.
-+	 */
-+	bfq_add_to_burst(bfqd, bfqq);
-+end:
-+	/*
-+	 * At this point, bfqq either has been added to the current
-+	 * burst or has caused the current burst to terminate and a
-+	 * possible new burst to start. In particular, in the second
-+	 * case, bfqq has become the first queue in the possible new
-+	 * burst.  In both cases last_ins_in_burst needs to be moved
-+	 * forward.
-+	 */
-+	bfqd->last_ins_in_burst = jiffies;
-+
-+}
-+
-+static int bfq_bfqq_budget_left(struct bfq_queue *bfqq)
-+{
-+	struct bfq_entity *entity = &bfqq->entity;
-+
-+	if (entity->budget < entity->service) {
-+		pr_crit("budget %d service %d\n",
-+			entity->budget, entity->service);
-+		BUG();
-+	}
-+	return entity->budget - entity->service;
-+}
-+
-+/*
-+ * If enough samples have been computed, return the current max budget
-+ * stored in bfqd, which is dynamically updated according to the
-+ * estimated disk peak rate; otherwise return the default max budget
-+ */
-+static int bfq_max_budget(struct bfq_data *bfqd)
-+{
-+	if (bfqd->budgets_assigned < bfq_stats_min_budgets)
-+		return bfq_default_max_budget;
-+	else
-+		return bfqd->bfq_max_budget;
-+}
-+
-+/*
-+ * Return min budget, which is a fraction of the current or default
-+ * max budget (trying with 1/32)
-+ */
-+static int bfq_min_budget(struct bfq_data *bfqd)
-+{
-+	if (bfqd->budgets_assigned < bfq_stats_min_budgets)
-+		return bfq_default_max_budget / 32;
-+	else
-+		return bfqd->bfq_max_budget / 32;
-+}
-+
-+static void bfq_bfqq_expire(struct bfq_data *bfqd,
-+			    struct bfq_queue *bfqq,
-+			    bool compensate,
-+			    enum bfqq_expiration reason);
-+
-+/*
-+ * The next function, invoked after the input queue bfqq switches from
-+ * idle to busy, updates the budget of bfqq. The function also tells
-+ * whether the in-service queue should be expired, by returning
-+ * true. The purpose of expiring the in-service queue is to give bfqq
-+ * the chance to possibly preempt the in-service queue, and the reason
-+ * for preempting the in-service queue is to achieve one of the two
-+ * goals below.
-+ *
-+ * 1. Guarantee to bfqq its reserved bandwidth even if bfqq has
-+ * expired because it has remained idle. In particular, bfqq may have
-+ * expired for one of the following two reasons:
-+ *
-+ * - BFQ_BFQQ_NO_MORE_REQUEST bfqq did not enjoy any device idling and
-+ *   did not make it to issue a new request before its last request
-+ *   was served;
-+ *
-+ * - BFQ_BFQQ_TOO_IDLE bfqq did enjoy device idling, but did not issue
-+ *   a new request before the expiration of the idling-time.
-+ *
-+ * Even if bfqq has expired for one of the above reasons, the process
-+ * associated with the queue may be however issuing requests greedily,
-+ * and thus be sensitive to the bandwidth it receives (bfqq may have
-+ * remained idle for other reasons: CPU high load, bfqq not enjoying
-+ * idling, I/O throttling somewhere in the path from the process to
-+ * the I/O scheduler, ...). But if, after every expiration for one of
-+ * the above two reasons, bfqq has to wait for the service of at least
-+ * one full budget of another queue before being served again, then
-+ * bfqq is likely to get a much lower bandwidth or resource time than
-+ * its reserved ones. To address this issue, two countermeasures need
-+ * to be taken.
-+ *
-+ * First, the budget and the timestamps of bfqq need to be updated in
-+ * a special way on bfqq reactivation: they need to be updated as if
-+ * bfqq did not remain idle and did not expire. In fact, if they are
-+ * computed as if bfqq expired and remained idle until reactivation,
-+ * then the process associated with bfqq is treated as if, instead of
-+ * being greedy, it stopped issuing requests when bfqq remained idle,
-+ * and restarts issuing requests only on this reactivation. In other
-+ * words, the scheduler does not help the process recover the "service
-+ * hole" between bfqq expiration and reactivation. As a consequence,
-+ * the process receives a lower bandwidth than its reserved one. In
-+ * contrast, to recover this hole, the budget must be updated as if
-+ * bfqq was not expired at all before this reactivation, i.e., it must
-+ * be set to the value of the remaining budget when bfqq was
-+ * expired. Along the same line, timestamps need to be assigned the
-+ * value they had the last time bfqq was selected for service, i.e.,
-+ * before last expiration. Thus timestamps need to be back-shifted
-+ * with respect to their normal computation (see [1] for more details
-+ * on this tricky aspect).
-+ *
-+ * Secondly, to allow the process to recover the hole, the in-service
-+ * queue must be expired too, to give bfqq the chance to preempt it
-+ * immediately. In fact, if bfqq has to wait for a full budget of the
-+ * in-service queue to be completed, then it may become impossible to
-+ * let the process recover the hole, even if the back-shifted
-+ * timestamps of bfqq are lower than those of the in-service queue. If
-+ * this happens for most or all of the holes, then the process may not
-+ * receive its reserved bandwidth. In this respect, it is worth noting
-+ * that, being the service of outstanding requests unpreemptible, a
-+ * little fraction of the holes may however be unrecoverable, thereby
-+ * causing a little loss of bandwidth.
-+ *
-+ * The last important point is detecting whether bfqq does need this
-+ * bandwidth recovery. In this respect, the next function deems the
-+ * process associated with bfqq greedy, and thus allows it to recover
-+ * the hole, if: 1) the process is waiting for the arrival of a new
-+ * request (which implies that bfqq expired for one of the above two
-+ * reasons), and 2) such a request has arrived soon. The first
-+ * condition is controlled through the flag non_blocking_wait_rq,
-+ * while the second through the flag arrived_in_time. If both
-+ * conditions hold, then the function computes the budget in the
-+ * above-described special way, and signals that the in-service queue
-+ * should be expired. Timestamp back-shifting is done later in
-+ * __bfq_activate_entity.
-+ *
-+ * 2. Reduce latency. Even if timestamps are not backshifted to let
-+ * the process associated with bfqq recover a service hole, bfqq may
-+ * however happen to have, after being (re)activated, a lower finish
-+ * timestamp than the in-service queue.  That is, the next budget of
-+ * bfqq may have to be completed before the one of the in-service
-+ * queue. If this is the case, then preempting the in-service queue
-+ * allows this goal to be achieved, apart from the unpreemptible,
-+ * outstanding requests mentioned above.
-+ *
-+ * Unfortunately, regardless of which of the above two goals one wants
-+ * to achieve, service trees need first to be updated to know whether
-+ * the in-service queue must be preempted. To have service trees
-+ * correctly updated, the in-service queue must be expired and
-+ * rescheduled, and bfqq must be scheduled too. This is one of the
-+ * most costly operations (in future versions, the scheduling
-+ * mechanism may be re-designed in such a way to make it possible to
-+ * know whether preemption is needed without needing to update service
-+ * trees). In addition, queue preemptions almost always cause random
-+ * I/O, and thus loss of throughput. Because of these facts, the next
-+ * function adopts the following simple scheme to avoid both costly
-+ * operations and too frequent preemptions: it requests the expiration
-+ * of the in-service queue (unconditionally) only for queues that need
-+ * to recover a hole, or that either are weight-raised or deserve to
-+ * be weight-raised.
-+ */
-+static bool bfq_bfqq_update_budg_for_activation(struct bfq_data *bfqd,
-+						struct bfq_queue *bfqq,
-+						bool arrived_in_time,
-+						bool wr_or_deserves_wr)
-+{
-+	struct bfq_entity *entity = &bfqq->entity;
-+
-+	if (bfq_bfqq_non_blocking_wait_rq(bfqq) && arrived_in_time) {
-+		/*
-+		 * We do not clear the flag non_blocking_wait_rq here, as
-+		 * the latter is used in bfq_activate_bfqq to signal
-+		 * that timestamps need to be back-shifted (and is
-+		 * cleared right after).
-+		 */
-+
-+		/*
-+		 * In next assignment we rely on that either
-+		 * entity->service or entity->budget are not updated
-+		 * on expiration if bfqq is empty (see
-+		 * __bfq_bfqq_recalc_budget). Thus both quantities
-+		 * remain unchanged after such an expiration, and the
-+		 * following statement therefore assigns to
-+		 * entity->budget the remaining budget on such an
-+		 * expiration.
-+		 */
-+		BUG_ON(bfqq->max_budget < 0);
-+		entity->budget = min_t(unsigned long,
-+				       bfq_bfqq_budget_left(bfqq),
-+				       bfqq->max_budget);
-+
-+		BUG_ON(entity->budget < 0);
-+
-+		/*
-+		 * At this point, we have used entity->service to get
-+		 * the budget left (needed for updating
-+		 * entity->budget). Thus we finally can, and have to,
-+		 * reset entity->service. The latter must be reset
-+		 * because bfqq would otherwise be charged again for
-+		 * the service it has received during its previous
-+		 * service slot(s).
-+		 */
-+		entity->service = 0;
-+
-+		return true;
-+	}
-+
-+	/*
-+	 * We can finally complete expiration, by setting service to 0.
-+	 */
-+	entity->service = 0;
-+	BUG_ON(bfqq->max_budget < 0);
-+	entity->budget = max_t(unsigned long, bfqq->max_budget,
-+			       bfq_serv_to_charge(bfqq->next_rq, bfqq));
-+	BUG_ON(entity->budget < 0);
-+
-+	bfq_clear_bfqq_non_blocking_wait_rq(bfqq);
-+	return wr_or_deserves_wr;
-+}
-+
-+/*
-+ * Return the farthest past time instant according to jiffies
-+ * macros.
-+ */
-+static unsigned long bfq_smallest_from_now(void)
-+{
-+	return jiffies - MAX_JIFFY_OFFSET;
-+}
-+
-+static void bfq_update_bfqq_wr_on_rq_arrival(struct bfq_data *bfqd,
-+					     struct bfq_queue *bfqq,
-+					     unsigned int old_wr_coeff,
-+					     bool wr_or_deserves_wr,
-+					     bool interactive,
-+					     bool in_burst,
-+					     bool soft_rt)
-+{
-+	if (old_wr_coeff == 1 && wr_or_deserves_wr) {
-+		/* start a weight-raising period */
-+		if (interactive) {
-+			bfqq->service_from_wr = 0;
-+			bfqq->wr_coeff = bfqd->bfq_wr_coeff;
-+			bfqq->wr_cur_max_time = bfq_wr_duration(bfqd);
-+		} else {
-+			/*
-+			 * No interactive weight raising in progress
-+			 * here: assign minus infinity to
-+			 * wr_start_at_switch_to_srt, to make sure
-+			 * that, at the end of the soft-real-time
-+			 * weight raising periods that is starting
-+			 * now, no interactive weight-raising period
-+			 * may be wrongly considered as still in
-+			 * progress (and thus actually started by
-+			 * mistake).
-+			 */
-+			bfqq->wr_start_at_switch_to_srt =
-+				bfq_smallest_from_now();
-+			bfqq->wr_coeff = bfqd->bfq_wr_coeff *
-+				BFQ_SOFTRT_WEIGHT_FACTOR;
-+			bfqq->wr_cur_max_time =
-+				bfqd->bfq_wr_rt_max_time;
-+		}
-+		/*
-+		 * If needed, further reduce budget to make sure it is
-+		 * close to bfqq's backlog, so as to reduce the
-+		 * scheduling-error component due to a too large
-+		 * budget. Do not care about throughput consequences,
-+		 * but only about latency. Finally, do not assign a
-+		 * too small budget either, to avoid increasing
-+		 * latency by causing too frequent expirations.
-+		 */
-+		bfqq->entity.budget = min_t(unsigned long,
-+					    bfqq->entity.budget,
-+					    2 * bfq_min_budget(bfqd));
-+
-+		bfq_log_bfqq(bfqd, bfqq,
-+			     "wrais starting at %lu, rais_max_time %u",
-+			     jiffies,
-+			     jiffies_to_msecs(bfqq->wr_cur_max_time));
-+	} else if (old_wr_coeff > 1) {
-+		if (interactive) { /* update wr coeff and duration */
-+			bfqq->wr_coeff = bfqd->bfq_wr_coeff;
-+			bfqq->wr_cur_max_time = bfq_wr_duration(bfqd);
-+		} else if (in_burst) {
-+			bfqq->wr_coeff = 1;
-+			bfq_log_bfqq(bfqd, bfqq,
-+				     "wrais ending at %lu, rais_max_time %u",
-+				     jiffies,
-+				     jiffies_to_msecs(bfqq->
-+						      wr_cur_max_time));
-+		} else if (soft_rt) {
-+			/*
-+			 * The application is now or still meeting the
-+			 * requirements for being deemed soft rt.  We
-+			 * can then correctly and safely (re)charge
-+			 * the weight-raising duration for the
-+			 * application with the weight-raising
-+			 * duration for soft rt applications.
-+			 *
-+			 * In particular, doing this recharge now, i.e.,
-+			 * before the weight-raising period for the
-+			 * application finishes, reduces the probability
-+			 * of the following negative scenario:
-+			 * 1) the weight of a soft rt application is
-+			 *    raised at startup (as for any newly
-+			 *    created application),
-+			 * 2) since the application is not interactive,
-+			 *    at a certain time weight-raising is
-+			 *    stopped for the application,
-+			 * 3) at that time the application happens to
-+			 *    still have pending requests, and hence
-+			 *    is destined to not have a chance to be
-+			 *    deemed soft rt before these requests are
-+			 *    completed (see the comments to the
-+			 *    function bfq_bfqq_softrt_next_start()
-+			 *    for details on soft rt detection),
-+			 * 4) these pending requests experience a high
-+			 *    latency because the application is not
-+			 *    weight-raised while they are pending.
-+			 */
-+			if (bfqq->wr_cur_max_time !=
-+				bfqd->bfq_wr_rt_max_time) {
-+				bfqq->wr_start_at_switch_to_srt =
-+					bfqq->last_wr_start_finish;
-+                BUG_ON(time_is_after_jiffies(bfqq->last_wr_start_finish));
-+
-+				bfqq->wr_cur_max_time =
-+					bfqd->bfq_wr_rt_max_time;
-+				bfqq->wr_coeff = bfqd->bfq_wr_coeff *
-+					BFQ_SOFTRT_WEIGHT_FACTOR;
-+				bfq_log_bfqq(bfqd, bfqq,
-+					     "switching to soft_rt wr");
-+			} else
-+				bfq_log_bfqq(bfqd, bfqq,
-+					"moving forward soft_rt wr duration");
-+			bfqq->last_wr_start_finish = jiffies;
-+		}
-+	}
-+}
-+
-+static bool bfq_bfqq_idle_for_long_time(struct bfq_data *bfqd,
-+					struct bfq_queue *bfqq)
-+{
-+	return bfqq->dispatched == 0 &&
-+		time_is_before_jiffies(
-+			bfqq->budget_timeout +
-+			bfqd->bfq_wr_min_idle_time);
-+}
-+
-+static void bfq_bfqq_handle_idle_busy_switch(struct bfq_data *bfqd,
-+					     struct bfq_queue *bfqq,
-+					     int old_wr_coeff,
-+					     struct request *rq,
-+					     bool *interactive)
-+{
-+	bool soft_rt, in_burst,	wr_or_deserves_wr,
-+		bfqq_wants_to_preempt,
-+		idle_for_long_time = bfq_bfqq_idle_for_long_time(bfqd, bfqq),
-+		/*
-+		 * See the comments on
-+		 * bfq_bfqq_update_budg_for_activation for
-+		 * details on the usage of the next variable.
-+		 */
-+		arrived_in_time =  ktime_get_ns() <=
-+			bfqq->ttime.last_end_request +
-+			bfqd->bfq_slice_idle * 3;
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+		     "bfq_add_request non-busy: "
-+		     "jiffies %lu, in_time %d, idle_long %d busyw %d "
-+		     "wr_coeff %u",
-+		     jiffies, arrived_in_time,
-+		     idle_for_long_time,
-+		     bfq_bfqq_non_blocking_wait_rq(bfqq),
-+		     old_wr_coeff);
-+
-+	BUG_ON(bfqq->entity.budget < bfqq->entity.service);
-+
-+	BUG_ON(bfqq == bfqd->in_service_queue);
-+
-+	/*
-+	 * bfqq deserves to be weight-raised if:
-+	 * - it is sync,
-+	 * - it does not belong to a large burst,
-+	 * - it has been idle for enough time or is soft real-time,
-+	 * - is linked to a bfq_io_cq (it is not shared in any sense)
-+	 */
-+	in_burst = bfq_bfqq_in_large_burst(bfqq);
-+	soft_rt = bfqd->bfq_wr_max_softrt_rate > 0 &&
-+		!in_burst &&
-+		time_is_before_jiffies(bfqq->soft_rt_next_start) &&
-+		bfqq->dispatched == 0;
-+	*interactive =
-+		!in_burst &&
-+		idle_for_long_time;
-+	wr_or_deserves_wr = bfqd->low_latency &&
-+		(bfqq->wr_coeff > 1 ||
-+		 (bfq_bfqq_sync(bfqq) &&
-+		  bfqq->bic && (*interactive || soft_rt)));
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+		     "bfq_add_request: "
-+		     "in_burst %d, "
-+		     "soft_rt %d (next %lu), inter %d, bic %p",
-+		     bfq_bfqq_in_large_burst(bfqq), soft_rt,
-+		     bfqq->soft_rt_next_start,
-+		     *interactive,
-+		     bfqq->bic);
-+
-+	/*
-+	 * Using the last flag, update budget and check whether bfqq
-+	 * may want to preempt the in-service queue.
-+	 */
-+	bfqq_wants_to_preempt =
-+		bfq_bfqq_update_budg_for_activation(bfqd, bfqq,
-+						    arrived_in_time,
-+						    wr_or_deserves_wr);
-+
-+	/*
-+	 * If bfqq happened to be activated in a burst, but has been
-+	 * idle for much more than an interactive queue, then we
-+	 * assume that, in the overall I/O initiated in the burst, the
-+	 * I/O associated with bfqq is finished. So bfqq does not need
-+	 * to be treated as a queue belonging to a burst
-+	 * anymore. Accordingly, we reset bfqq's in_large_burst flag
-+	 * if set, and remove bfqq from the burst list if it's
-+	 * there. We do not decrement burst_size, because the fact
-+	 * that bfqq does not need to belong to the burst list any
-+	 * more does not invalidate the fact that bfqq was created in
-+	 * a burst.
-+	 */
-+	if (likely(!bfq_bfqq_just_created(bfqq)) &&
-+	    idle_for_long_time &&
-+	    time_is_before_jiffies(
-+		    bfqq->budget_timeout +
-+		    msecs_to_jiffies(10000))) {
-+		hlist_del_init(&bfqq->burst_list_node);
-+		bfq_clear_bfqq_in_large_burst(bfqq);
-+	}
-+
-+	bfq_clear_bfqq_just_created(bfqq);
-+
-+	if (!bfq_bfqq_IO_bound(bfqq)) {
-+		if (arrived_in_time) {
-+			bfqq->requests_within_timer++;
-+			if (bfqq->requests_within_timer >=
-+			    bfqd->bfq_requests_within_timer)
-+				bfq_mark_bfqq_IO_bound(bfqq);
-+		} else
-+			bfqq->requests_within_timer = 0;
-+		bfq_log_bfqq(bfqd, bfqq, "requests in time %d",
-+			     bfqq->requests_within_timer);
-+	}
-+
-+	if (bfqd->low_latency) {
-+		if (unlikely(time_is_after_jiffies(bfqq->split_time)))
-+			/* wraparound */
-+			bfqq->split_time =
-+				jiffies - bfqd->bfq_wr_min_idle_time - 1;
-+
-+		if (time_is_before_jiffies(bfqq->split_time +
-+					   bfqd->bfq_wr_min_idle_time)) {
-+			bfq_update_bfqq_wr_on_rq_arrival(bfqd, bfqq,
-+							 old_wr_coeff,
-+							 wr_or_deserves_wr,
-+							 *interactive,
-+							 in_burst,
-+							 soft_rt);
-+
-+			if (old_wr_coeff != bfqq->wr_coeff)
-+				bfqq->entity.prio_changed = 1;
-+		}
-+	}
-+
-+	bfqq->last_idle_bklogged = jiffies;
-+	bfqq->service_from_backlogged = 0;
-+	bfq_clear_bfqq_softrt_update(bfqq);
-+
-+	bfq_add_bfqq_busy(bfqd, bfqq);
-+
-+	/*
-+	 * Expire in-service queue only if preemption may be needed
-+	 * for guarantees. In this respect, the function
-+	 * next_queue_may_preempt just checks a simple, necessary
-+	 * condition, and not a sufficient condition based on
-+	 * timestamps. In fact, for the latter condition to be
-+	 * evaluated, timestamps would need first to be updated, and
-+	 * this operation is quite costly (see the comments on the
-+	 * function bfq_bfqq_update_budg_for_activation).
-+	 */
-+	if (bfqd->in_service_queue && bfqq_wants_to_preempt &&
-+	    bfqd->in_service_queue->wr_coeff < bfqq->wr_coeff &&
-+	    next_queue_may_preempt(bfqd)) {
-+		struct bfq_queue *in_serv =
-+			bfqd->in_service_queue;
-+		BUG_ON(in_serv == bfqq);
-+
-+		bfq_bfqq_expire(bfqd, bfqd->in_service_queue,
-+				false, BFQ_BFQQ_PREEMPTED);
-+	}
-+}
-+
-+static void bfq_add_request(struct request *rq)
-+{
-+	struct bfq_queue *bfqq = RQ_BFQQ(rq);
-+	struct bfq_data *bfqd = bfqq->bfqd;
-+	struct request *next_rq, *prev;
-+	unsigned int old_wr_coeff = bfqq->wr_coeff;
-+	bool interactive = false;
-+
-+	bfq_log_bfqq(bfqd, bfqq, "size %u %s",
-+		     blk_rq_sectors(rq), rq_is_sync(rq) ? "S" : "A");
-+
-+	if (bfqq->wr_coeff > 1) /* queue is being weight-raised */
-+		bfq_log_bfqq(bfqd, bfqq,
-+			"raising period dur %u/%u msec, old coeff %u, w %d(%d)",
-+			jiffies_to_msecs(jiffies - bfqq->last_wr_start_finish),
-+			jiffies_to_msecs(bfqq->wr_cur_max_time),
-+			bfqq->wr_coeff,
-+			bfqq->entity.weight, bfqq->entity.orig_weight);
-+
-+	bfqq->queued[rq_is_sync(rq)]++;
-+	bfqd->queued++;
-+
-+	BUG_ON(!RQ_BFQQ(rq));
-+	BUG_ON(RQ_BFQQ(rq) != bfqq);
-+	WARN_ON(blk_rq_sectors(rq) == 0);
-+
-+	elv_rb_add(&bfqq->sort_list, rq);
-+
-+	/*
-+	 * Check if this request is a better next-to-serve candidate.
-+	 */
-+	prev = bfqq->next_rq;
-+	next_rq = bfq_choose_req(bfqd, bfqq->next_rq, rq, bfqd->last_position);
-+	BUG_ON(!next_rq);
-+	BUG_ON(!RQ_BFQQ(next_rq));
-+	BUG_ON(RQ_BFQQ(next_rq) != bfqq);
-+	bfqq->next_rq = next_rq;
-+
-+	/*
-+	 * Adjust priority tree position, if next_rq changes.
-+	 */
-+	if (prev != bfqq->next_rq)
-+		bfq_pos_tree_add_move(bfqd, bfqq);
-+
-+	if (!bfq_bfqq_busy(bfqq)) /* switching to busy ... */
-+		bfq_bfqq_handle_idle_busy_switch(bfqd, bfqq, old_wr_coeff,
-+						 rq, &interactive);
-+	else {
-+		if (bfqd->low_latency && old_wr_coeff == 1 && !rq_is_sync(rq) &&
-+		    time_is_before_jiffies(
-+				bfqq->last_wr_start_finish +
-+				bfqd->bfq_wr_min_inter_arr_async)) {
-+			bfqq->wr_coeff = bfqd->bfq_wr_coeff;
-+			bfqq->wr_cur_max_time = bfq_wr_duration(bfqd);
-+
-+			bfqd->wr_busy_queues++;
-+			BUG_ON(bfqd->wr_busy_queues > bfqd->busy_queues);
-+			bfqq->entity.prio_changed = 1;
-+			bfq_log_bfqq(bfqd, bfqq,
-+				     "non-idle wrais starting, "
-+				     "wr_max_time %u wr_busy %d",
-+				     jiffies_to_msecs(bfqq->wr_cur_max_time),
-+				     bfqd->wr_busy_queues);
-+		}
-+		if (prev != bfqq->next_rq)
-+			bfq_updated_next_req(bfqd, bfqq);
-+	}
-+
-+	/*
-+	 * Assign jiffies to last_wr_start_finish in the following
-+	 * cases:
-+	 *
-+	 * . if bfqq is not going to be weight-raised, because, for
-+	 *   non weight-raised queues, last_wr_start_finish stores the
-+	 *   arrival time of the last request; as of now, this piece
-+	 *   of information is used only for deciding whether to
-+	 *   weight-raise async queues
-+	 *
-+	 * . if bfqq is not weight-raised, because, if bfqq is now
-+	 *   switching to weight-raised, then last_wr_start_finish
-+	 *   stores the time when weight-raising starts
-+	 *
-+	 * . if bfqq is interactive, because, regardless of whether
-+	 *   bfqq is currently weight-raised, the weight-raising
-+	 *   period must start or restart (this case is considered
-+	 *   separately because it is not detected by the above
-+	 *   conditions, if bfqq is already weight-raised)
-+	 *
-+	 * last_wr_start_finish has to be updated also if bfqq is soft
-+	 * real-time, because the weight-raising period is constantly
-+	 * restarted on idle-to-busy transitions for these queues, but
-+	 * this is already done in bfq_bfqq_handle_idle_busy_switch if
-+	 * needed.
-+	 */
-+	if (bfqd->low_latency &&
-+		(old_wr_coeff == 1 || bfqq->wr_coeff == 1 || interactive))
-+		bfqq->last_wr_start_finish = jiffies;
-+}
-+
-+static struct request *bfq_find_rq_fmerge(struct bfq_data *bfqd,
-+					  struct bio *bio,
-+					  struct request_queue *q)
-+{
-+	struct bfq_queue *bfqq = bfqd->bio_bfqq;
-+
-+	BUG_ON(!bfqd->bio_bfqq_set);
-+
-+	if (bfqq)
-+		return elv_rb_find(&bfqq->sort_list, bio_end_sector(bio));
-+
-+	return NULL;
-+}
-+
-+static sector_t get_sdist(sector_t last_pos, struct request *rq)
-+{
-+	sector_t sdist = 0;
-+
-+	if (last_pos) {
-+		if (last_pos < blk_rq_pos(rq))
-+			sdist = blk_rq_pos(rq) - last_pos;
-+		else
-+			sdist = last_pos - blk_rq_pos(rq);
-+	}
-+
-+	return sdist;
-+}
-+
-+#if 0 /* Still not clear if we can do without next two functions */
-+static void bfq_activate_request(struct request_queue *q, struct request *rq)
-+{
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+	bfqd->rq_in_driver++;
-+}
-+
-+static void bfq_deactivate_request(struct request_queue *q, struct request *rq)
-+{
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+
-+	BUG_ON(bfqd->rq_in_driver == 0);
-+	bfqd->rq_in_driver--;
-+}
-+#endif
-+
-+static void bfq_remove_request(struct request_queue *q,
-+			       struct request *rq)
-+{
-+	struct bfq_queue *bfqq = RQ_BFQQ(rq);
-+	struct bfq_data *bfqd = bfqq->bfqd;
-+	const int sync = rq_is_sync(rq);
-+
-+	BUG_ON(bfqq->entity.service > bfqq->entity.budget);
-+
-+	if (bfqq->next_rq == rq) {
-+		bfqq->next_rq = bfq_find_next_rq(bfqd, bfqq, rq);
-+		if (bfqq->next_rq && !RQ_BFQQ(bfqq->next_rq)) {
-+			pr_crit("no bfqq! for next rq %p bfqq %p\n",
-+				bfqq->next_rq, bfqq);
-+		}
-+
-+		BUG_ON(bfqq->next_rq && !RQ_BFQQ(bfqq->next_rq));
-+		if (bfqq->next_rq && RQ_BFQQ(bfqq->next_rq) != bfqq) {
-+			pr_crit(
-+			"wrong bfqq! for next rq %p, rq_bfqq %p bfqq %p\n",
-+			bfqq->next_rq, RQ_BFQQ(bfqq->next_rq), bfqq);
-+		}
-+		BUG_ON(bfqq->next_rq && RQ_BFQQ(bfqq->next_rq) != bfqq);
-+
-+		bfq_updated_next_req(bfqd, bfqq);
-+	}
-+
-+	if (rq->queuelist.prev != &rq->queuelist)
-+		list_del_init(&rq->queuelist);
-+	BUG_ON(bfqq->queued[sync] == 0);
-+	bfqq->queued[sync]--;
-+	bfqd->queued--;
-+	elv_rb_del(&bfqq->sort_list, rq);
-+
-+	elv_rqhash_del(q, rq);
-+	if (q->last_merge == rq)
-+		q->last_merge = NULL;
-+
-+	if (RB_EMPTY_ROOT(&bfqq->sort_list)) {
-+		bfqq->next_rq = NULL;
-+
-+		BUG_ON(bfqq->entity.budget < 0);
-+
-+		if (bfq_bfqq_busy(bfqq) && bfqq != bfqd->in_service_queue) {
-+			BUG_ON(bfqq->ref < 2); /* referred by rq and on tree */
-+			bfq_del_bfqq_busy(bfqd, bfqq, false);
-+			/*
-+			 * bfqq emptied. In normal operation, when
-+			 * bfqq is empty, bfqq->entity.service and
-+			 * bfqq->entity.budget must contain,
-+			 * respectively, the service received and the
-+			 * budget used last time bfqq emptied. These
-+			 * facts do not hold in this case, as at least
-+			 * this last removal occurred while bfqq is
-+			 * not in service. To avoid inconsistencies,
-+			 * reset both bfqq->entity.service and
-+			 * bfqq->entity.budget, if bfqq has still a
-+			 * process that may issue I/O requests to it.
-+			 */
-+			bfqq->entity.budget = bfqq->entity.service = 0;
-+		}
-+
-+		/*
-+		 * Remove queue from request-position tree as it is empty.
-+		 */
-+		if (bfqq->pos_root) {
-+			rb_erase(&bfqq->pos_node, bfqq->pos_root);
-+			bfqq->pos_root = NULL;
-+		}
-+	} else {
-+		BUG_ON(!bfqq->next_rq);
-+		bfq_pos_tree_add_move(bfqd, bfqq);
-+	}
-+
-+	if (rq->cmd_flags & REQ_META) {
-+		BUG_ON(bfqq->meta_pending == 0);
-+		bfqq->meta_pending--;
-+	}
-+}
-+
-+static bool bfq_bio_merge(struct blk_mq_hw_ctx *hctx, struct bio *bio)
-+{
-+	struct request_queue *q = hctx->queue;
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+	struct request *free = NULL;
-+	/*
-+	 * bfq_bic_lookup grabs the queue_lock: invoke it now and
-+	 * store its return value for later use, to avoid nesting
-+	 * queue_lock inside the bfqd->lock. We assume that the bic
-+	 * returned by bfq_bic_lookup does not go away before
-+	 * bfqd->lock is taken.
-+	 */
-+	struct bfq_io_cq *bic = bfq_bic_lookup(bfqd, current->io_context, q);
-+	bool ret;
-+
-+	spin_lock_irq(&bfqd->lock);
-+
-+	if (bic)
-+		bfqd->bio_bfqq = bic_to_bfqq(bic, op_is_sync(bio->bi_opf));
-+	else
-+		bfqd->bio_bfqq = NULL;
-+	bfqd->bio_bic = bic;
-+	/* Set next flag just for testing purposes */
-+	bfqd->bio_bfqq_set = true;
-+
-+	ret = blk_mq_sched_try_merge(q, bio, &free);
-+
-+	/*
-+	 * XXX Not yet freeing without lock held, to avoid an
-+	 * inconsistency with respect to the lock-protected invocation
-+	 * of blk_mq_sched_try_insert_merge in bfq_bio_merge. Waiting
-+	 * for clarifications from Jens.
-+	 */
-+	if (free)
-+		blk_mq_free_request(free);
-+	bfqd->bio_bfqq_set = false;
-+	spin_unlock_irq(&bfqd->lock);
-+
-+	return ret;
-+}
-+
-+static int bfq_request_merge(struct request_queue *q, struct request **req,
-+			     struct bio *bio)
-+{
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+	struct request *__rq;
-+
-+	__rq = bfq_find_rq_fmerge(bfqd, bio, q);
-+	if (__rq && elv_bio_merge_ok(__rq, bio)) {
-+		*req = __rq;
-+		bfq_log(bfqd, "req %p", __rq);
-+
-+		return ELEVATOR_FRONT_MERGE;
-+	}
-+
-+	return ELEVATOR_NO_MERGE;
-+}
-+
-+static struct bfq_queue *bfq_init_rq(struct request *rq);
-+
-+static void bfq_request_merged(struct request_queue *q, struct request *req,
-+			       enum elv_merge type)
-+{
-+	BUG_ON(req->rq_flags & RQF_DISP_LIST);
-+
-+	if (type == ELEVATOR_FRONT_MERGE &&
-+	    rb_prev(&req->rb_node) &&
-+	    blk_rq_pos(req) <
-+	    blk_rq_pos(container_of(rb_prev(&req->rb_node),
-+				    struct request, rb_node))) {
-+		struct bfq_queue *bfqq = bfq_init_rq(req);
-+		struct bfq_data *bfqd = bfqq->bfqd;
-+		struct request *prev, *next_rq;
-+
-+		/* Reposition request in its sort_list */
-+		elv_rb_del(&bfqq->sort_list, req);
-+		BUG_ON(!RQ_BFQQ(req));
-+		BUG_ON(RQ_BFQQ(req) != bfqq);
-+		elv_rb_add(&bfqq->sort_list, req);
-+
-+		/* Choose next request to be served for bfqq */
-+		prev = bfqq->next_rq;
-+		next_rq = bfq_choose_req(bfqd, bfqq->next_rq, req,
-+					 bfqd->last_position);
-+		BUG_ON(!next_rq);
-+
-+		bfqq->next_rq = next_rq;
-+
-+		bfq_log_bfqq(bfqd, bfqq,
-+			"req %p prev %p next_rq %p bfqq %p",
-+			     req, prev, next_rq, bfqq);
-+
-+		/*
-+		 * If next_rq changes, update both the queue's budget to
-+		 * fit the new request and the queue's position in its
-+		 * rq_pos_tree.
-+		 */
-+		if (prev != bfqq->next_rq) {
-+			bfq_updated_next_req(bfqd, bfqq);
-+			bfq_pos_tree_add_move(bfqd, bfqq);
-+		}
-+	}
-+}
-+
-+/*
-+ * This function is called to notify the scheduler that the requests
-+ * rq and 'next' have been merged, with 'next' going away.  BFQ
-+ * exploits this hook to address the following issue: if 'next' has a
-+ * fifo_time lower that rq, then the fifo_time of rq must be set to
-+ * the value of 'next', to not forget the greater age of 'next'.
-+ *
-+ * NOTE: in this function we assume that rq is in a bfq_queue, basing
-+ * on that rq is picked from the hash table q->elevator->hash, which,
-+ * in its turn, is filled only with I/O requests present in
-+ * bfq_queues, while BFQ is in use for the request queue q. In fact,
-+ * the function that fills this hash table (elv_rqhash_add) is called
-+ * only by bfq_insert_request.
-+ */
-+static void bfq_requests_merged(struct request_queue *q, struct request *rq,
-+				struct request *next)
-+{
-+	struct bfq_queue *bfqq = bfq_init_rq(rq),
-+		*next_bfqq = bfq_init_rq(next);
-+
-+	BUG_ON(!RQ_BFQQ(rq));
-+	BUG_ON(!RQ_BFQQ(next)); /* this does not imply next is in a bfqq */
-+	BUG_ON(rq->rq_flags & RQF_DISP_LIST);
-+	BUG_ON(next->rq_flags & RQF_DISP_LIST);
-+
-+	lockdep_assert_held(&bfqq->bfqd->lock);
-+
-+	bfq_log_bfqq(bfqq->bfqd, bfqq,
-+		     "rq %p next %p bfqq %p next_bfqq %p",
-+		     rq, next, bfqq, next_bfqq);
-+
-+	/*
-+	 * If next and rq belong to the same bfq_queue and next is older
-+	 * than rq, then reposition rq in the fifo (by substituting next
-+	 * with rq). Otherwise, if next and rq belong to different
-+	 * bfq_queues, never reposition rq: in fact, we would have to
-+	 * reposition it with respect to next's position in its own fifo,
-+	 * which would most certainly be too expensive with respect to
-+	 * the benefits.
-+	 */
-+	if (bfqq == next_bfqq &&
-+	    !list_empty(&rq->queuelist) && !list_empty(&next->queuelist) &&
-+	    next->fifo_time < rq->fifo_time) {
-+		list_del_init(&rq->queuelist);
-+		list_replace_init(&next->queuelist, &rq->queuelist);
-+		rq->fifo_time = next->fifo_time;
-+	}
-+
-+	if (bfqq->next_rq == next)
-+		bfqq->next_rq = rq;
-+
-+	bfqg_stats_update_io_merged(bfqq_group(bfqq), next->cmd_flags);
-+}
-+
-+/* Must be called with bfqq != NULL */
-+static void bfq_bfqq_end_wr(struct bfq_queue *bfqq)
-+{
-+	BUG_ON(!bfqq);
-+
-+	if (bfq_bfqq_busy(bfqq)) {
-+		bfqq->bfqd->wr_busy_queues--;
-+		BUG_ON(bfqq->bfqd->wr_busy_queues < 0);
-+	}
-+	bfqq->wr_coeff = 1;
-+	bfqq->wr_cur_max_time = 0;
-+	bfqq->last_wr_start_finish = jiffies;
-+	/*
-+	 * Trigger a weight change on the next invocation of
-+	 * __bfq_entity_update_weight_prio.
-+	 */
-+	bfqq->entity.prio_changed = 1;
-+	bfq_log_bfqq(bfqq->bfqd, bfqq,
-+		     "wrais ending at %lu, rais_max_time %u",
-+		     bfqq->last_wr_start_finish,
-+		     jiffies_to_msecs(bfqq->wr_cur_max_time));
-+	bfq_log_bfqq(bfqq->bfqd, bfqq, "wr_busy %d",
-+		     bfqq->bfqd->wr_busy_queues);
-+}
-+
-+static void bfq_end_wr_async_queues(struct bfq_data *bfqd,
-+				    struct bfq_group *bfqg)
-+{
-+	int i, j;
-+
-+	for (i = 0; i < 2; i++)
-+		for (j = 0; j < IOPRIO_BE_NR; j++)
-+			if (bfqg->async_bfqq[i][j])
-+				bfq_bfqq_end_wr(bfqg->async_bfqq[i][j]);
-+	if (bfqg->async_idle_bfqq)
-+		bfq_bfqq_end_wr(bfqg->async_idle_bfqq);
-+}
-+
-+static void bfq_end_wr(struct bfq_data *bfqd)
-+{
-+	struct bfq_queue *bfqq;
-+
-+	spin_lock_irq(&bfqd->lock);
-+
-+	list_for_each_entry(bfqq, &bfqd->active_list, bfqq_list)
-+		bfq_bfqq_end_wr(bfqq);
-+	list_for_each_entry(bfqq, &bfqd->idle_list, bfqq_list)
-+		bfq_bfqq_end_wr(bfqq);
-+	bfq_end_wr_async(bfqd);
-+
-+	spin_unlock_irq(&bfqd->lock);
-+}
-+
-+static sector_t bfq_io_struct_pos(void *io_struct, bool request)
-+{
-+	if (request)
-+		return blk_rq_pos(io_struct);
-+	else
-+		return ((struct bio *)io_struct)->bi_iter.bi_sector;
-+}
-+
-+static int bfq_rq_close_to_sector(void *io_struct, bool request,
-+				  sector_t sector)
-+{
-+	return abs(bfq_io_struct_pos(io_struct, request) - sector) <=
-+	       BFQQ_CLOSE_THR;
-+}
-+
-+static struct bfq_queue *bfqq_find_close(struct bfq_data *bfqd,
-+					 struct bfq_queue *bfqq,
-+					 sector_t sector)
-+{
-+	struct rb_root *root = &bfq_bfqq_to_bfqg(bfqq)->rq_pos_tree;
-+	struct rb_node *parent, *node;
-+	struct bfq_queue *__bfqq;
-+
-+	if (RB_EMPTY_ROOT(root))
-+		return NULL;
-+
-+	/*
-+	 * First, if we find a request starting at the end of the last
-+	 * request, choose it.
-+	 */
-+	__bfqq = bfq_rq_pos_tree_lookup(bfqd, root, sector, &parent, NULL);
-+	if (__bfqq)
-+		return __bfqq;
-+
-+	/*
-+	 * If the exact sector wasn't found, the parent of the NULL leaf
-+	 * will contain the closest sector (rq_pos_tree sorted by
-+	 * next_request position).
-+	 */
-+	__bfqq = rb_entry(parent, struct bfq_queue, pos_node);
-+	if (bfq_rq_close_to_sector(__bfqq->next_rq, true, sector))
-+		return __bfqq;
-+
-+	if (blk_rq_pos(__bfqq->next_rq) < sector)
-+		node = rb_next(&__bfqq->pos_node);
-+	else
-+		node = rb_prev(&__bfqq->pos_node);
-+	if (!node)
-+		return NULL;
-+
-+	__bfqq = rb_entry(node, struct bfq_queue, pos_node);
-+	if (bfq_rq_close_to_sector(__bfqq->next_rq, true, sector))
-+		return __bfqq;
-+
-+	return NULL;
-+}
-+
-+static struct bfq_queue *bfq_find_close_cooperator(struct bfq_data *bfqd,
-+						   struct bfq_queue *cur_bfqq,
-+						   sector_t sector)
-+{
-+	struct bfq_queue *bfqq;
-+
-+	/*
-+	 * We shall notice if some of the queues are cooperating,
-+	 * e.g., working closely on the same area of the device. In
-+	 * that case, we can group them together and: 1) don't waste
-+	 * time idling, and 2) serve the union of their requests in
-+	 * the best possible order for throughput.
-+	 */
-+	bfqq = bfqq_find_close(bfqd, cur_bfqq, sector);
-+	if (!bfqq || bfqq == cur_bfqq)
-+		return NULL;
-+
-+	return bfqq;
-+}
-+
-+static struct bfq_queue *
-+bfq_setup_merge(struct bfq_queue *bfqq, struct bfq_queue *new_bfqq)
-+{
-+	int process_refs, new_process_refs;
-+	struct bfq_queue *__bfqq;
-+
-+	/*
-+	 * If there are no process references on the new_bfqq, then it is
-+	 * unsafe to follow the ->new_bfqq chain as other bfqq's in the chain
-+	 * may have dropped their last reference (not just their last process
-+	 * reference).
-+	 */
-+	if (!bfqq_process_refs(new_bfqq))
-+		return NULL;
-+
-+	/* Avoid a circular list and skip interim queue merges. */
-+	while ((__bfqq = new_bfqq->new_bfqq)) {
-+		if (__bfqq == bfqq)
-+			return NULL;
-+		new_bfqq = __bfqq;
-+	}
-+
-+	process_refs = bfqq_process_refs(bfqq);
-+	new_process_refs = bfqq_process_refs(new_bfqq);
-+	/*
-+	 * If the process for the bfqq has gone away, there is no
-+	 * sense in merging the queues.
-+	 */
-+	if (process_refs == 0 || new_process_refs == 0)
-+		return NULL;
-+
-+	bfq_log_bfqq(bfqq->bfqd, bfqq, "scheduling merge with queue %d",
-+		new_bfqq->pid);
-+
-+	/*
-+	 * Merging is just a redirection: the requests of the process
-+	 * owning one of the two queues are redirected to the other queue.
-+	 * The latter queue, in its turn, is set as shared if this is the
-+	 * first time that the requests of some process are redirected to
-+	 * it.
-+	 *
-+	 * We redirect bfqq to new_bfqq and not the opposite, because
-+	 * we are in the context of the process owning bfqq, thus we
-+	 * have the io_cq of this process. So we can immediately
-+	 * configure this io_cq to redirect the requests of the
-+	 * process to new_bfqq. In contrast, the io_cq of new_bfqq is
-+	 * not available any more (new_bfqq->bic == NULL).
-+	 *
-+	 * Anyway, even in case new_bfqq coincides with the in-service
-+	 * queue, redirecting requests the in-service queue is the
-+	 * best option, as we feed the in-service queue with new
-+	 * requests close to the last request served and, by doing so,
-+	 * are likely to increase the throughput.
-+	 */
-+	bfqq->new_bfqq = new_bfqq;
-+	new_bfqq->ref += process_refs;
-+	return new_bfqq;
-+}
-+
-+static bool bfq_may_be_close_cooperator(struct bfq_queue *bfqq,
-+					struct bfq_queue *new_bfqq)
-+{
-+	if (bfq_too_late_for_merging(new_bfqq)) {
-+		bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			     "too late for bfq%d to be merged",
-+				new_bfqq->pid);
-+		return false;
-+	}
-+
-+	if (bfq_class_idle(bfqq) || bfq_class_idle(new_bfqq) ||
-+	    (bfqq->ioprio_class != new_bfqq->ioprio_class))
-+		return false;
-+
-+	/*
-+	 * If either of the queues has already been detected as seeky,
-+	 * then merging it with the other queue is unlikely to lead to
-+	 * sequential I/O.
-+	 */
-+	if (BFQQ_SEEKY(bfqq) || BFQQ_SEEKY(new_bfqq))
-+		return false;
-+
-+	/*
-+	 * Interleaved I/O is known to be done by (some) applications
-+	 * only for reads, so it does not make sense to merge async
-+	 * queues.
-+	 */
-+	if (!bfq_bfqq_sync(bfqq) || !bfq_bfqq_sync(new_bfqq))
-+		return false;
-+
-+	return true;
-+}
-+
-+/*
-+ * Attempt to schedule a merge of bfqq with the currently in-service
-+ * queue or with a close queue among the scheduled queues.  Return
-+ * NULL if no merge was scheduled, a pointer to the shared bfq_queue
-+ * structure otherwise.
-+ *
-+ * The OOM queue is not allowed to participate to cooperation: in fact, since
-+ * the requests temporarily redirected to the OOM queue could be redirected
-+ * again to dedicated queues at any time, the state needed to correctly
-+ * handle merging with the OOM queue would be quite complex and expensive
-+ * to maintain. Besides, in such a critical condition as an out of memory,
-+ * the benefits of queue merging may be little relevant, or even negligible.
-+ *
-+ * WARNING: queue merging may impair fairness among non-weight raised
-+ * queues, for at least two reasons: 1) the original weight of a
-+ * merged queue may change during the merged state, 2) even being the
-+ * weight the same, a merged queue may be bloated with many more
-+ * requests than the ones produced by its originally-associated
-+ * process.
-+ */
-+static struct bfq_queue *
-+bfq_setup_cooperator(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+		     void *io_struct, bool request)
-+{
-+	struct bfq_queue *in_service_bfqq, *new_bfqq;
-+
-+	/*
-+	 * Prevent bfqq from being merged if it has been created too
-+	 * long ago. The idea is that true cooperating processes, and
-+	 * thus their associated bfq_queues, are supposed to be
-+	 * created shortly after each other. This is the case, e.g.,
-+	 * for KVM/QEMU and dump I/O threads. Basing on this
-+	 * assumption, the following filtering greatly reduces the
-+	 * probability that two non-cooperating processes, which just
-+	 * happen to do close I/O for some short time interval, have
-+	 * their queues merged by mistake.
-+	 */
-+	if (bfq_too_late_for_merging(bfqq)) {
-+		bfq_log_bfqq(bfqd, bfqq,
-+			     "would have looked for coop, but too late");
-+		return NULL;
-+	}
-+
-+	if (bfqq->new_bfqq)
-+		return bfqq->new_bfqq;
-+
-+	if (!io_struct || unlikely(bfqq == &bfqd->oom_bfqq))
-+		return NULL;
-+
-+	/* If there is only one backlogged queue, don't search. */
-+	if (bfqd->busy_queues == 1)
-+		return NULL;
-+
-+	in_service_bfqq = bfqd->in_service_queue;
-+
-+	if (in_service_bfqq && in_service_bfqq != bfqq &&
-+	    likely(in_service_bfqq != &bfqd->oom_bfqq) &&
-+	    bfq_rq_close_to_sector(io_struct, request, bfqd->last_position) &&
-+	    bfqq->entity.parent == in_service_bfqq->entity.parent &&
-+	    bfq_may_be_close_cooperator(bfqq, in_service_bfqq)) {
-+		new_bfqq = bfq_setup_merge(bfqq, in_service_bfqq);
-+		if (new_bfqq)
-+			return new_bfqq;
-+	}
-+	/*
-+	 * Check whether there is a cooperator among currently scheduled
-+	 * queues. The only thing we need is that the bio/request is not
-+	 * NULL, as we need it to establish whether a cooperator exists.
-+	 */
-+	new_bfqq = bfq_find_close_cooperator(bfqd, bfqq,
-+			bfq_io_struct_pos(io_struct, request));
-+
-+	BUG_ON(new_bfqq && bfqq->entity.parent != new_bfqq->entity.parent);
-+
-+	if (new_bfqq && likely(new_bfqq != &bfqd->oom_bfqq) &&
-+	    bfq_may_be_close_cooperator(bfqq, new_bfqq))
-+		return bfq_setup_merge(bfqq, new_bfqq);
-+
-+	return NULL;
-+}
-+
-+static void bfq_bfqq_save_state(struct bfq_queue *bfqq)
-+{
-+	struct bfq_io_cq *bic = bfqq->bic;
-+
-+	/*
-+	 * If !bfqq->bic, the queue is already shared or its requests
-+	 * have already been redirected to a shared queue; both idle window
-+	 * and weight raising state have already been saved. Do nothing.
-+	 */
-+	if (!bic)
-+		return;
-+
-+	bic->saved_ttime = bfqq->ttime;
-+	bic->saved_has_short_ttime = bfq_bfqq_has_short_ttime(bfqq);
-+	bic->saved_IO_bound = bfq_bfqq_IO_bound(bfqq);
-+	bic->saved_in_large_burst = bfq_bfqq_in_large_burst(bfqq);
-+	bic->was_in_burst_list = !hlist_unhashed(&bfqq->burst_list_node);
-+	if (unlikely(bfq_bfqq_just_created(bfqq) &&
-+		     !bfq_bfqq_in_large_burst(bfqq) &&
-+		     bfqq->bfqd->low_latency)) {
-+		/*
-+		 * bfqq being merged ritgh after being created: bfqq
-+		 * would have deserved interactive weight raising, but
-+		 * did not make it to be set in a weight-raised state,
-+		 * because of this early merge.  Store directly the
-+		 * weight-raising state that would have been assigned
-+		 * to bfqq, so that to avoid that bfqq unjustly fails
-+		 * to enjoy weight raising if split soon.
-+		 */
-+		bic->saved_wr_coeff = bfqq->bfqd->bfq_wr_coeff;
-+		bic->saved_wr_cur_max_time = bfq_wr_duration(bfqq->bfqd);
-+		bic->saved_last_wr_start_finish = jiffies;
-+	} else {
-+		bic->saved_wr_coeff = bfqq->wr_coeff;
-+		bic->saved_wr_start_at_switch_to_srt =
-+			bfqq->wr_start_at_switch_to_srt;
-+		bic->saved_last_wr_start_finish = bfqq->last_wr_start_finish;
-+		bic->saved_wr_cur_max_time = bfqq->wr_cur_max_time;
-+	}
-+	BUG_ON(time_is_after_jiffies(bfqq->last_wr_start_finish));
-+	bfq_log_bfqq(bfqq->bfqd, bfqq,
-+		     "bic %p wr_coeff %d start_finish %lu max_time %lu",
-+		     bic, bfqq->wr_coeff, bfqq->last_wr_start_finish,
-+		     bfqq->wr_cur_max_time);
-+}
-+
-+static void
-+bfq_merge_bfqqs(struct bfq_data *bfqd, struct bfq_io_cq *bic,
-+		struct bfq_queue *bfqq, struct bfq_queue *new_bfqq)
-+{
-+	bfq_log_bfqq(bfqd, bfqq, "merging with queue %lu",
-+		     (unsigned long) new_bfqq->pid);
-+	BUG_ON(bfqq->bic && bfqq->bic == new_bfqq->bic);
-+	/* Save weight raising and idle window of the merged queues */
-+	bfq_bfqq_save_state(bfqq);
-+	bfq_bfqq_save_state(new_bfqq);
-+
-+	if (bfq_bfqq_IO_bound(bfqq))
-+		bfq_mark_bfqq_IO_bound(new_bfqq);
-+	bfq_clear_bfqq_IO_bound(bfqq);
-+
-+	/*
-+	 * If bfqq is weight-raised, then let new_bfqq inherit
-+	 * weight-raising. To reduce false positives, neglect the case
-+	 * where bfqq has just been created, but has not yet made it
-+	 * to be weight-raised (which may happen because EQM may merge
-+	 * bfqq even before bfq_add_request is executed for the first
-+	 * time for bfqq). Handling this case would however be very
-+	 * easy, thanks to the flag just_created.
-+	 */
-+	if (new_bfqq->wr_coeff == 1 && bfqq->wr_coeff > 1) {
-+		new_bfqq->wr_coeff = bfqq->wr_coeff;
-+		new_bfqq->wr_cur_max_time = bfqq->wr_cur_max_time;
-+		new_bfqq->last_wr_start_finish = bfqq->last_wr_start_finish;
-+		new_bfqq->wr_start_at_switch_to_srt =
-+			bfqq->wr_start_at_switch_to_srt;
-+		if (bfq_bfqq_busy(new_bfqq)) {
-+			bfqd->wr_busy_queues++;
-+			BUG_ON(bfqd->wr_busy_queues > bfqd->busy_queues);
-+		}
-+
-+		new_bfqq->entity.prio_changed = 1;
-+		bfq_log_bfqq(bfqd, new_bfqq,
-+			     "wr start after merge with %d, rais_max_time %u",
-+			     bfqq->pid,
-+			     jiffies_to_msecs(bfqq->wr_cur_max_time));
-+	}
-+
-+	if (bfqq->wr_coeff > 1) { /* bfqq has given its wr to new_bfqq */
-+		bfqq->wr_coeff = 1;
-+		bfqq->entity.prio_changed = 1;
-+		if (bfq_bfqq_busy(bfqq)) {
-+			bfqd->wr_busy_queues--;
-+			BUG_ON(bfqd->wr_busy_queues < 0);
-+		}
-+
-+	}
-+
-+	bfq_log_bfqq(bfqd, new_bfqq, "wr_busy %d",
-+		     bfqd->wr_busy_queues);
-+
-+	/*
-+	 * Merge queues (that is, let bic redirect its requests to new_bfqq)
-+	 */
-+	bic_set_bfqq(bic, new_bfqq, 1);
-+	bfq_mark_bfqq_coop(new_bfqq);
-+	/*
-+	 * new_bfqq now belongs to at least two bics (it is a shared queue):
-+	 * set new_bfqq->bic to NULL. bfqq either:
-+	 * - does not belong to any bic any more, and hence bfqq->bic must
-+	 *   be set to NULL, or
-+	 * - is a queue whose owning bics have already been redirected to a
-+	 *   different queue, hence the queue is destined to not belong to
-+	 *   any bic soon and bfqq->bic is already NULL (therefore the next
-+	 *   assignment causes no harm).
-+	 */
-+	new_bfqq->bic = NULL;
-+	bfqq->bic = NULL;
-+	/* release process reference to bfqq */
-+	bfq_put_queue(bfqq);
-+}
-+
-+static bool bfq_allow_bio_merge(struct request_queue *q, struct request *rq,
-+				struct bio *bio)
-+{
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+	bool is_sync = op_is_sync(bio->bi_opf);
-+	struct bfq_queue *bfqq = bfqd->bio_bfqq, *new_bfqq;
-+
-+	assert_spin_locked(&bfqd->lock);
-+	/*
-+	 * Disallow merge of a sync bio into an async request.
-+	 */
-+	if (is_sync && !rq_is_sync(rq))
-+		return false;
-+
-+	/*
-+	 * Lookup the bfqq that this bio will be queued with. Allow
-+	 * merge only if rq is queued there.
-+	 */
-+	BUG_ON(!bfqd->bio_bfqq_set);
-+	if (!bfqq)
-+		return false;
-+
-+	/*
-+	 * We take advantage of this function to perform an early merge
-+	 * of the queues of possible cooperating processes.
-+	 */
-+	new_bfqq = bfq_setup_cooperator(bfqd, bfqq, bio, false);
-+	BUG_ON(new_bfqq == bfqq);
-+	if (new_bfqq) {
-+		/*
-+		 * bic still points to bfqq, then it has not yet been
-+		 * redirected to some other bfq_queue, and a queue
-+		 * merge beween bfqq and new_bfqq can be safely
-+		 * fulfillled, i.e., bic can be redirected to new_bfqq
-+		 * and bfqq can be put.
-+		 */
-+		bfq_merge_bfqqs(bfqd, bfqd->bio_bic, bfqq,
-+				new_bfqq);
-+		/*
-+		 * If we get here, bio will be queued into new_queue,
-+		 * so use new_bfqq to decide whether bio and rq can be
-+		 * merged.
-+		 */
-+		bfqq = new_bfqq;
-+
-+		/*
-+		 * Change also bqfd->bio_bfqq, as
-+		 * bfqd->bio_bic now points to new_bfqq, and
-+		 * this function may be invoked again (and then may
-+		 * use again bqfd->bio_bfqq).
-+		 */
-+		bfqd->bio_bfqq = bfqq;
-+	}
-+	return bfqq == RQ_BFQQ(rq);
-+}
-+
-+/*
-+ * Set the maximum time for the in-service queue to consume its
-+ * budget. This prevents seeky processes from lowering the throughput.
-+ * In practice, a time-slice service scheme is used with seeky
-+ * processes.
-+ */
-+static void bfq_set_budget_timeout(struct bfq_data *bfqd,
-+				   struct bfq_queue *bfqq)
-+{
-+	unsigned int timeout_coeff;
-+
-+	if (bfqq->wr_cur_max_time == bfqd->bfq_wr_rt_max_time)
-+		timeout_coeff = 1;
-+	else
-+		timeout_coeff = bfqq->entity.weight / bfqq->entity.orig_weight;
-+
-+	bfqd->last_budget_start = ktime_get();
-+
-+	bfqq->budget_timeout = jiffies +
-+		bfqd->bfq_timeout * timeout_coeff;
-+
-+	bfq_log_bfqq(bfqd, bfqq, "%u",
-+		jiffies_to_msecs(bfqd->bfq_timeout * timeout_coeff));
-+}
-+
-+static void __bfq_set_in_service_queue(struct bfq_data *bfqd,
-+				       struct bfq_queue *bfqq)
-+{
-+	if (bfqq) {
-+		bfq_clear_bfqq_fifo_expire(bfqq);
-+
-+		bfqd->budgets_assigned = (bfqd->budgets_assigned*7 + 256) / 8;
-+
-+		BUG_ON(bfqq == bfqd->in_service_queue);
-+		BUG_ON(RB_EMPTY_ROOT(&bfqq->sort_list));
-+
-+		if (time_is_before_jiffies(bfqq->last_wr_start_finish) &&
-+		    bfqq->wr_coeff > 1 &&
-+		    bfqq->wr_cur_max_time == bfqd->bfq_wr_rt_max_time &&
-+		    time_is_before_jiffies(bfqq->budget_timeout)) {
-+			/*
-+			 * For soft real-time queues, move the start
-+			 * of the weight-raising period forward by the
-+			 * time the queue has not received any
-+			 * service. Otherwise, a relatively long
-+			 * service delay is likely to cause the
-+			 * weight-raising period of the queue to end,
-+			 * because of the short duration of the
-+			 * weight-raising period of a soft real-time
-+			 * queue.  It is worth noting that this move
-+			 * is not so dangerous for the other queues,
-+			 * because soft real-time queues are not
-+			 * greedy.
-+			 *
-+			 * To not add a further variable, we use the
-+			 * overloaded field budget_timeout to
-+			 * determine for how long the queue has not
-+			 * received service, i.e., how much time has
-+			 * elapsed since the queue expired. However,
-+			 * this is a little imprecise, because
-+			 * budget_timeout is set to jiffies if bfqq
-+			 * not only expires, but also remains with no
-+			 * request.
-+			 */
-+			if (time_after(bfqq->budget_timeout,
-+				       bfqq->last_wr_start_finish))
-+				bfqq->last_wr_start_finish +=
-+					jiffies - bfqq->budget_timeout;
-+			else
-+				bfqq->last_wr_start_finish = jiffies;
-+
-+			if (time_is_after_jiffies(bfqq->last_wr_start_finish)) {
-+			       pr_crit(
-+			       "BFQ WARNING:last %lu budget %lu jiffies %lu",
-+			       bfqq->last_wr_start_finish,
-+			       bfqq->budget_timeout,
-+			       jiffies);
-+			       pr_crit("diff %lu", jiffies -
-+				       max_t(unsigned long,
-+					     bfqq->last_wr_start_finish,
-+					     bfqq->budget_timeout));
-+			       bfqq->last_wr_start_finish = jiffies;
-+			}
-+		}
-+
-+		bfq_set_budget_timeout(bfqd, bfqq);
-+		bfq_log_bfqq(bfqd, bfqq,
-+			     "cur-budget = %d",
-+			     bfqq->entity.budget);
-+	} else
-+		bfq_log(bfqd, "NULL");
-+
-+	bfqd->in_service_queue = bfqq;
-+}
-+
-+/*
-+ * Get and set a new queue for service.
-+ */
-+static struct bfq_queue *bfq_set_in_service_queue(struct bfq_data *bfqd)
-+{
-+	struct bfq_queue *bfqq = bfq_get_next_queue(bfqd);
-+
-+	__bfq_set_in_service_queue(bfqd, bfqq);
-+	return bfqq;
-+}
-+
-+static void bfq_arm_slice_timer(struct bfq_data *bfqd)
-+{
-+	struct bfq_queue *bfqq = bfqd->in_service_queue;
-+	u32 sl;
-+
-+	BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list));
-+
-+	bfq_mark_bfqq_wait_request(bfqq);
-+
-+	/*
-+	 * We don't want to idle for seeks, but we do want to allow
-+	 * fair distribution of slice time for a process doing back-to-back
-+	 * seeks. So allow a little bit of time for him to submit a new rq.
-+	 *
-+	 * To prevent processes with (partly) seeky workloads from
-+	 * being too ill-treated, grant them a small fraction of the
-+	 * assigned budget before reducing the waiting time to
-+	 * BFQ_MIN_TT. This happened to help reduce latency.
-+	 */
-+	sl = bfqd->bfq_slice_idle;
-+	/*
-+	 * Unless the queue is being weight-raised or the scenario is
-+	 * asymmetric, grant only minimum idle time if the queue
-+	 * is seeky. A long idling is preserved for a weight-raised
-+	 * queue, or, more in general, in an asymemtric scenario,
-+	 * because a long idling is needed for guaranteeing to a queue
-+	 * its reserved share of the throughput (in particular, it is
-+	 * needed if the queue has a higher weight than some other
-+	 * queue).
-+	 */
-+	if (BFQQ_SEEKY(bfqq) && bfqq->wr_coeff == 1 &&
-+	    bfq_symmetric_scenario(bfqd))
-+		sl = min_t(u32, sl, BFQ_MIN_TT);
-+
-+	bfqd->last_idling_start = ktime_get();
-+	hrtimer_start(&bfqd->idle_slice_timer, ns_to_ktime(sl),
-+		      HRTIMER_MODE_REL);
-+	bfqg_stats_set_start_idle_time(bfqq_group(bfqq));
-+	bfq_log(bfqd, "arm idle: %ld/%ld ms",
-+		sl / NSEC_PER_MSEC, bfqd->bfq_slice_idle / NSEC_PER_MSEC);
-+}
-+
-+/*
-+ * In autotuning mode, max_budget is dynamically recomputed as the
-+ * amount of sectors transferred in timeout at the estimated peak
-+ * rate. This enables BFQ to utilize a full timeslice with a full
-+ * budget, even if the in-service queue is served at peak rate. And
-+ * this maximises throughput with sequential workloads.
-+ */
-+static unsigned long bfq_calc_max_budget(struct bfq_data *bfqd)
-+{
-+	return (u64)bfqd->peak_rate * USEC_PER_MSEC *
-+		jiffies_to_msecs(bfqd->bfq_timeout)>>BFQ_RATE_SHIFT;
-+}
-+
-+/*
-+ * Update parameters related to throughput and responsiveness, as a
-+ * function of the estimated peak rate. See comments on
-+ * bfq_calc_max_budget(), and on the ref_wr_duration array.
-+ */
-+static void update_thr_responsiveness_params(struct bfq_data *bfqd)
-+{
-+	if (bfqd->bfq_user_max_budget == 0) {
-+		bfqd->bfq_max_budget =
-+			bfq_calc_max_budget(bfqd);
-+		BUG_ON(bfqd->bfq_max_budget < 0);
-+		bfq_log(bfqd, "new max_budget = %d",
-+			bfqd->bfq_max_budget);
-+	}
-+}
-+
-+static void bfq_reset_rate_computation(struct bfq_data *bfqd, struct request *rq)
-+{
-+	if (rq != NULL) { /* new rq dispatch now, reset accordingly */
-+		bfqd->last_dispatch = bfqd->first_dispatch = ktime_get_ns() ;
-+		bfqd->peak_rate_samples = 1;
-+		bfqd->sequential_samples = 0;
-+		bfqd->tot_sectors_dispatched = bfqd->last_rq_max_size =
-+			blk_rq_sectors(rq);
-+	} else /* no new rq dispatched, just reset the number of samples */
-+		bfqd->peak_rate_samples = 0; /* full re-init on next disp. */
-+
-+	bfq_log(bfqd,
-+		"at end, sample %u/%u tot_sects %llu",
-+		bfqd->peak_rate_samples, bfqd->sequential_samples,
-+		bfqd->tot_sectors_dispatched);
-+}
-+
-+static void bfq_update_rate_reset(struct bfq_data *bfqd, struct request *rq)
-+{
-+	u32 rate, weight, divisor;
-+
-+	/*
-+	 * For the convergence property to hold (see comments on
-+	 * bfq_update_peak_rate()) and for the assessment to be
-+	 * reliable, a minimum number of samples must be present, and
-+	 * a minimum amount of time must have elapsed. If not so, do
-+	 * not compute new rate. Just reset parameters, to get ready
-+	 * for a new evaluation attempt.
-+	 */
-+	if (bfqd->peak_rate_samples < BFQ_RATE_MIN_SAMPLES ||
-+	    bfqd->delta_from_first < BFQ_RATE_MIN_INTERVAL) {
-+		bfq_log(bfqd,
-+	"only resetting, delta_first %lluus samples %d",
-+			bfqd->delta_from_first>>10, bfqd->peak_rate_samples);
-+		goto reset_computation;
-+	}
-+
-+	/*
-+	 * If a new request completion has occurred after last
-+	 * dispatch, then, to approximate the rate at which requests
-+	 * have been served by the device, it is more precise to
-+	 * extend the observation interval to the last completion.
-+	 */
-+	bfqd->delta_from_first =
-+		max_t(u64, bfqd->delta_from_first,
-+		      bfqd->last_completion - bfqd->first_dispatch);
-+
-+	BUG_ON(bfqd->delta_from_first == 0);
-+	/*
-+	 * Rate computed in sects/usec, and not sects/nsec, for
-+	 * precision issues.
-+	 */
-+	rate = div64_ul(bfqd->tot_sectors_dispatched<<BFQ_RATE_SHIFT,
-+			div_u64(bfqd->delta_from_first, NSEC_PER_USEC));
-+
-+	bfq_log(bfqd,
-+"tot_sects %llu delta_first %lluus rate %llu sects/s (%d)",
-+		bfqd->tot_sectors_dispatched, bfqd->delta_from_first>>10,
-+		((USEC_PER_SEC*(u64)rate)>>BFQ_RATE_SHIFT),
-+		rate > 20<<BFQ_RATE_SHIFT);
-+
-+	/*
-+	 * Peak rate not updated if:
-+	 * - the percentage of sequential dispatches is below 3/4 of the
-+	 *   total, and rate is below the current estimated peak rate
-+	 * - rate is unreasonably high (> 20M sectors/sec)
-+	 */
-+	if ((bfqd->sequential_samples < (3 * bfqd->peak_rate_samples)>>2 &&
-+	     rate <= bfqd->peak_rate) ||
-+		rate > 20<<BFQ_RATE_SHIFT) {
-+		bfq_log(bfqd,
-+		"goto reset, samples %u/%u rate/peak %llu/%llu",
-+		bfqd->peak_rate_samples, bfqd->sequential_samples,
-+		((USEC_PER_SEC*(u64)rate)>>BFQ_RATE_SHIFT),
-+		((USEC_PER_SEC*(u64)bfqd->peak_rate)>>BFQ_RATE_SHIFT));
-+		goto reset_computation;
-+	} else {
-+		bfq_log(bfqd,
-+		"do update, samples %u/%u rate/peak %llu/%llu",
-+		bfqd->peak_rate_samples, bfqd->sequential_samples,
-+		((USEC_PER_SEC*(u64)rate)>>BFQ_RATE_SHIFT),
-+		((USEC_PER_SEC*(u64)bfqd->peak_rate)>>BFQ_RATE_SHIFT));
-+	}
-+
-+	/*
-+	 * We have to update the peak rate, at last! To this purpose,
-+	 * we use a low-pass filter. We compute the smoothing constant
-+	 * of the filter as a function of the 'weight' of the new
-+	 * measured rate.
-+	 *
-+	 * As can be seen in next formulas, we define this weight as a
-+	 * quantity proportional to how sequential the workload is,
-+	 * and to how long the observation time interval is.
-+	 *
-+	 * The weight runs from 0 to 8. The maximum value of the
-+	 * weight, 8, yields the minimum value for the smoothing
-+	 * constant. At this minimum value for the smoothing constant,
-+	 * the measured rate contributes for half of the next value of
-+	 * the estimated peak rate.
-+	 *
-+	 * So, the first step is to compute the weight as a function
-+	 * of how sequential the workload is. Note that the weight
-+	 * cannot reach 9, because bfqd->sequential_samples cannot
-+	 * become equal to bfqd->peak_rate_samples, which, in its
-+	 * turn, holds true because bfqd->sequential_samples is not
-+	 * incremented for the first sample.
-+	 */
-+	weight = (9 * bfqd->sequential_samples) / bfqd->peak_rate_samples;
-+
-+	/*
-+	 * Second step: further refine the weight as a function of the
-+	 * duration of the observation interval.
-+	 */
-+	weight = min_t(u32, 8,
-+		       div_u64(weight * bfqd->delta_from_first,
-+			       BFQ_RATE_REF_INTERVAL));
-+
-+	/*
-+	 * Divisor ranging from 10, for minimum weight, to 2, for
-+	 * maximum weight.
-+	 */
-+	divisor = 10 - weight;
-+	BUG_ON(divisor == 0);
-+
-+	/*
-+	 * Finally, update peak rate:
-+	 *
-+	 * peak_rate = peak_rate * (divisor-1) / divisor  +  rate / divisor
-+	 */
-+	bfqd->peak_rate *= divisor-1;
-+	bfqd->peak_rate /= divisor;
-+	rate /= divisor; /* smoothing constant alpha = 1/divisor */
-+
-+	bfq_log(bfqd,
-+		"divisor %d tmp_peak_rate %llu tmp_rate %u",
-+		divisor,
-+		((USEC_PER_SEC*(u64)bfqd->peak_rate)>>BFQ_RATE_SHIFT),
-+		(u32)((USEC_PER_SEC*(u64)rate)>>BFQ_RATE_SHIFT));
-+
-+	BUG_ON(bfqd->peak_rate == 0);
-+	BUG_ON(bfqd->peak_rate > 20<<BFQ_RATE_SHIFT);
-+
-+	bfqd->peak_rate += rate;
-+
-+	/*
-+	 * For a very slow device, bfqd->peak_rate can reach 0 (see
-+	 * the minimum representable values reported in the comments
-+	 * on BFQ_RATE_SHIFT). Push to 1 if this happens, to avoid
-+	 * divisions by zero where bfqd->peak_rate is used as a
-+	 * divisor.
-+	 */
-+	bfqd->peak_rate = max_t(u32, 1, bfqd->peak_rate);
-+
-+	update_thr_responsiveness_params(bfqd);
-+	BUG_ON(bfqd->peak_rate > 20<<BFQ_RATE_SHIFT);
-+
-+reset_computation:
-+	bfq_reset_rate_computation(bfqd, rq);
-+}
-+
-+/*
-+ * Update the read/write peak rate (the main quantity used for
-+ * auto-tuning, see update_thr_responsiveness_params()).
-+ *
-+ * It is not trivial to estimate the peak rate (correctly): because of
-+ * the presence of sw and hw queues between the scheduler and the
-+ * device components that finally serve I/O requests, it is hard to
-+ * say exactly when a given dispatched request is served inside the
-+ * device, and for how long. As a consequence, it is hard to know
-+ * precisely at what rate a given set of requests is actually served
-+ * by the device.
-+ *
-+ * On the opposite end, the dispatch time of any request is trivially
-+ * available, and, from this piece of information, the "dispatch rate"
-+ * of requests can be immediately computed. So, the idea in the next
-+ * function is to use what is known, namely request dispatch times
-+ * (plus, when useful, request completion times), to estimate what is
-+ * unknown, namely in-device request service rate.
-+ *
-+ * The main issue is that, because of the above facts, the rate at
-+ * which a certain set of requests is dispatched over a certain time
-+ * interval can vary greatly with respect to the rate at which the
-+ * same requests are then served. But, since the size of any
-+ * intermediate queue is limited, and the service scheme is lossless
-+ * (no request is silently dropped), the following obvious convergence
-+ * property holds: the number of requests dispatched MUST become
-+ * closer and closer to the number of requests completed as the
-+ * observation interval grows. This is the key property used in
-+ * the next function to estimate the peak service rate as a function
-+ * of the observed dispatch rate. The function assumes to be invoked
-+ * on every request dispatch.
-+ */
-+static void bfq_update_peak_rate(struct bfq_data *bfqd, struct request *rq)
-+{
-+	u64 now_ns = ktime_get_ns();
-+
-+	if (bfqd->peak_rate_samples == 0) { /* first dispatch */
-+		bfq_log(bfqd,
-+		"goto reset, samples %d",
-+				bfqd->peak_rate_samples) ;
-+		bfq_reset_rate_computation(bfqd, rq);
-+		goto update_last_values; /* will add one sample */
-+	}
-+
-+	/*
-+	 * Device idle for very long: the observation interval lasting
-+	 * up to this dispatch cannot be a valid observation interval
-+	 * for computing a new peak rate (similarly to the late-
-+	 * completion event in bfq_completed_request()). Go to
-+	 * update_rate_and_reset to have the following three steps
-+	 * taken:
-+	 * - close the observation interval at the last (previous)
-+	 *   request dispatch or completion
-+	 * - compute rate, if possible, for that observation interval
-+	 * - start a new observation interval with this dispatch
-+	 */
-+	if (now_ns - bfqd->last_dispatch > 100*NSEC_PER_MSEC &&
-+	    bfqd->rq_in_driver == 0) {
-+		bfq_log(bfqd,
-+"jumping to updating&resetting delta_last %lluus samples %d",
-+			(now_ns - bfqd->last_dispatch)>>10,
-+			bfqd->peak_rate_samples) ;
-+		goto update_rate_and_reset;
-+	}
-+
-+	/* Update sampling information */
-+	bfqd->peak_rate_samples++;
-+
-+	if ((bfqd->rq_in_driver > 0 ||
-+		now_ns - bfqd->last_completion < BFQ_MIN_TT)
-+	     && get_sdist(bfqd->last_position, rq) < BFQQ_SEEK_THR)
-+		bfqd->sequential_samples++;
-+
-+	bfqd->tot_sectors_dispatched += blk_rq_sectors(rq);
-+
-+	/* Reset max observed rq size every 32 dispatches */
-+	if (likely(bfqd->peak_rate_samples % 32))
-+		bfqd->last_rq_max_size =
-+			max_t(u32, blk_rq_sectors(rq), bfqd->last_rq_max_size);
-+	else
-+		bfqd->last_rq_max_size = blk_rq_sectors(rq);
-+
-+	bfqd->delta_from_first = now_ns - bfqd->first_dispatch;
-+
-+	bfq_log(bfqd,
-+	"added samples %u/%u tot_sects %llu delta_first %lluus",
-+		bfqd->peak_rate_samples, bfqd->sequential_samples,
-+		bfqd->tot_sectors_dispatched,
-+		bfqd->delta_from_first>>10);
-+
-+	/* Target observation interval not yet reached, go on sampling */
-+	if (bfqd->delta_from_first < BFQ_RATE_REF_INTERVAL)
-+		goto update_last_values;
-+
-+update_rate_and_reset:
-+	bfq_update_rate_reset(bfqd, rq);
-+update_last_values:
-+	bfqd->last_position = blk_rq_pos(rq) + blk_rq_sectors(rq);
-+	bfqd->last_dispatch = now_ns;
-+
-+	bfq_log(bfqd,
-+	"delta_first %lluus last_pos %llu peak_rate %llu",
-+		(now_ns - bfqd->first_dispatch)>>10,
-+		(unsigned long long) bfqd->last_position,
-+		((USEC_PER_SEC*(u64)bfqd->peak_rate)>>BFQ_RATE_SHIFT));
-+	bfq_log(bfqd,
-+	"samples at end %d", bfqd->peak_rate_samples);
-+}
-+
-+/*
-+ * Remove request from internal lists.
-+ */
-+static void bfq_dispatch_remove(struct request_queue *q, struct request *rq)
-+{
-+	struct bfq_queue *bfqq = RQ_BFQQ(rq);
-+
-+	/*
-+	 * For consistency, the next instruction should have been
-+	 * executed after removing the request from the queue and
-+	 * dispatching it.  We execute instead this instruction before
-+	 * bfq_remove_request() (and hence introduce a temporary
-+	 * inconsistency), for efficiency.  In fact, should this
-+	 * dispatch occur for a non in-service bfqq, this anticipated
-+	 * increment prevents two counters related to bfqq->dispatched
-+	 * from risking to be, first, uselessly decremented, and then
-+	 * incremented again when the (new) value of bfqq->dispatched
-+	 * happens to be taken into account.
-+	 */
-+	bfqq->dispatched++;
-+	bfq_update_peak_rate(q->elevator->elevator_data, rq);
-+
-+	bfq_remove_request(q, rq);
-+}
-+
-+static void __bfq_bfqq_expire(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	BUG_ON(bfqq != bfqd->in_service_queue);
-+
-+	/*
-+	 * If this bfqq is shared between multiple processes, check
-+	 * to make sure that those processes are still issuing I/Os
-+	 * within the mean seek distance. If not, it may be time to
-+	 * break the queues apart again.
-+	 */
-+	if (bfq_bfqq_coop(bfqq) && BFQQ_SEEKY(bfqq))
-+		bfq_mark_bfqq_split_coop(bfqq);
-+
-+	if (RB_EMPTY_ROOT(&bfqq->sort_list)) {
-+		if (bfqq->dispatched == 0)
-+			/*
-+			 * Overloading budget_timeout field to store
-+			 * the time at which the queue remains with no
-+			 * backlog and no outstanding request; used by
-+			 * the weight-raising mechanism.
-+			 */
-+			bfqq->budget_timeout = jiffies;
-+
-+		bfq_del_bfqq_busy(bfqd, bfqq, true);
-+	} else {
-+		bfq_requeue_bfqq(bfqd, bfqq, true);
-+		/*
-+		 * Resort priority tree of potential close cooperators.
-+		 */
-+		bfq_pos_tree_add_move(bfqd, bfqq);
-+	}
-+
-+	/*
-+	 * All in-service entities must have been properly deactivated
-+	 * or requeued before executing the next function, which
-+	 * resets all in-service entites as no more in service.
-+	 */
-+	__bfq_bfqd_reset_in_service(bfqd);
-+}
-+
-+/**
-+ * __bfq_bfqq_recalc_budget - try to adapt the budget to the @bfqq behavior.
-+ * @bfqd: device data.
-+ * @bfqq: queue to update.
-+ * @reason: reason for expiration.
-+ *
-+ * Handle the feedback on @bfqq budget at queue expiration.
-+ * See the body for detailed comments.
-+ */
-+static void __bfq_bfqq_recalc_budget(struct bfq_data *bfqd,
-+				     struct bfq_queue *bfqq,
-+				     enum bfqq_expiration reason)
-+{
-+	struct request *next_rq;
-+	int budget, min_budget;
-+
-+	BUG_ON(bfqq != bfqd->in_service_queue);
-+
-+	min_budget = bfq_min_budget(bfqd);
-+
-+	if (bfqq->wr_coeff == 1)
-+		budget = bfqq->max_budget;
-+	else /*
-+	      * Use a constant, low budget for weight-raised queues,
-+	      * to help achieve a low latency. Keep it slightly higher
-+	      * than the minimum possible budget, to cause a little
-+	      * bit fewer expirations.
-+	      */
-+		budget = 2 * min_budget;
-+
-+	bfq_log_bfqq(bfqd, bfqq, "last budg %d, budg left %d",
-+		bfqq->entity.budget, bfq_bfqq_budget_left(bfqq));
-+	bfq_log_bfqq(bfqd, bfqq, "last max_budg %d, min budg %d",
-+		budget, bfq_min_budget(bfqd));
-+	bfq_log_bfqq(bfqd, bfqq, "sync %d, seeky %d",
-+		bfq_bfqq_sync(bfqq), BFQQ_SEEKY(bfqd->in_service_queue));
-+
-+	if (bfq_bfqq_sync(bfqq) && bfqq->wr_coeff == 1) {
-+		switch (reason) {
-+		/*
-+		 * Caveat: in all the following cases we trade latency
-+		 * for throughput.
-+		 */
-+		case BFQ_BFQQ_TOO_IDLE:
-+			/*
-+			 * This is the only case where we may reduce
-+			 * the budget: if there is no request of the
-+			 * process still waiting for completion, then
-+			 * we assume (tentatively) that the timer has
-+			 * expired because the batch of requests of
-+			 * the process could have been served with a
-+			 * smaller budget.  Hence, betting that
-+			 * process will behave in the same way when it
-+			 * becomes backlogged again, we reduce its
-+			 * next budget.  As long as we guess right,
-+			 * this budget cut reduces the latency
-+			 * experienced by the process.
-+			 *
-+			 * However, if there are still outstanding
-+			 * requests, then the process may have not yet
-+			 * issued its next request just because it is
-+			 * still waiting for the completion of some of
-+			 * the still outstanding ones.  So in this
-+			 * subcase we do not reduce its budget, on the
-+			 * contrary we increase it to possibly boost
-+			 * the throughput, as discussed in the
-+			 * comments to the BUDGET_TIMEOUT case.
-+			 */
-+			if (bfqq->dispatched > 0) /* still outstanding reqs */
-+				budget = min(budget * 2, bfqd->bfq_max_budget);
-+			else {
-+				if (budget > 5 * min_budget)
-+					budget -= 4 * min_budget;
-+				else
-+					budget = min_budget;
-+			}
-+			break;
-+		case BFQ_BFQQ_BUDGET_TIMEOUT:
-+			/*
-+			 * We double the budget here because it gives
-+			 * the chance to boost the throughput if this
-+			 * is not a seeky process (and has bumped into
-+			 * this timeout because of, e.g., ZBR).
-+			 */
-+			budget = min(budget * 2, bfqd->bfq_max_budget);
-+			break;
-+		case BFQ_BFQQ_BUDGET_EXHAUSTED:
-+			/*
-+			 * The process still has backlog, and did not
-+			 * let either the budget timeout or the disk
-+			 * idling timeout expire. Hence it is not
-+			 * seeky, has a short thinktime and may be
-+			 * happy with a higher budget too. So
-+			 * definitely increase the budget of this good
-+			 * candidate to boost the disk throughput.
-+			 */
-+			budget = min(budget * 4, bfqd->bfq_max_budget);
-+			break;
-+		case BFQ_BFQQ_NO_MORE_REQUESTS:
-+			/*
-+			 * For queues that expire for this reason, it
-+			 * is particularly important to keep the
-+			 * budget close to the actual service they
-+			 * need. Doing so reduces the timestamp
-+			 * misalignment problem described in the
-+			 * comments in the body of
-+			 * __bfq_activate_entity. In fact, suppose
-+			 * that a queue systematically expires for
-+			 * BFQ_BFQQ_NO_MORE_REQUESTS and presents a
-+			 * new request in time to enjoy timestamp
-+			 * back-shifting. The larger the budget of the
-+			 * queue is with respect to the service the
-+			 * queue actually requests in each service
-+			 * slot, the more times the queue can be
-+			 * reactivated with the same virtual finish
-+			 * time. It follows that, even if this finish
-+			 * time is pushed to the system virtual time
-+			 * to reduce the consequent timestamp
-+			 * misalignment, the queue unjustly enjoys for
-+			 * many re-activations a lower finish time
-+			 * than all newly activated queues.
-+			 *
-+			 * The service needed by bfqq is measured
-+			 * quite precisely by bfqq->entity.service.
-+			 * Since bfqq does not enjoy device idling,
-+			 * bfqq->entity.service is equal to the number
-+			 * of sectors that the process associated with
-+			 * bfqq requested to read/write before waiting
-+			 * for request completions, or blocking for
-+			 * other reasons.
-+			 */
-+			budget = max_t(int, bfqq->entity.service, min_budget);
-+			break;
-+		default:
-+			return;
-+		}
-+	} else if (!bfq_bfqq_sync(bfqq))
-+		/*
-+		 * Async queues get always the maximum possible
-+		 * budget, as for them we do not care about latency
-+		 * (in addition, their ability to dispatch is limited
-+		 * by the charging factor).
-+		 */
-+		budget = bfqd->bfq_max_budget;
-+
-+	bfqq->max_budget = budget;
-+
-+	if (bfqd->budgets_assigned >= bfq_stats_min_budgets &&
-+	    !bfqd->bfq_user_max_budget)
-+		bfqq->max_budget = min(bfqq->max_budget, bfqd->bfq_max_budget);
-+
-+	/*
-+	 * If there is still backlog, then assign a new budget, making
-+	 * sure that it is large enough for the next request.  Since
-+	 * the finish time of bfqq must be kept in sync with the
-+	 * budget, be sure to call __bfq_bfqq_expire() *after* this
-+	 * update.
-+	 *
-+	 * If there is no backlog, then no need to update the budget;
-+	 * it will be updated on the arrival of a new request.
-+	 */
-+	next_rq = bfqq->next_rq;
-+	if (next_rq) {
-+		BUG_ON(reason == BFQ_BFQQ_TOO_IDLE ||
-+		       reason == BFQ_BFQQ_NO_MORE_REQUESTS);
-+		bfqq->entity.budget = max_t(unsigned long, bfqq->max_budget,
-+					    bfq_serv_to_charge(next_rq, bfqq));
-+		BUG_ON(!bfq_bfqq_busy(bfqq));
-+		BUG_ON(RB_EMPTY_ROOT(&bfqq->sort_list));
-+	}
-+
-+	bfq_log_bfqq(bfqd, bfqq, "head sect: %u, new budget %d",
-+			next_rq ? blk_rq_sectors(next_rq) : 0,
-+			bfqq->entity.budget);
-+}
-+
-+/*
-+ * Return true if the process associated with bfqq is "slow". The slow
-+ * flag is used, in addition to the budget timeout, to reduce the
-+ * amount of service provided to seeky processes, and thus reduce
-+ * their chances to lower the throughput. More details in the comments
-+ * on the function bfq_bfqq_expire().
-+ *
-+ * An important observation is in order: as discussed in the comments
-+ * on the function bfq_update_peak_rate(), with devices with internal
-+ * queues, it is hard if ever possible to know when and for how long
-+ * an I/O request is processed by the device (apart from the trivial
-+ * I/O pattern where a new request is dispatched only after the
-+ * previous one has been completed). This makes it hard to evaluate
-+ * the real rate at which the I/O requests of each bfq_queue are
-+ * served.  In fact, for an I/O scheduler like BFQ, serving a
-+ * bfq_queue means just dispatching its requests during its service
-+ * slot (i.e., until the budget of the queue is exhausted, or the
-+ * queue remains idle, or, finally, a timeout fires). But, during the
-+ * service slot of a bfq_queue, around 100 ms at most, the device may
-+ * be even still processing requests of bfq_queues served in previous
-+ * service slots. On the opposite end, the requests of the in-service
-+ * bfq_queue may be completed after the service slot of the queue
-+ * finishes.
-+ *
-+ * Anyway, unless more sophisticated solutions are used
-+ * (where possible), the sum of the sizes of the requests dispatched
-+ * during the service slot of a bfq_queue is probably the only
-+ * approximation available for the service received by the bfq_queue
-+ * during its service slot. And this sum is the quantity used in this
-+ * function to evaluate the I/O speed of a process.
-+ */
-+static bool bfq_bfqq_is_slow(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+				 bool compensate, enum bfqq_expiration reason,
-+				 unsigned long *delta_ms)
-+{
-+	ktime_t delta_ktime;
-+	u32 delta_usecs;
-+	bool slow = BFQQ_SEEKY(bfqq); /* if delta too short, use seekyness */
-+
-+	if (!bfq_bfqq_sync(bfqq))
-+		return false;
-+
-+	if (compensate)
-+		delta_ktime = bfqd->last_idling_start;
-+	else
-+		delta_ktime = ktime_get();
-+	delta_ktime = ktime_sub(delta_ktime, bfqd->last_budget_start);
-+	delta_usecs = ktime_to_us(delta_ktime);
-+
-+	/* don't use too short time intervals */
-+	if (delta_usecs < 1000) {
-+		if (blk_queue_nonrot(bfqd->queue))
-+			 /*
-+			  * give same worst-case guarantees as idling
-+			  * for seeky
-+			  */
-+			*delta_ms = BFQ_MIN_TT / NSEC_PER_MSEC;
-+		else /* charge at least one seek */
-+			*delta_ms = bfq_slice_idle / NSEC_PER_MSEC;
-+
-+		bfq_log(bfqd, "too short %u", delta_usecs);
-+
-+		return slow;
-+	}
-+
-+	*delta_ms = delta_usecs / USEC_PER_MSEC;
-+
-+	/*
-+	 * Use only long (> 20ms) intervals to filter out excessive
-+	 * spikes in service rate estimation.
-+	 */
-+	if (delta_usecs > 20000) {
-+		/*
-+		 * Caveat for rotational devices: processes doing I/O
-+		 * in the slower disk zones tend to be slow(er) even
-+		 * if not seeky. In this respect, the estimated peak
-+		 * rate is likely to be an average over the disk
-+		 * surface. Accordingly, to not be too harsh with
-+		 * unlucky processes, a process is deemed slow only if
-+		 * its rate has been lower than half of the estimated
-+		 * peak rate.
-+		 */
-+		slow = bfqq->entity.service < bfqd->bfq_max_budget / 2;
-+		bfq_log(bfqd, "relative rate %d/%d",
-+			bfqq->entity.service, bfqd->bfq_max_budget);
-+	}
-+
-+	bfq_log_bfqq(bfqd, bfqq, "slow %d", slow);
-+
-+	return slow;
-+}
-+
-+/*
-+ * To be deemed as soft real-time, an application must meet two
-+ * requirements. First, the application must not require an average
-+ * bandwidth higher than the approximate bandwidth required to playback or
-+ * record a compressed high-definition video.
-+ * The next function is invoked on the completion of the last request of a
-+ * batch, to compute the next-start time instant, soft_rt_next_start, such
-+ * that, if the next request of the application does not arrive before
-+ * soft_rt_next_start, then the above requirement on the bandwidth is met.
-+ *
-+ * The second requirement is that the request pattern of the application is
-+ * isochronous, i.e., that, after issuing a request or a batch of requests,
-+ * the application stops issuing new requests until all its pending requests
-+ * have been completed. After that, the application may issue a new batch,
-+ * and so on.
-+ * For this reason the next function is invoked to compute
-+ * soft_rt_next_start only for applications that meet this requirement,
-+ * whereas soft_rt_next_start is set to infinity for applications that do
-+ * not.
-+ *
-+ * Unfortunately, even a greedy (i.e., I/O-bound) application may
-+ * happen to meet, occasionally or systematically, both the above
-+ * bandwidth and isochrony requirements. This may happen at least in
-+ * the following circumstances. First, if the CPU load is high. The
-+ * application may stop issuing requests while the CPUs are busy
-+ * serving other processes, then restart, then stop again for a while,
-+ * and so on. The other circumstances are related to the storage
-+ * device: the storage device is highly loaded or reaches a low-enough
-+ * throughput with the I/O of the application (e.g., because the I/O
-+ * is random and/or the device is slow). In all these cases, the
-+ * I/O of the application may be simply slowed down enough to meet
-+ * the bandwidth and isochrony requirements. To reduce the probability
-+ * that greedy applications are deemed as soft real-time in these
-+ * corner cases, a further rule is used in the computation of
-+ * soft_rt_next_start: the return value of this function is forced to
-+ * be higher than the maximum between the following two quantities.
-+ *
-+ * (a) Current time plus: (1) the maximum time for which the arrival
-+ *     of a request is waited for when a sync queue becomes idle,
-+ *     namely bfqd->bfq_slice_idle, and (2) a few extra jiffies. We
-+ *     postpone for a moment the reason for adding a few extra
-+ *     jiffies; we get back to it after next item (b).  Lower-bounding
-+ *     the return value of this function with the current time plus
-+ *     bfqd->bfq_slice_idle tends to filter out greedy applications,
-+ *     because the latter issue their next request as soon as possible
-+ *     after the last one has been completed. In contrast, a soft
-+ *     real-time application spends some time processing data, after a
-+ *     batch of its requests has been completed.
-+ *
-+ * (b) Current value of bfqq->soft_rt_next_start. As pointed out
-+ *     above, greedy applications may happen to meet both the
-+ *     bandwidth and isochrony requirements under heavy CPU or
-+ *     storage-device load. In more detail, in these scenarios, these
-+ *     applications happen, only for limited time periods, to do I/O
-+ *     slowly enough to meet all the requirements described so far,
-+ *     including the filtering in above item (a). These slow-speed
-+ *     time intervals are usually interspersed between other time
-+ *     intervals during which these applications do I/O at a very high
-+ *     speed. Fortunately, exactly because of the high speed of the
-+ *     I/O in the high-speed intervals, the values returned by this
-+ *     function happen to be so high, near the end of any such
-+ *     high-speed interval, to be likely to fall *after* the end of
-+ *     the low-speed time interval that follows. These high values are
-+ *     stored in bfqq->soft_rt_next_start after each invocation of
-+ *     this function. As a consequence, if the last value of
-+ *     bfqq->soft_rt_next_start is constantly used to lower-bound the
-+ *     next value that this function may return, then, from the very
-+ *     beginning of a low-speed interval, bfqq->soft_rt_next_start is
-+ *     likely to be constantly kept so high that any I/O request
-+ *     issued during the low-speed interval is considered as arriving
-+ *     to soon for the application to be deemed as soft
-+ *     real-time. Then, in the high-speed interval that follows, the
-+ *     application will not be deemed as soft real-time, just because
-+ *     it will do I/O at a high speed. And so on.
-+ *
-+ * Getting back to the filtering in item (a), in the following two
-+ * cases this filtering might be easily passed by a greedy
-+ * application, if the reference quantity was just
-+ * bfqd->bfq_slice_idle:
-+ * 1) HZ is so low that the duration of a jiffy is comparable to or
-+ *    higher than bfqd->bfq_slice_idle. This happens, e.g., on slow
-+ *    devices with HZ=100. The time granularity may be so coarse
-+ *    that the approximation, in jiffies, of bfqd->bfq_slice_idle
-+ *    is rather lower than the exact value.
-+ * 2) jiffies, instead of increasing at a constant rate, may stop increasing
-+ *    for a while, then suddenly 'jump' by several units to recover the lost
-+ *    increments. This seems to happen, e.g., inside virtual machines.
-+ * To address this issue, in the filtering in (a) we do not use as a
-+ * reference time interval just bfqd->bfq_slice_idle, but
-+ * bfqd->bfq_slice_idle plus a few jiffies. In particular, we add the
-+ * minimum number of jiffies for which the filter seems to be quite
-+ * precise also in embedded systems and KVM/QEMU virtual machines.
-+ */
-+static unsigned long bfq_bfqq_softrt_next_start(struct bfq_data *bfqd,
-+						struct bfq_queue *bfqq)
-+{
-+	bfq_log_bfqq(bfqd, bfqq,
-+"service_blkg %lu soft_rate %u sects/sec interval %u",
-+		     bfqq->service_from_backlogged,
-+		     bfqd->bfq_wr_max_softrt_rate,
-+		     jiffies_to_msecs(HZ * bfqq->service_from_backlogged /
-+				      bfqd->bfq_wr_max_softrt_rate));
-+
-+	return max3(bfqq->soft_rt_next_start,
-+		    bfqq->last_idle_bklogged +
-+		    HZ * bfqq->service_from_backlogged /
-+		    bfqd->bfq_wr_max_softrt_rate,
-+		    jiffies + nsecs_to_jiffies(bfqq->bfqd->bfq_slice_idle) + 4);
-+}
-+
-+static bool bfq_bfqq_injectable(struct bfq_queue *bfqq)
-+{
-+	return BFQQ_SEEKY(bfqq) && bfqq->wr_coeff == 1 &&
-+		blk_queue_nonrot(bfqq->bfqd->queue) &&
-+		bfqq->bfqd->hw_tag;
-+}
-+
-+/**
-+ * bfq_bfqq_expire - expire a queue.
-+ * @bfqd: device owning the queue.
-+ * @bfqq: the queue to expire.
-+ * @compensate: if true, compensate for the time spent idling.
-+ * @reason: the reason causing the expiration.
-+ *
-+ * If the process associated with bfqq does slow I/O (e.g., because it
-+ * issues random requests), we charge bfqq with the time it has been
-+ * in service instead of the service it has received (see
-+ * bfq_bfqq_charge_time for details on how this goal is achieved). As
-+ * a consequence, bfqq will typically get higher timestamps upon
-+ * reactivation, and hence it will be rescheduled as if it had
-+ * received more service than what it has actually received. In the
-+ * end, bfqq receives less service in proportion to how slowly its
-+ * associated process consumes its budgets (and hence how seriously it
-+ * tends to lower the throughput). In addition, this time-charging
-+ * strategy guarantees time fairness among slow processes. In
-+ * contrast, if the process associated with bfqq is not slow, we
-+ * charge bfqq exactly with the service it has received.
-+ *
-+ * Charging time to the first type of queues and the exact service to
-+ * the other has the effect of using the WF2Q+ policy to schedule the
-+ * former on a timeslice basis, without violating service domain
-+ * guarantees among the latter.
-+ */
-+static void bfq_bfqq_expire(struct bfq_data *bfqd,
-+			    struct bfq_queue *bfqq,
-+			    bool compensate,
-+			    enum bfqq_expiration reason)
-+{
-+	bool slow;
-+	unsigned long delta = 0;
-+	struct bfq_entity *entity = &bfqq->entity;
-+	int ref;
-+
-+	BUG_ON(bfqq != bfqd->in_service_queue);
-+
-+	/*
-+	 * Check whether the process is slow (see bfq_bfqq_is_slow).
-+	 */
-+	slow = bfq_bfqq_is_slow(bfqd, bfqq, compensate, reason, &delta);
-+
-+	/*
-+	 * As above explained, charge slow (typically seeky) and
-+	 * timed-out queues with the time and not the service
-+	 * received, to favor sequential workloads.
-+	 *
-+	 * Processes doing I/O in the slower disk zones will tend to
-+	 * be slow(er) even if not seeky. Therefore, since the
-+	 * estimated peak rate is actually an average over the disk
-+	 * surface, these processes may timeout just for bad luck. To
-+	 * avoid punishing them, do not charge time to processes that
-+	 * succeeded in consuming at least 2/3 of their budget. This
-+	 * allows BFQ to preserve enough elasticity to still perform
-+	 * bandwidth, and not time, distribution with little unlucky
-+	 * or quasi-sequential processes.
-+	 */
-+	if (bfqq->wr_coeff == 1 &&
-+	    (slow ||
-+	     (reason == BFQ_BFQQ_BUDGET_TIMEOUT &&
-+	      bfq_bfqq_budget_left(bfqq) >=  entity->budget / 3)))
-+		bfq_bfqq_charge_time(bfqd, bfqq, delta);
-+
-+	BUG_ON(bfqq->entity.budget < bfqq->entity.service);
-+
-+	if (reason == BFQ_BFQQ_TOO_IDLE &&
-+	    entity->service <= 2 * entity->budget / 10)
-+		bfq_clear_bfqq_IO_bound(bfqq);
-+
-+	if (bfqd->low_latency && bfqq->wr_coeff == 1)
-+		bfqq->last_wr_start_finish = jiffies;
-+
-+	if (bfqd->low_latency && bfqd->bfq_wr_max_softrt_rate > 0 &&
-+	    RB_EMPTY_ROOT(&bfqq->sort_list)) {
-+		/*
-+		 * If we get here, and there are no outstanding
-+		 * requests, then the request pattern is isochronous
-+		 * (see the comments on the function
-+		 * bfq_bfqq_softrt_next_start()). Thus we can compute
-+		 * soft_rt_next_start. If, instead, the queue still
-+		 * has outstanding requests, then we have to wait for
-+		 * the completion of all the outstanding requests to
-+		 * discover whether the request pattern is actually
-+		 * isochronous.
-+		 */
-+		BUG_ON(bfqd->busy_queues < 1);
-+		if (bfqq->dispatched == 0) {
-+			bfqq->soft_rt_next_start =
-+				bfq_bfqq_softrt_next_start(bfqd, bfqq);
-+			bfq_log_bfqq(bfqd, bfqq, "new soft_rt_next %lu",
-+				     bfqq->soft_rt_next_start);
-+		} else {
-+			/*
-+			 * Schedule an update of soft_rt_next_start to when
-+			 * the task may be discovered to be isochronous.
-+			 */
-+			bfq_mark_bfqq_softrt_update(bfqq);
-+		}
-+	}
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+	"expire (%s, slow %d, num_disp %d, short %d, weight %d, serv %d/%d)",
-+		     reason_name[reason], slow, bfqq->dispatched,
-+		     bfq_bfqq_has_short_ttime(bfqq), entity->weight,
-+		     entity->service, entity->budget);
-+
-+	/*
-+	 * Increase, decrease or leave budget unchanged according to
-+	 * reason.
-+	 */
-+	BUG_ON(bfqq->entity.budget < bfqq->entity.service);
-+	__bfq_bfqq_recalc_budget(bfqd, bfqq, reason);
-+	BUG_ON(bfqq->next_rq == NULL &&
-+	       bfqq->entity.budget < bfqq->entity.service);
-+	ref = bfqq->ref;
-+	__bfq_bfqq_expire(bfqd, bfqq);
-+
-+	if (ref == 1) /* bfqq is gone, no more actions on it */
-+		return;
-+
-+	BUG_ON(ref > 1 &&
-+	       !bfq_bfqq_busy(bfqq) && reason == BFQ_BFQQ_BUDGET_EXHAUSTED &&
-+		!bfq_class_idle(bfqq));
-+
-+	bfqq->injected_service = 0;
-+
-+	/* mark bfqq as waiting a request only if a bic still points to it */
-+	if (!bfq_bfqq_busy(bfqq) &&
-+	    reason != BFQ_BFQQ_BUDGET_TIMEOUT &&
-+	    reason != BFQ_BFQQ_BUDGET_EXHAUSTED) {
-+		BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list));
-+		BUG_ON(bfqq->next_rq);
-+		bfq_mark_bfqq_non_blocking_wait_rq(bfqq);
-+		/*
-+		 * Not setting service to 0, because, if the next rq
-+		 * arrives in time, the queue will go on receiving
-+		 * service with this same budget (as if it never expired)
-+		 */
-+	} else {
-+		entity->service = 0;
-+		bfq_log_bfqq(bfqd, bfqq, "[%s] resetting service", __func__);
-+	}
-+
-+	/*
-+	 * Reset the received-service counter for every parent entity.
-+	 * Differently from what happens with bfqq->entity.service,
-+	 * the resetting of this counter never needs to be postponed
-+	 * for parent entities. In fact, in case bfqq may have a
-+	 * chance to go on being served using the last, partially
-+	 * consumed budget, bfqq->entity.service needs to be kept,
-+	 * because if bfqq then actually goes on being served using
-+	 * the same budget, the last value of bfqq->entity.service is
-+	 * needed to properly decrement bfqq->entity.budget by the
-+	 * portion already consumed. In contrast, it is not necessary
-+	 * to keep entity->service for parent entities too, because
-+	 * the bubble up of the new value of bfqq->entity.budget will
-+	 * make sure that the budgets of parent entities are correct,
-+	 * even in case bfqq and thus parent entities go on receiving
-+	 * service with the same budget.
-+	 */
-+	entity = entity->parent;
-+	for_each_entity(entity)
-+		entity->service = 0;
-+}
-+
-+/*
-+ * Budget timeout is not implemented through a dedicated timer, but
-+ * just checked on request arrivals and completions, as well as on
-+ * idle timer expirations.
-+ */
-+static bool bfq_bfqq_budget_timeout(struct bfq_queue *bfqq)
-+{
-+	return time_is_before_eq_jiffies(bfqq->budget_timeout);
-+}
-+
-+/*
-+ * If we expire a queue that is actively waiting (i.e., with the
-+ * device idled) for the arrival of a new request, then we may incur
-+ * the timestamp misalignment problem described in the body of the
-+ * function __bfq_activate_entity. Hence we return true only if this
-+ * condition does not hold, or if the queue is slow enough to deserve
-+ * only to be kicked off for preserving a high throughput.
-+ */
-+static bool bfq_may_expire_for_budg_timeout(struct bfq_queue *bfqq)
-+{
-+	bfq_log_bfqq(bfqq->bfqd, bfqq,
-+		"wait_request %d left %d timeout %d",
-+		bfq_bfqq_wait_request(bfqq),
-+			bfq_bfqq_budget_left(bfqq) >=  bfqq->entity.budget / 3,
-+		bfq_bfqq_budget_timeout(bfqq));
-+
-+	return (!bfq_bfqq_wait_request(bfqq) ||
-+		bfq_bfqq_budget_left(bfqq) >=  bfqq->entity.budget / 3)
-+		&&
-+		bfq_bfqq_budget_timeout(bfqq);
-+}
-+
-+/*
-+ * For a queue that becomes empty, device idling is allowed only if
-+ * this function returns true for that queue. As a consequence, since
-+ * device idling plays a critical role for both throughput boosting
-+ * and service guarantees, the return value of this function plays a
-+ * critical role as well.
-+ *
-+ * In a nutshell, this function returns true only if idling is
-+ * beneficial for throughput or, even if detrimental for throughput,
-+ * idling is however necessary to preserve service guarantees (low
-+ * latency, desired throughput distribution, ...). In particular, on
-+ * NCQ-capable devices, this function tries to return false, so as to
-+ * help keep the drives' internal queues full, whenever this helps the
-+ * device boost the throughput without causing any service-guarantee
-+ * issue.
-+ *
-+ * In more detail, the return value of this function is obtained by,
-+ * first, computing a number of boolean variables that take into
-+ * account throughput and service-guarantee issues, and, then,
-+ * combining these variables in a logical expression. Most of the
-+ * issues taken into account are not trivial. We discuss these issues
-+ * while introducing the variables.
-+ */
-+static bool bfq_better_to_idle(struct bfq_queue *bfqq)
-+{
-+	struct bfq_data *bfqd = bfqq->bfqd;
-+	bool rot_without_queueing =
-+		!blk_queue_nonrot(bfqd->queue) && !bfqd->hw_tag,
-+		bfqq_sequential_and_IO_bound,
-+		idling_boosts_thr, idling_boosts_thr_without_issues,
-+		idling_needed_for_service_guarantees,
-+		asymmetric_scenario;
-+
-+	if (bfqd->strict_guarantees)
-+		return true;
-+
-+	/*
-+	 * Idling is performed only if slice_idle > 0. In addition, we
-+	 * do not idle if
-+	 * (a) bfqq is async
-+	 * (b) bfqq is in the idle io prio class: in this case we do
-+	 * not idle because we want to minimize the bandwidth that
-+	 * queues in this class can steal to higher-priority queues
-+	 */
-+	if (bfqd->bfq_slice_idle == 0 || !bfq_bfqq_sync(bfqq) ||
-+	   bfq_class_idle(bfqq))
-+		return false;
-+
-+	bfqq_sequential_and_IO_bound = !BFQQ_SEEKY(bfqq) &&
-+		bfq_bfqq_IO_bound(bfqq) && bfq_bfqq_has_short_ttime(bfqq);
-+	/*
-+	 * The next variable takes into account the cases where idling
-+	 * boosts the throughput.
-+	 *
-+	 * The value of the variable is computed considering, first, that
-+	 * idling is virtually always beneficial for the throughput if:
-+	 * (a) the device is not NCQ-capable and rotational, or
-+	 * (b) regardless of the presence of NCQ, the device is rotational and
-+	 *     the request pattern for bfqq is I/O-bound and sequential, or
-+	 * (c) regardless of whether it is rotational, the device is
-+	 *     not NCQ-capable and the request pattern for bfqq is
-+	 *     I/O-bound and sequential.
-+	 *
-+	 * Secondly, and in contrast to the above item (b), idling an
-+	 * NCQ-capable flash-based device would not boost the
-+	 * throughput even with sequential I/O; rather it would lower
-+	 * the throughput in proportion to how fast the device
-+	 * is. Accordingly, the next variable is true if any of the
-+	 * above conditions (a), (b) or (c) is true, and, in
-+	 * particular, happens to be false if bfqd is an NCQ-capable
-+	 * flash-based device.
-+	 */
-+	idling_boosts_thr = rot_without_queueing ||
-+		((!blk_queue_nonrot(bfqd->queue) || !bfqd->hw_tag) &&
-+		 bfqq_sequential_and_IO_bound);
-+
-+	/*
-+	 * The value of the next variable,
-+	 * idling_boosts_thr_without_issues, is equal to that of
-+	 * idling_boosts_thr, unless a special case holds. In this
-+	 * special case, described below, idling may cause problems to
-+	 * weight-raised queues.
-+	 *
-+	 * When the request pool is saturated (e.g., in the presence
-+	 * of write hogs), if the processes associated with
-+	 * non-weight-raised queues ask for requests at a lower rate,
-+	 * then processes associated with weight-raised queues have a
-+	 * higher probability to get a request from the pool
-+	 * immediately (or at least soon) when they need one. Thus
-+	 * they have a higher probability to actually get a fraction
-+	 * of the device throughput proportional to their high
-+	 * weight. This is especially true with NCQ-capable drives,
-+	 * which enqueue several requests in advance, and further
-+	 * reorder internally-queued requests.
-+	 *
-+	 * For this reason, we force to false the value of
-+	 * idling_boosts_thr_without_issues if there are weight-raised
-+	 * busy queues. In this case, and if bfqq is not weight-raised,
-+	 * this guarantees that the device is not idled for bfqq (if,
-+	 * instead, bfqq is weight-raised, then idling will be
-+	 * guaranteed by another variable, see below). Combined with
-+	 * the timestamping rules of BFQ (see [1] for details), this
-+	 * behavior causes bfqq, and hence any sync non-weight-raised
-+	 * queue, to get a lower number of requests served, and thus
-+	 * to ask for a lower number of requests from the request
-+	 * pool, before the busy weight-raised queues get served
-+	 * again. This often mitigates starvation problems in the
-+	 * presence of heavy write workloads and NCQ, thereby
-+	 * guaranteeing a higher application and system responsiveness
-+	 * in these hostile scenarios.
-+	 */
-+	idling_boosts_thr_without_issues = idling_boosts_thr &&
-+		bfqd->wr_busy_queues == 0;
-+
-+	/*
-+	 * There is then a case where idling must be performed not
-+	 * for throughput concerns, but to preserve service
-+	 * guarantees.
-+	 *
-+	 * To introduce this case, we can note that allowing the drive
-+	 * to enqueue more than one request at a time, and hence
-+	 * delegating de facto final scheduling decisions to the
-+	 * drive's internal scheduler, entails loss of control on the
-+	 * actual request service order. In particular, the critical
-+	 * situation is when requests from different processes happen
-+	 * to be present, at the same time, in the internal queue(s)
-+	 * of the drive. In such a situation, the drive, by deciding
-+	 * the service order of the internally-queued requests, does
-+	 * determine also the actual throughput distribution among
-+	 * these processes. But the drive typically has no notion or
-+	 * concern about per-process throughput distribution, and
-+	 * makes its decisions only on a per-request basis. Therefore,
-+	 * the service distribution enforced by the drive's internal
-+	 * scheduler is likely to coincide with the desired
-+	 * device-throughput distribution only in a completely
-+	 * symmetric scenario where:
-+	 * (i)  each of these processes must get the same throughput as
-+	 *      the others;
-+	 * (ii) all these processes have the same I/O pattern
-+	 *      (either sequential or random).
-+	 * In fact, in such a scenario, the drive will tend to treat
-+	 * the requests of each of these processes in about the same
-+	 * way as the requests of the others, and thus to provide
-+	 * each of these processes with about the same throughput
-+	 * (which is exactly the desired throughput distribution). In
-+	 * contrast, in any asymmetric scenario, device idling is
-+	 * certainly needed to guarantee that bfqq receives its
-+	 * assigned fraction of the device throughput (see [1] for
-+	 * details).
-+	 *
-+	 * We address this issue by controlling, actually, only the
-+	 * symmetry sub-condition (i), i.e., provided that
-+	 * sub-condition (i) holds, idling is not performed,
-+	 * regardless of whether sub-condition (ii) holds. In other
-+	 * words, only if sub-condition (i) holds, then idling is
-+	 * allowed, and the device tends to be prevented from queueing
-+	 * many requests, possibly of several processes. The reason
-+	 * for not controlling also sub-condition (ii) is that we
-+	 * exploit preemption to preserve guarantees in case of
-+	 * symmetric scenarios, even if (ii) does not hold, as
-+	 * explained in the next two paragraphs.
-+	 *
-+	 * Even if a queue, say Q, is expired when it remains idle, Q
-+	 * can still preempt the new in-service queue if the next
-+	 * request of Q arrives soon (see the comments on
-+	 * bfq_bfqq_update_budg_for_activation). If all queues and
-+	 * groups have the same weight, this form of preemption,
-+	 * combined with the hole-recovery heuristic described in the
-+	 * comments on function bfq_bfqq_update_budg_for_activation,
-+	 * are enough to preserve a correct bandwidth distribution in
-+	 * the mid term, even without idling. In fact, even if not
-+	 * idling allows the internal queues of the device to contain
-+	 * many requests, and thus to reorder requests, we can rather
-+	 * safely assume that the internal scheduler still preserves a
-+	 * minimum of mid-term fairness. The motivation for using
-+	 * preemption instead of idling is that, by not idling,
-+	 * service guarantees are preserved without minimally
-+	 * sacrificing throughput. In other words, both a high
-+	 * throughput and its desired distribution are obtained.
-+	 *
-+	 * More precisely, this preemption-based, idleless approach
-+	 * provides fairness in terms of IOPS, and not sectors per
-+	 * second. This can be seen with a simple example. Suppose
-+	 * that there are two queues with the same weight, but that
-+	 * the first queue receives requests of 8 sectors, while the
-+	 * second queue receives requests of 1024 sectors. In
-+	 * addition, suppose that each of the two queues contains at
-+	 * most one request at a time, which implies that each queue
-+	 * always remains idle after it is served. Finally, after
-+	 * remaining idle, each queue receives very quickly a new
-+	 * request. It follows that the two queues are served
-+	 * alternatively, preempting each other if needed. This
-+	 * implies that, although both queues have the same weight,
-+	 * the queue with large requests receives a service that is
-+	 * 1024/8 times as high as the service received by the other
-+	 * queue.
-+	 *
-+	 * On the other hand, device idling is performed, and thus
-+	 * pure sector-domain guarantees are provided, for the
-+	 * following queues, which are likely to need stronger
-+	 * throughput guarantees: weight-raised queues, and queues
-+	 * with a higher weight than other queues. When such queues
-+	 * are active, sub-condition (i) is false, which triggers
-+	 * device idling.
-+	 *
-+	 * According to the above considerations, the next variable is
-+	 * true (only) if sub-condition (i) holds. To compute the
-+	 * value of this variable, we not only use the return value of
-+	 * the function bfq_symmetric_scenario(), but also check
-+	 * whether bfqq is being weight-raised, because
-+	 * bfq_symmetric_scenario() does not take into account also
-+	 * weight-raised queues (see comments on
-+	 * bfq_weights_tree_add()).
-+	 *
-+	 * As a side note, it is worth considering that the above
-+	 * device-idling countermeasures may however fail in the
-+	 * following unlucky scenario: if idling is (correctly)
-+	 * disabled in a time period during which all symmetry
-+	 * sub-conditions hold, and hence the device is allowed to
-+	 * enqueue many requests, but at some later point in time some
-+	 * sub-condition stops to hold, then it may become impossible
-+	 * to let requests be served in the desired order until all
-+	 * the requests already queued in the device have been served.
-+	 */
-+	asymmetric_scenario = bfqq->wr_coeff > 1 ||
-+		!bfq_symmetric_scenario(bfqd);
-+
-+	/*
-+	 * Finally, there is a case where maximizing throughput is the
-+	 * best choice even if it may cause unfairness toward
-+	 * bfqq. Such a case is when bfqq became active in a burst of
-+	 * queue activations. Queues that became active during a large
-+	 * burst benefit only from throughput, as discussed in the
-+	 * comments on bfq_handle_burst. Thus, if bfqq became active
-+	 * in a burst and not idling the device maximizes throughput,
-+	 * then the device must no be idled, because not idling the
-+	 * device provides bfqq and all other queues in the burst with
-+	 * maximum benefit. Combining this and the above case, we can
-+	 * now establish when idling is actually needed to preserve
-+	 * service guarantees.
-+	 */
-+	idling_needed_for_service_guarantees =
-+		asymmetric_scenario && !bfq_bfqq_in_large_burst(bfqq);
-+
-+	/*
-+	 * We have now all the components we need to compute the
-+	 * return value of the function, which is true only if idling
-+	 * either boosts the throughput (without issues), or is
-+	 * necessary to preserve service guarantees.
-+	 */
-+	bfq_log_bfqq(bfqd, bfqq, "sync %d idling_boosts_thr %d",
-+		     bfq_bfqq_sync(bfqq), idling_boosts_thr);
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+		     "wr_busy %d boosts %d IO-bound %d guar %d",
-+		     bfqd->wr_busy_queues,
-+		     idling_boosts_thr_without_issues,
-+		     bfq_bfqq_IO_bound(bfqq),
-+		     idling_needed_for_service_guarantees);
-+
-+	return idling_boosts_thr_without_issues ||
-+		idling_needed_for_service_guarantees;
-+}
-+
-+/*
-+ * If the in-service queue is empty but the function bfq_better_to_idle
-+ * returns true, then:
-+ * 1) the queue must remain in service and cannot be expired, and
-+ * 2) the device must be idled to wait for the possible arrival of a new
-+ *    request for the queue.
-+ * See the comments on the function bfq_better_to_idle for the reasons
-+ * why performing device idling is the best choice to boost the throughput
-+ * and preserve service guarantees when bfq_better_to_idle itself
-+ * returns true.
-+ */
-+static bool bfq_bfqq_must_idle(struct bfq_queue *bfqq)
-+{
-+	return RB_EMPTY_ROOT(&bfqq->sort_list) && bfq_better_to_idle(bfqq);
-+}
-+
-+static struct bfq_queue *bfq_choose_bfqq_for_injection(struct bfq_data *bfqd)
-+{
-+	struct bfq_queue *bfqq;
-+
-+	/*
-+	 * A linear search; but, with a high probability, very few
-+	 * steps are needed to find a candidate queue, i.e., a queue
-+	 * with enough budget left for its next request. In fact:
-+	 * - BFQ dynamically updates the budget of every queue so as
-+	 *   to accomodate the expected backlog of the queue;
-+	 * - if a queue gets all its requests dispatched as injected
-+	 *   service, then the queue is removed from the active list
-+	 *   (and re-added only if it gets new requests, but with
-+	 *   enough budget for its new backlog).
-+	 */
-+	list_for_each_entry(bfqq, &bfqd->active_list, bfqq_list)
-+		if (!RB_EMPTY_ROOT(&bfqq->sort_list) &&
-+		    bfq_serv_to_charge(bfqq->next_rq, bfqq) <=
-+		    bfq_bfqq_budget_left(bfqq)) {
-+			bfq_log_bfqq(bfqd, bfqq, "returned this queue");
-+			return bfqq;
-+		}
-+
-+	bfq_log(bfqd, "no queue found");
-+	return NULL;
-+}
-+
-+/*
-+ * Select a queue for service.  If we have a current queue in service,
-+ * check whether to continue servicing it, or retrieve and set a new one.
-+ */
-+static struct bfq_queue *bfq_select_queue(struct bfq_data *bfqd)
-+{
-+	struct bfq_queue *bfqq;
-+	struct request *next_rq;
-+	enum bfqq_expiration reason = BFQ_BFQQ_BUDGET_TIMEOUT;
-+
-+	bfqq = bfqd->in_service_queue;
-+	if (!bfqq)
-+		goto new_queue;
-+
-+	bfq_log_bfqq(bfqd, bfqq, "already in-service queue");
-+
-+	/*
-+	 * Do not expire bfqq for budget timeout if bfqq may be about
-+	 * to enjoy device idling. The reason why, in this case, we
-+	 * prevent bfqq from expiring is the same as in the comments
-+	 * on the case where bfq_bfqq_must_idle() returns true, in
-+	 * bfq_completed_request().
-+	 */
-+	if (bfq_may_expire_for_budg_timeout(bfqq) &&
-+	    !bfq_bfqq_must_idle(bfqq))
-+		goto expire;
-+
-+check_queue:
-+	/*
-+	 * This loop is rarely executed more than once. Even when it
-+	 * happens, it is much more convenient to re-execute this loop
-+	 * than to return NULL and trigger a new dispatch to get a
-+	 * request served.
-+	 */
-+	next_rq = bfqq->next_rq;
-+	/*
-+	 * If bfqq has requests queued and it has enough budget left to
-+	 * serve them, keep the queue, otherwise expire it.
-+	 */
-+	if (next_rq) {
-+		BUG_ON(RB_EMPTY_ROOT(&bfqq->sort_list));
-+
-+		if (bfq_serv_to_charge(next_rq, bfqq) >
-+			bfq_bfqq_budget_left(bfqq)) {
-+			/*
-+			 * Expire the queue for budget exhaustion,
-+			 * which makes sure that the next budget is
-+			 * enough to serve the next request, even if
-+			 * it comes from the fifo expired path.
-+			 */
-+			reason = BFQ_BFQQ_BUDGET_EXHAUSTED;
-+			goto expire;
-+		} else {
-+			/*
-+			 * The idle timer may be pending because we may
-+			 * not disable disk idling even when a new request
-+			 * arrives.
-+			 */
-+			if (bfq_bfqq_wait_request(bfqq)) {
-+				/*
-+				 * If we get here: 1) at least a new request
-+				 * has arrived but we have not disabled the
-+				 * timer because the request was too small,
-+				 * 2) then the block layer has unplugged
-+				 * the device, causing the dispatch to be
-+				 * invoked.
-+				 *
-+				 * Since the device is unplugged, now the
-+				 * requests are probably large enough to
-+				 * provide a reasonable throughput.
-+				 * So we disable idling.
-+				 */
-+				bfq_clear_bfqq_wait_request(bfqq);
-+				hrtimer_try_to_cancel(&bfqd->idle_slice_timer);
-+			}
-+			goto keep_queue;
-+		}
-+	}
-+
-+	/*
-+	 * No requests pending. However, if the in-service queue is idling
-+	 * for a new request, or has requests waiting for a completion and
-+	 * may idle after their completion, then keep it anyway.
-+	 *
-+	 * Yet, to boost throughput, inject service from other queues if
-+	 * possible.
-+	 */
-+	if (bfq_bfqq_wait_request(bfqq) ||
-+	    (bfqq->dispatched != 0 && bfq_better_to_idle(bfqq))) {
-+		if (bfq_bfqq_injectable(bfqq) &&
-+		    bfqq->injected_service * bfqq->inject_coeff <
-+		    bfqq->entity.service * 10) {
-+			bfq_log_bfqq(bfqd, bfqq, "looking for queue for injection");
-+			bfqq = bfq_choose_bfqq_for_injection(bfqd);
-+		} else {
-+			if (BFQQ_SEEKY(bfqq))
-+				bfq_log_bfqq(bfqd, bfqq,
-+					"injection saturated %d * %d >= %d * 10",
-+					bfqq->injected_service, bfqq->inject_coeff,
-+					bfqq->entity.service);
-+			bfqq = NULL;
-+		}
-+		goto keep_queue;
-+	}
-+
-+	reason = BFQ_BFQQ_NO_MORE_REQUESTS;
-+expire:
-+	bfq_bfqq_expire(bfqd, bfqq, false, reason);
-+new_queue:
-+	bfqq = bfq_set_in_service_queue(bfqd);
-+	if (bfqq) {
-+		bfq_log_bfqq(bfqd, bfqq, "checking new queue");
-+		goto check_queue;
-+	}
-+keep_queue:
-+	if (bfqq)
-+		bfq_log_bfqq(bfqd, bfqq, "returned this queue");
-+	else
-+		bfq_log(bfqd, "no queue returned");
-+
-+	return bfqq;
-+}
-+
-+static void bfq_update_wr_data(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	struct bfq_entity *entity = &bfqq->entity;
-+
-+	if (bfqq->wr_coeff > 1) { /* queue is being weight-raised */
-+		BUG_ON(bfqq->wr_cur_max_time == bfqd->bfq_wr_rt_max_time &&
-+		       time_is_after_jiffies(bfqq->last_wr_start_finish));
-+
-+		bfq_log_bfqq(bfqd, bfqq,
-+			"raising period dur %u/%u msec, old coeff %u, w %d(%d)",
-+			jiffies_to_msecs(jiffies - bfqq->last_wr_start_finish),
-+			jiffies_to_msecs(bfqq->wr_cur_max_time),
-+			bfqq->wr_coeff,
-+			bfqq->entity.weight, bfqq->entity.orig_weight);
-+
-+		BUG_ON(bfqq != bfqd->in_service_queue && entity->weight !=
-+		       entity->orig_weight * bfqq->wr_coeff);
-+		if (entity->prio_changed)
-+			bfq_log_bfqq(bfqd, bfqq, "WARN: pending prio change");
-+
-+		/*
-+		 * If the queue was activated in a burst, or too much
-+		 * time has elapsed from the beginning of this
-+		 * weight-raising period, then end weight raising.
-+		 */
-+		if (bfq_bfqq_in_large_burst(bfqq))
-+			bfq_bfqq_end_wr(bfqq);
-+		else if (time_is_before_jiffies(bfqq->last_wr_start_finish +
-+					   bfqq->wr_cur_max_time)) {
-+			if (bfqq->wr_cur_max_time != bfqd->bfq_wr_rt_max_time ||
-+			time_is_before_jiffies(bfqq->wr_start_at_switch_to_srt +
-+					bfq_wr_duration(bfqd)))
-+				bfq_bfqq_end_wr(bfqq);
-+			else {
-+				switch_back_to_interactive_wr(bfqq, bfqd);
-+				BUG_ON(time_is_after_jiffies(
-+					       bfqq->last_wr_start_finish));
-+				bfqq->entity.prio_changed = 1;
-+				bfq_log_bfqq(bfqd, bfqq,
-+					"back to interactive wr");
-+			}
-+		}
-+		if (bfqq->wr_coeff > 1 &&
-+		    bfqq->wr_cur_max_time != bfqd->bfq_wr_rt_max_time &&
-+		    bfqq->service_from_wr > max_service_from_wr) {
-+			/* see comments on max_service_from_wr */
-+			bfq_bfqq_end_wr(bfqq);
-+			bfq_log_bfqq(bfqd, bfqq,
-+				     "too much service");
-+		}
-+	}
-+	/*
-+	 * To improve latency (for this or other queues), immediately
-+	 * update weight both if it must be raised and if it must be
-+	 * lowered. Since, entity may be on some active tree here, and
-+	 * might have a pending change of its ioprio class, invoke
-+	 * next function with the last parameter unset (see the
-+	 * comments on the function).
-+	 */
-+	if ((entity->weight > entity->orig_weight) != (bfqq->wr_coeff > 1))
-+		__bfq_entity_update_weight_prio(bfq_entity_service_tree(entity),
-+						entity, false);
-+}
-+
-+/*
-+ * Dispatch next request from bfqq.
-+ */
-+static struct request *bfq_dispatch_rq_from_bfqq(struct bfq_data *bfqd,
-+						 struct bfq_queue *bfqq)
-+{
-+	struct request *rq = bfqq->next_rq;
-+	unsigned long service_to_charge;
-+
-+	BUG_ON(RB_EMPTY_ROOT(&bfqq->sort_list));
-+	BUG_ON(!rq);
-+	service_to_charge = bfq_serv_to_charge(rq, bfqq);
-+
-+	BUG_ON(service_to_charge > bfq_bfqq_budget_left(bfqq));
-+
-+	BUG_ON(bfqq->entity.budget < bfqq->entity.service);
-+
-+	bfq_bfqq_served(bfqq, service_to_charge);
-+
-+	BUG_ON(bfqq->entity.budget < bfqq->entity.service);
-+
-+	bfq_dispatch_remove(bfqd->queue, rq);
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+	     "dispatched %u sec req (%llu), budg left %d, new disp_nr %d",
-+			blk_rq_sectors(rq),
-+			(unsigned long long) blk_rq_pos(rq),
-+		     bfq_bfqq_budget_left(bfqq),
-+		     bfqq->dispatched);
-+
-+	if (bfqq != bfqd->in_service_queue) {
-+		if (likely(bfqd->in_service_queue)) {
-+			bfqd->in_service_queue->injected_service +=
-+				bfq_serv_to_charge(rq, bfqq);
-+			bfq_log_bfqq(bfqd, bfqd->in_service_queue,
-+				     "injected_service increased to %d",
-+				     bfqd->in_service_queue->injected_service);
-+		}
-+		goto return_rq;
-+	}
-+
-+	/*
-+	 * If weight raising has to terminate for bfqq, then next
-+	 * function causes an immediate update of bfqq's weight,
-+	 * without waiting for next activation. As a consequence, on
-+	 * expiration, bfqq will be timestamped as if has never been
-+	 * weight-raised during this service slot, even if it has
-+	 * received part or even most of the service as a
-+	 * weight-raised queue. This inflates bfqq's timestamps, which
-+	 * is beneficial, as bfqq is then more willing to leave the
-+	 * device immediately to possible other weight-raised queues.
-+	 */
-+	bfq_update_wr_data(bfqd, bfqq);
-+
-+	/*
-+	 * Expire bfqq, pretending that its budget expired, if bfqq
-+	 * belongs to CLASS_IDLE and other queues are waiting for
-+	 * service.
-+	 */
-+	if (!(bfqd->busy_queues > 1 && bfq_class_idle(bfqq)))
-+		goto return_rq;
-+
-+	bfq_bfqq_expire(bfqd, bfqq, false, BFQ_BFQQ_BUDGET_EXHAUSTED);
-+
-+return_rq:
-+	return rq;
-+}
-+
-+static bool bfq_has_work(struct blk_mq_hw_ctx *hctx)
-+{
-+	struct bfq_data *bfqd = hctx->queue->elevator->elevator_data;
-+
-+	bfq_log(bfqd, "dispatch_non_empty %d busy_queues %d",
-+		!list_empty_careful(&bfqd->dispatch), bfqd->busy_queues > 0);
-+
-+	/*
-+	 * Avoiding lock: a race on bfqd->busy_queues should cause at
-+	 * most a call to dispatch for nothing
-+	 */
-+	return !list_empty_careful(&bfqd->dispatch) ||
-+		bfqd->busy_queues > 0;
-+}
-+
-+static struct request *__bfq_dispatch_request(struct blk_mq_hw_ctx *hctx)
-+{
-+	struct bfq_data *bfqd = hctx->queue->elevator->elevator_data;
-+	struct request *rq = NULL;
-+	struct bfq_queue *bfqq = NULL;
-+
-+	if (!list_empty(&bfqd->dispatch)) {
-+		rq = list_first_entry(&bfqd->dispatch, struct request,
-+				      queuelist);
-+		list_del_init(&rq->queuelist);
-+		rq->rq_flags &= ~RQF_DISP_LIST;
-+
-+		bfq_log(bfqd,
-+			"picked %p from dispatch list", rq);
-+		bfqq = RQ_BFQQ(rq);
-+
-+		if (bfqq) {
-+			/*
-+			 * Increment counters here, because this
-+			 * dispatch does not follow the standard
-+			 * dispatch flow (where counters are
-+			 * incremented)
-+			 */
-+			bfqq->dispatched++;
-+
-+			/*
-+			 * TESTING: reset DISP_LIST flag, because: 1)
-+			 * this rq this request has passed through
-+			 * bfq_prepare_request, 2) then it will have
-+			 * bfq_finish_requeue_request invoked on it, and 3) in
-+			 * bfq_finish_requeue_request we use this flag to check
-+			 * that bfq_finish_requeue_request is not invoked on
-+			 * requests for which bfq_prepare_request has
-+			 * been invoked.
-+			 */
-+			rq->rq_flags &= ~RQF_DISP_LIST;
-+			goto inc_in_driver_start_rq;
-+		}
-+
-+		/*
-+		 * We exploit the bfq_finish_requeue_request hook to decrement
-+		 * rq_in_driver, but bfq_finish_requeue_request will not be
-+		 * invoked on this request. So, to avoid unbalance,
-+		 * just start this request, without incrementing
-+		 * rq_in_driver. As a negative consequence,
-+		 * rq_in_driver is deceptively lower than it should be
-+		 * while this request is in service. This may cause
-+		 * bfq_schedule_dispatch to be invoked uselessly.
-+		 *
-+		 * As for implementing an exact solution, the
-+		 * bfq_finish_requeue_request hook, if defined, is probably
-+		 * invoked also on this request. So, by exploiting
-+		 * this hook, we could 1) increment rq_in_driver here,
-+		 * and 2) decrement it in bfq_finish_requeue_request. Such a
-+		 * solution would let the value of the counter be
-+		 * always accurate, but it would entail using an extra
-+		 * interface function. This cost seems higher than the
-+		 * benefit, being the frequency of non-elevator-private
-+		 * requests very low.
-+		 */
-+		goto start_rq;
-+	}
-+
-+	bfq_log(bfqd, "%d busy queues", bfqd->busy_queues);
-+
-+	if (bfqd->busy_queues == 0)
-+		goto exit;
-+
-+	/*
-+	 * Force device to serve one request at a time if
-+	 * strict_guarantees is true. Forcing this service scheme is
-+	 * currently the ONLY way to guarantee that the request
-+	 * service order enforced by the scheduler is respected by a
-+	 * queueing device. Otherwise the device is free even to make
-+	 * some unlucky request wait for as long as the device
-+	 * wishes.
-+	 *
-+	 * Of course, serving one request at at time may cause loss of
-+	 * throughput.
-+	 */
-+	if (bfqd->strict_guarantees && bfqd->rq_in_driver > 0)
-+		goto exit;
-+
-+	bfqq = bfq_select_queue(bfqd);
-+	if (!bfqq)
-+		goto exit;
-+
-+	BUG_ON(bfqq == bfqd->in_service_queue &&
-+	       bfqq->entity.budget < bfqq->entity.service);
-+
-+	BUG_ON(bfqq == bfqd->in_service_queue &&
-+	       bfq_bfqq_wait_request(bfqq));
-+
-+	rq = bfq_dispatch_rq_from_bfqq(bfqd, bfqq);
-+
-+	BUG_ON(bfqq->entity.budget < bfqq->entity.service);
-+
-+	if (rq) {
-+	inc_in_driver_start_rq:
-+		bfqd->rq_in_driver++;
-+	start_rq:
-+		rq->rq_flags |= RQF_STARTED;
-+		if (bfqq)
-+			bfq_log_bfqq(bfqd, bfqq,
-+				"%s request %p, rq_in_driver %d",
-+				     bfq_bfqq_sync(bfqq) ? "sync" : "async",
-+				     rq,
-+				     bfqd->rq_in_driver);
-+		else
-+			bfq_log(bfqd,
-+		"request %p from dispatch list, rq_in_driver %d",
-+				rq, bfqd->rq_in_driver);
-+	} else
-+		bfq_log(bfqd,
-+		"returned NULL request, rq_in_driver %d",
-+			bfqd->rq_in_driver);
-+
-+exit:
-+	return rq;
-+}
-+
-+
-+#if defined(BFQ_GROUP_IOSCHED_ENABLED) && defined(CONFIG_DEBUG_BLK_CGROUP)
-+static void bfq_update_dispatch_stats(struct request_queue *q,
-+				      struct request *rq,
-+				      struct bfq_queue *in_serv_queue,
-+				      bool idle_timer_disabled)
-+{
-+	struct bfq_queue *bfqq = rq ? RQ_BFQQ(rq) : NULL;
-+
-+	if (!idle_timer_disabled && !bfqq)
-+		return;
-+
-+	/*
-+	 * rq and bfqq are guaranteed to exist until this function
-+	 * ends, for the following reasons. First, rq can be
-+	 * dispatched to the device, and then can be completed and
-+	 * freed, only after this function ends. Second, rq cannot be
-+	 * merged (and thus freed because of a merge) any longer,
-+	 * because it has already started. Thus rq cannot be freed
-+	 * before this function ends, and, since rq has a reference to
-+	 * bfqq, the same guarantee holds for bfqq too.
-+	 *
-+	 * In addition, the following queue lock guarantees that
-+	 * bfqq_group(bfqq) exists as well.
-+	 */
-+	spin_lock_irq(q->queue_lock);
-+	if (idle_timer_disabled)
-+		/*
-+		 * Since the idle timer has been disabled,
-+		 * in_serv_queue contained some request when
-+		 * __bfq_dispatch_request was invoked above, which
-+		 * implies that rq was picked exactly from
-+		 * in_serv_queue. Thus in_serv_queue == bfqq, and is
-+		 * therefore guaranteed to exist because of the above
-+		 * arguments.
-+		 */
-+		bfqg_stats_update_idle_time(bfqq_group(in_serv_queue));
-+	if (bfqq) {
-+		struct bfq_group *bfqg = bfqq_group(bfqq);
-+
-+		bfqg_stats_update_avg_queue_size(bfqg);
-+		bfqg_stats_set_start_empty_time(bfqg);
-+		bfqg_stats_update_io_remove(bfqg, rq->cmd_flags);
-+	}
-+	spin_unlock_irq(q->queue_lock);
-+}
-+#else
-+static inline void bfq_update_dispatch_stats(struct request_queue *q,
-+					     struct request *rq,
-+					     struct bfq_queue *in_serv_queue,
-+					     bool idle_timer_disabled) {}
-+#endif
-+static struct request *bfq_dispatch_request(struct blk_mq_hw_ctx *hctx)
-+{
-+	struct bfq_data *bfqd = hctx->queue->elevator->elevator_data;
-+	struct request *rq;
-+	struct bfq_queue *in_serv_queue;
-+	bool waiting_rq, idle_timer_disabled;
-+
-+	spin_lock_irq(&bfqd->lock);
-+
-+	in_serv_queue = bfqd->in_service_queue;
-+	waiting_rq = in_serv_queue && bfq_bfqq_wait_request(in_serv_queue);
-+
-+	rq = __bfq_dispatch_request(hctx);
-+
-+	idle_timer_disabled =
-+		waiting_rq && !bfq_bfqq_wait_request(in_serv_queue);
-+
-+	spin_unlock_irq(&bfqd->lock);
-+
-+	bfq_update_dispatch_stats(hctx->queue, rq, in_serv_queue,
-+				  idle_timer_disabled);
-+
-+	return rq;
-+}
-+
-+/*
-+ * Task holds one reference to the queue, dropped when task exits.  Each rq
-+ * in-flight on this queue also holds a reference, dropped when rq is freed.
-+ *
-+ * Scheduler lock must be held here. Recall not to use bfqq after calling
-+ * this function on it.
-+ */
-+static void bfq_put_queue(struct bfq_queue *bfqq)
-+{
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	struct bfq_group *bfqg = bfqq_group(bfqq);
-+#endif
-+
-+	assert_spin_locked(&bfqq->bfqd->lock);
-+
-+	BUG_ON(bfqq->ref <= 0);
-+
-+	if (bfqq->bfqd)
-+		bfq_log_bfqq(bfqq->bfqd, bfqq, "%p %d", bfqq, bfqq->ref);
-+
-+	bfqq->ref--;
-+	if (bfqq->ref)
-+		return;
-+
-+	BUG_ON(rb_first(&bfqq->sort_list));
-+	BUG_ON(bfqq->allocated != 0);
-+	BUG_ON(bfqq->entity.tree);
-+	BUG_ON(bfq_bfqq_busy(bfqq));
-+
-+	if (!hlist_unhashed(&bfqq->burst_list_node)) {
-+		hlist_del_init(&bfqq->burst_list_node);
-+		/*
-+		 * Decrement also burst size after the removal, if the
-+		 * process associated with bfqq is exiting, and thus
-+		 * does not contribute to the burst any longer. This
-+		 * decrement helps filter out false positives of large
-+		 * bursts, when some short-lived process (often due to
-+		 * the execution of commands by some service) happens
-+		 * to start and exit while a complex application is
-+		 * starting, and thus spawning several processes that
-+		 * do I/O (and that *must not* be treated as a large
-+		 * burst, see comments on bfq_handle_burst).
-+		 *
-+		 * In particular, the decrement is performed only if:
-+		 * 1) bfqq is not a merged queue, because, if it is,
-+		 * then this free of bfqq is not triggered by the exit
-+		 * of the process bfqq is associated with, but exactly
-+		 * by the fact that bfqq has just been merged.
-+		 * 2) burst_size is greater than 0, to handle
-+		 * unbalanced decrements. Unbalanced decrements may
-+		 * happen in te following case: bfqq is inserted into
-+		 * the current burst list--without incrementing
-+		 * bust_size--because of a split, but the current
-+		 * burst list is not the burst list bfqq belonged to
-+		 * (see comments on the case of a split in
-+		 * bfq_set_request).
-+		 */
-+		if (bfqq->bic && bfqq->bfqd->burst_size > 0)
-+			bfqq->bfqd->burst_size--;
-+	}
-+
-+	if (bfqq->bfqd)
-+		bfq_log_bfqq(bfqq->bfqd, bfqq, "%p freed", bfqq);
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	bfq_log_bfqq(bfqq->bfqd, bfqq, "putting blkg and bfqg %p\n", bfqg);
-+	bfqg_and_blkg_put(bfqg);
-+#endif
-+	kmem_cache_free(bfq_pool, bfqq);
-+}
-+
-+static void bfq_put_cooperator(struct bfq_queue *bfqq)
-+{
-+	struct bfq_queue *__bfqq, *next;
-+
-+	/*
-+	 * If this queue was scheduled to merge with another queue, be
-+	 * sure to drop the reference taken on that queue (and others in
-+	 * the merge chain). See bfq_setup_merge and bfq_merge_bfqqs.
-+	 */
-+	__bfqq = bfqq->new_bfqq;
-+	while (__bfqq) {
-+		if (__bfqq == bfqq)
-+			break;
-+		next = __bfqq->new_bfqq;
-+		bfq_put_queue(__bfqq);
-+		__bfqq = next;
-+	}
-+}
-+
-+static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	if (bfqq == bfqd->in_service_queue) {
-+		__bfq_bfqq_expire(bfqd, bfqq);
-+		bfq_schedule_dispatch(bfqd);
-+	}
-+
-+	bfq_log_bfqq(bfqd, bfqq, "%p, %d", bfqq, bfqq->ref);
-+
-+	bfq_put_cooperator(bfqq);
-+
-+	bfq_put_queue(bfqq); /* release process reference */
-+}
-+
-+static void bfq_exit_icq_bfqq(struct bfq_io_cq *bic, bool is_sync)
-+{
-+	struct bfq_queue *bfqq = bic_to_bfqq(bic, is_sync);
-+	struct bfq_data *bfqd;
-+
-+	if (bfqq)
-+		bfqd = bfqq->bfqd; /* NULL if scheduler already exited */
-+
-+	if (bfqq && bfqd) {
-+		unsigned long flags;
-+
-+		spin_lock_irqsave(&bfqd->lock, flags);
-+		bfq_exit_bfqq(bfqd, bfqq);
-+		bic_set_bfqq(bic, NULL, is_sync);
-+		spin_unlock_irqrestore(&bfqd->lock, flags);
-+	}
-+}
-+
-+static void bfq_exit_icq(struct io_cq *icq)
-+{
-+	struct bfq_io_cq *bic = icq_to_bic(icq);
-+
-+	BUG_ON(!bic);
-+	bfq_exit_icq_bfqq(bic, true);
-+	bfq_exit_icq_bfqq(bic, false);
-+}
-+
-+/*
-+ * Update the entity prio values; note that the new values will not
-+ * be used until the next (re)activation.
-+ */
-+static void bfq_set_next_ioprio_data(struct bfq_queue *bfqq,
-+				     struct bfq_io_cq *bic)
-+{
-+	struct task_struct *tsk = current;
-+	int ioprio_class;
-+	struct bfq_data *bfqd = bfqq->bfqd;
-+
-+	WARN_ON(!bfqd);
-+	if (!bfqd)
-+		return;
-+
-+	ioprio_class = IOPRIO_PRIO_CLASS(bic->ioprio);
-+	switch (ioprio_class) {
-+	default:
-+		dev_err(bfqq->bfqd->queue->backing_dev_info->dev,
-+			"bfq: bad prio class %d\n", ioprio_class);
-+	case IOPRIO_CLASS_NONE:
-+		/*
-+		 * No prio set, inherit CPU scheduling settings.
-+		 */
-+		bfqq->new_ioprio = task_nice_ioprio(tsk);
-+		bfqq->new_ioprio_class = task_nice_ioclass(tsk);
-+		break;
-+	case IOPRIO_CLASS_RT:
-+		bfqq->new_ioprio = IOPRIO_PRIO_DATA(bic->ioprio);
-+		bfqq->new_ioprio_class = IOPRIO_CLASS_RT;
-+		break;
-+	case IOPRIO_CLASS_BE:
-+		bfqq->new_ioprio = IOPRIO_PRIO_DATA(bic->ioprio);
-+		bfqq->new_ioprio_class = IOPRIO_CLASS_BE;
-+		break;
-+	case IOPRIO_CLASS_IDLE:
-+		bfqq->new_ioprio_class = IOPRIO_CLASS_IDLE;
-+		bfqq->new_ioprio = 7;
-+		break;
-+	}
-+
-+	if (bfqq->new_ioprio >= IOPRIO_BE_NR) {
-+		pr_crit("bfq_set_next_ioprio_data: new_ioprio %d\n",
-+			bfqq->new_ioprio);
-+		BUG();
-+	}
-+
-+	bfqq->entity.new_weight = bfq_ioprio_to_weight(bfqq->new_ioprio);
-+	bfqq->entity.prio_changed = 1;
-+	bfq_log_bfqq(bfqq->bfqd, bfqq,
-+		     "bic_class %d prio %d class %d",
-+		     ioprio_class, bfqq->new_ioprio, bfqq->new_ioprio_class);
-+}
-+
-+static void bfq_check_ioprio_change(struct bfq_io_cq *bic, struct bio *bio)
-+{
-+	struct bfq_data *bfqd = bic_to_bfqd(bic);
-+	struct bfq_queue *bfqq;
-+	unsigned long uninitialized_var(flags);
-+	int ioprio = bic->icq.ioc->ioprio;
-+
-+	/*
-+	 * This condition may trigger on a newly created bic, be sure to
-+	 * drop the lock before returning.
-+	 */
-+	if (unlikely(!bfqd) || likely(bic->ioprio == ioprio))
-+		return;
-+
-+	bic->ioprio = ioprio;
-+
-+	bfqq = bic_to_bfqq(bic, false);
-+	if (bfqq) {
-+		/* release process reference on this queue */
-+		bfq_put_queue(bfqq);
-+		bfqq = bfq_get_queue(bfqd, bio, BLK_RW_ASYNC, bic);
-+		bic_set_bfqq(bic, bfqq, false);
-+		bfq_log_bfqq(bfqd, bfqq,
-+			     "bfqq %p %d",
-+			     bfqq, bfqq->ref);
-+	}
-+
-+	bfqq = bic_to_bfqq(bic, true);
-+	if (bfqq)
-+		bfq_set_next_ioprio_data(bfqq, bic);
-+}
-+
-+static void bfq_init_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+			  struct bfq_io_cq *bic, pid_t pid, int is_sync)
-+{
-+	RB_CLEAR_NODE(&bfqq->entity.rb_node);
-+	INIT_LIST_HEAD(&bfqq->fifo);
-+	INIT_HLIST_NODE(&bfqq->burst_list_node);
-+	BUG_ON(!hlist_unhashed(&bfqq->burst_list_node));
-+
-+	bfqq->ref = 0;
-+	bfqq->bfqd = bfqd;
-+
-+	if (bic)
-+		bfq_set_next_ioprio_data(bfqq, bic);
-+
-+	if (is_sync) {
-+		/*
-+		 * No need to mark as has_short_ttime if in
-+		 * idle_class, because no device idling is performed
-+		 * for queues in idle class
-+		 */
-+		if (!bfq_class_idle(bfqq))
-+			/* tentatively mark as has_short_ttime */
-+			bfq_mark_bfqq_has_short_ttime(bfqq);
-+		bfq_mark_bfqq_sync(bfqq);
-+		bfq_mark_bfqq_just_created(bfqq);
-+		/*
-+		 * Aggressively inject a lot of service: up to 90%.
-+		 * This coefficient remains constant during bfqq life,
-+		 * but this behavior might be changed, after enough
-+		 * testing and tuning.
-+		 */
-+		bfqq->inject_coeff = 1;
-+	} else
-+		bfq_clear_bfqq_sync(bfqq);
-+
-+	bfqq->ttime.last_end_request = ktime_get_ns() - (1ULL<<32);
-+
-+	bfq_mark_bfqq_IO_bound(bfqq);
-+
-+	/* Tentative initial value to trade off between thr and lat */
-+	bfqq->max_budget = (2 * bfq_max_budget(bfqd)) / 3;
-+	bfqq->pid = pid;
-+
-+	bfqq->wr_coeff = 1;
-+	bfqq->last_wr_start_finish = jiffies;
-+	bfqq->wr_start_at_switch_to_srt = bfq_smallest_from_now();
-+	bfqq->budget_timeout = bfq_smallest_from_now();
-+	bfqq->split_time = bfq_smallest_from_now();
-+
-+	/*
-+	 * To not forget the possibly high bandwidth consumed by a
-+	 * process/queue in the recent past,
-+	 * bfq_bfqq_softrt_next_start() returns a value at least equal
-+	 * to the current value of bfqq->soft_rt_next_start (see
-+	 * comments on bfq_bfqq_softrt_next_start).  Set
-+	 * soft_rt_next_start to now, to mean that bfqq has consumed
-+	 * no bandwidth so far.
-+	 */
-+	bfqq->soft_rt_next_start = jiffies;
-+
-+	/* first request is almost certainly seeky */
-+	bfqq->seek_history = 1;
-+}
-+
-+static struct bfq_queue **bfq_async_queue_prio(struct bfq_data *bfqd,
-+					       struct bfq_group *bfqg,
-+					       int ioprio_class, int ioprio)
-+{
-+	switch (ioprio_class) {
-+	case IOPRIO_CLASS_RT:
-+		return &bfqg->async_bfqq[0][ioprio];
-+	case IOPRIO_CLASS_NONE:
-+		ioprio = IOPRIO_NORM;
-+		/* fall through */
-+	case IOPRIO_CLASS_BE:
-+		return &bfqg->async_bfqq[1][ioprio];
-+	case IOPRIO_CLASS_IDLE:
-+		return &bfqg->async_idle_bfqq;
-+	default:
-+		BUG();
-+	}
-+}
-+
-+static struct bfq_queue *bfq_get_queue(struct bfq_data *bfqd,
-+				       struct bio *bio, bool is_sync,
-+				       struct bfq_io_cq *bic)
-+{
-+	const int ioprio = IOPRIO_PRIO_DATA(bic->ioprio);
-+	const int ioprio_class = IOPRIO_PRIO_CLASS(bic->ioprio);
-+	struct bfq_queue **async_bfqq = NULL;
-+	struct bfq_queue *bfqq;
-+	struct bfq_group *bfqg;
-+
-+	rcu_read_lock();
-+
-+	bfqg = bfq_find_set_group(bfqd, bio_blkcg(bio));
-+	if (!bfqg) {
-+		bfqq = &bfqd->oom_bfqq;
-+		goto out;
-+	}
-+
-+	if (!is_sync) {
-+		async_bfqq = bfq_async_queue_prio(bfqd, bfqg, ioprio_class,
-+						  ioprio);
-+		bfqq = *async_bfqq;
-+		if (bfqq)
-+			goto out;
-+	}
-+
-+	bfqq = kmem_cache_alloc_node(bfq_pool,
-+				     GFP_NOWAIT | __GFP_ZERO | __GFP_NOWARN,
-+				     bfqd->queue->node);
-+
-+	if (bfqq) {
-+		bfq_init_bfqq(bfqd, bfqq, bic, current->pid,
-+			      is_sync);
-+		bfq_init_entity(&bfqq->entity, bfqg);
-+		bfq_log_bfqq(bfqd, bfqq, "allocated");
-+	} else {
-+		bfqq = &bfqd->oom_bfqq;
-+		bfq_log_bfqq(bfqd, bfqq, "using oom bfqq");
-+		goto out;
-+	}
-+
-+	/*
-+	 * Pin the queue now that it's allocated, scheduler exit will
-+	 * prune it.
-+	 */
-+	if (async_bfqq) {
-+		bfqq->ref++; /*
-+			      * Extra group reference, w.r.t. sync
-+			      * queue. This extra reference is removed
-+			      * only if bfqq->bfqg disappears, to
-+			      * guarantee that this queue is not freed
-+			      * until its group goes away.
-+			      */
-+		bfq_log_bfqq(bfqd, bfqq, "bfqq not in async: %p, %d",
-+			     bfqq, bfqq->ref);
-+		*async_bfqq = bfqq;
-+	}
-+
-+out:
-+	bfqq->ref++; /* get a process reference to this queue */
-+	bfq_log_bfqq(bfqd, bfqq, "at end: %p, %d", bfqq, bfqq->ref);
-+	rcu_read_unlock();
-+	return bfqq;
-+}
-+
-+static void bfq_update_io_thinktime(struct bfq_data *bfqd,
-+				    struct bfq_queue *bfqq)
-+{
-+	struct bfq_ttime *ttime = &bfqq->ttime;
-+	u64 elapsed = ktime_get_ns() - bfqq->ttime.last_end_request;
-+
-+	elapsed = min_t(u64, elapsed, 2 * bfqd->bfq_slice_idle);
-+
-+	ttime->ttime_samples = (7*bfqq->ttime.ttime_samples + 256) / 8;
-+	ttime->ttime_total = div_u64(7*ttime->ttime_total + 256*elapsed,  8);
-+	ttime->ttime_mean = div64_ul(ttime->ttime_total + 128,
-+				     ttime->ttime_samples);
-+}
-+
-+static void
-+bfq_update_io_seektime(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+		       struct request *rq)
-+{
-+	bfqq->seek_history <<= 1;
-+	bfqq->seek_history |=
-+		get_sdist(bfqq->last_request_pos, rq) > BFQQ_SEEK_THR &&
-+		(!blk_queue_nonrot(bfqd->queue) ||
-+		 blk_rq_sectors(rq) < BFQQ_SECT_THR_NONROT);
-+}
-+
-+static void bfq_update_has_short_ttime(struct bfq_data *bfqd,
-+				       struct bfq_queue *bfqq,
-+				       struct bfq_io_cq *bic)
-+{
-+	bool has_short_ttime = true;
-+
-+	/*
-+	 * No need to update has_short_ttime if bfqq is async or in
-+	 * idle io prio class, or if bfq_slice_idle is zero, because
-+	 * no device idling is performed for bfqq in this case.
-+	 */
-+	if (!bfq_bfqq_sync(bfqq) || bfq_class_idle(bfqq) ||
-+	    bfqd->bfq_slice_idle == 0)
-+		return;
-+
-+	/* Idle window just restored, statistics are meaningless. */
-+	if (time_is_after_eq_jiffies(bfqq->split_time +
-+				     bfqd->bfq_wr_min_idle_time))
-+		return;
-+
-+	/* Think time is infinite if no process is linked to
-+	 * bfqq. Otherwise check average think time to
-+	 * decide whether to mark as has_short_ttime
-+	 */
-+	if (atomic_read(&bic->icq.ioc->active_ref) == 0 ||
-+	    (bfq_sample_valid(bfqq->ttime.ttime_samples) &&
-+	     bfqq->ttime.ttime_mean > bfqd->bfq_slice_idle))
-+		has_short_ttime = false;
-+
-+	bfq_log_bfqq(bfqd, bfqq, "has_short_ttime %d",
-+		has_short_ttime);
-+
-+	if (has_short_ttime)
-+		bfq_mark_bfqq_has_short_ttime(bfqq);
-+	else
-+		bfq_clear_bfqq_has_short_ttime(bfqq);
-+}
-+
-+/*
-+ * Called when a new fs request (rq) is added to bfqq.  Check if there's
-+ * something we should do about it.
-+ */
-+static void bfq_rq_enqueued(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+			    struct request *rq)
-+{
-+	struct bfq_io_cq *bic = RQ_BIC(rq);
-+
-+	if (rq->cmd_flags & REQ_META)
-+		bfqq->meta_pending++;
-+
-+	bfq_update_io_thinktime(bfqd, bfqq);
-+	bfq_update_has_short_ttime(bfqd, bfqq, bic);
-+	bfq_update_io_seektime(bfqd, bfqq, rq);
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+		     "has_short_ttime=%d (seeky %d)",
-+		     bfq_bfqq_has_short_ttime(bfqq), BFQQ_SEEKY(bfqq));
-+
-+	bfqq->last_request_pos = blk_rq_pos(rq) + blk_rq_sectors(rq);
-+
-+	if (bfqq == bfqd->in_service_queue && bfq_bfqq_wait_request(bfqq)) {
-+		bool small_req = bfqq->queued[rq_is_sync(rq)] == 1 &&
-+				 blk_rq_sectors(rq) < 32;
-+		bool budget_timeout = bfq_bfqq_budget_timeout(bfqq);
-+
-+		/*
-+		 * There is just this request queued: if the request
-+		 * is small and the queue is not to be expired, then
-+		 * just exit.
-+		 *
-+		 * In this way, if the device is being idled to wait
-+		 * for a new request from the in-service queue, we
-+		 * avoid unplugging the device and committing the
-+		 * device to serve just a small request. On the
-+		 * contrary, we wait for the block layer to decide
-+		 * when to unplug the device: hopefully, new requests
-+		 * will be merged to this one quickly, then the device
-+		 * will be unplugged and larger requests will be
-+		 * dispatched.
-+		 */
-+		if (small_req && !budget_timeout)
-+			return;
-+
-+		/*
-+		 * A large enough request arrived, or the queue is to
-+		 * be expired: in both cases disk idling is to be
-+		 * stopped, so clear wait_request flag and reset
-+		 * timer.
-+		 */
-+		bfq_clear_bfqq_wait_request(bfqq);
-+		hrtimer_try_to_cancel(&bfqd->idle_slice_timer);
-+
-+		/*
-+		 * The queue is not empty, because a new request just
-+		 * arrived. Hence we can safely expire the queue, in
-+		 * case of budget timeout, without risking that the
-+		 * timestamps of the queue are not updated correctly.
-+		 * See [1] for more details.
-+		 */
-+		if (budget_timeout)
-+			bfq_bfqq_expire(bfqd, bfqq, false,
-+					BFQ_BFQQ_BUDGET_TIMEOUT);
-+	}
-+}
-+
-+/* returns true if it causes the idle timer to be disabled */
-+static bool __bfq_insert_request(struct bfq_data *bfqd, struct request *rq)
-+{
-+	struct bfq_queue *bfqq = RQ_BFQQ(rq), *new_bfqq;
-+	bool waiting, idle_timer_disabled = false;
-+	BUG_ON(!bfqq);
-+
-+	assert_spin_locked(&bfqd->lock);
-+
-+	bfq_log_bfqq(bfqd, bfqq, "rq %p bfqq %p", rq, bfqq);
-+
-+	/*
-+	 * An unplug may trigger a requeue of a request from the device
-+	 * driver: make sure we are in process context while trying to
-+	 * merge two bfq_queues.
-+	 */
-+	if (!in_interrupt()) {
-+		new_bfqq = bfq_setup_cooperator(bfqd, bfqq, rq, true);
-+		if (new_bfqq) {
-+			if (bic_to_bfqq(RQ_BIC(rq), 1) != bfqq)
-+				new_bfqq = bic_to_bfqq(RQ_BIC(rq), 1);
-+			/*
-+			 * Release the request's reference to the old bfqq
-+			 * and make sure one is taken to the shared queue.
-+			 */
-+			new_bfqq->allocated++;
-+			bfqq->allocated--;
-+			bfq_log_bfqq(bfqd, bfqq,
-+		     "new allocated %d", bfqq->allocated);
-+			bfq_log_bfqq(bfqd, new_bfqq,
-+		     "new_bfqq new allocated %d",
-+				     bfqq->allocated);
-+
-+			new_bfqq->ref++;
-+			/*
-+			 * If the bic associated with the process
-+			 * issuing this request still points to bfqq
-+			 * (and thus has not been already redirected
-+			 * to new_bfqq or even some other bfq_queue),
-+			 * then complete the merge and redirect it to
-+			 * new_bfqq.
-+			 */
-+			if (bic_to_bfqq(RQ_BIC(rq), 1) == bfqq)
-+				bfq_merge_bfqqs(bfqd, RQ_BIC(rq),
-+						bfqq, new_bfqq);
-+
-+			bfq_clear_bfqq_just_created(bfqq);
-+			/*
-+			 * rq is about to be enqueued into new_bfqq,
-+			 * release rq reference on bfqq
-+			 */
-+			bfq_put_queue(bfqq);
-+			rq->elv.priv[1] = new_bfqq;
-+			bfqq = new_bfqq;
-+		}
-+	}
-+
-+	waiting = bfqq && bfq_bfqq_wait_request(bfqq);
-+	bfq_add_request(rq);
-+	idle_timer_disabled = waiting && !bfq_bfqq_wait_request(bfqq);
-+
-+	rq->fifo_time = ktime_get_ns() + bfqd->bfq_fifo_expire[rq_is_sync(rq)];
-+	list_add_tail(&rq->queuelist, &bfqq->fifo);
-+
-+	bfq_rq_enqueued(bfqd, bfqq, rq);
-+
-+	return idle_timer_disabled;
-+}
-+
-+#if defined(BFQ_GROUP_IOSCHED_ENABLED) && defined(CONFIG_DEBUG_BLK_CGROUP)
-+static void bfq_update_insert_stats(struct request_queue *q,
-+				    struct bfq_queue *bfqq,
-+				    bool idle_timer_disabled,
-+				    unsigned int cmd_flags)
-+{
-+	if (!bfqq)
-+		return;
-+
-+	/*
-+	 * bfqq still exists, because it can disappear only after
-+	 * either it is merged with another queue, or the process it
-+	 * is associated with exits. But both actions must be taken by
-+	 * the same process currently executing this flow of
-+	 * instructions.
-+	 *
-+	 * In addition, the following queue lock guarantees that
-+	 * bfqq_group(bfqq) exists as well.
-+	 */
-+	spin_lock_irq(q->queue_lock);
-+	bfqg_stats_update_io_add(bfqq_group(bfqq), bfqq, cmd_flags);
-+	if (idle_timer_disabled)
-+		bfqg_stats_update_idle_time(bfqq_group(bfqq));
-+	spin_unlock_irq(q->queue_lock);
-+}
-+#else
-+static inline void bfq_update_insert_stats(struct request_queue *q,
-+					   struct bfq_queue *bfqq,
-+					   bool idle_timer_disabled,
-+					   unsigned int cmd_flags) {}
-+#endif
-+
-+static void bfq_insert_request(struct blk_mq_hw_ctx *hctx, struct request *rq,
-+			       bool at_head)
-+{
-+	struct request_queue *q = hctx->queue;
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+	struct bfq_queue *bfqq;
-+	bool idle_timer_disabled = false;
-+	unsigned int cmd_flags;
-+
-+	spin_lock_irq(&bfqd->lock);
-+	if (blk_mq_sched_try_insert_merge(q, rq)) {
-+		spin_unlock_irq(&bfqd->lock);
-+		return;
-+	}
-+
-+	spin_unlock_irq(&bfqd->lock);
-+
-+	blk_mq_sched_request_inserted(rq);
-+
-+	spin_lock_irq(&bfqd->lock);
-+
-+	bfqq = bfq_init_rq(rq);
-+	BUG_ON(!bfqq && !(at_head || blk_rq_is_passthrough(rq)));
-+	BUG_ON(bfqq && bic_to_bfqq(RQ_BIC(rq), rq_is_sync(rq)) != bfqq);
-+
-+	if (at_head || blk_rq_is_passthrough(rq)) {
-+		if (at_head)
-+			list_add(&rq->queuelist, &bfqd->dispatch);
-+		else
-+			list_add_tail(&rq->queuelist, &bfqd->dispatch);
-+
-+		rq->rq_flags |= RQF_DISP_LIST;
-+		if (bfqq)
-+			bfq_log_bfqq(bfqd, bfqq,
-+				     "%p in disp: at_head %d",
-+				     rq, at_head);
-+		else
-+			bfq_log(bfqd,
-+				"%p in disp: at_head %d",
-+				rq, at_head);
-+	} else { /* bfqq is assumed to be non null here */
-+		BUG_ON(!bfqq);
-+		BUG_ON(!(rq->rq_flags & RQF_GOT));
-+		rq->rq_flags &= ~RQF_GOT;
-+
-+		idle_timer_disabled = __bfq_insert_request(bfqd, rq);
-+		/*
-+		 * Update bfqq, because, if a queue merge has occurred
-+		 * in __bfq_insert_request, then rq has been
-+		 * redirected into a new queue.
-+		 */
-+		bfqq = RQ_BFQQ(rq);
-+
-+		if (rq_mergeable(rq)) {
-+			elv_rqhash_add(q, rq);
-+			if (!q->last_merge)
-+				q->last_merge = rq;
-+		}
-+	}
-+
-+	/*
-+	 * Cache cmd_flags before releasing scheduler lock, because rq
-+	 * may disappear afterwards (for example, because of a request
-+	 * merge).
-+	 */
-+	cmd_flags = rq->cmd_flags;
-+
-+	spin_unlock_irq(&bfqd->lock);
-+	bfq_update_insert_stats(q, bfqq, idle_timer_disabled,
-+				cmd_flags);
-+}
-+
-+static void bfq_insert_requests(struct blk_mq_hw_ctx *hctx,
-+				struct list_head *list, bool at_head)
-+{
-+	while (!list_empty(list)) {
-+		struct request *rq;
-+
-+		rq = list_first_entry(list, struct request, queuelist);
-+		list_del_init(&rq->queuelist);
-+		bfq_insert_request(hctx, rq, at_head);
-+	}
-+}
-+
-+static void bfq_update_hw_tag(struct bfq_data *bfqd)
-+{
-+	bfqd->max_rq_in_driver = max_t(int, bfqd->max_rq_in_driver,
-+				       bfqd->rq_in_driver);
-+
-+	if (bfqd->hw_tag == 1)
-+		return;
-+
-+	/*
-+	 * This sample is valid if the number of outstanding requests
-+	 * is large enough to allow a queueing behavior.  Note that the
-+	 * sum is not exact, as it's not taking into account deactivated
-+	 * requests.
-+	 */
-+	if (bfqd->rq_in_driver + bfqd->queued < BFQ_HW_QUEUE_THRESHOLD)
-+		return;
-+
-+	if (bfqd->hw_tag_samples++ < BFQ_HW_QUEUE_SAMPLES)
-+		return;
-+
-+	bfqd->hw_tag = bfqd->max_rq_in_driver > BFQ_HW_QUEUE_THRESHOLD;
-+	bfqd->max_rq_in_driver = 0;
-+	bfqd->hw_tag_samples = 0;
-+}
-+
-+static void bfq_completed_request(struct bfq_queue *bfqq, struct bfq_data *bfqd)
-+{
-+	u64 now_ns;
-+	u32 delta_us;
-+
-+	bfq_update_hw_tag(bfqd);
-+
-+	BUG_ON(!bfqd->rq_in_driver);
-+	BUG_ON(!bfqq->dispatched);
-+	bfqd->rq_in_driver--;
-+	bfqq->dispatched--;
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+		     "new disp %d, new rq_in_driver %d",
-+		     bfqq->dispatched, bfqd->rq_in_driver);
-+
-+	if (!bfqq->dispatched && !bfq_bfqq_busy(bfqq)) {
-+		BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list));
-+		/*
-+		 * Set budget_timeout (which we overload to store the
-+		 * time at which the queue remains with no backlog and
-+		 * no outstanding request; used by the weight-raising
-+		 * mechanism).
-+		 */
-+		bfqq->budget_timeout = jiffies;
-+
-+		bfq_weights_tree_remove(bfqd, bfqq);
-+	}
-+
-+	now_ns = ktime_get_ns();
-+
-+	bfqq->ttime.last_end_request = now_ns;
-+
-+	/*
-+	 * Using us instead of ns, to get a reasonable precision in
-+	 * computing rate in next check.
-+	 */
-+	delta_us = div_u64(now_ns - bfqd->last_completion, NSEC_PER_USEC);
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+		"delta %uus/%luus max_size %u rate %llu/%llu",
-+		delta_us, BFQ_MIN_TT/NSEC_PER_USEC, bfqd->last_rq_max_size,
-+		delta_us > 0 ?
-+		(USEC_PER_SEC*
-+		(u64)((bfqd->last_rq_max_size<<BFQ_RATE_SHIFT)/delta_us))
-+			>>BFQ_RATE_SHIFT :
-+		(USEC_PER_SEC*
-+		(u64)(bfqd->last_rq_max_size<<BFQ_RATE_SHIFT))>>BFQ_RATE_SHIFT,
-+		(USEC_PER_SEC*(u64)(1UL<<(BFQ_RATE_SHIFT-10)))>>BFQ_RATE_SHIFT);
-+
-+	/*
-+	 * If the request took rather long to complete, and, according
-+	 * to the maximum request size recorded, this completion latency
-+	 * implies that the request was certainly served at a very low
-+	 * rate (less than 1M sectors/sec), then the whole observation
-+	 * interval that lasts up to this time instant cannot be a
-+	 * valid time interval for computing a new peak rate.  Invoke
-+	 * bfq_update_rate_reset to have the following three steps
-+	 * taken:
-+	 * - close the observation interval at the last (previous)
-+	 *   request dispatch or completion
-+	 * - compute rate, if possible, for that observation interval
-+	 * - reset to zero samples, which will trigger a proper
-+	 *   re-initialization of the observation interval on next
-+	 *   dispatch
-+	 */
-+	if (delta_us > BFQ_MIN_TT/NSEC_PER_USEC &&
-+	   (bfqd->last_rq_max_size<<BFQ_RATE_SHIFT)/delta_us <
-+			1UL<<(BFQ_RATE_SHIFT - 10))
-+		bfq_update_rate_reset(bfqd, NULL);
-+	bfqd->last_completion = now_ns;
-+
-+	/*
-+	 * If we are waiting to discover whether the request pattern
-+	 * of the task associated with the queue is actually
-+	 * isochronous, and both requisites for this condition to hold
-+	 * are now satisfied, then compute soft_rt_next_start (see the
-+	 * comments on the function bfq_bfqq_softrt_next_start()). We
-+	 * schedule this delayed check when bfqq expires, if it still
-+	 * has in-flight requests.
-+	 */
-+	if (bfq_bfqq_softrt_update(bfqq) && bfqq->dispatched == 0 &&
-+	    RB_EMPTY_ROOT(&bfqq->sort_list))
-+		bfqq->soft_rt_next_start =
-+			bfq_bfqq_softrt_next_start(bfqd, bfqq);
-+
-+	/*
-+	 * If this is the in-service queue, check if it needs to be expired,
-+	 * or if we want to idle in case it has no pending requests.
-+	 */
-+	if (bfqd->in_service_queue == bfqq) {
-+		if (bfq_bfqq_must_idle(bfqq)) {
-+			if (bfqq->dispatched == 0)
-+				bfq_arm_slice_timer(bfqd);
-+			/*
-+			 * If we get here, we do not expire bfqq, even
-+			 * if bfqq was in budget timeout or had no
-+			 * more requests (as controlled in the next
-+			 * conditional instructions). The reason for
-+			 * not expiring bfqq is as follows.
-+			 *
-+			 * Here bfqq->dispatched > 0 holds, but
-+			 * bfq_bfqq_must_idle() returned true. This
-+			 * implies that, even if no request arrives
-+			 * for bfqq before bfqq->dispatched reaches 0,
-+			 * bfqq will, however, not be expired on the
-+			 * completion event that causes bfqq->dispatch
-+			 * to reach zero. In contrast, on this event,
-+			 * bfqq will start enjoying device idling
-+			 * (I/O-dispatch plugging).
-+			 *
-+			 * But, if we expired bfqq here, bfqq would
-+			 * not have the chance to enjoy device idling
-+			 * when bfqq->dispatched finally reaches
-+			 * zero. This would expose bfqq to violation
-+			 * of its reserved service guarantees.
-+			 */
-+			return;
-+		} else if (bfq_may_expire_for_budg_timeout(bfqq))
-+			bfq_bfqq_expire(bfqd, bfqq, false,
-+					BFQ_BFQQ_BUDGET_TIMEOUT);
-+		else if (RB_EMPTY_ROOT(&bfqq->sort_list) &&
-+			 (bfqq->dispatched == 0 ||
-+			  !bfq_better_to_idle(bfqq)))
-+			bfq_bfqq_expire(bfqd, bfqq, false,
-+					BFQ_BFQQ_NO_MORE_REQUESTS);
-+	}
-+}
-+
-+static void bfq_finish_requeue_request_body(struct bfq_queue *bfqq)
-+{
-+	bfq_log_bfqq(bfqq->bfqd, bfqq,
-+		     "allocated %d", bfqq->allocated);
-+	BUG_ON(!bfqq->allocated);
-+	bfqq->allocated--;
-+
-+	bfq_put_queue(bfqq);
-+}
-+
-+/*
-+ * Handle either a requeue or a finish for rq. The things to do are
-+ * the same in both cases: all references to rq are to be dropped. In
-+ * particular, rq is considered completed from the point of view of
-+ * the scheduler.
-+ */
-+static void bfq_finish_requeue_request(struct request *rq)
-+{
-+	struct bfq_queue *bfqq;
-+	struct bfq_data *bfqd;
-+	struct bfq_io_cq *bic;
-+
-+	BUG_ON(!rq);
-+
-+	bfqq = RQ_BFQQ(rq);
-+
-+	/*
-+	 * Requeue and finish hooks are invoked in blk-mq without
-+	 * checking whether the involved request is actually still
-+	 * referenced in the scheduler. To handle this fact, the
-+	 * following two checks make this function exit in case of
-+	 * spurious invocations, for which there is nothing to do.
-+	 *
-+	 * First, check whether rq has nothing to do with an elevator.
-+	 */
-+	if (unlikely(!(rq->rq_flags & RQF_ELVPRIV)))
-+		return;
-+
-+	/*
-+	 * rq either is not associated with any icq, or is an already
-+	 * requeued request that has not (yet) been re-inserted into
-+	 * a bfq_queue.
-+	 */
-+	if (!rq->elv.icq || !bfqq)
-+		return;
-+
-+	bic = RQ_BIC(rq);
-+	BUG_ON(!bic);
-+
-+	bfqd = bfqq->bfqd;
-+	BUG_ON(!bfqd);
-+
-+	if (rq->rq_flags & RQF_DISP_LIST) {
-+		pr_crit("putting disp rq %p for %d", rq, bfqq->pid);
-+		BUG();
-+	}
-+	BUG_ON(rq->rq_flags & RQF_QUEUED);
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+		     "putting rq %p with %u sects left, STARTED %d",
-+		     rq, blk_rq_sectors(rq),
-+		     rq->rq_flags & RQF_STARTED);
-+
-+	if (rq->rq_flags & RQF_STARTED)
-+		bfqg_stats_update_completion(bfqq_group(bfqq),
-+					     rq->start_time_ns,
-+					     rq->io_start_time_ns,
-+					     rq->cmd_flags);
-+
-+	WARN_ON(blk_rq_sectors(rq) == 0 && !(rq->rq_flags & RQF_STARTED));
-+
-+	if (likely(rq->rq_flags & RQF_STARTED)) {
-+		unsigned long flags;
-+
-+		spin_lock_irqsave(&bfqd->lock, flags);
-+
-+		bfq_completed_request(bfqq, bfqd);
-+		bfq_finish_requeue_request_body(bfqq);
-+
-+		spin_unlock_irqrestore(&bfqd->lock, flags);
-+	} else {
-+		/*
-+		 * Request rq may be still/already in the scheduler,
-+		 * in which case we need to remove it (this should
-+		 * never happen in case of requeue). And we cannot
-+		 * defer such a check and removal, to avoid
-+		 * inconsistencies in the time interval from the end
-+		 * of this function to the start of the deferred work.
-+		 * This situation seems to occur only in process
-+		 * context, as a consequence of a merge. In the
-+		 * current version of the code, this implies that the
-+		 * lock is held.
-+		 */
-+		BUG_ON(in_interrupt());
-+
-+		assert_spin_locked(&bfqd->lock);
-+		if (!RB_EMPTY_NODE(&rq->rb_node)) {
-+			bfq_remove_request(rq->q, rq);
-+			bfqg_stats_update_io_remove(bfqq_group(bfqq),
-+						    rq->cmd_flags);
-+		}
-+		bfq_finish_requeue_request_body(bfqq);
-+	}
-+
-+	/*
-+	 * Reset private fields. In case of a requeue, this allows
-+	 * this function to correctly do nothing if it is spuriously
-+	 * invoked again on this same request (see the check at the
-+	 * beginning of the function). Probably, a better general
-+	 * design would be to prevent blk-mq from invoking the requeue
-+	 * or finish hooks of an elevator, for a request that is not
-+	 * referred by that elevator.
-+	 *
-+	 * Resetting the following fields would break the
-+	 * request-insertion logic if rq is re-inserted into a bfq
-+	 * internal queue, without a re-preparation. Here we assume
-+	 * that re-insertions of requeued requests, without
-+	 * re-preparation, can happen only for pass_through or at_head
-+	 * requests (which are not re-inserted into bfq internal
-+	 * queues).
-+	 */
-+	rq->elv.priv[0] = NULL;
-+	rq->elv.priv[1] = NULL;
-+}
-+
-+/*
-+ * Returns NULL if a new bfqq should be allocated, or the old bfqq if this
-+ * was the last process referring to that bfqq.
-+ */
-+static struct bfq_queue *
-+bfq_split_bfqq(struct bfq_io_cq *bic, struct bfq_queue *bfqq)
-+{
-+	bfq_log_bfqq(bfqq->bfqd, bfqq, "splitting queue");
-+
-+	if (bfqq_process_refs(bfqq) == 1) {
-+		bfqq->pid = current->pid;
-+		bfq_clear_bfqq_coop(bfqq);
-+		bfq_clear_bfqq_split_coop(bfqq);
-+		return bfqq;
-+	}
-+
-+	bic_set_bfqq(bic, NULL, 1);
-+
-+	bfq_put_cooperator(bfqq);
-+
-+	bfq_put_queue(bfqq);
-+	return NULL;
-+}
-+
-+static struct bfq_queue *bfq_get_bfqq_handle_split(struct bfq_data *bfqd,
-+						   struct bfq_io_cq *bic,
-+						   struct bio *bio,
-+						   bool split, bool is_sync,
-+						   bool *new_queue)
-+{
-+	struct bfq_queue *bfqq = bic_to_bfqq(bic, is_sync);
-+
-+	if (likely(bfqq && bfqq != &bfqd->oom_bfqq))
-+		return bfqq;
-+
-+	if (new_queue)
-+		*new_queue = true;
-+
-+	if (bfqq)
-+		bfq_put_queue(bfqq);
-+	bfqq = bfq_get_queue(bfqd, bio, is_sync, bic);
-+	BUG_ON(!hlist_unhashed(&bfqq->burst_list_node));
-+
-+	bic_set_bfqq(bic, bfqq, is_sync);
-+	if (split && is_sync) {
-+		bfq_log_bfqq(bfqd, bfqq,
-+			     "get_request: was_in_list %d "
-+			     "was_in_large_burst %d "
-+			     "large burst in progress %d",
-+			     bic->was_in_burst_list,
-+			     bic->saved_in_large_burst,
-+			     bfqd->large_burst);
-+
-+		if ((bic->was_in_burst_list && bfqd->large_burst) ||
-+		    bic->saved_in_large_burst) {
-+			bfq_log_bfqq(bfqd, bfqq,
-+				     "get_request: marking in "
-+				     "large burst");
-+			bfq_mark_bfqq_in_large_burst(bfqq);
-+		} else {
-+			bfq_log_bfqq(bfqd, bfqq,
-+				     "get_request: clearing in "
-+				     "large burst");
-+			bfq_clear_bfqq_in_large_burst(bfqq);
-+			if (bic->was_in_burst_list)
-+				/*
-+				 * If bfqq was in the current
-+				 * burst list before being
-+				 * merged, then we have to add
-+				 * it back. And we do not need
-+				 * to increase burst_size, as
-+				 * we did not decrement
-+				 * burst_size when we removed
-+				 * bfqq from the burst list as
-+				 * a consequence of a merge
-+				 * (see comments in
-+				 * bfq_put_queue). In this
-+				 * respect, it would be rather
-+				 * costly to know whether the
-+				 * current burst list is still
-+				 * the same burst list from
-+				 * which bfqq was removed on
-+				 * the merge. To avoid this
-+				 * cost, if bfqq was in a
-+				 * burst list, then we add
-+				 * bfqq to the current burst
-+				 * list without any further
-+				 * check. This can cause
-+				 * inappropriate insertions,
-+				 * but rarely enough to not
-+				 * harm the detection of large
-+				 * bursts significantly.
-+				 */
-+				hlist_add_head(&bfqq->burst_list_node,
-+					       &bfqd->burst_list);
-+		}
-+		bfqq->split_time = jiffies;
-+	}
-+
-+	return bfqq;
-+}
-+
-+/*
-+ * Only reset private fields. The actual request preparation will be
-+ * performed by bfq_init_rq, when rq is either inserted or merged. See
-+ * comments on bfq_init_rq for the reason behind this delayed
-+ * preparation.
-+*/
-+static void bfq_prepare_request(struct request *rq, struct bio *bio)
-+{
-+	/*
-+	 * Regardless of whether we have an icq attached, we have to
-+	 * clear the scheduler pointers, as they might point to
-+	 * previously allocated bic/bfqq structs.
-+	 */
-+	rq->elv.priv[0] = rq->elv.priv[1] = NULL;
-+}
-+
-+/*
-+ * If needed, init rq, allocate bfq data structures associated with
-+ * rq, and increment reference counters in the destination bfq_queue
-+ * for rq. Return the destination bfq_queue for rq, or NULL is rq is
-+ * not associated with any bfq_queue.
-+ *
-+ * This function is invoked by the functions that perform rq insertion
-+ * or merging. One may have expected the above preparation operations
-+ * to be performed in bfq_prepare_request, and not delayed to when rq
-+ * is inserted or merged. The rationale behind this delayed
-+ * preparation is that, after the prepare_request hook is invoked for
-+ * rq, rq may still be transformed into a request with no icq, i.e., a
-+ * request not associated with any queue. No bfq hook is invoked to
-+ * signal this tranformation. As a consequence, should these
-+ * preparation operations be performed when the prepare_request hook
-+ * is invoked, and should rq be transformed one moment later, bfq
-+ * would end up in an inconsistent state, because it would have
-+ * incremented some queue counters for an rq destined to
-+ * transformation, without any chance to correctly lower these
-+ * counters back. In contrast, no transformation can still happen for
-+ * rq after rq has been inserted or merged. So, it is safe to execute
-+ * these preparation operations when rq is finally inserted or merged.
-+ */
-+static struct bfq_queue *bfq_init_rq(struct request *rq)
-+{
-+	struct request_queue *q = rq->q;
-+	struct bio *bio = rq->bio;
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+	struct bfq_io_cq *bic;
-+	const int is_sync = rq_is_sync(rq);
-+	struct bfq_queue *bfqq;
-+	bool bfqq_already_existing = false, split = false;
-+	bool new_queue = false;
-+
-+	if (unlikely(!rq->elv.icq))
-+		return NULL;
-+
-+	/*
-+	 * Assuming that elv.priv[1] is set only if everything is set
-+	 * for this rq. This holds true, because this function is
-+	 * invoked only for insertion or merging, and, after such
-+	 * events, a request cannot be manipulated any longer before
-+	 * being removed from bfq.
-+	 */
-+	if (rq->elv.priv[1]) {
-+		BUG_ON(!(rq->rq_flags & RQF_ELVPRIV));
-+		return rq->elv.priv[1];
-+	}
-+
-+	bic = icq_to_bic(rq->elv.icq);
-+
-+	bfq_check_ioprio_change(bic, bio);
-+
-+	bfq_bic_update_cgroup(bic, bio);
-+
-+	bfqq = bfq_get_bfqq_handle_split(bfqd, bic, bio, false, is_sync,
-+					 &new_queue);
-+
-+	if (likely(!new_queue)) {
-+		/* If the queue was seeky for too long, break it apart. */
-+		if (bfq_bfqq_coop(bfqq) && bfq_bfqq_split_coop(bfqq)) {
-+			BUG_ON(!is_sync);
-+			bfq_log_bfqq(bfqd, bfqq, "breaking apart bfqq");
-+
-+			/* Update bic before losing reference to bfqq */
-+			if (bfq_bfqq_in_large_burst(bfqq))
-+				bic->saved_in_large_burst = true;
-+
-+			bfqq = bfq_split_bfqq(bic, bfqq);
-+			split = true;
-+
-+			if (!bfqq)
-+				bfqq = bfq_get_bfqq_handle_split(bfqd, bic, bio,
-+								 true, is_sync,
-+								 NULL);
-+			else
-+				bfqq_already_existing = true;
-+
-+			BUG_ON(!bfqq);
-+			BUG_ON(bfqq == &bfqd->oom_bfqq);
-+		}
-+	}
-+
-+	bfqq->allocated++;
-+	bfq_log_bfqq(bfqq->bfqd, bfqq,
-+		     "new allocated %d", bfqq->allocated);
-+
-+	bfqq->ref++;
-+	bfq_log_bfqq(bfqd, bfqq, "%p: bfqq %p, %d", rq, bfqq, bfqq->ref);
-+
-+	rq->elv.priv[0] = bic;
-+	rq->elv.priv[1] = bfqq;
-+	rq->rq_flags &= ~RQF_DISP_LIST;
-+
-+	/*
-+	 * If a bfq_queue has only one process reference, it is owned
-+	 * by only this bic: we can then set bfqq->bic = bic. in
-+	 * addition, if the queue has also just been split, we have to
-+	 * resume its state.
-+	 */
-+	if (likely(bfqq != &bfqd->oom_bfqq) && bfqq_process_refs(bfqq) == 1) {
-+		bfqq->bic = bic;
-+		if (split) {
-+			/*
-+			 * The queue has just been split from a shared
-+			 * queue: restore the idle window and the
-+			 * possible weight raising period.
-+			 */
-+			bfq_bfqq_resume_state(bfqq, bfqd, bic,
-+					      bfqq_already_existing);
-+		}
-+	}
-+
-+	if (unlikely(bfq_bfqq_just_created(bfqq)))
-+		bfq_handle_burst(bfqd, bfqq);
-+
-+	rq->rq_flags |= RQF_GOT;
-+
-+	return bfqq;
-+}
-+
-+static void bfq_idle_slice_timer_body(struct bfq_queue *bfqq)
-+{
-+	struct bfq_data *bfqd = bfqq->bfqd;
-+	enum bfqq_expiration reason;
-+	unsigned long flags;
-+
-+	BUG_ON(!bfqd);
-+	spin_lock_irqsave(&bfqd->lock, flags);
-+
-+	bfq_log_bfqq(bfqd, bfqq, "handling slice_timer expiration");
-+	bfq_clear_bfqq_wait_request(bfqq);
-+
-+	if (bfqq != bfqd->in_service_queue) {
-+		spin_unlock_irqrestore(&bfqd->lock, flags);
-+		return;
-+	}
-+
-+	if (bfq_bfqq_budget_timeout(bfqq))
-+		/*
-+		 * Also here the queue can be safely expired
-+		 * for budget timeout without wasting
-+		 * guarantees
-+		 */
-+		reason = BFQ_BFQQ_BUDGET_TIMEOUT;
-+	else if (bfqq->queued[0] == 0 && bfqq->queued[1] == 0)
-+		/*
-+		 * The queue may not be empty upon timer expiration,
-+		 * because we may not disable the timer when the
-+		 * first request of the in-service queue arrives
-+		 * during disk idling.
-+		 */
-+		reason = BFQ_BFQQ_TOO_IDLE;
-+	else
-+		goto schedule_dispatch;
-+
-+	bfq_bfqq_expire(bfqd, bfqq, true, reason);
-+
-+schedule_dispatch:
-+	spin_unlock_irqrestore(&bfqd->lock, flags);
-+	bfq_schedule_dispatch(bfqd);
-+}
-+
-+/*
-+ * Handler of the expiration of the timer running if the in-service queue
-+ * is idling inside its time slice.
-+ */
-+static enum hrtimer_restart bfq_idle_slice_timer(struct hrtimer *timer)
-+{
-+	struct bfq_data *bfqd = container_of(timer, struct bfq_data,
-+					     idle_slice_timer);
-+	struct bfq_queue *bfqq = bfqd->in_service_queue;
-+
-+	bfq_log(bfqd, "expired");
-+
-+	/*
-+	 * Theoretical race here: the in-service queue can be NULL or
-+	 * different from the queue that was idling if a new request
-+	 * arrives for the current queue and there is a full dispatch
-+	 * cycle that changes the in-service queue.  This can hardly
-+	 * happen, but in the worst case we just expire a queue too
-+	 * early.
-+	 */
-+	if (bfqq)
-+		bfq_idle_slice_timer_body(bfqq);
-+
-+	return HRTIMER_NORESTART;
-+}
-+
-+static void __bfq_put_async_bfqq(struct bfq_data *bfqd,
-+				 struct bfq_queue **bfqq_ptr)
-+{
-+	struct bfq_group *root_group = bfqd->root_group;
-+	struct bfq_queue *bfqq = *bfqq_ptr;
-+
-+	bfq_log(bfqd, "%p", bfqq);
-+	if (bfqq) {
-+		bfq_bfqq_move(bfqd, bfqq, root_group);
-+		bfq_log_bfqq(bfqd, bfqq, "putting %p, %d",
-+			     bfqq, bfqq->ref);
-+		bfq_put_queue(bfqq);
-+		*bfqq_ptr = NULL;
-+	}
-+}
-+
-+/*
-+ * Release all the bfqg references to its async queues.  If we are
-+ * deallocating the group these queues may still contain requests, so
-+ * we reparent them to the root cgroup (i.e., the only one that will
-+ * exist for sure until all the requests on a device are gone).
-+ */
-+static void bfq_put_async_queues(struct bfq_data *bfqd, struct bfq_group *bfqg)
-+{
-+	int i, j;
-+
-+	for (i = 0; i < 2; i++)
-+		for (j = 0; j < IOPRIO_BE_NR; j++)
-+			__bfq_put_async_bfqq(bfqd, &bfqg->async_bfqq[i][j]);
-+
-+	__bfq_put_async_bfqq(bfqd, &bfqg->async_idle_bfqq);
-+}
-+
-+static void bfq_exit_queue(struct elevator_queue *e)
-+{
-+	struct bfq_data *bfqd = e->elevator_data;
-+	struct bfq_queue *bfqq, *n;
-+
-+	bfq_log(bfqd, "starting ...");
-+
-+	hrtimer_cancel(&bfqd->idle_slice_timer);
-+
-+	BUG_ON(bfqd->in_service_queue);
-+	BUG_ON(!list_empty(&bfqd->active_list));
-+
-+	spin_lock_irq(&bfqd->lock);
-+	list_for_each_entry_safe(bfqq, n, &bfqd->idle_list, bfqq_list)
-+		bfq_deactivate_bfqq(bfqd, bfqq, false, false);
-+	spin_unlock_irq(&bfqd->lock);
-+
-+	hrtimer_cancel(&bfqd->idle_slice_timer);
-+
-+	BUG_ON(hrtimer_active(&bfqd->idle_slice_timer));
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	/* release oom-queue reference to root group */
-+	bfqg_and_blkg_put(bfqd->root_group);
-+
-+	blkcg_deactivate_policy(bfqd->queue, &blkcg_policy_bfq);
-+#else
-+	spin_lock_irq(&bfqd->lock);
-+	bfq_put_async_queues(bfqd, bfqd->root_group);
-+	kfree(bfqd->root_group);
-+	spin_unlock_irq(&bfqd->lock);
-+#endif
-+
-+	bfq_log(bfqd, "finished ...");
-+	kfree(bfqd);
-+}
-+
-+static void bfq_init_root_group(struct bfq_group *root_group,
-+				struct bfq_data *bfqd)
-+{
-+	int i;
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	root_group->entity.parent = NULL;
-+	root_group->my_entity = NULL;
-+	root_group->bfqd = bfqd;
-+#endif
-+	root_group->rq_pos_tree = RB_ROOT;
-+	for (i = 0; i < BFQ_IOPRIO_CLASSES; i++)
-+		root_group->sched_data.service_tree[i] = BFQ_SERVICE_TREE_INIT;
-+	root_group->sched_data.bfq_class_idle_last_service = jiffies;
-+}
-+
-+static int bfq_init_queue(struct request_queue *q, struct elevator_type *e)
-+{
-+	struct bfq_data *bfqd;
-+	struct elevator_queue *eq;
-+
-+	eq = elevator_alloc(q, e);
-+	if (!eq)
-+		return -ENOMEM;
-+
-+	bfqd = kzalloc_node(sizeof(*bfqd), GFP_KERNEL, q->node);
-+	if (!bfqd) {
-+		kobject_put(&eq->kobj);
-+		return -ENOMEM;
-+	}
-+	eq->elevator_data = bfqd;
-+
-+	spin_lock_irq(q->queue_lock);
-+	q->elevator = eq;
-+	spin_unlock_irq(q->queue_lock);
-+
-+	/*
-+	 * Our fallback bfqq if bfq_find_alloc_queue() runs into OOM issues.
-+	 * Grab a permanent reference to it, so that the normal code flow
-+	 * will not attempt to free it.
-+	 */
-+	bfq_init_bfqq(bfqd, &bfqd->oom_bfqq, NULL, 1, 0);
-+	bfqd->oom_bfqq.ref++;
-+	bfqd->oom_bfqq.new_ioprio = BFQ_DEFAULT_QUEUE_IOPRIO;
-+	bfqd->oom_bfqq.new_ioprio_class = IOPRIO_CLASS_BE;
-+	bfqd->oom_bfqq.entity.new_weight =
-+		bfq_ioprio_to_weight(bfqd->oom_bfqq.new_ioprio);
-+
-+	/* oom_bfqq does not participate to bursts */
-+	bfq_clear_bfqq_just_created(&bfqd->oom_bfqq);
-+	/*
-+	 * Trigger weight initialization, according to ioprio, at the
-+	 * oom_bfqq's first activation. The oom_bfqq's ioprio and ioprio
-+	 * class won't be changed any more.
-+	 */
-+	bfqd->oom_bfqq.entity.prio_changed = 1;
-+
-+	bfqd->queue = q;
-+	INIT_LIST_HEAD(&bfqd->dispatch);
-+
-+	hrtimer_init(&bfqd->idle_slice_timer, CLOCK_MONOTONIC,
-+		     HRTIMER_MODE_REL);
-+	bfqd->idle_slice_timer.function = bfq_idle_slice_timer;
-+
-+	bfqd->queue_weights_tree = RB_ROOT;
-+	bfqd->group_weights_tree = RB_ROOT;
-+
-+	INIT_LIST_HEAD(&bfqd->active_list);
-+	INIT_LIST_HEAD(&bfqd->idle_list);
-+	INIT_HLIST_HEAD(&bfqd->burst_list);
-+
-+	bfqd->hw_tag = -1;
-+
-+	bfqd->bfq_max_budget = bfq_default_max_budget;
-+
-+	bfqd->bfq_fifo_expire[0] = bfq_fifo_expire[0];
-+	bfqd->bfq_fifo_expire[1] = bfq_fifo_expire[1];
-+	bfqd->bfq_back_max = bfq_back_max;
-+	bfqd->bfq_back_penalty = bfq_back_penalty;
-+	bfqd->bfq_slice_idle = bfq_slice_idle;
-+	bfqd->bfq_timeout = bfq_timeout;
-+
-+	bfqd->bfq_requests_within_timer = 120;
-+
-+	bfqd->bfq_large_burst_thresh = 8;
-+	bfqd->bfq_burst_interval = msecs_to_jiffies(180);
-+
-+	bfqd->low_latency = true;
-+
-+	/*
-+	 * Trade-off between responsiveness and fairness.
-+	 */
-+	bfqd->bfq_wr_coeff = 30;
-+	bfqd->bfq_wr_rt_max_time = msecs_to_jiffies(300);
-+	bfqd->bfq_wr_max_time = 0;
-+	bfqd->bfq_wr_min_idle_time = msecs_to_jiffies(2000);
-+	bfqd->bfq_wr_min_inter_arr_async = msecs_to_jiffies(500);
-+	bfqd->bfq_wr_max_softrt_rate = 7000; /*
-+					      * Approximate rate required
-+					      * to playback or record a
-+					      * high-definition compressed
-+					      * video.
-+					      */
-+	bfqd->wr_busy_queues = 0;
-+
-+	/*
-+	 * Begin by assuming, optimistically, that the device peak
-+	 * rate is equal to 2/3 of the highest reference rate.
-+	 */
-+	bfqd->rate_dur_prod = ref_rate[blk_queue_nonrot(bfqd->queue)] *
-+		ref_wr_duration[blk_queue_nonrot(bfqd->queue)];
-+	bfqd->peak_rate = ref_rate[blk_queue_nonrot(bfqd->queue)] * 2 / 3;
-+
-+	spin_lock_init(&bfqd->lock);
-+
-+	/*
-+	 * The invocation of the next bfq_create_group_hierarchy
-+	 * function is the head of a chain of function calls
-+	 * (bfq_create_group_hierarchy->blkcg_activate_policy->
-+	 * blk_mq_freeze_queue) that may lead to the invocation of the
-+	 * has_work hook function. For this reason,
-+	 * bfq_create_group_hierarchy is invoked only after all
-+	 * scheduler data has been initialized, apart from the fields
-+	 * that can be initialized only after invoking
-+	 * bfq_create_group_hierarchy. This, in particular, enables
-+	 * has_work to correctly return false. Of course, to avoid
-+	 * other inconsistencies, the blk-mq stack must then refrain
-+	 * from invoking further scheduler hooks before this init
-+	 * function is finished.
-+	*/
-+	bfqd->root_group = bfq_create_group_hierarchy(bfqd, q->node);
-+	if (!bfqd->root_group)
-+		goto out_free;
-+	bfq_init_root_group(bfqd->root_group, bfqd);
-+	bfq_init_entity(&bfqd->oom_bfqq.entity, bfqd->root_group);
-+
-+	wbt_disable_default(q);
-+	return 0;
-+
-+out_free:
-+	kfree(bfqd);
-+	kobject_put(&eq->kobj);
-+	return -ENOMEM;
-+}
-+
-+static void bfq_slab_kill(void)
-+{
-+	kmem_cache_destroy(bfq_pool);
-+}
-+
-+static int __init bfq_slab_setup(void)
-+{
-+	bfq_pool = KMEM_CACHE(bfq_queue, 0);
-+	if (!bfq_pool)
-+		return -ENOMEM;
-+	return 0;
-+}
-+
-+static ssize_t bfq_var_show(unsigned int var, char *page)
-+{
-+	return sprintf(page, "%u\n", var);
-+}
-+
-+static ssize_t bfq_var_store(unsigned long *var, const char *page,
-+			     size_t count)
-+{
-+	unsigned long new_val;
-+	int ret = kstrtoul(page, 10, &new_val);
-+
-+	if (ret == 0)
-+		*var = new_val;
-+
-+	return count;
-+}
-+
-+static ssize_t bfq_wr_max_time_show(struct elevator_queue *e, char *page)
-+{
-+	struct bfq_data *bfqd = e->elevator_data;
-+
-+	return sprintf(page, "%d\n", bfqd->bfq_wr_max_time > 0 ?
-+		       jiffies_to_msecs(bfqd->bfq_wr_max_time) :
-+		       jiffies_to_msecs(bfq_wr_duration(bfqd)));
-+}
-+
-+static ssize_t bfq_weights_show(struct elevator_queue *e, char *page)
-+{
-+	struct bfq_queue *bfqq;
-+	struct bfq_data *bfqd = e->elevator_data;
-+	ssize_t num_char = 0;
-+
-+	num_char += sprintf(page + num_char, "Tot reqs queued %d\n\n",
-+			    bfqd->queued);
-+
-+	spin_lock_irq(&bfqd->lock);
-+
-+	num_char += sprintf(page + num_char, "Active:\n");
-+	list_for_each_entry(bfqq, &bfqd->active_list, bfqq_list) {
-+		num_char += sprintf(page + num_char,
-+				    "pid%d: weight %hu, nr_queued %d %d, ",
-+				    bfqq->pid,
-+				    bfqq->entity.weight,
-+				    bfqq->queued[0],
-+				    bfqq->queued[1]);
-+		num_char += sprintf(page + num_char,
-+				    "dur %d/%u\n",
-+				    jiffies_to_msecs(
-+					    jiffies -
-+					    bfqq->last_wr_start_finish),
-+				    jiffies_to_msecs(bfqq->wr_cur_max_time));
-+	}
-+
-+	num_char += sprintf(page + num_char, "Idle:\n");
-+	list_for_each_entry(bfqq, &bfqd->idle_list, bfqq_list) {
-+		num_char += sprintf(page + num_char,
-+				    "pid%d: weight %hu, dur %d/%u\n",
-+				    bfqq->pid,
-+				    bfqq->entity.weight,
-+				    jiffies_to_msecs(jiffies -
-+						     bfqq->last_wr_start_finish),
-+				    jiffies_to_msecs(bfqq->wr_cur_max_time));
-+	}
-+
-+	spin_unlock_irq(&bfqd->lock);
-+
-+	return num_char;
-+}
-+
-+#define SHOW_FUNCTION(__FUNC, __VAR, __CONV)				\
-+static ssize_t __FUNC(struct elevator_queue *e, char *page)		\
-+{									\
-+	struct bfq_data *bfqd = e->elevator_data;			\
-+	u64 __data = __VAR;						\
-+	if (__CONV == 1)						\
-+		__data = jiffies_to_msecs(__data);			\
-+	else if (__CONV == 2)						\
-+		__data = div_u64(__data, NSEC_PER_MSEC);		\
-+	return bfq_var_show(__data, (page));				\
-+}
-+SHOW_FUNCTION(bfq_fifo_expire_sync_show, bfqd->bfq_fifo_expire[1], 2);
-+SHOW_FUNCTION(bfq_fifo_expire_async_show, bfqd->bfq_fifo_expire[0], 2);
-+SHOW_FUNCTION(bfq_back_seek_max_show, bfqd->bfq_back_max, 0);
-+SHOW_FUNCTION(bfq_back_seek_penalty_show, bfqd->bfq_back_penalty, 0);
-+SHOW_FUNCTION(bfq_slice_idle_show, bfqd->bfq_slice_idle, 2);
-+SHOW_FUNCTION(bfq_max_budget_show, bfqd->bfq_user_max_budget, 0);
-+SHOW_FUNCTION(bfq_timeout_sync_show, bfqd->bfq_timeout, 1);
-+SHOW_FUNCTION(bfq_strict_guarantees_show, bfqd->strict_guarantees, 0);
-+SHOW_FUNCTION(bfq_low_latency_show, bfqd->low_latency, 0);
-+SHOW_FUNCTION(bfq_wr_coeff_show, bfqd->bfq_wr_coeff, 0);
-+SHOW_FUNCTION(bfq_wr_rt_max_time_show, bfqd->bfq_wr_rt_max_time, 1);
-+SHOW_FUNCTION(bfq_wr_min_idle_time_show, bfqd->bfq_wr_min_idle_time, 1);
-+SHOW_FUNCTION(bfq_wr_min_inter_arr_async_show, bfqd->bfq_wr_min_inter_arr_async,
-+	1);
-+SHOW_FUNCTION(bfq_wr_max_softrt_rate_show, bfqd->bfq_wr_max_softrt_rate, 0);
-+#undef SHOW_FUNCTION
-+
-+#define USEC_SHOW_FUNCTION(__FUNC, __VAR)				\
-+static ssize_t __FUNC(struct elevator_queue *e, char *page)		\
-+{									\
-+	struct bfq_data *bfqd = e->elevator_data;			\
-+	u64 __data = __VAR;						\
-+	__data = div_u64(__data, NSEC_PER_USEC);			\
-+	return bfq_var_show(__data, (page));				\
-+}
-+USEC_SHOW_FUNCTION(bfq_slice_idle_us_show, bfqd->bfq_slice_idle);
-+#undef USEC_SHOW_FUNCTION
-+
-+#define STORE_FUNCTION(__FUNC, __PTR, MIN, MAX, __CONV)			\
-+static ssize_t								\
-+__FUNC(struct elevator_queue *e, const char *page, size_t count)	\
-+{									\
-+	struct bfq_data *bfqd = e->elevator_data;			\
-+	unsigned long uninitialized_var(__data);			\
-+	int ret = bfq_var_store(&__data, (page), count);		\
-+	if (__data < (MIN))						\
-+		__data = (MIN);						\
-+	else if (__data > (MAX))					\
-+		__data = (MAX);						\
-+	if (__CONV == 1)						\
-+		*(__PTR) = msecs_to_jiffies(__data);			\
-+	else if (__CONV == 2)						\
-+		*(__PTR) = (u64)__data * NSEC_PER_MSEC;			\
-+	else								\
-+		*(__PTR) = __data;					\
-+	return ret;							\
-+}
-+STORE_FUNCTION(bfq_fifo_expire_sync_store, &bfqd->bfq_fifo_expire[1], 1,
-+		INT_MAX, 2);
-+STORE_FUNCTION(bfq_fifo_expire_async_store, &bfqd->bfq_fifo_expire[0], 1,
-+		INT_MAX, 2);
-+STORE_FUNCTION(bfq_back_seek_max_store, &bfqd->bfq_back_max, 0, INT_MAX, 0);
-+STORE_FUNCTION(bfq_back_seek_penalty_store, &bfqd->bfq_back_penalty, 1,
-+		INT_MAX, 0);
-+STORE_FUNCTION(bfq_slice_idle_store, &bfqd->bfq_slice_idle, 0, INT_MAX, 2);
-+STORE_FUNCTION(bfq_wr_coeff_store, &bfqd->bfq_wr_coeff, 1, INT_MAX, 0);
-+STORE_FUNCTION(bfq_wr_max_time_store, &bfqd->bfq_wr_max_time, 0, INT_MAX, 1);
-+STORE_FUNCTION(bfq_wr_rt_max_time_store, &bfqd->bfq_wr_rt_max_time, 0, INT_MAX,
-+		1);
-+STORE_FUNCTION(bfq_wr_min_idle_time_store, &bfqd->bfq_wr_min_idle_time, 0,
-+		INT_MAX, 1);
-+STORE_FUNCTION(bfq_wr_min_inter_arr_async_store,
-+		&bfqd->bfq_wr_min_inter_arr_async, 0, INT_MAX, 1);
-+STORE_FUNCTION(bfq_wr_max_softrt_rate_store, &bfqd->bfq_wr_max_softrt_rate, 0,
-+		INT_MAX, 0);
-+#undef STORE_FUNCTION
-+
-+#define USEC_STORE_FUNCTION(__FUNC, __PTR, MIN, MAX)			\
-+static ssize_t __FUNC(struct elevator_queue *e, const char *page, size_t count)\
-+{									\
-+	struct bfq_data *bfqd = e->elevator_data;			\
-+	unsigned long uninitialized_var(__data);			\
-+	int ret = bfq_var_store(&__data, (page), count);		\
-+	if (__data < (MIN))						\
-+		__data = (MIN);						\
-+	else if (__data > (MAX))					\
-+		__data = (MAX);						\
-+	*(__PTR) = (u64)__data * NSEC_PER_USEC;				\
-+	return ret;							\
-+}
-+USEC_STORE_FUNCTION(bfq_slice_idle_us_store, &bfqd->bfq_slice_idle, 0,
-+		    UINT_MAX);
-+#undef USEC_STORE_FUNCTION
-+
-+/* do nothing for the moment */
-+static ssize_t bfq_weights_store(struct elevator_queue *e,
-+				    const char *page, size_t count)
-+{
-+	return count;
-+}
-+
-+static ssize_t bfq_max_budget_store(struct elevator_queue *e,
-+				    const char *page, size_t count)
-+{
-+	struct bfq_data *bfqd = e->elevator_data;
-+	unsigned long uninitialized_var(__data);
-+	int ret = bfq_var_store(&__data, (page), count);
-+
-+	if (__data == 0)
-+		bfqd->bfq_max_budget = bfq_calc_max_budget(bfqd);
-+	else {
-+		if (__data > INT_MAX)
-+			__data = INT_MAX;
-+		bfqd->bfq_max_budget = __data;
-+	}
-+
-+	bfqd->bfq_user_max_budget = __data;
-+
-+	return ret;
-+}
-+
-+/*
-+ * Leaving this name to preserve name compatibility with cfq
-+ * parameters, but this timeout is used for both sync and async.
-+ */
-+static ssize_t bfq_timeout_sync_store(struct elevator_queue *e,
-+				      const char *page, size_t count)
-+{
-+	struct bfq_data *bfqd = e->elevator_data;
-+	unsigned long uninitialized_var(__data);
-+	int ret = bfq_var_store(&__data, (page), count);
-+
-+	if (__data < 1)
-+		__data = 1;
-+	else if (__data > INT_MAX)
-+		__data = INT_MAX;
-+
-+	bfqd->bfq_timeout = msecs_to_jiffies(__data);
-+	if (bfqd->bfq_user_max_budget == 0)
-+		bfqd->bfq_max_budget = bfq_calc_max_budget(bfqd);
-+
-+	return ret;
-+}
-+
-+static ssize_t bfq_strict_guarantees_store(struct elevator_queue *e,
-+				     const char *page, size_t count)
-+{
-+	struct bfq_data *bfqd = e->elevator_data;
-+	unsigned long uninitialized_var(__data);
-+	int ret = bfq_var_store(&__data, (page), count);
-+
-+	if (__data > 1)
-+		__data = 1;
-+	if (!bfqd->strict_guarantees && __data == 1
-+	    && bfqd->bfq_slice_idle < 8 * NSEC_PER_MSEC)
-+		bfqd->bfq_slice_idle = 8 * NSEC_PER_MSEC;
-+
-+	bfqd->strict_guarantees = __data;
-+
-+	return ret;
-+}
-+
-+static ssize_t bfq_low_latency_store(struct elevator_queue *e,
-+				     const char *page, size_t count)
-+{
-+	struct bfq_data *bfqd = e->elevator_data;
-+	unsigned long uninitialized_var(__data);
-+	int ret = bfq_var_store(&__data, (page), count);
-+
-+	if (__data > 1)
-+		__data = 1;
-+	if (__data == 0 && bfqd->low_latency != 0)
-+		bfq_end_wr(bfqd);
-+	bfqd->low_latency = __data;
-+
-+	return ret;
-+}
-+
-+#define BFQ_ATTR(name) \
-+	__ATTR(name, S_IRUGO|S_IWUSR, bfq_##name##_show, bfq_##name##_store)
-+
-+static struct elv_fs_entry bfq_attrs[] = {
-+	BFQ_ATTR(fifo_expire_sync),
-+	BFQ_ATTR(fifo_expire_async),
-+	BFQ_ATTR(back_seek_max),
-+	BFQ_ATTR(back_seek_penalty),
-+	BFQ_ATTR(slice_idle),
-+	BFQ_ATTR(slice_idle_us),
-+	BFQ_ATTR(max_budget),
-+	BFQ_ATTR(timeout_sync),
-+	BFQ_ATTR(strict_guarantees),
-+	BFQ_ATTR(low_latency),
-+	BFQ_ATTR(wr_coeff),
-+	BFQ_ATTR(wr_max_time),
-+	BFQ_ATTR(wr_rt_max_time),
-+	BFQ_ATTR(wr_min_idle_time),
-+	BFQ_ATTR(wr_min_inter_arr_async),
-+	BFQ_ATTR(wr_max_softrt_rate),
-+	BFQ_ATTR(weights),
-+	__ATTR_NULL
-+};
-+
-+static struct elevator_type iosched_bfq_mq = {
-+	.ops.mq = {
-+		.limit_depth		= bfq_limit_depth,
-+		.prepare_request        = bfq_prepare_request,
-+		.requeue_request	= bfq_finish_requeue_request,
-+		.finish_request         = bfq_finish_requeue_request,
-+		.exit_icq		= bfq_exit_icq,
-+		.insert_requests	= bfq_insert_requests,
-+		.dispatch_request	= bfq_dispatch_request,
-+		.next_request		= elv_rb_latter_request,
-+		.former_request		= elv_rb_former_request,
-+		.allow_merge		= bfq_allow_bio_merge,
-+		.bio_merge		= bfq_bio_merge,
-+		.request_merge		= bfq_request_merge,
-+		.requests_merged	= bfq_requests_merged,
-+		.request_merged		= bfq_request_merged,
-+		.has_work		= bfq_has_work,
-+		.init_sched		= bfq_init_queue,
-+		.exit_sched		= bfq_exit_queue,
-+	},
-+
-+	.uses_mq = 		true,
-+	.icq_size =		sizeof(struct bfq_io_cq),
-+	.icq_align =		__alignof__(struct bfq_io_cq),
-+	.elevator_attrs =	bfq_attrs,
-+	.elevator_name =	"bfq-mq",
-+	.elevator_owner =	THIS_MODULE,
-+};
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+static struct blkcg_policy blkcg_policy_bfq = {
-+	.dfl_cftypes		= bfq_blkg_files,
-+	.legacy_cftypes		= bfq_blkcg_legacy_files,
-+
-+	.cpd_alloc_fn		= bfq_cpd_alloc,
-+	.cpd_init_fn		= bfq_cpd_init,
-+	.cpd_bind_fn	        = bfq_cpd_init,
-+	.cpd_free_fn		= bfq_cpd_free,
-+
-+	.pd_alloc_fn		= bfq_pd_alloc,
-+	.pd_init_fn		= bfq_pd_init,
-+	.pd_offline_fn		= bfq_pd_offline,
-+	.pd_free_fn		= bfq_pd_free,
-+	.pd_reset_stats_fn	= bfq_pd_reset_stats,
-+};
-+#endif
-+
-+static int __init bfq_init(void)
-+{
-+	int ret;
-+	char msg[60] = "BFQ I/O-scheduler: v8r12";
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	ret = blkcg_policy_register(&blkcg_policy_bfq);
-+	if (ret)
-+		return ret;
-+#endif
-+
-+	ret = -ENOMEM;
-+	if (bfq_slab_setup())
-+		goto err_pol_unreg;
-+
-+	/*
-+	 * Times to load large popular applications for the typical
-+	 * systems installed on the reference devices (see the
-+	 * comments before the definition of the next
-+	 * array). Actually, we use slightly lower values, as the
-+	 * estimated peak rate tends to be smaller than the actual
-+	 * peak rate.  The reason for this last fact is that estimates
-+	 * are computed over much shorter time intervals than the long
-+	 * intervals typically used for benchmarking. Why? First, to
-+	 * adapt more quickly to variations. Second, because an I/O
-+	 * scheduler cannot rely on a peak-rate-evaluation workload to
-+	 * be run for a long time.
-+	 */
-+	ref_wr_duration[0] = msecs_to_jiffies(7000); /* actually 8 sec */
-+	ref_wr_duration[1] = msecs_to_jiffies(2500); /* actually 3 sec */
-+
-+	ret = elv_register(&iosched_bfq_mq);
-+	if (ret)
-+		goto slab_kill;
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	strcat(msg, " (with cgroups support)");
-+#endif
-+	pr_info("%s", msg);
-+
-+	return 0;
-+
-+slab_kill:
-+	bfq_slab_kill();
-+err_pol_unreg:
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	blkcg_policy_unregister(&blkcg_policy_bfq);
-+#endif
-+	return ret;
-+}
-+
-+static void __exit bfq_exit(void)
-+{
-+	elv_unregister(&iosched_bfq_mq);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	blkcg_policy_unregister(&blkcg_policy_bfq);
-+#endif
-+	bfq_slab_kill();
-+}
-+
-+module_init(bfq_init);
-+module_exit(bfq_exit);
-+
-+MODULE_AUTHOR("Paolo Valente");
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("MQ Budget Fair Queueing I/O Scheduler");
-diff --git a/block/bfq-mq.h b/block/bfq-mq.h
-new file mode 100644
-index 000000000000..d15f8ab85817
---- /dev/null
-+++ b/block/bfq-mq.h
-@@ -0,0 +1,1031 @@
-+/*
-+ * BFQ v8r12 for 4.11.0: data structures and common functions prototypes.
-+ *
-+ * Based on ideas and code from CFQ:
-+ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
-+ *
-+ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
-+ *		      Paolo Valente <paolo.valente@unimore.it>
-+ *
-+ * Copyright (C) 2015 Paolo Valente <paolo.valente@unimore.it>
-+ *
-+ * Copyright (C) 2017 Paolo Valente <paolo.valente@linaro.org>
-+ */
-+
-+#ifndef _BFQ_H
-+#define _BFQ_H
-+
-+#include <linux/hrtimer.h>
-+#include <linux/blk-cgroup.h>
-+
-+/* see comments on CONFIG_BFQ_GROUP_IOSCHED in bfq.h */
-+#ifdef CONFIG_MQ_BFQ_GROUP_IOSCHED
-+#define BFQ_GROUP_IOSCHED_ENABLED
-+#endif
-+
-+#define BFQ_IOPRIO_CLASSES	3
-+#define BFQ_CL_IDLE_TIMEOUT	(HZ/5)
-+
-+#define BFQ_MIN_WEIGHT			1
-+#define BFQ_MAX_WEIGHT			1000
-+#define BFQ_WEIGHT_CONVERSION_COEFF	10
-+
-+#define BFQ_DEFAULT_QUEUE_IOPRIO	4
-+
-+#define BFQ_WEIGHT_LEGACY_DFL	100
-+#define BFQ_DEFAULT_GRP_IOPRIO	0
-+#define BFQ_DEFAULT_GRP_CLASS	IOPRIO_CLASS_BE
-+
-+/*
-+ * Soft real-time applications are extremely more latency sensitive
-+ * than interactive ones. Over-raise the weight of the former to
-+ * privilege them against the latter.
-+ */
-+#define BFQ_SOFTRT_WEIGHT_FACTOR	100
-+
-+struct bfq_entity;
-+
-+/**
-+ * struct bfq_service_tree - per ioprio_class service tree.
-+ *
-+ * Each service tree represents a B-WF2Q+ scheduler on its own.  Each
-+ * ioprio_class has its own independent scheduler, and so its own
-+ * bfq_service_tree.  All the fields are protected by the queue lock
-+ * of the containing bfqd.
-+ */
-+struct bfq_service_tree {
-+	/* tree for active entities (i.e., those backlogged) */
-+	struct rb_root active;
-+	/* tree for idle entities (i.e., not backlogged, with V <= F_i)*/
-+	struct rb_root idle;
-+
-+	struct bfq_entity *first_idle;	/* idle entity with minimum F_i */
-+	struct bfq_entity *last_idle;	/* idle entity with maximum F_i */
-+
-+	u64 vtime; /* scheduler virtual time */
-+	/* scheduler weight sum; active and idle entities contribute to it */
-+	unsigned long wsum;
-+};
-+
-+/**
-+ * struct bfq_sched_data - multi-class scheduler.
-+ *
-+ * bfq_sched_data is the basic scheduler queue.  It supports three
-+ * ioprio_classes, and can be used either as a toplevel queue or as an
-+ * intermediate queue in a hierarchical setup.
-+ *
-+ * The supported ioprio_classes are the same as in CFQ, in descending
-+ * priority order, IOPRIO_CLASS_RT, IOPRIO_CLASS_BE, IOPRIO_CLASS_IDLE.
-+ * Requests from higher priority queues are served before all the
-+ * requests from lower priority queues; among requests of the same
-+ * queue requests are served according to B-WF2Q+.
-+ *
-+ * The schedule is implemented by the service trees, plus the field
-+ * @next_in_service, which points to the entity on the active trees
-+ * that will be served next, if 1) no changes in the schedule occurs
-+ * before the current in-service entity is expired, 2) the in-service
-+ * queue becomes idle when it expires, and 3) if the entity pointed by
-+ * in_service_entity is not a queue, then the in-service child entity
-+ * of the entity pointed by in_service_entity becomes idle on
-+ * expiration. This peculiar definition allows for the following
-+ * optimization, not yet exploited: while a given entity is still in
-+ * service, we already know which is the best candidate for next
-+ * service among the other active entitities in the same parent
-+ * entity. We can then quickly compare the timestamps of the
-+ * in-service entity with those of such best candidate.
-+ *
-+ * All the fields are protected by the queue lock of the containing
-+ * bfqd.
-+ */
-+struct bfq_sched_data {
-+	struct bfq_entity *in_service_entity;  /* entity in service */
-+	/* head-of-the-line entity in the scheduler (see comments above) */
-+	struct bfq_entity *next_in_service;
-+	/* array of service trees, one per ioprio_class */
-+	struct bfq_service_tree service_tree[BFQ_IOPRIO_CLASSES];
-+	/* last time CLASS_IDLE was served */
-+	unsigned long bfq_class_idle_last_service;
-+
-+};
-+
-+/**
-+ * struct bfq_weight_counter - counter of the number of all active entities
-+ *                             with a given weight.
-+ */
-+struct bfq_weight_counter {
-+	unsigned int weight; /* weight of the entities this counter refers to */
-+	unsigned int num_active; /* nr of active entities with this weight */
-+	/*
-+	 * Weights tree member (see bfq_data's @queue_weights_tree and
-+	 * @group_weights_tree)
-+	 */
-+	struct rb_node weights_node;
-+};
-+
-+/**
-+ * struct bfq_entity - schedulable entity.
-+ *
-+ * A bfq_entity is used to represent either a bfq_queue (leaf node in the
-+ * cgroup hierarchy) or a bfq_group into the upper level scheduler.  Each
-+ * entity belongs to the sched_data of the parent group in the cgroup
-+ * hierarchy.  Non-leaf entities have also their own sched_data, stored
-+ * in @my_sched_data.
-+ *
-+ * Each entity stores independently its priority values; this would
-+ * allow different weights on different devices, but this
-+ * functionality is not exported to userspace by now.  Priorities and
-+ * weights are updated lazily, first storing the new values into the
-+ * new_* fields, then setting the @prio_changed flag.  As soon as
-+ * there is a transition in the entity state that allows the priority
-+ * update to take place the effective and the requested priority
-+ * values are synchronized.
-+ *
-+ * Unless cgroups are used, the weight value is calculated from the
-+ * ioprio to export the same interface as CFQ.  When dealing with
-+ * ``well-behaved'' queues (i.e., queues that do not spend too much
-+ * time to consume their budget and have true sequential behavior, and
-+ * when there are no external factors breaking anticipation) the
-+ * relative weights at each level of the cgroups hierarchy should be
-+ * guaranteed.  All the fields are protected by the queue lock of the
-+ * containing bfqd.
-+ */
-+struct bfq_entity {
-+	struct rb_node rb_node; /* service_tree member */
-+	/* pointer to the weight counter associated with this entity */
-+	struct bfq_weight_counter *weight_counter;
-+
-+	/*
-+	 * Flag, true if the entity is on a tree (either the active or
-+	 * the idle one of its service_tree) or is in service.
-+	 */
-+	bool on_st;
-+
-+	u64 finish; /* B-WF2Q+ finish timestamp (aka F_i) */
-+	u64 start;  /* B-WF2Q+ start timestamp (aka S_i) */
-+
-+	/* tree the entity is enqueued into; %NULL if not on a tree */
-+	struct rb_root *tree;
-+
-+	/*
-+	 * minimum start time of the (active) subtree rooted at this
-+	 * entity; used for O(log N) lookups into active trees
-+	 */
-+	u64 min_start;
-+
-+	/* amount of service received during the last service slot */
-+	int service;
-+
-+	/* budget, used also to calculate F_i: F_i = S_i + @budget / @weight */
-+	int budget;
-+
-+	unsigned int weight;	 /* weight of the queue */
-+	unsigned int new_weight; /* next weight if a change is in progress */
-+
-+	/* original weight, used to implement weight boosting */
-+	unsigned int orig_weight;
-+
-+	/* parent entity, for hierarchical scheduling */
-+	struct bfq_entity *parent;
-+
-+	/*
-+	 * For non-leaf nodes in the hierarchy, the associated
-+	 * scheduler queue, %NULL on leaf nodes.
-+	 */
-+	struct bfq_sched_data *my_sched_data;
-+	/* the scheduler queue this entity belongs to */
-+	struct bfq_sched_data *sched_data;
-+
-+	/* flag, set to request a weight, ioprio or ioprio_class change  */
-+	int prio_changed;
-+};
-+
-+struct bfq_group;
-+
-+/**
-+ * struct bfq_ttime - per process thinktime stats.
-+ */
-+struct bfq_ttime {
-+	u64 last_end_request; /* completion time of last request */
-+
-+	u64 ttime_total; /* total process thinktime */
-+	unsigned long ttime_samples; /* number of thinktime samples */
-+	u64 ttime_mean; /* average process thinktime */
-+
-+};
-+
-+/**
-+ * struct bfq_queue - leaf schedulable entity.
-+ *
-+ * A bfq_queue is a leaf request queue; it can be associated with an
-+ * io_context or more, if it  is  async or shared  between  cooperating
-+ * processes. @cgroup holds a reference to the cgroup, to be sure that it
-+ * does not disappear while a bfqq still references it (mostly to avoid
-+ * races between request issuing and task migration followed by cgroup
-+ * destruction).
-+ * All the fields are protected by the queue lock of the containing bfqd.
-+ */
-+struct bfq_queue {
-+	/* reference counter */
-+	int ref;
-+	/* parent bfq_data */
-+	struct bfq_data *bfqd;
-+
-+	/* current ioprio and ioprio class */
-+	unsigned short ioprio, ioprio_class;
-+	/* next ioprio and ioprio class if a change is in progress */
-+	unsigned short new_ioprio, new_ioprio_class;
-+
-+	/*
-+	 * Shared bfq_queue if queue is cooperating with one or more
-+	 * other queues.
-+	 */
-+	struct bfq_queue *new_bfqq;
-+	/* request-position tree member (see bfq_group's @rq_pos_tree) */
-+	struct rb_node pos_node;
-+	/* request-position tree root (see bfq_group's @rq_pos_tree) */
-+	struct rb_root *pos_root;
-+
-+	/* sorted list of pending requests */
-+	struct rb_root sort_list;
-+	/* if fifo isn't expired, next request to serve */
-+	struct request *next_rq;
-+	/* number of sync and async requests queued */
-+	int queued[2];
-+	/* number of requests currently allocated */
-+	int allocated;
-+	/* number of pending metadata requests */
-+	int meta_pending;
-+	/* fifo list of requests in sort_list */
-+	struct list_head fifo;
-+
-+	/* entity representing this queue in the scheduler */
-+	struct bfq_entity entity;
-+
-+	/* maximum budget allowed from the feedback mechanism */
-+	int max_budget;
-+	/* budget expiration (in jiffies) */
-+	unsigned long budget_timeout;
-+
-+	/* number of requests on the dispatch list or inside driver */
-+	int dispatched;
-+
-+	unsigned int flags; /* status flags.*/
-+
-+	/* node for active/idle bfqq list inside parent bfqd */
-+	struct list_head bfqq_list;
-+
-+	/* associated @bfq_ttime struct */
-+	struct bfq_ttime ttime;
-+
-+	/* bit vector: a 1 for each seeky requests in history */
-+	u32 seek_history;
-+
-+	/* node for the device's burst list */
-+	struct hlist_node burst_list_node;
-+
-+	/* position of the last request enqueued */
-+	sector_t last_request_pos;
-+
-+	/* Number of consecutive pairs of request completion and
-+	 * arrival, such that the queue becomes idle after the
-+	 * completion, but the next request arrives within an idle
-+	 * time slice; used only if the queue's IO_bound flag has been
-+	 * cleared.
-+	 */
-+	unsigned int requests_within_timer;
-+
-+	/* pid of the process owning the queue, used for logging purposes */
-+	pid_t pid;
-+
-+	/*
-+	 * Pointer to the bfq_io_cq owning the bfq_queue, set to %NULL
-+	 * if the queue is shared.
-+	 */
-+	struct bfq_io_cq *bic;
-+
-+	/* current maximum weight-raising time for this queue */
-+	unsigned long wr_cur_max_time;
-+	/*
-+	 * Minimum time instant such that, only if a new request is
-+	 * enqueued after this time instant in an idle @bfq_queue with
-+	 * no outstanding requests, then the task associated with the
-+	 * queue it is deemed as soft real-time (see the comments on
-+	 * the function bfq_bfqq_softrt_next_start())
-+	 */
-+	unsigned long soft_rt_next_start;
-+	/*
-+	 * Start time of the current weight-raising period if
-+	 * the @bfq-queue is being weight-raised, otherwise
-+	 * finish time of the last weight-raising period.
-+	 */
-+	unsigned long last_wr_start_finish;
-+	/* factor by which the weight of this queue is multiplied */
-+	unsigned int wr_coeff;
-+	/*
-+	 * Time of the last transition of the @bfq_queue from idle to
-+	 * backlogged.
-+	 */
-+	unsigned long last_idle_bklogged;
-+	/*
-+	 * Cumulative service received from the @bfq_queue since the
-+	 * last transition from idle to backlogged.
-+	 */
-+	unsigned long service_from_backlogged;
-+	/*
-+	 * Cumulative service received from the @bfq_queue since its
-+	 * last transition to weight-raised state.
-+	 */
-+	unsigned long service_from_wr;
-+	/*
-+	 * Value of wr start time when switching to soft rt
-+	 */
-+	unsigned long wr_start_at_switch_to_srt;
-+
-+	unsigned long split_time; /* time of last split */
-+	unsigned long first_IO_time; /* time of first I/O for this queue */
-+
-+	/* max service rate measured so far */
-+	u32 max_service_rate;
-+	/*
-+	 * Ratio between the service received by bfqq while it is in
-+	 * service, and the cumulative service (of requests of other
-+	 * queues) that may be injected while bfqq is empty but still
-+	 * in service. To increase precision, the coefficient is
-+	 * measured in tenths of unit. Here are some example of (1)
-+	 * ratios, (2) resulting percentages of service injected
-+	 * w.r.t. to the total service dispatched while bfqq is in
-+	 * service, and (3) corresponding values of the coefficient:
-+	 * 1 (50%) -> 10
-+	 * 2 (33%) -> 20
-+	 * 10 (9%) -> 100
-+	 * 9.9 (9%) -> 99
-+	 * 1.5 (40%) -> 15
-+	 * 0.5 (66%) -> 5
-+	 * 0.1 (90%) -> 1
-+	 *
-+	 * So, if the coefficient is lower than 10, then
-+	 * injected service is more than bfqq service.
-+	 */
-+	unsigned int inject_coeff;
-+	/* amount of service injected in current service slot */
-+	unsigned int injected_service;
-+};
-+
-+/**
-+ * struct bfq_io_cq - per (request_queue, io_context) structure.
-+ */
-+struct bfq_io_cq {
-+	/* associated io_cq structure */
-+	struct io_cq icq; /* must be the first member */
-+	/* array of two process queues, the sync and the async */
-+	struct bfq_queue *bfqq[2];
-+	/* per (request_queue, blkcg) ioprio */
-+	int ioprio;
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	uint64_t blkcg_serial_nr; /* the current blkcg serial */
-+#endif
-+
-+	/*
-+	 * Snapshot of the has_short_time flag before merging; taken
-+	 * to remember its value while the queue is merged, so as to
-+	 * be able to restore it in case of split.
-+	 */
-+	bool saved_has_short_ttime;
-+	/*
-+	 * Same purpose as the previous two fields for the I/O bound
-+	 * classification of a queue.
-+	 */
-+	bool saved_IO_bound;
-+
-+	/*
-+	 * Same purpose as the previous fields for the value of the
-+	 * field keeping the queue's belonging to a large burst
-+	 */
-+	bool saved_in_large_burst;
-+	/*
-+	 * True if the queue belonged to a burst list before its merge
-+	 * with another cooperating queue.
-+	 */
-+	bool was_in_burst_list;
-+
-+	/*
-+	 * Similar to previous fields: save wr information.
-+	 */
-+	unsigned long saved_wr_coeff;
-+	unsigned long saved_last_wr_start_finish;
-+	unsigned long saved_wr_start_at_switch_to_srt;
-+	unsigned int saved_wr_cur_max_time;
-+	struct bfq_ttime saved_ttime;
-+};
-+
-+/**
-+ * struct bfq_data - per-device data structure.
-+ *
-+ * All the fields are protected by @lock.
-+ */
-+struct bfq_data {
-+	/* device request queue */
-+	struct request_queue *queue;
-+	/* dispatch queue */
-+	struct list_head dispatch;
-+
-+	/* root bfq_group for the device */
-+	struct bfq_group *root_group;
-+
-+	/*
-+	 * rbtree of weight counters of @bfq_queues, sorted by
-+	 * weight. Used to keep track of whether all @bfq_queues have
-+	 * the same weight. The tree contains one counter for each
-+	 * distinct weight associated to some active and not
-+	 * weight-raised @bfq_queue (see the comments to the functions
-+	 * bfq_weights_tree_[add|remove] for further details).
-+	 */
-+	struct rb_root queue_weights_tree;
-+	/*
-+	 * rbtree of non-queue @bfq_entity weight counters, sorted by
-+	 * weight. Used to keep track of whether all @bfq_groups have
-+	 * the same weight. The tree contains one counter for each
-+	 * distinct weight associated to some active @bfq_group (see
-+	 * the comments to the functions bfq_weights_tree_[add|remove]
-+	 * for further details).
-+	 */
-+	struct rb_root group_weights_tree;
-+
-+	/*
-+	 * Number of bfq_queues containing requests (including the
-+	 * queue in service, even if it is idling).
-+	 */
-+	int busy_queues;
-+	/* number of weight-raised busy @bfq_queues */
-+	int wr_busy_queues;
-+	/* number of queued requests */
-+	int queued;
-+	/* number of requests dispatched and waiting for completion */
-+	int rq_in_driver;
-+
-+	/*
-+	 * Maximum number of requests in driver in the last
-+	 * @hw_tag_samples completed requests.
-+	 */
-+	int max_rq_in_driver;
-+	/* number of samples used to calculate hw_tag */
-+	int hw_tag_samples;
-+	/* flag set to one if the driver is showing a queueing behavior */
-+	int hw_tag;
-+
-+	/* number of budgets assigned */
-+	int budgets_assigned;
-+
-+	/*
-+	 * Timer set when idling (waiting) for the next request from
-+	 * the queue in service.
-+	 */
-+	struct hrtimer idle_slice_timer;
-+
-+	/* bfq_queue in service */
-+	struct bfq_queue *in_service_queue;
-+
-+	/* on-disk position of the last served request */
-+	sector_t last_position;
-+
-+	/* time of last request completion (ns) */
-+	u64 last_completion;
-+
-+	/* time of first rq dispatch in current observation interval (ns) */
-+	u64 first_dispatch;
-+	/* time of last rq dispatch in current observation interval (ns) */
-+	u64 last_dispatch;
-+
-+	/* beginning of the last budget */
-+	ktime_t last_budget_start;
-+	/* beginning of the last idle slice */
-+	ktime_t last_idling_start;
-+
-+	/* number of samples in current observation interval */
-+	int peak_rate_samples;
-+	/* num of samples of seq dispatches in current observation interval */
-+	u32 sequential_samples;
-+	/* total num of sectors transferred in current observation interval */
-+	u64 tot_sectors_dispatched;
-+	/* max rq size seen during current observation interval (sectors) */
-+	u32 last_rq_max_size;
-+	/* time elapsed from first dispatch in current observ. interval (us) */
-+	u64 delta_from_first;
-+	/*
-+	 * Current estimate of the device peak rate, measured in
-+	 * [(sectors/usec) / 2^BFQ_RATE_SHIFT]. The left-shift by
-+	 * BFQ_RATE_SHIFT is performed to increase precision in
-+	 * fixed-point calculations.
-+	 */
-+	u32 peak_rate;
-+
-+	/* maximum budget allotted to a bfq_queue before rescheduling */
-+	int bfq_max_budget;
-+
-+	/* list of all the bfq_queues active on the device */
-+	struct list_head active_list;
-+	/* list of all the bfq_queues idle on the device */
-+	struct list_head idle_list;
-+
-+	/*
-+	 * Timeout for async/sync requests; when it fires, requests
-+	 * are served in fifo order.
-+	 */
-+	u64 bfq_fifo_expire[2];
-+	/* weight of backward seeks wrt forward ones */
-+	unsigned int bfq_back_penalty;
-+	/* maximum allowed backward seek */
-+	unsigned int bfq_back_max;
-+	/* maximum idling time */
-+	u32 bfq_slice_idle;
-+
-+	/* user-configured max budget value (0 for auto-tuning) */
-+	int bfq_user_max_budget;
-+	/*
-+	 * Timeout for bfq_queues to consume their budget; used to
-+	 * prevent seeky queues from imposing long latencies to
-+	 * sequential or quasi-sequential ones (this also implies that
-+	 * seeky queues cannot receive guarantees in the service
-+	 * domain; after a timeout they are charged for the time they
-+	 * have been in service, to preserve fairness among them, but
-+	 * without service-domain guarantees).
-+	 */
-+	unsigned int bfq_timeout;
-+
-+	/*
-+	 * Number of consecutive requests that must be issued within
-+	 * the idle time slice to set again idling to a queue which
-+	 * was marked as non-I/O-bound (see the definition of the
-+	 * IO_bound flag for further details).
-+	 */
-+	unsigned int bfq_requests_within_timer;
-+
-+	/*
-+	 * Force device idling whenever needed to provide accurate
-+	 * service guarantees, without caring about throughput
-+	 * issues. CAVEAT: this may even increase latencies, in case
-+	 * of useless idling for processes that did stop doing I/O.
-+	 */
-+	bool strict_guarantees;
-+
-+	/*
-+	 * Last time at which a queue entered the current burst of
-+	 * queues being activated shortly after each other; for more
-+	 * details about this and the following parameters related to
-+	 * a burst of activations, see the comments on the function
-+	 * bfq_handle_burst.
-+	 */
-+	unsigned long last_ins_in_burst;
-+	/*
-+	 * Reference time interval used to decide whether a queue has
-+	 * been activated shortly after @last_ins_in_burst.
-+	 */
-+	unsigned long bfq_burst_interval;
-+	/* number of queues in the current burst of queue activations */
-+	int burst_size;
-+
-+	/* common parent entity for the queues in the burst */
-+	struct bfq_entity *burst_parent_entity;
-+	/* Maximum burst size above which the current queue-activation
-+	 * burst is deemed as 'large'.
-+	 */
-+	unsigned long bfq_large_burst_thresh;
-+	/* true if a large queue-activation burst is in progress */
-+	bool large_burst;
-+	/*
-+	 * Head of the burst list (as for the above fields, more
-+	 * details in the comments on the function bfq_handle_burst).
-+	 */
-+	struct hlist_head burst_list;
-+
-+	/* if set to true, low-latency heuristics are enabled */
-+	bool low_latency;
-+	/*
-+	 * Maximum factor by which the weight of a weight-raised queue
-+	 * is multiplied.
-+	 */
-+	unsigned int bfq_wr_coeff;
-+	/* maximum duration of a weight-raising period (jiffies) */
-+	unsigned int bfq_wr_max_time;
-+
-+	/* Maximum weight-raising duration for soft real-time processes */
-+	unsigned int bfq_wr_rt_max_time;
-+	/*
-+	 * Minimum idle period after which weight-raising may be
-+	 * reactivated for a queue (in jiffies).
-+	 */
-+	unsigned int bfq_wr_min_idle_time;
-+	/*
-+	 * Minimum period between request arrivals after which
-+	 * weight-raising may be reactivated for an already busy async
-+	 * queue (in jiffies).
-+	 */
-+	unsigned long bfq_wr_min_inter_arr_async;
-+
-+	/* Max service-rate for a soft real-time queue, in sectors/sec */
-+	unsigned int bfq_wr_max_softrt_rate;
-+	/*
-+	 * Cached value of the product ref_rate*ref_wr_duration, used
-+	 * for computing the maximum duration of weight raising
-+	 * automatically.
-+	 */
-+	u64 rate_dur_prod;
-+
-+	/* fallback dummy bfqq for extreme OOM conditions */
-+	struct bfq_queue oom_bfqq;
-+
-+	spinlock_t lock;
-+
-+	/*
-+	 * bic associated with the task issuing current bio for
-+	 * merging. This and the next field are used as a support to
-+	 * be able to perform the bic lookup, needed by bio-merge
-+	 * functions, before the scheduler lock is taken, and thus
-+	 * avoid taking the request-queue lock while the scheduler
-+	 * lock is being held.
-+	 */
-+	struct bfq_io_cq *bio_bic;
-+	/* bfqq associated with the task issuing current bio for merging */
-+	struct bfq_queue *bio_bfqq;
-+	/* Extra flag used only for TESTING */
-+	bool bio_bfqq_set;
-+
-+	/*
-+	 * Cached sbitmap shift, used to compute depth limits in
-+	 * bfq_update_depths.
-+	 */
-+	unsigned int sb_shift;
-+
-+	/*
-+	 * Depth limits used in bfq_limit_depth (see comments on the
-+	 * function)
-+	 */
-+	unsigned int word_depths[2][2];
-+};
-+
-+enum bfqq_state_flags {
-+	BFQ_BFQQ_FLAG_just_created = 0,	/* queue just allocated */
-+	BFQ_BFQQ_FLAG_busy,		/* has requests or is in service */
-+	BFQ_BFQQ_FLAG_wait_request,	/* waiting for a request */
-+	BFQ_BFQQ_FLAG_non_blocking_wait_rq, /*
-+					     * waiting for a request
-+					     * without idling the device
-+					     */
-+	BFQ_BFQQ_FLAG_fifo_expire,	/* FIFO checked in this slice */
-+	BFQ_BFQQ_FLAG_has_short_ttime,	/* queue has a short think time */
-+	BFQ_BFQQ_FLAG_sync,		/* synchronous queue */
-+	BFQ_BFQQ_FLAG_IO_bound,		/*
-+					 * bfqq has timed-out at least once
-+					 * having consumed at most 2/10 of
-+					 * its budget
-+					 */
-+	BFQ_BFQQ_FLAG_in_large_burst,	/*
-+					 * bfqq activated in a large burst,
-+					 * see comments to bfq_handle_burst.
-+					 */
-+	BFQ_BFQQ_FLAG_softrt_update,	/*
-+					 * may need softrt-next-start
-+					 * update
-+					 */
-+	BFQ_BFQQ_FLAG_coop,		/* bfqq is shared */
-+	BFQ_BFQQ_FLAG_split_coop	/* shared bfqq will be split */
-+};
-+
-+#define BFQ_BFQQ_FNS(name)						\
-+static void bfq_mark_bfqq_##name(struct bfq_queue *bfqq)		\
-+{									\
-+	(bfqq)->flags |= (1 << BFQ_BFQQ_FLAG_##name);			\
-+}									\
-+static void bfq_clear_bfqq_##name(struct bfq_queue *bfqq)		\
-+{									\
-+	(bfqq)->flags &= ~(1 << BFQ_BFQQ_FLAG_##name);			\
-+}									\
-+static int bfq_bfqq_##name(const struct bfq_queue *bfqq)		\
-+{									\
-+	return ((bfqq)->flags & (1 << BFQ_BFQQ_FLAG_##name)) != 0;	\
-+}
-+
-+BFQ_BFQQ_FNS(just_created);
-+BFQ_BFQQ_FNS(busy);
-+BFQ_BFQQ_FNS(wait_request);
-+BFQ_BFQQ_FNS(non_blocking_wait_rq);
-+BFQ_BFQQ_FNS(fifo_expire);
-+BFQ_BFQQ_FNS(has_short_ttime);
-+BFQ_BFQQ_FNS(sync);
-+BFQ_BFQQ_FNS(IO_bound);
-+BFQ_BFQQ_FNS(in_large_burst);
-+BFQ_BFQQ_FNS(coop);
-+BFQ_BFQQ_FNS(split_coop);
-+BFQ_BFQQ_FNS(softrt_update);
-+#undef BFQ_BFQQ_FNS
-+
-+/* Logging facilities. */
-+#ifdef CONFIG_BFQ_REDIRECT_TO_CONSOLE
-+
-+static const char *checked_dev_name(const struct device *dev)
-+{
-+	static const char nodev[] = "nodev";
-+
-+	if (dev)
-+		return dev_name(dev);
-+
-+	return nodev;
-+}
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+static struct bfq_group *bfqq_group(struct bfq_queue *bfqq);
-+static struct blkcg_gq *bfqg_to_blkg(struct bfq_group *bfqg);
-+
-+#define bfq_log_bfqq(bfqd, bfqq, fmt, args...)	do {			\
-+	pr_crit("%s bfq%d%c %s [%s] " fmt "\n",				\
-+		checked_dev_name((bfqd)->queue->backing_dev_info->dev),	\
-+		(bfqq)->pid,						\
-+		bfq_bfqq_sync((bfqq)) ? 'S' : 'A',			\
-+		bfqq_group(bfqq)->blkg_path, __func__, ##args);		\
-+} while (0)
-+
-+#define bfq_log_bfqg(bfqd, bfqg, fmt, args...)	do {			\
-+	pr_crit("%s %s [%s] " fmt "\n",					\
-+	checked_dev_name((bfqd)->queue->backing_dev_info->dev),		\
-+	bfqg->blkg_path, __func__, ##args);				\
-+} while (0)
-+
-+#else /* BFQ_GROUP_IOSCHED_ENABLED */
-+
-+#define bfq_log_bfqq(bfqd, bfqq, fmt, args...)				\
-+	pr_crit("%s bfq%d%c [%s] " fmt "\n",				\
-+		checked_dev_name((bfqd)->queue->backing_dev_info->dev),	\
-+		(bfqq)->pid, bfq_bfqq_sync((bfqq)) ? 'S' : 'A',		\
-+		__func__, ##args)
-+#define bfq_log_bfqg(bfqd, bfqg, fmt, args...)		do {} while (0)
-+
-+#endif /* BFQ_GROUP_IOSCHED_ENABLED */
-+
-+#define bfq_log(bfqd, fmt, args...) \
-+	pr_crit("%s bfq [%s] " fmt "\n",				\
-+		checked_dev_name((bfqd)->queue->backing_dev_info->dev),	\
-+		__func__, ##args)
-+
-+#else /* CONFIG_BFQ_REDIRECT_TO_CONSOLE */
-+
-+#if !defined(CONFIG_BLK_DEV_IO_TRACE)
-+
-+/* Avoid possible "unused-variable" warning. See commit message. */
-+
-+#define bfq_log_bfqq(bfqd, bfqq, fmt, args...)	((void) (bfqq))
-+
-+#define bfq_log_bfqg(bfqd, bfqg, fmt, args...)	((void) (bfqg))
-+
-+#define bfq_log(bfqd, fmt, args...)		do {} while (0)
-+
-+#else /* CONFIG_BLK_DEV_IO_TRACE */
-+
-+#include <linux/blktrace_api.h>
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+static struct bfq_group *bfqq_group(struct bfq_queue *bfqq);
-+static struct blkcg_gq *bfqg_to_blkg(struct bfq_group *bfqg);
-+
-+#define bfq_log_bfqq(bfqd, bfqq, fmt, args...)	do {			\
-+	blk_add_trace_msg((bfqd)->queue, "bfq%d%c %s [%s] " fmt, \
-+			  (bfqq)->pid,			  \
-+			  bfq_bfqq_sync((bfqq)) ? 'S' : 'A',	\
-+			  bfqq_group(bfqq)->blkg_path, __func__, ##args); \
-+} while (0)
-+
-+#define bfq_log_bfqg(bfqd, bfqg, fmt, args...)	do {			\
-+	blk_add_trace_msg((bfqd)->queue, "%s [%s] " fmt, bfqg->blkg_path, \
-+	__func__, ##args);\
-+} while (0)
-+
-+#else /* BFQ_GROUP_IOSCHED_ENABLED */
-+
-+#define bfq_log_bfqq(bfqd, bfqq, fmt, args...)	\
-+	blk_add_trace_msg((bfqd)->queue, "bfq%d%c [%s] " fmt, (bfqq)->pid, \
-+			bfq_bfqq_sync((bfqq)) ? 'S' : 'A',		\
-+				__func__, ##args)
-+#define bfq_log_bfqg(bfqd, bfqg, fmt, args...)		do {} while (0)
-+
-+#endif /* BFQ_GROUP_IOSCHED_ENABLED */
-+
-+#define bfq_log(bfqd, fmt, args...) \
-+	blk_add_trace_msg((bfqd)->queue, "bfq [%s] " fmt, __func__, ##args)
-+
-+#endif /* CONFIG_BLK_DEV_IO_TRACE */
-+#endif /* CONFIG_BFQ_REDIRECT_TO_CONSOLE */
-+
-+/* Expiration reasons. */
-+enum bfqq_expiration {
-+	BFQ_BFQQ_TOO_IDLE = 0,		/*
-+					 * queue has been idling for
-+					 * too long
-+					 */
-+	BFQ_BFQQ_BUDGET_TIMEOUT,	/* budget took too long to be used */
-+	BFQ_BFQQ_BUDGET_EXHAUSTED,	/* budget consumed */
-+	BFQ_BFQQ_NO_MORE_REQUESTS,	/* the queue has no more requests */
-+	BFQ_BFQQ_PREEMPTED		/* preemption in progress */
-+};
-+
-+
-+struct bfqg_stats {
-+#if defined(BFQ_GROUP_IOSCHED_ENABLED) &&  defined(CONFIG_DEBUG_BLK_CGROUP)
-+	/* number of ios merged */
-+	struct blkg_rwstat		merged;
-+	/* total time spent on device in ns, may not be accurate w/ queueing */
-+	struct blkg_rwstat		service_time;
-+	/* total time spent waiting in scheduler queue in ns */
-+	struct blkg_rwstat		wait_time;
-+	/* number of IOs queued up */
-+	struct blkg_rwstat		queued;
-+	/* total disk time and nr sectors dispatched by this group */
-+	struct blkg_stat		time;
-+	/* sum of number of ios queued across all samples */
-+	struct blkg_stat		avg_queue_size_sum;
-+	/* count of samples taken for average */
-+	struct blkg_stat		avg_queue_size_samples;
-+	/* how many times this group has been removed from service tree */
-+	struct blkg_stat		dequeue;
-+	/* total time spent waiting for it to be assigned a timeslice. */
-+	struct blkg_stat		group_wait_time;
-+	/* time spent idling for this blkcg_gq */
-+	struct blkg_stat		idle_time;
-+	/* total time with empty current active q with other requests queued */
-+	struct blkg_stat		empty_time;
-+	/* fields after this shouldn't be cleared on stat reset */
-+	uint64_t			start_group_wait_time;
-+	uint64_t			start_idle_time;
-+	uint64_t			start_empty_time;
-+	uint16_t			flags;
-+#endif /* BFQ_GROUP_IOSCHED_ENABLED && CONFIG_DEBUG_BLK_CGROUP */
-+};
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+/*
-+ * struct bfq_group_data - per-blkcg storage for the blkio subsystem.
-+ *
-+ * @ps: @blkcg_policy_storage that this structure inherits
-+ * @weight: weight of the bfq_group
-+ */
-+struct bfq_group_data {
-+	/* must be the first member */
-+	struct blkcg_policy_data pd;
-+
-+	unsigned int weight;
-+};
-+
-+/**
-+ * struct bfq_group - per (device, cgroup) data structure.
-+ * @entity: schedulable entity to insert into the parent group sched_data.
-+ * @sched_data: own sched_data, to contain child entities (they may be
-+ *              both bfq_queues and bfq_groups).
-+ * @bfqd: the bfq_data for the device this group acts upon.
-+ * @async_bfqq: array of async queues for all the tasks belonging to
-+ *              the group, one queue per ioprio value per ioprio_class,
-+ *              except for the idle class that has only one queue.
-+ * @async_idle_bfqq: async queue for the idle class (ioprio is ignored).
-+ * @my_entity: pointer to @entity, %NULL for the toplevel group; used
-+ *             to avoid too many special cases during group creation/
-+ *             migration.
-+ * @active_entities: number of active entities belonging to the group;
-+ *                   unused for the root group. Used to know whether there
-+ *                   are groups with more than one active @bfq_entity
-+ *                   (see the comments to the function
-+ *                   bfq_bfqq_may_idle()).
-+ * @rq_pos_tree: rbtree sorted by next_request position, used when
-+ *               determining if two or more queues have interleaving
-+ *               requests (see bfq_find_close_cooperator()).
-+ *
-+ * Each (device, cgroup) pair has its own bfq_group, i.e., for each cgroup
-+ * there is a set of bfq_groups, each one collecting the lower-level
-+ * entities belonging to the group that are acting on the same device.
-+ *
-+ * Locking works as follows:
-+ *    o @bfqd is protected by the queue lock, RCU is used to access it
-+ *      from the readers.
-+ *    o All the other fields are protected by the @bfqd queue lock.
-+ */
-+struct bfq_group {
-+	/* must be the first member */
-+	struct blkg_policy_data pd;
-+
-+	/* cached path for this blkg (see comments in bfq_bic_update_cgroup) */
-+	char blkg_path[128];
-+
-+	/* reference counter (see comments in bfq_bic_update_cgroup) */
-+	int ref;
-+
-+	struct bfq_entity entity;
-+	struct bfq_sched_data sched_data;
-+
-+	void *bfqd;
-+
-+	struct bfq_queue *async_bfqq[2][IOPRIO_BE_NR];
-+	struct bfq_queue *async_idle_bfqq;
-+
-+	struct bfq_entity *my_entity;
-+
-+	int active_entities;
-+
-+	struct rb_root rq_pos_tree;
-+
-+	struct bfqg_stats stats;
-+};
-+
-+#else
-+struct bfq_group {
-+	struct bfq_sched_data sched_data;
-+
-+	struct bfq_queue *async_bfqq[2][IOPRIO_BE_NR];
-+	struct bfq_queue *async_idle_bfqq;
-+
-+	struct rb_root rq_pos_tree;
-+};
-+#endif
-+
-+static struct bfq_queue *bfq_entity_to_bfqq(struct bfq_entity *entity);
-+
-+static unsigned int bfq_class_idx(struct bfq_entity *entity)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+
-+	return bfqq ? bfqq->ioprio_class - 1 :
-+		BFQ_DEFAULT_GRP_CLASS - 1;
-+}
-+
-+static struct bfq_service_tree *
-+bfq_entity_service_tree(struct bfq_entity *entity)
-+{
-+	struct bfq_sched_data *sched_data = entity->sched_data;
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+	unsigned int idx = bfq_class_idx(entity);
-+
-+	BUG_ON(idx >= BFQ_IOPRIO_CLASSES);
-+	BUG_ON(sched_data == NULL);
-+
-+	if (bfqq)
-+		bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			     "%p %d",
-+			     sched_data->service_tree + idx, idx);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	else {
-+		struct bfq_group *bfqg =
-+			container_of(entity, struct bfq_group, entity);
-+
-+		bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+			     "%p %d",
-+			     sched_data->service_tree + idx, idx);
-+	}
-+#endif
-+	return sched_data->service_tree + idx;
-+}
-+
-+static struct bfq_queue *bic_to_bfqq(struct bfq_io_cq *bic, bool is_sync)
-+{
-+	return bic->bfqq[is_sync];
-+}
-+
-+static void bic_set_bfqq(struct bfq_io_cq *bic, struct bfq_queue *bfqq,
-+			 bool is_sync)
-+{
-+	bic->bfqq[is_sync] = bfqq;
-+}
-+
-+static struct bfq_data *bic_to_bfqd(struct bfq_io_cq *bic)
-+{
-+	return bic->icq.q->elevator->elevator_data;
-+}
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+
-+static struct bfq_group *bfq_bfqq_to_bfqg(struct bfq_queue *bfqq)
-+{
-+	struct bfq_entity *group_entity = bfqq->entity.parent;
-+
-+	if (!group_entity)
-+		group_entity = &bfqq->bfqd->root_group->entity;
-+
-+	return container_of(group_entity, struct bfq_group, entity);
-+}
-+
-+#else
-+
-+static struct bfq_group *bfq_bfqq_to_bfqg(struct bfq_queue *bfqq)
-+{
-+	return bfqq->bfqd->root_group;
-+}
-+
-+#endif
-+
-+static void bfq_check_ioprio_change(struct bfq_io_cq *bic, struct bio *bio);
-+static void bfq_put_queue(struct bfq_queue *bfqq);
-+static struct bfq_queue *bfq_get_queue(struct bfq_data *bfqd,
-+				       struct bio *bio, bool is_sync,
-+				       struct bfq_io_cq *bic);
-+static void bfq_end_wr_async_queues(struct bfq_data *bfqd,
-+				    struct bfq_group *bfqg);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+static void bfq_put_async_queues(struct bfq_data *bfqd, struct bfq_group *bfqg);
-+#endif
-+static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq);
-+
-+#endif /* _BFQ_H */
-diff --git a/block/bfq-sched.c b/block/bfq-sched.c
-new file mode 100644
-index 000000000000..32d66282bec9
---- /dev/null
-+++ b/block/bfq-sched.c
-@@ -0,0 +1,2077 @@
-+/*
-+ * BFQ: Hierarchical B-WF2Q+ scheduler.
-+ *
-+ * Based on ideas and code from CFQ:
-+ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
-+ *
-+ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
-+ *		      Paolo Valente <paolo.valente@unimore.it>
-+ *
-+ * Copyright (C) 2015 Paolo Valente <paolo.valente@unimore.it>
-+ *
-+ * Copyright (C) 2016 Paolo Valente <paolo.valente@linaro.org>
-+ */
-+
-+static struct bfq_group *bfqq_group(struct bfq_queue *bfqq);
-+
-+/**
-+ * bfq_gt - compare two timestamps.
-+ * @a: first ts.
-+ * @b: second ts.
-+ *
-+ * Return @a > @b, dealing with wrapping correctly.
-+ */
-+static int bfq_gt(u64 a, u64 b)
-+{
-+	return (s64)(a - b) > 0;
-+}
-+
-+static struct bfq_entity *bfq_root_active_entity(struct rb_root *tree)
-+{
-+	struct rb_node *node = tree->rb_node;
-+
-+	return rb_entry(node, struct bfq_entity, rb_node);
-+}
-+
-+static struct bfq_entity *bfq_lookup_next_entity(struct bfq_sched_data *sd,
-+						 bool expiration);
-+
-+static bool bfq_update_parent_budget(struct bfq_entity *next_in_service);
-+
-+/**
-+ * bfq_update_next_in_service - update sd->next_in_service
-+ * @sd: sched_data for which to perform the update.
-+ * @new_entity: if not NULL, pointer to the entity whose activation,
-+ *		requeueing or repositionig triggered the invocation of
-+ *		this function.
-+ * @expiration: id true, this function is being invoked after the
-+ *		expiration of the in-service entity
-+ *
-+ * This function is called to update sd->next_in_service, which, in
-+ * its turn, may change as a consequence of the insertion or
-+ * extraction of an entity into/from one of the active trees of
-+ * sd. These insertions/extractions occur as a consequence of
-+ * activations/deactivations of entities, with some activations being
-+ * 'true' activations, and other activations being requeueings (i.e.,
-+ * implementing the second, requeueing phase of the mechanism used to
-+ * reposition an entity in its active tree; see comments on
-+ * __bfq_activate_entity and __bfq_requeue_entity for details). In
-+ * both the last two activation sub-cases, new_entity points to the
-+ * just activated or requeued entity.
-+ *
-+ * Returns true if sd->next_in_service changes in such a way that
-+ * entity->parent may become the next_in_service for its parent
-+ * entity.
-+ */
-+static bool bfq_update_next_in_service(struct bfq_sched_data *sd,
-+				       struct bfq_entity *new_entity,
-+				       bool expiration)
-+{
-+	struct bfq_entity *next_in_service = sd->next_in_service;
-+	struct bfq_queue *bfqq;
-+	bool parent_sched_may_change = false;
-+	bool change_without_lookup = false;
-+
-+	/*
-+	 * If this update is triggered by the activation, requeueing
-+	 * or repositiong of an entity that does not coincide with
-+	 * sd->next_in_service, then a full lookup in the active tree
-+	 * can be avoided. In fact, it is enough to check whether the
-+	 * just-modified entity has the same priority as
-+	 * sd->next_in_service, is eligible and has a lower virtual
-+	 * finish time than sd->next_in_service. If this compound
-+	 * condition holds, then the new entity becomes the new
-+	 * next_in_service. Otherwise no change is needed.
-+	 */
-+	if (new_entity && new_entity != sd->next_in_service) {
-+		/*
-+		 * Flag used to decide whether to replace
-+		 * sd->next_in_service with new_entity. Tentatively
-+		 * set to true, and left as true if
-+		 * sd->next_in_service is NULL.
-+		 */
-+		change_without_lookup = true;
-+
-+		/*
-+		 * If there is already a next_in_service candidate
-+		 * entity, then compare timestamps to decide whether
-+		 * to replace sd->service_tree with new_entity.
-+		 */
-+		if (next_in_service) {
-+			unsigned int new_entity_class_idx =
-+				bfq_class_idx(new_entity);
-+			struct bfq_service_tree *st =
-+				sd->service_tree + new_entity_class_idx;
-+
-+			change_without_lookup =
-+				(new_entity_class_idx ==
-+				 bfq_class_idx(next_in_service)
-+				 &&
-+				 !bfq_gt(new_entity->start, st->vtime)
-+				 &&
-+				 bfq_gt(next_in_service->finish,
-+					new_entity->finish));
-+		}
-+
-+		if (change_without_lookup) {
-+			next_in_service = new_entity;
-+			bfqq = bfq_entity_to_bfqq(next_in_service);
-+
-+			if (bfqq)
-+				bfq_log_bfqq(bfqq->bfqd, bfqq,
-+				"chose without lookup");
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+			else {
-+				struct bfq_group *bfqg =
-+					container_of(next_in_service,
-+						     struct bfq_group, entity);
-+
-+				bfq_log_bfqg((struct bfq_data*)bfqg->bfqd, bfqg,
-+				"chose without lookup");
-+			}
-+#endif
-+		}
-+	}
-+
-+	if (!change_without_lookup) /* lookup needed */
-+		next_in_service = bfq_lookup_next_entity(sd, expiration);
-+
-+	if (next_in_service) {
-+		bool new_budget_triggers_change =
-+			bfq_update_parent_budget(next_in_service);
-+
-+		parent_sched_may_change = !sd->next_in_service ||
-+			new_budget_triggers_change;
-+	}
-+
-+	sd->next_in_service = next_in_service;
-+
-+	if (!next_in_service)
-+		return parent_sched_may_change;
-+
-+	bfqq = bfq_entity_to_bfqq(next_in_service);
-+	if (bfqq)
-+		bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			     "chosen this queue");
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	else {
-+		struct bfq_group *bfqg =
-+			container_of(next_in_service,
-+				     struct bfq_group, entity);
-+
-+		bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+			     "chosen this entity");
-+	}
-+#endif
-+	return parent_sched_may_change;
-+}
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+/* both next loops stop at one of the child entities of the root group */
-+#define for_each_entity(entity)				\
-+	for (; entity ; entity = entity->parent)
-+
-+/*
-+ * For each iteration, compute parent in advance, so as to be safe if
-+ * entity is deallocated during the iteration. Such a deallocation may
-+ * happen as a consequence of a bfq_put_queue that frees the bfq_queue
-+ * containing entity.
-+ */
-+#define for_each_entity_safe(entity, parent)				\
-+	for (; entity && ({ parent = entity->parent; 1; }); entity = parent)
-+
-+/*
-+ * Returns true if this budget changes may let next_in_service->parent
-+ * become the next_in_service entity for its parent entity.
-+ */
-+static bool bfq_update_parent_budget(struct bfq_entity *next_in_service)
-+{
-+	struct bfq_entity *bfqg_entity;
-+	struct bfq_group *bfqg;
-+	struct bfq_sched_data *group_sd;
-+	bool ret = false;
-+
-+	BUG_ON(!next_in_service);
-+
-+	group_sd = next_in_service->sched_data;
-+
-+	bfqg = container_of(group_sd, struct bfq_group, sched_data);
-+	/*
-+	 * bfq_group's my_entity field is not NULL only if the group
-+	 * is not the root group. We must not touch the root entity
-+	 * as it must never become an in-service entity.
-+	 */
-+	bfqg_entity = bfqg->my_entity;
-+	if (bfqg_entity) {
-+		if (bfqg_entity->budget > next_in_service->budget)
-+			ret = true;
-+		bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+			"old budg: %d, new budg: %d",
-+			bfqg_entity->budget, next_in_service->budget);
-+		bfqg_entity->budget = next_in_service->budget;
-+	}
-+
-+	return ret;
-+}
-+
-+/*
-+ * This function tells whether entity stops being a candidate for next
-+ * service, according to the restrictive definition of the field
-+ * next_in_service. In particular, this function is invoked for an
-+ * entity that is about to be set in service.
-+ *
-+ * If entity is a queue, then the entity is no longer a candidate for
-+ * next service according to the that definition, because entity is
-+ * about to become the in-service queue. This function then returns
-+ * true if entity is a queue.
-+ *
-+ * In contrast, entity could still be a candidate for next service if
-+ * it is not a queue, and has more than one active child. In fact,
-+ * even if one of its children is about to be set in service, other
-+ * active children may still be the next to serve, for the parent
-+ * entity, even according to the above definition. As a consequence, a
-+ * non-queue entity is not a candidate for next-service only if it has
-+ * only one active child. And only if this condition holds, then this
-+ * function returns true for a non-queue entity.
-+ */
-+static bool bfq_no_longer_next_in_service(struct bfq_entity *entity)
-+{
-+	struct bfq_group *bfqg;
-+
-+	if (bfq_entity_to_bfqq(entity))
-+		return true;
-+
-+	bfqg = container_of(entity, struct bfq_group, entity);
-+
-+	BUG_ON(bfqg == ((struct bfq_data *)(bfqg->bfqd))->root_group);
-+	BUG_ON(bfqg->active_entities == 0);
-+	/*
-+	 * The field active_entities does not always contain the
-+	 * actual number of active children entities: it happens to
-+	 * not account for the in-service entity in case the latter is
-+	 * removed from its active tree (which may get done after
-+	 * invoking the function bfq_no_longer_next_in_service in
-+	 * bfq_get_next_queue). Fortunately, here, i.e., while
-+	 * bfq_no_longer_next_in_service is not yet completed in
-+	 * bfq_get_next_queue, bfq_active_extract has not yet been
-+	 * invoked, and thus active_entities still coincides with the
-+	 * actual number of active entities.
-+	 */
-+	if (bfqg->active_entities == 1)
-+		return true;
-+
-+	return false;
-+}
-+
-+#else /* BFQ_GROUP_IOSCHED_ENABLED */
-+#define for_each_entity(entity)	\
-+	for (; entity ; entity = NULL)
-+
-+#define for_each_entity_safe(entity, parent) \
-+	for (parent = NULL; entity ; entity = parent)
-+
-+static bool bfq_update_parent_budget(struct bfq_entity *next_in_service)
-+{
-+	return false;
-+}
-+
-+static bool bfq_no_longer_next_in_service(struct bfq_entity *entity)
-+{
-+	return true;
-+}
-+
-+#endif /* BFQ_GROUP_IOSCHED_ENABLED */
-+
-+/*
-+ * Shift for timestamp calculations.  This actually limits the maximum
-+ * service allowed in one timestamp delta (small shift values increase it),
-+ * the maximum total weight that can be used for the queues in the system
-+ * (big shift values increase it), and the period of virtual time
-+ * wraparounds.
-+ */
-+#define WFQ_SERVICE_SHIFT	22
-+
-+static struct bfq_queue *bfq_entity_to_bfqq(struct bfq_entity *entity)
-+{
-+	struct bfq_queue *bfqq = NULL;
-+
-+	BUG_ON(!entity);
-+
-+	if (!entity->my_sched_data)
-+		bfqq = container_of(entity, struct bfq_queue, entity);
-+
-+	return bfqq;
-+}
-+
-+
-+/**
-+ * bfq_delta - map service into the virtual time domain.
-+ * @service: amount of service.
-+ * @weight: scale factor (weight of an entity or weight sum).
-+ */
-+static u64 bfq_delta(unsigned long service, unsigned long weight)
-+{
-+	u64 d = (u64)service << WFQ_SERVICE_SHIFT;
-+
-+	do_div(d, weight);
-+	return d;
-+}
-+
-+/**
-+ * bfq_calc_finish - assign the finish time to an entity.
-+ * @entity: the entity to act upon.
-+ * @service: the service to be charged to the entity.
-+ */
-+static void bfq_calc_finish(struct bfq_entity *entity, unsigned long service)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+	unsigned long long start, finish, delta;
-+
-+	BUG_ON(entity->weight == 0);
-+
-+	entity->finish = entity->start +
-+		bfq_delta(service, entity->weight);
-+
-+	start = ((entity->start>>10)*1000)>>12;
-+	finish = ((entity->finish>>10)*1000)>>12;
-+	delta = ((bfq_delta(service, entity->weight)>>10)*1000)>>12;
-+
-+	if (bfqq) {
-+		bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			"serv %lu, w %d",
-+			service, entity->weight);
-+		bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			"start %llu, finish %llu, delta %llu",
-+			start, finish, delta);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	} else {
-+		struct bfq_group *bfqg =
-+			container_of(entity, struct bfq_group, entity);
-+
-+		bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+			"group: serv %lu, w %d",
-+			     service, entity->weight);
-+		bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+			"group: start %llu, finish %llu, delta %llu",
-+			start, finish, delta);
-+#endif
-+	}
-+}
-+
-+/**
-+ * bfq_entity_of - get an entity from a node.
-+ * @node: the node field of the entity.
-+ *
-+ * Convert a node pointer to the relative entity.  This is used only
-+ * to simplify the logic of some functions and not as the generic
-+ * conversion mechanism because, e.g., in the tree walking functions,
-+ * the check for a %NULL value would be redundant.
-+ */
-+static struct bfq_entity *bfq_entity_of(struct rb_node *node)
-+{
-+	struct bfq_entity *entity = NULL;
-+
-+	if (node)
-+		entity = rb_entry(node, struct bfq_entity, rb_node);
-+
-+	return entity;
-+}
-+
-+/**
-+ * bfq_extract - remove an entity from a tree.
-+ * @root: the tree root.
-+ * @entity: the entity to remove.
-+ */
-+static void bfq_extract(struct rb_root *root, struct bfq_entity *entity)
-+{
-+	BUG_ON(entity->tree != root);
-+
-+	entity->tree = NULL;
-+	rb_erase(&entity->rb_node, root);
-+}
-+
-+/**
-+ * bfq_idle_extract - extract an entity from the idle tree.
-+ * @st: the service tree of the owning @entity.
-+ * @entity: the entity being removed.
-+ */
-+static void bfq_idle_extract(struct bfq_service_tree *st,
-+			     struct bfq_entity *entity)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+	struct rb_node *next;
-+
-+	BUG_ON(entity->tree != &st->idle);
-+
-+	if (entity == st->first_idle) {
-+		next = rb_next(&entity->rb_node);
-+		st->first_idle = bfq_entity_of(next);
-+	}
-+
-+	if (entity == st->last_idle) {
-+		next = rb_prev(&entity->rb_node);
-+		st->last_idle = bfq_entity_of(next);
-+	}
-+
-+	bfq_extract(&st->idle, entity);
-+
-+	if (bfqq)
-+		list_del(&bfqq->bfqq_list);
-+}
-+
-+/**
-+ * bfq_insert - generic tree insertion.
-+ * @root: tree root.
-+ * @entity: entity to insert.
-+ *
-+ * This is used for the idle and the active tree, since they are both
-+ * ordered by finish time.
-+ */
-+static void bfq_insert(struct rb_root *root, struct bfq_entity *entity)
-+{
-+	struct bfq_entity *entry;
-+	struct rb_node **node = &root->rb_node;
-+	struct rb_node *parent = NULL;
-+
-+	BUG_ON(entity->tree);
-+
-+	while (*node) {
-+		parent = *node;
-+		entry = rb_entry(parent, struct bfq_entity, rb_node);
-+
-+		if (bfq_gt(entry->finish, entity->finish))
-+			node = &parent->rb_left;
-+		else
-+			node = &parent->rb_right;
-+	}
-+
-+	rb_link_node(&entity->rb_node, parent, node);
-+	rb_insert_color(&entity->rb_node, root);
-+
-+	entity->tree = root;
-+}
-+
-+/**
-+ * bfq_update_min - update the min_start field of a entity.
-+ * @entity: the entity to update.
-+ * @node: one of its children.
-+ *
-+ * This function is called when @entity may store an invalid value for
-+ * min_start due to updates to the active tree.  The function  assumes
-+ * that the subtree rooted at @node (which may be its left or its right
-+ * child) has a valid min_start value.
-+ */
-+static void bfq_update_min(struct bfq_entity *entity, struct rb_node *node)
-+{
-+	struct bfq_entity *child;
-+
-+	if (node) {
-+		child = rb_entry(node, struct bfq_entity, rb_node);
-+		if (bfq_gt(entity->min_start, child->min_start))
-+			entity->min_start = child->min_start;
-+	}
-+}
-+
-+/**
-+ * bfq_update_active_node - recalculate min_start.
-+ * @node: the node to update.
-+ *
-+ * @node may have changed position or one of its children may have moved,
-+ * this function updates its min_start value.  The left and right subtrees
-+ * are assumed to hold a correct min_start value.
-+ */
-+static void bfq_update_active_node(struct rb_node *node)
-+{
-+	struct bfq_entity *entity = rb_entry(node, struct bfq_entity, rb_node);
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+
-+	entity->min_start = entity->start;
-+	bfq_update_min(entity, node->rb_right);
-+	bfq_update_min(entity, node->rb_left);
-+
-+	if (bfqq) {
-+		bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			     "new min_start %llu",
-+			     ((entity->min_start>>10)*1000)>>12);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	} else {
-+		struct bfq_group *bfqg =
-+			container_of(entity, struct bfq_group, entity);
-+
-+		bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+			     "new min_start %llu",
-+			     ((entity->min_start>>10)*1000)>>12);
-+#endif
-+	}
-+}
-+
-+/**
-+ * bfq_update_active_tree - update min_start for the whole active tree.
-+ * @node: the starting node.
-+ *
-+ * @node must be the deepest modified node after an update.  This function
-+ * updates its min_start using the values held by its children, assuming
-+ * that they did not change, and then updates all the nodes that may have
-+ * changed in the path to the root.  The only nodes that may have changed
-+ * are the ones in the path or their siblings.
-+ */
-+static void bfq_update_active_tree(struct rb_node *node)
-+{
-+	struct rb_node *parent;
-+
-+up:
-+	bfq_update_active_node(node);
-+
-+	parent = rb_parent(node);
-+	if (!parent)
-+		return;
-+
-+	if (node == parent->rb_left && parent->rb_right)
-+		bfq_update_active_node(parent->rb_right);
-+	else if (parent->rb_left)
-+		bfq_update_active_node(parent->rb_left);
-+
-+	node = parent;
-+	goto up;
-+}
-+
-+static void bfq_weights_tree_add(struct bfq_data *bfqd,
-+				 struct bfq_entity *entity,
-+				 struct rb_root *root);
-+
-+static void __bfq_weights_tree_remove(struct bfq_data *bfqd,
-+				      struct bfq_entity *entity,
-+				      struct rb_root *root);
-+
-+static void bfq_weights_tree_remove(struct bfq_data *bfqd,
-+				    struct bfq_queue *bfqq);
-+
-+
-+/**
-+ * bfq_active_insert - insert an entity in the active tree of its
-+ *                     group/device.
-+ * @st: the service tree of the entity.
-+ * @entity: the entity being inserted.
-+ *
-+ * The active tree is ordered by finish time, but an extra key is kept
-+ * per each node, containing the minimum value for the start times of
-+ * its children (and the node itself), so it's possible to search for
-+ * the eligible node with the lowest finish time in logarithmic time.
-+ */
-+static void bfq_active_insert(struct bfq_service_tree *st,
-+			      struct bfq_entity *entity)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+	struct rb_node *node = &entity->rb_node;
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	struct bfq_sched_data *sd = NULL;
-+	struct bfq_group *bfqg = NULL;
-+	struct bfq_data *bfqd = NULL;
-+#endif
-+
-+	bfq_insert(&st->active, entity);
-+
-+	if (node->rb_left)
-+		node = node->rb_left;
-+	else if (node->rb_right)
-+		node = node->rb_right;
-+
-+	bfq_update_active_tree(node);
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	sd = entity->sched_data;
-+	bfqg = container_of(sd, struct bfq_group, sched_data);
-+	BUG_ON(!bfqg);
-+	bfqd = (struct bfq_data *)bfqg->bfqd;
-+#endif
-+	if (bfqq)
-+		list_add(&bfqq->bfqq_list, &bfqq->bfqd->active_list);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	if (bfqg != bfqd->root_group) {
-+		BUG_ON(!bfqg);
-+		BUG_ON(!bfqd);
-+		bfqg->active_entities++;
-+	}
-+#endif
-+}
-+
-+/**
-+ * bfq_ioprio_to_weight - calc a weight from an ioprio.
-+ * @ioprio: the ioprio value to convert.
-+ */
-+static unsigned short bfq_ioprio_to_weight(int ioprio)
-+{
-+	BUG_ON(ioprio < 0 || ioprio >= IOPRIO_BE_NR);
-+	return (IOPRIO_BE_NR - ioprio) * BFQ_WEIGHT_CONVERSION_COEFF;
-+}
-+
-+/**
-+ * bfq_weight_to_ioprio - calc an ioprio from a weight.
-+ * @weight: the weight value to convert.
-+ *
-+ * To preserve as much as possible the old only-ioprio user interface,
-+ * 0 is used as an escape ioprio value for weights (numerically) equal or
-+ * larger than IOPRIO_BE_NR * BFQ_WEIGHT_CONVERSION_COEFF.
-+ */
-+static unsigned short bfq_weight_to_ioprio(int weight)
-+{
-+	BUG_ON(weight < BFQ_MIN_WEIGHT || weight > BFQ_MAX_WEIGHT);
-+	return IOPRIO_BE_NR * BFQ_WEIGHT_CONVERSION_COEFF - weight < 0 ?
-+		0 : IOPRIO_BE_NR * BFQ_WEIGHT_CONVERSION_COEFF - weight;
-+}
-+
-+static void bfq_get_entity(struct bfq_entity *entity)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+
-+	if (bfqq) {
-+		bfqq->ref++;
-+		bfq_log_bfqq(bfqq->bfqd, bfqq, "%p %d",
-+			     bfqq, bfqq->ref);
-+	}
-+}
-+
-+/**
-+ * bfq_find_deepest - find the deepest node that an extraction can modify.
-+ * @node: the node being removed.
-+ *
-+ * Do the first step of an extraction in an rb tree, looking for the
-+ * node that will replace @node, and returning the deepest node that
-+ * the following modifications to the tree can touch.  If @node is the
-+ * last node in the tree return %NULL.
-+ */
-+static struct rb_node *bfq_find_deepest(struct rb_node *node)
-+{
-+	struct rb_node *deepest;
-+
-+	if (!node->rb_right && !node->rb_left)
-+		deepest = rb_parent(node);
-+	else if (!node->rb_right)
-+		deepest = node->rb_left;
-+	else if (!node->rb_left)
-+		deepest = node->rb_right;
-+	else {
-+		deepest = rb_next(node);
-+		if (deepest->rb_right)
-+			deepest = deepest->rb_right;
-+		else if (rb_parent(deepest) != node)
-+			deepest = rb_parent(deepest);
-+	}
-+
-+	return deepest;
-+}
-+
-+/**
-+ * bfq_active_extract - remove an entity from the active tree.
-+ * @st: the service_tree containing the tree.
-+ * @entity: the entity being removed.
-+ */
-+static void bfq_active_extract(struct bfq_service_tree *st,
-+			       struct bfq_entity *entity)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+	struct rb_node *node;
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	struct bfq_sched_data *sd = NULL;
-+	struct bfq_group *bfqg = NULL;
-+	struct bfq_data *bfqd = NULL;
-+#endif
-+
-+	node = bfq_find_deepest(&entity->rb_node);
-+	bfq_extract(&st->active, entity);
-+
-+	if (node)
-+		bfq_update_active_tree(node);
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	sd = entity->sched_data;
-+	bfqg = container_of(sd, struct bfq_group, sched_data);
-+	BUG_ON(!bfqg);
-+	bfqd = (struct bfq_data *)bfqg->bfqd;
-+#endif
-+	if (bfqq)
-+		list_del(&bfqq->bfqq_list);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	if (bfqg != bfqd->root_group) {
-+		BUG_ON(!bfqg);
-+		BUG_ON(!bfqd);
-+		BUG_ON(!bfqg->active_entities);
-+		bfqg->active_entities--;
-+	}
-+#endif
-+}
-+
-+/**
-+ * bfq_idle_insert - insert an entity into the idle tree.
-+ * @st: the service tree containing the tree.
-+ * @entity: the entity to insert.
-+ */
-+static void bfq_idle_insert(struct bfq_service_tree *st,
-+			    struct bfq_entity *entity)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+	struct bfq_entity *first_idle = st->first_idle;
-+	struct bfq_entity *last_idle = st->last_idle;
-+
-+	if (!first_idle || bfq_gt(first_idle->finish, entity->finish))
-+		st->first_idle = entity;
-+	if (!last_idle || bfq_gt(entity->finish, last_idle->finish))
-+		st->last_idle = entity;
-+
-+	bfq_insert(&st->idle, entity);
-+
-+	if (bfqq)
-+		list_add(&bfqq->bfqq_list, &bfqq->bfqd->idle_list);
-+}
-+
-+/**
-+ * bfq_forget_entity - do not consider entity any longer for scheduling
-+ * @st: the service tree.
-+ * @entity: the entity being removed.
-+ * @is_in_service: true if entity is currently the in-service entity.
-+ *
-+ * Forget everything about @entity. In addition, if entity represents
-+ * a queue, and the latter is not in service, then release the service
-+ * reference to the queue (the one taken through bfq_get_entity). In
-+ * fact, in this case, there is really no more service reference to
-+ * the queue, as the latter is also outside any service tree. If,
-+ * instead, the queue is in service, then __bfq_bfqd_reset_in_service
-+ * will take care of putting the reference when the queue finally
-+ * stops being served.
-+ */
-+static void bfq_forget_entity(struct bfq_service_tree *st,
-+			      struct bfq_entity *entity,
-+			      bool is_in_service)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+	BUG_ON(!entity->on_st);
-+
-+	entity->on_st = false;
-+	st->wsum -= entity->weight;
-+	if (bfqq && !is_in_service) {
-+		bfq_log_bfqq(bfqq->bfqd, bfqq, "(before): %p %d",
-+			     bfqq, bfqq->ref);
-+		bfq_put_queue(bfqq);
-+	}
-+}
-+
-+/**
-+ * bfq_put_idle_entity - release the idle tree ref of an entity.
-+ * @st: service tree for the entity.
-+ * @entity: the entity being released.
-+ */
-+static void bfq_put_idle_entity(struct bfq_service_tree *st,
-+				struct bfq_entity *entity)
-+{
-+	bfq_idle_extract(st, entity);
-+	bfq_forget_entity(st, entity,
-+			  entity == entity->sched_data->in_service_entity);
-+}
-+
-+/**
-+ * bfq_forget_idle - update the idle tree if necessary.
-+ * @st: the service tree to act upon.
-+ *
-+ * To preserve the global O(log N) complexity we only remove one entry here;
-+ * as the idle tree will not grow indefinitely this can be done safely.
-+ */
-+static void bfq_forget_idle(struct bfq_service_tree *st)
-+{
-+	struct bfq_entity *first_idle = st->first_idle;
-+	struct bfq_entity *last_idle = st->last_idle;
-+
-+	if (RB_EMPTY_ROOT(&st->active) && last_idle &&
-+	    !bfq_gt(last_idle->finish, st->vtime)) {
-+		/*
-+		 * Forget the whole idle tree, increasing the vtime past
-+		 * the last finish time of idle entities.
-+		 */
-+		st->vtime = last_idle->finish;
-+	}
-+
-+	if (first_idle && !bfq_gt(first_idle->finish, st->vtime))
-+		bfq_put_idle_entity(st, first_idle);
-+}
-+
-+/*
-+ * Update weight and priority of entity. If update_class_too is true,
-+ * then update the ioprio_class of entity too.
-+ *
-+ * The reason why the update of ioprio_class is controlled through the
-+ * last parameter is as follows. Changing the ioprio class of an
-+ * entity implies changing the destination service trees for that
-+ * entity. If such a change occurred when the entity is already on one
-+ * of the service trees for its previous class, then the state of the
-+ * entity would become more complex: none of the new possible service
-+ * trees for the entity, according to bfq_entity_service_tree(), would
-+ * match any of the possible service trees on which the entity
-+ * is. Complex operations involving these trees, such as entity
-+ * activations and deactivations, should take into account this
-+ * additional complexity.  To avoid this issue, this function is
-+ * invoked with update_class_too unset in the points in the code where
-+ * entity may happen to be on some tree.
-+ */
-+static struct bfq_service_tree *
-+__bfq_entity_update_weight_prio(struct bfq_service_tree *old_st,
-+				struct bfq_entity *entity,
-+				bool update_class_too)
-+{
-+	struct bfq_service_tree *new_st = old_st;
-+
-+	if (entity->prio_changed) {
-+		struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+		unsigned int prev_weight, new_weight;
-+		struct bfq_data *bfqd = NULL;
-+		struct rb_root *root;
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+		struct bfq_sched_data *sd;
-+		struct bfq_group *bfqg;
-+#endif
-+
-+		if (bfqq)
-+			bfqd = bfqq->bfqd;
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+		else {
-+			sd = entity->my_sched_data;
-+			bfqg = container_of(sd, struct bfq_group, sched_data);
-+			BUG_ON(!bfqg);
-+			bfqd = (struct bfq_data *)bfqg->bfqd;
-+			BUG_ON(!bfqd);
-+		}
-+#endif
-+
-+		BUG_ON(entity->tree && update_class_too);
-+		BUG_ON(old_st->wsum < entity->weight);
-+		old_st->wsum -= entity->weight;
-+
-+		if (entity->new_weight != entity->orig_weight) {
-+			if (entity->new_weight < BFQ_MIN_WEIGHT ||
-+			    entity->new_weight > BFQ_MAX_WEIGHT) {
-+				pr_crit("update_weight_prio: new_weight %d\n",
-+					entity->new_weight);
-+				if (entity->new_weight < BFQ_MIN_WEIGHT)
-+					entity->new_weight = BFQ_MIN_WEIGHT;
-+				else
-+					entity->new_weight = BFQ_MAX_WEIGHT;
-+			}
-+			entity->orig_weight = entity->new_weight;
-+			if (bfqq)
-+				bfqq->ioprio =
-+				  bfq_weight_to_ioprio(entity->orig_weight);
-+		}
-+
-+		if (bfqq && update_class_too)
-+			bfqq->ioprio_class = bfqq->new_ioprio_class;
-+
-+		/*
-+		 * Reset prio_changed only if the ioprio_class change
-+		 * is not pending any longer.
-+		 */
-+		if (!bfqq || bfqq->ioprio_class == bfqq->new_ioprio_class)
-+			entity->prio_changed = 0;
-+
-+		/*
-+		 * NOTE: here we may be changing the weight too early,
-+		 * this will cause unfairness.  The correct approach
-+		 * would have required additional complexity to defer
-+		 * weight changes to the proper time instants (i.e.,
-+		 * when entity->finish <= old_st->vtime).
-+		 */
-+		new_st = bfq_entity_service_tree(entity);
-+
-+		prev_weight = entity->weight;
-+		new_weight = entity->orig_weight *
-+			     (bfqq ? bfqq->wr_coeff : 1);
-+		/*
-+		 * If the weight of the entity changes, remove the entity
-+		 * from its old weight counter (if there is a counter
-+		 * associated with the entity), and add it to the counter
-+		 * associated with its new weight.
-+		 */
-+		if (prev_weight != new_weight) {
-+			if (bfqq)
-+				bfq_log_bfqq(bfqq->bfqd, bfqq,
-+					     "weight changed %d %d(%d %d)",
-+					     prev_weight, new_weight,
-+					     entity->orig_weight,
-+					     bfqq->wr_coeff);
-+
-+			root = bfqq ? &bfqd->queue_weights_tree :
-+				      &bfqd->group_weights_tree;
-+			__bfq_weights_tree_remove(bfqd, entity, root);
-+		}
-+		entity->weight = new_weight;
-+		/*
-+		 * Add the entity to its weights tree only if it is
-+		 * not associated with a weight-raised queue.
-+		 */
-+		if (prev_weight != new_weight &&
-+		    (bfqq ? bfqq->wr_coeff == 1 : 1))
-+			/* If we get here, root has been initialized. */
-+			bfq_weights_tree_add(bfqd, entity, root);
-+
-+		new_st->wsum += entity->weight;
-+
-+		if (new_st != old_st) {
-+			BUG_ON(!update_class_too);
-+			entity->start = new_st->vtime;
-+		}
-+	}
-+
-+	return new_st;
-+}
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+static void bfqg_stats_set_start_empty_time(struct bfq_group *bfqg);
-+#endif
-+
-+/**
-+ * bfq_bfqq_served - update the scheduler status after selection for
-+ *                   service.
-+ * @bfqq: the queue being served.
-+ * @served: bytes to transfer.
-+ *
-+ * NOTE: this can be optimized, as the timestamps of upper level entities
-+ * are synchronized every time a new bfqq is selected for service.  By now,
-+ * we keep it to better check consistency.
-+ */
-+static void bfq_bfqq_served(struct bfq_queue *bfqq, int served)
-+{
-+	struct bfq_entity *entity = &bfqq->entity;
-+	struct bfq_service_tree *st;
-+
-+	if (!bfqq->service_from_backlogged)
-+		bfqq->first_IO_time = jiffies;
-+
-+	if (bfqq->wr_coeff > 1)
-+		bfqq->service_from_wr += served;
-+
-+	bfqq->service_from_backlogged += served;
-+	for_each_entity(entity) {
-+		st = bfq_entity_service_tree(entity);
-+
-+		entity->service += served;
-+
-+		BUG_ON(st->wsum == 0);
-+
-+		st->vtime += bfq_delta(served, st->wsum);
-+		bfq_forget_idle(st);
-+	}
-+#ifndef BFQ_MQ
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	bfqg_stats_set_start_empty_time(bfqq_group(bfqq));
-+#endif
-+#endif
-+	st = bfq_entity_service_tree(&bfqq->entity);
-+	bfq_log_bfqq(bfqq->bfqd, bfqq, "bfqq_served %d secs, vtime %llu on %p",
-+		     served,  ((st->vtime>>10)*1000)>>12, st);
-+}
-+
-+/**
-+ * bfq_bfqq_charge_time - charge an amount of service equivalent to the length
-+ *			  of the time interval during which bfqq has been in
-+ *			  service.
-+ * @bfqd: the device
-+ * @bfqq: the queue that needs a service update.
-+ * @time_ms: the amount of time during which the queue has received service
-+ *
-+ * If a queue does not consume its budget fast enough, then providing
-+ * the queue with service fairness may impair throughput, more or less
-+ * severely. For this reason, queues that consume their budget slowly
-+ * are provided with time fairness instead of service fairness. This
-+ * goal is achieved through the BFQ scheduling engine, even if such an
-+ * engine works in the service, and not in the time domain. The trick
-+ * is charging these queues with an inflated amount of service, equal
-+ * to the amount of service that they would have received during their
-+ * service slot if they had been fast, i.e., if their requests had
-+ * been dispatched at a rate equal to the estimated peak rate.
-+ *
-+ * It is worth noting that time fairness can cause important
-+ * distortions in terms of bandwidth distribution, on devices with
-+ * internal queueing. The reason is that I/O requests dispatched
-+ * during the service slot of a queue may be served after that service
-+ * slot is finished, and may have a total processing time loosely
-+ * correlated with the duration of the service slot. This is
-+ * especially true for short service slots.
-+ */
-+static void bfq_bfqq_charge_time(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+				 unsigned long time_ms)
-+{
-+	struct bfq_entity *entity = &bfqq->entity;
-+	unsigned long timeout_ms = jiffies_to_msecs(bfq_timeout);
-+	unsigned long bounded_time_ms = min(time_ms, timeout_ms);
-+	int serv_to_charge_for_time =
-+		(bfqd->bfq_max_budget * bounded_time_ms) / timeout_ms;
-+	int tot_serv_to_charge = max(serv_to_charge_for_time, entity->service);
-+
-+	bfq_log_bfqq(bfqq->bfqd, bfqq,
-+		     "%lu/%lu ms, %d/%d/%d/%d sectors",
-+		     time_ms, timeout_ms,
-+		     entity->service,
-+		     tot_serv_to_charge,
-+		     bfqd->bfq_max_budget,
-+		     entity->budget);
-+
-+	/* Increase budget to avoid inconsistencies */
-+	if (tot_serv_to_charge > entity->budget)
-+		entity->budget = tot_serv_to_charge;
-+
-+	bfq_bfqq_served(bfqq,
-+			max_t(int, 0, tot_serv_to_charge - entity->service));
-+}
-+
-+static void bfq_update_fin_time_enqueue(struct bfq_entity *entity,
-+					struct bfq_service_tree *st,
-+					bool backshifted)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+	struct bfq_sched_data *sd = entity->sched_data;
-+
-+	/*
-+	 * When this function is invoked, entity is not in any service
-+	 * tree, then it is safe to invoke next function with the last
-+	 * parameter set (see the comments on the function).
-+	 */
-+	BUG_ON(entity->tree);
-+	st = __bfq_entity_update_weight_prio(st, entity, true);
-+	bfq_calc_finish(entity, entity->budget);
-+
-+	/*
-+	 * If some queues enjoy backshifting for a while, then their
-+	 * (virtual) finish timestamps may happen to become lower and
-+	 * lower than the system virtual time.  In particular, if
-+	 * these queues often happen to be idle for short time
-+	 * periods, and during such time periods other queues with
-+	 * higher timestamps happen to be busy, then the backshifted
-+	 * timestamps of the former queues can become much lower than
-+	 * the system virtual time. In fact, to serve the queues with
-+	 * higher timestamps while the ones with lower timestamps are
-+	 * idle, the system virtual time may be pushed-up to much
-+	 * higher values than the finish timestamps of the idle
-+	 * queues. As a consequence, the finish timestamps of all new
-+	 * or newly activated queues may end up being much larger than
-+	 * those of lucky queues with backshifted timestamps. The
-+	 * latter queues may then monopolize the device for a lot of
-+	 * time. This would simply break service guarantees.
-+	 *
-+	 * To reduce this problem, push up a little bit the
-+	 * backshifted timestamps of the queue associated with this
-+	 * entity (only a queue can happen to have the backshifted
-+	 * flag set): just enough to let the finish timestamp of the
-+	 * queue be equal to the current value of the system virtual
-+	 * time. This may introduce a little unfairness among queues
-+	 * with backshifted timestamps, but it does not break
-+	 * worst-case fairness guarantees.
-+	 *
-+	 * As a special case, if bfqq is weight-raised, push up
-+	 * timestamps much less, to keep very low the probability that
-+	 * this push up causes the backshifted finish timestamps of
-+	 * weight-raised queues to become higher than the backshifted
-+	 * finish timestamps of non weight-raised queues.
-+	 */
-+	if (backshifted && bfq_gt(st->vtime, entity->finish)) {
-+		unsigned long delta = st->vtime - entity->finish;
-+
-+		if (bfqq)
-+			delta /= bfqq->wr_coeff;
-+
-+		entity->start += delta;
-+		entity->finish += delta;
-+
-+		if (bfqq) {
-+			bfq_log_bfqq(bfqq->bfqd, bfqq,
-+				     "new queue finish %llu",
-+				     ((entity->finish>>10)*1000)>>12);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+		} else {
-+			struct bfq_group *bfqg =
-+				container_of(entity, struct bfq_group, entity);
-+
-+			bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+				     "new group finish %llu",
-+				     ((entity->finish>>10)*1000)>>12);
-+#endif
-+		}
-+	}
-+
-+	bfq_active_insert(st, entity);
-+
-+	if (bfqq) {
-+		bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			"queue %seligible in st %p",
-+			     entity->start <= st->vtime ? "" : "non ", st);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	} else {
-+		struct bfq_group *bfqg =
-+			container_of(entity, struct bfq_group, entity);
-+
-+		bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+			"group %seligible in st %p",
-+			     entity->start <= st->vtime ? "" : "non ", st);
-+#endif
-+	}
-+	BUG_ON(RB_EMPTY_ROOT(&st->active));
-+	BUG_ON(&st->active != &sd->service_tree->active &&
-+	       &st->active != &(sd->service_tree+1)->active &&
-+	       &st->active != &(sd->service_tree+2)->active);
-+}
-+
-+/**
-+ * __bfq_activate_entity - handle activation of entity.
-+ * @entity: the entity being activated.
-+ * @non_blocking_wait_rq: true if entity was waiting for a request
-+ *
-+ * Called for a 'true' activation, i.e., if entity is not active and
-+ * one of its children receives a new request.
-+ *
-+ * Basically, this function updates the timestamps of entity and
-+ * inserts entity into its active tree, after possibly extracting it
-+ * from its idle tree.
-+ */
-+static void __bfq_activate_entity(struct bfq_entity *entity,
-+				  bool non_blocking_wait_rq)
-+{
-+	struct bfq_sched_data *sd = entity->sched_data;
-+	struct bfq_service_tree *st = bfq_entity_service_tree(entity);
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+	bool backshifted = false;
-+	unsigned long long min_vstart;
-+
-+	BUG_ON(!sd);
-+	BUG_ON(!st);
-+
-+	/* See comments on bfq_fqq_update_budg_for_activation */
-+	if (non_blocking_wait_rq && bfq_gt(st->vtime, entity->finish)) {
-+		backshifted = true;
-+		min_vstart = entity->finish;
-+	} else
-+		min_vstart = st->vtime;
-+
-+	if (entity->tree == &st->idle) {
-+		/*
-+		 * Must be on the idle tree, bfq_idle_extract() will
-+		 * check for that.
-+		 */
-+		bfq_idle_extract(st, entity);
-+		BUG_ON(entity->tree);
-+		entity->start = bfq_gt(min_vstart, entity->finish) ?
-+			min_vstart : entity->finish;
-+	} else {
-+		BUG_ON(entity->tree);
-+		/*
-+		 * The finish time of the entity may be invalid, and
-+		 * it is in the past for sure, otherwise the queue
-+		 * would have been on the idle tree.
-+		 */
-+		entity->start = min_vstart;
-+		st->wsum += entity->weight;
-+		/*
-+		 * entity is about to be inserted into a service tree,
-+		 * and then set in service: get a reference to make
-+		 * sure entity does not disappear until it is no
-+		 * longer in service or scheduled for service.
-+		 */
-+		bfq_get_entity(entity);
-+
-+		BUG_ON(entity->on_st && bfqq);
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+		if (entity->on_st && !bfqq) {
-+			struct bfq_group *bfqg =
-+				container_of(entity, struct bfq_group,
-+					     entity);
-+
-+			bfq_log_bfqg((struct bfq_data *)bfqg->bfqd,
-+				     bfqg,
-+				     "activate bug, class %d in_service %p",
-+				     bfq_class_idx(entity), sd->in_service_entity);
-+		}
-+#endif
-+		BUG_ON(entity->on_st && !bfqq);
-+		entity->on_st = true;
-+	}
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	if (!bfq_entity_to_bfqq(entity)) { /* bfq_group */
-+		struct bfq_group *bfqg =
-+			container_of(entity, struct bfq_group, entity);
-+		struct bfq_data *bfqd = bfqg->bfqd;
-+
-+		BUG_ON(!bfqd);
-+		bfq_weights_tree_add(bfqd, entity, &bfqd->group_weights_tree);
-+	}
-+#endif
-+
-+	bfq_update_fin_time_enqueue(entity, st, backshifted);
-+}
-+
-+/**
-+ * __bfq_requeue_entity - handle requeueing or repositioning of an entity.
-+ * @entity: the entity being requeued or repositioned.
-+ *
-+ * Requeueing is needed if this entity stops being served, which
-+ * happens if a leaf descendant entity has expired. On the other hand,
-+ * repositioning is needed if the next_inservice_entity for the child
-+ * entity has changed. See the comments inside the function for
-+ * details.
-+ *
-+ * Basically, this function: 1) removes entity from its active tree if
-+ * present there, 2) updates the timestamps of entity and 3) inserts
-+ * entity back into its active tree (in the new, right position for
-+ * the new values of the timestamps).
-+ */
-+static void __bfq_requeue_entity(struct bfq_entity *entity)
-+{
-+	struct bfq_sched_data *sd = entity->sched_data;
-+	struct bfq_service_tree *st = bfq_entity_service_tree(entity);
-+
-+	BUG_ON(!sd);
-+	BUG_ON(!st);
-+
-+	BUG_ON(entity != sd->in_service_entity &&
-+	       entity->tree != &st->active);
-+
-+	if (entity == sd->in_service_entity) {
-+		/*
-+		 * We are requeueing the current in-service entity,
-+		 * which may have to be done for one of the following
-+		 * reasons:
-+		 * - entity represents the in-service queue, and the
-+		 *   in-service queue is being requeued after an
-+		 *   expiration;
-+		 * - entity represents a group, and its budget has
-+		 *   changed because one of its child entities has
-+		 *   just been either activated or requeued for some
-+		 *   reason; the timestamps of the entity need then to
-+		 *   be updated, and the entity needs to be enqueued
-+		 *   or repositioned accordingly.
-+		 *
-+		 * In particular, before requeueing, the start time of
-+		 * the entity must be moved forward to account for the
-+		 * service that the entity has received while in
-+		 * service. This is done by the next instructions. The
-+		 * finish time will then be updated according to this
-+		 * new value of the start time, and to the budget of
-+		 * the entity.
-+		 */
-+		bfq_calc_finish(entity, entity->service);
-+		entity->start = entity->finish;
-+		BUG_ON(entity->tree && entity->tree == &st->idle);
-+		BUG_ON(entity->tree && entity->tree != &st->active);
-+		/*
-+		 * In addition, if the entity had more than one child
-+		 * when set in service, then it was not extracted from
-+		 * the active tree. This implies that the position of
-+		 * the entity in the active tree may need to be
-+		 * changed now, because we have just updated the start
-+		 * time of the entity, and we will update its finish
-+		 * time in a moment (the requeueing is then, more
-+		 * precisely, a repositioning in this case). To
-+		 * implement this repositioning, we: 1) dequeue the
-+		 * entity here, 2) update the finish time and requeue
-+		 * the entity according to the new timestamps below.
-+		 */
-+		if (entity->tree)
-+			bfq_active_extract(st, entity);
-+	} else { /* The entity is already active, and not in service */
-+		/*
-+		 * In this case, this function gets called only if the
-+		 * next_in_service entity below this entity has
-+		 * changed, and this change has caused the budget of
-+		 * this entity to change, which, finally implies that
-+		 * the finish time of this entity must be
-+		 * updated. Such an update may cause the scheduling,
-+		 * i.e., the position in the active tree, of this
-+		 * entity to change. We handle this change by: 1)
-+		 * dequeueing the entity here, 2) updating the finish
-+		 * time and requeueing the entity according to the new
-+		 * timestamps below. This is the same approach as the
-+		 * non-extracted-entity sub-case above.
-+		 */
-+		bfq_active_extract(st, entity);
-+	}
-+
-+	bfq_update_fin_time_enqueue(entity, st, false);
-+}
-+
-+static void __bfq_activate_requeue_entity(struct bfq_entity *entity,
-+					  struct bfq_sched_data *sd,
-+					  bool non_blocking_wait_rq)
-+{
-+	struct bfq_service_tree *st = bfq_entity_service_tree(entity);
-+
-+	if (sd->in_service_entity == entity || entity->tree == &st->active)
-+		 /*
-+		  * in service or already queued on the active tree,
-+		  * requeue or reposition
-+		  */
-+		__bfq_requeue_entity(entity);
-+	else
-+		/*
-+		 * Not in service and not queued on its active tree:
-+		 * the activity is idle and this is a true activation.
-+		 */
-+		__bfq_activate_entity(entity, non_blocking_wait_rq);
-+}
-+
-+
-+/**
-+ * bfq_activate_requeue_entity - activate or requeue an entity representing a bfq_queue,
-+ *			 	 and activate, requeue or reposition all ancestors
-+ *			 	 for which such an update becomes necessary.
-+ * @entity: the entity to activate.
-+ * @non_blocking_wait_rq: true if this entity was waiting for a request
-+ * @requeue: true if this is a requeue, which implies that bfqq is
-+ *	     being expired; thus ALL its ancestors stop being served and must
-+ *	     therefore be requeued
-+ * @expiration: true if this function is being invoked in the expiration path
-+ *		of the in-service queue
-+ */
-+static void bfq_activate_requeue_entity(struct bfq_entity *entity,
-+					bool non_blocking_wait_rq,
-+					bool requeue, bool expiration)
-+{
-+	struct bfq_sched_data *sd;
-+
-+	for_each_entity(entity) {
-+		BUG_ON(!entity);
-+		sd = entity->sched_data;
-+		__bfq_activate_requeue_entity(entity, sd, non_blocking_wait_rq);
-+
-+		BUG_ON(RB_EMPTY_ROOT(&sd->service_tree->active) &&
-+		       RB_EMPTY_ROOT(&(sd->service_tree+1)->active) &&
-+		       RB_EMPTY_ROOT(&(sd->service_tree+2)->active));
-+
-+		if (!bfq_update_next_in_service(sd, entity, expiration) &&
-+		    !requeue) {
-+			BUG_ON(!sd->next_in_service);
-+			break;
-+		}
-+		BUG_ON(!sd->next_in_service);
-+	}
-+}
-+
-+/**
-+ * __bfq_deactivate_entity - deactivate an entity from its service tree.
-+ * @entity: the entity to deactivate.
-+ * @ins_into_idle_tree: if false, the entity will not be put into the
-+ *			idle tree.
-+ *
-+ * Deactivates an entity, independently of its previous state.  Must
-+ * be invoked only if entity is on a service tree. Extracts the entity
-+ * from that tree, and if necessary and allowed, puts it into the idle
-+ * tree.
-+ */
-+static bool __bfq_deactivate_entity(struct bfq_entity *entity,
-+				    bool ins_into_idle_tree)
-+{
-+	struct bfq_sched_data *sd = entity->sched_data;
-+	struct bfq_service_tree *st;
-+	bool is_in_service;
-+
-+	if (!entity->on_st) { /* entity never activated, or already inactive */
-+		BUG_ON(sd && entity == sd->in_service_entity);
-+		return false;
-+	}
-+
-+	/*
-+	 * If we get here, then entity is active, which implies that
-+	 * bfq_group_set_parent has already been invoked for the group
-+	 * represented by entity. Therefore, the field
-+	 * entity->sched_data has been set, and we can safely use it.
-+	 */
-+	st = bfq_entity_service_tree(entity);
-+	is_in_service = entity == sd->in_service_entity;
-+
-+	BUG_ON(is_in_service && entity->tree && entity->tree != &st->active);
-+
-+	bfq_calc_finish(entity, entity->service);
-+
-+	if (is_in_service) {
-+		sd->in_service_entity = NULL;
-+	} else
-+		/*
-+		 * Non in-service entity: nobody will take care of
-+		 * resetting its service counter on expiration. Do it
-+		 * now.
-+		 */
-+		entity->service = 0;
-+
-+	if (entity->tree == &st->active)
-+		bfq_active_extract(st, entity);
-+	else if (!is_in_service && entity->tree == &st->idle)
-+		bfq_idle_extract(st, entity);
-+	else if (entity->tree)
-+		BUG();
-+
-+	if (!ins_into_idle_tree || !bfq_gt(entity->finish, st->vtime))
-+		bfq_forget_entity(st, entity, is_in_service);
-+	else
-+		bfq_idle_insert(st, entity);
-+
-+	return true;
-+}
-+
-+/**
-+ * bfq_deactivate_entity - deactivate an entity representing a bfq_queue.
-+ * @entity: the entity to deactivate.
-+ * @ins_into_idle_tree: true if the entity can be put into the idle tree
-+ * @expiration: true if this function is being invoked in the expiration path
-+ *		of the in-service queue
-+ */
-+static void bfq_deactivate_entity(struct bfq_entity *entity,
-+				  bool ins_into_idle_tree,
-+				  bool expiration)
-+{
-+	struct bfq_sched_data *sd;
-+	struct bfq_entity *parent = NULL;
-+
-+	for_each_entity_safe(entity, parent) {
-+		sd = entity->sched_data;
-+
-+		BUG_ON(sd == NULL); /*
-+				     * It would mean that this is the
-+				     * root group.
-+				     */
-+
-+		BUG_ON(expiration && entity != sd->in_service_entity);
-+
-+		BUG_ON(entity != sd->in_service_entity &&
-+		       entity->tree ==
-+		       &bfq_entity_service_tree(entity)->active &&
-+		       !sd->next_in_service);
-+
-+		if (!__bfq_deactivate_entity(entity, ins_into_idle_tree)) {
-+			/*
-+			 * entity is not in any tree any more, so
-+			 * this deactivation is a no-op, and there is
-+			 * nothing to change for upper-level entities
-+			 * (in case of expiration, this can never
-+			 * happen).
-+			 */
-+			BUG_ON(expiration); /*
-+					     * entity cannot be already out of
-+					     * any tree
-+					     */
-+			return;
-+		}
-+
-+		if (sd->next_in_service == entity)
-+			/*
-+			 * entity was the next_in_service entity,
-+			 * then, since entity has just been
-+			 * deactivated, a new one must be found.
-+			 */
-+			bfq_update_next_in_service(sd, NULL, expiration);
-+
-+		if (sd->next_in_service || sd->in_service_entity) {
-+			/*
-+			 * The parent entity is still active, because
-+			 * either next_in_service or in_service_entity
-+			 * is not NULL. So, no further upwards
-+			 * deactivation must be performed.  Yet,
-+			 * next_in_service has changed.  Then the
-+			 * schedule does need to be updated upwards.
-+			 *
-+			 * NOTE If in_service_entity is not NULL, then
-+			 * next_in_service may happen to be NULL,
-+			 * although the parent entity is evidently
-+			 * active. This happens if 1) the entity
-+			 * pointed by in_service_entity is the only
-+			 * active entity in the parent entity, and 2)
-+			 * according to the definition of
-+			 * next_in_service, the in_service_entity
-+			 * cannot be considered as
-+			 * next_in_service. See the comments on the
-+			 * definition of next_in_service for details.
-+			 */
-+			BUG_ON(sd->next_in_service == entity);
-+			BUG_ON(sd->in_service_entity == entity);
-+			break;
-+		}
-+
-+		/*
-+		 * If we get here, then the parent is no more
-+		 * backlogged and we need to propagate the
-+		 * deactivation upwards. Thus let the loop go on.
-+		 */
-+
-+		/*
-+		 * Also let parent be queued into the idle tree on
-+		 * deactivation, to preserve service guarantees, and
-+		 * assuming that who invoked this function does not
-+		 * need parent entities too to be removed completely.
-+		 */
-+		ins_into_idle_tree = true;
-+	}
-+
-+	/*
-+	 * If the deactivation loop is fully executed, then there are
-+	 * no more entities to touch and next loop is not executed at
-+	 * all. Otherwise, requeue remaining entities if they are
-+	 * about to stop receiving service, or reposition them if this
-+	 * is not the case.
-+	 */
-+	entity = parent;
-+	for_each_entity(entity) {
-+		struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+
-+		/*
-+		 * Invoke __bfq_requeue_entity on entity, even if
-+		 * already active, to requeue/reposition it in the
-+		 * active tree (because sd->next_in_service has
-+		 * changed)
-+		 */
-+		__bfq_requeue_entity(entity);
-+
-+		sd = entity->sched_data;
-+		BUG_ON(expiration && sd->in_service_entity != entity);
-+
-+		if (bfqq)
-+			bfq_log_bfqq(bfqq->bfqd, bfqq,
-+				     "invoking udpdate_next for this queue");
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+		else {
-+			struct bfq_group *bfqg =
-+				container_of(entity,
-+					     struct bfq_group, entity);
-+
-+			bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+				     "invoking udpdate_next for this entity");
-+		}
-+#endif
-+		if (!bfq_update_next_in_service(sd, entity, expiration) &&
-+		    !expiration)
-+			/*
-+			 * next_in_service unchanged or not causing
-+			 * any change in entity->parent->sd, and no
-+			 * requeueing needed for expiration: stop
-+			 * here.
-+			 */
-+			break;
-+	}
-+}
-+
-+/**
-+ * bfq_calc_vtime_jump - compute the value to which the vtime should jump,
-+ *                       if needed, to have at least one entity eligible.
-+ * @st: the service tree to act upon.
-+ *
-+ * Assumes that st is not empty.
-+ */
-+static u64 bfq_calc_vtime_jump(struct bfq_service_tree *st)
-+{
-+	struct bfq_entity *root_entity = bfq_root_active_entity(&st->active);
-+
-+	if (bfq_gt(root_entity->min_start, st->vtime)) {
-+		struct bfq_queue *bfqq = bfq_entity_to_bfqq(root_entity);
-+
-+		if (bfqq)
-+			bfq_log_bfqq(bfqq->bfqd, bfqq,
-+				     "new value %llu",
-+				     ((root_entity->min_start>>10)*1000)>>12);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+		else {
-+			struct bfq_group *bfqg =
-+				container_of(root_entity, struct bfq_group,
-+					     entity);
-+
-+			bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+				     "new value %llu",
-+				     ((root_entity->min_start>>10)*1000)>>12);
-+		}
-+#endif
-+		return root_entity->min_start;
-+	}
-+	return st->vtime;
-+}
-+
-+static void bfq_update_vtime(struct bfq_service_tree *st, u64 new_value)
-+{
-+	if (new_value > st->vtime) {
-+		st->vtime = new_value;
-+		bfq_forget_idle(st);
-+	}
-+}
-+
-+/**
-+ * bfq_first_active_entity - find the eligible entity with
-+ *                           the smallest finish time
-+ * @st: the service tree to select from.
-+ * @vtime: the system virtual to use as a reference for eligibility
-+ *
-+ * This function searches the first schedulable entity, starting from the
-+ * root of the tree and going on the left every time on this side there is
-+ * a subtree with at least one eligible (start >= vtime) entity. The path on
-+ * the right is followed only if a) the left subtree contains no eligible
-+ * entities and b) no eligible entity has been found yet.
-+ */
-+static struct bfq_entity *bfq_first_active_entity(struct bfq_service_tree *st,
-+						  u64 vtime)
-+{
-+	struct bfq_entity *entry, *first = NULL;
-+	struct rb_node *node = st->active.rb_node;
-+
-+	while (node) {
-+		entry = rb_entry(node, struct bfq_entity, rb_node);
-+left:
-+		if (!bfq_gt(entry->start, vtime))
-+			first = entry;
-+
-+		BUG_ON(bfq_gt(entry->min_start, vtime));
-+
-+		if (node->rb_left) {
-+			entry = rb_entry(node->rb_left,
-+					 struct bfq_entity, rb_node);
-+			if (!bfq_gt(entry->min_start, vtime)) {
-+				node = node->rb_left;
-+				goto left;
-+			}
-+		}
-+		if (first)
-+			break;
-+		node = node->rb_right;
-+	}
-+
-+	BUG_ON(!first && !RB_EMPTY_ROOT(&st->active));
-+	return first;
-+}
-+
-+/**
-+ * __bfq_lookup_next_entity - return the first eligible entity in @st.
-+ * @st: the service tree.
-+ *
-+ * If there is no in-service entity for the sched_data st belongs to,
-+ * then return the entity that will be set in service if:
-+ * 1) the parent entity this st belongs to is set in service;
-+ * 2) no entity belonging to such parent entity undergoes a state change
-+ * that would influence the timestamps of the entity (e.g., becomes idle,
-+ * becomes backlogged, changes its budget, ...).
-+ *
-+ * In this first case, update the virtual time in @st too (see the
-+ * comments on this update inside the function).
-+ *
-+ * In constrast, if there is an in-service entity, then return the
-+ * entity that would be set in service if not only the above
-+ * conditions, but also the next one held true: the currently
-+ * in-service entity, on expiration,
-+ * 1) gets a finish time equal to the current one, or
-+ * 2) is not eligible any more, or
-+ * 3) is idle.
-+ */
-+static struct bfq_entity *
-+__bfq_lookup_next_entity(struct bfq_service_tree *st, bool in_service)
-+{
-+	struct bfq_entity *entity;
-+	u64 new_vtime;
-+	struct bfq_queue *bfqq;
-+
-+	if (RB_EMPTY_ROOT(&st->active))
-+		return NULL;
-+
-+	/*
-+	 * Get the value of the system virtual time for which at
-+	 * least one entity is eligible.
-+	 */
-+	new_vtime = bfq_calc_vtime_jump(st);
-+
-+	/*
-+	 * If there is no in-service entity for the sched_data this
-+	 * active tree belongs to, then push the system virtual time
-+	 * up to the value that guarantees that at least one entity is
-+	 * eligible. If, instead, there is an in-service entity, then
-+	 * do not make any such update, because there is already an
-+	 * eligible entity, namely the in-service one (even if the
-+	 * entity is not on st, because it was extracted when set in
-+	 * service).
-+	 */
-+	if (!in_service)
-+		bfq_update_vtime(st, new_vtime);
-+
-+	entity = bfq_first_active_entity(st, new_vtime);
-+	BUG_ON(bfq_gt(entity->start, new_vtime));
-+
-+	/* Log some information */
-+	bfqq = bfq_entity_to_bfqq(entity);
-+	if (bfqq)
-+		bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			     "start %llu vtime %llu st %p",
-+			     ((entity->start>>10)*1000)>>12,
-+			     ((new_vtime>>10)*1000)>>12, st);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	else {
-+		struct bfq_group *bfqg =
-+			container_of(entity, struct bfq_group, entity);
-+
-+		bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+			     "start %llu vtime %llu (%llu) st %p",
-+			     ((entity->start>>10)*1000)>>12,
-+			     ((st->vtime>>10)*1000)>>12,
-+			     ((new_vtime>>10)*1000)>>12, st);
-+	}
-+#endif
-+
-+	BUG_ON(!entity);
-+
-+	return entity;
-+}
-+
-+/**
-+ * bfq_lookup_next_entity - return the first eligible entity in @sd.
-+ * @sd: the sched_data.
-+ * @expiration: true if we are on the expiration path of the in-service queue
-+ *
-+ * This function is invoked when there has been a change in the trees
-+ * for sd, and we need to know what is the new next entity to serve
-+ * after this change.
-+ */
-+static struct bfq_entity *bfq_lookup_next_entity(struct bfq_sched_data *sd,
-+						 bool expiration)
-+{
-+	struct bfq_service_tree *st = sd->service_tree;
-+	struct bfq_service_tree *idle_class_st = st + (BFQ_IOPRIO_CLASSES - 1);
-+	struct bfq_entity *entity = NULL;
-+	struct bfq_queue *bfqq;
-+	int class_idx = 0;
-+
-+	BUG_ON(!sd);
-+	BUG_ON(!st);
-+	/*
-+	 * Choose from idle class, if needed to guarantee a minimum
-+	 * bandwidth to this class (and if there is some active entity
-+	 * in idle class). This should also mitigate
-+	 * priority-inversion problems in case a low priority task is
-+	 * holding file system resources.
-+	 */
-+	if (time_is_before_jiffies(sd->bfq_class_idle_last_service +
-+				   BFQ_CL_IDLE_TIMEOUT)) {
-+		if (!RB_EMPTY_ROOT(&idle_class_st->active))
-+			class_idx = BFQ_IOPRIO_CLASSES - 1;
-+		/* About to be served if backlogged, or not yet backlogged */
-+		sd->bfq_class_idle_last_service = jiffies;
-+	}
-+
-+	/*
-+	 * Find the next entity to serve for the highest-priority
-+	 * class, unless the idle class needs to be served.
-+	 */
-+	for (; class_idx < BFQ_IOPRIO_CLASSES; class_idx++) {
-+		/*
-+		 * If expiration is true, then bfq_lookup_next_entity
-+		 * is being invoked as a part of the expiration path
-+		 * of the in-service queue. In this case, even if
-+		 * sd->in_service_entity is not NULL,
-+		 * sd->in_service_entiy at this point is actually not
-+		 * in service any more, and, if needed, has already
-+		 * been properly queued or requeued into the right
-+		 * tree. The reason why sd->in_service_entity is still
-+		 * not NULL here, even if expiration is true, is that
-+		 * sd->in_service_entiy is reset as a last step in the
-+		 * expiration path. So, if expiration is true, tell
-+		 * __bfq_lookup_next_entity that there is no
-+		 * sd->in_service_entity.
-+		 */
-+		entity = __bfq_lookup_next_entity(st + class_idx,
-+						  sd->in_service_entity &&
-+						  !expiration);
-+
-+		if (entity)
-+			break;
-+	}
-+
-+	BUG_ON(!entity &&
-+	       (!RB_EMPTY_ROOT(&st->active) || !RB_EMPTY_ROOT(&(st+1)->active) ||
-+		!RB_EMPTY_ROOT(&(st+2)->active)));
-+
-+	if (!entity)
-+		return NULL;
-+
-+	/* Log some information */
-+	bfqq = bfq_entity_to_bfqq(entity);
-+	if (bfqq)
-+		bfq_log_bfqq(bfqq->bfqd, bfqq, "chosen from st %p %d",
-+			     st + class_idx, class_idx);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	else {
-+		struct bfq_group *bfqg =
-+			container_of(entity, struct bfq_group, entity);
-+
-+		bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+			     "chosen from st %p %d",
-+			     st + class_idx, class_idx);
-+	}
-+#endif
-+
-+	return entity;
-+}
-+
-+static bool next_queue_may_preempt(struct bfq_data *bfqd)
-+{
-+	struct bfq_sched_data *sd = &bfqd->root_group->sched_data;
-+
-+	return sd->next_in_service != sd->in_service_entity;
-+}
-+
-+/*
-+ * Get next queue for service.
-+ */
-+static struct bfq_queue *bfq_get_next_queue(struct bfq_data *bfqd)
-+{
-+	struct bfq_entity *entity = NULL;
-+	struct bfq_sched_data *sd;
-+	struct bfq_queue *bfqq;
-+
-+	BUG_ON(bfqd->in_service_queue);
-+
-+	if (bfqd->busy_queues == 0)
-+		return NULL;
-+
-+	/*
-+	 * Traverse the path from the root to the leaf entity to
-+	 * serve. Set in service all the entities visited along the
-+	 * way.
-+	 */
-+	sd = &bfqd->root_group->sched_data;
-+	for (; sd ; sd = entity->my_sched_data) {
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+		if (entity) {
-+			struct bfq_group *bfqg =
-+				container_of(entity, struct bfq_group, entity);
-+
-+			bfq_log_bfqg(bfqd, bfqg,
-+				     "lookup in this group");
-+			if (!sd->next_in_service)
-+				pr_crit("lookup in this group");
-+		} else {
-+			bfq_log_bfqg(bfqd, bfqd->root_group,
-+				     "lookup in root group");
-+			if (!sd->next_in_service)
-+				pr_crit("lookup in root group");
-+		}
-+#endif
-+
-+		BUG_ON(!sd->next_in_service);
-+
-+		/*
-+		 * WARNING. We are about to set the in-service entity
-+		 * to sd->next_in_service, i.e., to the (cached) value
-+		 * returned by bfq_lookup_next_entity(sd) the last
-+		 * time it was invoked, i.e., the last time when the
-+		 * service order in sd changed as a consequence of the
-+		 * activation or deactivation of an entity. In this
-+		 * respect, if we execute bfq_lookup_next_entity(sd)
-+		 * in this very moment, it may, although with low
-+		 * probability, yield a different entity than that
-+		 * pointed to by sd->next_in_service. This rare event
-+		 * happens in case there was no CLASS_IDLE entity to
-+		 * serve for sd when bfq_lookup_next_entity(sd) was
-+		 * invoked for the last time, while there is now one
-+		 * such entity.
-+		 *
-+		 * If the above event happens, then the scheduling of
-+		 * such entity in CLASS_IDLE is postponed until the
-+		 * service of the sd->next_in_service entity
-+		 * finishes. In fact, when the latter is expired,
-+		 * bfq_lookup_next_entity(sd) gets called again,
-+		 * exactly to update sd->next_in_service.
-+		 */
-+
-+		/* Make next_in_service entity become in_service_entity */
-+		entity = sd->next_in_service;
-+		sd->in_service_entity = entity;
-+
-+		/*
-+		 * If entity is no longer a candidate for next
-+		 * service, then it must be extracted from its active
-+		 * tree, so as to make sure that it won't be
-+		 * considered when computing next_in_service. See the
-+		 * comments on the function
-+		 * bfq_no_longer_next_in_service() for details.
-+		 */
-+		if (bfq_no_longer_next_in_service(entity))
-+			bfq_active_extract(bfq_entity_service_tree(entity),
-+					   entity);
-+
-+		/*
-+		 * Even if entity is not to be extracted according to
-+		 * the above check, a descendant entity may get
-+		 * extracted in one of the next iterations of this
-+		 * loop. Such an event could cause a change in
-+		 * next_in_service for the level of the descendant
-+		 * entity, and thus possibly back to this level.
-+		 *
-+		 * However, we cannot perform the resulting needed
-+		 * update of next_in_service for this level before the
-+		 * end of the whole loop, because, to know which is
-+		 * the correct next-to-serve candidate entity for each
-+		 * level, we need first to find the leaf entity to set
-+		 * in service. In fact, only after we know which is
-+		 * the next-to-serve leaf entity, we can discover
-+		 * whether the parent entity of the leaf entity
-+		 * becomes the next-to-serve, and so on.
-+		 */
-+
-+		/* Log some information */
-+		bfqq = bfq_entity_to_bfqq(entity);
-+		if (bfqq)
-+			bfq_log_bfqq(bfqd, bfqq,
-+			     "this queue, finish %llu",
-+				(((entity->finish>>10)*1000)>>10)>>2);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+		else {
-+			struct bfq_group *bfqg =
-+				container_of(entity, struct bfq_group, entity);
-+
-+			bfq_log_bfqg(bfqd, bfqg,
-+			     "this entity, finish %llu",
-+				(((entity->finish>>10)*1000)>>10)>>2);
-+		}
-+#endif
-+
-+	}
-+
-+	BUG_ON(!entity);
-+	bfqq = bfq_entity_to_bfqq(entity);
-+	BUG_ON(!bfqq);
-+
-+	/*
-+	 * We can finally update all next-to-serve entities along the
-+	 * path from the leaf entity just set in service to the root.
-+	 */
-+	for_each_entity(entity) {
-+		struct bfq_sched_data *sd = entity->sched_data;
-+
-+		if (!bfq_update_next_in_service(sd, NULL, false))
-+			break;
-+	}
-+
-+	return bfqq;
-+}
-+
-+static void __bfq_bfqd_reset_in_service(struct bfq_data *bfqd)
-+{
-+	struct bfq_queue *in_serv_bfqq = bfqd->in_service_queue;
-+	struct bfq_entity *in_serv_entity = &in_serv_bfqq->entity;
-+	struct bfq_entity *entity = in_serv_entity;
-+
-+#ifndef BFQ_MQ
-+	if (bfqd->in_service_bic) {
-+		put_io_context(bfqd->in_service_bic->icq.ioc);
-+		bfqd->in_service_bic = NULL;
-+	}
-+#endif
-+
-+	bfq_clear_bfqq_wait_request(in_serv_bfqq);
-+	hrtimer_try_to_cancel(&bfqd->idle_slice_timer);
-+	bfqd->in_service_queue = NULL;
-+
-+	/*
-+	 * When this function is called, all in-service entities have
-+	 * been properly deactivated or requeued, so we can safely
-+	 * execute the final step: reset in_service_entity along the
-+	 * path from entity to the root.
-+	 */
-+	for_each_entity(entity)
-+		entity->sched_data->in_service_entity = NULL;
-+
-+	/*
-+	 * in_serv_entity is no longer in service, so, if it is in no
-+	 * service tree either, then release the service reference to
-+	 * the queue it represents (taken with bfq_get_entity).
-+	 */
-+	if (!in_serv_entity->on_st)
-+		bfq_put_queue(in_serv_bfqq);
-+}
-+
-+static void bfq_deactivate_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+				bool ins_into_idle_tree, bool expiration)
-+{
-+	struct bfq_entity *entity = &bfqq->entity;
-+
-+	bfq_deactivate_entity(entity, ins_into_idle_tree, expiration);
-+}
-+
-+static void bfq_activate_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	struct bfq_entity *entity = &bfqq->entity;
-+	struct bfq_service_tree *st = bfq_entity_service_tree(entity);
-+
-+	BUG_ON(bfqq == bfqd->in_service_queue);
-+	BUG_ON(entity->tree != &st->active && entity->tree != &st->idle &&
-+	       entity->on_st);
-+
-+	bfq_activate_requeue_entity(entity, bfq_bfqq_non_blocking_wait_rq(bfqq),
-+				    false, false);
-+	bfq_clear_bfqq_non_blocking_wait_rq(bfqq);
-+}
-+
-+static void bfq_requeue_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+			     bool expiration)
-+{
-+	struct bfq_entity *entity = &bfqq->entity;
-+
-+	bfq_activate_requeue_entity(entity, false,
-+				    bfqq == bfqd->in_service_queue, expiration);
-+}
-+
-+static void bfqg_stats_update_dequeue(struct bfq_group *bfqg);
-+
-+/*
-+ * Called when the bfqq no longer has requests pending, remove it from
-+ * the service tree. As a special case, it can be invoked during an
-+ * expiration.
-+ */
-+static void bfq_del_bfqq_busy(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+			      bool expiration)
-+{
-+	BUG_ON(!bfq_bfqq_busy(bfqq));
-+	BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list));
-+
-+	bfq_log_bfqq(bfqd, bfqq, "del from busy");
-+
-+	bfq_clear_bfqq_busy(bfqq);
-+
-+	BUG_ON(bfqd->busy_queues == 0);
-+	bfqd->busy_queues--;
-+
-+	if (!bfqq->dispatched)
-+		bfq_weights_tree_remove(bfqd, bfqq);
-+
-+	if (bfqq->wr_coeff > 1) {
-+		bfqd->wr_busy_queues--;
-+		BUG_ON(bfqd->wr_busy_queues < 0);
-+	}
-+
-+	bfqg_stats_update_dequeue(bfqq_group(bfqq));
-+
-+	BUG_ON(bfqq->entity.budget < 0);
-+
-+	bfq_deactivate_bfqq(bfqd, bfqq, true, expiration);
-+}
-+
-+/*
-+ * Called when an inactive queue receives a new request.
-+ */
-+static void bfq_add_bfqq_busy(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	BUG_ON(bfq_bfqq_busy(bfqq));
-+	BUG_ON(bfqq == bfqd->in_service_queue);
-+
-+	bfq_log_bfqq(bfqd, bfqq, "add to busy");
-+
-+	bfq_activate_bfqq(bfqd, bfqq);
-+
-+	bfq_mark_bfqq_busy(bfqq);
-+	bfqd->busy_queues++;
-+
-+	if (!bfqq->dispatched)
-+		if (bfqq->wr_coeff == 1)
-+			bfq_weights_tree_add(bfqd, &bfqq->entity,
-+					     &bfqd->queue_weights_tree);
-+
-+	if (bfqq->wr_coeff > 1) {
-+		bfqd->wr_busy_queues++;
-+		BUG_ON(bfqd->wr_busy_queues > bfqd->busy_queues);
-+	}
-+
-+}
-diff --git a/block/bfq-sq-iosched.c b/block/bfq-sq-iosched.c
-new file mode 100644
-index 000000000000..bf8a44b30bbd
---- /dev/null
-+++ b/block/bfq-sq-iosched.c
-@@ -0,0 +1,5769 @@
-+/*
-+ * Budget Fair Queueing (BFQ) I/O scheduler.
-+ *
-+ * Based on ideas and code from CFQ:
-+ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
-+ *
-+ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
-+ *		      Paolo Valente <paolo.valente@unimore.it>
-+ *
-+ * Copyright (C) 2015 Paolo Valente <paolo.valente@unimore.it>
-+ *
-+ * Copyright (C) 2017 Paolo Valente <paolo.valente@linaro.org>
-+ *
-+ * Licensed under the GPL-2 as detailed in the accompanying COPYING.BFQ
-+ * file.
-+ *
-+ * BFQ is a proportional-share I/O scheduler, with some extra
-+ * low-latency capabilities. BFQ also supports full hierarchical
-+ * scheduling through cgroups. Next paragraphs provide an introduction
-+ * on BFQ inner workings. Details on BFQ benefits and usage can be
-+ * found in Documentation/block/bfq-iosched.txt.
-+ *
-+ * BFQ is a proportional-share storage-I/O scheduling algorithm based
-+ * on the slice-by-slice service scheme of CFQ. But BFQ assigns
-+ * budgets, measured in number of sectors, to processes instead of
-+ * time slices. The device is not granted to the in-service process
-+ * for a given time slice, but until it has exhausted its assigned
-+ * budget. This change from the time to the service domain enables BFQ
-+ * to distribute the device throughput among processes as desired,
-+ * without any distortion due to throughput fluctuations, or to device
-+ * internal queueing. BFQ uses an ad hoc internal scheduler, called
-+ * B-WF2Q+, to schedule processes according to their budgets. More
-+ * precisely, BFQ schedules queues associated with processes. Thanks to
-+ * the accurate policy of B-WF2Q+, BFQ can afford to assign high
-+ * budgets to I/O-bound processes issuing sequential requests (to
-+ * boost the throughput), and yet guarantee a low latency to
-+ * interactive and soft real-time applications.
-+ *
-+ * In particular, BFQ schedules I/O so as to achieve the latter goal--
-+ * low latency for interactive and soft real-time applications--if the
-+ * low_latency parameter is set (default configuration). To this
-+ * purpose, BFQ constantly tries to detect whether the I/O requests in
-+ * a bfq_queue come from an interactive or a soft real-time
-+ * application. For brevity, in these cases, the queue is said to be
-+ * interactive or soft real-time. In both cases, BFQ privileges the
-+ * service of the queue, over that of non-interactive and
-+ * non-soft-real-time queues. This privileging is performed, mainly,
-+ * by raising the weight of the queue. So, for brevity, we call just
-+ * weight-raising periods the time periods during which a queue is
-+ * privileged, because deemed interactive or soft real-time.
-+ *
-+ * The detection of soft real-time queues/applications is described in
-+ * detail in the comments on the function
-+ * bfq_bfqq_softrt_next_start. On the other hand, the detection of an
-+ * interactive queue works as follows: a queue is deemed interactive
-+ * if it is constantly non empty only for a limited time interval,
-+ * after which it does become empty. The queue may be deemed
-+ * interactive again (for a limited time), if it restarts being
-+ * constantly non empty, provided that this happens only after the
-+ * queue has remained empty for a given minimum idle time.
-+ *
-+ * By default, BFQ computes automatically the above maximum time
-+ * interval, i.e., the time interval after which a constantly
-+ * non-empty queue stops being deemed interactive. Since a queue is
-+ * weight-raised while it is deemed interactive, this maximum time
-+ * interval happens to coincide with the (maximum) duration of the
-+ * weight-raising for interactive queues.
-+ *
-+ * NOTE: if the main or only goal, with a given device, is to achieve
-+ * the maximum-possible throughput at all times, then do switch off
-+ * all low-latency heuristics for that device, by setting low_latency
-+ * to 0.
-+ *
-+ * BFQ is described in [1], where also a reference to the initial,
-+ * more theoretical paper on BFQ can be found. The interested reader
-+ * can find in the latter paper full details on the main algorithm, as
-+ * well as formulas of the guarantees and formal proofs of all the
-+ * properties.  With respect to the version of BFQ presented in these
-+ * papers, this implementation adds a few more heuristics, such as the
-+ * one that guarantees a low latency to soft real-time applications,
-+ * and a hierarchical extension based on H-WF2Q+.
-+ *
-+ * B-WF2Q+ is based on WF2Q+, that is described in [2], together with
-+ * H-WF2Q+, while the augmented tree used to implement B-WF2Q+ with O(log N)
-+ * complexity derives from the one introduced with EEVDF in [3].
-+ *
-+ * [1] P. Valente, A. Avanzini, "Evolution of the BFQ Storage I/O
-+ *   Scheduler", Proceedings of the First Workshop on Mobile System
-+ *   Technologies (MST-2015), May 2015.
-+ *   http://algogroup.unimore.it/people/paolo/disk_sched/mst-2015.pdf
-+ *
-+ * http://algogroup.unimo.it/people/paolo/disk_sched/bf1-v1-suite-results.pdf
-+ *
-+ * [2] Jon C.R. Bennett and H. Zhang, ``Hierarchical Packet Fair Queueing
-+ *     Algorithms,'' IEEE/ACM Transactions on Networking, 5(5):675-689,
-+ *     Oct 1997.
-+ *
-+ * http://www.cs.cmu.edu/~hzhang/papers/TON-97-Oct.ps.gz
-+ *
-+ * [3] I. Stoica and H. Abdel-Wahab, ``Earliest Eligible Virtual Deadline
-+ *     First: A Flexible and Accurate Mechanism for Proportional Share
-+ *     Resource Allocation,'' technical report.
-+ *
-+ * http://www.cs.berkeley.edu/~istoica/papers/eevdf-tr-95.pdf
-+ */
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/blkdev.h>
-+#include <linux/cgroup.h>
-+#include <linux/elevator.h>
-+#include <linux/jiffies.h>
-+#include <linux/rbtree.h>
-+#include <linux/ioprio.h>
-+#include "blk.h"
-+#include "bfq.h"
-+#include "blk-wbt.h"
-+
-+/* Expiration time of sync (0) and async (1) requests, in ns. */
-+static const u64 bfq_fifo_expire[2] = { NSEC_PER_SEC / 4, NSEC_PER_SEC / 8 };
-+
-+/* Maximum backwards seek, in KiB. */
-+static const int bfq_back_max = (16 * 1024);
-+
-+/* Penalty of a backwards seek, in number of sectors. */
-+static const int bfq_back_penalty = 2;
-+
-+/* Idling period duration, in ns. */
-+static u32 bfq_slice_idle = (NSEC_PER_SEC / 125);
-+
-+/* Minimum number of assigned budgets for which stats are safe to compute. */
-+static const int bfq_stats_min_budgets = 194;
-+
-+/* Default maximum budget values, in sectors and number of requests. */
-+static const int bfq_default_max_budget = (16 * 1024);
-+
-+/*
-+ * When a sync request is dispatched, the queue that contains that
-+ * request, and all the ancestor entities of that queue, are charged
-+ * with the number of sectors of the request. In constrast, if the
-+ * request is async, then the queue and its ancestor entities are
-+ * charged with the number of sectors of the request, multiplied by
-+ * the factor below. This throttles the bandwidth for async I/O,
-+ * w.r.t. to sync I/O, and it is done to counter the tendency of async
-+ * writes to steal I/O throughput to reads.
-+ *
-+ * The current value of this parameter is the result of a tuning with
-+ * several hardware and software configurations. We tried to find the
-+ * lowest value for which writes do not cause noticeable problems to
-+ * reads. In fact, the lower this parameter, the stabler I/O control,
-+ * in the following respect.  The lower this parameter is, the less
-+ * the bandwidth enjoyed by a group decreases
-+ * - when the group does writes, w.r.t. to when it does reads;
-+ * - when other groups do reads, w.r.t. to when they do writes.
-+ */
-+static const int bfq_async_charge_factor = 3;
-+
-+/* Default timeout values, in jiffies, approximating CFQ defaults. */
-+static const int bfq_timeout = (HZ / 8);
-+
-+/*
-+ * Time limit for merging (see comments in bfq_setup_cooperator). Set
-+ * to the slowest value that, in our tests, proved to be effective in
-+ * removing false positives, while not causing true positives to miss
-+ * queue merging.
-+ *
-+ * As can be deduced from the low time limit below, queue merging, if
-+ * successful, happens at the very beggining of the I/O of the involved
-+ * cooperating processes, as a consequence of the arrival of the very
-+ * first requests from each cooperator.  After that, there is very
-+ * little chance to find cooperators.
-+ */
-+static const unsigned long bfq_merge_time_limit = HZ/10;
-+
-+#define MAX_LENGTH_REASON_NAME 25
-+
-+static const char reason_name[][MAX_LENGTH_REASON_NAME] = {"TOO_IDLE",
-+"BUDGET_TIMEOUT", "BUDGET_EXHAUSTED", "NO_MORE_REQUESTS",
-+"PREEMPTED"};
-+
-+static struct kmem_cache *bfq_pool;
-+
-+/* Below this threshold (in ns), we consider thinktime immediate. */
-+#define BFQ_MIN_TT		(2 * NSEC_PER_MSEC)
-+
-+/* hw_tag detection: parallel requests threshold and min samples needed. */
-+#define BFQ_HW_QUEUE_THRESHOLD	4
-+#define BFQ_HW_QUEUE_SAMPLES	32
-+
-+#define BFQQ_SEEK_THR		(sector_t)(8 * 100)
-+#define BFQQ_SECT_THR_NONROT	(sector_t)(2 * 32)
-+#define BFQQ_CLOSE_THR		(sector_t)(8 * 1024)
-+#define BFQQ_SEEKY(bfqq)	(hweight32(bfqq->seek_history) > 19)
-+
-+/* Min number of samples required to perform peak-rate update */
-+#define BFQ_RATE_MIN_SAMPLES	32
-+/* Min observation time interval required to perform a peak-rate update (ns) */
-+#define BFQ_RATE_MIN_INTERVAL	(300*NSEC_PER_MSEC)
-+/* Target observation time interval for a peak-rate update (ns) */
-+#define BFQ_RATE_REF_INTERVAL	NSEC_PER_SEC
-+
-+/*
-+ * Shift used for peak-rate fixed precision calculations.
-+ * With
-+ * - the current shift: 16 positions
-+ * - the current type used to store rate: u32
-+ * - the current unit of measure for rate: [sectors/usec], or, more precisely,
-+ *   [(sectors/usec) / 2^BFQ_RATE_SHIFT] to take into account the shift,
-+ * the range of rates that can be stored is
-+ * [1 / 2^BFQ_RATE_SHIFT, 2^(32 - BFQ_RATE_SHIFT)] sectors/usec =
-+ * [1 / 2^16, 2^16] sectors/usec = [15e-6, 65536] sectors/usec =
-+ * [15, 65G] sectors/sec
-+ * Which, assuming a sector size of 512B, corresponds to a range of
-+ * [7.5K, 33T] B/sec
-+ */
-+#define BFQ_RATE_SHIFT		16
-+
-+/*
-+ * When configured for computing the duration of the weight-raising
-+ * for interactive queues automatically (see the comments at the
-+ * beginning of this file), BFQ does it using the following formula:
-+ * duration = (ref_rate / r) * ref_wr_duration,
-+ * where r is the peak rate of the device, and ref_rate and
-+ * ref_wr_duration are two reference parameters.  In particular,
-+ * ref_rate is the peak rate of the reference storage device (see
-+ * below), and ref_wr_duration is about the maximum time needed, with
-+ * BFQ and while reading two files in parallel, to load typical large
-+ * applications on the reference device (see the comments on
-+ * max_service_from_wr below, for more details on how ref_wr_duration
-+ * is obtained).  In practice, the slower/faster the device at hand
-+ * is, the more/less it takes to load applications with respect to the
-+ * reference device.  Accordingly, the longer/shorter BFQ grants
-+ * weight raising to interactive applications.
-+ *
-+ * BFQ uses two different reference pairs (ref_rate, ref_wr_duration),
-+ * depending on whether the device is rotational or non-rotational.
-+ *
-+ * In the following definitions, ref_rate[0] and ref_wr_duration[0]
-+ * are the reference values for a rotational device, whereas
-+ * ref_rate[1] and ref_wr_duration[1] are the reference values for a
-+ * non-rotational device. The reference rates are not the actual peak
-+ * rates of the devices used as a reference, but slightly lower
-+ * values. The reason for using slightly lower values is that the
-+ * peak-rate estimator tends to yield slightly lower values than the
-+ * actual peak rate (it can yield the actual peak rate only if there
-+ * is only one process doing I/O, and the process does sequential
-+ * I/O).
-+ *
-+ * The reference peak rates are measured in sectors/usec, left-shifted
-+ * by BFQ_RATE_SHIFT.
-+ */
-+static int ref_rate[2] = {14000, 33000};
-+/*
-+ * To improve readability, a conversion function is used to initialize
-+ * the following array, which entails that the array can be
-+ * initialized only in a function.
-+ */
-+static int ref_wr_duration[2];
-+
-+/*
-+ * BFQ uses the above-detailed, time-based weight-raising mechanism to
-+ * privilege interactive tasks. This mechanism is vulnerable to the
-+ * following false positives: I/O-bound applications that will go on
-+ * doing I/O for much longer than the duration of weight
-+ * raising. These applications have basically no benefit from being
-+ * weight-raised at the beginning of their I/O. On the opposite end,
-+ * while being weight-raised, these applications
-+ * a) unjustly steal throughput to applications that may actually need
-+ * low latency;
-+ * b) make BFQ uselessly perform device idling; device idling results
-+ * in loss of device throughput with most flash-based storage, and may
-+ * increase latencies when used purposelessly.
-+ *
-+ * BFQ tries to reduce these problems, by adopting the following
-+ * countermeasure. To introduce this countermeasure, we need first to
-+ * finish explaining how the duration of weight-raising for
-+ * interactive tasks is computed.
-+ *
-+ * For a bfq_queue deemed as interactive, the duration of weight
-+ * raising is dynamically adjusted, as a function of the estimated
-+ * peak rate of the device, so as to be equal to the time needed to
-+ * execute the 'largest' interactive task we benchmarked so far. By
-+ * largest task, we mean the task for which each involved process has
-+ * to do more I/O than for any of the other tasks we benchmarked. This
-+ * reference interactive task is the start-up of LibreOffice Writer,
-+ * and in this task each process/bfq_queue needs to have at most ~110K
-+ * sectors transfered.
-+ *
-+ * This last piece of information enables BFQ to reduce the actual
-+ * duration of weight-raising for at least one class of I/O-bound
-+ * applications: those doing sequential or quasi-sequential I/O. An
-+ * example is file copy. In fact, once started, the main I/O-bound
-+ * processes of these applications usually consume the above 110K
-+ * sectors in much less time than the processes of an application that
-+ * is starting, because these I/O-bound processes will greedily devote
-+ * almost all their CPU cycles only to their target,
-+ * throughput-friendly I/O operations. This is even more true if BFQ
-+ * happens to be underestimating the device peak rate, and thus
-+ * overestimating the duration of weight raising. But, according to
-+ * our measurements, once transferred 110K sectors, these processes
-+ * have no right to be weight-raised any longer.
-+ *
-+ * Basing on the last consideration, BFQ ends weight-raising for a
-+ * bfq_queue if the latter happens to have received an amount of
-+ * service at least equal to the following constant. The constant is
-+ * set to slightly more than 110K, to have a minimum safety margin.
-+ *
-+ * This early ending of weight-raising reduces the amount of time
-+ * during which interactive false positives cause the two problems
-+ * described at the beginning of these comments.
-+ */
-+static const unsigned long max_service_from_wr = 120000;
-+
-+#define BFQ_SERVICE_TREE_INIT	((struct bfq_service_tree)		\
-+				{ RB_ROOT, RB_ROOT, NULL, NULL, 0, 0 })
-+
-+#define RQ_BIC(rq)		icq_to_bic((rq)->elv.priv[0])
-+#define RQ_BFQQ(rq)		((rq)->elv.priv[1])
-+
-+static void bfq_schedule_dispatch(struct bfq_data *bfqd);
-+
-+#include "bfq-ioc.c"
-+#include "bfq-sched.c"
-+#include "bfq-cgroup-included.c"
-+
-+#define bfq_class_idle(bfqq)	((bfqq)->ioprio_class == IOPRIO_CLASS_IDLE)
-+#define bfq_class_rt(bfqq)	((bfqq)->ioprio_class == IOPRIO_CLASS_RT)
-+
-+#define bfq_sample_valid(samples)	((samples) > 80)
-+
-+/*
-+ * Scheduler run of queue, if there are requests pending and no one in the
-+ * driver that will restart queueing.
-+ */
-+static void bfq_schedule_dispatch(struct bfq_data *bfqd)
-+{
-+	if (bfqd->queued != 0) {
-+		bfq_log(bfqd, "");
-+		kblockd_schedule_work(&bfqd->unplug_work);
-+	}
-+}
-+
-+/*
-+ * Lifted from AS - choose which of rq1 and rq2 that is best served now.
-+ * We choose the request that is closesr to the head right now.  Distance
-+ * behind the head is penalized and only allowed to a certain extent.
-+ */
-+static struct request *bfq_choose_req(struct bfq_data *bfqd,
-+				      struct request *rq1,
-+				      struct request *rq2,
-+				      sector_t last)
-+{
-+	sector_t s1, s2, d1 = 0, d2 = 0;
-+	unsigned long back_max;
-+#define BFQ_RQ1_WRAP	0x01 /* request 1 wraps */
-+#define BFQ_RQ2_WRAP	0x02 /* request 2 wraps */
-+	unsigned int wrap = 0; /* bit mask: requests behind the disk head? */
-+
-+	if (!rq1 || rq1 == rq2)
-+		return rq2;
-+	if (!rq2)
-+		return rq1;
-+
-+	if (rq_is_sync(rq1) && !rq_is_sync(rq2))
-+		return rq1;
-+	else if (rq_is_sync(rq2) && !rq_is_sync(rq1))
-+		return rq2;
-+	if ((rq1->cmd_flags & REQ_META) && !(rq2->cmd_flags & REQ_META))
-+		return rq1;
-+	else if ((rq2->cmd_flags & REQ_META) && !(rq1->cmd_flags & REQ_META))
-+		return rq2;
-+
-+	s1 = blk_rq_pos(rq1);
-+	s2 = blk_rq_pos(rq2);
-+
-+	/*
-+	 * By definition, 1KiB is 2 sectors.
-+	 */
-+	back_max = bfqd->bfq_back_max * 2;
-+
-+	/*
-+	 * Strict one way elevator _except_ in the case where we allow
-+	 * short backward seeks which are biased as twice the cost of a
-+	 * similar forward seek.
-+	 */
-+	if (s1 >= last)
-+		d1 = s1 - last;
-+	else if (s1 + back_max >= last)
-+		d1 = (last - s1) * bfqd->bfq_back_penalty;
-+	else
-+		wrap |= BFQ_RQ1_WRAP;
-+
-+	if (s2 >= last)
-+		d2 = s2 - last;
-+	else if (s2 + back_max >= last)
-+		d2 = (last - s2) * bfqd->bfq_back_penalty;
-+	else
-+		wrap |= BFQ_RQ2_WRAP;
-+
-+	/* Found required data */
-+
-+	/*
-+	 * By doing switch() on the bit mask "wrap" we avoid having to
-+	 * check two variables for all permutations: --> faster!
-+	 */
-+	switch (wrap) {
-+	case 0: /* common case for CFQ: rq1 and rq2 not wrapped */
-+		if (d1 < d2)
-+			return rq1;
-+		else if (d2 < d1)
-+			return rq2;
-+
-+		if (s1 >= s2)
-+			return rq1;
-+		else
-+			return rq2;
-+
-+	case BFQ_RQ2_WRAP:
-+		return rq1;
-+	case BFQ_RQ1_WRAP:
-+		return rq2;
-+	case (BFQ_RQ1_WRAP|BFQ_RQ2_WRAP): /* both rqs wrapped */
-+	default:
-+		/*
-+		 * Since both rqs are wrapped,
-+		 * start with the one that's further behind head
-+		 * (--> only *one* back seek required),
-+		 * since back seek takes more time than forward.
-+		 */
-+		if (s1 <= s2)
-+			return rq1;
-+		else
-+			return rq2;
-+	}
-+}
-+
-+static struct bfq_queue *
-+bfq_rq_pos_tree_lookup(struct bfq_data *bfqd, struct rb_root *root,
-+		     sector_t sector, struct rb_node **ret_parent,
-+		     struct rb_node ***rb_link)
-+{
-+	struct rb_node **p, *parent;
-+	struct bfq_queue *bfqq = NULL;
-+
-+	parent = NULL;
-+	p = &root->rb_node;
-+	while (*p) {
-+		struct rb_node **n;
-+
-+		parent = *p;
-+		bfqq = rb_entry(parent, struct bfq_queue, pos_node);
-+
-+		/*
-+		 * Sort strictly based on sector. Smallest to the left,
-+		 * largest to the right.
-+		 */
-+		if (sector > blk_rq_pos(bfqq->next_rq))
-+			n = &(*p)->rb_right;
-+		else if (sector < blk_rq_pos(bfqq->next_rq))
-+			n = &(*p)->rb_left;
-+		else
-+			break;
-+		p = n;
-+		bfqq = NULL;
-+	}
-+
-+	*ret_parent = parent;
-+	if (rb_link)
-+		*rb_link = p;
-+
-+	bfq_log(bfqd, "%llu: returning %d",
-+		(unsigned long long) sector,
-+		bfqq ? bfqq->pid : 0);
-+
-+	return bfqq;
-+}
-+
-+static bool bfq_too_late_for_merging(struct bfq_queue *bfqq)
-+{
-+	return bfqq->service_from_backlogged > 0 &&
-+		time_is_before_jiffies(bfqq->first_IO_time +
-+				       bfq_merge_time_limit);
-+}
-+
-+static void bfq_pos_tree_add_move(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	struct rb_node **p, *parent;
-+	struct bfq_queue *__bfqq;
-+
-+	if (bfqq->pos_root) {
-+		rb_erase(&bfqq->pos_node, bfqq->pos_root);
-+		bfqq->pos_root = NULL;
-+	}
-+
-+	/*
-+	 * bfqq cannot be merged any longer (see comments in
-+	 * bfq_setup_cooperator): no point in adding bfqq into the
-+	 * position tree.
-+	 */
-+	if (bfq_too_late_for_merging(bfqq))
-+		return;
-+
-+	if (bfq_class_idle(bfqq))
-+		return;
-+	if (!bfqq->next_rq)
-+		return;
-+
-+	bfqq->pos_root = &bfq_bfqq_to_bfqg(bfqq)->rq_pos_tree;
-+	__bfqq = bfq_rq_pos_tree_lookup(bfqd, bfqq->pos_root,
-+			blk_rq_pos(bfqq->next_rq), &parent, &p);
-+	if (!__bfqq) {
-+		rb_link_node(&bfqq->pos_node, parent, p);
-+		rb_insert_color(&bfqq->pos_node, bfqq->pos_root);
-+	} else
-+		bfqq->pos_root = NULL;
-+}
-+
-+/*
-+ * Tell whether there are active queues or groups with differentiated weights.
-+ */
-+static bool bfq_differentiated_weights(struct bfq_data *bfqd)
-+{
-+	/*
-+	 * For weights to differ, at least one of the trees must contain
-+	 * at least two nodes.
-+	 */
-+	return (!RB_EMPTY_ROOT(&bfqd->queue_weights_tree) &&
-+		(bfqd->queue_weights_tree.rb_node->rb_left ||
-+		 bfqd->queue_weights_tree.rb_node->rb_right)
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	       ) ||
-+	       (!RB_EMPTY_ROOT(&bfqd->group_weights_tree) &&
-+		(bfqd->group_weights_tree.rb_node->rb_left ||
-+		 bfqd->group_weights_tree.rb_node->rb_right)
-+#endif
-+	       );
-+}
-+
-+/*
-+ * The following function returns true if every queue must receive the
-+ * same share of the throughput (this condition is used when deciding
-+ * whether idling may be disabled, see the comments in the function
-+ * bfq_better_to_idle()).
-+ *
-+ * Such a scenario occurs when:
-+ * 1) all active queues have the same weight,
-+ * 2) all active groups at the same level in the groups tree have the same
-+ *    weight,
-+ * 3) all active groups at the same level in the groups tree have the same
-+ *    number of children.
-+ *
-+ * Unfortunately, keeping the necessary state for evaluating exactly the
-+ * above symmetry conditions would be quite complex and time-consuming.
-+ * Therefore this function evaluates, instead, the following stronger
-+ * sub-conditions, for which it is much easier to maintain the needed
-+ * state:
-+ * 1) all active queues have the same weight,
-+ * 2) all active groups have the same weight,
-+ * 3) all active groups have at most one active child each.
-+ * In particular, the last two conditions are always true if hierarchical
-+ * support and the cgroups interface are not enabled, thus no state needs
-+ * to be maintained in this case.
-+ */
-+static bool bfq_symmetric_scenario(struct bfq_data *bfqd)
-+{
-+	return !bfq_differentiated_weights(bfqd);
-+}
-+
-+/*
-+ * If the weight-counter tree passed as input contains no counter for
-+ * the weight of the input entity, then add that counter; otherwise just
-+ * increment the existing counter.
-+ *
-+ * Note that weight-counter trees contain few nodes in mostly symmetric
-+ * scenarios. For example, if all queues have the same weight, then the
-+ * weight-counter tree for the queues may contain at most one node.
-+ * This holds even if low_latency is on, because weight-raised queues
-+ * are not inserted in the tree.
-+ * In most scenarios, the rate at which nodes are created/destroyed
-+ * should be low too.
-+ */
-+static void bfq_weights_tree_add(struct bfq_data *bfqd,
-+				 struct bfq_entity *entity,
-+				 struct rb_root *root)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+	struct rb_node **new = &(root->rb_node), *parent = NULL;
-+
-+	/*
-+	 * Do not insert if the entity is already associated with a
-+	 * counter, which happens if:
-+	 *   1) the entity is associated with a queue,
-+	 *   2) a request arrival has caused the queue to become both
-+	 *      non-weight-raised, and hence change its weight, and
-+	 *      backlogged; in this respect, each of the two events
-+	 *      causes an invocation of this function,
-+	 *   3) this is the invocation of this function caused by the
-+	 *      second event. This second invocation is actually useless,
-+	 *      and we handle this fact by exiting immediately. More
-+	 *      efficient or clearer solutions might possibly be adopted.
-+	 */
-+	if (entity->weight_counter)
-+		return;
-+
-+	while (*new) {
-+		struct bfq_weight_counter *__counter = container_of(*new,
-+						struct bfq_weight_counter,
-+						weights_node);
-+		parent = *new;
-+
-+		if (entity->weight == __counter->weight) {
-+			entity->weight_counter = __counter;
-+			goto inc_counter;
-+		}
-+		if (entity->weight < __counter->weight)
-+			new = &((*new)->rb_left);
-+		else
-+			new = &((*new)->rb_right);
-+	}
-+
-+	entity->weight_counter = kzalloc(sizeof(struct bfq_weight_counter),
-+					 GFP_ATOMIC);
-+
-+	/*
-+	 * In the unlucky event of an allocation failure, we just
-+	 * exit. This will cause the weight of entity to not be
-+	 * considered in bfq_differentiated_weights, which, in its
-+	 * turn, causes the scenario to be deemed wrongly symmetric in
-+	 * case entity's weight would have been the only weight making
-+	 * the scenario asymmetric. On the bright side, no unbalance
-+	 * will however occur when entity becomes inactive again (the
-+	 * invocation of this function is triggered by an activation
-+	 * of entity). In fact, bfq_weights_tree_remove does nothing
-+	 * if !entity->weight_counter.
-+	 */
-+	if (unlikely(!entity->weight_counter))
-+		return;
-+
-+	entity->weight_counter->weight = entity->weight;
-+	rb_link_node(&entity->weight_counter->weights_node, parent, new);
-+	rb_insert_color(&entity->weight_counter->weights_node, root);
-+
-+inc_counter:
-+	entity->weight_counter->num_active++;
-+
-+	if (bfqq) {
-+		bfq_log_bfqq(bfqq->bfqd, bfqq, "[%s] weight %d symmetric %d",
-+			     __func__, entity->weight,
-+			     bfq_symmetric_scenario(bfqd));
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	} else {
-+		struct bfq_group *bfqg =
-+			container_of(entity, struct bfq_group, entity);
-+
-+		bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+			     "[%s] weight %d symmetric %d",
-+			     __func__, entity->weight,
-+			     bfq_symmetric_scenario(bfqd));
-+#endif
-+	}
-+}
-+
-+/*
-+ * Decrement the weight counter associated with the entity, and, if the
-+ * counter reaches 0, remove the counter from the tree.
-+ * See the comments to the function bfq_weights_tree_add() for considerations
-+ * about overhead.
-+ */
-+static void __bfq_weights_tree_remove(struct bfq_data *bfqd,
-+				      struct bfq_entity *entity,
-+				      struct rb_root *root)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+
-+	if (!entity->weight_counter)
-+		return;
-+
-+	BUG_ON(RB_EMPTY_ROOT(root));
-+	BUG_ON(entity->weight_counter->weight != entity->weight);
-+
-+	BUG_ON(!entity->weight_counter->num_active);
-+	entity->weight_counter->num_active--;
-+
-+	if (entity->weight_counter->num_active > 0)
-+		goto reset_entity_pointer;
-+
-+	rb_erase(&entity->weight_counter->weights_node, root);
-+	kfree(entity->weight_counter);
-+
-+reset_entity_pointer:
-+	entity->weight_counter = NULL;
-+	if (bfqq) {
-+		bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			     "[%s] weight %d symmetric %d",
-+			     __func__, entity->weight,
-+			     bfq_symmetric_scenario(bfqd));
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	} else {
-+		struct bfq_group *bfqg =
-+			container_of(entity, struct bfq_group, entity);
-+
-+		bfq_log_bfqg(bfqd, bfqg,
-+			     "[%s] weight %d symmetric %d",
-+			     __func__, entity->weight,
-+			     bfq_symmetric_scenario(bfqd));
-+#endif
-+	}
-+}
-+
-+/*
-+ * Invoke __bfq_weights_tree_remove on bfqq and all its inactive
-+ * parent entities.
-+ */
-+static void bfq_weights_tree_remove(struct bfq_data *bfqd,
-+				    struct bfq_queue *bfqq)
-+{
-+	struct bfq_entity *entity = bfqq->entity.parent;
-+
-+	__bfq_weights_tree_remove(bfqd, &bfqq->entity,
-+				  &bfqd->queue_weights_tree);
-+
-+	for_each_entity(entity) {
-+		struct bfq_sched_data *sd = entity->my_sched_data;
-+
-+		BUG_ON(entity->sched_data == NULL); /*
-+						     * It would mean
-+						     * that this is
-+						     * the root group.
-+						     */
-+
-+		if (sd->next_in_service || sd->in_service_entity) {
-+			/*
-+			 * entity is still active, because either
-+			 * next_in_service or in_service_entity is not
-+			 * NULL (see the comments on the definition of
-+			 * next_in_service for details on why
-+			 * in_service_entity must be checked too).
-+			 *
-+			 * As a consequence, the weight of entity is
-+			 * not to be removed. In addition, if entity
-+			 * is active, then its parent entities are
-+			 * active as well, and thus their weights are
-+			 * not to be removed either. In the end, this
-+			 * loop must stop here.
-+			 */
-+			break;
-+		}
-+		__bfq_weights_tree_remove(bfqd, entity,
-+					  &bfqd->group_weights_tree);
-+	}
-+}
-+
-+/*
-+ * Return expired entry, or NULL to just start from scratch in rbtree.
-+ */
-+static struct request *bfq_check_fifo(struct bfq_queue *bfqq,
-+				      struct request *last)
-+{
-+	struct request *rq;
-+
-+	if (bfq_bfqq_fifo_expire(bfqq))
-+		return NULL;
-+
-+	bfq_mark_bfqq_fifo_expire(bfqq);
-+
-+	rq = rq_entry_fifo(bfqq->fifo.next);
-+
-+	if (rq == last || ktime_get_ns() < rq->fifo_time)
-+		return NULL;
-+
-+	bfq_log_bfqq(bfqq->bfqd, bfqq, "returned %p", rq);
-+	BUG_ON(RB_EMPTY_NODE(&rq->rb_node));
-+	return rq;
-+}
-+
-+static struct request *bfq_find_next_rq(struct bfq_data *bfqd,
-+					struct bfq_queue *bfqq,
-+					struct request *last)
-+{
-+	struct rb_node *rbnext = rb_next(&last->rb_node);
-+	struct rb_node *rbprev = rb_prev(&last->rb_node);
-+	struct request *next, *prev = NULL;
-+
-+	BUG_ON(list_empty(&bfqq->fifo));
-+
-+	/* Follow expired path, else get first next available. */
-+	next = bfq_check_fifo(bfqq, last);
-+	if (next) {
-+		BUG_ON(next == last);
-+		return next;
-+	}
-+
-+	BUG_ON(RB_EMPTY_NODE(&last->rb_node));
-+
-+	if (rbprev)
-+		prev = rb_entry_rq(rbprev);
-+
-+	if (rbnext)
-+		next = rb_entry_rq(rbnext);
-+	else {
-+		rbnext = rb_first(&bfqq->sort_list);
-+		if (rbnext && rbnext != &last->rb_node)
-+			next = rb_entry_rq(rbnext);
-+	}
-+
-+	return bfq_choose_req(bfqd, next, prev, blk_rq_pos(last));
-+}
-+
-+/* see the definition of bfq_async_charge_factor for details */
-+static unsigned long bfq_serv_to_charge(struct request *rq,
-+					struct bfq_queue *bfqq)
-+{
-+	if (bfq_bfqq_sync(bfqq) || bfqq->wr_coeff > 1)
-+		return blk_rq_sectors(rq);
-+
-+	return blk_rq_sectors(rq) * bfq_async_charge_factor;
-+}
-+
-+/**
-+ * bfq_updated_next_req - update the queue after a new next_rq selection.
-+ * @bfqd: the device data the queue belongs to.
-+ * @bfqq: the queue to update.
-+ *
-+ * If the first request of a queue changes we make sure that the queue
-+ * has enough budget to serve at least its first request (if the
-+ * request has grown).  We do this because if the queue has not enough
-+ * budget for its first request, it has to go through two dispatch
-+ * rounds to actually get it dispatched.
-+ */
-+static void bfq_updated_next_req(struct bfq_data *bfqd,
-+				 struct bfq_queue *bfqq)
-+{
-+	struct bfq_entity *entity = &bfqq->entity;
-+	struct bfq_service_tree *st = bfq_entity_service_tree(entity);
-+	struct request *next_rq = bfqq->next_rq;
-+	unsigned long new_budget;
-+
-+	if (!next_rq)
-+		return;
-+
-+	if (bfqq == bfqd->in_service_queue)
-+		/*
-+		 * In order not to break guarantees, budgets cannot be
-+		 * changed after an entity has been selected.
-+		 */
-+		return;
-+
-+	BUG_ON(entity->tree != &st->active);
-+	BUG_ON(entity == entity->sched_data->in_service_entity);
-+
-+	new_budget = max_t(unsigned long, bfqq->max_budget,
-+			   bfq_serv_to_charge(next_rq, bfqq));
-+	if (entity->budget != new_budget) {
-+		entity->budget = new_budget;
-+		bfq_log_bfqq(bfqd, bfqq, "new budget %lu",
-+					 new_budget);
-+		bfq_requeue_bfqq(bfqd, bfqq, false);
-+	}
-+}
-+
-+static unsigned int bfq_wr_duration(struct bfq_data *bfqd)
-+{
-+	u64 dur;
-+
-+	if (bfqd->bfq_wr_max_time > 0)
-+		return bfqd->bfq_wr_max_time;
-+
-+	dur = bfqd->rate_dur_prod;
-+	do_div(dur, bfqd->peak_rate);
-+
-+	/*
-+	 * Limit duration between 3 and 25 seconds. The upper limit
-+	 * has been conservatively set after the following worst case:
-+	 * on a QEMU/KVM virtual machine
-+	 * - running in a slow PC
-+	 * - with a virtual disk stacked on a slow low-end 5400rpm HDD
-+	 * - serving a heavy I/O workload, such as the sequential reading
-+	 *   of several files
-+	 * mplayer took 23 seconds to start, if constantly weight-raised.
-+	 *
-+	 * As for higher values than that accomodating the above bad
-+	 * scenario, tests show that higher values would often yield
-+	 * the opposite of the desired result, i.e., would worsen
-+	 * responsiveness by allowing non-interactive applications to
-+	 * preserve weight raising for too long.
-+	 *
-+	 * On the other end, lower values than 3 seconds make it
-+	 * difficult for most interactive tasks to complete their jobs
-+	 * before weight-raising finishes.
-+	 */
-+	return clamp_val(dur, msecs_to_jiffies(3000), msecs_to_jiffies(25000));
-+}
-+
-+/* switch back from soft real-time to interactive weight raising */
-+static void switch_back_to_interactive_wr(struct bfq_queue *bfqq,
-+					  struct bfq_data *bfqd)
-+{
-+	bfqq->wr_coeff = bfqd->bfq_wr_coeff;
-+	bfqq->wr_cur_max_time = bfq_wr_duration(bfqd);
-+	bfqq->last_wr_start_finish = bfqq->wr_start_at_switch_to_srt;
-+}
-+
-+static void
-+bfq_bfqq_resume_state(struct bfq_queue *bfqq, struct bfq_data *bfqd,
-+		      struct bfq_io_cq *bic, bool bfq_already_existing)
-+{
-+	unsigned int old_wr_coeff;
-+	bool busy = bfq_already_existing && bfq_bfqq_busy(bfqq);
-+
-+	if (bic->saved_has_short_ttime)
-+		bfq_mark_bfqq_has_short_ttime(bfqq);
-+	else
-+		bfq_clear_bfqq_has_short_ttime(bfqq);
-+
-+	if (bic->saved_IO_bound)
-+		bfq_mark_bfqq_IO_bound(bfqq);
-+	else
-+		bfq_clear_bfqq_IO_bound(bfqq);
-+
-+	if (unlikely(busy))
-+		old_wr_coeff = bfqq->wr_coeff;
-+
-+	bfqq->wr_coeff = bic->saved_wr_coeff;
-+	bfqq->wr_start_at_switch_to_srt = bic->saved_wr_start_at_switch_to_srt;
-+	BUG_ON(time_is_after_jiffies(bfqq->wr_start_at_switch_to_srt));
-+	bfqq->last_wr_start_finish = bic->saved_last_wr_start_finish;
-+	bfqq->wr_cur_max_time = bic->saved_wr_cur_max_time;
-+	BUG_ON(time_is_after_jiffies(bfqq->last_wr_start_finish));
-+
-+	bfq_log_bfqq(bfqq->bfqd, bfqq,
-+		     "bic %p wr_coeff %d start_finish %lu max_time %lu",
-+		     bic, bfqq->wr_coeff, bfqq->last_wr_start_finish,
-+		     bfqq->wr_cur_max_time);
-+
-+	if (bfqq->wr_coeff > 1 && (bfq_bfqq_in_large_burst(bfqq) ||
-+				   time_is_before_jiffies(bfqq->last_wr_start_finish +
-+							  bfqq->wr_cur_max_time))) {
-+		if (bfqq->wr_cur_max_time == bfqd->bfq_wr_rt_max_time &&
-+		    !bfq_bfqq_in_large_burst(bfqq) &&
-+		    time_is_after_eq_jiffies(bfqq->wr_start_at_switch_to_srt +
-+					     bfq_wr_duration(bfqd))) {
-+			switch_back_to_interactive_wr(bfqq, bfqd);
-+			bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			     "switching back to interactive");
-+		} else {
-+			bfqq->wr_coeff = 1;
-+			bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			     "switching off wr (%lu + %lu < %lu)",
-+			     bfqq->last_wr_start_finish, bfqq->wr_cur_max_time,
-+			     jiffies);
-+		}
-+	}
-+
-+	/* make sure weight will be updated, however we got here */
-+	bfqq->entity.prio_changed = 1;
-+
-+	if (likely(!busy))
-+		return;
-+
-+	if (old_wr_coeff == 1 && bfqq->wr_coeff > 1) {
-+		bfqd->wr_busy_queues++;
-+		BUG_ON(bfqd->wr_busy_queues > bfqd->busy_queues);
-+	} else if (old_wr_coeff > 1 && bfqq->wr_coeff == 1) {
-+		bfqd->wr_busy_queues--;
-+		BUG_ON(bfqd->wr_busy_queues < 0);
-+	}
-+}
-+
-+static int bfqq_process_refs(struct bfq_queue *bfqq)
-+{
-+	int process_refs, io_refs;
-+
-+	lockdep_assert_held(bfqq->bfqd->queue->queue_lock);
-+
-+	io_refs = bfqq->allocated[READ] + bfqq->allocated[WRITE];
-+	process_refs = bfqq->ref - io_refs - bfqq->entity.on_st;
-+	BUG_ON(process_refs < 0);
-+	return process_refs;
-+}
-+
-+/* Empty burst list and add just bfqq (see comments to bfq_handle_burst) */
-+static void bfq_reset_burst_list(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	struct bfq_queue *item;
-+	struct hlist_node *n;
-+
-+	hlist_for_each_entry_safe(item, n, &bfqd->burst_list, burst_list_node)
-+		hlist_del_init(&item->burst_list_node);
-+	hlist_add_head(&bfqq->burst_list_node, &bfqd->burst_list);
-+	bfqd->burst_size = 1;
-+	bfqd->burst_parent_entity = bfqq->entity.parent;
-+}
-+
-+/* Add bfqq to the list of queues in current burst (see bfq_handle_burst) */
-+static void bfq_add_to_burst(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	/* Increment burst size to take into account also bfqq */
-+	bfqd->burst_size++;
-+
-+	bfq_log_bfqq(bfqd, bfqq, "%d", bfqd->burst_size);
-+
-+	BUG_ON(bfqd->burst_size > bfqd->bfq_large_burst_thresh);
-+
-+	if (bfqd->burst_size == bfqd->bfq_large_burst_thresh) {
-+		struct bfq_queue *pos, *bfqq_item;
-+		struct hlist_node *n;
-+
-+		/*
-+		 * Enough queues have been activated shortly after each
-+		 * other to consider this burst as large.
-+		 */
-+		bfqd->large_burst = true;
-+		bfq_log_bfqq(bfqd, bfqq, "large burst started");
-+
-+		/*
-+		 * We can now mark all queues in the burst list as
-+		 * belonging to a large burst.
-+		 */
-+		hlist_for_each_entry(bfqq_item, &bfqd->burst_list,
-+				     burst_list_node) {
-+			bfq_mark_bfqq_in_large_burst(bfqq_item);
-+			bfq_log_bfqq(bfqd, bfqq_item, "marked in large burst");
-+		}
-+		bfq_mark_bfqq_in_large_burst(bfqq);
-+		bfq_log_bfqq(bfqd, bfqq, "marked in large burst");
-+
-+		/*
-+		 * From now on, and until the current burst finishes, any
-+		 * new queue being activated shortly after the last queue
-+		 * was inserted in the burst can be immediately marked as
-+		 * belonging to a large burst. So the burst list is not
-+		 * needed any more. Remove it.
-+		 */
-+		hlist_for_each_entry_safe(pos, n, &bfqd->burst_list,
-+					  burst_list_node)
-+			hlist_del_init(&pos->burst_list_node);
-+	} else /*
-+		* Burst not yet large: add bfqq to the burst list. Do
-+		* not increment the ref counter for bfqq, because bfqq
-+		* is removed from the burst list before freeing bfqq
-+		* in put_queue.
-+		*/
-+		hlist_add_head(&bfqq->burst_list_node, &bfqd->burst_list);
-+}
-+
-+/*
-+ * If many queues belonging to the same group happen to be created
-+ * shortly after each other, then the processes associated with these
-+ * queues have typically a common goal. In particular, bursts of queue
-+ * creations are usually caused by services or applications that spawn
-+ * many parallel threads/processes. Examples are systemd during boot,
-+ * or git grep. To help these processes get their job done as soon as
-+ * possible, it is usually better to not grant either weight-raising
-+ * or device idling to their queues.
-+ *
-+ * In this comment we describe, firstly, the reasons why this fact
-+ * holds, and, secondly, the next function, which implements the main
-+ * steps needed to properly mark these queues so that they can then be
-+ * treated in a different way.
-+ *
-+ * The above services or applications benefit mostly from a high
-+ * throughput: the quicker the requests of the activated queues are
-+ * cumulatively served, the sooner the target job of these queues gets
-+ * completed. As a consequence, weight-raising any of these queues,
-+ * which also implies idling the device for it, is almost always
-+ * counterproductive. In most cases it just lowers throughput.
-+ *
-+ * On the other hand, a burst of queue creations may be caused also by
-+ * the start of an application that does not consist of a lot of
-+ * parallel I/O-bound threads. In fact, with a complex application,
-+ * several short processes may need to be executed to start-up the
-+ * application. In this respect, to start an application as quickly as
-+ * possible, the best thing to do is in any case to privilege the I/O
-+ * related to the application with respect to all other
-+ * I/O. Therefore, the best strategy to start as quickly as possible
-+ * an application that causes a burst of queue creations is to
-+ * weight-raise all the queues created during the burst. This is the
-+ * exact opposite of the best strategy for the other type of bursts.
-+ *
-+ * In the end, to take the best action for each of the two cases, the
-+ * two types of bursts need to be distinguished. Fortunately, this
-+ * seems relatively easy, by looking at the sizes of the bursts. In
-+ * particular, we found a threshold such that only bursts with a
-+ * larger size than that threshold are apparently caused by
-+ * services or commands such as systemd or git grep. For brevity,
-+ * hereafter we call just 'large' these bursts. BFQ *does not*
-+ * weight-raise queues whose creation occurs in a large burst. In
-+ * addition, for each of these queues BFQ performs or does not perform
-+ * idling depending on which choice boosts the throughput more. The
-+ * exact choice depends on the device and request pattern at
-+ * hand.
-+ *
-+ * Unfortunately, false positives may occur while an interactive task
-+ * is starting (e.g., an application is being started). The
-+ * consequence is that the queues associated with the task do not
-+ * enjoy weight raising as expected. Fortunately these false positives
-+ * are very rare. They typically occur if some service happens to
-+ * start doing I/O exactly when the interactive task starts.
-+ *
-+ * Turning back to the next function, it implements all the steps
-+ * needed to detect the occurrence of a large burst and to properly
-+ * mark all the queues belonging to it (so that they can then be
-+ * treated in a different way). This goal is achieved by maintaining a
-+ * "burst list" that holds, temporarily, the queues that belong to the
-+ * burst in progress. The list is then used to mark these queues as
-+ * belonging to a large burst if the burst does become large. The main
-+ * steps are the following.
-+ *
-+ * . when the very first queue is created, the queue is inserted into the
-+ *   list (as it could be the first queue in a possible burst)
-+ *
-+ * . if the current burst has not yet become large, and a queue Q that does
-+ *   not yet belong to the burst is activated shortly after the last time
-+ *   at which a new queue entered the burst list, then the function appends
-+ *   Q to the burst list
-+ *
-+ * . if, as a consequence of the previous step, the burst size reaches
-+ *   the large-burst threshold, then
-+ *
-+ *     . all the queues in the burst list are marked as belonging to a
-+ *       large burst
-+ *
-+ *     . the burst list is deleted; in fact, the burst list already served
-+ *       its purpose (keeping temporarily track of the queues in a burst,
-+ *       so as to be able to mark them as belonging to a large burst in the
-+ *       previous sub-step), and now is not needed any more
-+ *
-+ *     . the device enters a large-burst mode
-+ *
-+ * . if a queue Q that does not belong to the burst is created while
-+ *   the device is in large-burst mode and shortly after the last time
-+ *   at which a queue either entered the burst list or was marked as
-+ *   belonging to the current large burst, then Q is immediately marked
-+ *   as belonging to a large burst.
-+ *
-+ * . if a queue Q that does not belong to the burst is created a while
-+ *   later, i.e., not shortly after, than the last time at which a queue
-+ *   either entered the burst list or was marked as belonging to the
-+ *   current large burst, then the current burst is deemed as finished and:
-+ *
-+ *        . the large-burst mode is reset if set
-+ *
-+ *        . the burst list is emptied
-+ *
-+ *        . Q is inserted in the burst list, as Q may be the first queue
-+ *          in a possible new burst (then the burst list contains just Q
-+ *          after this step).
-+ */
-+static void bfq_handle_burst(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	/*
-+	 * If bfqq is already in the burst list or is part of a large
-+	 * burst, or finally has just been split, then there is
-+	 * nothing else to do.
-+	 */
-+	if (!hlist_unhashed(&bfqq->burst_list_node) ||
-+	    bfq_bfqq_in_large_burst(bfqq) ||
-+	    time_is_after_eq_jiffies(bfqq->split_time +
-+				     msecs_to_jiffies(10)))
-+		return;
-+
-+	/*
-+	 * If bfqq's creation happens late enough, or bfqq belongs to
-+	 * a different group than the burst group, then the current
-+	 * burst is finished, and related data structures must be
-+	 * reset.
-+	 *
-+	 * In this respect, consider the special case where bfqq is
-+	 * the very first queue created after BFQ is selected for this
-+	 * device. In this case, last_ins_in_burst and
-+	 * burst_parent_entity are not yet significant when we get
-+	 * here. But it is easy to verify that, whether or not the
-+	 * following condition is true, bfqq will end up being
-+	 * inserted into the burst list. In particular the list will
-+	 * happen to contain only bfqq. And this is exactly what has
-+	 * to happen, as bfqq may be the first queue of the first
-+	 * burst.
-+	 */
-+	if (time_is_before_jiffies(bfqd->last_ins_in_burst +
-+	    bfqd->bfq_burst_interval) ||
-+	    bfqq->entity.parent != bfqd->burst_parent_entity) {
-+		bfqd->large_burst = false;
-+		bfq_reset_burst_list(bfqd, bfqq);
-+		bfq_log_bfqq(bfqd, bfqq,
-+			"late activation or different group");
-+		goto end;
-+	}
-+
-+	/*
-+	 * If we get here, then bfqq is being activated shortly after the
-+	 * last queue. So, if the current burst is also large, we can mark
-+	 * bfqq as belonging to this large burst immediately.
-+	 */
-+	if (bfqd->large_burst) {
-+		bfq_log_bfqq(bfqd, bfqq, "marked in burst");
-+		bfq_mark_bfqq_in_large_burst(bfqq);
-+		goto end;
-+	}
-+
-+	/*
-+	 * If we get here, then a large-burst state has not yet been
-+	 * reached, but bfqq is being activated shortly after the last
-+	 * queue. Then we add bfqq to the burst.
-+	 */
-+	bfq_add_to_burst(bfqd, bfqq);
-+end:
-+	/*
-+	 * At this point, bfqq either has been added to the current
-+	 * burst or has caused the current burst to terminate and a
-+	 * possible new burst to start. In particular, in the second
-+	 * case, bfqq has become the first queue in the possible new
-+	 * burst.  In both cases last_ins_in_burst needs to be moved
-+	 * forward.
-+	 */
-+	bfqd->last_ins_in_burst = jiffies;
-+
-+}
-+
-+static int bfq_bfqq_budget_left(struct bfq_queue *bfqq)
-+{
-+	struct bfq_entity *entity = &bfqq->entity;
-+
-+	if (entity->budget < entity->service) {
-+		pr_crit("budget %d service %d\n",
-+			entity->budget, entity->service);
-+		BUG();
-+	}
-+	return entity->budget - entity->service;
-+}
-+
-+/*
-+ * If enough samples have been computed, return the current max budget
-+ * stored in bfqd, which is dynamically updated according to the
-+ * estimated disk peak rate; otherwise return the default max budget
-+ */
-+static int bfq_max_budget(struct bfq_data *bfqd)
-+{
-+	if (bfqd->budgets_assigned < bfq_stats_min_budgets)
-+		return bfq_default_max_budget;
-+	else
-+		return bfqd->bfq_max_budget;
-+}
-+
-+/*
-+ * Return min budget, which is a fraction of the current or default
-+ * max budget (trying with 1/32)
-+ */
-+static int bfq_min_budget(struct bfq_data *bfqd)
-+{
-+	if (bfqd->budgets_assigned < bfq_stats_min_budgets)
-+		return bfq_default_max_budget / 32;
-+	else
-+		return bfqd->bfq_max_budget / 32;
-+}
-+
-+static void bfq_bfqq_expire(struct bfq_data *bfqd,
-+			    struct bfq_queue *bfqq,
-+			    bool compensate,
-+			    enum bfqq_expiration reason);
-+
-+/*
-+ * The next function, invoked after the input queue bfqq switches from
-+ * idle to busy, updates the budget of bfqq. The function also tells
-+ * whether the in-service queue should be expired, by returning
-+ * true. The purpose of expiring the in-service queue is to give bfqq
-+ * the chance to possibly preempt the in-service queue, and the reason
-+ * for preempting the in-service queue is to achieve one of the two
-+ * goals below.
-+ *
-+ * 1. Guarantee to bfqq its reserved bandwidth even if bfqq has
-+ * expired because it has remained idle. In particular, bfqq may have
-+ * expired for one of the following two reasons:
-+ *
-+ * - BFQ_BFQQ_NO_MORE_REQUEST bfqq did not enjoy any device idling and
-+ *   did not make it to issue a new request before its last request
-+ *   was served;
-+ *
-+ * - BFQ_BFQQ_TOO_IDLE bfqq did enjoy device idling, but did not issue
-+ *   a new request before the expiration of the idling-time.
-+ *
-+ * Even if bfqq has expired for one of the above reasons, the process
-+ * associated with the queue may be however issuing requests greedily,
-+ * and thus be sensitive to the bandwidth it receives (bfqq may have
-+ * remained idle for other reasons: CPU high load, bfqq not enjoying
-+ * idling, I/O throttling somewhere in the path from the process to
-+ * the I/O scheduler, ...). But if, after every expiration for one of
-+ * the above two reasons, bfqq has to wait for the service of at least
-+ * one full budget of another queue before being served again, then
-+ * bfqq is likely to get a much lower bandwidth or resource time than
-+ * its reserved ones. To address this issue, two countermeasures need
-+ * to be taken.
-+ *
-+ * First, the budget and the timestamps of bfqq need to be updated in
-+ * a special way on bfqq reactivation: they need to be updated as if
-+ * bfqq did not remain idle and did not expire. In fact, if they are
-+ * computed as if bfqq expired and remained idle until reactivation,
-+ * then the process associated with bfqq is treated as if, instead of
-+ * being greedy, it stopped issuing requests when bfqq remained idle,
-+ * and restarts issuing requests only on this reactivation. In other
-+ * words, the scheduler does not help the process recover the "service
-+ * hole" between bfqq expiration and reactivation. As a consequence,
-+ * the process receives a lower bandwidth than its reserved one. In
-+ * contrast, to recover this hole, the budget must be updated as if
-+ * bfqq was not expired at all before this reactivation, i.e., it must
-+ * be set to the value of the remaining budget when bfqq was
-+ * expired. Along the same line, timestamps need to be assigned the
-+ * value they had the last time bfqq was selected for service, i.e.,
-+ * before last expiration. Thus timestamps need to be back-shifted
-+ * with respect to their normal computation (see [1] for more details
-+ * on this tricky aspect).
-+ *
-+ * Secondly, to allow the process to recover the hole, the in-service
-+ * queue must be expired too, to give bfqq the chance to preempt it
-+ * immediately. In fact, if bfqq has to wait for a full budget of the
-+ * in-service queue to be completed, then it may become impossible to
-+ * let the process recover the hole, even if the back-shifted
-+ * timestamps of bfqq are lower than those of the in-service queue. If
-+ * this happens for most or all of the holes, then the process may not
-+ * receive its reserved bandwidth. In this respect, it is worth noting
-+ * that, being the service of outstanding requests unpreemptible, a
-+ * little fraction of the holes may however be unrecoverable, thereby
-+ * causing a little loss of bandwidth.
-+ *
-+ * The last important point is detecting whether bfqq does need this
-+ * bandwidth recovery. In this respect, the next function deems the
-+ * process associated with bfqq greedy, and thus allows it to recover
-+ * the hole, if: 1) the process is waiting for the arrival of a new
-+ * request (which implies that bfqq expired for one of the above two
-+ * reasons), and 2) such a request has arrived soon. The first
-+ * condition is controlled through the flag non_blocking_wait_rq,
-+ * while the second through the flag arrived_in_time. If both
-+ * conditions hold, then the function computes the budget in the
-+ * above-described special way, and signals that the in-service queue
-+ * should be expired. Timestamp back-shifting is done later in
-+ * __bfq_activate_entity.
-+ *
-+ * 2. Reduce latency. Even if timestamps are not backshifted to let
-+ * the process associated with bfqq recover a service hole, bfqq may
-+ * however happen to have, after being (re)activated, a lower finish
-+ * timestamp than the in-service queue.  That is, the next budget of
-+ * bfqq may have to be completed before the one of the in-service
-+ * queue. If this is the case, then preempting the in-service queue
-+ * allows this goal to be achieved, apart from the unpreemptible,
-+ * outstanding requests mentioned above.
-+ *
-+ * Unfortunately, regardless of which of the above two goals one wants
-+ * to achieve, service trees need first to be updated to know whether
-+ * the in-service queue must be preempted. To have service trees
-+ * correctly updated, the in-service queue must be expired and
-+ * rescheduled, and bfqq must be scheduled too. This is one of the
-+ * most costly operations (in future versions, the scheduling
-+ * mechanism may be re-designed in such a way to make it possible to
-+ * know whether preemption is needed without needing to update service
-+ * trees). In addition, queue preemptions almost always cause random
-+ * I/O, and thus loss of throughput. Because of these facts, the next
-+ * function adopts the following simple scheme to avoid both costly
-+ * operations and too frequent preemptions: it requests the expiration
-+ * of the in-service queue (unconditionally) only for queues that need
-+ * to recover a hole, or that either are weight-raised or deserve to
-+ * be weight-raised.
-+ */
-+static bool bfq_bfqq_update_budg_for_activation(struct bfq_data *bfqd,
-+						struct bfq_queue *bfqq,
-+						bool arrived_in_time,
-+						bool wr_or_deserves_wr)
-+{
-+	struct bfq_entity *entity = &bfqq->entity;
-+
-+	if (bfq_bfqq_non_blocking_wait_rq(bfqq) && arrived_in_time) {
-+		/*
-+		 * We do not clear the flag non_blocking_wait_rq here, as
-+		 * the latter is used in bfq_activate_bfqq to signal
-+		 * that timestamps need to be back-shifted (and is
-+		 * cleared right after).
-+		 */
-+
-+		/*
-+		 * In next assignment we rely on that either
-+		 * entity->service or entity->budget are not updated
-+		 * on expiration if bfqq is empty (see
-+		 * __bfq_bfqq_recalc_budget). Thus both quantities
-+		 * remain unchanged after such an expiration, and the
-+		 * following statement therefore assigns to
-+		 * entity->budget the remaining budget on such an
-+		 * expiration.
-+		 */
-+		BUG_ON(bfqq->max_budget < 0);
-+		entity->budget = min_t(unsigned long,
-+				       bfq_bfqq_budget_left(bfqq),
-+				       bfqq->max_budget);
-+
-+		BUG_ON(entity->budget < 0);
-+
-+		/*
-+		 * At this point, we have used entity->service to get
-+		 * the budget left (needed for updating
-+		 * entity->budget). Thus we finally can, and have to,
-+		 * reset entity->service. The latter must be reset
-+		 * because bfqq would otherwise be charged again for
-+		 * the service it has received during its previous
-+		 * service slot(s).
-+		 */
-+		entity->service = 0;
-+
-+		return true;
-+	}
-+
-+	/*
-+	 * We can finally complete expiration, by setting service to 0.
-+	 */
-+	entity->service = 0;
-+	BUG_ON(bfqq->max_budget < 0);
-+	entity->budget = max_t(unsigned long, bfqq->max_budget,
-+			       bfq_serv_to_charge(bfqq->next_rq, bfqq));
-+	BUG_ON(entity->budget < 0);
-+
-+	bfq_clear_bfqq_non_blocking_wait_rq(bfqq);
-+	return wr_or_deserves_wr;
-+}
-+
-+/*
-+ * Return the farthest past time instant according to jiffies
-+ * macros.
-+ */
-+static unsigned long bfq_smallest_from_now(void)
-+{
-+	return jiffies - MAX_JIFFY_OFFSET;
-+}
-+
-+static void bfq_update_bfqq_wr_on_rq_arrival(struct bfq_data *bfqd,
-+					     struct bfq_queue *bfqq,
-+					     unsigned int old_wr_coeff,
-+					     bool wr_or_deserves_wr,
-+					     bool interactive,
-+					     bool in_burst,
-+					     bool soft_rt)
-+{
-+	if (old_wr_coeff == 1 && wr_or_deserves_wr) {
-+		/* start a weight-raising period */
-+		if (interactive) {
-+			bfqq->service_from_wr = 0;
-+			bfqq->wr_coeff = bfqd->bfq_wr_coeff;
-+			bfqq->wr_cur_max_time = bfq_wr_duration(bfqd);
-+		} else {
-+			/*
-+			 * No interactive weight raising in progress
-+			 * here: assign minus infinity to
-+			 * wr_start_at_switch_to_srt, to make sure
-+			 * that, at the end of the soft-real-time
-+			 * weight raising periods that is starting
-+			 * now, no interactive weight-raising period
-+			 * may be wrongly considered as still in
-+			 * progress (and thus actually started by
-+			 * mistake).
-+			 */
-+			bfqq->wr_start_at_switch_to_srt =
-+				bfq_smallest_from_now();
-+			bfqq->wr_coeff = bfqd->bfq_wr_coeff *
-+				BFQ_SOFTRT_WEIGHT_FACTOR;
-+			bfqq->wr_cur_max_time =
-+				bfqd->bfq_wr_rt_max_time;
-+		}
-+		/*
-+		 * If needed, further reduce budget to make sure it is
-+		 * close to bfqq's backlog, so as to reduce the
-+		 * scheduling-error component due to a too large
-+		 * budget. Do not care about throughput consequences,
-+		 * but only about latency. Finally, do not assign a
-+		 * too small budget either, to avoid increasing
-+		 * latency by causing too frequent expirations.
-+		 */
-+		bfqq->entity.budget = min_t(unsigned long,
-+					    bfqq->entity.budget,
-+					    2 * bfq_min_budget(bfqd));
-+
-+		bfq_log_bfqq(bfqd, bfqq,
-+			     "wrais starting at %lu, rais_max_time %u",
-+			     jiffies,
-+			     jiffies_to_msecs(bfqq->wr_cur_max_time));
-+	} else if (old_wr_coeff > 1) {
-+		if (interactive) { /* update wr coeff and duration */
-+			bfqq->wr_coeff = bfqd->bfq_wr_coeff;
-+			bfqq->wr_cur_max_time = bfq_wr_duration(bfqd);
-+		} else if (in_burst) {
-+			bfqq->wr_coeff = 1;
-+			bfq_log_bfqq(bfqd, bfqq,
-+				     "wrais ending at %lu, rais_max_time %u",
-+				     jiffies,
-+				     jiffies_to_msecs(bfqq->
-+						      wr_cur_max_time));
-+		} else if (soft_rt) {
-+			/*
-+			 * The application is now or still meeting the
-+			 * requirements for being deemed soft rt.  We
-+			 * can then correctly and safely (re)charge
-+			 * the weight-raising duration for the
-+			 * application with the weight-raising
-+			 * duration for soft rt applications.
-+			 *
-+			 * In particular, doing this recharge now, i.e.,
-+			 * before the weight-raising period for the
-+			 * application finishes, reduces the probability
-+			 * of the following negative scenario:
-+			 * 1) the weight of a soft rt application is
-+			 *    raised at startup (as for any newly
-+			 *    created application),
-+			 * 2) since the application is not interactive,
-+			 *    at a certain time weight-raising is
-+			 *    stopped for the application,
-+			 * 3) at that time the application happens to
-+			 *    still have pending requests, and hence
-+			 *    is destined to not have a chance to be
-+			 *    deemed soft rt before these requests are
-+			 *    completed (see the comments to the
-+			 *    function bfq_bfqq_softrt_next_start()
-+			 *    for details on soft rt detection),
-+			 * 4) these pending requests experience a high
-+			 *    latency because the application is not
-+			 *    weight-raised while they are pending.
-+			 */
-+			if (bfqq->wr_cur_max_time !=
-+				bfqd->bfq_wr_rt_max_time) {
-+				bfqq->wr_start_at_switch_to_srt =
-+					bfqq->last_wr_start_finish;
-+                BUG_ON(time_is_after_jiffies(bfqq->last_wr_start_finish));
-+
-+				bfqq->wr_cur_max_time =
-+					bfqd->bfq_wr_rt_max_time;
-+				bfqq->wr_coeff = bfqd->bfq_wr_coeff *
-+					BFQ_SOFTRT_WEIGHT_FACTOR;
-+				bfq_log_bfqq(bfqd, bfqq,
-+					     "switching to soft_rt wr");
-+			} else
-+				bfq_log_bfqq(bfqd, bfqq,
-+					"moving forward soft_rt wr duration");
-+			bfqq->last_wr_start_finish = jiffies;
-+		}
-+	}
-+}
-+
-+static bool bfq_bfqq_idle_for_long_time(struct bfq_data *bfqd,
-+					struct bfq_queue *bfqq)
-+{
-+	return bfqq->dispatched == 0 &&
-+		time_is_before_jiffies(
-+			bfqq->budget_timeout +
-+			bfqd->bfq_wr_min_idle_time);
-+}
-+
-+static void bfq_bfqq_handle_idle_busy_switch(struct bfq_data *bfqd,
-+					     struct bfq_queue *bfqq,
-+					     int old_wr_coeff,
-+					     struct request *rq,
-+					     bool *interactive)
-+{
-+	bool soft_rt, in_burst,	wr_or_deserves_wr,
-+		bfqq_wants_to_preempt,
-+		idle_for_long_time = bfq_bfqq_idle_for_long_time(bfqd, bfqq),
-+		/*
-+		 * See the comments on
-+		 * bfq_bfqq_update_budg_for_activation for
-+		 * details on the usage of the next variable.
-+		 */
-+		arrived_in_time =  ktime_get_ns() <=
-+			RQ_BIC(rq)->ttime.last_end_request +
-+			bfqd->bfq_slice_idle * 3;
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+		     "bfq_add_request non-busy: "
-+		     "jiffies %lu, in_time %d, idle_long %d busyw %d "
-+		     "wr_coeff %u",
-+		     jiffies, arrived_in_time,
-+		     idle_for_long_time,
-+		     bfq_bfqq_non_blocking_wait_rq(bfqq),
-+		     old_wr_coeff);
-+
-+	BUG_ON(bfqq->entity.budget < bfqq->entity.service);
-+
-+	BUG_ON(bfqq == bfqd->in_service_queue);
-+	bfqg_stats_update_io_add(bfqq_group(RQ_BFQQ(rq)), bfqq, rq->cmd_flags);
-+
-+	/*
-+	 * bfqq deserves to be weight-raised if:
-+	 * - it is sync,
-+	 * - it does not belong to a large burst,
-+	 * - it has been idle for enough time or is soft real-time,
-+	 * - is linked to a bfq_io_cq (it is not shared in any sense)
-+	 */
-+	in_burst = bfq_bfqq_in_large_burst(bfqq);
-+	soft_rt = bfqd->bfq_wr_max_softrt_rate > 0 &&
-+		!in_burst &&
-+		time_is_before_jiffies(bfqq->soft_rt_next_start) &&
-+		bfqq->dispatched == 0;
-+	*interactive =
-+		!in_burst &&
-+		idle_for_long_time;
-+	wr_or_deserves_wr = bfqd->low_latency &&
-+		(bfqq->wr_coeff > 1 ||
-+		 (bfq_bfqq_sync(bfqq) &&
-+		  bfqq->bic && (*interactive || soft_rt)));
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+		     "bfq_add_request: "
-+		     "in_burst %d, "
-+		     "soft_rt %d (next %lu), inter %d, bic %p",
-+		     bfq_bfqq_in_large_burst(bfqq), soft_rt,
-+		     bfqq->soft_rt_next_start,
-+		     *interactive,
-+		     bfqq->bic);
-+
-+	/*
-+	 * Using the last flag, update budget and check whether bfqq
-+	 * may want to preempt the in-service queue.
-+	 */
-+	bfqq_wants_to_preempt =
-+		bfq_bfqq_update_budg_for_activation(bfqd, bfqq,
-+						    arrived_in_time,
-+						    wr_or_deserves_wr);
-+
-+	/*
-+	 * If bfqq happened to be activated in a burst, but has been
-+	 * idle for much more than an interactive queue, then we
-+	 * assume that, in the overall I/O initiated in the burst, the
-+	 * I/O associated with bfqq is finished. So bfqq does not need
-+	 * to be treated as a queue belonging to a burst
-+	 * anymore. Accordingly, we reset bfqq's in_large_burst flag
-+	 * if set, and remove bfqq from the burst list if it's
-+	 * there. We do not decrement burst_size, because the fact
-+	 * that bfqq does not need to belong to the burst list any
-+	 * more does not invalidate the fact that bfqq was created in
-+	 * a burst.
-+	 */
-+	if (likely(!bfq_bfqq_just_created(bfqq)) &&
-+	    idle_for_long_time &&
-+	    time_is_before_jiffies(
-+		    bfqq->budget_timeout +
-+		    msecs_to_jiffies(10000))) {
-+		hlist_del_init(&bfqq->burst_list_node);
-+		bfq_clear_bfqq_in_large_burst(bfqq);
-+	}
-+
-+	bfq_clear_bfqq_just_created(bfqq);
-+
-+	if (!bfq_bfqq_IO_bound(bfqq)) {
-+		if (arrived_in_time) {
-+			bfqq->requests_within_timer++;
-+			if (bfqq->requests_within_timer >=
-+			    bfqd->bfq_requests_within_timer)
-+				bfq_mark_bfqq_IO_bound(bfqq);
-+		} else
-+			bfqq->requests_within_timer = 0;
-+		bfq_log_bfqq(bfqd, bfqq, "requests in time %d",
-+			     bfqq->requests_within_timer);
-+	}
-+
-+	if (bfqd->low_latency) {
-+		if (unlikely(time_is_after_jiffies(bfqq->split_time)))
-+			/* wraparound */
-+			bfqq->split_time =
-+				jiffies - bfqd->bfq_wr_min_idle_time - 1;
-+
-+		if (time_is_before_jiffies(bfqq->split_time +
-+					   bfqd->bfq_wr_min_idle_time)) {
-+			bfq_update_bfqq_wr_on_rq_arrival(bfqd, bfqq,
-+							 old_wr_coeff,
-+							 wr_or_deserves_wr,
-+							 *interactive,
-+							 in_burst,
-+							 soft_rt);
-+
-+			if (old_wr_coeff != bfqq->wr_coeff)
-+				bfqq->entity.prio_changed = 1;
-+		}
-+	}
-+
-+	bfqq->last_idle_bklogged = jiffies;
-+	bfqq->service_from_backlogged = 0;
-+	bfq_clear_bfqq_softrt_update(bfqq);
-+
-+	bfq_add_bfqq_busy(bfqd, bfqq);
-+
-+	/*
-+	 * Expire in-service queue only if preemption may be needed
-+	 * for guarantees. In this respect, the function
-+	 * next_queue_may_preempt just checks a simple, necessary
-+	 * condition, and not a sufficient condition based on
-+	 * timestamps. In fact, for the latter condition to be
-+	 * evaluated, timestamps would need first to be updated, and
-+	 * this operation is quite costly (see the comments on the
-+	 * function bfq_bfqq_update_budg_for_activation).
-+	 */
-+	if (bfqd->in_service_queue && bfqq_wants_to_preempt &&
-+	    bfqd->in_service_queue->wr_coeff < bfqq->wr_coeff &&
-+	    next_queue_may_preempt(bfqd)) {
-+		struct bfq_queue *in_serv =
-+			bfqd->in_service_queue;
-+		BUG_ON(in_serv == bfqq);
-+
-+		bfq_bfqq_expire(bfqd, bfqd->in_service_queue,
-+				false, BFQ_BFQQ_PREEMPTED);
-+	}
-+}
-+
-+static void bfq_add_request(struct request *rq)
-+{
-+	struct bfq_queue *bfqq = RQ_BFQQ(rq);
-+	struct bfq_data *bfqd = bfqq->bfqd;
-+	struct request *next_rq, *prev;
-+	unsigned int old_wr_coeff = bfqq->wr_coeff;
-+	bool interactive = false;
-+
-+	bfq_log_bfqq(bfqd, bfqq, "size %u %s",
-+		     blk_rq_sectors(rq), rq_is_sync(rq) ? "S" : "A");
-+
-+	if (bfqq->wr_coeff > 1) /* queue is being weight-raised */
-+		bfq_log_bfqq(bfqd, bfqq,
-+			"raising period dur %u/%u msec, old coeff %u, w %d(%d)",
-+			jiffies_to_msecs(jiffies - bfqq->last_wr_start_finish),
-+			jiffies_to_msecs(bfqq->wr_cur_max_time),
-+			bfqq->wr_coeff,
-+			bfqq->entity.weight, bfqq->entity.orig_weight);
-+
-+	bfqq->queued[rq_is_sync(rq)]++;
-+	bfqd->queued++;
-+
-+	elv_rb_add(&bfqq->sort_list, rq);
-+
-+	/*
-+	 * Check if this request is a better next-to-serve candidate.
-+	 */
-+	prev = bfqq->next_rq;
-+	next_rq = bfq_choose_req(bfqd, bfqq->next_rq, rq, bfqd->last_position);
-+	BUG_ON(!next_rq);
-+	bfqq->next_rq = next_rq;
-+
-+	/*
-+	 * Adjust priority tree position, if next_rq changes.
-+	 */
-+	if (prev != bfqq->next_rq)
-+		bfq_pos_tree_add_move(bfqd, bfqq);
-+
-+	if (!bfq_bfqq_busy(bfqq)) /* switching to busy ... */
-+		bfq_bfqq_handle_idle_busy_switch(bfqd, bfqq, old_wr_coeff,
-+						 rq, &interactive);
-+	else {
-+		if (bfqd->low_latency && old_wr_coeff == 1 && !rq_is_sync(rq) &&
-+		    time_is_before_jiffies(
-+				bfqq->last_wr_start_finish +
-+				bfqd->bfq_wr_min_inter_arr_async)) {
-+			bfqq->wr_coeff = bfqd->bfq_wr_coeff;
-+			bfqq->wr_cur_max_time = bfq_wr_duration(bfqd);
-+
-+			bfqd->wr_busy_queues++;
-+			BUG_ON(bfqd->wr_busy_queues > bfqd->busy_queues);
-+			bfqq->entity.prio_changed = 1;
-+			bfq_log_bfqq(bfqd, bfqq,
-+				     "non-idle wrais starting, "
-+				     "wr_max_time %u wr_busy %d",
-+				     jiffies_to_msecs(bfqq->wr_cur_max_time),
-+				     bfqd->wr_busy_queues);
-+		}
-+		if (prev != bfqq->next_rq)
-+			bfq_updated_next_req(bfqd, bfqq);
-+	}
-+
-+	/*
-+	 * Assign jiffies to last_wr_start_finish in the following
-+	 * cases:
-+	 *
-+	 * . if bfqq is not going to be weight-raised, because, for
-+	 *   non weight-raised queues, last_wr_start_finish stores the
-+	 *   arrival time of the last request; as of now, this piece
-+	 *   of information is used only for deciding whether to
-+	 *   weight-raise async queues
-+	 *
-+	 * . if bfqq is not weight-raised, because, if bfqq is now
-+	 *   switching to weight-raised, then last_wr_start_finish
-+	 *   stores the time when weight-raising starts
-+	 *
-+	 * . if bfqq is interactive, because, regardless of whether
-+	 *   bfqq is currently weight-raised, the weight-raising
-+	 *   period must start or restart (this case is considered
-+	 *   separately because it is not detected by the above
-+	 *   conditions, if bfqq is already weight-raised)
-+	 *
-+	 * last_wr_start_finish has to be updated also if bfqq is soft
-+	 * real-time, because the weight-raising period is constantly
-+	 * restarted on idle-to-busy transitions for these queues, but
-+	 * this is already done in bfq_bfqq_handle_idle_busy_switch if
-+	 * needed.
-+	 */
-+	if (bfqd->low_latency &&
-+		(old_wr_coeff == 1 || bfqq->wr_coeff == 1 || interactive))
-+		bfqq->last_wr_start_finish = jiffies;
-+}
-+
-+static struct request *bfq_find_rq_fmerge(struct bfq_data *bfqd,
-+					  struct bio *bio)
-+{
-+	struct task_struct *tsk = current;
-+	struct bfq_io_cq *bic;
-+	struct bfq_queue *bfqq;
-+
-+	bic = bfq_bic_lookup(bfqd, tsk->io_context);
-+	if (!bic)
-+		return NULL;
-+
-+	bfqq = bic_to_bfqq(bic, op_is_sync(bio->bi_opf));
-+	if (bfqq)
-+		return elv_rb_find(&bfqq->sort_list, bio_end_sector(bio));
-+
-+	return NULL;
-+}
-+
-+static sector_t get_sdist(sector_t last_pos, struct request *rq)
-+{
-+	sector_t sdist = 0;
-+
-+	if (last_pos) {
-+		if (last_pos < blk_rq_pos(rq))
-+			sdist = blk_rq_pos(rq) - last_pos;
-+		else
-+			sdist = last_pos - blk_rq_pos(rq);
-+	}
-+
-+	return sdist;
-+}
-+
-+static void bfq_activate_request(struct request_queue *q, struct request *rq)
-+{
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+	bfqd->rq_in_driver++;
-+}
-+
-+static void bfq_deactivate_request(struct request_queue *q, struct request *rq)
-+{
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+
-+	BUG_ON(bfqd->rq_in_driver == 0);
-+	bfqd->rq_in_driver--;
-+}
-+
-+static void bfq_remove_request(struct request *rq)
-+{
-+	struct bfq_queue *bfqq = RQ_BFQQ(rq);
-+	struct bfq_data *bfqd = bfqq->bfqd;
-+	const int sync = rq_is_sync(rq);
-+
-+	BUG_ON(bfqq->entity.service > bfqq->entity.budget);
-+
-+	if (bfqq->next_rq == rq) {
-+		bfqq->next_rq = bfq_find_next_rq(bfqd, bfqq, rq);
-+		bfq_updated_next_req(bfqd, bfqq);
-+	}
-+
-+	if (rq->queuelist.prev != &rq->queuelist)
-+		list_del_init(&rq->queuelist);
-+	BUG_ON(bfqq->queued[sync] == 0);
-+	bfqq->queued[sync]--;
-+	bfqd->queued--;
-+	elv_rb_del(&bfqq->sort_list, rq);
-+
-+	if (RB_EMPTY_ROOT(&bfqq->sort_list)) {
-+		bfqq->next_rq = NULL;
-+
-+		BUG_ON(bfqq->entity.budget < 0);
-+
-+		if (bfq_bfqq_busy(bfqq) && bfqq != bfqd->in_service_queue) {
-+			BUG_ON(bfqq->ref < 2); /* referred by rq and on tree */
-+			bfq_del_bfqq_busy(bfqd, bfqq, false);
-+			/*
-+			 * bfqq emptied. In normal operation, when
-+			 * bfqq is empty, bfqq->entity.service and
-+			 * bfqq->entity.budget must contain,
-+			 * respectively, the service received and the
-+			 * budget used last time bfqq emptied. These
-+			 * facts do not hold in this case, as at least
-+			 * this last removal occurred while bfqq is
-+			 * not in service. To avoid inconsistencies,
-+			 * reset both bfqq->entity.service and
-+			 * bfqq->entity.budget, if bfqq has still a
-+			 * process that may issue I/O requests to it.
-+			 */
-+			bfqq->entity.budget = bfqq->entity.service = 0;
-+		}
-+
-+		/*
-+		 * Remove queue from request-position tree as it is empty.
-+		 */
-+		if (bfqq->pos_root) {
-+			rb_erase(&bfqq->pos_node, bfqq->pos_root);
-+			bfqq->pos_root = NULL;
-+		}
-+	} else {
-+		BUG_ON(!bfqq->next_rq);
-+		bfq_pos_tree_add_move(bfqd, bfqq);
-+	}
-+
-+	if (rq->cmd_flags & REQ_META) {
-+		BUG_ON(bfqq->meta_pending == 0);
-+		bfqq->meta_pending--;
-+	}
-+	bfqg_stats_update_io_remove(bfqq_group(bfqq), rq->cmd_flags);
-+}
-+
-+static enum elv_merge bfq_merge(struct request_queue *q, struct request **req,
-+				struct bio *bio)
-+{
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+	struct request *__rq;
-+
-+	__rq = bfq_find_rq_fmerge(bfqd, bio);
-+	if (__rq && elv_bio_merge_ok(__rq, bio)) {
-+		*req = __rq;
-+		return ELEVATOR_FRONT_MERGE;
-+	}
-+
-+	return ELEVATOR_NO_MERGE;
-+}
-+
-+static void bfq_merged_request(struct request_queue *q, struct request *req,
-+			       enum elv_merge type)
-+{
-+	if (type == ELEVATOR_FRONT_MERGE &&
-+	    rb_prev(&req->rb_node) &&
-+	    blk_rq_pos(req) <
-+	    blk_rq_pos(container_of(rb_prev(&req->rb_node),
-+				    struct request, rb_node))) {
-+		struct bfq_queue *bfqq = RQ_BFQQ(req);
-+		struct bfq_data *bfqd = bfqq->bfqd;
-+		struct request *prev, *next_rq;
-+
-+		/* Reposition request in its sort_list */
-+		elv_rb_del(&bfqq->sort_list, req);
-+		elv_rb_add(&bfqq->sort_list, req);
-+		/* Choose next request to be served for bfqq */
-+		prev = bfqq->next_rq;
-+		next_rq = bfq_choose_req(bfqd, bfqq->next_rq, req,
-+					 bfqd->last_position);
-+		BUG_ON(!next_rq);
-+		bfqq->next_rq = next_rq;
-+		/*
-+		 * If next_rq changes, update both the queue's budget to
-+		 * fit the new request and the queue's position in its
-+		 * rq_pos_tree.
-+		 */
-+		if (prev != bfqq->next_rq) {
-+			bfq_updated_next_req(bfqd, bfqq);
-+			bfq_pos_tree_add_move(bfqd, bfqq);
-+		}
-+	}
-+}
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+static void bfq_bio_merged(struct request_queue *q, struct request *req,
-+			   struct bio *bio)
-+{
-+	bfqg_stats_update_io_merged(bfqq_group(RQ_BFQQ(req)), bio->bi_opf);
-+}
-+#endif
-+
-+static void bfq_merged_requests(struct request_queue *q, struct request *rq,
-+				struct request *next)
-+{
-+	struct bfq_queue *bfqq = RQ_BFQQ(rq), *next_bfqq = RQ_BFQQ(next);
-+
-+	/*
-+	 * If next and rq belong to the same bfq_queue and next is older
-+	 * than rq, then reposition rq in the fifo (by substituting next
-+	 * with rq). Otherwise, if next and rq belong to different
-+	 * bfq_queues, never reposition rq: in fact, we would have to
-+	 * reposition it with respect to next's position in its own fifo,
-+	 * which would most certainly be too expensive with respect to
-+	 * the benefits.
-+	 */
-+	if (bfqq == next_bfqq &&
-+	    !list_empty(&rq->queuelist) && !list_empty(&next->queuelist) &&
-+	    next->fifo_time < rq->fifo_time) {
-+		list_del_init(&rq->queuelist);
-+		list_replace_init(&next->queuelist, &rq->queuelist);
-+		rq->fifo_time = next->fifo_time;
-+	}
-+
-+	if (bfqq->next_rq == next)
-+		bfqq->next_rq = rq;
-+
-+	bfq_remove_request(next);
-+	bfqg_stats_update_io_merged(bfqq_group(bfqq), next->cmd_flags);
-+}
-+
-+/* Must be called with bfqq != NULL */
-+static void bfq_bfqq_end_wr(struct bfq_queue *bfqq)
-+{
-+	BUG_ON(!bfqq);
-+
-+	if (bfq_bfqq_busy(bfqq)) {
-+		bfqq->bfqd->wr_busy_queues--;
-+		BUG_ON(bfqq->bfqd->wr_busy_queues < 0);
-+	}
-+	bfqq->wr_coeff = 1;
-+	bfqq->wr_cur_max_time = 0;
-+	bfqq->last_wr_start_finish = jiffies;
-+	/*
-+	 * Trigger a weight change on the next invocation of
-+	 * __bfq_entity_update_weight_prio.
-+	 */
-+	bfqq->entity.prio_changed = 1;
-+	bfq_log_bfqq(bfqq->bfqd, bfqq,
-+		     "wrais ending at %lu, rais_max_time %u",
-+		     bfqq->last_wr_start_finish,
-+		     jiffies_to_msecs(bfqq->wr_cur_max_time));
-+	bfq_log_bfqq(bfqq->bfqd, bfqq, "wr_busy %d",
-+		     bfqq->bfqd->wr_busy_queues);
-+}
-+
-+static void bfq_end_wr_async_queues(struct bfq_data *bfqd,
-+				    struct bfq_group *bfqg)
-+{
-+	int i, j;
-+
-+	for (i = 0; i < 2; i++)
-+		for (j = 0; j < IOPRIO_BE_NR; j++)
-+			if (bfqg->async_bfqq[i][j])
-+				bfq_bfqq_end_wr(bfqg->async_bfqq[i][j]);
-+	if (bfqg->async_idle_bfqq)
-+		bfq_bfqq_end_wr(bfqg->async_idle_bfqq);
-+}
-+
-+static void bfq_end_wr(struct bfq_data *bfqd)
-+{
-+	struct bfq_queue *bfqq;
-+
-+	spin_lock_irq(bfqd->queue->queue_lock);
-+
-+	list_for_each_entry(bfqq, &bfqd->active_list, bfqq_list)
-+		bfq_bfqq_end_wr(bfqq);
-+	list_for_each_entry(bfqq, &bfqd->idle_list, bfqq_list)
-+		bfq_bfqq_end_wr(bfqq);
-+	bfq_end_wr_async(bfqd);
-+
-+	spin_unlock_irq(bfqd->queue->queue_lock);
-+}
-+
-+static sector_t bfq_io_struct_pos(void *io_struct, bool request)
-+{
-+	if (request)
-+		return blk_rq_pos(io_struct);
-+	else
-+		return ((struct bio *)io_struct)->bi_iter.bi_sector;
-+}
-+
-+static int bfq_rq_close_to_sector(void *io_struct, bool request,
-+				  sector_t sector)
-+{
-+	return abs(bfq_io_struct_pos(io_struct, request) - sector) <=
-+	       BFQQ_CLOSE_THR;
-+}
-+
-+static struct bfq_queue *bfqq_find_close(struct bfq_data *bfqd,
-+					 struct bfq_queue *bfqq,
-+					 sector_t sector)
-+{
-+	struct rb_root *root = &bfq_bfqq_to_bfqg(bfqq)->rq_pos_tree;
-+	struct rb_node *parent, *node;
-+	struct bfq_queue *__bfqq;
-+
-+	if (RB_EMPTY_ROOT(root))
-+		return NULL;
-+
-+	/*
-+	 * First, if we find a request starting at the end of the last
-+	 * request, choose it.
-+	 */
-+	__bfqq = bfq_rq_pos_tree_lookup(bfqd, root, sector, &parent, NULL);
-+	if (__bfqq)
-+		return __bfqq;
-+
-+	/*
-+	 * If the exact sector wasn't found, the parent of the NULL leaf
-+	 * will contain the closest sector (rq_pos_tree sorted by
-+	 * next_request position).
-+	 */
-+	__bfqq = rb_entry(parent, struct bfq_queue, pos_node);
-+	if (bfq_rq_close_to_sector(__bfqq->next_rq, true, sector))
-+		return __bfqq;
-+
-+	if (blk_rq_pos(__bfqq->next_rq) < sector)
-+		node = rb_next(&__bfqq->pos_node);
-+	else
-+		node = rb_prev(&__bfqq->pos_node);
-+	if (!node)
-+		return NULL;
-+
-+	__bfqq = rb_entry(node, struct bfq_queue, pos_node);
-+	if (bfq_rq_close_to_sector(__bfqq->next_rq, true, sector))
-+		return __bfqq;
-+
-+	return NULL;
-+}
-+
-+static struct bfq_queue *bfq_find_close_cooperator(struct bfq_data *bfqd,
-+						   struct bfq_queue *cur_bfqq,
-+						   sector_t sector)
-+{
-+	struct bfq_queue *bfqq;
-+
-+	/*
-+	 * We shall notice if some of the queues are cooperating,
-+	 * e.g., working closely on the same area of the device. In
-+	 * that case, we can group them together and: 1) don't waste
-+	 * time idling, and 2) serve the union of their requests in
-+	 * the best possible order for throughput.
-+	 */
-+	bfqq = bfqq_find_close(bfqd, cur_bfqq, sector);
-+	if (!bfqq || bfqq == cur_bfqq)
-+		return NULL;
-+
-+	return bfqq;
-+}
-+
-+static struct bfq_queue *
-+bfq_setup_merge(struct bfq_queue *bfqq, struct bfq_queue *new_bfqq)
-+{
-+	int process_refs, new_process_refs;
-+	struct bfq_queue *__bfqq;
-+
-+	/*
-+	 * If there are no process references on the new_bfqq, then it is
-+	 * unsafe to follow the ->new_bfqq chain as other bfqq's in the chain
-+	 * may have dropped their last reference (not just their last process
-+	 * reference).
-+	 */
-+	if (!bfqq_process_refs(new_bfqq))
-+		return NULL;
-+
-+	/* Avoid a circular list and skip interim queue merges. */
-+	while ((__bfqq = new_bfqq->new_bfqq)) {
-+		if (__bfqq == bfqq)
-+			return NULL;
-+		new_bfqq = __bfqq;
-+	}
-+
-+	process_refs = bfqq_process_refs(bfqq);
-+	new_process_refs = bfqq_process_refs(new_bfqq);
-+	/*
-+	 * If the process for the bfqq has gone away, there is no
-+	 * sense in merging the queues.
-+	 */
-+	if (process_refs == 0 || new_process_refs == 0)
-+		return NULL;
-+
-+	bfq_log_bfqq(bfqq->bfqd, bfqq, "scheduling merge with queue %d",
-+		new_bfqq->pid);
-+
-+	/*
-+	 * Merging is just a redirection: the requests of the process
-+	 * owning one of the two queues are redirected to the other queue.
-+	 * The latter queue, in its turn, is set as shared if this is the
-+	 * first time that the requests of some process are redirected to
-+	 * it.
-+	 *
-+	 * We redirect bfqq to new_bfqq and not the opposite, because we
-+	 * are in the context of the process owning bfqq, hence we have
-+	 * the io_cq of this process. So we can immediately configure this
-+	 * io_cq to redirect the requests of the process to new_bfqq.
-+	 *
-+	 * NOTE, even if new_bfqq coincides with the in-service queue, the
-+	 * io_cq of new_bfqq is not available, because, if the in-service
-+	 * queue is shared, bfqd->in_service_bic may not point to the
-+	 * io_cq of the in-service queue.
-+	 * Redirecting the requests of the process owning bfqq to the
-+	 * currently in-service queue is in any case the best option, as
-+	 * we feed the in-service queue with new requests close to the
-+	 * last request served and, by doing so, hopefully increase the
-+	 * throughput.
-+	 */
-+	bfqq->new_bfqq = new_bfqq;
-+	new_bfqq->ref += process_refs;
-+	return new_bfqq;
-+}
-+
-+static bool bfq_may_be_close_cooperator(struct bfq_queue *bfqq,
-+					struct bfq_queue *new_bfqq)
-+{
-+	if (bfq_too_late_for_merging(new_bfqq)) {
-+		bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			     "too late for bfq%d to be merged",
-+				new_bfqq->pid);
-+		return false;
-+	}
-+
-+	if (bfq_class_idle(bfqq) || bfq_class_idle(new_bfqq) ||
-+	    (bfqq->ioprio_class != new_bfqq->ioprio_class))
-+		return false;
-+
-+	/*
-+	 * If either of the queues has already been detected as seeky,
-+	 * then merging it with the other queue is unlikely to lead to
-+	 * sequential I/O.
-+	 */
-+	if (BFQQ_SEEKY(bfqq) || BFQQ_SEEKY(new_bfqq))
-+		return false;
-+
-+	/*
-+	 * Interleaved I/O is known to be done by (some) applications
-+	 * only for reads, so it does not make sense to merge async
-+	 * queues.
-+	 */
-+	if (!bfq_bfqq_sync(bfqq) || !bfq_bfqq_sync(new_bfqq))
-+		return false;
-+
-+	return true;
-+}
-+
-+/*
-+ * Attempt to schedule a merge of bfqq with the currently in-service
-+ * queue or with a close queue among the scheduled queues.  Return
-+ * NULL if no merge was scheduled, a pointer to the shared bfq_queue
-+ * structure otherwise.
-+ *
-+ * The OOM queue is not allowed to participate to cooperation: in fact, since
-+ * the requests temporarily redirected to the OOM queue could be redirected
-+ * again to dedicated queues at any time, the state needed to correctly
-+ * handle merging with the OOM queue would be quite complex and expensive
-+ * to maintain. Besides, in such a critical condition as an out of memory,
-+ * the benefits of queue merging may be little relevant, or even negligible.
-+ *
-+ * WARNING: queue merging may impair fairness among non-weight raised
-+ * queues, for at least two reasons: 1) the original weight of a
-+ * merged queue may change during the merged state, 2) even being the
-+ * weight the same, a merged queue may be bloated with many more
-+ * requests than the ones produced by its originally-associated
-+ * process.
-+ */
-+static struct bfq_queue *
-+bfq_setup_cooperator(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+		     void *io_struct, bool request)
-+{
-+	struct bfq_queue *in_service_bfqq, *new_bfqq;
-+
-+	/*
-+	 * Prevent bfqq from being merged if it has been created too
-+	 * long ago. The idea is that true cooperating processes, and
-+	 * thus their associated bfq_queues, are supposed to be
-+	 * created shortly after each other. This is the case, e.g.,
-+	 * for KVM/QEMU and dump I/O threads. Basing on this
-+	 * assumption, the following filtering greatly reduces the
-+	 * probability that two non-cooperating processes, which just
-+	 * happen to do close I/O for some short time interval, have
-+	 * their queues merged by mistake.
-+	 */
-+	if (bfq_too_late_for_merging(bfqq)) {
-+		bfq_log_bfqq(bfqd, bfqq,
-+			     "would have looked for coop, but too late");
-+		return NULL;
-+	}
-+
-+	if (bfqq->new_bfqq)
-+		return bfqq->new_bfqq;
-+
-+	if (!io_struct || unlikely(bfqq == &bfqd->oom_bfqq))
-+		return NULL;
-+
-+	/* If there is only one backlogged queue, don't search. */
-+	if (bfqd->busy_queues == 1)
-+		return NULL;
-+
-+	in_service_bfqq = bfqd->in_service_queue;
-+
-+	if (in_service_bfqq && in_service_bfqq != bfqq &&
-+	    likely(in_service_bfqq != &bfqd->oom_bfqq) &&
-+	    bfq_rq_close_to_sector(io_struct, request, bfqd->last_position) &&
-+	    bfqq->entity.parent == in_service_bfqq->entity.parent &&
-+	    bfq_may_be_close_cooperator(bfqq, in_service_bfqq)) {
-+		new_bfqq = bfq_setup_merge(bfqq, in_service_bfqq);
-+		if (new_bfqq)
-+			return new_bfqq;
-+	}
-+	/*
-+	 * Check whether there is a cooperator among currently scheduled
-+	 * queues. The only thing we need is that the bio/request is not
-+	 * NULL, as we need it to establish whether a cooperator exists.
-+	 */
-+	new_bfqq = bfq_find_close_cooperator(bfqd, bfqq,
-+			bfq_io_struct_pos(io_struct, request));
-+
-+	BUG_ON(new_bfqq && bfqq->entity.parent != new_bfqq->entity.parent);
-+
-+	if (new_bfqq && likely(new_bfqq != &bfqd->oom_bfqq) &&
-+	    bfq_may_be_close_cooperator(bfqq, new_bfqq))
-+		return bfq_setup_merge(bfqq, new_bfqq);
-+
-+	return NULL;
-+}
-+
-+static void bfq_bfqq_save_state(struct bfq_queue *bfqq)
-+{
-+	struct bfq_io_cq *bic = bfqq->bic;
-+
-+	/*
-+	 * If !bfqq->bic, the queue is already shared or its requests
-+	 * have already been redirected to a shared queue; both idle window
-+	 * and weight raising state have already been saved. Do nothing.
-+	 */
-+	if (!bic)
-+		return;
-+
-+	bic->saved_has_short_ttime = bfq_bfqq_has_short_ttime(bfqq);
-+	bic->saved_IO_bound = bfq_bfqq_IO_bound(bfqq);
-+	bic->saved_in_large_burst = bfq_bfqq_in_large_burst(bfqq);
-+	bic->was_in_burst_list = !hlist_unhashed(&bfqq->burst_list_node);
-+	if (unlikely(bfq_bfqq_just_created(bfqq) &&
-+		     !bfq_bfqq_in_large_burst(bfqq) &&
-+		     bfqq->bfqd->low_latency)) {
-+		/*
-+		 * bfqq being merged ritgh after being created: bfqq
-+		 * would have deserved interactive weight raising, but
-+		 * did not make it to be set in a weight-raised state,
-+		 * because of this early merge.	Store directly the
-+		 * weight-raising state that would have been assigned
-+		 * to bfqq, so that to avoid that bfqq unjustly fails
-+		 * to enjoy weight raising if split soon.
-+		 */
-+		bic->saved_wr_coeff = bfqq->bfqd->bfq_wr_coeff;
-+		bic->saved_wr_cur_max_time = bfq_wr_duration(bfqq->bfqd);
-+		bic->saved_last_wr_start_finish = jiffies;
-+	} else {
-+		bic->saved_wr_coeff = bfqq->wr_coeff;
-+		bic->saved_wr_start_at_switch_to_srt =
-+			bfqq->wr_start_at_switch_to_srt;
-+		bic->saved_last_wr_start_finish = bfqq->last_wr_start_finish;
-+		bic->saved_wr_cur_max_time = bfqq->wr_cur_max_time;
-+	}
-+	BUG_ON(time_is_after_jiffies(bfqq->last_wr_start_finish));
-+}
-+
-+static void bfq_get_bic_reference(struct bfq_queue *bfqq)
-+{
-+	/*
-+	 * If bfqq->bic has a non-NULL value, the bic to which it belongs
-+	 * is about to begin using a shared bfq_queue.
-+	 */
-+	if (bfqq->bic)
-+		atomic_long_inc(&bfqq->bic->icq.ioc->refcount);
-+}
-+
-+static void
-+bfq_merge_bfqqs(struct bfq_data *bfqd, struct bfq_io_cq *bic,
-+		struct bfq_queue *bfqq, struct bfq_queue *new_bfqq)
-+{
-+	bfq_log_bfqq(bfqd, bfqq, "merging with queue %lu",
-+		     (unsigned long) new_bfqq->pid);
-+	/* Save weight raising and idle window of the merged queues */
-+	bfq_bfqq_save_state(bfqq);
-+	bfq_bfqq_save_state(new_bfqq);
-+	if (bfq_bfqq_IO_bound(bfqq))
-+		bfq_mark_bfqq_IO_bound(new_bfqq);
-+	bfq_clear_bfqq_IO_bound(bfqq);
-+
-+	/*
-+	 * If bfqq is weight-raised, then let new_bfqq inherit
-+	 * weight-raising. To reduce false positives, neglect the case
-+	 * where bfqq has just been created, but has not yet made it
-+	 * to be weight-raised (which may happen because EQM may merge
-+	 * bfqq even before bfq_add_request is executed for the first
-+	 * time for bfqq). Handling this case would however be very
-+	 * easy, thanks to the flag just_created.
-+	 */
-+	if (new_bfqq->wr_coeff == 1 && bfqq->wr_coeff > 1) {
-+		new_bfqq->wr_coeff = bfqq->wr_coeff;
-+		new_bfqq->wr_cur_max_time = bfqq->wr_cur_max_time;
-+		new_bfqq->last_wr_start_finish = bfqq->last_wr_start_finish;
-+		new_bfqq->wr_start_at_switch_to_srt =
-+			bfqq->wr_start_at_switch_to_srt;
-+		if (bfq_bfqq_busy(new_bfqq)) {
-+			bfqd->wr_busy_queues++;
-+			BUG_ON(bfqd->wr_busy_queues > bfqd->busy_queues);
-+		}
-+
-+		new_bfqq->entity.prio_changed = 1;
-+		bfq_log_bfqq(bfqd, new_bfqq,
-+			     "wr start after merge with %d, rais_max_time %u",
-+			     bfqq->pid,
-+			     jiffies_to_msecs(bfqq->wr_cur_max_time));
-+	}
-+
-+	if (bfqq->wr_coeff > 1) { /* bfqq has given its wr to new_bfqq */
-+		bfqq->wr_coeff = 1;
-+		bfqq->entity.prio_changed = 1;
-+		if (bfq_bfqq_busy(bfqq)) {
-+			bfqd->wr_busy_queues--;
-+			BUG_ON(bfqd->wr_busy_queues < 0);
-+		}
-+
-+	}
-+
-+	bfq_log_bfqq(bfqd, new_bfqq, "wr_busy %d",
-+		     bfqd->wr_busy_queues);
-+
-+	/*
-+	 * Grab a reference to the bic, to prevent it from being destroyed
-+	 * before being possibly touched by a bfq_split_bfqq().
-+	 */
-+	bfq_get_bic_reference(bfqq);
-+	bfq_get_bic_reference(new_bfqq);
-+	/*
-+	 * Merge queues (that is, let bic redirect its requests to new_bfqq)
-+	 */
-+	bic_set_bfqq(bic, new_bfqq, 1);
-+	bfq_mark_bfqq_coop(new_bfqq);
-+	/*
-+	 * new_bfqq now belongs to at least two bics (it is a shared queue):
-+	 * set new_bfqq->bic to NULL. bfqq either:
-+	 * - does not belong to any bic any more, and hence bfqq->bic must
-+	 *   be set to NULL, or
-+	 * - is a queue whose owning bics have already been redirected to a
-+	 *   different queue, hence the queue is destined to not belong to
-+	 *   any bic soon and bfqq->bic is already NULL (therefore the next
-+	 *   assignment causes no harm).
-+	 */
-+	new_bfqq->bic = NULL;
-+	bfqq->bic = NULL;
-+	/* release process reference to bfqq */
-+	bfq_put_queue(bfqq);
-+}
-+
-+static int bfq_allow_bio_merge(struct request_queue *q, struct request *rq,
-+			       struct bio *bio)
-+{
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+	bool is_sync = op_is_sync(bio->bi_opf);
-+	struct bfq_io_cq *bic;
-+	struct bfq_queue *bfqq, *new_bfqq;
-+
-+	/*
-+	 * Disallow merge of a sync bio into an async request.
-+	 */
-+	if (is_sync && !rq_is_sync(rq))
-+		return false;
-+
-+	/*
-+	 * Lookup the bfqq that this bio will be queued with. Allow
-+	 * merge only if rq is queued there.
-+	 * Queue lock is held here.
-+	 */
-+	bic = bfq_bic_lookup(bfqd, current->io_context);
-+	if (!bic)
-+		return false;
-+
-+	bfqq = bic_to_bfqq(bic, is_sync);
-+	/*
-+	 * We take advantage of this function to perform an early merge
-+	 * of the queues of possible cooperating processes.
-+	 */
-+	if (bfqq) {
-+		new_bfqq = bfq_setup_cooperator(bfqd, bfqq, bio, false);
-+		if (new_bfqq) {
-+			bfq_merge_bfqqs(bfqd, bic, bfqq, new_bfqq);
-+			/*
-+			 * If we get here, the bio will be queued in the
-+			 * shared queue, i.e., new_bfqq, so use new_bfqq
-+			 * to decide whether bio and rq can be merged.
-+			 */
-+			bfqq = new_bfqq;
-+		}
-+	}
-+
-+	return bfqq == RQ_BFQQ(rq);
-+}
-+
-+static int bfq_allow_rq_merge(struct request_queue *q, struct request *rq,
-+			      struct request *next)
-+{
-+	return RQ_BFQQ(rq) == RQ_BFQQ(next);
-+}
-+
-+/*
-+ * Set the maximum time for the in-service queue to consume its
-+ * budget. This prevents seeky processes from lowering the throughput.
-+ * In practice, a time-slice service scheme is used with seeky
-+ * processes.
-+ */
-+static void bfq_set_budget_timeout(struct bfq_data *bfqd,
-+				   struct bfq_queue *bfqq)
-+{
-+	unsigned int timeout_coeff;
-+
-+	if (bfqq->wr_cur_max_time == bfqd->bfq_wr_rt_max_time)
-+		timeout_coeff = 1;
-+	else
-+		timeout_coeff = bfqq->entity.weight / bfqq->entity.orig_weight;
-+
-+	bfqd->last_budget_start = ktime_get();
-+
-+	bfqq->budget_timeout = jiffies +
-+		bfqd->bfq_timeout * timeout_coeff;
-+
-+	bfq_log_bfqq(bfqd, bfqq, "%u",
-+		jiffies_to_msecs(bfqd->bfq_timeout * timeout_coeff));
-+}
-+
-+static void __bfq_set_in_service_queue(struct bfq_data *bfqd,
-+				       struct bfq_queue *bfqq)
-+{
-+	if (bfqq) {
-+		bfqg_stats_update_avg_queue_size(bfqq_group(bfqq));
-+		bfq_mark_bfqq_must_alloc(bfqq);
-+		bfq_clear_bfqq_fifo_expire(bfqq);
-+
-+		bfqd->budgets_assigned = (bfqd->budgets_assigned*7 + 256) / 8;
-+
-+		BUG_ON(bfqq == bfqd->in_service_queue);
-+		BUG_ON(RB_EMPTY_ROOT(&bfqq->sort_list));
-+
-+		if (time_is_before_jiffies(bfqq->last_wr_start_finish) &&
-+		    bfqq->wr_coeff > 1 &&
-+		    bfqq->wr_cur_max_time == bfqd->bfq_wr_rt_max_time &&
-+		    time_is_before_jiffies(bfqq->budget_timeout)) {
-+			/*
-+			 * For soft real-time queues, move the start
-+			 * of the weight-raising period forward by the
-+			 * time the queue has not received any
-+			 * service. Otherwise, a relatively long
-+			 * service delay is likely to cause the
-+			 * weight-raising period of the queue to end,
-+			 * because of the short duration of the
-+			 * weight-raising period of a soft real-time
-+			 * queue.  It is worth noting that this move
-+			 * is not so dangerous for the other queues,
-+			 * because soft real-time queues are not
-+			 * greedy.
-+			 *
-+			 * To not add a further variable, we use the
-+			 * overloaded field budget_timeout to
-+			 * determine for how long the queue has not
-+			 * received service, i.e., how much time has
-+			 * elapsed since the queue expired. However,
-+			 * this is a little imprecise, because
-+			 * budget_timeout is set to jiffies if bfqq
-+			 * not only expires, but also remains with no
-+			 * request.
-+			 */
-+			if (time_after(bfqq->budget_timeout,
-+				       bfqq->last_wr_start_finish))
-+				bfqq->last_wr_start_finish +=
-+					jiffies - bfqq->budget_timeout;
-+			else
-+				bfqq->last_wr_start_finish = jiffies;
-+
-+			if (time_is_after_jiffies(bfqq->last_wr_start_finish)) {
-+			       pr_crit(
-+			       "BFQ WARNING:last %lu budget %lu jiffies %lu",
-+			       bfqq->last_wr_start_finish,
-+			       bfqq->budget_timeout,
-+			       jiffies);
-+			       pr_crit("diff %lu", jiffies -
-+				       max_t(unsigned long,
-+					     bfqq->last_wr_start_finish,
-+					     bfqq->budget_timeout));
-+			       bfqq->last_wr_start_finish = jiffies;
-+			}
-+		}
-+
-+		bfq_set_budget_timeout(bfqd, bfqq);
-+		bfq_log_bfqq(bfqd, bfqq,
-+			     "cur-budget = %d",
-+			     bfqq->entity.budget);
-+	} else
-+		bfq_log(bfqd, "NULL");
-+
-+	bfqd->in_service_queue = bfqq;
-+}
-+
-+/*
-+ * Get and set a new queue for service.
-+ */
-+static struct bfq_queue *bfq_set_in_service_queue(struct bfq_data *bfqd)
-+{
-+	struct bfq_queue *bfqq = bfq_get_next_queue(bfqd);
-+
-+	__bfq_set_in_service_queue(bfqd, bfqq);
-+	return bfqq;
-+}
-+
-+static void bfq_arm_slice_timer(struct bfq_data *bfqd)
-+{
-+	struct bfq_queue *bfqq = bfqd->in_service_queue;
-+	struct bfq_io_cq *bic;
-+	u32 sl;
-+
-+	BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list));
-+
-+	/* Processes have exited, don't wait. */
-+	bic = bfqd->in_service_bic;
-+	if (!bic || atomic_read(&bic->icq.ioc->active_ref) == 0)
-+		return;
-+
-+	bfq_mark_bfqq_wait_request(bfqq);
-+
-+	/*
-+	 * We don't want to idle for seeks, but we do want to allow
-+	 * fair distribution of slice time for a process doing back-to-back
-+	 * seeks. So allow a little bit of time for him to submit a new rq.
-+	 *
-+	 * To prevent processes with (partly) seeky workloads from
-+	 * being too ill-treated, grant them a small fraction of the
-+	 * assigned budget before reducing the waiting time to
-+	 * BFQ_MIN_TT. This happened to help reduce latency.
-+	 */
-+	sl = bfqd->bfq_slice_idle;
-+	/*
-+	 * Unless the queue is being weight-raised or the scenario is
-+	 * asymmetric, grant only minimum idle time if the queue
-+	 * is seeky. A long idling is preserved for a weight-raised
-+	 * queue, or, more in general, in an asymemtric scenario,
-+	 * because a long idling is needed for guaranteeing to a queue
-+	 * its reserved share of the throughput (in particular, it is
-+	 * needed if the queue has a higher weight than some other
-+	 * queue).
-+	 */
-+	if (BFQQ_SEEKY(bfqq) && bfqq->wr_coeff == 1 &&
-+	    bfq_symmetric_scenario(bfqd))
-+		sl = min_t(u32, sl, BFQ_MIN_TT);
-+
-+	bfqd->last_idling_start = ktime_get();
-+	hrtimer_start(&bfqd->idle_slice_timer, ns_to_ktime(sl),
-+		      HRTIMER_MODE_REL);
-+	bfqg_stats_set_start_idle_time(bfqq_group(bfqq));
-+	bfq_log(bfqd, "arm idle: %ld/%ld ms",
-+		sl / NSEC_PER_MSEC, bfqd->bfq_slice_idle / NSEC_PER_MSEC);
-+}
-+
-+/*
-+ * In autotuning mode, max_budget is dynamically recomputed as the
-+ * amount of sectors transferred in timeout at the estimated peak
-+ * rate. This enables BFQ to utilize a full timeslice with a full
-+ * budget, even if the in-service queue is served at peak rate. And
-+ * this maximises throughput with sequential workloads.
-+ */
-+static unsigned long bfq_calc_max_budget(struct bfq_data *bfqd)
-+{
-+	return (u64)bfqd->peak_rate * USEC_PER_MSEC *
-+		jiffies_to_msecs(bfqd->bfq_timeout)>>BFQ_RATE_SHIFT;
-+}
-+
-+/*
-+ * Update parameters related to throughput and responsiveness, as a
-+ * function of the estimated peak rate. See comments on
-+ * bfq_calc_max_budget(), and on the ref_wr_duration array.
-+ */
-+static void update_thr_responsiveness_params(struct bfq_data *bfqd)
-+{
-+	if (bfqd->bfq_user_max_budget == 0) {
-+		bfqd->bfq_max_budget =
-+			bfq_calc_max_budget(bfqd);
-+		BUG_ON(bfqd->bfq_max_budget < 0);
-+		bfq_log(bfqd, "new max_budget = %d",
-+			bfqd->bfq_max_budget);
-+	}
-+}
-+
-+static void bfq_reset_rate_computation(struct bfq_data *bfqd, struct request *rq)
-+{
-+	if (rq != NULL) { /* new rq dispatch now, reset accordingly */
-+		bfqd->last_dispatch = bfqd->first_dispatch = ktime_get_ns() ;
-+		bfqd->peak_rate_samples = 1;
-+		bfqd->sequential_samples = 0;
-+		bfqd->tot_sectors_dispatched = bfqd->last_rq_max_size =
-+			blk_rq_sectors(rq);
-+	} else /* no new rq dispatched, just reset the number of samples */
-+		bfqd->peak_rate_samples = 0; /* full re-init on next disp. */
-+
-+	bfq_log(bfqd,
-+		"at end, sample %u/%u tot_sects %llu",
-+		bfqd->peak_rate_samples, bfqd->sequential_samples,
-+		bfqd->tot_sectors_dispatched);
-+}
-+
-+static void bfq_update_rate_reset(struct bfq_data *bfqd, struct request *rq)
-+{
-+	u32 rate, weight, divisor;
-+
-+	/*
-+	 * For the convergence property to hold (see comments on
-+	 * bfq_update_peak_rate()) and for the assessment to be
-+	 * reliable, a minimum number of samples must be present, and
-+	 * a minimum amount of time must have elapsed. If not so, do
-+	 * not compute new rate. Just reset parameters, to get ready
-+	 * for a new evaluation attempt.
-+	 */
-+	if (bfqd->peak_rate_samples < BFQ_RATE_MIN_SAMPLES ||
-+	    bfqd->delta_from_first < BFQ_RATE_MIN_INTERVAL) {
-+		bfq_log(bfqd,
-+	"only resetting, delta_first %lluus samples %d",
-+			bfqd->delta_from_first>>10, bfqd->peak_rate_samples);
-+		goto reset_computation;
-+	}
-+
-+	/*
-+	 * If a new request completion has occurred after last
-+	 * dispatch, then, to approximate the rate at which requests
-+	 * have been served by the device, it is more precise to
-+	 * extend the observation interval to the last completion.
-+	 */
-+	bfqd->delta_from_first =
-+		max_t(u64, bfqd->delta_from_first,
-+		      bfqd->last_completion - bfqd->first_dispatch);
-+
-+	BUG_ON(bfqd->delta_from_first == 0);
-+	/*
-+	 * Rate computed in sects/usec, and not sects/nsec, for
-+	 * precision issues.
-+	 */
-+	rate = div64_ul(bfqd->tot_sectors_dispatched<<BFQ_RATE_SHIFT,
-+			div_u64(bfqd->delta_from_first, NSEC_PER_USEC));
-+
-+	bfq_log(bfqd,
-+"tot_sects %llu delta_first %lluus rate %llu sects/s (%d)",
-+		bfqd->tot_sectors_dispatched, bfqd->delta_from_first>>10,
-+		((USEC_PER_SEC*(u64)rate)>>BFQ_RATE_SHIFT),
-+		rate > 20<<BFQ_RATE_SHIFT);
-+
-+	/*
-+	 * Peak rate not updated if:
-+	 * - the percentage of sequential dispatches is below 3/4 of the
-+	 *   total, and rate is below the current estimated peak rate
-+	 * - rate is unreasonably high (> 20M sectors/sec)
-+	 */
-+	if ((bfqd->sequential_samples < (3 * bfqd->peak_rate_samples)>>2 &&
-+	     rate <= bfqd->peak_rate) ||
-+		rate > 20<<BFQ_RATE_SHIFT) {
-+		bfq_log(bfqd,
-+		"goto reset, samples %u/%u rate/peak %llu/%llu",
-+		bfqd->peak_rate_samples, bfqd->sequential_samples,
-+		((USEC_PER_SEC*(u64)rate)>>BFQ_RATE_SHIFT),
-+		((USEC_PER_SEC*(u64)bfqd->peak_rate)>>BFQ_RATE_SHIFT));
-+		goto reset_computation;
-+	} else {
-+		bfq_log(bfqd,
-+		"do update, samples %u/%u rate/peak %llu/%llu",
-+		bfqd->peak_rate_samples, bfqd->sequential_samples,
-+		((USEC_PER_SEC*(u64)rate)>>BFQ_RATE_SHIFT),
-+		((USEC_PER_SEC*(u64)bfqd->peak_rate)>>BFQ_RATE_SHIFT));
-+	}
-+
-+	/*
-+	 * We have to update the peak rate, at last! To this purpose,
-+	 * we use a low-pass filter. We compute the smoothing constant
-+	 * of the filter as a function of the 'weight' of the new
-+	 * measured rate.
-+	 *
-+	 * As can be seen in next formulas, we define this weight as a
-+	 * quantity proportional to how sequential the workload is,
-+	 * and to how long the observation time interval is.
-+	 *
-+	 * The weight runs from 0 to 8. The maximum value of the
-+	 * weight, 8, yields the minimum value for the smoothing
-+	 * constant. At this minimum value for the smoothing constant,
-+	 * the measured rate contributes for half of the next value of
-+	 * the estimated peak rate.
-+	 *
-+	 * So, the first step is to compute the weight as a function
-+	 * of how sequential the workload is. Note that the weight
-+	 * cannot reach 9, because bfqd->sequential_samples cannot
-+	 * become equal to bfqd->peak_rate_samples, which, in its
-+	 * turn, holds true because bfqd->sequential_samples is not
-+	 * incremented for the first sample.
-+	 */
-+	weight = (9 * bfqd->sequential_samples) / bfqd->peak_rate_samples;
-+
-+	/*
-+	 * Second step: further refine the weight as a function of the
-+	 * duration of the observation interval.
-+	 */
-+	weight = min_t(u32, 8,
-+		       div_u64(weight * bfqd->delta_from_first,
-+			       BFQ_RATE_REF_INTERVAL));
-+
-+	/*
-+	 * Divisor ranging from 10, for minimum weight, to 2, for
-+	 * maximum weight.
-+	 */
-+	divisor = 10 - weight;
-+	BUG_ON(divisor == 0);
-+
-+	/*
-+	 * Finally, update peak rate:
-+	 *
-+	 * peak_rate = peak_rate * (divisor-1) / divisor  +  rate / divisor
-+	 */
-+	bfqd->peak_rate *= divisor-1;
-+	bfqd->peak_rate /= divisor;
-+	rate /= divisor; /* smoothing constant alpha = 1/divisor */
-+
-+	bfq_log(bfqd,
-+		"divisor %d tmp_peak_rate %llu tmp_rate %u",
-+		divisor,
-+		((USEC_PER_SEC*(u64)bfqd->peak_rate)>>BFQ_RATE_SHIFT),
-+		(u32)((USEC_PER_SEC*(u64)rate)>>BFQ_RATE_SHIFT));
-+
-+	BUG_ON(bfqd->peak_rate == 0);
-+	BUG_ON(bfqd->peak_rate > 20<<BFQ_RATE_SHIFT);
-+
-+	bfqd->peak_rate += rate;
-+
-+	/*
-+	 * For a very slow device, bfqd->peak_rate can reach 0 (see
-+	 * the minimum representable values reported in the comments
-+	 * on BFQ_RATE_SHIFT). Push to 1 if this happens, to avoid
-+	 * divisions by zero where bfqd->peak_rate is used as a
-+	 * divisor.
-+	 */
-+	bfqd->peak_rate = max_t(u32, 1, bfqd->peak_rate);
-+
-+	update_thr_responsiveness_params(bfqd);
-+	BUG_ON(bfqd->peak_rate > 20<<BFQ_RATE_SHIFT);
-+
-+reset_computation:
-+	bfq_reset_rate_computation(bfqd, rq);
-+}
-+
-+/*
-+ * Update the read/write peak rate (the main quantity used for
-+ * auto-tuning, see update_thr_responsiveness_params()).
-+ *
-+ * It is not trivial to estimate the peak rate (correctly): because of
-+ * the presence of sw and hw queues between the scheduler and the
-+ * device components that finally serve I/O requests, it is hard to
-+ * say exactly when a given dispatched request is served inside the
-+ * device, and for how long. As a consequence, it is hard to know
-+ * precisely at what rate a given set of requests is actually served
-+ * by the device.
-+ *
-+ * On the opposite end, the dispatch time of any request is trivially
-+ * available, and, from this piece of information, the "dispatch rate"
-+ * of requests can be immediately computed. So, the idea in the next
-+ * function is to use what is known, namely request dispatch times
-+ * (plus, when useful, request completion times), to estimate what is
-+ * unknown, namely in-device request service rate.
-+ *
-+ * The main issue is that, because of the above facts, the rate at
-+ * which a certain set of requests is dispatched over a certain time
-+ * interval can vary greatly with respect to the rate at which the
-+ * same requests are then served. But, since the size of any
-+ * intermediate queue is limited, and the service scheme is lossless
-+ * (no request is silently dropped), the following obvious convergence
-+ * property holds: the number of requests dispatched MUST become
-+ * closer and closer to the number of requests completed as the
-+ * observation interval grows. This is the key property used in
-+ * the next function to estimate the peak service rate as a function
-+ * of the observed dispatch rate. The function assumes to be invoked
-+ * on every request dispatch.
-+ */
-+static void bfq_update_peak_rate(struct bfq_data *bfqd, struct request *rq)
-+{
-+	u64 now_ns = ktime_get_ns();
-+
-+	if (bfqd->peak_rate_samples == 0) { /* first dispatch */
-+		bfq_log(bfqd,
-+		"goto reset, samples %d",
-+				bfqd->peak_rate_samples) ;
-+		bfq_reset_rate_computation(bfqd, rq);
-+		goto update_last_values; /* will add one sample */
-+	}
-+
-+	/*
-+	 * Device idle for very long: the observation interval lasting
-+	 * up to this dispatch cannot be a valid observation interval
-+	 * for computing a new peak rate (similarly to the late-
-+	 * completion event in bfq_completed_request()). Go to
-+	 * update_rate_and_reset to have the following three steps
-+	 * taken:
-+	 * - close the observation interval at the last (previous)
-+	 *   request dispatch or completion
-+	 * - compute rate, if possible, for that observation interval
-+	 * - start a new observation interval with this dispatch
-+	 */
-+	if (now_ns - bfqd->last_dispatch > 100*NSEC_PER_MSEC &&
-+	    bfqd->rq_in_driver == 0) {
-+		bfq_log(bfqd,
-+"jumping to updating&resetting delta_last %lluus samples %d",
-+			(now_ns - bfqd->last_dispatch)>>10,
-+			bfqd->peak_rate_samples) ;
-+		goto update_rate_and_reset;
-+	}
-+
-+	/* Update sampling information */
-+	bfqd->peak_rate_samples++;
-+
-+	if ((bfqd->rq_in_driver > 0 ||
-+		now_ns - bfqd->last_completion < BFQ_MIN_TT)
-+	     && get_sdist(bfqd->last_position, rq) < BFQQ_SEEK_THR)
-+		bfqd->sequential_samples++;
-+
-+	bfqd->tot_sectors_dispatched += blk_rq_sectors(rq);
-+
-+	/* Reset max observed rq size every 32 dispatches */
-+	if (likely(bfqd->peak_rate_samples % 32))
-+		bfqd->last_rq_max_size =
-+			max_t(u32, blk_rq_sectors(rq), bfqd->last_rq_max_size);
-+	else
-+		bfqd->last_rq_max_size = blk_rq_sectors(rq);
-+
-+	bfqd->delta_from_first = now_ns - bfqd->first_dispatch;
-+
-+	bfq_log(bfqd,
-+	"added samples %u/%u tot_sects %llu delta_first %lluus",
-+		bfqd->peak_rate_samples, bfqd->sequential_samples,
-+		bfqd->tot_sectors_dispatched,
-+		bfqd->delta_from_first>>10);
-+
-+	/* Target observation interval not yet reached, go on sampling */
-+	if (bfqd->delta_from_first < BFQ_RATE_REF_INTERVAL)
-+		goto update_last_values;
-+
-+update_rate_and_reset:
-+	bfq_update_rate_reset(bfqd, rq);
-+update_last_values:
-+	bfqd->last_position = blk_rq_pos(rq) + blk_rq_sectors(rq);
-+	bfqd->last_dispatch = now_ns;
-+
-+	bfq_log(bfqd,
-+	"delta_first %lluus last_pos %llu peak_rate %llu",
-+		(now_ns - bfqd->first_dispatch)>>10,
-+		(unsigned long long) bfqd->last_position,
-+		((USEC_PER_SEC*(u64)bfqd->peak_rate)>>BFQ_RATE_SHIFT));
-+	bfq_log(bfqd,
-+	"samples at end %d", bfqd->peak_rate_samples);
-+}
-+
-+/*
-+ * Move request from internal lists to the dispatch list of the request queue
-+ */
-+static void bfq_dispatch_insert(struct request_queue *q, struct request *rq)
-+{
-+	struct bfq_queue *bfqq = RQ_BFQQ(rq);
-+
-+	/*
-+	 * For consistency, the next instruction should have been executed
-+	 * after removing the request from the queue and dispatching it.
-+	 * We execute instead this instruction before bfq_remove_request()
-+	 * (and hence introduce a temporary inconsistency), for efficiency.
-+	 * In fact, in a forced_dispatch, this prevents two counters related
-+	 * to bfqq->dispatched to risk to be uselessly decremented if bfqq
-+	 * is not in service, and then to be incremented again after
-+	 * incrementing bfqq->dispatched.
-+	 */
-+	bfqq->dispatched++;
-+	bfq_update_peak_rate(q->elevator->elevator_data, rq);
-+
-+	bfq_remove_request(rq);
-+	elv_dispatch_sort(q, rq);
-+}
-+
-+static void __bfq_bfqq_expire(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	BUG_ON(bfqq != bfqd->in_service_queue);
-+
-+	/*
-+	 * If this bfqq is shared between multiple processes, check
-+	 * to make sure that those processes are still issuing I/Os
-+	 * within the mean seek distance. If not, it may be time to
-+	 * break the queues apart again.
-+	 */
-+	if (bfq_bfqq_coop(bfqq) && BFQQ_SEEKY(bfqq))
-+		bfq_mark_bfqq_split_coop(bfqq);
-+
-+	if (RB_EMPTY_ROOT(&bfqq->sort_list)) {
-+		if (bfqq->dispatched == 0)
-+			/*
-+			 * Overloading budget_timeout field to store
-+			 * the time at which the queue remains with no
-+			 * backlog and no outstanding request; used by
-+			 * the weight-raising mechanism.
-+			 */
-+			bfqq->budget_timeout = jiffies;
-+
-+		bfq_del_bfqq_busy(bfqd, bfqq, true);
-+	} else {
-+		bfq_requeue_bfqq(bfqd, bfqq, true);
-+		/*
-+		 * Resort priority tree of potential close cooperators.
-+		 */
-+		bfq_pos_tree_add_move(bfqd, bfqq);
-+	}
-+
-+	/*
-+	 * All in-service entities must have been properly deactivated
-+	 * or requeued before executing the next function, which
-+	 * resets all in-service entites as no more in service.
-+	 */
-+	__bfq_bfqd_reset_in_service(bfqd);
-+}
-+
-+/**
-+ * __bfq_bfqq_recalc_budget - try to adapt the budget to the @bfqq behavior.
-+ * @bfqd: device data.
-+ * @bfqq: queue to update.
-+ * @reason: reason for expiration.
-+ *
-+ * Handle the feedback on @bfqq budget at queue expiration.
-+ * See the body for detailed comments.
-+ */
-+static void __bfq_bfqq_recalc_budget(struct bfq_data *bfqd,
-+				     struct bfq_queue *bfqq,
-+				     enum bfqq_expiration reason)
-+{
-+	struct request *next_rq;
-+	int budget, min_budget;
-+
-+	BUG_ON(bfqq != bfqd->in_service_queue);
-+
-+	min_budget = bfq_min_budget(bfqd);
-+
-+	if (bfqq->wr_coeff == 1)
-+		budget = bfqq->max_budget;
-+	else /*
-+	      * Use a constant, low budget for weight-raised queues,
-+	      * to help achieve a low latency. Keep it slightly higher
-+	      * than the minimum possible budget, to cause a little
-+	      * bit fewer expirations.
-+	      */
-+		budget = 2 * min_budget;
-+
-+	bfq_log_bfqq(bfqd, bfqq, "last budg %d, budg left %d",
-+		bfqq->entity.budget, bfq_bfqq_budget_left(bfqq));
-+	bfq_log_bfqq(bfqd, bfqq, "last max_budg %d, min budg %d",
-+		budget, bfq_min_budget(bfqd));
-+	bfq_log_bfqq(bfqd, bfqq, "sync %d, seeky %d",
-+		bfq_bfqq_sync(bfqq), BFQQ_SEEKY(bfqd->in_service_queue));
-+
-+	if (bfq_bfqq_sync(bfqq) && bfqq->wr_coeff == 1) {
-+		switch (reason) {
-+		/*
-+		 * Caveat: in all the following cases we trade latency
-+		 * for throughput.
-+		 */
-+		case BFQ_BFQQ_TOO_IDLE:
-+			/*
-+			 * This is the only case where we may reduce
-+			 * the budget: if there is no request of the
-+			 * process still waiting for completion, then
-+			 * we assume (tentatively) that the timer has
-+			 * expired because the batch of requests of
-+			 * the process could have been served with a
-+			 * smaller budget.  Hence, betting that
-+			 * process will behave in the same way when it
-+			 * becomes backlogged again, we reduce its
-+			 * next budget.  As long as we guess right,
-+			 * this budget cut reduces the latency
-+			 * experienced by the process.
-+			 *
-+			 * However, if there are still outstanding
-+			 * requests, then the process may have not yet
-+			 * issued its next request just because it is
-+			 * still waiting for the completion of some of
-+			 * the still outstanding ones.  So in this
-+			 * subcase we do not reduce its budget, on the
-+			 * contrary we increase it to possibly boost
-+			 * the throughput, as discussed in the
-+			 * comments to the BUDGET_TIMEOUT case.
-+			 */
-+			if (bfqq->dispatched > 0) /* still outstanding reqs */
-+				budget = min(budget * 2, bfqd->bfq_max_budget);
-+			else {
-+				if (budget > 5 * min_budget)
-+					budget -= 4 * min_budget;
-+				else
-+					budget = min_budget;
-+			}
-+			break;
-+		case BFQ_BFQQ_BUDGET_TIMEOUT:
-+			/*
-+			 * We double the budget here because it gives
-+			 * the chance to boost the throughput if this
-+			 * is not a seeky process (and has bumped into
-+			 * this timeout because of, e.g., ZBR).
-+			 */
-+			budget = min(budget * 2, bfqd->bfq_max_budget);
-+			break;
-+		case BFQ_BFQQ_BUDGET_EXHAUSTED:
-+			/*
-+			 * The process still has backlog, and did not
-+			 * let either the budget timeout or the disk
-+			 * idling timeout expire. Hence it is not
-+			 * seeky, has a short thinktime and may be
-+			 * happy with a higher budget too. So
-+			 * definitely increase the budget of this good
-+			 * candidate to boost the disk throughput.
-+			 */
-+			budget = min(budget * 4, bfqd->bfq_max_budget);
-+			break;
-+		case BFQ_BFQQ_NO_MORE_REQUESTS:
-+			/*
-+			 * For queues that expire for this reason, it
-+			 * is particularly important to keep the
-+			 * budget close to the actual service they
-+			 * need. Doing so reduces the timestamp
-+			 * misalignment problem described in the
-+			 * comments in the body of
-+			 * __bfq_activate_entity. In fact, suppose
-+			 * that a queue systematically expires for
-+			 * BFQ_BFQQ_NO_MORE_REQUESTS and presents a
-+			 * new request in time to enjoy timestamp
-+			 * back-shifting. The larger the budget of the
-+			 * queue is with respect to the service the
-+			 * queue actually requests in each service
-+			 * slot, the more times the queue can be
-+			 * reactivated with the same virtual finish
-+			 * time. It follows that, even if this finish
-+			 * time is pushed to the system virtual time
-+			 * to reduce the consequent timestamp
-+			 * misalignment, the queue unjustly enjoys for
-+			 * many re-activations a lower finish time
-+			 * than all newly activated queues.
-+			 *
-+			 * The service needed by bfqq is measured
-+			 * quite precisely by bfqq->entity.service.
-+			 * Since bfqq does not enjoy device idling,
-+			 * bfqq->entity.service is equal to the number
-+			 * of sectors that the process associated with
-+			 * bfqq requested to read/write before waiting
-+			 * for request completions, or blocking for
-+			 * other reasons.
-+			 */
-+			budget = max_t(int, bfqq->entity.service, min_budget);
-+			break;
-+		default:
-+			return;
-+		}
-+	} else if (!bfq_bfqq_sync(bfqq))
-+		/*
-+		 * Async queues get always the maximum possible
-+		 * budget, as for them we do not care about latency
-+		 * (in addition, their ability to dispatch is limited
-+		 * by the charging factor).
-+		 */
-+		budget = bfqd->bfq_max_budget;
-+
-+	bfqq->max_budget = budget;
-+
-+	if (bfqd->budgets_assigned >= bfq_stats_min_budgets &&
-+	    !bfqd->bfq_user_max_budget)
-+		bfqq->max_budget = min(bfqq->max_budget, bfqd->bfq_max_budget);
-+
-+	/*
-+	 * If there is still backlog, then assign a new budget, making
-+	 * sure that it is large enough for the next request.  Since
-+	 * the finish time of bfqq must be kept in sync with the
-+	 * budget, be sure to call __bfq_bfqq_expire() *after* this
-+	 * update.
-+	 *
-+	 * If there is no backlog, then no need to update the budget;
-+	 * it will be updated on the arrival of a new request.
-+	 */
-+	next_rq = bfqq->next_rq;
-+	if (next_rq) {
-+		BUG_ON(reason == BFQ_BFQQ_TOO_IDLE ||
-+		       reason == BFQ_BFQQ_NO_MORE_REQUESTS);
-+		bfqq->entity.budget = max_t(unsigned long, bfqq->max_budget,
-+					    bfq_serv_to_charge(next_rq, bfqq));
-+		BUG_ON(!bfq_bfqq_busy(bfqq));
-+		BUG_ON(RB_EMPTY_ROOT(&bfqq->sort_list));
-+	}
-+
-+	bfq_log_bfqq(bfqd, bfqq, "head sect: %u, new budget %d",
-+			next_rq ? blk_rq_sectors(next_rq) : 0,
-+			bfqq->entity.budget);
-+}
-+
-+/*
-+ * Return true if the process associated with bfqq is "slow". The slow
-+ * flag is used, in addition to the budget timeout, to reduce the
-+ * amount of service provided to seeky processes, and thus reduce
-+ * their chances to lower the throughput. More details in the comments
-+ * on the function bfq_bfqq_expire().
-+ *
-+ * An important observation is in order: as discussed in the comments
-+ * on the function bfq_update_peak_rate(), with devices with internal
-+ * queues, it is hard if ever possible to know when and for how long
-+ * an I/O request is processed by the device (apart from the trivial
-+ * I/O pattern where a new request is dispatched only after the
-+ * previous one has been completed). This makes it hard to evaluate
-+ * the real rate at which the I/O requests of each bfq_queue are
-+ * served.  In fact, for an I/O scheduler like BFQ, serving a
-+ * bfq_queue means just dispatching its requests during its service
-+ * slot (i.e., until the budget of the queue is exhausted, or the
-+ * queue remains idle, or, finally, a timeout fires). But, during the
-+ * service slot of a bfq_queue, around 100 ms at most, the device may
-+ * be even still processing requests of bfq_queues served in previous
-+ * service slots. On the opposite end, the requests of the in-service
-+ * bfq_queue may be completed after the service slot of the queue
-+ * finishes.
-+ *
-+ * Anyway, unless more sophisticated solutions are used
-+ * (where possible), the sum of the sizes of the requests dispatched
-+ * during the service slot of a bfq_queue is probably the only
-+ * approximation available for the service received by the bfq_queue
-+ * during its service slot. And this sum is the quantity used in this
-+ * function to evaluate the I/O speed of a process.
-+ */
-+static bool bfq_bfqq_is_slow(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+				 bool compensate, enum bfqq_expiration reason,
-+				 unsigned long *delta_ms)
-+{
-+	ktime_t delta_ktime;
-+	u32 delta_usecs;
-+	bool slow = BFQQ_SEEKY(bfqq); /* if delta too short, use seekyness */
-+
-+	if (!bfq_bfqq_sync(bfqq))
-+		return false;
-+
-+	if (compensate)
-+		delta_ktime = bfqd->last_idling_start;
-+	else
-+		delta_ktime = ktime_get();
-+	delta_ktime = ktime_sub(delta_ktime, bfqd->last_budget_start);
-+	delta_usecs = ktime_to_us(delta_ktime);
-+
-+	/* don't use too short time intervals */
-+	if (delta_usecs < 1000) {
-+		if (blk_queue_nonrot(bfqd->queue))
-+			 /*
-+			  * give same worst-case guarantees as idling
-+			  * for seeky
-+			  */
-+			*delta_ms = BFQ_MIN_TT / NSEC_PER_MSEC;
-+		else /* charge at least one seek */
-+			*delta_ms = bfq_slice_idle / NSEC_PER_MSEC;
-+
-+		bfq_log(bfqd, "too short %u", delta_usecs);
-+
-+		return slow;
-+	}
-+
-+	*delta_ms = delta_usecs / USEC_PER_MSEC;
-+
-+	/*
-+	 * Use only long (> 20ms) intervals to filter out excessive
-+	 * spikes in service rate estimation.
-+	 */
-+	if (delta_usecs > 20000) {
-+		/*
-+		 * Caveat for rotational devices: processes doing I/O
-+		 * in the slower disk zones tend to be slow(er) even
-+		 * if not seeky. In this respect, the estimated peak
-+		 * rate is likely to be an average over the disk
-+		 * surface. Accordingly, to not be too harsh with
-+		 * unlucky processes, a process is deemed slow only if
-+		 * its rate has been lower than half of the estimated
-+		 * peak rate.
-+		 */
-+		slow = bfqq->entity.service < bfqd->bfq_max_budget / 2;
-+		bfq_log(bfqd, "relative rate %d/%d",
-+			bfqq->entity.service, bfqd->bfq_max_budget);
-+	}
-+
-+	bfq_log_bfqq(bfqd, bfqq, "slow %d", slow);
-+
-+	return slow;
-+}
-+
-+/*
-+ * To be deemed as soft real-time, an application must meet two
-+ * requirements. First, the application must not require an average
-+ * bandwidth higher than the approximate bandwidth required to playback or
-+ * record a compressed high-definition video.
-+ * The next function is invoked on the completion of the last request of a
-+ * batch, to compute the next-start time instant, soft_rt_next_start, such
-+ * that, if the next request of the application does not arrive before
-+ * soft_rt_next_start, then the above requirement on the bandwidth is met.
-+ *
-+ * The second requirement is that the request pattern of the application is
-+ * isochronous, i.e., that, after issuing a request or a batch of requests,
-+ * the application stops issuing new requests until all its pending requests
-+ * have been completed. After that, the application may issue a new batch,
-+ * and so on.
-+ * For this reason the next function is invoked to compute
-+ * soft_rt_next_start only for applications that meet this requirement,
-+ * whereas soft_rt_next_start is set to infinity for applications that do
-+ * not.
-+ *
-+ * Unfortunately, even a greedy (i.e., I/O-bound) application may
-+ * happen to meet, occasionally or systematically, both the above
-+ * bandwidth and isochrony requirements. This may happen at least in
-+ * the following circumstances. First, if the CPU load is high. The
-+ * application may stop issuing requests while the CPUs are busy
-+ * serving other processes, then restart, then stop again for a while,
-+ * and so on. The other circumstances are related to the storage
-+ * device: the storage device is highly loaded or reaches a low-enough
-+ * throughput with the I/O of the application (e.g., because the I/O
-+ * is random and/or the device is slow). In all these cases, the
-+ * I/O of the application may be simply slowed down enough to meet
-+ * the bandwidth and isochrony requirements. To reduce the probability
-+ * that greedy applications are deemed as soft real-time in these
-+ * corner cases, a further rule is used in the computation of
-+ * soft_rt_next_start: the return value of this function is forced to
-+ * be higher than the maximum between the following two quantities.
-+ *
-+ * (a) Current time plus: (1) the maximum time for which the arrival
-+ *     of a request is waited for when a sync queue becomes idle,
-+ *     namely bfqd->bfq_slice_idle, and (2) a few extra jiffies. We
-+ *     postpone for a moment the reason for adding a few extra
-+ *     jiffies; we get back to it after next item (b).  Lower-bounding
-+ *     the return value of this function with the current time plus
-+ *     bfqd->bfq_slice_idle tends to filter out greedy applications,
-+ *     because the latter issue their next request as soon as possible
-+ *     after the last one has been completed. In contrast, a soft
-+ *     real-time application spends some time processing data, after a
-+ *     batch of its requests has been completed.
-+ *
-+ * (b) Current value of bfqq->soft_rt_next_start. As pointed out
-+ *     above, greedy applications may happen to meet both the
-+ *     bandwidth and isochrony requirements under heavy CPU or
-+ *     storage-device load. In more detail, in these scenarios, these
-+ *     applications happen, only for limited time periods, to do I/O
-+ *     slowly enough to meet all the requirements described so far,
-+ *     including the filtering in above item (a). These slow-speed
-+ *     time intervals are usually interspersed between other time
-+ *     intervals during which these applications do I/O at a very high
-+ *     speed. Fortunately, exactly because of the high speed of the
-+ *     I/O in the high-speed intervals, the values returned by this
-+ *     function happen to be so high, near the end of any such
-+ *     high-speed interval, to be likely to fall *after* the end of
-+ *     the low-speed time interval that follows. These high values are
-+ *     stored in bfqq->soft_rt_next_start after each invocation of
-+ *     this function. As a consequence, if the last value of
-+ *     bfqq->soft_rt_next_start is constantly used to lower-bound the
-+ *     next value that this function may return, then, from the very
-+ *     beginning of a low-speed interval, bfqq->soft_rt_next_start is
-+ *     likely to be constantly kept so high that any I/O request
-+ *     issued during the low-speed interval is considered as arriving
-+ *     to soon for the application to be deemed as soft
-+ *     real-time. Then, in the high-speed interval that follows, the
-+ *     application will not be deemed as soft real-time, just because
-+ *     it will do I/O at a high speed. And so on.
-+ *
-+ * Getting back to the filtering in item (a), in the following two
-+ * cases this filtering might be easily passed by a greedy
-+ * application, if the reference quantity was just
-+ * bfqd->bfq_slice_idle:
-+ * 1) HZ is so low that the duration of a jiffy is comparable to or
-+ *    higher than bfqd->bfq_slice_idle. This happens, e.g., on slow
-+ *    devices with HZ=100. The time granularity may be so coarse
-+ *    that the approximation, in jiffies, of bfqd->bfq_slice_idle
-+ *    is rather lower than the exact value.
-+ * 2) jiffies, instead of increasing at a constant rate, may stop increasing
-+ *    for a while, then suddenly 'jump' by several units to recover the lost
-+ *    increments. This seems to happen, e.g., inside virtual machines.
-+ * To address this issue, in the filtering in (a) we do not use as a
-+ * reference time interval just bfqd->bfq_slice_idle, but
-+ * bfqd->bfq_slice_idle plus a few jiffies. In particular, we add the
-+ * minimum number of jiffies for which the filter seems to be quite
-+ * precise also in embedded systems and KVM/QEMU virtual machines.
-+ */
-+static unsigned long bfq_bfqq_softrt_next_start(struct bfq_data *bfqd,
-+						struct bfq_queue *bfqq)
-+{
-+	bfq_log_bfqq(bfqd, bfqq,
-+"service_blkg %lu soft_rate %u sects/sec interval %u",
-+		     bfqq->service_from_backlogged,
-+		     bfqd->bfq_wr_max_softrt_rate,
-+		     jiffies_to_msecs(HZ * bfqq->service_from_backlogged /
-+				      bfqd->bfq_wr_max_softrt_rate));
-+
-+	return max3(bfqq->soft_rt_next_start,
-+		    bfqq->last_idle_bklogged +
-+		    HZ * bfqq->service_from_backlogged /
-+		    bfqd->bfq_wr_max_softrt_rate,
-+		    jiffies + nsecs_to_jiffies(bfqq->bfqd->bfq_slice_idle) + 4);
-+}
-+
-+/**
-+ * bfq_bfqq_expire - expire a queue.
-+ * @bfqd: device owning the queue.
-+ * @bfqq: the queue to expire.
-+ * @compensate: if true, compensate for the time spent idling.
-+ * @reason: the reason causing the expiration.
-+ *
-+ * If the process associated with bfqq does slow I/O (e.g., because it
-+ * issues random requests), we charge bfqq with the time it has been
-+ * in service instead of the service it has received (see
-+ * bfq_bfqq_charge_time for details on how this goal is achieved). As
-+ * a consequence, bfqq will typically get higher timestamps upon
-+ * reactivation, and hence it will be rescheduled as if it had
-+ * received more service than what it has actually received. In the
-+ * end, bfqq receives less service in proportion to how slowly its
-+ * associated process consumes its budgets (and hence how seriously it
-+ * tends to lower the throughput). In addition, this time-charging
-+ * strategy guarantees time fairness among slow processes. In
-+ * contrast, if the process associated with bfqq is not slow, we
-+ * charge bfqq exactly with the service it has received.
-+ *
-+ * Charging time to the first type of queues and the exact service to
-+ * the other has the effect of using the WF2Q+ policy to schedule the
-+ * former on a timeslice basis, without violating service domain
-+ * guarantees among the latter.
-+ */
-+static void bfq_bfqq_expire(struct bfq_data *bfqd,
-+			    struct bfq_queue *bfqq,
-+			    bool compensate,
-+			    enum bfqq_expiration reason)
-+{
-+	bool slow;
-+	unsigned long delta = 0;
-+	struct bfq_entity *entity = &bfqq->entity;
-+	int ref;
-+
-+	BUG_ON(bfqq != bfqd->in_service_queue);
-+
-+	/*
-+	 * Check whether the process is slow (see bfq_bfqq_is_slow).
-+	 */
-+	slow = bfq_bfqq_is_slow(bfqd, bfqq, compensate, reason, &delta);
-+
-+	/*
-+	 * As above explained, charge slow (typically seeky) and
-+	 * timed-out queues with the time and not the service
-+	 * received, to favor sequential workloads.
-+	 *
-+	 * Processes doing I/O in the slower disk zones will tend to
-+	 * be slow(er) even if not seeky. Therefore, since the
-+	 * estimated peak rate is actually an average over the disk
-+	 * surface, these processes may timeout just for bad luck. To
-+	 * avoid punishing them, do not charge time to processes that
-+	 * succeeded in consuming at least 2/3 of their budget. This
-+	 * allows BFQ to preserve enough elasticity to still perform
-+	 * bandwidth, and not time, distribution with little unlucky
-+	 * or quasi-sequential processes.
-+	 */
-+	if (bfqq->wr_coeff == 1 &&
-+	    (slow ||
-+	     (reason == BFQ_BFQQ_BUDGET_TIMEOUT &&
-+	      bfq_bfqq_budget_left(bfqq) >=  entity->budget / 3)))
-+		bfq_bfqq_charge_time(bfqd, bfqq, delta);
-+
-+	BUG_ON(bfqq->entity.budget < bfqq->entity.service);
-+
-+	if (reason == BFQ_BFQQ_TOO_IDLE &&
-+	    entity->service <= 2 * entity->budget / 10)
-+		bfq_clear_bfqq_IO_bound(bfqq);
-+
-+	if (bfqd->low_latency && bfqq->wr_coeff == 1)
-+		bfqq->last_wr_start_finish = jiffies;
-+
-+	if (bfqd->low_latency && bfqd->bfq_wr_max_softrt_rate > 0 &&
-+	    RB_EMPTY_ROOT(&bfqq->sort_list)) {
-+		/*
-+		 * If we get here, and there are no outstanding
-+		 * requests, then the request pattern is isochronous
-+		 * (see the comments on the function
-+		 * bfq_bfqq_softrt_next_start()). Thus we can compute
-+		 * soft_rt_next_start. If, instead, the queue still
-+		 * has outstanding requests, then we have to wait for
-+		 * the completion of all the outstanding requests to
-+		 * discover whether the request pattern is actually
-+		 * isochronous.
-+		 */
-+		BUG_ON(bfqd->busy_queues < 1);
-+		if (bfqq->dispatched == 0) {
-+			bfqq->soft_rt_next_start =
-+				bfq_bfqq_softrt_next_start(bfqd, bfqq);
-+			bfq_log_bfqq(bfqd, bfqq, "new soft_rt_next %lu",
-+				     bfqq->soft_rt_next_start);
-+		} else {
-+			/*
-+			 * Schedule an update of soft_rt_next_start to when
-+			 * the task may be discovered to be isochronous.
-+			 */
-+			bfq_mark_bfqq_softrt_update(bfqq);
-+		}
-+	}
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+	"expire (%s, slow %d, num_disp %d, short %d, weight %d, serv %d/%d)",
-+		     reason_name[reason], slow, bfqq->dispatched,
-+		     bfq_bfqq_has_short_ttime(bfqq), entity->weight,
-+		     entity->service, entity->budget);
-+
-+	/*
-+	 * Increase, decrease or leave budget unchanged according to
-+	 * reason.
-+	 */
-+	BUG_ON(bfqq->entity.budget < bfqq->entity.service);
-+	__bfq_bfqq_recalc_budget(bfqd, bfqq, reason);
-+	BUG_ON(bfqq->next_rq == NULL &&
-+	       bfqq->entity.budget < bfqq->entity.service);
-+	ref = bfqq->ref;
-+	__bfq_bfqq_expire(bfqd, bfqq);
-+
-+	if (ref == 1) /* bfqq is gone, no more actions on it */
-+		return;
-+
-+	BUG_ON(ref > 1 &&
-+	       !bfq_bfqq_busy(bfqq) && reason == BFQ_BFQQ_BUDGET_EXHAUSTED &&
-+		!bfq_class_idle(bfqq));
-+
-+	/* mark bfqq as waiting a request only if a bic still points to it */
-+	if (!bfq_bfqq_busy(bfqq) &&
-+	    reason != BFQ_BFQQ_BUDGET_TIMEOUT &&
-+	    reason != BFQ_BFQQ_BUDGET_EXHAUSTED) {
-+		BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list));
-+		BUG_ON(bfqq->next_rq);
-+		bfq_mark_bfqq_non_blocking_wait_rq(bfqq);
-+		/*
-+		 * Not setting service to 0, because, if the next rq
-+		 * arrives in time, the queue will go on receiving
-+		 * service with this same budget (as if it never expired)
-+		 */
-+	} else {
-+		entity->service = 0;
-+		bfq_log_bfqq(bfqd, bfqq, "[%s] resetting service", __func__);
-+	}
-+
-+	/*
-+	 * Reset the received-service counter for every parent entity.
-+	 * Differently from what happens with bfqq->entity.service,
-+	 * the resetting of this counter never needs to be postponed
-+	 * for parent entities. In fact, in case bfqq may have a
-+	 * chance to go on being served using the last, partially
-+	 * consumed budget, bfqq->entity.service needs to be kept,
-+	 * because if bfqq then actually goes on being served using
-+	 * the same budget, the last value of bfqq->entity.service is
-+	 * needed to properly decrement bfqq->entity.budget by the
-+	 * portion already consumed. In contrast, it is not necessary
-+	 * to keep entity->service for parent entities too, because
-+	 * the bubble up of the new value of bfqq->entity.budget will
-+	 * make sure that the budgets of parent entities are correct,
-+	 * even in case bfqq and thus parent entities go on receiving
-+	 * service with the same budget.
-+	 */
-+	entity = entity->parent;
-+	for_each_entity(entity)
-+		entity->service = 0;
-+}
-+
-+/*
-+ * Budget timeout is not implemented through a dedicated timer, but
-+ * just checked on request arrivals and completions, as well as on
-+ * idle timer expirations.
-+ */
-+static bool bfq_bfqq_budget_timeout(struct bfq_queue *bfqq)
-+{
-+	return time_is_before_eq_jiffies(bfqq->budget_timeout);
-+}
-+
-+/*
-+ * If we expire a queue that is actively waiting (i.e., with the
-+ * device idled) for the arrival of a new request, then we may incur
-+ * the timestamp misalignment problem described in the body of the
-+ * function __bfq_activate_entity. Hence we return true only if this
-+ * condition does not hold, or if the queue is slow enough to deserve
-+ * only to be kicked off for preserving a high throughput.
-+ */
-+static bool bfq_may_expire_for_budg_timeout(struct bfq_queue *bfqq)
-+{
-+	bfq_log_bfqq(bfqq->bfqd, bfqq,
-+		"wait_request %d left %d timeout %d",
-+		bfq_bfqq_wait_request(bfqq),
-+			bfq_bfqq_budget_left(bfqq) >=  bfqq->entity.budget / 3,
-+		bfq_bfqq_budget_timeout(bfqq));
-+
-+	return (!bfq_bfqq_wait_request(bfqq) ||
-+		bfq_bfqq_budget_left(bfqq) >=  bfqq->entity.budget / 3)
-+		&&
-+		bfq_bfqq_budget_timeout(bfqq);
-+}
-+
-+/*
-+ * For a queue that becomes empty, device idling is allowed only if
-+ * this function returns true for that queue. As a consequence, since
-+ * device idling plays a critical role for both throughput boosting
-+ * and service guarantees, the return value of this function plays a
-+ * critical role as well.
-+ *
-+ * In a nutshell, this function returns true only if idling is
-+ * beneficial for throughput or, even if detrimental for throughput,
-+ * idling is however necessary to preserve service guarantees (low
-+ * latency, desired throughput distribution, ...). In particular, on
-+ * NCQ-capable devices, this function tries to return false, so as to
-+ * help keep the drives' internal queues full, whenever this helps the
-+ * device boost the throughput without causing any service-guarantee
-+ * issue.
-+ *
-+ * In more detail, the return value of this function is obtained by,
-+ * first, computing a number of boolean variables that take into
-+ * account throughput and service-guarantee issues, and, then,
-+ * combining these variables in a logical expression. Most of the
-+ * issues taken into account are not trivial. We discuss these issues
-+ * while introducing the variables.
-+ */
-+static bool bfq_better_to_idle(struct bfq_queue *bfqq)
-+{
-+	struct bfq_data *bfqd = bfqq->bfqd;
-+	bool rot_without_queueing =
-+		!blk_queue_nonrot(bfqd->queue) && !bfqd->hw_tag,
-+		bfqq_sequential_and_IO_bound,
-+		idling_boosts_thr, idling_boosts_thr_without_issues,
-+		idling_needed_for_service_guarantees,
-+		asymmetric_scenario;
-+
-+	if (bfqd->strict_guarantees)
-+		return true;
-+
-+	/*
-+	 * Idling is performed only if slice_idle > 0. In addition, we
-+	 * do not idle if
-+	 * (a) bfqq is async
-+	 * (b) bfqq is in the idle io prio class: in this case we do
-+	 * not idle because we want to minimize the bandwidth that
-+	 * queues in this class can steal to higher-priority queues
-+	 */
-+	if (bfqd->bfq_slice_idle == 0 || !bfq_bfqq_sync(bfqq) ||
-+	   bfq_class_idle(bfqq))
-+		return false;
-+
-+	bfqq_sequential_and_IO_bound = !BFQQ_SEEKY(bfqq) &&
-+		bfq_bfqq_IO_bound(bfqq) && bfq_bfqq_has_short_ttime(bfqq);
-+	/*
-+	 * The next variable takes into account the cases where idling
-+	 * boosts the throughput.
-+	 *
-+	 * The value of the variable is computed considering, first, that
-+	 * idling is virtually always beneficial for the throughput if:
-+	 * (a) the device is not NCQ-capable and rotational, or
-+	 * (b) regardless of the presence of NCQ, the device is rotational and
-+	 *     the request pattern for bfqq is I/O-bound and sequential, or
-+	 * (c) regardless of whether it is rotational, the device is
-+	 *     not NCQ-capable and the request pattern for bfqq is
-+	 *     I/O-bound and sequential.
-+	 *
-+	 * Secondly, and in contrast to the above item (b), idling an
-+	 * NCQ-capable flash-based device would not boost the
-+	 * throughput even with sequential I/O; rather it would lower
-+	 * the throughput in proportion to how fast the device
-+	 * is. Accordingly, the next variable is true if any of the
-+	 * above conditions (a), (b) or (c) is true, and, in
-+	 * particular, happens to be false if bfqd is an NCQ-capable
-+	 * flash-based device.
-+	 */
-+	idling_boosts_thr = rot_without_queueing ||
-+		((!blk_queue_nonrot(bfqd->queue) || !bfqd->hw_tag) &&
-+		 bfqq_sequential_and_IO_bound);
-+
-+	/*
-+	 * The value of the next variable,
-+	 * idling_boosts_thr_without_issues, is equal to that of
-+	 * idling_boosts_thr, unless a special case holds. In this
-+	 * special case, described below, idling may cause problems to
-+	 * weight-raised queues.
-+	 *
-+	 * When the request pool is saturated (e.g., in the presence
-+	 * of write hogs), if the processes associated with
-+	 * non-weight-raised queues ask for requests at a lower rate,
-+	 * then processes associated with weight-raised queues have a
-+	 * higher probability to get a request from the pool
-+	 * immediately (or at least soon) when they need one. Thus
-+	 * they have a higher probability to actually get a fraction
-+	 * of the device throughput proportional to their high
-+	 * weight. This is especially true with NCQ-capable drives,
-+	 * which enqueue several requests in advance, and further
-+	 * reorder internally-queued requests.
-+	 *
-+	 * For this reason, we force to false the value of
-+	 * idling_boosts_thr_without_issues if there are weight-raised
-+	 * busy queues. In this case, and if bfqq is not weight-raised,
-+	 * this guarantees that the device is not idled for bfqq (if,
-+	 * instead, bfqq is weight-raised, then idling will be
-+	 * guaranteed by another variable, see below). Combined with
-+	 * the timestamping rules of BFQ (see [1] for details), this
-+	 * behavior causes bfqq, and hence any sync non-weight-raised
-+	 * queue, to get a lower number of requests served, and thus
-+	 * to ask for a lower number of requests from the request
-+	 * pool, before the busy weight-raised queues get served
-+	 * again. This often mitigates starvation problems in the
-+	 * presence of heavy write workloads and NCQ, thereby
-+	 * guaranteeing a higher application and system responsiveness
-+	 * in these hostile scenarios.
-+	 */
-+	idling_boosts_thr_without_issues = idling_boosts_thr &&
-+		bfqd->wr_busy_queues == 0;
-+
-+	/*
-+	 * There is then a case where idling must be performed not
-+	 * for throughput concerns, but to preserve service
-+	 * guarantees.
-+	 *
-+	 * To introduce this case, we can note that allowing the drive
-+	 * to enqueue more than one request at a time, and hence
-+	 * delegating de facto final scheduling decisions to the
-+	 * drive's internal scheduler, entails loss of control on the
-+	 * actual request service order. In particular, the critical
-+	 * situation is when requests from different processes happen
-+	 * to be present, at the same time, in the internal queue(s)
-+	 * of the drive. In such a situation, the drive, by deciding
-+	 * the service order of the internally-queued requests, does
-+	 * determine also the actual throughput distribution among
-+	 * these processes. But the drive typically has no notion or
-+	 * concern about per-process throughput distribution, and
-+	 * makes its decisions only on a per-request basis. Therefore,
-+	 * the service distribution enforced by the drive's internal
-+	 * scheduler is likely to coincide with the desired
-+	 * device-throughput distribution only in a completely
-+	 * symmetric scenario where:
-+	 * (i)  each of these processes must get the same throughput as
-+	 *      the others;
-+	 * (ii) all these processes have the same I/O pattern
-+	 *      (either sequential or random).
-+	 * In fact, in such a scenario, the drive will tend to treat
-+	 * the requests of each of these processes in about the same
-+	 * way as the requests of the others, and thus to provide
-+	 * each of these processes with about the same throughput
-+	 * (which is exactly the desired throughput distribution). In
-+	 * contrast, in any asymmetric scenario, device idling is
-+	 * certainly needed to guarantee that bfqq receives its
-+	 * assigned fraction of the device throughput (see [1] for
-+	 * details).
-+	 *
-+	 * We address this issue by controlling, actually, only the
-+	 * symmetry sub-condition (i), i.e., provided that
-+	 * sub-condition (i) holds, idling is not performed,
-+	 * regardless of whether sub-condition (ii) holds. In other
-+	 * words, only if sub-condition (i) holds, then idling is
-+	 * allowed, and the device tends to be prevented from queueing
-+	 * many requests, possibly of several processes. The reason
-+	 * for not controlling also sub-condition (ii) is that we
-+	 * exploit preemption to preserve guarantees in case of
-+	 * symmetric scenarios, even if (ii) does not hold, as
-+	 * explained in the next two paragraphs.
-+	 *
-+	 * Even if a queue, say Q, is expired when it remains idle, Q
-+	 * can still preempt the new in-service queue if the next
-+	 * request of Q arrives soon (see the comments on
-+	 * bfq_bfqq_update_budg_for_activation). If all queues and
-+	 * groups have the same weight, this form of preemption,
-+	 * combined with the hole-recovery heuristic described in the
-+	 * comments on function bfq_bfqq_update_budg_for_activation,
-+	 * are enough to preserve a correct bandwidth distribution in
-+	 * the mid term, even without idling. In fact, even if not
-+	 * idling allows the internal queues of the device to contain
-+	 * many requests, and thus to reorder requests, we can rather
-+	 * safely assume that the internal scheduler still preserves a
-+	 * minimum of mid-term fairness. The motivation for using
-+	 * preemption instead of idling is that, by not idling,
-+	 * service guarantees are preserved without minimally
-+	 * sacrificing throughput. In other words, both a high
-+	 * throughput and its desired distribution are obtained.
-+	 *
-+	 * More precisely, this preemption-based, idleless approach
-+	 * provides fairness in terms of IOPS, and not sectors per
-+	 * second. This can be seen with a simple example. Suppose
-+	 * that there are two queues with the same weight, but that
-+	 * the first queue receives requests of 8 sectors, while the
-+	 * second queue receives requests of 1024 sectors. In
-+	 * addition, suppose that each of the two queues contains at
-+	 * most one request at a time, which implies that each queue
-+	 * always remains idle after it is served. Finally, after
-+	 * remaining idle, each queue receives very quickly a new
-+	 * request. It follows that the two queues are served
-+	 * alternatively, preempting each other if needed. This
-+	 * implies that, although both queues have the same weight,
-+	 * the queue with large requests receives a service that is
-+	 * 1024/8 times as high as the service received by the other
-+	 * queue.
-+	 *
-+	 * On the other hand, device idling is performed, and thus
-+	 * pure sector-domain guarantees are provided, for the
-+	 * following queues, which are likely to need stronger
-+	 * throughput guarantees: weight-raised queues, and queues
-+	 * with a higher weight than other queues. When such queues
-+	 * are active, sub-condition (i) is false, which triggers
-+	 * device idling.
-+	 *
-+	 * According to the above considerations, the next variable is
-+	 * true (only) if sub-condition (i) holds. To compute the
-+	 * value of this variable, we not only use the return value of
-+	 * the function bfq_symmetric_scenario(), but also check
-+	 * whether bfqq is being weight-raised, because
-+	 * bfq_symmetric_scenario() does not take into account also
-+	 * weight-raised queues (see comments on
-+	 * bfq_weights_tree_add()).
-+	 *
-+	 * As a side note, it is worth considering that the above
-+	 * device-idling countermeasures may however fail in the
-+	 * following unlucky scenario: if idling is (correctly)
-+	 * disabled in a time period during which all symmetry
-+	 * sub-conditions hold, and hence the device is allowed to
-+	 * enqueue many requests, but at some later point in time some
-+	 * sub-condition stops to hold, then it may become impossible
-+	 * to let requests be served in the desired order until all
-+	 * the requests already queued in the device have been served.
-+	 */
-+	asymmetric_scenario = bfqq->wr_coeff > 1 ||
-+		!bfq_symmetric_scenario(bfqd);
-+
-+	/*
-+	 * Finally, there is a case where maximizing throughput is the
-+	 * best choice even if it may cause unfairness toward
-+	 * bfqq. Such a case is when bfqq became active in a burst of
-+	 * queue activations. Queues that became active during a large
-+	 * burst benefit only from throughput, as discussed in the
-+	 * comments on bfq_handle_burst. Thus, if bfqq became active
-+	 * in a burst and not idling the device maximizes throughput,
-+	 * then the device must no be idled, because not idling the
-+	 * device provides bfqq and all other queues in the burst with
-+	 * maximum benefit. Combining this and the above case, we can
-+	 * now establish when idling is actually needed to preserve
-+	 * service guarantees.
-+	 */
-+	idling_needed_for_service_guarantees =
-+		asymmetric_scenario && !bfq_bfqq_in_large_burst(bfqq);
-+
-+	/*
-+	 * We have now all the components we need to compute the
-+	 * return value of the function, which is true only if idling
-+	 * either boosts the throughput (without issues), or is
-+	 * necessary to preserve service guarantees.
-+	 */
-+	bfq_log_bfqq(bfqd, bfqq, "sync %d idling_boosts_thr %d",
-+		     bfq_bfqq_sync(bfqq), idling_boosts_thr);
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+		     "wr_busy %d boosts %d IO-bound %d guar %d",
-+		     bfqd->wr_busy_queues,
-+		     idling_boosts_thr_without_issues,
-+		     bfq_bfqq_IO_bound(bfqq),
-+		     idling_needed_for_service_guarantees);
-+
-+	return idling_boosts_thr_without_issues ||
-+		idling_needed_for_service_guarantees;
-+}
-+
-+/*
-+ * If the in-service queue is empty but the function bfq_better_to_idle
-+ * returns true, then:
-+ * 1) the queue must remain in service and cannot be expired, and
-+ * 2) the device must be idled to wait for the possible arrival of a new
-+ *    request for the queue.
-+ * See the comments on the function bfq_better_to_idle for the reasons
-+ * why performing device idling is the best choice to boost the throughput
-+ * and preserve service guarantees when bfq_better_to_idle itself
-+ * returns true.
-+ */
-+static bool bfq_bfqq_must_idle(struct bfq_queue *bfqq)
-+{
-+	return RB_EMPTY_ROOT(&bfqq->sort_list) && bfq_better_to_idle(bfqq);
-+}
-+
-+/*
-+ * Select a queue for service.  If we have a current queue in service,
-+ * check whether to continue servicing it, or retrieve and set a new one.
-+ */
-+static struct bfq_queue *bfq_select_queue(struct bfq_data *bfqd)
-+{
-+	struct bfq_queue *bfqq;
-+	struct request *next_rq;
-+	enum bfqq_expiration reason = BFQ_BFQQ_BUDGET_TIMEOUT;
-+
-+	bfqq = bfqd->in_service_queue;
-+	if (!bfqq)
-+		goto new_queue;
-+
-+	bfq_log_bfqq(bfqd, bfqq, "already in-service queue");
-+
-+	/*
-+	 * Do not expire bfqq for budget timeout if bfqq may be about
-+	 * to enjoy device idling. The reason why, in this case, we
-+	 * prevent bfqq from expiring is the same as in the comments
-+	 * on the case where bfq_bfqq_must_idle() returns true, in
-+	 * bfq_completed_request().
-+	 */
-+	if (bfq_may_expire_for_budg_timeout(bfqq) &&
-+	    !bfq_bfqq_must_idle(bfqq))
-+		goto expire;
-+
-+check_queue:
-+	/*
-+	 * This loop is rarely executed more than once. Even when it
-+	 * happens, it is much more convenient to re-execute this loop
-+	 * than to return NULL and trigger a new dispatch to get a
-+	 * request served.
-+	 */
-+	next_rq = bfqq->next_rq;
-+	/*
-+	 * If bfqq has requests queued and it has enough budget left to
-+	 * serve them, keep the queue, otherwise expire it.
-+	 */
-+	if (next_rq) {
-+		BUG_ON(RB_EMPTY_ROOT(&bfqq->sort_list));
-+
-+		if (bfq_serv_to_charge(next_rq, bfqq) >
-+			bfq_bfqq_budget_left(bfqq)) {
-+			/*
-+			 * Expire the queue for budget exhaustion,
-+			 * which makes sure that the next budget is
-+			 * enough to serve the next request, even if
-+			 * it comes from the fifo expired path.
-+			 */
-+			reason = BFQ_BFQQ_BUDGET_EXHAUSTED;
-+			goto expire;
-+		} else {
-+			/*
-+			 * The idle timer may be pending because we may
-+			 * not disable disk idling even when a new request
-+			 * arrives.
-+			 */
-+			if (bfq_bfqq_wait_request(bfqq)) {
-+				BUG_ON(!hrtimer_active(&bfqd->idle_slice_timer));
-+				/*
-+				 * If we get here: 1) at least a new request
-+				 * has arrived but we have not disabled the
-+				 * timer because the request was too small,
-+				 * 2) then the block layer has unplugged
-+				 * the device, causing the dispatch to be
-+				 * invoked.
-+				 *
-+				 * Since the device is unplugged, now the
-+				 * requests are probably large enough to
-+				 * provide a reasonable throughput.
-+				 * So we disable idling.
-+				 */
-+				bfq_clear_bfqq_wait_request(bfqq);
-+				hrtimer_try_to_cancel(&bfqd->idle_slice_timer);
-+				bfqg_stats_update_idle_time(bfqq_group(bfqq));
-+			}
-+			goto keep_queue;
-+		}
-+	}
-+
-+	/*
-+	 * No requests pending. However, if the in-service queue is idling
-+	 * for a new request, or has requests waiting for a completion and
-+	 * may idle after their completion, then keep it anyway.
-+	 */
-+	if (hrtimer_active(&bfqd->idle_slice_timer) ||
-+	    (bfqq->dispatched != 0 && bfq_better_to_idle(bfqq))) {
-+		bfqq = NULL;
-+		goto keep_queue;
-+	}
-+
-+	reason = BFQ_BFQQ_NO_MORE_REQUESTS;
-+expire:
-+	bfq_bfqq_expire(bfqd, bfqq, false, reason);
-+new_queue:
-+	bfqq = bfq_set_in_service_queue(bfqd);
-+	if (bfqq) {
-+		bfq_log_bfqq(bfqd, bfqq, "checking new queue");
-+		goto check_queue;
-+	}
-+keep_queue:
-+	if (bfqq)
-+		bfq_log_bfqq(bfqd, bfqq, "returned this queue");
-+	else
-+		bfq_log(bfqd, "no queue returned");
-+
-+	return bfqq;
-+}
-+
-+static void bfq_update_wr_data(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	struct bfq_entity *entity = &bfqq->entity;
-+
-+	if (bfqq->wr_coeff > 1) { /* queue is being weight-raised */
-+		BUG_ON(bfqq->wr_cur_max_time == bfqd->bfq_wr_rt_max_time &&
-+		       time_is_after_jiffies(bfqq->last_wr_start_finish));
-+
-+		bfq_log_bfqq(bfqd, bfqq,
-+			"raising period dur %u/%u msec, old coeff %u, w %d(%d)",
-+			jiffies_to_msecs(jiffies - bfqq->last_wr_start_finish),
-+			jiffies_to_msecs(bfqq->wr_cur_max_time),
-+			bfqq->wr_coeff,
-+			bfqq->entity.weight, bfqq->entity.orig_weight);
-+
-+		BUG_ON(bfqq != bfqd->in_service_queue && entity->weight !=
-+		       entity->orig_weight * bfqq->wr_coeff);
-+		if (entity->prio_changed)
-+			bfq_log_bfqq(bfqd, bfqq, "WARN: pending prio change");
-+
-+		/*
-+		 * If the queue was activated in a burst, or too much
-+		 * time has elapsed from the beginning of this
-+		 * weight-raising period, then end weight raising.
-+		 */
-+		if (bfq_bfqq_in_large_burst(bfqq))
-+			bfq_bfqq_end_wr(bfqq);
-+		else if (time_is_before_jiffies(bfqq->last_wr_start_finish +
-+					   bfqq->wr_cur_max_time)) {
-+			if (bfqq->wr_cur_max_time != bfqd->bfq_wr_rt_max_time ||
-+			time_is_before_jiffies(bfqq->wr_start_at_switch_to_srt +
-+					bfq_wr_duration(bfqd)))
-+				bfq_bfqq_end_wr(bfqq);
-+			else {
-+				switch_back_to_interactive_wr(bfqq, bfqd);
-+				BUG_ON(time_is_after_jiffies(
-+					       bfqq->last_wr_start_finish));
-+				bfqq->entity.prio_changed = 1;
-+				bfq_log_bfqq(bfqd, bfqq,
-+					"back to interactive wr");
-+			}
-+		}
-+		if (bfqq->wr_coeff > 1 &&
-+		       bfqq->wr_cur_max_time != bfqd->bfq_wr_rt_max_time &&
-+		       bfqq->service_from_wr > max_service_from_wr) {
-+			       /* see comments on max_service_from_wr */
-+			       bfq_bfqq_end_wr(bfqq);
-+			       bfq_log_bfqq(bfqd, bfqq,
-+					       "too much service");
-+	       }
-+	}
-+	/*
-+	 * To improve latency (for this or other queues), immediately
-+	 * update weight both if it must be raised and if it must be
-+	 * lowered. Since, entity may be on some active tree here, and
-+	 * might have a pending change of its ioprio class, invoke
-+	 * next function with the last parameter unset (see the
-+	 * comments on the function).
-+	 */
-+	if ((entity->weight > entity->orig_weight) != (bfqq->wr_coeff > 1))
-+		__bfq_entity_update_weight_prio(bfq_entity_service_tree(entity),
-+						entity, false);
-+}
-+
-+/*
-+ * Dispatch one request from bfqq, moving it to the request queue
-+ * dispatch list.
-+ */
-+static int bfq_dispatch_request(struct bfq_data *bfqd,
-+				struct bfq_queue *bfqq)
-+{
-+	int dispatched = 0;
-+	struct request *rq = bfqq->next_rq;
-+	unsigned long service_to_charge;
-+
-+	BUG_ON(RB_EMPTY_ROOT(&bfqq->sort_list));
-+	BUG_ON(!rq);
-+	service_to_charge = bfq_serv_to_charge(rq, bfqq);
-+
-+	BUG_ON(service_to_charge > bfq_bfqq_budget_left(bfqq));
-+
-+	BUG_ON(bfqq->entity.budget < bfqq->entity.service);
-+
-+	bfq_bfqq_served(bfqq, service_to_charge);
-+
-+	BUG_ON(bfqq->entity.budget < bfqq->entity.service);
-+
-+	bfq_dispatch_insert(bfqd->queue, rq);
-+
-+	/*
-+	 * If weight raising has to terminate for bfqq, then next
-+	 * function causes an immediate update of bfqq's weight,
-+	 * without waiting for next activation. As a consequence, on
-+	 * expiration, bfqq will be timestamped as if has never been
-+	 * weight-raised during this service slot, even if it has
-+	 * received part or even most of the service as a
-+	 * weight-raised queue. This inflates bfqq's timestamps, which
-+	 * is beneficial, as bfqq is then more willing to leave the
-+	 * device immediately to possible other weight-raised queues.
-+	 */
-+	bfq_update_wr_data(bfqd, bfqq);
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+			"dispatched %u sec req (%llu), budg left %d",
-+			blk_rq_sectors(rq),
-+			(unsigned long long) blk_rq_pos(rq),
-+			bfq_bfqq_budget_left(bfqq));
-+
-+	dispatched++;
-+
-+	if (!bfqd->in_service_bic) {
-+		atomic_long_inc(&RQ_BIC(rq)->icq.ioc->refcount);
-+		bfqd->in_service_bic = RQ_BIC(rq);
-+		BUG_ON(!bfqd->in_service_bic);
-+	}
-+
-+	if (bfqd->busy_queues > 1 && bfq_class_idle(bfqq))
-+		goto expire;
-+
-+	return dispatched;
-+
-+expire:
-+	bfq_bfqq_expire(bfqd, bfqq, false, BFQ_BFQQ_BUDGET_EXHAUSTED);
-+	return dispatched;
-+}
-+
-+static int __bfq_forced_dispatch_bfqq(struct bfq_queue *bfqq)
-+{
-+	int dispatched = 0;
-+
-+	while (bfqq->next_rq) {
-+		bfq_dispatch_insert(bfqq->bfqd->queue, bfqq->next_rq);
-+		dispatched++;
-+	}
-+
-+	BUG_ON(!list_empty(&bfqq->fifo));
-+	return dispatched;
-+}
-+
-+/*
-+ * Drain our current requests.
-+ * Used for barriers and when switching io schedulers on-the-fly.
-+ */
-+static int bfq_forced_dispatch(struct bfq_data *bfqd)
-+{
-+	struct bfq_queue *bfqq, *n;
-+	struct bfq_service_tree *st;
-+	int dispatched = 0;
-+
-+	bfqq = bfqd->in_service_queue;
-+	if (bfqq)
-+		__bfq_bfqq_expire(bfqd, bfqq);
-+
-+	/*
-+	 * Loop through classes, and be careful to leave the scheduler
-+	 * in a consistent state, as feedback mechanisms and vtime
-+	 * updates cannot be disabled during the process.
-+	 */
-+	list_for_each_entry_safe(bfqq, n, &bfqd->active_list, bfqq_list) {
-+		st = bfq_entity_service_tree(&bfqq->entity);
-+
-+		dispatched += __bfq_forced_dispatch_bfqq(bfqq);
-+
-+		bfqq->max_budget = bfq_max_budget(bfqd);
-+		bfq_forget_idle(st);
-+	}
-+
-+	BUG_ON(bfqd->busy_queues != 0);
-+
-+	return dispatched;
-+}
-+
-+static int bfq_dispatch_requests(struct request_queue *q, int force)
-+{
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+	struct bfq_queue *bfqq;
-+
-+	bfq_log(bfqd, "%d busy queues", bfqd->busy_queues);
-+
-+	if (bfqd->busy_queues == 0)
-+		return 0;
-+
-+	if (unlikely(force))
-+		return bfq_forced_dispatch(bfqd);
-+
-+	/*
-+	 * Force device to serve one request at a time if
-+	 * strict_guarantees is true. Forcing this service scheme is
-+	 * currently the ONLY way to guarantee that the request
-+	 * service order enforced by the scheduler is respected by a
-+	 * queueing device. Otherwise the device is free even to make
-+	 * some unlucky request wait for as long as the device
-+	 * wishes.
-+	 *
-+	 * Of course, serving one request at at time may cause loss of
-+	 * throughput.
-+	 */
-+	if (bfqd->strict_guarantees && bfqd->rq_in_driver > 0)
-+		return 0;
-+
-+	bfqq = bfq_select_queue(bfqd);
-+	if (!bfqq)
-+		return 0;
-+
-+	BUG_ON(bfqq->entity.budget < bfqq->entity.service);
-+
-+	BUG_ON(bfq_bfqq_wait_request(bfqq));
-+
-+	if (!bfq_dispatch_request(bfqd, bfqq))
-+		return 0;
-+
-+	bfq_log_bfqq(bfqd, bfqq, "%s request",
-+			bfq_bfqq_sync(bfqq) ? "sync" : "async");
-+
-+	BUG_ON(bfqq->next_rq == NULL &&
-+	       bfqq->entity.budget < bfqq->entity.service);
-+	return 1;
-+}
-+
-+/*
-+ * Task holds one reference to the queue, dropped when task exits.  Each rq
-+ * in-flight on this queue also holds a reference, dropped when rq is freed.
-+ *
-+ * Queue lock must be held here. Recall not to use bfqq after calling
-+ * this function on it.
-+ */
-+static void bfq_put_queue(struct bfq_queue *bfqq)
-+{
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	struct bfq_group *bfqg = bfqq_group(bfqq);
-+#endif
-+
-+	BUG_ON(bfqq->ref <= 0);
-+
-+	bfq_log_bfqq(bfqq->bfqd, bfqq, "%p %d", bfqq, bfqq->ref);
-+	bfqq->ref--;
-+	if (bfqq->ref)
-+		return;
-+
-+	BUG_ON(rb_first(&bfqq->sort_list));
-+	BUG_ON(bfqq->allocated[READ] + bfqq->allocated[WRITE] != 0);
-+	BUG_ON(bfqq->entity.tree);
-+	BUG_ON(bfq_bfqq_busy(bfqq));
-+
-+	if (!hlist_unhashed(&bfqq->burst_list_node)) {
-+		hlist_del_init(&bfqq->burst_list_node);
-+		/*
-+		 * Decrement also burst size after the removal, if the
-+		 * process associated with bfqq is exiting, and thus
-+		 * does not contribute to the burst any longer. This
-+		 * decrement helps filter out false positives of large
-+		 * bursts, when some short-lived process (often due to
-+		 * the execution of commands by some service) happens
-+		 * to start and exit while a complex application is
-+		 * starting, and thus spawning several processes that
-+		 * do I/O (and that *must not* be treated as a large
-+		 * burst, see comments on bfq_handle_burst).
-+		 *
-+		 * In particular, the decrement is performed only if:
-+		 * 1) bfqq is not a merged queue, because, if it is,
-+		 * then this free of bfqq is not triggered by the exit
-+		 * of the process bfqq is associated with, but exactly
-+		 * by the fact that bfqq has just been merged.
-+		 * 2) burst_size is greater than 0, to handle
-+		 * unbalanced decrements. Unbalanced decrements may
-+		 * happen in te following case: bfqq is inserted into
-+		 * the current burst list--without incrementing
-+		 * bust_size--because of a split, but the current
-+		 * burst list is not the burst list bfqq belonged to
-+		 * (see comments on the case of a split in
-+		 * bfq_set_request).
-+		 */
-+		if (bfqq->bic && bfqq->bfqd->burst_size > 0)
-+			bfqq->bfqd->burst_size--;
-+	}
-+
-+	bfq_log_bfqq(bfqq->bfqd, bfqq, "%p freed", bfqq);
-+
-+	kmem_cache_free(bfq_pool, bfqq);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	bfqg_put(bfqg);
-+#endif
-+}
-+
-+static void bfq_put_cooperator(struct bfq_queue *bfqq)
-+{
-+	struct bfq_queue *__bfqq, *next;
-+
-+	/*
-+	 * If this queue was scheduled to merge with another queue, be
-+	 * sure to drop the reference taken on that queue (and others in
-+	 * the merge chain). See bfq_setup_merge and bfq_merge_bfqqs.
-+	 */
-+	__bfqq = bfqq->new_bfqq;
-+	while (__bfqq) {
-+		if (__bfqq == bfqq)
-+			break;
-+		next = __bfqq->new_bfqq;
-+		bfq_put_queue(__bfqq);
-+		__bfqq = next;
-+	}
-+}
-+
-+static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq)
-+{
-+	if (bfqq == bfqd->in_service_queue) {
-+		__bfq_bfqq_expire(bfqd, bfqq);
-+		bfq_schedule_dispatch(bfqd);
-+	}
-+
-+	bfq_log_bfqq(bfqd, bfqq, "%p, %d", bfqq, bfqq->ref);
-+
-+	bfq_put_cooperator(bfqq);
-+
-+	bfq_put_queue(bfqq); /* release process reference */
-+}
-+
-+static void bfq_init_icq(struct io_cq *icq)
-+{
-+	icq_to_bic(icq)->ttime.last_end_request = ktime_get_ns() - (1ULL<<32);
-+}
-+
-+static void bfq_exit_icq(struct io_cq *icq)
-+{
-+	struct bfq_io_cq *bic = icq_to_bic(icq);
-+	struct bfq_data *bfqd = bic_to_bfqd(bic);
-+
-+	if (bic_to_bfqq(bic, false)) {
-+		bfq_exit_bfqq(bfqd, bic_to_bfqq(bic, false));
-+		bic_set_bfqq(bic, NULL, false);
-+	}
-+
-+	if (bic_to_bfqq(bic, true)) {
-+		/*
-+		 * If the bic is using a shared queue, put the reference
-+		 * taken on the io_context when the bic started using a
-+		 * shared bfq_queue.
-+		 */
-+		if (bfq_bfqq_coop(bic_to_bfqq(bic, true)))
-+			put_io_context(icq->ioc);
-+		bfq_exit_bfqq(bfqd, bic_to_bfqq(bic, true));
-+		bic_set_bfqq(bic, NULL, true);
-+	}
-+}
-+
-+/*
-+ * Update the entity prio values; note that the new values will not
-+ * be used until the next (re)activation.
-+ */
-+static void bfq_set_next_ioprio_data(struct bfq_queue *bfqq,
-+				     struct bfq_io_cq *bic)
-+{
-+	struct task_struct *tsk = current;
-+	int ioprio_class;
-+
-+	ioprio_class = IOPRIO_PRIO_CLASS(bic->ioprio);
-+	switch (ioprio_class) {
-+	default:
-+		dev_err(bfqq->bfqd->queue->backing_dev_info->dev,
-+			"bfq: bad prio class %d\n", ioprio_class);
-+	case IOPRIO_CLASS_NONE:
-+		/*
-+		 * No prio set, inherit CPU scheduling settings.
-+		 */
-+		bfqq->new_ioprio = task_nice_ioprio(tsk);
-+		bfqq->new_ioprio_class = task_nice_ioclass(tsk);
-+		break;
-+	case IOPRIO_CLASS_RT:
-+		bfqq->new_ioprio = IOPRIO_PRIO_DATA(bic->ioprio);
-+		bfqq->new_ioprio_class = IOPRIO_CLASS_RT;
-+		break;
-+	case IOPRIO_CLASS_BE:
-+		bfqq->new_ioprio = IOPRIO_PRIO_DATA(bic->ioprio);
-+		bfqq->new_ioprio_class = IOPRIO_CLASS_BE;
-+		break;
-+	case IOPRIO_CLASS_IDLE:
-+		bfqq->new_ioprio_class = IOPRIO_CLASS_IDLE;
-+		bfqq->new_ioprio = 7;
-+		break;
-+	}
-+
-+	if (bfqq->new_ioprio >= IOPRIO_BE_NR) {
-+		pr_crit("bfq_set_next_ioprio_data: new_ioprio %d\n",
-+			bfqq->new_ioprio);
-+		BUG();
-+	}
-+
-+	bfqq->entity.new_weight = bfq_ioprio_to_weight(bfqq->new_ioprio);
-+	bfqq->entity.prio_changed = 1;
-+	bfq_log_bfqq(bfqq->bfqd, bfqq,
-+		     "bic_class %d prio %d class %d",
-+		     ioprio_class, bfqq->new_ioprio, bfqq->new_ioprio_class);
-+}
-+
-+static void bfq_check_ioprio_change(struct bfq_io_cq *bic, struct bio *bio)
-+{
-+	struct bfq_data *bfqd = bic_to_bfqd(bic);
-+	struct bfq_queue *bfqq;
-+	unsigned long uninitialized_var(flags);
-+	int ioprio = bic->icq.ioc->ioprio;
-+
-+	/*
-+	 * This condition may trigger on a newly created bic, be sure to
-+	 * drop the lock before returning.
-+	 */
-+	if (unlikely(!bfqd) || likely(bic->ioprio == ioprio))
-+		return;
-+
-+	bic->ioprio = ioprio;
-+
-+	bfqq = bic_to_bfqq(bic, false);
-+	if (bfqq) {
-+		/* release process reference on this queue */
-+		bfq_put_queue(bfqq);
-+		bfqq = bfq_get_queue(bfqd, bio, BLK_RW_ASYNC, bic);
-+		bic_set_bfqq(bic, bfqq, false);
-+		bfq_log_bfqq(bfqd, bfqq,
-+			     "bfqq %p %d",
-+			     bfqq, bfqq->ref);
-+	}
-+
-+	bfqq = bic_to_bfqq(bic, true);
-+	if (bfqq)
-+		bfq_set_next_ioprio_data(bfqq, bic);
-+}
-+
-+static void bfq_init_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+			  struct bfq_io_cq *bic, pid_t pid, int is_sync)
-+{
-+	RB_CLEAR_NODE(&bfqq->entity.rb_node);
-+	INIT_LIST_HEAD(&bfqq->fifo);
-+	INIT_HLIST_NODE(&bfqq->burst_list_node);
-+	BUG_ON(!hlist_unhashed(&bfqq->burst_list_node));
-+
-+	bfqq->ref = 0;
-+	bfqq->bfqd = bfqd;
-+
-+	if (bic)
-+		bfq_set_next_ioprio_data(bfqq, bic);
-+
-+	if (is_sync) {
-+		/*
-+		 * No need to mark as has_short_ttime if in
-+		 * idle_class, because no device idling is performed
-+		 * for queues in idle class
-+		 */
-+		if (!bfq_class_idle(bfqq))
-+			/* tentatively mark as has_short_ttime */
-+			bfq_mark_bfqq_has_short_ttime(bfqq);
-+		bfq_mark_bfqq_sync(bfqq);
-+		bfq_mark_bfqq_just_created(bfqq);
-+	} else
-+		bfq_clear_bfqq_sync(bfqq);
-+	bfq_mark_bfqq_IO_bound(bfqq);
-+
-+	/* Tentative initial value to trade off between thr and lat */
-+	bfqq->max_budget = (2 * bfq_max_budget(bfqd)) / 3;
-+	bfqq->pid = pid;
-+
-+	bfqq->wr_coeff = 1;
-+	bfqq->last_wr_start_finish = jiffies;
-+	bfqq->wr_start_at_switch_to_srt = bfq_smallest_from_now();
-+	bfqq->budget_timeout = bfq_smallest_from_now();
-+	bfqq->split_time = bfq_smallest_from_now();
-+
-+	/*
-+	 * To not forget the possibly high bandwidth consumed by a
-+	 * process/queue in the recent past,
-+	 * bfq_bfqq_softrt_next_start() returns a value at least equal
-+	 * to the current value of bfqq->soft_rt_next_start (see
-+	 * comments on bfq_bfqq_softrt_next_start).  Set
-+	 * soft_rt_next_start to now, to mean that bfqq has consumed
-+	 * no bandwidth so far.
-+	 */
-+	bfqq->soft_rt_next_start = jiffies;
-+
-+	/* first request is almost certainly seeky */
-+	bfqq->seek_history = 1;
-+}
-+
-+static struct bfq_queue **bfq_async_queue_prio(struct bfq_data *bfqd,
-+					       struct bfq_group *bfqg,
-+					       int ioprio_class, int ioprio)
-+{
-+	switch (ioprio_class) {
-+	case IOPRIO_CLASS_RT:
-+		return &bfqg->async_bfqq[0][ioprio];
-+	case IOPRIO_CLASS_NONE:
-+		ioprio = IOPRIO_NORM;
-+		/* fall through */
-+	case IOPRIO_CLASS_BE:
-+		return &bfqg->async_bfqq[1][ioprio];
-+	case IOPRIO_CLASS_IDLE:
-+		return &bfqg->async_idle_bfqq;
-+	default:
-+		BUG();
-+	}
-+}
-+
-+static struct bfq_queue *bfq_get_queue(struct bfq_data *bfqd,
-+				       struct bio *bio, bool is_sync,
-+				       struct bfq_io_cq *bic)
-+{
-+	const int ioprio = IOPRIO_PRIO_DATA(bic->ioprio);
-+	const int ioprio_class = IOPRIO_PRIO_CLASS(bic->ioprio);
-+	struct bfq_queue **async_bfqq = NULL;
-+	struct bfq_queue *bfqq;
-+	struct bfq_group *bfqg;
-+
-+	rcu_read_lock();
-+
-+	bfqg = bfq_find_set_group(bfqd, bio_blkcg(bio));
-+	if (!bfqg) {
-+		bfqq = &bfqd->oom_bfqq;
-+		goto out;
-+	}
-+
-+	if (!is_sync) {
-+		async_bfqq = bfq_async_queue_prio(bfqd, bfqg, ioprio_class,
-+						  ioprio);
-+		bfqq = *async_bfqq;
-+		if (bfqq)
-+			goto out;
-+	}
-+
-+	bfqq = kmem_cache_alloc_node(bfq_pool,
-+				     GFP_NOWAIT | __GFP_ZERO | __GFP_NOWARN,
-+				     bfqd->queue->node);
-+
-+	if (bfqq) {
-+		bfq_init_bfqq(bfqd, bfqq, bic, current->pid,
-+			      is_sync);
-+		bfq_init_entity(&bfqq->entity, bfqg);
-+		bfq_log_bfqq(bfqd, bfqq, "allocated");
-+	} else {
-+		bfqq = &bfqd->oom_bfqq;
-+		bfq_log_bfqq(bfqd, bfqq, "using oom bfqq");
-+		goto out;
-+	}
-+
-+	/*
-+	 * Pin the queue now that it's allocated, scheduler exit will
-+	 * prune it.
-+	 */
-+	if (async_bfqq) {
-+		bfqq->ref++; /*
-+			      * Extra group reference, w.r.t. sync
-+			      * queue. This extra reference is removed
-+			      * only if bfqq->bfqg disappears, to
-+			      * guarantee that this queue is not freed
-+			      * until its group goes away.
-+			      */
-+		bfq_log_bfqq(bfqd, bfqq, "bfqq not in async: %p, %d",
-+			     bfqq, bfqq->ref);
-+		*async_bfqq = bfqq;
-+	}
-+
-+out:
-+	bfqq->ref++; /* get a process reference to this queue */
-+	bfq_log_bfqq(bfqd, bfqq, "at end: %p, %d", bfqq, bfqq->ref);
-+	rcu_read_unlock();
-+	return bfqq;
-+}
-+
-+static void bfq_update_io_thinktime(struct bfq_data *bfqd,
-+				    struct bfq_io_cq *bic)
-+{
-+	struct bfq_ttime *ttime = &bic->ttime;
-+	u64 elapsed = ktime_get_ns() - bic->ttime.last_end_request;
-+
-+	elapsed = min_t(u64, elapsed, 2 * bfqd->bfq_slice_idle);
-+
-+	ttime->ttime_samples = (7*bic->ttime.ttime_samples + 256) / 8;
-+	ttime->ttime_total = div_u64(7*ttime->ttime_total + 256*elapsed,  8);
-+	ttime->ttime_mean = div64_ul(ttime->ttime_total + 128,
-+				     ttime->ttime_samples);
-+}
-+
-+static void
-+bfq_update_io_seektime(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+		       struct request *rq)
-+{
-+	bfqq->seek_history <<= 1;
-+	bfqq->seek_history |=
-+		get_sdist(bfqq->last_request_pos, rq) > BFQQ_SEEK_THR &&
-+		(!blk_queue_nonrot(bfqd->queue) ||
-+		 blk_rq_sectors(rq) < BFQQ_SECT_THR_NONROT);
-+}
-+
-+static void bfq_update_has_short_ttime(struct bfq_data *bfqd,
-+				       struct bfq_queue *bfqq,
-+				       struct bfq_io_cq *bic)
-+{
-+	bool has_short_ttime = true;
-+
-+	/*
-+	 * No need to update has_short_ttime if bfqq is async or in
-+	 * idle io prio class, or if bfq_slice_idle is zero, because
-+	 * no device idling is performed for bfqq in this case.
-+	 */
-+	if (!bfq_bfqq_sync(bfqq) || bfq_class_idle(bfqq) ||
-+	    bfqd->bfq_slice_idle == 0)
-+		return;
-+
-+	/* Idle window just restored, statistics are meaningless. */
-+	if (time_is_after_eq_jiffies(bfqq->split_time +
-+				     bfqd->bfq_wr_min_idle_time))
-+		return;
-+
-+	/* Think time is infinite if no process is linked to
-+	 * bfqq. Otherwise check average think time to
-+	 * decide whether to mark as has_short_ttime
-+	 */
-+	if (atomic_read(&bic->icq.ioc->active_ref) == 0 ||
-+	    (bfq_sample_valid(bic->ttime.ttime_samples) &&
-+	     bic->ttime.ttime_mean > bfqd->bfq_slice_idle))
-+		has_short_ttime = false;
-+
-+	bfq_log_bfqq(bfqd, bfqq, "has_short_ttime %d",
-+		has_short_ttime);
-+
-+	if (has_short_ttime)
-+		bfq_mark_bfqq_has_short_ttime(bfqq);
-+	else
-+		bfq_clear_bfqq_has_short_ttime(bfqq);
-+}
-+
-+/*
-+ * Called when a new fs request (rq) is added to bfqq.  Check if there's
-+ * something we should do about it.
-+ */
-+static void bfq_rq_enqueued(struct bfq_data *bfqd, struct bfq_queue *bfqq,
-+			    struct request *rq)
-+{
-+	struct bfq_io_cq *bic = RQ_BIC(rq);
-+
-+	if (rq->cmd_flags & REQ_META)
-+		bfqq->meta_pending++;
-+
-+	bfq_update_io_thinktime(bfqd, bic);
-+	bfq_update_has_short_ttime(bfqd, bfqq, bic);
-+	bfq_update_io_seektime(bfqd, bfqq, rq);
-+
-+	bfq_log_bfqq(bfqd, bfqq,
-+		     "has_short_ttime=%d (seeky %d)",
-+		     bfq_bfqq_has_short_ttime(bfqq), BFQQ_SEEKY(bfqq));
-+
-+	bfqq->last_request_pos = blk_rq_pos(rq) + blk_rq_sectors(rq);
-+
-+	if (bfqq == bfqd->in_service_queue && bfq_bfqq_wait_request(bfqq)) {
-+		bool small_req = bfqq->queued[rq_is_sync(rq)] == 1 &&
-+				 blk_rq_sectors(rq) < 32;
-+		bool budget_timeout = bfq_bfqq_budget_timeout(bfqq);
-+
-+		/*
-+		 * There is just this request queued: if the request
-+		 * is small and the queue is not to be expired, then
-+		 * just exit.
-+		 *
-+		 * In this way, if the device is being idled to wait
-+		 * for a new request from the in-service queue, we
-+		 * avoid unplugging the device and committing the
-+		 * device to serve just a small request. On the
-+		 * contrary, we wait for the block layer to decide
-+		 * when to unplug the device: hopefully, new requests
-+		 * will be merged to this one quickly, then the device
-+		 * will be unplugged and larger requests will be
-+		 * dispatched.
-+		 */
-+		if (small_req && !budget_timeout)
-+			return;
-+
-+		/*
-+		 * A large enough request arrived, or the queue is to
-+		 * be expired: in both cases disk idling is to be
-+		 * stopped, so clear wait_request flag and reset
-+		 * timer.
-+		 */
-+		bfq_clear_bfqq_wait_request(bfqq);
-+		hrtimer_try_to_cancel(&bfqd->idle_slice_timer);
-+		bfqg_stats_update_idle_time(bfqq_group(bfqq));
-+
-+		/*
-+		 * The queue is not empty, because a new request just
-+		 * arrived. Hence we can safely expire the queue, in
-+		 * case of budget timeout, without risking that the
-+		 * timestamps of the queue are not updated correctly.
-+		 * See [1] for more details.
-+		 */
-+		if (budget_timeout)
-+			bfq_bfqq_expire(bfqd, bfqq, false,
-+					BFQ_BFQQ_BUDGET_TIMEOUT);
-+
-+		/*
-+		 * Let the request rip immediately, or let a new queue be
-+		 * selected if bfqq has just been expired.
-+		 */
-+		__blk_run_queue(bfqd->queue);
-+	}
-+}
-+
-+static void bfq_insert_request(struct request_queue *q, struct request *rq)
-+{
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+	struct bfq_queue *bfqq = RQ_BFQQ(rq), *new_bfqq;
-+
-+	assert_spin_locked(bfqd->queue->queue_lock);
-+
-+	/*
-+	 * An unplug may trigger a requeue of a request from the device
-+	 * driver: make sure we are in process context while trying to
-+	 * merge two bfq_queues.
-+	 */
-+	if (!in_interrupt()) {
-+		new_bfqq = bfq_setup_cooperator(bfqd, bfqq, rq, true);
-+		if (new_bfqq) {
-+			if (bic_to_bfqq(RQ_BIC(rq), 1) != bfqq)
-+				new_bfqq = bic_to_bfqq(RQ_BIC(rq), 1);
-+			/*
-+			 * Release the request's reference to the old bfqq
-+			 * and make sure one is taken to the shared queue.
-+			 */
-+			new_bfqq->allocated[rq_data_dir(rq)]++;
-+			bfqq->allocated[rq_data_dir(rq)]--;
-+			new_bfqq->ref++;
-+			if (bic_to_bfqq(RQ_BIC(rq), 1) == bfqq)
-+				bfq_merge_bfqqs(bfqd, RQ_BIC(rq),
-+						bfqq, new_bfqq);
-+
-+			bfq_clear_bfqq_just_created(bfqq);
-+			/*
-+			 * rq is about to be enqueued into new_bfqq,
-+			 * release rq reference on bfqq
-+			 */
-+			bfq_put_queue(bfqq);
-+			rq->elv.priv[1] = new_bfqq;
-+			bfqq = new_bfqq;
-+		}
-+	}
-+
-+	bfq_add_request(rq);
-+
-+	rq->fifo_time = ktime_get_ns() + bfqd->bfq_fifo_expire[rq_is_sync(rq)];
-+	list_add_tail(&rq->queuelist, &bfqq->fifo);
-+
-+	bfq_rq_enqueued(bfqd, bfqq, rq);
-+}
-+
-+static void bfq_update_hw_tag(struct bfq_data *bfqd)
-+{
-+	bfqd->max_rq_in_driver = max_t(int, bfqd->max_rq_in_driver,
-+				       bfqd->rq_in_driver);
-+
-+	if (bfqd->hw_tag == 1)
-+		return;
-+
-+	/*
-+	 * This sample is valid if the number of outstanding requests
-+	 * is large enough to allow a queueing behavior.  Note that the
-+	 * sum is not exact, as it's not taking into account deactivated
-+	 * requests.
-+	 */
-+	if (bfqd->rq_in_driver + bfqd->queued < BFQ_HW_QUEUE_THRESHOLD)
-+		return;
-+
-+	if (bfqd->hw_tag_samples++ < BFQ_HW_QUEUE_SAMPLES)
-+		return;
-+
-+	bfqd->hw_tag = bfqd->max_rq_in_driver > BFQ_HW_QUEUE_THRESHOLD;
-+	bfqd->max_rq_in_driver = 0;
-+	bfqd->hw_tag_samples = 0;
-+}
-+
-+static void bfq_completed_request(struct request_queue *q, struct request *rq)
-+{
-+	struct bfq_queue *bfqq = RQ_BFQQ(rq);
-+	struct bfq_data *bfqd = bfqq->bfqd;
-+	u64 now_ns;
-+	u32 delta_us;
-+
-+	bfq_log_bfqq(bfqd, bfqq, "completed one req with %u sects left",
-+		     blk_rq_sectors(rq));
-+
-+	assert_spin_locked(bfqd->queue->queue_lock);
-+	bfq_update_hw_tag(bfqd);
-+
-+	BUG_ON(!bfqd->rq_in_driver);
-+	BUG_ON(!bfqq->dispatched);
-+	bfqd->rq_in_driver--;
-+	bfqq->dispatched--;
-+	bfqg_stats_update_completion(bfqq_group(bfqq),
-+				     rq->start_time_ns,
-+				     rq->io_start_time_ns,
-+				     rq->cmd_flags);
-+
-+	if (!bfqq->dispatched && !bfq_bfqq_busy(bfqq)) {
-+		BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list));
-+		/*
-+		 * Set budget_timeout (which we overload to store the
-+		 * time at which the queue remains with no backlog and
-+		 * no outstanding request; used by the weight-raising
-+		 * mechanism).
-+		 */
-+		bfqq->budget_timeout = jiffies;
-+
-+		bfq_weights_tree_remove(bfqd, bfqq);
-+	}
-+
-+	now_ns = ktime_get_ns();
-+
-+	RQ_BIC(rq)->ttime.last_end_request = now_ns;
-+
-+	/*
-+	 * Using us instead of ns, to get a reasonable precision in
-+	 * computing rate in next check.
-+	 */
-+	delta_us = div_u64(now_ns - bfqd->last_completion, NSEC_PER_USEC);
-+
-+	bfq_log(bfqd, "delta %uus/%luus max_size %u rate %llu/%llu",
-+		delta_us, BFQ_MIN_TT/NSEC_PER_USEC, bfqd->last_rq_max_size,
-+		delta_us > 0 ?
-+		(USEC_PER_SEC*
-+		(u64)((bfqd->last_rq_max_size<<BFQ_RATE_SHIFT)/delta_us))
-+			>>BFQ_RATE_SHIFT :
-+		(USEC_PER_SEC*
-+		(u64)(bfqd->last_rq_max_size<<BFQ_RATE_SHIFT))>>BFQ_RATE_SHIFT,
-+		(USEC_PER_SEC*(u64)(1UL<<(BFQ_RATE_SHIFT-10)))>>BFQ_RATE_SHIFT);
-+
-+	/*
-+	 * If the request took rather long to complete, and, according
-+	 * to the maximum request size recorded, this completion latency
-+	 * implies that the request was certainly served at a very low
-+	 * rate (less than 1M sectors/sec), then the whole observation
-+	 * interval that lasts up to this time instant cannot be a
-+	 * valid time interval for computing a new peak rate.  Invoke
-+	 * bfq_update_rate_reset to have the following three steps
-+	 * taken:
-+	 * - close the observation interval at the last (previous)
-+	 *   request dispatch or completion
-+	 * - compute rate, if possible, for that observation interval
-+	 * - reset to zero samples, which will trigger a proper
-+	 *   re-initialization of the observation interval on next
-+	 *   dispatch
-+	 */
-+	if (delta_us > BFQ_MIN_TT/NSEC_PER_USEC &&
-+	   (bfqd->last_rq_max_size<<BFQ_RATE_SHIFT)/delta_us <
-+			1UL<<(BFQ_RATE_SHIFT - 10))
-+		bfq_update_rate_reset(bfqd, NULL);
-+	bfqd->last_completion = now_ns;
-+
-+	/*
-+	 * If we are waiting to discover whether the request pattern
-+	 * of the task associated with the queue is actually
-+	 * isochronous, and both requisites for this condition to hold
-+	 * are now satisfied, then compute soft_rt_next_start (see the
-+	 * comments on the function bfq_bfqq_softrt_next_start()). We
-+	 * schedule this delayed check when bfqq expires, if it still
-+	 * has in-flight requests.
-+	 */
-+	if (bfq_bfqq_softrt_update(bfqq) && bfqq->dispatched == 0 &&
-+	    RB_EMPTY_ROOT(&bfqq->sort_list))
-+		bfqq->soft_rt_next_start =
-+			bfq_bfqq_softrt_next_start(bfqd, bfqq);
-+
-+	/*
-+	 * If this is the in-service queue, check if it needs to be expired,
-+	 * or if we want to idle in case it has no pending requests.
-+	 */
-+	if (bfqd->in_service_queue == bfqq) {
-+		if (bfq_bfqq_must_idle(bfqq)) {
-+			if (bfqq->dispatched == 0)
-+				bfq_arm_slice_timer(bfqd);
-+			/*
-+			 * If we get here, we do not expire bfqq, even
-+			 * if bfqq was in budget timeout or had no
-+			 * more requests (as controlled in the next
-+			 * conditional instructions). The reason for
-+			 * not expiring bfqq is as follows.
-+			 *
-+			 * Here bfqq->dispatched > 0 holds, but
-+			 * bfq_bfqq_must_idle() returned true. This
-+			 * implies that, even if no request arrives
-+			 * for bfqq before bfqq->dispatched reaches 0,
-+			 * bfqq will, however, not be expired on the
-+			 * completion event that causes bfqq->dispatch
-+			 * to reach zero. In contrast, on this event,
-+			 * bfqq will start enjoying device idling
-+			 * (I/O-dispatch plugging).
-+			 *
-+			 * But, if we expired bfqq here, bfqq would
-+			 * not have the chance to enjoy device idling
-+			 * when bfqq->dispatched finally reaches
-+			 * zero. This would expose bfqq to violation
-+			 * of its reserved service guarantees.
-+			 */
-+			goto out;
-+		} else if (bfq_may_expire_for_budg_timeout(bfqq))
-+			bfq_bfqq_expire(bfqd, bfqq, false,
-+					BFQ_BFQQ_BUDGET_TIMEOUT);
-+		else if (RB_EMPTY_ROOT(&bfqq->sort_list) &&
-+			 (bfqq->dispatched == 0 ||
-+			  !bfq_better_to_idle(bfqq)))
-+			bfq_bfqq_expire(bfqd, bfqq, false,
-+					BFQ_BFQQ_NO_MORE_REQUESTS);
-+	}
-+
-+	if (!bfqd->rq_in_driver)
-+		bfq_schedule_dispatch(bfqd);
-+
-+out:
-+	return;
-+}
-+
-+static int __bfq_may_queue(struct bfq_queue *bfqq)
-+{
-+	if (bfq_bfqq_wait_request(bfqq) && bfq_bfqq_must_alloc(bfqq)) {
-+		bfq_clear_bfqq_must_alloc(bfqq);
-+		return ELV_MQUEUE_MUST;
-+	}
-+
-+	return ELV_MQUEUE_MAY;
-+}
-+
-+static int bfq_may_queue(struct request_queue *q, unsigned int op)
-+{
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+	struct task_struct *tsk = current;
-+	struct bfq_io_cq *bic;
-+	struct bfq_queue *bfqq;
-+
-+	/*
-+	 * Don't force setup of a queue from here, as a call to may_queue
-+	 * does not necessarily imply that a request actually will be
-+	 * queued. So just lookup a possibly existing queue, or return
-+	 * 'may queue' if that fails.
-+	 */
-+	bic = bfq_bic_lookup(bfqd, tsk->io_context);
-+	if (!bic)
-+		return ELV_MQUEUE_MAY;
-+
-+	bfqq = bic_to_bfqq(bic, op_is_sync(op));
-+	if (bfqq)
-+		return __bfq_may_queue(bfqq);
-+
-+	return ELV_MQUEUE_MAY;
-+}
-+
-+/*
-+ * Queue lock held here.
-+ */
-+static void bfq_put_request(struct request *rq)
-+{
-+	struct bfq_queue *bfqq = RQ_BFQQ(rq);
-+
-+	if (bfqq) {
-+		const int rw = rq_data_dir(rq);
-+
-+		BUG_ON(!bfqq->allocated[rw]);
-+		bfqq->allocated[rw]--;
-+
-+		rq->elv.priv[0] = NULL;
-+		rq->elv.priv[1] = NULL;
-+
-+		bfq_log_bfqq(bfqq->bfqd, bfqq, "%p, %d",
-+			     bfqq, bfqq->ref);
-+		bfq_put_queue(bfqq);
-+	}
-+}
-+
-+/*
-+ * Returns NULL if a new bfqq should be allocated, or the old bfqq if this
-+ * was the last process referring to that bfqq.
-+ */
-+static struct bfq_queue *
-+bfq_split_bfqq(struct bfq_io_cq *bic, struct bfq_queue *bfqq)
-+{
-+	bfq_log_bfqq(bfqq->bfqd, bfqq, "splitting queue");
-+
-+	put_io_context(bic->icq.ioc);
-+
-+	if (bfqq_process_refs(bfqq) == 1) {
-+		bfqq->pid = current->pid;
-+		bfq_clear_bfqq_coop(bfqq);
-+		bfq_clear_bfqq_split_coop(bfqq);
-+		return bfqq;
-+	}
-+
-+	bic_set_bfqq(bic, NULL, 1);
-+
-+	bfq_put_cooperator(bfqq);
-+
-+	bfq_put_queue(bfqq);
-+	return NULL;
-+}
-+
-+/*
-+ * Allocate bfq data structures associated with this request.
-+ */
-+static int bfq_set_request(struct request_queue *q, struct request *rq,
-+			   struct bio *bio, gfp_t gfp_mask)
-+{
-+	struct bfq_data *bfqd = q->elevator->elevator_data;
-+	struct bfq_io_cq *bic = icq_to_bic(rq->elv.icq);
-+	const int rw = rq_data_dir(rq);
-+	const int is_sync = rq_is_sync(rq);
-+	struct bfq_queue *bfqq;
-+	unsigned long flags;
-+	bool bfqq_already_existing = false, split = false;
-+
-+	spin_lock_irqsave(q->queue_lock, flags);
-+
-+	if (!bic)
-+		goto queue_fail;
-+
-+	bfq_check_ioprio_change(bic, bio);
-+
-+	bfq_bic_update_cgroup(bic, bio);
-+
-+new_queue:
-+	bfqq = bic_to_bfqq(bic, is_sync);
-+	if (!bfqq || bfqq == &bfqd->oom_bfqq) {
-+		if (bfqq)
-+			bfq_put_queue(bfqq);
-+		bfqq = bfq_get_queue(bfqd, bio, is_sync, bic);
-+		BUG_ON(!hlist_unhashed(&bfqq->burst_list_node));
-+
-+		bic_set_bfqq(bic, bfqq, is_sync);
-+		if (split && is_sync) {
-+			bfq_log_bfqq(bfqd, bfqq,
-+				     "was_in_list %d "
-+				     "was_in_large_burst %d "
-+				     "large burst in progress %d",
-+				     bic->was_in_burst_list,
-+				     bic->saved_in_large_burst,
-+				     bfqd->large_burst);
-+
-+			if ((bic->was_in_burst_list && bfqd->large_burst) ||
-+			    bic->saved_in_large_burst) {
-+				bfq_log_bfqq(bfqd, bfqq,
-+					     "marking in "
-+					     "large burst");
-+				bfq_mark_bfqq_in_large_burst(bfqq);
-+			} else {
-+				bfq_log_bfqq(bfqd, bfqq,
-+					     "clearing in "
-+					     "large burst");
-+				bfq_clear_bfqq_in_large_burst(bfqq);
-+				if (bic->was_in_burst_list)
-+					/*
-+					 * If bfqq was in the current
-+					 * burst list before being
-+					 * merged, then we have to add
-+					 * it back. And we do not need
-+					 * to increase burst_size, as
-+					 * we did not decrement
-+					 * burst_size when we removed
-+					 * bfqq from the burst list as
-+					 * a consequence of a merge
-+					 * (see comments in
-+					 * bfq_put_queue). In this
-+					 * respect, it would be rather
-+					 * costly to know whether the
-+					 * current burst list is still
-+					 * the same burst list from
-+					 * which bfqq was removed on
-+					 * the merge. To avoid this
-+					 * cost, if bfqq was in a
-+					 * burst list, then we add
-+					 * bfqq to the current burst
-+					 * list without any further
-+					 * check. This can cause
-+					 * inappropriate insertions,
-+					 * but rarely enough to not
-+					 * harm the detection of large
-+					 * bursts significantly.
-+					 */
-+					hlist_add_head(&bfqq->burst_list_node,
-+						       &bfqd->burst_list);
-+			}
-+			bfqq->split_time = jiffies;
-+		}
-+	} else {
-+		/* If the queue was seeky for too long, break it apart. */
-+		if (bfq_bfqq_coop(bfqq) && bfq_bfqq_split_coop(bfqq)) {
-+			bfq_log_bfqq(bfqd, bfqq, "breaking apart bfqq");
-+
-+			/* Update bic before losing reference to bfqq */
-+			if (bfq_bfqq_in_large_burst(bfqq))
-+				bic->saved_in_large_burst = true;
-+
-+			bfqq = bfq_split_bfqq(bic, bfqq);
-+			split = true;
-+			if (!bfqq)
-+				goto new_queue;
-+			else
-+				bfqq_already_existing = true;
-+		}
-+	}
-+
-+	bfqq->allocated[rw]++;
-+	bfqq->ref++;
-+	bfq_log_bfqq(bfqd, bfqq, "bfqq %p, %d", bfqq, bfqq->ref);
-+
-+	rq->elv.priv[0] = bic;
-+	rq->elv.priv[1] = bfqq;
-+
-+	/*
-+	 * If a bfq_queue has only one process reference, it is owned
-+	 * by only one bfq_io_cq: we can set the bic field of the
-+	 * bfq_queue to the address of that structure. Also, if the
-+	 * queue has just been split, mark a flag so that the
-+	 * information is available to the other scheduler hooks.
-+	 */
-+	if (likely(bfqq != &bfqd->oom_bfqq) && bfqq_process_refs(bfqq) == 1) {
-+		bfqq->bic = bic;
-+		if (split) {
-+			/*
-+			 * If the queue has just been split from a shared
-+			 * queue, restore the idle window and the possible
-+			 * weight raising period.
-+			 */
-+			bfq_bfqq_resume_state(bfqq, bfqd, bic,
-+					      bfqq_already_existing);
-+		}
-+	}
-+
-+	if (unlikely(bfq_bfqq_just_created(bfqq)))
-+		bfq_handle_burst(bfqd, bfqq);
-+
-+	spin_unlock_irqrestore(q->queue_lock, flags);
-+
-+	return 0;
-+
-+queue_fail:
-+	bfq_schedule_dispatch(bfqd);
-+	spin_unlock_irqrestore(q->queue_lock, flags);
-+
-+	return 1;
-+}
-+
-+static void bfq_kick_queue(struct work_struct *work)
-+{
-+	struct bfq_data *bfqd =
-+		container_of(work, struct bfq_data, unplug_work);
-+	struct request_queue *q = bfqd->queue;
-+
-+	spin_lock_irq(q->queue_lock);
-+	__blk_run_queue(q);
-+	spin_unlock_irq(q->queue_lock);
-+}
-+
-+/*
-+ * Handler of the expiration of the timer running if the in-service queue
-+ * is idling inside its time slice.
-+ */
-+static enum hrtimer_restart bfq_idle_slice_timer(struct hrtimer *timer)
-+{
-+	struct bfq_data *bfqd = container_of(timer, struct bfq_data,
-+					     idle_slice_timer);
-+	struct bfq_queue *bfqq;
-+	unsigned long flags;
-+	enum bfqq_expiration reason;
-+
-+	spin_lock_irqsave(bfqd->queue->queue_lock, flags);
-+
-+	bfqq = bfqd->in_service_queue;
-+	/*
-+	 * Theoretical race here: the in-service queue can be NULL or
-+	 * different from the queue that was idling if the timer handler
-+	 * spins on the queue_lock and a new request arrives for the
-+	 * current queue and there is a full dispatch cycle that changes
-+	 * the in-service queue.  This can hardly happen, but in the worst
-+	 * case we just expire a queue too early.
-+	 */
-+	if (bfqq) {
-+		bfq_log_bfqq(bfqd, bfqq, "expired");
-+		bfq_clear_bfqq_wait_request(bfqq);
-+
-+		if (bfq_bfqq_budget_timeout(bfqq))
-+			/*
-+			 * Also here the queue can be safely expired
-+			 * for budget timeout without wasting
-+			 * guarantees
-+			 */
-+			reason = BFQ_BFQQ_BUDGET_TIMEOUT;
-+		else if (bfqq->queued[0] == 0 && bfqq->queued[1] == 0)
-+			/*
-+			 * The queue may not be empty upon timer expiration,
-+			 * because we may not disable the timer when the
-+			 * first request of the in-service queue arrives
-+			 * during disk idling.
-+			 */
-+			reason = BFQ_BFQQ_TOO_IDLE;
-+		else
-+			goto schedule_dispatch;
-+
-+		bfq_bfqq_expire(bfqd, bfqq, true, reason);
-+	}
-+
-+schedule_dispatch:
-+	bfq_schedule_dispatch(bfqd);
-+
-+	spin_unlock_irqrestore(bfqd->queue->queue_lock, flags);
-+	return HRTIMER_NORESTART;
-+}
-+
-+static void bfq_shutdown_timer_wq(struct bfq_data *bfqd)
-+{
-+	hrtimer_cancel(&bfqd->idle_slice_timer);
-+	cancel_work_sync(&bfqd->unplug_work);
-+}
-+
-+static void __bfq_put_async_bfqq(struct bfq_data *bfqd,
-+				 struct bfq_queue **bfqq_ptr)
-+{
-+	struct bfq_group *root_group = bfqd->root_group;
-+	struct bfq_queue *bfqq = *bfqq_ptr;
-+
-+	bfq_log(bfqd, "%p", bfqq);
-+	if (bfqq) {
-+		bfq_bfqq_move(bfqd, bfqq, root_group);
-+		bfq_log_bfqq(bfqd, bfqq, "putting %p, %d",
-+			     bfqq, bfqq->ref);
-+		bfq_put_queue(bfqq);
-+		*bfqq_ptr = NULL;
-+	}
-+}
-+
-+/*
-+ * Release all the bfqg references to its async queues.  If we are
-+ * deallocating the group these queues may still contain requests, so
-+ * we reparent them to the root cgroup (i.e., the only one that will
-+ * exist for sure until all the requests on a device are gone).
-+ */
-+static void bfq_put_async_queues(struct bfq_data *bfqd, struct bfq_group *bfqg)
-+{
-+	int i, j;
-+
-+	for (i = 0; i < 2; i++)
-+		for (j = 0; j < IOPRIO_BE_NR; j++)
-+			__bfq_put_async_bfqq(bfqd, &bfqg->async_bfqq[i][j]);
-+
-+	__bfq_put_async_bfqq(bfqd, &bfqg->async_idle_bfqq);
-+}
-+
-+static void bfq_exit_queue(struct elevator_queue *e)
-+{
-+	struct bfq_data *bfqd = e->elevator_data;
-+	struct request_queue *q = bfqd->queue;
-+	struct bfq_queue *bfqq, *n;
-+
-+	bfq_shutdown_timer_wq(bfqd);
-+
-+	spin_lock_irq(q->queue_lock);
-+
-+	BUG_ON(bfqd->in_service_queue);
-+	list_for_each_entry_safe(bfqq, n, &bfqd->idle_list, bfqq_list)
-+		bfq_deactivate_bfqq(bfqd, bfqq, false, false);
-+
-+	spin_unlock_irq(q->queue_lock);
-+
-+	bfq_shutdown_timer_wq(bfqd);
-+
-+	BUG_ON(hrtimer_active(&bfqd->idle_slice_timer));
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	/* release oom-queue reference to root group */
-+	bfqg_put(bfqd->root_group);
-+
-+	blkcg_deactivate_policy(q, &blkcg_policy_bfq);
-+#else
-+	bfq_put_async_queues(bfqd, bfqd->root_group);
-+	kfree(bfqd->root_group);
-+#endif
-+
-+	kfree(bfqd);
-+}
-+
-+static void bfq_init_root_group(struct bfq_group *root_group,
-+				struct bfq_data *bfqd)
-+{
-+	int i;
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	root_group->entity.parent = NULL;
-+	root_group->my_entity = NULL;
-+	root_group->bfqd = bfqd;
-+#endif
-+	root_group->rq_pos_tree = RB_ROOT;
-+	for (i = 0; i < BFQ_IOPRIO_CLASSES; i++)
-+		root_group->sched_data.service_tree[i] = BFQ_SERVICE_TREE_INIT;
-+	root_group->sched_data.bfq_class_idle_last_service = jiffies;
-+}
-+
-+static int bfq_init_queue(struct request_queue *q, struct elevator_type *e)
-+{
-+	struct bfq_data *bfqd;
-+	struct elevator_queue *eq;
-+
-+	eq = elevator_alloc(q, e);
-+	if (!eq)
-+		return -ENOMEM;
-+
-+	bfqd = kzalloc_node(sizeof(*bfqd), GFP_KERNEL, q->node);
-+	if (!bfqd) {
-+		kobject_put(&eq->kobj);
-+		return -ENOMEM;
-+	}
-+	eq->elevator_data = bfqd;
-+
-+	/*
-+	 * Our fallback bfqq if bfq_find_alloc_queue() runs into OOM issues.
-+	 * Grab a permanent reference to it, so that the normal code flow
-+	 * will not attempt to free it.
-+	 */
-+	bfq_init_bfqq(bfqd, &bfqd->oom_bfqq, NULL, 1, 0);
-+	bfqd->oom_bfqq.ref++;
-+	bfqd->oom_bfqq.new_ioprio = BFQ_DEFAULT_QUEUE_IOPRIO;
-+	bfqd->oom_bfqq.new_ioprio_class = IOPRIO_CLASS_BE;
-+	bfqd->oom_bfqq.entity.new_weight =
-+		bfq_ioprio_to_weight(bfqd->oom_bfqq.new_ioprio);
-+
-+	/* oom_bfqq does not participate to bursts */
-+	bfq_clear_bfqq_just_created(&bfqd->oom_bfqq);
-+	/*
-+	 * Trigger weight initialization, according to ioprio, at the
-+	 * oom_bfqq's first activation. The oom_bfqq's ioprio and ioprio
-+	 * class won't be changed any more.
-+	 */
-+	bfqd->oom_bfqq.entity.prio_changed = 1;
-+
-+	bfqd->queue = q;
-+
-+	spin_lock_irq(q->queue_lock);
-+	q->elevator = eq;
-+	spin_unlock_irq(q->queue_lock);
-+
-+	bfqd->root_group = bfq_create_group_hierarchy(bfqd, q->node);
-+	if (!bfqd->root_group)
-+		goto out_free;
-+	bfq_init_root_group(bfqd->root_group, bfqd);
-+	bfq_init_entity(&bfqd->oom_bfqq.entity, bfqd->root_group);
-+
-+	hrtimer_init(&bfqd->idle_slice_timer, CLOCK_MONOTONIC,
-+		     HRTIMER_MODE_REL);
-+	bfqd->idle_slice_timer.function = bfq_idle_slice_timer;
-+
-+	bfqd->queue_weights_tree = RB_ROOT;
-+	bfqd->group_weights_tree = RB_ROOT;
-+
-+	INIT_WORK(&bfqd->unplug_work, bfq_kick_queue);
-+
-+	INIT_LIST_HEAD(&bfqd->active_list);
-+	INIT_LIST_HEAD(&bfqd->idle_list);
-+	INIT_HLIST_HEAD(&bfqd->burst_list);
-+
-+	bfqd->hw_tag = -1;
-+
-+	bfqd->bfq_max_budget = bfq_default_max_budget;
-+
-+	bfqd->bfq_fifo_expire[0] = bfq_fifo_expire[0];
-+	bfqd->bfq_fifo_expire[1] = bfq_fifo_expire[1];
-+	bfqd->bfq_back_max = bfq_back_max;
-+	bfqd->bfq_back_penalty = bfq_back_penalty;
-+	bfqd->bfq_slice_idle = bfq_slice_idle;
-+	bfqd->bfq_timeout = bfq_timeout;
-+
-+	bfqd->bfq_requests_within_timer = 120;
-+
-+	bfqd->bfq_large_burst_thresh = 8;
-+	bfqd->bfq_burst_interval = msecs_to_jiffies(180);
-+
-+	bfqd->low_latency = true;
-+
-+	/*
-+	 * Trade-off between responsiveness and fairness.
-+	 */
-+	bfqd->bfq_wr_coeff = 30;
-+	bfqd->bfq_wr_rt_max_time = msecs_to_jiffies(300);
-+	bfqd->bfq_wr_max_time = 0;
-+	bfqd->bfq_wr_min_idle_time = msecs_to_jiffies(2000);
-+	bfqd->bfq_wr_min_inter_arr_async = msecs_to_jiffies(500);
-+	bfqd->bfq_wr_max_softrt_rate = 7000; /*
-+					      * Approximate rate required
-+					      * to playback or record a
-+					      * high-definition compressed
-+					      * video.
-+					      */
-+	bfqd->wr_busy_queues = 0;
-+
-+	/*
-+	 * Begin by assuming, optimistically, that the device peak
-+	 * rate is equal to 2/3 of the highest reference rate.
-+	 */
-+	bfqd->rate_dur_prod = ref_rate[blk_queue_nonrot(bfqd->queue)] *
-+		ref_wr_duration[blk_queue_nonrot(bfqd->queue)];
-+	bfqd->peak_rate = ref_rate[blk_queue_nonrot(bfqd->queue)] * 2 / 3;
-+
-+	return 0;
-+
-+out_free:
-+	kfree(bfqd);
-+	kobject_put(&eq->kobj);
-+	return -ENOMEM;
-+}
-+
-+static void bfq_registered_queue(struct request_queue *q)
-+{
-+	wbt_disable_default(q);
-+}
-+
-+static void bfq_slab_kill(void)
-+{
-+	kmem_cache_destroy(bfq_pool);
-+}
-+
-+static int __init bfq_slab_setup(void)
-+{
-+	bfq_pool = KMEM_CACHE(bfq_queue, 0);
-+	if (!bfq_pool)
-+		return -ENOMEM;
-+	return 0;
-+}
-+
-+static ssize_t bfq_var_show(unsigned int var, char *page)
-+{
-+	return sprintf(page, "%u\n", var);
-+}
-+
-+static ssize_t bfq_var_store(unsigned long *var, const char *page,
-+			     size_t count)
-+{
-+	unsigned long new_val;
-+	int ret = kstrtoul(page, 10, &new_val);
-+
-+	if (ret == 0)
-+		*var = new_val;
-+
-+	return count;
-+}
-+
-+static ssize_t bfq_wr_max_time_show(struct elevator_queue *e, char *page)
-+{
-+	struct bfq_data *bfqd = e->elevator_data;
-+
-+	return sprintf(page, "%d\n", bfqd->bfq_wr_max_time > 0 ?
-+		       jiffies_to_msecs(bfqd->bfq_wr_max_time) :
-+		       jiffies_to_msecs(bfq_wr_duration(bfqd)));
-+}
-+
-+static ssize_t bfq_weights_show(struct elevator_queue *e, char *page)
-+{
-+	struct bfq_queue *bfqq;
-+	struct bfq_data *bfqd = e->elevator_data;
-+	ssize_t num_char = 0;
-+
-+	num_char += sprintf(page + num_char, "Tot reqs queued %d\n\n",
-+			    bfqd->queued);
-+
-+	spin_lock_irq(bfqd->queue->queue_lock);
-+
-+	num_char += sprintf(page + num_char, "Active:\n");
-+	list_for_each_entry(bfqq, &bfqd->active_list, bfqq_list) {
-+		num_char += sprintf(page + num_char,
-+				    "pid%d: weight %hu, nr_queued %d %d, ",
-+				    bfqq->pid,
-+				    bfqq->entity.weight,
-+				    bfqq->queued[0],
-+				    bfqq->queued[1]);
-+		num_char += sprintf(page + num_char,
-+				    "dur %d/%u\n",
-+				    jiffies_to_msecs(
-+					    jiffies -
-+					    bfqq->last_wr_start_finish),
-+				    jiffies_to_msecs(bfqq->wr_cur_max_time));
-+	}
-+
-+	num_char += sprintf(page + num_char, "Idle:\n");
-+	list_for_each_entry(bfqq, &bfqd->idle_list, bfqq_list) {
-+		num_char += sprintf(page + num_char,
-+				    "pid%d: weight %hu, dur %d/%u\n",
-+				    bfqq->pid,
-+				    bfqq->entity.weight,
-+				    jiffies_to_msecs(jiffies -
-+						     bfqq->last_wr_start_finish),
-+				    jiffies_to_msecs(bfqq->wr_cur_max_time));
-+	}
-+
-+	spin_unlock_irq(bfqd->queue->queue_lock);
-+
-+	return num_char;
-+}
-+
-+#define SHOW_FUNCTION(__FUNC, __VAR, __CONV)				\
-+static ssize_t __FUNC(struct elevator_queue *e, char *page)		\
-+{									\
-+	struct bfq_data *bfqd = e->elevator_data;			\
-+	u64 __data = __VAR;						\
-+	if (__CONV == 1)						\
-+		__data = jiffies_to_msecs(__data);			\
-+	else if (__CONV == 2)						\
-+		__data = div_u64(__data, NSEC_PER_MSEC);		\
-+	return bfq_var_show(__data, (page));				\
-+}
-+SHOW_FUNCTION(bfq_fifo_expire_sync_show, bfqd->bfq_fifo_expire[1], 2);
-+SHOW_FUNCTION(bfq_fifo_expire_async_show, bfqd->bfq_fifo_expire[0], 2);
-+SHOW_FUNCTION(bfq_back_seek_max_show, bfqd->bfq_back_max, 0);
-+SHOW_FUNCTION(bfq_back_seek_penalty_show, bfqd->bfq_back_penalty, 0);
-+SHOW_FUNCTION(bfq_slice_idle_show, bfqd->bfq_slice_idle, 2);
-+SHOW_FUNCTION(bfq_max_budget_show, bfqd->bfq_user_max_budget, 0);
-+SHOW_FUNCTION(bfq_timeout_sync_show, bfqd->bfq_timeout, 1);
-+SHOW_FUNCTION(bfq_strict_guarantees_show, bfqd->strict_guarantees, 0);
-+SHOW_FUNCTION(bfq_low_latency_show, bfqd->low_latency, 0);
-+SHOW_FUNCTION(bfq_wr_coeff_show, bfqd->bfq_wr_coeff, 0);
-+SHOW_FUNCTION(bfq_wr_rt_max_time_show, bfqd->bfq_wr_rt_max_time, 1);
-+SHOW_FUNCTION(bfq_wr_min_idle_time_show, bfqd->bfq_wr_min_idle_time, 1);
-+SHOW_FUNCTION(bfq_wr_min_inter_arr_async_show, bfqd->bfq_wr_min_inter_arr_async,
-+	1);
-+SHOW_FUNCTION(bfq_wr_max_softrt_rate_show, bfqd->bfq_wr_max_softrt_rate, 0);
-+#undef SHOW_FUNCTION
-+
-+#define USEC_SHOW_FUNCTION(__FUNC, __VAR)				\
-+static ssize_t __FUNC(struct elevator_queue *e, char *page)		\
-+{									\
-+	struct bfq_data *bfqd = e->elevator_data;			\
-+	u64 __data = __VAR;						\
-+	__data = div_u64(__data, NSEC_PER_USEC);			\
-+	return bfq_var_show(__data, (page));				\
-+}
-+USEC_SHOW_FUNCTION(bfq_slice_idle_us_show, bfqd->bfq_slice_idle);
-+#undef USEC_SHOW_FUNCTION
-+
-+#define STORE_FUNCTION(__FUNC, __PTR, MIN, MAX, __CONV)			\
-+static ssize_t								\
-+__FUNC(struct elevator_queue *e, const char *page, size_t count)	\
-+{									\
-+	struct bfq_data *bfqd = e->elevator_data;			\
-+	unsigned long uninitialized_var(__data);			\
-+	int ret = bfq_var_store(&__data, (page), count);		\
-+	if (__data < (MIN))						\
-+		__data = (MIN);						\
-+	else if (__data > (MAX))					\
-+		__data = (MAX);						\
-+	if (__CONV == 1)						\
-+		*(__PTR) = msecs_to_jiffies(__data);			\
-+	else if (__CONV == 2)						\
-+		*(__PTR) = (u64)__data * NSEC_PER_MSEC;			\
-+	else								\
-+		*(__PTR) = __data;					\
-+	return ret;							\
-+}
-+STORE_FUNCTION(bfq_fifo_expire_sync_store, &bfqd->bfq_fifo_expire[1], 1,
-+		INT_MAX, 2);
-+STORE_FUNCTION(bfq_fifo_expire_async_store, &bfqd->bfq_fifo_expire[0], 1,
-+		INT_MAX, 2);
-+STORE_FUNCTION(bfq_back_seek_max_store, &bfqd->bfq_back_max, 0, INT_MAX, 0);
-+STORE_FUNCTION(bfq_back_seek_penalty_store, &bfqd->bfq_back_penalty, 1,
-+		INT_MAX, 0);
-+STORE_FUNCTION(bfq_slice_idle_store, &bfqd->bfq_slice_idle, 0, INT_MAX, 2);
-+STORE_FUNCTION(bfq_wr_coeff_store, &bfqd->bfq_wr_coeff, 1, INT_MAX, 0);
-+STORE_FUNCTION(bfq_wr_max_time_store, &bfqd->bfq_wr_max_time, 0, INT_MAX, 1);
-+STORE_FUNCTION(bfq_wr_rt_max_time_store, &bfqd->bfq_wr_rt_max_time, 0, INT_MAX,
-+		1);
-+STORE_FUNCTION(bfq_wr_min_idle_time_store, &bfqd->bfq_wr_min_idle_time, 0,
-+		INT_MAX, 1);
-+STORE_FUNCTION(bfq_wr_min_inter_arr_async_store,
-+		&bfqd->bfq_wr_min_inter_arr_async, 0, INT_MAX, 1);
-+STORE_FUNCTION(bfq_wr_max_softrt_rate_store, &bfqd->bfq_wr_max_softrt_rate, 0,
-+		INT_MAX, 0);
-+#undef STORE_FUNCTION
-+
-+#define USEC_STORE_FUNCTION(__FUNC, __PTR, MIN, MAX)			\
-+static ssize_t __FUNC(struct elevator_queue *e, const char *page, size_t count)\
-+{									\
-+	struct bfq_data *bfqd = e->elevator_data;			\
-+	unsigned long uninitialized_var(__data);			\
-+	int ret = bfq_var_store(&__data, (page), count);		\
-+	if (__data < (MIN))						\
-+		__data = (MIN);						\
-+	else if (__data > (MAX))					\
-+		__data = (MAX);						\
-+	*(__PTR) = (u64)__data * NSEC_PER_USEC;				\
-+	return ret;							\
-+}
-+USEC_STORE_FUNCTION(bfq_slice_idle_us_store, &bfqd->bfq_slice_idle, 0,
-+		    UINT_MAX);
-+#undef USEC_STORE_FUNCTION
-+
-+/* do nothing for the moment */
-+static ssize_t bfq_weights_store(struct elevator_queue *e,
-+				    const char *page, size_t count)
-+{
-+	return count;
-+}
-+
-+static ssize_t bfq_max_budget_store(struct elevator_queue *e,
-+				    const char *page, size_t count)
-+{
-+	struct bfq_data *bfqd = e->elevator_data;
-+	unsigned long uninitialized_var(__data);
-+	int ret = bfq_var_store(&__data, (page), count);
-+
-+	if (__data == 0)
-+		bfqd->bfq_max_budget = bfq_calc_max_budget(bfqd);
-+	else {
-+		if (__data > INT_MAX)
-+			__data = INT_MAX;
-+		bfqd->bfq_max_budget = __data;
-+	}
-+
-+	bfqd->bfq_user_max_budget = __data;
-+
-+	return ret;
-+}
-+
-+/*
-+ * Leaving this name to preserve name compatibility with cfq
-+ * parameters, but this timeout is used for both sync and async.
-+ */
-+static ssize_t bfq_timeout_sync_store(struct elevator_queue *e,
-+				      const char *page, size_t count)
-+{
-+	struct bfq_data *bfqd = e->elevator_data;
-+	unsigned long uninitialized_var(__data);
-+	int ret = bfq_var_store(&__data, (page), count);
-+
-+	if (__data < 1)
-+		__data = 1;
-+	else if (__data > INT_MAX)
-+		__data = INT_MAX;
-+
-+	bfqd->bfq_timeout = msecs_to_jiffies(__data);
-+	if (bfqd->bfq_user_max_budget == 0)
-+		bfqd->bfq_max_budget = bfq_calc_max_budget(bfqd);
-+
-+	return ret;
-+}
-+
-+static ssize_t bfq_strict_guarantees_store(struct elevator_queue *e,
-+				     const char *page, size_t count)
-+{
-+	struct bfq_data *bfqd = e->elevator_data;
-+	unsigned long uninitialized_var(__data);
-+	int ret = bfq_var_store(&__data, (page), count);
-+
-+	if (__data > 1)
-+		__data = 1;
-+	if (!bfqd->strict_guarantees && __data == 1
-+	    && bfqd->bfq_slice_idle < 8 * NSEC_PER_MSEC)
-+		bfqd->bfq_slice_idle = 8 * NSEC_PER_MSEC;
-+
-+	bfqd->strict_guarantees = __data;
-+
-+	return ret;
-+}
-+
-+static ssize_t bfq_low_latency_store(struct elevator_queue *e,
-+				     const char *page, size_t count)
-+{
-+	struct bfq_data *bfqd = e->elevator_data;
-+	unsigned long uninitialized_var(__data);
-+	int ret = bfq_var_store(&__data, (page), count);
-+
-+	if (__data > 1)
-+		__data = 1;
-+	if (__data == 0 && bfqd->low_latency != 0)
-+		bfq_end_wr(bfqd);
-+	bfqd->low_latency = __data;
-+
-+	return ret;
-+}
-+
-+#define BFQ_ATTR(name) \
-+	__ATTR(name, S_IRUGO|S_IWUSR, bfq_##name##_show, bfq_##name##_store)
-+
-+static struct elv_fs_entry bfq_attrs[] = {
-+	BFQ_ATTR(fifo_expire_sync),
-+	BFQ_ATTR(fifo_expire_async),
-+	BFQ_ATTR(back_seek_max),
-+	BFQ_ATTR(back_seek_penalty),
-+	BFQ_ATTR(slice_idle),
-+	BFQ_ATTR(slice_idle_us),
-+	BFQ_ATTR(max_budget),
-+	BFQ_ATTR(timeout_sync),
-+	BFQ_ATTR(strict_guarantees),
-+	BFQ_ATTR(low_latency),
-+	BFQ_ATTR(wr_coeff),
-+	BFQ_ATTR(wr_max_time),
-+	BFQ_ATTR(wr_rt_max_time),
-+	BFQ_ATTR(wr_min_idle_time),
-+	BFQ_ATTR(wr_min_inter_arr_async),
-+	BFQ_ATTR(wr_max_softrt_rate),
-+	BFQ_ATTR(weights),
-+	__ATTR_NULL
-+};
-+
-+static struct elevator_type iosched_bfq = {
-+	.ops.sq = {
-+		.elevator_merge_fn =		bfq_merge,
-+		.elevator_merged_fn =		bfq_merged_request,
-+		.elevator_merge_req_fn =	bfq_merged_requests,
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+		.elevator_bio_merged_fn =	bfq_bio_merged,
-+#endif
-+		.elevator_allow_bio_merge_fn =	bfq_allow_bio_merge,
-+		.elevator_allow_rq_merge_fn =	bfq_allow_rq_merge,
-+		.elevator_dispatch_fn =		bfq_dispatch_requests,
-+		.elevator_add_req_fn =		bfq_insert_request,
-+		.elevator_activate_req_fn =	bfq_activate_request,
-+		.elevator_deactivate_req_fn =	bfq_deactivate_request,
-+		.elevator_completed_req_fn =	bfq_completed_request,
-+		.elevator_former_req_fn =	elv_rb_former_request,
-+		.elevator_latter_req_fn =	elv_rb_latter_request,
-+		.elevator_init_icq_fn =		bfq_init_icq,
-+		.elevator_exit_icq_fn =		bfq_exit_icq,
-+		.elevator_set_req_fn =		bfq_set_request,
-+		.elevator_put_req_fn =		bfq_put_request,
-+		.elevator_may_queue_fn =	bfq_may_queue,
-+		.elevator_init_fn =		bfq_init_queue,
-+		.elevator_exit_fn =		bfq_exit_queue,
-+		.elevator_registered_fn =	bfq_registered_queue,
-+	},
-+	.icq_size =		sizeof(struct bfq_io_cq),
-+	.icq_align =		__alignof__(struct bfq_io_cq),
-+	.elevator_attrs =	bfq_attrs,
-+	.elevator_name =	"bfq-sq",
-+	.elevator_owner =	THIS_MODULE,
-+};
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+static struct blkcg_policy blkcg_policy_bfq = {
-+	.dfl_cftypes		= bfq_blkg_files,
-+	.legacy_cftypes		= bfq_blkcg_legacy_files,
-+
-+	.cpd_alloc_fn		= bfq_cpd_alloc,
-+	.cpd_init_fn		= bfq_cpd_init,
-+	.cpd_bind_fn	        = bfq_cpd_init,
-+	.cpd_free_fn		= bfq_cpd_free,
-+
-+	.pd_alloc_fn		= bfq_pd_alloc,
-+	.pd_init_fn		= bfq_pd_init,
-+	.pd_offline_fn		= bfq_pd_offline,
-+	.pd_free_fn		= bfq_pd_free,
-+	.pd_reset_stats_fn	= bfq_pd_reset_stats,
-+};
-+#endif
-+
-+static int __init bfq_init(void)
-+{
-+	int ret;
-+	char msg[60] = "BFQ I/O-scheduler: v8r12";
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	ret = blkcg_policy_register(&blkcg_policy_bfq);
-+	if (ret)
-+		return ret;
-+#endif
-+
-+	ret = -ENOMEM;
-+	if (bfq_slab_setup())
-+		goto err_pol_unreg;
-+
-+	/*
-+	 * Times to load large popular applications for the typical
-+	 * systems installed on the reference devices (see the
-+	 * comments before the definition of the next
-+	 * array). Actually, we use slightly lower values, as the
-+	 * estimated peak rate tends to be smaller than the actual
-+	 * peak rate.  The reason for this last fact is that estimates
-+	 * are computed over much shorter time intervals than the long
-+	 * intervals typically used for benchmarking. Why? First, to
-+	 * adapt more quickly to variations. Second, because an I/O
-+	 * scheduler cannot rely on a peak-rate-evaluation workload to
-+	 * be run for a long time.
-+	 */
-+	ref_wr_duration[0] = msecs_to_jiffies(7000); /* actually 8 sec */
-+	ref_wr_duration[1] = msecs_to_jiffies(2500); /* actually 3 sec */
-+
-+	ret = elv_register(&iosched_bfq);
-+	if (ret)
-+		goto slab_kill;
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	strcat(msg, " (with cgroups support)");
-+#endif
-+	pr_info("%s", msg);
-+
-+	return 0;
-+
-+slab_kill:
-+	bfq_slab_kill();
-+err_pol_unreg:
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	blkcg_policy_unregister(&blkcg_policy_bfq);
-+#endif
-+	return ret;
-+}
-+
-+static void __exit bfq_exit(void)
-+{
-+	elv_unregister(&iosched_bfq);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	blkcg_policy_unregister(&blkcg_policy_bfq);
-+#endif
-+	bfq_slab_kill();
-+}
-+
-+module_init(bfq_init);
-+module_exit(bfq_exit);
-+
-+MODULE_AUTHOR("Arianna Avanzini, Fabio Checconi, Paolo Valente");
-+MODULE_LICENSE("GPL");
-diff --git a/block/bfq.h b/block/bfq.h
-new file mode 100644
-index 000000000000..2850bf053b67
---- /dev/null
-+++ b/block/bfq.h
-@@ -0,0 +1,996 @@
-+/*
-+ * BFQ v8r12 for 4.11.0: data structures and common functions prototypes.
-+ *
-+ * Based on ideas and code from CFQ:
-+ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
-+ *
-+ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
-+ *		      Paolo Valente <paolo.valente@unimore.it>
-+ *
-+ * Copyright (C) 2015 Paolo Valente <paolo.valente@unimore.it>
-+ *
-+ * Copyright (C) 2017 Paolo Valente <paolo.valente@linaro.org>
-+ */
-+
-+#ifndef _BFQ_H
-+#define _BFQ_H
-+
-+#include <linux/hrtimer.h>
-+#include <linux/blk-cgroup.h>
-+
-+/*
-+ * Define an alternative macro to compile cgroups support. This is one
-+ * of the steps needed to let bfq-mq share the files bfq-sched.c and
-+ * bfq-cgroup.c with bfq-sq. For bfq-mq, the macro
-+ * BFQ_GROUP_IOSCHED_ENABLED will be defined as a function of whether
-+ * the configuration option CONFIG_BFQ_MQ_GROUP_IOSCHED, and not
-+ * CONFIG_BFQ_GROUP_IOSCHED, is defined.
-+ */
-+#ifdef CONFIG_BFQ_SQ_GROUP_IOSCHED
-+#define BFQ_GROUP_IOSCHED_ENABLED
-+#endif
-+
-+#define BFQ_IOPRIO_CLASSES	3
-+#define BFQ_CL_IDLE_TIMEOUT	(HZ/5)
-+
-+#define BFQ_MIN_WEIGHT			1
-+#define BFQ_MAX_WEIGHT			1000
-+#define BFQ_WEIGHT_CONVERSION_COEFF	10
-+
-+#define BFQ_DEFAULT_QUEUE_IOPRIO	4
-+
-+#define BFQ_WEIGHT_LEGACY_DFL	100
-+#define BFQ_DEFAULT_GRP_IOPRIO	0
-+#define BFQ_DEFAULT_GRP_CLASS	IOPRIO_CLASS_BE
-+
-+/*
-+ * Soft real-time applications are extremely more latency sensitive
-+ * than interactive ones. Over-raise the weight of the former to
-+ * privilege them against the latter.
-+ */
-+#define BFQ_SOFTRT_WEIGHT_FACTOR	100
-+
-+struct bfq_entity;
-+
-+/**
-+ * struct bfq_service_tree - per ioprio_class service tree.
-+ *
-+ * Each service tree represents a B-WF2Q+ scheduler on its own.  Each
-+ * ioprio_class has its own independent scheduler, and so its own
-+ * bfq_service_tree.  All the fields are protected by the queue lock
-+ * of the containing bfqd.
-+ */
-+struct bfq_service_tree {
-+	/* tree for active entities (i.e., those backlogged) */
-+	struct rb_root active;
-+	/* tree for idle entities (i.e., not backlogged, with V <= F_i)*/
-+	struct rb_root idle;
-+
-+	struct bfq_entity *first_idle;	/* idle entity with minimum F_i */
-+	struct bfq_entity *last_idle;	/* idle entity with maximum F_i */
-+
-+	u64 vtime; /* scheduler virtual time */
-+	/* scheduler weight sum; active and idle entities contribute to it */
-+	unsigned long wsum;
-+};
-+
-+/**
-+ * struct bfq_sched_data - multi-class scheduler.
-+ *
-+ * bfq_sched_data is the basic scheduler queue.  It supports three
-+ * ioprio_classes, and can be used either as a toplevel queue or as an
-+ * intermediate queue in a hierarchical setup.
-+ *
-+ * The supported ioprio_classes are the same as in CFQ, in descending
-+ * priority order, IOPRIO_CLASS_RT, IOPRIO_CLASS_BE, IOPRIO_CLASS_IDLE.
-+ * Requests from higher priority queues are served before all the
-+ * requests from lower priority queues; among requests of the same
-+ * queue requests are served according to B-WF2Q+.
-+ *
-+ * The schedule is implemented by the service trees, plus the field
-+ * @next_in_service, which points to the entity on the active trees
-+ * that will be served next, if 1) no changes in the schedule occurs
-+ * before the current in-service entity is expired, 2) the in-service
-+ * queue becomes idle when it expires, and 3) if the entity pointed by
-+ * in_service_entity is not a queue, then the in-service child entity
-+ * of the entity pointed by in_service_entity becomes idle on
-+ * expiration. This peculiar definition allows for the following
-+ * optimization, not yet exploited: while a given entity is still in
-+ * service, we already know which is the best candidate for next
-+ * service among the other active entitities in the same parent
-+ * entity. We can then quickly compare the timestamps of the
-+ * in-service entity with those of such best candidate.
-+ *
-+ * All the fields are protected by the queue lock of the containing
-+ * bfqd.
-+ */
-+struct bfq_sched_data {
-+	struct bfq_entity *in_service_entity;  /* entity in service */
-+	/* head-of-the-line entity in the scheduler (see comments above) */
-+	struct bfq_entity *next_in_service;
-+	/* array of service trees, one per ioprio_class */
-+	struct bfq_service_tree service_tree[BFQ_IOPRIO_CLASSES];
-+	/* last time CLASS_IDLE was served */
-+	unsigned long bfq_class_idle_last_service;
-+
-+};
-+
-+/**
-+ * struct bfq_weight_counter - counter of the number of all active entities
-+ *                             with a given weight.
-+ */
-+struct bfq_weight_counter {
-+	unsigned int weight; /* weight of the entities this counter refers to */
-+	unsigned int num_active; /* nr of active entities with this weight */
-+	/*
-+	 * Weights tree member (see bfq_data's @queue_weights_tree and
-+	 * @group_weights_tree)
-+	 */
-+	struct rb_node weights_node;
-+};
-+
-+/**
-+ * struct bfq_entity - schedulable entity.
-+ *
-+ * A bfq_entity is used to represent either a bfq_queue (leaf node in the
-+ * cgroup hierarchy) or a bfq_group into the upper level scheduler.  Each
-+ * entity belongs to the sched_data of the parent group in the cgroup
-+ * hierarchy.  Non-leaf entities have also their own sched_data, stored
-+ * in @my_sched_data.
-+ *
-+ * Each entity stores independently its priority values; this would
-+ * allow different weights on different devices, but this
-+ * functionality is not exported to userspace by now.  Priorities and
-+ * weights are updated lazily, first storing the new values into the
-+ * new_* fields, then setting the @prio_changed flag.  As soon as
-+ * there is a transition in the entity state that allows the priority
-+ * update to take place the effective and the requested priority
-+ * values are synchronized.
-+ *
-+ * Unless cgroups are used, the weight value is calculated from the
-+ * ioprio to export the same interface as CFQ.  When dealing with
-+ * ``well-behaved'' queues (i.e., queues that do not spend too much
-+ * time to consume their budget and have true sequential behavior, and
-+ * when there are no external factors breaking anticipation) the
-+ * relative weights at each level of the cgroups hierarchy should be
-+ * guaranteed.  All the fields are protected by the queue lock of the
-+ * containing bfqd.
-+ */
-+struct bfq_entity {
-+	struct rb_node rb_node; /* service_tree member */
-+	/* pointer to the weight counter associated with this entity */
-+	struct bfq_weight_counter *weight_counter;
-+
-+	/*
-+	 * Flag, true if the entity is on a tree (either the active or
-+	 * the idle one of its service_tree) or is in service.
-+	 */
-+	bool on_st;
-+
-+	u64 finish; /* B-WF2Q+ finish timestamp (aka F_i) */
-+	u64 start;  /* B-WF2Q+ start timestamp (aka S_i) */
-+
-+	/* tree the entity is enqueued into; %NULL if not on a tree */
-+	struct rb_root *tree;
-+
-+	/*
-+	 * minimum start time of the (active) subtree rooted at this
-+	 * entity; used for O(log N) lookups into active trees
-+	 */
-+	u64 min_start;
-+
-+	/* amount of service received during the last service slot */
-+	int service;
-+
-+	/* budget, used also to calculate F_i: F_i = S_i + @budget / @weight */
-+	int budget;
-+
-+	unsigned int weight;	 /* weight of the queue */
-+	unsigned int new_weight; /* next weight if a change is in progress */
-+
-+	/* original weight, used to implement weight boosting */
-+	unsigned int orig_weight;
-+
-+	/* parent entity, for hierarchical scheduling */
-+	struct bfq_entity *parent;
-+
-+	/*
-+	 * For non-leaf nodes in the hierarchy, the associated
-+	 * scheduler queue, %NULL on leaf nodes.
-+	 */
-+	struct bfq_sched_data *my_sched_data;
-+	/* the scheduler queue this entity belongs to */
-+	struct bfq_sched_data *sched_data;
-+
-+	/* flag, set to request a weight, ioprio or ioprio_class change  */
-+	int prio_changed;
-+};
-+
-+struct bfq_group;
-+
-+/**
-+ * struct bfq_queue - leaf schedulable entity.
-+ *
-+ * A bfq_queue is a leaf request queue; it can be associated with an
-+ * io_context or more, if it  is  async or shared  between  cooperating
-+ * processes. @cgroup holds a reference to the cgroup, to be sure that it
-+ * does not disappear while a bfqq still references it (mostly to avoid
-+ * races between request issuing and task migration followed by cgroup
-+ * destruction).
-+ * All the fields are protected by the queue lock of the containing bfqd.
-+ */
-+struct bfq_queue {
-+	/* reference counter */
-+	int ref;
-+	/* parent bfq_data */
-+	struct bfq_data *bfqd;
-+
-+	/* current ioprio and ioprio class */
-+	unsigned short ioprio, ioprio_class;
-+	/* next ioprio and ioprio class if a change is in progress */
-+	unsigned short new_ioprio, new_ioprio_class;
-+
-+	/*
-+	 * Shared bfq_queue if queue is cooperating with one or more
-+	 * other queues.
-+	 */
-+	struct bfq_queue *new_bfqq;
-+	/* request-position tree member (see bfq_group's @rq_pos_tree) */
-+	struct rb_node pos_node;
-+	/* request-position tree root (see bfq_group's @rq_pos_tree) */
-+	struct rb_root *pos_root;
-+
-+	/* sorted list of pending requests */
-+	struct rb_root sort_list;
-+	/* if fifo isn't expired, next request to serve */
-+	struct request *next_rq;
-+	/* number of sync and async requests queued */
-+	int queued[2];
-+	/* number of sync and async requests currently allocated */
-+	int allocated[2];
-+	/* number of pending metadata requests */
-+	int meta_pending;
-+	/* fifo list of requests in sort_list */
-+	struct list_head fifo;
-+
-+	/* entity representing this queue in the scheduler */
-+	struct bfq_entity entity;
-+
-+	/* maximum budget allowed from the feedback mechanism */
-+	int max_budget;
-+	/* budget expiration (in jiffies) */
-+	unsigned long budget_timeout;
-+
-+	/* number of requests on the dispatch list or inside driver */
-+	int dispatched;
-+
-+	unsigned int flags; /* status flags.*/
-+
-+	/* node for active/idle bfqq list inside parent bfqd */
-+	struct list_head bfqq_list;
-+
-+	/* bit vector: a 1 for each seeky requests in history */
-+	u32 seek_history;
-+
-+	/* node for the device's burst list */
-+	struct hlist_node burst_list_node;
-+
-+	/* position of the last request enqueued */
-+	sector_t last_request_pos;
-+
-+	/* Number of consecutive pairs of request completion and
-+	 * arrival, such that the queue becomes idle after the
-+	 * completion, but the next request arrives within an idle
-+	 * time slice; used only if the queue's IO_bound flag has been
-+	 * cleared.
-+	 */
-+	unsigned int requests_within_timer;
-+
-+	/* pid of the process owning the queue, used for logging purposes */
-+	pid_t pid;
-+
-+	/*
-+	 * Pointer to the bfq_io_cq owning the bfq_queue, set to %NULL
-+	 * if the queue is shared.
-+	 */
-+	struct bfq_io_cq *bic;
-+
-+	/* current maximum weight-raising time for this queue */
-+	unsigned long wr_cur_max_time;
-+	/*
-+	 * Minimum time instant such that, only if a new request is
-+	 * enqueued after this time instant in an idle @bfq_queue with
-+	 * no outstanding requests, then the task associated with the
-+	 * queue it is deemed as soft real-time (see the comments on
-+	 * the function bfq_bfqq_softrt_next_start())
-+	 */
-+	unsigned long soft_rt_next_start;
-+	/*
-+	 * Start time of the current weight-raising period if
-+	 * the @bfq-queue is being weight-raised, otherwise
-+	 * finish time of the last weight-raising period.
-+	 */
-+	unsigned long last_wr_start_finish;
-+	/* factor by which the weight of this queue is multiplied */
-+	unsigned int wr_coeff;
-+	/*
-+	 * Time of the last transition of the @bfq_queue from idle to
-+	 * backlogged.
-+	 */
-+	unsigned long last_idle_bklogged;
-+	/*
-+	 * Cumulative service received from the @bfq_queue since the
-+	 * last transition from idle to backlogged.
-+	 */
-+	unsigned long service_from_backlogged;
-+	/*
-+	 * Cumulative service received from the @bfq_queue since its
-+	 * last transition to weight-raised state.
-+	 */
-+	unsigned long service_from_wr;
-+	/*
-+	 * Value of wr start time when switching to soft rt
-+	 */
-+	unsigned long wr_start_at_switch_to_srt;
-+
-+	unsigned long split_time; /* time of last split */
-+
-+	unsigned long first_IO_time; /* time of first I/O for this queue */
-+};
-+
-+/**
-+ * struct bfq_ttime - per process thinktime stats.
-+ */
-+struct bfq_ttime {
-+	u64 last_end_request; /* completion time of last request */
-+
-+	u64 ttime_total; /* total process thinktime */
-+	unsigned long ttime_samples; /* number of thinktime samples */
-+	u64 ttime_mean; /* average process thinktime */
-+
-+};
-+
-+/**
-+ * struct bfq_io_cq - per (request_queue, io_context) structure.
-+ */
-+struct bfq_io_cq {
-+	/* associated io_cq structure */
-+	struct io_cq icq; /* must be the first member */
-+	/* array of two process queues, the sync and the async */
-+	struct bfq_queue *bfqq[2];
-+	/* associated @bfq_ttime struct */
-+	struct bfq_ttime ttime;
-+	/* per (request_queue, blkcg) ioprio */
-+	int ioprio;
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	uint64_t blkcg_serial_nr; /* the current blkcg serial */
-+#endif
-+
-+	/*
-+	 * Snapshot of the has_short_time flag before merging; taken
-+	 * to remember its value while the queue is merged, so as to
-+	 * be able to restore it in case of split.
-+	 */
-+	bool saved_has_short_ttime;
-+	/*
-+	 * Same purpose as the previous two fields for the I/O bound
-+	 * classification of a queue.
-+	 */
-+	bool saved_IO_bound;
-+
-+	/*
-+	 * Same purpose as the previous fields for the value of the
-+	 * field keeping the queue's belonging to a large burst
-+	 */
-+	bool saved_in_large_burst;
-+	/*
-+	 * True if the queue belonged to a burst list before its merge
-+	 * with another cooperating queue.
-+	 */
-+	bool was_in_burst_list;
-+
-+	/*
-+	 * Similar to previous fields: save wr information.
-+	 */
-+	unsigned long saved_wr_coeff;
-+	unsigned long saved_last_wr_start_finish;
-+	unsigned long saved_wr_start_at_switch_to_srt;
-+	unsigned int saved_wr_cur_max_time;
-+};
-+
-+/**
-+ * struct bfq_data - per-device data structure.
-+ *
-+ * All the fields are protected by the @queue lock.
-+ */
-+struct bfq_data {
-+	/* request queue for the device */
-+	struct request_queue *queue;
-+
-+	/* root bfq_group for the device */
-+	struct bfq_group *root_group;
-+
-+	/*
-+	 * rbtree of weight counters of @bfq_queues, sorted by
-+	 * weight. Used to keep track of whether all @bfq_queues have
-+	 * the same weight. The tree contains one counter for each
-+	 * distinct weight associated to some active and not
-+	 * weight-raised @bfq_queue (see the comments to the functions
-+	 * bfq_weights_tree_[add|remove] for further details).
-+	 */
-+	struct rb_root queue_weights_tree;
-+	/*
-+	 * rbtree of non-queue @bfq_entity weight counters, sorted by
-+	 * weight. Used to keep track of whether all @bfq_groups have
-+	 * the same weight. The tree contains one counter for each
-+	 * distinct weight associated to some active @bfq_group (see
-+	 * the comments to the functions bfq_weights_tree_[add|remove]
-+	 * for further details).
-+	 */
-+	struct rb_root group_weights_tree;
-+
-+	/*
-+	 * Number of bfq_queues containing requests (including the
-+	 * queue in service, even if it is idling).
-+	 */
-+	int busy_queues;
-+	/* number of weight-raised busy @bfq_queues */
-+	int wr_busy_queues;
-+	/* number of queued requests */
-+	int queued;
-+	/* number of requests dispatched and waiting for completion */
-+	int rq_in_driver;
-+
-+	/*
-+	 * Maximum number of requests in driver in the last
-+	 * @hw_tag_samples completed requests.
-+	 */
-+	int max_rq_in_driver;
-+	/* number of samples used to calculate hw_tag */
-+	int hw_tag_samples;
-+	/* flag set to one if the driver is showing a queueing behavior */
-+	int hw_tag;
-+
-+	/* number of budgets assigned */
-+	int budgets_assigned;
-+
-+	/*
-+	 * Timer set when idling (waiting) for the next request from
-+	 * the queue in service.
-+	 */
-+	struct hrtimer idle_slice_timer;
-+	/* delayed work to restart dispatching on the request queue */
-+	struct work_struct unplug_work;
-+
-+	/* bfq_queue in service */
-+	struct bfq_queue *in_service_queue;
-+	/* bfq_io_cq (bic) associated with the @in_service_queue */
-+	struct bfq_io_cq *in_service_bic;
-+
-+	/* on-disk position of the last served request */
-+	sector_t last_position;
-+
-+	/* time of last request completion (ns) */
-+	u64 last_completion;
-+
-+	/* time of first rq dispatch in current observation interval (ns) */
-+	u64 first_dispatch;
-+	/* time of last rq dispatch in current observation interval (ns) */
-+	u64 last_dispatch;
-+
-+	/* beginning of the last budget */
-+	ktime_t last_budget_start;
-+	/* beginning of the last idle slice */
-+	ktime_t last_idling_start;
-+
-+	/* number of samples in current observation interval */
-+	int peak_rate_samples;
-+	/* num of samples of seq dispatches in current observation interval */
-+	u32 sequential_samples;
-+	/* total num of sectors transferred in current observation interval */
-+	u64 tot_sectors_dispatched;
-+	/* max rq size seen during current observation interval (sectors) */
-+	u32 last_rq_max_size;
-+	/* time elapsed from first dispatch in current observ. interval (us) */
-+	u64 delta_from_first;
-+	/*
-+	 * Current estimate of the device peak rate, measured in
-+	 * [(sectors/usec) / 2^BFQ_RATE_SHIFT]. The left-shift by
-+	 * BFQ_RATE_SHIFT is performed to increase precision in
-+	 * fixed-point calculations.
-+	 */
-+	u32 peak_rate;
-+
-+	/* maximum budget allotted to a bfq_queue before rescheduling */
-+	int bfq_max_budget;
-+
-+	/* list of all the bfq_queues active on the device */
-+	struct list_head active_list;
-+	/* list of all the bfq_queues idle on the device */
-+	struct list_head idle_list;
-+
-+	/*
-+	 * Timeout for async/sync requests; when it fires, requests
-+	 * are served in fifo order.
-+	 */
-+	u64 bfq_fifo_expire[2];
-+	/* weight of backward seeks wrt forward ones */
-+	unsigned int bfq_back_penalty;
-+	/* maximum allowed backward seek */
-+	unsigned int bfq_back_max;
-+	/* maximum idling time */
-+	u32 bfq_slice_idle;
-+
-+	/* user-configured max budget value (0 for auto-tuning) */
-+	int bfq_user_max_budget;
-+	/*
-+	 * Timeout for bfq_queues to consume their budget; used to
-+	 * prevent seeky queues from imposing long latencies to
-+	 * sequential or quasi-sequential ones (this also implies that
-+	 * seeky queues cannot receive guarantees in the service
-+	 * domain; after a timeout they are charged for the time they
-+	 * have been in service, to preserve fairness among them, but
-+	 * without service-domain guarantees).
-+	 */
-+	unsigned int bfq_timeout;
-+
-+	/*
-+	 * Number of consecutive requests that must be issued within
-+	 * the idle time slice to set again idling to a queue which
-+	 * was marked as non-I/O-bound (see the definition of the
-+	 * IO_bound flag for further details).
-+	 */
-+	unsigned int bfq_requests_within_timer;
-+
-+	/*
-+	 * Force device idling whenever needed to provide accurate
-+	 * service guarantees, without caring about throughput
-+	 * issues. CAVEAT: this may even increase latencies, in case
-+	 * of useless idling for processes that did stop doing I/O.
-+	 */
-+	bool strict_guarantees;
-+
-+	/*
-+	 * Last time at which a queue entered the current burst of
-+	 * queues being activated shortly after each other; for more
-+	 * details about this and the following parameters related to
-+	 * a burst of activations, see the comments on the function
-+	 * bfq_handle_burst.
-+	 */
-+	unsigned long last_ins_in_burst;
-+	/*
-+	 * Reference time interval used to decide whether a queue has
-+	 * been activated shortly after @last_ins_in_burst.
-+	 */
-+	unsigned long bfq_burst_interval;
-+	/* number of queues in the current burst of queue activations */
-+	int burst_size;
-+
-+	/* common parent entity for the queues in the burst */
-+	struct bfq_entity *burst_parent_entity;
-+	/* Maximum burst size above which the current queue-activation
-+	 * burst is deemed as 'large'.
-+	 */
-+	unsigned long bfq_large_burst_thresh;
-+	/* true if a large queue-activation burst is in progress */
-+	bool large_burst;
-+	/*
-+	 * Head of the burst list (as for the above fields, more
-+	 * details in the comments on the function bfq_handle_burst).
-+	 */
-+	struct hlist_head burst_list;
-+
-+	/* if set to true, low-latency heuristics are enabled */
-+	bool low_latency;
-+	/*
-+	 * Maximum factor by which the weight of a weight-raised queue
-+	 * is multiplied.
-+	 */
-+	unsigned int bfq_wr_coeff;
-+	/* maximum duration of a weight-raising period (jiffies) */
-+	unsigned int bfq_wr_max_time;
-+
-+	/* Maximum weight-raising duration for soft real-time processes */
-+	unsigned int bfq_wr_rt_max_time;
-+	/*
-+	 * Minimum idle period after which weight-raising may be
-+	 * reactivated for a queue (in jiffies).
-+	 */
-+	unsigned int bfq_wr_min_idle_time;
-+	/*
-+	 * Minimum period between request arrivals after which
-+	 * weight-raising may be reactivated for an already busy async
-+	 * queue (in jiffies).
-+	 */
-+	unsigned long bfq_wr_min_inter_arr_async;
-+
-+	/* Max service-rate for a soft real-time queue, in sectors/sec */
-+	unsigned int bfq_wr_max_softrt_rate;
-+	/*
-+	 * Cached value of the product ref_rate*ref_wr_duration, used
-+	 * for computing the maximum duration of weight raising
-+	 * automatically.
-+	 */
-+	u64 rate_dur_prod;
-+
-+	/* fallback dummy bfqq for extreme OOM conditions */
-+	struct bfq_queue oom_bfqq;
-+};
-+
-+enum bfqq_state_flags {
-+	BFQ_BFQQ_FLAG_just_created = 0,	/* queue just allocated */
-+	BFQ_BFQQ_FLAG_busy,		/* has requests or is in service */
-+	BFQ_BFQQ_FLAG_wait_request,	/* waiting for a request */
-+	BFQ_BFQQ_FLAG_non_blocking_wait_rq, /*
-+					     * waiting for a request
-+					     * without idling the device
-+					     */
-+	BFQ_BFQQ_FLAG_must_alloc,	/* must be allowed rq alloc */
-+	BFQ_BFQQ_FLAG_fifo_expire,	/* FIFO checked in this slice */
-+	BFQ_BFQQ_FLAG_has_short_ttime,	/* queue has a short think time */
-+	BFQ_BFQQ_FLAG_sync,		/* synchronous queue */
-+	BFQ_BFQQ_FLAG_IO_bound,		/*
-+					 * bfqq has timed-out at least once
-+					 * having consumed at most 2/10 of
-+					 * its budget
-+					 */
-+	BFQ_BFQQ_FLAG_in_large_burst,	/*
-+					 * bfqq activated in a large burst,
-+					 * see comments to bfq_handle_burst.
-+					 */
-+	BFQ_BFQQ_FLAG_softrt_update,	/*
-+					 * may need softrt-next-start
-+					 * update
-+					 */
-+	BFQ_BFQQ_FLAG_coop,		/* bfqq is shared */
-+	BFQ_BFQQ_FLAG_split_coop	/* shared bfqq will be split */
-+};
-+
-+#define BFQ_BFQQ_FNS(name)						\
-+static void bfq_mark_bfqq_##name(struct bfq_queue *bfqq)		\
-+{									\
-+	(bfqq)->flags |= (1 << BFQ_BFQQ_FLAG_##name);			\
-+}									\
-+static void bfq_clear_bfqq_##name(struct bfq_queue *bfqq)		\
-+{									\
-+	(bfqq)->flags &= ~(1 << BFQ_BFQQ_FLAG_##name);			\
-+}									\
-+static int bfq_bfqq_##name(const struct bfq_queue *bfqq)		\
-+{									\
-+	return ((bfqq)->flags & (1 << BFQ_BFQQ_FLAG_##name)) != 0;	\
-+}
-+
-+BFQ_BFQQ_FNS(just_created);
-+BFQ_BFQQ_FNS(busy);
-+BFQ_BFQQ_FNS(wait_request);
-+BFQ_BFQQ_FNS(non_blocking_wait_rq);
-+BFQ_BFQQ_FNS(must_alloc);
-+BFQ_BFQQ_FNS(fifo_expire);
-+BFQ_BFQQ_FNS(has_short_ttime);
-+BFQ_BFQQ_FNS(sync);
-+BFQ_BFQQ_FNS(IO_bound);
-+BFQ_BFQQ_FNS(in_large_burst);
-+BFQ_BFQQ_FNS(coop);
-+BFQ_BFQQ_FNS(split_coop);
-+BFQ_BFQQ_FNS(softrt_update);
-+#undef BFQ_BFQQ_FNS
-+
-+/* Logging facilities. */
-+#ifdef CONFIG_BFQ_REDIRECT_TO_CONSOLE
-+
-+static const char *checked_dev_name(const struct device *dev)
-+{
-+	static const char nodev[] = "nodev";
-+
-+	if (dev)
-+		return dev_name(dev);
-+
-+	return nodev;
-+}
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+static struct bfq_group *bfqq_group(struct bfq_queue *bfqq);
-+static struct blkcg_gq *bfqg_to_blkg(struct bfq_group *bfqg);
-+
-+#define bfq_log_bfqq(bfqd, bfqq, fmt, args...)	do {			\
-+	char __pbuf[128];						\
-+									\
-+	assert_spin_locked((bfqd)->queue->queue_lock);			\
-+	blkg_path(bfqg_to_blkg(bfqq_group(bfqq)), __pbuf, sizeof(__pbuf)); \
-+	pr_crit("%s bfq%d%c %s [%s] " fmt "\n",				\
-+		checked_dev_name((bfqd)->queue->backing_dev_info->dev),	\
-+		(bfqq)->pid,						\
-+		bfq_bfqq_sync((bfqq)) ? 'S' : 'A',			\
-+		__pbuf, __func__, ##args);				\
-+} while (0)
-+
-+#define bfq_log_bfqg(bfqd, bfqg, fmt, args...)	do {			\
-+	char __pbuf[128];						\
-+									\
-+	blkg_path(bfqg_to_blkg(bfqg), __pbuf, sizeof(__pbuf));		\
-+	pr_crit("%s %s [%s] " fmt "\n",					\
-+	checked_dev_name((bfqd)->queue->backing_dev_info->dev),		\
-+	__pbuf, __func__, ##args);					\
-+} while (0)
-+
-+#else /* BFQ_GROUP_IOSCHED_ENABLED */
-+
-+#define bfq_log_bfqq(bfqd, bfqq, fmt, args...)				\
-+	pr_crit("%s bfq%d%c [%s] " fmt "\n",				\
-+		checked_dev_name((bfqd)->queue->backing_dev_info->dev),	\
-+		(bfqq)->pid, bfq_bfqq_sync((bfqq)) ? 'S' : 'A',		\
-+		__func__, ##args)
-+#define bfq_log_bfqg(bfqd, bfqg, fmt, args...)		do {} while (0)
-+
-+#endif /* BFQ_GROUP_IOSCHED_ENABLED */
-+
-+#define bfq_log(bfqd, fmt, args...) \
-+	pr_crit("%s bfq [%s] " fmt "\n",				\
-+		checked_dev_name((bfqd)->queue->backing_dev_info->dev),	\
-+		__func__, ##args)
-+
-+#else /* CONFIG_BFQ_REDIRECT_TO_CONSOLE */
-+
-+#if !defined(CONFIG_BLK_DEV_IO_TRACE)
-+
-+/* Avoid possible "unused-variable" warning. See commit message. */
-+
-+#define bfq_log_bfqq(bfqd, bfqq, fmt, args...)	((void) (bfqq))
-+
-+#define bfq_log_bfqg(bfqd, bfqg, fmt, args...)	((void) (bfqg))
-+
-+#define bfq_log(bfqd, fmt, args...)		do {} while (0)
-+
-+#else /* CONFIG_BLK_DEV_IO_TRACE */
-+
-+#include <linux/blktrace_api.h>
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+static struct bfq_group *bfqq_group(struct bfq_queue *bfqq);
-+static struct blkcg_gq *bfqg_to_blkg(struct bfq_group *bfqg);
-+
-+#define bfq_log_bfqq(bfqd, bfqq, fmt, args...)	do {			\
-+	char __pbuf[128];						\
-+									\
-+	assert_spin_locked((bfqd)->queue->queue_lock);			\
-+	blkg_path(bfqg_to_blkg(bfqq_group(bfqq)), __pbuf, sizeof(__pbuf)); \
-+	blk_add_trace_msg((bfqd)->queue, "bfq%d%c %s [%s] " fmt, \
-+			  (bfqq)->pid,			  \
-+			  bfq_bfqq_sync((bfqq)) ? 'S' : 'A',	\
-+			  __pbuf, __func__, ##args);			\
-+} while (0)
-+
-+#define bfq_log_bfqg(bfqd, bfqg, fmt, args...)	do {			\
-+	char __pbuf[128];						\
-+									\
-+	blkg_path(bfqg_to_blkg(bfqg), __pbuf, sizeof(__pbuf));		\
-+	blk_add_trace_msg((bfqd)->queue, "%s [%s] " fmt, __pbuf, \
-+	__func__, ##args);	\
-+} while (0)
-+
-+#else /* BFQ_GROUP_IOSCHED_ENABLED */
-+
-+#define bfq_log_bfqq(bfqd, bfqq, fmt, args...)	\
-+	blk_add_trace_msg((bfqd)->queue, "bfq%d%c [%s] " fmt, (bfqq)->pid, \
-+			bfq_bfqq_sync((bfqq)) ? 'S' : 'A',		\
-+				__func__, ##args)
-+#define bfq_log_bfqg(bfqd, bfqg, fmt, args...)		do {} while (0)
-+
-+#endif /* BFQ_GROUP_IOSCHED_ENABLED */
-+
-+#define bfq_log(bfqd, fmt, args...) \
-+	blk_add_trace_msg((bfqd)->queue, "bfq [%s] " fmt, __func__, ##args)
-+
-+#endif /* CONFIG_BLK_DEV_IO_TRACE */
-+#endif /* CONFIG_BFQ_REDIRECT_TO_CONSOLE */
-+
-+/* Expiration reasons. */
-+enum bfqq_expiration {
-+	BFQ_BFQQ_TOO_IDLE = 0,		/*
-+					 * queue has been idling for
-+					 * too long
-+					 */
-+	BFQ_BFQQ_BUDGET_TIMEOUT,	/* budget took too long to be used */
-+	BFQ_BFQQ_BUDGET_EXHAUSTED,	/* budget consumed */
-+	BFQ_BFQQ_NO_MORE_REQUESTS,	/* the queue has no more requests */
-+	BFQ_BFQQ_PREEMPTED		/* preemption in progress */
-+};
-+
-+
-+struct bfqg_stats {
-+#if defined(BFQ_GROUP_IOSCHED_ENABLED) &&  defined(CONFIG_DEBUG_BLK_CGROUP)
-+	/* number of ios merged */
-+	struct blkg_rwstat		merged;
-+	/* total time spent on device in ns, may not be accurate w/ queueing */
-+	struct blkg_rwstat		service_time;
-+	/* total time spent waiting in scheduler queue in ns */
-+	struct blkg_rwstat		wait_time;
-+	/* number of IOs queued up */
-+	struct blkg_rwstat		queued;
-+	/* total disk time and nr sectors dispatched by this group */
-+	struct blkg_stat		time;
-+	/* sum of number of ios queued across all samples */
-+	struct blkg_stat		avg_queue_size_sum;
-+	/* count of samples taken for average */
-+	struct blkg_stat		avg_queue_size_samples;
-+	/* how many times this group has been removed from service tree */
-+	struct blkg_stat		dequeue;
-+	/* total time spent waiting for it to be assigned a timeslice. */
-+	struct blkg_stat		group_wait_time;
-+	/* time spent idling for this blkcg_gq */
-+	struct blkg_stat		idle_time;
-+	/* total time with empty current active q with other requests queued */
-+	struct blkg_stat		empty_time;
-+	/* fields after this shouldn't be cleared on stat reset */
-+	uint64_t			start_group_wait_time;
-+	uint64_t			start_idle_time;
-+	uint64_t			start_empty_time;
-+	uint16_t			flags;
-+#endif /* BFQ_GROUP_IOSCHED_ENABLED && CONFIG_DEBUG_BLK_CGROUP */
-+};
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+/*
-+ * struct bfq_group_data - per-blkcg storage for the blkio subsystem.
-+ *
-+ * @ps: @blkcg_policy_storage that this structure inherits
-+ * @weight: weight of the bfq_group
-+ */
-+struct bfq_group_data {
-+	/* must be the first member */
-+	struct blkcg_policy_data pd;
-+
-+	unsigned int weight;
-+};
-+
-+/**
-+ * struct bfq_group - per (device, cgroup) data structure.
-+ * @entity: schedulable entity to insert into the parent group sched_data.
-+ * @sched_data: own sched_data, to contain child entities (they may be
-+ *              both bfq_queues and bfq_groups).
-+ * @bfqd: the bfq_data for the device this group acts upon.
-+ * @async_bfqq: array of async queues for all the tasks belonging to
-+ *              the group, one queue per ioprio value per ioprio_class,
-+ *              except for the idle class that has only one queue.
-+ * @async_idle_bfqq: async queue for the idle class (ioprio is ignored).
-+ * @my_entity: pointer to @entity, %NULL for the toplevel group; used
-+ *             to avoid too many special cases during group creation/
-+ *             migration.
-+ * @active_entities: number of active entities belonging to the group;
-+ *                   unused for the root group. Used to know whether there
-+ *                   are groups with more than one active @bfq_entity
-+ *                   (see the comments to the function
-+ *                   bfq_bfqq_may_idle()).
-+ * @rq_pos_tree: rbtree sorted by next_request position, used when
-+ *               determining if two or more queues have interleaving
-+ *               requests (see bfq_find_close_cooperator()).
-+ *
-+ * Each (device, cgroup) pair has its own bfq_group, i.e., for each cgroup
-+ * there is a set of bfq_groups, each one collecting the lower-level
-+ * entities belonging to the group that are acting on the same device.
-+ *
-+ * Locking works as follows:
-+ *    o @bfqd is protected by the queue lock, RCU is used to access it
-+ *      from the readers.
-+ *    o All the other fields are protected by the @bfqd queue lock.
-+ */
-+struct bfq_group {
-+	/* must be the first member */
-+	struct blkg_policy_data pd;
-+
-+	struct bfq_entity entity;
-+	struct bfq_sched_data sched_data;
-+
-+	void *bfqd;
-+
-+	struct bfq_queue *async_bfqq[2][IOPRIO_BE_NR];
-+	struct bfq_queue *async_idle_bfqq;
-+
-+	struct bfq_entity *my_entity;
-+
-+	int active_entities;
-+
-+	struct rb_root rq_pos_tree;
-+
-+	struct bfqg_stats stats;
-+};
-+
-+#else
-+struct bfq_group {
-+	struct bfq_sched_data sched_data;
-+
-+	struct bfq_queue *async_bfqq[2][IOPRIO_BE_NR];
-+	struct bfq_queue *async_idle_bfqq;
-+
-+	struct rb_root rq_pos_tree;
-+};
-+#endif
-+
-+static struct bfq_queue *bfq_entity_to_bfqq(struct bfq_entity *entity);
-+
-+static unsigned int bfq_class_idx(struct bfq_entity *entity)
-+{
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+
-+	return bfqq ? bfqq->ioprio_class - 1 :
-+		BFQ_DEFAULT_GRP_CLASS - 1;
-+}
-+
-+static struct bfq_service_tree *
-+bfq_entity_service_tree(struct bfq_entity *entity)
-+{
-+	struct bfq_sched_data *sched_data = entity->sched_data;
-+	struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
-+	unsigned int idx = bfq_class_idx(entity);
-+
-+	BUG_ON(idx >= BFQ_IOPRIO_CLASSES);
-+	BUG_ON(sched_data == NULL);
-+
-+	if (bfqq)
-+		bfq_log_bfqq(bfqq->bfqd, bfqq,
-+			     "%p %d",
-+			     sched_data->service_tree + idx, idx);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+	else {
-+		struct bfq_group *bfqg =
-+			container_of(entity, struct bfq_group, entity);
-+
-+		bfq_log_bfqg((struct bfq_data *)bfqg->bfqd, bfqg,
-+			     "%p %d",
-+			     sched_data->service_tree + idx, idx);
-+	}
-+#endif
-+	return sched_data->service_tree + idx;
-+}
-+
-+static struct bfq_queue *bic_to_bfqq(struct bfq_io_cq *bic, bool is_sync)
-+{
-+	return bic->bfqq[is_sync];
-+}
-+
-+static void bic_set_bfqq(struct bfq_io_cq *bic, struct bfq_queue *bfqq,
-+			 bool is_sync)
-+{
-+	bic->bfqq[is_sync] = bfqq;
-+}
-+
-+static struct bfq_data *bic_to_bfqd(struct bfq_io_cq *bic)
-+{
-+	return bic->icq.q->elevator->elevator_data;
-+}
-+
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+
-+static struct bfq_group *bfq_bfqq_to_bfqg(struct bfq_queue *bfqq)
-+{
-+	struct bfq_entity *group_entity = bfqq->entity.parent;
-+
-+	if (!group_entity)
-+		group_entity = &bfqq->bfqd->root_group->entity;
-+
-+	return container_of(group_entity, struct bfq_group, entity);
-+}
-+
-+#else
-+
-+static struct bfq_group *bfq_bfqq_to_bfqg(struct bfq_queue *bfqq)
-+{
-+	return bfqq->bfqd->root_group;
-+}
-+
-+#endif
-+
-+static void bfq_check_ioprio_change(struct bfq_io_cq *bic, struct bio *bio);
-+static void bfq_put_queue(struct bfq_queue *bfqq);
-+static void bfq_dispatch_insert(struct request_queue *q, struct request *rq);
-+static struct bfq_queue *bfq_get_queue(struct bfq_data *bfqd,
-+				       struct bio *bio, bool is_sync,
-+				       struct bfq_io_cq *bic);
-+static void bfq_end_wr_async_queues(struct bfq_data *bfqd,
-+				    struct bfq_group *bfqg);
-+#ifdef BFQ_GROUP_IOSCHED_ENABLED
-+static void bfq_put_async_queues(struct bfq_data *bfqd, struct bfq_group *bfqg);
-+#endif
-+static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq);
-+
-+#endif /* _BFQ_H */
-diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
-index 79226ca8f80f..897c63322bd7 100644
---- a/include/linux/blkdev.h
-+++ b/include/linux/blkdev.h
-@@ -129,6 +129,10 @@ typedef __u32 __bitwise req_flags_t;
- #define RQF_MQ_POLL_SLEPT	((__force req_flags_t)(1 << 20))
- /* ->timeout has been called, don't expire again */
- #define RQF_TIMED_OUT		((__force req_flags_t)(1 << 21))
-+/* DEBUG: rq in bfq-mq dispatch list */
-+#define RQF_DISP_LIST	((__force req_flags_t)(1 << 22))
-+/* DEBUG: rq had get_rq_private executed on it */
-+#define RQF_GOT	((__force req_flags_t)(1 << 23))
- 
- /* flags that prevent us from merging requests: */
- #define RQF_NOMERGE_FLAGS \
diff --git a/disabled/MuQSS-export-can_nice-for-binder.patch b/disabled/MuQSS-export-can_nice-for-binder.patch
deleted file mode 100644
index fab607c..0000000
--- a/disabled/MuQSS-export-can_nice-for-binder.patch
+++ /dev/null
@@ -1,11 +0,0 @@
-diff -up linux-5.2/kernel/sched/MuQSS.c.omv~ linux-5.2/kernel/sched/MuQSS.c
---- linux-5.2/kernel/sched/MuQSS.c.omv~	2019-07-31 14:33:11.842604878 +0200
-+++ linux-5.2/kernel/sched/MuQSS.c	2019-07-31 14:33:23.726553288 +0200
-@@ -4465,6 +4465,7 @@ int can_nice(const struct task_struct *p
- 	return (nice_rlim <= task_rlimit(p, RLIMIT_NICE) ||
- 		capable(CAP_SYS_NICE));
- }
-+EXPORT_SYMBOL_GPL(can_nice);
- 
- #ifdef __ARCH_WANT_SYS_NICE
- 
diff --git a/disabled/RFC-v3-01-13-bootsplash-Initial-implementation-showing-black-screen.patch b/disabled/RFC-v3-01-13-bootsplash-Initial-implementation-showing-black-screen.patch
deleted file mode 100644
index 3e6cbd4..0000000
--- a/disabled/RFC-v3-01-13-bootsplash-Initial-implementation-showing-black-screen.patch
+++ /dev/null
@@ -1,731 +0,0 @@
-diff -up linux-4.18/drivers/video/console/Kconfig.0100~ linux-4.18/drivers/video/console/Kconfig
---- linux-4.18/drivers/video/console/Kconfig.0100~	2018-08-27 10:28:08.073909394 +0200
-+++ linux-4.18/drivers/video/console/Kconfig	2018-08-27 10:29:04.500028244 +0200
-@@ -161,6 +161,30 @@ config FRAMEBUFFER_CONSOLE_DEFERRED_TAKE
- 	  by the firmware in place, rather then replacing the contents with a
- 	  black screen as soon as fbcon loads.
- 
-+config BOOTSPLASH
-+	bool "Bootup splash screen"
-+	depends on FRAMEBUFFER_CONSOLE
-+	---help---
-+	  This option enables the Linux bootsplash screen.
-+
-+	  The bootsplash is a full-screen logo or animation indicating a
-+	  booting system. It replaces the classic scrolling text with a
-+	  graphical alternative, similar to other systems.
-+
-+	  Since this is technically implemented as a hook on top of fbcon,
-+	  it can only work if the FRAMEBUFFER_CONSOLE is enabled and a
-+	  framebuffer driver is active. Thus, to get a text-free boot,
-+	  the system needs to boot with vesafb, efifb, or similar.
-+
-+	  Once built into the kernel, the bootsplash needs to be enabled
-+	  with bootsplash.enabled=1 and a splash file needs to be supplied.
-+
-+	  Further documentation can be found in:
-+	    Documentation/fb/bootsplash.txt
-+
-+	  If unsure, say N.
-+	  This is typically used by distributors and system integrators.
-+
- config STI_CONSOLE
-         bool "STI text console"
- 	depends on PARISC && HAS_IOMEM
-diff -up linux-4.18/drivers/video/fbdev/core/bootsplash.c.0100~ linux-4.18/drivers/video/fbdev/core/bootsplash.c
---- linux-4.18/drivers/video/fbdev/core/bootsplash.c.0100~	2018-08-27 10:28:08.073909394 +0200
-+++ linux-4.18/drivers/video/fbdev/core/bootsplash.c	2018-08-27 10:28:08.073909394 +0200
-@@ -0,0 +1,294 @@
-+/*
-+ * Kernel based bootsplash.
-+ *
-+ * (Main file: Glue code, workers, timer, PM, kernel and userland API)
-+ *
-+ * Authors:
-+ * Max Staudt <mstaudt@suse.de>
-+ *
-+ * SPDX-License-Identifier: GPL-2.0
-+ */
-+
-+#define pr_fmt(fmt) "bootsplash: " fmt
-+
-+
-+#include <linux/atomic.h>
-+#include <linux/bootsplash.h>
-+#include <linux/console.h>
-+#include <linux/device.h> /* dev_warn() */
-+#include <linux/fb.h>
-+#include <linux/fs.h>
-+#include <linux/kernel.h>
-+#include <linux/jiffies.h>
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+#include <linux/platform_device.h>
-+#include <linux/printk.h>
-+#include <linux/selection.h> /* console_blanked */
-+#include <linux/stringify.h>
-+#include <linux/types.h>
-+#include <linux/vmalloc.h>
-+#include <linux/vt_kern.h>
-+#include <linux/workqueue.h>
-+
-+#include "bootsplash_internal.h"
-+
-+
-+/*
-+ * We only have one splash screen, so let's keep a single
-+ * instance of the internal state.
-+ */
-+static struct splash_priv splash_state;
-+
-+
-+static void splash_callback_redraw_vc(struct work_struct *ignored)
-+{
-+	if (console_blanked)
-+		return;
-+
-+	console_lock();
-+	if (vc_cons[fg_console].d)
-+		update_screen(vc_cons[fg_console].d);
-+	console_unlock();
-+}
-+
-+
-+static bool is_fb_compatible(const struct fb_info *info)
-+{
-+	if (!(info->flags & FBINFO_BE_MATH)
-+	    != !fb_be_math((struct fb_info *)info)) {
-+		dev_warn(info->device,
-+			 "Can't draw on foreign endianness framebuffer.\n");
-+
-+		return false;
-+	}
-+
-+	if (info->flags & FBINFO_MISC_TILEBLITTING) {
-+		dev_warn(info->device,
-+			 "Can't draw splash on tiling framebuffer.\n");
-+
-+		return false;
-+	}
-+
-+	if (info->fix.type != FB_TYPE_PACKED_PIXELS
-+	    || (info->fix.visual != FB_VISUAL_TRUECOLOR
-+		&& info->fix.visual != FB_VISUAL_DIRECTCOLOR)) {
-+		dev_warn(info->device,
-+			 "Can't draw splash on non-packed or non-truecolor framebuffer.\n");
-+
-+		dev_warn(info->device,
-+			 "  type: %u   visual: %u\n",
-+			 info->fix.type, info->fix.visual);
-+
-+		return false;
-+	}
-+
-+	if (info->var.bits_per_pixel != 16
-+	    && info->var.bits_per_pixel != 24
-+	    && info->var.bits_per_pixel != 32) {
-+		dev_warn(info->device,
-+			 "We only support drawing on framebuffers with 16, 24, or 32 bpp, not %d.\n",
-+			 info->var.bits_per_pixel);
-+
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
-+
-+/*
-+ * Called by fbcon_switch() when an instance is activated or refreshed.
-+ */
-+void bootsplash_render_full(struct fb_info *info)
-+{
-+	if (!is_fb_compatible(info))
-+		return;
-+
-+	bootsplash_do_render_background(info);
-+}
-+
-+
-+/*
-+ * External status enquiry and on/off switch
-+ */
-+bool bootsplash_would_render_now(void)
-+{
-+	return !oops_in_progress
-+		&& !console_blanked
-+		&& bootsplash_is_enabled();
-+}
-+
-+bool bootsplash_is_enabled(void)
-+{
-+	bool was_enabled;
-+
-+	/* Make sure we have the newest state */
-+	smp_rmb();
-+
-+	was_enabled = test_bit(0, &splash_state.enabled);
-+
-+	return was_enabled;
-+}
-+
-+void bootsplash_disable(void)
-+{
-+	int was_enabled;
-+
-+	was_enabled = test_and_clear_bit(0, &splash_state.enabled);
-+
-+	if (was_enabled) {
-+		if (oops_in_progress) {
-+			/* Redraw screen now so we can see a panic */
-+			if (vc_cons[fg_console].d)
-+				update_screen(vc_cons[fg_console].d);
-+		} else {
-+			/* No urgency, redraw at next opportunity */
-+			schedule_work(&splash_state.work_redraw_vc);
-+		}
-+	}
-+}
-+
-+void bootsplash_enable(void)
-+{
-+	bool was_enabled;
-+
-+	if (oops_in_progress)
-+		return;
-+
-+	was_enabled = test_and_set_bit(0, &splash_state.enabled);
-+
-+	if (!was_enabled)
-+		schedule_work(&splash_state.work_redraw_vc);
-+}
-+
-+
-+/*
-+ * Userland API via platform device in sysfs
-+ */
-+static ssize_t splash_show_enabled(struct device *dev,
-+				   struct device_attribute *attr, char *buf)
-+{
-+	return sprintf(buf, "%d\n", bootsplash_is_enabled());
-+}
-+
-+static ssize_t splash_store_enabled(struct device *device,
-+				    struct device_attribute *attr,
-+				    const char *buf, size_t count)
-+{
-+	bool enable;
-+	int err;
-+
-+	if (!buf || !count)
-+		return -EFAULT;
-+
-+	err = kstrtobool(buf, &enable);
-+	if (err)
-+		return err;
-+
-+	if (enable)
-+		bootsplash_enable();
-+	else
-+		bootsplash_disable();
-+
-+	return count;
-+}
-+
-+static DEVICE_ATTR(enabled, 0644, splash_show_enabled, splash_store_enabled);
-+
-+
-+static struct attribute *splash_dev_attrs[] = {
-+	&dev_attr_enabled.attr,
-+	NULL
-+};
-+
-+ATTRIBUTE_GROUPS(splash_dev);
-+
-+
-+
-+
-+/*
-+ * Power management fixup via platform device
-+ *
-+ * When the system is woken from sleep or restored after hibernating, we
-+ * cannot expect the screen contents to still be present in video RAM.
-+ * Thus, we have to redraw the splash if we're currently active.
-+ */
-+static int splash_resume(struct device *device)
-+{
-+	if (bootsplash_would_render_now())
-+		schedule_work(&splash_state.work_redraw_vc);
-+
-+	return 0;
-+}
-+
-+static int splash_suspend(struct device *device)
-+{
-+	cancel_work_sync(&splash_state.work_redraw_vc);
-+
-+	return 0;
-+}
-+
-+
-+static const struct dev_pm_ops splash_pm_ops = {
-+	.thaw = splash_resume,
-+	.restore = splash_resume,
-+	.resume = splash_resume,
-+	.suspend = splash_suspend,
-+	.freeze = splash_suspend,
-+};
-+
-+static struct platform_driver splash_driver = {
-+	.driver = {
-+		.name = "bootsplash",
-+		.pm = &splash_pm_ops,
-+	},
-+};
-+
-+
-+/*
-+ * Main init
-+ */
-+void bootsplash_init(void)
-+{
-+	int ret;
-+
-+	/* Initialized already? */
-+	if (splash_state.splash_device)
-+		return;
-+
-+
-+	/* Register platform device to export user API */
-+	ret = platform_driver_register(&splash_driver);
-+	if (ret) {
-+		pr_err("platform_driver_register() failed: %d\n", ret);
-+		goto err;
-+	}
-+
-+	splash_state.splash_device
-+		= platform_device_alloc("bootsplash", 0);
-+
-+	if (!splash_state.splash_device)
-+		goto err_driver;
-+
-+	splash_state.splash_device->dev.groups = splash_dev_groups;
-+
-+	ret = platform_device_add(splash_state.splash_device);
-+	if (ret) {
-+		pr_err("platform_device_add() failed: %d\n", ret);
-+		goto err_device;
-+	}
-+
-+
-+	INIT_WORK(&splash_state.work_redraw_vc, splash_callback_redraw_vc);
-+
-+	return;
-+
-+err_device:
-+	platform_device_put(splash_state.splash_device);
-+	splash_state.splash_device = NULL;
-+err_driver:
-+	platform_driver_unregister(&splash_driver);
-+err:
-+	pr_err("Failed to initialize.\n");
-+}
-diff -up linux-4.18/drivers/video/fbdev/core/bootsplash_internal.h.0100~ linux-4.18/drivers/video/fbdev/core/bootsplash_internal.h
---- linux-4.18/drivers/video/fbdev/core/bootsplash_internal.h.0100~	2018-08-27 10:28:08.073909394 +0200
-+++ linux-4.18/drivers/video/fbdev/core/bootsplash_internal.h	2018-08-27 10:28:08.073909394 +0200
-@@ -0,0 +1,55 @@
-+/*
-+ * Kernel based bootsplash.
-+ *
-+ * (Internal data structures used at runtime)
-+ *
-+ * Authors:
-+ * Max Staudt <mstaudt@suse.de>
-+ *
-+ * SPDX-License-Identifier: GPL-2.0
-+ */
-+
-+#ifndef __BOOTSPLASH_INTERNAL_H
-+#define __BOOTSPLASH_INTERNAL_H
-+
-+
-+#include <linux/types.h>
-+#include <linux/fb.h>
-+#include <linux/kernel.h>
-+#include <linux/mutex.h>
-+#include <linux/spinlock.h>
-+
-+
-+/*
-+ * Runtime types
-+ */
-+struct splash_priv {
-+	/*
-+	 * Enabled/disabled state, to be used with atomic bit operations.
-+	 *   Bit 0: 0 = Splash hidden
-+	 *          1 = Splash shown
-+	 *
-+	 * Note: fbcon.c uses this twice, by calling
-+	 *       bootsplash_would_render_now() in set_blitting_type() and
-+	 *       in fbcon_switch().
-+	 *       This is racy, but eventually consistent: Turning the
-+	 *       splash on/off will cause a redraw, which calls
-+	 *       fbcon_switch(), which calls set_blitting_type().
-+	 *       So the last on/off toggle will make things consistent.
-+	 */
-+	unsigned long enabled;
-+
-+	/* Our gateway to userland via sysfs */
-+	struct platform_device *splash_device;
-+
-+	struct work_struct work_redraw_vc;
-+};
-+
-+
-+
-+/*
-+ * Rendering functions
-+ */
-+void bootsplash_do_render_background(struct fb_info *info);
-+
-+#endif
-diff -up linux-4.18/drivers/video/fbdev/core/bootsplash_render.c.0100~ linux-4.18/drivers/video/fbdev/core/bootsplash_render.c
---- linux-4.18/drivers/video/fbdev/core/bootsplash_render.c.0100~	2018-08-27 10:28:08.073909394 +0200
-+++ linux-4.18/drivers/video/fbdev/core/bootsplash_render.c	2018-08-27 10:28:08.073909394 +0200
-@@ -0,0 +1,93 @@
-+/*
-+ * Kernel based bootsplash.
-+ *
-+ * (Rendering functions)
-+ *
-+ * Authors:
-+ * Max Staudt <mstaudt@suse.de>
-+ *
-+ * SPDX-License-Identifier: GPL-2.0
-+ */
-+
-+#define pr_fmt(fmt) "bootsplash: " fmt
-+
-+
-+#include <linux/bootsplash.h>
-+#include <linux/fb.h>
-+#include <linux/kernel.h>
-+#include <linux/printk.h>
-+#include <linux/types.h>
-+
-+#include "bootsplash_internal.h"
-+
-+
-+
-+
-+/*
-+ * Rendering: Internal drawing routines
-+ */
-+
-+
-+/*
-+ * Pack pixel into target format and do Big/Little Endian handling.
-+ * This would be a good place to handle endianness conversion if necessary.
-+ */
-+static inline u32 pack_pixel(const struct fb_var_screeninfo *dst_var,
-+			     u8 red, u8 green, u8 blue)
-+{
-+	u32 dstpix;
-+
-+	/* Quantize pixel */
-+	red = red >> (8 - dst_var->red.length);
-+	green = green >> (8 - dst_var->green.length);
-+	blue = blue >> (8 - dst_var->blue.length);
-+
-+	/* Pack pixel */
-+	dstpix = red << (dst_var->red.offset)
-+		| green << (dst_var->green.offset)
-+		| blue << (dst_var->blue.offset);
-+
-+	/*
-+	 * Move packed pixel to the beginning of the memory cell,
-+	 * so we can memcpy() it out easily
-+	 */
-+#ifdef __BIG_ENDIAN
-+	switch (dst_var->bits_per_pixel) {
-+	case 16:
-+		dstpix <<= 16;
-+		break;
-+	case 24:
-+		dstpix <<= 8;
-+		break;
-+	case 32:
-+		break;
-+	}
-+#else
-+	/* This is intrinsically unnecessary on Little Endian */
-+#endif
-+
-+	return dstpix;
-+}
-+
-+
-+void bootsplash_do_render_background(struct fb_info *info)
-+{
-+	unsigned int x, y;
-+	u32 dstpix;
-+	u32 dst_octpp = info->var.bits_per_pixel / 8;
-+
-+	dstpix = pack_pixel(&info->var,
-+			    0,
-+			    0,
-+			    0);
-+
-+	for (y = 0; y < info->var.yres_virtual; y++) {
-+		u8 *dstline = info->screen_buffer + (y * info->fix.line_length);
-+
-+		for (x = 0; x < info->var.xres_virtual; x++) {
-+			memcpy(dstline, &dstpix, dst_octpp);
-+
-+			dstline += dst_octpp;
-+		}
-+	}
-+}
-diff -up linux-4.18/drivers/video/fbdev/core/dummyblit.c.0100~ linux-4.18/drivers/video/fbdev/core/dummyblit.c
---- linux-4.18/drivers/video/fbdev/core/dummyblit.c.0100~	2018-08-27 10:28:08.074909396 +0200
-+++ linux-4.18/drivers/video/fbdev/core/dummyblit.c	2018-08-27 10:28:08.074909396 +0200
-@@ -0,0 +1,89 @@
-+/*
-+ *  linux/drivers/video/fbdev/core/dummyblit.c -- Dummy Blitting Operation
-+ *
-+ *  Authors:
-+ *  Max Staudt <mstaudt@suse.de>
-+ *
-+ *  These functions are used in place of blitblit/tileblit to suppress
-+ *  fbcon's text output while a splash is shown.
-+ *
-+ *  Only suppressing actual rendering keeps the text buffer in the VC layer
-+ *  intact and makes it easy to switch back from the bootsplash to a full
-+ *  text console with a simple redraw (with the original functions in place).
-+ *
-+ *  Based on linux/drivers/video/fbdev/core/bitblit.c
-+ *       and linux/drivers/video/fbdev/core/tileblit.c
-+ *
-+ * SPDX-License-Identifier: GPL-2.0
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/fb.h>
-+#include <linux/vt_kern.h>
-+#include <linux/console.h>
-+#include <asm/types.h>
-+#include "fbcon.h"
-+
-+static void dummy_bmove(struct vc_data *vc, struct fb_info *info, int sy,
-+			int sx, int dy, int dx, int height, int width)
-+{
-+	;
-+}
-+
-+static void dummy_clear(struct vc_data *vc, struct fb_info *info, int sy,
-+			int sx, int height, int width)
-+{
-+	;
-+}
-+
-+static void dummy_putcs(struct vc_data *vc, struct fb_info *info,
-+			const unsigned short *s, int count, int yy, int xx,
-+			int fg, int bg)
-+{
-+	;
-+}
-+
-+static void dummy_clear_margins(struct vc_data *vc, struct fb_info *info,
-+				int color, int bottom_only)
-+{
-+	;
-+}
-+
-+static void dummy_cursor(struct vc_data *vc, struct fb_info *info, int mode,
-+			int softback_lines, int fg, int bg)
-+{
-+	;
-+}
-+
-+static int dummy_update_start(struct fb_info *info)
-+{
-+	/*
-+	 * Copied from bitblit.c and tileblit.c
-+	 *
-+	 * As of Linux 4.12, nobody seems to care about our return value.
-+	 */
-+	struct fbcon_ops *ops = info->fbcon_par;
-+	int err;
-+
-+	err = fb_pan_display(info, &ops->var);
-+	ops->var.xoffset = info->var.xoffset;
-+	ops->var.yoffset = info->var.yoffset;
-+	ops->var.vmode = info->var.vmode;
-+	return err;
-+}
-+
-+void fbcon_set_dummyops(struct fbcon_ops *ops)
-+{
-+	ops->bmove = dummy_bmove;
-+	ops->clear = dummy_clear;
-+	ops->putcs = dummy_putcs;
-+	ops->clear_margins = dummy_clear_margins;
-+	ops->cursor = dummy_cursor;
-+	ops->update_start = dummy_update_start;
-+	ops->rotate_font = NULL;
-+}
-+EXPORT_SYMBOL_GPL(fbcon_set_dummyops);
-+
-+MODULE_AUTHOR("Max Staudt <mstaudt@suse.de>");
-+MODULE_DESCRIPTION("Dummy Blitting Operation");
-+MODULE_LICENSE("GPL");
-diff -up linux-4.18/drivers/video/fbdev/core/fbcon.c.0100~ linux-4.18/drivers/video/fbdev/core/fbcon.c
---- linux-4.18/drivers/video/fbdev/core/fbcon.c.0100~	2018-08-27 10:28:08.025909293 +0200
-+++ linux-4.18/drivers/video/fbdev/core/fbcon.c	2018-08-27 10:28:08.074909396 +0200
-@@ -80,6 +80,7 @@
- #include <asm/irq.h>
- 
- #include "fbcon.h"
-+#include <linux/bootsplash.h>
- 
- #ifdef FBCONDEBUG
- #  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
-@@ -553,6 +554,8 @@ static int do_fbcon_takeover(int show_lo
- 	for (i = first_fb_vc; i <= last_fb_vc; i++)
- 		con2fb_map[i] = info_idx;
- 
-+	bootsplash_init();
-+
- 	err = do_take_over_console(&fb_con, first_fb_vc, last_fb_vc,
- 				fbcon_is_default);
- 
-@@ -673,6 +676,9 @@ static void set_blitting_type(struct vc_
- 	else {
- 		fbcon_set_rotation(info);
- 		fbcon_set_bitops(ops);
-+
-+		if (bootsplash_would_render_now())
-+			fbcon_set_dummyops(ops);
- 	}
- }
- 
-@@ -695,6 +701,19 @@ static void set_blitting_type(struct vc_
- 	ops->p = &fb_display[vc->vc_num];
- 	fbcon_set_rotation(info);
- 	fbcon_set_bitops(ops);
-+
-+	/*
-+	 * Note:
-+	 * This is *eventually correct*.
-+	 * Setting the fbcon operations and drawing the splash happen at
-+	 * different points in time. If the splash is enabled/disabled
-+	 * in between, then bootsplash_{en,dis}able will schedule a
-+	 * redraw, which will again render the splash (or not) and set
-+	 * the correct fbcon ops.
-+	 * The last run will then be the right one.
-+	 */
-+	if (bootsplash_would_render_now())
-+		fbcon_set_dummyops(ops);
- }
- 
- static int fbcon_invalid_charcount(struct fb_info *info, unsigned charcount)
-@@ -2206,6 +2225,9 @@ static int fbcon_switch(struct vc_data *
- 	info = registered_fb[con2fb_map[vc->vc_num]];
- 	ops = info->fbcon_par;
- 
-+	if (bootsplash_would_render_now())
-+		bootsplash_render_full(info);
-+
- 	if (softback_top) {
- 		if (softback_lines)
- 			fbcon_set_origin(vc);
-diff -up linux-4.18/drivers/video/fbdev/core/fbcon.h.0100~ linux-4.18/drivers/video/fbdev/core/fbcon.h
---- linux-4.18/drivers/video/fbdev/core/fbcon.h.0100~	2018-08-12 22:41:04.000000000 +0200
-+++ linux-4.18/drivers/video/fbdev/core/fbcon.h	2018-08-27 10:28:08.074909396 +0200
-@@ -215,6 +215,11 @@ static inline int attr_col_ec(int shift,
- #define SCROLL_REDRAW	   0x004
- #define SCROLL_PAN_REDRAW  0x005
- 
-+#ifdef CONFIG_BOOTSPLASH
-+extern void fbcon_set_dummyops(struct fbcon_ops *ops);
-+#else /* CONFIG_BOOTSPLASH */
-+#define fbcon_set_dummyops(x)
-+#endif /* CONFIG_BOOTSPLASH */
- #ifdef CONFIG_FB_TILEBLITTING
- extern void fbcon_set_tileops(struct vc_data *vc, struct fb_info *info);
- #endif
-diff -up linux-4.18/drivers/video/fbdev/core/Makefile.0100~ linux-4.18/drivers/video/fbdev/core/Makefile
---- linux-4.18/drivers/video/fbdev/core/Makefile.0100~	2018-08-12 22:41:04.000000000 +0200
-+++ linux-4.18/drivers/video/fbdev/core/Makefile	2018-08-27 10:28:08.074909396 +0200
-@@ -27,3 +27,6 @@ obj-$(CONFIG_FB_SYS_IMAGEBLIT) += sysimg
- obj-$(CONFIG_FB_SYS_FOPS)      += fb_sys_fops.o
- obj-$(CONFIG_FB_SVGALIB)       += svgalib.o
- obj-$(CONFIG_FB_DDC)           += fb_ddc.o
-+
-+obj-$(CONFIG_BOOTSPLASH)       += bootsplash.o bootsplash_render.o \
-+                                  dummyblit.o
-diff -up linux-4.18/include/linux/bootsplash.h.0100~ linux-4.18/include/linux/bootsplash.h
---- linux-4.18/include/linux/bootsplash.h.0100~	2018-08-27 10:28:08.074909396 +0200
-+++ linux-4.18/include/linux/bootsplash.h	2018-08-27 10:28:08.074909396 +0200
-@@ -0,0 +1,43 @@
-+/*
-+ * Kernel based bootsplash.
-+ *
-+ * Authors:
-+ * Max Staudt <mstaudt@suse.de>
-+ *
-+ * SPDX-License-Identifier: GPL-2.0
-+ */
-+
-+#ifndef __LINUX_BOOTSPLASH_H
-+#define __LINUX_BOOTSPLASH_H
-+
-+#include <linux/fb.h>
-+
-+
-+#ifdef CONFIG_BOOTSPLASH
-+
-+extern void bootsplash_render_full(struct fb_info *info);
-+
-+extern bool bootsplash_would_render_now(void);
-+
-+extern bool bootsplash_is_enabled(void);
-+extern void bootsplash_disable(void);
-+extern void bootsplash_enable(void);
-+
-+extern void bootsplash_init(void);
-+
-+#else /* CONFIG_BOOTSPLASH */
-+
-+#define bootsplash_render_full(x)
-+
-+#define bootsplash_would_render_now() (false)
-+
-+#define bootsplash_is_enabled() (false)
-+#define bootsplash_disable()
-+#define bootsplash_enable()
-+
-+#define bootsplash_init()
-+
-+#endif /* CONFIG_BOOTSPLASH */
-+
-+
-+#endif
-diff -up linux-4.18/MAINTAINERS.0100~ linux-4.18/MAINTAINERS
---- linux-4.18/MAINTAINERS.0100~	2018-08-27 10:28:07.950909135 +0200
-+++ linux-4.18/MAINTAINERS	2018-08-27 10:28:08.076909400 +0200
-@@ -2807,6 +2807,14 @@ S:	Supported
- F:	drivers/net/bonding/
- F:	include/uapi/linux/if_bonding.h
- 
-+BOOTSPLASH
-+M:	Max Staudt <mstaudt@suse.de>
-+L:	linux-fbdev@vger.kernel.org
-+S:	Maintained
-+F:	drivers/video/fbdev/core/bootsplash*.*
-+F:	drivers/video/fbdev/core/dummycon.c
-+F:	include/linux/bootsplash.h
-+
- BPF (Safe dynamic programs and tools)
- M:	Alexei Starovoitov <ast@kernel.org>
- M:	Daniel Borkmann <daniel@iogearbox.net>
diff --git a/disabled/RFC-v3-02-13-bootsplash-Add-file-reading-and-picture-rendering.patch b/disabled/RFC-v3-02-13-bootsplash-Add-file-reading-and-picture-rendering.patch
deleted file mode 100644
index 92d62ca..0000000
--- a/disabled/RFC-v3-02-13-bootsplash-Add-file-reading-and-picture-rendering.patch
+++ /dev/null
@@ -1,669 +0,0 @@
-diff --git a/MAINTAINERS b/MAINTAINERS
-index b5633b56391e..5c237445761e 100644
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -2712,6 +2712,7 @@ S:	Maintained
- F:	drivers/video/fbdev/core/bootsplash*.*
- F:	drivers/video/fbdev/core/dummycon.c
- F:	include/linux/bootsplash.h
-+F:	include/uapi/linux/bootsplash_file.h
- 
- BPF (Safe dynamic programs and tools)
- M:	Alexei Starovoitov <ast@kernel.org>
-diff --git a/drivers/video/fbdev/core/Makefile b/drivers/video/fbdev/core/Makefile
-index 66895321928e..6a8d1bab8a01 100644
---- a/drivers/video/fbdev/core/Makefile
-+++ b/drivers/video/fbdev/core/Makefile
-@@ -31,4 +31,4 @@ obj-$(CONFIG_FB_SVGALIB)       += svgalib.o
- obj-$(CONFIG_FB_DDC)           += fb_ddc.o
- 
- obj-$(CONFIG_BOOTSPLASH)       += bootsplash.o bootsplash_render.o \
--                                  dummyblit.o
-+                                  bootsplash_load.o dummyblit.o
-diff --git a/drivers/video/fbdev/core/bootsplash.c b/drivers/video/fbdev/core/bootsplash.c
-index e449755af268..843c5400fefc 100644
---- a/drivers/video/fbdev/core/bootsplash.c
-+++ b/drivers/video/fbdev/core/bootsplash.c
-@@ -32,6 +32,7 @@
- #include <linux/workqueue.h>
- 
- #include "bootsplash_internal.h"
-+#include "uapi/linux/bootsplash_file.h"
- 
- 
- /*
-@@ -102,10 +103,17 @@ static bool is_fb_compatible(const struct fb_info *info)
-  */
- void bootsplash_render_full(struct fb_info *info)
- {
-+	mutex_lock(&splash_state.data_lock);
-+
- 	if (!is_fb_compatible(info))
--		return;
-+		goto out;
-+
-+	bootsplash_do_render_background(info, splash_state.file);
-+
-+	bootsplash_do_render_pictures(info, splash_state.file);
- 
--	bootsplash_do_render_background(info);
-+out:
-+	mutex_unlock(&splash_state.data_lock);
- }
- 
- 
-@@ -116,6 +124,7 @@ bool bootsplash_would_render_now(void)
- {
- 	return !oops_in_progress
- 		&& !console_blanked
-+		&& splash_state.file
- 		&& bootsplash_is_enabled();
- }
- 
-@@ -252,6 +261,7 @@ static struct platform_driver splash_driver = {
- void bootsplash_init(void)
- {
- 	int ret;
-+	struct splash_file_priv *fp;
- 
- 	/* Initialized already? */
- 	if (splash_state.splash_device)
-@@ -280,8 +290,26 @@ void bootsplash_init(void)
- 	}
- 
- 
-+	mutex_init(&splash_state.data_lock);
-+	set_bit(0, &splash_state.enabled);
-+
- 	INIT_WORK(&splash_state.work_redraw_vc, splash_callback_redraw_vc);
- 
-+
-+	if (!splash_state.bootfile || !strlen(splash_state.bootfile))
-+		return;
-+
-+	fp = bootsplash_load_firmware(&splash_state.splash_device->dev,
-+				      splash_state.bootfile);
-+
-+	if (!fp)
-+		goto err;
-+
-+	mutex_lock(&splash_state.data_lock);
-+	splash_state.splash_fb = NULL;
-+	splash_state.file = fp;
-+	mutex_unlock(&splash_state.data_lock);
-+
- 	return;
- 
- err_device:
-@@ -292,3 +320,7 @@ void bootsplash_init(void)
- err:
- 	pr_err("Failed to initialize.\n");
- }
-+
-+
-+module_param_named(bootfile, splash_state.bootfile, charp, 0444);
-+MODULE_PARM_DESC(bootfile, "Bootsplash file to load on boot");
-diff --git a/drivers/video/fbdev/core/bootsplash_internal.h b/drivers/video/fbdev/core/bootsplash_internal.h
-index b11da5cb90bf..71e2a27ac0b8 100644
---- a/drivers/video/fbdev/core/bootsplash_internal.h
-+++ b/drivers/video/fbdev/core/bootsplash_internal.h
-@@ -15,15 +15,43 @@
- 
- #include <linux/types.h>
- #include <linux/fb.h>
-+#include <linux/firmware.h>
- #include <linux/kernel.h>
- #include <linux/mutex.h>
- #include <linux/spinlock.h>
- 
-+#include "uapi/linux/bootsplash_file.h"
-+
- 
- /*
-  * Runtime types
-  */
-+struct splash_blob_priv {
-+	struct splash_blob_header *blob_header;
-+	const void *data;
-+};
-+
-+
-+struct splash_pic_priv {
-+	const struct splash_pic_header *pic_header;
-+
-+	struct splash_blob_priv *blobs;
-+	u16 blobs_loaded;
-+};
-+
-+
-+struct splash_file_priv {
-+	const struct firmware *fw;
-+	const struct splash_file_header *header;
-+
-+	struct splash_pic_priv *pics;
-+};
-+
-+
- struct splash_priv {
-+	/* Bootup and runtime state */
-+	char *bootfile;
-+
- 	/*
- 	 * Enabled/disabled state, to be used with atomic bit operations.
- 	 *   Bit 0: 0 = Splash hidden
-@@ -43,6 +71,13 @@ struct splash_priv {
- 	struct platform_device *splash_device;
- 
- 	struct work_struct work_redraw_vc;
-+
-+	/* Splash data structures including lock for everything below */
-+	struct mutex data_lock;
-+
-+	struct fb_info *splash_fb;
-+
-+	struct splash_file_priv *file;
- };
- 
- 
-@@ -50,6 +85,14 @@ struct splash_priv {
- /*
-  * Rendering functions
-  */
--void bootsplash_do_render_background(struct fb_info *info);
-+void bootsplash_do_render_background(struct fb_info *info,
-+				     const struct splash_file_priv *fp);
-+void bootsplash_do_render_pictures(struct fb_info *info,
-+				   const struct splash_file_priv *fp);
-+
-+
-+void bootsplash_free_file(struct splash_file_priv *fp);
-+struct splash_file_priv *bootsplash_load_firmware(struct device *device,
-+						  const char *path);
- 
- #endif
-diff --git a/drivers/video/fbdev/core/bootsplash_load.c b/drivers/video/fbdev/core/bootsplash_load.c
-new file mode 100644
-index 000000000000..fd807571ab7d
---- /dev/null
-+++ b/drivers/video/fbdev/core/bootsplash_load.c
-@@ -0,0 +1,225 @@
-+/*
-+ * Kernel based bootsplash.
-+ *
-+ * (Loading and freeing functions)
-+ *
-+ * Authors:
-+ * Max Staudt <mstaudt@suse.de>
-+ *
-+ * SPDX-License-Identifier: GPL-2.0
-+ */
-+
-+#define pr_fmt(fmt) "bootsplash: " fmt
-+
-+
-+#include <linux/bootsplash.h>
-+#include <linux/fb.h>
-+#include <linux/firmware.h>
-+#include <linux/kernel.h>
-+#include <linux/mutex.h>
-+#include <linux/printk.h>
-+#include <linux/types.h>
-+#include <linux/vmalloc.h>
-+
-+#include "bootsplash_internal.h"
-+#include "uapi/linux/bootsplash_file.h"
-+
-+
-+
-+
-+/*
-+ * Free all vmalloc()'d resources describing a splash file.
-+ */
-+void bootsplash_free_file(struct splash_file_priv *fp)
-+{
-+	if (!fp)
-+		return;
-+
-+	if (fp->pics) {
-+		unsigned int i;
-+
-+		for (i = 0; i < fp->header->num_pics; i++) {
-+			struct splash_pic_priv *pp = &fp->pics[i];
-+
-+			if (pp->blobs)
-+				vfree(pp->blobs);
-+		}
-+
-+		vfree(fp->pics);
-+	}
-+
-+	release_firmware(fp->fw);
-+	vfree(fp);
-+}
-+
-+
-+
-+
-+/*
-+ * Load a splash screen from a "firmware" file.
-+ *
-+ * Parsing, and sanity checks.
-+ */
-+#ifdef __BIG_ENDIAN
-+	#define BOOTSPLASH_MAGIC BOOTSPLASH_MAGIC_BE
-+#else
-+	#define BOOTSPLASH_MAGIC BOOTSPLASH_MAGIC_LE
-+#endif
-+
-+struct splash_file_priv *bootsplash_load_firmware(struct device *device,
-+						  const char *path)
-+{
-+	const struct firmware *fw;
-+	struct splash_file_priv *fp;
-+	unsigned int i;
-+	const u8 *walker;
-+
-+	if (request_firmware(&fw, path, device))
-+		return NULL;
-+
-+	if (fw->size < sizeof(struct splash_file_header)
-+	    || memcmp(fw->data, BOOTSPLASH_MAGIC, sizeof(fp->header->id))) {
-+		pr_err("Not a bootsplash file.\n");
-+
-+		release_firmware(fw);
-+		return NULL;
-+	}
-+
-+	fp = vzalloc(sizeof(struct splash_file_priv));
-+	if (!fp) {
-+		release_firmware(fw);
-+		return NULL;
-+	}
-+
-+	pr_info("Loading splash file (%li bytes)\n", fw->size);
-+
-+	fp->fw = fw;
-+	fp->header = (struct splash_file_header *)fw->data;
-+
-+	/* Sanity checks */
-+	if (fp->header->version != BOOTSPLASH_VERSION) {
-+		pr_err("Loaded v%d file, but we only support version %d\n",
-+			fp->header->version,
-+			BOOTSPLASH_VERSION);
-+
-+		goto err;
-+	}
-+
-+	if (fw->size < sizeof(struct splash_file_header)
-+		+ fp->header->num_pics
-+			* sizeof(struct splash_pic_header)
-+		+ fp->header->num_blobs
-+			* sizeof(struct splash_blob_header)) {
-+		pr_err("File incomplete.\n");
-+
-+		goto err;
-+	}
-+
-+	/* Read picture headers */
-+	if (fp->header->num_pics) {
-+		fp->pics = vzalloc(fp->header->num_pics
-+				   * sizeof(struct splash_pic_priv));
-+		if (!fp->pics)
-+			goto err;
-+	}
-+
-+	walker = fw->data + sizeof(struct splash_file_header);
-+	for (i = 0; i < fp->header->num_pics; i++) {
-+		struct splash_pic_priv *pp = &fp->pics[i];
-+		struct splash_pic_header *ph = (void *)walker;
-+
-+		pr_debug("Picture %u: Size %ux%u\n", i, ph->width, ph->height);
-+
-+		if (ph->num_blobs < 1) {
-+			pr_err("Picture %u: Zero blobs? Aborting load.\n", i);
-+			goto err;
-+		}
-+
-+		pp->pic_header = ph;
-+		pp->blobs = vzalloc(ph->num_blobs
-+					* sizeof(struct splash_blob_priv));
-+		if (!pp->blobs)
-+			goto err;
-+
-+		walker += sizeof(struct splash_pic_header);
-+	}
-+
-+	/* Read blob headers */
-+	for (i = 0; i < fp->header->num_blobs; i++) {
-+		struct splash_blob_header *bh = (void *)walker;
-+		struct splash_pic_priv *pp;
-+
-+		if (walker + sizeof(struct splash_blob_header)
-+		    > fw->data + fw->size)
-+			goto err;
-+
-+		walker += sizeof(struct splash_blob_header);
-+
-+		if (walker + bh->length > fw->data + fw->size)
-+			goto err;
-+
-+		if (bh->picture_id >= fp->header->num_pics)
-+			goto nextblob;
-+
-+		pp = &fp->pics[bh->picture_id];
-+
-+		pr_debug("Blob %u, pic %u, blobs_loaded %u, num_blobs %u.\n",
-+			 i, bh->picture_id,
-+			 pp->blobs_loaded, pp->pic_header->num_blobs);
-+
-+		if (pp->blobs_loaded >= pp->pic_header->num_blobs)
-+			goto nextblob;
-+
-+		switch (bh->type) {
-+		case 0:
-+			/* Raw 24-bit packed pixels */
-+			if (bh->length != pp->pic_header->width
-+					* pp->pic_header->height * 3) {
-+				pr_err("Blob %u, type 1: Length doesn't match picture.\n",
-+				       i);
-+
-+				goto err;
-+			}
-+			break;
-+		default:
-+			pr_warn("Blob %u, unknown type %u.\n", i, bh->type);
-+			goto nextblob;
-+		}
-+
-+		pp->blobs[pp->blobs_loaded].blob_header = bh;
-+		pp->blobs[pp->blobs_loaded].data = walker;
-+		pp->blobs_loaded++;
-+
-+nextblob:
-+		walker += bh->length;
-+		if (bh->length % 16)
-+			walker += 16 - (bh->length % 16);
-+	}
-+
-+	if (walker != fw->data + fw->size)
-+		pr_warn("Trailing data in splash file.\n");
-+
-+	/* Walk over pictures and ensure all blob slots are filled */
-+	for (i = 0; i < fp->header->num_pics; i++) {
-+		struct splash_pic_priv *pp = &fp->pics[i];
-+
-+		if (pp->blobs_loaded != pp->pic_header->num_blobs) {
-+			pr_err("Picture %u doesn't have all blob slots filled.\n",
-+			       i);
-+
-+			goto err;
-+		}
-+	}
-+
-+	pr_info("Loaded (%ld bytes, %u pics, %u blobs).\n",
-+		fw->size,
-+		fp->header->num_pics,
-+		fp->header->num_blobs);
-+
-+	return fp;
-+
-+
-+err:
-+	bootsplash_free_file(fp);
-+	return NULL;
-+}
-diff --git a/drivers/video/fbdev/core/bootsplash_render.c b/drivers/video/fbdev/core/bootsplash_render.c
-index 4d7e0117f653..2ae36949d0e3 100644
---- a/drivers/video/fbdev/core/bootsplash_render.c
-+++ b/drivers/video/fbdev/core/bootsplash_render.c
-@@ -19,6 +19,7 @@
- #include <linux/types.h>
- 
- #include "bootsplash_internal.h"
-+#include "uapi/linux/bootsplash_file.h"
- 
- 
- 
-@@ -70,16 +71,69 @@ static inline u32 pack_pixel(const struct fb_var_screeninfo *dst_var,
- }
- 
- 
--void bootsplash_do_render_background(struct fb_info *info)
-+/*
-+ * Copy from source and blend into the destination picture.
-+ * Currently assumes that the source picture is 24bpp.
-+ * Currently assumes that the destination is <= 32bpp.
-+ */
-+static int splash_convert_to_fb(u8 *dst,
-+				const struct fb_var_screeninfo *dst_var,
-+				unsigned int dst_stride,
-+				unsigned int dst_xoff,
-+				unsigned int dst_yoff,
-+				const u8 *src,
-+				unsigned int src_width,
-+				unsigned int src_height)
-+{
-+	unsigned int x, y;
-+	unsigned int src_stride = 3 * src_width; /* Assume 24bpp packed */
-+	u32 dst_octpp = dst_var->bits_per_pixel / 8;
-+
-+	dst_xoff += dst_var->xoffset;
-+	dst_yoff += dst_var->yoffset;
-+
-+	/* Copy with stride and pixel size adjustment */
-+	for (y = 0;
-+	     y < src_height && y + dst_yoff < dst_var->yres_virtual;
-+	     y++) {
-+		const u8 *srcline = src + (y * src_stride);
-+		u8 *dstline = dst + ((y + dst_yoff) * dst_stride)
-+				  + (dst_xoff * dst_octpp);
-+
-+		for (x = 0;
-+		     x < src_width && x + dst_xoff < dst_var->xres_virtual;
-+		     x++) {
-+			u8 red, green, blue;
-+			u32 dstpix;
-+
-+			/* Read pixel */
-+			red = *srcline++;
-+			green = *srcline++;
-+			blue = *srcline++;
-+
-+			/* Write pixel */
-+			dstpix = pack_pixel(dst_var, red, green, blue);
-+			memcpy(dstline, &dstpix, dst_octpp);
-+
-+			dstline += dst_octpp;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+
-+void bootsplash_do_render_background(struct fb_info *info,
-+				     const struct splash_file_priv *fp)
- {
- 	unsigned int x, y;
- 	u32 dstpix;
- 	u32 dst_octpp = info->var.bits_per_pixel / 8;
- 
- 	dstpix = pack_pixel(&info->var,
--			    0,
--			    0,
--			    0);
-+			    fp->header->bg_red,
-+			    fp->header->bg_green,
-+			    fp->header->bg_blue);
- 
- 	for (y = 0; y < info->var.yres_virtual; y++) {
- 		u8 *dstline = info->screen_buffer + (y * info->fix.line_length);
-@@ -91,3 +145,44 @@ void bootsplash_do_render_background(struct fb_info *info)
- 		}
- 	}
- }
-+
-+
-+void bootsplash_do_render_pictures(struct fb_info *info,
-+				   const struct splash_file_priv *fp)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < fp->header->num_pics; i++) {
-+		struct splash_blob_priv *bp;
-+		struct splash_pic_priv *pp = &fp->pics[i];
-+		long dst_xoff, dst_yoff;
-+
-+		if (pp->blobs_loaded < 1)
-+			continue;
-+
-+		bp = &pp->blobs[0];
-+
-+		if (!bp || bp->blob_header->type != 0)
-+			continue;
-+
-+		dst_xoff = (info->var.xres - pp->pic_header->width) / 2;
-+		dst_yoff = (info->var.yres - pp->pic_header->height) / 2;
-+
-+		if (dst_xoff < 0
-+		    || dst_yoff < 0
-+		    || dst_xoff + pp->pic_header->width > info->var.xres
-+		    || dst_yoff + pp->pic_header->height > info->var.yres) {
-+			pr_info_once("Picture %u is out of bounds at current resolution: %dx%d\n"
-+				     "(this will only be printed once every reboot)\n",
-+				     i, info->var.xres, info->var.yres);
-+
-+			continue;
-+		}
-+
-+		/* Draw next splash frame */
-+		splash_convert_to_fb(info->screen_buffer, &info->var,
-+				info->fix.line_length, dst_xoff, dst_yoff,
-+				bp->data,
-+				pp->pic_header->width, pp->pic_header->height);
-+	}
-+}
-diff --git a/include/uapi/linux/bootsplash_file.h b/include/uapi/linux/bootsplash_file.h
-new file mode 100644
-index 000000000000..89dc9cca8f0c
---- /dev/null
-+++ b/include/uapi/linux/bootsplash_file.h
-@@ -0,0 +1,118 @@
-+/*
-+ * Kernel based bootsplash.
-+ *
-+ * (File format)
-+ *
-+ * Authors:
-+ * Max Staudt <mstaudt@suse.de>
-+ *
-+ * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
-+ */
-+
-+#ifndef __BOOTSPLASH_FILE_H
-+#define __BOOTSPLASH_FILE_H
-+
-+
-+#define BOOTSPLASH_VERSION 55561
-+
-+
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+
-+
-+/*
-+ * On-disk types
-+ *
-+ * A splash file consists of:
-+ *  - One single 'struct splash_file_header'
-+ *  - An array of 'struct splash_pic_header'
-+ *  - An array of raw data blocks, each padded to 16 bytes and
-+ *    preceded by a 'struct splash_blob_header'
-+ *
-+ * A single-frame splash may look like this:
-+ *
-+ * +--------------------+
-+ * |                    |
-+ * | splash_file_header |
-+ * |  -> num_blobs = 1  |
-+ * |  -> num_pics = 1   |
-+ * |                    |
-+ * +--------------------+
-+ * |                    |
-+ * | splash_pic_header  |
-+ * |                    |
-+ * +--------------------+
-+ * |                    |
-+ * | splash_blob_header |
-+ * |  -> type = 0       |
-+ * |  -> picture_id = 0 |
-+ * |                    |
-+ * | (raw RGB data)     |
-+ * | (pad to 16 bytes)  |
-+ * |                    |
-+ * +--------------------+
-+ *
-+ * All multi-byte values are stored on disk in the native format
-+ * expected by the system the file will be used on.
-+ */
-+#define BOOTSPLASH_MAGIC_BE "Linux bootsplash"
-+#define BOOTSPLASH_MAGIC_LE "hsalpstoob xuniL"
-+
-+struct splash_file_header {
-+	uint8_t  id[16]; /* "Linux bootsplash" (no trailing NUL) */
-+
-+	/* Splash file format version to avoid clashes */
-+	uint16_t version;
-+
-+	/* The background color */
-+	uint8_t bg_red;
-+	uint8_t bg_green;
-+	uint8_t bg_blue;
-+	uint8_t bg_reserved;
-+
-+	/*
-+	 * Number of pic/blobs so we can allocate memory for internal
-+	 * structures ahead of time when reading the file
-+	 */
-+	uint16_t num_blobs;
-+	uint8_t num_pics;
-+
-+	uint8_t padding[103];
-+} __attribute__((__packed__));
-+
-+
-+struct splash_pic_header {
-+	uint16_t width;
-+	uint16_t height;
-+
-+	/*
-+	 * Number of data packages associated with this picture.
-+	 * Currently, the only use for more than 1 is for animations.
-+	 */
-+	uint8_t num_blobs;
-+
-+	uint8_t padding[27];
-+} __attribute__((__packed__));
-+
-+
-+struct splash_blob_header {
-+	/* Length of the data block in bytes. */
-+	uint32_t length;
-+
-+	/*
-+	 * Type of the contents.
-+	 *  0 - Raw RGB data.
-+	 */
-+	uint16_t type;
-+
-+	/*
-+	 * Picture this blob is associated with.
-+	 * Blobs will be added to a picture in the order they are
-+	 * found in the file.
-+	 */
-+	uint8_t picture_id;
-+
-+	uint8_t padding[9];
-+} __attribute__((__packed__));
-+
-+#endif
diff --git a/disabled/RFC-v3-03-13-bootsplash-Flush-framebuffer-after-drawing.patch b/disabled/RFC-v3-03-13-bootsplash-Flush-framebuffer-after-drawing.patch
deleted file mode 100644
index 2169537..0000000
--- a/disabled/RFC-v3-03-13-bootsplash-Flush-framebuffer-after-drawing.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-diff --git a/drivers/video/fbdev/core/bootsplash.c b/drivers/video/fbdev/core/bootsplash.c
-index 843c5400fefc..815b007f81ca 100644
---- a/drivers/video/fbdev/core/bootsplash.c
-+++ b/drivers/video/fbdev/core/bootsplash.c
-@@ -112,6 +112,8 @@ void bootsplash_render_full(struct fb_info *info)
- 
- 	bootsplash_do_render_pictures(info, splash_state.file);
- 
-+	bootsplash_do_render_flush(info);
-+
- out:
- 	mutex_unlock(&splash_state.data_lock);
- }
-diff --git a/drivers/video/fbdev/core/bootsplash_internal.h b/drivers/video/fbdev/core/bootsplash_internal.h
-index 71e2a27ac0b8..0acb383aa4e3 100644
---- a/drivers/video/fbdev/core/bootsplash_internal.h
-+++ b/drivers/video/fbdev/core/bootsplash_internal.h
-@@ -89,6 +89,7 @@ void bootsplash_do_render_background(struct fb_info *info,
- 				     const struct splash_file_priv *fp);
- void bootsplash_do_render_pictures(struct fb_info *info,
- 				   const struct splash_file_priv *fp);
-+void bootsplash_do_render_flush(struct fb_info *info);
- 
- 
- void bootsplash_free_file(struct splash_file_priv *fp);
-diff --git a/drivers/video/fbdev/core/bootsplash_render.c b/drivers/video/fbdev/core/bootsplash_render.c
-index 2ae36949d0e3..8c09c306ff67 100644
---- a/drivers/video/fbdev/core/bootsplash_render.c
-+++ b/drivers/video/fbdev/core/bootsplash_render.c
-@@ -186,3 +186,36 @@ void bootsplash_do_render_pictures(struct fb_info *info,
- 				pp->pic_header->width, pp->pic_header->height);
- 	}
- }
-+
-+
-+void bootsplash_do_render_flush(struct fb_info *info)
-+{
-+	/*
-+	 * FB drivers using deferred_io (such as Xen) need to sync the
-+	 * screen after modifying its contents. When the FB is mmap()ed
-+	 * from userspace, this happens via a dirty pages callback, but
-+	 * when modifying the FB from the kernel, there is no such thing.
-+	 *
-+	 * So let's issue a fake fb_copyarea (copying the FB onto itself)
-+	 * to trick the FB driver into syncing the screen.
-+	 *
-+	 * A few DRM drivers' FB implementations are broken by not using
-+	 * deferred_io when they really should - we match on the known
-+	 * bad ones manually for now.
-+	 */
-+	if (info->fbdefio
-+	    || !strcmp(info->fix.id, "astdrmfb")
-+	    || !strcmp(info->fix.id, "cirrusdrmfb")
-+	    || !strcmp(info->fix.id, "mgadrmfb")) {
-+		struct fb_copyarea area;
-+
-+		area.dx = 0;
-+		area.dy = 0;
-+		area.width = info->var.xres;
-+		area.height = info->var.yres;
-+		area.sx = 0;
-+		area.sy = 0;
-+
-+		info->fbops->fb_copyarea(info, &area);
-+	}
-+}
diff --git a/disabled/RFC-v3-04-13-bootsplash-Add-corner-positioning.patch b/disabled/RFC-v3-04-13-bootsplash-Add-corner-positioning.patch
deleted file mode 100644
index 7eb54af..0000000
--- a/disabled/RFC-v3-04-13-bootsplash-Add-corner-positioning.patch
+++ /dev/null
@@ -1,215 +0,0 @@
-diff --git a/drivers/video/fbdev/core/bootsplash_render.c b/drivers/video/fbdev/core/bootsplash_render.c
-index 8c09c306ff67..07e3a4eab811 100644
---- a/drivers/video/fbdev/core/bootsplash_render.c
-+++ b/drivers/video/fbdev/core/bootsplash_render.c
-@@ -155,6 +155,7 @@ void bootsplash_do_render_pictures(struct fb_info *info,
- 	for (i = 0; i < fp->header->num_pics; i++) {
- 		struct splash_blob_priv *bp;
- 		struct splash_pic_priv *pp = &fp->pics[i];
-+		const struct splash_pic_header *ph = pp->pic_header;
- 		long dst_xoff, dst_yoff;
- 
- 		if (pp->blobs_loaded < 1)
-@@ -165,8 +166,139 @@ void bootsplash_do_render_pictures(struct fb_info *info,
- 		if (!bp || bp->blob_header->type != 0)
- 			continue;
- 
--		dst_xoff = (info->var.xres - pp->pic_header->width) / 2;
--		dst_yoff = (info->var.yres - pp->pic_header->height) / 2;
-+		switch (ph->position) {
-+		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_TOP_LEFT:
-+			dst_xoff = 0;
-+			dst_yoff = 0;
-+
-+			dst_xoff += ph->position_offset;
-+			dst_yoff += ph->position_offset;
-+			break;
-+		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_TOP:
-+			dst_xoff = info->var.xres - pp->pic_header->width;
-+			dst_xoff /= 2;
-+			dst_yoff = 0;
-+
-+			dst_yoff += ph->position_offset;
-+			break;
-+		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_TOP_RIGHT:
-+			dst_xoff = info->var.xres - pp->pic_header->width;
-+			dst_yoff = 0;
-+
-+			dst_xoff -= ph->position_offset;
-+			dst_yoff += ph->position_offset;
-+			break;
-+		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_RIGHT:
-+			dst_xoff = info->var.xres - pp->pic_header->width;
-+			dst_yoff = info->var.yres - pp->pic_header->height;
-+			dst_yoff /= 2;
-+
-+			dst_xoff -= ph->position_offset;
-+			break;
-+		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_BOTTOM_RIGHT:
-+			dst_xoff = info->var.xres - pp->pic_header->width;
-+			dst_yoff = info->var.yres - pp->pic_header->height;
-+
-+			dst_xoff -= ph->position_offset;
-+			dst_yoff -= ph->position_offset;
-+			break;
-+		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_BOTTOM:
-+			dst_xoff = info->var.xres - pp->pic_header->width;
-+			dst_xoff /= 2;
-+			dst_yoff = info->var.yres - pp->pic_header->height;
-+
-+			dst_yoff -= ph->position_offset;
-+			break;
-+		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_BOTTOM_LEFT:
-+			dst_xoff = 0 + ph->position_offset;
-+			dst_yoff = info->var.yres - pp->pic_header->height
-+						  - ph->position_offset;
-+			break;
-+		case SPLASH_POS_FLAG_CORNER | SPLASH_CORNER_LEFT:
-+			dst_xoff = 0;
-+			dst_yoff = info->var.yres - pp->pic_header->height;
-+			dst_yoff /= 2;
-+
-+			dst_xoff += ph->position_offset;
-+			break;
-+
-+		case SPLASH_CORNER_TOP_LEFT:
-+			dst_xoff = info->var.xres - pp->pic_header->width;
-+			dst_xoff /= 2;
-+			dst_yoff = info->var.yres - pp->pic_header->height;
-+			dst_yoff /= 2;
-+
-+			dst_xoff -= ph->position_offset;
-+			dst_yoff -= ph->position_offset;
-+			break;
-+		case SPLASH_CORNER_TOP:
-+			dst_xoff = info->var.xres - pp->pic_header->width;
-+			dst_xoff /= 2;
-+			dst_yoff = info->var.yres - pp->pic_header->height;
-+			dst_yoff /= 2;
-+
-+			dst_yoff -= ph->position_offset;
-+			break;
-+		case SPLASH_CORNER_TOP_RIGHT:
-+			dst_xoff = info->var.xres - pp->pic_header->width;
-+			dst_xoff /= 2;
-+			dst_yoff = info->var.yres - pp->pic_header->height;
-+			dst_yoff /= 2;
-+
-+			dst_xoff += ph->position_offset;
-+			dst_yoff -= ph->position_offset;
-+			break;
-+		case SPLASH_CORNER_RIGHT:
-+			dst_xoff = info->var.xres - pp->pic_header->width;
-+			dst_xoff /= 2;
-+			dst_yoff = info->var.yres - pp->pic_header->height;
-+			dst_yoff /= 2;
-+
-+			dst_xoff += ph->position_offset;
-+			break;
-+		case SPLASH_CORNER_BOTTOM_RIGHT:
-+			dst_xoff = info->var.xres - pp->pic_header->width;
-+			dst_xoff /= 2;
-+			dst_yoff = info->var.yres - pp->pic_header->height;
-+			dst_yoff /= 2;
-+
-+			dst_xoff += ph->position_offset;
-+			dst_yoff += ph->position_offset;
-+			break;
-+		case SPLASH_CORNER_BOTTOM:
-+			dst_xoff = info->var.xres - pp->pic_header->width;
-+			dst_xoff /= 2;
-+			dst_yoff = info->var.yres - pp->pic_header->height;
-+			dst_yoff /= 2;
-+
-+			dst_yoff += ph->position_offset;
-+			break;
-+		case SPLASH_CORNER_BOTTOM_LEFT:
-+			dst_xoff = info->var.xres - pp->pic_header->width;
-+			dst_xoff /= 2;
-+			dst_yoff = info->var.yres - pp->pic_header->height;
-+			dst_yoff /= 2;
-+
-+			dst_xoff -= ph->position_offset;
-+			dst_yoff += ph->position_offset;
-+			break;
-+		case SPLASH_CORNER_LEFT:
-+			dst_xoff = info->var.xres - pp->pic_header->width;
-+			dst_xoff /= 2;
-+			dst_yoff = info->var.yres - pp->pic_header->height;
-+			dst_yoff /= 2;
-+
-+			dst_xoff -= ph->position_offset;
-+			break;
-+
-+		default:
-+			/* As a fallback, center the picture. */
-+			dst_xoff = info->var.xres - pp->pic_header->width;
-+			dst_xoff /= 2;
-+			dst_yoff = info->var.yres - pp->pic_header->height;
-+			dst_yoff /= 2;
-+			break;
-+		}
- 
- 		if (dst_xoff < 0
- 		    || dst_yoff < 0
-diff --git a/include/uapi/linux/bootsplash_file.h b/include/uapi/linux/bootsplash_file.h
-index 89dc9cca8f0c..71cedcc68933 100644
---- a/include/uapi/linux/bootsplash_file.h
-+++ b/include/uapi/linux/bootsplash_file.h
-@@ -91,7 +91,32 @@ struct splash_pic_header {
- 	 */
- 	uint8_t num_blobs;
- 
--	uint8_t padding[27];
-+	/*
-+	 * Corner to move the picture to / from.
-+	 *  0x00 - Top left
-+	 *  0x01 - Top
-+	 *  0x02 - Top right
-+	 *  0x03 - Right
-+	 *  0x04 - Bottom right
-+	 *  0x05 - Bottom
-+	 *  0x06 - Bottom left
-+	 *  0x07 - Left
-+	 *
-+	 * Flags:
-+	 *  0x10 - Calculate offset from the corner towards the center,
-+	 *         rather than from the center towards the corner
-+	 */
-+	uint8_t position;
-+
-+	/*
-+	 * Pixel offset from the selected position.
-+	 * Example: If the picture is in the top right corner, it will
-+	 *          be placed position_offset pixels from the top and
-+	 *          position_offset pixels from the right margin.
-+	 */
-+	uint16_t position_offset;
-+
-+	uint8_t padding[24];
- } __attribute__((__packed__));
- 
- 
-@@ -115,4 +140,22 @@ struct splash_blob_header {
- 	uint8_t padding[9];
- } __attribute__((__packed__));
- 
-+
-+
-+
-+/*
-+ * Enums for on-disk types
-+ */
-+enum splash_position {
-+	SPLASH_CORNER_TOP_LEFT = 0,
-+	SPLASH_CORNER_TOP = 1,
-+	SPLASH_CORNER_TOP_RIGHT = 2,
-+	SPLASH_CORNER_RIGHT = 3,
-+	SPLASH_CORNER_BOTTOM_RIGHT = 4,
-+	SPLASH_CORNER_BOTTOM = 5,
-+	SPLASH_CORNER_BOTTOM_LEFT = 6,
-+	SPLASH_CORNER_LEFT = 7,
-+	SPLASH_POS_FLAG_CORNER = 0x10,
-+};
-+
- #endif
diff --git a/disabled/RFC-v3-05-13-bootsplash-Add-animation-support.patch b/disabled/RFC-v3-05-13-bootsplash-Add-animation-support.patch
deleted file mode 100644
index 2785c5e..0000000
--- a/disabled/RFC-v3-05-13-bootsplash-Add-animation-support.patch
+++ /dev/null
@@ -1,327 +0,0 @@
-diff --git a/drivers/video/fbdev/core/bootsplash.c b/drivers/video/fbdev/core/bootsplash.c
-index 815b007f81ca..c8642142cfea 100644
---- a/drivers/video/fbdev/core/bootsplash.c
-+++ b/drivers/video/fbdev/core/bootsplash.c
-@@ -53,6 +53,14 @@ static void splash_callback_redraw_vc(struct work_struct *ignored)
- 	console_unlock();
- }
- 
-+static void splash_callback_animation(struct work_struct *ignored)
-+{
-+	if (bootsplash_would_render_now()) {
-+		/* This will also re-schedule this delayed worker */
-+		splash_callback_redraw_vc(ignored);
-+	}
-+}
-+
- 
- static bool is_fb_compatible(const struct fb_info *info)
- {
-@@ -103,17 +111,44 @@ static bool is_fb_compatible(const struct fb_info *info)
-  */
- void bootsplash_render_full(struct fb_info *info)
- {
-+	bool is_update = false;
-+
- 	mutex_lock(&splash_state.data_lock);
- 
--	if (!is_fb_compatible(info))
--		goto out;
-+	/*
-+	 * If we've painted on this FB recently, we don't have to do
-+	 * the sanity checks and background drawing again.
-+	 */
-+	if (splash_state.splash_fb == info)
-+		is_update = true;
-+
-+
-+	if (!is_update) {
-+		/* Check whether we actually support this FB. */
-+		splash_state.splash_fb = NULL;
-+
-+		if (!is_fb_compatible(info))
-+			goto out;
-+
-+		/* Draw the background only once */
-+		bootsplash_do_render_background(info, splash_state.file);
- 
--	bootsplash_do_render_background(info, splash_state.file);
-+		/* Mark this FB as last seen */
-+		splash_state.splash_fb = info;
-+	}
- 
--	bootsplash_do_render_pictures(info, splash_state.file);
-+	bootsplash_do_render_pictures(info, splash_state.file, is_update);
- 
- 	bootsplash_do_render_flush(info);
- 
-+	bootsplash_do_step_animations(splash_state.file);
-+
-+	/* Schedule update for animated splash screens */
-+	if (splash_state.file->frame_ms > 0)
-+		schedule_delayed_work(&splash_state.dwork_animation,
-+				      msecs_to_jiffies(
-+				      splash_state.file->frame_ms));
-+
- out:
- 	mutex_unlock(&splash_state.data_lock);
- }
-@@ -169,8 +204,14 @@ void bootsplash_enable(void)
- 
- 	was_enabled = test_and_set_bit(0, &splash_state.enabled);
- 
--	if (!was_enabled)
-+	if (!was_enabled) {
-+		/* Force a full redraw when the splash is re-activated */
-+		mutex_lock(&splash_state.data_lock);
-+		splash_state.splash_fb = NULL;
-+		mutex_unlock(&splash_state.data_lock);
-+
- 		schedule_work(&splash_state.work_redraw_vc);
-+	}
- }
- 
- 
-@@ -227,6 +268,14 @@ ATTRIBUTE_GROUPS(splash_dev);
-  */
- static int splash_resume(struct device *device)
- {
-+	/*
-+	 * Force full redraw on resume since we've probably lost the
-+	 * framebuffer's contents meanwhile
-+	 */
-+	mutex_lock(&splash_state.data_lock);
-+	splash_state.splash_fb = NULL;
-+	mutex_unlock(&splash_state.data_lock);
-+
- 	if (bootsplash_would_render_now())
- 		schedule_work(&splash_state.work_redraw_vc);
- 
-@@ -235,6 +284,7 @@ static int splash_resume(struct device *device)
- 
- static int splash_suspend(struct device *device)
- {
-+	cancel_delayed_work_sync(&splash_state.dwork_animation);
- 	cancel_work_sync(&splash_state.work_redraw_vc);
- 
- 	return 0;
-@@ -296,6 +346,8 @@ void bootsplash_init(void)
- 	set_bit(0, &splash_state.enabled);
- 
- 	INIT_WORK(&splash_state.work_redraw_vc, splash_callback_redraw_vc);
-+	INIT_DELAYED_WORK(&splash_state.dwork_animation,
-+			  splash_callback_animation);
- 
- 
- 	if (!splash_state.bootfile || !strlen(splash_state.bootfile))
-diff --git a/drivers/video/fbdev/core/bootsplash_internal.h b/drivers/video/fbdev/core/bootsplash_internal.h
-index 0acb383aa4e3..b3a74835d90f 100644
---- a/drivers/video/fbdev/core/bootsplash_internal.h
-+++ b/drivers/video/fbdev/core/bootsplash_internal.h
-@@ -37,6 +37,8 @@ struct splash_pic_priv {
- 
- 	struct splash_blob_priv *blobs;
- 	u16 blobs_loaded;
-+
-+	u16 anim_nextframe;
- };
- 
- 
-@@ -45,6 +47,12 @@ struct splash_file_priv {
- 	const struct splash_file_header *header;
- 
- 	struct splash_pic_priv *pics;
-+
-+	/*
-+	 * A local copy of the frame delay in the header.
-+	 * We modify it to keep the code simple.
-+	 */
-+	u16 frame_ms;
- };
- 
- 
-@@ -71,6 +79,7 @@ struct splash_priv {
- 	struct platform_device *splash_device;
- 
- 	struct work_struct work_redraw_vc;
-+	struct delayed_work dwork_animation;
- 
- 	/* Splash data structures including lock for everything below */
- 	struct mutex data_lock;
-@@ -88,8 +97,10 @@ struct splash_priv {
- void bootsplash_do_render_background(struct fb_info *info,
- 				     const struct splash_file_priv *fp);
- void bootsplash_do_render_pictures(struct fb_info *info,
--				   const struct splash_file_priv *fp);
-+				   const struct splash_file_priv *fp,
-+				   bool is_update);
- void bootsplash_do_render_flush(struct fb_info *info);
-+void bootsplash_do_step_animations(struct splash_file_priv *fp);
- 
- 
- void bootsplash_free_file(struct splash_file_priv *fp);
-diff --git a/drivers/video/fbdev/core/bootsplash_load.c b/drivers/video/fbdev/core/bootsplash_load.c
-index fd807571ab7d..1f661b2d4cc9 100644
---- a/drivers/video/fbdev/core/bootsplash_load.c
-+++ b/drivers/video/fbdev/core/bootsplash_load.c
-@@ -71,6 +71,7 @@ struct splash_file_priv *bootsplash_load_firmware(struct device *device,
- {
- 	const struct firmware *fw;
- 	struct splash_file_priv *fp;
-+	bool have_anim = false;
- 	unsigned int i;
- 	const u8 *walker;
- 
-@@ -135,6 +136,13 @@ struct splash_file_priv *bootsplash_load_firmware(struct device *device,
- 			goto err;
- 		}
- 
-+		if (ph->anim_type > SPLASH_ANIM_LOOP_FORWARD) {
-+			pr_warn("Picture %u: Unsupported animation type %u.\n",
-+				i, ph->anim_type);
-+
-+			ph->anim_type = SPLASH_ANIM_NONE;
-+		}
-+
- 		pp->pic_header = ph;
- 		pp->blobs = vzalloc(ph->num_blobs
- 					* sizeof(struct splash_blob_priv));
-@@ -202,6 +210,7 @@ struct splash_file_priv *bootsplash_load_firmware(struct device *device,
- 	/* Walk over pictures and ensure all blob slots are filled */
- 	for (i = 0; i < fp->header->num_pics; i++) {
- 		struct splash_pic_priv *pp = &fp->pics[i];
-+		const struct splash_pic_header *ph = pp->pic_header;
- 
- 		if (pp->blobs_loaded != pp->pic_header->num_blobs) {
- 			pr_err("Picture %u doesn't have all blob slots filled.\n",
-@@ -209,8 +218,20 @@ struct splash_file_priv *bootsplash_load_firmware(struct device *device,
- 
- 			goto err;
- 		}
-+
-+		if (ph->anim_type
-+		    && ph->num_blobs > 1
-+		    && ph->anim_loop < pp->blobs_loaded)
-+			have_anim = true;
- 	}
- 
-+	if (!have_anim)
-+		/* Disable animation timer if there is nothing to animate */
-+		fp->frame_ms = 0;
-+	else
-+		/* Enforce minimum delay between frames */
-+		fp->frame_ms = max((u16)20, fp->header->frame_ms);
-+
- 	pr_info("Loaded (%ld bytes, %u pics, %u blobs).\n",
- 		fw->size,
- 		fp->header->num_pics,
-diff --git a/drivers/video/fbdev/core/bootsplash_render.c b/drivers/video/fbdev/core/bootsplash_render.c
-index 07e3a4eab811..76033606ca8a 100644
---- a/drivers/video/fbdev/core/bootsplash_render.c
-+++ b/drivers/video/fbdev/core/bootsplash_render.c
-@@ -148,7 +148,8 @@ void bootsplash_do_render_background(struct fb_info *info,
- 
- 
- void bootsplash_do_render_pictures(struct fb_info *info,
--				   const struct splash_file_priv *fp)
-+				   const struct splash_file_priv *fp,
-+				   bool is_update)
- {
- 	unsigned int i;
- 
-@@ -161,7 +162,11 @@ void bootsplash_do_render_pictures(struct fb_info *info,
- 		if (pp->blobs_loaded < 1)
- 			continue;
- 
--		bp = &pp->blobs[0];
-+		/* Skip static pictures when refreshing animations */
-+		if (ph->anim_type == SPLASH_ANIM_NONE && is_update)
-+			continue;
-+
-+		bp = &pp->blobs[pp->anim_nextframe];
- 
- 		if (!bp || bp->blob_header->type != 0)
- 			continue;
-@@ -351,3 +356,24 @@ void bootsplash_do_render_flush(struct fb_info *info)
- 		info->fbops->fb_copyarea(info, &area);
- 	}
- }
-+
-+
-+void bootsplash_do_step_animations(struct splash_file_priv *fp)
-+{
-+	unsigned int i;
-+
-+	/* Step every animation once */
-+	for (i = 0; i < fp->header->num_pics; i++) {
-+		struct splash_pic_priv *pp = &fp->pics[i];
-+
-+		if (pp->blobs_loaded < 2
-+		    || pp->pic_header->anim_loop > pp->blobs_loaded)
-+			continue;
-+
-+		if (pp->pic_header->anim_type == SPLASH_ANIM_LOOP_FORWARD) {
-+			pp->anim_nextframe++;
-+			if (pp->anim_nextframe >= pp->pic_header->num_blobs)
-+				pp->anim_nextframe = pp->pic_header->anim_loop;
-+		}
-+	}
-+}
-diff --git a/include/uapi/linux/bootsplash_file.h b/include/uapi/linux/bootsplash_file.h
-index 71cedcc68933..b3af0a3c6487 100644
---- a/include/uapi/linux/bootsplash_file.h
-+++ b/include/uapi/linux/bootsplash_file.h
-@@ -77,7 +77,17 @@ struct splash_file_header {
- 	uint16_t num_blobs;
- 	uint8_t num_pics;
- 
--	uint8_t padding[103];
-+	uint8_t unused_1;
-+
-+	/*
-+	 * Milliseconds to wait before painting the next frame in
-+	 * an animation.
-+	 * This is actually a minimum, as the system is allowed to
-+	 * stall for longer between frames.
-+	 */
-+	uint16_t frame_ms;
-+
-+	uint8_t padding[100];
- } __attribute__((__packed__));
- 
- 
-@@ -116,7 +126,23 @@ struct splash_pic_header {
- 	 */
- 	uint16_t position_offset;
- 
--	uint8_t padding[24];
-+	/*
-+	 * Animation type.
-+	 *  0 - off
-+	 *  1 - forward loop
-+	 */
-+	uint8_t anim_type;
-+
-+	/*
-+	 * Animation loop point.
-+	 * Actual meaning depends on animation type:
-+	 * Type 0 - Unused
-+	 *      1 - Frame at which to restart the forward loop
-+	 *          (allowing for "intro" frames)
-+	 */
-+	uint8_t anim_loop;
-+
-+	uint8_t padding[22];
- } __attribute__((__packed__));
- 
- 
-@@ -158,4 +184,9 @@ enum splash_position {
- 	SPLASH_POS_FLAG_CORNER = 0x10,
- };
- 
-+enum splash_anim_type {
-+	SPLASH_ANIM_NONE = 0,
-+	SPLASH_ANIM_LOOP_FORWARD = 1,
-+};
-+
- #endif
diff --git a/disabled/RFC-v3-06-13-vt-Redraw-bootsplash-fully-on-console_unblank.patch b/disabled/RFC-v3-06-13-vt-Redraw-bootsplash-fully-on-console_unblank.patch
deleted file mode 100644
index 827e65d..0000000
--- a/disabled/RFC-v3-06-13-vt-Redraw-bootsplash-fully-on-console_unblank.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-diff -up linux-4.19/drivers/tty/vt/vt.c.0105~ linux-4.19/drivers/tty/vt/vt.c
---- linux-4.19/drivers/tty/vt/vt.c.0105~	2018-11-15 02:55:33.904454394 +0100
-+++ linux-4.19/drivers/tty/vt/vt.c	2018-11-15 02:56:30.804027773 +0100
-@@ -104,6 +104,7 @@
- #include <linux/kdb.h>
- #include <linux/ctype.h>
- #include <linux/bsearch.h>
-+#include <linux/bootsplash.h>
- #include <linux/gcd.h>
- 
- #define MAX_NR_CON_DRIVER 16
-@@ -4235,6 +4236,7 @@ void do_unblank_screen(int leaving_gfx)
- 	}
- 
- 	console_blanked = 0;
-+	bootsplash_mark_dirty();
- 	if (vc->vc_sw->con_blank(vc, 0, leaving_gfx))
- 		/* Low-level driver cannot restore -> do it ourselves */
- 		update_screen(vc);
-diff -up linux-4.19/drivers/video/fbdev/core/bootsplash.c.0105~ linux-4.19/drivers/video/fbdev/core/bootsplash.c
---- linux-4.19/drivers/video/fbdev/core/bootsplash.c.0105~	2018-11-15 02:55:33.982455190 +0100
-+++ linux-4.19/drivers/video/fbdev/core/bootsplash.c	2018-11-15 02:55:33.983455200 +0100
-@@ -165,6 +165,13 @@ bool bootsplash_would_render_now(void)
- 		&& bootsplash_is_enabled();
- }
- 
-+void bootsplash_mark_dirty(void)
-+{
-+	mutex_lock(&splash_state.data_lock);
-+	splash_state.splash_fb = NULL;
-+	mutex_unlock(&splash_state.data_lock);
-+}
-+
- bool bootsplash_is_enabled(void)
- {
- 	bool was_enabled;
-@@ -206,9 +213,7 @@ void bootsplash_enable(void)
- 
- 	if (!was_enabled) {
- 		/* Force a full redraw when the splash is re-activated */
--		mutex_lock(&splash_state.data_lock);
--		splash_state.splash_fb = NULL;
--		mutex_unlock(&splash_state.data_lock);
-+		bootsplash_mark_dirty();
- 
- 		schedule_work(&splash_state.work_redraw_vc);
- 	}
-@@ -272,9 +277,7 @@ static int splash_resume(struct device *
- 	 * Force full redraw on resume since we've probably lost the
- 	 * framebuffer's contents meanwhile
- 	 */
--	mutex_lock(&splash_state.data_lock);
--	splash_state.splash_fb = NULL;
--	mutex_unlock(&splash_state.data_lock);
-+	bootsplash_mark_dirty();
- 
- 	if (bootsplash_would_render_now())
- 		schedule_work(&splash_state.work_redraw_vc);
-diff -up linux-4.19/include/linux/bootsplash.h.0105~ linux-4.19/include/linux/bootsplash.h
---- linux-4.19/include/linux/bootsplash.h.0105~	2018-11-15 02:55:33.975455118 +0100
-+++ linux-4.19/include/linux/bootsplash.h	2018-11-15 02:55:33.984455210 +0100
-@@ -19,6 +19,8 @@ extern void bootsplash_render_full(struc
- 
- extern bool bootsplash_would_render_now(void);
- 
-+extern void bootsplash_mark_dirty(void);
-+
- extern bool bootsplash_is_enabled(void);
- extern void bootsplash_disable(void);
- extern void bootsplash_enable(void);
-@@ -31,6 +33,8 @@ extern void bootsplash_init(void);
- 
- #define bootsplash_would_render_now() (false)
- 
-+#define bootsplash_mark_dirty()
-+
- #define bootsplash_is_enabled() (false)
- #define bootsplash_disable()
- #define bootsplash_enable()
diff --git a/disabled/RFC-v3-07-13-vt-Add-keyboard-hook-to-disable-bootsplash.patch b/disabled/RFC-v3-07-13-vt-Add-keyboard-hook-to-disable-bootsplash.patch
deleted file mode 100644
index e8cd479..0000000
--- a/disabled/RFC-v3-07-13-vt-Add-keyboard-hook-to-disable-bootsplash.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-diff --git a/drivers/tty/vt/keyboard.c b/drivers/tty/vt/keyboard.c
-index f4166263bb3a..a248429194bb 100644
---- a/drivers/tty/vt/keyboard.c
-+++ b/drivers/tty/vt/keyboard.c
-@@ -47,6 +47,8 @@
- 
- #include <asm/irq_regs.h>
- 
-+#include <linux/bootsplash.h>
-+
- extern void ctrl_alt_del(void);
- 
- /*
-@@ -1353,6 +1355,28 @@ static void kbd_keycode(unsigned int keycode, int down, int hw_raw)
- 	}
- #endif
- 
-+	/* Trap keys when bootsplash is shown */
-+	if (bootsplash_would_render_now()) {
-+		/* Deactivate bootsplash on ESC or Alt+Fxx VT switch */
-+		if (keycode >= KEY_F1 && keycode <= KEY_F12) {
-+			bootsplash_disable();
-+
-+			/*
-+			 * No return here since we want to actually
-+			 * perform the VT switch.
-+			 */
-+		} else {
-+			if (keycode == KEY_ESC)
-+				bootsplash_disable();
-+
-+			/*
-+			 * Just drop any other keys.
-+			 * Their effect would be hidden by the splash.
-+			 */
-+			return;
-+		}
-+	}
-+
- 	if (kbd->kbdmode == VC_MEDIUMRAW) {
- 		/*
- 		 * This is extended medium raw mode, with keys above 127
diff --git a/disabled/RFC-v3-08-13-sysrq-Disable-bootsplash-on-SAK.patch b/disabled/RFC-v3-08-13-sysrq-Disable-bootsplash-on-SAK.patch
deleted file mode 100644
index 8a3b715..0000000
--- a/disabled/RFC-v3-08-13-sysrq-Disable-bootsplash-on-SAK.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c
-index 3ffc1ce29023..bc6a24c9dfa8 100644
---- a/drivers/tty/sysrq.c
-+++ b/drivers/tty/sysrq.c
-@@ -49,6 +49,7 @@
- #include <linux/syscalls.h>
- #include <linux/of.h>
- #include <linux/rcupdate.h>
-+#include <linux/bootsplash.h>
- 
- #include <asm/ptrace.h>
- #include <asm/irq_regs.h>
-@@ -104,6 +105,8 @@ static void sysrq_handle_SAK(int key)
- {
- 	struct work_struct *SAK_work = &vc_cons[fg_console].SAK_work;
- 	schedule_work(SAK_work);
-+
-+	bootsplash_disable();
- }
- static struct sysrq_key_op sysrq_SAK_op = {
- 	.handler	= sysrq_handle_SAK,
diff --git a/disabled/RFC-v3-09-13-fbcon-Disable-bootsplash-on-oops.patch b/disabled/RFC-v3-09-13-fbcon-Disable-bootsplash-on-oops.patch
deleted file mode 100644
index add68e7..0000000
--- a/disabled/RFC-v3-09-13-fbcon-Disable-bootsplash-on-oops.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
-index 9a39a6fcfe98..8a9c67e1c5d8 100644
---- a/drivers/video/fbdev/core/fbcon.c
-+++ b/drivers/video/fbdev/core/fbcon.c
-@@ -1343,6 +1343,16 @@ static void fbcon_cursor(struct vc_data *vc, int mode)
- 	int y;
-  	int c = scr_readw((u16 *) vc->vc_pos);
- 
-+	/*
-+	 * Disable the splash here so we don't have to hook into
-+	 * vt_console_print() in drivers/tty/vt/vt.c
-+	 *
-+	 * We'd disable the splash just before the call to
-+	 * hide_cursor() anyway, so this spot is just fine.
-+	 */
-+	if (oops_in_progress)
-+		bootsplash_disable();
-+
- 	ops->cur_blink_jiffies = msecs_to_jiffies(vc->vc_cur_blink_ms);
- 
- 	if (fbcon_is_inactive(vc, info) || vc->vc_deccm != 1)
diff --git a/disabled/RFC-v3-10-13-Documentation-Add-bootsplash-main-documentation.patch b/disabled/RFC-v3-10-13-Documentation-Add-bootsplash-main-documentation.patch
deleted file mode 100644
index e5c1fd0..0000000
--- a/disabled/RFC-v3-10-13-Documentation-Add-bootsplash-main-documentation.patch
+++ /dev/null
@@ -1,321 +0,0 @@
-diff --git a/Documentation/ABI/testing/sysfs-platform-bootsplash b/Documentation/ABI/testing/sysfs-platform-bootsplash
-new file mode 100644
-index 000000000000..742c7b035ded
---- /dev/null
-+++ b/Documentation/ABI/testing/sysfs-platform-bootsplash
-@@ -0,0 +1,11 @@
-+What:		/sys/devices/platform/bootsplash.0/enabled
-+Date:		Oct 2017
-+KernelVersion:	4.14
-+Contact:	Max Staudt <mstaudt@suse.de>
-+Description:
-+		Can be set and read.
-+
-+		0: Splash is disabled.
-+		1: Splash is shown whenever fbcon would show a text console
-+		   (i.e. no graphical application is running), and a splash
-+		   file is loaded.
-diff --git a/Documentation/bootsplash.rst b/Documentation/bootsplash.rst
-new file mode 100644
-index 000000000000..611f0c558925
---- /dev/null
-+++ b/Documentation/bootsplash.rst
-@@ -0,0 +1,285 @@
-+====================
-+The Linux bootsplash
-+====================
-+
-+:Date: November, 2017
-+:Author: Max Staudt <mstaudt@suse.de>
-+
-+
-+The Linux bootsplash is a graphical replacement for the '``quiet``' boot
-+option, typically showing a logo and a spinner animation as the system starts.
-+
-+Currently, it is a part of the Framebuffer Console support, and can be found
-+as ``CONFIG_BOOTSPLASH`` in the kernel configuration. This means that as long
-+as it is enabled, it hijacks fbcon's output and draws a splash screen instead.
-+
-+Purely compiling in the bootsplash will not render it functional - to actually
-+render a splash, you will also need a splash theme file. See the example
-+utility and script in ``tools/bootsplash`` for a live demo.
-+
-+
-+
-+Motivation
-+==========
-+
-+- The '``quiet``' boot option only suppresses most messages during boot, but
-+  errors are still shown.
-+
-+- A user space implementation can only show a logo once user space has been
-+  initialized far enough to allow this. A kernel splash can display a splash
-+  immediately as soon as fbcon can be displayed.
-+
-+- Implementing a splash screen in user space (e.g. Plymouth) is problematic
-+  due to resource conflicts.
-+
-+  For example, if Plymouth is keeping ``/dev/fb0`` (provided via vesafb/efifb)
-+  open, then most DRM drivers can't replace it because the address space is
-+  still busy - thus leading to a VRAM reservation error.
-+
-+  See: https://bugzilla.opensuse.org/show_bug.cgi?id=980750
-+
-+
-+
-+Command line arguments
-+======================
-+
-+``bootsplash.bootfile``
-+  Which file in the initramfs to load.
-+
-+  The splash theme is loaded via request_firmware(), thus to load
-+  ``/lib/firmware/bootsplash/mytheme`` pass the command line:
-+
-+  ``bootsplash.bootfile=bootsplash/mytheme``
-+
-+  Note: The splash file *has to be* in the initramfs, as it needs to be
-+  available when the splash is initialized early on.
-+
-+  Default: none, i.e. a non-functional splash, falling back to showing text.
-+
-+
-+
-+sysfs run-time configuration
-+============================
-+
-+``/sys/devices/platform/bootsplash.0/enabled``
-+  Enable/disable the bootsplash.
-+  The system boots with this set to 1, but will not show a splash unless
-+  a splash theme file is also loaded.
-+
-+
-+
-+Kconfig
-+=======
-+
-+``BOOTSPLASH``
-+  Whether to compile in bootsplash support
-+  (depends on fbcon compiled in, i.e. ``FRAMEBUFFER_CONSOLE=y``)
-+
-+
-+
-+Bootsplash file format
-+======================
-+
-+A file specified in the kernel configuration as ``CONFIG_BOOTSPLASH_FILE``
-+or specified on the command line as ``bootsplash.bootfile`` will be loaded
-+and displayed as soon as fbcon is initialized.
-+
-+
-+Main blocks
-+-----------
-+
-+There are 3 main blocks in each file:
-+
-+  - one File header
-+  -   n Picture headers
-+  -   m (Blob header + payload) blocks
-+
-+
-+Structures
-+----------
-+
-+The on-disk structures are defined in
-+``drivers/video/fbdev/core/bootsplash_file.h`` and represent these blocks:
-+
-+  - ``struct splash_file_header``
-+
-+    Represents the file header, with splash-wide information including:
-+
-+      - The magic string "``Linux bootsplash``" on big-endian platforms
-+        (the reverse on little endian)
-+      - The file format version (for incompatible updates, hopefully never)
-+      - The background color
-+      - Number of picture and blob blocks
-+      - Animation speed (we only allow one delay for all animations)
-+
-+    The file header is followed by the first picture header.
-+
-+
-+  - ``struct splash_picture_header``
-+
-+    Represents an object (picture) drawn on screen, including its immutable
-+    properties:
-+      - Width, height
-+      - Positioning relative to screen corners or in the center
-+      - Animation, if any
-+      - Animation type
-+      - Number of blobs
-+
-+    The picture header is followed by another picture header, up until n
-+    picture headers (as defined in the file header) have been read. Then,
-+    the (blob header, payload) pairs follow.
-+
-+
-+  - ``struct splash_blob_header``
-+    (followed by payload)
-+
-+    Represents one raw data stream. So far, only picture data is defined.
-+
-+    The blob header is followed by a payload, then padding to n*16 bytes,
-+    then (if further blobs are defined in the file header) a further blob
-+    header.
-+
-+
-+Alignment
-+---------
-+
-+The bootsplash file is designed to be loaded into memory as-is.
-+
-+All structures are a multiple of 16 bytes long, all elements therein are
-+aligned to multiples of their length, and the payloads are always padded
-+up to multiples of 16 bytes. This is to allow aligned accesses in all
-+cases while still simply mapping the structures over an in-memory copy of
-+the bootsplash file.
-+
-+
-+Further information
-+-------------------
-+
-+Please see ``drivers/video/fbdev/core/bootsplash_file.h`` for further
-+details and possible values in the file.
-+
-+
-+
-+Hooks - how the bootsplash is integrated
-+========================================
-+
-+``drivers/video/fbdev/core/fbcon.c``
-+  ``fbcon_init()`` calls ``bootsplash_init()``, which loads the default
-+  bootsplash file or the one specified on the kernel command line.
-+
-+  ``fbcon_switch()`` draws the bootsplash when it's active, and is also
-+  one of the callers of ``set_blitting_type()``.
-+
-+  ``set_blitting_type()`` calls ``fbcon_set_dummyops()`` when the
-+  bootsplash is active, overriding the text rendering functions.
-+
-+  ``fbcon_cursor()`` will call ``bootsplash_disable()`` when an oops is
-+  being printed in order to make a kernel panic visible.
-+
-+``drivers/video/fbdev/core/dummyblit.c``
-+  This contains the dummy text rendering functions used to suppress text
-+  output while the bootsplash is shown.
-+
-+``drivers/tty/vt/keyboard.c``
-+  ``kbd_keycode()`` can call ``bootsplash_disable()`` when the user
-+  presses ESC or F1-F12 (changing VT). This is to provide a built-in way
-+  of disabling the splash manually at any time.
-+
-+
-+
-+FAQ: Frequently Asked Questions
-+===============================
-+
-+I want to see the log! How do I show the log?
-+---------------------------------------------
-+
-+Press ESC while the splash is shown, or remove the ``bootsplash.bootfile``
-+parameter from the kernel cmdline. Without that parameter, the bootsplash
-+will boot disabled.
-+
-+
-+Why use FB instead of modern DRM/KMS?
-+-------------------------------------
-+
-+This is a semantic problem:
-+ - What memory to draw the splash to?
-+ - And what mode will the screen be set to?
-+
-+Using the fbdev emulation solves these issues.
-+
-+Let's start from a bare KMS system, without fbcon, and without fbdev
-+emulation. In this case, as long as userspace doesn't open the KMS
-+device, the state of the screen is undefined. No framebuffer is
-+allocated in video RAM, and no particular mode is set.
-+
-+In this case, we'd have to allocate a framebuffer to show the splash,
-+and set our mode ourselves. This either wastes a screenful of video RAM
-+if the splash is to co-exist with the userspace program's own allocated
-+framebuffer, or there is a flicker as we deactivate and delete the
-+bootsplash's framebuffer and hand control over to userspace. Since we
-+may set a different mode than userspace, we'd also have flicker due
-+to mode switching.
-+
-+This logic is already contained in every KMS driver that performs fbdev
-+emulation. So we might as well use that. And the correct API to do so is
-+fbdev. Plus, we get compatibility with old, pure fbdev drivers for free.
-+With the fbdev emulation, there is *always* a well-defined framebuffer
-+to draw on. And the selection of mode has already been done by the
-+graphics driver, so we don't need to reinvent that wheel, either.
-+Finally, if userspace decides to use /dev/fbX, we don't have to worry
-+about wasting video RAM, either.
-+
-+
-+Why is the bootsplash integrated in fbcon?
-+------------------------------------------
-+
-+Right now, the bootsplash is drawn from within fbcon, as this allows us
-+to easily know *when* to draw - i.e. when we're safe from fbcon and
-+userspace drawing all over our beautiful splash logo.
-+
-+Separating them is not easy - see the to-do list below.
-+
-+
-+
-+TO DO list for future development
-+=================================
-+
-+Second enable/disable switch for the system
-+-------------------------------------------
-+
-+It may be helpful to differentiate between the system and the user
-+switching off the bootsplash. Thus, the system may make it disappear and
-+reappear e.g. for a password prompt, yet once the user has pressed ESC,
-+it could stay gone.
-+
-+
-+Fix buggy DRM/KMS drivers
-+-------------------------
-+
-+Currently, the splash code manually checks for fbdev emulation provided by
-+the ast, cirrus, and mgag200 DRM/KMS drivers.
-+These drivers use a manual mechanism similar to deferred I/O for their FB
-+emulation, and thus need to be manually flushed onto the screen in the same
-+way.
-+
-+This may be improved upon in several ways:
-+
-+1. Changing these drivers to expose the fbdev BO's memory directly, like
-+   bochsdrmfb does.
-+2. Creating a new fb_ops->fb_flush() API to allow the kernel to flush the
-+   framebuffer once the bootsplash has been drawn into it.
-+
-+
-+Separating from fbcon
-+---------------------
-+
-+Separating these two components would yield independence from fbcon being
-+compiled into the kernel, and thus lowering code size in embedded
-+applications.
-+
-+To do this cleanly will involve a clean separation of users of an FB device
-+within the kernel, i.e. fbcon, bootsplash, and userspace. Right now, the
-+legacy fbcon code and VT code co-operate to switch between fbcon and
-+userspace (by setting the VT into KD_GRAPHICS mode). Installing a muxer
-+between these components ensues refactoring of old code and checking for
-+correct locking.
-diff --git a/MAINTAINERS b/MAINTAINERS
-index 5c237445761e..7ffac272434e 100644
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -2709,6 +2709,8 @@ BOOTSPLASH
- M:	Max Staudt <mstaudt@suse.de>
- L:	linux-fbdev@vger.kernel.org
- S:	Maintained
-+F:	Documentation/ABI/testing/sysfs-platform-bootsplash
-+F:	Documentation/bootsplash.rst
- F:	drivers/video/fbdev/core/bootsplash*.*
- F:	drivers/video/fbdev/core/dummycon.c
- F:	include/linux/bootsplash.h
diff --git a/disabled/RFC-v3-11-13-bootsplash-sysfs-entries-to-load-and-unload-files.patch b/disabled/RFC-v3-11-13-bootsplash-sysfs-entries-to-load-and-unload-files.patch
deleted file mode 100644
index 8e87eb4..0000000
--- a/disabled/RFC-v3-11-13-bootsplash-sysfs-entries-to-load-and-unload-files.patch
+++ /dev/null
@@ -1,129 +0,0 @@
-diff --git a/Documentation/ABI/testing/sysfs-platform-bootsplash b/Documentation/ABI/testing/sysfs-platform-bootsplash
-index 742c7b035ded..f8f4b259220e 100644
---- a/Documentation/ABI/testing/sysfs-platform-bootsplash
-+++ b/Documentation/ABI/testing/sysfs-platform-bootsplash
-@@ -9,3 +9,35 @@ Description:
- 		1: Splash is shown whenever fbcon would show a text console
- 		   (i.e. no graphical application is running), and a splash
- 		   file is loaded.
-+
-+What:		/sys/devices/platform/bootsplash.0/drop_splash
-+Date:		Oct 2017
-+KernelVersion:	4.14
-+Contact:	Max Staudt <mstaudt@suse.de>
-+Description:
-+		Can only be set.
-+
-+		Any value written will cause the current splash theme file
-+		to be unloaded and the text console to be redrawn.
-+
-+What:		/sys/devices/platform/bootsplash.0/load_file
-+Date:		Oct 2017
-+KernelVersion:	4.14
-+Contact:	Max Staudt <mstaudt@suse.de>
-+Description:
-+		Can only be set.
-+
-+		Any value written will cause the splash to be disabled and
-+		internal memory structures to be freed.
-+
-+		A firmware path written will cause a new theme file to be
-+		loaded and the current bootsplash to be replaced.
-+		The current enabled/disabled status is not touched.
-+		If the splash is already active, it will be redrawn.
-+
-+		The path has to be a path in /lib/firmware since
-+		request_firmware() is used to fetch the data.
-+
-+		When setting the splash from the shell, echo -n has to be
-+		used as any trailing '\n' newline will be interpreted as
-+		part of the path.
-diff --git a/Documentation/bootsplash.rst b/Documentation/bootsplash.rst
-index 611f0c558925..b35aba5093e8 100644
---- a/Documentation/bootsplash.rst
-+++ b/Documentation/bootsplash.rst
-@@ -67,6 +67,14 @@ sysfs run-time configuration
-   a splash theme file is also loaded.
- 
- 
-+``/sys/devices/platform/bootsplash.0/drop_splash``
-+  Unload splash data and free memory.
-+
-+``/sys/devices/platform/bootsplash.0/load_file``
-+  Load a splash file from ``/lib/firmware/``.
-+  Note that trailing newlines will be interpreted as part of the file name.
-+
-+
- 
- Kconfig
- =======
-diff --git a/drivers/video/fbdev/core/bootsplash.c b/drivers/video/fbdev/core/bootsplash.c
-index 13fcaabbc2ca..16cb0493629d 100644
---- a/drivers/video/fbdev/core/bootsplash.c
-+++ b/drivers/video/fbdev/core/bootsplash.c
-@@ -251,11 +251,65 @@ static ssize_t splash_store_enabled(struct device *device,
- 	return count;
- }
- 
-+static ssize_t splash_store_drop_splash(struct device *device,
-+					struct device_attribute *attr,
-+					const char *buf, size_t count)
-+{
-+	struct splash_file_priv *fp;
-+
-+	if (!buf || !count || !splash_state.file)
-+		return count;
-+
-+	mutex_lock(&splash_state.data_lock);
-+	fp = splash_state.file;
-+	splash_state.file = NULL;
-+	mutex_unlock(&splash_state.data_lock);
-+
-+	/* Redraw the text console */
-+	schedule_work(&splash_state.work_redraw_vc);
-+
-+	bootsplash_free_file(fp);
-+
-+	return count;
-+}
-+
-+static ssize_t splash_store_load_file(struct device *device,
-+				      struct device_attribute *attr,
-+				      const char *buf, size_t count)
-+{
-+	struct splash_file_priv *fp, *fp_old;
-+
-+	if (!count)
-+		return 0;
-+
-+	fp = bootsplash_load_firmware(&splash_state.splash_device->dev,
-+				      buf);
-+
-+	if (!fp)
-+		return -ENXIO;
-+
-+	mutex_lock(&splash_state.data_lock);
-+	fp_old = splash_state.file;
-+	splash_state.splash_fb = NULL;
-+	splash_state.file = fp;
-+	mutex_unlock(&splash_state.data_lock);
-+
-+	/* Update the splash or text console */
-+	schedule_work(&splash_state.work_redraw_vc);
-+
-+	bootsplash_free_file(fp_old);
-+	return count;
-+}
-+
- static DEVICE_ATTR(enabled, 0644, splash_show_enabled, splash_store_enabled);
-+static DEVICE_ATTR(drop_splash, 0200, NULL, splash_store_drop_splash);
-+static DEVICE_ATTR(load_file, 0200, NULL, splash_store_load_file);
- 
- 
- static struct attribute *splash_dev_attrs[] = {
- 	&dev_attr_enabled.attr,
-+	&dev_attr_drop_splash.attr,
-+	&dev_attr_load_file.attr,
- 	NULL
- };
- 
diff --git a/disabled/RFC-v3-12-13-tools-bootsplash-Add-a-basic-splash-file-creation-tool.patch b/disabled/RFC-v3-12-13-tools-bootsplash-Add-a-basic-splash-file-creation-tool.patch
deleted file mode 100644
index 69bde2e..0000000
--- a/disabled/RFC-v3-12-13-tools-bootsplash-Add-a-basic-splash-file-creation-tool.patch
+++ /dev/null
@@ -1,511 +0,0 @@
-diff --git a/MAINTAINERS b/MAINTAINERS
-index 7ffac272434e..ddff07cd794c 100644
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -2715,6 +2715,7 @@ F:	drivers/video/fbdev/core/bootsplash*.*
- F:	drivers/video/fbdev/core/dummycon.c
- F:	include/linux/bootsplash.h
- F:	include/uapi/linux/bootsplash_file.h
-+F:	tools/bootsplash/*
- 
- BPF (Safe dynamic programs and tools)
- M:	Alexei Starovoitov <ast@kernel.org>
-diff --git a/tools/bootsplash/.gitignore b/tools/bootsplash/.gitignore
-new file mode 100644
-index 000000000000..091b99a17567
---- /dev/null
-+++ b/tools/bootsplash/.gitignore
-@@ -0,0 +1 @@
-+bootsplash-packer
-diff --git a/tools/bootsplash/Makefile b/tools/bootsplash/Makefile
-new file mode 100644
-index 000000000000..0ad8e8a84942
---- /dev/null
-+++ b/tools/bootsplash/Makefile
-@@ -0,0 +1,9 @@
-+CC := $(CROSS_COMPILE)gcc
-+CFLAGS := -I../../include/uapi -I../../include -I../../usr/include
-+
-+PROGS := bootsplash-packer
-+
-+all: $(PROGS)
-+
-+clean:
-+	rm -fr $(PROGS)
-diff --git a/tools/bootsplash/bootsplash-packer.c b/tools/bootsplash/bootsplash-packer.c
-new file mode 100644
-index 000000000000..ffb6a8b69885
---- /dev/null
-+++ b/tools/bootsplash/bootsplash-packer.c
-@@ -0,0 +1,471 @@
-+/*
-+ * Kernel based bootsplash.
-+ *
-+ * (Splash file packer tool)
-+ *
-+ * Authors:
-+ * Max Staudt <mstaudt@suse.de>
-+ *
-+ * SPDX-License-Identifier: GPL-2.0
-+ */
-+
-+#include <endian.h>
-+#include <getopt.h>
-+#include <stdint.h>
-+#include <stdio.h>
-+#include <stdlib.h>
-+#include <string.h>
-+
-+#include <linux/bootsplash_file.h>
-+
-+
-+static void print_help(char *progname)
-+{
-+	printf("Usage: %s [OPTIONS] outfile\n", progname);
-+	printf("\n"
-+	       "Options, executed in order given:\n"
-+	       "  -h, --help                   Print this help message\n"
-+	       "\n"
-+	       "  --bg_red <u8>                Background color (red part)\n"
-+	       "  --bg_green <u8>              Background color (green part)\n"
-+	       "  --bg_blue <u8>               Background color (blue part)\n"
-+	       "  --bg_reserved <u8>           (do not use)\n"
-+	       "  --frame_ms <u16>             Minimum milliseconds between animation steps\n"
-+	       "\n"
-+	       "  --picture                    Start describing the next picture\n"
-+	       "  --pic_width <u16>            Picture width in pixels\n"
-+	       "  --pic_height <u16>           Picture height in pixels\n"
-+	       "  --pic_position <u8>             Coarse picture placement:\n"
-+	       "                                  0x00 - Top left\n"
-+	       "                                  0x01 - Top\n"
-+	       "                                  0x02 - Top right\n"
-+	       "                                  0x03 - Right\n"
-+	       "                                  0x04 - Bottom right\n"
-+	       "                                  0x05 - Bottom\n"
-+	       "                                  0x06 - Bottom left\n"
-+	       "                                  0x07 - Left\n"
-+	       "\n"
-+	       "                                Flags:\n"
-+	       "                                 0x10 - Calculate offset from corner towards center,\n"
-+	       "                                         rather than from center towards corner\n"
-+	       "  --pic_position_offset <u16>  Distance from base position in pixels\n"
-+	       "  --pic_anim_type <u8>         Animation type:\n"
-+	       "                                 0 - None\n"
-+	       "                                 1 - Forward loop\n"
-+	       "  --pic_anim_loop <u8>         Loop point for animation\n"
-+	       "\n"
-+	       "  --blob <filename>            Include next data stream\n"
-+	       "  --blob_type <u16>            Type of data\n"
-+	       "  --blob_picture_id <u8>       Picture to associate this blob with, starting at 0\n"
-+	       "                                 (default: number of last --picture)\n"
-+	       "\n");
-+	printf("This tool will write %s files.\n\n",
-+#if __BYTE_ORDER == __BIG_ENDIAN
-+	       "Big Endian (BE)");
-+#elif __BYTE_ORDER == __LITTLE_ENDIAN
-+	       "Little Endian (LE)");
-+#else
-+#error
-+#endif
-+}
-+
-+
-+struct blob_entry {
-+	struct blob_entry *next;
-+
-+	char *fn;
-+
-+	struct splash_blob_header header;
-+};
-+
-+
-+static void dump_file_header(struct splash_file_header *h)
-+{
-+	printf(" --- File header ---\n");
-+	printf("\n");
-+	printf("  version:     %5u\n", h->version);
-+	printf("\n");
-+	printf("  bg_red:      %5u\n", h->bg_red);
-+	printf("  bg_green:    %5u\n", h->bg_green);
-+	printf("  bg_blue:     %5u\n", h->bg_blue);
-+	printf("  bg_reserved: %5u\n", h->bg_reserved);
-+	printf("\n");
-+	printf("  num_blobs:   %5u\n", h->num_blobs);
-+	printf("  num_pics:    %5u\n", h->num_pics);
-+	printf("\n");
-+	printf("  frame_ms:    %5u\n", h->frame_ms);
-+	printf("\n");
-+}
-+
-+static void dump_pic_header(struct splash_pic_header *ph)
-+{
-+	printf(" --- Picture header ---\n");
-+	printf("\n");
-+	printf("  width:           %5u\n", ph->width);
-+	printf("  height:          %5u\n", ph->height);
-+	printf("\n");
-+	printf("  num_blobs:       %5u\n", ph->num_blobs);
-+	printf("\n");
-+	printf("  position:        %0x3x\n", ph->position);
-+	printf("  position_offset: %5u\n", ph->position_offset);
-+	printf("\n");
-+	printf("  anim_type:       %5u\n", ph->anim_type);
-+	printf("  anim_loop:       %5u\n", ph->anim_loop);
-+	printf("\n");
-+}
-+
-+static void dump_blob(struct blob_entry *b)
-+{
-+	printf(" --- Blob header ---\n");
-+	printf("\n");
-+	printf("  length:     %7u\n", b->header.length);
-+	printf("  type:       %7u\n", b->header.type);
-+	printf("\n");
-+	printf("  picture_id: %7u\n", b->header.picture_id);
-+	printf("\n");
-+}
-+
-+
-+#define OPT_MAX(var, max) \
-+	do { \
-+		if ((var) > max) { \
-+			fprintf(stderr, "--%s: Invalid value\n", \
-+			long_options[option_index].name); \
-+			break; \
-+		} \
-+	} while (0)
-+
-+static struct option long_options[] = {
-+	{"help", 0, 0, 'h'},
-+	{"bg_red", 1, 0, 10001},
-+	{"bg_green", 1, 0, 10002},
-+	{"bg_blue", 1, 0, 10003},
-+	{"bg_reserved", 1, 0, 10004},
-+	{"frame_ms", 1, 0, 10005},
-+	{"picture", 0, 0, 20000},
-+	{"pic_width", 1, 0, 20001},
-+	{"pic_height", 1, 0, 20002},
-+	{"pic_position", 1, 0, 20003},
-+	{"pic_position_offset", 1, 0, 20004},
-+	{"pic_anim_type", 1, 0, 20005},
-+	{"pic_anim_loop", 1, 0, 20006},
-+	{"blob", 1, 0, 30000},
-+	{"blob_type", 1, 0, 30001},
-+	{"blob_picture_id", 1, 0, 30002},
-+	{NULL, 0, NULL, 0}
-+};
-+
-+
-+int main(int argc, char **argv)
-+{
-+	FILE *of;
-+	char *ofn;
-+	int c;
-+	int option_index = 0;
-+
-+	unsigned long ul;
-+	struct splash_file_header fh = {};
-+	struct splash_pic_header ph[255];
-+	struct blob_entry *blob_first = NULL;
-+	struct blob_entry *blob_last = NULL;
-+	struct blob_entry *blob_cur = NULL;
-+
-+	if (argc < 2) {
-+		print_help(argv[0]);
-+		return EXIT_FAILURE;
-+	}
-+
-+
-+	/* Parse and and execute user commands */
-+	while ((c = getopt_long(argc, argv, "h",
-+			  long_options, &option_index)) != -1) {
-+		switch (c) {
-+		case 10001:	/* bg_red */
-+			ul = strtoul(optarg, NULL, 0);
-+			OPT_MAX(ul, 255);
-+			fh.bg_red = ul;
-+			break;
-+		case 10002:	/* bg_green */
-+			ul = strtoul(optarg, NULL, 0);
-+			OPT_MAX(ul, 255);
-+			fh.bg_green = ul;
-+			break;
-+		case 10003:	/* bg_blue */
-+			ul = strtoul(optarg, NULL, 0);
-+			OPT_MAX(ul, 255);
-+			fh.bg_blue = ul;
-+			break;
-+		case 10004:	/* bg_reserved */
-+			ul = strtoul(optarg, NULL, 0);
-+			OPT_MAX(ul, 255);
-+			fh.bg_reserved = ul;
-+			break;
-+		case 10005:	/* frame_ms */
-+			ul = strtoul(optarg, NULL, 0);
-+			OPT_MAX(ul, 65535);
-+			fh.frame_ms = ul;
-+			break;
-+
-+
-+		case 20000:	/* picture */
-+			if (fh.num_pics >= 255) {
-+				fprintf(stderr, "--%s: Picture array full\n",
-+					long_options[option_index].name);
-+				break;
-+			}
-+
-+			fh.num_pics++;
-+			break;
-+
-+		case 20001:	/* pic_width */
-+			ul = strtoul(optarg, NULL, 0);
-+			OPT_MAX(ul, 65535);
-+			ph[fh.num_pics - 1].width = ul;
-+			break;
-+
-+		case 20002:	/* pic_height */
-+			ul = strtoul(optarg, NULL, 0);
-+			OPT_MAX(ul, 65535);
-+			ph[fh.num_pics - 1].height = ul;
-+			break;
-+
-+		case 20003:	/* pic_position */
-+			ul = strtoul(optarg, NULL, 0);
-+			OPT_MAX(ul, 255);
-+			ph[fh.num_pics - 1].position = ul;
-+			break;
-+
-+		case 20004:	/* pic_position_offset */
-+			ul = strtoul(optarg, NULL, 0);
-+			OPT_MAX(ul, 255);
-+			ph[fh.num_pics - 1].position_offset = ul;
-+			break;
-+
-+		case 20005:	/* pic_anim_type */
-+			ul = strtoul(optarg, NULL, 0);
-+			OPT_MAX(ul, 255);
-+			ph[fh.num_pics - 1].anim_type = ul;
-+			break;
-+
-+		case 20006:	/* pic_anim_loop */
-+			ul = strtoul(optarg, NULL, 0);
-+			OPT_MAX(ul, 255);
-+			ph[fh.num_pics - 1].anim_loop = ul;
-+			break;
-+
-+
-+		case 30000:	/* blob */
-+			if (fh.num_blobs >= 65535) {
-+				fprintf(stderr, "--%s: Blob array full\n",
-+					long_options[option_index].name);
-+				break;
-+			}
-+
-+			blob_cur = calloc(1, sizeof(struct blob_entry));
-+			if (!blob_cur) {
-+				fprintf(stderr, "--%s: Out of memory\n",
-+					long_options[option_index].name);
-+				break;
-+			}
-+
-+			blob_cur->fn = optarg;
-+			if (fh.num_pics)
-+				blob_cur->header.picture_id = fh.num_pics - 1;
-+
-+			if (!blob_first)
-+				blob_first = blob_cur;
-+			if (blob_last)
-+				blob_last->next = blob_cur;
-+			blob_last = blob_cur;
-+			fh.num_blobs++;
-+			break;
-+
-+		case 30001:	/* blob_type */
-+			if (!blob_cur) {
-+				fprintf(stderr, "--%s: No blob selected\n",
-+					long_options[option_index].name);
-+				break;
-+			}
-+
-+			ul = strtoul(optarg, NULL, 0);
-+			OPT_MAX(ul, 255);
-+			blob_cur->header.type = ul;
-+			break;
-+
-+		case 30002:	/* blob_picture_id */
-+			if (!blob_cur) {
-+				fprintf(stderr, "--%s: No blob selected\n",
-+					long_options[option_index].name);
-+				break;
-+			}
-+
-+			ul = strtoul(optarg, NULL, 0);
-+			OPT_MAX(ul, 255);
-+			blob_cur->header.picture_id = ul;
-+			break;
-+
-+
-+
-+		case 'h':
-+		case '?':
-+		default:
-+			print_help(argv[0]);
-+			goto EXIT;
-+		} /* switch (c) */
-+	} /* while ((c = getopt_long(...)) != -1) */
-+
-+	/* Consume and drop lone arguments */
-+	while (optind < argc) {
-+		ofn = argv[optind];
-+		optind++;
-+	}
-+
-+
-+	/* Read file lengths */
-+	for (blob_cur = blob_first; blob_cur; blob_cur = blob_cur->next) {
-+		FILE *f;
-+		long pos;
-+		int i;
-+
-+		if (!blob_cur->fn)
-+			continue;
-+
-+		f = fopen(blob_cur->fn, "rb");
-+		if (!f)
-+			goto ERR_FILE_LEN;
-+
-+		if (fseek(f, 0, SEEK_END))
-+			goto ERR_FILE_LEN;
-+
-+		pos = ftell(f);
-+		if (pos < 0 || pos > (1 << 30))
-+			goto ERR_FILE_LEN;
-+
-+		blob_cur->header.length = pos;
-+
-+		fclose(f);
-+		continue;
-+
-+ERR_FILE_LEN:
-+		fprintf(stderr, "Error getting file length (or too long): %s\n",
-+			blob_cur->fn);
-+		if (f)
-+			fclose(f);
-+		continue;
-+	}
-+
-+
-+	/* Set magic headers */
-+#if __BYTE_ORDER == __BIG_ENDIAN
-+	memcpy(&fh.id[0], BOOTSPLASH_MAGIC_BE, 16);
-+#elif __BYTE_ORDER == __LITTLE_ENDIAN
-+	memcpy(&fh.id[0], BOOTSPLASH_MAGIC_LE, 16);
-+#else
-+#error
-+#endif
-+	fh.version = BOOTSPLASH_VERSION;
-+
-+	/* Set blob counts */
-+	for (blob_cur = blob_first; blob_cur; blob_cur = blob_cur->next) {
-+		if (blob_cur->header.picture_id < fh.num_pics)
-+			ph[blob_cur->header.picture_id].num_blobs++;
-+	}
-+
-+
-+	/* Dump structs */
-+	dump_file_header(&fh);
-+
-+	for (ul = 0; ul < fh.num_pics; ul++)
-+		dump_pic_header(&ph[ul]);
-+
-+	for (blob_cur = blob_first; blob_cur; blob_cur = blob_cur->next)
-+		dump_blob(blob_cur);
-+
-+
-+	/* Write to file */
-+	printf("Writing splash to file: %s\n", ofn);
-+	of = fopen(ofn, "wb");
-+	if (!of)
-+		goto ERR_WRITING;
-+
-+	if (fwrite(&fh, sizeof(struct splash_file_header), 1, of) != 1)
-+		goto ERR_WRITING;
-+
-+	for (ul = 0; ul < fh.num_pics; ul++) {
-+		if (fwrite(&ph[ul], sizeof(struct splash_pic_header), 1, of)
-+		    != 1)
-+			goto ERR_WRITING;
-+	}
-+
-+	blob_cur = blob_first;
-+	while (blob_cur) {
-+		struct blob_entry *blob_old = blob_cur;
-+		FILE *f;
-+		char *buf[256];
-+		uint32_t left;
-+
-+		if (fwrite(&blob_cur->header,
-+			   sizeof(struct splash_blob_header), 1, of) != 1)
-+			goto ERR_WRITING;
-+
-+		if (!blob_cur->header.length || !blob_cur->fn)
-+			continue;
-+
-+		f = fopen(blob_cur->fn, "rb");
-+		if (!f)
-+			goto ERR_FILE_COPY;
-+
-+		left = blob_cur->header.length;
-+		while (left >= sizeof(buf)) {
-+			if (fread(buf, sizeof(buf), 1, f) != 1)
-+				goto ERR_FILE_COPY;
-+			if (fwrite(buf, sizeof(buf), 1, of) != 1)
-+				goto ERR_FILE_COPY;
-+			left -= sizeof(buf);
-+		}
-+		if (left) {
-+			if (fread(buf, left, 1, f) != 1)
-+				goto ERR_FILE_COPY;
-+			if (fwrite(buf, left, 1, of) != 1)
-+				goto ERR_FILE_COPY;
-+		}
-+
-+		/* Pad data stream to 16 bytes */
-+		if (left % 16) {
-+			if (fwrite("\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0",
-+					16 - (left % 16), 1, of) != 1)
-+				goto ERR_FILE_COPY;
-+		}
-+
-+		fclose(f);
-+		blob_cur = blob_cur->next;
-+		free(blob_old);
-+		continue;
-+
-+ERR_FILE_COPY:
-+		if (f)
-+			fclose(f);
-+		goto ERR_WRITING;
-+	}
-+
-+	fclose(of);
-+
-+EXIT:
-+	return EXIT_SUCCESS;
-+
-+
-+ERR_WRITING:
-+	fprintf(stderr, "Error writing splash.\n");
-+	fprintf(stderr, "The output file is probably corrupt.\n");
-+	if (of)
-+		fclose(of);
-+
-+	while (blob_cur) {
-+		struct blob_entry *blob_old = blob_cur;
-+
-+		blob_cur = blob_cur->next;
-+		free(blob_old);
-+	}
-+
-+	return EXIT_FAILURE;
-+}
diff --git a/disabled/RFC-v3-13-13-tools-bootsplash-Add-script-and-data-to-create-sample-file.patch b/disabled/RFC-v3-13-13-tools-bootsplash-Add-script-and-data-to-create-sample-file.patch
deleted file mode 100644
index 124ad07..0000000
--- a/disabled/RFC-v3-13-13-tools-bootsplash-Add-script-and-data-to-create-sample-file.patch
+++ /dev/null
@@ -1,162 +0,0 @@
-diff --git a/Documentation/bootsplash.rst b/Documentation/bootsplash.rst
-index b35aba5093e8..d4f132eca615 100644
---- a/Documentation/bootsplash.rst
-+++ b/Documentation/bootsplash.rst
-@@ -195,6 +195,16 @@ Hooks - how the bootsplash is integrated
- 
- 
- 
-+Crating a bootsplash theme file
-+===============================
-+
-+A simple tool for theme file creation is included in ``tools/bootsplash``.
-+
-+There is also an example shell script, as an example on how to use the tool
-+and in order to generate a reference bootsplash file.
-+
-+
-+
- FAQ: Frequently Asked Questions
- ===============================
- 
-diff --git a/tools/bootsplash/.gitignore b/tools/bootsplash/.gitignore
-index 091b99a17567..5dfced41ba82 100644
---- a/tools/bootsplash/.gitignore
-+++ b/tools/bootsplash/.gitignore
-@@ -1 +1,4 @@
- bootsplash-packer
-+bootsplash
-+logo.rgb
-+throbber*.rgb
-diff --git a/tools/bootsplash/ajax-loader.gif b/tools/bootsplash/ajax-loader.gif
-new file mode 100644
-index 0000000000000000000000000000000000000000..3288d1035d70bb86517e2c233f1a904e41f06b29
-GIT binary patch
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-HcmV?d00001
-
-diff --git a/tools/bootsplash/bootsplash-tux.sh b/tools/bootsplash/bootsplash-tux.sh
-new file mode 100755
-index 000000000000..1078f87644b9
---- /dev/null
-+++ b/tools/bootsplash/bootsplash-tux.sh
-@@ -0,0 +1,66 @@
-+#!/bin/bash
-+#
-+# A simple script to show how to create a bootsplash.
-+# Do with it whatever you wish.
-+#
-+# This needs ImageMagick for the 'convert' and 'identify' tools.
-+#
-+
-+LOGO=../../Documentation/logo.gif
-+LOGO_WIDTH=$(identify $LOGO | cut -d " " -f 3 | cut -d x -f 1)
-+LOGO_HEIGHT=$(identify $LOGO | cut -d " " -f 3 | cut -d x -f 2)
-+
-+THROBBER=ajax-loader.gif
-+THROBBER_WIDTH=$(identify $THROBBER | head -1 | cut -d " " -f 3 | \
-+						cut -d x -f 1)
-+THROBBER_HEIGHT=$(identify $THROBBER | head -1 | cut -d " " -f 3 | \
-+						 cut -d x -f 2)
-+
-+convert -alpha remove \
-+	-background "#ff3a40" \
-+	$LOGO \
-+	logo.rgb
-+
-+convert -alpha remove \
-+	-background "#ff3a40" \
-+	$THROBBER \
-+	throbber%02d.rgb
-+
-+
-+make clean
-+make bootsplash-packer
-+
-+
-+# Let's put Tux in the center of an orange background.
-+./bootsplash-packer \
-+	--bg_red 0xff \
-+	--bg_green 0x3a \
-+	--bg_blue 0x40 \
-+	--frame_ms 48 \
-+	--picture \
-+	--pic_width $LOGO_WIDTH \
-+	--pic_height $LOGO_HEIGHT \
-+	--pic_position 0 \
-+	--blob logo.rgb \
-+	--picture \
-+	--pic_width $THROBBER_WIDTH \
-+	--pic_height $THROBBER_HEIGHT \
-+	--pic_position 0x14 \
-+	--pic_position_offset 20 \
-+	--pic_anim_type 1 \
-+	--pic_anim_loop 0 \
-+	--blob throbber00.rgb \
-+	--blob throbber01.rgb \
-+	--blob throbber02.rgb \
-+	--blob throbber03.rgb \
-+	--blob throbber04.rgb \
-+	--blob throbber05.rgb \
-+	--blob throbber06.rgb \
-+	--blob throbber07.rgb \
-+	--blob throbber08.rgb \
-+	--blob throbber09.rgb \
-+	--blob throbber10.rgb \
-+	--blob throbber11.rgb \
-+	bootsplash
-+
-+rm *.rgb
diff --git a/disabled/SME-BSP_SME-microcode-update-fixes.patch b/disabled/SME-BSP_SME-microcode-update-fixes.patch
deleted file mode 100644
index 3082f70..0000000
--- a/disabled/SME-BSP_SME-microcode-update-fixes.patch
+++ /dev/null
@@ -1,742 +0,0 @@
-diff -Naur linux-4.14.13/arch/x86/include/asm/mem_encrypt.h linux-4.14.13-p/arch/x86/include/asm/mem_encrypt.h
---- linux-4.14.13/arch/x86/include/asm/mem_encrypt.h	2018-01-10 09:31:23.000000000 +0100
-+++ linux-4.14.13-p/arch/x86/include/asm/mem_encrypt.h	2018-01-11 01:39:30.270647953 +0100
-@@ -39,7 +39,7 @@
- 
- void __init sme_early_init(void);
- 
--void __init sme_encrypt_kernel(void);
-+void __init sme_encrypt_kernel(struct boot_params *bp);
- void __init sme_enable(struct boot_params *bp);
- 
- /* Architecture __weak replacement functions */
-@@ -61,7 +61,7 @@
- 
- static inline void __init sme_early_init(void) { }
- 
--static inline void __init sme_encrypt_kernel(void) { }
-+static inline void __init sme_encrypt_kernel(struct boot_params *bp) { }
- static inline void __init sme_enable(struct boot_params *bp) { }
- 
- #endif	/* CONFIG_AMD_MEM_ENCRYPT */
-diff -Naur linux-4.14.13/arch/x86/kernel/head64.c linux-4.14.13-p/arch/x86/kernel/head64.c
---- linux-4.14.13/arch/x86/kernel/head64.c	2018-01-10 09:31:23.000000000 +0100
-+++ linux-4.14.13-p/arch/x86/kernel/head64.c	2018-01-11 01:39:30.270647953 +0100
-@@ -157,8 +157,8 @@
- 	p = fixup_pointer(&phys_base, physaddr);
- 	*p += load_delta - sme_get_me_mask();
- 
--	/* Encrypt the kernel (if SME is active) */
--	sme_encrypt_kernel();
-+	/* Encrypt the kernel and related (if SME is active) */
-+	sme_encrypt_kernel(bp);
- 
- 	/*
- 	 * Return the SME encryption mask (if SME is active) to be used as a
-diff -Naur linux-4.14.13/arch/x86/kernel/setup.c linux-4.14.13-p/arch/x86/kernel/setup.c
---- linux-4.14.13/arch/x86/kernel/setup.c	2018-01-10 09:31:23.000000000 +0100
-+++ linux-4.14.13-p/arch/x86/kernel/setup.c	2018-01-11 01:43:12.727105535 +0100
-@@ -376,14 +376,6 @@
- 	    !ramdisk_image || !ramdisk_size)
- 		return;		/* No initrd provided by bootloader */
- 
--	/*
--	 * If SME is active, this memory will be marked encrypted by the
--	 * kernel when it is accessed (including relocation). However, the
--	 * ramdisk image was loaded decrypted by the bootloader, so make
--	 * sure that it is encrypted before accessing it.
--	 */
--	sme_early_encrypt(ramdisk_image, ramdisk_end - ramdisk_image);
--
- 	initrd_start = 0;
- 
- 	mapped_size = memblock_mem_size(max_pfn_mapped);
-diff -Naur linux-4.14.13/arch/x86/mm/mem_encrypt_boot.S linux-4.14.13-p/arch/x86/mm/mem_encrypt_boot.S
---- linux-4.14.13/arch/x86/mm/mem_encrypt_boot.S	2018-01-10 09:31:23.000000000 +0100
-+++ linux-4.14.13-p/arch/x86/mm/mem_encrypt_boot.S	2018-01-11 01:39:30.273981283 +0100
-@@ -22,9 +22,9 @@
- 
- 	/*
- 	 * Entry parameters:
--	 *   RDI - virtual address for the encrypted kernel mapping
--	 *   RSI - virtual address for the decrypted kernel mapping
--	 *   RDX - length of kernel
-+	 *   RDI - virtual address for the encrypted mapping
-+	 *   RSI - virtual address for the decrypted mapping
-+	 *   RDX - length to encrypt
- 	 *   RCX - virtual address of the encryption workarea, including:
- 	 *     - stack page (PAGE_SIZE)
- 	 *     - encryption routine page (PAGE_SIZE)
-@@ -41,9 +41,9 @@
- 	addq	$PAGE_SIZE, %rax	/* Workarea encryption routine */
- 
- 	push	%r12
--	movq	%rdi, %r10		/* Encrypted kernel */
--	movq	%rsi, %r11		/* Decrypted kernel */
--	movq	%rdx, %r12		/* Kernel length */
-+	movq	%rdi, %r10		/* Encrypted area */
-+	movq	%rsi, %r11		/* Decrypted area */
-+	movq	%rdx, %r12		/* Area length */
- 
- 	/* Copy encryption routine into the workarea */
- 	movq	%rax, %rdi				/* Workarea encryption routine */
-@@ -52,10 +52,10 @@
- 	rep	movsb
- 
- 	/* Setup registers for call */
--	movq	%r10, %rdi		/* Encrypted kernel */
--	movq	%r11, %rsi		/* Decrypted kernel */
-+	movq	%r10, %rdi		/* Encrypted area */
-+	movq	%r11, %rsi		/* Decrypted area */
- 	movq	%r8, %rdx		/* Pagetables used for encryption */
--	movq	%r12, %rcx		/* Kernel length */
-+	movq	%r12, %rcx		/* Area length */
- 	movq	%rax, %r8		/* Workarea encryption routine */
- 	addq	$PAGE_SIZE, %r8		/* Workarea intermediate copy buffer */
- 
-@@ -71,7 +71,7 @@
- 
- ENTRY(__enc_copy)
- /*
-- * Routine used to encrypt kernel.
-+ * Routine used to encrypt memory in place.
-  *   This routine must be run outside of the kernel proper since
-  *   the kernel will be encrypted during the process. So this
-  *   routine is defined here and then copied to an area outside
-@@ -79,19 +79,19 @@
-  *   during execution.
-  *
-  *   On entry the registers must be:
-- *     RDI - virtual address for the encrypted kernel mapping
-- *     RSI - virtual address for the decrypted kernel mapping
-+ *     RDI - virtual address for the encrypted mapping
-+ *     RSI - virtual address for the decrypted mapping
-  *     RDX - address of the pagetables to use for encryption
-- *     RCX - length of kernel
-+ *     RCX - length of area
-  *      R8 - intermediate copy buffer
-  *
-  *     RAX - points to this routine
-  *
-- * The kernel will be encrypted by copying from the non-encrypted
-- * kernel space to an intermediate buffer and then copying from the
-- * intermediate buffer back to the encrypted kernel space. The physical
-- * addresses of the two kernel space mappings are the same which
-- * results in the kernel being encrypted "in place".
-+ * The area will be encrypted by copying from the non-encrypted
-+ * memory space to an intermediate buffer and then copying from the
-+ * intermediate buffer back to the encrypted memory space. The physical
-+ * addresses of the two mappings are the same which results in the area
-+ * being encrypted "in place".
-  */
- 	/* Enable the new page tables */
- 	mov	%rdx, %cr3
-@@ -103,47 +103,55 @@
- 	orq	$X86_CR4_PGE, %rdx
- 	mov	%rdx, %cr4
- 
-+	push	%r15
-+	push	%r12
-+
-+	movq	%rcx, %r9		/* Save area length */
-+	movq	%rdi, %r10		/* Save encrypted area address */
-+	movq	%rsi, %r11		/* Save decrypted area address */
-+
- 	/* Set the PAT register PA5 entry to write-protect */
--	push	%rcx
- 	movl	$MSR_IA32_CR_PAT, %ecx
- 	rdmsr
--	push	%rdx			/* Save original PAT value */
-+	mov	%rdx, %r15		/* Save original PAT value */
- 	andl	$0xffff00ff, %edx	/* Clear PA5 */
- 	orl	$0x00000500, %edx	/* Set PA5 to WP */
- 	wrmsr
--	pop	%rdx			/* RDX contains original PAT value */
--	pop	%rcx
--
--	movq	%rcx, %r9		/* Save kernel length */
--	movq	%rdi, %r10		/* Save encrypted kernel address */
--	movq	%rsi, %r11		/* Save decrypted kernel address */
- 
- 	wbinvd				/* Invalidate any cache entries */
- 
--	/* Copy/encrypt 2MB at a time */
-+	/* Copy/encrypt up to 2MB at a time */
-+	movq	$PMD_PAGE_SIZE, %r12
- 1:
--	movq	%r11, %rsi		/* Source - decrypted kernel */
-+	cmpq	%r12, %r9
-+	jnb	2f
-+	movq	%r9, %r12
-+
-+2:
-+	movq	%r11, %rsi		/* Source - decrypted area */
- 	movq	%r8, %rdi		/* Dest   - intermediate copy buffer */
--	movq	$PMD_PAGE_SIZE, %rcx	/* 2MB length */
-+	movq	%r12, %rcx
- 	rep	movsb
- 
- 	movq	%r8, %rsi		/* Source - intermediate copy buffer */
--	movq	%r10, %rdi		/* Dest   - encrypted kernel */
--	movq	$PMD_PAGE_SIZE, %rcx	/* 2MB length */
-+	movq	%r10, %rdi		/* Dest   - encrypted area */
-+	movq	%r12, %rcx
- 	rep	movsb
- 
--	addq	$PMD_PAGE_SIZE, %r11
--	addq	$PMD_PAGE_SIZE, %r10
--	subq	$PMD_PAGE_SIZE, %r9	/* Kernel length decrement */
-+	addq	%r12, %r11
-+	addq	%r12, %r10
-+	subq	%r12, %r9		/* Kernel length decrement */
- 	jnz	1b			/* Kernel length not zero? */
- 
- 	/* Restore PAT register */
--	push	%rdx			/* Save original PAT value */
- 	movl	$MSR_IA32_CR_PAT, %ecx
- 	rdmsr
--	pop	%rdx			/* Restore original PAT value */
-+	mov	%r15, %rdx		/* Restore original PAT value */
- 	wrmsr
- 
-+	pop	%r12
-+	pop	%r15
-+
- 	ret
- .L__enc_copy_end:
- ENDPROC(__enc_copy)
-diff -Naur linux-4.14.13/arch/x86/mm/mem_encrypt.c linux-4.14.13-p/arch/x86/mm/mem_encrypt.c
---- linux-4.14.13/arch/x86/mm/mem_encrypt.c	2018-01-10 09:31:23.000000000 +0100
-+++ linux-4.14.13-p/arch/x86/mm/mem_encrypt.c	2018-01-11 01:39:30.273981283 +0100
-@@ -213,37 +213,62 @@
- 	set_memory_decrypted((unsigned long)vaddr, size >> PAGE_SHIFT);
- }
- 
--static void __init sme_clear_pgd(pgd_t *pgd_base, unsigned long start,
--				 unsigned long end)
-+struct sme_populate_pgd_data {
-+	void	*pgtable_area;
-+	pgd_t	*pgd;
-+
-+	pmdval_t pmd_flags;
-+	pteval_t pte_flags;
-+	unsigned long paddr;
-+
-+	unsigned long vaddr;
-+	unsigned long vaddr_end;
-+};
-+
-+static void __init sme_clear_pgd(struct sme_populate_pgd_data *ppd)
- {
- 	unsigned long pgd_start, pgd_end, pgd_size;
- 	pgd_t *pgd_p;
- 
--	pgd_start = start & PGDIR_MASK;
--	pgd_end = end & PGDIR_MASK;
-+	pgd_start = ppd->vaddr & PGDIR_MASK;
-+	pgd_end = ppd->vaddr_end & PGDIR_MASK;
- 
--	pgd_size = (((pgd_end - pgd_start) / PGDIR_SIZE) + 1);
--	pgd_size *= sizeof(pgd_t);
-+	pgd_size = (((pgd_end - pgd_start) / PGDIR_SIZE) + 1) * sizeof(pgd_t);
- 
--	pgd_p = pgd_base + pgd_index(start);
-+	pgd_p = ppd->pgd + pgd_index(ppd->vaddr);
- 
- 	memset(pgd_p, 0, pgd_size);
- }
- 
--#define PGD_FLAGS	_KERNPG_TABLE_NOENC
--#define P4D_FLAGS	_KERNPG_TABLE_NOENC
--#define PUD_FLAGS	_KERNPG_TABLE_NOENC
--#define PMD_FLAGS	(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL)
-+#define PGD_FLAGS		_KERNPG_TABLE_NOENC
-+#define P4D_FLAGS		_KERNPG_TABLE_NOENC
-+#define PUD_FLAGS		_KERNPG_TABLE_NOENC
-+#define PMD_FLAGS		_KERNPG_TABLE_NOENC
-+
-+#define PMD_FLAGS_LARGE		(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL)
-+
-+#define PMD_FLAGS_DEC		PMD_FLAGS_LARGE
-+#define PMD_FLAGS_DEC_WP	((PMD_FLAGS_DEC & ~_PAGE_CACHE_MASK) | \
-+				 (_PAGE_PAT | _PAGE_PWT))
-+
-+#define PMD_FLAGS_ENC		(PMD_FLAGS_LARGE | _PAGE_ENC)
-+
-+#define PTE_FLAGS		(__PAGE_KERNEL_EXEC & ~_PAGE_GLOBAL)
- 
--static void __init *sme_populate_pgd(pgd_t *pgd_base, void *pgtable_area,
--				     unsigned long vaddr, pmdval_t pmd_val)
-+#define PTE_FLAGS_DEC		PTE_FLAGS
-+#define PTE_FLAGS_DEC_WP	((PTE_FLAGS_DEC & ~_PAGE_CACHE_MASK) | \
-+				 (_PAGE_PAT | _PAGE_PWT))
-+
-+#define PTE_FLAGS_ENC		(PTE_FLAGS | _PAGE_ENC)
-+
-+static pmd_t __init *sme_prepare_pgd(struct sme_populate_pgd_data *ppd)
- {
- 	pgd_t *pgd_p;
- 	p4d_t *p4d_p;
- 	pud_t *pud_p;
- 	pmd_t *pmd_p;
- 
--	pgd_p = pgd_base + pgd_index(vaddr);
-+	pgd_p = ppd->pgd + pgd_index(ppd->vaddr);
- 	if (native_pgd_val(*pgd_p)) {
- 		if (IS_ENABLED(CONFIG_X86_5LEVEL))
- 			p4d_p = (p4d_t *)(native_pgd_val(*pgd_p) & ~PTE_FLAGS_MASK);
-@@ -253,15 +278,15 @@
- 		pgd_t pgd;
- 
- 		if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
--			p4d_p = pgtable_area;
-+			p4d_p = ppd->pgtable_area;
- 			memset(p4d_p, 0, sizeof(*p4d_p) * PTRS_PER_P4D);
--			pgtable_area += sizeof(*p4d_p) * PTRS_PER_P4D;
-+			ppd->pgtable_area += sizeof(*p4d_p) * PTRS_PER_P4D;
- 
- 			pgd = native_make_pgd((pgdval_t)p4d_p + PGD_FLAGS);
- 		} else {
--			pud_p = pgtable_area;
-+			pud_p = ppd->pgtable_area;
- 			memset(pud_p, 0, sizeof(*pud_p) * PTRS_PER_PUD);
--			pgtable_area += sizeof(*pud_p) * PTRS_PER_PUD;
-+			ppd->pgtable_area += sizeof(*pud_p) * PTRS_PER_PUD;
- 
- 			pgd = native_make_pgd((pgdval_t)pud_p + PGD_FLAGS);
- 		}
-@@ -269,58 +294,160 @@
- 	}
- 
- 	if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
--		p4d_p += p4d_index(vaddr);
-+		p4d_p += p4d_index(ppd->vaddr);
- 		if (native_p4d_val(*p4d_p)) {
- 			pud_p = (pud_t *)(native_p4d_val(*p4d_p) & ~PTE_FLAGS_MASK);
- 		} else {
- 			p4d_t p4d;
- 
--			pud_p = pgtable_area;
-+			pud_p = ppd->pgtable_area;
- 			memset(pud_p, 0, sizeof(*pud_p) * PTRS_PER_PUD);
--			pgtable_area += sizeof(*pud_p) * PTRS_PER_PUD;
-+			ppd->pgtable_area += sizeof(*pud_p) * PTRS_PER_PUD;
- 
- 			p4d = native_make_p4d((pudval_t)pud_p + P4D_FLAGS);
- 			native_set_p4d(p4d_p, p4d);
- 		}
- 	}
- 
--	pud_p += pud_index(vaddr);
-+	pud_p += pud_index(ppd->vaddr);
- 	if (native_pud_val(*pud_p)) {
- 		if (native_pud_val(*pud_p) & _PAGE_PSE)
--			goto out;
-+			return NULL;
- 
- 		pmd_p = (pmd_t *)(native_pud_val(*pud_p) & ~PTE_FLAGS_MASK);
- 	} else {
- 		pud_t pud;
- 
--		pmd_p = pgtable_area;
-+		pmd_p = ppd->pgtable_area;
- 		memset(pmd_p, 0, sizeof(*pmd_p) * PTRS_PER_PMD);
--		pgtable_area += sizeof(*pmd_p) * PTRS_PER_PMD;
-+		ppd->pgtable_area += sizeof(*pmd_p) * PTRS_PER_PMD;
- 
- 		pud = native_make_pud((pmdval_t)pmd_p + PUD_FLAGS);
- 		native_set_pud(pud_p, pud);
- 	}
- 
--	pmd_p += pmd_index(vaddr);
-+	return pmd_p;
-+}
-+
-+static void __init sme_populate_pgd_large(struct sme_populate_pgd_data *ppd)
-+{
-+	pmd_t *pmd_p;
-+
-+	pmd_p = sme_prepare_pgd(ppd);
-+	if (!pmd_p)
-+		return;
-+
-+	pmd_p += pmd_index(ppd->vaddr);
- 	if (!native_pmd_val(*pmd_p) || !(native_pmd_val(*pmd_p) & _PAGE_PSE))
--		native_set_pmd(pmd_p, native_make_pmd(pmd_val));
-+		native_set_pmd(pmd_p, native_make_pmd(ppd->paddr | ppd->pmd_flags));
-+}
-+
-+static void __init sme_populate_pgd(struct sme_populate_pgd_data *ppd)
-+{
-+	pmd_t *pmd_p;
-+	pte_t *pte_p;
-+
-+	pmd_p = sme_prepare_pgd(ppd);
-+	if (!pmd_p)
-+		return;
-+
-+	pmd_p += pmd_index(ppd->vaddr);
-+	if (native_pmd_val(*pmd_p)) {
-+		if (native_pmd_val(*pmd_p) & _PAGE_PSE)
-+			return;
-+
-+		pte_p = (pte_t *)(native_pmd_val(*pmd_p) & ~PTE_FLAGS_MASK);
-+	} else {
-+		pmd_t pmd;
-+
-+		pte_p = ppd->pgtable_area;
-+		memset(pte_p, 0, sizeof(*pte_p) * PTRS_PER_PTE);
-+		ppd->pgtable_area += sizeof(*pte_p) * PTRS_PER_PTE;
-+
-+		pmd = native_make_pmd((pteval_t)pte_p + PMD_FLAGS);
-+		native_set_pmd(pmd_p, pmd);
-+	}
-+
-+	pte_p += pte_index(ppd->vaddr);
-+	if (!native_pte_val(*pte_p))
-+		native_set_pte(pte_p, native_make_pte(ppd->paddr | ppd->pte_flags));
-+}
-+
-+static void __init __sme_map_range_pmd(struct sme_populate_pgd_data *ppd)
-+{
-+	while (ppd->vaddr < ppd->vaddr_end) {
-+		sme_populate_pgd_large(ppd);
-+
-+		ppd->vaddr += PMD_PAGE_SIZE;
-+		ppd->paddr += PMD_PAGE_SIZE;
-+	}
-+}
-+
-+static void __init __sme_map_range_pte(struct sme_populate_pgd_data *ppd)
-+{
-+	while (ppd->vaddr < ppd->vaddr_end) {
-+		sme_populate_pgd(ppd);
- 
--out:
--	return pgtable_area;
-+		ppd->vaddr += PAGE_SIZE;
-+		ppd->paddr += PAGE_SIZE;
-+	}
-+}
-+
-+static void __init __sme_map_range(struct sme_populate_pgd_data *ppd,
-+				   pmdval_t pmd_flags, pteval_t pte_flags)
-+{
-+	unsigned long vaddr_end;
-+
-+	ppd->pmd_flags = pmd_flags;
-+	ppd->pte_flags = pte_flags;
-+
-+	/* Save original end value since we modify the struct value */
-+	vaddr_end = ppd->vaddr_end;
-+
-+	/* If start is not 2MB aligned, create PTE entries */
-+	ppd->vaddr_end = ALIGN(ppd->vaddr, PMD_PAGE_SIZE);
-+	__sme_map_range_pte(ppd);
-+
-+	/* Create PMD entries */
-+	ppd->vaddr_end = vaddr_end & PMD_PAGE_MASK;
-+	__sme_map_range_pmd(ppd);
-+
-+	/* If end is not 2MB aligned, create PTE entries */
-+	ppd->vaddr_end = vaddr_end;
-+	__sme_map_range_pte(ppd);
-+}
-+
-+static void __init sme_map_range_encrypted(struct sme_populate_pgd_data *ppd)
-+{
-+	__sme_map_range(ppd, PMD_FLAGS_ENC, PTE_FLAGS_ENC);
-+}
-+
-+static void __init sme_map_range_decrypted(struct sme_populate_pgd_data *ppd)
-+{
-+	__sme_map_range(ppd, PMD_FLAGS_DEC, PTE_FLAGS_DEC);
-+}
-+
-+static void __init sme_map_range_decrypted_wp(struct sme_populate_pgd_data *ppd)
-+{
-+	__sme_map_range(ppd, PMD_FLAGS_DEC_WP, PTE_FLAGS_DEC_WP);
- }
- 
- static unsigned long __init sme_pgtable_calc(unsigned long len)
- {
--	unsigned long p4d_size, pud_size, pmd_size;
-+	unsigned long p4d_size, pud_size, pmd_size, pte_size;
- 	unsigned long total;
- 
- 	/*
- 	 * Perform a relatively simplistic calculation of the pagetable
--	 * entries that are needed. That mappings will be covered by 2MB
--	 * PMD entries so we can conservatively calculate the required
-+	 * entries that are needed. Those mappings will be covered mostly
-+	 * by 2MB PMD entries so we can conservatively calculate the required
- 	 * number of P4D, PUD and PMD structures needed to perform the
--	 * mappings. Incrementing the count for each covers the case where
--	 * the addresses cross entries.
-+	 * mappings.  For mappings that are not 2MB aligned, PTE mappings
-+	 * would be needed for the start and end portion of the address range
-+	 * that fall outside of the 2MB alignment.  This results in, at most,
-+	 * two extra pages to hold PTE entries for each range that is mapped.
-+	 * Incrementing the count for each covers the case where the addresses
-+	 * cross entries.
- 	 */
- 	if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
- 		p4d_size = (ALIGN(len, PGDIR_SIZE) / PGDIR_SIZE) + 1;
-@@ -334,8 +461,9 @@
- 	}
- 	pmd_size = (ALIGN(len, PUD_SIZE) / PUD_SIZE) + 1;
- 	pmd_size *= sizeof(pmd_t) * PTRS_PER_PMD;
-+	pte_size = 2 * sizeof(pte_t) * PTRS_PER_PTE;
- 
--	total = p4d_size + pud_size + pmd_size;
-+	total = p4d_size + pud_size + pmd_size + pte_size;
- 
- 	/*
- 	 * Now calculate the added pagetable structures needed to populate
-@@ -359,29 +487,29 @@
- 	return total;
- }
- 
--void __init sme_encrypt_kernel(void)
-+void __init sme_encrypt_kernel(struct boot_params *bp)
- {
- 	unsigned long workarea_start, workarea_end, workarea_len;
- 	unsigned long execute_start, execute_end, execute_len;
- 	unsigned long kernel_start, kernel_end, kernel_len;
-+	unsigned long initrd_start, initrd_end, initrd_len;
-+	struct sme_populate_pgd_data ppd;
- 	unsigned long pgtable_area_len;
--	unsigned long paddr, pmd_flags;
- 	unsigned long decrypted_base;
--	void *pgtable_area;
--	pgd_t *pgd;
- 
- 	if (!sme_active())
- 		return;
- 
- 	/*
--	 * Prepare for encrypting the kernel by building new pagetables with
--	 * the necessary attributes needed to encrypt the kernel in place.
-+	 * Prepare for encrypting the kernel and initrd by building new
-+	 * pagetables with the necessary attributes needed to encrypt the
-+	 * kernel in place.
- 	 *
- 	 *   One range of virtual addresses will map the memory occupied
--	 *   by the kernel as encrypted.
-+	 *   by the kernel and initrd as encrypted.
- 	 *
- 	 *   Another range of virtual addresses will map the memory occupied
--	 *   by the kernel as decrypted and write-protected.
-+	 *   by the kernel and initrd as decrypted and write-protected.
- 	 *
- 	 *     The use of write-protect attribute will prevent any of the
- 	 *     memory from being cached.
-@@ -392,6 +520,20 @@
- 	kernel_end = ALIGN(__pa_symbol(_end), PMD_PAGE_SIZE);
- 	kernel_len = kernel_end - kernel_start;
- 
-+	initrd_start = 0;
-+	initrd_end = 0;
-+	initrd_len = 0;
-+#ifdef CONFIG_BLK_DEV_INITRD
-+	initrd_len = (unsigned long)bp->hdr.ramdisk_size |
-+		     ((unsigned long)bp->ext_ramdisk_size << 32);
-+	if (initrd_len) {
-+		initrd_start = (unsigned long)bp->hdr.ramdisk_image |
-+			       ((unsigned long)bp->ext_ramdisk_image << 32);
-+		initrd_end = PAGE_ALIGN(initrd_start + initrd_len);
-+		initrd_len = initrd_end - initrd_start;
-+	}
-+#endif
-+
- 	/* Set the encryption workarea to be immediately after the kernel */
- 	workarea_start = kernel_end;
- 
-@@ -414,16 +556,21 @@
- 	 */
- 	pgtable_area_len = sizeof(pgd_t) * PTRS_PER_PGD;
- 	pgtable_area_len += sme_pgtable_calc(execute_end - kernel_start) * 2;
-+	if (initrd_len)
-+		pgtable_area_len += sme_pgtable_calc(initrd_len) * 2;
- 
- 	/* PUDs and PMDs needed in the current pagetables for the workarea */
- 	pgtable_area_len += sme_pgtable_calc(execute_len + pgtable_area_len);
- 
- 	/*
- 	 * The total workarea includes the executable encryption area and
--	 * the pagetable area.
-+	 * the pagetable area. The start of the workarea is already 2MB
-+	 * aligned, align the end of the workarea on a 2MB boundary so that
-+	 * we don't try to create/allocate PTE entries from the workarea
-+	 * before it is mapped.
- 	 */
- 	workarea_len = execute_len + pgtable_area_len;
--	workarea_end = workarea_start + workarea_len;
-+	workarea_end = ALIGN(workarea_start + workarea_len, PMD_PAGE_SIZE);
- 
- 	/*
- 	 * Set the address to the start of where newly created pagetable
-@@ -432,45 +579,30 @@
- 	 * pagetables and when the new encrypted and decrypted kernel
- 	 * mappings are populated.
- 	 */
--	pgtable_area = (void *)execute_end;
-+	ppd.pgtable_area = (void *)execute_end;
- 
- 	/*
- 	 * Make sure the current pagetable structure has entries for
- 	 * addressing the workarea.
- 	 */
--	pgd = (pgd_t *)native_read_cr3_pa();
--	paddr = workarea_start;
--	while (paddr < workarea_end) {
--		pgtable_area = sme_populate_pgd(pgd, pgtable_area,
--						paddr,
--						paddr + PMD_FLAGS);
--
--		paddr += PMD_PAGE_SIZE;
--	}
-+	ppd.pgd = (pgd_t *)native_read_cr3_pa();
-+	ppd.paddr = workarea_start;
-+	ppd.vaddr = workarea_start;
-+	ppd.vaddr_end = workarea_end;
-+	sme_map_range_decrypted(&ppd);
- 
- 	/* Flush the TLB - no globals so cr3 is enough */
- 	native_write_cr3(__native_read_cr3());
- 
- 	/*
- 	 * A new pagetable structure is being built to allow for the kernel
--	 * to be encrypted. It starts with an empty PGD that will then be
--	 * populated with new PUDs and PMDs as the encrypted and decrypted
--	 * kernel mappings are created.
--	 */
--	pgd = pgtable_area;
--	memset(pgd, 0, sizeof(*pgd) * PTRS_PER_PGD);
--	pgtable_area += sizeof(*pgd) * PTRS_PER_PGD;
--
--	/* Add encrypted kernel (identity) mappings */
--	pmd_flags = PMD_FLAGS | _PAGE_ENC;
--	paddr = kernel_start;
--	while (paddr < kernel_end) {
--		pgtable_area = sme_populate_pgd(pgd, pgtable_area,
--						paddr,
--						paddr + pmd_flags);
--
--		paddr += PMD_PAGE_SIZE;
--	}
-+	 * and initrd to be encrypted. It starts with an empty PGD that will
-+	 * then be populated with new PUDs and PMDs as the encrypted and
-+	 * decrypted kernel mappings are created.
-+	 */
-+	ppd.pgd = ppd.pgtable_area;
-+	memset(ppd.pgd, 0, sizeof(pgd_t) * PTRS_PER_PGD);
-+	ppd.pgtable_area += sizeof(pgd_t) * PTRS_PER_PGD;
- 
- 	/*
- 	 * A different PGD index/entry must be used to get different
-@@ -479,47 +611,79 @@
- 	 * the base of the mapping.
- 	 */
- 	decrypted_base = (pgd_index(workarea_end) + 1) & (PTRS_PER_PGD - 1);
-+	if (initrd_len) {
-+		unsigned long check_base;
-+
-+		check_base = (pgd_index(initrd_end) + 1) & (PTRS_PER_PGD - 1);
-+		decrypted_base = max(decrypted_base, check_base);
-+	}
- 	decrypted_base <<= PGDIR_SHIFT;
- 
--	/* Add decrypted, write-protected kernel (non-identity) mappings */
--	pmd_flags = (PMD_FLAGS & ~_PAGE_CACHE_MASK) | (_PAGE_PAT | _PAGE_PWT);
--	paddr = kernel_start;
--	while (paddr < kernel_end) {
--		pgtable_area = sme_populate_pgd(pgd, pgtable_area,
--						paddr + decrypted_base,
--						paddr + pmd_flags);
-+	/* Add encrypted kernel (identity) mappings */
-+	ppd.paddr = kernel_start;
-+	ppd.vaddr = kernel_start;
-+	ppd.vaddr_end = kernel_end;
-+	sme_map_range_encrypted(&ppd);
- 
--		paddr += PMD_PAGE_SIZE;
-+	/* Add decrypted, write-protected kernel (non-identity) mappings */
-+	ppd.paddr = kernel_start;
-+	ppd.vaddr = kernel_start + decrypted_base;
-+	ppd.vaddr_end = kernel_end + decrypted_base;
-+	sme_map_range_decrypted_wp(&ppd);
-+
-+	if (initrd_len) {
-+		/* Add encrypted initrd (identity) mappings */
-+		ppd.paddr = initrd_start;
-+		ppd.vaddr = initrd_start;
-+		ppd.vaddr_end = initrd_end;
-+		sme_map_range_encrypted(&ppd);
-+		/*
-+		 * Add decrypted, write-protected initrd (non-identity) mappings
-+		 */
-+		ppd.paddr = initrd_start;
-+		ppd.vaddr = initrd_start + decrypted_base;
-+		ppd.vaddr_end = initrd_end + decrypted_base;
-+		sme_map_range_decrypted_wp(&ppd);
- 	}
- 
- 	/* Add decrypted workarea mappings to both kernel mappings */
--	paddr = workarea_start;
--	while (paddr < workarea_end) {
--		pgtable_area = sme_populate_pgd(pgd, pgtable_area,
--						paddr,
--						paddr + PMD_FLAGS);
--
--		pgtable_area = sme_populate_pgd(pgd, pgtable_area,
--						paddr + decrypted_base,
--						paddr + PMD_FLAGS);
--
--		paddr += PMD_PAGE_SIZE;
--	}
-+	ppd.paddr = workarea_start;
-+	ppd.vaddr = workarea_start;
-+	ppd.vaddr_end = workarea_end;
-+	sme_map_range_decrypted(&ppd);
-+
-+	ppd.paddr = workarea_start;
-+	ppd.vaddr = workarea_start + decrypted_base;
-+	ppd.vaddr_end = workarea_end + decrypted_base;
-+	sme_map_range_decrypted(&ppd);
- 
- 	/* Perform the encryption */
- 	sme_encrypt_execute(kernel_start, kernel_start + decrypted_base,
--			    kernel_len, workarea_start, (unsigned long)pgd);
-+			    kernel_len, workarea_start, (unsigned long)ppd.pgd);
-+
-+	if (initrd_len)
-+		sme_encrypt_execute(initrd_start, initrd_start + decrypted_base,
-+				    initrd_len, workarea_start,
-+				    (unsigned long)ppd.pgd);
- 
- 	/*
- 	 * At this point we are running encrypted.  Remove the mappings for
- 	 * the decrypted areas - all that is needed for this is to remove
- 	 * the PGD entry/entries.
- 	 */
--	sme_clear_pgd(pgd, kernel_start + decrypted_base,
--		      kernel_end + decrypted_base);
-+	ppd.vaddr = kernel_start + decrypted_base;
-+	ppd.vaddr_end = kernel_end + decrypted_base;
-+	sme_clear_pgd(&ppd);
-+
-+	if (initrd_len) {
-+		ppd.vaddr = initrd_start + decrypted_base;
-+		ppd.vaddr_end = initrd_end + decrypted_base;
-+		sme_clear_pgd(&ppd);
-+	}
- 
--	sme_clear_pgd(pgd, workarea_start + decrypted_base,
--		      workarea_end + decrypted_base);
-+	ppd.vaddr = workarea_start + decrypted_base;
-+	ppd.vaddr_end = workarea_end + decrypted_base;
-+	sme_clear_pgd(&ppd);
- 
- 	/* Flush the TLB - no globals so cr3 is enough */
- 	native_write_cr3(__native_read_cr3());
diff --git a/disabled/acer-wmi-silence-unknow-functions-messages.patch b/disabled/acer-wmi-silence-unknow-functions-messages.patch
deleted file mode 100644
index 1205d5a..0000000
--- a/disabled/acer-wmi-silence-unknow-functions-messages.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-diff -Naur linux-5.3.1/drivers/platform/x86/acer-wmi.c linux-5.3.1-acer/drivers/platform/x86/acer-wmi.c
---- linux-5.3.1/drivers/platform/x86/acer-wmi.c	2019-09-21 07:19:47.000000000 +0200
-+++ linux-5.3.1-acer/drivers/platform/x86/acer-wmi.c	2019-09-27 16:10:57.372620915 +0200
-@@ -237,6 +237,7 @@
- static int force_series;
- static bool ec_raw_mode;
- static bool has_type_aa;
-+static bool be_silent;
- static u16 commun_func_bitmap;
- static u8 commun_fn_key_number;
- 
-@@ -245,11 +246,14 @@
- module_param(threeg, int, 0444);
- module_param(force_series, int, 0444);
- module_param(ec_raw_mode, bool, 0444);
-+module_param(be_silent, bool, 0444);
-+
- MODULE_PARM_DESC(mailled, "Set initial state of Mail LED");
- MODULE_PARM_DESC(brightness, "Set initial LCD backlight brightness");
- MODULE_PARM_DESC(threeg, "Set initial state of 3G hardware");
- MODULE_PARM_DESC(force_series, "Force a different laptop series");
- MODULE_PARM_DESC(ec_raw_mode, "Enable EC raw mode");
-+MODULE_PARM_DESC(be_silent, "Disables Unknow functions messages");
- 
- struct acer_data {
- 	int mailled;
-@@ -1773,8 +1777,10 @@
- 		acer_gsensor_event();
- 		break;
- 	default:
--		pr_warn("Unknown function number - %d - %d\n",
--			return_value.function, return_value.key_num);
-+		if (!be_silent) {
-+			pr_warn("Unknown function number - %d - %d\n",
-+				return_value.function, return_value.key_num);
-+		}
- 		break;
- 	}
- }
diff --git a/disabled/extra-dvb-drivers-4.16.patch b/disabled/extra-dvb-drivers-4.16.patch
deleted file mode 100644
index 5e2a537..0000000
--- a/disabled/extra-dvb-drivers-4.16.patch
+++ /dev/null
@@ -1,75 +0,0 @@
---- linux-4.15/drivers/media/dvb-frontends/si2168b.c.omv~	2018-02-13 13:01:39.417460412 +0100
-+++ linux-4.15/drivers/media/dvb-frontends/si2168b.c	2018-02-13 13:01:42.512477570 +0100
-@@ -12,7 +12,6 @@
- #include <linux/jiffies.h>
- #include <asm/div64.h>
- 
--#include "dvb_frontend.h"
- #include "si2168b_priv.h"
- #include "silabs_tercab.h"
- 
---- linux-4.15/drivers/media/dvb-frontends/si2168b.h.omv~	2018-02-13 13:02:20.033684040 +0100
-+++ linux-4.15/drivers/media/dvb-frontends/si2168b.h	2018-02-13 13:03:47.063152873 +0100
-@@ -20,7 +20,7 @@ struct dvb_stream_ids {
- 
- #include <linux/kconfig.h>
- #include <linux/dvb/frontend.h>
--#include "dvb_frontend.h"
-+#include <media/dvb_frontend.h>
- 
- extern int _sitrace; /* module parameter: SiTRACE on/off */
- 
---- linux-4.15/drivers/media/dvb-frontends/silg.c.omv~	2018-02-13 13:04:49.114479534 +0100
-+++ linux-4.15/drivers/media/dvb-frontends/silg.c	2018-02-13 13:04:56.647518801 +0100
-@@ -12,7 +12,7 @@
- #include <linux/string.h>
- #include <linux/slab.h>
- 
--#include "dvb_frontend.h"
-+#include <media/dvb_frontend.h>
- #include "silg.h"
- 
- static int debug = 0;
---- linux-4.15/drivers/media/dvb-frontends/silg.h.omv~	2018-02-13 13:05:45.946773861 +0100
-+++ linux-4.15/drivers/media/dvb-frontends/silg.h	2018-02-13 13:05:51.591802862 +0100
-@@ -3,7 +3,7 @@
- 
- #include <linux/kconfig.h>
- #include <linux/dvb/frontend.h>
--#include "dvb_frontend.h"
-+#include <media/dvb_frontend.h>
- 
- #include "lgdt3306a.h"
- #include "si2168b.h"
---- linux-4.15/drivers/media/tuners/silabs_tercab.c.omv~	2018-02-13 13:09:01.875759417 +0100
-+++ linux-4.15/drivers/media/tuners/silabs_tercab.c	2018-02-13 13:09:44.377968293 +0100
-@@ -7,8 +7,10 @@
-  *
-  */
- 
--#include  <linux/delay.h>
-+#include <linux/delay.h>
- #include <linux/videodev2.h>
-+#include <linux/module.h>
-+#include <media/dvb_frontend.h>
- #include "tuner-i2c.h"
- #include "silabs_tercab_priv.h"
- 
-@@ -3441,7 +3443,6 @@ MODULE_DESCRIPTION("Silicon Labs terrest
- MODULE_AUTHOR("Source code provided by Silicon Laboratories Inc.");
- MODULE_AUTHOR("Henning Garbers <hgarbers@pctvsystems.com>");
- MODULE_LICENSE("PROPRIETARY AND CONFIDENTIAL");
--MODULE_VERSION("2015-02-05");
- 
- /*
-  * Overrides for Emacs so that we follow Linus's tabbing style.
---- linux-4.15/drivers/media/tuners/silabs_tercab.h.omv~	2018-02-13 13:03:16.122987712 +0100
-+++ linux-4.15/drivers/media/tuners/silabs_tercab.h	2018-02-13 13:03:18.102998329 +0100
-@@ -20,7 +20,6 @@
- #define __SILABS_TERCAB_H__
- 
- #include <linux/i2c.h>
--#include "dvb_frontend.h"
- 
- #define HVR19x5_QAM_IF 4000
- #define HVR19x5_VSB_IF 3250
diff --git a/disabled/hauppauge-hvr-1975.patch b/disabled/hauppauge-hvr-1975.patch
deleted file mode 100644
index f080aca..0000000
--- a/disabled/hauppauge-hvr-1975.patch
+++ /dev/null
@@ -1,23046 +0,0 @@
---- linux-4.15/drivers/media/common/tveeprom.c.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/common/tveeprom.c	2018-02-12 11:32:52.760582121 +0100
-@@ -551,7 +551,8 @@ void tveeprom_hauppauge_analog(struct tv
- 				(eeprom_data[i+7] << 16)+
- 				(eeprom_data[i+8] << 24);
- 
--			if (eeprom_data[i + 8] == 0xf0) {
-+			if ((eeprom_data[i + 8] & 0xf0) &&
-+					(tvee->serial_number < 0xffffff)) {
- 				tvee->MAC_address[0] = 0x00;
- 				tvee->MAC_address[1] = 0x0D;
- 				tvee->MAC_address[2] = 0xFE;
---- linux-4.15/drivers/media/dvb-frontends/Kconfig.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/dvb-frontends/Kconfig	2018-02-12 11:32:52.760582121 +0100
-@@ -529,6 +529,13 @@ config DVB_SI2168
- 	help
- 	  Say Y when you want to support this frontend.
- 
-+config DVB_SI2168B
-+	tristate "Silicon Labs Si2168B"
-+	depends on DVB_CORE && I2C && I2C_MUX
-+	default m if !MEDIA_SUBDRV_AUTOSELECT
-+	help
-+	  Say Y when you want to support this frontend.
-+
- config DVB_AS102_FE
- 	tristate
- 	depends on DVB_CORE
-@@ -829,6 +836,14 @@ config DVB_SP2
- 	help
- 	  CIMaX SP2/SP2HF Common Interface module.
- 
-+config DVB_SILG
-+	tristate "SILG SiLabs + LG Dual Demodulator"
-+	depends on DVB_CORE && I2C
-+	default m if !MEDIA_SUBDRV_AUTOSELECT
-+	help
-+	  A DVB-T/T2/C + ATSC demodulator module. Say Y when
-+	  you want to support this frontend.
-+
- config DVB_LGS8GL5
- 	tristate "Silicon Legend LGS-8GL5 demodulator (OFDM)"
- 	depends on DVB_CORE && I2C
---- linux-4.15/drivers/media/dvb-frontends/Makefile.0140~	2018-02-12 11:32:52.007576605 +0100
-+++ linux-4.15/drivers/media/dvb-frontends/Makefile	2018-02-12 11:32:52.760582121 +0100
-@@ -87,6 +87,7 @@ obj-$(CONFIG_DVB_CX24117) += cx24117.o
- obj-$(CONFIG_DVB_CX24120) += cx24120.o
- obj-$(CONFIG_DVB_SI21XX) += si21xx.o
- obj-$(CONFIG_DVB_SI2168) += si2168.o
-+obj-$(CONFIG_DVB_SI2168B) += si2168b.o
- obj-$(CONFIG_DVB_STV0288) += stv0288.o
- obj-$(CONFIG_DVB_STB6000) += stb6000.o
- obj-$(CONFIG_DVB_S921) += s921.o
-@@ -129,3 +130,4 @@ obj-$(CONFIG_DVB_HORUS3A) += horus3a.o
- obj-$(CONFIG_DVB_ASCOT2E) += ascot2e.o
- obj-$(CONFIG_DVB_HELENE) += helene.o
- obj-$(CONFIG_DVB_ZD1301_DEMOD) += zd1301_demod.o
-+obj-$(CONFIG_DVB_SILG) += silg.o
---- linux-4.15/drivers/media/dvb-frontends/si2168b.c.0140~	2018-02-12 11:32:52.764582151 +0100
-+++ linux-4.15/drivers/media/dvb-frontends/si2168b.c	2018-02-12 11:32:52.764582151 +0100
-@@ -0,0 +1,6900 @@
-+/* DVB compliant Linux driver for the DVB-T/T2/C Si2168B demodulator
-+*
-+* Copyright (C) 2015 PCTV Systems S.à r.l & Silicon Laboratories Inc.
-+*
-+*/
-+
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/string.h>
-+#include <linux/slab.h>
-+#include <linux/jiffies.h>
-+#include <asm/div64.h>
-+
-+#include "dvb_frontend.h"
-+#include "si2168b_priv.h"
-+#include "silabs_tercab.h"
-+
-+static int sidebug = 0;
-+module_param_named(debug, sidebug, int, 0644);
-+
-+int _sitrace = 0;
-+module_param_named(sitrace, _sitrace, int, 0644);
-+
-+int mutex_on = 1;
-+module_param_named(mutex, mutex_on, int, 0644);
-+
-+/* #define __MCNS__ */
-+
-+#define siprintk(args...) \
-+	do { \
-+		if (sidebug) \
-+			printk(KERN_DEBUG "Si2168B: " args); \
-+	} while (0)
-+
-+static inline void _mutex_lock(struct mutex *lock)
-+{
-+	if (mutex_on) {
-+		mutex_lock(lock);
-+	}
-+}
-+
-+static inline void _mutex_unlock(struct mutex *lock)
-+{
-+	if (mutex_on) {
-+		mutex_unlock(lock);
-+	}
-+}
-+
-+/* names of the delivery systems for debugging purposes only */
-+static char *delsys_name(enum fe_delivery_system delsys)
-+{
-+	switch (delsys)	{
-+	case SYS_UNDEFINED    : {return (char*)"SYS_UNDEFINED"   ;}
-+	case SYS_DVBC_ANNEX_A : {return (char*)"SYS_DVBC_ANNEX_A";}
-+	case SYS_DVBC_ANNEX_B : {return (char*)"SYS_DVBC_ANNEX_B";}
-+	case SYS_DVBT         : {return (char*)"SYS_DVBT"        ;}
-+	case SYS_DSS          : {return (char*)"SYS_DSS"         ;}
-+	case SYS_DVBS         : {return (char*)"SYS_DVBS"        ;}
-+	case SYS_DVBS2        : {return (char*)"SYS_DVBS2"       ;}
-+	case SYS_DVBH         : {return (char*)"SYS_DVBH"        ;}
-+	case SYS_ISDBT        : {return (char*)"SYS_ISDBT"       ;}
-+	case SYS_ISDBS        : {return (char*)"SYS_ISDBS"       ;}
-+	case SYS_ISDBC        : {return (char*)"SYS_ISDBC"       ;}
-+	case SYS_ATSC         : {return (char*)"SYS_ATSC"        ;}
-+	case SYS_ATSCMH       : {return (char*)"SYS_ATSCMH"      ;}
-+	case SYS_DTMB         : {return (char*)"SYS_DTMB"        ;}
-+	case SYS_CMMB         : {return (char*)"SYS_CMMB"        ;}
-+	case SYS_DAB          : {return (char*)"SYS_DAB"         ;}
-+	case SYS_DVBT2        : {return (char*)"SYS_DVBT2"       ;}
-+	case SYS_TURBO        : {return (char*)"SYS_TURBO"       ;}
-+	case SYS_DVBC_ANNEX_C : {return (char*)"SYS_DVBC_ANNEX_C";}
-+    default:
-+    	break;
-+	}
-+	return (char*)"* UNKNOWN *";
-+}
-+
-+typedef enum custom_ts_mode_enum {
-+	SILABS_TS_TRISTATE = 0,
-+	SILABS_TS_SERIAL = 1,
-+	SILABS_TS_PARALLEL = 2,
-+	SILABS_TS_GPIF = 3,
-+	SILABS_TS_OFF = 4
-+} custom_ts_mode_enum;
-+
-+/* Standard code values used by the top-level application               */
-+/* <porting> set these values to match the top-level application values */
-+typedef enum custom_standard_enum {
-+	SILABS_ANALOG = 4,
-+	SILABS_DVB_T = 0,
-+	SILABS_DVB_C = 1,
-+	SILABS_DVB_S = 2,
-+	SILABS_DVB_S2 = 3,
-+	SILABS_DVB_T2 = 5,
-+	SILABS_DSS = 6,
-+	SILABS_MCNS = 7,
-+	SILABS_DVB_C2 = 8,
-+	SILABS_SLEEP = 100
-+} custom_standard_enum;
-+
-+typedef enum custom_constel_enum {
-+	SILABS_QAMAUTO = -1,
-+	SILABS_QAM16 = 0,
-+	SILABS_QAM32 = 1,
-+	SILABS_QAM64 = 2,
-+	SILABS_QAM128 = 3,
-+	SILABS_QAM256 = 4,
-+	SILABS_QPSK = 5,
-+	SILABS_8PSK = 6,
-+	SILABS_QAM1024 = 7,
-+	SILABS_QAM4096 = 8
-+} custom_constel_enum;
-+
-+typedef enum custom_stream_enum {
-+	SILABS_HP = 0,
-+	SILABS_LP = 1
-+} custom_stream_enum;
-+
-+typedef enum custom_t2_plp_type {
-+	SILABS_PLP_TYPE_COMMON = 0,
-+	SILABS_PLP_TYPE_DATA_TYPE1 = 1,
-+	SILABS_PLP_TYPE_DATA_TYPE2 = 2
-+} custom_t2_plp_type;
-+
-+typedef enum custom_hierarchy_enum {
-+	SILABS_HIERARCHY_NONE = 0,
-+	SILABS_HIERARCHY_ALFA1 = 1,
-+	SILABS_HIERARCHY_ALFA2 = 2,
-+	SILABS_HIERARCHY_ALFA4 = 3
-+} custom_hierarchy_enum;
-+
-+/************************************************************************************************************************
-+  system_time function
-+  Use:        current system time retrieval function
-+              Used to retrieve the current system time in milliseconds
-+  Returns:    The current system time in milliseconds
-+  Porting:    Needs to use the final system call
-+************************************************************************************************************************/
-+static inline u32 system_time(void)
-+{
-+  /* <porting> Replace 'clock' by whatever is necessary to return the system time in milliseconds */
-+  /* return (int)clock()*1000/CLOCKS_PER_SEC; */
-+  return (u32)jiffies_to_msecs(jiffies);
-+}
-+
-+#ifdef SiTRACES
-+#define SiTRACES_BUFFER_LENGTH  100000
-+#define SiTRACES_NAMESIZE           30
-+#define SiTRACES_FUNCTION_NAMESIZE  30
-+
-+#define CUSTOM_PRINTF(args...) \
-+	do { \
-+		if (_sitrace) \
-+			printk(KERN_INFO "si2168b: " args); \
-+	} while (0)
-+
-+typedef enum TYPE_OF_OUTPUT {
-+    TRACE_NONE = 0,
-+    TRACE_STDOUT,
-+    TRACE_EXTERN_FILE,
-+    TRACE_MEMORY
-+} TYPE_OF_OUTPUT;
-+
-+static TYPE_OF_OUTPUT trace_output_type;
-+
-+static u8  trace_init_done        = 0;
-+static u8  trace_suspend          = 0;
-+static u8  trace_config_lines     = 0;
-+static u8  trace_config_functions = 0;
-+static u8  trace_config_time      = 0;
-+static u8  trace_config_verbose   = 0;
-+static u32 trace_linenumber       = 0;
-+
-+static char trace_timer[50];
-+static char trace_elapsed_time[20];
-+static char trace_source_function[SiTRACES_FUNCTION_NAMESIZE+1];
-+static u8 trace_skip_info = 0;
-+
-+/************************************************************************************************************************
-+  traceElapsedTime function
-+  Use:        SiTRACES time formatting function.
-+              It allows the user to know when the trace has been treated.
-+              It is used to insert the time before the trace when -time 'on'.
-+  Returns:    text containing the execution time in HH:MM:SS.ms format.
-+  Porting:    Not compiled if SiTRACES is not defined in Silabs_L0_API.h.
-+ ************************************************************************************************************************/
-+static char *get_elapsed_time(void)
-+{
-+	u32 time_elapsed, ms, sec, min, hours;
-+
-+	time_elapsed = system_time();
-+	ms = time_elapsed % 1000;
-+	time_elapsed = time_elapsed/1000;
-+	sec = time_elapsed % 60;
-+	time_elapsed = time_elapsed/60;
-+	min = time_elapsed % 60;
-+	time_elapsed = time_elapsed/60;
-+	hours = time_elapsed % 60;
-+	sprintf(trace_elapsed_time, "%02u:%02u:%02u.%03u ", hours, min, sec, ms);
-+
-+	return trace_elapsed_time;
-+}
-+
-+/************************************************************************************************************************
-+  traceToStdout function
-+  Use:        SiTRACES stdout display function.
-+              It displays the current trace in the command window.
-+              It adds file name, line number,function name and time if selected.
-+  Parameter:  trace
-+  Returns:    void
-+ ************************************************************************************************************************/
-+static void trace_to_stdout(char* trace)
-+{
-+	if (!trace_skip_info) {
-+		if (trace_config_lines) {
-+			CUSTOM_PRINTF("%5u "  , trace_linenumber);
-+		}
-+		if (trace_config_functions) {
-+			CUSTOM_PRINTF("%-30s ", trace_source_function);
-+		}
-+	}
-+	if (trace_config_time) {
-+		CUSTOM_PRINTF("%s ", get_elapsed_time());
-+	}
-+	CUSTOM_PRINTF("%s", trace);
-+}
-+
-+/************************************************************************************************************************
-+  traceToDestination function
-+  Use:        switch the trace in the selected output mode.
-+  Comment:    In verbose mode, the trace is always displayed in stdout.
-+  Parameter:  trace, the trace string
-+  Returns:    void
-+  Porting:    Not compiled if SiTRACES is not defined in Silabs_L0_API.h.
-+************************************************************************************************************************/
-+static void trace_to_destination(char* trace)
-+{
-+	int last;
-+
-+	if (trace_suspend) {
-+		return;
-+	}
-+	/* If trace is a single CrLf, do not print the file/line/function info           */
-+	if (strcmp(trace,"\n")==0) {
-+		trace_skip_info = 1;
-+	}
-+	/* If file/line/function info printed, make sure there is a CrLf after each line */
-+	if (trace_config_lines + trace_config_functions + trace_config_time) {
-+		last = (int)strlen(trace)-1;
-+		if (trace[last] != 0x0a) {
-+			sprintf(trace, "%s\n", trace);
-+		}
-+	}
-+	trace_to_stdout(trace);
-+	if ((trace_config_verbose) & (trace_output_type!=TRACE_STDOUT)) {
-+		trace_to_stdout(trace);
-+	}
-+	if (strcmp(trace,"\n")==0) {
-+		trace_skip_info = 0;
-+	}
-+}
-+
-+/************************************************************************************************************************
-+  SiTraceFunction function
-+  Use:        SiTRACES trace formatting function.
-+              It formats the trace message with file name and line number and time if selected
-+              then saves it to the trace output.
-+  Parameter:  name    the file name where the trace is written.
-+  Parameter:  number  the line number where the trace is written.
-+  Parameter:  fmt     string content of trace message. Others arguments are sent thanks to the ellipse.
-+  Returns:    void
-+  Porting:    Not compiled if SiTRACES is not defined in Silabs_L0_API.h.
-+************************************************************************************************************************/
-+static void sitrace_function(const char *name, int number, const char *func, const char *fmt, ...)
-+{
-+	char message[850];
-+	const char *pfunc;
-+	va_list ap;
-+
-+	if (trace_output_type == TRACE_NONE)
-+		return;
-+
-+	/* print the line number in trace_linenumber */
-+	trace_linenumber = number;
-+
-+	/*print the function name in trace_source_function */
-+	pfunc = func;
-+	sprintf(trace_source_function, "%s", "");
-+	if (strlen(pfunc) > SiTRACES_FUNCTION_NAMESIZE) {
-+		pfunc += (strlen(pfunc) - SiTRACES_FUNCTION_NAMESIZE) + 2;
-+		strcpy(trace_source_function, "..");
-+	}
-+	strncat(trace_source_function, pfunc, SiTRACES_FUNCTION_NAMESIZE-2);
-+
-+	va_start(ap, fmt);
-+	vsnprintf(message, 900, fmt, ap);
-+	trace_to_destination(message);
-+	va_end(ap);
-+}
-+
-+/************************************************************************************************************************
-+  SiTraceDefaultConfiguration function
-+  Use:        SiTRACES initialization function.
-+              It is called on the first call to L0_Init (only once).
-+              It defines the default output and inserts date and time in the default file.
-+  Returns:    void
-+  Porting:    Not compiled if SiTRACES is not defined in Silabs_L0_API.h.
-+************************************************************************************************************************/
-+static void sitrace_default_configuration(void)
-+{
-+    if (trace_init_done)
-+    	return;
-+
-+    trace_output_type = TRACE_STDOUT;
-+    trace_init_done = 1;
-+    sprintf(trace_timer, "time");
-+}
-+
-+static inline void sitraces_suspend(void)
-+{
-+	trace_suspend = 1;
-+}
-+
-+static inline void sitraces_resume(void)
-+{
-+	trace_suspend = 0;
-+}
-+
-+/***********************************************************************************************************************
-+  si2168b_error_text function
-+  Use:        Error information function
-+              Used to retrieve a text based on an error code
-+  Returns:    the error text
-+  Parameter:  error_code the error code.
-+  Porting:    Useful for application development for debug purposes.
-+  Porting:    May not be required for the final application, can be removed if not used.
-+ ***********************************************************************************************************************/
-+static char* si2168b_error_text(int error_code)
-+{
-+	switch (error_code) {
-+	case NO_Si2168B_ERROR                     : return (char *)"No Si2168B error";
-+	case ERROR_Si2168B_ALLOCATING_CONTEXT     : return (char *)"Error while allocating Si2168B context";
-+	case ERROR_Si2168B_PARAMETER_OUT_OF_RANGE : return (char *)"Si2168B parameter(s) out of range";
-+	case ERROR_Si2168B_SENDING_COMMAND        : return (char *)"Error while sending Si2168B command";
-+	case ERROR_Si2168B_CTS_TIMEOUT            : return (char *)"Si2168B CTS timeout";
-+	case ERROR_Si2168B_ERR                    : return (char *)"Si2168B Error (status 'err' bit 1)";
-+	case ERROR_Si2168B_POLLING_CTS            : return (char *)"Si2168B Error while polling CTS";
-+	case ERROR_Si2168B_POLLING_RESPONSE       : return (char *)"Si2168B Error while polling response";
-+	case ERROR_Si2168B_LOADING_FIRMWARE       : return (char *)"Si2168B Error while loading firmware";
-+	case ERROR_Si2168B_LOADING_BOOTBLOCK      : return (char *)"Si2168B Error while loading bootblock";
-+	case ERROR_Si2168B_STARTING_FIRMWARE      : return (char *)"Si2168B Error while starting firmware";
-+	case ERROR_Si2168B_SW_RESET               : return (char *)"Si2168B Error during software reset";
-+	case ERROR_Si2168B_INCOMPATIBLE_PART      : return (char *)"Si2168B Error Incompatible part";
-+	case ERROR_Si2168B_UNKNOWN_COMMAND        : return (char *)"Si2168B Error unknown command";
-+	case ERROR_Si2168B_UNKNOWN_PROPERTY       : return (char *)"Si2168B Error unknown property";
-+	default:
-+		return (char *)"Unknown Si2168B error code";
-+	}
-+}
-+
-+/************************************************************************************************************************
-+  NAME: si2168b_trace_scan_status
-+  DESCRIPTION: traces the scan_status
-+  Parameter:  Pointer to Si2168B Context
-+  Returns:    void
-+************************************************************************************************************************/
-+static const char *si2168b_trace_scan_status(int scan_status)
-+{
-+	switch (scan_status) {
-+	case  Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_ANALOG_CHANNEL_FOUND  : { return "ANALOG  CHANNEL_FOUND"; break; }
-+	case  Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_DIGITAL_CHANNEL_FOUND : { return "DIGITAL CHANNEL_FOUND"; break; }
-+	case  Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_DEBUG                 : { return "DEBUG"                ; break; }
-+	case  Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_ERROR                 : { return "ERROR"                ; break; }
-+	case  Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_ENDED                 : { return "ENDED"                ; break; }
-+	case  Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_IDLE                  : { return "IDLE"                 ; break; }
-+	case  Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_SEARCHING             : { return "SEARCHING"            ; break; }
-+	case  Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_TUNE_REQUEST          : { return "TUNE_REQUEST"         ; break; }
-+	default                                                              : { return "Unknown!"             ; break; }
-+	}
-+}
-+
-+/***********************************************************************************************************************
-+  si2168b_tag_text function
-+  Use:        Error information function
-+              Used to retrieve a text containing the TAG information (related to the code version)
-+  Returns:    the TAG text
-+  Porting:    May not be required for the final application, can be removed if not used.
-+ ***********************************************************************************************************************/
-+char* si2168b_tag_text(void)
-+{
-+	return (char *)"V0.2.6";
-+}
-+
-+#else /* SiTRACES */
-+#define SiTRACE(...)               /* empty */
-+#define SiTracesSuspend()          /* empty */
-+#define SiTracesResume()           /* empty */
-+#endif /* SiTRACES */
-+
-+static const struct dvb_frontend_ops si2168b_ops;
-+
-+static int enable_tuner_i2c(void *p)
-+{
-+	/* nothing to do */
-+	return NO_Si2168B_ERROR;
-+}
-+
-+static int disable_tuner_i2c(void *p)
-+{
-+	/* nothing to do */
-+	return NO_Si2168B_ERROR;
-+}
-+
-+static int i2c_callback(void *p)
-+{
-+	/* nothing to do */
-+	return NO_Si2168B_ERROR;
-+}
-+
-+/************************************************************************************************************************
-+  L0_ReadBytes function
-+  Use:        lowest layer read function
-+              Used to read a given number of bytes from the Layer 1 instance.
-+  Parameters: i2c, a pointer to the Layer 0 context.
-+              iI2CIndex, the index of the first byte to read.
-+              iNbBytes, the number of bytes to read.
-+              *pbtDataBuffer, a pointer to a buffer used to store the bytes.
-+  Returns:    the number of bytes read.
-+  Porting:    If a single connection mode is allowed, the entire switch can be replaced by a call to the final i2c read function
-+************************************************************************************************************************/
-+static u16 i2c_read_bytes(struct i2c_adapter *i2c_adap, u8 i2c_addr, u16 iNbBytes, u8 *pucDataBuffer)
-+{
-+	struct i2c_msg msg = {
-+			.addr  = i2c_addr,
-+			.flags = I2C_M_RD,
-+			.buf   = pucDataBuffer,
-+			.len   = iNbBytes,
-+	};
-+
-+	if (i2c_adap == NULL) {
-+		SiTRACE("%s(): FATAL ERROR: i2c_adap is undefined!\n", __func__);
-+		return 0;
-+	}
-+
-+	if (i2c_transfer(i2c_adap, &msg, 1) != 1) {
-+		SiTRACE("%s(): i2c transfer failed\n", __func__);
-+		return 0;
-+	}
-+
-+	return iNbBytes;
-+}
-+
-+/************************************************************************************************************************
-+  i2c_write_bytes function
-+  Use:        lowest layer write function
-+              Used to write a given number of bytes from the Layer 1 instance.
-+  Parameters: i2c, a pointer to the Layer 0 context.
-+              iNbBytes, the number of bytes to write.
-+              *pbtDataBuffer, a pointer to a buffer containing the bytes to write.
-+  Returns:    the number of bytes read.
-+  Porting:    If a single connection mode is allowed, the entire switch can be replaced by a call to the final i2c write function
-+************************************************************************************************************************/
-+static int i2c_write_bytes(struct i2c_adapter *i2c_adap, u8 i2c_addr, u16 iNbBytes, u8 *pucDataBuffer)
-+{
-+	struct i2c_msg msg = {
-+			.addr  = i2c_addr,
-+			.flags = 0,
-+			.buf   = pucDataBuffer,
-+			.len   = iNbBytes,
-+	};
-+
-+	if (i2c_adap == NULL) {
-+		SiTRACE("%s(): FATAL ERROR: i2c_adap is undefined!\n", __func__);
-+		return 0;
-+	}
-+
-+	if (iNbBytes > 64) {
-+		SiTRACE("%s(): numbers of bytes (%u) exceeds limit of 64\n", __func__, iNbBytes);
-+		return 0;
-+	}
-+
-+	if (i2c_transfer(i2c_adap, &msg, 1) != 1) {
-+		SiTRACE("%s(): i2c transfer failed\n", __func__);
-+		return 0;
-+	}
-+
-+	return iNbBytes;
-+}
-+
-+/***********************************************************************************************************************
-+  si2168b_current_response_status function
-+  Use:        status checking function
-+              Used to fill the Si2168B_COMMON_REPLY_struct members with the ptDataBuffer byte's bits
-+  Comments:   The status byte definition being identical for all commands,
-+              using this function to fill the status structure helps reducing the code size
-+  Parameter: ptDataBuffer  a single byte received when reading a command's response (the first byte)
-+  Returns:   0 if the err bit (bit 6) is unset, 1 otherwise
-+ ***********************************************************************************************************************/
-+static u8 si2168b_current_response_status(si2168b_context *ctx, u8 databuffer)
-+{
-+	ctx->status_ddint   = ((databuffer >> 0 ) & 0x01);
-+	ctx->status_scanint = ((databuffer >> 1 ) & 0x01);
-+	ctx->status_err     = ((databuffer >> 6 ) & 0x01);
-+	ctx->status_cts     = ((databuffer >> 7 ) & 0x01);
-+
-+	return (ctx->status_err ? ERROR_Si2168B_ERR : NO_Si2168B_ERROR);
-+}
-+
-+/***********************************************************************************************************************
-+  si2168b_poll_for_response function
-+  Use:        command response retrieval function
-+              Used to retrieve the command response in the provided buffer
-+  Comments:   The status byte definition being identical for all commands,
-+              using this function to fill the status structure helps reducing the code size
-+              max timeout = 1000 ms
-+
-+  Parameter:  nbBytes          the number of response bytes to read
-+  Parameter:  pByteBuffer      a buffer into which bytes will be stored
-+  Returns:    0 if no error, an error code otherwise
-+ ***********************************************************************************************************************/
-+static u8 si2168b_poll_for_response(si2168b_context *ctx, u16 count, u8 *buffer)
-+{
-+	u8 dbg[7];
-+	u32 start_time = system_time();
-+
-+	do {
-+		if (i2c_read_bytes(ctx->i2c_adap, ctx->i2c_addr, count, buffer) != count) {
-+			SiTRACE("%s(): ERROR reading byte 0!\n", __func__);
-+			return ERROR_Si2168B_POLLING_RESPONSE;
-+		}
-+		/* return response err flag if CTS set */
-+		if (buffer[0] & 0x80)  {
-+			/* for debug purpose, read and trace 2 bytes in case the error bit is set */
-+			if (buffer[0] & 0x40)  {
-+				i2c_read_bytes(ctx->i2c_adap, ctx->i2c_addr, 7, &(dbg[0]) );
-+				SiTRACE("Si2168B debug bytes 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", dbg[0], dbg[1], dbg[2], dbg[3], dbg[4], dbg[5], dbg[6]);
-+			}
-+			return si2168b_current_response_status(ctx, buffer[0]);
-+		}
-+		msleep(10); /* FGR - pause a bit rather than just spinning on I2C */
-+	} while (system_time() - start_time < 1000); /* wait a maximum of 1000ms */
-+
-+	SiTRACE("%s(): ERROR CTS Timeout!\n", __func__);
-+	return ERROR_Si2168B_CTS_TIMEOUT;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_I2C_PASSTHROUGH COMMAND                  */
-+/*---------------------------------------------------*/
-+static u8 si2168b_i2c_passthrough(si2168b_context *ctx,
-+		u8 subcode,
-+		u8 i2c_passthru,
-+		u8 reserved)
-+{
-+	u8 cmdByteBuffer[3];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	/*ctx->rsp->i2c_passthrough.STATUS = ctx->status;*/
-+
-+	SiTRACE("%s()\n", __func__);
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_I2C_PASSTHROUGH_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( subcode      & Si2168B_I2C_PASSTHROUGH_CMD_SUBCODE_MASK      ) << Si2168B_I2C_PASSTHROUGH_CMD_SUBCODE_LSB     );
-+	cmdByteBuffer[2] = (u8) ( ( i2c_passthru & Si2168B_I2C_PASSTHROUGH_CMD_I2C_PASSTHRU_MASK ) << Si2168B_I2C_PASSTHROUGH_CMD_I2C_PASSTHRU_LSB|
-+			( reserved     & Si2168B_I2C_PASSTHROUGH_CMD_RESERVED_MASK     ) << Si2168B_I2C_PASSTHROUGH_CMD_RESERVED_LSB    );
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 3, cmdByteBuffer) != 3) {
-+		SiTRACE("Error writing I2C_PASSTHROUGH bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+	}
-+
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/************************************************************************************************************************
-+  si2168b_tuner_i2c_enable function
-+  Use:        Tuner i2c bus connection
-+              Used to allow communication with the tuners
-+  Parameter:  *front_end, the front-end handle
-+************************************************************************************************************************/
-+static u8 si2168b_tuner_i2c_enable(Si2168B_L2_Context *front_end)
-+{
-+    return si2168b_i2c_passthrough(front_end->demod, Si2168B_I2C_PASSTHROUGH_CMD_SUBCODE_CODE,
-+    		Si2168B_I2C_PASSTHROUGH_CMD_I2C_PASSTHRU_CLOSE, Si2168B_I2C_PASSTHROUGH_CMD_RESERVED_RESERVED);
-+}
-+
-+/************************************************************************************************************************
-+  si2168b_tuner_i2c_disable function
-+  Use:        Tuner i2c bus connection
-+              Used to disconnect i2c communication with the tuners
-+  Parameter:  *front_end, the front-end handle
-+************************************************************************************************************************/
-+static u8 si2168b_tuner_i2c_disable(Si2168B_L2_Context *front_end)
-+{
-+    return si2168b_i2c_passthrough(front_end->demod, Si2168B_I2C_PASSTHROUGH_CMD_SUBCODE_CODE,
-+    		Si2168B_I2C_PASSTHROUGH_CMD_I2C_PASSTHRU_OPEN, Si2168B_I2C_PASSTHROUGH_CMD_RESERVED_RESERVED);
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_SET_PROPERTY COMMAND                     */
-+/*---------------------------------------------------*/
-+static u8 si2168_set_property_cmd(si2168b_context *ctx, u16 prop, u16 data, Si2168B_SET_PROPERTY_CMD_REPLY_struct *set_property)
-+{
-+	const u8 reserved = 0;
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[6];
-+	u8 rspByteBuffer[4];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B SET_PROPERTY\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_SET_PROPERTY_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( reserved & Si2168B_SET_PROPERTY_CMD_RESERVED_MASK ) << Si2168B_SET_PROPERTY_CMD_RESERVED_LSB);
-+	cmdByteBuffer[2] = (u8) ( ( prop     & Si2168B_SET_PROPERTY_CMD_PROP_MASK     ) << Si2168B_SET_PROPERTY_CMD_PROP_LSB    );
-+	cmdByteBuffer[3] = (u8) ((( prop     & Si2168B_SET_PROPERTY_CMD_PROP_MASK     ) << Si2168B_SET_PROPERTY_CMD_PROP_LSB    )>>8);
-+	cmdByteBuffer[4] = (u8) ( ( data     & Si2168B_SET_PROPERTY_CMD_DATA_MASK     ) << Si2168B_SET_PROPERTY_CMD_DATA_LSB    );
-+	cmdByteBuffer[5] = (u8) ((( data     & Si2168B_SET_PROPERTY_CMD_DATA_MASK     ) << Si2168B_SET_PROPERTY_CMD_DATA_LSB    )>>8);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 6, cmdByteBuffer) != 6) {
-+		SiTRACE("Error writing SET_PROPERTY bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 4, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling SET_PROPERTY response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	set_property->reserved =   (( ( (rspByteBuffer[1]  )) >> Si2168B_SET_PROPERTY_RESPONSE_RESERVED_LSB ) & Si2168B_SET_PROPERTY_RESPONSE_RESERVED_MASK );
-+	set_property->data     =   (( ( (rspByteBuffer[2]  ) | (rspByteBuffer[3]  << 8 )) >> Si2168B_SET_PROPERTY_RESPONSE_DATA_LSB     ) & Si2168B_SET_PROPERTY_RESPONSE_DATA_MASK     );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/***********************************************************************************************************************
-+  si2168b_set_property function
-+  Use:        property set function
-+              Used to call L1_SET_PROPERTY with the property Id and data provided.
-+  Parameter: *api     the Si2168B context
-+  Parameter: prop     the property Id
-+  Parameter: data     the property bytes
-+  Behavior:  This function will only download the property if required.
-+               Conditions to download the property are:
-+                - The property changes
-+                - The propertyWriteMode is set to Si2168B_DOWNLOAD_ALWAYS
-+                - The property is unknown to Si2168B_PackProperty (this may be useful for debug purpose)
-+  Returns:    0 if no error, an error code otherwise
-+ ***********************************************************************************************************************/
-+static u8 si2168b_set_property(si2168b_context *ctx, u16 prop_code, u16 data)
-+{
-+	u8  res;
-+	Si2168B_SET_PROPERTY_CMD_REPLY_struct set_property;
-+
-+	res = si2168_set_property_cmd(ctx, prop_code, data, &set_property);
-+	SiTRACE("si2168b_set_property: Setting Property 0x%04x to 0x%04x(%d)\n", prop_code, data, data);
-+	if (res != NO_Si2168B_ERROR) {
-+		SiTRACE("ERROR: si2168b_set_property: %s 0x%04x!\n\n", si2168b_error_text(res), prop_code);
-+	}
-+	return res;
-+}
-+
-+/************************************************************************************************************************
-+ si2168b_set_ts_mode function
-+ Use:      Transport Stream control function
-+ Used to switch the TS output in the desired mode
-+ Parameter: mode the mode to switch to,
-+ clock mode
-+ ************************************************************************************************************************/
-+static u8 si2168b_set_ts_mode(struct Si2168B_Priv *priv, u8 ts_bus_mode)
-+{
-+	si2168b_context *demod = priv->si_front_end->demod;
-+
-+	const u8 ts_clk_invert              = priv->config->ts_par_clk_invert;
-+	const u8 ts_clk_shift               = priv->config->ts_par_clk_shift;
-+	const u8 ts_mode_clk_gapped_en      = priv->config->clk_gapped_en; /* (default 'DISABLED') */
-+	const u8 ts_mode_clock              = priv->config->ts_clock_mode; /* (default 'AUTO_FIXED') */
-+	const u8 ts_data_strength           = 3; /* (default     3) */
-+	const u8 ts_clk_strength            = 3; /* (default     3) */
-+	const u8 ts_parallel_data_shape     = 2;
-+	const u8 ts_parallel_clk_shape      = 2;
-+	const u8 ts_gpif_data_shape         = 7;
-+	const u8 ts_gpif_clk_shape          = 7;
-+	const u8 ts_mode_special            = Si2168B_DD_TS_MODE_PROP_SPECIAL_FULL_TS;              /* (default 'FULL_TS') */
-+	const u8 ts_mode_ts_err_polarity    = Si2168B_DD_TS_MODE_PROP_TS_ERR_POLARITY_NOT_INVERTED; /* (default 'NOT_INVERTED') */
-+	const u8 ts_mode_ts_freq_resolution = Si2168B_DD_TS_MODE_PROP_TS_FREQ_RESOLUTION_NORMAL;    /* (default 'NORMAL') */
-+
-+	u8  ts_mode_mode = Si2168B_DD_TS_MODE_PROP_MODE_TRISTATE; /* (default 'TRISTATE') */
-+	u8  ret = NO_Si2168B_ERROR;
-+	u16 data;
-+
-+	siprintk("%s() ts_bus_mode=%u\n", __func__, ts_bus_mode);
-+
-+	switch (ts_bus_mode) {
-+	case SILABS_TS_SERIAL:
-+		ts_mode_mode = Si2168B_DD_TS_MODE_PROP_MODE_SERIAL;
-+		break;
-+	case SILABS_TS_PARALLEL:
-+	    data = (ts_data_strength       & Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_STRENGTH_MASK) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_STRENGTH_LSB  |
-+	           (ts_parallel_data_shape & Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_SHAPE_MASK   ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_SHAPE_LSB  |
-+	           (ts_clk_strength        & Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_STRENGTH_MASK ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_STRENGTH_LSB  |
-+	           (ts_parallel_clk_shape  & Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHAPE_MASK    ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHAPE_LSB  |
-+	           (ts_clk_invert          & Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_INVERT_MASK   ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_INVERT_LSB  |
-+	           (ts_clk_shift           & Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHIFT_MASK    ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHIFT_LSB;
-+        ret = si2168b_set_property(demod, Si2168B_DD_TS_SETUP_PAR_PROP, data);
-+		ts_mode_mode = Si2168B_DD_TS_MODE_PROP_MODE_PARALLEL;
-+		break;
-+	case SILABS_TS_TRISTATE:
-+		ts_mode_mode = Si2168B_DD_TS_MODE_PROP_MODE_TRISTATE;
-+		break;
-+	case SILABS_TS_OFF:
-+		ts_mode_mode = Si2168B_DD_TS_MODE_PROP_MODE_OFF;
-+		break;
-+	case SILABS_TS_GPIF:
-+	    data = (ts_data_strength   & Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_STRENGTH_MASK) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_STRENGTH_LSB  |
-+	           (ts_gpif_data_shape & Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_SHAPE_MASK   ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_SHAPE_LSB  |
-+	           (ts_clk_strength    & Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_STRENGTH_MASK ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_STRENGTH_LSB  |
-+	           (ts_gpif_clk_shape  & Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHAPE_MASK    ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHAPE_LSB  |
-+	           (ts_clk_invert      & Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_INVERT_MASK   ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_INVERT_LSB  |
-+	           (ts_clk_shift       & Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHIFT_MASK    ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHIFT_LSB;
-+		ret = si2168b_set_property(demod, Si2168B_DD_TS_SETUP_PAR_PROP, data);
-+		ts_mode_mode = Si2168B_DD_TS_MODE_PROP_MODE_GPIF;
-+		break;
-+	default:
-+		/* return si2168b_set_ts_mode(priv, SILABS_TS_TRISTATE); */
-+		ts_mode_mode = Si2168B_DD_TS_MODE_PROP_MODE_TRISTATE;
-+		break;
-+	}
-+
-+	if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): si2168b_set_property(Si2168B_DD_TS_SETUP_PAR_PROP) failed\n", __func__);
-+	}
-+
-+    data = (ts_mode_mode               & Si2168B_DD_TS_MODE_PROP_MODE_MASK              ) << Si2168B_DD_TS_MODE_PROP_MODE_LSB  |
-+           (ts_mode_clock              & Si2168B_DD_TS_MODE_PROP_CLOCK_MASK             ) << Si2168B_DD_TS_MODE_PROP_CLOCK_LSB  |
-+           (ts_mode_clk_gapped_en      & Si2168B_DD_TS_MODE_PROP_CLK_GAPPED_EN_MASK     ) << Si2168B_DD_TS_MODE_PROP_CLK_GAPPED_EN_LSB  |
-+           (ts_mode_ts_err_polarity    & Si2168B_DD_TS_MODE_PROP_TS_ERR_POLARITY_MASK   ) << Si2168B_DD_TS_MODE_PROP_TS_ERR_POLARITY_LSB  |
-+           (ts_mode_special            & Si2168B_DD_TS_MODE_PROP_SPECIAL_MASK           ) << Si2168B_DD_TS_MODE_PROP_SPECIAL_LSB  |
-+           (ts_mode_ts_freq_resolution & Si2168B_DD_TS_MODE_PROP_TS_FREQ_RESOLUTION_MASK) << Si2168B_DD_TS_MODE_PROP_TS_FREQ_RESOLUTION_LSB;
-+    ret = si2168b_set_property(demod, Si2168B_DD_TS_MODE_PROP, data);
-+
-+	if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): si2168b_set_property(Si2168B_DD_TS_MODE_PROP) failed\n", __func__);
-+	}
-+	siprintk("%s() DONE (ret=%d)\n", __func__, ret);
-+	return ret;
-+}
-+
-+static int si2168b_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+
-+	siprintk("%s() enable=%d\n", __func__, enable);
-+
-+	if (enable) {
-+		if ( priv->config->indirect_i2c_connection ) { /* INDIRECT_I2C_CONNECTION? */
-+			if (priv->si_front_end->f_TER_tuner_enable(priv->si_front_end->callback) != NO_Si2168B_ERROR) {
-+				siprintk("%s(): f_TER_tuner_enable() failed\n", __func__);
-+				return -EIO;
-+			}
-+		} else {
-+			if (si2168b_tuner_i2c_enable(priv->si_front_end) != NO_Si2168B_ERROR) {
-+				siprintk("%s(): si2168b_tuner_i2c_enable() failed\n", __func__);
-+				return -EIO;
-+			}
-+		}
-+	} else {
-+		if ( priv->config->indirect_i2c_connection ) { /* INDIRECT_I2C_CONNECTION? */
-+			if (priv->si_front_end->f_TER_tuner_disable(priv->si_front_end->callback) != NO_Si2168B_ERROR) {
-+				siprintk("%s(): f_TER_tuner_disable() failed\n", __func__);
-+				return -EIO;
-+			}
-+		} else {
-+			if (si2168b_tuner_i2c_disable(priv->si_front_end) != NO_Si2168B_ERROR) {
-+				siprintk("%s(): si2168b_tuner_i2c_disable() failed\n", __func__);
-+				return -EIO;
-+			}
-+		}
-+	}
-+	siprintk("%s() I2C gate on Si2168B %sabled\n", __func__, enable ? "en" : "dis");
-+	return 0;
-+}
-+
-+/************************************************************************************************************************
-+  si2168b_infos function
-+  Use:        software information function
-+              Used to retrieve information about the compilation
-+  Parameter:  front_end, a pointer to the Si2168B_L2_Context context to be initialized
-+  Parameter:  infoString, a text buffer to be filled with teh information. It must be initialized by the caller.
-+  Return:     the length of the information string
-+************************************************************************************************************************/
-+static int si2168b_infos(Si2168B_L2_Context *front_end, char *infoString_UNUSED)
-+{
-+	if (infoString_UNUSED == NULL)
-+		return 0;
-+
-+	if (front_end == NULL) {
-+		SiTRACE("Si2168B front-end not initialized yet. Call si2168b_sw_init first!\n");
-+		return strlen(infoString_UNUSED);
-+	}
-+
-+	SiTRACE("\n");
-+	SiTRACE("--------------------------------------\n");
-+	SiTRACE("Demod                Si2168B  at 0x%02x\n", front_end->demod->i2c_addr);
-+	SiTRACE("Demod                Source code %s\n", si2168b_tag_text() );
-+	SiTRACE("Terrestrial tuner    SiLabs\n");
-+
-+	if ( front_end->demod->tuner_ter_clock_source == Si2168B_TER_Tuner_clock)
-+		SiTRACE("TER clock from  TER Tuner (%d MHz)\n", front_end->demod->tuner_ter_clock_freq);
-+	if ( front_end->demod->tuner_ter_clock_source == Si2168B_SAT_Tuner_clock)
-+		SiTRACE("TER clock from  SAT Tuner (%d MHz)\n", front_end->demod->tuner_ter_clock_freq);
-+	if ( front_end->demod->tuner_ter_clock_source == Si2168B_Xtal_clock)
-+		SiTRACE("TER clock from  Xtal      (%d MHz)\n", front_end->demod->tuner_ter_clock_freq);
-+	if ( front_end->demod->tuner_ter_clock_input == Si2168B_START_CLK_CMD_CLK_MODE_CLK_CLKIO)
-+		SiTRACE("TER clock input CLKIO\n");
-+	if ( front_end->demod->tuner_ter_clock_input == Si2168B_START_CLK_CMD_CLK_MODE_CLK_XTAL_IN)
-+		SiTRACE("TER clock input XTAL_IN\n");
-+	if ( front_end->demod->tuner_ter_clock_input == Si2168B_START_CLK_CMD_CLK_MODE_XTAL)
-+		SiTRACE("TER clock input XTAL\n");
-+
-+	if (front_end->demod->fef_mode == Si2168B_FEF_MODE_SLOW_NORMAL_AGC)
-+		SiTRACE("FEF mode 'SLOW NORMAL AGC'\n");
-+	if (front_end->demod->fef_mode == Si2168B_FEF_MODE_SLOW_INITIAL_AGC)
-+		SiTRACE("FEF mode 'SLOW INITIAL AGC'\n");
-+	if (front_end->demod->fef_mode == Si2168B_FEF_MODE_FREEZE_PIN)
-+		SiTRACE("FEF mode 'FREEZE PIN'\n");
-+	if (front_end->demod->fef_mode != front_end->demod->fef_selection)
-+		SiTRACE("(CHANGED!)\n");
-+
-+	SiTRACE("--------------------------------------\n");
-+	return strlen(infoString_UNUSED);
-+}
-+
-+/***********************************************************************************************************************
-+  Si2168B_L1_API_Init function
-+  Use:        software initialisation function
-+              Used to initialize the software context
-+  Returns:    0 if no error
-+  Comments:   It should be called first and once only when starting the application
-+  Parameter:   **ppapi         a pointer to the api context to initialize
-+  Parameter:  add            the Si2168B I2C address
-+  Porting:    Allocation errors need to be properly managed.
-+  Porting:    I2C initialization needs to be adapted to use the available I2C functions
-+ ***********************************************************************************************************************/
-+static u8 si2168b_ctx_init(si2168b_context *ctx, u8 addr, struct i2c_adapter *i2c_adap, const struct si2168b_config *config)
-+{
-+	mutex_init(&ctx->lock);
-+	mutex_init(&ctx->ts_bus_ctrl_lock);
-+	ctx->i2c_addr = addr;
-+	ctx->i2c_adap = i2c_adap;
-+	ctx->address  = addr;
-+
-+#ifdef SiTRACES
-+	if (!trace_init_done) {
-+		CUSTOM_PRINTF("********** SiTRACES activated *********\n");
-+		CUSTOM_PRINTF("Comment the '#define SiTRACES' line\n");
-+		CUSTOM_PRINTF("in Silabs_L0_API.h to de-activate all traces.\n");
-+		CUSTOM_PRINTF("***************************************\n");
-+		sitrace_default_configuration();
-+	}
-+#endif /* SiTRACES */
-+
-+	/* Clock settings as per compilation flags                     */
-+	/*  For multi-frontend HW, these may be adapted later on,      */
-+	/*   using Si2168B_L1_API_TER_Clock and Si2168B_L1_API_SAT_Clock */
-+	/* ctx->dvbt2_fef_tuner_flag  = Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_NOT_USED; */
-+	ctx->tuner_ter_clock_source  = Si2168B_TER_Tuner_clock;
-+	ctx->tuner_ter_clock_control = Si2168B_CLOCK_MANAGED;
-+	ctx->tuner_ter_clock_input   = Si2168B_CLOCK_MODE_TER;
-+	ctx->tuner_ter_clock_freq    = Si2168B_REF_FREQUENCY_TER;
-+
-+	ctx->Si2168B_in_standby      = 0;
-+
-+	ctx->dd_mode_modulation      = Si2168B_DD_MODE_PROP_MODULATION_DEFAULT;
-+	ctx->dd_mode_auto_detect     = Si2168B_DD_MODE_PROP_AUTO_DETECT_DEFAULT;
-+	ctx->dd_mode_invert_spectrum = Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_DEFAULT;
-+	ctx->dd_mode_bw              = Si2168B_DD_MODE_PROP_BW_DEFAULT;
-+
-+	ctx->dvbt_hierarchy_stream   = Si2168B_DVBT_HIERARCHY_PROP_STREAM_DEFAULT;
-+	ctx->dvbc_symbol_rate        = Si2168B_DVBC_SYMBOL_RATE_PROP_RATE_DEFAULT;
-+
-+	ctx->scan_fmin               = Si2168B_SCAN_FMIN_PROP_SCAN_FMIN_DEFAULT;
-+	ctx->scan_fmax               = Si2168B_SCAN_FMAX_PROP_SCAN_FMAX_DEFAULT;
-+	ctx->scan_symb_rate_min      = Si2168B_SCAN_SYMB_RATE_MIN_PROP_SCAN_SYMB_RATE_MIN_DEFAULT;
-+	ctx->scan_symb_rate_max      = Si2168B_SCAN_SYMB_RATE_MAX_PROP_SCAN_SYMB_RATE_MAX_DEFAULT;
-+
-+	ctx->fef_mode                = config->fef_mode;
-+	ctx->fef_selection           = config->fef_mode;
-+	ctx->fef_pin                 = config->fef_pin;
-+	ctx->fef_level               = config->fef_level;
-+
-+#ifdef L1_RF_TER_TUNER_FEF_MODE_SLOW_INITIAL_AGC_SETUP
-+	/* If the TER tuner has initial AGC speed control and it's the selected mode, activate it */
-+	if (ctx->fef_selection == Si2168B_FEF_MODE_SLOW_INITIAL_AGC) {
-+		SiTRACE("TER tuner FEF set to 'SLOW_INITIAL_AGC' mode\n");
-+		ctx->fef_mode = Si2168B_FEF_MODE_SLOW_INITIAL_AGC;
-+	}
-+#ifdef L1_RF_TER_TUNER_FEF_MODE_FREEZE_PIN_SETUP
-+	/* If the TER tuner has an AGC freeze pin and it's the selected mode, activate it */
-+	if (ctx->fef_selection == Si2168B_FEF_MODE_FREEZE_PIN) {
-+		SiTRACE("TER tuner FEF set to 'FREEZE_PIN' mode\n");
-+		ctx->fef_mode = Si2168B_FEF_MODE_FREEZE_PIN;
-+	}
-+#else /* L1_RF_TER_TUNER_FEF_MODE_FREEZE_PIN_SETUP */
-+	if (ctx->fef_selection == Si2168B_FEF_MODE_FREEZE_PIN) {
-+		SiTRACE("TER tuner FEF can not use 'FREEZE_PIN' mode, using 'SLOW_INITIAL_AGC' mode instead\n");
-+		ctx->fef_mode = Si2168B_FEF_MODE_SLOW_INITIAL_AGC;
-+	}
-+#endif /* L1_RF_TER_TUNER_FEF_MODE_FREEZE_PIN_SETUP */
-+#else  /* L1_RF_TER_TUNER_FEF_MODE_SLOW_INITIAL_AGC_SETUP */
-+	SiTRACE("TER tuner FEF set to 'SLOW_NORMAL_AGC' mode\n");
-+#endif /* L1_RF_TER_TUNER_FEF_MODE_SLOW_INITIAL_AGC_SETUP */
-+
-+	return NO_Si2168B_ERROR;
-+}
-+
-+/************************************************************************************************************************
-+  si2168b_sw_init function
-+  Use:        software initialization function
-+              Used to initialize the Si2168B and tuner structures
-+  Behavior:   This function performs all the steps necessary to initialize the Si2168B and tuner instances
-+  Parameter:  front_end, a pointer to the Si2168B_L2_Context context to be initialized
-+  Parameter:  demodAdd, the I2C address of the demod
-+  Parameter:  tunerAdd, the I2C address of the tuner
-+  Comments:     It MUST be called first and once before using any other function.
-+                It can be used to build a multi-demod/multi-tuner application, if called several times from the upper layer with different pointers and addresses
-+                After execution, all demod and tuner functions are accessible.
-+************************************************************************************************************************/
-+static char si2168b_sw_init(struct Si2168B_Priv *priv
-+		, int tunerAdd_Ter
-+		, Si2168B_INDIRECT_I2C_FUNC TER_tuner_enable_func
-+		, Si2168B_INDIRECT_I2C_FUNC TER_tuner_disable_func
-+		, void *p_context)
-+{
-+	Si2168B_L2_Context *front_end = priv->si_front_end;
-+	char infoStringBuffer[1000] = { 0 };
-+	char *infoString;
-+	infoString = &(infoStringBuffer[0]);
-+
-+	/* Pointers initialization */
-+	front_end->Si2168B_init_done   = 0;
-+	front_end->first_init_done     = 0;
-+	front_end->handshakeUsed       = 0; /* set to '0' by default for compatibility with previous versions */
-+	front_end->handshakeOn         = 0;
-+	front_end->handshakePeriod_ms  = 1000;
-+	front_end->TER_init_done       = 0;
-+	front_end->auto_detect_TER     = 1;
-+	front_end->f_TER_tuner_enable  = TER_tuner_enable_func;
-+	front_end->f_TER_tuner_disable = TER_tuner_disable_func;
-+	front_end->tuner_indirect_i2c_connection = priv->config->indirect_i2c_connection;
-+
-+	/* Calling underlying SW initialization functions */
-+	si2168b_ctx_init(front_end->demod, priv->config->demod_address, priv->i2c, priv->config);
-+	SiTRACE("Si2168B_L2_EVB_SW_Init starting...\n");
-+
-+	/* SiLabs_TER_Tuner_L1_API_Init(front_end->tuner_ter, tunerAdd_Ter, i2c_adap); */
-+	/* done in tuner module startup */
-+
-+	front_end->callback = p_context;
-+#ifdef SiTRACE
-+	if (si2168b_infos(front_end, infoString))  {
-+		SiTRACE("%s\n", infoString);
-+	}
-+#endif /* SiTRACE */
-+	SiTRACE("Si2168B_L2_EVB_SW_Init complete\n");
-+	return 1;
-+}
-+
-+/************************************************************************************************************************
-+  si2168b_media function
-+  Use:        media retrieval function
-+              Used to retrieve the media used by the Si2168B
-+************************************************************************************************************************/
-+static u8 si2168b_media(si2168b_context *ctx)
-+{
-+	switch (ctx->dd_mode_modulation) {
-+	default:
-+	case Si2168B_DD_MODE_PROP_MODULATION_AUTO_DETECT:
-+		switch (ctx->dd_mode_auto_detect) {
-+		default:
-+			break;
-+		case Si2168B_DD_MODE_PROP_AUTO_DETECT_AUTO_DVB_T_T2:
-+			return Si2168B_TERRESTRIAL;
-+		}
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT:
-+			return Si2168B_TERRESTRIAL;
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT2:
-+		return Si2168B_TERRESTRIAL;
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBC:
-+#ifdef __MCNS__
-+	case Si2168B_DD_MODE_PROP_MODULATION_MCNS:
-+#endif /* __MCNS__ */
-+		return Si2168B_TERRESTRIAL;
-+	}
-+	return 0;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_START_CLK COMMAND                        */
-+/*---------------------------------------------------*/
-+static u8 si2168b_start_clk(si2168b_context *ctx,
-+		u8  subcode,
-+		u8  reserved1,
-+		u8  tune_cap,
-+		u8  reserved2,
-+		u16 clk_mode,
-+		u8  reserved3,
-+		u8  reserved4,
-+		u8  start_clk)
-+{
-+	u8 cmdByteBuffer[13];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B START_CLK\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_START_CLK_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( subcode   & Si2168B_START_CLK_CMD_SUBCODE_MASK   ) << Si2168B_START_CLK_CMD_SUBCODE_LSB  );
-+	cmdByteBuffer[2] = (u8) ( ( reserved1 & Si2168B_START_CLK_CMD_RESERVED1_MASK ) << Si2168B_START_CLK_CMD_RESERVED1_LSB);
-+	cmdByteBuffer[3] = (u8) ( ( tune_cap  & Si2168B_START_CLK_CMD_TUNE_CAP_MASK  ) << Si2168B_START_CLK_CMD_TUNE_CAP_LSB |
-+			( reserved2 & Si2168B_START_CLK_CMD_RESERVED2_MASK ) << Si2168B_START_CLK_CMD_RESERVED2_LSB);
-+	cmdByteBuffer[4] = (u8) ( ( clk_mode  & Si2168B_START_CLK_CMD_CLK_MODE_MASK  ) << Si2168B_START_CLK_CMD_CLK_MODE_LSB );
-+	cmdByteBuffer[5] = (u8) ((( clk_mode  & Si2168B_START_CLK_CMD_CLK_MODE_MASK  ) << Si2168B_START_CLK_CMD_CLK_MODE_LSB )>>8);
-+	cmdByteBuffer[6] = (u8) ( ( reserved3 & Si2168B_START_CLK_CMD_RESERVED3_MASK ) << Si2168B_START_CLK_CMD_RESERVED3_LSB);
-+	cmdByteBuffer[7] = (u8) ( ( reserved4 & Si2168B_START_CLK_CMD_RESERVED4_MASK ) << Si2168B_START_CLK_CMD_RESERVED4_LSB);
-+	cmdByteBuffer[8] = (u8)0x00;
-+	cmdByteBuffer[9] = (u8)0x00;
-+	cmdByteBuffer[10] = (u8)0x00;
-+	cmdByteBuffer[11] = (u8)0x00;
-+	cmdByteBuffer[12] = (u8) ( ( start_clk & Si2168B_START_CLK_CMD_START_CLK_MASK ) << Si2168B_START_CLK_CMD_START_CLK_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 13, cmdByteBuffer) != 13) {
-+		SiTRACE("Error writing START_CLK bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+	}
-+
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_POWER_UP COMMAND                         */
-+/*---------------------------------------------------*/
-+static u8 si2168b_power_up(si2168b_context *ctx,
-+		u8   subcode,
-+		u8   reset,
-+		u8   reserved2,
-+		u8   reserved4,
-+		u8   reserved1,
-+		u8   addr_mode,
-+		u8   reserved5,
-+		u8   func,
-+		u8   clock_freq,
-+		u8   ctsien,
-+		u8   wake_up)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[8];
-+	u8 rspByteBuffer[1];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B POWER_UP\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_POWER_UP_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( subcode    & Si2168B_POWER_UP_CMD_SUBCODE_MASK    ) << Si2168B_POWER_UP_CMD_SUBCODE_LSB   );
-+	cmdByteBuffer[2] = (u8) ( ( reset      & Si2168B_POWER_UP_CMD_RESET_MASK      ) << Si2168B_POWER_UP_CMD_RESET_LSB     );
-+	cmdByteBuffer[3] = (u8) ( ( reserved2  & Si2168B_POWER_UP_CMD_RESERVED2_MASK  ) << Si2168B_POWER_UP_CMD_RESERVED2_LSB );
-+	cmdByteBuffer[4] = (u8) ( ( reserved4  & Si2168B_POWER_UP_CMD_RESERVED4_MASK  ) << Si2168B_POWER_UP_CMD_RESERVED4_LSB );
-+	cmdByteBuffer[5] = (u8) ( ( reserved1  & Si2168B_POWER_UP_CMD_RESERVED1_MASK  ) << Si2168B_POWER_UP_CMD_RESERVED1_LSB |
-+			( addr_mode  & Si2168B_POWER_UP_CMD_ADDR_MODE_MASK  ) << Si2168B_POWER_UP_CMD_ADDR_MODE_LSB |
-+			( reserved5  & Si2168B_POWER_UP_CMD_RESERVED5_MASK  ) << Si2168B_POWER_UP_CMD_RESERVED5_LSB );
-+	cmdByteBuffer[6] = (u8) ( ( func       & Si2168B_POWER_UP_CMD_FUNC_MASK       ) << Si2168B_POWER_UP_CMD_FUNC_LSB      |
-+			( clock_freq & Si2168B_POWER_UP_CMD_CLOCK_FREQ_MASK ) << Si2168B_POWER_UP_CMD_CLOCK_FREQ_LSB|
-+			( ctsien     & Si2168B_POWER_UP_CMD_CTSIEN_MASK     ) << Si2168B_POWER_UP_CMD_CTSIEN_LSB    );
-+	cmdByteBuffer[7] = (u8) ( ( wake_up    & Si2168B_POWER_UP_CMD_WAKE_UP_MASK    ) << Si2168B_POWER_UP_CMD_WAKE_UP_LSB   );
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 8, cmdByteBuffer) != 8) {
-+		SiTRACE("Error writing POWER_UP bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 1, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling POWER_UP response\n");
-+		ret = error_code;
-+	}
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: si2168b_wakeup
-+  DESCRIPTION:
-+  Parameter:  Pointer to Si2168B Context
-+  Returns:    I2C transaction error code, NO_Si2168B_ERROR if successful
-+************************************************************************************************************************/
-+static int si2168b_wakeup(si2168b_context *ctx)
-+{
-+	u8  start_clk_tune_cap;
-+	u16 start_clk_mode;
-+	u8  power_up_clock_freq;
-+
-+	int return_code;
-+	int media;
-+
-+	return_code = NO_Si2168B_ERROR;
-+	media       = si2168b_media(ctx);
-+	SiTRACE ("si2168b_wakeup: media %d\n", media);
-+
-+	/* Clock source selection */
-+	switch (media) {
-+	default:
-+	case Si2168B_TERRESTRIAL:
-+		start_clk_mode = ctx->tuner_ter_clock_input;
-+		break;
-+	}
-+	if (start_clk_mode == Si2168B_START_CLK_CMD_CLK_MODE_XTAL) {
-+		start_clk_tune_cap = Si2168B_START_CLK_CMD_TUNE_CAP_15P6;
-+	} else {
-+		start_clk_tune_cap = Si2168B_START_CLK_CMD_TUNE_CAP_EXT_CLK;
-+	}
-+	si2168b_start_clk (ctx,
-+			Si2168B_START_CLK_CMD_SUBCODE_CODE,
-+			Si2168B_START_CLK_CMD_RESERVED1_RESERVED,
-+			start_clk_tune_cap,
-+			Si2168B_START_CLK_CMD_RESERVED2_RESERVED,
-+			start_clk_mode,
-+			Si2168B_START_CLK_CMD_RESERVED3_RESERVED,
-+			Si2168B_START_CLK_CMD_RESERVED4_RESERVED,
-+			Si2168B_START_CLK_CMD_START_CLK_START_CLK);
-+	/* Reference frequency selection */
-+	switch (media) {
-+	default:
-+	case Si2168B_TERRESTRIAL : {
-+		if (ctx->tuner_ter_clock_freq == 16) {
-+			SiTRACE("Si2168B_POWER_UP_CMD_CLOCK_FREQ_CLK_16MHZ\n");
-+			power_up_clock_freq = Si2168B_POWER_UP_CMD_CLOCK_FREQ_CLK_16MHZ;
-+		} else if (ctx->tuner_ter_clock_freq == 24) {
-+			SiTRACE("Si2168B_POWER_UP_CMD_CLOCK_FREQ_CLK_24MHZ\n");
-+			power_up_clock_freq = Si2168B_POWER_UP_CMD_CLOCK_FREQ_CLK_24MHZ;
-+		} else {
-+			SiTRACE("Si2168B_POWER_UP_CMD_CLOCK_FREQ_CLK_27MHZ\n");
-+			power_up_clock_freq = Si2168B_POWER_UP_CMD_CLOCK_FREQ_CLK_27MHZ;
-+		}
-+		break;
-+	}
-+	}
-+
-+	return_code = si2168b_power_up(ctx,
-+			Si2168B_POWER_UP_CMD_SUBCODE_CODE,
-+			ctx->power_up_reset,
-+			Si2168B_POWER_UP_CMD_RESERVED2_RESERVED,
-+			Si2168B_POWER_UP_CMD_RESERVED4_RESERVED,
-+			Si2168B_POWER_UP_CMD_RESERVED1_RESERVED,
-+			Si2168B_POWER_UP_CMD_ADDR_MODE_CURRENT,
-+			Si2168B_POWER_UP_CMD_RESERVED5_RESERVED,
-+			ctx->power_up_func,
-+			power_up_clock_freq,
-+			Si2168B_POWER_UP_CMD_CTSIEN_DISABLE,
-+			Si2168B_POWER_UP_CMD_WAKE_UP_WAKE_UP);
-+
-+	if (start_clk_mode == Si2168B_START_CLK_CMD_CLK_MODE_CLK_CLKIO) {
-+		SiTRACE ("Si2168B_START_CLK_CMD_CLK_MODE_CLK_CLKIO\n");
-+	} else if (start_clk_mode == Si2168B_START_CLK_CMD_CLK_MODE_CLK_XTAL_IN) {
-+		SiTRACE ("Si2168B_START_CLK_CMD_CLK_MODE_CLK_XTAL_IN\n");
-+	} else if (start_clk_mode == Si2168B_START_CLK_CMD_CLK_MODE_XTAL) {
-+		SiTRACE ("Si2168B_START_CLK_CMD_CLK_MODE_XTAL\n");
-+	}
-+
-+	if (ctx->power_up_reset == Si2168B_POWER_UP_CMD_RESET_RESET) {
-+		SiTRACE ("Si2168B_POWER_UP_CMD_RESET_RESET\n");
-+	} else if (ctx->power_up_reset == Si2168B_POWER_UP_CMD_RESET_RESUME ) {
-+		SiTRACE ("Si2168B_POWER_UP_CMD_RESET_RESUME\n");
-+	}
-+
-+	if (return_code != NO_Si2168B_ERROR ) {
-+		SiTRACE("si2168b_wakeup: POWER_UP ERROR!\n");
-+		/* second try with reset... */
-+		return_code = si2168b_power_up(ctx,
-+				Si2168B_POWER_UP_CMD_SUBCODE_CODE,
-+				Si2168B_POWER_UP_CMD_RESET_RESET,
-+				Si2168B_POWER_UP_CMD_RESERVED2_RESERVED,
-+				Si2168B_POWER_UP_CMD_RESERVED4_RESERVED,
-+				Si2168B_POWER_UP_CMD_RESERVED1_RESERVED,
-+				Si2168B_POWER_UP_CMD_ADDR_MODE_CURRENT,
-+				Si2168B_POWER_UP_CMD_RESERVED5_RESERVED,
-+				ctx->power_up_func,
-+				power_up_clock_freq,
-+				Si2168B_POWER_UP_CMD_CTSIEN_DISABLE,
-+				Si2168B_POWER_UP_CMD_WAKE_UP_WAKE_UP);
-+		if (return_code != NO_Si2168B_ERROR ) {
-+			SiTRACE("si2168b_wakeup: POWER_UP ERROR (2)!\n");
-+			return return_code;
-+		}
-+	}
-+#if 1
-+	/* After a successful POWER_UP, set values for 'resume' only */
-+	ctx->power_up_reset = Si2168B_POWER_UP_CMD_RESET_RESUME;
-+#else /* reset always */
-+	ctx->power_up_reset = Si2168B_POWER_UP_CMD_RESET_RESET;
-+#endif
-+	ctx->power_up_func  = Si2168B_POWER_UP_CMD_FUNC_NORMAL;
-+
-+	return NO_Si2168B_ERROR;
-+}
-+
-+static int si2168b_ts_bus_ctrl(struct dvb_frontend* fe, int acquire)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	Si2168B_L2_Context *front_end = priv->si_front_end;
-+	u8 ts_bus_mode = 0;
-+	int ret = 0;
-+
-+	siprintk("%s() acquire=%d\n", __func__, acquire);
-+
-+	_mutex_lock(&front_end->demod->ts_bus_ctrl_lock);
-+
-+	if (front_end->demod->Si2168B_in_standby) {
-+		/* nothing to do */
-+		siprintk("%s() Si2168B is in standby mode. Nothing to do.\n", __func__);
-+		ret = 0;
-+		goto unlock_mutex;
-+	}
-+
-+	if (acquire) {
-+		ts_bus_mode = priv->config->ts_bus_mode;
-+	} else {
-+		ts_bus_mode = SILABS_TS_TRISTATE;
-+	}
-+	siprintk("%s() setting the Si2168B ts bus to mode %d\n", __func__, ts_bus_mode);
-+
-+    if (si2168b_set_ts_mode(priv, ts_bus_mode) != NO_Si2168B_ERROR) {
-+		printk(KERN_WARNING "%s(): si2168b_set_ts_mode(%u) failed\n", __func__, priv->config->ts_bus_mode);
-+		/* try to wake up... */
-+		front_end->demod->Si2168B_in_standby = 1;
-+		if (si2168b_wakeup(priv->si_front_end->demod) != NO_Si2168B_ERROR) {
-+			SiTRACE("si2168b_ts_bus_ctrl(): WAKEUP error!\n");
-+			ret = -EIO;
-+			goto unlock_mutex;
-+		}
-+		/* second try... */
-+		if (si2168b_set_ts_mode(priv, ts_bus_mode) != NO_Si2168B_ERROR) {
-+			printk(KERN_ERR "%s(): si2168b_set_ts_mode(%u) failed after wake up\n", __func__, priv->config->ts_bus_mode);
-+			ret = -EIO;
-+			goto unlock_mutex;
-+		}
-+	}
-+
-+	siprintk("%s() DONE.\n", __func__);
-+
-+unlock_mutex:
-+	_mutex_unlock(&front_end->demod->ts_bus_ctrl_lock);
-+	return ret;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_DD_STATUS COMMAND                        */
-+/*---------------------------------------------------*/
-+static u8 si2168b_dd_status(si2168b_context *ctx, u8 intack, Si2168B_DD_STATUS_CMD_REPLY_struct *dd_status)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[8];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	/*SiTRACE("Si2168B DD_STATUS ");*/
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DD_STATUS_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( intack & Si2168B_DD_STATUS_CMD_INTACK_MASK ) << Si2168B_DD_STATUS_CMD_INTACK_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing DD_STATUS bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 8, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DD_STATUS response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	dd_status->pclint       = (( ( (rspByteBuffer[1] )) >> Si2168B_DD_STATUS_RESPONSE_PCLINT_LSB       ) & Si2168B_DD_STATUS_RESPONSE_PCLINT_MASK       );
-+	dd_status->dlint        = (( ( (rspByteBuffer[1] )) >> Si2168B_DD_STATUS_RESPONSE_DLINT_LSB        ) & Si2168B_DD_STATUS_RESPONSE_DLINT_MASK        );
-+	dd_status->berint       = (( ( (rspByteBuffer[1] )) >> Si2168B_DD_STATUS_RESPONSE_BERINT_LSB       ) & Si2168B_DD_STATUS_RESPONSE_BERINT_MASK       );
-+	dd_status->uncorint     = (( ( (rspByteBuffer[1] )) >> Si2168B_DD_STATUS_RESPONSE_UNCORINT_LSB     ) & Si2168B_DD_STATUS_RESPONSE_UNCORINT_MASK     );
-+	dd_status->rsqint_bit5  = (( ( (rspByteBuffer[1] )) >> Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT5_LSB  ) & Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT5_MASK  );
-+	dd_status->rsqint_bit6  = (( ( (rspByteBuffer[1] )) >> Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT6_LSB  ) & Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT6_MASK  );
-+	dd_status->rsqint_bit7  = (( ( (rspByteBuffer[1] )) >> Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT7_LSB  ) & Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT7_MASK  );
-+	dd_status->pcl          = (( ( (rspByteBuffer[2] )) >> Si2168B_DD_STATUS_RESPONSE_PCL_LSB          ) & Si2168B_DD_STATUS_RESPONSE_PCL_MASK          );
-+	dd_status->dl           = (( ( (rspByteBuffer[2] )) >> Si2168B_DD_STATUS_RESPONSE_DL_LSB           ) & Si2168B_DD_STATUS_RESPONSE_DL_MASK           );
-+	dd_status->ber          = (( ( (rspByteBuffer[2] )) >> Si2168B_DD_STATUS_RESPONSE_BER_LSB          ) & Si2168B_DD_STATUS_RESPONSE_BER_MASK          );
-+	dd_status->uncor        = (( ( (rspByteBuffer[2] )) >> Si2168B_DD_STATUS_RESPONSE_UNCOR_LSB        ) & Si2168B_DD_STATUS_RESPONSE_UNCOR_MASK        );
-+	dd_status->rsqstat_bit5 = (( ( (rspByteBuffer[2] )) >> Si2168B_DD_STATUS_RESPONSE_RSQSTAT_BIT5_LSB ) & Si2168B_DD_STATUS_RESPONSE_RSQSTAT_BIT5_MASK );
-+	dd_status->rsqstat_bit6 = (( ( (rspByteBuffer[2] )) >> Si2168B_DD_STATUS_RESPONSE_RSQSTAT_BIT6_LSB ) & Si2168B_DD_STATUS_RESPONSE_RSQSTAT_BIT6_MASK );
-+	dd_status->rsqstat_bit7 = (( ( (rspByteBuffer[2] )) >> Si2168B_DD_STATUS_RESPONSE_RSQSTAT_BIT7_LSB ) & Si2168B_DD_STATUS_RESPONSE_RSQSTAT_BIT7_MASK );
-+	dd_status->modulation   = (( ( (rspByteBuffer[3] )) >> Si2168B_DD_STATUS_RESPONSE_MODULATION_LSB   ) & Si2168B_DD_STATUS_RESPONSE_MODULATION_MASK   );
-+	dd_status->ts_bit_rate  = (( ( (rspByteBuffer[4] ) | (rspByteBuffer[5]  << 8 )) >> Si2168B_DD_STATUS_RESPONSE_TS_BIT_RATE_LSB  ) & Si2168B_DD_STATUS_RESPONSE_TS_BIT_RATE_MASK  );
-+	dd_status->ts_clk_freq  = (( ( (rspByteBuffer[6] ) | (rspByteBuffer[7]  << 8 )) >> Si2168B_DD_STATUS_RESPONSE_TS_CLK_FREQ_LSB  ) & Si2168B_DD_STATUS_RESPONSE_TS_CLK_FREQ_MASK  );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_DVBT_STATUS COMMAND                      */
-+/*---------------------------------------------------*/
-+static u8 si2168b_dvbt_status(si2168b_context *ctx, u8 intack, Si2168B_DVBT_STATUS_CMD_REPLY_struct *dvbt_status)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[13];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B DVBT_STATUS\n");
-+
-+	_mutex_lock(&ctx->lock);
-+	cmdByteBuffer[0] = Si2168B_DVBT_STATUS_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( intack & Si2168B_DVBT_STATUS_CMD_INTACK_MASK ) << Si2168B_DVBT_STATUS_CMD_INTACK_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing DVBT_STATUS bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 13, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DVBT_STATUS response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	dvbt_status->pclint        =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT_STATUS_RESPONSE_PCLINT_LSB        ) & Si2168B_DVBT_STATUS_RESPONSE_PCLINT_MASK        );
-+	dvbt_status->dlint         =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT_STATUS_RESPONSE_DLINT_LSB         ) & Si2168B_DVBT_STATUS_RESPONSE_DLINT_MASK         );
-+	dvbt_status->berint        =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT_STATUS_RESPONSE_BERINT_LSB        ) & Si2168B_DVBT_STATUS_RESPONSE_BERINT_MASK        );
-+	dvbt_status->uncorint      =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT_STATUS_RESPONSE_UNCORINT_LSB      ) & Si2168B_DVBT_STATUS_RESPONSE_UNCORINT_MASK      );
-+	dvbt_status->notdvbtint    =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT_STATUS_RESPONSE_NOTDVBTINT_LSB    ) & Si2168B_DVBT_STATUS_RESPONSE_NOTDVBTINT_MASK    );
-+	dvbt_status->pcl           =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBT_STATUS_RESPONSE_PCL_LSB           ) & Si2168B_DVBT_STATUS_RESPONSE_PCL_MASK           );
-+	dvbt_status->dl            =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBT_STATUS_RESPONSE_DL_LSB            ) & Si2168B_DVBT_STATUS_RESPONSE_DL_MASK            );
-+	dvbt_status->ber           =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBT_STATUS_RESPONSE_BER_LSB           ) & Si2168B_DVBT_STATUS_RESPONSE_BER_MASK           );
-+	dvbt_status->uncor         =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBT_STATUS_RESPONSE_UNCOR_LSB         ) & Si2168B_DVBT_STATUS_RESPONSE_UNCOR_MASK         );
-+	dvbt_status->notdvbt       =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBT_STATUS_RESPONSE_NOTDVBT_LSB       ) & Si2168B_DVBT_STATUS_RESPONSE_NOTDVBT_MASK       );
-+	dvbt_status->cnr           =   (( ( (rspByteBuffer[3]  )) >> Si2168B_DVBT_STATUS_RESPONSE_CNR_LSB           ) & Si2168B_DVBT_STATUS_RESPONSE_CNR_MASK           );
-+	dvbt_status->afc_freq      = (((( ( (rspByteBuffer[4]  ) | (rspByteBuffer[5]  << 8 )) >> Si2168B_DVBT_STATUS_RESPONSE_AFC_FREQ_LSB      ) & Si2168B_DVBT_STATUS_RESPONSE_AFC_FREQ_MASK) <<Si2168B_DVBT_STATUS_RESPONSE_AFC_FREQ_SHIFT ) >>Si2168B_DVBT_STATUS_RESPONSE_AFC_FREQ_SHIFT      );
-+	dvbt_status->timing_offset = (((( ( (rspByteBuffer[6]  ) | (rspByteBuffer[7]  << 8 )) >> Si2168B_DVBT_STATUS_RESPONSE_TIMING_OFFSET_LSB ) & Si2168B_DVBT_STATUS_RESPONSE_TIMING_OFFSET_MASK) <<Si2168B_DVBT_STATUS_RESPONSE_TIMING_OFFSET_SHIFT ) >>Si2168B_DVBT_STATUS_RESPONSE_TIMING_OFFSET_SHIFT );
-+	dvbt_status->constellation =   (( ( (rspByteBuffer[8]  )) >> Si2168B_DVBT_STATUS_RESPONSE_CONSTELLATION_LSB ) & Si2168B_DVBT_STATUS_RESPONSE_CONSTELLATION_MASK );
-+	dvbt_status->sp_inv        =   (( ( (rspByteBuffer[8]  )) >> Si2168B_DVBT_STATUS_RESPONSE_SP_INV_LSB        ) & Si2168B_DVBT_STATUS_RESPONSE_SP_INV_MASK        );
-+	dvbt_status->rate_hp       =   (( ( (rspByteBuffer[9]  )) >> Si2168B_DVBT_STATUS_RESPONSE_RATE_HP_LSB       ) & Si2168B_DVBT_STATUS_RESPONSE_RATE_HP_MASK       );
-+	dvbt_status->rate_lp       =   (( ( (rspByteBuffer[9]  )) >> Si2168B_DVBT_STATUS_RESPONSE_RATE_LP_LSB       ) & Si2168B_DVBT_STATUS_RESPONSE_RATE_LP_MASK       );
-+	dvbt_status->fft_mode      =   (( ( (rspByteBuffer[10] )) >> Si2168B_DVBT_STATUS_RESPONSE_FFT_MODE_LSB      ) & Si2168B_DVBT_STATUS_RESPONSE_FFT_MODE_MASK      );
-+	dvbt_status->guard_int     =   (( ( (rspByteBuffer[10] )) >> Si2168B_DVBT_STATUS_RESPONSE_GUARD_INT_LSB     ) & Si2168B_DVBT_STATUS_RESPONSE_GUARD_INT_MASK     );
-+	dvbt_status->hierarchy     =   (( ( (rspByteBuffer[11] )) >> Si2168B_DVBT_STATUS_RESPONSE_HIERARCHY_LSB     ) & Si2168B_DVBT_STATUS_RESPONSE_HIERARCHY_MASK     );
-+	dvbt_status->tps_length    = (((( ( (rspByteBuffer[12] )) >> Si2168B_DVBT_STATUS_RESPONSE_TPS_LENGTH_LSB    ) & Si2168B_DVBT_STATUS_RESPONSE_TPS_LENGTH_MASK) <<Si2168B_DVBT_STATUS_RESPONSE_TPS_LENGTH_SHIFT ) >>Si2168B_DVBT_STATUS_RESPONSE_TPS_LENGTH_SHIFT    );
-+
-+	unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_DVBT2_STATUS COMMAND                     */
-+/*---------------------------------------------------*/
-+static u8 si2168b_dvbt2_status(si2168b_context *ctx, u8 intack, Si2168B_DVBT2_STATUS_CMD_REPLY_struct *dvbt2_status)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[14];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B DVBT2_STATUS\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DVBT2_STATUS_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( intack & Si2168B_DVBT2_STATUS_CMD_INTACK_MASK ) << Si2168B_DVBT2_STATUS_CMD_INTACK_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing DVBT2_STATUS bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 14, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DVBT2_STATUS response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	dvbt2_status->pclint        =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_PCLINT_LSB        ) & Si2168B_DVBT2_STATUS_RESPONSE_PCLINT_MASK        );
-+	dvbt2_status->dlint         =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_DLINT_LSB         ) & Si2168B_DVBT2_STATUS_RESPONSE_DLINT_MASK         );
-+	dvbt2_status->berint        =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_BERINT_LSB        ) & Si2168B_DVBT2_STATUS_RESPONSE_BERINT_MASK        );
-+	dvbt2_status->uncorint      =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_UNCORINT_LSB      ) & Si2168B_DVBT2_STATUS_RESPONSE_UNCORINT_MASK      );
-+	dvbt2_status->notdvbt2int   =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_NOTDVBT2INT_LSB   ) & Si2168B_DVBT2_STATUS_RESPONSE_NOTDVBT2INT_MASK   );
-+	dvbt2_status->pcl           =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_PCL_LSB           ) & Si2168B_DVBT2_STATUS_RESPONSE_PCL_MASK           );
-+	dvbt2_status->dl            =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_DL_LSB            ) & Si2168B_DVBT2_STATUS_RESPONSE_DL_MASK            );
-+	dvbt2_status->ber           =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_BER_LSB           ) & Si2168B_DVBT2_STATUS_RESPONSE_BER_MASK           );
-+	dvbt2_status->uncor         =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_UNCOR_LSB         ) & Si2168B_DVBT2_STATUS_RESPONSE_UNCOR_MASK         );
-+	dvbt2_status->notdvbt2      =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_NOTDVBT2_LSB      ) & Si2168B_DVBT2_STATUS_RESPONSE_NOTDVBT2_MASK      );
-+	dvbt2_status->cnr           =   (( ( (rspByteBuffer[3]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_CNR_LSB           ) & Si2168B_DVBT2_STATUS_RESPONSE_CNR_MASK           );
-+	dvbt2_status->afc_freq      = (((( ( (rspByteBuffer[4]  ) | (rspByteBuffer[5]  << 8 )) >> Si2168B_DVBT2_STATUS_RESPONSE_AFC_FREQ_LSB      ) & Si2168B_DVBT2_STATUS_RESPONSE_AFC_FREQ_MASK) <<Si2168B_DVBT2_STATUS_RESPONSE_AFC_FREQ_SHIFT ) >>Si2168B_DVBT2_STATUS_RESPONSE_AFC_FREQ_SHIFT      );
-+	dvbt2_status->timing_offset = (((( ( (rspByteBuffer[6]  ) | (rspByteBuffer[7]  << 8 )) >> Si2168B_DVBT2_STATUS_RESPONSE_TIMING_OFFSET_LSB ) & Si2168B_DVBT2_STATUS_RESPONSE_TIMING_OFFSET_MASK) <<Si2168B_DVBT2_STATUS_RESPONSE_TIMING_OFFSET_SHIFT ) >>Si2168B_DVBT2_STATUS_RESPONSE_TIMING_OFFSET_SHIFT );
-+	dvbt2_status->constellation =   (( ( (rspByteBuffer[8]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_LSB ) & Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_MASK );
-+	dvbt2_status->sp_inv        =   (( ( (rspByteBuffer[8]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_SP_INV_LSB        ) & Si2168B_DVBT2_STATUS_RESPONSE_SP_INV_MASK        );
-+	dvbt2_status->fef           =   (( ( (rspByteBuffer[8]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_FEF_LSB           ) & Si2168B_DVBT2_STATUS_RESPONSE_FEF_MASK           );
-+	dvbt2_status->fft_mode      =   (( ( (rspByteBuffer[9]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_LSB      ) & Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_MASK      );
-+	dvbt2_status->guard_int     =   (( ( (rspByteBuffer[9]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_LSB     ) & Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_MASK     );
-+	dvbt2_status->bw_ext        =   (( ( (rspByteBuffer[9]  )) >> Si2168B_DVBT2_STATUS_RESPONSE_BW_EXT_LSB        ) & Si2168B_DVBT2_STATUS_RESPONSE_BW_EXT_MASK        );
-+	dvbt2_status->num_plp       =   (( ( (rspByteBuffer[10] )) >> Si2168B_DVBT2_STATUS_RESPONSE_NUM_PLP_LSB       ) & Si2168B_DVBT2_STATUS_RESPONSE_NUM_PLP_MASK       );
-+	dvbt2_status->pilot_pattern =   (( ( (rspByteBuffer[11] )) >> Si2168B_DVBT2_STATUS_RESPONSE_PILOT_PATTERN_LSB ) & Si2168B_DVBT2_STATUS_RESPONSE_PILOT_PATTERN_MASK );
-+	dvbt2_status->tx_mode       =   (( ( (rspByteBuffer[11] )) >> Si2168B_DVBT2_STATUS_RESPONSE_TX_MODE_LSB       ) & Si2168B_DVBT2_STATUS_RESPONSE_TX_MODE_MASK       );
-+	dvbt2_status->rotated       =   (( ( (rspByteBuffer[11] )) >> Si2168B_DVBT2_STATUS_RESPONSE_ROTATED_LSB       ) & Si2168B_DVBT2_STATUS_RESPONSE_ROTATED_MASK       );
-+	dvbt2_status->short_frame   =   (( ( (rspByteBuffer[11] )) >> Si2168B_DVBT2_STATUS_RESPONSE_SHORT_FRAME_LSB   ) & Si2168B_DVBT2_STATUS_RESPONSE_SHORT_FRAME_MASK   );
-+	dvbt2_status->t2_mode       =   (( ( (rspByteBuffer[11] )) >> Si2168B_DVBT2_STATUS_RESPONSE_T2_MODE_LSB       ) & Si2168B_DVBT2_STATUS_RESPONSE_T2_MODE_MASK       );
-+	dvbt2_status->code_rate     =   (( ( (rspByteBuffer[12] )) >> Si2168B_DVBT2_STATUS_RESPONSE_CODE_RATE_LSB     ) & Si2168B_DVBT2_STATUS_RESPONSE_CODE_RATE_MASK     );
-+	dvbt2_status->t2_version    =   (( ( (rspByteBuffer[12] )) >> Si2168B_DVBT2_STATUS_RESPONSE_T2_VERSION_LSB    ) & Si2168B_DVBT2_STATUS_RESPONSE_T2_VERSION_MASK    );
-+	dvbt2_status->plp_id        =   (( ( (rspByteBuffer[13] )) >> Si2168B_DVBT2_STATUS_RESPONSE_PLP_ID_LSB        ) & Si2168B_DVBT2_STATUS_RESPONSE_PLP_ID_MASK        );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_DVBC_STATUS COMMAND                      */
-+/*---------------------------------------------------*/
-+static u8 si2168b_dvbc_status(si2168b_context *ctx, u8 intack, Si2168B_DVBC_STATUS_CMD_REPLY_struct *dvbc_status)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[9];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B DVBC_STATUS\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DVBC_STATUS_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( intack & Si2168B_DVBC_STATUS_CMD_INTACK_MASK ) << Si2168B_DVBC_STATUS_CMD_INTACK_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing DVBC_STATUS bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 9, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DVBC_STATUS response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	dvbc_status->pclint        =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBC_STATUS_RESPONSE_PCLINT_LSB        ) & Si2168B_DVBC_STATUS_RESPONSE_PCLINT_MASK        );
-+	dvbc_status->dlint         =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBC_STATUS_RESPONSE_DLINT_LSB         ) & Si2168B_DVBC_STATUS_RESPONSE_DLINT_MASK         );
-+	dvbc_status->berint        =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBC_STATUS_RESPONSE_BERINT_LSB        ) & Si2168B_DVBC_STATUS_RESPONSE_BERINT_MASK        );
-+	dvbc_status->uncorint      =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBC_STATUS_RESPONSE_UNCORINT_LSB      ) & Si2168B_DVBC_STATUS_RESPONSE_UNCORINT_MASK      );
-+	dvbc_status->pcl           =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBC_STATUS_RESPONSE_PCL_LSB           ) & Si2168B_DVBC_STATUS_RESPONSE_PCL_MASK           );
-+	dvbc_status->dl            =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBC_STATUS_RESPONSE_DL_LSB            ) & Si2168B_DVBC_STATUS_RESPONSE_DL_MASK            );
-+	dvbc_status->ber           =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBC_STATUS_RESPONSE_BER_LSB           ) & Si2168B_DVBC_STATUS_RESPONSE_BER_MASK           );
-+	dvbc_status->uncor         =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBC_STATUS_RESPONSE_UNCOR_LSB         ) & Si2168B_DVBC_STATUS_RESPONSE_UNCOR_MASK         );
-+	dvbc_status->cnr           =   (( ( (rspByteBuffer[3]  )) >> Si2168B_DVBC_STATUS_RESPONSE_CNR_LSB           ) & Si2168B_DVBC_STATUS_RESPONSE_CNR_MASK           );
-+	dvbc_status->afc_freq      = (((( ( (rspByteBuffer[4]  ) | (rspByteBuffer[5]  << 8 )) >> Si2168B_DVBC_STATUS_RESPONSE_AFC_FREQ_LSB      ) & Si2168B_DVBC_STATUS_RESPONSE_AFC_FREQ_MASK) <<Si2168B_DVBC_STATUS_RESPONSE_AFC_FREQ_SHIFT ) >>Si2168B_DVBC_STATUS_RESPONSE_AFC_FREQ_SHIFT      );
-+	dvbc_status->timing_offset = (((( ( (rspByteBuffer[6]  ) | (rspByteBuffer[7]  << 8 )) >> Si2168B_DVBC_STATUS_RESPONSE_TIMING_OFFSET_LSB ) & Si2168B_DVBC_STATUS_RESPONSE_TIMING_OFFSET_MASK) <<Si2168B_DVBC_STATUS_RESPONSE_TIMING_OFFSET_SHIFT ) >>Si2168B_DVBC_STATUS_RESPONSE_TIMING_OFFSET_SHIFT );
-+	dvbc_status->constellation =   (( ( (rspByteBuffer[8]  )) >> Si2168B_DVBC_STATUS_RESPONSE_CONSTELLATION_LSB ) & Si2168B_DVBC_STATUS_RESPONSE_CONSTELLATION_MASK );
-+	dvbc_status->sp_inv        =   (( ( (rspByteBuffer[8]  )) >> Si2168B_DVBC_STATUS_RESPONSE_SP_INV_LSB        ) & Si2168B_DVBC_STATUS_RESPONSE_SP_INV_MASK        );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/* Receive Signal Strength Indicator (RSSI) */
-+
-+static int si2168b_read_rssi(struct dvb_frontend *fe, u16 *rssi)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	int ret = 0;
-+
-+	if (fe->ops.tuner_ops.get_rf_strength == NULL) {
-+		siprintk("%s(): WARNING: get_rf_strength() not available\n", __func__);
-+		return -ENODEV;
-+	}
-+
-+	if ( priv->config->indirect_i2c_connection ) { /* INDIRECT_I2C_CONNECTION? */
-+		if (priv->si_front_end->f_TER_tuner_enable(priv->si_front_end->callback) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): f_TER_tuner_enable() failed\n", __func__);
-+			return -EFAULT;
-+		}
-+	} else {
-+		if (si2168b_tuner_i2c_enable(priv->si_front_end) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): si2168b_tuner_i2c_enable() failed\n", __func__);
-+			return -EFAULT;
-+		}
-+	}
-+	ret = fe->ops.tuner_ops.get_rf_strength(fe, rssi);
-+
-+	if (ret == 0) {
-+		siprintk("%s(): RSSI %3d dBm\n", __func__, *rssi);
-+	} else {
-+		siprintk("%s(): get_rf_strength() failed\n", __func__);
-+	}
-+
-+	if ( priv->config->indirect_i2c_connection ) { /* INDIRECT_I2C_CONNECTION? */
-+		if (priv->si_front_end->f_TER_tuner_disable(priv->si_front_end->callback) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): f_TER_tuner_disable() failed\n", __func__);
-+			return -EFAULT;
-+		}
-+	} else {
-+		if (si2168b_tuner_i2c_disable(priv->si_front_end) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): si2168b_tuner_i2c_disable() failed\n", __func__);
-+			return -EFAULT;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/* read carrier-to-noise ratio (C/N) */
-+
-+static int si2168b_read_cnr(struct dvb_frontend *fe, u16 *cnr)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	si2168b_context *demod = priv->si_front_end->demod;
-+
-+	Si2168B_DD_STATUS_CMD_REPLY_struct    dd_status;
-+	Si2168B_DVBT_STATUS_CMD_REPLY_struct  dvbt_status;
-+	Si2168B_DVBT2_STATUS_CMD_REPLY_struct dvbt2_status;
-+	Si2168B_DVBC_STATUS_CMD_REPLY_struct  dvbc_status;
-+
-+	/* Call the demod global status function */
-+	si2168b_dd_status(demod, Si2168B_DD_STATUS_CMD_INTACK_OK, &dd_status);
-+
-+	/* Call the standard-specific status function */
-+	switch (dd_status.modulation) {
-+	case Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBT:
-+		if (si2168b_dvbt_status(demod, Si2168B_DVBT_STATUS_CMD_INTACK_OK, &dvbt_status) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): si2168b_dvbt_status() failed\n", __func__);
-+			return -EFAULT;
-+		}
-+		*cnr = dvbt_status.cnr;
-+		break;
-+	case Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBT2:
-+		if (si2168b_dvbt2_status(demod, Si2168B_DVBT2_STATUS_CMD_INTACK_OK, &dvbt2_status) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): si2168b_dvbt2_status() failed\n", __func__);
-+			return -EFAULT;
-+		}
-+		*cnr = dvbt2_status.cnr;
-+		break;
-+	case Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBC:
-+		if (si2168b_dvbc_status(demod, Si2168B_DVBC_STATUS_CMD_INTACK_OK, &dvbc_status) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): si2168b_dvbc_status() failed\n", __func__);
-+			return -EFAULT;
-+		}
-+		*cnr = dvbc_status.cnr;
-+		break;
-+	default:
-+		siprintk("%s(): invalid mode\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	siprintk("%s(): C/N  %d dB\n", __func__, ((*cnr) / 4));
-+
-+	/**cnr *= 160;*/ /* linux value adjustment */
-+
-+	return 0;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_DD_BER COMMAND                           */
-+/*---------------------------------------------------*/
-+static u8 si2168b_dd_ber(si2168b_context *ctx, u8 rst, Si2168B_DD_BER_CMD_REPLY_struct *dd_ber)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[3];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B DD_BER\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DD_BER_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( rst & Si2168B_DD_BER_CMD_RST_MASK ) << Si2168B_DD_BER_CMD_RST_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing DD_BER bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 3, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DD_BER response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	dd_ber->exp  = (( ( (rspByteBuffer[1]  )) >> Si2168B_DD_BER_RESPONSE_EXP_LSB  ) & Si2168B_DD_BER_RESPONSE_EXP_MASK  );
-+	dd_ber->mant = (( ( (rspByteBuffer[2]  )) >> Si2168B_DD_BER_RESPONSE_MANT_LSB ) & Si2168B_DD_BER_RESPONSE_MANT_MASK );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_DD_UNCOR COMMAND                         */
-+/*---------------------------------------------------*/
-+static u8 si2168b_dd_uncor(si2168b_context *ctx, u8 rst, Si2168B_DD_UNCOR_CMD_REPLY_struct *dd_uncor)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[3];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B DD_UNCOR\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DD_UNCOR_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( rst & Si2168B_DD_UNCOR_CMD_RST_MASK ) << Si2168B_DD_UNCOR_CMD_RST_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing DD_UNCOR bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 3, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DD_UNCOR response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	dd_uncor->uncor_lsb =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DD_UNCOR_RESPONSE_UNCOR_LSB_LSB ) & Si2168B_DD_UNCOR_RESPONSE_UNCOR_LSB_MASK );
-+	dd_uncor->uncor_msb =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DD_UNCOR_RESPONSE_UNCOR_MSB_LSB ) & Si2168B_DD_UNCOR_RESPONSE_UNCOR_MSB_MASK );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+static inline int exp_10(int m)
-+{
-+	int i;
-+	int p = 1;
-+
-+	for (i = 1; i <= m; i++) {
-+		p *= 10;
-+	}
-+	return p;
-+}
-+
-+static int si2168b_read_ber(struct dvb_frontend *fe, u32 *ber)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
-+	si2168b_context *demod = priv->si_front_end->demod;
-+	Si2168B_DD_BER_CMD_REPLY_struct dd_ber;
-+
-+	/* Retrieving BER values */
-+	switch (p->delivery_system) {
-+	case SYS_DVBT:
-+	case SYS_DVBT2:
-+	case SYS_DVBC_ANNEX_A:
-+/*  case SILABS_MCNS : */
-+		if (si2168b_dd_ber(demod, Si2168B_DD_BER_CMD_RST_RUN, &dd_ber) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): si2168b_dd_ber() failed\n", __func__);
-+			return -EFAULT;
-+		}
-+		/* CHECK the exponent value to know if the BER is available or not */
-+		if (dd_ber.exp != 0) {
-+			*ber = (dd_ber.mant / 10) / exp_10(dd_ber.exp);
-+		} else {
-+			*ber = 0;
-+		}
-+		siprintk("%s(): BER=%u\n", __func__, *ber);
-+		break;
-+	default:
-+		return 0;
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int si2168b_read_uncorrs(struct dvb_frontend *fe, u32 *uncorrs)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	si2168b_context *demod = priv->si_front_end->demod;
-+	Si2168B_DD_UNCOR_CMD_REPLY_struct dd_uncor = { .uncor_msb=0, .uncor_lsb=0 };
-+
-+	if (si2168b_dd_uncor(demod, Si2168B_DD_UNCOR_CMD_RST_RUN, &dd_uncor) != NO_Si2168B_ERROR) {
-+		siprintk("%s(): si2168b_dd_uncor() failed\n", __func__);
-+		return 0;
-+	}
-+	*uncorrs = (((u32) dd_uncor.uncor_msb) << 8) + dd_uncor.uncor_lsb;
-+
-+	siprintk("%s(): uncorrs=%u\n", __func__, *uncorrs);
-+
-+	return 0;
-+}
-+
-+static int si2168b_get_stats(struct dvb_frontend *fe, enum fe_status *status)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	si2168b_context *demod = priv->si_front_end->demod;
-+	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
-+	Si2168B_DD_STATUS_CMD_REPLY_struct dd_status;
-+	u16 rssi;
-+	u16 cnr;
-+	u32 ber;
-+
-+	if (si2168b_dd_status(demod, Si2168B_DD_STATUS_CMD_INTACK_OK, &dd_status) != NO_Si2168B_ERROR) {
-+		siprintk("%s(): si2168b_dd_status() failed\n", __func__);
-+		return -EFAULT;
-+	}
-+
-+	/* reset status */
-+	*status = 0;
-+
-+	/* demod lock? */
-+	if (dd_status.pcl == Si2168B_DD_STATUS_RESPONSE_PCL_LOCKED) {
-+		*status |= FE_HAS_SIGNAL;
-+	}
-+
-+	/* fec lock */
-+	if (dd_status.dl == Si2168B_DD_STATUS_RESPONSE_DL_LOCKED) {
-+		*status |= FE_HAS_LOCK;
-+		*status |= FE_HAS_VITERBI;
-+
-+		/* ToDo: set the other flags correctly */
-+		*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_SYNC;
-+		/* if fec is locked signal, carrier and sync flags should be set too */
-+	}
-+
-+	c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+
-+	/* read RSSI from tuner */
-+
-+	if (si2168b_read_rssi(fe, &rssi)) {
-+		c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	} else {
-+		c->strength.stat[0].scale = FE_SCALE_DECIBEL;
-+		c->strength.stat[0].uvalue = rssi;
-+	}
-+
-+	if (si2168b_read_cnr(fe, &cnr)) {
-+		c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	} else {
-+		c->cnr.stat[0].uvalue = cnr * 1/*00*/;
-+		c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
-+	}
-+
-+	if (dd_status.dl != Si2168B_DD_STATUS_RESPONSE_DL_LOCKED) {
-+		c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+		c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+		return 0;
-+	}
-+
-+	/* read BER */
-+
-+	if (si2168b_read_ber(fe, &ber)) {
-+		c->block_error.stat[0].scale = FE_SCALE_COUNTER;
-+		c->block_error.stat[0].uvalue = ber;
-+		c->block_count.stat[0].scale = FE_SCALE_COUNTER;
-+		c->block_count.stat[0].uvalue = 0;
-+	} else {
-+		c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+		c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	}
-+
-+	return 0;
-+}
-+
-+static int si2168b_read_status(struct dvb_frontend *fe, enum fe_status *status)
-+{
-+	return si2168b_get_stats(fe, status);
-+}
-+
-+/************************************************************************************************************************
-+  NAME: Si2168B_L2_Channel_Seek_End
-+  DESCRIPTION: returns the chip back to normal use following a seek sequence
-+  Programming Guide Reference:    Flowchart TBD (Channel Scan flowchart)
-+
-+  Parameter:  Pointer to Si2168B Context
-+  Returns:    0 if successful, otherwise an error.
-+************************************************************************************************************************/
-+static int si2168b_channel_seek_end(struct dvb_frontend *fe)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	Si2168B_L2_Context *front_end = priv->si_front_end;
-+	const u8 dd_mode_bw = Si2168B_DD_MODE_PROP_BW_DEFAULT;
-+	const u8 dd_mode_invert_spectrum = Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_DEFAULT;
-+	u8 dd_mode_modulation = Si2168B_DD_MODE_PROP_MODULATION_DEFAULT;
-+	u8 dd_mode_auto_detect = Si2168B_DD_MODE_PROP_AUTO_DETECT_NONE;
-+    u16 data;
-+
-+	const u8 scan_ien_buzien = Si2168B_SCAN_IEN_PROP_BUZIEN_DISABLE ; /* (default 'DISABLE') */
-+	const u8 scan_ien_reqien = Si2168B_SCAN_IEN_PROP_REQIEN_DISABLE ; /* (default 'DISABLE') */
-+    data = (scan_ien_buzien & Si2168B_SCAN_IEN_PROP_BUZIEN_MASK) << Si2168B_SCAN_IEN_PROP_BUZIEN_LSB  |
-+           (scan_ien_reqien & Si2168B_SCAN_IEN_PROP_REQIEN_MASK) << Si2168B_SCAN_IEN_PROP_REQIEN_LSB ;
-+	si2168b_set_property(front_end->demod, Si2168B_SCAN_IEN_PROP, data);
-+
-+	switch (front_end->standard) {
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT:
-+		dd_mode_modulation = Si2168B_DD_MODE_PROP_MODULATION_DVBT;
-+		break;
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBC:
-+		dd_mode_modulation = Si2168B_DD_MODE_PROP_MODULATION_DVBC;
-+		break;
-+#ifdef __MCNS__
-+		case Si2168B_DD_MODE_PROP_MODULATION_MCNS:
-+		dd_mode_modulation = Si2168B_DD_MODE_PROP_MODULATION_MCNS;
-+		break;
-+#endif /* __MCNS__ */
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT2:
-+		dd_mode_modulation = Si2168B_DD_MODE_PROP_MODULATION_DVBT2;
-+		break;
-+	default:
-+		SiTRACE("UNKNOWN standard %d\n", front_end->standard);
-+		break;
-+	}
-+
-+	SiTRACE("auto_detect_TER %d\n",front_end->auto_detect_TER);
-+	if (front_end->auto_detect_TER) {
-+		switch (front_end->standard)	{
-+		case Si2168B_DD_MODE_PROP_MODULATION_DVBT:
-+		case Si2168B_DD_MODE_PROP_MODULATION_DVBT2:
-+			dd_mode_modulation  = Si2168B_DD_MODE_PROP_MODULATION_AUTO_DETECT;
-+			dd_mode_auto_detect = Si2168B_DD_MODE_PROP_AUTO_DETECT_AUTO_DVB_T_T2;
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+    data = (dd_mode_bw              & Si2168B_DD_MODE_PROP_BW_MASK             ) << Si2168B_DD_MODE_PROP_BW_LSB |
-+           (dd_mode_modulation      & Si2168B_DD_MODE_PROP_MODULATION_MASK     ) << Si2168B_DD_MODE_PROP_MODULATION_LSB |
-+           (dd_mode_invert_spectrum & Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_MASK) << Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_LSB |
-+           (dd_mode_auto_detect     & Si2168B_DD_MODE_PROP_AUTO_DETECT_MASK    ) << Si2168B_DD_MODE_PROP_AUTO_DETECT_LSB;
-+	si2168b_set_property(front_end->demod, Si2168B_DD_MODE_PROP, data);
-+
-+	return 0;
-+}
-+
-+/************************************************************************************************************************
-+  Si2168B_DVB_C_max_lock_ms function
-+  Use:        DVB-C lock time retrieval function
-+              Used to know how much time DVB-C lock will take in the worst case
-+************************************************************************************************************************/
-+static int si2168b_dvbc_max_lock_ms(si2168b_context *ctx, u8 constellation, u32 symbol_rate_baud)
-+{
-+	/* HG: replaced floating point operations by integer operations */
-+	/* calculation errors included now - but tolerated */
-+	u32 afc_khz = 100; /* (default 100 for DVB-C) */
-+	u32 swt;
-+	u32 swt_coeff;
-+	u32 lock_ms = 0;
-+
-+	/* To avoid division by 0, return 5000 if SR is 0 */
-+	if (symbol_rate_baud < 1000) {
-+		return 5000; /* HG: to avoid division by 0 */
-+	}
-+	if (afc_khz*1000 > symbol_rate_baud*11/100 ) {
-+		afc_khz = symbol_rate_baud*11/100000;
-+	}
-+	swt = (1 + (afc_khz* (22369621 / (symbol_rate_baud/1000)) / (symbol_rate_baud/1000) ) ) / 2;
-+	switch (constellation) {
-+	case Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM64:
-+	case Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM16:
-+	case Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM256:
-+		swt_coeff = 3;
-+		break;
-+	case Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM128:
-+		swt_coeff = 5;
-+		break;
-+	case Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_AUTO:
-+	default:
-+		swt_coeff = 11;
-+		break;
-+	}
-+	lock_ms = (720000000/symbol_rate_baud + swt*swt_coeff)+ 100;
-+	SiTRACE("afc_khz %3u, swt %6u, swt_coeff %u DVB_C_max_lock_ms %u\n", afc_khz, swt, swt_coeff, lock_ms);
-+	return lock_ms;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_DVBT2_PLP_SELECT COMMAND                 */
-+/*---------------------------------------------------*/
-+static u8 si2168b_dvbt2_plp_select(si2168b_context *ctx, u8 plp_id, u8 plp_id_sel_mode)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[3];
-+	u8 rspByteBuffer[1];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B DVBT2_PLP_SELECT ID=%u MODE=%u\n", plp_id, plp_id_sel_mode);
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DVBT2_PLP_SELECT_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( plp_id          & Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_MASK          ) << Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_LSB         );
-+	cmdByteBuffer[2] = (u8) ( ( plp_id_sel_mode & Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_SEL_MODE_MASK ) << Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_SEL_MODE_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 3, cmdByteBuffer) != 3) {
-+		SiTRACE("Error writing DVBT2_PLP_SELECT bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 1, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DVBT2_PLP_SELECT response\n");
-+		ret = error_code;
-+	}
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_DD_RESTART COMMAND                       */
-+/*---------------------------------------------------*/
-+static u8 si2168b_dd_restart(si2168b_context *ctx)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[1];
-+	u8 rspByteBuffer[1];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B DD_RESTART\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DD_RESTART_CMD;
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 1, cmdByteBuffer) != 1) {
-+		SiTRACE("Error writing DD_RESTART bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 1, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DD_RESTART response\n");
-+		ret = error_code;
-+	}
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/************************************************************************************************************************
-+  si2168b_standard_name function
-+  Use:        standard text retrieval function
-+              Used to retrieve the standard text used by the Si2168B
-+  Parameter:  standard, the value of the standard
-+************************************************************************************************************************/
-+static char *si2168b_standard_name(u8 standard)
-+{
-+	switch (standard) {
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT:
-+		return (char*)"DVB-T";
-+#ifdef __MCNS__
-+	case Si2168B_DD_MODE_PROP_MODULATION_MCNS:
-+		return (char*)"MCNS";
-+#endif /* __MCNS__ */
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBC:
-+		return (char*)"DVB-C";
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT2:
-+		return (char*)"DVB-T2";
-+	default:
-+		return (char*)"UNKNOWN";
-+	}
-+}
-+
-+/************************************************************************************************************************
-+  si2168b_ter_fef function
-+  Use:        TER tuner FEF activation function
-+              Used to enable/disable the FEF mode in the terrestrial tuner
-+  Comments:   If the tuner is connected via the demodulator's I2C switch, enabling/disabling the i2c_passthru is required before/after tuning.
-+  Parameter:  *front_end, the front-end handle
-+  Parameter:  fef, a flag controlling the selection between FEF 'off'(0) and FEF 'on'(1)
-+  Returns:    1
-+************************************************************************************************************************/
-+static int si2168b_ter_fef(Si2168B_L2_Context *front_end, u8 fef)
-+{
-+	SiTRACE("si2168b_ter_fef %d\n", fef);
-+
-+	if (front_end->demod->fef_mode == Si2168B_FEF_MODE_FREEZE_PIN) {
-+		SiTRACE("FEF mode Si2168B_FEF_MODE_FREEZE_PIN\n");
-+		/* handled in tuner module now */
-+	}
-+
-+#ifdef    L1_RF_TER_TUNER_FEF_MODE_SLOW_INITIAL_AGC_SETUP
-+	if (front_end->demod->fef_mode == Si2168B_FEF_MODE_SLOW_INITIAL_AGC) {
-+		SiTRACE("FEF mode Si2168B_FEF_MODE_SLOW_INITIAL_AGC (AGC slowed down after tuning)\n");
-+	}
-+#endif /* L1_RF_TER_TUNER_FEF_MODE_SLOW_INITIAL_AGC_SETUP */
-+
-+#ifdef    L1_RF_TER_TUNER_FEF_MODE_SLOW_NORMAL_AGC_SETUP
-+	if (front_end->demod->fef_mode == Si2168B_FEF_MODE_SLOW_NORMAL_AGC ) {
-+		SiTRACE("FEF mode Si2168B_FEF_MODE_SLOW_NORMAL_AGC: AGC slowed down\n");
-+		/* handled in tuner module now */
-+	}
-+#endif /* L1_RF_TER_TUNER_FEF_MODE_SLOW_NORMAL_AGC_SETUP */
-+
-+	return 1;
-+}
-+
-+/************************************************************************************************************************
-+  si2168b_tune function
-+  Use:        tuner current frequency retrieval function
-+              Used to retrieve the current RF from the tuner's driver.
-+  Porting:    Replace the internal TUNER function calls by the final tuner's corresponding calls
-+  Comments:   If the tuner is connected via the demodulator's I2C switch, enabling/disabling the i2c_passthru is required before/after tuning.
-+  Behavior:   This function closes the Si2168B's I2C switch then tunes and finally reopens the I2C switch
-+  Parameter:  *front_end, the front-end handle
-+  Parameter:  rf, the frequency to tune at
-+  Returns:    rf
-+************************************************************************************************************************/
-+static u32 si2168b_set_tuner_params(struct dvb_frontend *fe, u32 rf)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	Si2168B_L2_Context *front_end = priv->si_front_end;
-+	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
-+
-+	SiTRACE("si2168b_set_tuner_params() frequency=%u\n", rf);
-+
-+	if (front_end->tuner_indirect_i2c_connection) {  /* INDIRECT_I2C_CONNECTION? */
-+		/*  I2C connection will be done later on, depending on the media */
-+	} else {
-+		si2168b_tuner_i2c_enable(front_end);
-+	}
-+
-+	if (front_end->demod->media == Si2168B_TERRESTRIAL) {
-+		if ( front_end->tuner_indirect_i2c_connection ) {  /* INDIRECT_I2C_CONNECTION? */
-+			front_end->f_TER_tuner_enable(front_end->callback);
-+		}
-+		c->frequency = rf;
-+		if (fe->ops.tuner_ops.set_params) {
-+			if (fe->ops.tuner_ops.set_params(fe)) {
-+				SiTRACE("Terrestrial tuner set_params() error!\n");
-+			}
-+		} else {
-+			SiTRACE("WARNING: set_params() not available\n");
-+		}
-+		if ( front_end->tuner_indirect_i2c_connection ) {  /* INDIRECT_I2C_CONNECTION? */
-+			front_end->f_TER_tuner_disable(front_end->callback);
-+		}
-+	}
-+	if ( front_end->tuner_indirect_i2c_connection ) {  /* INDIRECT_I2C_CONNECTION? */
-+	} else {
-+		si2168b_tuner_i2c_disable(front_end);
-+	}
-+
-+	return rf;
-+}
-+
-+/************************************************************************************************************************
-+  Si2168B_lock_to_carrier function
-+  Use:      relocking function
-+            Used to relock on a channel for the current standard
-+            options:
-+              if freq = 0, do not tune. This is useful to test the lock time without the tuner delays.
-+              if freq < 0, do not tune and don't change settings. Just do a DD_RESTART. This is useful to test the relock time upom a reset.
-+  Parameter: standard the standard to lock to
-+  Parameter: freq                the frequency to lock to    (in Hz for TER, in kHz for SAT)
-+  Parameter: dvb_t_bandwidth_hz  the channel bandwidth in Hz (only for DVB-T and DVB-T2)
-+  Parameter: dvb_t_stream        the HP/LP stream            (only for DVB-T)
-+  Parameter: symbol_rate_bps     the symbol rate             (for DVB-C, MCNS and SAT)
-+  Parameter: dvb_c_constellation the DVB-C constellation     (only for DVB-C)
-+  Parameter: data_slice_id       the DVB-C2 data slice Id    (only for DVB-C2)
-+  Parameter: plp_id              the PLP Id                  (only for DVB-T2 and DVB-C2 when num_dslice  > 1)
-+  Parameter: T2_lock_mode        the DVB-T2 lock mode        (0='ANY', 1='T2-Base', 2='T2-Lite')
-+  Return:    1 if locked, 0 otherwise
-+************************************************************************************************************************/
-+static int si2168b_lock_to_carrier(struct dvb_frontend *fe
-+		, u8  standard
-+		, u32 freq
-+		, u32 dvb_t_bandwidth_hz
-+		, u8  dvb_t_stream
-+		, u32 symbol_rate_bps
-+		, u8  dvb_c_constellation
-+		, int plp_id
-+		, u8  T2_lock_mode
-+)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	Si2168B_L2_Context *front_end = priv->si_front_end;
-+	Si2168B_DD_STATUS_CMD_REPLY_struct dd_status;
-+	Si2168B_DD_BER_CMD_REPLY_struct dd_ber;
-+
-+	int return_code;
-+	u32 lock_start_time;       /* lockStartTime is used to trace the time spent in si2168b_lock_to_carrier and is only set at when entering the function                       */
-+	u32 start_time;           /* startTime is used to measure internal durations. It is set in various places, whenever required                                                */
-+	u32 search_start_time = 0; /* searchStartTime is used to trace the time spent trying to lock. It is set differently from lockStartTime when returning from a handshake       */
-+	u32 search_delay;
-+	u32 handshake_delay;
-+	int lock;
-+	int new_lock;
-+	u32 max_lock_time_ms = 0;
-+	u32 min_lock_time_ms = 0;
-+	u16 data;
-+	u8  dd_mode_bw;
-+	u8  dd_mode_modulation;
-+	u8  dd_mode_invert_spectrum = Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_NORMAL;
-+	u8  dd_mode_auto_detect = Si2168B_DD_MODE_PROP_AUTO_DETECT_NONE;
-+	u8  dvbt_hierarchy_stream;
-+	u8  dvbt2_mode_lock_mode;
-+	u8  u_plp_id;
-+	u8  plp_id_sel_mode;
-+	u16 dvbc_symbol_rate_rate;
-+	u8  dvbc_constellation_constellation;
-+#ifdef __MCNS__
-+	u16 mcns_symbol_rate_rate;
-+	u8  mcns_constellation_constellation;
-+#endif /* __MCNS__ */
-+	u8  dvbt2_plp_select_plp_id;
-+	u8  dvbt2_plp_select_plp_id_sel_mode;
-+	u8  lockAbort = 0;
-+
-+	lock_start_time = system_time(); /* lockStartTime is used to trace the time spent in si2168b_lock_to_carrier and is only set here */
-+	lock = 0;
-+
-+	SiTRACE ("relock to %s at %u\n", si2168b_standard_name(standard), freq);
-+
-+	if (front_end->handshakeUsed == 0) {
-+		new_lock = 1;
-+		search_start_time = lock_start_time;
-+	}
-+	if (front_end->handshakeUsed == 1) {
-+		if (front_end->handshakeOn == 1) {
-+			new_lock = 0;
-+			SiTRACE("lock_to_carrier_handshake : recalled after   handshake.\n");
-+		}
-+		if (front_end->handshakeOn == 0) {
-+			new_lock = 1;
-+			front_end->handshakeStart_ms = lock_start_time;
-+		}
-+		search_start_time = front_end->handshakeStart_ms;
-+		SiTRACE("lock_to_carrier_handshake : handshake start %d\n", front_end->handshakeStart_ms);
-+	}
-+
-+	/* Setting max_lock_time_ms and min_lock_time_ms for locking on required standard */
-+	switch (standard) {
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT:
-+		max_lock_time_ms = Si2168B_DVBT_MAX_LOCK_TIME;
-+		min_lock_time_ms = Si2168B_DVBT_MIN_LOCK_TIME;
-+		if (front_end->auto_detect_TER) {
-+			max_lock_time_ms = Si2168B_DVBT2_MAX_LOCK_TIME;
-+		}
-+		break;
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT2:
-+		max_lock_time_ms = Si2168B_DVBT2_MAX_LOCK_TIME;
-+		min_lock_time_ms = Si2168B_DVBT2_MIN_LOCK_TIME;
-+		if (front_end->auto_detect_TER) {
-+			min_lock_time_ms = Si2168B_DVBT_MIN_LOCK_TIME;
-+		}
-+		break;
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBC:
-+		max_lock_time_ms = si2168b_dvbc_max_lock_ms(front_end->demod, dvb_c_constellation, symbol_rate_bps);
-+		min_lock_time_ms = Si2168B_DVBC_MIN_LOCK_TIME;
-+		break;
-+#ifdef __MCNS__
-+	case Si2168B_DD_MODE_PROP_MODULATION_MCNS:
-+		max_lock_time_ms = si2168b_dvbc_max_lock_ms(front_end->demod, dvb_c_constellation, symbol_rate_bps);
-+		min_lock_time_ms = Si2168B_DVBC_MIN_LOCK_TIME;
-+		break;
-+#endif /* __MCNS__ */
-+	default: /* ATV */
-+		break;
-+	}
-+
-+	/* change settings only if not testing the relock time upon a reset (activated if freq<0) */
-+	if ( (freq >= 0 ) && (new_lock == 1) ) {
-+		/* Setting demod for locking on required standard */
-+		switch (standard) {
-+		case Si2168B_DD_MODE_PROP_MODULATION_DVBT2:
-+		case Si2168B_DD_MODE_PROP_MODULATION_DVBT: {
-+			dd_mode_bw = dvb_t_bandwidth_hz / 1000000;
-+			dvbt_hierarchy_stream = dvb_t_stream;
-+			data = (dvbt_hierarchy_stream & Si2168B_DVBT_HIERARCHY_PROP_STREAM_MASK) << Si2168B_DVBT_HIERARCHY_PROP_STREAM_LSB;
-+			return_code = si2168b_set_property(front_end->demod, Si2168B_DVBT_HIERARCHY_PROP, data);
-+			if (dvb_t_bandwidth_hz == 1700000) {
-+				dd_mode_bw = Si2168B_DD_MODE_PROP_BW_BW_1D7MHZ;
-+			}
-+			if (front_end->auto_detect_TER) {
-+				SiTRACE("DVB-T/T2 auto detect\n");
-+				if (plp_id != -1) {
-+					plp_id_sel_mode = Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_SEL_MODE_MANUAL;
-+					u_plp_id = (u8)plp_id;
-+				} else {
-+					plp_id_sel_mode = Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_SEL_MODE_AUTO;
-+					u_plp_id = 0;
-+				}
-+				si2168b_dvbt2_plp_select(front_end->demod, u_plp_id, plp_id_sel_mode);
-+				dd_mode_modulation   = Si2168B_DD_MODE_PROP_MODULATION_AUTO_DETECT;
-+				dd_mode_auto_detect  = Si2168B_DD_MODE_PROP_AUTO_DETECT_AUTO_DVB_T_T2;
-+				dvbt2_mode_lock_mode = T2_lock_mode;
-+				data = (dvbt2_mode_lock_mode & Si2168B_DVBT2_MODE_PROP_LOCK_MODE_MASK) << Si2168B_DVBT2_MODE_PROP_LOCK_MODE_LSB ;
-+				si2168b_set_property(front_end->demod, Si2168B_DVBT2_MODE_PROP, data);
-+				SiTRACE ("T2_lock_mode %u\n", T2_lock_mode);
-+			} else {
-+				if (standard == Si2168B_DD_MODE_PROP_MODULATION_DVBT) {
-+					dvbt_hierarchy_stream = dvb_t_stream;
-+					data = (dvbt_hierarchy_stream & Si2168B_DVBT_HIERARCHY_PROP_STREAM_MASK) << Si2168B_DVBT_HIERARCHY_PROP_STREAM_LSB;
-+					return_code = si2168b_set_property(front_end->demod, Si2168B_DVBT_HIERARCHY_PROP, data);
-+				}
-+				if (standard == Si2168B_DD_MODE_PROP_MODULATION_DVBT2) {
-+					if (plp_id != -1) {
-+						dvbt2_plp_select_plp_id_sel_mode = Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_SEL_MODE_MANUAL;
-+						dvbt2_plp_select_plp_id = (u8)plp_id;
-+					} else {
-+						dvbt2_plp_select_plp_id_sel_mode = Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_SEL_MODE_AUTO;
-+						dvbt2_plp_select_plp_id = 0;
-+					}
-+					si2168b_dvbt2_plp_select(front_end->demod, dvbt2_plp_select_plp_id, dvbt2_plp_select_plp_id_sel_mode);
-+					dvbt2_mode_lock_mode = T2_lock_mode;
-+					data = (dvbt2_mode_lock_mode & Si2168B_DVBT2_MODE_PROP_LOCK_MODE_MASK) << Si2168B_DVBT2_MODE_PROP_LOCK_MODE_LSB ;
-+					si2168b_set_property(front_end->demod, Si2168B_DVBT2_MODE_PROP, data);
-+					SiTRACE ("T2_lock_mode %d\n", T2_lock_mode);
-+				}
-+			}
-+			data = (dd_mode_bw              & Si2168B_DD_MODE_PROP_BW_MASK             ) << Si2168B_DD_MODE_PROP_BW_LSB  |
-+					(dd_mode_modulation      & Si2168B_DD_MODE_PROP_MODULATION_MASK     ) << Si2168B_DD_MODE_PROP_MODULATION_LSB  |
-+					(dd_mode_invert_spectrum & Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_MASK) << Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_LSB  |
-+					(dd_mode_auto_detect     & Si2168B_DD_MODE_PROP_AUTO_DETECT_MASK    ) << Si2168B_DD_MODE_PROP_AUTO_DETECT_LSB ;
-+			si2168b_set_property(front_end->demod, Si2168B_DD_MODE_PROP, data);
-+			SiTRACE("bw %d Hz\n", dvb_t_bandwidth_hz);
-+			break;
-+		}
-+		case Si2168B_DD_MODE_PROP_MODULATION_DVBC:
-+			dd_mode_bw                       = 8;
-+			dd_mode_modulation   = Si2168B_DD_MODE_PROP_MODULATION_DVBC;
-+			dd_mode_auto_detect  = Si2168B_DD_MODE_PROP_AUTO_DETECT_DEFAULT;
-+			dvbc_symbol_rate_rate            = symbol_rate_bps / 1000;
-+			dvbc_constellation_constellation = dvb_c_constellation;
-+			data = (dd_mode_bw              & Si2168B_DD_MODE_PROP_BW_MASK             ) << Si2168B_DD_MODE_PROP_BW_LSB  |
-+					(dd_mode_modulation      & Si2168B_DD_MODE_PROP_MODULATION_MASK     ) << Si2168B_DD_MODE_PROP_MODULATION_LSB  |
-+					(dd_mode_invert_spectrum & Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_MASK) << Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_LSB  |
-+					(dd_mode_auto_detect     & Si2168B_DD_MODE_PROP_AUTO_DETECT_MASK    ) << Si2168B_DD_MODE_PROP_AUTO_DETECT_LSB ;
-+			si2168b_set_property(front_end->demod, Si2168B_DD_MODE_PROP, data);
-+			data = (dvbc_symbol_rate_rate & Si2168B_DVBC_SYMBOL_RATE_PROP_RATE_MASK) << Si2168B_DVBC_SYMBOL_RATE_PROP_RATE_LSB ;
-+			si2168b_set_property(front_end->demod, Si2168B_DVBC_SYMBOL_RATE_PROP, data);
-+			data = (dvbc_constellation_constellation & Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_MASK) << Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_LSB ;
-+			si2168b_set_property(front_end->demod, Si2168B_DVBC_CONSTELLATION_PROP, data);
-+			SiTRACE("sr %d bps, constel %d\n", symbol_rate_bps, dvb_c_constellation);
-+			break;
-+#ifdef __MCNS__
-+		case Si2168B_DD_MODE_PROP_MODULATION_MCNS:
-+			dd_mode_bw                       = 8;
-+			mcns_symbol_rate_rate            = symbol_rate_bps / 1000;
-+			mcns_constellation_constellation = dvb_c_constellation;
-+			si2168b_set_property(front_end->demod, Si2168B_DD_MODE_PROP, data);
-+			data = (mcns_symbol_rate_rate & Si2168B_MCNS_SYMBOL_RATE_PROP_RATE_MASK) << Si2168B_MCNS_SYMBOL_RATE_PROP_RATE_LSB ;
-+			si2168b_set_property(front_end->demod, Si2168B_MCNS_SYMBOL_RATE_PROP, data);
-+			data = (mcns_constellation_constellation & Si2168B_MCNS_CONSTELLATION_PROP_CONSTELLATION_MASK) << Si2168B_MCNS_CONSTELLATION_PROP_CONSTELLATION_LSB ;
-+			si2168b_set_property(front_end->demod, Si2168B_MCNS_CONSTELLATION_PROP, data);
-+			SiTRACE("sr %d bps, constel %d\n", mcns_symbol_rate_rate, mcns_constellation_constellation);
-+			break;
-+#endif /* __MCNS__ */
-+		default: /* ATV */
-+			SiTRACE("'%d' standard (%s) is not managed by Si2168B_lock_to_carrier\n", standard, si2168b_standard_name(standard));
-+			return 0;
-+			break;
-+		}
-+
-+		if (lockAbort) {
-+			SiTRACE("si2168b_lock_to_carrier : lock aborted before tuning, after %d ms.\n", system_time() - lock_start_time );
-+			return 0;
-+		}
-+
-+		/* ALlow using this function without tuning */
-+		if (freq != 0) {
-+			start_time = system_time();
-+			si2168b_set_tuner_params(fe, freq);
-+			SiTRACE("Si2168B_lock_to_carrier 'tune'  took %3d ms\n", system_time() - start_time);
-+		}
-+
-+		start_time = system_time();
-+		si2168b_dd_restart(front_end->demod);
-+		SiTRACE("Si2168B_lock_to_carrier 'reset' took %3d ms\n", system_time() - start_time);
-+
-+		/* as we will not lock in less than min_lock_time_ms, wait a while..., but check for a possible 'abort' from the application */
-+		start_time = system_time();
-+		while (system_time() - start_time < min_lock_time_ms) {
-+			if (lockAbort) {
-+				SiTRACE("si2168b_lock_to_carrier : lock aborted before checking lock status, after %d ms.\n", system_time() - lock_start_time);
-+				return 0;
-+			}
-+			/* Adapt here the minimal 'reaction time' of the application*/
-+			msleep(20);
-+		}
-+	}
-+	/* testing the relock time upon a reset (activated if freq<0) */
-+	if (freq < 0) {
-+		SiTRACE("Si2168B_lock_to_carrier 'only_reset'\n");
-+		si2168b_dd_restart(front_end->demod);
-+	}
-+
-+	/* The actual lock check loop */
-+	while (1) {
-+		search_delay = system_time() - search_start_time;
-+
-+		/* Check the status for the current modulation */
-+
-+		switch (standard)
-+		default:
-+		case Si2168B_DD_MODE_PROP_MODULATION_DVBT:
-+		case Si2168B_DD_MODE_PROP_MODULATION_DVBT2: {
-+			/* DVB-T/T2 auto detect seek loop, using si2168b_dd_status                                          */
-+			/* if DL LOCKED                            : demod is locked on a dd_status->modulation signal        */
-+			/* if DL NO_LOCK and rsqint_bit5 NO_CHANGE : demod is searching for a DVB-T/T2 signal                 */
-+			/* if DL NO_LOCK and rsqint_bit5 CHANGE    : demod says this is not a DVB-T/T2 signal (= 'neverlock') */
-+			return_code = si2168b_dd_status(front_end->demod, Si2168B_DD_STATUS_CMD_INTACK_CLEAR, &dd_status);
-+			if (return_code != NO_Si2168B_ERROR) {
-+				SiTRACE("Si2168B_lock_to_carrier: si2168b_dd_status error\n");
-+				goto exit_lock;
-+				break;
-+			}
-+
-+			if (dd_status.dl == Si2168B_DD_STATUS_RESPONSE_DL_LOCKED) {
-+				/* Return 1 to signal that the Si2168B is locked on a valid DVB-T/T2 channel */
-+				SiTRACE("Si2168B_lock_to_carrier: locked on a %s signal\n", si2168b_standard_name(dd_status.modulation) );
-+				lock = 1;
-+				/* Make sure FEF mode is ON when locked on a T2 channel */
-+				if (dd_status.modulation == Si2168B_DD_MODE_PROP_MODULATION_DVBT2) {
-+					if (front_end->tuner_indirect_i2c_connection ) {  /* INDIRECT_I2C_CONNECTION? */
-+						front_end->f_TER_tuner_enable(front_end->callback);
-+					} else {
-+						si2168b_tuner_i2c_enable(front_end);
-+					}
-+					SiTRACE("Si2168B_lock_to_carrier: tuner should enable FEF for DVBT2\n");
-+					si2168b_ter_fef(front_end, 1);
-+					if ( front_end->tuner_indirect_i2c_connection ) {  /* INDIRECT_I2C_CONNECTION? */
-+						front_end->f_TER_tuner_disable(front_end->callback);
-+					} else {
-+						si2168b_tuner_i2c_disable(front_end);
-+					}
-+				}
-+				goto exit_lock;
-+			} else {
-+				/* SiTRACE("Si2168B_lock_to_carrier: NO LOCK\n"); */
-+				if (dd_status.rsqint_bit5 == Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT5_CHANGED ) {
-+					/* Return 0 if firmware signals 'no DVB-T/T2 channel' */
-+					SiTRACE ("'no DVB-T/T2 channel': not locked after %3d ms\n", search_delay);
-+					goto exit_lock;
-+				}
-+			}
-+			break;
-+		case Si2168B_DD_MODE_PROP_MODULATION_DVBC:
-+			return_code = si2168b_dd_status(front_end->demod, Si2168B_DD_STATUS_CMD_INTACK_CLEAR, &dd_status);
-+
-+			if (return_code != NO_Si2168B_ERROR) {
-+				SiTRACE("Si2168B_lock_to_carrier: si2168b_dd_status error\n");
-+				goto exit_lock;
-+				break;
-+			}
-+
-+			if (dd_status.dl == Si2168B_DD_STATUS_RESPONSE_DL_LOCKED) {
-+				/* Return 1 to signal that the Si2168B is locked on a valid SAT channel */
-+				SiTRACE("%s lock\n", si2168b_standard_name(dd_status.modulation));
-+				lock = 1;
-+				goto exit_lock;
-+			}
-+			break;
-+#ifdef __MCNS__
-+		case Si2168B_DD_MODE_PROP_MODULATION_MCNS:
-+			return_code = si2168b_dd_status(front_end->demod, Si2168B_DD_STATUS_CMD_INTACK_CLEAR, &dd_status);
-+
-+			if (return_code != NO_Si2168B_ERROR) {
-+				SiTRACE("Si2168B_lock_to_carrier: si2168b_dd_status error\n");
-+				goto exit_lock;
-+				break;
-+			}
-+
-+			if (dd_status.dl == Si2168B_DD_STATUS_RESPONSE_DL_LOCKED) {
-+				/* Return 1 to signal that the Si2168B is locked on a valid SAT channel */
-+				SiTRACE("%s lock\n", si2168b_standard_name(dd_status.modulation));
-+				lock = 1;
-+				goto exit_lock;
-+			}
-+			break;
-+#endif /* __MCNS__ */
-+		}
-+
-+		/* timeout management (this should never happen if timeout values are correctly set) */
-+		search_delay = system_time() - search_start_time;
-+		if (search_delay >= max_lock_time_ms) {
-+			SiTRACE ("Si2168B_lock_to_carrier timeout(%d) after %d ms\n", max_lock_time_ms, search_delay);
-+			goto exit_lock;
-+			break;
-+		}
-+
-+		if (front_end->handshakeUsed == 1) {
-+			handshake_delay = system_time() - lock_start_time;
-+			if (handshake_delay >= front_end->handshakePeriod_ms) {
-+				SiTRACE ("lock_to_carrier_handshake : handshake after %5d ms (at %10d). (search delay %6d ms)\n\n", handshake_delay, freq, search_delay);
-+				front_end->handshakeOn = 1;
-+				/* The application will check handshakeStart_ms to know whether the lock is complete or not */
-+				return search_delay;
-+			} else {
-+				SiTRACE ("lock_to_carrier_handshake : no handshake yet. (handshake delay %6d ms, search delay %6d ms)\n", handshake_delay, search_delay);
-+			}
-+		}
-+
-+		if (lockAbort) {
-+			SiTRACE("si2168b_lock_to_carrier : lock aborted after %d ms.\n", system_time() - lock_start_time);
-+			goto exit_lock;
-+		}
-+
-+		/* Check status every 10 ms */
-+		msleep(5);
-+	}
-+
-+	exit_lock:
-+
-+	front_end->handshakeOn = 0;
-+	search_delay = system_time() - search_start_time;
-+
-+	if (lock) {
-+		si2168b_dd_ber(front_end->demod, Si2168B_DD_BER_CMD_RST_CLEAR, &dd_ber);
-+		SiTRACE ("Si2168B_lock_to_carrier 'lock'  took %3d ms\n", search_delay);
-+	} else {
-+		SiTRACE ("Si2168B_lock_to_carrier at %10d (%s) failed after %d ms\n", freq, si2168b_standard_name(dd_status.modulation), search_delay);
-+	}
-+
-+	return lock;
-+}
-+
-+/***********************************************************************************************************************
-+  si2168b_check_status function
-+  Use:        Status information function
-+              Used to retrieve the status byte
-+  Returns:    0 if no error
-+  Parameter:  error_code the error code.
-+ ***********************************************************************************************************************/
-+static u8 si2168b_check_status(si2168b_context *ctx)
-+{
-+    u8 rspByteBuffer[1];
-+    u8 ret;
-+
-+	_mutex_lock(&ctx->lock);
-+    ret = si2168b_poll_for_response(ctx, 1, rspByteBuffer);
-+	_mutex_unlock(&ctx->lock);
-+    return ret;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_SCAN_STATUS COMMAND                      */
-+/*---------------------------------------------------*/
-+static u8 si2168b_scan_status(si2168b_context *ctx, u8 intack, Si2168B_SCAN_STATUS_CMD_REPLY_struct *scan_status)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[11];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B SCAN_STATUS\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_SCAN_STATUS_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( intack & Si2168B_SCAN_STATUS_CMD_INTACK_MASK ) << Si2168B_SCAN_STATUS_CMD_INTACK_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing SCAN_STATUS bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 11, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling SCAN_STATUS response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	scan_status->buzint      =   (( ( (rspByteBuffer[1]  )) >> Si2168B_SCAN_STATUS_RESPONSE_BUZINT_LSB      ) & Si2168B_SCAN_STATUS_RESPONSE_BUZINT_MASK      );
-+	scan_status->reqint      =   (( ( (rspByteBuffer[1]  )) >> Si2168B_SCAN_STATUS_RESPONSE_REQINT_LSB      ) & Si2168B_SCAN_STATUS_RESPONSE_REQINT_MASK      );
-+	scan_status->buz         =   (( ( (rspByteBuffer[2]  )) >> Si2168B_SCAN_STATUS_RESPONSE_BUZ_LSB         ) & Si2168B_SCAN_STATUS_RESPONSE_BUZ_MASK         );
-+	scan_status->req         =   (( ( (rspByteBuffer[2]  )) >> Si2168B_SCAN_STATUS_RESPONSE_REQ_LSB         ) & Si2168B_SCAN_STATUS_RESPONSE_REQ_MASK         );
-+	scan_status->scan_status =   (( ( (rspByteBuffer[3]  )) >> Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_LSB ) & Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_MASK );
-+	scan_status->rf_freq     =   (( ( (rspByteBuffer[4]  ) | (rspByteBuffer[5]  << 8 ) | (rspByteBuffer[6]  << 16 ) | (rspByteBuffer[7]  << 24 )) >> Si2168B_SCAN_STATUS_RESPONSE_RF_FREQ_LSB     ) & Si2168B_SCAN_STATUS_RESPONSE_RF_FREQ_MASK     );
-+	scan_status->symb_rate   =   (( ( (rspByteBuffer[8]  ) | (rspByteBuffer[9]  << 8 )) >> Si2168B_SCAN_STATUS_RESPONSE_SYMB_RATE_LSB   ) & Si2168B_SCAN_STATUS_RESPONSE_SYMB_RATE_MASK   );
-+	scan_status->modulation  =   (( ( (rspByteBuffer[10] )) >> Si2168B_SCAN_STATUS_RESPONSE_MODULATION_LSB  ) & Si2168B_SCAN_STATUS_RESPONSE_MODULATION_MASK  );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+#ifdef __MCNS__
-+/*---------------------------------------------------*/
-+/* Si2168B_MCNS_STATUS COMMAND                      */
-+/*---------------------------------------------------*/
-+static u8 si2168b_mcns_status(si2168b_context *ctx, u8 intack)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[10];
-+	u8 ret = NO_Si2168B_ERROR;
-+	ctx->rsp->mcns_status.STATUS = ctx->status;
-+
-+	SiTRACE("Si2168B MCNS_STATUS\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_MCNS_STATUS_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( intack & Si2168B_MCNS_STATUS_CMD_INTACK_MASK ) << Si2168B_MCNS_STATUS_CMD_INTACK_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing MCNS_STATUS bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 10, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling MCNS_STATUS response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	ctx->rsp->mcns_status.pclint        =   (( ( (rspByteBuffer[1]  )) >> Si2168B_MCNS_STATUS_RESPONSE_PCLINT_LSB        ) & Si2168B_MCNS_STATUS_RESPONSE_PCLINT_MASK        );
-+	ctx->rsp->mcns_status.dlint         =   (( ( (rspByteBuffer[1]  )) >> Si2168B_MCNS_STATUS_RESPONSE_DLINT_LSB         ) & Si2168B_MCNS_STATUS_RESPONSE_DLINT_MASK         );
-+	ctx->rsp->mcns_status.berint        =   (( ( (rspByteBuffer[1]  )) >> Si2168B_MCNS_STATUS_RESPONSE_BERINT_LSB        ) & Si2168B_MCNS_STATUS_RESPONSE_BERINT_MASK        );
-+	ctx->rsp->mcns_status.uncorint      =   (( ( (rspByteBuffer[1]  )) >> Si2168B_MCNS_STATUS_RESPONSE_UNCORINT_LSB      ) & Si2168B_MCNS_STATUS_RESPONSE_UNCORINT_MASK      );
-+	ctx->rsp->mcns_status.pcl           =   (( ( (rspByteBuffer[2]  )) >> Si2168B_MCNS_STATUS_RESPONSE_PCL_LSB           ) & Si2168B_MCNS_STATUS_RESPONSE_PCL_MASK           );
-+	ctx->rsp->mcns_status.dl            =   (( ( (rspByteBuffer[2]  )) >> Si2168B_MCNS_STATUS_RESPONSE_DL_LSB            ) & Si2168B_MCNS_STATUS_RESPONSE_DL_MASK            );
-+	ctx->rsp->mcns_status.ber           =   (( ( (rspByteBuffer[2]  )) >> Si2168B_MCNS_STATUS_RESPONSE_BER_LSB           ) & Si2168B_MCNS_STATUS_RESPONSE_BER_MASK           );
-+	ctx->rsp->mcns_status.uncor         =   (( ( (rspByteBuffer[2]  )) >> Si2168B_MCNS_STATUS_RESPONSE_UNCOR_LSB         ) & Si2168B_MCNS_STATUS_RESPONSE_UNCOR_MASK         );
-+	ctx->rsp->mcns_status.cnr           =   (( ( (rspByteBuffer[3]  )) >> Si2168B_MCNS_STATUS_RESPONSE_CNR_LSB           ) & Si2168B_MCNS_STATUS_RESPONSE_CNR_MASK           );
-+	ctx->rsp->mcns_status.afc_freq      = (((( ( (rspByteBuffer[4]  ) | (rspByteBuffer[5]  << 8 )) >> Si2168B_MCNS_STATUS_RESPONSE_AFC_FREQ_LSB      ) & Si2168B_MCNS_STATUS_RESPONSE_AFC_FREQ_MASK) <<Si2168B_MCNS_STATUS_RESPONSE_AFC_FREQ_SHIFT ) >>Si2168B_MCNS_STATUS_RESPONSE_AFC_FREQ_SHIFT      );
-+	ctx->rsp->mcns_status.timing_offset = (((( ( (rspByteBuffer[6]  ) | (rspByteBuffer[7]  << 8 )) >> Si2168B_MCNS_STATUS_RESPONSE_TIMING_OFFSET_LSB ) & Si2168B_MCNS_STATUS_RESPONSE_TIMING_OFFSET_MASK) <<Si2168B_MCNS_STATUS_RESPONSE_TIMING_OFFSET_SHIFT ) >>Si2168B_MCNS_STATUS_RESPONSE_TIMING_OFFSET_SHIFT );
-+	ctx->rsp->mcns_status.constellation =   (( ( (rspByteBuffer[8]  )) >> Si2168B_MCNS_STATUS_RESPONSE_CONSTELLATION_LSB ) & Si2168B_MCNS_STATUS_RESPONSE_CONSTELLATION_MASK );
-+	ctx->rsp->mcns_status.sp_inv        =   (( ( (rspByteBuffer[8]  )) >> Si2168B_MCNS_STATUS_RESPONSE_SP_INV_LSB        ) & Si2168B_MCNS_STATUS_RESPONSE_SP_INV_MASK        );
-+	ctx->rsp->mcns_status.interleaving  =   (( ( (rspByteBuffer[9]  )) >> Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_LSB  ) & Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_MASK  );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif /* __MCNS__ */
-+
-+/************************************************************************************************************************
-+  NAME: si2168b_set_invert_spectrum
-+  DESCRIPTION: return the required invert_spectrum value depending on the settings:
-+              front_end->demod->media
-+              front_end->satellite_spectrum_inversion
-+              front_end->lnb_type
-+              front_end->unicable_spectrum_inversion
-+
-+  Parameter:  Pointer to Si2168B Context
-+  Returns:    the required invert_spectrum value
-+************************************************************************************************************************/
-+static u8 si2168b_set_invert_spectrum(Si2168B_L2_Context *front_end)
-+{
-+	u8 inversion;
-+
-+	if (front_end->demod->media == Si2168B_TERRESTRIAL) {
-+		inversion = Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_NORMAL;
-+	}
-+	return inversion;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_SCAN_CTRL COMMAND                        */
-+/*---------------------------------------------------*/
-+static u8 si2168b_scan_ctrl(si2168b_context *ctx,
-+		u8 action,
-+		u32 tuned_rf_freq)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[8];
-+	u8 rspByteBuffer[1];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B SCAN_CTRL\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_SCAN_CTRL_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( action        & Si2168B_SCAN_CTRL_CMD_ACTION_MASK        ) << Si2168B_SCAN_CTRL_CMD_ACTION_LSB);
-+	cmdByteBuffer[2] = (u8)0x00;
-+	cmdByteBuffer[3] = (u8)0x00;
-+	cmdByteBuffer[4] = (u8) ( ( tuned_rf_freq & Si2168B_SCAN_CTRL_CMD_TUNED_RF_FREQ_MASK ) << Si2168B_SCAN_CTRL_CMD_TUNED_RF_FREQ_LSB);
-+	cmdByteBuffer[5] = (u8) ((( tuned_rf_freq & Si2168B_SCAN_CTRL_CMD_TUNED_RF_FREQ_MASK ) << Si2168B_SCAN_CTRL_CMD_TUNED_RF_FREQ_LSB)>>8);
-+	cmdByteBuffer[6] = (u8) ((( tuned_rf_freq & Si2168B_SCAN_CTRL_CMD_TUNED_RF_FREQ_MASK ) << Si2168B_SCAN_CTRL_CMD_TUNED_RF_FREQ_LSB)>>16);
-+	cmdByteBuffer[7] = (u8) ((( tuned_rf_freq & Si2168B_SCAN_CTRL_CMD_TUNED_RF_FREQ_MASK ) << Si2168B_SCAN_CTRL_CMD_TUNED_RF_FREQ_LSB)>>24);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 8, cmdByteBuffer) != 8) {
-+		SiTRACE("Error writing SCAN_CTRL bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 1, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling SCAN_CTRL response\n");
-+		ret = error_code;
-+	}
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: si2168b_channel_seek_init
-+  DESCRIPTION: logs the seek parameters in the context structure
-+  Programming Guide Reference:    Flowchart TBD (Channel Scan flowchart)
-+
-+  Parameter:  Pointer to Si2168B Context
-+  Parameter:  starting Frequency Hz
-+  Parameter:  ending Frequency Hz
-+  Parameter:  min RSSI dBm
-+  Parameter:  max RSSI dBm
-+  Parameter:  min SNR 1/2 dB
-+  Parameter:  max SNR 1/2 dB
-+  Returns:    0 if successful, otherwise an error.
-+************************************************************************************************************************/
-+static int si2168b_channel_seek_init(struct dvb_frontend *fe, Si2168B_CHANNEL_SEEK_PARAM_struct *seek_param)
-+{
-+	const u8 scan_ien_buzien = Si2168B_SCAN_IEN_PROP_BUZIEN_ENABLE; /* (default 'DISABLE') */
-+	const u8 scan_ien_reqien = Si2168B_SCAN_IEN_PROP_REQIEN_ENABLE; /* (default 'DISABLE') */
-+	const u8 scan_int_sense_reqnegen = Si2168B_SCAN_INT_SENSE_PROP_REQNEGEN_DISABLE; /* (default 'DISABLE') */
-+	const u8 scan_int_sense_reqposen = Si2168B_SCAN_INT_SENSE_PROP_REQPOSEN_ENABLE;  /* (default 'ENABLE') */
-+	const u8 scan_int_sense_buznegen = Si2168B_SCAN_INT_SENSE_PROP_BUZNEGEN_ENABLE;  /* (default 'ENABLE') */
-+	const u8 scan_int_sense_buzposen = Si2168B_SCAN_INT_SENSE_PROP_BUZPOSEN_DISABLE; /* (default 'DISABLE') */
-+    const u8 scan_ter_config_analog_bw = Si2168B_SCAN_TER_CONFIG_PROP_ANALOG_BW_8MHZ;
-+    const u8 scan_ter_config_search_analog = Si2168B_SCAN_TER_CONFIG_PROP_SEARCH_ANALOG_DISABLE;
-+
-+#ifdef ALLOW_Si2168B_BLINDSCAN_DEBUG
-+	const u8 scan_ter_config_scan_debug = 0x0f;
-+#else
-+	const u8 scan_ter_config_scan_debug = 0;
-+#endif /* ALLOW_Si2168B_BLINDSCAN_DEBUG */
-+
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	Si2168B_L2_Context *front_end = priv->si_front_end;
-+	Si2168B_SCAN_STATUS_CMD_REPLY_struct scan_status;
-+	u8  modulation = 0;
-+	u16 data;
-+	u8  dd_mode_bw = seek_param->seekBWHz / 1000000;
-+	u8  dd_mode_modulation = front_end->standard;
-+	u8  dd_mode_auto_detect = Si2168B_DD_MODE_PROP_AUTO_DETECT_NONE;
-+	u8  dd_mode_invert_spectrum = Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_DEFAULT;
-+	u8  dvbt2_mode_lock_mode;
-+	u8  dvbt_hierarchy_stream;
-+	u8  dvbc_constellation_constellation;
-+#ifdef __MCNS__
-+	u8  mcns_constellation_constellation;
-+#endif
-+	u16 scan_fmin = front_end->demod->scan_fmin;
-+	u16 scan_fmax = front_end->demod->scan_fmax;
-+	u16 scan_symb_rate_min = front_end->demod->scan_symb_rate_min;
-+	u16 scan_symb_rate_max = front_end->demod->scan_symb_rate_max;
-+    u8  scan_ter_config_mode;
-+
-+	if (front_end->demod->media == Si2168B_TERRESTRIAL) {
-+		SiTRACE("media TERRESTRIAL\n");
-+		front_end->tuneUnitHz = 1;
-+	}
-+	SiTRACE ("blindscan_interaction >> (init  ) si2168b_scan_ctrl( front_end->demod, Si2168B_SCAN_CTRL_CMD_ACTION_ABORT)\n");
-+	si2168b_scan_ctrl(front_end->demod, Si2168B_SCAN_CTRL_CMD_ACTION_ABORT, 0);
-+	/* Check detection standard based on dd_mode.modulation and dd_mode.auto_detect */
-+	SiTRACE("dd_mode.modulation %d, dd_mode.auto_detect %d\n",  dd_mode_modulation, dd_mode_auto_detect);
-+	switch (dd_mode_modulation) {
-+	case Si2168B_DD_MODE_PROP_MODULATION_AUTO_DETECT:
-+		switch (dd_mode_auto_detect) {
-+		case Si2168B_DD_MODE_PROP_AUTO_DETECT_AUTO_DVB_T_T2:
-+			modulation = Si2168B_DD_MODE_PROP_MODULATION_DVBT2;
-+			break;
-+		default:
-+			SiTRACE("AUTO DETECT '%d' is not managed by si2168b_channel_seek_init\n", dd_mode_auto_detect);
-+			break;
-+		}
-+		break;
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBC:
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT2:
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT:
-+		modulation = dd_mode_modulation;
-+		break;
-+	default:
-+		SiTRACE("'%d' modulation (%s) is not managed by si2168b_channel_seek_init\n", dd_mode_modulation, si2168b_standard_name(dd_mode_modulation));
-+		break;
-+	}
-+	SiTRACE("si2168b_channel_seek_init for %s (%d)\n", si2168b_standard_name(modulation), modulation );
-+	switch (modulation) {
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBC:
-+		/* Forcing BW to 8 MHz for DVB-C */
-+		seek_param->seekBWHz = 8000000;
-+		dd_mode_modulation  = Si2168B_DD_MODE_PROP_MODULATION_DVBC;
-+		dd_mode_auto_detect = Si2168B_DD_MODE_PROP_AUTO_DETECT_NONE;
-+		dvbc_constellation_constellation = Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_AUTO;
-+		data = (dvbc_constellation_constellation & Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_MASK) << Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_LSB;
-+		si2168b_set_property(front_end->demod, Si2168B_DVBC_CONSTELLATION_PROP, data);
-+		SiTRACE("DVB-C AFC range %d\n", 100);
-+		break;
-+#ifdef __MCNS__
-+	case Si2168B_DD_MODE_PROP_MODULATION_MCNS:
-+		/* Forcing BW to 8 MHz for MCNS */
-+		seekBWHz = 8000000;
-+		dd_mode_modulation  = Si2168B_DD_MODE_PROP_MODULATION_MCNS;
-+		dd_mode_auto_detect = Si2168B_DD_MODE_PROP_AUTO_DETECT_NONE;
-+		mcns_constellation_constellation = Si2168B_MCNS_CONSTELLATION_PROP_CONSTELLATION_AUTO;
-+		data = (mcns_constellation_constellation & Si2168B_MCNS_CONSTELLATION_PROP_CONSTELLATION_MASK) << Si2168B_MCNS_CONSTELLATION_PROP_CONSTELLATION_LSB;
-+		si2168b_set_property(front_end->demod, Si2168B_MCNS_CONSTELLATION_PROP, data);
-+		SiTRACE("MCNS AFC range %d\n", front_end->demod->prop->mcns_afc_range);
-+		break;
-+#endif /* __MCNS__ */
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT2:
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT:
-+		dvbt_hierarchy_stream = Si2168B_DVBT_HIERARCHY_PROP_STREAM_LP;
-+		data = (dvbt_hierarchy_stream & Si2168B_DVBT_HIERARCHY_PROP_STREAM_MASK) << Si2168B_DVBT_HIERARCHY_PROP_STREAM_LSB;
-+		si2168b_set_property(front_end->demod, Si2168B_DVBT_HIERARCHY_PROP, data);
-+		dd_mode_modulation  = Si2168B_DD_MODE_PROP_MODULATION_AUTO_DETECT;
-+		dd_mode_auto_detect = Si2168B_DD_MODE_PROP_AUTO_DETECT_AUTO_DVB_T_T2;
-+		SiTRACE("DVB-T AFC range %d DVB-T2 AFC range %d\n", 550, 550);
-+		si2168b_dvbt2_plp_select(front_end->demod, 0, Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_SEL_MODE_AUTO);
-+		dvbt2_mode_lock_mode = Si2168B_DVBT2_MODE_PROP_LOCK_MODE_ANY;
-+		data = (dvbt2_mode_lock_mode & Si2168B_DVBT2_MODE_PROP_LOCK_MODE_MASK) << Si2168B_DVBT2_MODE_PROP_LOCK_MODE_LSB;
-+		si2168b_set_property(front_end->demod, Si2168B_DVBT2_MODE_PROP, data);
-+		break;
-+	default:
-+		SiTRACE("'%d' modulation (%s) is not managed by si2168b_channel_seek_init\n", modulation, si2168b_standard_name(modulation));
-+		break;
-+	}
-+
-+	front_end->seekAbort = 0;
-+
-+	SiTRACE("si2168b_channel_seek_init with %d to  %d, sawBW %d, minSR %d, maxSR %d\n", seek_param->rangeMin, seek_param->rangeMax, seek_param->seekBWHz, seek_param->minSRbps, seek_param->maxSRbps);
-+	SiTRACE("spectrum inversion %d\n",front_end->demod->dd_mode_invert_spectrum );
-+	scan_fmin = front_end->tuneUnitHz ? seek_param->rangeMin >> 16 : seek_param->rangeMin & 0x0000FFFF;
-+	scan_fmax = front_end->tuneUnitHz ? seek_param->rangeMax >> 16 : seek_param->rangeMax & 0x0000FFFF;
-+	scan_symb_rate_min = seek_param->minSRbps / 1000;
-+	scan_symb_rate_max = seek_param->maxSRbps / 1000;
-+
-+	data = (scan_fmin & Si2168B_SCAN_FMIN_PROP_SCAN_FMIN_MASK) << Si2168B_SCAN_FMIN_PROP_SCAN_FMIN_LSB;
-+	si2168b_set_property(front_end->demod, Si2168B_SCAN_FMIN_PROP, data);
-+	data = (scan_fmax & Si2168B_SCAN_FMAX_PROP_SCAN_FMAX_MASK) << Si2168B_SCAN_FMAX_PROP_SCAN_FMAX_LSB;
-+	si2168b_set_property(front_end->demod, Si2168B_SCAN_FMAX_PROP, data);
-+	data = (scan_symb_rate_min & Si2168B_SCAN_SYMB_RATE_MIN_PROP_SCAN_SYMB_RATE_MIN_MASK) << Si2168B_SCAN_SYMB_RATE_MIN_PROP_SCAN_SYMB_RATE_MIN_LSB;
-+	si2168b_set_property(front_end->demod, Si2168B_SCAN_SYMB_RATE_MIN_PROP, data);
-+	data = (scan_symb_rate_max & Si2168B_SCAN_SYMB_RATE_MAX_PROP_SCAN_SYMB_RATE_MAX_MASK) << Si2168B_SCAN_SYMB_RATE_MAX_PROP_SCAN_SYMB_RATE_MAX_LSB;
-+	si2168b_set_property(front_end->demod, Si2168B_SCAN_SYMB_RATE_MAX_PROP, data);
-+
-+	data = (scan_ien_buzien & Si2168B_SCAN_IEN_PROP_BUZIEN_MASK) << Si2168B_SCAN_IEN_PROP_BUZIEN_LSB |
-+           (scan_ien_reqien & Si2168B_SCAN_IEN_PROP_REQIEN_MASK) << Si2168B_SCAN_IEN_PROP_REQIEN_LSB;
-+	si2168b_set_property(front_end->demod, Si2168B_SCAN_IEN_PROP, data);
-+
-+    data = (scan_int_sense_buznegen & Si2168B_SCAN_INT_SENSE_PROP_BUZNEGEN_MASK) << Si2168B_SCAN_INT_SENSE_PROP_BUZNEGEN_LSB |
-+           (scan_int_sense_reqnegen & Si2168B_SCAN_INT_SENSE_PROP_REQNEGEN_MASK) << Si2168B_SCAN_INT_SENSE_PROP_REQNEGEN_LSB |
-+           (scan_int_sense_buzposen & Si2168B_SCAN_INT_SENSE_PROP_BUZPOSEN_MASK) << Si2168B_SCAN_INT_SENSE_PROP_BUZPOSEN_LSB |
-+           (scan_int_sense_reqposen & Si2168B_SCAN_INT_SENSE_PROP_REQPOSEN_MASK) << Si2168B_SCAN_INT_SENSE_PROP_REQPOSEN_LSB ;
-+	si2168b_set_property(front_end->demod, Si2168B_SCAN_INT_SENSE_PROP, data);
-+
-+	if (front_end->demod->media == Si2168B_TERRESTRIAL) {
-+		if ( seek_param->rangeMin == seek_param->rangeMax ) {
-+			scan_ter_config_mode = Si2168B_SCAN_TER_CONFIG_PROP_MODE_BLIND_LOCK;
-+			SiTRACE("Blindlock < %8d %8d > < %8d %8d >\n", front_end->demod->scan_fmin, front_end->demod->scan_fmax, front_end->demod->scan_symb_rate_min, front_end->demod->scan_symb_rate_max);
-+		} else {
-+			scan_ter_config_mode = Si2168B_SCAN_TER_CONFIG_PROP_MODE_BLIND_SCAN;
-+			SiTRACE("Blindscan < %8d %8d > < %8d %8d >\n", front_end->demod->scan_fmin, front_end->demod->scan_fmax, front_end->demod->scan_symb_rate_min, front_end->demod->scan_symb_rate_max);
-+		}
-+	    data = (scan_ter_config_mode          & Si2168B_SCAN_TER_CONFIG_PROP_MODE_MASK         ) << Si2168B_SCAN_TER_CONFIG_PROP_MODE_LSB  |
-+	           (scan_ter_config_analog_bw     & Si2168B_SCAN_TER_CONFIG_PROP_ANALOG_BW_MASK    ) << Si2168B_SCAN_TER_CONFIG_PROP_ANALOG_BW_LSB  |
-+	           (scan_ter_config_search_analog & Si2168B_SCAN_TER_CONFIG_PROP_SEARCH_ANALOG_MASK) << Si2168B_SCAN_TER_CONFIG_PROP_SEARCH_ANALOG_LSB |
-+	           (scan_ter_config_scan_debug    & Si2168B_SCAN_TER_CONFIG_PROP_SCAN_DEBUG_MASK   ) << Si2168B_SCAN_TER_CONFIG_PROP_SCAN_DEBUG_LSB ;
-+		si2168b_set_property(front_end->demod, Si2168B_SCAN_TER_CONFIG_PROP, data);
-+		if (seek_param->seekBWHz == 1700000) {
-+			dd_mode_bw = Si2168B_DD_MODE_PROP_BW_BW_1D7MHZ;
-+		} else {
-+			dd_mode_bw = seek_param->seekBWHz / 1000000;
-+		}
-+	}
-+    data = (dd_mode_bw              & Si2168B_DD_MODE_PROP_BW_MASK             ) << Si2168B_DD_MODE_PROP_BW_LSB  |
-+           (dd_mode_modulation      & Si2168B_DD_MODE_PROP_MODULATION_MASK     ) << Si2168B_DD_MODE_PROP_MODULATION_LSB  |
-+           (dd_mode_invert_spectrum & Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_MASK) << Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_LSB  |
-+           (dd_mode_auto_detect     & Si2168B_DD_MODE_PROP_AUTO_DETECT_MASK    ) << Si2168B_DD_MODE_PROP_AUTO_DETECT_LSB ;
-+	si2168b_set_property(front_end->demod, Si2168B_DD_MODE_PROP, data);
-+
-+	si2168b_dd_restart(front_end->demod);
-+
-+	si2168b_scan_status(front_end->demod, Si2168B_SCAN_STATUS_CMD_INTACK_OK, &scan_status);
-+	SiTRACE("blindscan_status leaving Seek_Init %s\n", si2168b_trace_scan_status(scan_status.scan_status) );
-+	/* Preparing the next call to si2168b_scan_ctrl which needs to be a 'START'*/
-+	front_end->demod->scan_ctrl_action = Si2168B_SCAN_CTRL_CMD_ACTION_START;
-+	front_end->handshakeOn = 0;
-+	SiTRACE("blindscan_handshake : Seek_Next will return every ~%d ms\n", front_end->handshakePeriod_ms );
-+	return 0;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: si2168b_channel_seek_next
-+  DESCRIPTION: Looks for the next channel, starting from the last detected channel
-+  Programming Guide Reference:    Flowchart TBD (Channel Scan flowchart)
-+
-+  Parameter:  Pointer to Si2168B Context
-+  Returns:    1 if channel is found, 0 otherwise (either abort or end of range)
-+              Any other value represents the time spent searching (if front_end->handshakeUsed == 1)
-+************************************************************************************************************************/
-+static int si2168b_channel_seek_next(struct dvb_frontend *fe, Si2168B_CHANNEL_SEEK_PARAM_struct *seek_param, Si2168B_CHANNEL_SEEK_NEXT_REPLY_struct *channel_status)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	Si2168B_L2_Context *front_end = priv->si_front_end;
-+	Si2168B_DD_STATUS_CMD_REPLY_struct    dd_status = { 0 };
-+	Si2168B_DVBT_STATUS_CMD_REPLY_struct  dvbt_status = { 0 };
-+	Si2168B_DVBT2_STATUS_CMD_REPLY_struct dvbt2_status = { 0 };
-+	Si2168B_DVBC_STATUS_CMD_REPLY_struct  dvbc_status = { 0 };
-+	Si2168B_SCAN_STATUS_CMD_REPLY_struct  scan_status = { 0 };
-+	int return_code;
-+	int seek_freq;
-+	int seek_freq_kHz;
-+	s32 detected_rf;
-+	int channelIncrement;
-+	int startTime;        /* startTime is used to measure internal durations. It is set in various places, whenever required                                                       */
-+	int seekStartTime;    /* seekStartTime    is used to trace the time spent in si2168b_channel_seek_next and is only set when entering the function                            */
-+	int buzyStartTime;    /* buzyStartTime   is used to trace the time spent waiting for scan_status.buz to be different from 'BUZY'                                               */
-+	int timeoutStartTime; /* timeoutStartTime is used to make sure the FW is correctly responding. It is set differently from seekStartTime when returning from a handshake        */
-+	int searchStartTime = 0;  /* searchStartTime  is used to trace the time spent trying to detect a channel. It is set differently from seekStartTime when returning from a handshake */
-+	int timeoutDelay;
-+	int handshakeDelay;
-+	int searchDelay;
-+	int max_lock_time_ms;
-+	int min_lock_time_ms;
-+	int max_decision_time_ms;
-+	int blind_mode = 0;
-+	int skip_resume;
-+	int start_resume;
-+	u8 previous_scan_status;
-+	u8 jump_to_next_channel;
-+	si2168b_context *ctx;
-+
-+	scan_status.scan_status = Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_IDLE;
-+
-+	ctx = front_end->demod;
-+
-+	/* Clear all return values which may not be used depending on the standard */
-+	channel_status->bandwidth_Hz    = 0;
-+	channel_status->stream          = 0;
-+	channel_status->symbol_rate_bps = 0;
-+	channel_status->constellation   = 0;
-+	channel_status->num_plp         = 0;
-+	channel_status->T2_base_lite    = 0;
-+
-+	if (front_end->seekAbort) {
-+		SiTRACE("si2168b_channel_seek_next : previous run aborted. Please si2168b_channel_seek_init to perform a new search.\n");
-+		return 0;
-+	}
-+
-+	SiTRACE("front_end->standard %d (%s)\n",front_end->standard, si2168b_standard_name(front_end->standard) );
-+
-+	/* Setting max and max lock times and blind_mode flag */
-+	switch ( front_end->standard ) {
-+	/* For T/T2 detection, use the max value between Si2168B_DVBT_MAX_LOCK_TIME and Si2168B_DVBT2_MAX_LOCK_TIME */
-+	/* With Si2168B-A, it's Si2168B_DVBT2_MAX_LOCK_TIME                                                         */
-+	/* This value will be refined as soon as the standard is known, i.e. when PCL = 1                         */
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT2:
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT:
-+		blind_mode = 0;
-+		max_lock_time_ms = Si2168B_DVBT_MAX_LOCK_TIME;
-+		max_lock_time_ms = Si2168B_DVBT2_MAX_LOCK_TIME;
-+		min_lock_time_ms = Si2168B_DVBT_MIN_LOCK_TIME;
-+		break;
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBC:
-+		blind_mode = 1;
-+		max_lock_time_ms = Si2168B_DVBC_MAX_SEARCH_TIME;
-+		min_lock_time_ms = Si2168B_DVBC_MIN_LOCK_TIME;
-+		break;
-+	default:
-+		SiTRACE("'%d' standard (%s) is not managed by si2168b_channel_seek_next\n", front_end->demod->dd_mode_modulation, si2168b_standard_name(front_end->demod->dd_mode_modulation));
-+		front_end->seekAbort = 1;
-+		return 0;
-+	}
-+	SiTRACE("blindscan : max_lock_time_ms %d\n", max_lock_time_ms);
-+
-+	seekStartTime = system_time();
-+
-+	if (front_end->handshakeUsed == 0) {
-+		start_resume = 1;
-+		searchStartTime = seekStartTime;
-+	}
-+
-+	if (front_end->handshakeUsed == 1) {
-+		/* Skip tuner and demod settings if recalled after handshaking */
-+		if (front_end->handshakeOn == 1) {
-+			start_resume = 0;
-+			SiTRACE("blindscan_handshake : recalled after handshake. Skipping tuner and demod settings\n");
-+		}
-+		if (front_end->handshakeOn == 0) {
-+			start_resume = 1;
-+			if (front_end->demod->scan_ctrl_action == Si2168B_SCAN_CTRL_CMD_ACTION_START) {
-+				SiTRACE("blindscan_handshake : no handshake : starting.\n");
-+			} else {
-+				SiTRACE("blindscan_handshake : no handshake : resuming.\n");
-+			}
-+			front_end->handshakeStart_ms = seekStartTime;
-+			SiTRACE("blindscan_handshake : handshake start %d\n", front_end->handshakeStart_ms);
-+		}
-+		searchStartTime = front_end->handshakeStart_ms;
-+	}
-+
-+	if (start_resume == 1) {
-+		/* Enabling FEF control for T/T2 */
-+		switch ( front_end->standard ) {
-+		case Si2168B_DD_MODE_PROP_MODULATION_DVBT2:
-+		case Si2168B_DD_MODE_PROP_MODULATION_DVBT:
-+			if ( front_end->tuner_indirect_i2c_connection ) {  /* INDIRECT_I2C_CONNECTION? */
-+				front_end->f_TER_tuner_enable(front_end->callback);
-+			} else {
-+				si2168b_tuner_i2c_enable(front_end);
-+			}
-+			si2168b_ter_fef(front_end,1);
-+			if ( front_end->tuner_indirect_i2c_connection ) {  /* INDIRECT_I2C_CONNECTION? */
-+				front_end->f_TER_tuner_disable(front_end->callback);
-+			} else {
-+				si2168b_tuner_i2c_disable(front_end);
-+			}
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	max_decision_time_ms = max_lock_time_ms;
-+
-+	/* Select TER channel increment (this value will only be used for 'TER' scanning) */
-+	channelIncrement = seek_param->seekStepHz;
-+
-+	/* Start Seeking */
-+	SiTRACE("si2168b_channel_seek_next rangeMin %10d, rangeMax %10d blind_mode %d\n", seek_param->rangeMin, seek_param->rangeMax, blind_mode);
-+
-+	seek_freq = seek_param->rangeMin;
-+
-+	if (blind_mode == 0) { /* DVB-T / DVB-T2 */
-+		while ( seek_freq <= seek_param->rangeMax ) {
-+			/* Call the si2168b_tune command to tune the frequency */
-+			if (si2168b_set_tuner_params(fe, seek_freq )!= seek_freq) {
-+				/* Manage possible tune error */
-+				SiTRACE("si2168b_channel_seek_next Tune error at %d, aborting (skipped)\n", seek_freq);
-+				front_end->seekAbort = 1;
-+				return 0;
-+			}
-+
-+			timeoutStartTime = system_time();
-+			si2168b_dd_restart(ctx);
-+
-+			/* as we will not lock in less than min_lock_time_ms, wait a while... */
-+			msleep(min_lock_time_ms);
-+
-+			jump_to_next_channel = 0;
-+
-+			while (!jump_to_next_channel) {
-+
-+				if ((front_end->standard == Si2168B_DD_MODE_PROP_MODULATION_DVBT) || (front_end->standard == Si2168B_DD_MODE_PROP_MODULATION_DVBT2) ) {
-+
-+					return_code = si2168b_dd_status(ctx, Si2168B_DD_STATUS_CMD_INTACK_CLEAR, &dd_status);
-+					if (return_code != NO_Si2168B_ERROR) {
-+						SiTRACE("si2168b_channel_seek_next: si2168b_dd_status error at %d, aborting\n", seek_freq);
-+						front_end->seekAbort = 1;
-+						return 0;
-+					}
-+
-+					searchDelay = system_time() - searchStartTime;
-+
-+					if ( (dd_status.dl == Si2168B_DD_STATUS_RESPONSE_DL_NO_LOCK) && (dd_status.rsqstat_bit5 == Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT5_NO_CHANGE ) ) {
-+						/* Check PCL to refine the max_lock_time_ms value if the standard has been detected */
-+						if (dd_status.pcl == Si2168B_DD_STATUS_RESPONSE_PCL_LOCKED) {
-+							if (dd_status.modulation == Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBT) {
-+								max_lock_time_ms = Si2168B_DVBT_MAX_LOCK_TIME ;
-+							}
-+						}
-+					}
-+					if ( (dd_status.dl == Si2168B_DD_STATUS_RESPONSE_DL_NO_LOCK) && (dd_status.rsqstat_bit5 == Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT5_CHANGED) ) {
-+						SiTRACE ("NO DVBT/T2. Jumping from  %d after %3d ms\n", seek_freq/1000000, searchDelay);
-+						if (seek_freq == seek_param->rangeMax) {
-+							seek_param->rangeMin = seek_freq;
-+						}
-+						seek_freq = seek_freq + channelIncrement;
-+						jump_to_next_channel = 1;
-+						break;
-+					}
-+					if ( (dd_status.dl == Si2168B_DD_STATUS_RESPONSE_DL_LOCKED) && (dd_status.rsqstat_bit5 == Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT5_NO_CHANGE ) ) {
-+						channel_status->standard = dd_status.modulation;
-+						if (channel_status->standard == Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBT) {
-+							si2168b_dvbt_status(ctx, Si2168B_DVBT_STATUS_CMD_INTACK_CLEAR, &dvbt_status);
-+							detected_rf = seek_freq + dvbt_status.afc_freq * 1000;
-+							if (dvbt_status.hierarchy == Si2168B_DVBT_STATUS_RESPONSE_HIERARCHY_NONE) {
-+								channel_status->stream = Si2168B_DVBT_HIERARCHY_PROP_STREAM_HP;
-+							} else {
-+								channel_status->stream = dvbt_status.hierarchy;
-+							}
-+							channel_status->bandwidth_Hz = front_end->demod->dd_mode_bw * 1000000;
-+							channel_status->freq         = detected_rf;
-+							SiTRACE ("DVB-T  lock at %d after %3d ms\n", (detected_rf)/1000000, searchDelay);
-+						}
-+						if (channel_status->standard == Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBT2) {
-+							if ( front_end->tuner_indirect_i2c_connection ) {  /* INDIRECT_I2C_CONNECTION? */
-+								front_end->f_TER_tuner_enable(front_end->callback);
-+							} else {
-+								si2168b_tuner_i2c_enable(front_end);
-+							}
-+							si2168b_ter_fef(front_end,1);
-+							if ( front_end->tuner_indirect_i2c_connection ) {  /* INDIRECT_I2C_CONNECTION? */
-+								front_end->f_TER_tuner_disable(front_end->callback);
-+							} else {
-+								si2168b_tuner_i2c_disable(front_end);
-+							}
-+							si2168b_dvbt2_status(ctx, Si2168B_DVBT_STATUS_CMD_INTACK_CLEAR, &dvbt2_status);
-+							channel_status->num_plp = dvbt2_status.num_plp;
-+							detected_rf = seek_freq + dvbt2_status.afc_freq * 1000;
-+							SiTRACE ("DVB-T2 lock at %d after %3d ms\n", detected_rf / 1000000, searchDelay);
-+							switch (front_end->demod->dd_mode_bw) {
-+							case Si2168B_DD_MODE_PROP_BW_BW_1D7MHZ : {
-+								channel_status->bandwidth_Hz = 1700000;
-+								break;
-+							}
-+							default: {
-+								channel_status->bandwidth_Hz = front_end->demod->dd_mode_bw * 1000000;
-+								break; }
-+							}
-+							channel_status->T2_base_lite = dvbt2_status.t2_mode;
-+							channel_status->freq         = detected_rf;
-+						}
-+						/* Set min seek_freq for next seek */
-+						seek_param->rangeMin = seek_freq + seek_param->seekBWHz;
-+						/* Return 1 to signal that the Si2168B is locked on a valid channel */
-+						return 1;
-+					}
-+				}
-+
-+				/* timeout management (this should only trigger if the channel is very difficult, i.e. when pcl = 1 and dl = 0 until the timeout) */
-+				timeoutDelay = system_time() - timeoutStartTime;
-+				if (timeoutDelay >= max_lock_time_ms) {
-+					SiTRACE ("Timeout (blind_mode = 0) from  %d after %3d ms\n", seek_freq/1000000, timeoutDelay);
-+					seek_freq = seek_freq + channelIncrement;
-+					jump_to_next_channel = 1;
-+					break;
-+				}
-+				/* Check status every n ms */
-+				msleep(10);
-+			}
-+		}
-+	}
-+
-+	if (blind_mode == 1) { /* DVB-C / DVB-S / DVB-S2 / MCNS */
-+
-+		if (front_end->tuneUnitHz == 1) {
-+			seek_freq_kHz = seek_freq / 1000;
-+		} else {
-+			seek_freq_kHz = seek_freq;
-+		}
-+
-+		previous_scan_status = scan_status.scan_status;
-+		/* Checking blindscan status before issuing a 'start' or 'resume' */
-+		si2168b_scan_status(front_end->demod, Si2168B_SCAN_STATUS_CMD_INTACK_OK, &scan_status);
-+		SiTRACE("blindscan_status      %s buz %d\n", si2168b_trace_scan_status(scan_status.scan_status), scan_status.buz);
-+
-+		if (scan_status.scan_status != previous_scan_status) {
-+			SiTRACE ("scan_status changed from %s to %s\n", si2168b_trace_scan_status(previous_scan_status), si2168b_trace_scan_status(scan_status.scan_status));
-+		}
-+
-+		if (start_resume) {
-+			/* Wait for scan_status.buz to be '0' before issuing SCAN_CTRL */
-+			buzyStartTime = system_time();
-+			while (scan_status.buz == Si2168B_SCAN_STATUS_RESPONSE_BUZ_BUSY) {
-+				si2168b_scan_status(front_end->demod, Si2168B_SCAN_STATUS_CMD_INTACK_OK, &scan_status);
-+				SiTRACE ("blindscan_interaction ?? (buzy)   si2168b_scan_status scan_status.buz %d after %d ms\n", scan_status.buz, system_time() - buzyStartTime);
-+				if (system_time() - buzyStartTime > 100) {
-+					SiTRACE ("blindscan_interaction -- (error)  si2168b_scan_status is always 'BUZY'\n");
-+					return 0;
-+				}
-+			}
-+			if (front_end->demod->scan_ctrl_action == Si2168B_SCAN_CTRL_CMD_ACTION_START) {
-+				SiTRACE ("blindscan_interaction >> (start ) si2168b_scan_ctrl( front_end->demod, %d, %8d) \n", front_end->demod->scan_ctrl_action, seek_freq_kHz);
-+			} else {
-+				SiTRACE ("blindscan_interaction >> (resume) si2168b_scan_ctrl( front_end->demod, %d, %8d) \n", front_end->demod->scan_ctrl_action, seek_freq_kHz);
-+			}
-+			return_code = si2168b_scan_ctrl (front_end->demod, front_end->demod->scan_ctrl_action, seek_freq_kHz);
-+			if (return_code != NO_Si2168B_ERROR) {
-+				SiTRACE ("blindscan_interaction -- (error1) si2168b_scan_ctrl %d      ERROR at %10d (%d)\n!!!!!!!!!!!!!!!!!!!!!!!\n", front_end->demod->scan_ctrl_action, seek_freq_kHz, scan_status.scan_status);
-+				SiTRACE("scan_status.buz %d\n", scan_status.buz);
-+				return 0;
-+			}
-+		}
-+		front_end->demod->scan_ctrl_action = Si2168B_SCAN_CTRL_CMD_ACTION_RESUME;
-+
-+		startTime = system_time();
-+		/* as we will not lock in less than min_lock_time_ms, wait a while... */
-+		while (system_time() - startTime < min_lock_time_ms) {
-+			if (front_end->seekAbort) {
-+				break;
-+			}
-+			/* Adapt here the minimal 'reaction time' of the application*/
-+			msleep(20);
-+		}
-+
-+		timeoutStartTime = system_time();
-+
-+		/* The actual search loop... */
-+		while ( 1 ) {
-+
-+			si2168b_check_status(front_end->demod);
-+
-+			searchDelay = system_time() - searchStartTime;
-+
-+			if ( (front_end->demod->status_scanint == Si2168B_STATUS_SCANINT_TRIGGERED) ) {
-+
-+				/* There is an interaction with the FW, refresh the timeoutStartTime */
-+				timeoutStartTime = system_time();
-+
-+				si2168b_scan_status(front_end->demod, Si2168B_SCAN_STATUS_CMD_INTACK_CLEAR, &scan_status);
-+				SiTRACE("blindscan_status      %s\n", si2168b_trace_scan_status(scan_status.scan_status) );
-+				skip_resume = 0;
-+
-+				switch (scan_status.scan_status) {
-+				case  Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_TUNE_REQUEST          : {
-+					SiTRACE ("blindscan_interaction -- (tune  ) SCAN TUNE_REQUEST at %8ld kHz\n", scan_status.rf_freq);
-+					if (front_end->tuneUnitHz == 1) {
-+						seek_freq = si2168b_set_tuner_params(fe, scan_status.rf_freq*1000);
-+						seek_freq_kHz = seek_freq/1000;
-+					} else {
-+						seek_freq = si2168b_set_tuner_params(fe, scan_status.rf_freq);
-+						seek_freq_kHz = seek_freq;
-+					}
-+					channel_status->freq = seek_param->rangeMin = seek_freq;
-+					/* as we will not lock in less than min_lock_time_ms, wait a while... */
-+					msleep(min_lock_time_ms);
-+					break;
-+				}
-+				case  Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_DIGITAL_CHANNEL_FOUND : {
-+					channel_status->standard = scan_status.modulation;
-+					switch (scan_status.modulation) {
-+					case Si2168B_SCAN_STATUS_RESPONSE_MODULATION_DVBC : {
-+						channel_status->freq            = scan_status.rf_freq * 1000;
-+						channel_status->symbol_rate_bps = scan_status.symb_rate * 1000;
-+						si2168b_dvbc_status(front_end->demod, Si2168B_DVBC_STATUS_CMD_INTACK_OK, &dvbc_status);
-+						front_end->demod->dvbc_symbol_rate = scan_status.symb_rate;
-+						channel_status->constellation = dvbc_status.constellation;
-+						break;
-+					}
-+#ifdef __MCNS__
-+					case Si2168B_SCAN_STATUS_RESPONSE_MODULATION_MCNS : {
-+						*freq            = front_end->demod->rsp->scan_status.rf_freq * 1000;
-+						*symbol_rate_bps = front_end->demod->rsp->scan_status.symb_rate * 1000;
-+						si2168b_mcns_status(front_end->demod, Si2168B_MCNS_STATUS_CMD_INTACK_OK);
-+						front_end->demod->prop->mcns_symbol_rate.rate = front_end->demod->rsp->scan_status.symb_rate;
-+						*constellation   = front_end->demod->rsp->mcns_status.constellation;
-+						break;
-+					}
-+#endif /* __MCNS__ */
-+					default : {
-+						SiTRACE("si2168b_channel_seek_next DIGITAL_CHANNEL_FOUND error at %d: un-handled modulation (%d), aborting (skipped)\n", seek_freq, scan_status.modulation);
-+						front_end->seekAbort = 1;
-+						return 0;
-+					}
-+					}
-+					SiTRACE ("blindscan_interaction -- (locked) SCAN DIGITAL lock at %d MHz after %3d ms. modulation %3d (%s)\n", channel_status->freq/1000, searchDelay, channel_status->standard, si2168b_standard_name(channel_status->standard));
-+					front_end->handshakeOn = 0;
-+					return 1;
-+				}
-+				case  Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_ERROR: {
-+					SiTRACE ("blindscan_interaction -- (error2) SCAN error at %d after %4d ms\n", seek_freq/1000000, searchDelay);
-+					front_end->handshakeOn = 0;
-+					return 0;
-+				}
-+				case  Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_SEARCHING: {
-+					SiTRACE("SCAN Searching...\n");
-+					skip_resume = 1;
-+					break;
-+				}
-+				case  Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_ENDED: {
-+					SiTRACE ("blindscan_interaction -- (ended ) SCAN ENDED\n");
-+					si2168b_scan_ctrl (front_end->demod, Si2168B_SCAN_CTRL_CMD_ACTION_ABORT , 0);
-+					front_end->handshakeOn = 0;
-+					return 0;
-+				}
-+#ifdef ALLOW_Si2168B_BLINDSCAN_DEBUG
-+				case  Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_DEBUG                 : {
-+					SiTRACE ("blindscan_interaction -- (debug) SCAN DEBUG code %d\n", front_end->demod->rsp->scan_status.symb_rate);
-+					switch (front_end->demod->rsp->scan_status.symb_rate) {
-+					case 4: { /* SPECTRUM */
-+#ifndef DO_NOT_DRAW_SPECTRUM
-+						Si2168B_plot(front_end, "spectrum", 0, seek_freq);
-+#endif /* DO_NOT_DRAW_SPECTRUM */
-+						break;
-+					}
-+					case 9: { /* TRYLOCK */
-+#ifndef DO_NOT_TRACK_TRYLOCKS
-+						Si2168B_plot(front_end, "trylock", 0, seek_freq);
-+#endif /* DO_NOT_DRAW_SPECTRUM */
-+						break;
-+					}
-+					default: {}
-+					}
-+					/* There has been a debug request by the FW, refresh the timeoutStartTime */
-+					timeoutStartTime = system_time();
-+					break;
-+				}
-+#else /* ALLOW_Si2168B_BLINDSCAN_DEBUG */
-+				case  63                 : {
-+					SiTRACE("blindscan_interaction -- (warning) You probably run a DEBUG fw, so you need to define ALLOW_Si2168B_BLINDSCAN_DEBUG at project level\n");
-+					break;
-+				}
-+#endif /* ALLOW_Si2168B_BLINDSCAN_DEBUG */
-+				default : {
-+					SiTRACE("unknown scan_status %d\n", scan_status.scan_status);
-+					skip_resume = 1;
-+					break;
-+				}
-+				}
-+
-+				if (skip_resume == 0) {
-+					SiTRACE ("blindscan_interaction >> (resume) si2168b_scan_ctrl( front_end->demod, %d, %8d)\n", front_end->demod->scan_ctrl_action, seek_freq_kHz);
-+					return_code = si2168b_scan_ctrl(front_end->demod, front_end->demod->scan_ctrl_action, seek_freq_kHz);
-+					if (return_code != NO_Si2168B_ERROR) {
-+						SiTRACE("si2168b_scan_ctrl ERROR at %d (%d)\n!!!!!!!!!!!!!!!!!!!!!!!\n", seek_freq_kHz, scan_status.scan_status);
-+						SiTRACE("si2168b_scan_ctrl 'RESUME' ERROR during seek loop\n");
-+					}
-+				}
-+			}
-+
-+			/* timeout management (this should never happen if timeout values are correctly set) */
-+			timeoutDelay = system_time() - timeoutStartTime;
-+			if (system_time() - timeoutStartTime >= max_decision_time_ms) {
-+				SiTRACE ("Scan decision timeout (blind_mode = 1) from  %d after %d ms. Check your timeout limits!\n", seek_freq_kHz/1000, timeoutDelay);
-+				front_end->seekAbort   = 1;
-+				front_end->handshakeOn = 0;
-+				break;
-+			}
-+
-+			if (front_end->handshakeUsed) {
-+				handshakeDelay = system_time() - seekStartTime;
-+				if (handshakeDelay >= front_end->handshakePeriod_ms) {
-+					SiTRACE ("blindscan_handshake : handshake after %5d ms (at %10d). (search delay %6d ms) %*s\n", handshakeDelay, seek_param->rangeMin, searchDelay, (searchDelay)/1000, "*");
-+					channel_status->freq = seek_freq;
-+					front_end->handshakeOn = 1;
-+					/* The application will check handshakeStart_ms to know whether the blindscan is ended or not */
-+					return searchDelay;
-+				} else {
-+					SiTRACE ("blindscan_handshake : no handshake yet. (handshake delay %6d ms, search delay %6d ms)\n", handshakeDelay, searchDelay);
-+				}
-+			}
-+
-+			/* Check seekAbort flag (set in case of timeout or by the top-level application) */
-+			if (front_end->seekAbort) {
-+				/* Abort the SCAN loop to allow it to restart with the new rangeMin frequency */
-+				SiTRACE ("blindscan_interaction >> (abort!) si2168b_scan_ctrl(front_end->demod, Si2168B_SCAN_CTRL_CMD_ACTION_ABORT)\n");
-+				si2168b_scan_ctrl (front_end->demod, Si2168B_SCAN_CTRL_CMD_ACTION_ABORT , 0);
-+				front_end->handshakeOn = 0;
-+				return 0;
-+			}
-+
-+			/* Check status every 100 ms */
-+			msleep(100);
-+		}
-+	}
-+	front_end->handshakeOn = 0;
-+	return 0;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_POWER_DOWN COMMAND                       */
-+/*---------------------------------------------------*/
-+static u8 si2168b_power_down(si2168b_context *ctx)
-+{
-+	u8 cmdByteBuffer[1];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("si2168b_power_down\n");
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_POWER_DOWN_CMD;
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 1, cmdByteBuffer) != 1) {
-+		SiTRACE("Error writing POWER_DOWN bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+	}
-+
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: si2168b_standby
-+  DESCRIPTION:
-+  Parameter:  Pointer to Si2168B Context
-+  Returns:    I2C transaction error code, NO_Si2168B_ERROR if successful
-+************************************************************************************************************************/
-+static int si2168b_standby(si2168b_context *ctx)
-+{
-+	SiTRACE("si2168b_standby()\n");
-+	return si2168b_power_down(ctx);
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_PART_INFO COMMAND                        */
-+/*---------------------------------------------------*/
-+static u8 si2168b_part_info(si2168b_context *ctx, Si2168B_PART_INFO_CMD_REPLY_struct *part_info)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[1];
-+	u8 rspByteBuffer[13];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B PART_INFO\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_PART_INFO_CMD;
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 1, cmdByteBuffer) != 1) {
-+		SiTRACE("Error writing PART_INFO bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 13, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling PART_INFO response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	part_info->chiprev  =   (( ( (rspByteBuffer[1]  )) >> Si2168B_PART_INFO_RESPONSE_CHIPREV_LSB  ) & Si2168B_PART_INFO_RESPONSE_CHIPREV_MASK  );
-+	part_info->part     =   (( ( (rspByteBuffer[2]  )) >> Si2168B_PART_INFO_RESPONSE_PART_LSB     ) & Si2168B_PART_INFO_RESPONSE_PART_MASK     );
-+	part_info->pmajor   =   (( ( (rspByteBuffer[3]  )) >> Si2168B_PART_INFO_RESPONSE_PMAJOR_LSB   ) & Si2168B_PART_INFO_RESPONSE_PMAJOR_MASK   );
-+	part_info->pminor   =   (( ( (rspByteBuffer[4]  )) >> Si2168B_PART_INFO_RESPONSE_PMINOR_LSB   ) & Si2168B_PART_INFO_RESPONSE_PMINOR_MASK   );
-+	part_info->pbuild   =   (( ( (rspByteBuffer[5]  )) >> Si2168B_PART_INFO_RESPONSE_PBUILD_LSB   ) & Si2168B_PART_INFO_RESPONSE_PBUILD_MASK   );
-+	part_info->reserved =   (( ( (rspByteBuffer[6]  ) | (rspByteBuffer[7]  << 8 )) >> Si2168B_PART_INFO_RESPONSE_RESERVED_LSB ) & Si2168B_PART_INFO_RESPONSE_RESERVED_MASK );
-+	part_info->serial   =   (( ( (rspByteBuffer[8]  ) | (rspByteBuffer[9]  << 8 ) | (rspByteBuffer[10] << 16 ) | (rspByteBuffer[11] << 24 )) >> Si2168B_PART_INFO_RESPONSE_SERIAL_LSB   ) & Si2168B_PART_INFO_RESPONSE_SERIAL_MASK   );
-+	part_info->romid    =   (( ( (rspByteBuffer[12] )) >> Si2168B_PART_INFO_RESPONSE_ROMID_LSB    ) & Si2168B_PART_INFO_RESPONSE_ROMID_MASK    );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/***********************************************************************************************************************
-+  si2168b_patch function
-+  Use:        Patch information function
-+              Used to send a number of bytes to the Si2168B. Useful to download the firmware.
-+  Returns:    0 if no error
-+  Parameter:  error_code the error code.
-+  Porting:    Useful for application development for debug purposes.
-+  Porting:    May not be required for the final application, can be removed if not used.
-+ ***********************************************************************************************************************/
-+static u8 si2168b_patch(si2168b_context *ctx, int iNbBytes, u8 *pucDataBuffer)
-+{
-+	int res;
-+	u8 ret = NO_Si2168B_ERROR;
-+	u8 rspByteBuffer[1];
-+
-+	SiTRACE("Si2168B Patch %d bytes\n",iNbBytes);
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	res = i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, iNbBytes, pucDataBuffer);
-+	if (res!=iNbBytes) {
-+		SiTRACE("si2168b_patch error writing bytes: %s\n", si2168b_error_text(ERROR_Si2168B_LOADING_FIRMWARE) );
-+		ret = ERROR_Si2168B_LOADING_FIRMWARE;
-+		goto unlock_mutex;
-+	}
-+
-+	res = si2168b_poll_for_response(ctx, 1, rspByteBuffer);
-+	if (res != NO_Si2168B_ERROR) {
-+		SiTRACE("si2168b_patch error 0x%02x polling response: %s\n", res, si2168b_error_text(res) );
-+		ret = ERROR_Si2168B_POLLING_RESPONSE;
-+	}
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: si2168b_load_firmware_16
-+  DESCRIPTON: Load firmware from firmware_struct array in Si2168B_Firmware_x_y_build_z.h file into Si2168B
-+              Requires Si2168B to be in bootloader mode after PowerUp
-+
-+  Parameter:  Si2168B Context (I2C address)
-+  Parameter:  pointer to firmware_struct array
-+  Parameter:  number of lines in firmware table array (size in bytes / firmware_struct)
-+  Returns:    Si2168B/I2C transaction error code, NO_Si2168B_ERROR if successful
-+************************************************************************************************************************/
-+static int si2168b_load_firmware_16(si2168b_context *ctx, firmware_struct fw_table[], int nbLines)
-+{
-+	int return_code = NO_Si2168B_ERROR;
-+	int line;
-+
-+	SiTRACE ("si2168b_load_firmware_16 starting...\n");
-+	SiTRACE ("si2168b_load_firmware_16 nbLines %d\n", nbLines);
-+
-+	/* for each line in fw_table */
-+	for (line = 0; line < nbLines; line++) {
-+		if (fw_table[line].firmware_len > 0)  /* don't download if length is 0 , e.g. dummy firmware */
-+		{
-+			/* send firmware_len bytes (up to 16) to Si2168B */
-+			if ((return_code = si2168b_patch(ctx, fw_table[line].firmware_len, fw_table[line].firmware_table)) != NO_Si2168B_ERROR)
-+			{
-+				SiTRACE("si2168b_load_firmware_16 error 0x%02x patching line %d: %s\n", return_code, line, si2168b_error_text(return_code) );
-+				if (line == 0) {
-+					SiTRACE("The firmware is incompatible with the part!\n");
-+				}
-+				return ERROR_Si2168B_LOADING_FIRMWARE;
-+			}
-+			if (line==3) {
-+				sitraces_suspend();
-+			}
-+		}
-+	}
-+	sitraces_resume();
-+	SiTRACE ("si2168b_load_firmware_16 complete...\n");
-+	return NO_Si2168B_ERROR;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_EXIT_BOOTLOADER COMMAND                  */
-+/*---------------------------------------------------*/
-+static u8 si2168b_exit_bootloader(si2168b_context *ctx,
-+		u8 func,
-+		u8 ctsien)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[1];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B EXIT_BOOTLOADER\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_EXIT_BOOTLOADER_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( func   & Si2168B_EXIT_BOOTLOADER_CMD_FUNC_MASK   ) << Si2168B_EXIT_BOOTLOADER_CMD_FUNC_LSB  |
-+			( ctsien & Si2168B_EXIT_BOOTLOADER_CMD_CTSIEN_MASK ) << Si2168B_EXIT_BOOTLOADER_CMD_CTSIEN_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing EXIT_BOOTLOADER bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 1, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling EXIT_BOOTLOADER response\n");
-+		ret = error_code;
-+	}
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: si2168b_start_firmware
-+  DESCRIPTION: Start Si2168B firmware (put the Si2168B into run mode)
-+  Parameter:   Si2168B Context (I2C address)
-+  Parameter (passed by Reference):   ExitBootloadeer Response Status byte : tunint, atvint, dtvint, err, cts
-+  Returns:     I2C transaction error code, NO_Si2168B_ERROR if successful
-+ ************************************************************************************************************************/
-+static int si2168b_start_firmware(si2168b_context *ctx)
-+{
-+	int ret = NO_Si2168B_ERROR;
-+
-+	ret = si2168b_exit_bootloader(ctx, Si2168B_EXIT_BOOTLOADER_CMD_FUNC_NORMAL, Si2168B_EXIT_BOOTLOADER_CMD_CTSIEN_OFF);
-+	if (ret != NO_Si2168B_ERROR) {
-+		return ERROR_Si2168B_STARTING_FIRMWARE;
-+	}
-+
-+	return NO_Si2168B_ERROR;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_GET_REV COMMAND                          */
-+/*---------------------------------------------------*/
-+static u8 si2168b_get_revision(si2168b_context *ctx, Si2168B_GET_REV_CMD_REPLY_struct *get_rev)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[1];
-+	u8 rspByteBuffer[10];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B GET_REV\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_GET_REV_CMD;
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 1, cmdByteBuffer) != 1) {
-+		SiTRACE("Error writing GET_REV bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 10, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling GET_REV response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	get_rev->pn       =   (( ( (rspByteBuffer[1]  )) >> Si2168B_GET_REV_RESPONSE_PN_LSB       ) & Si2168B_GET_REV_RESPONSE_PN_MASK       );
-+	get_rev->fwmajor  =   (( ( (rspByteBuffer[2]  )) >> Si2168B_GET_REV_RESPONSE_FWMAJOR_LSB  ) & Si2168B_GET_REV_RESPONSE_FWMAJOR_MASK  );
-+	get_rev->fwminor  =   (( ( (rspByteBuffer[3]  )) >> Si2168B_GET_REV_RESPONSE_FWMINOR_LSB  ) & Si2168B_GET_REV_RESPONSE_FWMINOR_MASK  );
-+	get_rev->patch    =   (( ( (rspByteBuffer[4]  ) | (rspByteBuffer[5]  << 8 )) >> Si2168B_GET_REV_RESPONSE_PATCH_LSB    ) & Si2168B_GET_REV_RESPONSE_PATCH_MASK    );
-+	get_rev->cmpmajor =   (( ( (rspByteBuffer[6]  )) >> Si2168B_GET_REV_RESPONSE_CMPMAJOR_LSB ) & Si2168B_GET_REV_RESPONSE_CMPMAJOR_MASK );
-+	get_rev->cmpminor =   (( ( (rspByteBuffer[7]  )) >> Si2168B_GET_REV_RESPONSE_CMPMINOR_LSB ) & Si2168B_GET_REV_RESPONSE_CMPMINOR_MASK );
-+	get_rev->cmpbuild =   (( ( (rspByteBuffer[8]  )) >> Si2168B_GET_REV_RESPONSE_CMPBUILD_LSB ) & Si2168B_GET_REV_RESPONSE_CMPBUILD_MASK );
-+	get_rev->chiprev  =   (( ( (rspByteBuffer[9]  )) >> Si2168B_GET_REV_RESPONSE_CHIPREV_LSB  ) & Si2168B_GET_REV_RESPONSE_CHIPREV_MASK  );
-+	get_rev->mcm_die  =   (( ( (rspByteBuffer[9]  )) >> Si2168B_GET_REV_RESPONSE_MCM_DIE_LSB  ) & Si2168B_GET_REV_RESPONSE_MCM_DIE_MASK  );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: si2168b_power_up_with_patch
-+  DESCRIPTION: Send Si2168B API PowerUp Command with PowerUp to bootloader,
-+  Check the Chip rev and part, and ROMID are compared to expected values.
-+  Load the Firmware Patch then Start the Firmware.
-+  Programming Guide Reference:    Flowchart A.2 (POWER_UP with patch flowchart)
-+
-+  Parameter:  pointer to Si2168B Context
-+  Returns:    Si2168B/I2C transaction error code, NO_Si2168B_ERROR if successful
-+************************************************************************************************************************/
-+static int si2168b_power_up_with_patch(si2168b_context *ctx)
-+{
-+	int return_code = NO_Si2168B_ERROR;
-+	int fw_loaded = 0;
-+	Si2168B_GET_REV_CMD_REPLY_struct get_rev;
-+	Si2168B_PART_INFO_CMD_REPLY_struct part_info = { 0 };
-+
-+	/* Before patching, set POWER_UP values for 'RESET' and 'BOOTLOADER' */
-+	ctx->power_up_reset = Si2168B_POWER_UP_CMD_RESET_RESET;
-+	ctx->power_up_func  = Si2168B_POWER_UP_CMD_FUNC_BOOTLOADER,
-+
-+	return_code = si2168b_wakeup(ctx);
-+
-+	if (return_code != NO_Si2168B_ERROR) {
-+		SiTRACE("si2168b_power_up_with_patch: WAKEUP error!\n");
-+		return return_code;
-+	}
-+
-+	ctx->Si2168B_in_standby = 0;
-+
-+	/* Get the Part Info from the chip.   This command is only valid in Bootloader mode */
-+	if ((return_code = si2168b_part_info(ctx, &part_info)) != NO_Si2168B_ERROR) {
-+		SiTRACE ("si2168b_part_info error 0x%02x: %s\n", return_code, si2168b_error_text(return_code) );
-+		return return_code;
-+	}
-+	SiTRACE("part    Si21%02d", part_info.part   );
-+	if (part_info.chiprev == Si2168B_PART_INFO_RESPONSE_CHIPREV_A) {
-+		SiTRACE("A\n");
-+	} else if (part_info.chiprev == Si2168B_PART_INFO_RESPONSE_CHIPREV_B) {
-+		SiTRACE("B\n");
-+	} else {
-+		SiTRACE("\nchiprev %d\n", part_info.chiprev);
-+	}
-+	SiTRACE("romid   %d\n",     part_info.romid  );
-+	SiTRACE("pmajor  0x%02x\n", part_info.pmajor );
-+	SiTRACE("pminor  0x%02x\n", part_info.pminor );
-+	SiTRACE("pbuild  %d\n",     part_info.pbuild );
-+	if ((part_info.pmajor >= 0x30) & (part_info.pminor >= 0x30)) {
-+		SiTRACE("Full Info       'Si21%02d-%c%c%c ROM%x NVM%c_%cb%d'\n\n\n", part_info.part, part_info.chiprev + 0x40, part_info.pmajor, part_info.pminor, part_info.romid, part_info.pmajor, part_info.pminor, part_info.pbuild );
-+	}
-+
-+	/* Check part info values and load the proper firmware */
-+#ifdef    Si2168B_A40_COMPATIBLE
-+#ifdef    Si2168B_PATCH16_4_4b7_LINES
-+	if (!fw_loaded) {
-+		SiTRACE  ("Is this part a  'Si21%2d_ROM%x_%c_%c_b%d'?\n", Si2168B_PATCH16_4_4b7_PART, Si2168B_PATCH16_4_4b7_ROM, Si2168B_PATCH16_4_4b7_PMAJOR, Si2168B_PATCH16_4_4b7_PMINOR, Si2168B_PATCH16_4_4b7_PBUILD );
-+		if ((ctx->rsp->part_info.romid  == Si2168B_PATCH16_4_4b7_ROM   )
-+				&(  (ctx->rsp->part_info.part == 64 )
-+						|| (ctx->rsp->part_info.part == 62 )
-+						|| (ctx->rsp->part_info.part == 60 )
-+				)
-+				& (ctx->rsp->part_info.pmajor == Si2168B_PATCH16_4_4b7_PMAJOR)
-+				& (ctx->rsp->part_info.pminor == Si2168B_PATCH16_4_4b7_PMINOR)
-+				& (ctx->rsp->part_info.pbuild == Si2168B_PATCH16_4_4b7_PBUILD)
-+		) {
-+			SiTRACE("Updating FW for 'Si21%2d NVM%c_%cb%d'\n", ctx->rsp->part_info.part, ctx->rsp->part_info.pmajor, ctx->rsp->part_info.pminor, ctx->rsp->part_info.pbuild );
-+#ifdef    Si2168B_PATCH16_4_4b7_INFOS
-+			SiTRACE(Si2168B_PATCH16_4_4b7_INFOS);
-+#endif /* Si2168B_PATCH16_4_4b7_INFOS */
-+			if ((return_code = si2168b_load_firmware_16(ctx, Si2168B_PATCH16_4_4b7, Si2168B_PATCH16_4_4b7_LINES)) != NO_Si2168B_ERROR) {
-+				SiTRACE ("si2168b_load_firmware_16 error 0x%02x: %s\n", return_code, si2168b_error_text(return_code) );
-+				return return_code;
-+			}
-+			fw_loaded++;
-+		}
-+	}
-+#endif /* Si2168B_PATCH16_4_4b7_LINES */
-+#ifdef    Si2168B_PATCH16_4_0b9_LINES
-+	if (!fw_loaded) {
-+		SiTRACE  ("Is this part a  'Si21%2d_ROM%x_%c_%c_b%d'?\n", Si2168B_PATCH16_4_0b9_PART, Si2168B_PATCH16_4_0b9_ROM, Si2168B_PATCH16_4_0b9_PMAJOR, Si2168B_PATCH16_4_0b9_PMINOR, Si2168B_PATCH16_4_0b9_PBUILD );
-+		if ((part_info.romid  == Si2168B_PATCH16_4_0b9_ROM   )
-+				&& (  (part_info.part == 69 )
-+						|| (part_info.part == 68 )
-+				)
-+				&& (part_info.pmajor == Si2168B_PATCH16_4_0b9_PMAJOR)
-+				&& (part_info.pminor == Si2168B_PATCH16_4_0b9_PMINOR)
-+				&& (part_info.pbuild == Si2168B_PATCH16_4_0b9_PBUILD)
-+		) {
-+			SiTRACE("Updating FW for 'Si21%2d NVM%c_%cb%d'\n", part_info.part, part_info.pmajor, part_info.pminor, part_info.pbuild);
-+#ifdef    Si2168B_PATCH16_4_0b9_INFOS
-+			SiTRACE(Si2168B_PATCH16_4_0b9_INFOS);
-+#endif /* Si2168B_PATCH16_4_0b9_INFOS */
-+			if ((return_code = si2168b_load_firmware_16(ctx, Si2168B_PATCH16_4_0b9, Si2168B_PATCH16_4_0b9_LINES)) != NO_Si2168B_ERROR) {
-+				SiTRACE ("si2168b_load_firmware_16 error 0x%02x: %s\n", return_code, si2168b_error_text(return_code) );
-+				return return_code;
-+			}
-+			fw_loaded++;
-+		}
-+	}
-+#endif /* Si2168B_PATCH16_4_0b9_LINES */
-+#endif /* Si2168B_A40_COMPATIBLE */
-+#ifdef    Si2168B_ES_COMPATIBLE
-+#ifdef    Si2168B_FIRMWARE_3_Ab12_LINES
-+	if (!fw_loaded) {
-+		SiTRACE  ("Is this part a  'Si21%2d_ROM%x_%c_%c_b%d'?\n", Si2168B_FIRMWARE_3_Ab12_PART, Si2168B_FIRMWARE_3_Ab12_ROM, Si2168B_FIRMWARE_3_Ab12_PMAJOR, Si2168B_FIRMWARE_3_Ab12_PMINOR, Si2168B_FIRMWARE_3_Ab12_PBUILD );
-+		if ((ctx->rsp->part_info.romid  == Si2168B_FIRMWARE_3_Ab12_ROM   )
-+				&(  (ctx->rsp->part_info.part == 69 )
-+						|| (ctx->rsp->part_info.part == 68 )
-+						|| (ctx->rsp->part_info.part == 64 )
-+						|| (ctx->rsp->part_info.part == 62 )
-+						|| (ctx->rsp->part_info.part == 60 )
-+						|| (ctx->rsp->part_info.part == 0  )
-+				)
-+				/*
-+        & (ctx->rsp->part_info.pmajor == Si2168B_FIRMWARE_3_Ab12_PMAJOR)
-+        & (ctx->rsp->part_info.pminor == Si2168B_FIRMWARE_3_Ab12_PMINOR)
-+        & (ctx->rsp->part_info.pbuild == Si2168B_FIRMWARE_3_Ab12_PBUILD)
-+				 */
-+		) {
-+			SiTRACE("Updating FW for 'Si21%2d NVM%c_%cb%d' (full download)\n", ctx->rsp->part_info.part, ctx->rsp->part_info.pmajor, ctx->rsp->part_info.pminor, ctx->rsp->part_info.pbuild );
-+#ifdef    Si2168B_FIRMWARE_3_Ab12_INFOS
-+			SiTRACE(Si2168B_FIRMWARE_3_Ab12_INFOS);
-+#endif /* Si2168B_FIRMWARE_3_Ab12_INFOS */
-+			if ((return_code = Si2168B_LoadFirmware(ctx, Si2168B_FIRMWARE_3_Ab12, Si2168B_FIRMWARE_3_Ab12_LINES)) != NO_Si2168B_ERROR) {
-+				SiTRACE ("Si2168B_LoadFirmware error 0x%02x: %s\n", return_code, si2168b_error_text(return_code) );
-+				return return_code;
-+			}
-+			fw_loaded++;
-+		}
-+	}
-+#endif /* Si2168B_FIRMWARE_3_Ab12_LINES */
-+#endif /* Si2168B_ES_COMPATIBLE */
-+#ifdef    Si2169_30_COMPATIBLE
-+#ifdef    Si2169_PATCH_3_0b18_LINES
-+	if (!fw_loaded) {
-+		SiTRACE  ("Is this part a  'Si21%2d_ROM%x_%c_%c_b%d'?\n", Si2169_PATCH_3_0b18_PART, Si2169_PATCH_3_0b18_ROM, Si2169_PATCH_3_0b18_PMAJOR, Si2169_PATCH_3_0b18_PMINOR, Si2169_PATCH_3_0b18_PBUILD );
-+		if ((ctx->rsp->part_info.romid  == Si2169_PATCH_3_0b18_ROM   )
-+				&((ctx->rsp->part_info.part   == 69 ) || (ctx->rsp->part_info.part == 68 ))
-+				& (ctx->rsp->part_info.pmajor == Si2169_PATCH_3_0b18_PMAJOR)
-+				& (ctx->rsp->part_info.pminor == Si2169_PATCH_3_0b18_PMINOR)
-+				& (ctx->rsp->part_info.pbuild == Si2169_PATCH_3_0b18_PBUILD)) {
-+			SiTRACE("Updating FW for 'Si21%2d_ROM%x %c_%c_b%d'\n", ctx->rsp->part_info.part, ctx->rsp->part_info.romid, ctx->rsp->part_info.pmajor, ctx->rsp->part_info.pminor, ctx->rsp->part_info.pbuild );
-+#ifdef    Si2169_PATCH_3_0b18_INFOS
-+			SiTRACE(Si2169_PATCH_3_0b18_INFOS);
-+#endif /* Si2169_PATCH_3_0b18_INFOS */
-+			if ((return_code = Si2168B_LoadFirmware(ctx, Si2169_PATCH_3_0b18, Si2169_PATCH_3_0b18_LINES)) != NO_Si2168B_ERROR) {
-+				SiTRACE ("Si2169_LoadFirmware error 0x%02x: %s\n", return_code, si2168b_error_text(return_code) );
-+				return return_code;
-+			}
-+			fw_loaded++;
-+		}
-+	}
-+#endif /* Si2169_PATCH_3_0b18_LINES */
-+#endif /* Si2169_0_COMPATIBLE */
-+#ifdef    Si2167B_20_COMPATIBLE
-+#ifdef    Si2167B_PATCH_2_0b5_LINES
-+	if (!fw_loaded) {
-+		SiTRACE  ("Is this part a  'Si21%2d_ROM%x_%c_%c_b%d'?\n", Si2167B_PATCH_2_0b5_PART, Si2167B_PATCH_2_0b5_ROM, Si2167B_PATCH_2_0b5_PMAJOR, Si2167B_PATCH_2_0b5_PMINOR, Si2167B_PATCH_2_0b5_PBUILD );
-+		if ((ctx->rsp->part_info.romid  == Si2167B_PATCH_2_0b5_ROM   )
-+				&((ctx->rsp->part_info.part   == 67 ) || (ctx->rsp->part_info.part == 66 ))
-+				& (ctx->rsp->part_info.pmajor == Si2167B_PATCH_2_0b5_PMAJOR)
-+				& (ctx->rsp->part_info.pminor == Si2167B_PATCH_2_0b5_PMINOR)
-+				& (ctx->rsp->part_info.pbuild == Si2167B_PATCH_2_0b5_PBUILD)) {
-+			SiTRACE("Updating FW for 'Si21%2d_FW_%c_%c_b%d'\n", ctx->rsp->part_info.part, ctx->rsp->part_info.pmajor, ctx->rsp->part_info.pminor, ctx->rsp->part_info.pbuild );
-+#ifdef    Si2167B_PATCH_2_0b5_INFOS
-+			SiTRACE("%s\n", Si2167B_PATCH_2_0b5_INFOS);
-+#endif /* Si2167B_PATCH_2_0b5_INFOS */
-+			if ((return_code = Si2167B_LoadFirmware(ctx, Si2167B_PATCH_2_0b5, Si2167B_PATCH_2_0b5_LINES)) != NO_Si2167B_ERROR) {
-+				SiTRACE ("Si2167B_LoadPatch error 0x%02x: %s\n", return_code, Si2167B_L1_API_ERROR_TEXT(return_code) );
-+				return return_code;
-+			}
-+			fw_loaded++;
-+		}
-+	}
-+#endif /* Si2167B_PATCH_2_0b5_LINES */
-+#ifdef    Si2167B_20_PATCH_CUSTOMER_LINES
-+	if (!fw_loaded) {
-+		SiTRACE  ("Is this part a  'Si21%2d_ROM%x_%c_%c_b%d'?\n", Si2167B_20_PATCH_CUSTOMER_PART, Si2167B_20_PATCH_CUSTOMER_ROM, Si2167B_20_PATCH_CUSTOMER_PMAJOR, Si2167B_20_PATCH_CUSTOMER_PMINOR, Si2167B_20_PATCH_CUSTOMER_PBUILD );
-+		if ((ctx->rsp->part_info.romid  == Si2167B_20_PATCH_CUSTOMER_ROM   )
-+				&((ctx->rsp->part_info.part   == 67 ) || (ctx->rsp->part_info.part == 66 ))
-+				& (ctx->rsp->part_info.pmajor == Si2167B_20_PATCH_CUSTOMER_PMAJOR)
-+				& (ctx->rsp->part_info.pminor == Si2167B_20_PATCH_CUSTOMER_PMINOR)
-+				& (ctx->rsp->part_info.pbuild == Si2167B_20_PATCH_CUSTOMER_PBUILD)) {
-+			SiTRACE("Updating FW for 'Si21%2d_ROM%x %c_%c_b%d'\n", ctx->rsp->part_info.part, ctx->rsp->part_info.romid, ctx->rsp->part_info.pmajor, ctx->rsp->part_info.pminor, ctx->rsp->part_info.pbuild );
-+#ifdef    Si2167B_20_PATCH_CUSTOMER_INFOS
-+			SiTRACE(Si2167B_20_PATCH_CUSTOMER_INFOS);
-+#endif /* Si2167B_20_PATCH_CUSTOMER_INFOS */
-+			if ((return_code = Si2167B_LoadFirmware(ctx, Si2167B_20_PATCH_CUSTOMER, Si2167B_20_PATCH_CUSTOMER_LINES)) != NO_Si2167B_ERROR) {
-+				SiTRACE ("Si2167B_LoadFirmware error 0x%02x: %s\n", return_code, Si2167B_L1_API_ERROR_TEXT(return_code) );
-+				return return_code;
-+			}
-+			fw_loaded++;
-+		}
-+	}
-+#endif /* Si2167B_20_PATCH_CUSTOMER_LINES */
-+#ifdef    Si2167B_PATCH_2_0b21_LINES
-+	if (!fw_loaded) {
-+		SiTRACE  ("Is this part a  'Si21%2d_ROM%x_%c_%c_b%d'?\n", Si2167B_PATCH_2_0b21_PART, Si2167B_PATCH_2_0b21_ROM, Si2167B_PATCH_2_0b21_PMAJOR, Si2167B_PATCH_2_0b21_PMINOR, Si2167B_PATCH_2_0b21_PBUILD );
-+		if ((ctx->rsp->part_info.romid  == Si2167B_PATCH_2_0b21_ROM   )
-+				&((ctx->rsp->part_info.part   == 67 ) || (ctx->rsp->part_info.part == 66 ))
-+				& (ctx->rsp->part_info.pmajor == Si2167B_PATCH_2_0b21_PMAJOR)
-+				& (ctx->rsp->part_info.pminor == Si2167B_PATCH_2_0b21_PMINOR)
-+				& (ctx->rsp->part_info.pbuild == Si2167B_PATCH_2_0b21_PBUILD)) {
-+			SiTRACE("Updating FW for 'Si21%2d_FW_%c_%c_b%d'\n", ctx->rsp->part_info.part, ctx->rsp->part_info.pmajor, ctx->rsp->part_info.pminor, ctx->rsp->part_info.pbuild );
-+#ifdef    Si2167B_PATCH_2_0b21_INFOS
-+			SiTRACE("%s\n", Si2167B_PATCH_2_0b21_INFOS);
-+#endif /* Si2167B_PATCH_2_0b21_INFOS */
-+			if ((return_code = Si2168B_LoadFirmware(ctx, Si2167B_PATCH_2_0b21, Si2167B_PATCH_2_0b21_LINES)) != NO_Si2168B_ERROR) {
-+				SiTRACE ("Si2167B_LoadPatch error 0x%02x: %s\n", return_code, si2168b_error_text(return_code) );
-+				return return_code;
-+			}
-+			fw_loaded++;
-+		}
-+	}
-+#endif /* Si2167B_PATCH_2_0b21_LINES */
-+#endif /* Si2167B_20_COMPATIBLE */
-+
-+	if (!fw_loaded) {
-+		SiTRACE ("Si2168B_LoadFirmware error: NO Firmware Loaded! Possible part/code incompatibility !\n");
-+		return ERROR_Si2168B_LOADING_FIRMWARE;
-+	}
-+
-+	/*Start the Firmware */
-+	return_code = si2168b_start_firmware(ctx);
-+	if (return_code != NO_Si2168B_ERROR) {
-+		/* Start firmware */
-+		SiTRACE ("si2168b_start_firmware error 0x%02x: %s\n", return_code, si2168b_error_text(return_code) );
-+		return return_code;
-+	}
-+
-+	return_code = si2168b_get_revision(ctx, &get_rev);
-+	if (return_code == NO_Si2168B_ERROR) {
-+		if ((get_rev.mcm_die) != Si2168B_GET_REV_RESPONSE_MCM_DIE_SINGLE) {
-+			SiTRACE("Si21%2d%d-%c%c%c Die %c Part running 'FW_%c_%cb%d'\n", part_info.part
-+					, 2
-+					, part_info.chiprev + 0x40
-+					, part_info.pmajor
-+					, part_info.pminor
-+					, get_rev.mcm_die   + 0x40
-+					, get_rev.cmpmajor
-+					, get_rev.cmpminor
-+					, get_rev.cmpbuild );
-+		} else {
-+			SiTRACE("Si21%2d-%c%c%c Part running 'FW_%c_%cb%d'\n", part_info.part
-+					, part_info.chiprev + 0x40
-+					, part_info.pmajor
-+					, part_info.pminor
-+					, get_rev.cmpmajor
-+					, get_rev.cmpminor
-+					, get_rev.cmpbuild );
-+		}
-+	}
-+
-+	return NO_Si2168B_ERROR;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_CONFIG_PINS COMMAND                      */
-+/*---------------------------------------------------*/
-+static u8 si2168b_config_pins(si2168b_context *ctx,
-+		u8   gpio0_mode,
-+		u8   gpio0_read,
-+		u8   gpio1_mode,
-+		u8   gpio1_read,
-+		Si2168B_CONFIG_PINS_CMD_REPLY_struct *config_pins)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[3];
-+	u8 rspByteBuffer[3];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B CONFIG_PINS\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_CONFIG_PINS_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( gpio0_mode & Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_MASK ) << Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_LSB|
-+			( gpio0_read & Si2168B_CONFIG_PINS_CMD_GPIO0_READ_MASK ) << Si2168B_CONFIG_PINS_CMD_GPIO0_READ_LSB);
-+	cmdByteBuffer[2] = (u8) ( ( gpio1_mode & Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_MASK ) << Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_LSB|
-+			( gpio1_read & Si2168B_CONFIG_PINS_CMD_GPIO1_READ_MASK ) << Si2168B_CONFIG_PINS_CMD_GPIO1_READ_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 3, cmdByteBuffer) != 3) {
-+		SiTRACE("Error writing CONFIG_PINS bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 3, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling CONFIG_PINS response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	config_pins->gpio0_mode  = (( ( (rspByteBuffer[1]  )) >> Si2168B_CONFIG_PINS_RESPONSE_GPIO0_MODE_LSB  ) & Si2168B_CONFIG_PINS_RESPONSE_GPIO0_MODE_MASK  );
-+	config_pins->gpio0_state = (( ( (rspByteBuffer[1]  )) >> Si2168B_CONFIG_PINS_RESPONSE_GPIO0_STATE_LSB ) & Si2168B_CONFIG_PINS_RESPONSE_GPIO0_STATE_MASK );
-+	config_pins->gpio1_mode  = (( ( (rspByteBuffer[2]  )) >> Si2168B_CONFIG_PINS_RESPONSE_GPIO1_MODE_LSB  ) & Si2168B_CONFIG_PINS_RESPONSE_GPIO1_MODE_MASK  );
-+	config_pins->gpio1_state = (( ( (rspByteBuffer[2]  )) >> Si2168B_CONFIG_PINS_RESPONSE_GPIO1_STATE_LSB ) & Si2168B_CONFIG_PINS_RESPONSE_GPIO1_STATE_MASK );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_DVBT2_TX_ID COMMAND                      */
-+/*---------------------------------------------------*/
-+static u8 si2168b_dvbt2_tx_id(si2168b_context *ctx)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[1];
-+	u8 rspByteBuffer[8];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	dvbt2_tx_id->STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B DVBT2_TX_ID\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DVBT2_TX_ID_CMD;
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 1, cmdByteBuffer) != 1) {
-+		SiTRACE("Error writing DVBT2_TX_ID bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 8, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DVBT2_TX_ID response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	ctx->rsp->dvbt2_tx_id.tx_id_availability =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT2_TX_ID_RESPONSE_TX_ID_AVAILABILITY_LSB ) & Si2168B_DVBT2_TX_ID_RESPONSE_TX_ID_AVAILABILITY_MASK );
-+	ctx->rsp->dvbt2_tx_id.cell_id            =   (( ( (rspByteBuffer[2]  ) | (rspByteBuffer[3]  << 8 )) >> Si2168B_DVBT2_TX_ID_RESPONSE_CELL_ID_LSB            ) & Si2168B_DVBT2_TX_ID_RESPONSE_CELL_ID_MASK            );
-+	ctx->rsp->dvbt2_tx_id.network_id         =   (( ( (rspByteBuffer[4]  ) | (rspByteBuffer[5]  << 8 )) >> Si2168B_DVBT2_TX_ID_RESPONSE_NETWORK_ID_LSB         ) & Si2168B_DVBT2_TX_ID_RESPONSE_NETWORK_ID_MASK         );
-+	ctx->rsp->dvbt2_tx_id.t2_system_id       =   (( ( (rspByteBuffer[6]  ) | (rspByteBuffer[7]  << 8 )) >> Si2168B_DVBT2_TX_ID_RESPONSE_T2_SYSTEM_ID_LSB       ) & Si2168B_DVBT2_TX_ID_RESPONSE_T2_SYSTEM_ID_MASK       );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_SPI_PASSTHROUGH COMMAND                  */
-+/*---------------------------------------------------*/
-+static u8 si2168b_spi_passthrough(si2168b_context *ctx,
-+		u8   subcode,
-+		u8   spi_passthr_clk,
-+		u8   spi_passth_data)
-+{
-+	u8 cmdByteBuffer[4];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	ctx->rsp->spi_passthrough.STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B SPI_PASSTHROUGH\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_SPI_PASSTHROUGH_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( subcode         & Si2168B_SPI_PASSTHROUGH_CMD_SUBCODE_MASK         ) << Si2168B_SPI_PASSTHROUGH_CMD_SUBCODE_LSB        );
-+	cmdByteBuffer[2] = (u8) ( ( spi_passthr_clk & Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_MASK ) << Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_LSB);
-+	cmdByteBuffer[3] = (u8) ( ( spi_passth_data & Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_MASK ) << Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 4, cmdByteBuffer) != 4) {
-+		SiTRACE("Error writing SPI_PASSTHROUGH bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+	}
-+
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_DOWNLOAD_DATASET_CONTINUE COMMAND        */
-+/*---------------------------------------------------*/
-+static u8 si2168b_download_dataset_continue(si2168b_context *ctx,
-+		u8 data0,
-+		u8 data1,
-+		u8 data2,
-+		u8 data3,
-+		u8 data4,
-+		u8 data5,
-+		u8 data6)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[8];
-+	u8 rspByteBuffer[1];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	ctx->rsp->download_dataset_continue.STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B DOWNLOAD_DATASET_CONTINUE\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( data0 & Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA0_MASK ) << Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA0_LSB);
-+	cmdByteBuffer[2] = (u8) ( ( data1 & Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA1_MASK ) << Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA1_LSB);
-+	cmdByteBuffer[3] = (u8) ( ( data2 & Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA2_MASK ) << Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA2_LSB);
-+	cmdByteBuffer[4] = (u8) ( ( data3 & Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA3_MASK ) << Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA3_LSB);
-+	cmdByteBuffer[5] = (u8) ( ( data4 & Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA4_MASK ) << Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA4_LSB);
-+	cmdByteBuffer[6] = (u8) ( ( data5 & Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA5_MASK ) << Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA5_LSB);
-+	cmdByteBuffer[7] = (u8) ( ( data6 & Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA6_MASK ) << Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA6_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 8, cmdByteBuffer) != 8) {
-+		SiTRACE("Error writing DOWNLOAD_DATASET_CONTINUE bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 1, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DOWNLOAD_DATASET_CONTINUE response\n");
-+		ret = error_code;
-+	}
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_DD_EXT_AGC_TER COMMAND                   */
-+/*---------------------------------------------------*/
-+static u8 si2168b_dd_ext_agc_ter(si2168b_context *ctx,
-+		u8   agc_1_mode,
-+		u8   agc_1_inv,
-+		u8   agc_2_mode,
-+		u8   agc_2_inv,
-+		u8   agc_1_kloop,
-+		u8   agc_2_kloop,
-+		u8   agc_1_min,
-+		u8   agc_2_min,
-+		Si2168B_DD_EXT_AGC_TER_CMD_REPLY_struct *dd_ext_agc_ter)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[6];
-+	u8 rspByteBuffer[3];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B DD_EXT_AGC_TER\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DD_EXT_AGC_TER_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( agc_1_mode  & Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_MASK  ) << Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_LSB |
-+			( agc_1_inv   & Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_INV_MASK   ) << Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_INV_LSB  |
-+			( agc_2_mode  & Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MODE_MASK  ) << Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MODE_LSB |
-+			( agc_2_inv   & Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_INV_MASK   ) << Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_INV_LSB  );
-+	cmdByteBuffer[2] = (u8) ( ( agc_1_kloop & Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_KLOOP_MASK ) << Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_KLOOP_LSB);
-+	cmdByteBuffer[3] = (u8) ( ( agc_2_kloop & Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_KLOOP_MASK ) << Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_KLOOP_LSB);
-+	cmdByteBuffer[4] = (u8) ( ( agc_1_min   & Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MIN_MASK   ) << Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MIN_LSB  );
-+	cmdByteBuffer[5] = (u8) ( ( agc_2_min   & Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MIN_MASK   ) << Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MIN_LSB  );
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 6, cmdByteBuffer) != 6) {
-+		SiTRACE("Error writing DD_EXT_AGC_TER bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 3, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DD_EXT_AGC_TER response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	dd_ext_agc_ter->agc_1_level = (( ( (rspByteBuffer[1]  )) >> Si2168B_DD_EXT_AGC_TER_RESPONSE_AGC_1_LEVEL_LSB ) & Si2168B_DD_EXT_AGC_TER_RESPONSE_AGC_1_LEVEL_MASK );
-+	dd_ext_agc_ter->agc_2_level = (( ( (rspByteBuffer[2]  )) >> Si2168B_DD_EXT_AGC_TER_RESPONSE_AGC_2_LEVEL_LSB ) & Si2168B_DD_EXT_AGC_TER_RESPONSE_AGC_2_LEVEL_MASK );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_GET_PROPERTY COMMAND                     */
-+/*---------------------------------------------------*/
-+static u8 si2168b_get_property(si2168b_context *ctx,
-+		u8   reserved,
-+		unsigned int    prop)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[4];
-+	u8 rspByteBuffer[4];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	ctx->rsp->get_property.STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B GET_PROPERTY\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_GET_PROPERTY_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( reserved & Si2168B_GET_PROPERTY_CMD_RESERVED_MASK ) << Si2168B_GET_PROPERTY_CMD_RESERVED_LSB);
-+	cmdByteBuffer[2] = (u8) ( ( prop     & Si2168B_GET_PROPERTY_CMD_PROP_MASK     ) << Si2168B_GET_PROPERTY_CMD_PROP_LSB    );
-+	cmdByteBuffer[3] = (u8) ((( prop     & Si2168B_GET_PROPERTY_CMD_PROP_MASK     ) << Si2168B_GET_PROPERTY_CMD_PROP_LSB    )>>8);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 4, cmdByteBuffer) != 4) {
-+		SiTRACE("Error writing GET_PROPERTY bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 4, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling GET_PROPERTY response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	ctx->rsp->get_property.reserved =   (( ( (rspByteBuffer[1]  )) >> Si2168B_GET_PROPERTY_RESPONSE_RESERVED_LSB ) & Si2168B_GET_PROPERTY_RESPONSE_RESERVED_MASK );
-+	ctx->rsp->get_property.data     =   (( ( (rspByteBuffer[2]  ) | (rspByteBuffer[3]  << 8 )) >> Si2168B_GET_PROPERTY_RESPONSE_DATA_LSB     ) & Si2168B_GET_PROPERTY_RESPONSE_DATA_MASK     );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_DD_MP_DEFAULTS COMMAND                   */
-+/*---------------------------------------------------*/
-+static u8 si2168b_dd_mp_defaults(si2168b_context *ctx,
-+		u8 mp_a_mode,
-+		u8 mp_b_mode,
-+		u8 mp_c_mode,
-+		u8 mp_d_mode,
-+		Si2168B_DD_MP_DEFAULTS_CMD_REPLY_struct *dd_mp_defaults)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[5];
-+	u8 rspByteBuffer[5];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B DD_MP_DEFAULTS\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DD_MP_DEFAULTS_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( mp_a_mode & Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_MASK ) << Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_LSB);
-+	cmdByteBuffer[2] = (u8) ( ( mp_b_mode & Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_MASK ) << Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_LSB);
-+	cmdByteBuffer[3] = (u8) ( ( mp_c_mode & Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_MASK ) << Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_LSB);
-+	cmdByteBuffer[4] = (u8) ( ( mp_d_mode & Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_MASK ) << Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 5, cmdByteBuffer) != 5) {
-+		SiTRACE("Error writing DD_MP_DEFAULTS bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 5, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DD_MP_DEFAULTS response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	dd_mp_defaults->mp_a_mode = (( ( (rspByteBuffer[1]  )) >> Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_A_MODE_LSB ) & Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_A_MODE_MASK );
-+	dd_mp_defaults->mp_b_mode = (( ( (rspByteBuffer[2]  )) >> Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_B_MODE_LSB ) & Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_B_MODE_MASK );
-+	dd_mp_defaults->mp_c_mode = (( ( (rspByteBuffer[3]  )) >> Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_C_MODE_LSB ) & Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_C_MODE_MASK );
-+	dd_mp_defaults->mp_d_mode = (( ( (rspByteBuffer[4]  )) >> Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_D_MODE_LSB ) & Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_D_MODE_MASK );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_DD_FER COMMAND                           */
-+/*---------------------------------------------------*/
-+static u8 Si2168B_L1_DD_FER(si2168b_context *ctx, u8 rst)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[3];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	ctx->rsp->dd_fer.STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B DD_FER\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DD_FER_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( rst & Si2168B_DD_FER_CMD_RST_MASK ) << Si2168B_DD_FER_CMD_RST_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing DD_FER bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 3, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DD_FER response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	ctx->rsp->dd_fer.exp  =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DD_FER_RESPONSE_EXP_LSB  ) & Si2168B_DD_FER_RESPONSE_EXP_MASK  );
-+	ctx->rsp->dd_fer.mant =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DD_FER_RESPONSE_MANT_LSB ) & Si2168B_DD_FER_RESPONSE_MANT_MASK );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_SPI_LINK COMMAND                         */
-+/*---------------------------------------------------*/
-+static u8 Si2168B_L1_SPI_LINK(si2168b_context *ctx,
-+		u8   subcode,
-+		u8   spi_pbl_key,
-+		u8   spi_pbl_num,
-+		u8   spi_conf_clk,
-+		u8   spi_clk_pola,
-+		u8   spi_conf_data,
-+		u8   spi_data_dir,
-+		u8   spi_enable)
-+{
-+	u8 cmdByteBuffer[7];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	ctx->rsp->spi_link.STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B SPI_LINK\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_SPI_LINK_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( subcode       & Si2168B_SPI_LINK_CMD_SUBCODE_MASK       ) << Si2168B_SPI_LINK_CMD_SUBCODE_LSB      );
-+	cmdByteBuffer[2] = (u8) ( ( spi_pbl_key   & Si2168B_SPI_LINK_CMD_SPI_PBL_KEY_MASK   ) << Si2168B_SPI_LINK_CMD_SPI_PBL_KEY_LSB  );
-+	cmdByteBuffer[3] = (u8) ( ( spi_pbl_num   & Si2168B_SPI_LINK_CMD_SPI_PBL_NUM_MASK   ) << Si2168B_SPI_LINK_CMD_SPI_PBL_NUM_LSB  );
-+	cmdByteBuffer[4] = (u8) ( ( spi_conf_clk  & Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_MASK  ) << Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_LSB |
-+			( spi_clk_pola  & Si2168B_SPI_LINK_CMD_SPI_CLK_POLA_MASK  ) << Si2168B_SPI_LINK_CMD_SPI_CLK_POLA_LSB );
-+	cmdByteBuffer[5] = (u8) ( ( spi_conf_data & Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_MASK ) << Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_LSB|
-+			( spi_data_dir  & Si2168B_SPI_LINK_CMD_SPI_DATA_DIR_MASK  ) << Si2168B_SPI_LINK_CMD_SPI_DATA_DIR_LSB );
-+	cmdByteBuffer[6] = (u8) ( ( spi_enable    & Si2168B_SPI_LINK_CMD_SPI_ENABLE_MASK    ) << Si2168B_SPI_LINK_CMD_SPI_ENABLE_LSB   );
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 7, cmdByteBuffer) != 7) {
-+		SiTRACE("Error writing SPI_LINK bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+	}
-+
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_DOWNLOAD_DATASET_START COMMAND           */
-+/*---------------------------------------------------*/
-+static u8 Si2168B_L1_DOWNLOAD_DATASET_START(si2168b_context *ctx,
-+		u8   dataset_id,
-+		u8   dataset_checksum,
-+		u8   data0,
-+		u8   data1,
-+		u8   data2,
-+		u8   data3,
-+		u8   data4)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[8];
-+	u8 rspByteBuffer[1];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	ctx->rsp->download_dataset_start.STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B DOWNLOAD_DATASET_START\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DOWNLOAD_DATASET_START_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( dataset_id       & Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_ID_MASK       ) << Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_ID_LSB      );
-+	cmdByteBuffer[2] = (u8) ( ( dataset_checksum & Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_CHECKSUM_MASK ) << Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_CHECKSUM_LSB);
-+	cmdByteBuffer[3] = (u8) ( ( data0            & Si2168B_DOWNLOAD_DATASET_START_CMD_DATA0_MASK            ) << Si2168B_DOWNLOAD_DATASET_START_CMD_DATA0_LSB           );
-+	cmdByteBuffer[4] = (u8) ( ( data1            & Si2168B_DOWNLOAD_DATASET_START_CMD_DATA1_MASK            ) << Si2168B_DOWNLOAD_DATASET_START_CMD_DATA1_LSB           );
-+	cmdByteBuffer[5] = (u8) ( ( data2            & Si2168B_DOWNLOAD_DATASET_START_CMD_DATA2_MASK            ) << Si2168B_DOWNLOAD_DATASET_START_CMD_DATA2_LSB           );
-+	cmdByteBuffer[6] = (u8) ( ( data3            & Si2168B_DOWNLOAD_DATASET_START_CMD_DATA3_MASK            ) << Si2168B_DOWNLOAD_DATASET_START_CMD_DATA3_LSB           );
-+	cmdByteBuffer[7] = (u8) ( ( data4            & Si2168B_DOWNLOAD_DATASET_START_CMD_DATA4_MASK            ) << Si2168B_DOWNLOAD_DATASET_START_CMD_DATA4_LSB           );
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 8, cmdByteBuffer) != 8) {
-+		SiTRACE("Error writing DOWNLOAD_DATASET_START bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 1, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DOWNLOAD_DATASET_START response\n");
-+		ret = error_code;
-+	}
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_RSSI_ADC COMMAND                         */
-+/*---------------------------------------------------*/
-+static u8 Si2168B_L1_RSSI_ADC(si2168b_context *ctx, u8 on_off)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[2];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	ctx->rsp->rssi_adc.STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B RSSI_ADC\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_RSSI_ADC_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( on_off & Si2168B_RSSI_ADC_CMD_ON_OFF_MASK ) << Si2168B_RSSI_ADC_CMD_ON_OFF_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing RSSI_ADC bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 2, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling RSSI_ADC response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	ctx->rsp->rssi_adc.level = (( ( (rspByteBuffer[1]  )) >> Si2168B_RSSI_ADC_RESPONSE_LEVEL_LSB ) & Si2168B_RSSI_ADC_RESPONSE_LEVEL_MASK );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_DD_SET_REG COMMAND                       */
-+/*---------------------------------------------------*/
-+static u8 Si2168B_L1_DD_SET_REG(si2168b_context *ctx,
-+		u8   reg_code_lsb,
-+		u8   reg_code_mid,
-+		u8   reg_code_msb,
-+		unsigned long   value)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[8];
-+	u8 rspByteBuffer[1];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	ctx->rsp->dd_set_reg.STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B DD_SET_REG\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DD_SET_REG_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( reg_code_lsb & Si2168B_DD_SET_REG_CMD_REG_CODE_LSB_MASK ) << Si2168B_DD_SET_REG_CMD_REG_CODE_LSB_LSB);
-+	cmdByteBuffer[2] = (u8) ( ( reg_code_mid & Si2168B_DD_SET_REG_CMD_REG_CODE_MID_MASK ) << Si2168B_DD_SET_REG_CMD_REG_CODE_MID_LSB);
-+	cmdByteBuffer[3] = (u8) ( ( reg_code_msb & Si2168B_DD_SET_REG_CMD_REG_CODE_MSB_MASK ) << Si2168B_DD_SET_REG_CMD_REG_CODE_MSB_LSB);
-+	cmdByteBuffer[4] = (u8) ( ( value        & Si2168B_DD_SET_REG_CMD_VALUE_MASK        ) << Si2168B_DD_SET_REG_CMD_VALUE_LSB       );
-+	cmdByteBuffer[5] = (u8) ((( value        & Si2168B_DD_SET_REG_CMD_VALUE_MASK        ) << Si2168B_DD_SET_REG_CMD_VALUE_LSB       )>>8);
-+	cmdByteBuffer[6] = (u8) ((( value        & Si2168B_DD_SET_REG_CMD_VALUE_MASK        ) << Si2168B_DD_SET_REG_CMD_VALUE_LSB       )>>16);
-+	cmdByteBuffer[7] = (u8) ((( value        & Si2168B_DD_SET_REG_CMD_VALUE_MASK        ) << Si2168B_DD_SET_REG_CMD_VALUE_LSB       )>>24);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 8, cmdByteBuffer) != 8) {
-+		SiTRACE("Error writing DD_SET_REG bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 1, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DD_SET_REG response\n");
-+		ret = error_code;
-+	}
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_DD_GET_REG COMMAND                       */
-+/*---------------------------------------------------*/
-+static u8 Si2168B_L1_DD_GET_REG(si2168b_context *ctx,
-+		u8   reg_code_lsb,
-+		u8   reg_code_mid,
-+		u8   reg_code_msb)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[4];
-+	u8 rspByteBuffer[5];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	ctx->rsp->dd_get_reg.STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B DD_GET_REG\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DD_GET_REG_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( reg_code_lsb & Si2168B_DD_GET_REG_CMD_REG_CODE_LSB_MASK ) << Si2168B_DD_GET_REG_CMD_REG_CODE_LSB_LSB);
-+	cmdByteBuffer[2] = (u8) ( ( reg_code_mid & Si2168B_DD_GET_REG_CMD_REG_CODE_MID_MASK ) << Si2168B_DD_GET_REG_CMD_REG_CODE_MID_LSB);
-+	cmdByteBuffer[3] = (u8) ( ( reg_code_msb & Si2168B_DD_GET_REG_CMD_REG_CODE_MSB_MASK ) << Si2168B_DD_GET_REG_CMD_REG_CODE_MSB_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 4, cmdByteBuffer) != 4) {
-+		SiTRACE("Error writing DD_GET_REG bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 5, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DD_GET_REG response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	ctx->rsp->dd_get_reg.data1 =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DD_GET_REG_RESPONSE_DATA1_LSB ) & Si2168B_DD_GET_REG_RESPONSE_DATA1_MASK );
-+	ctx->rsp->dd_get_reg.data2 =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DD_GET_REG_RESPONSE_DATA2_LSB ) & Si2168B_DD_GET_REG_RESPONSE_DATA2_MASK );
-+	ctx->rsp->dd_get_reg.data3 =   (( ( (rspByteBuffer[3]  )) >> Si2168B_DD_GET_REG_RESPONSE_DATA3_LSB ) & Si2168B_DD_GET_REG_RESPONSE_DATA3_MASK );
-+	ctx->rsp->dd_get_reg.data4 =   (( ( (rspByteBuffer[4]  )) >> Si2168B_DD_GET_REG_RESPONSE_DATA4_LSB ) & Si2168B_DD_GET_REG_RESPONSE_DATA4_MASK );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_DVBT2_PLP_INFO COMMAND                   */
-+/*---------------------------------------------------*/
-+static u8 si2168b_dvbt2_plp_info(si2168b_context *ctx, u8 plp_index, Si2168B_DVBT2_PLP_INFO_CMD_REPLY_struct *dvbt2_plp_info)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[13];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B DVBT2_PLP_INFO\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DVBT2_PLP_INFO_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( plp_index & Si2168B_DVBT2_PLP_INFO_CMD_PLP_INDEX_MASK ) << Si2168B_DVBT2_PLP_INFO_CMD_PLP_INDEX_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing DVBT2_PLP_INFO bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 13, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DVBT2_PLP_INFO response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	dvbt2_plp_info->plp_id                 =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_ID_LSB                 ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_ID_MASK                 );
-+	dvbt2_plp_info->plp_payload_type       =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_PAYLOAD_TYPE_LSB       ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_PAYLOAD_TYPE_MASK       );
-+	dvbt2_plp_info->plp_type               =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_TYPE_LSB               ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_TYPE_MASK               );
-+	dvbt2_plp_info->first_frame_idx_msb    =   (( ( (rspByteBuffer[3]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_FIRST_FRAME_IDX_MSB_LSB    ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_FIRST_FRAME_IDX_MSB_MASK    );
-+	dvbt2_plp_info->first_rf_idx           =   (( ( (rspByteBuffer[3]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_FIRST_RF_IDX_LSB           ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_FIRST_RF_IDX_MASK           );
-+	dvbt2_plp_info->ff_flag                =   (( ( (rspByteBuffer[3]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_FF_FLAG_LSB                ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_FF_FLAG_MASK                );
-+	dvbt2_plp_info->plp_group_id_msb       =   (( ( (rspByteBuffer[4]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_GROUP_ID_MSB_LSB       ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_GROUP_ID_MSB_MASK       );
-+	dvbt2_plp_info->first_frame_idx_lsb    =   (( ( (rspByteBuffer[4]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_FIRST_FRAME_IDX_LSB_LSB    ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_FIRST_FRAME_IDX_LSB_MASK    );
-+	dvbt2_plp_info->plp_mod_msb            =   (( ( (rspByteBuffer[5]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MOD_MSB_LSB            ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MOD_MSB_MASK            );
-+	dvbt2_plp_info->plp_cod                =   (( ( (rspByteBuffer[5]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_COD_LSB                ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_COD_MASK                );
-+	dvbt2_plp_info->plp_group_id_lsb       =   (( ( (rspByteBuffer[5]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_GROUP_ID_LSB_LSB       ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_GROUP_ID_LSB_MASK       );
-+	dvbt2_plp_info->plp_num_blocks_max_msb =   (( ( (rspByteBuffer[6]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_NUM_BLOCKS_MAX_MSB_LSB ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_NUM_BLOCKS_MAX_MSB_MASK );
-+	dvbt2_plp_info->plp_fec_type           =   (( ( (rspByteBuffer[6]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_FEC_TYPE_LSB           ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_FEC_TYPE_MASK           );
-+	dvbt2_plp_info->plp_rot                =   (( ( (rspByteBuffer[6]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_ROT_LSB                ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_ROT_MASK                );
-+	dvbt2_plp_info->plp_mod_lsb            =   (( ( (rspByteBuffer[6]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MOD_LSB_LSB            ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MOD_LSB_MASK            );
-+	dvbt2_plp_info->frame_interval_msb     =   (( ( (rspByteBuffer[7]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_FRAME_INTERVAL_MSB_LSB     ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_FRAME_INTERVAL_MSB_MASK     );
-+	dvbt2_plp_info->plp_num_blocks_max_lsb =   (( ( (rspByteBuffer[7]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_NUM_BLOCKS_MAX_LSB_LSB ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_NUM_BLOCKS_MAX_LSB_MASK );
-+	dvbt2_plp_info->time_il_length_msb     =   (( ( (rspByteBuffer[8]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_TIME_IL_LENGTH_MSB_LSB     ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_TIME_IL_LENGTH_MSB_MASK     );
-+	dvbt2_plp_info->frame_interval_lsb     =   (( ( (rspByteBuffer[8]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_FRAME_INTERVAL_LSB_LSB     ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_FRAME_INTERVAL_LSB_MASK     );
-+	dvbt2_plp_info->time_il_type           =   (( ( (rspByteBuffer[9]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_TIME_IL_TYPE_LSB           ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_TIME_IL_TYPE_MASK           );
-+	dvbt2_plp_info->time_il_length_lsb     =   (( ( (rspByteBuffer[9]  )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_TIME_IL_LENGTH_LSB_LSB     ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_TIME_IL_LENGTH_LSB_MASK     );
-+	dvbt2_plp_info->reserved_1_1           =   (( ( (rspByteBuffer[10] )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_RESERVED_1_1_LSB           ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_RESERVED_1_1_MASK           );
-+	dvbt2_plp_info->in_band_b_flag         =   (( ( (rspByteBuffer[10] )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_IN_BAND_B_FLAG_LSB         ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_IN_BAND_B_FLAG_MASK         );
-+	dvbt2_plp_info->in_band_a_flag         =   (( ( (rspByteBuffer[10] )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_IN_BAND_A_FLAG_LSB         ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_IN_BAND_A_FLAG_MASK         );
-+	dvbt2_plp_info->static_flag            =   (( ( (rspByteBuffer[11] )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_STATIC_FLAG_LSB            ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_STATIC_FLAG_MASK            );
-+	dvbt2_plp_info->plp_mode               =   (( ( (rspByteBuffer[11] )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MODE_LSB               ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MODE_MASK               );
-+	dvbt2_plp_info->reserved_1_2           =   (( ( (rspByteBuffer[11] )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_RESERVED_1_2_LSB           ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_RESERVED_1_2_MASK           );
-+	dvbt2_plp_info->static_padding_flag    =   (( ( (rspByteBuffer[12] )) >> Si2168B_DVBT2_PLP_INFO_RESPONSE_STATIC_PADDING_FLAG_LSB    ) & Si2168B_DVBT2_PLP_INFO_RESPONSE_STATIC_PADDING_FLAG_MASK    );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2168B_DVBT2_FEF COMMAND                        */
-+/*---------------------------------------------------*/
-+static u8 si2168b_dvbt2_fef(si2168b_context *ctx,
-+		u8   fef_tuner_flag,
-+		u8   fef_tuner_flag_inv,
-+		Si2168B_DVBT2_FEF_CMD_REPLY_struct *dvbt2_fef)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[12];
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("Si2168B DVBT2_FEF\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DVBT2_FEF_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( fef_tuner_flag     & Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MASK     ) << Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_LSB    |
-+			( fef_tuner_flag_inv & Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_INV_MASK ) << Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_INV_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing DVBT2_FEF bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 12, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DVBT2_FEF response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	dvbt2_fef->fef_type       =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT2_FEF_RESPONSE_FEF_TYPE_LSB       ) & Si2168B_DVBT2_FEF_RESPONSE_FEF_TYPE_MASK       );
-+	dvbt2_fef->fef_length     =   (( ( (rspByteBuffer[4]  ) | (rspByteBuffer[5]  << 8 ) | (rspByteBuffer[6]  << 16 ) | (rspByteBuffer[7]  << 24 )) >> Si2168B_DVBT2_FEF_RESPONSE_FEF_LENGTH_LSB     ) & Si2168B_DVBT2_FEF_RESPONSE_FEF_LENGTH_MASK     );
-+	dvbt2_fef->fef_repetition =   (( ( (rspByteBuffer[8]  ) | (rspByteBuffer[9]  << 8 ) | (rspByteBuffer[10] << 16 ) | (rspByteBuffer[11] << 24 )) >> Si2168B_DVBT2_FEF_RESPONSE_FEF_REPETITION_LSB ) & Si2168B_DVBT2_FEF_RESPONSE_FEF_REPETITION_MASK );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_DD_CBER COMMAND                          */
-+/*---------------------------------------------------*/
-+static u8 Si2168B_L1_DD_CBER(si2168b_context *ctx, u8 rst)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[3];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	ctx->rsp->dd_cber.STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B DD_CBER\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DD_CBER_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( rst & Si2168B_DD_CBER_CMD_RST_MASK ) << Si2168B_DD_CBER_CMD_RST_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing DD_CBER bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 3, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DD_CBER response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	ctx->rsp->dd_cber.exp  =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DD_CBER_RESPONSE_EXP_LSB  ) & Si2168B_DD_CBER_RESPONSE_EXP_MASK  );
-+	ctx->rsp->dd_cber.mant =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DD_CBER_RESPONSE_MANT_LSB ) & Si2168B_DD_CBER_RESPONSE_MANT_MASK );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_CONFIG_CLKIO COMMAND                     */
-+/*---------------------------------------------------*/
-+static u8 Si2168B_L1_CONFIG_CLKIO(si2168b_context *ctx,
-+		u8   output,
-+		u8   pre_driver_str,
-+		u8   driver_str)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[4];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	ctx->rsp->config_clkio.STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B CONFIG_CLKIO\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_CONFIG_CLKIO_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( output         & Si2168B_CONFIG_CLKIO_CMD_OUTPUT_MASK         ) << Si2168B_CONFIG_CLKIO_CMD_OUTPUT_LSB        |
-+			( pre_driver_str & Si2168B_CONFIG_CLKIO_CMD_PRE_DRIVER_STR_MASK ) << Si2168B_CONFIG_CLKIO_CMD_PRE_DRIVER_STR_LSB|
-+			( driver_str     & Si2168B_CONFIG_CLKIO_CMD_DRIVER_STR_MASK     ) << Si2168B_CONFIG_CLKIO_CMD_DRIVER_STR_LSB    );
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing CONFIG_CLKIO bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 4, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling CONFIG_CLKIO response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	ctx->rsp->config_clkio.mode           =   (( ( (rspByteBuffer[1]  )) >> Si2168B_CONFIG_CLKIO_RESPONSE_MODE_LSB           ) & Si2168B_CONFIG_CLKIO_RESPONSE_MODE_MASK           );
-+	ctx->rsp->config_clkio.pre_driver_str =   (( ( (rspByteBuffer[2]  )) >> Si2168B_CONFIG_CLKIO_RESPONSE_PRE_DRIVER_STR_LSB ) & Si2168B_CONFIG_CLKIO_RESPONSE_PRE_DRIVER_STR_MASK );
-+	ctx->rsp->config_clkio.driver_str     =   (( ( (rspByteBuffer[3]  )) >> Si2168B_CONFIG_CLKIO_RESPONSE_DRIVER_STR_LSB     ) & Si2168B_CONFIG_CLKIO_RESPONSE_DRIVER_STR_MASK     );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_DVBT_TPS_EXTRA COMMAND                   */
-+/*---------------------------------------------------*/
-+static u8 Si2168B_L1_DVBT_TPS_EXTRA(si2168b_context *ctx)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[1];
-+	u8 rspByteBuffer[6];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	ctx->rsp->dvbt_tps_extra.STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B DVBT_TPS_EXTRA\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DVBT_TPS_EXTRA_CMD;
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 1, cmdByteBuffer) != 1) {
-+		SiTRACE("Error writing DVBT_TPS_EXTRA bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 6, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DVBT_TPS_EXTRA response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	ctx->rsp->dvbt_tps_extra.lptimeslice =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT_TPS_EXTRA_RESPONSE_LPTIMESLICE_LSB ) & Si2168B_DVBT_TPS_EXTRA_RESPONSE_LPTIMESLICE_MASK );
-+	ctx->rsp->dvbt_tps_extra.hptimeslice =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT_TPS_EXTRA_RESPONSE_HPTIMESLICE_LSB ) & Si2168B_DVBT_TPS_EXTRA_RESPONSE_HPTIMESLICE_MASK );
-+	ctx->rsp->dvbt_tps_extra.lpmpefec    =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT_TPS_EXTRA_RESPONSE_LPMPEFEC_LSB    ) & Si2168B_DVBT_TPS_EXTRA_RESPONSE_LPMPEFEC_MASK    );
-+	ctx->rsp->dvbt_tps_extra.hpmpefec    =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT_TPS_EXTRA_RESPONSE_HPMPEFEC_LSB    ) & Si2168B_DVBT_TPS_EXTRA_RESPONSE_HPMPEFEC_MASK    );
-+	ctx->rsp->dvbt_tps_extra.dvbhinter   =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DVBT_TPS_EXTRA_RESPONSE_DVBHINTER_LSB   ) & Si2168B_DVBT_TPS_EXTRA_RESPONSE_DVBHINTER_MASK   );
-+	ctx->rsp->dvbt_tps_extra.cell_id     = (((( ( (rspByteBuffer[2]  ) | (rspByteBuffer[3]  << 8 )) >> Si2168B_DVBT_TPS_EXTRA_RESPONSE_CELL_ID_LSB     ) & Si2168B_DVBT_TPS_EXTRA_RESPONSE_CELL_ID_MASK) <<Si2168B_DVBT_TPS_EXTRA_RESPONSE_CELL_ID_SHIFT ) >>Si2168B_DVBT_TPS_EXTRA_RESPONSE_CELL_ID_SHIFT     );
-+	ctx->rsp->dvbt_tps_extra.tps_res1    =   (( ( (rspByteBuffer[4]  )) >> Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES1_LSB    ) & Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES1_MASK    );
-+	ctx->rsp->dvbt_tps_extra.tps_res2    =   (( ( (rspByteBuffer[4]  )) >> Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES2_LSB    ) & Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES2_MASK    );
-+	ctx->rsp->dvbt_tps_extra.tps_res3    =   (( ( (rspByteBuffer[5]  )) >> Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES3_LSB    ) & Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES3_MASK    );
-+	ctx->rsp->dvbt_tps_extra.tps_res4    =   (( ( (rspByteBuffer[5]  )) >> Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES4_LSB    ) & Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES4_MASK    );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_DD_PER COMMAND                           */
-+/*---------------------------------------------------*/
-+static u8 Si2168B_L1_DD_PER(si2168b_context *ctx, u8 rst)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[3];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	ctx->rsp->dd_per.STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B DD_PER\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DD_PER_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( rst & Si2168B_DD_PER_CMD_RST_MASK ) << Si2168B_DD_PER_CMD_RST_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing DD_PER bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 3, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DD_PER response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	ctx->rsp->dd_per.exp  =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DD_PER_RESPONSE_EXP_LSB  ) & Si2168B_DD_PER_RESPONSE_EXP_MASK  );
-+	ctx->rsp->dd_per.mant =   (( ( (rspByteBuffer[2]  )) >> Si2168B_DD_PER_RESPONSE_MANT_LSB ) & Si2168B_DD_PER_RESPONSE_MANT_MASK );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+#ifdef __EXTRA_COMMANDS__
-+/*---------------------------------------------------*/
-+/* Si2168B_DD_SSI_SQI COMMAND                       */
-+/*---------------------------------------------------*/
-+static u8 Si2168B_L1_DD_SSI_SQI(si2168b_context *ctx, char tuner_rssi)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[3];
-+	u8 ret = NO_Si2168B_ERROR;
-+#ifdef __COMMONREPLYOBJ__
-+	ctx->rsp->dd_ssi_sqi.STATUS = ctx->status;
-+#endif
-+
-+	SiTRACE("Si2168B DD_SSI_SQI\n");
-+
-+	_mutex_lock(&ctx->lock);
-+
-+	cmdByteBuffer[0] = Si2168B_DD_SSI_SQI_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( tuner_rssi & Si2168B_DD_SSI_SQI_CMD_TUNER_RSSI_MASK ) << Si2168B_DD_SSI_SQI_CMD_TUNER_RSSI_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing DD_SSI_SQI bytes!\n");
-+		ret = ERROR_Si2168B_SENDING_COMMAND;
-+		goto unlock_mutex;
-+	}
-+
-+	error_code = si2168b_poll_for_response(ctx, 3, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling DD_SSI_SQI response\n");
-+		ret = error_code;
-+		goto unlock_mutex;
-+	}
-+
-+	ctx->rsp->dd_ssi_sqi.ssi =   (( ( (rspByteBuffer[1]  )) >> Si2168B_DD_SSI_SQI_RESPONSE_SSI_LSB ) & Si2168B_DD_SSI_SQI_RESPONSE_SSI_MASK );
-+	ctx->rsp->dd_ssi_sqi.sqi = (((( ( (rspByteBuffer[2]  )) >> Si2168B_DD_SSI_SQI_RESPONSE_SQI_LSB ) & Si2168B_DD_SSI_SQI_RESPONSE_SQI_MASK) <<Si2168B_DD_SSI_SQI_RESPONSE_SQI_SHIFT ) >>Si2168B_DD_SSI_SQI_RESPONSE_SQI_SHIFT );
-+
-+unlock_mutex:
-+	_mutex_unlock(&ctx->lock);
-+
-+	return ret;
-+}
-+#endif
-+
-+/*****************************************************************************************
-+ NAME: si2168b_set_common_properties
-+  DESCRIPTION: Setup Si2168B COMMON properties configuration
-+  This function will download all the COMMON configuration properties.
-+  The function Si2168B_storeUserProperties should be called before the first call to this function.
-+  Parameter:  Pointer to Si2168B Context
-+  Returns:    I2C transaction error code, NO_Si2168B_ERROR if successful
-+  Programming Guide Reference:    COMMON setup flowchart
-+******************************************************************************************/
-+static int si2168b_set_common_properties(si2168b_context *ctx)
-+{
-+	const u8 master_ien_ddien   = Si2168B_MASTER_IEN_PROP_DDIEN_OFF   ; /* (default 'OFF') */
-+	const u8 master_ien_scanien = Si2168B_MASTER_IEN_PROP_SCANIEN_OFF ; /* (default 'OFF') */
-+	const u8 master_ien_errien  = Si2168B_MASTER_IEN_PROP_ERRIEN_OFF  ; /* (default 'OFF') */
-+	const u8 master_ien_ctsien  = Si2168B_MASTER_IEN_PROP_CTSIEN_OFF  ; /* (default 'OFF') */
-+
-+	u8  ret;
-+	u8  err = NO_Si2168B_ERROR;
-+	u16 data;
-+
-+	SiTRACE("si2168b_set_common_properties\n");
-+
-+	data = (master_ien_ddien   & Si2168B_MASTER_IEN_PROP_DDIEN_MASK  ) << Si2168B_MASTER_IEN_PROP_DDIEN_LSB |
-+           (master_ien_scanien & Si2168B_MASTER_IEN_PROP_SCANIEN_MASK) << Si2168B_MASTER_IEN_PROP_SCANIEN_LSB |
-+           (master_ien_errien  & Si2168B_MASTER_IEN_PROP_ERRIEN_MASK ) << Si2168B_MASTER_IEN_PROP_ERRIEN_LSB |
-+           (master_ien_ctsien  & Si2168B_MASTER_IEN_PROP_CTSIEN_MASK ) << Si2168B_MASTER_IEN_PROP_CTSIEN_LSB;
-+
-+	ret = si2168b_set_property(ctx, Si2168B_MASTER_IEN_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_MASTER_IEN_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+	return err;
-+}
-+
-+/*****************************************************************************************
-+ NAME: si2168b_set_dd_properties
-+  DESCRIPTION: Setup Si2168B DD properties configuration
-+  This function will download all the DD configuration properties.
-+  The function Si2168B_storeUserProperties should be called before the first call to this function.
-+  Parameter:  Pointer to Si2168B Context
-+  Returns:    I2C transaction error code, NO_Si2168B_ERROR if successful
-+  Programming Guide Reference:    DD setup flowchart
-+******************************************************************************************/
-+static int si2168b_set_dd_properties(si2168b_context *ctx)
-+{
-+	const u8  dd_ber_resol_exp                     = 7; /* (default     7) */
-+	const u8  dd_ber_resol_mant                    = 1; /* (default     1) */
-+	const u8  dd_cber_resol_exp                    = 5; /* (default     5) */
-+	const u8  dd_cber_resol_mant                   = 1; /* (default     1) */
-+	const u8  dd_fer_resol_exp                     = 3; /* (default     3) */
-+	const u8  dd_fer_resol_mant                    = 1; /* (default     1) */
-+    const u8  dd_ien_ien_bit0                      = Si2168B_DD_IEN_PROP_IEN_BIT0_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_ien_ien_bit1                      = Si2168B_DD_IEN_PROP_IEN_BIT1_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_ien_ien_bit2                      = Si2168B_DD_IEN_PROP_IEN_BIT2_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_ien_ien_bit3                      = Si2168B_DD_IEN_PROP_IEN_BIT3_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_ien_ien_bit4                      = Si2168B_DD_IEN_PROP_IEN_BIT4_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_ien_ien_bit5                      = Si2168B_DD_IEN_PROP_IEN_BIT5_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_ien_ien_bit6                      = Si2168B_DD_IEN_PROP_IEN_BIT6_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_ien_ien_bit7                      = Si2168B_DD_IEN_PROP_IEN_BIT7_DISABLE; /* (default 'DISABLE') */
-+	const u16 dd_if_input_freq_offset              = 5000; /* (default  5000) */
-+    const u8  dd_int_sense_neg_bit0                = Si2168B_DD_INT_SENSE_PROP_NEG_BIT0_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_neg_bit1                = Si2168B_DD_INT_SENSE_PROP_NEG_BIT1_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_neg_bit2                = Si2168B_DD_INT_SENSE_PROP_NEG_BIT2_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_neg_bit3                = Si2168B_DD_INT_SENSE_PROP_NEG_BIT3_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_neg_bit4                = Si2168B_DD_INT_SENSE_PROP_NEG_BIT4_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_neg_bit5                = Si2168B_DD_INT_SENSE_PROP_NEG_BIT5_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_neg_bit6                = Si2168B_DD_INT_SENSE_PROP_NEG_BIT6_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_neg_bit7                = Si2168B_DD_INT_SENSE_PROP_NEG_BIT7_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_pos_bit0                = Si2168B_DD_INT_SENSE_PROP_POS_BIT0_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_pos_bit1                = Si2168B_DD_INT_SENSE_PROP_POS_BIT1_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_pos_bit2                = Si2168B_DD_INT_SENSE_PROP_POS_BIT2_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_pos_bit3                = Si2168B_DD_INT_SENSE_PROP_POS_BIT3_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_pos_bit4                = Si2168B_DD_INT_SENSE_PROP_POS_BIT4_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_pos_bit5                = Si2168B_DD_INT_SENSE_PROP_POS_BIT5_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_pos_bit6                = Si2168B_DD_INT_SENSE_PROP_POS_BIT6_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_int_sense_pos_bit7                = Si2168B_DD_INT_SENSE_PROP_POS_BIT7_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_mode_bw                           = Si2168B_DD_MODE_PROP_BW_BW_8MHZ; /* (default 'BW_8MHZ') */
-+    const u8  dd_mode_modulation                   = Si2168B_DD_MODE_PROP_MODULATION_DVBT; /* (default 'DVBT') */
-+    const u8  dd_mode_invert_spectrum              = Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_NORMAL; /* (default 'NORMAL') */
-+    const u8  dd_mode_auto_detect                  = Si2168B_DD_MODE_PROP_AUTO_DETECT_NONE; /* (default 'NONE') */
-+    const u8  dd_per_resol_exp                     = 5; /* (default     5) */
-+    const u8  dd_per_resol_mant                    = 1; /* (default     1) */
-+    const u8  dd_rsq_ber_threshold_exp             = 1; /* (default     1) */
-+    const u8  dd_rsq_ber_threshold_mant            = 10; /* (default    10) */
-+    const u8  dd_ssi_sqi_param_sqi_average         = 1; /* (default     1) */
-+	const u16 dd_ts_freq_req_freq_10khz            = 720; /* (default   720) */
-+    const u8  dd_ts_mode_mode                      = Si2168B_DD_TS_MODE_PROP_MODE_TRISTATE; /* (default 'TRISTATE') */
-+    const u8  dd_ts_mode_clock                     = Si2168B_DD_TS_MODE_PROP_CLOCK_AUTO_FIXED; /* (default 'AUTO_FIXED') */
-+    const u8  dd_ts_mode_clk_gapped_en             = Si2168B_DD_TS_MODE_PROP_CLK_GAPPED_EN_DISABLED; /* (default 'DISABLED') */
-+    const u8  dd_ts_mode_ts_err_polarity           = Si2168B_DD_TS_MODE_PROP_TS_ERR_POLARITY_NOT_INVERTED; /* (default 'NOT_INVERTED') */
-+    const u8  dd_ts_mode_special                   = Si2168B_DD_TS_MODE_PROP_SPECIAL_FULL_TS; /* (default 'FULL_TS') */
-+    const u8  dd_ts_mode_ts_freq_resolution        = Si2168B_DD_TS_MODE_PROP_TS_FREQ_RESOLUTION_NORMAL; /* (default 'NORMAL') */
-+    const u8  dd_ts_serial_diff_ts_data1_strength  = 15; /* (default    15) */
-+    const u8  dd_ts_serial_diff_ts_data1_shape     = 3; /* (default     3) */
-+    const u8  dd_ts_serial_diff_ts_data2_strength  = 15; /* (default    15) */
-+    const u8  dd_ts_serial_diff_ts_data2_shape     = 3; /* (default     3) */
-+    const u8  dd_ts_serial_diff_ts_clkb_on_data1   = Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_CLKB_ON_DATA1_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_ts_serial_diff_ts_data0b_on_data2 = Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA0B_ON_DATA2_DISABLE; /* (default 'DISABLE') */
-+    const u8  dd_ts_setup_par_ts_data_strength     = 3; /* (default     3) */
-+    const u8  dd_ts_setup_par_ts_data_shape        = 1; /* (default     1) */
-+    const u8  dd_ts_setup_par_ts_clk_strength      = 3; /* (default     3) */
-+    const u8  dd_ts_setup_par_ts_clk_shape         = 1; /* (default     1) */
-+    const u8  dd_ts_setup_par_ts_clk_invert        = Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_INVERT_INVERTED; /* (default 'INVERTED') */
-+    const u8  dd_ts_setup_par_ts_clk_shift         = 0; /* (default     0) */
-+    const u8  dd_ts_setup_ser_ts_data_strength     = 15; /* (default    15) */
-+    const u8  dd_ts_setup_ser_ts_data_shape        = 3; /* (default     3) */
-+    const u8  dd_ts_setup_ser_ts_clk_strength      = 15; /* (default    15) */
-+    const u8  dd_ts_setup_ser_ts_clk_shape         = 3; /* (default     3) */
-+    const u8  dd_ts_setup_ser_ts_clk_invert        = Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_INVERT_INVERTED; /* (default 'INVERTED') */
-+    const u8  dd_ts_setup_ser_ts_sync_duration     = Si2168B_DD_TS_SETUP_SER_PROP_TS_SYNC_DURATION_FIRST_BYTE; /* (default 'FIRST_BYTE') */
-+    const u8  dd_ts_setup_ser_ts_byte_order        = Si2168B_DD_TS_SETUP_SER_PROP_TS_BYTE_ORDER_MSB_FIRST; /* (default 'MSB_FIRST') */
-+
-+#ifdef    Si2168B_DD_DISEQC_FREQ_PROP
-+	dd_diseqc_freq.freq_hz                         = 22000; /* (default 22000) */
-+#endif /* Si2168B_DD_DISEQC_FREQ_PROP */
-+
-+#ifdef    Si2168B_DD_DISEQC_PARAM_PROP
-+	dd_diseqc_param.sequence_mode                  = Si2168B_DD_DISEQC_PARAM_PROP_SEQUENCE_MODE_GAP ; /* (default 'GAP') */
-+#endif /* Si2168B_DD_DISEQC_PARAM_PROP */
-+
-+	u8  ret;
-+	u8  err = NO_Si2168B_ERROR;
-+	u16 data;
-+
-+	SiTRACE("si2168b_set_dd_properties\n");
-+
-+    data = (dd_ber_resol_exp  & Si2168B_DD_BER_RESOL_PROP_EXP_MASK ) << Si2168B_DD_BER_RESOL_PROP_EXP_LSB |
-+           (dd_ber_resol_mant & Si2168B_DD_BER_RESOL_PROP_MANT_MASK) << Si2168B_DD_BER_RESOL_PROP_MANT_LSB;
-+	ret = si2168b_set_property(ctx, Si2168B_DD_BER_RESOL_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_BER_RESOL_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dd_cber_resol_exp  & Si2168B_DD_CBER_RESOL_PROP_EXP_MASK ) << Si2168B_DD_CBER_RESOL_PROP_EXP_LSB |
-+           (dd_cber_resol_mant & Si2168B_DD_CBER_RESOL_PROP_MANT_MASK) << Si2168B_DD_CBER_RESOL_PROP_MANT_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DD_CBER_RESOL_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_CBER_RESOL_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dd_fer_resol_exp  & Si2168B_DD_FER_RESOL_PROP_EXP_MASK ) << Si2168B_DD_FER_RESOL_PROP_EXP_LSB |
-+           (dd_fer_resol_mant & Si2168B_DD_FER_RESOL_PROP_MANT_MASK) << Si2168B_DD_FER_RESOL_PROP_MANT_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DD_FER_RESOL_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_FER_RESOL_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dd_ien_ien_bit0 & Si2168B_DD_IEN_PROP_IEN_BIT0_MASK) << Si2168B_DD_IEN_PROP_IEN_BIT0_LSB |
-+           (dd_ien_ien_bit1 & Si2168B_DD_IEN_PROP_IEN_BIT1_MASK) << Si2168B_DD_IEN_PROP_IEN_BIT1_LSB |
-+           (dd_ien_ien_bit2 & Si2168B_DD_IEN_PROP_IEN_BIT2_MASK) << Si2168B_DD_IEN_PROP_IEN_BIT2_LSB |
-+           (dd_ien_ien_bit3 & Si2168B_DD_IEN_PROP_IEN_BIT3_MASK) << Si2168B_DD_IEN_PROP_IEN_BIT3_LSB |
-+           (dd_ien_ien_bit4 & Si2168B_DD_IEN_PROP_IEN_BIT4_MASK) << Si2168B_DD_IEN_PROP_IEN_BIT4_LSB |
-+           (dd_ien_ien_bit5 & Si2168B_DD_IEN_PROP_IEN_BIT5_MASK) << Si2168B_DD_IEN_PROP_IEN_BIT5_LSB |
-+           (dd_ien_ien_bit6 & Si2168B_DD_IEN_PROP_IEN_BIT6_MASK) << Si2168B_DD_IEN_PROP_IEN_BIT6_LSB |
-+           (dd_ien_ien_bit7 & Si2168B_DD_IEN_PROP_IEN_BIT7_MASK) << Si2168B_DD_IEN_PROP_IEN_BIT7_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DD_IEN_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_IEN_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dd_if_input_freq_offset & Si2168B_DD_IF_INPUT_FREQ_PROP_OFFSET_MASK) << Si2168B_DD_IF_INPUT_FREQ_PROP_OFFSET_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DD_IF_INPUT_FREQ_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_IF_INPUT_FREQ_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dd_int_sense_neg_bit0 & Si2168B_DD_INT_SENSE_PROP_NEG_BIT0_MASK) << Si2168B_DD_INT_SENSE_PROP_NEG_BIT0_LSB |
-+           (dd_int_sense_neg_bit1 & Si2168B_DD_INT_SENSE_PROP_NEG_BIT1_MASK) << Si2168B_DD_INT_SENSE_PROP_NEG_BIT1_LSB |
-+           (dd_int_sense_neg_bit2 & Si2168B_DD_INT_SENSE_PROP_NEG_BIT2_MASK) << Si2168B_DD_INT_SENSE_PROP_NEG_BIT2_LSB |
-+           (dd_int_sense_neg_bit3 & Si2168B_DD_INT_SENSE_PROP_NEG_BIT3_MASK) << Si2168B_DD_INT_SENSE_PROP_NEG_BIT3_LSB |
-+           (dd_int_sense_neg_bit4 & Si2168B_DD_INT_SENSE_PROP_NEG_BIT4_MASK) << Si2168B_DD_INT_SENSE_PROP_NEG_BIT4_LSB |
-+           (dd_int_sense_neg_bit5 & Si2168B_DD_INT_SENSE_PROP_NEG_BIT5_MASK) << Si2168B_DD_INT_SENSE_PROP_NEG_BIT5_LSB |
-+           (dd_int_sense_neg_bit6 & Si2168B_DD_INT_SENSE_PROP_NEG_BIT6_MASK) << Si2168B_DD_INT_SENSE_PROP_NEG_BIT6_LSB |
-+           (dd_int_sense_neg_bit7 & Si2168B_DD_INT_SENSE_PROP_NEG_BIT7_MASK) << Si2168B_DD_INT_SENSE_PROP_NEG_BIT7_LSB |
-+           (dd_int_sense_pos_bit0 & Si2168B_DD_INT_SENSE_PROP_POS_BIT0_MASK) << Si2168B_DD_INT_SENSE_PROP_POS_BIT0_LSB |
-+           (dd_int_sense_pos_bit1 & Si2168B_DD_INT_SENSE_PROP_POS_BIT1_MASK) << Si2168B_DD_INT_SENSE_PROP_POS_BIT1_LSB |
-+           (dd_int_sense_pos_bit2 & Si2168B_DD_INT_SENSE_PROP_POS_BIT2_MASK) << Si2168B_DD_INT_SENSE_PROP_POS_BIT2_LSB |
-+           (dd_int_sense_pos_bit3 & Si2168B_DD_INT_SENSE_PROP_POS_BIT3_MASK) << Si2168B_DD_INT_SENSE_PROP_POS_BIT3_LSB |
-+           (dd_int_sense_pos_bit4 & Si2168B_DD_INT_SENSE_PROP_POS_BIT4_MASK) << Si2168B_DD_INT_SENSE_PROP_POS_BIT4_LSB |
-+           (dd_int_sense_pos_bit5 & Si2168B_DD_INT_SENSE_PROP_POS_BIT5_MASK) << Si2168B_DD_INT_SENSE_PROP_POS_BIT5_LSB |
-+           (dd_int_sense_pos_bit6 & Si2168B_DD_INT_SENSE_PROP_POS_BIT6_MASK) << Si2168B_DD_INT_SENSE_PROP_POS_BIT6_LSB |
-+           (dd_int_sense_pos_bit7 & Si2168B_DD_INT_SENSE_PROP_POS_BIT7_MASK) << Si2168B_DD_INT_SENSE_PROP_POS_BIT7_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DD_INT_SENSE_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_INT_SENSE_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dd_mode_bw              & Si2168B_DD_MODE_PROP_BW_MASK             ) << Si2168B_DD_MODE_PROP_BW_LSB |
-+           (dd_mode_modulation      & Si2168B_DD_MODE_PROP_MODULATION_MASK     ) << Si2168B_DD_MODE_PROP_MODULATION_LSB |
-+           (dd_mode_invert_spectrum & Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_MASK) << Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_LSB |
-+           (dd_mode_auto_detect     & Si2168B_DD_MODE_PROP_AUTO_DETECT_MASK    ) << Si2168B_DD_MODE_PROP_AUTO_DETECT_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DD_MODE_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_MODE_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dd_per_resol_exp  & Si2168B_DD_PER_RESOL_PROP_EXP_MASK ) << Si2168B_DD_PER_RESOL_PROP_EXP_LSB |
-+           (dd_per_resol_mant & Si2168B_DD_PER_RESOL_PROP_MANT_MASK) << Si2168B_DD_PER_RESOL_PROP_MANT_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DD_PER_RESOL_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_PER_RESOL_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dd_rsq_ber_threshold_exp  & Si2168B_DD_RSQ_BER_THRESHOLD_PROP_EXP_MASK ) << Si2168B_DD_RSQ_BER_THRESHOLD_PROP_EXP_LSB |
-+           (dd_rsq_ber_threshold_mant & Si2168B_DD_RSQ_BER_THRESHOLD_PROP_MANT_MASK) << Si2168B_DD_RSQ_BER_THRESHOLD_PROP_MANT_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DD_RSQ_BER_THRESHOLD_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_RSQ_BER_THRESHOLD_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dd_ssi_sqi_param_sqi_average & Si2168B_DD_SSI_SQI_PARAM_PROP_SQI_AVERAGE_MASK) << Si2168B_DD_SSI_SQI_PARAM_PROP_SQI_AVERAGE_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DD_SSI_SQI_PARAM_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_SSI_SQI_PARAM_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dd_ts_freq_req_freq_10khz & Si2168B_DD_TS_FREQ_PROP_REQ_FREQ_10KHZ_MASK) << Si2168B_DD_TS_FREQ_PROP_REQ_FREQ_10KHZ_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DD_TS_FREQ_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_TS_FREQ_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dd_ts_mode_mode            & Si2168B_DD_TS_MODE_PROP_MODE_MASK           ) << Si2168B_DD_TS_MODE_PROP_MODE_LSB |
-+           (dd_ts_mode_clock           & Si2168B_DD_TS_MODE_PROP_CLOCK_MASK          ) << Si2168B_DD_TS_MODE_PROP_CLOCK_LSB |
-+           (dd_ts_mode_clk_gapped_en   & Si2168B_DD_TS_MODE_PROP_CLK_GAPPED_EN_MASK  ) << Si2168B_DD_TS_MODE_PROP_CLK_GAPPED_EN_LSB |
-+           (dd_ts_mode_ts_err_polarity & Si2168B_DD_TS_MODE_PROP_TS_ERR_POLARITY_MASK) << Si2168B_DD_TS_MODE_PROP_TS_ERR_POLARITY_LSB |
-+           (dd_ts_mode_special            & Si2168B_DD_TS_MODE_PROP_SPECIAL_MASK     ) << Si2168B_DD_TS_MODE_PROP_SPECIAL_LSB |
-+           (dd_ts_mode_ts_freq_resolution & Si2168B_DD_TS_MODE_PROP_TS_FREQ_RESOLUTION_MASK) << Si2168B_DD_TS_MODE_PROP_TS_FREQ_RESOLUTION_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DD_TS_MODE_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_TS_MODE_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dd_ts_serial_diff_ts_data1_strength  & Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA1_STRENGTH_MASK ) << Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA1_STRENGTH_LSB |
-+           (dd_ts_serial_diff_ts_data1_shape     & Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA1_SHAPE_MASK    ) << Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA1_SHAPE_LSB |
-+           (dd_ts_serial_diff_ts_data2_strength  & Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA2_STRENGTH_MASK ) << Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA2_STRENGTH_LSB |
-+           (dd_ts_serial_diff_ts_data2_shape     & Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA2_SHAPE_MASK    ) << Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA2_SHAPE_LSB |
-+           (dd_ts_serial_diff_ts_clkb_on_data1   & Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_CLKB_ON_DATA1_MASK  ) << Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_CLKB_ON_DATA1_LSB |
-+           (dd_ts_serial_diff_ts_data0b_on_data2 & Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA0B_ON_DATA2_MASK) << Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA0B_ON_DATA2_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DD_TS_SERIAL_DIFF_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_TS_SERIAL_DIFF_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dd_ts_setup_par_ts_data_strength & Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_STRENGTH_MASK) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_STRENGTH_LSB |
-+           (dd_ts_setup_par_ts_data_shape    & Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_SHAPE_MASK   ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_SHAPE_LSB |
-+           (dd_ts_setup_par_ts_clk_strength  & Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_STRENGTH_MASK ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_STRENGTH_LSB |
-+           (dd_ts_setup_par_ts_clk_shape     & Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHAPE_MASK    ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHAPE_LSB |
-+           (dd_ts_setup_par_ts_clk_invert    & Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_INVERT_MASK   ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_INVERT_LSB |
-+           (dd_ts_setup_par_ts_clk_shift     & Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHIFT_MASK    ) << Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHIFT_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DD_TS_SETUP_PAR_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_TS_SETUP_PAR_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dd_ts_setup_ser_ts_data_strength & Si2168B_DD_TS_SETUP_SER_PROP_TS_DATA_STRENGTH_MASK) << Si2168B_DD_TS_SETUP_SER_PROP_TS_DATA_STRENGTH_LSB  |
-+           (dd_ts_setup_ser_ts_data_shape    & Si2168B_DD_TS_SETUP_SER_PROP_TS_DATA_SHAPE_MASK   ) << Si2168B_DD_TS_SETUP_SER_PROP_TS_DATA_SHAPE_LSB  |
-+           (dd_ts_setup_ser_ts_clk_strength  & Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_STRENGTH_MASK ) << Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_STRENGTH_LSB  |
-+           (dd_ts_setup_ser_ts_clk_shape     & Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_SHAPE_MASK    ) << Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_SHAPE_LSB  |
-+           (dd_ts_setup_ser_ts_clk_invert    & Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_INVERT_MASK   ) << Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_INVERT_LSB  |
-+           (dd_ts_setup_ser_ts_sync_duration & Si2168B_DD_TS_SETUP_SER_PROP_TS_SYNC_DURATION_MASK) << Si2168B_DD_TS_SETUP_SER_PROP_TS_SYNC_DURATION_LSB  |
-+           (dd_ts_setup_ser_ts_byte_order    & Si2168B_DD_TS_SETUP_SER_PROP_TS_BYTE_ORDER_MASK   ) << Si2168B_DD_TS_SETUP_SER_PROP_TS_BYTE_ORDER_LSB ;
-+    ret = si2168b_set_property(ctx, Si2168B_DD_TS_SETUP_SER_PROP, data);
-+    pr_info("%s(): setting property Si2168B_DD_TS_SETUP_SER_PROP 0x%04X: data=0x%04X\n", __func__, Si2168B_DD_TS_SETUP_SER_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DD_TS_SETUP_SER_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    return err;
-+}
-+
-+/*****************************************************************************************
-+ NAME: si2168b_set_dvbc_properties
-+  DESCRIPTION: Setup Si2168B DVBC properties configuration
-+  This function will download all the DVBC configuration properties.
-+  The function Si2168B_storeUserProperties should be called before the first call to this function.
-+  Parameter:  Pointer to Si2168B Context
-+  Returns:    I2C transaction error code, NO_Si2168B_ERROR if successful
-+  Programming Guide Reference:    DVBC setup flowchart
-+******************************************************************************************/
-+static int si2168b_set_dvbc_properties(si2168b_context *ctx)
-+{
-+    const u8  dvbc_adc_crest_factor_crest_factor = 112; /* (default   112) */
-+    const u16 dvbc_afc_range_range_khz           = 100; /* (default   100) */
-+    const u8  dvbc_constellation_constellation   = Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_AUTO ; /* (default 'AUTO') */
-+    const u16 dvbc_symbol_rate_rate              = 6900; /* (default  6900) */
-+
-+	u8  ret;
-+	u8  err = NO_Si2168B_ERROR;
-+	u16 data;
-+
-+	SiTRACE("si2168b_set_dvbc_properties\n");
-+
-+    data = (dvbc_adc_crest_factor_crest_factor & Si2168B_DVBC_ADC_CREST_FACTOR_PROP_CREST_FACTOR_MASK) << Si2168B_DVBC_ADC_CREST_FACTOR_PROP_CREST_FACTOR_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DVBC_ADC_CREST_FACTOR_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DVBC_ADC_CREST_FACTOR_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dvbc_afc_range_range_khz & Si2168B_DVBC_AFC_RANGE_PROP_RANGE_KHZ_MASK) << Si2168B_DVBC_AFC_RANGE_PROP_RANGE_KHZ_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DVBC_AFC_RANGE_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DVBC_AFC_RANGE_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dvbc_constellation_constellation & Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_MASK) << Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DVBC_CONSTELLATION_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DVBC_CONSTELLATION_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dvbc_symbol_rate_rate & Si2168B_DVBC_SYMBOL_RATE_PROP_RATE_MASK) << Si2168B_DVBC_SYMBOL_RATE_PROP_RATE_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DVBC_SYMBOL_RATE_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DVBC_SYMBOL_RATE_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    return err;
-+}
-+
-+/*****************************************************************************************
-+ NAME: si2168b_set_dvbt_properties
-+  DESCRIPTION: Setup Si2168B DVBT properties configuration
-+  This function will download all the DVBT configuration properties.
-+  The function Si2168B_storeUserProperties should be called before the first call to this function.
-+  Parameter:  Pointer to Si2168B Context
-+  Returns:    I2C transaction error code, NO_Si2168B_ERROR if successful
-+  Programming Guide Reference:    DVBT setup flowchart
-+******************************************************************************************/
-+static int si2168b_set_dvbt_properties(si2168b_context *ctx)
-+{
-+    const u8  dvbt_adc_crest_factor_crest_factor = 130; /* (default   130) */
-+    const u16 dvbt_afc_range_range_khz           = 550; /* (default   550) */
-+    const u8  dvbt_hierarchy_stream              = Si2168B_DVBT_HIERARCHY_PROP_STREAM_HP; /* (default 'HP') */
-+
-+	u8  ret;
-+	u8  err = NO_Si2168B_ERROR;
-+	u16 data;
-+
-+	SiTRACE("si2168b_set_dvbt_properties\n");
-+
-+    data = (dvbt_adc_crest_factor_crest_factor & Si2168B_DVBT_ADC_CREST_FACTOR_PROP_CREST_FACTOR_MASK) << Si2168B_DVBT_ADC_CREST_FACTOR_PROP_CREST_FACTOR_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DVBT_ADC_CREST_FACTOR_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DVBT_ADC_CREST_FACTOR_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dvbt_afc_range_range_khz & Si2168B_DVBT_AFC_RANGE_PROP_RANGE_KHZ_MASK) << Si2168B_DVBT_AFC_RANGE_PROP_RANGE_KHZ_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DVBT_AFC_RANGE_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DVBT_AFC_RANGE_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dvbt_hierarchy_stream & Si2168B_DVBT_HIERARCHY_PROP_STREAM_MASK) << Si2168B_DVBT_HIERARCHY_PROP_STREAM_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_DVBT_HIERARCHY_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DVBT_HIERARCHY_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+	return err;
-+}
-+
-+/*****************************************************************************************
-+ NAME: si2168b_set_dvbt2_properties
-+  DESCRIPTION: Setup Si2168B DVBT2 properties configuration
-+  This function will download all the DVBT2 configuration properties.
-+  The function Si2168B_storeUserProperties should be called before the first call to this function.
-+  Parameter:  Pointer to Si2168B Context
-+  Returns:    I2C transaction error code, NO_Si2168B_ERROR if successful
-+  Programming Guide Reference:    DVBT2 setup flowchart
-+******************************************************************************************/
-+static int si2168b_set_dvbt2_properties(si2168b_context *ctx)
-+{
-+    const u8  dvbt2_adc_crest_factor_crest_factor = 130; /* (default   130) */
-+    const u16 dvbt2_afc_range_range_khz           = 550; /* (default   550) */
-+    const u8  dvbt2_fef_tuner_tuner_delay         = 1; /* (default     1) */
-+    const u8  dvbt2_fef_tuner_tuner_freeze_time   = 1; /* (default     1) */
-+    const u8  dvbt2_fef_tuner_tuner_unfreeze_time = 1; /* (default     1) */
-+    const u8  dvbt2_mode_lock_mode                = Si2168B_DVBT2_MODE_PROP_LOCK_MODE_ANY; /* (default 'ANY') */
-+
-+	u8  ret;
-+	u8  err = NO_Si2168B_ERROR;
-+	u16 data;
-+
-+    SiTRACE("si2168b_set_dvbt2_properties\n");
-+
-+    data = (dvbt2_adc_crest_factor_crest_factor & Si2168B_DVBT2_ADC_CREST_FACTOR_PROP_CREST_FACTOR_MASK) << Si2168B_DVBT2_ADC_CREST_FACTOR_PROP_CREST_FACTOR_LSB ;
-+    ret = si2168b_set_property(ctx, Si2168B_DVBT2_ADC_CREST_FACTOR_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DVBT2_ADC_CREST_FACTOR_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dvbt2_afc_range_range_khz & Si2168B_DVBT2_AFC_RANGE_PROP_RANGE_KHZ_MASK) << Si2168B_DVBT2_AFC_RANGE_PROP_RANGE_KHZ_LSB ;
-+    ret = si2168b_set_property(ctx, Si2168B_DVBT2_AFC_RANGE_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DVBT2_AFC_RANGE_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dvbt2_fef_tuner_tuner_delay         & Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_DELAY_MASK        ) << Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_DELAY_LSB  |
-+            (dvbt2_fef_tuner_tuner_freeze_time   & Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_FREEZE_TIME_MASK  ) << Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_FREEZE_TIME_LSB  |
-+            (dvbt2_fef_tuner_tuner_unfreeze_time & Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_UNFREEZE_TIME_MASK) << Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_UNFREEZE_TIME_LSB ;
-+    ret = si2168b_set_property(ctx, Si2168B_DVBT2_FEF_TUNER_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DVBT2_FEF_TUNER_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (dvbt2_mode_lock_mode & Si2168B_DVBT2_MODE_PROP_LOCK_MODE_MASK) << Si2168B_DVBT2_MODE_PROP_LOCK_MODE_LSB ;
-+    ret = si2168b_set_property(ctx, Si2168B_DVBT2_MODE_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_DVBT2_MODE_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    return err;
-+}
-+
-+#ifdef __MCNS__
-+/*****************************************************************************************
-+ NAME: si2168b_set_mcns_properties
-+  DESCRIPTION: Setup Si2168B MCNS properties configuration
-+  This function will download all the MCNS configuration properties.
-+  The function Si2168B_storeUserProperties should be called before the first call to this function.
-+  Parameter:  Pointer to Si2168B Context
-+  Returns:    I2C transaction error code, NO_Si2168B_ERROR if successful
-+  Programming Guide Reference:    MCNS setup flowchart
-+******************************************************************************************/
-+static int si2168b_set_mcns_properties(si2168b_context *ctx)
-+{
-+#ifdef __MCNS__
-+#ifdef    Si2168B_MCNS_ADC_CREST_FACTOR_PROP
-+	mcns_adc_crest_factor_crest_factor                               =   112; /* (default   112) */
-+#endif /* Si2168B_MCNS_ADC_CREST_FACTOR_PROP */
-+
-+#ifdef    Si2168B_MCNS_AFC_RANGE_PROP
-+	mcns_afc_range_range_khz                                         =   100; /* (default   100) */
-+#endif /* Si2168B_MCNS_AFC_RANGE_PROP */
-+
-+#ifdef    Si2168B_MCNS_CONSTELLATION_PROP
-+	mcns_constellation_constellation                                 = Si2168B_MCNS_CONSTELLATION_PROP_CONSTELLATION_AUTO ; /* (default 'AUTO') */
-+#endif /* Si2168B_MCNS_CONSTELLATION_PROP */
-+
-+#ifdef    Si2168B_MCNS_SYMBOL_RATE_PROP
-+	mcns_symbol_rate_rate                                            =  6900; /* (default  6900) */
-+#endif /* Si2168B_MCNS_SYMBOL_RATE_PROP */
-+#endif /* __MCNS__ */
-+
-+	u8 ret = NO_Si2168B_ERROR;
-+
-+	SiTRACE("si2168b_set_mcns_properties\n");
-+#ifdef    Si2168B_MCNS_ADC_CREST_FACTOR_PROP
-+	ret = si2168b_set_property2(ctx, Si2168B_MCNS_ADC_CREST_FACTOR_PROP_CODE);
-+	if (ret != NO_Si2168B_ERROR) {
-+		return ERROR_Si2168B_SENDING_COMMAND;
-+	}
-+#endif /* Si2168B_MCNS_ADC_CREST_FACTOR_PROP */
-+#ifdef    Si2168B_MCNS_AFC_RANGE_PROP
-+	ret = si2168b_set_property2(ctx, Si2168B_MCNS_AFC_RANGE_PROP_CODE);
-+	if (ret != NO_Si2168B_ERROR) {
-+		return ERROR_Si2168B_SENDING_COMMAND;
-+	}
-+#endif /* Si2168B_MCNS_AFC_RANGE_PROP */
-+#ifdef    Si2168B_MCNS_CONSTELLATION_PROP
-+	ret = si2168b_set_property2(ctx, Si2168B_MCNS_CONSTELLATION_PROP_CODE);
-+	if (ret != NO_Si2168B_ERROR) {
-+		return ERROR_Si2168B_SENDING_COMMAND;
-+	}
-+#endif /* Si2168B_MCNS_CONSTELLATION_PROP */
-+#ifdef    Si2168B_MCNS_SYMBOL_RATE_PROP
-+	ret = si2168b_set_property2(ctx, Si2168B_MCNS_SYMBOL_RATE_PROP_CODE);
-+	if (ret != NO_Si2168B_ERROR) {
-+		return ERROR_Si2168B_SENDING_COMMAND;
-+	}
-+#endif /* Si2168B_MCNS_SYMBOL_RATE_PROP */
-+	return NO_Si2168B_ERROR;
-+}
-+#endif /* __MCNS__ */
-+
-+/*****************************************************************************************
-+ NAME: si2168b_set_scan_properties
-+  DESCRIPTION: Setup Si2168B SCAN properties configuration
-+  This function will download all the SCAN configuration properties.
-+  The function Si2168B_storeUserProperties should be called before the first call to this function.
-+  Parameter:  Pointer to Si2168B Context
-+  Returns:    I2C transaction error code, NO_Si2168B_ERROR if successful
-+  Programming Guide Reference:    SCAN setup flowchart
-+******************************************************************************************/
-+static int si2168b_set_scan_properties(si2168b_context *ctx)
-+{
-+	const u16 scan_fmax_scan_fmax                   = 0; /* (default     0) */
-+    const u16 scan_fmin_scan_fmin                   = 0; /* (default     0) */
-+    const u8  scan_ien_buzien                       = Si2168B_SCAN_IEN_PROP_BUZIEN_DISABLE; /* (default 'DISABLE') */
-+    const u8  scan_ien_reqien                       = Si2168B_SCAN_IEN_PROP_REQIEN_DISABLE; /* (default 'DISABLE') */
-+    const u8  scan_int_sense_buznegen               = Si2168B_SCAN_INT_SENSE_PROP_BUZNEGEN_ENABLE; /* (default 'ENABLE') */
-+    const u8  scan_int_sense_reqnegen               = Si2168B_SCAN_INT_SENSE_PROP_REQNEGEN_DISABLE; /* (default 'DISABLE') */
-+    const u8  scan_int_sense_buzposen               = Si2168B_SCAN_INT_SENSE_PROP_BUZPOSEN_DISABLE; /* (default 'DISABLE') */
-+    const u8  scan_int_sense_reqposen               = Si2168B_SCAN_INT_SENSE_PROP_REQPOSEN_ENABLE; /* (default 'ENABLE') */
-+	const u16 scan_symb_rate_max_scan_symb_rate_max = 0; /* (default     0) */
-+    const u16 scan_symb_rate_min_scan_symb_rate_min = 0; /* (default     0) */
-+    /* const u8  scan_ter_config_mode                  = Si2168B_SCAN_TER_CONFIG_PROP_MODE_MAPPING_SCAN; */ /* (default 'BLIND_SCAN') */
-+    const u8  scan_ter_config_mode                  = Si2168B_SCAN_TER_CONFIG_PROP_MODE_BLIND_SCAN; /* (default 'BLIND_SCAN') */
-+    const u8  scan_ter_config_analog_bw             = Si2168B_SCAN_TER_CONFIG_PROP_ANALOG_BW_8MHZ; /* (default '8MHZ') */
-+    const u8  scan_ter_config_search_analog         = Si2168B_SCAN_TER_CONFIG_PROP_SEARCH_ANALOG_DISABLE; /* (default 'DISABLE') */
-+    const u8  scan_ter_config_scan_debug            = 0;
-+
-+#ifdef Si2168B_SCAN_SAT_CONFIG_PROP
-+	scan_sat_config_analog_detect                                    = Si2168B_SCAN_SAT_CONFIG_PROP_ANALOG_DETECT_DISABLED ; /* (default 'DISABLED') */
-+	scan_sat_config_reserved1                                        =     0; /* (default     0) */
-+	scan_sat_config_reserved2                                        =    12; /* (default    12) */
-+#endif /* Si2168B_SCAN_SAT_CONFIG_PROP */
-+#ifdef Si2168B_SCAN_SAT_UNICABLE_BW_PROP
-+	scan_sat_unicable_bw_scan_sat_unicable_bw                        =     0; /* (default     0) */
-+#endif /* Si2168B_SCAN_SAT_UNICABLE_BW_PROP */
-+#ifdef Si2168B_SCAN_SAT_UNICABLE_MIN_TUNE_STEP_PROP
-+	scan_sat_unicable_min_tune_step_scan_sat_unicable_min_tune_step  =    50; /* (default    50) */
-+#endif /* Si2168B_SCAN_SAT_UNICABLE_MIN_TUNE_STEP_PROP */
-+
-+	u8  ret;
-+	u8  err = NO_Si2168B_ERROR;
-+	u16 data;
-+
-+	SiTRACE("si2168b_set_scan_properties\n");
-+
-+    data = (scan_fmax_scan_fmax & Si2168B_SCAN_FMAX_PROP_SCAN_FMAX_MASK) << Si2168B_SCAN_FMAX_PROP_SCAN_FMAX_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_SCAN_FMAX_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_SCAN_FMAX_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (scan_fmin_scan_fmin & Si2168B_SCAN_FMIN_PROP_SCAN_FMIN_MASK) << Si2168B_SCAN_FMIN_PROP_SCAN_FMIN_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_SCAN_FMIN_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_SCAN_FMIN_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (scan_ien_buzien & Si2168B_SCAN_IEN_PROP_BUZIEN_MASK) << Si2168B_SCAN_IEN_PROP_BUZIEN_LSB |
-+           (scan_ien_reqien & Si2168B_SCAN_IEN_PROP_REQIEN_MASK) << Si2168B_SCAN_IEN_PROP_REQIEN_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_SCAN_IEN_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_SCAN_IEN_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (scan_int_sense_buznegen & Si2168B_SCAN_INT_SENSE_PROP_BUZNEGEN_MASK) << Si2168B_SCAN_INT_SENSE_PROP_BUZNEGEN_LSB |
-+           (scan_int_sense_reqnegen & Si2168B_SCAN_INT_SENSE_PROP_REQNEGEN_MASK) << Si2168B_SCAN_INT_SENSE_PROP_REQNEGEN_LSB |
-+           (scan_int_sense_buzposen & Si2168B_SCAN_INT_SENSE_PROP_BUZPOSEN_MASK) << Si2168B_SCAN_INT_SENSE_PROP_BUZPOSEN_LSB |
-+           (scan_int_sense_reqposen & Si2168B_SCAN_INT_SENSE_PROP_REQPOSEN_MASK) << Si2168B_SCAN_INT_SENSE_PROP_REQPOSEN_LSB;
-+    ret = si2168b_set_property(ctx, Si2168B_SCAN_INT_SENSE_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_SCAN_INT_SENSE_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (scan_symb_rate_max_scan_symb_rate_max & Si2168B_SCAN_SYMB_RATE_MAX_PROP_SCAN_SYMB_RATE_MAX_MASK) << Si2168B_SCAN_SYMB_RATE_MAX_PROP_SCAN_SYMB_RATE_MAX_LSB ;
-+    ret = si2168b_set_property(ctx, Si2168B_SCAN_SYMB_RATE_MAX_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_SCAN_SYMB_RATE_MAX_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (scan_symb_rate_min_scan_symb_rate_min & Si2168B_SCAN_SYMB_RATE_MIN_PROP_SCAN_SYMB_RATE_MIN_MASK) << Si2168B_SCAN_SYMB_RATE_MIN_PROP_SCAN_SYMB_RATE_MIN_LSB ;
-+    ret = si2168b_set_property(ctx, Si2168B_SCAN_SYMB_RATE_MIN_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_SCAN_SYMB_RATE_MIN_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    data = (scan_ter_config_mode          & Si2168B_SCAN_TER_CONFIG_PROP_MODE_MASK         ) << Si2168B_SCAN_TER_CONFIG_PROP_MODE_LSB  |
-+           (scan_ter_config_analog_bw     & Si2168B_SCAN_TER_CONFIG_PROP_ANALOG_BW_MASK    ) << Si2168B_SCAN_TER_CONFIG_PROP_ANALOG_BW_LSB  |
-+           (scan_ter_config_search_analog & Si2168B_SCAN_TER_CONFIG_PROP_SEARCH_ANALOG_MASK) << Si2168B_SCAN_TER_CONFIG_PROP_SEARCH_ANALOG_LSB |
-+           (scan_ter_config_scan_debug    & Si2168B_SCAN_TER_CONFIG_PROP_SCAN_DEBUG_MASK   ) << Si2168B_SCAN_TER_CONFIG_PROP_SCAN_DEBUG_LSB ;
-+    ret = si2168b_set_property(ctx, Si2168B_SCAN_TER_CONFIG_PROP, data);
-+    if (ret != NO_Si2168B_ERROR) {
-+		siprintk("%s(): setting property Si2168B_SCAN_TER_CONFIG_PROP failed.\n", __func__);
-+		err = ERROR_Si2168B_SENDING_COMMAND;
-+    }
-+
-+    return err;
-+}
-+
-+static int si2168b_set_all_properties(si2168b_context *ctx)
-+{
-+	si2168b_set_common_properties(ctx);
-+	si2168b_set_dd_properties(ctx);
-+	si2168b_set_dvbc_properties(ctx);
-+	si2168b_set_dvbt_properties(ctx);
-+	si2168b_set_dvbt2_properties(ctx);
-+#ifdef __MCNS__
-+	si2168b_set_mcns_properties(ctx);
-+#endif /* __MCNS__ */
-+	si2168b_set_scan_properties(ctx);
-+	return 0;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: si2168b_configure
-+  DESCRIPTION: Setup TER and SAT AGCs, Common Properties startup
-+  Parameter:  Pointer to Si2168B Context
-+  Returns:    I2C transaction error code, NO_Si2168B_ERROR if successful
-+************************************************************************************************************************/
-+static int si2168b_configure(si2168b_context *ctx)
-+{
-+	const u8 dd_ext_agc_ter_agc_1_mode = Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_NO_CHANGE;
-+	const u8 dd_ext_agc_ter_agc_1_inv  = Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_INV_NOT_INVERTED;
-+	const u8 dd_ext_agc_ter_agc_2_mode = Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MODE_NO_CHANGE;
-+	const u8 dd_ext_agc_ter_agc_2_inv  = Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_INV_NOT_INVERTED;
-+
-+	Si2168B_DD_MP_DEFAULTS_CMD_REPLY_struct dd_mp_defaults;
-+	Si2168B_DD_EXT_AGC_TER_CMD_REPLY_struct dd_ext_agc_ter;
-+	Si2168B_CONFIG_PINS_CMD_REPLY_struct config_pins;
-+	Si2168B_DVBT2_FEF_CMD_REPLY_struct dvbt2_fef;
-+	Si2168B_GET_REV_CMD_REPLY_struct get_rev;
-+	u8 dd_mp_defaults_mp_a_mode;
-+	u8 dd_mp_defaults_mp_b_mode;
-+	u8 dd_mp_defaults_mp_c_mode;
-+	u8 dd_mp_defaults_mp_d_mode;
-+	u8 dd_ext_agc_ter_agc_1_kloop;
-+	u8 dd_ext_agc_ter_agc_2_kloop;
-+	u8 dd_ext_agc_ter_agc_1_min;
-+	u8 dd_ext_agc_ter_agc_2_min;
-+	u8 config_pins_gpio0_mode;
-+	u8 config_pins_gpio0_read;
-+	u8 config_pins_gpio1_mode;
-+	u8 config_pins_gpio1_read;
-+	u8 dvbt2_fef_tuner_flag     = Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_NOT_USED;
-+	u8 dvbt2_fef_tuner_flag_inv = Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_INV_FEF_HIGH;
-+	u8 fef_pin   = 0;
-+	u8 fef_level = 0;
-+
-+	int return_code = NO_Si2168B_ERROR;
-+
-+	SiTRACE("media %d\n", ctx->media);
-+
-+	return_code = si2168b_get_revision(ctx, &get_rev);
-+	if (return_code != NO_Si2168B_ERROR) {
-+		SiTRACE ("si2168b_get_revision error 0x%02x: %s\n", return_code, si2168b_error_text(return_code) );
-+		return return_code;
-+	}
-+
-+	/* AGC settings when not used */
-+	if ( get_rev.mcm_die == Si2168B_GET_REV_RESPONSE_MCM_DIE_DIE_A) {
-+		dd_mp_defaults_mp_a_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_DISABLE;
-+		dd_mp_defaults_mp_b_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_NO_CHANGE;
-+		dd_mp_defaults_mp_c_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_DISABLE;
-+		dd_mp_defaults_mp_d_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_NO_CHANGE;
-+	} else if ( get_rev.mcm_die == Si2168B_GET_REV_RESPONSE_MCM_DIE_DIE_B) {
-+		dd_mp_defaults_mp_a_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_NO_CHANGE;
-+		dd_mp_defaults_mp_b_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_DISABLE;
-+		dd_mp_defaults_mp_c_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_NO_CHANGE;
-+		dd_mp_defaults_mp_d_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_DISABLE;
-+	} else {
-+		dd_mp_defaults_mp_a_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_DISABLE;
-+		dd_mp_defaults_mp_b_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_DISABLE;
-+		dd_mp_defaults_mp_c_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_DISABLE;
-+		dd_mp_defaults_mp_d_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_DISABLE;
-+	}
-+
-+	/************************************************************************************************************************
-+	  Si2168B_L2_TER_FEF_CONFIG function
-+	  Use:        TER tuner FEF pin selection function
-+	              Used to select the FEF pin connected to the terrestrial tuner
-+	  Parameter:  *front_end, the front-end handle
-+	  Parameter:  fef_mode, a flag controlling the FEF mode between SLOW_NORMAL_AGC(0), FREEZE_PIN(1)' and SLOW_INITIAL_AGC(2)
-+	  Parameter:  fef_pin: where the FEF signal comes from.
-+	              possible modes:
-+	                0x0: Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_NOT_USED
-+	                0xA: Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_A
-+	                0xB: Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_B
-+	                0xC: Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_C
-+	                0xD: Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_D
-+	  Parameter:  fef_level, a flag controlling the FEF signal level when active between 'low'(0) and 'high'(1)
-+	  Returns:    1
-+	************************************************************************************************************************/
-+
-+	switch (ctx->fef_mode) {
-+	default:
-+	case Si2168B_FEF_MODE_SLOW_NORMAL_AGC:
-+	case Si2168B_FEF_MODE_SLOW_INITIAL_AGC:
-+		fef_pin   = 0x0;
-+		fef_level = 0;
-+		break;
-+	case Si2168B_FEF_MODE_FREEZE_PIN:
-+		fef_pin   = ctx->fef_pin;
-+		fef_level = ctx->fef_level;
-+		break;
-+	}
-+
-+	switch (fef_pin) {
-+	default:
-+	case 0x0: { dvbt2_fef_tuner_flag  = Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_NOT_USED; break; }
-+	case 0xA: { dvbt2_fef_tuner_flag  = Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_A    ; break; }
-+	case 0xB: { dvbt2_fef_tuner_flag  = Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_B    ; break; }
-+	case 0xC: { dvbt2_fef_tuner_flag  = Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_C    ; break; }
-+	case 0xD: { dvbt2_fef_tuner_flag  = Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_D    ; break; }
-+	}
-+
-+	if (fef_level == 0) {
-+		dvbt2_fef_tuner_flag_inv = Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_INV_FEF_LOW ;
-+	} else {
-+		dvbt2_fef_tuner_flag_inv = Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_INV_FEF_HIGH;
-+	}
-+
-+	/*  For DVB_T2, if the TER tuner has a FEF freeze input pin, drive this pin to 0 or 1 when NOT in T2 */
-+	/* if FEF is active high, set the pin to 0 when NOT in T2 */
-+	/* if FEF is active low,  set the pin to 1 when NOT in T2 */
-+	if (ctx->fef_mode == Si2168B_FEF_MODE_FREEZE_PIN) {
-+		switch (fef_pin) {
-+		case Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_MP_A: {
-+			dvbt2_fef_tuner_flag = Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_A;
-+			if (fef_level == 1) {
-+				dd_mp_defaults_mp_a_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_DRIVE_0;
-+			} else {
-+				dd_mp_defaults_mp_a_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_DRIVE_1;
-+			}
-+			break;
-+		}
-+		case Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_MP_B: {
-+			dvbt2_fef_tuner_flag = Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_B;
-+			if (fef_level == 1) {
-+				dd_mp_defaults_mp_b_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_DRIVE_0;
-+			} else {
-+				dd_mp_defaults_mp_b_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_DRIVE_1;
-+			}
-+			break;
-+		}
-+		case Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_MP_C: {
-+			dvbt2_fef_tuner_flag = Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_C;
-+			if (fef_level == 1) {
-+				dd_mp_defaults_mp_c_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_DRIVE_0;
-+			} else {
-+				dd_mp_defaults_mp_c_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_DRIVE_1;
-+			}
-+			break;
-+		}
-+		case Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_MP_D: {
-+			dvbt2_fef_tuner_flag = Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_D;
-+			if (fef_level == 1) {
-+				dd_mp_defaults_mp_d_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_DRIVE_0;
-+			} else {
-+				dd_mp_defaults_mp_d_mode = Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_DRIVE_1;
-+			}
-+			break;
-+		}
-+		default: break;
-+		}
-+	}
-+	/* Si2168B_L1_SendCommand2(ctx, Si2168B_DVBT2_FEF_CMD_CODE); */
-+	si2168b_dvbt2_fef(ctx, dvbt2_fef_tuner_flag, dvbt2_fef_tuner_flag_inv, &dvbt2_fef);
-+	/* Si2168B_L1_SendCommand2(ctx, Si2168B_DD_MP_DEFAULTS_CMD_CODE); */
-+	si2168b_dd_mp_defaults(ctx, dd_mp_defaults_mp_a_mode, dd_mp_defaults_mp_b_mode, dd_mp_defaults_mp_c_mode, dd_mp_defaults_mp_d_mode, &dd_mp_defaults);
-+
-+	if (ctx->media == Si2168B_TERRESTRIAL) {
-+		/* TER AGC pins and inversion are previously selected using Si2168B_L2_TER_AGC */
-+		dd_ext_agc_ter_agc_1_kloop = Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_KLOOP_MIN;
-+		dd_ext_agc_ter_agc_1_min   = Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MIN_MIN;
-+
-+		dd_ext_agc_ter_agc_2_kloop = 18;
-+		dd_ext_agc_ter_agc_2_min   = Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MIN_MIN;
-+		/* Si2168B_L1_SendCommand2(ctx, Si2168B_DD_EXT_AGC_TER_CMD_CODE); */
-+		si2168b_dd_ext_agc_ter(ctx,
-+				dd_ext_agc_ter_agc_1_mode,
-+				dd_ext_agc_ter_agc_1_inv,
-+				dd_ext_agc_ter_agc_2_mode,
-+				dd_ext_agc_ter_agc_2_inv,
-+				dd_ext_agc_ter_agc_1_kloop,
-+				dd_ext_agc_ter_agc_2_kloop,
-+				dd_ext_agc_ter_agc_1_min,
-+				dd_ext_agc_ter_agc_2_min,
-+				&dd_ext_agc_ter);
-+	}
-+
-+	/* LEDS MANAGEMENT */
-+	/* set hardware lock on LED */
-+	if ( get_rev.mcm_die == Si2168B_GET_REV_RESPONSE_MCM_DIE_DIE_A) {
-+		config_pins_gpio0_mode = Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_NO_CHANGE;
-+		config_pins_gpio0_read = Si2168B_CONFIG_PINS_CMD_GPIO0_READ_DO_NOT_READ;
-+		config_pins_gpio1_mode = Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_HW_LOCK;
-+		config_pins_gpio1_read = Si2168B_CONFIG_PINS_CMD_GPIO1_READ_DO_NOT_READ;
-+	} else if ( get_rev.mcm_die == Si2168B_GET_REV_RESPONSE_MCM_DIE_DIE_B) {
-+		config_pins_gpio0_mode = Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_HW_LOCK;
-+		config_pins_gpio0_read = Si2168B_CONFIG_PINS_CMD_GPIO0_READ_DO_NOT_READ;
-+		config_pins_gpio1_mode = Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_NO_CHANGE;
-+		config_pins_gpio1_read = Si2168B_CONFIG_PINS_CMD_GPIO1_READ_DO_NOT_READ;
-+	} else {
-+		config_pins_gpio0_mode = Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_HW_LOCK;
-+		config_pins_gpio0_read = Si2168B_CONFIG_PINS_CMD_GPIO0_READ_DO_NOT_READ;
-+		config_pins_gpio1_mode = Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_TS_ERR;
-+		config_pins_gpio1_read = Si2168B_CONFIG_PINS_CMD_GPIO1_READ_DO_NOT_READ;
-+	}
-+	/* Si2168B_L1_SendCommand2(ctx, Si2168B_CONFIG_PINS_CMD_CODE); */
-+	si2168b_config_pins(ctx, config_pins_gpio0_mode, config_pins_gpio0_read, config_pins_gpio1_mode, config_pins_gpio1_read, &config_pins);
-+
-+	/* Download properties different from 'default' */
-+	si2168b_set_all_properties(ctx);
-+
-+#ifdef    USB_Capability
-+	if ( ctx->rsp->get_rev.mcm_die == Si2168B_GET_REV_RESPONSE_MCM_DIE_SINGLE) {
-+		/* Setting GPIF clock to not_inverted to allow TS over USB transfer */
-+		Si2168B_L1_DD_SET_REG(ctx, 0 , 35, 1, 0);
-+	}
-+#endif /* USB_Capability */
-+
-+	return return_code;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: si2168b_first_init
-+  DESCRIPTION:Reset and Initialize Si2168B
-+  Parameter:  Si2168B Context (I2C address)
-+  Returns:    I2C transaction error code, NO_Si2168B_ERROR if successful
-+************************************************************************************************************************/
-+static int si2168b_first_init(si2168b_context *ctx)
-+{
-+    int return_code;
-+    SiTRACE("si2168b_first_init() starting...\n");
-+
-+    if ((return_code = si2168b_power_up_with_patch(ctx)) != NO_Si2168B_ERROR) {   /* PowerUp into bootloader */
-+        SiTRACE ("si2168b_power_up_with_patch error 0x%02x: %s\n", return_code, si2168b_error_text(return_code) );
-+        return return_code;
-+    }
-+    /* At this point, FW is loaded and started.  */
-+    si2168b_configure(ctx);
-+    SiTRACE("si2168b_first_init() complete...\n");
-+    return NO_Si2168B_ERROR;
-+}
-+
-+/************************************************************************************************************************
-+  si2168b_ter_fef_setup function
-+  Use:        TER tuner LPF setting function
-+              Used to configure the FEF mode in the terrestrial tuner
-+  Comments:   If the tuner is connected via the demodulator's I2C switch, enabling/disabling the i2c_passthru is required before/after tuning.
-+  Behavior:   This function closes the Si2168B's I2C switch then sets the TER FEF mode and finally reopens the I2C switch
-+  Parameter:  *front_end, the front-end handle
-+  Parameter:  fef, a flag controlling the selection between FEF 'off'(0) and FEF 'on'(1)
-+  Returns:    1
-+************************************************************************************************************************/
-+static int si2168b_ter_fef_setup(Si2168B_L2_Context *front_end, int fef)
-+{
-+	SiTRACE("si2168b_ter_fef_setup %d\n",fef);
-+
-+#ifdef L1_RF_TER_TUNER_FEF_MODE_FREEZE_PIN_SETUP
-+	if (front_end->demod->fef_mode == Si2168B_FEF_MODE_FREEZE_PIN) {
-+		SiTRACE("FEF mode Si2168B_FEF_MODE_FREEZE_PIN\n");
-+		/* setup now in tuner module */
-+	}
-+#endif /* L1_RF_TER_TUNER_FEF_MODE_FREEZE_PIN_SETUP */
-+
-+#ifdef L1_RF_TER_TUNER_FEF_MODE_SLOW_INITIAL_AGC_SETUP
-+	if (front_end->demod->fef_mode == Si2168B_FEF_MODE_SLOW_INITIAL_AGC) {
-+		SiTRACE("FEF mode Si2168B_FEF_MODE_SLOW_INITIAL_AGC (AGC slowed down after tuning)\n");
-+		/* setup now in tuner module */
-+	}
-+#endif /* L1_RF_TER_TUNER_FEF_MODE_SLOW_INITIAL_AGC_SETUP */
-+
-+#ifdef L1_RF_TER_TUNER_FEF_MODE_SLOW_NORMAL_AGC_SETUP
-+	if (front_end->demod->fef_mode == Si2168B_FEF_MODE_SLOW_NORMAL_AGC) {
-+		SiTRACE("FEF mode Si2168B_FEF_MODE_SLOW_NORMAL_AGC: AGC slowed down\n");
-+		/* setup now in tuner module */
-+	}
-+#endif /* L1_RF_TER_TUNER_FEF_MODE_SLOW_NORMAL_AGC */
-+
-+	if ( front_end->tuner_indirect_i2c_connection ) {  /* INDIRECT_I2C_CONNECTION? */
-+		front_end->f_TER_tuner_enable(front_end->callback);
-+	} else {
-+		si2168b_tuner_i2c_enable(front_end);
-+	}
-+
-+	si2168b_ter_fef(front_end, fef);
-+
-+	if ( front_end->tuner_indirect_i2c_connection ) {  /* INDIRECT_I2C_CONNECTION? */
-+		front_end->f_TER_tuner_disable(front_end->callback);
-+	} else {
-+		si2168b_tuner_i2c_disable(front_end);
-+	}
-+
-+	SiTRACE("si2168b_ter_fef_setup done\n");
-+	return 1;
-+}
-+
-+/************************************************************************************************************************
-+  si2168b_switch_to_standard function
-+  Use:      Standard switching function selection
-+            Used to switch nicely to the wanted standard, taking into account the previous state
-+  Parameter: new_standard the wanted standard to switch to
-+  Behavior: This function positions a set of flags to easily decide what needs to be done to
-+              switch between standards.
-+************************************************************************************************************************/
-+static int si2168b_switch_to_standard(struct dvb_frontend *fe, u8 new_standard, u8 force_full_init)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	Si2168B_L2_Context *front_end = priv->si_front_end;
-+
-+	/* previous state flags */
-+	int dtv_demod_already_used = 0;
-+	int i2c_connected          = 0;
-+	int ter_tuner_already_used = 0;
-+	int ter_clock_already_used = 0;
-+	/* new state flags      */
-+	int dtv_demod_needed       = 0;
-+	int ter_tuner_needed       = 0;
-+	int ter_clock_needed       = 0;
-+	int dtv_demod_sleep_request= 0;
-+	int res;
-+
-+	u8  dd_mode_bw = 8;
-+	u8  dd_mode_modulation  = Si2168B_DD_MODE_PROP_MODULATION_DVBT;
-+	u8  dd_mode_auto_detect = Si2168B_DD_MODE_PROP_AUTO_DETECT_NONE;
-+	u8  dd_mode_invert_spectrum = Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_NORMAL;
-+	u16 data;
-+
-+	SiTRACE("Si2168B_switch_to_standard %d starting... (full_init=%d)\n", new_standard, force_full_init);
-+	SiTRACE("starting with Si2168B_init_done %d, first_init_done     %d\n", front_end->Si2168B_init_done, front_end->first_init_done);
-+	SiTRACE("TER flags:    TER_init_done    %d\n", front_end->TER_init_done);
-+
-+	/* In this function is called for the first time, force a full init */
-+	if (front_end->first_init_done == 0) {
-+		force_full_init = 1;
-+	}
-+	/* ------------------------------------------------------------ */
-+	/* Set Previous Flags                                           */
-+	/* Setting flags representing the previous state                */
-+	/* NB: Any value not matching a known standard will init as ATV */
-+	/* Logic applied:                                               */
-+	/*  dtv demod was used for TERRESTRIAL and SATELLITE reception  */
-+	/*  ter tuner was used for TERRESTRIAL reception                */
-+	/*   and for SATELLITE reception if it is the SAT clock source  */
-+	/*  sat tuner was used for SATELLITE reception                  */
-+	/*   and for TERRESTRIAL reception if it is the TER clock source*/
-+	/* ------------------------------------------------------------ */
-+	switch (front_end->previous_standard) {
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT:
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT2:
-+#ifdef __MCNS__
-+	case Si2168B_DD_MODE_PROP_MODULATION_MCNS:
-+#endif /* __MCNS__ */
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBC: {
-+		dtv_demod_already_used = 1;
-+		ter_tuner_already_used = 1;
-+		if ( front_end->demod->tuner_ter_clock_source == Si2168B_TER_Tuner_clock) {
-+			ter_clock_already_used = 1;
-+		}
-+		break;
-+	}
-+	case Si2168B_DD_MODE_PROP_MODULATION_ANALOG: {
-+		ter_tuner_already_used = 1;
-+		break;
-+	}
-+	default : /* SLEEP */   {
-+		siprintk("%s(): unknown previous standard %d.\n", __func__, front_end->previous_standard);
-+		ter_tuner_already_used = 0;
-+		break;
-+	}
-+	}
-+	/* ------------------------------------------------------------ */
-+	/* Set Needed Flags                                             */
-+	/* Setting flags representing the new state                     */
-+	/* Logic applied:                                               */
-+	/*  dtv demod is needed for TERRESTRIAL and SATELLITE reception */
-+	/*  ter tuner is needed for TERRESTRIAL reception               */
-+	/*   and for SATELLITE reception if it is the SAT clock source  */
-+	/*  sat tuner is needed for SATELLITE reception                 */
-+	/*   and for TERRESTRIAL reception if it is the TER clock source*/
-+	/* ------------------------------------------------------------ */
-+	switch (new_standard) {
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT:
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBT2:
-+#ifdef __MCNS__
-+	case Si2168B_DD_MODE_PROP_MODULATION_MCNS:
-+#endif /* __MCNS__ */
-+	case Si2168B_DD_MODE_PROP_MODULATION_DVBC: {
-+		dtv_demod_needed = 1;
-+		ter_tuner_needed = 1;
-+		if ( front_end->demod->tuner_ter_clock_source == Si2168B_TER_Tuner_clock) {
-+			ter_clock_needed = 1;
-+		}
-+		break;
-+	}
-+	case Si2168B_DD_MODE_PROP_MODULATION_ANALOG: {
-+		ter_tuner_needed = 1;
-+		break;
-+	}
-+	default : /* SLEEP */   {
-+		siprintk("%s(): unknown modulation %d submitted. Entering SLEEP mode now...\n", __func__, new_standard);
-+		ter_tuner_needed = 0;
-+		break;
-+	}
-+	}
-+	/* ------------------------------------------------------------ */
-+	/* For multiple front-ends: override clock_needed flags         */
-+	/*  to avoid switching shared clocks                            */
-+	/* ------------------------------------------------------------ */
-+	/* For multiple front-ends: overrride clock_needed flags to avoid switching shared clocks */
-+	if (ter_clock_needed == 0) {
-+		if ( front_end->demod->tuner_ter_clock_control == Si2168B_CLOCK_ALWAYS_ON ) {
-+			SiTRACE("forcing ter_clock_needed = 1\n");
-+			ter_clock_needed = 1;
-+		}
-+	} else {
-+		if ( front_end->demod->tuner_ter_clock_control == Si2168B_CLOCK_ALWAYS_OFF) {
-+			SiTRACE("forcing ter_clock_needed = 0\n");
-+			ter_clock_needed = 0;
-+		}
-+	}
-+
-+	/* ------------------------------------------------------------ */
-+	/* if 'force' flag is set, set flags to trigger a full init     */
-+	/* This can be used to re-init the NIM after a power cycle      */
-+	/*  or a HW reset                                               */
-+	/* ------------------------------------------------------------ */
-+	if (force_full_init) {
-+		SiTRACE("Forcing full init\n");
-+		/* set 'init_done' flags to force full init     */
-+		front_end->first_init_done     = 0;
-+		front_end->Si2168B_init_done    = 0;
-+		front_end->TER_init_done       = 0;
-+		/* set 'already used' flags to force full init  */
-+		ter_tuner_already_used = 0;
-+		dtv_demod_already_used = 0;
-+	}
-+
-+	/* ------------------------------------------------------------ */
-+	/* Request demodulator sleep if its clock will be stopped       */
-+	/* ------------------------------------------------------------ */
-+	if ((ter_tuner_already_used == 1) & (ter_tuner_needed == 0) ) {
-+		SiTRACE("TER tuner 1->0 \n");
-+	}
-+	if ((ter_tuner_already_used == 0) & (ter_tuner_needed == 1) ) {
-+		SiTRACE("TER tuner 0->1 \n");
-+	}
-+	if ((ter_clock_already_used == 1) & (ter_clock_needed == 0) ) {
-+		SiTRACE("TER clock 1->0 \n");
-+		dtv_demod_sleep_request = 1;
-+	}
-+	if ((ter_clock_already_used == 0) & (ter_clock_needed == 1) ) {
-+		SiTRACE("TER clock 0->1 \n");
-+		dtv_demod_sleep_request = 1;
-+	}
-+	/* ------------------------------------------------------------ */
-+	/* Request demodulator sleep if transition from '1' to '0'      */
-+	/* ------------------------------------------------------------ */
-+	if ((dtv_demod_already_used == 1) & (dtv_demod_needed == 0) ) {
-+		dtv_demod_sleep_request = 1;
-+	}
-+	SiTRACE("dtv_demod_already_used %d, dtv_demod_needed %d, dtv_demod_sleep_request %d\n", dtv_demod_already_used , dtv_demod_needed, dtv_demod_sleep_request);
-+	/* ------------------------------------------------------------ */
-+	/* Sleep dtv demodulator if requested                           */
-+	/* ------------------------------------------------------------ */
-+	if (dtv_demod_sleep_request == 1) {
-+		SiTRACE("Sleep DTV demod\n");
-+		/* To avoid issues with the FEF pin when switching from T2 to ANALOG, set the demodulator for DVB-T/non auto detect reception before POWER_DOWN */
-+		if (new_standard == Si2168B_DD_MODE_PROP_MODULATION_ANALOG) {
-+			if ( ( (front_end->previous_standard == Si2168B_DD_MODE_PROP_MODULATION_DVBT  )
-+					& (front_end->demod->dd_mode_auto_detect == Si2168B_DD_MODE_PROP_AUTO_DETECT_AUTO_DVB_T_T2) )
-+					| (front_end->previous_standard == Si2168B_DD_MODE_PROP_MODULATION_DVBT2 ) ) {
-+				dd_mode_modulation  = Si2168B_DD_MODE_PROP_MODULATION_DVBT;
-+				dd_mode_auto_detect = Si2168B_DD_MODE_PROP_AUTO_DETECT_NONE;
-+			    data = (dd_mode_bw              & Si2168B_DD_MODE_PROP_BW_MASK             ) << Si2168B_DD_MODE_PROP_BW_LSB |
-+			           (dd_mode_modulation      & Si2168B_DD_MODE_PROP_MODULATION_MASK     ) << Si2168B_DD_MODE_PROP_MODULATION_LSB |
-+			           (dd_mode_invert_spectrum & Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_MASK) << Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_LSB |
-+			           (dd_mode_auto_detect     & Si2168B_DD_MODE_PROP_AUTO_DETECT_MASK    ) << Si2168B_DD_MODE_PROP_AUTO_DETECT_LSB;
-+				si2168b_set_property(front_end->demod, Si2168B_DD_MODE_PROP, data);
-+				si2168b_dd_restart(front_end->demod);
-+			}
-+		}
-+		si2168b_standby(front_end->demod);
-+	}
-+
-+	/* ------------------------------------------------------------ */
-+	/* Set media for new standard                                   */
-+	/* ------------------------------------------------------------ */
-+	front_end->demod->dd_mode_modulation = new_standard;
-+	front_end->demod->media = si2168b_media(front_end->demod);
-+
-+	/* ------------------------------------------------------------ */
-+	/* Allow i2c traffic to reach the tuners                        */
-+	/* ------------------------------------------------------------ */
-+	if ( front_end->tuner_indirect_i2c_connection ) { /* INDIRECT_I2C_CONNECTION? */
-+		/* Connection will be done later on, depending on TER/SAT */
-+	} else {
-+		SiTRACE("Connect tuners i2c\n");
-+		si2168b_tuner_i2c_enable(front_end);
-+		i2c_connected = 1;
-+	}
-+	/* ------------------------------------------------------------ */
-+	/* Sleep Ter Tuner                                              */
-+	/* Sleep terrestrial tuner  if transition from '1' to '0'       */
-+	/* ------------------------------------------------------------ */
-+	if ((ter_tuner_already_used == 1) & (ter_tuner_needed == 0) ) {
-+		if ( front_end->tuner_indirect_i2c_connection ) { /* INDIRECT_I2C_CONNECTION? */
-+			if (i2c_connected==0) {
-+				SiTRACE("-- I2C -- Connect TER tuner i2c to sleep it\n");
-+				front_end->f_TER_tuner_enable(front_end->callback);
-+				i2c_connected++;
-+			}
-+		}
-+		SiTRACE("Sleep terrestrial tuner\n");
-+		if (fe->ops.tuner_ops.sleep) {
-+			res = fe->ops.tuner_ops.sleep(fe);
-+			if (res) {
-+				SiTRACE("Terrestrial tuner sleep error!\n");
-+			}
-+		} else {
-+			SiTRACE("WARNING: sleep() not available\n");
-+		}
-+	}
-+
-+	/* ------------------------------------------------------------ */
-+	/* Wakeup Ter Tuner                                             */
-+	/* Wake up terrestrial tuner if transition from '0' to '1'      */
-+	/* ------------------------------------------------------------ */
-+	if ((ter_tuner_already_used == 0) & (ter_tuner_needed == 1)) {
-+		if ( front_end->tuner_indirect_i2c_connection ) { /* INDIRECT_I2C_CONNECTION? */
-+			if (i2c_connected==0) {
-+				SiTRACE("-- I2C -- Connect TER tuner i2c to init/wakeup it\n");
-+				front_end->f_TER_tuner_enable(front_end->callback);
-+				i2c_connected++;
-+			}
-+		}
-+		if (fe->ops.tuner_ops.init) {
-+			res = fe->ops.tuner_ops.init(fe);
-+			if (res) {
-+				SiTRACE("Terrestrial tuner init error!\n");
-+			}
-+		} else {
-+			SiTRACE("WARNING: init() not available\n");
-+		}
-+	}
-+
-+	if ((front_end->previous_standard != new_standard) & (dtv_demod_needed == 0) & (front_end->demod->media == Si2168B_TERRESTRIAL)) {
-+		if (front_end->demod->media == Si2168B_TERRESTRIAL) {
-+#ifdef    TER_TUNER_ATV_LO_INJECTION
-+			TER_TUNER_ATV_LO_INJECTION(front_end->tuner_ter);
-+#endif /* TER_TUNER_ATV_LO_INJECTION */
-+
-+		}
-+	}
-+	/* ------------------------------------------------------------ */
-+	/* Change Dtv Demod standard if required                        */
-+	/* ------------------------------------------------------------ */
-+	if ((front_end->previous_standard != new_standard) & (dtv_demod_needed == 1)) {
-+		SiTRACE("Store demod standard (%d)\n", new_standard);
-+		front_end->standard = new_standard;
-+		/* Set flag to trigger Si2168B init or re_init, to complete    */
-+		/*  the standard change                                       */
-+		dtv_demod_already_used = 0;
-+		if (front_end->demod->media == Si2168B_TERRESTRIAL) {
-+#ifdef    TER_TUNER_DTV_LO_INJECTION
-+			TER_TUNER_DTV_LO_INJECTION(front_end->tuner_ter);
-+#endif /* TER_TUNER_DTV_LO_INJECTION */
-+#ifdef    TER_TUNER_DTV_LIF_OUT_AMP
-+			/* Adjusting LIF signal for cable or terrestrial reception */
-+			switch (new_standard) {
-+			case Si2168B_DD_MODE_PROP_MODULATION_DVBT:
-+			case Si2168B_DD_MODE_PROP_MODULATION_DVBT2:
-+			{
-+				TER_TUNER_DTV_LIF_OUT_AMP(front_end->tuner_ter, 0);
-+				break;
-+			}
-+#ifdef __MCNS__
-+			case Si2168B_DD_MODE_PROP_MODULATION_MCNS:
-+#endif /* __MCNS__ */
-+			case Si2168B_DD_MODE_PROP_MODULATION_DVBC: {
-+				TER_TUNER_DTV_LIF_OUT_AMP(front_end->tuner_ter, 1);
-+				break;
-+			}
-+			default: break;
-+			}
-+#endif /* TER_TUNER_DTV_LIF_OUT_AMP */
-+		}
-+	}
-+	/* ------------------------------------------------------------ */
-+	/* Wakeup Dtv Demod                                             */
-+	/*  if it has been put in 'standby mode' and is needed          */
-+	/* ------------------------------------------------------------ */
-+	if (front_end->Si2168B_init_done) {
-+		SiTRACE("dtv_demod_sleep_request %d\n",dtv_demod_sleep_request);
-+		if ((dtv_demod_sleep_request == 1) & (dtv_demod_needed == 1) ) {
-+			SiTRACE("Wake UP DTV demod\n");
-+			if (si2168b_wakeup (front_end->demod) == NO_Si2168B_ERROR) {
-+				SiTRACE("Wake UP DTV demod OK\n");
-+				front_end->demod->Si2168B_in_standby = 0;
-+			} else {
-+				SiTRACE("Wake UP DTV demod failed!\n");
-+				return 0;
-+			}
-+		}
-+	}
-+	/* ------------------------------------------------------------ */
-+	/* Setup Dtv Demod                                              */
-+	/* Setup dtv demodulator if transition from '0' to '1'          */
-+	/* ------------------------------------------------------------ */
-+	if ((dtv_demod_already_used == 0) & (dtv_demod_needed == 1)) {
-+		/* Do the 'first init' only the first time, plus if requested  */
-+		/* (when 'force' flag is 1, Si2168B_init_done is set to '0')   */
-+		if (!front_end->Si2168B_init_done) {
-+			SiTRACE("Init demod\n");
-+			if (si2168b_first_init(front_end->demod) == NO_Si2168B_ERROR) {
-+				front_end->Si2168B_init_done = 1;
-+				SiTRACE("Demod init OK\n");
-+			} else {
-+				SiTRACE("Demod init failed!\n");
-+				return 0;
-+			}
-+		}
-+		if (front_end->demod->media == Si2168B_TERRESTRIAL) {
-+			SiTRACE("front_end->demod->media Si2168B_TERRESTRIAL\n");
-+			if (front_end->TER_init_done == 0) {
-+				SiTRACE("Configure demod for TER\n");
-+				if (si2168b_configure(front_end->demod) == NO_Si2168B_ERROR) {
-+					/* set dd_mode.modulation again, as it is overwritten by si2168b_configure */
-+					front_end->demod->dd_mode_modulation = new_standard;
-+					front_end->TER_init_done = 1;
-+				} else {
-+					SiTRACE("Demod TER configuration failed !\n");
-+					return 0;
-+				}
-+			}
-+			/* ------------------------------------------------------------ */
-+			/* Manage FEF mode in TER tuner                                 */
-+			/* ------------------------------------------------------------ */
-+			if (new_standard == Si2168B_DD_MODE_PROP_MODULATION_DVBT2) {
-+				si2168b_ter_fef_setup(front_end, 1);
-+			} else {
-+				si2168b_ter_fef_setup(front_end, 0);
-+			}
-+		}
-+		dd_mode_invert_spectrum = si2168b_set_invert_spectrum(front_end);
-+	    data = (dd_mode_bw              & Si2168B_DD_MODE_PROP_BW_MASK             ) << Si2168B_DD_MODE_PROP_BW_LSB |
-+	           (dd_mode_modulation      & Si2168B_DD_MODE_PROP_MODULATION_MASK     ) << Si2168B_DD_MODE_PROP_MODULATION_LSB |
-+	           (dd_mode_invert_spectrum & Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_MASK) << Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_LSB |
-+	           (dd_mode_auto_detect     & Si2168B_DD_MODE_PROP_AUTO_DETECT_MASK    ) << Si2168B_DD_MODE_PROP_AUTO_DETECT_LSB;
-+		if (si2168b_set_property(front_end->demod, Si2168B_DD_MODE_PROP, data)==0) {
-+			si2168b_dd_restart(front_end->demod);
-+		} else {
-+			SiTRACE("Demod restart failed !\n");
-+			return 0;
-+		}
-+	}
-+
-+	/* ------------------------------------------------------------ */
-+	/* Forbid i2c traffic to reach the tuners                       */
-+	/* ------------------------------------------------------------ */
-+	if ( front_end->tuner_indirect_i2c_connection ) { /* INDIRECT_I2C_CONNECTION? */
-+		if (i2c_connected) {
-+			SiTRACE("-- I2C -- Disconnect TER tuner i2c\n");
-+			front_end->f_TER_tuner_disable(front_end->callback);
-+		}
-+	} else {
-+		if (i2c_connected) {
-+			SiTRACE("Disconnect tuners i2c\n");
-+			si2168b_tuner_i2c_disable(front_end);
-+		}
-+	}
-+	/* ------------------------------------------------------------ */
-+	/* update value of previous_standard to prepare next call       */
-+	/* ------------------------------------------------------------ */
-+	front_end->previous_standard = new_standard;
-+	front_end->standard          = new_standard;
-+
-+	front_end->first_init_done = 1;
-+
-+	SiTRACE("Si2168B_switch_to_standard complete\n");
-+	return 1;
-+}
-+
-+static int si2168b_initialize(struct dvb_frontend *fe)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+
-+	siprintk("((((((((((((((((((((((((((((((((((((((((((((((((((((((((((\n");
-+	siprintk("(((                  %s()              )))\n", __func__);
-+	siprintk("))))))))))))))))))))))))))))))))))))))))))))))))))))))))))\n");
-+
-+	if (!si2168b_switch_to_standard(fe, Si2168B_DD_MODE_PROP_MODULATION_DVBT, 1)) {
-+		printk(KERN_ERR "%s(): si2168b_switch_to_standard() failed.\n", __func__);
-+		goto err;
-+	}
-+
-+	/* hardware related settings from base driver */
-+	siprintk("%s(): ts_clk_invert=%d\n", __func__, priv->config->ts_par_clk_invert);
-+	siprintk("%s(): ts_clk_shift=%d\n", __func__,  priv->config->ts_par_clk_shift);
-+	siprintk("%s(): clock=%d\n", __func__,         priv->config->ts_clock_mode);
-+	siprintk("%s(): clk_gapped_en=%d\n", __func__, priv->config->clk_gapped_en);
-+	siprintk("%s(): fef_mode=%d\n", __func__,      priv->config->fef_mode);
-+
-+	if (si2168b_ts_bus_ctrl(fe, 1)) { /* set the bus mode */
-+		printk(KERN_ERR "%s(): si2168b_ts_bus_ctrl(1) failed\n", __func__);
-+		/* goto err; */
-+	}
-+	return 0;
-+
-+err:
-+	printk(KERN_ERR "%s(): failed\n", __func__);
-+	return -ENODEV;
-+}
-+
-+static int si2168b_dvbc_auto_tune(struct dvb_frontend *fe, si2168b_context *demod, struct dtv_frontend_properties *p, u32 freq, int lock_start_ms)
-+{
-+	Si2168B_DVBC_STATUS_CMD_REPLY_struct dvbc_status;
-+	Si2168B_CHANNEL_SEEK_PARAM_struct seek_param = {
-+			.rangeMin     = freq,
-+			.rangeMax     = freq,
-+			.seekBWHz     = 8000000,
-+			.seekStepHz   = 0,
-+			.minSRbps     = 870000,
-+			.maxSRbps     = 7500000,
-+			/*.minRSSIdBm   = 0,*/
-+			/*.maxRSSIdBm   = 0,*/
-+			/*.minSNRHalfdB = 0,*/
-+			/*.maxSNRHalfdB = 0,*/
-+	};
-+	Si2168B_CHANNEL_SEEK_NEXT_REPLY_struct channel_status;
-+	int locked = 0;
-+    int cnr = 0;
-+
-+	siprintk("%s(): +++ DVB-C AUTO TUNING (QAM AND SYMBOL RATE DETECTION) +++\n", __func__);
-+
-+	if (si2168b_channel_seek_init(fe, &seek_param)) {
-+		pr_err("si2168b_channel_seek_init() failed.\n");
-+	}
-+	si2168b_set_tuner_params(fe, freq); /* tune first */
-+
-+    locked = si2168b_channel_seek_next(fe, &seek_param, &channel_status);
-+
-+    if (locked == 1) {
-+		pr_info("%s(): Channel detected(standard %s, f=%d SR=%d constel=%d BW=%u)\n", __func__,
-+				si2168b_standard_name(channel_status.standard),
-+				channel_status.freq,
-+				channel_status.symbol_rate_bps,
-+				channel_status.constellation,
-+				channel_status.bandwidth_Hz);
-+		p->symbol_rate = channel_status.symbol_rate_bps;
-+		switch (channel_status.constellation) {
-+		case Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_AUTO:   p->modulation = QAM_AUTO; break;
-+		case Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM128: p->modulation = QAM_128;  break;
-+		case Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM16:  p->modulation = QAM_16;   break;
-+		case Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM256: p->modulation = QAM_256;  break;
-+		case Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM32:  p->modulation = QAM_32;   break;
-+		case Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM64:  p->modulation = QAM_64;   break;
-+		default:
-+			/* invalid constellation returned */
-+			break;
-+		}
-+		msleep(150);
-+
-+		if (si2168b_dvbc_status(demod, Si2168B_DVBC_STATUS_CMD_INTACK_OK, &dvbc_status) == NO_Si2168B_ERROR) {
-+			cnr = dvbc_status.cnr / 4;
-+		} else {
-+			siprintk("%s(): si2168b_dvbc_status() failed\n", __func__);
-+		}
-+
-+		while (cnr < 1) {
-+			if (si2168b_dvbc_status(demod, Si2168B_DVBC_STATUS_CMD_INTACK_OK, &dvbc_status) == NO_Si2168B_ERROR) {
-+				cnr = dvbc_status.cnr / 4;
-+			} else {
-+				siprintk("%s(): si2168b_dvbc_status() failed\n", __func__);
-+			}
-+			if (system_time() - lock_start_ms > 1000){
-+				break;
-+			}
-+			msleep(150);
-+		}
-+		siprintk("%s(): C/N %u dB (%u ms)\n", __func__, cnr, (system_time() - lock_start_ms));
-+	} else {
-+		siprintk("%s(): Channel not locked (locked=%d)\n", __func__, locked);
-+	}
-+	si2168b_channel_seek_end(fe);
-+	return locked;
-+}
-+
-+static int si2168b_set_frontend(struct dvb_frontend *fe)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+    Si2168B_L2_Context *front_end = priv->si_front_end;
-+	si2168b_context *demod = priv->si_front_end->demod;
-+	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
-+
-+	u8  standard = 0;
-+	u32 freq = p->frequency;
-+	u32 dvb_t_bandwidth_hz = p->bandwidth_hz;
-+	u8  dvb_t_stream = 0;
-+	u32 symbol_rate_bps = 0;
-+	u8  dvb_c_constellation = 0;
-+	int plp_id = (int)p->stream_id;
-+	u8  T2_lock_mode = 0;
-+	int locked = 0;
-+	u8  force_full_init = 0;
-+    int lock_start_ms;
-+
-+    if (plp_id == 0)
-+    	plp_id = -1; /* set to auto detection */
-+
-+	siprintk("%s(): FE_SET_FRONTEND f=%u inv=%d mod=%d bw=%u plp_id=%d\n", __func__, p->frequency, p->inversion, p->modulation, p->bandwidth_hz, plp_id);
-+
-+	switch (p->delivery_system) {
-+	case SYS_DVBT:         standard = Si2168B_DD_MODE_PROP_MODULATION_DVBT; break;
-+	case SYS_DVBT2:	       standard = Si2168B_DD_MODE_PROP_MODULATION_DVBT2; break;
-+	case SYS_DVBC_ANNEX_A: standard = Si2168B_DD_MODE_PROP_MODULATION_DVBC;
-+		symbol_rate_bps = p->symbol_rate;
-+		switch (p->modulation) {
-+		case QAM_AUTO: dvb_c_constellation = Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_AUTO;   break;
-+		case QAM_128:  dvb_c_constellation = Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM128; break;
-+		case QAM_16:   dvb_c_constellation = Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM16;  break;
-+		case QAM_256:  dvb_c_constellation = Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM256; break;
-+		case QAM_32:   dvb_c_constellation = Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM32;  break;
-+		case QAM_64:   dvb_c_constellation = Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM64;  break;
-+		default:       dvb_c_constellation = Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_AUTO;   break;
-+		}
-+		break;
-+	default:
-+		siprintk("%s : ERROR: delivery system not supported\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	if (standard != front_end->demod->dd_mode_modulation) {
-+		siprintk("%s(): switching from standard %s to %s\n", __func__, si2168b_standard_name(front_end->demod->dd_mode_modulation), si2168b_standard_name(standard));
-+		if (!si2168b_switch_to_standard(fe, standard, force_full_init)) {
-+			siprintk("%s(): si2168b_switch_to_standard() failed.\n", __func__);
-+			return -ENODEV;
-+		}
-+		priv->delivery_system = p->delivery_system;
-+	}
-+
-+	if (standard == Si2168B_DD_MODE_PROP_MODULATION_DVBC) {
-+		demod->dvbc_symbol_rate = symbol_rate_bps / 1000;
-+	} else {
-+		demod->dvbc_symbol_rate = 0; /* clear old setting */
-+	}
-+
-+	siprintk("%s(): delsys=%s  Si2168B_standard=%s  freq=%d  symbol_rate_bps=%d  dvb_c_constellation=%d\n",
-+			__func__, delsys_name(p->delivery_system), si2168b_standard_name(front_end->demod->dd_mode_modulation),
-+			freq, symbol_rate_bps, dvb_c_constellation);
-+
-+	lock_start_ms = system_time();
-+
-+	if (standard == Si2168B_DD_MODE_PROP_MODULATION_DVBC && symbol_rate_bps == 7501000) { /* 7501000 = AUTO */
-+		locked = si2168b_dvbc_auto_tune(fe, demod, p, freq, lock_start_ms);
-+	} else {
-+		locked = si2168b_lock_to_carrier(fe, standard, freq,
-+				dvb_t_bandwidth_hz, dvb_t_stream, symbol_rate_bps,
-+				dvb_c_constellation, plp_id, T2_lock_mode);
-+	}
-+
-+	if (locked == 1) {
-+		siprintk("%s(): locked to carrier %dHz (duration=%dms)\n", __func__, freq, system_time()-lock_start_ms);
-+		msleep(100);
-+
-+		if (priv->config->start_ctrl)
-+			priv->config->start_ctrl(fe);
-+	} else {
-+		siprintk("%s(): not locked to carrier %dHz (duration=%dms)\n", __func__, freq, system_time()-lock_start_ms);
-+	}
-+
-+	/* After set_frontend, stats aren't available */
-+	p->strength.stat[0].scale = FE_SCALE_RELATIVE;
-+	p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+
-+	return 0;
-+}
-+
-+static int si2168b_get_tune_settings(struct dvb_frontend *fe,
-+		struct dvb_frontend_tune_settings
-+		*fe_tune_settings)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+
-+	fe_tune_settings->min_delay_ms = priv->config->min_delay_ms;
-+	siprintk("%s(): min delay = %dms\n", __func__, fe_tune_settings->min_delay_ms);
-+	return 0;
-+}
-+
-+#if defined(FE_READ_STREAM_IDS) || defined(__MPLP_TEST__)
-+static int si2168b_read_stream_ids(struct dvb_frontend *fe, struct dvb_stream_ids* ids)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	si2168b_context *demod = priv->si_front_end->demod;
-+	Si2168B_DD_STATUS_CMD_REPLY_struct      dd_status;
-+	Si2168B_DVBT2_STATUS_CMD_REPLY_struct   dvbt2_status;
-+	Si2168B_DVBT2_PLP_INFO_CMD_REPLY_struct dvbt2_plp_info;
-+	int data_plp_count;
-+	int num_plp;
-+	int plp_index;
-+	int plp_id;
-+	int plp_type;
-+	int ret = 0;
-+
-+	if (priv->delivery_system != SYS_DVBT2) {
-+		siprintk("%s(): delivery system is not DVB-T2. Aborting...\n", __func__);
-+	}
-+
-+	/* check demod */
-+	if (si2168b_dd_status(demod, Si2168B_DD_STATUS_CMD_INTACK_OK, &dd_status) != NO_Si2168B_ERROR) {
-+		siprintk("%s(): si2168b_dd_status() failed\n", __func__);
-+		return -1;
-+	}
-+
-+	if (dd_status.modulation != Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBT2) {
-+		siprintk("%s(): demod modulation is not DVB-T2. Aborting...\n", __func__);
-+		return -1;
-+	}
-+
-+	if (si2168b_dvbt2_status(demod, Si2168B_DVBT2_STATUS_CMD_INTACK_OK, &dvbt2_status) != NO_Si2168B_ERROR) {
-+		siprintk("%s(): si2168b_dvbt2_status() failed\n", __func__);
-+		return -1;
-+	}
-+
-+	SiTRACE("dvbt2_status.pcl %d\n", dvbt2_status.pcl);
-+
-+	num_plp = dvbt2_status.num_plp;
-+	plp_id  = dvbt2_status.plp_id;
-+
-+	SiTRACE("There are %d PLPs in this stream\n", num_plp);
-+	SiTRACE("PLP ID = %d\n", plp_id);
-+
-+	/* hard limiter */
-+	if (num_plp > 255) {
-+		siprintk("%s(): WARNING: limiting found %d PLPs to 255\n", __func__, num_plp);
-+		num_plp = 255;
-+	}
-+
-+	ids->num = num_plp; /* number of valid stream ids in 'val' */
-+	ids->cur = plp_id;  /* currently selected stream id */
-+
-+	data_plp_count = 0;
-+	dvbt2_plp_info.plp_id = 0;
-+	dvbt2_plp_info.plp_type = 3;
-+
-+	for (plp_index=0; plp_index<num_plp; plp_index++) {
-+		if (si2168b_dvbt2_plp_info(demod, plp_index, &dvbt2_plp_info) ==  NO_Si2168B_ERROR) {
-+			plp_id   = dvbt2_plp_info.plp_id;
-+			plp_type = dvbt2_plp_info.plp_type;
-+
-+			ids->val[plp_index] = plp_id;
-+
-+			SiTRACE("PLP index %3d: PLP ID %3d, PLP TYPE %d : ", plp_index, plp_id, plp_type);
-+			if (plp_type == Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_TYPE_COMMON) {
-+				SiTRACE("COMMON PLP at index %3d: PLP ID %3d, PLP TYPE COMMON\n", plp_index, plp_id);
-+			} else {
-+				SiTRACE("DATA   PLP at index %3d: PLP ID %3d, PLP TYPE %d\n", plp_index, plp_id, plp_type);
-+				data_plp_count++;
-+			}
-+		} else {
-+			siprintk("%s(): si2168b_dvbt2_plp_info() index %d failed\n", __func__, plp_index);
-+			ids->val[plp_index] = 0;
-+			ret = -1;
-+		}
-+	}
-+	SiTRACE("data_plp_count=%d\n", data_plp_count);
-+	return ret;
-+}
-+#endif /* FE_READ_STREAM_IDS */
-+
-+static int si2168b_get_frontend(struct dvb_frontend *fe, struct dtv_frontend_properties *fe_params)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
-+	si2168b_context *demod = priv->si_front_end->demod;
-+	Si2168B_DD_STATUS_CMD_REPLY_struct    dd_status;
-+	Si2168B_DVBT_STATUS_CMD_REPLY_struct  dvbt_status;
-+	Si2168B_DVBT2_STATUS_CMD_REPLY_struct dvbt2_status;
-+	Si2168B_DVBC_STATUS_CMD_REPLY_struct  dvbc_status;
-+
-+#if defined(FE_READ_STREAM_IDS) || defined(__MPLP_TEST__)
-+	struct dvb_stream_ids ids;
-+#endif
-+
-+	if (priv->delivery_system == SYS_UNDEFINED)
-+		return -EINVAL;
-+
-+	if (si2168b_dd_status(demod, Si2168B_DD_STATUS_CMD_INTACK_OK, &dd_status) != NO_Si2168B_ERROR) {
-+		siprintk("%s(): si2168b_dd_status() failed\n", __func__);
-+		return -EFAULT;
-+	}
-+
-+    if (dd_status.dl == Si2168B_DD_STATUS_RESPONSE_DL_LOCKED) {
-+		siprintk("%s(): FE HAS LOCK\n", __func__);
-+    }
-+
-+    switch (dd_status.modulation) {
-+	case Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBT:
-+		siprintk("%s() delivery system SYS_DVBT\n", __func__);
-+		if (si2168b_dvbt_status(demod, Si2168B_DVBT_STATUS_CMD_INTACK_OK, &dvbt_status) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): si2168b_dvbt_status() failed\n", __func__);
-+			return -EFAULT;
-+		}
-+		switch (dvbt_status.constellation) {
-+		case Si2168B_DVBT_STATUS_RESPONSE_CONSTELLATION_QAM16: p->modulation = QAM_16; break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_CONSTELLATION_QAM64: p->modulation = QAM_64; break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_CONSTELLATION_QPSK:  p->modulation = QPSK;   break;
-+		default:
-+			siprintk("%s(): invalid DVB-T constellation returned\n", __func__);
-+		}
-+		switch (dvbt_status.sp_inv) {
-+		case Si2168B_DVBT_STATUS_RESPONSE_SP_INV_INVERTED: p->inversion = INVERSION_ON;	 break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_SP_INV_NORMAL:   p->inversion = INVERSION_OFF; break;
-+		default:
-+			siprintk("%s(): invalid DVB-T sp_inv returned\n", __func__);
-+		}
-+		switch (dvbt_status.rate_hp) {
-+		case Si2168B_DVBT_STATUS_RESPONSE_RATE_HP_1_2: p->code_rate_HP = FEC_1_2; break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_RATE_HP_2_3: p->code_rate_HP = FEC_2_3; break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_RATE_HP_3_4: p->code_rate_HP = FEC_3_4; break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_RATE_HP_5_6: p->code_rate_HP = FEC_5_6; break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_RATE_HP_7_8: p->code_rate_HP = FEC_7_8; break;
-+		default:
-+			siprintk("%s(): invalid DVB-T rate_hp returned\n", __func__);
-+		}
-+		switch (dvbt_status.rate_lp) {
-+		case Si2168B_DVBT_STATUS_RESPONSE_RATE_LP_1_2: p->code_rate_LP = FEC_1_2; break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_RATE_LP_2_3: p->code_rate_LP = FEC_2_3; break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_RATE_LP_3_4: p->code_rate_LP = FEC_3_4; break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_RATE_LP_5_6: p->code_rate_LP = FEC_5_6; break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_RATE_LP_7_8: p->code_rate_LP = FEC_7_8; break;
-+		default:
-+			siprintk("%s(): invalid DVB-T rate_lp returned\n", __func__);
-+		}
-+		switch (dvbt_status.fft_mode) {
-+		case Si2168B_DVBT_STATUS_RESPONSE_FFT_MODE_2K: p->transmission_mode = TRANSMISSION_MODE_2K; break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_FFT_MODE_4K: p->transmission_mode = TRANSMISSION_MODE_4K; break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_FFT_MODE_8K: p->transmission_mode = TRANSMISSION_MODE_8K; break;
-+		default:
-+			siprintk("%s(): invalid DVB-T fft_mode returned\n", __func__);
-+		}
-+		switch (dvbt_status.guard_int) {
-+		case Si2168B_DVBT_STATUS_RESPONSE_GUARD_INT_1_16: p->guard_interval = GUARD_INTERVAL_1_16; break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_GUARD_INT_1_32: p->guard_interval = GUARD_INTERVAL_1_32; break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_GUARD_INT_1_4:  p->guard_interval = GUARD_INTERVAL_1_4;  break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_GUARD_INT_1_8:  p->guard_interval = GUARD_INTERVAL_1_8;  break;
-+		default:
-+			siprintk("%s(): invalid DVB-T guard_int returned\n", __func__);
-+		}
-+		switch (dvbt_status.hierarchy) {
-+		case Si2168B_DVBT_STATUS_RESPONSE_HIERARCHY_ALFA1: p->hierarchy = HIERARCHY_1;    break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_HIERARCHY_ALFA2: p->hierarchy = HIERARCHY_2;    break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_HIERARCHY_ALFA4: p->hierarchy = HIERARCHY_4;    break;
-+		case Si2168B_DVBT_STATUS_RESPONSE_HIERARCHY_NONE:  p->hierarchy = HIERARCHY_NONE; break;
-+		default:
-+			siprintk("%s(): invalid DVB-T hierarchy returned\n", __func__);
-+		}
-+		p->fec_inner = FEC_NONE;
-+		break;
-+	case Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBT2:
-+		siprintk("%s() delivery system SYS_DVBT2\n", __func__);
-+
-+		if (priv->delivery_system != SYS_DVBT2) {
-+			siprintk("%s(): delivery system changed from %s to SYS_DVBT2\n", __func__, delsys_name(p->delivery_system));
-+			p->delivery_system = SYS_DVBT2;
-+		}
-+
-+		if (si2168b_dvbt2_status(demod, Si2168B_DVBT2_STATUS_CMD_INTACK_OK, &dvbt2_status) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): si2168b_dvbt2_status() failed\n", __func__);
-+			return -EFAULT;
-+		}
-+		switch (dvbt2_status.constellation) {
-+		case Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_QAM128: p->modulation = QAM_128; break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_QAM16:  p->modulation = QAM_16;  break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_QAM256: p->modulation = QAM_256; break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_QAM32:  p->modulation = QAM_32;  break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_QAM64:  p->modulation = QAM_64;  break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_QPSK:   p->modulation = QPSK;    break;
-+		default:
-+			siprintk("%s(): invalid DVB-T2 constellation returned\n", __func__);
-+		}
-+		switch (dvbt2_status.sp_inv) {
-+		case Si2168B_DVBT2_STATUS_RESPONSE_SP_INV_INVERTED: p->inversion = INVERSION_ON;  break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_SP_INV_NORMAL:   p->inversion = INVERSION_OFF; break;
-+		default:
-+			siprintk("%s(): invalid DVB-T2 sp_inv returned\n", __func__);
-+		}
-+		switch (dvbt2_status.fft_mode) {
-+		case Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_16K: p->transmission_mode = TRANSMISSION_MODE_16K; break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_1K:  p->transmission_mode = TRANSMISSION_MODE_1K;  break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_2K:  p->transmission_mode = TRANSMISSION_MODE_2K;  break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_32K: p->transmission_mode = TRANSMISSION_MODE_32K; break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_4K:  p->transmission_mode = TRANSMISSION_MODE_4K;  break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_8K:  p->transmission_mode = TRANSMISSION_MODE_8K;  break;
-+		default:
-+			siprintk("%s(): invalid DVB-T2 fft_mode returned\n", __func__);
-+		}
-+		switch (dvbt2_status.guard_int) {
-+		case Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_19_128: p->guard_interval = GUARD_INTERVAL_19_128; break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_19_256: p->guard_interval = GUARD_INTERVAL_19_256; break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_1_128:  p->guard_interval = GUARD_INTERVAL_1_128;  break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_1_16:   p->guard_interval = GUARD_INTERVAL_1_16;   break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_1_32:   p->guard_interval = GUARD_INTERVAL_1_32;   break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_1_4:    p->guard_interval = GUARD_INTERVAL_1_4;    break;
-+		case Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_1_8:    p->guard_interval = GUARD_INTERVAL_1_8;    break;
-+		default:
-+			siprintk("%s(): invalid DVB-T2 guard_int returned\n", __func__);
-+		}
-+		p->fec_inner = FEC_NONE;
-+		p->code_rate_HP = FEC_NONE;
-+		p->code_rate_LP = FEC_NONE;
-+		p->hierarchy = HIERARCHY_NONE;
-+		p->stream_id = dvbt2_status.plp_id;
-+
-+#if defined(FE_READ_STREAM_IDS) || defined(__MPLP_TEST__)
-+		si2168b_read_stream_ids(fe, &ids);
-+#endif
-+		break;
-+	case Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBC:
-+		if (priv->delivery_system != SYS_DVBC_ANNEX_A) {
-+			siprintk("%s(): delivery system changed from %s to SYS_DVBC_ANNEX_A\n", __func__, delsys_name(p->delivery_system));
-+			p->delivery_system = SYS_DVBC_ANNEX_A;
-+		} else {
-+			siprintk("%s() delivery system SYS_DVBC_ANNEX_A\n", __func__);
-+		}
-+		if (si2168b_dvbc_status(demod, Si2168B_DVBC_STATUS_CMD_INTACK_OK, &dvbc_status) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): si2168b_dvbc_status() failed\n", __func__);
-+			return -EFAULT;
-+		}
-+		switch (dvbc_status.constellation) {
-+		case Si2168B_DVBC_STATUS_RESPONSE_CONSTELLATION_QAM128: p->modulation = QAM_128; break;
-+		case Si2168B_DVBC_STATUS_RESPONSE_CONSTELLATION_QAM16:  p->modulation = QAM_16;  break;
-+		case Si2168B_DVBC_STATUS_RESPONSE_CONSTELLATION_QAM256: p->modulation = QAM_256; break;
-+		case Si2168B_DVBC_STATUS_RESPONSE_CONSTELLATION_QAM32:  p->modulation = QAM_32;  break;
-+		case Si2168B_DVBC_STATUS_RESPONSE_CONSTELLATION_QAM64:  p->modulation = QAM_64;  break;
-+		default:
-+			siprintk("%s(): invalid DVB-C constellation returned\n", __func__);
-+		}
-+		switch (dvbc_status.sp_inv) {
-+		case Si2168B_DVBC_STATUS_RESPONSE_SP_INV_INVERTED: p->inversion = INVERSION_ON;  break;
-+		case Si2168B_DVBC_STATUS_RESPONSE_SP_INV_NORMAL:   p->inversion = INVERSION_OFF; break;
-+		default:
-+			siprintk("%s(): invalid DVB-C sp_inv returned\n", __func__);
-+		}
-+		p->symbol_rate = demod->dvbc_symbol_rate * 1000;
-+		p->fec_inner = FEC_NONE;
-+		break;
-+	default:
-+		siprintk("%s() delivery system not supported\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	memcpy(fe_params, p, sizeof(struct dtv_frontend_properties));
-+
-+	return 0;
-+}
-+
-+static int si2168b_sleep(struct dvb_frontend *fe)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	Si2168B_L2_Context *front_end = priv->si_front_end;
-+
-+#if 1 /* FGR - BUGBUG try alternate power down */
-+	siprintk("%s()\n", __func__);
-+
-+	if (si2168b_ts_bus_ctrl(fe, 0)) { /* set the bus mode */
-+		printk(KERN_ERR "%s(): si2168b_ts_bus_ctrl(0) failed\n", __func__);
-+	}
-+
-+	if (!si2168b_switch_to_standard(fe, Si2168B_DD_MODE_PROP_MODULATION_SLEEP, 0)) {
-+		printk(KERN_ERR "%s(): si2168b_switch_to_standard() failed.\n", __func__);
-+		return -EIO;
-+	}
-+
-+	front_end->demod->Si2168B_in_standby = 1;
-+
-+#else /* FGR */
-+	si2168b_context *demod = priv->si_front_end->demod;
-+
-+	siprintk("%s()\n", __func__);
-+
-+	if (si2168b_ts_bus_ctrl(fe, 0)) { /* set the bus mode */
-+		printk(KERN_ERR "%s(): si2168b_ts_bus_ctrl(0) failed\n", __func__);
-+	}
-+
-+	if ( priv->config->indirect_i2c_connection ) { /* INDIRECT_I2C_CONNECTION? */
-+		if (priv->si_front_end->f_TER_tuner_enable(priv->si_front_end->callback) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): f_TER_tuner_enable() failed\n", __func__);
-+			return -EIO;
-+		}
-+	} else {
-+		if (si2168b_tuner_i2c_enable(priv->si_front_end) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): si2168b_tuner_i2c_enable() failed\n", __func__);
-+			return -EIO;
-+		}
-+	}
-+
-+	/* power down tuner */
-+	/* ToDo */
-+	/* ... */
-+
-+	if ( priv->config->indirect_i2c_connection ) { /* INDIRECT_I2C_CONNECTION? */
-+		if (priv->si_front_end->f_TER_tuner_disable(priv->si_front_end->callback) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): f_TER_tuner_disable() failed\n", __func__);
-+			return -EIO;
-+		}
-+	} else {
-+		if (si2168b_tuner_i2c_disable(priv->si_front_end) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): si2168b_tuner_i2c_disable() failed\n", __func__);
-+			return -EIO;
-+		}
-+	}
-+
-+	if (si2168b_power_down(demod) != NO_Si2168B_ERROR) {
-+		siprintk("%s(): si2168b_power_down() failed\n", __func__);
-+		return -EIO;
-+	}
-+	front_end->demod->Si2168B_in_standby = 1;
-+#endif /* FGR */
-+
-+	return 0;
-+}
-+
-+static void si2168b_release(struct dvb_frontend *fe)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+
-+	siprintk("%s\n", __func__);
-+
-+	if (priv->si_front_end->demod)
-+		kfree(priv->si_front_end->demod);
-+
-+	if (priv->si_front_end)
-+		kfree(priv->si_front_end);
-+
-+	if (priv)
-+		kfree(priv);
-+}
-+
-+static enum dvbfe_algo si2168b_get_frontend_algo(struct dvb_frontend *fe)
-+{
-+#if 1
-+	/*siprintk("%s(): DVBFE_ALGO_HW\n", __func__);*/
-+	return DVBFE_ALGO_HW;      /* = si2168b_tune()          */
-+#endif
-+#if 0
-+	siprintk("%s(): DVBFE_ALGO_SW\n", __func__);
-+	return DVBFE_ALGO_SW;      /* = dvb_frontend_swzigzag() */
-+#endif
-+#if 0
-+	siprintk("%s(): DVBFE_ALGO_CUSTOM\n", __func__);
-+	return DVBFE_ALGO_CUSTOM;  /* = Si2168B_Search()        */
-+#endif
-+}
-+
-+static int si2168b_tune(struct dvb_frontend *fe, bool re_tune, unsigned int mode_flags, unsigned int *delay, enum fe_status *status)
-+{
-+	int rc = 0;
-+
-+	siprintk("%s(): re_tune=%d  mode_flags=%u\n", __func__, (int)re_tune, mode_flags);
-+
-+	if (re_tune)
-+		rc = si2168b_set_frontend(fe);
-+
-+	if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
-+		si2168b_read_status(fe, status);
-+
-+	return rc;
-+}
-+
-+static enum dvbfe_search si2168b_search(struct dvb_frontend *fe)
-+{
-+	struct Si2168B_Priv *priv = fe->demodulator_priv;
-+	/*si2168b_context *demod = priv->si_front_end->demod;*/
-+	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
-+	int ret, i;
-+	enum fe_status status = 0;
-+
-+	siprintk("%s(): delsys=%d\n", __func__,	fe->dtv_property_cache.delivery_system);
-+
-+	/* switch between DVB-T and DVB-T2 when tune fails */
-+	if (priv->last_tune_failed) {
-+		if (priv->delivery_system == SYS_DVBT) {
-+			c->delivery_system = SYS_DVBT2;
-+		} else if (priv->delivery_system == SYS_DVBT2) {
-+			c->delivery_system = SYS_DVBT;
-+		}
-+	}
-+
-+	/* set frontend */
-+	ret = si2168b_set_frontend(fe);
-+	if (ret)
-+		goto error;
-+
-+
-+	/* frontend lock wait loop count */
-+	switch (priv->delivery_system) {
-+	case SYS_DVBT:
-+	case SYS_DVBC_ANNEX_A:
-+		i = 2;
-+		break;
-+	case SYS_DVBT2:
-+		i = 4;
-+		break;
-+	case SYS_UNDEFINED:
-+	default:
-+		i = 0;
-+		break;
-+	}
-+
-+	/* wait frontend lock */
-+	for (; i > 0; i--) {
-+		siprintk("%s(): loop=%d\n", __func__, i);
-+		msleep(50);
-+		ret = si2168b_read_status(fe, &status);
-+		if (ret)
-+			goto error;
-+
-+		if (status & FE_HAS_LOCK)
-+			break;
-+	}
-+
-+	/* check if we have a valid signal */
-+	if (status & FE_HAS_LOCK) {
-+		priv->last_tune_failed = 0;
-+		return DVBFE_ALGO_SEARCH_SUCCESS;
-+	} else {
-+		priv->last_tune_failed = 1;
-+		return DVBFE_ALGO_SEARCH_AGAIN;
-+	}
-+
-+error:
-+	siprintk("%s(): failed=%d\n", __func__, ret);
-+	return DVBFE_ALGO_SEARCH_ERROR;
-+}
-+
-+static const struct dvb_frontend_ops si2168b_ops = {
-+		.delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
-+		.info = {
-+				.name = "Si2168B DVB-T/T2/C",
-+				.frequency_stepsize = 62500,
-+				.frequency_min = 48000000,
-+				.frequency_max = 870000000,
-+				.symbol_rate_min = 870000,
-+				.symbol_rate_max = 7501000,
-+				.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3
-+				| FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8
-+				| FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_32
-+				| FE_CAN_QAM_64 | FE_CAN_QAM_128 | FE_CAN_QAM_256
-+				| FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO
-+				| FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
-+				| FE_CAN_MULTISTREAM | FE_CAN_2G_MODULATION | FE_CAN_MUTE_TS
-+		},
-+
-+		.release = si2168b_release,
-+		/*.release_sec,*/
-+
-+		.init = si2168b_initialize,
-+		.sleep = si2168b_sleep,
-+
-+		/*.write,*/
-+
-+		/* if this is set, it overrides the default swzigzag */
-+		.tune = si2168b_tune,
-+		/* get frontend tuning algorithm from the module */
-+		.get_frontend_algo = si2168b_get_frontend_algo,
-+
-+		/* these two are only used for the swzigzag code */
-+		.set_frontend = si2168b_set_frontend,
-+		.get_tune_settings = si2168b_get_tune_settings,
-+		.get_frontend = si2168b_get_frontend,
-+
-+		.read_status = si2168b_read_status,
-+		.read_ber = si2168b_read_ber,
-+		.read_signal_strength = si2168b_read_rssi,
-+		.read_snr = si2168b_read_cnr,
-+		.read_ucblocks = si2168b_read_uncorrs,
-+
-+		/* Sat:
-+		.diseqc_reset_overload,
-+		.diseqc_send_master_cmd,
-+		.diseqc_recv_slave_reply,
-+		.diseqc_send_burst,
-+		.set_tone,
-+		.set_voltage,
-+		.enable_high_lnb_voltage,
-+		.dishnetwork_send_legacy_command,
-+		*/
-+
-+		.i2c_gate_ctrl = si2168b_i2c_gate_ctrl,
-+		.ts_bus_ctrl = si2168b_ts_bus_ctrl,
-+		/* .set_lna set in em28xx-dvb.c */
-+
-+		/* These callbacks are for devices that implement their own
-+		 * tuning algorithms, rather than a simple swzigzag
-+		 */
-+		.search = si2168b_search,
-+
-+		/* Allow the frontend to validate incoming properties */
-+		/*.set_property,*/
-+		/*.get_property,*/
-+#ifdef FE_READ_STREAM_IDS
-+		.read_stream_ids = si2168b_read_stream_ids,
-+#endif
-+};
-+
-+
-+struct dvb_frontend *si2168b_attach(const struct si2168b_config *config, struct i2c_adapter *i2c)
-+{
-+	struct dtv_frontend_properties *p;
-+	struct Si2168B_Priv *priv;
-+
-+	siprintk("%s()\n", __func__);
-+
-+	/* allocate memory */
-+	priv = kzalloc(sizeof(struct Si2168B_Priv), GFP_KERNEL);
-+	if (priv == NULL) {
-+		siprintk("%s(): kzalloc() failed.\n", __func__);
-+		goto error;
-+	}
-+
-+	priv->si_front_end = kzalloc(sizeof(struct Si2168B_L2_Context), GFP_KERNEL);
-+	if (priv->si_front_end == NULL) {
-+		siprintk("%s(): kzalloc si_front_end failed.\n", __func__);
-+		kfree(priv);
-+		goto error;
-+	}
-+
-+	priv->si_front_end->demod = kzalloc(sizeof(struct si2168b_context), GFP_KERNEL);
-+	if (priv->si_front_end->demod == NULL) {
-+		siprintk("%s(): kzalloc demod failed.\n", __func__);
-+		kfree(priv->si_front_end);
-+		kfree(priv);
-+		goto error;
-+	}
-+
-+	priv->config = config;
-+	priv->i2c = i2c;
-+	priv->delivery_system = SYS_UNDEFINED;
-+
-+	/* create dvb_frontend */
-+	memcpy(&priv->frontend.ops, &si2168b_ops, sizeof(struct dvb_frontend_ops));
-+	priv->frontend.demodulator_priv = priv;
-+
-+	if (!si2168b_sw_init(priv,
-+			0,
-+			enable_tuner_i2c,
-+			disable_tuner_i2c,
-+			i2c_callback)){
-+		printk(KERN_ERR "%s(): si2168b_sw_init() failed.\n", __func__);
-+	}
-+	/* enable tuner i2c routing for tuner autodetection */
-+	if ( priv->config->indirect_i2c_connection ) { /* INDIRECT_I2C_CONNECTION? */
-+		if (priv->si_front_end->f_TER_tuner_enable(priv->si_front_end->callback) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): f_TER_tuner_enable() failed\n", __func__);
-+		}
-+	} else {
-+		if (si2168b_tuner_i2c_enable(priv->si_front_end) != NO_Si2168B_ERROR) {
-+			siprintk("%s(): si2168b_tuner_i2c_enable() failed\n", __func__);
-+		}
-+	}
-+	/* tuner i2c routing is disabled automatically after first tuner access */
-+
-+	/* Initialize stats */
-+	p = &priv->frontend.dtv_property_cache;
-+	p->strength.len = 1;
-+	p->cnr.len = 1;
-+	p->block_error.len = 1;
-+	p->block_count.len = 1;
-+	p->pre_bit_error.len = 1;
-+	p->pre_bit_count.len = 1;
-+	p->post_bit_error.len = 1;
-+	p->post_bit_count.len = 1;
-+
-+	p->strength.stat[0].scale = FE_SCALE_DECIBEL;
-+	p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+	p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
-+
-+	return &priv->frontend;
-+
-+error:
-+	return NULL;
-+}
-+EXPORT_SYMBOL(si2168b_attach);
-+
-+MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
-+MODULE_PARM_DESC(sitrace, "Turn on/off SiTRACE messages (default:off).");
-+MODULE_PARM_DESC(mutex, "Turn on/off mutex (default:on).");
-+
-+MODULE_DESCRIPTION("SiLabs 2168B T/T2/C DVB driver");
-+MODULE_AUTHOR("Source code provided by Silicon Laboratories Inc.");
-+MODULE_AUTHOR("Henning Garbers <hgarbers@pctvsystems.com>");
-+MODULE_LICENSE("PROPRIETARY AND CONFIDENTIAL");
-+MODULE_VERSION("2015-03-09");
---- linux-4.15/drivers/media/dvb-frontends/si2168b.h.0140~	2018-02-12 11:32:52.764582151 +0100
-+++ linux-4.15/drivers/media/dvb-frontends/si2168b.h	2018-02-12 11:32:52.764582151 +0100
-@@ -0,0 +1,70 @@
-+#ifndef SI2168B_H
-+#define SI2168B_H
-+
-+#define DRIVER_BUILD
-+#define TER_TUNER_SILABS
-+#define HAUPPAUGE
-+#define HCW_10BDA
-+#define no_CHECK_CRC
-+#define no_RANGE_CHECK
-+#define __MPLP_TEST__
-+#ifndef FE_READ_STREAM_IDS
-+#ifdef __MPLP_TEST__
-+struct dvb_stream_ids {
-+	__u8	val[256];	/* stream ids seen on the transponder */
-+	__u8    num;		/* number of valid stream ids in 'val' */
-+	__u8    cur;		/* currently selected stream id */
-+};
-+#endif
-+#endif
-+
-+#include <linux/kconfig.h>
-+#include <linux/dvb/frontend.h>
-+#include "dvb_frontend.h"
-+
-+extern int _sitrace; /* module parameter: SiTRACE on/off */
-+
-+struct si2168b_config {
-+	/* the demodulator's i2c address */
-+	u8 demod_address;
-+
-+	/* minimum delay before retuning */
-+	int min_delay_ms;
-+
-+	u8 ts_bus_mode; /*1-serial, 2-parallel.*/
-+	u8 ts_clock_mode; /*0-auto, 1-manual.*/
-+	u8 clk_gapped_en; /*0-disabled, 1-enabled.*/
-+	u8 ts_par_clk_invert; /* 0-not-invert, 1-invert */
-+	u8 ts_par_clk_shift;
-+
-+	/* TER Tuner FEF management options
-+	   FEF_MODE_SLOW_NORMAL_AGC  (=0)
-+	   FEF_MODE_FREEZE_PIN       (=1)
-+	   FEF_MODE_SLOW_INITIAL_AGC (=2) */
-+    u8 fef_mode;
-+    /* FEF pin connected to TER tuner AGC freeze input */
-+	u8 fef_pin;
-+	 /* GPIO state on FEF_pin when used (during FEF periods) */
-+	u8 fef_level;
-+
-+    /* tuner i2c connection               */
-+	/* 0-tuner connected through Si2168B  */
-+	/* 1-tuner is direct accessible       */
-+	u8 indirect_i2c_connection;
-+
-+	int (*start_ctrl)(struct dvb_frontend *fe);
-+};
-+
-+#if IS_ENABLED(CONFIG_DVB_SI2168B)
-+extern struct dvb_frontend *si2168b_attach(const struct si2168b_config *config,
-+						struct i2c_adapter *i2c);
-+#else
-+static inline struct dvb_frontend *si2168b_attach(
-+		const struct si2168b_config *config, struct i2c_adapter *i2c)
-+{
-+	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
-+	return NULL;
-+}
-+#endif
-+
-+#endif
---- linux-4.15/drivers/media/dvb-frontends/si2168b_priv.h.0140~	2018-02-12 11:32:52.766582165 +0100
-+++ linux-4.15/drivers/media/dvb-frontends/si2168b_priv.h	2018-02-12 11:32:52.766582165 +0100
-@@ -0,0 +1,4390 @@
-+#ifndef __SI2168B_PRIV_H__
-+#define __SI2168B_PRIV_H__
-+
-+#include "si2168b.h"
-+
-+/* Uncomment the following line to activate all traces in the code */
-+#define SiTRACES
-+
-+#define Si2168B_A40_COMPATIBLE
-+
-+#define Si2168B_REF_FREQUENCY_TER 24
-+#define Si2168B_CLOCK_MODE_TER    Si2168B_START_CLK_CMD_CLK_MODE_CLK_CLKIO
-+
-+#define TUNERTER_API
-+#define L1_RF_TER_TUNER_FEF_MODE_FREEZE_PIN_SETUP
-+#define L1_RF_TER_TUNER_FEF_MODE_SLOW_INITIAL_AGC_SETUP
-+#define L1_RF_TER_TUNER_FEF_MODE_SLOW_NORMAL_AGC_SETUP
-+
-+#define Si2168B_DOWNLOAD_ON_CHANGE 1
-+#define Si2168B_DOWNLOAD_ALWAYS    0
-+
-+#define Si2168B_TERRESTRIAL 1
-+
-+#define Si2168B_DVBT_MIN_LOCK_TIME    100
-+#define Si2168B_DVBT_MAX_LOCK_TIME   2000
-+
-+#define Si2168B_CLOCK_ALWAYS_OFF 0
-+#define Si2168B_CLOCK_ALWAYS_ON  1
-+#define Si2168B_CLOCK_MANAGED    2
-+
-+#define Si2168B_DVBT2_MIN_LOCK_TIME   100
-+#define Si2168B_DVBT2_MAX_LOCK_TIME  2000
-+
-+#define Si2168B_DVBC_MIN_LOCK_TIME     20
-+#define Si2168B_DVBC_MAX_SEARCH_TIME 5000
-+
-+#define Si2168B_COMMAND_PROTOTYPES
-+
-+/* <porting> Replace  CUSTOM_PRINTF with your print-out function.*/
-+/* #define CUSTOM_PRINTF printf */
-+
-+#define ERROR_MESSAGE_MAX_LENGH 1000
-+#define CHECK_FOR_ERRORS  if (L0_ErrorMessage()) printf("\n\n**************\n%s**************\n\n\n", L0_error_message);
-+
-+#ifdef SiTRACES
-+/* Porting: Select which of the following lines will allow you to display the function names */
-+/* Porting: __FUNCTION__ is defined by GCC                                                   */
-+/* Porting: __func__     is defined by C99 (it is not defined for VisualStudio 6)            */
-+/* Porting: ""           will not display the function names, but will work on all platforms */
-+#define SiTRACE(...)        sitrace_function(__FILE__, __LINE__, __FUNCTION__ ,__VA_ARGS__)
-+/*#define SiTRACE(...)        SiTraceFunction(__FILE__, __LINE__, __func__     ,__VA_ARGS__)*/
-+/*#define SiTRACE(...)        SiTraceFunction(__FILE__, __LINE__, ""           ,__VA_ARGS__)*/
-+/*#define SiTRACE(...) */       /* nothing */
-+
-+/* Replace 'SiTRACES_FULL' by 'SiTRACES_MINIMAL' in the following line to de-activate full features mode */
-+/* WARNING : the minimal features mode disables tracing functions in stdout and the extern file          */
-+#define SiTRACES_FULL                  1
-+#define SiTRACES_MINIMAL               0
-+#define SiTRACES_FEATURES     SiTRACES_MINIMAL
-+
-+#else
-+#define SiTRACE(...)               /* empty */
-+#define SiTraceConfiguration(...)  /* empty */
-+#define SiTracesSuspend()          /* empty */
-+#define SiTracesResume()           /* empty */
-+#endif /* SiTRACES */
-+
-+#define TRACES_PRINTF                SiTRACE
-+#define ALLOCATION_ERROR_MESSAGE     SiTRACE
-+#define TREAT_ERROR_MESSAGE          SiTRACE
-+#define TRACES_ERR                   SiTRACE
-+#define TRACES_TRACE                 SiTRACE
-+#define TRACES_SHOW                  SiTRACE
-+#define TRACES_USE                   SiTRACE
-+
-+#ifdef RWTRACES
-+/*    #warning "register-level traces activated (RWTRACES defined)" */
-+#define L1_READ(ptr,  register)     L0_ReadRegisterTrace  (ptr->i2c, #register,     register##_ADDRESS, register##_OFFSET, register##_NBBIT, register##_SIGNED)
-+#define L1_WRITE(ptr, register, v ) L0_WriteRegisterTrace (ptr->i2c, #register, #v, register##_ADDRESS, register##_OFFSET, register##_NBBIT, register##_ALONE, v)
-+#else
-+#define L1_READ(ptr,  register)     L0_ReadRegister       (ptr->i2c,                register##_ADDRESS, register##_OFFSET, register##_NBBIT, register##_SIGNED)
-+#define L1_WRITE(ptr, register, v ) L0_WriteRegister      (ptr->i2c,                register##_ADDRESS, register##_OFFSET, register##_NBBIT, register##_ALONE, v)
-+#endif
-+
-+/******************************************************************************/
-+/* TER Tuner FEF management options */
-+/******************************************************************************/
-+#define Si2168B_FEF_MODE_SLOW_NORMAL_AGC  0
-+#define Si2168B_FEF_MODE_FREEZE_PIN       1
-+#define Si2168B_FEF_MODE_SLOW_INITIAL_AGC 2
-+
-+/******************************************************************************/
-+/* TER Tuner FEF management selection (possible values are defined above) */
-+/* NB : This selection is the 'preferred' solution.                           */
-+/* The code will use more compilation flags to slect the final mode based     */
-+/*  on what the TER tuner can actually do.                                    */
-+/******************************************************************************/
-+/*#define Si2168B_FEF_MODE    Si2168B_FEF_MODE_FREEZE_PIN*/
-+/*#define Si2168B_FEF_MODE    Si2168B_FEF_MODE_SLOW_NORMAL_AGC*/
-+
-+/******************************************************************************/
-+/* Clock sources definition (allows using 'clear' names for clock sources)    */
-+/******************************************************************************/
-+typedef enum Si2168B_CLOCK_SOURCE {
-+	Si2168B_Xtal_clock = 0,
-+	Si2168B_TER_Tuner_clock,
-+	Si2168B_SAT_Tuner_clock
-+} Si2168B_CLOCK_SOURCE;
-+
-+#ifndef    Si2168B_A40_COMPATIBLE
-+#ifndef    Si2168B_A3A_COMPATIBLE
-+"If you get a compilation error on these lines, it means that no Si2168B version has been selected.";
-+"Please define Si2168B_A40_COMPATIBLE or Si2168B_A3A_COMPATIBLE at project level!";
-+"Once the flags will be defined, this code will not be visible to the compiler anymore";
-+"Do NOT comment these lines, they are here to help, showing if there are missing project flags";
-+#endif /* Si2168B_A3A_COMPATIBLE */
-+#endif /* Si2168B_A40_COMPATIBLE */
-+
-+/* Si2168B DD_BER_RESOL property definition */
-+#define Si2168B_DD_BER_RESOL_PROP 0x1003
-+
-+#ifdef Si2168B_DD_BER_RESOL_PROP
-+#define Si2168B_DD_BER_RESOL_PROP_CODE 0x001003
-+
-+
-+typedef struct { /* Si2168B_DD_BER_RESOL_PROP_struct */
-+	u8  exp;
-+	u8  mant;
-+} Si2168B_DD_BER_RESOL_PROP_struct;
-+
-+/* DD_BER_RESOL property, EXP field definition (NO TITLE)*/
-+#define Si2168B_DD_BER_RESOL_PROP_EXP_LSB         0
-+#define Si2168B_DD_BER_RESOL_PROP_EXP_MASK        0x0f
-+#define Si2168B_DD_BER_RESOL_PROP_EXP_DEFAULT    7
-+#define Si2168B_DD_BER_RESOL_PROP_EXP_EXPLO_MIN  1
-+#define Si2168B_DD_BER_RESOL_PROP_EXP_EXPLO_MAX  8
-+
-+/* DD_BER_RESOL property, MANT field definition (NO TITLE)*/
-+#define Si2168B_DD_BER_RESOL_PROP_MANT_LSB         4
-+#define Si2168B_DD_BER_RESOL_PROP_MANT_MASK        0x0f
-+#define Si2168B_DD_BER_RESOL_PROP_MANT_DEFAULT    1
-+#define Si2168B_DD_BER_RESOL_PROP_MANT_MANTLO_MIN  1
-+#define Si2168B_DD_BER_RESOL_PROP_MANT_MANTLO_MAX  9
-+
-+#endif /* Si2168B_DD_BER_RESOL_PROP */
-+
-+/* Si2168B DD_CBER_RESOL property definition */
-+#define Si2168B_DD_CBER_RESOL_PROP 0x1002
-+
-+#ifdef Si2168B_DD_CBER_RESOL_PROP
-+#define Si2168B_DD_CBER_RESOL_PROP_CODE 0x001002
-+
-+
-+typedef struct { /* Si2168B_DD_CBER_RESOL_PROP_struct */
-+	u8  exp;
-+	u8  mant;
-+} Si2168B_DD_CBER_RESOL_PROP_struct;
-+
-+/* DD_CBER_RESOL property, EXP field definition (NO TITLE)*/
-+#define Si2168B_DD_CBER_RESOL_PROP_EXP_LSB         0
-+#define Si2168B_DD_CBER_RESOL_PROP_EXP_MASK        0x0f
-+#define Si2168B_DD_CBER_RESOL_PROP_EXP_DEFAULT    5
-+#define Si2168B_DD_CBER_RESOL_PROP_EXP_EXPLO_MIN  1
-+#define Si2168B_DD_CBER_RESOL_PROP_EXP_EXPLO_MAX  8
-+
-+/* DD_CBER_RESOL property, MANT field definition (NO TITLE)*/
-+#define Si2168B_DD_CBER_RESOL_PROP_MANT_LSB         4
-+#define Si2168B_DD_CBER_RESOL_PROP_MANT_MASK        0x0f
-+#define Si2168B_DD_CBER_RESOL_PROP_MANT_DEFAULT    1
-+#define Si2168B_DD_CBER_RESOL_PROP_MANT_MANTLO_MIN  1
-+#define Si2168B_DD_CBER_RESOL_PROP_MANT_MANTLO_MAX  9
-+
-+#endif /* Si2168B_DD_CBER_RESOL_PROP */
-+
-+/* Si2168B DD_FER_RESOL property definition */
-+#define Si2168B_DD_FER_RESOL_PROP 0x100c
-+
-+#ifdef Si2168B_DD_FER_RESOL_PROP
-+#define Si2168B_DD_FER_RESOL_PROP_CODE 0x00100c
-+
-+typedef struct { /* Si2168B_DD_FER_RESOL_PROP_struct */
-+	u8  exp;
-+	u8  mant;
-+} Si2168B_DD_FER_RESOL_PROP_struct;
-+
-+/* DD_FER_RESOL property, EXP field definition (NO TITLE)*/
-+#define Si2168B_DD_FER_RESOL_PROP_EXP_LSB         0
-+#define Si2168B_DD_FER_RESOL_PROP_EXP_MASK        0x0f
-+#define Si2168B_DD_FER_RESOL_PROP_EXP_DEFAULT    3
-+#define Si2168B_DD_FER_RESOL_PROP_EXP_EXP_MIN  1
-+#define Si2168B_DD_FER_RESOL_PROP_EXP_EXP_MAX  4
-+
-+/* DD_FER_RESOL property, MANT field definition (NO TITLE)*/
-+#define Si2168B_DD_FER_RESOL_PROP_MANT_LSB         4
-+#define Si2168B_DD_FER_RESOL_PROP_MANT_MASK        0x0f
-+#define Si2168B_DD_FER_RESOL_PROP_MANT_DEFAULT    1
-+#define Si2168B_DD_FER_RESOL_PROP_MANT_MANT_MIN  1
-+#define Si2168B_DD_FER_RESOL_PROP_MANT_MANT_MAX  9
-+
-+#endif /* Si2168B_DD_FER_RESOL_PROP */
-+
-+/* Si2168B DD_IEN property definition */
-+#define Si2168B_DD_IEN_PROP 0x1006
-+
-+#ifdef Si2168B_DD_IEN_PROP
-+#define Si2168B_DD_IEN_PROP_CODE 0x001006
-+
-+typedef struct { /* Si2168B_DD_IEN_PROP_struct */
-+	u8  ien_bit0;
-+	u8  ien_bit1;
-+	u8  ien_bit2;
-+	u8  ien_bit3;
-+	u8  ien_bit4;
-+	u8  ien_bit5;
-+	u8  ien_bit6;
-+	u8  ien_bit7;
-+} Si2168B_DD_IEN_PROP_struct;
-+
-+/* DD_IEN property, IEN_BIT0 field definition (NO TITLE)*/
-+#define Si2168B_DD_IEN_PROP_IEN_BIT0_LSB         0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT0_MASK        0x01
-+#define Si2168B_DD_IEN_PROP_IEN_BIT0_DEFAULT    0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT0_DISABLE  0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT0_ENABLE   1
-+
-+/* DD_IEN property, IEN_BIT1 field definition (NO TITLE)*/
-+#define Si2168B_DD_IEN_PROP_IEN_BIT1_LSB         1
-+#define Si2168B_DD_IEN_PROP_IEN_BIT1_MASK        0x01
-+#define Si2168B_DD_IEN_PROP_IEN_BIT1_DEFAULT    0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT1_DISABLE  0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT1_ENABLE   1
-+
-+/* DD_IEN property, IEN_BIT2 field definition (NO TITLE)*/
-+#define Si2168B_DD_IEN_PROP_IEN_BIT2_LSB         2
-+#define Si2168B_DD_IEN_PROP_IEN_BIT2_MASK        0x01
-+#define Si2168B_DD_IEN_PROP_IEN_BIT2_DEFAULT    0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT2_DISABLE  0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT2_ENABLE   1
-+
-+/* DD_IEN property, IEN_BIT3 field definition (NO TITLE)*/
-+#define Si2168B_DD_IEN_PROP_IEN_BIT3_LSB         3
-+#define Si2168B_DD_IEN_PROP_IEN_BIT3_MASK        0x01
-+#define Si2168B_DD_IEN_PROP_IEN_BIT3_DEFAULT    0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT3_DISABLE  0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT3_ENABLE   1
-+
-+/* DD_IEN property, IEN_BIT4 field definition (NO TITLE)*/
-+#define Si2168B_DD_IEN_PROP_IEN_BIT4_LSB         4
-+#define Si2168B_DD_IEN_PROP_IEN_BIT4_MASK        0x01
-+#define Si2168B_DD_IEN_PROP_IEN_BIT4_DEFAULT    0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT4_DISABLE  0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT4_ENABLE   1
-+
-+/* DD_IEN property, IEN_BIT5 field definition (NO TITLE)*/
-+#define Si2168B_DD_IEN_PROP_IEN_BIT5_LSB         5
-+#define Si2168B_DD_IEN_PROP_IEN_BIT5_MASK        0x01
-+#define Si2168B_DD_IEN_PROP_IEN_BIT5_DEFAULT    0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT5_DISABLE  0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT5_ENABLE   1
-+
-+/* DD_IEN property, IEN_BIT6 field definition (NO TITLE)*/
-+#define Si2168B_DD_IEN_PROP_IEN_BIT6_LSB         6
-+#define Si2168B_DD_IEN_PROP_IEN_BIT6_MASK        0x01
-+#define Si2168B_DD_IEN_PROP_IEN_BIT6_DEFAULT    0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT6_DISABLE  0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT6_ENABLE   1
-+
-+/* DD_IEN property, IEN_BIT7 field definition (NO TITLE)*/
-+#define Si2168B_DD_IEN_PROP_IEN_BIT7_LSB         7
-+#define Si2168B_DD_IEN_PROP_IEN_BIT7_MASK        0x01
-+#define Si2168B_DD_IEN_PROP_IEN_BIT7_DEFAULT    0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT7_DISABLE  0
-+#define Si2168B_DD_IEN_PROP_IEN_BIT7_ENABLE   1
-+
-+#endif /* Si2168B_DD_IEN_PROP */
-+
-+/* Si2168B DD_IF_INPUT_FREQ property definition */
-+#define Si2168B_DD_IF_INPUT_FREQ_PROP 0x100b
-+
-+#ifdef Si2168B_DD_IF_INPUT_FREQ_PROP
-+#define Si2168B_DD_IF_INPUT_FREQ_PROP_CODE 0x00100b
-+
-+
-+typedef struct { /* Si2168B_DD_IF_INPUT_FREQ_PROP_struct */
-+	u16 offset;
-+} Si2168B_DD_IF_INPUT_FREQ_PROP_struct;
-+
-+/* DD_IF_INPUT_FREQ property, OFFSET field definition (NO TITLE)*/
-+#define Si2168B_DD_IF_INPUT_FREQ_PROP_OFFSET_LSB         0
-+#define Si2168B_DD_IF_INPUT_FREQ_PROP_OFFSET_MASK        0xffff
-+#define Si2168B_DD_IF_INPUT_FREQ_PROP_OFFSET_DEFAULT    5000
-+#define Si2168B_DD_IF_INPUT_FREQ_PROP_OFFSET_OFFSET_MIN  0
-+#define Si2168B_DD_IF_INPUT_FREQ_PROP_OFFSET_OFFSET_MAX  36000
-+
-+#endif /* Si2168B_DD_IF_INPUT_FREQ_PROP */
-+
-+/* Si2168B DD_INT_SENSE property definition */
-+#define Si2168B_DD_INT_SENSE_PROP 0x1007
-+
-+#ifdef Si2168B_DD_INT_SENSE_PROP
-+#define Si2168B_DD_INT_SENSE_PROP_CODE 0x001007
-+
-+typedef struct { /* Si2168B_DD_INT_SENSE_PROP_struct */
-+	u8  neg_bit0;
-+	u8  neg_bit1;
-+	u8  neg_bit2;
-+	u8  neg_bit3;
-+	u8  neg_bit4;
-+	u8  neg_bit5;
-+	u8  neg_bit6;
-+	u8  neg_bit7;
-+	u8  pos_bit0;
-+	u8  pos_bit1;
-+	u8  pos_bit2;
-+	u8  pos_bit3;
-+	u8  pos_bit4;
-+	u8  pos_bit5;
-+	u8  pos_bit6;
-+	u8  pos_bit7;
-+} Si2168B_DD_INT_SENSE_PROP_struct;
-+
-+/* DD_INT_SENSE property, NEG_BIT0 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT0_LSB         0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT0_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT0_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT0_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT0_ENABLE   1
-+
-+/* DD_INT_SENSE property, NEG_BIT1 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT1_LSB         1
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT1_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT1_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT1_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT1_ENABLE   1
-+
-+/* DD_INT_SENSE property, NEG_BIT2 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT2_LSB         2
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT2_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT2_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT2_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT2_ENABLE   1
-+
-+/* DD_INT_SENSE property, NEG_BIT3 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT3_LSB         3
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT3_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT3_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT3_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT3_ENABLE   1
-+
-+/* DD_INT_SENSE property, NEG_BIT4 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT4_LSB         4
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT4_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT4_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT4_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT4_ENABLE   1
-+
-+/* DD_INT_SENSE property, NEG_BIT5 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT5_LSB         5
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT5_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT5_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT5_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT5_ENABLE   1
-+
-+/* DD_INT_SENSE property, NEG_BIT6 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT6_LSB         6
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT6_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT6_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT6_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT6_ENABLE   1
-+
-+/* DD_INT_SENSE property, NEG_BIT7 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT7_LSB         7
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT7_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT7_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT7_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_NEG_BIT7_ENABLE   1
-+
-+/* DD_INT_SENSE property, POS_BIT0 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT0_LSB         8
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT0_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT0_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT0_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT0_ENABLE   1
-+
-+/* DD_INT_SENSE property, POS_BIT1 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT1_LSB         9
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT1_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT1_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT1_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT1_ENABLE   1
-+
-+/* DD_INT_SENSE property, POS_BIT2 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT2_LSB         10
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT2_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT2_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT2_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT2_ENABLE   1
-+
-+/* DD_INT_SENSE property, POS_BIT3 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT3_LSB         11
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT3_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT3_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT3_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT3_ENABLE   1
-+
-+/* DD_INT_SENSE property, POS_BIT4 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT4_LSB         12
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT4_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT4_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT4_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT4_ENABLE   1
-+
-+/* DD_INT_SENSE property, POS_BIT5 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT5_LSB         13
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT5_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT5_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT5_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT5_ENABLE   1
-+
-+/* DD_INT_SENSE property, POS_BIT6 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT6_LSB         14
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT6_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT6_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT6_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT6_ENABLE   1
-+
-+/* DD_INT_SENSE property, POS_BIT7 field definition (NO TITLE)*/
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT7_LSB         15
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT7_MASK        0x01
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT7_DEFAULT    0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT7_DISABLE  0
-+#define Si2168B_DD_INT_SENSE_PROP_POS_BIT7_ENABLE   1
-+
-+#endif /* Si2168B_DD_INT_SENSE_PROP */
-+
-+/* Si2168B DD_MODE property definition */
-+#define Si2168B_DD_MODE_PROP 0x100a
-+
-+#ifdef Si2168B_DD_MODE_PROP
-+#define Si2168B_DD_MODE_PROP_CODE 0x00100a
-+
-+typedef struct { /* Si2168B_DD_MODE_PROP_struct */
-+	u8  auto_detect;
-+	u8  bw;
-+	u8  invert_spectrum;
-+	u8  modulation;
-+} Si2168B_DD_MODE_PROP_struct;
-+
-+/* DD_MODE property, AUTO_DETECT field definition (NO TITLE)*/
-+#define Si2168B_DD_MODE_PROP_AUTO_DETECT_LSB         9
-+#define Si2168B_DD_MODE_PROP_AUTO_DETECT_MASK        0x07
-+#define Si2168B_DD_MODE_PROP_AUTO_DETECT_DEFAULT    0
-+#define Si2168B_DD_MODE_PROP_AUTO_DETECT_NONE               0
-+#define Si2168B_DD_MODE_PROP_AUTO_DETECT_AUTO_DVB_T_T2      1
-+#define Si2168B_DD_MODE_PROP_AUTO_DETECT_AUTO_DVB_S_S2      2
-+#define Si2168B_DD_MODE_PROP_AUTO_DETECT_AUTO_DVB_S_S2_DSS  3
-+
-+/* DD_MODE property, BW field definition (NO TITLE)*/
-+#define Si2168B_DD_MODE_PROP_BW_LSB         0
-+#define Si2168B_DD_MODE_PROP_BW_MASK        0x0f
-+#define Si2168B_DD_MODE_PROP_BW_DEFAULT    8
-+#define Si2168B_DD_MODE_PROP_BW_BW_5MHZ    5
-+#define Si2168B_DD_MODE_PROP_BW_BW_6MHZ    6
-+#define Si2168B_DD_MODE_PROP_BW_BW_7MHZ    7
-+#define Si2168B_DD_MODE_PROP_BW_BW_8MHZ    8
-+#define Si2168B_DD_MODE_PROP_BW_BW_1D7MHZ  2
-+
-+/* DD_MODE property, INVERT_SPECTRUM field definition (NO TITLE)*/
-+#define Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_LSB         8
-+#define Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_MASK        0x01
-+#define Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_DEFAULT    0
-+#define Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_NORMAL    0
-+#define Si2168B_DD_MODE_PROP_INVERT_SPECTRUM_INVERTED  1
-+
-+/* DD_MODE property, MODULATION field definition (NO TITLE)*/
-+#define Si2168B_DD_MODE_PROP_MODULATION_LSB         4
-+#define Si2168B_DD_MODE_PROP_MODULATION_MASK        0x0f
-+#define Si2168B_DD_MODE_PROP_MODULATION_DEFAULT    2
-+#define Si2168B_DD_MODE_PROP_MODULATION_MCNS         1
-+#define Si2168B_DD_MODE_PROP_MODULATION_DVBT         2
-+#define Si2168B_DD_MODE_PROP_MODULATION_DVBC         3
-+#define Si2168B_DD_MODE_PROP_MODULATION_DVBT2        7
-+#define Si2168B_DD_MODE_PROP_MODULATION_DVBS         8
-+#define Si2168B_DD_MODE_PROP_MODULATION_DVBS2        9
-+#define Si2168B_DD_MODE_PROP_MODULATION_DSS          10
-+#define Si2168B_DD_MODE_PROP_MODULATION_DVBC2        11
-+#define Si2168B_DD_MODE_PROP_MODULATION_AUTO_DETECT  15
-+#define Si2168B_DD_MODE_PROP_MODULATION_ANALOG     100
-+/* new mode definition to set SLEEP mode */
-+#define Si2168B_DD_MODE_PROP_MODULATION_SLEEP      0xFF
-+
-+#endif /* Si2168B_DD_MODE_PROP */
-+
-+/* Si2168B DD_PER_RESOL property definition */
-+#define Si2168B_DD_PER_RESOL_PROP 0x1004
-+
-+#ifdef Si2168B_DD_PER_RESOL_PROP
-+#define Si2168B_DD_PER_RESOL_PROP_CODE 0x001004
-+
-+typedef struct { /* Si2168B_DD_PER_RESOL_PROP_struct */
-+	u8  exp;
-+	u8  mant;
-+} Si2168B_DD_PER_RESOL_PROP_struct;
-+
-+/* DD_PER_RESOL property, EXP field definition (NO TITLE)*/
-+#define Si2168B_DD_PER_RESOL_PROP_EXP_LSB         0
-+#define Si2168B_DD_PER_RESOL_PROP_EXP_MASK        0x0f
-+#define Si2168B_DD_PER_RESOL_PROP_EXP_DEFAULT    5
-+#define Si2168B_DD_PER_RESOL_PROP_EXP_EXPLO_MIN  1
-+#define Si2168B_DD_PER_RESOL_PROP_EXP_EXPLO_MAX  9
-+
-+/* DD_PER_RESOL property, MANT field definition (NO TITLE)*/
-+#define Si2168B_DD_PER_RESOL_PROP_MANT_LSB         4
-+#define Si2168B_DD_PER_RESOL_PROP_MANT_MASK        0x0f
-+#define Si2168B_DD_PER_RESOL_PROP_MANT_DEFAULT    1
-+#define Si2168B_DD_PER_RESOL_PROP_MANT_MANTLO_MIN  1
-+#define Si2168B_DD_PER_RESOL_PROP_MANT_MANTLO_MAX  9
-+
-+#endif /* Si2168B_DD_PER_RESOL_PROP */
-+
-+/* Si2168B DD_RSQ_BER_THRESHOLD property definition */
-+#define Si2168B_DD_RSQ_BER_THRESHOLD_PROP 0x1005
-+
-+#ifdef Si2168B_DD_RSQ_BER_THRESHOLD_PROP
-+#define Si2168B_DD_RSQ_BER_THRESHOLD_PROP_CODE 0x001005
-+
-+typedef struct { /* Si2168B_DD_RSQ_BER_THRESHOLD_PROP_struct */
-+	u8  exp;
-+	u8  mant;
-+} Si2168B_DD_RSQ_BER_THRESHOLD_PROP_struct;
-+
-+/* DD_RSQ_BER_THRESHOLD property, EXP field definition (NO TITLE)*/
-+#define Si2168B_DD_RSQ_BER_THRESHOLD_PROP_EXP_LSB         0
-+#define Si2168B_DD_RSQ_BER_THRESHOLD_PROP_EXP_MASK        0x0f
-+#define Si2168B_DD_RSQ_BER_THRESHOLD_PROP_EXP_DEFAULT    1
-+#define Si2168B_DD_RSQ_BER_THRESHOLD_PROP_EXP_EXP_MIN  1
-+#define Si2168B_DD_RSQ_BER_THRESHOLD_PROP_EXP_EXP_MAX  8
-+
-+/* DD_RSQ_BER_THRESHOLD property, MANT field definition (NO TITLE)*/
-+#define Si2168B_DD_RSQ_BER_THRESHOLD_PROP_MANT_LSB         4
-+#define Si2168B_DD_RSQ_BER_THRESHOLD_PROP_MANT_MASK        0x0f
-+#define Si2168B_DD_RSQ_BER_THRESHOLD_PROP_MANT_DEFAULT    10
-+#define Si2168B_DD_RSQ_BER_THRESHOLD_PROP_MANT_MANT_MIN  0
-+#define Si2168B_DD_RSQ_BER_THRESHOLD_PROP_MANT_MANT_MAX  99
-+
-+#endif /* Si2168B_DD_RSQ_BER_THRESHOLD_PROP */
-+
-+/* Si2168B DD_SSI_SQI_PARAM property definition */
-+#define Si2168B_DD_SSI_SQI_PARAM_PROP 0x100f
-+
-+#ifdef Si2168B_DD_SSI_SQI_PARAM_PROP
-+#define Si2168B_DD_SSI_SQI_PARAM_PROP_CODE 0x00100f
-+
-+typedef struct { /* Si2168B_DD_SSI_SQI_PARAM_PROP_struct */
-+	u8  sqi_average;
-+} Si2168B_DD_SSI_SQI_PARAM_PROP_struct;
-+
-+/* DD_SSI_SQI_PARAM property, SQI_AVERAGE field definition (NO TITLE)*/
-+#define Si2168B_DD_SSI_SQI_PARAM_PROP_SQI_AVERAGE_LSB         0
-+#define Si2168B_DD_SSI_SQI_PARAM_PROP_SQI_AVERAGE_MASK        0x1f
-+#define Si2168B_DD_SSI_SQI_PARAM_PROP_SQI_AVERAGE_DEFAULT    1
-+#define Si2168B_DD_SSI_SQI_PARAM_PROP_SQI_AVERAGE_SQI_AVERAGE_MIN  1
-+#define Si2168B_DD_SSI_SQI_PARAM_PROP_SQI_AVERAGE_SQI_AVERAGE_MAX  30
-+
-+#endif /* Si2168B_DD_SSI_SQI_PARAM_PROP */
-+
-+/* Si2168B DD_TS_FREQ property definition */
-+#define Si2168B_DD_TS_FREQ_PROP 0x100d
-+
-+#ifdef Si2168B_DD_TS_FREQ_PROP
-+#define Si2168B_DD_TS_FREQ_PROP_CODE 0x00100d
-+
-+typedef struct { /* Si2168B_DD_TS_FREQ_PROP_struct */
-+	u16 req_freq_10khz;
-+} Si2168B_DD_TS_FREQ_PROP_struct;
-+
-+/* DD_TS_FREQ property, REQ_FREQ_10KHZ field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_FREQ_PROP_REQ_FREQ_10KHZ_LSB         0
-+#define Si2168B_DD_TS_FREQ_PROP_REQ_FREQ_10KHZ_MASK        0x3fff
-+#define Si2168B_DD_TS_FREQ_PROP_REQ_FREQ_10KHZ_DEFAULT    720
-+#define Si2168B_DD_TS_FREQ_PROP_REQ_FREQ_10KHZ_REQ_FREQ_10KHZ_MIN  0
-+#define Si2168B_DD_TS_FREQ_PROP_REQ_FREQ_10KHZ_REQ_FREQ_10KHZ_MAX  14550
-+
-+#endif /* Si2168B_DD_TS_FREQ_PROP */
-+
-+/* Si2168B DD_TS_MODE property definition */
-+#define Si2168B_DD_TS_MODE_PROP 0x1001
-+
-+#ifdef Si2168B_DD_TS_MODE_PROP
-+#define Si2168B_DD_TS_MODE_PROP_CODE 0x001001
-+
-+typedef struct { /* Si2168B_DD_TS_MODE_PROP_struct */
-+	u8  clk_gapped_en;
-+	u8  clock;
-+	u8  mode;
-+	u8  special;
-+	u8  ts_err_polarity;
-+	u8  ts_freq_resolution;
-+} Si2168B_DD_TS_MODE_PROP_struct;
-+
-+/* DD_TS_MODE property, CLK_GAPPED_EN field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_MODE_PROP_CLK_GAPPED_EN_LSB         6
-+#define Si2168B_DD_TS_MODE_PROP_CLK_GAPPED_EN_MASK        0x01
-+#define Si2168B_DD_TS_MODE_PROP_CLK_GAPPED_EN_DEFAULT    0
-+#define Si2168B_DD_TS_MODE_PROP_CLK_GAPPED_EN_DISABLED  0
-+#define Si2168B_DD_TS_MODE_PROP_CLK_GAPPED_EN_ENABLED   1
-+
-+/* DD_TS_MODE property, CLOCK field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_MODE_PROP_CLOCK_LSB         4
-+#define Si2168B_DD_TS_MODE_PROP_CLOCK_MASK        0x03
-+#define Si2168B_DD_TS_MODE_PROP_CLOCK_DEFAULT    0
-+#define Si2168B_DD_TS_MODE_PROP_CLOCK_AUTO_FIXED  0
-+#define Si2168B_DD_TS_MODE_PROP_CLOCK_AUTO_ADAPT  1
-+#define Si2168B_DD_TS_MODE_PROP_CLOCK_MANUAL      2
-+
-+/* DD_TS_MODE property, MODE field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_MODE_PROP_MODE_LSB         0
-+#define Si2168B_DD_TS_MODE_PROP_MODE_MASK        0x0f
-+#define Si2168B_DD_TS_MODE_PROP_MODE_DEFAULT    0
-+#define Si2168B_DD_TS_MODE_PROP_MODE_TRISTATE  0
-+#define Si2168B_DD_TS_MODE_PROP_MODE_OFF       1
-+#define Si2168B_DD_TS_MODE_PROP_MODE_SERIAL    3
-+#define Si2168B_DD_TS_MODE_PROP_MODE_PARALLEL  6
-+#define Si2168B_DD_TS_MODE_PROP_MODE_GPIF      7
-+
-+/* DD_TS_MODE property, SPECIAL field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_MODE_PROP_SPECIAL_LSB         8
-+#define Si2168B_DD_TS_MODE_PROP_SPECIAL_MASK        0x03
-+#define Si2168B_DD_TS_MODE_PROP_SPECIAL_DEFAULT    0
-+#define Si2168B_DD_TS_MODE_PROP_SPECIAL_FULL_TS         0
-+#define Si2168B_DD_TS_MODE_PROP_SPECIAL_DATAS_TRISTATE  1
-+
-+/* DD_TS_MODE property, TS_ERR_POLARITY field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_MODE_PROP_TS_ERR_POLARITY_LSB         7
-+#define Si2168B_DD_TS_MODE_PROP_TS_ERR_POLARITY_MASK        0x01
-+#define Si2168B_DD_TS_MODE_PROP_TS_ERR_POLARITY_DEFAULT    0
-+#define Si2168B_DD_TS_MODE_PROP_TS_ERR_POLARITY_NOT_INVERTED  0
-+#define Si2168B_DD_TS_MODE_PROP_TS_ERR_POLARITY_INVERTED      1
-+
-+/* DD_TS_MODE property, TS_FREQ_RESOLUTION field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_MODE_PROP_TS_FREQ_RESOLUTION_LSB         10
-+#define Si2168B_DD_TS_MODE_PROP_TS_FREQ_RESOLUTION_MASK        0x01
-+#define Si2168B_DD_TS_MODE_PROP_TS_FREQ_RESOLUTION_DEFAULT    0
-+#define Si2168B_DD_TS_MODE_PROP_TS_FREQ_RESOLUTION_NORMAL  0
-+#define Si2168B_DD_TS_MODE_PROP_TS_FREQ_RESOLUTION_FINE    1
-+
-+#endif /* Si2168B_DD_TS_MODE_PROP */
-+
-+/* Si2168B DD_TS_SERIAL_DIFF property definition */
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP 0x1012
-+
-+#ifdef Si2168B_DD_TS_SERIAL_DIFF_PROP
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_CODE 0x001012
-+
-+typedef struct { /* Si2168B_DD_TS_SERIAL_DIFF_PROP_struct */
-+	u8  ts_clkb_on_data1;
-+	u8  ts_data0b_on_data2;
-+	u8  ts_data1_shape;
-+	u8  ts_data1_strength;
-+	u8  ts_data2_shape;
-+	u8  ts_data2_strength;
-+} Si2168B_DD_TS_SERIAL_DIFF_PROP_struct;
-+
-+/* DD_TS_SERIAL_DIFF property, TS_CLKB_ON_DATA1 field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_CLKB_ON_DATA1_LSB         12
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_CLKB_ON_DATA1_MASK        0x01
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_CLKB_ON_DATA1_DEFAULT    0
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_CLKB_ON_DATA1_DISABLE  0
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_CLKB_ON_DATA1_ENABLE   1
-+
-+/* DD_TS_SERIAL_DIFF property, TS_DATA0B_ON_DATA2 field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA0B_ON_DATA2_LSB         13
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA0B_ON_DATA2_MASK        0x01
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA0B_ON_DATA2_DEFAULT    0
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA0B_ON_DATA2_DISABLE  0
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA0B_ON_DATA2_ENABLE   1
-+
-+/* DD_TS_SERIAL_DIFF property, TS_DATA1_SHAPE field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA1_SHAPE_LSB         4
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA1_SHAPE_MASK        0x03
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA1_SHAPE_DEFAULT    3
-+/* DD_TS_SERIAL_DIFF property, TS_DATA1_STRENGTH field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA1_STRENGTH_LSB         0
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA1_STRENGTH_MASK        0x0f
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA1_STRENGTH_DEFAULT    15
-+/* DD_TS_SERIAL_DIFF property, TS_DATA2_SHAPE field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA2_SHAPE_LSB         10
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA2_SHAPE_MASK        0x03
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA2_SHAPE_DEFAULT    3
-+/* DD_TS_SERIAL_DIFF property, TS_DATA2_STRENGTH field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA2_STRENGTH_LSB         6
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA2_STRENGTH_MASK        0x0f
-+#define Si2168B_DD_TS_SERIAL_DIFF_PROP_TS_DATA2_STRENGTH_DEFAULT    15
-+#endif /* Si2168B_DD_TS_SERIAL_DIFF_PROP */
-+
-+/* Si2168B DD_TS_SETUP_PAR property definition */
-+#define Si2168B_DD_TS_SETUP_PAR_PROP 0x1009
-+
-+#ifdef Si2168B_DD_TS_SETUP_PAR_PROP
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_CODE 0x001009
-+
-+typedef struct { /* Si2168B_DD_TS_SETUP_PAR_PROP_struct */
-+	u8  ts_clk_invert;
-+	u8  ts_clk_shape;
-+	u8  ts_clk_shift;
-+	u8  ts_clk_strength;
-+	u8  ts_data_shape;
-+	u8  ts_data_strength;
-+} Si2168B_DD_TS_SETUP_PAR_PROP_struct;
-+
-+/* DD_TS_SETUP_PAR property, TS_CLK_INVERT field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_INVERT_LSB         12
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_INVERT_MASK        0x01
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_INVERT_DEFAULT    1
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_INVERT_NOT_INVERTED  0
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_INVERT_INVERTED      1
-+
-+/* DD_TS_SETUP_PAR property, TS_CLK_SHAPE field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHAPE_LSB         10
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHAPE_MASK        0x03
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHAPE_DEFAULT    1
-+/* DD_TS_SETUP_PAR property, TS_CLK_SHIFT field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHIFT_LSB         13
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHIFT_MASK        0x07
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_SHIFT_DEFAULT    0
-+/* DD_TS_SETUP_PAR property, TS_CLK_STRENGTH field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_STRENGTH_LSB         6
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_STRENGTH_MASK        0x0f
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_CLK_STRENGTH_DEFAULT    3
-+/* DD_TS_SETUP_PAR property, TS_DATA_SHAPE field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_SHAPE_LSB         4
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_SHAPE_MASK        0x03
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_SHAPE_DEFAULT    1
-+/* DD_TS_SETUP_PAR property, TS_DATA_STRENGTH field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_STRENGTH_LSB         0
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_STRENGTH_MASK        0x0f
-+#define Si2168B_DD_TS_SETUP_PAR_PROP_TS_DATA_STRENGTH_DEFAULT    3
-+#endif /* Si2168B_DD_TS_SETUP_PAR_PROP */
-+
-+/* Si2168B DD_TS_SETUP_SER property definition */
-+#define Si2168B_DD_TS_SETUP_SER_PROP 0x1008
-+
-+#ifdef Si2168B_DD_TS_SETUP_SER_PROP
-+#define Si2168B_DD_TS_SETUP_SER_PROP_CODE 0x001008
-+
-+typedef struct { /* Si2168B_DD_TS_SETUP_SER_PROP_struct */
-+	u8  ts_byte_order;
-+	u8  ts_clk_invert;
-+	u8  ts_clk_shape;
-+	u8  ts_clk_strength;
-+	u8  ts_data_shape;
-+	u8  ts_data_strength;
-+	u8  ts_sync_duration;
-+} Si2168B_DD_TS_SETUP_SER_PROP_struct;
-+
-+/* DD_TS_SETUP_SER property, TS_BYTE_ORDER field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_BYTE_ORDER_LSB         14
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_BYTE_ORDER_MASK        0x01
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_BYTE_ORDER_DEFAULT    0
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_BYTE_ORDER_MSB_FIRST  0
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_BYTE_ORDER_LSB_FIRST  1
-+
-+/* DD_TS_SETUP_SER property, TS_CLK_INVERT field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_INVERT_LSB         12
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_INVERT_MASK        0x01
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_INVERT_DEFAULT    1
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_INVERT_NOT_INVERTED  0
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_INVERT_INVERTED      1
-+
-+/* DD_TS_SETUP_SER property, TS_CLK_SHAPE field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_SHAPE_LSB         10
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_SHAPE_MASK        0x03
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_SHAPE_DEFAULT    3
-+/* DD_TS_SETUP_SER property, TS_CLK_STRENGTH field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_STRENGTH_LSB         6
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_STRENGTH_MASK        0x0f
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_CLK_STRENGTH_DEFAULT    15
-+/* DD_TS_SETUP_SER property, TS_DATA_SHAPE field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_DATA_SHAPE_LSB         4
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_DATA_SHAPE_MASK        0x03
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_DATA_SHAPE_DEFAULT    3
-+/* DD_TS_SETUP_SER property, TS_DATA_STRENGTH field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_DATA_STRENGTH_LSB         0
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_DATA_STRENGTH_MASK        0x0f
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_DATA_STRENGTH_DEFAULT    15
-+/* DD_TS_SETUP_SER property, TS_SYNC_DURATION field definition (NO TITLE)*/
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_SYNC_DURATION_LSB         13
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_SYNC_DURATION_MASK        0x01
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_SYNC_DURATION_DEFAULT    0
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_SYNC_DURATION_FIRST_BYTE  0
-+#define Si2168B_DD_TS_SETUP_SER_PROP_TS_SYNC_DURATION_FIRST_BIT   1
-+
-+#endif /* Si2168B_DD_TS_SETUP_SER_PROP */
-+
-+/* Si2168B DVBC_ADC_CREST_FACTOR property definition */
-+#define Si2168B_DVBC_ADC_CREST_FACTOR_PROP 0x1104
-+
-+#ifdef Si2168B_DVBC_ADC_CREST_FACTOR_PROP
-+#define Si2168B_DVBC_ADC_CREST_FACTOR_PROP_CODE 0x001104
-+
-+typedef struct { /* Si2168B_DVBC_ADC_CREST_FACTOR_PROP_struct */
-+	u8  crest_factor;
-+} Si2168B_DVBC_ADC_CREST_FACTOR_PROP_struct;
-+
-+/* DVBC_ADC_CREST_FACTOR property, CREST_FACTOR field definition (NO TITLE)*/
-+#define Si2168B_DVBC_ADC_CREST_FACTOR_PROP_CREST_FACTOR_LSB         0
-+#define Si2168B_DVBC_ADC_CREST_FACTOR_PROP_CREST_FACTOR_MASK        0xff
-+#define Si2168B_DVBC_ADC_CREST_FACTOR_PROP_CREST_FACTOR_DEFAULT    112
-+#endif /* Si2168B_DVBC_ADC_CREST_FACTOR_PROP */
-+
-+/* Si2168B DVBC_AFC_RANGE property definition */
-+#define Si2168B_DVBC_AFC_RANGE_PROP 0x1103
-+
-+#ifdef Si2168B_DVBC_AFC_RANGE_PROP
-+#define Si2168B_DVBC_AFC_RANGE_PROP_CODE 0x001103
-+
-+typedef struct { /* Si2168B_DVBC_AFC_RANGE_PROP_struct */
-+	u16 range_khz;
-+} Si2168B_DVBC_AFC_RANGE_PROP_struct;
-+
-+/* DVBC_AFC_RANGE property, RANGE_KHZ field definition (NO TITLE)*/
-+#define Si2168B_DVBC_AFC_RANGE_PROP_RANGE_KHZ_LSB         0
-+#define Si2168B_DVBC_AFC_RANGE_PROP_RANGE_KHZ_MASK        0xffff
-+#define Si2168B_DVBC_AFC_RANGE_PROP_RANGE_KHZ_DEFAULT    100
-+#endif /* Si2168B_DVBC_AFC_RANGE_PROP */
-+
-+/* Si2168B DVBC_CONSTELLATION property definition */
-+#define Si2168B_DVBC_CONSTELLATION_PROP 0x1101
-+
-+#ifdef Si2168B_DVBC_CONSTELLATION_PROP
-+#define Si2168B_DVBC_CONSTELLATION_PROP_CODE 0x001101
-+
-+typedef struct { /* Si2168B_DVBC_CONSTELLATION_PROP_struct */
-+	u8  constellation;
-+} Si2168B_DVBC_CONSTELLATION_PROP_struct;
-+
-+/* DVBC_CONSTELLATION property, CONSTELLATION field definition (NO TITLE)*/
-+#define Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_LSB         0
-+#define Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_MASK        0x3f
-+#define Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_DEFAULT    0
-+#define Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_AUTO    0
-+#define Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM16   7
-+#define Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM32   8
-+#define Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM64   9
-+#define Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM128  10
-+#define Si2168B_DVBC_CONSTELLATION_PROP_CONSTELLATION_QAM256  11
-+
-+#endif /* Si2168B_DVBC_CONSTELLATION_PROP */
-+
-+/* Si2168B DVBC_SYMBOL_RATE property definition */
-+#define Si2168B_DVBC_SYMBOL_RATE_PROP 0x1102
-+
-+#ifdef Si2168B_DVBC_SYMBOL_RATE_PROP
-+#define Si2168B_DVBC_SYMBOL_RATE_PROP_CODE 0x001102
-+
-+typedef struct { /* Si2168B_DVBC_SYMBOL_RATE_PROP_struct */
-+	u16 rate;
-+} Si2168B_DVBC_SYMBOL_RATE_PROP_struct;
-+
-+/* DVBC_SYMBOL_RATE property, RATE field definition (NO TITLE)*/
-+#define Si2168B_DVBC_SYMBOL_RATE_PROP_RATE_LSB         0
-+#define Si2168B_DVBC_SYMBOL_RATE_PROP_RATE_MASK        0xffff
-+#define Si2168B_DVBC_SYMBOL_RATE_PROP_RATE_DEFAULT    6900
-+#endif /* Si2168B_DVBC_SYMBOL_RATE_PROP */
-+
-+/* Si2168B DVBT2_ADC_CREST_FACTOR property definition */
-+#define Si2168B_DVBT2_ADC_CREST_FACTOR_PROP 0x1303
-+
-+#ifdef Si2168B_DVBT2_ADC_CREST_FACTOR_PROP
-+#define Si2168B_DVBT2_ADC_CREST_FACTOR_PROP_CODE 0x001303
-+
-+typedef struct { /* Si2168B_DVBT2_ADC_CREST_FACTOR_PROP_struct */
-+	u8  crest_factor;
-+} Si2168B_DVBT2_ADC_CREST_FACTOR_PROP_struct;
-+
-+/* DVBT2_ADC_CREST_FACTOR property, CREST_FACTOR field definition (NO TITLE)*/
-+#define Si2168B_DVBT2_ADC_CREST_FACTOR_PROP_CREST_FACTOR_LSB         0
-+#define Si2168B_DVBT2_ADC_CREST_FACTOR_PROP_CREST_FACTOR_MASK        0xff
-+#define Si2168B_DVBT2_ADC_CREST_FACTOR_PROP_CREST_FACTOR_DEFAULT    130
-+#endif /* Si2168B_DVBT2_ADC_CREST_FACTOR_PROP */
-+
-+/* Si2168B DVBT2_AFC_RANGE property definition */
-+#define Si2168B_DVBT2_AFC_RANGE_PROP 0x1301
-+
-+#ifdef Si2168B_DVBT2_AFC_RANGE_PROP
-+#define Si2168B_DVBT2_AFC_RANGE_PROP_CODE 0x001301
-+
-+typedef struct { /* Si2168B_DVBT2_AFC_RANGE_PROP_struct */
-+	u16 range_khz;
-+} Si2168B_DVBT2_AFC_RANGE_PROP_struct;
-+
-+/* DVBT2_AFC_RANGE property, RANGE_KHZ field definition (NO TITLE)*/
-+#define Si2168B_DVBT2_AFC_RANGE_PROP_RANGE_KHZ_LSB         0
-+#define Si2168B_DVBT2_AFC_RANGE_PROP_RANGE_KHZ_MASK        0xffff
-+#define Si2168B_DVBT2_AFC_RANGE_PROP_RANGE_KHZ_DEFAULT    550
-+#endif /* Si2168B_DVBT2_AFC_RANGE_PROP */
-+
-+/* Si2168B DVBT2_FEF_TUNER property definition */
-+#define Si2168B_DVBT2_FEF_TUNER_PROP 0x1302
-+
-+#ifdef Si2168B_DVBT2_FEF_TUNER_PROP
-+#define Si2168B_DVBT2_FEF_TUNER_PROP_CODE 0x001302
-+
-+typedef struct { /* Si2168B_DVBT2_FEF_TUNER_PROP_struct */
-+	u8  tuner_delay;
-+	u8  tuner_freeze_time;
-+	u8  tuner_unfreeze_time;
-+} Si2168B_DVBT2_FEF_TUNER_PROP_struct;
-+
-+/* DVBT2_FEF_TUNER property, TUNER_DELAY field definition (NO TITLE)*/
-+#define Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_DELAY_LSB         0
-+#define Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_DELAY_MASK        0xff
-+#define Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_DELAY_DEFAULT    1
-+/* DVBT2_FEF_TUNER property, TUNER_FREEZE_TIME field definition (NO TITLE)*/
-+#define Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_FREEZE_TIME_LSB         8
-+#define Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_FREEZE_TIME_MASK        0x0f
-+#define Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_FREEZE_TIME_DEFAULT    1
-+/* DVBT2_FEF_TUNER property, TUNER_UNFREEZE_TIME field definition (NO TITLE)*/
-+#define Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_UNFREEZE_TIME_LSB         12
-+#define Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_UNFREEZE_TIME_MASK        0x0f
-+#define Si2168B_DVBT2_FEF_TUNER_PROP_TUNER_UNFREEZE_TIME_DEFAULT    1
-+#endif /* Si2168B_DVBT2_FEF_TUNER_PROP */
-+
-+/* Si2168B DVBT2_MODE property definition */
-+#define Si2168B_DVBT2_MODE_PROP 0x1304
-+
-+#ifdef Si2168B_DVBT2_MODE_PROP
-+#define Si2168B_DVBT2_MODE_PROP_CODE 0x001304
-+
-+typedef struct { /* Si2168B_DVBT2_MODE_PROP_struct */
-+	u8  lock_mode;
-+} Si2168B_DVBT2_MODE_PROP_struct;
-+
-+/* DVBT2_MODE property, LOCK_MODE field definition (NO TITLE)*/
-+#define Si2168B_DVBT2_MODE_PROP_LOCK_MODE_LSB         0
-+#define Si2168B_DVBT2_MODE_PROP_LOCK_MODE_MASK        0x03
-+#define Si2168B_DVBT2_MODE_PROP_LOCK_MODE_DEFAULT    0
-+#define Si2168B_DVBT2_MODE_PROP_LOCK_MODE_ANY        0
-+#define Si2168B_DVBT2_MODE_PROP_LOCK_MODE_BASE_ONLY  1
-+#define Si2168B_DVBT2_MODE_PROP_LOCK_MODE_LITE_ONLY  2
-+#define Si2168B_DVBT2_MODE_PROP_LOCK_MODE_RESERVED   3
-+
-+#endif /* Si2168B_DVBT2_MODE_PROP */
-+
-+/* Si2168B DVBT_ADC_CREST_FACTOR property definition */
-+#define Si2168B_DVBT_ADC_CREST_FACTOR_PROP 0x1203
-+
-+#ifdef Si2168B_DVBT_ADC_CREST_FACTOR_PROP
-+#define Si2168B_DVBT_ADC_CREST_FACTOR_PROP_CODE 0x001203
-+
-+typedef struct { /* Si2168B_DVBT_ADC_CREST_FACTOR_PROP_struct */
-+	u8  crest_factor;
-+} Si2168B_DVBT_ADC_CREST_FACTOR_PROP_struct;
-+
-+/* DVBT_ADC_CREST_FACTOR property, CREST_FACTOR field definition (NO TITLE)*/
-+#define Si2168B_DVBT_ADC_CREST_FACTOR_PROP_CREST_FACTOR_LSB         0
-+#define Si2168B_DVBT_ADC_CREST_FACTOR_PROP_CREST_FACTOR_MASK        0xff
-+#define Si2168B_DVBT_ADC_CREST_FACTOR_PROP_CREST_FACTOR_DEFAULT    130
-+#endif /* Si2168B_DVBT_ADC_CREST_FACTOR_PROP */
-+
-+/* Si2168B DVBT_AFC_RANGE property definition */
-+#define Si2168B_DVBT_AFC_RANGE_PROP 0x1202
-+
-+#ifdef Si2168B_DVBT_AFC_RANGE_PROP
-+#define Si2168B_DVBT_AFC_RANGE_PROP_CODE 0x001202
-+
-+typedef struct { /* Si2168B_DVBT_AFC_RANGE_PROP_struct */
-+	u16 range_khz;
-+} Si2168B_DVBT_AFC_RANGE_PROP_struct;
-+
-+/* DVBT_AFC_RANGE property, RANGE_KHZ field definition (NO TITLE)*/
-+#define Si2168B_DVBT_AFC_RANGE_PROP_RANGE_KHZ_LSB         0
-+#define Si2168B_DVBT_AFC_RANGE_PROP_RANGE_KHZ_MASK        0xffff
-+#define Si2168B_DVBT_AFC_RANGE_PROP_RANGE_KHZ_DEFAULT    550
-+#endif /* Si2168B_DVBT_AFC_RANGE_PROP */
-+
-+/* Si2168B DVBT_HIERARCHY property definition */
-+#define Si2168B_DVBT_HIERARCHY_PROP 0x1201
-+
-+#ifdef Si2168B_DVBT_HIERARCHY_PROP
-+#define Si2168B_DVBT_HIERARCHY_PROP_CODE 0x001201
-+
-+typedef struct { /* Si2168B_DVBT_HIERARCHY_PROP_struct */
-+	u8  stream;
-+} Si2168B_DVBT_HIERARCHY_PROP_struct;
-+
-+/* DVBT_HIERARCHY property, STREAM field definition (NO TITLE)*/
-+#define Si2168B_DVBT_HIERARCHY_PROP_STREAM_LSB         0
-+#define Si2168B_DVBT_HIERARCHY_PROP_STREAM_MASK        0x01
-+#define Si2168B_DVBT_HIERARCHY_PROP_STREAM_DEFAULT    0
-+#define Si2168B_DVBT_HIERARCHY_PROP_STREAM_HP  0
-+#define Si2168B_DVBT_HIERARCHY_PROP_STREAM_LP  1
-+
-+#endif /* Si2168B_DVBT_HIERARCHY_PROP */
-+
-+/* Si2168B MASTER_IEN property definition */
-+#define Si2168B_MASTER_IEN_PROP 0x0401
-+
-+#ifdef Si2168B_MASTER_IEN_PROP
-+#define Si2168B_MASTER_IEN_PROP_CODE 0x000401
-+
-+typedef struct { /* Si2168B_MASTER_IEN_PROP_struct */
-+	u8  ctsien;
-+	u8  ddien;
-+	u8  errien;
-+	u8  scanien;
-+} Si2168B_MASTER_IEN_PROP_struct;
-+
-+/* MASTER_IEN property, CTSIEN field definition (NO TITLE)*/
-+#define Si2168B_MASTER_IEN_PROP_CTSIEN_LSB         7
-+#define Si2168B_MASTER_IEN_PROP_CTSIEN_MASK        0x01
-+#define Si2168B_MASTER_IEN_PROP_CTSIEN_DEFAULT    0
-+#define Si2168B_MASTER_IEN_PROP_CTSIEN_OFF  0
-+#define Si2168B_MASTER_IEN_PROP_CTSIEN_ON   1
-+
-+/* MASTER_IEN property, DDIEN field definition (NO TITLE)*/
-+#define Si2168B_MASTER_IEN_PROP_DDIEN_LSB         0
-+#define Si2168B_MASTER_IEN_PROP_DDIEN_MASK        0x01
-+#define Si2168B_MASTER_IEN_PROP_DDIEN_DEFAULT    0
-+#define Si2168B_MASTER_IEN_PROP_DDIEN_OFF  0
-+#define Si2168B_MASTER_IEN_PROP_DDIEN_ON   1
-+
-+/* MASTER_IEN property, ERRIEN field definition (NO TITLE)*/
-+#define Si2168B_MASTER_IEN_PROP_ERRIEN_LSB         6
-+#define Si2168B_MASTER_IEN_PROP_ERRIEN_MASK        0x01
-+#define Si2168B_MASTER_IEN_PROP_ERRIEN_DEFAULT    0
-+#define Si2168B_MASTER_IEN_PROP_ERRIEN_OFF  0
-+#define Si2168B_MASTER_IEN_PROP_ERRIEN_ON   1
-+
-+/* MASTER_IEN property, SCANIEN field definition (NO TITLE)*/
-+#define Si2168B_MASTER_IEN_PROP_SCANIEN_LSB         1
-+#define Si2168B_MASTER_IEN_PROP_SCANIEN_MASK        0x01
-+#define Si2168B_MASTER_IEN_PROP_SCANIEN_DEFAULT    0
-+#define Si2168B_MASTER_IEN_PROP_SCANIEN_OFF  0
-+#define Si2168B_MASTER_IEN_PROP_SCANIEN_ON   1
-+
-+#endif /* Si2168B_MASTER_IEN_PROP */
-+
-+/* Si2168B MCNS_ADC_CREST_FACTOR property definition */
-+#define Si2168B_MCNS_ADC_CREST_FACTOR_PROP 0x1604
-+
-+#ifdef Si2168B_MCNS_ADC_CREST_FACTOR_PROP
-+#define Si2168B_MCNS_ADC_CREST_FACTOR_PROP_CODE 0x001604
-+
-+typedef struct { /* Si2168B_MCNS_ADC_CREST_FACTOR_PROP_struct */
-+	u8  crest_factor;
-+} Si2168B_MCNS_ADC_CREST_FACTOR_PROP_struct;
-+
-+/* MCNS_ADC_CREST_FACTOR property, CREST_FACTOR field definition (NO TITLE)*/
-+#define Si2168B_MCNS_ADC_CREST_FACTOR_PROP_CREST_FACTOR_LSB         0
-+#define Si2168B_MCNS_ADC_CREST_FACTOR_PROP_CREST_FACTOR_MASK        0xff
-+#define Si2168B_MCNS_ADC_CREST_FACTOR_PROP_CREST_FACTOR_DEFAULT    112
-+#endif /* Si2168B_MCNS_ADC_CREST_FACTOR_PROP */
-+
-+/* Si2168B MCNS_AFC_RANGE property definition */
-+#define Si2168B_MCNS_AFC_RANGE_PROP 0x1603
-+
-+#ifdef Si2168B_MCNS_AFC_RANGE_PROP
-+#define Si2168B_MCNS_AFC_RANGE_PROP_CODE 0x001603
-+
-+typedef struct { /* Si2168B_MCNS_AFC_RANGE_PROP_struct */
-+	u16 range_khz;
-+} Si2168B_MCNS_AFC_RANGE_PROP_struct;
-+
-+/* MCNS_AFC_RANGE property, RANGE_KHZ field definition (NO TITLE)*/
-+#define Si2168B_MCNS_AFC_RANGE_PROP_RANGE_KHZ_LSB         0
-+#define Si2168B_MCNS_AFC_RANGE_PROP_RANGE_KHZ_MASK        0xffff
-+#define Si2168B_MCNS_AFC_RANGE_PROP_RANGE_KHZ_DEFAULT    100
-+#endif /* Si2168B_MCNS_AFC_RANGE_PROP */
-+
-+/* Si2168B MCNS_CONSTELLATION property definition */
-+#define Si2168B_MCNS_CONSTELLATION_PROP 0x1601
-+
-+#ifdef Si2168B_MCNS_CONSTELLATION_PROP
-+#define Si2168B_MCNS_CONSTELLATION_PROP_CODE 0x001601
-+
-+typedef struct { /* Si2168B_MCNS_CONSTELLATION_PROP_struct */
-+	u8  constellation;
-+} Si2168B_MCNS_CONSTELLATION_PROP_struct;
-+
-+/* MCNS_CONSTELLATION property, CONSTELLATION field definition (NO TITLE)*/
-+#define Si2168B_MCNS_CONSTELLATION_PROP_CONSTELLATION_LSB         0
-+#define Si2168B_MCNS_CONSTELLATION_PROP_CONSTELLATION_MASK        0x3f
-+#define Si2168B_MCNS_CONSTELLATION_PROP_CONSTELLATION_DEFAULT    0
-+#define Si2168B_MCNS_CONSTELLATION_PROP_CONSTELLATION_AUTO    0
-+#define Si2168B_MCNS_CONSTELLATION_PROP_CONSTELLATION_QAM64   9
-+#define Si2168B_MCNS_CONSTELLATION_PROP_CONSTELLATION_QAM256  11
-+
-+#endif /* Si2168B_MCNS_CONSTELLATION_PROP */
-+
-+/* Si2168B MCNS_SYMBOL_RATE property definition */
-+#define Si2168B_MCNS_SYMBOL_RATE_PROP 0x1602
-+
-+#ifdef Si2168B_MCNS_SYMBOL_RATE_PROP
-+#define Si2168B_MCNS_SYMBOL_RATE_PROP_CODE 0x001602
-+
-+typedef struct { /* Si2168B_MCNS_SYMBOL_RATE_PROP_struct */
-+	u16 rate;
-+} Si2168B_MCNS_SYMBOL_RATE_PROP_struct;
-+
-+/* MCNS_SYMBOL_RATE property, RATE field definition (NO TITLE)*/
-+#define Si2168B_MCNS_SYMBOL_RATE_PROP_RATE_LSB         0
-+#define Si2168B_MCNS_SYMBOL_RATE_PROP_RATE_MASK        0xffff
-+#define Si2168B_MCNS_SYMBOL_RATE_PROP_RATE_DEFAULT    6900
-+#endif /* Si2168B_MCNS_SYMBOL_RATE_PROP */
-+
-+/* Si2168B SCAN_FMAX property definition */
-+#define Si2168B_SCAN_FMAX_PROP 0x0304
-+
-+#ifdef Si2168B_SCAN_FMAX_PROP
-+#define Si2168B_SCAN_FMAX_PROP_CODE 0x000304
-+
-+typedef struct { /* Si2168B_SCAN_FMAX_PROP_struct */
-+	u16 scan_fmax;
-+} Si2168B_SCAN_FMAX_PROP_struct;
-+
-+/* SCAN_FMAX property, SCAN_FMAX field definition (NO TITLE)*/
-+#define Si2168B_SCAN_FMAX_PROP_SCAN_FMAX_LSB         0
-+#define Si2168B_SCAN_FMAX_PROP_SCAN_FMAX_MASK        0xffff
-+#define Si2168B_SCAN_FMAX_PROP_SCAN_FMAX_DEFAULT    0
-+#endif /* Si2168B_SCAN_FMAX_PROP */
-+
-+/* Si2168B SCAN_FMIN property definition */
-+#define Si2168B_SCAN_FMIN_PROP 0x0303
-+
-+#ifdef Si2168B_SCAN_FMIN_PROP
-+#define Si2168B_SCAN_FMIN_PROP_CODE 0x000303
-+
-+typedef struct { /* Si2168B_SCAN_FMIN_PROP_struct */
-+	u16 scan_fmin;
-+} Si2168B_SCAN_FMIN_PROP_struct;
-+
-+/* SCAN_FMIN property, SCAN_FMIN field definition (NO TITLE)*/
-+#define Si2168B_SCAN_FMIN_PROP_SCAN_FMIN_LSB         0
-+#define Si2168B_SCAN_FMIN_PROP_SCAN_FMIN_MASK        0xffff
-+#define Si2168B_SCAN_FMIN_PROP_SCAN_FMIN_DEFAULT    0
-+#endif /* Si2168B_SCAN_FMIN_PROP */
-+
-+/* Si2168B SCAN_IEN property definition */
-+#define Si2168B_SCAN_IEN_PROP 0x0308
-+
-+#ifdef Si2168B_SCAN_IEN_PROP
-+#define Si2168B_SCAN_IEN_PROP_CODE 0x000308
-+
-+typedef struct { /* Si2168B_SCAN_IEN_PROP_struct */
-+	u8  buzien;
-+	u8  reqien;
-+} Si2168B_SCAN_IEN_PROP_struct;
-+
-+/* SCAN_IEN property, BUZIEN field definition (NO TITLE)*/
-+#define Si2168B_SCAN_IEN_PROP_BUZIEN_LSB         0
-+#define Si2168B_SCAN_IEN_PROP_BUZIEN_MASK        0x01
-+#define Si2168B_SCAN_IEN_PROP_BUZIEN_DEFAULT    0
-+#define Si2168B_SCAN_IEN_PROP_BUZIEN_DISABLE  0
-+#define Si2168B_SCAN_IEN_PROP_BUZIEN_ENABLE   1
-+
-+/* SCAN_IEN property, REQIEN field definition (NO TITLE)*/
-+#define Si2168B_SCAN_IEN_PROP_REQIEN_LSB         1
-+#define Si2168B_SCAN_IEN_PROP_REQIEN_MASK        0x01
-+#define Si2168B_SCAN_IEN_PROP_REQIEN_DEFAULT    0
-+#define Si2168B_SCAN_IEN_PROP_REQIEN_DISABLE  0
-+#define Si2168B_SCAN_IEN_PROP_REQIEN_ENABLE   1
-+
-+#endif /* Si2168B_SCAN_IEN_PROP */
-+
-+/* Si2168B SCAN_INT_SENSE property definition */
-+#define Si2168B_SCAN_INT_SENSE_PROP 0x0307
-+
-+#ifdef Si2168B_SCAN_INT_SENSE_PROP
-+#define Si2168B_SCAN_INT_SENSE_PROP_CODE 0x000307
-+
-+typedef struct { /* Si2168B_SCAN_INT_SENSE_PROP_struct */
-+	u8  buznegen;
-+	u8  buzposen;
-+	u8  reqnegen;
-+	u8  reqposen;
-+} Si2168B_SCAN_INT_SENSE_PROP_struct;
-+
-+/* SCAN_INT_SENSE property, BUZNEGEN field definition (NO TITLE)*/
-+#define Si2168B_SCAN_INT_SENSE_PROP_BUZNEGEN_LSB         0
-+#define Si2168B_SCAN_INT_SENSE_PROP_BUZNEGEN_MASK        0x01
-+#define Si2168B_SCAN_INT_SENSE_PROP_BUZNEGEN_DEFAULT    1
-+#define Si2168B_SCAN_INT_SENSE_PROP_BUZNEGEN_DISABLE  0
-+#define Si2168B_SCAN_INT_SENSE_PROP_BUZNEGEN_ENABLE   1
-+
-+/* SCAN_INT_SENSE property, BUZPOSEN field definition (NO TITLE)*/
-+#define Si2168B_SCAN_INT_SENSE_PROP_BUZPOSEN_LSB         8
-+#define Si2168B_SCAN_INT_SENSE_PROP_BUZPOSEN_MASK        0x01
-+#define Si2168B_SCAN_INT_SENSE_PROP_BUZPOSEN_DEFAULT    0
-+#define Si2168B_SCAN_INT_SENSE_PROP_BUZPOSEN_DISABLE  0
-+#define Si2168B_SCAN_INT_SENSE_PROP_BUZPOSEN_ENABLE   1
-+
-+/* SCAN_INT_SENSE property, REQNEGEN field definition (NO TITLE)*/
-+#define Si2168B_SCAN_INT_SENSE_PROP_REQNEGEN_LSB         1
-+#define Si2168B_SCAN_INT_SENSE_PROP_REQNEGEN_MASK        0x01
-+#define Si2168B_SCAN_INT_SENSE_PROP_REQNEGEN_DEFAULT    0
-+#define Si2168B_SCAN_INT_SENSE_PROP_REQNEGEN_DISABLE  0
-+#define Si2168B_SCAN_INT_SENSE_PROP_REQNEGEN_ENABLE   1
-+
-+/* SCAN_INT_SENSE property, REQPOSEN field definition (NO TITLE)*/
-+#define Si2168B_SCAN_INT_SENSE_PROP_REQPOSEN_LSB         9
-+#define Si2168B_SCAN_INT_SENSE_PROP_REQPOSEN_MASK        0x01
-+#define Si2168B_SCAN_INT_SENSE_PROP_REQPOSEN_DEFAULT    1
-+#define Si2168B_SCAN_INT_SENSE_PROP_REQPOSEN_DISABLE  0
-+#define Si2168B_SCAN_INT_SENSE_PROP_REQPOSEN_ENABLE   1
-+
-+#endif /* Si2168B_SCAN_INT_SENSE_PROP */
-+
-+/* Si2168B SCAN_SYMB_RATE_MAX property definition */
-+#define Si2168B_SCAN_SYMB_RATE_MAX_PROP 0x0306
-+
-+#ifdef Si2168B_SCAN_SYMB_RATE_MAX_PROP
-+#define Si2168B_SCAN_SYMB_RATE_MAX_PROP_CODE 0x000306
-+
-+typedef struct { /* Si2168B_SCAN_SYMB_RATE_MAX_PROP_struct */
-+	u16 scan_symb_rate_max;
-+} Si2168B_SCAN_SYMB_RATE_MAX_PROP_struct;
-+
-+/* SCAN_SYMB_RATE_MAX property, SCAN_SYMB_RATE_MAX field definition (NO TITLE)*/
-+#define Si2168B_SCAN_SYMB_RATE_MAX_PROP_SCAN_SYMB_RATE_MAX_LSB         0
-+#define Si2168B_SCAN_SYMB_RATE_MAX_PROP_SCAN_SYMB_RATE_MAX_MASK        0xffff
-+#define Si2168B_SCAN_SYMB_RATE_MAX_PROP_SCAN_SYMB_RATE_MAX_DEFAULT    0
-+#endif /* Si2168B_SCAN_SYMB_RATE_MAX_PROP */
-+
-+/* Si2168B SCAN_SYMB_RATE_MIN property definition */
-+#define Si2168B_SCAN_SYMB_RATE_MIN_PROP 0x0305
-+
-+#ifdef Si2168B_SCAN_SYMB_RATE_MIN_PROP
-+#define Si2168B_SCAN_SYMB_RATE_MIN_PROP_CODE 0x000305
-+
-+typedef struct { /* Si2168B_SCAN_SYMB_RATE_MIN_PROP_struct */
-+	u16 scan_symb_rate_min;
-+} Si2168B_SCAN_SYMB_RATE_MIN_PROP_struct;
-+
-+/* SCAN_SYMB_RATE_MIN property, SCAN_SYMB_RATE_MIN field definition (NO TITLE)*/
-+#define Si2168B_SCAN_SYMB_RATE_MIN_PROP_SCAN_SYMB_RATE_MIN_LSB         0
-+#define Si2168B_SCAN_SYMB_RATE_MIN_PROP_SCAN_SYMB_RATE_MIN_MASK        0xffff
-+#define Si2168B_SCAN_SYMB_RATE_MIN_PROP_SCAN_SYMB_RATE_MIN_DEFAULT    0
-+#endif /* Si2168B_SCAN_SYMB_RATE_MIN_PROP */
-+
-+/* Si2168B SCAN_TER_CONFIG property definition */
-+#define Si2168B_SCAN_TER_CONFIG_PROP 0x0301
-+
-+#ifdef Si2168B_SCAN_TER_CONFIG_PROP
-+#define Si2168B_SCAN_TER_CONFIG_PROP_CODE 0x000301
-+
-+typedef struct { /* Si2168B_SCAN_TER_CONFIG_PROP_struct */
-+	u8  analog_bw;
-+	u8  mode;
-+	u8  scan_debug;
-+	u8  search_analog;
-+} Si2168B_SCAN_TER_CONFIG_PROP_struct;
-+
-+/* SCAN_TER_CONFIG property, ANALOG_BW field definition (NO TITLE)*/
-+#define Si2168B_SCAN_TER_CONFIG_PROP_ANALOG_BW_LSB         2
-+#define Si2168B_SCAN_TER_CONFIG_PROP_ANALOG_BW_MASK        0x03
-+#define Si2168B_SCAN_TER_CONFIG_PROP_ANALOG_BW_DEFAULT    3
-+#define Si2168B_SCAN_TER_CONFIG_PROP_ANALOG_BW_6MHZ  1
-+#define Si2168B_SCAN_TER_CONFIG_PROP_ANALOG_BW_7MHZ  2
-+#define Si2168B_SCAN_TER_CONFIG_PROP_ANALOG_BW_8MHZ  3
-+
-+/* SCAN_TER_CONFIG property, MODE field definition (NO TITLE)*/
-+#define Si2168B_SCAN_TER_CONFIG_PROP_MODE_LSB         0
-+#define Si2168B_SCAN_TER_CONFIG_PROP_MODE_MASK        0x03
-+#define Si2168B_SCAN_TER_CONFIG_PROP_MODE_DEFAULT    0
-+#define Si2168B_SCAN_TER_CONFIG_PROP_MODE_BLIND_SCAN    0
-+#define Si2168B_SCAN_TER_CONFIG_PROP_MODE_MAPPING_SCAN  1
-+#define Si2168B_SCAN_TER_CONFIG_PROP_MODE_BLIND_LOCK    2
-+
-+/* SCAN_TER_CONFIG property, SCAN_DEBUG field definition (NO TITLE)*/
-+#define Si2168B_SCAN_TER_CONFIG_PROP_SCAN_DEBUG_LSB         12
-+#define Si2168B_SCAN_TER_CONFIG_PROP_SCAN_DEBUG_MASK        0x0f
-+#define Si2168B_SCAN_TER_CONFIG_PROP_SCAN_DEBUG_DEFAULT    0
-+/* SCAN_TER_CONFIG property, SEARCH_ANALOG field definition (NO TITLE)*/
-+#define Si2168B_SCAN_TER_CONFIG_PROP_SEARCH_ANALOG_LSB         4
-+#define Si2168B_SCAN_TER_CONFIG_PROP_SEARCH_ANALOG_MASK        0x01
-+#define Si2168B_SCAN_TER_CONFIG_PROP_SEARCH_ANALOG_DEFAULT    0
-+#define Si2168B_SCAN_TER_CONFIG_PROP_SEARCH_ANALOG_DISABLE  0
-+#define Si2168B_SCAN_TER_CONFIG_PROP_SEARCH_ANALOG_ENABLE   1
-+
-+#endif /* Si2168B_SCAN_TER_CONFIG_PROP */
-+
-+/* STATUS fields definition */
-+/* STATUS, DDINT field definition (address 0, size 1, lsb 0, unsigned)*/
-+#define Si2168B_STATUS_DDINT_LSB         0
-+#define Si2168B_STATUS_DDINT_MASK        0x01
-+#define Si2168B_STATUS_DDINT_NOT_TRIGGERED  0
-+#define Si2168B_STATUS_DDINT_TRIGGERED      1
-+/* STATUS, SCANINT field definition (address 0, size 1, lsb 1, unsigned)*/
-+#define Si2168B_STATUS_SCANINT_LSB         1
-+#define Si2168B_STATUS_SCANINT_MASK        0x01
-+#define Si2168B_STATUS_SCANINT_NOT_TRIGGERED  0
-+#define Si2168B_STATUS_SCANINT_TRIGGERED      1
-+/* STATUS, ERR field definition (address 0, size 1, lsb 6, unsigned)*/
-+#define Si2168B_STATUS_ERR_LSB         6
-+#define Si2168B_STATUS_ERR_MASK        0x01
-+#define Si2168B_STATUS_ERR_ERROR     1
-+#define Si2168B_STATUS_ERR_NO_ERROR  0
-+/* STATUS, CTS field definition (address 0, size 1, lsb 7, unsigned)*/
-+#define Si2168B_STATUS_CTS_LSB         7
-+#define Si2168B_STATUS_CTS_MASK        0x01
-+#define Si2168B_STATUS_CTS_COMPLETED  1
-+#define Si2168B_STATUS_CTS_WAIT       0
-+
-+/* Si2168B_CONFIG_CLKIO command definition */
-+#define Si2168B_CONFIG_CLKIO_CMD 0x18
-+
-+#ifdef Si2168B_CONFIG_CLKIO_CMD
-+#define Si2168B_CONFIG_CLKIO_CMD_CODE 0x010018
-+
-+typedef struct { /* Si2168B_CONFIG_CLKIO_CMD_struct */
-+	u8  output;
-+	u8  pre_driver_str;
-+	u8  driver_str;
-+} Si2168B_CONFIG_CLKIO_CMD_struct;
-+
-+typedef struct { /* Si2168B_CONFIG_CLKIO_CMD_REPLY_struct */
-+	u8  mode;
-+	u8  pre_driver_str;
-+	u8  driver_str;
-+} Si2168B_CONFIG_CLKIO_CMD_REPLY_struct;
-+
-+/* CONFIG_CLKIO command, OUTPUT field definition (address 1,size 2, lsb 0, unsigned) */
-+#define Si2168B_CONFIG_CLKIO_CMD_OUTPUT_LSB         0
-+#define Si2168B_CONFIG_CLKIO_CMD_OUTPUT_MASK        0x03
-+#define Si2168B_CONFIG_CLKIO_CMD_OUTPUT_MIN         0
-+#define Si2168B_CONFIG_CLKIO_CMD_OUTPUT_MAX         2
-+#define Si2168B_CONFIG_CLKIO_CMD_OUTPUT_NO_CHANGE  0
-+#define Si2168B_CONFIG_CLKIO_CMD_OUTPUT_OFF        2
-+#define Si2168B_CONFIG_CLKIO_CMD_OUTPUT_ON         1
-+/* CONFIG_CLKIO command, PRE_DRIVER_STR field definition (address 1,size 2, lsb 2, unsigned) */
-+#define Si2168B_CONFIG_CLKIO_CMD_PRE_DRIVER_STR_LSB         2
-+#define Si2168B_CONFIG_CLKIO_CMD_PRE_DRIVER_STR_MASK        0x03
-+#define Si2168B_CONFIG_CLKIO_CMD_PRE_DRIVER_STR_MIN         0
-+#define Si2168B_CONFIG_CLKIO_CMD_PRE_DRIVER_STR_MAX         3
-+#define Si2168B_CONFIG_CLKIO_CMD_PRE_DRIVER_STR_PRE_DRIVER_MIN  0
-+#define Si2168B_CONFIG_CLKIO_CMD_PRE_DRIVER_STR_PRE_DRIVER_MAX  3
-+/* CONFIG_CLKIO command, DRIVER_STR field definition (address 1,size 4, lsb 4, unsigned) */
-+#define Si2168B_CONFIG_CLKIO_CMD_DRIVER_STR_LSB         4
-+#define Si2168B_CONFIG_CLKIO_CMD_DRIVER_STR_MASK        0x0f
-+#define Si2168B_CONFIG_CLKIO_CMD_DRIVER_STR_MIN         0
-+#define Si2168B_CONFIG_CLKIO_CMD_DRIVER_STR_MAX         15
-+#define Si2168B_CONFIG_CLKIO_CMD_DRIVER_STR_DRIVER_MIN  0
-+#define Si2168B_CONFIG_CLKIO_CMD_DRIVER_STR_DRIVER_MAX  15
-+/* CONFIG_CLKIO command, MODE field definition (address 1, size 2, lsb 0, unsigned)*/
-+#define Si2168B_CONFIG_CLKIO_RESPONSE_MODE_LSB         0
-+#define Si2168B_CONFIG_CLKIO_RESPONSE_MODE_MASK        0x03
-+#define Si2168B_CONFIG_CLKIO_RESPONSE_MODE_CLK_INPUT   2
-+#define Si2168B_CONFIG_CLKIO_RESPONSE_MODE_CLK_OUTPUT  1
-+#define Si2168B_CONFIG_CLKIO_RESPONSE_MODE_UNUSED      0
-+/* CONFIG_CLKIO command, PRE_DRIVER_STR field definition (address 2, size 8, lsb 0, unsigned)*/
-+#define Si2168B_CONFIG_CLKIO_RESPONSE_PRE_DRIVER_STR_LSB         0
-+#define Si2168B_CONFIG_CLKIO_RESPONSE_PRE_DRIVER_STR_MASK        0xff
-+/* CONFIG_CLKIO command, DRIVER_STR field definition (address 3, size 8, lsb 0, unsigned)*/
-+#define Si2168B_CONFIG_CLKIO_RESPONSE_DRIVER_STR_LSB         0
-+#define Si2168B_CONFIG_CLKIO_RESPONSE_DRIVER_STR_MASK        0xff
-+
-+#endif /* Si2168B_CONFIG_CLKIO_CMD */
-+
-+/* Si2168B_CONFIG_PINS command definition */
-+#define Si2168B_CONFIG_PINS_CMD 0x12
-+
-+#ifdef Si2168B_CONFIG_PINS_CMD
-+#define Si2168B_CONFIG_PINS_CMD_CODE 0x010012
-+
-+typedef struct { /* Si2168B_CONFIG_PINS_CMD_struct */
-+	u8  gpio0_mode;
-+	u8  gpio0_read;
-+	u8  gpio1_mode;
-+	u8  gpio1_read;
-+} Si2168B_CONFIG_PINS_CMD_struct;
-+
-+typedef struct { /* Si2168B_CONFIG_PINS_CMD_REPLY_struct */
-+	u8  gpio0_mode;
-+	u8  gpio0_state;
-+	u8  gpio1_mode;
-+	u8  gpio1_state;
-+}  Si2168B_CONFIG_PINS_CMD_REPLY_struct;
-+
-+/* CONFIG_PINS command, GPIO0_MODE field definition (address 1,size 7, lsb 0, unsigned) */
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_LSB         0
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_MASK        0x7f
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_MIN         0
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_MAX         8
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_DISABLE    1
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_DRIVE_0    2
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_DRIVE_1    3
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_HW_LOCK    8
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_INT_FLAG   7
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_NO_CHANGE  0
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_MODE_TS_ERR     4
-+/* CONFIG_PINS command, GPIO0_READ field definition (address 1,size 1, lsb 7, unsigned) */
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_READ_LSB         7
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_READ_MASK        0x01
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_READ_MIN         0
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_READ_MAX         1
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_READ_DO_NOT_READ  0
-+#define Si2168B_CONFIG_PINS_CMD_GPIO0_READ_READ         1
-+/* CONFIG_PINS command, GPIO1_MODE field definition (address 2,size 7, lsb 0, unsigned) */
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_LSB         0
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_MASK        0x7f
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_MIN         0
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_MAX         8
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_DISABLE    1
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_DRIVE_0    2
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_DRIVE_1    3
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_HW_LOCK    8
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_INT_FLAG   7
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_NO_CHANGE  0
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_MODE_TS_ERR     4
-+/* CONFIG_PINS command, GPIO1_READ field definition (address 2,size 1, lsb 7, unsigned) */
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_READ_LSB         7
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_READ_MASK        0x01
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_READ_MIN         0
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_READ_MAX         1
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_READ_DO_NOT_READ  0
-+#define Si2168B_CONFIG_PINS_CMD_GPIO1_READ_READ         1
-+/* CONFIG_PINS command, GPIO0_MODE field definition (address 1, size 7, lsb 0, unsigned)*/
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO0_MODE_LSB         0
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO0_MODE_MASK        0x7f
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO0_MODE_DISABLE   1
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO0_MODE_DRIVE_0   2
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO0_MODE_DRIVE_1   3
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO0_MODE_HW_LOCK   8
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO0_MODE_INT_FLAG  7
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO0_MODE_TS_ERR    4
-+/* CONFIG_PINS command, GPIO0_STATE field definition (address 1, size 1, lsb 7, unsigned)*/
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO0_STATE_LSB         7
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO0_STATE_MASK        0x01
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO0_STATE_READ_0  0
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO0_STATE_READ_1  1
-+/* CONFIG_PINS command, GPIO1_MODE field definition (address 2, size 7, lsb 0, unsigned)*/
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO1_MODE_LSB         0
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO1_MODE_MASK        0x7f
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO1_MODE_DISABLE   1
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO1_MODE_DRIVE_0   2
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO1_MODE_DRIVE_1   3
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO1_MODE_HW_LOCK   8
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO1_MODE_INT_FLAG  7
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO1_MODE_TS_ERR    4
-+/* CONFIG_PINS command, GPIO1_STATE field definition (address 2, size 1, lsb 7, unsigned)*/
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO1_STATE_LSB         7
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO1_STATE_MASK        0x01
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO1_STATE_READ_0  0
-+#define Si2168B_CONFIG_PINS_RESPONSE_GPIO1_STATE_READ_1  1
-+
-+#endif /* Si2168B_CONFIG_PINS_CMD */
-+
-+/* Si2168B_DD_BER command definition */
-+#define Si2168B_DD_BER_CMD 0x82
-+
-+#ifdef Si2168B_DD_BER_CMD
-+#define Si2168B_DD_BER_CMD_CODE 0x010082
-+
-+typedef struct { /* Si2168B_DD_BER_CMD_struct */
-+	u8  rst;
-+} Si2168B_DD_BER_CMD_struct;
-+
-+typedef struct { /* Si2168B_DD_BER_CMD_REPLY_struct */
-+	u8  exp;
-+	u8  mant;
-+}  Si2168B_DD_BER_CMD_REPLY_struct;
-+
-+/* DD_BER command, RST field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2168B_DD_BER_CMD_RST_LSB         0
-+#define Si2168B_DD_BER_CMD_RST_MASK        0x01
-+#define Si2168B_DD_BER_CMD_RST_MIN         0
-+#define Si2168B_DD_BER_CMD_RST_MAX         1
-+#define Si2168B_DD_BER_CMD_RST_CLEAR  1
-+#define Si2168B_DD_BER_CMD_RST_RUN    0
-+/* DD_BER command, EXP field definition (address 1, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DD_BER_RESPONSE_EXP_LSB         0
-+#define Si2168B_DD_BER_RESPONSE_EXP_MASK        0x0f
-+#define Si2168B_DD_BER_RESPONSE_EXP_EXP_MIN  0
-+#define Si2168B_DD_BER_RESPONSE_EXP_EXP_MAX  8
-+/* DD_BER command, MANT field definition (address 2, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DD_BER_RESPONSE_MANT_LSB         0
-+#define Si2168B_DD_BER_RESPONSE_MANT_MASK        0xff
-+#define Si2168B_DD_BER_RESPONSE_MANT_MANT_MIN  0
-+#define Si2168B_DD_BER_RESPONSE_MANT_MANT_MAX  99
-+
-+#endif /* Si2168B_DD_BER_CMD */
-+
-+/* Si2168B_DD_CBER command definition */
-+#define Si2168B_DD_CBER_CMD 0x81
-+
-+#ifdef Si2168B_DD_CBER_CMD
-+#define Si2168B_DD_CBER_CMD_CODE 0x010081
-+
-+typedef struct { /* Si2168B_DD_CBER_CMD_struct */
-+	u8  rst;
-+} Si2168B_DD_CBER_CMD_struct;
-+
-+typedef struct { /* Si2168B_DD_CBER_CMD_REPLY_struct */
-+	u8  exp;
-+	u8  mant;
-+}  Si2168B_DD_CBER_CMD_REPLY_struct;
-+
-+/* DD_CBER command, RST field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2168B_DD_CBER_CMD_RST_LSB         0
-+#define Si2168B_DD_CBER_CMD_RST_MASK        0x01
-+#define Si2168B_DD_CBER_CMD_RST_MIN         0
-+#define Si2168B_DD_CBER_CMD_RST_MAX         1
-+#define Si2168B_DD_CBER_CMD_RST_CLEAR  1
-+#define Si2168B_DD_CBER_CMD_RST_RUN    0
-+/* DD_CBER command, EXP field definition (address 1, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DD_CBER_RESPONSE_EXP_LSB         0
-+#define Si2168B_DD_CBER_RESPONSE_EXP_MASK        0x0f
-+#define Si2168B_DD_CBER_RESPONSE_EXP_EXP_MIN  0
-+#define Si2168B_DD_CBER_RESPONSE_EXP_EXP_MAX  8
-+/* DD_CBER command, MANT field definition (address 2, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DD_CBER_RESPONSE_MANT_LSB         0
-+#define Si2168B_DD_CBER_RESPONSE_MANT_MASK        0xff
-+#define Si2168B_DD_CBER_RESPONSE_MANT_MANT_MIN  0
-+#define Si2168B_DD_CBER_RESPONSE_MANT_MANT_MAX  99
-+
-+#endif /* Si2168B_DD_CBER_CMD */
-+
-+/* Si2168B_DD_EXT_AGC_TER command definition */
-+#define Si2168B_DD_EXT_AGC_TER_CMD 0x89
-+
-+#ifdef Si2168B_DD_EXT_AGC_TER_CMD
-+#define Si2168B_DD_EXT_AGC_TER_CMD_CODE 0x010089
-+
-+typedef struct { /* Si2168B_DD_EXT_AGC_TER_CMD_struct */
-+	u8  agc_1_mode;
-+	u8  agc_1_inv;
-+	u8  agc_2_mode;
-+	u8  agc_2_inv;
-+	u8  agc_1_kloop;
-+	u8  agc_2_kloop;
-+	u8  agc_1_min;
-+	u8  agc_2_min;
-+} Si2168B_DD_EXT_AGC_TER_CMD_struct;
-+
-+typedef struct { /* Si2168B_DD_EXT_AGC_TER_CMD_REPLY_struct */
-+	u8  agc_1_level;
-+	u8  agc_2_level;
-+}  Si2168B_DD_EXT_AGC_TER_CMD_REPLY_struct;
-+
-+/* DD_EXT_AGC_TER command, AGC_1_MODE field definition (address 1,size 3, lsb 0, unsigned) */
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_LSB         0
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_MASK        0x07
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_MIN         0
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_MAX         5
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_MP_A       2
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_MP_B       3
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_MP_C       4
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_MP_D       5
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_NOT_USED   1
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MODE_NO_CHANGE  0
-+/* DD_EXT_AGC_TER command, AGC_1_INV field definition (address 1,size 1, lsb 3, unsigned) */
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_INV_LSB         3
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_INV_MASK        0x01
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_INV_MIN         0
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_INV_MAX         1
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_INV_INVERTED      1
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_INV_NOT_INVERTED  0
-+/* DD_EXT_AGC_TER command, AGC_2_MODE field definition (address 1,size 3, lsb 4, unsigned) */
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MODE_LSB         4
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MODE_MASK        0x07
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MODE_MIN         0
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MODE_MAX         5
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MODE_MP_A       2
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MODE_MP_B       3
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MODE_MP_C       4
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MODE_MP_D       5
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MODE_NOT_USED   1
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MODE_NO_CHANGE  0
-+/* DD_EXT_AGC_TER command, AGC_2_INV field definition (address 1,size 1, lsb 7, unsigned) */
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_INV_LSB         7
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_INV_MASK        0x01
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_INV_MIN         0
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_INV_MAX         1
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_INV_INVERTED      1
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_INV_NOT_INVERTED  0
-+/* DD_EXT_AGC_TER command, AGC_1_KLOOP field definition (address 2,size 5, lsb 0, unsigned) */
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_KLOOP_LSB         0
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_KLOOP_MASK        0x1f
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_KLOOP_MIN         6
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_KLOOP_MAX         20
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_KLOOP_AGC_1_KLOOP_MIN  6
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_KLOOP_AGC_1_KLOOP_MAX  20
-+/* DD_EXT_AGC_TER command, AGC_2_KLOOP field definition (address 3,size 5, lsb 0, unsigned) */
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_KLOOP_LSB         0
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_KLOOP_MASK        0x1f
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_KLOOP_MIN         6
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_KLOOP_MAX         20
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_KLOOP_AGC_2_KLOOP_MIN  6
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_KLOOP_AGC_2_KLOOP_MAX  20
-+/* DD_EXT_AGC_TER command, AGC_1_MIN field definition (address 4,size 8, lsb 0, unsigned) */
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MIN_LSB         0
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MIN_MASK        0xff
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MIN_MIN         0
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MIN_MAX         255
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MIN_AGC_1_MIN_MIN  0
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_1_MIN_AGC_1_MIN_MAX  255
-+/* DD_EXT_AGC_TER command, AGC_2_MIN field definition (address 5,size 8, lsb 0, unsigned) */
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MIN_LSB         0
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MIN_MASK        0xff
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MIN_MIN         0
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MIN_MAX         255
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MIN_AGC_2_MIN_MIN  0
-+#define Si2168B_DD_EXT_AGC_TER_CMD_AGC_2_MIN_AGC_2_MIN_MAX  255
-+/* DD_EXT_AGC_TER command, AGC_1_LEVEL field definition (address 1, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DD_EXT_AGC_TER_RESPONSE_AGC_1_LEVEL_LSB         0
-+#define Si2168B_DD_EXT_AGC_TER_RESPONSE_AGC_1_LEVEL_MASK        0xff
-+/* DD_EXT_AGC_TER command, AGC_2_LEVEL field definition (address 2, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DD_EXT_AGC_TER_RESPONSE_AGC_2_LEVEL_LSB         0
-+#define Si2168B_DD_EXT_AGC_TER_RESPONSE_AGC_2_LEVEL_MASK        0xff
-+
-+#endif /* Si2168B_DD_EXT_AGC_TER_CMD */
-+
-+/* Si2168B_DD_FER command definition */
-+#define Si2168B_DD_FER_CMD 0x86
-+
-+#ifdef Si2168B_DD_FER_CMD
-+#define Si2168B_DD_FER_CMD_CODE 0x010086
-+
-+typedef struct { /* Si2168B_DD_FER_CMD_struct */
-+	u8  rst;
-+} Si2168B_DD_FER_CMD_struct;
-+
-+typedef struct { /* Si2168B_DD_FER_CMD_REPLY_struct */
-+	u8  exp;
-+	u8  mant;
-+}  Si2168B_DD_FER_CMD_REPLY_struct;
-+
-+/* DD_FER command, RST field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2168B_DD_FER_CMD_RST_LSB         0
-+#define Si2168B_DD_FER_CMD_RST_MASK        0x01
-+#define Si2168B_DD_FER_CMD_RST_MIN         0
-+#define Si2168B_DD_FER_CMD_RST_MAX         1
-+#define Si2168B_DD_FER_CMD_RST_CLEAR  1
-+#define Si2168B_DD_FER_CMD_RST_RUN    0
-+/* DD_FER command, EXP field definition (address 1, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DD_FER_RESPONSE_EXP_LSB         0
-+#define Si2168B_DD_FER_RESPONSE_EXP_MASK        0x0f
-+#define Si2168B_DD_FER_RESPONSE_EXP_EXP_MIN  0
-+#define Si2168B_DD_FER_RESPONSE_EXP_EXP_MAX  8
-+/* DD_FER command, MANT field definition (address 2, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DD_FER_RESPONSE_MANT_LSB         0
-+#define Si2168B_DD_FER_RESPONSE_MANT_MASK        0xff
-+#define Si2168B_DD_FER_RESPONSE_MANT_MANT_MIN  0
-+#define Si2168B_DD_FER_RESPONSE_MANT_MANT_MAX  99
-+
-+#endif /* Si2168B_DD_FER_CMD */
-+
-+/* Si2168B_DD_GET_REG command definition */
-+#define Si2168B_DD_GET_REG_CMD 0x8f
-+
-+#ifdef Si2168B_DD_GET_REG_CMD
-+#define Si2168B_DD_GET_REG_CMD_CODE 0x01008f
-+
-+typedef struct { /* Si2168B_DD_GET_REG_CMD_struct */
-+	u8  reg_code_lsb;
-+	u8  reg_code_mid;
-+	u8  reg_code_msb;
-+} Si2168B_DD_GET_REG_CMD_struct;
-+
-+
-+typedef struct { /* Si2168B_DD_GET_REG_CMD_REPLY_struct */
-+	u8  data1;
-+	u8  data2;
-+	u8  data3;
-+	u8  data4;
-+}  Si2168B_DD_GET_REG_CMD_REPLY_struct;
-+
-+/* DD_GET_REG command, REG_CODE_LSB field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_LSB_LSB         0
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_LSB_MASK        0xff
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_LSB_MIN         0
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_LSB_MAX         255
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_LSB_REG_CODE_LSB_MIN  0
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_LSB_REG_CODE_LSB_MAX  255
-+/* DD_GET_REG command, REG_CODE_MID field definition (address 2,size 8, lsb 0, unsigned) */
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_MID_LSB         0
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_MID_MASK        0xff
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_MID_MIN         0
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_MID_MAX         255
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_MID_REG_CODE_MID_MIN  0
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_MID_REG_CODE_MID_MAX  255
-+/* DD_GET_REG command, REG_CODE_MSB field definition (address 3,size 8, lsb 0, unsigned) */
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_MSB_LSB         0
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_MSB_MASK        0xff
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_MSB_MIN         0
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_MSB_MAX         255
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_MSB_REG_CODE_MSB_MIN  0
-+#define Si2168B_DD_GET_REG_CMD_REG_CODE_MSB_REG_CODE_MSB_MAX  255
-+/* DD_GET_REG command, DATA1 field definition (address 1, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA1_LSB         0
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA1_MASK        0xff
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA1_DATA1_MIN  0
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA1_DATA1_MAX  255
-+/* DD_GET_REG command, DATA2 field definition (address 2, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA2_LSB         0
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA2_MASK        0xff
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA2_DATA2_MIN  0
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA2_DATA2_MAX  255
-+/* DD_GET_REG command, DATA3 field definition (address 3, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA3_LSB         0
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA3_MASK        0xff
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA3_DATA3_MIN  0
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA3_DATA3_MAX  255
-+/* DD_GET_REG command, DATA4 field definition (address 4, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA4_LSB         0
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA4_MASK        0xff
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA4_DATA4_MIN  0
-+#define Si2168B_DD_GET_REG_RESPONSE_DATA4_DATA4_MAX  255
-+
-+#endif /* Si2168B_DD_GET_REG_CMD */
-+
-+/* Si2168B_DD_MP_DEFAULTS command definition */
-+#define Si2168B_DD_MP_DEFAULTS_CMD 0x88
-+
-+#ifdef Si2168B_DD_MP_DEFAULTS_CMD
-+#define Si2168B_DD_MP_DEFAULTS_CMD_CODE 0x010088
-+
-+typedef struct { /* Si2168B_DD_MP_DEFAULTS_CMD_struct */
-+	u8  mp_a_mode;
-+	u8  mp_b_mode;
-+	u8  mp_c_mode;
-+	u8  mp_d_mode;
-+} Si2168B_DD_MP_DEFAULTS_CMD_struct;
-+
-+typedef struct { /* Si2168B_DD_MP_DEFAULTS_CMD_REPLY_struct */
-+	u8  mp_a_mode;
-+	u8  mp_b_mode;
-+	u8  mp_c_mode;
-+	u8  mp_d_mode;
-+}  Si2168B_DD_MP_DEFAULTS_CMD_REPLY_struct;
-+
-+/* DD_MP_DEFAULTS command, MP_A_MODE field definition (address 1,size 7, lsb 0, unsigned) */
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_LSB         0
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_MASK        0x7f
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_MIN         0
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_MAX         3
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_DISABLE    1
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_DRIVE_0    2
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_DRIVE_1    3
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_A_MODE_NO_CHANGE  0
-+/* DD_MP_DEFAULTS command, MP_B_MODE field definition (address 2,size 7, lsb 0, unsigned) */
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_LSB         0
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_MASK        0x7f
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_MIN         0
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_MAX         3
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_DISABLE    1
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_DRIVE_0    2
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_DRIVE_1    3
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_B_MODE_NO_CHANGE  0
-+/* DD_MP_DEFAULTS command, MP_C_MODE field definition (address 3,size 7, lsb 0, unsigned) */
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_LSB         0
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_MASK        0x7f
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_MIN         0
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_MAX         3
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_DISABLE    1
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_DRIVE_0    2
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_DRIVE_1    3
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_C_MODE_NO_CHANGE  0
-+/* DD_MP_DEFAULTS command, MP_D_MODE field definition (address 4,size 7, lsb 0, unsigned) */
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_LSB         0
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_MASK        0x7f
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_MIN         0
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_MAX         3
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_DISABLE    1
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_DRIVE_0    2
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_DRIVE_1    3
-+#define Si2168B_DD_MP_DEFAULTS_CMD_MP_D_MODE_NO_CHANGE  0
-+/* DD_MP_DEFAULTS command, MP_A_MODE field definition (address 1, size 7, lsb 0, unsigned)*/
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_A_MODE_LSB         0
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_A_MODE_MASK        0x7f
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_A_MODE_AGC_1           3
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_A_MODE_AGC_1_INVERTED  4
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_A_MODE_AGC_2           5
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_A_MODE_AGC_2_INVERTED  6
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_A_MODE_DISABLE         0
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_A_MODE_DRIVE_0         1
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_A_MODE_DRIVE_1         2
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_A_MODE_FEF             7
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_A_MODE_FEF_INVERTED    8
-+/* DD_MP_DEFAULTS command, MP_B_MODE field definition (address 2, size 7, lsb 0, unsigned)*/
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_B_MODE_LSB         0
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_B_MODE_MASK        0x7f
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_B_MODE_AGC_1           3
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_B_MODE_AGC_1_INVERTED  4
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_B_MODE_AGC_2           5
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_B_MODE_AGC_2_INVERTED  6
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_B_MODE_DISABLE         0
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_B_MODE_DRIVE_0         1
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_B_MODE_DRIVE_1         2
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_B_MODE_FEF             7
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_B_MODE_FEF_INVERTED    8
-+/* DD_MP_DEFAULTS command, MP_C_MODE field definition (address 3, size 7, lsb 0, unsigned)*/
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_C_MODE_LSB         0
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_C_MODE_MASK        0x7f
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_C_MODE_AGC_1           3
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_C_MODE_AGC_1_INVERTED  4
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_C_MODE_AGC_2           5
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_C_MODE_AGC_2_INVERTED  6
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_C_MODE_DISABLE         0
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_C_MODE_DRIVE_0         1
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_C_MODE_DRIVE_1         2
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_C_MODE_FEF             7
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_C_MODE_FEF_INVERTED    8
-+/* DD_MP_DEFAULTS command, MP_D_MODE field definition (address 4, size 7, lsb 0, unsigned)*/
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_D_MODE_LSB         0
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_D_MODE_MASK        0x7f
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_D_MODE_AGC_1           3
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_D_MODE_AGC_1_INVERTED  4
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_D_MODE_AGC_2           5
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_D_MODE_AGC_2_INVERTED  6
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_D_MODE_DISABLE         0
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_D_MODE_DRIVE_0         1
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_D_MODE_DRIVE_1         2
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_D_MODE_FEF             7
-+#define Si2168B_DD_MP_DEFAULTS_RESPONSE_MP_D_MODE_FEF_INVERTED    8
-+
-+#endif /* Si2168B_DD_MP_DEFAULTS_CMD */
-+
-+/* Si2168B_DD_PER command definition */
-+#define Si2168B_DD_PER_CMD 0x83
-+
-+#ifdef Si2168B_DD_PER_CMD
-+#define Si2168B_DD_PER_CMD_CODE 0x010083
-+
-+typedef struct { /* Si2168B_DD_PER_CMD_struct */
-+	u8  rst;
-+} Si2168B_DD_PER_CMD_struct;
-+
-+typedef struct { /* Si2168B_DD_PER_CMD_REPLY_struct */
-+	u8  exp;
-+	u8  mant;
-+}  Si2168B_DD_PER_CMD_REPLY_struct;
-+
-+/* DD_PER command, RST field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2168B_DD_PER_CMD_RST_LSB         0
-+#define Si2168B_DD_PER_CMD_RST_MASK        0x01
-+#define Si2168B_DD_PER_CMD_RST_MIN         0
-+#define Si2168B_DD_PER_CMD_RST_MAX         1
-+#define Si2168B_DD_PER_CMD_RST_CLEAR  1
-+#define Si2168B_DD_PER_CMD_RST_RUN    0
-+/* DD_PER command, EXP field definition (address 1, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DD_PER_RESPONSE_EXP_LSB         0
-+#define Si2168B_DD_PER_RESPONSE_EXP_MASK        0x0f
-+#define Si2168B_DD_PER_RESPONSE_EXP_EXP_MIN  0
-+#define Si2168B_DD_PER_RESPONSE_EXP_EXP_MAX  8
-+/* DD_PER command, MANT field definition (address 2, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DD_PER_RESPONSE_MANT_LSB         0
-+#define Si2168B_DD_PER_RESPONSE_MANT_MASK        0xff
-+#define Si2168B_DD_PER_RESPONSE_MANT_MANT_MIN  0
-+#define Si2168B_DD_PER_RESPONSE_MANT_MANT_MAX  99
-+
-+#endif /* Si2168B_DD_PER_CMD */
-+
-+/* Si2168B_DD_RESTART command definition */
-+#define Si2168B_DD_RESTART_CMD 0x85
-+
-+#ifdef Si2168B_DD_RESTART_CMD
-+#define Si2168B_DD_RESTART_CMD_CODE 0x010085
-+
-+typedef struct { /* Si2168B_DD_RESTART_CMD_struct */
-+	u8  nothing;
-+} Si2168B_DD_RESTART_CMD_struct;
-+
-+#endif /* Si2168B_DD_RESTART_CMD */
-+
-+/* Si2168B_DD_SET_REG command definition */
-+#define Si2168B_DD_SET_REG_CMD 0x8e
-+
-+#ifdef Si2168B_DD_SET_REG_CMD
-+#define Si2168B_DD_SET_REG_CMD_CODE 0x01008e
-+
-+typedef struct { /* Si2168B_DD_SET_REG_CMD_struct */
-+	u8  reg_code_lsb;
-+	u8  reg_code_mid;
-+	u8  reg_code_msb;
-+	u32 value;
-+} Si2168B_DD_SET_REG_CMD_struct;
-+
-+/* DD_SET_REG command, REG_CODE_LSB field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_LSB_LSB         0
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_LSB_MASK        0xff
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_LSB_MIN         0
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_LSB_MAX         255
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_LSB_REG_CODE_LSB_MIN  0
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_LSB_REG_CODE_LSB_MAX  255
-+/* DD_SET_REG command, REG_CODE_MID field definition (address 2,size 8, lsb 0, unsigned) */
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_MID_LSB         0
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_MID_MASK        0xff
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_MID_MIN         0
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_MID_MAX         255
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_MID_REG_CODE_MID_MIN  0
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_MID_REG_CODE_MID_MAX  255
-+/* DD_SET_REG command, REG_CODE_MSB field definition (address 3,size 8, lsb 0, unsigned) */
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_MSB_LSB         0
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_MSB_MASK        0xff
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_MSB_MIN         0
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_MSB_MAX         255
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_MSB_REG_CODE_MSB_MIN  0
-+#define Si2168B_DD_SET_REG_CMD_REG_CODE_MSB_REG_CODE_MSB_MAX  255
-+/* DD_SET_REG command, VALUE field definition (address 4,size 32, lsb 0, unsigned) */
-+#define Si2168B_DD_SET_REG_CMD_VALUE_LSB         0
-+#define Si2168B_DD_SET_REG_CMD_VALUE_MASK        0xffffffff
-+#define Si2168B_DD_SET_REG_CMD_VALUE_MIN         0
-+#define Si2168B_DD_SET_REG_CMD_VALUE_MAX         4294967295
-+#define Si2168B_DD_SET_REG_CMD_VALUE_VALUE_MIN  0
-+#define Si2168B_DD_SET_REG_CMD_VALUE_VALUE_MAX  4294967295
-+#endif /* Si2168B_DD_SET_REG_CMD */
-+
-+/* Si2168B_DD_SSI_SQI command definition */
-+#define Si2168B_DD_SSI_SQI_CMD 0x8b
-+
-+#ifdef Si2168B_DD_SSI_SQI_CMD
-+#define Si2168B_DD_SSI_SQI_CMD_CODE 0x01008b
-+
-+typedef struct { /* Si2168B_DD_SSI_SQI_CMD_struct */
-+	s8  tuner_rssi;
-+} Si2168B_DD_SSI_SQI_CMD_struct;
-+
-+
-+typedef struct { /* Si2168B_DD_SSI_SQI_CMD_REPLY_struct */
-+	u8  ssi;
-+	s8  sqi;
-+}  Si2168B_DD_SSI_SQI_CMD_REPLY_struct;
-+
-+/* DD_SSI_SQI command, TUNER_RSSI field definition (address 1,size 8, lsb 0, signed) */
-+#define Si2168B_DD_SSI_SQI_CMD_TUNER_RSSI_LSB         0
-+#define Si2168B_DD_SSI_SQI_CMD_TUNER_RSSI_MASK        0xff
-+#define Si2168B_DD_SSI_SQI_CMD_TUNER_RSSI_SHIFT       24
-+#define Si2168B_DD_SSI_SQI_CMD_TUNER_RSSI_MIN         -128
-+#define Si2168B_DD_SSI_SQI_CMD_TUNER_RSSI_MAX         127
-+/* DD_SSI_SQI command, SSI field definition (address 1, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DD_SSI_SQI_RESPONSE_SSI_LSB         0
-+#define Si2168B_DD_SSI_SQI_RESPONSE_SSI_MASK        0xff
-+#define Si2168B_DD_SSI_SQI_RESPONSE_SSI_SSI_MIN  0
-+#define Si2168B_DD_SSI_SQI_RESPONSE_SSI_SSI_MAX  100
-+/* DD_SSI_SQI command, SQI field definition (address 2, size 8, lsb 0, signed)*/
-+#define Si2168B_DD_SSI_SQI_RESPONSE_SQI_LSB         0
-+#define Si2168B_DD_SSI_SQI_RESPONSE_SQI_MASK        0xff
-+#define Si2168B_DD_SSI_SQI_RESPONSE_SQI_SHIFT       24
-+#define Si2168B_DD_SSI_SQI_RESPONSE_SQI_SQI_MIN  -1
-+#define Si2168B_DD_SSI_SQI_RESPONSE_SQI_SQI_MAX  100
-+
-+#endif /* Si2168B_DD_SSI_SQI_CMD */
-+
-+/* Si2168B_DD_STATUS command definition */
-+#define Si2168B_DD_STATUS_CMD 0x87
-+
-+#ifdef Si2168B_DD_STATUS_CMD
-+#define Si2168B_DD_STATUS_CMD_CODE 0x010087
-+
-+typedef struct { /* Si2168B_DD_STATUS_CMD_struct */
-+	u8  intack;
-+} Si2168B_DD_STATUS_CMD_struct;
-+
-+typedef struct { /* Si2168B_DD_STATUS_CMD_REPLY_struct */
-+	u8  pclint;
-+	u8  dlint;
-+	u8  berint;
-+	u8  uncorint;
-+	u8  rsqint_bit5;
-+	u8  rsqint_bit6;
-+	u8  rsqint_bit7;
-+	u8  pcl;
-+	u8  dl;
-+	u8  ber;
-+	u8  uncor;
-+	u8  rsqstat_bit5;
-+	u8  rsqstat_bit6;
-+	u8  rsqstat_bit7;
-+	u8  modulation;
-+	u16 ts_bit_rate;
-+	u16 ts_clk_freq;
-+}  Si2168B_DD_STATUS_CMD_REPLY_struct;
-+
-+/* DD_STATUS command, INTACK field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2168B_DD_STATUS_CMD_INTACK_LSB         0
-+#define Si2168B_DD_STATUS_CMD_INTACK_MASK        0x01
-+#define Si2168B_DD_STATUS_CMD_INTACK_MIN         0
-+#define Si2168B_DD_STATUS_CMD_INTACK_MAX         1
-+#define Si2168B_DD_STATUS_CMD_INTACK_CLEAR  1
-+#define Si2168B_DD_STATUS_CMD_INTACK_OK     0
-+/* DD_STATUS command, PCLINT field definition (address 1, size 1, lsb 1, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_PCLINT_LSB         1
-+#define Si2168B_DD_STATUS_RESPONSE_PCLINT_MASK        0x01
-+#define Si2168B_DD_STATUS_RESPONSE_PCLINT_CHANGED    1
-+#define Si2168B_DD_STATUS_RESPONSE_PCLINT_NO_CHANGE  0
-+/* DD_STATUS command, DLINT field definition (address 1, size 1, lsb 2, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_DLINT_LSB         2
-+#define Si2168B_DD_STATUS_RESPONSE_DLINT_MASK        0x01
-+#define Si2168B_DD_STATUS_RESPONSE_DLINT_CHANGED    1
-+#define Si2168B_DD_STATUS_RESPONSE_DLINT_NO_CHANGE  0
-+/* DD_STATUS command, BERINT field definition (address 1, size 1, lsb 3, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_BERINT_LSB         3
-+#define Si2168B_DD_STATUS_RESPONSE_BERINT_MASK        0x01
-+#define Si2168B_DD_STATUS_RESPONSE_BERINT_CHANGED    1
-+#define Si2168B_DD_STATUS_RESPONSE_BERINT_NO_CHANGE  0
-+/* DD_STATUS command, UNCORINT field definition (address 1, size 1, lsb 4, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_UNCORINT_LSB         4
-+#define Si2168B_DD_STATUS_RESPONSE_UNCORINT_MASK        0x01
-+#define Si2168B_DD_STATUS_RESPONSE_UNCORINT_CHANGED    1
-+#define Si2168B_DD_STATUS_RESPONSE_UNCORINT_NO_CHANGE  0
-+/* DD_STATUS command, RSQINT_BIT5 field definition (address 1, size 1, lsb 5, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT5_LSB         5
-+#define Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT5_MASK        0x01
-+#define Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT5_CHANGED    1
-+#define Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT5_NO_CHANGE  0
-+/* DD_STATUS command, RSQINT_BIT6 field definition (address 1, size 1, lsb 6, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT6_LSB         6
-+#define Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT6_MASK        0x01
-+#define Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT6_CHANGED    1
-+#define Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT6_NO_CHANGE  0
-+/* DD_STATUS command, RSQINT_BIT7 field definition (address 1, size 1, lsb 7, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT7_LSB         7
-+#define Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT7_MASK        0x01
-+#define Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT7_CHANGED    1
-+#define Si2168B_DD_STATUS_RESPONSE_RSQINT_BIT7_NO_CHANGE  0
-+/* DD_STATUS command, PCL field definition (address 2, size 1, lsb 1, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_PCL_LSB         1
-+#define Si2168B_DD_STATUS_RESPONSE_PCL_MASK        0x01
-+#define Si2168B_DD_STATUS_RESPONSE_PCL_LOCKED   1
-+#define Si2168B_DD_STATUS_RESPONSE_PCL_NO_LOCK  0
-+/* DD_STATUS command, DL field definition (address 2, size 1, lsb 2, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_DL_LSB         2
-+#define Si2168B_DD_STATUS_RESPONSE_DL_MASK        0x01
-+#define Si2168B_DD_STATUS_RESPONSE_DL_LOCKED   1
-+#define Si2168B_DD_STATUS_RESPONSE_DL_NO_LOCK  0
-+/* DD_STATUS command, BER field definition (address 2, size 1, lsb 3, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_BER_LSB         3
-+#define Si2168B_DD_STATUS_RESPONSE_BER_MASK        0x01
-+#define Si2168B_DD_STATUS_RESPONSE_BER_BER_ABOVE  1
-+#define Si2168B_DD_STATUS_RESPONSE_BER_BER_BELOW  0
-+/* DD_STATUS command, UNCOR field definition (address 2, size 1, lsb 4, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_UNCOR_LSB         4
-+#define Si2168B_DD_STATUS_RESPONSE_UNCOR_MASK        0x01
-+#define Si2168B_DD_STATUS_RESPONSE_UNCOR_NO_UNCOR_FOUND  0
-+#define Si2168B_DD_STATUS_RESPONSE_UNCOR_UNCOR_FOUND     1
-+/* DD_STATUS command, RSQSTAT_BIT5 field definition (address 2, size 1, lsb 5, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_RSQSTAT_BIT5_LSB         5
-+#define Si2168B_DD_STATUS_RESPONSE_RSQSTAT_BIT5_MASK        0x01
-+#define Si2168B_DD_STATUS_RESPONSE_RSQSTAT_BIT5_NO_CHANGE 0
-+#define Si2168B_DD_STATUS_RESPONSE_RSQSTAT_BIT5_CHANGE    1
-+/* DD_STATUS command, RSQSTAT_BIT6 field definition (address 2, size 1, lsb 6, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_RSQSTAT_BIT6_LSB         6
-+#define Si2168B_DD_STATUS_RESPONSE_RSQSTAT_BIT6_MASK        0x01
-+/* DD_STATUS command, RSQSTAT_BIT7 field definition (address 2, size 1, lsb 7, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_RSQSTAT_BIT7_LSB         7
-+#define Si2168B_DD_STATUS_RESPONSE_RSQSTAT_BIT7_MASK        0x01
-+/* DD_STATUS command, MODULATION field definition (address 3, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_MODULATION_LSB         0
-+#define Si2168B_DD_STATUS_RESPONSE_MODULATION_MASK        0x0f
-+#define Si2168B_DD_STATUS_RESPONSE_MODULATION_DSS    10
-+#define Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBC   3
-+#define Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBC2  11
-+#define Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBS   8
-+#define Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBS2  9
-+#define Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBT   2
-+#define Si2168B_DD_STATUS_RESPONSE_MODULATION_DVBT2  7
-+#define Si2168B_DD_STATUS_RESPONSE_MODULATION_MCNS   1
-+/* DD_STATUS command, TS_BIT_RATE field definition (address 4, size 16, lsb 0, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_TS_BIT_RATE_LSB         0
-+#define Si2168B_DD_STATUS_RESPONSE_TS_BIT_RATE_MASK        0xffff
-+/* DD_STATUS command, TS_CLK_FREQ field definition (address 6, size 16, lsb 0, unsigned)*/
-+#define Si2168B_DD_STATUS_RESPONSE_TS_CLK_FREQ_LSB         0
-+#define Si2168B_DD_STATUS_RESPONSE_TS_CLK_FREQ_MASK        0xffff
-+
-+#endif /* Si2168B_DD_STATUS_CMD */
-+
-+/* Si2168B_DD_UNCOR command definition */
-+#define Si2168B_DD_UNCOR_CMD 0x84
-+
-+#ifdef Si2168B_DD_UNCOR_CMD
-+#define Si2168B_DD_UNCOR_CMD_CODE 0x010084
-+
-+typedef struct { /* Si2168B_DD_UNCOR_CMD_struct */
-+	u8  rst;
-+} Si2168B_DD_UNCOR_CMD_struct;
-+
-+typedef struct { /* Si2168B_DD_UNCOR_CMD_REPLY_struct */
-+	u8  uncor_lsb;
-+	u8  uncor_msb;
-+}  Si2168B_DD_UNCOR_CMD_REPLY_struct;
-+
-+/* DD_UNCOR command, RST field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2168B_DD_UNCOR_CMD_RST_LSB         0
-+#define Si2168B_DD_UNCOR_CMD_RST_MASK        0x01
-+#define Si2168B_DD_UNCOR_CMD_RST_MIN         0
-+#define Si2168B_DD_UNCOR_CMD_RST_MAX         1
-+#define Si2168B_DD_UNCOR_CMD_RST_CLEAR  1
-+#define Si2168B_DD_UNCOR_CMD_RST_RUN    0
-+/* DD_UNCOR command, UNCOR_LSB field definition (address 1, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DD_UNCOR_RESPONSE_UNCOR_LSB_LSB         0
-+#define Si2168B_DD_UNCOR_RESPONSE_UNCOR_LSB_MASK        0xff
-+/* DD_UNCOR command, UNCOR_MSB field definition (address 2, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DD_UNCOR_RESPONSE_UNCOR_MSB_LSB         0
-+#define Si2168B_DD_UNCOR_RESPONSE_UNCOR_MSB_MASK        0xff
-+
-+#endif /* Si2168B_DD_UNCOR_CMD */
-+
-+/* Si2168B_DOWNLOAD_DATASET_CONTINUE command definition */
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD 0xb9
-+
-+#ifdef Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_CODE 0x0100b9
-+
-+typedef struct { /* Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_struct */
-+	u8  data0;
-+	u8  data1;
-+	u8  data2;
-+	u8  data3;
-+	u8  data4;
-+	u8  data5;
-+	u8  data6;
-+} Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_struct;
-+
-+typedef struct { /* Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_REPLY_struct */
-+}  Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_REPLY_struct;
-+
-+/* DOWNLOAD_DATASET_CONTINUE command, DATA0 field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA0_LSB         0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA0_MASK        0xff
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA0_MIN         0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA0_MAX         255
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA0_DATA0_MIN  0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA0_DATA0_MAX  255
-+/* DOWNLOAD_DATASET_CONTINUE command, DATA1 field definition (address 2,size 8, lsb 0, unsigned) */
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA1_LSB         0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA1_MASK        0xff
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA1_MIN         0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA1_MAX         255
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA1_DATA1_MIN  0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA1_DATA1_MAX  255
-+/* DOWNLOAD_DATASET_CONTINUE command, DATA2 field definition (address 3,size 8, lsb 0, unsigned) */
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA2_LSB         0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA2_MASK        0xff
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA2_MIN         0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA2_MAX         255
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA2_DATA2_MIN  0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA2_DATA2_MAX  255
-+/* DOWNLOAD_DATASET_CONTINUE command, DATA3 field definition (address 4,size 8, lsb 0, unsigned) */
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA3_LSB         0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA3_MASK        0xff
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA3_MIN         0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA3_MAX         255
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA3_DATA3_MIN  0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA3_DATA3_MAX  255
-+/* DOWNLOAD_DATASET_CONTINUE command, DATA4 field definition (address 5,size 8, lsb 0, unsigned) */
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA4_LSB         0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA4_MASK        0xff
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA4_MIN         0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA4_MAX         255
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA4_DATA4_MIN  0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA4_DATA4_MAX  255
-+/* DOWNLOAD_DATASET_CONTINUE command, DATA5 field definition (address 6,size 8, lsb 0, unsigned) */
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA5_LSB         0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA5_MASK        0xff
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA5_MIN         0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA5_MAX         255
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA5_DATA5_MIN  0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA5_DATA5_MAX  255
-+/* DOWNLOAD_DATASET_CONTINUE command, DATA6 field definition (address 7,size 8, lsb 0, unsigned) */
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA6_LSB         0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA6_MASK        0xff
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA6_MIN         0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA6_MAX         255
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA6_DATA6_MIN  0
-+#define Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD_DATA6_DATA6_MAX  255
-+#endif /* Si2168B_DOWNLOAD_DATASET_CONTINUE_CMD */
-+
-+/* Si2168B_DOWNLOAD_DATASET_START command definition */
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD 0xb8
-+
-+#ifdef Si2168B_DOWNLOAD_DATASET_START_CMD
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_CODE 0x0100b8
-+
-+typedef struct { /* Si2168B_DOWNLOAD_DATASET_START_CMD_struct */
-+	u8  dataset_id;
-+	u8  dataset_checksum;
-+	u8  data0;
-+	u8  data1;
-+	u8  data2;
-+	u8  data3;
-+	u8  data4;
-+} Si2168B_DOWNLOAD_DATASET_START_CMD_struct;
-+
-+/* DOWNLOAD_DATASET_START command, DATASET_ID field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_ID_LSB         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_ID_MASK        0xff
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_ID_MIN         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_ID_MAX         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_ID_RFU  0
-+/* DOWNLOAD_DATASET_START command, DATASET_CHECKSUM field definition (address 2,size 8, lsb 0, unsigned) */
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_CHECKSUM_LSB         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_CHECKSUM_MASK        0xff
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_CHECKSUM_MIN         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_CHECKSUM_MAX         255
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_CHECKSUM_DATASET_CHECKSUM_MIN  0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATASET_CHECKSUM_DATASET_CHECKSUM_MAX  255
-+/* DOWNLOAD_DATASET_START command, DATA0 field definition (address 3,size 8, lsb 0, unsigned) */
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA0_LSB         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA0_MASK        0xff
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA0_MIN         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA0_MAX         255
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA0_DATA0_MIN  0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA0_DATA0_MAX  255
-+/* DOWNLOAD_DATASET_START command, DATA1 field definition (address 4,size 8, lsb 0, unsigned) */
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA1_LSB         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA1_MASK        0xff
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA1_MIN         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA1_MAX         255
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA1_DATA1_MIN  0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA1_DATA1_MAX  255
-+/* DOWNLOAD_DATASET_START command, DATA2 field definition (address 5,size 8, lsb 0, unsigned) */
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA2_LSB         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA2_MASK        0xff
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA2_MIN         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA2_MAX         255
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA2_DATA2_MIN  0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA2_DATA2_MAX  255
-+/* DOWNLOAD_DATASET_START command, DATA3 field definition (address 6,size 8, lsb 0, unsigned) */
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA3_LSB         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA3_MASK        0xff
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA3_MIN         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA3_MAX         255
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA3_DATA3_MIN  0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA3_DATA3_MAX  255
-+/* DOWNLOAD_DATASET_START command, DATA4 field definition (address 7,size 8, lsb 0, unsigned) */
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA4_LSB         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA4_MASK        0xff
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA4_MIN         0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA4_MAX         255
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA4_DATA4_MIN  0
-+#define Si2168B_DOWNLOAD_DATASET_START_CMD_DATA4_DATA4_MAX  255
-+#endif /* Si2168B_DOWNLOAD_DATASET_START_CMD */
-+
-+/* Si2168B_DVBC_STATUS command definition */
-+#define Si2168B_DVBC_STATUS_CMD 0x90
-+
-+#ifdef Si2168B_DVBC_STATUS_CMD
-+#define Si2168B_DVBC_STATUS_CMD_CODE 0x010090
-+
-+typedef struct { /* Si2168B_DVBC_STATUS_CMD_struct */
-+	u8  intack;
-+} Si2168B_DVBC_STATUS_CMD_struct;
-+
-+typedef struct { /* Si2168B_DVBC_STATUS_CMD_REPLY_struct */
-+	u8  pclint;
-+	u8  dlint;
-+	u8  berint;
-+	u8  uncorint;
-+	u8  pcl;
-+	u8  dl;
-+	u8  ber;
-+	u8  uncor;
-+	u8  cnr;
-+	s16 afc_freq;
-+	s16 timing_offset;
-+	u8  constellation;
-+	u8  sp_inv;
-+}  Si2168B_DVBC_STATUS_CMD_REPLY_struct;
-+
-+/* DVBC_STATUS command, INTACK field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2168B_DVBC_STATUS_CMD_INTACK_LSB         0
-+#define Si2168B_DVBC_STATUS_CMD_INTACK_MASK        0x01
-+#define Si2168B_DVBC_STATUS_CMD_INTACK_MIN         0
-+#define Si2168B_DVBC_STATUS_CMD_INTACK_MAX         1
-+#define Si2168B_DVBC_STATUS_CMD_INTACK_CLEAR  1
-+#define Si2168B_DVBC_STATUS_CMD_INTACK_OK     0
-+/* DVBC_STATUS command, PCLINT field definition (address 1, size 1, lsb 1, unsigned)*/
-+#define Si2168B_DVBC_STATUS_RESPONSE_PCLINT_LSB         1
-+#define Si2168B_DVBC_STATUS_RESPONSE_PCLINT_MASK        0x01
-+#define Si2168B_DVBC_STATUS_RESPONSE_PCLINT_CHANGED    1
-+#define Si2168B_DVBC_STATUS_RESPONSE_PCLINT_NO_CHANGE  0
-+/* DVBC_STATUS command, DLINT field definition (address 1, size 1, lsb 2, unsigned)*/
-+#define Si2168B_DVBC_STATUS_RESPONSE_DLINT_LSB         2
-+#define Si2168B_DVBC_STATUS_RESPONSE_DLINT_MASK        0x01
-+#define Si2168B_DVBC_STATUS_RESPONSE_DLINT_CHANGED    1
-+#define Si2168B_DVBC_STATUS_RESPONSE_DLINT_NO_CHANGE  0
-+/* DVBC_STATUS command, BERINT field definition (address 1, size 1, lsb 3, unsigned)*/
-+#define Si2168B_DVBC_STATUS_RESPONSE_BERINT_LSB         3
-+#define Si2168B_DVBC_STATUS_RESPONSE_BERINT_MASK        0x01
-+#define Si2168B_DVBC_STATUS_RESPONSE_BERINT_CHANGED    1
-+#define Si2168B_DVBC_STATUS_RESPONSE_BERINT_NO_CHANGE  0
-+/* DVBC_STATUS command, UNCORINT field definition (address 1, size 1, lsb 4, unsigned)*/
-+#define Si2168B_DVBC_STATUS_RESPONSE_UNCORINT_LSB         4
-+#define Si2168B_DVBC_STATUS_RESPONSE_UNCORINT_MASK        0x01
-+#define Si2168B_DVBC_STATUS_RESPONSE_UNCORINT_CHANGED    1
-+#define Si2168B_DVBC_STATUS_RESPONSE_UNCORINT_NO_CHANGE  0
-+/* DVBC_STATUS command, PCL field definition (address 2, size 1, lsb 1, unsigned)*/
-+#define Si2168B_DVBC_STATUS_RESPONSE_PCL_LSB         1
-+#define Si2168B_DVBC_STATUS_RESPONSE_PCL_MASK        0x01
-+#define Si2168B_DVBC_STATUS_RESPONSE_PCL_LOCKED   1
-+#define Si2168B_DVBC_STATUS_RESPONSE_PCL_NO_LOCK  0
-+/* DVBC_STATUS command, DL field definition (address 2, size 1, lsb 2, unsigned)*/
-+#define Si2168B_DVBC_STATUS_RESPONSE_DL_LSB         2
-+#define Si2168B_DVBC_STATUS_RESPONSE_DL_MASK        0x01
-+#define Si2168B_DVBC_STATUS_RESPONSE_DL_LOCKED   1
-+#define Si2168B_DVBC_STATUS_RESPONSE_DL_NO_LOCK  0
-+/* DVBC_STATUS command, BER field definition (address 2, size 1, lsb 3, unsigned)*/
-+#define Si2168B_DVBC_STATUS_RESPONSE_BER_LSB         3
-+#define Si2168B_DVBC_STATUS_RESPONSE_BER_MASK        0x01
-+#define Si2168B_DVBC_STATUS_RESPONSE_BER_BER_ABOVE  1
-+#define Si2168B_DVBC_STATUS_RESPONSE_BER_BER_BELOW  0
-+/* DVBC_STATUS command, UNCOR field definition (address 2, size 1, lsb 4, unsigned)*/
-+#define Si2168B_DVBC_STATUS_RESPONSE_UNCOR_LSB         4
-+#define Si2168B_DVBC_STATUS_RESPONSE_UNCOR_MASK        0x01
-+#define Si2168B_DVBC_STATUS_RESPONSE_UNCOR_NO_UNCOR_FOUND  0
-+#define Si2168B_DVBC_STATUS_RESPONSE_UNCOR_UNCOR_FOUND     1
-+/* DVBC_STATUS command, CNR field definition (address 3, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DVBC_STATUS_RESPONSE_CNR_LSB         0
-+#define Si2168B_DVBC_STATUS_RESPONSE_CNR_MASK        0xff
-+/* DVBC_STATUS command, AFC_FREQ field definition (address 4, size 16, lsb 0, signed)*/
-+#define Si2168B_DVBC_STATUS_RESPONSE_AFC_FREQ_LSB         0
-+#define Si2168B_DVBC_STATUS_RESPONSE_AFC_FREQ_MASK        0xffff
-+#define Si2168B_DVBC_STATUS_RESPONSE_AFC_FREQ_SHIFT       16
-+/* DVBC_STATUS command, TIMING_OFFSET field definition (address 6, size 16, lsb 0, signed)*/
-+#define Si2168B_DVBC_STATUS_RESPONSE_TIMING_OFFSET_LSB         0
-+#define Si2168B_DVBC_STATUS_RESPONSE_TIMING_OFFSET_MASK        0xffff
-+#define Si2168B_DVBC_STATUS_RESPONSE_TIMING_OFFSET_SHIFT       16
-+/* DVBC_STATUS command, CONSTELLATION field definition (address 8, size 6, lsb 0, unsigned)*/
-+#define Si2168B_DVBC_STATUS_RESPONSE_CONSTELLATION_LSB         0
-+#define Si2168B_DVBC_STATUS_RESPONSE_CONSTELLATION_MASK        0x3f
-+#define Si2168B_DVBC_STATUS_RESPONSE_CONSTELLATION_QAM128  10
-+#define Si2168B_DVBC_STATUS_RESPONSE_CONSTELLATION_QAM16   7
-+#define Si2168B_DVBC_STATUS_RESPONSE_CONSTELLATION_QAM256  11
-+#define Si2168B_DVBC_STATUS_RESPONSE_CONSTELLATION_QAM32   8
-+#define Si2168B_DVBC_STATUS_RESPONSE_CONSTELLATION_QAM64   9
-+/* DVBC_STATUS command, SP_INV field definition (address 8, size 1, lsb 6, unsigned)*/
-+#define Si2168B_DVBC_STATUS_RESPONSE_SP_INV_LSB         6
-+#define Si2168B_DVBC_STATUS_RESPONSE_SP_INV_MASK        0x01
-+#define Si2168B_DVBC_STATUS_RESPONSE_SP_INV_INVERTED  1
-+#define Si2168B_DVBC_STATUS_RESPONSE_SP_INV_NORMAL    0
-+
-+#endif /* Si2168B_DVBC_STATUS_CMD */
-+
-+/* Si2168B_DVBT2_FEF command definition */
-+#define Si2168B_DVBT2_FEF_CMD 0x51
-+
-+#ifdef Si2168B_DVBT2_FEF_CMD
-+#define Si2168B_DVBT2_FEF_CMD_CODE 0x010051
-+
-+typedef struct { /* Si2168B_DVBT2_FEF_CMD_struct */
-+	u8  fef_tuner_flag;
-+	u8  fef_tuner_flag_inv;
-+} Si2168B_DVBT2_FEF_CMD_struct;
-+
-+typedef struct { /* Si2168B_DVBT2_FEF_CMD_REPLY_struct */
-+	u8  fef_type;
-+	u32 fef_length;
-+	u32 fef_repetition;
-+}  Si2168B_DVBT2_FEF_CMD_REPLY_struct;
-+
-+/* DVBT2_FEF command, FEF_TUNER_FLAG field definition (address 1,size 3, lsb 0, unsigned) */
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_LSB         0
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MASK        0x07
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MIN         0
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MAX         5
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_A       2
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_B       3
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_C       4
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_MP_D       5
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_NOT_USED   1
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_NO_CHANGE  0
-+/* DVBT2_FEF command, FEF_TUNER_FLAG_INV field definition (address 1,size 1, lsb 3, unsigned) */
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_INV_LSB         3
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_INV_MASK        0x01
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_INV_MIN         0
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_INV_MAX         1
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_INV_FEF_HIGH  0
-+#define Si2168B_DVBT2_FEF_CMD_FEF_TUNER_FLAG_INV_FEF_LOW   1
-+/* DVBT2_FEF command, FEF_TYPE field definition (address 1, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_FEF_RESPONSE_FEF_TYPE_LSB         0
-+#define Si2168B_DVBT2_FEF_RESPONSE_FEF_TYPE_MASK        0x0f
-+/* DVBT2_FEF command, FEF_LENGTH field definition (address 4, size 32, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_FEF_RESPONSE_FEF_LENGTH_LSB         0
-+#define Si2168B_DVBT2_FEF_RESPONSE_FEF_LENGTH_MASK        0xffffffff
-+/* DVBT2_FEF command, FEF_REPETITION field definition (address 8, size 32, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_FEF_RESPONSE_FEF_REPETITION_LSB         0
-+#define Si2168B_DVBT2_FEF_RESPONSE_FEF_REPETITION_MASK        0xffffffff
-+
-+#endif /* Si2168B_DVBT2_FEF_CMD */
-+
-+/* Si2168B_DVBT2_PLP_INFO command definition */
-+#define Si2168B_DVBT2_PLP_INFO_CMD 0x53
-+
-+#ifdef Si2168B_DVBT2_PLP_INFO_CMD
-+#define Si2168B_DVBT2_PLP_INFO_CMD_CODE 0x010053
-+
-+typedef struct { /* Si2168B_DVBT2_PLP_INFO_CMD_struct */
-+	u8  plp_index;
-+} Si2168B_DVBT2_PLP_INFO_CMD_struct;
-+
-+typedef struct { /* Si2168B_DVBT2_PLP_INFO_CMD_REPLY_struct */
-+	u8  plp_id;
-+	u8  reserved_1_1;
-+	u8  in_band_b_flag;
-+	u8  in_band_a_flag;
-+	u8  static_flag;
-+	u8  plp_mode;
-+	u8  reserved_1_2;
-+	u8  static_padding_flag;
-+	u8  plp_payload_type;
-+	u8  plp_type;
-+	u8  first_frame_idx_msb;
-+	u8  first_rf_idx;
-+	u8  ff_flag;
-+	u8  plp_group_id_msb;
-+	u8  first_frame_idx_lsb;
-+	u8  plp_mod_msb;
-+	u8  plp_cod;
-+	u8  plp_group_id_lsb;
-+	u8  plp_num_blocks_max_msb;
-+	u8  plp_fec_type;
-+	u8  plp_rot;
-+	u8  plp_mod_lsb;
-+	u8  frame_interval_msb;
-+	u8  plp_num_blocks_max_lsb;
-+	u8  time_il_length_msb;
-+	u8  frame_interval_lsb;
-+	u8  time_il_type;
-+	u8  time_il_length_lsb;
-+}  Si2168B_DVBT2_PLP_INFO_CMD_REPLY_struct;
-+
-+/* DVBT2_PLP_INFO command, PLP_INDEX field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2168B_DVBT2_PLP_INFO_CMD_PLP_INDEX_LSB         0
-+#define Si2168B_DVBT2_PLP_INFO_CMD_PLP_INDEX_MASK        0xff
-+#define Si2168B_DVBT2_PLP_INFO_CMD_PLP_INDEX_MIN         0
-+#define Si2168B_DVBT2_PLP_INFO_CMD_PLP_INDEX_MAX         255
-+/* DVBT2_PLP_INFO command, PLP_ID field definition (address 1, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_ID_LSB         0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_ID_MASK        0xff
-+/* DVBT2_PLP_INFO command, RESERVED_1_1 field definition (address 10, size 6, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_RESERVED_1_1_LSB         0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_RESERVED_1_1_MASK        0x3f
-+/* DVBT2_PLP_INFO command, IN_BAND_B_FLAG field definition (address 10, size 1, lsb 6, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_IN_BAND_B_FLAG_LSB         6
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_IN_BAND_B_FLAG_MASK        0x01
-+/* DVBT2_PLP_INFO command, IN_BAND_A_FLAG field definition (address 10, size 1, lsb 7, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_IN_BAND_A_FLAG_LSB         7
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_IN_BAND_A_FLAG_MASK        0x01
-+/* DVBT2_PLP_INFO command, STATIC_FLAG field definition (address 11, size 1, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_STATIC_FLAG_LSB         0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_STATIC_FLAG_MASK        0x01
-+/* DVBT2_PLP_INFO command, PLP_MODE field definition (address 11, size 2, lsb 1, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MODE_LSB         1
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MODE_MASK        0x03
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MODE_HIGH_EFFICIENCY_MODE  2
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MODE_NORMAL_MODE           1
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MODE_NOT_SPECIFIED         0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MODE_RESERVED              3
-+/* DVBT2_PLP_INFO command, RESERVED_1_2 field definition (address 11, size 5, lsb 3, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_RESERVED_1_2_LSB         3
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_RESERVED_1_2_MASK        0x1f
-+/* DVBT2_PLP_INFO command, STATIC_PADDING_FLAG field definition (address 12, size 1, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_STATIC_PADDING_FLAG_LSB         0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_STATIC_PADDING_FLAG_MASK        0x01
-+/* DVBT2_PLP_INFO command, PLP_PAYLOAD_TYPE field definition (address 2, size 5, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_PAYLOAD_TYPE_LSB         0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_PAYLOAD_TYPE_MASK        0x1f
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_PAYLOAD_TYPE_GCS   1
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_PAYLOAD_TYPE_GFPS  0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_PAYLOAD_TYPE_GSE   2
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_PAYLOAD_TYPE_TS    3
-+/* DVBT2_PLP_INFO command, PLP_TYPE field definition (address 2, size 3, lsb 5, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_TYPE_LSB         5
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_TYPE_MASK        0x07
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_TYPE_COMMON      0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_TYPE_DATA_TYPE1  1
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_TYPE_DATA_TYPE2  2
-+/* DVBT2_PLP_INFO command, FIRST_FRAME_IDX_MSB field definition (address 3, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_FIRST_FRAME_IDX_MSB_LSB         0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_FIRST_FRAME_IDX_MSB_MASK        0x0f
-+/* DVBT2_PLP_INFO command, FIRST_RF_IDX field definition (address 3, size 3, lsb 4, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_FIRST_RF_IDX_LSB         4
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_FIRST_RF_IDX_MASK        0x07
-+/* DVBT2_PLP_INFO command, FF_FLAG field definition (address 3, size 1, lsb 7, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_FF_FLAG_LSB         7
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_FF_FLAG_MASK        0x01
-+/* DVBT2_PLP_INFO command, PLP_GROUP_ID_MSB field definition (address 4, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_GROUP_ID_MSB_LSB         0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_GROUP_ID_MSB_MASK        0x0f
-+/* DVBT2_PLP_INFO command, FIRST_FRAME_IDX_LSB field definition (address 4, size 4, lsb 4, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_FIRST_FRAME_IDX_LSB_LSB         4
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_FIRST_FRAME_IDX_LSB_MASK        0x0f
-+/* DVBT2_PLP_INFO command, PLP_MOD_MSB field definition (address 5, size 1, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MOD_MSB_LSB         0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MOD_MSB_MASK        0x01
-+/* DVBT2_PLP_INFO command, PLP_COD field definition (address 5, size 3, lsb 1, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_COD_LSB         1
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_COD_MASK        0x07
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_COD_1_2  0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_COD_2_3  2
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_COD_3_4  3
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_COD_3_5  1
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_COD_4_5  4
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_COD_5_6  5
-+/* DVBT2_PLP_INFO command, PLP_GROUP_ID_LSB field definition (address 5, size 4, lsb 4, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_GROUP_ID_LSB_LSB         4
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_GROUP_ID_LSB_MASK        0x0f
-+/* DVBT2_PLP_INFO command, PLP_NUM_BLOCKS_MAX_MSB field definition (address 6, size 3, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_NUM_BLOCKS_MAX_MSB_LSB         0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_NUM_BLOCKS_MAX_MSB_MASK        0x07
-+/* DVBT2_PLP_INFO command, PLP_FEC_TYPE field definition (address 6, size 2, lsb 3, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_FEC_TYPE_LSB         3
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_FEC_TYPE_MASK        0x03
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_FEC_TYPE_16K_LDPC  0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_FEC_TYPE_64K_LDPC  1
-+/* DVBT2_PLP_INFO command, PLP_ROT field definition (address 6, size 1, lsb 5, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_ROT_LSB         5
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_ROT_MASK        0x01
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_ROT_NOT_ROTATED  0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_ROT_ROTATED      1
-+/* DVBT2_PLP_INFO command, PLP_MOD_LSB field definition (address 6, size 2, lsb 6, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MOD_LSB_LSB         6
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_MOD_LSB_MASK        0x03
-+/* DVBT2_PLP_INFO command, FRAME_INTERVAL_MSB field definition (address 7, size 1, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_FRAME_INTERVAL_MSB_LSB         0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_FRAME_INTERVAL_MSB_MASK        0x01
-+/* DVBT2_PLP_INFO command, PLP_NUM_BLOCKS_MAX_LSB field definition (address 7, size 7, lsb 1, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_NUM_BLOCKS_MAX_LSB_LSB         1
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_PLP_NUM_BLOCKS_MAX_LSB_MASK        0x7f
-+/* DVBT2_PLP_INFO command, TIME_IL_LENGTH_MSB field definition (address 8, size 1, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_TIME_IL_LENGTH_MSB_LSB         0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_TIME_IL_LENGTH_MSB_MASK        0x01
-+/* DVBT2_PLP_INFO command, FRAME_INTERVAL_LSB field definition (address 8, size 7, lsb 1, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_FRAME_INTERVAL_LSB_LSB         1
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_FRAME_INTERVAL_LSB_MASK        0x7f
-+/* DVBT2_PLP_INFO command, TIME_IL_TYPE field definition (address 9, size 1, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_TIME_IL_TYPE_LSB         0
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_TIME_IL_TYPE_MASK        0x01
-+/* DVBT2_PLP_INFO command, TIME_IL_LENGTH_LSB field definition (address 9, size 7, lsb 1, unsigned)*/
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_TIME_IL_LENGTH_LSB_LSB         1
-+#define Si2168B_DVBT2_PLP_INFO_RESPONSE_TIME_IL_LENGTH_LSB_MASK        0x7f
-+
-+#endif /* Si2168B_DVBT2_PLP_INFO_CMD */
-+
-+/* Si2168B_DVBT2_PLP_SELECT command definition */
-+#define Si2168B_DVBT2_PLP_SELECT_CMD 0x52
-+
-+#ifdef Si2168B_DVBT2_PLP_SELECT_CMD
-+#define Si2168B_DVBT2_PLP_SELECT_CMD_CODE 0x010052
-+
-+typedef struct { /* Si2168B_DVBT2_PLP_SELECT_CMD_struct */
-+	u8  plp_id;
-+	u8  plp_id_sel_mode;
-+} Si2168B_DVBT2_PLP_SELECT_CMD_struct;
-+
-+/* DVBT2_PLP_SELECT command, PLP_ID field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_LSB         0
-+#define Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_MASK        0xff
-+#define Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_MIN         0
-+#define Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_MAX         255
-+/* DVBT2_PLP_SELECT command, PLP_ID_SEL_MODE field definition (address 2,size 1, lsb 0, unsigned) */
-+#define Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_SEL_MODE_LSB         0
-+#define Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_SEL_MODE_MASK        0x01
-+#define Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_SEL_MODE_MIN         0
-+#define Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_SEL_MODE_MAX         1
-+#define Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_SEL_MODE_AUTO    0
-+#define Si2168B_DVBT2_PLP_SELECT_CMD_PLP_ID_SEL_MODE_MANUAL  1
-+#endif /* Si2168B_DVBT2_PLP_SELECT_CMD */
-+
-+/* Si2168B_DVBT2_STATUS command definition */
-+#define Si2168B_DVBT2_STATUS_CMD 0x50
-+
-+#ifdef Si2168B_DVBT2_STATUS_CMD
-+#define Si2168B_DVBT2_STATUS_CMD_CODE 0x010050
-+
-+typedef struct { /* Si2168B_DVBT2_STATUS_CMD_struct */
-+	u8  intack;
-+} Si2168B_DVBT2_STATUS_CMD_struct;
-+
-+typedef struct { /* Si2168B_DVBT2_STATUS_CMD_REPLY_struct */
-+	u8  pclint;
-+	u8  dlint;
-+	u8  berint;
-+	u8  uncorint;
-+	u8  notdvbt2int;
-+	u8  num_plp;
-+	u8  pilot_pattern;
-+	u8  tx_mode;
-+	u8  rotated;
-+	u8  short_frame;
-+	u8  t2_mode;
-+	u8  code_rate;
-+	u8  t2_version;
-+	u8  plp_id;
-+	u8  pcl;
-+	u8  dl;
-+	u8  ber;
-+	u8  uncor;
-+	u8  notdvbt2;
-+	u8  cnr;
-+	s16 afc_freq;
-+	s16 timing_offset;
-+	u8  constellation;
-+	u8  sp_inv;
-+	u8  fef;
-+	u8  fft_mode;
-+	u8  guard_int;
-+	u8  bw_ext;
-+}  Si2168B_DVBT2_STATUS_CMD_REPLY_struct;
-+
-+/* DVBT2_STATUS command, INTACK field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2168B_DVBT2_STATUS_CMD_INTACK_LSB         0
-+#define Si2168B_DVBT2_STATUS_CMD_INTACK_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_CMD_INTACK_MIN         0
-+#define Si2168B_DVBT2_STATUS_CMD_INTACK_MAX         1
-+#define Si2168B_DVBT2_STATUS_CMD_INTACK_CLEAR  1
-+#define Si2168B_DVBT2_STATUS_CMD_INTACK_OK     0
-+/* DVBT2_STATUS command, PCLINT field definition (address 1, size 1, lsb 1, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PCLINT_LSB         1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PCLINT_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PCLINT_CHANGED    1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PCLINT_NO_CHANGE  0
-+/* DVBT2_STATUS command, DLINT field definition (address 1, size 1, lsb 2, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_DLINT_LSB         2
-+#define Si2168B_DVBT2_STATUS_RESPONSE_DLINT_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_DLINT_CHANGED    1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_DLINT_NO_CHANGE  0
-+/* DVBT2_STATUS command, BERINT field definition (address 1, size 1, lsb 3, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_BERINT_LSB         3
-+#define Si2168B_DVBT2_STATUS_RESPONSE_BERINT_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_BERINT_CHANGED    1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_BERINT_NO_CHANGE  0
-+/* DVBT2_STATUS command, UNCORINT field definition (address 1, size 1, lsb 4, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_UNCORINT_LSB         4
-+#define Si2168B_DVBT2_STATUS_RESPONSE_UNCORINT_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_UNCORINT_CHANGED    1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_UNCORINT_NO_CHANGE  0
-+/* DVBT2_STATUS command, NOTDVBT2INT field definition (address 1, size 1, lsb 5, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_NOTDVBT2INT_LSB         5
-+#define Si2168B_DVBT2_STATUS_RESPONSE_NOTDVBT2INT_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_NOTDVBT2INT_CHANGED    1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_NOTDVBT2INT_NO_CHANGE  0
-+/* DVBT2_STATUS command, NUM_PLP field definition (address 10, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_NUM_PLP_LSB         0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_NUM_PLP_MASK        0xff
-+/* DVBT2_STATUS command, PILOT_PATTERN field definition (address 11, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PILOT_PATTERN_LSB         0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PILOT_PATTERN_MASK        0x0f
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PILOT_PATTERN_PP1  0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PILOT_PATTERN_PP2  1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PILOT_PATTERN_PP3  2
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PILOT_PATTERN_PP4  3
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PILOT_PATTERN_PP5  4
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PILOT_PATTERN_PP6  5
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PILOT_PATTERN_PP7  6
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PILOT_PATTERN_PP8  7
-+/* DVBT2_STATUS command, TX_MODE field definition (address 11, size 1, lsb 4, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_TX_MODE_LSB         4
-+#define Si2168B_DVBT2_STATUS_RESPONSE_TX_MODE_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_TX_MODE_MISO  1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_TX_MODE_SISO  0
-+/* DVBT2_STATUS command, ROTATED field definition (address 11, size 1, lsb 5, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_ROTATED_LSB         5
-+#define Si2168B_DVBT2_STATUS_RESPONSE_ROTATED_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_ROTATED_NORMAL   0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_ROTATED_ROTATED  1
-+/* DVBT2_STATUS command, SHORT_FRAME field definition (address 11, size 1, lsb 6, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_SHORT_FRAME_LSB         6
-+#define Si2168B_DVBT2_STATUS_RESPONSE_SHORT_FRAME_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_SHORT_FRAME_16K_LDPC  0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_SHORT_FRAME_64K_LDPC  1
-+/* DVBT2_STATUS command, T2_MODE field definition (address 11, size 1, lsb 7, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_T2_MODE_LSB         7
-+#define Si2168B_DVBT2_STATUS_RESPONSE_T2_MODE_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_T2_MODE_BASE  0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_T2_MODE_LITE  1
-+/* DVBT2_STATUS command, CODE_RATE field definition (address 12, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CODE_RATE_LSB         0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CODE_RATE_MASK        0x0f
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CODE_RATE_1_2  1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CODE_RATE_1_3  10
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CODE_RATE_2_3  2
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CODE_RATE_2_5  12
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CODE_RATE_3_4  3
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CODE_RATE_3_5  13
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CODE_RATE_4_5  4
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CODE_RATE_5_6  5
-+/* DVBT2_STATUS command, T2_VERSION field definition (address 12, size 4, lsb 4, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_T2_VERSION_LSB         4
-+#define Si2168B_DVBT2_STATUS_RESPONSE_T2_VERSION_MASK        0x0f
-+#define Si2168B_DVBT2_STATUS_RESPONSE_T2_VERSION_1_1_1  0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_T2_VERSION_1_2_1  1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_T2_VERSION_1_3_1  2
-+/* DVBT2_STATUS command, PLP_ID field definition (address 13, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PLP_ID_LSB         0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PLP_ID_MASK        0xff
-+/* DVBT2_STATUS command, PCL field definition (address 2, size 1, lsb 1, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PCL_LSB         1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PCL_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PCL_LOCKED   1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_PCL_NO_LOCK  0
-+/* DVBT2_STATUS command, DL field definition (address 2, size 1, lsb 2, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_DL_LSB         2
-+#define Si2168B_DVBT2_STATUS_RESPONSE_DL_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_DL_LOCKED   1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_DL_NO_LOCK  0
-+/* DVBT2_STATUS command, BER field definition (address 2, size 1, lsb 3, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_BER_LSB         3
-+#define Si2168B_DVBT2_STATUS_RESPONSE_BER_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_BER_BER_ABOVE  1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_BER_BER_BELOW  0
-+/* DVBT2_STATUS command, UNCOR field definition (address 2, size 1, lsb 4, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_UNCOR_LSB         4
-+#define Si2168B_DVBT2_STATUS_RESPONSE_UNCOR_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_UNCOR_NO_UNCOR_FOUND  0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_UNCOR_UNCOR_FOUND     1
-+/* DVBT2_STATUS command, NOTDVBT2 field definition (address 2, size 1, lsb 5, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_NOTDVBT2_LSB         5
-+#define Si2168B_DVBT2_STATUS_RESPONSE_NOTDVBT2_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_NOTDVBT2_DVBT2      0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_NOTDVBT2_NOT_DVBT2  1
-+/* DVBT2_STATUS command, CNR field definition (address 3, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CNR_LSB         0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CNR_MASK        0xff
-+/* DVBT2_STATUS command, AFC_FREQ field definition (address 4, size 16, lsb 0, signed)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_AFC_FREQ_LSB         0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_AFC_FREQ_MASK        0xffff
-+#define Si2168B_DVBT2_STATUS_RESPONSE_AFC_FREQ_SHIFT       16
-+/* DVBT2_STATUS command, TIMING_OFFSET field definition (address 6, size 16, lsb 0, signed)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_TIMING_OFFSET_LSB         0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_TIMING_OFFSET_MASK        0xffff
-+#define Si2168B_DVBT2_STATUS_RESPONSE_TIMING_OFFSET_SHIFT       16
-+/* DVBT2_STATUS command, CONSTELLATION field definition (address 8, size 6, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_LSB         0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_MASK        0x3f
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_QAM128  10
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_QAM16   7
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_QAM256  11
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_QAM32   8
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_QAM64   9
-+#define Si2168B_DVBT2_STATUS_RESPONSE_CONSTELLATION_QPSK    3
-+/* DVBT2_STATUS command, SP_INV field definition (address 8, size 1, lsb 6, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_SP_INV_LSB         6
-+#define Si2168B_DVBT2_STATUS_RESPONSE_SP_INV_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_SP_INV_INVERTED  1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_SP_INV_NORMAL    0
-+/* DVBT2_STATUS command, FEF field definition (address 8, size 1, lsb 7, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_FEF_LSB         7
-+#define Si2168B_DVBT2_STATUS_RESPONSE_FEF_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_FEF_FEF     1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_FEF_NO_FEF  0
-+/* DVBT2_STATUS command, FFT_MODE field definition (address 9, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_LSB         0
-+#define Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_MASK        0x0f
-+#define Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_16K  14
-+#define Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_1K   10
-+#define Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_2K   11
-+#define Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_32K  15
-+#define Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_4K   12
-+#define Si2168B_DVBT2_STATUS_RESPONSE_FFT_MODE_8K   13
-+/* DVBT2_STATUS command, GUARD_INT field definition (address 9, size 3, lsb 4, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_LSB         4
-+#define Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_MASK        0x07
-+#define Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_19_128  6
-+#define Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_19_256  7
-+#define Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_1_128   5
-+#define Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_1_16    2
-+#define Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_1_32    1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_1_4     4
-+#define Si2168B_DVBT2_STATUS_RESPONSE_GUARD_INT_1_8     3
-+/* DVBT2_STATUS command, BW_EXT field definition (address 9, size 1, lsb 7, unsigned)*/
-+#define Si2168B_DVBT2_STATUS_RESPONSE_BW_EXT_LSB         7
-+#define Si2168B_DVBT2_STATUS_RESPONSE_BW_EXT_MASK        0x01
-+#define Si2168B_DVBT2_STATUS_RESPONSE_BW_EXT_EXTENDED  1
-+#define Si2168B_DVBT2_STATUS_RESPONSE_BW_EXT_NORMAL    0
-+
-+#endif /* Si2168B_DVBT2_STATUS_CMD */
-+
-+/* Si2168B_DVBT2_TX_ID command definition */
-+#define Si2168B_DVBT2_TX_ID_CMD 0x54
-+
-+#ifdef Si2168B_DVBT2_TX_ID_CMD
-+#define Si2168B_DVBT2_TX_ID_CMD_CODE 0x010054
-+
-+typedef struct { /* Si2168B_DVBT2_TX_ID_CMD_struct */
-+	u8  nothing;
-+} Si2168B_DVBT2_TX_ID_CMD_struct;
-+
-+typedef struct { /* Si2168B_DVBT2_TX_ID_CMD_REPLY_struct */
-+	u8  tx_id_availability;
-+	u16 cell_id;
-+	u16 network_id;
-+	u16 t2_system_id;
-+}  Si2168B_DVBT2_TX_ID_CMD_REPLY_struct;
-+
-+/* DVBT2_TX_ID command, TX_ID_AVAILABILITY field definition (address 1, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_TX_ID_RESPONSE_TX_ID_AVAILABILITY_LSB         0
-+#define Si2168B_DVBT2_TX_ID_RESPONSE_TX_ID_AVAILABILITY_MASK        0xff
-+/* DVBT2_TX_ID command, CELL_ID field definition (address 2, size 16, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_TX_ID_RESPONSE_CELL_ID_LSB         0
-+#define Si2168B_DVBT2_TX_ID_RESPONSE_CELL_ID_MASK        0xffff
-+/* DVBT2_TX_ID command, NETWORK_ID field definition (address 4, size 16, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_TX_ID_RESPONSE_NETWORK_ID_LSB         0
-+#define Si2168B_DVBT2_TX_ID_RESPONSE_NETWORK_ID_MASK        0xffff
-+/* DVBT2_TX_ID command, T2_SYSTEM_ID field definition (address 6, size 16, lsb 0, unsigned)*/
-+#define Si2168B_DVBT2_TX_ID_RESPONSE_T2_SYSTEM_ID_LSB         0
-+#define Si2168B_DVBT2_TX_ID_RESPONSE_T2_SYSTEM_ID_MASK        0xffff
-+
-+#endif /* Si2168B_DVBT2_TX_ID_CMD */
-+
-+/* Si2168B_DVBT_STATUS command definition */
-+#define Si2168B_DVBT_STATUS_CMD 0xa0
-+
-+#ifdef Si2168B_DVBT_STATUS_CMD
-+#define Si2168B_DVBT_STATUS_CMD_CODE 0x0100a0
-+
-+typedef struct { /* Si2168B_DVBT_STATUS_CMD_struct */
-+	u8  intack;
-+} Si2168B_DVBT_STATUS_CMD_struct;
-+
-+typedef struct { /* Si2168B_DVBT_STATUS_CMD_REPLY_struct */
-+	u8  pclint;
-+	u8  dlint;
-+	u8  berint;
-+	u8  uncorint;
-+	u8  notdvbtint;
-+	u8  fft_mode;
-+	u8  guard_int;
-+	u8  hierarchy;
-+	s8  tps_length;
-+	u8  pcl;
-+	u8  dl;
-+	u8  ber;
-+	u8  uncor;
-+	u8  notdvbt;
-+	u8  cnr;
-+	s16 afc_freq;
-+	s16 timing_offset;
-+	u8  constellation;
-+	u8  sp_inv;
-+	u8  rate_hp;
-+	u8  rate_lp;
-+}  Si2168B_DVBT_STATUS_CMD_REPLY_struct;
-+
-+/* DVBT_STATUS command, INTACK field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2168B_DVBT_STATUS_CMD_INTACK_LSB         0
-+#define Si2168B_DVBT_STATUS_CMD_INTACK_MASK        0x01
-+#define Si2168B_DVBT_STATUS_CMD_INTACK_MIN         0
-+#define Si2168B_DVBT_STATUS_CMD_INTACK_MAX         1
-+#define Si2168B_DVBT_STATUS_CMD_INTACK_CLEAR  1
-+#define Si2168B_DVBT_STATUS_CMD_INTACK_OK     0
-+/* DVBT_STATUS command, PCLINT field definition (address 1, size 1, lsb 1, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_PCLINT_LSB         1
-+#define Si2168B_DVBT_STATUS_RESPONSE_PCLINT_MASK        0x01
-+#define Si2168B_DVBT_STATUS_RESPONSE_PCLINT_CHANGED    1
-+#define Si2168B_DVBT_STATUS_RESPONSE_PCLINT_NO_CHANGE  0
-+/* DVBT_STATUS command, DLINT field definition (address 1, size 1, lsb 2, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_DLINT_LSB         2
-+#define Si2168B_DVBT_STATUS_RESPONSE_DLINT_MASK        0x01
-+#define Si2168B_DVBT_STATUS_RESPONSE_DLINT_CHANGED    1
-+#define Si2168B_DVBT_STATUS_RESPONSE_DLINT_NO_CHANGE  0
-+/* DVBT_STATUS command, BERINT field definition (address 1, size 1, lsb 3, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_BERINT_LSB         3
-+#define Si2168B_DVBT_STATUS_RESPONSE_BERINT_MASK        0x01
-+#define Si2168B_DVBT_STATUS_RESPONSE_BERINT_CHANGED    1
-+#define Si2168B_DVBT_STATUS_RESPONSE_BERINT_NO_CHANGE  0
-+/* DVBT_STATUS command, UNCORINT field definition (address 1, size 1, lsb 4, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_UNCORINT_LSB         4
-+#define Si2168B_DVBT_STATUS_RESPONSE_UNCORINT_MASK        0x01
-+#define Si2168B_DVBT_STATUS_RESPONSE_UNCORINT_CHANGED    1
-+#define Si2168B_DVBT_STATUS_RESPONSE_UNCORINT_NO_CHANGE  0
-+/* DVBT_STATUS command, NOTDVBTINT field definition (address 1, size 1, lsb 5, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_NOTDVBTINT_LSB         5
-+#define Si2168B_DVBT_STATUS_RESPONSE_NOTDVBTINT_MASK        0x01
-+#define Si2168B_DVBT_STATUS_RESPONSE_NOTDVBTINT_CHANGED    1
-+#define Si2168B_DVBT_STATUS_RESPONSE_NOTDVBTINT_NO_CHANGE  0
-+/* DVBT_STATUS command, FFT_MODE field definition (address 10, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_FFT_MODE_LSB         0
-+#define Si2168B_DVBT_STATUS_RESPONSE_FFT_MODE_MASK        0x0f
-+#define Si2168B_DVBT_STATUS_RESPONSE_FFT_MODE_2K  11
-+#define Si2168B_DVBT_STATUS_RESPONSE_FFT_MODE_4K  12
-+#define Si2168B_DVBT_STATUS_RESPONSE_FFT_MODE_8K  13
-+/* DVBT_STATUS command, GUARD_INT field definition (address 10, size 3, lsb 4, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_GUARD_INT_LSB         4
-+#define Si2168B_DVBT_STATUS_RESPONSE_GUARD_INT_MASK        0x07
-+#define Si2168B_DVBT_STATUS_RESPONSE_GUARD_INT_1_16  2
-+#define Si2168B_DVBT_STATUS_RESPONSE_GUARD_INT_1_32  1
-+#define Si2168B_DVBT_STATUS_RESPONSE_GUARD_INT_1_4   4
-+#define Si2168B_DVBT_STATUS_RESPONSE_GUARD_INT_1_8   3
-+/* DVBT_STATUS command, HIERARCHY field definition (address 11, size 3, lsb 0, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_HIERARCHY_LSB         0
-+#define Si2168B_DVBT_STATUS_RESPONSE_HIERARCHY_MASK        0x07
-+#define Si2168B_DVBT_STATUS_RESPONSE_HIERARCHY_ALFA1  2
-+#define Si2168B_DVBT_STATUS_RESPONSE_HIERARCHY_ALFA2  3
-+#define Si2168B_DVBT_STATUS_RESPONSE_HIERARCHY_ALFA4  5
-+#define Si2168B_DVBT_STATUS_RESPONSE_HIERARCHY_NONE   1
-+/* DVBT_STATUS command, TPS_LENGTH field definition (address 12, size 7, lsb 0, signed)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_TPS_LENGTH_LSB         0
-+#define Si2168B_DVBT_STATUS_RESPONSE_TPS_LENGTH_MASK        0x7f
-+#define Si2168B_DVBT_STATUS_RESPONSE_TPS_LENGTH_SHIFT       25
-+/* DVBT_STATUS command, PCL field definition (address 2, size 1, lsb 1, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_PCL_LSB         1
-+#define Si2168B_DVBT_STATUS_RESPONSE_PCL_MASK        0x01
-+#define Si2168B_DVBT_STATUS_RESPONSE_PCL_LOCKED   1
-+#define Si2168B_DVBT_STATUS_RESPONSE_PCL_NO_LOCK  0
-+/* DVBT_STATUS command, DL field definition (address 2, size 1, lsb 2, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_DL_LSB         2
-+#define Si2168B_DVBT_STATUS_RESPONSE_DL_MASK        0x01
-+#define Si2168B_DVBT_STATUS_RESPONSE_DL_LOCKED   1
-+#define Si2168B_DVBT_STATUS_RESPONSE_DL_NO_LOCK  0
-+/* DVBT_STATUS command, BER field definition (address 2, size 1, lsb 3, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_BER_LSB         3
-+#define Si2168B_DVBT_STATUS_RESPONSE_BER_MASK        0x01
-+#define Si2168B_DVBT_STATUS_RESPONSE_BER_BER_ABOVE  1
-+#define Si2168B_DVBT_STATUS_RESPONSE_BER_BER_BELOW  0
-+/* DVBT_STATUS command, UNCOR field definition (address 2, size 1, lsb 4, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_UNCOR_LSB         4
-+#define Si2168B_DVBT_STATUS_RESPONSE_UNCOR_MASK        0x01
-+#define Si2168B_DVBT_STATUS_RESPONSE_UNCOR_NO_UNCOR_FOUND  0
-+#define Si2168B_DVBT_STATUS_RESPONSE_UNCOR_UNCOR_FOUND     1
-+/* DVBT_STATUS command, NOTDVBT field definition (address 2, size 1, lsb 5, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_NOTDVBT_LSB         5
-+#define Si2168B_DVBT_STATUS_RESPONSE_NOTDVBT_MASK        0x01
-+#define Si2168B_DVBT_STATUS_RESPONSE_NOTDVBT_DVBT      0
-+#define Si2168B_DVBT_STATUS_RESPONSE_NOTDVBT_NOT_DVBT  1
-+/* DVBT_STATUS command, CNR field definition (address 3, size 8, lsb 0, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_CNR_LSB         0
-+#define Si2168B_DVBT_STATUS_RESPONSE_CNR_MASK        0xff
-+/* DVBT_STATUS command, AFC_FREQ field definition (address 4, size 16, lsb 0, signed)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_AFC_FREQ_LSB         0
-+#define Si2168B_DVBT_STATUS_RESPONSE_AFC_FREQ_MASK        0xffff
-+#define Si2168B_DVBT_STATUS_RESPONSE_AFC_FREQ_SHIFT       16
-+/* DVBT_STATUS command, TIMING_OFFSET field definition (address 6, size 16, lsb 0, signed)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_TIMING_OFFSET_LSB         0
-+#define Si2168B_DVBT_STATUS_RESPONSE_TIMING_OFFSET_MASK        0xffff
-+#define Si2168B_DVBT_STATUS_RESPONSE_TIMING_OFFSET_SHIFT       16
-+/* DVBT_STATUS command, CONSTELLATION field definition (address 8, size 6, lsb 0, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_CONSTELLATION_LSB         0
-+#define Si2168B_DVBT_STATUS_RESPONSE_CONSTELLATION_MASK        0x3f
-+#define Si2168B_DVBT_STATUS_RESPONSE_CONSTELLATION_QAM16  7
-+#define Si2168B_DVBT_STATUS_RESPONSE_CONSTELLATION_QAM64  9
-+#define Si2168B_DVBT_STATUS_RESPONSE_CONSTELLATION_QPSK   3
-+/* DVBT_STATUS command, SP_INV field definition (address 8, size 1, lsb 6, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_SP_INV_LSB         6
-+#define Si2168B_DVBT_STATUS_RESPONSE_SP_INV_MASK        0x01
-+#define Si2168B_DVBT_STATUS_RESPONSE_SP_INV_INVERTED  1
-+#define Si2168B_DVBT_STATUS_RESPONSE_SP_INV_NORMAL    0
-+/* DVBT_STATUS command, RATE_HP field definition (address 9, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_RATE_HP_LSB         0
-+#define Si2168B_DVBT_STATUS_RESPONSE_RATE_HP_MASK        0x0f
-+#define Si2168B_DVBT_STATUS_RESPONSE_RATE_HP_1_2  1
-+#define Si2168B_DVBT_STATUS_RESPONSE_RATE_HP_2_3  2
-+#define Si2168B_DVBT_STATUS_RESPONSE_RATE_HP_3_4  3
-+#define Si2168B_DVBT_STATUS_RESPONSE_RATE_HP_5_6  5
-+#define Si2168B_DVBT_STATUS_RESPONSE_RATE_HP_7_8  7
-+/* DVBT_STATUS command, RATE_LP field definition (address 9, size 4, lsb 4, unsigned)*/
-+#define Si2168B_DVBT_STATUS_RESPONSE_RATE_LP_LSB         4
-+#define Si2168B_DVBT_STATUS_RESPONSE_RATE_LP_MASK        0x0f
-+#define Si2168B_DVBT_STATUS_RESPONSE_RATE_LP_1_2  1
-+#define Si2168B_DVBT_STATUS_RESPONSE_RATE_LP_2_3  2
-+#define Si2168B_DVBT_STATUS_RESPONSE_RATE_LP_3_4  3
-+#define Si2168B_DVBT_STATUS_RESPONSE_RATE_LP_5_6  5
-+#define Si2168B_DVBT_STATUS_RESPONSE_RATE_LP_7_8  7
-+
-+#endif /* Si2168B_DVBT_STATUS_CMD */
-+
-+/* Si2168B_DVBT_TPS_EXTRA command definition */
-+#define Si2168B_DVBT_TPS_EXTRA_CMD 0xa1
-+
-+#ifdef Si2168B_DVBT_TPS_EXTRA_CMD
-+#define Si2168B_DVBT_TPS_EXTRA_CMD_CODE 0x0100a1
-+
-+typedef struct { /* Si2168B_DVBT_TPS_EXTRA_CMD_struct */
-+	u8  nothing;
-+} Si2168B_DVBT_TPS_EXTRA_CMD_struct;
-+
-+typedef struct { /* Si2168B_DVBT_TPS_EXTRA_CMD_REPLY_struct */
-+	u8  lptimeslice;
-+	u8  hptimeslice;
-+	u8  lpmpefec;
-+	u8  hpmpefec;
-+	u8  dvbhinter;
-+	s16 cell_id;
-+	u8  tps_res1;
-+	u8  tps_res2;
-+	u8  tps_res3;
-+	u8  tps_res4;
-+}  Si2168B_DVBT_TPS_EXTRA_CMD_REPLY_struct;
-+
-+/* DVBT_TPS_EXTRA command, LPTIMESLICE field definition (address 1, size 1, lsb 0, unsigned)*/
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_LPTIMESLICE_LSB         0
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_LPTIMESLICE_MASK        0x01
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_LPTIMESLICE_OFF  0
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_LPTIMESLICE_ON   1
-+/* DVBT_TPS_EXTRA command, HPTIMESLICE field definition (address 1, size 1, lsb 1, unsigned)*/
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_HPTIMESLICE_LSB         1
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_HPTIMESLICE_MASK        0x01
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_HPTIMESLICE_OFF  0
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_HPTIMESLICE_ON   1
-+/* DVBT_TPS_EXTRA command, LPMPEFEC field definition (address 1, size 1, lsb 2, unsigned)*/
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_LPMPEFEC_LSB         2
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_LPMPEFEC_MASK        0x01
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_LPMPEFEC_OFF  0
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_LPMPEFEC_ON   1
-+/* DVBT_TPS_EXTRA command, HPMPEFEC field definition (address 1, size 1, lsb 3, unsigned)*/
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_HPMPEFEC_LSB         3
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_HPMPEFEC_MASK        0x01
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_HPMPEFEC_OFF  0
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_HPMPEFEC_ON   1
-+/* DVBT_TPS_EXTRA command, DVBHINTER field definition (address 1, size 1, lsb 4, unsigned)*/
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_DVBHINTER_LSB         4
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_DVBHINTER_MASK        0x01
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_DVBHINTER_IN_DEPTH  1
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_DVBHINTER_NATIVE    0
-+/* DVBT_TPS_EXTRA command, CELL_ID field definition (address 2, size 16, lsb 0, signed)*/
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_CELL_ID_LSB         0
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_CELL_ID_MASK        0xffff
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_CELL_ID_SHIFT       16
-+/* DVBT_TPS_EXTRA command, TPS_RES1 field definition (address 4, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES1_LSB         0
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES1_MASK        0x0f
-+/* DVBT_TPS_EXTRA command, TPS_RES2 field definition (address 4, size 4, lsb 4, unsigned)*/
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES2_LSB         4
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES2_MASK        0x0f
-+/* DVBT_TPS_EXTRA command, TPS_RES3 field definition (address 5, size 4, lsb 0, unsigned)*/
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES3_LSB         0
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES3_MASK        0x0f
-+/* DVBT_TPS_EXTRA command, TPS_RES4 field definition (address 5, size 4, lsb 4, unsigned)*/
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES4_LSB         4
-+#define Si2168B_DVBT_TPS_EXTRA_RESPONSE_TPS_RES4_MASK        0x0f
-+
-+#endif /* Si2168B_DVBT_TPS_EXTRA_CMD */
-+
-+/* Si2168B_EXIT_BOOTLOADER command definition */
-+#define Si2168B_EXIT_BOOTLOADER_CMD 0x01
-+
-+#ifdef Si2168B_EXIT_BOOTLOADER_CMD
-+#define Si2168B_EXIT_BOOTLOADER_CMD_CODE 0x010001
-+
-+typedef struct { /* Si2168B_EXIT_BOOTLOADER_CMD_struct */
-+	u8  func;
-+	u8  ctsien;
-+} Si2168B_EXIT_BOOTLOADER_CMD_struct;
-+
-+/* EXIT_BOOTLOADER command, FUNC field definition (address 1,size 4, lsb 0, unsigned) */
-+#define Si2168B_EXIT_BOOTLOADER_CMD_FUNC_LSB         0
-+#define Si2168B_EXIT_BOOTLOADER_CMD_FUNC_MASK        0x0f
-+#define Si2168B_EXIT_BOOTLOADER_CMD_FUNC_MIN         0
-+#define Si2168B_EXIT_BOOTLOADER_CMD_FUNC_MAX         1
-+#define Si2168B_EXIT_BOOTLOADER_CMD_FUNC_BOOTLOADER  0
-+#define Si2168B_EXIT_BOOTLOADER_CMD_FUNC_NORMAL      1
-+/* EXIT_BOOTLOADER command, CTSIEN field definition (address 1,size 1, lsb 7, unsigned) */
-+#define Si2168B_EXIT_BOOTLOADER_CMD_CTSIEN_LSB         7
-+#define Si2168B_EXIT_BOOTLOADER_CMD_CTSIEN_MASK        0x01
-+#define Si2168B_EXIT_BOOTLOADER_CMD_CTSIEN_MIN         0
-+#define Si2168B_EXIT_BOOTLOADER_CMD_CTSIEN_MAX         1
-+#define Si2168B_EXIT_BOOTLOADER_CMD_CTSIEN_OFF  0
-+#define Si2168B_EXIT_BOOTLOADER_CMD_CTSIEN_ON   1
-+#endif /* Si2168B_EXIT_BOOTLOADER_CMD */
-+
-+/* Si2168B_GET_PROPERTY command definition */
-+#define Si2168B_GET_PROPERTY_CMD 0x15
-+
-+#ifdef Si2168B_GET_PROPERTY_CMD
-+#define Si2168B_GET_PROPERTY_CMD_CODE 0x010015
-+
-+typedef struct { /* Si2168B_GET_PROPERTY_CMD_struct */
-+	u8  reserved;
-+	u16 prop;
-+} Si2168B_GET_PROPERTY_CMD_struct;
-+
-+typedef struct { /* Si2168B_GET_PROPERTY_CMD_REPLY_struct */
-+	u8  reserved;
-+	u16 data;
-+}  Si2168B_GET_PROPERTY_CMD_REPLY_struct;
-+
-+/* GET_PROPERTY command, RESERVED field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2168B_GET_PROPERTY_CMD_RESERVED_LSB         0
-+#define Si2168B_GET_PROPERTY_CMD_RESERVED_MASK        0xff
-+#define Si2168B_GET_PROPERTY_CMD_RESERVED_MIN         0
-+#define Si2168B_GET_PROPERTY_CMD_RESERVED_MAX         0
-+#define Si2168B_GET_PROPERTY_CMD_RESERVED_RESERVED_MIN  0
-+#define Si2168B_GET_PROPERTY_CMD_RESERVED_RESERVED_MAX  0
-+/* GET_PROPERTY command, PROP field definition (address 2,size 16, lsb 0, unsigned) */
-+#define Si2168B_GET_PROPERTY_CMD_PROP_LSB         0
-+#define Si2168B_GET_PROPERTY_CMD_PROP_MASK        0xffff
-+#define Si2168B_GET_PROPERTY_CMD_PROP_MIN         0
-+#define Si2168B_GET_PROPERTY_CMD_PROP_MAX         65535
-+#define Si2168B_GET_PROPERTY_CMD_PROP_PROP_MIN  0
-+#define Si2168B_GET_PROPERTY_CMD_PROP_PROP_MAX  65535
-+/* GET_PROPERTY command, RESERVED field definition (address 1, size 8, lsb 0, unsigned)*/
-+#define Si2168B_GET_PROPERTY_RESPONSE_RESERVED_LSB         0
-+#define Si2168B_GET_PROPERTY_RESPONSE_RESERVED_MASK        0xff
-+/* GET_PROPERTY command, DATA field definition (address 2, size 16, lsb 0, unsigned)*/
-+#define Si2168B_GET_PROPERTY_RESPONSE_DATA_LSB         0
-+#define Si2168B_GET_PROPERTY_RESPONSE_DATA_MASK        0xffff
-+
-+#endif /* Si2168B_GET_PROPERTY_CMD */
-+
-+/* Si2168B_GET_REV command definition */
-+#define Si2168B_GET_REV_CMD 0x11
-+
-+#ifdef Si2168B_GET_REV_CMD
-+#define Si2168B_GET_REV_CMD_CODE 0x010011
-+
-+typedef struct { /* Si2168B_GET_REV_CMD_struct */
-+	u8  nothing;
-+} Si2168B_GET_REV_CMD_struct;
-+
-+typedef struct { /* Si2168B_GET_REV_CMD_REPLY_struct */
-+	u8  pn;
-+	u8  fwmajor;
-+	u8  fwminor;
-+	u16 patch;
-+	u8  cmpmajor;
-+	u8  cmpminor;
-+	u8  cmpbuild;
-+	u8  chiprev;
-+	u8  mcm_die;
-+}  Si2168B_GET_REV_CMD_REPLY_struct;
-+
-+/* GET_REV command, PN field definition (address 1, size 8, lsb 0, unsigned)*/
-+#define Si2168B_GET_REV_RESPONSE_PN_LSB         0
-+#define Si2168B_GET_REV_RESPONSE_PN_MASK        0xff
-+/* GET_REV command, FWMAJOR field definition (address 2, size 8, lsb 0, unsigned)*/
-+#define Si2168B_GET_REV_RESPONSE_FWMAJOR_LSB         0
-+#define Si2168B_GET_REV_RESPONSE_FWMAJOR_MASK        0xff
-+/* GET_REV command, FWMINOR field definition (address 3, size 8, lsb 0, unsigned)*/
-+#define Si2168B_GET_REV_RESPONSE_FWMINOR_LSB         0
-+#define Si2168B_GET_REV_RESPONSE_FWMINOR_MASK        0xff
-+/* GET_REV command, PATCH field definition (address 4, size 16, lsb 0, unsigned)*/
-+#define Si2168B_GET_REV_RESPONSE_PATCH_LSB         0
-+#define Si2168B_GET_REV_RESPONSE_PATCH_MASK        0xffff
-+/* GET_REV command, CMPMAJOR field definition (address 6, size 8, lsb 0, unsigned)*/
-+#define Si2168B_GET_REV_RESPONSE_CMPMAJOR_LSB         0
-+#define Si2168B_GET_REV_RESPONSE_CMPMAJOR_MASK        0xff
-+/* GET_REV command, CMPMINOR field definition (address 7, size 8, lsb 0, unsigned)*/
-+#define Si2168B_GET_REV_RESPONSE_CMPMINOR_LSB         0
-+#define Si2168B_GET_REV_RESPONSE_CMPMINOR_MASK        0xff
-+/* GET_REV command, CMPBUILD field definition (address 8, size 8, lsb 0, unsigned)*/
-+#define Si2168B_GET_REV_RESPONSE_CMPBUILD_LSB         0
-+#define Si2168B_GET_REV_RESPONSE_CMPBUILD_MASK        0xff
-+#define Si2168B_GET_REV_RESPONSE_CMPBUILD_CMPBUILD_MIN  0
-+#define Si2168B_GET_REV_RESPONSE_CMPBUILD_CMPBUILD_MAX  255
-+/* GET_REV command, CHIPREV field definition (address 9, size 4, lsb 0, unsigned)*/
-+#define Si2168B_GET_REV_RESPONSE_CHIPREV_LSB         0
-+#define Si2168B_GET_REV_RESPONSE_CHIPREV_MASK        0x0f
-+#define Si2168B_GET_REV_RESPONSE_CHIPREV_A  1
-+#define Si2168B_GET_REV_RESPONSE_CHIPREV_B  2
-+#define Si2168B_GET_REV_RESPONSE_CHIPREV_C  2
-+/* GET_REV command, MCM_DIE field definition (address 9, size 4, lsb 4, unsigned)*/
-+#define Si2168B_GET_REV_RESPONSE_MCM_DIE_LSB         4
-+#define Si2168B_GET_REV_RESPONSE_MCM_DIE_MASK        0x0f
-+#define Si2168B_GET_REV_RESPONSE_MCM_DIE_DIE_A   1
-+#define Si2168B_GET_REV_RESPONSE_MCM_DIE_DIE_B   2
-+#define Si2168B_GET_REV_RESPONSE_MCM_DIE_SINGLE  0
-+
-+#endif /* Si2168B_GET_REV_CMD */
-+
-+/* Si2168B_I2C_PASSTHROUGH command definition */
-+#define Si2168B_I2C_PASSTHROUGH_CMD 0xc0
-+
-+#ifdef Si2168B_I2C_PASSTHROUGH_CMD
-+#define Si2168B_I2C_PASSTHROUGH_CMD_CODE 0x0100c0
-+
-+typedef struct { /* Si2168B_I2C_PASSTHROUGH_CMD_struct */
-+	u8  subcode;
-+	u8  i2c_passthru;
-+	u8  reserved;
-+} Si2168B_I2C_PASSTHROUGH_CMD_struct;
-+
-+/* I2C_PASSTHROUGH command, SUBCODE field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2168B_I2C_PASSTHROUGH_CMD_SUBCODE_LSB         0
-+#define Si2168B_I2C_PASSTHROUGH_CMD_SUBCODE_MASK        0xff
-+#define Si2168B_I2C_PASSTHROUGH_CMD_SUBCODE_MIN         13
-+#define Si2168B_I2C_PASSTHROUGH_CMD_SUBCODE_MAX         13
-+#define Si2168B_I2C_PASSTHROUGH_CMD_SUBCODE_CODE  13
-+/* I2C_PASSTHROUGH command, I2C_PASSTHRU field definition (address 2,size 1, lsb 0, unsigned) */
-+#define Si2168B_I2C_PASSTHROUGH_CMD_I2C_PASSTHRU_LSB         0
-+#define Si2168B_I2C_PASSTHROUGH_CMD_I2C_PASSTHRU_MASK        0x01
-+#define Si2168B_I2C_PASSTHROUGH_CMD_I2C_PASSTHRU_MIN         0
-+#define Si2168B_I2C_PASSTHROUGH_CMD_I2C_PASSTHRU_MAX         1
-+#define Si2168B_I2C_PASSTHROUGH_CMD_I2C_PASSTHRU_CLOSE  1
-+#define Si2168B_I2C_PASSTHROUGH_CMD_I2C_PASSTHRU_OPEN   0
-+/* I2C_PASSTHROUGH command, RESERVED field definition (address 2,size 7, lsb 1, unsigned) */
-+#define Si2168B_I2C_PASSTHROUGH_CMD_RESERVED_LSB         1
-+#define Si2168B_I2C_PASSTHROUGH_CMD_RESERVED_MASK        0x7f
-+#define Si2168B_I2C_PASSTHROUGH_CMD_RESERVED_MIN         0
-+#define Si2168B_I2C_PASSTHROUGH_CMD_RESERVED_MAX         0
-+#define Si2168B_I2C_PASSTHROUGH_CMD_RESERVED_RESERVED  0
-+#endif /* Si2168B_I2C_PASSTHROUGH_CMD */
-+
-+/* Si2168B_MCNS_STATUS command definition */
-+#define Si2168B_MCNS_STATUS_CMD 0x98
-+
-+#ifdef Si2168B_MCNS_STATUS_CMD
-+#define Si2168B_MCNS_STATUS_CMD_CODE 0x010098
-+
-+typedef struct { /* Si2168B_MCNS_STATUS_CMD_struct */
-+	u8  intack;
-+} Si2168B_MCNS_STATUS_CMD_struct;
-+
-+typedef struct { /* Si2168B_MCNS_STATUS_CMD_REPLY_struct */
-+	u8  pclint;
-+	u8  dlint;
-+	u8  berint;
-+	u8  uncorint;
-+	u8  pcl;
-+	u8  dl;
-+	u8  ber;
-+	u8  uncor;
-+	u8  cnr;
-+	s16 afc_freq;
-+	s16 timing_offset;
-+	u8  constellation;
-+	u8  sp_inv;
-+	u8  interleaving;
-+}  Si2168B_MCNS_STATUS_CMD_REPLY_struct;
-+
-+/* MCNS_STATUS command, INTACK field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2168B_MCNS_STATUS_CMD_INTACK_LSB         0
-+#define Si2168B_MCNS_STATUS_CMD_INTACK_MASK        0x01
-+#define Si2168B_MCNS_STATUS_CMD_INTACK_MIN         0
-+#define Si2168B_MCNS_STATUS_CMD_INTACK_MAX         1
-+#define Si2168B_MCNS_STATUS_CMD_INTACK_CLEAR  1
-+#define Si2168B_MCNS_STATUS_CMD_INTACK_OK     0
-+/* MCNS_STATUS command, PCLINT field definition (address 1, size 1, lsb 1, unsigned)*/
-+#define Si2168B_MCNS_STATUS_RESPONSE_PCLINT_LSB         1
-+#define Si2168B_MCNS_STATUS_RESPONSE_PCLINT_MASK        0x01
-+#define Si2168B_MCNS_STATUS_RESPONSE_PCLINT_CHANGED    1
-+#define Si2168B_MCNS_STATUS_RESPONSE_PCLINT_NO_CHANGE  0
-+/* MCNS_STATUS command, DLINT field definition (address 1, size 1, lsb 2, unsigned)*/
-+#define Si2168B_MCNS_STATUS_RESPONSE_DLINT_LSB         2
-+#define Si2168B_MCNS_STATUS_RESPONSE_DLINT_MASK        0x01
-+#define Si2168B_MCNS_STATUS_RESPONSE_DLINT_CHANGED    1
-+#define Si2168B_MCNS_STATUS_RESPONSE_DLINT_NO_CHANGE  0
-+/* MCNS_STATUS command, BERINT field definition (address 1, size 1, lsb 3, unsigned)*/
-+#define Si2168B_MCNS_STATUS_RESPONSE_BERINT_LSB         3
-+#define Si2168B_MCNS_STATUS_RESPONSE_BERINT_MASK        0x01
-+#define Si2168B_MCNS_STATUS_RESPONSE_BERINT_CHANGED    1
-+#define Si2168B_MCNS_STATUS_RESPONSE_BERINT_NO_CHANGE  0
-+/* MCNS_STATUS command, UNCORINT field definition (address 1, size 1, lsb 4, unsigned)*/
-+#define Si2168B_MCNS_STATUS_RESPONSE_UNCORINT_LSB         4
-+#define Si2168B_MCNS_STATUS_RESPONSE_UNCORINT_MASK        0x01
-+#define Si2168B_MCNS_STATUS_RESPONSE_UNCORINT_CHANGED    1
-+#define Si2168B_MCNS_STATUS_RESPONSE_UNCORINT_NO_CHANGE  0
-+/* MCNS_STATUS command, PCL field definition (address 2, size 1, lsb 1, unsigned)*/
-+#define Si2168B_MCNS_STATUS_RESPONSE_PCL_LSB         1
-+#define Si2168B_MCNS_STATUS_RESPONSE_PCL_MASK        0x01
-+#define Si2168B_MCNS_STATUS_RESPONSE_PCL_LOCKED   1
-+#define Si2168B_MCNS_STATUS_RESPONSE_PCL_NO_LOCK  0
-+/* MCNS_STATUS command, DL field definition (address 2, size 1, lsb 2, unsigned)*/
-+#define Si2168B_MCNS_STATUS_RESPONSE_DL_LSB         2
-+#define Si2168B_MCNS_STATUS_RESPONSE_DL_MASK        0x01
-+#define Si2168B_MCNS_STATUS_RESPONSE_DL_LOCKED   1
-+#define Si2168B_MCNS_STATUS_RESPONSE_DL_NO_LOCK  0
-+/* MCNS_STATUS command, BER field definition (address 2, size 1, lsb 3, unsigned)*/
-+#define Si2168B_MCNS_STATUS_RESPONSE_BER_LSB         3
-+#define Si2168B_MCNS_STATUS_RESPONSE_BER_MASK        0x01
-+#define Si2168B_MCNS_STATUS_RESPONSE_BER_BER_ABOVE  1
-+#define Si2168B_MCNS_STATUS_RESPONSE_BER_BER_BELOW  0
-+/* MCNS_STATUS command, UNCOR field definition (address 2, size 1, lsb 4, unsigned)*/
-+#define Si2168B_MCNS_STATUS_RESPONSE_UNCOR_LSB         4
-+#define Si2168B_MCNS_STATUS_RESPONSE_UNCOR_MASK        0x01
-+#define Si2168B_MCNS_STATUS_RESPONSE_UNCOR_NO_UNCOR_FOUND  0
-+#define Si2168B_MCNS_STATUS_RESPONSE_UNCOR_UNCOR_FOUND     1
-+/* MCNS_STATUS command, CNR field definition (address 3, size 8, lsb 0, unsigned)*/
-+#define Si2168B_MCNS_STATUS_RESPONSE_CNR_LSB         0
-+#define Si2168B_MCNS_STATUS_RESPONSE_CNR_MASK        0xff
-+/* MCNS_STATUS command, AFC_FREQ field definition (address 4, size 16, lsb 0, signed)*/
-+#define Si2168B_MCNS_STATUS_RESPONSE_AFC_FREQ_LSB         0
-+#define Si2168B_MCNS_STATUS_RESPONSE_AFC_FREQ_MASK        0xffff
-+#define Si2168B_MCNS_STATUS_RESPONSE_AFC_FREQ_SHIFT       16
-+/* MCNS_STATUS command, TIMING_OFFSET field definition (address 6, size 16, lsb 0, signed)*/
-+#define Si2168B_MCNS_STATUS_RESPONSE_TIMING_OFFSET_LSB         0
-+#define Si2168B_MCNS_STATUS_RESPONSE_TIMING_OFFSET_MASK        0xffff
-+#define Si2168B_MCNS_STATUS_RESPONSE_TIMING_OFFSET_SHIFT       16
-+/* MCNS_STATUS command, CONSTELLATION field definition (address 8, size 6, lsb 0, unsigned)*/
-+#define Si2168B_MCNS_STATUS_RESPONSE_CONSTELLATION_LSB         0
-+#define Si2168B_MCNS_STATUS_RESPONSE_CONSTELLATION_MASK        0x3f
-+#define Si2168B_MCNS_STATUS_RESPONSE_CONSTELLATION_QAM256  11
-+#define Si2168B_MCNS_STATUS_RESPONSE_CONSTELLATION_QAM64   9
-+/* MCNS_STATUS command, SP_INV field definition (address 8, size 1, lsb 6, unsigned)*/
-+#define Si2168B_MCNS_STATUS_RESPONSE_SP_INV_LSB         6
-+#define Si2168B_MCNS_STATUS_RESPONSE_SP_INV_MASK        0x01
-+#define Si2168B_MCNS_STATUS_RESPONSE_SP_INV_INVERTED  1
-+#define Si2168B_MCNS_STATUS_RESPONSE_SP_INV_NORMAL    0
-+/* MCNS_STATUS command, INTERLEAVING field definition (address 9, size 4, lsb 0, unsigned)*/
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_LSB         0
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_MASK        0x0f
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_0__128_1      0
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_10__128_6     10
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_11__RESERVED  11
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_12__128_7     12
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_13__RESERVED  13
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_14__128_8     14
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_15__RESERVED  15
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_1__128_1      1
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_2__128_2      2
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_3__64_2       3
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_4__128_3      4
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_5__32_4       5
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_6__128_4      6
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_7__16_8       7
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_8__128_5      8
-+#define Si2168B_MCNS_STATUS_RESPONSE_INTERLEAVING_9__8_16       9
-+
-+#endif /* Si2168B_MCNS_STATUS_CMD */
-+
-+/* Si2168B_PART_INFO command definition */
-+#define Si2168B_PART_INFO_CMD 0x02
-+
-+#ifdef Si2168B_PART_INFO_CMD
-+#define Si2168B_PART_INFO_CMD_CODE 0x010002
-+
-+typedef struct { /* Si2168B_PART_INFO_CMD_struct */
-+	u8  nothing;
-+} Si2168B_PART_INFO_CMD_struct;
-+
-+typedef struct { /* Si2168B_PART_INFO_CMD_REPLY_struct */
-+	u8  chiprev;
-+	u8  romid;
-+	u8  part;
-+	u8  pmajor;
-+	u8  pminor;
-+	u8  pbuild;
-+	u16 reserved;
-+	u32 serial;
-+}  Si2168B_PART_INFO_CMD_REPLY_struct;
-+
-+/* PART_INFO command, CHIPREV field definition (address 1, size 4, lsb 0, unsigned)*/
-+#define Si2168B_PART_INFO_RESPONSE_CHIPREV_LSB         0
-+#define Si2168B_PART_INFO_RESPONSE_CHIPREV_MASK        0x0f
-+#define Si2168B_PART_INFO_RESPONSE_CHIPREV_A  1
-+#define Si2168B_PART_INFO_RESPONSE_CHIPREV_B  2
-+/* PART_INFO command, ROMID field definition (address 12, size 8, lsb 0, unsigned)*/
-+#define Si2168B_PART_INFO_RESPONSE_ROMID_LSB         0
-+#define Si2168B_PART_INFO_RESPONSE_ROMID_MASK        0xff
-+/* PART_INFO command, PART field definition (address 2, size 8, lsb 0, unsigned)*/
-+#define Si2168B_PART_INFO_RESPONSE_PART_LSB         0
-+#define Si2168B_PART_INFO_RESPONSE_PART_MASK        0xff
-+/* PART_INFO command, PMAJOR field definition (address 3, size 8, lsb 0, unsigned)*/
-+#define Si2168B_PART_INFO_RESPONSE_PMAJOR_LSB         0
-+#define Si2168B_PART_INFO_RESPONSE_PMAJOR_MASK        0xff
-+/* PART_INFO command, PMINOR field definition (address 4, size 8, lsb 0, unsigned)*/
-+#define Si2168B_PART_INFO_RESPONSE_PMINOR_LSB         0
-+#define Si2168B_PART_INFO_RESPONSE_PMINOR_MASK        0xff
-+/* PART_INFO command, PBUILD field definition (address 5, size 8, lsb 0, unsigned)*/
-+#define Si2168B_PART_INFO_RESPONSE_PBUILD_LSB         0
-+#define Si2168B_PART_INFO_RESPONSE_PBUILD_MASK        0xff
-+/* PART_INFO command, RESERVED field definition (address 6, size 16, lsb 0, unsigned)*/
-+#define Si2168B_PART_INFO_RESPONSE_RESERVED_LSB         0
-+#define Si2168B_PART_INFO_RESPONSE_RESERVED_MASK        0xffff
-+/* PART_INFO command, SERIAL field definition (address 8, size 32, lsb 0, unsigned)*/
-+#define Si2168B_PART_INFO_RESPONSE_SERIAL_LSB         0
-+#define Si2168B_PART_INFO_RESPONSE_SERIAL_MASK        0xffffffff
-+
-+#endif /* Si2168B_PART_INFO_CMD */
-+
-+/* Si2168B_POWER_DOWN command definition */
-+#define Si2168B_POWER_DOWN_CMD 0x13
-+
-+#ifdef Si2168B_POWER_DOWN_CMD
-+#define Si2168B_POWER_DOWN_CMD_CODE 0x010013
-+
-+typedef struct { /* Si2168B_POWER_DOWN_CMD_struct */
-+	u8  nothing;
-+} Si2168B_POWER_DOWN_CMD_struct;
-+
-+#endif /* Si2168B_POWER_DOWN_CMD */
-+
-+/* Si2168B_POWER_UP command definition */
-+#define Si2168B_POWER_UP_CMD 0xc0
-+
-+#ifdef Si2168B_POWER_UP_CMD
-+#define Si2168B_POWER_UP_CMD_CODE 0x0200c0
-+
-+typedef struct { /* Si2168B_POWER_UP_CMD_struct */
-+	u8  subcode;
-+	u8  reset;
-+	u8  reserved2;
-+	u8  reserved4;
-+	u8  reserved1;
-+	u8  addr_mode;
-+	u8  reserved5;
-+	u8  func;
-+	u8  clock_freq;
-+	u8  ctsien;
-+	u8  wake_up;
-+} Si2168B_POWER_UP_CMD_struct;
-+
-+/* POWER_UP command, SUBCODE field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2168B_POWER_UP_CMD_SUBCODE_LSB         0
-+#define Si2168B_POWER_UP_CMD_SUBCODE_MASK        0xff
-+#define Si2168B_POWER_UP_CMD_SUBCODE_MIN         6
-+#define Si2168B_POWER_UP_CMD_SUBCODE_MAX         6
-+#define Si2168B_POWER_UP_CMD_SUBCODE_CODE  6
-+/* POWER_UP command, RESET field definition (address 2,size 8, lsb 0, unsigned) */
-+#define Si2168B_POWER_UP_CMD_RESET_LSB         0
-+#define Si2168B_POWER_UP_CMD_RESET_MASK        0xff
-+#define Si2168B_POWER_UP_CMD_RESET_MIN         1
-+#define Si2168B_POWER_UP_CMD_RESET_MAX         8
-+#define Si2168B_POWER_UP_CMD_RESET_RESET   1
-+#define Si2168B_POWER_UP_CMD_RESET_RESUME  8
-+/* POWER_UP command, RESERVED2 field definition (address 3,size 8, lsb 0, unsigned) */
-+#define Si2168B_POWER_UP_CMD_RESERVED2_LSB         0
-+#define Si2168B_POWER_UP_CMD_RESERVED2_MASK        0xff
-+#define Si2168B_POWER_UP_CMD_RESERVED2_MIN         15
-+#define Si2168B_POWER_UP_CMD_RESERVED2_MAX         15
-+#define Si2168B_POWER_UP_CMD_RESERVED2_RESERVED  15
-+/* POWER_UP command, RESERVED4 field definition (address 4,size 8, lsb 0, unsigned) */
-+#define Si2168B_POWER_UP_CMD_RESERVED4_LSB         0
-+#define Si2168B_POWER_UP_CMD_RESERVED4_MASK        0xff
-+#define Si2168B_POWER_UP_CMD_RESERVED4_MIN         0
-+#define Si2168B_POWER_UP_CMD_RESERVED4_MAX         0
-+#define Si2168B_POWER_UP_CMD_RESERVED4_RESERVED  0
-+/* POWER_UP command, RESERVED1 field definition (address 5,size 4, lsb 0, unsigned) */
-+#define Si2168B_POWER_UP_CMD_RESERVED1_LSB         0
-+#define Si2168B_POWER_UP_CMD_RESERVED1_MASK        0x0f
-+#define Si2168B_POWER_UP_CMD_RESERVED1_MIN         0
-+#define Si2168B_POWER_UP_CMD_RESERVED1_MAX         0
-+#define Si2168B_POWER_UP_CMD_RESERVED1_RESERVED  0
-+/* POWER_UP command, ADDR_MODE field definition (address 5,size 1, lsb 4, unsigned) */
-+#define Si2168B_POWER_UP_CMD_ADDR_MODE_LSB         4
-+#define Si2168B_POWER_UP_CMD_ADDR_MODE_MASK        0x01
-+#define Si2168B_POWER_UP_CMD_ADDR_MODE_MIN         0
-+#define Si2168B_POWER_UP_CMD_ADDR_MODE_MAX         1
-+#define Si2168B_POWER_UP_CMD_ADDR_MODE_CAPTURE  1
-+#define Si2168B_POWER_UP_CMD_ADDR_MODE_CURRENT  0
-+/* POWER_UP command, RESERVED5 field definition (address 5,size 1, lsb 5, unsigned) */
-+#define Si2168B_POWER_UP_CMD_RESERVED5_LSB         5
-+#define Si2168B_POWER_UP_CMD_RESERVED5_MASK        0x01
-+#define Si2168B_POWER_UP_CMD_RESERVED5_MIN         1
-+#define Si2168B_POWER_UP_CMD_RESERVED5_MAX         1
-+#define Si2168B_POWER_UP_CMD_RESERVED5_RESERVED  1
-+/* POWER_UP command, FUNC field definition (address 6,size 4, lsb 0, unsigned) */
-+#define Si2168B_POWER_UP_CMD_FUNC_LSB         0
-+#define Si2168B_POWER_UP_CMD_FUNC_MASK        0x0f
-+#define Si2168B_POWER_UP_CMD_FUNC_MIN         0
-+#define Si2168B_POWER_UP_CMD_FUNC_MAX         1
-+#define Si2168B_POWER_UP_CMD_FUNC_BOOTLOADER  0
-+#define Si2168B_POWER_UP_CMD_FUNC_NORMAL      1
-+/* POWER_UP command, CLOCK_FREQ field definition (address 6,size 3, lsb 4, unsigned) */
-+#define Si2168B_POWER_UP_CMD_CLOCK_FREQ_LSB         4
-+#define Si2168B_POWER_UP_CMD_CLOCK_FREQ_MASK        0x07
-+#define Si2168B_POWER_UP_CMD_CLOCK_FREQ_MIN         0
-+#define Si2168B_POWER_UP_CMD_CLOCK_FREQ_MAX         4
-+#define Si2168B_POWER_UP_CMD_CLOCK_FREQ_CLK_16MHZ  0
-+#define Si2168B_POWER_UP_CMD_CLOCK_FREQ_CLK_24MHZ  2
-+#define Si2168B_POWER_UP_CMD_CLOCK_FREQ_CLK_27MHZ  3
-+/* POWER_UP command, CTSIEN field definition (address 6,size 1, lsb 7, unsigned) */
-+#define Si2168B_POWER_UP_CMD_CTSIEN_LSB         7
-+#define Si2168B_POWER_UP_CMD_CTSIEN_MASK        0x01
-+#define Si2168B_POWER_UP_CMD_CTSIEN_MIN         0
-+#define Si2168B_POWER_UP_CMD_CTSIEN_MAX         1
-+#define Si2168B_POWER_UP_CMD_CTSIEN_DISABLE  0
-+#define Si2168B_POWER_UP_CMD_CTSIEN_ENABLE   1
-+/* POWER_UP command, WAKE_UP field definition (address 7,size 1, lsb 0, unsigned) */
-+#define Si2168B_POWER_UP_CMD_WAKE_UP_LSB         0
-+#define Si2168B_POWER_UP_CMD_WAKE_UP_MASK        0x01
-+#define Si2168B_POWER_UP_CMD_WAKE_UP_MIN         1
-+#define Si2168B_POWER_UP_CMD_WAKE_UP_MAX         1
-+#define Si2168B_POWER_UP_CMD_WAKE_UP_WAKE_UP  1
-+#endif /* Si2168B_POWER_UP_CMD */
-+
-+/* Si2168B_RSSI_ADC command definition */
-+#define Si2168B_RSSI_ADC_CMD 0x17
-+
-+#ifdef Si2168B_RSSI_ADC_CMD
-+#define Si2168B_RSSI_ADC_CMD_CODE 0x010017
-+
-+typedef struct { /* Si2168B_RSSI_ADC_CMD_struct */
-+	u8  on_off;
-+} Si2168B_RSSI_ADC_CMD_struct;
-+
-+typedef struct { /* Si2168B_RSSI_ADC_CMD_REPLY_struct */
-+	u8  level;
-+}  Si2168B_RSSI_ADC_CMD_REPLY_struct;
-+
-+/* RSSI_ADC command, ON_OFF field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2168B_RSSI_ADC_CMD_ON_OFF_LSB         0
-+#define Si2168B_RSSI_ADC_CMD_ON_OFF_MASK        0x01
-+#define Si2168B_RSSI_ADC_CMD_ON_OFF_MIN         0
-+#define Si2168B_RSSI_ADC_CMD_ON_OFF_MAX         1
-+#define Si2168B_RSSI_ADC_CMD_ON_OFF_OFF  0
-+#define Si2168B_RSSI_ADC_CMD_ON_OFF_ON   1
-+/* RSSI_ADC command, LEVEL field definition (address 1, size 8, lsb 0, unsigned)*/
-+#define Si2168B_RSSI_ADC_RESPONSE_LEVEL_LSB         0
-+#define Si2168B_RSSI_ADC_RESPONSE_LEVEL_MASK        0xff
-+
-+#endif /* Si2168B_RSSI_ADC_CMD */
-+
-+/* Si2168B_SCAN_CTRL command definition */
-+#define Si2168B_SCAN_CTRL_CMD 0x31
-+
-+#ifdef Si2168B_SCAN_CTRL_CMD
-+#define Si2168B_SCAN_CTRL_CMD_CODE 0x010031
-+
-+typedef struct { /* Si2168B_SCAN_CTRL_CMD_struct */
-+	u8  action;
-+	u32 tuned_rf_freq;
-+} Si2168B_SCAN_CTRL_CMD_struct;
-+
-+/* SCAN_CTRL command, ACTION field definition (address 1,size 4, lsb 0, unsigned) */
-+#define Si2168B_SCAN_CTRL_CMD_ACTION_LSB         0
-+#define Si2168B_SCAN_CTRL_CMD_ACTION_MASK        0x0f
-+#define Si2168B_SCAN_CTRL_CMD_ACTION_MIN         1
-+#define Si2168B_SCAN_CTRL_CMD_ACTION_MAX         3
-+#define Si2168B_SCAN_CTRL_CMD_ACTION_ABORT   3
-+#define Si2168B_SCAN_CTRL_CMD_ACTION_RESUME  2
-+#define Si2168B_SCAN_CTRL_CMD_ACTION_START   1
-+/* SCAN_CTRL command, TUNED_RF_FREQ field definition (address 4,size 32, lsb 0, unsigned) */
-+#define Si2168B_SCAN_CTRL_CMD_TUNED_RF_FREQ_LSB         0
-+#define Si2168B_SCAN_CTRL_CMD_TUNED_RF_FREQ_MASK        0xffffffff
-+#define Si2168B_SCAN_CTRL_CMD_TUNED_RF_FREQ_MIN         0
-+#define Si2168B_SCAN_CTRL_CMD_TUNED_RF_FREQ_MAX         4294967
-+#define Si2168B_SCAN_CTRL_CMD_TUNED_RF_FREQ_TUNED_RF_FREQ_MIN  0
-+#define Si2168B_SCAN_CTRL_CMD_TUNED_RF_FREQ_TUNED_RF_FREQ_MAX  4294967
-+#endif /* Si2168B_SCAN_CTRL_CMD */
-+
-+/* Si2168B_SCAN_STATUS command definition */
-+#define Si2168B_SCAN_STATUS_CMD 0x30
-+
-+#ifdef Si2168B_SCAN_STATUS_CMD
-+#define Si2168B_SCAN_STATUS_CMD_CODE 0x010030
-+
-+typedef struct { /* Si2168B_SCAN_STATUS_CMD_struct */
-+	u8  intack;
-+} Si2168B_SCAN_STATUS_CMD_struct;
-+
-+typedef struct { /* Si2168B_SCAN_STATUS_CMD_REPLY_struct */
-+	u8  buzint;
-+	u8  reqint;
-+	u8  modulation;
-+	u8  buz;
-+	u8  req;
-+	u8  scan_status;
-+	u32 rf_freq;
-+	u16 symb_rate;
-+}  Si2168B_SCAN_STATUS_CMD_REPLY_struct;
-+
-+/* SCAN_STATUS command, INTACK field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2168B_SCAN_STATUS_CMD_INTACK_LSB         0
-+#define Si2168B_SCAN_STATUS_CMD_INTACK_MASK        0x01
-+#define Si2168B_SCAN_STATUS_CMD_INTACK_MIN         0
-+#define Si2168B_SCAN_STATUS_CMD_INTACK_MAX         1
-+#define Si2168B_SCAN_STATUS_CMD_INTACK_CLEAR  1
-+#define Si2168B_SCAN_STATUS_CMD_INTACK_OK     0
-+/* SCAN_STATUS command, BUZINT field definition (address 1, size 1, lsb 0, unsigned)*/
-+#define Si2168B_SCAN_STATUS_RESPONSE_BUZINT_LSB         0
-+#define Si2168B_SCAN_STATUS_RESPONSE_BUZINT_MASK        0x01
-+#define Si2168B_SCAN_STATUS_RESPONSE_BUZINT_CHANGED    1
-+#define Si2168B_SCAN_STATUS_RESPONSE_BUZINT_NO_CHANGE  0
-+/* SCAN_STATUS command, REQINT field definition (address 1, size 1, lsb 1, unsigned)*/
-+#define Si2168B_SCAN_STATUS_RESPONSE_REQINT_LSB         1
-+#define Si2168B_SCAN_STATUS_RESPONSE_REQINT_MASK        0x01
-+#define Si2168B_SCAN_STATUS_RESPONSE_REQINT_CHANGED    1
-+#define Si2168B_SCAN_STATUS_RESPONSE_REQINT_NO_CHANGE  0
-+/* SCAN_STATUS command, MODULATION field definition (address 10, size 4, lsb 0, unsigned)*/
-+#define Si2168B_SCAN_STATUS_RESPONSE_MODULATION_LSB         0
-+#define Si2168B_SCAN_STATUS_RESPONSE_MODULATION_MASK        0x0f
-+#define Si2168B_SCAN_STATUS_RESPONSE_MODULATION_DSS    10
-+#define Si2168B_SCAN_STATUS_RESPONSE_MODULATION_DVBC   3
-+#define Si2168B_SCAN_STATUS_RESPONSE_MODULATION_DVBC2  11
-+#define Si2168B_SCAN_STATUS_RESPONSE_MODULATION_DVBS   8
-+#define Si2168B_SCAN_STATUS_RESPONSE_MODULATION_DVBS2  9
-+#define Si2168B_SCAN_STATUS_RESPONSE_MODULATION_DVBT   2
-+#define Si2168B_SCAN_STATUS_RESPONSE_MODULATION_DVBT2  7
-+#define Si2168B_SCAN_STATUS_RESPONSE_MODULATION_MCNS   1
-+/* SCAN_STATUS command, BUZ field definition (address 2, size 1, lsb 0, unsigned)*/
-+#define Si2168B_SCAN_STATUS_RESPONSE_BUZ_LSB         0
-+#define Si2168B_SCAN_STATUS_RESPONSE_BUZ_MASK        0x01
-+#define Si2168B_SCAN_STATUS_RESPONSE_BUZ_BUSY  1
-+#define Si2168B_SCAN_STATUS_RESPONSE_BUZ_CTS   0
-+/* SCAN_STATUS command, REQ field definition (address 2, size 1, lsb 1, unsigned)*/
-+#define Si2168B_SCAN_STATUS_RESPONSE_REQ_LSB         1
-+#define Si2168B_SCAN_STATUS_RESPONSE_REQ_MASK        0x01
-+#define Si2168B_SCAN_STATUS_RESPONSE_REQ_NO_REQUEST  0
-+#define Si2168B_SCAN_STATUS_RESPONSE_REQ_REQUEST     1
-+/* SCAN_STATUS command, SCAN_STATUS field definition (address 3, size 6, lsb 0, unsigned)*/
-+#define Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_LSB         0
-+#define Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_MASK        0x3f
-+#define Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_ANALOG_CHANNEL_FOUND   6
-+#define Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_DEBUG                  63
-+#define Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_DIGITAL_CHANNEL_FOUND  5
-+#define Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_ENDED                  2
-+#define Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_ERROR                  3
-+#define Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_IDLE                   0
-+#define Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_SEARCHING              1
-+#define Si2168B_SCAN_STATUS_RESPONSE_SCAN_STATUS_TUNE_REQUEST           4
-+/* SCAN_STATUS command, RF_FREQ field definition (address 4, size 32, lsb 0, unsigned)*/
-+#define Si2168B_SCAN_STATUS_RESPONSE_RF_FREQ_LSB         0
-+#define Si2168B_SCAN_STATUS_RESPONSE_RF_FREQ_MASK        0xffffffff
-+/* SCAN_STATUS command, SYMB_RATE field definition (address 8, size 16, lsb 0, unsigned)*/
-+#define Si2168B_SCAN_STATUS_RESPONSE_SYMB_RATE_LSB         0
-+#define Si2168B_SCAN_STATUS_RESPONSE_SYMB_RATE_MASK        0xffff
-+
-+#endif /* Si2168B_SCAN_STATUS_CMD */
-+
-+/* Si2168B_SET_PROPERTY command definition */
-+#define Si2168B_SET_PROPERTY_CMD 0x14
-+
-+#ifdef Si2168B_SET_PROPERTY_CMD
-+#define Si2168B_SET_PROPERTY_CMD_CODE 0x010014
-+
-+typedef struct { /* Si2168B_SET_PROPERTY_CMD_struct */
-+	u8  reserved;
-+	u16 prop;
-+	u16 data;
-+} Si2168B_SET_PROPERTY_CMD_struct;
-+
-+typedef struct { /* Si2168B_SET_PROPERTY_CMD_REPLY_struct */
-+	u8  reserved;
-+	u16 data;
-+} Si2168B_SET_PROPERTY_CMD_REPLY_struct;
-+
-+/* SET_PROPERTY command, RESERVED field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2168B_SET_PROPERTY_CMD_RESERVED_LSB         0
-+#define Si2168B_SET_PROPERTY_CMD_RESERVED_MASK        0xff
-+#define Si2168B_SET_PROPERTY_CMD_RESERVED_MIN         0
-+#define Si2168B_SET_PROPERTY_CMD_RESERVED_MAX         255
-+/* SET_PROPERTY command, PROP field definition (address 2,size 16, lsb 0, unsigned) */
-+#define Si2168B_SET_PROPERTY_CMD_PROP_LSB         0
-+#define Si2168B_SET_PROPERTY_CMD_PROP_MASK        0xffff
-+#define Si2168B_SET_PROPERTY_CMD_PROP_MIN         0
-+#define Si2168B_SET_PROPERTY_CMD_PROP_MAX         65535
-+#define Si2168B_SET_PROPERTY_CMD_PROP_PROP_MIN  0
-+#define Si2168B_SET_PROPERTY_CMD_PROP_PROP_MAX  65535
-+/* SET_PROPERTY command, DATA field definition (address 4,size 16, lsb 0, unsigned) */
-+#define Si2168B_SET_PROPERTY_CMD_DATA_LSB         0
-+#define Si2168B_SET_PROPERTY_CMD_DATA_MASK        0xffff
-+#define Si2168B_SET_PROPERTY_CMD_DATA_MIN         0
-+#define Si2168B_SET_PROPERTY_CMD_DATA_MAX         65535
-+#define Si2168B_SET_PROPERTY_CMD_DATA_DATA_MIN  0
-+#define Si2168B_SET_PROPERTY_CMD_DATA_DATA_MAX  65535
-+/* SET_PROPERTY command, RESERVED field definition (address 1, size 8, lsb 0, unsigned)*/
-+#define Si2168B_SET_PROPERTY_RESPONSE_RESERVED_LSB         0
-+#define Si2168B_SET_PROPERTY_RESPONSE_RESERVED_MASK        0xff
-+#define Si2168B_SET_PROPERTY_RESPONSE_RESERVED_RESERVED_MIN  0
-+#define Si2168B_SET_PROPERTY_RESPONSE_RESERVED_RESERVED_MAX  0
-+/* SET_PROPERTY command, DATA field definition (address 2, size 16, lsb 0, unsigned)*/
-+#define Si2168B_SET_PROPERTY_RESPONSE_DATA_LSB         0
-+#define Si2168B_SET_PROPERTY_RESPONSE_DATA_MASK        0xffff
-+
-+#endif /* Si2168B_SET_PROPERTY_CMD */
-+
-+/* Si2168B_SPI_LINK command definition */
-+#define Si2168B_SPI_LINK_CMD 0xc0
-+
-+#ifdef Si2168B_SPI_LINK_CMD
-+#define Si2168B_SPI_LINK_CMD_CODE 0x0400c0
-+
-+typedef struct { /* Si2168B_SPI_LINK_CMD_struct */
-+	u8  subcode;
-+	u8  spi_pbl_key;
-+	u8  spi_pbl_num;
-+	u8  spi_conf_clk;
-+	u8  spi_clk_pola;
-+	u8  spi_conf_data;
-+	u8  spi_data_dir;
-+	u8  spi_enable;
-+} Si2168B_SPI_LINK_CMD_struct;
-+
-+/* SPI_LINK command, SUBCODE field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2168B_SPI_LINK_CMD_SUBCODE_LSB         0
-+#define Si2168B_SPI_LINK_CMD_SUBCODE_MASK        0xff
-+#define Si2168B_SPI_LINK_CMD_SUBCODE_MIN         56
-+#define Si2168B_SPI_LINK_CMD_SUBCODE_MAX         56
-+#define Si2168B_SPI_LINK_CMD_SUBCODE_CODE  56
-+/* SPI_LINK command, SPI_PBL_KEY field definition (address 2,size 8, lsb 0, unsigned) */
-+#define Si2168B_SPI_LINK_CMD_SPI_PBL_KEY_LSB         0
-+#define Si2168B_SPI_LINK_CMD_SPI_PBL_KEY_MASK        0xff
-+#define Si2168B_SPI_LINK_CMD_SPI_PBL_KEY_MIN         0
-+#define Si2168B_SPI_LINK_CMD_SPI_PBL_KEY_MAX         255
-+/* SPI_LINK command, SPI_PBL_NUM field definition (address 3,size 4, lsb 0, unsigned) */
-+#define Si2168B_SPI_LINK_CMD_SPI_PBL_NUM_LSB         0
-+#define Si2168B_SPI_LINK_CMD_SPI_PBL_NUM_MASK        0x0f
-+#define Si2168B_SPI_LINK_CMD_SPI_PBL_NUM_MIN         0
-+#define Si2168B_SPI_LINK_CMD_SPI_PBL_NUM_MAX         15
-+/* SPI_LINK command, SPI_CONF_CLK field definition (address 4,size 4, lsb 0, unsigned) */
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_LSB         0
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_MASK        0x0f
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_MIN         0
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_MAX         9
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_DISABLE     0
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_DISEQC_CMD  9
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_DISEQC_IN   7
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_DISEQC_OUT  8
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_GPIO0       5
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_GPIO1       6
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_MP_A        1
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_MP_B        2
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_MP_C        3
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_CLK_MP_D        4
-+/* SPI_LINK command, SPI_CLK_POLA field definition (address 4,size 1, lsb 4, unsigned) */
-+#define Si2168B_SPI_LINK_CMD_SPI_CLK_POLA_LSB         4
-+#define Si2168B_SPI_LINK_CMD_SPI_CLK_POLA_MASK        0x01
-+#define Si2168B_SPI_LINK_CMD_SPI_CLK_POLA_MIN         0
-+#define Si2168B_SPI_LINK_CMD_SPI_CLK_POLA_MAX         1
-+#define Si2168B_SPI_LINK_CMD_SPI_CLK_POLA_FALLING  1
-+#define Si2168B_SPI_LINK_CMD_SPI_CLK_POLA_RISING   0
-+/* SPI_LINK command, SPI_CONF_DATA field definition (address 5,size 4, lsb 0, unsigned) */
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_LSB         0
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_MASK        0x0f
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_MIN         0
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_MAX         9
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_DISABLE     0
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_DISEQC_CMD  9
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_DISEQC_IN   7
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_DISEQC_OUT  8
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_GPIO0       5
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_GPIO1       6
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_MP_A        1
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_MP_B        2
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_MP_C        3
-+#define Si2168B_SPI_LINK_CMD_SPI_CONF_DATA_MP_D        4
-+/* SPI_LINK command, SPI_DATA_DIR field definition (address 5,size 1, lsb 4, unsigned) */
-+#define Si2168B_SPI_LINK_CMD_SPI_DATA_DIR_LSB         4
-+#define Si2168B_SPI_LINK_CMD_SPI_DATA_DIR_MASK        0x01
-+#define Si2168B_SPI_LINK_CMD_SPI_DATA_DIR_MIN         0
-+#define Si2168B_SPI_LINK_CMD_SPI_DATA_DIR_MAX         1
-+#define Si2168B_SPI_LINK_CMD_SPI_DATA_DIR_LSB_FIRST  1
-+#define Si2168B_SPI_LINK_CMD_SPI_DATA_DIR_MSB_FIRST  0
-+/* SPI_LINK command, SPI_ENABLE field definition (address 6,size 1, lsb 0, unsigned) */
-+#define Si2168B_SPI_LINK_CMD_SPI_ENABLE_LSB         0
-+#define Si2168B_SPI_LINK_CMD_SPI_ENABLE_MASK        0x01
-+#define Si2168B_SPI_LINK_CMD_SPI_ENABLE_MIN         0
-+#define Si2168B_SPI_LINK_CMD_SPI_ENABLE_MAX         1
-+#define Si2168B_SPI_LINK_CMD_SPI_ENABLE_DISABLE  0
-+#define Si2168B_SPI_LINK_CMD_SPI_ENABLE_ENABLE   1
-+#endif /* Si2168B_SPI_LINK_CMD */
-+
-+/* Si2168B_SPI_PASSTHROUGH command definition */
-+#define Si2168B_SPI_PASSTHROUGH_CMD 0xc0
-+
-+#ifdef Si2168B_SPI_PASSTHROUGH_CMD
-+#define Si2168B_SPI_PASSTHROUGH_CMD_CODE 0x0500c0
-+
-+typedef struct { /* Si2168B_SPI_PASSTHROUGH_CMD_struct */
-+	u8  subcode;
-+	u8  spi_passthr_clk;
-+	u8  spi_passth_data;
-+} Si2168B_SPI_PASSTHROUGH_CMD_struct;
-+
-+/* SPI_PASSTHROUGH command, SUBCODE field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SUBCODE_LSB         0
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SUBCODE_MASK        0xff
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SUBCODE_MIN         64
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SUBCODE_MAX         64
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SUBCODE_CODE  64
-+/* SPI_PASSTHROUGH command, SPI_PASSTHR_CLK field definition (address 2,size 4, lsb 0, unsigned) */
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_LSB         0
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_MASK        0x0f
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_MIN         0
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_MAX         10
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_DISABLE     0
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_DISEQC_CMD  9
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_DISEQC_IN   7
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_DISEQC_OUT  8
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_GPIO0       5
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_GPIO1       6
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_MP_A        1
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_MP_B        2
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_MP_C        3
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_MP_D        4
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTHR_CLK_SCL_MAST    10
-+/* SPI_PASSTHROUGH command, SPI_PASSTH_DATA field definition (address 3,size 4, lsb 0, unsigned) */
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_LSB         0
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_MASK        0x0f
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_MIN         0
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_MAX         10
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_DISABLE     0
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_DISEQC_CMD  9
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_DISEQC_IN   7
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_DISEQC_OUT  8
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_GPIO0       5
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_GPIO1       6
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_MP_A        1
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_MP_B        2
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_MP_C        3
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_MP_D        4
-+#define Si2168B_SPI_PASSTHROUGH_CMD_SPI_PASSTH_DATA_SDA_MAST    10
-+#endif /* Si2168B_SPI_PASSTHROUGH_CMD */
-+
-+/* Si2168B_START_CLK command definition */
-+#define Si2168B_START_CLK_CMD 0xc0
-+
-+#ifdef Si2168B_START_CLK_CMD
-+#define Si2168B_START_CLK_CMD_CODE 0x0300c0
-+
-+typedef struct { /* Si2168B_START_CLK_CMD_struct */
-+	u8  subcode;
-+	u8  reserved1;
-+	u8  tune_cap;
-+	u8  reserved2;
-+	u16 clk_mode;
-+	u8  reserved3;
-+	u8  reserved4;
-+	u8  start_clk;
-+} Si2168B_START_CLK_CMD_struct;
-+
-+/* START_CLK command, SUBCODE field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2168B_START_CLK_CMD_SUBCODE_LSB         0
-+#define Si2168B_START_CLK_CMD_SUBCODE_MASK        0xff
-+#define Si2168B_START_CLK_CMD_SUBCODE_MIN         18
-+#define Si2168B_START_CLK_CMD_SUBCODE_MAX         18
-+#define Si2168B_START_CLK_CMD_SUBCODE_CODE  18
-+/* START_CLK command, RESERVED1 field definition (address 2,size 8, lsb 0, unsigned) */
-+#define Si2168B_START_CLK_CMD_RESERVED1_LSB         0
-+#define Si2168B_START_CLK_CMD_RESERVED1_MASK        0xff
-+#define Si2168B_START_CLK_CMD_RESERVED1_MIN         0
-+#define Si2168B_START_CLK_CMD_RESERVED1_MAX         0
-+#define Si2168B_START_CLK_CMD_RESERVED1_RESERVED  0
-+/* START_CLK command, TUNE_CAP field definition (address 3,size 4, lsb 0, unsigned) */
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_LSB         0
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_MASK        0x0f
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_MIN         0
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_MAX         15
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_10P4     8
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_11P7     9
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_13P0     10
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_14P3     11
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_15P6     12
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_16P9     13
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_18P2     14
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_19P5     15
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_1P3      1
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_2P6      2
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_3P9      3
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_5P2      4
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_6P5      5
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_7P8      6
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_9P1      7
-+#define Si2168B_START_CLK_CMD_TUNE_CAP_EXT_CLK  0
-+/* START_CLK command, RESERVED2 field definition (address 3,size 4, lsb 4, unsigned) */
-+#define Si2168B_START_CLK_CMD_RESERVED2_LSB         4
-+#define Si2168B_START_CLK_CMD_RESERVED2_MASK        0x0f
-+#define Si2168B_START_CLK_CMD_RESERVED2_MIN         0
-+#define Si2168B_START_CLK_CMD_RESERVED2_MAX         0
-+#define Si2168B_START_CLK_CMD_RESERVED2_RESERVED  0
-+/* START_CLK command, CLK_MODE field definition (address 4,size 12, lsb 0, unsigned) */
-+#define Si2168B_START_CLK_CMD_CLK_MODE_LSB         0
-+#define Si2168B_START_CLK_CMD_CLK_MODE_MASK        0xfff
-+#define Si2168B_START_CLK_CMD_CLK_MODE_MIN         575
-+#define Si2168B_START_CLK_CMD_CLK_MODE_MAX         3328
-+#define Si2168B_START_CLK_CMD_CLK_MODE_CLK_CLKIO    3328
-+#define Si2168B_START_CLK_CMD_CLK_MODE_CLK_XTAL_IN  1536
-+#define Si2168B_START_CLK_CMD_CLK_MODE_XTAL         575
-+/* START_CLK command, RESERVED3 field definition (address 6,size 8, lsb 0, unsigned) */
-+#define Si2168B_START_CLK_CMD_RESERVED3_LSB         0
-+#define Si2168B_START_CLK_CMD_RESERVED3_MASK        0xff
-+#define Si2168B_START_CLK_CMD_RESERVED3_MIN         22
-+#define Si2168B_START_CLK_CMD_RESERVED3_MAX         22
-+#define Si2168B_START_CLK_CMD_RESERVED3_RESERVED  22
-+/* START_CLK command, RESERVED4 field definition (address 7,size 1, lsb 0, unsigned) */
-+#define Si2168B_START_CLK_CMD_RESERVED4_LSB         0
-+#define Si2168B_START_CLK_CMD_RESERVED4_MASK        0x01
-+#define Si2168B_START_CLK_CMD_RESERVED4_MIN         0
-+#define Si2168B_START_CLK_CMD_RESERVED4_MAX         0
-+#define Si2168B_START_CLK_CMD_RESERVED4_RESERVED  0
-+/* START_CLK command, START_CLK field definition (address 12,size 1, lsb 0, unsigned) */
-+#define Si2168B_START_CLK_CMD_START_CLK_LSB         0
-+#define Si2168B_START_CLK_CMD_START_CLK_MASK        0x01
-+#define Si2168B_START_CLK_CMD_START_CLK_MIN         0
-+#define Si2168B_START_CLK_CMD_START_CLK_MAX         0
-+#define Si2168B_START_CLK_CMD_START_CLK_START_CLK  0
-+#endif /* Si2168B_START_CLK_CMD */
-+
-+/* readback values (detected channel properties) */
-+typedef struct { /* Si2168B_CHANNEL_SEEK_NEXT_REPLY_struct */
-+    s32 freq;
-+    u32 bandwidth_Hz;
-+    u32 symbol_rate_bps;
-+    u8  stream;
-+	u8  standard;
-+    u8  constellation;
-+    u8  num_plp;
-+    u8  T2_base_lite;
-+} Si2168B_CHANNEL_SEEK_NEXT_REPLY_struct;
-+
-+typedef struct {
-+	u32  rangeMin;
-+	u32  rangeMax;
-+	u32  seekBWHz;
-+	u32  seekStepHz;
-+	u32  minSRbps;
-+	u32  maxSRbps;
-+	/*int  minRSSIdBm;*/
-+	/*int  maxRSSIdBm;*/
-+	/*int  minSNRHalfdB;*/
-+	/*int  maxSNRHalfdB;*/
-+} Si2168B_CHANNEL_SEEK_PARAM_struct;
-+
-+#define Si2168B_GET_COMMAND_STRINGS
-+
-+#define NO_Si2168B_ERROR                     0x00
-+#define ERROR_Si2168B_PARAMETER_OUT_OF_RANGE 0x01
-+#define ERROR_Si2168B_ALLOCATING_CONTEXT     0x02
-+#define ERROR_Si2168B_SENDING_COMMAND        0x03
-+#define ERROR_Si2168B_CTS_TIMEOUT            0x04
-+#define ERROR_Si2168B_ERR                    0x05
-+#define ERROR_Si2168B_POLLING_CTS            0x06
-+#define ERROR_Si2168B_POLLING_RESPONSE       0x07
-+#define ERROR_Si2168B_LOADING_FIRMWARE       0x08
-+#define ERROR_Si2168B_LOADING_BOOTBLOCK      0x09
-+#define ERROR_Si2168B_STARTING_FIRMWARE      0x0a
-+#define ERROR_Si2168B_SW_RESET               0x0b
-+#define ERROR_Si2168B_INCOMPATIBLE_PART      0x0c
-+#define ERROR_Si2168B_DISEQC_BUS_NOT_READY   0x0d
-+#define ERROR_Si2168B_UNKNOWN_COMMAND        0xf0
-+#define ERROR_Si2168B_UNKNOWN_PROPERTY       0xf1
-+
-+typedef int  (*Si2168B_INDIRECT_I2C_FUNC)  (void*);
-+
-+typedef struct si2168b_context {
-+	struct i2c_adapter *i2c_adap;
-+	u8  address;
-+	u8  i2c_addr;
-+	u8  power_up_reset;
-+	u8  power_up_func;
-+	u8  scan_ctrl_action;
-+	u8  dd_mode_modulation;
-+	u8  dd_mode_auto_detect;
-+	u8  dd_mode_invert_spectrum;
-+	u8  dd_mode_bw;
-+	u8  dvbt_hierarchy_stream;
-+	u16 dvbc_symbol_rate;
-+	u16 scan_fmin;
-+	u16 scan_fmax;
-+	u16 scan_symb_rate_min;
-+	u16 scan_symb_rate_max;
-+	u8  status_ddint;
-+	u8  status_scanint;
-+	u8  status_err;
-+	u8  status_cts;
-+	u8  media;
-+
-+	/* _additional_struct_members_point */
-+	Si2168B_CLOCK_SOURCE tuner_ter_clock_source;
-+	u8  tuner_ter_clock_freq;
-+	u16 tuner_ter_clock_input;
-+	u8  tuner_ter_clock_control;
-+	u8  fef_selection;
-+	u8  fef_mode;
-+	u8  fef_pin;   /* FEF pin connected to TER tuner AGC freeze input      */
-+	u8  fef_level; /* GPIO state on FEF_pin when used (during FEF periods) */
-+	u8  Si2168B_in_standby;
-+	struct mutex lock;
-+	struct mutex ts_bus_ctrl_lock;
-+} si2168b_context;
-+
-+typedef struct Si2168B_L2_Context {
-+	si2168b_context *demod;
-+	Si2168B_INDIRECT_I2C_FUNC  f_TER_tuner_enable;
-+	Si2168B_INDIRECT_I2C_FUNC  f_TER_tuner_disable;
-+	void *callback;
-+	u8  standard;
-+	u8  previous_standard;
-+	u8  first_init_done;
-+	u8  Si2168B_init_done;
-+	u8  TER_init_done;
-+	u8  tuner_indirect_i2c_connection;
-+	u8  auto_detect_TER;
-+	u8  tuneUnitHz;
-+	u8  seekAbort;
-+	u8  handshakeUsed;
-+	u32 handshakeStart_ms;
-+	u32 handshakePeriod_ms;
-+	u8  handshakeOn;
-+} Si2168B_L2_Context;
-+
-+/* firmware_struct needs to be declared to allow loading the FW in 16 bytes mode */
-+#ifndef __FIRMWARE_STRUCT__
-+#define __FIRMWARE_STRUCT__
-+typedef struct firmware_struct {
-+	u8 firmware_len;
-+	u8 firmware_table[16];
-+} firmware_struct;
-+#endif /* __FIRMWARE_STRUCT__ */
-+
-+struct Si2168B_Priv {
-+	struct i2c_adapter *i2c;
-+	const struct si2168b_config *config;
-+	struct dvb_frontend frontend;
-+	Si2168B_L2_Context *si_front_end;
-+	enum fe_delivery_system delivery_system;
-+	bool last_tune_failed; /* for switch between T and T2 tune */
-+};
-+
-+#if defined(SiTRACES)
-+static void sitrace_default_configuration(void);
-+static void sitrace_function(const char *name, int trace_linenumber, const char *func, const char *fmt, ...);
-+#ifdef DRIVER_BUILD
-+#define SiTraceConfiguration(...) /* empty */
-+#else
-+char * SiTraceConfiguration(const char *config);
-+#endif
-+static void sitraces_suspend(void);
-+static void sitraces_resume(void);
-+#else
-+#define SiTraceDefaultConfiguration(...) /* empty */
-+#define SiTracesSuspend()                /* empty */
-+#define SiTracesResume()                 /* empty */
-+#define sitraces_suspend()               /* empty */
-+#define sitraces_resume()                /* empty */
-+#endif /* SiTRACES */
-+
-+#ifndef __FIRMWARE_STRUCT__
-+#define __FIRMWARE_STRUCT__
-+typedef struct  {
-+	u8 firmware_len;
-+	u8 firmware_table[16];
-+} firmware_struct;
-+#endif /* __FIRMWARE_STRUCT__ */
-+
-+#define _Si2168B_PATCH16_4_0b9_TABLE_H_
-+
-+#define Si2168B_PATCH16_4_0b9_PART    68
-+#define Si2168B_PATCH16_4_0b9_ROM      1
-+#define Si2168B_PATCH16_4_0b9_PMAJOR  '4'
-+#define Si2168B_PATCH16_4_0b9_PMINOR  '0'
-+#define Si2168B_PATCH16_4_0b9_PBUILD   2
-+
-+#ifndef __FIRMWARE_STRUCT__
-+#define __FIRMWARE_STRUCT__
-+typedef struct firmware_struct {
-+	u8 firmware_len;
-+	u8 firmware_table[16];
-+} firmware_struct;
-+#endif /* __FIRMWARE_STRUCT__ */
-+
-+firmware_struct Si2168B_PATCH16_4_0b9[] = {
-+		{  8 , { 0x05,0x00,0xF6,0x30,0x56,0x40,0x00,0x00 } },
-+		{  8 , { 0x0C,0x58,0x70,0xA0,0x93,0x5E,0x38,0x95 } },
-+		{  3 , { 0x4A,0x4F,0xFA } },
-+		{  8 , { 0x0C,0xD2,0xAA,0x09,0x35,0xDD,0xF3,0x87 } },
-+		{  6 , { 0x4D,0x8E,0x5B,0xAC,0x28,0xB5 } },
-+		{  8 , { 0x0C,0x53,0x6F,0x17,0xD9,0x7C,0x82,0xBD } },
-+		{  3 , { 0x4A,0x55,0xF4 } },
-+		{  8 , { 0x0C,0xC4,0x62,0x78,0x18,0x46,0x92,0xCF } },
-+		{ 12 , { 0x3B,0xC5,0x82,0xE0,0xD9,0x60,0x03,0xDC,0x4C,0x1B,0xA0,0xC7 } },
-+		{  8 , { 0x08,0xEE,0x78,0xEE,0xD4,0xCF,0x22,0xAA } },
-+		{  8 , { 0x0C,0x03,0xCD,0x8E,0x92,0xD6,0x73,0xA6 } },
-+		{  3 , { 0x42,0x10,0xAA } },
-+		{  8 , { 0x0C,0x16,0xB2,0xD3,0x2D,0xC0,0xBB,0xF5 } },
-+		{  3 , { 0x4A,0x95,0x66 } },
-+		{  8 , { 0x0C,0xEC,0xA1,0x54,0xC2,0xA2,0x1E,0xCD } },
-+		{ 16 , { 0x3F,0x4F,0xF5,0x82,0x11,0x5D,0xD9,0x99,0x0D,0xD1,0xE7,0xBC,0xCA,0x9C,0x50,0x52 } },
-+		{  3 , { 0x4A,0x2A,0xBC } },
-+		{  8 , { 0x09,0x65,0x97,0x63,0x35,0xFB,0xDC,0xEF } },
-+		{  8 , { 0x09,0x2E,0xC0,0x2B,0xC4,0xBF,0x17,0x6E } },
-+		{  8 , { 0x08,0x27,0x3D,0x6F,0x7A,0x38,0x99,0x91 } },
-+		{  9 , { 0x38,0xE2,0xAC,0x75,0xDC,0x28,0x6A,0x7D,0x63 } },
-+		{  8 , { 0x08,0xEA,0xA3,0xAF,0xC6,0x01,0xE7,0x58 } },
-+		{  5 , { 0x44,0x97,0x01,0x98,0xBC } },
-+		{  8 , { 0x09,0x50,0x28,0x28,0xFA,0x1E,0x0B,0xC5 } },
-+		{ 13 , { 0x34,0x30,0xA5,0x54,0x05,0x07,0xE4,0x44,0x1C,0xEE,0x15,0xD4,0x87 } },
-+		{  8 , { 0x08,0xC2,0xF6,0x3D,0x59,0xF4,0x0D,0xC0 } },
-+		{  4 , { 0x43,0xD5,0x47,0x3C } },
-+		{  8 , { 0x09,0x40,0xC7,0xBF,0x5E,0x22,0x74,0x99 } },
-+		{ 16 , { 0x3F,0xFC,0xF1,0x57,0x95,0x67,0x26,0xA7,0x38,0x7A,0xB4,0x9B,0xFD,0xA5,0x29,0xB9 } },
-+		{ 16 , { 0x3F,0x71,0x73,0x43,0xB4,0x27,0x6D,0xAB,0x98,0xC9,0x95,0xD6,0x8F,0x77,0xE6,0xDF } },
-+		{ 12 , { 0x3B,0x84,0xC5,0x5B,0x75,0x7F,0x80,0x6C,0xED,0x09,0x65,0xE8 } },
-+		{  8 , { 0x09,0x32,0xE6,0x0D,0x2D,0x20,0x13,0x94 } },
-+		{ 16 , { 0x3F,0x4B,0xC8,0xAC,0x22,0x45,0x44,0x2F,0x99,0xA7,0x2E,0x1F,0xD9,0xDE,0xF4,0x76 } },
-+		{ 16 , { 0x37,0x9B,0x3F,0xAA,0x3A,0x33,0x16,0xA4,0xD5,0xDF,0xD9,0xBA,0x5C,0x3A,0x39,0x2B } },
-+		{  8 , { 0x09,0xE0,0xAD,0xDE,0x8A,0x6B,0x2F,0xDB } },
-+		{ 16 , { 0x37,0xC5,0xE2,0xAC,0x74,0x5D,0x77,0xAC,0x2E,0x79,0x2B,0x65,0x66,0xCA,0xDE,0xB2 } },
-+		{ 16 , { 0x37,0xEF,0x9C,0x99,0x03,0x34,0xF7,0xEF,0xEE,0x71,0xD1,0x71,0xCE,0x0B,0xF3,0x23 } },
-+		{ 16 , { 0x3F,0xCE,0xAC,0xF4,0x52,0x29,0x1D,0xFD,0xA8,0xF9,0xDC,0xCA,0x5B,0x71,0xF8,0x7B } },
-+		{ 16 , { 0x3F,0x20,0xB1,0xB9,0xA8,0xBA,0x4E,0xC3,0x43,0xBF,0xD4,0x37,0xE1,0x21,0xED,0x4E } },
-+		{ 16 , { 0x37,0x02,0xE2,0x06,0x37,0x01,0x19,0x03,0x46,0x9E,0x25,0xC2,0xAF,0xA5,0x0C,0x05 } },
-+		{ 16 , { 0x3F,0x24,0xFB,0x02,0x2F,0x87,0x72,0x72,0x78,0x33,0x20,0x06,0xC4,0x92,0x11,0x52 } },
-+		{ 16 , { 0x3F,0x12,0x59,0xDB,0xB6,0xA0,0xF6,0x5F,0x8D,0xF5,0x5D,0x42,0x6F,0x0B,0x85,0xFF } },
-+		{ 16 , { 0x37,0x9D,0x7F,0xC0,0x52,0xA4,0xB1,0xA7,0xC6,0x15,0x78,0xDF,0xFA,0x1D,0x25,0xEA } },
-+		{ 13 , { 0x3C,0x4C,0xFA,0x1F,0x73,0x44,0x7B,0xEA,0x30,0xBD,0xD6,0xB6,0xCF } },
-+		{  8 , { 0x0C,0x64,0x3E,0xB6,0x62,0xE2,0x4F,0x90 } },
-+		{ 16 , { 0x3F,0x04,0xA9,0xCF,0xC3,0x9C,0x93,0xFE,0x68,0x91,0xD3,0x30,0x5F,0x5C,0x34,0x4A } },
-+		{ 10 , { 0x39,0xDB,0xD8,0x30,0x2F,0xB5,0x7A,0xFE,0x1A,0x37 } },
-+		{  8 , { 0x0C,0x5A,0x55,0x79,0xD2,0x70,0xCC,0x14 } },
-+		{  3 , { 0x4A,0x61,0xD8 } },
-+		{  8 , { 0x08,0xBF,0x36,0xE1,0x0F,0x76,0x0E,0x97 } },
-+		{  8 , { 0x09,0xBF,0x03,0x26,0xB6,0x79,0x25,0x4C } },
-+		{  8 , { 0x09,0x23,0xE6,0x93,0x4E,0xC1,0x1D,0xE6 } },
-+		{  8 , { 0x0C,0x65,0x84,0xE0,0x20,0xAB,0x9A,0xA7 } },
-+		{  5 , { 0x44,0xF2,0xCE,0x5B,0x51 } },
-+		{  8 , { 0x0C,0xF6,0x12,0xDA,0x80,0x37,0x21,0x29 } },
-+		{  5 , { 0x44,0x4F,0x25,0x61,0xA1 } },
-+		{  8 , { 0x0C,0x98,0xC3,0x69,0x6C,0x0A,0xBD,0x02 } },
-+		{  9 , { 0x30,0x6D,0xA6,0x9C,0xE7,0x35,0xE1,0xF8,0xB2 } },
-+		{  8 , { 0x0C,0x74,0xA9,0x08,0x36,0xAC,0x71,0xD7 } },
-+		{  5 , { 0x44,0x3E,0x84,0x38,0x27 } },
-+		{  8 , { 0x0C,0x1A,0x98,0xB0,0x3D,0x03,0x53,0xD6 } },
-+		{  5 , { 0x44,0xE6,0x56,0xFF,0x61 } },
-+		{  8 , { 0x0C,0x8F,0xCC,0xCA,0xB6,0x41,0x85,0xDE } },
-+		{  5 , { 0x4C,0xB1,0x93,0xE7,0x2A } },
-+		{  8 , { 0x0C,0x0A,0xBD,0xB6,0xED,0xD5,0xC0,0x5B } },
-+		{  5 , { 0x4C,0x2B,0x36,0x8D,0xA2 } },
-+		{  8 , { 0x0C,0x7A,0x22,0x9D,0x40,0x0F,0x83,0xE9 } },
-+		{  5 , { 0x4C,0xE0,0x9D,0xC6,0xE1 } },
-+		{  8 , { 0x0C,0xFA,0x6E,0x54,0x74,0x21,0xBF,0x33 } },
-+		{  5 , { 0x44,0xB1,0xE5,0xC4,0xCC } },
-+		{  8 , { 0x0C,0xEF,0xFB,0xE5,0x37,0x7E,0xB8,0xC0 } },
-+		{ 16 , { 0x3F,0xF5,0x51,0x23,0xE2,0x63,0x8A,0x44,0xF2,0xD1,0x48,0xAA,0x8E,0x32,0x3F,0x24 } },
-+		{  2 , { 0x49,0x54 } },
-+		{  8 , { 0x0C,0xBF,0x04,0xB0,0xDA,0xEF,0xD3,0x63 } },
-+		{  5 , { 0x4C,0xEF,0xE1,0x6F,0xD0 } },
-+		{  8 , { 0x0C,0x23,0xC4,0xF2,0xB0,0x9F,0x5D,0xF8 } },
-+		{  5 , { 0x44,0x76,0x8F,0x57,0x79 } },
-+		{  8 , { 0x0C,0x11,0xE4,0xE8,0x77,0x54,0x91,0x24 } },
-+		{  5 , { 0x4C,0x94,0x2F,0x21,0xF6 } },
-+		{  8 , { 0x0C,0x4A,0xBE,0xCC,0xE2,0xC5,0x58,0xCF } },
-+		{  5 , { 0x4C,0x79,0xEE,0x3E,0xE6 } },
-+		{  8 , { 0x0C,0xE0,0xD0,0x42,0xAA,0xFB,0xBB,0xAC } },
-+		{  5 , { 0x44,0xC4,0x86,0x6D,0x84 } },
-+		{  8 , { 0x0C,0x04,0x16,0x66,0x22,0xDA,0x5E,0x1C } },
-+		{  5 , { 0x44,0xE2,0xE2,0x56,0x4D } },
-+		{  8 , { 0x0C,0x2D,0x68,0x26,0xE7,0xAA,0x22,0x0A } },
-+		{  5 , { 0x44,0x10,0x7F,0x20,0xF6 } },
-+		{  8 , { 0x0C,0x60,0x61,0xD4,0xE4,0xD1,0xBF,0x01 } },
-+		{  5 , { 0x4C,0x58,0x91,0xA2,0xF2 } },
-+		{  8 , { 0x0C,0xA9,0xD1,0x46,0x0A,0x23,0xBB,0xB8 } },
-+		{  9 , { 0x38,0x84,0xBF,0x5A,0xAB,0x0D,0x95,0x87,0x60 } },
-+		{  8 , { 0x0C,0x75,0xE8,0x5D,0x32,0x86,0x20,0x8D } },
-+		{  5 , { 0x4C,0xD0,0x18,0xDA,0x26 } },
-+		{  8 , { 0x0C,0xF1,0xE0,0x5E,0xF7,0x77,0xCE,0xFF } },
-+		{  5 , { 0x4C,0x78,0x75,0x06,0xBF } },
-+		{  8 , { 0x0C,0x18,0x5A,0x27,0xE7,0x2A,0x50,0x94 } },
-+		{  5 , { 0x4C,0xD0,0xAC,0x59,0xDD } },
-+		{  8 , { 0x0C,0x92,0xB2,0xFD,0xB9,0xE0,0x7A,0x15 } },
-+		{  5 , { 0x4C,0x6A,0x3C,0x2B,0xD3 } },
-+		{  8 , { 0x0C,0x2D,0xF3,0x5C,0x73,0xD2,0x3C,0x0F } },
-+		{  5 , { 0x4C,0xFA,0xE2,0xA5,0x9D } },
-+		{  8 , { 0x0C,0xFE,0xCD,0x58,0x12,0x14,0xA9,0x19 } },
-+		{  5 , { 0x4C,0x97,0x9A,0xF9,0xA9 } },
-+		{  8 , { 0x0C,0x4F,0x48,0xAC,0xF1,0x7B,0x52,0xE6 } },
-+		{ 13 , { 0x3C,0x1B,0x90,0xB6,0xD1,0x38,0x35,0xE8,0x29,0x04,0x18,0xD3,0x16 } },
-+		{  8 , { 0x0C,0xBD,0x2C,0x0F,0xFC,0x2B,0xFF,0xD9 } },
-+		{  5 , { 0x4C,0xEE,0x32,0x98,0x52 } },
-+		{  8 , { 0x0C,0xF5,0x9E,0x18,0x04,0xBE,0x0E,0xCD } },
-+		{ 13 , { 0x3C,0x29,0xC5,0x08,0x14,0x7B,0x01,0x05,0xAB,0x1C,0xE1,0x07,0xF6 } },
-+		{  8 , { 0x0C,0x97,0xA0,0xE5,0x29,0x15,0xD1,0x32 } },
-+		{  5 , { 0x44,0x30,0x41,0x18,0xA3 } },
-+		{  8 , { 0x0C,0xAC,0x97,0xBE,0xAE,0x5F,0xFE,0x0B } },
-+		{  5 , { 0x4C,0x60,0x20,0xB8,0x04 } },
-+		{  8 , { 0x0C,0xA9,0x9F,0x96,0x2E,0xF7,0x11,0x05 } },
-+		{  5 , { 0x44,0x1B,0x00,0x99,0xE5 } },
-+		{  8 , { 0x0C,0x92,0x29,0x74,0x3B,0x1C,0x50,0x7C } },
-+		{ 16 , { 0x37,0x0F,0xE9,0x22,0x33,0x2A,0x96,0x93,0x9E,0x99,0x71,0xA4,0x5D,0xA2,0xC5,0x4A } },
-+		{  2 , { 0x49,0xB4 } },
-+		{  8 , { 0x08,0x95,0x6D,0x10,0x64,0x62,0xF2,0x68 } },
-+		{ 16 , { 0x3F,0x1F,0xE6,0x74,0x05,0x4E,0x58,0xE0,0x8E,0x17,0x31,0x18,0x3F,0xB7,0xEC,0x68 } },
-+		{  2 , { 0x49,0x96 } },
-+		{  8 , { 0x09,0x61,0xC0,0x9C,0x35,0x49,0x44,0x82 } },
-+		{  8 , { 0x08,0x1C,0x39,0x93,0xC8,0xBD,0xF1,0x87 } },
-+		{ 16 , { 0x3F,0x3A,0x78,0xF2,0x62,0x23,0x18,0x11,0x13,0xEB,0xDF,0x66,0x9A,0x2D,0x40,0x5E } },
-+		{ 16 , { 0x37,0x91,0x61,0x2B,0x76,0xF7,0x15,0xF9,0xCD,0x82,0xB7,0x97,0xB4,0xF5,0x5D,0x7A } },
-+		{ 16 , { 0x37,0xED,0x0A,0x9F,0xF1,0x60,0xAA,0xF4,0x30,0x65,0xC0,0xDF,0x73,0x56,0x9D,0xE2 } },
-+		{  4 , { 0x4B,0x6B,0xB3,0x23 } },
-+		{  8 , { 0x09,0xFB,0x68,0xD7,0x90,0x6D,0x20,0xA2 } },
-+		{  5 , { 0x44,0x7C,0x22,0xF3,0x48 } },
-+		{  8 , { 0x09,0x47,0x06,0x1B,0x86,0x03,0xAC,0x02 } },
-+		{ 16 , { 0x37,0x06,0xF1,0xB0,0xF6,0xC1,0x21,0x94,0xB7,0xA4,0xDB,0x07,0x70,0x65,0x70,0xB7 } },
-+		{ 16 , { 0x37,0xFE,0x60,0x67,0x04,0x50,0x0D,0xC4,0x4D,0x1F,0x3F,0xCD,0xE2,0x0D,0x2A,0xF4 } },
-+		{ 11 , { 0x3A,0x98,0x70,0x26,0x0F,0x02,0x44,0xD9,0x5B,0x7A,0x25 } },
-+		{  8 , { 0x09,0x70,0x85,0x33,0x5C,0xB0,0x38,0x76 } },
-+		{ 16 , { 0x37,0xB4,0x46,0x17,0xC8,0x3B,0x40,0x06,0xF6,0x09,0xC1,0x50,0xFC,0x88,0xF8,0x78 } },
-+		{  6 , { 0x45,0x58,0x72,0x01,0x68,0x55 } },
-+		{  8 , { 0x08,0xC3,0x6B,0x35,0x0B,0x23,0x96,0x68 } },
-+		{ 13 , { 0x34,0xFE,0x7E,0xC9,0x63,0xAE,0x53,0xDB,0x84,0x39,0xE5,0x49,0xC4 } },
-+		{  8 , { 0x09,0x78,0xD6,0x0A,0x49,0x2E,0xA9,0x12 } },
-+		{ 16 , { 0x3F,0x52,0x76,0xCD,0x56,0x9C,0xB5,0xD1,0x28,0xA0,0x76,0x38,0x86,0x0E,0x6F,0xEE } },
-+		{ 16 , { 0x3F,0x27,0xFF,0x9D,0xD2,0xAF,0xAB,0x85,0xAB,0x99,0x66,0x59,0x4E,0x65,0x22,0xDF } },
-+		{ 16 , { 0x3F,0x6A,0x5F,0x3F,0x88,0xB1,0x12,0x3B,0x98,0x87,0xCD,0x33,0x17,0x58,0xAA,0x94 } },
-+		{  4 , { 0x43,0xC3,0xD6,0xE6 } },
-+		{  8 , { 0x08,0x66,0x32,0xC6,0xE7,0x19,0x82,0x94 } },
-+		{  5 , { 0x44,0x13,0x97,0x1A,0x8C } },
-+		{ 16 , { 0x37,0x7B,0x0A,0xC5,0x48,0xA8,0xAF,0x6C,0xA1,0x85,0x76,0x54,0x67,0xE8,0x36,0xDE } },
-+		{ 16 , { 0x3F,0x45,0x8A,0xE8,0x61,0xB7,0xEE,0xB9,0xD1,0x45,0x51,0x79,0xDF,0x92,0xD9,0x9E } },
-+		{ 15 , { 0x3E,0xF5,0x2B,0x36,0xF7,0xF6,0xD7,0x19,0x01,0xAF,0x24,0x2F,0xBA,0xCD,0xA7 } },
-+		{  9 , { 0x30,0x91,0xE3,0x38,0x34,0xF6,0x6E,0xF0,0x92 } },
-+		{  8 , { 0x09,0x7A,0xD7,0x88,0x59,0x78,0xF9,0x59 } },
-+		{  5 , { 0x4C,0x57,0xFB,0xBF,0xAC } },
-+		{  8 , { 0x09,0x4B,0x26,0xCE,0x3B,0x4B,0xEE,0x40 } },
-+		{ 16 , { 0x3F,0xF0,0xB2,0x05,0xAC,0x79,0x46,0xE6,0x7D,0xBA,0xB1,0x03,0xCF,0x1E,0x9B,0x64 } },
-+		{ 16 , { 0x3F,0x78,0x48,0xC1,0xE6,0xB1,0xD6,0x82,0x74,0x76,0x42,0x58,0x60,0xE5,0x8B,0x88 } },
-+		{ 16 , { 0x37,0x11,0x9D,0xE5,0x9C,0xEE,0x0D,0xC3,0x67,0x6F,0x5D,0x3D,0x1F,0x23,0x13,0x7D } },
-+		{  8 , { 0x4F,0x87,0x20,0x35,0xEF,0xA2,0x48,0xCA } },
-+		{  8 , { 0x09,0xA6,0x14,0x0A,0xF5,0xD2,0xFE,0xAE } },
-+		{ 13 , { 0x3C,0x5A,0x4D,0xCE,0x7B,0x72,0x54,0x2D,0xF5,0x6A,0xC6,0xC7,0x2B } },
-+		{  8 , { 0x08,0xF3,0xD9,0xF6,0x53,0x35,0xDE,0xA5 } },
-+		{  5 , { 0x44,0xED,0xD5,0x5C,0x8C } },
-+		{  8 , { 0x09,0xDB,0xB8,0x6B,0x17,0x9A,0xC1,0x11 } },
-+		{  9 , { 0x38,0x5C,0x74,0x5A,0x22,0x89,0x60,0x5B,0xAA } },
-+		{  8 , { 0x08,0x5E,0x13,0x0B,0x04,0xD3,0xFC,0xFF } },
-+		{ 13 , { 0x34,0x68,0x58,0xCC,0x67,0x2B,0x87,0xE3,0x8D,0xEF,0x87,0x1F,0x32 } },
-+		{  8 , { 0x09,0x21,0x6F,0xBD,0x66,0x70,0xD8,0xC1 } },
-+		{ 16 , { 0x3F,0x7E,0xC0,0xEF,0x53,0x59,0x30,0x8C,0xE3,0x18,0x28,0x80,0x21,0x7F,0x60,0x64 } },
-+		{ 16 , { 0x3F,0xFC,0x48,0x57,0x25,0x34,0xD4,0xA8,0xA1,0x43,0x24,0x27,0x2D,0x56,0xFE,0x01 } },
-+		{  3 , { 0x4A,0x57,0x84 } },
-+		{  8 , { 0x08,0xAF,0x8D,0xAF,0x3F,0xB1,0x32,0x44 } },
-+		{ 13 , { 0x34,0xA6,0x91,0xDE,0x72,0x1D,0xA2,0x93,0x46,0xC3,0x4E,0x17,0x38 } },
-+		{  8 , { 0x09,0x26,0x42,0x44,0x9D,0x31,0x64,0xB1 } },
-+		{ 16 , { 0x37,0xA9,0x53,0x9E,0x8D,0x66,0xD6,0x00,0xAC,0xEF,0x05,0x82,0xE8,0x8E,0xD7,0x2E } },
-+		{ 16 , { 0x3F,0xCF,0xD3,0x4D,0xFA,0x81,0x57,0xC2,0xF3,0x50,0x24,0x18,0x94,0xED,0xE6,0x6C } },
-+		{ 16 , { 0x3F,0x80,0xE7,0x7C,0x16,0xE1,0x26,0xB7,0x33,0x5F,0x4B,0x9E,0xF4,0x05,0x48,0x44 } },
-+		{ 16 , { 0x3F,0x44,0xEF,0x9D,0xF9,0x40,0xE5,0xA6,0x73,0xA5,0x76,0xF3,0x0E,0x15,0x66,0x2A } },
-+		{ 16 , { 0x37,0xF0,0xF9,0x7C,0xE2,0x35,0x47,0x57,0xB5,0x0C,0xE5,0x0D,0x4B,0xE0,0x4F,0x1B } },
-+		{ 14 , { 0x3D,0x24,0x58,0x97,0x02,0x2F,0xA2,0x4A,0x59,0xA9,0xD7,0xDE,0x9C,0x9E } },
-+		{  8 , { 0x08,0x9A,0xCD,0xEF,0x62,0xCF,0xB6,0x61 } },
-+		{ 16 , { 0x37,0xFE,0x79,0xFB,0x0A,0x3E,0x19,0x70,0x03,0x94,0x5E,0x6E,0x63,0x71,0xE3,0x06 } },
-+		{ 14 , { 0x35,0x54,0x2D,0x0F,0x07,0xBB,0x46,0x9E,0x34,0xF8,0xBA,0x87,0x0B,0xA6 } },
-+		{  8 , { 0x09,0x47,0x0B,0x2F,0x06,0xF3,0x6E,0x1D } },
-+		{ 16 , { 0x37,0x9F,0x27,0xCA,0x16,0xAC,0x24,0x71,0x8E,0xB2,0xD2,0x35,0x09,0x8C,0xAD,0x81 } },
-+		{ 16 , { 0x3F,0x82,0xF9,0xDA,0x35,0xEF,0x0C,0x7C,0x2C,0x11,0xE1,0x43,0x8A,0x29,0x42,0x05 } },
-+		{ 11 , { 0x32,0xA5,0x72,0x9C,0x34,0x7F,0x0D,0xC6,0xCF,0xF2,0x1D } },
-+		{  8 , { 0x08,0xED,0x1F,0x44,0x44,0x2C,0x17,0x10 } },
-+		{  8 , { 0x08,0xBD,0x19,0x2E,0xC6,0x50,0x2F,0xEE } },
-+		{  8 , { 0x09,0x1F,0x38,0x17,0x95,0x2C,0xE6,0x27 } },
-+		{ 16 , { 0x37,0x4F,0x69,0x25,0x5E,0xC9,0xC0,0xF4,0xAB,0xA2,0x22,0xCB,0x6F,0xEA,0xE0,0x5A } },
-+		{ 16 , { 0x37,0x2D,0xCD,0x85,0xCE,0x41,0x68,0xD9,0x0D,0x5C,0x7A,0x6A,0x02,0x56,0xAF,0xEB } },
-+		{ 16 , { 0x37,0xF4,0x10,0x4F,0x26,0x9C,0x8B,0x60,0x9F,0x68,0x3F,0xD6,0x93,0x6D,0x44,0xC6 } },
-+		{ 12 , { 0x33,0x00,0xAC,0x78,0xE9,0xFA,0xC3,0x23,0x0E,0x08,0x9B,0xC9 } },
-+		{  8 , { 0x09,0x35,0x6A,0x8B,0xB1,0xC4,0xFD,0x82 } },
-+		{  5 , { 0x4C,0x56,0x39,0x5C,0x71 } },
-+		{  8 , { 0x08,0x4C,0x31,0xB8,0x3C,0x35,0x55,0x0E } },
-+		{  8 , { 0x08,0x52,0xB6,0x48,0xCA,0x40,0xF8,0xBA } },
-+		{ 16 , { 0x37,0x85,0x77,0x83,0x57,0x26,0x9E,0xEC,0x2D,0x81,0x3A,0x47,0x64,0x49,0x4E,0x47 } },
-+		{ 16 , { 0x37,0x70,0xB5,0x66,0x86,0xC6,0x4C,0x24,0x6A,0x68,0x08,0x8F,0xBE,0xAE,0x4E,0xC4 } },
-+		{ 16 , { 0x3F,0x98,0xD2,0x93,0xA9,0x12,0x4D,0x50,0x0B,0x81,0x66,0x76,0xA8,0x52,0x06,0xC6 } },
-+		{  4 , { 0x43,0x85,0xDC,0x56 } },
-+		{  8 , { 0x09,0xD7,0x87,0x39,0x2E,0xDD,0xB5,0xB6 } },
-+		{  5 , { 0x44,0x93,0x97,0x06,0x9C } },
-+		{  8 , { 0x09,0x73,0x13,0x82,0xF4,0x86,0x61,0xBF } },
-+		{ 16 , { 0x37,0xEE,0xAB,0xB5,0x6D,0x7E,0x15,0x5E,0x8F,0x08,0xBB,0xA5,0x8F,0x02,0xBA,0xDF } },
-+		{ 16 , { 0x37,0x9F,0xA6,0x5E,0x6D,0x3B,0x07,0xA1,0x0B,0x00,0xE4,0x59,0xCF,0x95,0x02,0x17 } },
-+		{ 16 , { 0x3F,0x4A,0x51,0xF9,0xE5,0xC7,0xEA,0xCA,0x17,0xBB,0xEC,0xE3,0x72,0xB8,0x38,0xD3 } },
-+		{ 16 , { 0x3F,0x3C,0x5F,0x81,0xAD,0xA7,0xC2,0x6B,0x9E,0x58,0x64,0xB5,0x1E,0xDF,0xBC,0x9D } },
-+		{ 16 , { 0x3F,0x1A,0x62,0x2B,0x7E,0x4E,0xD0,0x13,0x2A,0xEE,0xFA,0xBD,0x65,0xF6,0x66,0x61 } },
-+		{ 16 , { 0x37,0x98,0xBE,0xD4,0xEA,0xED,0x1B,0x7B,0x04,0xC4,0x32,0x52,0x4E,0x33,0x1A,0x8A } },
-+		{ 16 , { 0x3F,0x3E,0x8C,0x16,0xDE,0xC6,0x6E,0xBE,0x50,0x36,0x72,0xF6,0x26,0xE6,0x51,0xDE } },
-+		{ 16 , { 0x37,0xE5,0x60,0x86,0xC3,0xBE,0xC0,0x0F,0xBF,0x05,0x1F,0xED,0x23,0xC3,0x1D,0x13 } },
-+		{ 16 , { 0x3F,0x91,0xFF,0xB3,0x9A,0x12,0x8F,0x04,0x4D,0x23,0x48,0xAD,0x0E,0x46,0xA4,0xBB } },
-+		{ 16 , { 0x37,0x87,0xF1,0x65,0xE2,0xE8,0x29,0xDA,0x4B,0x1B,0x06,0x7C,0xF6,0xCF,0x14,0xD9 } },
-+		{ 16 , { 0x37,0x9D,0x62,0x38,0x13,0xFD,0x8D,0x8D,0xA7,0xB9,0xDE,0x06,0xCE,0xFF,0xE1,0xB5 } },
-+		{ 16 , { 0x37,0x23,0xFB,0x05,0xD1,0x48,0x3C,0x22,0x92,0x48,0x4F,0x08,0x0B,0x5D,0x0C,0x1B } },
-+		{  9 , { 0x38,0x49,0xC0,0x76,0x17,0xEB,0x3C,0x04,0xDC } },
-+		{  8 , { 0x08,0x29,0xB6,0x14,0xBF,0x69,0x79,0x13 } },
-+		{ 16 , { 0x3F,0xB8,0x0A,0x0A,0x97,0xCC,0xD5,0x0C,0x82,0x49,0x3A,0x81,0x5A,0x3E,0x25,0x84 } },
-+		{  6 , { 0x45,0x96,0x0B,0xA8,0x89,0xE6 } },
-+		{  8 , { 0x08,0x6F,0x77,0xA1,0xD4,0x50,0x7F,0xDB } },
-+		{  9 , { 0x38,0xAA,0xE7,0x85,0xFF,0x84,0x56,0xF4,0x3E } },
-+		{  8 , { 0x08,0x2A,0x70,0xD6,0x03,0x5C,0x4B,0xA5 } },
-+		{ 16 , { 0x3F,0x82,0xBC,0x35,0xA6,0xF7,0x6A,0x91,0x47,0x93,0x11,0x28,0xE4,0xE8,0x9E,0xA3 } },
-+		{  2 , { 0x49,0x07 } },
-+		{  8 , { 0x09,0xAD,0x07,0x5A,0xF2,0xAF,0x56,0x37 } },
-+		{ 16 , { 0x37,0xAF,0xE4,0x5E,0x58,0xF8,0x0A,0xDE,0x26,0x03,0x1B,0x5C,0x1C,0x81,0xF3,0xB0 } },
-+		{ 16 , { 0x3F,0xD7,0x45,0xCE,0xB0,0xBF,0xC2,0x55,0x28,0xA2,0xF8,0xB2,0x35,0x6E,0xE1,0x35 } },
-+		{ 15 , { 0x3E,0x17,0x2C,0x12,0x65,0x14,0x35,0xA6,0xA6,0x7A,0x8A,0xC3,0x9E,0x87,0x3C } },
-+		{  8 , { 0x08,0xC8,0x85,0x2D,0xC7,0xCC,0xF3,0xED } },
-+		{ 13 , { 0x34,0xC4,0xC3,0x32,0x18,0xA5,0x53,0x6B,0xD3,0x75,0x40,0x3D,0x44 } },
-+		{  8 , { 0x09,0xA7,0xDC,0xA4,0x12,0xEE,0xE3,0x8A } },
-+		{  9 , { 0x30,0x8E,0x7D,0x3B,0x11,0x55,0x02,0x49,0xC0 } },
-+		{  8 , { 0x08,0xE9,0x20,0xCC,0xB1,0x89,0xA2,0xF4 } },
-+		{ 16 , { 0x3F,0x8C,0x8E,0xCC,0xA2,0x89,0x74,0x0D,0x43,0x07,0x3E,0x3A,0xD4,0x9E,0xFF,0x92 } },
-+		{  6 , { 0x4D,0xAB,0x50,0x1C,0xEF,0x26 } },
-+		{  8 , { 0x09,0xA1,0xF6,0x31,0xB1,0x21,0x5B,0x18 } },
-+		{  8 , { 0x08,0x82,0xAF,0xF6,0x75,0x9E,0xF5,0xE5 } },
-+		{  5 , { 0x44,0xB0,0x28,0xA9,0x5A } },
-+		{  8 , { 0x08,0xF9,0xE1,0xBF,0x17,0x87,0x46,0x52 } },
-+		{  9 , { 0x38,0x92,0x8E,0x4C,0x3A,0x62,0x95,0x43,0xB6 } },
-+		{  8 , { 0x09,0x73,0xCC,0x09,0xEC,0x39,0x6B,0xF1 } },
-+		{ 16 , { 0x37,0x30,0x72,0x00,0x70,0x8D,0x5A,0x92,0x0B,0x60,0x73,0xFC,0x1D,0xCE,0xB9,0x44 } },
-+		{ 16 , { 0x3F,0x1D,0x5E,0x80,0x26,0x5C,0x3E,0x96,0xCF,0x07,0x8F,0x82,0x80,0xDF,0x25,0xD1 } },
-+		{ 16 , { 0x3F,0xCC,0x57,0xB9,0x5F,0xCA,0xAB,0x45,0xB1,0x0E,0xC7,0x3B,0x62,0x3A,0x30,0x01 } },
-+		{ 12 , { 0x33,0x32,0x0A,0xA4,0xBE,0xBE,0x99,0xD7,0xDC,0x95,0x88,0xFB } },
-+		{  8 , { 0x09,0xED,0x55,0xE1,0x3C,0x18,0x46,0x38 } },
-+		{ 16 , { 0x37,0x05,0xC4,0x09,0x1F,0xFA,0x8C,0x16,0xB1,0x7A,0x9F,0x89,0x0C,0x83,0x60,0xC1 } },
-+		{ 16 , { 0x3F,0xCA,0xCD,0x6E,0xEB,0xBD,0x49,0x97,0x1E,0x35,0x12,0x88,0x5C,0xE6,0xF7,0x98 } },
-+		{ 16 , { 0x3F,0xE8,0x2B,0x09,0x4D,0x20,0xFC,0x5D,0xE2,0xCA,0xF2,0x49,0xA5,0x9D,0x31,0x8A } },
-+		{ 16 , { 0x37,0x8A,0xFA,0x1F,0x45,0x41,0xD7,0x58,0x12,0x19,0x85,0x00,0x44,0xB2,0x25,0x65 } },
-+		{ 16 , { 0x37,0xEA,0xCE,0xAE,0x51,0xAB,0xC9,0x70,0x4D,0x62,0x90,0x29,0xDC,0x1D,0x09,0xCB } },
-+		{ 16 , { 0x37,0xF9,0x1F,0x54,0x3F,0x6D,0x3F,0x22,0x31,0x72,0x0C,0xC8,0x5E,0x4E,0x91,0x34 } },
-+		{ 16 , { 0x37,0x4E,0x62,0xC7,0x66,0xBB,0xD0,0xE2,0xB9,0x78,0x61,0x91,0x8C,0xA8,0x5E,0x17 } },
-+		{  8 , { 0x4F,0xC4,0xC9,0x92,0x59,0xEE,0x5D,0x5B } },
-+		{  8 , { 0x09,0xCA,0xF6,0xD7,0xCD,0xD5,0x3D,0x43 } },
-+		{ 16 , { 0x37,0x52,0xF3,0xD4,0x4E,0x2D,0xE6,0xB0,0xBD,0xDC,0x4C,0x35,0x68,0x16,0x03,0x93 } },
-+		{ 16 , { 0x3F,0xDD,0xA8,0x12,0xD5,0x79,0x45,0x67,0x26,0x0C,0x51,0x79,0x0B,0xA2,0x54,0x2F } },
-+		{ 16 , { 0x3F,0xA7,0x56,0x10,0x6F,0x24,0x28,0xE4,0x00,0x5A,0x49,0xD0,0xB9,0x2A,0x06,0x1F } },
-+		{ 16 , { 0x3F,0x79,0x0E,0x2E,0x83,0x73,0xA0,0x83,0xDA,0xD0,0x10,0x7B,0x83,0xFC,0x67,0x6F } },
-+		{  5 , { 0x44,0xCF,0xA9,0x50,0x91 } },
-+		{  8 , { 0x09,0xA6,0xFB,0x86,0xC8,0x29,0x89,0x28 } },
-+		{ 13 , { 0x34,0xDC,0x56,0x07,0x57,0x9F,0xC3,0xFB,0x41,0xEB,0xE6,0x4D,0x34 } },
-+		{  8 , { 0x09,0x9D,0x4C,0xA5,0x30,0x55,0x5D,0xD9 } },
-+		{ 13 , { 0x3C,0x4B,0x6F,0x76,0x77,0xC0,0xF8,0x43,0xCF,0x4D,0x1A,0x2E,0x30 } },
-+		{  8 , { 0x08,0xE3,0x0A,0x9D,0x98,0xE8,0x25,0xCF } },
-+		{ 13 , { 0x3C,0xB9,0x8E,0x93,0xFD,0x5C,0xF3,0xB9,0xB9,0xD9,0x0E,0x17,0xC8 } },
-+		{  8 , { 0x08,0xE5,0xDC,0xB4,0xB5,0x0F,0x98,0x17 } },
-+		{ 16 , { 0x3F,0xBB,0x57,0x3C,0x39,0xBD,0x08,0x95,0x38,0x50,0xEE,0x51,0xB5,0xC1,0xB7,0xC7 } },
-+		{ 16 , { 0x3F,0xF7,0x40,0xEC,0x32,0x6A,0xDA,0x10,0x53,0xFE,0x61,0x7F,0x83,0xC7,0xE8,0xC1 } },
-+		{ 16 , { 0x3F,0xEB,0xB3,0x78,0x08,0xDC,0xA8,0x60,0x81,0xC0,0x8C,0xDF,0xD8,0x5A,0xC8,0xF7 } },
-+		{ 12 , { 0x33,0xC8,0xFD,0x05,0xEB,0x76,0xEC,0x8E,0x5F,0x25,0xF7,0x6D } },
-+		{  8 , { 0x08,0x70,0x26,0xB9,0x7F,0xFA,0x22,0xEB } },
-+		{  9 , { 0x30,0x6C,0xDA,0xCD,0xA7,0x86,0x50,0xFD,0x26 } },
-+		{  8 , { 0x08,0x08,0xE0,0xE6,0x21,0xE8,0xCC,0x8C } },
-+		{ 16 , { 0x37,0x90,0x95,0x4A,0x38,0x84,0x29,0x10,0xF5,0x0C,0x08,0xD3,0xD8,0x2F,0x82,0xE9 } },
-+		{ 16 , { 0x3F,0x1D,0x05,0x60,0xBD,0x0F,0x8C,0x27,0xD9,0xB6,0xC6,0x8B,0x6F,0x28,0x1C,0x13 } },
-+		{ 15 , { 0x3E,0x37,0xB5,0x9C,0x38,0xD3,0xA1,0x12,0xEC,0xBA,0xF8,0x70,0x53,0xCF,0x16 } },
-+		{  8 , { 0x09,0x48,0x57,0x7A,0x00,0xE5,0x9C,0xDA } },
-+		{ 13 , { 0x34,0x9D,0xDC,0xEE,0x29,0x17,0x13,0x9D,0xE8,0x9E,0xBB,0x00,0xB0 } },
-+		{  8 , { 0x08,0xA7,0x36,0xE1,0x6B,0x48,0xD0,0x34 } },
-+		{ 13 , { 0x34,0xE7,0xDA,0x19,0xD3,0x7E,0x72,0xFE,0x90,0xAE,0xFD,0xEB,0x10 } },
-+		{  9 , { 0x38,0x70,0x17,0xCB,0x60,0xD3,0x2D,0x8C,0xEE } },
-+		{ 13 , { 0x3C,0x9F,0xEF,0xD3,0x42,0x6D,0x9A,0x4C,0x2E,0x5F,0x71,0x5C,0xDB } },
-+		{  8 , { 0x09,0x9F,0xA6,0x25,0x1A,0xF9,0x8E,0x5C } },
-+		{ 16 , { 0x37,0x86,0x9D,0xE9,0xB0,0x5B,0xFF,0xED,0x54,0x35,0x35,0xD6,0x53,0x83,0xE5,0x27 } },
-+		{ 16 , { 0x3F,0x49,0x92,0x79,0x9A,0xFB,0x31,0x3D,0x52,0x27,0xE4,0x03,0x82,0x29,0x2F,0xAE } },
-+		{ 11 , { 0x3A,0x67,0xBE,0x11,0x4D,0xD7,0x54,0x69,0x39,0x4C,0xA5 } },
-+		{  8 , { 0x08,0x23,0x53,0xF8,0xAD,0x1A,0x16,0x32 } },
-+		{ 16 , { 0x37,0xF1,0x60,0x33,0x96,0x65,0x9C,0xFA,0x0D,0xFE,0xB2,0x8B,0x23,0xC1,0x8E,0x71 } },
-+		{ 16 , { 0x37,0xD9,0x47,0xF3,0x29,0x7D,0x5F,0x45,0xDF,0x1C,0x06,0x48,0x9F,0x46,0x0E,0x92 } },
-+		{ 15 , { 0x3E,0xCF,0x0C,0xA9,0xEC,0xC7,0x04,0x32,0xE1,0x45,0xC6,0x4D,0x41,0xF8,0x4A } },
-+		{  8 , { 0x09,0x07,0x12,0x20,0x49,0x55,0x4D,0x7F } },
-+		{  8 , { 0x09,0xBE,0xB6,0x6E,0x4F,0x4B,0x6C,0x81 } },
-+		{ 16 , { 0x37,0xCD,0x51,0x38,0x9B,0x79,0x7C,0x51,0x03,0x5A,0x36,0xDF,0x82,0x19,0x26,0x72 } },
-+		{ 16 , { 0x37,0x33,0x0E,0xC1,0xE0,0xDD,0xE4,0x55,0x2A,0xD2,0xDE,0x6E,0x80,0x61,0x61,0x23 } },
-+		{  3 , { 0x42,0x6B,0x73 } },
-+		{  8 , { 0x08,0x46,0x0D,0x86,0x64,0xF1,0x19,0x6B } },
-+		{  5 , { 0x44,0xC1,0x08,0xE4,0x0C } },
-+		{  8 , { 0x09,0x01,0x11,0x85,0x50,0xA6,0x93,0xFA } },
-+		{  9 , { 0x30,0xDB,0xA2,0xC0,0x32,0x71,0x01,0x0E,0x74 } },
-+		{  8 , { 0x08,0x88,0x1D,0x53,0x31,0x2D,0xC7,0xDB } },
-+		{  5 , { 0x44,0xB7,0x51,0x3C,0xA1 } },
-+		{  8 , { 0x08,0xA6,0x93,0xF0,0xCD,0x5C,0x3B,0x7B } },
-+		{ 16 , { 0x3F,0x17,0x48,0x96,0x2D,0x0A,0xC3,0x14,0x70,0xD6,0xEC,0x24,0x71,0xDB,0xDB,0x82 } },
-+		{  2 , { 0x49,0x21 } },
-+		{  8 , { 0x09,0x57,0xDB,0xE1,0x20,0xFB,0x35,0x57 } },
-+		{  9 , { 0x30,0x5C,0xA6,0xAD,0x48,0xB4,0x01,0xBB,0xAA } },
-+		{  8 , { 0x08,0x24,0xC6,0xCA,0x88,0x05,0xEB,0x0D } },
-+		{  8 , { 0x09,0xFB,0x99,0x0D,0x52,0xC8,0x71,0x4B } },
-+		{  8 , { 0x09,0x98,0x83,0x4B,0x9C,0x41,0x93,0x5C } },
-+		{  8 , { 0x09,0xC0,0xA7,0x87,0xA8,0x67,0x51,0x2E } },
-+		{  8 , { 0x09,0x94,0x08,0xC0,0x40,0x10,0x05,0xF7 } },
-+		{ 16 , { 0x37,0xE7,0x85,0xBC,0x24,0xF5,0x61,0x3C,0xBE,0x31,0xC1,0x83,0xB7,0x79,0x7B,0x43 } },
-+		{ 14 , { 0x3D,0x23,0xB3,0x28,0x54,0x4C,0x71,0x5C,0x0C,0x0D,0x21,0x54,0x8D,0x0C } },
-+		{  8 , { 0x08,0xD2,0x3A,0x3D,0x3E,0xC0,0xF8,0xB9 } },
-+		{  5 , { 0x4C,0x67,0x23,0xFD,0x70 } },
-+		{  8 , { 0x08,0xC5,0x5F,0x78,0xAD,0x9A,0xF8,0x67 } },
-+		{ 13 , { 0x34,0x4F,0x69,0x06,0x88,0x5D,0x7C,0xDA,0x73,0xA6,0x17,0xEA,0x2C } },
-+		{  8 , { 0x08,0xDF,0xB2,0x29,0x5C,0x3B,0x23,0x37 } },
-+		{ 16 , { 0x3F,0x4C,0x6B,0xB5,0x32,0xB7,0x53,0x99,0xA8,0x80,0x84,0xE8,0xE9,0x71,0x64,0x53 } },
-+		{ 16 , { 0x3F,0x71,0xDB,0x81,0xBE,0x53,0xA7,0xF2,0x57,0xF1,0x54,0xBA,0x14,0x1C,0x42,0x10 } },
-+		{ 16 , { 0x3F,0x59,0x82,0xFE,0xCE,0xBE,0x25,0x1E,0x29,0x28,0x99,0x74,0x42,0xBA,0x9D,0x14 } },
-+		{ 12 , { 0x33,0x06,0xB7,0x70,0xF5,0x3A,0x89,0x4F,0x9C,0x0B,0xAE,0xA8 } },
-+		{  8 , { 0x08,0xD9,0x9A,0x8A,0x8C,0x3C,0x6A,0xB5 } },
-+		{  8 , { 0x09,0x34,0x15,0x18,0xBE,0xC4,0x27,0x0A } },
-+		{  9 , { 0x38,0x7A,0x10,0x24,0x6F,0x03,0x1C,0xB8,0xF2 } },
-+		{  8 , { 0x09,0x49,0x91,0xB8,0x48,0x5E,0x8D,0xEF } },
-+		{ 16 , { 0x37,0xDB,0xB7,0x21,0xA1,0x45,0x9A,0xC3,0x91,0x09,0xE5,0xD4,0xC4,0x67,0x81,0xE9 } },
-+		{ 16 , { 0x37,0x54,0xE4,0x9E,0x5E,0x2D,0x85,0xF0,0x89,0x6C,0xFC,0xBF,0x26,0x4E,0xC1,0xD2 } },
-+		{  7 , { 0x46,0x94,0xC0,0x9A,0xCC,0x58,0x8D } },
-+		{  8 , { 0x09,0x2F,0x2B,0xD6,0xC3,0xCC,0x48,0x83 } },
-+		{  9 , { 0x38,0x96,0x61,0xE9,0x98,0xB3,0x44,0x12,0xE6 } },
-+		{  8 , { 0x08,0x82,0xE4,0x8D,0x30,0xDA,0xDE,0x5B } },
-+		{  9 , { 0x30,0x4F,0xE9,0x03,0xFF,0x9B,0x20,0x0B,0xD8 } },
-+		{  8 , { 0x09,0x81,0x4B,0x22,0xD3,0xE2,0xA5,0x2E } },
-+		{ 16 , { 0x37,0xDC,0xF7,0x8D,0xFA,0xC8,0xBE,0x3D,0x7D,0xBC,0x2E,0x62,0x20,0x17,0x87,0x1B } },
-+		{  2 , { 0x41,0x64 } },
-+		{  8 , { 0x08,0xE8,0x9F,0xDE,0x19,0xCD,0x78,0xEE } },
-+		{  9 , { 0x38,0x42,0xAA,0xBE,0x44,0xAC,0xFA,0x33,0x78 } },
-+		{  8 , { 0x08,0xD7,0x97,0x0C,0x6C,0xF2,0xEC,0xE7 } },
-+		{  5 , { 0x44,0x3E,0x3D,0x8F,0x96 } },
-+		{  8 , { 0x09,0x36,0x0E,0xA2,0xB8,0xF8,0x01,0x1C } },
-+		{  8 , { 0x09,0xA3,0xA3,0xD2,0x53,0x5F,0xD4,0xD0 } },
-+		{ 16 , { 0x3F,0xFA,0xD0,0xBF,0xD6,0x21,0xB4,0x67,0xA0,0xCC,0x51,0xDC,0xB5,0x7D,0xFD,0xBE } },
-+		{  2 , { 0x49,0x20 } },
-+		{  8 , { 0x08,0xC1,0xE2,0x4D,0xF4,0x56,0xAD,0xAD } },
-+		{  8 , { 0x08,0x12,0xDF,0x04,0xA3,0x1B,0xC2,0x81 } },
-+		{ 16 , { 0x3F,0x83,0xD3,0x97,0x48,0xDA,0xE9,0x2C,0x2C,0xE4,0x24,0x5B,0x95,0x4F,0x9E,0x12 } },
-+		{  6 , { 0x45,0x39,0x9F,0x86,0xF8,0x31 } },
-+		{  8 , { 0x09,0x23,0x5A,0xF5,0xB1,0x91,0x9D,0x82 } },
-+		{  9 , { 0x38,0x3D,0xBD,0xED,0x9C,0xC7,0x98,0x22,0x0E } },
-+		{  8 , { 0x08,0xE1,0x7B,0x7B,0xB5,0x9B,0xFA,0xFC } },
-+		{  5 , { 0x4C,0x01,0x2D,0x76,0x1C } },
-+		{  8 , { 0x08,0xFC,0x48,0x5D,0x0A,0x61,0x17,0xD7 } },
-+		{  8 , { 0x08,0x6E,0xB0,0x81,0x3C,0xC9,0x2D,0x77 } },
-+		{  5 , { 0x44,0xDA,0x56,0x75,0xB0 } },
-+		{  8 , { 0x08,0x4F,0xDF,0x0C,0xC0,0x6F,0x32,0xBA } },
-+		{  5 , { 0x4C,0xB5,0x3F,0xB7,0xDC } },
-+		{  8 , { 0x08,0x06,0xF3,0xAD,0x9A,0x4B,0x73,0x1F } },
-+		{  8 , { 0x0C,0x8E,0x0E,0x1C,0x6A,0x87,0x89,0x05 } },
-+		{  9 , { 0x38,0xF4,0x5C,0x97,0x8B,0x78,0x77,0x75,0xAD } },
-+		{  8 , { 0x0C,0xB1,0x6E,0x1E,0x67,0x04,0x01,0x6E } },
-+};
-+
-+#define Si2168B_PATCH16_4_0b9_LINES (sizeof(Si2168B_PATCH16_4_0b9)/(sizeof(firmware_struct)))
-+
-+#endif /* __SI2168B_PRIV_H__ */
---- linux-4.15/drivers/media/dvb-frontends/silg.c.0140~	2018-02-12 11:32:52.766582165 +0100
-+++ linux-4.15/drivers/media/dvb-frontends/silg.c	2018-02-12 11:32:52.766582165 +0100
-@@ -0,0 +1,709 @@
-+/* DVB compliant Linux driver for dual demodulator system with
-+*  a Silicon Labs Si2168B DVB-T/T2/C demodulator
-+*  and a LG 3306A ATSC demodulator
-+*
-+* Copyright (C) 2014 PCTV Systems S.à r.l & Silicon Laboratories Inc.
-+*
-+*/
-+
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/string.h>
-+#include <linux/slab.h>
-+
-+#include "dvb_frontend.h"
-+#include "silg.h"
-+
-+static int debug = 0;
-+module_param_named(debug, debug, int, 0644);
-+
-+#define _SI_ 0 /* index referencing Silicon Labs Si2168B demodulator */
-+#define _LG_ 1 /* index referencing LG3306A demodulator */
-+
-+#define silg_printk(args...) \
-+	do { \
-+		if (debug) \
-+			printk(KERN_DEBUG "silg: " args); \
-+	} while (0)
-+
-+struct silg_priv {
-+	int si_demod_enable:1;
-+	int lg_demod_enable:1;
-+	struct si2168b_config si2168b_cfg;
-+	struct lgdt3306a_config lgdt3306a_cfg;
-+	struct dvb_frontend *demod[2];
-+	int demod_bus_state[2]; /* flag to avoid unnecessary calls */
-+	struct dvb_frontend frontend;
-+	enum fe_delivery_system delivery_system;
-+	u32 dmid; /* demod id used as index */
-+};
-+
-+/* names of the delivery systems for debugging purposes only */
-+static char *delsys_name(enum fe_delivery_system delsys)
-+{
-+	switch (delsys)	{
-+	case SYS_UNDEFINED    : {return (char*)"SYS_UNDEFINED"   ;}
-+	case SYS_DVBC_ANNEX_A : {return (char*)"SYS_DVBC_ANNEX_A";}
-+	case SYS_DVBC_ANNEX_B : {return (char*)"SYS_DVBC_ANNEX_B";}
-+	case SYS_DVBT         : {return (char*)"SYS_DVBT"        ;}
-+	case SYS_DSS          : {return (char*)"SYS_DSS"         ;}
-+	case SYS_DVBS         : {return (char*)"SYS_DVBS"        ;}
-+	case SYS_DVBS2        : {return (char*)"SYS_DVBS2"       ;}
-+	case SYS_DVBH         : {return (char*)"SYS_DVBH"        ;}
-+	case SYS_ISDBT        : {return (char*)"SYS_ISDBT"       ;}
-+	case SYS_ISDBS        : {return (char*)"SYS_ISDBS"       ;}
-+	case SYS_ISDBC        : {return (char*)"SYS_ISDBC"       ;}
-+	case SYS_ATSC         : {return (char*)"SYS_ATSC"        ;}
-+	case SYS_ATSCMH       : {return (char*)"SYS_ATSCMH"      ;}
-+	case SYS_DTMB         : {return (char*)"SYS_DTMB"        ;}
-+	case SYS_CMMB         : {return (char*)"SYS_CMMB"        ;}
-+	case SYS_DAB          : {return (char*)"SYS_DAB"         ;}
-+	case SYS_DVBT2        : {return (char*)"SYS_DVBT2"       ;}
-+	case SYS_TURBO        : {return (char*)"SYS_TURBO"       ;}
-+	case SYS_DVBC_ANNEX_C : {return (char*)"SYS_DVBC_ANNEX_C";}
-+    default:
-+    	break;
-+	}
-+	return (char*)"* UNKNOWN *";
-+}
-+
-+static int silg_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod = priv->demod[priv->dmid];
-+
-+	return demod ? demod->ops.i2c_gate_ctrl(demod, enable) : -ENODEV;
-+}
-+
-+/* control both demodulator ts busses to avoid bus conflicts
-+   modes:
-+   Si2168B ON,        LG3306A tri-state
-+   Si2168B tri-state, LG3306A ON
-+   Si2168B tri-state, LG3306A tri-state
-+ */
-+static int silg_ts_bus_ctrl(struct dvb_frontend* fe, int acquire)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod;
-+	int ret = 0;
-+
-+	silg_printk("%s() acquire=%d\n", __func__, acquire);
-+
-+	if (acquire) {
-+		if (priv->dmid == _SI_) {
-+			/* turn off demod[_LG_] */
-+			if (priv->lg_demod_enable && priv->demod_bus_state[_LG_] != 0 ) {
-+				demod = priv->demod[_LG_];
-+				silg_printk("%s() disabling LG3306A output bus\n", __func__);
-+				ret = demod->ops.ts_bus_ctrl(demod, 0);
-+				if (ret==0) priv->demod_bus_state[_LG_] = 0;
-+			}
-+			/* turn on demod[_SI_] */
-+			if (priv->si_demod_enable && priv->demod_bus_state[_SI_] != 1 ) {
-+				demod = priv->demod[_SI_];
-+				silg_printk("%s() enabling Si2168B output bus\n", __func__);
-+				ret = demod->ops.ts_bus_ctrl(demod, 1);
-+				if (ret==0) priv->demod_bus_state[_SI_] = 1;
-+			}
-+		} else { /* priv->dmid != _SI_ */
-+			/* turn off demod[_SI_] */
-+			if (priv->si_demod_enable && priv->demod_bus_state[_SI_] != 0 ) {
-+				demod = priv->demod[_SI_];
-+				silg_printk("%s() disabling Si2168B output bus\n", __func__);
-+				ret = demod->ops.ts_bus_ctrl(demod, 0);
-+				if (ret==0) priv->demod_bus_state[_SI_] = 0;
-+			}
-+			/* turn on demod[_LG_] */
-+			if (priv->lg_demod_enable && priv->demod_bus_state[_LG_] != 1 ) {
-+				demod = priv->demod[_LG_];
-+				silg_printk("%s() enabling LG3306A output bus\n", __func__);
-+				ret = demod->ops.ts_bus_ctrl(demod, 1);
-+				if (ret==0) priv->demod_bus_state[_LG_] = 1;
-+			}
-+		}
-+	} else { /* !acquire */
-+		silg_printk("%s() setting all demod output buses to tri-state\n", __func__);
-+		if (priv->si_demod_enable && priv->demod_bus_state[_SI_] != 0) {
-+			demod = priv->demod[_SI_];
-+			ret = demod->ops.ts_bus_ctrl(demod, 0);
-+			if (ret==0) priv->demod_bus_state[_SI_] = 0;
-+		}
-+		if (ret == 0 && priv->lg_demod_enable && priv->demod_bus_state[_LG_] != 0) {
-+			demod = priv->demod[_LG_];
-+			ret = demod->ops.ts_bus_ctrl(demod, 0);
-+			if (ret==0) priv->demod_bus_state[_LG_] = 0;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+static int silg_init(struct dvb_frontend *fe)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod;
-+
-+	silg_printk("((((((((((((((((((((((((((((((((((((((((((((((((((((((((((\n");
-+	silg_printk("(((                       %s()                  )))\n", __func__);
-+	silg_printk("))))))))))))))))))))))))))))))))))))))))))))))))))))))))))\n");
-+
-+	if (priv->si_demod_enable) {
-+		demod = priv->demod[_SI_];
-+		if (!demod) {
-+			silg_printk("%s(): Silicon Labs demod configured but not available\n", __func__);
-+			goto err;
-+		}
-+		if (fe->tuner_priv) {
-+			demod->tuner_priv = fe->tuner_priv;
-+			memcpy(&demod->ops.tuner_ops, &fe->ops.tuner_ops, sizeof(struct dvb_tuner_ops));
-+		}
-+		if (demod->ops.init(demod)) {
-+			silg_printk("%s(): initializing Silicon Labs demod failed\n", __func__);
-+			goto err;
-+		}
-+		/* reconfigure the ts bus tri-state control after init */
-+		switch (priv->demod_bus_state[_SI_]) {
-+		case 0: demod->ops.ts_bus_ctrl(demod, 0); break;
-+		case 1: demod->ops.ts_bus_ctrl(demod, 1); break;
-+		}
-+	}
-+	silg_printk("%s(): initializing Silicon Labs demod succeeded\n", __func__);
-+
-+	if (priv->lg_demod_enable) {
-+		demod = priv->demod[_LG_];
-+		if (!demod) {
-+			silg_printk("%s(): LG demod configured but not available\n", __func__);
-+			goto err;
-+		}
-+		if (fe->tuner_priv) {
-+			demod->tuner_priv = fe->tuner_priv;
-+			memcpy(&demod->ops.tuner_ops, &fe->ops.tuner_ops, sizeof(struct dvb_tuner_ops));
-+		}
-+		if (demod->ops.init(demod)) {
-+			silg_printk("%s(): initializing LG demod failed\n", __func__);
-+			goto err;
-+		}
-+		/* reconfigure the ts bus tri-state control after init */
-+		switch (priv->demod_bus_state[_LG_]) {
-+		case 0: demod->ops.ts_bus_ctrl(demod, 0); break;
-+		case 1: demod->ops.ts_bus_ctrl(demod, 1); break;
-+		default:
-+			silg_printk("%s(): lg demod not reconfigured (demod_bus_state=%d)\n", __func__, priv->demod_bus_state[_LG_]);
-+			break;
-+		}
-+	}
-+	silg_printk("%s(): initializing LG demod succeeded\n", __func__);
-+
-+	return 0;
-+
-+err:
-+	printk(KERN_ERR "%s(): failed\n", __func__);
-+	return -ENODEV;
-+}
-+
-+static int silg_read_status(struct dvb_frontend *fe, enum fe_status *status)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod = priv->demod[priv->dmid];
-+
-+	return demod ? demod->ops.read_status(demod, status) : -ENODEV;
-+}
-+
-+static int silg_read_signal_strength(struct dvb_frontend *fe, u16 *rssi)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod = priv->demod[priv->dmid];
-+
-+	return demod ? demod->ops.read_signal_strength(demod, rssi) : -ENODEV;
-+}
-+
-+static int silg_read_ber(struct dvb_frontend *fe, u32 *ber)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod = priv->demod[priv->dmid];
-+
-+	return demod ? demod->ops.read_ber(demod, ber) : -ENODEV;
-+}
-+
-+static int silg_read_snr(struct dvb_frontend *fe, u16 *cnr)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod = priv->demod[priv->dmid];
-+
-+	return demod ? demod->ops.read_snr(demod, cnr) : -ENODEV;
-+}
-+
-+static int silg_read_ucblocks(struct dvb_frontend *fe, u32 *uncorrs)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod = priv->demod[priv->dmid];
-+
-+	return demod ? demod->ops.read_ucblocks(demod, uncorrs) : -ENODEV;
-+}
-+
-+static int select_demod(struct dvb_frontend *fe, enum fe_delivery_system delsys)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	u32    dmid = priv->dmid;
-+
-+	switch (delsys) {
-+	case SYS_ATSC:
-+	case SYS_DVBC_ANNEX_B:
-+		dmid = _LG_; /* LG demod */
-+		break;
-+	case SYS_DVBT:
-+	case SYS_DVBT2:
-+	case SYS_DVBC_ANNEX_A:
-+		dmid = _SI_; /* SiLabs demod */
-+		break;
-+	default:
-+		silg_printk("%s : ERROR: delivery system %s not supported\n", __func__, delsys_name(delsys));
-+		return -EINVAL;
-+	}
-+	silg_printk("%s(): changing delivery system from %s to %s\n", __func__,
-+			delsys_name(priv->delivery_system), delsys_name(delsys));
-+
-+	priv->delivery_system = delsys;
-+
-+	if (dmid != priv->dmid) {
-+		silg_printk("%s(): changing demod from %s to %s\n", __func__,
-+				priv->dmid ? "LG" : "SI", dmid ? "LG" : "SI");
-+		priv->dmid = dmid;
-+	}
-+	return 0;
-+}
-+
-+static int silg_set_frontend(struct dvb_frontend *fe)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod;
-+	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
-+	int ret = 0;
-+
-+	silg_printk("%s(): FE_SET_FRONTEND delsys=%s\n", __func__, delsys_name(p->delivery_system));
-+
-+	if (p->delivery_system != priv->delivery_system) {
-+		ret = select_demod(fe, p->delivery_system);
-+		if (ret) {
-+			return ret;
-+		}
-+	}
-+
-+	demod = priv->demod[priv->dmid];
-+	if (!demod) {
-+		silg_printk("%s(): ERROR: no demod for index=%u\n", __func__, priv->dmid);
-+		return -ENODEV;
-+	}
-+
-+	if (priv->demod_bus_state[priv->dmid] != 1) { /* ts bus of the demod already enabled? */
-+		ret = silg_ts_bus_ctrl(fe, 1); /* enable ts bus of the selected demod */
-+		if (ret) {
-+			return ret;
-+		}
-+	}
-+
-+	memcpy(&demod->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
-+	return demod->ops.set_frontend(demod);
-+}
-+
-+static int silg_get_frontend(struct dvb_frontend *fe, struct dtv_frontend_properties *fe_params)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod = priv->demod[priv->dmid];
-+	int ret = 0;
-+
-+	if (!demod)
-+		return -ENODEV;
-+
-+	ret = demod->ops.get_frontend(demod, fe_params);
-+	if (ret) {
-+		return ret;
-+	}
-+	memcpy(&fe->dtv_property_cache, &demod->dtv_property_cache, sizeof(struct dtv_frontend_properties));
-+	memcpy(fe_params, &demod->dtv_property_cache, sizeof(struct dtv_frontend_properties));
-+	return ret;
-+}
-+
-+static int silg_sleep(struct dvb_frontend *fe)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod;
-+	int ret = 0;
-+
-+	if (priv->si_demod_enable) {
-+		demod = priv->demod[_SI_];
-+		if(!demod){
-+			silg_printk("%s : ERROR: no demod for index=%d\n", __func__, _SI_);
-+			return -ENODEV;
-+		}
-+		ret = demod->ops.sleep(demod);
-+	}
-+	if (priv->lg_demod_enable) {
-+		demod = priv->demod[_LG_];
-+		if(!demod){
-+			silg_printk("%s : ERROR: no demod for index=%d\n", __func__, _LG_);
-+			return -ENODEV;
-+		}
-+		ret |= demod->ops.sleep(demod);
-+	}
-+	return ret;
-+}
-+
-+static void silg_release(struct dvb_frontend *fe)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod;
-+
-+	silg_printk("%s\n", __func__);
-+
-+	if (priv->si_demod_enable) {
-+		demod = priv->demod[_SI_];
-+		if(demod){
-+			demod->ops.release(demod);
-+			symbol_put_addr((void*)demod->ops.release);
-+		} else {
-+			silg_printk("%s : ERROR: no demod for index=%d\n", __func__, _SI_);
-+		}
-+	}
-+	if (priv->lg_demod_enable) {
-+		demod = priv->demod[_LG_];
-+		if(demod){
-+			demod->ops.release(demod);
-+			symbol_put_addr((void*)demod->ops.release);
-+		} else {
-+			silg_printk("%s : ERROR: no demod for index=%d\n", __func__, _LG_);
-+		}
-+	}
-+	if (priv)
-+		kfree(priv);
-+}
-+
-+static int silg_get_tune_settings(struct dvb_frontend *fe,
-+				      struct dvb_frontend_tune_settings
-+					*fe_tune_settings)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod = priv->demod[priv->dmid];
-+
-+	return demod ? demod->ops.get_tune_settings(demod, fe_tune_settings) : -ENODEV;
-+}
-+
-+#ifdef CUSTOM_TUNING_ALGO
-+static int silg_tune(struct dvb_frontend *fe, bool re_tune, unsigned int mode_flags, unsigned int *delay, enum fe_status *status)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod;
-+	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
-+	int ret = 0;
-+
-+	silg_printk("%s(): delsys=%s\n", __func__, delsys_name(p->delivery_system));
-+
-+	if (p->delivery_system != priv->delivery_system) {
-+		ret = select_demod(fe, p->delivery_system);
-+		if (ret) {
-+			return ret;
-+		}
-+	}
-+
-+	demod = priv->demod[priv->dmid];
-+	if(!demod) {
-+		silg_printk("%s : ERROR: no demod for index=%u\n", __func__, priv->dmid);
-+		return -ENODEV;
-+	}
-+
-+	if (priv->demod_bus_state[priv->dmid] != 1) { /* ts bus of the demod already enabled? */
-+		ret = silg_ts_bus_ctrl(fe, 1); /* enable ts bus of the selected demod */
-+		if (ret) {
-+			return ret;
-+		}
-+	}
-+
-+	memcpy(&demod->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
-+	return demod ? demod->ops.tune(demod, re_tune, mode_flags, delay, status) : -ENODEV;
-+}
-+
-+static enum dvbfe_algo silg_get_frontend_algo(struct dvb_frontend *fe)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod = priv->demod[priv->dmid];
-+
-+	return demod ? demod->ops.get_frontend_algo(demod) : -ENODEV;
-+}
-+
-+static enum dvbfe_search silg_search(struct dvb_frontend *fe)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod;
-+	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
-+	int ret = 0;
-+
-+	silg_printk("%s(): delsys=%s\n", __func__, delsys_name(p->delivery_system));
-+
-+	if (p->delivery_system != priv->delivery_system) {
-+		ret = select_demod(fe, p->delivery_system);
-+		if (ret) {
-+			return ret;
-+		}
-+	}
-+
-+	demod = priv->demod[priv->dmid];
-+	if(!demod) {
-+		silg_printk("%s : ERROR: no demod for index=%u\n", __func__, priv->dmid);
-+		return -ENODEV;
-+	}
-+
-+	if (priv->demod_bus_state[priv->dmid] != 1) { /* ts bus of the demod already enabled? */
-+		ret = silg_ts_bus_ctrl(fe, 1); /* enable ts bus of the selected demod */
-+		if (ret) {
-+			return ret;
-+		}
-+	}
-+
-+	memcpy(&demod->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
-+	return demod->ops.search(demod);
-+}
-+#endif /* CUSTOM_TUNING_ALGO */
-+
-+#ifdef FE_READ_STREAM_IDS
-+static int silg_read_stream_ids(struct dvb_frontend *fe, struct dvb_stream_ids* ids)
-+{
-+	struct silg_priv *priv = fe->demodulator_priv;
-+	struct dvb_frontend *demod = priv->demod[priv->dmid];
-+
-+	return demod ? demod->ops.read_stream_ids(demod, ids) : -ENODEV;
-+}
-+#endif /* FE_READ_STREAM_IDS */
-+
-+static const struct dvb_frontend_ops silg_ops = {
-+		.delsys = { SYS_DVBC_ANNEX_B, SYS_ATSC, SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
-+		.info = {
-+				.name = "SILG DVB-T/T2/C ATSC",
-+				.frequency_stepsize = 62500,
-+				.frequency_min = 48000000,
-+				.frequency_max = 870000000,
-+				.symbol_rate_min = 870000,
-+				.symbol_rate_max = 7501000,
-+				.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3
-+				| FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8
-+				| FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_32
-+				| FE_CAN_QAM_64 | FE_CAN_QAM_128 | FE_CAN_QAM_256
-+				| FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO
-+				| FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
-+				| FE_CAN_MULTISTREAM | FE_CAN_2G_MODULATION | FE_CAN_MUTE_TS
-+				| FE_CAN_8VSB
-+		},
-+
-+		.release = silg_release,
-+		/*.release_sec,*/
-+
-+		.init = silg_init,
-+		.sleep = silg_sleep,
-+
-+		/*.write,*/
-+
-+		/* these two are only used for the swzigzag code */
-+		.set_frontend = silg_set_frontend,
-+		.get_tune_settings = silg_get_tune_settings,
-+
-+		.get_frontend = silg_get_frontend,
-+
-+		.read_status = silg_read_status,
-+		.read_ber = silg_read_ber,
-+		.read_signal_strength = silg_read_signal_strength,
-+		.read_snr = silg_read_snr,
-+		.read_ucblocks = silg_read_ucblocks,
-+
-+		.i2c_gate_ctrl = silg_i2c_gate_ctrl,
-+		.ts_bus_ctrl = silg_ts_bus_ctrl,
-+		/* .set_lna, */
-+
-+#ifdef CUSTOM_TUNING_ALGO
-+		/* if this is set, it overrides the default swzigzag */
-+		.tune = silg_tune,
-+		/* get frontend tuning algorithm from the module */
-+		.get_frontend_algo = silg_get_frontend_algo,
-+
-+		/* These callbacks are for devices that implement their own
-+		 * tuning algorithms, rather than a simple swzigzag
-+		 */
-+		.search = silg_search,
-+#endif
-+
-+		/* Allow the frontend to validate incoming properties */
-+		/*.set_property, */
-+		/*.get_property, */
-+#ifdef FE_READ_STREAM_IDS
-+		.read_stream_ids = silg_read_stream_ids,
-+#endif
-+};
-+
-+static int ops_incomplete(struct dvb_frontend *demod)
-+{
-+	int ret = 0;
-+	if (!demod){
-+		silg_printk("ERROR: demod==NULL\n"); return -1;
-+	}
-+	if (!demod->ops.release){
-+		silg_printk("ERROR: ops.release missing\n"); ret = -1;
-+	}
-+	if (!demod->ops.sleep){
-+		silg_printk("ERROR: ops.sleep missing\n"); ret = -1;
-+	}
-+	if (!demod->ops.sleep){
-+		silg_printk("ERROR: ops.sleep missing\n"); ret = -1;
-+	}
-+	if (!demod->ops.set_frontend){
-+		silg_printk("ERROR: ops.set_frontend missing\n"); ret = -1;
-+	}
-+	if (!demod->ops.get_tune_settings){
-+		silg_printk("ERROR: ops.get_tune_settings missing\n"); ret = -1;
-+	}
-+	if (!demod->ops.get_frontend){
-+		silg_printk("ERROR: ops.get_frontend missing\n"); ret = -1;
-+	}
-+	if (!demod->ops.read_status){
-+		silg_printk("ERROR: ops.read_status missing\n"); ret = -1;
-+	}
-+	if (!demod->ops.read_ber){
-+		silg_printk("ERROR: ops.read_ber missing\n"); ret = -1;
-+	}
-+	if (!demod->ops.read_signal_strength){
-+		silg_printk("ERROR: ops.read_signal_strength missing\n"); ret = -1;
-+	}
-+	if (!demod->ops.read_snr){
-+		silg_printk("ERROR: ops.read_snr missing\n"); ret = -1;
-+	}
-+	if (!demod->ops.read_ucblocks){
-+		silg_printk("ERROR: ops.read_ucblocks missing\n"); ret = -1;
-+	}
-+	if (!demod->ops.i2c_gate_ctrl){
-+		silg_printk("ERROR: ops.i2c_gate_ctrl missing\n"); ret = -1;
-+	}
-+	if (!demod->ops.ts_bus_ctrl){
-+		silg_printk("ERROR: ops.ts_bus_ctrl missing\n"); ret = -1;
-+	}
-+
-+#ifdef CUSTOM_TUNING_ALGO
-+	if (!demod->ops.tune){
-+		silg_printk("ERROR: ops.tune missing\n"); ret = -1;
-+	}
-+	if (!demod->ops.get_frontend_algo){
-+		silg_printk("ERROR: ops.get_frontend_algo missing\n"); ret = -1;
-+	}
-+	if (!demod->ops.search){
-+		silg_printk("ERROR: ops.search missing\n"); ret = -1;
-+	}
-+#endif
-+
-+#ifdef FE_READ_STREAM_IDS
-+	if (!demod->ops.read_stream_ids){
-+		silg_printk("ERROR: ops.read_stream_ids missing\n"); ret = -1;
-+	}
-+#endif
-+	return ret;
-+}
-+
-+struct dvb_frontend *silg_attach(const struct silg_config *config, struct i2c_adapter *i2c)
-+{
-+	struct silg_priv *priv = NULL;
-+
-+	silg_printk("%s()\n", __func__);
-+
-+	if (!config) {
-+		silg_printk("ERROR: configuration missing\n");
-+		goto error;
-+	}
-+
-+	if (config->si_demod_enable == 0 && config->lg_demod_enable == 0) {
-+		silg_printk("%s(): no demodulator configured.\n", __func__);
-+		goto error;
-+	}
-+
-+	/* allocate memory */
-+	priv = kzalloc(sizeof(struct silg_priv), GFP_KERNEL);
-+	if (priv == NULL) {
-+		silg_printk("%s(): kzalloc() failed.\n", __func__);
-+		goto error;
-+	}
-+
-+	priv->si_demod_enable = config->si_demod_enable;
-+	if (priv->si_demod_enable) {
-+		priv->si2168b_cfg.demod_address = config->si_i2c_addr;
-+		priv->si2168b_cfg.min_delay_ms = config->min_delay_ms;
-+		priv->si2168b_cfg.ts_bus_mode = config->ts_bus_mode;
-+		priv->si2168b_cfg.ts_clock_mode = config->ts_clock_mode;
-+		priv->si2168b_cfg.clk_gapped_en = config->clk_gapped_en;
-+		priv->si2168b_cfg.ts_par_clk_invert = config->ts_par_clk_invert;
-+		priv->si2168b_cfg.ts_par_clk_shift = config->ts_par_clk_shift;
-+		priv->si2168b_cfg.fef_mode = config->fef_mode;
-+		priv->si2168b_cfg.fef_pin = config->fef_pin;
-+		priv->si2168b_cfg.fef_level = config->fef_level;
-+		priv->si2168b_cfg.indirect_i2c_connection = config->indirect_i2c_connection;
-+		priv->si2168b_cfg.start_ctrl = config->start_ctrl;
-+
-+		priv->demod[_SI_] = dvb_attach(si2168b_attach, &priv->si2168b_cfg, i2c);
-+		if (!priv->demod[_SI_]) {
-+			silg_printk("%s(): ERROR: attaching module si2168b failed.\n", __func__);
-+			kfree(priv);
-+			goto error;
-+		}
-+		if (ops_incomplete(priv->demod[_SI_])) {
-+			silg_printk("%s(): ERROR: interface of si2168b is incomplete.\n", __func__);
-+			kfree(priv);
-+			goto error;
-+		}
-+		priv->demod_bus_state[_SI_] = -1; /* undefined */
-+		pr_info("%s(): attached si2168b\n", __func__);
-+	}
-+
-+	priv->lg_demod_enable = config->si_demod_enable;
-+	if (priv->lg_demod_enable) {
-+		priv->lgdt3306a_cfg.i2c_addr           = config->lg_i2c_addr;
-+		priv->lgdt3306a_cfg.mpeg_mode          = config->mpeg_mode;
-+		priv->lgdt3306a_cfg.tpclk_edge         = config->tpclk_edge;
-+		priv->lgdt3306a_cfg.tpvalid_polarity   = config->tpvalid_polarity;
-+		priv->lgdt3306a_cfg.deny_i2c_rptr      = config->deny_i2c_rptr;
-+		priv->lgdt3306a_cfg.spectral_inversion = config->spectral_inversion;
-+		priv->lgdt3306a_cfg.qam_if_khz         = config->qam_if_khz;
-+		priv->lgdt3306a_cfg.vsb_if_khz         = config->vsb_if_khz;
-+		priv->lgdt3306a_cfg.xtalMHz            = config->xtalMHz;
-+		priv->demod[_LG_] = dvb_attach(lgdt3306a_attach, &priv->lgdt3306a_cfg, i2c);
-+		if (!priv->demod[_LG_]) {
-+			silg_printk("%s(): ERROR: attaching module lgdt3306a failed.\n", __func__);
-+			kfree(priv);
-+			goto error;
-+		}
-+		if (ops_incomplete(priv->demod[_LG_])) {
-+			silg_printk("%s(): ERROR: interface of lgdt3306a is incomplete.\n", __func__);
-+			kfree(priv);
-+			goto error;
-+		}
-+		priv->demod_bus_state[_LG_] = -1; /* undefined */
-+		pr_info("%s(): attached lgdt3306a\n", __func__);
-+	}
-+
-+	priv->dmid = (priv->si_demod_enable) ? _SI_ : _LG_; /* set default demod */
-+	priv->delivery_system = SYS_UNDEFINED;
-+
-+	/* create dvb_frontend */
-+	memcpy(&priv->frontend.ops, &silg_ops, sizeof(struct dvb_frontend_ops));
-+	priv->frontend.demodulator_priv = priv;
-+
-+	return &priv->frontend;
-+
-+error:
-+	return NULL;
-+}
-+EXPORT_SYMBOL(silg_attach);
-+
-+MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
-+
-+MODULE_DESCRIPTION("SILG SiLabs + LG Dual Demodulator Driver");
-+MODULE_AUTHOR("Henning Garbers <hgarbers@pctvsystems.com>");
-+/* MODULE_LICENSE("Proprietary"); */
-+/* GPL discussion for silg not finished. Set to GPL for internal usage only. */
-+/* The module uses GPL functions and is rejected by the kernel build if the */
-+/* license is set to 'Proprietary'. */
-+MODULE_LICENSE("GPL");
-+MODULE_VERSION("1.0");
---- linux-4.15/drivers/media/dvb-frontends/silg.h.0140~	2018-02-12 11:32:52.767582173 +0100
-+++ linux-4.15/drivers/media/dvb-frontends/silg.h	2018-02-12 11:32:52.767582173 +0100
-@@ -0,0 +1,69 @@
-+#ifndef SILG_H
-+#define SILG_H
-+
-+#include <linux/kconfig.h>
-+#include <linux/dvb/frontend.h>
-+#include "dvb_frontend.h"
-+
-+#include "lgdt3306a.h"
-+#include "si2168b.h"
-+
-+#define CUSTOM_TUNING_ALGO
-+
-+struct silg_config {
-+	/* Si2168B demodulator configuration */
-+	int si_demod_enable:1; /* 0:no SiLabs demod 1:SiLabs demod present */
-+
-+	u8 si_i2c_addr; /* the Si2168B demodulator's i2c address */
-+	u8 ts_bus_mode; /*1-serial, 2-parallel.*/
-+	u8 ts_clock_mode; /*0-auto, 1-manual.*/
-+	u8 clk_gapped_en; /*0-disabled, 1-enabled.*/
-+	u8 ts_par_clk_invert; /* 0-not-invert, 1-invert */
-+	u8 ts_par_clk_shift;
-+    u8 fef_mode; /*0-slow normal AGC, 1-freeze pin, 2-slow initial AGC*/
-+	u8 fef_pin; /* FEF pin connected to TER tuner AGC freeze input */
-+	u8 fef_level; /* GPIO state on FEF_pin when used (during FEF periods) */
-+
-+	/* tuner i2c connection               */
-+	/* 0-tuner connected through Si2168B  */
-+	/* 1-tuner is direct accessible       */
-+	u8 indirect_i2c_connection;
-+
-+	int min_delay_ms; /* minimum delay before retuning */
-+	int (*start_ctrl)(struct dvb_frontend *fe);
-+
-+	/* LG3306A demodulator configuration */
-+	int lg_demod_enable:1; /* 0:no LG demod 1:LG demod present */
-+
-+	u8 lg_i2c_addr; /* the LG3306A demodulator's i2c address */
-+
-+	/* user defined IF frequency in KHz */
-+	u16 qam_if_khz;
-+	u16 vsb_if_khz;
-+
-+	/* disable i2c repeater - 0:repeater enabled 1:repeater disabled */
-+	int deny_i2c_rptr:1;
-+
-+	/* spectral inversion - 0:disabled 1:enabled */
-+	int spectral_inversion:1;
-+
-+	enum lgdt3306a_mpeg_mode mpeg_mode;
-+	enum lgdt3306a_tp_clock_edge tpclk_edge;
-+	enum lgdt3306a_tp_valid_polarity tpvalid_polarity;
-+
-+	int  xtalMHz;//demod clock freq in MHz; 24 or 25 supported
-+};
-+
-+#if IS_ENABLED(CONFIG_DVB_SILG)
-+extern struct dvb_frontend *silg_attach(const struct silg_config *config,
-+						struct i2c_adapter *i2c);
-+#else
-+static inline struct dvb_frontend *silg_attach(
-+		const struct silg_config *config, struct i2c_adapter *i2c)
-+{
-+	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
-+	return NULL;
-+}
-+#endif
-+
-+#endif
---- linux-4.15/drivers/media/pci/saa7164/Kconfig.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/pci/saa7164/Kconfig	2018-02-12 11:32:52.767582173 +0100
-@@ -7,7 +7,10 @@ config VIDEO_SAA7164
- 	select VIDEO_TVEEPROM
- 	select DVB_TDA10048 if MEDIA_SUBDRV_AUTOSELECT
- 	select DVB_S5H1411 if MEDIA_SUBDRV_AUTOSELECT
-+	select DVB_LGDT3306A if MEDIA_SUBDRV_AUTOSELECT
-+	select DVB_SI2168B if MEDIA_SUBDRV_AUTOSELECT
- 	select MEDIA_TUNER_TDA18271 if MEDIA_SUBDRV_AUTOSELECT
-+	select MEDIA_TUNER_SILABS_TERCAB if MEDIA_SUBDRV_AUTOSELECT
- 	---help---
- 	  This is a video4linux driver for NXP SAA7164 based
- 	  TV cards.
---- linux-4.15/drivers/media/pci/saa7164/saa7164-api.c.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/pci/saa7164/saa7164-api.c	2018-02-12 11:32:52.767582173 +0100
-@@ -560,12 +560,43 @@ int saa7164_api_set_audio_std(struct saa
- 		printk(KERN_ERR "%s() error, ret = 0x%x\n", __func__, ret);
- 
- 	/* Manually select the appropriate TV audio standard */
--	if (port->encodernorm.id & V4L2_STD_NTSC) {
-+	if ((port->encodernorm.id & V4L2_STD_NTSC_M) == port->encodernorm.id) {
-+		dprintk(DBGLVL_API, " NTSC-M Audio\n");
- 		tvaudio.std = TU_STANDARD_NTSC_M;
- 		tvaudio.country = 1;
--	} else {
-+	} else if ((port->encodernorm.id & V4L2_STD_NTSC_M_JP) == port->encodernorm.id) {
-+		dprintk(DBGLVL_API, " NTSC-M-JP Audio\n");
-+		tvaudio.std = TU_STANDARD_NTSC_M_J;
-+		tvaudio.country = 81;
-+	} else if ((port->encodernorm.id & V4L2_STD_NTSC_443) == port->encodernorm.id) {
-+		dprintk(DBGLVL_API, " NTSC-443 Audio\n");
-+		tvaudio.std = TU_STANDARD_NTSC_433;
-+		tvaudio.country = 1;
-+	} else if ((port->encodernorm.id & V4L2_STD_PAL_BG) == port->encodernorm.id) {
-+		dprintk(DBGLVL_API, " PAL-BG Audio\n");
-+		tvaudio.std = TU_STANDARD_PAL_B;
-+		tvaudio.country = 49;
-+	} else if ((port->encodernorm.id & V4L2_STD_PAL_I) == port->encodernorm.id) {
-+		dprintk(DBGLVL_API, " PAL-I Audio\n");
- 		tvaudio.std = TU_STANDARD_PAL_I;
- 		tvaudio.country = 44;
-+	} else if ((port->encodernorm.id & V4L2_STD_PAL_DK) == port->encodernorm.id) {
-+		dprintk(DBGLVL_API, " PAL-DK Audio\n");
-+		tvaudio.std = TU_STANDARD_PAL_D;
-+		tvaudio.country = 48;
-+	} else if ((port->encodernorm.id & V4L2_STD_SECAM_L) == port->encodernorm.id) {
-+		dprintk(DBGLVL_API, " SECAM-L\n");
-+		tvaudio.std = TU_STANDARD_SECAM_L;
-+		tvaudio.country = 33;
-+	} else if ((port->encodernorm.id & V4L2_STD_SECAM_LC) == port->encodernorm.id) {
-+		dprintk(DBGLVL_API, " SECAM-Lc Audio\n");
-+		tvaudio.std = TU_STANDARD_SECAM_L1;
-+		tvaudio.country = 33;
-+	} else {
-+		/* Unknown standard, set NTSC-M */
-+		tvaudio.std = 1;
-+		tvaudio.country = 1;
-+		dprintk(DBGLVL_API, " Unknown (assuming NTSC-M Audio)\n");
- 	}
- 
- 	ret = saa7164_cmd_send(port->dev, port->tunerunit.unitid, SET_CUR,
-@@ -573,6 +604,7 @@ int saa7164_api_set_audio_std(struct saa
- 	if (ret != SAA_OK)
- 		printk(KERN_ERR "%s() TU_STANDARD_CONTROL error, ret = 0x%x\n",
- 			__func__, ret);
-+
- 	return ret;
- }
- 
-@@ -627,10 +659,14 @@ static int saa7164_api_set_dif(struct sa
- 	dprintk(DBGLVL_API, "%s(nr=%d type=%d val=%x)\n", __func__,
- 		port->nr, port->type, val);
- 
--	if (port->nr == 0)
-+	if (port->nr == SAA7164_PORT_ENC1) {
- 		mas = 0xd0;
--	else
-+	} else if (port->nr == SAA7164_PORT_ENC2) {
- 		mas = 0xe0;
-+	} else {
-+		printk(KERN_ERR "%s() invalid port nr %d\n", __func__, port->nr);
-+		return -EIO;
-+	}
- 
- 	memset(buf, 0, sizeof(buf));
- 
-@@ -676,50 +712,45 @@ static int saa7164_api_set_dif(struct sa
- int saa7164_api_configure_dif(struct saa7164_port *port, u32 std)
- {
- 	struct saa7164_dev *dev = port->dev;
--	u8 agc_disable;
-+	int ret = 0;
-+	u8 agc_disable = 0;
-+	u8 video_standard = 0;
- 
- 	dprintk(DBGLVL_API, "%s(nr=%d, 0x%x)\n", __func__, port->nr, std);
- 
--	if (std & V4L2_STD_NTSC) {
--		dprintk(DBGLVL_API, " NTSC\n");
--		saa7164_api_set_dif(port, 0x00, 0x01); /* Video Standard */
--		agc_disable = 0;
--	} else if (std & V4L2_STD_PAL_I) {
-+	if ((std & V4L2_STD_NTSC_M) == std) {
-+		dprintk(DBGLVL_API, " NTSC-M\n");
-+		video_standard = 0x01;
-+	} else if ((std & V4L2_STD_NTSC_M_JP) == std) {
-+		dprintk(DBGLVL_API, " NTSC-M-JP\n");
-+		video_standard = 0x01;
-+	} else if ((std & V4L2_STD_NTSC_443) == std) {
-+		dprintk(DBGLVL_API, " NTSC-443\n");
-+		video_standard = 0x01;
-+	} else if ((std & V4L2_STD_PAL_BG) == std) {
-+		dprintk(DBGLVL_API, " PAL-BG\n");
-+		video_standard = 0x02;
-+	} else if ((std & V4L2_STD_PAL_I) == std) {
- 		dprintk(DBGLVL_API, " PAL-I\n");
--		saa7164_api_set_dif(port, 0x00, 0x08); /* Video Standard */
--		agc_disable = 0;
--	} else if (std & V4L2_STD_PAL_M) {
--		dprintk(DBGLVL_API, " PAL-M\n");
--		saa7164_api_set_dif(port, 0x00, 0x01); /* Video Standard */
--		agc_disable = 0;
--	} else if (std & V4L2_STD_PAL_N) {
--		dprintk(DBGLVL_API, " PAL-N\n");
--		saa7164_api_set_dif(port, 0x00, 0x01); /* Video Standard */
--		agc_disable = 0;
--	} else if (std & V4L2_STD_PAL_Nc) {
--		dprintk(DBGLVL_API, " PAL-Nc\n");
--		saa7164_api_set_dif(port, 0x00, 0x01); /* Video Standard */
--		agc_disable = 0;
--	} else if (std & V4L2_STD_PAL_B) {
--		dprintk(DBGLVL_API, " PAL-B\n");
--		saa7164_api_set_dif(port, 0x00, 0x02); /* Video Standard */
--		agc_disable = 0;
--	} else if (std & V4L2_STD_PAL_DK) {
-+		video_standard = 0x08;
-+	} else if ((std & V4L2_STD_PAL_DK) == std) {
- 		dprintk(DBGLVL_API, " PAL-DK\n");
--		saa7164_api_set_dif(port, 0x00, 0x10); /* Video Standard */
--		agc_disable = 0;
--	} else if (std & V4L2_STD_SECAM_L) {
-+		video_standard = 0x10;
-+	} else if ((std & V4L2_STD_SECAM_L) == std) {
- 		dprintk(DBGLVL_API, " SECAM-L\n");
--		saa7164_api_set_dif(port, 0x00, 0x20); /* Video Standard */
--		agc_disable = 0;
-+		video_standard = 0x20;
-+	} else if ((std & V4L2_STD_SECAM_LC) == std) {
-+		dprintk(DBGLVL_API, " SECAM-Lc\n");
-+		video_standard = 0x40;
- 	} else {
- 		/* Unknown standard, assume DTV */
- 		dprintk(DBGLVL_API, " Unknown (assuming DTV)\n");
- 		/* Undefinded Video Standard */
--		saa7164_api_set_dif(port, 0x00, 0x80);
-+		video_standard = 0x80;
- 		agc_disable = 1;
- 	}
- 
-+	saa7164_api_set_dif(port, 0x00, video_standard);
- 	saa7164_api_set_dif(port, 0x48, 0xa0); /* AGC Functions 1 */
- 	saa7164_api_set_dif(port, 0xc0, agc_disable); /* AGC Output Disable */
- 	saa7164_api_set_dif(port, 0x7c, 0x04); /* CVBS EQ */
-@@ -728,7 +759,7 @@ int saa7164_api_configure_dif(struct saa
- 	saa7164_api_set_dif(port, 0x04, 0x00); /* Active (again) */
- 	msleep(100);
- 
--	return 0;
-+	return ret;
- }
- 
- /* Ensure the dif is in the correct state for the operating mode
---- linux-4.15/drivers/media/pci/saa7164/saa7164-cards.c.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/pci/saa7164/saa7164-cards.c	2018-02-12 11:32:52.767582173 +0100
-@@ -634,6 +634,52 @@ struct saa7164_board saa7164_boards[] =
- 			.i2c_reg_len	= REGLEN_0bit,
- 		} },
- 	},
-+	[SAA7164_BOARD_HAUPPAUGE_HVR2215] = {
-+		.name		= "Hauppauge WinTV-HVR2215",
-+		.porta		= SAA7164_MPEG_DVB,
-+		.portb		= SAA7164_MPEG_DVB,
-+		.portc		= SAA7164_MPEG_ENCODER,
-+		.portd		= SAA7164_MPEG_ENCODER,
-+		.porte		= SAA7164_MPEG_VBI,
-+		.portf		= SAA7164_MPEG_VBI,
-+		.chiprev	= SAA7164_CHIP_REV3,
-+		.unit		= {{
-+			.id		= 0x28,
-+			.type		= SAA7164_UNIT_EEPROM,
-+			.name		= "4K EEPROM",
-+			.i2c_bus_nr	= SAA7164_I2C_BUS_0,
-+			.i2c_bus_addr	= 0xa0 >> 1,
-+			.i2c_reg_len	= REGLEN_8bit,
-+		}, {
-+			.id		= 0x04,
-+			.type		= SAA7164_UNIT_TUNER,
-+			.name		= "SI2157-1",
-+			.i2c_bus_nr	= SAA7164_I2C_BUS_1,	/* physical i2c bus 0 */
-+			.i2c_bus_addr	= 0xc0 >> 1,
-+			.i2c_reg_len	= 0,
-+		}, {
-+			.id		= 0x05,
-+			.type		= SAA7164_UNIT_DIGITAL_DEMODULATOR,
-+			.name		= "SI2168B-1",
-+			.i2c_bus_nr	= SAA7164_I2C_BUS_1,	/* physical i2c bus 2 */
-+			.i2c_bus_addr	= 0xc8 >> 1,
-+			.i2c_reg_len	= 0,
-+		}, {
-+			.id		= 0x25,
-+			.type		= SAA7164_UNIT_TUNER,
-+			.name		= "SI2157-2",
-+			.i2c_bus_nr	= SAA7164_I2C_BUS_2,	/* physical i2c bus 1 */
-+			.i2c_bus_addr	= 0xc0 >> 1,
-+			.i2c_reg_len	= 0,
-+		}, {
-+			.id		= 0x26,
-+			.type		= SAA7164_UNIT_DIGITAL_DEMODULATOR,
-+			.name		= "SI2168B-2",
-+			.i2c_bus_nr	= SAA7164_I2C_BUS_2,
-+			.i2c_bus_addr	= 0xcc >> 1,
-+			.i2c_reg_len	= 0,
-+		} },
-+	},
- };
- const unsigned int saa7164_bcount = ARRAY_SIZE(saa7164_boards);
- 
-@@ -696,6 +742,10 @@ struct saa7164_subid saa7164_subids[] =
- 		.subvendor = 0x0070,
- 		.subdevice = 0xf120,
- 		.card      = SAA7164_BOARD_HAUPPAUGE_HVR2205,
-+	}, {
-+		.subvendor = 0x0070,
-+		.subdevice = 0xf123,
-+		.card      = SAA7164_BOARD_HAUPPAUGE_HVR2215,
- 	},
- };
- const unsigned int saa7164_idcount = ARRAY_SIZE(saa7164_subids);
-@@ -747,6 +797,7 @@ void saa7164_gpio_setup(struct saa7164_d
- 	case SAA7164_BOARD_HAUPPAUGE_HVR2255proto:
- 	case SAA7164_BOARD_HAUPPAUGE_HVR2255:
- 	case SAA7164_BOARD_HAUPPAUGE_HVR2205:
-+	case SAA7164_BOARD_HAUPPAUGE_HVR2215:
- 		/*
- 		HVR2200 / HVR2250
- 		GPIO 2: s5h1411 / tda10048-1 demod reset
-@@ -856,6 +907,7 @@ void saa7164_card_setup(struct saa7164_d
- 	case SAA7164_BOARD_HAUPPAUGE_HVR2255proto:
- 	case SAA7164_BOARD_HAUPPAUGE_HVR2255:
- 	case SAA7164_BOARD_HAUPPAUGE_HVR2205:
-+	case SAA7164_BOARD_HAUPPAUGE_HVR2215:
- 		hauppauge_eeprom(dev, &eeprom[0]);
- 		break;
- 	}
---- linux-4.15/drivers/media/pci/saa7164/saa7164-core.c.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/pci/saa7164/saa7164-core.c	2018-02-12 11:32:52.767582173 +0100
-@@ -34,6 +34,7 @@
- MODULE_DESCRIPTION("Driver for NXP SAA7164 based TV cards");
- MODULE_AUTHOR("Steven Toth <stoth@kernellabs.com>");
- MODULE_LICENSE("GPL");
-+MODULE_VERSION("2015-07-10");
- 
- /*
-  *  1 Basic
---- linux-4.15/drivers/media/pci/saa7164/saa7164-dvb.c.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/pci/saa7164/saa7164-dvb.c	2018-02-12 11:32:52.768582180 +0100
-@@ -23,6 +23,8 @@
- #include "si2157.h"
- #include "si2168.h"
- #include "lgdt3306a.h"
-+#include "si2168b.h"
-+#include "silabs_tercab.h"
- 
- #define DRIVER_NAME "saa7164"
- 
-@@ -81,6 +83,95 @@ static struct s5h1411_config hauppauge_s
- 	.mpeg_timing   = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
- };
- 
-+static struct lgdt3306a_config hauppauge_lgdt3306a_1_config = {
-+	/* LG3306A demodulator configuration */
-+	.i2c_addr           = 0xB2 >> 1,
-+
-+	/* user defined IF frequency in KHz */
-+	.qam_if_khz         = HVR19x5_QAM_IF, /* needs to match tuner */
-+	.vsb_if_khz         = HVR19x5_VSB_IF, /* needs to match tuner */
-+
-+	/* disable i2c repeater - 0:repeater enabled 1:repeater disabled */
-+	.deny_i2c_rptr      = 1,
-+
-+	/* spectral inversion - 0:disabled 1:enabled */
-+	.spectral_inversion = 1,
-+
-+	.mpeg_mode          = LGDT3306A_MPEG_SERIAL,
-+	.tpclk_edge         = LGDT3306A_TPCLK_RISING_EDGE,
-+	.tpvalid_polarity   = LGDT3306A_TP_VALID_HIGH,
-+
-+	.xtalMHz            = 25, /* demod clock freq in MHz; 24 or 25 supported */
-+};
-+
-+static struct lgdt3306a_config hauppauge_lgdt3306a_2_config = {
-+	/* LG3306A demodulator configuration */
-+	.i2c_addr           = 0x1C >> 1,
-+
-+	/* user defined IF frequency in KHz */
-+	.qam_if_khz         = HVR19x5_QAM_IF, /* needs to match tuner */
-+	.vsb_if_khz         = HVR19x5_VSB_IF, /* needs to match tuner */
-+
-+	/* disable i2c repeater - 0:repeater enabled 1:repeater disabled */
-+	.deny_i2c_rptr      = 1,
-+
-+	/* spectral inversion - 0:disabled 1:enabled */
-+	.spectral_inversion = 1,
-+
-+	.mpeg_mode          = LGDT3306A_MPEG_SERIAL,
-+	.tpclk_edge         = LGDT3306A_TPCLK_RISING_EDGE,
-+	.tpvalid_polarity   = LGDT3306A_TP_VALID_HIGH,
-+
-+	.xtalMHz            = 25, /* demod clock freq in MHz; 24 or 25 supported */
-+};
-+
-+static struct si2168b_config hauppauge_si2168b_1_config = {
-+	/* the demodulator's i2c address */
-+	.demod_address = 0xC8 >> 1,
-+
-+	/* minimum delay before retuning */
-+	.min_delay_ms = 85,
-+	.ts_bus_mode = 1, /*1-serial, 2-parallel.*/
-+	.ts_clock_mode = 1, /*0-auto_fixed, 1-auto_adapt, 2-manual.*/
-+	.clk_gapped_en = 1, /*0-disabled, 1-enabled.*/
-+	.ts_par_clk_invert = 1, /*0-not-invert, 1-invert*/
-+	.ts_par_clk_shift = 1, /*DVB-C QAM256 fix*/
-+	.fef_mode = 1, /* needs to match tuner */
-+	.fef_pin = 3,
-+	.fef_level = 0,
-+	.indirect_i2c_connection = 1, /*Si2157 connected directly*/
-+	.start_ctrl = NULL,
-+};
-+
-+static struct si2168b_config hauppauge_si2168b_2_config = {
-+	/* the demodulator's i2c address */
-+	.demod_address = 0xCC >> 1,
-+
-+	/* minimum delay before retuning */
-+	.min_delay_ms = 85,
-+	.ts_bus_mode = 1, /*1-serial, 2-parallel.*/
-+	.ts_clock_mode = 1, /*0-auto_fixed, 1-auto_adapt, 2-manual.*/
-+	.clk_gapped_en = 1, /*0-disabled, 1-enabled.*/
-+	.ts_par_clk_invert = 1, /*0-not-invert, 1-invert*/
-+	.ts_par_clk_shift = 1, /*DVB-C QAM256 fix*/
-+	.fef_mode = 1, /* needs to match tuner */
-+	.fef_pin = 3,
-+	.fef_level = 0,
-+	.indirect_i2c_connection = 1, /*Si2157 connected directly*/
-+	.start_ctrl = NULL,
-+};
-+
-+static struct silabs_tercab_config hauppauge_si2157_config = {
-+	.tuner_address           = 0xC0 >> 1,      /* address of the tuner for ATSC/DVB-T */
-+	.qam_if_khz              = HVR19x5_QAM_IF, /* needs to match demods qam if */
-+	.vsb_if_khz              = HVR19x5_VSB_IF, /* needs to match demods vsb if */
-+	.tuner_clock_control     = 1, /* 0:always off 1:always on 2:clock managed */
-+	.tuner_agc_control       = 1,
-+	.fef_mode                = 1, /* fef mode slow normal agc */
-+	.crystal_trim_xo_cap     = 8,
-+	.indirect_i2c_connection = 1, /* Si2157 connected directly */
-+};
-+
- static struct lgdt3306a_config hauppauge_hvr2255a_config = {
- 	.i2c_addr               = 0xb2 >> 1,
- 	.qam_if_khz             = 4000,
-@@ -729,6 +820,19 @@ int saa7164_dvb_register(struct saa7164_
- 		}
- 
- 		break;
-+	case SAA7164_BOARD_HAUPPAUGE_HVR2215:
-+		i2c_bus = &dev->i2c_bus[port->nr + 1];
-+
-+		port->dvb.frontend = dvb_attach(si2168b_attach,
-+			(port->nr == 0) ?
-+			&hauppauge_si2168b_1_config : &hauppauge_si2168b_2_config,
-+			&i2c_bus->i2c_adap);
-+
-+		if (port->dvb.frontend != NULL) {
-+			dvb_attach(silabs_tercab_attach, port->dvb.frontend,
-+				&i2c_bus->i2c_adap,	&hauppauge_si2157_config);
-+		}
-+		break;
- 	default:
- 		printk(KERN_ERR "%s: The frontend isn't supported\n",
- 		       dev->name);
---- linux-4.15/drivers/media/pci/saa7164/saa7164-encoder.c.0140~	2018-02-12 11:32:52.013576649 +0100
-+++ linux-4.15/drivers/media/pci/saa7164/saa7164-encoder.c	2018-02-12 11:32:52.768582180 +0100
-@@ -40,6 +40,24 @@ static struct saa7164_tvnorm saa7164_tvn
- 	}, {
- 		.name      = "NTSC-JP",
- 		.id        = V4L2_STD_NTSC_M_JP,
-+	}, {
-+		.name      = "NTSC-443",
-+		.id        = V4L2_STD_NTSC_443,
-+	}, {
-+		.name      = "PAL-BG",
-+		.id        = V4L2_STD_PAL_BG,
-+	}, {
-+		.name      = "PAL-I",
-+		.id        = V4L2_STD_PAL_I,
-+	}, {
-+		.name      = "PAL-DK",
-+		.id        = V4L2_STD_PAL_DK,
-+	}, {
-+		.name      = "SECAM-L",
-+		.id        = V4L2_STD_SECAM_L,
-+	}, {
-+		.name      = "SECAM-Lc",
-+		.id        = V4L2_STD_SECAM_LC,
- 	}
- };
- 
-@@ -215,8 +233,8 @@ int saa7164_s_std(struct saa7164_port *p
- 		return -EINVAL;
- 
- 	port->encodernorm = saa7164_tvnorms[i];
--	port->std = id;
- 
-+	port->std = id;
- 	/* Update the audio decoder while is not running in
- 	 * auto detect mode.
- 	 */
-@@ -1030,6 +1048,7 @@ int saa7164_encoder_register(struct saa7
- 	/* Establish encoder defaults here */
- 	/* Set default TV standard */
- 	port->encodernorm = saa7164_tvnorms[0];
-+	port->std = saa7164_tvnorms[0].id;
- 	port->width = 720;
- 	port->mux_input = 1; /* Composite */
- 	port->video_format = EU_VIDEO_FORMAT_MPEG_2;
---- linux-4.15/drivers/media/pci/saa7164/saa7164-fw.c.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/pci/saa7164/saa7164-fw.c	2018-02-12 11:32:52.768582180 +0100
-@@ -26,6 +26,9 @@
- #define SAA7164_REV3_FIRMWARE		"NXP7164-2010-03-10.1.fw"
- #define SAA7164_REV3_FIRMWARE_SIZE	4019072
- 
-+#define SAA7164_HVR2255_FIRMWARE		"NXP7164-2010-04-01.1.fw"
-+#define SAA7164_HVR2255_FIRMWARE_SIZE	3283792
-+
- struct fw_header {
- 	u32	firmwaresize;
- 	u32	bslsize;
-@@ -214,8 +217,15 @@ int saa7164_downloadfirmware(struct saa7
- 		fwname = SAA7164_REV2_FIRMWARE;
- 		fwlength = SAA7164_REV2_FIRMWARE_SIZE;
- 	} else {
--		fwname = SAA7164_REV3_FIRMWARE;
--		fwlength = SAA7164_REV3_FIRMWARE_SIZE;
-+		if (dev->board == SAA7164_BOARD_HAUPPAUGE_HVR2255
-+				|| dev->board == SAA7164_BOARD_HAUPPAUGE_HVR2205
-+				|| dev->board == SAA7164_BOARD_HAUPPAUGE_HVR2215) {
-+			fwname = SAA7164_HVR2255_FIRMWARE;
-+			fwlength = SAA7164_HVR2255_FIRMWARE_SIZE;
-+		} else {
-+			fwname = SAA7164_REV3_FIRMWARE;
-+			fwlength = SAA7164_REV3_FIRMWARE_SIZE;
-+		}
- 	}
- 
- 	version = saa7164_getcurrentfirmwareversion(dev);
---- linux-4.15/drivers/media/pci/saa7164/saa7164.h.0140~	2018-02-12 11:32:52.013576649 +0100
-+++ linux-4.15/drivers/media/pci/saa7164/saa7164.h	2018-02-12 11:32:52.768582180 +0100
-@@ -82,6 +82,7 @@
- #define SAA7164_BOARD_HAUPPAUGE_HVR2255proto	11
- #define SAA7164_BOARD_HAUPPAUGE_HVR2255		12
- #define SAA7164_BOARD_HAUPPAUGE_HVR2205		13
-+#define SAA7164_BOARD_HAUPPAUGE_HVR2215		14
- 
- #define SAA7164_MAX_UNITS		8
- #define SAA7164_TS_NUMBER_OF_LINES	312
-@@ -113,7 +114,8 @@
- #define DBGLVL_CPU 8192
- 
- #define SAA7164_NORMS \
--	(V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP)
-+	(V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | V4L2_STD_PAL_BG | \
-+	 V4L2_STD_PAL_I | V4L2_STD_PAL_DK | V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)
- 
- /* TV frequency range copied from tuner-core.c */
- #define SAA7164_TV_MIN_FREQ (44U * 16U)
---- linux-4.15/drivers/media/pci/saa7164/saa7164-reg.h.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/pci/saa7164/saa7164-reg.h	2018-02-12 11:32:52.768582180 +0100
-@@ -177,7 +177,24 @@
- #define TU_STANDARD_AUTO_CONTROL	0x01
- #define TU_STANDARD_NONE		0x00
- #define TU_STANDARD_NTSC_M		0x01
-+#define TU_STANDARD_NTSC_M_J	0x02
-+#define TU_STANDARD_NTSC_433	0x03
-+#define TU_STANDARD_PAL_B		0x04
-+#define TU_STANDARD_PAL_D		0x05
-+#define TU_STANDARD_PAL_G		0x06
-+#define TU_STANDARD_PAL_H		0x07
- #define TU_STANDARD_PAL_I		0x08
-+#define TU_STANDARD_PAL_M		0x09
-+#define TU_STANDARD_PAL_N		0x0a
-+#define TU_STANDARD_PAL_60		0x0b
-+#define TU_STANDARD_SECAM_B		0x0c
-+#define TU_STANDARD_SECAM_D		0x0d
-+#define TU_STANDARD_SECAM_G		0x0e
-+#define TU_STANDARD_SECAM_H		0x0f
-+#define TU_STANDARD_SECAM_K		0x10
-+#define TU_STANDARD_SECAM_K1	0x11
-+#define TU_STANDARD_SECAM_L		0x12
-+#define TU_STANDARD_SECAM_L1	0x13
- #define TU_STANDARD_MANUAL		0x00
- #define TU_STANDARD_AUTO		0x01
- 
---- linux-4.15/drivers/media/tuners/Kconfig.0140~	2018-02-12 11:32:52.016576671 +0100
-+++ linux-4.15/drivers/media/tuners/Kconfig	2018-02-12 11:32:52.768582180 +0100
-@@ -255,6 +255,20 @@ config MEDIA_TUNER_SI2157
- 	help
- 	  Silicon Labs Si2157 silicon tuner driver.
- 
-+config MEDIA_TUNER_SILABS_TERCAB
-+	tristate "Silicon Labs terrestrial/cable tuner series"
-+	depends on MEDIA_SUPPORT && I2C
-+	default m if !MEDIA_SUBDRV_AUTOSELECT
-+	help
-+	  Silicon Labs hybrid terrestrial/cable tuner series driver.
-+
-+config MEDIA_TUNER_SILABS_TERCAB
-+	tristate "Silicon Labs terrestrial/cable tuner series"
-+	depends on MEDIA_SUPPORT && I2C
-+	default m if !MEDIA_SUBDRV_AUTOSELECT
-+	help
-+	  Silicon Labs hybrid terrestrial/cable tuner series driver.
-+
- config MEDIA_TUNER_IT913X
- 	tristate "ITE Tech IT913x silicon tuner"
- 	depends on MEDIA_SUPPORT && I2C
---- linux-4.15/drivers/media/tuners/Makefile.0140~	2018-02-12 11:32:52.768582180 +0100
-+++ linux-4.15/drivers/media/tuners/Makefile	2018-02-12 11:35:11.303551576 +0100
-@@ -43,5 +43,6 @@ obj-$(CONFIG_MEDIA_TUNER_MXL301RF) += mx
- obj-$(CONFIG_MEDIA_TUNER_QM1D1C0042) += qm1d1c0042.o
- obj-$(CONFIG_MEDIA_TUNER_M88RS6000T) += m88rs6000t.o
- obj-$(CONFIG_MEDIA_TUNER_TDA18250) += tda18250.o
-+obj-$(CONFIG_MEDIA_TUNER_SILABS_TERCAB) += silabs_tercab.o
- 
- ccflags-y += -I$(srctree)/drivers/media/dvb-frontends
---- linux-4.15/drivers/media/tuners/silabs_tercab.c.0140~	2018-02-12 11:32:52.770582195 +0100
-+++ linux-4.15/drivers/media/tuners/silabs_tercab.c	2018-02-12 11:32:52.770582195 +0100
-@@ -0,0 +1,3452 @@
-+/*
-+ * silabs_tercab.c - Silicon Labs terrestrial/cable hybrid tuner driver
-+ * for the tuners Si2157 and Si2177
-+ *
-+ * (C) Copyright 2014, PCTV Systems S.à r.l
-+ * Henning Garbers <hgarbers@pctvsystems.com>
-+ *
-+ */
-+
-+#include  <linux/delay.h>
-+#include <linux/videodev2.h>
-+#include "tuner-i2c.h"
-+#include "silabs_tercab_priv.h"
-+
-+static int silabs_tercab_debug = 0;
-+module_param_named(debug, silabs_tercab_debug, int, 0644);
-+
-+#ifdef SiTRACES
-+static int silabs_tercab_trace = 0;
-+module_param_named(sitrace, silabs_tercab_trace, int, 0644);
-+#endif
-+
-+static DEFINE_MUTEX(silabs_tercab_list_mutex);
-+static LIST_HEAD(hybrid_tuner_instance_list);
-+
-+/*---------------------------------------------------------------------*/
-+
-+#define DBG_INFO 1
-+
-+__attribute__((format(printf, 4, 5)))
-+int _silabs_tercab_printk(struct silabs_tercab_priv *state, const char *level,
-+		const char *func, const char *fmt, ...)
-+{
-+	struct va_format vaf;
-+	va_list args;
-+	int rtn;
-+
-+	va_start(args, fmt);
-+
-+	vaf.fmt = fmt;
-+	vaf.va = &args;
-+
-+	if (state)
-+		rtn = printk("%s%s: [%d-%04x] %pV",
-+				level, func, i2c_adapter_id(state->i2c_props.adap),
-+				state->i2c_props.addr,
-+				&vaf);
-+	else
-+		rtn = printk("%s%s: %pV", level, func, &vaf);
-+
-+	va_end(args);
-+
-+	return rtn;
-+}
-+
-+#define silabs_tercab_printk(st, lvl, fmt, arg...)			\
-+		_silabs_tercab_printk(st, lvl, __func__, fmt, ##arg)
-+
-+#define si2158_dprintk(st, lvl, fmt, arg...)			\
-+		do {								\
-+			if (silabs_tercab_debug & lvl)				\
-+			silabs_tercab_printk(st, KERN_DEBUG, fmt, ##arg);		\
-+		} while (0)
-+
-+#define silabs_tercab_info(fmt, arg...) silabs_tercab_printk(priv, KERN_INFO, fmt, ##arg)
-+#define silabs_tercab_warn(fmt, arg...) silabs_tercab_printk(priv, KERN_WARNING, fmt, ##arg)
-+#define silabs_tercab_err(fmt, arg...)  silabs_tercab_printk(priv, KERN_ERR, fmt, ##arg)
-+#define silabs_tercab_dbg(fmt, arg...)  si2158_dprintk(priv, DBG_INFO, fmt, ##arg)
-+
-+#define silabs_tercab_fail(ret)							     \
-+		({									     \
-+			int __ret;							     \
-+			__ret = (ret != NO_SILABS_TERCAB_ERROR);						     \
-+			if (__ret)							     \
-+			silabs_tercab_printk(priv, KERN_ERR,				     \
-+					"error %d on line %d\n", ret, __LINE__);	     \
-+					__ret;								     \
-+		})
-+
-+#ifdef SiTRACES
-+#define SiTRACES_BUFFER_LENGTH  100000
-+#define SiTRACES_NAMESIZE           30
-+#define SiTRACES_FUNCTION_NAMESIZE  30
-+
-+#define CUSTOM_PRINTF(args...) \
-+		do { \
-+			if (silabs_tercab_trace) \
-+			printk(KERN_INFO "Silabs tuner: " args); \
-+		} while (0)
-+
-+typedef enum TYPE_OF_OUTPUT {
-+	TRACE_NONE = 0,
-+	TRACE_STDOUT,
-+	TRACE_EXTERN_FILE,
-+	TRACE_MEMORY
-+} TYPE_OF_OUTPUT;
-+
-+static TYPE_OF_OUTPUT trace_output_type;
-+
-+static char trace_timer[50];
-+
-+static u8 trace_init_done         = 0;
-+static u8 trace_suspend           = 0;
-+static u8 trace_skip_info         = 0;
-+static u8 trace_config_lines      = 0;
-+static u8 trace_config_files      = 0;
-+static u8 trace_config_functions  = 0;
-+static u8 trace_config_time       = 0;
-+static int trace_linenumber       = 0;
-+static int trace_count            = 0;
-+
-+static char trace_timer[50];
-+static char trace_elapsed_time[20];
-+static char trace_source_file[100];
-+static char trace_source_function[SiTRACES_FUNCTION_NAMESIZE+1];
-+
-+static void SiTraceFunction(const char *name, int trace_linenumber, const char *func, const char *fmt, ...);
-+#define SiTRACE(...) SiTraceFunction(__FILE__, __LINE__, __FUNCTION__ ,__VA_ARGS__)
-+
-+/************************************************************************************************************************
-+      traceElapsedTime function
-+      Use:        SiTRACES time formatting function.
-+                  It allows the user to know when the trace has been treated.
-+                  It is used to insert the time before the trace when -time 'on'.
-+      Returns:    text containing the execution time in HH:MM:SS.ms format.
-+      Porting:    Not compiled if SiTRACES is not defined in Silabs_L0_ctx.h.
-+************************************************************************************************************************/
-+static char *traceElapsedTime(void)
-+{
-+	unsigned int timeElapsed, ms, sec, min, hours;
-+	timeElapsed = jiffies_to_msecs(jiffies);
-+	ms=timeElapsed%1000;
-+	timeElapsed=timeElapsed/1000;
-+	sec=timeElapsed%60;
-+	timeElapsed=timeElapsed/60;
-+	min=timeElapsed%60;
-+	timeElapsed=timeElapsed/60;
-+	hours=timeElapsed%60;
-+	sprintf(trace_elapsed_time,"%02d:%02d:%02d.%03d ",hours,min,sec,ms);
-+	return trace_elapsed_time;
-+}
-+
-+/************************************************************************************************************************
-+      traceToStdout function
-+      Use:        SiTRACES stdout display function.
-+                  It displays the current trace in the command window.
-+                  It adds file name, line number,function name and time if selected.
-+      Parameter:  trace
-+      Returns:    void
-+************************************************************************************************************************/
-+static void traceToStdout(char* trace)
-+{
-+	if (!trace_skip_info) {
-+		if (trace_config_files    ) { CUSTOM_PRINTF("%-40s ", trace_source_file    ); }
-+		if (trace_config_lines    ) { CUSTOM_PRINTF("%5d "  , trace_linenumber     ); }
-+		if (trace_config_functions) { CUSTOM_PRINTF("%-30s ", trace_source_function); }
-+	}
-+	if (trace_config_time     ) { CUSTOM_PRINTF("%s ",    traceElapsedTime()   ); }
-+	CUSTOM_PRINTF("%s",     trace);
-+}
-+
-+/************************************************************************************************************************
-+  traceToDestination function
-+  Use:        switch the trace in the selected output mode.
-+  Comment:    In verbose mode, the trace is always displayed in stdout.
-+  Parameter:  trace, the trace string
-+  Returns:    void
-+  Porting:    Not compiled if SiTRACES is not defined in Silabs_L0_ctx.h.
-+************************************************************************************************************************/
-+static void  traceToDestination(char* trace)
-+{
-+	int last;
-+	if (trace_suspend) {
-+		return;
-+	}
-+	/* If trace is a single CrLf, do not print the file/line/function info           */
-+	if (strcmp(trace,"\n")==0) {
-+		trace_skip_info = 1;
-+	}
-+	/* If file/line/function info printed, make sure there is a CrLf after each line */
-+	if (trace_config_files + trace_config_lines + trace_config_functions + trace_config_time) {
-+		last = (int)strlen(trace)-1;
-+		if (trace[last] != 0x0a) {
-+			sprintf(trace, "%s\n", trace);
-+		}
-+	}
-+	traceToStdout(trace);
-+	if (strcmp(trace,"\n")==0) {
-+		trace_skip_info = 0;
-+	}
-+	trace_count++;
-+}
-+
-+/************************************************************************************************************************
-+  SiTraceFunction function
-+  Use:        SiTRACES trace formatting function.
-+              It formats the trace message with file name and line number and time if selected
-+              then saves it to the trace output.
-+  Parameter:  name    the file name where the trace is written.
-+  Parameter:  number  the line number where the trace is written.
-+  Parameter:  fmt     string content of trace message. Others arguments are sent thanks to the ellipse.
-+  Returns:    void
-+  Porting:    Not compiled if SiTRACES is not defined in Silabs_L0_ctx.h.
-+************************************************************************************************************************/
-+static void SiTraceFunction(const char *name, int number, const char *func, const char *fmt, ...)
-+{
-+	char        message[850];
-+	const char *pname;
-+	const char *pfunc;
-+	va_list     ap;
-+	/* print the line number in trace_linenumber */
-+	trace_linenumber = number;
-+	pname=name;
-+
-+	/* print the file name in trace_source_file */
-+	if(strlen(pname)>SiTRACES_NAMESIZE) {
-+		pname+=strlen(pname)-SiTRACES_NAMESIZE;
-+	}
-+	strncpy(trace_source_file,pname,SiTRACES_NAMESIZE);
-+
-+	/*print the function name in trace_source_function */
-+	pfunc=func;
-+	sprintf(trace_source_function,"%s","");
-+	if(strlen(pfunc)>SiTRACES_FUNCTION_NAMESIZE) {
-+		pfunc+=(strlen(pfunc)-SiTRACES_FUNCTION_NAMESIZE)+2;
-+		strcpy(trace_source_function,"..");
-+	}
-+	strncat(trace_source_function,pfunc,SiTRACES_FUNCTION_NAMESIZE-2);
-+
-+	va_start(ap, fmt);
-+	vsnprintf(message,900,fmt,ap);
-+	traceToDestination(message);
-+	va_end(ap);
-+	return;
-+}
-+
-+/************************************************************************************************************************
-+  SiTraceDefaultConfiguration function
-+  Use:        SiTRACES initialization function.
-+              It is called on the first call to L0_Init (only once).
-+              It defines the default output and inserts date and time in the default file.
-+  Returns:    void
-+  Porting:    Not compiled if SiTRACES is not defined in Silabs_L0_ctx.h.
-+************************************************************************************************************************/
-+static void SiTraceDefaultConfiguration(void)
-+{
-+	if (trace_init_done) return;
-+	trace_output_type=TRACE_STDOUT;
-+	trace_init_done=1;
-+	sprintf(trace_timer, "time");
-+}
-+
-+/************************************************************************************************************************
-+  silabs_tercab_infos function
-+  Use:        software information function
-+              Used to retrieve information about the compilation
-+  Parameter:  front_end, a pointer to the Si2158_L2_Context context to be initialized
-+  Parameter:  infoString, a text buffer to be filled with teh information. It must be initialized by the caller.
-+  Return:     the length of the information string
-+ ************************************************************************************************************************/
-+static int silabs_tercab_infos(struct silabs_tercab_priv *priv, char *infoString_UNUSED)
-+{
-+	if (infoString_UNUSED == NULL)
-+		return 0;
-+	if (!priv) {
-+		SiTRACE("Si2158 front-end not initialized yet. Call silabs_tercab_sw_init first!\n");
-+		return strlen(infoString_UNUSED);
-+	}
-+
-+	SiTRACE("\n");
-+	SiTRACE("--------------------------------------\n");
-+	SiTRACE("Terrestrial/Cable Tuner Si21%u at 0x%02x\n", priv->tuner.part, priv->tuner.i2c_addr);
-+	SiTRACE("--------------------------------------\n");
-+	return strlen(infoString_UNUSED);
-+}
-+
-+static inline void SiTracesSuspend(void)
-+{
-+	trace_suspend = 1;
-+}
-+static inline void SiTracesResume(void)
-+{
-+	trace_suspend = 0;
-+}
-+#else /* SiTRACES */
-+#define SiTRACE(...)               /* empty */
-+#define SiTracesSuspend()          /* empty */
-+#define SiTracesResume()           /* empty */
-+#endif /* SiTRACES */
-+
-+/************************************************************************************************************************
-+  i2c_read_bytes function
-+
-+  Parameters: iNbBytes, the number of bytes to read.
-+              *pbtDataBuffer, a pointer to a buffer used to store the bytes.
-+  Returns:    the number of bytes read.
-+************************************************************************************************************************/
-+static u16 i2c_read_bytes(struct i2c_adapter *i2c_adap, u8 i2c_addr, u16 iNbBytes, u8 *pucDataBuffer)
-+{
-+	struct silabs_tercab_priv *priv = NULL; /* for debug output only */
-+	u16 nbReadBytes = 0;
-+	struct i2c_msg msg = {
-+			.addr  = i2c_addr,
-+			.flags = I2C_M_RD,
-+			.buf   = pucDataBuffer,
-+			.len   = iNbBytes,
-+	};
-+
-+	if (i2c_adap == NULL) {
-+		silabs_tercab_err("%s(): FATAL ERROR: i2c_adap is undefined!\n", __func__);
-+		return 0;
-+	}
-+
-+	if (i2c_transfer(i2c_adap, &msg, 1) == 1) {
-+		nbReadBytes = iNbBytes;
-+	} else {
-+		silabs_tercab_err("%s(): i2c transfer failed\n", __func__);
-+	}
-+
-+	return nbReadBytes;
-+}
-+
-+/************************************************************************************************************************
-+  i2c_write_bytes function
-+
-+  Parameters: iNbBytes, the number of bytes to write.
-+              *pbtDataBuffer, a pointer to a buffer containing the bytes to write.
-+  Returns:    the number of written bytes.
-+************************************************************************************************************************/
-+static u16 i2c_write_bytes(struct i2c_adapter *i2c_adap, u8 i2c_addr, u16 iNbBytes, u8 *pucDataBuffer)
-+{
-+	u16 nbWrittenBytes = 0;
-+	int write_error = 0;
-+	struct i2c_msg msg = {
-+			.addr  = i2c_addr,
-+			.flags = 0,
-+			.buf   = pucDataBuffer,
-+			.len   = iNbBytes
-+	};
-+	struct silabs_tercab_priv *priv = NULL; /* for debug output only */
-+
-+	if (i2c_adap == NULL) {
-+		silabs_tercab_err("%s(): FATAL ERROR: i2c_adap is undefined!\n", __func__);
-+		return 0;
-+	}
-+
-+	nbWrittenBytes = 0;
-+	write_error    = 0;
-+	if (iNbBytes <= 64) {
-+		if (i2c_transfer(i2c_adap, &msg, 1) == 1) {
-+			nbWrittenBytes = iNbBytes;
-+		} else {
-+			silabs_tercab_err("%s(): i2c transfer failed\n", __func__);
-+			write_error++;
-+		}
-+	} else {
-+		silabs_tercab_err("%s(): numbers of bytes exceeds limit of 64\n", __func__);
-+		write_error++;
-+	}
-+
-+	if (write_error) return 0;
-+	return nbWrittenBytes;
-+}
-+
-+static u8 silabs_tercab_poll_cts(struct i2c_adapter *i2c_adap, u8 i2c_addr)
-+{
-+	u8 rspByteBuffer[1];
-+	struct silabs_tercab_priv *priv = NULL; /* for debug output only */
-+	unsigned int start_time = jiffies_to_msecs(jiffies);
-+
-+	do {
-+		if (i2c_read_bytes(i2c_adap, i2c_addr, 1, rspByteBuffer) != 1) {
-+			silabs_tercab_err("%s() ERROR reading byte 0!\n", __func__);
-+			return ERROR_SILABS_TERCAB_POLLING_CTS;
-+		}
-+		/* return OK if CTS set */
-+		if (rspByteBuffer[0] & 0x80) {
-+			return NO_SILABS_TERCAB_ERROR;
-+		}
-+		msleep(10); /* FGR - pause a bit rather than just spinning on I2C */
-+	} while (jiffies_to_msecs(jiffies) - start_time <1000);/* wait a maximum of 1000ms */
-+
-+	silabs_tercab_err("%s() ERROR CTS Timeout!\n", __func__);
-+	return ERROR_SILABS_TERCAB_CTS_TIMEOUT;
-+}
-+
-+static u8 silabs_tercab_poll_response(struct i2c_adapter *i2c_adap, u8 i2c_addr, u16 nbBytes, u8 *pByteBuffer, silabs_tercab_status *status)
-+{
-+	struct silabs_tercab_priv *priv = NULL; /* for debug output only */
-+	unsigned int start_time = jiffies_to_msecs(jiffies);
-+
-+	do {
-+		if (i2c_read_bytes(i2c_adap, i2c_addr, nbBytes, pByteBuffer) != nbBytes) {
-+			silabs_tercab_err("%s() ERROR reading byte 0!\n", __func__);
-+			return ERROR_SILABS_TERCAB_POLLING_RESPONSE;
-+		}
-+		/* return response err flag if CTS set */
-+		if (pByteBuffer[0] & 0x80)  {
-+			status->tunint = (pByteBuffer[0] >> 0) & 0x01;
-+			status->atvint = (pByteBuffer[0] >> 1) & 0x01;
-+			status->dtvint = (pByteBuffer[0] >> 2) & 0x01;
-+			status->err    = (pByteBuffer[0] >> 6) & 0x01;
-+			status->cts    = (pByteBuffer[0] >> 7) & 0x01;
-+			if (status->err) {
-+				silabs_tercab_info("ERROR flag is on!\n");
-+			}
-+			return (status->err ? ERROR_SILABS_TERCAB_ERR : NO_SILABS_TERCAB_ERROR);
-+		}
-+		msleep(10); /* pause a bit rather than just spinning on I2C */
-+	} while (jiffies_to_msecs(jiffies) - start_time <1000); /* wait a maximum of 1000ms */
-+
-+	silabs_tercab_err("%s() ERROR CTS Timeout!\n", __func__);
-+	return ERROR_SILABS_TERCAB_CTS_TIMEOUT;
-+}
-+
-+/***********************************************************************************************************************
-+  silabs_tercab_check_status function
-+  Use:        Status information function
-+              Used to retrieve the status byte
-+  Returns:    0 if no error
-+  Parameter:  error_code the error code.
-+ ***********************************************************************************************************************/
-+static u8 silabs_tercab_check_status(silabs_tercab_context *ctx)
-+{
-+	u8 rspByteBuffer[1];
-+	return silabs_tercab_poll_response(ctx->i2c_adap, ctx->i2c_addr, 1, rspByteBuffer, &ctx->status);
-+}
-+
-+/***********************************************************************************************************************
-+  silabs_tercab_set_property function
-+  Use:        property set function
-+              Used to call L1_SET_PROPERTY with the property Id and data provided.
-+  Parameter: *ctx     the Si2158 context
-+  Parameter: prop     the property Id
-+  Parameter: data     the property bytes
-+  Returns:    0 if no error, an error code otherwise
-+ ***********************************************************************************************************************/
-+static u8 silabs_tercab_set_property(silabs_tercab_context *ctx, u16 prop, u16 data)
-+{
-+	u8 error_code = 0;
-+	u8 reserved = 0;
-+	u8 cmdByteBuffer[6];
-+	u8 rspByteBuffer[4];
-+
-+	SiTRACE("%s(resv=0x%x prop=0x%x data=0x%x\n", __func__, reserved, prop, data);
-+
-+	cmdByteBuffer[0] = Si2158_SET_PROPERTY_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( reserved & Si2158_SET_PROPERTY_CMD_RESERVED_MASK ) << Si2158_SET_PROPERTY_CMD_RESERVED_LSB);
-+	cmdByteBuffer[2] = (u8) ( ( prop     & Si2158_SET_PROPERTY_CMD_PROP_MASK     ) << Si2158_SET_PROPERTY_CMD_PROP_LSB    );
-+	cmdByteBuffer[3] = (u8) ((( prop     & Si2158_SET_PROPERTY_CMD_PROP_MASK     ) << Si2158_SET_PROPERTY_CMD_PROP_LSB    ) >> 8);
-+	cmdByteBuffer[4] = (u8) ( ( data     & Si2158_SET_PROPERTY_CMD_DATA_MASK     ) << Si2158_SET_PROPERTY_CMD_DATA_LSB    );
-+	cmdByteBuffer[5] = (u8) ((( data     & Si2158_SET_PROPERTY_CMD_DATA_MASK     ) << Si2158_SET_PROPERTY_CMD_DATA_LSB    ) >> 8);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 6, cmdByteBuffer) != 6) {
-+		SiTRACE("Error writing SET_PROPERTY bytes!\n");
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	error_code = silabs_tercab_poll_response(ctx->i2c_adap, ctx->i2c_addr, 4, rspByteBuffer, &ctx->status);
-+	if (error_code) {
-+		SiTRACE("Error polling SET_PROPERTY response\n");
-+		return error_code;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+static u8 silabs_tercab_power_up(struct i2c_adapter *i2c_adap,
-+		u8   i2c_addr,
-+		u8   subcode,
-+		u8   clock_mode,
-+		u8   en_xout,
-+		u8   pd_ldo,
-+		u8   reserved2,
-+		u8   reserved3,
-+		u8   reserved4,
-+		u8   reserved5,
-+		u8   reserved6,
-+		u8   reserved7,
-+		u8   reset,
-+		u8   clock_freq,
-+		u8   reserved8,
-+		u8   func,
-+#ifndef __SI2158__
-+		u8   reserved9,
-+#endif
-+		u8   ctsien,
-+		u8   wake_up,
-+		silabs_tercab_status *status)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[15];
-+	u8 rspByteBuffer[1];
-+	struct silabs_tercab_priv *priv = NULL; /* for debug output only */
-+	//ctx->rsp.power_up.STATUS = ctx->status;
-+
-+	silabs_tercab_info("%s(): clock mode=%u  en_xout=%u\n", __func__, clock_mode, en_xout);
-+
-+	cmdByteBuffer[0]  = Si2158_POWER_UP_CMD;
-+	cmdByteBuffer[1]  = (u8) ( ( subcode    & Si2158_POWER_UP_CMD_SUBCODE_MASK    ) << Si2158_POWER_UP_CMD_SUBCODE_LSB   );
-+	cmdByteBuffer[2]  = (u8) ( ( clock_mode & Si2158_POWER_UP_CMD_CLOCK_MODE_MASK ) << Si2158_POWER_UP_CMD_CLOCK_MODE_LSB|
-+							   ( en_xout    & Si2158_POWER_UP_CMD_EN_XOUT_MASK    ) << Si2158_POWER_UP_CMD_EN_XOUT_LSB   );
-+	cmdByteBuffer[3]  = (u8) ( ( pd_ldo     & Si2158_POWER_UP_CMD_PD_LDO_MASK     ) << Si2158_POWER_UP_CMD_PD_LDO_LSB    );
-+	cmdByteBuffer[4]  = (u8) ( ( reserved2  & Si2158_POWER_UP_CMD_RESERVED2_MASK  ) << Si2158_POWER_UP_CMD_RESERVED2_LSB );
-+	cmdByteBuffer[5]  = (u8) ( ( reserved3  & Si2158_POWER_UP_CMD_RESERVED3_MASK  ) << Si2158_POWER_UP_CMD_RESERVED3_LSB );
-+	cmdByteBuffer[6]  = (u8) ( ( reserved4  & Si2158_POWER_UP_CMD_RESERVED4_MASK  ) << Si2158_POWER_UP_CMD_RESERVED4_LSB );
-+	cmdByteBuffer[7]  = (u8) ( ( reserved5  & Si2158_POWER_UP_CMD_RESERVED5_MASK  ) << Si2158_POWER_UP_CMD_RESERVED5_LSB );
-+	cmdByteBuffer[8]  = (u8) ( ( reserved6  & Si2158_POWER_UP_CMD_RESERVED6_MASK  ) << Si2158_POWER_UP_CMD_RESERVED6_LSB );
-+	cmdByteBuffer[9]  = (u8) ( ( reserved7  & Si2158_POWER_UP_CMD_RESERVED7_MASK  ) << Si2158_POWER_UP_CMD_RESERVED7_LSB );
-+	cmdByteBuffer[10] = (u8) ( ( reset      & Si2158_POWER_UP_CMD_RESET_MASK      ) << Si2158_POWER_UP_CMD_RESET_LSB     );
-+	cmdByteBuffer[11] = (u8) ( ( clock_freq & Si2158_POWER_UP_CMD_CLOCK_FREQ_MASK ) << Si2158_POWER_UP_CMD_CLOCK_FREQ_LSB);
-+	cmdByteBuffer[12] = (u8) ( ( reserved8  & Si2158_POWER_UP_CMD_RESERVED8_MASK  ) << Si2158_POWER_UP_CMD_RESERVED8_LSB );
-+	cmdByteBuffer[13] = (u8) ( ( func       & Si2158_POWER_UP_CMD_FUNC_MASK       ) << Si2158_POWER_UP_CMD_FUNC_LSB      |
-+							   ( reserved9  & Si2157_POWER_UP_CMD_RESERVED9_MASK  ) << Si2157_POWER_UP_CMD_RESERVED9_LSB |
-+							   ( ctsien     & Si2158_POWER_UP_CMD_CTSIEN_MASK     ) << Si2158_POWER_UP_CMD_CTSIEN_LSB    );
-+	cmdByteBuffer[14] = (u8) ( ( wake_up    & Si2158_POWER_UP_CMD_WAKE_UP_MASK    ) << Si2158_POWER_UP_CMD_WAKE_UP_LSB   );
-+
-+	if (i2c_write_bytes(i2c_adap, i2c_addr, 15, cmdByteBuffer) != 15) {
-+		silabs_tercab_err("Error writing POWER_UP bytes!\n");
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	msleep(10);
-+
-+	error_code = silabs_tercab_poll_response(i2c_adap, i2c_addr, 1, rspByteBuffer, status);
-+	if (error_code) {
-+		silabs_tercab_err("Error polling POWER_UP response\n");
-+		return error_code;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2158_PART_INFO COMMAND                        */
-+/*---------------------------------------------------*/
-+static u8 si2158_part_info(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct part_info *part_info)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[1];
-+	u8 rspByteBuffer[13];
-+	silabs_tercab_status status;
-+	struct silabs_tercab_priv *priv = NULL; /* for debug output only */
-+	//ctx->rsp.part_info.STATUS = ctx->status;
-+
-+	silabs_tercab_info("%s()\n", __func__);
-+
-+	cmdByteBuffer[0] = Si2158_PART_INFO_CMD;
-+
-+	if (i2c_write_bytes(i2c_adap, i2c_addr, 1, cmdByteBuffer) != 1) {
-+		silabs_tercab_err("Error writing PART_INFO bytes!\n");
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	error_code = silabs_tercab_poll_response(i2c_adap, i2c_addr, 13, rspByteBuffer, &status);
-+	if (error_code) {
-+		silabs_tercab_err("Error polling PART_INFO response\n");
-+		return error_code;
-+	}
-+
-+	part_info->chiprev  = rspByteBuffer[1] & 0x0f;
-+	part_info->part     = rspByteBuffer[2];
-+	part_info->pmajor   = rspByteBuffer[3];
-+	part_info->pminor   = rspByteBuffer[4];
-+	part_info->pbuild   = rspByteBuffer[5];
-+	part_info->reserved = (( ( rspByteBuffer[6] | (rspByteBuffer[7]  << 8 )) >> 0 ) & 0xffff );
-+	part_info->serial   = (( ( rspByteBuffer[8] | (rspByteBuffer[9]  << 8 ) | (rspByteBuffer[10] << 16 ) | (rspByteBuffer[11] << 24 )) >> 0 ) & 0xffffffff );
-+	part_info->romid    = rspByteBuffer[12];
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/***********************************************************************************************************************
-+  silabs_tercab_error_text function
-+  Use:        Error information function
-+              Used to retrieve a text based on an error code
-+  Returns:    the error text
-+  Parameter:  error_code the error code.
-+  Porting:    Useful for application development for debug purposes.
-+  Porting:    May not be required for the final application, can be removed if not used.
-+ ***********************************************************************************************************************/
-+static char* silabs_tercab_error_text(int error_code)
-+{
-+	switch (error_code) {
-+	case NO_SILABS_TERCAB_ERROR                     : return (char *)"No error";
-+	case ERROR_SILABS_TERCAB_ALLOCATING_CONTEXT     : return (char *)"Error while allocating Si2158 context";
-+	case ERROR_SILABS_TERCAB_PARAMETER_OUT_OF_RANGE : return (char *)"parameter(s) out of range";
-+	case ERROR_SILABS_TERCAB_SENDING_COMMAND        : return (char *)"Error while sending Si2158 command";
-+	case ERROR_SILABS_TERCAB_CTS_TIMEOUT            : return (char *)"CTS timeout";
-+	case ERROR_SILABS_TERCAB_ERR                    : return (char *)"Error (status 'err' bit 1)";
-+	case ERROR_SILABS_TERCAB_POLLING_CTS            : return (char *)"Error while polling CTS";
-+	case ERROR_SILABS_TERCAB_POLLING_RESPONSE       : return (char *)"Error while polling response";
-+	case ERROR_SILABS_TERCAB_LOADING_FIRMWARE       : return (char *)"Error while loading firmware";
-+	case ERROR_SILABS_TERCAB_LOADING_BOOTBLOCK      : return (char *)"Error while loading bootblock";
-+	case ERROR_SILABS_TERCAB_STARTING_FIRMWARE      : return (char *)"Error while starting firmware";
-+	case ERROR_SILABS_TERCAB_SW_RESET               : return (char *)"Error during software reset";
-+	case ERROR_SILABS_TERCAB_INCOMPATIBLE_PART      : return (char *)"Error Incompatible part";
-+#ifndef __SI2158__
-+	case ERROR_Si2157_UNKNOWN_COMMAND               : return (char *)"Error unknown command";
-+	case ERROR_Si2157_UNKNOWN_PROPERTY              : return (char *)"Error unknown property";
-+#endif
-+	/* _specific_error_text_string_insertion_start */
-+	case ERROR_SILABS_TERCAB_TUNINT_TIMEOUT         : return (char *)"Error TUNINT Timeout";
-+	case ERROR_SILABS_TERCAB_xTVINT_TIMEOUT         : return (char *)"Error xTVINT Timeout";
-+	case ERROR_SILABS_TERCAB_CRC_CHECK_ERROR        : return (char *)"Error CRC Check Error";
-+	/* _specific_error_text_string_insertion_point */
-+	default                                         : return (char *)"Unknown silabs_tercab error code";
-+	}
-+}
-+
-+/***********************************************************************************************************************
-+  silabs_tercab_firmware_patch function
-+  Use:        Patch information function
-+              Used to send a number of bytes to the Si2158. Useful to download the firmware.
-+  Returns:    0 if no error
-+  Parameter:  error_code the error code.
-+  Porting:    Useful for application development for debug purposes.
-+  Porting:    May not be required for the final application, can be removed if not used.
-+ ***********************************************************************************************************************/
-+static u8 silabs_tercab_firmware_patch(silabs_tercab_context *ctx, u16 iNbBytes, u8 *pucDataBuffer)
-+{
-+	int res;
-+	u8 rspByteBuffer[1];
-+
-+	SiTRACE("Si2158 Patch %d bytes\n",iNbBytes);
-+
-+	res = i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, iNbBytes, pucDataBuffer);
-+	if (res!=iNbBytes) {
-+		SiTRACE("silabs_tercab_firmware_patch error writing bytes: %s\n", silabs_tercab_error_text(ERROR_SILABS_TERCAB_LOADING_FIRMWARE) );
-+		return ERROR_SILABS_TERCAB_LOADING_FIRMWARE;
-+	}
-+
-+	res = silabs_tercab_poll_response(ctx->i2c_adap, ctx->i2c_addr, 1, rspByteBuffer, &ctx->status);
-+	if (res != NO_SILABS_TERCAB_ERROR) {
-+		SiTRACE("silabs_tercab_firmware_patch error 0x%02x polling response: %s\n", res, silabs_tercab_error_text(res) );
-+		return ERROR_SILABS_TERCAB_POLLING_RESPONSE;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: silabs_tercab_load_firmware_16
-+  DESCRIPTION: Load firmware from firmware_struct array in Si2158_Firmware_x_y_build_z.h file into Si2158
-+              Requires Si2158 to be in bootloader mode after PowerUp
-+  Programming Guide Reference:    Flowchart A.3 (Download FW PATCH flowchart)
-+
-+  Parameter:  Si2158 Context (I2C address)
-+  Parameter:  pointer to firmware_struct array
-+  Parameter:  number of lines in firmware table array (size in bytes / firmware_struct)
-+  Returns:    Si2158/I2C transaction error code, NO_SILABS_TERCAB_ERROR if successful
-+ ************************************************************************************************************************/
-+static int silabs_tercab_load_firmware_16(silabs_tercab_context *ctx, firmware_struct fw_table[], int nbLines)
-+{
-+	int return_code;
-+	int line;
-+	return_code = NO_SILABS_TERCAB_ERROR;
-+
-+	SiTRACE ("silabs_tercab_load_firmware_16 nbLines=%d\n", nbLines);
-+
-+	/* for each line in fw_table */
-+	for (line = 0; line < nbLines; line++)
-+	{
-+		if (fw_table[line].firmware_len > 0)  /* don't download if length is 0 , e.g. dummy firmware */
-+		{
-+			/* send firmware_len bytes (up to 16) to Si2158 */
-+			if ((return_code = silabs_tercab_firmware_patch(ctx, fw_table[line].firmware_len, fw_table[line].firmware_table)) != NO_SILABS_TERCAB_ERROR)
-+			{
-+				SiTRACE("silabs_tercab_load_firmware_16 error 0x%02x patching line %d: %s\n", return_code, line, silabs_tercab_error_text(return_code) );
-+				if (line == 0) {
-+					SiTRACE("The firmware is incompatible with the part!\n");
-+				}
-+				return ERROR_SILABS_TERCAB_LOADING_FIRMWARE;
-+			}
-+			if (line==3) {
-+				SiTracesSuspend();
-+			}
-+		}
-+	}
-+	SiTracesResume();
-+	SiTRACE ("silabs_tercab_load_firmware_16 complete...\n");
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: silabs_tercab_load_firmware
-+  DESCRIPTON: Load firmware from FIRMWARE_TABLE array in Si2158_Firmware_x_y_build_z.h file into Si2158
-+              Requires Si2158 to be in bootloader mode after PowerUp
-+  Programming Guide Reference:    Flowchart A.3 (Download FW PATCH flowchart)
-+
-+  Parameter:  Si2158 Context (I2C address)
-+  Parameter:  pointer to firmware table array
-+  Parameter:  number of lines in firmware table array (size in bytes / BYTES_PER_LINE)
-+  Returns:    Si2158/I2C transaction error code, NO_SILABS_TERCAB_ERROR if successful
-+ ************************************************************************************************************************/
-+static int silabs_tercab_load_firmware(silabs_tercab_context *ctx, u8 fw_table[], int nbLines)
-+{
-+	int return_code;
-+	int line;
-+	return_code = NO_SILABS_TERCAB_ERROR;
-+
-+	SiTRACE ("silabs_tercab_load_firmware nbLines=%d\n", nbLines);
-+
-+	/* for each line in fw_table */
-+	for (line = 0; line < nbLines; line++)
-+	{
-+		/* send Si2158_BYTES_PER_LINE fw bytes to Si2158 */
-+		if ((return_code = silabs_tercab_firmware_patch(ctx, Si2158_BYTES_PER_LINE, fw_table + Si2158_BYTES_PER_LINE*line)) != NO_SILABS_TERCAB_ERROR)
-+		{
-+			SiTRACE("silabs_tercab_load_firmware error 0x%02x patching line %d: %s\n", return_code, line, silabs_tercab_error_text(return_code) );
-+			if (line == 0) {
-+				SiTRACE("The firmware is incompatible with the part!\n");
-+			}
-+			return ERROR_SILABS_TERCAB_LOADING_FIRMWARE;
-+		}
-+		if (line==3) {
-+			SiTracesSuspend();
-+		}
-+	}
-+	SiTracesResume();
-+	SiTRACE ("silabs_tercab_load_firmware complete...\n");
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2158_EXIT_BOOTLOADER COMMAND                  */
-+/*---------------------------------------------------*/
-+static u8 silabs_tercab_exit_bootloader(silabs_tercab_context *ctx,
-+		u8   func,
-+		u8   ctsien)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[1];
-+	//ctx->rsp.exit_bootloader.STATUS = ctx->status;
-+
-+	SiTRACE("%s()\n", __func__);
-+
-+	cmdByteBuffer[0] = Si2158_EXIT_BOOTLOADER_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( func   & Si2158_EXIT_BOOTLOADER_CMD_FUNC_MASK   ) << Si2158_EXIT_BOOTLOADER_CMD_FUNC_LSB  |
-+			( ctsien & Si2158_EXIT_BOOTLOADER_CMD_CTSIEN_MASK ) << Si2158_EXIT_BOOTLOADER_CMD_CTSIEN_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing EXIT_BOOTLOADER bytes!\n");
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	error_code = silabs_tercab_poll_response(ctx->i2c_adap, ctx->i2c_addr, 1, rspByteBuffer, &ctx->status);
-+	if (error_code) {
-+		SiTRACE("Error polling EXIT_BOOTLOADER response\n");
-+		return error_code;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: silabs_tercab_start_firmware
-+  DESCRIPTION: Start Si2158 firmware (put the Si2158 into run mode)
-+  Parameter:   Si2158 Context (I2C address)
-+  Parameter (passed by Reference):   ExitBootloadeer Response Status byte : tunint, atvint, dtvint, err, cts
-+  Returns:     I2C transaction error code, NO_SILABS_TERCAB_ERROR if successful
-+ ************************************************************************************************************************/
-+static int silabs_tercab_start_firmware(silabs_tercab_context *ctx)
-+{
-+	if (silabs_tercab_exit_bootloader(ctx, Si2158_EXIT_BOOTLOADER_CMD_FUNC_TUNER, Si2158_EXIT_BOOTLOADER_CMD_CTSIEN_OFF) != NO_SILABS_TERCAB_ERROR)	{
-+		return ERROR_SILABS_TERCAB_STARTING_FIRMWARE;
-+	}
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: silabs_tercab_power_up_with_patch
-+  DESCRIPTION: Send Si2158 ctx PowerUp Command with PowerUp to bootloader,
-+  Check the Chip rev and part, and ROMID are compared to expected values.
-+  Load the Firmware Patch then Start the Firmware.
-+  Programming Guide Reference:    Flowchart A.2 (POWER_UP with patch flowchart)
-+
-+  Parameter:  pointer to Si2158 Context
-+  Returns:    Si2158/I2C transaction error code, NO_SILABS_TERCAB_ERROR if successful
-+ ************************************************************************************************************************/
-+static int silabs_tercab_power_up_with_patch(struct silabs_tercab_priv *priv)
-+{
-+	silabs_tercab_context *ctx = &priv->tuner;
-+	struct part_info part_info;
-+	int return_code = NO_SILABS_TERCAB_ERROR;
-+	u16 docrc = 0;
-+
-+	/* always wait for CTS prior to POWER_UP command */
-+	if ((return_code = silabs_tercab_poll_cts(ctx->i2c_adap, ctx->i2c_addr)) != NO_SILABS_TERCAB_ERROR) {
-+		SiTRACE ("Si2158_pollForCTS error 0x%02x\n", return_code);
-+		return return_code;
-+	}
-+
-+	if ((return_code = silabs_tercab_power_up(ctx->i2c_adap, ctx->i2c_addr,
-+			Si2158_POWER_UP_CMD_SUBCODE_CODE,
-+			Si2158_POWER_UP_CMD_CLOCK_MODE_XTAL,
-+			Si2158_POWER_UP_CMD_EN_XOUT_EN_XOUT,
-+			Si2158_POWER_UP_CMD_PD_LDO_LDO_POWER_UP,
-+			Si2158_POWER_UP_CMD_RESERVED2_RESERVED,
-+			Si2158_POWER_UP_CMD_RESERVED3_RESERVED,
-+			Si2158_POWER_UP_CMD_RESERVED4_RESERVED,
-+			Si2158_POWER_UP_CMD_RESERVED5_RESERVED,
-+			Si2158_POWER_UP_CMD_RESERVED6_RESERVED,
-+			Si2158_POWER_UP_CMD_RESERVED7_RESERVED,
-+			Si2158_POWER_UP_CMD_RESET_RESET,
-+			Si2158_POWER_UP_CMD_CLOCK_FREQ_CLK_24MHZ,
-+			Si2158_POWER_UP_CMD_RESERVED8_RESERVED,
-+			Si2158_POWER_UP_CMD_FUNC_BOOTLOADER,
-+#ifndef __SI2158__
-+			Si2157_POWER_UP_CMD_RESERVED9_RESERVED,
-+#endif
-+			Si2158_POWER_UP_CMD_CTSIEN_DISABLE,
-+			Si2158_POWER_UP_CMD_WAKE_UP_WAKE_UP,
-+			&ctx->status
-+	)) != NO_SILABS_TERCAB_ERROR) {
-+		/* _power_up_call_insertion_point */
-+
-+		SiTRACE ("silabs_tercab power up error 0x%02x: %s\n", return_code, silabs_tercab_error_text(return_code) );
-+		return return_code;
-+	}
-+
-+	/* Get the Part Info from the chip.   This command is only valid in Bootloader mode */
-+	if ((return_code = si2158_part_info(priv->i2c_props.adap, priv->i2c_props.addr, &part_info)) != NO_SILABS_TERCAB_ERROR) {
-+		SiTRACE ("silabs_tercab part info error 0x%02x: %s\n", return_code, silabs_tercab_error_text(return_code) );
-+		return return_code;
-+	}
-+	ctx->rsp.part_info.chiprev  = part_info.chiprev;
-+	ctx->rsp.part_info.part     = part_info.part;
-+	ctx->rsp.part_info.pmajor   = part_info.pmajor;
-+	ctx->rsp.part_info.pbuild   = part_info.pbuild;
-+	ctx->rsp.part_info.romid    = part_info.romid;
-+	ctx->rsp.part_info.reserved = part_info.reserved;
-+	ctx->rsp.part_info.serial   = part_info.serial;
-+
-+#ifdef SiTRACES
-+	SiTRACE("chiprev %d\n",        ctx->rsp.part_info.chiprev);
-+	SiTRACE("part    Si21%d\n",    ctx->rsp.part_info.part   );
-+	SiTRACE("pmajor  %d\n",        ctx->rsp.part_info.pmajor );
-+	if (ctx->rsp.part_info.pmajor >= 0x30) {
-+		SiTRACE("pmajor '%c'\n",       ctx->rsp.part_info.pmajor );
-+	}
-+	SiTRACE("pminor  %d\n",        ctx->rsp.part_info.pminor );
-+	if (ctx->rsp.part_info.pminor >= 0x30) {
-+		SiTRACE("pminor '%c'\n",       ctx->rsp.part_info.pminor );
-+	}
-+#ifndef __SI2158__
-+	SiTRACE("pbuild %d\n",         ctx->rsp.part_info.pbuild );
-+#endif
-+	SiTRACE("romid %3d/0x%02x\n",  ctx->rsp.part_info.romid,  ctx->rsp.part_info.romid );
-+#endif /* SiTRACES */
-+
-+	if (ctx->rsp.part_info.part == 77) {
-+#ifdef PART_INTEGRITY_CHECKS
-+		/* Check the Chip revision, part and ROMID against expected values and report an error if incompatible */
-+		if (ctx->rsp.part_info.chiprev != ctx->chiprev) {
-+			SiTRACE ("INCOMPATIBLE PART error chiprev %d (expected %d)\n", ctx->rsp.part_info.chiprev, ctx->chiprev);
-+			return_code = ERROR_Si2177_INCOMPATIBLE_PART;
-+		}
-+		/* Part Number is represented as the last 2 digits */
-+		if (ctx->rsp.part_info.part != ctx->part) {
-+			SiTRACE ("INCOMPATIBLE PART error part   %d (expected %d)\n", ctx->rsp.part_info.part, ctx->part);
-+			return_code = ERROR_Si2177_INCOMPATIBLE_PART;
-+		}
-+		/* Part Major Version in ASCII */
-+		if (ctx->rsp.part_info.pmajor != ctx->partMajorVersion) {
-+			SiTRACE ("INCOMPATIBLE PART error pmajor %d (expected %d)\n", ctx->rsp.part_info.pmajor, ctx->partMajorVersion);
-+			return_code = ERROR_Si2177_INCOMPATIBLE_PART;
-+		}
-+		/* Part Minor Version in ASCII */
-+		if (ctx->rsp.part_info.pminor != ctx->partMinorVersion) {
-+			SiTRACE ("INCOMPATIBLE PART error pminor %d (expected %d)\n", ctx->rsp.part_info.pminor, ctx->partMinorVersion);
-+			return_code = ERROR_Si2177_INCOMPATIBLE_PART;
-+		}
-+		/* ROMID in byte representation */
-+		if (ctx->rsp.part_info.romid != ctx->partRomid) {
-+			SiTRACE ("INCOMPATIBLE PART error romid %3d (expected %2d)\n", ctx->rsp.part_info.romid, ctx->partRomid);
-+			return_code = ERROR_Si2177_INCOMPATIBLE_PART;
-+		}
-+		if (return_code != NO_SILABS_TERCAB_ERROR) return return_code;
-+#endif /* PART_INTEGRITY_CHECKS */
-+		if (ctx->rsp.part_info.romid == 0x50) {
-+			if ((return_code = silabs_tercab_load_firmware_16(ctx, Si2177_FW_3_0bx, FIRMWARE_LINES_3_0bx)) != NO_SILABS_TERCAB_ERROR) {
-+				SiTRACE ("silabs_tercab_load_firmware_16 error 0x%02x: %s\n", return_code, silabs_tercab_error_text(return_code) );
-+				return return_code;
-+			}
-+		} else {
-+			SiTRACE ("Invalid ROMID error 0x%02x: ROMID=%02x\n", ERROR_SILABS_TERCAB_INCOMPATIBLE_PART, ctx->rsp.part_info.romid );
-+			return ERROR_SILABS_TERCAB_INCOMPATIBLE_PART;
-+		}
-+	}
-+
-+	docrc = RAM_CRC_2_1b9;//FGR Si2158
-+
-+#ifndef __SI2158__
-+	if (ctx->rsp.part_info.romid == 0x50) {
-+		docrc = 0;//FGR - 21x7 have no CRC command
-+		SiTRACE ("silabs_tercab_load_firmware found Si21x7\n");
-+
-+		/* Only load the Firmware if we are NOT a Si2157-A30 part*/
-+		if ((ctx->rsp.part_info.pmajor == '3') && (ctx->rsp.part_info.pminor == '0') && (ctx->rsp.part_info.pbuild == 5)) {
-+			SiTRACE ("No firmware to download for Si21x7-A30. Loading from NVM only\n" );
-+		} else {
-+			if ((return_code = silabs_tercab_load_firmware_16(ctx, Si2157_FW_3_0b5, FIRMWARE_LINES_3_0b5)) != NO_SILABS_TERCAB_ERROR) {
-+				SiTRACE ("silabs_tercab_load_firmware error 0x%02x: %s\n", return_code, silabs_tercab_error_text(return_code) );
-+				return return_code;
-+			}
-+		}
-+	} else
-+#endif
-+		/* Load the Firmware based on ROMID */
-+		if (ctx->rsp.part_info.romid == 0x32) {
-+			/* Load the Firmware */
-+			if ((return_code = silabs_tercab_load_firmware(ctx, Si2158_FW_0_Eb15, FIRMWARE_LINES_0_Eb15)) != NO_SILABS_TERCAB_ERROR) {
-+				SiTRACE ("silabs_tercab_load_firmware error 0x%02x: %s\n", return_code, silabs_tercab_error_text(return_code) );
-+				return return_code;
-+			}
-+		} else if (ctx->rsp.part_info.romid == 0x33) { /* if Si2158-A20 part load firmware patch (currently a dummy patch , 20bx) */
-+			/* This dummy patch (20bx) will skip the loadFirmware function and boot from NVM only.
-+           When a new patch is available for the Si2158-A20, include the patch file and replace the firmware array and size in the function below */
-+			if ((return_code = silabs_tercab_load_firmware_16(ctx, Si2158_FW_2_1b9, FIRMWARE_LINES_2_1b9)) != NO_SILABS_TERCAB_ERROR) {
-+				SiTRACE ("silabs_tercab_load_firmware_16 error 0x%02x: %s\n", return_code, silabs_tercab_error_text(return_code) );
-+				return return_code;
-+			}
-+		} else {
-+			SiTRACE ("INCOMPATIBLE PART error ROMID 0x%02x\n", ctx->rsp.part_info.romid);
-+			return ERROR_SILABS_TERCAB_INCOMPATIBLE_PART;
-+		}
-+#ifdef RAM_CRC_CHECK
-+	if (docrc) {
-+		/* Check the RAM_CRC value and compare with the expected value */
-+		/* If they match then move on,  otherwise indicate error */
-+		/* This check is bypassed by default to speed boot time. */
-+
-+		if ((return_code = Si2158_L1_RAM_CRC(ctx)) != NO_SILABS_TERCAB_ERROR) {
-+			SiTRACE ("Si2158_L1_RAM_CRC error 0x%02x: %s\n", return_code, silabs_tercab_error_text(return_code) );
-+			return return_code;
-+		}
-+		SiTRACE("RAM CRC = 0x%X\n",ctx->rsp.ram_crc.crc);
-+		if (ctx->rsp.ram_crc.crc != docrc) {
-+			return_code = ERROR_SILABS_TERCAB_CRC_CHECK_ERROR;
-+			SiTRACE ("RAM_CRC (0x%X) does not match expected (0x%X) error 0x%02x: %s\n",ctx->rsp.ram_crc.crc,docrc,return_code, silabs_tercab_error_text(return_code) );
-+			return return_code;
-+		}
-+	}
-+#endif /* RAM_CRC_CHECK */
-+
-+	/* Start the Firmware */
-+	return_code = silabs_tercab_start_firmware(ctx);
-+	if (return_code != NO_SILABS_TERCAB_ERROR) {
-+		SiTRACE("silabs_tercab_start_firmware error 0x%02x: %s\n", return_code, silabs_tercab_error_text(return_code));
-+		return return_code;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2158_CONFIG_PINS COMMAND                      */
-+/*---------------------------------------------------*/
-+static u8 silabs_tercab_config_pins(silabs_tercab_context *ctx,
-+		u8   gpio1_mode,
-+		u8   gpio1_read,
-+		u8   gpio2_mode,
-+		u8   gpio2_read,
-+		u8   reserved1,
-+		u8   reserved2,
-+		u8   reserved3)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[6];
-+	u8 rspByteBuffer[6];
-+
-+	SiTRACE("%s()\n", __func__);
-+
-+	cmdByteBuffer[0] = Si2158_CONFIG_PINS_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( gpio1_mode & Si2158_CONFIG_PINS_CMD_GPIO1_MODE_MASK ) << Si2158_CONFIG_PINS_CMD_GPIO1_MODE_LSB|
-+							  ( gpio1_read & Si2158_CONFIG_PINS_CMD_GPIO1_READ_MASK ) << Si2158_CONFIG_PINS_CMD_GPIO1_READ_LSB);
-+	cmdByteBuffer[2] = (u8) ( ( gpio2_mode & Si2158_CONFIG_PINS_CMD_GPIO2_MODE_MASK ) << Si2158_CONFIG_PINS_CMD_GPIO2_MODE_LSB|
-+							  ( gpio2_read & Si2158_CONFIG_PINS_CMD_GPIO2_READ_MASK ) << Si2158_CONFIG_PINS_CMD_GPIO2_READ_LSB);
-+	cmdByteBuffer[3] = (u8) ( ( reserved1  & Si2158_CONFIG_PINS_CMD_RESERVED1_MASK  ) << Si2158_CONFIG_PINS_CMD_RESERVED1_LSB );
-+	cmdByteBuffer[4] = (u8) ( ( reserved2  & Si2158_CONFIG_PINS_CMD_RESERVED2_MASK  ) << Si2158_CONFIG_PINS_CMD_RESERVED2_LSB );
-+	cmdByteBuffer[5] = (u8) ( ( reserved3  & Si2158_CONFIG_PINS_CMD_RESERVED3_MASK  ) << Si2158_CONFIG_PINS_CMD_RESERVED3_LSB );
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 6, cmdByteBuffer) != 6) {
-+		SiTRACE("Error writing CONFIG_PINS bytes!\n");
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	error_code = silabs_tercab_poll_response(ctx->i2c_adap, ctx->i2c_addr, 6, rspByteBuffer, &ctx->status);
-+	if (error_code) {
-+		SiTRACE("Error polling CONFIG_PINS response\n");
-+		return error_code;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/***********************************************************************************************************************
-+  silabs_tercab_ctx_init function
-+  Use:        software initialisation function
-+              Used to initialize the software context
-+  Returns:    0 if no error
-+  Comments:   It should be called first and once only when starting the application
-+  Parameter:   **ppctx         a pointer to the ctx context to initialize
-+  Parameter:  add            the Si2158 I2C address
-+  Porting:    Allocation errors need to be properly managed.
-+  Porting:    I2C initialization needs to be adapted to use the available I2C functions
-+ ***********************************************************************************************************************/
-+static u8 silabs_tercab_ctx_init(silabs_tercab_context *ctx, u8 addr, struct i2c_adapter *i2c_adap)
-+{
-+	ctx->i2c_addr = addr;
-+	ctx->i2c_adap = i2c_adap;
-+
-+#ifdef SiTRACES
-+	if (!trace_init_done) {
-+		CUSTOM_PRINTF("********** SiTRACES activated *********\n");
-+		CUSTOM_PRINTF("Comment the '#define SiTRACES' line\n");
-+		CUSTOM_PRINTF("in silabs_tercab_priv.h\n");
-+		CUSTOM_PRINTF("to deactivate all traces.\n");
-+		CUSTOM_PRINTF("***************************************\n");
-+		SiTraceDefaultConfiguration();
-+	}
-+#endif /* SiTRACES */
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/************************************************************************************************************************
-+  silabs_tercab_sw_init function
-+  Use:        software initialization function
-+              Used to initialize the Si2158 and tuner structures
-+  Behavior:   This function performs all the steps necessary to initialize the Si2158 tuner instances
-+  Parameter:  front_end, a pointer to the Si2158_L2_Context context to be initialized
-+  Parameter:  tunerAdd, the I2C address of the tuner
-+  Comments:     It MUST be called first and once before using any other function.
-+                It can be used to build a multi-demod/multi-tuner application, if called several times from the upper layer with different pointers and addresses
-+                After execution, all demod and tuner functions are accessible.
-+ ************************************************************************************************************************/
-+static char silabs_tercab_sw_init(struct silabs_tercab_priv *priv
-+		, int tunerAdd
-+		, void *p_context
-+		, struct i2c_adapter *i2c_adap
-+)
-+{
-+#ifdef    SiTRACES
-+	char infoStringBuffer[1000] = { 0 };
-+	char *infoString;
-+	infoString = &(infoStringBuffer[0]);
-+#endif /* SiTRACE */
-+
-+	/* Pointers initialization */
-+	priv->silabs_tercab_init_done = 0;
-+	priv->firmware_started = 0;
-+	/* Calling underlying SW initialization functions */
-+	SiTRACE("silabs_tercab_ctx_init starting...\n");
-+	silabs_tercab_ctx_init(&priv->tuner, tunerAdd, i2c_adap);
-+#ifdef    SiTRACES
-+	if (silabs_tercab_infos(priv, infoString)) {
-+		SiTRACE("%s\n", infoString);
-+	}
-+#endif /* SiTRACE */
-+	SiTRACE("silabs_tercab_ctx_init complete\n");
-+	return 1;
-+}
-+
-+/*****************************************************************************************
-+NAME: silabs_tercab_download_atv_properties
-+ DESCRIPTION: Setup Si2158 ATV properties configuration
-+ This function will download all the ATV configuration properties.
-+ The function SetupATVDefaults() should be called before the first call to this function.
-+ Parameter:  Pointer to Si2158 Context
-+ Returns:    I2C transaction error code, NO_SILABS_TERCAB_ERROR if successful
-+ Programming Guide Reference:    ATV setup flowchart
-+ ******************************************************************************************/
-+static int silabs_tercab_download_atv_properties(silabs_tercab_context *ctx)
-+{
-+	const u16 atv_afc_range_khz                   = 1000; /* (default  1000) */
-+	const u8  atv_af_out_mute                     = Si2177_ATV_AF_OUT_PROP_MUTE_NORMAL; /* Si2177 (default 'NORMAL') */
-+	const u8  atv_af_out_volume                   = 0; /* Si2177 (default     0) */
-+	const u8  atv_agc_speed_if_agc_speed          = Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_AUTO; /* (default 'AUTO') */
-+	const u8  atv_agc_speed_low_rssi_if_agc_speed = Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_158; /* (default '158') */
-+	const s8  atv_agc_speed_low_rssi_thld         = -128; /* (default  -128) */
-+	const u8  atv_artificial_snow_gain            = Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_AUTO; /* (default 'AUTO') */
-+	const s8  atv_artificial_snow_offset          = 0; /* (default     0) */
-+	const u8  atv_artificial_snow_period          = Si2177_ATV_ARTIFICIAL_SNOW_PROP_PERIOD_LONG; /* (default 'LONG') */
-+	const u8  atv_artificial_snow_sound           = Si2177_ATV_ARTIFICIAL_SNOW_PROP_SOUND_MUTE; /* (default 'MUTE') */
-+	const u8  atv_audio_mode_audio_sys            = Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_DEFAULT; /* Si2177 (default 'DEFAULT') */
-+	const u8  atv_audio_mode_chan_bw              = Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_DEFAULT; /* Si2177 (default 'DEFAULT') */
-+	const u8  atv_audio_mode_demod_mode           = Si2177_ATV_AUDIO_MODE_PROP_DEMOD_MODE_SIF; /* Si2177 (default 'SIF') */
-+	const u8  atv_config_if_port_atv_agc_source   = Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_AGC_SOURCE_AGC1_3DB; /* Si2158 (default 'INTERNAL') */
-+	const u8  atv_config_if_port_atv_out_type     = Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_LIF_DIFF_IF1; /* (default 'LIF_DIFF_IF1') */
-+	const u8  atv_cvbs_out_amp                    = 200; /* Si2177 (default   200) */
-+	const u8  atv_cvbs_out_offset                 = 25; /* Si2177 (default    25) */
-+	const u8  atv_cvbs_out_fine_amp               = 100; /* Si2177 (default   100) */
-+	const s8  atv_cvbs_out_fine_offset            = 0; /* Si2177 (default     0) */
-+	const u8  atv_hsync_out_gpio_sel              = Si2177_ATV_HSYNC_OUT_PROP_GPIO_SEL_NONE ; /* (default 'NONE') */
-+	const s8  atv_hsync_out_offset                = 0; /* Si2177 (default     0) */
-+	const u8  atv_hsync_out_width                 = 42; /* Si2177 (default    42) */
-+	const u8  atv_ext_agc_max_10mv                = 200; /* (default   200) */
-+	const u8  atv_ext_agc_min_10mv                = 50; /* (default    50) */
-+	const u8  atv_ien_chlien                      = Si2158_ATV_IEN_PROP_CHLIEN_ENABLE;           /* (default 'ENABLE') */
-+	const u8  atv_ien_pclien                      = Si2158_ATV_IEN_PROP_PCLIEN_DISABLE;          /* (default 'DISABLE') */
-+	const u8  atv_ien_dlien                       = Si2177_ATV_IEN_PROP_DLIEN_DISABLE;           /* (default 'DISABLE') */
-+	const u8  atv_ien_snrlien                     = Si2177_ATV_IEN_PROP_SNRLIEN_DISABLE;         /* (default 'DISABLE') */
-+	const u8  atv_ien_snrhien                     = Si2177_ATV_IEN_PROP_SNRHIEN_DISABLE;         /* (default 'DISABLE') */
-+	const u8  atv_int_sense_chlnegen              = Si2158_ATV_INT_SENSE_PROP_CHLNEGEN_DISABLE;  /* (default 'DISABLE') */
-+	const u8  atv_int_sense_pclnegen              = Si2158_ATV_INT_SENSE_PROP_PCLNEGEN_DISABLE;  /* (default 'DISABLE') */
-+	const u8  atv_int_sense_chlposen              = Si2158_ATV_INT_SENSE_PROP_CHLPOSEN_ENABLE ;  /* (default 'ENABLE') */
-+	const u8  atv_int_sense_pclposen              = Si2158_ATV_INT_SENSE_PROP_PCLPOSEN_ENABLE;   /* (default 'ENABLE') */
-+	const u8  atv_int_sense_dlnegen               = Si2177_ATV_INT_SENSE_PROP_DLNEGEN_DISABLE;   /* (default 'DISABLE') */
-+	const u8  atv_int_sense_snrlnegen             = Si2177_ATV_INT_SENSE_PROP_SNRLNEGEN_DISABLE; /* (default 'DISABLE') */
-+	const u8  atv_int_sense_snrhnegen             = Si2177_ATV_INT_SENSE_PROP_SNRHNEGEN_DISABLE; /* (default 'DISABLE') */
-+	const u8  atv_int_sense_dlposen               = Si2177_ATV_INT_SENSE_PROP_DLPOSEN_ENABLE;    /* (default 'ENABLE') */
-+	const u8  atv_int_sense_snrlposen             = Si2177_ATV_INT_SENSE_PROP_SNRLPOSEN_ENABLE;  /* (default 'ENABLE') */
-+	const u8  atv_int_sense_snrhposen             = Si2177_ATV_INT_SENSE_PROP_SNRHPOSEN_ENABLE;  /* (default 'ENABLE') */
-+	const u16 atv_lif_freq_offset                 = 4000; /* (default  5000) */
-+	const u8  atv_lif_out_amp                     = 100; /* (default   100) */
-+	const u8  atv_lif_out_offset                  = 148; /* (default   148) */
-+	const u8  atv_pga_target_override_enable      = Si2158_ATV_PGA_TARGET_PROP_OVERRIDE_ENABLE_DISABLE; /* (default 'DISABLE') */
-+	const s8  atv_pga_target_pga_target           = 0; /* (default     0) */
-+	const u8  atv_rf_top_atv_rf_top               = Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_AUTO; /* (default 'AUTO') */
-+	const s8  atv_rsq_rssi_threshold_hi           = 0; /* (default     0) */
-+	const s8  atv_rsq_rssi_threshold_lo           = -70; /* (default   -70) */
-+	const u8  atv_rsq_snr_threshold_hi            = 45; /* Si2177 (default    45) */
-+	const u8  atv_rsq_snr_threshold_lo            = 25; /* Si2177 (default    25) */
-+	const u8  atv_sif_out_amp                     = 60; /* Si2177 (default    60) */
-+	const u8  atv_sif_out_offset                  = 135; /* Si2177 (default   135) */
-+	const s8  atv_sound_agc_limit_max_gain        = 84; /* Si2177 (default    84) */
-+	const s8  atv_sound_agc_limit_min_gain        = -84; /* Si2177 (default   -84) */
-+	const u8  atv_sound_agc_speed_other_systems   = 4; /* Si2177 (default     4) */
-+	const u8  atv_sound_agc_speed_system_l        = 5; /* Si2177 (default     5) */
-+	const s8  atv_video_equalizer_slope           = 0; /* Si2177 (default     0) */
-+	const u8  atv_video_mode_color                = Si2158_ATV_VIDEO_MODE_PROP_COLOR_PAL_NTSC; /* (default 'PAL_NTSC') */
-+	const u8  atv_video_mode_invert_spectrum      = Si2158_ATV_VIDEO_MODE_PROP_INVERT_SPECTRUM_INVERTED; /* (default 'INVERTED') */
-+	const u8  atv_video_mode_video_sys            = Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_M; /* (default 'B') */
-+	const u8  atv_vsnr_cap_atv_vsnr_cap           = 0; /* (default     0) */
-+
-+	u16 si2158_atv_afc_range__prop_data;
-+	u16 si2177_atv_af_out__prop_data;
-+	u16 si2158_atv_agc_speed__prop_data;
-+	u16 si2158_atv_agc_speed_low_rssi__prop_data;
-+	u16 si2177_atv_artificial_snow__prop_data;
-+	u16 si2158_atv_artificial_snow__prop_data;
-+	u16 si2177_atv_audio_mode__prop_data;
-+	u16 si2158_atv_config_if_port__prop_data;
-+	u16 si2177_atv_config_if_port__prop_data;
-+	u16 si2158_atv_ext_agc__prop_data;
-+	u16 si2177_atv_cvbs_out__prop_data;
-+	u16 si2177_atv_cvbs_out_fine__prop_data;
-+	u16 si2177_atv_hsync_out__prop_data;
-+	u16 si2158_atv_ien__prop_data;
-+	u16 si2177_atv_ien__prop_data;
-+	u16 si2158_atv_int_sense__prop_data;
-+	u16 si2177_atv_int_sense__prop_data;
-+	u16 si2158_atv_lif_freq__prop_data;
-+	u16 si2158_atv_lif_out__prop_data;
-+	u16 si2158_atv_pga_target__prop_data;
-+	u16 si2158_atv_rf_top__prop_data;
-+	u16 si2158_atv_rsq_rssi_threshold__prop_data;
-+	u16 si2177_atv_rsq_snr_threshold__prop_data;
-+	u16 si2177_atv_sif_out__prop_data;
-+	u16 si2177_atv_sound_agc_limit__prop_data;
-+	u16 si2177_atv_sound_agc_speed__prop_data;
-+	u16 si2177_atv_video_equalizer__prop_data;
-+	u16 si2158_atv_video_mode__prop_data;
-+	u16 si2177_atv_video_mode__prop_data;
-+	u16 si2158_atv_vsnr_cap__prop_data;
-+
-+	SiTRACE("%s()\n", __func__);
-+
-+	si2158_atv_afc_range__prop_data = (atv_afc_range_khz & Si2158_ATV_AFC_RANGE_PROP_RANGE_KHZ_MASK) << Si2158_ATV_AFC_RANGE_PROP_RANGE_KHZ_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_ATV_AFC_RANGE_PROP_CODE, si2158_atv_afc_range__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	if (ctx->part == 77) {
-+		si2177_atv_af_out__prop_data = (atv_af_out_volume & Si2177_ATV_AF_OUT_PROP_VOLUME_MASK) << Si2177_ATV_AF_OUT_PROP_VOLUME_LSB  |
-+			   (atv_af_out_mute   & Si2177_ATV_AF_OUT_PROP_MUTE_MASK  ) << Si2177_ATV_AF_OUT_PROP_MUTE_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2177_ATV_AF_OUT_PROP_CODE, si2177_atv_af_out__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+	}
-+
-+	si2158_atv_agc_speed__prop_data = (atv_agc_speed_if_agc_speed & Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_MASK) << Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_ATV_AGC_SPEED_PROP_CODE, si2158_atv_agc_speed__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_atv_agc_speed_low_rssi__prop_data = (atv_agc_speed_low_rssi_if_agc_speed & Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_MASK) << Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_LSB  |
-+		   (atv_agc_speed_low_rssi_thld         & Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_THLD_MASK        ) << Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_THLD_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_CODE, si2158_atv_agc_speed_low_rssi__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	if (ctx->part == 77) {
-+		si2177_atv_artificial_snow__prop_data = (atv_artificial_snow_gain   & Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_MASK  ) << Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_LSB  |
-+				(atv_artificial_snow_sound  & Si2177_ATV_ARTIFICIAL_SNOW_PROP_SOUND_MASK ) << Si2177_ATV_ARTIFICIAL_SNOW_PROP_SOUND_LSB  |
-+				(atv_artificial_snow_period & Si2177_ATV_ARTIFICIAL_SNOW_PROP_PERIOD_MASK) << Si2177_ATV_ARTIFICIAL_SNOW_PROP_PERIOD_LSB  |
-+				(atv_artificial_snow_offset & Si2158_ATV_ARTIFICIAL_SNOW_PROP_OFFSET_MASK) << Si2158_ATV_ARTIFICIAL_SNOW_PROP_OFFSET_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2158_ATV_ARTIFICIAL_SNOW_PROP_CODE, si2177_atv_artificial_snow__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+	} else {
-+		si2158_atv_artificial_snow__prop_data = (atv_artificial_snow_gain   & Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_MASK  ) << Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_LSB  |
-+			   (atv_artificial_snow_offset & Si2158_ATV_ARTIFICIAL_SNOW_PROP_OFFSET_MASK) << Si2158_ATV_ARTIFICIAL_SNOW_PROP_OFFSET_LSB ;
-+
-+		if (silabs_tercab_set_property(ctx, Si2158_ATV_ARTIFICIAL_SNOW_PROP_CODE, si2158_atv_artificial_snow__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+	}
-+
-+	if (ctx->part == 77) {
-+		si2177_atv_audio_mode__prop_data = (atv_audio_mode_audio_sys  & Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_MASK ) << Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_LSB  |
-+			   (atv_audio_mode_demod_mode & Si2177_ATV_AUDIO_MODE_PROP_DEMOD_MODE_MASK) << Si2177_ATV_AUDIO_MODE_PROP_DEMOD_MODE_LSB  |
-+			   (atv_audio_mode_chan_bw    & Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_MASK   ) << Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2177_ATV_AUDIO_MODE_PROP_CODE, si2177_atv_audio_mode__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+	}
-+
-+	switch (ctx->part) {
-+	case 57:
-+		si2158_atv_config_if_port__prop_data = (atv_config_if_port_atv_out_type   & Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_MASK  ) << Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_LSB  |
-+		       (atv_config_if_port_atv_agc_source & Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_AGC_SOURCE_MASK) << Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_AGC_SOURCE_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2158_ATV_CONFIG_IF_PORT_PROP_CODE, si2158_atv_config_if_port__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+		break;
-+	case 77: /* Si2177 has no ATV_AGC_SOURCE */
-+		si2177_atv_config_if_port__prop_data = (atv_config_if_port_atv_out_type & Si2177_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_MASK) << Si2177_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2158_ATV_CONFIG_IF_PORT_PROP_CODE, si2177_atv_config_if_port__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+		break;
-+	default:
-+		pr_warn("%s(): unsupported tuner model Si21%02u\n", __func__, ctx->part);
-+		break;
-+	}
-+
-+	si2158_atv_ext_agc__prop_data = (atv_ext_agc_min_10mv & Si2158_ATV_EXT_AGC_PROP_MIN_10MV_MASK) << Si2158_ATV_EXT_AGC_PROP_MIN_10MV_LSB  |
-+		   (atv_ext_agc_max_10mv & Si2158_ATV_EXT_AGC_PROP_MAX_10MV_MASK) << Si2158_ATV_EXT_AGC_PROP_MAX_10MV_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_ATV_EXT_AGC_PROP_CODE, si2158_atv_ext_agc__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	if (ctx->part == 77) {
-+		si2177_atv_cvbs_out__prop_data = (atv_cvbs_out_offset & Si2177_ATV_CVBS_OUT_PROP_OFFSET_MASK) << Si2177_ATV_CVBS_OUT_PROP_OFFSET_LSB  |
-+			   (atv_cvbs_out_amp    & Si2177_ATV_CVBS_OUT_PROP_AMP_MASK   ) << Si2177_ATV_CVBS_OUT_PROP_AMP_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2177_ATV_CVBS_OUT_PROP_CODE, si2177_atv_cvbs_out__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+
-+		si2177_atv_cvbs_out_fine__prop_data = (atv_cvbs_out_fine_offset & Si2177_ATV_CVBS_OUT_FINE_PROP_OFFSET_MASK) << Si2177_ATV_CVBS_OUT_FINE_PROP_OFFSET_LSB  |
-+			   (atv_cvbs_out_fine_amp    & Si2177_ATV_CVBS_OUT_FINE_PROP_AMP_MASK   ) << Si2177_ATV_CVBS_OUT_FINE_PROP_AMP_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2177_ATV_CVBS_OUT_FINE_PROP_CODE, si2177_atv_cvbs_out_fine__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+
-+		si2177_atv_hsync_out__prop_data = (atv_hsync_out_gpio_sel & Si2177_ATV_HSYNC_OUT_PROP_GPIO_SEL_MASK) << Si2177_ATV_HSYNC_OUT_PROP_GPIO_SEL_LSB  |
-+	           (atv_hsync_out_width    & Si2177_ATV_HSYNC_OUT_PROP_WIDTH_MASK   ) << Si2177_ATV_HSYNC_OUT_PROP_WIDTH_LSB  |
-+	           (atv_hsync_out_offset   & Si2177_ATV_HSYNC_OUT_PROP_OFFSET_MASK  ) << Si2177_ATV_HSYNC_OUT_PROP_OFFSET_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2177_ATV_HSYNC_OUT_PROP_CODE, si2177_atv_hsync_out__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+	}
-+
-+	switch (ctx->part) {
-+	case 57:
-+		si2158_atv_ien__prop_data = (atv_ien_chlien & Si2158_ATV_IEN_PROP_CHLIEN_MASK) << Si2158_ATV_IEN_PROP_CHLIEN_LSB  |
-+		       (atv_ien_pclien & Si2158_ATV_IEN_PROP_PCLIEN_MASK) << Si2158_ATV_IEN_PROP_PCLIEN_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2158_ATV_IEN_PROP_CODE, si2158_atv_ien__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+		break;
-+	case 77:
-+		si2177_atv_ien__prop_data = (atv_ien_chlien  & Si2158_ATV_IEN_PROP_CHLIEN_MASK ) << Si2158_ATV_IEN_PROP_CHLIEN_LSB  |
-+		       (atv_ien_pclien  & Si2158_ATV_IEN_PROP_PCLIEN_MASK ) << Si2158_ATV_IEN_PROP_PCLIEN_LSB  |
-+		       (atv_ien_dlien   & Si2177_ATV_IEN_PROP_DLIEN_MASK  ) << Si2177_ATV_IEN_PROP_DLIEN_LSB  |
-+		       (atv_ien_snrlien & Si2177_ATV_IEN_PROP_SNRLIEN_MASK) << Si2177_ATV_IEN_PROP_SNRLIEN_LSB  |
-+		       (atv_ien_snrhien & Si2177_ATV_IEN_PROP_SNRHIEN_MASK) << Si2177_ATV_IEN_PROP_SNRHIEN_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2158_ATV_IEN_PROP_CODE, si2177_atv_ien__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+		break;
-+	default:
-+		pr_warn("%s(): unsupported tuner model Si21%02u\n", __func__, ctx->part);
-+		break;
-+	}
-+
-+	switch (ctx->part) {
-+	case 57:
-+		si2158_atv_int_sense__prop_data = (atv_int_sense_chlnegen & Si2158_ATV_INT_SENSE_PROP_CHLNEGEN_MASK) << Si2158_ATV_INT_SENSE_PROP_CHLNEGEN_LSB  |
-+		       (atv_int_sense_pclnegen & Si2158_ATV_INT_SENSE_PROP_PCLNEGEN_MASK) << Si2158_ATV_INT_SENSE_PROP_PCLNEGEN_LSB  |
-+		       (atv_int_sense_chlposen & Si2158_ATV_INT_SENSE_PROP_CHLPOSEN_MASK) << Si2158_ATV_INT_SENSE_PROP_CHLPOSEN_LSB  |
-+		       (atv_int_sense_pclposen & Si2158_ATV_INT_SENSE_PROP_PCLPOSEN_MASK) << Si2158_ATV_INT_SENSE_PROP_PCLPOSEN_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2158_ATV_INT_SENSE_PROP_CODE, si2158_atv_int_sense__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+		break;
-+	case 77:
-+		si2177_atv_int_sense__prop_data = (atv_int_sense_chlnegen  & Si2158_ATV_INT_SENSE_PROP_CHLNEGEN_MASK ) << Si2158_ATV_INT_SENSE_PROP_CHLNEGEN_LSB  |
-+		       (atv_int_sense_pclnegen  & Si2158_ATV_INT_SENSE_PROP_PCLNEGEN_MASK ) << Si2158_ATV_INT_SENSE_PROP_PCLNEGEN_LSB  |
-+		       (atv_int_sense_dlnegen   & Si2177_ATV_INT_SENSE_PROP_DLNEGEN_MASK  ) << Si2177_ATV_INT_SENSE_PROP_DLNEGEN_LSB  |
-+		       (atv_int_sense_snrlnegen & Si2177_ATV_INT_SENSE_PROP_SNRLNEGEN_MASK) << Si2177_ATV_INT_SENSE_PROP_SNRLNEGEN_LSB  |
-+		       (atv_int_sense_snrhnegen & Si2177_ATV_INT_SENSE_PROP_SNRHNEGEN_MASK) << Si2177_ATV_INT_SENSE_PROP_SNRHNEGEN_LSB  |
-+		       (atv_int_sense_chlposen  & Si2158_ATV_INT_SENSE_PROP_CHLPOSEN_MASK ) << Si2158_ATV_INT_SENSE_PROP_CHLPOSEN_LSB  |
-+		       (atv_int_sense_pclposen  & Si2158_ATV_INT_SENSE_PROP_PCLPOSEN_MASK ) << Si2158_ATV_INT_SENSE_PROP_PCLPOSEN_LSB  |
-+		       (atv_int_sense_dlposen   & Si2177_ATV_INT_SENSE_PROP_DLPOSEN_MASK  ) << Si2177_ATV_INT_SENSE_PROP_DLPOSEN_LSB  |
-+		       (atv_int_sense_snrlposen & Si2177_ATV_INT_SENSE_PROP_SNRLPOSEN_MASK) << Si2177_ATV_INT_SENSE_PROP_SNRLPOSEN_LSB  |
-+		       (atv_int_sense_snrhposen & Si2177_ATV_INT_SENSE_PROP_SNRHPOSEN_MASK) << Si2177_ATV_INT_SENSE_PROP_SNRHPOSEN_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2158_ATV_INT_SENSE_PROP_CODE, si2177_atv_int_sense__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+		break;
-+	default:
-+		pr_warn("%s(): unsupported tuner model Si21%02u\n", __func__, ctx->part);
-+		break;
-+	}
-+
-+	si2158_atv_lif_freq__prop_data = (atv_lif_freq_offset & Si2158_ATV_LIF_FREQ_PROP_OFFSET_MASK) << Si2158_ATV_LIF_FREQ_PROP_OFFSET_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_ATV_LIF_FREQ_PROP_CODE, si2158_atv_lif_freq__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_atv_lif_out__prop_data = (atv_lif_out_offset & Si2158_ATV_LIF_OUT_PROP_OFFSET_MASK) << Si2158_ATV_LIF_OUT_PROP_OFFSET_LSB  |
-+		   (atv_lif_out_amp    & Si2158_ATV_LIF_OUT_PROP_AMP_MASK   ) << Si2158_ATV_LIF_OUT_PROP_AMP_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_ATV_LIF_OUT_PROP_CODE, si2158_atv_lif_out__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_atv_pga_target__prop_data = (atv_pga_target_pga_target      & Si2158_ATV_PGA_TARGET_PROP_PGA_TARGET_MASK     ) << Si2158_ATV_PGA_TARGET_PROP_PGA_TARGET_LSB  |
-+		   (atv_pga_target_override_enable & Si2158_ATV_PGA_TARGET_PROP_OVERRIDE_ENABLE_MASK) << Si2158_ATV_PGA_TARGET_PROP_OVERRIDE_ENABLE_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_ATV_PGA_TARGET_PROP_CODE, si2158_atv_pga_target__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_atv_rf_top__prop_data = (atv_rf_top_atv_rf_top & Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_MASK) << Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_ATV_RF_TOP_PROP_CODE, si2158_atv_rf_top__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_atv_rsq_rssi_threshold__prop_data = (atv_rsq_rssi_threshold_lo & Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_LO_MASK) << Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_LO_LSB  |
-+		   (atv_rsq_rssi_threshold_hi & Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_HI_MASK) << Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_HI_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_CODE, si2158_atv_rsq_rssi_threshold__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	if (ctx->part == 77) {
-+		si2177_atv_rsq_snr_threshold__prop_data = (atv_rsq_snr_threshold_lo & Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_LO_MASK) << Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_LO_LSB  |
-+			   (atv_rsq_snr_threshold_hi & Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_HI_MASK) << Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_HI_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_CODE, si2177_atv_rsq_snr_threshold__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+
-+		si2177_atv_sif_out__prop_data = (atv_sif_out_offset & Si2177_ATV_SIF_OUT_PROP_OFFSET_MASK) << Si2177_ATV_SIF_OUT_PROP_OFFSET_LSB  |
-+			   (atv_sif_out_amp    & Si2177_ATV_SIF_OUT_PROP_AMP_MASK   ) << Si2177_ATV_SIF_OUT_PROP_AMP_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2177_ATV_SIF_OUT_PROP_CODE, si2177_atv_sif_out__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+
-+		si2177_atv_sound_agc_limit__prop_data = (atv_sound_agc_limit_max_gain & Si2177_ATV_SOUND_AGC_LIMIT_PROP_MAX_GAIN_MASK) << Si2177_ATV_SOUND_AGC_LIMIT_PROP_MAX_GAIN_LSB  |
-+			   (atv_sound_agc_limit_min_gain & Si2177_ATV_SOUND_AGC_LIMIT_PROP_MIN_GAIN_MASK) << Si2177_ATV_SOUND_AGC_LIMIT_PROP_MIN_GAIN_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2177_ATV_SOUND_AGC_LIMIT_PROP_CODE, si2177_atv_sound_agc_limit__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+
-+		si2177_atv_sound_agc_speed__prop_data = (atv_sound_agc_speed_system_l      & Si2177_ATV_SOUND_AGC_SPEED_PROP_SYSTEM_L_MASK     ) << Si2177_ATV_SOUND_AGC_SPEED_PROP_SYSTEM_L_LSB  |
-+			   (atv_sound_agc_speed_other_systems & Si2177_ATV_SOUND_AGC_SPEED_PROP_OTHER_SYSTEMS_MASK) << Si2177_ATV_SOUND_AGC_SPEED_PROP_OTHER_SYSTEMS_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2177_ATV_SOUND_AGC_SPEED_PROP_CODE, si2177_atv_sound_agc_speed__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+
-+		si2177_atv_video_equalizer__prop_data = (atv_video_equalizer_slope & Si2177_ATV_VIDEO_EQUALIZER_PROP_SLOPE_MASK) << Si2177_ATV_VIDEO_EQUALIZER_PROP_SLOPE_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2177_ATV_VIDEO_EQUALIZER_PROP_CODE, si2177_atv_video_equalizer__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+	}
-+
-+	switch (ctx->part) {
-+	case 57:
-+		si2158_atv_video_mode__prop_data = (atv_video_mode_video_sys       & Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_MASK      ) << Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_LSB  |
-+		       (atv_video_mode_color           & Si2158_ATV_VIDEO_MODE_PROP_COLOR_MASK          ) << Si2158_ATV_VIDEO_MODE_PROP_COLOR_LSB  |
-+		       (atv_video_mode_invert_spectrum & Si2158_ATV_VIDEO_MODE_PROP_INVERT_SPECTRUM_MASK) << Si2158_ATV_VIDEO_MODE_PROP_INVERT_SPECTRUM_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2158_ATV_VIDEO_MODE_PROP_CODE, si2158_atv_video_mode__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+		break;
-+	case 77:
-+		si2177_atv_video_mode__prop_data = (atv_video_mode_video_sys       & Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_MASK    ) << Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_LSB  |
-+		       (atv_video_mode_color           & Si2158_ATV_VIDEO_MODE_PROP_COLOR_MASK        ) << Si2158_ATV_VIDEO_MODE_PROP_COLOR_LSB  |
-+		       (atv_video_mode_invert_spectrum & Si2177_ATV_VIDEO_MODE_PROP_INVERT_SIGNAL_MASK) << Si2177_ATV_VIDEO_MODE_PROP_INVERT_SIGNAL_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2158_ATV_VIDEO_MODE_PROP_CODE, si2177_atv_video_mode__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+		break;
-+	default:
-+		pr_warn("%s(): unsupported tuner model Si21%02u\n", __func__, ctx->part);
-+		break;
-+	}
-+
-+	si2158_atv_vsnr_cap__prop_data = (atv_vsnr_cap_atv_vsnr_cap & Si2158_ATV_VSNR_CAP_PROP_ATV_VSNR_CAP_MASK) << Si2158_ATV_VSNR_CAP_PROP_ATV_VSNR_CAP_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_ATV_VSNR_CAP_PROP_CODE, si2158_atv_vsnr_cap__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/*****************************************************************************************
-+NAME: silabs_tercap_download_common_properties
-+ DESCRIPTION: Setup Si2158 COMMON properties configuration
-+ This function will download all the COMMON configuration properties.
-+ The function SetupCOMMONDefaults() should be called before the first call to this function.
-+ Parameter:  Pointer to Si2158 Context
-+ Returns:    I2C transaction error code, NO_SILABS_TERCAB_ERROR if successful
-+ Programming Guide Reference:    COMMON setup flowchart
-+ ******************************************************************************************/
-+static int silabs_tercap_download_common_properties(silabs_tercab_context *ctx)
-+{
-+	const u8 crystal_trim_xo_cap = Si2158_CRYSTAL_TRIM_PROP_XO_CAP_6P7PF ; /* (default '8') */
-+	const u8 master_ien_atvien   = Si2158_MASTER_IEN_PROP_ATVIEN_OFF ; /* (default 'OFF') */
-+	const u8 master_ien_ctsien   = Si2158_MASTER_IEN_PROP_CTSIEN_OFF ; /* (default 'OFF') */
-+	const u8 master_ien_dtvien   = Si2158_MASTER_IEN_PROP_DTVIEN_OFF ; /* (default 'OFF') */
-+	const u8 master_ien_errien   = Si2158_MASTER_IEN_PROP_ERRIEN_OFF ; /* (default 'OFF') */
-+	const u8 master_ien_tunien   = Si2158_MASTER_IEN_PROP_TUNIEN_OFF ; /* (default 'OFF') */
-+	const u8 xout_amp            = Si2158_XOUT_PROP_AMP_HIGH ; /* (default 'HIGH') */
-+
-+	u16 si2158_crystal_trim_prop_data;
-+	u16 si2158_master_ien_prop_data;
-+	u16 si2158_xout_prop_data;
-+
-+	SiTRACE("%s()\n", __func__);
-+
-+	si2158_crystal_trim_prop_data = (crystal_trim_xo_cap & Si2158_CRYSTAL_TRIM_PROP_XO_CAP_MASK) << Si2158_CRYSTAL_TRIM_PROP_XO_CAP_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_CRYSTAL_TRIM_PROP_CODE, si2158_crystal_trim_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_master_ien_prop_data = (master_ien_tunien & Si2158_MASTER_IEN_PROP_TUNIEN_MASK) << Si2158_MASTER_IEN_PROP_TUNIEN_LSB  |
-+		   (master_ien_atvien & Si2158_MASTER_IEN_PROP_ATVIEN_MASK) << Si2158_MASTER_IEN_PROP_ATVIEN_LSB  |
-+		   (master_ien_dtvien & Si2158_MASTER_IEN_PROP_DTVIEN_MASK) << Si2158_MASTER_IEN_PROP_DTVIEN_LSB  |
-+		   (master_ien_errien & Si2158_MASTER_IEN_PROP_ERRIEN_MASK) << Si2158_MASTER_IEN_PROP_ERRIEN_LSB  |
-+		   (master_ien_ctsien & Si2158_MASTER_IEN_PROP_CTSIEN_MASK) << Si2158_MASTER_IEN_PROP_CTSIEN_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_MASTER_IEN_PROP_CODE, si2158_master_ien_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_xout_prop_data = (xout_amp & Si2158_XOUT_PROP_AMP_MASK) << Si2158_XOUT_PROP_AMP_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_XOUT_PROP_CODE, si2158_xout_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/*****************************************************************************************
-+NAME: silabs_tercap_download_dtv_properties
-+ DESCRIPTION: Setup Si2158 DTV properties configuration
-+ This function will download all the DTV configuration properties.
-+ The function SetupDTVDefaults() should be called before the first call to this function.
-+ Parameter:  Pointer to Si2158 Context
-+ Returns:    I2C transaction error code, NO_SILABS_TERCAB_ERROR if successful
-+ Programming Guide Reference:    DTV setup flowchart
-+ ******************************************************************************************/
-+static int silabs_tercap_download_dtv_properties(silabs_tercab_context *ctx)
-+{
-+	const u8  dtv_agc_freeze_input_level          = Si2158_DTV_AGC_FREEZE_INPUT_PROP_LEVEL_LOW  ; /* (default 'LOW') */
-+	const u8  dtv_agc_freeze_input_pin            = Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_NONE   ; /* (default 'NONE') */
-+	const u8  dtv_agc_speed_agc_decim             = Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_OFF     ; /* (default 'OFF') */
-+	const u8  dtv_agc_speed_if_agc_speed          = Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_AUTO ; /* (default 'AUTO') */
-+	const u8  dtv_config_if_port_dtv_agc_source   = Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_AGC_SOURCE_AGC2_3DB ; /* (default 'INTERNAL') */
-+	const u8  dtv_config_if_port_dtv_out_type     = Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_OUT_TYPE_LIF_IF2   ; /* (default 'LIF_IF2') */
-+	const u8  dtv_ext_agc_max_10mv                =   200; /* (default   200) */
-+	const u8  dtv_ext_agc_min_10mv                =    50; /* (default    50) */
-+	const u8  dtv_filter_select_filter            = Si2158_DTV_FILTER_SELECT_PROP_FILTER_CUSTOM1 ; /* (default 'CUSTOM1') */
-+	const u8  dtv_ien_chlien                      = Si2158_DTV_IEN_PROP_CHLIEN_ENABLE ; /* (default 'ENABLE') */
-+	const u8  dtv_initial_agc_speed_agc_decim     = Si2158_DTV_INITIAL_AGC_SPEED_PROP_AGC_DECIM_OFF     ; /* (default 'OFF') */
-+	const u8  dtv_initial_agc_speed_if_agc_speed  = Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_AUTO ; /* (default 'AUTO') */
-+	const u16 dtv_initial_agc_speed_period        =     0; /* (default     0) */
-+	const u8  dtv_internal_zif_atsc               = Si2158_DTV_INTERNAL_ZIF_PROP_ATSC_LIF   ; /* (default 'LIF') */
-+	const u8  dtv_internal_zif_dtmb               = Si2158_DTV_INTERNAL_ZIF_PROP_DTMB_LIF   ; /* (default 'LIF') */
-+	const u8  dtv_internal_zif_dvbc               = Si2158_DTV_INTERNAL_ZIF_PROP_DVBC_LIF   ; /* (default 'LIF') */
-+	const u8  dtv_internal_zif_dvbt               = Si2158_DTV_INTERNAL_ZIF_PROP_DVBT_LIF   ; /* (default 'LIF') */
-+	const u8  dtv_internal_zif_isdbc              = Si2158_DTV_INTERNAL_ZIF_PROP_ISDBC_LIF  ; /* (default 'LIF') */
-+	const u8  dtv_internal_zif_isdbt              = Si2158_DTV_INTERNAL_ZIF_PROP_ISDBT_LIF  ; /* (default 'LIF') */
-+	const u8  dtv_internal_zif_qam_us             = Si2158_DTV_INTERNAL_ZIF_PROP_QAM_US_LIF ; /* (default 'LIF') */
-+	const u8  dtv_int_sense_chlnegen              = Si2158_DTV_INT_SENSE_PROP_CHLNEGEN_DISABLE ; /* (default 'DISABLE') */
-+	const u8  dtv_int_sense_chlposen              = Si2158_DTV_INT_SENSE_PROP_CHLPOSEN_ENABLE  ; /* (default 'ENABLE') */
-+	const u16 dtv_lif_freq_offset                 =  4000; /* (default  5000) */
-+	const u8  dtv_lif_out_amp                     =    27; /* (default    27) */
-+	const u8  dtv_lif_out_offset                  =   148; /* (default   148) */
-+	const u8  dtv_mode_bw                         = Si2158_DTV_MODE_PROP_BW_BW_6MHZ              ; /* (default 'BW_8MHZ') */
-+	const u8  dtv_mode_invert_spectrum            = Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_NORMAL  ; /* (default 'NORMAL') */
-+	const u8  dtv_mode_modulation                 = Si2158_DTV_MODE_PROP_MODULATION_ATSC         ; /* (default 'DVBT') */
-+	const s8  dtv_pga_limits_max                  =    -1; /* (default    -1) */
-+	const s8  dtv_pga_limits_min                  =    -1; /* (default    -1) */
-+	const u8  dtv_pga_target_override_enable      = Si2158_DTV_PGA_TARGET_PROP_OVERRIDE_ENABLE_DISABLE ; /* (default 'DISABLE') */
-+	const s8  dtv_pga_target_pga_target           =     0; /* (default     0) */
-+	const u8  dtv_rf_top_dtv_rf_top               = Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_AUTO ; /* (default 'AUTO') */
-+	const s8  dtv_rsq_rssi_threshold_hi           =     0; /* (default     0) */
-+	const s8  dtv_rsq_rssi_threshold_lo           =   -80; /* (default   -80) */
-+	const u8  dtv_zif_dc_canceller_bw_bandwidth   = Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_DEFAULT ; /* (default 'DEFAULT') */
-+
-+	u16 si2158_dtv_agc_freeze_input_prop_data;
-+	u16 si2158_dtv_agc_speed_prop_data;
-+	u16 si2158_dtv_config_if_port_prop_data;
-+	u16 si2158_dtv_ext_agc_prop_data;
-+	u16 si2158_dtv_filter_select_prop_data;
-+	u16 si2158_dtv_ien_prop_data;
-+	u16 si2158_dtv_initial_agc_speed_prop_data;
-+	u16 si2158_dtv_initial_agc_speed_period_prop_data;
-+	u16 si2158_dtv_internal_zif_prop_data;
-+	u16 si2158_dtv_int_sense_prop_data;
-+	u16 si2158_dtv_lif_freq_prop_data;
-+	u16 si2158_dtv_lif_out_prop_data;
-+	u16 si2158_dtv_mode_prop_data;
-+	u16 si2158_dtv_pga_limits_prop_data;
-+	u16 si2158_dtv_pga_target_prop_data;
-+	u16 si2158_dtv_rf_top_prop_data;
-+	u16 si2158_dtv_rsq_rssi_threshold_prop_data;
-+	u16 si2158_dtv_zif_dc_canceller_bw_prop_data;
-+
-+	SiTRACE("%s()\n", __func__);
-+
-+	si2158_dtv_agc_freeze_input_prop_data = (dtv_agc_freeze_input_level & Si2158_DTV_AGC_FREEZE_INPUT_PROP_LEVEL_MASK) << Si2158_DTV_AGC_FREEZE_INPUT_PROP_LEVEL_LSB  |
-+		   (dtv_agc_freeze_input_pin   & Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_MASK  ) << Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_AGC_FREEZE_INPUT_PROP_CODE, si2158_dtv_agc_freeze_input_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_agc_speed_prop_data = (dtv_agc_speed_if_agc_speed & Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_MASK) << Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_LSB  |
-+		   (dtv_agc_speed_agc_decim    & Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_MASK   ) << Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_AGC_SPEED_PROP_CODE, si2158_dtv_agc_speed_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_config_if_port_prop_data = (dtv_config_if_port_dtv_out_type   & Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_OUT_TYPE_MASK  ) << Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_OUT_TYPE_LSB  |
-+		   (dtv_config_if_port_dtv_agc_source & Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_AGC_SOURCE_MASK) << Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_AGC_SOURCE_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_CONFIG_IF_PORT_PROP_CODE, si2158_dtv_config_if_port_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_ext_agc_prop_data = (dtv_ext_agc_min_10mv & Si2158_DTV_EXT_AGC_PROP_MIN_10MV_MASK) << Si2158_DTV_EXT_AGC_PROP_MIN_10MV_LSB  |
-+		   (dtv_ext_agc_max_10mv & Si2158_DTV_EXT_AGC_PROP_MAX_10MV_MASK) << Si2158_DTV_EXT_AGC_PROP_MAX_10MV_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_EXT_AGC_PROP_CODE, si2158_dtv_ext_agc_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	switch (ctx->part) {
-+	case 58:
-+		si2158_dtv_filter_select_prop_data = (dtv_filter_select_filter & Si2158_DTV_FILTER_SELECT_PROP_FILTER_MASK) << Si2158_DTV_FILTER_SELECT_PROP_FILTER_LSB ;
-+		if (silabs_tercab_set_property(ctx, Si2158_DTV_FILTER_SELECT_PROP_CODE, si2158_dtv_filter_select_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+		}
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	si2158_dtv_ien_prop_data = (dtv_ien_chlien & Si2158_DTV_IEN_PROP_CHLIEN_MASK) << Si2158_DTV_IEN_PROP_CHLIEN_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_IEN_PROP_CODE, si2158_dtv_ien_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_initial_agc_speed_prop_data = (dtv_initial_agc_speed_if_agc_speed & Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_MASK) << Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_LSB  |
-+		   (dtv_initial_agc_speed_agc_decim    & Si2158_DTV_INITIAL_AGC_SPEED_PROP_AGC_DECIM_MASK   ) << Si2158_DTV_INITIAL_AGC_SPEED_PROP_AGC_DECIM_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_INITIAL_AGC_SPEED_PROP_CODE, si2158_dtv_initial_agc_speed_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_initial_agc_speed_period_prop_data = (dtv_initial_agc_speed_period & Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_PERIOD_MASK) << Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_PERIOD_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_CODE, si2158_dtv_initial_agc_speed_period_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_internal_zif_prop_data = (dtv_internal_zif_atsc   & Si2158_DTV_INTERNAL_ZIF_PROP_ATSC_MASK  ) << Si2158_DTV_INTERNAL_ZIF_PROP_ATSC_LSB  |
-+		   (dtv_internal_zif_qam_us & Si2158_DTV_INTERNAL_ZIF_PROP_QAM_US_MASK) << Si2158_DTV_INTERNAL_ZIF_PROP_QAM_US_LSB  |
-+		   (dtv_internal_zif_dvbt   & Si2158_DTV_INTERNAL_ZIF_PROP_DVBT_MASK  ) << Si2158_DTV_INTERNAL_ZIF_PROP_DVBT_LSB  |
-+		   (dtv_internal_zif_dvbc   & Si2158_DTV_INTERNAL_ZIF_PROP_DVBC_MASK  ) << Si2158_DTV_INTERNAL_ZIF_PROP_DVBC_LSB  |
-+		   (dtv_internal_zif_isdbt  & Si2158_DTV_INTERNAL_ZIF_PROP_ISDBT_MASK ) << Si2158_DTV_INTERNAL_ZIF_PROP_ISDBT_LSB  |
-+		   (dtv_internal_zif_isdbc  & Si2158_DTV_INTERNAL_ZIF_PROP_ISDBC_MASK ) << Si2158_DTV_INTERNAL_ZIF_PROP_ISDBC_LSB  |
-+		   (dtv_internal_zif_dtmb   & Si2158_DTV_INTERNAL_ZIF_PROP_DTMB_MASK  ) << Si2158_DTV_INTERNAL_ZIF_PROP_DTMB_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_INTERNAL_ZIF_PROP_CODE, si2158_dtv_internal_zif_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_int_sense_prop_data = (dtv_int_sense_chlnegen & Si2158_DTV_INT_SENSE_PROP_CHLNEGEN_MASK) << Si2158_DTV_INT_SENSE_PROP_CHLNEGEN_LSB  |
-+		   (dtv_int_sense_chlposen & Si2158_DTV_INT_SENSE_PROP_CHLPOSEN_MASK) << Si2158_DTV_INT_SENSE_PROP_CHLPOSEN_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_INT_SENSE_PROP_CODE, si2158_dtv_int_sense_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_lif_freq_prop_data = (dtv_lif_freq_offset & Si2158_DTV_LIF_FREQ_PROP_OFFSET_MASK) << Si2158_DTV_LIF_FREQ_PROP_OFFSET_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_LIF_FREQ_PROP_CODE, si2158_dtv_lif_freq_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_lif_out_prop_data = (dtv_lif_out_offset & Si2158_DTV_LIF_OUT_PROP_OFFSET_MASK) << Si2158_DTV_LIF_OUT_PROP_OFFSET_LSB  |
-+		   (dtv_lif_out_amp    & Si2158_DTV_LIF_OUT_PROP_AMP_MASK   ) << Si2158_DTV_LIF_OUT_PROP_AMP_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_LIF_OUT_PROP_CODE, si2158_dtv_lif_out_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_mode_prop_data = (dtv_mode_bw              & Si2158_DTV_MODE_PROP_BW_MASK             ) << Si2158_DTV_MODE_PROP_BW_LSB  |
-+		   (dtv_mode_modulation      & Si2158_DTV_MODE_PROP_MODULATION_MASK     ) << Si2158_DTV_MODE_PROP_MODULATION_LSB  |
-+		   (dtv_mode_invert_spectrum & Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_MASK) << Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_MODE_PROP_CODE, si2158_dtv_mode_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_pga_limits_prop_data = (dtv_pga_limits_min & Si2158_DTV_PGA_LIMITS_PROP_MIN_MASK) << Si2158_DTV_PGA_LIMITS_PROP_MIN_LSB  |
-+		   (dtv_pga_limits_max & Si2158_DTV_PGA_LIMITS_PROP_MAX_MASK) << Si2158_DTV_PGA_LIMITS_PROP_MAX_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_PGA_LIMITS_PROP_CODE, si2158_dtv_pga_limits_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_pga_target_prop_data = (dtv_pga_target_pga_target      & Si2158_DTV_PGA_TARGET_PROP_PGA_TARGET_MASK     ) << Si2158_DTV_PGA_TARGET_PROP_PGA_TARGET_LSB  |
-+		   (dtv_pga_target_override_enable & Si2158_DTV_PGA_TARGET_PROP_OVERRIDE_ENABLE_MASK) << Si2158_DTV_PGA_TARGET_PROP_OVERRIDE_ENABLE_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_PGA_TARGET_PROP_CODE, si2158_dtv_pga_target_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_rf_top_prop_data = (dtv_rf_top_dtv_rf_top & Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_MASK) << Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_RF_TOP_PROP_CODE, si2158_dtv_rf_top_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_rsq_rssi_threshold_prop_data = (dtv_rsq_rssi_threshold_lo & Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_LO_MASK) << Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_LO_LSB  |
-+		   (dtv_rsq_rssi_threshold_hi & Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_HI_MASK) << Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_HI_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_CODE, si2158_dtv_rsq_rssi_threshold_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_dtv_zif_dc_canceller_bw_prop_data = (dtv_zif_dc_canceller_bw_bandwidth & Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_MASK) << Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_CODE, si2158_dtv_zif_dc_canceller_bw_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/*****************************************************************************************
-+NAME: silabs_tercap_download_tuner_properties
-+ DESCRIPTION: Setup Si2158 TUNER properties configuration
-+ This function will download all the TUNER configuration properties.
-+ The function SetupTUNERDefaults() should be called before the first call to this function.
-+ Parameter:  Pointer to Si2158 Context
-+ Returns:    I2C transaction error code, NO_SILABS_TERCAB_ERROR if successful
-+ Programming Guide Reference:    TUNER setup flowchart
-+ ******************************************************************************************/
-+static int silabs_tercap_download_tuner_properties(silabs_tercab_context *ctx)
-+{
-+	const s16 tuner_blocked_vco_vco_code = 0x8000; /* (default 0x8000) */
-+	const u8  tuner_ien_rssihien         = Si2158_TUNER_IEN_PROP_RSSIHIEN_DISABLE;          /* (default 'DISABLE') */
-+	const u8  tuner_ien_rssilien         = Si2158_TUNER_IEN_PROP_RSSILIEN_DISABLE;          /* (default 'DISABLE') */
-+	const u8  tuner_ien_tcien            = Si2158_TUNER_IEN_PROP_TCIEN_ENABLE;              /* (default 'ENABLE') */
-+	const u8  tuner_int_sense_tcnegen    = Si2158_TUNER_INT_SENSE_PROP_TCNEGEN_DISABLE;     /* (default 'DISABLE') */
-+	const u8  tuner_int_sense_rssilnegen = Si2158_TUNER_INT_SENSE_PROP_RSSILNEGEN_DISABLE;  /* (default 'DISABLE') */
-+	const u8  tuner_int_sense_rssihnegen = Si2158_TUNER_INT_SENSE_PROP_RSSIHNEGEN_DISABLE;  /* (default 'DISABLE') */
-+	const u8  tuner_int_sense_tcposen    = Si2158_TUNER_INT_SENSE_PROP_TCPOSEN_ENABLE;      /* (default 'ENABLE') */
-+	const u8  tuner_int_sense_rssilposen = Si2158_TUNER_INT_SENSE_PROP_RSSILPOSEN_ENABLE;   /* (default 'ENABLE') */
-+	const u8  tuner_int_sense_rssihposen = Si2158_TUNER_INT_SENSE_PROP_RSSIHPOSEN_ENABLE;   /* (default 'ENABLE') */
-+	const u8  tuner_lo_injection_band_1  = Si2158_TUNER_LO_INJECTION_PROP_BAND_1_HIGH_SIDE; /* (default 'HIGH_SIDE') */
-+	const u8  tuner_lo_injection_band_2  = Si2158_TUNER_LO_INJECTION_PROP_BAND_2_LOW_SIDE;  /* (default 'LOW_SIDE') */
-+	const u8  tuner_lo_injection_band_3  = Si2158_TUNER_LO_INJECTION_PROP_BAND_3_LOW_SIDE;  /* (default 'LOW_SIDE') */
-+	const u8  tuner_return_loss_config   = Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_127;        /* (default '127') */
-+	const u8  tuner_return_loss_mode     = Si2158_TUNER_RETURN_LOSS_PROP_MODE_TERRESTRIAL;  /* (default 'TERRESTRIAL') */
-+
-+	u16 si2158_tuner_blocked_vco_prop_data;
-+	u16 si2158_tuner_ien_prop_data;
-+	u16 si2158_tuner_int_sense_prop_data;
-+	u16 si2158_tuner_lo_injection_prop_data;
-+	u16 si2158_tuner_return_loss_prop_data;
-+
-+	SiTRACE("%s()\n", __func__);
-+
-+	si2158_tuner_blocked_vco_prop_data = (tuner_blocked_vco_vco_code & Si2158_TUNER_BLOCKED_VCO_PROP_VCO_CODE_MASK) << Si2158_TUNER_BLOCKED_VCO_PROP_VCO_CODE_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_TUNER_BLOCKED_VCO_PROP_CODE, si2158_tuner_blocked_vco_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_tuner_ien_prop_data = (tuner_ien_tcien    & Si2158_TUNER_IEN_PROP_TCIEN_MASK   ) << Si2158_TUNER_IEN_PROP_TCIEN_LSB  |
-+		   (tuner_ien_rssilien & Si2158_TUNER_IEN_PROP_RSSILIEN_MASK) << Si2158_TUNER_IEN_PROP_RSSILIEN_LSB  |
-+		   (tuner_ien_rssihien & Si2158_TUNER_IEN_PROP_RSSIHIEN_MASK) << Si2158_TUNER_IEN_PROP_RSSIHIEN_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_TUNER_IEN_PROP_CODE, si2158_tuner_ien_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_tuner_int_sense_prop_data = (tuner_int_sense_tcnegen    & Si2158_TUNER_INT_SENSE_PROP_TCNEGEN_MASK   ) << Si2158_TUNER_INT_SENSE_PROP_TCNEGEN_LSB  |
-+		   (tuner_int_sense_rssilnegen & Si2158_TUNER_INT_SENSE_PROP_RSSILNEGEN_MASK) << Si2158_TUNER_INT_SENSE_PROP_RSSILNEGEN_LSB  |
-+		   (tuner_int_sense_rssihnegen & Si2158_TUNER_INT_SENSE_PROP_RSSIHNEGEN_MASK) << Si2158_TUNER_INT_SENSE_PROP_RSSIHNEGEN_LSB  |
-+		   (tuner_int_sense_tcposen    & Si2158_TUNER_INT_SENSE_PROP_TCPOSEN_MASK   ) << Si2158_TUNER_INT_SENSE_PROP_TCPOSEN_LSB  |
-+		   (tuner_int_sense_rssilposen & Si2158_TUNER_INT_SENSE_PROP_RSSILPOSEN_MASK) << Si2158_TUNER_INT_SENSE_PROP_RSSILPOSEN_LSB  |
-+		   (tuner_int_sense_rssihposen & Si2158_TUNER_INT_SENSE_PROP_RSSIHPOSEN_MASK) << Si2158_TUNER_INT_SENSE_PROP_RSSIHPOSEN_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_TUNER_INT_SENSE_PROP_CODE, si2158_tuner_int_sense_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_tuner_lo_injection_prop_data = (tuner_lo_injection_band_1 & Si2158_TUNER_LO_INJECTION_PROP_BAND_1_MASK) << Si2158_TUNER_LO_INJECTION_PROP_BAND_1_LSB  |
-+		   (tuner_lo_injection_band_2 & Si2158_TUNER_LO_INJECTION_PROP_BAND_2_MASK) << Si2158_TUNER_LO_INJECTION_PROP_BAND_2_LSB  |
-+		   (tuner_lo_injection_band_3 & Si2158_TUNER_LO_INJECTION_PROP_BAND_3_MASK) << Si2158_TUNER_LO_INJECTION_PROP_BAND_3_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_TUNER_LO_INJECTION_PROP_CODE, si2158_tuner_lo_injection_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	si2158_tuner_return_loss_prop_data = (tuner_return_loss_config & Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_MASK) << Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_LSB  |
-+		   (tuner_return_loss_mode   & Si2158_TUNER_RETURN_LOSS_PROP_MODE_MASK  ) << Si2158_TUNER_RETURN_LOSS_PROP_MODE_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_TUNER_RETURN_LOSS_PROP_CODE, si2158_tuner_return_loss_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+static int silabs_tercap_download_all_properties(silabs_tercab_context *ctx)
-+{
-+	struct silabs_tercab_priv *priv = NULL; /* for debug output only */
-+	int err = NO_SILABS_TERCAB_ERROR;
-+	int ret = silabs_tercab_download_atv_properties(ctx);
-+	if (ret) {
-+		err = ret;
-+		silabs_tercab_err("ERROR: download all ATV properties failed=0x%x\n", err);
-+	}
-+	ret = silabs_tercap_download_common_properties(ctx);
-+	if (ret) {
-+		err = ret;
-+		silabs_tercab_err("ERROR: download all COMMON properties failed=0x%x\n", err);
-+	}
-+	ret = silabs_tercap_download_dtv_properties(ctx);
-+	if (ret) {
-+		err = ret;
-+		silabs_tercab_err("ERROR: download all DTV properties failed=0x%x\n", err);
-+	}
-+	ret = silabs_tercap_download_tuner_properties(ctx);
-+	if (ret) {
-+		err = ret;
-+		silabs_tercab_err("ERROR: download all TUNER properties failed=0x%x\n", err);
-+	}
-+	return err;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: silabs_tercab_configure
-+  DESCRIPTION: Setup Si2158 video filters, GPIOs/clocks, Common Properties startup, etc.
-+  Parameter:  Pointer to Si2158 Context
-+  Returns:    I2C transaction error code, NO_SILABS_TERCAB_ERROR if successful
-+ ************************************************************************************************************************/
-+static int silabs_tercab_configure(silabs_tercab_context *ctx)
-+{
-+	/* Set All Properties startup configuration */
-+	return silabs_tercap_download_all_properties(ctx);
-+}
-+
-+/************************************************************************************************************************
-+  NAME: silabs_tercab_init
-+  DESCRIPTION:Reset and Initialize Si2158
-+  Parameter:  Si2158 Context (I2C address)
-+  Returns:    I2C transaction error code, NO_SILABS_TERCAB_ERROR if successful
-+ ************************************************************************************************************************/
-+static int silabs_tercab_init(struct silabs_tercab_priv *priv)
-+{
-+	silabs_tercab_context *ctx = &priv->tuner;
-+	int return_code;
-+	SiTRACE("silabs_tercab_init starting...\n");
-+
-+	/* PowerUp into bootloader */
-+	return_code = silabs_tercab_power_up_with_patch(priv);
-+	if (return_code != NO_SILABS_TERCAB_ERROR) {
-+		SiTRACE ("silabs_tercab_power_up_with_patch error 0x%02x: %s\n", return_code, silabs_tercab_error_text(return_code) );
-+		return return_code;
-+	}
-+	/* At this point, FW is loaded and started.  */
-+	silabs_tercab_configure(ctx);
-+	SiTRACE("silabs_tercab_init complete...\n");
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2158_CONFIG_CLOCKS COMMAND                    */
-+/*---------------------------------------------------*/
-+static u8 silabs_tercab_config_clocks(silabs_tercab_context *ctx,
-+		u8   subcode,
-+		u8   clock_mode,
-+		u8   en_xout)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[3];
-+	u8 rspByteBuffer[1];
-+
-+	SiTRACE("%s()\n", __func__);
-+
-+	cmdByteBuffer[0] = Si2158_CONFIG_CLOCKS_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( subcode    & Si2158_CONFIG_CLOCKS_CMD_SUBCODE_MASK    ) << Si2158_CONFIG_CLOCKS_CMD_SUBCODE_LSB   );
-+	cmdByteBuffer[2] = (u8) ( ( clock_mode & Si2158_CONFIG_CLOCKS_CMD_CLOCK_MODE_MASK ) << Si2158_CONFIG_CLOCKS_CMD_CLOCK_MODE_LSB|
-+			                  ( en_xout    & Si2158_CONFIG_CLOCKS_CMD_EN_XOUT_MASK    ) << Si2158_CONFIG_CLOCKS_CMD_EN_XOUT_LSB   );
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 3, cmdByteBuffer) != 3) {
-+		SiTRACE("Error writing CONFIG_CLOCKS bytes!\n");
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	error_code = silabs_tercab_poll_response(ctx->i2c_adap, ctx->i2c_addr, 1, rspByteBuffer, &ctx->status);
-+	if (error_code) {
-+		SiTRACE("Error polling CONFIG_CLOCKS response\n");
-+		return error_code;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/************************************************************************************************************************
-+  NAME: silabs_tercab_xout_on
-+  Parameter:  Pointer to Si2158 Context (I2C address)
-+  Returns:    I2C transaction error code, NO_SILABS_TERCAB_ERROR if successful
-+ ************************************************************************************************************************/
-+static int silabs_tercab_xout_on(silabs_tercab_context *ctx)
-+{
-+	SiTRACE("Turning Xout ON\n");
-+
-+	return silabs_tercab_config_clocks(ctx,
-+				Si2158_CONFIG_CLOCKS_CMD_SUBCODE_CODE,
-+				Si2158_CONFIG_CLOCKS_CMD_CLOCK_MODE_XTAL,
-+				Si2158_CONFIG_CLOCKS_CMD_EN_XOUT_EN_XOUT);
-+}
-+
-+/************************************************************************************************************************
-+  NAME: silabs_tercab_xout_off
-+  Parameter:  Pointer to Si2158 Context (I2C address)
-+  Returns:    I2C transaction error code, NO_SILABS_TERCAB_ERROR if successful
-+ ************************************************************************************************************************/
-+static int silabs_tercab_xout_off(silabs_tercab_context *ctx)
-+{
-+	SiTRACE("Turning Xout OFF\n");
-+
-+	return silabs_tercab_config_clocks(ctx,
-+			Si2158_CONFIG_CLOCKS_CMD_SUBCODE_CODE,
-+			Si2158_CONFIG_CLOCKS_CMD_CLOCK_MODE_XTAL,
-+			Si2158_CONFIG_CLOCKS_CMD_EN_XOUT_DIS_XOUT);
-+}
-+
-+static int silabs_tercab_initialize(struct dvb_frontend *fe)
-+{
-+	struct silabs_tercab_priv *priv = fe->tuner_priv;
-+	int ter_clock_needed = 1;
-+	int res = 0;
-+	int ret = 0;
-+	u16 data;
-+
-+	mutex_lock(&priv->lock);
-+
-+	/* Do a full init of the Ter Tuner only if it has not been already done */
-+	if (priv->silabs_tercab_init_done==0) {
-+		silabs_tercab_info("%s()\n", __func__);
-+		SiTRACE("Init terrestrial tuner @ 0x%02X\n", priv->tuner.i2c_addr);
-+		if ((res= silabs_tercab_init(priv)) != NO_SILABS_TERCAB_ERROR) {
-+			silabs_tercab_err("silabs_tercab_init() failed.\n");
-+			SiTRACE("Terrestrial tuner HW init error: 0x%02x : %s\n",res, silabs_tercab_error_text(res) );
-+			ret = -ENODEV;
-+			goto fail;
-+		}
-+		priv->tuner.part = priv->tuner.rsp.part_info.part;
-+		priv->tuner.chiprev = priv->tuner.rsp.part_info.chiprev;
-+		silabs_tercab_info("Silicon Labs tuner Si21%u rev. %u detected\n", priv->tuner.part, priv->tuner.chiprev);
-+		if (priv->agc_control) {
-+			data = (Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_OUT_TYPE_LIF_IF1 & Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_OUT_TYPE_MASK  ) << Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_OUT_TYPE_LSB  |
-+				   (Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_AGC_SOURCE_INTERNAL & Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_AGC_SOURCE_MASK) << Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_AGC_SOURCE_LSB ;
-+			silabs_tercab_set_property(&priv->tuner, Si2158_DTV_CONFIG_IF_PORT_PROP_CODE, data);
-+		}
-+		data = (priv->crystal_trim_xo_cap & Si2158_CRYSTAL_TRIM_PROP_XO_CAP_MASK) << Si2158_CRYSTAL_TRIM_PROP_XO_CAP_LSB;
-+		if (silabs_tercab_set_property(&priv->tuner, Si2158_CRYSTAL_TRIM_PROP_CODE, data) != NO_SILABS_TERCAB_ERROR) {
-+			ret = -EIO;
-+			goto fail;
-+		}
-+	} else {
-+		SiTRACE("Wakeup terrestrial tuner\n");
-+		if ((res= silabs_tercab_poll_cts(priv->i2c_props.adap, priv->i2c_props.addr)) != NO_SILABS_TERCAB_ERROR) {
-+			silabs_tercab_err("tuner Si2158 wake up failed.\n");
-+			SiTRACE("Terrestrial tuner wake up error: 0x%02x : %s\n",res, silabs_tercab_error_text(res) );
-+			ret = -ENODEV;
-+			goto fail;
-+		}
-+	}
-+
-+	/* ------------------------------------------------------------ */
-+	/* If the terrestrial tuner's clock is required, activate it    */
-+	/* ------------------------------------------------------------ */
-+	SiTRACE("ter_clock_needed %d\n",ter_clock_needed);
-+	if (ter_clock_needed) {
-+		SiTRACE("Turn terrestrial tuner clock on\n");
-+		if (priv->clock_control != 0 /* Si2168B_CLOCK_ALWAYS_OFF */) {
-+			SiTRACE("Terrestrial tuner CLOCK ON\n");
-+			if ((res = silabs_tercab_xout_on(&priv->tuner) ) != 0) {
-+				SiTRACE("Terrestrial tuner CLOCK ON error: 0x%02x : %s\n",res, silabs_tercab_error_text(res) );
-+				ret = -ENODEV;
-+				goto fail;
-+			}
-+		}
-+	}
-+
-+fail:
-+	mutex_unlock(&priv->lock);
-+
-+	if (ret==0) {
-+		priv->silabs_tercab_init_done = 1;
-+		silabs_tercab_dbg("initializing tuner succeeded\n");
-+	} else {
-+		priv->silabs_tercab_init_done = 0;
-+	}
-+
-+	return ret;
-+}
-+
-+#if 0
-+/*---------------------------------------------------*/
-+/* Si2158_STANDBY COMMAND                          */
-+/*---------------------------------------------------*/
-+static u8 silabs_tercab_standby(silabs_tercab_context *ctx,	u8 type)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[1];
-+	ctx->rsp.standby.STATUS = ctx->status;
-+
-+	SiTRACE("%s()\n", __func__);
-+
-+	cmdByteBuffer[0] = Si2158_STANDBY_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( type & Si2158_STANDBY_CMD_TYPE_MASK ) << Si2158_STANDBY_CMD_TYPE_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing STANDBY bytes!\n");
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	error_code = Si2158_pollForResponse(ctx, 1, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling STANDBY response\n");
-+		return error_code;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2158_POWER_DOWN COMMAND                       */
-+/*---------------------------------------------------*/
-+static u8 silabs_tercab_power_down(silabs_tercab_context *ctx)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[1];
-+	u8 rspByteBuffer[1];
-+	ctx->rsp.power_down.STATUS = ctx->status;
-+
-+	SiTRACE("%s()\n", __func__);
-+
-+	cmdByteBuffer[0] = Si2158_POWER_DOWN_CMD;
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 1, cmdByteBuffer) != 1) {
-+		SiTRACE("Error writing POWER_DOWN bytes!\n");
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	error_code = Si2158_pollForResponse(ctx, 1, rspByteBuffer);
-+	if (error_code) {
-+		SiTRACE("Error polling POWER_DOWN response\n");
-+		return error_code;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+#endif
-+
-+static int silabs_tercab_sleep(struct dvb_frontend *fe)
-+{
-+	struct silabs_tercab_priv *priv = fe->tuner_priv;
-+	int res;
-+	int ret = 0;
-+
-+	silabs_tercab_dbg("\n");
-+
-+	mutex_lock(&priv->lock);
-+
-+	if (priv->clock_control != 1 /* Si2168B_CLOCK_ALWAYS_ON */) {
-+		SiTRACE("Terrestrial tuner clock OFF\n");
-+		res = silabs_tercab_xout_off(&priv->tuner);
-+		if (res) {
-+			SiTRACE("Terrestrial tuner CLOCK OFF error: 0x%02x : %s\n",res, silabs_tercab_error_text(res) );
-+			ret = -EPERM;
-+		}
-+	}
-+#if 1
-+#if 0
-+#define  Si2158_STANDBY_CMD_TYPE_MIN 0
-+	priv->silabs_tercab_init_done = 0;
-+	priv->firmware_started = 0;
-+	SiTRACE("Terrestrial tuner STANDBY\n");
-+	if ((res= silabs_tercab_standby(&priv->tuner, Si2158_STANDBY_CMD_TYPE_MIN)) !=0 ) {
-+		SiTRACE("Terrestrial tuner Standby error: 0x%02x : %s\n",res, silabs_tercab_error_text(res) );
-+		ret = -EPERM;
-+	};
-+#else
-+	silabs_tercab_info("Standby ignored\n");
-+#endif
-+#else
-+	priv->silabs_tercab_init_done = 0;
-+	priv->firmware_started = 0;
-+	if (silabs_tercab_power_down(&priv->tuner) != NO_SILABS_TERCAB_ERROR) {
-+		silabs_tercab_err("silabs_tercab_power_down() failed\n");
-+		ret = -EPERM;
-+	}
-+#endif
-+
-+	mutex_unlock(&priv->lock);
-+
-+	return ret;
-+}
-+
-+/************************************************************************************************************************
-+  silabs_tercab_fef function
-+  Use:        TER tuner FEF activation function
-+              Used to enable/disable the FEF mode in the terrestrial tuner
-+  Comments:   If the tuner is connected via the demodulator's I2C switch, enabling/disabling the i2c_passthru is required before/after tuning.
-+  Parameter:  *front_end, the front-end handle
-+  Parameter:  fef, a flag controlling the selection between FEF 'off'(0) and FEF 'on'(1)
-+  Returns:    1
-+ ************************************************************************************************************************/
-+static int silabs_tercab_fef(struct dvb_frontend *fe, int fef)
-+{
-+	struct silabs_tercab_priv *priv = fe->tuner_priv;
-+	u8  agc_freeze_input_pin;
-+	u8  agc_speed_agc_decim;
-+	u8  agc_speed_if_agc_speed;
-+	u16 si2158_dtv_agc_freeze_input__prop_data;
-+	u16 si2158_dtv_agc_speed__prop_data;
-+
-+	SiTRACE("%s(): FEF MODE=%d FEF=%d\n", __func__, priv->fef_mode, fef);
-+
-+	if (priv->fef_mode == Si2177_FEF_MODE_FREEZE_PIN) {
-+		SiTRACE("FEF mode Si2177_FEF_MODE_FREEZE_PIN\n");
-+		if (fef == 0) {
-+			agc_freeze_input_pin = Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_NONE;
-+		} else {
-+			agc_freeze_input_pin = Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_GPIO1;
-+		}
-+		si2158_dtv_agc_freeze_input__prop_data = (Si2158_DTV_AGC_FREEZE_INPUT_PROP_LEVEL_HIGH & Si2158_DTV_AGC_FREEZE_INPUT_PROP_LEVEL_MASK) << Si2158_DTV_AGC_FREEZE_INPUT_PROP_LEVEL_LSB  |
-+			   (agc_freeze_input_pin   & Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_MASK  ) << Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_LSB ;
-+		silabs_tercab_set_property(&priv->tuner,  Si2158_DTV_AGC_FREEZE_INPUT_PROP_CODE, si2158_dtv_agc_freeze_input__prop_data);
-+	}
-+
-+#ifdef L1_RF_TER_TUNER_FEF_MODE_SLOW_INITIAL_AGC_SETUP
-+	if (priv->fef_mode == Si2177_FEF_MODE_SLOW_INITIAL_AGC) {
-+		SiTRACE("FEF mode Si2168B_FEF_MODE_SLOW_INITIAL_AGC (AGC slowed down after tuning)\n");
-+	}
-+#endif /* L1_RF_TER_TUNER_FEF_MODE_SLOW_INITIAL_AGC_SETUP */
-+
-+#ifdef L1_RF_TER_TUNER_FEF_MODE_SLOW_NORMAL_AGC_SETUP
-+	if (priv->fef_mode == Si2177_FEF_MODE_SLOW_NORMAL_AGC) {
-+		SiTRACE("FEF mode Si2168B_FEF_MODE_SLOW_NORMAL_AGC: AGC slowed down\n");
-+		if (fef == 0) {
-+			agc_speed_agc_decim    = Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_OFF;
-+			agc_speed_if_agc_speed = Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_AUTO;
-+		} else {
-+			agc_speed_if_agc_speed = Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_39;
-+			agc_speed_agc_decim    = Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_4;
-+		}
-+		si2158_dtv_agc_speed__prop_data = (agc_speed_if_agc_speed & Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_MASK) << Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_LSB  |
-+			   (agc_speed_agc_decim    & Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_MASK   ) << Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2158_DTV_AGC_SPEED_PROP_CODE, si2158_dtv_agc_speed__prop_data);
-+	}
-+#endif /* L1_RF_TER_TUNER_FEF_MODE_SLOW_NORMAL_AGC_SETUP */
-+	SiTRACE("silabs_tercab_fef done\n");
-+	return 1;
-+}
-+
-+/************************************************************************************************************************
-+  silabs_tercab_fef_setup function
-+  Use:        TER tuner LPF setting function
-+              Used to configure the FEF mode in the terrestrial tuner
-+  Comments:   If the tuner is connected via the demodulator's I2C switch, enabling/disabling the i2c_passthru is required before/after tuning.
-+  Behavior:   This function closes the Si2168B's I2C switch then sets the TER FEF mode and finally reopens the I2C switch
-+  Parameter:  *front_end, the front-end handle
-+  Parameter:  fef, a flag controlling the selection between FEF 'off'(0) and FEF 'on'(1)
-+  Returns:    1
-+ ************************************************************************************************************************/
-+static int silabs_tercab_fef_setup(struct dvb_frontend *fe, int fef)
-+{
-+	struct silabs_tercab_priv *priv = fe->tuner_priv;
-+	u8  initial_agc_speed_agc_decim;
-+	u8  initial_agc_speed_if_agc_speed;
-+	u16 initial_agc_speed_period;
-+	u8  agc_speed_agc_decim;
-+	u8  agc_speed_if_agc_speed;
-+	u16 initial_agc_speed_period_prop;
-+	u16 agc_speed_prop;
-+
-+	SiTRACE("%s(): FEF=%d\n", __func__, fef);
-+
-+#ifdef L1_RF_TER_TUNER_FEF_MODE_FREEZE_PIN_SETUP
-+	if (priv->fef_mode == Si2177_FEF_MODE_FREEZE_PIN) {
-+		SiTRACE("FEF mode Si2168B_FEF_MODE_FREEZE_PIN\n");
-+		initial_agc_speed_agc_decim    = Si2158_DTV_INITIAL_AGC_SPEED_PROP_AGC_DECIM_OFF;
-+		initial_agc_speed_if_agc_speed = Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_AUTO;
-+		initial_agc_speed_period       = 0;
-+		agc_speed_agc_decim            = Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_OFF;
-+		agc_speed_if_agc_speed         = Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_AUTO;
-+		//Si2158_L1_SendCommand2(&priv->tuner, Si2158_CONFIG_PINS_CMD_CODE);
-+		silabs_tercab_config_pins (&priv->tuner,
-+				Si2158_CONFIG_PINS_CMD_GPIO1_MODE_DISABLE,
-+				Si2158_CONFIG_PINS_CMD_GPIO1_READ_DO_NOT_READ,
-+				Si2158_CONFIG_PINS_CMD_GPIO2_MODE_DISABLE,
-+				Si2158_CONFIG_PINS_CMD_GPIO2_READ_DO_NOT_READ,
-+				Si2158_CONFIG_PINS_CMD_RESERVED1_RESERVED,
-+				Si2158_CONFIG_PINS_CMD_RESERVED2_RESERVED,
-+				Si2158_CONFIG_PINS_CMD_RESERVED3_RESERVED);
-+
-+		initial_agc_speed_period_prop = (initial_agc_speed_period & Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_PERIOD_MASK) << Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_PERIOD_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_CODE, initial_agc_speed_period_prop);
-+
-+		agc_speed_prop = (agc_speed_if_agc_speed & Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_MASK) << Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_LSB  |
-+			   (agc_speed_agc_decim & Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_MASK) << Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2158_DTV_AGC_SPEED_PROP_CODE, agc_speed_prop);
-+	}
-+#endif /* L1_RF_TER_TUNER_FEF_MODE_FREEZE_PIN_SETUP */
-+
-+#ifdef L1_RF_TER_TUNER_FEF_MODE_SLOW_INITIAL_AGC_SETUP
-+	if (priv->fef_mode == Si2177_FEF_MODE_SLOW_INITIAL_AGC) {
-+		SiTRACE("FEF mode Si2168B_FEF_MODE_SLOW_INITIAL_AGC (AGC slowed down after tuning)\n");
-+		if (fef == 0) {
-+			initial_agc_speed_agc_decim    = Si2158_DTV_INITIAL_AGC_SPEED_PROP_AGC_DECIM_OFF;
-+		    initial_agc_speed_if_agc_speed = Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_AUTO;
-+		    initial_agc_speed_period       = 0;
-+		    agc_speed_agc_decim            = Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_OFF;
-+		    agc_speed_if_agc_speed         = Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_AUTO;
-+		} else {
-+			initial_agc_speed_agc_decim    = Si2158_DTV_INITIAL_AGC_SPEED_PROP_AGC_DECIM_OFF;
-+			initial_agc_speed_if_agc_speed = Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_AUTO;
-+			initial_agc_speed_period       = 240;
-+			agc_speed_agc_decim            = Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_4;
-+			agc_speed_if_agc_speed         = Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_39;
-+		}
-+		initial_agc_speed_period_prop = (initial_agc_speed_period & Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_PERIOD_MASK) << Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_PERIOD_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_CODE, initial_agc_speed_period_prop);
-+
-+		agc_speed_prop = (agc_speed_if_agc_speed & Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_MASK) << Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_LSB  |
-+			   (agc_speed_agc_decim    & Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_MASK   ) << Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2158_DTV_AGC_SPEED_PROP_CODE, agc_speed_prop);
-+	}
-+#endif /* L1_RF_TER_TUNER_FEF_MODE_SLOW_INITIAL_AGC_SETUP */
-+
-+#ifdef L1_RF_TER_TUNER_FEF_MODE_SLOW_NORMAL_AGC_SETUP
-+	if (priv->fef_mode == Si2177_FEF_MODE_SLOW_NORMAL_AGC ) {
-+		SiTRACE("FEF mode Si2168B_FEF_MODE_SLOW_NORMAL_AGC: AGC slowed down\n");
-+		initial_agc_speed_period = 0;
-+		if (fef == 0) {
-+			agc_speed_agc_decim    = Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_OFF;
-+			agc_speed_if_agc_speed = Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_AUTO;
-+		} else {
-+			agc_speed_if_agc_speed = Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_39;
-+			agc_speed_agc_decim    = Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_4;
-+		}
-+		initial_agc_speed_period_prop = (initial_agc_speed_period & Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_PERIOD_MASK) << Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_PERIOD_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_CODE, initial_agc_speed_period_prop);
-+
-+		agc_speed_prop = (agc_speed_if_agc_speed & Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_MASK) << Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_LSB  |
-+			   (agc_speed_agc_decim & Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_MASK) << Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2158_DTV_AGC_SPEED_PROP_CODE, agc_speed_prop);
-+	}
-+#endif /* L1_RF_TER_TUNER_FEF_MODE_SLOW_NORMAL_AGC */
-+
-+	silabs_tercab_fef(fe, fef);
-+
-+	SiTRACE("%s done\n", __func__);
-+	return 1;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2158_TUNER_TUNE_FREQ COMMAND                  */
-+/*---------------------------------------------------*/
-+static u8 silabs_tercab_tune_freq(silabs_tercab_context *ctx, u8  mode, u32 freq)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[8];
-+	u8 rspByteBuffer[1];
-+
-+	SiTRACE("%s()\n", __func__);
-+
-+	cmdByteBuffer[0] = Si2158_TUNER_TUNE_FREQ_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( mode & Si2158_TUNER_TUNE_FREQ_CMD_MODE_MASK ) << Si2158_TUNER_TUNE_FREQ_CMD_MODE_LSB);
-+	cmdByteBuffer[2] = (u8) 0x00;
-+	cmdByteBuffer[3] = (u8) 0x00;
-+	cmdByteBuffer[4] = (u8) ( ( freq & Si2158_TUNER_TUNE_FREQ_CMD_FREQ_MASK ) << Si2158_TUNER_TUNE_FREQ_CMD_FREQ_LSB);
-+	cmdByteBuffer[5] = (u8) ((( freq & Si2158_TUNER_TUNE_FREQ_CMD_FREQ_MASK ) << Si2158_TUNER_TUNE_FREQ_CMD_FREQ_LSB) >> 8);
-+	cmdByteBuffer[6] = (u8) ((( freq & Si2158_TUNER_TUNE_FREQ_CMD_FREQ_MASK ) << Si2158_TUNER_TUNE_FREQ_CMD_FREQ_LSB) >> 16);
-+	cmdByteBuffer[7] = (u8) ((( freq & Si2158_TUNER_TUNE_FREQ_CMD_FREQ_MASK ) << Si2158_TUNER_TUNE_FREQ_CMD_FREQ_LSB) >> 24);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 8, cmdByteBuffer) != 8) {
-+		SiTRACE("Error writing TUNER_TUNE_FREQ bytes!\n");
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	error_code = silabs_tercab_poll_response(ctx->i2c_adap, ctx->i2c_addr, 1, rspByteBuffer, &ctx->status);
-+	if (error_code) {
-+		SiTRACE("Error polling TUNER_TUNE_FREQ response\n");
-+		return error_code;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+/************************************************************************************************************************
-+ NAME: Si2158_Tune
-+ DESCRIPTIION: Tune Si2158 in specified mode (ATV/DTV) at center frequency, wait for TUNINT and xTVINT with timeout
-+
-+ Parameter:  Pointer to Si2158 Context (I2C address)
-+ Parameter:  Mode (ATV or DTV) use Si2158_TUNER_TUNE_FREQ_CMD_MODE_ATV or Si2158_TUNER_TUNE_FREQ_CMD_MODE_DTV constants
-+ Parameter:  frequency (Hz) as a u32 integer
-+ Returns:    0 if channel found.  A nonzero value means either an error occurred or channel not locked.
-+ Programming Guide Reference:    Flowchart A.7 (Tune flowchart)
-+ ************************************************************************************************************************/
-+static int silabs_tercab_tune(silabs_tercab_context *ctx, u8 mode, u32 freq)
-+{
-+	unsigned int start_time  = 0;
-+	int return_code = 0;
-+	unsigned int timeout = 40;//FGR allow for PC clock granularity
-+
-+	if (silabs_tercab_tune_freq(ctx, mode, freq) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	start_time = jiffies_to_msecs(jiffies);
-+
-+	/* wait for TUNINT, timeout is 36ms */
-+	while ( (jiffies_to_msecs(jiffies) - start_time) < timeout )
-+	{
-+		if ((return_code = silabs_tercab_check_status(ctx)) != NO_SILABS_TERCAB_ERROR)
-+			return return_code;
-+		if (ctx->status.tunint)
-+			break;
-+        msleep(5);
-+	}
-+	if (!ctx->status.tunint) {
-+		SiTRACE("Timeout waiting for TUNINT\n");
-+		return ERROR_SILABS_TERCAB_TUNINT_TIMEOUT;
-+	}
-+
-+	/* wait for xTVINT, timeout is 150ms for ATVINT and 10 ms for DTVINT */
-+	start_time = jiffies_to_msecs(jiffies);
-+	timeout    = ((mode==Si2158_TUNER_TUNE_FREQ_CMD_MODE_ATV) ? 300 : 100);//FGR allow for PC clock granularity
-+	while ( (jiffies_to_msecs(jiffies) - start_time) < timeout )
-+	{
-+		if ((return_code = silabs_tercab_check_status(ctx)) != NO_SILABS_TERCAB_ERROR)
-+			return return_code;
-+		if (mode == Si2158_TUNER_TUNE_FREQ_CMD_MODE_ATV) {
-+			if (ctx->status.atvint)
-+				break;
-+		} else {
-+			if (ctx->status.dtvint)
-+				break;
-+		}
-+        msleep(5);
-+	}
-+
-+	if (mode == Si2158_TUNER_TUNE_FREQ_CMD_MODE_ATV) {
-+		if (ctx->status.atvint) {
-+			SiTRACE("ATV Tune Successful\n");
-+			return NO_SILABS_TERCAB_ERROR;
-+		} else {
-+			SiTRACE("Timeout waiting for ATVINT\n");
-+		}
-+	} else {
-+		if (ctx->status.dtvint) {
-+			SiTRACE("DTV Tune Successful\n");
-+			return NO_SILABS_TERCAB_ERROR;
-+		} else {
-+			SiTRACE("Timeout waiting for DTVINT\n");
-+		}
-+	}
-+
-+	return ERROR_SILABS_TERCAB_xTVINT_TIMEOUT;
-+}
-+
-+/************************************************************************************************************************
-+ NAME: silabs_tercab_dtv_tune
-+ DESCRIPTION: Update DTV_MODE and tune DTV mode at center frequency
-+ Parameter:  Pointer to Si2158 Context (I2C address)
-+ Parameter:  frequency (Hz)
-+ Parameter:  bandwidth , 6,7 or 8 MHz
-+ Parameter:  modulation,  e.g. use constant Si2158_DTV_MODE_PROP_MODULATION_DVBT for DVBT mode
-+ Parameter:  rsp - commandResp structure to returns tune status info.
-+ Returns:    I2C transaction error code, 0 if successful
-+ Programming Guide Reference:    Flowchart A.7 (Tune flowchart)
-+ ************************************************************************************************************************/
-+static int silabs_tercab_dtv_tune(silabs_tercab_context *ctx, u32 freq, u8 bw, u8 modulation, u8 invert_spectrum)
-+{
-+	u16 data;
-+
-+	/* update DTV_MODE_PROP property */
-+	data = (bw              & Si2158_DTV_MODE_PROP_BW_MASK             ) << Si2158_DTV_MODE_PROP_BW_LSB  |
-+		   (modulation      & Si2158_DTV_MODE_PROP_MODULATION_MASK     ) << Si2158_DTV_MODE_PROP_MODULATION_LSB  |
-+		   (invert_spectrum & Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_MASK) << Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_LSB ;
-+	if (silabs_tercab_set_property(ctx, Si2158_DTV_MODE_PROP_CODE, data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	return silabs_tercab_tune(ctx, Si2158_TUNER_TUNE_FREQ_CMD_MODE_DTV, freq);
-+}
-+
-+/* ------------------------------------------------------------------ */
-+#if 0
-+/*---------------------------------------------------*/
-+/* Si2177_GET_PROPERTY COMMAND                     */
-+/*---------------------------------------------------*/
-+static u8 silabs_tercab_get_property(silabs_tercab_context *ctx, u16 prop, u16 *data)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[4];
-+	u8 rspByteBuffer[4];
-+	u8 reserved = 0;
-+
-+	SiTRACE("Si2177 GET_PROPERTY\n");
-+
-+	cmdByteBuffer[0] = Si2158_GET_PROPERTY_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( reserved & Si2158_GET_PROPERTY_CMD_RESERVED_MASK ) << Si2158_GET_PROPERTY_CMD_RESERVED_LSB);
-+	cmdByteBuffer[2] = (u8) ( ( prop     & Si2158_GET_PROPERTY_CMD_PROP_MASK     ) << Si2158_GET_PROPERTY_CMD_PROP_LSB    );
-+	cmdByteBuffer[3] = (u8) ((( prop     & Si2158_GET_PROPERTY_CMD_PROP_MASK     ) << Si2158_GET_PROPERTY_CMD_PROP_LSB    )>>8);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 4, cmdByteBuffer) != 4) {
-+		SiTRACE("Error writing GET_PROPERTY bytes!\n");
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	error_code = silabs_tercab_poll_response(ctx->i2c_adap, ctx->i2c_addr, 4, rspByteBuffer, &ctx->status);
-+	if (error_code) {
-+		SiTRACE("Error polling SET_PROPERTY response\n");
-+		return error_code;
-+	}
-+
-+	reserved =   (( ( (rspByteBuffer[1]  )) >> Si2158_GET_PROPERTY_RESPONSE_RESERVED_LSB ) & Si2158_GET_PROPERTY_RESPONSE_RESERVED_MASK );
-+	*data    =   (( ( (rspByteBuffer[2]  ) | (rspByteBuffer[3]  << 8 )) >> Si2158_GET_PROPERTY_RESPONSE_DATA_LSB     ) & Si2158_GET_PROPERTY_RESPONSE_DATA_MASK     );
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+#endif
-+
-+static int silabs_tercab_set_params(struct dvb_frontend *fe)
-+{
-+	struct silabs_tercab_priv *priv = fe->tuner_priv;
-+	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
-+	u32 freq          = c->frequency;
-+	u8 bw             = c->bandwidth_hz/1000000;
-+	u8 modulation     = Si2158_DTV_MODE_PROP_MODULATION_DEFAULT;
-+	u8 invert_signal  = Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_DEFAULT;
-+	u16 if_freq       = Si2158_DTV_LIF_FREQ_PROP_OFFSET_DEFAULT;
-+	u8 lif_out_offset = 148; /* (default   148) */
-+	u8 lif_out_amp    = Si2158_DTV_LIF_OUT_PROP_AMP_DEFAULT;
-+	int res, ret=0;
-+	u16 data;
-+
-+	silabs_tercab_dbg("delivery system=%u\n", (u32)c->delivery_system);
-+	silabs_tercab_dbg("frequency=%u\n", c->frequency);
-+	silabs_tercab_dbg("modulation=%u\n", (u32)c->modulation);
-+	silabs_tercab_dbg("inversion=%u\n", (u32)c->inversion);
-+	silabs_tercab_dbg("bandwidth=%u (%u MHz)\n", c->bandwidth_hz, bw);
-+
-+	priv->mode = SILABS_TERCAB_DIGITAL;
-+
-+	switch(c->inversion) {
-+	case INVERSION_OFF:  invert_signal = Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_NORMAL;   break;
-+	case INVERSION_ON:   invert_signal = Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_INVERTED; break;
-+	case INVERSION_AUTO:
-+		silabs_tercab_dbg("inversion AUTO not supported!\n");
-+		/* return -EINVAL; */
-+		/* fall through */
-+	default:
-+		break;
-+	}
-+
-+	switch (c->delivery_system) {
-+	case SYS_ATSC:
-+		invert_signal = Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_INVERTED;
-+		modulation = Si2158_DTV_MODE_PROP_MODULATION_ATSC;
-+		if_freq = priv->vsb_if_khz;
-+		bw = 6; /* always use 6 MHz bandwidth */
-+		break;
-+	case SYS_ISDBT:
-+	case SYS_DVBT:
-+	case SYS_DVBT2:
-+		modulation = Si2158_DTV_MODE_PROP_MODULATION_DVBT;
-+		lif_out_amp = 32;
-+		break;
-+	case SYS_DVBC_ANNEX_B:
-+		invert_signal = Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_NORMAL;
-+		modulation = Si2158_DTV_MODE_PROP_MODULATION_QAM_US;
-+		if_freq = priv->qam_if_khz;
-+		bw = 6; /* always use 6 MHz bandwidth */
-+		break;
-+	case SYS_DVBC_ANNEX_A:
-+	case SYS_DVBC_ANNEX_C:
-+		modulation = Si2158_DTV_MODE_PROP_MODULATION_DVBC;
-+		lif_out_amp = 43;
-+		//invert_signal = Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_INVERTED;
-+		bw = 8; /* always use 8 MHz bandwidth */
-+		break;
-+	default:
-+		silabs_tercab_warn("modulation type not supported!\n");
-+		return -EINVAL;
-+	}
-+
-+	/* When tuning digital, the analog demod must be tri-stated */
-+	if (fe->ops.analog_ops.standby)
-+		fe->ops.analog_ops.standby(fe);
-+
-+	mutex_lock(&priv->lock);
-+
-+	SiTRACE("Wakeup terrestrial tuner\n");
-+	res= silabs_tercab_poll_cts(priv->i2c_props.adap, priv->i2c_props.addr);
-+	if (res != NO_SILABS_TERCAB_ERROR) {
-+		silabs_tercab_err("tuner Si2177 wake up failed.\n");
-+		SiTRACE("Terrestrial tuner wake up error: 0x%02x : %s\n",res, silabs_tercab_error_text(res) );
-+		ret = -EIO;
-+		goto fail;
-+	}
-+
-+	switch (priv->tuner.part) {
-+	case 57:
-+		if (!priv->firmware_started) {
-+			if (silabs_tercab_power_up_with_patch(priv) == NO_SILABS_TERCAB_ERROR) {
-+				priv->firmware_started = 1;
-+			} else {
-+				silabs_tercab_err("%s(): ERROR: Si2177_PowerUpWithPatch() failed\n", __func__);
-+			}
-+		}
-+		break;
-+	case 77:
-+	default:
-+		break;
-+	}
-+
-+	/* ------------------------------------------------------------ */
-+	/* Manage FEF mode in TER tuner                                 */
-+	/* ------------------------------------------------------------ */
-+	if (c->delivery_system == SYS_DVBT2) {
-+		silabs_tercab_fef_setup(fe, 1);
-+	} else {
-+		silabs_tercab_fef_setup(fe, 0);
-+	}
-+
-+	data = (lif_out_offset & Si2158_DTV_LIF_OUT_PROP_OFFSET_MASK) << Si2158_DTV_LIF_OUT_PROP_OFFSET_LSB  |
-+		   (lif_out_amp    & Si2158_DTV_LIF_OUT_PROP_AMP_MASK   ) << Si2158_DTV_LIF_OUT_PROP_AMP_LSB ;
-+	silabs_tercab_set_property(&priv->tuner, Si2158_DTV_LIF_OUT_PROP_CODE, data);
-+
-+	//Set IF Center freq
-+	data = (if_freq & Si2158_DTV_LIF_FREQ_PROP_OFFSET_MASK) << Si2158_DTV_LIF_FREQ_PROP_OFFSET_LSB ;
-+	silabs_tercab_set_property(&priv->tuner, Si2158_DTV_LIF_FREQ_PROP_CODE, data);
-+
-+	silabs_tercab_dbg("silabs_tercab_dtv_tune( , %u, %u, %u, %u) (IF=%u kHz)\n", freq, bw, modulation, invert_signal, if_freq);
-+	res = silabs_tercab_dtv_tune(&priv->tuner, freq, bw, modulation, invert_signal);
-+	msleep(85);
-+	if (c->delivery_system == SYS_DVBT2) {
-+		silabs_tercab_fef(fe, 1);
-+	}
-+
-+	if (res != NO_SILABS_TERCAB_ERROR) {
-+		silabs_tercab_err("silabs_tercab_dtv_tune() failed.\n");
-+		SiTRACE("silabs_tercab_dtv_tune() failed. Error: 0x%02x : %s\n", res, silabs_tercab_error_text(res));
-+		ret = -EIO;
-+		goto fail;
-+	}
-+
-+	priv->frequency    = freq;
-+	priv->if_frequency = 1000 * if_freq;
-+	priv->bandwidth    = 1000000 * bw;
-+
-+fail:
-+	mutex_unlock(&priv->lock);
-+	return ret;
-+}
-+
-+/************************************************************************************************************************
-+ NAME: silabs_tercab_atv_tune
-+ DESCRIPTION:Update ATV_VIDEO_MODE and tune ATV mode at center frequency
-+ Parameter:  Pointer to Si2158 Context (I2C address)
-+ Parameter:  frequency (Hz)
-+ Parameter:  Video system , e.g. use constant Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_M for system M
-+ Parameter:  transport,  e.g. use constant Si2158_ATV_VIDEO_MODE_PROP_TRANS_TERRESTRIAL for terrestrial
-+ Parameter:  color , e.g. use constant Si2158_ATV_VIDEO_MODE_PROP_COLOR_PAL_NTSC for PAL or NTSC
-+ Parameter:  invert_signal, 0= normal, 1= inverted
-+ Parameter:  rsp - commandResp structure to returns tune status info.
-+ Returns:    I2C transaction error code, 0 if successful
-+ Programming Guide Reference:    Flowchart A.7 (Tune flowchart)
-+ ************************************************************************************************************************/
-+static int silabs_tercab_atv_tune(silabs_tercab_context *ctx, u32 freq, u8 video_sys, u8 color, u8 invert_spectrum)
-+{
-+	Si2158_ATV_VIDEO_MODE_PROP_struct atv_video_mode;
-+	u16 data;
-+
-+	/* update ATV_VIDEO_MODE property */
-+	atv_video_mode.video_sys       = video_sys;
-+	atv_video_mode.color           = color;
-+	atv_video_mode.invert_spectrum = invert_spectrum;
-+	switch (ctx->part) {
-+	case 57:
-+		data = (atv_video_mode.video_sys       & Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_MASK      ) << Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_LSB  |
-+		       (atv_video_mode.color           & Si2158_ATV_VIDEO_MODE_PROP_COLOR_MASK          ) << Si2158_ATV_VIDEO_MODE_PROP_COLOR_LSB  |
-+		       (atv_video_mode.invert_spectrum & Si2158_ATV_VIDEO_MODE_PROP_INVERT_SPECTRUM_MASK) << Si2158_ATV_VIDEO_MODE_PROP_INVERT_SPECTRUM_LSB;
-+		break;
-+	case 77:
-+		data = (atv_video_mode.video_sys       & Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_MASK    ) << Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_LSB  |
-+		       (atv_video_mode.color           & Si2158_ATV_VIDEO_MODE_PROP_COLOR_MASK        ) << Si2158_ATV_VIDEO_MODE_PROP_COLOR_LSB  |
-+		       (atv_video_mode.invert_spectrum & Si2177_ATV_VIDEO_MODE_PROP_INVERT_SIGNAL_MASK) << Si2177_ATV_VIDEO_MODE_PROP_INVERT_SIGNAL_LSB;
-+		break;
-+	default:
-+		pr_warn("%s(): unsupported tuner model Si21%02u\n", __func__, ctx->part);
-+		return ERROR_SILABS_TERCAB_INCOMPATIBLE_PART;
-+	}
-+	if (silabs_tercab_set_property(ctx, Si2158_ATV_VIDEO_MODE_PROP_CODE, data) != NO_SILABS_TERCAB_ERROR) {
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	return silabs_tercab_tune(ctx, Si2158_TUNER_TUNE_FREQ_CMD_MODE_ATV, freq);
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2158_ATV_STATUS COMMAND                       */
-+/*---------------------------------------------------*/
-+static u8 silabs_tercab_atv_status(struct silabs_tercab_priv *priv, u8 intack)
-+{
-+	silabs_tercab_context *ctx = &priv->tuner;
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[12]; /* Si2177 */
-+
-+	ctx->rsp.atv_status.STATUS = &ctx->status;
-+
-+	SiTRACE("%s()\n", __func__);
-+
-+	cmdByteBuffer[0] = Si2158_ATV_STATUS_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( intack & Si2158_ATV_STATUS_CMD_INTACK_MASK ) << Si2158_ATV_STATUS_CMD_INTACK_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing ATV_STATUS bytes!\n");
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	error_code = silabs_tercab_poll_response(ctx->i2c_adap, ctx->i2c_addr, sizeof(rspByteBuffer), rspByteBuffer, &ctx->status);
-+	if (error_code) {
-+		SiTRACE("Error polling ATV_STATUS response\n");
-+		return error_code;
-+	}
-+
-+	ctx->rsp.atv_status.chlint    = (rspByteBuffer[1] >> Si2158_ATV_STATUS_RESPONSE_CHLINT_LSB)    & Si2158_ATV_STATUS_RESPONSE_CHLINT_MASK;
-+	ctx->rsp.atv_status.pclint    = (rspByteBuffer[1] >> Si2158_ATV_STATUS_RESPONSE_PCLINT_LSB)    & Si2158_ATV_STATUS_RESPONSE_PCLINT_MASK;
-+	ctx->rsp.atv_status.chl       = (rspByteBuffer[2] >> Si2158_ATV_STATUS_RESPONSE_CHL_LSB)       & Si2158_ATV_STATUS_RESPONSE_CHL_MASK;
-+	ctx->rsp.atv_status.pcl       = (rspByteBuffer[2] >> Si2158_ATV_STATUS_RESPONSE_PCL_LSB)       & Si2158_ATV_STATUS_RESPONSE_PCL_MASK;
-+	ctx->rsp.atv_status.afc_freq  = (((((rspByteBuffer[4] | (rspByteBuffer[5] << 8)) >> Si2158_ATV_STATUS_RESPONSE_AFC_FREQ_LSB) & Si2158_ATV_STATUS_RESPONSE_AFC_FREQ_MASK) << Si2158_ATV_STATUS_RESPONSE_AFC_FREQ_SHIFT) >> Si2158_ATV_STATUS_RESPONSE_AFC_FREQ_SHIFT);
-+	ctx->rsp.atv_status.video_sys = (rspByteBuffer[8] >> Si2158_ATV_STATUS_RESPONSE_VIDEO_SYS_LSB) & Si2158_ATV_STATUS_RESPONSE_VIDEO_SYS_MASK;
-+	ctx->rsp.atv_status.color     = (rspByteBuffer[8] >> Si2158_ATV_STATUS_RESPONSE_COLOR_LSB)     & Si2158_ATV_STATUS_RESPONSE_COLOR_MASK;
-+
-+	switch (priv->tuner.part) {
-+	case 57:
-+		break;
-+	case 77:
-+		ctx->rsp.atv_status.dlint            = (rspByteBuffer[1]  >> Si2177_ATV_STATUS_RESPONSE_DLINT_LSB    ) & Si2177_ATV_STATUS_RESPONSE_DLINT_MASK;
-+		ctx->rsp.atv_status.snrlint          = (rspByteBuffer[1]  >> Si2177_ATV_STATUS_RESPONSE_SNRLINT_LSB  ) & Si2177_ATV_STATUS_RESPONSE_SNRLINT_MASK;
-+		ctx->rsp.atv_status.snrhint          = (rspByteBuffer[1]  >> Si2177_ATV_STATUS_RESPONSE_SNRHINT_LSB  ) & Si2177_ATV_STATUS_RESPONSE_SNRHINT_MASK;
-+		ctx->rsp.atv_status.dl               = (rspByteBuffer[2]  >> Si2177_ATV_STATUS_RESPONSE_DL_LSB       ) & Si2177_ATV_STATUS_RESPONSE_DL_MASK;
-+		ctx->rsp.atv_status.snrl             = (rspByteBuffer[2]  >> Si2177_ATV_STATUS_RESPONSE_SNRL_LSB     ) & Si2177_ATV_STATUS_RESPONSE_SNRL_MASK;
-+		ctx->rsp.atv_status.snrh             = (rspByteBuffer[2]  >> Si2177_ATV_STATUS_RESPONSE_SNRH_LSB     ) & Si2177_ATV_STATUS_RESPONSE_SNRH_MASK;
-+		ctx->rsp.atv_status.video_snr        = (rspByteBuffer[3]  >> Si2177_ATV_STATUS_RESPONSE_VIDEO_SNR_LSB) & Si2177_ATV_STATUS_RESPONSE_VIDEO_SNR_MASK;
-+		ctx->rsp.atv_status.video_sc_spacing = (((((rspByteBuffer[6] | (rspByteBuffer[7] << 8)) >> Si2177_ATV_STATUS_RESPONSE_VIDEO_SC_SPACING_LSB) & Si2177_ATV_STATUS_RESPONSE_VIDEO_SC_SPACING_MASK) << Si2177_ATV_STATUS_RESPONSE_VIDEO_SC_SPACING_SHIFT) >> Si2177_ATV_STATUS_RESPONSE_VIDEO_SC_SPACING_SHIFT);
-+		ctx->rsp.atv_status.lines            = (rspByteBuffer[8]  >> Si2177_ATV_STATUS_RESPONSE_LINES_LSB           ) & Si2177_ATV_STATUS_RESPONSE_LINES_MASK;
-+		ctx->rsp.atv_status.audio_sys        = (rspByteBuffer[9]  >> Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_LSB       ) & Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_MASK;
-+		ctx->rsp.atv_status.audio_demod_mode = (rspByteBuffer[9]  >> Si2177_ATV_STATUS_RESPONSE_AUDIO_DEMOD_MODE_LSB) & Si2177_ATV_STATUS_RESPONSE_AUDIO_DEMOD_MODE_MASK;
-+		ctx->rsp.atv_status.audio_chan_bw    = (rspByteBuffer[10] >> Si2177_ATV_STATUS_RESPONSE_AUDIO_CHAN_BW_LSB   ) & Si2177_ATV_STATUS_RESPONSE_AUDIO_CHAN_BW_MASK;
-+		ctx->rsp.atv_status.sound_level      = ((((rspByteBuffer[11] >> Si2177_ATV_STATUS_RESPONSE_SOUND_LEVEL_LSB ) & Si2177_ATV_STATUS_RESPONSE_SOUND_LEVEL_MASK) << Si2177_ATV_STATUS_RESPONSE_SOUND_LEVEL_SHIFT) >> Si2177_ATV_STATUS_RESPONSE_SOUND_LEVEL_SHIFT);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+static int silabs_tercab_set_analog_params(struct dvb_frontend *fe, struct analog_parameters *params)
-+{
-+	struct silabs_tercab_priv *priv = fe->tuner_priv;
-+	int res, ret     = 0;
-+	u32 freq         = params->frequency * 125 * ((params->mode == V4L2_TUNER_RADIO) ? 1 : 1000) / 2;
-+	u32 centerfreq   = 0;
-+	u32 if_frequency = 5400000;
-+	u32 bw           = 8000000;
-+	u8 video_sys     = Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_DEFAULT;
-+	u8 color         = Si2158_ATV_VIDEO_MODE_PROP_COLOR_DEFAULT;
-+	u8 invert_signal = Si2158_ATV_VIDEO_MODE_PROP_INVERT_SPECTRUM_DEFAULT;
-+
-+	const u16 atv_afc_range_khz    =  1000; //1500;
-+	const u8  tuner_ien_tcien     =  Si2158_TUNER_IEN_PROP_TCIEN_ENABLE;
-+	const u8  tuner_ien_rssilien  =  Si2158_TUNER_IEN_PROP_RSSILIEN_DISABLE;
-+	const u8  tuner_ien_rssihien  =  Si2158_TUNER_IEN_PROP_RSSIHIEN_DISABLE;
-+	const u8  atv_agc_speed_if_agc_speed = Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_AUTO;
-+	const u8  atv_lif_out_amp = 100; /* (default    100) */
-+	const u8  atv_lif_out_offset = 148; /* (default   148) */
-+	const s8  atv_rsq_rssi_threshold_hi = 0;
-+	const s8  atv_rsq_rssi_threshold_lo = -70;
-+	const u8  atv_ien_chlien    =  Si2158_ATV_IEN_PROP_CHLIEN_ENABLE;
-+	const u8  atv_ien_pclien    =  Si2158_ATV_IEN_PROP_PCLIEN_DISABLE;
-+	const u8  atv_config_if_port_atv_agc_source = Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_AGC_SOURCE_AGC2_3DB;
-+	const u8  atv_config_if_port_atv_out_type_58 = Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_LIF_DIFF_IF1;
-+
-+	/* Si2177 */
-+	const u8  atv_config_if_port_atv_out_type_77 = Si2177_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_CVBS_IF2B_SOUND_IF2A;
-+	const u8  atv_sif_out_amp = 60; /* 77 (default 60) */
-+	const u8  atv_sif_out_offset = 135;  /* 77 (default 135) */
-+	const u8  atv_cvbs_out_amp = 200; /* 77 (default 200) */
-+	const u8  atv_cvbs_out_offset = 25;  /* 77 (default 25) */
-+	const u8  atv_cvbs_out_fine_amp = 100; /* 77 (default 100) */
-+	const s8  atv_cvbs_out_fine_offset = 0;  /* 77 (default 0) */
-+	const s8  atv_video_equalizer_slope = 0;  /* 77 (default 0) */
-+	const u8  atv_rsq_snr_threshold_hi = Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_HI_DEFAULT;// 77 45 maxSNRHalfdB;
-+	const u8  atv_rsq_snr_threshold_lo = Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_LO_DEFAULT;// 77 25 minSNRHalfdB;
-+	const u8  atv_ien_dlien     =  Si2177_ATV_IEN_PROP_DLIEN_DISABLE;
-+	const u8  atv_ien_snrhien   =  Si2177_ATV_IEN_PROP_SNRHIEN_DISABLE;
-+	const u8  atv_ien_snrlien   =  Si2177_ATV_IEN_PROP_SNRLIEN_DISABLE;
-+	const u8  atv_audio_mode_audio_sys  = Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_DEFAULT;
-+	const u8  atv_audio_mode_chan_bw    = Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_DEFAULT;
-+	const u8  atv_audio_mode_demod_mode = Si2177_ATV_AUDIO_MODE_PROP_DEMOD_MODE_SIF;
-+	const u8  atv_ext_agc_min_10mv = 50; // 58 (default  50)
-+	const u8  atv_ext_agc_max_10mv = 200; // 58 (default 200)
-+
-+	u16 lif_freq_offset;
-+
-+	u16 si2158_atv_agc_speed_prop_data;
-+	u16 si2158_atv_lif_out_prop_data;
-+	u16 si2158_atv_lif_freq_prop_data;
-+	u16 si2158_atv_config_if_port_prop_data;
-+	u16 si2177_atv_config_if_port_prop_data;
-+	u16 si2177_atv_sif_out_prop_data;
-+	u16 si2177_atv_cvbs_out_prop_data;
-+	u16 si2177_atv_cvbs_out_fine_prop_data;
-+	u16 si2177_atv_video_equalizer_prop_data;
-+	u16 si2158_atv_ext_agc_prop_data;
-+	u16 si2158_atv_rsq_rssi_threshold_prop_data;
-+	u16 si2177_atv_rsq_snr_threshold_prop_data;
-+	u16 si2158_tuner_ien__prop_data;
-+	u16 si2158_atv_ien_prop_data;
-+	u16 si2177_atv_ien_prop_data;
-+	u16 si2177_atv_audio_mode_prop_data;
-+	u16 si2158_atv_afc_range_prop_data;
-+
-+	silabs_tercab_dbg("freq = %d, video_sys = %u, color = %u\n", freq, video_sys, color);
-+
-+	priv->mode = SILABS_TERCAB_ANALOG;
-+
-+	if (params->mode == V4L2_TUNER_RADIO) {
-+		video_sys = Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_DEFAULT;
-+		silabs_tercab_warn("radio mode is not supported\n");
-+	} else if (params->std & (V4L2_STD_MN | V4L2_STD_NTSC_443)) {
-+		if_frequency = 5400000;  /*5.4MHz	*/
-+		bw = 6000000;
-+		video_sys = Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_M;
-+		silabs_tercab_info("using video_sys Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_M\n");
-+	} else if (params->std & V4L2_STD_B) {
-+		if_frequency = 6000000;  /*6.0MHz	*/
-+		bw = 7000000;
-+		video_sys = Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_B;
-+		silabs_tercab_info("using video_sys Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_B\n");
-+	} else if (params->std & (V4L2_STD_PAL_DK | V4L2_STD_SECAM_DK)){
-+		if_frequency = 6900000;  /*6.9MHz	*/
-+		bw = 8000000;
-+		video_sys = Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_DK;
-+	} else if (params->std & V4L2_STD_GH){
-+		if_frequency = 7100000;  /*7.1MHz	*/
-+		bw = 8000000;
-+		video_sys = Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_GH;
-+		silabs_tercab_info("using video_sys Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_GH\n");
-+	} else if (params->std & V4L2_STD_PAL_I){
-+		if_frequency = 7250000;  /*7.25MHz	*/
-+		bw = 8000000;
-+		video_sys = Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_I;
-+	} else if (params->std & V4L2_STD_SECAM_L){
-+		if_frequency = 6900000;  /*6.9MHz	*/
-+		bw = 8000000;
-+		video_sys = Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_L;
-+		color = Si2158_ATV_VIDEO_MODE_PROP_COLOR_SECAM;
-+	} else if (params->std & V4L2_STD_SECAM_LC){
-+		if_frequency = 1250000;  /*1.25MHz	*/
-+		bw = 7000000;
-+		video_sys = Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_LP; /* ToDo: lc == lp? */
-+		color = Si2158_ATV_VIDEO_MODE_PROP_COLOR_SECAM;
-+	} else {
-+		video_sys = Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_DEFAULT;
-+		silabs_tercab_warn("unsupported video system\n");
-+	}
-+
-+	mutex_lock(&priv->lock);
-+
-+	SiTRACE("Wakeup terrestrial tuner\n");
-+	res = silabs_tercab_poll_cts(priv->i2c_props.adap, priv->i2c_props.addr);
-+	if (res != NO_SILABS_TERCAB_ERROR) {
-+		silabs_tercab_err("tuner Si2158 wake up failed.\n");
-+		SiTRACE("Terrestrial tuner wake up error: 0x%02x : %s\n", res, silabs_tercab_error_text(res));
-+		ret = -EIO;
-+		goto fail;
-+	}
-+
-+	//Calc IF Center for given Video Carrier
-+	//uIF = if_frequency + 1250000 - (bw/2);
-+	//invert_signal = Si2177_ATV_VIDEO_MODE_PROP_INVERT_SPECTRUM_INVERTED;
-+
-+	//Set IF output level
-+	//dwValue = 100; //m_Config.uIFLEVEL;
-+
-+	switch (priv->tuner.part) {
-+	case 57:
-+		silabs_tercab_info("%s(): initializing tuner type Si21%02u\n", __func__, priv->tuner.part);
-+
-+		if (!priv->firmware_started) {
-+			if (silabs_tercab_power_up_with_patch(priv) == NO_SILABS_TERCAB_ERROR) {
-+				priv->firmware_started = 1;
-+			} else {
-+				silabs_tercab_err("%s(): ERROR: Si2177_PowerUpWithPatch() failed\n", __func__);
-+			}
-+		}
-+		invert_signal = Si2158_ATV_VIDEO_MODE_PROP_INVERT_SPECTRUM_DEFAULT;
-+
-+		si2158_atv_agc_speed_prop_data = (atv_agc_speed_if_agc_speed & Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_MASK) << Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2158_ATV_AGC_SPEED_PROP_CODE, si2158_atv_agc_speed_prop_data); /* windows 0x0 */
-+
-+		si2158_atv_lif_out_prop_data = (atv_lif_out_offset & Si2158_ATV_LIF_OUT_PROP_OFFSET_MASK) << Si2158_ATV_LIF_OUT_PROP_OFFSET_LSB  |
-+			   (atv_lif_out_amp    & Si2158_ATV_LIF_OUT_PROP_AMP_MASK   ) << Si2158_ATV_LIF_OUT_PROP_AMP_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2158_ATV_LIF_OUT_PROP_CODE, si2158_atv_lif_out_prop_data); /* windows 0x6494 */
-+
-+		//Set IF Center freq
-+		lif_freq_offset = (u16)((if_frequency + 1250000 - (bw/2))/1000);
-+		silabs_tercab_info("atv_lif_freq.offset=%u uBW=%u video_sys=%u\n", lif_freq_offset, bw, video_sys);
-+		si2158_atv_lif_freq_prop_data = (lif_freq_offset & Si2158_ATV_LIF_FREQ_PROP_OFFSET_MASK) << Si2158_ATV_LIF_FREQ_PROP_OFFSET_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2158_ATV_LIF_FREQ_PROP_CODE, si2158_atv_lif_freq_prop_data); /* windows 0xe42 */
-+
-+		si2158_atv_config_if_port_prop_data = (atv_config_if_port_atv_out_type_58 & Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_MASK  ) << Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_LSB  |
-+			   (atv_config_if_port_atv_agc_source & Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_AGC_SOURCE_MASK) << Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_AGC_SOURCE_LSB ;
-+
-+		//atv_agc_source isn't really supported on si2177, but lets set it to a known value
-+		//atv_config_if_port_atv_agc_source = (u8)Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_AGC_SOURCE_INTERNAL;
-+
-+		silabs_tercab_set_property(&priv->tuner, Si2158_ATV_CONFIG_IF_PORT_PROP_CODE, si2158_atv_config_if_port_prop_data); /* windows 0x208 */
-+		break;
-+
-+	case 77:
-+		silabs_tercab_info("%s(): initializing tuner type Si21%02u\n", __func__, priv->tuner.part);
-+
-+		invert_signal = Si2177_ATV_VIDEO_MODE_PROP_INVERT_SIGNAL_DEFAULT;
-+
-+		si2177_atv_config_if_port_prop_data = (atv_config_if_port_atv_out_type_77 & Si2177_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_MASK) << Si2177_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2158_ATV_CONFIG_IF_PORT_PROP_CODE, si2177_atv_config_if_port_prop_data);
-+
-+		si2177_atv_sif_out_prop_data = (atv_sif_out_offset & Si2177_ATV_SIF_OUT_PROP_OFFSET_MASK) << Si2177_ATV_SIF_OUT_PROP_OFFSET_LSB  |
-+			   (atv_sif_out_amp    & Si2177_ATV_SIF_OUT_PROP_AMP_MASK   ) << Si2177_ATV_SIF_OUT_PROP_AMP_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2177_ATV_SIF_OUT_PROP_CODE, si2177_atv_sif_out_prop_data);
-+
-+		si2177_atv_cvbs_out_prop_data = (atv_cvbs_out_offset & Si2177_ATV_CVBS_OUT_PROP_OFFSET_MASK) << Si2177_ATV_CVBS_OUT_PROP_OFFSET_LSB  |
-+			   (atv_cvbs_out_amp    & Si2177_ATV_CVBS_OUT_PROP_AMP_MASK   ) << Si2177_ATV_CVBS_OUT_PROP_AMP_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2177_ATV_CVBS_OUT_PROP_CODE, si2177_atv_cvbs_out_prop_data);
-+
-+		si2177_atv_cvbs_out_fine_prop_data = (atv_cvbs_out_fine_offset & Si2177_ATV_CVBS_OUT_FINE_PROP_OFFSET_MASK) << Si2177_ATV_CVBS_OUT_FINE_PROP_OFFSET_LSB  |
-+			   (atv_cvbs_out_fine_amp    & Si2177_ATV_CVBS_OUT_FINE_PROP_AMP_MASK   ) << Si2177_ATV_CVBS_OUT_FINE_PROP_AMP_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2177_ATV_CVBS_OUT_FINE_PROP_CODE, si2177_atv_cvbs_out_fine_prop_data);
-+
-+		si2177_atv_video_equalizer_prop_data = (atv_video_equalizer_slope & Si2177_ATV_VIDEO_EQUALIZER_PROP_SLOPE_MASK) << Si2177_ATV_VIDEO_EQUALIZER_PROP_SLOPE_LSB ;
-+		silabs_tercab_set_property(&priv->tuner, Si2177_ATV_VIDEO_EQUALIZER_PROP_CODE, si2177_atv_video_equalizer_prop_data);
-+		break;
-+
-+	default:
-+		silabs_tercab_warn("%s(): unsupported tuner model Si21%02u\n", __func__, priv->tuner.part);
-+		break;
-+	}
-+
-+	if (priv->tuner.part != 77) {
-+		/* setup external AGC settings */
-+		si2158_atv_ext_agc_prop_data = (atv_ext_agc_min_10mv & Si2158_ATV_EXT_AGC_PROP_MIN_10MV_MASK) << Si2158_ATV_EXT_AGC_PROP_MIN_10MV_LSB  |
-+		   (atv_ext_agc_max_10mv & Si2158_ATV_EXT_AGC_PROP_MAX_10MV_MASK) << Si2158_ATV_EXT_AGC_PROP_MAX_10MV_LSB ;
-+		silabs_tercab_set_property (&priv->tuner, Si2158_ATV_EXT_AGC_PROP_CODE, si2158_atv_ext_agc_prop_data); /* windows 0xc832 */
-+	}
-+
-+	/* configure the RSQ / RSSI threshold properties */
-+	si2158_atv_rsq_rssi_threshold_prop_data = (atv_rsq_rssi_threshold_lo & Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_LO_MASK) << Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_LO_LSB  |
-+		   (atv_rsq_rssi_threshold_hi & Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_HI_MASK) << Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_HI_LSB ;
-+
-+	if (silabs_tercab_set_property(&priv->tuner, Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_CODE, si2158_atv_rsq_rssi_threshold_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		silabs_tercab_err("%s() silabs_tercab_set_property(Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_CODE) failed.\n", __func__);
-+		ret = -EIO;
-+		goto fail;
-+	}
-+
-+	if (priv->tuner.part == 77) { //Si2177
-+		/* configure the RSQ / SNR threshold properties */
-+		si2177_atv_rsq_snr_threshold_prop_data = (atv_rsq_snr_threshold_lo & Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_LO_MASK) << Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_LO_LSB  |
-+			   (atv_rsq_snr_threshold_hi & Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_HI_MASK) << Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_HI_LSB ;
-+		if (silabs_tercab_set_property(&priv->tuner, Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_CODE, si2177_atv_rsq_snr_threshold_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			silabs_tercab_warn("%s() silabs_tercab_set_property(Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_CODE) failed.\n", __func__);
-+		}
-+	}
-+
-+	/* setup IEN properties to enable TUNINT on TC  */
-+	si2158_tuner_ien__prop_data = (tuner_ien_tcien    & Si2158_TUNER_IEN_PROP_TCIEN_MASK   ) << Si2158_TUNER_IEN_PROP_TCIEN_LSB  |
-+		   (tuner_ien_rssilien & Si2158_TUNER_IEN_PROP_RSSILIEN_MASK) << Si2158_TUNER_IEN_PROP_RSSILIEN_LSB  |
-+		   (tuner_ien_rssihien & Si2158_TUNER_IEN_PROP_RSSIHIEN_MASK) << Si2158_TUNER_IEN_PROP_RSSIHIEN_LSB ;
-+	if (silabs_tercab_set_property(&priv->tuner, Si2158_TUNER_IEN_PROP_CODE, si2158_tuner_ien__prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		silabs_tercab_warn("%s() silabs_tercab_set_property(Si2158_TUNER_IEN_PROP_CODE) failed.\n", __func__);
-+	}
-+
-+	/* setup IEN properties to enable ATVINT on CHL  */
-+	if (priv->tuner.part == 77) { //Si2177
-+		si2177_atv_ien_prop_data = (atv_ien_chlien  & Si2158_ATV_IEN_PROP_CHLIEN_MASK ) << Si2158_ATV_IEN_PROP_CHLIEN_LSB  |
-+			   (atv_ien_pclien  & Si2158_ATV_IEN_PROP_PCLIEN_MASK ) << Si2158_ATV_IEN_PROP_PCLIEN_LSB  |
-+			   (atv_ien_dlien   & Si2177_ATV_IEN_PROP_DLIEN_MASK  ) << Si2177_ATV_IEN_PROP_DLIEN_LSB  |
-+			   (atv_ien_snrlien & Si2177_ATV_IEN_PROP_SNRLIEN_MASK) << Si2177_ATV_IEN_PROP_SNRLIEN_LSB  |
-+			   (atv_ien_snrhien & Si2177_ATV_IEN_PROP_SNRHIEN_MASK) << Si2177_ATV_IEN_PROP_SNRHIEN_LSB ;
-+		if (silabs_tercab_set_property(&priv->tuner, Si2158_ATV_IEN_PROP_CODE, si2177_atv_ien_prop_data) != NO_SILABS_TERCAB_ERROR) { /* windows 0x1 */
-+			silabs_tercab_warn("%s() silabs_tercab_set_property(Si2158_ATV_IEN_PROP_CODE) failed.\n", __func__);
-+		}
-+	} else {
-+		si2158_atv_ien_prop_data = (atv_ien_chlien  & Si2158_ATV_IEN_PROP_CHLIEN_MASK ) << Si2158_ATV_IEN_PROP_CHLIEN_LSB  |
-+			   (atv_ien_pclien  & Si2158_ATV_IEN_PROP_PCLIEN_MASK ) << Si2158_ATV_IEN_PROP_PCLIEN_LSB ;
-+		if (silabs_tercab_set_property(&priv->tuner, Si2158_ATV_IEN_PROP_CODE, si2158_atv_ien_prop_data) != NO_SILABS_TERCAB_ERROR) { /* windows 0x1 */
-+			silabs_tercab_warn("%s() silabs_tercab_set_property(Si2158_ATV_IEN_PROP_CODE) failed.\n", __func__);
-+		}
-+	}
-+	if (priv->tuner.part == 77) { //Si2177
-+		/* setup ATV audio property for wide SIF scanning*/
-+		si2177_atv_audio_mode_prop_data = (atv_audio_mode_audio_sys  & Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_MASK ) << Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_LSB  |
-+			   (atv_audio_mode_demod_mode & Si2177_ATV_AUDIO_MODE_PROP_DEMOD_MODE_MASK) << Si2177_ATV_AUDIO_MODE_PROP_DEMOD_MODE_LSB  |
-+			   (atv_audio_mode_chan_bw    & Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_MASK   ) << Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_LSB ;
-+		if (silabs_tercab_set_property(&priv->tuner, Si2177_ATV_AUDIO_MODE_PROP_CODE, si2177_atv_audio_mode_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+			silabs_tercab_warn("%s() silabs_tercab_set_property(Si2177_ATV_AUDIO_MODE_PROP_CODE) failed.\n", __func__);
-+		}
-+	}
-+	/* setup AFC acquisition range property to 1.5MHz for scanning */
-+	si2158_atv_afc_range_prop_data = (atv_afc_range_khz & Si2158_ATV_AFC_RANGE_PROP_RANGE_KHZ_MASK) << Si2158_ATV_AFC_RANGE_PROP_RANGE_KHZ_LSB ;
-+	if (silabs_tercab_set_property(&priv->tuner, Si2158_ATV_AFC_RANGE_PROP_CODE, si2158_atv_afc_range_prop_data) != NO_SILABS_TERCAB_ERROR) {
-+		silabs_tercab_warn("%s() silabs_tercab_set_property(Si2158_ATV_AFC_RANGE_PROP) failed.\n", __func__);
-+	}
-+
-+	centerfreq = freq - 1250000 + (bw/2);
-+
-+	//tune to channel center freq
-+	silabs_tercab_dbg("tuning to center frequency %u, video system %u, color %u, invert %u\n", centerfreq, video_sys, color, invert_signal);
-+
-+	res = silabs_tercab_atv_tune(&priv->tuner, centerfreq, video_sys, color, invert_signal);
-+	if (res == NO_SILABS_TERCAB_ERROR) {
-+		/* Get ATV status */
-+		if (silabs_tercab_atv_status (priv, Si2158_ATV_STATUS_CMD_INTACK_OK)) {
-+			silabs_tercab_err("%s() silabs_tercab_atv_status() failed.\n", __func__);
-+			ret = -EIO;
-+			goto fail;
-+		}
-+	} else {
-+		silabs_tercab_dbg("silabs_tercab_atv_tune(fe, %u, %u, %u, %u) failed (err=%d %s).\n",
-+				centerfreq, video_sys, color, invert_signal, res, silabs_tercab_error_text(res));
-+		ret = -EIO;
-+		goto fail;
-+	}
-+	msleep(85);
-+
-+	priv->frequency = freq;
-+	priv->if_frequency = if_frequency;
-+	priv->bandwidth = bw;
-+	ret = 0;
-+
-+fail:
-+	mutex_unlock(&priv->lock);
-+
-+	return ret;
-+}
-+
-+static void silabs_tercab_release(struct dvb_frontend *fe)
-+{
-+	struct silabs_tercab_priv *priv = fe->tuner_priv;
-+
-+	silabs_tercab_dbg("\n");
-+
-+	mutex_lock(&silabs_tercab_list_mutex);
-+
-+	if (priv)
-+		hybrid_tuner_release_state(priv);
-+
-+	mutex_unlock(&silabs_tercab_list_mutex);
-+
-+	fe->tuner_priv = NULL;
-+}
-+
-+static int silabs_tercab_get_frequency(struct dvb_frontend *fe, u32 *frequency)
-+{
-+	struct silabs_tercab_priv *priv = fe->tuner_priv;
-+	silabs_tercab_dbg("frequency=%u\n", priv->frequency);
-+	*frequency = priv->frequency;
-+	return 0;
-+}
-+
-+static int silabs_tercab_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
-+{
-+	struct silabs_tercab_priv *priv = fe->tuner_priv;
-+	silabs_tercab_dbg("bandwidth=%u\n", priv->bandwidth);
-+	*bandwidth = priv->bandwidth;
-+	return 0;
-+}
-+
-+static int silabs_tercab_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
-+{
-+	struct silabs_tercab_priv *priv = fe->tuner_priv;
-+	silabs_tercab_dbg("if_frequency=%u\n", priv->if_frequency);
-+	*frequency = (u32)priv->if_frequency;
-+	return 0;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2158_DTV_STATUS COMMAND                       */
-+/*---------------------------------------------------*/
-+static u8 silabs_tercab_dtv_status(silabs_tercab_context *ctx, u8 intack)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[4];
-+	ctx->rsp.dtv_status.STATUS = &ctx->status;
-+
-+	SiTRACE("%s()\n", __func__);
-+
-+	cmdByteBuffer[0] = Si2158_DTV_STATUS_CMD;
-+	cmdByteBuffer[1] = (u8)((intack & Si2158_DTV_STATUS_CMD_INTACK_MASK) << Si2158_DTV_STATUS_CMD_INTACK_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing DTV_STATUS bytes!\n");
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	error_code = silabs_tercab_poll_response(ctx->i2c_adap, ctx->i2c_addr, 4, rspByteBuffer, &ctx->status);
-+	if (error_code) {
-+		SiTRACE("Error polling DTV_STATUS response\n");
-+		return error_code;
-+	}
-+
-+	ctx->rsp.dtv_status.chlint     = (rspByteBuffer[1] >> Si2158_DTV_STATUS_RESPONSE_CHLINT_LSB    ) & Si2158_DTV_STATUS_RESPONSE_CHLINT_MASK;
-+	ctx->rsp.dtv_status.chl        = (rspByteBuffer[2] >> Si2158_DTV_STATUS_RESPONSE_CHL_LSB       ) & Si2158_DTV_STATUS_RESPONSE_CHL_MASK;
-+	ctx->rsp.dtv_status.bw         = (rspByteBuffer[3] >> Si2158_DTV_STATUS_RESPONSE_BW_LSB        ) & Si2158_DTV_STATUS_RESPONSE_BW_MASK;
-+	ctx->rsp.dtv_status.modulation = (rspByteBuffer[3] >> Si2158_DTV_STATUS_RESPONSE_MODULATION_LSB) & Si2158_DTV_STATUS_RESPONSE_MODULATION_MASK;
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+static int silabs_tercab_get_status(struct dvb_frontend *fe, u32 *status)
-+{
-+	struct silabs_tercab_priv *priv = fe->tuner_priv;
-+	u8 res;
-+	u8 ATV_Sync_Lock;
-+	u8 ATV_Master_Lock;
-+
-+	*status = 0;
-+
-+	if (priv->mode == SILABS_TERCAB_ANALOG) {
-+		mutex_lock(&priv->lock);
-+		res = silabs_tercab_atv_status(priv, Si2158_ATV_STATUS_CMD_INTACK_OK);
-+		mutex_unlock(&priv->lock);
-+		if (res != NO_SILABS_TERCAB_ERROR) {
-+			silabs_tercab_err("Si2177_L1_ATV_STATUS() failed (err=%d)\n", res);
-+			return -EIO;
-+		}
-+		ATV_Sync_Lock   = priv->tuner.rsp.atv_status.pcl;
-+		ATV_Master_Lock = priv->tuner.rsp.atv_status.dl;
-+
-+		silabs_tercab_dbg("ATV_Sync_Lock=%u  ATV_Master_Lock=%u  Channel=%u\n", ATV_Sync_Lock, ATV_Master_Lock, priv->tuner.rsp.atv_status.chl);
-+
-+		if (ATV_Sync_Lock && ATV_Master_Lock) {
-+			*status = TUNER_STATUS_LOCKED;
-+		}
-+	} else {
-+		mutex_lock(&priv->lock);
-+		res = silabs_tercab_dtv_status(&priv->tuner, Si2158_DTV_STATUS_CMD_INTACK_OK);
-+		mutex_unlock(&priv->lock);
-+		if (res != NO_SILABS_TERCAB_ERROR) {
-+			silabs_tercab_err("Si2177_L1_DTV_STATUS() failed (err=%d)\n", res);
-+			return -EIO;
-+		}
-+		silabs_tercab_dbg("Channel=%u\n", priv->tuner.rsp.dtv_status.chl);
-+		if (priv->tuner.rsp.dtv_status.chl) { /* ToDo: is this a lock indicator? */
-+			*status = TUNER_STATUS_LOCKED;
-+		}
-+	}
-+
-+#if 0
-+	if (tuner_stereo(priv->type, tuner_status))
-+		*status |= TUNER_STATUS_STEREO;
-+#endif
-+
-+	silabs_tercab_dbg("Status=%d\n", *status);
-+
-+	return 0;
-+}
-+
-+/*---------------------------------------------------*/
-+/* Si2158_TUNER_STATUS COMMAND                     */
-+/*---------------------------------------------------*/
-+static u8 silabs_tercab_tuner_status(silabs_tercab_context *ctx, u8 intack)
-+{
-+	u8 error_code = 0;
-+	u8 cmdByteBuffer[2];
-+	u8 rspByteBuffer[12];
-+	ctx->rsp.tuner_status.STATUS = &ctx->status;
-+
-+	SiTRACE("%s()\n", __func__);
-+
-+	cmdByteBuffer[0] = Si2158_TUNER_STATUS_CMD;
-+	cmdByteBuffer[1] = (u8) ( ( intack & Si2158_TUNER_STATUS_CMD_INTACK_MASK ) << Si2158_TUNER_STATUS_CMD_INTACK_LSB);
-+
-+	if (i2c_write_bytes(ctx->i2c_adap, ctx->i2c_addr, 2, cmdByteBuffer) != 2) {
-+		SiTRACE("Error writing TUNER_STATUS bytes!\n");
-+		return ERROR_SILABS_TERCAB_SENDING_COMMAND;
-+	}
-+
-+	error_code = silabs_tercab_poll_response(ctx->i2c_adap, ctx->i2c_addr, 12, rspByteBuffer, &ctx->status);
-+	if (error_code) {
-+		SiTRACE("Error polling TUNER_STATUS response\n");
-+		return error_code;
-+	}
-+
-+	ctx->rsp.tuner_status.tcint    =   (( ( (rspByteBuffer[1]  )) >> Si2158_TUNER_STATUS_RESPONSE_TCINT_LSB    ) & Si2158_TUNER_STATUS_RESPONSE_TCINT_MASK    );
-+	ctx->rsp.tuner_status.rssilint =   (( ( (rspByteBuffer[1]  )) >> Si2158_TUNER_STATUS_RESPONSE_RSSILINT_LSB ) & Si2158_TUNER_STATUS_RESPONSE_RSSILINT_MASK );
-+	ctx->rsp.tuner_status.rssihint =   (( ( (rspByteBuffer[1]  )) >> Si2158_TUNER_STATUS_RESPONSE_RSSIHINT_LSB ) & Si2158_TUNER_STATUS_RESPONSE_RSSIHINT_MASK );
-+	ctx->rsp.tuner_status.tc       =   (( ( (rspByteBuffer[2]  )) >> Si2158_TUNER_STATUS_RESPONSE_TC_LSB       ) & Si2158_TUNER_STATUS_RESPONSE_TC_MASK       );
-+	ctx->rsp.tuner_status.rssil    =   (( ( (rspByteBuffer[2]  )) >> Si2158_TUNER_STATUS_RESPONSE_RSSIL_LSB    ) & Si2158_TUNER_STATUS_RESPONSE_RSSIL_MASK    );
-+	ctx->rsp.tuner_status.rssih    =   (( ( (rspByteBuffer[2]  )) >> Si2158_TUNER_STATUS_RESPONSE_RSSIH_LSB    ) & Si2158_TUNER_STATUS_RESPONSE_RSSIH_MASK    );
-+	ctx->rsp.tuner_status.rssi     = (((( ( (rspByteBuffer[3]  )) >> Si2158_TUNER_STATUS_RESPONSE_RSSI_LSB     ) & Si2158_TUNER_STATUS_RESPONSE_RSSI_MASK) << Si2158_TUNER_STATUS_RESPONSE_RSSI_SHIFT ) >> Si2158_TUNER_STATUS_RESPONSE_RSSI_SHIFT);
-+	ctx->rsp.tuner_status.freq     =   (( ( (rspByteBuffer[4]  ) | (rspByteBuffer[5]  << 8 ) | (rspByteBuffer[6]  << 16 ) | (rspByteBuffer[7]  << 24 )) >> Si2158_TUNER_STATUS_RESPONSE_FREQ_LSB     ) & Si2158_TUNER_STATUS_RESPONSE_FREQ_MASK);
-+	ctx->rsp.tuner_status.mode     =   (( ( (rspByteBuffer[8]  )) >> Si2158_TUNER_STATUS_RESPONSE_MODE_LSB     ) & Si2158_TUNER_STATUS_RESPONSE_MODE_MASK     );
-+	ctx->rsp.tuner_status.vco_code = (((( ( (rspByteBuffer[10] ) | (rspByteBuffer[11] << 8 )) >> Si2158_TUNER_STATUS_RESPONSE_VCO_CODE_LSB ) & Si2158_TUNER_STATUS_RESPONSE_VCO_CODE_MASK) << Si2158_TUNER_STATUS_RESPONSE_VCO_CODE_SHIFT) >> Si2158_TUNER_STATUS_RESPONSE_VCO_CODE_SHIFT);
-+
-+	return NO_SILABS_TERCAB_ERROR;
-+}
-+
-+static int silabs_tercab_get_signal(struct dvb_frontend *fe, u16 *strength)
-+{
-+	struct silabs_tercab_priv *priv = fe->tuner_priv;
-+	int rc = 0;
-+	char rssi = 0;
-+	u8 res;
-+	u32 freq;
-+	u8 mode;
-+	u8 ATV_Sync_Lock;
-+	u8 ATV_Master_Lock;
-+	u8 chl;
-+
-+	mutex_lock(&priv->lock);
-+	res = silabs_tercab_tuner_status(&priv->tuner, Si2158_TUNER_STATUS_CMD_INTACK_OK);
-+	mutex_unlock(&priv->lock);
-+	if (res != NO_SILABS_TERCAB_ERROR) {
-+		silabs_tercab_err("Si2177_L1_TUNER_STATUS() failed (err=%d)\n", res);
-+		return -EIO;
-+	}
-+
-+	//vco_code =  priv->tuner.rsp.tuner_status.vco_code;
-+	//tc       =  priv->tuner.rsp.tuner_status.tc;
-+	//rssil    =  priv->tuner.rsp.tuner_status.rssil;
-+	//rssih    =  priv->tuner.rsp.tuner_status.rssih;
-+	rssi     =  priv->tuner.rsp.tuner_status.rssi;
-+	freq     =  priv->tuner.rsp.tuner_status.freq;
-+	mode     =  priv->tuner.rsp.tuner_status.mode;
-+
-+	silabs_tercab_dbg("freq=%u  mode=%u\n", freq, mode);
-+
-+	if (priv->mode == SILABS_TERCAB_ANALOG) {
-+		mutex_lock(&priv->lock);
-+		res = silabs_tercab_atv_status(priv, Si2158_ATV_STATUS_CMD_INTACK_OK);
-+		mutex_unlock(&priv->lock);
-+		if (res != NO_SILABS_TERCAB_ERROR) {
-+			silabs_tercab_err("Si2177_L1_ATV_STATUS() failed (err=%d)\n", res);
-+			return -EIO;
-+		}
-+		ATV_Sync_Lock    = priv->tuner.rsp.atv_status.pcl;
-+		ATV_Master_Lock  = priv->tuner.rsp.atv_status.dl;
-+
-+		silabs_tercab_dbg("chlint           = %d\n", priv->tuner.rsp.atv_status.chlint);
-+		silabs_tercab_dbg("pclint           = %d\n", priv->tuner.rsp.atv_status.pclint);
-+		silabs_tercab_dbg("dlint            = %d\n", priv->tuner.rsp.atv_status.dlint);
-+		silabs_tercab_dbg("snrlint          = %d\n", priv->tuner.rsp.atv_status.snrlint);
-+		silabs_tercab_dbg("snrhint          = %d\n", priv->tuner.rsp.atv_status.snrhint);
-+		silabs_tercab_dbg("chl              = %d\n", priv->tuner.rsp.atv_status.chl);
-+		silabs_tercab_dbg("snrl             = %d\n", priv->tuner.rsp.atv_status.snrl);
-+		silabs_tercab_dbg("snrh             = %d\n", priv->tuner.rsp.atv_status.snrh);
-+		silabs_tercab_dbg("video_snr        = %d\n", priv->tuner.rsp.atv_status.video_snr);
-+		silabs_tercab_dbg("afc_freq         = %d\n", priv->tuner.rsp.atv_status.afc_freq);
-+		silabs_tercab_dbg("video_sc_spacing = %d\n", priv->tuner.rsp.atv_status.video_sc_spacing);
-+		silabs_tercab_dbg("video_sys        = %d\n", priv->tuner.rsp.atv_status.video_sys);
-+		silabs_tercab_dbg("lines            = %d\n", priv->tuner.rsp.atv_status.lines);
-+		silabs_tercab_dbg("audio_sys        = %d\n", priv->tuner.rsp.atv_status.audio_sys);
-+		silabs_tercab_dbg("audio_demod_mode = %d\n", priv->tuner.rsp.atv_status.audio_demod_mode);
-+		silabs_tercab_dbg("audio_chan_bw    = %d\n", priv->tuner.rsp.atv_status.audio_chan_bw);
-+		silabs_tercab_dbg("sound_level      = %d\n", priv->tuner.rsp.atv_status.sound_level);
-+
-+		silabs_tercab_dbg("ATV_Sync_Lock=%u  ATV_Master_Lock=%u\n", ATV_Sync_Lock, ATV_Master_Lock);
-+
-+		if (priv->tuner.rsp.atv_status.chl && priv->tuner.rsp.atv_status.pcl) {
-+			silabs_tercab_dbg("RSSI analog: %ddBm\n", rssi);
-+			*strength = (rssi > -50) ? (u16)rssi + 120 : 0;
-+		} else {
-+			silabs_tercab_dbg("RSSI analog: no signal\n");
-+			*strength = 0;
-+		}
-+	} else {
-+		mutex_lock(&priv->lock);
-+		res = silabs_tercab_dtv_status(&priv->tuner, Si2158_DTV_STATUS_CMD_INTACK_OK);
-+		mutex_unlock(&priv->lock);
-+		if (res != NO_SILABS_TERCAB_ERROR) {
-+			silabs_tercab_err("Si2177_L1_DTV_STATUS() failed (err=%d)\n", res);
-+			return -EIO;
-+		}
-+		chl                =  priv->tuner.rsp.dtv_status.chl;
-+		//bw                 =  priv->tuner.rsp.dtv_status.bw;
-+		//modulation         =  priv->tuner.rsp.dtv_status.modulation;
-+		silabs_tercab_dbg("RSSI digital: %ddBm (channel=%u)\n", rssi, chl);
-+		*strength = (rssi > -50) ? (u16)rssi + 120 : 0;
-+	}
-+	return rc;
-+}
-+
-+static int silabs_tercab_setup_configuration(struct dvb_frontend *fe,
-+		struct silabs_tercab_config *cfg)
-+{
-+	struct silabs_tercab_priv *priv = fe->tuner_priv;
-+
-+	silabs_tercab_dbg("\n");
-+
-+	priv->config = cfg;
-+
-+	priv->qam_if_khz              = (cfg) ? cfg->qam_if_khz : 4000;
-+	priv->vsb_if_khz              = (cfg) ? cfg->vsb_if_khz : 3250;
-+	priv->clock_control           = (cfg) ? cfg->tuner_clock_control : _Si2168B_CLOCK_MANAGED;
-+	priv->agc_control             = (cfg) ? cfg->tuner_agc_control : 1;
-+	priv->fef_mode                = (cfg) ? cfg->fef_mode : Si2177_FEF_MODE_SLOW_NORMAL_AGC;
-+	priv->crystal_trim_xo_cap     = (cfg) ? cfg->crystal_trim_xo_cap : Si2158_CRYSTAL_TRIM_PROP_XO_CAP_DEFAULT;
-+	priv->indirect_i2c_connection = (cfg) ? cfg->indirect_i2c_connection : 1;
-+	return 0;
-+}
-+
-+static int silabs_tercab_set_config(struct dvb_frontend *fe, void *priv_cfg)
-+{
-+	struct silabs_tercab_priv *priv = fe->tuner_priv;
-+	struct silabs_tercab_config *cfg = (struct silabs_tercab_config *) priv_cfg;
-+
-+	silabs_tercab_dbg("\n");
-+
-+	silabs_tercab_setup_configuration(fe, cfg);
-+
-+	return 0;
-+}
-+
-+int silabs_tercab_autodetection(struct i2c_adapter* i2c_adapter, u8 i2c_addr)
-+{
-+	u8 power_up_clock_mode = 0; /* clock mode xtal */
-+	u8 power_up_en_xout = 0;    /* disable xout */
-+	struct silabs_tercab_priv *priv = NULL; /* for debug output only */
-+	struct part_info part_info;
-+	silabs_tercab_status status;
-+	int return_code = 0;
-+
-+	silabs_tercab_info("%s(): i2c addr=0x%02X  clock mode=%u  en_xou=%u\n", __func__, i2c_addr, power_up_clock_mode, power_up_en_xout);
-+
-+	/* always wait for CTS prior to POWER_UP command */
-+	if ((return_code = silabs_tercab_poll_cts(i2c_adapter, i2c_addr)) != 0) {
-+		silabs_tercab_err("silabs_tercab_poll_cts error 0x%02x\n", return_code);
-+		return -ENODEV;
-+	}
-+
-+	if ((return_code = silabs_tercab_power_up(i2c_adapter, i2c_addr, Si2158_POWER_UP_CMD_SUBCODE_CODE,
-+			power_up_clock_mode,
-+			power_up_en_xout,
-+			Si2158_POWER_UP_CMD_PD_LDO_LDO_POWER_UP,
-+			Si2158_POWER_UP_CMD_RESERVED2_RESERVED,
-+			Si2158_POWER_UP_CMD_RESERVED3_RESERVED,
-+			Si2158_POWER_UP_CMD_RESERVED4_RESERVED,
-+			Si2158_POWER_UP_CMD_RESERVED5_RESERVED,
-+			Si2158_POWER_UP_CMD_RESERVED6_RESERVED,
-+			Si2158_POWER_UP_CMD_RESERVED7_RESERVED,
-+			Si2158_POWER_UP_CMD_RESET_RESET,
-+			Si2158_POWER_UP_CMD_CLOCK_FREQ_CLK_24MHZ,
-+			Si2158_POWER_UP_CMD_RESERVED8_RESERVED,
-+			Si2158_POWER_UP_CMD_FUNC_BOOTLOADER,
-+#ifndef __SI2158__
-+			Si2157_POWER_UP_CMD_RESERVED9_RESERVED,
-+#endif
-+			Si2158_POWER_UP_CMD_CTSIEN_DISABLE,
-+			Si2158_POWER_UP_CMD_WAKE_UP_WAKE_UP,
-+			&status)) != 0)
-+	{
-+		silabs_tercab_err("silabs_tercab_power_up() failed (err 0x%02x).\n", return_code);
-+		return -ENODEV;
-+	}
-+
-+	/* Get the Part Info from the chip.   This command is only valid in Bootloader mode */
-+	if ((return_code = si2158_part_info(i2c_adapter, i2c_addr, &part_info)) != 0) {
-+		silabs_tercab_err("si2158_part_info() failed (err 0x%02x).\n", return_code);
-+		return -ENODEV;
-+	}
-+	switch (part_info.part) {
-+	case 57:
-+	case 77:
-+		/* supported */
-+		break;
-+	default:
-+		silabs_tercab_info("unsupported Silicon Labs tuner (part %d)\n", part_info.part);
-+		return -ENODEV;
-+	}
-+
-+	silabs_tercab_info("detected Silicon Labs tuner Si21%d (Rev. %d)\n", part_info.part, part_info.chiprev);
-+	silabs_tercab_info("pmajor  %d\n",        part_info.pmajor );
-+	if (part_info.pmajor >= 0x30) {
-+		silabs_tercab_info("pmajor '%c'\n",   part_info.pmajor );
-+	}
-+	silabs_tercab_info("pminor  %d\n",        part_info.pminor );
-+	if (part_info.pminor >= 0x30) {
-+		silabs_tercab_info("pminor '%c'\n",   part_info.pminor );
-+	}
-+	silabs_tercab_info("pbuild %d\n",         part_info.pbuild );
-+	silabs_tercab_info("romid %3d/0x%02x\n",  part_info.romid,  part_info.romid );
-+
-+	return 0; /* Silicon Labs tuner detected */
-+}
-+EXPORT_SYMBOL(silabs_tercab_autodetection);
-+
-+static const struct dvb_tuner_ops si2158_tuner_ops = {
-+		.info = {
-+				.name = "Silicon Labs terrestrial/cable tuner",
-+				.frequency_min  =  45000000,
-+				.frequency_max  = 864000000,
-+				.frequency_step =     62500
-+		},
-+		/* int (*release)(struct dvb_frontend *fe); */
-+		.release           = silabs_tercab_release,
-+		/* int (*init)(struct dvb_frontend *fe); */
-+		.init              = silabs_tercab_initialize,
-+		/* int (*sleep)(struct dvb_frontend *fe); */
-+		.sleep             = silabs_tercab_sleep,
-+
-+		/** This is for simple PLLs - set all parameters in one go. */
-+		/* int (*set_params)(struct dvb_frontend *fe); */
-+		.set_params        = silabs_tercab_set_params,
-+		/* int (*set_analog_params)(struct dvb_frontend *fe, struct analog_parameters *p); */
-+		.set_analog_params = silabs_tercab_set_analog_params,
-+
-+		/** This is support for demods like the mt352 - fills out the supplied buffer with what to write. */
-+		/* int (*calc_regs)(struct dvb_frontend *fe, u8 *buf, int buf_len); */
-+
-+		/** This is to allow setting tuner-specific configs */
-+		/* int (*set_config)(struct dvb_frontend *fe, void *priv_cfg); */
-+		.set_config        = silabs_tercab_set_config,
-+
-+		/* int (*get_frequency)(struct dvb_frontend *fe, u32 *frequency); */
-+		.get_frequency     = silabs_tercab_get_frequency,
-+		/* int (*get_bandwidth)(struct dvb_frontend *fe, u32 *bandwidth); */
-+		.get_bandwidth     = silabs_tercab_get_bandwidth,
-+		/* int (*get_if_frequency)(struct dvb_frontend *fe, u32 *frequency); */
-+		.get_if_frequency  = silabs_tercab_get_if_frequency,
-+
-+		/* int (*get_status)(struct dvb_frontend *fe, u32 *status); */
-+		.get_status        = silabs_tercab_get_status,
-+		/* int (*get_rf_strength)(struct dvb_frontend *fe, u16 *strength); */
-+		.get_rf_strength   = silabs_tercab_get_signal,
-+		/* int (*get_afc)(struct dvb_frontend *fe, s32 *afc); */
-+
-+		/** These are provided separately from set_params in order to facilitate silicon
-+		 * tuners which require sophisticated tuning loops, controlling each parameter separately. */
-+		/* int (*set_frequency)(struct dvb_frontend *fe, u32 frequency); */
-+		/* int (*set_bandwidth)(struct dvb_frontend *fe, u32 bandwidth); */
-+
-+		/*
-+		 * These are provided separately from set_params in order to facilitate silicon
-+		 * tuners which require sophisticated tuning loops, controlling each parameter separately.
-+		 */
-+		/* int (*set_state)(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state); */
-+		/* int (*get_state)(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state); */
-+};
-+
-+struct dvb_frontend *silabs_tercab_attach(struct dvb_frontend *fe,
-+		struct i2c_adapter *i2c,
-+		struct silabs_tercab_config *cfg)
-+{
-+	struct silabs_tercab_priv *priv = NULL;
-+	struct part_info part_info;
-+	int instance, ret;
-+
-+	mutex_lock(&silabs_tercab_list_mutex);
-+
-+	if (!cfg) {
-+		silabs_tercab_err("no configuration submitted\n");
-+		goto fail;
-+	}
-+
-+	instance = hybrid_tuner_request_state(struct silabs_tercab_priv, priv,
-+			hybrid_tuner_instance_list,
-+			i2c, cfg->tuner_address, "silabs_tercab");
-+
-+	switch (instance) {
-+	case 0:
-+		goto fail;
-+	case 1:
-+		/* new tuner instance */
-+		silabs_tercab_info("%s(): new instance for tuner @0x%02x\n", __func__, cfg->tuner_address);
-+		fe->tuner_priv = priv;
-+
-+		silabs_tercab_setup_configuration(fe, cfg);
-+
-+		mutex_init(&priv->lock);
-+
-+		break;
-+	default:
-+		/* existing tuner instance */
-+		fe->tuner_priv = priv;
-+
-+		/* allow dvb driver to override configuration settings */
-+		if (cfg) {
-+			silabs_tercab_info("%s(0x%02X): dvb driver submitted configuration\n", __func__, cfg->tuner_address);
-+			priv->clock_control       = cfg->tuner_clock_control;
-+			priv->agc_control         = cfg->tuner_agc_control;
-+			priv->fef_mode            = cfg->fef_mode;
-+			priv->crystal_trim_xo_cap = cfg->crystal_trim_xo_cap;
-+		} else {
-+			silabs_tercab_info("%s(0x%02X): default configuration\n", __func__, priv->tuner.i2c_addr);
-+		}
-+		break;
-+	}
-+
-+	if (!priv->indirect_i2c_connection && fe->ops.i2c_gate_ctrl)
-+		fe->ops.i2c_gate_ctrl(fe, 1); /* enable i2c gate */
-+
-+	if (silabs_tercab_autodetection(priv->i2c_props.adap, cfg->tuner_address)) {
-+		silabs_tercab_err("autodetection failed.\n");
-+		goto fail;
-+	}
-+
-+	/* Get the Part Info from the chip.   This command is only valid in Bootloader mode */
-+	if (si2158_part_info(priv->i2c_props.adap, cfg->tuner_address, &part_info)) {
-+		silabs_tercab_err("si2158_part_info() failed \n");
-+		goto fail;
-+	}
-+	priv->tuner.part    = part_info.part;
-+	priv->tuner.chiprev = part_info.chiprev;
-+
-+	silabs_tercab_info("%s(): Silicon Labs tuner Si21%02d rev. %d @0x%02x\n", __func__, priv->tuner.part, priv->tuner.chiprev, cfg->tuner_address);
-+
-+	if (!silabs_tercab_sw_init(priv, priv->i2c_props.addr, NULL, priv->i2c_props.adap)) {
-+		silabs_tercab_err("silabs_tercab_sw_init() failed.\n");
-+		goto fail;
-+	}
-+
-+	if (silabs_tercab_initialize(fe)) {
-+		silabs_tercab_err("silabs_tercab_initialize() failed.\n");
-+		goto fail;
-+	}
-+
-+	/* enter standby mode, with required output features enabled */
-+	ret = silabs_tercab_sleep(fe);
-+	silabs_tercab_fail(ret);
-+
-+	if (!priv->indirect_i2c_connection && fe->ops.i2c_gate_ctrl)
-+		fe->ops.i2c_gate_ctrl(fe, 0); /* disable i2c gate */
-+
-+	mutex_unlock(&silabs_tercab_list_mutex);
-+
-+	memcpy(&fe->ops.tuner_ops, &si2158_tuner_ops, sizeof(struct dvb_tuner_ops));
-+
-+	return fe;
-+
-+fail:
-+	mutex_unlock(&silabs_tercab_list_mutex);
-+
-+	if (!priv->indirect_i2c_connection && fe->ops.i2c_gate_ctrl)
-+		fe->ops.i2c_gate_ctrl(fe, 0); /* disable i2c gate */
-+
-+	silabs_tercab_release(fe);
-+	return NULL;
-+}
-+EXPORT_SYMBOL(silabs_tercab_attach);
-+
-+static int silabs_tercab_probe(struct i2c_client *client,
-+		const struct i2c_device_id *id)
-+{
-+	struct silabs_tercab_config *cfg = client->dev.platform_data;
-+	struct silabs_tercab_priv *priv = NULL;
-+	struct dvb_frontend *fe;
-+
-+	printk(KERN_INFO "%s: attaching Silicon Labs tuner...\n", __func__);
-+
-+	fe = silabs_tercab_attach(cfg->fe, client->adapter, cfg);
-+
-+	if (fe == NULL) {
-+		printk(KERN_ERR "%s: attaching Silicon Labs tuner failed\n", __func__);
-+		dev_dbg(&client->dev, "%s: failed\n", __func__);
-+		return -ENODEV;
-+	}
-+	priv = fe->tuner_priv;
-+	priv->client = client;
-+	priv->fe = cfg->fe;
-+
-+	i2c_set_clientdata(client, fe->tuner_priv);
-+
-+	dev_info(&priv->client->dev,
-+			"%s: Silicon Labs Tuner successfully attached\n",
-+			KBUILD_MODNAME);
-+
-+	return 0;
-+}
-+
-+static int silabs_tercab_remove(struct i2c_client *client)
-+{
-+	struct silabs_tercab_priv *priv = i2c_get_clientdata(client);
-+	struct dvb_frontend *fe = priv->fe;
-+
-+	dev_dbg(&client->dev, "%s:\n", __func__);
-+
-+	memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops));
-+	silabs_tercab_release(fe);
-+	return 0;
-+}
-+
-+static const struct i2c_device_id silabs_tercab_id[] = {
-+		{"silabs_tercab", 0},
-+		{}
-+};
-+MODULE_DEVICE_TABLE(i2c, silabs_tercab_id);
-+
-+static struct i2c_driver silabs_tercab_driver = {
-+		.driver = {
-+				.owner	= THIS_MODULE,
-+				.name	= "silabs_tercab",
-+		},
-+		.probe		= silabs_tercab_probe,
-+		.remove		= silabs_tercab_remove,
-+		.id_table	= silabs_tercab_id,
-+};
-+
-+module_i2c_driver(silabs_tercab_driver);
-+
-+MODULE_DESCRIPTION("Silicon Labs terrestrial/cable hybrid tuner driver");
-+MODULE_AUTHOR("Source code provided by Silicon Laboratories Inc.");
-+MODULE_AUTHOR("Henning Garbers <hgarbers@pctvsystems.com>");
-+MODULE_LICENSE("PROPRIETARY AND CONFIDENTIAL");
-+MODULE_VERSION("2015-02-05");
-+
-+/*
-+ * Overrides for Emacs so that we follow Linus's tabbing style.
-+ * ---------------------------------------------------------------------------
-+ * Local variables:
-+ * c-basic-offset: 8
-+ * End:
-+ */
---- linux-4.15/drivers/media/tuners/silabs_tercab.h.0140~	2018-02-12 11:32:52.770582195 +0100
-+++ linux-4.15/drivers/media/tuners/silabs_tercab.h	2018-02-12 11:32:52.770582195 +0100
-@@ -0,0 +1,102 @@
-+/*
-+ * silabs_tercab.h - header for the Silicon Laboratories terrestrial/cable
-+ * hybrid tuner series
-+ *
-+ * (C) Copyright 2014, PCTV Systems S.à r.l
-+ * Henning Garbers <hgarbers@pctvsystems.com>
-+ *
-+ *    This program is free software; you can redistribute it and/or modify
-+ *    it under the terms of the GNU General Public License as published by
-+ *    the Free Software Foundation; either version 2 of the License, or
-+ *    (at your option) any later version.
-+ *
-+ *    This program is distributed in the hope that it will be useful,
-+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *    GNU General Public License for more details.
-+ */
-+
-+#ifndef __SILABS_TERCAB_H__
-+#define __SILABS_TERCAB_H__
-+
-+#include <linux/i2c.h>
-+#include "dvb_frontend.h"
-+
-+#define HVR19x5_QAM_IF 4000
-+#define HVR19x5_VSB_IF 3250
-+
-+#define _Si2168B_CLOCK_ALWAYS_OFF 0  /* turn clock ON then never switch it off, used when the clock is provided to another part */
-+#define _Si2168B_CLOCK_ALWAYS_ON  1  /* never switch it on, used when the clock is not going anywhere */
-+#define _Si2168B_CLOCK_MANAGED    2  /* control clock state as before */
-+
-+/* settings for the Silicon Labs demod driver */
-+#define L1_RF_TER_TUNER_FEF_MODE_FREEZE_PIN_SETUP
-+#define L1_RF_TER_TUNER_FEF_MODE_SLOW_INITIAL_AGC_SETUP
-+#define L1_RF_TER_TUNER_FEF_MODE_SLOW_NORMAL_AGC_SETUP
-+
-+/******************************************************************************/
-+/* Si2177 Tuner FEF management options */
-+/******************************************************************************/
-+#define Si2177_FEF_MODE_SLOW_NORMAL_AGC  0
-+#define Si2177_FEF_MODE_FREEZE_PIN       1
-+#define Si2177_FEF_MODE_SLOW_INITIAL_AGC 2
-+
-+struct silabs_tercab_config {
-+	/* the tuner's i2c address */
-+	u8 tuner_address;
-+
-+	/* user defined IF frequencies in KHz */
-+	u16 qam_if_khz;
-+	u16 vsb_if_khz;
-+
-+	/* tuner clock_control:   how the TER clock must be controlled
-+       possible modes:
-+       CLOCK_ALWAYS_ON  (=0)
-+       CLOCK_ALWAYS_OFF (=1)
-+	   CLOCK_MANAGED    (=2) */
-+	u8 tuner_clock_control;
-+
-+	/* enable / disable AGC */
-+	u8 tuner_agc_control;
-+
-+	/* FEF management options
-+	   FEF_MODE_SLOW_NORMAL_AGC  (=0)
-+	   FEF_MODE_FREEZE_PIN       (=1)
-+	   FEF_MODE_SLOW_INITIAL_AGC (=2) */
-+    u8 fef_mode;
-+
-+    u8  crystal_trim_xo_cap;
-+
-+	/* tuner i2c connection               */
-+	/* 0-tuner connected through Si2168B  */
-+	/* 1-tuner is direct accessible       */
-+	u8 indirect_i2c_connection;
-+
-+	struct dvb_frontend *fe;
-+};
-+
-+#if IS_ENABLED(CONFIG_MEDIA_TUNER_SILABS_TERCAB)
-+extern int silabs_tercab_autodetection(struct i2c_adapter* i2c_adapter, u8 i2c_addr);
-+
-+extern struct dvb_frontend *silabs_tercab_attach(struct dvb_frontend *fe,
-+					    struct i2c_adapter *i2c,
-+					    struct silabs_tercab_config *cfg);
-+#else
-+static inline int silabs_tercab_autodetection(struct i2c_adapter* i2c_adapter,
-+					u8 i2c_addr)
-+{
-+	printk(KERN_INFO "%s: not probed - driver disabled by Kconfig\n",
-+	       __func__);
-+	return -EINVAL;
-+}
-+
-+static inline struct dvb_frontend *silabs_tercab_attach(struct dvb_frontend *fe,
-+						   struct i2c_adapter *i2c,
-+						   struct silabs_tercab_config *cfg)
-+{
-+	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
-+	return NULL;
-+}
-+#endif
-+
-+#endif /* __SILABS_TERCAB_H__ */
---- linux-4.15/drivers/media/tuners/silabs_tercab_priv.h.0140~	2018-02-12 11:32:52.773582217 +0100
-+++ linux-4.15/drivers/media/tuners/silabs_tercab_priv.h	2018-02-12 11:32:52.773582217 +0100
-@@ -0,0 +1,5651 @@
-+/*************************************************************************************
-+                  Silicon Laboratories Broadcast Si2158 Layer 1 API
-+   API types used by commands and properties
-+   FILE: Si2158_typedefs.h
-+   Supported IC : Si2158
-+   Compiled for ROM 33 firmware 2_1_build_9
-+   Revision: 0.1
-+   Date: March 20 2013
-+  (C) Copyright 2013, Silicon Laboratories, Inc. All rights reserved.
-+ **************************************************************************************/
-+#ifndef __SILABS_TERCAB_PRIV_H__
-+#define __SILABS_TERCAB_PRIV_H__
-+
-+#include "silabs_tercab.h"
-+
-+/* Uncomment the following line to activate all traces in the code */
-+/* #define SiTRACES */
-+
-+#ifdef _DEBUG
-+#define RAM_CRC_CHECK 1
-+#endif
-+
-+#define DOWNLOAD_ON_CHANGE 1
-+#define DOWNLOAD_ALWAYS    0
-+
-+#define __SI2157__
-+#define __SI2177__
-+
-+/* Si2158 API Specific Includes */
-+#define Si2158_BYTES_PER_LINE 8
-+
-+enum silabs_tercab_mode {
-+	SILABS_TERCAB_ANALOG = 0,
-+	SILABS_TERCAB_DIGITAL,
-+};
-+
-+typedef struct silabs_tercab_i2c_context
-+{
-+	u8 address;
-+	struct i2c_adapter *i2c_adap; /* linux kernel */
-+} silabs_tercab_i2c_context;
-+
-+#ifndef __SILABS_FIRMWARE_STRUCT__
-+#define __SILABS_FIRMWARE_STRUCT__
-+typedef struct  {
-+	u8 firmware_len;
-+	u8 firmware_table[16];
-+} firmware_struct;
-+#endif /* __SILABS_FIRMWARE_STRUCT__ */
-+
-+/* STATUS structure definition */
-+typedef struct { /* silabs_tercab_status */
-+	u8   tunint;
-+	u8   atvint;
-+	u8   dtvint;
-+	u8   err;
-+	u8   cts;
-+}  silabs_tercab_status;
-+
-+/* STATUS fields definition */
-+/* STATUS, TUNINT field definition (address 0, size 1, lsb 0, unsigned)*/
-+#define Si2158_STATUS_TUNINT_LSB         0
-+#define Si2158_STATUS_TUNINT_MASK        0x01
-+#define Si2158_STATUS_TUNINT_NOT_TRIGGERED  0
-+#define Si2158_STATUS_TUNINT_TRIGGERED      1
-+/* STATUS, ATVINT field definition (address 0, size 1, lsb 1, unsigned)*/
-+#define Si2158_STATUS_ATVINT_LSB         1
-+#define Si2158_STATUS_ATVINT_MASK        0x01
-+#define Si2158_STATUS_ATVINT_NOT_TRIGGERED  0
-+#define Si2158_STATUS_ATVINT_TRIGGERED      1
-+/* STATUS, DTVINT field definition (address 0, size 1, lsb 2, unsigned)*/
-+#define Si2158_STATUS_DTVINT_LSB         2
-+#define Si2158_STATUS_DTVINT_MASK        0x01
-+#define Si2158_STATUS_DTVINT_NOT_TRIGGERED  0
-+#define Si2158_STATUS_DTVINT_TRIGGERED      1
-+/* STATUS, ERR field definition (address 0, size 1, lsb 6, unsigned)*/
-+#define Si2158_STATUS_ERR_LSB         6
-+#define Si2158_STATUS_ERR_MASK        0x01
-+#define Si2158_STATUS_ERR_ERROR     1
-+#define Si2158_STATUS_ERR_NO_ERROR  0
-+/* STATUS, CTS field definition (address 0, size 1, lsb 7, unsigned)*/
-+#define Si2158_STATUS_CTS_LSB         7
-+#define Si2158_STATUS_CTS_MASK        0x01
-+#define Si2158_STATUS_CTS_COMPLETED  1
-+#define Si2158_STATUS_CTS_WAIT       0
-+
-+/* Si2158_AGC_OVERRIDE command definition */
-+#define Si2158_AGC_OVERRIDE_CMD 0x44
-+
-+#define Si2158_AGC_OVERRIDE_CMD_CODE 0x010044
-+
-+typedef struct { /* Si2158_AGC_OVERRIDE_CMD_struct */
-+	u8   force_max_gain;
-+	u8   force_top_gain;
-+} Si2158_AGC_OVERRIDE_CMD_struct;
-+
-+typedef struct { /* Si2158_AGC_OVERRIDE_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+}  Si2158_AGC_OVERRIDE_CMD_REPLY_struct;
-+
-+/* AGC_OVERRIDE command, FORCE_MAX_GAIN field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2158_AGC_OVERRIDE_CMD_FORCE_MAX_GAIN_LSB         0
-+#define Si2158_AGC_OVERRIDE_CMD_FORCE_MAX_GAIN_MASK        0x01
-+#define Si2158_AGC_OVERRIDE_CMD_FORCE_MAX_GAIN_MIN         0
-+#define Si2158_AGC_OVERRIDE_CMD_FORCE_MAX_GAIN_MAX         1
-+#define Si2158_AGC_OVERRIDE_CMD_FORCE_MAX_GAIN_DISABLE  0
-+#define Si2158_AGC_OVERRIDE_CMD_FORCE_MAX_GAIN_ENABLE   1
-+/* AGC_OVERRIDE command, FORCE_TOP_GAIN field definition (address 1,size 1, lsb 1, unsigned) */
-+#define Si2158_AGC_OVERRIDE_CMD_FORCE_TOP_GAIN_LSB         1
-+#define Si2158_AGC_OVERRIDE_CMD_FORCE_TOP_GAIN_MASK        0x01
-+#define Si2158_AGC_OVERRIDE_CMD_FORCE_TOP_GAIN_MIN         0
-+#define Si2158_AGC_OVERRIDE_CMD_FORCE_TOP_GAIN_MAX         1
-+#define Si2158_AGC_OVERRIDE_CMD_FORCE_TOP_GAIN_DISABLE  0
-+#define Si2158_AGC_OVERRIDE_CMD_FORCE_TOP_GAIN_ENABLE   1
-+
-+/* Si2158_ATV_CW_TEST command definition */
-+#define Si2158_ATV_CW_TEST_CMD 0x53
-+
-+#define Si2158_ATV_CW_TEST_CMD_CODE 0x010053
-+
-+typedef struct { /* Si2158_ATV_CW_TEST_CMD_struct */
-+	u8   pc_lock;
-+} Si2158_ATV_CW_TEST_CMD_struct;
-+
-+
-+typedef struct { /* Si2158_ATV_CW_TEST_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+}  Si2158_ATV_CW_TEST_CMD_REPLY_struct;
-+
-+/* ATV_CW_TEST command, PC_LOCK field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2158_ATV_CW_TEST_CMD_PC_LOCK_LSB         0
-+#define Si2158_ATV_CW_TEST_CMD_PC_LOCK_MASK        0x01
-+#define Si2158_ATV_CW_TEST_CMD_PC_LOCK_MIN         0
-+#define Si2158_ATV_CW_TEST_CMD_PC_LOCK_MAX         1
-+#define Si2158_ATV_CW_TEST_CMD_PC_LOCK_LOCK    1
-+#define Si2158_ATV_CW_TEST_CMD_PC_LOCK_UNLOCK  0
-+
-+/* Si2158_ATV_RESTART command definition */
-+#define Si2158_ATV_RESTART_CMD 0x51
-+
-+#define Si2158_ATV_RESTART_CMD_CODE 0x010051
-+
-+typedef struct { /* Si2158_ATV_RESTART_CMD_struct */
-+	u8   mode;
-+} Si2158_ATV_RESTART_CMD_struct;
-+
-+typedef struct { /* Si2158_ATV_RESTART_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+}  Si2158_ATV_RESTART_CMD_REPLY_struct;
-+
-+#ifdef __SI2177__
-+/* ATV_RESTART command, MODE field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2177_ATV_RESTART_CMD_MODE_LSB         0
-+#define Si2177_ATV_RESTART_CMD_MODE_MASK        0x01
-+#define Si2177_ATV_RESTART_CMD_MODE_MIN         0
-+#define Si2177_ATV_RESTART_CMD_MODE_MAX         1
-+#define Si2177_ATV_RESTART_CMD_MODE_AUDIO_ONLY  1
-+#define Si2177_ATV_RESTART_CMD_MODE_AUDIO_VIDEO 0
-+#endif /* __SI2177__ */
-+
-+/* Si2158_ATV_STATUS command definition */
-+#define Si2158_ATV_STATUS_CMD 0x52
-+
-+#define Si2158_ATV_STATUS_CMD_CODE 0x010052
-+
-+typedef struct { /* Si2158_ATV_STATUS_CMD_struct */
-+	u8   intack;
-+} Si2158_ATV_STATUS_CMD_struct;
-+
-+#ifdef __SI2158__
-+typedef struct { /* Si2158_ATV_STATUS_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+	u8  chlint;
-+	u8  pclint;
-+	u8  chl;
-+	u8  pcl;
-+	u32 afc_freq;
-+	u8  video_sys;
-+	u8  color;
-+}  Si2158_ATV_STATUS_CMD_REPLY_struct;
-+#endif /* __SI2158__ */
-+
-+#ifdef __SI2177__
-+typedef struct { /* Si2177_ATV_STATUS_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+	u8   chlint;
-+	u8   pclint;
-+	u8   dlint;
-+	u8   snrlint;
-+	u8   snrhint;
-+	u8   audio_chan_bw;
-+	s8   sound_level;
-+	u8   chl;
-+	u8   pcl;
-+	u8   dl;
-+	u8   snrl;
-+	u8   snrh;
-+	u8   video_snr;
-+	u32  afc_freq;
-+	u32  video_sc_spacing;
-+	u8   video_sys;
-+	u8   color;
-+	u8   lines;
-+	u8   audio_sys;
-+	u8   audio_demod_mode;
-+}  Si2158_ATV_STATUS_CMD_REPLY_struct;
-+#endif /* __SI2177__ */
-+
-+/* ATV_STATUS command, INTACK field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2158_ATV_STATUS_CMD_INTACK_LSB         0
-+#define Si2158_ATV_STATUS_CMD_INTACK_MASK        0x01
-+#define Si2158_ATV_STATUS_CMD_INTACK_MIN         0
-+#define Si2158_ATV_STATUS_CMD_INTACK_MAX         1
-+#define Si2158_ATV_STATUS_CMD_INTACK_CLEAR  1
-+#define Si2158_ATV_STATUS_CMD_INTACK_OK     0
-+/* ATV_STATUS command, CHLINT field definition (address 1, size 1, lsb 0, unsigned)*/
-+#define Si2158_ATV_STATUS_RESPONSE_CHLINT_LSB         0
-+#define Si2158_ATV_STATUS_RESPONSE_CHLINT_MASK        0x01
-+#define Si2158_ATV_STATUS_RESPONSE_CHLINT_CHANGED    1
-+#define Si2158_ATV_STATUS_RESPONSE_CHLINT_NO_CHANGE  0
-+/* ATV_STATUS command, PCLINT field definition (address 1, size 1, lsb 1, unsigned)*/
-+#define Si2158_ATV_STATUS_RESPONSE_PCLINT_LSB         1
-+#define Si2158_ATV_STATUS_RESPONSE_PCLINT_MASK        0x01
-+#define Si2158_ATV_STATUS_RESPONSE_PCLINT_CHANGED    1
-+#define Si2158_ATV_STATUS_RESPONSE_PCLINT_NO_CHANGE  0
-+#ifdef __SI2177__
-+/* ATV_STATUS command, DLINT field definition (address 1, size 1, lsb 2, unsigned)*/
-+#define Si2177_ATV_STATUS_RESPONSE_DLINT_LSB         2
-+#define Si2177_ATV_STATUS_RESPONSE_DLINT_MASK        0x01
-+#define Si2177_ATV_STATUS_RESPONSE_DLINT_CHANGED    1
-+#define Si2177_ATV_STATUS_RESPONSE_DLINT_NO_CHANGE  0
-+/* ATV_STATUS command, SNRLINT field definition (address 1, size 1, lsb 3, unsigned)*/
-+#define Si2177_ATV_STATUS_RESPONSE_SNRLINT_LSB         3
-+#define Si2177_ATV_STATUS_RESPONSE_SNRLINT_MASK        0x01
-+#define Si2177_ATV_STATUS_RESPONSE_SNRLINT_CHANGED    1
-+#define Si2177_ATV_STATUS_RESPONSE_SNRLINT_NO_CHANGE  0
-+/* ATV_STATUS command, SNRHINT field definition (address 1, size 1, lsb 4, unsigned)*/
-+#define Si2177_ATV_STATUS_RESPONSE_SNRHINT_LSB         4
-+#define Si2177_ATV_STATUS_RESPONSE_SNRHINT_MASK        0x01
-+#define Si2177_ATV_STATUS_RESPONSE_SNRHINT_CHANGED    1
-+#define Si2177_ATV_STATUS_RESPONSE_SNRHINT_NO_CHANGE  0
-+/* ATV_STATUS command, AUDIO_CHAN_BW field definition (address 10, size 4, lsb 0, unsigned)*/
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_CHAN_BW_LSB         0
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_CHAN_BW_MASK        0x0f
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_CHAN_BW_12X_OVERMOD     3
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_CHAN_BW_150_KHZ_OFFSET  8
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_CHAN_BW_15_KHZ_OFFSET   5
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_CHAN_BW_30_KHZ_OFFSET   6
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_CHAN_BW_4X_OVERMOD      1
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_CHAN_BW_75_KHZ_OFFSET   7
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_CHAN_BW_7P5_KHZ_OFFSET  4
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_CHAN_BW_8X_OVERMOD      2
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_CHAN_BW_CUSTOM          9
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_CHAN_BW_RSVD            0
-+/* ATV_STATUS command, SOUND_LEVEL field definition (address 11, size 8, lsb 0, signed)*/
-+#define Si2177_ATV_STATUS_RESPONSE_SOUND_LEVEL_LSB         0
-+#define Si2177_ATV_STATUS_RESPONSE_SOUND_LEVEL_MASK        0xff
-+#define Si2177_ATV_STATUS_RESPONSE_SOUND_LEVEL_SHIFT       24
-+#endif /* __SI2177__ */
-+/* ATV_STATUS command, CHL field definition (address 2, size 1, lsb 0, unsigned)*/
-+#define Si2158_ATV_STATUS_RESPONSE_CHL_LSB         0
-+#define Si2158_ATV_STATUS_RESPONSE_CHL_MASK        0x01
-+#define Si2158_ATV_STATUS_RESPONSE_CHL_CHANNEL     1
-+#define Si2158_ATV_STATUS_RESPONSE_CHL_NO_CHANNEL  0
-+/* ATV_STATUS command, PCL field definition (address 2, size 1, lsb 1, unsigned)*/
-+#define Si2158_ATV_STATUS_RESPONSE_PCL_LSB         1
-+#define Si2158_ATV_STATUS_RESPONSE_PCL_MASK        0x01
-+#define Si2158_ATV_STATUS_RESPONSE_PCL_LOCKED   1
-+#define Si2158_ATV_STATUS_RESPONSE_PCL_NO_LOCK  0
-+#ifdef __SI2177__
-+/* ATV_STATUS command, DL field definition (address 2, size 1, lsb 2, unsigned)*/
-+#define Si2177_ATV_STATUS_RESPONSE_DL_LSB         2
-+#define Si2177_ATV_STATUS_RESPONSE_DL_MASK        0x01
-+#define Si2177_ATV_STATUS_RESPONSE_DL_LOCKED   1
-+#define Si2177_ATV_STATUS_RESPONSE_DL_NO_LOCK  0
-+/* ATV_STATUS command, SNRL field definition (address 2, size 1, lsb 3, unsigned)*/
-+#define Si2177_ATV_STATUS_RESPONSE_SNRL_LSB         3
-+#define Si2177_ATV_STATUS_RESPONSE_SNRL_MASK        0x01
-+#define Si2177_ATV_STATUS_RESPONSE_SNRL_SNR_LOW      1
-+#define Si2177_ATV_STATUS_RESPONSE_SNRL_SNR_NOT_LOW  0
-+/* ATV_STATUS command, SNRH field definition (address 2, size 1, lsb 4, unsigned)*/
-+#define Si2177_ATV_STATUS_RESPONSE_SNRH_LSB         4
-+#define Si2177_ATV_STATUS_RESPONSE_SNRH_MASK        0x01
-+#define Si2177_ATV_STATUS_RESPONSE_SNRH_SNR_HIGH      1
-+#define Si2177_ATV_STATUS_RESPONSE_SNRH_SNR_NOT_HIGH  0
-+/* ATV_STATUS command, VIDEO_SNR field definition (address 3, size 8, lsb 0, unsigned)*/
-+#define Si2177_ATV_STATUS_RESPONSE_VIDEO_SNR_LSB         0
-+#define Si2177_ATV_STATUS_RESPONSE_VIDEO_SNR_MASK        0xff
-+#endif /* __SI2177__ */
-+/* ATV_STATUS command, AFC_FREQ field definition (address 4, size 16, lsb 0, signed)*/
-+#define Si2158_ATV_STATUS_RESPONSE_AFC_FREQ_LSB         0
-+#define Si2158_ATV_STATUS_RESPONSE_AFC_FREQ_MASK        0xffff
-+#define Si2158_ATV_STATUS_RESPONSE_AFC_FREQ_SHIFT       16
-+#ifdef __SI2177__
-+/* ATV_STATUS command, VIDEO_SC_SPACING field definition (address 6, size 16, lsb 0, signed)*/
-+#define Si2177_ATV_STATUS_RESPONSE_VIDEO_SC_SPACING_LSB         0
-+#define Si2177_ATV_STATUS_RESPONSE_VIDEO_SC_SPACING_MASK        0xffff
-+#define Si2177_ATV_STATUS_RESPONSE_VIDEO_SC_SPACING_SHIFT       16
-+#endif /* __SI2177__ */
-+/* ATV_STATUS command, VIDEO_SYS field definition (address 8, size 3, lsb 0, unsigned)*/
-+#define Si2158_ATV_STATUS_RESPONSE_VIDEO_SYS_LSB         0
-+#define Si2158_ATV_STATUS_RESPONSE_VIDEO_SYS_MASK        0x07
-+#define Si2158_ATV_STATUS_RESPONSE_VIDEO_SYS_B   0
-+#define Si2158_ATV_STATUS_RESPONSE_VIDEO_SYS_DK  5
-+#define Si2158_ATV_STATUS_RESPONSE_VIDEO_SYS_GH  1
-+#define Si2158_ATV_STATUS_RESPONSE_VIDEO_SYS_I   4
-+#define Si2158_ATV_STATUS_RESPONSE_VIDEO_SYS_L   6
-+#define Si2158_ATV_STATUS_RESPONSE_VIDEO_SYS_LP  7
-+#define Si2158_ATV_STATUS_RESPONSE_VIDEO_SYS_M   2
-+#define Si2158_ATV_STATUS_RESPONSE_VIDEO_SYS_N   3
-+/* ATV_STATUS command, COLOR field definition (address 8, size 1, lsb 4, unsigned)*/
-+#define Si2158_ATV_STATUS_RESPONSE_COLOR_LSB         4
-+#define Si2158_ATV_STATUS_RESPONSE_COLOR_MASK        0x01
-+#define Si2158_ATV_STATUS_RESPONSE_COLOR_PAL_NTSC  0
-+#define Si2158_ATV_STATUS_RESPONSE_COLOR_SECAM     1
-+
-+#ifdef __SI2177__
-+/* ATV_STATUS command, LINES field definition (address 8, size 1, lsb 7, unsigned)*/
-+#define Si2177_ATV_STATUS_RESPONSE_LINES_LSB         7
-+#define Si2177_ATV_STATUS_RESPONSE_LINES_MASK        0x01
-+#define Si2177_ATV_STATUS_RESPONSE_LINES_525  0
-+#define Si2177_ATV_STATUS_RESPONSE_LINES_625  1
-+/* ATV_STATUS command, AUDIO_SYS field definition (address 9, size 4, lsb 0, unsigned)*/
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_LSB         0
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_MASK        0x0f
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_A2               3
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_A2_DK2           4
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_A2_DK3           5
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_A2_DK4           9
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_BTSC             6
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_EIAJ             7
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_MONO             1
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_MONO_NICAM       2
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_MONO_NICAM_10DB  12
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_MONO_NICAM_6DB   11
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_RSVD             0
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_SCAN             8
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_SYS_WIDE_SCAN        10
-+/* ATV_STATUS command, AUDIO_DEMOD_MODE field definition (address 9, size 2, lsb 4, unsigned)*/
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_DEMOD_MODE_LSB         4
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_DEMOD_MODE_MASK        0x03
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_DEMOD_MODE_AM   1
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_DEMOD_MODE_FM1  2
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_DEMOD_MODE_FM2  3
-+#define Si2177_ATV_STATUS_RESPONSE_AUDIO_DEMOD_MODE_SIF  0
-+#endif /* __SI2177__ */
-+
-+/* Si2158_CONFIG_CLOCKS command definition */
-+#define Si2158_CONFIG_CLOCKS_CMD 0xc0
-+
-+#define Si2158_CONFIG_CLOCKS_CMD_CODE 0x0100c0
-+
-+typedef struct { /* Si2158_CONFIG_CLOCKS_CMD_struct */
-+	u8   subcode;
-+	u8   clock_mode;
-+	u8   en_xout;
-+} Si2158_CONFIG_CLOCKS_CMD_struct;
-+
-+typedef struct { /* Si2158_CONFIG_CLOCKS_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+}  Si2158_CONFIG_CLOCKS_CMD_REPLY_struct;
-+
-+/* CONFIG_CLOCKS command, SUBCODE field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2158_CONFIG_CLOCKS_CMD_SUBCODE_LSB         0
-+#define Si2158_CONFIG_CLOCKS_CMD_SUBCODE_MASK        0xff
-+#define Si2158_CONFIG_CLOCKS_CMD_SUBCODE_MIN         0
-+#define Si2158_CONFIG_CLOCKS_CMD_SUBCODE_MAX         0
-+#define Si2158_CONFIG_CLOCKS_CMD_SUBCODE_CODE  0
-+/* CONFIG_CLOCKS command, CLOCK_MODE field definition (address 2,size 2, lsb 0, unsigned) */
-+#define Si2158_CONFIG_CLOCKS_CMD_CLOCK_MODE_LSB         0
-+#define Si2158_CONFIG_CLOCKS_CMD_CLOCK_MODE_MASK        0x03
-+#define Si2158_CONFIG_CLOCKS_CMD_CLOCK_MODE_MIN         0
-+#define Si2158_CONFIG_CLOCKS_CMD_CLOCK_MODE_MAX         2
-+#define Si2158_CONFIG_CLOCKS_CMD_CLOCK_MODE_EXTCLK  2
-+#define Si2158_CONFIG_CLOCKS_CMD_CLOCK_MODE_XTAL    0
-+/* CONFIG_CLOCKS command, EN_XOUT field definition (address 2,size 3, lsb 2, unsigned) */
-+#define Si2158_CONFIG_CLOCKS_CMD_EN_XOUT_LSB         2
-+#define Si2158_CONFIG_CLOCKS_CMD_EN_XOUT_MASK        0x07
-+#define Si2158_CONFIG_CLOCKS_CMD_EN_XOUT_MIN         0
-+#define Si2158_CONFIG_CLOCKS_CMD_EN_XOUT_MAX         3
-+#define Si2158_CONFIG_CLOCKS_CMD_EN_XOUT_DIS_XOUT  0
-+#define Si2158_CONFIG_CLOCKS_CMD_EN_XOUT_EN_XOUT   3
-+
-+#ifdef __SI2177__
-+/* Si2177_CONFIG_I2C command definition */
-+#define Si2177_CONFIG_I2C_CMD 0xc0
-+
-+#define Si2177_CONFIG_I2C_CMD_CODE 0x0200c0
-+
-+typedef struct { /* Si2177_CONFIG_I2C_CMD_struct */
-+	u8   subcode;
-+	u8   i2c_broadcast;
-+} Si2177_CONFIG_I2C_CMD_struct;
-+
-+
-+typedef struct { /* Si2177_CONFIG_I2C_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+}  Si2177_CONFIG_I2C_CMD_REPLY_struct;
-+
-+/* CONFIG_I2C command, SUBCODE field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2177_CONFIG_I2C_CMD_SUBCODE_LSB         0
-+#define Si2177_CONFIG_I2C_CMD_SUBCODE_MASK        0xff
-+#define Si2177_CONFIG_I2C_CMD_SUBCODE_MIN         36
-+#define Si2177_CONFIG_I2C_CMD_SUBCODE_MAX         36
-+#define Si2177_CONFIG_I2C_CMD_SUBCODE_CODE  36
-+/* CONFIG_I2C command, I2C_BROADCAST field definition (address 2,size 2, lsb 0, unsigned) */
-+#define Si2177_CONFIG_I2C_CMD_I2C_BROADCAST_LSB         0
-+#define Si2177_CONFIG_I2C_CMD_I2C_BROADCAST_MASK        0x03
-+#define Si2177_CONFIG_I2C_CMD_I2C_BROADCAST_MIN         0
-+#define Si2177_CONFIG_I2C_CMD_I2C_BROADCAST_MAX         1
-+#define Si2177_CONFIG_I2C_CMD_I2C_BROADCAST_DISABLED  0
-+#define Si2177_CONFIG_I2C_CMD_I2C_BROADCAST_ENABLED   1
-+#endif /* __SI2177__ */
-+
-+/* Si2158_CONFIG_PINS command definition */
-+#define Si2158_CONFIG_PINS_CMD 0x12
-+
-+#define Si2158_CONFIG_PINS_CMD_CODE 0x010012
-+
-+typedef struct { /* Si2158_CONFIG_PINS_CMD_struct */
-+	u8   gpio1_mode;
-+	u8   gpio1_read;
-+	u8   gpio2_mode;
-+	u8   gpio2_read;
-+	u8   reserved1;
-+	u8   reserved2;
-+	u8   reserved3;
-+} Si2158_CONFIG_PINS_CMD_struct;
-+
-+
-+typedef struct { /* Si2158_CONFIG_PINS_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+	u8   gpio1_mode;
-+	u8   gpio1_state;
-+	u8   gpio2_mode;
-+	u8   gpio2_state;
-+	u8   reserved1;
-+	u8   reserved2;
-+	u8   reserved3;
-+}  Si2158_CONFIG_PINS_CMD_REPLY_struct;
-+
-+/* CONFIG_PINS command, GPIO1_MODE field definition (address 1,size 7, lsb 0, unsigned) */
-+#define Si2158_CONFIG_PINS_CMD_GPIO1_MODE_LSB         0
-+#define Si2158_CONFIG_PINS_CMD_GPIO1_MODE_MASK        0x7f
-+#define Si2158_CONFIG_PINS_CMD_GPIO1_MODE_MIN         0
-+#define Si2158_CONFIG_PINS_CMD_GPIO1_MODE_MAX         3
-+#define Si2158_CONFIG_PINS_CMD_GPIO1_MODE_DISABLE    1
-+#define Si2158_CONFIG_PINS_CMD_GPIO1_MODE_DRIVE_0    2
-+#define Si2158_CONFIG_PINS_CMD_GPIO1_MODE_DRIVE_1    3
-+#define Si2158_CONFIG_PINS_CMD_GPIO1_MODE_NO_CHANGE  0
-+/* CONFIG_PINS command, GPIO1_READ field definition (address 1,size 1, lsb 7, unsigned) */
-+#define Si2158_CONFIG_PINS_CMD_GPIO1_READ_LSB         7
-+#define Si2158_CONFIG_PINS_CMD_GPIO1_READ_MASK        0x01
-+#define Si2158_CONFIG_PINS_CMD_GPIO1_READ_MIN         0
-+#define Si2158_CONFIG_PINS_CMD_GPIO1_READ_MAX         1
-+#define Si2158_CONFIG_PINS_CMD_GPIO1_READ_DO_NOT_READ  0
-+#define Si2158_CONFIG_PINS_CMD_GPIO1_READ_READ         1
-+/* CONFIG_PINS command, GPIO2_MODE field definition (address 2,size 7, lsb 0, unsigned) */
-+#define Si2158_CONFIG_PINS_CMD_GPIO2_MODE_LSB         0
-+#define Si2158_CONFIG_PINS_CMD_GPIO2_MODE_MASK        0x7f
-+#define Si2158_CONFIG_PINS_CMD_GPIO2_MODE_MIN         0
-+#define Si2158_CONFIG_PINS_CMD_GPIO2_MODE_MAX         3
-+#define Si2158_CONFIG_PINS_CMD_GPIO2_MODE_DISABLE    1
-+#define Si2158_CONFIG_PINS_CMD_GPIO2_MODE_DRIVE_0    2
-+#define Si2158_CONFIG_PINS_CMD_GPIO2_MODE_DRIVE_1    3
-+#define Si2158_CONFIG_PINS_CMD_GPIO2_MODE_NO_CHANGE  0
-+/* CONFIG_PINS command, GPIO2_READ field definition (address 2,size 1, lsb 7, unsigned) */
-+#define Si2158_CONFIG_PINS_CMD_GPIO2_READ_LSB         7
-+#define Si2158_CONFIG_PINS_CMD_GPIO2_READ_MASK        0x01
-+#define Si2158_CONFIG_PINS_CMD_GPIO2_READ_MIN         0
-+#define Si2158_CONFIG_PINS_CMD_GPIO2_READ_MAX         1
-+#define Si2158_CONFIG_PINS_CMD_GPIO2_READ_DO_NOT_READ  0
-+#define Si2158_CONFIG_PINS_CMD_GPIO2_READ_READ         1
-+/* CONFIG_PINS command, RESERVED1 field definition (address 3,size 8, lsb 0, unsigned) */
-+#define Si2158_CONFIG_PINS_CMD_RESERVED1_LSB         0
-+#define Si2158_CONFIG_PINS_CMD_RESERVED1_MASK        0xff
-+#define Si2158_CONFIG_PINS_CMD_RESERVED1_MIN         1
-+#define Si2158_CONFIG_PINS_CMD_RESERVED1_MAX         1
-+#define Si2158_CONFIG_PINS_CMD_RESERVED1_RESERVED  1
-+/* CONFIG_PINS command, RESERVED2 field definition (address 4,size 8, lsb 0, unsigned) */
-+#define Si2158_CONFIG_PINS_CMD_RESERVED2_LSB         0
-+#define Si2158_CONFIG_PINS_CMD_RESERVED2_MASK        0xff
-+#define Si2158_CONFIG_PINS_CMD_RESERVED2_MIN         1
-+#define Si2158_CONFIG_PINS_CMD_RESERVED2_MAX         1
-+#define Si2158_CONFIG_PINS_CMD_RESERVED2_RESERVED  1
-+/* CONFIG_PINS command, RESERVED3 field definition (address 5,size 8, lsb 0, unsigned) */
-+#define Si2158_CONFIG_PINS_CMD_RESERVED3_LSB         0
-+#define Si2158_CONFIG_PINS_CMD_RESERVED3_MASK        0xff
-+#define Si2158_CONFIG_PINS_CMD_RESERVED3_MIN         1
-+#define Si2158_CONFIG_PINS_CMD_RESERVED3_MAX         1
-+#define Si2158_CONFIG_PINS_CMD_RESERVED3_RESERVED  1
-+/* CONFIG_PINS command, GPIO1_MODE field definition (address 1, size 7, lsb 0, unsigned)*/
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO1_MODE_LSB         0
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO1_MODE_MASK        0x7f
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO1_MODE_DISABLE  1
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO1_MODE_DRIVE_0  2
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO1_MODE_DRIVE_1  3
-+/* CONFIG_PINS command, GPIO1_STATE field definition (address 1, size 1, lsb 7, unsigned)*/
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO1_STATE_LSB         7
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO1_STATE_MASK        0x01
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO1_STATE_READ_0  0
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO1_STATE_READ_1  1
-+/* CONFIG_PINS command, GPIO2_MODE field definition (address 2, size 7, lsb 0, unsigned)*/
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO2_MODE_LSB         0
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO2_MODE_MASK        0x7f
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO2_MODE_DISABLE  1
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO2_MODE_DRIVE_0  2
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO2_MODE_DRIVE_1  3
-+/* CONFIG_PINS command, GPIO2_STATE field definition (address 2, size 1, lsb 7, unsigned)*/
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO2_STATE_LSB         7
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO2_STATE_MASK        0x01
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO2_STATE_READ_0  0
-+#define Si2158_CONFIG_PINS_RESPONSE_GPIO2_STATE_READ_1  1
-+/* CONFIG_PINS command, RESERVED1 field definition (address 3, size 8, lsb 0, unsigned)*/
-+#define Si2158_CONFIG_PINS_RESPONSE_RESERVED1_LSB         0
-+#define Si2158_CONFIG_PINS_RESPONSE_RESERVED1_MASK        0xff
-+#define Si2158_CONFIG_PINS_RESPONSE_RESERVED1_RESERVED1_MIN  1
-+#define Si2158_CONFIG_PINS_RESPONSE_RESERVED1_RESERVED1_MAX  1
-+/* CONFIG_PINS command, RESERVED2 field definition (address 4, size 8, lsb 0, unsigned)*/
-+#define Si2158_CONFIG_PINS_RESPONSE_RESERVED2_LSB         0
-+#define Si2158_CONFIG_PINS_RESPONSE_RESERVED2_MASK        0xff
-+#define Si2158_CONFIG_PINS_RESPONSE_RESERVED2_RESERVED2_MIN  1
-+#define Si2158_CONFIG_PINS_RESPONSE_RESERVED2_RESERVED2_MAX  1
-+/* CONFIG_PINS command, RESERVED3 field definition (address 5, size 8, lsb 0, unsigned)*/
-+#define Si2158_CONFIG_PINS_RESPONSE_RESERVED3_LSB         0
-+#define Si2158_CONFIG_PINS_RESPONSE_RESERVED3_MASK        0xff
-+#define Si2158_CONFIG_PINS_RESPONSE_RESERVED3_RESERVED3_MIN  1
-+#define Si2158_CONFIG_PINS_RESPONSE_RESERVED3_RESERVED3_MAX  1
-+
-+
-+/* Si2158_DTV_RESTART command definition */
-+#define Si2158_DTV_RESTART_CMD 0x61
-+
-+#define Si2158_DTV_RESTART_CMD_CODE 0x010061
-+
-+typedef struct { /* Si2158_DTV_RESTART_CMD_struct */
-+	u8   nothing;
-+} Si2158_DTV_RESTART_CMD_struct;
-+
-+typedef struct { /* Si2158_DTV_RESTART_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+}  Si2158_DTV_RESTART_CMD_REPLY_struct;
-+
-+
-+/* Si2158_DTV_STATUS command definition */
-+#define Si2158_DTV_STATUS_CMD 0x62
-+
-+#define Si2158_DTV_STATUS_CMD_CODE 0x010062
-+
-+typedef struct { /* Si2158_DTV_STATUS_CMD_struct */
-+	u8   intack;
-+} Si2158_DTV_STATUS_CMD_struct;
-+
-+typedef struct { /* Si2158_DTV_STATUS_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+	u8   chlint;
-+	u8   chl;
-+	u8   bw;
-+	u8   modulation;
-+}  Si2158_DTV_STATUS_CMD_REPLY_struct;
-+
-+/* DTV_STATUS command, INTACK field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2158_DTV_STATUS_CMD_INTACK_LSB         0
-+#define Si2158_DTV_STATUS_CMD_INTACK_MASK        0x01
-+#define Si2158_DTV_STATUS_CMD_INTACK_MIN         0
-+#define Si2158_DTV_STATUS_CMD_INTACK_MAX         1
-+#define Si2158_DTV_STATUS_CMD_INTACK_CLEAR  1
-+#define Si2158_DTV_STATUS_CMD_INTACK_OK     0
-+/* DTV_STATUS command, CHLINT field definition (address 1, size 1, lsb 0, unsigned)*/
-+#define Si2158_DTV_STATUS_RESPONSE_CHLINT_LSB         0
-+#define Si2158_DTV_STATUS_RESPONSE_CHLINT_MASK        0x01
-+#define Si2158_DTV_STATUS_RESPONSE_CHLINT_CHANGED    1
-+#define Si2158_DTV_STATUS_RESPONSE_CHLINT_NO_CHANGE  0
-+/* DTV_STATUS command, CHL field definition (address 2, size 1, lsb 0, unsigned)*/
-+#define Si2158_DTV_STATUS_RESPONSE_CHL_LSB         0
-+#define Si2158_DTV_STATUS_RESPONSE_CHL_MASK        0x01
-+#define Si2158_DTV_STATUS_RESPONSE_CHL_CHANNEL     1
-+#define Si2158_DTV_STATUS_RESPONSE_CHL_NO_CHANNEL  0
-+/* DTV_STATUS command, BW field definition (address 3, size 4, lsb 0, unsigned)*/
-+#define Si2158_DTV_STATUS_RESPONSE_BW_LSB         0
-+#define Si2158_DTV_STATUS_RESPONSE_BW_MASK        0x0f
-+#define Si2157_DTV_STATUS_RESPONSE_BW_BW_1P7MHZ  9
-+#define Si2158_DTV_STATUS_RESPONSE_BW_BW_6MHZ  6
-+#define Si2157_DTV_STATUS_RESPONSE_BW_BW_6P1MHZ  10
-+#define Si2158_DTV_STATUS_RESPONSE_BW_BW_7MHZ  7
-+#define Si2158_DTV_STATUS_RESPONSE_BW_BW_8MHZ  8
-+/* DTV_STATUS command, MODULATION field definition (address 3, size 4, lsb 4, unsigned)*/
-+#define Si2158_DTV_STATUS_RESPONSE_MODULATION_LSB         4
-+#define Si2158_DTV_STATUS_RESPONSE_MODULATION_MASK        0x0f
-+#define Si2158_DTV_STATUS_RESPONSE_MODULATION_ATSC    0
-+#define Si2158_DTV_STATUS_RESPONSE_MODULATION_DTMB    6
-+#define Si2158_DTV_STATUS_RESPONSE_MODULATION_DVBC    3
-+#define Si2158_DTV_STATUS_RESPONSE_MODULATION_DVBT    2
-+#define Si2158_DTV_STATUS_RESPONSE_MODULATION_ISDBC   5
-+#define Si2158_DTV_STATUS_RESPONSE_MODULATION_ISDBT   4
-+#define Si2158_DTV_STATUS_RESPONSE_MODULATION_QAM_US  1
-+
-+
-+/* Si2158_EXIT_BOOTLOADER command definition */
-+#define Si2158_EXIT_BOOTLOADER_CMD 0x01
-+
-+#define Si2158_EXIT_BOOTLOADER_CMD_CODE 0x010001
-+
-+typedef struct { /* Si2158_EXIT_BOOTLOADER_CMD_struct */
-+	u8   func;
-+	u8   ctsien;
-+} Si2158_EXIT_BOOTLOADER_CMD_struct;
-+
-+
-+typedef struct { /* Si2158_EXIT_BOOTLOADER_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+}  Si2158_EXIT_BOOTLOADER_CMD_REPLY_struct;
-+
-+/* EXIT_BOOTLOADER command, FUNC field definition (address 1,size 4, lsb 0, unsigned) */
-+#define Si2158_EXIT_BOOTLOADER_CMD_FUNC_LSB         0
-+#define Si2158_EXIT_BOOTLOADER_CMD_FUNC_MASK        0x0f
-+#define Si2158_EXIT_BOOTLOADER_CMD_FUNC_MIN         0
-+#define Si2158_EXIT_BOOTLOADER_CMD_FUNC_MAX         1
-+#define Si2158_EXIT_BOOTLOADER_CMD_FUNC_BOOTLOADER  0
-+#define Si2158_EXIT_BOOTLOADER_CMD_FUNC_TUNER       1
-+/* EXIT_BOOTLOADER command, CTSIEN field definition (address 1,size 1, lsb 7, unsigned) */
-+#define Si2158_EXIT_BOOTLOADER_CMD_CTSIEN_LSB         7
-+#define Si2158_EXIT_BOOTLOADER_CMD_CTSIEN_MASK        0x01
-+#define Si2158_EXIT_BOOTLOADER_CMD_CTSIEN_MIN         0
-+#define Si2158_EXIT_BOOTLOADER_CMD_CTSIEN_MAX         1
-+#define Si2158_EXIT_BOOTLOADER_CMD_CTSIEN_OFF  0
-+#define Si2158_EXIT_BOOTLOADER_CMD_CTSIEN_ON   1
-+
-+/* Si2158_FINE_TUNE command definition */
-+#define Si2158_FINE_TUNE_CMD 0x45
-+
-+#define Si2158_FINE_TUNE_CMD_CODE 0x010045
-+
-+typedef struct { /* Si2158_FINE_TUNE_CMD_struct */
-+	u8  persistence;
-+	u8  apply_to_lif;
-+	s16 offset_500hz;
-+} Si2158_FINE_TUNE_CMD_struct;
-+
-+typedef struct { /* Si2158_FINE_TUNE_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+}  Si2158_FINE_TUNE_CMD_REPLY_struct;
-+
-+/* FINE_TUNE command, PERSISTENCE field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2158_FINE_TUNE_CMD_PERSISTENCE_LSB         0
-+#define Si2158_FINE_TUNE_CMD_PERSISTENCE_MASK        0x01
-+#define Si2158_FINE_TUNE_CMD_PERSISTENCE_MIN         0
-+#define Si2158_FINE_TUNE_CMD_PERSISTENCE_MAX         1
-+#define Si2158_FINE_TUNE_CMD_PERSISTENCE_NON_PERSISTENT  0
-+#define Si2158_FINE_TUNE_CMD_PERSISTENCE_PERSISTENT      1
-+/* FINE_TUNE command, APPLY_TO_LIF field definition (address 1,size 1, lsb 1, unsigned) */
-+#define Si2158_FINE_TUNE_CMD_APPLY_TO_LIF_LSB         1
-+#define Si2158_FINE_TUNE_CMD_APPLY_TO_LIF_MASK        0x01
-+#define Si2158_FINE_TUNE_CMD_APPLY_TO_LIF_MIN         0
-+#define Si2158_FINE_TUNE_CMD_APPLY_TO_LIF_MAX         1
-+#define Si2158_FINE_TUNE_CMD_APPLY_TO_LIF_APPLY_TO_LIF         1
-+#define Si2158_FINE_TUNE_CMD_APPLY_TO_LIF_DO_NOT_APPLY_TO_LIF  0
-+/* FINE_TUNE command, OFFSET_500HZ field definition (address 2,size 16, lsb 0, signed) */
-+#define Si2158_FINE_TUNE_CMD_OFFSET_500HZ_LSB         0
-+#define Si2158_FINE_TUNE_CMD_OFFSET_500HZ_MASK        0xffff
-+#define Si2158_FINE_TUNE_CMD_OFFSET_500HZ_SHIFT       16
-+#define Si2158_FINE_TUNE_CMD_OFFSET_500HZ_MIN         -4000
-+#define Si2158_FINE_TUNE_CMD_OFFSET_500HZ_MAX         4000
-+#define Si2158_FINE_TUNE_CMD_OFFSET_500HZ_OFFSET_500HZ_MIN  -4000
-+#define Si2158_FINE_TUNE_CMD_OFFSET_500HZ_OFFSET_500HZ_MAX  4000
-+
-+/* Si2158_GET_PROPERTY command definition */
-+#define Si2158_GET_PROPERTY_CMD 0x15
-+
-+#define Si2158_GET_PROPERTY_CMD_CODE 0x010015
-+
-+typedef struct { /* Si2158_GET_PROPERTY_CMD_struct */
-+	u8  reserved;
-+	u16 prop;
-+} Si2158_GET_PROPERTY_CMD_struct;
-+
-+typedef struct { /* Si2158_GET_PROPERTY_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+	u8  reserved;
-+	u16 data;
-+}  Si2158_GET_PROPERTY_CMD_REPLY_struct;
-+
-+/* GET_PROPERTY command, RESERVED field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2158_GET_PROPERTY_CMD_RESERVED_LSB         0
-+#define Si2158_GET_PROPERTY_CMD_RESERVED_MASK        0xff
-+#define Si2158_GET_PROPERTY_CMD_RESERVED_MIN         0
-+#define Si2158_GET_PROPERTY_CMD_RESERVED_MAX         0
-+#define Si2158_GET_PROPERTY_CMD_RESERVED_RESERVED_MIN  0
-+#define Si2158_GET_PROPERTY_CMD_RESERVED_RESERVED_MAX  0
-+/* GET_PROPERTY command, PROP field definition (address 2,size 16, lsb 0, unsigned) */
-+#define Si2158_GET_PROPERTY_CMD_PROP_LSB         0
-+#define Si2158_GET_PROPERTY_CMD_PROP_MASK        0xffff
-+#define Si2158_GET_PROPERTY_CMD_PROP_MIN         0
-+#define Si2158_GET_PROPERTY_CMD_PROP_MAX         65535
-+#define Si2158_GET_PROPERTY_CMD_PROP_PROP_MIN  0
-+#define Si2158_GET_PROPERTY_CMD_PROP_PROP_MAX  65535
-+/* GET_PROPERTY command, RESERVED field definition (address 1, size 8, lsb 0, unsigned)*/
-+#define Si2158_GET_PROPERTY_RESPONSE_RESERVED_LSB         0
-+#define Si2158_GET_PROPERTY_RESPONSE_RESERVED_MASK        0xff
-+/* GET_PROPERTY command, DATA field definition (address 2, size 16, lsb 0, unsigned)*/
-+#define Si2158_GET_PROPERTY_RESPONSE_DATA_LSB         0
-+#define Si2158_GET_PROPERTY_RESPONSE_DATA_MASK        0xffff
-+
-+
-+/* Si2158_GET_REV command definition */
-+#define Si2158_GET_REV_CMD 0x11
-+
-+#define Si2158_GET_REV_CMD_CODE 0x010011
-+
-+typedef struct { /* Si2158_GET_REV_CMD_struct */
-+	u8   nothing;
-+} Si2158_GET_REV_CMD_struct;
-+
-+
-+typedef struct { /* Si2158_GET_REV_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+	u8   pn;
-+	u8   fwmajor;
-+	u8   fwminor;
-+	u16  patch;
-+	u8   cmpmajor;
-+	u8   cmpminor;
-+	u8   cmpbuild;
-+	u8   chiprev;
-+}  Si2158_GET_REV_CMD_REPLY_struct;
-+
-+/* GET_REV command, PN field definition (address 1, size 8, lsb 0, unsigned)*/
-+#define Si2158_GET_REV_RESPONSE_PN_LSB         0
-+#define Si2158_GET_REV_RESPONSE_PN_MASK        0xff
-+/* GET_REV command, FWMAJOR field definition (address 2, size 8, lsb 0, unsigned)*/
-+#define Si2158_GET_REV_RESPONSE_FWMAJOR_LSB         0
-+#define Si2158_GET_REV_RESPONSE_FWMAJOR_MASK        0xff
-+/* GET_REV command, FWMINOR field definition (address 3, size 8, lsb 0, unsigned)*/
-+#define Si2158_GET_REV_RESPONSE_FWMINOR_LSB         0
-+#define Si2158_GET_REV_RESPONSE_FWMINOR_MASK        0xff
-+/* GET_REV command, PATCH field definition (address 4, size 16, lsb 0, unsigned)*/
-+#define Si2158_GET_REV_RESPONSE_PATCH_LSB         0
-+#define Si2158_GET_REV_RESPONSE_PATCH_MASK        0xffff
-+/* GET_REV command, CMPMAJOR field definition (address 6, size 8, lsb 0, unsigned)*/
-+#define Si2158_GET_REV_RESPONSE_CMPMAJOR_LSB         0
-+#define Si2158_GET_REV_RESPONSE_CMPMAJOR_MASK        0xff
-+/* GET_REV command, CMPMINOR field definition (address 7, size 8, lsb 0, unsigned)*/
-+#define Si2158_GET_REV_RESPONSE_CMPMINOR_LSB         0
-+#define Si2158_GET_REV_RESPONSE_CMPMINOR_MASK        0xff
-+/* GET_REV command, CMPBUILD field definition (address 8, size 8, lsb 0, unsigned)*/
-+#define Si2158_GET_REV_RESPONSE_CMPBUILD_LSB         0
-+#define Si2158_GET_REV_RESPONSE_CMPBUILD_MASK        0xff
-+#define Si2158_GET_REV_RESPONSE_CMPBUILD_CMPBUILD_MIN  0
-+#define Si2158_GET_REV_RESPONSE_CMPBUILD_CMPBUILD_MAX  255
-+/* GET_REV command, CHIPREV field definition (address 9, size 4, lsb 0, unsigned)*/
-+#define Si2158_GET_REV_RESPONSE_CHIPREV_LSB         0
-+#define Si2158_GET_REV_RESPONSE_CHIPREV_MASK        0x0f
-+#define Si2158_GET_REV_RESPONSE_CHIPREV_A  1
-+#define Si2158_GET_REV_RESPONSE_CHIPREV_B  2
-+
-+
-+/* Si2158_PART_INFO command definition */
-+#define Si2158_PART_INFO_CMD 0x02
-+
-+#define Si2158_PART_INFO_CMD_CODE 0x010002
-+
-+typedef struct { /* Si2158_PART_INFO_CMD_struct */
-+	u8   nothing;
-+} Si2158_PART_INFO_CMD_struct;
-+
-+
-+typedef struct { /* Si2158_PART_INFO_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+	u8   chiprev;
-+	u8   romid;
-+	u8   part;
-+	u8   pmajor;
-+	u8   pminor;
-+	u8   pbuild;
-+	u16  reserved;
-+	u32  serial;
-+}  Si2158_PART_INFO_CMD_REPLY_struct;
-+
-+/* PART_INFO command, CHIPREV field definition (address 1, size 4, lsb 0, unsigned)*/
-+#define Si2158_PART_INFO_RESPONSE_CHIPREV_LSB         0
-+#define Si2158_PART_INFO_RESPONSE_CHIPREV_MASK        0x0f
-+#define Si2158_PART_INFO_RESPONSE_CHIPREV_A  1
-+#define Si2158_PART_INFO_RESPONSE_CHIPREV_B  2
-+/* PART_INFO command, ROMID field definition (address 12, size 8, lsb 0, unsigned)*/
-+#define Si2158_PART_INFO_RESPONSE_ROMID_LSB         0
-+#define Si2158_PART_INFO_RESPONSE_ROMID_MASK        0xff
-+/* PART_INFO command, PART field definition (address 2, size 8, lsb 0, unsigned)*/
-+#define Si2158_PART_INFO_RESPONSE_PART_LSB         0
-+#define Si2158_PART_INFO_RESPONSE_PART_MASK        0xff
-+/* PART_INFO command, PMAJOR field definition (address 3, size 8, lsb 0, unsigned)*/
-+#define Si2158_PART_INFO_RESPONSE_PMAJOR_LSB         0
-+#define Si2158_PART_INFO_RESPONSE_PMAJOR_MASK        0xff
-+/* PART_INFO command, PMINOR field definition (address 4, size 8, lsb 0, unsigned)*/
-+#define Si2158_PART_INFO_RESPONSE_PMINOR_LSB         0
-+#define Si2158_PART_INFO_RESPONSE_PMINOR_MASK        0xff
-+/* PART_INFO command, PBUILD field definition (address 5, size 8, lsb 0, unsigned)*/
-+#define Si2158_PART_INFO_RESPONSE_PBUILD_LSB         0
-+#define Si2158_PART_INFO_RESPONSE_PBUILD_MASK        0xff
-+/* PART_INFO command, RESERVED field definition (address 6, size 16, lsb 0, unsigned)*/
-+#define Si2158_PART_INFO_RESPONSE_RESERVED_LSB         0
-+#define Si2158_PART_INFO_RESPONSE_RESERVED_MASK        0xffff
-+/* PART_INFO command, SERIAL field definition (address 8, size 32, lsb 0, unsigned)*/
-+#define Si2158_PART_INFO_RESPONSE_SERIAL_LSB         0
-+#define Si2158_PART_INFO_RESPONSE_SERIAL_MASK        0xffffffff
-+
-+
-+/* Si2158_POWER_DOWN command definition */
-+#define Si2158_POWER_DOWN_CMD 0x13
-+
-+#define Si2158_POWER_DOWN_CMD_CODE 0x010013
-+
-+typedef struct { /* Si2158_POWER_DOWN_CMD_struct */
-+	u8   nothing;
-+} Si2158_POWER_DOWN_CMD_struct;
-+
-+
-+typedef struct { /* Si2158_POWER_DOWN_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+}  Si2158_POWER_DOWN_CMD_REPLY_struct;
-+
-+
-+/* Si2158_POWER_DOWN_HW command definition */
-+#define Si2158_POWER_DOWN_HW_CMD 0xc0
-+
-+#define Si2158_POWER_DOWN_HW_CMD_CODE 0x0200c0
-+
-+typedef struct { /* Si2158_POWER_DOWN_HW_CMD_struct */
-+	u8   subcode;
-+	u8   pd_xo_osc;
-+	u8   reserved1;
-+	u8   en_xout;
-+	u8   reserved2;
-+	u8   pd_ldo;
-+	u8   reserved3;
-+	u8   reserved4;
-+	u8   reserved5;
-+	u8   reserved6;
-+	u8   reserved7;
-+	u8   reserved8;
-+} Si2158_POWER_DOWN_HW_CMD_struct;
-+
-+typedef struct { /* Si2158_POWER_DOWN_HW_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+}  Si2158_POWER_DOWN_HW_CMD_REPLY_struct;
-+
-+/* POWER_DOWN_HW command, SUBCODE field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_DOWN_HW_CMD_SUBCODE_LSB         0
-+#define Si2158_POWER_DOWN_HW_CMD_SUBCODE_MASK        0xff
-+#define Si2158_POWER_DOWN_HW_CMD_SUBCODE_MIN         0
-+#define Si2158_POWER_DOWN_HW_CMD_SUBCODE_MAX         0
-+#define Si2158_POWER_DOWN_HW_CMD_SUBCODE_CODE  0
-+/* POWER_DOWN_HW command, PD_XO_OSC field definition (address 2,size 1, lsb 0, unsigned) */
-+#define Si2158_POWER_DOWN_HW_CMD_PD_XO_OSC_LSB         0
-+#define Si2158_POWER_DOWN_HW_CMD_PD_XO_OSC_MASK        0x01
-+#define Si2158_POWER_DOWN_HW_CMD_PD_XO_OSC_MIN         0
-+#define Si2158_POWER_DOWN_HW_CMD_PD_XO_OSC_MAX         1
-+#define Si2158_POWER_DOWN_HW_CMD_PD_XO_OSC_XO_OSC_POWER_DOWN  1
-+#define Si2158_POWER_DOWN_HW_CMD_PD_XO_OSC_XO_OSC_POWER_UP    0
-+/* POWER_DOWN_HW command, RESERVED1 field definition (address 2,size 1, lsb 1, unsigned) */
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED1_LSB         1
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED1_MASK        0x01
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED1_MIN         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED1_MAX         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED1_RESERVED  0
-+/* POWER_DOWN_HW command, EN_XOUT field definition (address 2,size 3, lsb 2, unsigned) */
-+#define Si2158_POWER_DOWN_HW_CMD_EN_XOUT_LSB         2
-+#define Si2158_POWER_DOWN_HW_CMD_EN_XOUT_MASK        0x07
-+#define Si2158_POWER_DOWN_HW_CMD_EN_XOUT_MIN         0
-+#define Si2158_POWER_DOWN_HW_CMD_EN_XOUT_MAX         3
-+#define Si2158_POWER_DOWN_HW_CMD_EN_XOUT_DIS_XOUT  0
-+#define Si2158_POWER_DOWN_HW_CMD_EN_XOUT_EN_XOUT   3
-+/* POWER_DOWN_HW command, RESERVED2 field definition (address 2,size 4, lsb 4, unsigned) */
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED2_LSB         5
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED2_MASK        0x07
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED2_MIN         1
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED2_MAX         1
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED2_RESERVED  1
-+/* POWER_DOWN_HW command, PD_LDO field definition (address 3,size 1, lsb 0, unsigned) */
-+#define Si2158_POWER_DOWN_HW_CMD_PD_LDO_LSB         0
-+#define Si2158_POWER_DOWN_HW_CMD_PD_LDO_MASK        0x01
-+#define Si2158_POWER_DOWN_HW_CMD_PD_LDO_MIN         0
-+#define Si2158_POWER_DOWN_HW_CMD_PD_LDO_MAX         1
-+#define Si2158_POWER_DOWN_HW_CMD_PD_LDO_LDO_POWER_DOWN  1
-+#define Si2158_POWER_DOWN_HW_CMD_PD_LDO_LDO_POWER_UP    0
-+/* POWER_DOWN_HW command, RESERVED3 field definition (address 4,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED3_LSB         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED3_MASK        0xff
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED3_MIN         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED3_MAX         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED3_RESERVED  0
-+/* POWER_DOWN_HW command, RESERVED4 field definition (address 5,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED4_LSB         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED4_MASK        0xff
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED4_MIN         1
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED4_MAX         1
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED4_RESERVED  1
-+/* POWER_DOWN_HW command, RESERVED5 field definition (address 6,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED5_LSB         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED5_MASK        0xff
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED5_MIN         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED5_MAX         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED5_RESERVED  0
-+/* POWER_DOWN_HW command, RESERVED6 field definition (address 7,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED6_LSB         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED6_MASK        0xff
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED6_MIN         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED6_MAX         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED6_RESERVED  0
-+/* POWER_DOWN_HW command, RESERVED7 field definition (address 8,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED7_LSB         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED7_MASK        0xff
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED7_MIN         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED7_MAX         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED7_RESERVED  0
-+/* POWER_DOWN_HW command, RESERVED8 field definition (address 9,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED8_LSB         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED8_MASK        0xff
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED8_MIN         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED8_MAX         0
-+#define Si2158_POWER_DOWN_HW_CMD_RESERVED8_RESERVED  0
-+
-+/* Si2158_POWER_UP command definition */
-+#define Si2158_POWER_UP_CMD 0xc0
-+
-+#define Si2158_POWER_UP_CMD_CODE 0x0300c0
-+
-+typedef struct { /* Si2158_POWER_UP_CMD_struct */
-+	u8   subcode;
-+//	u8   clock_mode;
-+//	u8   en_xout;
-+	u8   pd_ldo;
-+	u8   reserved2;
-+	u8   reserved3;
-+	u8   reserved4;
-+	u8   reserved5;
-+	u8   reserved6;
-+	u8   reserved7;
-+	u8   reset;
-+	u8   clock_freq;
-+	u8   reserved8;
-+	u8   func;
-+#ifndef __SI2158__
-+	u8   reserved9;
-+#endif /* __SI2158__ */
-+	u8   ctsien;
-+	u8   wake_up;
-+} Si2158_POWER_UP_CMD_struct;
-+
-+
-+typedef struct { /* Si2158_POWER_UP_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+}  Si2158_POWER_UP_CMD_REPLY_struct;
-+
-+/* POWER_UP command, SUBCODE field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_UP_CMD_SUBCODE_LSB         0
-+#define Si2158_POWER_UP_CMD_SUBCODE_MASK        0xff
-+#define Si2158_POWER_UP_CMD_SUBCODE_MIN         0
-+#define Si2158_POWER_UP_CMD_SUBCODE_MAX         0
-+#define Si2158_POWER_UP_CMD_SUBCODE_CODE  0
-+/* POWER_UP command, CLOCK_MODE field definition (address 2,size 2, lsb 0, unsigned) */
-+#define Si2158_POWER_UP_CMD_CLOCK_MODE_LSB         0
-+#define Si2158_POWER_UP_CMD_CLOCK_MODE_MASK        0x03
-+#define Si2158_POWER_UP_CMD_CLOCK_MODE_MIN         0
-+#define Si2158_POWER_UP_CMD_CLOCK_MODE_MAX         2
-+#define Si2158_POWER_UP_CMD_CLOCK_MODE_EXTCLK  2
-+#define Si2158_POWER_UP_CMD_CLOCK_MODE_XTAL    0
-+/* POWER_UP command, EN_XOUT field definition (address 2,size 3, lsb 2, unsigned) */
-+#define Si2158_POWER_UP_CMD_EN_XOUT_LSB         2
-+#define Si2158_POWER_UP_CMD_EN_XOUT_MASK        0x07
-+#define Si2158_POWER_UP_CMD_EN_XOUT_MIN         0
-+#define Si2158_POWER_UP_CMD_EN_XOUT_MAX         3
-+#define Si2158_POWER_UP_CMD_EN_XOUT_DIS_XOUT  0
-+#define Si2158_POWER_UP_CMD_EN_XOUT_EN_XOUT   3
-+/* POWER_UP command, PD_LDO field definition (address 3,size 1, lsb 0, unsigned) */
-+#define Si2158_POWER_UP_CMD_PD_LDO_LSB         0
-+#define Si2158_POWER_UP_CMD_PD_LDO_MASK        0x01
-+#define Si2158_POWER_UP_CMD_PD_LDO_MIN         0
-+#define Si2158_POWER_UP_CMD_PD_LDO_MAX         1
-+#define Si2158_POWER_UP_CMD_PD_LDO_LDO_POWER_DOWN  1
-+#define Si2158_POWER_UP_CMD_PD_LDO_LDO_POWER_UP    0
-+/* POWER_UP command, RESERVED2 field definition (address 4,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_UP_CMD_RESERVED2_LSB         0
-+#define Si2158_POWER_UP_CMD_RESERVED2_MASK        0xff
-+#define Si2158_POWER_UP_CMD_RESERVED2_MIN         0
-+#define Si2158_POWER_UP_CMD_RESERVED2_MAX         0
-+#define Si2158_POWER_UP_CMD_RESERVED2_RESERVED  0
-+/* POWER_UP command, RESERVED3 field definition (address 5,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_UP_CMD_RESERVED3_LSB         0
-+#define Si2158_POWER_UP_CMD_RESERVED3_MASK        0xff
-+#define Si2158_POWER_UP_CMD_RESERVED3_MIN         1
-+#define Si2158_POWER_UP_CMD_RESERVED3_MAX         1
-+#define Si2158_POWER_UP_CMD_RESERVED3_RESERVED  1
-+/* POWER_UP command, RESERVED4 field definition (address 6,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_UP_CMD_RESERVED4_LSB         0
-+#define Si2158_POWER_UP_CMD_RESERVED4_MASK        0xff
-+#define Si2158_POWER_UP_CMD_RESERVED4_MIN         1
-+#define Si2158_POWER_UP_CMD_RESERVED4_MAX         1
-+#define Si2158_POWER_UP_CMD_RESERVED4_RESERVED  1
-+/* POWER_UP command, RESERVED5 field definition (address 7,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_UP_CMD_RESERVED5_LSB         0
-+#define Si2158_POWER_UP_CMD_RESERVED5_MASK        0xff
-+#define Si2158_POWER_UP_CMD_RESERVED5_MIN         1
-+#define Si2158_POWER_UP_CMD_RESERVED5_MAX         1
-+#define Si2158_POWER_UP_CMD_RESERVED5_RESERVED  1
-+/* POWER_UP command, RESERVED6 field definition (address 8,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_UP_CMD_RESERVED6_LSB         0
-+#define Si2158_POWER_UP_CMD_RESERVED6_MASK        0xff
-+#define Si2158_POWER_UP_CMD_RESERVED6_MIN         1
-+#define Si2158_POWER_UP_CMD_RESERVED6_MAX         1
-+#define Si2158_POWER_UP_CMD_RESERVED6_RESERVED  1
-+/* POWER_UP command, RESERVED7 field definition (address 9,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_UP_CMD_RESERVED7_LSB         0
-+#define Si2158_POWER_UP_CMD_RESERVED7_MASK        0xff
-+#define Si2158_POWER_UP_CMD_RESERVED7_MIN         1
-+#define Si2158_POWER_UP_CMD_RESERVED7_MAX         1
-+#define Si2158_POWER_UP_CMD_RESERVED7_RESERVED  1
-+/* POWER_UP command, RESET field definition (address 10,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_UP_CMD_RESET_LSB         0
-+#define Si2158_POWER_UP_CMD_RESET_MASK        0xff
-+#define Si2158_POWER_UP_CMD_RESET_MIN         1
-+#define Si2158_POWER_UP_CMD_RESET_MAX         1
-+#define Si2158_POWER_UP_CMD_RESET_RESET  1
-+/* POWER_UP command, CLOCK_FREQ field definition (address 11,size 2, lsb 0, unsigned) */
-+#define Si2158_POWER_UP_CMD_CLOCK_FREQ_LSB         0
-+#define Si2158_POWER_UP_CMD_CLOCK_FREQ_MASK        0x03
-+#define Si2158_POWER_UP_CMD_CLOCK_FREQ_MIN         0
-+#define Si2158_POWER_UP_CMD_CLOCK_FREQ_MAX         3
-+#define Si2158_POWER_UP_CMD_CLOCK_FREQ_CLK_24MHZ  2
-+/* POWER_UP command, RESERVED8 field definition (address 12,size 8, lsb 0, unsigned) */
-+#define Si2158_POWER_UP_CMD_RESERVED8_LSB         0
-+#define Si2158_POWER_UP_CMD_RESERVED8_MASK        0xff
-+#define Si2158_POWER_UP_CMD_RESERVED8_MIN         0
-+#define Si2158_POWER_UP_CMD_RESERVED8_MAX         0
-+#define Si2158_POWER_UP_CMD_RESERVED8_RESERVED  0
-+/* POWER_UP command, FUNC field definition (address 13,size 4, lsb 0, unsigned) */
-+#define Si2158_POWER_UP_CMD_FUNC_LSB         0
-+#define Si2158_POWER_UP_CMD_FUNC_MASK        0x07
-+#define Si2158_POWER_UP_CMD_FUNC_MIN         0
-+#define Si2158_POWER_UP_CMD_FUNC_MAX         1
-+#define Si2158_POWER_UP_CMD_FUNC_BOOTLOADER  0
-+#define Si2158_POWER_UP_CMD_FUNC_NORMAL      1
-+#ifdef __SI2157__
-+/* POWER_UP command, RESERVED9 field definition (address 13,size 4, lsb 3, unsigned) */
-+#define Si2157_POWER_UP_CMD_RESERVED9_LSB         3
-+#define Si2157_POWER_UP_CMD_RESERVED9_MASK        0x0f
-+#define Si2157_POWER_UP_CMD_RESERVED9_MIN         0
-+#define Si2157_POWER_UP_CMD_RESERVED9_MAX         0
-+#define Si2157_POWER_UP_CMD_RESERVED9_RESERVED  0
-+#endif /* __SI2157__ */
-+/* POWER_UP command, CTSIEN field definition (address 13,size 1, lsb 7, unsigned) */
-+#define Si2158_POWER_UP_CMD_CTSIEN_LSB         7
-+#define Si2158_POWER_UP_CMD_CTSIEN_MASK        0x01
-+#define Si2158_POWER_UP_CMD_CTSIEN_MIN         0
-+#define Si2158_POWER_UP_CMD_CTSIEN_MAX         1
-+#define Si2158_POWER_UP_CMD_CTSIEN_DISABLE  0
-+#define Si2158_POWER_UP_CMD_CTSIEN_ENABLE   1
-+/* POWER_UP command, WAKE_UP field definition (address 14,size 1, lsb 0, unsigned) */
-+#define Si2158_POWER_UP_CMD_WAKE_UP_LSB         0
-+#define Si2158_POWER_UP_CMD_WAKE_UP_MASK        0x01
-+#define Si2158_POWER_UP_CMD_WAKE_UP_MIN         1
-+#define Si2158_POWER_UP_CMD_WAKE_UP_MAX         1
-+#define Si2158_POWER_UP_CMD_WAKE_UP_WAKE_UP  1
-+
-+/* Si2158_RAM_CRC command definition */
-+#define Si2158_RAM_CRC_CMD 0x03
-+
-+#define Si2158_RAM_CRC_CMD_CODE 0x010003
-+
-+typedef struct { /* Si2158_RAM_CRC_CMD_struct */
-+	u8   nothing;
-+} Si2158_RAM_CRC_CMD_struct;
-+
-+typedef struct { /* Si2158_RAM_CRC_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+	u16 crc;
-+}  Si2158_RAM_CRC_CMD_REPLY_struct;
-+
-+/* RAM_CRC command, CRC field definition (address 2, size 16, lsb 0, unsigned)*/
-+#define Si2158_RAM_CRC_RESPONSE_CRC_LSB         0
-+#define Si2158_RAM_CRC_RESPONSE_CRC_MASK        0xffff
-+
-+
-+/* Si2158_SET_PROPERTY command definition */
-+#define Si2158_SET_PROPERTY_CMD 0x14
-+
-+#define Si2158_SET_PROPERTY_CMD_CODE 0x010014
-+
-+typedef struct { /* Si2158_SET_PROPERTY_CMD_struct */
-+	u8  reserved;
-+	u16 prop;
-+	u16 data;
-+} Si2158_SET_PROPERTY_CMD_struct;
-+
-+typedef struct { /* Si2158_SET_PROPERTY_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+	u8  reserved;
-+	u16 data;
-+}  Si2158_SET_PROPERTY_CMD_REPLY_struct;
-+
-+/* SET_PROPERTY command, RESERVED field definition (address 1,size 8, lsb 0, unsigned) */
-+#define Si2158_SET_PROPERTY_CMD_RESERVED_LSB         0
-+#define Si2158_SET_PROPERTY_CMD_RESERVED_MASK        0xff
-+#define Si2158_SET_PROPERTY_CMD_RESERVED_MIN         0
-+#define Si2158_SET_PROPERTY_CMD_RESERVED_MAX         255.0
-+/* SET_PROPERTY command, PROP field definition (address 2,size 16, lsb 0, unsigned) */
-+#define Si2158_SET_PROPERTY_CMD_PROP_LSB         0
-+#define Si2158_SET_PROPERTY_CMD_PROP_MASK        0xffff
-+#define Si2158_SET_PROPERTY_CMD_PROP_MIN         0
-+#define Si2158_SET_PROPERTY_CMD_PROP_MAX         65535
-+#define Si2158_SET_PROPERTY_CMD_PROP_PROP_MIN  0
-+#define Si2158_SET_PROPERTY_CMD_PROP_PROP_MAX  65535
-+/* SET_PROPERTY command, DATA field definition (address 4,size 16, lsb 0, unsigned) */
-+#define Si2158_SET_PROPERTY_CMD_DATA_LSB         0
-+#define Si2158_SET_PROPERTY_CMD_DATA_MASK        0xffff
-+#define Si2158_SET_PROPERTY_CMD_DATA_MIN         0
-+#define Si2158_SET_PROPERTY_CMD_DATA_MAX         65535
-+#define Si2158_SET_PROPERTY_CMD_DATA_DATA_MIN  0
-+#define Si2158_SET_PROPERTY_CMD_DATA_DATA_MAX  65535
-+/* SET_PROPERTY command, RESERVED field definition (address 1, size 8, lsb 0, unsigned)*/
-+#define Si2158_SET_PROPERTY_RESPONSE_RESERVED_LSB         0
-+#define Si2158_SET_PROPERTY_RESPONSE_RESERVED_MASK        0xff
-+#define Si2158_SET_PROPERTY_RESPONSE_RESERVED_RESERVED_MIN  0
-+#define Si2158_SET_PROPERTY_RESPONSE_RESERVED_RESERVED_MAX  0
-+/* SET_PROPERTY command, DATA field definition (address 2, size 16, lsb 0, unsigned)*/
-+#define Si2158_SET_PROPERTY_RESPONSE_DATA_LSB         0
-+#define Si2158_SET_PROPERTY_RESPONSE_DATA_MASK        0xffff
-+
-+
-+/* Si2158_STANDBY command definition */
-+#define Si2158_STANDBY_CMD 0x16
-+
-+#define Si2158_STANDBY_CMD_CODE 0x010016
-+
-+typedef struct { /* Si2158_STANDBY_CMD_struct */
-+	u8   type;
-+} Si2158_STANDBY_CMD_struct;
-+
-+
-+typedef struct { /* Si2158_STANDBY_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+}  Si2158_STANDBY_CMD_REPLY_struct;
-+
-+/* STANDBY command, TYPE field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2158_STANDBY_CMD_TYPE_LSB         0
-+#define Si2158_STANDBY_CMD_TYPE_MASK        0x01
-+#define Si2158_STANDBY_CMD_TYPE_MIN         0
-+#define Si2158_STANDBY_CMD_TYPE_MAX         1
-+#define Si2158_STANDBY_CMD_TYPE_LNA_OFF  1
-+#define Si2158_STANDBY_CMD_TYPE_LNA_ON   0
-+
-+/* Si2158_TUNER_STATUS command definition */
-+#define Si2158_TUNER_STATUS_CMD 0x42
-+
-+#define Si2158_TUNER_STATUS_CMD_CODE 0x010042
-+
-+typedef struct { /* Si2158_TUNER_STATUS_CMD_struct */
-+	u8   intack;
-+} Si2158_TUNER_STATUS_CMD_struct;
-+
-+
-+typedef struct { /* Si2158_TUNER_STATUS_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+	u8  tcint;
-+	u8  rssilint;
-+	u8  rssihint;
-+	s16 vco_code;
-+	u8  tc;
-+	u8  rssil;
-+	u8  rssih;
-+	s8  rssi;
-+	u32 freq;
-+	u8  mode;
-+}  Si2158_TUNER_STATUS_CMD_REPLY_struct;
-+
-+/* TUNER_STATUS command, INTACK field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2158_TUNER_STATUS_CMD_INTACK_LSB         0
-+#define Si2158_TUNER_STATUS_CMD_INTACK_MASK        0x01
-+#define Si2158_TUNER_STATUS_CMD_INTACK_MIN         0
-+#define Si2158_TUNER_STATUS_CMD_INTACK_MAX         1
-+#define Si2158_TUNER_STATUS_CMD_INTACK_CLEAR  1
-+#define Si2158_TUNER_STATUS_CMD_INTACK_OK     0
-+/* TUNER_STATUS command, TCINT field definition (address 1, size 1, lsb 0, unsigned)*/
-+#define Si2158_TUNER_STATUS_RESPONSE_TCINT_LSB         0
-+#define Si2158_TUNER_STATUS_RESPONSE_TCINT_MASK        0x01
-+#define Si2158_TUNER_STATUS_RESPONSE_TCINT_CHANGED    1
-+#define Si2158_TUNER_STATUS_RESPONSE_TCINT_NO_CHANGE  0
-+/* TUNER_STATUS command, RSSILINT field definition (address 1, size 1, lsb 1, unsigned)*/
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSILINT_LSB         1
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSILINT_MASK        0x01
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSILINT_CHANGED    1
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSILINT_NO_CHANGE  0
-+/* TUNER_STATUS command, RSSIHINT field definition (address 1, size 1, lsb 2, unsigned)*/
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSIHINT_LSB         2
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSIHINT_MASK        0x01
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSIHINT_CHANGED    1
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSIHINT_NO_CHANGE  0
-+/* TUNER_STATUS command, VCO_CODE field definition (address 10, size 16, lsb 0, signed)*/
-+#define Si2158_TUNER_STATUS_RESPONSE_VCO_CODE_LSB         0
-+#define Si2158_TUNER_STATUS_RESPONSE_VCO_CODE_MASK        0xffff
-+#define Si2158_TUNER_STATUS_RESPONSE_VCO_CODE_SHIFT       16
-+/* TUNER_STATUS command, TC field definition (address 2, size 1, lsb 0, unsigned)*/
-+#define Si2158_TUNER_STATUS_RESPONSE_TC_LSB         0
-+#define Si2158_TUNER_STATUS_RESPONSE_TC_MASK        0x01
-+#define Si2158_TUNER_STATUS_RESPONSE_TC_BUSY  0
-+#define Si2158_TUNER_STATUS_RESPONSE_TC_DONE  1
-+/* TUNER_STATUS command, RSSIL field definition (address 2, size 1, lsb 1, unsigned)*/
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSIL_LSB         1
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSIL_MASK        0x01
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSIL_LOW  1
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSIL_OK   0
-+/* TUNER_STATUS command, RSSIH field definition (address 2, size 1, lsb 2, unsigned)*/
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSIH_LSB         2
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSIH_MASK        0x01
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSIH_HIGH  1
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSIH_OK    0
-+/* TUNER_STATUS command, RSSI field definition (address 3, size 8, lsb 0, signed)*/
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSI_LSB         0
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSI_MASK        0xff
-+#define Si2158_TUNER_STATUS_RESPONSE_RSSI_SHIFT       24
-+/* TUNER_STATUS command, FREQ field definition (address 4, size 32, lsb 0, unsigned)*/
-+#define Si2158_TUNER_STATUS_RESPONSE_FREQ_LSB         0
-+#define Si2158_TUNER_STATUS_RESPONSE_FREQ_MASK        0xffffffff
-+/* TUNER_STATUS command, MODE field definition (address 8, size 1, lsb 0, unsigned)*/
-+#define Si2158_TUNER_STATUS_RESPONSE_MODE_LSB         0
-+#define Si2158_TUNER_STATUS_RESPONSE_MODE_MASK        0x01
-+#define Si2158_TUNER_STATUS_RESPONSE_MODE_ATV  1
-+#define Si2158_TUNER_STATUS_RESPONSE_MODE_DTV  0
-+
-+
-+/* Si2158_TUNER_TUNE_FREQ command definition */
-+#define Si2158_TUNER_TUNE_FREQ_CMD 0x41
-+
-+#define Si2158_TUNER_TUNE_FREQ_CMD_CODE 0x010041
-+
-+typedef struct { /* Si2158_TUNER_TUNE_FREQ_CMD_struct */
-+	u8  mode;
-+	u32 freq;
-+} Si2158_TUNER_TUNE_FREQ_CMD_struct;
-+
-+
-+typedef struct { /* Si2158_TUNER_TUNE_FREQ_CMD_REPLY_struct */
-+	silabs_tercab_status * STATUS;
-+}  Si2158_TUNER_TUNE_FREQ_CMD_REPLY_struct;
-+
-+/* TUNER_TUNE_FREQ command, MODE field definition (address 1,size 1, lsb 0, unsigned) */
-+#define Si2158_TUNER_TUNE_FREQ_CMD_MODE_LSB         0
-+#define Si2158_TUNER_TUNE_FREQ_CMD_MODE_MASK        0x01
-+#define Si2158_TUNER_TUNE_FREQ_CMD_MODE_MIN         0
-+#define Si2158_TUNER_TUNE_FREQ_CMD_MODE_MAX         1
-+#define Si2158_TUNER_TUNE_FREQ_CMD_MODE_ATV  1
-+#define Si2158_TUNER_TUNE_FREQ_CMD_MODE_DTV  0
-+/* TUNER_TUNE_FREQ command, FREQ field definition (address 4,size 32, lsb 0, unsigned) */
-+#define Si2158_TUNER_TUNE_FREQ_CMD_FREQ_LSB         0
-+#define Si2158_TUNER_TUNE_FREQ_CMD_FREQ_MASK        0xffffffff
-+#define Si2158_TUNER_TUNE_FREQ_CMD_FREQ_MIN         40000000
-+#define Si2158_TUNER_TUNE_FREQ_CMD_FREQ_MAX         1002000000
-+#define Si2158_TUNER_TUNE_FREQ_CMD_FREQ_FREQ_MIN  40000000
-+#define Si2158_TUNER_TUNE_FREQ_CMD_FREQ_FREQ_MAX  1002000000
-+
-+/* _commands_reply_struct_insertion_point */
-+
-+#ifdef _DEBUG
-+#define Si2158_GET_COMMAND_STRINGS
-+#endif
-+
-+/* Si2158 ATV_AFC_RANGE property definition */
-+#define Si2158_ATV_AFC_RANGE_PROP 0x0610
-+
-+#define Si2158_ATV_AFC_RANGE_PROP_CODE 0x000610
-+
-+typedef struct { /* Si2158_ATV_AFC_RANGE_PROP_struct */
-+	u16 range_khz;
-+} Si2158_ATV_AFC_RANGE_PROP_struct;
-+
-+/* ATV_AFC_RANGE property, RANGE_KHZ field definition (NO TITLE)*/
-+#define Si2158_ATV_AFC_RANGE_PROP_RANGE_KHZ_LSB         0
-+#define Si2158_ATV_AFC_RANGE_PROP_RANGE_KHZ_MASK        0xffff
-+#define Si2158_ATV_AFC_RANGE_PROP_RANGE_KHZ_DEFAULT    1000
-+#define Si2158_ATV_AFC_RANGE_PROP_RANGE_KHZ_RANGE_KHZ_MIN  0
-+#define Si2158_ATV_AFC_RANGE_PROP_RANGE_KHZ_RANGE_KHZ_MAX  65535
-+
-+
-+#ifdef __SI2177__
-+/* Si2177 ATV_AF_OUT property definition */
-+#define Si2177_ATV_AF_OUT_PROP 0x060b
-+
-+#define Si2177_ATV_AF_OUT_PROP_CODE 0x00060b
-+
-+
-+typedef struct { /* Si2177_ATV_AF_OUT_PROP_struct */
-+	u8   mute;
-+	u8   volume;
-+} Si2177_ATV_AF_OUT_PROP_struct;
-+
-+/* ATV_AF_OUT property, MUTE field definition (NO TITLE)*/
-+#define Si2177_ATV_AF_OUT_PROP_MUTE_LSB         6
-+#define Si2177_ATV_AF_OUT_PROP_MUTE_MASK        0x01
-+#define Si2177_ATV_AF_OUT_PROP_MUTE_DEFAULT    0
-+#define Si2177_ATV_AF_OUT_PROP_MUTE_NORMAL  0
-+#define Si2177_ATV_AF_OUT_PROP_MUTE_MUTE    1
-+
-+/* ATV_AF_OUT property, VOLUME field definition (NO TITLE)*/
-+#define Si2177_ATV_AF_OUT_PROP_VOLUME_LSB         0
-+#define Si2177_ATV_AF_OUT_PROP_VOLUME_MASK        0x3f
-+#define Si2177_ATV_AF_OUT_PROP_VOLUME_DEFAULT    0
-+#define Si2177_ATV_AF_OUT_PROP_VOLUME_VOLUME_MIN  0
-+#define Si2177_ATV_AF_OUT_PROP_VOLUME_VOLUME_MAX  63
-+#endif /* __SI2177__ */
-+
-+/* Si2158 ATV_AGC_SPEED property definition */
-+#define Si2158_ATV_AGC_SPEED_PROP 0x0611
-+
-+#define Si2158_ATV_AGC_SPEED_PROP_CODE 0x000611
-+
-+
-+typedef struct { /* Si2158_ATV_AGC_SPEED_PROP_struct */
-+	u8   if_agc_speed;
-+} Si2158_ATV_AGC_SPEED_PROP_struct;
-+
-+/* ATV_AGC_SPEED property, IF_AGC_SPEED field definition (NO TITLE)*/
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_LSB         0
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_MASK        0xff
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_DEFAULT    0
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_AUTO    0
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_89      89
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_105     105
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_121     121
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_137     137
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_158     158
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_172     172
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_178     178
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_185     185
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_196     196
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_206     206
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_216     216
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_219     219
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_222     222
-+#define Si2177_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_223     223
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_248     248
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_250     250
-+#define Si2158_ATV_AGC_SPEED_PROP_IF_AGC_SPEED_251     251
-+
-+
-+/* Si2158 ATV_AGC_SPEED_LOW_RSSI property definition */
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP 0x0623
-+
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_CODE 0x000623
-+
-+
-+typedef struct { /* Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_struct */
-+	u8 if_agc_speed;
-+	s8 thld;
-+} Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_struct;
-+
-+/* ATV_AGC_SPEED_LOW_RSSI property, IF_AGC_SPEED field definition (NO TITLE)*/
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_LSB         0
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_MASK        0xff
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_DEFAULT    158
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_89      89
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_105     105
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_121     121
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_137     137
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_158     158
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_172     172
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_178     178
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_185     185
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_196     196
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_206     206
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_216     216
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_219     219
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_222     222
-+#define Si2177_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_223     223
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_248     248
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_250     250
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_IF_AGC_SPEED_251     251
-+
-+/* ATV_AGC_SPEED_LOW_RSSI property, THLD field definition (NO TITLE)*/
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_THLD_LSB         8
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_THLD_MASK        0xff
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_THLD_DEFAULT    -128
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_THLD_THLD_MIN  -128
-+#define Si2158_ATV_AGC_SPEED_LOW_RSSI_PROP_THLD_THLD_MAX  127
-+
-+
-+/* Si2158 ATV_ARTIFICIAL_SNOW property definition */
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP 0x0624
-+
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_CODE 0x000624
-+
-+typedef struct { /* Si2158_ATV_ARTIFICIAL_SNOW_PROP_struct */
-+	u8 gain;
-+	s8 offset;
-+	u8 period;
-+	u8 sound;
-+} Si2158_ATV_ARTIFICIAL_SNOW_PROP_struct;
-+
-+/* ATV_ARTIFICIAL_SNOW property, GAIN field definition (NO TITLE)*/
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_LSB         0
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_MASK        0x0f
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_DEFAULT    0
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_AUTO  0
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_0DB   1
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_6DB   2
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_12DB  3
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_18DB  4
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_24DB  5
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_30DB  6
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_36DB  7
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_42DB  8
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_GAIN_OFF   9
-+
-+/* ATV_ARTIFICIAL_SNOW property, OFFSET field definition (NO TITLE)*/
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_OFFSET_LSB         8
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_OFFSET_MASK        0xff
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_OFFSET_DEFAULT    0
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_OFFSET_OFFSET_MIN  -128
-+#define Si2158_ATV_ARTIFICIAL_SNOW_PROP_OFFSET_OFFSET_MAX  127
-+
-+/* ATV_ARTIFICIAL_SNOW property, PERIOD field definition (NO TITLE)*/
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_PERIOD_LSB         7
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_PERIOD_MASK        0x01
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_PERIOD_DEFAULT    0
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_PERIOD_LONG   0
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_PERIOD_SHORT  1
-+
-+/* ATV_ARTIFICIAL_SNOW property, SOUND field definition (NO TITLE)*/
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_SOUND_LSB         4
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_SOUND_MASK        0x07
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_SOUND_DEFAULT    0
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_SOUND_MUTE          0
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_SOUND_6DB           1
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_SOUND_12DB          2
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_SOUND_18DB          3
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_SOUND_24DB          4
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_SOUND_30DB          5
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_SOUND_36DB          6
-+#define Si2177_ATV_ARTIFICIAL_SNOW_PROP_SOUND_PASS_THROUGH  7
-+
-+
-+#ifdef __SI2177__
-+/* Si2177 ATV_AUDIO_MODE property definition */
-+#define Si2177_ATV_AUDIO_MODE_PROP 0x0602
-+
-+#define Si2177_ATV_AUDIO_MODE_PROP_CODE 0x000602
-+
-+
-+typedef struct { /* Si2177_ATV_AUDIO_MODE_PROP_struct */
-+	u8   audio_sys;
-+	u8   chan_bw;
-+	u8   demod_mode;
-+} Si2177_ATV_AUDIO_MODE_PROP_struct;
-+
-+/* ATV_AUDIO_MODE property, AUDIO_SYS field definition (NO TITLE)*/
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_LSB         0
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_MASK        0x0f
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_DEFAULT    0
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_DEFAULT          0
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_MONO             1
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_MONO_NICAM       2
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_A2               3
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_A2_DK2           4
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_A2_DK3           5
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_BTSC             6
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_EIAJ             7
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_SCAN             8
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_A2_DK4           9
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_WIDE_SCAN        10
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_MONO_NICAM_6DB   11
-+#define Si2177_ATV_AUDIO_MODE_PROP_AUDIO_SYS_MONO_NICAM_10DB  12
-+
-+/* ATV_AUDIO_MODE property, CHAN_BW field definition (NO TITLE)*/
-+#define Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_LSB         8
-+#define Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_MASK        0x0f
-+#define Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_DEFAULT    0
-+#define Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_DEFAULT         0
-+#define Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_4X_OVERMOD      1
-+#define Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_8X_OVERMOD      2
-+#define Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_12X_OVERMOD     3
-+#define Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_7P5_KHZ_OFFSET  4
-+#define Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_15_KHZ_OFFSET   5
-+#define Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_30_KHZ_OFFSET   6
-+#define Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_75_KHZ_OFFSET   7
-+#define Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_150_KHZ_OFFSET  8
-+#define Si2177_ATV_AUDIO_MODE_PROP_CHAN_BW_CUSTOM          9
-+
-+/* ATV_AUDIO_MODE property, DEMOD_MODE field definition (NO TITLE)*/
-+#define Si2177_ATV_AUDIO_MODE_PROP_DEMOD_MODE_LSB         4
-+#define Si2177_ATV_AUDIO_MODE_PROP_DEMOD_MODE_MASK        0x03
-+#define Si2177_ATV_AUDIO_MODE_PROP_DEMOD_MODE_DEFAULT    0
-+#define Si2177_ATV_AUDIO_MODE_PROP_DEMOD_MODE_SIF  0
-+#define Si2177_ATV_AUDIO_MODE_PROP_DEMOD_MODE_AM   1
-+#define Si2177_ATV_AUDIO_MODE_PROP_DEMOD_MODE_FM1  2
-+#define Si2177_ATV_AUDIO_MODE_PROP_DEMOD_MODE_FM2  3
-+#endif /* __SI2177__ */
-+
-+/* Si2158 ATV_CONFIG_IF_PORT property definition */
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP 0x0603
-+
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP_CODE 0x000603
-+
-+typedef struct { /* Si2158_ATV_CONFIG_IF_PORT_PROP_struct */
-+	u8   atv_agc_source; /* Si2177 has no ATV_AGC_SOURCE */
-+	u8   atv_out_type;
-+} Si2158_ATV_CONFIG_IF_PORT_PROP_struct;
-+
-+/* ATV_CONFIG_IF_PORT property, ATV_AGC_SOURCE field definition (NO TITLE)*/
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_AGC_SOURCE_LSB         8
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_AGC_SOURCE_MASK        0x07
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_AGC_SOURCE_DEFAULT    0
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_AGC_SOURCE_INTERNAL  0
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_AGC_SOURCE_AGC1_3DB  1
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_AGC_SOURCE_AGC2_3DB  2
-+
-+/* ATV_CONFIG_IF_PORT property, ATV_OUT_TYPE field definition (NO TITLE)*/
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_LSB         0
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_MASK        0x0f
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_DEFAULT    8
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_LIF_DIFF_IF1  8
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_LIF_DIFF_IF2  10
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_LIF_SE_IF1A   12
-+#define Si2158_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_LIF_SE_IF2A   14
-+#ifdef __SI2177__
-+/* ATV_CONFIG_IF_PORT property, ATV_OUT_TYPE field definition (NO TITLE)*/
-+#define Si2177_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_LSB         0
-+#define Si2177_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_MASK        0x0f
-+#define Si2177_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_DEFAULT    0
-+#define Si2177_ATV_CONFIG_IF_PORT_PROP_ATV_OUT_TYPE_CVBS_IF2B_SOUND_IF2A  0
-+#endif /* __SI2177__ */
-+
-+
-+#ifdef __SI2177__
-+/* Si2177 ATV_CVBS_OUT property definition */
-+#define Si2177_ATV_CVBS_OUT_PROP 0x0609
-+
-+#define Si2177_ATV_CVBS_OUT_PROP_CODE 0x000609
-+
-+
-+typedef struct { /* Si2177_ATV_CVBS_OUT_PROP_struct */
-+	u8   amp;
-+	u8   offset;
-+} Si2177_ATV_CVBS_OUT_PROP_struct;
-+
-+/* ATV_CVBS_OUT property, AMP field definition (NO TITLE)*/
-+#define Si2177_ATV_CVBS_OUT_PROP_AMP_LSB         8
-+#define Si2177_ATV_CVBS_OUT_PROP_AMP_MASK        0xff
-+#define Si2177_ATV_CVBS_OUT_PROP_AMP_DEFAULT    200
-+#define Si2177_ATV_CVBS_OUT_PROP_AMP_AMP_MIN  0
-+#define Si2177_ATV_CVBS_OUT_PROP_AMP_AMP_MAX  255
-+
-+/* ATV_CVBS_OUT property, OFFSET field definition (NO TITLE)*/
-+#define Si2177_ATV_CVBS_OUT_PROP_OFFSET_LSB         0
-+#define Si2177_ATV_CVBS_OUT_PROP_OFFSET_MASK        0xff
-+#define Si2177_ATV_CVBS_OUT_PROP_OFFSET_DEFAULT    25
-+#define Si2177_ATV_CVBS_OUT_PROP_OFFSET_OFFSET_MIN  0
-+#define Si2177_ATV_CVBS_OUT_PROP_OFFSET_OFFSET_MAX  255
-+
-+
-+/* Si2177 ATV_CVBS_OUT_FINE property definition */
-+#define Si2177_ATV_CVBS_OUT_FINE_PROP 0x0614
-+#define Si2177_ATV_CVBS_OUT_FINE_PROP_CODE 0x000614
-+
-+typedef struct { /* Si2177_ATV_CVBS_OUT_FINE_PROP_struct */
-+	u8 amp;
-+	s8 offset;
-+} Si2177_ATV_CVBS_OUT_FINE_PROP_struct;
-+
-+/* ATV_CVBS_OUT_FINE property, AMP field definition (NO TITLE)*/
-+#define Si2177_ATV_CVBS_OUT_FINE_PROP_AMP_LSB         8
-+#define Si2177_ATV_CVBS_OUT_FINE_PROP_AMP_MASK        0xff
-+#define Si2177_ATV_CVBS_OUT_FINE_PROP_AMP_DEFAULT    100
-+#define Si2177_ATV_CVBS_OUT_FINE_PROP_AMP_AMP_MIN  25
-+#define Si2177_ATV_CVBS_OUT_FINE_PROP_AMP_AMP_MAX  100
-+
-+/* ATV_CVBS_OUT_FINE property, OFFSET field definition (NO TITLE)*/
-+#define Si2177_ATV_CVBS_OUT_FINE_PROP_OFFSET_LSB         0
-+#define Si2177_ATV_CVBS_OUT_FINE_PROP_OFFSET_MASK        0xff
-+#define Si2177_ATV_CVBS_OUT_FINE_PROP_OFFSET_DEFAULT    0
-+#define Si2177_ATV_CVBS_OUT_FINE_PROP_OFFSET_OFFSET_MIN  -128
-+#define Si2177_ATV_CVBS_OUT_FINE_PROP_OFFSET_OFFSET_MAX  127
-+#endif /* __SI2177__ */
-+
-+/* Si2158 ATV_EXT_AGC property definition */
-+#define Si2158_ATV_EXT_AGC_PROP 0x0607
-+
-+#define Si2158_ATV_EXT_AGC_PROP_CODE 0x000607
-+
-+typedef struct { /* Si2158_ATV_EXT_AGC_PROP_struct */
-+	u8   max_10mv;
-+	u8   min_10mv;
-+} Si2158_ATV_EXT_AGC_PROP_struct;
-+
-+/* ATV_EXT_AGC property, MAX_10MV field definition (NO TITLE)*/
-+#define Si2158_ATV_EXT_AGC_PROP_MAX_10MV_LSB         8
-+#define Si2158_ATV_EXT_AGC_PROP_MAX_10MV_MASK        0xff
-+#define Si2158_ATV_EXT_AGC_PROP_MAX_10MV_DEFAULT    200
-+#define Si2158_ATV_EXT_AGC_PROP_MAX_10MV_MAX_10MV_MIN  0
-+#define Si2158_ATV_EXT_AGC_PROP_MAX_10MV_MAX_10MV_MAX  255
-+
-+/* ATV_EXT_AGC property, MIN_10MV field definition (NO TITLE)*/
-+#define Si2158_ATV_EXT_AGC_PROP_MIN_10MV_LSB         0
-+#define Si2158_ATV_EXT_AGC_PROP_MIN_10MV_MASK        0xff
-+#define Si2158_ATV_EXT_AGC_PROP_MIN_10MV_DEFAULT    50
-+#define Si2158_ATV_EXT_AGC_PROP_MIN_10MV_MIN_10MV_MIN  0
-+#define Si2158_ATV_EXT_AGC_PROP_MIN_10MV_MIN_10MV_MAX  255
-+
-+#ifdef __SI2177__
-+/* Si2177 ATV_HSYNC_OUT property definition */
-+#define Si2177_ATV_HSYNC_OUT_PROP 0x0627
-+#define Si2177_ATV_HSYNC_OUT_PROP_CODE 0x000627
-+
-+typedef struct { /* Si2177_ATV_HSYNC_OUT_PROP_struct */
-+	u8 gpio_sel;
-+	s8 offset;
-+	u8 width;
-+} Si2177_ATV_HSYNC_OUT_PROP_struct;
-+
-+/* ATV_HSYNC_OUT property, GPIO_SEL field definition (NO TITLE)*/
-+#define Si2177_ATV_HSYNC_OUT_PROP_GPIO_SEL_LSB         0
-+#define Si2177_ATV_HSYNC_OUT_PROP_GPIO_SEL_MASK        0x03
-+#define Si2177_ATV_HSYNC_OUT_PROP_GPIO_SEL_DEFAULT    0
-+#define Si2177_ATV_HSYNC_OUT_PROP_GPIO_SEL_NONE   0
-+#define Si2177_ATV_HSYNC_OUT_PROP_GPIO_SEL_GPIO1  1
-+#define Si2177_ATV_HSYNC_OUT_PROP_GPIO_SEL_GPIO2  2
-+
-+/* ATV_HSYNC_OUT property, OFFSET field definition (NO TITLE)*/
-+#define Si2177_ATV_HSYNC_OUT_PROP_OFFSET_LSB         8
-+#define Si2177_ATV_HSYNC_OUT_PROP_OFFSET_MASK        0xff
-+#define Si2177_ATV_HSYNC_OUT_PROP_OFFSET_DEFAULT    0
-+#define Si2177_ATV_HSYNC_OUT_PROP_OFFSET_OFFSET_MIN  -128
-+#define Si2177_ATV_HSYNC_OUT_PROP_OFFSET_OFFSET_MAX  127
-+
-+/* ATV_HSYNC_OUT property, WIDTH field definition (NO TITLE)*/
-+#define Si2177_ATV_HSYNC_OUT_PROP_WIDTH_LSB         2
-+#define Si2177_ATV_HSYNC_OUT_PROP_WIDTH_MASK        0x3f
-+#define Si2177_ATV_HSYNC_OUT_PROP_WIDTH_DEFAULT    42
-+#define Si2177_ATV_HSYNC_OUT_PROP_WIDTH_WIDTH_MIN  0
-+#define Si2177_ATV_HSYNC_OUT_PROP_WIDTH_WIDTH_MAX  51
-+#endif /* __SI2177__ */
-+
-+/* Si2158 ATV_IEN property definition */
-+#define Si2158_ATV_IEN_PROP 0x0601
-+
-+#define Si2158_ATV_IEN_PROP_CODE 0x000601
-+
-+
-+#ifdef __SI2158__
-+typedef struct { /* Si2158_ATV_IEN_PROP_struct */
-+	u8   chlien;
-+	u8   pclien;
-+} Si2158_ATV_IEN_PROP_struct;
-+#endif /* __SI2158__ */
-+
-+#ifdef __SI2177__
-+typedef struct { /* Si2177_ATV_IEN_PROP_struct */
-+	u8   chlien;
-+	u8   dlien;
-+	u8   pclien;
-+	u8   snrhien;
-+	u8   snrlien;
-+} Si2158_ATV_IEN_PROP_struct;
-+#endif /* __SI2177__ */
-+
-+/* ATV_IEN property, CHLIEN field definition (NO TITLE)*/
-+#define Si2158_ATV_IEN_PROP_CHLIEN_LSB         0
-+#define Si2158_ATV_IEN_PROP_CHLIEN_MASK        0x01
-+#define Si2158_ATV_IEN_PROP_CHLIEN_DEFAULT    1
-+#define Si2158_ATV_IEN_PROP_CHLIEN_DISABLE  0
-+#define Si2158_ATV_IEN_PROP_CHLIEN_ENABLE   1
-+
-+#ifdef __SI2177__
-+/* ATV_IEN property, DLIEN field definition (NO TITLE)*/
-+#define Si2177_ATV_IEN_PROP_DLIEN_LSB         2
-+#define Si2177_ATV_IEN_PROP_DLIEN_MASK        0x01
-+#define Si2177_ATV_IEN_PROP_DLIEN_DEFAULT    0
-+#define Si2177_ATV_IEN_PROP_DLIEN_DISABLE  0
-+#define Si2177_ATV_IEN_PROP_DLIEN_ENABLE   1
-+#endif /* __SI2177__ */
-+
-+/* ATV_IEN property, PCLIEN field definition (NO TITLE)*/
-+#define Si2158_ATV_IEN_PROP_PCLIEN_LSB         1
-+#define Si2158_ATV_IEN_PROP_PCLIEN_MASK        0x01
-+#define Si2158_ATV_IEN_PROP_PCLIEN_DEFAULT    0
-+#define Si2158_ATV_IEN_PROP_PCLIEN_DISABLE  0
-+#define Si2158_ATV_IEN_PROP_PCLIEN_ENABLE   1
-+
-+#ifdef __SI2177__
-+/* ATV_IEN property, SNRHIEN field definition (NO TITLE)*/
-+#define Si2177_ATV_IEN_PROP_SNRHIEN_LSB         4
-+#define Si2177_ATV_IEN_PROP_SNRHIEN_MASK        0x01
-+#define Si2177_ATV_IEN_PROP_SNRHIEN_DEFAULT    0
-+#define Si2177_ATV_IEN_PROP_SNRHIEN_DISABLE  0
-+#define Si2177_ATV_IEN_PROP_SNRHIEN_ENABLE   1
-+
-+/* ATV_IEN property, SNRLIEN field definition (NO TITLE)*/
-+#define Si2177_ATV_IEN_PROP_SNRLIEN_LSB         3
-+#define Si2177_ATV_IEN_PROP_SNRLIEN_MASK        0x01
-+#define Si2177_ATV_IEN_PROP_SNRLIEN_DEFAULT    0
-+#define Si2177_ATV_IEN_PROP_SNRLIEN_DISABLE  0
-+#define Si2177_ATV_IEN_PROP_SNRLIEN_ENABLE   1
-+#endif /* __SI2177__ */
-+
-+
-+/* Si2158 ATV_INT_SENSE property definition */
-+#define Si2158_ATV_INT_SENSE_PROP 0x0613
-+
-+#define Si2158_ATV_INT_SENSE_PROP_CODE 0x000613
-+
-+
-+#ifdef __SI2158__
-+typedef struct { /* Si2158_ATV_INT_SENSE_PROP_struct */
-+	u8   chlnegen;
-+	u8   chlposen;
-+	u8   pclnegen;
-+	u8   pclposen;
-+} Si2158_ATV_INT_SENSE_PROP_struct;
-+#endif /* __SI2158__ */
-+
-+#ifdef __SI2177__
-+typedef struct { /* Si2177_ATV_INT_SENSE_PROP_struct */
-+	u8   chlnegen;
-+	u8   chlposen;
-+	u8   dlnegen;
-+	u8   dlposen;
-+	u8   pclnegen;
-+	u8   pclposen;
-+	u8   snrhnegen;
-+	u8   snrhposen;
-+	u8   snrlnegen;
-+	u8   snrlposen;
-+} Si2158_ATV_INT_SENSE_PROP_struct;
-+#endif /* __SI2177__ */
-+
-+/* ATV_INT_SENSE property, CHLNEGEN field definition (NO TITLE)*/
-+#define Si2158_ATV_INT_SENSE_PROP_CHLNEGEN_LSB         0
-+#define Si2158_ATV_INT_SENSE_PROP_CHLNEGEN_MASK        0x01
-+#define Si2158_ATV_INT_SENSE_PROP_CHLNEGEN_DEFAULT    0
-+#define Si2158_ATV_INT_SENSE_PROP_CHLNEGEN_DISABLE  0
-+#define Si2158_ATV_INT_SENSE_PROP_CHLNEGEN_ENABLE   1
-+
-+/* ATV_INT_SENSE property, CHLPOSEN field definition (NO TITLE)*/
-+#define Si2158_ATV_INT_SENSE_PROP_CHLPOSEN_LSB         8
-+#define Si2158_ATV_INT_SENSE_PROP_CHLPOSEN_MASK        0x01
-+#define Si2158_ATV_INT_SENSE_PROP_CHLPOSEN_DEFAULT    1
-+#define Si2158_ATV_INT_SENSE_PROP_CHLPOSEN_DISABLE  0
-+#define Si2158_ATV_INT_SENSE_PROP_CHLPOSEN_ENABLE   1
-+
-+#ifdef __SI2177__
-+/* ATV_INT_SENSE property, DLNEGEN field definition (NO TITLE)*/
-+#define Si2177_ATV_INT_SENSE_PROP_DLNEGEN_LSB         2
-+#define Si2177_ATV_INT_SENSE_PROP_DLNEGEN_MASK        0x01
-+#define Si2177_ATV_INT_SENSE_PROP_DLNEGEN_DEFAULT    0
-+#define Si2177_ATV_INT_SENSE_PROP_DLNEGEN_DISABLE  0
-+#define Si2177_ATV_INT_SENSE_PROP_DLNEGEN_ENABLE   1
-+
-+/* ATV_INT_SENSE property, DLPOSEN field definition (NO TITLE)*/
-+#define Si2177_ATV_INT_SENSE_PROP_DLPOSEN_LSB         10
-+#define Si2177_ATV_INT_SENSE_PROP_DLPOSEN_MASK        0x01
-+#define Si2177_ATV_INT_SENSE_PROP_DLPOSEN_DEFAULT    1
-+#define Si2177_ATV_INT_SENSE_PROP_DLPOSEN_DISABLE  0
-+#define Si2177_ATV_INT_SENSE_PROP_DLPOSEN_ENABLE   1
-+
-+#endif /* __SI2177__ */
-+/* ATV_INT_SENSE property, PCLNEGEN field definition (NO TITLE)*/
-+#define Si2158_ATV_INT_SENSE_PROP_PCLNEGEN_LSB         1
-+#define Si2158_ATV_INT_SENSE_PROP_PCLNEGEN_MASK        0x01
-+#define Si2158_ATV_INT_SENSE_PROP_PCLNEGEN_DEFAULT    0
-+#define Si2158_ATV_INT_SENSE_PROP_PCLNEGEN_DISABLE  0
-+#define Si2158_ATV_INT_SENSE_PROP_PCLNEGEN_ENABLE   1
-+
-+/* ATV_INT_SENSE property, PCLPOSEN field definition (NO TITLE)*/
-+#define Si2158_ATV_INT_SENSE_PROP_PCLPOSEN_LSB         9
-+#define Si2158_ATV_INT_SENSE_PROP_PCLPOSEN_MASK        0x01
-+#define Si2158_ATV_INT_SENSE_PROP_PCLPOSEN_DEFAULT    1
-+#define Si2158_ATV_INT_SENSE_PROP_PCLPOSEN_DISABLE  0
-+#define Si2158_ATV_INT_SENSE_PROP_PCLPOSEN_ENABLE   1
-+
-+
-+#ifdef __SI2177__
-+/* ATV_INT_SENSE property, SNRHNEGEN field definition (NO TITLE)*/
-+#define Si2177_ATV_INT_SENSE_PROP_SNRHNEGEN_LSB         4
-+#define Si2177_ATV_INT_SENSE_PROP_SNRHNEGEN_MASK        0x01
-+#define Si2177_ATV_INT_SENSE_PROP_SNRHNEGEN_DEFAULT    0
-+#define Si2177_ATV_INT_SENSE_PROP_SNRHNEGEN_DISABLE  0
-+#define Si2177_ATV_INT_SENSE_PROP_SNRHNEGEN_ENABLE   1
-+
-+/* ATV_INT_SENSE property, SNRHPOSEN field definition (NO TITLE)*/
-+#define Si2177_ATV_INT_SENSE_PROP_SNRHPOSEN_LSB         12
-+#define Si2177_ATV_INT_SENSE_PROP_SNRHPOSEN_MASK        0x01
-+#define Si2177_ATV_INT_SENSE_PROP_SNRHPOSEN_DEFAULT    1
-+#define Si2177_ATV_INT_SENSE_PROP_SNRHPOSEN_DISABLE  0
-+#define Si2177_ATV_INT_SENSE_PROP_SNRHPOSEN_ENABLE   1
-+
-+/* ATV_INT_SENSE property, SNRLNEGEN field definition (NO TITLE)*/
-+#define Si2177_ATV_INT_SENSE_PROP_SNRLNEGEN_LSB         3
-+#define Si2177_ATV_INT_SENSE_PROP_SNRLNEGEN_MASK        0x01
-+#define Si2177_ATV_INT_SENSE_PROP_SNRLNEGEN_DEFAULT    0
-+#define Si2177_ATV_INT_SENSE_PROP_SNRLNEGEN_DISABLE  0
-+#define Si2177_ATV_INT_SENSE_PROP_SNRLNEGEN_ENABLE   1
-+
-+/* ATV_INT_SENSE property, SNRLPOSEN field definition (NO TITLE)*/
-+#define Si2177_ATV_INT_SENSE_PROP_SNRLPOSEN_LSB         11
-+#define Si2177_ATV_INT_SENSE_PROP_SNRLPOSEN_MASK        0x01
-+#define Si2177_ATV_INT_SENSE_PROP_SNRLPOSEN_DEFAULT    1
-+#define Si2177_ATV_INT_SENSE_PROP_SNRLPOSEN_DISABLE  0
-+#define Si2177_ATV_INT_SENSE_PROP_SNRLPOSEN_ENABLE   1
-+#endif /* __SI2177__ */
-+
-+/* Si2158 ATV_LIF_FREQ property definition */
-+#define Si2158_ATV_LIF_FREQ_PROP 0x060c
-+
-+#define Si2158_ATV_LIF_FREQ_PROP_CODE 0x00060c
-+
-+typedef struct { /* Si2158_ATV_LIF_FREQ_PROP_struct */
-+	u16 offset;
-+} Si2158_ATV_LIF_FREQ_PROP_struct;
-+
-+/* ATV_LIF_FREQ property, OFFSET field definition (NO TITLE)*/
-+#define Si2158_ATV_LIF_FREQ_PROP_OFFSET_LSB         0
-+#define Si2158_ATV_LIF_FREQ_PROP_OFFSET_MASK        0xffff
-+#define Si2158_ATV_LIF_FREQ_PROP_OFFSET_DEFAULT    5000
-+#define Si2158_ATV_LIF_FREQ_PROP_OFFSET_OFFSET_MIN  0
-+#define Si2158_ATV_LIF_FREQ_PROP_OFFSET_OFFSET_MAX  7000
-+
-+
-+/* Si2158 ATV_LIF_OUT property definition */
-+#define Si2158_ATV_LIF_OUT_PROP 0x060d
-+
-+#define Si2158_ATV_LIF_OUT_PROP_CODE 0x00060d
-+
-+
-+typedef struct { /* Si2158_ATV_LIF_OUT_PROP_struct */
-+	u8   amp;
-+	u8   offset;
-+} Si2158_ATV_LIF_OUT_PROP_struct;
-+
-+/* ATV_LIF_OUT property, AMP field definition (NO TITLE)*/
-+#define Si2158_ATV_LIF_OUT_PROP_AMP_LSB         8
-+#define Si2158_ATV_LIF_OUT_PROP_AMP_MASK        0xff
-+#define Si2158_ATV_LIF_OUT_PROP_AMP_DEFAULT    100
-+#define Si2158_ATV_LIF_OUT_PROP_AMP_AMP_MIN  0
-+#define Si2158_ATV_LIF_OUT_PROP_AMP_AMP_MAX  255
-+
-+/* ATV_LIF_OUT property, OFFSET field definition (NO TITLE)*/
-+#define Si2158_ATV_LIF_OUT_PROP_OFFSET_LSB         0
-+#define Si2158_ATV_LIF_OUT_PROP_OFFSET_MASK        0xff
-+#define Si2158_ATV_LIF_OUT_PROP_OFFSET_DEFAULT    148
-+#define Si2158_ATV_LIF_OUT_PROP_OFFSET_OFFSET_MIN  0
-+#define Si2158_ATV_LIF_OUT_PROP_OFFSET_OFFSET_MAX  255
-+
-+
-+/* Si2158 ATV_PGA_TARGET property definition */
-+#define Si2158_ATV_PGA_TARGET_PROP 0x0617
-+
-+#define Si2158_ATV_PGA_TARGET_PROP_CODE 0x000617
-+
-+typedef struct { /* Si2158_ATV_PGA_TARGET_PROP_struct */
-+	u8 override_enable;
-+	s8 pga_target;
-+} Si2158_ATV_PGA_TARGET_PROP_struct;
-+
-+/* ATV_PGA_TARGET property, OVERRIDE_ENABLE field definition (NO TITLE)*/
-+#define Si2158_ATV_PGA_TARGET_PROP_OVERRIDE_ENABLE_LSB         8
-+#define Si2158_ATV_PGA_TARGET_PROP_OVERRIDE_ENABLE_MASK        0x01
-+#define Si2158_ATV_PGA_TARGET_PROP_OVERRIDE_ENABLE_DEFAULT    0
-+#define Si2158_ATV_PGA_TARGET_PROP_OVERRIDE_ENABLE_DISABLE  0
-+#define Si2158_ATV_PGA_TARGET_PROP_OVERRIDE_ENABLE_ENABLE   1
-+
-+/* ATV_PGA_TARGET property, PGA_TARGET field definition (NO TITLE)*/
-+#define Si2158_ATV_PGA_TARGET_PROP_PGA_TARGET_LSB         0
-+#define Si2158_ATV_PGA_TARGET_PROP_PGA_TARGET_MASK        0xff
-+#define Si2158_ATV_PGA_TARGET_PROP_PGA_TARGET_DEFAULT    0
-+#define Si2158_ATV_PGA_TARGET_PROP_PGA_TARGET_PGA_TARGET_MIN  -13
-+#define Si2158_ATV_PGA_TARGET_PROP_PGA_TARGET_PGA_TARGET_MAX  7
-+
-+
-+/* Si2158 ATV_RF_TOP property definition */
-+#define Si2158_ATV_RF_TOP_PROP 0x0612
-+
-+#define Si2158_ATV_RF_TOP_PROP_CODE 0x000612
-+
-+
-+typedef struct { /* Si2158_ATV_RF_TOP_PROP_struct */
-+	u8   atv_rf_top;
-+} Si2158_ATV_RF_TOP_PROP_struct;
-+
-+/* ATV_RF_TOP property, ATV_RF_TOP field definition (NO TITLE)*/
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_LSB         0
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_MASK        0xff
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_DEFAULT    0
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_AUTO   0
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_P2DB   4
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_P1DB   5
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_0DB    6
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_M1DB   7
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_M2DB   8
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_M3DB   9
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_M4DB   10
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_M5DB   11
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_M6DB   12
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_M7DB   13
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_M8DB   14
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_M9DB   15
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_M10DB  16
-+#define Si2158_ATV_RF_TOP_PROP_ATV_RF_TOP_M11DB  17
-+
-+
-+/* Si2158 ATV_RSQ_RSSI_THRESHOLD property definition */
-+#define Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP 0x0605
-+
-+#define Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_CODE 0x000605
-+
-+
-+typedef struct { /* Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_struct */
-+	s8 hi;
-+	s8 lo;
-+} Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_struct;
-+
-+/* ATV_RSQ_RSSI_THRESHOLD property, HI field definition (NO TITLE)*/
-+#define Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_HI_LSB         8
-+#define Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_HI_MASK        0xff
-+#define Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_HI_DEFAULT    0
-+#define Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_HI_HI_MIN  -128
-+#define Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_HI_HI_MAX  127
-+
-+/* ATV_RSQ_RSSI_THRESHOLD property, LO field definition (NO TITLE)*/
-+#define Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_LO_LSB         0
-+#define Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_LO_MASK        0xff
-+#define Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_LO_DEFAULT    -70
-+#define Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_LO_LO_MIN  -128
-+#define Si2158_ATV_RSQ_RSSI_THRESHOLD_PROP_LO_LO_MAX  127
-+
-+
-+#ifdef __SI2177__
-+/* Si2177 ATV_RSQ_SNR_THRESHOLD property definition */
-+#define Si2177_ATV_RSQ_SNR_THRESHOLD_PROP 0x0606
-+
-+#define Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_CODE 0x000606
-+
-+
-+typedef struct { /* Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_struct */
-+	u8   hi;
-+	u8   lo;
-+} Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_struct;
-+
-+/* ATV_RSQ_SNR_THRESHOLD property, HI field definition (NO TITLE)*/
-+#define Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_HI_LSB         8
-+#define Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_HI_MASK        0xff
-+#define Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_HI_DEFAULT    45
-+#define Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_HI_HI_MIN  0
-+#define Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_HI_HI_MAX  255
-+
-+/* ATV_RSQ_SNR_THRESHOLD property, LO field definition (NO TITLE)*/
-+#define Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_LO_LSB         0
-+#define Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_LO_MASK        0xff
-+#define Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_LO_DEFAULT    25
-+#define Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_LO_LO_MIN  0
-+#define Si2177_ATV_RSQ_SNR_THRESHOLD_PROP_LO_LO_MAX  255
-+
-+
-+/* Si2177 ATV_SIF_OUT property definition */
-+#define Si2177_ATV_SIF_OUT_PROP 0x060a
-+
-+#define Si2177_ATV_SIF_OUT_PROP_CODE 0x00060a
-+
-+
-+typedef struct { /* Si2177_ATV_SIF_OUT_PROP_struct */
-+	u8   amp;
-+	u8   offset;
-+} Si2177_ATV_SIF_OUT_PROP_struct;
-+
-+/* ATV_SIF_OUT property, AMP field definition (NO TITLE)*/
-+#define Si2177_ATV_SIF_OUT_PROP_AMP_LSB         8
-+#define Si2177_ATV_SIF_OUT_PROP_AMP_MASK        0xff
-+#define Si2177_ATV_SIF_OUT_PROP_AMP_DEFAULT    60
-+#define Si2177_ATV_SIF_OUT_PROP_AMP_AMP_MIN  0
-+#define Si2177_ATV_SIF_OUT_PROP_AMP_AMP_MAX  255
-+
-+/* ATV_SIF_OUT property, OFFSET field definition (NO TITLE)*/
-+#define Si2177_ATV_SIF_OUT_PROP_OFFSET_LSB         0
-+#define Si2177_ATV_SIF_OUT_PROP_OFFSET_MASK        0xff
-+#define Si2177_ATV_SIF_OUT_PROP_OFFSET_DEFAULT    135
-+#define Si2177_ATV_SIF_OUT_PROP_OFFSET_OFFSET_MIN  0
-+#define Si2177_ATV_SIF_OUT_PROP_OFFSET_OFFSET_MAX  255
-+
-+
-+/* Si2177 ATV_SOUND_AGC_LIMIT property definition */
-+#define Si2177_ATV_SOUND_AGC_LIMIT_PROP 0x0618
-+
-+#define Si2177_ATV_SOUND_AGC_LIMIT_PROP_CODE 0x000618
-+
-+
-+typedef struct { /* Si2177_ATV_SOUND_AGC_LIMIT_PROP_struct */
-+	s8 max_gain;
-+	s8 min_gain;
-+} Si2177_ATV_SOUND_AGC_LIMIT_PROP_struct;
-+
-+/* ATV_SOUND_AGC_LIMIT property, MAX_GAIN field definition (NO TITLE)*/
-+#define Si2177_ATV_SOUND_AGC_LIMIT_PROP_MAX_GAIN_LSB         0
-+#define Si2177_ATV_SOUND_AGC_LIMIT_PROP_MAX_GAIN_MASK        0xff
-+#define Si2177_ATV_SOUND_AGC_LIMIT_PROP_MAX_GAIN_DEFAULT    84
-+#define Si2177_ATV_SOUND_AGC_LIMIT_PROP_MAX_GAIN_MAX_GAIN_MIN  -84
-+#define Si2177_ATV_SOUND_AGC_LIMIT_PROP_MAX_GAIN_MAX_GAIN_MAX  84
-+
-+/* ATV_SOUND_AGC_LIMIT property, MIN_GAIN field definition (NO TITLE)*/
-+#define Si2177_ATV_SOUND_AGC_LIMIT_PROP_MIN_GAIN_LSB         8
-+#define Si2177_ATV_SOUND_AGC_LIMIT_PROP_MIN_GAIN_MASK        0xff
-+#define Si2177_ATV_SOUND_AGC_LIMIT_PROP_MIN_GAIN_DEFAULT    -84
-+#define Si2177_ATV_SOUND_AGC_LIMIT_PROP_MIN_GAIN_MIN_GAIN_MIN  -84
-+#define Si2177_ATV_SOUND_AGC_LIMIT_PROP_MIN_GAIN_MIN_GAIN_MAX  84
-+
-+
-+/* Si2177 ATV_SOUND_AGC_SPEED property definition */
-+#define Si2177_ATV_SOUND_AGC_SPEED_PROP 0x0619
-+
-+#define Si2177_ATV_SOUND_AGC_SPEED_PROP_CODE 0x000619
-+
-+
-+typedef struct { /* Si2177_ATV_SOUND_AGC_SPEED_PROP_struct */
-+	u8   other_systems;
-+	u8   system_l;
-+} Si2177_ATV_SOUND_AGC_SPEED_PROP_struct;
-+
-+/* ATV_SOUND_AGC_SPEED property, OTHER_SYSTEMS field definition (NO TITLE)*/
-+#define Si2177_ATV_SOUND_AGC_SPEED_PROP_OTHER_SYSTEMS_LSB         8
-+#define Si2177_ATV_SOUND_AGC_SPEED_PROP_OTHER_SYSTEMS_MASK        0xff
-+#define Si2177_ATV_SOUND_AGC_SPEED_PROP_OTHER_SYSTEMS_DEFAULT    4
-+#define Si2177_ATV_SOUND_AGC_SPEED_PROP_OTHER_SYSTEMS_OTHER_SYSTEMS_MIN  0
-+#define Si2177_ATV_SOUND_AGC_SPEED_PROP_OTHER_SYSTEMS_OTHER_SYSTEMS_MAX  15
-+
-+/* ATV_SOUND_AGC_SPEED property, SYSTEM_L field definition (NO TITLE)*/
-+#define Si2177_ATV_SOUND_AGC_SPEED_PROP_SYSTEM_L_LSB         0
-+#define Si2177_ATV_SOUND_AGC_SPEED_PROP_SYSTEM_L_MASK        0xff
-+#define Si2177_ATV_SOUND_AGC_SPEED_PROP_SYSTEM_L_DEFAULT    5
-+#define Si2177_ATV_SOUND_AGC_SPEED_PROP_SYSTEM_L_SYSTEM_L_MIN  0
-+#define Si2177_ATV_SOUND_AGC_SPEED_PROP_SYSTEM_L_SYSTEM_L_MAX  15
-+
-+
-+/* Si2177 ATV_VIDEO_EQUALIZER property definition */
-+#define Si2177_ATV_VIDEO_EQUALIZER_PROP 0x0608
-+
-+#define Si2177_ATV_VIDEO_EQUALIZER_PROP_CODE 0x000608
-+
-+
-+typedef struct { /* Si2177_ATV_VIDEO_EQUALIZER_PROP_struct */
-+	s8 slope;
-+} Si2177_ATV_VIDEO_EQUALIZER_PROP_struct;
-+
-+/* ATV_VIDEO_EQUALIZER property, SLOPE field definition (NO TITLE)*/
-+#define Si2177_ATV_VIDEO_EQUALIZER_PROP_SLOPE_LSB         0
-+#define Si2177_ATV_VIDEO_EQUALIZER_PROP_SLOPE_MASK        0xff
-+#define Si2177_ATV_VIDEO_EQUALIZER_PROP_SLOPE_DEFAULT    0
-+#define Si2177_ATV_VIDEO_EQUALIZER_PROP_SLOPE_SLOPE_MIN  -8
-+#define Si2177_ATV_VIDEO_EQUALIZER_PROP_SLOPE_SLOPE_MAX  7
-+
-+#endif /* __SI2177__ */
-+
-+/* Si2158 ATV_VIDEO_MODE property definition */
-+#define Si2158_ATV_VIDEO_MODE_PROP 0x0604
-+
-+#define Si2158_ATV_VIDEO_MODE_PROP_CODE 0x000604
-+
-+
-+typedef struct { /* Si2158_ATV_VIDEO_MODE_PROP_struct */
-+	u8   color;
-+	u8   invert_spectrum;
-+	u8   video_sys;
-+} Si2158_ATV_VIDEO_MODE_PROP_struct;
-+
-+/* ATV_VIDEO_MODE property, COLOR field definition (NO TITLE)*/
-+#define Si2158_ATV_VIDEO_MODE_PROP_COLOR_LSB         4
-+#define Si2158_ATV_VIDEO_MODE_PROP_COLOR_MASK        0x01
-+#define Si2158_ATV_VIDEO_MODE_PROP_COLOR_DEFAULT    0
-+#define Si2158_ATV_VIDEO_MODE_PROP_COLOR_PAL_NTSC  0
-+#define Si2158_ATV_VIDEO_MODE_PROP_COLOR_SECAM     1
-+
-+/* ATV_VIDEO_MODE property, INVERT_SPECTRUM field definition (NO TITLE)*/
-+#define Si2158_ATV_VIDEO_MODE_PROP_INVERT_SPECTRUM_LSB      9
-+#define Si2158_ATV_VIDEO_MODE_PROP_INVERT_SPECTRUM_MASK     0x01
-+#define Si2158_ATV_VIDEO_MODE_PROP_INVERT_SPECTRUM_DEFAULT  1
-+#define Si2158_ATV_VIDEO_MODE_PROP_INVERT_SPECTRUM_NORMAL   0
-+#define Si2158_ATV_VIDEO_MODE_PROP_INVERT_SPECTRUM_INVERTED 1
-+
-+#ifdef __SI2177__ /* different definition */
-+/* ATV_VIDEO_MODE property, INVERT_SIGNAL field definition (NO TITLE)*/
-+#define Si2177_ATV_VIDEO_MODE_PROP_INVERT_SIGNAL_LSB        10
-+#define Si2177_ATV_VIDEO_MODE_PROP_INVERT_SIGNAL_MASK       0x01
-+#define Si2177_ATV_VIDEO_MODE_PROP_INVERT_SIGNAL_DEFAULT    0
-+#define Si2177_ATV_VIDEO_MODE_PROP_INVERT_SIGNAL_NORMAL     0
-+#define Si2177_ATV_VIDEO_MODE_PROP_INVERT_SIGNAL_INVERTED   1
-+#endif /* __SI2177__ */
-+
-+/* ATV_VIDEO_MODE property, VIDEO_SYS field definition (NO TITLE)*/
-+#define Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_LSB         0
-+#define Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_MASK        0x07
-+#define Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_DEFAULT    0
-+#define Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_B   0
-+#define Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_GH  1
-+#define Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_M   2
-+#define Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_N   3
-+#define Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_I   4
-+#define Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_DK  5
-+#define Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_L   6
-+#define Si2158_ATV_VIDEO_MODE_PROP_VIDEO_SYS_LP  7
-+
-+
-+/* Si2158 ATV_VSNR_CAP property definition */
-+#define Si2158_ATV_VSNR_CAP_PROP 0x0616
-+
-+#define Si2158_ATV_VSNR_CAP_PROP_CODE 0x000616
-+
-+
-+typedef struct { /* Si2158_ATV_VSNR_CAP_PROP_struct */
-+	u8   atv_vsnr_cap;
-+} Si2158_ATV_VSNR_CAP_PROP_struct;
-+
-+/* ATV_VSNR_CAP property, ATV_VSNR_CAP field definition (NO TITLE)*/
-+#define Si2158_ATV_VSNR_CAP_PROP_ATV_VSNR_CAP_LSB         0
-+#define Si2158_ATV_VSNR_CAP_PROP_ATV_VSNR_CAP_MASK        0xff
-+#define Si2158_ATV_VSNR_CAP_PROP_ATV_VSNR_CAP_DEFAULT    0
-+#define Si2158_ATV_VSNR_CAP_PROP_ATV_VSNR_CAP_ATV_VSNR_CAP_MIN  0
-+#define Si2158_ATV_VSNR_CAP_PROP_ATV_VSNR_CAP_ATV_VSNR_CAP_MAX  127
-+
-+
-+/* Si2158 CRYSTAL_TRIM property definition */
-+#define Si2158_CRYSTAL_TRIM_PROP 0x0402
-+
-+#define Si2158_CRYSTAL_TRIM_PROP_CODE 0x000402
-+
-+
-+typedef struct { /* Si2158_CRYSTAL_TRIM_PROP_struct */
-+	u8   xo_cap;
-+} Si2158_CRYSTAL_TRIM_PROP_struct;
-+
-+/* CRYSTAL_TRIM property, XO_CAP field definition (NO TITLE)*/
-+#define Si2158_CRYSTAL_TRIM_PROP_XO_CAP_LSB         0
-+#define Si2158_CRYSTAL_TRIM_PROP_XO_CAP_MASK        0x0f
-+#define Si2158_CRYSTAL_TRIM_PROP_XO_CAP_DEFAULT    8
-+#define Si2158_CRYSTAL_TRIM_PROP_XO_CAP_4P7PF   0
-+#define Si2158_CRYSTAL_TRIM_PROP_XO_CAP_5P2PF   2
-+#define Si2158_CRYSTAL_TRIM_PROP_XO_CAP_5P7PF   4
-+#define Si2158_CRYSTAL_TRIM_PROP_XO_CAP_6P2PF   6
-+#define Si2158_CRYSTAL_TRIM_PROP_XO_CAP_6P7PF   8
-+#define Si2158_CRYSTAL_TRIM_PROP_XO_CAP_7P2PF  10
-+#define Si2158_CRYSTAL_TRIM_PROP_XO_CAP_7P7PF  12
-+#define Si2158_CRYSTAL_TRIM_PROP_XO_CAP_8P2PF  14
-+
-+
-+/* Si2158 DTV_AGC_FREEZE_INPUT property definition */
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP 0x0711
-+
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_CODE 0x000711
-+
-+
-+typedef struct { /* Si2158_DTV_AGC_FREEZE_INPUT_PROP_struct */
-+	u8   level;
-+	u8   pin;
-+} Si2158_DTV_AGC_FREEZE_INPUT_PROP_struct;
-+
-+/* DTV_AGC_FREEZE_INPUT property, LEVEL field definition (NO TITLE)*/
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_LEVEL_LSB         0
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_LEVEL_MASK        0x01
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_LEVEL_DEFAULT    0
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_LEVEL_LOW   0
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_LEVEL_HIGH  1
-+
-+/* DTV_AGC_FREEZE_INPUT property, PIN field definition (NO TITLE)*/
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_LSB         1
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_MASK        0x07
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_DEFAULT    0
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_NONE      0
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_GPIO1     1
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_GPIO2     2
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_RESERVED  3
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_AGC1      4
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_AGC2      5
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_LIF1A     6
-+#define Si2158_DTV_AGC_FREEZE_INPUT_PROP_PIN_LIF1B     7
-+
-+
-+/* Si2158 DTV_AGC_SPEED property definition */
-+#define Si2158_DTV_AGC_SPEED_PROP 0x0708
-+
-+#define Si2158_DTV_AGC_SPEED_PROP_CODE 0x000708
-+
-+
-+typedef struct { /* Si2158_DTV_AGC_SPEED_PROP_struct */
-+	u8   agc_decim;
-+	u8   if_agc_speed;
-+} Si2158_DTV_AGC_SPEED_PROP_struct;
-+
-+/* DTV_AGC_SPEED property, AGC_DECIM field definition (NO TITLE)*/
-+#define Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_LSB         8
-+#define Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_MASK        0x03
-+#define Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_DEFAULT    0
-+#define Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_OFF  0
-+#define Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_2    1
-+#define Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_4    2
-+#define Si2158_DTV_AGC_SPEED_PROP_AGC_DECIM_8    3
-+
-+/* DTV_AGC_SPEED property, IF_AGC_SPEED field definition (NO TITLE)*/
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_LSB         0
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_MASK        0xff
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_DEFAULT    0
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_AUTO  0
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_39    39
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_54    54
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_63    63
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_89    89
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_105   105
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_121   121
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_137   137
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_158   158
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_172   172
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_185   185
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_196   196
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_206   206
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_216   216
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_219   219
-+#define Si2158_DTV_AGC_SPEED_PROP_IF_AGC_SPEED_222   222
-+
-+
-+/* Si2158 DTV_CONFIG_IF_PORT property definition */
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP 0x0702
-+
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP_CODE 0x000702
-+
-+
-+typedef struct { /* Si2158_DTV_CONFIG_IF_PORT_PROP_struct */
-+	u8   dtv_agc_source;
-+	u8   dtv_out_type;
-+} Si2158_DTV_CONFIG_IF_PORT_PROP_struct;
-+
-+/* DTV_CONFIG_IF_PORT property, DTV_AGC_SOURCE field definition (NO TITLE)*/
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_AGC_SOURCE_LSB         8
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_AGC_SOURCE_MASK        0x07
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_AGC_SOURCE_DEFAULT    0
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_AGC_SOURCE_INTERNAL   0
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_AGC_SOURCE_AGC1_3DB   1
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_AGC_SOURCE_AGC2_3DB   2
-+
-+/* DTV_CONFIG_IF_PORT property, DTV_OUT_TYPE field definition (NO TITLE)*/
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_OUT_TYPE_LSB         0
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_OUT_TYPE_MASK        0x0f
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_OUT_TYPE_DEFAULT    1
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_OUT_TYPE_LIF_IF1      0
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_OUT_TYPE_LIF_IF2      1
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_OUT_TYPE_LIF_SE_IF1A  4
-+#define Si2158_DTV_CONFIG_IF_PORT_PROP_DTV_OUT_TYPE_LIF_SE_IF2A  5
-+
-+
-+/* Si2158 DTV_EXT_AGC property definition */
-+#define Si2158_DTV_EXT_AGC_PROP 0x0705
-+
-+#define Si2158_DTV_EXT_AGC_PROP_CODE 0x000705
-+
-+
-+typedef struct { /* Si2158_DTV_EXT_AGC_PROP_struct */
-+	u8   max_10mv;
-+	u8   min_10mv;
-+} Si2158_DTV_EXT_AGC_PROP_struct;
-+
-+/* DTV_EXT_AGC property, MAX_10MV field definition (NO TITLE)*/
-+#define Si2158_DTV_EXT_AGC_PROP_MAX_10MV_LSB         8
-+#define Si2158_DTV_EXT_AGC_PROP_MAX_10MV_MASK        0xff
-+#define Si2158_DTV_EXT_AGC_PROP_MAX_10MV_DEFAULT    200
-+#define Si2158_DTV_EXT_AGC_PROP_MAX_10MV_MAX_10MV_MIN  0
-+#define Si2158_DTV_EXT_AGC_PROP_MAX_10MV_MAX_10MV_MAX  255
-+
-+/* DTV_EXT_AGC property, MIN_10MV field definition (NO TITLE)*/
-+#define Si2158_DTV_EXT_AGC_PROP_MIN_10MV_LSB         0
-+#define Si2158_DTV_EXT_AGC_PROP_MIN_10MV_MASK        0xff
-+#define Si2158_DTV_EXT_AGC_PROP_MIN_10MV_DEFAULT    50
-+#define Si2158_DTV_EXT_AGC_PROP_MIN_10MV_MIN_10MV_MIN  0
-+#define Si2158_DTV_EXT_AGC_PROP_MIN_10MV_MIN_10MV_MAX  255
-+
-+
-+/* Si2158 DTV_FILTER_SELECT property definition */
-+#define Si2158_DTV_FILTER_SELECT_PROP 0x070c
-+
-+#define Si2158_DTV_FILTER_SELECT_PROP_CODE 0x00070c
-+
-+
-+typedef struct { /* Si2158_DTV_FILTER_SELECT_PROP_struct */
-+	u8   filter;
-+} Si2158_DTV_FILTER_SELECT_PROP_struct;
-+
-+/* DTV_FILTER_SELECT property, FILTER field definition (NO TITLE)*/
-+#define Si2158_DTV_FILTER_SELECT_PROP_FILTER_LSB         0
-+#define Si2158_DTV_FILTER_SELECT_PROP_FILTER_MASK        0x03
-+#define Si2158_DTV_FILTER_SELECT_PROP_FILTER_DEFAULT    1
-+#define Si2158_DTV_FILTER_SELECT_PROP_FILTER_LEGACY   0
-+#define Si2158_DTV_FILTER_SELECT_PROP_FILTER_CUSTOM1  1
-+#define Si2158_DTV_FILTER_SELECT_PROP_FILTER_CUSTOM2  2
-+
-+
-+/* Si2158 DTV_IEN property definition */
-+#define Si2158_DTV_IEN_PROP 0x0701
-+
-+#define Si2158_DTV_IEN_PROP_CODE 0x000701
-+
-+
-+typedef struct { /* Si2158_DTV_IEN_PROP_struct */
-+	u8   chlien;
-+} Si2158_DTV_IEN_PROP_struct;
-+
-+/* DTV_IEN property, CHLIEN field definition (NO TITLE)*/
-+#define Si2158_DTV_IEN_PROP_CHLIEN_LSB         0
-+#define Si2158_DTV_IEN_PROP_CHLIEN_MASK        0x01
-+#define Si2158_DTV_IEN_PROP_CHLIEN_DEFAULT    1
-+#define Si2158_DTV_IEN_PROP_CHLIEN_DISABLE  0
-+#define Si2158_DTV_IEN_PROP_CHLIEN_ENABLE   1
-+
-+
-+/* Si2158 DTV_INITIAL_AGC_SPEED property definition */
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP 0x070d
-+
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_CODE 0x00070d
-+
-+
-+typedef struct { /* Si2158_DTV_INITIAL_AGC_SPEED_PROP_struct */
-+	u8   agc_decim;
-+	u8   if_agc_speed;
-+} Si2158_DTV_INITIAL_AGC_SPEED_PROP_struct;
-+
-+/* DTV_INITIAL_AGC_SPEED property, AGC_DECIM field definition (NO TITLE)*/
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_AGC_DECIM_LSB         8
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_AGC_DECIM_MASK        0x03
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_AGC_DECIM_DEFAULT    0
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_AGC_DECIM_OFF  0
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_AGC_DECIM_2    1
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_AGC_DECIM_4    2
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_AGC_DECIM_8    3
-+
-+/* DTV_INITIAL_AGC_SPEED property, IF_AGC_SPEED field definition (NO TITLE)*/
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_LSB         0
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_MASK        0xff
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_DEFAULT    0
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_AUTO  0
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_39    39
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_54    54
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_63    63
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_89    89
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_105   105
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_121   121
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_137   137
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_158   158
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_172   172
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_185   185
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_196   196
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_206   206
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_216   216
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_219   219
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PROP_IF_AGC_SPEED_222   222
-+
-+
-+/* Si2158 DTV_INITIAL_AGC_SPEED_PERIOD property definition */
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP 0x070e
-+
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_CODE 0x00070e
-+
-+
-+typedef struct { /* Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_struct */
-+	u16 period;
-+} Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_struct;
-+
-+/* DTV_INITIAL_AGC_SPEED_PERIOD property, PERIOD field definition (NO TITLE)*/
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_PERIOD_LSB         0
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_PERIOD_MASK        0xffff
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_PERIOD_DEFAULT    0
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_PERIOD_PERIOD_MIN  0
-+#define Si2158_DTV_INITIAL_AGC_SPEED_PERIOD_PROP_PERIOD_PERIOD_MAX  65535
-+
-+
-+/* Si2158 DTV_INTERNAL_ZIF property definition */
-+#define Si2158_DTV_INTERNAL_ZIF_PROP 0x0710
-+
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_CODE 0x000710
-+
-+
-+typedef struct { /* Si2158_DTV_INTERNAL_ZIF_PROP_struct */
-+	u8   atsc;
-+	u8   dtmb;
-+	u8   dvbc;
-+	u8   dvbt;
-+	u8   isdbc;
-+	u8   isdbt;
-+	u8   qam_us;
-+} Si2158_DTV_INTERNAL_ZIF_PROP_struct;
-+
-+/* DTV_INTERNAL_ZIF property, ATSC field definition (NO TITLE)*/
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ATSC_LSB         0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ATSC_MASK        0x01
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ATSC_DEFAULT    0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ATSC_LIF  0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ATSC_ZIF  1
-+
-+/* DTV_INTERNAL_ZIF property, DTMB field definition (NO TITLE)*/
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DTMB_LSB         6
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DTMB_MASK        0x01
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DTMB_DEFAULT    0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DTMB_LIF  0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DTMB_ZIF  1
-+
-+/* DTV_INTERNAL_ZIF property, DVBC field definition (NO TITLE)*/
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DVBC_LSB         3
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DVBC_MASK        0x01
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DVBC_DEFAULT    0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DVBC_LIF  0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DVBC_ZIF  1
-+
-+/* DTV_INTERNAL_ZIF property, DVBT field definition (NO TITLE)*/
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DVBT_LSB         2
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DVBT_MASK        0x01
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DVBT_DEFAULT    0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DVBT_LIF  0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_DVBT_ZIF  1
-+
-+/* DTV_INTERNAL_ZIF property, ISDBC field definition (NO TITLE)*/
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ISDBC_LSB         5
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ISDBC_MASK        0x01
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ISDBC_DEFAULT    0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ISDBC_LIF  0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ISDBC_ZIF  1
-+
-+/* DTV_INTERNAL_ZIF property, ISDBT field definition (NO TITLE)*/
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ISDBT_LSB         4
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ISDBT_MASK        0x01
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ISDBT_DEFAULT    0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ISDBT_LIF  0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_ISDBT_ZIF  1
-+
-+/* DTV_INTERNAL_ZIF property, QAM_US field definition (NO TITLE)*/
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_QAM_US_LSB         1
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_QAM_US_MASK        0x01
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_QAM_US_DEFAULT    0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_QAM_US_LIF  0
-+#define Si2158_DTV_INTERNAL_ZIF_PROP_QAM_US_ZIF  1
-+
-+
-+/* Si2158 DTV_INT_SENSE property definition */
-+#define Si2158_DTV_INT_SENSE_PROP 0x070a
-+
-+#define Si2158_DTV_INT_SENSE_PROP_CODE 0x00070a
-+
-+
-+typedef struct { /* Si2158_DTV_INT_SENSE_PROP_struct */
-+	u8   chlnegen;
-+	u8   chlposen;
-+} Si2158_DTV_INT_SENSE_PROP_struct;
-+
-+/* DTV_INT_SENSE property, CHLNEGEN field definition (NO TITLE)*/
-+#define Si2158_DTV_INT_SENSE_PROP_CHLNEGEN_LSB         0
-+#define Si2158_DTV_INT_SENSE_PROP_CHLNEGEN_MASK        0x01
-+#define Si2158_DTV_INT_SENSE_PROP_CHLNEGEN_DEFAULT    0
-+#define Si2158_DTV_INT_SENSE_PROP_CHLNEGEN_DISABLE  0
-+#define Si2158_DTV_INT_SENSE_PROP_CHLNEGEN_ENABLE   1
-+
-+/* DTV_INT_SENSE property, CHLPOSEN field definition (NO TITLE)*/
-+#define Si2158_DTV_INT_SENSE_PROP_CHLPOSEN_LSB         8
-+#define Si2158_DTV_INT_SENSE_PROP_CHLPOSEN_MASK        0x01
-+#define Si2158_DTV_INT_SENSE_PROP_CHLPOSEN_DEFAULT    1
-+#define Si2158_DTV_INT_SENSE_PROP_CHLPOSEN_DISABLE  0
-+#define Si2158_DTV_INT_SENSE_PROP_CHLPOSEN_ENABLE   1
-+
-+
-+/* Si2158 DTV_LIF_FREQ property definition */
-+#define Si2158_DTV_LIF_FREQ_PROP 0x0706
-+
-+#define Si2158_DTV_LIF_FREQ_PROP_CODE 0x000706
-+
-+
-+typedef struct { /* Si2158_DTV_LIF_FREQ_PROP_struct */
-+	u16 offset;
-+} Si2158_DTV_LIF_FREQ_PROP_struct;
-+
-+/* DTV_LIF_FREQ property, OFFSET field definition (NO TITLE)*/
-+#define Si2158_DTV_LIF_FREQ_PROP_OFFSET_LSB         0
-+#define Si2158_DTV_LIF_FREQ_PROP_OFFSET_MASK        0xffff
-+#define Si2158_DTV_LIF_FREQ_PROP_OFFSET_DEFAULT    5000
-+#define Si2158_DTV_LIF_FREQ_PROP_OFFSET_OFFSET_MIN  0
-+#define Si2158_DTV_LIF_FREQ_PROP_OFFSET_OFFSET_MAX  7000
-+
-+
-+/* Si2158 DTV_LIF_OUT property definition */
-+#define Si2158_DTV_LIF_OUT_PROP 0x0707
-+
-+#define Si2158_DTV_LIF_OUT_PROP_CODE 0x000707
-+
-+
-+typedef struct { /* Si2158_DTV_LIF_OUT_PROP_struct */
-+	u8   amp;
-+	u8   offset;
-+} Si2158_DTV_LIF_OUT_PROP_struct;
-+
-+/* DTV_LIF_OUT property, AMP field definition (NO TITLE)*/
-+#define Si2158_DTV_LIF_OUT_PROP_AMP_LSB         8
-+#define Si2158_DTV_LIF_OUT_PROP_AMP_MASK        0xff
-+#define Si2158_DTV_LIF_OUT_PROP_AMP_DEFAULT    27
-+#define Si2158_DTV_LIF_OUT_PROP_AMP_AMP_MIN  0
-+#define Si2158_DTV_LIF_OUT_PROP_AMP_AMP_MAX  255
-+
-+/* DTV_LIF_OUT property, OFFSET field definition (NO TITLE)*/
-+#define Si2158_DTV_LIF_OUT_PROP_OFFSET_LSB         0
-+#define Si2158_DTV_LIF_OUT_PROP_OFFSET_MASK        0xff
-+#define Si2158_DTV_LIF_OUT_PROP_OFFSET_DEFAULT    148
-+#define Si2158_DTV_LIF_OUT_PROP_OFFSET_OFFSET_MIN  0
-+#define Si2158_DTV_LIF_OUT_PROP_OFFSET_OFFSET_MAX  255
-+
-+
-+/* Si2158 DTV_MODE property definition */
-+#define Si2158_DTV_MODE_PROP 0x0703
-+
-+#define Si2158_DTV_MODE_PROP_CODE 0x000703
-+
-+
-+typedef struct { /* Si2158_DTV_MODE_PROP_struct */
-+	u8   bw;
-+	u8   invert_spectrum;
-+	u8   modulation;
-+} Si2158_DTV_MODE_PROP_struct;
-+
-+/* DTV_MODE property, BW field definition (NO TITLE)*/
-+#define Si2158_DTV_MODE_PROP_BW_LSB         0
-+#define Si2158_DTV_MODE_PROP_BW_MASK        0x0f
-+#define Si2158_DTV_MODE_PROP_BW_DEFAULT    8
-+#define Si2158_DTV_MODE_PROP_BW_BW_6MHZ  6
-+#define Si2158_DTV_MODE_PROP_BW_BW_7MHZ  7
-+#define Si2158_DTV_MODE_PROP_BW_BW_8MHZ  8
-+#ifdef __SI2157__
-+#define Si2157_DTV_MODE_PROP_BW_BW_1P7MHZ  9
-+#define Si2157_DTV_MODE_PROP_BW_BW_6P1MHZ  10
-+#endif /* __SI2157__ */
-+
-+/* DTV_MODE property, INVERT_SPECTRUM field definition (NO TITLE)*/
-+#define Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_LSB         8
-+#define Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_MASK        0x01
-+#define Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_DEFAULT    0
-+#define Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_NORMAL    0
-+#define Si2158_DTV_MODE_PROP_INVERT_SPECTRUM_INVERTED  1
-+
-+/* DTV_MODE property, MODULATION field definition (NO TITLE)*/
-+#define Si2158_DTV_MODE_PROP_MODULATION_LSB         4
-+#define Si2158_DTV_MODE_PROP_MODULATION_MASK        0x0f
-+#define Si2158_DTV_MODE_PROP_MODULATION_DEFAULT    2
-+#define Si2158_DTV_MODE_PROP_MODULATION_ATSC    0
-+#define Si2158_DTV_MODE_PROP_MODULATION_QAM_US  1
-+#define Si2158_DTV_MODE_PROP_MODULATION_DVBT    2
-+#define Si2158_DTV_MODE_PROP_MODULATION_DVBC    3
-+#define Si2158_DTV_MODE_PROP_MODULATION_ISDBT   4
-+#define Si2158_DTV_MODE_PROP_MODULATION_ISDBC   5
-+#define Si2158_DTV_MODE_PROP_MODULATION_DTMB    6
-+
-+
-+/* Si2158 DTV_PGA_LIMITS property definition */
-+#define Si2158_DTV_PGA_LIMITS_PROP 0x0713
-+
-+#define Si2158_DTV_PGA_LIMITS_PROP_CODE 0x000713
-+
-+
-+typedef struct { /* Si2158_DTV_PGA_LIMITS_PROP_struct */
-+	s8 max;
-+	s8 min;
-+} Si2158_DTV_PGA_LIMITS_PROP_struct;
-+
-+/* DTV_PGA_LIMITS property, MAX field definition (NO TITLE)*/
-+#define Si2158_DTV_PGA_LIMITS_PROP_MAX_LSB         8
-+#define Si2158_DTV_PGA_LIMITS_PROP_MAX_MASK        0xff
-+#define Si2158_DTV_PGA_LIMITS_PROP_MAX_DEFAULT    -1
-+#define Si2158_DTV_PGA_LIMITS_PROP_MAX_MAX_MIN  -1
-+#define Si2158_DTV_PGA_LIMITS_PROP_MAX_MAX_MAX  56
-+
-+/* DTV_PGA_LIMITS property, MIN field definition (NO TITLE)*/
-+#define Si2158_DTV_PGA_LIMITS_PROP_MIN_LSB         0
-+#define Si2158_DTV_PGA_LIMITS_PROP_MIN_MASK        0xff
-+#define Si2158_DTV_PGA_LIMITS_PROP_MIN_DEFAULT    -1
-+#define Si2158_DTV_PGA_LIMITS_PROP_MIN_MIN_MIN  -1
-+#define Si2158_DTV_PGA_LIMITS_PROP_MIN_MIN_MAX  56
-+
-+
-+/* Si2158 DTV_PGA_TARGET property definition */
-+#define Si2158_DTV_PGA_TARGET_PROP 0x070f
-+
-+#define Si2158_DTV_PGA_TARGET_PROP_CODE 0x00070f
-+
-+
-+typedef struct { /* Si2158_DTV_PGA_TARGET_PROP_struct */
-+	u8   override_enable;
-+	s8   pga_target;
-+} Si2158_DTV_PGA_TARGET_PROP_struct;
-+
-+/* DTV_PGA_TARGET property, OVERRIDE_ENABLE field definition (NO TITLE)*/
-+#define Si2158_DTV_PGA_TARGET_PROP_OVERRIDE_ENABLE_LSB         8
-+#define Si2158_DTV_PGA_TARGET_PROP_OVERRIDE_ENABLE_MASK        0x01
-+#define Si2158_DTV_PGA_TARGET_PROP_OVERRIDE_ENABLE_DEFAULT    0
-+#define Si2158_DTV_PGA_TARGET_PROP_OVERRIDE_ENABLE_DISABLE  0
-+#define Si2158_DTV_PGA_TARGET_PROP_OVERRIDE_ENABLE_ENABLE   1
-+
-+/* DTV_PGA_TARGET property, PGA_TARGET field definition (NO TITLE)*/
-+#define Si2158_DTV_PGA_TARGET_PROP_PGA_TARGET_LSB         0
-+#define Si2158_DTV_PGA_TARGET_PROP_PGA_TARGET_MASK        0xff
-+#define Si2158_DTV_PGA_TARGET_PROP_PGA_TARGET_DEFAULT    0
-+#define Si2158_DTV_PGA_TARGET_PROP_PGA_TARGET_PGA_TARGET_MIN  -13
-+#define Si2158_DTV_PGA_TARGET_PROP_PGA_TARGET_PGA_TARGET_MAX  7
-+
-+
-+/* Si2158 DTV_RF_TOP property definition */
-+#define Si2158_DTV_RF_TOP_PROP 0x0709
-+
-+#define Si2158_DTV_RF_TOP_PROP_CODE 0x000709
-+
-+
-+typedef struct { /* Si2158_DTV_RF_TOP_PROP_struct */
-+	u8   dtv_rf_top;
-+} Si2158_DTV_RF_TOP_PROP_struct;
-+
-+/* DTV_RF_TOP property, DTV_RF_TOP field definition (NO TITLE)*/
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_LSB         0
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_MASK        0xff
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_DEFAULT    0
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_AUTO     0
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_P6DB     9
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_P5P5DB   10
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_P5DB     11
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_P4P5DB   12
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_P4DB     13
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_P3P5DB   14
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_P3DB     15
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_P2P5DB   16
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_P2DB     17
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_P1P5DB   18
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_P1DB     19
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_P0P5DB   20
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_0DB      21
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M0P5DB   22
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M1DB     23
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M1P5DB   24
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M2DB     25
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M2P5DB   26
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M3DB     27
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M3P5DB   28
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M4DB     29
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M4P5DB   30
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M5DB     31
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M5P5DB   32
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M6DB     33
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M6P5DB   34
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M7DB     35
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M7P5DB   36
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M8DB     37
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M8P5DB   38
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M9DB     39
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M9P5DB   40
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M10DB    41
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M10P5DB  42
-+#define Si2158_DTV_RF_TOP_PROP_DTV_RF_TOP_M11DB    43
-+
-+
-+/* Si2158 DTV_RSQ_RSSI_THRESHOLD property definition */
-+#define Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP 0x0704
-+
-+#define Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_CODE 0x000704
-+
-+
-+typedef struct { /* Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_struct */
-+	s8   hi;
-+	s8   lo;
-+} Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_struct;
-+
-+/* DTV_RSQ_RSSI_THRESHOLD property, HI field definition (NO TITLE)*/
-+#define Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_HI_LSB         8
-+#define Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_HI_MASK        0xff
-+#define Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_HI_DEFAULT    0
-+#define Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_HI_HI_MIN  -128
-+#define Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_HI_HI_MAX  127
-+
-+/* DTV_RSQ_RSSI_THRESHOLD property, LO field definition (NO TITLE)*/
-+#define Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_LO_LSB         0
-+#define Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_LO_MASK        0xff
-+#define Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_LO_DEFAULT    -80
-+#define Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_LO_LO_MIN  -128
-+#define Si2158_DTV_RSQ_RSSI_THRESHOLD_PROP_LO_LO_MAX  127
-+
-+
-+/* Si2158 DTV_ZIF_DC_CANCELLER_BW property definition */
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP 0x0712
-+
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_CODE 0x000712
-+
-+
-+typedef struct { /* Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_struct */
-+	u8   bandwidth;
-+} Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_struct;
-+
-+/* DTV_ZIF_DC_CANCELLER_BW property, BANDWIDTH field definition (NO TITLE)*/
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_LSB         0
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_MASK        0xff
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_DEFAULT    16
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_4_HZ       0
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_8_HZ       1
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_15_HZ      2
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_30_HZ      3
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_61_HZ      4
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_121_HZ     5
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_243_HZ     6
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_486_HZ     7
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_972_HZ     8
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_1943_HZ    9
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_3888_HZ    10
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_7779_HZ    11
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_15573_HZ   12
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_31207_HZ   13
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_62658_HZ   14
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_126303_HZ  15
-+#define Si2158_DTV_ZIF_DC_CANCELLER_BW_PROP_BANDWIDTH_DEFAULT    16
-+
-+
-+/* Si2158 MASTER_IEN property definition */
-+#define Si2158_MASTER_IEN_PROP 0x0401
-+
-+#define Si2158_MASTER_IEN_PROP_CODE 0x000401
-+
-+
-+typedef struct { /* Si2158_MASTER_IEN_PROP_struct */
-+	u8   atvien;
-+	u8   ctsien;
-+	u8   dtvien;
-+	u8   errien;
-+	u8   tunien;
-+} Si2158_MASTER_IEN_PROP_struct;
-+
-+/* MASTER_IEN property, ATVIEN field definition (NO TITLE)*/
-+#define Si2158_MASTER_IEN_PROP_ATVIEN_LSB         1
-+#define Si2158_MASTER_IEN_PROP_ATVIEN_MASK        0x01
-+#define Si2158_MASTER_IEN_PROP_ATVIEN_DEFAULT    0
-+#define Si2158_MASTER_IEN_PROP_ATVIEN_OFF  0
-+#define Si2158_MASTER_IEN_PROP_ATVIEN_ON   1
-+
-+/* MASTER_IEN property, CTSIEN field definition (NO TITLE)*/
-+#define Si2158_MASTER_IEN_PROP_CTSIEN_LSB         7
-+#define Si2158_MASTER_IEN_PROP_CTSIEN_MASK        0x01
-+#define Si2158_MASTER_IEN_PROP_CTSIEN_DEFAULT    0
-+#define Si2158_MASTER_IEN_PROP_CTSIEN_OFF  0
-+#define Si2158_MASTER_IEN_PROP_CTSIEN_ON   1
-+
-+/* MASTER_IEN property, DTVIEN field definition (NO TITLE)*/
-+#define Si2158_MASTER_IEN_PROP_DTVIEN_LSB         2
-+#define Si2158_MASTER_IEN_PROP_DTVIEN_MASK        0x01
-+#define Si2158_MASTER_IEN_PROP_DTVIEN_DEFAULT    0
-+#define Si2158_MASTER_IEN_PROP_DTVIEN_OFF  0
-+#define Si2158_MASTER_IEN_PROP_DTVIEN_ON   1
-+
-+/* MASTER_IEN property, ERRIEN field definition (NO TITLE)*/
-+#define Si2158_MASTER_IEN_PROP_ERRIEN_LSB         6
-+#define Si2158_MASTER_IEN_PROP_ERRIEN_MASK        0x01
-+#define Si2158_MASTER_IEN_PROP_ERRIEN_DEFAULT    0
-+#define Si2158_MASTER_IEN_PROP_ERRIEN_OFF  0
-+#define Si2158_MASTER_IEN_PROP_ERRIEN_ON   1
-+
-+/* MASTER_IEN property, TUNIEN field definition (NO TITLE)*/
-+#define Si2158_MASTER_IEN_PROP_TUNIEN_LSB         0
-+#define Si2158_MASTER_IEN_PROP_TUNIEN_MASK        0x01
-+#define Si2158_MASTER_IEN_PROP_TUNIEN_DEFAULT    0
-+#define Si2158_MASTER_IEN_PROP_TUNIEN_OFF  0
-+#define Si2158_MASTER_IEN_PROP_TUNIEN_ON   1
-+
-+
-+/* Si2158 TUNER_BLOCKED_VCO property definition */
-+#define Si2158_TUNER_BLOCKED_VCO_PROP 0x0504
-+
-+#define Si2158_TUNER_BLOCKED_VCO_PROP_CODE 0x000504
-+
-+typedef struct { /* Si2158_TUNER_BLOCKED_VCO_PROP_struct */
-+	s16    vco_code;
-+} Si2158_TUNER_BLOCKED_VCO_PROP_struct;
-+
-+/* TUNER_BLOCKED_VCO property, VCO_CODE field definition (NO TITLE)*/
-+#define Si2158_TUNER_BLOCKED_VCO_PROP_VCO_CODE_LSB         0
-+#define Si2158_TUNER_BLOCKED_VCO_PROP_VCO_CODE_MASK        0xffff
-+#define Si2158_TUNER_BLOCKED_VCO_PROP_VCO_CODE_DEFAULT    0x8000
-+#define Si2158_TUNER_BLOCKED_VCO_PROP_VCO_CODE_VCO_CODE_MIN  -32768
-+#define Si2158_TUNER_BLOCKED_VCO_PROP_VCO_CODE_VCO_CODE_MAX  32767
-+
-+
-+/* Si2158 TUNER_IEN property definition */
-+#define Si2158_TUNER_IEN_PROP 0x0501
-+
-+#define Si2158_TUNER_IEN_PROP_CODE 0x000501
-+
-+typedef struct { /* Si2158_TUNER_IEN_PROP_struct */
-+	u8   rssihien;
-+	u8   rssilien;
-+	u8   tcien;
-+} Si2158_TUNER_IEN_PROP_struct;
-+
-+/* TUNER_IEN property, RSSIHIEN field definition (NO TITLE)*/
-+#define Si2158_TUNER_IEN_PROP_RSSIHIEN_LSB         2
-+#define Si2158_TUNER_IEN_PROP_RSSIHIEN_MASK        0x01
-+#define Si2158_TUNER_IEN_PROP_RSSIHIEN_DEFAULT    0
-+#define Si2158_TUNER_IEN_PROP_RSSIHIEN_DISABLE  0
-+#define Si2158_TUNER_IEN_PROP_RSSIHIEN_ENABLE   1
-+
-+/* TUNER_IEN property, RSSILIEN field definition (NO TITLE)*/
-+#define Si2158_TUNER_IEN_PROP_RSSILIEN_LSB         1
-+#define Si2158_TUNER_IEN_PROP_RSSILIEN_MASK        0x01
-+#define Si2158_TUNER_IEN_PROP_RSSILIEN_DEFAULT    0
-+#define Si2158_TUNER_IEN_PROP_RSSILIEN_DISABLE  0
-+#define Si2158_TUNER_IEN_PROP_RSSILIEN_ENABLE   1
-+
-+/* TUNER_IEN property, TCIEN field definition (NO TITLE)*/
-+#define Si2158_TUNER_IEN_PROP_TCIEN_LSB         0
-+#define Si2158_TUNER_IEN_PROP_TCIEN_MASK        0x01
-+#define Si2158_TUNER_IEN_PROP_TCIEN_DEFAULT    1
-+#define Si2158_TUNER_IEN_PROP_TCIEN_DISABLE  0
-+#define Si2158_TUNER_IEN_PROP_TCIEN_ENABLE   1
-+
-+
-+/* Si2158 TUNER_INT_SENSE property definition */
-+#define Si2158_TUNER_INT_SENSE_PROP 0x0505
-+
-+#define Si2158_TUNER_INT_SENSE_PROP_CODE 0x000505
-+
-+typedef struct { /* Si2158_TUNER_INT_SENSE_PROP_struct */
-+	u8   rssihnegen;
-+	u8   rssihposen;
-+	u8   rssilnegen;
-+	u8   rssilposen;
-+	u8   tcnegen;
-+	u8   tcposen;
-+} Si2158_TUNER_INT_SENSE_PROP_struct;
-+
-+/* TUNER_INT_SENSE property, RSSIHNEGEN field definition (NO TITLE)*/
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSIHNEGEN_LSB         2
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSIHNEGEN_MASK        0x01
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSIHNEGEN_DEFAULT    0
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSIHNEGEN_DISABLE  0
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSIHNEGEN_ENABLE   1
-+
-+/* TUNER_INT_SENSE property, RSSIHPOSEN field definition (NO TITLE)*/
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSIHPOSEN_LSB         10
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSIHPOSEN_MASK        0x01
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSIHPOSEN_DEFAULT    1
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSIHPOSEN_DISABLE  0
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSIHPOSEN_ENABLE   1
-+
-+/* TUNER_INT_SENSE property, RSSILNEGEN field definition (NO TITLE)*/
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSILNEGEN_LSB         1
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSILNEGEN_MASK        0x01
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSILNEGEN_DEFAULT    0
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSILNEGEN_DISABLE  0
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSILNEGEN_ENABLE   1
-+
-+/* TUNER_INT_SENSE property, RSSILPOSEN field definition (NO TITLE)*/
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSILPOSEN_LSB         9
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSILPOSEN_MASK        0x01
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSILPOSEN_DEFAULT    1
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSILPOSEN_DISABLE  0
-+#define Si2158_TUNER_INT_SENSE_PROP_RSSILPOSEN_ENABLE   1
-+
-+/* TUNER_INT_SENSE property, TCNEGEN field definition (NO TITLE)*/
-+#define Si2158_TUNER_INT_SENSE_PROP_TCNEGEN_LSB         0
-+#define Si2158_TUNER_INT_SENSE_PROP_TCNEGEN_MASK        0x01
-+#define Si2158_TUNER_INT_SENSE_PROP_TCNEGEN_DEFAULT    0
-+#define Si2158_TUNER_INT_SENSE_PROP_TCNEGEN_DISABLE  0
-+#define Si2158_TUNER_INT_SENSE_PROP_TCNEGEN_ENABLE   1
-+
-+/* TUNER_INT_SENSE property, TCPOSEN field definition (NO TITLE)*/
-+#define Si2158_TUNER_INT_SENSE_PROP_TCPOSEN_LSB         8
-+#define Si2158_TUNER_INT_SENSE_PROP_TCPOSEN_MASK        0x01
-+#define Si2158_TUNER_INT_SENSE_PROP_TCPOSEN_DEFAULT    1
-+#define Si2158_TUNER_INT_SENSE_PROP_TCPOSEN_DISABLE  0
-+#define Si2158_TUNER_INT_SENSE_PROP_TCPOSEN_ENABLE   1
-+
-+
-+/* Si2158 TUNER_LO_INJECTION property definition */
-+#define Si2158_TUNER_LO_INJECTION_PROP 0x0506
-+
-+#define Si2158_TUNER_LO_INJECTION_PROP_CODE 0x000506
-+
-+typedef struct { /* Si2158_TUNER_LO_INJECTION_PROP_struct */
-+	u8   band_1;
-+	u8   band_2;
-+	u8   band_3;
-+} Si2158_TUNER_LO_INJECTION_PROP_struct;
-+
-+/* TUNER_LO_INJECTION property, BAND_1 field definition (NO TITLE)*/
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_1_LSB         0
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_1_MASK        0x01
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_1_DEFAULT    1
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_1_LOW_SIDE   0
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_1_HIGH_SIDE  1
-+
-+/* TUNER_LO_INJECTION property, BAND_2 field definition (NO TITLE)*/
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_2_LSB         1
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_2_MASK        0x01
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_2_DEFAULT    0
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_2_LOW_SIDE   0
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_2_HIGH_SIDE  1
-+
-+/* TUNER_LO_INJECTION property, BAND_3 field definition (NO TITLE)*/
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_3_LSB         2
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_3_MASK        0x01
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_3_DEFAULT    0
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_3_LOW_SIDE   0
-+#define Si2158_TUNER_LO_INJECTION_PROP_BAND_3_HIGH_SIDE  1
-+
-+
-+/* Si2158 TUNER_RETURN_LOSS property definition */
-+#define Si2158_TUNER_RETURN_LOSS_PROP 0x0507
-+
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CODE 0x000507
-+
-+typedef struct { /* Si2158_TUNER_RETURN_LOSS_PROP_struct */
-+	u8   config;
-+	u8   mode;
-+} Si2158_TUNER_RETURN_LOSS_PROP_struct;
-+
-+/* TUNER_RETURN_LOSS property, CONFIG field definition (NO TITLE)*/
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_LSB         0
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_MASK        0xff
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_DEFAULT    127
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_27   27
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_31   31
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_35   35
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_39   39
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_43   43
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_47   47
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_51   51
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_59   59
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_67   67
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_75   75
-+#ifdef __SI2157__
-+#define Si2157_TUNER_RETURN_LOSS_PROP_CONFIG_83   83
-+#define Si2157_TUNER_RETURN_LOSS_PROP_CONFIG_91   91
-+#define Si2157_TUNER_RETURN_LOSS_PROP_CONFIG_103  103
-+#define Si2157_TUNER_RETURN_LOSS_PROP_CONFIG_115  115
-+#endif /* __SI2157__ */
-+#define Si2158_TUNER_RETURN_LOSS_PROP_CONFIG_127  127
-+
-+/* TUNER_RETURN_LOSS property, MODE field definition (NO TITLE)*/
-+#define Si2158_TUNER_RETURN_LOSS_PROP_MODE_LSB         8
-+#define Si2158_TUNER_RETURN_LOSS_PROP_MODE_MASK        0xff
-+#define Si2158_TUNER_RETURN_LOSS_PROP_MODE_DEFAULT     0
-+#define Si2158_TUNER_RETURN_LOSS_PROP_MODE_TERRESTRIAL 0
-+#define Si2158_TUNER_RETURN_LOSS_PROP_MODE_CABLE       1
-+
-+
-+/* Si2158 XOUT property definition */
-+#define Si2158_XOUT_PROP 0x0404
-+
-+#define Si2158_XOUT_PROP_CODE 0x000404
-+
-+typedef struct { /* Si2158_XOUT_PROP_struct */
-+	u8   amp;
-+} Si2158_XOUT_PROP_struct;
-+
-+/* XOUT property, AMP field definition (NO TITLE)*/
-+#define Si2158_XOUT_PROP_AMP_LSB     0
-+#define Si2158_XOUT_PROP_AMP_MASK    0x01
-+#define Si2158_XOUT_PROP_AMP_DEFAULT 0
-+#define Si2158_XOUT_PROP_AMP_HIGH    0
-+#define Si2158_XOUT_PROP_AMP_LOW     1
-+
-+#if 0
-+/* --------------------------------------------*/
-+/* COMMANDS STRUCT                             */
-+/* This is used to store all command fields    */
-+/* --------------------------------------------*/
-+typedef struct { /* silabs_tercab_cmd_obj struct */
-+	Si2158_AGC_OVERRIDE_CMD_struct     agc_override;
-+	Si2158_ATV_CW_TEST_CMD_struct      atv_cw_test;
-+	Si2158_ATV_RESTART_CMD_struct      atv_restart;
-+	Si2158_ATV_STATUS_CMD_struct       atv_status;
-+	Si2158_CONFIG_CLOCKS_CMD_struct    config_clocks;
-+	Si2177_CONFIG_I2C_CMD_struct       config_i2c;
-+	Si2158_CONFIG_PINS_CMD_struct      config_pins;
-+	Si2158_DTV_RESTART_CMD_struct      dtv_restart;
-+	Si2158_DTV_STATUS_CMD_struct       dtv_status;
-+	Si2158_EXIT_BOOTLOADER_CMD_struct  exit_bootloader;
-+	Si2158_FINE_TUNE_CMD_struct        fine_tune;
-+	Si2158_GET_PROPERTY_CMD_struct     get_property;
-+	Si2158_GET_REV_CMD_struct          get_rev;
-+	Si2158_PART_INFO_CMD_struct        part_info;
-+	Si2158_POWER_DOWN_CMD_struct       power_down;
-+	Si2158_POWER_DOWN_HW_CMD_struct    power_down_hw;
-+	Si2158_POWER_UP_CMD_struct         power_up;
-+	Si2158_RAM_CRC_CMD_struct          ram_crc;
-+	Si2158_SET_PROPERTY_CMD_struct     set_property;
-+	Si2158_STANDBY_CMD_struct          standby;
-+	Si2158_TUNER_STATUS_CMD_struct     tuner_status;
-+	Si2158_TUNER_TUNE_FREQ_CMD_struct  tuner_tune_freq;
-+} silabs_tercab_cmd_obj;
-+#endif
-+/* --------------------------------------------*/
-+/* COMMANDS REPLY STRUCT                       */
-+/* This stores all command reply fields        */
-+/* --------------------------------------------*/
-+typedef struct { /* silabs_tercap_cmd_reply_obj struct */
-+	Si2158_ATV_STATUS_CMD_REPLY_struct   atv_status;
-+	Si2158_DTV_STATUS_CMD_REPLY_struct   dtv_status;
-+	Si2158_PART_INFO_CMD_REPLY_struct    part_info;
-+	Si2158_TUNER_STATUS_CMD_REPLY_struct tuner_status;
-+} silabs_tercap_cmd_reply;
-+
-+typedef struct silabs_tercab_context {
-+	u8 chiprev;	  /*chip rev constants for integrity checking */
-+	u8 part;      /* Last 2 digits of part number */
-+	u8 i2c_addr;
-+	struct i2c_adapter *i2c_adap;
-+	silabs_tercap_cmd_reply rsp;
-+	silabs_tercab_status status;
-+} silabs_tercab_context;
-+
-+struct silabs_tercab_priv {
-+	struct list_head hybrid_tuner_instance_list;
-+	struct tuner_i2c_props i2c_props;
-+	struct i2c_client *client;
-+	struct dvb_frontend *fe;
-+	struct mutex lock;
-+	silabs_tercab_context tuner;
-+
-+	enum silabs_tercab_mode mode;
-+
-+	u32 frequency;
-+	u32 if_frequency;
-+	u32 bandwidth;
-+	u16 qam_if_khz;
-+	u16 vsb_if_khz;
-+	u8  clock_control;
-+	u8  agc_control;
-+	u8  fef_mode;
-+	u8  crystal_trim_xo_cap;
-+	u8  indirect_i2c_connection;
-+	int silabs_tercab_init_done;
-+	int firmware_started;
-+
-+	const struct silabs_tercab_config *config;
-+};
-+
-+struct part_info {
-+	u8  chiprev;
-+	u8  romid;
-+	u8  part;
-+	u8  pmajor;
-+	u8  pminor;
-+	u8  pbuild;
-+	u16 reserved;
-+	u32 serial;
-+};
-+
-+/* Layer 1 core types definitions */
-+typedef enum ErrorCode
-+{
-+	Error_CODE_BASE                 = 2000,
-+	Error_INCORRECT_NB_READ,       /* 2001 */
-+	Error_INCORRECT_NB_WRITTEN,    /* 2002 */
-+	Error_DLL_LOAD,                /* 2003 */
-+	Error_ENUM_VAL_UNKNOWN,        /* 2004 */
-+	Error_COULD_NOT_WRITE_ITEM,    /* 2005 */
-+	Error_REGISTER_TYPE_UNKNOWN,   /* 2006 */
-+	Error_ENUM_OUT_OF_RANGE,       /* 2007 */
-+	Error_TYPE_IS_NOT_ENUMERATE,   /* 2008 */
-+	Error_VALUE_NOT_IN_ENUM_LIST,  /* 2009 */
-+	Error_COULD_NOT_UPDATE_ITEM,   /* 2010 */
-+	Error_VALUE_OUT_OF_RANGE,      /* 2011 */
-+	Error_UNKNOW_REGISTER,         /* 2012 */
-+	Error_READ_TRACES_ERROR,       /* 2013 */
-+	Error_WRITE_TRACES_ERROR,      /* 2014 */
-+	Error_UNKNOWN_COMMAND,         /* 2015 */
-+	Error_BUFFER_DOES_NOT_CONTAIN_REQUIRED_DATA         /* 2016 */
-+} ErrorCode;
-+
-+#define Si2158_GET_PROPERTY_STRING
-+
-+#define NO_SILABS_TERCAB_ERROR                     0x00
-+#define ERROR_SILABS_TERCAB_PARAMETER_OUT_OF_RANGE 0x01
-+#define ERROR_SILABS_TERCAB_ALLOCATING_CONTEXT     0x02
-+#define ERROR_SILABS_TERCAB_SENDING_COMMAND        0x03
-+#define ERROR_SILABS_TERCAB_CTS_TIMEOUT            0x04
-+#define ERROR_SILABS_TERCAB_ERR                    0x05
-+#define ERROR_SILABS_TERCAB_POLLING_CTS            0x06
-+#define ERROR_SILABS_TERCAB_POLLING_RESPONSE       0x07
-+#define ERROR_SILABS_TERCAB_LOADING_FIRMWARE       0x08
-+#define ERROR_SILABS_TERCAB_LOADING_BOOTBLOCK      0x09
-+#define ERROR_SILABS_TERCAB_STARTING_FIRMWARE      0x0a
-+#define ERROR_SILABS_TERCAB_SW_RESET               0x0b
-+#define ERROR_SILABS_TERCAB_INCOMPATIBLE_PART      0x0c
-+#define ERROR_SILABS_TERCAB_TUNINT_TIMEOUT         0x0d
-+#define ERROR_SILABS_TERCAB_xTVINT_TIMEOUT         0x0e
-+#define ERROR_SILABS_TERCAB_CRC_CHECK_ERROR        0x10
-+#ifdef __SI2157__
-+#define ERROR_Si2157_UNKNOWN_COMMAND               0xf0
-+#define ERROR_Si2157_UNKNOWN_PROPERTY              0xf1
-+#endif /* __SI2157__ */
-+
-+/* SI2157_FIRMWARE_3_0_BUILD_5 */
-+firmware_struct Si2157_FW_3_0b5[] = {
-+		{ 16 , { 0xBF,0x21,0xB1,0xF8,0x50,0xD4,0xBD,0xDA,0x05,0x05,0xEE,0xC4,0xC2,0x3D,0x38,0x3E } },
-+		{ 8 , { 0x05,0x37,0x88,0x3C,0xE8,0x9D,0x8C,0x73 } },
-+		{ 16 , { 0x37,0x7E,0x76,0x05,0x28,0xFF,0xE7,0x9E,0xFF,0xB2,0xAC,0xA8,0x4C,0x34,0x27,0xD5 } },
-+		{ 16 , { 0x37,0x61,0x1B,0x98,0x42,0x2A,0xF4,0x94,0x3A,0x41,0x54,0x62,0xC5,0x63,0x64,0xE8 } },
-+		{ 8 , { 0x0F,0x25,0x9C,0x90,0x29,0xF4,0x01,0xB9 } },
-+		{ 16 , { 0x3F,0x19,0x38,0xD3,0xCF,0x93,0x28,0xE7,0x0F,0x88,0x6E,0x9A,0x63,0x9D,0xC8,0xA9 } },
-+		{ 11 , { 0x3A,0xF5,0x4F,0x80,0x53,0xA7,0x3B,0x61,0x61,0xB8,0x8E } },
-+		{ 11 , { 0x07,0x35,0xFD,0xB8,0x08,0x47,0xD6,0xEF,0x42,0x55,0xB3 } },
-+		{ 11 , { 0x0F,0x37,0x0E,0x93,0x3C,0xC5,0x95,0x6E,0x4A,0x16,0x87 } },
-+		{ 8 , { 0x07,0xE0,0x62,0xC7,0x47,0x85,0x6F,0xE4 } },
-+		{ 16 , { 0x3F,0xD1,0xE5,0xEB,0x0F,0xF8,0x8F,0x2E,0x92,0xEC,0xF8,0xF5,0xF5,0x4B,0x03,0x60 } },
-+		{ 14 , { 0x4A,0xA5,0xC6,0x07,0x43,0x80,0x4D,0x16,0x73,0x23,0x62,0x4A,0x40,0xC6 } },
-+		{ 8 , { 0x07,0xE8,0xC4,0x65,0xF3,0xE8,0xA8,0x40 } },
-+		{ 9 , { 0x38,0xC6,0xF7,0xA0,0x83,0xDE,0x0A,0x2B,0xD9 } },
-+		{ 16 , { 0x0F,0x90,0x5C,0x69,0x81,0x8E,0x3B,0x10,0x0F,0x04,0xB5,0x39,0xC5,0x45,0xD1,0x30 } },
-+		{ 16 , { 0x07,0x94,0xB3,0xE8,0x5A,0xCD,0x12,0x3E,0x0F,0x52,0x02,0x0B,0x4C,0xA8,0x53,0x25 } },
-+		{ 11 , { 0x0F,0x74,0xE6,0x3B,0xC2,0x52,0x80,0x11,0x4A,0xD8,0xF7 } },
-+		{ 14 , { 0x07,0x12,0x8F,0xAF,0x41,0xAA,0x21,0x92,0x45,0x97,0xDE,0x8C,0xDF,0x61 } },
-+		{ 8 , { 0x07,0x6C,0xF5,0xD0,0x97,0x73,0x1D,0x64 } },
-+		{ 9 , { 0x30,0x59,0x7F,0xD1,0xF3,0x95,0x19,0x8C,0x83 } },
-+		{ 11 , { 0x0F,0xA5,0xEB,0x96,0x1A,0xF7,0xDD,0xCF,0x42,0xCF,0x67 } },
-+		{ 8 , { 0x07,0xBF,0x08,0xF6,0x58,0x2B,0xE6,0xF6 } },
-+		{ 16 , { 0x3F,0x7A,0x11,0xF4,0x49,0xA2,0x2B,0x77,0xAA,0xFC,0xA4,0x62,0x96,0x92,0x2E,0x2E } },
-+		{ 14 , { 0x42,0x2E,0xA7,0x07,0x4D,0x77,0x36,0x86,0x14,0xA8,0xF6,0x42,0x50,0xED } },
-+		{ 16 , { 0x07,0xC9,0xCC,0xF5,0x96,0x73,0x36,0x27,0x0F,0x46,0xAD,0xB8,0x42,0xBB,0x20,0x5D } },
-+		{ 8 , { 0x07,0x65,0x6C,0x82,0x0F,0xD3,0x75,0x2C } },
-+		{ 12 , { 0x33,0x94,0xF7,0xCA,0x9B,0x4B,0x3D,0x9D,0x60,0x6A,0xF1,0xCF } },
-+		{ 11 , { 0x0F,0x32,0x3B,0x72,0xF8,0x49,0x84,0xFB,0x42,0x0F,0x42 } },
-+		{ 11 , { 0x07,0x26,0x87,0x28,0x8F,0x05,0xA3,0xAD,0x4A,0x59,0xC3 } },
-+		{ 16 , { 0x0A,0xBE,0xBB,0x9F,0x7D,0xE9,0x1A,0x74,0x12,0xD6,0xED,0xA3,0xB8,0x4A,0xDE,0x61 } },
-+		{ 8 , { 0x0F,0xB0,0x9C,0x7C,0x83,0xAE,0x64,0x9E } },
-+		{ 9 , { 0x30,0x48,0xE3,0xC4,0xDF,0xB6,0x69,0xB1,0x28 } },
-+		{ 11 , { 0x0F,0x33,0xAF,0x5A,0x2A,0xCE,0xFF,0xC2,0x4A,0x91,0x28 } },
-+		{ 8 , { 0x0F,0xF9,0xC1,0x42,0xA9,0x47,0x1C,0x6F } },
-+		{ 15 , { 0x36,0x39,0xE5,0x7D,0x4E,0xFE,0x74,0xA9,0x56,0x6F,0xB5,0x45,0x4E,0x3B,0x11 } },
-+		{ 8 , { 0x07,0x89,0xCB,0x17,0x5D,0x68,0x45,0xE4 } },
-+		{ 16 , { 0x3F,0xE5,0x65,0x79,0xE1,0x2F,0x88,0xAE,0x71,0x61,0xC6,0x44,0x08,0x9A,0xEC,0xA6 } },
-+		{ 8 , { 0x07,0x69,0x5C,0x05,0xA4,0x7B,0x8C,0xB8 } },
-+		{ 16 , { 0x3F,0xFD,0xF6,0x55,0x1C,0xE7,0x84,0xEF,0x78,0xA2,0x15,0x4C,0x27,0x20,0xE2,0xFC } },
-+		{ 9 , { 0x30,0x72,0x05,0x23,0x31,0xA9,0x3F,0x1C,0xD0 } },
-+		{ 11 , { 0x07,0xF3,0xC2,0xC4,0x9E,0xD9,0xD3,0x2E,0x42,0x0A,0x09 } },
-+		{ 8 , { 0x07,0x7F,0x52,0x33,0xF7,0x79,0x0C,0x79 } },
-+		{ 16 , { 0x3F,0xC0,0xCC,0xD6,0x65,0xC1,0xD2,0xEC,0x6F,0xB4,0xDC,0x42,0x26,0xCC,0xDF,0x8F } },
-+		{ 8 , { 0x07,0x7C,0x43,0x52,0xB1,0x44,0x70,0xDC } },
-+		{ 9 , { 0x38,0x66,0xE8,0x62,0xEA,0xE4,0xBA,0xFF,0xBB } },
-+		{ 8 , { 0x0F,0x22,0xFA,0xF3,0xA6,0xE9,0xDC,0xFB } },
-+		{ 15 , { 0x3E,0xE3,0x1F,0x9D,0xC0,0x56,0xB9,0xDD,0x71,0xA1,0x42,0x1C,0xD4,0x7C,0x0E } },
-+		{ 15 , { 0x0F,0x6A,0x56,0xB2,0x84,0x4F,0xB2,0xA9,0x4E,0x67,0x14,0x82,0x57,0x3F,0xC8 } },
-+		{ 11 , { 0x0F,0x87,0xA0,0x15,0x24,0x5F,0x03,0xF9,0x4A,0x50,0xB3 } },
-+		{ 8 , { 0x0F,0x5B,0x7E,0x34,0x20,0x7A,0xC3,0xCF } },
-+		{ 12 , { 0x33,0x5C,0xCB,0x58,0x7F,0x83,0x83,0xF7,0xC0,0x9E,0xC0,0x89 } },
-+		{ 11 , { 0x0F,0x03,0x21,0x5C,0x19,0x58,0x3B,0x1F,0x42,0xB8,0x7B } },
-+		{ 11 , { 0x07,0xDA,0x87,0x66,0x4A,0x8F,0xDB,0xCE,0x4A,0x04,0xBF } },
-+		{ 8 , { 0x0F,0xD1,0xA3,0x5A,0xEC,0xB0,0xE1,0xA0 } },
-+		{ 12 , { 0x3B,0xF6,0x00,0xE4,0x3D,0xDD,0x51,0x25,0x27,0xD2,0x50,0xB6 } },
-+		{ 8 , { 0x0F,0xA2,0x36,0x93,0x50,0xD5,0xF8,0xE1 } },
-+		{ 16 , { 0x3F,0x18,0x99,0xAE,0x84,0x94,0xE4,0x94,0xDE,0x75,0x12,0xE3,0xAA,0xD2,0x3D,0x18 } },
-+		{ 11 , { 0x42,0xDB,0x33,0x07,0x2B,0x3C,0x18,0x8C,0x92,0x18,0x69 } },
-+		{ 16 , { 0x07,0x6C,0x85,0xAA,0x6D,0xFD,0x7A,0xBD,0x07,0xB1,0x16,0x9B,0x5B,0xBA,0x9E,0x52 } },
-+		{ 16 , { 0x3F,0x96,0x5C,0x2B,0x48,0x02,0x12,0x13,0x54,0xDD,0xAA,0x3F,0x44,0x14,0x6E,0x87 } },
-+		{ 14 , { 0x4D,0x4C,0xF3,0x8A,0x52,0x04,0x0F,0x23,0x9C,0x12,0x15,0xB3,0xBA,0x00 } },
-+		{ 14 , { 0x4D,0x2B,0x05,0x56,0x44,0x3A,0x07,0x40,0x3A,0x70,0xDA,0x3C,0x41,0xB2 } },
-+		{ 12 , { 0x33,0xFB,0xE7,0x39,0x88,0x89,0x25,0x73,0x29,0xDB,0x47,0x09 } },
-+		{ 11 , { 0x0F,0x39,0x30,0x9F,0xF9,0xD5,0x7B,0xB5,0x42,0x11,0x97 } },
-+		{ 16 , { 0x07,0xC2,0xCD,0xF1,0x7C,0x63,0x5B,0x26,0x07,0x04,0xDD,0x5B,0x94,0x45,0xC8,0x9C } },
-+		{ 14 , { 0x07,0x0C,0x4A,0x33,0xFA,0x28,0x1D,0x6B,0x4D,0x11,0xDC,0xA2,0xA7,0x84 } },
-+		{ 11 , { 0x0F,0xD1,0x46,0xE6,0x27,0xBB,0xAD,0x8D,0x42,0xCE,0x58 } },
-+		{ 11 , { 0x0F,0xD5,0xE3,0x25,0x5F,0x6F,0x1E,0xFC,0x42,0x93,0x8D } },
-+		{ 8 , { 0x0F,0xD9,0xAB,0xC7,0xD7,0x96,0xF8,0xBE } },
-+		{ 9 , { 0x30,0xA5,0x11,0xDE,0x14,0x5E,0xA3,0x07,0xBE } },
-+		{ 8 , { 0x0F,0xFF,0xB5,0x28,0x4F,0xCF,0xA7,0x3C } },
-+		{ 16 , { 0x3F,0x86,0x17,0x1A,0x00,0x6C,0xBF,0x7F,0x83,0xB2,0x3F,0xE4,0xD2,0xFF,0xC2,0x18 } },
-+		{ 16 , { 0x37,0x37,0x1B,0x81,0x82,0xFE,0x8C,0xC2,0x8A,0xB1,0x1C,0x4A,0x4B,0x8A,0x94,0x66 } },
-+		{ 16 , { 0x37,0x80,0x53,0x9C,0x2B,0x32,0x97,0xE4,0x7A,0x5A,0xE2,0xF3,0x75,0x47,0xA6,0xF1 } },
-+		{ 16 , { 0x3F,0x44,0xCF,0x82,0x2F,0xD8,0x5D,0xED,0x9F,0xC0,0x3A,0x28,0x7F,0x7C,0x21,0x53 } },
-+		{ 15 , { 0x3E,0x31,0x35,0xA6,0xF3,0xC8,0xAA,0x7E,0x98,0x8E,0x60,0x80,0xE0,0xE6,0xCC } },
-+		{ 8 , { 0x07,0xB8,0x98,0xC0,0xA5,0xC9,0x9E,0x6A } },
-+		{ 11 , { 0x32,0xEC,0x2E,0x11,0xB6,0x4C,0x71,0xBF,0xC2,0x31,0x1C } },
-+		{ 8 , { 0x0F,0x00,0x13,0x7B,0x74,0xBC,0xD8,0x8B } },
-+		{ 11 , { 0x32,0x7F,0xFD,0x3D,0x1A,0x34,0x1C,0x25,0x50,0xBB,0xD3 } },
-+		{ 8 , { 0x07,0x7E,0xAE,0x2A,0x43,0x25,0x07,0x9C } },
-+		{ 13 , { 0x34,0x8C,0xF2,0xD5,0x5D,0x83,0xF7,0xD6,0x82,0xD4,0x12,0xB5,0x7B } },
-+		{ 8 , { 0x07,0xBC,0xC7,0x76,0x7E,0xDD,0xF4,0xA2 } },
-+		{ 16 , { 0x3F,0x91,0x33,0x61,0xAB,0x3A,0x7F,0x94,0x75,0x86,0xC8,0x5B,0xB6,0xE9,0x4C,0x6F } },
-+		{ 16 , { 0x37,0xB4,0x2A,0x7D,0xFB,0xDD,0x19,0x38,0xA4,0x06,0xE3,0xF9,0x02,0x25,0x1D,0x5D } },
-+		{ 16 , { 0x37,0x80,0xDD,0xAC,0x0A,0x35,0x44,0xC4,0xC9,0x80,0x46,0x5A,0x84,0x78,0x32,0x08 } },
-+		{ 16 , { 0x37,0x2D,0xA5,0x43,0xA2,0x87,0xDC,0x80,0xE9,0xE0,0xDA,0xDD,0x7B,0xD0,0x94,0x9E } },
-+		{ 16 , { 0x3F,0xD8,0x40,0x1F,0xDC,0x59,0x13,0xC3,0xEA,0x88,0x9F,0x8E,0xD5,0xB8,0x7D,0xDF } },
-+		{ 16 , { 0x37,0x94,0xB8,0x51,0x44,0x90,0x8B,0x9A,0xF7,0x4C,0x51,0xCB,0x3D,0xA7,0xEC,0x49 } },
-+		{ 16 , { 0x3F,0x6E,0x1D,0xD3,0xDB,0x45,0xC1,0x0C,0xA2,0x8E,0xA7,0xD4,0x32,0x7A,0x41,0x13 } },
-+		{ 16 , { 0x3F,0xFA,0x54,0xF6,0xCB,0x58,0x83,0x00,0x60,0x60,0x06,0x62,0x42,0xAD,0xD2,0xD9 } },
-+		{ 16 , { 0x37,0xAD,0x2E,0xDB,0x84,0xB3,0xFE,0xB6,0x7C,0xA9,0x6D,0x2D,0x40,0x30,0x10,0x15 } },
-+		{ 16 , { 0x37,0x3D,0xBC,0x3F,0xA5,0xD1,0x7F,0x67,0x2F,0xEE,0x6D,0x40,0x5E,0x9C,0x27,0xCF } },
-+		{ 16 , { 0x3F,0x56,0xDD,0xBE,0x1E,0xC1,0xDE,0xC4,0x2D,0xC5,0xA9,0xC1,0xF6,0x90,0xF5,0x60 } },
-+		{ 16 , { 0x37,0x2E,0xCF,0x9E,0x9E,0x48,0x77,0x0A,0xEF,0x20,0x7F,0xC2,0x3D,0xF3,0x89,0x09 } },
-+		{ 12 , { 0x4B,0x61,0x03,0x39,0x0F,0x42,0x5F,0x38,0xB8,0xE0,0xB1,0x6F } },
-+		{ 16 , { 0x37,0xC0,0xD5,0xD8,0xEE,0xA6,0xD2,0xFA,0x1D,0x3C,0x14,0xE4,0xA8,0x46,0x39,0x81 } },
-+		{ 11 , { 0x42,0xCA,0x93,0x0F,0x49,0xDE,0x8A,0xFD,0x03,0xA9,0x8D } },
-+		{ 16 , { 0x3F,0x00,0x49,0x34,0x7E,0xC3,0xF5,0x0A,0x2D,0x92,0xAC,0x4D,0x5F,0x4A,0x79,0x5C } },
-+		{ 14 , { 0x35,0x62,0xD2,0xB7,0xEB,0x20,0x05,0x91,0x94,0xB3,0xAA,0xC1,0x99,0x0F } },
-+		{ 16 , { 0x0F,0x6A,0x19,0xA9,0x88,0x8C,0x15,0x60,0x07,0x46,0x2D,0xAF,0xAF,0x89,0x27,0x5B } },
-+		{ 8 , { 0x07,0xD9,0x28,0x8D,0x41,0xEA,0x18,0x2D } },
-+		{ 13 , { 0x3C,0xD9,0x32,0x17,0x25,0x6E,0x6F,0xA3,0xAB,0x11,0x31,0x68,0x94 } },
-+		{ 8 , { 0x0F,0xF1,0x57,0xF0,0xA4,0x1C,0x39,0x3F } },
-+		{ 16 , { 0x3F,0xF2,0xF4,0xAE,0xB6,0xD9,0xC2,0xE5,0x32,0x4C,0xCC,0xBE,0xFA,0xE0,0xF4,0xB5 } },
-+		{ 12 , { 0x4B,0xB6,0xAB,0x11,0x07,0x5E,0xFD,0x85,0x07,0x12,0x00,0x4E } },
-+		{ 16 , { 0x0F,0x62,0x77,0x4B,0x1C,0xE7,0xF6,0xCF,0x0F,0x6A,0x38,0xE0,0x0F,0xD3,0x38,0xF5 } },
-+		{ 15 , { 0x46,0x56,0x66,0xEA,0x53,0x0F,0xB1,0x07,0xE1,0xF9,0x0F,0x5D,0x1F,0x87,0xF8 } },
-+		{ 12 , { 0x43,0x78,0x82,0xAD,0x07,0xFE,0x7D,0xA3,0x16,0x91,0xDB,0xE5 } },
-+		{ 16 , { 0x3F,0x6E,0x45,0x3F,0xBF,0x02,0x48,0x32,0x36,0x9C,0x4A,0xCB,0xDA,0x27,0x8B,0x1D } },
-+		{ 16 , { 0x3F,0x80,0x02,0x95,0x30,0x74,0xFB,0xC6,0x4B,0x04,0xFC,0xE1,0x0B,0xCD,0x4B,0x79 } },
-+		{ 16 , { 0x3F,0xB6,0x0A,0xFE,0x6C,0x99,0x59,0x3A,0xD2,0xD9,0x04,0xBF,0x7D,0x39,0xE5,0xB3 } },
-+		{ 16 , { 0x3F,0x59,0x27,0x2B,0x03,0x7B,0xE3,0xE2,0xFF,0x1B,0x86,0x58,0x5D,0xDD,0xA2,0x3B } },
-+		{ 16 , { 0x37,0x42,0x1B,0x79,0xAD,0x8F,0x9B,0x68,0x3A,0x81,0xFA,0x18,0x37,0xC4,0x4F,0x3D } },
-+		{ 16 , { 0x3F,0x14,0x7C,0x79,0x53,0x52,0xA5,0x31,0xA3,0x19,0x57,0xC2,0xDE,0xB5,0x6A,0x14 } },
-+		{ 16 , { 0x3F,0x7E,0x5E,0xB9,0xFE,0xBF,0xCD,0x3E,0xC4,0xA9,0x43,0x9A,0xF8,0xA8,0xF7,0x88 } },
-+		{ 16 , { 0x37,0x99,0xEC,0xB0,0xD5,0x6C,0x71,0x8F,0x91,0x44,0x74,0x4A,0x1B,0x39,0x94,0x29 } },
-+		{ 16 , { 0x3F,0x40,0x38,0x62,0xDD,0x93,0xFB,0xCB,0x05,0xD9,0x88,0x18,0x33,0xB7,0x8A,0xE3 } },
-+		{ 14 , { 0x35,0xA6,0x13,0x62,0xFF,0x44,0x4C,0xF0,0x04,0xCA,0xBA,0xE6,0x5B,0x93 } },
-+		{ 16 , { 0x07,0xFE,0x29,0x6D,0xAD,0x38,0xD1,0xE9,0x07,0xA3,0x64,0x82,0x18,0x5E,0x46,0x84 } },
-+		{ 8 , { 0x07,0x15,0x32,0x84,0x60,0x3E,0xCA,0x70 } },
-+		{ 16 , { 0x37,0x29,0x2C,0xA9,0xD8,0xD6,0x8B,0x10,0x0A,0x60,0x9C,0xA0,0x68,0x6B,0x55,0xE7 } },
-+		{ 16 , { 0x37,0x8B,0x84,0xB7,0x98,0x73,0x79,0x45,0xD8,0x14,0x8F,0xFB,0x76,0x9C,0x3F,0xA0 } },
-+		{ 12 , { 0x3B,0xF1,0x16,0x24,0xC8,0x0B,0x2F,0xF6,0x82,0x38,0x2B,0x04 } },
-+		{ 16 , { 0x0F,0xD4,0xA4,0xF8,0x07,0x6C,0x30,0x5F,0x0F,0x2C,0xF3,0xC5,0x41,0x31,0xF2,0xC9 } },
-+		{ 8 , { 0x07,0x96,0x56,0x07,0x18,0x1C,0xBA,0x48 } },
-+		{ 16 , { 0x37,0x3A,0xCA,0x6D,0xB5,0xC7,0x14,0xDD,0xE5,0x68,0x63,0x10,0x70,0x7D,0xAF,0x36 } },
-+		{ 12 , { 0x4B,0x20,0x19,0xE4,0x07,0x1E,0xBB,0x82,0x34,0xE1,0x73,0x30 } },
-+		{ 8 , { 0x0F,0x38,0x5B,0xBA,0xBD,0x26,0xBF,0xEE } },
-+		{ 16 , { 0x3F,0x57,0x0D,0x9B,0x6B,0x4A,0xD0,0x74,0xC0,0x8A,0x92,0x68,0xA0,0x3C,0xA8,0xF1 } },
-+		{ 16 , { 0x37,0xE9,0x6E,0x50,0x76,0x7C,0x51,0x06,0x70,0x1B,0x06,0x6F,0x42,0xDC,0x8E,0x3E } },
-+		{ 16 , { 0x37,0x2E,0xAB,0x45,0x2C,0xBE,0xDA,0x19,0xA4,0xD5,0xC9,0x66,0xB9,0x0B,0x3A,0x0B } },
-+		{ 14 , { 0x35,0x68,0x6B,0xCC,0x33,0x46,0xF4,0x5F,0x17,0xE5,0x02,0xF0,0xCD,0x65 } },
-+		{ 8 , { 0x07,0xBB,0xE2,0xB6,0xCF,0x13,0xD3,0x6F } },
-+		{ 16 , { 0x3F,0x12,0xA4,0x99,0x1E,0x91,0x51,0x3D,0x77,0x99,0xE4,0x3C,0x7D,0xF4,0xA6,0xBB } },
-+		{ 10 , { 0x31,0x9C,0x6A,0x32,0xCE,0x00,0x1E,0x36,0x59,0x25 } },
-+		{ 16 , { 0x0F,0x6A,0x0B,0x4C,0x7E,0x1F,0x11,0x54,0x0F,0x24,0x71,0xA6,0xC2,0xDA,0x3B,0xBC } },
-+		{ 16 , { 0x0F,0x19,0x13,0x70,0x9E,0x0A,0xF4,0xB5,0x0F,0x58,0x5E,0xC5,0xFC,0x30,0xA4,0x42 } },
-+		{ 8 , { 0x07,0xBC,0xFA,0xCC,0xBD,0x2B,0x76,0xC0 } },
-+		{ 12 , { 0x3B,0x72,0xF4,0xCE,0x70,0x40,0x39,0xFC,0xBA,0xD0,0xA2,0x4F } },
-+		{ 16 , { 0x0F,0x3B,0x9F,0x47,0xED,0xBA,0xA7,0x72,0x0F,0x29,0x3A,0x7A,0x97,0xDA,0x12,0x9C } },
-+		{ 8 , { 0x0F,0x34,0x49,0x97,0x2B,0xB6,0xD0,0x66 } },
-+		{ 16 , { 0x3F,0xAD,0xFB,0xC5,0xDF,0x94,0x43,0xB3,0xE2,0x24,0x27,0x37,0xA1,0x50,0xB6,0x09 } },
-+		{ 10 , { 0x39,0x1D,0x5F,0x06,0x1B,0x96,0x0D,0x48,0x22,0x67 } },
-+		{ 16 , { 0x0F,0x02,0xBA,0xB1,0xDD,0xEA,0x97,0xD3,0x07,0x9E,0x8B,0xD7,0xBB,0x41,0x0A,0x72 } },
-+		{ 13 , { 0x0F,0x25,0xE3,0x4D,0x16,0x55,0x16,0x3B,0x44,0x08,0xB1,0x9D,0x63 } },
-+		{ 16 , { 0x0F,0xF5,0x2A,0xDF,0x2A,0xB7,0x2B,0x0B,0x0F,0xE2,0xFF,0xCC,0x0D,0x37,0x7A,0x9E } },
-+		{ 14 , { 0x45,0x84,0xCE,0x77,0x29,0x6D,0x07,0x09,0x0C,0x6B,0x83,0x21,0x2C,0x15 } },
-+		{ 8 , { 0x07,0x63,0xA0,0x85,0xEF,0x5A,0xD3,0x55 } },
-+		{ 9 , { 0x38,0xD5,0xC5,0xC5,0x3C,0xCB,0x70,0x54,0x69 } },
-+		{ 8 , { 0x07,0x7D,0xA2,0x73,0x6A,0x98,0x4D,0x27 } },
-+		{ 16 , { 0x3F,0x6C,0xE6,0x12,0x77,0x30,0x22,0x34,0xBB,0x27,0xBB,0xCD,0x4E,0xD0,0xE6,0xDF } },
-+		{ 16 , { 0x3F,0x10,0x54,0x9A,0x1F,0x07,0x35,0x14,0xE1,0x33,0x0A,0x9B,0x67,0x4D,0xA0,0x5D } },
-+		{ 12 , { 0x3B,0x56,0x33,0x93,0xC9,0xB3,0x30,0xA1,0x23,0xC8,0xDD,0xF5 } },
-+		{ 8 , { 0x07,0xB2,0x01,0x59,0x31,0xDA,0xE4,0xDF } },
-+		{ 16 , { 0x37,0xA6,0x2C,0xC8,0x2C,0x67,0x87,0xE6,0x00,0x8F,0x3E,0xC7,0x52,0x90,0xBE,0xD4 } },
-+		{ 11 , { 0x4A,0x72,0x20,0x07,0x61,0xFC,0x3E,0x1C,0x7F,0xF4,0x77 } },
-+		{ 14 , { 0x07,0xB2,0x8A,0x78,0xE5,0xED,0x6F,0x10,0x4D,0x47,0x27,0xA0,0x3A,0x71 } },
-+		{ 8 , { 0x07,0xF6,0x45,0x4E,0x76,0x6D,0x01,0xCC } },
-+		{ 16 , { 0x37,0x71,0xE1,0x5E,0xAF,0x55,0x06,0x4B,0x95,0x12,0xFF,0x95,0x6B,0x49,0xC4,0x46 } },
-+		{ 9 , { 0x38,0xCC,0x51,0x29,0xB5,0x81,0x39,0x55,0xB9 } },
-+		{ 8 , { 0x0F,0xD8,0xB3,0xDF,0xE6,0x61,0x5B,0x03 } },
-+		{ 16 , { 0x3F,0xE8,0x82,0xC6,0x1F,0x26,0xBE,0x33,0x3A,0x7A,0x1C,0xBF,0x31,0x90,0x25,0x6B } },
-+		{ 16 , { 0x3F,0x75,0x0F,0xDB,0x5A,0x87,0x26,0x5E,0x67,0x24,0xC3,0xB4,0xE9,0x43,0xAE,0x95 } },
-+		{ 16 , { 0x3F,0xAF,0xE1,0xC1,0x3B,0x56,0x3F,0x19,0xC5,0xE1,0xC4,0xBB,0x63,0x0A,0xC3,0x4E } },
-+		{ 13 , { 0x34,0x26,0xDC,0x69,0xF4,0xA9,0xAC,0x3B,0x98,0x13,0xF6,0x4E,0xAB } },
-+		{ 8 , { 0x0F,0xD4,0x90,0x19,0x0A,0xA5,0x8D,0xB8 } },
-+		{ 16 , { 0x3F,0xD2,0x8D,0xC3,0xA7,0x13,0x44,0x4C,0x23,0xF6,0xD2,0xDC,0xAB,0x0F,0x55,0x82 } },
-+		{ 12 , { 0x4B,0x84,0xBA,0x97,0x0F,0x79,0x49,0xDF,0x1E,0xF9,0xA1,0x48 } },
-+		{ 12 , { 0x33,0xE7,0x23,0x04,0xA1,0x71,0x37,0x3C,0x99,0x5D,0xF2,0x06 } },
-+		{ 8 , { 0x0F,0x27,0xDF,0xFD,0xB0,0xEA,0xD5,0xDD } },
-+		{ 16 , { 0x37,0x8D,0x8A,0xDB,0xDF,0x3F,0xF7,0xCD,0xC7,0x9E,0x7F,0x05,0xFD,0x77,0x33,0x20 } },
-+		{ 11 , { 0x4A,0xDA,0x04,0x0F,0x6A,0xD1,0xB2,0xAA,0x1A,0x55,0x55 } },
-+		{ 16 , { 0x3F,0x39,0xCB,0x0A,0x0C,0x92,0xE1,0xDB,0xB9,0xC6,0x7D,0x11,0x04,0xC7,0x87,0x66 } },
-+		{ 15 , { 0x3E,0x1D,0x65,0x83,0x25,0xCD,0xFE,0x86,0x48,0xD3,0xC1,0x7B,0x03,0x05,0x87 } },
-+		{ 16 , { 0x0F,0x4A,0x31,0xF5,0x39,0x24,0xB8,0x37,0x0F,0x96,0x51,0xCE,0xC1,0xC1,0xF6,0x4B } },
-+		{ 16 , { 0x3F,0xF5,0xCC,0xC2,0x04,0xFC,0x8C,0xAD,0xD6,0x20,0x76,0x08,0x85,0x63,0x2B,0xD1 } },
-+		{ 16 , { 0x3F,0xC3,0x83,0x8A,0xEA,0xF7,0x89,0x94,0x3E,0xE3,0x93,0x5E,0xEC,0xDF,0x40,0x01 } },
-+		{ 12 , { 0x3B,0x1C,0x23,0x40,0xF6,0xD5,0x01,0xF6,0x2A,0x93,0xE4,0x1D } },
-+		{ 8 , { 0x0F,0x0F,0x83,0xE8,0x76,0x50,0x92,0xFA } },
-+		{ 16 , { 0x37,0x82,0x47,0x45,0x7E,0xE2,0x0F,0x32,0x49,0xCD,0x37,0x38,0x2B,0x4B,0x9A,0x8A } },
-+		{ 12 , { 0x43,0x05,0xC8,0x40,0x0F,0x02,0xE3,0x6D,0x30,0x61,0xF1,0x98 } },
-+		{ 16 , { 0x37,0x91,0x37,0xCB,0x68,0x81,0x9A,0xA8,0x61,0xCE,0xBF,0x67,0xC2,0x06,0xE8,0x09 } },
-+		{ 16 , { 0x37,0x12,0xA4,0x7A,0xE4,0x73,0x20,0x90,0xAA,0x78,0x49,0xD0,0xD9,0xE1,0x18,0x47 } },
-+		{ 16 , { 0x3F,0x52,0x80,0x43,0x40,0x41,0x19,0xFA,0xE5,0x06,0x64,0x39,0x94,0x2A,0xB1,0xA4 } },
-+		{ 16 , { 0x37,0xB5,0xDD,0x62,0x66,0x1E,0x0B,0x00,0x0E,0x81,0x73,0x44,0xDB,0xDC,0xC5,0x37 } },
-+		{ 16 , { 0x37,0xF1,0x6B,0x04,0xA6,0xFD,0x2E,0xD3,0x03,0x6B,0x8E,0xAA,0x9F,0x76,0xC5,0xA4 } },
-+		{ 16 , { 0x3F,0x0E,0xAA,0x91,0x72,0xC3,0xFC,0xCD,0x1B,0xD2,0xA3,0x74,0x29,0xF8,0x3F,0xE3 } },
-+		{ 16 , { 0x37,0x24,0xD1,0x29,0xAF,0x44,0xB2,0x93,0x93,0x91,0x69,0xC9,0xE3,0x9D,0x56,0x93 } },
-+		{ 16 , { 0x37,0x2F,0x93,0xAC,0x2F,0x95,0x12,0x32,0x7E,0x48,0x21,0xC5,0xE1,0xBC,0xA7,0xAD } },
-+		{ 9 , { 0x38,0x9C,0xD0,0x3C,0x03,0x8B,0x7E,0x43,0x07 } },
-+		{ 16 , { 0x07,0xC3,0xE2,0x9B,0x18,0x67,0x79,0xE0,0x0F,0xEF,0x99,0xF4,0x9C,0xF2,0xFE,0xF7 } },
-+		{ 8 , { 0x0F,0x52,0xB4,0x2B,0xEA,0xDE,0x46,0xCE } },
-+		{ 9 , { 0x30,0x3B,0x55,0x5E,0x2C,0x34,0x56,0xD4,0x0C } },
-+		{ 8 , { 0x07,0xC7,0x87,0xE0,0x46,0x48,0xD1,0x1B } },
-+		{ 15 , { 0x36,0xDD,0x84,0xBA,0x2B,0x8C,0x84,0x56,0xA1,0x62,0x14,0x49,0x06,0xDA,0x5F } },
-+		{ 8 , { 0x0F,0xB6,0x5B,0xF3,0x92,0xFC,0x8D,0xAA } },
-+		{ 11 , { 0x3A,0xC6,0xAD,0x54,0x97,0x23,0x5A,0x03,0x17,0xDD,0x64 } },
-+		{ 12 , { 0x07,0xB2,0x2B,0x95,0x16,0x06,0x37,0xB1,0x4B,0xFA,0x31,0x04 } },
-+		{ 8 , { 0x07,0xF0,0x84,0xFA,0x66,0xED,0x51,0xCD } },
-+		{ 16 , { 0x3F,0xDF,0x05,0x91,0xCC,0xE7,0x9D,0x26,0x0F,0x01,0xA9,0x2F,0x1B,0xB8,0x0A,0xBB } },
-+		{ 16 , { 0x3F,0xF1,0x49,0xCE,0x04,0x53,0xA9,0x9F,0xA1,0xAC,0x0E,0x58,0x01,0x7C,0x67,0x35 } },
-+		{ 10 , { 0x49,0x4C,0x0F,0x9C,0xB0,0xCD,0x55,0xD9,0xF6,0x70 } },
-+		{ 16 , { 0x3F,0xDE,0x13,0xB5,0x3B,0xDE,0x4E,0x47,0x0B,0x5F,0xB4,0x18,0x04,0xDE,0xE0,0xD2 } },
-+		{ 14 , { 0x3D,0x85,0x5E,0xE1,0x71,0x69,0xCD,0x41,0xF0,0x5B,0x96,0xD4,0x29,0x72 } },
-+		{ 8 , { 0x07,0x8E,0xCC,0xDB,0xD8,0x27,0x78,0x0B } },
-+		{ 16 , { 0x37,0x38,0x08,0x9E,0xC7,0xE3,0x95,0xF2,0xCD,0x5D,0xCA,0xC9,0x47,0xBB,0xE0,0x04 } },
-+		{ 14 , { 0x4D,0x11,0x72,0x0F,0x5E,0x1D,0x07,0xAD,0x6B,0x91,0x10,0x83,0x73,0xF5 } },
-+		{ 16 , { 0x3F,0x12,0x72,0xA8,0x60,0x89,0xA3,0xB0,0xED,0xBE,0x1D,0x50,0x40,0x53,0x68,0x05 } },
-+		{ 10 , { 0x49,0x23,0x07,0x4B,0xB2,0x11,0x36,0x62,0xDB,0x95 } },
-+		{ 12 , { 0x3B,0x5D,0xBD,0xB1,0xEC,0x89,0x9C,0x14,0x04,0xA7,0xCF,0x91 } },
-+		{ 8 , { 0x07,0xF6,0xB7,0xC4,0xF5,0xDB,0xD6,0x63 } },
-+		{ 11 , { 0x32,0x85,0x4A,0x56,0x1E,0x4B,0xAA,0xC6,0xD3,0xC8,0xED } },
-+		{ 8 , { 0x0F,0x06,0x72,0x2F,0x17,0xE1,0xCA,0x13 } },
-+		{ 16 , { 0x37,0x52,0x65,0xC2,0xC7,0xFB,0x89,0xFF,0xC0,0x3F,0xFC,0x71,0x9D,0x25,0x78,0xA0 } },
-+		{ 11 , { 0x42,0xF2,0x84,0x0F,0x27,0x44,0x0C,0x66,0x46,0xDA,0x5C } },
-+		{ 16 , { 0x37,0x22,0x51,0x61,0x14,0x17,0xBF,0x7F,0x9F,0x66,0x66,0x5E,0xA9,0xDC,0x8D,0xDB } },
-+		{ 16 , { 0x3F,0xFE,0xE5,0x71,0x5C,0x57,0xE1,0x45,0x8C,0xBF,0x9B,0x64,0xA3,0xFB,0xF8,0x70 } },
-+		{ 16 , { 0x37,0x3C,0x21,0x70,0x1E,0xB8,0x7F,0x67,0x87,0xB7,0xAF,0x60,0xB8,0xC3,0x90,0xAE } },
-+		{ 12 , { 0x43,0xC1,0x59,0xF0,0x0F,0x1B,0x98,0x95,0x23,0x1F,0x78,0xF8 } },
-+		{ 16 , { 0x07,0xC4,0x9F,0x90,0x47,0x00,0x75,0xAB,0x07,0x98,0xD5,0xE6,0xCE,0x04,0x38,0x1E } },
-+		{ 13 , { 0x0F,0xD5,0x47,0x57,0xDC,0xE1,0xE1,0xFF,0x4C,0x51,0xFC,0xD4,0x87 } },
-+		{ 8 , { 0x0F,0xCE,0x8A,0x5C,0xFA,0xDD,0x0E,0x91 } },
-+		{ 16 , { 0x3F,0x0C,0xE7,0x71,0x60,0x3E,0x73,0x63,0x7C,0x5C,0xD0,0x7C,0xB0,0xD3,0x12,0x07 } },
-+		{ 16 , { 0x3F,0x48,0xB6,0x42,0x9D,0xA2,0x2E,0x0F,0x84,0xA6,0x63,0xCF,0x3D,0xBA,0x70,0xBA } },
-+		{ 13 , { 0x44,0x4B,0x8D,0xBB,0x82,0x07,0xED,0xB2,0xDB,0x83,0x50,0xEC,0xB9 } },
-+		{ 16 , { 0x47,0x58,0x73,0xE5,0x80,0x68,0x3A,0x05,0x0F,0x4F,0x8C,0xCB,0xB0,0x41,0x9D,0x55 } },
-+		{ 9 , { 0x38,0xDE,0x4B,0x78,0xD8,0x07,0x9F,0x91,0xA7 } },
-+		{ 16 , { 0x0F,0xDD,0x11,0xF5,0xEA,0xCB,0x86,0x31,0x0F,0xBB,0xE2,0x90,0x54,0x2A,0xF5,0x72 } },
-+		{ 16 , { 0x07,0x16,0x1A,0x60,0xFE,0x8D,0xBB,0xEE,0x0F,0x82,0xCD,0x90,0xE1,0x7E,0x7A,0x66 } },
-+		{ 16 , { 0x4F,0x1E,0xBB,0xA1,0xAB,0x6E,0xA9,0x6E,0x0F,0x57,0xCD,0x9B,0x84,0x4C,0x79,0xBA } },
-+		{ 8 , { 0x07,0xFA,0xD6,0x7D,0xA2,0x3A,0x39,0x5D } },
-+		{ 16 , { 0x3F,0xB8,0x9E,0xD7,0x7A,0xEA,0x9E,0x94,0xC3,0x09,0x07,0x81,0x77,0xB0,0xFB,0xBC } },
-+		{ 16 , { 0x37,0x08,0x37,0x2A,0x6F,0xBE,0x2D,0x2D,0x27,0x41,0x41,0x23,0xAA,0x33,0xE4,0x22 } },
-+		{ 14 , { 0x3D,0x82,0x43,0x9B,0xCA,0x91,0x6C,0x3E,0xBD,0x6E,0xDF,0x30,0x4B,0x30 } },
-+		{ 8 , { 0x07,0xDB,0x20,0xD6,0xF6,0x82,0x22,0x6A } },
-+		{ 10 , { 0x39,0x8B,0x3F,0x89,0xD8,0x3A,0x93,0x6B,0x9E,0xC7 } },
-+		{ 11 , { 0x0F,0xB8,0x7C,0xB1,0x17,0xBD,0x12,0xE4,0x42,0xEF,0xFF } },
-+		{ 16 , { 0x0F,0x60,0x65,0x98,0x8B,0xA1,0x3F,0x68,0x07,0x6F,0x7D,0xB5,0x1F,0x50,0xE4,0x8C } },
-+		{ 16 , { 0x3F,0x1A,0x52,0x7B,0x5A,0x8C,0x21,0x96,0xBE,0xEC,0x41,0xCA,0x41,0x4D,0xB3,0x40 } },
-+		{ 15 , { 0x36,0x19,0xEA,0x24,0x82,0x68,0xF4,0x94,0xD9,0x32,0x88,0x08,0x80,0xD8,0xA8 } },
-+		{ 15 , { 0x0F,0xC2,0xA8,0x88,0x1A,0x13,0xE9,0x71,0x4E,0xC9,0x44,0x2B,0xF7,0xA7,0xC2 } },
-+		{ 8 , { 0x07,0xDF,0x40,0x91,0x36,0x50,0x67,0x54 } },
-+		{ 16 , { 0x3F,0xFC,0x1A,0x13,0xB3,0xC5,0x79,0xE2,0x3C,0x41,0x25,0x51,0x11,0x22,0xE1,0x8E } },
-+		{ 10 , { 0x49,0xEB,0x07,0x52,0x3D,0x83,0x21,0xE1,0xC6,0xC3 } },
-+		{ 16 , { 0x37,0x38,0x99,0xD0,0x79,0xBE,0x79,0x36,0x35,0x74,0x36,0x2C,0x35,0x8F,0x68,0x95 } },
-+		{ 16 , { 0x37,0xB9,0x7E,0x02,0x7D,0xA8,0xD5,0xF7,0x88,0x78,0x5D,0x84,0x12,0x6C,0x61,0x79 } },
-+		{ 14 , { 0x3D,0xEE,0x31,0xFB,0x94,0x3E,0x12,0xF2,0x48,0x69,0x0B,0x45,0xD0,0xF2 } },
-+		{ 8 , { 0x07,0x58,0x12,0x06,0xA9,0x9C,0x4E,0xB8 } },
-+		{ 16 , { 0x3F,0x43,0x49,0x56,0x87,0x35,0x32,0xD9,0xD7,0xF8,0x6A,0x4D,0xD5,0x0D,0xAB,0x41 } },
-+		{ 8 , { 0x07,0xF2,0x3E,0x03,0x8A,0xCD,0x9A,0x33 } },
-+		{ 16 , { 0x37,0x2F,0x03,0x02,0xBA,0x6A,0x1D,0xBB,0x04,0x41,0x9A,0x2D,0xFC,0x3D,0x2E,0x8B } },
-+		{ 11 , { 0x32,0xA9,0x46,0xBA,0x15,0xEB,0x89,0xD9,0x31,0xD9,0x3B } },
-+		{ 11 , { 0x0F,0xC1,0xBA,0x17,0x15,0xD7,0x5D,0xF2,0x4A,0xF0,0x9A } },
-+		{ 16 , { 0x0F,0xD6,0x67,0x39,0x57,0xFA,0xA9,0xF4,0x07,0xAA,0x67,0x94,0x43,0x80,0x9F,0x92 } },
-+		{ 15 , { 0x3E,0xF1,0xD0,0x74,0xAB,0x8C,0x65,0x3C,0x6B,0x9D,0x52,0x4A,0x32,0x85,0xE2 } },
-+		{ 13 , { 0x0F,0xEC,0x54,0xAB,0x98,0xB4,0xC3,0x60,0x44,0xB1,0x0A,0xFF,0xCC } },
-+		{ 8 , { 0x0F,0x06,0x90,0x91,0x8F,0xE6,0xB9,0xB0 } },
-+		{ 16 , { 0x37,0xFE,0x8D,0xDC,0xF0,0xEE,0x13,0xCE,0x52,0xF0,0xCF,0x8E,0xC1,0x0F,0x50,0x53 } },
-+		{ 16 , { 0x3F,0xDA,0xA8,0xA3,0x0E,0xB0,0xD1,0xF9,0x5B,0x84,0xF3,0xA9,0xF4,0x53,0x30,0x9F } },
-+		{ 16 , { 0x37,0xD1,0x96,0xCE,0x04,0xB2,0x00,0xB3,0xED,0x9D,0x0B,0xF6,0xC5,0x0C,0x8D,0x11 } },
-+		{ 13 , { 0x4C,0x3E,0x02,0x0A,0xD3,0x0F,0xF4,0x07,0x05,0x8C,0xB2,0x35,0x58 } },
-+		{ 8 , { 0x07,0xA8,0xF2,0xC2,0x8D,0x4E,0x09,0x17 } },
-+		{ 16 , { 0x3F,0xB8,0xF0,0x39,0x43,0x6B,0x99,0x0E,0xF9,0xB5,0x8B,0x4B,0xAB,0xF4,0x89,0x9B } },
-+		{ 15 , { 0x46,0xDC,0x23,0x96,0xFF,0xDA,0x67,0x07,0x43,0x32,0x86,0x98,0xF4,0x16,0xD8 } },
-+		{ 16 , { 0x37,0x7E,0x89,0xCC,0x0A,0x11,0x5C,0x15,0x44,0xE0,0x7F,0x07,0xD2,0x84,0xD0,0x89 } },
-+		{ 8 , { 0x07,0x58,0x0B,0xFB,0x86,0x8A,0x15,0x5B } },
-+		{ 16 , { 0x37,0xE8,0xC7,0xA5,0xFB,0xCA,0x15,0xA3,0x73,0x21,0x48,0xA5,0x01,0xF8,0x02,0x6D } },
-+		{ 16 , { 0x47,0x90,0xAD,0xAB,0x23,0x9F,0x1C,0xD1,0x07,0xA5,0x2D,0xDA,0x7D,0xD8,0x1A,0x93 } },
-+		{ 16 , { 0x3F,0x6C,0x78,0xD0,0x93,0x51,0x32,0x13,0xF5,0x31,0x5B,0x81,0x0A,0xC9,0x7D,0x78 } },
-+		{ 8 , { 0x07,0x1E,0x5E,0xCA,0x94,0xD5,0xAC,0x36 } },
-+		{ 16 , { 0x37,0x81,0x62,0x6E,0xF0,0x57,0x7B,0xBD,0xA1,0xC6,0x27,0x43,0xFA,0x94,0x60,0x51 } },
-+		{ 14 , { 0x45,0xC2,0x9B,0xC0,0x3B,0xC3,0x0F,0xAD,0x27,0x05,0x30,0x42,0x8B,0xB5 } },
-+		{ 16 , { 0x37,0x41,0xB3,0x68,0x5D,0x45,0x9D,0xF6,0x1B,0xA0,0xA8,0xF8,0xE0,0x3C,0x3B,0xE2 } },
-+		{ 16 , { 0x4F,0x3B,0xC5,0xDD,0x66,0x4E,0x34,0x4D,0x07,0x1B,0xB7,0xB7,0x91,0x0A,0x16,0x02 } },
-+		{ 8 , { 0x07,0x4E,0xCA,0xA6,0xC9,0xBB,0xED,0x13 } },
-+		{ 14 , { 0x35,0x6B,0x54,0x76,0xAF,0xAE,0x99,0x31,0x50,0xA1,0xF6,0xCD,0xD8,0x09 } },
-+		{ 8 , { 0x07,0x0B,0x8E,0x8D,0x4E,0x76,0x43,0xC3 } },
-+		{ 9 , { 0x38,0xA0,0xDC,0x85,0x10,0x36,0xAF,0x08,0xCF } },
-+		{ 16 , { 0x0F,0x2C,0xE0,0x87,0x76,0xF5,0x35,0xE6,0x07,0x36,0x11,0xD5,0x54,0xDE,0x1B,0x5F } },
-+		{ 8 , { 0x07,0xFD,0xE5,0x38,0x62,0xEB,0x5B,0x3A } },
-+		{ 12 , { 0x3B,0x8D,0x13,0x42,0xDA,0x9C,0xF7,0x44,0xFA,0xF2,0x36,0x63 } },
-+		{ 12 , { 0x07,0x81,0x52,0xA9,0x09,0x16,0x1C,0x59,0x43,0xA2,0x94,0x52 } },
-+		{ 8 , { 0x0F,0x03,0x28,0x69,0x47,0xFD,0x3D,0x02 } },
-+		{ 16 , { 0x3F,0xE6,0x7D,0x07,0x0B,0xF0,0xAA,0xB6,0xCA,0x0D,0x18,0x55,0x53,0xA0,0x56,0x56 } },
-+		{ 13 , { 0x3C,0x65,0x7D,0xC0,0x23,0x85,0xDD,0x21,0x69,0x7B,0xFF,0x44,0x9E } },
-+		{ 8 , { 0x0F,0xCD,0x81,0x71,0x90,0x1B,0x42,0x2B } },
-+		{ 16 , { 0x3F,0x5E,0x33,0x19,0x91,0xD0,0xA2,0x17,0xA6,0xED,0x02,0x84,0x6F,0x4F,0xC0,0x67 } },
-+		{ 14 , { 0x45,0x60,0x88,0x51,0xD8,0x54,0x07,0xD5,0xD9,0xC3,0x29,0xF0,0x85,0x98 } },
-+		{ 16 , { 0x07,0x11,0xED,0x7E,0x4A,0xB5,0x85,0x55,0x0F,0xBA,0xCA,0x55,0xBB,0x39,0x2A,0xA6 } },
-+		{ 16 , { 0x37,0x11,0x18,0xDE,0x57,0xFE,0x66,0x70,0x2D,0x6C,0x56,0x18,0x7F,0x10,0xDF,0xB6 } },
-+		{ 10 , { 0x39,0xF8,0x7F,0x56,0xE2,0x3A,0x7B,0x55,0x6A,0xEC } },
-+		{ 8 , { 0x0F,0x0E,0xAD,0x4D,0x8E,0x00,0x06,0xCB } },
-+		{ 16 , { 0x37,0xAE,0x90,0xE3,0x86,0xA5,0x5C,0x0F,0x2E,0x20,0x78,0x90,0xED,0x54,0x1F,0x18 } },
-+		{ 15 , { 0x3E,0x61,0x60,0x83,0x21,0xBE,0xCF,0x2E,0x04,0x91,0x4F,0xB4,0xE3,0x60,0xF3 } },
-+		{ 16 , { 0x0F,0xA6,0x1F,0x08,0x4F,0x81,0x29,0xEC,0x0F,0x18,0x70,0x0D,0x34,0xE9,0x73,0x64 } },
-+		{ 8 , { 0x0F,0x79,0x96,0x0D,0x78,0xB1,0x0A,0x32 } },
-+		{ 16 , { 0x37,0x27,0xB5,0x9E,0xEC,0xCD,0xA0,0xD5,0x36,0x15,0xB1,0x77,0x3A,0x71,0x15,0x70 } },
-+		{ 15 , { 0x36,0xDA,0xD0,0xF9,0xF8,0xB3,0x39,0x6B,0x2D,0xC4,0xD5,0x4B,0xCC,0xAD,0x27 } },
-+		{ 16 , { 0x07,0xF0,0x92,0x1C,0x74,0x87,0xB9,0x1E,0x07,0xB0,0x9F,0xB5,0x42,0xC6,0x8E,0x0E } },
-+		{ 12 , { 0x33,0xBE,0x5E,0x78,0xB1,0x9A,0xD7,0xBE,0x8D,0x8E,0x47,0x8E } },
-+		{ 16 , { 0x0F,0xD1,0x61,0x6F,0x32,0x27,0x55,0xB0,0x47,0x84,0xDB,0xF3,0x19,0xD7,0xCF,0xA0 } },
-+		{ 16 , { 0x0F,0x4C,0x5E,0xC6,0xAB,0x62,0xB9,0x1C,0x07,0x23,0xA4,0x04,0xBB,0xB7,0xE8,0x3E } },
-+		{ 16 , { 0x07,0xB9,0x1D,0xEC,0xDA,0x51,0x7C,0xEE,0x07,0xEF,0x36,0x6F,0x99,0xA7,0x60,0xEE } },
-+		{ 10 , { 0x31,0xF1,0xA1,0xB0,0x7E,0xF4,0xF0,0xFB,0xD7,0x03 } },
-+		{ 11 , { 0x07,0xA5,0xD3,0x30,0x8B,0x9E,0x18,0xCA,0x4A,0xFE,0xF8 } },
-+		{ 8 , { 0x0F,0x3C,0x2C,0x93,0xDE,0xDD,0x4D,0x7D } },
-+		{ 10 , { 0x31,0x3D,0x04,0x75,0x1D,0xD7,0x88,0xCF,0x79,0x47 } },
-+		{ 14 , { 0x07,0xB0,0x2F,0x40,0xB4,0xBB,0xCD,0xF8,0x45,0x04,0x36,0xAE,0xDD,0x1E } },
-+		{ 12 , { 0x07,0x20,0x97,0x04,0xCB,0xCD,0x75,0xF6,0x4B,0xF0,0x67,0xFD } },
-+		{ 8 , { 0x07,0x63,0x8D,0x9E,0xA6,0x73,0x6C,0x66 } },
-+		{ 16 , { 0x37,0xDD,0xEE,0x63,0xFB,0x69,0xD9,0x97,0x29,0xCD,0x9C,0x28,0xCB,0xF5,0x84,0x14 } },
-+		{ 14 , { 0x4D,0x6E,0xC5,0x07,0xD3,0xF9,0x07,0x93,0xD9,0xC3,0xA8,0x73,0xCE,0x2D } },
-+		{ 16 , { 0x0F,0x50,0xA5,0x8D,0xA4,0x37,0x28,0x5F,0x0F,0x52,0xCD,0xA7,0xDC,0xD4,0x65,0xE2 } },
-+		{ 15 , { 0x4E,0x8C,0xEF,0x15,0x9C,0xBF,0x86,0x07,0x2E,0x1F,0x32,0xA7,0x2F,0x6B,0x57 } },
-+		{ 16 , { 0x0F,0x91,0x68,0xD0,0x0B,0x9C,0xD5,0xE4,0x0F,0xFF,0x25,0x1C,0x00,0xF7,0xAB,0xFD } },
-+		{ 16 , { 0x3F,0x13,0x90,0x4A,0x31,0xAA,0x30,0xFD,0x23,0x42,0x47,0x48,0x93,0x6A,0x67,0xE1 } },
-+		{ 16 , { 0x37,0x18,0x15,0x7E,0xC8,0x54,0xB6,0x4E,0x2A,0xC6,0x5E,0x7B,0x10,0x33,0x6E,0x4A } },
-+		{ 16 , { 0x3F,0x1F,0x68,0xD6,0xE9,0xC4,0x67,0x0A,0x85,0x73,0x8F,0x2C,0xED,0xBF,0x28,0x05 } },
-+		{ 10 , { 0x49,0xC3,0x07,0x50,0x3B,0x78,0xBE,0x7A,0xEC,0x55 } },
-+		{ 16 , { 0x37,0xA6,0x01,0x77,0x03,0x70,0xA6,0xAF,0x1D,0x20,0x64,0xB5,0xD1,0x65,0xAA,0xAF } },
-+		{ 12 , { 0x3B,0x66,0x4A,0x9E,0x1C,0x9B,0xBF,0xC2,0xBD,0xE1,0x2D,0xC8 } },
-+		{ 8 , { 0x07,0xE8,0xD1,0x66,0x37,0x01,0x14,0xB8 } },
-+		{ 9 , { 0x30,0xA6,0xD6,0xD4,0x63,0x39,0x57,0x59,0x07 } },
-+		{ 16 , { 0x0F,0xDF,0x1B,0xDB,0xE2,0xBA,0x2B,0x24,0x0F,0x7B,0xBB,0x49,0x89,0xC8,0x66,0x1F } },
-+		{ 8 , { 0x07,0x9E,0x4E,0x3E,0x1A,0x84,0xC2,0x54 } },
-+		{ 16 , { 0x37,0xD7,0x37,0x60,0x62,0xC9,0x78,0x31,0x90,0xC7,0xA2,0x94,0xF0,0x52,0xC4,0xF9 } },
-+		{ 16 , { 0x3F,0x05,0x4D,0xE0,0xE2,0x40,0xA7,0x92,0x03,0x1C,0xB0,0x0B,0xED,0xFF,0x7D,0xE9 } },
-+		{ 10 , { 0x39,0xDE,0xA0,0x71,0x01,0x82,0xA7,0x55,0x2A,0x84 } },
-+		{ 8 , { 0x0F,0x15,0x60,0xBF,0xAE,0x55,0xDF,0xE3 } },
-+		{ 16 , { 0x3F,0x75,0xB1,0x9F,0x82,0x1A,0x65,0x0D,0x59,0x65,0x2F,0x10,0x51,0xA8,0x95,0x7D } },
-+		{ 10 , { 0x41,0xD2,0x0F,0x44,0x8F,0x80,0x6C,0xF0,0x4B,0x43 } },
-+		{ 12 , { 0x0F,0x28,0x34,0xC5,0x8D,0x81,0xD1,0xBE,0x43,0x77,0x0A,0x5D } },
-+		{ 8 , { 0x07,0xD9,0xBA,0x5C,0xE1,0xD0,0x70,0x8E } },
-+		{ 16 , { 0x3F,0x93,0xDC,0x98,0x4F,0x52,0xBC,0x9E,0x11,0x1A,0x45,0x53,0x67,0xE4,0x49,0x3F } },
-+		{ 13 , { 0x4C,0xA0,0xA1,0x4B,0xD1,0x07,0x25,0x20,0xC2,0x6E,0x39,0x89,0x4C } },
-+		{ 16 , { 0x07,0x87,0x44,0xBF,0x88,0x9A,0x36,0x6D,0x07,0xB4,0x0A,0x8E,0xAD,0x38,0x07,0xA2 } },
-+		{ 15 , { 0x4E,0x41,0x05,0xA4,0x52,0x84,0x93,0x07,0x50,0xDD,0x56,0x01,0x5A,0x8B,0xAE } },
-+		{ 16 , { 0x3F,0x5F,0x20,0xA9,0xC3,0x5E,0x96,0xE1,0xAD,0x1F,0x47,0x05,0x73,0xBA,0x67,0x30 } },
-+		{ 16 , { 0x3F,0x8B,0x9C,0x55,0x2E,0x6A,0x7F,0x88,0x87,0x61,0xDA,0x61,0x85,0xE1,0x6D,0xD4 } },
-+		{ 16 , { 0x3F,0xA1,0x4B,0xD7,0x69,0xD3,0xF0,0xB5,0x84,0x23,0xFF,0x2E,0x75,0x1C,0x3D,0x29 } },
-+		{ 9 , { 0x30,0x39,0x00,0xC9,0xFA,0x81,0x8D,0xEC,0x39 } },
-+		{ 8 , { 0x0F,0x2E,0x6E,0x74,0x4A,0x61,0xCF,0x65 } },
-+		{ 16 , { 0x3F,0x47,0x90,0xE3,0x6B,0x9D,0x69,0x94,0xF6,0x41,0x74,0xD4,0xA8,0x6E,0xFF,0x1A } },
-+		{ 11 , { 0x3A,0x51,0xCA,0xC7,0xFB,0x0F,0x80,0x84,0x69,0xA5,0x77 } },
-+		{ 16 , { 0x0F,0x02,0x65,0xA8,0x3C,0x56,0x34,0x5A,0x07,0x1D,0xFB,0xB0,0x28,0x1C,0xF2,0x46 } },
-+		{ 14 , { 0x45,0x3E,0x3B,0xCD,0xB4,0x0D,0x07,0x19,0x55,0x8D,0x5C,0x47,0x5C,0xEE } },
-+		{ 12 , { 0x43,0x40,0x9A,0xA5,0x0F,0x85,0x9F,0x44,0xD6,0x13,0x96,0x52 } },
-+		{ 16 , { 0x3F,0x4A,0x42,0x0D,0xEA,0x94,0x6F,0xF2,0x71,0xE0,0xF4,0xCE,0xE8,0x06,0xB9,0x70 } },
-+		{ 16 , { 0x37,0x42,0x01,0x45,0xFB,0x15,0x97,0xB9,0xDB,0x1D,0x6F,0x85,0x2E,0xCF,0xFB,0x46 } },
-+		{ 16 , { 0x3F,0xB0,0x3F,0x54,0xAE,0x7B,0xD1,0xCB,0xB9,0xE3,0x61,0x66,0x45,0xAD,0x8A,0xD4 } },
-+		{ 13 , { 0x44,0x77,0x86,0x5D,0x20,0x07,0x55,0xD0,0xB1,0xE4,0x79,0x66,0xC5 } },
-+		{ 8 , { 0x07,0x97,0xBB,0x36,0xC6,0xCA,0x63,0x7B } },
-+		{ 14 , { 0x35,0xFE,0x06,0x3A,0xB5,0x7A,0x96,0x81,0x71,0x20,0xB7,0x92,0x02,0xA4 } },
-+		{ 8 , { 0x07,0x4C,0xED,0x96,0x46,0x61,0xEE,0x30 } },
-+		{ 16 , { 0x3F,0xFF,0x0D,0x10,0xE7,0x39,0x25,0xC2,0xCA,0xBC,0x8B,0x3D,0x5A,0x44,0xA4,0xF8 } },
-+		{ 15 , { 0x46,0xEB,0xAA,0x98,0xE9,0x2C,0xBD,0x07,0x01,0x63,0x82,0x19,0x65,0x31,0x84 } },
-+		{ 16 , { 0x3F,0x58,0xFA,0x1E,0x5D,0x4E,0x9A,0xCF,0x1C,0x51,0x7B,0xE2,0x8D,0xE6,0xA2,0x10 } },
-+		{ 16 , { 0x37,0x94,0x7B,0x52,0x03,0xC5,0x18,0x86,0xB6,0xD1,0x44,0x3B,0xBD,0x69,0xDC,0x21 } },
-+		{ 16 , { 0x3F,0xB9,0x57,0xEA,0xA5,0x13,0xBE,0x6B,0xF3,0x0A,0x54,0x85,0x8D,0x77,0x44,0x69 } },
-+		{ 16 , { 0x37,0x29,0xB7,0xE1,0xAD,0xC0,0x47,0x53,0xB2,0x3F,0x10,0x9E,0xDC,0x70,0x71,0x22 } },
-+		{ 16 , { 0x3F,0x14,0xCA,0x0D,0x42,0x9B,0x02,0x25,0xD5,0x43,0xBD,0xB4,0xB4,0xF4,0x0E,0x8A } },
-+		{ 14 , { 0x4D,0xE6,0xF8,0xC8,0x36,0x22,0x07,0x67,0xC0,0x28,0x4F,0xB4,0xF0,0xBF } },
-+		{ 13 , { 0x44,0xB0,0x86,0x2E,0x98,0x07,0x5A,0x2B,0x23,0x14,0x75,0x08,0x85 } },
-+		{ 12 , { 0x4B,0x37,0x90,0x92,0x0F,0x69,0x7F,0x43,0xE5,0x5E,0x1D,0xBA } },
-+		{ 16 , { 0x37,0x6F,0xED,0x83,0x81,0x1B,0x11,0x4C,0x27,0x82,0x22,0x32,0x74,0xCB,0xBF,0xB4 } },
-+		{ 16 , { 0x37,0x8E,0xFC,0xDC,0x2D,0x93,0xA8,0x19,0x58,0x86,0x3B,0x74,0xB0,0xB7,0x79,0x5C } },
-+		{ 16 , { 0x47,0x0E,0xA6,0xEF,0xBF,0x9B,0xAF,0x73,0x07,0xAB,0xDE,0xF0,0x70,0x07,0xBA,0xCB } },
-+		{ 11 , { 0x4A,0x43,0xCC,0x07,0x69,0x9B,0xED,0x59,0x5C,0x91,0xED } },
-+		{ 9 , { 0x30,0xEB,0xA0,0xA2,0x75,0xD2,0x2B,0xA3,0x52 } },
-+		{ 16 , { 0x07,0xF3,0xB4,0xA9,0x75,0x4C,0x97,0xC6,0x07,0x33,0x44,0x76,0x7A,0xD1,0xF2,0x4E } },
-+		{ 16 , { 0x07,0x65,0x1C,0xAB,0xE1,0x9E,0x83,0xCC,0x0F,0x77,0x0B,0xB9,0x11,0x65,0x59,0x4A } },
-+		{ 15 , { 0x0F,0x45,0xDD,0xE8,0x58,0x2B,0x7B,0xB0,0x46,0x55,0x36,0x83,0x02,0xC7,0xED } },
-+		{ 16 , { 0x0F,0x8F,0xB9,0x0D,0xB4,0xA1,0x23,0x21,0x0F,0x35,0x51,0x00,0xD1,0xC9,0x1C,0x59 } },
-+		{ 13 , { 0x3C,0x89,0x2D,0x0D,0x45,0x36,0x2F,0x46,0x28,0xDC,0x43,0x95,0xE1 } },
-+		{ 8 , { 0x0F,0x77,0x09,0x07,0x56,0xBC,0x50,0xD4 } },
-+		{ 16 , { 0x37,0x9C,0x70,0x02,0xEE,0x41,0xB2,0x36,0xA7,0x99,0x6E,0x5E,0xAD,0xAB,0x1B,0x01 } },
-+		{ 16 , { 0x3F,0x8A,0xA8,0xBD,0x6E,0x6A,0x74,0x37,0xF7,0x2A,0x89,0x47,0x91,0x75,0x4C,0xFB } },
-+		{ 14 , { 0x45,0xE5,0x74,0xB2,0xBB,0x6E,0x0F,0x3B,0xC4,0x2E,0x57,0xDA,0x90,0x9B } },
-+		{ 12 , { 0x3B,0xD1,0xB0,0xFC,0x79,0xBD,0xF5,0xB8,0xA4,0x63,0x37,0x97 } },
-+		{ 16 , { 0x0F,0x54,0xEA,0x19,0x33,0x1F,0x43,0x1E,0x0F,0xE7,0x32,0x43,0xAE,0x27,0xFB,0xD2 } },
-+		{ 8 , { 0x0F,0x3A,0x48,0x55,0x48,0x5A,0x16,0x0E } },
-+		{ 11 , { 0x3A,0xBF,0xA9,0x8D,0x02,0x34,0x58,0x6D,0xE0,0x89,0x6A } },
-+		{ 8 , { 0x0F,0x84,0xDF,0xCA,0xFD,0x33,0x0C,0xFF } },
-+		{ 12 , { 0x3B,0x6D,0x30,0x86,0x93,0x33,0x8B,0xBD,0x86,0xFE,0x86,0xDB } },
-+		{ 8 , { 0x07,0x98,0x0C,0x52,0x0F,0xC3,0x23,0x6A } },
-+		{ 10 , { 0x39,0x89,0xF5,0x34,0x03,0xF0,0xAE,0x70,0xA0,0x33 } },
-+		{ 11 , { 0x0F,0x12,0x47,0x09,0x2D,0x0F,0xBC,0xF8,0x42,0x67,0xAE } },
-+		{ 14 , { 0x07,0xED,0x76,0x41,0xC2,0xD3,0x39,0xDE,0x45,0x4F,0x2B,0x2E,0x2C,0x89 } },
-+		{ 14 , { 0x07,0xFB,0xBA,0x30,0xC0,0xDD,0xF5,0x06,0x45,0x10,0x62,0x58,0x63,0xA0 } },
-+		{ 8 , { 0x07,0xED,0xA3,0x2A,0xAE,0x0F,0x91,0xDB } },
-+		{ 16 , { 0x3F,0xB1,0xC1,0xF6,0xEF,0x12,0x9B,0x3E,0x65,0xF7,0x4F,0x21,0x31,0xB8,0x2E,0x23 } },
-+		{ 12 , { 0x3B,0x9C,0xD2,0xE4,0x4C,0xAD,0x3F,0xF1,0x3D,0xF7,0xBD,0x56 } },
-+		{ 12 , { 0x07,0x01,0xEA,0x75,0xF4,0x2A,0xD3,0xC6,0x4B,0xDC,0x4C,0x6A } },
-+		{ 16 , { 0x0F,0xA2,0x38,0xE3,0xBF,0x4E,0x78,0x83,0x0F,0xCC,0x5A,0x4E,0x96,0xB0,0x2E,0xFA } },
-+		{ 8 , { 0x07,0xE8,0x5A,0x55,0x26,0x2C,0xB5,0x1D } },
-+		{ 16 , { 0x3F,0x26,0xEF,0x93,0x95,0x13,0x6A,0x36,0xE3,0x81,0x81,0x9A,0x6C,0x00,0x21,0x60 } },
-+		{ 16 , { 0x3F,0x6D,0xF1,0x70,0x5F,0x19,0xDD,0xB9,0x28,0xB1,0xE8,0x06,0xF1,0x35,0x7F,0x14 } },
-+		{ 16 , { 0x37,0xAE,0x87,0x10,0xD7,0xCF,0x8F,0xD6,0xBF,0x53,0x76,0x3A,0xD4,0x94,0x1A,0xEC } },
-+		{ 16 , { 0x37,0xC5,0x41,0xC5,0x2A,0x32,0x72,0x9A,0x4A,0x62,0x88,0xD3,0x1E,0x58,0xED,0x5A } },
-+		{ 16 , { 0x37,0x41,0x33,0xA6,0xB2,0x4C,0xF2,0x01,0x92,0x14,0xBD,0x7D,0xB2,0x3F,0xEF,0xE1 } },
-+		{ 16 , { 0x3F,0xEC,0x09,0xF1,0x3D,0x09,0xFE,0x0B,0xA9,0xEA,0xAB,0x45,0x72,0xA4,0x1F,0x43 } },
-+		{ 15 , { 0x3E,0x3D,0xD0,0x37,0xBA,0xE9,0xB6,0xDE,0xE4,0xAF,0x22,0x7A,0x18,0x48,0xEE } },
-+		{ 8 , { 0x0F,0x05,0xF1,0x64,0x74,0x28,0x1B,0x93 } },
-+		{ 16 , { 0x37,0x47,0x68,0xA8,0x7F,0x0E,0x0A,0xD4,0x6C,0xC0,0x0D,0xF0,0x82,0x86,0x83,0x1E } },
-+		{ 16 , { 0x37,0xBD,0x51,0x92,0x8E,0xCE,0x04,0x83,0x95,0xBC,0xAB,0x2A,0x2B,0x5D,0x5D,0x85 } },
-+		{ 16 , { 0x3F,0x39,0x1C,0x2C,0x62,0x37,0x74,0xF4,0xBF,0xB1,0x96,0x75,0xBC,0x6B,0x81,0xFD } },
-+		{ 16 , { 0x37,0x24,0xC9,0xFA,0x39,0xD8,0xC1,0x40,0x49,0x78,0x4A,0x0A,0xAB,0x0E,0x6F,0x34 } },
-+		{ 16 , { 0x3F,0xB0,0x13,0xBA,0x55,0x70,0x67,0x51,0x34,0x87,0xA9,0x8C,0x5B,0x4F,0x6A,0x14 } },
-+		{ 16 , { 0x37,0xC9,0x85,0xCD,0xFB,0xF9,0x87,0x68,0x1B,0xB6,0xB6,0xED,0x4A,0x03,0xC5,0xE3 } },
-+		{ 16 , { 0x37,0xA8,0x1D,0xFA,0x88,0xBA,0x0E,0x45,0x98,0x9C,0xCC,0x15,0xCC,0x6C,0x34,0xC6 } },
-+		{ 16 , { 0x37,0x12,0x71,0x87,0x21,0xD8,0x35,0x81,0xFE,0x50,0xEB,0x70,0x9B,0x3D,0x0F,0x24 } },
-+		{ 16 , { 0x37,0x48,0x21,0xC0,0x54,0xEB,0x80,0xBE,0x58,0x2C,0x7A,0xBF,0xE1,0x55,0xAC,0x0A } },
-+		{ 16 , { 0x3F,0xAC,0xE6,0x81,0x16,0xE1,0x94,0x35,0x9E,0x3F,0x44,0x01,0xD9,0x39,0xF6,0x96 } },
-+		{ 16 , { 0x3F,0x87,0x2E,0xC2,0x20,0x44,0x09,0x82,0xD5,0x5A,0xF0,0x5C,0x4F,0x4A,0x24,0xE4 } },
-+		{ 16 , { 0x37,0x58,0x7B,0x6F,0x8C,0xF9,0x84,0x6A,0x60,0xDB,0xB7,0xBB,0x2C,0x13,0xBF,0x2B } },
-+		{ 16 , { 0x37,0xD8,0x21,0x0F,0x40,0x35,0x0E,0x46,0x72,0x27,0x4A,0x4E,0x88,0x8E,0x27,0xF8 } },
-+		{ 10 , { 0x39,0x8C,0x56,0x15,0xF5,0xE2,0xAA,0x99,0x98,0x80 } },
-+		{ 8 , { 0x0F,0x5A,0x04,0xD3,0x73,0x75,0x7D,0x5A } },
-+		{ 14 , { 0x35,0xC7,0x99,0x87,0xBC,0xC8,0x19,0xF8,0xC0,0xFA,0xAD,0x03,0xF7,0xE5 } },
-+		{ 8 , { 0x07,0x7F,0xA5,0xD1,0xCC,0x2F,0xA2,0x83 } },
-+		{ 16 , { 0x3F,0x53,0xD7,0xC5,0xE9,0xD5,0xC2,0x72,0xAC,0x4F,0xF9,0xE1,0x13,0x0E,0x8B,0x76 } },
-+		{ 16 , { 0x3F,0x9C,0xFD,0xFC,0x8B,0x2A,0x8C,0x58,0x20,0xC5,0x4B,0x79,0x5A,0x7A,0xC8,0x35 } },
-+		{ 16 , { 0x37,0x52,0x61,0x5D,0x2C,0x37,0x3C,0x7C,0x27,0x2B,0x56,0x28,0xA4,0x29,0x89,0x0E } },
-+		{ 16 , { 0x3F,0xDE,0x96,0x85,0x21,0x5B,0x42,0x0E,0x23,0xD3,0xBF,0xDC,0x3C,0x36,0x55,0xE5 } },
-+		{ 16 , { 0x3F,0xE6,0x7E,0x72,0x37,0x4E,0x37,0xEB,0x3E,0x80,0xEE,0x8F,0xED,0x4C,0xBE,0xE0 } },
-+		{ 11 , { 0x3A,0xF7,0xAD,0xD0,0x67,0x3F,0xFA,0x83,0xD9,0x46,0xC5 } },
-+		{ 8 , { 0x07,0x41,0xDB,0x56,0x6C,0xEF,0xDF,0xA9 } },
-+		{ 16 , { 0x3F,0x7B,0x59,0xE3,0x57,0x3A,0x43,0x46,0xA3,0xFB,0x1B,0xC4,0xCD,0x40,0x5B,0xBB } },
-+		{ 16 , { 0x3F,0x3D,0x37,0x62,0xE9,0x61,0x90,0x2C,0xAA,0x1C,0x53,0xCD,0x16,0x3D,0xEA,0xE9 } },
-+		{ 16 , { 0x37,0x5E,0xAC,0xDC,0x22,0xD4,0x48,0xE1,0x0E,0x2E,0x46,0xB4,0xFC,0xD7,0x92,0xB9 } },
-+		{ 16 , { 0x37,0x00,0x45,0xE4,0x2C,0x11,0xB7,0x3A,0x79,0x67,0x7F,0x45,0x86,0xB2,0xE5,0xD8 } },
-+		{ 10 , { 0x41,0x4F,0x07,0x91,0x17,0x0B,0xDD,0x28,0xDE,0x9F } },
-+		{ 16 , { 0x3F,0x9B,0x06,0x46,0x87,0xF1,0x83,0x1F,0xDD,0xE4,0x4D,0xD4,0xAB,0x0F,0x51,0x8E } },
-+		{ 16 , { 0x37,0x01,0x73,0x10,0x44,0x79,0xF4,0x00,0x00,0x55,0x5D,0x87,0x88,0xFD,0x11,0x5D } },
-+		{ 11 , { 0x32,0x78,0x0B,0xA8,0x77,0x42,0x2B,0xD6,0xB5,0xFC,0x55 } },
-+		{ 8 , { 0x0F,0x8D,0x29,0x21,0xFD,0x22,0xCA,0xB7 } },
-+		{ 16 , { 0x37,0x08,0x2C,0x76,0xDA,0x2B,0xDC,0x12,0xAB,0xC0,0x94,0xC5,0x1D,0x6D,0x7F,0x0B } },
-+		{ 16 , { 0x37,0xB6,0x4A,0xC6,0xE0,0x36,0xC6,0x51,0x27,0x90,0x3B,0xAA,0xDD,0x85,0x62,0xBC } },
-+		{ 16 , { 0x3F,0xA0,0x29,0x29,0x43,0xB0,0x96,0x14,0xF9,0x6B,0x86,0xBD,0xBD,0xAD,0x99,0x85 } },
-+		{ 16 , { 0x3F,0xB0,0x4F,0x3B,0x70,0x33,0xB4,0x4D,0x51,0xA8,0x61,0xAA,0xDF,0x6F,0xDC,0x4B } },
-+		{ 16 , { 0x37,0x1C,0x91,0x82,0xCC,0xF8,0x51,0x02,0xE3,0x2C,0x29,0x76,0x02,0x2E,0x48,0x3D } },
-+		{ 16 , { 0x4F,0x93,0x5F,0x26,0xA3,0xA8,0x6A,0x4B,0x07,0xEA,0x6C,0x7C,0xED,0x1A,0x18,0x89 } },
-+		{ 13 , { 0x3C,0x35,0xDE,0xE4,0xF2,0x10,0xC7,0x6B,0xF3,0x4A,0x92,0x71,0xFC } },
-+		{ 16 , { 0x07,0xAC,0xD9,0x0E,0xBB,0x10,0xFA,0xF4,0x07,0xB6,0x10,0x48,0x8B,0x75,0x88,0x08 } },
-+		{ 8 , { 0x0F,0x48,0xCC,0x6D,0xC4,0x40,0x1F,0xAD } },
-+		{ 9 , { 0x38,0x46,0x81,0xAD,0x86,0x94,0x7F,0x98,0xFA } },
-+		{ 8 , { 0x07,0x9C,0xEB,0x03,0x7C,0x62,0xB9,0x25 } },
-+		{ 16 , { 0x3F,0x8D,0xC0,0x24,0xF9,0x4E,0xB5,0xE0,0x05,0x37,0xBE,0x8A,0x8A,0xCC,0xE1,0x9B } },
-+		{ 16 , { 0x3F,0xED,0xD6,0x84,0x39,0x2D,0xAD,0xF2,0xD1,0xC9,0x98,0x58,0xD3,0xBB,0x7D,0x4A } },
-+		{ 16 , { 0x47,0x6D,0x97,0x3E,0x93,0xF7,0x16,0xFE,0x07,0x82,0xA5,0xD2,0x9A,0xF0,0x19,0x3C } },
-+		{ 16 , { 0x3F,0x68,0x5C,0x5A,0x3F,0xA7,0xE7,0x42,0xC6,0x2A,0x6C,0x3B,0xE7,0xC7,0x7B,0xE1 } },
-+		{ 11 , { 0x42,0xCB,0x39,0x07,0x59,0x5C,0x8C,0xF3,0xB1,0x46,0x37 } },
-+		{ 16 , { 0x3F,0x3B,0xC2,0x98,0xBD,0x94,0x10,0x15,0xBC,0x76,0xA0,0x98,0x8E,0x6F,0x09,0xEA } },
-+		{ 12 , { 0x4B,0x9E,0x75,0x9C,0x0F,0x2E,0xED,0xEE,0x09,0x3B,0x0F,0xDF } },
-+		{ 16 , { 0x0F,0x70,0x5B,0x7D,0x1A,0x36,0x09,0x14,0x0F,0x18,0xDD,0x9D,0x72,0x99,0x10,0x51 } },
-+		{ 16 , { 0x37,0x46,0x82,0x0C,0xF3,0xF5,0xA7,0x33,0xFD,0xD3,0x54,0xDE,0xC0,0x97,0xEF,0x49 } },
-+		{ 11 , { 0x4A,0x61,0xE7,0x07,0xE6,0x7F,0x70,0xB9,0xC2,0xBC,0x1B } },
-+		{ 16 , { 0x07,0xCC,0x93,0x86,0xE0,0x2B,0x4D,0x3D,0x07,0x23,0x8A,0x2F,0xD7,0x49,0x9A,0x6D } },
-+		{ 8 , { 0x07,0x0A,0xCF,0x3A,0x24,0x67,0x2A,0x63 } },
-+		{ 11 , { 0x3A,0xC2,0xC9,0x06,0x90,0xBD,0x45,0x5D,0xAB,0xFC,0x7C } },
-+		{ 13 , { 0x0F,0x5C,0x63,0xB6,0xE8,0xF8,0x4C,0x03,0x4C,0x13,0xC5,0x44,0x45 } },
-+		{ 16 , { 0x0F,0xB5,0x7F,0xFF,0xF8,0x2C,0xA7,0x7A,0x4F,0xD1,0xAA,0x18,0x7A,0x42,0xE7,0x6A } },
-+		{ 8 , { 0x07,0x56,0xFD,0xCA,0x84,0x27,0x09,0xA0 } },
-+		{ 15 , { 0x36,0x5F,0x77,0x76,0x77,0x10,0xEE,0x1D,0x1B,0x5D,0x32,0xCB,0xC5,0x1F,0x1E } },
-+		{ 15 , { 0x07,0x49,0x7D,0x86,0xE2,0x53,0x2A,0x36,0x46,0xC3,0xC2,0x2D,0xCB,0xBB,0xC4 } },
-+		{ 16 , { 0x0F,0xDC,0x74,0x41,0xCA,0xC6,0x87,0xC5,0x07,0x24,0x52,0x58,0x1B,0x73,0xE3,0xDF } },
-+		{ 15 , { 0x46,0x69,0x5B,0xFF,0x46,0xA8,0xD0,0x07,0xE3,0x46,0x2C,0x1B,0xA6,0x12,0x30 } },
-+		{ 16 , { 0x37,0xD4,0xE0,0xD1,0xDA,0x09,0xE6,0x65,0x3B,0xC6,0x2C,0xA9,0x8A,0x5B,0x59,0xF8 } },
-+		{ 16 , { 0x37,0x6A,0x6D,0x61,0x48,0x58,0x13,0xB1,0x48,0xE9,0xD9,0x0F,0x8E,0x22,0x30,0x9D } },
-+		{ 16 , { 0x37,0x84,0xE6,0x21,0xFD,0x23,0xA9,0x85,0x23,0x52,0x68,0x2C,0xDE,0x07,0x9F,0x06 } },
-+		{ 16 , { 0x37,0xBF,0x16,0xA5,0x7E,0x14,0x45,0xE2,0x20,0xDC,0x77,0x5E,0xF1,0xF8,0xB8,0xB2 } },
-+		{ 16 , { 0x3F,0x0D,0x41,0x9B,0x88,0x55,0x39,0x4A,0x33,0xA9,0x0F,0x26,0x8B,0xFC,0x70,0xAC } },
-+		{ 10 , { 0x41,0x70,0x0F,0x76,0xBD,0x5A,0xED,0x08,0x09,0x04 } },
-+		{ 16 , { 0x0F,0xEA,0x6E,0x20,0xC8,0xD3,0x19,0xA3,0x07,0x60,0x16,0x50,0x6C,0xC9,0x4B,0x6F } },
-+		{ 11 , { 0x32,0x97,0x0F,0x94,0x24,0x6C,0x5F,0x97,0xC2,0xE2,0x55 } },
-+		{ 13 , { 0x0F,0x7C,0x3E,0xA8,0x8C,0xC4,0xF4,0x83,0x44,0x24,0x5A,0x1B,0xF2 } },
-+		{ 8 , { 0x07,0x01,0xC5,0x03,0x17,0x44,0xB9,0x97 } },
-+		{ 16 , { 0x37,0x75,0x9A,0xD9,0x9C,0x26,0x49,0x09,0xDF,0xCB,0x23,0x2E,0xF6,0xBD,0xB3,0x92 } },
-+		{ 11 , { 0x32,0xE5,0xCF,0x57,0x9C,0xF4,0x13,0x27,0xC8,0xD8,0xD9 } },
-+		{ 11 , { 0x0F,0xCE,0xF0,0x4A,0x6C,0xDF,0x4F,0xF5,0x4A,0xB2,0x1D } },
-+		{ 8 , { 0x0F,0x32,0xC1,0x9A,0xAC,0x00,0xB0,0x79 } },
-+		{ 16 , { 0x3F,0xEB,0x6B,0x6A,0x75,0xE5,0x01,0x4A,0x73,0x44,0x54,0x49,0x34,0xA9,0x9A,0x1A } },
-+		{ 16 , { 0x4F,0x7D,0xBE,0x96,0xC1,0x63,0x46,0x61,0x07,0xAC,0x09,0x7D,0x47,0xDC,0x62,0xB3 } },
-+		{ 14 , { 0x35,0x6F,0x4E,0x24,0xCB,0x25,0x62,0xA6,0xAB,0x37,0xE2,0xAC,0xE3,0x13 } },
-+		{ 16 , { 0x07,0x93,0x60,0x60,0xB1,0x8D,0xC6,0xBB,0x07,0x29,0xBC,0x5C,0x13,0x8D,0x39,0xF4 } },
-+		{ 8 , { 0x0F,0xAF,0x57,0xC7,0xB8,0x9E,0x72,0x0F } },
-+		{ 16 , { 0x37,0xF0,0xC3,0x26,0xAA,0x26,0x48,0x7C,0x42,0xCA,0xB8,0x23,0x1B,0xC4,0xE8,0xB3 } },
-+		{ 15 , { 0x46,0x67,0xC8,0xF8,0x0A,0x70,0x94,0x07,0x3C,0xF5,0xC8,0x66,0xE9,0x14,0x0C } },
-+		{ 15 , { 0x36,0xA5,0x8E,0x38,0x1A,0xED,0x60,0x56,0x31,0x78,0xDE,0x6A,0x96,0xE3,0xEE } },
-+		{ 16 , { 0x0F,0xAC,0x49,0xAD,0xBB,0x3B,0xCA,0x70,0x07,0xF7,0x4E,0xFC,0xE8,0x34,0x3E,0x7E } },
-+		{ 8 , { 0x0F,0xE4,0xAE,0xEE,0x2B,0x08,0xEE,0xD0 } },
-+		{ 16 , { 0x3F,0xE7,0x40,0x35,0x54,0xDF,0x0F,0x71,0x4A,0x92,0xC3,0xDF,0x8B,0x52,0x72,0xE7 } },
-+		{ 12 , { 0x33,0x3C,0x92,0x3B,0xA2,0x2F,0x2D,0xD5,0x38,0xBB,0xF4,0xC1 } },
-+		{ 8 , { 0x0F,0x07,0xFC,0x05,0xBB,0x58,0x06,0x5A } },
-+		{ 9 , { 0x38,0x37,0x9A,0x45,0x6F,0x99,0xCE,0xC9,0xF6 } },
-+		{ 16 , { 0x0F,0x72,0x45,0xC8,0x00,0x0D,0x68,0xAA,0x07,0xDE,0xDF,0x82,0x69,0x0E,0x32,0xE9 } },
-+		{ 16 , { 0x07,0x78,0xC1,0x67,0x9E,0x54,0x8A,0x2B,0x07,0xEA,0xA7,0x77,0xD4,0x9E,0xE5,0xE3 } },
-+		{ 8 , { 0x07,0xB6,0xB9,0xFE,0xBE,0xD9,0x74,0x8A } },
-+		{ 12 , { 0x33,0x88,0x98,0xA2,0xC2,0x9F,0x73,0x68,0x12,0xAB,0xC5,0x1C } },
-+		{ 8 , { 0x07,0xBB,0xD3,0x37,0x63,0x4C,0x82,0x3F } },
-+		{ 16 , { 0x3F,0xD3,0xD1,0xD6,0x5A,0xED,0x66,0xB7,0xAB,0x9F,0x84,0xE6,0xE5,0x0F,0x1E,0x93 } },
-+		{ 16 , { 0x37,0xFB,0x70,0x41,0x8C,0xD8,0x54,0x2A,0x99,0xD0,0x57,0x8F,0xE7,0x09,0x91,0x3C } },
-+		{ 16 , { 0x37,0x5B,0x65,0x7A,0x89,0x19,0xF8,0xAD,0x6E,0x25,0x02,0x48,0xA4,0xBE,0xE2,0xD2 } },
-+		{ 16 , { 0x3F,0x2C,0x56,0x91,0xB0,0xFA,0x21,0x6E,0x88,0xC0,0x24,0x84,0x93,0xBA,0xC7,0x6E } },
-+		{ 16 , { 0x3F,0xD6,0x00,0x15,0x3F,0x12,0x31,0x6D,0x12,0x53,0x27,0xDC,0xAC,0x8C,0x77,0xED } },
-+		{ 13 , { 0x44,0xD3,0x8E,0xEF,0xE2,0x0F,0x81,0xD6,0xCB,0xBA,0xA0,0x64,0x40 } },
-+		{ 16 , { 0x37,0xDC,0x24,0xEA,0x2D,0xCB,0x61,0xA7,0x1A,0x97,0xFF,0x6B,0xA0,0x5C,0xB8,0xF9 } },
-+		{ 16 , { 0x37,0x30,0x53,0x4C,0x24,0x5D,0x31,0x12,0x57,0x02,0x7C,0x0E,0x41,0x80,0x79,0xC1 } },
-+		{ 10 , { 0x49,0xC8,0x0F,0x23,0x35,0xC5,0xD2,0x8A,0xC9,0x16 } },
-+		{ 16 , { 0x37,0x3C,0xED,0x06,0x89,0xCA,0x5C,0xE6,0x02,0x2E,0x09,0xA2,0xC3,0xF0,0x64,0x32 } },
-+		{ 16 , { 0x0F,0xF2,0x4F,0x8F,0xDE,0x9F,0xBA,0x5C,0x0F,0x67,0xB2,0xC5,0xB9,0x28,0xCC,0x2E } },
-+		{ 16 , { 0x07,0xF8,0xE1,0xF2,0x5E,0xFF,0xCE,0xC6,0x07,0x9F,0x9D,0x23,0x64,0xAC,0x9B,0x67 } },
-+		{ 16 , { 0x07,0x2A,0x4C,0x3D,0x14,0xBB,0xD4,0x31,0x0F,0x0C,0x24,0xD2,0x12,0x8C,0xD1,0x65 } },
-+		{ 16 , { 0x37,0x12,0x02,0x1B,0xEC,0x92,0xEF,0x9E,0x56,0xA7,0x96,0x6E,0xB2,0x8D,0x12,0x2F } },
-+		{ 16 , { 0x37,0xAB,0x09,0x10,0x3C,0x5C,0x1C,0xE5,0x4A,0x38,0x19,0xC8,0x7A,0xA9,0x7C,0x60 } },
-+		{ 16 , { 0x3F,0x05,0xDE,0x7F,0x76,0x75,0x33,0x73,0x43,0x68,0xB4,0xC2,0xD0,0xA8,0x47,0xAC } },
-+		{ 16 , { 0x3F,0x40,0xE3,0xB5,0x09,0xF4,0xF0,0x07,0x1A,0x4E,0x61,0x25,0x0D,0x25,0x34,0x28 } },
-+		{ 16 , { 0x3F,0x77,0xA1,0xA0,0xC2,0x84,0x9F,0x70,0xF0,0x5F,0x71,0x0E,0x1F,0x68,0xA7,0x3F } },
-+		{ 16 , { 0x3F,0x3A,0x52,0x96,0x83,0x9A,0x02,0x06,0x35,0x2A,0x1C,0x3A,0x75,0xBA,0x65,0xD8 } },
-+		{ 12 , { 0x43,0x34,0x82,0x22,0x07,0xDE,0x9A,0xE0,0xE3,0x0C,0x23,0x86 } },
-+		{ 16 , { 0x37,0x1F,0x51,0x23,0xD9,0x7B,0x66,0x1C,0x8C,0xE0,0xA5,0xB6,0xA8,0x89,0xA3,0x4C } },
-+		{ 16 , { 0x37,0xB2,0xC7,0x45,0x42,0xCA,0x16,0xE9,0x86,0xEA,0xA9,0x8A,0x22,0xEF,0xB4,0xCA } },
-+		{ 16 , { 0x37,0xD7,0xD1,0x5F,0x7B,0x33,0x07,0x21,0x52,0x59,0x61,0x89,0xF3,0x90,0xF8,0xEA } },
-+		{ 14 , { 0x4D,0xC3,0x87,0xBB,0x9D,0xAF,0x0F,0xBC,0x66,0x33,0xBE,0x92,0x62,0xEF } },
-+		{ 16 , { 0x3F,0x62,0xA8,0xCE,0xF1,0xB2,0x3D,0x16,0xCF,0xD6,0x21,0x1F,0xA3,0x48,0x26,0xC8 } },
-+		{ 10 , { 0x41,0x43,0x07,0xC2,0x55,0x4B,0x1D,0xEA,0x49,0x68 } },
-+		{ 13 , { 0x3C,0xD4,0xE5,0xA3,0x20,0xCB,0x42,0x9D,0xC4,0xFC,0x7E,0xAB,0xCA } },
-+		{ 8 , { 0x07,0xB1,0x04,0xB5,0x51,0xE4,0xDF,0x9F } },
-+		{ 16 , { 0x37,0x1F,0x5E,0xEB,0xAC,0x9C,0x8C,0xE9,0xF9,0xA1,0xBB,0x8A,0x68,0x47,0x61,0xA2 } },
-+		{ 16 , { 0x37,0x04,0x7B,0xC4,0xE1,0x7F,0x2B,0xBE,0x2A,0x60,0x13,0xC7,0x50,0xA1,0xB8,0x36 } },
-+		{ 10 , { 0x39,0x35,0xAE,0x58,0xAA,0x84,0xEA,0x76,0x52,0xCC } },
-+		{ 8 , { 0x07,0x69,0x40,0x3F,0x04,0x60,0x17,0x2C } },
-+		{ 16 , { 0x37,0xD4,0x50,0x3E,0x2E,0xCE,0x73,0xF2,0xED,0x7E,0x12,0x5A,0xF1,0x21,0xFA,0xEC } },
-+		{ 8 , { 0x0F,0x54,0x0A,0x35,0x46,0xF8,0xA4,0x34 } },
-+		{ 12 , { 0x3B,0x1A,0x6B,0x4D,0x95,0xCE,0x02,0x0D,0x54,0x48,0x11,0x49 } },
-+		{ 16 , { 0x07,0xE2,0x68,0x94,0x50,0x03,0x14,0xD5,0x07,0x1E,0x04,0xD6,0x66,0x5B,0xF0,0x8B } },
-+		{ 8 , { 0x07,0xD8,0xD1,0x2F,0x35,0x9C,0x42,0x9F } },
-+		{ 16 , { 0x3F,0xD1,0xDA,0x9A,0xF7,0x0E,0x1D,0xAD,0xD2,0x16,0xD7,0x2B,0xD3,0x74,0x89,0x92 } },
-+		{ 16 , { 0x3F,0xBA,0x99,0xBA,0x03,0x40,0xB0,0xE5,0x21,0x57,0x3A,0x4C,0x91,0x9F,0x8B,0x73 } },
-+		{ 15 , { 0x49,0x68,0x07,0x9F,0xCE,0xC6,0xE1,0xFE,0xB7,0xC8,0x44,0xD0,0xAC,0x97,0x5E } },
-+		{ 8 , { 0x0F,0x86,0xF1,0xFE,0x3B,0x83,0x5B,0x71 } },
-+		{ 10 , { 0x39,0x5C,0xEE,0xC6,0xAB,0xA2,0x32,0xB6,0xCD,0x1E } },
-+		{ 16 , { 0x0F,0xDB,0xD5,0x00,0x80,0xE5,0x8F,0xF4,0x07,0x9F,0xCE,0x1A,0x6D,0x00,0x91,0x8F } },
-+		{ 8 , { 0x0F,0xDC,0x4B,0xE8,0x37,0xAC,0x80,0xE7 } },
-+		{ 9 , { 0x38,0x0D,0x16,0xF8,0x22,0x6D,0x54,0xB5,0x72 } },
-+		{ 11 , { 0x0F,0x3F,0xCB,0x62,0x48,0xA7,0xB9,0x92,0x4A,0x85,0x17 } },
-+		{ 8 , { 0x07,0xCA,0x4B,0x40,0x47,0xA0,0x82,0xF6 } },
-+		{ 16 , { 0x3F,0x01,0xC0,0x03,0x69,0x3F,0x89,0x4A,0xAA,0x24,0xC2,0x3C,0x24,0xA4,0x0A,0x12 } },
-+		{ 16 , { 0x37,0xD8,0x01,0x02,0x77,0xAB,0xB4,0xC1,0xC9,0xB4,0x04,0x68,0x15,0xBE,0x6A,0xEC } },
-+		{ 10 , { 0x39,0x2C,0x13,0x17,0x37,0xE1,0xF9,0xF6,0xEE,0x00 } },
-+		{ 15 , { 0x0F,0x06,0x30,0x10,0x12,0x3B,0x7C,0xDB,0x4E,0x33,0xB6,0xAF,0xEF,0x95,0x0E } },
-+		{ 16 , { 0x0F,0xE0,0xF5,0xE4,0xFA,0xEA,0x82,0x32,0x0F,0xA6,0x8D,0x92,0x58,0x06,0xDF,0x08 } },
-+		{ 16 , { 0x37,0x52,0x3C,0xA9,0x93,0xE8,0xFC,0x3F,0x1A,0x44,0x67,0x10,0xEE,0x0C,0xBF,0x23 } },
-+		{ 10 , { 0x41,0x20,0x07,0xE8,0xA2,0xB8,0x53,0x92,0x44,0x14 } },
-+		{ 16 , { 0x3F,0x15,0xA4,0xE8,0x4B,0x85,0x0C,0x9D,0xC4,0x9C,0x60,0x2F,0x42,0x5E,0xF6,0xEE } },
-+		{ 16 , { 0x3F,0x55,0x5A,0xAD,0x27,0x5F,0xDC,0x07,0xEF,0x32,0x7E,0x58,0xD2,0xFA,0x2A,0x4A } },
-+		{ 8 , { 0x07,0xBD,0xD5,0x42,0x09,0x21,0x5E,0xD5 } },
-+		{ 12 , { 0x3B,0x18,0x38,0x33,0x0B,0x23,0x35,0x69,0xB1,0x65,0x91,0x0C } },
-+		{ 16 , { 0x0F,0x81,0xA7,0xDA,0x78,0x40,0xE2,0x71,0x07,0x2C,0x50,0x4E,0x27,0xB3,0x61,0xE6 } },
-+		{ 15 , { 0x3E,0x83,0xCC,0xDB,0xCF,0x1F,0xC7,0x07,0x06,0xB3,0x98,0xF7,0x51,0x18,0x91 } },
-+		{ 16 , { 0x0F,0x8C,0x4F,0xEF,0x7E,0x6A,0x7D,0x58,0x07,0xFC,0xCD,0xCC,0xF6,0x1C,0xB9,0x73 } },
-+		{ 16 , { 0x07,0xF3,0x72,0xCC,0x1E,0x9E,0x11,0xCC,0x07,0x2C,0x65,0xF1,0x73,0xDB,0xFE,0x79 } },
-+		{ 8 , { 0x07,0xFB,0x7F,0x9D,0x8C,0x26,0x05,0x5A } },
-+		{ 9 , { 0x38,0xCE,0xD2,0x5A,0x36,0xC6,0x18,0x62,0xC9 } },
-+		{ 11 , { 0x0F,0xE4,0x9C,0xEA,0x55,0x57,0x84,0x37,0x4A,0x8A,0x90 } },
-+		{ 8 , { 0x07,0x6D,0xC9,0xA9,0x20,0xFC,0x83,0xF8 } },
-+		{ 15 , { 0x36,0xCB,0x14,0x43,0x10,0x8C,0x98,0x38,0x76,0x25,0x4E,0xBA,0x68,0x79,0xB7 } },
-+		{ 8 , { 0x0F,0x99,0x87,0xAB,0x3D,0x0D,0x21,0x82 } },
-+		{ 15 , { 0x36,0x82,0xB5,0xAA,0xF8,0xB2,0xBC,0xDD,0x00,0xD7,0xE1,0x42,0x38,0xB2,0x7D } },
-+		{ 8 , { 0x07,0x40,0x3D,0x78,0xDB,0x54,0x66,0xCA } },
-+		{ 13 , { 0x34,0xAF,0x5F,0x79,0x9B,0xF9,0x60,0x55,0x75,0xE0,0x6B,0x94,0x3C } },
-+		{ 16 , { 0x0F,0x81,0xAE,0x7E,0x06,0xC7,0x27,0x9F,0x07,0xD2,0x33,0xC1,0x0E,0x97,0x51,0xED } },
-+		{ 16 , { 0x0F,0x23,0x3C,0xCA,0x98,0x51,0x36,0xFC,0x47,0x5D,0x47,0x14,0x9C,0x43,0xBB,0x42 } },
-+		{ 16 , { 0x07,0x5A,0xE1,0x01,0xEF,0xE4,0x77,0xCA,0x07,0xC4,0xF9,0x29,0x20,0x13,0xA5,0xC1 } },
-+		{ 13 , { 0x07,0x8B,0xB8,0xD3,0xA3,0xC9,0xA4,0xEE,0x4C,0xCB,0xCB,0x74,0x0E } },
-+		{ 8 , { 0x0F,0x94,0x40,0xDC,0x4A,0xA9,0x1A,0x30 } },
-+		{ 16 , { 0x37,0x06,0x49,0xC5,0xA7,0xF4,0x91,0x9C,0xB6,0x9E,0x0F,0x83,0xFD,0x8B,0xF9,0x67 } },
-+		{ 16 , { 0x37,0x85,0x94,0x0A,0x41,0x14,0x42,0xA8,0x68,0x1F,0xAB,0xC1,0x8D,0xA0,0xD0,0x54 } },
-+		{ 16 , { 0x37,0x2F,0x03,0xEF,0xEA,0x78,0x16,0xC3,0xB6,0xEF,0xA5,0xE2,0x8C,0xC2,0x5D,0xB6 } },
-+		{ 12 , { 0x43,0xAF,0x0C,0x94,0x0F,0xC7,0xD1,0x32,0x5A,0x52,0xC6,0x5A } },
-+		{ 8 , { 0x07,0x91,0x72,0x13,0x08,0x57,0x30,0xB6 } },
-+		{ 16 , { 0x37,0x6D,0x6F,0x19,0xEE,0xB4,0x6F,0x00,0x1B,0x49,0xA2,0xD8,0xE1,0x3A,0x9E,0x47 } },
-+		{ 14 , { 0x45,0xD5,0xFB,0x6D,0x44,0x21,0x07,0xD8,0x13,0xF5,0x21,0x6B,0xDC,0x60 } },
-+		{ 8 , { 0x07,0x6B,0x70,0xE2,0xBB,0xB0,0x57,0xC1 } },
-+		{ 9 , { 0x38,0xB9,0x67,0x42,0x0E,0xDB,0x02,0xD6,0xC9 } },
-+		{ 8 , { 0x07,0x11,0xF6,0x9D,0x3B,0xC8,0x66,0xC1 } },
-+		{ 16 , { 0x37,0x91,0xA4,0x40,0x6D,0xC7,0x10,0x5F,0xB6,0xC8,0x59,0x55,0x59,0x6C,0x66,0x92 } },
-+		{ 16 , { 0x3F,0x0B,0xF7,0x08,0x80,0x30,0xE9,0x19,0x64,0x69,0xE1,0xCE,0x90,0x03,0x88,0xE5 } },
-+		{ 12 , { 0x43,0xF9,0xEB,0x0D,0x07,0xB3,0xAC,0x79,0x50,0x7A,0x71,0x81 } },
-+		{ 16 , { 0x37,0xAD,0x92,0x83,0x55,0x86,0x1A,0xA2,0x9C,0xA7,0xBC,0x6E,0x62,0xD1,0x13,0x09 } },
-+		{ 16 , { 0x3F,0x69,0x5C,0x04,0x2A,0x3E,0x2B,0xBC,0xDC,0x0F,0x31,0x71,0xDD,0x45,0xFD,0xE3 } },
-+		{ 16 , { 0x37,0x01,0xA3,0x13,0xAD,0xEB,0xEF,0x95,0x59,0xA7,0xF8,0x1B,0x8E,0x7E,0xE2,0xB5 } },
-+		{ 16 , { 0x3F,0x8D,0xCA,0x8A,0x62,0x0F,0xF9,0xDA,0xC2,0xAB,0x30,0x94,0x89,0x13,0x3F,0xB5 } },
-+		{ 13 , { 0x44,0x13,0x19,0x74,0x65,0x05,0x10,0x80,0xE7,0x42,0x88,0x82,0xEC } },
-+		{ 16 , { 0x37,0xC4,0x35,0x3F,0x16,0x05,0x58,0x44,0x79,0x75,0xE6,0x97,0x11,0x0F,0x7F,0xEE } },
-+		{ 16 , { 0x37,0x33,0x82,0x31,0x49,0x1E,0x56,0x05,0x82,0xF2,0xB0,0xD2,0x8F,0x3B,0x56,0xF8 } },
-+		{ 16 , { 0x37,0x74,0x0C,0xE0,0xC0,0x2B,0xC5,0xCD,0xFD,0x9B,0x30,0x34,0x08,0xFA,0xAA,0xDF } },
-+		{ 16 , { 0x3F,0xD8,0x1D,0xD5,0xCF,0x32,0x6D,0xF2,0xF2,0x90,0xEF,0x51,0x16,0x89,0x2D,0x75 } },
-+		{ 16 , { 0x37,0xE5,0x67,0xA4,0xF4,0x90,0xFF,0x5B,0x52,0x0B,0x4E,0xF1,0xF7,0xE9,0x0C,0x98 } },
-+		{ 16 , { 0x37,0xB9,0x2B,0x9A,0x6D,0xB8,0x02,0x03,0xD4,0x6C,0x58,0x2C,0xE7,0x97,0xF7,0x8A } },
-+		{ 16 , { 0x3F,0x65,0x61,0x93,0xDA,0x29,0x88,0xE9,0x85,0x0F,0xEE,0xD4,0x5E,0x18,0x82,0x5E } },
-+		{ 16 , { 0x3F,0x01,0x83,0xB0,0x32,0x5C,0x76,0xBA,0x30,0x2D,0x6C,0xE0,0x2F,0x96,0x04,0x25 } },
-+		{ 16 , { 0x37,0x17,0x4E,0x91,0x10,0xD2,0xB9,0x9F,0x9B,0x68,0x5F,0x84,0xB7,0xF6,0x3F,0x9F } },
-+		{ 16 , { 0x3F,0x4F,0x0B,0xDD,0x28,0x52,0xF3,0x6E,0x8A,0x6C,0x07,0xD1,0x7A,0x52,0xE6,0xFC } },
-+		{ 13 , { 0x3C,0x2C,0x7E,0x6D,0xAE,0xFD,0x2B,0xC1,0x21,0xB4,0x4C,0x78,0x89 } },
-+		{ 16 , { 0x07,0x16,0x9A,0xEC,0xA4,0xF3,0xEB,0xD3,0x07,0xA4,0x56,0xDE,0xDF,0x04,0x05,0xCB } },
-+		{ 16 , { 0x37,0xDD,0xFB,0x88,0x60,0x7F,0x6D,0x5F,0x1A,0xCF,0x0C,0xC8,0x94,0x82,0x63,0x1F } },
-+		{ 16 , { 0x3F,0x94,0x23,0x91,0xFB,0xDB,0xC1,0x02,0x5C,0x69,0xBA,0x49,0xE4,0xFD,0x90,0x6C } },
-+		{ 16 , { 0x3F,0x1C,0xF5,0x74,0x3A,0xAA,0x02,0xA3,0x4A,0x69,0x8E,0x2A,0xFF,0x30,0xFA,0x71 } },
-+		{ 16 , { 0x3F,0x0E,0x07,0x8C,0xEC,0x21,0x9F,0x9A,0xF2,0xBD,0x30,0xA5,0x6C,0xB9,0x2A,0xD5 } },
-+		{ 16 , { 0x3F,0x21,0x1D,0xC7,0x0D,0xF4,0xE0,0x71,0x14,0xFE,0x88,0xD0,0xB3,0x90,0x30,0x77 } },
-+		{ 16 , { 0x37,0x3D,0x55,0x05,0x42,0x07,0x3F,0xC1,0x5E,0x45,0xA2,0x6D,0xA2,0xF4,0x1E,0xDC } },
-+		{ 16 , { 0x3F,0xA1,0x5B,0xB5,0x6A,0x9C,0x8F,0x22,0x4D,0x0F,0x8A,0xBE,0x4A,0xF8,0x8D,0xB8 } },
-+		{ 16 , { 0x3F,0xC0,0xD7,0x2C,0x97,0xB5,0x96,0xF6,0x37,0x13,0xB7,0x70,0x3B,0xC7,0xCE,0x3B } },
-+		{ 16 , { 0x37,0x2E,0x7D,0x7B,0x5E,0xEA,0x83,0x72,0x62,0x01,0xDC,0x5E,0x8E,0xCF,0x44,0x52 } },
-+		{ 16 , { 0x3F,0x54,0x59,0xB7,0x0A,0x69,0x37,0x51,0xB9,0x72,0x50,0xB0,0xC8,0xF3,0xDF,0x0F } },
-+		{ 16 , { 0x37,0x9C,0x35,0xB1,0x3B,0x93,0x84,0x5F,0xF4,0xB0,0x2F,0xA0,0xB9,0xC9,0x1C,0x09 } },
-+		{ 16 , { 0x37,0xC4,0x03,0xB8,0x6A,0xDD,0xC3,0x7F,0x3D,0x88,0xFA,0x9E,0x46,0xBF,0x67,0x3C } },
-+		{ 11 , { 0x42,0x92,0x5D,0x07,0x16,0x24,0x54,0x46,0x48,0x3D,0xDA } },
-+		{ 16 , { 0x37,0x29,0x6B,0x4B,0x22,0xCA,0x10,0x55,0x0C,0xF3,0x94,0x4F,0x39,0x45,0x57,0xC1 } },
-+		{ 15 , { 0x36,0xF8,0x9F,0xED,0xB2,0x9D,0xA0,0x92,0xFC,0x09,0x42,0xFF,0x51,0xD8,0x70 } },
-+		{ 14 , { 0x07,0x2A,0x9F,0xD6,0x5F,0x90,0x8C,0x27,0x45,0xD7,0x7C,0xA1,0x3C,0x27 } },
-+		{ 8 , { 0x0F,0x39,0x9A,0x9A,0x63,0x03,0xFA,0x94 } },
-+		{ 16 , { 0x37,0x47,0xF1,0x16,0xC3,0xD6,0x7B,0x88,0x6D,0x8B,0x15,0x30,0xD5,0xEB,0x25,0x22 } },
-+		{ 16 , { 0x37,0xD1,0xD7,0x78,0xBC,0xF7,0xC4,0xDD,0xA0,0x45,0x89,0x08,0x54,0x95,0xA8,0x12 } },
-+		{ 16 , { 0x37,0x24,0x55,0x7F,0xA5,0x20,0xE2,0x51,0x06,0xEE,0x40,0x98,0xF1,0x47,0xA1,0x9E } },
-+		{ 11 , { 0x32,0x4C,0x65,0xB2,0x97,0x7D,0x88,0x13,0xCE,0x17,0x4E } },
-+		{ 8 , { 0x07,0xA9,0x71,0x73,0xE8,0x0E,0x03,0x8B } },
-+		{ 16 , { 0x3F,0xF1,0x11,0x00,0x5B,0xCA,0xE8,0x92,0xDE,0xCB,0x25,0xB5,0xBA,0x2C,0x61,0x02 } },
-+		{ 16 , { 0x37,0x7B,0xA5,0x54,0x4D,0xDA,0x95,0xC1,0x3B,0xB3,0x80,0xAE,0xAC,0x03,0xEA,0xF2 } },
-+		{ 16 , { 0x37,0xB2,0xCE,0x77,0x35,0x7C,0x20,0x57,0x05,0x35,0xFA,0x5E,0x8A,0xD9,0x09,0x65 } },
-+		{ 16 , { 0x3F,0xA6,0x89,0xF1,0xCB,0x7F,0xD3,0x1D,0x0C,0x97,0x6E,0x7F,0x31,0x7B,0x67,0xDF } },
-+		{ 10 , { 0x41,0x78,0x0F,0xF8,0xB9,0xD0,0x37,0xBD,0xB4,0x92 } },
-+		{ 16 , { 0x07,0x22,0x23,0x00,0xB7,0xA1,0x75,0xEE,0x07,0x40,0x28,0x63,0x9D,0x45,0x68,0x4B } },
-+		{ 16 , { 0x37,0xB7,0xA3,0x6D,0xFB,0x16,0xC4,0x23,0x1D,0x7E,0xB8,0x87,0x45,0x9D,0x6E,0x03 } },
-+		{ 16 , { 0x37,0xF1,0x0D,0x4E,0xAB,0xA0,0xF0,0x47,0xE8,0x6E,0xB4,0x68,0xAD,0xC6,0x38,0x20 } },
-+		{ 16 , { 0x37,0x6E,0xF5,0x4E,0xC2,0xE6,0x51,0x6D,0xD2,0xC1,0x63,0x01,0xB5,0x6D,0x5F,0xFD } },
-+		{ 9 , { 0x30,0x72,0xCE,0xAE,0xFE,0x96,0xC4,0x20,0x70 } },
-+		{ 11 , { 0x07,0x39,0xCC,0xFB,0x91,0xB9,0xA7,0x66,0x4A,0xF6,0xB8 } },
-+		{ 8 , { 0x07,0xA1,0xE8,0x8D,0x69,0xE2,0x04,0xA2 } },
-+		{ 16 , { 0x37,0x06,0x3F,0x8C,0x15,0x4A,0x5D,0xF6,0x6F,0xD6,0x25,0x35,0x20,0x3C,0x9F,0x9D } },
-+		{ 16 , { 0x3F,0x52,0x8D,0xFC,0x2A,0x47,0x00,0x6C,0xC6,0x3D,0x1E,0x8B,0xFE,0x65,0xC7,0x31 } },
-+		{ 16 , { 0x3F,0xC9,0x13,0x38,0xE8,0x26,0xDE,0x16,0xD9,0xBD,0x16,0x06,0xD8,0x5A,0x26,0x36 } },
-+		{ 16 , { 0x3F,0x31,0xAC,0x7E,0xA8,0x90,0xF6,0x3A,0x02,0x59,0x6B,0xF1,0x1E,0x02,0x1B,0xD1 } },
-+		{ 10 , { 0x41,0x8D,0x0F,0x60,0xD8,0x95,0xC9,0x3C,0x0B,0x2A } },
-+		{ 16 , { 0x0F,0x17,0xA0,0xDA,0x40,0x72,0x9A,0x78,0x07,0x4C,0x6B,0x32,0xAD,0x21,0x9C,0xB0 } },
-+		{ 8 , { 0x0F,0x6A,0x23,0x4C,0x65,0x56,0x33,0x0D } },
-+		{ 12 , { 0x33,0x7F,0xA0,0x9C,0xC7,0x08,0x60,0xCB,0x35,0x59,0x22,0xAA } },
-+		{ 16 , { 0x07,0x3B,0xDB,0xFF,0x14,0x24,0xCB,0x64,0x0F,0xF5,0x60,0xE6,0x68,0x48,0xF3,0x43 } },
-+		{ 16 , { 0x07,0x78,0x60,0x84,0x3F,0xC7,0x43,0xEE,0x0F,0xA8,0xA1,0x0F,0xCF,0xE1,0x3F,0x86 } },
-+		{ 16 , { 0x0F,0xC0,0x67,0x53,0xC3,0x8E,0x5E,0x0A,0x07,0x7C,0x30,0xDA,0x6C,0x6A,0xCA,0xAA } },
-+		{ 16 , { 0x0F,0x07,0x88,0x95,0x22,0xB7,0x88,0xBC,0x07,0x4A,0x2C,0xB3,0x7A,0xB9,0x75,0x22 } },
-+		{ 11 , { 0x07,0x2A,0x62,0x95,0x87,0x61,0x93,0x59,0x42,0xEA,0x8F } },
-+		{ 16 , { 0x0F,0x62,0x4C,0xC9,0x92,0xA0,0x43,0x96,0x0F,0x7C,0xD1,0x8B,0x51,0x25,0x67,0xC4 } },
-+		{ 16 , { 0x07,0x39,0x88,0x93,0xDE,0x93,0x29,0x80,0x07,0xA7,0xAE,0x2A,0xE0,0xB1,0xB4,0x79 } },
-+		{ 16 , { 0x0F,0x1C,0xDE,0x1C,0xEB,0x0F,0x9C,0x74,0x0F,0xC5,0xC2,0x09,0x0A,0xED,0x50,0x79 } },
-+		{ 8 , { 0x07,0x0B,0x1A,0x05,0x6D,0x49,0xE0,0xFB } },
-+		{ 16 , { 0x37,0x2A,0xBA,0x74,0x71,0xA9,0x88,0xCB,0x42,0x3E,0x0D,0x5F,0x1A,0xD2,0xAA,0xE1 } },
-+		{ 11 , { 0x32,0x02,0x90,0xE7,0xD3,0x09,0xFA,0x1A,0xC8,0x33,0x65 } },
-+		{ 15 , { 0x05,0xA6,0x9F,0x84,0x95,0x2F,0x16,0x7B,0x4E,0xCD,0xEA,0xBD,0x84,0xB1,0xC0 } },
-+		{ 16 , { 0x07,0xF4,0x5F,0x53,0xA9,0x9D,0xC2,0x2F,0x0F,0x86,0xA5,0x30,0x58,0x55,0x79,0xF4 } },
-+		{ 16 , { 0x0F,0xAF,0x6F,0x5D,0x7D,0xD5,0x5E,0xB2,0x07,0x4C,0x26,0x58,0xA7,0x42,0xBC,0x88 } },
-+		{ 16 , { 0x0F,0x66,0xF8,0xAE,0xA1,0x28,0x54,0x49,0x07,0x77,0x84,0x7E,0xF5,0xD6,0xF2,0x1C } },
-+		{ 8 , { 0x07,0x2E,0xFD,0xAD,0xB8,0x75,0xFE,0xE1 } },
-+		{ 9 , { 0x38,0x8B,0x53,0xED,0xF4,0x54,0x51,0x36,0xFC } },
-+		{ 16 , { 0x0F,0xCD,0x55,0xD1,0x59,0xC8,0xFB,0xF0,0x0F,0xFB,0x6D,0x1D,0xFE,0x5B,0xEE,0x2E } },
-+		{ 16 , { 0x0F,0xF9,0xA0,0xF7,0xCB,0x23,0x7D,0x43,0x0F,0x3D,0xB8,0x0B,0x82,0x66,0xC8,0xB1 } },
-+		{ 9 , { 0x38,0x9E,0xDD,0xDE,0xDD,0x88,0xC2,0xD1,0x83 } },
-+		{ 16 , { 0x0F,0xE9,0xCA,0xB0,0xF9,0x8B,0x10,0xB0,0x0F,0xEE,0x0C,0x59,0x94,0x87,0x00,0xAF } },
-+		{ 16 , { 0x37,0x17,0x34,0x12,0xB6,0xB0,0xAB,0xEA,0xD9,0xB7,0x7B,0x4C,0x85,0xA1,0xE3,0x99 } },
-+		{ 10 , { 0x49,0x96,0x0F,0xE1,0xAD,0xB7,0xA8,0xDE,0xF5,0x51 } },
-+		{ 16 , { 0x07,0xFD,0x04,0xDE,0xB1,0x80,0xFA,0x56,0x0F,0x56,0xCC,0xDB,0xF2,0x2B,0x38,0xE3 } },
-+		{ 16 , { 0x0F,0xC6,0x2F,0x42,0x67,0x15,0x5F,0xDB,0x07,0x21,0xF4,0x54,0x8E,0x31,0x45,0x44 } },
-+		{ 15 , { 0x0F,0x54,0xD7,0xEC,0x08,0x9A,0x13,0xD3,0x4E,0xE7,0xDC,0x69,0xA9,0xEC,0x98 } },
-+		{ 16 , { 0x0F,0xAB,0x2F,0x3F,0x45,0x7A,0xD1,0x61,0x05,0xFE,0x24,0x54,0x46,0x54,0x61,0x1F } },
-+		{ 13 , { 0x3C,0x1C,0x56,0x93,0xC7,0x68,0xF5,0x2A,0x4B,0xA1,0x29,0x84,0x25 } },
-+		{ 16 , { 0x0F,0xDB,0x0F,0x14,0x77,0xAC,0xC5,0xC8,0x07,0xCA,0xCA,0x31,0x22,0x97,0x36,0x40 } },
-+		{ 11 , { 0x07,0xD3,0x2C,0x22,0x69,0x8E,0xEC,0xD9,0x42,0x1C,0x11 } },
-+		{ 16 , { 0x0F,0xE6,0x96,0x1E,0xA9,0x3C,0x25,0x8A,0x07,0x49,0x16,0x97,0xE8,0x2B,0xA1,0xCA } },
-+		{ 8 , { 0x0F,0xD8,0x78,0xF7,0x58,0x40,0xA0,0x0A } },
-+		{ 16 , { 0x3F,0x77,0x26,0x27,0xEF,0x07,0xBE,0xB1,0x17,0xF7,0x21,0x48,0x15,0x63,0x02,0xAB } },
-+		{ 10 , { 0x39,0xF0,0x01,0x60,0x65,0xD7,0xC2,0x23,0x19,0xDC } },
-+		{ 12 , { 0x07,0x01,0xB1,0x42,0xEE,0x5D,0x1B,0xDB,0x4B,0xA0,0xD3,0xD7 } },
-+		{ 16 , { 0x07,0xF0,0xD1,0x0F,0x00,0x04,0x54,0xF5,0x05,0x34,0x94,0x2F,0xDC,0xAA,0x34,0xEB } }
-+};
-+
-+#define FIRMWARE_LINES_3_0b5 (sizeof(Si2157_FW_3_0b5)/(sizeof(firmware_struct)))
-+#define RAM_SIG_3_0b5 0xDABDD450
-+#define RAM_CRC_3_0b5 0x1F4E
-+
-+/* SI2158_FIRMWARE_0_E_BUILD_15 */
-+u8 Si2158_FW_0_Eb15[] = {
-+		0x04,0x01,0x80,0x00,0xCC,0x58,0x98,0xD7,
-+		0x05,0xD3,0x99,0xC6,0xB2,0xBD,0x68,0x8B,
-+		0x05,0xDF,0xB3,0x1B,0x73,0x9E,0xAA,0x51,
-+		0x27,0xCF,0xF6,0x6C,0xCD,0xDD,0x5E,0x64,
-+		0x22,0xEB,0x8D,0x75,0xC2,0x4A,0xA8,0xFB,
-+		0x0F,0x04,0x3A,0x48,0x7C,0xCF,0x5A,0x5A,
-+		0x27,0x4B,0x3E,0x35,0x0D,0xBA,0xE9,0x2A,
-+		0x29,0x50,0x14,0x34,0xC1,0xD7,0x08,0x8B,
-+		0x07,0x1F,0xA0,0x69,0xFB,0xBD,0xA5,0x46,
-+		0x2E,0xF3,0xF8,0xBB,0xFD,0xC9,0x64,0xCB,
-+		0x0F,0x7E,0x43,0xA7,0xAA,0x87,0x5E,0x3B,
-+		0x2F,0x41,0xAB,0xE6,0xB5,0x5D,0xF0,0x86,
-+		0x2B,0x16,0x7D,0x1A,0x4C,0x72,0x68,0xFB,
-+		0x07,0x17,0x87,0x60,0x3C,0x6D,0x0C,0x60,
-+		0x26,0x8C,0xCD,0xE5,0x90,0x80,0x5C,0x53,
-+		0x07,0x6E,0xA1,0x0F,0x6A,0xBE,0x0D,0x3B,
-+		0x2F,0x15,0xB8,0x23,0xED,0x6D,0x1A,0xDE,
-+		0x24,0x6F,0xE7,0x95,0x1E,0x6F,0x9A,0x85,
-+		0x0F,0xE4,0x4F,0x35,0xA8,0xE6,0x37,0xBF,
-+		0x22,0x76,0xD4,0x39,0x4C,0xFA,0x73,0x59,
-+		0x0F,0xD6,0xB4,0xF1,0x43,0x6B,0xCE,0xF1,
-+		0x2A,0xE2,0xF6,0xC6,0x39,0x39,0x82,0x2A,
-+		0x0F,0xB9,0xF6,0x5D,0xD6,0x3C,0x25,0x17,
-+		0x2F,0x0C,0x63,0x24,0xC6,0xF1,0xB1,0x37,
-+		0x2F,0xF9,0xA4,0xED,0x41,0xD0,0xCA,0xED,
-+		0x23,0xD4,0x9D,0x4A,0xAB,0xF1,0x81,0x3C,
-+		0x07,0x79,0xF8,0xA4,0xB4,0x71,0x25,0xCE,
-+		0x2F,0xCC,0x0A,0x0C,0x1D,0x0F,0x79,0x1F,
-+		0x2F,0x2A,0xB8,0x84,0xE2,0x43,0x4E,0x1B,
-+		0x26,0xAA,0x6B,0x06,0x2B,0xB1,0x6F,0xB2,
-+		0x0F,0x12,0x4F,0xCB,0x29,0x04,0xFB,0xD0,
-+		0x25,0x3E,0xE7,0x17,0x64,0xF1,0x47,0xC0,
-+		0x0F,0x8F,0x43,0x9F,0x23,0x2A,0x50,0x36,
-+		0x2A,0x6C,0x03,0xD7,0x29,0x87,0xA5,0x99,
-+		0x07,0xC3,0x49,0x0D,0x73,0x77,0x0C,0xC6,
-+		0x07,0x3A,0x8E,0x3D,0x75,0xB8,0x48,0x55,
-+		0x0F,0xAB,0x62,0x72,0x46,0x0D,0xD6,0x80,
-+		0x27,0x75,0x1F,0x93,0x37,0x7A,0x0D,0x41,
-+		0x21,0xCB,0xD3,0x31,0x0E,0x28,0x7B,0x26,
-+		0x0F,0xBA,0x8F,0x86,0xC0,0xE7,0xE1,0x26,
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-+		0x07,0x3F,0x54,0x83,0xF1,0x1D,0xEB,0x1C,
-+		0x0F,0x71,0xCB,0xCB,0x35,0x16,0x70,0xCF,
-+		0x07,0x9B,0x6C,0x52,0xBE,0xDC,0xE9,0x53,
-+		0x07,0x1E,0xA5,0xB4,0xE5,0xDB,0x90,0xC8,
-+		0x07,0x09,0x8A,0xC3,0xD0,0x44,0xA3,0xC2,
-+		0x27,0x88,0x28,0x62,0xFD,0x5D,0x04,0x32,
-+		0x23,0xE6,0xBE,0xD2,0x75,0x3D,0xF2,0x31,
-+		0x0F,0x24,0x16,0xFE,0x9F,0x59,0x7F,0xF6,
-+		0x0F,0x9D,0x27,0xEF,0x9B,0x9D,0x73,0x37,
-+		0x05,0xDC,0x6B,0xF9,0xA2,0xC7,0xD9,0x10,
-+		0x27,0x78,0x0D,0x95,0x0C,0x68,0xF1,0x1E,
-+		0x29,0x73,0x97,0x66,0x65,0xD2,0x5F,0xE3,
-+		0x07,0x6E,0xF8,0x1F,0xAA,0x15,0xA1,0x2D,
-+		0x0F,0xB3,0x8F,0x2C,0x08,0x51,0x96,0xE3,
-+		0x07,0xDF,0x6E,0x4A,0x2F,0x82,0x86,0x2D,
-+		0x0F,0x72,0xAA,0x0B,0xF3,0x22,0xF1,0x8E,
-+		0x07,0x84,0x6C,0x74,0xD3,0x32,0x80,0xE5,
-+		0x0F,0x62,0xC0,0x47,0xD5,0xF6,0xAB,0xDE,
-+		0x0F,0xBF,0xC1,0x20,0x97,0x19,0xBF,0x96,
-+		0x07,0x56,0x96,0xC3,0x74,0x0A,0x44,0x5A,
-+		0x26,0x93,0x78,0x0F,0x1F,0xF3,0x8B,0xC0,
-+		0x07,0xCC,0x52,0x10,0x0B,0x36,0x2E,0x4A,
-+		0x07,0x13,0x9D,0x25,0x52,0x95,0x90,0xE0,
-+		0x07,0xEF,0x65,0xC1,0x0E,0x43,0x18,0x49,
-+		0x05,0x19,0x6E,0xD4,0x67,0xBE,0x84,0xE9,
-+		0x27,0x7C,0x05,0xEA,0x57,0xBA,0x1E,0xEF,
-+		0x29,0x5A,0x88,0x54,0x89,0x9F,0x69,0x00,
-+		0x0F,0xE9,0xF6,0x6F,0x62,0xA0,0xA9,0x81,
-+		0x07,0x59,0xE1,0x41,0xBD,0x9B,0xAB,0x04,
-+		0x07,0xE4,0xD1,0x8E,0x35,0x9E,0xCD,0xD0,
-+		0x07,0x63,0x61,0x1A,0xD5,0x0B,0xED,0x8D,
-+		0x05,0xFA,0x25,0x5E,0x79,0x75,0x93,0x40,
-+		0x2D,0x56,0x6B,0x14,0x24,0x4F,0x62,0xCA,
-+		0x07,0x2F,0x0D,0x7D,0xB2,0xBA,0xD6,0xCC,
-+		0x0F,0x25,0xBA,0xD6,0x20,0x15,0xA2,0x8C,
-+		0x05,0x82,0x31,0x96,0x3A,0xD0,0x48,0x95,
-+		0x27,0xBD,0x4A,0x80,0x4C,0xD1,0x93,0x61,
-+		0x27,0x8A,0xD7,0x55,0xC2,0x82,0xBF,0x82,
-+		0x2F,0x34,0x42,0x4C,0x4F,0xAF,0x7C,0x57,
-+		0x27,0xB5,0x5B,0xE6,0x5B,0xA0,0x4D,0xFE,
-+		0x2C,0x1F,0x8E,0x76,0xB2,0xCF,0xD5,0xED,
-+		0x07,0x72,0x0F,0x0E,0x29,0x1C,0xD9,0xB0,
-+		0x2B,0xDC,0x0B,0x98,0xFA,0x34,0xD5,0x69,
-+		0x07,0x5F,0x24,0xAD,0x22,0xF9,0x90,0x2D,
-+		0x07,0xE3,0x21,0x4B,0xDF,0x46,0x09,0x62,
-+		0x07,0xF1,0x8A,0x19,0x92,0xF3,0x4C,0xAF,
-+		0x0F,0xBB,0xFA,0x83,0x0C,0x3F,0x49,0x79,
-+		0x07,0x16,0xF4,0xA4,0x4D,0x82,0x5C,0xF2,
-+		0x24,0x4B,0xE4,0x69,0xB1,0xD2,0x0D,0xDF,
-+		0x0F,0x21,0x9D,0xC8,0xCF,0xE2,0xB5,0x58,
-+		0x0F,0x2F,0xD6,0x94,0xCD,0x52,0x1E,0x5F,
-+		0x0F,0xFC,0xA6,0xC8,0x3C,0x20,0xAD,0x07,
-+		0x07,0x6A,0x13,0x7B,0xAD,0x5C,0x57,0x42,
-+		0x07,0xEC,0x4E,0x2A,0x3A,0x04,0xD3,0x86,
-+		0x27,0x72,0x2A,0x4D,0xC0,0xDA,0x3F,0xA5,
-+		0x24,0x32,0x26,0x8D,0xA2,0x66,0xDB,0x69,
-+		0x0F,0x58,0x83,0x18,0x14,0xFB,0x88,0x0C,
-+		0x0F,0x8A,0xE6,0x04,0x2C,0x71,0x0C,0x54,
-+		0x2F,0x34,0xC3,0xD8,0x00,0x1C,0x38,0xDD,
-+		0x21,0x1D,0x44,0x05,0x28,0xF8,0xC5,0x85,
-+		0x07,0xA3,0x17,0x50,0x3A,0x03,0x6A,0xF0,
-+		0x07,0x40,0xA7,0xFC,0x81,0x15,0x58,0x9E,
-+		0x0F,0xB2,0x91,0x6B,0xB9,0x17,0xCE,0xE2,
-+		0x0F,0xE5,0x50,0xDD,0x47,0xE6,0xEE,0x6D,
-+		0x07,0x84,0x20,0xD6,0xA9,0x5A,0x8C,0x02,
-+		0x0F,0xEE,0xA5,0x18,0xD6,0x38,0xD5,0x46,
-+		0x0F,0xBE,0xB4,0x03,0xE7,0x04,0x10,0x04,
-+		0x05,0x53,0xF1,0x43,0xCC,0xD1,0xCA,0x3E,
-+		0x2E,0x87,0xD9,0xD1,0x9A,0x54,0x46,0x77,
-+		0x05,0xB7,0xF5,0x3D,0x7C,0xE4,0x58,0xA3,
-+		0x27,0xE7,0xA3,0x7B,0xB8,0x2C,0xCC,0xB3,
-+		0x2A,0x8D,0x21,0xD6,0xC6,0xCF,0x99,0x7A,
-+		0x0F,0x27,0x92,0xE1,0x4A,0x9C,0x02,0x9D,
-+		0x07,0x52,0x8E,0x05,0xCC,0xC9,0xC3,0xFA,
-+		0x22,0x05,0xC3,0x5A,0x3D,0x72,0x70,0x0D,
-+		0x0F,0x52,0xEE,0x30,0x16,0xC0,0x8F,0xE7,
-+		0x0F,0x44,0x3E,0x46,0xE7,0xF6,0xD0,0x64,
-+		0x07,0x06,0xDD,0xCC,0xF8,0x4E,0x23,0x82,
-+		0x0F,0x9F,0x05,0xC0,0xA9,0x91,0x9E,0x0B,
-+		0x2F,0x60,0xD8,0x39,0x2B,0x95,0x38,0x22,
-+		0x22,0x9C,0x32,0xAC,0x8A,0x8F,0x89,0xCF,
-+		0x05,0xD2,0x48,0x9C,0x7A,0x99,0x9C,0xAC,
-+		0x2A,0xCD,0x32,0x74,0xED,0xF8,0x63,0xBA,
-+		0x0F,0xB2,0xFE,0x1B,0x00,0x53,0x0F,0x3A,
-+		0x24,0xAB,0xA2,0xC1,0x5B,0x1D,0xAD,0x83,
-+		0x07,0xDB,0x87,0x28,0x0E,0x1E,0x5A,0xEC,
-+		0x05,0x93,0x50,0x53,0x13,0x2C,0x0C,0xAD
-+};
-+
-+#define FIRMWARE_LINES_0_Eb15 (sizeof(Si2158_FW_0_Eb15)/(8*sizeof(u8)))
-+
-+/* SI2158_FIRMWARE_2_1_BUILD_9 */
-+firmware_struct Si2158_FW_2_1b9[] = {
-+		{ 8 , { 0x04,0x01,0x00,0x00,0x08,0x05,0xC0,0xC9 } },
-+		{ 8 , { 0x05,0x59,0x32,0xCC,0x7E,0xC3,0x44,0x59 } },
-+		{ 9 , { 0x30,0xF7,0x1A,0x64,0x2B,0x5D,0x3C,0xDC,0x31 } },
-+		{ 8 , { 0x05,0xED,0x7F,0xD4,0x82,0x46,0x77,0x2B } },
-+		{ 3 , { 0x4A,0xB1,0x1F } },
-+		{ 8 , { 0x05,0xFF,0x6D,0x48,0x94,0x99,0xDE,0x3C } },
-+		{ 3 , { 0x4A,0xAE,0x22 } },
-+		{ 8 , { 0x05,0x82,0xE1,0xEA,0x8D,0xBF,0xC5,0x60 } },
-+		{ 3 , { 0x42,0x5C,0x7B } },
-+		{ 8 , { 0x05,0x57,0x5C,0xB6,0x05,0x14,0x3F,0xB3 } },
-+		{ 16 , { 0x3F,0xA8,0xA8,0xFC,0xEE,0xA8,0x80,0xD9,0x0B,0x5C,0x1B,0xE9,0x79,0x2F,0xEF,0x47 } },
-+		{ 3 , { 0x4A,0x00,0x19 } },
-+		{ 8 , { 0x05,0x04,0x18,0x06,0xF0,0xAD,0x25,0xF8 } },
-+		{ 3 , { 0x42,0x71,0xBE } },
-+		{ 8 , { 0x05,0x57,0x16,0xEA,0x42,0xC3,0x42,0x59 } },
-+		{ 3 , { 0x42,0xD9,0x8D } },
-+		{ 8 , { 0x05,0x95,0xFA,0x37,0x21,0x80,0x85,0x77 } },
-+		{ 3 , { 0x42,0xE2,0x90 } },
-+		{ 8 , { 0x0F,0x49,0x8C,0x27,0xE9,0xD6,0x90,0xF2 } },
-+		{ 8 , { 0x07,0x78,0xF5,0x29,0x13,0x23,0x7A,0xF6 } },
-+		{ 8 , { 0x05,0xFF,0xDA,0xAF,0x0E,0x74,0x59,0xFB } },
-+		{ 3 , { 0x4A,0x3E,0x98 } },
-+		{ 8 , { 0x05,0xD8,0x18,0x5F,0x5A,0xEC,0x31,0xC0 } },
-+		{ 12 , { 0x33,0x5D,0xD6,0xFE,0x3C,0x39,0x21,0x69,0x1C,0x1A,0x3B,0x0F } },
-+		{ 8 , { 0x05,0x2A,0x3D,0x38,0x56,0xD6,0x2E,0x0B } },
-+		{ 3 , { 0x4A,0x23,0x4B } },
-+		{ 8 , { 0x05,0x7A,0x89,0x27,0x18,0x15,0x58,0xAA } },
-+		{ 6 , { 0x45,0x32,0x93,0x16,0xB2,0xB9 } },
-+		{ 8 , { 0x05,0x9B,0xEB,0x36,0x7E,0x4F,0x32,0x37 } },
-+		{ 3 , { 0x42,0x06,0x1F } },
-+		{ 8 , { 0x05,0xDB,0xEF,0x38,0xA7,0x63,0x6D,0x4E } },
-+		{ 6 , { 0x4D,0x72,0x68,0x95,0x2B,0xB0 } },
-+		{ 8 , { 0x05,0x93,0x29,0xC2,0x99,0xD1,0xB3,0x71 } },
-+		{ 6 , { 0x4D,0xFA,0xC2,0xDC,0xF3,0x60 } },
-+		{ 8 , { 0x05,0x6F,0x9A,0x59,0x5E,0x5C,0x38,0xF9 } },
-+		{ 3 , { 0x42,0xEE,0x30 } },
-+		{ 8 , { 0x07,0xFF,0x5B,0x93,0xA5,0xDF,0xBA,0xCA } },
-+		{ 8 , { 0x05,0xC1,0x43,0xB7,0xB6,0x4A,0x74,0xDF } },
-+		{ 3 , { 0x42,0x4E,0xF9 } },
-+		{ 8 , { 0x05,0x7A,0xF6,0xDF,0x17,0xED,0x5E,0x4D } },
-+		{ 3 , { 0x4A,0xD3,0xA5 } },
-+		{ 8 , { 0x05,0x08,0xA5,0xBE,0x9F,0x84,0xC2,0x9D } },
-+		{ 3 , { 0x4A,0x0C,0x97 } },
-+		{ 8 , { 0x05,0x1B,0xB3,0x3C,0x0E,0x65,0x0D,0x5C } },
-+		{ 12 , { 0x3B,0xC6,0xF3,0x1F,0x65,0xF2,0x7D,0x3D,0x0D,0xD9,0xA4,0x25 } },
-+		{ 8 , { 0x05,0x56,0x10,0x31,0x77,0xDC,0x0C,0xAB } },
-+		{ 3 , { 0x4A,0xAB,0x42 } },
-+		{ 8 , { 0x05,0xB6,0x64,0x3B,0x81,0xFA,0x98,0xB2 } },
-+		{ 3 , { 0x4A,0x54,0x52 } },
-+		{ 8 , { 0x0F,0xAF,0x20,0xE1,0xEB,0x09,0xC7,0x88 } },
-+		{ 16 , { 0x37,0x55,0x1C,0x23,0xF6,0xA8,0x09,0x99,0xA2,0x36,0xD9,0x6C,0xBC,0xE6,0xB3,0xBC } },
-+		{ 16 , { 0x37,0x8A,0xCF,0x6A,0x73,0xA7,0xF5,0x6E,0x7E,0x53,0xC5,0xF7,0x97,0x79,0x05,0xF3 } },
-+		{ 16 , { 0x3F,0x9B,0x16,0xF7,0xDE,0x7D,0xFD,0x7F,0xD6,0xA7,0x0A,0x28,0xCC,0x88,0xE0,0x4E } },
-+		{ 7 , { 0x46,0x7F,0xD9,0xA2,0x28,0xA9,0x40 } },
-+		{ 8 , { 0x0F,0x00,0xAB,0xD2,0xAC,0xAF,0x9C,0x12 } },
-+		{ 8 , { 0x07,0x08,0x66,0x92,0xE7,0x63,0xA0,0x77 } },
-+		{ 8 , { 0x07,0x0A,0x29,0x92,0x84,0x59,0x90,0x7C } },
-+		{ 16 , { 0x37,0x2B,0x17,0xC6,0xB6,0x17,0x58,0x21,0x98,0xB9,0x41,0xC8,0xBF,0x7D,0x7C,0x65 } },
-+		{ 16 , { 0x3F,0xDD,0x21,0x88,0x43,0x62,0x85,0x0A,0x99,0x69,0xD5,0x3F,0x06,0xFF,0x5A,0x7B } },
-+		{ 12 , { 0x33,0x10,0xE2,0x87,0x96,0xB9,0x26,0x78,0xF3,0x79,0x73,0xB6 } },
-+		{ 8 , { 0x07,0x0D,0x76,0xB0,0x4F,0xAD,0x99,0x59 } },
-+		{ 16 , { 0x3F,0x20,0x79,0xB8,0x2F,0x46,0x60,0x66,0x00,0x7C,0xE2,0x92,0x12,0x14,0x36,0xEE } },
-+		{ 16 , { 0x37,0xDF,0xBF,0x96,0x35,0xED,0xC5,0x62,0x20,0xE1,0xB9,0xB6,0xCE,0xDC,0x4E,0x71 } },
-+		{ 16 , { 0x3F,0xE9,0x1C,0x63,0xBE,0xE2,0x71,0xB4,0xC3,0xE4,0x1D,0xC6,0xA2,0xB3,0xAB,0xC8 } },
-+		{ 16 , { 0x37,0x02,0x54,0x92,0x51,0x8A,0x20,0xD2,0xD5,0x66,0xF0,0x17,0x72,0x9E,0x5D,0x3A } },
-+		{ 16 , { 0x37,0xDF,0x3E,0x72,0x35,0x31,0xA5,0x1C,0x81,0x6F,0xF9,0x93,0xF3,0x99,0xB2,0xE2 } },
-+		{ 16 , { 0x37,0x4D,0x18,0xA1,0xCE,0xD0,0x05,0x43,0x96,0x55,0x7A,0x62,0xF6,0xB6,0xBB,0x55 } },
-+		{ 16 , { 0x3F,0xF5,0xFD,0x0D,0x3D,0x5F,0xE4,0xFE,0x5F,0x8A,0xC4,0x7B,0x96,0xA9,0xE1,0xD4 } },
-+		{ 8 , { 0x07,0x91,0x26,0x16,0x6D,0x15,0x18,0xB6 } },
-+		{ 12 , { 0x3B,0x09,0x7A,0xB4,0x74,0x5E,0x73,0x35,0xCE,0x52,0xC0,0xD5 } },
-+		{ 8 , { 0x07,0xD3,0xA3,0x50,0xE8,0x7A,0xEE,0xCB } },
-+		{ 10 , { 0x31,0xFB,0xF8,0x05,0xA5,0x5D,0x46,0xEB,0xB2,0xC5 } },
-+		{ 8 , { 0x0F,0xD7,0xAE,0xE2,0x18,0x26,0x1C,0x84 } },
-+		{ 3 , { 0x42,0x96,0xC2 } },
-+		{ 8 , { 0x0F,0x6B,0xB4,0xA7,0xB2,0x2C,0x56,0xE3 } },
-+		{ 8 , { 0x0F,0xC1,0xAF,0xB7,0xAC,0xB3,0x47,0x02 } },
-+		{ 8 , { 0x0F,0x75,0x59,0xD9,0xB0,0x1F,0xD8,0xFE } },
-+		{ 15 , { 0x36,0xED,0x5A,0x41,0xC2,0xB1,0x1E,0xF7,0x21,0x05,0xA2,0x44,0xF6,0x34,0x97 } },
-+		{ 8 , { 0x07,0x2D,0xAB,0x62,0xD9,0x1E,0x8C,0x5E } },
-+		{ 16 , { 0x3F,0x44,0x2C,0xE8,0x20,0xC7,0x20,0x8C,0x05,0x89,0xBC,0xA7,0x20,0xDE,0xBB,0xA3 } },
-+		{ 12 , { 0x3B,0x6E,0x7B,0x57,0x4E,0xF8,0x00,0xAB,0x2E,0xB3,0xB9,0x17 } },
-+		{ 8 , { 0x0F,0x5E,0x5B,0x43,0x88,0x57,0xA3,0x93 } },
-+		{ 16 , { 0x37,0xDA,0xD7,0xC0,0x3A,0xE0,0x63,0x35,0x32,0x67,0x4D,0x27,0x7D,0x23,0x50,0x4A } },
-+		{ 3 , { 0x42,0xB8,0xCC } },
-+		{ 8 , { 0x0F,0x7D,0x55,0xDB,0x19,0x4B,0x63,0x53 } },
-+		{ 8 , { 0x0F,0xB3,0x50,0xE5,0x34,0xD5,0x99,0x5F } },
-+		{ 9 , { 0x30,0x7B,0xE5,0xDB,0x63,0xA8,0xAD,0xEE,0x27 } },
-+		{ 8 , { 0x0F,0xCE,0xD5,0x78,0x5B,0xAF,0xFE,0x43 } },
-+		{ 8 , { 0x0F,0x32,0x32,0x7C,0xFA,0x38,0xED,0x1C } },
-+		{ 8 , { 0x0F,0x99,0x8A,0x79,0x24,0xE4,0xFC,0xE4 } },
-+		{ 8 , { 0x07,0x7D,0xE3,0x78,0x64,0x19,0xD2,0x63 } },
-+		{ 16 , { 0x3F,0xD9,0xE8,0x39,0x61,0x0D,0xC1,0x4A,0x47,0x9A,0x0B,0xEE,0xCF,0xC4,0xB9,0xB0 } },
-+		{ 3 , { 0x4A,0x4B,0x42 } },
-+		{ 8 , { 0x07,0x00,0x0A,0x54,0xAD,0x5B,0x3B,0xDD } },
-+		{ 16 , { 0x3F,0xF8,0x79,0xD7,0xE8,0xF7,0xD8,0xC1,0xA9,0x78,0xED,0x03,0xAD,0x8F,0x09,0xC1 } },
-+		{ 9 , { 0x30,0x0B,0x4B,0x0E,0x27,0xAE,0x5B,0x01,0x5E } },
-+		{ 8 , { 0x0F,0xC4,0x6F,0x0A,0xC5,0x6C,0x7F,0x18 } },
-+		{ 16 , { 0x3F,0xC5,0x7F,0xAA,0x23,0x11,0xB2,0xDA,0x20,0xD7,0x1E,0x3B,0xF2,0x67,0x62,0x43 } },
-+		{ 16 , { 0x37,0xA7,0x7B,0x4F,0x8E,0x2D,0xC7,0x9F,0x66,0x4B,0x6F,0xC2,0x72,0x4F,0xAB,0x1B } },
-+		{ 16 , { 0x37,0x80,0x9B,0x79,0xB2,0xE8,0x00,0x0D,0xCB,0x7F,0xD4,0x01,0x32,0xAC,0x03,0xA0 } },
-+		{ 16 , { 0x37,0x14,0x0E,0x27,0x29,0x16,0x5D,0x97,0x9F,0x48,0x83,0x66,0x37,0x0D,0x6D,0xCB } },
-+		{ 16 , { 0x3F,0x7F,0xEE,0xC5,0x93,0x7C,0xF9,0xAE,0xA5,0x17,0xA0,0xB4,0x31,0x5C,0xBD,0x7C } },
-+		{ 16 , { 0x37,0xF0,0x48,0xCE,0xB7,0xB2,0x20,0x7C,0x58,0x7E,0xAA,0x36,0x50,0xA3,0x36,0x8B } },
-+		{ 9 , { 0x38,0x5E,0x8A,0xAC,0x3F,0x65,0x82,0xA8,0xD6 } },
-+		{ 8 , { 0x0F,0x9B,0x94,0x3C,0x30,0x23,0x73,0x79 } },
-+		{ 16 , { 0x37,0x02,0xEB,0xC2,0x5E,0xF9,0xB2,0x3D,0xED,0xAD,0xDC,0x28,0x15,0x02,0x4E,0x2B } },
-+		{ 16 , { 0x37,0x35,0xC0,0xD5,0xA9,0x5F,0x1D,0xFD,0x16,0xEF,0xF6,0x92,0x46,0xEB,0x08,0x4C } },
-+		{ 10 , { 0x39,0xE1,0x0B,0xF4,0xC4,0x90,0x76,0xE2,0x57,0x4B } },
-+		{ 8 , { 0x07,0x2B,0x61,0x0B,0xAB,0x49,0x56,0x7F } },
-+		{ 16 , { 0x37,0xED,0x94,0xCB,0x5A,0x80,0x7C,0x35,0x1C,0xA2,0xE9,0x20,0xAD,0xAB,0x40,0x09 } },
-+		{ 16 , { 0x37,0x04,0x38,0x28,0x6D,0xCF,0x96,0x1E,0x3A,0x0F,0x42,0xF8,0x19,0xC2,0x89,0x2E } },
-+		{ 16 , { 0x3F,0x70,0x87,0x81,0xB3,0xA9,0x68,0x5C,0x23,0xDB,0x06,0x58,0x54,0xAC,0xF5,0x45 } },
-+		{ 16 , { 0x3F,0xDD,0x6C,0x6D,0xF0,0xDB,0x03,0x18,0x59,0x4F,0xFC,0x3C,0x13,0x91,0x57,0x20 } },
-+		{ 16 , { 0x3F,0xAD,0xDA,0xD9,0xD2,0xBB,0xF3,0x2D,0xF6,0x04,0xA5,0xBB,0x8C,0x80,0xF1,0xC9 } },
-+		{ 16 , { 0x37,0x70,0xF0,0xC6,0xD3,0xD3,0xA7,0x31,0x42,0xF3,0xB3,0x16,0xD1,0x86,0x24,0xFE } },
-+		{ 16 , { 0x3F,0xB8,0x07,0xEC,0xEA,0x3E,0x4D,0xEF,0x93,0xB2,0xD7,0x52,0xD2,0xA9,0x4D,0xF4 } },
-+		{ 16 , { 0x3F,0x97,0x07,0x2E,0xE9,0xD3,0x53,0x8D,0xF0,0xF7,0xBD,0x65,0x7F,0xAE,0x82,0xAD } },
-+		{ 10 , { 0x39,0xF3,0x0E,0xD4,0x4A,0xE3,0x88,0x36,0x3F,0xB3 } },
-+		{ 8 , { 0x07,0xBC,0x8A,0x76,0xEA,0x6E,0x16,0x55 } },
-+		{ 16 , { 0x37,0xD6,0xE1,0x5A,0xFE,0x2D,0x0F,0x07,0x26,0x2E,0x30,0xA1,0x02,0xFD,0xD9,0xCC } },
-+		{ 16 , { 0x3F,0xDC,0x2E,0xE1,0xA4,0x8D,0x91,0x56,0xC2,0xF7,0xAB,0xEF,0x50,0x3F,0x71,0xEF } },
-+		{ 4 , { 0x4B,0x7F,0x97,0x0A } },
-+		{ 8 , { 0x0F,0x7B,0x28,0x01,0x3B,0xA0,0x15,0xAA } },
-+		{ 16 , { 0x37,0xAB,0x0A,0xD2,0x4E,0x5D,0x71,0xC3,0x65,0xA5,0x4B,0x1D,0xFF,0xF2,0x67,0x58 } },
-+		{ 6 , { 0x45,0x0E,0x64,0xB4,0x06,0xA4 } },
-+		{ 8 , { 0x07,0x92,0xA7,0x51,0x55,0x92,0xF0,0xF4 } },
-+		{ 8 , { 0x0F,0x0F,0x14,0x76,0x79,0x5C,0x1D,0xE7 } },
-+		{ 8 , { 0x0F,0x2E,0xDC,0xEB,0x45,0x2A,0xA1,0xAF } },
-+		{ 9 , { 0x30,0xC0,0xDA,0xA2,0x98,0xAE,0x47,0xD7,0x1E } },
-+		{ 8 , { 0x0F,0xAF,0x3B,0xFE,0x7A,0xD8,0x27,0x45 } },
-+		{ 13 , { 0x34,0x85,0x34,0x05,0x7A,0xDA,0x80,0xE0,0x1B,0x03,0x46,0xF1,0x91 } },
-+		{ 8 , { 0x0F,0x87,0xB3,0xE8,0x64,0xF0,0x3F,0x6C } },
-+		{ 8 , { 0x07,0x48,0xA9,0x0B,0xBB,0xDB,0x96,0xC4 } },
-+		{ 8 , { 0x07,0xCD,0x13,0x81,0xDA,0xAF,0x30,0x57 } },
-+		{ 8 , { 0x0F,0xA8,0xC5,0x94,0xCC,0x87,0xD6,0xF0 } },
-+		{ 8 , { 0x0F,0x93,0xAA,0x67,0xC2,0x6D,0x41,0x07 } },
-+		{ 8 , { 0x07,0x74,0x00,0x38,0xBD,0x3C,0x36,0xEB } },
-+		{ 8 , { 0x07,0xB1,0x1D,0x97,0x83,0x96,0xCC,0xBC } },
-+		{ 16 , { 0x37,0xD7,0xCC,0xCD,0x2B,0x64,0x65,0x0E,0x4F,0x17,0x63,0xDE,0x8A,0xBD,0xB8,0xEF } },
-+		{ 16 , { 0x3F,0x60,0x84,0x7E,0x13,0x7E,0xFB,0xCC,0xBF,0x1D,0x64,0x07,0x01,0xE9,0x2C,0xFF } },
-+		{ 16 , { 0x3F,0xE9,0x51,0x42,0x62,0x9E,0xBC,0xD7,0x4D,0xD1,0xF6,0x83,0x3E,0xA7,0x77,0xA7 } },
-+		{ 3 , { 0x42,0x54,0xB2 } },
-+		{ 8 , { 0x0F,0x86,0xB5,0x33,0xCD,0x1A,0xAB,0x1C } },
-+		{ 8 , { 0x07,0x83,0xBA,0xAC,0xCE,0xC0,0xCC,0xF7 } },
-+		{ 8 , { 0x0F,0x89,0x1B,0x32,0xA4,0x56,0x8E,0x09 } },
-+		{ 16 , { 0x3F,0x11,0xFE,0xC2,0x5D,0x6B,0xD3,0x98,0xEC,0xB7,0x7B,0x93,0x49,0x6C,0x6A,0x34 } },
-+		{ 16 , { 0x37,0xCC,0x63,0xA8,0x32,0x4C,0xCE,0x8B,0xD9,0x68,0xDD,0xB3,0xBB,0x33,0xFB,0x67 } },
-+		{ 16 , { 0x3F,0x31,0x5C,0x89,0x74,0x6B,0xAC,0xBE,0xA6,0xAF,0xBD,0xC7,0x65,0x5C,0x67,0x65 } },
-+		{ 2 , { 0x41,0x55 } },
-+		{ 8 , { 0x0F,0xE7,0xF0,0xD9,0xFC,0xB7,0xC9,0xC5 } },
-+		{ 16 , { 0x3F,0x70,0xB5,0x33,0x10,0xDF,0xAE,0x71,0x6A,0xBF,0x2D,0x7A,0xAC,0xC0,0xC2,0x38 } },
-+		{ 16 , { 0x37,0x44,0x81,0xE0,0xD2,0x7D,0xB6,0xF9,0xB3,0x94,0x7A,0x95,0xBE,0x91,0x00,0x92 } },
-+		{ 6 , { 0x45,0x2C,0xA4,0x61,0xF8,0x79 } },
-+		{ 8 , { 0x0F,0xC2,0x7C,0x4C,0x82,0xFB,0x57,0x63 } },
-+		{ 8 , { 0x07,0xEB,0x27,0xB7,0x95,0x55,0x22,0x02 } },
-+		{ 8 , { 0x07,0x1F,0xEA,0xD4,0x5F,0x5A,0x3D,0xE5 } },
-+		{ 8 , { 0x4F,0xD8,0xBC,0x2C,0x62,0xC2,0xC7,0x1D } },
-+		{ 8 , { 0x07,0x55,0x7A,0xD3,0xA8,0x31,0x9A,0x92 } },
-+		{ 11 , { 0x32,0x95,0x47,0x7E,0x9D,0x12,0xC4,0xFE,0x5E,0x2B,0x5D } },
-+		{ 8 , { 0x0F,0x7A,0xA6,0x31,0xC2,0xC2,0x52,0x63 } },
-+		{ 16 , { 0x3F,0xCB,0xC6,0x22,0xE7,0xC3,0xCA,0xCA,0xA2,0x33,0xEA,0xC0,0xFD,0x40,0xCE,0x76 } },
-+		{ 16 , { 0x3F,0x60,0x2B,0x04,0x87,0xD1,0x17,0x3E,0x57,0xE1,0x28,0xCC,0x7E,0x5D,0x5E,0xEE } },
-+		{ 16 , { 0x3F,0xEE,0xCC,0x45,0xED,0x18,0x92,0x8E,0xE7,0xDC,0x1D,0x1F,0xFB,0xF5,0x23,0x44 } },
-+		{ 4 , { 0x4B,0x8E,0x7C,0xA3 } },
-+		{ 8 , { 0x07,0x23,0x2F,0xA5,0x62,0xB1,0xD3,0x85 } },
-+		{ 8 , { 0x07,0x6F,0xAE,0x2E,0xED,0x4E,0xC5,0x51 } },
-+		{ 16 , { 0x37,0xF2,0x33,0x90,0x26,0xE1,0x48,0x1C,0x4D,0x77,0xAD,0x41,0x72,0x2E,0x80,0x06 } },
-+		{ 16 , { 0x37,0xD9,0x7E,0xDC,0x74,0xBC,0xC1,0xFC,0xFE,0xF3,0x12,0x3C,0x2B,0xF5,0x7E,0x21 } },
-+		{ 12 , { 0x33,0xD2,0xDA,0x26,0x98,0x28,0x95,0x23,0x7C,0x85,0x3F,0xD3 } },
-+		{ 8 , { 0x0F,0x5B,0x43,0xFF,0x3C,0x0A,0x38,0x24 } },
-+		{ 8 , { 0x07,0x9C,0xC0,0x34,0x66,0x43,0x2D,0x26 } },
-+		{ 12 , { 0x3B,0x84,0xCC,0xF9,0x4F,0x03,0xC3,0x79,0xDB,0x56,0x3E,0x23 } },
-+		{ 8 , { 0x07,0x3D,0xE8,0x69,0x5F,0x05,0x8D,0x2D } },
-+		{ 16 , { 0x37,0x5C,0xD7,0x1A,0xEA,0x7C,0xE8,0x98,0x7B,0xDA,0x93,0x68,0x00,0xAA,0xCC,0x4D } },
-+		{ 6 , { 0x4D,0x54,0x4D,0xDC,0x5A,0x72 } },
-+		{ 8 , { 0x0F,0x5A,0x8B,0x3B,0xD4,0xDD,0x23,0x1E } },
-+		{ 8 , { 0x0F,0xE0,0xEB,0x8F,0x29,0x1D,0x59,0x8B } },
-+		{ 16 , { 0x37,0xB7,0x0E,0x77,0xFC,0xAC,0x44,0x58,0xA1,0xC7,0x8A,0xE0,0x69,0x1E,0x42,0xD6 } },
-+		{ 16 , { 0x3F,0x92,0xD4,0x52,0xBB,0x2B,0xA3,0xD0,0xEB,0x09,0x7B,0xD4,0x50,0xD5,0x65,0xEA } },
-+		{ 16 , { 0x3F,0x2F,0xC9,0x00,0x87,0xD8,0x52,0xC3,0x56,0x9E,0x4B,0xD5,0xE3,0xF9,0x44,0x63 } },
-+		{ 5 , { 0x44,0x55,0x2A,0x42,0x85 } },
-+		{ 8 , { 0x07,0xA4,0xAA,0x4F,0xAA,0x8F,0xE2,0x55 } },
-+		{ 16 , { 0x3F,0x8C,0x80,0x2D,0x17,0x7C,0x9F,0x28,0xA4,0x02,0x78,0x20,0x10,0xC4,0x2F,0x37 } },
-+		{ 8 , { 0x4F,0x64,0x61,0x54,0x6D,0x01,0xB5,0x03 } },
-+		{ 8 , { 0x07,0xC4,0xDB,0x5D,0x0D,0x38,0x9E,0x9A } },
-+		{ 8 , { 0x07,0x54,0xC6,0xA9,0x5A,0x9A,0xFA,0xDB } },
-+		{ 8 , { 0x07,0x65,0xC4,0xC3,0xDE,0xDB,0x48,0xEE } },
-+		{ 8 , { 0x07,0xBE,0x09,0x79,0x96,0x93,0x88,0x2C } },
-+		{ 8 , { 0x0F,0x6B,0xC2,0xF7,0x6B,0x03,0xEE,0x62 } },
-+		{ 8 , { 0x07,0x97,0x44,0x7A,0x49,0x06,0xE5,0x29 } },
-+		{ 16 , { 0x3F,0x9F,0x17,0xBD,0xEC,0x56,0x21,0x32,0x74,0xBA,0x2E,0xE1,0x23,0x4A,0x90,0x06 } },
-+		{ 3 , { 0x4A,0xD3,0xF0 } },
-+		{ 8 , { 0x0F,0x84,0x98,0xC8,0x34,0x61,0x8D,0xC4 } },
-+		{ 7 , { 0x46,0x7E,0x08,0xD7,0x14,0x64,0xD9 } },
-+		{ 8 , { 0x07,0xBF,0x74,0xC3,0xA3,0x8D,0xEF,0xC5 } },
-+		{ 16 , { 0x3F,0x05,0x3D,0x45,0x36,0xB1,0xEF,0x45,0x06,0xCF,0x28,0xE4,0x0F,0xB3,0x6E,0x84 } },
-+		{ 16 , { 0x37,0x89,0xB5,0x8F,0x8C,0x33,0x8E,0x47,0x24,0x56,0xC0,0x96,0x2C,0x05,0x77,0x68 } },
-+		{ 4 , { 0x4B,0x60,0x96,0xD6 } },
-+		{ 8 , { 0x0F,0x76,0xBB,0x4D,0xAE,0x16,0xB4,0xCC } },
-+		{ 16 , { 0x3F,0x7A,0x5E,0x8D,0x26,0x07,0x70,0xB8,0x20,0xB0,0x70,0xB7,0x8D,0x67,0x08,0xEE } },
-+		{ 16 , { 0x3F,0x96,0x11,0x7D,0x07,0x4B,0xB7,0xAB,0xB9,0xA1,0x5D,0x71,0x91,0x2F,0xD8,0x45 } },
-+		{ 16 , { 0x3F,0xBF,0x43,0x9A,0xC9,0x6F,0x59,0xA8,0x42,0x8D,0xB7,0x03,0x7F,0xCC,0x10,0xEF } },
-+		{ 8 , { 0x0F,0x08,0xB2,0xB3,0x2D,0xE0,0x4B,0x03 } },
-+		{ 16 , { 0x37,0xFB,0x41,0x38,0x34,0xF1,0x67,0x80,0x51,0x74,0xEE,0x95,0x9C,0xF2,0x5C,0x83 } },
-+		{ 16 , { 0x37,0x2F,0xDC,0x23,0x04,0x18,0xDB,0x5E,0x45,0xD9,0x82,0x52,0x44,0x84,0xA8,0x52 } },
-+		{ 16 , { 0x3F,0xFE,0x4A,0xA1,0xC7,0x55,0xEB,0x52,0xB9,0xA2,0xF3,0xFC,0xD2,0xFF,0x68,0xDD } },
-+		{ 16 , { 0x3F,0xDB,0x99,0xB0,0x4C,0x7A,0xC3,0x2C,0xDD,0xE1,0x98,0x4E,0x1A,0x11,0xC4,0x5C } },
-+		{ 16 , { 0x37,0x05,0xF2,0x5C,0x8C,0x7D,0x3D,0x42,0x1A,0xBF,0x6A,0xAE,0x9B,0xB6,0x25,0xF0 } },
-+		{ 7 , { 0x4E,0xCD,0x41,0x82,0xBA,0x1B,0xBA } },
-+		{ 8 , { 0x07,0x04,0xE8,0xFB,0x55,0xFE,0x6A,0x55 } },
-+		{ 12 , { 0x33,0x2A,0x4A,0xF1,0xE7,0xC5,0x57,0xBC,0xD2,0x91,0x95,0xF6 } },
-+		{ 8 , { 0x0F,0x04,0x90,0xC5,0x1A,0xC8,0x16,0xC1 } },
-+		{ 15 , { 0x36,0x3A,0x76,0x53,0x18,0x92,0x0B,0xAB,0x8F,0xB7,0x7F,0x29,0xC8,0xB0,0x7F } },
-+		{ 8 , { 0x07,0x6D,0xD7,0x8B,0xD8,0xB3,0x0D,0xAE } },
-+		{ 8 , { 0x0F,0x72,0xA3,0xDE,0x53,0x0D,0x04,0x91 } },
-+		{ 16 , { 0x37,0x36,0xB9,0xEC,0x73,0x12,0xB2,0x78,0xC4,0x4C,0x57,0xDA,0x05,0xE1,0x4F,0xA4 } },
-+		{ 16 , { 0x3F,0x12,0x5F,0x23,0xFC,0x93,0x7C,0x1D,0x13,0xF5,0x74,0xFC,0x88,0x9F,0x35,0x4E } },
-+		{ 16 , { 0x37,0xD7,0xAA,0x39,0xD0,0x73,0xFB,0x1F,0xB7,0xF3,0x45,0x0C,0x69,0x42,0x20,0x35 } },
-+		{ 16 , { 0x37,0x6C,0x9E,0xED,0x31,0x9E,0x8C,0xE5,0x22,0x4B,0x08,0x4D,0x0C,0xA3,0x7D,0xCF } },
-+		{ 16 , { 0x37,0x24,0xF7,0x9D,0xEE,0xCA,0xCE,0x02,0x9A,0xA2,0x53,0xAF,0x96,0x0E,0xBB,0x7E } },
-+		{ 16 , { 0x3F,0xDF,0xE0,0xE9,0xA7,0x54,0xB8,0x79,0x19,0xB2,0x05,0x30,0x7A,0x36,0x4A,0xF5 } },
-+		{ 16 , { 0x3F,0xB8,0x24,0x96,0x76,0xF9,0x55,0x0C,0x1D,0xCA,0x9E,0xD2,0x6F,0xD5,0xBB,0xEF } },
-+		{ 16 , { 0x37,0x00,0xC5,0xB5,0x31,0xB4,0x1C,0x1D,0xAD,0xE8,0x62,0xEA,0x04,0x66,0x19,0x35 } },
-+		{ 16 , { 0x3F,0xF0,0x6F,0x48,0x7A,0xE9,0x89,0xB9,0xB8,0x8B,0x36,0x1F,0xC9,0x36,0xC6,0x4C } },
-+		{ 12 , { 0x33,0xA7,0x21,0x01,0x2E,0x0E,0xAE,0x0F,0xCB,0xEF,0x4C,0x1C } },
-+		{ 8 , { 0x0F,0x0A,0x61,0x64,0x6E,0xB5,0x87,0xEA } },
-+		{ 16 , { 0x3F,0x48,0x99,0x69,0xB0,0x30,0x44,0xCA,0xF3,0x64,0x46,0x4A,0xD8,0x0A,0xA9,0xBA } },
-+		{ 3 , { 0x42,0x89,0x21 } },
-+		{ 8 , { 0x0F,0x30,0x66,0x77,0x60,0x58,0x89,0x2E } },
-+		{ 9 , { 0x30,0x4E,0x53,0xDA,0xD5,0x3C,0x1C,0xD4,0xD1 } },
-+		{ 8 , { 0x07,0xF9,0x3A,0x4B,0x50,0x92,0x63,0x2E } },
-+		{ 16 , { 0x3F,0x0F,0x1A,0x48,0x7C,0x81,0x60,0x76,0xEA,0x3F,0x64,0xF5,0x81,0xD5,0x02,0x1D } },
-+		{ 16 , { 0x37,0x45,0x0C,0xAD,0x74,0x7C,0x34,0x4C,0x33,0x42,0xCC,0xC1,0xBC,0x93,0x3A,0xC2 } },
-+		{ 16 , { 0x3F,0xED,0x96,0x5A,0x20,0x7A,0x04,0x41,0xD3,0x16,0x61,0x46,0xD7,0xEF,0xF8,0x6C } },
-+		{ 8 , { 0x47,0xBB,0x80,0x07,0x48,0x7F,0x26,0xBA } },
-+		{ 8 , { 0x0F,0x3D,0xDF,0x9C,0x27,0x6B,0x13,0x14 } },
-+		{ 16 , { 0x3F,0x6B,0xBA,0x51,0xB6,0xA1,0xD6,0x9D,0xA9,0x49,0x85,0x2C,0xF6,0x17,0xAD,0xF6 } },
-+		{ 16 , { 0x37,0x1F,0x00,0x69,0xC5,0x3C,0xD7,0xA1,0xF3,0x45,0x4E,0x72,0xFE,0x86,0x3E,0x2A } },
-+		{ 15 , { 0x3E,0x85,0x16,0x3F,0xE3,0xE5,0xE4,0xB0,0xD7,0xB0,0xB5,0x41,0x62,0x66,0x3E } },
-+		{ 8 , { 0x07,0xCC,0xBA,0xDA,0xE6,0xEF,0xAC,0x96 } },
-+		{ 16 , { 0x3F,0x24,0x1D,0xBE,0xE5,0xF8,0xB4,0x88,0x63,0xBE,0x1E,0xCC,0xD7,0x17,0x21,0xEB } },
-+		{ 5 , { 0x44,0x9C,0x91,0x1A,0x0A } },
-+		{ 8 , { 0x0F,0x17,0x67,0x37,0xBF,0x99,0xA8,0x7E } },
-+		{ 8 , { 0x07,0xF7,0x1C,0x25,0x05,0x0F,0x66,0xE5 } },
-+		{ 11 , { 0x3A,0xD9,0xA1,0x29,0x9A,0x4E,0xCB,0xC5,0xF9,0x04,0xA9 } },
-+		{ 8 , { 0x07,0x04,0x2E,0x50,0xD3,0x86,0x71,0xFB } },
-+		{ 8 , { 0x07,0x47,0xB0,0xC1,0x3D,0x76,0x30,0xFA } },
-+		{ 10 , { 0x39,0xEA,0xD0,0xAE,0xBC,0x00,0x7D,0x09,0x0D,0x3B } },
-+		{ 8 , { 0x0F,0x2D,0x39,0x28,0x73,0xB9,0x70,0x02 } },
-+		{ 8 , { 0x07,0x59,0x65,0x65,0x56,0x52,0x86,0xAD } },
-+		{ 8 , { 0x07,0x73,0xFA,0xF9,0x93,0x24,0x5B,0x05 } },
-+		{ 8 , { 0x07,0x6E,0x23,0xDC,0x21,0xC8,0x71,0x29 } },
-+		{ 8 , { 0x07,0x51,0x32,0x7A,0x79,0x60,0x2A,0xD7 } },
-+		{ 8 , { 0x07,0x15,0x45,0xCE,0x84,0xB1,0x5C,0x3D } },
-+		{ 8 , { 0x0F,0x91,0x48,0xCA,0x5F,0xFB,0x50,0xAE } },
-+		{ 8 , { 0x0F,0xB0,0xCB,0xD6,0x4C,0xB4,0x13,0xCE } },
-+		{ 8 , { 0x0F,0x21,0xED,0x0A,0x49,0xC0,0x81,0xC9 } },
-+		{ 8 , { 0x07,0x2D,0x97,0x99,0x2F,0x65,0xC3,0x9A } },
-+		{ 8 , { 0x05,0xC3,0xB3,0x23,0x81,0x31,0x79,0x84 } },
-+		{ 16 , { 0x37,0x86,0xDD,0x4B,0x34,0x71,0x62,0x4B,0xD5,0x26,0x5A,0xD9,0x5A,0x7D,0xDC,0x6B } },
-+		{ 16 , { 0x37,0x9B,0x88,0xDA,0xD9,0x62,0x3B,0xBA,0x02,0x4C,0x60,0xCB,0x46,0x31,0x2E,0x6B } },
-+		{ 16 , { 0x3F,0x33,0x45,0x16,0xD9,0xB2,0x21,0x3A,0x37,0x2A,0x8F,0x77,0x01,0x46,0xC1,0xE5 } },
-+		{ 16 , { 0x37,0xCC,0xF7,0x27,0x47,0x9B,0xF5,0x62,0x31,0xDF,0x30,0xC3,0x79,0x69,0x50,0xDF } },
-+		{ 16 , { 0x37,0x94,0x9E,0x56,0x65,0x1E,0x42,0xD3,0xE1,0x21,0x5C,0xEB,0x7D,0xD4,0x3F,0x10 } },
-+		{ 16 , { 0x3F,0x32,0x8B,0xBA,0xB6,0xAF,0x76,0xCC,0x13,0xD4,0xE7,0x32,0x3B,0x1E,0xAF,0xA0 } },
-+		{ 5 , { 0x4C,0x8B,0x97,0x95,0x3A } },
-+		{ 8 , { 0x0F,0x6A,0x37,0xDD,0x72,0x2C,0x3B,0x34 } },
-+		{ 16 , { 0x3F,0xAC,0xA0,0x8F,0x8B,0x02,0x16,0x77,0x6A,0xD6,0x31,0x5A,0x2A,0x9A,0xFA,0x7F } },
-+		{ 2 , { 0x41,0xA3 } },
-+		{ 8 , { 0x07,0xB7,0x7A,0xDB,0x23,0x6A,0x87,0xCF } },
-+		{ 8 , { 0x4F,0xB6,0xD9,0x2F,0x8A,0xDD,0x57,0x97 } },
-+		{ 8 , { 0x07,0xFD,0x54,0x4A,0x13,0x07,0x46,0xEA } },
-+		{ 8 , { 0x0F,0x05,0x4F,0x89,0xB2,0xDD,0xC8,0xA4 } },
-+		{ 16 , { 0x37,0xE4,0x8C,0xB2,0x7E,0x33,0x42,0x3A,0x69,0x75,0xB2,0xA3,0x4D,0x67,0x0F,0x38 } },
-+		{ 11 , { 0x3A,0x03,0xD7,0xA8,0x84,0xB3,0x82,0x94,0xA5,0x67,0xD9 } },
-+		{ 8 , { 0x05,0xD7,0xE7,0x4F,0x86,0x59,0x2E,0x5C } },
-+		{ 5 , { 0x44,0xF9,0xDF,0xCF,0x34 } },
-+		{ 8 , { 0x07,0x32,0x60,0x69,0xF9,0xA1,0xA4,0x36 } },
-+		{ 8 , { 0x05,0x38,0xB2,0xB2,0x87,0xE6,0xEF,0x0D } },
-+		{ 3 , { 0x4A,0x7F,0x84 } },
-+		{ 8 , { 0x07,0xB4,0xB0,0xA1,0xDD,0xED,0xAD,0x9E } },
-+		{ 8 , { 0x0F,0x28,0xA0,0xA7,0x2A,0xA5,0x91,0x03 } },
-+		{ 8 , { 0x0F,0xC1,0x6B,0x5C,0xB1,0x38,0x12,0x92 } },
-+		{ 8 , { 0x07,0x05,0x68,0x27,0x1D,0xED,0x33,0x4D } },
-+		{ 8 , { 0x05,0xAF,0x64,0x15,0x9B,0x1B,0x92,0x56 } },
-+		{ 3 , { 0x42,0x49,0x6A } },
-+		{ 8 , { 0x07,0x29,0x89,0x48,0xD7,0xD1,0x07,0x0D } },
-+		{ 8 , { 0x05,0x34,0x2E,0x9E,0xFF,0x87,0x0C,0xDE } },
-+		{ 3 , { 0x42,0xC6,0xCA } },
-+		{ 8 , { 0x05,0xF3,0xD2,0xBD,0xE6,0xEF,0x3B,0x23 } },
-+		{ 3 , { 0x4A,0xFE,0xB0 } },
-+		{ 8 , { 0x05,0x84,0x37,0xAF,0x14,0x4D,0x11,0x6F } },
-+		{ 4 , { 0x4B,0x09,0xD5,0x2D } },
-+		{ 8 , { 0x07,0xF8,0x5F,0xAD,0x4F,0x58,0x6B,0xC6 } },
-+		{ 8 , { 0x05,0x57,0x0A,0x23,0xD6,0x3F,0x5B,0x14 } }
-+};
-+
-+#define FIRMWARE_LINES_2_1b9 (sizeof(Si2158_FW_2_1b9)/(sizeof(firmware_struct)))
-+#define RAM_CRC_2_1b9 0x16F7
-+
-+/***************************************************************************************
-+                  Silicon Laboratories Broadcast Si2157  API
-+   FILE: Si2177_firmware_3_0_build_x.h
-+   Supported IC : Si2157
-+   Date: August 22 2013
-+   (C) Copyright 2012, Silicon Laboratories, Inc. All rights reserved.
-+
-+   This is a dummy firmware patch for Si2177-A30 devices.
-+   When a new patch becomes available,  replace this file and all calls to it with the new patch.
-+   This patch is formatted in the new 16 byte download format.  The future patches will match this structure.
-+ ****************************************************************************************/
-+/* Si2177_FIRMWARE_3_0_BUILD_X */
-+
-+firmware_struct Si2177_FW_3_0bx[] = {
-+		{ 0 , { 0x00} }
-+};
-+
-+#define FIRMWARE_LINES_3_0bx (sizeof(Si2177_FW_3_0bx)/(sizeof(firmware_struct)))
-+
-+#endif /* __SILABS_TERCAB_PRIV_H__ */
---- linux-4.15/drivers/media/tuners/tuner-types.c.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/tuners/tuner-types.c	2018-02-12 11:32:52.773582217 +0100
-@@ -1433,6 +1433,16 @@ static struct tuner_params tuner_sony_bt
- 	},
- };
- 
-+/* ------------ TUNER_SILABS_TERCAB - Si2157 NTSC ------------ */
-+
-+static struct tuner_params tuner_silabs_tercab_params[] = {
-+	{
-+		.type   = TUNER_PARAM_TYPE_DIGITAL,
-+		.ranges = tuner_fm1236_mk3_ntsc_ranges,
-+		.count  = ARRAY_SIZE(tuner_fm1236_mk3_ntsc_ranges),
-+	},
-+};
-+
- /* --------------------------------------------------------------------- */
- 
- struct tunertype tuners[] = {
-@@ -1941,6 +1951,11 @@ struct tunertype tuners[] = {
- 		.params = tuner_sony_btf_pg463z_params,
- 		.count  = ARRAY_SIZE(tuner_sony_btf_pg463z_params),
- 	},
-+	[TUNER_SILABS_TERCAB] = {
-+		.name   = "Silicon Labs terrestrial/cable multistandard",
-+		.params = tuner_silabs_tercab_params,
-+		.count  = ARRAY_SIZE(tuner_silabs_tercab_params),
-+	},
- };
- EXPORT_SYMBOL(tuners);
- 
---- linux-4.15/drivers/media/usb/cx231xx/cx231xx-avcore.c.0140~	2018-02-12 11:32:52.017576679 +0100
-+++ linux-4.15/drivers/media/usb/cx231xx/cx231xx-avcore.c	2018-02-12 11:32:52.774582224 +0100
-@@ -355,6 +355,9 @@ int cx231xx_afe_update_power_control(str
- 	case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
- 	case CX231XX_BOARD_HAUPPAUGE_EXETER:
- 	case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx:
-+	case CX231XX_BOARD_HAUPPAUGE_EXETER_955Q:
-+	case CX231XX_BOARD_HAUPPAUGE_935C:
-+	case CX231XX_BOARD_HAUPPAUGE_975:
- 	case CX231XX_BOARD_HAUPPAUGE_USBLIVE2:
- 	case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
- 	case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
-@@ -599,7 +602,7 @@ int cx231xx_set_video_input_mux(struct c
- 				return status;
- 			}
- 		}
--		if (dev->tuner_type == TUNER_NXP_TDA18271)
-+		if (dev->tuner_type == TUNER_NXP_TDA18271 || dev->tuner_type == TUNER_SILABS_TERCAB)
- 			status = cx231xx_set_decoder_video_input(dev,
- 							CX231XX_VMUX_TELEVISION,
- 							INPUT(input)->vmux);
-@@ -1209,7 +1212,8 @@ int cx231xx_set_audio_decoder_input(stru
- 			   new boards in case they use a tuner type we don't
- 			   currently know about */
- 			dev_info(dev->dev,
--				 "Unknown tuner type configuring SIF");
-+				 "Unknown tuner type %d configuring SIF",
-+				 dev->board.tuner_type);
- 			break;
- 		}
- 		break;
-@@ -1750,6 +1754,9 @@ int cx231xx_dif_set_standard(struct cx23
- 	case CX231XX_BOARD_CNXT_RDU_250:
- 	case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
- 	case CX231XX_BOARD_HAUPPAUGE_EXETER:
-+	case CX231XX_BOARD_HAUPPAUGE_EXETER_955Q:
-+	case CX231XX_BOARD_HAUPPAUGE_935C:
-+	case CX231XX_BOARD_HAUPPAUGE_975:
- 	case CX231XX_BOARD_OTG102:
- 		func_mode = 0x03;
- 		break;
---- linux-4.15/drivers/media/usb/cx231xx/cx231xx-cards.c.0140~	2018-02-12 11:32:52.017576679 +0100
-+++ linux-4.15/drivers/media/usb/cx231xx/cx231xx-cards.c	2018-02-12 11:34:46.081381342 +0100
-@@ -34,6 +34,7 @@
- #include <media/dvb-usb-ids.h>
- #include "xc5000.h"
- #include "tda18271.h"
-+#include "si2157.h"
- 
- 
- static int tuner = -1;
-@@ -376,6 +377,123 @@ struct cx231xx_board cx231xx_boards[] =
- 			.gpio = NULL,
- 		} },
- 	},
-+	[CX231XX_BOARD_HAUPPAUGE_EXETER_955Q] = {
-+		.name = "Hauppauge EXETER 955Q",
-+		.tuner_type = TUNER_SILABS_TERCAB,
-+		.tuner_addr = 0x60,
-+		.tuner_gpio = RDE250_XCV_TUNER,
-+		.tuner_sif_gpio = -1, //0x05,
-+		.tuner_scl_gpio = -1, //0x1a,
-+		.tuner_sda_gpio = -1, //0x1b,
-+		.decoder = CX231XX_AVDECODER,
-+		.output_mode = OUT_MODE_VIP11,
-+		.demod_xfer_mode = 0,
-+		.ctl_pin_status_mask = 0xFFFFFFC4,
-+		.agc_analog_digital_select_gpio = 0x0c,
-+		.gpio_pin_status_mask = 0x4001000,
-+		.tuner_i2c_master = I2C_1_MUX_3,
-+		.demod_i2c_master = I2C_2,
-+		.has_dvb = 1,
-+		.demod_addr = 0xB2 >> 1,
-+		.norm = V4L2_STD_NTSC,
-+
-+		.input = {{
-+			.type = CX231XX_VMUX_TELEVISION,
-+			.vmux = CX231XX_VIN_3_1,
-+			.amux = CX231XX_AMUX_VIDEO,
-+			.gpio = NULL,
-+		}, {
-+			.type = CX231XX_VMUX_COMPOSITE1,
-+			.vmux = CX231XX_VIN_2_1,
-+			.amux = CX231XX_AMUX_LINE_IN,
-+			.gpio = NULL,
-+		}, {
-+			.type = CX231XX_VMUX_SVIDEO,
-+			.vmux = CX231XX_VIN_1_1 |
-+				(CX231XX_VIN_1_2 << 8) |
-+				CX25840_SVIDEO_ON,
-+			.amux = CX231XX_AMUX_LINE_IN,
-+			.gpio = NULL,
-+		} },
-+	},
-+	[CX231XX_BOARD_HAUPPAUGE_935C] = {
-+		.name = "Hauppauge WinTV 935C",
-+		.tuner_type = TUNER_SILABS_TERCAB,
-+		.tuner_addr = 0x60,
-+		.tuner_gpio = RDE250_XCV_TUNER,
-+		.tuner_sif_gpio = -1, //0x05,
-+		.tuner_scl_gpio = -1, //0x1a,
-+		.tuner_sda_gpio = -1, //0x1b,
-+		.decoder = CX231XX_AVDECODER,
-+		.output_mode = OUT_MODE_VIP11,
-+		.demod_xfer_mode = 0,
-+		.ctl_pin_status_mask = 0xFFFFFFC4,
-+		.agc_analog_digital_select_gpio = 0x0c,
-+		.gpio_pin_status_mask = 0x4001000,
-+		.tuner_i2c_master = I2C_1_MUX_3,
-+		.demod_i2c_master = I2C_2,
-+		.has_dvb = 1,
-+		.demod_addr = 0xC8 >> 1,
-+		.norm = V4L2_STD_PAL,
-+
-+		.input = {{
-+			.type = CX231XX_VMUX_TELEVISION,
-+			.vmux = CX231XX_VIN_3_1,
-+			.amux = CX231XX_AMUX_VIDEO,
-+			.gpio = NULL,
-+		}, {
-+			.type = CX231XX_VMUX_COMPOSITE1,
-+			.vmux = CX231XX_VIN_2_1,
-+			.amux = CX231XX_AMUX_LINE_IN,
-+			.gpio = NULL,
-+		}, {
-+			.type = CX231XX_VMUX_SVIDEO,
-+			.vmux = CX231XX_VIN_1_1 |
-+				(CX231XX_VIN_1_2 << 8) |
-+				CX25840_SVIDEO_ON,
-+			.amux = CX231XX_AMUX_LINE_IN,
-+			.gpio = NULL,
-+		} },
-+	},
-+	[CX231XX_BOARD_HAUPPAUGE_975] = {
-+		.name = "Hauppauge WinTV 975",
-+		.tuner_type = TUNER_SILABS_TERCAB,
-+		.tuner_addr = 0x60,
-+		.tuner_gpio = RDE250_XCV_TUNER,
-+		.tuner_sif_gpio = -1, //0x05,
-+		.tuner_scl_gpio = -1, //0x1a,
-+		.tuner_sda_gpio = -1, //0x1b,
-+		.decoder = CX231XX_AVDECODER,
-+		.output_mode = OUT_MODE_VIP11,
-+		.demod_xfer_mode = 0,
-+		.ctl_pin_status_mask = 0xFFFFFFC4,
-+		.agc_analog_digital_select_gpio = 0x0c,
-+		.gpio_pin_status_mask = 0x4001000,
-+		.tuner_i2c_master = I2C_1_MUX_3,
-+		.demod_i2c_master = I2C_2,
-+		.has_dvb = 1,
-+		.demod_addr = -1,
-+		.norm = V4L2_STD_PAL,
-+
-+		.input = {{
-+			.type = CX231XX_VMUX_TELEVISION,
-+			.vmux = CX231XX_VIN_3_1,
-+			.amux = CX231XX_AMUX_VIDEO,
-+			.gpio = NULL,
-+		}, {
-+			.type = CX231XX_VMUX_COMPOSITE1,
-+			.vmux = CX231XX_VIN_2_1,
-+			.amux = CX231XX_AMUX_LINE_IN,
-+			.gpio = NULL,
-+		}, {
-+			.type = CX231XX_VMUX_SVIDEO,
-+			.vmux = CX231XX_VIN_1_1 |
-+				(CX231XX_VIN_1_2 << 8) |
-+				CX25840_SVIDEO_ON,
-+			.amux = CX231XX_AMUX_LINE_IN,
-+			.gpio = NULL,
-+		} },
-+	},
- 	[CX231XX_BOARD_HAUPPAUGE_USBLIVE2] = {
- 		.name = "Hauppauge USB Live 2",
- 		.tuner_type = TUNER_ABSENT,
-@@ -965,6 +1083,12 @@ struct usb_device_id cx231xx_id_table[]
- 	 .driver_info = CX231XX_BOARD_HAUPPAUGE_930C_HD_1114xx},
- 	{USB_DEVICE(0x2040, 0xb140),
- 	 .driver_info = CX231XX_BOARD_HAUPPAUGE_EXETER},
-+	{USB_DEVICE(0x2040, 0xb151),
-+	 .driver_info = CX231XX_BOARD_HAUPPAUGE_935C},
-+	{USB_DEVICE(0x2040, 0xb123),
-+	 .driver_info = CX231XX_BOARD_HAUPPAUGE_EXETER_955Q},
-+	{USB_DEVICE(0x2040, 0xb150),
-+	 .driver_info = CX231XX_BOARD_HAUPPAUGE_975},
- 	{USB_DEVICE(0x2040, 0xc200),
- 	 .driver_info = CX231XX_BOARD_HAUPPAUGE_USBLIVE2},
- 	/* PCTV QuatroStick 521e */
-@@ -1024,7 +1148,7 @@ int cx231xx_tuner_callback(void *ptr, in
- 					       1);
- 			msleep(10);
- 		}
--	} else if (dev->tuner_type == TUNER_NXP_TDA18271) {
-+	} else if (dev->tuner_type == TUNER_NXP_TDA18271 || dev->tuner_type == TUNER_SILABS_TERCAB) {
- 		switch (command) {
- 		case TDA18271_CALLBACK_CMD_AGC_ENABLE:
- 			if (dev->model == CX231XX_BOARD_PV_PLAYTV_USB_HYBRID)
-@@ -1173,7 +1297,6 @@ static int read_eeprom(struct cx231xx *d
- 
- void cx231xx_card_setup(struct cx231xx *dev)
- {
--
- 	cx231xx_set_model(dev);
- 
- 	dev->tuner_type = cx231xx_boards[dev->model].tuner_type;
-@@ -1211,6 +1334,9 @@ void cx231xx_card_setup(struct cx231xx *
- 	case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx:
- 	case CX231XX_BOARD_HAUPPAUGE_930C_HD_1114xx:
- 	case CX231XX_BOARD_HAUPPAUGE_955Q:
-+	case CX231XX_BOARD_HAUPPAUGE_EXETER_955Q:
-+	case CX231XX_BOARD_HAUPPAUGE_935C:
-+	case CX231XX_BOARD_HAUPPAUGE_975:
- 		{
- 			struct eeprom {
- 				struct tveeprom tvee;
---- linux-4.15/drivers/media/usb/cx231xx/cx231xx-core.c.0140~	2018-02-12 11:32:52.018576686 +0100
-+++ linux-4.15/drivers/media/usb/cx231xx/cx231xx-core.c	2018-02-12 11:32:52.775582231 +0100
-@@ -720,6 +720,9 @@ int cx231xx_set_mode(struct cx231xx *dev
- 			break;
- 		case CX231XX_BOARD_HAUPPAUGE_EXETER:
- 		case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx:
-+		case CX231XX_BOARD_HAUPPAUGE_EXETER_955Q:
-+		case CX231XX_BOARD_HAUPPAUGE_935C:
-+		case CX231XX_BOARD_HAUPPAUGE_975:
- 			errCode = cx231xx_set_power_mode(dev,
- 						POLARIS_AVMODE_DIGITAL);
- 			break;
-@@ -739,6 +742,9 @@ int cx231xx_set_mode(struct cx231xx *dev
- 		case CX231XX_BOARD_CNXT_RDU_253S:
- 		case CX231XX_BOARD_HAUPPAUGE_EXETER:
- 		case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx:
-+		case CX231XX_BOARD_HAUPPAUGE_EXETER_955Q:
-+		case CX231XX_BOARD_HAUPPAUGE_935C:
-+		case CX231XX_BOARD_HAUPPAUGE_975:
- 		case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
- 		case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
- 		case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
-@@ -1443,6 +1449,9 @@ int cx231xx_dev_init(struct cx231xx *dev
- 	case CX231XX_BOARD_CNXT_RDU_253S:
- 	case CX231XX_BOARD_HAUPPAUGE_EXETER:
- 	case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx:
-+	case CX231XX_BOARD_HAUPPAUGE_EXETER_955Q:
-+	case CX231XX_BOARD_HAUPPAUGE_935C:
-+	case CX231XX_BOARD_HAUPPAUGE_975:
- 	case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
- 	case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL:
- 	case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC:
---- linux-4.15/drivers/media/usb/cx231xx/cx231xx-dvb.c.0140~	2018-02-12 11:32:52.018576686 +0100
-+++ linux-4.15/drivers/media/usb/cx231xx/cx231xx-dvb.c	2018-02-12 11:32:52.775582231 +0100
-@@ -34,8 +34,11 @@
- #include "lgdt3305.h"
- #include "si2165.h"
- #include "si2168.h"
-+#include "si2168b.h"
-+#include "silg.h"
- #include "mb86a20s.h"
- #include "si2157.h"
-+#include "silabs_tercab.h"
- #include "lgdt3306a.h"
- #include "r820t.h"
- #include "mn88473.h"
-@@ -131,6 +134,38 @@ static struct lgdt3305_config hcw_lgdt33
- 	.vsb_if_khz         = 3250,
- };
- 
-+static struct lgdt3306a_config hcw_lgdt3306a_config = {
-+	/* LG3306A demodulator configuration */
-+	.i2c_addr           = 0xB2 >> 1,
-+
-+	/* user defined IF frequency in KHz */
-+	.qam_if_khz         = HVR19x5_QAM_IF, //needs to match tuner
-+	.vsb_if_khz         = HVR19x5_VSB_IF, //needs to match tuner
-+
-+	/* disable i2c repeater - 0:repeater enabled 1:repeater disabled */
-+	.deny_i2c_rptr      = 1,
-+
-+	/* spectral inversion - 0:disabled 1:enabled */
-+	.spectral_inversion = 1,
-+
-+	.mpeg_mode          = LGDT3306A_MPEG_SERIAL,
-+	.tpclk_edge         = LGDT3306A_TPCLK_RISING_EDGE,
-+	.tpvalid_polarity   = LGDT3306A_TP_VALID_HIGH,
-+
-+	.xtalMHz            = 25, //demod clock freq in MHz; 24 or 25 supported
-+};
-+
-+static struct silabs_tercab_config hauppauge_si2157_config = {
-+	.tuner_address           = 0xC0 >> 1,      /* address of the tuner for ATSC/DVB-T */
-+	.qam_if_khz              = HVR19x5_QAM_IF, /* needs to match demods qam if */
-+	.vsb_if_khz              = HVR19x5_VSB_IF, /* needs to match demods vsb if */
-+	.tuner_clock_control     = 1, /* 0:always off 1:always on 2:clock managed */
-+	.tuner_agc_control       = 1,
-+	.fef_mode                = 0, /* fef mode slow normal agc */
-+	.crystal_trim_xo_cap     = 2,
-+	.indirect_i2c_connection = 1, /* Si2157 connected directly */
-+};
-+
- static struct tda18271_std_map hauppauge_tda18271_std_map = {
- 	.atsc_6   = { .if_freq = 3250, .agc_mode = 3, .std = 4,
- 		      .if_lvl = 1, .rfagc_top = 0x58, },
-@@ -173,6 +208,50 @@ static struct r820t_config astrometa_t2h
- 	.max_i2c_msg_len	= 2,
- };
- 
-+static const struct si2168b_config hauppauge_935C_si2168b_config = {
-+	.demod_address           = 0xC8 >> 1,
-+	.min_delay_ms            = 85,
-+	.ts_bus_mode             = 1, /*1-serial, 2-parallel.*/
-+	.ts_clock_mode           = 1, /*0-auto_fixed, 1-auto_adapt, 2-manual.*/
-+	.clk_gapped_en           = 1, /*0-disabled, 1-enabled.*/
-+	.ts_par_clk_invert       = 1, /*0-not-invert, 1-invert*/
-+	.ts_par_clk_shift        = 0,
-+	.fef_mode                = 0, /* needs to match tuner */
-+	.fef_pin                 = 3,
-+	.fef_level               = 0,
-+	.indirect_i2c_connection = 1, /*Si2177 connected directly*/
-+	.start_ctrl              = NULL,
-+};
-+
-+static struct silg_config hauppauge_975_silg_config = {
-+	/* Si2168B demodulator configuration */
-+	.si_demod_enable         = !0,
-+	.si_i2c_addr             = 0xC8 >> 1,
-+	.min_delay_ms            = 85,
-+	.ts_bus_mode             = 1, /*1-serial, 2-parallel.*/
-+	.ts_clock_mode           = 1, /*0-auto_fixed, 1-auto_adapt, 2-manual.*/
-+	.clk_gapped_en           = 1, /*0-disabled, 1-enabled.*/
-+	.ts_par_clk_invert       = 1, /*0-not-invert, 1-invert*/
-+	.ts_par_clk_shift        = 0,
-+	.fef_mode                = 0, /* needs to match tuner */
-+	.fef_pin                 = 3,
-+	.fef_level               = 0,
-+	.indirect_i2c_connection = 1, /*Si2177 connected directly*/
-+	.start_ctrl              = NULL,
-+
-+	/* LG3306A demodulator configuration */
-+	.lg_demod_enable         = !0,
-+	.lg_i2c_addr             = 0xB2 >> 1,
-+	.mpeg_mode               = LGDT3306A_MPEG_SERIAL,
-+	.tpclk_edge              = LGDT3306A_TPCLK_RISING_EDGE,
-+	.tpvalid_polarity        = LGDT3306A_TP_VALID_HIGH,
-+	.deny_i2c_rptr           = 1,
-+	.spectral_inversion      = 1,
-+	.qam_if_khz              = HVR19x5_QAM_IF, /* needs to match tuner */
-+	.vsb_if_khz              = HVR19x5_VSB_IF, /* needs to match tuner */
-+	.xtalMHz                 = 25,
-+};
-+
- static inline void print_err_status(struct cx231xx *dev, int packet, int status)
- {
- 	char *errmsg = "Unknown";
-@@ -275,7 +354,7 @@ static int start_streaming(struct cx231x
- 
- 	if (dev->USE_ISO) {
- 		dev_dbg(dev->dev, "DVB transfer mode is ISO.\n");
--		cx231xx_set_alt_setting(dev, INDEX_TS1, 4);
-+		cx231xx_set_alt_setting(dev, INDEX_TS1, 5);
- 		rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
- 		if (rc < 0)
- 			return rc;
-@@ -933,6 +1012,87 @@ static int dvb_init(struct cx231xx *dev)
- 		dev->dvb->i2c_client_tuner = client;
- 		break;
- 	}
-+	case CX231XX_BOARD_HAUPPAUGE_EXETER_955Q:
-+
-+		dev_info(dev->dev,
-+			"%s: looking for tuner / demod on i2c bus: %d\n",
-+			__func__, i2c_adapter_id(tuner_i2c));
-+
-+		dev->dvb->frontend = dvb_attach(lgdt3306a_attach,
-+			&hcw_lgdt3306a_config,
-+			tuner_i2c);
-+
-+		if (dev->dvb->frontend == NULL) {
-+			dev_info(dev->dev,
-+			       ": Failed to attach LG3306A front end\n");
-+			result = -EINVAL;
-+			goto out_free;
-+		}
-+
-+		dev->dvb->frontend->ops.i2c_gate_ctrl = NULL;
-+
-+		/* define general-purpose callback pointer */
-+		dvb->frontend->callback = cx231xx_tuner_callback;
-+
-+		dvb_attach(silabs_tercab_attach, dev->dvb->frontend,
-+			tuner_i2c,
-+			&hauppauge_si2157_config);
-+		break;
-+
-+	case CX231XX_BOARD_HAUPPAUGE_935C:
-+
-+		dev_info(dev->dev,
-+			"%s: looking for tuner / demod on i2c bus: %d\n",
-+			__func__, i2c_adapter_id(tuner_i2c));
-+
-+		dev->dvb->frontend = dvb_attach(si2168b_attach,
-+			&hauppauge_935C_si2168b_config,
-+			tuner_i2c);
-+
-+		if (dev->dvb->frontend == NULL) {
-+			dev_info(dev->dev,
-+			       ": Failed to attach Si2168B front end\n");
-+			result = -EINVAL;
-+			goto out_free;
-+		}
-+
-+		dev->dvb->frontend->ops.i2c_gate_ctrl = NULL;
-+
-+		/* define general-purpose callback pointer */
-+		dvb->frontend->callback = cx231xx_tuner_callback;
-+
-+		dvb_attach(silabs_tercab_attach, dev->dvb->frontend,
-+			tuner_i2c,
-+			&hauppauge_si2157_config);
-+		break;
-+
-+	case CX231XX_BOARD_HAUPPAUGE_975:
-+
-+		dev_info(dev->dev,
-+			"%s: looking for tuner / demod on i2c bus: %d\n",
-+			__func__, i2c_adapter_id(tuner_i2c));
-+
-+		dev->dvb->frontend = dvb_attach(silg_attach,
-+			&hauppauge_975_silg_config,
-+			tuner_i2c);
-+
-+		if (dev->dvb->frontend == NULL) {
-+			dev_info(dev->dev,
-+			       ": Failed to attach SILG front end\n");
-+			result = -EINVAL;
-+			goto out_free;
-+		}
-+
-+		dev->dvb->frontend->ops.i2c_gate_ctrl = NULL;
-+
-+		/* define general-purpose callback pointer */
-+		dvb->frontend->callback = cx231xx_tuner_callback;
-+
-+		dvb_attach(silabs_tercab_attach, dev->dvb->frontend,
-+			tuner_i2c,
-+			&hauppauge_si2157_config);
-+		break;
-+
- 	case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
- 	case CX231XX_BOARD_KWORLD_UB430_USB_HYBRID:
- 
-@@ -1103,12 +1263,20 @@ out_free:
- 
- static int dvb_fini(struct cx231xx *dev)
- {
-+	struct i2c_client *client;
-+
- 	if (!dev->board.has_dvb) {
- 		/* This device does not support the extension */
- 		return 0;
- 	}
- 
- 	if (dev->dvb) {
-+		client = dev->dvb->i2c_client_tuner;
-+		/* remove I2C tuner */
-+		if (client) {
-+			module_put(client->dev.driver->owner);
-+			i2c_unregister_device(client);
-+		}
- 		unregister_dvb(dev->dvb);
- 		dev->dvb = NULL;
- 	}
---- linux-4.15/drivers/media/usb/cx231xx/cx231xx.h.0140~	2018-02-12 11:32:52.775582231 +0100
-+++ linux-4.15/drivers/media/usb/cx231xx/cx231xx.h	2018-02-12 11:34:17.881187893 +0100
-@@ -81,6 +81,9 @@
- #define CX231XX_BOARD_EVROMEDIA_FULL_HYBRID_FULLHD 23
- #define CX231XX_BOARD_ASTROMETA_T2HYBRID 24
- #define CX231XX_BOARD_THE_IMAGING_SOURCE_DFG_USB2_PRO 25
-+#define CX231XX_BOARD_HAUPPAUGE_EXETER_955Q 26
-+#define CX231XX_BOARD_HAUPPAUGE_935C 27
-+#define CX231XX_BOARD_HAUPPAUGE_975 28
- 
- /* Limits minimum and default number of buffers */
- #define CX231XX_MIN_BUF                 4
---- linux-4.15/drivers/media/usb/cx231xx/cx231xx-video.c.0140~	2018-02-12 11:32:52.018576686 +0100
-+++ linux-4.15/drivers/media/usb/cx231xx/cx231xx-video.c	2018-02-12 11:32:52.776582239 +0100
-@@ -1094,6 +1094,18 @@ static int vidioc_s_std(struct file *fil
- 	/* do mode control overrides */
- 	cx231xx_do_mode_ctrl_overrides(dev);
- 
-+	dev_info(dev->dev,
-+			"%s(): calling cx231xx_dif_set_standards(): norm=0x%08llX\n",
-+			__func__, dev->norm);
-+	rc = cx231xx_dif_set_standard(dev, dev->norm);
-+	if (rc < 0) {
-+		dev_err(dev->dev,
-+				"%s: cx231xx_dif set to By pass"
-+				" mode- errCode [%d]!\n",
-+				__func__, rc);
-+		return -EIO;
-+	}
-+
- 	return 0;
- }
- 
-@@ -1317,7 +1329,7 @@ int cx231xx_s_frequency(struct file *fil
- 	/* set post channel change settings in DIF first */
- 	rc = cx231xx_tuner_post_channel_change(dev);
- 
--	if (dev->tuner_type == TUNER_NXP_TDA18271) {
-+	if (dev->tuner_type == TUNER_NXP_TDA18271 || dev->tuner_type == TUNER_SILABS_TERCAB) {
- 		if (dev->norm & (V4L2_STD_MN | V4L2_STD_NTSC_443))
- 			if_frequency = 5400000;  /*5.4MHz	*/
- 		else if (dev->norm & V4L2_STD_B)
---- linux-4.15/drivers/media/usb/cx231xx/Kconfig.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/usb/cx231xx/Kconfig	2018-02-12 11:32:52.776582239 +0100
-@@ -45,12 +45,15 @@ config VIDEO_CX231XX_DVB
- 	select VIDEOBUF_DVB
- 	select MEDIA_TUNER_XC5000 if MEDIA_SUBDRV_AUTOSELECT
- 	select MEDIA_TUNER_TDA18271 if MEDIA_SUBDRV_AUTOSELECT
-+	select MEDIA_TUNER_SILABS_TERCAB if MEDIA_SUBDRV_AUTOSELECT
- 	select DVB_MB86A20S if MEDIA_SUBDRV_AUTOSELECT
- 	select DVB_LGDT3305 if MEDIA_SUBDRV_AUTOSELECT
- 	select DVB_LGDT3306A if MEDIA_SUBDRV_AUTOSELECT
- 	select DVB_TDA18271C2DD if MEDIA_SUBDRV_AUTOSELECT
- 	select DVB_SI2165 if MEDIA_SUBDRV_AUTOSELECT
- 	select DVB_SI2168 if MEDIA_SUBDRV_AUTOSELECT
-+	select DVB_SI2168B if MEDIA_SUBDRV_AUTOSELECT
-+	select DVB_SILG if MEDIA_SUBDRV_AUTOSELECT
- 	select MEDIA_TUNER_SI2157 if MEDIA_SUBDRV_AUTOSELECT
- 	select DVB_MN88473 if MEDIA_SUBDRV_AUTOSELECT
- 	select MEDIA_TUNER_R820T if MEDIA_SUBDRV_AUTOSELECT
---- linux-4.15/drivers/media/usb/pvrusb2/Kconfig.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/usb/pvrusb2/Kconfig	2018-02-12 11:32:52.776582239 +0100
-@@ -39,10 +39,13 @@ config VIDEO_PVRUSB2_DVB
- 	select DVB_LGDT330X if MEDIA_SUBDRV_AUTOSELECT
- 	select DVB_S5H1409 if MEDIA_SUBDRV_AUTOSELECT
- 	select DVB_S5H1411 if MEDIA_SUBDRV_AUTOSELECT
-+	select DVB_SI2168B if MEDIA_SUBDRV_AUTOSELECT
-+	select DVB_SILG if MEDIA_SUBDRV_AUTOSELECT
- 	select DVB_TDA10048 if MEDIA_SUBDRV_AUTOSELECT
- 	select MEDIA_TUNER_TDA18271 if MEDIA_SUBDRV_AUTOSELECT
- 	select MEDIA_TUNER_SIMPLE if MEDIA_SUBDRV_AUTOSELECT
- 	select MEDIA_TUNER_TDA8290 if MEDIA_SUBDRV_AUTOSELECT
-++	select MEDIA_TUNER_SILABS_TERCAB if MEDIA_SUBDRV_AUTOSELECT
- 	---help---
- 	  This option enables a DVB interface for the pvrusb2 driver.
- 	  If your device does not support digital television, this
---- linux-4.15/drivers/media/usb/pvrusb2/pvrusb2-cx2584x-v4l.c.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/usb/pvrusb2/pvrusb2-cx2584x-v4l.c	2018-02-12 11:32:52.776582239 +0100
-@@ -112,10 +112,35 @@ static const struct routing_scheme routi
- 	.cnt = ARRAY_SIZE(routing_schemeav400),
- };
- 
-+static const struct routing_scheme_item routing_scheme160xxx[] = {
-+	[PVR2_CVAL_INPUT_TV] = {
-+		.vid = CX25840_COMPOSITE7,
-+		.aud = CX25840_AUDIO8,
-+	},
-+	[PVR2_CVAL_INPUT_RADIO] = {
-+		.vid = CX25840_COMPOSITE4,
-+		.aud = CX25840_AUDIO6,
-+	},
-+	[PVR2_CVAL_INPUT_COMPOSITE] = {
-+		.vid = CX25840_COMPOSITE3,
-+		.aud = CX25840_AUDIO_SERIAL,
-+	},
-+	[PVR2_CVAL_INPUT_SVIDEO] = {
-+		.vid = CX25840_SVIDEO1,
-+		.aud = CX25840_AUDIO_SERIAL,
-+	},
-+};
-+
-+static const struct routing_scheme routing_def160xxx = {
-+	.def = routing_scheme160xxx,
-+	.cnt = ARRAY_SIZE(routing_scheme160xxx),
-+};
-+
- static const struct routing_scheme *routing_schemes[] = {
- 	[PVR2_ROUTING_SCHEME_HAUPPAUGE] = &routing_def0,
- 	[PVR2_ROUTING_SCHEME_GOTVIEW] = &routing_defgv,
- 	[PVR2_ROUTING_SCHEME_AV400] = &routing_defav400,
-+	[PVR2_ROUTING_SCHEME_HAUP160XXX] = &routing_def160xxx,
- };
- 
- void pvr2_cx25840_subdev_update(struct pvr2_hdw *hdw, struct v4l2_subdev *sd)
---- linux-4.15/drivers/media/usb/pvrusb2/pvrusb2-devattr.c.0140~	2018-02-12 11:32:52.020576701 +0100
-+++ linux-4.15/drivers/media/usb/pvrusb2/pvrusb2-devattr.c	2018-02-12 11:32:52.776582239 +0100
-@@ -31,15 +31,18 @@ pvr2_device_desc structures.
- #ifdef CONFIG_VIDEO_PVRUSB2_DVB
- #include "pvrusb2-hdw-internal.h"
- #include "lgdt330x.h"
-+#include "lgdt3306a.h"
- #include "s5h1409.h"
- #include "s5h1411.h"
- #include "tda10048.h"
- #include "tda18271.h"
- #include "tda8290.h"
- #include "tuner-simple.h"
-+#include "silabs_tercab.h"
-+#include "si2168b.h"
-+#include "silg.h"
- #endif
- 
--
- /*------------------------------------------------------------------------*/
- /* Hauppauge PVR-USB2 Model 29xxx */
- 
-@@ -474,6 +477,143 @@ static const struct pvr2_dvb_props pvr2_
- };
- #endif
- 
-+/*------------------------------------------------------------------------*/
-+/* Hauppauge PVR-USB2 Models 160xxx */
-+
-+#ifdef CONFIG_VIDEO_PVRUSB2_DVB
-+#define HVR19x5_QAM_IF 4000
-+#define HVR19x5_VSB_IF 3250
-+
-+static struct silabs_tercab_config hauppauge_si2177_config = {
-+	.tuner_address           = 0xC0 >> 1,      /* address of the tuner for ATSC/DVB-T */
-+	.qam_if_khz              = HVR19x5_QAM_IF, /* needs to match demods qam if */
-+	.vsb_if_khz              = HVR19x5_VSB_IF, /* needs to match demods vsb if */
-+	.tuner_clock_control     = 2, /*0-always off 1-always on 2-clock managed */
-+	.tuner_agc_control       = 1,
-+	.fef_mode                = 0, /*0-slow normal AGC, 1-freeze pin, 2-slow initial AGC*/
-+	.crystal_trim_xo_cap     = 8,
-+	.indirect_i2c_connection = 1, /* Si2177 connected directly */
-+};
-+
-+static int pvr2_si2177_attach(struct pvr2_dvb_adapter *adap)
-+{
-+	pr_info("%s()\n", __func__);
-+
-+	dvb_attach(silabs_tercab_attach, adap->fe,
-+		   &adap->channel.hdw->i2c_adap,
-+		   &hauppauge_si2177_config);
-+
-+	return 0;
-+}
-+
-+/*------------------------------------------------------------------------*/
-+/* Hauppauge PVR-USB2 Model 160000 */
-+
-+static struct silg_config pvr2_hvr1975_silg_config = {
-+	/* Si2168B demodulator configuration */
-+	.si_demod_enable         = !0,
-+	.si_i2c_addr             = 0xC8 >> 1,
-+	.min_delay_ms            = 85,
-+	.ts_bus_mode             = 2, /*1-serial, 2-parallel.*/
-+	.ts_clock_mode           = 2, /*0-auto_fixed, 1-auto_adapt, 2-manual.*/
-+	.clk_gapped_en           = 1, /*0-disabled, 1-enabled.*/
-+	.ts_par_clk_invert       = 0, /*0-not-invert, 1-invert*/
-+	.ts_par_clk_shift        = 3, /*DVB-C QAM256 fix*/
-+	.fef_mode                = 0, /* needs to match tuner */
-+	.fef_pin                 = 3,
-+	.fef_level               = 0,
-+	.indirect_i2c_connection = 1, /*Si2177 connected directly*/
-+	.start_ctrl              = NULL,
-+
-+	/* LG3306A demodulator configuration */
-+	.lg_demod_enable         = !0,
-+	.lg_i2c_addr             = 0xB2 >> 1,
-+	.mpeg_mode               = LGDT3306A_MPEG_PARALLEL,
-+	.tpclk_edge              = LGDT3306A_TPCLK_FALLING_EDGE,
-+	.tpvalid_polarity        = LGDT3306A_TP_VALID_LOW,
-+	.deny_i2c_rptr           = 1,
-+	.spectral_inversion      = 1,
-+	.qam_if_khz              = HVR19x5_QAM_IF, /* needs to match tuner */
-+	.vsb_if_khz              = HVR19x5_VSB_IF, /* needs to match tuner */
-+	.xtalMHz                 = 25,
-+};
-+
-+static int pvr2_silg_attach(struct pvr2_dvb_adapter *adap)
-+{
-+	pr_info("%s()\n", __func__);
-+
-+	adap->fe = dvb_attach(silg_attach,
-+				  &pvr2_hvr1975_silg_config,
-+			      &adap->channel.hdw->i2c_adap);
-+	if (adap->fe) {
-+		pr_info("%s(): attached silg\n", __func__);
-+		return 0;
-+	}
-+
-+	return -EIO;
-+}
-+
-+static const struct pvr2_dvb_props pvr2_160000_dvb_props = {
-+	.frontend_attach = pvr2_silg_attach,
-+	.tuner_attach    = pvr2_si2177_attach,
-+};
-+
-+static const struct pvr2_device_client_desc pvr2_cli_160000[] = {
-+	{ .module_id = PVR2_CLIENT_ID_CX25840 },
-+	{ .module_id = PVR2_CLIENT_ID_TUNER,
-+	  .i2c_address_list = "\x60" },
-+	{ .module_id = PVR2_CLIENT_ID_DEMOD,
-+	  .i2c_address_list = "\x59" },	//LG3306a addr
-+};
-+
-+/*------------------------------------------------------------------------*/
-+/* Hauppauge PVR-USB2 Model 160111 */
-+
-+static struct lgdt3306a_config pvr2_lgdt3306a_config = {
-+	/* LG3306A demodulator configuration */
-+	.i2c_addr           = 0xB2 >> 1,
-+
-+	/* user defined IF frequency in KHz */
-+	.qam_if_khz         = HVR19x5_QAM_IF, //FGR - BUGBUG - needs to match tuner
-+	.vsb_if_khz         = HVR19x5_VSB_IF, //FGR - BUGBUG - needs to match tuner
-+
-+	/* disable i2c repeater - 0:repeater enabled 1:repeater disabled */
-+	.deny_i2c_rptr      = 1,
-+
-+	/* spectral inversion - 0:disabled 1:enabled */
-+	.spectral_inversion = 1,
-+
-+	.mpeg_mode          = LGDT3306A_MPEG_PARALLEL,
-+	.tpclk_edge         = LGDT3306A_TPCLK_FALLING_EDGE,
-+	.tpvalid_polarity   = LGDT3306A_TP_VALID_LOW,
-+
-+	.xtalMHz            = 25, //demod clock freq in MHz; 24 or 25 supported
-+};
-+
-+static int pvr2_lgdt3306a_attach(struct pvr2_dvb_adapter *adap)
-+{
-+	adap->fe = dvb_attach(lgdt3306a_attach, &pvr2_lgdt3306a_config,
-+			      &adap->channel.hdw->i2c_adap);
-+	if (adap->fe)
-+		return 0;
-+
-+	return -EIO;
-+}
-+
-+static const struct pvr2_dvb_props pvr2_160111_dvb_props = {
-+	.frontend_attach = pvr2_lgdt3306a_attach,
-+	.tuner_attach    = pvr2_si2177_attach,
-+};
-+
-+static const struct pvr2_device_client_desc pvr2_cli_160111[] = {
-+	{ .module_id = PVR2_CLIENT_ID_CX25840 },
-+	{ .module_id = PVR2_CLIENT_ID_TUNER,
-+	  .i2c_address_list = "\x60" },
-+	{ .module_id = PVR2_CLIENT_ID_DEMOD,
-+	  .i2c_address_list = "\x59" },	//LG3306a addr
-+};
-+#endif
-+
- #define PVR2_FIRMWARE_75xxx "v4l-pvrusb2-73xxx-01.fw"
- static const char *pvr2_fw1_names_75xxx[] = {
- 		PVR2_FIRMWARE_75xxx,
-@@ -525,7 +665,58 @@ static const struct pvr2_device_desc pvr
- #endif
- };
- 
-+#define PVR2_FIRMWARE_160xxx "v4l-pvrusb2-160xxx-01.fw"
-+static const char *pvr2_fw1_names_160xxx[] = {
-+		PVR2_FIRMWARE_160xxx,
-+};
- 
-+static const struct pvr2_device_desc pvr2_device_160000 = {
-+		.description = "WinTV HVR-1975 Model 160000",
-+		.shortname = "160000",
-+		.client_table.lst = pvr2_cli_160000,
-+		.client_table.cnt = ARRAY_SIZE(pvr2_cli_160000),
-+		.fx2_firmware.lst = pvr2_fw1_names_160xxx,
-+		.fx2_firmware.cnt = ARRAY_SIZE(pvr2_fw1_names_160xxx),
-+		.default_tuner_type = TUNER_SILABS_TERCAB,
-+		.flag_has_cx25840 = !0,
-+		.flag_has_hauppauge_rom = !0,
-+		.flag_has_analogtuner = !0,
-+		.flag_has_composite = !0,
-+		.flag_has_svideo = !0,
-+		.flag_fx2_16kb = !0,
-+		.signal_routing_scheme = PVR2_ROUTING_SCHEME_HAUPPAUGE,
-+		.digital_control_scheme = PVR2_DIGITAL_SCHEME_HAUPPAUGE,
-+		.default_std_mask = V4L2_STD_NTSC_M,
-+		.led_scheme = PVR2_LED_SCHEME_HAUPPAUGE,
-+		.ir_scheme = PVR2_IR_SCHEME_ZILOG,
-+#ifdef CONFIG_VIDEO_PVRUSB2_DVB
-+		.dvb_props = &pvr2_160000_dvb_props,
-+#endif
-+};
-+
-+static const struct pvr2_device_desc pvr2_device_160111 = {
-+		.description = "WinTV HVR-1955 Model 160111",
-+		.shortname = "160111",
-+		.client_table.lst = pvr2_cli_160111,
-+		.client_table.cnt = ARRAY_SIZE(pvr2_cli_160111),
-+		.fx2_firmware.lst = pvr2_fw1_names_160xxx,
-+		.fx2_firmware.cnt = ARRAY_SIZE(pvr2_fw1_names_160xxx),
-+		.default_tuner_type = TUNER_SILABS_TERCAB,
-+		.flag_has_cx25840 = !0,
-+		.flag_has_hauppauge_rom = !0,
-+		.flag_has_analogtuner = !0,
-+		.flag_has_composite = !0,
-+		.flag_has_svideo = !0,
-+		.flag_fx2_16kb = !0,
-+		.signal_routing_scheme = PVR2_ROUTING_SCHEME_HAUPPAUGE,
-+		.digital_control_scheme = PVR2_DIGITAL_SCHEME_HAUPPAUGE,
-+		.default_std_mask = V4L2_STD_NTSC_M,
-+		.led_scheme = PVR2_LED_SCHEME_HAUPPAUGE,
-+		.ir_scheme = PVR2_IR_SCHEME_ZILOG,
-+#ifdef CONFIG_VIDEO_PVRUSB2_DVB
-+		.dvb_props = &pvr2_160111_dvb_props,
-+#endif
-+};
- 
- /*------------------------------------------------------------------------*/
- 
-@@ -552,6 +743,10 @@ struct usb_device_id pvr2_device_table[]
- 	  .driver_info = (kernel_ulong_t)&pvr2_device_751xx},
- 	{ USB_DEVICE(0x0ccd, 0x0039),
- 	  .driver_info = (kernel_ulong_t)&pvr2_device_av400},
-+	{ USB_DEVICE(0x2040, 0x7502), /* HVR-1955 */
-+	  .driver_info = (kernel_ulong_t)&pvr2_device_160111},
-+	{ USB_DEVICE(0x2040, 0x7510), /* HVR-1975 */
-+	  .driver_info = (kernel_ulong_t)&pvr2_device_160000},
- 	{ }
- };
- 
-@@ -560,3 +755,4 @@ MODULE_FIRMWARE(PVR2_FIRMWARE_29xxx);
- MODULE_FIRMWARE(PVR2_FIRMWARE_24xxx);
- MODULE_FIRMWARE(PVR2_FIRMWARE_73xxx);
- MODULE_FIRMWARE(PVR2_FIRMWARE_75xxx);
-+MODULE_FIRMWARE(PVR2_FIRMWARE_160xxx);
---- linux-4.15/drivers/media/usb/pvrusb2/pvrusb2-devattr.h.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/usb/pvrusb2/pvrusb2-devattr.h	2018-02-12 11:32:52.776582239 +0100
-@@ -66,6 +66,7 @@ struct pvr2_string_table {
- #define PVR2_ROUTING_SCHEME_GOTVIEW 1
- #define PVR2_ROUTING_SCHEME_ONAIR 2
- #define PVR2_ROUTING_SCHEME_AV400 3
-+#define PVR2_ROUTING_SCHEME_HAUP160XXX 4
- 
- #define PVR2_DIGITAL_SCHEME_NONE 0
- #define PVR2_DIGITAL_SCHEME_HAUPPAUGE 1
---- linux-4.15/drivers/media/usb/pvrusb2/pvrusb2-dvb.c.0140~	2018-02-12 11:32:52.020576701 +0100
-+++ linux-4.15/drivers/media/usb/pvrusb2/pvrusb2-dvb.c	2018-02-12 11:32:52.776582239 +0100
-@@ -244,6 +244,13 @@ static int pvr2_dvb_stop_feed(struct dvb
- static int pvr2_dvb_bus_ctrl(struct dvb_frontend *fe, int acquire)
- {
- 	struct pvr2_dvb_adapter *adap = fe->dvb->priv;
-+	const struct pvr2_hdw *hdw = adap->channel.hdw;
-+
-+	pvr2_trace(PVR2_TRACE_DVB_FEED, "%s(): dvb bus ctrl: %d", __func__, acquire);
-+
-+	if (hdw->fe_ts_bus_ctrl)
-+		hdw->fe_ts_bus_ctrl(fe, acquire);
-+
- 	return pvr2_channel_limit_inputs(
- 	    &adap->channel,
- 	    (acquire ? (1 << PVR2_CVAL_INPUT_DTV) : 0));
-@@ -361,8 +368,10 @@ static int pvr2_dvb_frontend_init(struct
- 			adap->fe->ops.analog_ops.standby(adap->fe);
- 
- 		/* Ensure all frontends negotiate bus access */
-+		/* save the original function pointer */
-+		hdw->fe_ts_bus_ctrl = adap->fe->ops.ts_bus_ctrl;
-+		pvr2_trace(PVR2_TRACE_INFO, "transferring ts_bus_ctrl() to pvr2_dvb_bus_ctrl()");
- 		adap->fe->ops.ts_bus_ctrl = pvr2_dvb_bus_ctrl;
--
- 	} else {
- 		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
- 			   "no frontend was attached!");
---- linux-4.15/drivers/media/usb/pvrusb2/pvrusb2-fx2-cmd.h.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/usb/pvrusb2/pvrusb2-fx2-cmd.h	2018-02-12 11:32:52.776582239 +0100
-@@ -38,6 +38,10 @@
- 
- #define FX2CMD_FWPOST1          0x52u
- 
-+/* These 2 only exist on Model 160xxx */
-+#define FX2CMD_HCW_DEMOD_RESET_PIN 0xd4u
-+#define FX2CMD_HCW_MAKO_SLEEP_PIN  0xd5u
-+
- #define FX2CMD_POWER_OFF        0xdcu
- #define FX2CMD_POWER_ON         0xdeu
- 
---- linux-4.15/drivers/media/usb/pvrusb2/pvrusb2-hdw.c.0140~	2018-02-12 11:32:52.020576701 +0100
-+++ linux-4.15/drivers/media/usb/pvrusb2/pvrusb2-hdw.c	2018-02-12 11:32:52.777582246 +0100
-@@ -316,6 +316,8 @@ static const struct pvr2_fx2cmd_descdef
- 	{FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
- 	{FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
- 	{FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
-+	{FX2CMD_HCW_DEMOD_RESET_PIN, "hcw demod reset pin"},
-+	{FX2CMD_HCW_MAKO_SLEEP_PIN, "hcw mako sleep pin"},
- };
- 
- 
-@@ -2093,6 +2095,7 @@ static void pvr2_hdw_setup_low(struct pv
- 	unsigned int idx;
- 	struct pvr2_ctrl *cptr;
- 	int reloadFl = 0;
-+
- 	if (hdw->hdw_desc->fx2_firmware.cnt) {
- 		if (!reloadFl) {
- 			reloadFl =
-@@ -2141,6 +2144,23 @@ static void pvr2_hdw_setup_low(struct pv
- 	pvr2_i2c_core_init(hdw);
- 	if (!pvr2_hdw_dev_ok(hdw)) return;
- 
-+	/* reset demod only on Hauppauge 160xxx platform */
-+	if (hdw->usb_dev->descriptor.idVendor == 0x2040 &&
-+			(hdw->usb_dev->descriptor.idProduct == 0x7502 || hdw->usb_dev->descriptor.idProduct == 0x7510)) {
-+		pr_info("%s(): resetting 160xxx demod\n", __func__);
-+		//FGR - not sure this is the proper place to reset demods once only
-+		pvr2_issue_simple_cmd(hdw,
-+				     FX2CMD_HCW_DEMOD_RESET_PIN |
-+				     (1 << 8) |
-+				     ((0) << 16));
-+		msleep(10);
-+		pvr2_issue_simple_cmd(hdw,
-+				     FX2CMD_HCW_DEMOD_RESET_PIN |
-+				     (1 << 8) |
-+				     ((1) << 16));
-+		msleep(10);
-+	}
-+
- 	pvr2_hdw_load_modules(hdw);
- 	if (!pvr2_hdw_dev_ok(hdw)) return;
- 
-@@ -2205,7 +2225,6 @@ static void pvr2_hdw_setup_low(struct pv
- 			   hdw->tuner_type);
- 	}
- 
--
- 	if (!pvr2_hdw_dev_ok(hdw)) return;
- 
- 	if (hdw->hdw_desc->signal_routing_scheme ==
-@@ -4011,6 +4030,17 @@ int pvr2_hdw_cmd_decoder_reset(struct pv
- static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
- {
- 	hdw->flag_ok = !0;
-+
-+	//BUGBUG - use this for 160xxx, but how can we tell it's the right HW
-+	if (hdw->usb_dev->descriptor.idVendor == 0x2040 &&
-+			(hdw->usb_dev->descriptor.idProduct == 0x7502 || hdw->usb_dev->descriptor.idProduct == 0x7510)) {
-+		pr_info("%s(): resetting demod on Hauppauge 160xxx platform skipped\n", __func__);
-+		//FGR don't want Demod reset on 160xxx or it will trash Demod tristate
-+		return pvr2_issue_simple_cmd(hdw,
-+				     FX2CMD_HCW_MAKO_SLEEP_PIN |
-+				     (1 << 8) |
-+				     ((onoff ? 1 : 0) << 16));
-+	}
- 	return pvr2_issue_simple_cmd(hdw,
- 				     FX2CMD_HCW_DEMOD_RESETIN |
- 				     (1 << 8) |
---- linux-4.15/drivers/media/usb/pvrusb2/pvrusb2-hdw-internal.h.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/usb/pvrusb2/pvrusb2-hdw-internal.h	2018-02-12 11:32:52.777582246 +0100
-@@ -381,6 +381,9 @@ struct pvr2_hdw {
- 
- 	struct pvr2_ctrl *controls;
- 	unsigned int control_cnt;
-+
-+	/* experimental... */
-+	int (*fe_ts_bus_ctrl) (struct dvb_frontend*, int);
- };
- 
- /* This function gets the current frequency */
---- linux-4.15/drivers/media/v4l2-core/tuner-core.c.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/drivers/media/v4l2-core/tuner-core.c	2018-02-12 11:32:52.778582253 +0100
-@@ -40,6 +40,7 @@
- #include "xc5000.h"
- #include "tda18271.h"
- #include "xc4000.h"
-+#include "silabs_tercab.h"
- 
- #define UNSET (-1U)
- 
-@@ -396,6 +397,30 @@ static void set_type(struct i2c_client *
- 		tune_now = 0;
- 		break;
- 	}
-+	case TUNER_SILABS_TERCAB:
-+	{
-+		static struct silabs_tercab_config silabs_config = {
-+			.tuner_address           = 0xC0 >> 1,      /* address of the tuner for ATSC/DVB-T */
-+			.qam_if_khz              = HVR19x5_QAM_IF, /* needs to match demods qam if */
-+			.vsb_if_khz              = HVR19x5_VSB_IF, /* needs to match demods vsb if */
-+			.tuner_clock_control     = 1, /* 0:always off 1:always on 2:clock managed */
-+			.tuner_agc_control       = 1,
-+			.fef_mode                = 0, /* fef mode slow normal agc */
-+			.crystal_trim_xo_cap     = 8,
-+			.indirect_i2c_connection = 1, /* tuner connected directly(?) */
-+		};
-+
-+		printk(KERN_INFO "%s: looking for Silicon Labs tuner on i2c bus: %d\n",
-+		       __func__, i2c_adapter_id(t->i2c->adapter));
-+
-+		if (!dvb_attach(silabs_tercab_attach, &t->fe, t->i2c->adapter, &silabs_config)) {
-+			printk(KERN_ERR "%s: attaching Silicon Labs tuner failed\n", __func__);
-+			goto attach_failed;
-+		}
-+		printk(KERN_INFO "%s: Silicon Labs tuner attached\n", __func__);
-+		tune_now = 0;
-+		break;
-+	}
- 	default:
- 		if (!dvb_attach(simple_tuner_attach, &t->fe,
- 				t->i2c->adapter, t->i2c->addr, t->type))
-@@ -643,17 +668,27 @@ static int tuner_probe(struct i2c_client
- 			}
- 			break;
- 		case 0x60:
--			if (tuner_symbol_probe(tea5767_autodetection,
-+			if (tuner_symbol_probe(silabs_tercab_autodetection,
- 					       t->i2c->adapter, t->i2c->addr)
--					>= 0) {
--				t->type = TUNER_TEA5767;
--				t->mode_mask = T_RADIO;
--				/* Sets freq to FM range */
--				tuner_lookup(t->i2c->adapter, &radio, &tv);
--				if (tv)
--					tv->mode_mask &= ~T_RADIO;
--
-+					== 0) {
-+				dprintk("Silicon Labs tuner @ 0x%02X detected\n", t->i2c->addr);
-+				t->type = TUNER_SILABS_TERCAB;
-+				t->mode_mask = T_ANALOG_TV;
- 				goto register_client;
-+			} else {
-+				dprintk("i2c addr 0x60: tea5767_autodetection\n");
-+				if (tuner_symbol_probe(tea5767_autodetection,
-+					       	   t->i2c->adapter, t->i2c->addr)
-+						>= 0) {
-+					t->type = TUNER_TEA5767;
-+					t->mode_mask = T_RADIO;
-+					/* Sets freq to FM range */
-+					tuner_lookup(t->i2c->adapter, &radio, &tv);
-+					if (tv)
-+						tv->mode_mask &= ~T_RADIO;
-+
-+					goto register_client;
-+				}
- 			}
- 			break;
- 		}
---- linux-4.15/include/media/tuner.h.0140~	2018-01-28 22:20:33.000000000 +0100
-+++ linux-4.15/include/media/tuner.h	2018-02-12 11:32:52.778582253 +0100
-@@ -142,6 +142,8 @@
- #define TUNER_SONY_BTF_PK467Z		90	/* NTSC_JP */
- #define TUNER_SONY_BTF_PB463Z		91	/* NTSC */
- 
-+#define TUNER_SILABS_TERCAB		92	/* Silicon Labs terrestrial/cable tuner series */
-+
- /* tv card specific */
- #define TDA9887_PRESENT			(1<<0)
- #define TDA9887_PORT1_INACTIVE		(1<<1)
diff --git a/disabled/kernel-4.14-K70LUX.patch b/disabled/kernel-4.14-K70LUX.patch
deleted file mode 100644
index fa76d79..0000000
--- a/disabled/kernel-4.14-K70LUX.patch
+++ /dev/null
@@ -1,12 +0,0 @@
---- linux-4.13/drivers/usb/core/quirks.c.omv~	2017-11-02 20:28:55.104625978 +0100
-+++ linux-4.13/drivers/usb/core/quirks.c	2017-11-02 20:29:54.184437806 +0100
-@@ -221,6 +221,9 @@ static const struct usb_device_id usb_qu
- 	/* Corsair Strafe RGB */
- 	{ USB_DEVICE(0x1b1c, 0x1b20), .driver_info = USB_QUIRK_DELAY_INIT },
- 
-+	/* Corsair K70 LUX */
-+	{ USB_DEVICE(0x1b1c, 0x1b36), .driver_info = USB_QUIRK_DELAY_INIT },
-+
- 	/* MIDI keyboard WORLDE MINI */
- 	{ USB_DEVICE(0x1c75, 0x0204), .driver_info =
- 			USB_QUIRK_CONFIG_INTF_STRINGS },
diff --git a/disabled/kernel-4.17-rc7-add-lima-driver.patch b/disabled/kernel-4.17-rc7-add-lima-driver.patch
deleted file mode 100644
index 14f7923..0000000
--- a/disabled/kernel-4.17-rc7-add-lima-driver.patch
+++ /dev/null
@@ -1,5257 +0,0 @@
-diff -up linux-4.17/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi.0150~ linux-4.17/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
---- linux-4.17/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi.0150~	2018-07-02 19:37:07.980000969 +0200
-+++ linux-4.17/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi	2018-07-02 19:37:08.164000956 +0200
-@@ -241,6 +241,7 @@
- 			"pp2", "ppmmu2";
- 		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
- 		clock-names = "bus", "core";
-+		switch-delay = <0xffff>;
- 
- 		/*
- 		 * Mali clocking is provided by two identical clock paths
-diff -up linux-4.17/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi.0150~ linux-4.17/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
---- linux-4.17/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi.0150~	2018-07-02 19:37:07.980000969 +0200
-+++ linux-4.17/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi	2018-07-02 19:37:08.164000956 +0200
-@@ -23,6 +23,7 @@
- 			"pp2", "ppmmu2";
- 		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
- 		clock-names = "bus", "core";
-+		switch-delay = <0xffff>;
- 
- 		/*
- 		 * Mali clocking is provided by two identical clock paths
-diff -up linux-4.17/arch/arm/boot/dts/exynos4.dtsi.0150~ linux-4.17/arch/arm/boot/dts/exynos4.dtsi
---- linux-4.17/arch/arm/boot/dts/exynos4.dtsi.0150~	2018-07-02 19:37:07.976000970 +0200
-+++ linux-4.17/arch/arm/boot/dts/exynos4.dtsi	2018-07-02 19:37:08.163000956 +0200
-@@ -730,6 +730,39 @@
- 			status = "disabled";
- 		};
- 
-+		gpu: gpu@13000000 {
-+			compatible = "samsung,exynos4-mali", "arm,mali-400";
-+			reg = <0x13000000 0x30000>;
-+			power-domains = <&pd_g3d>;
-+
-+			/*
-+			 * Propagate VPLL output clock to SCLK_G3D and
-+			 * ensure that the DIV_G3D divider is 1.
-+			 */
-+			assigned-clocks = <&clock CLK_MOUT_G3D1>, <&clock CLK_MOUT_G3D>,
-+					  <&clock CLK_FOUT_VPLL>, <&clock CLK_SCLK_G3D>;
-+			assigned-clock-parents = <&clock CLK_SCLK_VPLL>,
-+						 <&clock CLK_MOUT_G3D1>;
-+			assigned-clock-rates = <0>, <0>, <160000000>, <160000000>;
-+
-+			clocks = <&clock CLK_SCLK_G3D>, <&clock CLK_G3D>;
-+			clock-names = "bus", "core";
-+
-+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "ppmmu0", "ppmmu1", "ppmmu2", "ppmmu3",
-+					  "gpmmu", "pp0", "pp1", "pp2", "pp3", "gp";
-+			status = "disabled";
-+		};
-+
- 		tmu: tmu@100c0000 {
- 			interrupt-parent = <&combiner>;
- 			reg = <0x100C0000 0x100>;
-diff -up linux-4.17/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt.0150~ linux-4.17/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
---- linux-4.17/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt.0150~	2018-07-02 19:37:07.972000970 +0200
-+++ linux-4.17/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt	2018-07-02 19:37:08.163000956 +0200
-@@ -58,6 +58,10 @@ Optional properties:
-     A power domain consumer specifier as defined in
-     Documentation/devicetree/bindings/power/power_domain.txt
- 
-+  - switch-delay:
-+    This value is the number of Mali clock cycles it takes to
-+    enable the power gates and turn on the power mesh.
-+
- Vendor-specific bindings
- ------------------------
- 
-diff -up linux-4.17/drivers/gpu/drm/Kconfig.0150~ linux-4.17/drivers/gpu/drm/Kconfig
---- linux-4.17/drivers/gpu/drm/Kconfig.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/Kconfig	2018-07-02 19:37:38.119998781 +0200
-@@ -294,6 +294,8 @@ source "drivers/gpu/drm/tve200/Kconfig"
- 
- source "drivers/gpu/drm/xen/Kconfig"
- 
-+source "drivers/gpu/drm/lima/Kconfig"
-+
- # Keep legacy drivers last
- 
- menuconfig DRM_LEGACY
-diff -up linux-4.17/drivers/gpu/drm/lima/Kconfig.0150~ linux-4.17/drivers/gpu/drm/lima/Kconfig
---- linux-4.17/drivers/gpu/drm/lima/Kconfig.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/Kconfig	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,11 @@
-+# SPDX-License-Identifier: GPL-2.0 OR MIT
-+# Copyright 2017-2018 Qiang Yu <yuq825@gmail.com>
-+
-+config DRM_LIMA
-+       tristate "LIMA (DRM support for ARM Mali 400/450 GPU)"
-+       depends on DRM
-+       depends on ARM || ARM64 || COMPILE_TEST
-+       select DRM_SCHED
-+       select DRM_TTM
-+       help
-+         DRM driver for ARM Mali 400/450 GPUs.
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_bcast.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_bcast.c
---- linux-4.17/drivers/gpu/drm/lima/lima_bcast.c.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_bcast.c	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,46 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <linux/io.h>
-+#include <linux/device.h>
-+
-+#include "lima_device.h"
-+#include "lima_bcast.h"
-+#include "lima_regs.h"
-+
-+#define bcast_write(reg, data) writel(data, ip->iomem + LIMA_BCAST_##reg)
-+#define bcast_read(reg) readl(ip->iomem + LIMA_BCAST_##reg)
-+
-+void lima_bcast_enable(struct lima_device *dev)
-+{
-+	struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
-+	struct lima_ip *ip = dev->ip + lima_ip_bcast;
-+	int i, mask = 0;
-+
-+	for (i = 0; i < pipe->num_processor; i++) {
-+		struct lima_ip *pp = pipe->processor[i];
-+		mask |= 1 << (pp->id - lima_ip_pp0);
-+	}
-+
-+	bcast_write(BROADCAST_MASK, (mask << 16) | mask);
-+	bcast_write(INTERRUPT_MASK, mask);
-+}
-+
-+void lima_bcast_disable(struct lima_device *dev)
-+{
-+	struct lima_ip *ip = dev->ip + lima_ip_bcast;
-+
-+	bcast_write(BROADCAST_MASK, 0);
-+	bcast_write(INTERRUPT_MASK, 0);
-+}
-+
-+int lima_bcast_init(struct lima_ip *ip)
-+{
-+	return 0;
-+}
-+
-+void lima_bcast_fini(struct lima_ip *ip)
-+{
-+	
-+}
-+
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_bcast.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_bcast.h
---- linux-4.17/drivers/gpu/drm/lima/lima_bcast.h.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_bcast.h	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_BCAST_H__
-+#define __LIMA_BCAST_H__
-+
-+struct lima_ip;
-+
-+int lima_bcast_init(struct lima_ip *ip);
-+void lima_bcast_fini(struct lima_ip *ip);
-+
-+void lima_bcast_enable(struct lima_device *dev);
-+void lima_bcast_disable(struct lima_device *dev);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_ctx.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_ctx.c
---- linux-4.17/drivers/gpu/drm/lima/lima_ctx.c.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_ctx.c	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,124 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <linux/slab.h>
-+
-+#include "lima_device.h"
-+#include "lima_ctx.h"
-+
-+int lima_ctx_create(struct lima_device *dev, struct lima_ctx_mgr *mgr, u32 *id)
-+{
-+	struct lima_ctx *ctx;
-+	int i, err;
-+
-+	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
-+	if (!ctx)
-+		return -ENOMEM;
-+	ctx->dev = dev;
-+	kref_init(&ctx->refcnt);
-+
-+	for (i = 0; i < lima_pipe_num; i++) {
-+		err = lima_sched_context_init(dev->pipe + i, ctx->context + i, &ctx->guilty);
-+		if (err)
-+			goto err_out0;
-+	}
-+
-+	idr_preload(GFP_KERNEL);
-+	spin_lock(&mgr->lock);
-+	err = idr_alloc(&mgr->handles, ctx, 1, 0, GFP_ATOMIC);
-+	spin_unlock(&mgr->lock);
-+	idr_preload_end();
-+	if (err < 0)
-+		goto err_out0;
-+
-+	*id = err;
-+	return 0;
-+
-+err_out0:
-+	for (i--; i >= 0; i--)
-+		lima_sched_context_fini(dev->pipe + i, ctx->context + i);
-+	kfree(ctx);
-+	return err;
-+}
-+
-+static void lima_ctx_do_release(struct kref *ref)
-+{
-+	struct lima_ctx *ctx = container_of(ref, struct lima_ctx, refcnt);
-+	int i;
-+
-+	for (i = 0; i < lima_pipe_num; i++)
-+		lima_sched_context_fini(ctx->dev->pipe + i, ctx->context + i);
-+	kfree(ctx);
-+}
-+
-+int lima_ctx_free(struct lima_ctx_mgr *mgr, u32 id)
-+{
-+	struct lima_ctx *ctx;
-+
-+	spin_lock(&mgr->lock);
-+	ctx = idr_remove(&mgr->handles, id);
-+	spin_unlock(&mgr->lock);
-+
-+	if (ctx) {
-+		kref_put(&ctx->refcnt, lima_ctx_do_release);
-+		return 0;
-+	}
-+	return -EINVAL;
-+}
-+
-+struct lima_ctx *lima_ctx_get(struct lima_ctx_mgr *mgr, u32 id)
-+{
-+	struct lima_ctx *ctx;
-+
-+	spin_lock(&mgr->lock);
-+	ctx = idr_find(&mgr->handles, id);
-+	if (ctx)
-+		kref_get(&ctx->refcnt);
-+	spin_unlock(&mgr->lock);
-+	return ctx;
-+}
-+
-+void lima_ctx_put(struct lima_ctx *ctx)
-+{
-+	kref_put(&ctx->refcnt, lima_ctx_do_release);
-+}
-+
-+void lima_ctx_mgr_init(struct lima_ctx_mgr *mgr)
-+{
-+        spin_lock_init(&mgr->lock);
-+	idr_init(&mgr->handles);
-+}
-+
-+void lima_ctx_mgr_fini(struct lima_ctx_mgr *mgr)
-+{
-+	struct lima_ctx *ctx;
-+	struct idr *idp;
-+	uint32_t id;
-+
-+	idp = &mgr->handles;
-+
-+	idr_for_each_entry(idp, ctx, id) {
-+	        kref_put(&ctx->refcnt, lima_ctx_do_release);
-+	}
-+
-+	idr_destroy(&mgr->handles);
-+}
-+
-+struct dma_fence *lima_ctx_get_native_fence(struct lima_ctx_mgr *mgr,
-+					    u32 ctx, u32 pipe, u32 seq)
-+{
-+	struct lima_ctx *c;
-+	struct dma_fence *ret;
-+
-+	if (pipe >= lima_pipe_num)
-+		return ERR_PTR(-EINVAL);
-+
-+	c = lima_ctx_get(mgr, ctx);
-+	if (!c)
-+		return ERR_PTR(-ENOENT);
-+
-+	ret = lima_sched_context_get_fence(c->context + pipe, seq);
-+
-+	lima_ctx_put(c);
-+	return ret;
-+}
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_ctx.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_ctx.h
---- linux-4.17/drivers/gpu/drm/lima/lima_ctx.h.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_ctx.h	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,33 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_CTX_H__
-+#define __LIMA_CTX_H__
-+
-+#include <linux/idr.h>
-+
-+#include "lima_device.h"
-+
-+struct lima_ctx {
-+	struct kref refcnt;
-+	struct lima_device *dev;
-+	struct lima_sched_context context[lima_pipe_num];
-+	atomic_t guilty;
-+};
-+
-+struct lima_ctx_mgr {
-+	spinlock_t lock;
-+	struct idr handles;
-+};
-+
-+int lima_ctx_create(struct lima_device *dev, struct lima_ctx_mgr *mgr, u32 *id);
-+int lima_ctx_free(struct lima_ctx_mgr *mgr, u32 id);
-+struct lima_ctx *lima_ctx_get(struct lima_ctx_mgr *mgr, u32 id);
-+void lima_ctx_put(struct lima_ctx *ctx);
-+void lima_ctx_mgr_init(struct lima_ctx_mgr *mgr);
-+void lima_ctx_mgr_fini(struct lima_ctx_mgr *mgr);
-+
-+struct dma_fence *lima_ctx_get_native_fence(struct lima_ctx_mgr *mgr,
-+					    u32 ctx, u32 pipe, u32 seq);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_device.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_device.c
---- linux-4.17/drivers/gpu/drm/lima/lima_device.c.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_device.c	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,389 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <linux/regulator/consumer.h>
-+#include <linux/reset.h>
-+#include <linux/clk.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/platform_device.h>
-+
-+#include "lima_device.h"
-+#include "lima_gp.h"
-+#include "lima_pp.h"
-+#include "lima_mmu.h"
-+#include "lima_pmu.h"
-+#include "lima_l2_cache.h"
-+#include "lima_dlbu.h"
-+#include "lima_bcast.h"
-+#include "lima_vm.h"
-+
-+struct lima_ip_desc {
-+	char *name;
-+	char *irq_name;
-+	bool must_have[lima_gpu_num];
-+	int offset[lima_gpu_num];
-+
-+	int (*init)(struct lima_ip *);
-+	void (*fini)(struct lima_ip *);
-+};
-+
-+#define LIMA_IP_DESC(ipname, mst0, mst1, off0, off1, func, irq) \
-+	[lima_ip_##ipname] = { \
-+		.name = #ipname, \
-+		.irq_name = irq, \
-+		.must_have = { \
-+			[lima_gpu_mali400] = mst0, \
-+			[lima_gpu_mali450] = mst1, \
-+		}, \
-+		.offset = { \
-+			[lima_gpu_mali400] = off0, \
-+			[lima_gpu_mali450] = off1, \
-+		}, \
-+		.init = lima_##func##_init, \
-+		.fini = lima_##func##_fini, \
-+	}
-+
-+static struct lima_ip_desc lima_ip_desc[lima_ip_num] = {
-+	LIMA_IP_DESC(pmu,         false, false, 0x02000, 0x02000, pmu,      "pmu"),
-+	LIMA_IP_DESC(l2_cache0,   true,  true,  0x01000, 0x10000, l2_cache, NULL),
-+	LIMA_IP_DESC(l2_cache1,   false, true,  -1,      0x01000, l2_cache, NULL),
-+	LIMA_IP_DESC(l2_cache2,   false, false, -1,      0x11000, l2_cache, NULL),
-+	LIMA_IP_DESC(gp,          true,  true,  0x00000, 0x00000, gp,       "gp"),
-+	LIMA_IP_DESC(pp0,         true,  true,  0x08000, 0x08000, pp,       "pp0"),
-+	LIMA_IP_DESC(pp1,         false, false, 0x0A000, 0x0A000, pp,       "pp1"),
-+	LIMA_IP_DESC(pp2,         false, false, 0x0C000, 0x0C000, pp,       "pp2"),
-+	LIMA_IP_DESC(pp3,         false, false, 0x0E000, 0x0E000, pp,       "pp3"),
-+	LIMA_IP_DESC(pp4,         false, false, -1,      0x28000, pp,       "pp4"),
-+	LIMA_IP_DESC(pp5,         false, false, -1,      0x2A000, pp,       "pp5"),
-+	LIMA_IP_DESC(pp6,         false, false, -1,      0x2C000, pp,       "pp6"),
-+	LIMA_IP_DESC(pp7,         false, false, -1,      0x2E000, pp,       "pp7"),
-+	LIMA_IP_DESC(gpmmu,       true,  true,  0x03000, 0x03000, mmu,      "gpmmu"),
-+	LIMA_IP_DESC(ppmmu0,      true,  true,  0x04000, 0x04000, mmu,      "ppmmu0"),
-+	LIMA_IP_DESC(ppmmu1,      false, false, 0x05000, 0x05000, mmu,      "ppmmu1"),
-+	LIMA_IP_DESC(ppmmu2,      false, false, 0x06000, 0x06000, mmu,      "ppmmu2"),
-+	LIMA_IP_DESC(ppmmu3,      false, false, 0x07000, 0x07000, mmu,      "ppmmu3"),
-+	LIMA_IP_DESC(ppmmu4,      false, false, -1,      0x1C000, mmu,      "ppmmu4"),
-+	LIMA_IP_DESC(ppmmu5,      false, false, -1,      0x1D000, mmu,      "ppmmu5"),
-+	LIMA_IP_DESC(ppmmu6,      false, false, -1,      0x1E000, mmu,      "ppmmu6"),
-+	LIMA_IP_DESC(ppmmu7,      false, false, -1,      0x1F000, mmu,      "ppmmu7"),
-+	LIMA_IP_DESC(dlbu,        false, true,  -1,      0x14000, dlbu,     NULL),
-+	LIMA_IP_DESC(bcast,       false, true,  -1,      0x13000, bcast,    NULL),
-+	LIMA_IP_DESC(pp_bcast,    false, true,  -1,      0x16000, pp_bcast, "pp"),
-+	LIMA_IP_DESC(ppmmu_bcast, false, true,  -1,      0x15000, mmu,      NULL),
-+};
-+
-+const char *lima_ip_name(struct lima_ip *ip)
-+{
-+	return lima_ip_desc[ip->id].name;
-+}
-+
-+static int lima_clk_init(struct lima_device *dev)
-+{
-+	int err;
-+	unsigned long bus_rate, gpu_rate;
-+
-+	dev->clk_bus = devm_clk_get(dev->dev, "bus");
-+	if (IS_ERR(dev->clk_bus)) {
-+		dev_err(dev->dev, "get bus clk failed %ld\n", PTR_ERR(dev->clk_bus));
-+		return PTR_ERR(dev->clk_bus);
-+	}
-+
-+	dev->clk_gpu = devm_clk_get(dev->dev, "core");
-+	if (IS_ERR(dev->clk_gpu)) {
-+		dev_err(dev->dev, "get core clk failed %ld\n", PTR_ERR(dev->clk_gpu));
-+		return PTR_ERR(dev->clk_gpu);
-+	}
-+
-+	bus_rate = clk_get_rate(dev->clk_bus);
-+	dev_info(dev->dev, "bus rate = %lu\n", bus_rate);
-+
-+	gpu_rate = clk_get_rate(dev->clk_gpu);
-+	dev_info(dev->dev, "mod rate = %lu", gpu_rate);
-+
-+	if ((err = clk_prepare_enable(dev->clk_bus)))
-+		return err;
-+	if ((err = clk_prepare_enable(dev->clk_gpu)))
-+		goto error_out0;
-+
-+	dev->reset = devm_reset_control_get_optional(dev->dev, NULL);
-+	if (IS_ERR(dev->reset)) {
-+		err = PTR_ERR(dev->reset);
-+		goto error_out1;
-+	} else if (dev->reset != NULL) {
-+		if ((err = reset_control_deassert(dev->reset)))
-+			goto error_out1;
-+	}
-+
-+	return 0;
-+
-+error_out1:
-+	clk_disable_unprepare(dev->clk_gpu);
-+error_out0:
-+	clk_disable_unprepare(dev->clk_bus);
-+	return err;
-+}
-+
-+static void lima_clk_fini(struct lima_device *dev)
-+{
-+	if (dev->reset != NULL)
-+		reset_control_assert(dev->reset);
-+	clk_disable_unprepare(dev->clk_gpu);
-+	clk_disable_unprepare(dev->clk_bus);
-+}
-+
-+static int lima_regulator_init(struct lima_device *dev)
-+{
-+	int ret;
-+	dev->regulator = devm_regulator_get_optional(dev->dev, "mali");
-+	if (IS_ERR(dev->regulator)) {
-+		ret = PTR_ERR(dev->regulator);
-+		dev->regulator = NULL;
-+		if (ret == -ENODEV)
-+			return 0;
-+		dev_err(dev->dev, "failed to get regulator: %ld\n", PTR_ERR(dev->regulator));
-+		return ret;
-+	}
-+
-+	ret = regulator_enable(dev->regulator);
-+	if (ret < 0) {
-+		dev_err(dev->dev, "failed to enable regulator: %d\n", ret);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static void lima_regulator_fini(struct lima_device *dev)
-+{
-+	if (dev->regulator)
-+		regulator_disable(dev->regulator);
-+}
-+
-+static int lima_init_ip(struct lima_device *dev, int index)
-+{
-+	struct lima_ip_desc *desc = lima_ip_desc + index;
-+	struct lima_ip *ip = dev->ip + index;
-+	int offset = desc->offset[dev->id];
-+	bool must = desc->must_have[dev->id];
-+	int err;
-+
-+	if (offset < 0)
-+		return 0;
-+
-+	ip->dev = dev;
-+	ip->id = index;
-+	ip->iomem = dev->iomem + offset;
-+	if (desc->irq_name) {
-+		err = platform_get_irq_byname(dev->pdev, desc->irq_name);
-+		if (err < 0)
-+			goto out;
-+		ip->irq = err;
-+	}
-+
-+	err = desc->init(ip);
-+	if (!err) {
-+		ip->present = true;
-+		return 0;
-+	}
-+
-+out:
-+	return must ? err : 0;
-+}
-+
-+static void lima_fini_ip(struct lima_device *ldev, int index)
-+{
-+	struct lima_ip_desc *desc = lima_ip_desc + index;
-+	struct lima_ip *ip = ldev->ip + index;
-+
-+	if (ip->present)
-+		desc->fini(ip);
-+}
-+
-+static int lima_init_gp_pipe(struct lima_device *dev)
-+{
-+	struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp;
-+	int err;
-+
-+	if ((err = lima_sched_pipe_init(pipe, "gp")))
-+		return err;
-+
-+	pipe->l2_cache[pipe->num_l2_cache++] = dev->ip + lima_ip_l2_cache0;
-+	pipe->mmu[pipe->num_mmu++] = dev->ip + lima_ip_gpmmu;
-+	pipe->processor[pipe->num_processor++] = dev->ip + lima_ip_gp;
-+
-+	if ((err = lima_gp_pipe_init(dev))) {
-+		lima_sched_pipe_fini(pipe);
-+		return err;
-+	}
-+
-+	return 0;
-+}
-+
-+static void lima_fini_gp_pipe(struct lima_device *dev)
-+{
-+	struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp;
-+
-+	lima_gp_pipe_fini(dev);
-+	lima_sched_pipe_fini(pipe);
-+}
-+
-+static int lima_init_pp_pipe(struct lima_device *dev)
-+{
-+	struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
-+	int err, i;
-+
-+	if ((err = lima_sched_pipe_init(pipe, "pp")))
-+		return err;
-+
-+	for (i = 0; i < LIMA_SCHED_PIPE_MAX_PROCESSOR; i++) {
-+		struct lima_ip *pp = dev->ip + lima_ip_pp0 + i;
-+		struct lima_ip *ppmmu = dev->ip + lima_ip_ppmmu0 + i;
-+		struct lima_ip *l2_cache;
-+
-+		if (dev->id == lima_gpu_mali400)
-+			l2_cache = dev->ip + lima_ip_l2_cache0;
-+		else
-+			l2_cache = dev->ip + lima_ip_l2_cache1 + (i >> 2);
-+
-+		if (pp->present && ppmmu->present && l2_cache->present) {
-+			pipe->mmu[pipe->num_mmu++] = ppmmu;
-+			pipe->processor[pipe->num_processor++] = pp;
-+			if (!pipe->l2_cache[i >> 2])
-+				pipe->l2_cache[pipe->num_l2_cache++] = l2_cache;
-+		}
-+	}
-+
-+	if (dev->ip[lima_ip_bcast].present) {
-+		pipe->bcast_processor = dev->ip + lima_ip_pp_bcast;
-+		pipe->bcast_mmu = dev->ip + lima_ip_ppmmu_bcast;
-+	}
-+
-+	if ((err = lima_pp_pipe_init(dev))) {
-+		lima_sched_pipe_fini(pipe);
-+		return err;
-+	}
-+
-+	return 0;
-+}
-+
-+static void lima_fini_pp_pipe(struct lima_device *dev)
-+{
-+	struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
-+
-+	lima_pp_pipe_fini(dev);
-+	lima_sched_pipe_fini(pipe);
-+}
-+
-+int lima_device_init(struct lima_device *ldev)
-+{
-+	int err, i;
-+	struct resource *res;
-+
-+	dma_set_coherent_mask(ldev->dev, DMA_BIT_MASK(32));
-+
-+	err = lima_clk_init(ldev);
-+	if (err) {
-+		dev_err(ldev->dev, "clk init fail %d\n", err);
-+		return err;
-+	}
-+
-+	if ((err = lima_regulator_init(ldev))) {
-+		dev_err(ldev->dev, "regulator init fail %d\n", err);
-+		goto err_out0;
-+	}
-+
-+	err = lima_ttm_init(ldev);
-+	if (err)
-+		goto err_out1;
-+
-+	ldev->empty_vm = lima_vm_create(ldev);
-+	if (!ldev->empty_vm) {
-+		err = -ENOMEM;
-+		goto err_out2;
-+	}
-+
-+	ldev->va_start = 0;
-+	if (ldev->id == lima_gpu_mali450) {
-+		ldev->va_end = LIMA_VA_RESERVE_START;
-+		ldev->dlbu_cpu = dma_alloc_wc(
-+			ldev->dev, LIMA_PAGE_SIZE,
-+			&ldev->dlbu_dma, GFP_KERNEL);
-+		if (!ldev->dlbu_cpu) {
-+			err = -ENOMEM;
-+			goto err_out3;
-+		}
-+	}
-+	else
-+		ldev->va_end = LIMA_VA_RESERVE_END;
-+
-+	res = platform_get_resource(ldev->pdev, IORESOURCE_MEM, 0);
-+	ldev->iomem = devm_ioremap_resource(ldev->dev, res);
-+	if (IS_ERR(ldev->iomem)) {
-+		dev_err(ldev->dev, "fail to ioremap iomem\n");
-+	        err = PTR_ERR(ldev->iomem);
-+		goto err_out4;
-+	}
-+
-+	for (i = 0; i < lima_ip_num; i++) {
-+		err = lima_init_ip(ldev, i);
-+		if (err)
-+			goto err_out5;
-+	}
-+
-+	err = lima_init_gp_pipe(ldev);
-+	if (err)
-+		goto err_out5;
-+
-+	err = lima_init_pp_pipe(ldev);
-+	if (err)
-+		goto err_out6;
-+
-+	if (ldev->id == lima_gpu_mali450) {
-+		lima_dlbu_enable(ldev);
-+		lima_bcast_enable(ldev);
-+	}
-+
-+	return 0;
-+
-+err_out6:
-+	lima_fini_gp_pipe(ldev);
-+err_out5:
-+	while (--i >= 0)
-+		lima_fini_ip(ldev, i);
-+err_out4:
-+	if (ldev->dlbu_cpu)
-+		dma_free_wc(ldev->dev, LIMA_PAGE_SIZE,
-+			    ldev->dlbu_cpu, ldev->dlbu_dma);
-+err_out3:
-+	lima_vm_put(ldev->empty_vm);
-+err_out2:
-+	lima_ttm_fini(ldev);
-+err_out1:
-+	lima_regulator_fini(ldev);
-+err_out0:
-+	lima_clk_fini(ldev);
-+	return err;
-+}
-+
-+void lima_device_fini(struct lima_device *ldev)
-+{
-+	int i;
-+
-+	lima_fini_pp_pipe(ldev);
-+	lima_fini_gp_pipe(ldev);
-+
-+	for (i = lima_ip_num - 1; i >= 0; i--)
-+		lima_fini_ip(ldev, i);
-+
-+	if (ldev->dlbu_cpu)
-+		dma_free_wc(ldev->dev, LIMA_PAGE_SIZE,
-+			    ldev->dlbu_cpu, ldev->dlbu_dma);
-+
-+	lima_vm_put(ldev->empty_vm);
-+
-+	lima_ttm_fini(ldev);
-+
-+	lima_regulator_fini(ldev);
-+
-+	lima_clk_fini(ldev);
-+}
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_device.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_device.h
---- linux-4.17/drivers/gpu/drm/lima/lima_device.h.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_device.h	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,118 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_DEVICE_H__
-+#define __LIMA_DEVICE_H__
-+
-+#include <drm/drm_device.h>
-+
-+#include "lima_sched.h"
-+#include "lima_ttm.h"
-+
-+enum lima_gpu_id {
-+	lima_gpu_mali400 = 0,
-+	lima_gpu_mali450,
-+	lima_gpu_num,
-+};
-+
-+enum lima_ip_id {
-+	lima_ip_pmu,
-+	lima_ip_gpmmu,
-+	lima_ip_ppmmu0,
-+	lima_ip_ppmmu1,
-+	lima_ip_ppmmu2,
-+	lima_ip_ppmmu3,
-+	lima_ip_ppmmu4,
-+	lima_ip_ppmmu5,
-+	lima_ip_ppmmu6,
-+	lima_ip_ppmmu7,
-+	lima_ip_gp,
-+	lima_ip_pp0,
-+	lima_ip_pp1,
-+	lima_ip_pp2,
-+	lima_ip_pp3,
-+	lima_ip_pp4,
-+	lima_ip_pp5,
-+	lima_ip_pp6,
-+	lima_ip_pp7,
-+	lima_ip_l2_cache0,
-+	lima_ip_l2_cache1,
-+	lima_ip_l2_cache2,
-+	lima_ip_dlbu,
-+	lima_ip_bcast,
-+	lima_ip_pp_bcast,
-+	lima_ip_ppmmu_bcast,
-+	lima_ip_num,
-+};
-+
-+struct lima_device;
-+
-+struct lima_ip {
-+	struct lima_device *dev;
-+	enum lima_ip_id id;
-+	bool present;
-+
-+	void __iomem *iomem;
-+	int irq;
-+
-+	union {
-+		/* pmu */
-+		unsigned switch_delay;
-+		/* gp/pp */
-+		bool async_reset;
-+		/* l2 cache */
-+		spinlock_t lock;
-+	} data;
-+};
-+
-+enum lima_pipe_id {
-+	lima_pipe_gp,
-+	lima_pipe_pp,
-+	lima_pipe_num,
-+};
-+
-+struct lima_device {
-+	struct device *dev;
-+	struct drm_device *ddev;
-+	struct platform_device *pdev;
-+
-+	enum lima_gpu_id id;
-+	int num_pp;
-+
-+	void __iomem *iomem;
-+	struct clk *clk_bus;
-+	struct clk *clk_gpu;
-+	struct reset_control *reset;
-+	struct regulator *regulator;
-+
-+	struct lima_ip ip[lima_ip_num];
-+	struct lima_sched_pipe pipe[lima_pipe_num];
-+
-+	struct lima_mman mman;
-+
-+	struct lima_vm *empty_vm;
-+	uint64_t va_start;
-+	uint64_t va_end;
-+
-+	u32 *dlbu_cpu;
-+	dma_addr_t dlbu_dma;
-+};
-+
-+static inline struct lima_device *
-+to_lima_dev(struct drm_device *dev)
-+{
-+	return dev->dev_private;
-+}
-+
-+static inline struct lima_device *
-+ttm_to_lima_dev(struct ttm_bo_device *dev)
-+{
-+	return container_of(dev, struct lima_device, mman.bdev);
-+}
-+
-+int lima_device_init(struct lima_device *ldev);
-+void lima_device_fini(struct lima_device *ldev);
-+
-+const char *lima_ip_name(struct lima_ip *ip);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_dlbu.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_dlbu.c
---- linux-4.17/drivers/gpu/drm/lima/lima_dlbu.c.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_dlbu.c	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,56 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <linux/io.h>
-+#include <linux/device.h>
-+
-+#include "lima_device.h"
-+#include "lima_dlbu.h"
-+#include "lima_vm.h"
-+#include "lima_regs.h"
-+
-+#define dlbu_write(reg, data) writel(data, ip->iomem + LIMA_DLBU_##reg)
-+#define dlbu_read(reg) readl(ip->iomem + LIMA_DLBU_##reg)
-+
-+void lima_dlbu_enable(struct lima_device *dev)
-+{
-+	struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
-+	struct lima_ip *ip = dev->ip + lima_ip_dlbu;
-+	int i, mask = 0;
-+
-+	for (i = 0; i < pipe->num_processor; i++) {
-+		struct lima_ip *pp = pipe->processor[i];
-+		mask |= 1 << (pp->id - lima_ip_pp0);
-+	}
-+
-+	dlbu_write(PP_ENABLE_MASK, mask);
-+}
-+
-+void lima_dlbu_disable(struct lima_device *dev)
-+{
-+	struct lima_ip *ip = dev->ip + lima_ip_dlbu;
-+	dlbu_write(PP_ENABLE_MASK, 0);
-+}
-+
-+void lima_dlbu_set_reg(struct lima_ip *ip, u32 *reg)
-+{
-+	dlbu_write(TLLIST_VBASEADDR, reg[0]);
-+	dlbu_write(FB_DIM, reg[1]);
-+	dlbu_write(TLLIST_CONF, reg[2]);
-+	dlbu_write(START_TILE_POS, reg[3]);
-+}
-+
-+int lima_dlbu_init(struct lima_ip *ip)
-+{
-+	struct lima_device *dev = ip->dev;
-+
-+	dlbu_write(MASTER_TLLIST_PHYS_ADDR, dev->dlbu_dma | 1);
-+	dlbu_write(MASTER_TLLIST_VADDR, LIMA_VA_RESERVE_DLBU);
-+
-+	return 0;
-+}
-+
-+void lima_dlbu_fini(struct lima_ip *ip)
-+{
-+	
-+}
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_dlbu.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_dlbu.h
---- linux-4.17/drivers/gpu/drm/lima/lima_dlbu.h.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_dlbu.h	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,18 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_DLBU_H__
-+#define __LIMA_DLBU_H__
-+
-+struct lima_ip;
-+struct lima_device;
-+
-+void lima_dlbu_enable(struct lima_device *dev);
-+void lima_dlbu_disable(struct lima_device *dev);
-+
-+void lima_dlbu_set_reg(struct lima_ip *ip, u32 *reg);
-+
-+int lima_dlbu_init(struct lima_ip *ip);
-+void lima_dlbu_fini(struct lima_ip *ip);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_drv.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_drv.c
---- linux-4.17/drivers/gpu/drm/lima/lima_drv.c.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_drv.c	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,453 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/log2.h>
-+#include <drm/drm_prime.h>
-+#include <drm/lima_drm.h>
-+
-+#include "lima_drv.h"
-+#include "lima_gem.h"
-+#include "lima_gem_prime.h"
-+#include "lima_vm.h"
-+
-+int lima_sched_timeout_ms = 0;
-+int lima_sched_max_tasks = 32;
-+int lima_max_mem = -1;
-+
-+MODULE_PARM_DESC(sched_timeout_ms, "task run timeout in ms (0 = no timeout (default))");
-+module_param_named(sched_timeout_ms, lima_sched_timeout_ms, int, 0444);
-+
-+MODULE_PARM_DESC(sched_max_tasks, "max queued task num in a context (default 32)");
-+module_param_named(sched_max_tasks, lima_sched_max_tasks, int, 0444);
-+
-+MODULE_PARM_DESC(max_mem, "Max memory size in MB can be used (<0 = auto)");
-+module_param_named(max_mem, lima_max_mem, int, 0444);
-+
-+static int lima_ioctl_info(struct drm_device *dev, void *data, struct drm_file *file)
-+{
-+	struct drm_lima_info *info = data;
-+	struct lima_device *ldev = to_lima_dev(dev);
-+
-+	switch (ldev->id) {
-+	case lima_gpu_mali400:
-+		info->gpu_id = LIMA_INFO_GPU_MALI400;
-+		break;
-+	case lima_gpu_mali450:
-+		info->gpu_id = LIMA_INFO_GPU_MALI450;
-+		break;
-+	default:
-+		return -ENODEV;
-+	}
-+	info->num_pp = ldev->pipe[lima_pipe_pp].num_processor;
-+	info->va_start = ldev->va_start;
-+	info->va_end = ldev->va_end;
-+	return 0;
-+}
-+
-+static int lima_ioctl_gem_create(struct drm_device *dev, void *data, struct drm_file *file)
-+{
-+	struct drm_lima_gem_create *args = data;
-+
-+	if (args->flags)
-+		return -EINVAL;
-+
-+	if (args->size == 0)
-+		return -EINVAL;
-+
-+	return lima_gem_create_handle(dev, file, args->size, args->flags, &args->handle);
-+}
-+
-+static int lima_ioctl_gem_info(struct drm_device *dev, void *data, struct drm_file *file)
-+{
-+	struct drm_lima_gem_info *args = data;
-+
-+	return lima_gem_mmap_offset(file, args->handle, &args->offset);
-+}
-+
-+static int lima_ioctl_gem_va(struct drm_device *dev, void *data, struct drm_file *file)
-+{
-+	struct drm_lima_gem_va *args = data;
-+
-+	switch (args->op) {
-+	case LIMA_VA_OP_MAP:
-+		return lima_gem_va_map(file, args->handle, args->flags, args->va);
-+	case LIMA_VA_OP_UNMAP:
-+		return lima_gem_va_unmap(file, args->handle, args->va);
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
-+static int lima_ioctl_gem_submit(struct drm_device *dev, void *data, struct drm_file *file)
-+{
-+	struct drm_lima_gem_submit_in *args = data;
-+	struct lima_device *ldev = to_lima_dev(dev);
-+	struct lima_drm_priv *priv = file->driver_priv;
-+	struct drm_lima_gem_submit_bo *bos;
-+	struct ttm_validate_buffer *vbs;
-+	union drm_lima_gem_submit_dep *deps = NULL;
-+	struct lima_sched_pipe *pipe;
-+	struct lima_sched_task *task;
-+	struct lima_ctx *ctx;
-+	struct lima_submit submit = {0};
-+	int err = 0, size;
-+
-+	if (args->pipe >= lima_pipe_num || args->nr_bos == 0)
-+		return -EINVAL;
-+
-+	if (args->flags & ~(LIMA_SUBMIT_FLAG_EXPLICIT_FENCE |
-+			    LIMA_SUBMIT_FLAG_SYNC_FD_OUT))
-+		return -EINVAL;
-+
-+	pipe = ldev->pipe + args->pipe;
-+	if (args->frame_size != pipe->frame_size)
-+		return -EINVAL;
-+
-+	size = args->nr_bos * (sizeof(*submit.bos) + sizeof(*submit.vbs)) +
-+		args->nr_deps * sizeof(*submit.deps);
-+	bos = kzalloc(size, GFP_KERNEL);
-+	if (!bos)
-+		return -ENOMEM;
-+
-+	size = args->nr_bos * sizeof(*submit.bos);
-+	if (copy_from_user(bos, u64_to_user_ptr(args->bos), size)) {
-+		err = -EFAULT;
-+		goto out0;
-+	}
-+
-+	vbs = (void *)bos + size;
-+
-+	if (args->nr_deps) {
-+		deps = (void *)vbs + args->nr_bos * sizeof(*submit.vbs);
-+		size = args->nr_deps * sizeof(*submit.deps);
-+		if (copy_from_user(deps, u64_to_user_ptr(args->deps), size)) {
-+			err = -EFAULT;
-+			goto out0;
-+		}
-+	}
-+
-+	task = kmem_cache_zalloc(pipe->task_slab, GFP_KERNEL);
-+	if (!task) {
-+		err = -ENOMEM;
-+		goto out0;
-+	}
-+
-+	task->frame = task + 1;
-+	if (copy_from_user(task->frame, u64_to_user_ptr(args->frame), args->frame_size)) {
-+		err = -EFAULT;
-+		goto out1;
-+	}
-+
-+	err = pipe->task_validate(pipe, task);
-+	if (err)
-+		goto out1;
-+
-+	ctx = lima_ctx_get(&priv->ctx_mgr, args->ctx);
-+	if (!ctx) {
-+		err = -ENOENT;
-+		goto out1;
-+	}
-+
-+	submit.pipe = args->pipe;
-+	submit.bos = bos;
-+	submit.vbs = vbs;
-+	submit.nr_bos = args->nr_bos;
-+	submit.task = task;
-+	submit.ctx = ctx;
-+	submit.deps = deps;
-+	submit.nr_deps = args->nr_deps;
-+	submit.flags = args->flags;
-+
-+	err = lima_gem_submit(file, &submit);
-+	if (!err) {
-+		struct drm_lima_gem_submit_out *out = data;
-+		out->fence = submit.fence;
-+		out->done = submit.done;
-+		out->sync_fd = submit.sync_fd;
-+	}
-+
-+	lima_ctx_put(ctx);
-+out1:
-+	if (err)
-+		kmem_cache_free(pipe->task_slab, task);
-+out0:
-+	kfree(bos);
-+	return err;
-+}
-+
-+static int lima_wait_fence(struct dma_fence *fence, u64 timeout_ns)
-+{
-+	signed long ret;
-+
-+	if (!timeout_ns)
-+		ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
-+	else {
-+		unsigned long timeout = lima_timeout_to_jiffies(timeout_ns);
-+
-+		/* must use long for result check because in 64bit arch int
-+		 * will overflow if timeout is too large and get <0 result
-+		 */
-+		ret = dma_fence_wait_timeout(fence, true, timeout);
-+		if (ret == 0)
-+			ret = timeout ? -ETIMEDOUT : -EBUSY;
-+		else if (ret > 0)
-+			ret = 0;
-+	}
-+
-+	return ret;
-+}
-+
-+static int lima_ioctl_wait_fence(struct drm_device *dev, void *data, struct drm_file *file)
-+{
-+	struct drm_lima_wait_fence *args = data;
-+	struct lima_drm_priv *priv = file->driver_priv;
-+	struct dma_fence *fence;
-+	int err = 0;
-+
-+	fence = lima_ctx_get_native_fence(&priv->ctx_mgr, args->ctx,
-+					  args->pipe, args->seq);
-+	if (IS_ERR(fence))
-+		return PTR_ERR(fence);
-+
-+	if (fence) {
-+		err = lima_wait_fence(fence, args->timeout_ns);
-+		dma_fence_put(fence);
-+	}
-+
-+	return err;
-+}
-+
-+static int lima_ioctl_gem_wait(struct drm_device *dev, void *data, struct drm_file *file)
-+{
-+	struct drm_lima_gem_wait *args = data;
-+
-+	if (!(args->op & (LIMA_GEM_WAIT_READ|LIMA_GEM_WAIT_WRITE)))
-+	    return -EINVAL;
-+
-+	return lima_gem_wait(file, args->handle, args->op, args->timeout_ns);
-+}
-+
-+static int lima_ioctl_ctx(struct drm_device *dev, void *data, struct drm_file *file)
-+{
-+	struct drm_lima_ctx *args = data;
-+	struct lima_drm_priv *priv = file->driver_priv;
-+	struct lima_device *ldev = to_lima_dev(dev);
-+
-+	if (args->op == LIMA_CTX_OP_CREATE)
-+		return lima_ctx_create(ldev, &priv->ctx_mgr, &args->id);
-+	else if (args->op == LIMA_CTX_OP_FREE)
-+		return lima_ctx_free(&priv->ctx_mgr, args->id);
-+
-+	return -EINVAL;
-+}
-+
-+static int lima_ioctl_gem_mod(struct drm_device *dev, void *data, struct drm_file *file)
-+{
-+	struct drm_lima_gem_mod *args = data;
-+
-+	if (args->op == LIMA_GEM_MOD_OP_GET)
-+		return lima_gem_get_modifier(file, args->handle, &args->modifier);
-+	else if (args->op == LIMA_GEM_MOD_OP_SET)
-+		return lima_gem_set_modifier(file, args->handle, args->modifier);
-+
-+	return -EINVAL;
-+}
-+
-+static int lima_drm_driver_open(struct drm_device *dev, struct drm_file *file)
-+{
-+	int err;
-+	struct lima_drm_priv *priv;
-+	struct lima_device *ldev = to_lima_dev(dev);
-+
-+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	priv->vm = lima_vm_create(ldev);
-+	if (!priv->vm) {
-+		err = -ENOMEM;
-+		goto err_out0;
-+	}
-+
-+        lima_ctx_mgr_init(&priv->ctx_mgr);
-+
-+	file->driver_priv = priv;
-+	return 0;
-+
-+err_out0:
-+	kfree(priv);
-+	return err;
-+}
-+
-+static void lima_drm_driver_postclose(struct drm_device *dev, struct drm_file *file)
-+{
-+	struct lima_drm_priv *priv = file->driver_priv;
-+
-+	lima_ctx_mgr_fini(&priv->ctx_mgr);
-+	lima_vm_put(priv->vm);
-+	kfree(priv);
-+}
-+
-+static const struct drm_ioctl_desc lima_drm_driver_ioctls[] = {
-+	DRM_IOCTL_DEF_DRV(LIMA_INFO, lima_ioctl_info, DRM_AUTH|DRM_RENDER_ALLOW),
-+	DRM_IOCTL_DEF_DRV(LIMA_GEM_CREATE, lima_ioctl_gem_create, DRM_AUTH|DRM_RENDER_ALLOW),
-+	DRM_IOCTL_DEF_DRV(LIMA_GEM_INFO, lima_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
-+	DRM_IOCTL_DEF_DRV(LIMA_GEM_VA, lima_ioctl_gem_va, DRM_AUTH|DRM_RENDER_ALLOW),
-+	DRM_IOCTL_DEF_DRV(LIMA_GEM_SUBMIT, lima_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
-+	DRM_IOCTL_DEF_DRV(LIMA_WAIT_FENCE, lima_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
-+	DRM_IOCTL_DEF_DRV(LIMA_GEM_WAIT, lima_ioctl_gem_wait, DRM_AUTH|DRM_RENDER_ALLOW),
-+	DRM_IOCTL_DEF_DRV(LIMA_CTX, lima_ioctl_ctx, DRM_AUTH|DRM_RENDER_ALLOW),
-+	DRM_IOCTL_DEF_DRV(LIMA_GEM_MOD, lima_ioctl_gem_mod, DRM_AUTH|DRM_RENDER_ALLOW),
-+};
-+
-+static const struct file_operations lima_drm_driver_fops = {
-+	.owner              = THIS_MODULE,
-+	.open               = drm_open,
-+	.release            = drm_release,
-+	.unlocked_ioctl     = drm_ioctl,
-+#ifdef CONFIG_COMPAT
-+	.compat_ioctl       = drm_compat_ioctl,
-+#endif
-+	.mmap               = lima_gem_mmap,
-+};
-+
-+static struct drm_driver lima_drm_driver = {
-+	.driver_features    = DRIVER_RENDER | DRIVER_GEM | DRIVER_PRIME,
-+	.open               = lima_drm_driver_open,
-+	.postclose          = lima_drm_driver_postclose,
-+	.ioctls             = lima_drm_driver_ioctls,
-+	.num_ioctls         = ARRAY_SIZE(lima_drm_driver_ioctls),
-+	.fops               = &lima_drm_driver_fops,
-+	.gem_free_object_unlocked = lima_gem_free_object,
-+	.gem_open_object    = lima_gem_object_open,
-+	.gem_close_object   = lima_gem_object_close,
-+	.name               = "lima",
-+	.desc               = "lima DRM",
-+	.date               = "20170325",
-+	.major              = 1,
-+	.minor              = 0,
-+	.patchlevel         = 0,
-+
-+	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
-+	.gem_prime_import   = drm_gem_prime_import,
-+	.gem_prime_import_sg_table = lima_gem_prime_import_sg_table,
-+	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
-+	.gem_prime_export   = drm_gem_prime_export,
-+	.gem_prime_res_obj  = lima_gem_prime_res_obj,
-+	.gem_prime_get_sg_table = lima_gem_prime_get_sg_table,
-+};
-+
-+static int lima_pdev_probe(struct platform_device *pdev)
-+{
-+	struct lima_device *ldev;
-+	struct drm_device *ddev;
-+	int err;
-+
-+	ldev = devm_kzalloc(&pdev->dev, sizeof(*ldev), GFP_KERNEL);
-+	if (!ldev)
-+		return -ENOMEM;
-+
-+	ldev->pdev = pdev;
-+	ldev->dev = &pdev->dev;
-+	ldev->id = (enum lima_gpu_id)of_device_get_match_data(&pdev->dev);
-+
-+	platform_set_drvdata(pdev, ldev);
-+
-+	/* Allocate and initialize the DRM device. */
-+	ddev = drm_dev_alloc(&lima_drm_driver, &pdev->dev);
-+	if (IS_ERR(ddev))
-+		return PTR_ERR(ddev);
-+
-+	ddev->dev_private = ldev;
-+	ldev->ddev = ddev;
-+
-+	err = lima_device_init(ldev);
-+	if (err) {
-+		dev_err(&pdev->dev, "Fatal error during GPU init\n");
-+		goto err_out0;
-+	}
-+
-+	/*
-+	 * Register the DRM device with the core and the connectors with
-+	 * sysfs.
-+	 */
-+	err = drm_dev_register(ddev, 0);
-+	if (err < 0)
-+		goto err_out1;
-+
-+	return 0;
-+
-+err_out1:
-+	lima_device_fini(ldev);
-+err_out0:
-+	drm_dev_unref(ddev);
-+	return err;
-+}
-+
-+static int lima_pdev_remove(struct platform_device *pdev)
-+{
-+	struct lima_device *ldev = platform_get_drvdata(pdev);
-+	struct drm_device *ddev = ldev->ddev;
-+
-+	drm_dev_unregister(ddev);
-+	lima_device_fini(ldev);
-+	drm_dev_unref(ddev);
-+	return 0;
-+}
-+
-+static const struct of_device_id dt_match[] = {
-+	{ .compatible = "arm,mali-400", .data = (void *)lima_gpu_mali400 },
-+	{ .compatible = "arm,mali-450", .data = (void *)lima_gpu_mali450 },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, dt_match);
-+
-+static struct platform_driver lima_platform_driver = {
-+	.probe      = lima_pdev_probe,
-+	.remove     = lima_pdev_remove,
-+	.driver     = {
-+		.name   = "lima",
-+		.of_match_table = dt_match,
-+	},
-+};
-+
-+static void lima_check_module_param(void)
-+{
-+	if (lima_sched_max_tasks < 4)
-+		lima_sched_max_tasks = 4;
-+	else
-+		lima_sched_max_tasks = roundup_pow_of_two(lima_sched_max_tasks);
-+
-+	if (lima_max_mem < 32)
-+		lima_max_mem = -1;
-+}
-+
-+static int __init lima_init(void)
-+{
-+	int ret;
-+
-+	lima_check_module_param();
-+	ret = lima_sched_slab_init();
-+	if (ret)
-+		return ret;
-+
-+	ret = platform_driver_register(&lima_platform_driver);
-+	if (ret)
-+		lima_sched_slab_fini();
-+
-+	return ret;
-+}
-+module_init(lima_init);
-+
-+static void __exit lima_exit(void)
-+{
-+	platform_driver_unregister(&lima_platform_driver);
-+	lima_sched_slab_fini();
-+}
-+module_exit(lima_exit);
-+
-+MODULE_AUTHOR("Lima Project Developers");
-+MODULE_DESCRIPTION("Lima DRM Driver");
-+MODULE_LICENSE("GPL v2");
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_drv.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_drv.h
---- linux-4.17/drivers/gpu/drm/lima/lima_drv.h.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_drv.h	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,59 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_DRV_H__
-+#define __LIMA_DRV_H__
-+
-+#include <drm/drmP.h>
-+#include <drm/ttm/ttm_execbuf_util.h>
-+
-+#include "lima_ctx.h"
-+
-+extern int lima_sched_timeout_ms;
-+extern int lima_sched_max_tasks;
-+extern int lima_max_mem;
-+
-+struct lima_vm;
-+struct lima_bo;
-+struct lima_sched_task;
-+
-+struct drm_lima_gem_submit_bo;
-+
-+#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
-+
-+struct lima_drm_priv {
-+	struct lima_vm *vm;
-+	struct lima_ctx_mgr ctx_mgr;
-+};
-+
-+struct lima_submit {
-+	struct lima_ctx *ctx;
-+	int pipe;
-+	u32 flags;
-+
-+	struct drm_lima_gem_submit_bo *bos;
-+	struct ttm_validate_buffer *vbs;
-+	u32 nr_bos;
-+
-+	struct ttm_validate_buffer vm_pd_vb;
-+	struct ww_acquire_ctx ticket;
-+	struct list_head duplicates;
-+	struct list_head validated;
-+
-+	union drm_lima_gem_submit_dep *deps;
-+	u32 nr_deps;
-+
-+	struct lima_sched_task *task;
-+
-+	uint32_t fence;
-+	uint32_t done;
-+	int sync_fd;
-+};
-+
-+static inline struct lima_drm_priv *
-+to_lima_drm_priv(struct drm_file *file)
-+{
-+	return file->driver_priv;
-+}
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_gem.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_gem.c
---- linux-4.17/drivers/gpu/drm/lima/lima_gem.c.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_gem.c	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,478 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <drm/drmP.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/pagemap.h>
-+#include <linux/sync_file.h>
-+
-+#include <drm/lima_drm.h>
-+
-+#include "lima_drv.h"
-+#include "lima_gem.h"
-+#include "lima_vm.h"
-+#include "lima_object.h"
-+
-+int lima_gem_create_handle(struct drm_device *dev, struct drm_file *file,
-+			   u32 size, u32 flags, u32 *handle)
-+{
-+	int err;
-+	struct lima_bo *bo;
-+	struct lima_device *ldev = to_lima_dev(dev);
-+
-+	bo = lima_bo_create(ldev, size, flags, ttm_bo_type_device, NULL, NULL);
-+	if (IS_ERR(bo))
-+		return PTR_ERR(bo);
-+
-+	err = drm_gem_handle_create(file, &bo->gem, handle);
-+
-+	/* drop reference from allocate - handle holds it now */
-+	drm_gem_object_put_unlocked(&bo->gem);
-+
-+	return err;
-+}
-+
-+void lima_gem_free_object(struct drm_gem_object *obj)
-+{
-+	struct lima_bo *bo = to_lima_bo(obj);
-+
-+	if (!list_empty(&bo->va))
-+		dev_err(obj->dev->dev, "lima gem free bo still has va\n");
-+
-+	lima_bo_unref(bo);
-+}
-+
-+int lima_gem_object_open(struct drm_gem_object *obj, struct drm_file *file)
-+{
-+	struct lima_bo *bo = to_lima_bo(obj);
-+	struct lima_drm_priv *priv = to_lima_drm_priv(file);
-+	struct lima_vm *vm = priv->vm;
-+	int err;
-+
-+	err = lima_bo_reserve(bo, true);
-+	if (err)
-+		return err;
-+
-+	err = lima_vm_bo_add(vm, bo);
-+
-+	lima_bo_unreserve(bo);
-+	return err;
-+}
-+
-+void lima_gem_object_close(struct drm_gem_object *obj, struct drm_file *file)
-+{
-+	struct lima_bo *bo = to_lima_bo(obj);
-+	struct lima_device *dev = to_lima_dev(obj->dev);
-+	struct lima_drm_priv *priv = to_lima_drm_priv(file);
-+	struct lima_vm *vm = priv->vm;
-+
-+	LIST_HEAD(list);
-+	struct ttm_validate_buffer tv_bo, tv_pd;
-+	struct ww_acquire_ctx ticket;
-+	int r;
-+
-+	tv_bo.bo = &bo->tbo;
-+	tv_bo.shared = true;
-+	list_add(&tv_bo.head, &list);
-+
-+	tv_pd.bo = &vm->pd->tbo;
-+	tv_pd.shared = true;
-+	list_add(&tv_pd.head, &list);
-+
-+	r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
-+	if (r) {
-+		dev_err(dev->dev, "leeking bo va because we "
-+			"fail to reserve bo (%d)\n", r);
-+		return;
-+	}
-+
-+	lima_vm_bo_del(vm, bo);
-+
-+	ttm_eu_backoff_reservation(&ticket, &list);
-+}
-+
-+int lima_gem_mmap_offset(struct drm_file *file, u32 handle, u64 *offset)
-+{
-+	struct drm_gem_object *obj;
-+	struct lima_bo *bo;
-+
-+	obj = drm_gem_object_lookup(file, handle);
-+	if (!obj)
-+		return -ENOENT;
-+
-+	bo = to_lima_bo(obj);
-+	*offset = drm_vma_node_offset_addr(&bo->tbo.vma_node);
-+
-+	drm_gem_object_put_unlocked(obj);
-+	return 0;
-+}
-+
-+int lima_gem_mmap(struct file *filp, struct vm_area_struct *vma)
-+{
-+	struct drm_file *file_priv;
-+	struct lima_device *dev;
-+
-+	if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
-+		return -EINVAL;
-+
-+	file_priv = filp->private_data;
-+	dev = file_priv->minor->dev->dev_private;
-+	if (dev == NULL)
-+		return -EINVAL;
-+
-+	return ttm_bo_mmap(filp, vma, &dev->mman.bdev);
-+}
-+
-+int lima_gem_va_map(struct drm_file *file, u32 handle, u32 flags, u32 va)
-+{
-+	struct lima_drm_priv *priv = to_lima_drm_priv(file);
-+	struct lima_vm *vm = priv->vm;
-+	struct drm_gem_object *obj;
-+	struct lima_bo *bo;
-+	struct lima_device *dev;
-+	int err;
-+
-+	LIST_HEAD(list);
-+	struct ttm_validate_buffer tv_bo, tv_pd;
-+	struct ww_acquire_ctx ticket;
-+
-+	if (!PAGE_ALIGNED(va))
-+		return -EINVAL;
-+
-+	obj = drm_gem_object_lookup(file, handle);
-+	if (!obj)
-+		return -ENOENT;
-+
-+	bo = to_lima_bo(obj);
-+	dev = to_lima_dev(obj->dev);
-+
-+	/* carefully handle overflow when calculate range */
-+	if (va < dev->va_start || dev->va_end - obj->size < va) {
-+		err = -EINVAL;
-+		goto out;
-+	}
-+
-+	tv_bo.bo = &bo->tbo;
-+	tv_bo.shared = true;
-+	list_add(&tv_bo.head, &list);
-+
-+	tv_pd.bo = &vm->pd->tbo;
-+	tv_pd.shared = true;
-+	list_add(&tv_pd.head, &list);
-+
-+	err = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
-+	if (err)
-+		goto out;
-+
-+	err = lima_vm_bo_map(vm, bo, va);
-+
-+	ttm_eu_backoff_reservation(&ticket, &list);
-+out:
-+	drm_gem_object_put_unlocked(obj);
-+	return err;
-+}
-+
-+int lima_gem_va_unmap(struct drm_file *file, u32 handle, u32 va)
-+{
-+	struct lima_drm_priv *priv = to_lima_drm_priv(file);
-+	struct lima_vm *vm = priv->vm;
-+	struct drm_gem_object *obj;
-+	struct lima_bo *bo;
-+	int err;
-+
-+	LIST_HEAD(list);
-+	struct ttm_validate_buffer tv_bo, tv_pd;
-+	struct ww_acquire_ctx ticket;
-+
-+	if (!PAGE_ALIGNED(va))
-+		return -EINVAL;
-+
-+	obj = drm_gem_object_lookup(file, handle);
-+	if (!obj)
-+		return -ENOENT;
-+
-+	bo = to_lima_bo(obj);
-+
-+	tv_bo.bo = &bo->tbo;
-+	tv_bo.shared = true;
-+	list_add(&tv_bo.head, &list);
-+
-+	tv_pd.bo = &vm->pd->tbo;
-+	tv_pd.shared = true;
-+	list_add(&tv_pd.head, &list);
-+
-+	err = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
-+	if (err)
-+		goto out;
-+
-+	err = lima_vm_bo_unmap(vm, bo, va);
-+
-+	ttm_eu_backoff_reservation(&ticket, &list);
-+out:
-+	drm_gem_object_put_unlocked(obj);
-+	return err;
-+}
-+
-+static int lima_gem_sync_bo(struct lima_sched_task *task, struct lima_bo *bo,
-+			    bool write, bool explicit)
-+{
-+	int err = 0;
-+
-+	if (!write) {
-+		err = reservation_object_reserve_shared(bo->tbo.resv);
-+		if (err)
-+			return err;
-+	}
-+
-+	/* explicit sync use user passed dep fence */
-+	if (explicit)
-+		return 0;
-+
-+	/* implicit sync use bo fence in resv obj */
-+	if (write) {
-+		unsigned nr_fences;
-+		struct dma_fence **fences;
-+		int i;
-+
-+		err = reservation_object_get_fences_rcu(
-+			bo->tbo.resv, NULL, &nr_fences, &fences);
-+		if (err || !nr_fences)
-+			return err;
-+
-+		for (i = 0; i < nr_fences; i++) {
-+			err = lima_sched_task_add_dep(task, fences[i]);
-+			if (err)
-+				break;
-+		}
-+
-+		/* for error case free remaining fences */
-+		for ( ; i < nr_fences; i++)
-+			dma_fence_put(fences[i]);
-+
-+		kfree(fences);
-+	}
-+	else {
-+		struct dma_fence *fence;
-+		fence = reservation_object_get_excl_rcu(bo->tbo.resv);
-+		if (fence) {
-+			err = lima_sched_task_add_dep(task, fence);
-+			if (err)
-+				dma_fence_put(fence);
-+		}
-+	}
-+
-+	return err;
-+}
-+
-+static int lima_gem_add_deps(struct lima_ctx_mgr *mgr, struct lima_submit *submit)
-+{
-+	int i, err = 0;
-+
-+	for (i = 0; i < submit->nr_deps; i++) {
-+		union drm_lima_gem_submit_dep *dep = submit->deps + i;
-+		struct dma_fence *fence;
-+
-+		if (dep->type == LIMA_SUBMIT_DEP_FENCE) {
-+			fence = lima_ctx_get_native_fence(
-+				mgr, dep->fence.ctx, dep->fence.pipe,
-+				dep->fence.seq);
-+			if (IS_ERR(fence)) {
-+				err = PTR_ERR(fence);
-+				break;
-+			}
-+		}
-+		else if (dep->type == LIMA_SUBMIT_DEP_SYNC_FD) {
-+			fence = sync_file_get_fence(dep->sync_fd.fd);
-+			if (!fence) {
-+				err = -EINVAL;
-+				break;
-+			}
-+		}
-+		else {
-+			err = -EINVAL;
-+			break;
-+		}
-+
-+		if (fence) {
-+			err = lima_sched_task_add_dep(submit->task, fence);
-+			if (err) {
-+				dma_fence_put(fence);
-+				break;
-+			}
-+		}
-+	}
-+
-+	return err;
-+}
-+
-+static int lima_gem_get_sync_fd(struct dma_fence *fence)
-+{
-+	struct sync_file *sync_file;
-+	int fd;
-+
-+	fd = get_unused_fd_flags(O_CLOEXEC);
-+	if (fd < 0)
-+		return fd;
-+
-+	sync_file = sync_file_create(fence);
-+	if (!sync_file) {
-+		put_unused_fd(fd);
-+		return -ENOMEM;
-+	}
-+
-+	fd_install(fd, sync_file->file);
-+	return fd;
-+}
-+
-+int lima_gem_submit(struct drm_file *file, struct lima_submit *submit)
-+{
-+	int i, err = 0;
-+	struct lima_drm_priv *priv = to_lima_drm_priv(file);
-+	struct lima_vm *vm = priv->vm;
-+
-+	INIT_LIST_HEAD(&submit->validated);
-+	INIT_LIST_HEAD(&submit->duplicates);
-+
-+	for (i = 0; i < submit->nr_bos; i++) {
-+		struct drm_gem_object *obj;
-+		struct drm_lima_gem_submit_bo *bo = submit->bos + i;
-+		struct ttm_validate_buffer *vb = submit->vbs + i;
-+
-+		obj = drm_gem_object_lookup(file, bo->handle);
-+		if (!obj) {
-+			err = -ENOENT;
-+			goto out0;
-+		}
-+
-+		vb->bo = &to_lima_bo(obj)->tbo;
-+		vb->shared = !(bo->flags & LIMA_SUBMIT_BO_WRITE);
-+		list_add_tail(&vb->head, &submit->validated);
-+	}
-+
-+	submit->vm_pd_vb.bo = &vm->pd->tbo;
-+	submit->vm_pd_vb.shared = true;
-+	list_add(&submit->vm_pd_vb.head, &submit->validated);
-+
-+	err = ttm_eu_reserve_buffers(&submit->ticket, &submit->validated,
-+				     true, &submit->duplicates);
-+	if (err)
-+		goto out0;
-+
-+	err = lima_sched_task_init(
-+		submit->task, submit->ctx->context + submit->pipe, vm);
-+	if (err)
-+		goto out1;
-+
-+	err = lima_gem_add_deps(&priv->ctx_mgr, submit);
-+	if (err)
-+		goto out2;
-+
-+	for (i = 0; i < submit->nr_bos; i++) {
-+		struct ttm_validate_buffer *vb = submit->vbs + i;
-+		struct lima_bo *bo = ttm_to_lima_bo(vb->bo);
-+		err = lima_gem_sync_bo(
-+			submit->task, bo, !vb->shared,
-+			submit->flags & LIMA_SUBMIT_FLAG_EXPLICIT_FENCE);
-+		if (err)
-+			goto out2;
-+	}
-+
-+	if (submit->flags & LIMA_SUBMIT_FLAG_SYNC_FD_OUT) {
-+		int fd = lima_gem_get_sync_fd(
-+			&submit->task->base.s_fence->finished);
-+		if (fd < 0) {
-+			err = fd;
-+			goto out2;
-+		}
-+		submit->sync_fd = fd;
-+	}
-+
-+	submit->fence = lima_sched_context_queue_task(
-+		submit->ctx->context + submit->pipe, submit->task,
-+		&submit->done);
-+
-+	ttm_eu_fence_buffer_objects(&submit->ticket, &submit->validated,
-+				    &submit->task->base.s_fence->finished);
-+
-+out2:
-+	if (err)
-+		lima_sched_task_fini(submit->task);
-+out1:
-+        if (err)
-+		ttm_eu_backoff_reservation(&submit->ticket, &submit->validated);
-+out0:
-+	for (i = 0; i < submit->nr_bos; i++) {
-+		struct ttm_validate_buffer *vb = submit->vbs + i;
-+		if (!vb->bo)
-+			break;
-+		drm_gem_object_put_unlocked(&ttm_to_lima_bo(vb->bo)->gem);
-+	}
-+	return err;
-+}
-+
-+int lima_gem_wait(struct drm_file *file, u32 handle, u32 op, u64 timeout_ns)
-+{
-+	bool write = op & LIMA_GEM_WAIT_WRITE;
-+	struct drm_gem_object *obj;
-+	struct lima_bo *bo;
-+	signed long ret;
-+	unsigned long timeout;
-+
-+	obj = drm_gem_object_lookup(file, handle);
-+	if (!obj)
-+		return -ENOENT;
-+
-+	bo = to_lima_bo(obj);
-+
-+	timeout = timeout_ns ? lima_timeout_to_jiffies(timeout_ns) : 0;
-+
-+	ret = lima_bo_reserve(bo, true);
-+	if (ret)
-+		goto out;
-+
-+	/* must use long for result check because in 64bit arch int
-+	 * will overflow if timeout is too large and get <0 result
-+	 */
-+	ret = reservation_object_wait_timeout_rcu(bo->tbo.resv, write, true, timeout);
-+	if (ret == 0)
-+		ret = timeout ? -ETIMEDOUT : -EBUSY;
-+	else if (ret > 0)
-+		ret = 0;
-+
-+	lima_bo_unreserve(bo);
-+out:
-+	drm_gem_object_put_unlocked(obj);
-+	return ret;
-+}
-+
-+int lima_gem_get_modifier(struct drm_file *file, u32 handle, u64 *modifier)
-+{
-+	struct drm_gem_object *obj;
-+	struct lima_bo *bo;
-+
-+	obj = drm_gem_object_lookup(file, handle);
-+	if (!obj)
-+		return -ENOENT;
-+
-+	bo = to_lima_bo(obj);
-+	*modifier = bo->modifier;
-+
-+	drm_gem_object_put_unlocked(obj);
-+	return 0;
-+}
-+
-+int lima_gem_set_modifier(struct drm_file *file, u32 handle, u64 modifier)
-+{
-+	struct drm_gem_object *obj;
-+	struct lima_bo *bo;
-+
-+	obj = drm_gem_object_lookup(file, handle);
-+	if (!obj)
-+		return -ENOENT;
-+
-+	bo = to_lima_bo(obj);
-+	bo->modifier = modifier;
-+
-+	drm_gem_object_put_unlocked(obj);
-+	return 0;
-+}
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_gem.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_gem.h
---- linux-4.17/drivers/gpu/drm/lima/lima_gem.h.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_gem.h	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,25 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_GEM_H__
-+#define __LIMA_GEM_H__
-+
-+struct lima_bo;
-+struct lima_submit;
-+
-+struct lima_bo *lima_gem_create_bo(struct drm_device *dev, u32 size, u32 flags);
-+int lima_gem_create_handle(struct drm_device *dev, struct drm_file *file,
-+			   u32 size, u32 flags, u32 *handle);
-+void lima_gem_free_object(struct drm_gem_object *obj);
-+int lima_gem_object_open(struct drm_gem_object *obj, struct drm_file *file);
-+void lima_gem_object_close(struct drm_gem_object *obj, struct drm_file *file);
-+int lima_gem_mmap_offset(struct drm_file *file, u32 handle, u64 *offset);
-+int lima_gem_mmap(struct file *filp, struct vm_area_struct *vma);
-+int lima_gem_va_map(struct drm_file *file, u32 handle, u32 flags, u32 va);
-+int lima_gem_va_unmap(struct drm_file *file, u32 handle, u32 va);
-+int lima_gem_submit(struct drm_file *file, struct lima_submit *submit);
-+int lima_gem_wait(struct drm_file *file, u32 handle, u32 op, u64 timeout_ns);
-+int lima_gem_get_modifier(struct drm_file *file, u32 handle, u64 *modifier);
-+int lima_gem_set_modifier(struct drm_file *file, u32 handle, u64 modifier);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_gem_prime.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_gem_prime.c
---- linux-4.17/drivers/gpu/drm/lima/lima_gem_prime.c.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_gem_prime.c	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,47 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <linux/dma-buf.h>
-+#include <drm/drm_prime.h>
-+
-+#include "lima_device.h"
-+#include "lima_object.h"
-+#include "lima_gem_prime.h"
-+
-+struct drm_gem_object *lima_gem_prime_import_sg_table(
-+	struct drm_device *dev, struct dma_buf_attachment *attach,
-+	struct sg_table *sgt)
-+{
-+	struct reservation_object *resv = attach->dmabuf->resv;
-+	struct lima_device *ldev = to_lima_dev(dev);
-+	struct lima_bo *bo;
-+
-+	ww_mutex_lock(&resv->lock, NULL);
-+
-+	bo = lima_bo_create(ldev, attach->dmabuf->size, 0,
-+			    ttm_bo_type_sg, sgt, resv);
-+	if (IS_ERR(bo))
-+		goto err_out;
-+
-+	ww_mutex_unlock(&resv->lock);
-+	return &bo->gem;
-+
-+err_out:
-+	ww_mutex_unlock(&resv->lock);
-+	return (void *)bo;
-+}
-+
-+struct reservation_object *lima_gem_prime_res_obj(struct drm_gem_object *obj)
-+{
-+        struct lima_bo *bo = to_lima_bo(obj);
-+
-+	return bo->tbo.resv;
-+}
-+
-+struct sg_table *lima_gem_prime_get_sg_table(struct drm_gem_object *obj)
-+{
-+	struct lima_bo *bo = to_lima_bo(obj);
-+	int npages = bo->tbo.num_pages;
-+
-+	return drm_prime_pages_to_sg(bo->tbo.ttm->pages, npages);
-+}
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_gem_prime.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_gem_prime.h
---- linux-4.17/drivers/gpu/drm/lima/lima_gem_prime.h.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_gem_prime.h	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,13 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_GEM_PRIME_H__
-+#define __LIMA_GEM_PRIME_H__
-+
-+struct drm_gem_object *lima_gem_prime_import_sg_table(
-+	struct drm_device *dev, struct dma_buf_attachment *attach,
-+	struct sg_table *sgt);
-+struct sg_table *lima_gem_prime_get_sg_table(struct drm_gem_object *obj);
-+struct reservation_object *lima_gem_prime_res_obj(struct drm_gem_object *obj);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_gp.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_gp.c
---- linux-4.17/drivers/gpu/drm/lima/lima_gp.c.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_gp.c	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,274 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/device.h>
-+#include <linux/slab.h>
-+
-+#include <drm/lima_drm.h>
-+
-+#include "lima_device.h"
-+#include "lima_gp.h"
-+#include "lima_regs.h"
-+
-+#define gp_write(reg, data) writel(data, ip->iomem + LIMA_GP_##reg)
-+#define gp_read(reg) readl(ip->iomem + LIMA_GP_##reg)
-+
-+static irqreturn_t lima_gp_irq_handler(int irq, void *data)
-+{
-+	struct lima_ip *ip = data;
-+	struct lima_device *dev = ip->dev;
-+	struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp;
-+	u32 state = gp_read(INT_STAT);
-+	u32 status = gp_read(STATUS);
-+	bool done = false;
-+
-+	/* for shared irq case */
-+	if (!state)
-+		return IRQ_NONE;
-+
-+	if (state & LIMA_GP_IRQ_MASK_ERROR) {
-+		dev_err(dev->dev, "gp error irq state=%x status=%x\n",
-+			state, status);
-+
-+		/* mask all interrupts before hard reset */
-+		gp_write(INT_MASK, 0);
-+
-+		pipe->error = true;
-+		done = true;
-+	}
-+	else {
-+		bool valid = state & (LIMA_GP_IRQ_VS_END_CMD_LST |
-+				      LIMA_GP_IRQ_PLBU_END_CMD_LST);
-+		bool active = status & (LIMA_GP_STATUS_VS_ACTIVE |
-+					LIMA_GP_STATUS_PLBU_ACTIVE);
-+		done = valid && !active;
-+	}
-+
-+	gp_write(INT_CLEAR, state);
-+
-+	if (done)
-+		lima_sched_pipe_task_done(pipe);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static void lima_gp_soft_reset_async(struct lima_ip *ip)
-+{
-+	if (ip->data.async_reset)
-+		return;
-+
-+	gp_write(INT_MASK, 0);
-+	gp_write(INT_CLEAR, LIMA_GP_IRQ_RESET_COMPLETED);
-+	gp_write(CMD, LIMA_GP_CMD_SOFT_RESET);
-+	ip->data.async_reset = true;
-+}
-+
-+static int lima_gp_soft_reset_async_wait(struct lima_ip *ip)
-+{
-+	struct lima_device *dev = ip->dev;
-+	int timeout;
-+
-+	if (!ip->data.async_reset)
-+		return 0;
-+
-+	for (timeout = 1000; timeout > 0; timeout--) {
-+		if (gp_read(INT_RAWSTAT) & LIMA_GP_IRQ_RESET_COMPLETED)
-+			break;
-+	}
-+	if (!timeout) {
-+		dev_err(dev->dev, "gp soft reset time out\n");
-+		return -ETIMEDOUT;
-+	}
-+
-+	gp_write(INT_CLEAR, LIMA_GP_IRQ_MASK_ALL);
-+	gp_write(INT_MASK, LIMA_GP_IRQ_MASK_USED);
-+
-+	ip->data.async_reset = false;
-+	return 0;
-+}
-+
-+static int lima_gp_task_validate(struct lima_sched_pipe *pipe,
-+				 struct lima_sched_task *task)
-+{
-+	struct drm_lima_gp_frame *frame = task->frame;
-+	u32 *f = frame->frame;
-+	(void)pipe;
-+
-+	if (f[LIMA_GP_VSCL_START_ADDR >> 2] >
-+	    f[LIMA_GP_VSCL_END_ADDR >> 2] ||
-+	    f[LIMA_GP_PLBUCL_START_ADDR >> 2] >
-+	    f[LIMA_GP_PLBUCL_END_ADDR >> 2] ||
-+	    f[LIMA_GP_PLBU_ALLOC_START_ADDR >> 2] >
-+	    f[LIMA_GP_PLBU_ALLOC_END_ADDR >> 2])
-+		return -EINVAL;
-+
-+	if (f[LIMA_GP_VSCL_START_ADDR >> 2] ==
-+	    f[LIMA_GP_VSCL_END_ADDR >> 2] &&
-+	    f[LIMA_GP_PLBUCL_START_ADDR >> 2] ==
-+	    f[LIMA_GP_PLBUCL_END_ADDR >> 2])
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+
-+static void lima_gp_task_run(struct lima_sched_pipe *pipe,
-+			     struct lima_sched_task *task)
-+{
-+	struct lima_ip *ip = pipe->processor[0];
-+	struct drm_lima_gp_frame *frame = task->frame;
-+	u32 *f = frame->frame;
-+	u32 cmd = 0;
-+	int i;
-+
-+	if (f[LIMA_GP_VSCL_START_ADDR >> 2] !=
-+	    f[LIMA_GP_VSCL_END_ADDR >> 2])
-+		cmd |= LIMA_GP_CMD_START_VS;
-+	if (f[LIMA_GP_PLBUCL_START_ADDR >> 2] !=
-+	    f[LIMA_GP_PLBUCL_END_ADDR >> 2])
-+		cmd |= LIMA_GP_CMD_START_PLBU;
-+
-+	/* before any hw ops, wait last success task async soft reset */
-+	lima_gp_soft_reset_async_wait(ip);
-+
-+	for (i = 0; i < LIMA_GP_FRAME_REG_NUM; i++)
-+		writel(f[i], ip->iomem + LIMA_GP_VSCL_START_ADDR + i * 4);
-+
-+	gp_write(CMD, LIMA_GP_CMD_UPDATE_PLBU_ALLOC);
-+	gp_write(CMD, cmd);
-+}
-+
-+static int lima_gp_hard_reset(struct lima_ip *ip)
-+{
-+	struct lima_device *dev = ip->dev;
-+	int timeout;
-+
-+	gp_write(PERF_CNT_0_LIMIT, 0xC0FFE000);
-+	gp_write(INT_MASK, 0);
-+	gp_write(CMD, LIMA_GP_CMD_RESET);
-+	for (timeout = 1000; timeout > 0; timeout--) {
-+		gp_write(PERF_CNT_0_LIMIT, 0xC01A0000);
-+		if (gp_read(PERF_CNT_0_LIMIT) == 0xC01A0000)
-+			break;
-+	}
-+	if (!timeout) {
-+		dev_err(dev->dev, "gp hard reset timeout\n");
-+		return -ETIMEDOUT;
-+	}
-+
-+	gp_write(PERF_CNT_0_LIMIT, 0);
-+	gp_write(INT_CLEAR, LIMA_GP_IRQ_MASK_ALL);
-+	gp_write(INT_MASK, LIMA_GP_IRQ_MASK_USED);
-+	return 0;
-+}
-+
-+static void lima_gp_task_fini(struct lima_sched_pipe *pipe)
-+{
-+	lima_gp_soft_reset_async(pipe->processor[0]);
-+}
-+
-+static void lima_gp_task_error(struct lima_sched_pipe *pipe)
-+{
-+	lima_gp_hard_reset(pipe->processor[0]);
-+}
-+
-+static void lima_gp_task_mmu_error(struct lima_sched_pipe *pipe)
-+{
-+	lima_sched_pipe_task_done(pipe);
-+}
-+
-+static void lima_gp_print_version(struct lima_ip *ip)
-+{
-+	u32 version, major, minor;
-+	char *name;
-+
-+	version = gp_read(VERSION);
-+	major = (version >> 8) & 0xFF;
-+	minor = version & 0xFF;
-+	switch (version >> 16) {
-+	case 0xA07:
-+	    name = "mali200";
-+		break;
-+	case 0xC07:
-+		name = "mali300";
-+		break;
-+	case 0xB07:
-+		name = "mali400";
-+		break;
-+	case 0xD07:
-+		name = "mali450";
-+		break;
-+	default:
-+		name = "unknow";
-+		break;
-+	}
-+	dev_info(ip->dev->dev, "%s - %s version major %d minor %d\n",
-+		 lima_ip_name(ip), name, major, minor);
-+}
-+
-+static struct kmem_cache *lima_gp_task_slab = NULL;
-+static int lima_gp_task_slab_refcnt = 0;
-+
-+int lima_gp_init(struct lima_ip *ip)
-+{
-+	struct lima_device *dev = ip->dev;
-+	int err;
-+
-+	lima_gp_print_version(ip);
-+
-+	ip->data.async_reset = false;
-+	lima_gp_soft_reset_async(ip);
-+	err = lima_gp_soft_reset_async_wait(ip);
-+	if (err)
-+		return err;
-+
-+	err = devm_request_irq(dev->dev, ip->irq, lima_gp_irq_handler,
-+			       IRQF_SHARED, lima_ip_name(ip), ip);
-+	if (err) {
-+		dev_err(dev->dev, "gp %s fail to request irq\n",
-+			lima_ip_name(ip));
-+		return err;
-+	}
-+
-+	return 0;
-+}
-+
-+void lima_gp_fini(struct lima_ip *ip)
-+{
-+
-+}
-+
-+int lima_gp_pipe_init(struct lima_device *dev)
-+{
-+	int frame_size = sizeof(struct drm_lima_gp_frame);
-+	struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp;
-+
-+	if (!lima_gp_task_slab) {
-+		lima_gp_task_slab = kmem_cache_create(
-+			"lima_gp_task", sizeof(struct lima_sched_task) + frame_size,
-+			0, SLAB_HWCACHE_ALIGN, NULL);
-+		if (!lima_gp_task_slab)
-+			return -ENOMEM;
-+	}
-+	lima_gp_task_slab_refcnt++;
-+
-+	pipe->frame_size = frame_size;
-+	pipe->task_slab = lima_gp_task_slab;
-+
-+	pipe->task_validate = lima_gp_task_validate;
-+	pipe->task_run = lima_gp_task_run;
-+	pipe->task_fini = lima_gp_task_fini;
-+	pipe->task_error = lima_gp_task_error;
-+	pipe->task_mmu_error = lima_gp_task_mmu_error;
-+
-+	return 0;
-+}
-+
-+void lima_gp_pipe_fini(struct lima_device *dev)
-+{
-+	if (!--lima_gp_task_slab_refcnt) {
-+		kmem_cache_destroy(lima_gp_task_slab);
-+		lima_gp_task_slab = NULL;
-+	}
-+}
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_gp.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_gp.h
---- linux-4.17/drivers/gpu/drm/lima/lima_gp.h.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_gp.h	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_GP_H__
-+#define __LIMA_GP_H__
-+
-+struct lima_ip;
-+struct lima_device;
-+
-+int lima_gp_init(struct lima_ip *ip);
-+void lima_gp_fini(struct lima_ip *ip);
-+
-+int lima_gp_pipe_init(struct lima_device *dev);
-+void lima_gp_pipe_fini(struct lima_device *dev);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_l2_cache.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_l2_cache.c
---- linux-4.17/drivers/gpu/drm/lima/lima_l2_cache.c.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_l2_cache.c	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,79 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <linux/io.h>
-+#include <linux/device.h>
-+
-+#include "lima_device.h"
-+#include "lima_l2_cache.h"
-+#include "lima_regs.h"
-+
-+#define l2_cache_write(reg, data) writel(data, ip->iomem + LIMA_L2_CACHE_##reg)
-+#define l2_cache_read(reg) readl(ip->iomem + LIMA_L2_CACHE_##reg)
-+
-+static int lima_l2_cache_wait_idle(struct lima_ip *ip)
-+{
-+	int timeout;
-+	struct lima_device *dev = ip->dev;
-+
-+	for (timeout = 100000; timeout > 0; timeout--) {
-+	    if (!(l2_cache_read(STATUS) & LIMA_L2_CACHE_STATUS_COMMAND_BUSY))
-+		break;
-+	}
-+	if (!timeout) {
-+	    dev_err(dev->dev, "l2 cache wait command timeout\n");
-+	    return -ETIMEDOUT;
-+	}
-+	return 0;
-+}
-+
-+int lima_l2_cache_flush(struct lima_ip *ip)
-+{
-+	int ret;
-+
-+	spin_lock(&ip->data.lock);
-+	l2_cache_write(COMMAND, LIMA_L2_CACHE_COMMAND_CLEAR_ALL);
-+	ret = lima_l2_cache_wait_idle(ip);
-+	spin_unlock(&ip->data.lock);
-+	return ret;
-+}
-+
-+int lima_l2_cache_init(struct lima_ip *ip)
-+{
-+	int i, err;
-+	u32 size;
-+	struct lima_device *dev = ip->dev;
-+
-+	/* l2_cache2 only exists when one of PP4-7 present */
-+	if (ip->id == lima_ip_l2_cache2) {
-+		for (i = lima_ip_pp4; i <= lima_ip_pp7; i++) {
-+			if (dev->ip[i].present)
-+				break;
-+		}
-+		if (i > lima_ip_pp7)
-+			return -ENODEV;
-+	}
-+
-+	spin_lock_init(&ip->data.lock);
-+
-+	size = l2_cache_read(SIZE);
-+	dev_info(dev->dev, "l2 cache %uK, %u-way, %ubyte cache line, %ubit external bus\n",
-+		 1 << (((size >> 16) & 0xff) - 10),
-+		 1 << ((size >> 8) & 0xff),
-+		 1 << (size & 0xff),
-+		 1 << ((size >> 24) & 0xff));
-+
-+	err = lima_l2_cache_flush(ip);
-+	if (err)
-+		return err;
-+
-+	l2_cache_write(ENABLE, LIMA_L2_CACHE_ENABLE_ACCESS | LIMA_L2_CACHE_ENABLE_READ_ALLOCATE);
-+	l2_cache_write(MAX_READS, 0x1c);
-+
-+	return 0;
-+}
-+
-+void lima_l2_cache_fini(struct lima_ip *ip)
-+{
-+
-+}
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_l2_cache.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_l2_cache.h
---- linux-4.17/drivers/gpu/drm/lima/lima_l2_cache.h.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_l2_cache.h	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,14 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_L2_CACHE_H__
-+#define __LIMA_L2_CACHE_H__
-+
-+struct lima_ip;
-+
-+int lima_l2_cache_init(struct lima_ip *ip);
-+void lima_l2_cache_fini(struct lima_ip *ip);
-+
-+int lima_l2_cache_flush(struct lima_ip *ip);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_mmu.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_mmu.c
---- linux-4.17/drivers/gpu/drm/lima/lima_mmu.c.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_mmu.c	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,135 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/device.h>
-+
-+#include "lima_device.h"
-+#include "lima_mmu.h"
-+#include "lima_vm.h"
-+#include "lima_object.h"
-+#include "lima_regs.h"
-+
-+#define mmu_write(reg, data) writel(data, ip->iomem + LIMA_MMU_##reg)
-+#define mmu_read(reg) readl(ip->iomem + LIMA_MMU_##reg)
-+
-+#define lima_mmu_send_command(command, condition)	     \
-+({							     \
-+	int __timeout, __ret = 0;			     \
-+							     \
-+	mmu_write(COMMAND, command);			     \
-+	for (__timeout = 1000; __timeout > 0; __timeout--) { \
-+		if (condition)				     \
-+			break;				     \
-+	}						     \
-+	if (!__timeout)	{				     \
-+		dev_err(dev->dev, "mmu command %x timeout\n", command); \
-+		__ret = -ETIMEDOUT;			     \
-+	}						     \
-+	__ret;						     \
-+})
-+
-+static irqreturn_t lima_mmu_irq_handler(int irq, void *data)
-+{
-+	struct lima_ip *ip = data;
-+	struct lima_device *dev = ip->dev;
-+	u32 status = mmu_read(INT_STATUS);
-+	struct lima_sched_pipe *pipe;
-+
-+	/* for shared irq case */
-+	if (!status)
-+		return IRQ_NONE;
-+
-+	if (status & LIMA_MMU_INT_PAGE_FAULT) {
-+		u32 fault = mmu_read(PAGE_FAULT_ADDR);
-+		dev_err(dev->dev, "mmu page fault at 0x%x from bus id %d of type %s on %s\n",
-+			fault, LIMA_MMU_STATUS_BUS_ID(status),
-+			status & LIMA_MMU_STATUS_PAGE_FAULT_IS_WRITE ? "write" : "read",
-+			lima_ip_name(ip));
-+	}
-+
-+	if (status & LIMA_MMU_INT_READ_BUS_ERROR) {
-+		dev_err(dev->dev, "mmu %s irq bus error\n", lima_ip_name(ip));
-+	}
-+
-+	/* mask all interrupts before resume */
-+	mmu_write(INT_MASK, 0);
-+	mmu_write(INT_CLEAR, status);
-+
-+	pipe = dev->pipe + (ip->id == lima_ip_gpmmu ? lima_pipe_gp : lima_pipe_pp);
-+	lima_sched_pipe_mmu_error(pipe);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+int lima_mmu_init(struct lima_ip *ip)
-+{
-+	struct lima_device *dev = ip->dev;
-+	int err;
-+
-+	if (ip->id == lima_ip_ppmmu_bcast)
-+		return 0;
-+
-+	mmu_write(DTE_ADDR, 0xCAFEBABE);
-+	if (mmu_read(DTE_ADDR) != 0xCAFEB000) {
-+		dev_err(dev->dev, "mmu %s dte write test fail\n", lima_ip_name(ip));
-+		return -EIO;
-+	}
-+
-+	err = lima_mmu_send_command(LIMA_MMU_COMMAND_HARD_RESET, mmu_read(DTE_ADDR) == 0);
-+	if (err)
-+		return err;
-+
-+	err = devm_request_irq(dev->dev, ip->irq, lima_mmu_irq_handler,
-+			       IRQF_SHARED, lima_ip_name(ip), ip);
-+	if (err) {
-+		dev_err(dev->dev, "mmu %s fail to request irq\n", lima_ip_name(ip));
-+		return err;
-+	}
-+
-+	mmu_write(INT_MASK, LIMA_MMU_INT_PAGE_FAULT | LIMA_MMU_INT_READ_BUS_ERROR);
-+	mmu_write(DTE_ADDR, *lima_bo_get_pages(dev->empty_vm->pd));
-+	return lima_mmu_send_command(LIMA_MMU_COMMAND_ENABLE_PAGING,
-+				     mmu_read(STATUS) & LIMA_MMU_STATUS_PAGING_ENABLED);
-+}
-+
-+void lima_mmu_fini(struct lima_ip *ip)
-+{
-+
-+}
-+
-+void lima_mmu_switch_vm(struct lima_ip *ip, struct lima_vm *vm)
-+{
-+	struct lima_device *dev = ip->dev;
-+
-+	lima_mmu_send_command(LIMA_MMU_COMMAND_ENABLE_STALL,
-+			      mmu_read(STATUS) & LIMA_MMU_STATUS_STALL_ACTIVE);
-+
-+	if (vm)
-+		mmu_write(DTE_ADDR, *lima_bo_get_pages(vm->pd));
-+
-+	/* flush the TLB */
-+	mmu_write(COMMAND, LIMA_MMU_COMMAND_ZAP_CACHE);
-+
-+	lima_mmu_send_command(LIMA_MMU_COMMAND_DISABLE_STALL,
-+			      !(mmu_read(STATUS) & LIMA_MMU_STATUS_STALL_ACTIVE));
-+}
-+
-+void lima_mmu_page_fault_resume(struct lima_ip *ip)
-+{
-+	struct lima_device *dev = ip->dev;
-+	u32 status = mmu_read(STATUS);
-+
-+	if (status & LIMA_MMU_STATUS_PAGE_FAULT_ACTIVE) {
-+		dev_info(dev->dev, "mmu resume\n");
-+
-+		mmu_write(INT_MASK, 0);
-+		mmu_write(DTE_ADDR, 0xCAFEBABE);
-+		lima_mmu_send_command(LIMA_MMU_COMMAND_HARD_RESET, mmu_read(DTE_ADDR) == 0);
-+	        mmu_write(INT_MASK, LIMA_MMU_INT_PAGE_FAULT | LIMA_MMU_INT_READ_BUS_ERROR);
-+		mmu_write(DTE_ADDR, *lima_bo_get_pages(dev->empty_vm->pd));
-+		lima_mmu_send_command(LIMA_MMU_COMMAND_ENABLE_PAGING,
-+				      mmu_read(STATUS) & LIMA_MMU_STATUS_PAGING_ENABLED);
-+	}
-+}
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_mmu.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_mmu.h
---- linux-4.17/drivers/gpu/drm/lima/lima_mmu.h.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_mmu.h	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_MMU_H__
-+#define __LIMA_MMU_H__
-+
-+struct lima_ip;
-+struct lima_vm;
-+
-+int lima_mmu_init(struct lima_ip *ip);
-+void lima_mmu_fini(struct lima_ip *ip);
-+
-+void lima_mmu_switch_vm(struct lima_ip *ip, struct lima_vm *vm);
-+void lima_mmu_page_fault_resume(struct lima_ip *ip);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_object.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_object.c
---- linux-4.17/drivers/gpu/drm/lima/lima_object.c.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_object.c	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,103 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <drm/drm_prime.h>
-+#include <drm/drm_fourcc.h>
-+
-+#include "lima_object.h"
-+
-+static void lima_bo_init_placement(struct lima_bo *bo)
-+{
-+	struct ttm_placement *placement = &bo->placement;
-+	struct ttm_place *place = &bo->place;
-+
-+	place->fpfn = 0;
-+	place->lpfn = 0;
-+	place->flags = TTM_PL_FLAG_TT | TTM_PL_FLAG_WC;
-+
-+	/* pin all bo for now */
-+	place->flags |= TTM_PL_FLAG_NO_EVICT;
-+
-+	placement->num_placement = 1;
-+	placement->placement = place;
-+
-+	placement->num_busy_placement = 1;
-+	placement->busy_placement = place;
-+}
-+
-+static void lima_bo_destroy(struct ttm_buffer_object *tbo)
-+{
-+	struct lima_bo *bo = ttm_to_lima_bo(tbo);
-+
-+	if (bo->gem.import_attach)
-+		drm_prime_gem_destroy(&bo->gem, bo->tbo.sg);
-+	drm_gem_object_release(&bo->gem);
-+	kfree(bo);
-+}
-+
-+struct lima_bo *lima_bo_create(struct lima_device *dev, u64 size,
-+			       u32 flags, enum ttm_bo_type type,
-+			       struct sg_table *sg,
-+			       struct reservation_object *resv)
-+{
-+	struct lima_bo *bo;
-+	struct ttm_mem_type_manager *man;
-+	size_t acc_size;
-+	int err;
-+
-+	size = PAGE_ALIGN(size);
-+	man = dev->mman.bdev.man + TTM_PL_TT;
-+	if (size >= (man->size << PAGE_SHIFT))
-+		return ERR_PTR(-ENOMEM);
-+
-+	acc_size = ttm_bo_dma_acc_size(&dev->mman.bdev, size,
-+				       sizeof(struct lima_bo));
-+
-+	bo = kzalloc(sizeof(*bo), GFP_KERNEL);
-+	if (!bo)
-+		return ERR_PTR(-ENOMEM);
-+
-+	drm_gem_private_object_init(dev->ddev, &bo->gem, size);
-+
-+	INIT_LIST_HEAD(&bo->va);
-+
-+	bo->tbo.bdev = &dev->mman.bdev;
-+
-+	lima_bo_init_placement(bo);
-+
-+	err = ttm_bo_init(&dev->mman.bdev, &bo->tbo, size, type,
-+			  &bo->placement, 0, type != ttm_bo_type_kernel,
-+			  acc_size, sg, resv, &lima_bo_destroy);
-+	if (err)
-+		goto err_out;
-+
-+	bo->modifier = DRM_FORMAT_MOD_INVALID;
-+	return bo;
-+
-+err_out:
-+	kfree(bo);
-+	return ERR_PTR(err);
-+}
-+
-+dma_addr_t *lima_bo_get_pages(struct lima_bo *bo)
-+{
-+	struct lima_ttm_tt *ttm = (void *)bo->tbo.ttm;
-+	return ttm->ttm.dma_address;
-+}
-+
-+void *lima_bo_kmap(struct lima_bo *bo)
-+{
-+	bool is_iomem;
-+	void *ret;
-+	int err;
-+
-+	ret = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
-+	if (ret)
-+		return ret;
-+
-+	err = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
-+	if (err)
-+		return ERR_PTR(err);
-+
-+	return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
-+}
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_object.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_object.h
---- linux-4.17/drivers/gpu/drm/lima/lima_object.h.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_object.h	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,71 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_OBJECT_H__
-+#define __LIMA_OBJECT_H__
-+
-+#include <drm/drm_gem.h>
-+#include <drm/ttm/ttm_placement.h>
-+#include <drm/ttm/ttm_bo_api.h>
-+
-+#include "lima_device.h"
-+
-+struct lima_bo {
-+	struct drm_gem_object gem;
-+
-+	struct ttm_place place;
-+	struct ttm_placement placement;
-+	struct ttm_buffer_object tbo;
-+	struct ttm_bo_kmap_obj kmap;
-+
-+	struct list_head va;
-+
-+	u64 modifier;
-+};
-+
-+static inline struct lima_bo *
-+to_lima_bo(struct drm_gem_object *obj)
-+{
-+	return container_of(obj, struct lima_bo, gem);
-+}
-+
-+static inline struct lima_bo *
-+ttm_to_lima_bo(struct ttm_buffer_object *tbo)
-+{
-+	return container_of(tbo, struct lima_bo, tbo);
-+}
-+
-+static inline int lima_bo_reserve(struct lima_bo *bo, bool intr)
-+{
-+	struct lima_device *dev = ttm_to_lima_dev(bo->tbo.bdev);
-+	int r;
-+
-+	r = ttm_bo_reserve(&bo->tbo, intr, false, NULL);
-+	if (unlikely(r != 0)) {
-+		if (r != -ERESTARTSYS)
-+			dev_err(dev->dev, "%p reserve failed\n", bo);
-+		return r;
-+	}
-+	return 0;
-+}
-+
-+static inline void lima_bo_unreserve(struct lima_bo *bo)
-+{
-+	ttm_bo_unreserve(&bo->tbo);
-+}
-+
-+struct lima_bo *lima_bo_create(struct lima_device *dev, u64 size,
-+			       u32 flags, enum ttm_bo_type type,
-+			       struct sg_table *sg,
-+			       struct reservation_object *resv);
-+
-+static inline void lima_bo_unref(struct lima_bo *bo)
-+{
-+	struct ttm_buffer_object *tbo = &bo->tbo;
-+	ttm_bo_unref(&tbo);
-+}
-+
-+dma_addr_t *lima_bo_get_pages(struct lima_bo *bo);
-+void *lima_bo_kmap(struct lima_bo *bo);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_pmu.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_pmu.c
---- linux-4.17/drivers/gpu/drm/lima/lima_pmu.c.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_pmu.c	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,66 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <linux/of.h>
-+#include <linux/io.h>
-+#include <linux/device.h>
-+
-+#include "lima_device.h"
-+#include "lima_pmu.h"
-+#include "lima_regs.h"
-+
-+#define pmu_write(reg, data) writel(data, ip->iomem + LIMA_PMU_##reg)
-+#define pmu_read(reg) readl(ip->iomem + LIMA_PMU_##reg)
-+
-+static int lima_pmu_wait_cmd(struct lima_ip *ip)
-+{
-+	struct lima_device *dev = ip->dev;
-+	u32 stat, timeout;
-+
-+	for (timeout = 1000000; timeout > 0; timeout--) {
-+		stat = pmu_read(INT_RAWSTAT);
-+		if (stat & LIMA_PMU_INT_CMD_MASK)
-+			break;
-+	}
-+
-+	if (!timeout) {
-+		dev_err(dev->dev, "timeout wait pmd cmd\n");
-+		return -ETIMEDOUT;
-+	}
-+
-+	pmu_write(INT_CLEAR, LIMA_PMU_INT_CMD_MASK);
-+	return 0;
-+}
-+
-+int lima_pmu_init(struct lima_ip *ip)
-+{
-+	int err;
-+	u32 stat;
-+	struct lima_device *dev = ip->dev;
-+	struct device_node *np = dev->dev->of_node;
-+
-+	/* If this value is too low, when in high GPU clk freq,
-+	 * GPU will be in unstable state. */
-+	if (of_property_read_u32(np, "switch-delay", &ip->data.switch_delay))
-+		ip->data.switch_delay = 0xff;
-+
-+	pmu_write(INT_MASK, 0);
-+	pmu_write(SW_DELAY, ip->data.switch_delay);
-+
-+	/* status reg 1=off 0=on */
-+	stat = pmu_read(STATUS);
-+
-+	/* power up all ip */
-+	if (stat) {
-+		pmu_write(POWER_UP, stat);
-+		err = lima_pmu_wait_cmd(ip);
-+		if (err)
-+			return err;
-+	}
-+	return 0;
-+}
-+
-+void lima_pmu_fini(struct lima_ip *ip)
-+{
-+
-+}
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_pmu.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_pmu.h
---- linux-4.17/drivers/gpu/drm/lima/lima_pmu.h.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_pmu.h	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_PMU_H__
-+#define __LIMA_PMU_H__
-+
-+struct lima_ip;
-+
-+int lima_pmu_init(struct lima_ip *ip);
-+void lima_pmu_fini(struct lima_ip *ip);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_pp.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_pp.c
---- linux-4.17/drivers/gpu/drm/lima/lima_pp.c.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_pp.c	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,399 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/device.h>
-+#include <linux/slab.h>
-+
-+#include <drm/lima_drm.h>
-+
-+#include "lima_device.h"
-+#include "lima_pp.h"
-+#include "lima_dlbu.h"
-+#include "lima_bcast.h"
-+#include "lima_vm.h"
-+#include "lima_regs.h"
-+
-+#define pp_write(reg, data) writel(data, ip->iomem + LIMA_PP_##reg)
-+#define pp_read(reg) readl(ip->iomem + LIMA_PP_##reg)
-+
-+static void lima_pp_handle_irq(struct lima_ip *ip, u32 state)
-+{
-+	struct lima_device *dev = ip->dev;
-+	struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
-+
-+	if (state & LIMA_PP_IRQ_MASK_ERROR) {
-+		u32 status = pp_read(STATUS);
-+
-+		dev_err(dev->dev, "pp error irq state=%x status=%x\n",
-+			state, status);
-+
-+		pipe->error = true;
-+
-+		/* mask all interrupts before hard reset */
-+		pp_write(INT_MASK, 0);
-+	}
-+
-+	pp_write(INT_CLEAR, state);
-+}
-+
-+static irqreturn_t lima_pp_irq_handler(int irq, void *data)
-+{
-+	struct lima_ip *ip = data;
-+	struct lima_device *dev = ip->dev;
-+	struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
-+	u32 state = pp_read(INT_STATUS);
-+
-+	/* for shared irq case */
-+	if (!state)
-+		return IRQ_NONE;
-+
-+	lima_pp_handle_irq(ip, state);
-+
-+	if (atomic_dec_and_test(&pipe->task))
-+		lima_sched_pipe_task_done(pipe);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static irqreturn_t lima_pp_bcast_irq_handler(int irq, void *data)
-+{
-+	int i;
-+	irqreturn_t ret = IRQ_NONE;
-+	struct lima_ip *pp_bcast = data;
-+	struct lima_device *dev = pp_bcast->dev;
-+	struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
-+
-+	for (i = 0; i < pipe->num_processor; i++) {
-+		struct lima_ip *ip = pipe->processor[i];
-+		u32 status, state;
-+
-+		if (pipe->done & (1 << i))
-+			continue;
-+
-+		/* status read first in case int state change in the middle
-+		 * which may miss the interrupt handling */
-+		status = pp_read(STATUS);
-+		state = pp_read(INT_STATUS);
-+
-+		if (state) {
-+			lima_pp_handle_irq(ip, state);
-+			ret = IRQ_HANDLED;
-+		}
-+		else {
-+			if (status & LIMA_PP_STATUS_RENDERING_ACTIVE)
-+				continue;
-+		}
-+
-+		pipe->done |= (1 << i);
-+		if (atomic_dec_and_test(&pipe->task))
-+			lima_sched_pipe_task_done(pipe);
-+	}
-+
-+	return ret;
-+}
-+
-+static void lima_pp_soft_reset_async(struct lima_ip *ip)
-+{
-+	if (ip->data.async_reset)
-+		return;
-+
-+	pp_write(INT_MASK, 0);
-+	pp_write(INT_RAWSTAT, LIMA_PP_IRQ_MASK_ALL);
-+	pp_write(CTRL, LIMA_PP_CTRL_SOFT_RESET);
-+	ip->data.async_reset = true;
-+}
-+
-+static int lima_pp_soft_reset_async_wait_one(struct lima_ip *ip)
-+{
-+	struct lima_device *dev = ip->dev;
-+	int timeout;
-+
-+	for (timeout = 1000; timeout > 0; timeout--) {
-+		if (!(pp_read(STATUS) & LIMA_PP_STATUS_RENDERING_ACTIVE) &&
-+		    pp_read(INT_RAWSTAT) == LIMA_PP_IRQ_RESET_COMPLETED)
-+			break;
-+	}
-+	if (!timeout) {
-+		dev_err(dev->dev, "pp %s reset time out\n", lima_ip_name(ip));
-+		return -ETIMEDOUT;
-+	}
-+
-+	pp_write(INT_CLEAR, LIMA_PP_IRQ_MASK_ALL);
-+	pp_write(INT_MASK, LIMA_PP_IRQ_MASK_USED);
-+	return 0;
-+}
-+
-+static int lima_pp_soft_reset_async_wait(struct lima_ip *ip)
-+{
-+	int i, err = 0;
-+
-+	if (!ip->data.async_reset)
-+		return 0;
-+
-+	if (ip->id == lima_ip_pp_bcast) {
-+		struct lima_device *dev = ip->dev;
-+		struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
-+		for (i = 0; i < pipe->num_processor; i++)
-+			err |= lima_pp_soft_reset_async_wait_one(pipe->processor[i]);
-+	}
-+	else
-+		err = lima_pp_soft_reset_async_wait_one(ip);
-+
-+	ip->data.async_reset = false;
-+	return err;
-+}
-+
-+static void lima_pp_start_task(struct lima_ip *ip, u32 *frame, u32 *wb,
-+			       bool skip_stack_addr)
-+{
-+	int i, j, n = 0;
-+
-+	for (i = 0; i < LIMA_PP_FRAME_REG_NUM; i++) {
-+		if (skip_stack_addr && i * 4 == LIMA_PP_STACK)
-+			continue;
-+
-+		writel(frame[i], ip->iomem + LIMA_PP_FRAME + i * 4);
-+	}
-+
-+	for (i = 0; i < 3; i++) {
-+		for (j = 0; j < LIMA_PP_WB_REG_NUM; j++)
-+			writel(wb[n++], ip->iomem + LIMA_PP_WB(i) + j * 4);
-+	}
-+
-+	pp_write(CTRL, LIMA_PP_CTRL_START_RENDERING);
-+}
-+
-+static int lima_pp_hard_reset(struct lima_ip *ip)
-+{
-+	struct lima_device *dev = ip->dev;
-+	int timeout;
-+
-+	pp_write(PERF_CNT_0_LIMIT, 0xC0FFE000);
-+	pp_write(INT_MASK, 0);
-+	pp_write(CTRL, LIMA_PP_CTRL_FORCE_RESET);
-+	for (timeout = 1000; timeout > 0; timeout--) {
-+		pp_write(PERF_CNT_0_LIMIT, 0xC01A0000);
-+		if (pp_read(PERF_CNT_0_LIMIT) == 0xC01A0000)
-+			break;
-+	}
-+	if (!timeout) {
-+		dev_err(dev->dev, "pp hard reset timeout\n");
-+		return -ETIMEDOUT;
-+	}
-+
-+	pp_write(PERF_CNT_0_LIMIT, 0);
-+	pp_write(INT_CLEAR, LIMA_PP_IRQ_MASK_ALL);
-+	pp_write(INT_MASK, LIMA_PP_IRQ_MASK_USED);
-+	return 0;
-+}
-+
-+static void lima_pp_print_version(struct lima_ip *ip)
-+{
-+	u32 version, major, minor;
-+	char *name;
-+
-+	version = pp_read(VERSION);
-+	major = (version >> 8) & 0xFF;
-+	minor = version & 0xFF;
-+	switch (version >> 16) {
-+	case 0xC807:
-+	    name = "mali200";
-+		break;
-+	case 0xCE07:
-+		name = "mali300";
-+		break;
-+	case 0xCD07:
-+		name = "mali400";
-+		break;
-+	case 0xCF07:
-+		name = "mali450";
-+		break;
-+	default:
-+		name = "unknow";
-+		break;
-+	}
-+	dev_info(ip->dev->dev, "%s - %s version major %d minor %d\n",
-+		 lima_ip_name(ip), name, major, minor);
-+}
-+
-+int lima_pp_init(struct lima_ip *ip)
-+{
-+	struct lima_device *dev = ip->dev;
-+	int err;
-+
-+	lima_pp_print_version(ip);
-+
-+	ip->data.async_reset = false;
-+	lima_pp_soft_reset_async(ip);
-+	err = lima_pp_soft_reset_async_wait(ip);
-+	if (err)
-+		return err;
-+
-+	err = devm_request_irq(dev->dev, ip->irq, lima_pp_irq_handler,
-+			       IRQF_SHARED, lima_ip_name(ip), ip);
-+	if (err) {
-+		dev_err(dev->dev, "pp %s fail to request irq\n",
-+			lima_ip_name(ip));
-+		return err;
-+	}
-+
-+	return 0;
-+}
-+
-+void lima_pp_fini(struct lima_ip *ip)
-+{
-+	
-+}
-+
-+int lima_pp_bcast_init(struct lima_ip *ip)
-+{
-+	struct lima_device *dev = ip->dev;
-+	int err;
-+
-+	err = devm_request_irq(dev->dev, ip->irq, lima_pp_bcast_irq_handler,
-+			       IRQF_SHARED, lima_ip_name(ip), ip);
-+	if (err) {
-+		dev_err(dev->dev, "pp %s fail to request irq\n",
-+			lima_ip_name(ip));
-+		return err;
-+	}
-+
-+	return 0;
-+}
-+
-+void lima_pp_bcast_fini(struct lima_ip *ip)
-+{
-+	
-+}
-+
-+static int lima_pp_task_validate(struct lima_sched_pipe *pipe,
-+				 struct lima_sched_task *task)
-+{
-+	if (!pipe->bcast_processor) {
-+		struct drm_lima_m400_pp_frame *f = task->frame;
-+
-+		if (f->num_pp > pipe->num_processor)
-+			return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static void lima_pp_task_run(struct lima_sched_pipe *pipe,
-+			     struct lima_sched_task *task)
-+{
-+	if (pipe->bcast_processor) {
-+		struct drm_lima_m450_pp_frame *frame = task->frame;
-+		struct lima_device *dev = pipe->bcast_processor->dev;
-+		int i;
-+
-+		pipe->done = 0;
-+		atomic_set(&pipe->task, pipe->num_processor);
-+
-+		frame->frame[LIMA_PP_FRAME >> 2] = LIMA_VA_RESERVE_DLBU;
-+		lima_dlbu_set_reg(dev->ip + lima_ip_dlbu, frame->dlbu_regs);
-+
-+		lima_pp_soft_reset_async_wait(pipe->bcast_processor);
-+
-+		for (i = 0; i < pipe->num_processor; i++) {
-+			struct lima_ip *ip = pipe->processor[i];
-+			pp_write(STACK, frame->fragment_stack_address[i]);
-+		}
-+
-+		lima_pp_start_task(pipe->bcast_processor, frame->frame,
-+				   frame->wb, true);
-+	}
-+	else {
-+		struct drm_lima_m400_pp_frame *frame = task->frame;
-+		int i;
-+
-+		atomic_set(&pipe->task, frame->num_pp);
-+
-+		for (i = 0; i < frame->num_pp; i++) {
-+			frame->frame[LIMA_PP_FRAME >> 2] =
-+				frame->plbu_array_address[i];
-+			frame->frame[LIMA_PP_STACK >> 2] =
-+				frame->fragment_stack_address[i];
-+
-+			lima_pp_soft_reset_async_wait(pipe->processor[i]);
-+
-+			lima_pp_start_task(pipe->processor[i], frame->frame,
-+					   frame->wb, false);
-+		}
-+	}
-+}
-+
-+static void lima_pp_task_fini(struct lima_sched_pipe *pipe)
-+{
-+	if (pipe->bcast_processor)
-+		lima_pp_soft_reset_async(pipe->bcast_processor);
-+	else {
-+		int i;
-+		for (i = 0; i < pipe->num_processor; i++)
-+			lima_pp_soft_reset_async(pipe->processor[i]);
-+	}
-+}
-+
-+static void lima_pp_task_error(struct lima_sched_pipe *pipe)
-+{
-+	int i;
-+
-+	if (pipe->bcast_processor)
-+		lima_bcast_disable(pipe->bcast_processor->dev);
-+
-+	for (i = 0; i < pipe->num_processor; i++)
-+		lima_pp_hard_reset(pipe->processor[i]);
-+
-+	if (pipe->bcast_processor)
-+		lima_bcast_enable(pipe->bcast_processor->dev);
-+}
-+
-+static void lima_pp_task_mmu_error(struct lima_sched_pipe *pipe)
-+{
-+	if (atomic_dec_and_test(&pipe->task))
-+		lima_sched_pipe_task_done(pipe);
-+}
-+
-+static struct kmem_cache *lima_pp_task_slab = NULL;
-+static int lima_pp_task_slab_refcnt = 0;
-+
-+int lima_pp_pipe_init(struct lima_device *dev)
-+{
-+	int frame_size;
-+	struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
-+
-+	if (dev->id == lima_gpu_mali400)
-+		frame_size = sizeof(struct drm_lima_m400_pp_frame);
-+	else
-+		frame_size = sizeof(struct drm_lima_m450_pp_frame);
-+
-+	if (!lima_pp_task_slab) {
-+		lima_pp_task_slab = kmem_cache_create(
-+			"lima_pp_task", sizeof(struct lima_sched_task) + frame_size,
-+			0, SLAB_HWCACHE_ALIGN, NULL);
-+		if (!lima_pp_task_slab)
-+			return -ENOMEM;
-+	}
-+	lima_pp_task_slab_refcnt++;
-+
-+	pipe->frame_size = frame_size;
-+	pipe->task_slab = lima_pp_task_slab;
-+
-+	pipe->task_validate = lima_pp_task_validate;
-+	pipe->task_run = lima_pp_task_run;
-+	pipe->task_fini = lima_pp_task_fini;
-+	pipe->task_error = lima_pp_task_error;
-+	pipe->task_mmu_error = lima_pp_task_mmu_error;
-+
-+	return 0;
-+}
-+
-+void lima_pp_pipe_fini(struct lima_device *dev)
-+{
-+	if (!--lima_pp_task_slab_refcnt) {
-+		kmem_cache_destroy(lima_pp_task_slab);
-+		lima_pp_task_slab = NULL;
-+	}
-+}
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_pp.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_pp.h
---- linux-4.17/drivers/gpu/drm/lima/lima_pp.h.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_pp.h	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,19 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_PP_H__
-+#define __LIMA_PP_H__
-+
-+struct lima_ip;
-+struct lima_device;
-+
-+int lima_pp_init(struct lima_ip *ip);
-+void lima_pp_fini(struct lima_ip *ip);
-+
-+int lima_pp_bcast_init(struct lima_ip *ip);
-+void lima_pp_bcast_fini(struct lima_ip *ip);
-+
-+int lima_pp_pipe_init(struct lima_device *dev);
-+void lima_pp_pipe_fini(struct lima_device *dev);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_regs.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_regs.h
---- linux-4.17/drivers/gpu/drm/lima/lima_regs.h.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_regs.h	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,298 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/* Copyright 2010-2017 ARM Limited. All rights reserved.
-+ * Copyright 2017-2018 Qiang Yu <yuq825@gmail.com>
-+ */
-+
-+#ifndef __LIMA_REGS_H__
-+#define __LIMA_REGS_H__
-+
-+/* This file's register definition is collected from the
-+ * official ARM Mali Utgard GPU kernel driver source code
-+ */
-+
-+/* PMU regs */
-+#define LIMA_PMU_POWER_UP                  0x00
-+#define LIMA_PMU_POWER_DOWN                0x04
-+#define   LIMA_PMU_POWER_GP0_MASK          BIT(0)
-+#define   LIMA_PMU_POWER_L2_MASK           BIT(1)
-+#define   LIMA_PMU_POWER_PP_MASK(i)        BIT(2 + i)
-+
-+/*
-+ * On Mali450 each block automatically starts up its corresponding L2
-+ * and the PPs are not fully independent controllable.
-+ * Instead PP0, PP1-3 and PP4-7 can be turned on or off.
-+ */
-+#define   LIMA450_PMU_POWER_PP0_MASK       BIT(1)
-+#define   LIMA450_PMU_POWER_PP13_MASK      BIT(2)
-+#define   LIMA450_PMU_POWER_PP47_MASK      BIT(3)
-+
-+#define LIMA_PMU_STATUS                    0x08
-+#define LIMA_PMU_INT_MASK                  0x0C
-+#define LIMA_PMU_INT_RAWSTAT               0x10
-+#define LIMA_PMU_INT_CLEAR                 0x18
-+#define   LIMA_PMU_INT_CMD_MASK            BIT(0)
-+#define LIMA_PMU_SW_DELAY                  0x1C
-+
-+/* L2 cache regs */
-+#define LIMA_L2_CACHE_SIZE                   0x0004
-+#define LIMA_L2_CACHE_STATUS                 0x0008
-+#define   LIMA_L2_CACHE_STATUS_COMMAND_BUSY  BIT(0)
-+#define   LIMA_L2_CACHE_STATUS_DATA_BUSY     BIT(1)
-+#define LIMA_L2_CACHE_COMMAND                0x0010
-+#define   LIMA_L2_CACHE_COMMAND_CLEAR_ALL    BIT(0)
-+#define LIMA_L2_CACHE_CLEAR_PAGE             0x0014
-+#define LIMA_L2_CACHE_MAX_READS              0x0018
-+#define LIMA_L2_CACHE_ENABLE                 0x001C
-+#define   LIMA_L2_CACHE_ENABLE_ACCESS        BIT(0)
-+#define   LIMA_L2_CACHE_ENABLE_READ_ALLOCATE BIT(1)
-+#define LIMA_L2_CACHE_PERFCNT_SRC0           0x0020
-+#define LIMA_L2_CACHE_PERFCNT_VAL0           0x0024
-+#define LIMA_L2_CACHE_PERFCNT_SRC1           0x0028
-+#define LIMA_L2_CACHE_ERFCNT_VAL1            0x002C
-+
-+/* GP regs */
-+#define LIMA_GP_VSCL_START_ADDR                0x00
-+#define LIMA_GP_VSCL_END_ADDR                  0x04
-+#define LIMA_GP_PLBUCL_START_ADDR              0x08
-+#define LIMA_GP_PLBUCL_END_ADDR                0x0c
-+#define LIMA_GP_PLBU_ALLOC_START_ADDR          0x10
-+#define LIMA_GP_PLBU_ALLOC_END_ADDR            0x14
-+#define LIMA_GP_CMD                            0x20
-+#define   LIMA_GP_CMD_START_VS                 BIT(0)
-+#define   LIMA_GP_CMD_START_PLBU               BIT(1)
-+#define   LIMA_GP_CMD_UPDATE_PLBU_ALLOC        BIT(4)
-+#define   LIMA_GP_CMD_RESET                    BIT(5)
-+#define   LIMA_GP_CMD_FORCE_HANG               BIT(6)
-+#define   LIMA_GP_CMD_STOP_BUS                 BIT(9)
-+#define   LIMA_GP_CMD_SOFT_RESET               BIT(10)
-+#define LIMA_GP_INT_RAWSTAT                    0x24
-+#define LIMA_GP_INT_CLEAR                      0x28
-+#define LIMA_GP_INT_MASK                       0x2C
-+#define LIMA_GP_INT_STAT                       0x30
-+#define   LIMA_GP_IRQ_VS_END_CMD_LST           BIT(0)
-+#define   LIMA_GP_IRQ_PLBU_END_CMD_LST         BIT(1)
-+#define   LIMA_GP_IRQ_PLBU_OUT_OF_MEM          BIT(2)
-+#define   LIMA_GP_IRQ_VS_SEM_IRQ               BIT(3)
-+#define   LIMA_GP_IRQ_PLBU_SEM_IRQ             BIT(4)
-+#define   LIMA_GP_IRQ_HANG                     BIT(5)
-+#define   LIMA_GP_IRQ_FORCE_HANG               BIT(6)
-+#define   LIMA_GP_IRQ_PERF_CNT_0_LIMIT         BIT(7)
-+#define   LIMA_GP_IRQ_PERF_CNT_1_LIMIT         BIT(8)
-+#define   LIMA_GP_IRQ_WRITE_BOUND_ERR          BIT(9)
-+#define   LIMA_GP_IRQ_SYNC_ERROR               BIT(10)
-+#define   LIMA_GP_IRQ_AXI_BUS_ERROR            BIT(11)
-+#define   LIMA_GP_IRQ_AXI_BUS_STOPPED          BIT(12)
-+#define   LIMA_GP_IRQ_VS_INVALID_CMD           BIT(13)
-+#define   LIMA_GP_IRQ_PLB_INVALID_CMD          BIT(14)
-+#define   LIMA_GP_IRQ_RESET_COMPLETED          BIT(19)
-+#define   LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW      BIT(20)
-+#define   LIMA_GP_IRQ_SEMAPHORE_OVERFLOW       BIT(21)
-+#define   LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS  BIT(22)
-+#define LIMA_GP_WRITE_BOUND_LOW                0x34
-+#define LIMA_GP_PERF_CNT_0_ENABLE              0x3C
-+#define LIMA_GP_PERF_CNT_1_ENABLE              0x40
-+#define LIMA_GP_PERF_CNT_0_SRC                 0x44
-+#define LIMA_GP_PERF_CNT_1_SRC                 0x48
-+#define LIMA_GP_PERF_CNT_0_VALUE               0x4C
-+#define LIMA_GP_PERF_CNT_1_VALUE               0x50
-+#define LIMA_GP_PERF_CNT_0_LIMIT               0x54
-+#define LIMA_GP_STATUS                         0x68
-+#define   LIMA_GP_STATUS_VS_ACTIVE             BIT(1)
-+#define   LIMA_GP_STATUS_BUS_STOPPED           BIT(2)
-+#define   LIMA_GP_STATUS_PLBU_ACTIVE           BIT(3)
-+#define   LIMA_GP_STATUS_BUS_ERROR             BIT(6)
-+#define   LIMA_GP_STATUS_WRITE_BOUND_ERR       BIT(8)
-+#define LIMA_GP_VERSION                        0x6C
-+#define LIMA_GP_VSCL_START_ADDR_READ           0x80
-+#define LIMA_GP_PLBCL_START_ADDR_READ          0x84
-+#define LIMA_GP_CONTR_AXI_BUS_ERROR_STAT       0x94
-+
-+#define LIMA_GP_IRQ_MASK_ALL		   \
-+	(				   \
-+	 LIMA_GP_IRQ_VS_END_CMD_LST      | \
-+	 LIMA_GP_IRQ_PLBU_END_CMD_LST    | \
-+	 LIMA_GP_IRQ_PLBU_OUT_OF_MEM     | \
-+	 LIMA_GP_IRQ_VS_SEM_IRQ          | \
-+	 LIMA_GP_IRQ_PLBU_SEM_IRQ        | \
-+	 LIMA_GP_IRQ_HANG                | \
-+	 LIMA_GP_IRQ_FORCE_HANG          | \
-+	 LIMA_GP_IRQ_PERF_CNT_0_LIMIT    | \
-+	 LIMA_GP_IRQ_PERF_CNT_1_LIMIT    | \
-+	 LIMA_GP_IRQ_WRITE_BOUND_ERR     | \
-+	 LIMA_GP_IRQ_SYNC_ERROR          | \
-+	 LIMA_GP_IRQ_AXI_BUS_ERROR       | \
-+	 LIMA_GP_IRQ_AXI_BUS_STOPPED     | \
-+	 LIMA_GP_IRQ_VS_INVALID_CMD      | \
-+	 LIMA_GP_IRQ_PLB_INVALID_CMD     | \
-+	 LIMA_GP_IRQ_RESET_COMPLETED     | \
-+	 LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW | \
-+	 LIMA_GP_IRQ_SEMAPHORE_OVERFLOW  | \
-+	 LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS)
-+
-+#define LIMA_GP_IRQ_MASK_ERROR             \
-+	(                                  \
-+	 LIMA_GP_IRQ_PLBU_OUT_OF_MEM     | \
-+	 LIMA_GP_IRQ_FORCE_HANG          | \
-+	 LIMA_GP_IRQ_WRITE_BOUND_ERR     | \
-+	 LIMA_GP_IRQ_SYNC_ERROR          | \
-+	 LIMA_GP_IRQ_AXI_BUS_ERROR       | \
-+	 LIMA_GP_IRQ_VS_INVALID_CMD      | \
-+	 LIMA_GP_IRQ_PLB_INVALID_CMD     | \
-+	 LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW | \
-+	 LIMA_GP_IRQ_SEMAPHORE_OVERFLOW  | \
-+	 LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS)
-+
-+#define LIMA_GP_IRQ_MASK_USED		   \
-+	(				   \
-+	 LIMA_GP_IRQ_VS_END_CMD_LST      | \
-+	 LIMA_GP_IRQ_PLBU_END_CMD_LST    | \
-+	 LIMA_GP_IRQ_MASK_ERROR)
-+
-+/* PP regs */
-+#define LIMA_PP_FRAME                        0x0000
-+#define LIMA_PP_RSW			     0x0004
-+#define LIMA_PP_STACK			     0x0030
-+#define LIMA_PP_STACK_SIZE		     0x0034
-+#define LIMA_PP_ORIGIN_OFFSET_X	             0x0040
-+#define LIMA_PP_WB(i) 			     (0x0100 * (i + 1))
-+#define   LIMA_PP_WB_SOURCE_SELECT           0x0000
-+#define	  LIMA_PP_WB_SOURCE_ADDR             0x0004
-+
-+#define LIMA_PP_VERSION                      0x1000
-+#define LIMA_PP_CURRENT_REND_LIST_ADDR       0x1004
-+#define LIMA_PP_STATUS                       0x1008
-+#define   LIMA_PP_STATUS_RENDERING_ACTIVE    BIT(0)
-+#define   LIMA_PP_STATUS_BUS_STOPPED         BIT(4)
-+#define LIMA_PP_CTRL                         0x100c
-+#define   LIMA_PP_CTRL_STOP_BUS              BIT(0)
-+#define   LIMA_PP_CTRL_FLUSH_CACHES          BIT(3)
-+#define   LIMA_PP_CTRL_FORCE_RESET           BIT(5)
-+#define   LIMA_PP_CTRL_START_RENDERING       BIT(6)
-+#define   LIMA_PP_CTRL_SOFT_RESET            BIT(7)
-+#define LIMA_PP_INT_RAWSTAT                  0x1020
-+#define LIMA_PP_INT_CLEAR                    0x1024
-+#define LIMA_PP_INT_MASK                     0x1028
-+#define LIMA_PP_INT_STATUS                   0x102c
-+#define   LIMA_PP_IRQ_END_OF_FRAME           BIT(0)
-+#define   LIMA_PP_IRQ_END_OF_TILE            BIT(1)
-+#define   LIMA_PP_IRQ_HANG                   BIT(2)
-+#define   LIMA_PP_IRQ_FORCE_HANG             BIT(3)
-+#define   LIMA_PP_IRQ_BUS_ERROR              BIT(4)
-+#define   LIMA_PP_IRQ_BUS_STOP               BIT(5)
-+#define   LIMA_PP_IRQ_CNT_0_LIMIT            BIT(6)
-+#define   LIMA_PP_IRQ_CNT_1_LIMIT            BIT(7)
-+#define   LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR   BIT(8)
-+#define   LIMA_PP_IRQ_INVALID_PLIST_COMMAND  BIT(9)
-+#define   LIMA_PP_IRQ_CALL_STACK_UNDERFLOW   BIT(10)
-+#define   LIMA_PP_IRQ_CALL_STACK_OVERFLOW    BIT(11)
-+#define   LIMA_PP_IRQ_RESET_COMPLETED        BIT(12)
-+#define LIMA_PP_WRITE_BOUNDARY_LOW           0x1044
-+#define LIMA_PP_BUS_ERROR_STATUS             0x1050
-+#define LIMA_PP_PERF_CNT_0_ENABLE            0x1080
-+#define LIMA_PP_PERF_CNT_0_SRC               0x1084
-+#define LIMA_PP_PERF_CNT_0_LIMIT             0x1088
-+#define LIMA_PP_PERF_CNT_0_VALUE             0x108c
-+#define LIMA_PP_PERF_CNT_1_ENABLE            0x10a0
-+#define LIMA_PP_PERF_CNT_1_SRC               0x10a4
-+#define LIMA_PP_PERF_CNT_1_LIMIT             0x10a8
-+#define LIMA_PP_PERF_CNT_1_VALUE             0x10ac
-+#define LIMA_PP_PERFMON_CONTR                0x10b0
-+#define LIMA_PP_PERFMON_BASE                 0x10b4
-+
-+#define LIMA_PP_IRQ_MASK_ALL                 \
-+	(                                    \
-+	 LIMA_PP_IRQ_END_OF_FRAME          | \
-+	 LIMA_PP_IRQ_END_OF_TILE           | \
-+	 LIMA_PP_IRQ_HANG                  | \
-+	 LIMA_PP_IRQ_FORCE_HANG            | \
-+	 LIMA_PP_IRQ_BUS_ERROR             | \
-+	 LIMA_PP_IRQ_BUS_STOP              | \
-+	 LIMA_PP_IRQ_CNT_0_LIMIT           | \
-+	 LIMA_PP_IRQ_CNT_1_LIMIT           | \
-+	 LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR  | \
-+	 LIMA_PP_IRQ_INVALID_PLIST_COMMAND | \
-+	 LIMA_PP_IRQ_CALL_STACK_UNDERFLOW  | \
-+	 LIMA_PP_IRQ_CALL_STACK_OVERFLOW   | \
-+	 LIMA_PP_IRQ_RESET_COMPLETED)
-+
-+#define LIMA_PP_IRQ_MASK_ERROR               \
-+	(                                    \
-+	 LIMA_PP_IRQ_FORCE_HANG            | \
-+	 LIMA_PP_IRQ_BUS_ERROR             | \
-+	 LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR  | \
-+	 LIMA_PP_IRQ_INVALID_PLIST_COMMAND | \
-+	 LIMA_PP_IRQ_CALL_STACK_UNDERFLOW  | \
-+	 LIMA_PP_IRQ_CALL_STACK_OVERFLOW)
-+
-+#define LIMA_PP_IRQ_MASK_USED                \
-+	(                                    \
-+	 LIMA_PP_IRQ_END_OF_FRAME          | \
-+	 LIMA_PP_IRQ_MASK_ERROR)
-+
-+/* MMU regs */
-+#define LIMA_MMU_DTE_ADDR                     0x0000
-+#define LIMA_MMU_STATUS                       0x0004
-+#define   LIMA_MMU_STATUS_PAGING_ENABLED      BIT(0)
-+#define   LIMA_MMU_STATUS_PAGE_FAULT_ACTIVE   BIT(1)
-+#define   LIMA_MMU_STATUS_STALL_ACTIVE        BIT(2)
-+#define   LIMA_MMU_STATUS_IDLE                BIT(3)
-+#define   LIMA_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4)
-+#define   LIMA_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5)
-+#define   LIMA_MMU_STATUS_BUS_ID(x)           ((x >> 6) & 0x1F)
-+#define LIMA_MMU_COMMAND                      0x0008
-+#define   LIMA_MMU_COMMAND_ENABLE_PAGING      0x00
-+#define   LIMA_MMU_COMMAND_DISABLE_PAGING     0x01
-+#define   LIMA_MMU_COMMAND_ENABLE_STALL       0x02
-+#define   LIMA_MMU_COMMAND_DISABLE_STALL      0x03
-+#define   LIMA_MMU_COMMAND_ZAP_CACHE          0x04
-+#define   LIMA_MMU_COMMAND_PAGE_FAULT_DONE    0x05
-+#define   LIMA_MMU_COMMAND_HARD_RESET         0x06
-+#define LIMA_MMU_PAGE_FAULT_ADDR              0x000C
-+#define LIMA_MMU_ZAP_ONE_LINE                 0x0010
-+#define LIMA_MMU_INT_RAWSTAT                  0x0014
-+#define LIMA_MMU_INT_CLEAR                    0x0018
-+#define LIMA_MMU_INT_MASK                     0x001C
-+#define   LIMA_MMU_INT_PAGE_FAULT             BIT(0)
-+#define   LIMA_MMU_INT_READ_BUS_ERROR         BIT(1)
-+#define LIMA_MMU_INT_STATUS                   0x0020
-+
-+#define LIMA_VM_FLAG_PRESENT          BIT(0)
-+#define LIMA_VM_FLAG_READ_PERMISSION  BIT(1)
-+#define LIMA_VM_FLAG_WRITE_PERMISSION BIT(2)
-+#define LIMA_VM_FLAG_OVERRIDE_CACHE   BIT(3)
-+#define LIMA_VM_FLAG_WRITE_CACHEABLE  BIT(4)
-+#define LIMA_VM_FLAG_WRITE_ALLOCATE   BIT(5)
-+#define LIMA_VM_FLAG_WRITE_BUFFERABLE BIT(6)
-+#define LIMA_VM_FLAG_READ_CACHEABLE   BIT(7)
-+#define LIMA_VM_FLAG_READ_ALLOCATE    BIT(8)
-+#define LIMA_VM_FLAG_MASK             0x1FF
-+
-+#define LIMA_VM_FLAGS_CACHE (			 \
-+		LIMA_VM_FLAG_PRESENT |		 \
-+		LIMA_VM_FLAG_READ_PERMISSION |	 \
-+		LIMA_VM_FLAG_WRITE_PERMISSION |	 \
-+		LIMA_VM_FLAG_OVERRIDE_CACHE |	 \
-+		LIMA_VM_FLAG_WRITE_CACHEABLE |	 \
-+		LIMA_VM_FLAG_WRITE_BUFFERABLE |	 \
-+		LIMA_VM_FLAG_READ_CACHEABLE |	 \
-+		LIMA_VM_FLAG_READ_ALLOCATE )
-+
-+#define LIMA_VM_FLAGS_UNCACHE (			\
-+		LIMA_VM_FLAG_PRESENT |		\
-+		LIMA_VM_FLAG_READ_PERMISSION |	\
-+		LIMA_VM_FLAG_WRITE_PERMISSION )
-+
-+/* DLBU regs */
-+#define LIMA_DLBU_MASTER_TLLIST_PHYS_ADDR  0x0000
-+#define	LIMA_DLBU_MASTER_TLLIST_VADDR      0x0004
-+#define	LIMA_DLBU_TLLIST_VBASEADDR         0x0008
-+#define	LIMA_DLBU_FB_DIM                   0x000C
-+#define	LIMA_DLBU_TLLIST_CONF              0x0010
-+#define	LIMA_DLBU_START_TILE_POS           0x0014
-+#define	LIMA_DLBU_PP_ENABLE_MASK           0x0018
-+
-+/* BCAST regs */
-+#define LIMA_BCAST_BROADCAST_MASK    0x0
-+#define LIMA_BCAST_INTERRUPT_MASK    0x4
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_sched.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_sched.c
---- linux-4.17/drivers/gpu/drm/lima/lima_sched.c.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_sched.c	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,480 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <linux/kthread.h>
-+#include <linux/slab.h>
-+
-+#include "lima_drv.h"
-+#include "lima_sched.h"
-+#include "lima_vm.h"
-+#include "lima_mmu.h"
-+#include "lima_l2_cache.h"
-+
-+struct lima_fence {
-+	struct dma_fence base;
-+	struct lima_sched_pipe *pipe;
-+};
-+
-+static struct kmem_cache *lima_fence_slab = NULL;
-+
-+int lima_sched_slab_init(void)
-+{
-+	lima_fence_slab = kmem_cache_create(
-+		"lima_fence", sizeof(struct lima_fence), 0,
-+		SLAB_HWCACHE_ALIGN, NULL);
-+	if (!lima_fence_slab)
-+		return -ENOMEM;
-+
-+	return 0;
-+}
-+
-+void lima_sched_slab_fini(void)
-+{
-+	if (lima_fence_slab)
-+		kmem_cache_destroy(lima_fence_slab);
-+}
-+
-+static inline struct lima_fence *to_lima_fence(struct dma_fence *fence)
-+{
-+	return container_of(fence, struct lima_fence, base);
-+}
-+
-+static const char *lima_fence_get_driver_name(struct dma_fence *fence)
-+{
-+	return "lima";
-+}
-+
-+static const char *lima_fence_get_timeline_name(struct dma_fence *fence)
-+{
-+	struct lima_fence *f = to_lima_fence(fence);
-+
-+	return f->pipe->base.name;
-+}
-+
-+static bool lima_fence_enable_signaling(struct dma_fence *fence)
-+{
-+	return true;
-+}
-+
-+static void lima_fence_release_rcu(struct rcu_head *rcu)
-+{
-+	struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
-+	struct lima_fence *fence = to_lima_fence(f);
-+
-+	kmem_cache_free(lima_fence_slab, fence);
-+}
-+
-+static void lima_fence_release(struct dma_fence *fence)
-+{
-+	struct lima_fence *f = to_lima_fence(fence);
-+
-+	call_rcu(&f->base.rcu, lima_fence_release_rcu);
-+}
-+
-+static const struct dma_fence_ops lima_fence_ops = {
-+	.get_driver_name = lima_fence_get_driver_name,
-+	.get_timeline_name = lima_fence_get_timeline_name,
-+	.enable_signaling = lima_fence_enable_signaling,
-+	.wait = dma_fence_default_wait,
-+	.release = lima_fence_release,
-+};
-+
-+static struct lima_fence *lima_fence_create(struct lima_sched_pipe *pipe)
-+{
-+	struct lima_fence *fence;
-+
-+	fence = kmem_cache_zalloc(lima_fence_slab, GFP_KERNEL);
-+	if (!fence)
-+	       return NULL;
-+
-+	fence->pipe = pipe;
-+	dma_fence_init(&fence->base, &lima_fence_ops, &pipe->fence_lock,
-+		       pipe->fence_context, ++pipe->fence_seqno);
-+
-+	return fence;
-+}
-+
-+static inline struct lima_sched_task *to_lima_task(struct drm_sched_job *job)
-+{
-+	return container_of(job, struct lima_sched_task, base);
-+}
-+
-+static inline struct lima_sched_pipe *to_lima_pipe(struct drm_gpu_scheduler *sched)
-+{
-+	return container_of(sched, struct lima_sched_pipe, base);
-+}
-+
-+int lima_sched_task_init(struct lima_sched_task *task,
-+			 struct lima_sched_context *context,
-+			 struct lima_vm *vm)
-+{
-+	int err;
-+
-+	err = drm_sched_job_init(&task->base, context->base.sched,
-+				 &context->base, vm);
-+	if (err)
-+		return err;
-+
-+	task->vm = lima_vm_get(vm);
-+	return 0;
-+}
-+
-+void lima_sched_task_fini(struct lima_sched_task *task)
-+{
-+	dma_fence_put(&task->base.s_fence->finished);
-+}
-+
-+int lima_sched_task_add_dep(struct lima_sched_task *task, struct dma_fence *fence)
-+{
-+	int i, new_dep = 4;
-+
-+	/* same context's fence is definitly earlier then this task */
-+	if (fence->context == task->base.s_fence->finished.context)
-+		return 0;
-+
-+	if (task->dep && task->num_dep == task->max_dep)
-+		new_dep = task->max_dep * 2;
-+
-+	if (task->max_dep < new_dep) {
-+		void *dep = krealloc(task->dep, sizeof(*task->dep) * new_dep, GFP_KERNEL);
-+		if (!dep)
-+			return -ENOMEM;
-+		task->max_dep = new_dep;
-+		task->dep = dep;
-+	}
-+
-+	for (i = 0; i < task->num_dep; i++) {
-+		if (task->dep[i]->context == fence->context &&
-+		    dma_fence_is_later(fence, task->dep[i])) {
-+			dma_fence_put(task->dep[i]);
-+			task->dep[i] = fence;
-+			return 0;
-+		}
-+	}
-+
-+	task->dep[task->num_dep++] = fence;
-+	return 0;
-+}
-+
-+int lima_sched_context_init(struct lima_sched_pipe *pipe,
-+			    struct lima_sched_context *context,
-+			    atomic_t *guilty)
-+{
-+	struct drm_sched_rq *rq = pipe->base.sched_rq + DRM_SCHED_PRIORITY_NORMAL;
-+	int err;
-+
-+	context->fences =
-+		kzalloc(sizeof(*context->fences) * lima_sched_max_tasks, GFP_KERNEL);
-+	if (!context->fences)
-+		return -ENOMEM;
-+
-+	mutex_init(&context->lock);
-+	err = drm_sched_entity_init(&pipe->base, &context->base, rq,
-+				    lima_sched_max_tasks, guilty);
-+	if (err) {
-+		kfree(context->fences);
-+		context->fences = NULL;
-+		return err;
-+	}
-+
-+	return 0;
-+}
-+
-+void lima_sched_context_fini(struct lima_sched_pipe *pipe,
-+			     struct lima_sched_context *context)
-+{
-+	drm_sched_entity_fini(&pipe->base, &context->base);
-+
-+	mutex_destroy(&context->lock);
-+
-+	if (context->fences)
-+		kfree(context->fences);
-+}
-+
-+static uint32_t lima_sched_context_add_fence(struct lima_sched_context *context,
-+					     struct dma_fence *fence,
-+					     uint32_t *done)
-+{
-+	uint32_t seq, idx, i;
-+	struct dma_fence *other;
-+
-+	mutex_lock(&context->lock);
-+
-+	seq = context->sequence;
-+	idx = seq & (lima_sched_max_tasks - 1);
-+	other = context->fences[idx];
-+
-+	if (other) {
-+		int err = dma_fence_wait(other, false);
-+		if (err)
-+			DRM_ERROR("Error %d waiting context fence\n", err);
-+	}
-+
-+	context->fences[idx] = dma_fence_get(fence);
-+	context->sequence++;
-+
-+	/* get finished fence offset from seq */
-+	for (i = 1; i < lima_sched_max_tasks; i++) {
-+		idx = (seq - i) & (lima_sched_max_tasks - 1);
-+		if (!context->fences[idx] ||
-+		    dma_fence_is_signaled(context->fences[idx]))
-+			break;
-+	}
-+
-+	mutex_unlock(&context->lock);
-+
-+	dma_fence_put(other);
-+
-+	*done = i;
-+	return seq;
-+}
-+
-+struct dma_fence *lima_sched_context_get_fence(
-+	struct lima_sched_context *context, uint32_t seq)
-+{
-+	struct dma_fence *fence;
-+	int idx;
-+	uint32_t max, min;
-+
-+	mutex_lock(&context->lock);
-+
-+	max = context->sequence - 1;
-+	min = context->sequence - lima_sched_max_tasks;
-+
-+	/* handle overflow case */
-+	if ((min < max && (seq < min || seq > max)) ||
-+	    (min > max && (seq < min && seq > max))) {
-+		    fence = NULL;
-+		    goto out;
-+	}
-+
-+	idx = seq & (lima_sched_max_tasks - 1);
-+	fence = dma_fence_get(context->fences[idx]);
-+
-+out:
-+	mutex_unlock(&context->lock);
-+
-+	return fence;
-+}
-+
-+uint32_t lima_sched_context_queue_task(struct lima_sched_context *context,
-+				       struct lima_sched_task *task,
-+				       uint32_t *done)
-+{
-+	uint32_t seq = lima_sched_context_add_fence(
-+		context, &task->base.s_fence->finished, done);
-+	drm_sched_entity_push_job(&task->base, &context->base);
-+	return seq;
-+}
-+
-+static struct dma_fence *lima_sched_dependency(struct drm_sched_job *job,
-+					       struct drm_sched_entity *entity)
-+{
-+	struct lima_sched_task *task = to_lima_task(job);
-+	int i;
-+
-+	for (i = 0; i < task->num_dep; i++) {
-+		struct dma_fence *fence = task->dep[i];
-+
-+		if (!task->dep[i])
-+			continue;
-+
-+		task->dep[i] = NULL;
-+
-+		if (!dma_fence_is_signaled(fence))
-+			return fence;
-+
-+		dma_fence_put(fence);
-+	}
-+
-+	return NULL;
-+}
-+
-+static struct dma_fence *lima_sched_run_job(struct drm_sched_job *job)
-+{
-+	struct lima_sched_task *task = to_lima_task(job);
-+	struct lima_sched_pipe *pipe = to_lima_pipe(job->sched);
-+	struct lima_fence *fence;
-+	struct dma_fence *ret;
-+	struct lima_vm *vm = NULL, *last_vm = NULL;
-+	int i;
-+
-+	/* after GPU reset */
-+	if (job->s_fence->finished.error < 0)
-+		return NULL;
-+
-+	fence = lima_fence_create(pipe);
-+	if (!fence)
-+		return NULL;
-+	task->fence = &fence->base;
-+
-+	/* for caller usage of the fence, otherwise irq handler 
-+	 * may consume the fence before caller use it */
-+	ret = dma_fence_get(task->fence);
-+
-+	pipe->current_task = task;
-+
-+	/* this is needed for MMU to work correctly, otherwise GP/PP
-+	 * will hang or page fault for unknown reason after running for
-+	 * a while.
-+	 *
-+	 * Need to investigate:
-+	 * 1. is it related to TLB
-+	 * 2. how much performance will be affected by L2 cache flush
-+	 * 3. can we reduce the calling of this function because all
-+	 *    GP/PP use the same L2 cache on mali400
-+	 *
-+	 * TODO:
-+	 * 1. move this to task fini to save some wait time?
-+	 * 2. when GP/PP use different l2 cache, need PP wait GP l2
-+	 *    cache flush?
-+	 */
-+	for (i = 0; i < pipe->num_l2_cache; i++)
-+		lima_l2_cache_flush(pipe->l2_cache[i]);
-+
-+	if (task->vm != pipe->current_vm) {
-+		vm = lima_vm_get(task->vm);
-+		last_vm = pipe->current_vm;
-+		pipe->current_vm = task->vm;
-+	}
-+
-+	if (pipe->bcast_mmu)
-+		lima_mmu_switch_vm(pipe->bcast_mmu, vm);
-+	else {
-+		for (i = 0; i < pipe->num_mmu; i++)
-+			lima_mmu_switch_vm(pipe->mmu[i], vm);
-+	}
-+
-+	if (last_vm)
-+		lima_vm_put(last_vm);
-+
-+	pipe->error = false;
-+	pipe->task_run(pipe, task);
-+
-+	return task->fence;
-+}
-+
-+static void lima_sched_handle_error_task(struct lima_sched_pipe *pipe,
-+					 struct lima_sched_task *task)
-+{
-+	kthread_park(pipe->base.thread);
-+	drm_sched_hw_job_reset(&pipe->base, &task->base);
-+
-+	pipe->task_error(pipe);
-+
-+	if (pipe->bcast_mmu)
-+		lima_mmu_page_fault_resume(pipe->bcast_mmu);
-+	else {
-+		int i;
-+		for (i = 0; i < pipe->num_mmu; i++)
-+			lima_mmu_page_fault_resume(pipe->mmu[i]);
-+	}
-+
-+	if (pipe->current_vm)
-+		lima_vm_put(pipe->current_vm);
-+
-+	pipe->current_vm = NULL;
-+	pipe->current_task = NULL;
-+
-+	drm_sched_job_recovery(&pipe->base);
-+	kthread_unpark(pipe->base.thread);
-+}
-+
-+static void lima_sched_timedout_job(struct drm_sched_job *job)
-+{
-+	struct lima_sched_pipe *pipe = to_lima_pipe(job->sched);
-+	struct lima_sched_task *task = to_lima_task(job);
-+
-+	lima_sched_handle_error_task(pipe, task);
-+}
-+
-+static void lima_sched_free_job(struct drm_sched_job *job)
-+{
-+	struct lima_sched_task *task = to_lima_task(job);
-+	struct lima_sched_pipe *pipe = to_lima_pipe(job->sched);
-+	int i;
-+
-+	dma_fence_put(task->fence);
-+
-+	for (i = 0; i < task->num_dep; i++) {
-+		if (task->dep[i])
-+			dma_fence_put(task->dep[i]);
-+	}
-+
-+	if (task->dep)
-+		kfree(task->dep);
-+
-+	lima_vm_put(task->vm);
-+	kmem_cache_free(pipe->task_slab, task);
-+}
-+
-+const struct drm_sched_backend_ops lima_sched_ops = {
-+	.dependency = lima_sched_dependency,
-+	.run_job = lima_sched_run_job,
-+	.timedout_job = lima_sched_timedout_job,
-+	.free_job = lima_sched_free_job,
-+};
-+
-+static void lima_sched_error_work(struct work_struct *work)
-+{
-+	struct lima_sched_pipe *pipe =
-+		container_of(work, struct lima_sched_pipe, error_work);
-+	struct lima_sched_task *task = pipe->current_task;
-+
-+	lima_sched_handle_error_task(pipe, task);
-+}
-+
-+int lima_sched_pipe_init(struct lima_sched_pipe *pipe, const char *name)
-+{
-+	long timeout;
-+
-+	if (lima_sched_timeout_ms <= 0)
-+		timeout = MAX_SCHEDULE_TIMEOUT;
-+	else
-+		timeout = msecs_to_jiffies(lima_sched_timeout_ms);
-+
-+	pipe->fence_context = dma_fence_context_alloc(1);
-+	spin_lock_init(&pipe->fence_lock);
-+
-+	INIT_WORK(&pipe->error_work, lima_sched_error_work);
-+
-+	return drm_sched_init(&pipe->base, &lima_sched_ops, 1, 0, timeout, name);
-+}
-+
-+void lima_sched_pipe_fini(struct lima_sched_pipe *pipe)
-+{
-+	drm_sched_fini(&pipe->base);
-+}
-+
-+unsigned long lima_timeout_to_jiffies(u64 timeout_ns)
-+{
-+	unsigned long timeout_jiffies;
-+	ktime_t timeout;
-+
-+	/* clamp timeout if it's to large */
-+	if (((s64)timeout_ns) < 0)
-+		return MAX_SCHEDULE_TIMEOUT;
-+
-+	timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
-+	if (ktime_to_ns(timeout) < 0)
-+		return 0;
-+
-+	timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
-+	/*  clamp timeout to avoid unsigned-> signed overflow */
-+	if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
-+		return MAX_SCHEDULE_TIMEOUT;
-+
-+	return timeout_jiffies;
-+}
-+
-+void lima_sched_pipe_task_done(struct lima_sched_pipe *pipe)
-+{
-+	if (pipe->error)
-+	        schedule_work(&pipe->error_work);
-+	else {
-+		struct lima_sched_task *task = pipe->current_task;
-+
-+		pipe->task_fini(pipe);
-+		dma_fence_signal(task->fence);
-+	}
-+}
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_sched.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_sched.h
---- linux-4.17/drivers/gpu/drm/lima/lima_sched.h.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_sched.h	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,108 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_SCHED_H__
-+#define __LIMA_SCHED_H__
-+
-+#include <drm/gpu_scheduler.h>
-+
-+struct lima_vm;
-+
-+struct lima_sched_task {
-+	struct drm_sched_job base;
-+
-+	struct lima_vm *vm;
-+	void *frame;
-+
-+	struct dma_fence **dep;
-+	int num_dep;
-+	int max_dep;
-+
-+	/* pipe fence */
-+	struct dma_fence *fence;
-+};
-+
-+struct lima_sched_context {
-+	struct drm_sched_entity base;
-+	struct mutex lock;
-+	struct dma_fence **fences;
-+	uint32_t sequence;
-+};
-+
-+#define LIMA_SCHED_PIPE_MAX_MMU       8
-+#define LIMA_SCHED_PIPE_MAX_L2_CACHE  2
-+#define LIMA_SCHED_PIPE_MAX_PROCESSOR 8
-+
-+struct lima_ip;
-+
-+struct lima_sched_pipe {
-+	struct drm_gpu_scheduler base;
-+
-+	u64 fence_context;
-+	u32 fence_seqno;
-+	spinlock_t fence_lock;
-+
-+	struct lima_sched_task *current_task;
-+	struct lima_vm *current_vm;
-+
-+	struct lima_ip *mmu[LIMA_SCHED_PIPE_MAX_MMU];
-+	int num_mmu;
-+
-+	struct lima_ip *l2_cache[LIMA_SCHED_PIPE_MAX_L2_CACHE];
-+	int num_l2_cache;
-+
-+	struct lima_ip *processor[LIMA_SCHED_PIPE_MAX_PROCESSOR];
-+	int num_processor;
-+
-+	struct lima_ip *bcast_processor;
-+	struct lima_ip *bcast_mmu;
-+
-+	u32 done;
-+	bool error;
-+	atomic_t task;
-+
-+	int frame_size;
-+	struct kmem_cache *task_slab;
-+
-+	int (*task_validate)(struct lima_sched_pipe *pipe, struct lima_sched_task *task);
-+	void (*task_run)(struct lima_sched_pipe *pipe, struct lima_sched_task *task);
-+	void (*task_fini)(struct lima_sched_pipe *pipe);
-+	void (*task_error)(struct lima_sched_pipe *pipe);
-+	void (*task_mmu_error)(struct lima_sched_pipe *pipe);
-+
-+	struct work_struct error_work;
-+};
-+
-+int lima_sched_task_init(struct lima_sched_task *task,
-+			 struct lima_sched_context *context,
-+			 struct lima_vm *vm);
-+void lima_sched_task_fini(struct lima_sched_task *task);
-+int lima_sched_task_add_dep(struct lima_sched_task *task, struct dma_fence *fence);
-+
-+int lima_sched_context_init(struct lima_sched_pipe *pipe,
-+			    struct lima_sched_context *context,
-+			    atomic_t *guilty);
-+void lima_sched_context_fini(struct lima_sched_pipe *pipe,
-+			     struct lima_sched_context *context);
-+uint32_t lima_sched_context_queue_task(struct lima_sched_context *context,
-+				       struct lima_sched_task *task,
-+				       uint32_t *done);
-+struct dma_fence *lima_sched_context_get_fence(
-+	struct lima_sched_context *context, uint32_t seq);
-+
-+int lima_sched_pipe_init(struct lima_sched_pipe *pipe, const char *name);
-+void lima_sched_pipe_fini(struct lima_sched_pipe *pipe);
-+void lima_sched_pipe_task_done(struct lima_sched_pipe *pipe);
-+
-+static inline void lima_sched_pipe_mmu_error(struct lima_sched_pipe *pipe)
-+{
-+	pipe->error = true;
-+	pipe->task_mmu_error(pipe);
-+}
-+
-+int lima_sched_slab_init(void);
-+void lima_sched_slab_fini(void);
-+
-+unsigned long lima_timeout_to_jiffies(u64 timeout_ns);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_ttm.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_ttm.c
---- linux-4.17/drivers/gpu/drm/lima/lima_ttm.c.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_ttm.c	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,390 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <linux/mm.h>
-+#include <drm/ttm/ttm_page_alloc.h>
-+
-+#include "lima_drv.h"
-+#include "lima_device.h"
-+#include "lima_object.h"
-+
-+
-+static int lima_ttm_mem_global_init(struct drm_global_reference *ref)
-+{
-+	return ttm_mem_global_init(ref->object);
-+}
-+
-+static void lima_ttm_mem_global_release(struct drm_global_reference *ref)
-+{
-+	ttm_mem_global_release(ref->object);
-+}
-+
-+static int lima_ttm_global_init(struct lima_device *dev)
-+{
-+	struct drm_global_reference *global_ref;
-+	int err;
-+
-+	dev->mman.mem_global_referenced = false;
-+	global_ref = &dev->mman.mem_global_ref;
-+	global_ref->global_type = DRM_GLOBAL_TTM_MEM;
-+	global_ref->size = sizeof(struct ttm_mem_global);
-+	global_ref->init = &lima_ttm_mem_global_init;
-+	global_ref->release = &lima_ttm_mem_global_release;
-+
-+	err = drm_global_item_ref(global_ref);
-+	if (err != 0) {
-+		dev_err(dev->dev, "Failed setting up TTM memory accounting "
-+			"subsystem.\n");
-+		return err;
-+	}
-+
-+	dev->mman.bo_global_ref.mem_glob =
-+		dev->mman.mem_global_ref.object;
-+	global_ref = &dev->mman.bo_global_ref.ref;
-+	global_ref->global_type = DRM_GLOBAL_TTM_BO;
-+	global_ref->size = sizeof(struct ttm_bo_global);
-+	global_ref->init = &ttm_bo_global_init;
-+	global_ref->release = &ttm_bo_global_release;
-+	err = drm_global_item_ref(global_ref);
-+	if (err != 0) {
-+		dev_err(dev->dev, "Failed setting up TTM BO subsystem.\n");
-+		drm_global_item_unref(&dev->mman.mem_global_ref);
-+		return err;
-+	}
-+
-+	dev->mman.mem_global_referenced = true;
-+	return 0;
-+}
-+
-+static void lima_ttm_global_fini(struct lima_device *dev)
-+{
-+	if (dev->mman.mem_global_referenced) {
-+		drm_global_item_unref(&dev->mman.bo_global_ref.ref);
-+		drm_global_item_unref(&dev->mman.mem_global_ref);
-+		dev->mman.mem_global_referenced = false;
-+	}
-+}
-+
-+struct lima_tt_mgr {
-+	spinlock_t lock;
-+	unsigned long available;
-+};
-+
-+static int lima_ttm_bo_man_init(struct ttm_mem_type_manager *man,
-+				unsigned long p_size)
-+{
-+	struct lima_tt_mgr *mgr;
-+
-+	mgr = kmalloc(sizeof(*mgr), GFP_KERNEL);
-+	if (!mgr)
-+		return -ENOMEM;
-+
-+	spin_lock_init(&mgr->lock);
-+	mgr->available = p_size;
-+	man->priv = mgr;
-+	return 0;
-+}
-+
-+static int lima_ttm_bo_man_takedown(struct ttm_mem_type_manager *man)
-+{
-+	struct lima_tt_mgr *mgr = man->priv;
-+
-+	kfree(mgr);
-+	man->priv = NULL;
-+	return 0;
-+}
-+
-+static int lima_ttm_bo_man_get_node(struct ttm_mem_type_manager *man,
-+				    struct ttm_buffer_object *bo,
-+				    const struct ttm_place *place,
-+				    struct ttm_mem_reg *mem)
-+{
-+	struct lima_tt_mgr *mgr = man->priv;
-+
-+	/* don't exceed the mem limit */
-+	spin_lock(&mgr->lock);
-+	if (mgr->available < mem->num_pages) {
-+		spin_unlock(&mgr->lock);
-+		return 0;
-+	}
-+	mgr->available -= mem->num_pages;
-+	spin_unlock(&mgr->lock);
-+
-+	/* just fake a non-null pointer to tell caller success */
-+	mem->mm_node = (void *)1;
-+	return 0;
-+}
-+
-+static void lima_ttm_bo_man_put_node(struct ttm_mem_type_manager *man,
-+				     struct ttm_mem_reg *mem)
-+{
-+	struct lima_tt_mgr *mgr = man->priv;
-+
-+	spin_lock(&mgr->lock);
-+	mgr->available += mem->num_pages;
-+	spin_unlock(&mgr->lock);
-+
-+	mem->mm_node = NULL;
-+}
-+
-+static void lima_ttm_bo_man_debug(struct ttm_mem_type_manager *man,
-+				  struct drm_printer *printer)
-+{
-+}
-+
-+static const struct ttm_mem_type_manager_func lima_bo_manager_func = {
-+	.init = lima_ttm_bo_man_init,
-+	.takedown = lima_ttm_bo_man_takedown,
-+	.get_node = lima_ttm_bo_man_get_node,
-+	.put_node = lima_ttm_bo_man_put_node,
-+	.debug = lima_ttm_bo_man_debug
-+};
-+
-+static int lima_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
-+			      struct ttm_mem_type_manager *man)
-+{
-+	struct lima_device *dev = ttm_to_lima_dev(bdev);
-+
-+	switch (type) {
-+	case TTM_PL_SYSTEM:
-+		/* System memory */
-+		man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
-+		man->available_caching = TTM_PL_MASK_CACHING;
-+		man->default_caching = TTM_PL_FLAG_CACHED;
-+		break;
-+	case TTM_PL_TT:
-+		man->func = &lima_bo_manager_func;
-+		man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
-+		man->available_caching = TTM_PL_MASK_CACHING;
-+		man->default_caching = TTM_PL_FLAG_CACHED;
-+		break;
-+	default:
-+		dev_err(dev->dev, "Unsupported memory type %u\n",
-+			(unsigned int)type);
-+		return -EINVAL;
-+	}
-+	return 0;
-+}
-+
-+static int lima_ttm_backend_bind(struct ttm_tt *ttm,
-+				 struct ttm_mem_reg *bo_mem)
-+{
-+	return 0;
-+}
-+
-+static int lima_ttm_backend_unbind(struct ttm_tt *ttm)
-+{
-+	return 0;
-+}
-+
-+static void lima_ttm_backend_destroy(struct ttm_tt *ttm)
-+{
-+	struct lima_ttm_tt *tt = (void *)ttm;
-+
-+	ttm_dma_tt_fini(&tt->ttm);
-+	kfree(tt);
-+}
-+
-+static struct ttm_backend_func lima_ttm_backend_func = {
-+	.bind = &lima_ttm_backend_bind,
-+	.unbind = &lima_ttm_backend_unbind,
-+	.destroy = &lima_ttm_backend_destroy,
-+};
-+
-+static struct ttm_tt *lima_ttm_tt_create(struct ttm_buffer_object *bo,
-+					 uint32_t page_flags)
-+{
-+	struct lima_ttm_tt *tt;
-+
-+	tt = kzalloc(sizeof(struct lima_ttm_tt), GFP_KERNEL);
-+	if (tt == NULL)
-+		return NULL;
-+
-+	tt->ttm.ttm.func = &lima_ttm_backend_func;
-+
-+	if (ttm_sg_tt_init(&tt->ttm, bo, page_flags)) {
-+		kfree(tt);
-+		return NULL;
-+	}
-+
-+	return &tt->ttm.ttm;
-+}
-+
-+static int lima_ttm_tt_populate(struct ttm_tt *ttm,
-+				struct ttm_operation_ctx *ctx)
-+{
-+	struct lima_device *dev = ttm_to_lima_dev(ttm->bdev);
-+	struct lima_ttm_tt *tt = (void *)ttm;
-+	bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
-+
-+	if (slave) {
-+		drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
-+						 tt->ttm.dma_address,
-+						 ttm->num_pages);
-+		ttm->state = tt_unbound;
-+		return 0;
-+	}
-+
-+	return ttm_populate_and_map_pages(dev->dev, &tt->ttm, ctx);
-+}
-+
-+static void lima_ttm_tt_unpopulate(struct ttm_tt *ttm)
-+{
-+	struct lima_device *dev = ttm_to_lima_dev(ttm->bdev);
-+	struct lima_ttm_tt *tt = (void *)ttm;
-+	bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
-+
-+	if (slave)
-+		return;
-+
-+	ttm_unmap_and_unpopulate_pages(dev->dev, &tt->ttm);
-+}
-+
-+static int lima_invalidate_caches(struct ttm_bo_device *bdev,
-+				  uint32_t flags)
-+{
-+	struct lima_device *dev = ttm_to_lima_dev(bdev);
-+
-+	dev_err(dev->dev, "%s not implemented\n", __FUNCTION__);
-+	return 0;
-+}
-+
-+static void lima_evict_flags(struct ttm_buffer_object *tbo,
-+			     struct ttm_placement *placement)
-+{
-+	struct lima_bo *bo = ttm_to_lima_bo(tbo);
-+	struct lima_device *dev = to_lima_dev(bo->gem.dev);
-+
-+	dev_err(dev->dev, "%s not implemented\n", __FUNCTION__);
-+}
-+
-+static int lima_verify_access(struct ttm_buffer_object *tbo,
-+			      struct file *filp)
-+{
-+	struct lima_bo *bo = ttm_to_lima_bo(tbo);
-+
-+	return drm_vma_node_verify_access(&bo->gem.vma_node,
-+					  filp->private_data);
-+}
-+
-+static int lima_ttm_io_mem_reserve(struct ttm_bo_device *bdev,
-+				   struct ttm_mem_reg *mem)
-+{
-+	struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
-+
-+	mem->bus.addr = NULL;
-+	mem->bus.offset = 0;
-+	mem->bus.size = mem->num_pages << PAGE_SHIFT;
-+	mem->bus.base = 0;
-+	mem->bus.is_iomem = false;
-+
-+	if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
-+		return -EINVAL;
-+
-+	switch (mem->mem_type) {
-+	case TTM_PL_SYSTEM:
-+	case TTM_PL_TT:
-+		return 0;
-+	default:
-+		return -EINVAL;
-+	}
-+	return 0;
-+}
-+
-+static void lima_ttm_io_mem_free(struct ttm_bo_device *bdev,
-+				 struct ttm_mem_reg *mem)
-+{
-+
-+}
-+
-+static void lima_bo_move_notify(struct ttm_buffer_object *tbo, bool evict,
-+				struct ttm_mem_reg *new_mem)
-+{
-+	struct lima_bo *bo = ttm_to_lima_bo(tbo);
-+	struct lima_device *dev = to_lima_dev(bo->gem.dev);
-+
-+	if (evict)
-+		dev_err(dev->dev, "%s not implemented\n", __FUNCTION__);
-+}
-+
-+static void lima_bo_swap_notify(struct ttm_buffer_object *tbo)
-+{
-+	struct lima_bo *bo = ttm_to_lima_bo(tbo);
-+	struct lima_device *dev = to_lima_dev(bo->gem.dev);
-+
-+	dev_err(dev->dev, "%s not implemented\n", __FUNCTION__);
-+}
-+
-+static struct ttm_bo_driver lima_bo_driver = {
-+	.ttm_tt_create = lima_ttm_tt_create,
-+	.ttm_tt_populate = lima_ttm_tt_populate,
-+	.ttm_tt_unpopulate = lima_ttm_tt_unpopulate,
-+	.invalidate_caches = lima_invalidate_caches,
-+	.init_mem_type = lima_init_mem_type,
-+	.eviction_valuable = ttm_bo_eviction_valuable,
-+	.evict_flags = lima_evict_flags,
-+	.verify_access = lima_verify_access,
-+	.io_mem_reserve = lima_ttm_io_mem_reserve,
-+	.io_mem_free = lima_ttm_io_mem_free,
-+	.move_notify = lima_bo_move_notify,
-+	.swap_notify = lima_bo_swap_notify,
-+};
-+
-+int lima_ttm_init(struct lima_device *dev)
-+{
-+	int err;
-+	bool need_dma32;
-+	u64 gtt_size;
-+
-+	err = lima_ttm_global_init(dev);
-+	if (err)
-+		return err;
-+
-+#if defined(CONFIG_ARM) && !defined(CONFIG_ARM_LPAE)
-+	need_dma32 = false;
-+#else
-+	need_dma32 = true;
-+#endif
-+
-+	err = ttm_bo_device_init(&dev->mman.bdev,
-+				 dev->mman.bo_global_ref.ref.object,
-+				 &lima_bo_driver,
-+				 dev->ddev->anon_inode->i_mapping,
-+				 DRM_FILE_PAGE_OFFSET,
-+				 need_dma32);
-+	if (err) {
-+		dev_err(dev->dev, "failed initializing buffer object "
-+			"driver(%d).\n", err);
-+		goto err_out0;
-+	}
-+
-+	if (lima_max_mem < 0) {
-+		struct sysinfo si;
-+		si_meminfo(&si);
-+		/* TODO: better to have lower 32 mem size */
-+		gtt_size = min(((u64)si.totalram * si.mem_unit * 3/4),
-+			       0x100000000ULL);
-+	}
-+	else
-+		gtt_size = (u64)lima_max_mem << 20;
-+
-+	err = ttm_bo_init_mm(&dev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
-+	if (err) {
-+		dev_err(dev->dev, "Failed initializing GTT heap.\n");
-+		goto err_out1;
-+	}
-+	return 0;
-+
-+err_out1:
-+	ttm_bo_device_release(&dev->mman.bdev);
-+err_out0:
-+	lima_ttm_global_fini(dev);
-+	return err;
-+}
-+
-+void lima_ttm_fini(struct lima_device *dev)
-+{
-+	ttm_bo_device_release(&dev->mman.bdev);
-+	lima_ttm_global_fini(dev);
-+	dev_info(dev->dev, "ttm finalized\n");
-+}
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_ttm.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_ttm.h
---- linux-4.17/drivers/gpu/drm/lima/lima_ttm.h.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_ttm.h	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,26 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_TTM_H__
-+#define __LIMA_TTM_H__
-+
-+#include <drm/ttm/ttm_bo_driver.h>
-+
-+struct lima_mman {
-+	struct ttm_bo_global_ref bo_global_ref;
-+	struct drm_global_reference mem_global_ref;
-+	struct ttm_bo_device bdev;
-+	bool mem_global_referenced;
-+};
-+
-+struct lima_ttm_tt {
-+	struct ttm_dma_tt ttm;
-+};
-+
-+struct lima_device;
-+struct lima_bo;
-+
-+int lima_ttm_init(struct lima_device *dev);
-+void lima_ttm_fini(struct lima_device *dev);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_vm.c.0150~ linux-4.17/drivers/gpu/drm/lima/lima_vm.c
---- linux-4.17/drivers/gpu/drm/lima/lima_vm.c.0150~	2018-07-02 19:37:08.165000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_vm.c	2018-07-02 19:37:08.165000956 +0200
-@@ -0,0 +1,354 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#include <linux/slab.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/interval_tree_generic.h>
-+
-+#include "lima_device.h"
-+#include "lima_vm.h"
-+#include "lima_object.h"
-+#include "lima_regs.h"
-+
-+struct lima_bo_va_mapping {
-+	struct list_head list;
-+	struct rb_node rb;
-+	uint32_t start;
-+	uint32_t last;
-+	uint32_t __subtree_last;
-+};
-+
-+struct lima_bo_va {
-+	struct list_head list;
-+	unsigned ref_count;
-+
-+	struct list_head mapping;
-+
-+	struct lima_vm *vm;
-+};
-+
-+#define LIMA_VM_PD_SHIFT 22
-+#define LIMA_VM_PT_SHIFT 12
-+#define LIMA_VM_PB_SHIFT (LIMA_VM_PD_SHIFT + LIMA_VM_NUM_PT_PER_BT_SHIFT)
-+#define LIMA_VM_BT_SHIFT LIMA_VM_PT_SHIFT
-+
-+#define LIMA_VM_PT_MASK ((1 << LIMA_VM_PD_SHIFT) - 1)
-+#define LIMA_VM_BT_MASK ((1 << LIMA_VM_PB_SHIFT) - 1)
-+
-+#define LIMA_PDE(va) (va >> LIMA_VM_PD_SHIFT)
-+#define LIMA_PTE(va) ((va & LIMA_VM_PT_MASK) >> LIMA_VM_PT_SHIFT)
-+#define LIMA_PBE(va) (va >> LIMA_VM_PB_SHIFT)
-+#define LIMA_BTE(va) ((va & LIMA_VM_BT_MASK) >> LIMA_VM_BT_SHIFT)
-+
-+#define START(node) ((node)->start)
-+#define LAST(node) ((node)->last)
-+
-+INTERVAL_TREE_DEFINE(struct lima_bo_va_mapping, rb, uint32_t, __subtree_last,
-+		     START, LAST, static, lima_vm_it)
-+
-+#undef START
-+#undef LAST
-+
-+static void lima_vm_unmap_page_table(struct lima_vm *vm, u32 start, u32 end)
-+{
-+	u32 addr;
-+
-+	for (addr = start; addr <= end; addr += LIMA_PAGE_SIZE) {
-+		u32 pbe = LIMA_PBE(addr);
-+		u32 bte = LIMA_BTE(addr);
-+		u32 *bt;
-+
-+		bt = lima_bo_kmap(vm->bts[pbe]);
-+		bt[bte] = 0;
-+	}
-+}
-+
-+static int lima_vm_map_page_table(struct lima_vm *vm, dma_addr_t *dma,
-+				  u32 start, u32 end)
-+{
-+	u64 addr;
-+	int err, i = 0;
-+
-+	for (addr = start; addr <= end; addr += LIMA_PAGE_SIZE) {
-+		u32 pbe = LIMA_PBE(addr);
-+		u32 bte = LIMA_BTE(addr);
-+		u32 *bt;
-+
-+		if (vm->bts[pbe])
-+			bt = lima_bo_kmap(vm->bts[pbe]);
-+		else {
-+			struct lima_bo *bt_bo;
-+			dma_addr_t *pts;
-+			u32 *pd;
-+			int j;
-+
-+			bt_bo = lima_bo_create(
-+				vm->dev, LIMA_PAGE_SIZE << LIMA_VM_NUM_PT_PER_BT_SHIFT,
-+				0, ttm_bo_type_kernel,
-+				NULL, vm->pd->tbo.resv);
-+			if (IS_ERR(bt_bo)) {
-+				err = PTR_ERR(bt_bo);
-+				goto err_out;
-+			}
-+
-+			bt = lima_bo_kmap(bt_bo);
-+			if (IS_ERR(bt)) {
-+				lima_bo_unref(bt_bo);
-+				err = PTR_ERR(bt);
-+				goto err_out;
-+			}
-+			memset(bt, 0, LIMA_PAGE_SIZE << LIMA_VM_NUM_PT_PER_BT_SHIFT);
-+
-+			vm->bts[pbe] = bt_bo;
-+			pd = lima_bo_kmap(vm->pd);
-+			pd += pbe << LIMA_VM_NUM_PT_PER_BT_SHIFT;
-+			pts = lima_bo_get_pages(bt_bo);
-+			for (j = 0; j < LIMA_VM_NUM_PT_PER_BT; j++)
-+				*pd++ = *pts++ | LIMA_VM_FLAG_PRESENT;
-+		}
-+
-+		bt[bte] = dma[i++] | LIMA_VM_FLAGS_CACHE;
-+	}
-+
-+	return 0;
-+
-+err_out:
-+	if (addr != start)
-+		lima_vm_unmap_page_table(vm, start, addr - 1);
-+	return err;
-+}
-+
-+static struct lima_bo_va *
-+lima_vm_bo_find(struct lima_vm *vm, struct lima_bo *bo)
-+{
-+	struct lima_bo_va *bo_va, *ret = NULL;
-+
-+	list_for_each_entry(bo_va, &bo->va, list) {
-+		if (bo_va->vm == vm) {
-+			ret = bo_va;
-+			break;
-+		}
-+	}
-+
-+	return ret;
-+}
-+
-+int lima_vm_bo_map(struct lima_vm *vm, struct lima_bo *bo, u32 start)
-+{
-+	int err;
-+	struct lima_bo_va_mapping *it, *mapping;
-+	u32 end = start + bo->gem.size - 1;
-+	dma_addr_t *pages_dma = lima_bo_get_pages(bo);
-+	struct lima_bo_va *bo_va;
-+
-+	it = lima_vm_it_iter_first(&vm->va, start, end);
-+	if (it) {
-+		dev_dbg(bo->gem.dev->dev, "lima vm map va overlap %x-%x %x-%x\n",
-+			start, end, it->start, it->last);
-+		return -EINVAL;
-+	}
-+
-+	mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
-+	if (!mapping)
-+		return -ENOMEM;
-+	mapping->start = start;
-+	mapping->last = end;
-+
-+	err = lima_vm_map_page_table(vm, pages_dma, start, end);
-+	if (err) {
-+		kfree(mapping);
-+		return err;
-+	}
-+
-+	lima_vm_it_insert(mapping, &vm->va);
-+
-+	bo_va = lima_vm_bo_find(vm, bo);
-+	list_add_tail(&mapping->list, &bo_va->mapping);
-+
-+	return 0;
-+}
-+
-+static void lima_vm_unmap(struct lima_vm *vm,
-+			  struct lima_bo_va_mapping *mapping)
-+{
-+	lima_vm_it_remove(mapping, &vm->va);
-+
-+	lima_vm_unmap_page_table(vm, mapping->start, mapping->last);
-+
-+	list_del(&mapping->list);
-+	kfree(mapping);
-+}
-+
-+int lima_vm_bo_unmap(struct lima_vm *vm, struct lima_bo *bo, u32 start)
-+{
-+	struct lima_bo_va *bo_va;
-+	struct lima_bo_va_mapping *mapping;
-+
-+	bo_va = lima_vm_bo_find(vm, bo);
-+	list_for_each_entry(mapping, &bo_va->mapping, list) {
-+		if (mapping->start == start) {
-+		        lima_vm_unmap(vm, mapping);
-+			break;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+int lima_vm_bo_add(struct lima_vm *vm, struct lima_bo *bo)
-+{
-+	struct lima_bo_va *bo_va;
-+
-+	bo_va = lima_vm_bo_find(vm, bo);
-+	if (bo_va) {
-+		bo_va->ref_count++;
-+		return 0;
-+	}
-+
-+	bo_va = kmalloc(sizeof(*bo_va), GFP_KERNEL);
-+	if (!bo_va)
-+		return -ENOMEM;
-+
-+	bo_va->vm = vm;
-+	bo_va->ref_count = 1;
-+	INIT_LIST_HEAD(&bo_va->mapping);
-+	list_add_tail(&bo_va->list, &bo->va);
-+	return 0;
-+}
-+
-+/* wait only fence of resv from task using vm */
-+static int lima_vm_wait_resv(struct lima_vm *vm,
-+			     struct reservation_object *resv)
-+{
-+	unsigned nr_fences;
-+	struct dma_fence **fences;
-+	int i;
-+	long err;
-+
-+	err = reservation_object_get_fences_rcu(resv, NULL, &nr_fences, &fences);
-+	if (err || !nr_fences)
-+		return err;
-+
-+	for (i = 0; i < nr_fences; i++) {
-+		struct drm_sched_fence *sf = to_drm_sched_fence(fences[i]);
-+		if (sf && sf->owner == vm)
-+			err |= dma_fence_wait(fences[i], false);
-+		dma_fence_put(fences[i]);
-+	}
-+
-+	kfree(fences);
-+	return err;
-+}
-+
-+int lima_vm_bo_del(struct lima_vm *vm, struct lima_bo *bo)
-+{
-+	struct lima_bo_va *bo_va;
-+	struct lima_bo_va_mapping *mapping, *tmp;
-+	int err;
-+
-+	bo_va = lima_vm_bo_find(vm, bo);
-+	if (--bo_va->ref_count > 0)
-+		return 0;
-+
-+	/* wait bo idle before unmap it from vm in case user
-+	 * space application is terminated when bo is busy.
-+	 */
-+	err = lima_vm_wait_resv(vm, bo->tbo.resv);
-+	if (err)
-+		dev_err(vm->dev->dev, "bo del fail to wait (%d)\n", err);
-+
-+	list_for_each_entry_safe(mapping, tmp, &bo_va->mapping, list) {
-+	        lima_vm_unmap(vm, mapping);
-+	}
-+	list_del(&bo_va->list);
-+	kfree(bo_va);
-+	return 0;
-+}
-+
-+struct lima_vm *lima_vm_create(struct lima_device *dev)
-+{
-+	struct lima_vm *vm;
-+	void *pd;
-+
-+	vm = kzalloc(sizeof(*vm), GFP_KERNEL);
-+	if (!vm)
-+		return NULL;
-+
-+	vm->dev = dev;
-+	vm->va = RB_ROOT_CACHED;
-+	kref_init(&vm->refcount);
-+
-+	vm->pd = lima_bo_create(dev, LIMA_PAGE_SIZE, 0,
-+				ttm_bo_type_kernel, NULL, NULL);
-+	if (IS_ERR(vm->pd))
-+		goto err_out0;
-+
-+	pd = lima_bo_kmap(vm->pd);
-+	if (IS_ERR(pd))
-+		goto err_out1;
-+	memset(pd, 0, LIMA_PAGE_SIZE);
-+
-+	if (dev->dlbu_cpu) {
-+		int err = lima_vm_map_page_table(
-+			vm, &dev->dlbu_dma, LIMA_VA_RESERVE_DLBU,
-+			LIMA_VA_RESERVE_DLBU + LIMA_PAGE_SIZE - 1);
-+		if (err)
-+			goto err_out1;
-+	}
-+
-+	return vm;
-+
-+err_out1:
-+	lima_bo_unref(vm->pd);
-+err_out0:
-+	kfree(vm);
-+	return NULL;
-+}
-+
-+void lima_vm_release(struct kref *kref)
-+{
-+	struct lima_vm *vm = container_of(kref, struct lima_vm, refcount);
-+	struct lima_device *dev = vm->dev;
-+	int i;
-+
-+	if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
-+		dev_err(dev->dev, "still active bo inside vm\n");
-+	}
-+
-+	for (i = 0; i < LIMA_VM_NUM_BT; i++) {
-+		if (vm->bts[i])
-+			lima_bo_unref(vm->bts[i]);
-+	}
-+
-+	if (vm->pd)
-+	        lima_bo_unref(vm->pd);
-+
-+	kfree(vm);
-+}
-+
-+void lima_vm_print(struct lima_vm *vm)
-+{
-+	int i, j, k;
-+	u32 *pd, *pt;
-+
-+	/* to avoid the defined by not used warning */
-+	(void)&lima_vm_it_iter_next;
-+
-+	pd = lima_bo_kmap(vm->pd);
-+	for (i = 0; i < LIMA_VM_NUM_BT; i++) {
-+		if (!vm->bts[i])
-+			continue;
-+
-+		pt = lima_bo_kmap(vm->bts[i]);
-+		for (j = 0; j < LIMA_VM_NUM_PT_PER_BT; j++) {
-+			int idx = (i << LIMA_VM_NUM_PT_PER_BT_SHIFT) + j;
-+			printk(KERN_INFO "lima vm pd %03x:%08x\n", idx, pd[idx]);
-+
-+			for (k = 0; k < LIMA_PAGE_ENT_NUM; k++) {
-+				u32 pte = *pt++;
-+				if (pte)
-+					printk(KERN_INFO "  pt %03x:%08x\n", k, pte);
-+			}
-+		}
-+	}
-+}
-diff -up linux-4.17/drivers/gpu/drm/lima/lima_vm.h.0150~ linux-4.17/drivers/gpu/drm/lima/lima_vm.h
---- linux-4.17/drivers/gpu/drm/lima/lima_vm.h.0150~	2018-07-02 19:37:08.166000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/lima_vm.h	2018-07-02 19:37:08.166000956 +0200
-@@ -0,0 +1,59 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_VM_H__
-+#define __LIMA_VM_H__
-+
-+#include <linux/rbtree.h>
-+#include <linux/kref.h>
-+
-+#define LIMA_PAGE_SIZE    4096
-+#define LIMA_PAGE_MASK    (LIMA_PAGE_SIZE - 1)
-+#define LIMA_PAGE_ENT_NUM (LIMA_PAGE_SIZE / sizeof(u32))
-+
-+#define LIMA_VM_NUM_PT_PER_BT_SHIFT 3
-+#define LIMA_VM_NUM_PT_PER_BT (1 << LIMA_VM_NUM_PT_PER_BT_SHIFT)
-+#define LIMA_VM_NUM_BT (LIMA_PAGE_ENT_NUM >> LIMA_VM_NUM_PT_PER_BT_SHIFT)
-+
-+#define LIMA_VA_RESERVE_START  0xFFF00000
-+#define LIMA_VA_RESERVE_DLBU   LIMA_VA_RESERVE_START
-+#define LIMA_VA_RESERVE_END    0x100000000
-+
-+struct lima_bo;
-+struct lima_device;
-+
-+struct lima_vm {
-+	struct kref refcount;
-+
-+	/* tree of virtual addresses mapped */
-+	struct rb_root_cached va;
-+
-+	struct lima_device *dev;
-+
-+	struct lima_bo *pd;
-+	struct lima_bo *bts[LIMA_VM_NUM_BT];
-+};
-+
-+int lima_vm_bo_map(struct lima_vm *vm, struct lima_bo *bo, u32 start);
-+int lima_vm_bo_unmap(struct lima_vm *vm, struct lima_bo *bo, u32 start);
-+
-+int lima_vm_bo_add(struct lima_vm *vm, struct lima_bo *bo);
-+int lima_vm_bo_del(struct lima_vm *vm, struct lima_bo *bo);
-+
-+struct lima_vm *lima_vm_create(struct lima_device *dev);
-+void lima_vm_release(struct kref *kref);
-+
-+static inline struct lima_vm *lima_vm_get(struct lima_vm *vm)
-+{
-+	kref_get(&vm->refcount);
-+	return vm;
-+}
-+
-+static inline void lima_vm_put(struct lima_vm *vm)
-+{
-+	kref_put(&vm->refcount, lima_vm_release);
-+}
-+
-+void lima_vm_print(struct lima_vm *vm);
-+
-+#endif
-diff -up linux-4.17/drivers/gpu/drm/lima/Makefile.0150~ linux-4.17/drivers/gpu/drm/lima/Makefile
---- linux-4.17/drivers/gpu/drm/lima/Makefile.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/lima/Makefile	2018-07-02 19:37:08.164000956 +0200
-@@ -0,0 +1,22 @@
-+# SPDX-License-Identifier: GPL-2.0 OR MIT
-+# Copyright 2017-2018 Qiang Yu <yuq825@gmail.com>
-+
-+lima-y := \
-+	lima_drv.o \
-+	lima_device.o \
-+	lima_pmu.o \
-+	lima_l2_cache.o \
-+	lima_mmu.o \
-+	lima_gp.o \
-+	lima_pp.o \
-+	lima_gem.o \
-+	lima_vm.o \
-+	lima_sched.o \
-+	lima_ctx.o \
-+	lima_gem_prime.o \
-+	lima_dlbu.o \
-+	lima_bcast.o \
-+	lima_ttm.o \
-+	lima_object.o
-+
-+obj-$(CONFIG_DRM_LIMA) += lima.o
-diff -up linux-4.17/drivers/gpu/drm/Makefile.0150~ linux-4.17/drivers/gpu/drm/Makefile
---- linux-4.17/drivers/gpu/drm/Makefile.0150~	2018-07-02 19:37:08.164000956 +0200
-+++ linux-4.17/drivers/gpu/drm/Makefile	2018-07-02 19:37:54.583997586 +0200
-@@ -105,3 +105,4 @@ obj-$(CONFIG_DRM_TINYDRM) += tinydrm/
- obj-$(CONFIG_DRM_PL111) += pl111/
- obj-$(CONFIG_DRM_TVE200) += tve200/
- obj-$(CONFIG_DRM_XEN) += xen/
-+obj-$(CONFIG_DRM_LIMA)  += lima/
-diff -up linux-4.17/include/uapi/drm/lima_drm.h.0150~ linux-4.17/include/uapi/drm/lima_drm.h
---- linux-4.17/include/uapi/drm/lima_drm.h.0150~	2018-07-02 19:37:08.166000956 +0200
-+++ linux-4.17/include/uapi/drm/lima_drm.h	2018-07-02 19:37:08.166000956 +0200
-@@ -0,0 +1,188 @@
-+/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */
-+/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
-+
-+#ifndef __LIMA_DRM_H__
-+#define __LIMA_DRM_H__
-+
-+#include "drm.h"
-+
-+#if defined(__cplusplus)
-+extern "C" {
-+#endif
-+
-+#define LIMA_INFO_GPU_MALI400 0x00
-+#define LIMA_INFO_GPU_MALI450 0x01
-+
-+struct drm_lima_info {
-+	__u32 gpu_id;   /* out */
-+	__u32 num_pp;   /* out */
-+	__u64 va_start; /* out */
-+	__u64 va_end;   /* out */
-+};
-+
-+struct drm_lima_gem_create {
-+	__u32 size;    /* in */
-+	__u32 flags;   /* in */
-+	__u32 handle;  /* out */
-+	__u32 pad;
-+};
-+
-+struct drm_lima_gem_info {
-+	__u32 handle;  /* in */
-+	__u32 pad;
-+	__u64 offset;  /* out */
-+};
-+
-+#define LIMA_VA_OP_MAP    1
-+#define LIMA_VA_OP_UNMAP  2
-+
-+struct drm_lima_gem_va {
-+	__u32 handle;  /* in */
-+	__u32 op;      /* in */
-+	__u32 flags;   /* in */
-+	__u32 va;      /* in */
-+};
-+
-+#define LIMA_SUBMIT_BO_READ   0x01
-+#define LIMA_SUBMIT_BO_WRITE  0x02
-+
-+struct drm_lima_gem_submit_bo {
-+	__u32 handle;  /* in */
-+	__u32 flags;   /* in */
-+};
-+
-+#define LIMA_SUBMIT_DEP_FENCE   0x00
-+#define LIMA_SUBMIT_DEP_SYNC_FD 0x01
-+
-+struct drm_lima_gem_submit_dep_fence {
-+	__u32 type;
-+	__u32 ctx;
-+	__u32 pipe;
-+	__u32 seq;
-+};
-+
-+struct drm_lima_gem_submit_dep_sync_fd {
-+	__u32 type;
-+	__u32 fd;
-+};
-+
-+union drm_lima_gem_submit_dep {
-+	__u32 type;
-+	struct drm_lima_gem_submit_dep_fence fence;
-+	struct drm_lima_gem_submit_dep_sync_fd sync_fd;
-+};
-+
-+#define LIMA_GP_FRAME_REG_NUM 6
-+
-+struct drm_lima_gp_frame {
-+	__u32 frame[LIMA_GP_FRAME_REG_NUM];
-+};
-+
-+#define LIMA_PP_FRAME_REG_NUM 23
-+#define LIMA_PP_WB_REG_NUM 12
-+
-+struct drm_lima_m400_pp_frame {
-+	__u32 frame[LIMA_PP_FRAME_REG_NUM];
-+	__u32 num_pp;
-+	__u32 wb[3 * LIMA_PP_WB_REG_NUM];
-+	__u32 plbu_array_address[4];
-+	__u32 fragment_stack_address[4];
-+};
-+
-+struct drm_lima_m450_pp_frame {
-+	__u32 frame[LIMA_PP_FRAME_REG_NUM];
-+	__u32 _pad;
-+	__u32 wb[3 * LIMA_PP_WB_REG_NUM];
-+	__u32 dlbu_regs[4];
-+	__u32 fragment_stack_address[8];
-+};
-+
-+#define LIMA_PIPE_GP  0x00
-+#define LIMA_PIPE_PP  0x01
-+
-+#define LIMA_SUBMIT_FLAG_EXPLICIT_FENCE (1 << 0)
-+#define LIMA_SUBMIT_FLAG_SYNC_FD_OUT    (1 << 1)
-+
-+struct drm_lima_gem_submit_in {
-+	__u32 ctx;
-+	__u32 pipe;
-+	__u32 nr_bos;
-+	__u32 frame_size;
-+	__u64 bos;
-+	__u64 frame;
-+	__u64 deps;
-+	__u32 nr_deps;
-+	__u32 flags;
-+};
-+
-+struct drm_lima_gem_submit_out {
-+	__u32 fence;
-+	__u32 done;
-+	__u32 sync_fd;
-+	__u32 _pad;
-+};
-+
-+union drm_lima_gem_submit {
-+	struct drm_lima_gem_submit_in in;
-+	struct drm_lima_gem_submit_out out;
-+};
-+
-+struct drm_lima_wait_fence {
-+	__u32 ctx;         /* in */
-+	__u32 pipe;        /* in */
-+	__u64 timeout_ns;  /* in */
-+	__u32 seq;         /* in */
-+	__u32 _pad;
-+};
-+
-+#define LIMA_GEM_WAIT_READ   0x01
-+#define LIMA_GEM_WAIT_WRITE  0x02
-+
-+struct drm_lima_gem_wait {
-+	__u32 handle;      /* in */
-+	__u32 op;          /* in */
-+	__u64 timeout_ns;  /* in */
-+};
-+
-+#define LIMA_CTX_OP_CREATE 1
-+#define LIMA_CTX_OP_FREE   2
-+
-+struct drm_lima_ctx {
-+	__u32 op;          /* in */
-+	__u32 id;          /* in/out */
-+};
-+
-+#define LIMA_GEM_MOD_OP_GET 0
-+#define LIMA_GEM_MOD_OP_SET 1
-+
-+struct drm_lima_gem_mod {
-+	__u32 handle;      /* in */
-+	__u32 op;          /* in */
-+	__u64 modifier;    /* in/out */
-+};
-+
-+#define DRM_LIMA_INFO        0x00
-+#define DRM_LIMA_GEM_CREATE  0x01
-+#define DRM_LIMA_GEM_INFO    0x02
-+#define DRM_LIMA_GEM_VA      0x03
-+#define DRM_LIMA_GEM_SUBMIT  0x04
-+#define DRM_LIMA_WAIT_FENCE  0x05
-+#define DRM_LIMA_GEM_WAIT    0x06
-+#define DRM_LIMA_CTX         0x07
-+#define DRM_LIMA_GEM_MOD     0x08
-+
-+#define DRM_IOCTL_LIMA_INFO DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_INFO, struct drm_lima_info)
-+#define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create)
-+#define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info)
-+#define DRM_IOCTL_LIMA_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_VA, struct drm_lima_gem_va)
-+#define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, union drm_lima_gem_submit)
-+#define DRM_IOCTL_LIMA_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_WAIT_FENCE, struct drm_lima_wait_fence)
-+#define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait)
-+#define DRM_IOCTL_LIMA_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_CTX, struct drm_lima_ctx)
-+#define DRM_IOCTL_LIMA_GEM_MOD DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_MOD, struct drm_lima_gem_mod)
-+
-+#if defined(__cplusplus)
-+}
-+#endif
-+
-+#endif /* __LIMA_DRM_H__ */
diff --git a/disabled/linux-5.0-rc8-fix-aquantia-ethernet.patch b/disabled/linux-5.0-rc8-fix-aquantia-ethernet.patch
deleted file mode 100644
index d0e3d74..0000000
--- a/disabled/linux-5.0-rc8-fix-aquantia-ethernet.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-diff -up linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c.omv~ linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
---- linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c.omv~	2019-02-27 00:42:53.540895184 +0100
-+++ linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c	2019-02-27 00:43:16.117266512 +0100
-@@ -275,6 +275,9 @@ static int hw_atl_b0_hw_offload_set(stru
- 
- static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)
- {
-+	/* Tx TC/Queue number config */
-+	hw_atl_rpb_tps_tx_tc_mode_set(self, 1U);
-+
- 	hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
- 	hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
- 	hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
-diff -up linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c.omv~ linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c
---- linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c.omv~	2019-02-27 00:43:25.767425197 +0100
-+++ linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c	2019-02-27 00:44:27.310436679 +0100
-@@ -1274,6 +1274,15 @@ void hw_atl_tpb_tx_buff_en_set(struct aq
- 			    HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en);
- }
- 
-+void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw,
-+                                   u32 tx_traf_class_mode)
-+{
-+	aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR,
-+			    HW_ATL_TPB_TX_TC_MODE_MSK,
-+			    HW_ATL_TPB_TX_TC_MODE_SHIFT,
-+			    tx_traf_class_mode);
-+}
-+
- void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
- 						u32 tx_buff_hi_threshold_per_tc,
- 					 u32 buffer)
-diff -up linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h.omv~ linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h
---- linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h.omv~	2019-02-27 00:44:40.135647360 +0100
-+++ linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h	2019-02-27 00:45:05.930070990 +0100
-@@ -605,6 +605,10 @@ void hw_atl_thm_lso_tcp_flag_of_middle_p
- 
- /* tpb */
- 
-+/* set TX Traffic Class Mode */
-+void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw,
-+				   u32 tx_traf_class_mode);
-+
- /* set tx buffer enable */
- void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en);
- 
-diff -up linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h.omv~ linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h
---- linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h.omv~	2019-02-27 00:45:18.159271784 +0100
-+++ linux-5.0-rc8/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h	2019-02-27 00:45:37.661591941 +0100
-@@ -1948,6 +1948,19 @@
- /* default value of bitfield tx_buf_en */
- #define HW_ATL_TPB_TX_BUF_EN_DEFAULT 0x0
- 
-+/* register address for bitfield tx_tc_mode */
-+#define HW_ATL_TPB_TX_TC_MODE_ADDR 0x00007900
-+/* bitmask for bitfield tx_tc_mode */
-+#define HW_ATL_TPB_TX_TC_MODE_MSK 0x00000100
-+/* inverted bitmask for bitfield tx_tc_mode */
-+#define HW_ATL_TPB_TX_TC_MODE_MSKN 0xFFFFFEFF
-+/* lower bit position of bitfield tx_tc_mode */
-+#define HW_ATL_TPB_TX_TC_MODE_SHIFT 8
-+/* width of bitfield tx_tc_mode */
-+#define HW_ATL_TPB_TX_TC_MODE_WIDTH 1
-+/* default value of bitfield tx_tc_mode */
-+#define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0
-+
- /* tx tx{b}_hi_thresh[c:0] bitfield definitions
-  * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]".
-  * parameter: buffer {b} | stride size 0x10 | range [0, 7]
diff --git a/disabled/pass-ldbfd-4.5.0-linux.patch b/disabled/pass-ldbfd-4.5.0-linux.patch
deleted file mode 100644
index 50e2faf..0000000
--- a/disabled/pass-ldbfd-4.5.0-linux.patch
+++ /dev/null
@@ -1,13 +0,0 @@
-diff --git a/arch/arm64/kernel/vdso/Makefile b/arch/arm64/kernel/vdso/Makefile
-index b467fd0..ecf6711 100644
---- a/arch/arm64/kernel/vdso/Makefile
-+++ b/arch/arm64/kernel/vdso/Makefile
-@@ -13,7 +13,7 @@ obj-vdso := $(addprefix $(obj)/, $(obj-vdso))
- 
- ccflags-y := -shared -fno-common -fno-builtin
- ccflags-y += -nostdlib -Wl,-soname=linux-vdso.so.1 \
--		$(call cc-ldoption, -Wl$(comma)--hash-style=sysv)
-+		$(call cc-ldoption, -Wl$(comma)--hash-style=sysv -fuse-ld=bfd)
- 
- # Disable gcov profiling for VDSO code
- GCOV_PROFILE := n
diff --git a/disabled/retpoline-fill_RSB_on_context_switch_for_affected_CPUs.patch b/disabled/retpoline-fill_RSB_on_context_switch_for_affected_CPUs.patch
deleted file mode 100644
index 8f402eb..0000000
--- a/disabled/retpoline-fill_RSB_on_context_switch_for_affected_CPUs.patch
+++ /dev/null
@@ -1,175 +0,0 @@
-From c995efd5a740d9cbafbf58bde4973e8b50b4d761 Mon Sep 17 00:00:00 2001
-From: David Woodhouse <dwmw@amazon.co.uk>
-Date: Fri, 12 Jan 2018 17:49:25 +0000
-Subject: x86/retpoline: Fill RSB on context switch for affected CPUs
-
-On context switch from a shallow call stack to a deeper one, as the CPU
-does 'ret' up the deeper side it may encounter RSB entries (predictions for
-where the 'ret' goes to) which were populated in userspace.
-
-This is problematic if neither SMEP nor KPTI (the latter of which marks
-userspace pages as NX for the kernel) are active, as malicious code in
-userspace may then be executed speculatively.
-
-Overwrite the CPU's return prediction stack with calls which are predicted
-to return to an infinite loop, to "capture" speculation if this
-happens. This is required both for retpoline, and also in conjunction with
-IBRS for !SMEP && !KPTI.
-
-On Skylake+ the problem is slightly different, and an *underflow* of the
-RSB may cause errant branch predictions to occur. So there it's not so much
-overwrite, as *filling* the RSB to attempt to prevent it getting
-empty. This is only a partial solution for Skylake+ since there are many
-other conditions which may result in the RSB becoming empty. The full
-solution on Skylake+ is to use IBRS, which will prevent the problem even
-when the RSB becomes empty. With IBRS, the RSB-stuffing will not be
-required on context switch.
-
-[ tglx: Added missing vendor check and slighty massaged comments and
-  	changelog ]
-
-Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
-Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-Acked-by: Arjan van de Ven <arjan@linux.intel.com>
-Cc: gnomes@lxorguk.ukuu.org.uk
-Cc: Rik van Riel <riel@redhat.com>
-Cc: Andi Kleen <ak@linux.intel.com>
-Cc: Josh Poimboeuf <jpoimboe@redhat.com>
-Cc: thomas.lendacky@amd.com
-Cc: Peter Zijlstra <peterz@infradead.org>
-Cc: Linus Torvalds <torvalds@linux-foundation.org>
-Cc: Jiri Kosina <jikos@kernel.org>
-Cc: Andy Lutomirski <luto@amacapital.net>
-Cc: Dave Hansen <dave.hansen@intel.com>
-Cc: Kees Cook <keescook@google.com>
-Cc: Tim Chen <tim.c.chen@linux.intel.com>
-Cc: Greg Kroah-Hartman <gregkh@linux-foundation.org>
-Cc: Paul Turner <pjt@google.com>
-Link: https://lkml.kernel.org/r/1515779365-9032-1-git-send-email-dwmw@amazon.co.uk
----
- arch/x86/entry/entry_32.S          | 11 +++++++++++
- arch/x86/entry/entry_64.S          | 11 +++++++++++
- arch/x86/include/asm/cpufeatures.h |  1 +
- arch/x86/kernel/cpu/bugs.c         | 36 ++++++++++++++++++++++++++++++++++++
- 4 files changed, 59 insertions(+)
-
-diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S
-index a1f28a5..60c4c34 100644
---- a/arch/x86/entry/entry_32.S
-+++ b/arch/x86/entry/entry_32.S
-@@ -244,6 +244,17 @@ ENTRY(__switch_to_asm)
- 	movl	%ebx, PER_CPU_VAR(stack_canary)+stack_canary_offset
- #endif
- 
-+#ifdef CONFIG_RETPOLINE
-+	/*
-+	 * When switching from a shallower to a deeper call stack
-+	 * the RSB may either underflow or use entries populated
-+	 * with userspace addresses. On CPUs where those concerns
-+	 * exist, overwrite the RSB with entries which capture
-+	 * speculative execution to prevent attack.
-+	 */
-+	FILL_RETURN_BUFFER %ebx, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
-+#endif
-+
- 	/* restore callee-saved registers */
- 	popl	%esi
- 	popl	%edi
-diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
-index 59874bc..d54a0ed 100644
---- a/arch/x86/entry/entry_64.S
-+++ b/arch/x86/entry/entry_64.S
-@@ -487,6 +487,17 @@ ENTRY(__switch_to_asm)
- 	movq	%rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset
- #endif
- 
-+#ifdef CONFIG_RETPOLINE
-+	/*
-+	 * When switching from a shallower to a deeper call stack
-+	 * the RSB may either underflow or use entries populated
-+	 * with userspace addresses. On CPUs where those concerns
-+	 * exist, overwrite the RSB with entries which capture
-+	 * speculative execution to prevent attack.
-+	 */
-+	FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
-+#endif
-+
- 	/* restore callee-saved registers */
- 	popq	%r15
- 	popq	%r14
-diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
-index f275447..aa09559 100644
---- a/arch/x86/include/asm/cpufeatures.h
-+++ b/arch/x86/include/asm/cpufeatures.h
-@@ -211,6 +211,7 @@
- #define X86_FEATURE_AVX512_4FMAPS	( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */
- 
- #define X86_FEATURE_MBA			( 7*32+18) /* Memory Bandwidth Allocation */
-+#define X86_FEATURE_RSB_CTXSW		( 7*32+19) /* Fill RSB on context switches */
- 
- /* Virtualization flags: Linux defined, word 8 */
- #define X86_FEATURE_TPR_SHADOW		( 8*32+ 0) /* Intel TPR Shadow */
-diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
-index e4dc261..390b3dc 100644
---- a/arch/x86/kernel/cpu/bugs.c
-+++ b/arch/x86/kernel/cpu/bugs.c
-@@ -23,6 +23,7 @@
- #include <asm/alternative.h>
- #include <asm/pgtable.h>
- #include <asm/set_memory.h>
-+#include <asm/intel-family.h>
- 
- static void __init spectre_v2_select_mitigation(void);
- 
-@@ -155,6 +156,23 @@ disable:
- 	return SPECTRE_V2_CMD_NONE;
- }
- 
-+/* Check for Skylake-like CPUs (for RSB handling) */
-+static bool __init is_skylake_era(void)
-+{
-+	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
-+	    boot_cpu_data.x86 == 6) {
-+		switch (boot_cpu_data.x86_model) {
-+		case INTEL_FAM6_SKYLAKE_MOBILE:
-+		case INTEL_FAM6_SKYLAKE_DESKTOP:
-+		case INTEL_FAM6_SKYLAKE_X:
-+		case INTEL_FAM6_KABYLAKE_MOBILE:
-+		case INTEL_FAM6_KABYLAKE_DESKTOP:
-+			return true;
-+		}
-+	}
-+	return false;
-+}
-+
- static void __init spectre_v2_select_mitigation(void)
- {
- 	enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
-@@ -213,6 +231,24 @@ retpoline_auto:
- 
- 	spectre_v2_enabled = mode;
- 	pr_info("%s\n", spectre_v2_strings[mode]);
-+
-+	/*
-+	 * If neither SMEP or KPTI are available, there is a risk of
-+	 * hitting userspace addresses in the RSB after a context switch
-+	 * from a shallow call stack to a deeper one. To prevent this fill
-+	 * the entire RSB, even when using IBRS.
-+	 *
-+	 * Skylake era CPUs have a separate issue with *underflow* of the
-+	 * RSB, when they will predict 'ret' targets from the generic BTB.
-+	 * The proper mitigation for this is IBRS. If IBRS is not supported
-+	 * or deactivated in favour of retpolines the RSB fill on context
-+	 * switch is required.
-+	 */
-+	if ((!boot_cpu_has(X86_FEATURE_PTI) &&
-+	     !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
-+		setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
-+		pr_info("Filling RSB on context switch\n");
-+	}
- }
- 
- #undef pr_fmt
--- 
-cgit v1.1
-
diff --git a/disabled/retpoline_add_LFENCE_to_the_retpoline_filling_RSB_macros.patch b/disabled/retpoline_add_LFENCE_to_the_retpoline_filling_RSB_macros.patch
deleted file mode 100644
index d930100..0000000
--- a/disabled/retpoline_add_LFENCE_to_the_retpoline_filling_RSB_macros.patch
+++ /dev/null
@@ -1,90 +0,0 @@
-From 28d437d550e1e39f805d99f9f8ac399c778827b7 Mon Sep 17 00:00:00 2001
-From: Tom Lendacky <thomas.lendacky@amd.com>
-Date: Sat, 13 Jan 2018 17:27:30 -0600
-Subject: x86/retpoline: Add LFENCE to the retpoline/RSB filling RSB macros
-
-The PAUSE instruction is currently used in the retpoline and RSB filling
-macros as a speculation trap.  The use of PAUSE was originally suggested
-because it showed a very, very small difference in the amount of
-cycles/time used to execute the retpoline as compared to LFENCE.  On AMD,
-the PAUSE instruction is not a serializing instruction, so the pause/jmp
-loop will use excess power as it is speculated over waiting for return
-to mispredict to the correct target.
-
-The RSB filling macro is applicable to AMD, and, if software is unable to
-verify that LFENCE is serializing on AMD (possible when running under a
-hypervisor), the generic retpoline support will be used and, so, is also
-applicable to AMD.  Keep the current usage of PAUSE for Intel, but add an
-LFENCE instruction to the speculation trap for AMD.
-
-The same sequence has been adopted by GCC for the GCC generated retpolines.
-
-Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
-Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-Reviewed-by: Borislav Petkov <bp@alien8.de>
-Acked-by: David Woodhouse <dwmw@amazon.co.uk>
-Acked-by: Arjan van de Ven <arjan@linux.intel.com>
-Cc: Rik van Riel <riel@redhat.com>
-Cc: Andi Kleen <ak@linux.intel.com>
-Cc: Paul Turner <pjt@google.com>
-Cc: Peter Zijlstra <peterz@infradead.org>
-Cc: Tim Chen <tim.c.chen@linux.intel.com>
-Cc: Jiri Kosina <jikos@kernel.org>
-Cc: Dave Hansen <dave.hansen@intel.com>
-Cc: Andy Lutomirski <luto@kernel.org>
-Cc: Josh Poimboeuf <jpoimboe@redhat.com>
-Cc: Dan Williams <dan.j.williams@intel.com>
-Cc: Linus Torvalds <torvalds@linux-foundation.org>
-Cc: Greg Kroah-Hartman <gregkh@linux-foundation.org>
-Cc: Kees Cook <keescook@google.com>
-Link: https://lkml.kernel.org/r/20180113232730.31060.36287.stgit@tlendack-t1.amdoffice.net
----
- arch/x86/include/asm/nospec-branch.h | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h
-index 402a11c..7b45d84 100644
---- a/arch/x86/include/asm/nospec-branch.h
-+++ b/arch/x86/include/asm/nospec-branch.h
-@@ -11,7 +11,7 @@
-  * Fill the CPU return stack buffer.
-  *
-  * Each entry in the RSB, if used for a speculative 'ret', contains an
-- * infinite 'pause; jmp' loop to capture speculative execution.
-+ * infinite 'pause; lfence; jmp' loop to capture speculative execution.
-  *
-  * This is required in various cases for retpoline and IBRS-based
-  * mitigations for the Spectre variant 2 vulnerability. Sometimes to
-@@ -38,11 +38,13 @@
- 	call	772f;				\
- 773:	/* speculation trap */			\
- 	pause;					\
-+	lfence;					\
- 	jmp	773b;				\
- 772:						\
- 	call	774f;				\
- 775:	/* speculation trap */			\
- 	pause;					\
-+	lfence;					\
- 	jmp	775b;				\
- 774:						\
- 	dec	reg;				\
-@@ -73,6 +75,7 @@
- 	call	.Ldo_rop_\@
- .Lspec_trap_\@:
- 	pause
-+	lfence
- 	jmp	.Lspec_trap_\@
- .Ldo_rop_\@:
- 	mov	\reg, (%_ASM_SP)
-@@ -165,6 +168,7 @@
- 	"       .align 16\n"					\
- 	"901:	call   903f;\n"					\
- 	"902:	pause;\n"					\
-+	"    	lfence;\n"					\
- 	"       jmp    902b;\n"					\
- 	"       .align 16\n"					\
- 	"903:	addl   $4, %%esp;\n"				\
--- 
-cgit v1.1
-
diff --git a/disabled/vbox-modules-5.0.patch b/disabled/vbox-modules-5.0.patch
deleted file mode 100644
index 6281fce..0000000
--- a/disabled/vbox-modules-5.0.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-diff -up linux-5.0-rc2/drivers/virt/vboxdrv/r0drv/linux/memuserkernel-r0drv-linux.c.omv~ linux-5.0-rc2/drivers/virt/vboxdrv/r0drv/linux/memuserkernel-r0drv-linux.c
---- linux-5.0-rc2/drivers/virt/vboxdrv/r0drv/linux/memuserkernel-r0drv-linux.c.omv~	2019-01-14 04:09:04.040288864 +0100
-+++ linux-5.0-rc2/drivers/virt/vboxdrv/r0drv/linux/memuserkernel-r0drv-linux.c	2019-01-14 04:11:20.071678928 +0100
-@@ -66,7 +66,7 @@ RT_EXPORT_SYMBOL(RTR0MemUserCopyTo);
- RTR0DECL(bool) RTR0MemUserIsValidAddr(RTR3PTR R3Ptr)
- {
-     IPRT_LINUX_SAVE_EFL_AC();
--    bool fRc = access_ok(VERIFY_READ, (void *)R3Ptr);
-+    bool fRc = access_ok((void *)R3Ptr, sizeof(R3Ptr));
-     IPRT_LINUX_RESTORE_EFL_AC();
-     return fRc;
- }
-diff -up linux-5.0-rc2/fs/vboxsf/super.c.omv~ linux-5.0-rc2/fs/vboxsf/super.c
---- linux-5.0-rc2/fs/vboxsf/super.c.omv~	2019-01-14 04:11:57.486326225 +0100
-+++ linux-5.0-rc2/fs/vboxsf/super.c	2019-01-14 04:12:26.646828086 +0100
-@@ -12,6 +12,7 @@
- 
- #include <linux/magic.h>
- #include <linux/module.h>
-+#include <uapi/linux/mount.h>
- #include <linux/nls.h>
- #include <linux/parser.h>
- #include <linux/statfs.h>
diff --git a/disabled/virtualbox-kernel-5.3.patch b/disabled/virtualbox-kernel-5.3.patch
deleted file mode 100644
index bf90473..0000000
--- a/disabled/virtualbox-kernel-5.3.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-diff -up linux-5.3/drivers/net/vboxnetflt/linux/VBoxNetFlt-linux.c.omv~ linux-5.3/drivers/net/vboxnetflt/linux/VBoxNetFlt-linux.c
---- linux-5.3/drivers/net/vboxnetflt/linux/VBoxNetFlt-linux.c.omv~	2019-09-16 21:17:58.193558616 +0200
-+++ linux-5.3/drivers/net/vboxnetflt/linux/VBoxNetFlt-linux.c	2019-09-16 21:46:25.574504611 +0200
-@@ -2106,6 +2106,7 @@ static int vboxNetFltLinuxEnumeratorCall
-     struct net_device *dev  = VBOX_NETDEV_NOTIFIER_INFO_TO_DEV(ptr);
-     struct in_device *in_dev;
-     struct inet6_dev *in6_dev;
-+    const struct in_ifaddr *ifa;
- 
-     if (ulEventType != NETDEV_REGISTER)
-         return NOTIFY_OK;
-@@ -2123,7 +2124,7 @@ static int vboxNetFltLinuxEnumeratorCall
- #endif
-     if (in_dev != NULL)
-     {
--        for_ifa(in_dev) {
-+        in_dev_for_each_ifa_rcu(ifa, in_dev) {
-             if (VBOX_IPV4_IS_LOOPBACK(ifa->ifa_address))
-                 return NOTIFY_OK;
- 
-@@ -2137,7 +2138,7 @@ static int vboxNetFltLinuxEnumeratorCall
- 
-             pThis->pSwitchPort->pfnNotifyHostAddress(pThis->pSwitchPort,
-                 /* :fAdded */ true, kIntNetAddrType_IPv4, &ifa->ifa_address);
--        } endfor_ifa(in_dev);
-+        }
-     }
- 
-     /*
-diff -up linux-5.3/drivers/virt/vboxdrv/r0drv/linux/mp-r0drv-linux.c.omv~ linux-5.3/drivers/virt/vboxdrv/r0drv/linux/mp-r0drv-linux.c
---- linux-5.3/drivers/virt/vboxdrv/r0drv/linux/mp-r0drv-linux.c.omv~	2019-09-16 21:44:46.283687150 +0200
-+++ linux-5.3/drivers/virt/vboxdrv/r0drv/linux/mp-r0drv-linux.c	2019-09-16 21:45:20.384699043 +0200
-@@ -284,11 +284,10 @@ RTDECL(int) RTMpOnAll(PFNRTMPWORKER pfnW
-     {
-         /* Fire the function on all other CPUs without waiting for completion. */
- # if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
--        int rc = smp_call_function(rtmpLinuxAllWrapper, &Args, 0 /* wait */);
-+        smp_call_function(rtmpLinuxAllWrapper, &Args, 0 /* wait */);
- # else
-         int rc = smp_call_function(rtmpLinuxAllWrapper, &Args, 0 /* retry */, 0 /* wait */);
- # endif
--        Assert(!rc); NOREF(rc);
-     }
- #endif
- 
-@@ -338,13 +337,12 @@ RTDECL(int) RTMpOnOthers(PFNRTMPWORKER p
- 
-     RTThreadPreemptDisable(&PreemptState);
- # if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
--    rc = smp_call_function(rtmpLinuxWrapper, &Args, 1 /* wait */);
-+    smp_call_function(rtmpLinuxWrapper, &Args, 1 /* wait */);
- # else /* older kernels */
--    rc = smp_call_function(rtmpLinuxWrapper, &Args, 0 /* retry */, 1 /* wait */);
-+    smp_call_function(rtmpLinuxWrapper, &Args, 0 /* retry */, 1 /* wait */);
- # endif /* older kernels */
-     RTThreadPreemptRestore(&PreemptState);
- 
--    Assert(rc == 0); NOREF(rc);
-     IPRT_LINUX_RESTORE_EFL_AC();
- #else
-     RT_NOREF(pfnWorker, pvUser1, pvUser2);
diff --git a/dont-disable-rdseed.patch b/dont-disable-rdseed.patch
new file mode 100644
index 0000000..bd1b646
--- /dev/null
+++ b/dont-disable-rdseed.patch
@@ -0,0 +1,16 @@
+diff -up linux-6.19-rc7/arch/x86/kernel/cpu/amd.c.omv~ linux-6.19-rc7/arch/x86/kernel/cpu/amd.c
+--- linux-6.19-rc7/arch/x86/kernel/cpu/amd.c.omv~	2026-01-30 02:05:08.858869357 +0100
++++ linux-6.19-rc7/arch/x86/kernel/cpu/amd.c	2026-01-30 02:06:11.445042277 +0100
+@@ -1051,9 +1051,9 @@ static const struct x86_cpu_id zen5_rdse
+ static void init_amd_zen5(struct cpuinfo_x86 *c)
+ {
+ 	if (!x86_match_min_microcode_rev(zen5_rdseed_microcode)) {
+-		clear_cpu_cap(c, X86_FEATURE_RDSEED);
+-		msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18);
+-		pr_emerg_once("RDSEED32 is broken. Disabling the corresponding CPUID bit.\n");
++/*		clear_cpu_cap(c, X86_FEATURE_RDSEED);
++		msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18); */
++		pr_emerg_once("RDSEED32 is broken. This may result in unsafe crypto. Update your BIOS ASAP!\n");
+ 	}
+ }
+ 
diff --git a/e0c5c98b4558d336ecb6b5a3c174816b4ed41db2.patch b/e0c5c98b4558d336ecb6b5a3c174816b4ed41db2.patch
new file mode 100644
index 0000000..45db6c7
--- /dev/null
+++ b/e0c5c98b4558d336ecb6b5a3c174816b4ed41db2.patch
@@ -0,0 +1,870 @@
+From e0c5c98b4558d336ecb6b5a3c174816b4ed41db2 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andyshrk@gmail.com>
+Date: Mon, 31 Oct 2022 11:36:07 +0800
+Subject: [PATCH] arm64: rockchip: Add rockchip_defconfig
+
+Signed-off-by: Andy Yan <andyshrk@gmail.com>
+---
+ arch/arm64/configs/rockchip_defconfig | 853 ++++++++++++++++++++++++++
+ 1 file changed, 853 insertions(+)
+ create mode 100644 arch/arm64/configs/rockchip_defconfig
+
+diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig
+new file mode 100644
+index 00000000000000..739fb1eef862cc
+--- /dev/null
++++ b/arch/arm64/configs/rockchip_defconfig
+@@ -0,0 +1,853 @@
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_AUDIT=y
++CONFIG_NO_HZ_IDLE=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_BPF_JIT=y
++CONFIG_PREEMPT=y
++CONFIG_IRQ_TIME_ACCOUNTING=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_NUMA_BALANCING=y
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CGROUP_HUGETLB=y
++CONFIG_CPUSETS=y
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_CGROUP_PERF=y
++CONFIG_CGROUP_BPF=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_KALLSYMS_ALL=y
++CONFIG_PROFILING=y
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_ARM64_VA_BITS_48=y
++CONFIG_SCHED_MC=y
++CONFIG_SCHED_SMT=y
++CONFIG_NUMA=y
++CONFIG_KEXEC=y
++CONFIG_KEXEC_FILE=y
++CONFIG_CRASH_DUMP=y
++CONFIG_XEN=y
++CONFIG_COMPAT=y
++CONFIG_RANDOMIZE_BASE=y
++CONFIG_HIBERNATION=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_ENERGY_MODEL=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=m
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
++CONFIG_CPUFREQ_DT=y
++CONFIG_ACPI_CPPC_CPUFREQ=m
++CONFIG_ARM_SCPI_CPUFREQ=y
++CONFIG_ARM_SCMI_CPUFREQ=y
++CONFIG_ACPI=y
++CONFIG_ACPI_HOTPLUG_MEMORY=y
++CONFIG_ACPI_HMAT=y
++CONFIG_ACPI_APEI=y
++CONFIG_ACPI_APEI_GHES=y
++CONFIG_ACPI_APEI_PCIEAER=y
++CONFIG_ACPI_APEI_MEMORY_FAILURE=y
++CONFIG_ACPI_APEI_EINJ=y
++CONFIG_VIRTUALIZATION=y
++CONFIG_KVM=y
++CONFIG_JUMP_LABEL=y
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++# CONFIG_COMPAT_BRK is not set
++CONFIG_MEMORY_HOTPLUG=y
++CONFIG_MEMORY_HOTREMOVE=y
++CONFIG_KSM=y
++CONFIG_MEMORY_FAILURE=y
++CONFIG_TRANSPARENT_HUGEPAGE=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++CONFIG_IPV6=m
++CONFIG_NETFILTER=y
++CONFIG_BRIDGE_NETFILTER=m
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_EVENTS=y
++CONFIG_NETFILTER_XT_MARK=m
++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
++CONFIG_NETFILTER_XT_TARGET_LOG=m
++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
++CONFIG_NETFILTER_XT_MATCH_IPVS=m
++CONFIG_IP_VS=m
++CONFIG_IP_NF_IPTABLES=m
++CONFIG_IP_NF_FILTER=m
++CONFIG_IP_NF_TARGET_REJECT=m
++CONFIG_IP_NF_NAT=m
++CONFIG_IP_NF_TARGET_MASQUERADE=m
++CONFIG_IP_NF_MANGLE=m
++CONFIG_IP6_NF_IPTABLES=m
++CONFIG_IP6_NF_FILTER=m
++CONFIG_IP6_NF_TARGET_REJECT=m
++CONFIG_IP6_NF_MANGLE=m
++CONFIG_IP6_NF_NAT=m
++CONFIG_IP6_NF_TARGET_MASQUERADE=m
++CONFIG_BRIDGE=m
++CONFIG_BRIDGE_VLAN_FILTERING=y
++CONFIG_NET_DSA=m
++CONFIG_NET_DSA_TAG_OCELOT=m
++CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
++CONFIG_VLAN_8021Q=m
++CONFIG_VLAN_8021Q_GVRP=y
++CONFIG_VLAN_8021Q_MVRP=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_CBS=m
++CONFIG_NET_SCH_ETF=m
++CONFIG_NET_SCH_TAPRIO=m
++CONFIG_NET_SCH_MQPRIO=m
++CONFIG_NET_SCH_INGRESS=m
++CONFIG_NET_CLS_BASIC=m
++CONFIG_NET_CLS_FLOWER=m
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_GACT=m
++CONFIG_NET_ACT_MIRRED=m
++CONFIG_NET_ACT_GATE=m
++CONFIG_QRTR_SMD=m
++CONFIG_QRTR_TUN=m
++CONFIG_CAN=m
++CONFIG_BT=m
++CONFIG_BT_HIDP=m
++# CONFIG_BT_LE is not set
++CONFIG_BT_LEDS=y
++# CONFIG_BT_DEBUGFS is not set
++CONFIG_BT_HCIBTUSB=m
++CONFIG_BT_HCIUART=m
++CONFIG_BT_HCIUART_LL=y
++CONFIG_BT_HCIUART_BCM=y
++CONFIG_BT_HCIUART_QCA=y
++CONFIG_BT_HCIUART_MRVL=y
++CONFIG_BT_MRVL=m
++CONFIG_BT_MRVL_SDIO=m
++CONFIG_CFG80211=m
++CONFIG_MAC80211=m
++CONFIG_MAC80211_LEDS=y
++CONFIG_RFKILL=m
++CONFIG_NET_9P=y
++CONFIG_NET_9P_VIRTIO=y
++CONFIG_NFC=m
++CONFIG_NFC_NCI=m
++CONFIG_NFC_S3FWRN5_I2C=m
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_PCI=y
++CONFIG_PCIEPORTBUS=y
++CONFIG_PCIEAER=y
++CONFIG_PCI_IOV=y
++CONFIG_PCI_PASID=y
++CONFIG_HOTPLUG_PCI=y
++CONFIG_HOTPLUG_PCI_ACPI=y
++CONFIG_PCI_HOST_GENERIC=y
++CONFIG_PCI_XGENE=y
++CONFIG_PCIE_ALTERA=y
++CONFIG_PCIE_ALTERA_MSI=y
++CONFIG_PCI_HOST_THUNDER_PEM=y
++CONFIG_PCI_HOST_THUNDER_ECAM=y
++CONFIG_PCIE_ROCKCHIP_HOST=m
++CONFIG_PCI_HISI=y
++CONFIG_PCIE_KIRIN=y
++CONFIG_PCI_MESON=m
++CONFIG_PCI_ENDPOINT=y
++CONFIG_PCI_ENDPOINT_CONFIGFS=y
++CONFIG_PCI_EPF_TEST=m
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_FW_LOADER_USER_HELPER=y
++CONFIG_BRCMSTB_GISB_ARB=y
++CONFIG_VEXPRESS_CONFIG=y
++CONFIG_ARM_SCMI_PROTOCOL=y
++CONFIG_ARM_SCPI_PROTOCOL=y
++CONFIG_EFI_CAPSULE_LOADER=y
++CONFIG_GNSS=m
++CONFIG_GNSS_MTK_SERIAL=m
++CONFIG_MTD=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_CFI=y
++CONFIG_MTD_CFI_ADV_OPTIONS=y
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++CONFIG_MTD_CFI_STAA=y
++CONFIG_MTD_PHYSMAP=y
++CONFIG_MTD_PHYSMAP_OF=y
++CONFIG_MTD_DATAFLASH=y
++CONFIG_MTD_SST25L=y
++CONFIG_MTD_RAW_NAND=y
++CONFIG_MTD_NAND_DENALI_DT=y
++CONFIG_MTD_NAND_BRCMNAND=m
++CONFIG_MTD_NAND_BRCMNAND_BCMBCA=m
++CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=m
++CONFIG_MTD_NAND_BRCMNAND_IPROC=m
++CONFIG_MTD_SPI_NOR=y
++CONFIG_OF_OVERLAY=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_NBD=m
++CONFIG_VIRTIO_BLK=y
++CONFIG_BLK_DEV_NVME=m
++CONFIG_SRAM=y
++CONFIG_PCI_ENDPOINT_TEST=m
++CONFIG_EEPROM_AT24=m
++CONFIG_EEPROM_AT25=m
++CONFIG_UACCE=m
++# CONFIG_SCSI_PROC_FS is not set
++CONFIG_BLK_DEV_SD=y
++CONFIG_SCSI_SAS_ATA=y
++CONFIG_SCSI_HISI_SAS=y
++CONFIG_SCSI_HISI_SAS_PCI=y
++CONFIG_MEGARAID_SAS=y
++CONFIG_SCSI_MPT3SAS=m
++CONFIG_ATA=y
++CONFIG_SATA_AHCI=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_CEVA=y
++CONFIG_AHCI_XGENE=y
++CONFIG_AHCI_QORIQ=y
++CONFIG_SATA_SIL24=y
++CONFIG_PATA_OF_PLATFORM=y
++CONFIG_MD=y
++CONFIG_BLK_DEV_MD=m
++CONFIG_BLK_DEV_DM=m
++CONFIG_DM_MIRROR=m
++CONFIG_DM_ZERO=m
++CONFIG_NETDEVICES=y
++CONFIG_MACVLAN=m
++CONFIG_MACVTAP=m
++CONFIG_TUN=y
++CONFIG_VETH=m
++CONFIG_VIRTIO_NET=y
++CONFIG_B53_SRAB_DRIVER=m
++CONFIG_NET_DSA_BCM_SF2=m
++CONFIG_AMD_XGBE=y
++CONFIG_ATL1C=m
++CONFIG_BCMGENET=m
++CONFIG_BNX2X=m
++CONFIG_SYSTEMPORT=m
++CONFIG_MACB=y
++CONFIG_THUNDER_NIC_PF=y
++CONFIG_HIX5HD2_GMAC=y
++CONFIG_HNS_DSAF=y
++CONFIG_HNS_ENET=y
++CONFIG_HNS3=y
++CONFIG_HNS3_HCLGE=y
++CONFIG_HNS3_ENET=y
++CONFIG_E1000=y
++CONFIG_E1000E=y
++CONFIG_IGB=y
++CONFIG_IGBVF=y
++CONFIG_MVMDIO=y
++CONFIG_SKY2=y
++CONFIG_MLX4_EN=m
++CONFIG_MLX5_CORE=m
++CONFIG_MLX5_CORE_EN=y
++CONFIG_QCOM_EMAC=m
++CONFIG_RMNET=m
++CONFIG_R8169=m
++CONFIG_SMC91X=y
++CONFIG_SMSC911X=y
++CONFIG_STMMAC_ETH=y
++CONFIG_AQUANTIA_PHY=y
++CONFIG_BROADCOM_PHY=m
++CONFIG_BCM54140_PHY=m
++CONFIG_MARVELL_PHY=m
++CONFIG_MARVELL_10G_PHY=m
++CONFIG_MICREL_PHY=y
++CONFIG_MICROSEMI_PHY=y
++CONFIG_AT803X_PHY=y
++CONFIG_REALTEK_PHY=y
++CONFIG_ROCKCHIP_PHY=y
++CONFIG_DP83867_PHY=y
++CONFIG_VITESSE_PHY=y
++CONFIG_CAN_FLEXCAN=m
++CONFIG_CAN_MCP251XFD=m
++CONFIG_MDIO_BITBANG=y
++CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
++CONFIG_MDIO_BUS_MUX_MMIOREG=y
++CONFIG_USB_PEGASUS=m
++CONFIG_USB_RTL8150=m
++CONFIG_USB_RTL8152=m
++CONFIG_USB_LAN78XX=m
++CONFIG_USB_USBNET=m
++CONFIG_USB_NET_DM9601=m
++CONFIG_USB_NET_SR9800=m
++CONFIG_USB_NET_SMSC75XX=m
++CONFIG_USB_NET_SMSC95XX=m
++CONFIG_USB_NET_PLUSB=m
++CONFIG_USB_NET_MCS7830=m
++CONFIG_ATH10K=m
++CONFIG_ATH10K_PCI=m
++CONFIG_WCN36XX=m
++CONFIG_ATH11K=m
++CONFIG_ATH11K_AHB=m
++CONFIG_ATH11K_PCI=m
++CONFIG_BRCMFMAC=m
++CONFIG_MWIFIEX=m
++CONFIG_MWIFIEX_SDIO=m
++CONFIG_MWIFIEX_PCIE=m
++CONFIG_WL18XX=m
++CONFIG_WLCORE_SDIO=m
++CONFIG_INPUT_EVDEV=y
++CONFIG_KEYBOARD_ADC=m
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_CROS_EC=y
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_ATMEL_MXT=m
++CONFIG_TOUCHSCREEN_GOODIX=m
++CONFIG_TOUCHSCREEN_EDT_FT5X06=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_PWM_BEEPER=m
++CONFIG_INPUT_PWM_VIBRA=m
++# CONFIG_SERIO_SERPORT is not set
++CONFIG_SERIO_AMBAKMI=y
++CONFIG_LEGACY_PTY_COUNT=16
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_SERIAL_XILINX_PS_UART=y
++CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
++CONFIG_SERIAL_FSL_LPUART=y
++CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
++CONFIG_SERIAL_FSL_LINFLEXUART=y
++CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
++CONFIG_SERIAL_DEV_BUS=y
++CONFIG_VIRTIO_CONSOLE=y
++CONFIG_IPMI_HANDLER=m
++CONFIG_IPMI_DEVICE_INTERFACE=m
++CONFIG_IPMI_SI=m
++CONFIG_TCG_TPM=y
++CONFIG_TCG_TIS_I2C_INFINEON=y
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_MUX_PCA954x=y
++CONFIG_I2C_CADENCE=m
++CONFIG_I2C_DESIGNWARE_PLATFORM=y
++CONFIG_I2C_GPIO=m
++CONFIG_I2C_RK3X=y
++CONFIG_I2C_CROS_EC_TUNNEL=y
++CONFIG_I2C_SLAVE=y
++CONFIG_SPI=y
++CONFIG_SPI_CADENCE_QUADSPI=y
++CONFIG_SPI_DESIGNWARE=m
++CONFIG_SPI_DW_DMA=y
++CONFIG_SPI_DW_MMIO=m
++CONFIG_SPI_NXP_FLEXSPI=y
++CONFIG_SPI_PL022=y
++CONFIG_SPI_ROCKCHIP=y
++CONFIG_SPI_SPIDEV=m
++CONFIG_SPMI=y
++CONFIG_PINCTRL_MAX77620=y
++CONFIG_PINCTRL_SINGLE=y
++CONFIG_GPIO_ALTERA=m
++CONFIG_GPIO_DWAPB=y
++CONFIG_GPIO_MB86S7X=y
++CONFIG_GPIO_PL061=y
++CONFIG_GPIO_WCD934X=m
++CONFIG_GPIO_XGENE=y
++CONFIG_GPIO_MAX732X=y
++CONFIG_GPIO_PCA953X=y
++CONFIG_GPIO_PCA953X_IRQ=y
++CONFIG_GPIO_BD9571MWV=m
++CONFIG_GPIO_MAX77620=y
++CONFIG_POWER_RESET_BRCMSTB=y
++CONFIG_POWER_RESET_XGENE=y
++CONFIG_POWER_RESET_SYSCON=y
++CONFIG_SYSCON_REBOOT_MODE=y
++CONFIG_BATTERY_SBS=m
++CONFIG_BATTERY_BQ27XXX=y
++CONFIG_BATTERY_MAX17042=m
++CONFIG_CHARGER_MT6360=m
++CONFIG_CHARGER_BQ25890=m
++CONFIG_CHARGER_BQ25980=m
++CONFIG_SENSORS_ARM_SCMI=y
++CONFIG_SENSORS_ARM_SCPI=y
++CONFIG_SENSORS_GPIO_FAN=m
++CONFIG_SENSORS_JC42=m
++CONFIG_SENSORS_LM75=m
++CONFIG_SENSORS_LM90=m
++CONFIG_SENSORS_PWM_FAN=m
++CONFIG_SENSORS_INA2XX=m
++CONFIG_SENSORS_INA3221=m
++CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
++CONFIG_CPU_THERMAL=y
++CONFIG_DEVFREQ_THERMAL=y
++CONFIG_THERMAL_EMULATION=y
++CONFIG_ROCKCHIP_THERMAL=m
++CONFIG_WATCHDOG=y
++CONFIG_ARM_SP805_WATCHDOG=y
++CONFIG_ARM_SBSA_WATCHDOG=y
++CONFIG_DW_WATCHDOG=y
++CONFIG_ARM_SMC_WATCHDOG=y
++CONFIG_MFD_BD9571MWV=y
++CONFIG_MFD_AXP20X_I2C=y
++CONFIG_MFD_HI6421_PMIC=y
++CONFIG_MFD_MAX77620=y
++CONFIG_MFD_MT6360=y
++CONFIG_MFD_MT6397=y
++CONFIG_MFD_RK808=y
++CONFIG_MFD_SEC_CORE=y
++CONFIG_MFD_WM8994=m
++CONFIG_MFD_ROHM_BD718XX=y
++CONFIG_MFD_WCD934X=m
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_BD718XX=y
++CONFIG_REGULATOR_BD9571MWV=y
++CONFIG_REGULATOR_FAN53555=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_HI6421V530=y
++CONFIG_REGULATOR_MAX77620=y
++CONFIG_REGULATOR_MAX8973=y
++CONFIG_REGULATOR_MP8859=y
++CONFIG_REGULATOR_MT6358=y
++CONFIG_REGULATOR_MT6359=y
++CONFIG_REGULATOR_MT6360=y
++CONFIG_REGULATOR_MT6397=y
++CONFIG_REGULATOR_PCA9450=y
++CONFIG_REGULATOR_PF8X00=y
++CONFIG_REGULATOR_PFUZE100=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_REGULATOR_QCOM_SPMI=y
++CONFIG_REGULATOR_RK808=y
++CONFIG_REGULATOR_S2MPS11=y
++CONFIG_REGULATOR_TPS65132=m
++CONFIG_REGULATOR_VCTRL=m
++CONFIG_RC_CORE=m
++CONFIG_RC_DECODERS=y
++CONFIG_RC_DEVICES=y
++CONFIG_MEDIA_SUPPORT=m
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
++CONFIG_MEDIA_SDR_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++# CONFIG_DVB_NET is not set
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_SDR_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_HANTRO=m
++CONFIG_VIDEO_IMX219=m
++CONFIG_VIDEO_OV5640=m
++CONFIG_VIDEO_OV5645=m
++CONFIG_DRM=y
++CONFIG_DRM_I2C_NXP_TDA998X=m
++CONFIG_DRM_HDLCD=m
++CONFIG_DRM_MALI_DISPLAY=m
++CONFIG_DRM_KOMEDA=m
++CONFIG_DRM_NOUVEAU=m
++CONFIG_DRM_ROCKCHIP=y
++# CONFIG_ROCKCHIP_VOP is not set
++CONFIG_ROCKCHIP_VOP2=y
++CONFIG_ROCKCHIP_CDN_DP=y
++CONFIG_ROCKCHIP_DW_HDMI=y
++CONFIG_ROCKCHIP_DW_MIPI_DSI=y
++CONFIG_ROCKCHIP_INNO_HDMI=y
++CONFIG_ROCKCHIP_LVDS=y
++CONFIG_DRM_RCAR_DW_HDMI=m
++CONFIG_DRM_RCAR_USE_LVDS=y
++CONFIG_DRM_RCAR_MIPI_DSI=m
++CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
++CONFIG_DRM_PANEL_LVDS=m
++CONFIG_DRM_PANEL_SIMPLE=m
++CONFIG_DRM_PANEL_EDP=m
++CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
++CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
++CONFIG_DRM_PANEL_SITRONIX_ST7703=m
++CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
++CONFIG_DRM_DISPLAY_CONNECTOR=m
++CONFIG_DRM_LONTIUM_LT8912B=m
++CONFIG_DRM_LONTIUM_LT9611=m
++CONFIG_DRM_LONTIUM_LT9611UXC=m
++CONFIG_DRM_NWL_MIPI_DSI=m
++CONFIG_DRM_PARADE_PS8640=m
++CONFIG_DRM_SII902X=m
++CONFIG_DRM_SIMPLE_BRIDGE=m
++CONFIG_DRM_THINE_THC63LVD1024=m
++CONFIG_DRM_TI_SN65DSI86=m
++CONFIG_DRM_I2C_ADV7511=m
++CONFIG_DRM_I2C_ADV7511_AUDIO=y
++CONFIG_DRM_CDNS_MHDP8546=m
++CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
++CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
++CONFIG_DRM_DW_HDMI_CEC=m
++CONFIG_DRM_ETNAVIV=m
++CONFIG_DRM_HISI_HIBMC=m
++CONFIG_DRM_HISI_KIRIN=m
++CONFIG_DRM_MXSFB=m
++CONFIG_DRM_PL111=m
++CONFIG_DRM_LIMA=m
++CONFIG_DRM_PANFROST=y
++CONFIG_DRM_TIDSS=m
++CONFIG_FB=y
++CONFIG_FB_MODE_HELPERS=y
++CONFIG_FB_EFI=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=m
++CONFIG_BACKLIGHT_LP855X=m
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_DYNAMIC_MINORS=y
++CONFIG_SND_SOC=y
++CONFIG_SND_SOC_FSL_ASRC=m
++CONFIG_SND_SOC_FSL_SAI=m
++CONFIG_SND_SOC_FSL_AUDMIX=m
++CONFIG_SND_SOC_FSL_SSI=m
++CONFIG_SND_SOC_FSL_SPDIF=m
++CONFIG_SND_SOC_FSL_ESAI=m
++CONFIG_SND_SOC_FSL_MICFIL=m
++CONFIG_SND_SOC_FSL_EASRC=m
++CONFIG_SND_SOC_IMX_AUDMUX=m
++CONFIG_SND_SOC_ROCKCHIP=m
++CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
++CONFIG_SND_SOC_ROCKCHIP_RT5645=m
++CONFIG_SND_SOC_RK3399_GRU_SOUND=m
++CONFIG_SND_SOC_ADAU7002=m
++CONFIG_SND_SOC_AK4613=m
++CONFIG_SND_SOC_CROS_EC_CODEC=m
++CONFIG_SND_SOC_ES7134=m
++CONFIG_SND_SOC_ES7241=m
++CONFIG_SND_SOC_GTM601=m
++CONFIG_SND_SOC_MAX98927=m
++CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
++CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
++CONFIG_SND_SOC_PCM3168A_I2C=m
++CONFIG_SND_SOC_RT5659=m
++CONFIG_SND_SOC_SGTL5000=m
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
++CONFIG_SND_SOC_SIMPLE_MUX=m
++CONFIG_SND_SOC_SPDIF=m
++CONFIG_SND_SOC_TAS571X=m
++CONFIG_SND_SOC_TLV320AIC31XX=m
++CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
++CONFIG_SND_SOC_WCD9335=m
++CONFIG_SND_SOC_WCD934X=m
++CONFIG_SND_SOC_WCD938X_SDW=m
++CONFIG_SND_SOC_WM8524=m
++CONFIG_SND_SOC_WM8904=m
++CONFIG_SND_SOC_WM8960=m
++CONFIG_SND_SOC_WM8962=m
++CONFIG_SND_SOC_WM8978=m
++CONFIG_SND_SOC_WSA881X=m
++CONFIG_SND_SOC_NAU8822=m
++CONFIG_SND_SOC_LPASS_WSA_MACRO=m
++CONFIG_SND_SOC_LPASS_VA_MACRO=m
++CONFIG_SND_SOC_LPASS_RX_MACRO=m
++CONFIG_SND_SOC_LPASS_TX_MACRO=m
++CONFIG_SND_SIMPLE_CARD=m
++CONFIG_SND_AUDIO_GRAPH_CARD=m
++CONFIG_SND_AUDIO_GRAPH_CARD2=m
++CONFIG_HID_MULTITOUCH=m
++CONFIG_I2C_HID_ACPI=m
++CONFIG_I2C_HID_OF=m
++CONFIG_USB_CONN_GPIO=y
++CONFIG_USB=y
++CONFIG_USB_OTG=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PCI_RENESAS=m
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_HCD_PLATFORM=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_HCD_PLATFORM=y
++CONFIG_USB_ACM=m
++CONFIG_USB_STORAGE=y
++CONFIG_USB_CDNS_SUPPORT=m
++CONFIG_USB_CDNS3=m
++CONFIG_USB_CDNS3_GADGET=y
++CONFIG_USB_CDNS3_HOST=y
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_DWC3=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_CHIPIDEA=y
++CONFIG_USB_CHIPIDEA_UDC=y
++CONFIG_USB_CHIPIDEA_HOST=y
++CONFIG_USB_ISP1760=y
++CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_CP210X=m
++CONFIG_USB_SERIAL_FTDI_SIO=m
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_USB_HSIC_USB3503=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_ULPI=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_SNP_UDC_PLAT=y
++CONFIG_USB_BDC_UDC=y
++CONFIG_USB_CONFIGFS=m
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_TYPEC=m
++CONFIG_TYPEC_TCPM=m
++CONFIG_TYPEC_TCPCI=m
++CONFIG_TYPEC_FUSB302=m
++CONFIG_TYPEC_TPS6598X=m
++CONFIG_TYPEC_HD3SS3220=m
++CONFIG_MMC=y
++CONFIG_MMC_BLOCK_MINORS=32
++CONFIG_MMC_ARMMMCI=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_ACPI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_OF_ARASAN=y
++CONFIG_MMC_SDHCI_OF_DWCMSHC=y
++CONFIG_MMC_SDHCI_CADENCE=y
++CONFIG_MMC_SDHCI_F_SDH30=y
++CONFIG_MMC_SPI=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_EXYNOS=y
++CONFIG_MMC_DW_HI3798CV200=y
++CONFIG_MMC_DW_K3=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_MMC_MTK=y
++CONFIG_MMC_SDHCI_XENON=y
++CONFIG_MMC_SDHCI_AM654=y
++CONFIG_SCSI_UFSHCD=y
++CONFIG_SCSI_UFSHCD_PLATFORM=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS_MULTICOLOR=m
++CONFIG_LEDS_LM3692X=m
++CONFIG_LEDS_PCA9532=m
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_PWM=y
++CONFIG_LEDS_SYSCON=y
++CONFIG_LEDS_QCOM_LPG=m
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_DISK=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_EDAC=y
++CONFIG_EDAC_GHES=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_DRV_DS1307=m
++CONFIG_RTC_DRV_HYM8563=m
++CONFIG_RTC_DRV_MAX77686=y
++CONFIG_RTC_DRV_RK808=m
++CONFIG_RTC_DRV_PCF85063=m
++CONFIG_RTC_DRV_PCF85363=m
++CONFIG_RTC_DRV_M41T80=m
++CONFIG_RTC_DRV_RX8581=m
++CONFIG_RTC_DRV_RV3028=m
++CONFIG_RTC_DRV_RV8803=m
++CONFIG_RTC_DRV_S5M=y
++CONFIG_RTC_DRV_DS3232=y
++CONFIG_RTC_DRV_PCF2127=m
++CONFIG_RTC_DRV_EFI=y
++CONFIG_RTC_DRV_CROS_EC=y
++CONFIG_RTC_DRV_PL031=y
++CONFIG_RTC_DRV_MT6397=m
++CONFIG_DMADEVICES=y
++CONFIG_BCM_SBA_RAID=m
++CONFIG_FSL_EDMA=y
++CONFIG_MV_XOR_V2=y
++CONFIG_PL330_DMA=y
++CONFIG_QCOM_HIDMA_MGMT=y
++CONFIG_QCOM_HIDMA=y
++CONFIG_VFIO=y
++CONFIG_VFIO_PCI=y
++CONFIG_VIRTIO_PCI=y
++CONFIG_VIRTIO_BALLOON=y
++CONFIG_VIRTIO_MMIO=y
++CONFIG_XEN_GNTDEV=y
++CONFIG_XEN_GRANT_DEV_ALLOC=y
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_MAX96712=m
++CONFIG_CHROME_PLATFORMS=y
++CONFIG_CROS_EC=y
++CONFIG_CROS_EC_I2C=y
++CONFIG_CROS_EC_SPI=y
++CONFIG_CROS_EC_CHARDEV=m
++CONFIG_CLK_VEXPRESS_OSC=y
++CONFIG_COMMON_CLK_RK808=y
++CONFIG_COMMON_CLK_SCMI=y
++CONFIG_COMMON_CLK_SCPI=y
++CONFIG_COMMON_CLK_CS2000_CP=y
++CONFIG_COMMON_CLK_S2MPS11=y
++CONFIG_COMMON_CLK_XGENE=y
++CONFIG_COMMON_CLK_PWM=y
++CONFIG_COMMON_CLK_VC5=y
++CONFIG_COMMON_CLK_BD718XX=m
++CONFIG_HWSPINLOCK=y
++CONFIG_ARM_MHU=y
++CONFIG_PLATFORM_MHU=y
++CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
++CONFIG_IOMMU_IO_PGTABLE_DART=y
++CONFIG_ROCKCHIP_IOMMU=y
++CONFIG_ARM_SMMU=y
++CONFIG_ARM_SMMU_V3=y
++CONFIG_REMOTEPROC=y
++CONFIG_RPMSG_CHAR=m
++CONFIG_RPMSG_CTRL=m
++CONFIG_RPMSG_QCOM_GLINK_RPM=y
++CONFIG_SOUNDWIRE=m
++CONFIG_SOUNDWIRE_QCOM=m
++CONFIG_SOC_BRCMSTB=y
++CONFIG_FSL_RCPM=y
++CONFIG_ROCKCHIP_IODOMAIN=y
++CONFIG_ROCKCHIP_PM_DOMAINS=y
++CONFIG_SOC_TI=y
++CONFIG_DEVFREQ_GOV_USERSPACE=m
++CONFIG_EXTCON_PTN5150=m
++CONFIG_EXTCON_USB_GPIO=y
++CONFIG_EXTCON_USBC_CROS_EC=y
++CONFIG_MEMORY=y
++CONFIG_IIO=y
++CONFIG_MAX9611=m
++CONFIG_QCOM_SPMI_VADC=m
++CONFIG_QCOM_SPMI_ADC5=m
++CONFIG_ROCKCHIP_SARADC=m
++CONFIG_TI_ADS1015=m
++CONFIG_IIO_CROS_EC_SENSORS_CORE=m
++CONFIG_IIO_CROS_EC_SENSORS=m
++CONFIG_IIO_ST_LSM6DSX=m
++CONFIG_IIO_CROS_EC_LIGHT_PROX=m
++CONFIG_SENSORS_ISL29018=m
++CONFIG_VCNL4000=m
++CONFIG_IIO_ST_MAGN_3AXIS=m
++CONFIG_IIO_CROS_EC_BARO=m
++CONFIG_MPL3115=m
++CONFIG_PWM=y
++CONFIG_PWM_CROS_EC=m
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_PHY_XGENE=y
++CONFIG_PHY_CADENCE_TORRENT=m
++CONFIG_PHY_CADENCE_SIERRA=m
++CONFIG_PHY_QCOM_USB_HS=m
++CONFIG_PHY_ROCKCHIP_EMMC=y
++CONFIG_PHY_ROCKCHIP_INNO_HDMI=m
++CONFIG_PHY_ROCKCHIP_INNO_USB2=y
++CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m
++CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
++CONFIG_PHY_ROCKCHIP_PCIE=m
++CONFIG_PHY_ROCKCHIP_TYPEC=y
++CONFIG_PHY_ROCKCHIP_USB=y
++CONFIG_PHY_SAMSUNG_USB2=y
++CONFIG_ARM_CCI_PMU=m
++CONFIG_ARM_CCN=m
++CONFIG_ARM_CMN=m
++CONFIG_ARM_SMMU_V3_PMU=m
++CONFIG_ARM_DSU_PMU=m
++CONFIG_ARM_SPE_PMU=m
++CONFIG_ARM_DMC620_PMU=m
++CONFIG_HISI_PMU=y
++CONFIG_NVMEM_RMEM=m
++CONFIG_NVMEM_ROCKCHIP_EFUSE=y
++CONFIG_FPGA=y
++CONFIG_FPGA_MGR_ALTERA_CVP=m
++CONFIG_FPGA_BRIDGE=m
++CONFIG_ALTERA_FREEZE_BRIDGE=m
++CONFIG_FPGA_REGION=m
++CONFIG_OF_FPGA_REGION=m
++CONFIG_TEE=y
++CONFIG_OPTEE=y
++CONFIG_MUX_MMIO=y
++CONFIG_SLIM_QCOM_CTRL=m
++CONFIG_INTERCONNECT=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_BTRFS_FS=m
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_FANOTIFY=y
++CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
++CONFIG_QUOTA=y
++CONFIG_AUTOFS4_FS=y
++CONFIG_FUSE_FS=m
++CONFIG_CUSE=m
++CONFIG_OVERLAY_FS=m
++CONFIG_VFAT_FS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_HUGETLBFS=y
++CONFIG_EFIVAR_FS=y
++CONFIG_SQUASHFS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V4=y
++CONFIG_NFS_V4_1=y
++CONFIG_NFS_V4_2=y
++CONFIG_ROOT_NFS=y
++CONFIG_9P_FS=y
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_SECURITY=y
++CONFIG_CRYPTO_DES=m
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_MICHAEL_MIC=m
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_RNG=m
++CONFIG_CRYPTO_CHACHA20_NEON=m
++CONFIG_CRYPTO_GHASH_ARM64_CE=y
++CONFIG_CRYPTO_SHA1_ARM64_CE=y
++CONFIG_CRYPTO_SHA2_ARM64_CE=y
++CONFIG_CRYPTO_SHA512_ARM64_CE=m
++CONFIG_CRYPTO_SHA3_ARM64=m
++CONFIG_CRYPTO_SM3_ARM64_CE=m
++CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
++CONFIG_CRYPTO_AES_ARM64_BS=m
++CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
++CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
++CONFIG_CRYPTO_DEV_CCREE=m
++CONFIG_CRYPTO_DEV_HISI_SEC2=m
++CONFIG_CRYPTO_DEV_HISI_ZIP=m
++CONFIG_CRYPTO_DEV_HISI_HPRE=m
++CONFIG_CRYPTO_DEV_HISI_TRNG=m
++CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
++CONFIG_INDIRECT_PIO=y
++CONFIG_CRC_CCITT=m
++CONFIG_CMA_SIZE_MBYTES=32
++CONFIG_PRINTK_TIME=y
++CONFIG_DEBUG_KERNEL=y
++CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
++CONFIG_DEBUG_INFO_REDUCED=y
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_DEBUG_PREEMPT is not set
++# CONFIG_FTRACE is not set
++CONFIG_CORESIGHT=m
++CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m
++CONFIG_CORESIGHT_CATU=m
++CONFIG_CORESIGHT_SINK_TPIU=m
++CONFIG_CORESIGHT_SINK_ETBV10=m
++CONFIG_CORESIGHT_STM=m
++CONFIG_CORESIGHT_CPU_DEBUG=m
++CONFIG_CORESIGHT_CTI=m
++CONFIG_MEMTEST=y
diff --git a/evdi-6.14.patch b/evdi-6.14.patch
new file mode 100644
index 0000000..b86914b
--- /dev/null
+++ b/evdi-6.14.patch
@@ -0,0 +1,13 @@
+diff -up linux-6.14-rc2/drivers/gpu/drm/evdi/evdi_drm_drv.c.omv~ linux-6.14-rc2/drivers/gpu/drm/evdi/evdi_drm_drv.c
+--- linux-6.14-rc2/drivers/gpu/drm/evdi/evdi_drm_drv.c.omv~	2025-02-15 15:28:14.750935583 +0100
++++ linux-6.14-rc2/drivers/gpu/drm/evdi/evdi_drm_drv.c	2025-02-15 15:28:36.992947952 +0100
+@@ -147,7 +147,9 @@ static struct drm_driver driver = {
+ 
+ 	.name = DRIVER_NAME,
+ 	.desc = DRIVER_DESC,
++#if LINUX_VERSION_CODE < KERNEL_VERSION(6,14,0)
+ 	.date = DRIVER_DATE,
++#endif
+ 	.major = DRIVER_MAJOR,
+ 	.minor = DRIVER_MINOR,
+ 	.patchlevel = DRIVER_PATCH,
diff --git a/evdi-6.18.patch b/evdi-6.18.patch
new file mode 100644
index 0000000..96a1fa2
--- /dev/null
+++ b/evdi-6.18.patch
@@ -0,0 +1,76 @@
+diff -up linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_drm_drv.c.omv~ linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_drm_drv.c
+--- linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_drm_drv.c.omv~	2025-10-30 19:54:08.226744784 +0100
++++ linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_drm_drv.c	2025-10-30 20:36:27.450965435 +0100
+@@ -169,6 +169,7 @@ static void evdi_drm_device_release_cb(_
+ 
+ 	evdi_cursor_free(evdi->cursor);
+ 	evdi_painter_cleanup(evdi->painter);
++	mutex_destroy(&evdi->lock);
+ 	kfree(evdi);
+ 	dev->dev_private = NULL;
+ 	EVDI_INFO("Evdi drm_device removed.\n");
+@@ -189,6 +190,7 @@ static int evdi_drm_device_init(struct d
+ 	evdi->ddev = dev;
+ 	evdi->dev_index = dev->primary->index;
+ 	evdi->cursor_events_enabled = false;
++	mutex_init(&evdi->lock);
+ 	dev->dev_private = evdi;
+ 	ret = evdi_painter_init(evdi);
+ 	if (ret)
+diff -up linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_drm_drv.h.omv~ linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_drm_drv.h
+--- linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_drm_drv.h.omv~	2025-10-30 19:53:02.617222632 +0100
++++ linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_drm_drv.h	2025-10-30 20:36:39.258735918 +0100
+@@ -58,6 +58,8 @@ struct evdi_device {
+ 	struct i2c_adapter *i2c_adapter;
+ 
+ 	int dev_index;
++
++	struct mutex lock;
+ };
+ 
+ struct evdi_gem_object {
+diff -up linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_gem.c.omv~ linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_gem.c
+--- linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_gem.c.omv~	2025-10-30 20:35:51.418877933 +0100
++++ linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_gem.c	2025-10-30 20:39:32.745487651 +0100
+@@ -400,9 +400,10 @@ int evdi_gem_mmap(struct drm_file *file,
+ {
+ 	struct evdi_gem_object *gobj;
+ 	struct drm_gem_object *obj;
++	struct evdi_device *evdi = dev->dev_private;
+ 	int ret = 0;
+ 
+-	mutex_lock(&dev->struct_mutex);
++	mutex_lock(&evdi->lock);
+ 	obj = drm_gem_object_lookup(file, handle);
+ 	if (obj == NULL) {
+ 		ret = -ENOENT;
+@@ -430,7 +431,7 @@ int evdi_gem_mmap(struct drm_file *file,
+  out:
+ 	drm_gem_object_put(&gobj->base);
+  unlock:
+-	mutex_unlock(&dev->struct_mutex);
++	mutex_unlock(&evdi->lock);
+ 	return ret;
+ }
+ 
+diff -up linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_modeset.c.omv~ linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_modeset.c
+--- linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_modeset.c.omv~	2025-10-30 19:46:19.668163744 +0100
++++ linux-6.18-rc3/drivers/gpu/drm/evdi/evdi_modeset.c	2025-10-30 20:36:52.565083211 +0100
+@@ -343,7 +343,7 @@ static void evdi_cursor_atomic_update(st
+ 		int32_t cursor_position_x = 0;
+ 		int32_t cursor_position_y = 0;
+ 
+-		mutex_lock(&plane->dev->struct_mutex);
++		mutex_lock(&evdi->lock);
+ 
+ 		evdi_cursor_position(evdi->cursor, &cursor_position_x,
+ 		&cursor_position_y);
+@@ -369,7 +369,7 @@ static void evdi_cursor_atomic_update(st
+ 			cursor_changed = true;
+ 		}
+ 
+-		mutex_unlock(&plane->dev->struct_mutex);
++		mutex_unlock(&evdi->lock);
+ 		if (!evdi->cursor_events_enabled) {
+ 			if (fb != NULL) {
+ 				if (efb->obj->allow_sw_cursor_rect_updates) {
diff --git a/export-symbols-needed-by-android-drivers.patch b/export-symbols-needed-by-android-drivers.patch
index 9d6c956..6b42bb4 100644
--- a/export-symbols-needed-by-android-drivers.patch
+++ b/export-symbols-needed-by-android-drivers.patch
@@ -1,40 +1,40 @@
-diff -up linux-5.19/fs/file.c.29~ linux-5.19/fs/file.c
---- linux-5.19/fs/file.c.29~	2022-09-08 15:55:44.097318572 +0200
-+++ linux-5.19/fs/file.c	2022-09-08 15:56:15.849895645 +0200
-@@ -813,6 +813,7 @@ struct file *close_fd_get_file(unsigned
+diff -up linux-6.19-rc4/fs/file.c.29~ linux-6.19-rc4/fs/file.c
+--- linux-6.19-rc4/fs/file.c.29~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/fs/file.c	2026-01-10 15:38:25.855309909 +0100
+@@ -881,6 +881,7 @@ struct file *file_close_fd(unsigned int
  
  	return file;
  }
-+EXPORT_SYMBOL_GPL(close_fd_get_file);
++EXPORT_SYMBOL_GPL(file_close_fd);
  
  void do_close_on_exec(struct files_struct *files)
  {
-diff -up linux-5.19/ipc/msgutil.c.29~ linux-5.19/ipc/msgutil.c
---- linux-5.19/ipc/msgutil.c.29~	2022-07-31 23:03:01.000000000 +0200
-+++ linux-5.19/ipc/msgutil.c	2022-09-08 15:55:44.097318572 +0200
-@@ -33,6 +33,7 @@ struct ipc_namespace init_ipc_ns = {
- 	.ns.ops = &ipcns_operations,
- #endif
+diff -up linux-6.19-rc4/ipc/msgutil.c.29~ linux-6.19-rc4/ipc/msgutil.c
+--- linux-6.19-rc4/ipc/msgutil.c.29~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/ipc/msgutil.c	2026-01-10 15:39:57.558810001 +0100
+@@ -30,6 +30,7 @@ struct ipc_namespace init_ipc_ns = {
+ 	.ns = NS_COMMON_INIT(init_ipc_ns),
+ 	.user_ns = &init_user_ns,
  };
 +EXPORT_SYMBOL_GPL(init_ipc_ns);
  
  struct msg_msgseg {
  	struct msg_msgseg *next;
-diff -up linux-5.19/ipc/namespace.c.29~ linux-5.19/ipc/namespace.c
---- linux-5.19/ipc/namespace.c.29~	2022-07-31 23:03:01.000000000 +0200
-+++ linux-5.19/ipc/namespace.c	2022-09-08 15:55:44.097318572 +0200
-@@ -185,6 +185,7 @@ void put_ipc_ns(struct ipc_namespace *ns
+diff -up linux-6.19-rc4/ipc/namespace.c.29~ linux-6.19-rc4/ipc/namespace.c
+--- linux-6.19-rc4/ipc/namespace.c.29~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/ipc/namespace.c	2026-01-10 15:38:25.855823455 +0100
+@@ -210,6 +210,7 @@ void put_ipc_ns(struct ipc_namespace *ns
  			schedule_work(&free_ipc_work);
  	}
  }
 +EXPORT_SYMBOL_GPL(put_ipc_ns);
  
- static inline struct ipc_namespace *to_ipc_ns(struct ns_common *ns)
+ static struct ns_common *ipcns_get(struct task_struct *task)
  {
-diff -up linux-5.19/kernel/sched/core.c.29~ linux-5.19/kernel/sched/core.c
---- linux-5.19/kernel/sched/core.c.29~	2022-09-08 15:55:44.099318545 +0200
-+++ linux-5.19/kernel/sched/core.c	2022-09-08 15:56:40.669564489 +0200
-@@ -7036,6 +7036,7 @@ int can_nice(const struct task_struct *p
+diff -up linux-6.19-rc4/kernel/sched/syscalls.c.29~ linux-6.19-rc4/kernel/sched/syscalls.c
+--- linux-6.19-rc4/kernel/sched/syscalls.c.29~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/kernel/sched/syscalls.c	2026-01-10 15:38:25.856118649 +0100
+@@ -119,6 +119,7 @@ int can_nice(const struct task_struct *p
  {
  	return is_nice_reduction(p, nice) || capable(CAP_SYS_NICE);
  }
@@ -42,10 +42,21 @@ diff -up linux-5.19/kernel/sched/core.c.29~ linux-5.19/kernel/sched/core.c
  
  #ifdef __ARCH_WANT_SYS_NICE
  
-diff -up linux-5.19/kernel/signal.c.29~ linux-5.19/kernel/signal.c
---- linux-5.19/kernel/signal.c.29~	2022-09-08 15:55:44.100318532 +0200
-+++ linux-5.19/kernel/signal.c	2022-09-08 15:57:02.379274455 +0200
-@@ -1411,6 +1411,7 @@ struct sighand_struct *__lock_task_sigha
+diff -up linux-6.19-rc4/kernel/sched/wait.c.29~ linux-6.19-rc4/kernel/sched/wait.c
+--- linux-6.19-rc4/kernel/sched/wait.c.29~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/kernel/sched/wait.c	2026-01-10 15:38:25.856350262 +0100
+@@ -231,6 +231,7 @@ void __wake_up_pollfree(struct wait_queu
+ 	/* POLLFREE must have cleared the queue. */
+ 	WARN_ON_ONCE(waitqueue_active(wq_head));
+ }
++EXPORT_SYMBOL_GPL(__wake_up_pollfree);
+ 
+ /*
+  * Note: we use "set_current_state()" _after_ the wait-queue add,
+diff -up linux-6.19-rc4/kernel/signal.c.29~ linux-6.19-rc4/kernel/signal.c
+--- linux-6.19-rc4/kernel/signal.c.29~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/kernel/signal.c	2026-01-10 15:38:25.856884348 +0100
+@@ -1386,6 +1386,7 @@ struct sighand_struct *__lock_task_sigha
  
  	return sighand;
  }
@@ -53,10 +64,10 @@ diff -up linux-5.19/kernel/signal.c.29~ linux-5.19/kernel/signal.c
  
  #ifdef CONFIG_LOCKDEP
  void lockdep_assert_task_sighand_held(struct task_struct *task)
-diff -up linux-5.19/kernel/task_work.c.29~ linux-5.19/kernel/task_work.c
---- linux-5.19/kernel/task_work.c.29~	2022-07-31 23:03:01.000000000 +0200
-+++ linux-5.19/kernel/task_work.c	2022-09-08 15:55:44.100318532 +0200
-@@ -73,6 +73,7 @@ int task_work_add(struct task_struct *ta
+diff -up linux-6.19-rc4/kernel/task_work.c.29~ linux-6.19-rc4/kernel/task_work.c
+--- linux-6.19-rc4/kernel/task_work.c.29~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/kernel/task_work.c	2026-01-10 15:38:25.857379754 +0100
+@@ -102,6 +102,7 @@ int task_work_add(struct task_struct *ta
  
  	return 0;
  }
@@ -64,32 +75,32 @@ diff -up linux-5.19/kernel/task_work.c.29~ linux-5.19/kernel/task_work.c
  
  /**
   * task_work_cancel_match - cancel a pending work added by task_work_add()
-diff -up linux-5.19/mm/memory.c.29~ linux-5.19/mm/memory.c
---- linux-5.19/mm/memory.c.29~	2022-07-31 23:03:01.000000000 +0200
-+++ linux-5.19/mm/memory.c	2022-09-08 15:55:44.101318518 +0200
-@@ -1749,6 +1749,7 @@ void zap_page_range(struct vm_area_struc
- 	mmu_notifier_invalidate_range_end(&range);
+diff -up linux-6.19-rc4/mm/memory.c.29~ linux-6.19-rc4/mm/memory.c
+--- linux-6.19-rc4/mm/memory.c.29~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/mm/memory.c	2026-01-10 15:38:25.858090962 +0100
+@@ -2165,6 +2165,7 @@ void zap_page_range_single(struct vm_are
+ 	zap_page_range_single_batched(&tlb, vma, address, size, details);
  	tlb_finish_mmu(&tlb);
  }
-+EXPORT_SYMBOL_GPL(zap_page_range);
++EXPORT_SYMBOL_GPL(zap_page_range_single);
  
  /**
-  * zap_page_range_single - remove user pages in a given range
-diff -up linux-5.19/mm/shmem.c.29~ linux-5.19/mm/shmem.c
---- linux-5.19/mm/shmem.c.29~	2022-09-08 15:55:43.804322470 +0200
-+++ linux-5.19/mm/shmem.c	2022-09-08 15:55:44.101318518 +0200
-@@ -4173,6 +4173,7 @@ int shmem_zero_setup(struct vm_area_stru
+  * zap_vma_ptes - remove ptes mapping the vma
+diff -up linux-6.19-rc4/mm/shmem.c.29~ linux-6.19-rc4/mm/shmem.c
+--- linux-6.19-rc4/mm/shmem.c.29~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/mm/shmem.c	2026-01-10 15:38:25.859022363 +0100
+@@ -5943,6 +5943,7 @@ int shmem_zero_setup_desc(struct vm_area
  
  	return 0;
  }
 +EXPORT_SYMBOL_GPL(shmem_zero_setup);
  
  /**
-  * shmem_read_mapping_page_gfp - read into page cache, using specified page allocation flags.
-diff -up linux-5.19/mm/vmalloc.c.29~ linux-5.19/mm/vmalloc.c
---- linux-5.19/mm/vmalloc.c.29~	2022-09-08 15:55:43.805322457 +0200
-+++ linux-5.19/mm/vmalloc.c	2022-09-08 15:55:44.101318518 +0200
-@@ -2499,6 +2499,7 @@ struct vm_struct *get_vm_area(unsigned l
+  * shmem_read_folio_gfp - read into page cache, using specified page allocation flags.
+diff -up linux-6.19-rc4/mm/vmalloc.c.29~ linux-6.19-rc4/mm/vmalloc.c
+--- linux-6.19-rc4/mm/vmalloc.c.29~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/mm/vmalloc.c	2026-01-10 15:38:25.859809903 +0100
+@@ -3263,6 +3263,7 @@ struct vm_struct *get_vm_area(unsigned l
  				  NUMA_NO_NODE, GFP_KERNEL,
  				  __builtin_return_address(0));
  }
@@ -97,46 +108,38 @@ diff -up linux-5.19/mm/vmalloc.c.29~ linux-5.19/mm/vmalloc.c
  
  struct vm_struct *get_vm_area_caller(unsigned long size, unsigned long flags,
  				const void *caller)
-diff -up linux-5.19/security/security.c.29~ linux-5.19/security/security.c
---- linux-5.19/security/security.c.29~	2022-09-08 15:55:44.102318505 +0200
-+++ linux-5.19/security/security.c	2022-09-08 15:57:59.885504578 +0200
-@@ -752,24 +752,28 @@ int security_binder_set_context_mgr(cons
+diff -up linux-6.19-rc4/security/security.c.29~ linux-6.19-rc4/security/security.c
+--- linux-6.19-rc4/security/security.c.29~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/security/security.c	2026-01-10 15:38:25.860556942 +0100
+@@ -488,6 +488,7 @@ int security_binder_set_context_mgr(cons
  {
- 	return call_int_hook(binder_set_context_mgr, 0, mgr);
+ 	return call_int_hook(binder_set_context_mgr, mgr);
  }
 +EXPORT_SYMBOL_GPL(security_binder_set_context_mgr);
  
- int security_binder_transaction(const struct cred *from,
- 				const struct cred *to)
+ /**
+  * security_binder_transaction() - Check if a binder transaction is allowed
+@@ -503,6 +504,7 @@ int security_binder_transaction(const st
  {
- 	return call_int_hook(binder_transaction, 0, from, to);
+ 	return call_int_hook(binder_transaction, from, to);
  }
 +EXPORT_SYMBOL_GPL(security_binder_transaction);
  
- int security_binder_transfer_binder(const struct cred *from,
- 				    const struct cred *to)
+ /**
+  * security_binder_transfer_binder() - Check if a binder transfer is allowed
+@@ -518,6 +520,7 @@ int security_binder_transfer_binder(cons
  {
- 	return call_int_hook(binder_transfer_binder, 0, from, to);
+ 	return call_int_hook(binder_transfer_binder, from, to);
  }
 +EXPORT_SYMBOL_GPL(security_binder_transfer_binder);
  
- int security_binder_transfer_file(const struct cred *from,
- 				  const struct cred *to, struct file *file)
+ /**
+  * security_binder_transfer_file() - Check if a binder file xfer is allowed
+@@ -534,6 +537,7 @@ int security_binder_transfer_file(const
  {
- 	return call_int_hook(binder_transfer_file, 0, from, to, file);
+ 	return call_int_hook(binder_transfer_file, from, to, file);
  }
 +EXPORT_SYMBOL_GPL(security_binder_transfer_file);
  
- int security_ptrace_access_check(struct task_struct *child, unsigned int mode)
- {
-diff -up linux-5.19/kernel/sched/wait.c.omv~ linux-5.19/kernel/sched/wait.c
---- linux-5.19/kernel/sched/wait.c.omv~	2022-09-08 17:05:46.292683449 +0200
-+++ linux-5.19/kernel/sched/wait.c	2022-09-08 17:06:01.908468384 +0200
-@@ -243,6 +243,7 @@ void __wake_up_pollfree(struct wait_queu
- 	/* POLLFREE must have cleared the queue. */
- 	WARN_ON_ONCE(waitqueue_active(wq_head));
- }
-+EXPORT_SYMBOL_GPL(__wake_up_pollfree);
- 
- /*
-  * Note: we use "set_current_state()" _after_ the wait-queue add,
+ /**
+  * security_ptrace_access_check() - Check if tracing is allowed
diff --git a/f0118748bc1f791775c90c52791a1770f4429702.patch b/f0118748bc1f791775c90c52791a1770f4429702.patch
new file mode 100644
index 0000000..fa5db31
--- /dev/null
+++ b/f0118748bc1f791775c90c52791a1770f4429702.patch
@@ -0,0 +1,37 @@
+From f0118748bc1f791775c90c52791a1770f4429702 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 24 Oct 2023 18:09:57 +0200
+Subject: [PATCH] clk: composite: replace open-coded abs_diff()
+
+Replace the open coded abs_diff() with the existing helper function.
+
+Suggested-by: Andy Shevchenko <andriy.shevchenko@intel.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ drivers/clk/clk-composite.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
+index 66759fe28fad67..478a4e594336a3 100644
+--- a/drivers/clk/clk-composite.c
++++ b/drivers/clk/clk-composite.c
+@@ -6,6 +6,7 @@
+ #include <linux/clk-provider.h>
+ #include <linux/device.h>
+ #include <linux/err.h>
++#include <linux/math.h>
+ #include <linux/slab.h>
+ 
+ static u8 clk_composite_get_parent(struct clk_hw *hw)
+@@ -119,10 +120,7 @@ static int clk_composite_determine_rate(struct clk_hw *hw,
+ 			if (ret)
+ 				continue;
+ 
+-			if (req->rate >= tmp_req.rate)
+-				rate_diff = req->rate - tmp_req.rate;
+-			else
+-				rate_diff = tmp_req.rate - req->rate;
++			rate_diff = abs_diff(req->rate, tmp_req.rate);
+ 
+ 			if (!rate_diff || !req->best_parent_hw
+ 				       || best_rate_diff > rate_diff) {
diff --git a/f45ac0c8b0145582ba277f149a39ad386b0627b1.patch b/f45ac0c8b0145582ba277f149a39ad386b0627b1.patch
new file mode 100644
index 0000000..0c38efe
--- /dev/null
+++ b/f45ac0c8b0145582ba277f149a39ad386b0627b1.patch
@@ -0,0 +1,23 @@
+From f45ac0c8b0145582ba277f149a39ad386b0627b1 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Sat, 27 Apr 2024 19:05:09 +0800
+Subject: [PATCH] arm: dts: rockchip: rk3036-kylin: Force MAC address
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ arch/arm/boot/dts/rockchip/rk3036-kylin.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts
+index 1d4313f371fe4f..270aac86a334af 100644
+--- a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts
++++ b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts
+@@ -118,7 +118,7 @@
+ 	phy = <&phy0>;
+ 
+ 	status = "okay";
+-
++	mac-address = [ fe 46 f2 84 84 fe ];
+ 	phy0: ethernet-phy@0 {
+ 		reg = <0>;
+ 	};
diff --git a/filesystems.fragment b/filesystems.fragment
new file mode 100644
index 0000000..bec47f5
--- /dev/null
+++ b/filesystems.fragment
@@ -0,0 +1,456 @@
+#
+# File systems
+#
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_VALIDATE_FS_PARSER=y
+CONFIG_FS_IOMAP=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_LEGACY_DIRECT_IO=y
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_USE_FOR_EXT2=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+# CONFIG_EXT4_KUNIT_TESTS is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+CONFIG_REISERFS_PROC_INFO=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_JFS_FS=m
+CONFIG_JFS_POSIX_ACL=y
+CONFIG_JFS_SECURITY=y
+# CONFIG_JFS_DEBUG is not set
+CONFIG_JFS_STATISTICS=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_SUPPORT_V4 is not set
+# CONFIG_XFS_SUPPORT_ASCII_CI is not set
+CONFIG_XFS_QUOTA=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_XFS_RT=y
+CONFIG_XFS_DRAIN_INTENTS=y
+CONFIG_XFS_ONLINE_SCRUB=y
+# CONFIG_XFS_ONLINE_SCRUB_STATS is not set
+# CONFIG_XFS_ONLINE_REPAIR is not set
+# CONFIG_XFS_WARN is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+CONFIG_OCFS2_FS=m
+CONFIG_OCFS2_FS_O2CB=m
+CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+# CONFIG_OCFS2_FS_STATS is not set
+CONFIG_OCFS2_DEBUG_MASKLOG=y
+CONFIG_OCFS2_DEBUG_FS=y
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
+# CONFIG_BTRFS_DEBUG is not set
+# CONFIG_BTRFS_ASSERT is not set
+# CONFIG_BTRFS_EXPERIMENTAL is not set
+# CONFIG_BTRFS_FS_REF_VERIFY is not set
+CONFIG_NILFS2_FS=m
+CONFIG_F2FS_FS=m
+CONFIG_F2FS_STAT_FS=y
+CONFIG_F2FS_FS_XATTR=y
+CONFIG_F2FS_FS_POSIX_ACL=y
+CONFIG_F2FS_FS_SECURITY=y
+# CONFIG_F2FS_CHECK_FS is not set
+# CONFIG_F2FS_FAULT_INJECTION is not set
+CONFIG_F2FS_FS_COMPRESSION=y
+CONFIG_F2FS_FS_LZO=y
+CONFIG_F2FS_FS_LZORLE=y
+CONFIG_F2FS_FS_LZ4=y
+CONFIG_F2FS_FS_LZ4HC=y
+CONFIG_F2FS_FS_ZSTD=y
+# CONFIG_F2FS_IOSTAT is not set
+# CONFIG_F2FS_UNFAIR_RWSEM is not set
+CONFIG_BCACHEFS_FS=m
+CONFIG_BCACHEFS_QUOTA=y
+# CONFIG_BCACHEFS_ERASURE_CODING is not set
+CONFIG_BCACHEFS_POSIX_ACL=y
+# CONFIG_BCACHEFS_DEBUG_TRANSACTIONS is not set
+# CONFIG_BCACHEFS_DEBUG is not set
+# CONFIG_BCACHEFS_TESTS is not set
+# CONFIG_BCACHEFS_LOCK_TIME_STATS is not set
+CONFIG_BCACHEFS_NO_LATENCY_ACCT=y
+CONFIG_BCACHEFS_SIX_OPTIMISTIC_SPIN=y
+# CONFIG_BCACHEFS_TRANS_KMALLOC_TRACE is not set
+# CONFIG_BCACHEFS_ASYNC_OBJECT_LISTS is not set
+# CONFIG_BCACHEFS_PATH_TRACEPOINTS is not set
+# CONFIG_MEAN_AND_VARIANCE_UNIT_TEST is not set
+CONFIG_FS_DAX=y
+CONFIG_ZONEFS_FS=m
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_EXPORTFS_BLOCK_OPS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FS_ENCRYPTION=y
+CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
+CONFIG_FS_ENCRYPTION_ALGS=y
+CONFIG_FS_VERITY=y
+# CONFIG_FS_VERITY_BUILTIN_SIGNATURES is not set
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_QUOTA_DEBUG is not set
+CONFIG_QUOTA_TREE=m
+CONFIG_QFMT_V1=m
+CONFIG_QFMT_V2=m
+CONFIG_QUOTACTL=y
+CONFIG_AUTOFS_FS=m
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+CONFIG_VIRTIO_FS=m
+CONFIG_FUSE_PASSTHROUGH=y
+CONFIG_FUSE_IO_URING=y
+CONFIG_FUSE_DAX=y
+CONFIG_OVERLAY_FS=m
+CONFIG_OVERLAY_FS_REDIRECT_DIR=y
+CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
+CONFIG_OVERLAY_FS_INDEX=y
+CONFIG_OVERLAY_FS_NFS_EXPORT=y
+CONFIG_OVERLAY_FS_XINO_AUTO=y
+# CONFIG_OVERLAY_FS_METACOPY is not set
+# CONFIG_OVERLAY_FS_DEBUG is not set
+
+#
+# Caches
+#
+CONFIG_NETFS_SUPPORT=m
+CONFIG_NETFS_STATS=y
+# CONFIG_NETFS_DEBUG is not set
+CONFIG_FSCACHE=m
+CONFIG_FSCACHE_STATS=y
+# CONFIG_FSCACHE_DEBUG is not set
+CONFIG_CACHEFILES=m
+# CONFIG_CACHEFILES_DEBUG is not set
+# CONFIG_CACHEFILES_ERROR_INJECTION is not set
+# CONFIG_CACHEFILES_ONDEMAND is not set
+# end of Caches
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+# end of CD-ROM/DVD Filesystems
+
+#
+# DOS/FAT/EXFAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
+CONFIG_FAT_DEFAULT_UTF8=y
+# CONFIG_FAT_KUNIT_TEST is not set
+CONFIG_EXFAT_FS=m
+CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+CONFIG_NTFS3_FS=m
+# CONFIG_NTFS3_64BIT_CLUSTER is not set
+CONFIG_NTFS3_LZX_XPRESS=y
+CONFIG_NTFS3_FS_POSIX_ACL=y
+# end of DOS/FAT/EXFAT/NT Filesystems
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PROC_VMCORE_DEVICE_DUMP=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_PROC_PID_ARCH_STATUS=y
+CONFIG_PROC_CPU_RESCTRL=y
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+CONFIG_TMPFS_INODE64=y
+CONFIG_TMPFS_QUOTA=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y
+CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON=y
+CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_EFIVAR_FS=m
+# end of Pseudo filesystems
+
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_ORANGEFS_FS=m
+CONFIG_ADFS_FS=m
+# CONFIG_ADFS_FS_RW is not set
+CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+CONFIG_BFS_FS=m
+CONFIG_EFS_FS=m
+CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_UBIFS_FS=m
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UBIFS_FS_ZSTD=y
+CONFIG_UBIFS_ATIME_SUPPORT=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_SECURITY=y
+# CONFIG_UBIFS_FS_AUTHENTICATION is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=m
+# CONFIG_SQUASHFS_FILE_CACHE is not set
+CONFIG_SQUASHFS_FILE_DIRECT=y
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_DECOMP_MULTI=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y
+CONFIG_SQUASHFS_MOUNT_DECOMP_THREADS=y
+CONFIG_SQUASHFS_XATTR=y
+# CONFIG_SQUASHFS_COMP_CACHE_FULL is not set
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SQUASHFS_LZ4=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_ZSTD=y
+CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
+CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+CONFIG_VXFS_FS=m
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
+CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_QNX6FS_FS=m
+# CONFIG_QNX6FS_DEBUG is not set
+CONFIG_ROMFS_FS=m
+# CONFIG_ROMFS_BACKED_BY_BLOCK is not set
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+CONFIG_ROMFS_BACKED_BY_BOTH=y
+CONFIG_ROMFS_ON_BLOCK=y
+CONFIG_ROMFS_ON_MTD=y
+CONFIG_PSTORE=y
+CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
+CONFIG_PSTORE_COMPRESS=y
+# CONFIG_PSTORE_CONSOLE is not set
+CONFIG_PSTORE_PMSG=y
+# CONFIG_PSTORE_FTRACE is not set
+CONFIG_PSTORE_RAM=m
+CONFIG_PSTORE_ZONE=m
+CONFIG_PSTORE_BLK=m
+CONFIG_PSTORE_BLK_BLKDEV=""
+CONFIG_PSTORE_BLK_KMSG_SIZE=64
+CONFIG_PSTORE_BLK_MAX_REASON=2
+CONFIG_PSTORE_BLK_PMSG_SIZE=64
+CONFIG_SYSV_FS=m
+CONFIG_UFS_FS=m
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_UFS_DEBUG is not set
+CONFIG_EROFS_FS=m
+# CONFIG_EROFS_FS_DEBUG is not set
+CONFIG_EROFS_FS_XATTR=y
+CONFIG_EROFS_FS_POSIX_ACL=y
+CONFIG_EROFS_FS_SECURITY=y
+CONFIG_EROFS_FS_BACKED_BY_FILE=y
+CONFIG_EROFS_FS_ZIP=y
+CONFIG_EROFS_FS_ZIP_LZMA=y
+CONFIG_EROFS_FS_ZIP_DEFLATE=y
+CONFIG_EROFS_FS_ZIP_ZSTD=y
+CONFIG_EROFS_FS_ZIP_ACCEL=y
+CONFIG_EROFS_FS_PCPU_KTHREAD=y
+# CONFIG_EROFS_FS_PCPU_KTHREAD_HIPRI is not set
+# CONFIG_EROFS_FS_ONDEMAND is not set
+CONFIG_VBOXSF_FS=m
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V2=m
+CONFIG_NFS_V3=m
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=m
+CONFIG_NFS_SWAP=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_PNFS_FILE_LAYOUT=m
+CONFIG_PNFS_BLOCK=m
+CONFIG_PNFS_FLEXFILE_LAYOUT=m
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
+CONFIG_NFS_V4_1_MIGRATION=y
+CONFIG_NFS_FSCACHE=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFS_DISABLE_UDP_SUPPORT=y
+CONFIG_NFS_V4_2_READ_PLUS=y
+CONFIG_NFSD=m
+# CONFIG_NFSD_V2 is not set
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_NFSD_PNFS=y
+CONFIG_NFSD_BLOCKLAYOUT=y
+CONFIG_NFSD_SCSILAYOUT=y
+CONFIG_NFSD_FLEXFILELAYOUT=y
+CONFIG_NFSD_V4_2_INTER_SSC=y
+# CONFIG_NFSD_LEGACY_CLIENT_TRACKING is not set
+CONFIG_NFSD_V4_DELEG_TIMESTAMPS=y
+CONFIG_NFS_LOCALIO=y
+CONFIG_NFSD_V4_SECURITY_LABEL=y
+CONFIG_GRACE_PERIOD=m
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_NFS_V4_2_SSC_HELPER=y
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_GSS=m
+CONFIG_SUNRPC_BACKCHANNEL=y
+CONFIG_SUNRPC_SWAP=y
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_RPCSEC_GSS_KRB5_KUNIT_TEST is not set
+CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y
+CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y
+CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y
+# CONFIG_SUNRPC_DEBUG is not set
+CONFIG_SUNRPC_XPRT_RDMA=m
+# CONFIG_CEPH_FS is not set
+CONFIG_CIFS=m
+CONFIG_CIFS_STATS2=y
+CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
+CONFIG_CIFS_UPCALL=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+# CONFIG_CIFS_DEBUG is not set
+CONFIG_CIFS_DFS_UPCALL=y
+CONFIG_CIFS_SWN_UPCALL=y
+# CONFIG_CIFS_SMB_DIRECT is not set
+CONFIG_CIFS_FSCACHE=y
+CONFIG_CIFS_COMPRESSION=y
+CONFIG_SMB_SERVER=m
+CONFIG_SMB_SERVER_SMBDIRECT=y
+CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
+CONFIG_SMB_SERVER_KERBEROS5=y
+CONFIG_SMBFS=m
+CONFIG_CODA_FS=m
+CONFIG_AFS_FS=m
+# CONFIG_AFS_DEBUG is not set
+CONFIG_AFS_FSCACHE=y
+# CONFIG_AFS_DEBUG_CURSOR is not set
+CONFIG_9P_FS=m
+CONFIG_9P_FSCACHE=y
+CONFIG_9P_FS_POSIX_ACL=y
+CONFIG_9P_FS_SECURITY=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_MAC_ROMAN=m
+CONFIG_NLS_MAC_CELTIC=m
+CONFIG_NLS_MAC_CENTEURO=m
+CONFIG_NLS_MAC_CROATIAN=m
+CONFIG_NLS_MAC_CYRILLIC=m
+CONFIG_NLS_MAC_GAELIC=m
+CONFIG_NLS_MAC_GREEK=m
+CONFIG_NLS_MAC_ICELAND=m
+CONFIG_NLS_MAC_INUIT=m
+CONFIG_NLS_MAC_ROMANIAN=m
+CONFIG_NLS_MAC_TURKISH=m
+CONFIG_NLS_UTF8=m
+CONFIG_NLS_UCS2_UTILS=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+CONFIG_UNICODE=y
+CONFIG_UNICODE_NORMALIZATION_SELFTEST=m
+CONFIG_IO_WQ=y
+# end of File systems
+CONFIG_SWAP=y
+CONFIG_ZSWAP=y
+# CONFIG_ZSWAP_DEFAULT_ON is not set
+CONFIG_ZSWAP_EXCLUSIVE_LOADS_DEFAULT_ON=y
+CONFIG_ZSWAP_SHRINKER_DEFAULT_ON=y
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
+# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
+CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
+CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
+CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
+# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD_DEPRECATED is not set
+# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
+CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
+CONFIG_ZBUD=y
+# CONFIG_Z3FOLD_DEPRECATED is not set
+CONFIG_ZSMALLOC=y
+# CONFIG_ZSMALLOC_STAT is not set
+CONFIG_ZSMALLOC_CHAIN_SIZE=8
diff --git a/firmware.fragment b/firmware.fragment
new file mode 100644
index 0000000..3e80882
--- /dev/null
+++ b/firmware.fragment
@@ -0,0 +1,3 @@
+CONFIG_FWCTL=m
+CONFIG_FWCTL_MLX5=m
+CONFIG_FWCTL_PDS=m
diff --git a/fix_virtualbox.patch b/fix_virtualbox.patch
deleted file mode 100644
index da706e2..0000000
--- a/fix_virtualbox.patch
+++ /dev/null
@@ -1,11 +0,0 @@
-diff -up linux-5.13/mm/vmalloc.c.30~ linux-5.13/mm/vmalloc.c
---- linux-5.13/mm/vmalloc.c.30~	2021-06-30 02:05:21.596002648 +0200
-+++ linux-5.13/mm/vmalloc.c	2021-06-30 02:07:22.121226062 +0200
-@@ -2388,6 +2388,7 @@ struct vm_struct *__get_vm_area_caller(u
- 	return __get_vm_area_node(size, 1, PAGE_SHIFT, flags, start, end,
- 				  NUMA_NO_NODE, GFP_KERNEL, caller);
- }
-+EXPORT_SYMBOL(__get_vm_area_caller);
- 
- /**
-  * get_vm_area - reserve a contiguous kernel virtual area
diff --git a/framer.fragment b/framer.fragment
new file mode 100644
index 0000000..0440eaa
--- /dev/null
+++ b/framer.fragment
@@ -0,0 +1,2 @@
+CONFIG_FRAMER=m
+CONFIG_FRAMER_PEF2256=m
diff --git a/gcc-plugins.fragment b/gcc-plugins.fragment
new file mode 100644
index 0000000..0199eff
--- /dev/null
+++ b/gcc-plugins.fragment
@@ -0,0 +1,8 @@
+CONFIG_GCC_PLUGINS=y
+# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
+# CONFIG_GCC_PLUGIN_STACKLEAK is not set
+# CONFIG_RANDSTRUCT_NONE is not set
+# CONFIG_RANDSTRUCT_FULL is not set
+CONFIG_RANDSTRUCT_PERFORMANCE=y
+# CONFIG_READABLE_ASM is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
diff --git a/general-fix-inno-usb2-phy-init.patch b/general-fix-inno-usb2-phy-init.patch
deleted file mode 100644
index dd5abdf..0000000
--- a/general-fix-inno-usb2-phy-init.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From e4cd72bcf2b4581122d065c2854fdb6be4b19bc3 Mon Sep 17 00:00:00 2001
-From: Paolo Sabatino <paolo.sabatino@gmail.com>
-Date: Mon, 22 Aug 2022 20:51:22 +0000
-Subject: [PATCH] remove usb2phy extcon initialization causing kernel oops
-
----
- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 5 -----
- 1 file changed, 5 deletions(-)
-
-diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-index e6ededc51..bfb2546e4 100644
---- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
-@@ -1167,11 +1167,6 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
- 			goto out;
- 		}
- 
--		if (!of_property_read_bool(rphy->dev->of_node, "extcon")) {
--			/* do initial sync of usb state */
--			id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
--			extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
--		}
- 	}
- 
- out:
--- 
-2.34.1
-
diff --git a/general-increasing_DMA_block_memory_allocation_to_2048.patch b/general-increasing_DMA_block_memory_allocation_to_2048.patch
index fc6c248..fbf8f2c 100644
--- a/general-increasing_DMA_block_memory_allocation_to_2048.patch
+++ b/general-increasing_DMA_block_memory_allocation_to_2048.patch
@@ -1,21 +1,12 @@
-diff --git a/kernel/dma/pool.c b/kernel/dma/pool.c
-index 6bc74a2d5..e3827da51 100644
---- a/kernel/dma/pool.c
-+++ b/kernel/dma/pool.c
-@@ -164,13 +164,11 @@ static int __init dma_atomic_pool_init(void)
- 	int ret = 0;
- 
- 	/*
--	 * If coherent_pool was not used on the command line, default the pool
--	 * sizes to 128KB per 1GB of memory, min 128KB, max MAX_ORDER-1.
-+	 * Always use 2MiB as default pool size.
-+	 * See: https://forum.armbian.com/topic/4811-uas-mainline-kernel-coherent-pool-memory-size/
- 	 */
+diff -up linux-6.4/kernel/dma/pool.c.40~ linux-6.4/kernel/dma/pool.c
+--- linux-6.4/kernel/dma/pool.c.40~	2023-06-27 13:38:23.032647398 +0200
++++ linux-6.4/kernel/dma/pool.c	2023-06-27 13:41:36.204933529 +0200
+@@ -195,7 +195,7 @@ static int __init dma_atomic_pool_init(v
  	if (!atomic_pool_size) {
--		unsigned long pages = totalram_pages() / (SZ_1G / SZ_128K);
--		pages = min_t(unsigned long, pages, MAX_ORDER_NR_PAGES);
+ 		unsigned long pages = totalram_pages() / (SZ_1G / SZ_128K);
+ 		pages = min_t(unsigned long, pages, MAX_ORDER_NR_PAGES);
 -		atomic_pool_size = max_t(size_t, pages << PAGE_SHIFT, SZ_128K);
-+		atomic_pool_size = SZ_2M;
++		atomic_pool_size = max_t(size_t, pages << PAGE_SHIFT, SZ_2M);
  	}
  	INIT_WORK(&atomic_pool_work, atomic_pool_work_fn);
  
diff --git a/general-legacy-rockchip-hwrng.patch b/general-legacy-rockchip-hwrng.patch
deleted file mode 100644
index f4fd5b9..0000000
--- a/general-legacy-rockchip-hwrng.patch
+++ /dev/null
@@ -1,393 +0,0 @@
-diff -Naur a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
---- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi	2022-10-02 21:09:07.000000000 +0000
-+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi	2022-10-29 14:18:29.652921824 +0000
-@@ -694,6 +694,21 @@
- 		status = "disabled";
- 	};
- 
-+	rng: rng@ff2f0000 {
-+		compatible = "rockchip,cryptov2-rng";
-+		reg = <0x0 0xff2f0000 0x0 0x4000>;
-+		clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
-+			<&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
-+		clock-names = "clk_crypto", "clk_crypto_apk",
-+			"aclk_crypto", "hclk_crypto";
-+		assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
-+			<&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
-+		assigned-clock-rates = <150000000>, <150000000>,
-+			<200000000>, <100000000>;
-+		resets = <&cru SRST_CRYPTO>;
-+		reset-names = "reset";
-+	};
-+
- 	nfc: nand-controller@ff4b0000 {
- 		compatible = "rockchip,rk3308-nfc",
- 			     "rockchip,rv1108-nfc";
-diff -Naur a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
---- a/drivers/char/hw_random/Kconfig	2022-10-02 21:09:07.000000000 +0000
-+++ b/drivers/char/hw_random/Kconfig	2022-10-29 14:19:22.232641789 +0000
-@@ -372,6 +372,19 @@
- 
- 	  If unsure, say N.
- 
-+config HW_RANDOM_ROCKCHIP
-+	tristate "Rockchip Random Number Generator support"
-+	depends on ARCH_ROCKCHIP
-+	default HW_RANDOM
-+	help
-+	  This driver provides kernel-side support for the Random Number
-+	  Generator hardware found on Rockchip cpus.
-+
-+	  To compile this driver as a module, choose M here: the
-+	  module will be called rockchip-rng.
-+
-+	  If unsure, say Y.
-+
- config HW_RANDOM_PIC32
- 	tristate "Microchip PIC32 Random Number Generator support"
- 	depends on HW_RANDOM && MACH_PIC32
-diff -Naur a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
---- a/drivers/char/hw_random/Makefile	2022-10-02 21:09:07.000000000 +0000
-+++ b/drivers/char/hw_random/Makefile	2022-10-29 14:19:22.232641789 +0000
-@@ -34,6 +34,7 @@
- obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
- obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
- obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
-+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
- obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
- obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
- obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
-diff -Naur a/drivers/char/hw_random/rockchip-rng.c b/drivers/char/hw_random/rockchip-rng.c
---- a/drivers/char/hw_random/rockchip-rng.c	1970-01-01 00:00:00.000000000 +0000
-+++ b/drivers/char/hw_random/rockchip-rng.c	2022-10-29 14:19:22.242641736 +0000
-@@ -0,0 +1,330 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * rockchip-rng.c Random Number Generator driver for the Rockchip
-+ *
-+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
-+ * Author: Lin Jinhan <troy.lin@rock-chips.com>
-+ *
-+ */
-+#include <linux/clk.h>
-+#include <linux/hw_random.h>
-+#include <linux/iopoll.h>
-+#include <linux/module.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm_runtime.h>
-+
-+#define _SBF(s, v)	((v) << (s))
-+#define HIWORD_UPDATE(val, mask, shift) \
-+			((val) << (shift) | (mask) << ((shift) + 16))
-+
-+#define ROCKCHIP_AUTOSUSPEND_DELAY		100
-+#define ROCKCHIP_POLL_PERIOD_US			100
-+#define ROCKCHIP_POLL_TIMEOUT_US		10000
-+#define RK_MAX_RNG_BYTE				(32)
-+
-+#define CRYPTO_V1_CTRL				0x0008
-+#define CRYPTO_V1_RNG_START			BIT(8)
-+#define CRYPTO_V1_RNG_FLUSH			BIT(9)
-+#define CRYPTO_V1_TRNG_CTRL			0x0200
-+#define CRYPTO_V1_OSC_ENABLE			BIT(16)
-+#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x)		(x)
-+#define CRYPTO_V1_TRNG_DOUT_0			0x0204
-+
-+#define CRYPTO_V2_RNG_CTL			0x0400
-+#define CRYPTO_V2_RNG_64_BIT_LEN		_SBF(4, 0x00)
-+#define CRYPTO_V2_RNG_128_BIT_LEN		_SBF(4, 0x01)
-+#define CRYPTO_V2_RNG_192_BIT_LEN		_SBF(4, 0x02)
-+#define CRYPTO_V2_RNG_256_BIT_LEN		_SBF(4, 0x03)
-+#define CRYPTO_V2_RNG_FATESY_SOC_RING		_SBF(2, 0x00)
-+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0		_SBF(2, 0x01)
-+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1		_SBF(2, 0x02)
-+#define CRYPTO_V2_RNG_SLOWEST_SOC_RING		_SBF(2, 0x03)
-+#define CRYPTO_V2_RNG_ENABLE			BIT(1)
-+#define CRYPTO_V2_RNG_START			BIT(0)
-+#define CRYPTO_V2_RNG_SAMPLE_CNT		0x0404
-+#define CRYPTO_V2_RNG_DOUT_0			0x0410
-+
-+struct rk_rng_soc_data {
-+	const char * const *clks;
-+	int clks_num;
-+	int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
-+};
-+
-+struct rk_rng {
-+	struct device		*dev;
-+	struct hwrng		rng;
-+	void __iomem		*mem;
-+	struct rk_rng_soc_data	*soc_data;
-+	u32			clk_num;
-+	struct clk_bulk_data	*clk_bulks;
-+};
-+
-+static const char * const rk_rng_v1_clks[] = {
-+	"hclk_crypto",
-+	"clk_crypto",
-+};
-+
-+static const char * const rk_rng_v2_clks[] = {
-+	"hclk_crypto",
-+	"aclk_crypto",
-+	"clk_crypto",
-+	"clk_crypto_apk",
-+};
-+
-+static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
-+{
-+	__raw_writel(val, rng->mem + offset);
-+}
-+
-+static u32 rk_rng_readl(struct rk_rng *rng, u32 offset)
-+{
-+	return __raw_readl(rng->mem + offset);
-+}
-+
-+static int rk_rng_init(struct hwrng *rng)
-+{
-+	int ret;
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+	ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
-+	if (ret < 0) {
-+		dev_err(rk_rng->dev, "failed to enable clks %d\n", ret);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static void rk_rng_cleanup(struct hwrng *rng)
-+{
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+	clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
-+}
-+
-+static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
-+			     size_t size)
-+{
-+	u32 i, sample;
-+
-+	for (i = 0; i < size; i += 4) {
-+		sample = rk_rng_readl(rng, offset + i);
-+		memcpy(buf + i, &sample, sizeof(sample));
-+	}
-+}
-+
-+static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-+{
-+	int ret = 0;
-+	u32 reg_ctrl = 0;
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+	ret = pm_runtime_get_sync(rk_rng->dev);
-+	if (ret < 0) {
-+		pm_runtime_put_noidle(rk_rng->dev);
-+		return ret;
-+	}
-+
-+	/* enable osc_ring to get entropy, sample period is set as 100 */
-+	reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
-+	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
-+
-+	reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0);
-+
-+	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);
-+
-+	ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V1_CTRL, reg_ctrl,
-+				 !(reg_ctrl & CRYPTO_V1_RNG_START),
-+				 ROCKCHIP_POLL_PERIOD_US,
-+				 ROCKCHIP_POLL_TIMEOUT_US);
-+	if (ret < 0)
-+		goto out;
-+
-+	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
-+
-+	rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret);
-+
-+out:
-+	/* close TRNG */
-+	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
-+		      CRYPTO_V1_CTRL);
-+
-+	pm_runtime_mark_last_busy(rk_rng->dev);
-+	pm_runtime_put_sync_autosuspend(rk_rng->dev);
-+
-+	return ret;
-+}
-+
-+static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-+{
-+	int ret = 0;
-+	u32 reg_ctrl = 0;
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+	ret = pm_runtime_get_sync(rk_rng->dev);
-+	if (ret < 0) {
-+		pm_runtime_put_noidle(rk_rng->dev);
-+		return ret;
-+	}
-+
-+	/* enable osc_ring to get entropy, sample period is set as 100 */
-+	rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
-+
-+	reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN;
-+	reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
-+	reg_ctrl |= CRYPTO_V2_RNG_ENABLE;
-+	reg_ctrl |= CRYPTO_V2_RNG_START;
-+
-+	rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
-+			CRYPTO_V2_RNG_CTL);
-+
-+	ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl,
-+				 !(reg_ctrl & CRYPTO_V2_RNG_START),
-+				 ROCKCHIP_POLL_PERIOD_US,
-+				 ROCKCHIP_POLL_TIMEOUT_US);
-+	if (ret < 0)
-+		goto out;
-+
-+	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
-+
-+	rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret);
-+
-+out:
-+	/* close TRNG */
-+	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
-+
-+	pm_runtime_mark_last_busy(rk_rng->dev);
-+	pm_runtime_put_sync_autosuspend(rk_rng->dev);
-+
-+	return ret;
-+}
-+
-+static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
-+	.clks_num = ARRAY_SIZE(rk_rng_v1_clks),
-+	.clks = rk_rng_v1_clks,
-+	.rk_rng_read = rk_rng_v1_read,
-+};
-+
-+static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
-+	.clks_num = ARRAY_SIZE(rk_rng_v2_clks),
-+	.clks = rk_rng_v2_clks,
-+	.rk_rng_read = rk_rng_v2_read,
-+};
-+
-+static const struct of_device_id rk_rng_dt_match[] = {
-+	{
-+		.compatible = "rockchip,cryptov1-rng",
-+		.data = (void *)&rk_rng_v1_soc_data,
-+	},
-+	{
-+		.compatible = "rockchip,cryptov2-rng",
-+		.data = (void *)&rk_rng_v2_soc_data,
-+	},
-+	{ },
-+};
-+
-+MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
-+
-+static int rk_rng_probe(struct platform_device *pdev)
-+{
-+	int i;
-+	int ret;
-+	struct rk_rng *rk_rng;
-+	struct device_node *np = pdev->dev.of_node;
-+	const struct of_device_id *match;
-+
-+	rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
-+	if (!rk_rng)
-+		return -ENOMEM;
-+
-+	match = of_match_node(rk_rng_dt_match, np);
-+	rk_rng->soc_data = (struct rk_rng_soc_data *)match->data;
-+
-+	rk_rng->dev = &pdev->dev;
-+	rk_rng->rng.name    = "rockchip";
-+#ifndef CONFIG_PM
-+	rk_rng->rng.init    = rk_rng_init;
-+	rk_rng->rng.cleanup = rk_rng_cleanup,
-+#endif
-+	rk_rng->rng.read    = rk_rng->soc_data->rk_rng_read;
-+	rk_rng->rng.quality = 1024;
-+
-+	rk_rng->clk_bulks =
-+		devm_kzalloc(&pdev->dev, sizeof(*rk_rng->clk_bulks) *
-+			     rk_rng->soc_data->clks_num, GFP_KERNEL);
-+
-+	rk_rng->clk_num = rk_rng->soc_data->clks_num;
-+
-+	for (i = 0; i < rk_rng->soc_data->clks_num; i++)
-+		rk_rng->clk_bulks[i].id = rk_rng->soc_data->clks[i];
-+
-+	rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
-+	if (IS_ERR(rk_rng->mem))
-+		return PTR_ERR(rk_rng->mem);
-+
-+	ret = devm_clk_bulk_get(&pdev->dev, rk_rng->clk_num,
-+				rk_rng->clk_bulks);
-+	if (ret) {
-+		dev_err(&pdev->dev, "failed to get clks property\n");
-+		return ret;
-+	}
-+
-+	platform_set_drvdata(pdev, rk_rng);
-+
-+	pm_runtime_set_autosuspend_delay(&pdev->dev,
-+					ROCKCHIP_AUTOSUSPEND_DELAY);
-+	pm_runtime_use_autosuspend(&pdev->dev);
-+	pm_runtime_enable(&pdev->dev);
-+
-+	ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng);
-+	if (ret) {
-+		pm_runtime_dont_use_autosuspend(&pdev->dev);
-+		pm_runtime_disable(&pdev->dev);
-+	}
-+
-+	return ret;
-+}
-+
-+#ifdef CONFIG_PM
-+static int rk_rng_runtime_suspend(struct device *dev)
-+{
-+	struct rk_rng *rk_rng = dev_get_drvdata(dev);
-+
-+	rk_rng_cleanup(&rk_rng->rng);
-+
-+	return 0;
-+}
-+
-+static int rk_rng_runtime_resume(struct device *dev)
-+{
-+	struct rk_rng *rk_rng = dev_get_drvdata(dev);
-+
-+	return rk_rng_init(&rk_rng->rng);
-+}
-+
-+static const struct dev_pm_ops rk_rng_pm_ops = {
-+	SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
-+				rk_rng_runtime_resume, NULL)
-+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
-+				pm_runtime_force_resume)
-+};
-+#endif
-+
-+static struct platform_driver rk_rng_driver = {
-+	.driver	= {
-+		.name	= "rockchip-rng",
-+#ifdef CONFIG_PM
-+		.pm	= &rk_rng_pm_ops,
-+#endif
-+		.of_match_table = rk_rng_dt_match,
-+	},
-+	.probe	= rk_rng_probe,
-+};
-+
-+module_platform_driver(rk_rng_driver);
-+
-+MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver");
-+MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
-+MODULE_LICENSE("GPL v2");
diff --git a/general-legacy-rockchip-hwrng_5.10.patch b/general-legacy-rockchip-hwrng_5.10.patch
deleted file mode 100644
index 5cf7349..0000000
--- a/general-legacy-rockchip-hwrng_5.10.patch
+++ /dev/null
@@ -1,495 +0,0 @@
-diff --git a/drivers/char/hw_random/rockchip-rng.c b/drivers/char/hw_random/rockchip-rng.c
-index c0121f1f5..13503c54f 100644
---- a/drivers/char/hw_random/rockchip-rng.c
-+++ b/drivers/char/hw_random/rockchip-rng.c
-@@ -21,18 +21,24 @@
- 
- #define ROCKCHIP_AUTOSUSPEND_DELAY		100
- #define ROCKCHIP_POLL_PERIOD_US			100
--#define ROCKCHIP_POLL_TIMEOUT_US		10000
-+#define ROCKCHIP_POLL_TIMEOUT_US		50000
- #define RK_MAX_RNG_BYTE				(32)
- 
-+/* start of CRYPTO V1 register define */
- #define CRYPTO_V1_CTRL				0x0008
- #define CRYPTO_V1_RNG_START			BIT(8)
- #define CRYPTO_V1_RNG_FLUSH			BIT(9)
-+
- #define CRYPTO_V1_TRNG_CTRL			0x0200
- #define CRYPTO_V1_OSC_ENABLE			BIT(16)
- #define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x)		(x)
-+
- #define CRYPTO_V1_TRNG_DOUT_0			0x0204
-+/* end of CRYPTO V1 register define */
- 
--#define CRYPTO_V2_RNG_CTL			0x0400
-+/* start of CRYPTO V2 register define */
-+#define CRYPTO_V2_RNG_DEFAULT_OFFSET		0x0400
-+#define CRYPTO_V2_RNG_CTL			0x0
- #define CRYPTO_V2_RNG_64_BIT_LEN		_SBF(4, 0x00)
- #define CRYPTO_V2_RNG_128_BIT_LEN		_SBF(4, 0x01)
- #define CRYPTO_V2_RNG_192_BIT_LEN		_SBF(4, 0x02)
-@@ -43,12 +49,48 @@
- #define CRYPTO_V2_RNG_SLOWEST_SOC_RING		_SBF(2, 0x03)
- #define CRYPTO_V2_RNG_ENABLE			BIT(1)
- #define CRYPTO_V2_RNG_START			BIT(0)
--#define CRYPTO_V2_RNG_SAMPLE_CNT		0x0404
--#define CRYPTO_V2_RNG_DOUT_0			0x0410
-+#define CRYPTO_V2_RNG_SAMPLE_CNT		0x0004
-+#define CRYPTO_V2_RNG_DOUT_0			0x0010
-+/* end of CRYPTO V2 register define */
-+
-+/* start of TRNG_V1 register define */
-+/* TRNG is no longer subordinate to the Crypto module */
-+#define TRNG_V1_CTRL				0x0000
-+#define TRNG_V1_CTRL_NOP			_SBF(0, 0x00)
-+#define TRNG_V1_CTRL_RAND			_SBF(0, 0x01)
-+#define TRNG_V1_CTRL_SEED			_SBF(0, 0x02)
-+
-+#define TRNG_V1_STAT				0x0004
-+#define TRNG_V1_STAT_SEEDED			BIT(9)
-+#define TRNG_V1_STAT_GENERATING			BIT(30)
-+#define TRNG_V1_STAT_RESEEDING			BIT(31)
-+
-+#define TRNG_V1_MODE				0x0008
-+#define TRNG_V1_MODE_128_BIT			_SBF(3, 0x00)
-+#define TRNG_V1_MODE_256_BIT			_SBF(3, 0x01)
-+
-+#define TRNG_V1_IE				0x0010
-+#define TRNG_V1_IE_GLBL_EN			BIT(31)
-+#define TRNG_V1_IE_SEED_DONE_EN			BIT(1)
-+#define TRNG_V1_IE_RAND_RDY_EN			BIT(0)
-+
-+#define TRNG_V1_ISTAT				0x0014
-+#define TRNG_V1_ISTAT_RAND_RDY			BIT(0)
-+
-+/* RAND0 ~ RAND7 */
-+#define TRNG_V1_RAND0				0x0020
-+#define TRNG_V1_RAND7				0x003C
-+
-+#define TRNG_V1_AUTO_RQSTS			0x0060
-+
-+#define TRNG_V1_VERSION				0x00F0
-+#define TRNG_v1_VERSION_CODE			0x46bc
-+/* end of TRNG_V1 register define */
- 
- struct rk_rng_soc_data {
--	const char * const *clks;
--	int clks_num;
-+	u32 default_offset;
-+
-+	int (*rk_rng_init)(struct hwrng *rng);
- 	int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
- };
- 
-@@ -57,22 +99,10 @@ struct rk_rng {
- 	struct hwrng		rng;
- 	void __iomem		*mem;
- 	struct rk_rng_soc_data	*soc_data;
--	u32			clk_num;
-+	int			clk_num;
- 	struct clk_bulk_data	*clk_bulks;
- };
- 
--static const char * const rk_rng_v1_clks[] = {
--	"hclk_crypto",
--	"clk_crypto",
--};
--
--static const char * const rk_rng_v2_clks[] = {
--	"hclk_crypto",
--	"aclk_crypto",
--	"clk_crypto",
--	"clk_crypto_apk",
--};
--
- static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
- {
- 	__raw_writel(val, rng->mem + offset);
-@@ -88,6 +118,8 @@ static int rk_rng_init(struct hwrng *rng)
- 	int ret;
- 	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
- 
-+	dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n");
-+
- 	ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
- 	if (ret < 0) {
- 		dev_err(rk_rng->dev, "failed to enable clks %d\n", ret);
-@@ -101,32 +133,57 @@ static void rk_rng_cleanup(struct hwrng *rng)
- {
- 	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
- 
-+	dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n");
- 	clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
- }
- 
-+static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-+{
-+	int ret;
-+	int read_len = 0;
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+	if (!rk_rng->soc_data->rk_rng_read)
-+		return -EFAULT;
-+
-+	ret = pm_runtime_get_sync(rk_rng->dev);
-+	if (ret < 0) {
-+		pm_runtime_put_noidle(rk_rng->dev);
-+		return ret;
-+	}
-+
-+	ret = 0;
-+	while (max > ret) {
-+		read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret,
-+							 max - ret, wait);
-+		if (read_len < 0) {
-+			ret = read_len;
-+			break;
-+		}
-+		ret += read_len;
-+	}
-+
-+	pm_runtime_mark_last_busy(rk_rng->dev);
-+	pm_runtime_put_sync_autosuspend(rk_rng->dev);
-+
-+	return ret;
-+}
-+
- static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
- 			     size_t size)
- {
--	u32 i, sample;
-+	u32 i;
- 
--	for (i = 0; i < size; i += 4) {
--		sample = rk_rng_readl(rng, offset + i);
--		memcpy(buf + i, &sample, sizeof(sample));
--	}
-+	for (i = 0; i < size; i += 4)
-+		*(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
- }
- 
--static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-+static int rk_crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
- {
- 	int ret = 0;
- 	u32 reg_ctrl = 0;
- 	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
- 
--	ret = pm_runtime_get_sync(rk_rng->dev);
--	if (ret < 0) {
--		pm_runtime_put_noidle(rk_rng->dev);
--		return ret;
--	}
--
- 	/* enable osc_ring to get entropy, sample period is set as 100 */
- 	reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
- 	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
-@@ -135,10 +192,12 @@ static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
- 
- 	rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);
- 
--	ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V1_CTRL, reg_ctrl,
--				 !(reg_ctrl & CRYPTO_V1_RNG_START),
--				 ROCKCHIP_POLL_PERIOD_US,
--				 ROCKCHIP_POLL_TIMEOUT_US);
-+	ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
-+				!(reg_ctrl & CRYPTO_V1_RNG_START),
-+				ROCKCHIP_POLL_PERIOD_US,
-+				ROCKCHIP_POLL_TIMEOUT_US, false,
-+				rk_rng, CRYPTO_V1_CTRL);
-+
- 	if (ret < 0)
- 		goto out;
- 
-@@ -151,24 +210,15 @@ static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
- 	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
- 		      CRYPTO_V1_CTRL);
- 
--	pm_runtime_mark_last_busy(rk_rng->dev);
--	pm_runtime_put_sync_autosuspend(rk_rng->dev);
--
- 	return ret;
- }
- 
--static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-+static int rk_crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
- {
- 	int ret = 0;
- 	u32 reg_ctrl = 0;
- 	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
- 
--	ret = pm_runtime_get_sync(rk_rng->dev);
--	if (ret < 0) {
--		pm_runtime_put_noidle(rk_rng->dev);
--		return ret;
--	}
--
- 	/* enable osc_ring to get entropy, sample period is set as 100 */
- 	rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
- 
-@@ -178,12 +228,13 @@ static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
- 	reg_ctrl |= CRYPTO_V2_RNG_START;
- 
- 	rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
--			CRYPTO_V2_RNG_CTL);
-+		      CRYPTO_V2_RNG_CTL);
- 
--	ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl,
--				 !(reg_ctrl & CRYPTO_V2_RNG_START),
--				 ROCKCHIP_POLL_PERIOD_US,
--				 ROCKCHIP_POLL_TIMEOUT_US);
-+	ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
-+				!(reg_ctrl & CRYPTO_V2_RNG_START),
-+				ROCKCHIP_POLL_PERIOD_US,
-+				ROCKCHIP_POLL_TIMEOUT_US, false,
-+				rk_rng, CRYPTO_V2_RNG_CTL);
- 	if (ret < 0)
- 		goto out;
- 
-@@ -195,32 +246,141 @@ static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
- 	/* close TRNG */
- 	rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
- 
-+	return ret;
-+}
-+
-+static int rk_trng_v1_init(struct hwrng *rng)
-+{
-+	int ret;
-+	uint32_t auto_reseed_cnt = 1000;
-+	uint32_t reg_ctrl, status, version;
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+	ret = pm_runtime_get_sync(rk_rng->dev);
-+	if (ret < 0) {
-+		pm_runtime_put_noidle(rk_rng->dev);
-+		return ret;
-+	}
-+
-+	version = rk_rng_readl(rk_rng, TRNG_V1_VERSION);
-+	if (version != TRNG_v1_VERSION_CODE) {
-+		dev_err(rk_rng->dev,
-+			"wrong trng version, expected = %08x, actual = %08x\n",
-+			TRNG_V1_VERSION, version);
-+		ret = -EFAULT;
-+		goto exit;
-+	}
-+
-+	status = rk_rng_readl(rk_rng, TRNG_V1_STAT);
-+
-+	/* TRNG should wait RAND_RDY triggered if it is busy or not seeded */
-+	if (!(status & TRNG_V1_STAT_SEEDED) ||
-+	    (status & TRNG_V1_STAT_GENERATING) ||
-+	    (status & TRNG_V1_STAT_RESEEDING)) {
-+		uint32_t mask = TRNG_V1_STAT_SEEDED |
-+				TRNG_V1_STAT_GENERATING |
-+				TRNG_V1_STAT_RESEEDING;
-+
-+		udelay(10);
-+
-+		/* wait for GENERATING and RESEEDING flag to clear */
-+		read_poll_timeout(rk_rng_readl, reg_ctrl,
-+				  (reg_ctrl & mask) == TRNG_V1_STAT_SEEDED,
-+				  ROCKCHIP_POLL_PERIOD_US,
-+				  ROCKCHIP_POLL_TIMEOUT_US, false,
-+				  rk_rng, TRNG_V1_STAT);
-+	}
-+
-+	/* clear ISTAT flag because trng may auto reseeding when power on */
-+	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
-+	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
-+
-+	/* auto reseed after (auto_reseed_cnt * 16) byte rand generate */
-+	rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS);
-+
-+	ret = 0;
-+exit:
- 	pm_runtime_mark_last_busy(rk_rng->dev);
- 	pm_runtime_put_sync_autosuspend(rk_rng->dev);
- 
- 	return ret;
- }
- 
--static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
--	.clks_num = ARRAY_SIZE(rk_rng_v1_clks),
--	.clks = rk_rng_v1_clks,
--	.rk_rng_read = rk_rng_v1_read,
-+static int rk_trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-+{
-+	int ret = 0;
-+	u32 reg_ctrl = 0;
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+
-+	/* clear ISTAT anyway */
-+	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
-+	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
-+
-+	/* generate 256bit random */
-+	rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE);
-+	rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL);
-+
-+	/*
-+	 * Generate2 56 bit random data will cost 1024 clock cycles.
-+	 * Estimated at 150M RNG module frequency, it takes 6.7 microseconds.
-+	 */
-+	udelay(10);
-+	reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
-+	if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) {
-+		/* wait RAND_RDY triggered */
-+		ret = read_poll_timeout(rk_rng_readl, reg_ctrl,
-+					(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY),
-+					ROCKCHIP_POLL_PERIOD_US,
-+					ROCKCHIP_POLL_TIMEOUT_US, false,
-+					rk_rng, TRNG_V1_ISTAT);
-+		if (ret < 0)
-+			goto out;
-+	}
-+
-+	ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
-+
-+	rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret);
-+
-+	/* clear all status flag */
-+	rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
-+out:
-+	/* close TRNG */
-+	rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL);
-+
-+	return ret;
-+}
-+
-+static const struct rk_rng_soc_data rk_crypto_v1_soc_data = {
-+	.default_offset = 0,
-+
-+	.rk_rng_read = rk_crypto_v1_read,
- };
- 
--static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
--	.clks_num = ARRAY_SIZE(rk_rng_v2_clks),
--	.clks = rk_rng_v2_clks,
--	.rk_rng_read = rk_rng_v2_read,
-+static const struct rk_rng_soc_data rk_crypto_v2_soc_data = {
-+	.default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET,
-+
-+	.rk_rng_read = rk_crypto_v2_read,
-+};
-+
-+static const struct rk_rng_soc_data rk_trng_v1_soc_data = {
-+	.default_offset = 0,
-+
-+	.rk_rng_init = rk_trng_v1_init,
-+	.rk_rng_read = rk_trng_v1_read,
- };
- 
- static const struct of_device_id rk_rng_dt_match[] = {
- 	{
- 		.compatible = "rockchip,cryptov1-rng",
--		.data = (void *)&rk_rng_v1_soc_data,
-+		.data = (void *)&rk_crypto_v1_soc_data,
- 	},
- 	{
- 		.compatible = "rockchip,cryptov2-rng",
--		.data = (void *)&rk_rng_v2_soc_data,
-+		.data = (void *)&rk_crypto_v2_soc_data,
-+	},
-+	{
-+		.compatible = "rockchip,trngv1",
-+		.data = (void *)&rk_trng_v1_soc_data,
- 	},
- 	{ },
- };
-@@ -229,12 +389,13 @@ MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
- 
- static int rk_rng_probe(struct platform_device *pdev)
- {
--	int i;
- 	int ret;
- 	struct rk_rng *rk_rng;
- 	struct device_node *np = pdev->dev.of_node;
- 	const struct of_device_id *match;
-+	resource_size_t map_size;
- 
-+	dev_dbg(&pdev->dev, "probing...\n");
- 	rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
- 	if (!rk_rng)
- 		return -ENOMEM;
-@@ -248,33 +409,37 @@ static int rk_rng_probe(struct platform_device *pdev)
- 	rk_rng->rng.init    = rk_rng_init;
- 	rk_rng->rng.cleanup = rk_rng_cleanup,
- #endif
--	rk_rng->rng.read    = rk_rng->soc_data->rk_rng_read;
--	rk_rng->rng.quality = 1024;
--
--	rk_rng->clk_bulks =
--		devm_kzalloc(&pdev->dev, sizeof(*rk_rng->clk_bulks) *
--			     rk_rng->soc_data->clks_num, GFP_KERNEL);
-+	rk_rng->rng.read    = rk_rng_read;
-+	rk_rng->rng.quality = 999;
- 
--	rk_rng->clk_num = rk_rng->soc_data->clks_num;
--
--	for (i = 0; i < rk_rng->soc_data->clks_num; i++)
--		rk_rng->clk_bulks[i].id = rk_rng->soc_data->clks[i];
--
--	rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
-+	rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size);
- 	if (IS_ERR(rk_rng->mem))
- 		return PTR_ERR(rk_rng->mem);
- 
--	ret = devm_clk_bulk_get(&pdev->dev, rk_rng->clk_num,
--				rk_rng->clk_bulks);
--	if (ret) {
-+	/* compatible with crypto v2 module */
-+	/*
-+	 * With old dtsi configurations, the RNG base was equal to the crypto
-+	 * base, so both drivers could not be enabled at the same time.
-+	 * RNG base = CRYPTO base + RNG offset
-+	 * (Since RK356X, RNG module is no longer belongs to CRYPTO module)
-+	 *
-+	 * With new dtsi configurations, CRYPTO regs is divided into two parts
-+	 * |---cipher---|---rng---|---pka---|, and RNG base is real RNG base.
-+	 * RNG driver and CRYPTO driver could be enabled at the same time.
-+	 */
-+	if (map_size > rk_rng->soc_data->default_offset)
-+		rk_rng->mem += rk_rng->soc_data->default_offset;
-+
-+	rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
-+	if (rk_rng->clk_num < 0) {
- 		dev_err(&pdev->dev, "failed to get clks property\n");
--		return ret;
-+		return -ENODEV;
- 	}
- 
- 	platform_set_drvdata(pdev, rk_rng);
- 
- 	pm_runtime_set_autosuspend_delay(&pdev->dev,
--					ROCKCHIP_AUTOSUSPEND_DELAY);
-+					 ROCKCHIP_AUTOSUSPEND_DELAY);
- 	pm_runtime_use_autosuspend(&pdev->dev);
- 	pm_runtime_enable(&pdev->dev);
- 
-@@ -284,6 +449,10 @@ static int rk_rng_probe(struct platform_device *pdev)
- 		pm_runtime_disable(&pdev->dev);
- 	}
- 
-+	/* for some platform need hardware operation when probe */
-+	if (rk_rng->soc_data->rk_rng_init)
-+		ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng);
-+
- 	return ret;
- }
- 
-@@ -306,10 +475,11 @@ static int rk_rng_runtime_resume(struct device *dev)
- 
- static const struct dev_pm_ops rk_rng_pm_ops = {
- 	SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
--				rk_rng_runtime_resume, NULL)
-+			   rk_rng_runtime_resume, NULL)
- 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
- 				pm_runtime_force_resume)
- };
-+
- #endif
- 
- static struct platform_driver rk_rng_driver = {
diff --git a/general-rk808-configurable-switch-voltage-steps.patch b/general-rk808-configurable-switch-voltage-steps.patch
index 0293515..b395528 100644
--- a/general-rk808-configurable-switch-voltage-steps.patch
+++ b/general-rk808-configurable-switch-voltage-steps.patch
@@ -1,7 +1,7 @@
-diff -up linux-5.14-rc1/drivers/regulator/rk808-regulator.c.39~ linux-5.14-rc1/drivers/regulator/rk808-regulator.c
---- linux-5.14-rc1/drivers/regulator/rk808-regulator.c.39~	2021-07-12 00:07:40.000000000 +0200
-+++ linux-5.14-rc1/drivers/regulator/rk808-regulator.c	2021-07-12 12:11:16.127005371 +0200
-@@ -156,6 +156,7 @@
+diff -up linux-6.13-rc1/drivers/regulator/rk808-regulator.c.44~ linux-6.13-rc1/drivers/regulator/rk808-regulator.c
+--- linux-6.13-rc1/drivers/regulator/rk808-regulator.c.44~	2024-12-01 23:28:56.000000000 +0100
++++ linux-6.13-rc1/drivers/regulator/rk808-regulator.c	2024-12-02 01:00:23.047359211 +0100
+@@ -207,6 +207,7 @@ struct rk8xx_register_bit {
  
  struct rk808_regulator_data {
  	struct gpio_desc *dvs_gpio[2];
@@ -9,7 +9,7 @@ diff -up linux-5.14-rc1/drivers/regulator/rk808-regulator.c.39~ linux-5.14-rc1/d
  };
  
  static const struct linear_range rk808_ldo3_voltage_ranges[] = {
-@@ -241,7 +242,8 @@ static int rk808_buck1_2_get_voltage_sel
+@@ -419,7 +420,8 @@ static int rk808_buck1_2_get_voltage_sel
  }
  
  static int rk808_buck1_2_i2c_set_voltage_sel(struct regulator_dev *rdev,
@@ -19,7 +19,7 @@ diff -up linux-5.14-rc1/drivers/regulator/rk808-regulator.c.39~ linux-5.14-rc1/d
  {
  	int ret, delta_sel;
  	unsigned int old_sel, tmp, val, mask = rdev->desc->vsel_mask;
-@@ -260,8 +262,8 @@ static int rk808_buck1_2_i2c_set_voltage
+@@ -438,8 +440,8 @@ static int rk808_buck1_2_i2c_set_voltage
  	 * the risk of overshoot. Put it into a multi-step, can effectively
  	 * avoid this problem, a step is 100mv here.
  	 */
@@ -30,7 +30,7 @@ diff -up linux-5.14-rc1/drivers/regulator/rk808-regulator.c.39~ linux-5.14-rc1/d
  		val = old_sel << (ffs(mask) - 1);
  		val |= tmp;
  
-@@ -295,12 +297,13 @@ static int rk808_buck1_2_set_voltage_sel
+@@ -473,12 +475,13 @@ static int rk808_buck1_2_set_voltage_sel
  	struct rk808_regulator_data *pdata = rdev_get_drvdata(rdev);
  	int id = rdev_get_id(rdev);
  	struct gpio_desc *gpio = pdata->dvs_gpio[id];
@@ -45,11 +45,11 @@ diff -up linux-5.14-rc1/drivers/regulator/rk808-regulator.c.39~ linux-5.14-rc1/d
  
  	gpio_level = gpiod_get_value(gpio);
  	if (gpio_level == 0) {
-@@ -1278,6 +1281,12 @@ static int rk808_regulator_dt_parse_pdat
- 				0 : tmp);
+@@ -1860,6 +1863,12 @@ static int rk808_regulator_dt_parse_pdat
+ 					 gpiod_is_active_low(pdata->dvs_gpio[i]) ? 0 : tmp);
  	}
  
-+	tmp = of_property_read_u32(client_dev->of_node, "max-buck-steps-per-change", &pdata->max_buck_steps_per_change);
++	tmp = of_property_read_u32(dev->of_node, "max-buck-steps-per-change", &pdata->max_buck_steps_per_change);
 +	if (tmp) {
 +		pdata->max_buck_steps_per_change = MAX_STEPS_ONE_TIME;
 +	}
diff --git a/generic-omv-defconfig b/generic-omv-defconfig
new file mode 100644
index 0000000..0f2e04b
--- /dev/null
+++ b/generic-omv-defconfig
@@ -0,0 +1,1221 @@
+CONFIG_ACPI_EC=y
+CONFIG_AD3530R=m
+CONFIG_AD3552R_HS=m
+CONFIG_AD7625=m
+CONFIG_AD7779=m
+CONFIG_AD8460=m
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_AF_RXRPC_IPV6=y
+CONFIG_AHCI_CEVA=m
+CONFIG_AIO=y
+CONFIG_AIR_EN8811H_PHY=m
+CONFIG_AIROHA_THERMAL=m
+CONFIG_AL_FIC=y
+CONFIG_ALS31300=m
+CONFIG_ALTERA_PR_IP_CORE_PLAT=m
+CONFIG_AMD_3D_VCACHE=m
+CONFIG_AMD_HSMP_ACPI=m
+CONFIG_AMD_HSMP_PLAT=m
+CONFIG_AMD_SBRMI_HWMON=y
+CONFIG_AMD_SBRMI_I2C=m
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
+CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
+CONFIG_ARCH_HAS_PTE_SPECIAL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM64_GCS=y
+CONFIG_ARM64_HAFT=y
+CONFIG_ARM_CCA_GUEST=m
+CONFIG_ARM_CCA_GUEST=y
+CONFIG_ARM_SMMU_V3_IOMMUFD=y
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ATA_BMDMA=y
+CONFIG_ATA_SFF=y
+CONFIG_ATH10K_AHB=y
+CONFIG_ATH12K_COREDUMP=y
+CONFIG_BACKLIGHT_LED=m
+CONFIG_BACKLIGHT_LM3509=m
+CONFIG_BACKLIGHT_TPS65217=m
+CONFIG_BALLOON_COMPACTION=y
+CONFIG_BASE_FULL=y
+CONFIG_BASE_SMALL=0
+CONFIG_BATTERY_ACT8945A=m
+CONFIG_BATTERY_CHAGALL=m
+CONFIG_BATTERY_CPCAP=m
+CONFIG_BATTERY_HUAWEI_GAOKUN=m
+CONFIG_BATTERY_MAX1720X=m
+CONFIG_BATTERY_QCOM_BATTMGR=m
+CONFIG_BCM2712_MIP=m
+CONFIG_BCMA_POSSIBLE=y
+CONFIG_BD957XMUF_WATCHDOG=m
+CONFIG_BD96801_WATCHDOG=m
+CONFIG_BIG_KEYS=y
+CONFIG_BINARY_PRINTF=y
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_SCRIPT=y
+CONFIG_BITREVERSE=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_WRITE_MOUNTED=y
+CONFIG_BLK_DEV=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_BLK_PM=y
+CONFIG_BLOCK=y
+CONFIG_BMI270_I2C=m
+CONFIG_BMI270_SPI=m
+CONFIG_BPF_JIT_ALWAYS_ON=y
+CONFIG_BPF_JIT=y
+CONFIG_BPF_SYSCALL=y
+CONFIG_BPF=y
+CONFIG_BUILDTIME_TABLE_SORT=y
+CONFIG_BUILTIN_MODULE_RANGES=y
+CONFIG_CACHESTAT_SYSCALL=y
+CONFIG_CAN_CTUCANFD_PLATFORM=m
+CONFIG_CAN_FLEXCAN=m
+CONFIG_CAN_GRCAN=m
+CONFIG_CC_HAS_ASM_INLINE=y
+CONFIG_CC_HAS_KASAN_GENERIC=y
+CONFIG_CC_HAS_SANCOV_TRACE_PC=y
+CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_CGBC_WDT=m
+CONFIG_CHARGER_BQ257XX=m
+CONFIG_CHARGER_DETECTOR_MAX14656=m
+CONFIG_CHARGER_MAX77650=m
+CONFIG_CHARGER_MAX77705=m
+CONFIG_CHARGER_MAX8971=m
+CONFIG_CHARGER_RK817=m
+CONFIG_CHARGER_TPS65217=m
+CONFIG_CHARGER_TWL6030=m
+CONFIG_CHARGER_UCS1002=m
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_CHROMEOS_OF_HW_PROBER=m
+CONFIG_CLK_FD_KUNIT_TEST=m
+CONFIG_CLK_FIXED_RATE_KUNIT_TEST=m
+CONFIG_CLK_GATE_KUNIT_TEST=m
+CONFIG_CLK_KUNIT_TEST=m
+CONFIG_CLK_LGM_CGU=y
+CONFIG_CLK_RENESAS_VBATTB=m
+CONFIG_CLZ_TAB=y
+CONFIG_COMMON_CLK_AXI_CLKGEN=m
+CONFIG_COMMON_CLK_BD718XX=m
+CONFIG_COMMON_CLK_CDCE706=m
+CONFIG_COMMON_CLK_CDCE925=m
+CONFIG_COMMON_CLK_CS2000_CP=m
+CONFIG_COMMON_CLK_FIXED_MMIO=y
+CONFIG_COMMON_CLK_LOCHNAGAR=m
+CONFIG_COMMON_CLK_MAX77686=m
+CONFIG_COMMON_CLK_MAX9485=m
+CONFIG_COMMON_CLK_MT6735_IMGSYS=m
+CONFIG_COMMON_CLK_MT6735=m
+CONFIG_COMMON_CLK_MT6735_MFGCFG=m
+CONFIG_COMMON_CLK_MT6735_VDECSYS=m
+CONFIG_COMMON_CLK_MT6735_VENCSYS=m
+CONFIG_COMMON_CLK_NPCM8XX=m
+CONFIG_COMMON_CLK_RK808=m
+CONFIG_COMMON_CLK_RS9_PCIE=m
+CONFIG_COMMON_CLK_S2MPS11=m
+CONFIG_COMMON_CLK_SI514=m
+CONFIG_COMMON_CLK_SI521XX=m
+CONFIG_COMMON_CLK_SI533=m
+CONFIG_COMMON_CLK_SI5341=m
+CONFIG_COMMON_CLK_SI5351=m
+CONFIG_COMMON_CLK_SI544=m
+CONFIG_COMMON_CLK_SI570=m
+CONFIG_COMMON_CLK_VC3=m
+CONFIG_COMMON_CLK_VC5=m
+CONFIG_COMMON_CLK_VC7=m
+CONFIG_COMMON_CLK_XLNX_CLKWZRD=m
+CONFIG_COMPACTION=y
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
+CONFIG_CONSOLE_LOGLEVEL_QUIET=4
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_COREDUMP=y
+CONFIG_CPCAP_ADC=m
+CONFIG_CPUFREQ_DT=m
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_FREQ_THERMAL=y
+CONFIG_CPUFREQ_VIRT=m
+CONFIG_CPU_IDLE_THERMAL=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPUSETS_V1=y
+CONFIG_CPUSETS=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRC16_KUNIT_TEST=m
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC32=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC_OPTIMIZATIONS=y
+CONFIG_CROS_EC_RPMSG=m
+CONFIG_CROS_EC_UCSI=m
+CONFIG_CROS_EC_VBC=m
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_AKCIPHER=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_BENCHMARK=m
+CONFIG_CRYPTO_DEV_CCREE=m
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_KPP2=y
+CONFIG_CRYPTO_KRB5ENC=m
+CONFIG_CRYPTO_KRB5=m
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_SKCIPHER2=y
+CONFIG_CRYPTO_SKCIPHER=y
+CONFIG_CRYPTO=y
+CONFIG_DA9062_THERMAL=m
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_ZSTD=y
+CONFIG_DEFAULT_INIT=""
+CONFIG_DEVMEM=y
+CONFIG_DEVPORT=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DEVTMPFS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DM_BIO_PRISON=m
+CONFIG_DM_BUFIO=m
+CONFIG_DMEM=y
+CONFIG_DM_PERSISTENT_DATA=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_VDO=m
+CONFIG_DQL=y
+CONFIG_DRM_ANALOGIX_ANX6345=m
+CONFIG_DRM_ANALOGIX_ANX7625=m
+CONFIG_DRM_ARCPGU=m
+CONFIG_DRM_CDNS_DSI_J721E=y
+CONFIG_DRM_CDNS_DSI=m
+CONFIG_DRM_CDNS_MHDP8546=m
+CONFIG_DRM_CHIPONE_ICN6211=m
+CONFIG_DRM_CHRONTEL_CH7033=m
+CONFIG_DRM_CROS_EC_ANX7688=m
+CONFIG_DRM_DISPLAY_CONNECTOR=m
+CONFIG_DRM_I2C_ADV7511_AUDIO=y
+CONFIG_DRM_I2C_ADV7511_CEC=y
+CONFIG_DRM_I2C_ADV7511=m
+CONFIG_DRM_ITE_IT6263=m
+CONFIG_DRM_ITE_IT6505=m
+CONFIG_DRM_ITE_IT66121=m
+CONFIG_DRM_KOMEDA=m
+CONFIG_DRM_LOGICVC=m
+CONFIG_DRM_LONTIUM_LT8912B=m
+CONFIG_DRM_LONTIUM_LT9211=m
+CONFIG_DRM_LONTIUM_LT9611=m
+CONFIG_DRM_LONTIUM_LT9611UXC=m
+CONFIG_DRM_LVDS_CODEC=m
+CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m
+CONFIG_DRM_NWL_MIPI_DSI=m
+CONFIG_DRM_NXP_PTN3460=m
+CONFIG_DRM_PANEL_ABT_Y030XX067A=m
+CONFIG_DRM_PANEL_ARM_VERSATILE=m
+CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
+CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
+CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
+CONFIG_DRM_PANEL_BOE_TD4320=m
+CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A=m
+CONFIG_DRM_PANEL_BOE_TV101WUM_LL2=m
+CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
+CONFIG_DRM_PANEL_DSI_CM=m
+CONFIG_DRM_PANEL_EBBG_FT8719=m
+CONFIG_DRM_PANEL_EDP=m
+CONFIG_DRM_PANEL_ELIDA_KD35T133=m
+CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
+CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
+CONFIG_DRM_PANEL_HIMAX_HX8279=m
+CONFIG_DRM_PANEL_HIMAX_HX83102=m
+CONFIG_DRM_PANEL_HIMAX_HX83112A=m
+CONFIG_DRM_PANEL_HIMAX_HX83112B=m
+CONFIG_DRM_PANEL_HIMAX_HX8394=m
+CONFIG_DRM_PANEL_HYDIS_HV101HD1=m
+CONFIG_DRM_PANEL_ILITEK_IL9322=m
+CONFIG_DRM_PANEL_ILITEK_ILI9805=m
+CONFIG_DRM_PANEL_ILITEK_ILI9806E=m
+CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
+CONFIG_DRM_PANEL_ILITEK_ILI9882T=m
+CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
+CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
+CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=m
+CONFIG_DRM_PANEL_JDI_LPM102A188A=m
+CONFIG_DRM_PANEL_JDI_LT070ME05000=m
+CONFIG_DRM_PANEL_JDI_R63452=m
+CONFIG_DRM_PANEL_KHADAS_TS050=m
+CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m
+CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
+CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
+CONFIG_DRM_PANEL_LG_LB035Q02=m
+CONFIG_DRM_PANEL_LG_LG4573=m
+CONFIG_DRM_PANEL_LG_SW43408=m
+CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m
+CONFIG_DRM_PANEL_LVDS=m
+CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m
+CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
+CONFIG_DRM_PANEL_NEC_NL8048HL11=m
+CONFIG_DRM_PANEL_NEWVISION_NV3051D=m
+CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
+CONFIG_DRM_PANEL_NOVATEK_NT35510=m
+CONFIG_DRM_PANEL_NOVATEK_NT35560=m
+CONFIG_DRM_PANEL_NOVATEK_NT35950=m
+CONFIG_DRM_PANEL_NOVATEK_NT36523=m
+CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
+CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
+CONFIG_DRM_PANEL_NOVATEK_NT37801=m
+CONFIG_DRM_PANEL_NOVATEK_NT39016=m
+CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
+CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
+CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
+CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m
+CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
+CONFIG_DRM_PANEL_RAYDIUM_RM67200=m
+CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
+CONFIG_DRM_PANEL_RAYDIUM_RM692E5=m
+CONFIG_DRM_PANEL_RAYDIUM_RM69380=m
+CONFIG_DRM_PANEL_RENESAS_R61307=m
+CONFIG_DRM_PANEL_RENESAS_R69328=m
+CONFIG_DRM_PANEL_RONBO_RB070D30=m
+CONFIG_DRM_PANEL_SAMSUNG_AMS581VF01=m
+CONFIG_DRM_PANEL_SAMSUNG_AMS639RQ08=m
+CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
+CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
+CONFIG_DRM_PANEL_SAMSUNG_LD9040=m
+CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
+CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
+CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS427AP24=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01=m
+CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
+CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
+CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
+CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
+CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
+CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
+CONFIG_DRM_PANEL_SIMPLE=m
+CONFIG_DRM_PANEL_SITRONIX_ST7701=m
+CONFIG_DRM_PANEL_SITRONIX_ST7703=m
+CONFIG_DRM_PANEL_SITRONIX_ST7789V=m
+CONFIG_DRM_PANEL_SONY_ACX565AKM=m
+CONFIG_DRM_PANEL_SONY_TD4353_JDI=m
+CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
+CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m
+CONFIG_DRM_PANEL_SUMMIT=m
+CONFIG_DRM_PANEL_SYNAPTICS_R63353=m
+CONFIG_DRM_PANEL_TDO_TL070WSH30=m
+CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
+CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
+CONFIG_DRM_PANEL_TPO_TPG110=m
+CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
+CONFIG_DRM_PANEL_VISIONOX_G2647FB105=m
+CONFIG_DRM_PANEL_VISIONOX_R66451=m
+CONFIG_DRM_PANEL_VISIONOX_RM69299=m
+CONFIG_DRM_PANEL_VISIONOX_RM692E5=m
+CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
+CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
+CONFIG_DRM_PARADE_PS8622=m
+CONFIG_DRM_PARADE_PS8640=m
+CONFIG_DRM_RZG2L_USE_MIPI_DSI=y
+CONFIG_DRM_SAMSUNG_DSIM=m
+CONFIG_DRM_SII902X=m
+CONFIG_DRM_SII9234=m
+CONFIG_DRM_SIL_SII8620=m
+CONFIG_DRM_SIMPLE_BRIDGE=m
+CONFIG_DRM_SOLOMON_SSD2825=m
+CONFIG_DRM_ST7571_I2C=m
+CONFIG_DRM_ST7586=m
+CONFIG_DRM_ST7735R=m
+CONFIG_DRM_THINE_THC63LVD1024=m
+CONFIG_DRM_TI_DLPC3433=m
+CONFIG_DRM_TI_SN65DSI83=m
+CONFIG_DRM_TI_SN65DSI86=m
+CONFIG_DRM_TI_TDP158=m
+CONFIG_DRM_TI_TFP410=m
+CONFIG_DRM_TI_TPD12S015=m
+CONFIG_DRM_TOSHIBA_TC358762=m
+CONFIG_DRM_TOSHIBA_TC358764=m
+CONFIG_DRM_TOSHIBA_TC358767=m
+CONFIG_DRM_TOSHIBA_TC358768=m
+CONFIG_DRM_TOSHIBA_TC358775=m
+CONFIG_DRM_WAVESHARE_BRIDGE=m
+CONFIG_DST_CACHE=y
+CONFIG_DTPM_CPU=y
+CONFIG_DTPM_DEVFREQ=y
+CONFIG_DTPM=y
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DW_AXI_DMAC=m
+CONFIG_EEPROM_M24LR=m
+CONFIG_EFI_PARTITION=y
+CONFIG_ELF_CORE=y
+CONFIG_ELFCORE=y
+CONFIG_EPOLL=y
+CONFIG_ETHTOOL_NETLINK=y
+CONFIG_EVENTFD=y
+CONFIG_EXTRA_FIRMWARE=""
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_NOTIFY=y
+CONFIG_FB=y
+CONFIG_FHANDLE=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FPGA_MGR_ICE40_SPI=m
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FREEZER=y
+CONFIG_FSI=m
+CONFIG_FSI_MASTER_ASPEED=m
+CONFIG_FSI_MASTER_GPIO=m
+CONFIG_FSI_MASTER_HUB=m
+CONFIG_FSI_MASTER_I2CR=m
+CONFIG_FSI_NEW_DEV_NODE=y
+CONFIG_FSI_OCC=m
+CONFIG_FSI_SBEFIFO=m
+CONFIG_FSI_SCOM=m
+CONFIG_FSL_EDMA=m
+CONFIG_FUNCTION_GRAPH_RETADDR=y
+CONFIG_FUTEX_PI=y
+CONFIG_FUTEX=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER=y
+CONFIG_GCC_PLUGINS=y
+CONFIG_GEHC_PMC_ADC=m
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIB_AGILENT_82350B=m
+CONFIG_GPIB_AGILENT_82357A=m
+CONFIG_GPIB_CB7210=m
+CONFIG_GPIB_CEC_PCI=m
+CONFIG_GPIB_COMMON=m
+CONFIG_GPIB_FLUKE=m
+CONFIG_GPIB_FMH=m
+CONFIG_GPIB_GPIO=m
+CONFIG_GPIB_INES=m
+CONFIG_GPIB_LPVO=m
+CONFIG_GPIB=m
+CONFIG_GPIB_NI_PCI_ISA=m
+CONFIG_GPIB_NI_USB=m
+CONFIG_GPIB_PCMCIA=y
+CONFIG_GPIO_74X164=m
+CONFIG_GPIO_74XX_MMIO=m
+CONFIG_GPIO_ADNP=m
+CONFIG_GPIO_ADP5585=m
+CONFIG_GPIO_ALTERA=m
+CONFIG_GPIO_BD71815=m
+CONFIG_GPIO_BD71828=m
+CONFIG_GPIO_BLZP1600=m
+CONFIG_GPIO_CADENCE=m
+CONFIG_GPIO_CGBC=m
+CONFIG_GPIO_FTGPIO010=y
+CONFIG_GPIO_GRGPIO=m
+CONFIG_GPIO_GW_PLD=m
+CONFIG_GPIO_HLWD=m
+CONFIG_GPIOLIB_FASTPATH_LIMIT=512
+CONFIG_GPIO_LOGICVC=m
+CONFIG_GPIO_LP87565=m
+CONFIG_GPIO_MACSMC=m
+CONFIG_GPIO_MAX7360=m
+CONFIG_GPIO_MAX77620=m
+CONFIG_GPIO_MAX77650=m
+CONFIG_GPIO_MAX77759=m
+CONFIG_GPIO_MOXTET=m
+CONFIG_GPIO_MPSSE=m
+CONFIG_GPIO_NCT6694=m
+CONFIG_GPIO_POLARFIRE_SOC=y
+CONFIG_GPIO_PXA=y
+CONFIG_GPIO_SIFIVE=m
+CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER=m
+CONFIG_GPIO_SODAVILLE=y
+CONFIG_GPIO_STMPE=y
+CONFIG_GPIO_SYSCON=m
+CONFIG_GPIO_TC3589X=y
+CONFIG_GPIO_TPS65218=m
+CONFIG_GPIO_TPS65219=m
+CONFIG_GPIO_USBIO=m
+CONFIG_GPIO_VIRTUSER=m
+CONFIG_GPIO_WATCHDOG=m
+CONFIG_GPIO_WCD934X=m
+CONFIG_GPIO_XILINX=m
+CONFIG_GRO_CELLS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HI6421V600_IRQ=m
+CONFIG_HIBMCGE=m
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HISI_HIKEY_USB=m
+CONFIG_HISILICON_ERRATUM_162100801=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI_OCTEONEP=y
+CONFIG_HVC_DRIVER=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM_AIROHA=m
+CONFIG_HW_RANDOM_ATMEL=m
+CONFIG_HW_RANDOM_BCM74110=m
+CONFIG_HW_RANDOM_CCTRNG=m
+CONFIG_HW_RANDOM_IPROC_RNG200=m
+CONFIG_I2C_AMD_ASF=m
+CONFIG_I2C_ARB_GPIO_CHALLENGE=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CGBC=m
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_DEMUX_PINCTRL=m
+CONFIG_I2C_DESIGNWARE_AMDISP=m
+CONFIG_I2C_FSI=m
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_KEBA=m
+CONFIG_I2C_MUX_GPMUX=m
+CONFIG_I2C_MUX_PINCTRL=m
+CONFIG_I2C_PXA=m
+CONFIG_I2C_PXA_SLAVE=y
+CONFIG_I2C_RK3X=m
+CONFIG_I2CR_SCOM=m
+CONFIG_IKHEADERS=m
+CONFIG_IMX_AIPSTZ=m
+CONFIG_IMX_SCMI_MISC_DRV=m
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_INITRAMFS_PRESERVE_MTIME=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT_88PM886_ONKEY=m
+CONFIG_INPUT_ATMEL_CAPTOUCH=m
+CONFIG_INPUT_AW86927=m
+CONFIG_INPUT_CPCAP_PWRBUTTON=m
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_MAX77650_ONKEY=m
+CONFIG_INPUT_MAX77693_HAPTIC=m
+CONFIG_INPUT_RK805_PWRKEY=m
+CONFIG_INPUT_STPMIC1_ONKEY=m
+CONFIG_INPUT_TPS65218_PWRBUTTON=m
+CONFIG_INPUT_TPS65219_PWRBUTTON=m
+CONFIG_INPUT_TPS6594_PWRBUTTON=m
+CONFIG_INPUT=y
+CONFIG_INTERCONNECT_MTK_DVFSRC_EMI=m
+CONFIG_INTERCONNECT_MTK_MT8183=m
+CONFIG_INTERCONNECT_MTK_MT8195=m
+CONFIG_INTERCONNECT_QCOM_QCS615=m
+CONFIG_INTERCONNECT_QCOM_QCS8300=m
+CONFIG_INTERCONNECT_QCOM_SAR2130P=m
+CONFIG_INTERVAL_TREE=y
+CONFIG_IOMMU_API=y
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IO_URING_MOCK_FILE=m
+CONFIG_IO_URING=y
+CONFIG_IPC_NS=y
+CONFIG_IPMB_DEVICE_INTERFACE=m
+CONFIG_IP_NF_IPTABLES_LEGACY=m
+CONFIG_IPQ_GCC_5424=m
+CONFIG_IR_GPIO_CIR=m
+CONFIG_IR_GPIO_TX=m
+CONFIG_IR_HIX5HD2=m
+CONFIG_IR_PWM_TX=m
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_IR_SPI=m
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+CONFIG_KALLSYMS=y
+CONFIG_KEBA_CP500=m
+CONFIG_KEBA_LAN9252=m
+CONFIG_KEYBOARD_ADP5585=m
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_BCM=m
+CONFIG_KEYBOARD_CAP11XX=m
+CONFIG_KEYBOARD_MAX7360=m
+CONFIG_KEYBOARD_OMAP4=m
+CONFIG_KEYBOARD_STMPE=m
+CONFIG_KEYBOARD_TC3589X=m
+CONFIG_KEYS=y
+CONFIG_KPROBES=y
+CONFIG_LAN966X_OIC=m
+CONFIG_LAN969X_SWITCH=y
+CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y
+CONFIG_LDISC_AUTOLOAD=y
+CONFIG_LEDS_AAT1290=m
+CONFIG_LEDS_AN30259A=m
+CONFIG_LEDS_AW2013=m
+CONFIG_LEDS_BCM6328=m
+CONFIG_LEDS_BCM6358=m
+CONFIG_LEDS_BLINKM_MULTICOLOR=y
+CONFIG_LEDS_CPCAP=m
+CONFIG_LEDS_CR0014114=m
+CONFIG_LEDS_EL15203000=m
+CONFIG_LEDS_IS31FL32XX=m
+CONFIG_LEDS_KTD2692=m
+CONFIG_LEDS_LGM=m
+CONFIG_LEDS_LM3692X=m
+CONFIG_LEDS_LM3697=m
+CONFIG_LEDS_LP5521=m
+CONFIG_LEDS_LP5523=m
+CONFIG_LEDS_LP5562=m
+CONFIG_LEDS_LP5569=m
+CONFIG_LEDS_LP55XX_COMMON=m
+CONFIG_LEDS_LP8501=m
+CONFIG_LEDS_LP8860=m
+CONFIG_LEDS_LP8864=m
+CONFIG_LEDS_MAX5970=m
+CONFIG_LEDS_MAX77650=m
+CONFIG_LEDS_MAX77693=m
+CONFIG_LEDS_MAX77705=m
+CONFIG_LEDS_MT6360=m
+CONFIG_LEDS_QCOM_LPG=m
+CONFIG_LEDS_QNAP_MCU=m
+CONFIG_LEDS_RT4505=m
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TPS6131X=m
+CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m
+CONFIG_LITEX_SOC_CONTROLLER=m
+CONFIG_LOCALVERSION=""
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+CONFIG_MAILBOX_TEST=m
+CONFIG_MARVELL_CN10K_DPI=m
+CONFIG_MARVELL_PEM_PMU=m
+CONFIG_MAX77620_THERMAL=m
+CONFIG_MAX77620_WATCHDOG=m
+CONFIG_MAXLINEAR_86100_PHY=m
+CONFIG_MAXLINEAR_86110_PHY=m
+CONFIG_MCHP_LAN966X_PCI=m
+CONFIG_MDIO_AIROHA=m
+CONFIG_MDIO_BUS_MUX_GPIO=m
+CONFIG_MDIO_BUS_MUX_MMIOREG=m
+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=m
+CONFIG_MDIO_HISI_FEMAC=m
+CONFIG_MDIO_IPQ4019=m
+CONFIG_MDIO_IPQ8064=m
+CONFIG_MDIO_OCTEON=m
+CONFIG_MD_LLBITMAP=y
+CONFIG_MD=y
+CONFIG_MEDIATEK_2P5GE_PHY=m
+CONFIG_MEMBARRIER=y
+CONFIG_MEMCG_V1=y
+CONFIG_MEMCG=y
+CONFIG_MEMORY_BALLOON=y
+CONFIG_MEMTEST=y
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+CONFIG_MFD_ACT8945A=m
+CONFIG_MFD_ADP5585=m
+CONFIG_MFD_AS3722=m
+CONFIG_MFD_ATMEL_FLEXCOM=m
+CONFIG_MFD_ATMEL_HLCDC=m
+CONFIG_MFD_BQ257XX=m
+CONFIG_MFD_CGBC=m
+CONFIG_MFD_CPCAP=m
+CONFIG_MFD_CS40L50_I2C=m
+CONFIG_MFD_CS40L50_SPI=m
+CONFIG_MFD_GATEWORKS_GSC=m
+CONFIG_MFD_HI6421_PMIC=m
+CONFIG_MFD_HI6421_SPMI=m
+CONFIG_MFD_LOCHNAGAR=y
+CONFIG_MFD_MAX5970=m
+CONFIG_MFD_MAX7360=m
+CONFIG_MFD_MAX77620=y
+CONFIG_MFD_MAX77650=m
+CONFIG_MFD_MAX77686=m
+CONFIG_MFD_MAX77705=m
+CONFIG_MFD_MAX77714=m
+CONFIG_MFD_MAX77759=m
+CONFIG_MFD_NCT6694=m
+CONFIG_MFD_NTXEC=m
+CONFIG_MFD_QCOM_PM8008=m
+CONFIG_MFD_RK8XX_I2C=m
+CONFIG_MFD_RK8XX_SPI=m
+CONFIG_MFD_RN5T618=m
+CONFIG_MFD_ROHM_BD71828=m
+CONFIG_MFD_ROHM_BD718XX=m
+CONFIG_MFD_ROHM_BD957XMUF=m
+CONFIG_MFD_ROHM_BD96801=m
+CONFIG_MFD_RSMU_I2C=m
+CONFIG_MFD_RSMU_SPI=m
+CONFIG_MFD_SEC_ACPM=m
+CONFIG_MFD_SEC_CORE=m
+CONFIG_MFD_SEC_I2C=m
+CONFIG_MFD_STMFX=m
+CONFIG_MFD_STMPE=y
+CONFIG_MFD_STPMIC1=m
+CONFIG_MFD_TC3589X=y
+CONFIG_MFD_TI_LP87565=m
+CONFIG_MFD_TPS65217=m
+CONFIG_MFD_TPS65218=m
+CONFIG_MFD_TPS65219=m
+CONFIG_MHZ19B=m
+CONFIG_MIGRATION=y
+CONFIG_MMC_LITEX=m
+CONFIG_MMC_SDHCI_CADENCE=m
+CONFIG_MMC_SDHCI_MILBEAUT=m
+CONFIG_MMC_SDHCI_OF_ARASAN=m
+CONFIG_MMC_SDHCI_OF_AT91=m
+CONFIG_MMC_SDHCI_OF_DWCMSHC=m
+CONFIG_MMU_NOTIFIER=y
+CONFIG_MMU=y
+CONFIG_MOST_DIM2=m
+CONFIG_MOXTET=m
+CONFIG_MPILIB=y
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_MTD_NAND_CADENCE=m
+CONFIG_MTD_NAND_DENALI_DT=m
+CONFIG_MTD_NAND_INTEL_LGM=m
+CONFIG_MTD_OF_PARTS=m
+CONFIG_MTD_PCI=m
+CONFIG_MTD_PHYSMAP_GEMINI=y
+CONFIG_MTD_PHYSMAP_GPIO_ADDR=y
+CONFIG_MTD_PHYSMAP_IXP4XX=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_PHYSMAP_VERSATILE=y
+CONFIG_MTK_DVFSRC=m
+CONFIG_MULTIUSER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_MUX_ADG792A=m
+CONFIG_MUX_GPIO=m
+CONFIG_MUX_MMIO=m
+CONFIG_NAMESPACES=y
+CONFIG_NCT6694_WATCHDOG=m
+CONFIG_NCT7201=m
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_CORE=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_DSA_MV88E6XXX_LEDS=y
+CONFIG_NET_NS=y
+CONFIG_NET_SOCK_MSG=y
+CONFIG_NET_VRF=m
+CONFIG_NLATTR=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NTSYNC=m
+CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=m
+CONFIG_NVMEM_MAX77759=m
+CONFIG_NVMEM_RCAR_EFUSE=m
+CONFIG_NVMEM_REBOOT_MODE=m
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVMEM_U_BOOT_ENV=m
+CONFIG_NVMEM=y
+CONFIG_NXP_ENETC4=m
+CONFIG_NXP_NETC_BLK_CTRL=m
+CONFIG_NXP_STM_TIMER=y
+CONFIG_OF_FPGA_REGION=m
+CONFIG_OF_PARTITION=y
+CONFIG_OF_PMEM=m
+CONFIG_OID_REGISTRY=y
+CONFIG_OPEN_DICE=m
+CONFIG_PACKING_KUNIT_TEST=m
+CONFIG_PAGE_COUNTER=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PATA_OF_PLATFORM=m
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCIE_CADENCE_PLAT_EP=y
+CONFIG_PCIE_CADENCE_PLAT_HOST=y
+CONFIG_PCIE_INTEL_GW=y
+CONFIG_PCIE_MICROCHIP_HOST=m
+CONFIG_PCIE_THERMAL=y
+CONFIG_PCIE_TPH=y
+CONFIG_PCIE_XILINX=y
+CONFIG_PCI_FTPCI100=y
+CONFIG_PCI_HOST_GENERIC=m
+CONFIG_PCI_MSI=y
+CONFIG_PCI_NPEM=y
+CONFIG_PCI_PWRCTL_SLOT=m
+CONFIG_PCI_PWRCTRL_SLOT=m
+CONFIG_PCI_QUIRKS=y
+CONFIG_PCI=y
+CONFIG_PCP_BATCH_SCALE_MAX=5
+CONFIG_PCS_RZN1_MIIC=m
+CONFIG_PERF_EVENTS=y
+CONFIG_PFCP=m
+CONFIG_PHY_CADENCE_DPHY=m
+CONFIG_PHY_CADENCE_DPHY_RX=m
+CONFIG_PHY_CADENCE_SALVO=m
+CONFIG_PHY_CADENCE_SIERRA=m
+CONFIG_PHY_CADENCE_TORRENT=m
+CONFIG_PHY_INTEL_LGM_COMBO=y
+CONFIG_PHY_LAN966X_SERDES=m
+CONFIG_PHY_MAPPHONE_MDM6600=m
+CONFIG_PHY_NXP_PTN3222=m
+CONFIG_PHY_OCELOT_SERDES=m
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_SNPS_EUSB2=m
+CONFIG_PHY_STM32_COMBOPHY=m
+CONFIG_PHY_TEGRA194_P2U=m
+CONFIG_PID_NS=y
+CONFIG_PINCTRL_AIROHA=m
+CONFIG_PINCTRL_AS3722=m
+CONFIG_PINCTRL_AW9523=m
+CONFIG_PINCTRL_AXP209=m
+CONFIG_PINCTRL_EQUILIBRIUM=m
+CONFIG_PINCTRL_IPQ5424=m
+CONFIG_PINCTRL_LOCHNAGAR=m
+CONFIG_PINCTRL_MAX77620=m
+CONFIG_PINCTRL_MICROCHIP_SGPIO=m
+CONFIG_PINCTRL_MT6893=y
+CONFIG_PINCTRL_MT8196=y
+CONFIG_PINCTRL_OCELOT=m
+CONFIG_PINCTRL_PALMAS=m
+CONFIG_PINCTRL_PEF2256=m
+CONFIG_PINCTRL_QCS615=m
+CONFIG_PINCTRL_QCS8300=m
+CONFIG_PINCTRL_RK805=m
+CONFIG_PINCTRL_SAR2130P=m
+CONFIG_PINCTRL_SINGLE=m
+CONFIG_PINCTRL_SM8750=m
+CONFIG_PINCTRL_STMFX=m
+CONFIG_PINCTRL_TPS6594=m
+CONFIG_PKCS7_MESSAGE_PARSER=y
+CONFIG_PLATFORM_MHU=m
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM=y
+CONFIG_POSIX_AUX_CLOCKS=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_TIMERS=y
+CONFIG_POWER_RESET_AS3722=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_LTC2952=y
+CONFIG_POWER_RESET_REGULATOR=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_TORADEX_EC=m
+CONFIG_POWER_SEQUENCING=m
+CONFIG_POWER_SEQUENCING_QCOM_WCN=m
+CONFIG_POWER_SEQUENCING_TH1520_GPU=m
+CONFIG_PREEMPT_LAZY=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_PRINTK=y
+CONFIG_PROC_MEM_ALWAYS_FORCE=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_PROFILING=y
+CONFIG_PTP_1588_CLOCK_VMCLOCK=m
+CONFIG_PWM_ADP5585=m
+CONFIG_PWM_ARGON_FAN_HAT=m
+CONFIG_PWM_ATMEL_HLCDC_PWM=m
+CONFIG_PWM_ATMEL_TCB=m
+CONFIG_PWM_FSL_FTM=m
+CONFIG_PWM_INTEL_LGM=m
+CONFIG_PWM_MC33XS2410=m
+CONFIG_PWM_NTXEC=m
+CONFIG_PWM_RENESAS_RCAR=m
+CONFIG_PWM_RENESAS_RZG2L_GPT=m
+CONFIG_PWM_RENESAS_RZ_MTU3=m
+CONFIG_PWM_STMPE=y
+CONFIG_PWM_XILINX=m
+CONFIG_PWRSEQ_EMMC=m
+CONFIG_PWRSEQ_SD8787=m
+CONFIG_PWRSEQ_SIMPLE=m
+CONFIG_QCOM_PD_MAPPER=m
+CONFIG_QCOM_PMIC_GLINK=m
+CONFIG_QCS_GCC_615=m
+CONFIG_QCS_GCC_8300=m
+CONFIG_QEDI=m
+CONFIG_RANDOMIZE_KSTACK_OFFSET=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS_CEC=y
+CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
+CONFIG_RCU_NEED_SEGCBLIST=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_XZ=y
+CONFIG_RD_ZSTD=y
+CONFIG_REALTEK_PHY_HWMON=y
+CONFIG_REGMAP=y
+CONFIG_REGULATOR_ACT8945A=m
+CONFIG_REGULATOR_AS3722=m
+CONFIG_REGULATOR_BD71815=m
+CONFIG_REGULATOR_BD71828=m
+CONFIG_REGULATOR_BD718XX=m
+CONFIG_REGULATOR_BD957XMUF=m
+CONFIG_REGULATOR_BD96801=m
+CONFIG_REGULATOR_BQ257XX=m
+CONFIG_REGULATOR_CPCAP=m
+CONFIG_REGULATOR_CROS_EC=m
+CONFIG_REGULATOR_DA9063=m
+CONFIG_REGULATOR_DA9121=m
+CONFIG_REGULATOR_FAN53880=m
+CONFIG_REGULATOR_HI6421=m
+CONFIG_REGULATOR_HI6421V530=m
+CONFIG_REGULATOR_HI6421V600=m
+CONFIG_REGULATOR_LOCHNAGAR=m
+CONFIG_REGULATOR_LP873X=m
+CONFIG_REGULATOR_LP87565=m
+CONFIG_REGULATOR_MAX77620=m
+CONFIG_REGULATOR_MAX77650=m
+CONFIG_REGULATOR_MAX77686=m
+CONFIG_REGULATOR_MAX77802=m
+CONFIG_REGULATOR_MAX8973=m
+CONFIG_REGULATOR_MCP16502=m
+CONFIG_REGULATOR_MP5416=m
+CONFIG_REGULATOR_MP886X=m
+CONFIG_REGULATOR_MPQ7920=m
+CONFIG_REGULATOR_MTK_DVFSRC=m
+CONFIG_REGULATOR_PF8X00=m
+CONFIG_REGULATOR_PFUZE100=m
+CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
+CONFIG_REGULATOR_RK808=m
+CONFIG_REGULATOR_RN5T618=m
+CONFIG_REGULATOR_S2MPA01=m
+CONFIG_REGULATOR_S2MPS11=m
+CONFIG_REGULATOR_S5M8767=m
+CONFIG_REGULATOR_STPMIC1=m
+CONFIG_REGULATOR_SY8106A=m
+CONFIG_REGULATOR_SY8824X=m
+CONFIG_REGULATOR_SY8827N=m
+CONFIG_REGULATOR_TPS6286X=m
+CONFIG_REGULATOR_TPS6287X=m
+CONFIG_REGULATOR_TPS65217=m
+CONFIG_REGULATOR_TPS65218=m
+CONFIG_REGULATOR_TPS65219=m
+CONFIG_REGULATOR_TPS6594=m
+CONFIG_REGULATOR_VCTRL=m
+CONFIG_RESET_GPIO=m
+CONFIG_RESET_IMX_SCU=m
+CONFIG_RESET_INTEL_GW=y
+CONFIG_RESET_MCHP_SPARX5=m
+CONFIG_RESET_MESON_AUX=m
+CONFIG_RESET_RZV2H_USB2PHY=m
+CONFIG_RN5T618_ADC=m
+CONFIG_RN5T618_POWER=m
+CONFIG_RN5T618_WATCHDOG=m
+CONFIG_ROHM_BD79112=m
+CONFIG_ROHM_BD79124=m
+CONFIG_RPMB=m
+CONFIG_RSEQ=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_88PM886=m
+CONFIG_RTC_DRV_AMLOGIC_A4=m
+CONFIG_RTC_DRV_AS3722=m
+CONFIG_RTC_DRV_BD70528=m
+CONFIG_RTC_DRV_CADENCE=m
+CONFIG_RTC_DRV_CPCAP=m
+CONFIG_RTC_DRV_HYM8563=m
+CONFIG_RTC_DRV_ISL12026=m
+CONFIG_RTC_DRV_MAX77686=m
+CONFIG_RTC_DRV_NCT3018Y=m
+CONFIG_RTC_DRV_NCT6694=m
+CONFIG_RTC_DRV_NTXEC=m
+CONFIG_RTC_DRV_R7301=m
+CONFIG_RTC_DRV_RC5T619=m
+CONFIG_RTC_DRV_RENESAS_RTCA3=m
+CONFIG_RTC_DRV_RK808=m
+CONFIG_RTC_DRV_RX8111=m
+CONFIG_RTC_DRV_S32G=m
+CONFIG_RTC_DRV_S5M=m
+CONFIG_RTC_DRV_SD2405AL=m
+CONFIG_RTC_DRV_TWL4030=m
+CONFIG_RTC_DRV_ZYNQMP=m
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_NVMEM=y
+CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
+CONFIG_RTC_SYSTOHC=y
+CONFIG_RT_MUTEXES=y
+CONFIG_RTW88_8812AU=m
+CONFIG_RTW88_8814AE=m
+CONFIG_RTW88_8814AU=m
+CONFIG_RTW88_8821AU=m
+CONFIG_RUST_FW_LOADER_ABSTRACTIONS=y
+CONFIG_RUST=y
+CONFIG_RVU_ESWITCH=m
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SA_CAMCC_8775P=m
+CONFIG_SA_DISPCC_8775P=m
+CONFIG_SAR_GCC_2130P=m
+CONFIG_SAR_GPUCC_2130P=m
+CONFIG_SATA_HOST=y
+CONFIG_SATA_MOBILE_LPM_POLICY=0
+CONFIG_SATA_PMP=y
+CONFIG_SA_VIDEOCC_8775P=m
+CONFIG_SBITMAP=y
+CONFIG_SCHED_CLASS_EXT=y
+CONFIG_SCHED_HRTICK=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m
+CONFIG_SECCOMP_FILTER=y
+CONFIG_SECCOMP=y
+CONFIG_SECURITYFS=y
+CONFIG_SEN0322=m
+CONFIG_SENSORS_ISL28022=m
+CONFIG_SENSORS_KBATT=m
+CONFIG_SENSORS_KFAN=m
+CONFIG_SENSORS_LOCHNAGAR=m
+CONFIG_SENSORS_NCT7363=m
+CONFIG_SENSORS_OCC_P9_SBE=m
+CONFIG_SERIAL_CONEXANT_DIGICOLOR=m
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_LITEUART=m
+CONFIG_SERIAL_LITEUART_MAX_PORTS=2
+CONFIG_SERIAL_OF_PLATFORM=m
+CONFIG_SERIAL_SIFIVE=m
+CONFIG_SERIAL_XILINX_PS_UART=m
+CONFIG_SERIO_APBPS2=m
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_OLPC_APSP=m
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SHMEM=y
+CONFIG_SIGNALFD=y
+CONFIG_SLAB_BUCKETS=y
+CONFIG_SLUB_CPU_PARTIAL=y
+CONFIG_SLUB=y
+CONFIG_SMI240=m
+CONFIG_SMP=y
+CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
+CONFIG_SND_AUDIO_GRAPH_CARD2=m
+CONFIG_SND_AUDIO_GRAPH_CARD=m
+CONFIG_SND_HDA_ACPI=m
+CONFIG_SND_SERIAL_GENERIC=m
+CONFIG_SND_SOC_ADAU1373=m
+CONFIG_SND_SOC_AMD_LEGACY_SDW_MACH=m
+CONFIG_SND_SOC_AW88081=m
+CONFIG_SND_SOC_CPCAP=m
+CONFIG_SND_SOC_CS42L84=m
+CONFIG_SND_SOC_CS48L32=m
+CONFIG_SND_SOC_ES8323=m
+CONFIG_SND_SOC_ES8375=m
+CONFIG_SND_SOC_ES8389=m
+CONFIG_SND_SOC_LOCHNAGAR_SC=m
+CONFIG_SND_SOC_MIKROE_PROTO=m
+CONFIG_SND_SOC_MSIOF=m
+CONFIG_SND_SOC_NTP8835=m
+CONFIG_SND_SOC_NTP8918=m
+CONFIG_SND_SOC_QDSP6_USB=m
+CONFIG_SND_SOC_RK817=m
+CONFIG_SND_SOC_ROCKCHIP_SAI=m
+CONFIG_SND_SOC_RT721_SDCA_SDW=m
+CONFIG_SND_SOC_RT9123=m
+CONFIG_SND_SOC_RT9123P=m
+CONFIG_SND_SOC_RTQ9124=m
+CONFIG_SND_SOC_SMA1307=m
+CONFIG_SND_SOC_SOF_OF=m
+CONFIG_SND_SOC_SSM3515=m
+CONFIG_SND_SOC_UDA1342=m
+CONFIG_SND_SOC_USB=m
+CONFIG_SND_SOC_WM8998=m
+CONFIG_SND_TEST_COMPONENT=m
+CONFIG_SND_USB_AUDIO_QMI=m
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPI_CADENCE_QUADSPI=m
+CONFIG_SPI_CADENCE_XSPI=m
+CONFIG_SPI_FSI=m
+CONFIG_SPI_FSL_SPI=m
+CONFIG_SPI_SN_F_OSPI=m
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_SSB_POSSIBLE=y
+CONFIG_SSIF_IPMI_BMC=m
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_STM32_OMM=m
+CONFIG_STMPE_ADC=m
+CONFIG_STMPE_I2C=y
+CONFIG_STMPE_SPI=y
+CONFIG_STPMIC1_WATCHDOG=m
+CONFIG_SUN50I_H6_PRCM_PPU=m
+CONFIG_SUN55I_PCK600=m
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SUSPEND=y
+CONFIG_SWIOTLB=y
+CONFIG_SYMBOLIC_ERRNAME=y
+CONFIG_SYSCON_REBOOT_MODE=m
+CONFIG_SYSCTL=y
+CONFIG_SYSTEM_TRUSTED_KEYS=""
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_SYSVIPC=y
+CONFIG_TASKS_RCU_GENERIC=y
+CONFIG_TASKS_TRACE_RCU=y
+CONFIG_TCG_TPM2_HMAC=y
+CONFIG_THERMAL_MMIO=m
+CONFIG_THERMAL_OF=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_TI_FPC202=m
+CONFIG_TIME_NS=y
+CONFIG_TIMERFD=y
+CONFIG_TINYDRM_SHARP_MEMORY=m
+CONFIG_TOUCHSCREEN_AR1021_I2C=m
+CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m
+CONFIG_TOUCHSCREEN_EGALAX=m
+CONFIG_TOUCHSCREEN_IMX6UL_TSC=m
+CONFIG_TOUCHSCREEN_STMPE=m
+CONFIG_TRACE_GPU_MEM=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TTY=y
+CONFIG_TYPEC_MUX_TUSB1046=m
+CONFIG_UCSI_HUAWEI_GAOKUN=m
+CONFIG_UCSI_PMIC_GLINK=m
+CONFIG_UIO=m
+CONFIG_UNIX98_PTYS=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_AUTOSUSPEND_DELAY=2
+CONFIG_USB_CHIPIDEA_IMX=m
+CONFIG_USB_CHIPIDEA_TEGRA=m
+CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1
+CONFIG_USB_DEFAULT_PERSIST=y
+CONFIG_USB_DWC3_OF_SIMPLE=m
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_USB_EXTRON_DA_HD_4K_PLUS_CEC=m
+CONFIG_USB_GADGET_XILINX=m
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_ONBOARD_DEV=m
+CONFIG_USB_ONBOARD_DEV_USB5744=y
+CONFIG_USB_PCI=y
+CONFIG_USB_SNP_UDC_PLAT=m
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_XHCI_SIDEBAND=y
+CONFIG_USER_NS=y
+CONFIG_UTIL_MACROS_KUNIT=m
+CONFIG_UTS_NS=y
+CONFIG_VCPU_STALL_DETECTOR=m
+CONFIG_VEML3235=m
+CONFIG_VGA_ARB=y
+CONFIG_VHOST_ENABLE_FORK_OWNER_CONTROL=y
+CONFIG_VHOST_MENU=y
+CONFIG_VHOST_NET=m
+CONFIG_VHOST_VSOCK=m
+CONFIG_VIDEO_ADV748X=m
+CONFIG_VIDEO_C3_ISP=m
+CONFIG_VIDEO_C3_MIPI_ADAPTER=m
+CONFIG_VIDEO_C3_MIPI_CSI2=m
+CONFIG_VIDEO_CAMERA_LENS=y
+CONFIG_VIDEO_IMX334=m
+CONFIG_VIDEO_IMX335=m
+CONFIG_VIDEO_IMX412=m
+CONFIG_VIDEO_IMX415=m
+CONFIG_VIDEO_INTEL_IPU6=m
+CONFIG_VIDEO_ISL7998X=m
+CONFIG_VIDEO_LENS=y
+CONFIG_VIDEO_LT6911UXE=m
+CONFIG_VIDEO_MAX9286=m
+CONFIG_VIDEO_MAX96712=m
+CONFIG_VIDEO_MAX96714=m
+CONFIG_VIDEO_MAX96717=m
+CONFIG_VIDEO_MUX=m
+CONFIG_VIDEO_OV02C10=m
+CONFIG_VIDEO_OV02E10=m
+CONFIG_VIDEO_OV5640=m
+CONFIG_VIDEO_OV5645=m
+CONFIG_VIDEO_OV9282=m
+CONFIG_VIDEO_RP1_CFE=m
+CONFIG_VIDEO_SYNOPSYS_HDMIRX_LOAD_DEFAULT_EDID=y
+CONFIG_VIDEO_SYNOPSYS_HDMIRX=m
+CONFIG_VIDEO_VD55G1=m
+CONFIG_VIDEO_VD56G3=m
+CONFIG_VIDEO_VGXY61=m
+CONFIG_VIDEO_XILINX_CSI2RXSS=m
+CONFIG_VIDEO_XILINX=m
+CONFIG_VIDEO_XILINX_TPG=m
+CONFIG_VIDEO_XILINX_VTC=m
+CONFIG_VIRTIO_MENU=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_RTC_ARM=y
+CONFIG_VIRTIO_RTC_CLASS=y
+CONFIG_VIRTIO_RTC=m
+CONFIG_VIRTIO_RTC_PTP=y
+CONFIG_VIRTIO_VFIO_PCI=m
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VMLINUX_MAP=y
+CONFIG_VPA_PMU=m
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_VT=y
+CONFIG_WIRELESS=y
+CONFIG_WLAN_VENDOR_ADMTEK=y
+CONFIG_WLAN_VENDOR_ATH=y
+CONFIG_WLAN_VENDOR_ATMEL=y
+CONFIG_WLAN_VENDOR_BROADCOM=y
+CONFIG_WLAN_VENDOR_INTEL=y
+CONFIG_WLAN_VENDOR_INTERSIL=y
+CONFIG_WLAN_VENDOR_MARVELL=y
+CONFIG_WLAN_VENDOR_MEDIATEK=y
+CONFIG_WLAN_VENDOR_MICROCHIP=y
+CONFIG_WLAN_VENDOR_PURELIFI=y
+CONFIG_WLAN_VENDOR_QUANTENNA=y
+CONFIG_WLAN_VENDOR_RALINK=y
+CONFIG_WLAN_VENDOR_REALTEK=y
+CONFIG_WLAN_VENDOR_RSI=y
+CONFIG_WLAN_VENDOR_SILABS=y
+CONFIG_WLAN_VENDOR_ST=y
+CONFIG_WLAN_VENDOR_TI=y
+CONFIG_WLAN_VENDOR_ZYDAS=y
+CONFIG_WLAN=y
+CONFIG_WLCORE_SPI=m
+CONFIG_WMT_SOCINFO=y
+CONFIG_X509_CERTIFICATE_PARSER=y
+CONFIG_X86_BUS_LOCK_DETECT=y
+CONFIG_XIL_AXIS_FIFO=m
+CONFIG_XILINX_INTC=y
+CONFIG_XILINX_VCU=m
+CONFIG_XILINX_ZYNQMP_DPDMA=m
+CONFIG_XILLYBUS_OF=m
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM64=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_RISCV=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC=y
+CONFIG_ZL3073X_I2C=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZRAM_BACKEND_842=y
+CONFIG_ZRAM_BACKEND_DEFLATE=y
+CONFIG_ZRAM_BACKEND_LZ4HC=y
+CONFIG_ZRAM_BACKEND_LZ4=y
+CONFIG_ZRAM_BACKEND_LZO=y
+CONFIG_ZRAM_BACKEND_ZSTD=y
+CONFIG_ZRAM_DEF_COMP_ZSTD=y
+CONFIG_ZRAM=m
+CONFIG_ZSTD_DECOMPRESS=y
+CONFIG_NEXUS=m
diff --git a/hid.fragment b/hid.fragment
new file mode 100644
index 0000000..42fdcf4
--- /dev/null
+++ b/hid.fragment
@@ -0,0 +1,197 @@
+#
+# HID support
+#
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+CONFIG_HID_BPF=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_HIDRAW=y
+CONFIG_UHID=m
+CONFIG_HID_GENERIC=m
+CONFIG_HID_HAPTIC=y
+
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=m
+CONFIG_HID_ACCUTOUCH=m
+CONFIG_HID_ACRUX=m
+CONFIG_HID_ACRUX_FF=y
+CONFIG_HID_APPLE=m
+CONFIG_HID_APPLEIR=m
+CONFIG_HID_APPLETB_KBD=m
+CONFIG_HID_APPLETB_BL=m
+CONFIG_HID_ASUS=m
+CONFIG_HID_AUREAL=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_BETOP_FF=m
+CONFIG_HID_BIGBEN_FF=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CORSAIR=m
+CONFIG_HID_COUGAR=m
+CONFIG_HID_MACALLY=m
+CONFIG_HID_PRODIKEYS=m
+CONFIG_HID_CMEDIA=m
+CONFIG_HID_CP2112=m
+CONFIG_HID_CREATIVE_SB0540=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_DRAGONRISE=m
+CONFIG_DRAGONRISE_FF=y
+CONFIG_HID_EMS_FF=m
+CONFIG_HID_ELAN=m
+CONFIG_HID_ELECOM=m
+CONFIG_HID_ELO=m
+CONFIG_HID_EVISION=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_FT260=m
+CONFIG_HID_GEMBIRD=m
+CONFIG_HID_GFRM=m
+CONFIG_HID_GLORIOUS=m
+CONFIG_HID_HOLTEK=m
+CONFIG_HOLTEK_FF=y
+CONFIG_HID_GOODIX_SPI=m
+CONFIG_HID_GOOGLE_HAMMER=m
+CONFIG_HID_GOOGLE_STADIA_FF=m
+CONFIG_HID_VIVALDI=m
+CONFIG_HID_GT683R=m
+CONFIG_HID_KEYTOUCH=m
+CONFIG_HID_KYE=m
+CONFIG_HID_UCLOGIC=m
+CONFIG_HID_WALTOP=m
+CONFIG_HID_VIEWSONIC=m
+CONFIG_HID_VRC2=m
+CONFIG_HID_XIAOMI=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_ICADE=m
+CONFIG_HID_ITE=m
+CONFIG_HID_JABRA=m
+CONFIG_HID_TWINHAN=m
+CONFIG_HID_KENSINGTON=m
+CONFIG_HID_KYSONA=m
+CONFIG_HID_LCPOWER=m
+CONFIG_HID_LED=m
+CONFIG_HID_LENOVO=m
+CONFIG_HID_LETSKETCH=m
+CONFIG_HID_LOGITECH=m
+CONFIG_HID_LOGITECH_DJ=m
+CONFIG_HID_LOGITECH_HIDPP=m
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_LOGIWHEELS_FF=y
+CONFIG_HID_MAGICMOUSE=m
+CONFIG_HID_MALTRON=m
+CONFIG_HID_MAYFLASH=m
+CONFIG_HID_MEGAWORLD_FF=m
+CONFIG_HID_REDRAGON=m
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_MULTITOUCH=m
+CONFIG_HID_NINTENDO=m
+CONFIG_NINTENDO_FF=y
+CONFIG_HID_NTI=m
+CONFIG_HID_NTRIG=m
+CONFIG_HID_NVIDIA_SHIELD=m
+CONFIG_NVIDIA_SHIELD_FF=y
+CONFIG_HID_ORTEK=m
+CONFIG_HID_PANTHERLORD=m
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PENMOUNT=m
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_PICOLCD=m
+CONFIG_HID_PICOLCD_FB=y
+CONFIG_HID_PICOLCD_BACKLIGHT=y
+CONFIG_HID_PICOLCD_LCD=y
+CONFIG_HID_PICOLCD_LEDS=y
+CONFIG_HID_PICOLCD_CIR=y
+CONFIG_HID_PLANTRONICS=m
+CONFIG_HID_PLAYSTATION=m
+CONFIG_HID_PXRC=m
+CONFIG_HID_RAZER=m
+CONFIG_PLAYSTATION_FF=y
+CONFIG_HID_PRIMAX=m
+CONFIG_HID_RETRODE=m
+CONFIG_HID_ROCCAT=m
+CONFIG_HID_SAITEK=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SEMITEK=m
+CONFIG_HID_SIGMAMICRO=m
+CONFIG_HID_SONY=m
+CONFIG_SONY_FF=y
+CONFIG_HID_SPEEDLINK=m
+CONFIG_HID_STEAM=m
+CONFIG_STEAM_FF=y
+CONFIG_HID_STEELSERIES=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_HID_RMI=m
+CONFIG_HID_GREENASIA=m
+CONFIG_GREENASIA_FF=y
+CONFIG_HID_HYPERV_MOUSE=m
+CONFIG_HID_SMARTJOYPLUS=m
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TIVO=m
+CONFIG_HID_TOPSEED=m
+CONFIG_HID_TOPRE=m
+CONFIG_HID_THINGM=m
+CONFIG_HID_TMFF_NEW=m
+CONFIG_HID_UDRAW_PS3=m
+CONFIG_HID_U2FZERO=m
+CONFIG_HID_UNIVERSAL_PIDFF=m
+CONFIG_HID_WACOM=m
+CONFIG_HID_WIIMOTE=m
+CONFIG_HID_WINWING=m
+CONFIG_HID_XINMO=m
+CONFIG_HID_ZEROPLUS=m
+CONFIG_ZEROPLUS_FF=y
+CONFIG_HID_ZYDACRON=m
+CONFIG_HID_SENSOR_HUB=m
+CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
+CONFIG_HID_ALPS=m
+CONFIG_HID_MCP2200=m
+CONFIG_HID_MCP2221=m
+CONFIG_SURFACE_HID=m
+CONFIG_SURFACE_KBD=m
+# end of Special HID drivers
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=m
+CONFIG_HID_PID=y
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+# end of USB HID Boot Protocol drivers
+# end of USB HID support
+
+#
+# I2C HID support
+#
+CONFIG_I2C_HID=m
+CONFIG_I2C_HID_OF=m
+CONFIG_I2C_HID_OF_ELAN=m
+CONFIG_USB_ONBOARD_HUB=m
+CONFIG_I2C_HID_OF_GOODIX=m
+CONFIG_I2C_HID_ACPI=m
+# end of I2C HID support
+# end of HID support
+
+CONFIG_RMI4_CORE=m
+CONFIG_RMI4_I2C=m
+CONFIG_RMI4_SPI=m
+CONFIG_RMI4_SMB=m
+CONFIG_RMI4_F03=y
+CONFIG_RMI4_F11=y
+CONFIG_RMI4_F12=y
+CONFIG_RMI4_F1A=y
+CONFIG_RMI4_F21=y
+CONFIG_RMI4_F30=y
+CONFIG_RMI4_F34=y
+CONFIG_RMI4_F3A=y
+CONFIG_RMI4_F54=y
+CONFIG_RMI4_F55=y
diff --git a/i686-desktop-gcc-omv-defconfig b/i386-omv-defconfig
similarity index 52%
rename from i686-desktop-gcc-omv-defconfig
rename to i386-omv-defconfig
index 03b77d9..bbf5fed 100644
--- a/i686-desktop-gcc-omv-defconfig
+++ b/i386-omv-defconfig
@@ -1,8675 +1,806 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# Linux/i386 5.10.0-rc1 Kernel Configuration
-#
-CONFIG_CC_VERSION_TEXT="gcc (GCC) 10.2.0 20200723 (OpenMandriva)"
-CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=100200
-CONFIG_LD_VERSION=235010000
-CONFIG_CLANG_VERSION=0
-CONFIG_CC_CAN_LINK=y
-CONFIG_CC_CAN_LINK_STATIC=y
-CONFIG_CC_HAS_ASM_GOTO=y
-CONFIG_CC_HAS_ASM_INLINE=y
-CONFIG_IRQ_WORK=y
-CONFIG_BUILDTIME_TABLE_SORT=y
-CONFIG_THREAD_INFO_IN_TASK=y
-
-#
-# General setup
-#
-CONFIG_INIT_ENV_ARG_LIMIT=32
-# CONFIG_COMPILE_TEST is not set
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_BUILD_SALT="c5a5e571e4bde848c6c8a2b691b08c7ffb4e1a11"
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_BZIP2=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_ZSTD=y
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_BZIP2 is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_KERNEL_ZSTD=y
-CONFIG_DEFAULT_INIT=""
-CONFIG_DEFAULT_HOSTNAME="omv"
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_POSIX_MQUEUE_SYSCTL=y
-# CONFIG_WATCH_QUEUE is not set
-CONFIG_CROSS_MEMORY_ATTACH=y
-# CONFIG_USELIB is not set
-# CONFIG_AUDIT is not set
-# CONFIG_HAVE_ARCH_AUDITSYSCALL is not set
-# CONFIG_AUDITSYSCALL is not set
-
-#
-# IRQ subsystem
-#
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_SIM=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
-CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_SPARSE_IRQ=y
-# CONFIG_GENERIC_IRQ_DEBUGFS is not set
-# end of IRQ subsystem
-
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-CONFIG_ARCH_CLOCKSOURCE_INIT=y
-CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-
-#
-# Timers subsystem
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ_COMMON=y
-# CONFIG_HZ_PERIODIC is not set
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
-# end of Timers subsystem
-
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_COUNT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_DYNAMIC=y
-CONFIG_CPU_SUP_VORTEX_32=y
-CONFIG_SCHED_CORE=y
-
-#
-# CPU/Task time and stats accounting
-#
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_SCHED_AVG_IRQ=y
-CONFIG_BSD_PROCESS_ACCT=y
-# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_PSI=y
-# CONFIG_PSI_DEFAULT_DISABLED is not set
-# end of CPU/Task time and stats accounting
-
-CONFIG_CPU_ISOLATION=y
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-CONFIG_PREEMPT_RCU=y
-# CONFIG_RCU_EXPERT is not set
-CONFIG_SRCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TASKS_RCU_GENERIC=y
-CONFIG_TASKS_RCU=y
-CONFIG_TASKS_RUDE_RCU=y
-CONFIG_TASKS_TRACE_RCU=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RCU_NEED_SEGCBLIST=y
-# end of RCU Subsystem
-
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-# CONFIG_IKHEADERS is not set
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
-CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
-CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
-
-#
-# Scheduler features
-#
-# CONFIG_UCLAMP_TASK is not set
-# end of Scheduler features
-
-CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
-CONFIG_CGROUPS=y
-CONFIG_PAGE_COUNTER=y
-CONFIG_MEMCG=y
-CONFIG_MEMCG_SWAP=y
-CONFIG_MEMCG_KMEM=y
-CONFIG_BLK_CGROUP=y
-CONFIG_CGROUP_WRITEBACK=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_CFS_BANDWIDTH=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_CGROUP_PIDS=y
-CONFIG_CGROUP_RDMA=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_HUGETLB=y
-CONFIG_CPUSETS=y
-CONFIG_PROC_PID_CPUSET=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_PERF=y
-CONFIG_CGROUP_BPF=y
-CONFIG_CGROUP_MISC=y
-# CONFIG_CGROUP_DEBUG is not set
-CONFIG_SOCK_CGROUP_DATA=y
-CONFIG_NAMESPACES=y
-CONFIG_UTS_NS=y
-CONFIG_TIME_NS=y
-CONFIG_IPC_NS=y
-CONFIG_USER_NS=y
-CONFIG_PID_NS=y
-CONFIG_NET_NS=y
-CONFIG_CHECKPOINT_RESTORE=y
-CONFIG_SCHED_AUTOGROUP=y
-# CONFIG_SYSFS_DEPRECATED is not set
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_XZ=y
-CONFIG_RD_LZO=y
-CONFIG_RD_LZ4=y
-CONFIG_RD_ZSTD=y
-CONFIG_BOOT_CONFIG=y
-# CONFIG_CC_OPTIMIZE_BASAL is not set
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_HAVE_UID16=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_HAVE_PCSPKR_PLATFORM=y
-CONFIG_BPF=y
-CONFIG_EXPERT=y
-CONFIG_UID16=y
-CONFIG_MULTIUSER=y
-CONFIG_SGETMASK_SYSCALL=y
-# CONFIG_SYSFS_SYSCALL is not set
-CONFIG_FHANDLE=y
-CONFIG_POSIX_TIMERS=y
-CONFIG_PRINTK=y
-CONFIG_PRINTK_NMI=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_PCSPKR_PLATFORM=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_FUTEX_PI=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_IO_URING=y
-CONFIG_ADVISE_SYSCALLS=y
-CONFIG_MEMBARRIER=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_BASE_RELATIVE=y
-CONFIG_BPF_SYSCALL=y
-CONFIG_BPF_JIT_ALWAYS_ON=y
-# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
-CONFIG_BPF_JIT_DEFAULT_ON=y
-CONFIG_USERMODE_DRIVER=y
-# CONFIG_BPF_PRELOAD is not set
-CONFIG_USERFAULTFD=y
-CONFIG_LRU_GEN=y
-CONFIG_LRU_GEN_ENABLED=y
-# CONFIG_LRU_GEN_STATS is not set
-CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
-CONFIG_RSEQ=y
-# CONFIG_DEBUG_RSEQ is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_HAVE_PERF_EVENTS=y
-# CONFIG_PC104 is not set
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_PERF_EVENTS=y
-# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
-# end of Kernel Performance Events And Counters
-
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_SLUB_MEMCG_SYSFS_ON is not set
-# CONFIG_COMPAT_BRK is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-CONFIG_SLAB_MERGE_DEFAULT=y
-CONFIG_SLAB_FREELIST_RANDOM=y
-CONFIG_SLAB_FREELIST_HARDENED=y
-CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
-CONFIG_SLUB_CPU_PARTIAL=y
-CONFIG_SYSTEM_DATA_VERIFICATION=y
-# CONFIG_PROFILING is not set
-CONFIG_TRACEPOINTS=y
-# end of General setup
-
-CONFIG_X86_32=y
-CONFIG_FORCE_DYNAMIC_FTRACE=y
-CONFIG_X86=y
-CONFIG_INSTRUCTION_DECODER=y
-CONFIG_OUTPUT_FORMAT="elf32-i386"
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_MMU=y
-CONFIG_ARCH_MMAP_RND_BITS_MIN=8
-CONFIG_ARCH_MMAP_RND_BITS_MAX=16
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_BUG=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_HAS_CPU_RELAX=y
-CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
-CONFIG_ARCH_HAS_FILTER_PGPROT=y
-CONFIG_HAVE_SETUP_PER_CPU_AREA=y
-CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
-CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-# CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC is not set
-CONFIG_HAVE_INTEL_TXT=y
-CONFIG_X86_32_SMP=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_CC_HAS_SANE_STACKPROTECTOR=y
-
-#
-# Processor type and features
-#
-CONFIG_ZONE_DMA=y
-CONFIG_SMP=y
-CONFIG_X86_FEATURE_NAMES=y
-CONFIG_X86_MPPARSE=y
-# CONFIG_GOLDFISH is not set
-CONFIG_RETPOLINE=y
-CONFIG_RETHUNK=y
-CONFIG_SLS=y
-CONFIG_X86_CPU_RESCTRL=y
-CONFIG_X86_BIGSMP=y
-# CONFIG_X86_EXTENDED_PLATFORM is not set
-CONFIG_X86_INTEL_LPSS=y
-CONFIG_X86_AMD_PLATFORM_DEVICE=y
-CONFIG_IOSF_MBI=y
-# CONFIG_IOSF_MBI_DEBUG is not set
-CONFIG_X86_32_IRIS=m
-CONFIG_SCHED_OMIT_FRAME_POINTER=y
-CONFIG_HYPERVISOR_GUEST=y
-CONFIG_PARAVIRT=y
-# CONFIG_PARAVIRT_DEBUG is not set
-# CONFIG_PARAVIRT_SPINLOCKS is not set
-CONFIG_X86_HV_CALLBACK_VECTOR=y
-# CONFIG_XEN is not set
-CONFIG_KVM_GUEST=y
-CONFIG_ARCH_CPUIDLE_HALTPOLL=y
-CONFIG_PVH=y
-# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
-CONFIG_PARAVIRT_CLOCK=y
-# CONFIG_M486SX is not set
-# CONFIG_M486 is not set
-# CONFIG_M586 is not set
-# CONFIG_M586TSC is not set
-# CONFIG_M586MMX is not set
-CONFIG_M686=y
-# CONFIG_MPENTIUMII is not set
-# CONFIG_MPENTIUMIII is not set
-# CONFIG_MPENTIUMM is not set
-# CONFIG_MPENTIUM4 is not set
-# CONFIG_MK6 is not set
-# CONFIG_MK7 is not set
-# CONFIG_MK8 is not set
-# CONFIG_MK8SSE3 is not set
-# CONFIG_MK10 is not set
-# CONFIG_MBARCELONA is not set
-# CONFIG_MBOBCAT is not set
-# CONFIG_MJAGUAR is not set
-# CONFIG_MBULLDOZER is not set
-# CONFIG_MPILEDRIVER is not set
-# CONFIG_MSTEAMROLLER is not set
-# CONFIG_MEXCAVATOR is not set
-# CONFIG_MZEN is not set
-# CONFIG_MZEN2 is not set
-# CONFIG_MZEN3 is not set
-# CONFIG_MCRUSOE is not set
-# CONFIG_MEFFICEON is not set
-# CONFIG_MWINCHIPC6 is not set
-# CONFIG_MWINCHIP3D is not set
-# CONFIG_MELAN is not set
-# CONFIG_MGEODEGX1 is not set
-# CONFIG_MGEODE_LX is not set
-# CONFIG_MCYRIXIII is not set
-# CONFIG_MVIAC3_2 is not set
-# CONFIG_MVIAC7 is not set
-# CONFIG_MATOM is not set
-# CONFIG_MCORE2 is not set
-# CONFIG_MNEHALEM is not set
-# CONFIG_MWESTMERE is not set
-# CONFIG_MSILVERMONT is not set
-# CONFIG_MGOLDMONT is not set
-# CONFIG_MGOLDMONTPLUS is not set
-# CONFIG_MSANDYBRIDGE is not set
-# CONFIG_MIVYBRIDGE is not set
-# CONFIG_MHASWELL is not set
-# CONFIG_MBROADWELL is not set
-# CONFIG_MSKYLAKE is not set
-# CONFIG_MSKYLAKEX is not set
-# CONFIG_MCANNONLAKE is not set
-# CONFIG_MICELAKE is not set
-# CONFIG_MCASCADELAKE is not set
-# CONFIG_MCOOPERLAKE is not set
-# CONFIG_MTIGERLAKE is not set
-# CONFIG_MSAPPHIRERAPIDS is not set
-# CONFIG_MROCKETLAKE is not set
-# CONFIG_MALDERLAKE is not set
-# CONFIG_MNATIVE_INTEL is not set
-# CONFIG_MNATIVE_AMD is not set
-# CONFIG_MNATIVE is not set
-# CONFIG_GENERIC_CPU2 is not set
-# CONFIG_GENERIC_CPU3 is not set
-# CONFIG_GENERIC_CPU4 is not set
-CONFIG_X86_GENERIC=y
-CONFIG_X86_INTERNODE_CACHE_SHIFT=6
-CONFIG_X86_L1_CACHE_SHIFT=6
-CONFIG_X86_INTEL_USERCOPY=y
-CONFIG_X86_USE_PPRO_CHECKSUM=y
-CONFIG_X86_TSC=y
-CONFIG_X86_CMPXCHG64=y
-CONFIG_X86_CMOV=y
-CONFIG_X86_MINIMUM_CPU_FAMILY=6
-CONFIG_X86_DEBUGCTLMSR=y
-CONFIG_IA32_FEAT_CTL=y
-CONFIG_X86_VMX_FEATURE_NAMES=y
-CONFIG_PROCESSOR_SELECT=y
-CONFIG_CPU_SUP_INTEL=y
-CONFIG_CPU_SUP_CYRIX_32=y
-CONFIG_CPU_SUP_AMD=y
-CONFIG_CPU_SUP_HYGON=y
-CONFIG_CPU_SUP_CENTAUR=y
-CONFIG_CPU_SUP_TRANSMETA_32=y
-CONFIG_CPU_SUP_UMC_32=y
-CONFIG_CPU_SUP_ZHAOXIN=y
-CONFIG_HPET_TIMER=y
-CONFIG_HPET_EMULATE_RTC=y
-CONFIG_DMI=y
-CONFIG_NR_CPUS_RANGE_BEGIN=2
-CONFIG_NR_CPUS_RANGE_END=64
-CONFIG_NR_CPUS_DEFAULT=32
-CONFIG_NR_CPUS=32
-CONFIG_SCHED_CLUSTER=y
-CONFIG_SCHED_SMT=y
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_MC_PRIO=y
-CONFIG_X86_LOCAL_APIC=y
-CONFIG_X86_IO_APIC=y
-CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
-CONFIG_X86_MCE=y
-# CONFIG_X86_MCELOG_LEGACY is not set
-CONFIG_X86_MCE_INTEL=y
-CONFIG_X86_MCE_AMD=y
-CONFIG_X86_ANCIENT_MCE=y
-CONFIG_X86_MCE_THRESHOLD=y
-# CONFIG_X86_MCE_INJECT is not set
-CONFIG_X86_THERMAL_VECTOR=y
-
-#
-# Performance monitoring
-#
-CONFIG_PERF_EVENTS_INTEL_UNCORE=m
-CONFIG_PERF_EVENTS_INTEL_RAPL=m
-CONFIG_PERF_EVENTS_INTEL_CSTATE=m
-CONFIG_PERF_EVENTS_AMD_POWER=m
-CONFIG_PERF_EVENTS_AMD_UNCORE=m
-CONFIG_PERF_EVENTS_AMD_BRS=y
-# end of Performance monitoring
-
-CONFIG_X86_LEGACY_VM86=y
-CONFIG_VM86=y
-CONFIG_X86_16BIT=y
-CONFIG_X86_ESPFIX32=y
-CONFIG_X86_IOPL_IOPERM=y
-CONFIG_TOSHIBA=m
-CONFIG_I8K=m
-CONFIG_X86_REBOOTFIXUPS=y
-CONFIG_MICROCODE=y
-CONFIG_MICROCODE_INTEL=y
-CONFIG_MICROCODE_AMD=y
-# CONFIG_MICROCODE_LATE_LOADING is not set
-# CONFIG_MICROCODE_OLD_INTERFACE is not set
-CONFIG_X86_MSR=m
-CONFIG_X86_CPUID=m
-# CONFIG_NOHIGHMEM is not set
-# CONFIG_HIGHMEM4G is not set
-CONFIG_HIGHMEM64G=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_HIGHMEM=y
-CONFIG_X86_PAE=y
-# CONFIG_X86_CPA_STATISTICS is not set
-CONFIG_NUMA=y
-# CONFIG_NUMA_EMU is not set
-CONFIG_NODES_SHIFT=10
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ILLEGAL_POINTER_VALUE=0
-CONFIG_X86_PMEM_LEGACY_DEVICE=y
-CONFIG_X86_PMEM_LEGACY=m
-CONFIG_HIGHPTE=y
-CONFIG_X86_CHECK_BIOS_CORRUPTION=y
-CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y
-CONFIG_X86_RESERVE_LOW=64
-CONFIG_MTRR=y
-CONFIG_MTRR_SANITIZER=y
-CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0
-CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
-CONFIG_X86_PAT=y
-CONFIG_ARCH_USES_PG_UNCACHED=y
-CONFIG_ARCH_RANDOM=y
-CONFIG_X86_SMAP=y
-CONFIG_X86_UMIP=y
-CONFIG_X86_KERNEL_IBT=y
-CONFIG_X86_INTEL_TSX_MODE_OFF=y
-# CONFIG_X86_INTEL_TSX_MODE_ON is not set
-# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set
-CONFIG_EFI=y
-CONFIG_EFI_STUB=y
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_250 is not set
-# CONFIG_HZ_300 is not set
-CONFIG_HZ_1000=y
-CONFIG_HZ=1000
-CONFIG_ARCH_FORCE_MAX_ORDER=12
-CONFIG_SCHED_HRTICK=y
-CONFIG_KEXEC=y
-# CONFIG_CRASH_DUMP is not set
-CONFIG_KEXEC_JUMP=y
-CONFIG_PHYSICAL_START=0x1000000
-CONFIG_RELOCATABLE=y
-CONFIG_RANDOMIZE_BASE=y
-CONFIG_X86_NEED_RELOCS=y
-CONFIG_PHYSICAL_ALIGN=0x1000000
-CONFIG_HOTPLUG_CPU=y
-CONFIG_BOOTPARAM_HOTPLUG_CPU0=y
-# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
-# CONFIG_COMPAT_VDSO is not set
-# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
-# CONFIG_CMDLINE_BOOL is not set
-CONFIG_MODIFY_LDT_SYSCALL=y
-# CONFIG_STRICT_SIGALTSTACK_SIZE is not set
-# end of Processor type and features
-
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_USE_PERCPU_NUMA_NODE_ID=y
-CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
-
-#
-# Power management and ACPI options
-#
-CONFIG_ARCH_HIBERNATION_HEADER=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_SUSPEND_SKIP_SYNC is not set
-CONFIG_HIBERNATE_CALLBACKS=y
-CONFIG_HIBERNATION=y
-CONFIG_HIBERNATION_SNAPSHOT_DEV=y
-CONFIG_PM_STD_PARTITION=""
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_PM_AUTOSLEEP=y
-CONFIG_PM_WAKELOCKS=y
-CONFIG_PM_WAKELOCKS_LIMIT=100
-CONFIG_PM_WAKELOCKS_GC=y
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_ENERGY_MODEL=y
-CONFIG_ARCH_SUPPORTS_ACPI=y
-CONFIG_ACPI=y
-CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
-CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
-CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
-# CONFIG_ACPI_DEBUGGER is not set
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_FPDT=y
-CONFIG_ACPI_SLEEP=y
-CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
-# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_60XX_WDT=m
+CONFIG_842_COMPRESS=y
+CONFIG_842_DECOMPRESS=y
+CONFIG_88PM886_GPADC=m
+CONFIG_ABP060MG=m
+CONFIG_AC97_BUS=m
+CONFIG_ACERHDF=m
+CONFIG_ACER_WIRELESS=m
+CONFIG_ACER_WMI=m
+CONFIG_ACORN_PARTITION_ADFS=y
+CONFIG_ACORN_PARTITION_CUMANA=y
+CONFIG_ACORN_PARTITION_EESOX=y
+CONFIG_ACORN_PARTITION_ICS=y
+CONFIG_ACORN_PARTITION_POWERTEC=y
+CONFIG_ACORN_PARTITION_RISCIX=y
+CONFIG_ACORN_PARTITION=y
 CONFIG_ACPI_AC=m
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_PCIEAER=y
+CONFIG_ACPI_APEI=y
 CONFIG_ACPI_BATTERY=m
+CONFIG_ACPI_BGRT=y
 CONFIG_ACPI_BUTTON=m
-CONFIG_ACPI_VIDEO=m
-CONFIG_ACPI_TINY_POWER_BUTTON=m
-CONFIG_ACPI_TINY_POWER_BUTTON_SIGNAL=38
-CONFIG_ACPI_VIDEO=m
-CONFIG_ACPI_FAN=m
-CONFIG_ACPI_TAD=m
-CONFIG_ACPI_DOCK=y
+CONFIG_ACPI_CMPC=m
+CONFIG_ACPI_CONFIGFS=m
+CONFIG_ACPI_CONTAINER=y
 CONFIG_ACPI_CPU_FREQ_PSS=y
+CONFIG_ACPI_DOCK=y
+CONFIG_ACPI_DPTF=y
+CONFIG_ACPI_EXTLOG=m
+CONFIG_ACPI_FAN=m
+CONFIG_ACPI_FFH=y
+CONFIG_ACPI_HED=y
+CONFIG_ACPI_HMAT=y
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_HOTPLUG_IOAPIC=y
+CONFIG_ACPI_IPMI=m
+CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
+CONFIG_ACPI_MDIO=m
+CONFIG_ACPI_NUMA=y
+CONFIG_ACPI_PCC=y
+CONFIG_ACPI_PCI_SLOT=y
+CONFIG_ACPI_PLATFORM_PROFILE=m
+CONFIG_ACPI_PROCESSOR_AGGREGATOR=m
 CONFIG_ACPI_PROCESSOR_CSTATE=y
 CONFIG_ACPI_PROCESSOR_IDLE=y
 CONFIG_ACPI_PROCESSOR=y
-CONFIG_ACPI_IPMI=m
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_PROCESSOR_AGGREGATOR=m
-CONFIG_ACPI_THERMAL=m
-CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
-CONFIG_ACPI_TABLE_UPGRADE=y
-# CONFIG_ACPI_DEBUG is not set
-CONFIG_ACPI_PCI_SLOT=y
-CONFIG_ACPI_CONTAINER=y
-CONFIG_ACPI_HOTPLUG_IOAPIC=y
+CONFIG_ACPI_QUICKSTART=m
+CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
 CONFIG_ACPI_SBS=m
-CONFIG_ACPI_HED=y
-# CONFIG_ACPI_CUSTOM_METHOD is not set
-CONFIG_ACPI_BGRT=y
-# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
-CONFIG_ACPI_NUMA=y
-CONFIG_ACPI_HMAT=y
-CONFIG_HAVE_ACPI_APEI=y
-CONFIG_HAVE_ACPI_APEI_NMI=y
-CONFIG_ACPI_APEI=y
-CONFIG_ACPI_APEI_GHES=y
-CONFIG_ACPI_APEI_PCIEAER=y
-# CONFIG_ACPI_APEI_EINJ is not set
-# CONFIG_ACPI_APEI_ERST_DEBUG is not set
-CONFIG_ACPI_DPTF=y
-CONFIG_DPTF_POWER=m
-CONFIG_DPTF_PCH_FIVR=m
+CONFIG_ACPI_SLEEP=y
+CONFIG_ACPI_SPCR_TABLE=y
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+CONFIG_ACPI_TABLE_LIB=y
+CONFIG_ACPI_TABLE_UPGRADE=y
+CONFIG_ACPI_TAD=m
+CONFIG_ACPI_THERMAL=m
+CONFIG_ACPI_TINY_POWER_BUTTON=m
+CONFIG_ACPI_TINY_POWER_BUTTON_SIGNAL=38
+CONFIG_ACPI_TOSHIBA=m
+CONFIG_ACPI_VIDEO=m
+CONFIG_ACPI_VIOT=y
 CONFIG_ACPI_WATCHDOG=y
-CONFIG_ACPI_EXTLOG=m
-CONFIG_ACPI_CONFIGFS=m
-CONFIG_ACPI_PFRUT=m
-CONFIG_ACPI_PCC=y
-CONFIG_ACPI_PRMT=y
-CONFIG_TPS68470_PMIC_OPREGION=y
-CONFIG_PMIC_OPREGION=y
-# CONFIG_XPOWER_PMIC_OPREGION is not set
-# CONFIG_BXT_WC_PMIC_OPREGION is not set
-CONFIG_CHT_DC_TI_PMIC_OPREGION=y
-CONFIG_X86_PM_TIMER=y
-CONFIG_ACPI_PRMT=y
-CONFIG_SFI=y
-CONFIG_X86_APM_BOOT=y
-CONFIG_APM=m
-# CONFIG_APM_IGNORE_USER_SUSPEND is not set
-# CONFIG_APM_DO_ENABLE is not set
-# CONFIG_APM_CPU_IDLE is not set
-# CONFIG_APM_DISPLAY_BLANK is not set
-# CONFIG_APM_ALLOW_INTS is not set
-
-#
-# CPU Frequency scaling
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-
-#
-# CPU frequency scaling drivers
-#
-CONFIG_X86_INTEL_PSTATE=y
-CONFIG_X86_PCC_CPUFREQ=m
-CONFIG_X86_AMD_PSTATE=y
-CONFIG_X86_AMD_PSTATE_UT=m
-CONFIG_X86_ACPI_CPUFREQ=m
-CONFIG_X86_ACPI_CPUFREQ_CPB=y
-CONFIG_X86_POWERNOW_K6=m
-CONFIG_X86_POWERNOW_K7=m
-CONFIG_X86_POWERNOW_K7_ACPI=y
-CONFIG_X86_POWERNOW_K8=m
-CONFIG_X86_AMD_FREQ_SENSITIVITY=m
-CONFIG_X86_GX_SUSPMOD=m
-# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
-CONFIG_X86_SPEEDSTEP_ICH=m
-CONFIG_X86_SPEEDSTEP_SMI=m
-# CONFIG_X86_P4_CLOCKMOD is not set
-CONFIG_X86_CPUFREQ_NFORCE2=m
-CONFIG_X86_LONGRUN=m
-CONFIG_X86_LONGHAUL=m
-CONFIG_X86_E_POWERSAVER=m
-
-#
-# shared options
-#
-CONFIG_X86_SPEEDSTEP_LIB=m
-# CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK is not set
-# end of CPU Frequency scaling
-
-#
-# CPU Idle
-#
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-# CONFIG_CPU_IDLE_GOV_TEO is not set
-# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set
-CONFIG_HALTPOLL_CPUIDLE=y
-# end of CPU Idle
-
-CONFIG_INTEL_IDLE=y
-# end of Power management and ACPI options
-
-#
-# Bus options (PCI etc.)
-#
-# CONFIG_PCI_GOBIOS is not set
-# CONFIG_PCI_GOMMCONFIG is not set
-# CONFIG_PCI_GODIRECT is not set
-CONFIG_PCI_GOANY=y
-CONFIG_PCI_BIOS=y
-CONFIG_PCI_DIRECT=y
-CONFIG_PCI_MMCONFIG=y
-# CONFIG_PCI_CNB20LE_QUIRK is not set
-# CONFIG_ISA_BUS is not set
-CONFIG_ISA_DMA_API=y
-CONFIG_ISA=y
-# CONFIG_SCx200 is not set
-# CONFIG_ALIX is not set
-# CONFIG_NET5501 is not set
-# CONFIG_GEOS is not set
+CONFIG_ACPI_WMI_LEGACY_DEVICE_NAMES=y
+CONFIG_ACPI_WMI=m
+CONFIG_ACPI=y
+CONFIG_ACQUIRE_WDT=m
+CONFIG_AD2S1200=m
+CONFIG_AD2S1210=m
+CONFIG_AD2S90=m
+CONFIG_AD3552R=m
+CONFIG_AD4000=m
+CONFIG_AD4030=m
+CONFIG_AD4080=m
+CONFIG_AD4130=m
+CONFIG_AD4170_4=m
+CONFIG_AD4695=m
+CONFIG_AD4851=m
+CONFIG_AD5064=m
+CONFIG_AD5110=m
+CONFIG_AD525X_DPOT_I2C=m
+CONFIG_AD525X_DPOT=m
+CONFIG_AD525X_DPOT_SPI=m
+CONFIG_AD5272=m
+CONFIG_AD5360=m
+CONFIG_AD5380=m
+CONFIG_AD5421=m
+CONFIG_AD5446=m
+CONFIG_AD5449=m
+CONFIG_AD5504=m
+CONFIG_AD5592R_BASE=m
+CONFIG_AD5592R=m
+CONFIG_AD5593R=m
+CONFIG_AD5624R_SPI=m
+CONFIG_AD5686=m
+CONFIG_AD5686_SPI=m
+CONFIG_AD5696_I2C=m
+CONFIG_AD5755=m
+CONFIG_AD5758=m
+CONFIG_AD5761=m
+CONFIG_AD5764=m
+CONFIG_AD5766=m
+CONFIG_AD5770R=m
+CONFIG_AD5791=m
+CONFIG_AD5933=m
+CONFIG_AD7091R5=m
+CONFIG_AD7091R8=m
+CONFIG_AD7124=m
+CONFIG_AD7150=m
+CONFIG_AD7173=m
+CONFIG_AD7191=m
+CONFIG_AD7192=m
+CONFIG_AD7266=m
+CONFIG_AD7280=m
+CONFIG_AD7291=m
+CONFIG_AD7292=m
+CONFIG_AD7293=m
+CONFIG_AD7298=m
+CONFIG_AD7303=m
+CONFIG_AD7380=m
+CONFIG_AD7405=m
+CONFIG_AD74115=m
+CONFIG_AD74413R=m
+CONFIG_AD7476=m
+CONFIG_AD7606_IFACE_PARALLEL=m
+CONFIG_AD7606_IFACE_SPI=m
+CONFIG_AD7606=m
+CONFIG_AD7746=m
+CONFIG_AD7766=m
+CONFIG_AD7768_1=m
+CONFIG_AD7780=m
+CONFIG_AD7791=m
+CONFIG_AD7793=m
+CONFIG_AD7816=m
+CONFIG_AD7887=m
+CONFIG_AD7923=m
+CONFIG_AD7944=m
+CONFIG_AD7949=m
+CONFIG_AD799X=m
+CONFIG_AD8366=m
+CONFIG_AD8801=m
+CONFIG_AD9467=m
+CONFIG_AD9523=m
+CONFIG_AD9739A=m
+CONFIG_AD9832=m
+CONFIG_AD9834=m
+CONFIG_ADA4250=m
+CONFIG_ADE9000=m
+CONFIG_ADF4350=m
+CONFIG_ADF4371=m
+CONFIG_ADF4377=m
+CONFIG_ADI_AXI_ADC=m
+CONFIG_ADI_AXI_DAC=m
+CONFIG_ADI_I3C_MASTER=m
+CONFIG_ADIN1100_PHY=m
+CONFIG_ADIN_PHY=m
+CONFIG_ADIS16080=m
+CONFIG_ADIS16130=m
+CONFIG_ADIS16136=m
+CONFIG_ADIS16201=m
+CONFIG_ADIS16203=m
+CONFIG_ADIS16209=m
+CONFIG_ADIS16240=m
+CONFIG_ADIS16260=m
+CONFIG_ADIS16400=m
+CONFIG_ADIS16460=m
+CONFIG_ADIS16475=m
+CONFIG_ADIS16480=m
+CONFIG_ADIS16550=m
+CONFIG_ADJD_S311=m
+CONFIG_ADM8211=m
+CONFIG_ADMFM2000=m
+CONFIG_ADMV1013=m
+CONFIG_ADMV4420=m
+CONFIG_ADRF6780=m
+CONFIG_AD_SIGMA_DELTA=m
+CONFIG_ADT7316_I2C=m
+CONFIG_ADT7316=m
+CONFIG_ADT7316_SPI=m
+CONFIG_ADUX1020=m
+CONFIG_ADVANTECH_EC_WDT=m
+CONFIG_ADVANTECH_WDT=m
+CONFIG_ADV_SWBUTTON=m
+CONFIG_ADXL313_I2C=m
+CONFIG_ADXL313=m
+CONFIG_ADXL313_SPI=m
+CONFIG_ADXL355_I2C=m
+CONFIG_ADXL355=m
+CONFIG_ADXL355_SPI=m
+CONFIG_ADXL367_I2C=m
+CONFIG_ADXL367=m
+CONFIG_ADXL367_SPI=m
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372=m
+CONFIG_ADXL372_SPI=m
+CONFIG_ADXL380_I2C=m
+CONFIG_ADXL380_SPI=m
+CONFIG_ADXRS290=m
+CONFIG_ADXRS450=m
+CONFIG_AF8133J=m
+CONFIG_AFE4403=m
+CONFIG_AFE4404=m
+CONFIG_AF_KCM=m
+CONFIG_AF_RXRPC=m
+CONFIG_AGP_AMD64=m
+CONFIG_AGP_INTEL=m
+CONFIG_AGP=m
+CONFIG_AGP_SIS=m
+CONFIG_AGP_VIA=m
+CONFIG_AHCI_DWC=m
+CONFIG_AIC79XX_CMDS_PER_DEVICE=4
+CONFIG_AIC79XX_DEBUG_MASK=0
+CONFIG_AIC79XX_RESET_DELAY_MS=15000
+CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
+CONFIG_AIC7XXX_DEBUG_MASK=0
+CONFIG_AIC7XXX_RESET_DELAY_MS=15000
+CONFIG_AIRO_CS=m
+CONFIG_AIRO=m
+CONFIG_AIX_PARTITION=y
+CONFIG_AK09911=m
+CONFIG_AK8974=m
+CONFIG_AK8975=m
+CONFIG_AL3000A=m
+CONFIG_AL3010=m
+CONFIG_AL3320A=m
+CONFIG_ALIBABA_ENI_VDPA=m
+CONFIG_ALIENWARE_WMI_LEGACY=y
+CONFIG_ALIENWARE_WMI=m
+CONFIG_ALIENWARE_WMI_WMAX=y
+CONFIG_ALIM1535_WDT=m
+CONFIG_ALIM7101_WDT=m
+CONFIG_ALTERA_FREEZE_BRIDGE=m
+CONFIG_ALTERA_MBOX=m
+CONFIG_ALTERA_MSGDMA=m
+CONFIG_ALTERA_PR_IP_CORE=m
+CONFIG_ALTERA_STAPL=m
+CONFIG_AM2315=m
+CONFIG_AMD_HFI=y
+CONFIG_AMD_MP2_STB=y
 CONFIG_AMD_NB=y
-CONFIG_X86_SYSFB=y
-# end of Bus options (PCI etc.)
-
-#
-# Binary Emulations
-#
-CONFIG_COMPAT_32=y
-# end of Binary Emulations
-
-CONFIG_HAVE_ATOMIC_IOMAP=y
-
-#
-# Firmware Drivers
-#
-CONFIG_EDD=m
-# CONFIG_EDD_OFF is not set
-CONFIG_FIRMWARE_MEMMAP=y
-CONFIG_DMIID=y
-CONFIG_DMI_SYSFS=m
-CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
-CONFIG_ISCSI_IBFT_FIND=y
-CONFIG_ISCSI_IBFT=m
-CONFIG_FW_CFG_SYSFS=m
-# CONFIG_FW_CFG_SYSFS_CMDLINE is not set
-CONFIG_SYSFB_SIMPLEFB=y
-CONFIG_GOOGLE_FIRMWARE=y
-CONFIG_GOOGLE_SMI=m
-CONFIG_GOOGLE_COREBOOT_TABLE=m
-CONFIG_GOOGLE_MEMCONSOLE=m
-CONFIG_GOOGLE_MEMCONSOLE_X86_LEGACY=m
-CONFIG_GOOGLE_FRAMEBUFFER_COREBOOT=m
-CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m
-CONFIG_GOOGLE_VPD=m
-
-#
-# EFI (Extensible Firmware Interface) Support
-#
-CONFIG_EFI_VARS=m
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_VARS_PSTORE=m
-CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
-CONFIG_EFI_RUNTIME_MAP=y
-# CONFIG_EFI_FAKE_MEMMAP is not set
-CONFIG_EFI_SOFT_RESERVE=y
-CONFIG_EFI_ZBOOT=y
-# CONFIG_EFI_ZBOOT_SIGNING is not set
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
-CONFIG_EFI_BOOTLOADER_CONTROL=m
-CONFIG_EFI_CAPSULE_LOADER=y
-CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH=y
-CONFIG_EFI_TEST=m
+CONFIG_AMD_PHY=m
+CONFIG_AMD_PMC=m
+CONFIG_AMD_PMF=m
+CONFIG_AMD_QDMA=m
+CONFIG_AMD_WBRF=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_AMILO_RFKILL=m
+CONFIG_AMT=m
+CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
+CONFIG_ANDROID_BINDERFS=y
+CONFIG_ANDROID_BINDER_IPC=m
+CONFIG_AOSONG_AGS02MA=m
+CONFIG_APDS9160=m
+CONFIG_APDS9300=m
+CONFIG_APDS9306=m
+CONFIG_APDS9802ALS=m
+CONFIG_APDS9960=m
+CONFIG_APERTURE_HELPERS=y
+CONFIG_APM=m
+CONFIG_APPLE_GMUX=m
+CONFIG_APPLE_MFI_FASTCHARGE=m
 CONFIG_APPLE_PROPERTIES=y
-CONFIG_RESET_ATTACK_MITIGATION=y
-CONFIG_EFI_RCI2_TABLE=y
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# end of EFI (Extensible Firmware Interface) Support
-
-CONFIG_UEFI_CPER=y
-CONFIG_UEFI_CPER_X86=y
-CONFIG_EFI_DEV_PATH_PARSER=y
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-
-#
-# Tegra firmware driver
-#
-# end of Tegra firmware driver
-# end of Firmware Drivers
-
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_KVM_IRQCHIP=y
-CONFIG_HAVE_KVM_IRQFD=y
-CONFIG_HAVE_KVM_IRQ_ROUTING=y
-CONFIG_HAVE_KVM_EVENTFD=y
-CONFIG_KVM_MMIO=y
-CONFIG_KVM_ASYNC_PF=y
-CONFIG_HAVE_KVM_MSI=y
-CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
-CONFIG_KVM_VFIO=y
-CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
-CONFIG_HAVE_KVM_IRQ_BYPASS=y
-CONFIG_HAVE_KVM_NO_POLL=y
-CONFIG_KVM_XFER_TO_GUEST_WORK=y
-CONFIG_VIRTUALIZATION=y
-CONFIG_KVM=m
-CONFIG_KVM_WERROR=y
-CONFIG_KVM_INTEL=m
-CONFIG_X86_SGX_KVM=y
-CONFIG_KVM_AMD=m
-CONFIG_KVM_XEN=y
-# CONFIG_KVM_MMU_AUDIT is not set
-CONFIG_AS_AVX512=y
-CONFIG_AS_SHA1_NI=y
-CONFIG_AS_SHA256_NI=y
-CONFIG_AS_TPAUSE=y
-
-#
-# General architecture-dependent options
-#
-CONFIG_CRASH_CORE=y
-CONFIG_KEXEC_CORE=y
-CONFIG_HOTPLUG_SMT=y
-CONFIG_GENERIC_ENTRY=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_OPROFILE_NMI_TIMER=y
-CONFIG_KPROBES=y
-CONFIG_JUMP_LABEL=y
-# CONFIG_STATIC_KEYS_SELFTEST is not set
-# CONFIG_STATIC_CALL_SELFTEST is not set
-CONFIG_OPTPROBES=y
-CONFIG_KPROBES_ON_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_KRETPROBES=y
-CONFIG_USER_RETURN_NOTIFIER=y
-CONFIG_HAVE_IOREMAP_PROT=y
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_KPROBES_ON_FTRACE=y
-# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set
-CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
-CONFIG_HAVE_NMI=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
-CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
-CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
+CONFIG_APPLICOM=m
+CONFIG_AQUANTIA_PHY=m
+CONFIG_AR5523=m
 CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_HAVE_ASM_MODVERSIONS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
-CONFIG_HAVE_USER_RETURN_NOTIFIER=y
-CONFIG_HAVE_PERF_EVENTS_NMI=y
-CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
-CONFIG_MMU_GATHER_TABLE_FREE=y
-CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
-CONFIG_HAVE_CMPXCHG_LOCAL=y
-CONFIG_HAVE_CMPXCHG_DOUBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_HAVE_ARCH_SECCOMP=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_SECCOMP=y
-# CONFIG_SECCOMP_CACHE_DEBUG is not set
-CONFIG_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_STACKLEAK=y
-CONFIG_HAVE_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR_STRONG=y
-CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MOVE_PMD=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-CONFIG_HAVE_ARCH_HUGE_VMAP=y
-CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
-CONFIG_HAVE_EXIT_THREAD=y
-CONFIG_ARCH_MMAP_RND_BITS=8
-CONFIG_ISA_BUS_API=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_VMAP_STACK=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y
+CONFIG_ARCH_CLOCKSOURCE_INIT=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_ARCH_CPUIDLE_HALTPOLL=y
+CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
+CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION=y
+CONFIG_ARCH_HAS_CPU_FINALIZE_INIT=y
+CONFIG_ARCH_HAS_CPU_RELAX=y
+CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
+CONFIG_ARCH_HAS_DEBUG_WX=y
+CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
+CONFIG_ARCH_HAS_MEM_ENCRYPT=y
+CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
+CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG=y
+CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y
+CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
 CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_STRICT_KERNEL_RWX=y
 CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_STRICT_MODULE_RWX=y
-CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
-CONFIG_ARCH_USE_MEMREMAP_PROT=y
-# CONFIG_LOCK_EVENT_COUNTS is not set
-CONFIG_X86_PLATFORM_DRIVERS_INTEL=y
-CONFIG_INTEL_SKL_INT3472=m
-# CONFIG_KCSAN is not set
-CONFIG_ARCH_HAS_MEM_ENCRYPT=y
-CONFIG_HAVE_STATIC_CALL=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-# end of GCOV-based kernel profiling
-
-CONFIG_HAVE_GCC_PLUGINS=y
-# CONFIG_GCC_PLUGINS is not set
-# end of General architecture-dependent options
-
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_ASM_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_MODULE_SIG is not set
-CONFIG_MODULE_COMPRESS_NONE=y
-# CONFIG_MODULE_COMPRESS_GZIP is not set
-# CONFIG_MODULE_COMPRESS_XZ is not set
-# CONFIG_MODULE_COMPRESS_ZSTD is not set
-# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
-CONFIG_MODPROBE_PATH="/sbin/modprobe"
-# CONFIG_TRIM_UNUSED_KSYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_TRIM_UNUSED_KSYMS is not set
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_BLOCK=y
-# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set
-CONFIG_BLK_SCSI_REQUEST=y
-CONFIG_BLK_CGROUP_RWSTAT=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=m
-CONFIG_BLK_DEV_ZONED=y
-CONFIG_BLK_DEV_THROTTLING=y
-# CONFIG_BLK_DEV_THROTTLING_LOW is not set
-CONFIG_BLK_CMDLINE_PARSER=y
-CONFIG_BLK_WBT=y
-CONFIG_BLK_CGROUP_IOLATENCY=y
-# CONFIG_BLK_CGROUP_FC_APPID is not set
-# CONFIG_BLK_CGROUP_IOCOST is not set
-# CONFIG_BLK_CGROUP_IOPRIO is not set
-CONFIG_BLK_WBT_MQ=y
-# CONFIG_BLK_DEBUG_FS is not set
-CONFIG_BLK_DEBUG_FS_ZONED=y
-# CONFIG_BLK_SED_OPAL is not set
-# CONFIG_BLK_INLINE_ENCRYPTION is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_ACORN_PARTITION=y
-CONFIG_ACORN_PARTITION_CUMANA=y
-CONFIG_ACORN_PARTITION_EESOX=y
-CONFIG_ACORN_PARTITION_ICS=y
-CONFIG_ACORN_PARTITION_ADFS=y
-CONFIG_ACORN_PARTITION_POWERTEC=y
-CONFIG_ACORN_PARTITION_RISCIX=y
-CONFIG_AIX_PARTITION=y
-CONFIG_OSF_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_ATARI_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_MSDOS_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_LDM_DEBUG=y
-CONFIG_SGI_PARTITION=y
-CONFIG_ULTRIX_PARTITION=y
-CONFIG_SUN_PARTITION=y
-CONFIG_KARMA_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_SYSV68_PARTITION=y
-CONFIG_CMDLINE_PARTITION=y
-# end of Partition Types
-
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_MQ_RDMA=y
-CONFIG_BLK_PM=y
-
-#
-# IO Schedulers
-#
-CONFIG_MQ_IOSCHED_DEADLINE=y
-CONFIG_MQ_IOSCHED_KYBER=m
-CONFIG_IOSCHED_BFQ=y
-CONFIG_BFQ_GROUP_IOSCHED=y
-# CONFIG_BFQ_CGROUP_DEBUG is not set
-# end of IO Schedulers
-
-CONFIG_PREEMPT_NOTIFIERS=y
-CONFIG_PADATA=y
-CONFIG_ASN1=y
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
 CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y
 CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
-CONFIG_FREEZER=y
-
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_ELFCORE=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_BINFMT_SCRIPT=y
-CONFIG_BINFMT_MISC=m
-CONFIG_COREDUMP=y
-# end of Executable file formats
-
-#
-# Memory Management options
-#
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM=y
-CONFIG_NEED_MULTIPLE_NODES=y
-CONFIG_SPARSEMEM_STATIC=y
-CONFIG_HAVE_FAST_GUP=y
-CONFIG_NUMA_KEEP_MEMINFO=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_MEMORY_BALLOON=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_COMPACTION=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_MIGRATION=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_BOUNCE=y
-CONFIG_VIRT_TO_BUS=y
-CONFIG_MMU_NOTIFIER=y
-CONFIG_KSM=y
-CONFIG_UKSM=y
-# CONFIG_KSM_LEGACY is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
-CONFIG_TRANSPARENT_HUGEPAGE=y
-CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
-# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-CONFIG_CLEANCACHE=y
-CONFIG_FRONTSWAP=y
-CONFIG_CMA=y
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SYSFS=y
-CONFIG_CMA_AREAS=7
-CONFIG_ZSWAP=y
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
-CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
-CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
-# CONFIG_ZSWAP_DEFAULT_ON is not set
-CONFIG_ZPOOL=y
-CONFIG_ZBUD=y
-CONFIG_Z3FOLD=m
-CONFIG_ZSMALLOC=y
-# CONFIG_ZSMALLOC_PGTABLE_MAPPING is not set
-# CONFIG_ZSMALLOC_STAT is not set
-CONFIG_GENERIC_EARLY_IOREMAP=y
-# CONFIG_IDLE_PAGE_TRACKING is not set
-CONFIG_HMM_MIRROR=y
-CONFIG_VMAP_PFN=y
-CONFIG_FRAME_VECTOR=y
-# CONFIG_PERCPU_STATS is not set
-# CONFIG_GUP_TEST is not set
-# CONFIG_GUP_BENCHMARK is not set
-CONFIG_GUP_GET_PTE_LOW_HIGH=y
-# CONFIG_READ_ONLY_THP_FOR_FS is not set
-CONFIG_ARCH_HAS_PTE_SPECIAL=y
-CONFIG_MAPPING_DIRTY_HELPERS=y
-# end of Memory Management options
-
-CONFIG_NET=y
-CONFIG_NET_INGRESS=y
-CONFIG_NET_EGRESS=y
-CONFIG_NET_REDIRECT=y
-CONFIG_SKB_EXTENSIONS=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=m
-CONFIG_PACKET_DIAG=m
-CONFIG_UNIX=y
-CONFIG_UNIX_SCM=y
-CONFIG_UNIX_DIAG=m
-CONFIG_TLS=m
-# CONFIG_TLS_DEVICE is not set
-# CONFIG_TLS_TOE is not set
-CONFIG_XFRM=y
-CONFIG_XFRM_OFFLOAD=y
-CONFIG_XFRM_ALGO=m
-CONFIG_XFRM_USER=m
-CONFIG_XFRM_INTERFACE=m
-CONFIG_XFRM_SUB_POLICY=y
-CONFIG_XFRM_MIGRATE=y
-CONFIG_XFRM_STATISTICS=y
-CONFIG_XFRM_AH=m
-CONFIG_XFRM_ESP=m
-CONFIG_XFRM_IPCOMP=m
-CONFIG_NET_KEY=m
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_XFRM_ESPINTCP=y
-CONFIG_SMC=m
-CONFIG_SMC_DIAG=m
-CONFIG_XDP_SOCKETS=y
-CONFIG_XDP_SOCKETS_DIAG=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_FIB_TRIE_STATS=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-# CONFIG_IP_ROUTE_VERBOSE is not set
-CONFIG_IP_ROUTE_CLASSID=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE_DEMUX=m
-CONFIG_NET_IP_TUNNEL=m
-CONFIG_NET_IPGRE=m
-CONFIG_NET_IPGRE_BROADCAST=y
-CONFIG_IP_MROUTE_COMMON=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_NET_IPVTI=m
-CONFIG_NET_UDP_TUNNEL=m
-CONFIG_NET_FOU=m
-CONFIG_NET_FOU_IP_TUNNELS=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_ESP_OFFLOAD=m
-CONFIG_INET_ESPINTCP=y
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_TABLE_PERTURB_ORDER=16
-CONFIG_INET_XFRM_TUNNEL=m
-CONFIG_INET_TUNNEL=m
-CONFIG_INET_DIAG=m
-CONFIG_INET_TCP_DIAG=m
-CONFIG_INET_UDP_DIAG=m
-CONFIG_INET_RAW_DIAG=m
-CONFIG_INET_DIAG_DESTROY=y
-CONFIG_TCP_CONG_ADVANCED=y
-CONFIG_TCP_CONG_BIC=m
-CONFIG_TCP_CONG_CUBIC=m
-CONFIG_TCP_CONG_WESTWOOD=m
-CONFIG_TCP_CONG_HTCP=m
-CONFIG_TCP_CONG_HSTCP=m
-CONFIG_TCP_CONG_HYBLA=m
-CONFIG_TCP_CONG_VEGAS=m
-CONFIG_TCP_CONG_NV=m
-CONFIG_TCP_CONG_SCALABLE=m
-CONFIG_TCP_CONG_LP=m
-CONFIG_TCP_CONG_VENO=m
-CONFIG_TCP_CONG_YEAH=m
-CONFIG_TCP_CONG_ILLINOIS=m
-CONFIG_TCP_CONG_DCTCP=m
-# CONFIG_TCP_CONG_CDG is not set
-CONFIG_TCP_CONG_BBR=m
-CONFIG_DEFAULT_RENO=y
-CONFIG_DEFAULT_TCP_CONG="reno"
-CONFIG_TCP_MD5SIG=y
-CONFIG_IPV6=m
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_ESP_OFFLOAD=m
-# CONFIG_INET6_ESPINTCP is not set
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_IPV6_ILA=m
-CONFIG_INET6_XFRM_TUNNEL=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_IPV6_VTI=m
-CONFIG_IPV6_SIT=m
-CONFIG_IPV6_SIT_6RD=y
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_GRE=m
-CONFIG_IPV6_FOU=m
-CONFIG_IPV6_FOU_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-CONFIG_IPV6_MROUTE=y
-CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IPV6_PIMSM_V2=y
-CONFIG_IPV6_SEG6_LWTUNNEL=y
-CONFIG_IPV6_SEG6_HMAC=y
-CONFIG_IPV6_RPL_LWTUNNEL=y
-CONFIG_MPTCP=y
-CONFIG_INET_MPTCP_DIAG=m
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NETWORK_PHY_TIMESTAMPING=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_ADVANCED=y
-CONFIG_BRIDGE_NETFILTER=m
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_INGRESS=y
-CONFIG_NETFILTER_NETLINK_HOOK=m
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_FAMILY_BRIDGE=y
-CONFIG_NETFILTER_FAMILY_ARP=y
-CONFIG_NETFILTER_NETLINK_ACCT=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NETFILTER_NETLINK_OSF=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_LOG_SYSLOG=m
-CONFIG_NF_LOG_COMMON=m
-CONFIG_NF_LOG_NETDEV=m
-CONFIG_NETFILTER_CONNCOUNT=m
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_ZONES=y
-CONFIG_NF_CONNTRACK_PROCFS=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CONNTRACK_TIMEOUT=y
-CONFIG_NF_CONNTRACK_TIMESTAMP=y
-CONFIG_NF_CONNTRACK_LABELS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_GRE=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_BROADCAST=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_SNMP=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NF_CT_NETLINK_TIMEOUT=m
-CONFIG_NF_CT_NETLINK_HELPER=m
-CONFIG_NETFILTER_NETLINK_GLUE_CT=y
-CONFIG_NF_NAT=m
-CONFIG_NF_NAT_AMANDA=m
-CONFIG_NF_NAT_FTP=m
-CONFIG_NF_NAT_IRC=m
-CONFIG_NF_NAT_SIP=m
-CONFIG_NF_NAT_TFTP=m
-CONFIG_NF_NAT_REDIRECT=y
-CONFIG_NF_NAT_MASQUERADE=y
-CONFIG_NETFILTER_SYNPROXY=m
-CONFIG_NF_TABLES=m
-CONFIG_NF_TABLES_INET=y
-CONFIG_NF_TABLES_NETDEV=y
-CONFIG_NFT_NUMGEN=m
-CONFIG_NFT_CT=m
-CONFIG_NFT_FLOW_OFFLOAD=m
-CONFIG_NFT_COUNTER=m
-CONFIG_NFT_CONNLIMIT=m
-CONFIG_NFT_LOG=m
-CONFIG_NFT_LIMIT=m
-CONFIG_NFT_MASQ=m
-CONFIG_NFT_REDIR=m
-CONFIG_NFT_NAT=m
-CONFIG_NFT_TUNNEL=m
-CONFIG_NFT_OBJREF=m
-CONFIG_NFT_QUEUE=m
-CONFIG_NFT_QUOTA=m
-CONFIG_NFT_REJECT=m
-CONFIG_NFT_REJECT_INET=m
-CONFIG_NFT_COMPAT=m
-CONFIG_NFT_HASH=m
-CONFIG_NFT_FIB_INET=m
-CONFIG_NFT_FIB=m
-CONFIG_NFT_FIB_INET=m
-CONFIG_NFT_XFRM=m
-CONFIG_NFT_SOCKET=m
-CONFIG_NFT_OSF=m
-CONFIG_NFT_TPROXY=m
-CONFIG_NFT_SYNPROXY=m
-CONFIG_NF_DUP_NETDEV=m
-CONFIG_NFT_DUP_NETDEV=m
-CONFIG_NFT_FWD_NETDEV=m
-CONFIG_NFT_FIB_NETDEV=m
-CONFIG_NFT_REJECT_NETDEV=m
-CONFIG_NF_FLOW_TABLE_INET=m
-CONFIG_NF_FLOW_TABLE=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XTABLES_COMPAT=y
-
-#
-# Xtables combined modules
-#
-CONFIG_NETFILTER_XT_MARK=m
-CONFIG_NETFILTER_XT_CONNMARK=m
-CONFIG_NETFILTER_XT_SET=m
-
-#
-# Xtables targets
-#
-CONFIG_NETFILTER_XT_TARGET_AUDIT=m
-CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CT=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_HL=m
-CONFIG_NETFILTER_XT_TARGET_HMARK=m
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
-CONFIG_NETFILTER_XT_TARGET_LOG=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_NAT=m
-CONFIG_NETFILTER_XT_TARGET_NETMAP=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-CONFIG_NETFILTER_XT_TARGET_RATEEST=m
-CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
-CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
-CONFIG_NETFILTER_XT_TARGET_TEE=m
-CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-CONFIG_NETFILTER_XT_TARGET_TRACE=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-
-#
-# Xtables matches
-#
-CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
-CONFIG_NETFILTER_XT_MATCH_BPF=m
-CONFIG_NETFILTER_XT_MATCH_CGROUP=m
-CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_CPU=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ECN=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_HL=m
-CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_IPVS=m
-CONFIG_NETFILTER_XT_MATCH_L2TP=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-CONFIG_NETFILTER_XT_MATCH_OSF=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-# end of Core Netfilter Configuration
-
-CONFIG_IP_SET=m
-CONFIG_IP_SET_MAX=256
-CONFIG_IP_SET_BITMAP_IP=m
-CONFIG_IP_SET_BITMAP_IPMAC=m
-CONFIG_IP_SET_BITMAP_PORT=m
-CONFIG_IP_SET_HASH_IP=m
-CONFIG_IP_SET_HASH_IPMARK=m
-CONFIG_IP_SET_HASH_IPPORT=m
-CONFIG_IP_SET_HASH_IPPORTIP=m
-CONFIG_IP_SET_HASH_IPPORTNET=m
-CONFIG_IP_SET_HASH_IPMAC=m
-CONFIG_IP_SET_HASH_MAC=m
-CONFIG_IP_SET_HASH_NETPORTNET=m
-CONFIG_IP_SET_HASH_NET=m
-CONFIG_IP_SET_HASH_NETNET=m
-CONFIG_IP_SET_HASH_NETPORT=m
-CONFIG_IP_SET_HASH_NETIFACE=m
-CONFIG_IP_SET_LIST_SET=m
-CONFIG_IP_VS=m
-CONFIG_IP_VS_IPV6=y
-# CONFIG_IP_VS_DEBUG is not set
-CONFIG_IP_VS_TAB_BITS=12
-
-#
-# IPVS transport protocol load balancing support
-#
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_AH_ESP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_PROTO_SCTP=y
-
-#
-# IPVS scheduler
-#
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_FO=m
-CONFIG_IP_VS_OVF=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_MH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_TWOS=m
-
-#
-# IPVS SH scheduler
-#
-CONFIG_IP_VS_SH_TAB_BITS=8
-
-#
-# IPVS MH scheduler
-#
-CONFIG_IP_VS_MH_TAB_INDEX=12
-
-#
-# IPVS application helper
-#
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_VS_NFCT=y
-CONFIG_IP_VS_PE_SIP=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_DEFRAG_IPV4=m
-CONFIG_NF_SOCKET_IPV4=m
-CONFIG_NF_TPROXY_IPV4=m
-CONFIG_NF_TABLES_IPV4=y
-CONFIG_NFT_REJECT_IPV4=m
-CONFIG_NFT_DUP_IPV4=m
-CONFIG_NFT_FIB_IPV4=m
-CONFIG_NF_TABLES_ARP=y
-CONFIG_NF_FLOW_TABLE_IPV4=m
-CONFIG_NF_DUP_IPV4=m
-CONFIG_NF_LOG_ARP=m
-CONFIG_NF_LOG_IPV4=m
-CONFIG_NF_REJECT_IPV4=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_NF_NAT_PPTP=m
-CONFIG_NF_NAT_H323=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_RPFILTER=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_SYNPROXY=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-# end of IP: Netfilter Configuration
-
-#
-# IPv6: Netfilter Configuration
-#
-CONFIG_NF_SOCKET_IPV6=m
-CONFIG_NF_TPROXY_IPV6=m
-CONFIG_NF_TABLES_IPV6=y
-CONFIG_NFT_REJECT_IPV6=m
-CONFIG_NFT_DUP_IPV6=m
-CONFIG_NFT_FIB_IPV6=m
-CONFIG_NF_FLOW_TABLE_IPV6=m
-CONFIG_NF_DUP_IPV6=m
-CONFIG_NF_REJECT_IPV6=m
-CONFIG_NF_LOG_IPV6=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RPFILTER=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_MATCH_SRH=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_TARGET_SYNPROXY=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_IP6_NF_NAT=m
-CONFIG_IP6_NF_TARGET_MASQUERADE=m
-CONFIG_IP6_NF_TARGET_NPT=m
-# end of IPv6: Netfilter Configuration
-
-CONFIG_NF_DEFRAG_IPV6=m
-
-#
-# DECnet: Netfilter Configuration
-#
-CONFIG_DECNET_NF_GRABULATOR=m
-# end of DECnet: Netfilter Configuration
-
-CONFIG_NF_TABLES_BRIDGE=m
-CONFIG_NFT_BRIDGE_META=m
-CONFIG_NFT_BRIDGE_REJECT=m
-CONFIG_NF_LOG_BRIDGE=m
-CONFIG_NF_CONNTRACK_BRIDGE=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_IP6=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_BRIDGE_EBT_NFLOG=m
-# CONFIG_BPFILTER is not set
-CONFIG_IP_DCCP=m
-CONFIG_INET_DCCP_DIAG=m
-
-#
-# DCCP CCIDs Configuration
-#
-# CONFIG_IP_DCCP_CCID2_DEBUG is not set
-CONFIG_IP_DCCP_CCID3=y
-# CONFIG_IP_DCCP_CCID3_DEBUG is not set
-CONFIG_IP_DCCP_TFRC_LIB=y
-# end of DCCP CCIDs Configuration
-
-#
-# DCCP Kernel Hacking
-#
-# CONFIG_IP_DCCP_DEBUG is not set
-# end of DCCP Kernel Hacking
-
-CONFIG_IP_SCTP=m
-# CONFIG_SCTP_DBG_OBJCNT is not set
-CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
-CONFIG_SCTP_COOKIE_HMAC_MD5=y
-CONFIG_SCTP_COOKIE_HMAC_SHA1=y
-CONFIG_INET_SCTP_DIAG=m
-CONFIG_RDS=m
-CONFIG_RDS_RDMA=m
-CONFIG_RDS_TCP=m
-# CONFIG_RDS_DEBUG is not set
-CONFIG_TIPC=m
-CONFIG_TIPC_MEDIA_IB=y
-CONFIG_TIPC_MEDIA_UDP=y
-CONFIG_TIPC_CRYPTO=y
-CONFIG_TIPC_DIAG=m
-CONFIG_ATM=m
-CONFIG_ATM_CLIP=m
-# CONFIG_ATM_CLIP_NO_ICMP is not set
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-# CONFIG_ATM_BR2684_IPFILTER is not set
-CONFIG_L2TP=m
-# CONFIG_L2TP_DEBUGFS is not set
-CONFIG_L2TP_V3=y
-CONFIG_L2TP_IP=m
-CONFIG_L2TP_ETH=m
-CONFIG_STP=m
-CONFIG_GARP=m
-CONFIG_MRP=m
-CONFIG_BRIDGE=m
-CONFIG_BRIDGE_IGMP_SNOOPING=y
-CONFIG_BRIDGE_VLAN_FILTERING=y
-# CONFIG_BRIDGE_MRP is not set
-# CONFIG_BRIDGE_CFM is not set
-CONFIG_HAVE_NET_DSA=y
-CONFIG_NET_DSA=m
-CONFIG_NET_DSA_TAG_8021Q=m
-CONFIG_NET_DSA_TAG_AR9331=m
-CONFIG_NET_DSA_TAG_BRCM_COMMON=m
-CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
-CONFIG_NET_DSA_TAG_BRCM=m
-CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
-CONFIG_NET_DSA_TAG_HELLCREEK=m
-CONFIG_NET_DSA_TAG_GSWIP=m
-CONFIG_NET_DSA_TAG_DSA=m
-CONFIG_NET_DSA_TAG_EDSA=m
-CONFIG_NET_DSA_TAG_MTK=m
-CONFIG_NET_DSA_TAG_KSZ=m
-CONFIG_NET_DSA_TAG_RTL4_A=m
-CONFIG_NET_DSA_TAG_RTL8_4=m
-CONFIG_NET_DSA_TAG_OCELOT=m
-CONFIG_NET_DSA_TAG_QCA=m
-CONFIG_NET_DSA_TAG_LAN9303=m
-CONFIG_NET_DSA_TAG_SJA1105=m
-CONFIG_NET_DSA_TAG_TRAILER=m
-CONFIG_NET_DSA_TAG_XRS700X=m
-CONFIG_NET_DSA_REALTEK=m
-CONFIG_NET_DSA_REALTEK_MDIO=m
-CONFIG_NET_DSA_REALTEK_RTL8365MB=m
-CONFIG_NET_DSA_REALTEK_RTL8366RB=m
-CONFIG_VLAN_8021Q=m
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_VLAN_8021Q_MVRP=y
-CONFIG_DECNET=m
-CONFIG_DECNET_ROUTER=y
-CONFIG_LLC=m
-CONFIG_LLC2=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-# CONFIG_LTPC is not set
-# CONFIG_COPS is not set
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_PHONET=m
-CONFIG_6LOWPAN=m
-# CONFIG_6LOWPAN_DEBUGFS is not set
-CONFIG_6LOWPAN_NHC=m
-CONFIG_6LOWPAN_NHC_DEST=m
-CONFIG_6LOWPAN_NHC_FRAGMENT=m
-CONFIG_6LOWPAN_NHC_HOP=m
-CONFIG_6LOWPAN_NHC_IPV6=m
-CONFIG_6LOWPAN_NHC_MOBILITY=m
-CONFIG_6LOWPAN_NHC_ROUTING=m
-CONFIG_6LOWPAN_NHC_UDP=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
-CONFIG_6LOWPAN_GHC_UDP=m
-CONFIG_6LOWPAN_GHC_ICMPV6=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
-CONFIG_IEEE802154=m
-CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
-CONFIG_IEEE802154_SOCKET=m
-CONFIG_IEEE802154_6LOWPAN=m
-CONFIG_MAC802154=m
-CONFIG_NET_SCHED=y
-
-#
-# Queueing/Scheduling
-#
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_MULTIQ=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFB=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_CBS=m
-CONFIG_NET_SCH_ETF=m
-CONFIG_NET_SCH_TAPRIO=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_DRR=m
-CONFIG_NET_SCH_MQPRIO=m
-CONFIG_NET_SCH_SKBPRIO=m
-CONFIG_NET_SCH_CHOKE=m
-CONFIG_NET_SCH_QFQ=m
-CONFIG_NET_SCH_CODEL=m
-CONFIG_NET_SCH_FQ_CODEL=y
-CONFIG_NET_SCH_CAKE=m
-CONFIG_NET_SCH_FQ=m
-CONFIG_NET_SCH_HHF=m
-CONFIG_NET_SCH_PIE=m
-CONFIG_NET_SCH_FQ_PIE=m
-CONFIG_NET_SCH_INGRESS=m
-CONFIG_NET_SCH_PLUG=m
-CONFIG_NET_SCH_ETS=m
-# CONFIG_NET_SCH_DEFAULT is not set
-
-#
-# Classification
-#
-CONFIG_NET_CLS=y
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_CLS_U32_PERF=y
-CONFIG_CLS_U32_MARK=y
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_CLS_FLOW=m
-CONFIG_NET_CLS_CGROUP=m
-CONFIG_NET_CLS_BPF=m
-CONFIG_NET_CLS_FLOWER=m
-CONFIG_NET_CLS_MATCHALL=m
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_STACK=32
-CONFIG_NET_EMATCH_CMP=m
-CONFIG_NET_EMATCH_NBYTE=m
-CONFIG_NET_EMATCH_U32=m
-CONFIG_NET_EMATCH_META=m
-CONFIG_NET_EMATCH_TEXT=m
-CONFIG_NET_EMATCH_CANID=m
-CONFIG_NET_EMATCH_IPSET=m
-CONFIG_NET_EMATCH_IPT=m
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=m
-CONFIG_NET_ACT_GACT=m
-CONFIG_GACT_PROB=y
-CONFIG_NET_ACT_MIRRED=m
-CONFIG_NET_ACT_SAMPLE=m
-CONFIG_NET_ACT_IPT=m
-CONFIG_NET_ACT_NAT=m
-CONFIG_NET_ACT_PEDIT=m
-# CONFIG_NET_ACT_SIMP is not set
-CONFIG_NET_ACT_SKBEDIT=m
-CONFIG_NET_ACT_CSUM=m
-CONFIG_NET_ACT_MPLS=m
-CONFIG_NET_ACT_VLAN=m
-CONFIG_NET_ACT_BPF=m
-CONFIG_NET_ACT_CONNMARK=m
-CONFIG_NET_ACT_CTINFO=m
-CONFIG_NET_ACT_SKBMOD=m
-CONFIG_NET_ACT_IFE=m
-CONFIG_NET_ACT_TUNNEL_KEY=m
-CONFIG_NET_ACT_CT=m
-CONFIG_NET_ACT_GATE=m
-CONFIG_NET_IFE_SKBMARK=m
-CONFIG_NET_IFE_SKBPRIO=m
-CONFIG_NET_IFE_SKBTCINDEX=m
-# CONFIG_NET_TC_SKB_EXT is not set
-CONFIG_NET_SCH_FIFO=y
-CONFIG_DCB=y
-CONFIG_DNS_RESOLVER=y
-CONFIG_BATMAN_ADV=m
-# CONFIG_BATMAN_ADV_BATMAN_V is not set
-CONFIG_BATMAN_ADV_BLA=y
-CONFIG_BATMAN_ADV_DAT=y
-CONFIG_BATMAN_ADV_NC=y
-CONFIG_BATMAN_ADV_MCAST=y
-CONFIG_BATMAN_ADV_DEBUGFS=y
-# CONFIG_BATMAN_ADV_DEBUG is not set
-CONFIG_BATMAN_ADV_SYSFS=y
-# CONFIG_BATMAN_ADV_TRACING is not set
-CONFIG_OPENVSWITCH=m
-CONFIG_OPENVSWITCH_GRE=m
-CONFIG_OPENVSWITCH_VXLAN=m
-CONFIG_OPENVSWITCH_GENEVE=m
-CONFIG_VSOCKETS=m
-CONFIG_VSOCKETS_DIAG=m
-CONFIG_VSOCKETS_LOOPBACK=m
-CONFIG_VMWARE_VMCI_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS_COMMON=m
-CONFIG_HYPERV_VSOCKETS=m
-CONFIG_NETLINK_DIAG=m
-CONFIG_MPLS=y
-CONFIG_NET_MPLS_GSO=m
-CONFIG_MPLS_ROUTING=m
-CONFIG_MPLS_IPTUNNEL=m
-CONFIG_NET_NSH=m
-CONFIG_HSR=m
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_L3_MASTER_DEV=y
-CONFIG_QRTR=m
-CONFIG_QRTR_SMD=m
-CONFIG_QRTR_TUN=m
-CONFIG_QRTR_MHI=m
-# CONFIG_NET_NCSI is not set
-CONFIG_PCPU_DEV_REFCNT=y
-CONFIG_RPS=y
-CONFIG_RFS_ACCEL=y
-CONFIG_XPS=y
-CONFIG_CGROUP_NET_PRIO=y
-CONFIG_CGROUP_NET_CLASSID=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_BQL=y
-CONFIG_BPF_JIT=y
-CONFIG_BPF_STREAM_PARSER=y
-CONFIG_NET_FLOW_LIMIT=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NET_DROP_MONITOR is not set
-# end of Network testing
-# end of Networking options
-
-CONFIG_HAMRADIO=y
-
-#
-# Packet Radio protocols
-#
-CONFIG_AX25=m
-CONFIG_AX25_DAMA_SLAVE=y
-CONFIG_NETROM=m
-CONFIG_ROSE=m
-
-#
-# AX.25 network device drivers
-#
-CONFIG_MKISS=m
-CONFIG_6PACK=m
-CONFIG_BPQETHER=m
-# CONFIG_SCC is not set
-CONFIG_BAYCOM_SER_FDX=m
-CONFIG_BAYCOM_SER_HDX=m
-CONFIG_BAYCOM_PAR=m
-# CONFIG_BAYCOM_EPP is not set
-CONFIG_YAM=m
-# end of AX.25 network device drivers
-
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_GW=m
-CONFIG_CAN_J1939=m
-CONFIG_CAN_ISOTP=m
-CONFIG_CAN_ETAS_ES58X=m
-
-#
-# CAN Device Drivers
-#
-CONFIG_CAN_VCAN=m
-CONFIG_CAN_VXCAN=m
-CONFIG_CAN_SLCAN=m
-CONFIG_CAN_DEV=m
-CONFIG_CAN_CALC_BITTIMING=y
-CONFIG_CAN_JANZ_ICAN3=m
-CONFIG_CAN_KVASER_PCIEFD=m
-CONFIG_PCH_CAN=m
-CONFIG_CAN_C_CAN=m
-CONFIG_CAN_C_CAN_PLATFORM=m
-CONFIG_CAN_C_CAN_PCI=m
-CONFIG_CAN_CC770=m
-CONFIG_CAN_CC770_ISA=m
-CONFIG_CAN_CC770_PLATFORM=m
-CONFIG_CAN_IFI_CANFD=m
-CONFIG_CAN_M_CAN=m
-CONFIG_CAN_M_CAN_PCI=m
-CONFIG_CAN_M_CAN_PLATFORM=m
-CONFIG_CAN_M_CAN_TCAN4X5X=m
-CONFIG_CAN_PEAK_PCIEFD=m
-CONFIG_CAN_SJA1000=m
-CONFIG_CAN_EMS_PCI=m
-CONFIG_CAN_EMS_PCMCIA=m
-CONFIG_CAN_F81601=m
-CONFIG_CAN_KVASER_PCI=m
-CONFIG_CAN_PEAK_PCI=m
-CONFIG_CAN_PEAK_PCIEC=y
-CONFIG_CAN_PEAK_PCMCIA=m
-CONFIG_CAN_PLX_PCI=m
-CONFIG_CAN_SJA1000_ISA=m
-CONFIG_CAN_SJA1000_PLATFORM=m
-# CONFIG_CAN_TSCAN1 is not set
-CONFIG_CAN_SOFTING=m
-CONFIG_CAN_SOFTING_CS=m
-
-#
-# CAN SPI interfaces
-#
-CONFIG_CAN_HI311X=m
-CONFIG_CAN_MCP251X=m
-CONFIG_CAN_MCP251XFD=m
-# CONFIG_CAN_MCP251XFD_SANITY is not set
-# end of CAN SPI interfaces
-
-#
-# CAN USB interfaces
-#
-CONFIG_CAN_8DEV_USB=m
-CONFIG_CAN_EMS_USB=m
-CONFIG_CAN_ESD_USB2=m
-CONFIG_CAN_GS_USB=m
-CONFIG_CAN_KVASER_USB=m
-CONFIG_CAN_MCBA_USB=m
-CONFIG_CAN_PEAK_USB=m
-CONFIG_CAN_UCAN=m
-# end of CAN USB interfaces
-
-# CONFIG_CAN_DEBUG_DEVICES is not set
-# end of CAN Device Drivers
-
-CONFIG_BT=m
-CONFIG_BT_BREDR=y
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_CMTP=m
-CONFIG_BT_HIDP=m
-CONFIG_BT_HS=y
-CONFIG_BT_LE=y
-CONFIG_BT_6LOWPAN=m
-CONFIG_BT_LEDS=y
-CONFIG_BT_MSFTEXT=y
-CONFIG_BT_AOSPEXT=y
-CONFIG_BT_DEBUGFS=y
-# CONFIG_BT_SELFTEST is not set
-# CONFIG_BT_FEATURE_DEBUG is not set
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_INTEL=m
-CONFIG_BT_BCM=m
-CONFIG_BT_RTL=m
-CONFIG_BT_QCA=m
-CONFIG_BT_HCIBTUSB=m
-# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
-CONFIG_BT_HCIBTUSB_BCM=y
-CONFIG_BT_HCIBTUSB_MTK=y
-CONFIG_BT_HCIBTUSB_RTL=y
-CONFIG_BT_HCIBTSDIO=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_SERDEV=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_NOKIA=m
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_ATH3K=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIUART_3WIRE=y
-CONFIG_BT_HCIUART_INTEL=y
-CONFIG_BT_HCIUART_RTL=y
-CONFIG_BT_HCIUART_QCA=y
-CONFIG_BT_HCIUART_AG6XX=y
-CONFIG_BT_HCIUART_MRVL=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIDTL1=m
-CONFIG_BT_HCIBT3C=m
-CONFIG_BT_HCIBLUECARD=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_BT_MRVL=m
-CONFIG_BT_MRVL_SDIO=m
-CONFIG_BT_ATH3K=m
-CONFIG_BT_MTKSDIO=m
-CONFIG_BT_MTKUART=m
-CONFIG_BT_VIRTIO=m
-CONFIG_BT_HCIRSI=m
-# end of Bluetooth device drivers
-
-CONFIG_AF_RXRPC=m
-CONFIG_AF_RXRPC_IPV6=y
-# CONFIG_AF_RXRPC_INJECT_LOSS is not set
-# CONFIG_AF_RXRPC_DEBUG is not set
-# CONFIG_RXKAD is not set
-CONFIG_AF_KCM=m
-CONFIG_STREAM_PARSER=y
-CONFIG_FIB_RULES=y
-CONFIG_WIRELESS=y
-CONFIG_WIRELESS_EXT=y
-# CONFIG_WEXT_CORE is not set
-# CONFIG_WEXT_PROC is not set
-# CONFIG_WEXT_SPY is not set
-# CONFIG_WEXT_PRIV is not set
-CONFIG_CFG80211=m
-CONFIG_NL80211_TESTMODE=y
-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
-CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
-CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
-CONFIG_CFG80211_DEFAULT_PS=y
-# CONFIG_CFG80211_DEBUGFS is not set
-CONFIG_CFG80211_CRDA_SUPPORT=y
-# CONFIG_CFG80211_WEXT is not set
-# CONFIG_CFG80211_WEXT_EXPORT is not set
-CONFIG_LIB80211=m
-CONFIG_LIB80211_CRYPT_WEP=m
-CONFIG_LIB80211_CRYPT_CCMP=m
-CONFIG_LIB80211_CRYPT_TKIP=m
-# CONFIG_LIB80211_DEBUG is not set
-CONFIG_MAC80211=m
-CONFIG_MAC80211_HAS_RC=y
-CONFIG_MAC80211_RC_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
-CONFIG_MAC80211_MESH=y
-CONFIG_MAC80211_LEDS=y
-# CONFIG_MAC80211_DEBUGFS is not set
-# CONFIG_MAC80211_MESSAGE_TRACING is not set
-# CONFIG_MAC80211_DEBUG_MENU is not set
-CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
-CONFIG_WIMAX=m
-CONFIG_WIMAX_DEBUG_LEVEL=8
-CONFIG_RFKILL=m
-CONFIG_RFKILL_LEDS=y
-CONFIG_RFKILL_INPUT=y
-CONFIG_RFKILL_GPIO=m
-CONFIG_NET_9P=m
-CONFIG_NET_9P_VIRTIO=m
-CONFIG_NET_9P_RDMA=m
-# CONFIG_NET_9P_DEBUG is not set
-CONFIG_CAIF=m
-# CONFIG_CAIF_DEBUG is not set
-CONFIG_CAIF_NETDEV=m
-CONFIG_CAIF_USB=m
-CONFIG_CEPH_LIB=m
-# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
-CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
-CONFIG_NFC=m
-CONFIG_NFC_DIGITAL=m
-CONFIG_NFC_NCI=m
-CONFIG_NFC_NCI_SPI=m
-CONFIG_NFC_NCI_UART=m
-CONFIG_NFC_HCI=m
-CONFIG_NFC_SHDLC=y
-
-#
-# Near Field Communication (NFC) devices
-#
-CONFIG_NFC_TRF7970A=m
-CONFIG_NFC_MEI_PHY=m
-CONFIG_NFC_SIM=m
-CONFIG_NFC_PORT100=m
-CONFIG_NFC_VIRTUAL_NCI=m
-CONFIG_NFC_FDP=m
-CONFIG_NFC_FDP_I2C=m
-CONFIG_NFC_PN544=m
-CONFIG_NFC_PN544_I2C=m
-CONFIG_NFC_PN544_MEI=m
-CONFIG_NFC_PN533=m
-CONFIG_NFC_PN533_USB=m
-CONFIG_NFC_PN533_I2C=m
-CONFIG_NFC_PN532_UART=m
-CONFIG_NFC_MICROREAD=m
-CONFIG_NFC_MICROREAD_I2C=m
-CONFIG_NFC_MICROREAD_MEI=m
-CONFIG_NFC_MRVL=m
-CONFIG_NFC_MRVL_USB=m
-CONFIG_NFC_MRVL_UART=m
-CONFIG_NFC_MRVL_I2C=m
-CONFIG_NFC_MRVL_SPI=m
-CONFIG_NFC_ST21NFCA=m
-CONFIG_NFC_ST21NFCA_I2C=m
-CONFIG_NFC_ST_NCI=m
-CONFIG_NFC_ST_NCI_I2C=m
-CONFIG_NFC_ST_NCI_SPI=m
-CONFIG_NFC_NXP_NCI=m
-CONFIG_NFC_NXP_NCI_I2C=m
-CONFIG_NFC_S3FWRN5=m
-CONFIG_NFC_S3FWRN5_I2C=m
-CONFIG_NFC_S3FWRN82_UART=m
-CONFIG_NFC_ST95HF=m
-# end of Near Field Communication (NFC) devices
-
-CONFIG_PSAMPLE=m
-CONFIG_NET_IFE=m
-CONFIG_LWTUNNEL=y
-CONFIG_LWTUNNEL_BPF=y
-# CONFIG_PAGE_POOL_STATS is not set
-CONFIG_DST_CACHE=y
-CONFIG_GRO_CELLS=y
-CONFIG_NET_SOCK_MSG=y
-CONFIG_NET_DEVLINK=y
-CONFIG_PAGE_POOL=y
-CONFIG_FAILOVER=m
-CONFIG_ETHTOOL_NETLINK=y
-CONFIG_HAVE_EBPF_JIT=y
-
-#
-# Device Drivers
-#
-CONFIG_HAVE_EISA=y
-# CONFIG_EISA is not set
-CONFIG_HAVE_PCI=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_HOTPLUG_PCI_PCIE=y
-CONFIG_PCIEAER=y
-# CONFIG_PCIEAER_INJECT is not set
-CONFIG_PCIE_ECRC=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-CONFIG_PCIE_PME=y
-CONFIG_PCIE_DPC=y
-CONFIG_PCIE_PTM=y
-# CONFIG_PCIE_BW is not set
-CONFIG_PCIE_EDR=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_QUIRKS=y
-# CONFIG_PCI_DEBUG is not set
-CONFIG_PCI_REALLOC_ENABLE_AUTO=y
-CONFIG_PCI_STUB=m
-CONFIG_PCI_PF_STUB=m
-CONFIG_PCI_ATS=y
-CONFIG_PCI_LOCKLESS_CONFIG=y
-CONFIG_PCI_IOV=y
-CONFIG_PCI_PRI=y
-CONFIG_PCI_PASID=y
-CONFIG_PCI_LABEL=y
-# CONFIG_PCIE_BUS_TUNE_OFF is not set
-CONFIG_PCIE_BUS_DEFAULT=y
-# CONFIG_PCIE_BUS_SAFE is not set
-# CONFIG_PCIE_BUS_PERFORMANCE is not set
-# CONFIG_PCIE_BUS_PEER2PEER is not set
-CONFIG_HOTPLUG_PCI=y
-# CONFIG_HOTPLUG_PCI_COMPAQ is not set
-# CONFIG_HOTPLUG_PCI_IBM is not set
-CONFIG_HOTPLUG_PCI_ACPI=y
-CONFIG_HOTPLUG_PCI_ACPI_IBM=m
-CONFIG_HOTPLUG_PCI_CPCI=y
-CONFIG_HOTPLUG_PCI_CPCI_ZT5550=m
-CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m
-CONFIG_HOTPLUG_PCI_SHPC=y
-
-#
-# PCI controller drivers
-#
-
-#
-# DesignWare PCI Core Support
-#
-# CONFIG_PCIE_DW_PLAT_HOST is not set
-# CONFIG_PCIE_DW_PLAT_EP is not set
-# CONFIG_PCI_MESON is not set
-# end of DesignWare PCI Core Support
-
-#
-# Mobiveil PCIe Core Support
-#
-# end of Mobiveil PCIe Core Support
-
-#
-# Cadence PCIe controllers support
-#
-# end of Cadence PCIe controllers support
-# end of PCI controller drivers
-
-#
-# PCI Endpoint
-#
-CONFIG_PCI_ENDPOINT=y
-CONFIG_PCI_ENDPOINT_CONFIGFS=y
-# CONFIG_PCI_EPF_TEST is not set
-CONFIG_PCI_EPF_NTB=m
-# end of PCI Endpoint
-CONFIG_CXL_BUS=m
-CONFIG_CXL_PCI=m
-CONFIG_CXL_MEM=m
-CONFIG_CXL_MEM_RAW_COMMANDS=y
-CONFIG_CXL_ACPI=m
-CONFIG_CXL_PMEM=m
-
-#
-# PCI switch controller drivers
-#
-CONFIG_PCI_SW_SWITCHTEC=m
-# end of PCI switch controller drivers
-
-CONFIG_PCCARD=m
-CONFIG_PCMCIA=m
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_CARDBUS=y
-
-#
-# PC-card bridges
-#
-CONFIG_YENTA=m
-CONFIG_YENTA_O2=y
-CONFIG_YENTA_RICOH=y
-CONFIG_YENTA_TI=y
-CONFIG_YENTA_ENE_TUNE=y
-CONFIG_YENTA_TOSHIBA=y
-CONFIG_PD6729=m
-CONFIG_I82092=m
-# CONFIG_I82365 is not set
-# CONFIG_TCIC is not set
-CONFIG_PCMCIA_PROBE=y
-CONFIG_PCCARD_NONSTATIC=y
-CONFIG_RAPIDIO=m
-CONFIG_RAPIDIO_TSI721=m
-CONFIG_RAPIDIO_DISC_TIMEOUT=30
-CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y
-CONFIG_RAPIDIO_DMA_ENGINE=y
-# CONFIG_RAPIDIO_DEBUG is not set
-CONFIG_RAPIDIO_ENUM_BASIC=m
-CONFIG_RAPIDIO_CHMAN=m
-CONFIG_RAPIDIO_MPORT_CDEV=m
-
-#
-# RapidIO Switch drivers
-#
-CONFIG_RAPIDIO_TSI57X=m
-CONFIG_RAPIDIO_CPS_XX=m
-CONFIG_RAPIDIO_TSI568=m
-CONFIG_RAPIDIO_CPS_GEN2=m
-CONFIG_RAPIDIO_RXS_GEN3=m
-# end of RapidIO Switch drivers
-
-#
-# Generic Driver Options
-#
-# CONFIG_UEVENT_HELPER is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-
-#
-# Firmware loader
-#
-CONFIG_FW_LOADER=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_FW_LOADER_USER_HELPER is not set
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_FW_LOADER_COMPRESS=y
-CONFIG_FW_CACHE=y
-# end of Firmware loader
-
-CONFIG_WANT_DEV_COREDUMP=y
-CONFIG_ALLOW_DEV_COREDUMP=y
-CONFIG_DEV_COREDUMP=y
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
-CONFIG_HMEM_REPORTING=y
-CONFIG_TEST_ASYNC_DRIVER_PROBE=m
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=m
-CONFIG_REGMAP_SLIMBUS=m
-CONFIG_REGMAP_SPI=y
-CONFIG_REGMAP_SPMI=m
-CONFIG_REGMAP_W1=m
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_SOUNDWIRE=m
-CONFIG_REGMAP_SCCB=m
-CONFIG_REGMAP_I3C=m
-CONFIG_REGMAP_SPI_AVMM=m
-CONFIG_DMA_SHARED_BUFFER=y
-# CONFIG_DMA_FENCE_TRACE is not set
-# end of Generic Driver Options
-
-#
-# Bus devices
-#
-CONFIG_MHI_BUS=m
-CONFIG_MHI_BUS_DEBUG=y
-CONFIG_MHI_BUS_PCI_GENERIC=m
-# end of Bus devices
-
-CONFIG_CONNECTOR=m
-CONFIG_GNSS=m
-CONFIG_GNSS_SERIAL=m
-CONFIG_GNSS_MTK_SERIAL=m
-CONFIG_GNSS_SIRF_SERIAL=m
-CONFIG_GNSS_UBX_SERIAL=m
-CONFIG_MTD=m
-CONFIG_MTD_TESTS=m
-
-#
-# Partition parsers
-#
-CONFIG_MTD_AR7_PARTS=m
-CONFIG_MTD_CMDLINE_PARTS=m
-CONFIG_MTD_REDBOOT_PARTS=m
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-CONFIG_MTD_QCOMSMEM_PARTS=m
-# end of Partition parsers
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
-CONFIG_MTD_BLOCK_RO=m
-CONFIG_FTL=m
-CONFIG_NFTL=m
-CONFIG_NFTL_RW=y
-CONFIG_INFTL=m
-CONFIG_RFD_FTL=m
-CONFIG_SSFDC=m
-CONFIG_SM_FTL=m
-CONFIG_MTD_OOPS=m
-CONFIG_MTD_PSTORE=m
-CONFIG_MTD_SWAP=m
-# CONFIG_MTD_PARTITIONED_MASTER is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_GEN_PROBE=m
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-CONFIG_MTD_CFI_INTELEXT=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_CFI_STAA=m
-CONFIG_MTD_CFI_UTIL=m
-CONFIG_MTD_RAM=m
-CONFIG_MTD_ROM=m
-CONFIG_MTD_ABSENT=m
-# end of RAM/ROM/Flash chip drivers
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=m
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-# CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set
-CONFIG_MTD_SBC_GXX=m
-CONFIG_MTD_AMD76XROM=m
-CONFIG_MTD_ICHXROM=m
-CONFIG_MTD_ESB2ROM=m
-CONFIG_MTD_CK804XROM=m
-CONFIG_MTD_SCB2_FLASH=m
-CONFIG_MTD_NETtel=m
-CONFIG_MTD_L440GX=m
-CONFIG_MTD_PCI=m
-CONFIG_MTD_PCMCIA=m
-# CONFIG_MTD_PCMCIA_ANONYMOUS is not set
-CONFIG_MTD_INTEL_VR_NOR=m
-CONFIG_MTD_PLATRAM=m
-# end of Mapping drivers for chip access
-
-#
-# Self-contained MTD device drivers
-#
-CONFIG_MTD_PMC551=m
-CONFIG_MTD_PMC551_BUGFIX=y
-# CONFIG_MTD_PMC551_DEBUG is not set
-CONFIG_MTD_DATAFLASH=m
-CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
-CONFIG_MTD_DATAFLASH_OTP=y
-CONFIG_MTD_MCHP23K256=m
-CONFIG_MTD_MCHP48L640=m
-CONFIG_MTD_SST25L=m
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTDRAM_TOTAL_SIZE=4096
-CONFIG_MTDRAM_ERASE_SIZE=128
-CONFIG_MTD_BLOCK2MTD=m
-
-#
-# Disk-On-Chip Device Drivers
-#
-CONFIG_MTD_DOCG3=m
-CONFIG_BCH_CONST_M=14
-CONFIG_BCH_CONST_T=4
-# end of Self-contained MTD device drivers
-
-#
-# NAND
-#
-CONFIG_MTD_NAND_CORE=m
-CONFIG_MTD_ONENAND=m
-CONFIG_MTD_ONENAND_VERIFY_WRITE=y
-CONFIG_MTD_ONENAND_GENERIC=m
-CONFIG_MTD_ONENAND_OTP=y
-CONFIG_MTD_ONENAND_2X_PROGRAM=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=m
-# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
-CONFIG_MTD_RAW_NAND=m
-CONFIG_MTD_NAND_ECC_SW_BCH=y
-CONFIG_MTD_NAND_ECC_MXIC=y
-
-#
-# Raw/parallel NAND flash controllers
-#
-CONFIG_MTD_NAND_DENALI=m
-CONFIG_MTD_NAND_DENALI_PCI=m
-CONFIG_MTD_NAND_CAFE=m
-# CONFIG_MTD_NAND_CS553X is not set
-CONFIG_MTD_NAND_MXIC=m
-CONFIG_MTD_NAND_GPIO=m
-CONFIG_MTD_NAND_PLATFORM=m
-CONFIG_MTD_NAND_ARASAN=m
-CONFIG_MTD_NAND_INTEL_LGM=m
-CONFIG_MTD_NAND_ROCKCHIP=m
-CONFIG_MTD_NAND_PL35X=m
-
-#
-# Misc
-#
-CONFIG_MTD_SM_COMMON=m
-CONFIG_MTD_NAND_NANDSIM=m
-CONFIG_MTD_NAND_RICOH=m
-CONFIG_MTD_NAND_DISKONCHIP=m
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
-CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
-CONFIG_MTD_SPI_NAND=m
-
-#
-# ECC engine support
-#
-CONFIG_MTD_NAND_ECC=y
-# end of ECC engine support
-# end of NAND
-
-#
-# LPDDR & LPDDR2 PCM memory drivers
-#
-CONFIG_MTD_LPDDR=m
-CONFIG_MTD_QINFO_PROBE=m
-# end of LPDDR & LPDDR2 PCM memory drivers
-
-CONFIG_MTD_SPI_NOR=m
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SPI_NOR_SWP_DISABLE=y
-# CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE is not set
-# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
-CONFIG_SPI_INTEL_SPI=m
-CONFIG_SPI_INTEL_SPI_PCI=m
-CONFIG_SPI_INTEL_SPI_PLATFORM=m
-CONFIG_MTD_UBI=m
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_FASTMAP=y
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_HYPERBUS=m
-# CONFIG_OF is not set
+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
+CONFIG_ARCH_HAS_ZONE_DMA_SET=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
+CONFIG_ARCH_HIBERNATION_HEADER=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
 CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_PARPORT=m
-CONFIG_PARPORT_PC=m
-CONFIG_PARPORT_SERIAL=m
-CONFIG_PARPORT_PC_FIFO=y
-CONFIG_PARPORT_PC_SUPERIO=y
-CONFIG_PARPORT_PC_PCMCIA=m
-CONFIG_PARPORT_AX88796=m
-CONFIG_PARPORT_1284=y
-CONFIG_PARPORT_NOT_PC=y
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG_MESSAGES is not set
-
-#
-# Protocols
-#
-CONFIG_ISAPNP=y
-CONFIG_PNPBIOS=y
-CONFIG_PNPBIOS_PROC_FS=y
-CONFIG_PNPACPI=y
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_NULL_BLK is not set
-CONFIG_BLK_DEV_FD=m
-CONFIG_BLK_DEV_FD_RAWCMD=y
-CONFIG_CDROM=m
-# CONFIG_PARIDE is not set
-
-CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
-CONFIG_ZRAM=m
-# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
-CONFIG_ZRAM_DEF_COMP_ZSTD=y
-# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
-# CONFIG_ZRAM_DEF_COMP_LZO is not set
-# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
-# CONFIG_ZRAM_DEF_COMP_842 is not set
-CONFIG_ZRAM_WRITEBACK=y
-# CONFIG_ZRAM_MEMORY_TRACKING is not set
-CONFIG_BLK_DEV_UMEM=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_DRBD=m
-# CONFIG_DRBD_FAULT_INJECTION is not set
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_SX8=m
-CONFIG_BLK_DEV_RAM=m
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS=8
+CONFIG_ARCH_MMAP_RND_BITS_MAX=16
+CONFIG_ARCH_MMAP_RND_BITS_MIN=8
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_SPLIT_ARG64=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUPPORTS_ACPI=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_MEMREMAP_PROT=y
+CONFIG_ARCH_USE_MEMTEST=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
+CONFIG_ARCH_USES_PG_UNCACHED=y
+CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
+CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
+CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCNET_1051=m
+CONFIG_ARCNET_1201=m
+CONFIG_ARCNET_CAP=m
+CONFIG_ARCNET_COM20020_CS=m
+CONFIG_ARCNET_COM20020_ISA=m
+CONFIG_ARCNET_COM20020=m
+CONFIG_ARCNET_COM20020_PCI=m
+CONFIG_ARCNET_COM90xxIO=m
+CONFIG_ARCNET_COM90xx=m
+CONFIG_ARCNET=m
+CONFIG_ARCNET_RAW=m
+CONFIG_ARCNET_RIM_I=m
+CONFIG_AS3935=m
+CONFIG_AS73211=m
+CONFIG_AS_AVX512=y
+CONFIG_AS_GFNI=y
+CONFIG_AS_IS_LLVM=y
+CONFIG_ASN1_ENCODER=m
+CONFIG_AS_SHA1_NI=y
+CONFIG_AS_SHA256_NI=y
+CONFIG_AS_TPAUSE=y
+CONFIG_ASUS_LAPTOP=m
+CONFIG_ASUS_NB_WMI=m
+CONFIG_ASUS_TF103C_DOCK=m
+CONFIG_ASUS_WIRELESS=m
+CONFIG_ASUS_WMI=m
+CONFIG_AS_VERSION=160006
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_ASYNC_TX_DMA=y
+CONFIG_ASYNC_XOR=m
+CONFIG_AT76C50X_USB=m
+CONFIG_AT803X_PHY=m
+CONFIG_ATA_ACPI=y
+CONFIG_ATA_GENERIC=m
+CONFIG_ATA=m
+CONFIG_ATA_OVER_ETH=m
+CONFIG_ATA_PIIX=m
+CONFIG_ATARI_PARTITION=y
+CONFIG_ATH10K_CE=y
+CONFIG_ATH10K=m
+CONFIG_ATH10K_PCI=m
+CONFIG_ATH10K_SDIO=m
+CONFIG_ATH10K_USB=m
+CONFIG_ATH11K=m
+CONFIG_ATH11K_PCI=m
+CONFIG_ATH12K=m
+CONFIG_ATH5K=m
+CONFIG_ATH5K_PCI=y
+CONFIG_ATH6KL=m
+CONFIG_ATH6KL_SDIO=m
+CONFIG_ATH6KL_USB=m
+CONFIG_ATH9K_AHB=y
+CONFIG_ATH9K_BTCOEX_SUPPORT=y
+CONFIG_ATH9K_CHANNEL_CONTEXT=y
+CONFIG_ATH9K_COMMON=m
+CONFIG_ATH9K_DYNACK=y
+CONFIG_ATH9K_HTC=m
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_HWRNG=y
+CONFIG_ATH9K=m
+CONFIG_ATH9K_PCI_NO_EEPROM=m
+CONFIG_ATH9K_PCI=y
+CONFIG_ATH9K_PCOEM=y
+CONFIG_ATH9K_RFKILL=y
+CONFIG_ATH9K_WOW=y
+CONFIG_ATH_COMMON=m
+CONFIG_ATLAS_EZO_SENSOR=m
+CONFIG_ATLAS_PH_SENSOR=m
+CONFIG_ATMEL=m
+CONFIG_AUXDISPLAY=y
+CONFIG_AUXILIARY_BUS=y
+CONFIG_AW96103=m
+CONFIG_AX88796B_PHY=m
+CONFIG_AXP20X_ADC=m
+CONFIG_AXP20X_POWER=m
+CONFIG_AXP288_ADC=m
+CONFIG_AXP288_CHARGER=m
+CONFIG_AXP288_FUEL_GAUGE=m
+CONFIG_B43_BCMA_PIO=y
+CONFIG_B43_BCMA=y
+CONFIG_B43_BUSES_BCMA_AND_SSB=y
+CONFIG_B43_HWRNG=y
+CONFIG_B43_LEDS=y
+CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
+CONFIG_B43LEGACY_DMA=y
+CONFIG_B43LEGACY_HWRNG=y
+CONFIG_B43LEGACY_LEDS=y
+CONFIG_B43LEGACY=m
+CONFIG_B43LEGACY_PCI_AUTOSELECT=y
+CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
+CONFIG_B43LEGACY_PIO=y
+CONFIG_B43=m
+CONFIG_B43_PCI_AUTOSELECT=y
+CONFIG_B43_PCICORE_AUTOSELECT=y
+CONFIG_B43_PHY_G=y
+CONFIG_B43_PHY_HT=y
+CONFIG_B43_PHY_LP=y
+CONFIG_B43_PHY_N=y
+CONFIG_B43_PIO=y
+CONFIG_B43_SDIO=y
+CONFIG_B43_SSB=y
+CONFIG_BACKLIGHT_ADP8860=m
+CONFIG_BACKLIGHT_ADP8870=m
+CONFIG_BACKLIGHT_APPLE=m
+CONFIG_BACKLIGHT_ARCXCNN=m
+CONFIG_BACKLIGHT_BD6107=m
+CONFIG_BACKLIGHT_CARILLO_RANCH=m
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_DA9052=m
+CONFIG_BACKLIGHT_GPIO=m
+CONFIG_BACKLIGHT_KTD253=m
+CONFIG_BACKLIGHT_KTD2801=m
+CONFIG_BACKLIGHT_KTZ8866=m
+CONFIG_BACKLIGHT_LM3533=m
+CONFIG_BACKLIGHT_LM3630A=m
+CONFIG_BACKLIGHT_LM3639=m
+CONFIG_BACKLIGHT_LP855X=m
+CONFIG_BACKLIGHT_LV5207LP=m
+CONFIG_BACKLIGHT_MP3309C=m
+CONFIG_BACKLIGHT_MT6370=m
+CONFIG_BACKLIGHT_PCF50633=m
+CONFIG_BACKLIGHT_PWM=m
+CONFIG_BACKLIGHT_QCOM_WLED=m
+CONFIG_BACKLIGHT_RAVE_SP=m
+CONFIG_BACKLIGHT_RT4831=m
+CONFIG_BACKLIGHT_SAHARA=m
+CONFIG_BACKLIGHT_SKY81452=m
+CONFIG_BACKLIGHT_WM831X=m
+CONFIG_BARCO_P50_GPIO=m
+CONFIG_BAREUDP=m
+CONFIG_BATTERY_AXP20X=m
+CONFIG_BATTERY_BQ27XXX_HDQ=m
+CONFIG_BATTERY_BQ27XXX_I2C=m
+CONFIG_BATTERY_BQ27XXX=m
+CONFIG_BATTERY_CW2015=m
+CONFIG_BATTERY_DA9052=m
+CONFIG_BATTERY_DA9150=m
+CONFIG_BATTERY_DS2760=m
+CONFIG_BATTERY_DS2780=m
+CONFIG_BATTERY_DS2781=m
+CONFIG_BATTERY_DS2782=m
+CONFIG_BATTERY_GAUGE_LTC2941=m
+CONFIG_BATTERY_GOLDFISH=m
+CONFIG_BATTERY_MAX17040=m
+CONFIG_BATTERY_MAX17042=m
+CONFIG_BATTERY_MAX1721X=m
+CONFIG_BATTERY_RT5033=m
+CONFIG_BATTERY_SBS=m
+CONFIG_BATTERY_SURFACE=m
+CONFIG_BATTERY_UG3105=m
+CONFIG_BCACHE_ASYNC_REGISTRATION=y
+CONFIG_BCACHE=m
+CONFIG_BCH_CONST_M=14
+CONFIG_BCH_CONST_T=4
+CONFIG_BCH=m
+CONFIG_BCM54140_PHY=m
+CONFIG_BCM7XXX_PHY=m
+CONFIG_BCM84881_PHY=m
+CONFIG_BCM87XX_PHY=m
+CONFIG_BCMA_BLOCKIO=y
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
+CONFIG_BCMA_DRIVER_GPIO=y
+CONFIG_BCMA_DRIVER_PCI=y
+CONFIG_BCMA_HOST_PCI_POSSIBLE=y
+CONFIG_BCMA_HOST_PCI=y
+CONFIG_BCMA_HOST_SOC=y
+CONFIG_BCMA=m
+CONFIG_BCMA_SFLASH=y
+CONFIG_BCM_KONA_USB2_PHY=m
+CONFIG_BCM_NET_PHYLIB=m
+CONFIG_BCM_NET_PHYPTP=m
+CONFIG_BCM_VK=m
+CONFIG_BCM_VK_TTY=y
+CONFIG_BD79703=m
+CONFIG_BE2ISCSI=m
+CONFIG_BFQ_GROUP_IOSCHED=y
+CONFIG_BH1745=m
+CONFIG_BH1750=m
+CONFIG_BH1780=m
+CONFIG_BINFMT_MISC=m
+CONFIG_BLK_CGROUP_IOLATENCY=y
+CONFIG_BLK_CGROUP_PUNT_BIO=y
+CONFIG_BLK_CGROUP_RWSTAT=y
+CONFIG_BLK_CGROUP=y
+CONFIG_BLK_DEV_3W_XXXX_RAID=m
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_DM=m
+CONFIG_BLK_DEV_DRBD=m
+CONFIG_BLK_DEV_FD=m
+CONFIG_BLK_DEV_FD_RAWCMD=y
+CONFIG_BLK_DEV_INTEGRITY_T10=m
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
+CONFIG_BLK_DEV_PMEM=m
 CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM=m
 CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-CONFIG_CDROM_PKTCDVD_WCACHE=y
-CONFIG_ATA_OVER_ETH=m
-CONFIG_VIRTIO_BLK=m
 CONFIG_BLK_DEV_RBD=m
-CONFIG_BLK_DEV_RSXX=m
-CONFIG_BLK_DEV_RNBD=y
 CONFIG_BLK_DEV_RNBD_CLIENT=m
 CONFIG_BLK_DEV_RNBD_SERVER=m
-
-#
-# NVME Support
-#
-CONFIG_NVME_CORE=m
-CONFIG_BLK_DEV_NVME=m
-# CONFIG_NVME_MULTIPATH is not set
-CONFIG_NVME_VERBOSE_ERRORS=y
-CONFIG_NVME_HWMON=y
-CONFIG_NVME_FABRICS=m
-CONFIG_NVME_RDMA=m
-CONFIG_NVME_FC=m
-CONFIG_NVME_TCP=m
-CONFIG_NVME_TARGET=m
-CONFIG_NVME_TARGET_PASSTHRU=y
-CONFIG_NVME_TARGET_LOOP=m
-CONFIG_NVME_TARGET_RDMA=m
-CONFIG_NVME_TARGET_FC=m
-CONFIG_NVME_TARGET_FCLOOP=m
-CONFIG_NVME_TARGET_TCP=m
-# end of NVME Support
-
-#
-# Misc devices
-#
-CONFIG_SENSORS_LIS3LV02D=m
-CONFIG_AD525X_DPOT=m
-CONFIG_AD525X_DPOT_I2C=m
-CONFIG_AD525X_DPOT_SPI=m
-# CONFIG_DUMMY_IRQ is not set
-CONFIG_IBM_ASM=m
-CONFIG_PHANTOM=m
-CONFIG_TIFM_CORE=m
-CONFIG_TIFM_7XX1=m
-CONFIG_ICS932S401=m
-CONFIG_ENCLOSURE_SERVICES=m
-CONFIG_HP_ILO=m
-CONFIG_APDS9802ALS=m
-CONFIG_ISL29003=m
-CONFIG_ISL29020=m
-CONFIG_SENSORS_TSL2550=m
-CONFIG_SENSORS_BH1770=m
-CONFIG_SENSORS_APDS990X=m
-CONFIG_HMC6352=m
-CONFIG_DS1682=m
-CONFIG_VMWARE_BALLOON=m
-CONFIG_PCH_PHUB=m
-CONFIG_LATTICE_ECP3_CONFIG=m
-CONFIG_SRAM=y
-CONFIG_DW_XDATA_PCIE=m
-CONFIG_PCI_ENDPOINT_TEST=m
-CONFIG_XILINX_SDFEC=m
-CONFIG_MISC_RTSX=m
-CONFIG_PVPANIC=m
-CONFIG_GP_PCI1XXXX=m
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-CONFIG_EEPROM_AT24=m
-CONFIG_EEPROM_AT25=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_EEPROM_MAX6875=m
-CONFIG_EEPROM_93CX6=m
-CONFIG_EEPROM_93XX46=m
-CONFIG_EEPROM_IDT_89HPESX=m
-CONFIG_EEPROM_EE1004=m
-# end of EEPROM support
-
-CONFIG_CB710_CORE=m
-# CONFIG_CB710_DEBUG is not set
-CONFIG_CB710_DEBUG_ASSUMPTIONS=y
-
-#
-# Texas Instruments shared transport line discipline
-#
-CONFIG_TI_ST=m
-# end of Texas Instruments shared transport line discipline
-
-CONFIG_SENSORS_LIS3_I2C=m
-
-#
-# Altera FPGA firmware download module (requires I2C)
-#
-CONFIG_ALTERA_STAPL=m
-CONFIG_INTEL_MEI=y
-CONFIG_INTEL_MEI_ME=y
-CONFIG_INTEL_MEI_TXE=m
-CONFIG_INTEL_MEI_VIRTIO=m
-CONFIG_INTEL_MEI_HDCP=m
-CONFIG_INTEL_MEI_PXP=m
-CONFIG_VMWARE_VMCI=m
-
-#
-# Intel MIC & related support
-#
-CONFIG_VOP_BUS=m
-CONFIG_VOP=m
-# end of Intel MIC & related support
-
-CONFIG_ECHO=m
-CONFIG_BCM_VK=m
-CONFIG_BCM_VK_TTY=y
-CONFIG_MISC_ALCOR_PCI=m
-CONFIG_MISC_RTSX_PCI=m
-CONFIG_MISC_RTSX_USB=m
-CONFIG_HABANA_AI=m
-CONFIG_UACCE=m
-CONFIG_PVPANIC=y
-CONFIG_PVPANIC_MMIO=m
-CONFIG_PVPANIC_PCI=m
-# end of Misc devices
-
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=m
-CONFIG_RAID_ATTRS=m
-CONFIG_SCSI=m
-CONFIG_SCSI_DMA=y
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
+CONFIG_BLK_DEV_RNBD=y
 CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
 CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
+CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BLK_DEV_UBLK=m
+CONFIG_BLK_DEV_ZONED_LOOP=m
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_ICQ=y
+CONFIG_BLK_MQ_STACKING=y
+CONFIG_BLK_WBT_MQ=y
+CONFIG_BLK_WBT=y
+CONFIG_BLOCK_HOLDER_DEPRECATED=y
+CONFIG_BMA220=m
+CONFIG_BMA400_I2C=m
+CONFIG_BMA400=m
+CONFIG_BMA400_SPI=m
+CONFIG_BMC150_ACCEL_I2C=m
+CONFIG_BMC150_ACCEL=m
+CONFIG_BMC150_ACCEL_SPI=m
+CONFIG_BMC150_MAGN_I2C=m
+CONFIG_BMC150_MAGN=m
+CONFIG_BMC150_MAGN_SPI=m
+CONFIG_BME680_I2C=m
+CONFIG_BME680=m
+CONFIG_BME680_SPI=m
+CONFIG_BMG160_I2C=m
+CONFIG_BMG160=m
+CONFIG_BMG160_SPI=m
+CONFIG_BMI088_ACCEL=m
+CONFIG_BMI088_ACCEL_SPI=m
+CONFIG_BMI160_I2C=m
+CONFIG_BMI160=m
+CONFIG_BMI160_SPI=m
+CONFIG_BMI323_I2C=m
+CONFIG_BMI323_SPI=m
+CONFIG_BMP280_I2C=m
+CONFIG_BMP280=m
+CONFIG_BMP280_SPI=m
+CONFIG_BOARD_TPCI200=m
+CONFIG_BONDING=m
+CONFIG_BOOT_CONFIG=y
+CONFIG_BOOT_VESA_SUPPORT=y
+CONFIG_BOSCH_BNO055_I2C=m
+CONFIG_BOSCH_BNO055=m
+CONFIG_BOSCH_BNO055_SERIAL=m
+CONFIG_BOUNCE=y
+CONFIG_BPF_JIT_DEFAULT_ON=y
+CONFIG_BRCMFMAC=m
+CONFIG_BRCMFMAC_PCIE=y
+CONFIG_BRCMFMAC_PROTO_BCDC=y
+CONFIG_BRCMFMAC_PROTO_MSGBUF=y
+CONFIG_BRCMFMAC_SDIO=y
+CONFIG_BRCMFMAC_USB=y
+CONFIG_BRCMSMAC_LEDS=y
+CONFIG_BRCMSMAC=m
+CONFIG_BRCM_TRACING=y
+CONFIG_BRCMUTIL=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_BSD_DISKLABEL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BTREE=y
+CONFIG_BTT=y
+CONFIG_BUG=y
+CONFIG_BUILD_SALT="97aada2af1e16dbcdfedca01595db288dbfb0d58"
+CONFIG_CADENCE_WATCHDOG=m
+CONFIG_CAIF=m
+CONFIG_CAIF_NETDEV=m
+CONFIG_CAIF_USB=m
+CONFIG_CAN_8DEV_USB=m
+CONFIG_CAN_BCM=m
+CONFIG_CAN_CALC_BITTIMING=y
+CONFIG_CAN_CAN327=m
+CONFIG_CAN_CC770_ISA=m
+CONFIG_CAN_CC770=m
+CONFIG_CAN_CC770_PLATFORM=m
+CONFIG_CAN_C_CAN=m
+CONFIG_CAN_C_CAN_PCI=m
+CONFIG_CAN_C_CAN_PLATFORM=m
+CONFIG_CAN_CTUCANFD=m
+CONFIG_CAN_CTUCANFD_PCI=m
+CONFIG_CAN_DEV=m
+CONFIG_CAN_EMS_PCI=m
+CONFIG_CAN_EMS_PCMCIA=m
+CONFIG_CAN_EMS_USB=m
+CONFIG_CAN_ESD_402_PCI=m
+CONFIG_CAN_ESD_USB=m
+CONFIG_CAN_ETAS_ES58X=m
+CONFIG_CAN_F81601=m
+CONFIG_CAN_F81604=m
+CONFIG_CAN_GS_USB=m
+CONFIG_CAN_GW=m
+CONFIG_CAN_HI311X=m
+CONFIG_CAN_IFI_CANFD=m
+CONFIG_CAN_ISOTP=m
+CONFIG_CAN_J1939=m
+CONFIG_CAN_JANZ_ICAN3=m
+CONFIG_CAN_KVASER_PCIEFD=m
+CONFIG_CAN_KVASER_PCI=m
+CONFIG_CAN_KVASER_USB=m
+CONFIG_CAN=m
+CONFIG_CAN_M_CAN=m
+CONFIG_CAN_M_CAN_PCI=m
+CONFIG_CAN_M_CAN_PLATFORM=m
+CONFIG_CAN_M_CAN_TCAN4X5X=m
+CONFIG_CAN_MCBA_USB=m
+CONFIG_CAN_MCP251XFD=m
+CONFIG_CAN_MCP251X=m
+CONFIG_CAN_NCT6694=m
+CONFIG_CAN_NETLINK=y
+CONFIG_CAN_PEAK_PCIEC=y
+CONFIG_CAN_PEAK_PCIEFD=m
+CONFIG_CAN_PEAK_PCI=m
+CONFIG_CAN_PEAK_PCMCIA=m
+CONFIG_CAN_PEAK_USB=m
+CONFIG_CAN_PLX_PCI=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_RX_OFFLOAD=y
+CONFIG_CAN_SJA1000_ISA=m
+CONFIG_CAN_SJA1000=m
+CONFIG_CAN_SJA1000_PLATFORM=m
+CONFIG_CAN_SLCAN=m
+CONFIG_CAN_SOFTING_CS=m
+CONFIG_CAN_SOFTING=m
+CONFIG_CAN_UCAN=m
+CONFIG_CAN_VCAN=m
+CONFIG_CAN_VXCAN=m
+CONFIG_CAPI_TRACE=y
+CONFIG_CARDBUS=y
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170=m
+CONFIG_CARL9170_WPC=y
+CONFIG_CB710_CORE=m
+CONFIG_CB710_DEBUG_ASSUMPTIONS=y
+CONFIG_CC10001_ADC=m
+CONFIG_CC_CAN_LINK_STATIC=y
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
+CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
+CONFIG_CC_HAS_ENTRY_PADDING=y
+CONFIG_CC_HAS_IBT=y
+CONFIG_CC_HAS_KASAN_SW_TAGS=y
+CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
+CONFIG_CC_HAS_RANDSTRUCT=y
+CONFIG_CC_HAS_RETURN_THUNK=y
+CONFIG_CC_HAS_SANE_STACKPROTECTOR=y
+CONFIG_CC_HAS_SLS=y
+CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough"
+CONFIG_CC_IS_CLANG=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+CONFIG_CCS811=m
+CONFIG_CC_VERSION_TEXT="OpenMandriva 16.0.6-3 clang version 16.0.6 (/builddir/build/BUILD/llvm-project-16.0.6.src/clang 2d21ec58bba683586362941f17e8179860b49206)"
+CONFIG_CDNS_I3C_MASTER=m
+CONFIG_CDROM=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_WCACHE=y
+CONFIG_CEC_CH7322=m
+CONFIG_CEC_CORE=m
+CONFIG_CEC_CROS_EC=m
+CONFIG_CEC_GPIO=m
+CONFIG_CEC_NOTIFIER=y
+CONFIG_CEC_NXP_TDA9950=m
+CONFIG_CEC_PIN=y
+CONFIG_CEC_SECO=m
+CONFIG_CEC_SECO_RC=y
+CONFIG_CEPH_LIB=m
+CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
+CONFIG_CFAG12864B=m
+CONFIG_CFAG12864B_RATE=20
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_CFG80211=m
+CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
+CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
+CONFIG_CFG80211_WEXT_EXPORT=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CGROUP_MISC=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_RDMA=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_WRITEBACK=y
+CONFIG_CHARGER_ADP5061=m
+CONFIG_CHARGER_AXP20X=m
+CONFIG_CHARGER_BD99954=m
+CONFIG_CHARGER_BQ2415X=m
+CONFIG_CHARGER_BQ24190=m
+CONFIG_CHARGER_BQ24257=m
+CONFIG_CHARGER_BQ24735=m
+CONFIG_CHARGER_BQ2515X=m
+CONFIG_CHARGER_BQ256XX=m
+CONFIG_CHARGER_BQ25890=m
+CONFIG_CHARGER_BQ25980=m
+CONFIG_CHARGER_CROS_CONTROL=m
+CONFIG_CHARGER_CROS_PCHG=m
+CONFIG_CHARGER_CROS_USBPD=m
+CONFIG_CHARGER_DA9150=m
+CONFIG_CHARGER_GPIO=m
+CONFIG_CHARGER_ISP1704=m
+CONFIG_CHARGER_LP8727=m
+CONFIG_CHARGER_LT3651=m
+CONFIG_CHARGER_LTC4162L=m
+CONFIG_CHARGER_MANAGER=y
+CONFIG_CHARGER_MAX14577=m
+CONFIG_CHARGER_MAX77693=m
+CONFIG_CHARGER_MAX77705=m
+CONFIG_CHARGER_MAX77976=m
+CONFIG_CHARGER_MAX8903=m
+CONFIG_CHARGER_MP2629=m
+CONFIG_CHARGER_MT6360=m
+CONFIG_CHARGER_MT6370=m
+CONFIG_CHARGER_PCF50633=m
+CONFIG_CHARGER_RT5033=m
+CONFIG_CHARGER_RT9455=m
+CONFIG_CHARGER_RT9467=m
+CONFIG_CHARGER_RT9471=m
+CONFIG_CHARGER_SBS=m
+CONFIG_CHARGER_SMB347=m
+CONFIG_CHARGER_SURFACE=m
+CONFIG_CHARGER_WILCO=m
+CONFIG_CHARLCD_BL_FLASH=y
+CONFIG_CHARLCD=m
+CONFIG_CHECK_SIGNATURE=y
 CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_ENCLOSURE=m
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_ISCSI_ATTRS=m
-CONFIG_SCSI_SAS_ATTRS=m
-CONFIG_SCSI_SAS_LIBSAS=m
-CONFIG_SCSI_SAS_ATA=y
-CONFIG_SCSI_SAS_HOST_SMP=y
-CONFIG_SCSI_SRP_ATTRS=m
-# end of SCSI Transports
-
-CONFIG_SCSI_LOWLEVEL=y
-CONFIG_ISCSI_TCP=m
-CONFIG_ISCSI_BOOT_SYSFS=m
-CONFIG_SCSI_CXGB3_ISCSI=m
-CONFIG_SCSI_CXGB4_ISCSI=m
-CONFIG_SCSI_BNX2_ISCSI=m
-CONFIG_SCSI_BNX2X_FCOE=m
-CONFIG_BE2ISCSI=m
-CONFIG_BLK_DEV_3W_XXXX_RAID=m
-CONFIG_SCSI_HPSA=m
-CONFIG_SCSI_3W_9XXX=m
-CONFIG_SCSI_3W_SAS=m
-CONFIG_SCSI_ACARD=m
-CONFIG_SCSI_AHA152X=m
-CONFIG_SCSI_AHA1542=m
-CONFIG_SCSI_AACRAID=m
-CONFIG_SCSI_AIC7XXX=m
-CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
-CONFIG_AIC7XXX_RESET_DELAY_MS=15000
-# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
-CONFIG_AIC7XXX_DEBUG_MASK=0
-# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC79XX=m
-CONFIG_AIC79XX_CMDS_PER_DEVICE=4
-CONFIG_AIC79XX_RESET_DELAY_MS=15000
-# CONFIG_AIC79XX_DEBUG_ENABLE is not set
-CONFIG_AIC79XX_DEBUG_MASK=0
-# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC94XX=m
-# CONFIG_AIC94XX_DEBUG is not set
-CONFIG_SCSI_MVSAS=m
-# CONFIG_SCSI_MVSAS_DEBUG is not set
-CONFIG_SCSI_MVSAS_TASKLET=y
-CONFIG_SCSI_MVUMI=m
-CONFIG_SCSI_DPT_I2O=m
-CONFIG_SCSI_ADVANSYS=m
-CONFIG_SCSI_ARCMSR=m
-CONFIG_SCSI_ESAS2R=m
-CONFIG_MEGARAID_NEWGEN=y
-CONFIG_MEGARAID_MM=m
-CONFIG_MEGARAID_MAILBOX=m
-CONFIG_MEGARAID_LEGACY=m
-CONFIG_MEGARAID_SAS=m
-CONFIG_SCSI_MPT3SAS=m
-CONFIG_SCSI_MPT2SAS_MAX_SGE=128
-CONFIG_SCSI_MPT3SAS_MAX_SGE=128
-CONFIG_SCSI_MPT2SAS=m
-CONFIG_SCSI_MPI3MR=m
-CONFIG_SCSI_SMARTPQI=m
-CONFIG_SCSI_UFSHCD=m
-CONFIG_SCSI_UFSHCD_PCI=m
-CONFIG_SCSI_UFS_DWC_TC_PCI=m
-CONFIG_SCSI_UFSHCD_PLATFORM=m
-CONFIG_SCSI_UFS_CDNS_PLATFORM=m
-CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m
-# CONFIG_SCSI_UFS_BSG is not set
-CONFIG_SCSI_HPTIOP=m
-CONFIG_SCSI_BUSLOGIC=m
-CONFIG_SCSI_FLASHPOINT=y
-CONFIG_SCSI_MYRB=m
-CONFIG_SCSI_MYRS=m
-CONFIG_VMWARE_PVSCSI=m
-CONFIG_HYPERV_STORAGE=m
-CONFIG_LIBFC=m
-CONFIG_LIBFCOE=m
-CONFIG_FCOE=m
-CONFIG_FCOE_FNIC=m
-CONFIG_SCSI_SNIC=m
-# CONFIG_SCSI_SNIC_DEBUG_FS is not set
-CONFIG_SCSI_DMX3191D=m
-CONFIG_SCSI_FDOMAIN=m
-CONFIG_SCSI_FDOMAIN_PCI=m
-CONFIG_SCSI_FDOMAIN_ISA=m
-CONFIG_SCSI_GDTH=m
-CONFIG_SCSI_ISCI=m
-CONFIG_SCSI_GENERIC_NCR5380=m
-CONFIG_SCSI_IPS=m
-CONFIG_SCSI_INITIO=m
-CONFIG_SCSI_INIA100=m
-CONFIG_SCSI_PPA=m
-CONFIG_SCSI_IMM=m
-# CONFIG_SCSI_IZIP_EPP16 is not set
-# CONFIG_SCSI_IZIP_SLOW_CTR is not set
-CONFIG_SCSI_STEX=m
-CONFIG_SCSI_SYM53C8XX_2=m
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_IPR=m
-# CONFIG_SCSI_IPR_TRACE is not set
-# CONFIG_SCSI_IPR_DUMP is not set
-CONFIG_SCSI_QLOGIC_FAS=m
-CONFIG_SCSI_QLOGIC_1280=m
-CONFIG_SCSI_QLA_FC=m
-CONFIG_TCM_QLA2XXX=m
-# CONFIG_TCM_QLA2XXX_DEBUG is not set
-CONFIG_SCSI_QLA_ISCSI=m
-CONFIG_QEDI=m
-CONFIG_QEDF=m
-CONFIG_SCSI_LPFC=m
-CONFIG_SCSI_EFCT=m
-# CONFIG_SCSI_LPFC_DEBUG_FS is not set
-CONFIG_SCSI_DC395x=m
-CONFIG_SCSI_AM53C974=m
-CONFIG_SCSI_NSP32=m
-CONFIG_SCSI_WD719X=m
-# CONFIG_SCSI_DEBUG is not set
-CONFIG_SCSI_PMCRAID=m
-CONFIG_SCSI_PM8001=m
-CONFIG_SCSI_BFA_FC=m
-CONFIG_SCSI_VIRTIO=m
-CONFIG_SCSI_CHELSIO_FCOE=m
-CONFIG_SCSI_LOWLEVEL_PCMCIA=y
-CONFIG_PCMCIA_AHA152X=m
-CONFIG_PCMCIA_FDOMAIN=m
-CONFIG_PCMCIA_NINJA_SCSI=m
-CONFIG_PCMCIA_QLOGIC=m
-CONFIG_PCMCIA_SYM53C500=m
-CONFIG_SCSI_DH=y
-CONFIG_SCSI_DH_RDAC=m
-CONFIG_SCSI_DH_HP_SW=m
-CONFIG_SCSI_DH_EMC=m
-CONFIG_SCSI_DH_ALUA=m
-# end of SCSI device support
-
-CONFIG_ATA=m
-CONFIG_SATA_HOST=y
-CONFIG_PATA_TIMINGS=y
-# CONFIG_ATA_VERBOSE_ERROR is not set
-CONFIG_ATA_FORCE=y
-CONFIG_ATA_ACPI=y
-CONFIG_SATA_ZPODD=y
-CONFIG_SATA_PMP=y
-
-#
-# Controllers with non-SFF native interface
-#
-CONFIG_SATA_AHCI=m
-CONFIG_SATA_MOBILE_LPM_POLICY=0
-CONFIG_SATA_AHCI_PLATFORM=m
-CONFIG_SATA_INIC162X=m
-CONFIG_SATA_ACARD_AHCI=m
-CONFIG_SATA_SIL24=m
-CONFIG_ATA_SFF=y
-
-#
-# SFF controllers with custom DMA interface
-#
-CONFIG_PDC_ADMA=m
-CONFIG_SATA_QSTOR=m
-CONFIG_SATA_SX4=m
-CONFIG_ATA_BMDMA=y
-
-#
-# SATA SFF controllers with BMDMA
-#
-CONFIG_ATA_PIIX=m
-CONFIG_SATA_DWC=m
-# CONFIG_SATA_DWC_OLD_DMA is not set
-# CONFIG_SATA_DWC_DEBUG is not set
-CONFIG_SATA_MV=m
-CONFIG_SATA_NV=m
-CONFIG_SATA_PROMISE=m
-CONFIG_SATA_SIL=m
-CONFIG_SATA_SIS=m
-CONFIG_SATA_SVW=m
-CONFIG_SATA_ULI=m
-CONFIG_SATA_VIA=m
-CONFIG_SATA_VITESSE=m
-
-#
-# PATA SFF controllers with BMDMA
-#
-CONFIG_PATA_ALI=m
-CONFIG_PATA_AMD=m
-CONFIG_PATA_ARTOP=m
-CONFIG_PATA_ATIIXP=m
-CONFIG_PATA_ATP867X=m
-CONFIG_PATA_CMD64X=m
-CONFIG_PATA_CS5520=m
-CONFIG_PATA_CS5530=m
-CONFIG_PATA_CS5535=m
-CONFIG_PATA_CS5536=m
-CONFIG_PATA_CYPRESS=m
-CONFIG_PATA_EFAR=m
-CONFIG_PATA_HPT366=m
-CONFIG_PATA_HPT37X=m
-CONFIG_PATA_HPT3X2N=m
-CONFIG_PATA_HPT3X3=m
-CONFIG_PATA_HPT3X3_DMA=y
-CONFIG_PATA_IT8213=m
-CONFIG_PATA_IT821X=m
-CONFIG_PATA_JMICRON=m
-CONFIG_PATA_MARVELL=m
-CONFIG_PATA_NETCELL=m
-CONFIG_PATA_NINJA32=m
-CONFIG_PATA_NS87415=m
-CONFIG_PATA_OLDPIIX=m
-CONFIG_PATA_OPTIDMA=m
-CONFIG_PATA_PDC2027X=m
-CONFIG_PATA_PDC_OLD=m
-CONFIG_PATA_RADISYS=m
-CONFIG_PATA_RDC=m
-CONFIG_PATA_SC1200=m
-CONFIG_PATA_SCH=m
-CONFIG_PATA_SERVERWORKS=m
-CONFIG_PATA_SIL680=m
-CONFIG_PATA_SIS=m
-CONFIG_PATA_TOSHIBA=m
-CONFIG_PATA_TRIFLEX=m
-CONFIG_PATA_VIA=m
-CONFIG_PATA_WINBOND=m
-
-#
-# PIO-only SFF controllers
-#
-CONFIG_PATA_CMD640_PCI=m
-# CONFIG_PATA_ISAPNP is not set
-CONFIG_PATA_MPIIX=m
-CONFIG_PATA_NS87410=m
-CONFIG_PATA_OPTI=m
-CONFIG_PATA_PCMCIA=m
-# CONFIG_PATA_PLATFORM is not set
-CONFIG_PATA_OF_PLATFORM=m
-CONFIG_PATA_QDI=m
-CONFIG_PATA_RZ1000=m
-CONFIG_PATA_WINBOND_VLB=m
-
-#
-# Generic fallback / legacy drivers
-#
-CONFIG_PATA_ACPI=m
-CONFIG_ATA_GENERIC=m
-CONFIG_PATA_LEGACY=m
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID456=m
-CONFIG_MD_MULTIPATH=m
-CONFIG_MD_FAULTY=m
-CONFIG_MD_CLUSTER=m
-CONFIG_BCACHE=m
-# CONFIG_BCACHE_DEBUG is not set
-# CONFIG_BCACHE_CLOSURES_DEBUG is not set
-CONFIG_BCACHE_ASYNC_REGISTRATION=y
-CONFIG_BLK_DEV_DM_BUILTIN=y
-CONFIG_BLK_DEV_DM=m
-# CONFIG_DM_DEBUG is not set
-CONFIG_DM_BUFIO=m
-# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
-CONFIG_DM_BIO_PRISON=m
-CONFIG_DM_PERSISTENT_DATA=m
-CONFIG_DM_UNSTRIPED=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_THIN_PROVISIONING=m
-CONFIG_DM_CACHE=m
-CONFIG_DM_CACHE_SMQ=m
-CONFIG_DM_WRITECACHE=m
-# CONFIG_DM_EBS is not set
-CONFIG_DM_ERA=m
-CONFIG_DM_CLONE=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_LOG_USERSPACE=m
-CONFIG_DM_RAID=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_QL=m
-CONFIG_DM_MULTIPATH_ST=m
-CONFIG_DM_MULTIPATH_HST=m
-CONFIG_DM_MULTIPATH_IOA=m
-CONFIG_DM_DELAY=m
-CONFIG_DM_DUST=m
-CONFIG_DM_UEVENT=y
-CONFIG_DM_FLAKEY=m
-CONFIG_DM_VERITY=m
-CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
-# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING is not set
-# CONFIG_DM_VERITY_FEC is not set
-CONFIG_DM_SWITCH=m
-CONFIG_DM_LOG_WRITES=m
-CONFIG_DM_INTEGRITY=m
-CONFIG_DM_ZONED=m
-CONFIG_TARGET_CORE=m
-CONFIG_TCM_IBLOCK=m
-CONFIG_TCM_FILEIO=m
-CONFIG_TCM_PSCSI=m
-CONFIG_TCM_USER2=m
-CONFIG_LOOPBACK_TARGET=m
-CONFIG_TCM_FC=m
-CONFIG_ISCSI_TARGET=m
-CONFIG_ISCSI_TARGET_CXGB4=m
-CONFIG_SBP_TARGET=m
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=m
-CONFIG_FUSION_FC=m
-CONFIG_FUSION_SAS=m
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_CTL=m
-CONFIG_FUSION_LAN=m
-CONFIG_FUSION_LOGGING=y
-
-#
-# IEEE 1394 (FireWire) support
-#
-CONFIG_FIREWIRE=m
-CONFIG_FIREWIRE_OHCI=m
-CONFIG_FIREWIRE_SBP2=m
-CONFIG_FIREWIRE_NET=m
-CONFIG_FIREWIRE_NOSY=m
-# end of IEEE 1394 (FireWire) support
-
-CONFIG_MACINTOSH_DRIVERS=y
-CONFIG_MAC_EMUMOUSEBTN=m
-CONFIG_NETDEVICES=y
-CONFIG_MII=m
-CONFIG_NET_CORE=y
-CONFIG_BONDING=m
-CONFIG_DUMMY=m
-CONFIG_WIREGUARD=m
-# CONFIG_WIREGUARD_DEBUG is not set
-CONFIG_EQUALIZER=m
-CONFIG_NET_FC=y
-CONFIG_IFB=m
-CONFIG_NET_TEAM=m
-CONFIG_NET_TEAM_MODE_BROADCAST=m
-CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
-CONFIG_NET_TEAM_MODE_RANDOM=m
-CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
-CONFIG_NET_TEAM_MODE_LOADBALANCE=m
-CONFIG_MACVLAN=m
-CONFIG_MACVTAP=m
-CONFIG_IPVLAN_L3S=y
-CONFIG_IPVLAN=m
-CONFIG_IPVTAP=m
-CONFIG_VXLAN=m
-CONFIG_GENEVE=m
-CONFIG_BAREUDP=m
-CONFIG_GTP=m
-CONFIG_MACSEC=m
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_NETPOLL=y
-CONFIG_NET_POLL_CONTROLLER=y
-CONFIG_NTB_NETDEV=m
-CONFIG_RIONET=m
-CONFIG_RIONET_TX_SIZE=128
-CONFIG_RIONET_RX_SIZE=128
-CONFIG_TUN=m
-CONFIG_TAP=m
-# CONFIG_TUN_VNET_CROSS_LE is not set
-CONFIG_VETH=m
-CONFIG_VIRTIO_NET=m
-CONFIG_NLMON=m
-CONFIG_NET_VRF=m
-CONFIG_VSOCKMON=m
-CONFIG_MHI_NET=m
-CONFIG_SUNGEM_PHY=m
-CONFIG_ARCNET=m
-CONFIG_ARCNET_1201=m
-CONFIG_ARCNET_1051=m
-CONFIG_ARCNET_RAW=m
-CONFIG_ARCNET_CAP=m
-CONFIG_ARCNET_COM90xx=m
-CONFIG_ARCNET_COM90xxIO=m
-CONFIG_ARCNET_RIM_I=m
-CONFIG_ARCNET_COM20020=m
-CONFIG_ARCNET_COM20020_ISA=m
-CONFIG_ARCNET_COM20020_PCI=m
-CONFIG_ARCNET_COM20020_CS=m
-CONFIG_ATM_DRIVERS=y
-# CONFIG_ATM_DUMMY is not set
-CONFIG_ATM_TCP=m
-CONFIG_ATM_LANAI=m
-CONFIG_ATM_ENI=m
-# CONFIG_ATM_ENI_DEBUG is not set
-# CONFIG_ATM_ENI_TUNE_BURST is not set
-CONFIG_ATM_FIRESTREAM=m
-CONFIG_ATM_ZATM=m
-# CONFIG_ATM_ZATM_DEBUG is not set
-CONFIG_ATM_NICSTAR=m
-CONFIG_ATM_NICSTAR_USE_SUNI=y
-CONFIG_ATM_NICSTAR_USE_IDT77105=y
-CONFIG_ATM_IDT77252=m
-# CONFIG_ATM_IDT77252_DEBUG is not set
-# CONFIG_ATM_IDT77252_RCV_ALL is not set
-CONFIG_ATM_IDT77252_USE_SUNI=y
-CONFIG_ATM_AMBASSADOR=m
-# CONFIG_ATM_AMBASSADOR_DEBUG is not set
-CONFIG_ATM_HORIZON=m
-# CONFIG_ATM_HORIZON_DEBUG is not set
-CONFIG_ATM_IA=m
-# CONFIG_ATM_IA_DEBUG is not set
-CONFIG_ATM_FORE200E=m
-CONFIG_ATM_FORE200E_USE_TASKLET=y
-CONFIG_ATM_FORE200E_TX_RETRY=16
-CONFIG_ATM_FORE200E_DEBUG=0
-CONFIG_ATM_HE=m
-CONFIG_ATM_HE_USE_SUNI=y
-CONFIG_ATM_SOLOS=m
-# CONFIG_CAIF_DRIVERS is not set
-
-#
-# Distributed Switch Architecture drivers
-#
-CONFIG_B53=m
-CONFIG_B53_SPI_DRIVER=m
-CONFIG_B53_MDIO_DRIVER=m
-CONFIG_B53_MMAP_DRIVER=m
-CONFIG_B53_SRAB_DRIVER=m
-CONFIG_B53_SERDES=m
-CONFIG_NET_DSA_BCM_SF2=m
-CONFIG_NET_DSA_LOOP=m
-CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
-CONFIG_NET_DSA_LANTIQ_GSWIP=m
-CONFIG_NET_DSA_MT7530=m
-CONFIG_NET_DSA_MV88E6060=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-CONFIG_NET_DSA_MV88E6XXX=m
-CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
-CONFIG_NET_DSA_MV88E6XXX_PTP=y
-CONFIG_NET_DSA_MSCC_SEVILLE=m
-CONFIG_NET_DSA_AR9331=m
-CONFIG_NET_DSA_SJA1105=m
-CONFIG_NET_DSA_SJA1105_PTP=y
-CONFIG_NET_DSA_SJA1105_TAS=y
-# CONFIG_NET_DSA_SJA1105_VL is not set
-CONFIG_NET_DSA_XRS700X_I2C=m
-CONFIG_NET_DSA_XRS700X_MDIO=m
-CONFIG_NET_DSA_QCA8K=m
-CONFIG_NET_DSA_REALTEK_SMI=m
-CONFIG_NET_DSA_SMSC_LAN9303=m
-CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
-CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
-CONFIG_NET_DSA_VITESSE_VSC73XX=m
-CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
-CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
-# end of Distributed Switch Architecture drivers
-
-CONFIG_ETHERNET=y
-CONFIG_MDIO=m
-CONFIG_NET_VENDOR_3COM=y
-CONFIG_NET_VENDOR_ACTIONS=y
-CONFIG_OWL_EMAC=m
-CONFIG_EL3=m
-CONFIG_3C515=m
-CONFIG_PCMCIA_3C574=m
-CONFIG_PCMCIA_3C589=m
-CONFIG_VORTEX=m
-CONFIG_TYPHOON=m
-CONFIG_NET_VENDOR_ADAPTEC=y
-CONFIG_ADAPTEC_STARFIRE=m
-CONFIG_NET_VENDOR_AGERE=y
-CONFIG_ET131X=m
-CONFIG_NET_VENDOR_ALACRITECH=y
-CONFIG_SLICOSS=m
-CONFIG_NET_VENDOR_ALTEON=y
-CONFIG_ACENIC=m
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
-CONFIG_ALTERA_TSE=m
-CONFIG_NET_VENDOR_AMAZON=y
-CONFIG_ENA_ETHERNET=m
-CONFIG_NET_VENDOR_AMD=y
-CONFIG_AMD8111_ETH=m
-CONFIG_LANCE=m
-CONFIG_PCNET32=m
-CONFIG_PCMCIA_NMCLAN=m
-CONFIG_NI65=m
-CONFIG_AMD_XGBE=m
-CONFIG_AMD_XGBE_DCB=y
-CONFIG_AMD_XGBE_HAVE_ECC=y
-CONFIG_NET_VENDOR_AQUANTIA=y
-CONFIG_AQTION=m
-CONFIG_NET_VENDOR_ARC=y
-CONFIG_NET_VENDOR_ATHEROS=y
-CONFIG_ATL2=m
-CONFIG_ATL1=m
-CONFIG_ATL1E=m
-CONFIG_ATL1C=m
-CONFIG_ALX=m
-CONFIG_NET_VENDOR_AURORA=y
-CONFIG_AURORA_NB8800=m
-CONFIG_NET_VENDOR_BROADCOM=y
-CONFIG_B44=m
-CONFIG_BCM4908_ENET=m
-CONFIG_B44_PCI_AUTOSELECT=y
-CONFIG_B44_PCICORE_AUTOSELECT=y
-CONFIG_B44_PCI=y
-CONFIG_BCMGENET=m
-CONFIG_BNX2=m
-CONFIG_CNIC=m
-CONFIG_TIGON3=m
-CONFIG_TIGON3_HWMON=y
-CONFIG_BNX2X=m
-CONFIG_BNX2X_SRIOV=y
-CONFIG_SYSTEMPORT=m
-CONFIG_BNXT=m
-CONFIG_BNXT_SRIOV=y
-CONFIG_BNXT_FLOWER_OFFLOAD=y
-CONFIG_BNXT_DCB=y
-CONFIG_BNXT_HWMON=y
-CONFIG_NET_VENDOR_BROCADE=y
-CONFIG_BNA=m
-CONFIG_NET_VENDOR_CADENCE=y
-CONFIG_MACB=m
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MACB_PCI=m
-CONFIG_NET_VENDOR_CAVIUM=y
-CONFIG_NET_VENDOR_CHELSIO=y
-CONFIG_CHELSIO_T1=m
-CONFIG_CHELSIO_T1_1G=y
-CONFIG_CHELSIO_T3=m
-CONFIG_CHELSIO_T4=m
-CONFIG_CHELSIO_T4_DCB=y
-# CONFIG_CHELSIO_T4_FCOE is not set
-CONFIG_CHELSIO_T4VF=m
-CONFIG_CHELSIO_LIB=m
-CONFIG_CHELSIO_INLINE_CRYPTO=y
-CONFIG_CHELSIO_IPSEC_INLINE=m
-CONFIG_NET_VENDOR_CIRRUS=y
-# CONFIG_CS89x0 is not set
-CONFIG_CS89x0_ISA=m
-CONFIG_NET_VENDOR_CISCO=y
-CONFIG_ENIC=m
-# CONFIG_NET_VENDOR_CORTINA is not set
-CONFIG_NET_VENDOR_DAVICOM=y
-CONFIG_DM9051=m
-CONFIG_CX_ECAT=m
-CONFIG_DNET=m
-CONFIG_NET_VENDOR_DEC=y
-CONFIG_NET_TULIP=y
-CONFIG_DE2104X=m
-CONFIG_DE2104X_DSL=0
-CONFIG_TULIP=m
-CONFIG_TULIP_MWI=y
-CONFIG_TULIP_MMIO=y
-CONFIG_TULIP_NAPI=y
-CONFIG_TULIP_NAPI_HW_MITIGATION=y
-CONFIG_DE4X5=m
-CONFIG_WINBOND_840=m
-CONFIG_DM9102=m
-CONFIG_ULI526X=m
-CONFIG_PCMCIA_XIRCOM=m
-CONFIG_NET_VENDOR_DLINK=y
-CONFIG_DL2K=m
-CONFIG_SUNDANCE=m
-# CONFIG_SUNDANCE_MMIO is not set
-CONFIG_NET_VENDOR_EMULEX=y
-CONFIG_BE2NET=m
-CONFIG_BE2NET_HWMON=y
-CONFIG_BE2NET_BE2=y
-CONFIG_BE2NET_BE3=y
-CONFIG_BE2NET_LANCER=y
-CONFIG_BE2NET_SKYHAWK=y
-CONFIG_NET_VENDOR_EZCHIP=y
-CONFIG_NET_VENDOR_FUJITSU=y
-CONFIG_NET_VENDOR_FUNGIBLE=y
-CONFIG_FUN_ETH=m
-CONFIG_PCMCIA_FMVJ18X=m
-CONFIG_NET_VENDOR_GOOGLE=y
-CONFIG_GVE=m
-CONFIG_NET_VENDOR_HUAWEI=y
-CONFIG_HINIC=m
-CONFIG_NET_VENDOR_I825XX=y
-CONFIG_NET_VENDOR_INTEL=y
-CONFIG_E100=m
-CONFIG_E1000=m
-CONFIG_E1000E=m
-CONFIG_E1000E_HWTS=y
-CONFIG_IGB=m
-CONFIG_IGB_HWMON=y
-CONFIG_IGBVF=m
-CONFIG_IXGB=m
-CONFIG_IXGBE=m
-CONFIG_IXGBE_HWMON=y
-CONFIG_IXGBE_DCB=y
-CONFIG_IXGBE_IPSEC=y
-CONFIG_IXGBEVF=m
-CONFIG_IXGBEVF_IPSEC=y
-CONFIG_I40E=m
-CONFIG_I40E_DCB=y
-CONFIG_IAVF=m
-CONFIG_I40EVF=m
-CONFIG_ICE=m
-CONFIG_FM10K=m
-CONFIG_IGC=m
-CONFIG_NET_VENDOR_MICROSOFT=y
-CONFIG_MICROSOFT_MANA=m
-CONFIG_JME=m
-CONFIG_NET_VENDOR_MARVELL=y
-CONFIG_MVMDIO=m
-CONFIG_SKGE=m
-# CONFIG_SKGE_DEBUG is not set
-CONFIG_SKGE_GENESIS=y
-CONFIG_SKY2=m
-# CONFIG_SKY2_DEBUG is not set
-CONFIG_PRESTERA=m
-CONFIG_PRESTERA_PCI=m
-CONFIG_NET_VENDOR_MELLANOX=y
-CONFIG_MLX4_EN=m
-CONFIG_MLX4_EN_DCB=y
-CONFIG_MLX4_CORE=m
-# CONFIG_MLX4_DEBUG is not set
-CONFIG_MLX4_CORE_GEN2=y
-CONFIG_MLX5_CORE=m
-CONFIG_MLX5_ACCEL=y
-CONFIG_MLX5_FPGA=y
-# CONFIG_MLX5_CORE_EN is not set
-CONFIG_MLX5_FPGA_IPSEC=y
-CONFIG_MLXSW_CORE=m
-CONFIG_MLXSW_CORE_HWMON=y
-CONFIG_MLXSW_CORE_THERMAL=y
-CONFIG_MLXSW_PCI=m
-CONFIG_MLXSW_I2C=m
-CONFIG_MLXSW_SWITCHIB=m
-CONFIG_MLXSW_SWITCHX2=m
-CONFIG_MLXSW_SPECTRUM=m
-CONFIG_MLXSW_SPECTRUM_DCB=y
-CONFIG_MLXSW_MINIMAL=m
-CONFIG_MLXFW=m
-CONFIG_MLXFW_GIGE=m
-CONFIG_MLXBF_GIGE=m
-CONFIG_NET_VENDOR_MICREL=y
-CONFIG_KS8842=m
-CONFIG_KS8851=m
-CONFIG_KS8851_MLL=m
-CONFIG_KSZ884X_PCI=m
-CONFIG_NET_VENDOR_MICROCHIP=y
-CONFIG_ENC28J60=m
-# CONFIG_ENC28J60_WRITEVERIFY is not set
-CONFIG_ENCX24J600=m
-CONFIG_LAN743X=m
-CONFIG_SPARX5_SWITCH=m
-CONFIG_NET_VENDOR_MICROSEMI=y
-CONFIG_MSCC_OCELOT_SWITCH_LIB=m
-CONFIG_NET_VENDOR_MYRI=y
-CONFIG_MYRI10GE=m
-CONFIG_FEALNX=m
-CONFIG_NET_VENDOR_NATSEMI=y
-CONFIG_NATSEMI=m
-CONFIG_NS83820=m
-CONFIG_NET_VENDOR_NETERION=y
-CONFIG_S2IO=m
-CONFIG_VXGE=m
-# CONFIG_VXGE_DEBUG_TRACE_ALL is not set
-CONFIG_NET_VENDOR_NETRONOME=y
-CONFIG_NFP=m
-# CONFIG_NFP_APP_FLOWER is not set
-CONFIG_NFP_APP_ABM_NIC=y
-# CONFIG_NFP_DEBUG is not set
-CONFIG_NET_VENDOR_NI=y
-CONFIG_NI_XGE_MANAGEMENT_ENET=m
-CONFIG_NET_VENDOR_8390=y
-CONFIG_PCMCIA_AXNET=m
-# CONFIG_NE2000 is not set
-CONFIG_NE2K_PCI=m
-CONFIG_PCMCIA_PCNET=m
-# CONFIG_ULTRA is not set
-# CONFIG_WD80x3 is not set
-CONFIG_NET_VENDOR_NVIDIA=y
-CONFIG_FORCEDETH=m
-CONFIG_NET_VENDOR_OKI=y
-# CONFIG_PCH_GBE is not set
-CONFIG_ETHOC=m
-CONFIG_NET_VENDOR_PACKET_ENGINES=y
-CONFIG_HAMACHI=m
-CONFIG_YELLOWFIN=m
-CONFIG_NET_VENDOR_PENSANDO=y
-CONFIG_NET_VENDOR_QLOGIC=y
-CONFIG_QLA3XXX=m
-CONFIG_QLCNIC=m
-CONFIG_QLCNIC_SRIOV=y
-CONFIG_QLCNIC_DCB=y
-CONFIG_QLCNIC_HWMON=y
-CONFIG_NETXEN_NIC=m
-CONFIG_QED=m
-CONFIG_QED_LL2=y
-CONFIG_QED_SRIOV=y
-CONFIG_QEDE=m
-CONFIG_QED_ISCSI=y
-CONFIG_QED_FCOE=y
-CONFIG_QED_OOO=y
-CONFIG_NET_VENDOR_QUALCOMM=y
-CONFIG_QCOM_EMAC=m
-CONFIG_RMNET=m
-CONFIG_NET_VENDOR_RDC=y
-CONFIG_R6040=m
-CONFIG_NET_VENDOR_REALTEK=y
-CONFIG_ATP=m
-CONFIG_8139CP=m
-CONFIG_8139TOO=m
-# CONFIG_8139TOO_PIO is not set
-CONFIG_8139TOO_TUNE_TWISTER=y
-CONFIG_8139TOO_8129=y
-# CONFIG_8139_OLD_RX_RESET is not set
-CONFIG_R8169=m
-CONFIG_NET_VENDOR_RENESAS=y
-CONFIG_NET_VENDOR_ROCKER=y
-CONFIG_ROCKER=m
-CONFIG_NET_VENDOR_SAMSUNG=y
-CONFIG_SXGBE_ETH=m
-CONFIG_NET_VENDOR_SEEQ=y
-CONFIG_NET_VENDOR_SOLARFLARE=y
-CONFIG_SFC=m
-CONFIG_SFC_MTD=y
-CONFIG_SFC_MCDI_MON=y
-CONFIG_SFC_SRIOV=y
-CONFIG_SFC_MCDI_LOGGING=y
-CONFIG_SFC_FALCON=m
-CONFIG_SFC_FALCON_MTD=y
-CONFIG_NET_VENDOR_SILAN=y
-CONFIG_SC92031=m
-CONFIG_NET_VENDOR_SIS=y
-CONFIG_SIS900=m
-CONFIG_SIS190=m
-CONFIG_NET_VENDOR_SMSC=y
-# CONFIG_SMC9194 is not set
-CONFIG_PCMCIA_SMC91C92=m
-CONFIG_EPIC100=m
-CONFIG_SMSC911X=m
-CONFIG_SMSC9420=m
-# CONFIG_NET_VENDOR_SOCIONEXT is not set
-CONFIG_NET_VENDOR_STMICRO=y
-CONFIG_STMMAC_ETH=m
-# CONFIG_STMMAC_SELFTESTS is not set
-CONFIG_STMMAC_PLATFORM=m
-CONFIG_DWMAC_LOONGSON=m
-CONFIG_DWMAC_GENERIC=m
-CONFIG_DWMAC_INTEL=m
-CONFIG_STMMAC_PCI=m
-CONFIG_NET_VENDOR_SUN=y
-CONFIG_HAPPYMEAL=m
-CONFIG_SUNGEM=m
-CONFIG_CASSINI=m
-CONFIG_NIU=m
-CONFIG_NET_VENDOR_SYNOPSYS=y
-CONFIG_DWC_XLGMAC=m
-CONFIG_DWC_XLGMAC_PCI=m
-CONFIG_NET_VENDOR_TEHUTI=y
-CONFIG_TEHUTI=m
-CONFIG_NET_VENDOR_TI=y
-# CONFIG_TI_CPSW_PHY_SEL is not set
-CONFIG_TLAN=m
-CONFIG_NET_VENDOR_VIA=y
-CONFIG_VIA_RHINE=m
-CONFIG_VIA_RHINE_MMIO=y
-CONFIG_VIA_VELOCITY=m
-CONFIG_NET_VENDOR_WIZNET=y
-CONFIG_WIZNET_W5100=m
-CONFIG_WIZNET_W5300=m
-# CONFIG_WIZNET_BUS_DIRECT is not set
-# CONFIG_WIZNET_BUS_INDIRECT is not set
-CONFIG_WIZNET_BUS_ANY=y
-CONFIG_WIZNET_W5100_SPI=m
-CONFIG_NET_VENDOR_XILINX=y
-CONFIG_XILINX_EMACLITE=m
-CONFIG_XILINX_AXI_EMAC=m
-CONFIG_XILINX_LL_TEMAC=m
-CONFIG_NET_VENDOR_XIRCOM=y
-CONFIG_PCMCIA_XIRC2PS=m
-CONFIG_FDDI=m
-CONFIG_DEFXX=m
-# CONFIG_DEFXX_MMIO is not set
-CONFIG_SKFP=m
-CONFIG_HIPPI=y
-CONFIG_ROADRUNNER=m
-CONFIG_ROADRUNNER_LARGE_RINGS=y
-CONFIG_NET_SB1000=m
-CONFIG_PHYLINK=m
-CONFIG_PHYLIB=m
-CONFIG_SWPHY=y
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_FIXED_PHY=m
-CONFIG_SFP=m
-
-#
-# MII PHY device drivers
-#
-CONFIG_AMD_PHY=m
-CONFIG_ADIN_PHY=m
-CONFIG_AQUANTIA_PHY=m
-CONFIG_AX88796B_PHY=m
-CONFIG_BROADCOM_PHY=m
-CONFIG_BCM54140_PHY=m
-CONFIG_BCM7XXX_PHY=m
-CONFIG_BCM84881_PHY=m
-CONFIG_BCM87XX_PHY=m
-CONFIG_BCM_NET_PHYLIB=m
-CONFIG_CICADA_PHY=m
-CONFIG_CORTINA_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_ICPLUS_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_INTEL_XWAY_PHY=m
-CONFIG_LSI_ET1011C_PHY=m
-CONFIG_MARVELL_PHY=m
-CONFIG_MARVELL_10G_PHY=m
-CONFIG_MARVELL_88X2222_PHY=m
-CONFIG_MEDIATEK_GE_PHY=m
-CONFIG_MICREL_PHY=m
-CONFIG_MICROCHIP_PHY=m
-CONFIG_MICROCHIP_T1_PHY=m
-CONFIG_MICROSEMI_PHY=m
-CONFIG_MOTORCOMM_PHY=m
-CONFIG_NATIONAL_PHY=m
-CONFIG_NXP_C45_TJA11XX_PHY=m
-CONFIG_NXP_TJA11XX_PHY=m
-CONFIG_AT803X_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_REALTEK_PHY=m
-CONFIG_RENESAS_PHY=m
-CONFIG_ROCKCHIP_PHY=m
-CONFIG_SMSC_PHY=m
-CONFIG_STE10XP=m
-CONFIG_TERANETICS_PHY=m
-CONFIG_DP83822_PHY=m
-CONFIG_DP83TC811_PHY=m
-CONFIG_DP83848_PHY=m
-CONFIG_DP83867_PHY=m
-CONFIG_DP83869_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_XILINX_GMII2RGMII=m
-CONFIG_WWAN=y
-CONFIG_WWAN_HWSIM=m
-CONFIG_WWAN_CORE=m
-CONFIG_RPMSG_WWAN_CTRL=m
-# CONFIG_TEST_MAPLE_TREE is not set
-CONFIG_IOSM=m
-CONFIG_MHI_WWAN_CTRL=m
-CONFIG_MICREL_KS8995MA=m
-CONFIG_MDIO_DEVICE=m
-CONFIG_MDIO_BUS=m
-CONFIG_MDIO_DEVRES=m
-CONFIG_MDIO_BITBANG=m
-CONFIG_MDIO_BCM_UNIMAC=m
-CONFIG_MDIO_GPIO=m
-CONFIG_MDIO_I2C=m
-CONFIG_MDIO_MVUSB=m
-CONFIG_MDIO_MSCC_MIIM=m
-
-#
-# MDIO Multiplexers
-#
-
-#
-# PCS device drivers
-#
-CONFIG_PCS_XPCS=m
-CONFIG_PCS_LYNX=m
-# end of PCS device drivers
-
-CONFIG_PLIP=m
-CONFIG_PPP=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_MPPE=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPPOATM=m
-CONFIG_PPPOE=m
-CONFIG_PPTP=m
-CONFIG_PPPOL2TP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_SLIP=m
-CONFIG_SLHC=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-
-#
-# Host-side USB support is needed for USB Network Adapter support
-#
-CONFIG_USB_NET_DRIVERS=m
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_RTL8152=m
-CONFIG_USB_LAN78XX=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_AX8817X=m
-CONFIG_USB_NET_AX88179_178A=m
-CONFIG_USB_NET_CDCETHER=m
-CONFIG_USB_NET_CDC_EEM=m
-CONFIG_USB_NET_CDC_NCM=m
-CONFIG_USB_NET_HUAWEI_CDC_NCM=m
-CONFIG_USB_NET_CDC_MBIM=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_SR9700=m
-CONFIG_USB_NET_SR9800=m
-CONFIG_USB_NET_SMSC75XX=m
-CONFIG_USB_NET_SMSC95XX=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_NET1080=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_MCS7830=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
-CONFIG_USB_NET_CDC_SUBSET=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_BELKIN=y
-CONFIG_USB_ARMLINUX=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-CONFIG_USB_NET_ZAURUS=m
-CONFIG_USB_NET_CX82310_ETH=m
-CONFIG_USB_NET_KALMIA=m
-CONFIG_USB_NET_QMI_WWAN=m
-CONFIG_USB_HSO=m
-CONFIG_USB_NET_INT51X1=m
-CONFIG_USB_CDC_PHONET=m
-CONFIG_USB_IPHETH=m
-CONFIG_USB_SIERRA_NET=m
-CONFIG_USB_VL600=m
-CONFIG_USB_NET_CH9200=m
-CONFIG_USB_NET_AQC111=m
-CONFIG_USB_RTL8153_ECM=m
-CONFIG_WLAN=y
-# CONFIG_WIRELESS_WDS is not set
-CONFIG_WLAN_VENDOR_ADMTEK=y
-CONFIG_ADM8211=m
-CONFIG_ATH_COMMON=m
-CONFIG_WLAN_VENDOR_ATH=y
-# CONFIG_ATH_DEBUG is not set
-CONFIG_ATH5K=m
-# CONFIG_ATH5K_DEBUG is not set
-# CONFIG_ATH5K_TRACER is not set
-CONFIG_ATH5K_PCI=y
-CONFIG_ATH9K_HW=m
-CONFIG_ATH9K_COMMON=m
-CONFIG_ATH9K_BTCOEX_SUPPORT=y
-CONFIG_ATH9K=m
-CONFIG_ATH9K_PCI=y
-CONFIG_ATH9K_AHB=y
-# CONFIG_ATH9K_DEBUGFS is not set
-CONFIG_ATH9K_DYNACK=y
-CONFIG_ATH9K_WOW=y
-CONFIG_ATH9K_RFKILL=y
-CONFIG_ATH9K_CHANNEL_CONTEXT=y
-CONFIG_ATH9K_PCOEM=y
-CONFIG_ATH9K_PCI_NO_EEPROM=m
-CONFIG_ATH9K_HTC=m
-# CONFIG_ATH9K_HTC_DEBUGFS is not set
-CONFIG_ATH9K_HWRNG=y
-CONFIG_CARL9170=m
-CONFIG_CARL9170_LEDS=y
-CONFIG_CARL9170_WPC=y
-# CONFIG_CARL9170_HWRNG is not set
-CONFIG_ATH6KL=m
-CONFIG_ATH6KL_SDIO=m
-CONFIG_ATH6KL_USB=m
-# CONFIG_ATH6KL_DEBUG is not set
-# CONFIG_ATH6KL_TRACING is not set
-CONFIG_AR5523=m
-CONFIG_WIL6210=m
-CONFIG_WIL6210_ISR_COR=y
-CONFIG_WIL6210_TRACING=y
-CONFIG_WIL6210_DEBUGFS=y
-CONFIG_ATH10K=m
-CONFIG_ATH10K_CE=y
-CONFIG_ATH10K_PCI=m
-CONFIG_ATH10K_SDIO=m
-CONFIG_ATH10K_USB=m
-# CONFIG_ATH10K_DEBUG is not set
-# CONFIG_ATH10K_DEBUGFS is not set
-# CONFIG_ATH10K_TRACING is not set
-CONFIG_WCN36XX=m
-# CONFIG_WCN36XX_DEBUGFS is not set
-CONFIG_ATH11K=m
-CONFIG_ATH11K_PCI=m
-# CONFIG_ATH11K_DEBUG is not set
-# CONFIG_ATH11K_TRACING is not set
-CONFIG_WLAN_VENDOR_ATMEL=y
-CONFIG_ATMEL=m
-CONFIG_PCI_ATMEL=m
-CONFIG_PCMCIA_ATMEL=m
-CONFIG_AT76C50X_USB=m
-CONFIG_WLAN_VENDOR_BROADCOM=y
-CONFIG_B43=m
-CONFIG_B43_BCMA=y
-CONFIG_B43_SSB=y
-CONFIG_B43_BUSES_BCMA_AND_SSB=y
-# CONFIG_B43_BUSES_BCMA is not set
-# CONFIG_B43_BUSES_SSB is not set
-CONFIG_B43_PCI_AUTOSELECT=y
-CONFIG_B43_PCICORE_AUTOSELECT=y
-CONFIG_B43_SDIO=y
-CONFIG_B43_BCMA_PIO=y
-CONFIG_B43_PIO=y
-CONFIG_B43_PHY_G=y
-CONFIG_B43_PHY_N=y
-CONFIG_B43_PHY_LP=y
-CONFIG_B43_PHY_HT=y
-CONFIG_B43_LEDS=y
-CONFIG_B43_HWRNG=y
-# CONFIG_B43_DEBUG is not set
-CONFIG_B43LEGACY=m
-CONFIG_B43LEGACY_PCI_AUTOSELECT=y
-CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
-CONFIG_B43LEGACY_LEDS=y
-CONFIG_B43LEGACY_HWRNG=y
-# CONFIG_B43LEGACY_DEBUG is not set
-CONFIG_B43LEGACY_DMA=y
-CONFIG_B43LEGACY_PIO=y
-CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
-# CONFIG_B43LEGACY_DMA_MODE is not set
-# CONFIG_B43LEGACY_PIO_MODE is not set
-CONFIG_BRCMUTIL=m
-CONFIG_BRCMSMAC=m
-CONFIG_BRCMFMAC=m
-CONFIG_BRCMFMAC_PROTO_BCDC=y
-CONFIG_BRCMFMAC_PROTO_MSGBUF=y
-CONFIG_BRCMFMAC_SDIO=y
-CONFIG_BRCMFMAC_USB=y
-CONFIG_BRCMFMAC_PCIE=y
-CONFIG_BRCM_TRACING=y
-# CONFIG_BRCMDBG is not set
-CONFIG_WLAN_VENDOR_CISCO=y
-CONFIG_AIRO=m
-CONFIG_AIRO_CS=m
-CONFIG_WLAN_VENDOR_INTEL=y
-CONFIG_IPW2100=m
-CONFIG_IPW2100_MONITOR=y
-# CONFIG_IPW2100_DEBUG is not set
-CONFIG_IPW2200=m
-CONFIG_IPW2200_MONITOR=y
-CONFIG_IPW2200_RADIOTAP=y
-CONFIG_IPW2200_PROMISCUOUS=y
-CONFIG_IPW2200_QOS=y
-# CONFIG_IPW2200_DEBUG is not set
-CONFIG_LIBIPW=m
-# CONFIG_LIBIPW_DEBUG is not set
-CONFIG_IWLEGACY=m
-CONFIG_IWL4965=m
-CONFIG_IWL3945=m
-
-#
-# iwl3945 / iwl4965 Debugging Options
-#
-# CONFIG_IWLEGACY_DEBUG is not set
-# end of iwl3945 / iwl4965 Debugging Options
-
-CONFIG_IWLWIFI=m
-CONFIG_IWLWIFI_LEDS=y
-CONFIG_IWLDVM=m
-CONFIG_IWLMVM=m
-CONFIG_IWLWIFI_OPMODE_MODULAR=y
-# CONFIG_IWLWIFI_BCAST_FILTERING is not set
-CONFIG_IWLMEI=m
-
-#
-# Debugging Options
-#
-# CONFIG_IWLWIFI_DEBUG is not set
-CONFIG_IWLWIFI_DEVICE_TRACING=y
-# end of Debugging Options
-
-CONFIG_WLAN_VENDOR_INTERSIL=y
-CONFIG_HOSTAP=m
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_HOSTAP_PLX=m
-CONFIG_HOSTAP_PCI=m
-CONFIG_HOSTAP_CS=m
-CONFIG_HERMES=m
-CONFIG_HERMES_PRISM=y
-CONFIG_HERMES_CACHE_FW_ON_INIT=y
-CONFIG_PLX_HERMES=m
-CONFIG_TMD_HERMES=m
-CONFIG_NORTEL_HERMES=m
-CONFIG_PCI_HERMES=m
-CONFIG_PCMCIA_HERMES=m
-CONFIG_PCMCIA_SPECTRUM=m
-CONFIG_ORINOCO_USB=m
-CONFIG_P54_COMMON=m
-CONFIG_P54_USB=m
-CONFIG_P54_PCI=m
-CONFIG_P54_SPI=m
-CONFIG_P54_SPI_DEFAULT_EEPROM=y
-CONFIG_P54_LEDS=y
-CONFIG_PRISM54=m
-CONFIG_WLAN_VENDOR_MARVELL=y
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_USB=m
-CONFIG_LIBERTAS_CS=m
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_LIBERTAS_SPI=m
-# CONFIG_LIBERTAS_DEBUG is not set
-CONFIG_LIBERTAS_MESH=y
-CONFIG_LIBERTAS_THINFIRM=m
-# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
-CONFIG_LIBERTAS_THINFIRM_USB=m
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
-CONFIG_MWIFIEX_PCIE=m
-CONFIG_MWIFIEX_USB=m
-CONFIG_MWL8K=m
-CONFIG_WLAN_VENDOR_MEDIATEK=y
-CONFIG_MT7601U=m
-CONFIG_MT76_CORE=m
-CONFIG_MT76_LEDS=y
-CONFIG_MT76_USB=m
-CONFIG_MT76_SDIO=m
-CONFIG_MT76x02_LIB=m
-CONFIG_MT76x02_USB=m
-CONFIG_MT76x0_COMMON=m
-CONFIG_MT76x0U=m
-CONFIG_MT76x0E=m
-CONFIG_MT76x2_COMMON=m
-CONFIG_MT76x2E=m
-CONFIG_MT76x2U=m
-CONFIG_MT7603E=m
-CONFIG_MT7615_COMMON=m
-CONFIG_MT7615E=m
-CONFIG_MT7663_USB_SDIO_COMMON=m
-CONFIG_MT7663U=m
-CONFIG_MT7663S=m
-CONFIG_MT7915E=m
-CONFIG_MT7986_WMAC=y
-CONFIG_MT7921E=m
-CONFIG_WLAN_VENDOR_MICROCHIP=y
-CONFIG_WILC1000=m
-CONFIG_WILC1000_SDIO=m
-CONFIG_WILC1000_SPI=m
-# CONFIG_WILC1000_HW_OOB_INTR is not set
-CONFIG_WLAN_VENDOR_RALINK=y
-CONFIG_RT2X00=m
-CONFIG_RT2400PCI=m
-CONFIG_RT2500PCI=m
-CONFIG_RT61PCI=m
-CONFIG_RT2800PCI=m
-CONFIG_RT2800PCI_RT33XX=y
-CONFIG_RT2800PCI_RT35XX=y
-CONFIG_RT2800PCI_RT53XX=y
-CONFIG_RT2800PCI_RT3290=y
-CONFIG_RT2500USB=m
-CONFIG_RT73USB=m
-CONFIG_RT2800USB=m
-CONFIG_RT2800USB_RT33XX=y
-CONFIG_RT2800USB_RT35XX=y
-CONFIG_RT2800USB_RT3573=y
-CONFIG_RT2800USB_RT53XX=y
-CONFIG_RT2800USB_RT55XX=y
-CONFIG_RT2800USB_UNKNOWN=y
-CONFIG_RT2800_LIB=m
-CONFIG_RT2800_LIB_MMIO=m
-CONFIG_RT2X00_LIB_MMIO=m
-CONFIG_RT2X00_LIB_PCI=m
-CONFIG_RT2X00_LIB_USB=m
-CONFIG_RT2X00_LIB=m
-CONFIG_RT2X00_LIB_FIRMWARE=y
-CONFIG_RT2X00_LIB_CRYPTO=y
-CONFIG_RT2X00_LIB_LEDS=y
-# CONFIG_RT2X00_DEBUG is not set
-CONFIG_WLAN_VENDOR_REALTEK=y
-CONFIG_RTL8180=m
-CONFIG_RTL8187=m
-CONFIG_RTL8187_LEDS=y
-CONFIG_RTL_CARDS=m
-CONFIG_RTL8192CE=m
-CONFIG_RTL8192SE=m
-CONFIG_RTL8192DE=m
-CONFIG_RTL8723AE=m
-CONFIG_RTL8723BE=m
-CONFIG_RTL8188EE=m
-CONFIG_RTL8192EE=m
-CONFIG_RTL8821AE=m
-CONFIG_RTL8192CU=m
-CONFIG_RTLWIFI=m
-CONFIG_RTLWIFI_PCI=m
-CONFIG_RTLWIFI_USB=m
-# CONFIG_RTLWIFI_DEBUG is not set
-CONFIG_RTL8192C_COMMON=m
-CONFIG_RTL8723_COMMON=m
-CONFIG_RTLBTCOEXIST=m
-CONFIG_RTL8XXXU=m
-CONFIG_RTL8XXXU_UNTESTED=y
-CONFIG_RTW88=m
-CONFIG_RTW88_CORE=m
-CONFIG_RTW88_PCI=m
-CONFIG_RTW88_8822B=m
-CONFIG_RTW88_8822C=m
-CONFIG_RTW88_8723D=m
-CONFIG_RTW88_8821C=m
-CONFIG_RTW88_8822BE=m
-CONFIG_RTW88_8822CE=m
-CONFIG_RTW88_8723DE=m
-CONFIG_RTW88_8821CE=m
-# CONFIG_RTW88_DEBUG is not set
-# CONFIG_RTW88_DEBUGFS is not set
-CONFIG_WLAN_VENDOR_RSI=y
-CONFIG_RSI_91X=m
-# CONFIG_RSI_DEBUGFS is not set
-CONFIG_RSI_SDIO=m
-CONFIG_RSI_USB=m
-CONFIG_RSI_COEX=y
-CONFIG_WLAN_VENDOR_ST=y
-CONFIG_CW1200=m
-CONFIG_CW1200_WLAN_SDIO=m
-CONFIG_CW1200_WLAN_SPI=m
-CONFIG_WLAN_VENDOR_TI=y
-CONFIG_WL1251=m
-CONFIG_WL1251_SPI=m
-CONFIG_WL1251_SDIO=m
-CONFIG_WL12XX=m
-CONFIG_WL18XX=m
-CONFIG_WLCORE=m
-CONFIG_WLCORE_SDIO=m
-CONFIG_WILINK_PLATFORM_DATA=y
-CONFIG_WLAN_VENDOR_ZYDAS=y
-CONFIG_USB_ZD1201=m
-CONFIG_ZD1211RW=m
-# CONFIG_ZD1211RW_DEBUG is not set
-CONFIG_WLAN_VENDOR_QUANTENNA=y
-CONFIG_QTNFMAC=m
-CONFIG_QTNFMAC_PCIE=m
-CONFIG_PCMCIA_RAYCS=m
-CONFIG_PCMCIA_WL3501=m
-# CONFIG_MAC80211_HWSIM is not set
-CONFIG_USB_NET_RNDIS_WLAN=m
-CONFIG_VIRT_WIFI=m
-
-#
-# WiMAX Wireless Broadband devices
-#
-CONFIG_WIMAX_I2400M=m
-CONFIG_WIMAX_I2400M_USB=m
-CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8
-# end of WiMAX Wireless Broadband devices
-
-CONFIG_WAN=y
-# CONFIG_HOSTESS_SV11 is not set
-# CONFIG_COSA is not set
-CONFIG_LANMEDIA=m
-# CONFIG_SEALEVEL_4021 is not set
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_PCI200SYN=m
-CONFIG_WANXL=m
-CONFIG_PC300TOO=m
-# CONFIG_N2 is not set
-# CONFIG_C101 is not set
-CONFIG_FARSYNC=m
-CONFIG_DLCI=m
-CONFIG_DLCI_MAX=8
-# CONFIG_SDLA is not set
-CONFIG_LAPBETHER=m
-CONFIG_X25_ASY=m
-CONFIG_SBNI=m
-CONFIG_SBNI_MULTILINE=y
-CONFIG_IEEE802154_DRIVERS=m
-CONFIG_IEEE802154_FAKELB=m
-CONFIG_IEEE802154_AT86RF230=m
-# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set
-CONFIG_IEEE802154_MRF24J40=m
-CONFIG_IEEE802154_CC2520=m
-CONFIG_IEEE802154_ATUSB=m
-CONFIG_IEEE802154_ADF7242=m
-CONFIG_IEEE802154_CA8210=m
-# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
-CONFIG_IEEE802154_MCR20A=m
-CONFIG_IEEE802154_HWSIM=m
-CONFIG_VMXNET3=m
-CONFIG_FUJITSU_ES=m
-CONFIG_USB4_NET=m
-CONFIG_HYPERV_NET=m
-CONFIG_NETDEVSIM=m
-CONFIG_NET_FAILOVER=m
-CONFIG_ISDN=y
-CONFIG_ISDN_CAPI=m
-CONFIG_CAPI_TRACE=y
-CONFIG_ISDN_CAPI_MIDDLEWARE=m
-CONFIG_MISDN=m
-CONFIG_MISDN_DSP=m
-CONFIG_MISDN_L1OIP=m
-
-#
-# mISDN hardware drivers
-#
-CONFIG_MISDN_HFCPCI=m
-CONFIG_MISDN_HFCMULTI=m
-CONFIG_MISDN_HFCUSB=m
-CONFIG_MISDN_AVMFRITZ=m
-CONFIG_MISDN_SPEEDFAX=m
-CONFIG_MISDN_INFINEON=m
-CONFIG_MISDN_W6692=m
-CONFIG_MISDN_NETJET=m
-CONFIG_MISDN_HDLC=m
-CONFIG_MISDN_IPAC=m
-CONFIG_MISDN_ISAR=m
-CONFIG_NVM=y
-CONFIG_NVM_PBLK=m
-# CONFIG_NVM_PBLK_DEBUG is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_LEDS=m
-CONFIG_INPUT_FF_MEMLESS=m
-CONFIG_INPUT_POLLDEV=m
-CONFIG_INPUT_SPARSEKMAP=m
-CONFIG_INPUT_MATRIXKMAP=m
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ADC=m
-CONFIG_KEYBOARD_ADP5588=m
-CONFIG_KEYBOARD_ADP5589=m
-CONFIG_KEYBOARD_APPLESPI=m
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_KEYBOARD_QT1050=m
-CONFIG_KEYBOARD_QT1070=m
-CONFIG_KEYBOARD_QT2160=m
-CONFIG_KEYBOARD_DLINK_DIR685=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_GPIO=m
-CONFIG_KEYBOARD_GPIO_POLLED=m
-CONFIG_KEYBOARD_TCA6416=m
-CONFIG_KEYBOARD_TCA8418=m
-CONFIG_KEYBOARD_MATRIX=m
-CONFIG_KEYBOARD_LM8323=m
-CONFIG_KEYBOARD_LM8333=m
-CONFIG_KEYBOARD_MAX7359=m
-CONFIG_KEYBOARD_MCS=m
-CONFIG_KEYBOARD_MPR121=m
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_OPENCORES=m
-CONFIG_KEYBOARD_PINEPHONE=m
-CONFIG_KEYBOARD_SAMSUNG=m
-CONFIG_KEYBOARD_STOWAWAY=m
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_IQS62X=m
-CONFIG_KEYBOARD_TM2_TOUCHKEY=m
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_KEYBOARD_CROS_EC=m
-CONFIG_KEYBOARD_MTK_PMIC=m
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_BYD=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
-CONFIG_MOUSE_PS2_CYPRESS=y
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-CONFIG_MOUSE_PS2_ELANTECH=y
-CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
-CONFIG_MOUSE_PS2_SENTELIC=y
-CONFIG_MOUSE_PS2_TOUCHKIT=y
-CONFIG_MOUSE_PS2_FOCALTECH=y
-# CONFIG_MOUSE_PS2_VMMOUSE is not set
-CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_APPLETOUCH=m
-CONFIG_MOUSE_BCM5974=m
-CONFIG_MOUSE_CYAPA=m
-CONFIG_MOUSE_ELAN_I2C=m
-CONFIG_MOUSE_ELAN_I2C_I2C=y
-CONFIG_MOUSE_ELAN_I2C_SMBUS=y
-# CONFIG_MOUSE_INPORT is not set
-# CONFIG_MOUSE_LOGIBM is not set
-# CONFIG_MOUSE_PC110PAD is not set
-CONFIG_MOUSE_VSXXXAA=m
-CONFIG_MOUSE_GPIO=m
-CONFIG_MOUSE_SYNAPTICS_I2C=m
-CONFIG_MOUSE_SYNAPTICS_USB=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADC=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=m
-CONFIG_JOYSTICK_IFORCE_232=m
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_TWIDJOY=m
-CONFIG_JOYSTICK_ZHENHUA=m
-CONFIG_JOYSTICK_DB9=m
-CONFIG_JOYSTICK_GAMECON=m
-CONFIG_JOYSTICK_TURBOGRAFX=m
-CONFIG_JOYSTICK_AS5011=m
-# CONFIG_JOYSTICK_JOYDUMP is not set
-CONFIG_JOYSTICK_XPAD=m
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_JOYSTICK_WALKERA0701=m
-CONFIG_JOYSTICK_PSXPAD_SPI=m
-CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
-CONFIG_JOYSTICK_PXRC=m
-CONFIG_JOYSTICK_QWIIC=m
-CONFIG_JOYSTICK_FSIA6B=m
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=m
-CONFIG_TABLET_USB_AIPTEK=m
-CONFIG_TABLET_USB_GTCO=m
-CONFIG_TABLET_USB_HANWANG=m
-CONFIG_TABLET_USB_KBTAB=m
-CONFIG_TABLET_USB_PEGASUS=m
-CONFIG_TABLET_SERIAL_WACOM4=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_PROPERTIES=y
-CONFIG_TOUCHSCREEN_ADS7846=m
-CONFIG_TOUCHSCREEN_AD7877=m
-CONFIG_TOUCHSCREEN_AD7879=m
-CONFIG_TOUCHSCREEN_AD7879_I2C=m
-CONFIG_TOUCHSCREEN_AD7879_SPI=m
-CONFIG_TOUCHSCREEN_ADC=m
-CONFIG_TOUCHSCREEN_ATMEL_MXT=m
-# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set
-CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
-CONFIG_TOUCHSCREEN_BU21013=m
-CONFIG_TOUCHSCREEN_BU21029=m
-CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
-CONFIG_TOUCHSCREEN_CY8CTMA140=m
-CONFIG_TOUCHSCREEN_CY8CTMG110=m
-CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
-CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
-CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
-CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
-CONFIG_TOUCHSCREEN_DA9052=m
-CONFIG_TOUCHSCREEN_DYNAPRO=m
-CONFIG_TOUCHSCREEN_HAMPSHIRE=m
-CONFIG_TOUCHSCREEN_EETI=m
-CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
-CONFIG_TOUCHSCREEN_EXC3000=m
-CONFIG_TOUCHSCREEN_FUJITSU=m
-CONFIG_TOUCHSCREEN_GOODIX=m
-CONFIG_TOUCHSCREEN_HIDEEP=m
-CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
-CONFIG_TOUCHSCREEN_ILI210X=m
-CONFIG_TOUCHSCREEN_ILITEK=m
-CONFIG_TOUCHSCREEN_S6SY761=m
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_TOUCHSCREEN_EKTF2127=m
-CONFIG_TOUCHSCREEN_ELAN=m
-CONFIG_TOUCHSCREEN_ELO=m
-CONFIG_TOUCHSCREEN_WACOM_W8001=m
-CONFIG_TOUCHSCREEN_WACOM_I2C=m
-CONFIG_TOUCHSCREEN_MAX11801=m
-CONFIG_TOUCHSCREEN_MCS5000=m
-CONFIG_TOUCHSCREEN_MMS114=m
-CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
-CONFIG_TOUCHSCREEN_MSG2638=m
-CONFIG_TOUCHSCREEN_MTOUCH=m
-CONFIG_TOUCHSCREEN_IMAGIS=m
-CONFIG_TOUCHSCREEN_INEXIO=m
-CONFIG_TOUCHSCREEN_MK712=m
-# CONFIG_TOUCHSCREEN_HTCPEN is not set
-CONFIG_TOUCHSCREEN_PENMOUNT=m
-CONFIG_TOUCHSCREEN_EDT_FT5X06=m
-CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
-CONFIG_TOUCHSCREEN_TOUCHWIN=m
-CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m
-CONFIG_TOUCHSCREEN_UCB1400=m
-CONFIG_TOUCHSCREEN_PIXCIR=m
-CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
-CONFIG_TOUCHSCREEN_WM831X=m
-CONFIG_TOUCHSCREEN_WM97XX=m
-CONFIG_TOUCHSCREEN_WM9705=y
-CONFIG_TOUCHSCREEN_WM9712=y
-CONFIG_TOUCHSCREEN_WM9713=y
-CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-CONFIG_TOUCHSCREEN_MC13783=m
-CONFIG_TOUCHSCREEN_USB_EGALAX=y
-CONFIG_TOUCHSCREEN_USB_PANJIT=y
-CONFIG_TOUCHSCREEN_USB_3M=y
-CONFIG_TOUCHSCREEN_USB_ITM=y
-CONFIG_TOUCHSCREEN_USB_ETURBO=y
-CONFIG_TOUCHSCREEN_USB_GUNZE=y
-CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
-CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
-CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
-CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
-CONFIG_TOUCHSCREEN_USB_GOTOP=y
-CONFIG_TOUCHSCREEN_USB_JASTEC=y
-CONFIG_TOUCHSCREEN_USB_ELO=y
-CONFIG_TOUCHSCREEN_USB_E2I=y
-CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
-CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
-CONFIG_TOUCHSCREEN_USB_NEXIO=y
-CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
-CONFIG_TOUCHSCREEN_TOUCHIT213=m
-CONFIG_TOUCHSCREEN_TSC_SERIO=m
-CONFIG_TOUCHSCREEN_TSC200X_CORE=m
-CONFIG_TOUCHSCREEN_TSC2004=m
-CONFIG_TOUCHSCREEN_TSC2005=m
-CONFIG_TOUCHSCREEN_TSC2007=m
-CONFIG_TOUCHSCREEN_TSC2007_IIO=y
-CONFIG_TOUCHSCREEN_PCAP=m
-CONFIG_TOUCHSCREEN_RM_TS=m
-CONFIG_TOUCHSCREEN_SILEAD=m
-CONFIG_TOUCHSCREEN_SIS_I2C=m
-CONFIG_TOUCHSCREEN_ST1232=m
-CONFIG_TOUCHSCREEN_STMFTS=m
-CONFIG_TOUCHSCREEN_SUR40=m
-CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
-CONFIG_TOUCHSCREEN_SX8654=m
-CONFIG_TOUCHSCREEN_TPS6507X=m
-CONFIG_TOUCHSCREEN_ZET6223=m
-CONFIG_TOUCHSCREEN_ZFORCE=m
-CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
-CONFIG_TOUCHSCREEN_ROHM_BU21023=m
-CONFIG_TOUCHSCREEN_IQS5XX=m
-CONFIG_TOUCHSCREEN_ZINITIX=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_ATC260X_ONKEY=m
-CONFIG_INPUT_88PM80X_ONKEY=m
-CONFIG_INPUT_AD714X=m
-CONFIG_INPUT_AD714X_I2C=m
-CONFIG_INPUT_AD714X_SPI=m
-CONFIG_INPUT_ARIZONA_HAPTICS=m
-CONFIG_INPUT_BMA150=m
-CONFIG_INPUT_E3X0_BUTTON=m
-CONFIG_INPUT_PCSPKR=m
-CONFIG_INPUT_MAX77693_HAPTIC=m
-CONFIG_INPUT_MC13783_PWRBUTTON=m
-CONFIG_INPUT_MMA8450=m
-CONFIG_INPUT_APANEL=m
-CONFIG_INPUT_GPIO_BEEPER=m
-CONFIG_INPUT_GPIO_DECODER=m
-CONFIG_INPUT_GPIO_VIBRA=m
-# CONFIG_INPUT_WISTRON_BTNS is not set
-CONFIG_INPUT_ATLAS_BTNS=m
-CONFIG_INPUT_ATI_REMOTE2=m
-CONFIG_INPUT_KEYSPAN_REMOTE=m
-CONFIG_INPUT_KXTJ9=m
-CONFIG_INPUT_POWERMATE=m
-CONFIG_INPUT_YEALINK=m
-CONFIG_INPUT_CM109=m
-CONFIG_INPUT_REGULATOR_HAPTIC=m
-CONFIG_INPUT_RETU_PWRBUTTON=m
-CONFIG_INPUT_AXP20X_PEK=m
-CONFIG_INPUT_UINPUT=m
-CONFIG_INPUT_PCF50633_PMU=m
-CONFIG_INPUT_PCF8574=m
-CONFIG_INPUT_PWM_BEEPER=m
-CONFIG_INPUT_PWM_VIBRA=m
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-CONFIG_INPUT_DA7280_HAPTICS=m
-CONFIG_INPUT_DA9052_ONKEY=m
-CONFIG_INPUT_DA9063_ONKEY=m
-CONFIG_INPUT_WM831X_ON=m
-CONFIG_INPUT_PCAP=m
-CONFIG_INPUT_ADXL34X=m
-CONFIG_INPUT_IBM_PANEL=m
-CONFIG_INPUT_ADXL34X_I2C=m
-CONFIG_INPUT_ADXL34X_SPI=m
-CONFIG_INPUT_IMS_PCU=m
-CONFIG_INPUT_IQS269A=m
-CONFIG_INPUT_IQS626A=m
-CONFIG_INPUT_CMA3000=m
-CONFIG_INPUT_CMA3000_I2C=m
-CONFIG_INPUT_IDEAPAD_SLIDEBAR=m
-CONFIG_INPUT_SOC_BUTTON_ARRAY=m
-CONFIG_INPUT_DRV260X_HAPTICS=m
-CONFIG_INPUT_DRV2665_HAPTICS=m
-CONFIG_INPUT_DRV2667_HAPTICS=m
-CONFIG_INPUT_RAVE_SP_PWRBUTTON=m
-CONFIG_INPUT_RT5120_PWRKEY=m
-CONFIG_RMI4_CORE=m
-CONFIG_RMI4_I2C=m
-CONFIG_RMI4_SPI=m
-CONFIG_RMI4_SMB=m
-CONFIG_RMI4_F03=y
-CONFIG_RMI4_F03_SERIO=m
-CONFIG_RMI4_2D_SENSOR=y
-CONFIG_RMI4_F11=y
-CONFIG_RMI4_F12=y
-CONFIG_RMI4_F30=y
-CONFIG_RMI4_F34=y
-CONFIG_RMI4_F3A=y
-CONFIG_RMI4_F54=y
-CONFIG_RMI4_F55=y
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=m
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_SERIO_I8042=y
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_CT82C710=m
-CONFIG_SERIO_PARKBD=m
-CONFIG_SERIO_PCIPS2=m
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_RAW=m
-CONFIG_SERIO_ALTERA_PS2=m
-CONFIG_SERIO_PS2MULT=m
-CONFIG_SERIO_ARC_PS2=m
-CONFIG_HYPERV_KEYBOARD=m
-CONFIG_SERIO_GPIO_PS2=m
-CONFIG_USERIO=m
-CONFIG_GAMEPORT=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_GAMEPORT_EMU10K1=m
-CONFIG_GAMEPORT_FM801=m
-# end of Hardware I/O ports
-# end of Input device support
-
-#
-# Character devices
-#
-CONFIG_TTY=y
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LDISC_AUTOLOAD=y
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_EARLYCON=y
-CONFIG_SERIAL_8250=y
-# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-CONFIG_SERIAL_8250_PNP=y
-# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
-CONFIG_SERIAL_8250_FINTEK=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_DMA=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_CS=m
-CONFIG_SERIAL_8250_MEN_MCB=m
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-# CONFIG_SERIAL_8250_FOURPORT is not set
-# CONFIG_SERIAL_8250_ACCENT is not set
-# CONFIG_SERIAL_8250_BOCA is not set
-# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
-# CONFIG_SERIAL_8250_HUB6 is not set
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_DW=m
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_8250_LPSS=y
-CONFIG_SERIAL_8250_MID=y
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_MAX3100=m
-CONFIG_SERIAL_MAX310X=y
-CONFIG_SERIAL_UARTLITE=m
-CONFIG_SERIAL_UARTLITE_NR_UARTS=1
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_JSM=m
-CONFIG_SERIAL_LANTIQ=m
-CONFIG_SERIAL_SCCNXP=m
-CONFIG_SERIAL_SC16IS7XX_CORE=m
-CONFIG_SERIAL_SC16IS7XX=m
-CONFIG_SERIAL_SC16IS7XX_I2C=y
-CONFIG_SERIAL_SC16IS7XX_SPI=y
-# CONFIG_SERIAL_TIMBERDALE is not set
-CONFIG_SERIAL_BCM63XX=m
-CONFIG_SERIAL_ALTERA_JTAGUART=m
-CONFIG_SERIAL_ALTERA_UART=m
-CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
-CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
-CONFIG_SERIAL_IFX6X60=m
-# CONFIG_SERIAL_PCH_UART is not set
-CONFIG_SERIAL_ARC=m
-CONFIG_SERIAL_ARC_NR_PORTS=1
-CONFIG_SERIAL_RP2=m
-CONFIG_SERIAL_RP2_NR_UARTS=32
-CONFIG_SERIAL_FSL_LPUART=m
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_FSL_LINFLEXUART=m
-CONFIG_SERIAL_MEN_Z135=m
-CONFIG_SERIAL_SPRD=m
-# end of Serial drivers
-
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_ROCKETPORT=m
-CONFIG_CYCLADES=m
-CONFIG_CYZ_INTR=y
-CONFIG_MOXA_INTELLIO=m
-CONFIG_MOXA_SMARTIO=m
-CONFIG_SYNCLINK=m
-CONFIG_SYNCLINKMP=m
-CONFIG_SYNCLINK_GT=m
-CONFIG_ISI=m
-CONFIG_N_HDLC=m
-CONFIG_N_GSM=m
-CONFIG_NOZOMI=m
-CONFIG_NULL_TTY=m
-CONFIG_TRACE_ROUTER=m
-CONFIG_TRACE_SINK=m
-CONFIG_HVC_DRIVER=y
-CONFIG_SERIAL_DEV_BUS=m
-# CONFIG_TTY_PRINTK is not set
-CONFIG_PRINTER=m
-CONFIG_LP_CONSOLE=y
-CONFIG_PPDEV=m
-CONFIG_VIRTIO_CONSOLE=m
-CONFIG_IPMI_HANDLER=m
-CONFIG_IPMI_DMI_DECODE=y
-CONFIG_IPMI_PLAT_DATA=y
-CONFIG_IPMI_PANIC_EVENT=y
-CONFIG_IPMI_PANIC_STRING=y
-CONFIG_IPMI_DEVICE_INTERFACE=m
-CONFIG_IPMI_SI=m
-CONFIG_IPMI_SSIF=m
-CONFIG_IPMI_WATCHDOG=m
-CONFIG_IPMI_POWEROFF=m
-CONFIG_NPCM7XX_KCS_IPMI_BMC=m
-CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m
-CONFIG_IPMI_KCS_BMC_SERIO=m
-CONFIG_IPMB_DEVICE_INTERFACE=m
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=y
-CONFIG_HW_RANDOM_INTEL=y
-CONFIG_HW_RANDOM_AMD=y
-CONFIG_HW_RANDOM_BA431=y
-CONFIG_HW_RANDOM_GEODE=y
-CONFIG_HW_RANDOM_VIA=y
-# CONFIG_HW_RANDOM_VIRTIO is not set
-CONFIG_HW_RANDOM_XIPHERA=m
-# CONFIG_DTLK is not set
-CONFIG_APPLICOM=m
-# CONFIG_SONYPI is not set
-
-#
-# PCMCIA character devices
-#
-CONFIG_SYNCLINK_CS=m
-CONFIG_CARDMAN_4000=m
-CONFIG_CARDMAN_4040=m
-CONFIG_SCR24X=m
-CONFIG_IPWIRELESS=m
-# end of PCMCIA character devices
-
-CONFIG_MWAVE=m
-# CONFIG_PC8736x_GPIO is not set
-# CONFIG_NSC_GPIO is not set
-CONFIG_DEVMEM=y
-# CONFIG_DEVKMEM is not set
-CONFIG_NVRAM=m
-CONFIG_RAW_DRIVER=m
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_DEVPORT=y
-CONFIG_HPET=y
-CONFIG_HPET_MMAP=y
-CONFIG_HPET_MMAP_DEFAULT=y
-CONFIG_HANGCHECK_TIMER=m
-CONFIG_TCG_TPM=m
-CONFIG_HW_RANDOM_TPM=y
-CONFIG_TCG_TIS_CORE=m
-CONFIG_TCG_TIS=m
-CONFIG_TCG_TIS_SPI=m
-# CONFIG_TCG_TIS_SPI_CR50 is not set
-CONFIG_TCG_TIS_I2C_CR50=m
-CONFIG_TCG_TIS_I2C_ATMEL=m
-CONFIG_TCG_TIS_I2C_INFINEON=m
-CONFIG_TCG_TIS_I2C_NUVOTON=m
-CONFIG_TCG_NSC=m
-CONFIG_TCG_ATMEL=m
-CONFIG_TCG_INFINEON=m
-CONFIG_TCG_CRB=m
-CONFIG_TCG_VTPM_PROXY=m
-CONFIG_TCG_TIS_ST33ZP24=m
-CONFIG_TCG_TIS_ST33ZP24_I2C=m
-CONFIG_TCG_TIS_ST33ZP24_SPI=m
-CONFIG_TELCLOCK=m
-CONFIG_XILLYBUS=m
-CONFIG_XILLYBUS_PCIE=m
-CONFIG_XILLYUSB=m
-# end of Character devices
-
-CONFIG_RANDOM_TRUST_CPU=y
-CONFIG_RANDOM_TRUST_BOOTLOADER=y
-
-#
-# I2C support
-#
-CONFIG_I2C=m
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_MUX=m
-
-#
-# Multiplexer I2C Chip support
-#
-CONFIG_I2C_MUX_GPIO=m
-CONFIG_I2C_MUX_LTC4306=m
-CONFIG_I2C_MUX_PCA9541=m
-CONFIG_I2C_MUX_PCA954x=m
-CONFIG_I2C_MUX_REG=m
-CONFIG_I2C_MUX_MLXCPLD=m
-# end of Multiplexer I2C Chip support
-
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_SMBUS=m
-CONFIG_I2C_ALGOBIT=m
-CONFIG_I2C_ALGOPCA=m
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# PC SMBus host controller drivers
-#
-CONFIG_I2C_ALI1535=m
-CONFIG_I2C_ALI1563=m
-CONFIG_I2C_ALI15X3=m
-CONFIG_I2C_AMD756=m
-CONFIG_I2C_AMD756_S4882=m
-CONFIG_I2C_AMD8111=m
-CONFIG_I2C_AMD_MP2=m
-CONFIG_I2C_I801=m
-CONFIG_I2C_ISCH=m
-CONFIG_I2C_ISMT=m
-CONFIG_I2C_PIIX4=m
-CONFIG_I2C_NFORCE2=m
-CONFIG_I2C_NFORCE2_S4985=m
-CONFIG_I2C_NVIDIA_GPU=m
-CONFIG_I2C_SIS5595=m
-CONFIG_I2C_SIS630=m
-CONFIG_I2C_SIS96X=m
-CONFIG_I2C_VIA=m
-CONFIG_I2C_VIAPRO=m
-
-#
-# ACPI drivers
-#
-CONFIG_I2C_SCMI=m
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-CONFIG_I2C_CBUS_GPIO=m
-CONFIG_I2C_DESIGNWARE_CORE=m
-# CONFIG_I2C_DESIGNWARE_SLAVE is not set
-CONFIG_I2C_DESIGNWARE_PLATFORM=m
-CONFIG_I2C_DESIGNWARE_AMDPSP=y
-# CONFIG_I2C_DESIGNWARE_BAYTRAIL is not set
-CONFIG_I2C_DESIGNWARE_PCI=m
-# CONFIG_I2C_EG20T is not set
-CONFIG_I2C_EMEV2=m
-CONFIG_I2C_GPIO=m
-CONFIG_I2C_HISI=m
-# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
-CONFIG_I2C_KEMPLD=m
-CONFIG_I2C_OCORES=m
-CONFIG_I2C_PCA_PLATFORM=m
-CONFIG_I2C_SIMTEC=m
-CONFIG_I2C_XILINX=m
-
-#
-# External I2C/SMBus adapter drivers
-#
-CONFIG_I2C_DIOLAN_U2C=m
-CONFIG_I2C_CP2615=m
-CONFIG_I2C_DLN2=m
-CONFIG_I2C_PARPORT=m
-CONFIG_I2C_PCI1XXXX=m
-CONFIG_I2C_ROBOTFUZZ_OSIF=m
-CONFIG_I2C_TAOS_EVM=m
-CONFIG_I2C_TINY_USB=m
-CONFIG_I2C_VIPERBOARD=m
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_ISA is not set
-CONFIG_I2C_CROS_EC_TUNNEL=m
-# CONFIG_SCx200_ACB is not set
-# end of I2C Hardware Bus support
-
-# CONFIG_I2C_STUB is not set
-CONFIG_I2C_SLAVE=y
-CONFIG_I2C_SLAVE_EEPROM=m
-CONFIG_I2C_SLAVE_TESTUNIT=m
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# end of I2C support
-
-CONFIG_I3C=m
-CONFIG_CDNS_I3C_MASTER=m
-CONFIG_DW_I3C_MASTER=m
-CONFIG_SVC_I3C_MASTER=m
-CONFIG_MIPI_I3C_HCI=m
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-
-#
-# SPI Master Controller Drivers
-#
-CONFIG_SPI_ALTERA=m
-CONFIG_SPI_ALTERA_CORE=m
-CONFIG_SPI_ALTERA_DFL=m
-CONFIG_SPI_AXI_SPI_ENGINE=m
-CONFIG_SPI_BITBANG=m
-CONFIG_SPI_BUTTERFLY=m
-CONFIG_SPI_CADENCE=m
-CONFIG_SPI_DESIGNWARE=m
-# CONFIG_SPI_DW_DMA is not set
-CONFIG_SPI_DW_PCI=m
-CONFIG_SPI_DW_MMIO=m
-CONFIG_SPI_DLN2=m
-CONFIG_SPI_NXP_FLEXSPI=m
-CONFIG_SPI_GPIO=m
-CONFIG_SPI_INTEL_PCI=m
-CONFIG_SPI_INTEL_PLATFORM=m
-CONFIG_SPI_LM70_LLP=m
-CONFIG_SPI_LANTIQ_SSC=m
-CONFIG_SPI_OC_TINY=m
-CONFIG_SPI_PXA2XX=m
-CONFIG_SPI_PXA2XX_PCI=m
-# CONFIG_SPI_ROCKCHIP is not set
-CONFIG_SPI_SC18IS602=m
-CONFIG_SPI_SIFIVE=m
-CONFIG_SPI_MXIC=m
-CONFIG_SPI_TEGRA210_QUAD=m
-# CONFIG_SPI_TOPCLIFF_PCH is not set
-CONFIG_SPI_XCOMM=m
-CONFIG_SPI_XILINX=m
-CONFIG_SPI_ZYNQMP_GQSPI=m
-CONFIG_SPI_AMD=m
-
-#
-# SPI Multiplexer support
-#
-CONFIG_SPI_MUX=m
-
-#
-# SPI Protocol Masters
-#
-CONFIG_SPI_SPIDEV=m
-CONFIG_SPI_LOOPBACK_TEST=m
-CONFIG_SPI_TLE62X0=m
-CONFIG_SPI_SLAVE=y
-CONFIG_SPI_SLAVE_TIME=m
-CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPMI=m
-CONFIG_HSI=m
-CONFIG_HSI_BOARDINFO=y
-
-#
-# HSI controllers
-#
-
-#
-# HSI clients
-#
-CONFIG_HSI_CHAR=m
-CONFIG_PPS=y
-# CONFIG_PPS_DEBUG is not set
-
-#
-# PPS clients support
-#
-# CONFIG_PPS_CLIENT_KTIMER is not set
-CONFIG_PPS_CLIENT_LDISC=m
-CONFIG_PPS_CLIENT_PARPORT=m
-CONFIG_PPS_CLIENT_GPIO=m
-
-#
-# PPS generators support
-#
-
-#
-# PTP clock support
-#
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_DP83640_PHY=m
-CONFIG_PTP_1588_CLOCK_INES=m
-CONFIG_PTP_1588_CLOCK_KVM=m
-# CONFIG_PTP_1588_CLOCK_PCH is not set
-CONFIG_PTP_1588_CLOCK_KVM=m
-CONFIG_PTP_1588_CLOCK_IDT82P33=m
-CONFIG_PTP_1588_CLOCK_IDTCM=m
-CONFIG_PTP_1588_CLOCK_OCP=m
-CONFIG_PTP_1588_CLOCK_VMW=m
-# end of PTP clock support
-
-CONFIG_PINCTRL=y
-CONFIG_PINMUX=y
-CONFIG_PINCONF=y
-CONFIG_GENERIC_PINCONF=y
-# CONFIG_DEBUG_PINCTRL is not set
-CONFIG_PINCTRL_AMD=m
-CONFIG_PINCTRL_CY8C95X0=m
-CONFIG_PINCTRL_DA9062=m
-CONFIG_PINCTRL_MCP23S08_I2C=m
-CONFIG_PINCTRL_MCP23S08_SPI=m
-CONFIG_PINCTRL_MCP23S08=m
-CONFIG_PINCTRL_BAYTRAIL=y
-CONFIG_PINCTRL_CHERRYVIEW=m
-CONFIG_PINCTRL_LYNXPOINT=m
-CONFIG_PINCTRL_ALDERLAKE=m
-CONFIG_PINCTRL_INTEL=y
-CONFIG_PINCTRL_BROXTON=m
-CONFIG_PINCTRL_CANNONLAKE=m
-CONFIG_PINCTRL_CEDARFORK=m
-CONFIG_PINCTRL_DENVERTON=m
-CONFIG_PINCTRL_ELKHARTLAKE=m
-CONFIG_PINCTRL_EMMITSBURG=m
-CONFIG_PINCTRL_GEMINILAKE=m
-CONFIG_PINCTRL_ICELAKE=m
-CONFIG_PINCTRL_JASPERLAKE=m
-CONFIG_PINCTRL_LAKEFIELD=m
-CONFIG_PINCTRL_LEWISBURG=m
-CONFIG_PINCTRL_METEORLAKE=m
-CONFIG_PINCTRL_SUNRISEPOINT=m
-CONFIG_PINCTRL_TIGERLAKE=m
-
-#
-# Renesas pinctrl drivers
-#
-# end of Renesas pinctrl drivers
-
-CONFIG_PINCTRL_MADERA=m
-CONFIG_PINCTRL_CS47L15=y
-CONFIG_PINCTRL_CS47L35=y
-CONFIG_PINCTRL_CS47L85=y
-CONFIG_PINCTRL_CS47L90=y
-CONFIG_PINCTRL_CS47L92=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_FASTPATH_LIMIT=512
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIOLIB_IRQCHIP=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_CDEV=y
-# CONFIG_GPIO_CDEV_V1 is not set
-CONFIG_GPIO_GENERIC=m
-CONFIG_GPIO_REGMAP=m
-CONFIG_GPIO_MAX730X=m
-
-#
-# Memory mapped GPIO drivers
-#
-CONFIG_GPIO_AMDPT=m
-CONFIG_GPIO_DWAPB=m
-CONFIG_GPIO_EXAR=m
-CONFIG_GPIO_GENERIC_PLATFORM=m
-CONFIG_GPIO_ICH=m
-CONFIG_GPIO_MB86S7X=m
-CONFIG_GPIO_MENZ127=m
-CONFIG_GPIO_SIOX=m
-CONFIG_GPIO_VX855=m
-CONFIG_GPIO_XILINX=m
-CONFIG_GPIO_AMD_FCH=m
-CONFIG_GPIO_MSC313=y
-# end of Memory mapped GPIO drivers
-
-#
-# Port-mapped I/O GPIO drivers
-#
-CONFIG_GPIO_F7188X=m
-CONFIG_GPIO_IT87=m
-CONFIG_GPIO_SCH=m
-CONFIG_GPIO_SCH311X=m
-CONFIG_GPIO_WINBOND=m
-CONFIG_GPIO_WS16C48=m
-# end of Port-mapped I/O GPIO drivers
-
-#
-# I2C GPIO expanders
-#
-CONFIG_GPIO_ADP5588=m
-CONFIG_GPIO_MAX7300=m
-CONFIG_GPIO_MAX732X=m
-CONFIG_GPIO_PCA953X=m
-# CONFIG_GPIO_PCA953X_IRQ is not set
-CONFIG_GPIO_PCA9570=m
-CONFIG_GPIO_PCF857X=m
-CONFIG_GPIO_TPIC2810=m
-# end of I2C GPIO expanders
-
-#
-# MFD GPIO expanders
-#
-CONFIG_GPIO_ARIZONA=m
-CONFIG_GPIO_BD9571MWV=m
-CONFIG_GPIO_DA9052=m
-CONFIG_GPIO_DLN2=m
-CONFIG_GPIO_JANZ_TTL=m
-CONFIG_GPIO_KEMPLD=m
-CONFIG_GPIO_LP3943=m
-CONFIG_GPIO_LP873X=m
-CONFIG_GPIO_MADERA=m
-CONFIG_GPIO_SL28CPLD=m
-CONFIG_GPIO_TPS65086=m
-CONFIG_GPIO_TPS65912=m
-CONFIG_GPIO_TPS68470=y
-CONFIG_GPIO_TQMX86=m
-CONFIG_GPIO_UCB1400=m
-CONFIG_GPIO_WHISKEY_COVE=m
-CONFIG_GPIO_WM831X=m
-CONFIG_GPIO_WM8994=m
-# end of MFD GPIO expanders
-
-#
-# PCI GPIO expanders
-#
-CONFIG_GPIO_AMD8111=m
-CONFIG_GPIO_ML_IOH=m
-# CONFIG_GPIO_PCH is not set
-CONFIG_GPIO_PCI_IDIO_16=m
-CONFIG_GPIO_PCIE_IDIO_24=m
-CONFIG_GPIO_RDC321X=m
-# end of PCI GPIO expanders
-
-#
-# SPI GPIO expanders
-#
-CONFIG_GPIO_MAX3191X=m
-CONFIG_GPIO_MAX7301=m
-CONFIG_GPIO_MC33880=m
-CONFIG_GPIO_PISOSR=m
-CONFIG_GPIO_XRA1403=m
-# end of SPI GPIO expanders
-
-#
-# USB GPIO expanders
-#
-CONFIG_GPIO_VIPERBOARD=m
-# end of USB GPIO expanders
-
-CONFIG_GPIO_AGGREGATOR=m
-CONFIG_GPIO_MOCKUP=m
-CONFIG_W1=m
-CONFIG_W1_CON=y
-
-#
-# 1-wire Bus Masters
-#
-CONFIG_W1_MASTER_MATROX=m
-CONFIG_W1_MASTER_DS2490=m
-CONFIG_W1_MASTER_DS2482=m
-CONFIG_W1_MASTER_DS1WM=m
-CONFIG_W1_MASTER_GPIO=m
-CONFIG_W1_MASTER_SGI=m
-# end of 1-wire Bus Masters
-
-#
-# 1-wire Slaves
-#
-CONFIG_W1_SLAVE_THERM=m
-CONFIG_W1_SLAVE_SMEM=m
-# CONFIG_W1_SLAVE_DS2405 is not set
-CONFIG_W1_SLAVE_DS2408=m
-# CONFIG_W1_SLAVE_DS2408_READBACK is not set
-CONFIG_W1_SLAVE_DS2413=m
-CONFIG_W1_SLAVE_DS2406=m
-CONFIG_W1_SLAVE_DS2423=m
-CONFIG_W1_SLAVE_DS2805=m
-CONFIG_W1_SLAVE_DS2430=m
-CONFIG_W1_SLAVE_DS2431=m
-CONFIG_W1_SLAVE_DS2433=m
-CONFIG_W1_SLAVE_DS2433_CRC=y
-CONFIG_W1_SLAVE_DS2438=m
-CONFIG_W1_SLAVE_DS250X=m
-CONFIG_W1_SLAVE_DS2780=m
-CONFIG_W1_SLAVE_DS2781=m
-CONFIG_W1_SLAVE_DS28E04=m
-CONFIG_W1_SLAVE_DS28E17=m
-# end of 1-wire Slaves
-
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_MT6323=y
-CONFIG_POWER_RESET_ATC260X=m
-# CONFIG_POWER_RESET_RESTART is not set
-CONFIG_POWER_RESET_REGULATOR=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PDA_POWER=m
-CONFIG_GENERIC_ADC_BATTERY=m
-CONFIG_IP5XXX_POWER=m
-CONFIG_WM831X_BACKUP=m
-CONFIG_WM831X_POWER=m
-# CONFIG_TEST_POWER is not set
-CONFIG_CHARGER_ADP5061=m
-CONFIG_BATTERY_CW2015=m
-CONFIG_BATTERY_DS2760=m
-CONFIG_BATTERY_DS2780=m
-CONFIG_BATTERY_DS2781=m
-CONFIG_BATTERY_DS2782=m
-# CONFIG_BATTERY_SAMSUNG_SDI is not set
-CONFIG_BATTERY_SBS=m
-CONFIG_CHARGER_SBS=m
-CONFIG_MANAGER_SBS=m
-CONFIG_BATTERY_BQ27XXX=m
-CONFIG_BATTERY_BQ27XXX_I2C=m
-CONFIG_BATTERY_BQ27XXX_HDQ=m
-# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set
-CONFIG_BATTERY_DA9052=m
-CONFIG_CHARGER_DA9150=m
-CONFIG_BATTERY_DA9150=m
-CONFIG_CHARGER_AXP20X=m
-CONFIG_BATTERY_AXP20X=m
-CONFIG_AXP20X_POWER=m
-CONFIG_AXP288_CHARGER=m
-CONFIG_AXP288_FUEL_GAUGE=m
-CONFIG_BATTERY_MAX17040=m
-CONFIG_BATTERY_MAX17042=m
-CONFIG_BATTERY_MAX1721X=m
-CONFIG_CHARGER_PCF50633=m
-CONFIG_CHARGER_ISP1704=m
-CONFIG_CHARGER_MAX8903=m
-CONFIG_CHARGER_LP8727=m
-CONFIG_CHARGER_GPIO=m
-CONFIG_CHARGER_MANAGER=y
-CONFIG_CHARGER_LT3651=m
-CONFIG_CHARGER_LTC4162L=m
-CONFIG_CHARGER_MAX14577=m
-CONFIG_CHARGER_MAX77693=m
-CONFIG_CHARGER_MP2629=m
-CONFIG_CHARGER_BQ2415X=m
-CONFIG_CHARGER_BQ24190=m
-CONFIG_CHARGER_BQ24257=m
-CONFIG_CHARGER_BQ24735=m
-CONFIG_CHARGER_BQ2515X=m
-CONFIG_CHARGER_BQ25890=m
-CONFIG_CHARGER_BQ25980=m
-CONFIG_CHARGER_BQ256XX=m
-CONFIG_CHARGER_RK817=m
-CONFIG_CHARGER_SMB347=m
-CONFIG_BATTERY_GAUGE_LTC2941=m
-CONFIG_BATTERY_GOLDFISH=m
-CONFIG_BATTERY_RT5033=m
-CONFIG_CHARGER_RT9455=m
-CONFIG_CHARGER_CROS_USBPD=m
-CONFIG_CHARGER_BD99954=m
-CONFIG_BATTERY_UG3105=m
-CONFIG_CHARGER_SURFACE=m
-CONFIG_SURFACE_HID=m
-CONFIG_BATTERY_SURFACE=m
-CONFIG_CHARGER_WILCO=m
-CONFIG_HWMON=y
-CONFIG_HWMON_VID=m
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Native drivers
-#
-CONFIG_SENSORS_ABITUGURU=m
-CONFIG_SENSORS_ABITUGURU3=m
-CONFIG_SENSORS_AD7314=m
-CONFIG_SENSORS_AD7414=m
-CONFIG_SENSORS_AD7418=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1026=m
-CONFIG_SENSORS_ADM1029=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_ADM1177=m
-CONFIG_SENSORS_ADM9240=m
-CONFIG_SENSORS_ADT7X10=m
-CONFIG_SENSORS_ADT7310=m
-CONFIG_SENSORS_ADT7410=m
-CONFIG_SENSORS_ADT7411=m
-CONFIG_SENSORS_ADT7462=m
-CONFIG_SENSORS_ADT7470=m
-CONFIG_SENSORS_ADT7475=m
-CONFIG_SENSORS_AHT10=m
-CONFIG_SENSORS_AS370=m
-CONFIG_SENSORS_ASC7621=m
-CONFIG_SENSORS_AXI_FAN_CONTROL=m
-CONFIG_SENSORS_K8TEMP=m
-CONFIG_SENSORS_K10TEMP=m
-CONFIG_SENSORS_FAM15H_POWER=m
-CONFIG_SENSORS_AMD_ENERGY=m
-CONFIG_SENSORS_APPLESMC=m
-CONFIG_SENSORS_ASB100=m
-CONFIG_SENSORS_ASPEED=m
-CONFIG_SENSORS_ATXP1=m
-CONFIG_SENSORS_CORSAIR_CPRO=m
-CONFIG_SENSORS_CORSAIR_PSU=m
-CONFIG_SENSORS_DRIVETEMP=m
-CONFIG_SENSORS_DS620=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_DELL_SMM=m
-# CONFIG_I8K is not set
-CONFIG_SENSORS_DA9052_ADC=m
-CONFIG_SENSORS_I5K_AMB=m
-CONFIG_SENSORS_F71805F=m
-CONFIG_SENSORS_F71882FG=m
-CONFIG_SENSORS_F75375S=m
-CONFIG_SENSORS_MC13783_ADC=m
-CONFIG_SENSORS_FSCHMD=m
-CONFIG_SENSORS_FTSTEUTATES=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_GL520SM=m
-CONFIG_SENSORS_G760A=m
-CONFIG_SENSORS_G762=m
-CONFIG_SENSORS_HIH6130=m
-CONFIG_SENSORS_IBMAEM=m
-CONFIG_SENSORS_IBMPEX=m
-CONFIG_SENSORS_IIO_HWMON=m
-CONFIG_SENSORS_I5500=m
-CONFIG_SENSORS_CORETEMP=m
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_JC42=m
-CONFIG_SENSORS_POWR1220=m
-CONFIG_SENSORS_LINEAGE=m
-CONFIG_SENSORS_LTC2945=m
-CONFIG_SENSORS_LTC2947=m
-CONFIG_SENSORS_LTC2947_I2C=m
-CONFIG_SENSORS_LTC2947_SPI=m
-CONFIG_SENSORS_LTC2990=m
-CONFIG_SENSORS_LTC2992=m
-CONFIG_SENSORS_LTC4151=m
-CONFIG_SENSORS_LTC4215=m
-CONFIG_SENSORS_LTC4222=m
-CONFIG_SENSORS_LTC4245=m
-CONFIG_SENSORS_LTC4260=m
-CONFIG_SENSORS_LTC4261=m
-CONFIG_SENSORS_MAX1111=m
-CONFIG_SENSORS_MAX127=m
-CONFIG_SENSORS_MAX16065=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_MAX1668=m
-CONFIG_SENSORS_MAX197=m
-CONFIG_SENSORS_MAX31722=m
-CONFIG_SENSORS_MAX31730=m
-CONFIG_SENSORS_MAX31760=m
-CONFIG_SENSORS_MAX6621=m
-CONFIG_SENSORS_MAX6639=m
-CONFIG_SENSORS_MAX6642=m
-CONFIG_SENSORS_MAX6650=m
-CONFIG_SENSORS_MAX6697=m
-CONFIG_SENSORS_MAX31790=m
-CONFIG_SENSORS_PM6764TR=m
-CONFIG_SENSORS_Q54SJ108A2=m
-CONFIG_SENSORS_STPDDC60=m
-CONFIG_SENSORS_MCP3021=m
-CONFIG_SENSORS_MLXREG_FAN=m
-CONFIG_SENSORS_TC654=m
-CONFIG_SENSORS_TPS23861=m
-CONFIG_SENSORS_MENF21BMC_HWMON=m
-CONFIG_SENSORS_MR75203=m
-CONFIG_SENSORS_ADCXX=m
-CONFIG_SENSORS_LM63=m
-CONFIG_SENSORS_LM70=m
-CONFIG_SENSORS_LM73=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM87=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_LM92=m
-CONFIG_SENSORS_LM93=m
-CONFIG_SENSORS_LM95234=m
-CONFIG_SENSORS_LM95241=m
-CONFIG_SENSORS_LM95245=m
-CONFIG_SENSORS_PC87360=m
-CONFIG_SENSORS_PC87427=m
-CONFIG_SENSORS_NTC_THERMISTOR=m
-CONFIG_SENSORS_NCT6683=m
-CONFIG_SENSORS_NCT6775=m
-CONFIG_SENSORS_NCT7802=m
-CONFIG_SENSORS_NCT7904=m
-CONFIG_SENSORS_NPCM7XX=m
-CONFIG_SENSORS_NZXT_KRAKEN2=m
-CONFIG_SENSORS_BPA_RS600=m
-CONFIG_SENSORS_FSP_3Y=m
-CONFIG_SENSORS_PCF8591=m
-CONFIG_PMBUS=m
-CONFIG_SENSORS_PMBUS=m
-CONFIG_SENSORS_ADM1266=m
-CONFIG_SENSORS_ADM1275=m
-CONFIG_SENSORS_BEL_PFE=m
-CONFIG_SENSORS_IBM_CFFPS=m
-CONFIG_SENSORS_DPS920AB=m
-CONFIG_SENSORS_INSPUR_IPSPS=m
-CONFIG_SENSORS_IR35221=m
-CONFIG_SENSORS_IR36021=m
-CONFIG_SENSORS_IR38064=m
-CONFIG_SENSORS_IRPS5401=m
-CONFIG_SENSORS_ISL68137=m
-CONFIG_SENSORS_LM25066=m
-CONFIG_SENSORS_LM25066_REGULATOR=y
-CONFIG_SENSORS_LTC2978=m
-CONFIG_SENSORS_LTC2978_REGULATOR=y
-CONFIG_SENSORS_LTC3815=m
-CONFIG_SENSORS_MAX15301=m
-CONFIG_SENSORS_MAX16064=m
-CONFIG_SENSORS_MAX16601=m
-CONFIG_SENSORS_MAX20730=m
-CONFIG_SENSORS_MAX20751=m
-CONFIG_SENSORS_MAX31785=m
-CONFIG_SENSORS_MAX34440=m
-CONFIG_SENSORS_MAX8688=m
-CONFIG_SENSORS_MP2888=m
-CONFIG_SENSORS_MP2975=m
-CONFIG_SENSORS_PIM4328=m
-CONFIG_SENSORS_PLI1209BC=m
-CONFIG_SENSORS_PLI1209BC_REGULATOR=y
-CONFIG_SENSORS_PXE1610=m
-CONFIG_SENSORS_TPS40422=m
-CONFIG_SENSORS_TPS53679=m
-CONFIG_SENSORS_TPS546D24=m
-CONFIG_SENSORS_UCD9000=m
-CONFIG_SENSORS_UCD9200=m
-CONFIG_SENSORS_XDPE122=m
-CONFIG_SENSORS_XDPE122_REGULATOR=y
-CONFIG_SENSORS_ZL6100=m
-CONFIG_SENSORS_SL28CPLD=m
-CONFIG_SENSORS_SBTSI=m
-CONFIG_AMD_SFH_HID=m
-CONFIG_SENSORS_SHT15=m
-CONFIG_SENSORS_SHT21=m
-CONFIG_SENSORS_SHT3x=m
-CONFIG_SENSORS_SHT4x=m
-CONFIG_SENSORS_SHTC1=m
-CONFIG_SENSORS_SIS5595=m
-CONFIG_SENSORS_SY7636A=m
-CONFIG_SENSORS_DME1737=m
-CONFIG_SENSORS_EMC1403=m
-CONFIG_SENSORS_EMC2103=m
-CONFIG_SENSORS_EMC2305=m
-CONFIG_SENSORS_EMC6W201=m
-CONFIG_SENSORS_SMSC47M1=m
-CONFIG_SENSORS_SMSC47M192=m
-CONFIG_SENSORS_SMSC47B397=m
-CONFIG_SENSORS_SCH56XX_COMMON=m
-CONFIG_SENSORS_SCH5627=m
-CONFIG_SENSORS_SCH5636=m
-CONFIG_SENSORS_STTS751=m
-CONFIG_SENSORS_SMM665=m
-CONFIG_SENSORS_ADC128D818=m
-CONFIG_SENSORS_ADS7828=m
-CONFIG_SENSORS_ADS7871=m
-CONFIG_SENSORS_AMC6821=m
-CONFIG_SENSORS_INA209=m
-CONFIG_SENSORS_INA2XX=m
-CONFIG_SENSORS_INA3221=m
-CONFIG_SENSORS_TC74=m
-CONFIG_SENSORS_THMC50=m
-CONFIG_SENSORS_TMP102=m
-CONFIG_SENSORS_TMP103=m
-CONFIG_SENSORS_TMP108=m
-CONFIG_SENSORS_TMP401=m
-CONFIG_SENSORS_TMP421=m
-CONFIG_SENSORS_TMP464=m
-CONFIG_SENSORS_TMP513=m
-CONFIG_SENSORS_VIA_CPUTEMP=m
-CONFIG_SENSORS_VIA686A=m
-CONFIG_SENSORS_VT1211=m
-CONFIG_SENSORS_VT8231=m
-CONFIG_SENSORS_W83773G=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83791D=m
-CONFIG_SENSORS_W83792D=m
-CONFIG_SENSORS_W83793=m
-CONFIG_SENSORS_W83795=m
-CONFIG_SENSORS_W83795_FANCTRL=y
-CONFIG_SENSORS_W83L785TS=m
-CONFIG_SENSORS_W83L786NG=m
-CONFIG_SENSORS_W83627HF=m
-CONFIG_SENSORS_W83627EHF=m
-CONFIG_SENSORS_WM831X=m
-CONFIG_SENSORS_XGENE=m
-CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m
-CONFIG_QCOM_SPMI_ADC_TM5=m
-
-#
-# ACPI drivers
-#
-CONFIG_SENSORS_ACPI_POWER=m
-CONFIG_SENSORS_ATK0110=m
-CONFIG_SENSORS_ASUS_WMI_EC=m
-CONFIG_SENSORS_ASUS_EC=m
-CONFIG_SENSORS_ASUS_WMI=m
-CONFIG_THERMAL=y
-CONFIG_THERMAL_NETLINK=y
-CONFIG_THERMAL_STATISTICS=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=100
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
-CONFIG_DEVFREQ_THERMAL=y
-# CONFIG_THERMAL_EMULATION is not set
-
-#
-# Intel thermal drivers
-#
-CONFIG_INTEL_POWERCLAMP=m
-CONFIG_X86_PKG_TEMP_THERMAL=m
-CONFIG_INTEL_SOC_DTS_IOSF_CORE=m
-CONFIG_INTEL_SOC_DTS_THERMAL=m
-
-#
-# ACPI INT340X thermal drivers
-#
-CONFIG_INT340X_THERMAL=m
-CONFIG_ACPI_THERMAL_REL=m
-CONFIG_INT3406_THERMAL=m
-# end of ACPI INT340X thermal drivers
-
-CONFIG_INTEL_BXT_PMIC_THERMAL=m
-CONFIG_INTEL_PCH_THERMAL=m
-CONFIG_INTEL_TCC_COOLING=m
-# end of Intel thermal drivers
-
-CONFIG_GENERIC_ADC_THERMAL=m
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_CORE=m
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
-CONFIG_WATCHDOG_OPEN_TIMEOUT=0
-# CONFIG_WATCHDOG_SYSFS is not set
-# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
-
-#
-# Watchdog Pretimeout Governors
-#
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-
-#
-# Watchdog Device Drivers
-#
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_BD957XMUF_WATCHDOG=m
-# CONFIG_SOFT_WATCHDOG_PRETIMEOUT is not set
-CONFIG_DA9052_WATCHDOG=m
-CONFIG_DA9063_WATCHDOG=m
-CONFIG_DA9062_WATCHDOG=m
-CONFIG_MENF21BMC_WATCHDOG=m
-CONFIG_MENZ069_WATCHDOG=m
-CONFIG_WDAT_WDT=m
-CONFIG_WM831X_WATCHDOG=m
-CONFIG_XILINX_WATCHDOG=m
-CONFIG_ZIIRAVE_WATCHDOG=m
-CONFIG_RAVE_SP_WATCHDOG=m
-CONFIG_MLX_WDT=m
-CONFIG_SL28CPLD_WATCHDOG=m
-CONFIG_CADENCE_WATCHDOG=m
-CONFIG_DW_WATCHDOG=m
-CONFIG_MAX63XX_WATCHDOG=m
-CONFIG_MAX77620_WATCHDOG=m
-CONFIG_RETU_WATCHDOG=m
-CONFIG_ACQUIRE_WDT=m
-CONFIG_ADVANTECH_WDT=m
-CONFIG_ALIM1535_WDT=m
-CONFIG_ALIM7101_WDT=m
-CONFIG_EBC_C384_WDT=m
-CONFIG_EXAR_WDT=m
-CONFIG_F71808E_WDT=m
-# CONFIG_SP5100_TCO is not set
-CONFIG_SBC_FITPC2_WATCHDOG=m
-CONFIG_EUROTECH_WDT=m
-CONFIG_IB700_WDT=m
-CONFIG_IBMASR=m
-CONFIG_WAFER_WDT=m
-CONFIG_I6300ESB_WDT=m
-CONFIG_HP_WATCHDOG=m
-CONFIG_IE6XX_WDT=m
-CONFIG_ITCO_WDT=m
-CONFIG_ITCO_VENDOR_SUPPORT=y
-CONFIG_IT8712F_WDT=m
-CONFIG_IT87_WDT=m
-CONFIG_HP_WATCHDOG=m
-CONFIG_HPWDT_NMI_DECODING=y
-CONFIG_KEMPLD_WDT=m
-CONFIG_BCM7038_WDT=m
-CONFIG_SC1200_WDT=m
-CONFIG_PC87413_WDT=m
-CONFIG_NV_TCO=m
-CONFIG_60XX_WDT=m
-# CONFIG_SBC8360_WDT is not set
-# CONFIG_SBC7240_WDT is not set
-CONFIG_CPU5_WDT=m
-CONFIG_SMSC_SCH311X_WDT=m
-CONFIG_SMSC37B787_WDT=m
-CONFIG_TQMX86_WDT=m
-CONFIG_VIA_WDT=m
-CONFIG_W83627HF_WDT=m
-CONFIG_W83877F_WDT=m
-CONFIG_W83977F_WDT=m
-CONFIG_MACHZ_WDT=m
-CONFIG_SBC_EPX_C3_WATCHDOG=m
-CONFIG_INTEL_MEI_WDT=m
-CONFIG_NI903X_WDT=m
-CONFIG_NIC7018_WDT=m
-CONFIG_SIEMENS_SIMATIC_IPC_WDT=m
-CONFIG_MEN_A21_WDT=m
-
-#
-# ISA-based Watchdog Cards
-#
-# CONFIG_PCWATCHDOG is not set
-# CONFIG_MIXCOMWD is not set
-# CONFIG_WDT is not set
-
-#
-# PCI-based Watchdog Cards
-#
-CONFIG_PCIPCWATCHDOG=m
-CONFIG_WDTPCI=m
-
-#
-# USB-based Watchdog Cards
-#
-CONFIG_USBPCWATCHDOG=m
-CONFIG_KEEMBAY_WATCHDOG=m
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SSB=m
-CONFIG_SSB_SPROM=y
-CONFIG_SSB_BLOCKIO=y
-CONFIG_SSB_PCIHOST_POSSIBLE=y
-CONFIG_SSB_PCIHOST=y
-CONFIG_SSB_B43_PCI_BRIDGE=y
-CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
-CONFIG_SSB_PCMCIAHOST=y
-CONFIG_SSB_SDIOHOST_POSSIBLE=y
-CONFIG_SSB_SDIOHOST=y
-CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
-CONFIG_SSB_DRIVER_PCICORE=y
-CONFIG_SSB_DRIVER_GPIO=y
-CONFIG_BCMA_POSSIBLE=y
-CONFIG_BCMA=m
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_SOC=y
-CONFIG_BCMA_DRIVER_PCI=y
-CONFIG_BCMA_SFLASH=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_DRIVER_GPIO=y
-# CONFIG_BCMA_DEBUG is not set
-
-#
-# Multifunction device drivers
-#
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_CS5535 is not set
-CONFIG_MFD_BCM590XX=m
-CONFIG_MFD_BD9571MWV=m
-CONFIG_MFD_AXP20X=m
-CONFIG_MFD_AXP20X_I2C=m
-CONFIG_MFD_CROS_EC_DEV=m
-CONFIG_MFD_MADERA=m
-CONFIG_MFD_MADERA_I2C=m
-CONFIG_MFD_MADERA_SPI=m
-CONFIG_MFD_CS47L15=y
-CONFIG_MFD_CS47L35=y
-CONFIG_MFD_CS47L85=y
-CONFIG_MFD_CS47L90=y
-CONFIG_MFD_CS47L92=y
-CONFIG_PMIC_DA9052=y
-CONFIG_MFD_DA9052_SPI=y
-CONFIG_MFD_DA9062=m
-CONFIG_MFD_DA9063=m
-CONFIG_MFD_DA9150=m
-CONFIG_MFD_DLN2=m
-CONFIG_MFD_MC13XXX=m
-CONFIG_MFD_MC13XXX_SPI=m
-CONFIG_MFD_MC13XXX_I2C=m
-CONFIG_MFD_MP2629=m
-CONFIG_HTC_PASIC3=m
-CONFIG_MFD_INTEL_QUARK_I2C_GPIO=m
-CONFIG_LPC_ICH=m
-CONFIG_LPC_SCH=m
-CONFIG_MFD_INTEL_PMT=m
-CONFIG_INTEL_SOC_PMIC_BXTWC=m
-CONFIG_INTEL_SOC_PMIC_CHTDC_TI=m
-CONFIG_INTEL_SOC_PMIC_MRFLD=m
-CONFIG_MFD_INTEL_LPSS=m
-CONFIG_MFD_INTEL_LPSS_ACPI=m
-CONFIG_MFD_INTEL_LPSS_PCI=m
-# CONFIG_MFD_INTEL_MSIC is not set
-CONFIG_MFD_INTEL_PMC_BXT=m
-CONFIG_MFD_IQS62X=m
-CONFIG_MFD_JANZ_CMODIO=m
-CONFIG_MFD_KEMPLD=m
-CONFIG_MFD_88PM800=m
-CONFIG_MFD_88PM805=m
-CONFIG_MFD_MAX14577=m
-CONFIG_MFD_MAX77693=m
-CONFIG_MFD_MAX77714=m
-CONFIG_MFD_MAX8907=m
-CONFIG_MFD_MT6360=m
-CONFIG_MFD_MT6370=m
-CONFIG_MFD_MT6397=m
-CONFIG_MFD_MENF21BMC=m
-CONFIG_MFD_OCELOT=m
-CONFIG_EZX_PCAP=y
-CONFIG_MFD_VIPERBOARD=m
-CONFIG_MFD_NTXEC=m
-CONFIG_MFD_ROHM_BD957XMUF=m
-CONFIG_MFD_RETU=m
-CONFIG_MFD_PCF50633=m
-CONFIG_PCF50633_ADC=m
-CONFIG_PCF50633_GPIO=m
-CONFIG_UCB1400_CORE=m
-CONFIG_MFD_SY7636A=m
-CONFIG_MFD_RDC321X=m
-CONFIG_MFD_RT4831=m
-CONFIG_MFD_RT5033=m
-CONFIG_MFD_RT5120=m
-CONFIG_MFD_SI476X_CORE=m
-CONFIG_MFD_SIMPLE_MFD_I2C=m
-CONFIG_MFD_SL28CPLD=m
-CONFIG_MFD_SM501=m
-CONFIG_MFD_SM501_GPIO=y
-CONFIG_MFD_SKY81452=m
-CONFIG_ABX500_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MFD_TI_AM335X_TSCADC=m
-CONFIG_MFD_LP3943=m
-CONFIG_MFD_TI_LMU=m
-CONFIG_TPS6105X=m
-CONFIG_TPS65010=m
-CONFIG_TPS6507X=m
-CONFIG_MFD_TPS65086=m
-CONFIG_MFD_TI_LP873X=m
-CONFIG_MFD_TPS65912=y
-CONFIG_MFD_TPS65912_I2C=m
-CONFIG_MFD_TPS65912_SPI=y
-CONFIG_MFD_WL1273_CORE=m
-CONFIG_MFD_LM3533=m
-# CONFIG_MFD_TIMBERDALE is not set
-CONFIG_MFD_TQMX86=m
-CONFIG_MFD_VX855=m
-CONFIG_MFD_ARIZONA=y
-CONFIG_MFD_ARIZONA_I2C=m
-CONFIG_MFD_ARIZONA_SPI=m
-CONFIG_MFD_CS47L24=y
-CONFIG_MFD_WM5102=y
-CONFIG_MFD_WM5110=y
-CONFIG_MFD_WM8997=y
-CONFIG_MFD_WM8998=y
-CONFIG_MFD_WM831X=y
-CONFIG_MFD_WM831X_SPI=y
-CONFIG_MFD_WM8994=m
-CONFIG_MFD_WCD934X=m
-CONFIG_MFD_ATC260X_I2C=m
-CONFIG_RAVE_SP_CORE=m
-CONFIG_MFD_INTEL_M10_BMC=m
-# end of Multifunction device drivers
-
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=m
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
-CONFIG_REGULATOR_USERSPACE_CONSUMER=m
-CONFIG_REGULATOR_88PG86X=m
-CONFIG_REGULATOR_88PM800=m
-CONFIG_REGULATOR_ACT8865=m
-CONFIG_REGULATOR_AD5398=m
-CONFIG_REGULATOR_ARIZONA_LDO1=m
-CONFIG_REGULATOR_ATC260X=m
-CONFIG_REGULATOR_ARIZONA_MICSUPP=m
-CONFIG_REGULATOR_AXP20X=m
-CONFIG_REGULATOR_BCM590XX=m
-CONFIG_REGULATOR_BD9571MWV=m
-CONFIG_REGULATOR_BD957XMUF=m
-CONFIG_REGULATOR_DA9052=m
-CONFIG_REGULATOR_DA9062=m
-CONFIG_REGULATOR_DA9210=m
-CONFIG_REGULATOR_DA9211=m
-CONFIG_REGULATOR_DA9121=m
-CONFIG_REGULATOR_FAN53555=m
-CONFIG_REGULATOR_GPIO=m
-CONFIG_REGULATOR_ISL9305=m
-CONFIG_REGULATOR_ISL6271A=m
-CONFIG_REGULATOR_LM363X=m
-CONFIG_REGULATOR_LP3971=m
-CONFIG_REGULATOR_LP3972=m
-CONFIG_REGULATOR_LP872X=m
-CONFIG_REGULATOR_LP8755=m
-CONFIG_REGULATOR_LTC3589=m
-CONFIG_REGULATOR_LTC3676=m
-CONFIG_REGULATOR_MAX14577=m
-CONFIG_REGULATOR_MAX1586=m
-CONFIG_REGULATOR_MAX8649=m
-CONFIG_REGULATOR_MAX8660=m
-CONFIG_REGULATOR_MAX8893=m
-CONFIG_REGULATOR_MAX8907=m
-CONFIG_REGULATOR_MAX8952=m
-CONFIG_REGULATOR_MAX77693=m
-CONFIG_REGULATOR_MAX77826=m
-CONFIG_REGULATOR_MC13XXX_CORE=m
-CONFIG_REGULATOR_MC13783=m
-CONFIG_REGULATOR_MC13892=m
-CONFIG_REGULATOR_MP8859=m
-CONFIG_REGULATOR_MT6311=m
-CONFIG_REGULATOR_MT6315=m
-CONFIG_REGULATOR_MT6370=m
-CONFIG_REGULATOR_MT6323=m
-CONFIG_REGULATOR_MT6331=m
-CONFIG_REGULATOR_MT6332=m
-CONFIG_REGULATOR_MT6358=m
-CONFIG_REGULATOR_MT6359=m
-CONFIG_REGULATOR_MT6360=m
-CONFIG_REGULATOR_MT6370=m
-CONFIG_REGULATOR_MT6397=m
-CONFIG_REGULATOR_PCA9450=m
-CONFIG_REGULATOR_PF8X00=m
-CONFIG_REGULATOR_PCAP=m
-CONFIG_REGULATOR_PCF50633=m
-CONFIG_REGULATOR_PFUZE100=m
-CONFIG_REGULATOR_PV88060=m
-CONFIG_REGULATOR_PV88080=m
-CONFIG_REGULATOR_PV88090=m
-CONFIG_REGULATOR_PWM=m
-CONFIG_REGULATOR_QCOM_SPMI=m
-CONFIG_REGULATOR_QCOM_USB_VBUS=m
-CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
-CONFIG_REGULATOR_RT4801=m
-CONFIG_REGULATOR_RT4831=m
-CONFIG_REGULATOR_RT5120=m
-CONFIG_REGULATOR_RT5190A=m
-CONFIG_REGULATOR_RT6160=m
-CONFIG_REGULATOR_RT6245=m
-CONFIG_REGULATOR_RT5033=m
-CONFIG_REGULATOR_RT5120=m
-CONFIG_REGULATOR_RT5190A=m
-CONFIG_REGULATOR_SY7636A=m
-CONFIG_REGULATOR_RT6245=m
-CONFIG_REGULATOR_RT6160=m
-CONFIG_REGULATOR_RTMV20=m
-CONFIG_REGULATOR_SKY81452=m
-CONFIG_REGULATOR_SLG51000=m
-CONFIG_REGULATOR_SY7636A=m
-CONFIG_REGULATOR_TPS51632=m
-CONFIG_REGULATOR_TPS6105X=m
-CONFIG_REGULATOR_TPS62360=m
-CONFIG_REGULATOR_TPS6286X=m
-CONFIG_REGULATOR_TPS65023=m
-CONFIG_REGULATOR_TPS6507X=m
-CONFIG_REGULATOR_TPS65086=m
-CONFIG_REGULATOR_TPS65132=m
-CONFIG_REGULATOR_TPS6524X=m
-CONFIG_REGULATOR_TPS65912=m
-CONFIG_REGULATOR_TPS68470=m
-CONFIG_REGULATOR_WM831X=m
-CONFIG_REGULATOR_WM8994=m
-CONFIG_REGULATOR_QCOM_LABIBB=m
-CONFIG_RC_CORE=m
-CONFIG_RC_MAP=m
-CONFIG_LIRC=y
-CONFIG_RC_DECODERS=y
-CONFIG_IR_NEC_DECODER=m
-CONFIG_IR_RC5_DECODER=m
-CONFIG_IR_RC6_DECODER=m
-CONFIG_IR_JVC_DECODER=m
-CONFIG_IR_SONY_DECODER=m
-CONFIG_IR_SANYO_DECODER=m
-CONFIG_IR_SHARP_DECODER=m
-CONFIG_IR_MCE_KBD_DECODER=m
-CONFIG_IR_XMP_DECODER=m
-CONFIG_IR_IMON_DECODER=m
-CONFIG_IR_RCMM_DECODER=m
-CONFIG_RC_DEVICES=y
-CONFIG_RC_ATI_REMOTE=m
-CONFIG_IR_ENE=m
-CONFIG_IR_IMON=m
-CONFIG_IR_IMON_RAW=m
-CONFIG_IR_MCEUSB=m
-CONFIG_IR_ITE_CIR=m
-CONFIG_IR_FINTEK=m
-CONFIG_IR_NUVOTON=m
-CONFIG_IR_REDRAT3=m
-CONFIG_IR_STREAMZAP=m
-CONFIG_IR_WINBOND_CIR=m
-CONFIG_IR_IGORPLUGUSB=m
-CONFIG_IR_IGUANA=m
-CONFIG_IR_TTUSBIR=m
-CONFIG_RC_LOOPBACK=m
-CONFIG_IR_SERIAL=m
-CONFIG_IR_SERIAL_TRANSMITTER=y
-CONFIG_IR_SIR=m
-CONFIG_RC_XBOX_DVD=m
-CONFIG_IR_TOY=m
-CONFIG_CEC_CORE=m
-CONFIG_CEC_NOTIFIER=y
-CONFIG_CEC_PIN=y
-CONFIG_MEDIA_CEC_RC=y
-# CONFIG_CEC_PIN_ERROR_INJ is not set
-CONFIG_MEDIA_CEC_SUPPORT=y
-CONFIG_CEC_CH7322=m
-CONFIG_CEC_CROS_EC=m
-CONFIG_CEC_GPIO=m
-CONFIG_CEC_SECO=m
-CONFIG_CEC_SECO_RC=y
-CONFIG_USB_PULSE8_CEC=m
-CONFIG_USB_RAINSHADOW_CEC=m
-CONFIG_MEDIA_SUPPORT=m
-CONFIG_MEDIA_SUPPORT_FILTER=y
-CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
-
-#
-# Media device types
-#
-CONFIG_MEDIA_PLATFORM_DRIVERS=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_SDR_SUPPORT=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-# CONFIG_MEDIA_TEST_SUPPORT is not set
-# end of Media device types
-
-CONFIG_VIDEO_DEV=m
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_DVB_CORE=m
-
-#
-# Video4Linux options
-#
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L2_I2C=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_TUNER=m
-CONFIG_V4L2_MEM2MEM_DEV=m
-CONFIG_V4L2_FLASH_LED_CLASS=m
-CONFIG_V4L2_FWNODE=m
-CONFIG_VIDEOBUF_GEN=m
-CONFIG_VIDEOBUF_DMA_SG=m
-CONFIG_VIDEOBUF_VMALLOC=m
-# end of Video4Linux options
-
-#
-# Media controller options
-#
-CONFIG_MEDIA_CONTROLLER_DVB=y
-# end of Media controller options
-
-#
-# Digital TV options
-#
-# CONFIG_DVB_MMAP is not set
-CONFIG_DVB_NET=y
-CONFIG_DVB_MAX_ADAPTERS=8
-CONFIG_DVB_DYNAMIC_MINORS=y
-# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
-# CONFIG_DVB_ULE_DEBUG is not set
-# end of Digital TV options
-
-#
-# Media drivers
-#
-
-#
-# Drivers filtered as selected at 'Filter media drivers'
-#
-CONFIG_TTPCI_EEPROM=m
-CONFIG_MEDIA_USB_SUPPORT=y
-
-#
-# Webcam devices
-#
-CONFIG_USB_VIDEO_CLASS=m
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-CONFIG_USB_M5602=m
-CONFIG_USB_STV06XX=m
-CONFIG_USB_GL860=m
-CONFIG_USB_GSPCA_BENQ=m
-CONFIG_USB_GSPCA_CONEX=m
-CONFIG_USB_GSPCA_CPIA1=m
-CONFIG_USB_GSPCA_DTCS033=m
-CONFIG_USB_GSPCA_ETOMS=m
-CONFIG_USB_GSPCA_FINEPIX=m
-CONFIG_USB_GSPCA_JEILINJ=m
-CONFIG_USB_GSPCA_JL2005BCD=m
-CONFIG_USB_GSPCA_KINECT=m
-CONFIG_USB_GSPCA_KONICA=m
-CONFIG_USB_GSPCA_MARS=m
-CONFIG_USB_GSPCA_MR97310A=m
-CONFIG_USB_GSPCA_NW80X=m
-CONFIG_USB_GSPCA_OV519=m
-CONFIG_USB_GSPCA_OV534=m
-CONFIG_USB_GSPCA_OV534_9=m
-CONFIG_USB_GSPCA_PAC207=m
-CONFIG_USB_GSPCA_PAC7302=m
-CONFIG_USB_GSPCA_PAC7311=m
-CONFIG_USB_GSPCA_SE401=m
-CONFIG_USB_GSPCA_SN9C2028=m
-CONFIG_USB_GSPCA_SN9C20X=m
-CONFIG_USB_GSPCA_SONIXB=m
-CONFIG_USB_GSPCA_SONIXJ=m
-CONFIG_USB_GSPCA_SPCA500=m
-CONFIG_USB_GSPCA_SPCA501=m
-CONFIG_USB_GSPCA_SPCA505=m
-CONFIG_USB_GSPCA_SPCA506=m
-CONFIG_USB_GSPCA_SPCA508=m
-CONFIG_USB_GSPCA_SPCA561=m
-CONFIG_USB_GSPCA_SPCA1528=m
-CONFIG_USB_GSPCA_SQ905=m
-CONFIG_USB_GSPCA_SQ905C=m
-CONFIG_USB_GSPCA_SQ930X=m
-CONFIG_USB_GSPCA_STK014=m
-CONFIG_USB_GSPCA_STK1135=m
-CONFIG_USB_GSPCA_STV0680=m
-CONFIG_USB_GSPCA_SUNPLUS=m
-CONFIG_USB_GSPCA_T613=m
-CONFIG_USB_GSPCA_TOPRO=m
-CONFIG_USB_GSPCA_TOUPTEK=m
-CONFIG_USB_GSPCA_TV8532=m
-CONFIG_USB_GSPCA_VC032X=m
-CONFIG_USB_GSPCA_VICAM=m
-CONFIG_USB_GSPCA_XIRLINK_CIT=m
-CONFIG_USB_GSPCA_ZC3XX=m
-CONFIG_USB_PWC=m
-# CONFIG_USB_PWC_DEBUG is not set
-CONFIG_USB_PWC_INPUT_EVDEV=y
-CONFIG_VIDEO_CPIA2=m
-CONFIG_USB_ZR364XX=m
-CONFIG_USB_STKWEBCAM=m
-CONFIG_USB_S2255=m
-CONFIG_VIDEO_USBTV=m
-
-#
-# Analog TV USB devices
-#
-CONFIG_VIDEO_PVRUSB2=m
-CONFIG_VIDEO_PVRUSB2_SYSFS=y
-CONFIG_VIDEO_PVRUSB2_DVB=y
-# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
-CONFIG_VIDEO_HDPVR=m
-CONFIG_VIDEO_STK1160_COMMON=m
-CONFIG_VIDEO_STK1160=m
-CONFIG_VIDEO_GO7007=m
-CONFIG_VIDEO_GO7007_USB=m
-CONFIG_VIDEO_GO7007_LOADER=m
-CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
-
-#
-# Analog/digital TV USB devices
-#
-CONFIG_VIDEO_AU0828=m
-CONFIG_VIDEO_AU0828_V4L2=y
-CONFIG_VIDEO_AU0828_RC=y
-CONFIG_VIDEO_CX231XX=m
-CONFIG_VIDEO_CX231XX_RC=y
-CONFIG_VIDEO_CX231XX_ALSA=m
-CONFIG_VIDEO_CX231XX_DVB=m
-CONFIG_VIDEO_TM6000=m
-CONFIG_VIDEO_TM6000_ALSA=m
-CONFIG_VIDEO_TM6000_DVB=m
-
-#
-# Digital TV USB devices
-#
-CONFIG_DVB_USB=m
-# CONFIG_DVB_USB_DEBUG is not set
-CONFIG_DVB_USB_DIB3000MC=m
-CONFIG_DVB_USB_A800=m
-CONFIG_DVB_USB_DIBUSB_MB=m
-CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
-CONFIG_DVB_USB_DIBUSB_MC=m
-CONFIG_DVB_USB_DIB0700=m
-CONFIG_DVB_USB_UMT_010=m
-CONFIG_DVB_USB_CXUSB=m
-CONFIG_DVB_USB_CXUSB_ANALOG=y
-CONFIG_DVB_USB_M920X=m
-CONFIG_DVB_USB_DIGITV=m
-CONFIG_DVB_USB_VP7045=m
-CONFIG_DVB_USB_VP702X=m
-CONFIG_DVB_USB_GP8PSK=m
-CONFIG_DVB_USB_NOVA_T_USB2=m
-CONFIG_DVB_USB_TTUSB2=m
-CONFIG_DVB_USB_DTT200U=m
-CONFIG_DVB_USB_OPERA1=m
-CONFIG_DVB_USB_AF9005=m
-CONFIG_DVB_USB_AF9005_REMOTE=m
-CONFIG_DVB_USB_PCTV452E=m
-CONFIG_DVB_USB_DW2102=m
-CONFIG_DVB_USB_CINERGY_T2=m
-CONFIG_DVB_USB_DTV5100=m
-CONFIG_DVB_USB_AZ6027=m
-CONFIG_DVB_USB_TECHNISAT_USB2=m
-CONFIG_DVB_USB_V2=m
-CONFIG_DVB_USB_AF9015=m
-CONFIG_DVB_USB_AF9035=m
-CONFIG_DVB_USB_ANYSEE=m
-CONFIG_DVB_USB_AU6610=m
-CONFIG_DVB_USB_AZ6007=m
-CONFIG_DVB_USB_CE6230=m
-CONFIG_DVB_USB_EC168=m
-CONFIG_DVB_USB_GL861=m
-CONFIG_DVB_USB_LME2510=m
-CONFIG_DVB_USB_MXL111SF=m
-CONFIG_DVB_USB_RTL28XXU=m
-CONFIG_DVB_USB_DVBSKY=m
-CONFIG_DVB_USB_ZD1301=m
-CONFIG_DVB_TTUSB_BUDGET=m
-CONFIG_DVB_TTUSB_DEC=m
-CONFIG_SMS_USB_DRV=m
-CONFIG_DVB_B2C2_FLEXCOP_USB=m
-# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
-CONFIG_DVB_AS102=m
-
-#
-# Webcam, TV (analog/digital) USB devices
-#
-CONFIG_VIDEO_EM28XX=m
-CONFIG_VIDEO_EM28XX_V4L2=m
-CONFIG_VIDEO_EM28XX_ALSA=m
-CONFIG_VIDEO_EM28XX_DVB=m
-CONFIG_VIDEO_EM28XX_RC=m
-
-#
-# Software defined radio USB devices
-#
-CONFIG_USB_AIRSPY=m
-CONFIG_USB_HACKRF=m
-CONFIG_USB_MSI2500=m
-CONFIG_MEDIA_PCI_SUPPORT=y
-
-#
-# Media capture support
-#
-CONFIG_VIDEO_MEYE=m
-CONFIG_VIDEO_SOLO6X10=m
-CONFIG_VIDEO_TW5864=m
-CONFIG_VIDEO_TW68=m
-CONFIG_VIDEO_TW686X=m
-
-#
-# Media capture/analog TV support
-#
-CONFIG_VIDEO_IVTV=m
-# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
-CONFIG_VIDEO_IVTV_ALSA=m
-CONFIG_VIDEO_FB_IVTV=m
-# CONFIG_VIDEO_FB_IVTV_FORCE_PAT is not set
-CONFIG_VIDEO_HEXIUM_GEMINI=m
-CONFIG_VIDEO_HEXIUM_ORION=m
-CONFIG_VIDEO_MXB=m
-CONFIG_VIDEO_DT3155=m
-
-#
-# Media capture/analog/hybrid TV support
-#
-CONFIG_VIDEO_CX18=m
-CONFIG_VIDEO_CX18_ALSA=m
-CONFIG_VIDEO_CX23885=m
-CONFIG_MEDIA_ALTERA_CI=m
-CONFIG_VIDEO_CX25821=m
-CONFIG_VIDEO_CX25821_ALSA=m
-CONFIG_VIDEO_CX88=m
-CONFIG_VIDEO_CX88_ALSA=m
-CONFIG_VIDEO_CX88_BLACKBIRD=m
-CONFIG_VIDEO_CX88_DVB=m
-CONFIG_VIDEO_CX88_ENABLE_VP3054=y
-CONFIG_VIDEO_CX88_VP3054=m
-CONFIG_VIDEO_CX88_MPEG=m
-CONFIG_VIDEO_BT848=m
-CONFIG_DVB_BT8XX=m
-CONFIG_VIDEO_SAA7134=m
-CONFIG_VIDEO_SAA7134_ALSA=m
-CONFIG_VIDEO_SAA7134_RC=y
-CONFIG_VIDEO_SAA7134_DVB=m
-CONFIG_VIDEO_SAA7134_GO7007=m
-CONFIG_VIDEO_SAA7164=m
-# CONFIG_VIDEO_COBALT is not set
-
-#
-# Media digital TV PCI Adapters
-#
-CONFIG_DVB_AV7110_IR=y
-CONFIG_DVB_AV7110=m
-CONFIG_DVB_AV7110_OSD=y
-CONFIG_DVB_BUDGET_CORE=m
-CONFIG_DVB_BUDGET=m
-CONFIG_DVB_BUDGET_CI=m
-CONFIG_DVB_BUDGET_AV=m
-CONFIG_DVB_BUDGET_PATCH=m
-CONFIG_DVB_B2C2_FLEXCOP_PCI=m
-# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
-CONFIG_DVB_PLUTO2=m
-CONFIG_DVB_DM1105=m
-CONFIG_DVB_PT1=m
-CONFIG_DVB_PT3=m
-CONFIG_MANTIS_CORE=m
-CONFIG_DVB_MANTIS=m
-CONFIG_DVB_HOPPER=m
-CONFIG_DVB_NGENE=m
-CONFIG_DVB_DDBRIDGE=m
-# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set
-CONFIG_DVB_SMIPCIE=m
-CONFIG_DVB_NETUP_UNIDVB=m
-CONFIG_VIDEO_IPU3_CIO2=m
-CONFIG_CIO2_BRIDGE=y
-CONFIG_RADIO_ADAPTERS=y
-CONFIG_RADIO_TEA575X=m
-CONFIG_RADIO_SI470X=m
-CONFIG_USB_SI470X=m
-CONFIG_I2C_SI470X=m
-CONFIG_RADIO_SI4713=m
-CONFIG_USB_SI4713=m
-CONFIG_PLATFORM_SI4713=m
-CONFIG_I2C_SI4713=m
-CONFIG_RADIO_SI476X=m
-CONFIG_USB_MR800=m
-CONFIG_USB_DSBR=m
-CONFIG_RADIO_MAXIRADIO=m
-CONFIG_RADIO_SHARK=m
-CONFIG_RADIO_SHARK2=m
-CONFIG_USB_KEENE=m
-CONFIG_USB_RAREMONO=m
-CONFIG_USB_MA901=m
-CONFIG_RADIO_TEA5764=m
-CONFIG_RADIO_SAA7706H=m
-CONFIG_RADIO_TEF6862=m
-CONFIG_RADIO_WL1273=m
-CONFIG_RADIO_WL128X=m
-# CONFIG_V4L_RADIO_ISA_DRIVERS is not set
-CONFIG_MEDIA_COMMON_OPTIONS=y
-
-#
-# common driver options
-#
-CONFIG_VIDEO_CX2341X=m
-CONFIG_VIDEO_TVEEPROM=m
-CONFIG_CYPRESS_FIRMWARE=m
-CONFIG_VIDEOBUF2_CORE=m
-CONFIG_VIDEOBUF2_V4L2=m
-CONFIG_VIDEOBUF2_MEMOPS=m
-CONFIG_VIDEOBUF2_DMA_CONTIG=m
-CONFIG_VIDEOBUF2_VMALLOC=m
-CONFIG_VIDEOBUF2_DMA_SG=m
-CONFIG_VIDEOBUF2_DVB=m
-CONFIG_DVB_B2C2_FLEXCOP=m
-CONFIG_VIDEO_SAA7146=m
-CONFIG_VIDEO_SAA7146_VV=m
-CONFIG_SMS_SIANO_MDTV=m
-CONFIG_SMS_SIANO_RC=y
-# CONFIG_SMS_SIANO_DEBUGFS is not set
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_CAFE_CCIC=m
-CONFIG_VIDEO_VIA_CAMERA=m
-CONFIG_VIDEO_CADENCE=y
-CONFIG_VIDEO_CADENCE_CSI2RX=m
-CONFIG_VIDEO_CADENCE_CSI2TX=m
-CONFIG_VIDEO_ASPEED=m
-CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_VIDEO_ALLEGRO_DVT=m
-CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
-CONFIG_VIDEO_MESON_GE2D=m
-CONFIG_VIDEO_AMPHION_VPU=m
-CONFIG_DVB_PLATFORM_DRIVERS=y
-CONFIG_SDR_PLATFORM_DRIVERS=y
-
-#
-# MMC/SDIO DVB adapters
-#
-CONFIG_SMS_SDIO_DRV=m
-
-#
-# FireWire (IEEE 1394) Adapters
-#
-CONFIG_DVB_FIREDTV=m
-CONFIG_DVB_FIREDTV_INPUT=y
-# end of Media drivers
-
-#
-# Media ancillary drivers
-#
-CONFIG_MEDIA_ATTACH=y
-
-#
-# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
-#
-CONFIG_VIDEO_IR_I2C=m
-
-#
-# Audio decoders, processors and mixers
-#
-CONFIG_VIDEO_TVAUDIO=m
-CONFIG_VIDEO_TDA7432=m
-CONFIG_VIDEO_TDA9840=m
-# CONFIG_VIDEO_TDA1997X is not set
-CONFIG_VIDEO_TEA6415C=m
-CONFIG_VIDEO_TEA6420=m
-CONFIG_VIDEO_MSP3400=m
-CONFIG_VIDEO_CS3308=m
-CONFIG_VIDEO_CS5345=m
-CONFIG_VIDEO_CS53L32A=m
-# CONFIG_VIDEO_TLV320AIC23B is not set
-CONFIG_VIDEO_UDA1342=m
-CONFIG_VIDEO_WM8775=m
-CONFIG_VIDEO_WM8739=m
-CONFIG_VIDEO_VP27SMPX=m
-CONFIG_VIDEO_SONY_BTF_MPX=m
-# end of Audio decoders, processors and mixers
-
-#
-# RDS decoders
-#
-CONFIG_VIDEO_SAA6588=m
-# end of RDS decoders
-
-#
-# Video decoders
-#
-# CONFIG_VIDEO_ADV7180 is not set
-# CONFIG_VIDEO_ADV7183 is not set
-# CONFIG_VIDEO_ADV7604 is not set
-# CONFIG_VIDEO_ADV7842 is not set
-CONFIG_VIDEO_BT819=m
-CONFIG_VIDEO_BT856=m
-CONFIG_VIDEO_BT866=m
-CONFIG_VIDEO_ISL7998X=m
-CONFIG_VIDEO_KS0127=m
-# CONFIG_VIDEO_ML86V7667 is not set
-CONFIG_VIDEO_SAA7110=m
-CONFIG_VIDEO_SAA711X=m
-# CONFIG_VIDEO_TC358743 is not set
-# CONFIG_VIDEO_TVP514X is not set
-CONFIG_VIDEO_TVP5150=m
-# CONFIG_VIDEO_TVP7002 is not set
-CONFIG_VIDEO_TW2804=m
-CONFIG_VIDEO_TW9903=m
-CONFIG_VIDEO_TW9906=m
-# CONFIG_VIDEO_TW9910 is not set
-CONFIG_VIDEO_VPX3220=m
-
-#
-# Video and audio decoders
-#
-CONFIG_VIDEO_SAA717X=m
-CONFIG_VIDEO_CX25840=m
-# end of Video decoders
-
-#
-# Video encoders
-#
-CONFIG_VIDEO_SAA7127=m
-CONFIG_VIDEO_SAA7185=m
-CONFIG_VIDEO_ADV7170=m
-CONFIG_VIDEO_ADV7175=m
-# CONFIG_VIDEO_ADV7343 is not set
-# CONFIG_VIDEO_ADV7393 is not set
-# CONFIG_VIDEO_ADV7511 is not set
-# CONFIG_VIDEO_AD9389B is not set
-# CONFIG_VIDEO_AK881X is not set
-# CONFIG_VIDEO_THS8200 is not set
-# end of Video encoders
-
-#
-# Video improvement chips
-#
-CONFIG_VIDEO_UPD64031A=m
-CONFIG_VIDEO_UPD64083=m
-# end of Video improvement chips
-
-#
-# Audio/Video compression chips
-#
-CONFIG_VIDEO_SAA6752HS=m
-# end of Audio/Video compression chips
-
-#
-# SDR tuner chips
-#
-# CONFIG_SDR_MAX2175 is not set
-# end of SDR tuner chips
-
-#
-# Miscellaneous helper chips
-#
-# CONFIG_VIDEO_THS7303 is not set
-CONFIG_VIDEO_M52790=m
-# CONFIG_VIDEO_I2C is not set
-# CONFIG_VIDEO_ST_MIPID02 is not set
-# end of Miscellaneous helper chips
-
-#
-# Camera sensor devices
-#
-CONFIG_VIDEO_APTINA_PLL=m
-CONFIG_VIDEO_SMIAPP_PLL=m
-CONFIG_VIDEO_HI556=m
-CONFIG_VIDEO_IMX208=m
-CONFIG_VIDEO_IMX214=m
-CONFIG_VIDEO_IMX219=m
-CONFIG_VIDEO_IMX258=m
-CONFIG_VIDEO_IMX274=m
-CONFIG_VIDEO_IMX290=m
-CONFIG_VIDEO_IMX319=m
-CONFIG_VIDEO_IMX334=m
-CONFIG_VIDEO_IMX355=m
-CONFIG_VIDEO_OV02A10=m
-CONFIG_VIDEO_OV08D10=m
-CONFIG_VIDEO_OV2640=m
-CONFIG_VIDEO_OV2659=m
-CONFIG_VIDEO_OV2680=m
-CONFIG_VIDEO_OV2685=m
-CONFIG_VIDEO_OV2740=m
-CONFIG_VIDEO_OV5647=m
-CONFIG_VIDEO_OV5648=m
-CONFIG_VIDEO_OV6650=m
-CONFIG_VIDEO_OV5670=m
-CONFIG_VIDEO_OV5675=m
-CONFIG_VIDEO_OV5695=m
-CONFIG_VIDEO_OV7251=m
-CONFIG_VIDEO_OV772X=m
-CONFIG_VIDEO_OV7640=m
-CONFIG_VIDEO_OV7670=m
-CONFIG_VIDEO_OV7740=m
-CONFIG_VIDEO_OV8856=m
-CONFIG_VIDEO_OV8865=m
-CONFIG_VIDEO_OV9640=m
-CONFIG_VIDEO_OV9650=m
-CONFIG_VIDEO_OV9734=m
-CONFIG_VIDEO_OV13858=m
-CONFIG_VIDEO_VS6624=m
-CONFIG_VIDEO_MT9M001=m
-CONFIG_VIDEO_MT9M032=m
-CONFIG_VIDEO_MT9M111=m
-CONFIG_VIDEO_MT9P031=m
-CONFIG_VIDEO_MT9T001=m
-CONFIG_VIDEO_MT9T112=m
-CONFIG_VIDEO_MT9V011=m
-CONFIG_VIDEO_MT9V032=m
-CONFIG_VIDEO_MT9V111=m
-CONFIG_VIDEO_SR030PC30=m
-CONFIG_VIDEO_NOON010PC30=m
-CONFIG_VIDEO_OG01A1B=m
-CONFIG_VIDEO_M5MOLS=m
-CONFIG_VIDEO_RDACM20=m
-CONFIG_VIDEO_RDACM21=m
-CONFIG_VIDEO_RJ54N1=m
-CONFIG_VIDEO_S5K6AA=m
-CONFIG_VIDEO_S5K6A3=m
-CONFIG_VIDEO_S5K4ECGX=m
-CONFIG_VIDEO_S5K5BAF=m
-CONFIG_VIDEO_CCS=m
-CONFIG_VIDEO_SMIAPP=m
-CONFIG_VIDEO_ET8EK8=m
-CONFIG_VIDEO_S5C73M3=m
-# end of Camera sensor devices
-
-#
-# Lens drivers
-#
-CONFIG_VIDEO_AD5820=m
-CONFIG_VIDEO_AK7375=m
-CONFIG_VIDEO_DW9714=m
-CONFIG_VIDEO_DW9768=m
-CONFIG_VIDEO_DW9807_VCM=m
-# end of Lens drivers
-
-#
-# Flash devices
-#
-CONFIG_VIDEO_ADP1653=m
-CONFIG_VIDEO_LM3560=m
-CONFIG_VIDEO_LM3646=m
-# end of Flash devices
-
-#
-# SPI helper chips
-#
-# CONFIG_VIDEO_GS1662 is not set
-# end of SPI helper chips
-
-#
-# Media SPI Adapters
-#
-CONFIG_CXD2880_SPI_DRV=m
-# end of Media SPI Adapters
-
-CONFIG_MEDIA_TUNER=m
-
-#
-# Customize TV tuners
-#
-CONFIG_MEDIA_TUNER_SIMPLE=m
-CONFIG_MEDIA_TUNER_TDA18250=m
-CONFIG_MEDIA_TUNER_TDA8290=m
-CONFIG_MEDIA_TUNER_TDA827X=m
-CONFIG_MEDIA_TUNER_TDA18271=m
-CONFIG_MEDIA_TUNER_TDA9887=m
-CONFIG_MEDIA_TUNER_TEA5761=m
-CONFIG_MEDIA_TUNER_TEA5767=m
-CONFIG_MEDIA_TUNER_MSI001=m
-CONFIG_MEDIA_TUNER_MT20XX=m
-CONFIG_MEDIA_TUNER_MT2060=m
-CONFIG_MEDIA_TUNER_MT2063=m
-CONFIG_MEDIA_TUNER_MT2266=m
-CONFIG_MEDIA_TUNER_MT2131=m
-CONFIG_MEDIA_TUNER_QT1010=m
-CONFIG_MEDIA_TUNER_XC2028=m
-CONFIG_MEDIA_TUNER_XC5000=m
-CONFIG_MEDIA_TUNER_XC4000=m
-CONFIG_MEDIA_TUNER_MXL5005S=m
-CONFIG_MEDIA_TUNER_MXL5007T=m
-CONFIG_MEDIA_TUNER_MC44S803=m
-CONFIG_MEDIA_TUNER_MAX2165=m
-CONFIG_MEDIA_TUNER_TDA18218=m
-CONFIG_MEDIA_TUNER_FC0011=m
-CONFIG_MEDIA_TUNER_FC0012=m
-CONFIG_MEDIA_TUNER_FC0013=m
-CONFIG_MEDIA_TUNER_TDA18212=m
-CONFIG_MEDIA_TUNER_E4000=m
-CONFIG_MEDIA_TUNER_FC2580=m
-CONFIG_MEDIA_TUNER_M88RS6000T=m
-CONFIG_MEDIA_TUNER_TUA9001=m
-CONFIG_MEDIA_TUNER_SI2157=m
-CONFIG_MEDIA_TUNER_IT913X=m
-CONFIG_MEDIA_TUNER_R820T=m
-CONFIG_MEDIA_TUNER_MXL301RF=m
-CONFIG_MEDIA_TUNER_QM1D1C0042=m
-CONFIG_MEDIA_TUNER_QM1D1B0004=m
-CONFIG_MEDIA_TUNER_AV201X=m
-CONFIG_MEDIA_TUNER_STV6120=m
-# end of Customize TV tuners
-
-#
-# Customise DVB Frontends
-#
-
-#
-# Multistandard (satellite) frontends
-#
-CONFIG_DVB_STB0899=m
-CONFIG_DVB_STB6100=m
-CONFIG_DVB_STV090x=m
-CONFIG_DVB_STV0910=m
-CONFIG_DVB_STV6110x=m
-CONFIG_DVB_STV6111=m
-CONFIG_DVB_MXL5XX=m
-CONFIG_DVB_M88DS3103=m
-
-#
-# Multistandard (cable + terrestrial) frontends
-#
-CONFIG_DVB_DRXK=m
-CONFIG_DVB_TDA18271C2DD=m
-CONFIG_DVB_SI2165=m
-CONFIG_DVB_MN88472=m
-CONFIG_DVB_MN88473=m
-
-#
-# DVB-S (satellite) frontends
-#
-CONFIG_DVB_CX24110=m
-CONFIG_DVB_CX24123=m
-CONFIG_DVB_MT312=m
-CONFIG_DVB_ZL10036=m
-CONFIG_DVB_ZL10039=m
-CONFIG_DVB_S5H1420=m
-CONFIG_DVB_STV0288=m
-CONFIG_DVB_STB6000=m
-CONFIG_DVB_STV0299=m
-CONFIG_DVB_STV6110=m
-CONFIG_DVB_STV0900=m
-CONFIG_DVB_TDA8083=m
-CONFIG_DVB_TDA10086=m
-CONFIG_DVB_TDA8261=m
-CONFIG_DVB_VES1X93=m
-CONFIG_DVB_TUNER_ITD1000=m
-CONFIG_DVB_TUNER_CX24113=m
-CONFIG_DVB_TDA826X=m
-CONFIG_DVB_TUA6100=m
-CONFIG_DVB_CX24116=m
-CONFIG_DVB_CX24117=m
-CONFIG_DVB_CX24120=m
-CONFIG_DVB_SI21XX=m
-CONFIG_DVB_TS2020=m
-CONFIG_DVB_DS3000=m
-CONFIG_DVB_MB86A16=m
-CONFIG_DVB_TDA10071=m
-
-#
-# DVB-T (terrestrial) frontends
-#
-CONFIG_DVB_SP8870=m
-CONFIG_DVB_SP887X=m
-CONFIG_DVB_CX22700=m
-CONFIG_DVB_CX22702=m
-# CONFIG_DVB_S5H1432 is not set
-CONFIG_DVB_DRXD=m
-CONFIG_DVB_L64781=m
-CONFIG_DVB_TDA1004X=m
-CONFIG_DVB_NXT6000=m
-CONFIG_DVB_MT352=m
-CONFIG_DVB_ZL10353=m
-CONFIG_DVB_DIB3000MB=m
-CONFIG_DVB_DIB3000MC=m
-CONFIG_DVB_DIB7000M=m
-CONFIG_DVB_DIB7000P=m
-# CONFIG_DVB_DIB9000 is not set
-CONFIG_DVB_TDA10048=m
-CONFIG_DVB_AF9013=m
-CONFIG_DVB_EC100=m
-CONFIG_DVB_STV0367=m
-CONFIG_DVB_CXD2820R=m
-CONFIG_DVB_CXD2841ER=m
-CONFIG_DVB_RTL2830=m
-CONFIG_DVB_RTL2832=m
-CONFIG_DVB_RTL2832_SDR=m
-CONFIG_DVB_SI2168=m
-CONFIG_DVB_AS102_FE=m
-CONFIG_DVB_ZD1301_DEMOD=m
-CONFIG_DVB_GP8PSK_FE=m
-# CONFIG_DVB_CXD2880 is not set
-
-#
-# DVB-C (cable) frontends
-#
-CONFIG_DVB_VES1820=m
-CONFIG_DVB_TDA10021=m
-CONFIG_DVB_TDA10023=m
-CONFIG_DVB_STV0297=m
-
-#
-# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
-#
-CONFIG_DVB_NXT200X=m
-CONFIG_DVB_OR51211=m
-CONFIG_DVB_OR51132=m
-CONFIG_DVB_BCM3510=m
-CONFIG_DVB_LGDT330X=m
-CONFIG_DVB_LGDT3305=m
-CONFIG_DVB_LGDT3306A=m
-CONFIG_DVB_LG2160=m
-CONFIG_DVB_S5H1409=m
-CONFIG_DVB_AU8522=m
-CONFIG_DVB_AU8522_DTV=m
-CONFIG_DVB_AU8522_V4L=m
-CONFIG_DVB_S5H1411=m
-
-#
-# ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_S921=m
-CONFIG_DVB_DIB8000=m
-CONFIG_DVB_MB86A20S=m
-
-#
-# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_TC90522=m
-# CONFIG_DVB_MN88443X is not set
-
-#
-# Digital terrestrial only tuners/PLL
-#
-CONFIG_DVB_PLL=m
-CONFIG_DVB_TUNER_DIB0070=m
-CONFIG_DVB_TUNER_DIB0090=m
-
-#
-# SEC control devices for DVB-S
-#
-CONFIG_DVB_DRX39XYJ=m
-CONFIG_DVB_LNBH25=m
-# CONFIG_DVB_LNBH29 is not set
-CONFIG_DVB_LNBP21=m
-CONFIG_DVB_LNBP22=m
-CONFIG_DVB_ISL6405=m
-CONFIG_DVB_ISL6421=m
-CONFIG_DVB_ISL6422=m
-CONFIG_DVB_ISL6423=m
-CONFIG_DVB_A8293=m
-# CONFIG_DVB_LGS8GL5 is not set
-CONFIG_DVB_LGS8GXX=m
-CONFIG_DVB_ATBM8830=m
-CONFIG_DVB_TDA665x=m
-CONFIG_DVB_IX2505V=m
-CONFIG_DVB_M88RS2000=m
-CONFIG_DVB_AF9033=m
-CONFIG_DVB_TAS2101=m
-CONFIG_DVB_HORUS3A=m
-CONFIG_DVB_ASCOT2E=m
-CONFIG_DVB_HELENE=m
-
-#
-# Common Interface (EN50221) controller drivers
-#
-CONFIG_DVB_CXD2099=m
-CONFIG_DVB_SP2=m
-# end of Customise DVB Frontends
-# end of Media ancillary drivers
-
-#
-# Graphics support
-#
-CONFIG_AGP=m
-# CONFIG_AGP_ALI is not set
-# CONFIG_AGP_ATI is not set
-# CONFIG_AGP_AMD is not set
-CONFIG_AGP_AMD64=m
-CONFIG_AGP_INTEL=m
-# CONFIG_AGP_NVIDIA is not set
-CONFIG_AGP_SIS=m
-# CONFIG_AGP_SWORKS is not set
-CONFIG_AGP_VIA=m
-# CONFIG_AGP_EFFICEON is not set
-CONFIG_INTEL_GTT=m
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-CONFIG_VGA_SWITCHEROO=y
-CONFIG_BOOTSPLASH=y
-CONFIG_DRM=m
-CONFIG_DRM_GUD=m
-CONFIG_DRM_SSD130X=m
-CONFIG_DRM_SSD130X_I2C=m
-CONFIG_DRM_SPRD=m
-CONFIG_DRM_HYPERV=m
-CONFIG_DRM_MIPI_DBI=m
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_DP_AUX_CHARDEV=y
-# CONFIG_DRM_DEBUG_MM is not set
-# CONFIG_DRM_DEBUG_SELFTEST is not set
-CONFIG_DRM_KMS_HELPER=m
-CONFIG_DRM_KMS_FB_HELPER=y
-# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
-# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
-# CONFIG_DRM_DP_CEC is not set
-CONFIG_DRM_TTM=m
-CONFIG_DRM_TTM_DMA_PAGE_POOL=y
-CONFIG_DRM_VRAM_HELPER=m
-CONFIG_DRM_TTM_HELPER=m
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-CONFIG_DRM_VM=y
-CONFIG_DRM_SCHED=m
-
-#
-# I2C encoder or helper chips
-#
-CONFIG_DRM_I2C_CH7006=m
-CONFIG_DRM_I2C_SIL164=m
-CONFIG_DRM_I2C_NXP_TDA998X=m
-CONFIG_DRM_I2C_NXP_TDA9950=m
-# end of I2C encoder or helper chips
-
-#
-# ARM devices
-#
-# end of ARM devices
-
-CONFIG_DRM_RADEON=m
-# CONFIG_DRM_RADEON_USERPTR is not set
-CONFIG_DRM_AMDGPU=m
-CONFIG_DRM_AMDGPU_SI=y
-CONFIG_DRM_AMDGPU_CIK=y
-# CONFIG_DRM_AMDGPU_USERPTR is not set
-# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set
-
-#
-# ACP (Audio CoProcessor) Configuration
-#
-CONFIG_DRM_AMD_ACP=y
-# end of ACP (Audio CoProcessor) Configuration
-
-#
-# Display Engine Configuration
-#
-CONFIG_DRM_AMD_DC=y
-CONFIG_DRM_AMD_DC_DCN=y
-CONFIG_DRM_AMD_DC_DCN3_0=y
-CONFIG_DRM_AMD_DC_HDCP=y
-CONFIG_DRM_AMD_DC_SI=y
-CONFIG_DRM_AMD_SECURE_DISPLAY=y
-CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
-# CONFIG_DEBUG_KERNEL_DC is not set
-# end of Display Engine Configuration
-
-CONFIG_DRM_NOUVEAU=m
-CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT=y
-CONFIG_NOUVEAU_DEBUG=5
-CONFIG_NOUVEAU_DEBUG_DEFAULT=3
-# CONFIG_NOUVEAU_DEBUG_MMU is not set
-# CONFIG_NOUVEAU_DEBUG_PUSH is not set
-CONFIG_DRM_NOUVEAU_BACKLIGHT=y
-CONFIG_DRM_I915=m
-CONFIG_DRM_I915_FORCE_PROBE=""
-CONFIG_DRM_I915_CAPTURE_ERROR=y
-CONFIG_DRM_I915_COMPRESS_ERROR=y
-CONFIG_DRM_I915_USERPTR=y
-CONFIG_DRM_I915_PXP=y
-
-#
-# drm/i915 Debugging
-#
-# CONFIG_DRM_I915_WERROR is not set
-# CONFIG_DRM_I915_DEBUG is not set
-# CONFIG_DRM_I915_DEBUG_MMIO is not set
-# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
-# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
-# CONFIG_DRM_I915_DEBUG_GUC is not set
-# CONFIG_DRM_I915_SELFTEST is not set
-# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
-# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
-# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set
-# end of drm/i915 Debugging
-
-#
-# drm/i915 Profile Guided Optimisation
-#
-CONFIG_DRM_I915_FENCE_TIMEOUT=10000
-CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
-CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
-CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
-CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
-CONFIG_DRM_I915_STOP_TIMEOUT=100
-CONFIG_DRM_I915_TIMESLICE_DURATION=1
-# end of drm/i915 Profile Guided Optimisation
-
-CONFIG_DRM_VGEM=m
-CONFIG_DRM_VKMS=m
-CONFIG_DRM_VMWGFX=m
-CONFIG_DRM_VMWGFX_FBCON=y
-CONFIG_DRM_VMWGFX_MKSSTATS=y
-CONFIG_DRM_GMA500=m
-CONFIG_DRM_PANEL_MIPI_DBI=m
-CONFIG_DRM_GMA600=y
-CONFIG_DRM_GMA3600=y
-CONFIG_DRM_UDL=m
-CONFIG_DRM_AST=m
-CONFIG_DRM_MGAG200=m
-CONFIG_DRM_QXL=m
-CONFIG_DRM_BOCHS=m
-CONFIG_DRM_VIRTIO_GPU=m
-CONFIG_DRM_PANEL=y
-
-#
-# Display Panels
-#
-CONFIG_DRM_PANEL_ABT_Y030XX067A=m
-CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
-# end of Display Panels
-
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_PANEL_BRIDGE=y
-
-#
-# Display Interface Bridges
-#
-CONFIG_DRM_ANALOGIX_ANX78XX=m
-CONFIG_DRM_ANALOGIX_ANX7625=m
-CONFIG_DRM_ANALOGIX_DP=m
-# end of Display Interface Bridges
-
-CONFIG_DRM_ETNAVIV=m
-CONFIG_DRM_ETNAVIV_THERMAL=y
-CONFIG_DRM_CIRRUS_QEMU=m
-CONFIG_DRM_GM12U320=m
-CONFIG_DRM_SIMPLEDRM=y
-CONFIG_TINYDRM_HX8357D=m
-CONFIG_TINYDRM_ILI9225=m
-CONFIG_TINYDRM_ILI9341=m
-CONFIG_TINYDRM_ILI9486=m
-CONFIG_TINYDRM_MI0283QT=m
-CONFIG_TINYDRM_REPAPER=m
-CONFIG_TINYDRM_ST7586=m
-CONFIG_TINYDRM_ST7735R=m
-CONFIG_DRM_VBOXVIDEO=m
-CONFIG_DRM_LEGACY=y
-CONFIG_DRM_TDFX=m
-CONFIG_DRM_R128=m
-CONFIG_DRM_MGA=m
-CONFIG_DRM_SIS=m
-CONFIG_DRM_VIA=m
-CONFIG_DRM_SAVAGE=m
-CONFIG_DRM_EXPORT_FOR_TESTS=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_LIB_RANDOM=y
-
-#
-# Frame buffer Devices
-#
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_NOTIFY=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_DDC=m
-CONFIG_FB_BOOT_VESA_SUPPORT=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SYS_FILLRECT=m
-CONFIG_FB_SYS_COPYAREA=m
-CONFIG_FB_SYS_IMAGEBLIT=m
-CONFIG_FB_FOREIGN_ENDIAN=y
-CONFIG_FB_BOTH_ENDIAN=y
-# CONFIG_FB_BIG_ENDIAN is not set
-# CONFIG_FB_LITTLE_ENDIAN is not set
-CONFIG_FB_SYS_FOPS=m
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_HECUBA=m
-CONFIG_FB_SVGALIB=m
-CONFIG_FB_BACKLIGHT=m
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
-
-#
-# Frame buffer hardware drivers
-#
-CONFIG_FB_CIRRUS=m
-CONFIG_FB_PM2=m
-CONFIG_FB_PM2_FIFO_DISCONNECT=y
-CONFIG_FB_CYBER2000=m
-CONFIG_FB_CYBER2000_DDC=y
-CONFIG_FB_ARC=m
-CONFIG_FB_ASILIANT=y
-CONFIG_FB_IMSTT=y
-CONFIG_FB_VGA16=m
-CONFIG_FB_UVESA=m
-CONFIG_FB_VESA=y
-CONFIG_FB_EFI=y
-CONFIG_FB_N411=m
-# CONFIG_FB_HGA is not set
-CONFIG_FB_OPENCORES=m
-CONFIG_FB_S1D13XXX=m
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-CONFIG_FB_I740=m
-# CONFIG_FB_I810 is not set
-CONFIG_FB_LE80578=m
-CONFIG_FB_CARILLO_RANCH=m
-# CONFIG_FB_INTEL is not set
-CONFIG_FB_MATROX=m
-CONFIG_FB_MATROX_MILLENIUM=y
-CONFIG_FB_MATROX_MYSTIQUE=y
-CONFIG_FB_MATROX_G=y
-CONFIG_FB_MATROX_I2C=m
-CONFIG_FB_MATROX_MAVEN=m
-CONFIG_FB_RADEON=m
-CONFIG_FB_RADEON_I2C=y
-CONFIG_FB_RADEON_BACKLIGHT=y
-# CONFIG_FB_RADEON_DEBUG is not set
-CONFIG_FB_ATY128=m
-CONFIG_FB_ATY128_BACKLIGHT=y
-CONFIG_FB_ATY=m
-CONFIG_FB_ATY_CT=y
-CONFIG_FB_ATY_GENERIC_LCD=y
-CONFIG_FB_ATY_GX=y
-CONFIG_FB_ATY_BACKLIGHT=y
-CONFIG_FB_S3=m
-CONFIG_FB_S3_DDC=y
-CONFIG_FB_SAVAGE=m
-CONFIG_FB_SAVAGE_I2C=y
-CONFIG_FB_SAVAGE_ACCEL=y
-CONFIG_FB_SIS=m
-CONFIG_FB_SIS_300=y
-CONFIG_FB_SIS_315=y
-CONFIG_FB_VIA=m
-# CONFIG_FB_VIA_DIRECT_PROCFS is not set
-CONFIG_FB_VIA_X_COMPATIBILITY=y
-CONFIG_FB_NEOMAGIC=m
-CONFIG_FB_KYRO=m
-CONFIG_FB_3DFX=m
-CONFIG_FB_3DFX_ACCEL=y
-CONFIG_FB_3DFX_I2C=y
-CONFIG_FB_VOODOO1=m
-CONFIG_FB_VT8623=m
-CONFIG_FB_TRIDENT=m
-CONFIG_FB_ARK=m
-CONFIG_FB_PM3=m
-CONFIG_FB_CARMINE=m
-CONFIG_FB_CARMINE_DRAM_EVAL=y
-# CONFIG_CARMINE_DRAM_CUSTOM is not set
-# CONFIG_FB_GEODE is not set
-CONFIG_FB_SM501=m
-CONFIG_FB_SMSCUFX=m
-CONFIG_FB_UDL=m
-CONFIG_FB_IBM_GXT4500=m
-CONFIG_FB_VIRTUAL=m
-CONFIG_FB_METRONOME=m
-CONFIG_FB_MB862XX=m
-CONFIG_FB_MB862XX_PCI_GDC=y
-CONFIG_FB_MB862XX_I2C=y
-CONFIG_FB_HYPERV=m
-CONFIG_FB_SIMPLE=y
-CONFIG_FB_SSD1307=m
-CONFIG_FB_SM712=m
-# end of Frame buffer Devices
-
-#
-# Backlight & LCD device support
-#
-CONFIG_LCD_CLASS_DEVICE=m
-CONFIG_LCD_L4F00242T03=m
-CONFIG_LCD_LMS283GF05=m
-CONFIG_LCD_LTV350QV=m
-CONFIG_LCD_ILI922X=m
-CONFIG_LCD_ILI9320=m
-CONFIG_LCD_TDO24M=m
-CONFIG_LCD_VGG2432A4=m
-CONFIG_LCD_PLATFORM=m
-CONFIG_LCD_AMS369FG06=m
-CONFIG_LCD_LMS501KF03=m
-CONFIG_LCD_HX8357=m
-CONFIG_LCD_OTM3225A=m
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_KTD253=m
-CONFIG_BACKLIGHT_LM3533=m
-CONFIG_BACKLIGHT_CARILLO_RANCH=m
-CONFIG_BACKLIGHT_PWM=m
-CONFIG_BACKLIGHT_MT6370=m
-CONFIG_BACKLIGHT_DA9052=m
-CONFIG_BACKLIGHT_MT6370=m
-CONFIG_BACKLIGHT_APPLE=m
-CONFIG_BACKLIGHT_QCOM_WLED=m
-CONFIG_BACKLIGHT_RT4831=m
-CONFIG_BACKLIGHT_SAHARA=m
-CONFIG_BACKLIGHT_WM831X=m
-CONFIG_BACKLIGHT_ADP8860=m
-CONFIG_BACKLIGHT_ADP8870=m
-CONFIG_BACKLIGHT_PCF50633=m
-CONFIG_BACKLIGHT_LM3630A=m
-CONFIG_BACKLIGHT_LM3639=m
-CONFIG_BACKLIGHT_LP855X=m
-CONFIG_BACKLIGHT_SKY81452=m
-CONFIG_BACKLIGHT_GPIO=m
-CONFIG_BACKLIGHT_LV5207LP=m
-CONFIG_BACKLIGHT_BD6107=m
-CONFIG_BACKLIGHT_ARCXCNN=m
-CONFIG_BACKLIGHT_RAVE_SP=m
-# end of Backlight & LCD device support
-
-CONFIG_VGASTATE=m
-CONFIG_HDMI=y
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-# CONFIG_MDA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DUMMY_CONSOLE_COLUMNS=80
-CONFIG_DUMMY_CONSOLE_ROWS=25
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
-# end of Console display driver support
-
-# CONFIG_LOGO is not set
-# end of Graphics support
-
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_PCM_ELD=y
-CONFIG_SND_PCM_IEC958=y
-CONFIG_SND_DMAENGINE_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_SEQ_DEVICE=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_COMPRESS_OFFLOAD=m
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_PCM_TIMER=y
-CONFIG_SND_HRTIMER=m
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_MAX_CARDS=32
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_PROC_FS=y
-CONFIG_SND_VERBOSE_PROCFS=y
-CONFIG_SND_CTL_FAST_LOOKUP=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_CTL_INPUT_VALIDATION=y
-CONFIG_SND_VMASTER=y
-CONFIG_SND_DMA_SGBUF=y
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_SEQUENCER_OSS=m
-CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
-CONFIG_SND_SEQ_MIDI_EVENT=m
-CONFIG_SND_SEQ_MIDI=m
-CONFIG_SND_SEQ_MIDI_EMUL=m
-CONFIG_SND_SEQ_VIRMIDI=m
-CONFIG_SND_MPU401_UART=m
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_OPL3_LIB_SEQ=m
-CONFIG_SND_VX_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_PCSP is not set
-CONFIG_SND_DUMMY=m
-CONFIG_SND_ALOOP=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_MTS64=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_PORTMAN2X4=m
-CONFIG_SND_AC97_POWER_SAVE=y
-CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
-CONFIG_SND_SB_COMMON=m
-CONFIG_SND_ISA=y
-# CONFIG_SND_ADLIB is not set
-# CONFIG_SND_AD1816A is not set
-# CONFIG_SND_AD1848 is not set
-# CONFIG_SND_ALS100 is not set
-# CONFIG_SND_AZT1605 is not set
-# CONFIG_SND_AZT2316 is not set
-# CONFIG_SND_AZT2320 is not set
-# CONFIG_SND_CMI8328 is not set
-# CONFIG_SND_CMI8330 is not set
-# CONFIG_SND_CS4231 is not set
-# CONFIG_SND_CS4236 is not set
-# CONFIG_SND_ES1688 is not set
-# CONFIG_SND_ES18XX is not set
-# CONFIG_SND_SC6000 is not set
-# CONFIG_SND_GUSCLASSIC is not set
-# CONFIG_SND_GUSEXTREME is not set
-# CONFIG_SND_GUSMAX is not set
-# CONFIG_SND_INTERWAVE is not set
-# CONFIG_SND_INTERWAVE_STB is not set
-# CONFIG_SND_JAZZ16 is not set
-# CONFIG_SND_OPL3SA2 is not set
-# CONFIG_SND_OPTI92X_AD1848 is not set
-# CONFIG_SND_OPTI92X_CS4231 is not set
-# CONFIG_SND_OPTI93X is not set
-# CONFIG_SND_MIRO is not set
-# CONFIG_SND_SB8 is not set
-# CONFIG_SND_SB16 is not set
-# CONFIG_SND_SBAWE is not set
-# CONFIG_SND_SSCAPE is not set
-# CONFIG_SND_WAVEFRONT is not set
-# CONFIG_SND_MSND_PINNACLE is not set
-# CONFIG_SND_MSND_CLASSIC is not set
-CONFIG_SND_PCI=y
-CONFIG_SND_AD1889=m
-CONFIG_SND_ALS300=m
-CONFIG_SND_ALS4000=m
-CONFIG_SND_ALI5451=m
-CONFIG_SND_ASIHPI=m
-CONFIG_SND_ATIIXP=m
-CONFIG_SND_ATIIXP_MODEM=m
-CONFIG_SND_AU8810=m
-CONFIG_SND_AU8820=m
-CONFIG_SND_AU8830=m
-CONFIG_SND_AW2=m
-CONFIG_SND_AZT3328=m
-CONFIG_SND_BT87X=m
-CONFIG_SND_BT87X_OVERCLOCK=y
-CONFIG_SND_CA0106=m
-CONFIG_SND_CMIPCI=m
-CONFIG_SND_OXYGEN_LIB=m
-CONFIG_SND_OXYGEN=m
-CONFIG_SND_CS4281=m
-CONFIG_SND_CS46XX=m
-CONFIG_SND_CS46XX_NEW_DSP=y
-# CONFIG_SND_CS5530 is not set
-# CONFIG_SND_CS5535AUDIO is not set
-CONFIG_SND_CTXFI=m
-CONFIG_SND_DARLA20=m
-CONFIG_SND_GINA20=m
-CONFIG_SND_LAYLA20=m
-CONFIG_SND_DARLA24=m
-CONFIG_SND_GINA24=m
-CONFIG_SND_LAYLA24=m
-CONFIG_SND_MONA=m
-CONFIG_SND_MIA=m
-CONFIG_SND_ECHO3G=m
-CONFIG_SND_INDIGO=m
-CONFIG_SND_INDIGOIO=m
-CONFIG_SND_INDIGODJ=m
-CONFIG_SND_INDIGOIOX=m
-CONFIG_SND_INDIGODJX=m
-CONFIG_SND_EMU10K1=m
-CONFIG_SND_EMU10K1_SEQ=m
-CONFIG_SND_EMU10K1X=m
-CONFIG_SND_ENS1370=m
-CONFIG_SND_ENS1371=m
-CONFIG_SND_ES1938=m
-CONFIG_SND_ES1968=m
-CONFIG_SND_ES1968_INPUT=y
-CONFIG_SND_ES1968_RADIO=y
-CONFIG_SND_FM801=m
-CONFIG_SND_FM801_TEA575X_BOOL=y
-CONFIG_SND_HDSP=m
-CONFIG_SND_HDSPM=m
-CONFIG_SND_ICE1712=m
-CONFIG_SND_ICE1724=m
-CONFIG_SND_INTEL8X0=m
-CONFIG_SND_INTEL8X0M=m
-CONFIG_SND_KORG1212=m
-CONFIG_SND_LOLA=m
-CONFIG_SND_LX6464ES=m
-CONFIG_SND_MAESTRO3=m
-CONFIG_SND_MAESTRO3_INPUT=y
-CONFIG_SND_MIXART=m
-CONFIG_SND_NM256=m
-CONFIG_SND_PCXHR=m
-CONFIG_SND_RIPTIDE=m
-CONFIG_SND_RME32=m
-CONFIG_SND_RME96=m
-CONFIG_SND_RME9652=m
-# CONFIG_SND_SIS7019 is not set
-CONFIG_SND_SONICVIBES=m
-CONFIG_SND_TRIDENT=m
-CONFIG_SND_VIA82XX=m
-CONFIG_SND_VIA82XX_MODEM=m
-CONFIG_SND_VIRTUOSO=m
-CONFIG_SND_VX222=m
-CONFIG_SND_YMFPCI=m
-
-#
-# HD-Audio
-#
-CONFIG_SND_HDA=m
-CONFIG_SND_HDA_GENERIC_LEDS=y
-CONFIG_SND_HDA_INTEL=m
-CONFIG_SND_HDA_HWDEP=y
-CONFIG_SND_HDA_RECONFIG=y
-CONFIG_SND_HDA_INPUT_BEEP=y
-CONFIG_SND_HDA_INPUT_BEEP_MODE=1
-CONFIG_SND_HDA_PATCH_LOADER=y
-CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m
-CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m
-CONFIG_SND_HDA_CODEC_REALTEK=m
-CONFIG_SND_HDA_CODEC_ANALOG=m
-CONFIG_SND_HDA_CODEC_SIGMATEL=m
-CONFIG_SND_HDA_CODEC_VIA=m
-CONFIG_SND_HDA_CODEC_HDMI=m
-CONFIG_SND_HDA_CODEC_CIRRUS=m
-CONFIG_SND_HDA_CODEC_CONEXANT=m
-CONFIG_SND_HDA_CODEC_CA0110=m
-CONFIG_SND_HDA_CODEC_CA0132=m
-CONFIG_SND_HDA_CODEC_CA0132_DSP=y
-CONFIG_SND_HDA_CODEC_CMEDIA=m
-CONFIG_SND_HDA_CODEC_SI3054=m
-CONFIG_SND_HDA_GENERIC=m
-CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
-# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
-# end of HD-Audio
-
-CONFIG_SND_HDA_CORE=m
-CONFIG_SND_HDA_DSP_LOADER=y
-CONFIG_SND_HDA_COMPONENT=y
-CONFIG_SND_HDA_I915=y
-CONFIG_SND_HDA_EXT_CORE=m
-CONFIG_SND_HDA_PREALLOC_SIZE=2048
-CONFIG_SND_VIRTIO=m
-CONFIG_SND_INTEL_BYT_PREFER_SOF=y
-CONFIG_SND_INTEL_NHLT=y
-CONFIG_SND_INTEL_DSP_CONFIG=m
-CONFIG_SND_SPI=y
-CONFIG_SND_USB=y
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
-CONFIG_SND_USB_UA101=m
-CONFIG_SND_USB_USX2Y=m
-CONFIG_SND_USB_CAIAQ=m
-CONFIG_SND_USB_CAIAQ_INPUT=y
-CONFIG_SND_USB_US122L=m
-CONFIG_SND_USB_6FIRE=m
-CONFIG_SND_USB_HIFACE=m
-CONFIG_SND_BCD2000=m
-CONFIG_SND_USB_LINE6=m
-CONFIG_SND_USB_POD=m
-CONFIG_SND_USB_PODHD=m
-CONFIG_SND_USB_TONEPORT=m
-CONFIG_SND_USB_VARIAX=m
-CONFIG_SND_FIREWIRE=y
-CONFIG_SND_FIREWIRE_LIB=m
-CONFIG_SND_DICE=m
-CONFIG_SND_OXFW=m
-CONFIG_SND_ISIGHT=m
-CONFIG_SND_FIREWORKS=m
-CONFIG_SND_BEBOB=m
-CONFIG_SND_FIREWIRE_DIGI00X=m
-CONFIG_SND_FIREWIRE_TASCAM=m
-CONFIG_SND_FIREWIRE_MOTU=m
-CONFIG_SND_FIREFACE=m
-CONFIG_SND_PCMCIA=y
-CONFIG_SND_VXPOCKET=m
-CONFIG_SND_PDAUDIOCF=m
-CONFIG_SND_SOC=m
-CONFIG_SND_SOC_ADI=m
-CONFIG_SND_SOC_ADI_AXI_I2S=m
-CONFIG_SND_SOC_ADI_AXI_SPDIF=m
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_COMPRESS=y
-CONFIG_SND_SOC_TOPOLOGY=y
-CONFIG_SND_SOC_ACPI=m
-CONFIG_SND_SOC_AMD_ACP=m
-CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m
-CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m
-CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
-CONFIG_SND_SOC_AMD_ACP3x=m
-CONFIG_SND_SOC_AMD_RV_RT5682_MACH=m
-CONFIG_SND_SOC_AMD_RENOIR=m
-CONFIG_SND_SOC_AMD_RENOIR_MACH=m
-CONFIG_SND_SOC_AMD_ACP5x=m
-CONFIG_SND_SOC_AMD_VANGOGH_MACH=m
-CONFIG_SND_SOC_AMD_ACP6x=m
-CONFIG_SND_SOC_AMD_YC_MACH=m
-CONFIG_SND_SOC_AMD_ACP_COMMON=m
-CONFIG_SND_SOC_AMD_ACP_PCI=m
-CONFIG_SND_AMD_ASOC_RENOIR=m
-CONFIG_SND_AMD_ASOC_REMBRANDT=m
-CONFIG_SND_SOC_AMD_LEGACY_MACH=m
-CONFIG_SND_SOC_AMD_SOF_MACH=m
-CONFIG_SND_SOC_AMD_RPL_ACP6x=m
-CONFIG_SND_SOC_AMD_PS=m
-CONFIG_SND_SOC_AMD_PS_MACH=m
-CONFIG_SND_ATMEL_SOC=m
-CONFIG_SND_BCM63XX_I2S_WHISTLER=m
-CONFIG_SND_DESIGNWARE_I2S=m
-CONFIG_SND_DESIGNWARE_PCM=y
-
-#
-# SoC Audio for Freescale CPUs
-#
-
-#
-# Common SoC Audio options for Freescale CPUs:
-#
-CONFIG_SND_SOC_FSL_ASRC=m
-CONFIG_SND_SOC_FSL_SAI=m
-CONFIG_SND_SOC_FSL_MQS=m
-CONFIG_SND_SOC_FSL_AUDMIX=m
-CONFIG_SND_SOC_FSL_SSI=m
-CONFIG_SND_SOC_FSL_SPDIF=m
-CONFIG_SND_SOC_FSL_ESAI=m
-CONFIG_SND_SOC_FSL_MICFIL=m
-CONFIG_SND_SOC_FSL_EASRC=m
-CONFIG_SND_SOC_FSL_XCVR=m
-CONFIG_SND_SOC_FSL_AUD2HTX=m
-CONFIG_SND_SOC_FSL_RPMSG=m
-CONFIG_SND_SOC_IMX_AUDMUX=m
-# end of SoC Audio for Freescale CPUs
-
-CONFIG_SND_I2S_HI6210_I2S=m
-CONFIG_SND_SOC_IMG=y
-CONFIG_SND_SOC_IMG_I2S_IN=m
-CONFIG_SND_SOC_IMG_I2S_OUT=m
-CONFIG_SND_SOC_IMG_PARALLEL_OUT=m
-CONFIG_SND_SOC_IMG_SPDIF_IN=m
-CONFIG_SND_SOC_IMG_SPDIF_OUT=m
-CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m
-CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y
-CONFIG_SND_SOC_INTEL_AVS=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=m
-CONFIG_SND_SST_IPC=m
-CONFIG_SND_SST_IPC_PCI=m
-CONFIG_SND_SST_IPC_ACPI=m
-CONFIG_SND_SOC_INTEL_SST=m
-CONFIG_SND_SOC_INTEL_CATPT=m
-CONFIG_SND_SST_ATOM_HIFI2_PLATFORM=m
-CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI=m
-CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI=m
-CONFIG_SND_SOC_INTEL_SKYLAKE=m
-CONFIG_SND_SOC_INTEL_SKL=m
-CONFIG_SND_SOC_INTEL_APL=m
-CONFIG_SND_SOC_INTEL_KBL=m
-CONFIG_SND_SOC_INTEL_GLK=m
-CONFIG_SND_SOC_INTEL_CNL=m
-CONFIG_SND_SOC_INTEL_CFL=m
-CONFIG_SND_SOC_INTEL_CML_H=m
-CONFIG_SND_SOC_INTEL_CML_LP=m
-CONFIG_SND_SOC_INTEL_SKYLAKE_FAMILY=m
-CONFIG_SND_SOC_INTEL_SKYLAKE_SSP_CLK=m
-CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC=y
-CONFIG_SND_SOC_INTEL_AVS=m
-CONFIG_SND_SOC_INTEL_SKYLAKE_COMMON=m
-CONFIG_SND_SOC_ACPI_INTEL_MATCH=m
-CONFIG_SND_SOC_INTEL_MACH=y
-# CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES is not set
-CONFIG_SND_SOC_INTEL_HASWELL_MACH=m
-CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH=m
-CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=m
-CONFIG_SND_SOC_INTEL_BROADWELL_MACH=m
-CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=m
-CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH=m
-CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH=m
-CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=m
-CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH=m
-CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH=m
-CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH=m
-CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH=m
-CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH=m
-CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH=m
-CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH=m
-CONFIG_SND_SOC_INTEL_SKL_RT286_MACH=m
-CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH=m
-CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_DA7219_MAX98357A_GENERIC=m
-CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_COMMON=m
-CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_BXT_RT298_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98927_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_RT5660_MACH=m
-CONFIG_SND_SOC_INTEL_GLK_DA7219_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_GLK_RT5682_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_CS42L42_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_ES8336_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_NAU8825_MACH=m
-CONFIG_SND_SOC_INTEL_CML_LP_DA7219_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_CML_RT1011_RT5682_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_DA7219_MAX98373_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_SSP_AMP_MACH=m
-CONFIG_SND_SOC_INTEL_EHL_RT5660_MACH=m
-CONFIG_SND_SOC_MTK_BTCVSD=m
-CONFIG_SND_SOC_MT8192=m
-CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682=m
-CONFIG_SND_SOC_SOF_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_PCI=m
-CONFIG_SND_SOC_SOF_ACPI=m
-# CONFIG_SND_SOC_SOF_DEBUG_PROBES is not set
-# CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT is not set
-CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m
-CONFIG_SND_SOC_SOF_AMD_RENOIR=m
-CONFIG_SND_SOC_SOF_AMD_REMBRANDT=m
-CONFIG_SND_SOC_SOF=m
-CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE=y
-CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_BAYTRAIL=m
-CONFIG_SND_SOC_SOF_BAYTRAIL_SUPPORT=y
-CONFIG_SND_SOC_SOF_INTEL_ACPI=m
-CONFIG_SND_SOC_SOF_INTEL_PCI=m
-CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC=m
-CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP=m
-CONFIG_SND_SOC_SOF_INTEL_COMMON=m
-CONFIG_SND_SOC_SOF_BROADWELL_SUPPORT=y
-CONFIG_SND_SOC_SOF_BROADWELL=m
-CONFIG_SND_SOC_SOF_MERRIFIELD_SUPPORT=y
-CONFIG_SND_SOC_SOF_MERRIFIELD=m
-CONFIG_SND_SOC_SOF_SKYLAKE=m
-CONFIG_SND_SOC_SOF_KABYLAKE=m
-CONFIG_SND_SOC_SOF_APOLLOLAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_APOLLOLAKE=m
-CONFIG_SND_SOC_SOF_GEMINILAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_GEMINILAKE=m
-CONFIG_SND_SOC_SOF_CANNONLAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_CANNONLAKE=m
-CONFIG_SND_SOC_SOF_COFFEELAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_COFFEELAKE=m
-CONFIG_SND_SOC_SOF_ICELAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_ICELAKE=m
-CONFIG_SND_SOC_SOF_COMETLAKE=m
-CONFIG_SND_SOC_SOF_COMETLAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_COMETLAKE_LP_SUPPORT=y
-CONFIG_SND_SOC_SOF_TIGERLAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_TIGERLAKE=m
-CONFIG_SND_SOC_SOF_ELKHARTLAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_ELKHARTLAKE=m
-CONFIG_SND_SOC_SOF_ALDERLAKE=m
-CONFIG_SND_SOC_SOF_METEORLAKE=m
-CONFIG_SND_SOC_SOF_JASPERLAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_JASPERLAKE=m
-CONFIG_SND_SOC_SOF_ALDERLAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_HDA_COMMON=m
-CONFIG_SND_SOC_SOF_HDA_LINK=y
-CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC=y
-CONFIG_SND_SOC_SOF_HDA_ALWAYS_ENABLE_DMI_L1=y
-CONFIG_SND_SOC_SOF_HDA_LINK_BASELINE=m
-CONFIG_SND_SOC_SOF_HDA=m
-CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK=y
-CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE=m
-CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE=m
-CONFIG_SND_SOC_SOF_XTENSA=m
-
-#
-# STMicroelectronics STM32 SOC audio support
-#
-# end of STMicroelectronics STM32 SOC audio support
-
-CONFIG_SND_SOC_XILINX_I2S=m
-CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
-CONFIG_SND_SOC_XILINX_SPDIF=m
-CONFIG_SND_SOC_XTFPGA_I2S=m
-CONFIG_ZX_TDM=m
-CONFIG_SND_SOC_I2C_AND_SPI=m
-
-#
-# CODEC drivers
-#
-CONFIG_SND_SOC_AC97_CODEC=m
-CONFIG_SND_SOC_ADAU1372_I2C=m
-CONFIG_SND_SOC_ADAU1372_SPI=m
-CONFIG_SND_SOC_ADAU_UTILS=m
-CONFIG_SND_SOC_ADAU1701=m
-CONFIG_SND_SOC_ADAU17X1=m
-CONFIG_SND_SOC_ADAU1761=m
-CONFIG_SND_SOC_ADAU1761_I2C=m
-CONFIG_SND_SOC_ADAU1761_SPI=m
-CONFIG_SND_SOC_ADAU7002=m
-CONFIG_SND_SOC_ADAU7118=m
-CONFIG_SND_SOC_ADAU7118_HW=m
-CONFIG_SND_SOC_ADAU7118_I2C=m
-CONFIG_SND_SOC_AK4104=m
-CONFIG_SND_SOC_AK4118=m
-CONFIG_SND_SOC_AK4458=m
-CONFIG_SND_SOC_AK4554=m
-CONFIG_SND_SOC_AK4613=m
-CONFIG_SND_SOC_AK4642=m
-CONFIG_SND_SOC_AK5386=m
-CONFIG_SND_SOC_AK5558=m
-CONFIG_SND_SOC_ALC5623=m
-CONFIG_SND_SOC_AW8738=m
-CONFIG_SND_SOC_BD28623=m
-# CONFIG_SND_SOC_BT_SCO is not set
-CONFIG_SND_SOC_CROS_EC_CODEC=m
-CONFIG_SND_SOC_CS35L32=m
-CONFIG_SND_SOC_CS35L33=m
-CONFIG_SND_SOC_CS35L34=m
-CONFIG_SND_SOC_CS35L35=m
-CONFIG_SND_SOC_CS35L36=m
-CONFIG_SND_SOC_CS42L42=m
-CONFIG_SND_SOC_CS42L51=m
-CONFIG_SND_SOC_CS42L51_I2C=m
-CONFIG_SND_SOC_CS42L52=m
-CONFIG_SND_SOC_CS42L56=m
-CONFIG_SND_SOC_CS42L73=m
-CONFIG_SND_SOC_CS42L83=m
-CONFIG_SND_SOC_CS4234=m
-CONFIG_SND_SOC_CS4265=m
-CONFIG_SND_SOC_CS4270=m
-CONFIG_SND_SOC_CS4271=m
-CONFIG_SND_SOC_CS4271_I2C=m
-CONFIG_SND_SOC_CS4271_SPI=m
-CONFIG_SND_SOC_CS42XX8=m
-CONFIG_SND_SOC_CS42XX8_I2C=m
-CONFIG_SND_SOC_CS43130=m
-CONFIG_SND_SOC_CS4341=m
-CONFIG_SND_SOC_CS4349=m
-CONFIG_SND_SOC_CS53L30=m
-CONFIG_SND_SOC_CX2072X=m
-CONFIG_SND_SOC_DA7213=m
-CONFIG_SND_SOC_DA7219=m
-CONFIG_SND_SOC_DMIC=m
-CONFIG_SND_SOC_HDMI_CODEC=m
-CONFIG_SND_SOC_ES7134=m
-CONFIG_SND_SOC_ES7241=m
-CONFIG_SND_SOC_ES8316=m
-CONFIG_SND_SOC_ES8326=m
-CONFIG_SND_SOC_ES8328=m
-CONFIG_SND_SOC_ES8328_I2C=m
-CONFIG_SND_SOC_ES8328_SPI=m
-CONFIG_SND_SOC_GTM601=m
-CONFIG_SND_SOC_HDA=m
-CONFIG_SND_SOC_HDAC_HDMI=m
-CONFIG_SND_SOC_HDAC_HDA=m
-CONFIG_SND_SOC_INNO_RK3036=m
-CONFIG_SND_SOC_MAX98088=m
-CONFIG_SND_SOC_MAX98090=m
-CONFIG_SND_SOC_MAX98357A=m
-CONFIG_SND_SOC_MAX98504=m
-CONFIG_SND_SOC_MAX9867=m
-CONFIG_SND_SOC_MAX98927=m
-CONFIG_SND_SOC_MAX98373=m
-CONFIG_SND_SOC_MAX98373_I2C=m
-CONFIG_SND_SOC_MAX98373_SDW=m
-CONFIG_SND_SOC_MAX98390=m
-CONFIG_SND_SOC_MAX9860=m
-CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
-CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
-CONFIG_SND_SOC_PCM1681=m
-CONFIG_SND_SOC_PCM1789=m
-CONFIG_SND_SOC_PCM1789_I2C=m
-CONFIG_SND_SOC_PCM179X=m
-CONFIG_SND_SOC_PCM179X_I2C=m
-CONFIG_SND_SOC_PCM179X_SPI=m
-CONFIG_SND_SOC_PCM186X=m
-CONFIG_SND_SOC_PCM186X_I2C=m
-CONFIG_SND_SOC_PCM186X_SPI=m
-CONFIG_SND_SOC_PCM3060=m
-CONFIG_SND_SOC_PCM3060_I2C=m
-CONFIG_SND_SOC_PCM3060_SPI=m
-CONFIG_SND_SOC_PCM3168A=m
-CONFIG_SND_SOC_PCM3168A_I2C=m
-CONFIG_SND_SOC_PCM3168A_SPI=m
-CONFIG_SND_SOC_PCM5102A=m
-CONFIG_SND_SOC_PCM512x=m
-CONFIG_SND_SOC_PCM512x_I2C=m
-CONFIG_SND_SOC_PCM512x_SPI=m
-CONFIG_SND_SOC_RK3328=m
-CONFIG_SND_SOC_RK817=m
-CONFIG_SND_SOC_RL6231=m
-CONFIG_SND_SOC_RL6347A=m
-CONFIG_SND_SOC_RT286=m
-CONFIG_SND_SOC_RT298=m
-CONFIG_SND_SOC_RT1011=m
-CONFIG_SND_SOC_RT1015=m
-CONFIG_SND_SOC_RT1308_SDW=m
-CONFIG_SND_SOC_RT1316_SDW=m
-CONFIG_SND_SOC_RT5514=m
-CONFIG_SND_SOC_RT5514_SPI=m
-CONFIG_SND_SOC_RT5616=m
-CONFIG_SND_SOC_RT5631=m
-CONFIG_SND_SOC_RT5640=m
-CONFIG_SND_SOC_RT5659=m
-CONFIG_SND_SOC_RT5640=m
-CONFIG_SND_SOC_RT5645=m
-CONFIG_SND_SOC_RT5651=m
-CONFIG_SND_SOC_RT5660=m
-CONFIG_SND_SOC_RT5663=m
-CONFIG_SND_SOC_RT5670=m
-CONFIG_SND_SOC_RT5677=m
-CONFIG_SND_SOC_RT5677_SPI=m
-CONFIG_SND_SOC_RT5682=m
-CONFIG_SND_SOC_RT5682_I2C=m
-CONFIG_SND_SOC_RT5682_SDW=m
-CONFIG_SND_SOC_RT700=m
-CONFIG_SND_SOC_RT700_SDW=m
-CONFIG_SND_SOC_RT711=m
-CONFIG_SND_SOC_RT711_SDW=m
-CONFIG_SND_SOC_RT711_SDCA_SDW=m
-CONFIG_SND_SOC_RT715=m
-CONFIG_SND_SOC_RT715_SDW=m
-CONFIG_SND_SOC_RT715_SDCA_SDW=m
-CONFIG_SND_SOC_SGTL5000=m
-CONFIG_SND_SOC_SI476X=m
-CONFIG_SND_SOC_SIGMADSP=m
-CONFIG_SND_SOC_SIGMADSP_I2C=m
-CONFIG_SND_SOC_SIGMADSP_REGMAP=m
-CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
-CONFIG_SND_SOC_SIMPLE_MUX=m
-CONFIG_SND_SOC_SIRF_AUDIO_CODEC=m
-CONFIG_SND_SOC_SPDIF=m
-CONFIG_SND_SOC_SRC4XXX_I2C=m
-CONFIG_SND_SOC_SSM2305=m
-CONFIG_SND_SOC_SSM2518=m
-CONFIG_SND_SOC_SSM2602=m
-CONFIG_SND_SOC_SSM2602_SPI=m
-CONFIG_SND_SOC_SSM2602_I2C=m
-CONFIG_SND_SOC_SSM4567=m
-CONFIG_SND_SOC_STA32X=m
-CONFIG_SND_SOC_STA350=m
-CONFIG_SND_SOC_STI_SAS=m
-CONFIG_SND_SOC_TAS2552=m
-CONFIG_SND_SOC_TAS2562=m
-CONFIG_SND_SOC_TAS2764=m
-CONFIG_SND_SOC_TAS2770=m
-CONFIG_SND_SOC_TAS2780=m
-CONFIG_SND_SOC_WSA883X=m
-CONFIG_SND_SOC_TAS5086=m
-CONFIG_SND_SOC_TAS571X=m
-CONFIG_SND_SOC_TAS5720=m
-CONFIG_SND_SOC_TAS5805M=m
-CONFIG_SND_SOC_TAS6424=m
-CONFIG_SND_SOC_TDA7419=m
-CONFIG_SND_SOC_TFA9879=m
-CONFIG_SND_SOC_TFA989X=m
-CONFIG_SND_SOC_TLV320AIC23=m
-CONFIG_SND_SOC_TLV320AIC23_I2C=m
-CONFIG_SND_SOC_TLV320AIC23_SPI=m
-CONFIG_SND_SOC_TLV320AIC31XX=m
-CONFIG_SND_SOC_TLV320AIC32X4=m
-CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
-CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
-CONFIG_SND_SOC_TLV320AIC3X_I2C=m
-CONFIG_SND_SOC_TLV320AIC3X_SPI=m
-CONFIG_SND_SOC_TLV320AIC3X=m
-CONFIG_SND_SOC_TLV320ADCX140=m
-CONFIG_SND_SOC_TS3A227E=m
-CONFIG_SND_SOC_TSCS42XX=m
-CONFIG_SND_SOC_TSCS454=m
-CONFIG_SND_SOC_UDA1334=m
-CONFIG_SND_SOC_WCD938X_SDW=m
-CONFIG_SND_SOC_WCD9335=m
-CONFIG_SND_SOC_WCD934X=m
-CONFIG_SND_SOC_WCD938X_SDW=m
-CONFIG_SND_SOC_WM8510=m
-CONFIG_SND_SOC_WM8523=m
-CONFIG_SND_SOC_WM8524=m
-CONFIG_SND_SOC_WM8580=m
-CONFIG_SND_SOC_WM8711=m
-CONFIG_SND_SOC_WM8728=m
-CONFIG_SND_SOC_WM8731=m
-CONFIG_SND_SOC_WM8737=m
-CONFIG_SND_SOC_WM8741=m
-CONFIG_SND_SOC_WM8750=m
-CONFIG_SND_SOC_WM8753=m
-CONFIG_SND_SOC_WM8770=m
-CONFIG_SND_SOC_WM8776=m
-CONFIG_SND_SOC_WM8782=m
-CONFIG_SND_SOC_WM8804=m
-CONFIG_SND_SOC_WM8804_I2C=m
-CONFIG_SND_SOC_WM8804_SPI=m
-CONFIG_SND_SOC_WM8903=m
-CONFIG_SND_SOC_WM8904=m
-CONFIG_SND_SOC_WM8960=m
-CONFIG_SND_SOC_WM8962=m
-CONFIG_SND_SOC_WM8974=m
-CONFIG_SND_SOC_WM8978=m
-CONFIG_SND_SOC_WM8985=m
-CONFIG_SND_SOC_WSA881X=m
-CONFIG_SND_SOC_ZL38060=m
-CONFIG_SND_SOC_ZX_AUD96P22=m
-CONFIG_SND_SOC_MAX9759=m
-CONFIG_SND_SOC_MT6351=m
-CONFIG_SND_SOC_MT6358=m
-CONFIG_SND_SOC_MT6660=m
-CONFIG_SND_SOC_NAU8315=m
-CONFIG_SND_SOC_NAU8540=m
-CONFIG_SND_SOC_NAU8810=m
-CONFIG_SND_SOC_NAU8822=m
-CONFIG_SND_SOC_NAU8824=m
-CONFIG_SND_SOC_NAU8825=m
-CONFIG_SND_SOC_TPA6130A2=m
-CONFIG_SND_SOC_LPASS_WSA_MACRO=m
-CONFIG_SND_SOC_LPASS_VA_MACRO=m
-CONFIG_SND_SOC_LPASS_RX_MACRO=m
-CONFIG_SND_SOC_LPASS_TX_MACRO=m
-# end of CODEC drivers
-
-CONFIG_SND_SIMPLE_CARD_UTILS=m
-CONFIG_SND_SIMPLE_CARD=m
-CONFIG_SND_X86=y
-CONFIG_HDMI_LPE_AUDIO=m
-CONFIG_SND_SYNTH_EMUX=m
-CONFIG_AC97_BUS=m
-
-#
-# HID support
-#
-CONFIG_HID=m
-CONFIG_HID_BATTERY_STRENGTH=y
-CONFIG_HIDRAW=y
-CONFIG_UHID=m
-CONFIG_HID_GENERIC=m
-
-#
-# Special HID drivers
-#
-CONFIG_HID_A4TECH=m
-CONFIG_HID_ACCUTOUCH=m
-CONFIG_HID_ACRUX=m
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=m
-CONFIG_HID_APPLEIR=m
-CONFIG_HID_ASUS=m
-CONFIG_HID_AUREAL=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_BETOP_FF=m
-CONFIG_HID_BIGBEN_FF=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CORSAIR=m
-CONFIG_HID_COUGAR=m
-CONFIG_HID_MACALLY=m
-CONFIG_HID_PRODIKEYS=m
-CONFIG_HID_CMEDIA=m
-CONFIG_HID_CP2112=m
-CONFIG_HID_CREATIVE_SB0540=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_DRAGONRISE=m
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=m
-CONFIG_HID_ELAN=m
-CONFIG_HID_ELECOM=m
-CONFIG_HID_ELO=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_FT260=m
-CONFIG_HID_GEMBIRD=m
-CONFIG_HID_GFRM=m
-CONFIG_HID_GLORIOUS=m
-CONFIG_HID_HOLTEK=m
-CONFIG_HOLTEK_FF=y
-CONFIG_HID_GOOGLE_HAMMER=m
-CONFIG_HID_VIVALDI=m
-CONFIG_HID_GT683R=m
-CONFIG_HID_KEYTOUCH=m
-CONFIG_HID_KYE=m
-CONFIG_HID_UCLOGIC=m
-CONFIG_HID_WALTOP=m
-CONFIG_HID_VIEWSONIC=m
-CONFIG_HID_VRC2=m
-CONFIG_HID_GYRATION=m
-CONFIG_HID_ICADE=m
-CONFIG_HID_ITE=m
-CONFIG_HID_JABRA=m
-CONFIG_HID_TWINHAN=m
-CONFIG_HID_KENSINGTON=m
-CONFIG_HID_LCPOWER=m
-CONFIG_HID_LED=m
-CONFIG_HID_LENOVO=m
-CONFIG_HID_LOGITECH=m
-CONFIG_HID_LOGITECH_DJ=m
-CONFIG_HID_LOGITECH_HIDPP=m
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWHEELS_FF=y
-CONFIG_HID_MAGICMOUSE=m
-CONFIG_HID_MALTRON=m
-CONFIG_HID_MAYFLASH=m
-CONFIG_HID_REDRAGON=m
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_MULTITOUCH=m
-CONFIG_HID_NTI=m
-CONFIG_HID_NTRIG=m
-CONFIG_HID_ORTEK=m
-CONFIG_HID_PANTHERLORD=m
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PENMOUNT=m
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_PICOLCD=m
-# CONFIG_HID_PICOLCD_FB is not set
-# CONFIG_HID_PICOLCD_BACKLIGHT is not set
-# CONFIG_HID_PICOLCD_LCD is not set
-# CONFIG_HID_PICOLCD_LEDS is not set
-# CONFIG_HID_PICOLCD_CIR is not set
-CONFIG_HID_PLANTRONICS=m
-CONFIG_HID_PLAYSTATION=m
-CONFIG_HID_PXRC=m
-CONFIG_HID_RAZER=m
-CONFIG_PLAYSTATION_FF=y
-CONFIG_HID_PRIMAX=m
-CONFIG_HID_RETRODE=m
-CONFIG_HID_ROCCAT=m
-CONFIG_HID_SAITEK=m
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SEMITEK=m
-CONFIG_HID_SIGMAMICRO=m
-CONFIG_HID_SONY=m
-CONFIG_SONY_FF=y
-CONFIG_HID_SPEEDLINK=m
-CONFIG_HID_STEAM=m
-CONFIG_HID_STEELSERIES=m
-CONFIG_HID_SUNPLUS=m
-CONFIG_HID_RMI=m
-CONFIG_HID_GREENASIA=m
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_HYPERV_MOUSE=m
-CONFIG_HID_SMARTJOYPLUS=m
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TIVO=m
-CONFIG_HID_TOPSEED=m
-CONFIG_HID_TOPRE=m
-CONFIG_HID_THINGM=m
-CONFIG_HID_THRUSTMASTER=m
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_UDRAW_PS3=m
-CONFIG_HID_U2FZERO=m
-CONFIG_HID_WACOM=m
-CONFIG_HID_WIIMOTE=m
-CONFIG_HID_XINMO=m
-CONFIG_HID_ZEROPLUS=m
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=m
-CONFIG_HID_SENSOR_HUB=m
-CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
-CONFIG_HID_ALPS=m
-CONFIG_HID_MCP2221=m
-# end of Special HID drivers
-
-#
-# USB HID support
-#
-CONFIG_USB_HID=m
-CONFIG_HID_PID=y
-CONFIG_USB_HIDDEV=y
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# end of USB HID Boot Protocol drivers
-# end of USB HID support
-
-#
-# I2C HID support
-#
-CONFIG_I2C_HID=m
-CONFIG_I2C_HID_OF=m
-CONFIG_I2C_HID_OF_ELAN=m
-CONFIG_USB_ONBOARD_HUB=m
-CONFIG_I2C_HID_OF_GOODIX=m
-CONFIG_I2C_HID_ACPI=m
-# end of I2C HID support
-# end of HID support
-
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_LED_TRIG=y
-CONFIG_USB_ULPI_BUS=m
-CONFIG_USB_CONN_GPIO=m
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB=m
-CONFIG_USB_PCI=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEFAULT_PERSIST=y
-CONFIG_USB_FEW_INIT_RETRIES=y
-CONFIG_USB_DYNAMIC_MINORS=y
-CONFIG_USB_OTG=y
-# CONFIG_USB_OTG_PRODUCTLIST is not set
-# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
-CONFIG_USB_OTG_FSM=m
-CONFIG_USB_LEDS_TRIGGER_USBPORT=m
-CONFIG_USB_AUTOSUSPEND_DELAY=2
-CONFIG_USB_MON=m
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_C67X00_HCD=m
-CONFIG_USB_XHCI_HCD=m
-CONFIG_USB_XHCI_DBGCAP=y
-CONFIG_USB_XHCI_PCI=m
-CONFIG_USB_XHCI_PCI_RENESAS=m
-CONFIG_USB_XHCI_PLATFORM=m
-CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-CONFIG_USB_EHCI_PCI=m
-CONFIG_USB_EHCI_FSL=m
-CONFIG_USB_EHCI_HCD_NPCM7XX=m
-CONFIG_USB_EHCI_HCD_PLATFORM=m
-CONFIG_USB_OXU210HP_HCD=m
-CONFIG_USB_ISP116X_HCD=m
-CONFIG_USB_FOTG210_HCD=m
-CONFIG_USB_MAX3421_HCD=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_OHCI_HCD_PCI=m
-CONFIG_USB_OHCI_HCD_SSB=y
-CONFIG_USB_OHCI_HCD_PLATFORM=m
-CONFIG_USB_UHCI_HCD=m
-CONFIG_USB_U132_HCD=m
-CONFIG_USB_SL811_HCD=m
-# CONFIG_USB_SL811_HCD_ISO is not set
-CONFIG_USB_SL811_CS=m
-CONFIG_USB_R8A66597_HCD=m
-CONFIG_USB_HCD_BCMA=m
-CONFIG_USB_HCD_SSB=m
-# CONFIG_USB_HCD_TEST_MODE is not set
-
-#
-# USB Device Class drivers
-#
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_WDM=m
-CONFIG_USB_TMC=m
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-CONFIG_USB_STORAGE_REALTEK=m
-CONFIG_REALTEK_AUTOPM=y
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_ISD200=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_STORAGE_ALAUDA=m
-CONFIG_USB_STORAGE_ONETOUCH=m
-CONFIG_USB_STORAGE_KARMA=m
-CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-CONFIG_USB_STORAGE_ENE_UB6250=m
-CONFIG_USB_UAS=m
-
-#
-# USB Imaging devices
-#
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USBIP_CORE=m
-CONFIG_USBIP_VHCI_HCD=m
-CONFIG_USBIP_VHCI_HC_PORTS=8
-CONFIG_USBIP_VHCI_NR_HCS=1
-CONFIG_USBIP_HOST=m
-CONFIG_USBIP_VUDC=m
-# CONFIG_USBIP_DEBUG is not set
-CONFIG_USB_CDNS_SUPPORT=m
-CONFIG_USB_CDNS3=m
-CONFIG_USB_CDNSP_PCI=m
-CONFIG_USB_CDNSP_GADGET=y
-CONFIG_USB_CDNSP_HOST=y
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_USB_CDNS3_HOST=y
-CONFIG_USB_CDNS3_PCI_WRAP=m
-CONFIG_USB_MUSB_HDRC=m
-# CONFIG_USB_MUSB_HOST is not set
-# CONFIG_USB_MUSB_GADGET is not set
-CONFIG_USB_MUSB_DUAL_ROLE=y
-
-#
-# Platform Glue Layer
-#
-
-#
-# MUSB DMA mode
-#
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_DWC3=m
-# CONFIG_USB_DWC3_ULPI is not set
-# CONFIG_USB_DWC3_HOST is not set
-# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_DUAL_ROLE=y
-
-#
-# Platform Glue Driver Support
-#
-CONFIG_USB_DWC3_PCI=m
-CONFIG_USB_DWC3_HAPS=m
-CONFIG_USB_DWC2=m
-# CONFIG_USB_DWC2_HOST is not set
-
-#
-# Gadget/Dual-role mode requires USB Gadget support to be enabled
-#
-# CONFIG_USB_DWC2_PERIPHERAL is not set
-CONFIG_USB_DWC2_DUAL_ROLE=y
-CONFIG_USB_DWC2_PCI=m
-# CONFIG_USB_DWC2_DEBUG is not set
-# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
-CONFIG_USB_CHIPIDEA=m
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_PCI=m
-CONFIG_USB_CHIPIDEA_MSM=m
-CONFIG_USB_CHIPIDEA_GENERIC=m
-CONFIG_USB_ISP1760=m
-CONFIG_USB_ISP1760_HCD=y
-CONFIG_USB_ISP1761_UDC=y
-# CONFIG_USB_ISP1760_HOST_ROLE is not set
-# CONFIG_USB_ISP1760_GADGET_ROLE is not set
-CONFIG_USB_ISP1760_DUAL_ROLE=y
-
-#
-# USB port drivers
-#
-CONFIG_USB_USS720=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_SIMPLE=m
-CONFIG_USB_SERIAL_AIRCABLE=m
-CONFIG_USB_SERIAL_ARK3116=m
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_CH341=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CP210X=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_F81232=m
-CONFIG_USB_SERIAL_F8153X=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_IUU=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_METRO=m
-CONFIG_USB_SERIAL_MOS7720=m
-CONFIG_USB_SERIAL_MOS7715_PARPORT=y
-CONFIG_USB_SERIAL_MOS7840=m
-CONFIG_USB_SERIAL_MXUPORT=m
-CONFIG_USB_SERIAL_NAVMAN=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_OTI6858=m
-CONFIG_USB_SERIAL_QCAUX=m
-CONFIG_USB_SERIAL_QUALCOMM=m
-CONFIG_USB_SERIAL_SPCP8X5=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_SAFE_PADDED=y
-CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-CONFIG_USB_SERIAL_SYMBOL=m
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-CONFIG_USB_SERIAL_WWAN=m
-CONFIG_USB_SERIAL_OPTION=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_SERIAL_OPTICON=m
-CONFIG_USB_SERIAL_XSENS_MT=m
-CONFIG_USB_SERIAL_WISHBONE=m
-CONFIG_USB_SERIAL_SSU100=m
-CONFIG_USB_SERIAL_QT2=m
-# CONFIG_USB_SERIAL_UPD78F0730 is not set
-CONFIG_USB_SERIAL_XR=m
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_ADUTUX=m
-CONFIG_USB_SEVSEG=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_CYPRESS_CY7C63=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_IDMOUSE=m
-CONFIG_USB_FTDI_ELAN=m
-CONFIG_USB_APPLEDISPLAY=m
-CONFIG_USB_QCOM_EUD=m
-CONFIG_APPLE_MFI_FASTCHARGE=m
-CONFIG_USB_SISUSBVGA=m
-CONFIG_USB_SISUSBVGA_CON=y
-CONFIG_USB_LD=m
-CONFIG_USB_TRANCEVIBRATOR=m
-CONFIG_USB_IOWARRIOR=m
-CONFIG_USB_TEST=m
-CONFIG_USB_EHSET_TEST_FIXTURE=m
-CONFIG_USB_ISIGHTFW=m
-CONFIG_USB_YUREX=m
-CONFIG_USB_EZUSB_FX2=m
-CONFIG_USB_HUB_USB251XB=m
-CONFIG_USB_HSIC_USB3503=m
-CONFIG_USB_HSIC_USB4604=m
-CONFIG_USB_LINK_LAYER_TEST=m
-CONFIG_USB_CHAOSKEY=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_CXACRU=m
-CONFIG_USB_UEAGLEATM=m
-CONFIG_USB_XUSBATM=m
-
-#
-# USB Physical Layer drivers
-#
-CONFIG_USB_PHY=y
-CONFIG_NOP_USB_XCEIV=m
-CONFIG_USB_GPIO_VBUS=m
-CONFIG_TAHVO_USB=m
-CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y
-CONFIG_USB_ISP1301=m
-# end of USB Physical Layer drivers
-
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
-CONFIG_U_SERIAL_CONSOLE=y
-
-#
-# USB Peripheral Controller
-#
-CONFIG_USB_FOTG210_UDC=m
-CONFIG_USB_GR_UDC=m
-CONFIG_USB_R8A66597=m
-CONFIG_USB_PXA27X=m
-CONFIG_USB_MV_UDC=m
-CONFIG_USB_MV_U3D=m
-CONFIG_USB_SNP_CORE=m
-CONFIG_USB_M66592=m
-CONFIG_USB_BDC_UDC=m
-
-#
-# Platform Support
-#
-CONFIG_USB_BDC_PCI=m
-CONFIG_USB_AMD5536UDC=m
-CONFIG_USB_NET2272=m
-CONFIG_USB_NET2272_DMA=y
-CONFIG_USB_NET2280=m
-CONFIG_USB_GOKU=m
-CONFIG_USB_EG20T=m
-CONFIG_USB_MAX3420_UDC=m
-# CONFIG_USB_DUMMY_HCD is not set
-# end of USB Peripheral Controller
-
-CONFIG_USB_LIBCOMPOSITE=m
-CONFIG_USB_F_ACM=m
-CONFIG_USB_F_SS_LB=m
-CONFIG_USB_U_SERIAL=m
-CONFIG_USB_U_ETHER=m
-CONFIG_USB_U_AUDIO=m
-CONFIG_USB_F_SERIAL=m
-CONFIG_USB_F_OBEX=m
-CONFIG_USB_F_NCM=m
-CONFIG_USB_F_ECM=m
-CONFIG_USB_F_PHONET=m
-CONFIG_USB_F_EEM=m
-CONFIG_USB_F_SUBSET=m
-CONFIG_USB_F_RNDIS=m
-CONFIG_USB_F_MASS_STORAGE=m
-CONFIG_USB_F_FS=m
-CONFIG_USB_F_UAC1=m
-CONFIG_USB_F_UAC2=m
-CONFIG_USB_F_UVC=m
-CONFIG_USB_F_MIDI=m
-CONFIG_USB_F_HID=m
-CONFIG_USB_F_PRINTER=m
-CONFIG_USB_F_TCM=m
-CONFIG_USB_CONFIGFS=m
-CONFIG_USB_CONFIGFS_SERIAL=y
-CONFIG_USB_CONFIGFS_ACM=y
-CONFIG_USB_CONFIGFS_OBEX=y
-CONFIG_USB_CONFIGFS_NCM=y
-CONFIG_USB_CONFIGFS_ECM=y
-CONFIG_USB_CONFIGFS_ECM_SUBSET=y
-CONFIG_USB_CONFIGFS_RNDIS=y
-CONFIG_USB_CONFIGFS_EEM=y
-CONFIG_USB_CONFIGFS_PHONET=y
-CONFIG_USB_CONFIGFS_MASS_STORAGE=y
-CONFIG_USB_CONFIGFS_F_LB_SS=y
-CONFIG_USB_CONFIGFS_F_FS=y
-CONFIG_USB_CONFIGFS_F_UAC1=y
-# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
-CONFIG_USB_CONFIGFS_F_UAC2=y
-CONFIG_USB_CONFIGFS_F_MIDI=y
-CONFIG_USB_CONFIGFS_F_HID=y
-CONFIG_USB_CONFIGFS_F_UVC=y
-CONFIG_USB_CONFIGFS_F_PRINTER=y
-CONFIG_USB_CONFIGFS_F_TCM=y
-
-#
-# USB Gadget precomposed configurations
-#
-CONFIG_USB_ZERO=m
-CONFIG_USB_ZERO_HNPTEST=y
-CONFIG_USB_AUDIO=m
-CONFIG_GADGET_UAC1=y
-# CONFIG_GADGET_UAC1_LEGACY is not set
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-CONFIG_USB_ETH_EEM=y
-CONFIG_USB_G_NCM=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FUNCTIONFS=m
-CONFIG_USB_FUNCTIONFS_ETH=y
-CONFIG_USB_FUNCTIONFS_RNDIS=y
-CONFIG_USB_FUNCTIONFS_GENERIC=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_GADGET_TARGET=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_MIDI_GADGET=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_NOKIA=m
-CONFIG_USB_G_ACM_MS=m
-CONFIG_USB_G_MULTI=m
-CONFIG_USB_G_MULTI_RNDIS=y
-CONFIG_USB_G_MULTI_CDC=y
-CONFIG_USB_G_HID=m
-# CONFIG_USB_G_DBGP is not set
-CONFIG_USB_G_WEBCAM=m
-CONFIG_USB_RAW_GADGET=m
-# end of USB Gadget precomposed configurations
-
-CONFIG_TYPEC=m
-CONFIG_TYPEC_TCPM=m
-CONFIG_TYPEC_TCPCI=m
-CONFIG_TYPEC_RT1711H=m
-CONFIG_TYPEC_TCPCI_MT6370=m
-CONFIG_TYPEC_MT6360=m
-CONFIG_TYPEC_TCPCI_MT6370=m
-CONFIG_TYPEC_TCPCI_MAXIM=m
-CONFIG_TYPEC_FUSB302=m
-CONFIG_TYPEC_UCSI=m
-CONFIG_UCSI_CCG=m
-CONFIG_UCSI_ACPI=m
-CONFIG_UCSI_STM32G0=m
-CONFIG_TYPEC_HD3SS3220=m
-CONFIG_TYPEC_TPS6598X=m
-CONFIG_TYPEC_ANX7411=m
-CONFIG_TYPEC_RT1719=m
-CONFIG_TYPEC_STUSB160X=m
-CONFIG_TYPEC_WUSB3801=m
-CONFIG_TYPEC_EXTCON=m
-
-#
-# USB Type-C Multiplexer/DeMultiplexer Switch support
-#
-CONFIG_TYPEC_MUX_PI3USB30532=m
-CONFIG_TYPEC_MUX_INTEL_PMC=m
-# end of USB Type-C Multiplexer/DeMultiplexer Switch support
-
-#
-# USB Type-C Alternate Mode drivers
-#
-CONFIG_TYPEC_DP_ALTMODE=m
-CONFIG_TYPEC_NVIDIA_ALTMODE=m
-# end of USB Type-C Alternate Mode drivers
-
-CONFIG_USB_ROLE_SWITCH=m
-CONFIG_USB_ROLES_INTEL_XHCI=m
-CONFIG_MMC=m
-CONFIG_MMC_BLOCK=m
-CONFIG_MMC_BLOCK_MINORS=8
-CONFIG_SDIO_UART=m
-# CONFIG_MMC_TEST is not set
-CONFIG_MMC_CRYPTO=y
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_SDHCI=m
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PCI=m
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI_ACPI=m
-CONFIG_MMC_SDHCI_PLTFM=m
-CONFIG_MMC_SDHCI_F_SDH30=m
-CONFIG_MMC_WBSD=m
-CONFIG_MMC_ALCOR=m
-CONFIG_MMC_TIFM_SD=m
-CONFIG_MMC_SPI=m
-CONFIG_MMC_SDRICOH_CS=m
-CONFIG_MMC_CB710=m
-CONFIG_MMC_VIA_SDMMC=m
-CONFIG_MMC_VUB300=m
-CONFIG_MMC_USHC=m
-CONFIG_MMC_USDHI6ROL0=m
-CONFIG_MMC_REALTEK_PCI=m
-CONFIG_MMC_REALTEK_USB=m
-CONFIG_MMC_CQHCI=m
-CONFIG_MMC_HSQ=m
-# CONFIG_MMC_TOSHIBA_PCI is not set
-CONFIG_MMC_MTK=m
-CONFIG_MMC_SDHCI_XENON=m
-CONFIG_MEMSTICK=m
-# CONFIG_MEMSTICK_DEBUG is not set
-
-#
-# MemoryStick drivers
-#
-# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
-CONFIG_MSPRO_BLOCK=m
-CONFIG_MS_BLOCK=m
-
-#
-# MemoryStick Host Controller Drivers
-#
-CONFIG_MEMSTICK_TIFM_MS=m
-CONFIG_MEMSTICK_JMICRON_38X=m
-CONFIG_MEMSTICK_R592=m
-CONFIG_MEMSTICK_REALTEK_PCI=m
-CONFIG_MEMSTICK_REALTEK_USB=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_RT4505=m
-CONFIG_LEDS_CLASS_FLASH=m
-CONFIG_LEDS_CLASS_MULTICOLOR=m
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-
-#
-# LED drivers
-#
-CONFIG_LEDS_APU=m
-CONFIG_LEDS_AS3645A=m
-CONFIG_LEDS_LM3530=m
-CONFIG_LEDS_LM3532=m
-CONFIG_LEDS_LM3533=m
-CONFIG_LEDS_LM3642=m
-CONFIG_LEDS_LM3601X=m
-CONFIG_LEDS_MT6323=m
-CONFIG_LEDS_PCA9532=m
-CONFIG_LEDS_PCA9532_GPIO=y
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_LP3944=m
-CONFIG_LEDS_LP3952=m
-CONFIG_LEDS_LP50XX=m
-CONFIG_LEDS_CLEVO_MAIL=m
-CONFIG_LEDS_PCA955X=m
-# CONFIG_LEDS_PCA955X_GPIO is not set
-CONFIG_LEDS_PCA963X=m
-CONFIG_LEDS_WM831X_STATUS=m
-CONFIG_LEDS_DA9052=m
-CONFIG_LEDS_DAC124S085=m
-CONFIG_LEDS_PWM=m
-CONFIG_LEDS_REGULATOR=m
-CONFIG_LEDS_BD2802=m
-CONFIG_LEDS_INTEL_SS4200=m
-CONFIG_LEDS_LT3593=m
-CONFIG_LEDS_MC13783=m
-CONFIG_LEDS_TCA6507=m
-CONFIG_LEDS_TLC591XX=m
-CONFIG_LEDS_LM355x=m
-# CONFIG_LEDS_OT200 is not set
-CONFIG_LEDS_MENF21BMC=m
-CONFIG_LEDS_IS31FL319X=m
-CONFIG_LEDS_RT8515=m
-
-#
-# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
-#
-CONFIG_LEDS_BLINKM=m
-CONFIG_LEDS_MLXCPLD=m
-CONFIG_LEDS_MLXREG=m
-CONFIG_LEDS_USER=m
-CONFIG_LEDS_NIC78BX=m
-CONFIG_LEDS_TI_LMU_COMMON=m
-CONFIG_LEDS_BCM63138=m
-CONFIG_LEDS_LM36274=m
-CONFIG_LEDS_TPS6105X=m
-CONFIG_LEDS_SGM3140=m
-CONFIG_LEDS_SIEMENS_SIMATIC_IPC=m
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_ONESHOT=m
-CONFIG_LEDS_TRIGGER_DISK=y
-# CONFIG_LEDS_TRIGGER_MTD is not set
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_LEDS_TRIGGER_BACKLIGHT=m
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_ACTIVITY=m
-CONFIG_LEDS_TRIGGER_GPIO=m
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-CONFIG_LEDS_TRIGGER_TRANSIENT=m
-CONFIG_LEDS_TRIGGER_CAMERA=m
-CONFIG_LEDS_TRIGGER_PANIC=y
-CONFIG_LEDS_TRIGGER_NETDEV=m
-CONFIG_LEDS_TRIGGER_PATTERN=m
-CONFIG_LEDS_TRIGGER_AUDIO=m
-CONFIG_LEDS_TRIGGER_TTY=m
-CONFIG_LEDS_BLINK=y
-CONFIG_LEDS_BLINK_LGM=m
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_A11Y_BRAILLE_CONSOLE=y
-
-#
-# Speakup console speech
-#
-CONFIG_SPEAKUP=m
-CONFIG_SPEAKUP_SERIALIO=y
-CONFIG_SPEAKUP_SYNTH_ACNTSA=m
-# CONFIG_SPEAKUP_SYNTH_ACNTPC is not set
-CONFIG_SPEAKUP_SYNTH_APOLLO=m
-CONFIG_SPEAKUP_SYNTH_AUDPTR=m
-CONFIG_SPEAKUP_SYNTH_BNS=m
-CONFIG_SPEAKUP_SYNTH_DECTLK=m
-CONFIG_SPEAKUP_SYNTH_DECEXT=m
-# CONFIG_SPEAKUP_SYNTH_DECPC is not set
-# CONFIG_SPEAKUP_SYNTH_DTLK is not set
-# CONFIG_SPEAKUP_SYNTH_KEYPC is not set
-CONFIG_SPEAKUP_SYNTH_LTLK=m
-CONFIG_SPEAKUP_SYNTH_SOFT=m
-CONFIG_SPEAKUP_SYNTH_SPKOUT=m
-CONFIG_SPEAKUP_SYNTH_TXPRT=m
-# CONFIG_SPEAKUP_SYNTH_DUMMY is not set
-# end of Speakup console speech
-
-CONFIG_INFINIBAND=m
-CONFIG_INFINIBAND_USER_MAD=m
-CONFIG_INFINIBAND_USER_ACCESS=m
-CONFIG_INFINIBAND_USER_MEM=y
-CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
-CONFIG_INFINIBAND_ADDR_TRANS=y
-CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
-CONFIG_INFINIBAND_MTHCA=m
-# CONFIG_INFINIBAND_MTHCA_DEBUG is not set
-CONFIG_INFINIBAND_CXGB4=m
-CONFIG_INFINIBAND_IRDMA=m
-CONFIG_INFINIBAND_I40IW=m
-CONFIG_MLX4_INFINIBAND=m
-CONFIG_MLX5_INFINIBAND=m
-CONFIG_INFINIBAND_OCRDMA=m
-CONFIG_INFINIBAND_VMWARE_PVRDMA=m
-CONFIG_INFINIBAND_USNIC=m
-CONFIG_RDMA_RXE=m
-CONFIG_RDMA_SIW=m
-CONFIG_INFINIBAND_IPOIB=m
-CONFIG_INFINIBAND_IPOIB_CM=y
-# CONFIG_INFINIBAND_IPOIB_DEBUG is not set
-# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set
-CONFIG_INFINIBAND_SRP=m
-CONFIG_INFINIBAND_SRPT=m
-CONFIG_INFINIBAND_ISER=m
-CONFIG_INFINIBAND_ISERT=m
-CONFIG_INFINIBAND_RTRS=m
-CONFIG_INFINIBAND_RTRS_CLIENT=m
-CONFIG_INFINIBAND_RTRS_SERVER=m
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EDAC=m
-CONFIG_EDAC_LEGACY_SYSFS=y
-# CONFIG_EDAC_DEBUG is not set
-CONFIG_EDAC_DECODE_MCE=m
-CONFIG_EDAC_GHES=y
-CONFIG_EDAC_AMD64=m
-CONFIG_EDAC_AMD64_ERROR_INJECTION=y
-# CONFIG_EDAC_AMD76X is not set
-# CONFIG_EDAC_E7XXX is not set
-CONFIG_EDAC_E752X=m
-# CONFIG_EDAC_I82875P is not set
-CONFIG_EDAC_I82975X=m
-CONFIG_EDAC_I3000=m
-CONFIG_EDAC_I3200=m
-CONFIG_EDAC_IE31200=m
-CONFIG_EDAC_X38=m
-CONFIG_EDAC_I5400=m
-CONFIG_EDAC_I7CORE=m
-# CONFIG_EDAC_I82860 is not set
-# CONFIG_EDAC_R82600 is not set
-CONFIG_EDAC_I5000=m
-CONFIG_EDAC_I5100=m
-CONFIG_EDAC_I7300=m
-CONFIG_RTC_LIB=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-CONFIG_RTC_SYSTOHC=y
-CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-CONFIG_RTC_NVMEM=y
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-CONFIG_RTC_DRV_88PM80X=m
-CONFIG_RTC_DRV_ABB5ZES3=m
-CONFIG_RTC_DRV_ABEOZ9=m
-CONFIG_RTC_DRV_ABX80X=m
-CONFIG_RTC_DRV_DS1307=m
-# CONFIG_RTC_DRV_DS1307_CENTURY is not set
-CONFIG_RTC_DRV_DS1374=m
-CONFIG_RTC_DRV_DS1374_WDT=y
-CONFIG_RTC_DRV_DS1672=m
-CONFIG_RTC_DRV_MAX6900=m
-CONFIG_RTC_DRV_MAX8907=m
-CONFIG_RTC_DRV_RS5C372=m
-CONFIG_RTC_DRV_ISL1208=m
-CONFIG_RTC_DRV_ISL12022=m
-CONFIG_RTC_DRV_X1205=m
-CONFIG_RTC_DRV_PCF8523=m
-CONFIG_RTC_DRV_PCF85063=m
-CONFIG_RTC_DRV_PCF85363=m
-CONFIG_RTC_DRV_PCF8563=m
-CONFIG_RTC_DRV_PCF8583=m
-CONFIG_RTC_DRV_M41T80=m
-CONFIG_RTC_DRV_M41T80_WDT=y
-CONFIG_RTC_DRV_BQ32K=m
-CONFIG_RTC_DRV_S35390A=m
-CONFIG_RTC_DRV_FM3130=m
-CONFIG_RTC_DRV_RX8010=m
-CONFIG_RTC_DRV_RX8581=m
-CONFIG_RTC_DRV_RX8025=m
-CONFIG_RTC_DRV_EM3027=m
-CONFIG_RTC_DRV_RV3028=m
-CONFIG_RTC_DRV_RV3032=m
-CONFIG_RTC_DRV_RV8803=m
-CONFIG_RTC_DRV_SD3078=m
-
-#
-# SPI RTC drivers
-#
-CONFIG_RTC_DRV_M41T93=m
-CONFIG_RTC_DRV_M41T94=m
-CONFIG_RTC_DRV_DS1302=m
-CONFIG_RTC_DRV_DS1305=m
-CONFIG_RTC_DRV_DS1343=m
-CONFIG_RTC_DRV_DS1347=m
-CONFIG_RTC_DRV_DS1390=m
-CONFIG_RTC_DRV_MAX6916=m
-CONFIG_RTC_DRV_R9701=m
-CONFIG_RTC_DRV_RX4581=m
-CONFIG_RTC_DRV_RX6110=m
-CONFIG_RTC_DRV_RS5C348=m
-CONFIG_RTC_DRV_MAX6902=m
-CONFIG_RTC_DRV_PCF2123=m
-CONFIG_RTC_DRV_MCP795=m
-CONFIG_RTC_I2C_AND_SPI=m
-
-#
-# SPI and I2C RTC drivers
-#
-CONFIG_RTC_DRV_DS3232=m
-CONFIG_RTC_DRV_DS3232_HWMON=y
-CONFIG_RTC_DRV_PCF2127=m
-CONFIG_RTC_DRV_RV3029C2=m
-CONFIG_RTC_DRV_RV3029_HWMON=y
-
-#
-# Platform RTC drivers
-#
-CONFIG_RTC_DRV_CMOS=y
-CONFIG_RTC_DRV_DS1286=m
-CONFIG_RTC_DRV_DS1511=m
-CONFIG_RTC_DRV_DS1553=m
-CONFIG_RTC_DRV_DS1685_FAMILY=m
-CONFIG_RTC_DRV_DS1685=y
-# CONFIG_RTC_DRV_DS1689 is not set
-# CONFIG_RTC_DRV_DS17285 is not set
-# CONFIG_RTC_DRV_DS17485 is not set
-# CONFIG_RTC_DRV_DS17885 is not set
-CONFIG_RTC_DRV_DS1742=m
-CONFIG_RTC_DRV_DS2404=m
-CONFIG_RTC_DRV_DA9052=m
-CONFIG_RTC_DRV_DA9063=m
-CONFIG_RTC_DRV_STK17TA8=m
-CONFIG_RTC_DRV_M48T86=m
-CONFIG_RTC_DRV_M48T35=m
-CONFIG_RTC_DRV_M48T59=m
-CONFIG_RTC_DRV_MSM6242=m
-CONFIG_RTC_DRV_BQ4802=m
-CONFIG_RTC_DRV_RP5C01=m
-CONFIG_RTC_DRV_V3020=m
-CONFIG_RTC_DRV_OPTEE=m
-CONFIG_RTC_DRV_WM831X=m
-CONFIG_RTC_DRV_PCF50633=m
-# CONFIG_RTC_DRV_CROS_EC is not set
-CONFIG_RTC_DRV_NTXEC=m
-
-#
-# on-CPU RTC drivers
-#
-CONFIG_RTC_DRV_FTRTC010=m
-CONFIG_RTC_DRV_PCAP=m
-CONFIG_RTC_DRV_MC13XXX=m
-CONFIG_RTC_DRV_MT6397=m
-
-#
-# HID Sensor RTC drivers
-#
-CONFIG_RTC_DRV_HID_SENSOR_TIME=m
-CONFIG_RTC_DRV_GOLDFISH=m
-CONFIG_RTC_DRV_WILCO_EC=m
-CONFIG_DMADEVICES=y
-# CONFIG_DMADEVICES_DEBUG is not set
-
-#
-# DMA Devices
-#
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DMA_ACPI=y
-CONFIG_ALTERA_MSGDMA=m
-CONFIG_INTEL_IDMA64=m
-# CONFIG_PCH_DMA is not set
-CONFIG_PLX_DMA=m
-CONFIG_AMD_PTDMA=m
-CONFIG_XILINX_ZYNQMP_DPDMA=m
-CONFIG_QCOM_HIDMA_MGMT=m
-CONFIG_QCOM_HIDMA=m
-CONFIG_DW_DMAC_CORE=y
-CONFIG_DW_DMAC=m
-CONFIG_DW_DMAC_PCI=y
-CONFIG_DW_EDMA=m
-CONFIG_DW_EDMA_PCIE=m
-CONFIG_HSU_DMA=y
-CONFIG_SF_PDMA=m
-CONFIG_INTEL_LDMA=y
-
-#
-# DMA Clients
-#
-CONFIG_ASYNC_TX_DMA=y
-# CONFIG_DMATEST is not set
-CONFIG_X86_PLATFORM_DRIVERS_DELL=y
-
-#
-# DMABUF options
-#
-CONFIG_SYNC_FILE=y
-# CONFIG_SW_SYNC is not set
-# CONFIG_UDMABUF is not set
-# CONFIG_DMABUF_MOVE_NOTIFY is not set
-# CONFIG_DMABUF_DEBUG is not set
-CONFIG_DMABUF_SELFTESTS=m
-# CONFIG_DMABUF_HEAPS is not set
-# end of DMABUF options
-
-CONFIG_AUXDISPLAY=y
-CONFIG_HD44780=m
-CONFIG_KS0108=m
-CONFIG_KS0108_PORT=0x378
-CONFIG_KS0108_DELAY=2
-CONFIG_CFAG12864B=m
-CONFIG_CFAG12864B_RATE=20
-CONFIG_IMG_ASCII_LCD=m
-CONFIG_HT16K33=m
-CONFIG_LCD2S=m
-CONFIG_PARPORT_PANEL=m
-CONFIG_PANEL_PARPORT=0
-CONFIG_PANEL_PROFILE=5
-# CONFIG_PANEL_CHANGE_MESSAGE is not set
-# CONFIG_CHARLCD_BL_OFF is not set
-# CONFIG_CHARLCD_BL_ON is not set
-CONFIG_CHARLCD_BL_FLASH=y
-CONFIG_PANEL=m
-CONFIG_CHARLCD=m
-CONFIG_UIO=m
-CONFIG_UIO_CIF=m
-CONFIG_UIO_PDRV_GENIRQ=m
-CONFIG_UIO_DMEM_GENIRQ=m
-CONFIG_UIO_AEC=m
-CONFIG_UIO_SERCOS3=m
-CONFIG_UIO_PCI_GENERIC=m
-CONFIG_UIO_NETX=m
-CONFIG_UIO_PRUSS=m
-CONFIG_UIO_MF624=m
-CONFIG_UIO_DFL=m
-CONFIG_UIO_HV_GENERIC=m
-CONFIG_VFIO_IOMMU_TYPE1=m
-CONFIG_VFIO_VIRQFD=m
-CONFIG_VFIO=m
-# CONFIG_VFIO_NOIOMMU is not set
-CONFIG_VFIO_PCI=m
-CONFIG_MLX5_VFIO_PCI=m
-CONFIG_HISI_ACC_VFIO_PCI=m
-CONFIG_VFIO_PCI_VGA=y
-CONFIG_VFIO_PCI_MMAP=y
-CONFIG_VFIO_PCI_INTX=y
-CONFIG_VFIO_PCI_IGD=y
-CONFIG_VFIO_MDEV=m
-CONFIG_VFIO_MDEV_DEVICE=m
-CONFIG_IRQ_BYPASS_MANAGER=m
-CONFIG_VIRT_DRIVERS=y
-CONFIG_VMGENID=m
-CONFIG_VBOXGUEST=m
-CONFIG_NITRO_ENCLAVES=m
-CONFIG_VIRTIO=m
-CONFIG_VIRTIO_MENU=y
-CONFIG_VIRTIO_PCI=m
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_VDPA=m
-CONFIG_VP_VDPA=m
-CONFIG_ALIBABA_ENI_VDPA=m
-CONFIG_VIRTIO_PMEM=m
-CONFIG_VIRTIO_BALLOON=m
-CONFIG_VIRTIO_MEM=m
-CONFIG_VIRTIO_INPUT=m
-CONFIG_VIRTIO_MMIO=m
-CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
-CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
-CONFIG_VDPA=m
-CONFIG_IFCVF=m
-CONFIG_MLX5_VDPA=y
-CONFIG_MLX5_VDPA_NET=m
-CONFIG_VHOST_IOTLB=m
-CONFIG_VHOST_RING=m
-CONFIG_VHOST=m
-CONFIG_VHOST_MENU=y
-CONFIG_VHOST_NET=m
-CONFIG_VHOST_SCSI=m
-CONFIG_VHOST_VSOCK=m
-CONFIG_VHOST_VDPA=m
-# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
-
-#
-# Microsoft Hyper-V guest support
-#
-CONFIG_HYPERV=m
-CONFIG_HYPERV_TIMER=y
-CONFIG_HYPERV_UTILS=m
-CONFIG_HYPERV_BALLOON=m
-# end of Microsoft Hyper-V guest support
-
-CONFIG_GREYBUS=m
-CONFIG_GREYBUS_ES2=m
-CONFIG_STAGING=y
-CONFIG_PRISM2_USB=m
-CONFIG_COMEDI=m
-CONFIG_COMEDI_TESTS=m
-CONFIG_COMEDI_TESTS_EXAMPLE=m
-CONFIG_COMEDI_TESTS_NI_ROUTES=m
-# CONFIG_COMEDI_DEBUG is not set
-CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
-CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
-CONFIG_COMEDI_MISC_DRIVERS=y
-CONFIG_COMEDI_BOND=m
-CONFIG_COMEDI_TEST=m
-CONFIG_COMEDI_PARPORT=m
-# CONFIG_COMEDI_SSV_DNP is not set
-CONFIG_COMEDI_ISA_DRIVERS=y
-CONFIG_COMEDI_PCL711=m
-CONFIG_COMEDI_PCL724=m
-CONFIG_COMEDI_PCL726=m
-CONFIG_COMEDI_PCL730=m
-CONFIG_COMEDI_PCL812=m
-CONFIG_COMEDI_PCL816=m
-CONFIG_COMEDI_PCL818=m
-CONFIG_COMEDI_PCM3724=m
-CONFIG_COMEDI_AMPLC_DIO200_ISA=m
-CONFIG_COMEDI_AMPLC_PC236_ISA=m
-CONFIG_COMEDI_AMPLC_PC263_ISA=m
-CONFIG_COMEDI_RTI800=m
-CONFIG_COMEDI_RTI802=m
-CONFIG_COMEDI_DAC02=m
-CONFIG_COMEDI_DAS16M1=m
-CONFIG_COMEDI_DAS08_ISA=m
-CONFIG_COMEDI_DAS16=m
-CONFIG_COMEDI_DAS800=m
-CONFIG_COMEDI_DAS1800=m
-CONFIG_COMEDI_DAS6402=m
-CONFIG_COMEDI_DT2801=m
-CONFIG_COMEDI_DT2811=m
-CONFIG_COMEDI_DT2814=m
-CONFIG_COMEDI_DT2815=m
-CONFIG_COMEDI_DT2817=m
-CONFIG_COMEDI_DT282X=m
-CONFIG_COMEDI_DMM32AT=m
-CONFIG_COMEDI_FL512=m
-CONFIG_COMEDI_AIO_AIO12_8=m
-CONFIG_COMEDI_AIO_IIRO_16=m
-CONFIG_COMEDI_II_PCI20KC=m
-CONFIG_COMEDI_C6XDIGIO=m
-CONFIG_COMEDI_MPC624=m
-CONFIG_COMEDI_ADQ12B=m
-CONFIG_COMEDI_NI_AT_A2150=m
-CONFIG_COMEDI_NI_AT_AO=m
-CONFIG_COMEDI_NI_ATMIO=m
-CONFIG_COMEDI_NI_ATMIO16D=m
-CONFIG_COMEDI_NI_LABPC_ISA=m
-CONFIG_COMEDI_PCMAD=m
-CONFIG_COMEDI_PCMDA12=m
-CONFIG_COMEDI_PCMMIO=m
-CONFIG_COMEDI_PCMUIO=m
-CONFIG_COMEDI_MULTIQ3=m
-CONFIG_COMEDI_S526=m
-CONFIG_COMEDI_PCI_DRIVERS=m
+CONFIG_CHR_DEV_SG=m
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHROMEOS_ACPI=m
+CONFIG_CHROMEOS_LAPTOP=m
+CONFIG_CHROMEOS_PRIVACY_SCREEN=m
+CONFIG_CHROMEOS_PSTORE=m
+CONFIG_CHROMEOS_TBMC=m
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CICADA_PHY=m
+CONFIG_CIO2_BRIDGE=y
+CONFIG_CLANG_VERSION=160006
+CONFIG_CLKBLD_I8253=y
+CONFIG_CLKEVT_I8253=y
+CONFIG_CLKSRC_I8253=y
+CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
+CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CM32181=m
+CONFIG_CM3232=m
+CONFIG_CM3323=m
+CONFIG_CM3605=m
+CONFIG_CM36651=m
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+CONFIG_CMA_SIZE_MBYTES=0
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+CONFIG_CMA_SYSFS=y
+CONFIG_CMA=y
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_COMEDI_8255=m
 CONFIG_COMEDI_8255_PCI=m
-CONFIG_COMEDI_ADDI_WATCHDOG=m
+CONFIG_COMEDI_8255_SA=m
 CONFIG_COMEDI_ADDI_APCI_1032=m
 CONFIG_COMEDI_ADDI_APCI_1500=m
 CONFIG_COMEDI_ADDI_APCI_1516=m
@@ -8680,187 +811,954 @@ CONFIG_COMEDI_ADDI_APCI_2200=m
 CONFIG_COMEDI_ADDI_APCI_3120=m
 CONFIG_COMEDI_ADDI_APCI_3501=m
 CONFIG_COMEDI_ADDI_APCI_3XXX=m
+CONFIG_COMEDI_ADDI_WATCHDOG=m
 CONFIG_COMEDI_ADL_PCI6208=m
+CONFIG_COMEDI_ADL_PCI7250=m
 CONFIG_COMEDI_ADL_PCI7X3X=m
 CONFIG_COMEDI_ADL_PCI8164=m
 CONFIG_COMEDI_ADL_PCI9111=m
 CONFIG_COMEDI_ADL_PCI9118=m
+CONFIG_COMEDI_ADQ12B=m
 CONFIG_COMEDI_ADV_PCI1710=m
 CONFIG_COMEDI_ADV_PCI1720=m
 CONFIG_COMEDI_ADV_PCI1723=m
 CONFIG_COMEDI_ADV_PCI1724=m
 CONFIG_COMEDI_ADV_PCI1760=m
 CONFIG_COMEDI_ADV_PCI_DIO=m
+CONFIG_COMEDI_AIO_AIO12_8=m
+CONFIG_COMEDI_AIO_IIRO_16=m
+CONFIG_COMEDI_AMPLC_DIO200_ISA=m
 CONFIG_COMEDI_AMPLC_DIO200_PCI=m
+CONFIG_COMEDI_AMPLC_PC236_ISA=m
+CONFIG_COMEDI_AMPLC_PC236=m
 CONFIG_COMEDI_AMPLC_PC236_PCI=m
+CONFIG_COMEDI_AMPLC_PC263_ISA=m
 CONFIG_COMEDI_AMPLC_PC263_PCI=m
 CONFIG_COMEDI_AMPLC_PCI224=m
 CONFIG_COMEDI_AMPLC_PCI230=m
+CONFIG_COMEDI_BOND=m
+CONFIG_COMEDI_C6XDIGIO=m
+CONFIG_COMEDI_CB_DAS16_CS=m
+CONFIG_COMEDI_CB_PCIDAS64=m
+CONFIG_COMEDI_CB_PCIDAS=m
+CONFIG_COMEDI_CB_PCIDDA=m
+CONFIG_COMEDI_CB_PCIMDAS=m
+CONFIG_COMEDI_CB_PCIMDDA=m
 CONFIG_COMEDI_CONTEC_PCI_DIO=m
+CONFIG_COMEDI_DAC02=m
+CONFIG_COMEDI_DAQBOARD2000=m
+CONFIG_COMEDI_DAS08_CS=m
+CONFIG_COMEDI_DAS08_ISA=m
 CONFIG_COMEDI_DAS08_PCI=m
+CONFIG_COMEDI_DAS16=m
+CONFIG_COMEDI_DAS16M1=m
+CONFIG_COMEDI_DAS1800=m
+CONFIG_COMEDI_DAS6402=m
+CONFIG_COMEDI_DAS800=m
+CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
+CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
+CONFIG_COMEDI_DMM32AT=m
+CONFIG_COMEDI_DT2801=m
+CONFIG_COMEDI_DT2811=m
+CONFIG_COMEDI_DT2814=m
+CONFIG_COMEDI_DT2815=m
+CONFIG_COMEDI_DT2817=m
+CONFIG_COMEDI_DT282X=m
 CONFIG_COMEDI_DT3000=m
+CONFIG_COMEDI_DT9812=m
 CONFIG_COMEDI_DYNA_PCI10XX=m
+CONFIG_COMEDI_FL512=m
 CONFIG_COMEDI_GSC_HPDI=m
-CONFIG_COMEDI_MF6X4=m
 CONFIG_COMEDI_ICP_MULTI=m
-CONFIG_COMEDI_DAQBOARD2000=m
+CONFIG_COMEDI_II_PCI20KC=m
+CONFIG_COMEDI_ISADMA=m
+CONFIG_COMEDI_ISA_DRIVERS=y
 CONFIG_COMEDI_JR3_PCI=m
+CONFIG_COMEDI_KCOMEDILIB=m
 CONFIG_COMEDI_KE_COUNTER=m
-CONFIG_COMEDI_CB_PCIDAS64=m
-CONFIG_COMEDI_CB_PCIDAS=m
-CONFIG_COMEDI_CB_PCIDDA=m
-CONFIG_COMEDI_CB_PCIMDAS=m
-CONFIG_COMEDI_CB_PCIMDDA=m
+CONFIG_COMEDI=m
 CONFIG_COMEDI_ME4000=m
 CONFIG_COMEDI_ME_DAQ=m
+CONFIG_COMEDI_MF6X4=m
+CONFIG_COMEDI_MISC_DRIVERS=y
+CONFIG_COMEDI_MITE=m
+CONFIG_COMEDI_MPC624=m
+CONFIG_COMEDI_MULTIQ3=m
 CONFIG_COMEDI_NI_6527=m
 CONFIG_COMEDI_NI_65XX=m
 CONFIG_COMEDI_NI_660X=m
 CONFIG_COMEDI_NI_670X=m
+CONFIG_COMEDI_NI_AT_A2150=m
+CONFIG_COMEDI_NI_AT_AO=m
+CONFIG_COMEDI_NI_ATMIO16D=m
+CONFIG_COMEDI_NI_ATMIO=m
+CONFIG_COMEDI_NI_DAQ_700_CS=m
+CONFIG_COMEDI_NI_DAQ_DIO24_CS=m
+CONFIG_COMEDI_NI_LABPC_CS=m
+CONFIG_COMEDI_NI_LABPC_ISA=m
 CONFIG_COMEDI_NI_LABPC_PCI=m
+CONFIG_COMEDI_NI_MIO_CS=m
 CONFIG_COMEDI_NI_PCIDIO=m
 CONFIG_COMEDI_NI_PCIMIO=m
-CONFIG_COMEDI_RTD520=m
-CONFIG_COMEDI_S626=m
-CONFIG_COMEDI_MITE=m
+CONFIG_COMEDI_NI_ROUTING=m
 CONFIG_COMEDI_NI_TIOCMD=m
+CONFIG_COMEDI_NI_TIO=m
+CONFIG_COMEDI_NI_USB6501=m
+CONFIG_COMEDI_PARPORT=m
+CONFIG_COMEDI_PCI_DRIVERS=m
+CONFIG_COMEDI_PCL711=m
+CONFIG_COMEDI_PCL724=m
+CONFIG_COMEDI_PCL726=m
+CONFIG_COMEDI_PCL730=m
+CONFIG_COMEDI_PCL812=m
+CONFIG_COMEDI_PCL816=m
+CONFIG_COMEDI_PCL818=m
+CONFIG_COMEDI_PCM3724=m
+CONFIG_COMEDI_PCMAD=m
 CONFIG_COMEDI_PCMCIA_DRIVERS=m
-CONFIG_COMEDI_CB_DAS16_CS=m
-CONFIG_COMEDI_DAS08_CS=m
-CONFIG_COMEDI_NI_DAQ_700_CS=m
-CONFIG_COMEDI_NI_DAQ_DIO24_CS=m
-CONFIG_COMEDI_NI_LABPC_CS=m
-CONFIG_COMEDI_NI_MIO_CS=m
+CONFIG_COMEDI_PCMDA12=m
+CONFIG_COMEDI_PCMMIO=m
+CONFIG_COMEDI_PCMUIO=m
 CONFIG_COMEDI_QUATECH_DAQP_CS=m
+CONFIG_COMEDI_RTD520=m
+CONFIG_COMEDI_RTI800=m
+CONFIG_COMEDI_RTI802=m
+CONFIG_COMEDI_S526=m
+CONFIG_COMEDI_S626=m
+CONFIG_COMEDI_TEST=m
+CONFIG_COMEDI_TESTS_EXAMPLE=m
+CONFIG_COMEDI_TESTS=m
+CONFIG_COMEDI_TESTS_NI_ROUTES=m
 CONFIG_COMEDI_USB_DRIVERS=m
-CONFIG_COMEDI_DT9812=m
-CONFIG_COMEDI_NI_USB6501=m
-CONFIG_COMEDI_USBDUX=m
 CONFIG_COMEDI_USBDUXFAST=m
+CONFIG_COMEDI_USBDUX=m
 CONFIG_COMEDI_USBDUXSIGMA=m
 CONFIG_COMEDI_VMK80XX=m
-CONFIG_COMEDI_8254=m
-CONFIG_COMEDI_8255=m
-CONFIG_COMEDI_8255_SA=m
-CONFIG_COMEDI_KCOMEDILIB=m
-CONFIG_COMEDI_AMPLC_DIO200=m
-CONFIG_COMEDI_AMPLC_PC236=m
-CONFIG_COMEDI_DAS08=m
-CONFIG_COMEDI_ISADMA=m
-CONFIG_COMEDI_NI_LABPC=m
-CONFIG_COMEDI_NI_LABPC_ISADMA=m
-CONFIG_COMEDI_NI_TIO=m
-CONFIG_COMEDI_NI_ROUTING=m
-CONFIG_RTL8192U=m
-CONFIG_RTLLIB=m
-CONFIG_RTLLIB_CRYPTO_CCMP=m
-CONFIG_RTLLIB_CRYPTO_TKIP=m
-CONFIG_RTLLIB_CRYPTO_WEP=m
-CONFIG_RTL8192E=m
-CONFIG_RTL8723BS=m
-CONFIG_R8712U=m
-CONFIG_R8188EU=m
-CONFIG_88EU_AP_MODE=y
-CONFIG_RTS5208=m
-CONFIG_VT6655=m
-CONFIG_VT6656=m
-
-#
-# IIO staging drivers
-#
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16203=m
-CONFIG_ADIS16240=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD7816=m
-CONFIG_AD7280=m
-# end of Analog to digital converters
-
-#
-# Analog digital bi-direction converters
-#
-CONFIG_ADT7316=m
-CONFIG_ADT7316_SPI=m
-CONFIG_ADT7316_I2C=m
-# end of Analog digital bi-direction converters
-
-#
-# Capacitance to digital converters
-#
-CONFIG_AD7150=m
-CONFIG_AD7746=m
-# end of Capacitance to digital converters
-
-#
-# Direct Digital Synthesis
-#
-CONFIG_AD9832=m
-CONFIG_AD9834=m
-# end of Direct Digital Synthesis
-
-#
-# Network Analyzer, Impedance Converters
-#
-CONFIG_AD5933=m
-# end of Network Analyzer, Impedance Converters
-
-#
-# Active energy metering IC
-#
-CONFIG_ADE7854=m
-CONFIG_ADE7854_I2C=m
-CONFIG_ADE7854_SPI=m
-# end of Active energy metering IC
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S1210=m
-# end of Resolver to digital converters
-# end of IIO staging drivers
-
+CONFIG_COMMON_CLK_CDCE706=m
+CONFIG_COMMON_CLK_CS2000_CP=m
+CONFIG_COMMON_CLK_MAX9485=m
+CONFIG_COMMON_CLK_PWM=m
+CONFIG_COMMON_CLK_SI5341=m
+CONFIG_COMMON_CLK_SI5351=m
+CONFIG_COMMON_CLK_SI544=m
+CONFIG_COMMON_CLK_TPS68470=m
+CONFIG_COMMON_CLK_WM831X=m
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAL_LAPTOP=m
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_COMPAT_32=y
+CONFIG_CONNECTOR=m
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CORDIC=m
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CORTINA_PHY=m
+CONFIG_COUNTER=m
+CONFIG_CPU5_WDT=m
+CONFIG_CPUFREQ_ARCH_CUR_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_IDLE_GOV_HALTPOLL=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_SUP_AMD=y
+CONFIG_CPU_SUP_CENTAUR=y
+CONFIG_CPU_SUP_CYRIX_32=y
+CONFIG_CPU_SUP_HYGON=y
+CONFIG_CPU_SUP_INTEL=y
+CONFIG_CPU_SUP_TRANSMETA_32=y
+CONFIG_CPU_SUP_UMC_32=y
+CONFIG_CPU_SUP_VORTEX_32=y
+CONFIG_CPU_SUP_ZHAOXIN=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRC16=y
+CONFIG_CRC4=m
+CONFIG_CRC64=m
+CONFIG_CRC64_ROCKSOFT=m
+CONFIG_CRC7=m
+CONFIG_CRC8=m
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CROS_EC_CHARDEV=m
+CONFIG_CROS_EC_DEBUGFS=m
+CONFIG_CROS_EC_I2C=m
+CONFIG_CROS_EC_LIGHTBAR=m
+CONFIG_CROS_EC_LPC=m
+CONFIG_CROS_EC=m
+CONFIG_CROS_EC_MKBP_PROXIMITY=m
+CONFIG_CROS_EC_PROTO=y
+CONFIG_CROS_EC_SENSORHUB=m
+CONFIG_CROS_EC_SPI=m
+CONFIG_CROS_EC_SYSFS=m
+CONFIG_CROS_EC_TYPEC=m
+CONFIG_CROS_EC_UART=m
+CONFIG_CROS_EC_WATCHDOG=m
+CONFIG_CROS_HPS_I2C=m
+CONFIG_CROS_KBD_LED_BACKLIGHT=m
+CONFIG_CROS_TYPEC_SWITCH=m
+CONFIG_CROS_USBPD_LOGGER=m
+CONFIG_CROS_USBPD_NOTIFY=m
+CONFIG_CRYPTO_842=y
+CONFIG_CRYPTO_ADIANTUM=m
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEGIS128=m
+CONFIG_CRYPTO_AES_NI_INTEL=m
+CONFIG_CRYPTO_AES_TI=m
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARIA=m
+CONFIG_CRYPTO_BLAKE2B=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_CAST_COMMON=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CFB=m
+CONFIG_CRYPTO_CHACHA20=m
+CONFIG_CRYPTO_CHACHA20POLY1305=m
+CONFIG_CRYPTO_CMAC=m
+CONFIG_CRYPTO_CRC32C_INTEL=m
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32=m
+CONFIG_CRYPTO_CRC32_PCLMUL=m
+CONFIG_CRYPTO_CRC64_ROCKSOFT=m
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_CURVE25519=m
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
+CONFIG_CRYPTO_DEV_ATMEL_ECC=m
+CONFIG_CRYPTO_DEV_ATMEL_I2C=m
+CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
+CONFIG_CRYPTO_DEV_CCP_CRYPTO=m
+CONFIG_CRYPTO_DEV_CCP_DD=m
+CONFIG_CRYPTO_DEV_CCP=y
+CONFIG_CRYPTO_DEV_CHELSIO=m
+CONFIG_CRYPTO_DEV_PADLOCK_AES=m
+CONFIG_CRYPTO_DEV_PADLOCK=m
+CONFIG_CRYPTO_DEV_PADLOCK_SHA=m
+CONFIG_CRYPTO_DEV_QAT_420XX=m
+CONFIG_CRYPTO_DEV_QAT_4XXX=m
+CONFIG_CRYPTO_DEV_QAT_6XXX=m
+CONFIG_CRYPTO_DEV_QAT_C3XXX=m
+CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
+CONFIG_CRYPTO_DEV_QAT_C62X=m
+CONFIG_CRYPTO_DEV_QAT_C62XVF=m
+CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
+CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
+CONFIG_CRYPTO_DEV_QAT=m
+CONFIG_CRYPTO_DEV_SAFEXCEL=m
+CONFIG_CRYPTO_DEV_SP_CCP=y
+CONFIG_CRYPTO_DEV_VIRTIO=m
+CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
+CONFIG_CRYPTO_DH=y
+CONFIG_CRYPTO_DRBG_CTR=y
+CONFIG_CRYPTO_DRBG_HASH=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECC=m
+CONFIG_CRYPTO_ECDH=m
+CONFIG_CRYPTO_ECDSA=m
+CONFIG_CRYPTO_ECHAINIV=m
+CONFIG_CRYPTO_ECRDSA=m
+CONFIG_CRYPTO_ENGINE=m
+CONFIG_CRYPTO_ESSIV=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_GENIV=m
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HCTR2=m
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_KDF800108_CTR=y
+CONFIG_CRYPTO_KEYWRAP=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_KPP=y
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_GF128MUL=m
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_LZ4HC=y
+CONFIG_CRYPTO_LZ4=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_NHPOLY1305=m
+CONFIG_CRYPTO_NULL2=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_OFB=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_PCRYPT=m
+CONFIG_CRYPTO_POLY1305=m
+CONFIG_CRYPTO_POLYVAL=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SIG2=y
+CONFIG_CRYPTO_SIMD=m
+CONFIG_CRYPTO_SM2=m
+CONFIG_CRYPTO_SM3_GENERIC=m
+CONFIG_CRYPTO_SM3=m
+CONFIG_CRYPTO_SM4_GENERIC=m
+CONFIG_CRYPTO_SM4=m
+CONFIG_CRYPTO_STREEBOG=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_USER_API_AEAD=m
+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_RNG_CAVP=y
+CONFIG_CRYPTO_USER_API_RNG=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_USER_API=y
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_XCTR=m
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_XXHASH=m
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CW1200=m
+CONFIG_CW1200_WLAN_SDIO=m
+CONFIG_CW1200_WLAN_SPI=m
+CONFIG_CXD2880_SPI_DRV=m
+CONFIG_CXL_ACPI=m
+CONFIG_CXL_BUS=m
+CONFIG_CXL_FEATURES=y
+CONFIG_CXL_MEM=m
+CONFIG_CXL_MEM_RAW_COMMANDS=y
+CONFIG_CXL_PCI=m
+CONFIG_CXL_PMEM=m
+CONFIG_CXL_PMU=m
+CONFIG_CXL_PORT=m
+CONFIG_CXL_REGION=y
+CONFIG_CXL_SUSPEND=y
+CONFIG_CYPRESS_FIRMWARE=m
+CONFIG_DA280=m
+CONFIG_DA311=m
+CONFIG_DA9052_WATCHDOG=m
+CONFIG_DA9062_WATCHDOG=m
+CONFIG_DA9063_WATCHDOG=m
+CONFIG_DA9150_GPADC=m
+CONFIG_DASHARO_ACPI=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_DAX=y
+CONFIG_DCDBAS=m
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_WX=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DEFAULT_HOSTNAME="omv"
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DELL_LAPTOP=m
+CONFIG_DELL_PC=m
+CONFIG_DELL_RBTN=m
+CONFIG_DELL_RBU=m
+CONFIG_DELL_SMBIOS=m
+CONFIG_DELL_SMBIOS_SMM=y
+CONFIG_DELL_SMBIOS_WMI=y
+CONFIG_DELL_SMO8800=m
+CONFIG_DELL_UART_BACKLIGHT=m
+CONFIG_DELL_WMI_AIO=m
+CONFIG_DELL_WMI_DDV=m
+CONFIG_DELL_WMI_DESCRIPTOR=m
+CONFIG_DELL_WMI_LED=m
+CONFIG_DELL_WMI=m
+CONFIG_DELL_WMI_PRIVACY=y
+CONFIG_DELL_WMI_SYSMAN=m
+CONFIG_DEV_DAX_CXL=m
+CONFIG_DEV_DAX_HMEM_DEVICES=y
+CONFIG_DEV_DAX_HMEM=m
+CONFIG_DEV_DAX=m
+CONFIG_DEVFREQ_GOV_PASSIVE=m
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_DEVTMPFS_SAFE=y
+CONFIG_DHT11=m
+CONFIG_DIMLIB=y
+CONFIG_DLHL60D=m
+CONFIG_DLN2_ADC=m
+CONFIG_DMA_ACPI=y
+CONFIG_DMABUF_SELFTESTS=m
+CONFIG_DMA_CMA=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_NUMA_CMA=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_PERNUMA_CMA=y
+CONFIG_DMARD06=m
+CONFIG_DMARD09=m
+CONFIG_DMARD10=m
+CONFIG_DMAR_TABLE=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DM_CACHE=m
+CONFIG_DM_CACHE_SMQ=m
+CONFIG_DM_CLONE=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_DELAY=m
+CONFIG_DM_DUST=m
+CONFIG_DM_EBS=m
+CONFIG_DM_ERA=m
+CONFIG_DM_FLAKEY=m
+CONFIG_DMIID=y
+CONFIG_DM_INTEGRITY=m
+CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
+CONFIG_DMI_SYSFS=m
+CONFIG_DMI=y
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_LOG_WRITES=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_MULTIPATH_HST=m
+CONFIG_DM_MULTIPATH_IOA=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_PCACHE=m
+CONFIG_DM_RAID=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_SWITCH=m
+CONFIG_DM_UEVENT=y
+CONFIG_DM_UNSTRIPED=m
+CONFIG_DM_VERITY=m
+CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
+CONFIG_DM_WRITECACHE=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_ZONED=m
+CONFIG_DP83640_PHY=m
+CONFIG_DP83822_PHY=m
+CONFIG_DP83848_PHY=m
+CONFIG_DP83867_PHY=m
+CONFIG_DP83869_PHY=m
+CONFIG_DP83TC811_PHY=m
+CONFIG_DP83TD510_PHY=m
+CONFIG_DP83TG720_PHY=m
+CONFIG_DPOT_DAC=m
+CONFIG_DPS310=m
+CONFIG_DPTF_PCH_FIVR=m
+CONFIG_DPTF_POWER=m
+CONFIG_DRM_ACCEL_QAIC=m
+CONFIG_DRM_ACCEL=y
+CONFIG_DRM_AMD_ACP=y
+CONFIG_DRM_AMDGPU_CIK=y
+CONFIG_DRM_AMDGPU=m
+CONFIG_DRM_AMDGPU_SI=y
+CONFIG_DRM_AMD_ISP=y
+CONFIG_DRM_ANALOGIX_ANX78XX=m
+CONFIG_DRM_ANALOGIX_DP=m
+CONFIG_DRM_APPLETBDRM=m
+CONFIG_DRM_AST=m
+CONFIG_DRM_BOCHS=m
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_BUDDY=m
+CONFIG_DRM_CIRRUS_QEMU=m
+CONFIG_DRM_CLIENT_DEFAULT_LOG=y
+CONFIG_DRM_CLIENT_LOG=y
+CONFIG_DRM_DISPLAY_DP_AUX_CEC=y
+CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV=y
+CONFIG_DRM_DISPLAY_DP_HELPER=y
+CONFIG_DRM_DISPLAY_HDCP_HELPER=y
+CONFIG_DRM_DISPLAY_HDMI_HELPER=y
+CONFIG_DRM_DISPLAY_HELPER=m
+CONFIG_DRM_DP_AUX_CHARDEV=y
+CONFIG_DRM_ETNAVIV=m
+CONFIG_DRM_ETNAVIV_THERMAL=y
+CONFIG_DRM_EVDI=m
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_GEM_DMA_HELPER=m
+CONFIG_DRM_GEM_SHMEM_HELPER=m
+CONFIG_DRM_GM12U320=m
+CONFIG_DRM_GMA500=m
+CONFIG_DRM_GUD=m
+CONFIG_DRM_HISI_HIBMC=m
+CONFIG_DRM_HYPERV=m
+CONFIG_DRM_I2C_CH7006=m
+CONFIG_DRM_I2C_NXP_TDA9950=m
+CONFIG_DRM_I2C_NXP_TDA998X=m
+CONFIG_DRM_I2C_SIL164=m
+CONFIG_DRM_I915_CAPTURE_ERROR=y
+CONFIG_DRM_I915_COMPRESS_ERROR=y
+CONFIG_DRM_I915_DP_TUNNEL=y
+CONFIG_DRM_I915_FENCE_TIMEOUT=10000
+CONFIG_DRM_I915_FORCE_PROBE=""
+CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
+CONFIG_DRM_I915=m
+CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
+CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
+CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE=7500
+CONFIG_DRM_I915_PXP=y
+CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
+CONFIG_DRM_I915_STOP_TIMEOUT=100
+CONFIG_DRM_I915_TIMESLICE_DURATION=1
+CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
+CONFIG_DRM_I915_USERPTR=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_LEGACY=y
+CONFIG_DRM_LOONGSON=m
+CONFIG_DRM_MGAG200=m
+CONFIG_DRM_MIPI_DBI=m
+CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_NOUVEAU_BACKLIGHT=y
+CONFIG_DRM_NOUVEAU_CH7006=m
+CONFIG_DRM_NOUVEAU_GSP_DEFAULT=y
+CONFIG_DRM_NOUVEAU=m
+CONFIG_DRM_NOUVEAU_SIL164=m
+CONFIG_DRM_PANEL_AUO_A030JTN01=m
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ILITEK_ILI9341=m
+CONFIG_DRM_PANEL_MIPI_DBI=m
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_PANEL_ORISETECH_OTA5601A=m
+CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
+CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANIC_BACKGROUND_COLOR=0x000000
+CONFIG_DRM_PANIC_FOREGROUND_COLOR=0xa0a0a0
+CONFIG_DRM_PANIC_SCREEN="user"
+CONFIG_DRM_PANIC=y
+CONFIG_DRM_PIXPAPER=m
+CONFIG_DRM_POWERVR=m
+CONFIG_DRM_PRIVACY_SCREEN=y
+CONFIG_DRM_QXL=m
+CONFIG_DRM_RADEON=m
+CONFIG_DRM_SCHED=m
+CONFIG_DRM_SIMPLEDRM=y
+CONFIG_DRM_SSD130X_I2C=m
+CONFIG_DRM_SSD130X=m
+CONFIG_DRM_SSD130X_SPI=m
+CONFIG_DRM_SUBALLOC_HELPER=m
+CONFIG_DRM_TTM_HELPER=m
+CONFIG_DRM_TTM=m
+CONFIG_DRM_UDL=m
+CONFIG_DRM_VBOXVIDEO=m
+CONFIG_DRM_VGEM=m
+CONFIG_DRM_VIRTIO_GPU_KMS=y
+CONFIG_DRM_VIRTIO_GPU=m
+CONFIG_DRM_VKMS=m
+CONFIG_DRM_VMWGFX=m
+CONFIG_DRM_VMWGFX_MKSSTATS=y
+CONFIG_DRM_VRAM_HELPER=m
+CONFIG_DRM_XE_DEVMEM_MIRROR=y
+CONFIG_DRM_XE_DISPLAY=y
+CONFIG_DRM_XE_DP_TUNNEL=y
+CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT=y
+CONFIG_DRM_XE_FORCE_PROBE=""
+CONFIG_DRM_XE_JOB_TIMEOUT_MAX=10000
+CONFIG_DRM_XE_JOB_TIMEOUT_MIN=1
+CONFIG_DRM_XE=m
+CONFIG_DRM_XE_PREEMPT_TIMEOUT=640000
+CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX=10000000
+CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN=1
+CONFIG_DRM_XE_SIMPLE_ERROR_CAPTURE=y
+CONFIG_DRM_XE_TIMESLICE_MAX=10000000
+CONFIG_DRM_XE_TIMESLICE_MIN=1
+CONFIG_DRM=y
+CONFIG_DS1682=m
+CONFIG_DS1803=m
+CONFIG_DS4424=m
+CONFIG_DUMMY_CONSOLE_ROWS=30
+CONFIG_DUMMY=m
+CONFIG_DVB_A8293=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_AF9033=m
+CONFIG_DVB_AS102_FE=m
+CONFIG_DVB_AS102=m
+CONFIG_DVB_ASCOT2E=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_AU8522_DTV=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_AU8522_V4L=m
+CONFIG_DVB_AV7110_IR=y
+CONFIG_DVB_AV7110=m
+CONFIG_DVB_AV7110_OSD=y
+CONFIG_DVB_B2C2_FLEXCOP=m
+CONFIG_DVB_B2C2_FLEXCOP_PCI=m
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_BT8XX=m
+CONFIG_DVB_BUDGET_AV=m
+CONFIG_DVB_BUDGET_CI=m
+CONFIG_DVB_BUDGET_CORE=m
+CONFIG_DVB_BUDGET=m
+CONFIG_DVB_BUDGET_PATCH=m
+CONFIG_DVB_CORE=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_CX24117=m
+CONFIG_DVB_CX24120=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_CXD2099=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_CXD2841ER=m
+CONFIG_DVB_DDBRIDGE=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_DM1105=m
+CONFIG_DVB_DRX39XYJ=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_DYNAMIC_MINORS=y
+CONFIG_DVB_EC100=m
+CONFIG_DVB_FIREDTV_INPUT=y
+CONFIG_DVB_FIREDTV=m
+CONFIG_DVB_GP8PSK_FE=m
+CONFIG_DVB_HELENE=m
+CONFIG_DVB_HOPPER=m
+CONFIG_DVB_HORUS3A=m
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6422=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_LG2160=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_LGDT3306A=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_LNBH25=m
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_M88DS3103=m
+CONFIG_DVB_M88RS2000=m
+CONFIG_DVB_MANTIS=m
+CONFIG_DVB_MAX_ADAPTERS=8
+CONFIG_DVB_MB86A16=m
+CONFIG_DVB_MB86A20S=m
+CONFIG_DVB_MN88472=m
+CONFIG_DVB_MN88473=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_MXL5XX=m
+CONFIG_DVB_MXL692=m
+CONFIG_DVB_NETUP_UNIDVB=m
+CONFIG_DVB_NET=y
+CONFIG_DVB_NGENE=m
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_PLATFORM_DRIVERS=y
+CONFIG_DVB_PLL=m
+CONFIG_DVB_PLUTO2=m
+CONFIG_DVB_PT1=m
+CONFIG_DVB_PT3=m
+CONFIG_DVB_RTL2830=m
+CONFIG_DVB_RTL2832=m
+CONFIG_DVB_RTL2832_SDR=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_S5H1411=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_S921=m
+CONFIG_DVB_SI2165=m
+CONFIG_DVB_SI2168=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_SMIPCIE=m
+CONFIG_DVB_SP2=m
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STV0297=m
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV0910=m
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV6110x=m
+CONFIG_DVB_STV6111=m
+CONFIG_DVB_TAS2101=m
+CONFIG_DVB_TC90522=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_TDA10071=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA18271C2DD=m
+CONFIG_DVB_TDA665x=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TS2020=m
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_CXUSB_ANALOG=y
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_DIB3000MC=m
+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
+CONFIG_DVB_USB_DIBUSB_MB=m
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_DVBSKY=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_V2=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_ZD1301=m
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_ZD1301_DEMOD=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DW_DMAC_CORE=y
+CONFIG_DW_DMAC=m
+CONFIG_DW_DMAC_PCI=y
+CONFIG_DW_EDMA=m
+CONFIG_DW_EDMA_PCIE=m
+CONFIG_DW_I3C_MASTER=m
+CONFIG_DW_WATCHDOG=m
+CONFIG_DW_XDATA_PCIE=m
+CONFIG_DYNAMIC_SIGFRAME=y
+CONFIG_EBC_C384_WDT=m
+CONFIG_ECHO=m
+CONFIG_EDAC_AMD64=m
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_DECODE_MCE=m
+CONFIG_EDAC_E752X=m
+CONFIG_EDAC_ECS=y
+CONFIG_EDAC_GHES=m
+CONFIG_EDAC_I3000=m
+CONFIG_EDAC_I3200=m
+CONFIG_EDAC_I5100=m
+CONFIG_EDAC_I5400=m
+CONFIG_EDAC_I7300=m
+CONFIG_EDAC_I7CORE=m
+CONFIG_EDAC_I82975X=m
+CONFIG_EDAC_IE31200=m
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC=m
+CONFIG_EDAC_MEM_REPAIR=y
+CONFIG_EDAC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EDAC_X38=m
+CONFIG_EDD=m
+CONFIG_EEEPC_LAPTOP=m
+CONFIG_EEEPC_WMI=m
+CONFIG_EEPROM_93CX6=m
+CONFIG_EEPROM_93XX46=m
+CONFIG_EEPROM_AT24=m
+CONFIG_EEPROM_AT25=m
+CONFIG_EEPROM_EE1004=m
+CONFIG_EEPROM_IDT_89HPESX=m
+CONFIG_EEPROM_LEGACY=m
+CONFIG_EEPROM_MAX6875=m
+CONFIG_EFI_BOOTLOADER_CONTROL=m
+CONFIG_EFI_CAPSULE_LOADER=y
+CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH=y
+CONFIG_EFI_COCO_SECRET=y
+CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
+CONFIG_EFI_DEV_PATH_PARSER=y
+CONFIG_EFI_DXE_MEM_ATTRIBUTES=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_HANDOVER_PROTOCOL=y
+CONFIG_EFI_RCI2_TABLE=y
+CONFIG_EFI_RUNTIME_MAP=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_SBAT_FILE=""
+CONFIG_EFI_SOFT_RESERVE=y
+CONFIG_EFI_STUB=y
+CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
+CONFIG_EFI_VARS_PSTORE=m
+CONFIG_EFI=y
+CONFIG_ENCLOSURE_SERVICES=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_ENERGY_MODEL=y
+CONFIG_ENS160=m
+CONFIG_ENS210=m
+CONFIG_ENVELOPE_DETECTOR=m
+CONFIG_EQUALIZER=m
+CONFIG_EUROTECH_WDT=m
+CONFIG_EXAR_WDT=m
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXPERT=y
+CONFIG_EXTCON_ADC_JACK=m
+CONFIG_EXTCON_AXP288=m
+CONFIG_EXTCON_FSA9480=m
+CONFIG_EXTCON_GPIO=m
+CONFIG_EXTCON_INTEL_INT3496=m
+CONFIG_EXTCON_INTEL_MRFLD=m
+CONFIG_EXTCON_LC824206XA=m
+CONFIG_EXTCON_MAX14526=m
+CONFIG_EXTCON_MAX14577=m
+CONFIG_EXTCON_MAX3355=m
+CONFIG_EXTCON_MAX77693=m
+CONFIG_EXTCON_PTN5150=m
+CONFIG_EXTCON_RT8973A=m
+CONFIG_EXTCON_RTK_TYPE_C=m
+CONFIG_EXTCON_SM5502=m
+CONFIG_EXTCON_USBC_CROS_EC=m
+CONFIG_EXTCON_USBC_TUSB320=m
+CONFIG_EXTCON_USB_GPIO=m
+CONFIG_EXTCON=y
+CONFIG_EZX_PCAP=y
+CONFIG_F71808E_WDT=m
+CONFIG_FAILOVER=m
+CONFIG_FARSYNC=m
+CONFIG_FB_3DFX_ACCEL=y
+CONFIG_FB_3DFX_I2C=y
+CONFIG_FB_3DFX=m
+CONFIG_FB_ARC=m
+CONFIG_FB_ARK=m
+CONFIG_FB_ASILIANT=y
+CONFIG_FB_ATY128_BACKLIGHT=y
+CONFIG_FB_ATY128=m
+CONFIG_FB_ATY_BACKLIGHT=y
+CONFIG_FB_ATY_CT=y
+CONFIG_FB_ATY_GENERIC_LCD=y
+CONFIG_FB_ATY_GX=y
+CONFIG_FB_ATY=m
+CONFIG_FB_BACKLIGHT=m
+CONFIG_FB_BOTH_ENDIAN=y
+CONFIG_FB_CARILLO_RANCH=m
+CONFIG_FB_CARMINE_DRAM_EVAL=y
+CONFIG_FB_CARMINE=m
+CONFIG_FB_CIRRUS=m
+CONFIG_FB_CYBER2000_DDC=y
+CONFIG_FB_CYBER2000=m
+CONFIG_FB_DDC=m
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_EFI=y
+CONFIG_FB_FOREIGN_ENDIAN=y
+CONFIG_FB_HECUBA=m
+CONFIG_FB_HYPERV=m
+CONFIG_FB_I740=m
+CONFIG_FB_IBM_GXT4500=m
+CONFIG_FB_IMSTT=y
+CONFIG_FB_IO_HELPERS=y
+CONFIG_FB_KYRO=m
+CONFIG_FB_LE80578=m
+CONFIG_FB_MATROX_G=y
+CONFIG_FB_MATROX_I2C=m
+CONFIG_FB_MATROX=m
+CONFIG_FB_MATROX_MAVEN=m
+CONFIG_FB_MATROX_MILLENIUM=y
+CONFIG_FB_MATROX_MYSTIQUE=y
+CONFIG_FB_MB862XX_I2C=y
+CONFIG_FB_MB862XX=m
+CONFIG_FB_MB862XX_PCI_GDC=y
+CONFIG_FB_METRONOME=m
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_N411=m
+CONFIG_FB_NEOMAGIC=m
+CONFIG_FB_OPENCORES=m
+CONFIG_FB_PM2_FIFO_DISCONNECT=y
+CONFIG_FB_PM2=m
+CONFIG_FB_PM3=m
+CONFIG_FB_RADEON_BACKLIGHT=y
+CONFIG_FB_RADEON_I2C=y
+CONFIG_FB_RADEON=m
+CONFIG_FB_S1D13XXX=m
+CONFIG_FB_S3_DDC=y
+CONFIG_FB_S3=m
+CONFIG_FB_SAVAGE_ACCEL=y
+CONFIG_FB_SAVAGE_I2C=y
+CONFIG_FB_SAVAGE=m
+CONFIG_FB_SIS_300=y
+CONFIG_FB_SIS_315=y
+CONFIG_FB_SIS=m
+CONFIG_FB_SM501=m
+CONFIG_FB_SM712=m
 CONFIG_FB_SM750=m
-CONFIG_STAGING_MEDIA=y
-CONFIG_INTEL_ATOMISP=y
-CONFIG_VIDEO_ATOMISP=m
-CONFIG_VIDEO_ATOMISP_ISP2401=y
-CONFIG_VIDEO_ATOMISP_OV2722=m
-CONFIG_VIDEO_ATOMISP_GC2235=m
-CONFIG_VIDEO_ATOMISP_MSRLIST_HELPER=m
-CONFIG_VIDEO_ATOMISP_MT9M114=m
-CONFIG_VIDEO_ATOMISP_GC0310=m
-CONFIG_VIDEO_ATOMISP_OV2680=m
-CONFIG_VIDEO_ATOMISP_OV5693=m
-CONFIG_VIDEO_ATOMISP_LM3554=m
-CONFIG_VIDEO_ZORAN=m
-CONFIG_VIDEO_ZORAN_DC30=y
-CONFIG_VIDEO_ZORAN_ZR36060=y
-CONFIG_VIDEO_ZORAN_BUZ=y
-CONFIG_VIDEO_ZORAN_DC10=y
-CONFIG_VIDEO_ZORAN_LML33=y
-CONFIG_VIDEO_ZORAN_LML33R10=y
-CONFIG_VIDEO_ZORAN_AVS6EYES=y
-CONFIG_VIDEO_IPU3_IMGU=m
-
-#
-# Android
-#
-# end of Android
-
-CONFIG_LTE_GDM724X=m
-CONFIG_FIREWIRE_SERIAL=m
-CONFIG_FWTTY_MAX_TOTAL_PORTS=64
-CONFIG_FWTTY_MAX_CARD_PORTS=32
-CONFIG_GS_FPGABOOT=m
-CONFIG_UNISYSSPAR=y
-CONFIG_FB_TFT=m
+CONFIG_FB_SMSCUFX=m
+CONFIG_FB_SSD1307=m
+CONFIG_FB_SVGALIB=m
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_HELPERS_DEFERRED=y
+CONFIG_FB_SYS_HELPERS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
 CONFIG_FB_TFT_AGM1264K_FL=m
 CONFIG_FB_TFT_BD663474=m
 CONFIG_FB_TFT_HX8340BN=m
@@ -8874,6 +1772,7 @@ CONFIG_FB_TFT_ILI9340=m
 CONFIG_FB_TFT_ILI9341=m
 CONFIG_FB_TFT_ILI9481=m
 CONFIG_FB_TFT_ILI9486=m
+CONFIG_FB_TFT=m
 CONFIG_FB_TFT_PCD8544=m
 CONFIG_FB_TFT_RA8875=m
 CONFIG_FB_TFT_S6D02A1=m
@@ -8885,2693 +1784,4948 @@ CONFIG_FB_TFT_SSD1305=m
 CONFIG_FB_TFT_SSD1306=m
 CONFIG_FB_TFT_SSD1331=m
 CONFIG_FB_TFT_SSD1351=m
-# CONFIG_FB_TFT_ST7735R is not set
 CONFIG_FB_TFT_ST7789V=m
 CONFIG_FB_TFT_TINYLCD=m
 CONFIG_FB_TFT_TLS8204=m
 CONFIG_FB_TFT_UC1611=m
 CONFIG_FB_TFT_UC1701=m
 CONFIG_FB_TFT_UPD161704=m
-CONFIG_FB_TFT_WATTEROTT=m
-CONFIG_MOST_COMPONENTS=m
-CONFIG_MOST_NET=m
-CONFIG_MOST_SOUND=m
-CONFIG_MOST_VIDEO=m
-CONFIG_MOST_I2C=m
-CONFIG_KS7010=m
-CONFIG_GREYBUS_AUDIO=m
+CONFIG_FB_TILEBLITTING=y
+CONFIG_FB_TRIDENT=m
+CONFIG_FB_UDL=m
+CONFIG_FB_UVESA=m
+CONFIG_FB_VGA16=m
+CONFIG_FB_VIA=m
+CONFIG_FB_VIA_X_COMPATIBILITY=y
+CONFIG_FB_VIRTUAL=m
+CONFIG_FB_VOODOO1=m
+CONFIG_FB_VT8623=m
+CONFIG_FCOE_FNIC=m
+CONFIG_FCOE=m
+CONFIG_FIB_RULES=y
+CONFIG_FIELDBUS_DEV=m
+CONFIG_FIREWIRE=m
+CONFIG_FIREWIRE_NET=m
+CONFIG_FIREWIRE_NOSY=m
+CONFIG_FIREWIRE_OHCI=m
+CONFIG_FIREWIRE_SBP2=m
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FONT_6x8=y
+CONFIG_FONTS=y
+CONFIG_FONT_TER16x32=y
+CONFIG_FPGA_BRIDGE=m
+CONFIG_FPGA_DFL_AFU=m
+CONFIG_FPGA_DFL_EMIF=m
+CONFIG_FPGA_DFL_FME_BRIDGE=m
+CONFIG_FPGA_DFL_FME=m
+CONFIG_FPGA_DFL_FME_MGR=m
+CONFIG_FPGA_DFL_FME_REGION=m
+CONFIG_FPGA_DFL=m
+CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
+CONFIG_FPGA_DFL_PCI=m
+CONFIG_FPGA=m
+CONFIG_FPGA_M10_BMC_SEC_UPDATE=m
+CONFIG_FPGA_MGR_ALTERA_CVP=m
+CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
+CONFIG_FPGA_MGR_LATTICE_SYSCONFIG=m
+CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=m
+CONFIG_FPGA_MGR_MACHXO2_SPI=m
+CONFIG_FPGA_MGR_MICROCHIP_SPI=m
+CONFIG_FPGA_MGR_XILINX_SELECTMAP=m
+CONFIG_FPGA_MGR_XILINX_SPI=m
+CONFIG_FPGA_REGION=m
+CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FRONTSWAP=y
+CONFIG_FTL=m
+CONFIG_FUEL_GAUGE_MM8013=m
+CONFIG_FUEL_GAUGE_STC3117=m
+CONFIG_FUJITSU_ES=m
+CONFIG_FUJITSU_LAPTOP=m
+CONFIG_FUJITSU_TABLET=m
+CONFIG_FUNCTION_ALIGNMENT=4
+CONFIG_FUNCTION_ALIGNMENT_4B=y
+CONFIG_FUNCTION_PADDING_BYTES=4
+CONFIG_FUNCTION_PADDING_CFI=0
+CONFIG_FUSION_CTL=m
+CONFIG_FUSION_FC=m
+CONFIG_FUSION_LAN=m
+CONFIG_FUSION_LOGGING=y
+CONFIG_FUSION_MAX_SGE=128
+CONFIG_FUSION_SAS=m
+CONFIG_FUSION_SPI=m
+CONFIG_FUSION=y
+CONFIG_FW_ATTR_CLASS=m
+CONFIG_FW_CFG_SYSFS_CMDLINE=y
+CONFIG_FW_CFG_SYSFS=m
+CONFIG_FW_CS_DSP=m
+CONFIG_FW_LOADER_COMPRESS_XZ=y
+CONFIG_FW_LOADER_COMPRESS=y
+CONFIG_FW_LOADER_COMPRESS_ZSTD=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_FWNODE_MDIO=m
+CONFIG_FW_UPLOAD=y
+CONFIG_FXAS21002C_I2C=m
+CONFIG_FXAS21002C=m
+CONFIG_FXAS21002C_SPI=m
+CONFIG_FXLS8962AF_I2C=m
+CONFIG_FXLS8962AF=m
+CONFIG_FXLS8962AF_SPI=m
+CONFIG_FXOS8700_I2C=m
+CONFIG_FXOS8700=m
+CONFIG_FXOS8700_SPI=m
+CONFIG_GADGET_UAC1=y
+CONFIG_GAMEPORT_EMU10K1=m
+CONFIG_GAMEPORT_FM801=m
+CONFIG_GAMEPORT_L4=m
+CONFIG_GAMEPORT=m
+CONFIG_GAMEPORT_NS558=m
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y
+CONFIG_GCC_VERSION=0
+CONFIG_GENERIC_ADC_BATTERY=m
+CONFIG_GENERIC_ADC_THERMAL=m
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_ENTRY=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_PENDING_IRQ=y
+CONFIG_GENERIC_PHY_MIPI_DPHY=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PTDUMP=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GENERIC_VDSO_TIME_NS=y
+CONFIG_GENEVE=m
+CONFIG_GET_FREE_REGION=y
+CONFIG_GIGABYTE_WMI=m
+CONFIG_GNSS=m
+CONFIG_GNSS_MTK_SERIAL=m
+CONFIG_GNSS_SERIAL=m
+CONFIG_GNSS_SIRF_SERIAL=m
+CONFIG_GNSS_UBX_SERIAL=m
+CONFIG_GNSS_USB=m
+CONFIG_GOOGLE_CBMEM=m
+CONFIG_GOOGLE_COREBOOT_TABLE=m
+CONFIG_GOOGLE_FIRMWARE=y
+CONFIG_GOOGLE_FRAMEBUFFER_COREBOOT=m
+CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m
+CONFIG_GOOGLE_MEMCONSOLE=m
+CONFIG_GOOGLE_MEMCONSOLE_X86_LEGACY=m
+CONFIG_GOOGLE_SMI=m
+CONFIG_GOOGLE_VPD=m
+CONFIG_GP2AP002=m
+CONFIG_GP2AP020A00F=m
+CONFIG_GPD_POCKET_FAN=m
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIO_AGGREGATOR=m
+CONFIG_GPIO_AMD8111=m
+CONFIG_GPIO_AMD_FCH=m
+CONFIG_GPIO_AMDPT=m
+CONFIG_GPIO_ARIZONA=m
+CONFIG_GPIO_BD9571MWV=m
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CROS_EC=m
+CONFIG_GPIO_DA9052=m
+CONFIG_GPIO_DLN2=m
+CONFIG_GPIO_DS4520=m
+CONFIG_GPIO_DWAPB=m
+CONFIG_GPIO_ELKHARTLAKE=m
+CONFIG_GPIO_EXAR=m
+CONFIG_GPIO_F7188X=m
+CONFIG_GPIO_FXL6408=m
+CONFIG_GPIO_GENERIC=m
+CONFIG_GPIO_GENERIC_PLATFORM=m
+CONFIG_GPIO_GRANITERAPIDS=m
+CONFIG_GPIO_ICH=m
+CONFIG_GPIO_IDIO_16=m
+CONFIG_GPIO_IT87=m
+CONFIG_GPIO_JANZ_TTL=m
+CONFIG_GPIO_KEMPLD=m
+CONFIG_GPIO_LATCH=m
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_LJCA=m
+CONFIG_GPIO_LP3943=m
+CONFIG_GPIO_LP873X=m
+CONFIG_GPIO_MADERA=m
+CONFIG_GPIO_MAX3191X=m
+CONFIG_GPIO_MAX7300=m
+CONFIG_GPIO_MAX7301=m
+CONFIG_GPIO_MAX730X=m
+CONFIG_GPIO_MAX732X=m
+CONFIG_GPIO_MB86S7X=m
+CONFIG_GPIO_MC33880=m
+CONFIG_GPIO_MENZ127=m
+CONFIG_GPIO_ML_IOH=m
+CONFIG_GPIO_MOCKUP=m
+CONFIG_GPIO_PCA953X=m
+CONFIG_GPIO_PCA9570=m
+CONFIG_GPIO_PCF857X=m
+CONFIG_GPIO_PCIE_IDIO_24=m
+CONFIG_GPIO_PCI_IDIO_16=m
+CONFIG_GPIO_PISOSR=m
+CONFIG_GPIO_RDC321X=m
+CONFIG_GPIO_REGMAP=m
+CONFIG_GPIO_SCH311X=m
+CONFIG_GPIO_SCH=m
+CONFIG_GPIO_SIM=m
+CONFIG_GPIO_SIOX=m
+CONFIG_GPIO_SYSFS_LEGACY=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_TANGIER=m
+CONFIG_GPIO_TPIC2810=m
+CONFIG_GPIO_TPS65086=m
+CONFIG_GPIO_TPS65912=m
+CONFIG_GPIO_TPS68470=m
+CONFIG_GPIO_TQMX86=m
+CONFIG_GPIO_VIPERBOARD=m
+CONFIG_GPIO_VIRTIO=m
+CONFIG_GPIO_VX855=m
+CONFIG_GPIO_WHISKEY_COVE=m
+CONFIG_GPIO_WINBOND=m
+CONFIG_GPIO_WM831X=m
+CONFIG_GPIO_WM8994=m
+CONFIG_GPIO_WS16C48=m
+CONFIG_GPIO_XRA1403=m
+CONFIG_GP_PCI1XXXX=m
 CONFIG_GREYBUS_AUDIO_APB_CODEC=m
+CONFIG_GREYBUS_AUDIO=m
+CONFIG_GREYBUS_BEAGLEPLAY=m
 CONFIG_GREYBUS_BOOTROM=m
+CONFIG_GREYBUS_BRIDGED_PHY=m
+CONFIG_GREYBUS_ES2=m
 CONFIG_GREYBUS_FIRMWARE=m
+CONFIG_GREYBUS_GPIO=m
 CONFIG_GREYBUS_HID=m
+CONFIG_GREYBUS_I2C=m
 CONFIG_GREYBUS_LIGHT=m
 CONFIG_GREYBUS_LOG=m
 CONFIG_GREYBUS_LOOPBACK=m
+CONFIG_GREYBUS=m
 CONFIG_GREYBUS_POWER=m
-CONFIG_GREYBUS_RAW=m
-CONFIG_GREYBUS_VIBRATOR=m
-CONFIG_GREYBUS_BRIDGED_PHY=m
-CONFIG_GREYBUS_GPIO=m
-CONFIG_GREYBUS_I2C=m
 CONFIG_GREYBUS_PWM=m
+CONFIG_GREYBUS_RAW=m
 CONFIG_GREYBUS_SDIO=m
 CONFIG_GREYBUS_SPI=m
 CONFIG_GREYBUS_UART=m
 CONFIG_GREYBUS_USB=m
-CONFIG_PI433=m
-
-#
-# Gasket devices
-#
-# end of Gasket devices
-
-CONFIG_FIELDBUS_DEV=m
-CONFIG_KPC2000=y
-CONFIG_KPC2000_CORE=m
-CONFIG_KPC2000_SPI=m
-CONFIG_KPC2000_I2C=m
-CONFIG_KPC2000_DMA=m
-CONFIG_QLGE=m
-CONFIG_WFX=m
-CONFIG_RTL8723CS=m
-CONFIG_SPMI_HISI3670=m
-CONFIG_RTL8723CS=m
-CONFIG_X86_PLATFORM_DEVICES=y
-CONFIG_ACPI_WMI=m
-CONFIG_WMI_BMOF=m
-CONFIG_ALIENWARE_WMI=m
-CONFIG_HUAWEI_WMI=m
-CONFIG_INTEL_WMI_SBL_FW_UPDATE=m
-CONFIG_INTEL_WMI_THUNDERBOLT=m
-CONFIG_MXM_WMI=m
-CONFIG_PEAQ_WMI=m
-CONFIG_NVIDIA_WMI_EC_BACKLIGHT=m
-CONFIG_XIAOMI_WMI=m
-CONFIG_GIGABYTE_WMI=m
-CONFIG_YOGABOOK_WMI=m
-CONFIG_ACERHDF=m
-CONFIG_ACER_WIRELESS=m
-CONFIG_ACER_WMI=m
-CONFIG_AMD_PMF=m
-CONFIG_AMD_PMC=m
-CONFIG_AMD_HSMP=m
-CONFIG_ADV_SWBUTTON=m
-CONFIG_APPLE_GMUX=m
-CONFIG_ASUS_LAPTOP=m
-CONFIG_ASUS_WIRELESS=m
-CONFIG_ASUS_WMI=m
-CONFIG_ASUS_NB_WMI=m
-CONFIG_ASUS_TF103C_DOCK=m
-CONFIG_MERAKI_MX100=m
-CONFIG_EEEPC_LAPTOP=m
-CONFIG_EEEPC_WMI=m
-CONFIG_DCDBAS=m
-CONFIG_DELL_SMBIOS=m
-CONFIG_DELL_SMBIOS_WMI=y
-CONFIG_DELL_SMBIOS_SMM=y
-CONFIG_DELL_LAPTOP=m
-CONFIG_DELL_RBTN=m
-CONFIG_DELL_RBU=m
-CONFIG_DELL_SMO8800=m
-CONFIG_DELL_WMI=m
-CONFIG_DELL_WMI_PRIVACY=y
-CONFIG_DELL_WMI_SYSMAN=m
-CONFIG_DELL_WMI_DESCRIPTOR=m
-CONFIG_DELL_WMI_AIO=m
-CONFIG_DELL_WMI_LED=m
-CONFIG_AMILO_RFKILL=m
-CONFIG_FUJITSU_LAPTOP=m
-CONFIG_FUJITSU_TABLET=m
-CONFIG_GPD_POCKET_FAN=m
+CONFIG_GREYBUS_VIBRATOR=m
+CONFIG_GTP=m
+CONFIG_GUEST_PERF_EVENTS=y
+CONFIG_GUP_GET_PXX_LOW_HIGH=y
+CONFIG_HALTPOLL_CPUIDLE=y
+CONFIG_HANGCHECK_TIMER=m
+CONFIG_HARDENED_USERCOPY=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_LTO_CLANG=y
+CONFIG_HD44780_COMMON=m
+CONFIG_HD44780=m
+CONFIG_HDC100X=m
+CONFIG_HDC2010=m
+CONFIG_HDC3020=m
+CONFIG_HDLC_CISCO=m
+CONFIG_HDLC_FR=m
+CONFIG_HDLC=m
+CONFIG_HDLC_PPP=m
+CONFIG_HDLC_RAW_ETH=m
+CONFIG_HDLC_RAW=m
+CONFIG_HDLC_X25=m
+CONFIG_HDMI_LPE_AUDIO=m
+CONFIG_HDMI=y
+CONFIG_HERMES_CACHE_FW_ON_INIT=y
+CONFIG_HERMES=m
+CONFIG_HERMES_PRISM=y
+CONFIG_HI8435=m
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION_COMP_LZO=y
+CONFIG_HIBERNATION_SNAPSHOT_DEV=y
+CONFIG_HIBERNATION=y
+CONFIG_HID_SENSOR_ACCEL_3D=m
+CONFIG_HID_SENSOR_ALS=m
+CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
+CONFIG_HID_SENSOR_DEVICE_ROTATION=m
+CONFIG_HID_SENSOR_GYRO_3D=m
+CONFIG_HID_SENSOR_HUMIDITY=m
+CONFIG_HID_SENSOR_IIO_COMMON=m
+CONFIG_HID_SENSOR_IIO_TRIGGER=m
+CONFIG_HID_SENSOR_INCLINOMETER_3D=m
+CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
+CONFIG_HID_SENSOR_PRESS=m
+CONFIG_HID_SENSOR_PROX=m
+CONFIG_HID_SENSOR_TEMP=m
+CONFIG_HIGHMEM64G=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HMC425=m
+CONFIG_HMC6352=m
+CONFIG_HMEM_REPORTING=y
+CONFIG_HMM_MIRROR=y
+CONFIG_HOSTAP_CS=m
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_PCI=m
+CONFIG_HOSTAP_PLX=m
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CORE_SYNC_FULL=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_PCI_ACPI_IBM=m
+CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m
+CONFIG_HOTPLUG_PCI_CPCI=y
+CONFIG_HOTPLUG_PCI_CPCI_ZT5550=m
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_HOTPLUG_PCI_SHPC=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_SMT=y
+CONFIG_HOTPLUG_SPLIT_STARTUP=y
+CONFIG_HP03=m
+CONFIG_HP206C=m
 CONFIG_HP_ACCEL=m
-CONFIG_WIRELESS_HOTKEY=m
-CONFIG_HP_WIRELESS=m
+CONFIG_HP_BIOSCFG=m
+CONFIG_HPET_EMULATE_RTC=y
+CONFIG_HPET_MMAP_DEFAULT=y
+CONFIG_HPET_MMAP=y
+CONFIG_HPET_TIMER=y
+CONFIG_HPET=y
+CONFIG_HP_ILO=m
+CONFIG_HP_WATCHDOG=m
+CONFIG_HPWDT_NMI_DECODING=y
 CONFIG_HP_WMI=m
-# CONFIG_TC1100_WMI is not set
+CONFIG_HSC030PA=m
+CONFIG_HSI_BOARDINFO=y
+CONFIG_HSI_CHAR=m
+CONFIG_HSI=m
+CONFIG_HSU_DMA=m
+CONFIG_HT16K33=m
+CONFIG_HTE=y
+CONFIG_HTS221_I2C=m
+CONFIG_HTS221=m
+CONFIG_HTS221_SPI=m
+CONFIG_HTU21=m
+CONFIG_HUAWEI_WMI=m
+CONFIG_HWMON_VID=m
+CONFIG_HW_RANDOM_AMD=y
+CONFIG_HW_RANDOM_BA431=y
+CONFIG_HW_RANDOM_GEODE=y
+CONFIG_HW_RANDOM_INTEL=y
+CONFIG_HW_RANDOM_TIMERIOMEM=y
+CONFIG_HW_RANDOM_TPM=y
+CONFIG_HW_RANDOM_VIA=y
+CONFIG_HW_RANDOM_XIPHERA=m
+CONFIG_HW_RANDOM=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HX711=m
+CONFIG_HX9023S=m
+CONFIG_HYPERV_BALLOON=m
+CONFIG_HYPERV_IOMMU=y
+CONFIG_HYPERVISOR_GUEST=y
+CONFIG_HYPERV_KEYBOARD=m
+CONFIG_HYPERV_NET=m
+CONFIG_HYPERV_STORAGE=m
+CONFIG_HYPERV_TIMER=y
+CONFIG_HYPERV_UTILS=m
+CONFIG_HYPERV_VMBUS=m
+CONFIG_HYPERV=y
+CONFIG_HZ=1000
+CONFIG_HZ_1000=y
+CONFIG_I2C_ALGOBIT=m
+CONFIG_I2C_ALGOPCA=m
+CONFIG_I2C_ALI1535=m
+CONFIG_I2C_ALI1563=m
+CONFIG_I2C_ALI15X3=m
+CONFIG_I2C_AMD756=m
+CONFIG_I2C_AMD756_S4882=m
+CONFIG_I2C_AMD8111=m
+CONFIG_I2C_AMD_MP2=m
+CONFIG_I2C_ATR=m
+CONFIG_I2C_CBUS_GPIO=m
+CONFIG_I2C_CCGX_UCSI=m
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_CP2615=m
+CONFIG_I2C_CROS_EC_TUNNEL=m
+CONFIG_I2C_DESIGNWARE_CORE=m
+CONFIG_I2C_DESIGNWARE_PCI=m
+CONFIG_I2C_DESIGNWARE_PLATFORM=m
+CONFIG_I2C_DIOLAN_U2C=m
+CONFIG_I2C_DLN2=m
+CONFIG_I2C_EMEV2=m
+CONFIG_I2C_GPIO=m
+CONFIG_I2C_I801=m
+CONFIG_I2C_ISCH=m
+CONFIG_I2C_ISMT=m
+CONFIG_I2C_KEMPLD=m
+CONFIG_I2C_LJCA=m
+CONFIG_I2C=m
+CONFIG_I2C_MLXCPLD=m
+CONFIG_I2C_MUX_GPIO=m
+CONFIG_I2C_MUX_LTC4306=m
+CONFIG_I2C_MUX=m
+CONFIG_I2C_MUX_MLXCPLD=m
+CONFIG_I2C_MUX_MULE=m
+CONFIG_I2C_MUX_PCA9541=m
+CONFIG_I2C_MUX_PCA954x=m
+CONFIG_I2C_MUX_REG=m
+CONFIG_I2C_NCT6694=m
+CONFIG_I2C_NFORCE2=m
+CONFIG_I2C_NFORCE2_S4985=m
+CONFIG_I2C_NVIDIA_GPU=m
+CONFIG_I2C_OCORES=m
+CONFIG_I2C_PARPORT=m
+CONFIG_I2C_PCA_PLATFORM=m
+CONFIG_I2C_PCI1XXXX=m
+CONFIG_I2C_PIIX4=m
+CONFIG_I2C_ROBOTFUZZ_OSIF=m
+CONFIG_I2C_SCMI=m
+CONFIG_I2C_SI470X=m
+CONFIG_I2C_SI4713=m
+CONFIG_I2C_SIMTEC=m
+CONFIG_I2C_SIS5595=m
+CONFIG_I2C_SIS630=m
+CONFIG_I2C_SIS96X=m
+CONFIG_I2C_SLAVE_EEPROM=m
+CONFIG_I2C_SLAVE_TESTUNIT=m
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SMBUS=m
+CONFIG_I2C_TAOS_EVM=m
+CONFIG_I2C_TINY_USB=m
+CONFIG_I2C_USBIO=m
+CONFIG_I2C_VIA=m
+CONFIG_I2C_VIAPRO=m
+CONFIG_I2C_VIPERBOARD=m
+CONFIG_I2C_VIRTIO=m
+CONFIG_I2C_XILINX=m
+CONFIG_I2C_ZHAOXIN=m
+CONFIG_I3C=m
+CONFIG_I6300ESB_WDT=m
+CONFIG_I82092=m
+CONFIG_I8253_LOCK=y
+CONFIG_IA32_FEAT_CTL=y
+CONFIG_IAQCORE=m
+CONFIG_IB700_WDT=m
+CONFIG_IBM_ASM=m
+CONFIG_IBMASR=m
 CONFIG_IBM_RTL=m
+CONFIG_ICP10100=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_ICS932S401=m
 CONFIG_IDEAPAD_LAPTOP=m
-CONFIG_SENSORS_HDAPS=m
-CONFIG_THINKPAD_ACPI=m
-CONFIG_THINKPAD_ACPI_ALSA_SUPPORT=y
-# CONFIG_THINKPAD_ACPI_DEBUGFACILITIES is not set
-# CONFIG_THINKPAD_ACPI_DEBUG is not set
-# CONFIG_THINKPAD_ACPI_UNSAFE_LEDS is not set
-CONFIG_THINKPAD_ACPI_VIDEO=y
-CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y
-CONFIG_THINKPAD_LMI=m
+CONFIG_IDLE_INJECT=y
+CONFIG_IE6XX_WDT=m
+CONFIG_IFB=m
+CONFIG_IFCVF=m
+CONFIG_IIO_ADIS_LIB_BUFFER=y
+CONFIG_IIO_ADIS_LIB=m
+CONFIG_IIO_BUFFER_CB=m
+CONFIG_IIO_BUFFER_DMAENGINE=m
+CONFIG_IIO_BUFFER_DMA=m
+CONFIG_IIO_BUFFER_HW_CONSUMER=m
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_CONFIGFS=m
+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
+CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
+CONFIG_IIO_CROS_EC_ACTIVITY=m
+CONFIG_IIO_CROS_EC_BARO=m
+CONFIG_IIO_CROS_EC_LIGHT_PROX=m
+CONFIG_IIO_CROS_EC_SENSORS_CORE=m
+CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m
+CONFIG_IIO_CROS_EC_SENSORS=m
+CONFIG_IIO_GTS_HELPER=m
+CONFIG_IIO_HRTIMER_TRIGGER=m
+CONFIG_IIO_INTERRUPT_TRIGGER=m
+CONFIG_IIO_KFIFO_BUF=m
+CONFIG_IIO_KX022A_I2C=m
+CONFIG_IIO_KX022A=m
+CONFIG_IIO_KX022A_SPI=m
+CONFIG_IIO=m
+CONFIG_IIO_MS_SENSORS_I2C=m
+CONFIG_IIO_MUX=m
+CONFIG_IIO_RESCALE=m
+CONFIG_IIO_SSP_SENSORHUB=m
+CONFIG_IIO_SSP_SENSORS_COMMONS=m
+CONFIG_IIO_ST_ACCEL_3AXIS=m
+CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
+CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
+CONFIG_IIO_ST_GYRO_3AXIS=m
+CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
+CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
+CONFIG_IIO_ST_LSM6DSX_I2C=m
+CONFIG_IIO_ST_LSM6DSX_I3C=m
+CONFIG_IIO_ST_LSM6DSX=m
+CONFIG_IIO_ST_LSM6DSX_SPI=m
+CONFIG_IIO_ST_LSM9DS0_I2C=m
+CONFIG_IIO_ST_LSM9DS0=m
+CONFIG_IIO_ST_LSM9DS0_SPI=m
+CONFIG_IIO_ST_MAGN_3AXIS=m
+CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
+CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
+CONFIG_IIO_ST_PRESS_I2C=m
+CONFIG_IIO_ST_PRESS=m
+CONFIG_IIO_ST_PRESS_SPI=m
+CONFIG_IIO_ST_SENSORS_CORE=m
+CONFIG_IIO_ST_SENSORS_I2C=m
+CONFIG_IIO_ST_SENSORS_SPI=m
+CONFIG_IIO_SW_DEVICE=m
+CONFIG_IIO_SW_TRIGGER=m
+CONFIG_IIO_SYSFS_TRIGGER=m
+CONFIG_IIO_TIGHTLOOP_TRIGGER=m
+CONFIG_IIO_TRIGGERED_BUFFER=m
+CONFIG_IIO_TRIGGERED_EVENT=m
+CONFIG_IIO_TRIGGER=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
+CONFIG_ILLEGAL_POINTER_VALUE=0
+CONFIG_IMG_ASCII_LCD=m
+CONFIG_INA2XX_ADC=m
+CONFIG_INFINEON_TLV493D=m
+CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
+CONFIG_INFINIBAND_ADDR_TRANS=y
+CONFIG_INFINIBAND_CXGB4=m
+CONFIG_INFINIBAND_IPOIB_CM=y
+CONFIG_INFINIBAND_IPOIB=m
+CONFIG_INFINIBAND_IRDMA=m
+CONFIG_INFINIBAND_ISER=m
+CONFIG_INFINIBAND_ISERT=m
+CONFIG_INFINIBAND=m
+CONFIG_INFINIBAND_MTHCA=m
+CONFIG_INFINIBAND_OCRDMA=m
+CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
+CONFIG_INFINIBAND_QEDR=m
+CONFIG_INFINIBAND_RTRS_CLIENT=m
+CONFIG_INFINIBAND_RTRS=m
+CONFIG_INFINIBAND_RTRS_SERVER=m
+CONFIG_INFINIBAND_SRP=m
+CONFIG_INFINIBAND_SRPT=m
+CONFIG_INFINIBAND_USER_ACCESS=m
+CONFIG_INFINIBAND_USER_MAD=m
+CONFIG_INFINIBAND_USER_MEM=y
+CONFIG_INFINIBAND_USNIC=m
+CONFIG_INFINIBAND_VMWARE_PVRDMA=m
+CONFIG_INFTL=m
+CONFIG_INIT_STACK_NONE=y
+CONFIG_INPUT_88PM80X_ONKEY=m
+CONFIG_INPUT_AD714X_I2C=m
+CONFIG_INPUT_AD714X=m
+CONFIG_INPUT_AD714X_SPI=m
+CONFIG_INPUT_ADXL34X_I2C=m
+CONFIG_INPUT_ADXL34X=m
+CONFIG_INPUT_ADXL34X_SPI=m
+CONFIG_INPUT_APANEL=m
+CONFIG_INPUT_ARIZONA_HAPTICS=m
+CONFIG_INPUT_ATC260X_ONKEY=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_ATLAS_BTNS=m
+CONFIG_INPUT_AXP20X_PEK=m
+CONFIG_INPUT_BMA150=m
+CONFIG_INPUT_CM109=m
+CONFIG_INPUT_CMA3000_I2C=m
+CONFIG_INPUT_CMA3000=m
+CONFIG_INPUT_CS40L50_VIBRA=m
+CONFIG_INPUT_DA7280_HAPTICS=m
+CONFIG_INPUT_DA9052_ONKEY=m
+CONFIG_INPUT_DA9063_ONKEY=m
+CONFIG_INPUT_DRV260X_HAPTICS=m
+CONFIG_INPUT_DRV2665_HAPTICS=m
+CONFIG_INPUT_DRV2667_HAPTICS=m
+CONFIG_INPUT_E3X0_BUTTON=m
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_GPIO_BEEPER=m
+CONFIG_INPUT_GPIO_DECODER=m
+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
+CONFIG_INPUT_GPIO_VIBRA=m
+CONFIG_INPUT_IBM_PANEL=m
+CONFIG_INPUT_IDEAPAD_SLIDEBAR=m
+CONFIG_INPUT_IMS_PCU=m
+CONFIG_INPUT_IQS269A=m
+CONFIG_INPUT_IQS626A=m
+CONFIG_INPUT_IQS7222=m
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_KXTJ9=m
+CONFIG_INPUT_LEDS=m
+CONFIG_INPUT_MATRIXKMAP=m
+CONFIG_INPUT_MAX7360_ROTARY=m
+CONFIG_INPUT_MAX77693_HAPTIC=m
+CONFIG_INPUT_MC13783_PWRBUTTON=m
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MMA8450=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_PCAP=m
+CONFIG_INPUT_PCF50633_PMU=m
+CONFIG_INPUT_PCF8574=m
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_PWM_BEEPER=m
+CONFIG_INPUT_PWM_VIBRA=m
+CONFIG_INPUT_QNAP_MCU=m
+CONFIG_INPUT_RAVE_SP_PWRBUTTON=m
+CONFIG_INPUT_REGULATOR_HAPTIC=m
+CONFIG_INPUT_RETU_PWRBUTTON=m
+CONFIG_INPUT_RT5120_PWRKEY=m
+CONFIG_INPUT_SOC_BUTTON_ARRAY=m
+CONFIG_INPUT_SPARSEKMAP=m
+CONFIG_INPUT_TABLET=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_UINPUT=m
+CONFIG_INPUT_VIVALDIFMAP=y
+CONFIG_INPUT_WM831X_ON=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INSPUR_PLATFORM_PROFILE=m
+CONFIG_INSTRUCTION_DECODER=y
 CONFIG_INTEL_ATOMISP2_LED=m
-CONFIG_INTEL_SAR_INT1092=m
-CONFIG_INTEL_SKL_INT3472=m
-CONFIG_INTEL_CHT_INT33FE=m
-CONFIG_INTEL_HID_EVENT=m
-CONFIG_INTEL_INT0002_VGPIO=m
-CONFIG_INTEL_MENLOW=m
-CONFIG_INTEL_HFI_THERMAL=y
-CONFIG_INTEL_OAKTRAIL=m
-CONFIG_INTEL_VBTN=m
-CONFIG_SURFACE3_WMI=m
-CONFIG_SURFACE_KBD=m
-CONFIG_SURFACE_3_BUTTON=m
-CONFIG_SURFACE_DTX=m
-CONFIG_SURFACE_3_POWER_OPREGION=m
-CONFIG_SURFACE_ACPI_NOTIFY=m
-CONFIG_SURFACE_AGGREGATOR_CDEV=m
-CONFIG_SURFACE_AGGREGATOR_HUB=m
-CONFIG_SURFACE_AGGREGATOR_REGISTRY=m
-CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m
-CONFIG_SURFACE_PRO3_BUTTON=m
-CONFIG_MSI_LAPTOP=m
-CONFIG_MSI_WMI=m
-CONFIG_PCENGINES_APU2=m
-CONFIG_BARCO_P50_GPIO=m
-CONFIG_SAMSUNG_LAPTOP=m
-CONFIG_SAMSUNG_Q10=m
-CONFIG_ACPI_TOSHIBA=m
-CONFIG_TOSHIBA_BT_RFKILL=m
-CONFIG_TOSHIBA_HAPS=m
-CONFIG_TOSHIBA_WMI=m
-CONFIG_ACPI_CMPC=m
-CONFIG_COMPAL_LAPTOP=m
-CONFIG_LG_LAPTOP=m
-CONFIG_PANASONIC_LAPTOP=m
-CONFIG_SONY_LAPTOP=m
-CONFIG_SONYPI_COMPAT=y
-CONFIG_SYSTEM76_ACPI=m
-CONFIG_TOPSTAR_LAPTOP=m
-CONFIG_SERIAL_MULTI_INSTANTIATE=m
-CONFIG_I2C_MULTI_INSTANTIATE=m
-CONFIG_MLX_PLATFORM=m
-CONFIG_X86_ANDROID_TABLETS=m
-CONFIG_INTEL_IPS=m
-CONFIG_INTEL_RST=m
-CONFIG_INTEL_SDSI=m
-CONFIG_INTEL_SMARTCONNECT=m
-CONFIG_INTEL_VSEC=m
+CONFIG_INTEL_ATOMISP2_PDX86=y
+CONFIG_INTEL_ATOMISP=y
+CONFIG_INTEL_BXT_PMIC_THERMAL=m
 CONFIG_INTEL_BXTWC_PMIC_TMU=m
 CONFIG_INTEL_CHTWC_INT33FE=m
-CONFIG_INTEL_CHTDC_TI_PWRBTN=m
-CONFIG_INTEL_ISHTP_ECLITE=m
-CONFIG_INTEL_MID_POWER_BUTTON=m
-CONFIG_INTEL_MRFLD_PWRBTN=m
-CONFIG_INTEL_PMC_CORE=y
-CONFIG_INTEL_PMT_CLASS=m
-CONFIG_INTEL_PMT_TELEMETRY=m
-CONFIG_INTEL_PMT_CRASHLOG=m
-CONFIG_INTEL_PUNIT_IPC=m
-CONFIG_INTEL_SCU_IPC=y
-CONFIG_SIEMENS_SIMATIC_IPC=m
-CONFIG_INTEL_SCU=y
-CONFIG_INTEL_SCU_PCI=y
-CONFIG_INTEL_SCU_PLATFORM=m
-CONFIG_INTEL_SCU_IPC_UTIL=m
-CONFIG_ICST=y
-CONFIG_CLK_SP810=y
-CONFIG_PMC_ATOM=y
-CONFIG_CHROME_PLATFORMS=y
-CONFIG_CHROMEOS_LAPTOP=m
-CONFIG_CHROMEOS_PSTORE=m
-CONFIG_CHROMEOS_TBMC=m
-CONFIG_CROS_EC=m
-CONFIG_CROS_EC_I2C=m
-CONFIG_CROS_EC_SPI=m
-CONFIG_CROS_EC_LPC=m
-CONFIG_CROS_EC_PROTO=y
-CONFIG_CROS_KBD_LED_BACKLIGHT=m
-CONFIG_CROS_EC_CHARDEV=m
-CONFIG_CROS_EC_LIGHTBAR=m
-CONFIG_CROS_EC_DEBUGFS=m
-CONFIG_CROS_EC_SENSORHUB=m
-CONFIG_CROS_EC_SYSFS=m
-CONFIG_CROS_EC_TYPEC=m
-CONFIG_CROS_USBPD_LOGGER=m
-CONFIG_CROS_USBPD_NOTIFY=m
-CONFIG_CHROMEOS_PRIVACY_SCREEN=m
-CONFIG_CROS_TYPEC_SWITCH=m
-CONFIG_WILCO_EC=m
-CONFIG_WILCO_EC_DEBUGFS=m
-CONFIG_WILCO_EC_EVENTS=m
-CONFIG_WILCO_EC_TELEMETRY=m
-CONFIG_MELLANOX_PLATFORM=y
-CONFIG_MLXREG_HOTPLUG=m
-CONFIG_MLXREG_IO=m
-CONFIG_MLXREG_LC=m
-CONFIG_HAVE_CLK=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_WM831X=m
-CONFIG_LMK04832=m
-CONFIG_COMMON_CLK_APPLE_NCO=m
-CONFIG_COMMON_CLK_MAX9485=m
-CONFIG_COMMON_CLK_SI5341=m
-CONFIG_COMMON_CLK_SI5351=m
-CONFIG_COMMON_CLK_SI544=m
-CONFIG_COMMON_CLK_CDCE706=m
-CONFIG_COMMON_CLK_TPS68470=m
-CONFIG_COMMON_CLK_CS2000_CP=m
-CONFIG_COMMON_CLK_PWM=m
-CONFIG_COMMON_CLK_RS9_PCIE=m
-CONFIG_HWSPINLOCK=y
-
-#
-# Clock Source drivers
-#
-CONFIG_CLKSRC_I8253=y
-CONFIG_CLKEVT_I8253=y
-CONFIG_I8253_LOCK=y
-CONFIG_CLKBLD_I8253=y
-# end of Clock Source drivers
-
-CONFIG_MAILBOX=y
-CONFIG_PCC=y
-CONFIG_ALTERA_MBOX=m
-CONFIG_IOMMU_IOVA=y
-CONFIG_IOASID=y
-CONFIG_IOMMU_API=y
-CONFIG_IOMMU_SUPPORT=y
-
-#
-# Generic IOMMU Pagetable Support
-#
-# end of Generic IOMMU Pagetable Support
-
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_DMAR_TABLE=y
-CONFIG_INTEL_IOMMU=y
-# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set
+CONFIG_INTEL_GTT=m
+CONFIG_INTEL_HFI_THERMAL=y
+CONFIG_INTEL_HID_EVENT=m
+CONFIG_INTEL_IDLE=y
+CONFIG_INTEL_IDMA64=m
+CONFIG_INTEL_INT0002_VGPIO=m
 CONFIG_INTEL_IOMMU_FLOPPY_WA=y
-# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set
-CONFIG_HYPERV_IOMMU=y
-CONFIG_VIRTIO_IOMMU=m
-
-#
-# Remoteproc drivers
-#
-# CONFIG_REMOTEPROC is not set
-# end of Remoteproc drivers
-
-#
-# Rpmsg drivers
-#
-CONFIG_RPMSG=m
-CONFIG_RPMSG_CHAR=m
-CONFIG_RPMSG_CTRL=m
-CONFIG_RPMSG_QCOM_GLINK=m
-CONFIG_RPMSG_QCOM_GLINK_RPM=m
-CONFIG_RPMSG_VIRTIO=m
-# end of Rpmsg drivers
-
-CONFIG_SOUNDWIRE=y
-
-#
-# SoundWire Devices
-#
-CONFIG_SOUNDWIRE_CADENCE=m
-CONFIG_SOUNDWIRE_INTEL=m
-CONFIG_SOUNDWIRE_QCOM=m
-CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=m
-
-#
-# SOC (System On Chip) specific Drivers
-#
-
-#
-# Amlogic SoC drivers
-#
-# end of Amlogic SoC drivers
-
-#
-# Aspeed SoC drivers
-#
-# end of Aspeed SoC drivers
-
-#
-# Broadcom SoC drivers
-#
-# end of Broadcom SoC drivers
-
-#
-# NXP/Freescale QorIQ SoC drivers
-#
-# end of NXP/Freescale QorIQ SoC drivers
-
-#
-# i.MX SoC drivers
-#
-# end of i.MX SoC drivers
-
-#
-# Qualcomm SoC drivers
-#
-CONFIG_QCOM_QMI_HELPERS=m
-# end of Qualcomm SoC drivers
-
-# CONFIG_SOC_TI is not set
-
-#
-# Xilinx SoC drivers
-#
-# CONFIG_XILINX_VCU is not set
-# end of Xilinx SoC drivers
-# end of SOC (System On Chip) specific Drivers
-
-CONFIG_PM_DEVFREQ=y
-
-#
-# DEVFREQ Governors
-#
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_PERFORMANCE=y
-CONFIG_DEVFREQ_GOV_POWERSAVE=y
-CONFIG_DEVFREQ_GOV_USERSPACE=y
-CONFIG_DEVFREQ_GOV_PASSIVE=m
-
-#
-# DEVFREQ Drivers
-#
-CONFIG_PM_DEVFREQ_EVENT=y
-CONFIG_EXTCON=y
-
-#
-# Extcon Device Drivers
-#
-CONFIG_EXTCON_ADC_JACK=m
-CONFIG_EXTCON_ARIZONA=m
-CONFIG_EXTCON_AXP288=m
-CONFIG_EXTCON_FSA9480=m
-CONFIG_EXTCON_GPIO=m
-CONFIG_EXTCON_INTEL_INT3496=m
-CONFIG_EXTCON_INTEL_MRFLD=m
-CONFIG_EXTCON_MAX14577=m
-CONFIG_EXTCON_MAX3355=m
-CONFIG_EXTCON_MAX77693=m
-CONFIG_EXTCON_PTN5150=m
-CONFIG_EXTCON_RT8973A=m
-CONFIG_EXTCON_SM5502=m
-CONFIG_EXTCON_USB_GPIO=m
-CONFIG_EXTCON_USBC_CROS_EC=m
-CONFIG_EXTCON_USBC_TUSB320=m
-CONFIG_MEMORY=y
-CONFIG_FPGA_DFL_EMIF=m
-CONFIG_IIO=m
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_BUFFER_CB=m
-CONFIG_IIO_BUFFER_DMA=m
-CONFIG_IIO_BUFFER_DMAENGINE=m
-CONFIG_IIO_BUFFER_HW_CONSUMER=m
-CONFIG_IIO_KFIFO_BUF=m
-CONFIG_IIO_TRIGGERED_BUFFER=m
-CONFIG_IIO_CONFIGFS=m
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
-CONFIG_IIO_SW_DEVICE=m
-CONFIG_IIO_SW_TRIGGER=m
-CONFIG_IIO_TRIGGERED_EVENT=m
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16201=m
-CONFIG_ADIS16209=m
-CONFIG_ADXL372=m
-CONFIG_ADXL372_SPI=m
-CONFIG_ADXL372_I2C=m
-CONFIG_BMA220=m
-CONFIG_BMA400=m
-CONFIG_BMA400_I2C=m
-CONFIG_BMA400_SPI=m
-CONFIG_BMC150_ACCEL=m
-CONFIG_BMI088_ACCEL=m
-CONFIG_TI_ADS131E08=m
-CONFIG_BMC150_ACCEL_I2C=m
-CONFIG_BMC150_ACCEL_SPI=m
-CONFIG_DA280=m
-CONFIG_DA311=m
-CONFIG_DMARD09=m
-CONFIG_DMARD10=m
-CONFIG_FXLS8962AF_SPI=m
-CONFIG_FXLS8962AF_I2C=m
-CONFIG_HID_SENSOR_ACCEL_3D=m
-CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
-CONFIG_IIO_ST_ACCEL_3AXIS=m
-CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
-CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
+CONFIG_INTEL_IOMMU_PERF_EVENTS=y
+CONFIG_INTEL_IOMMU=y
+CONFIG_INTEL_IPS=m
+CONFIG_INTEL_LDMA=y
+CONFIG_INTEL_MEI_GSC=m
+CONFIG_INTEL_MEI_GSC_PROXY=m
+CONFIG_INTEL_MEI_HDCP=m
+CONFIG_INTEL_MEI_LB=m
+CONFIG_INTEL_MEI_ME=y
+CONFIG_INTEL_MEI_PXP=m
+CONFIG_INTEL_MEI_TXE=m
+CONFIG_INTEL_MEI_VSC_HW=m
+CONFIG_INTEL_MEI_VSC=m
+CONFIG_INTEL_MEI_WDT=m
+CONFIG_INTEL_MEI=y
+CONFIG_INTEL_MRFLD_ADC=m
+CONFIG_INTEL_MRFLD_PWRBTN=m
+CONFIG_INTEL_OAKTRAIL=m
+CONFIG_INTEL_OC_WATCHDOG=m
+CONFIG_INTEL_PCH_THERMAL=m
+CONFIG_INTEL_PMC_CORE=y
+CONFIG_INTEL_PMT_CLASS=m
+CONFIG_INTEL_PMT_CRASHLOG=m
+CONFIG_INTEL_PMT_TELEMETRY=m
+CONFIG_INTEL_POWERCLAMP=m
+CONFIG_INTEL_PUNIT_IPC=m
+CONFIG_INTEL_QEP=m
+CONFIG_INTEL_RAPL_CORE=m
+CONFIG_INTEL_RAPL=m
+CONFIG_INTEL_RST=m
+CONFIG_INTEL_SAR_INT1092=m
+CONFIG_INTEL_SCU_IPC_UTIL=m
+CONFIG_INTEL_SCU_IPC=y
+CONFIG_INTEL_SCU_PCI=y
+CONFIG_INTEL_SCU_PLATFORM=m
+CONFIG_INTEL_SCU=y
+CONFIG_INTEL_SKL_INT3472=m
+CONFIG_INTEL_SMARTCONNECT=m
+CONFIG_INTEL_SOC_DTS_IOSF_CORE=m
+CONFIG_INTEL_SOC_DTS_THERMAL=m
+CONFIG_INTEL_SOC_PMIC_BXTWC=m
+CONFIG_INTEL_SOC_PMIC_MRFLD=m
+CONFIG_INTEL_TCC_COOLING=m
+CONFIG_INTEL_TCC=y
+CONFIG_INTEL_TH_ACPI=m
+CONFIG_INTEL_TH_GTH=m
+CONFIG_INTEL_TH=m
+CONFIG_INTEL_TH_MSU=m
+CONFIG_INTEL_TH_PCI=m
+CONFIG_INTEL_TH_PTI=m
+CONFIG_INTEL_TH_STH=m
+CONFIG_INTEL_TXT=y
+CONFIG_INTEL_VBTN=m
+CONFIG_INTEL_VSC=m
+CONFIG_INTEL_VSEC=m
+CONFIG_INTEL_WMI_SBL_FW_UPDATE=m
+CONFIG_INTEL_WMI_THUNDERBOLT=m
+CONFIG_INTEL_WMI=y
+CONFIG_INTEL_XWAY_PHY=m
+CONFIG_INTERRUPT_CNT=m
+CONFIG_INTERVAL_TREE_SPAN_ITER=y
+CONFIG_INV_ICM42600_I2C=m
+CONFIG_INV_ICM42600=m
+CONFIG_INV_ICM42600_SPI=m
+CONFIG_INV_MPU6050_I2C=m
+CONFIG_INV_MPU6050_IIO=m
+CONFIG_INV_MPU6050_SPI=m
+CONFIG_IO_DELAY_0X80=y
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMUFD=m
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOSCHED_BFQ=y
+CONFIG_IOSF_MBI=y
+CONFIG_IOSM=m
+CONFIG_IP5XXX_POWER=m
+CONFIG_IPACK_BUS=m
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_DMI_DECODE=y
+CONFIG_IPMI_HANDLER=m
+CONFIG_IPMI_IPMB=m
+CONFIG_IPMI_PANIC_EVENT=y
+CONFIG_IPMI_PANIC_STRING=y
+CONFIG_IPMI_PLAT_DATA=y
+CONFIG_IPMI_POWEROFF=m
+CONFIG_IPMI_SI=m
+CONFIG_IPMI_SSIF=m
+CONFIG_IPMI_WATCHDOG=m
+CONFIG_IPU_BRIDGE=m
+CONFIG_IPVLAN_L3S=y
+CONFIG_IPVLAN=m
+CONFIG_IPVTAP=m
+CONFIG_IPW2100=m
+CONFIG_IPW2100_MONITOR=y
+CONFIG_IPW2200=m
+CONFIG_IPW2200_MONITOR=y
+CONFIG_IPW2200_PROMISCUOUS=y
+CONFIG_IPW2200_QOS=y
+CONFIG_IPW2200_RADIOTAP=y
+CONFIG_IPWIRELESS=m
+CONFIG_IQS620AT_TEMP=m
+CONFIG_IQS621_ALS=m
+CONFIG_IQS624_POS=m
+CONFIG_IR_ENE=m
+CONFIG_IR_FINTEK=m
+CONFIG_IR_IGORPLUGUSB=m
+CONFIG_IR_IGUANA=m
+CONFIG_IR_IMON_DECODER=m
+CONFIG_IR_IMON=m
+CONFIG_IR_IMON_RAW=m
+CONFIG_IR_ITE_CIR=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_IR_MCEUSB=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_NUVOTON=m
+CONFIG_IRQ_BYPASS_MANAGER=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_POLL=y
+CONFIG_IRQ_SIM=y
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_RCMM_DECODER=m
+CONFIG_IR_REDRAT3=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IRSD200=m
+CONFIG_IR_SERIAL=m
+CONFIG_IR_SERIAL_TRANSMITTER=y
+CONFIG_IR_SHARP_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_STREAMZAP=m
+CONFIG_IR_TOY=m
+CONFIG_IR_TTUSBIR=m
+CONFIG_IR_WINBOND_CIR=m
+CONFIG_IR_XMP_DECODER=m
+CONFIG_ISA_BUS_API=y
+CONFIG_ISA_DMA_API=y
+CONFIG_ISAPNP=y
+CONFIG_ISA=y
+CONFIG_ISCSI_BOOT_SYSFS=m
+CONFIG_ISCSI_IBFT_FIND=y
+CONFIG_ISCSI_IBFT=m
+CONFIG_ISCSI_TARGET_CXGB4=m
+CONFIG_ISCSI_TARGET=m
+CONFIG_ISCSI_TCP=m
+CONFIG_ISDN_CAPI_MIDDLEWARE=y
+CONFIG_ISDN_CAPI=y
+CONFIG_ISDN=y
+CONFIG_ISL29003=m
+CONFIG_ISL29020=m
+CONFIG_ISL29125=m
+CONFIG_ISL29501=m
+CONFIG_ISL76682=m
+CONFIG_IT8712F_WDT=m
+CONFIG_IT87_WDT=m
+CONFIG_ITCO_VENDOR_SUPPORT=y
+CONFIG_ITCO_WDT=m
+CONFIG_ITG3200=m
+CONFIG_IWL3945=m
+CONFIG_IWL4965=m
+CONFIG_IWLDVM=m
+CONFIG_IWLEGACY=m
+CONFIG_IWLMLD=m
+CONFIG_IWLMVM=m
+CONFIG_IWLWIFI_LEDS=y
+CONFIG_IWLWIFI=m
+CONFIG_IWLWIFI_OPMODE_MODULAR=y
+CONFIG_JOYSTICK_A3D=m
+CONFIG_JOYSTICK_ADC=m
+CONFIG_JOYSTICK_ADI=m
+CONFIG_JOYSTICK_ANALOG=m
+CONFIG_JOYSTICK_AS5011=m
+CONFIG_JOYSTICK_COBRA=m
+CONFIG_JOYSTICK_DB9=m
+CONFIG_JOYSTICK_FSIA6B=m
+CONFIG_JOYSTICK_GAMECON=m
+CONFIG_JOYSTICK_GF2K=m
+CONFIG_JOYSTICK_GRIP=m
+CONFIG_JOYSTICK_GRIP_MP=m
+CONFIG_JOYSTICK_GUILLEMOT=m
+CONFIG_JOYSTICK_IFORCE_232=m
+CONFIG_JOYSTICK_IFORCE=m
+CONFIG_JOYSTICK_IFORCE_USB=m
+CONFIG_JOYSTICK_INTERACT=m
+CONFIG_JOYSTICK_MAGELLAN=m
+CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
+CONFIG_JOYSTICK_PSXPAD_SPI=m
+CONFIG_JOYSTICK_PXRC=m
+CONFIG_JOYSTICK_QWIIC=m
+CONFIG_JOYSTICK_SEESAW=m
+CONFIG_JOYSTICK_SENSEHAT=m
+CONFIG_JOYSTICK_SIDEWINDER=m
+CONFIG_JOYSTICK_SPACEBALL=m
+CONFIG_JOYSTICK_SPACEORB=m
+CONFIG_JOYSTICK_STINGER=m
+CONFIG_JOYSTICK_TMDC=m
+CONFIG_JOYSTICK_TURBOGRAFX=m
+CONFIG_JOYSTICK_TWIDJOY=m
+CONFIG_JOYSTICK_WALKERA0701=m
+CONFIG_JOYSTICK_WARRIOR=m
+CONFIG_JOYSTICK_XPAD_FF=y
+CONFIG_JOYSTICK_XPAD_LEDS=y
+CONFIG_JOYSTICK_XPAD=m
+CONFIG_JOYSTICK_ZHENHUA=m
+CONFIG_JSA1212=m
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KARMA_PARTITION=y
+CONFIG_KCMP=y
+CONFIG_KEMPLD_WDT=m
+CONFIG_KERNEL_ZSTD=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEXEC_JUMP=y
+CONFIG_KEXEC=y
+CONFIG_KEYBOARD_ADC=m
+CONFIG_KEYBOARD_ADP5588=m
+CONFIG_KEYBOARD_ADP5589=m
+CONFIG_KEYBOARD_APPLESPI=m
+CONFIG_KEYBOARD_CROS_EC=m
+CONFIG_KEYBOARD_CYPRESS_SF=m
+CONFIG_KEYBOARD_DLINK_DIR685=m
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_KEYBOARD_GPIO_POLLED=m
+CONFIG_KEYBOARD_IQS62X=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_LM8323=m
+CONFIG_KEYBOARD_LM8333=m
+CONFIG_KEYBOARD_MATRIX=m
+CONFIG_KEYBOARD_MAX7359=m
+CONFIG_KEYBOARD_MCS=m
+CONFIG_KEYBOARD_MPR121=m
+CONFIG_KEYBOARD_MTK_PMIC=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_OPENCORES=m
+CONFIG_KEYBOARD_PINEPHONE=m
+CONFIG_KEYBOARD_QT1050=m
+CONFIG_KEYBOARD_QT1070=m
+CONFIG_KEYBOARD_QT2160=m
+CONFIG_KEYBOARD_SAMSUNG=m
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_TCA6416=m
+CONFIG_KEYBOARD_TCA8418=m
+CONFIG_KEYBOARD_TM2_TOUCHKEY=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEY_DH_OPERATIONS=y
+CONFIG_KEYS_REQUEST_CACHE=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMX61=m
+CONFIG_KRETPROBE_ON_RETHOOK=y
+CONFIG_KRETPROBES=y
+CONFIG_KS0108_DELAY=2
+CONFIG_KS0108=m
+CONFIG_KS0108_PORT=0x378
+CONFIG_KS7010=m
+CONFIG_KSM=y
+CONFIG_KUNPENG_HCCS=m
+CONFIG_KVM_AMD=m
+CONFIG_KVM_ASYNC_PF=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y
+CONFIG_KVM_GUEST=y
+CONFIG_KVM_HYPERV=y
+CONFIG_KVM_INTEL=m
+CONFIG_KVM_IOAPIC=y
+CONFIG_KVM_MAX_NR_VCPUS=1024
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_PROVE_MMU=y
+CONFIG_KVM_SMM=y
+CONFIG_KVM_VFIO=y
+CONFIG_KVM_WERROR=y
+CONFIG_KVM_XEN=y
+CONFIG_KVM_XFER_TO_GUEST_WORK=y
+CONFIG_KVM=y
+CONFIG_KXCJK1013=m
+CONFIG_KXSD9_I2C=m
 CONFIG_KXSD9=m
 CONFIG_KXSD9_SPI=m
-CONFIG_KXSD9_I2C=m
-CONFIG_KXCJK1013=m
-CONFIG_MC3230=m
-CONFIG_MMA7455=m
-CONFIG_MMA7455_I2C=m
-CONFIG_MMA7455_SPI=m
-CONFIG_MMA7660=m
-CONFIG_MMA8452=m
-CONFIG_MMA9551_CORE=m
-CONFIG_MMA9551=m
-CONFIG_MMA9553=m
-CONFIG_MSA311=m
-CONFIG_MXC4005=m
-CONFIG_MXC6255=m
-CONFIG_SCA3000=m
-CONFIG_SCA3300=m
-CONFIG_STK8312=m
-CONFIG_STK8BA50=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD_SIGMA_DELTA=m
-CONFIG_AD7091R5=m
-CONFIG_AD7124=m
-CONFIG_AD7192=m
-CONFIG_AD7266=m
-CONFIG_AD7291=m
-CONFIG_AD7292=m
-CONFIG_AD7298=m
-CONFIG_AD7476=m
-CONFIG_AD7606=m
-CONFIG_AD7606_IFACE_PARALLEL=m
-CONFIG_AD7606_IFACE_SPI=m
-CONFIG_AD7766=m
-CONFIG_AD7768_1=m
-CONFIG_AD7780=m
-CONFIG_AD7791=m
-CONFIG_AD7793=m
-CONFIG_AD7887=m
-CONFIG_AD7923=m
-CONFIG_AD7949=m
-CONFIG_AD799X=m
-CONFIG_AD9467=m
-CONFIG_ADI_AXI_ADC=m
-CONFIG_AXP20X_ADC=m
-CONFIG_AXP288_ADC=m
-CONFIG_CC10001_ADC=m
-CONFIG_DA9150_GPADC=m
-CONFIG_DLN2_ADC=m
-CONFIG_ENVELOPE_DETECTOR=m
-CONFIG_HI8435=m
-CONFIG_HX711=m
-CONFIG_INA2XX_ADC=m
-CONFIG_INTEL_MRFLD_ADC=m
+CONFIG_LAPBETHER=m
+CONFIG_LATENCYTOP=y
+CONFIG_LATTICE_ECP3_CONFIG=m
+CONFIG_LCD2S=m
+CONFIG_LCD_AMS369FG06=m
+CONFIG_LCD_CLASS_DEVICE=m
+CONFIG_LCD_HX8357=m
+CONFIG_LCD_ILI922X=m
+CONFIG_LCD_ILI9320=m
+CONFIG_LCD_L4F00242T03=m
+CONFIG_LCD_LMS283GF05=m
+CONFIG_LCD_LMS501KF03=m
+CONFIG_LCD_LTV350QV=m
+CONFIG_LCD_OTM3225A=m
+CONFIG_LCD_PLATFORM=m
+CONFIG_LCD_TDO24M=m
+CONFIG_LCD_VGG2432A4=m
+CONFIG_LD_IS_LLD=y
+CONFIG_LDM_DEBUG=y
+CONFIG_LDM_PARTITION=y
+CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
+CONFIG_LD_ORPHAN_WARN=y
+CONFIG_LD_VERSION=0
+CONFIG_LEDS_APU=m
+CONFIG_LEDS_AS3645A=m
+CONFIG_LEDS_AW200XX=m
+CONFIG_LEDS_BD2606MVV=m
+CONFIG_LEDS_BD2802=m
+CONFIG_LEDS_BLINKM=m
+CONFIG_LEDS_CLASS_FLASH=m
+CONFIG_LEDS_CLASS_MULTICOLOR=m
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CROS_EC=m
+CONFIG_LEDS_DA9052=m
+CONFIG_LEDS_DAC124S085=m
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_GROUP_MULTICOLOR=m
+CONFIG_LEDS_INTEL_SS4200=m
+CONFIG_LEDS_IS31FL319X=m
+CONFIG_LEDS_KTD202X=m
+CONFIG_LEDS_LM3530=m
+CONFIG_LEDS_LM3532=m
+CONFIG_LEDS_LM3533=m
+CONFIG_LEDS_LM355x=m
+CONFIG_LEDS_LM3601X=m
+CONFIG_LEDS_LM36274=m
+CONFIG_LEDS_LM3642=m
+CONFIG_LEDS_LP3944=m
+CONFIG_LEDS_LP3952=m
+CONFIG_LEDS_LP50XX=m
+CONFIG_LEDS_LT3593=m
+CONFIG_LEDS_MAX5970=m
+CONFIG_LEDS_MC13783=m
+CONFIG_LEDS_MENF21BMC=m
+CONFIG_LEDS_MLXCPLD=m
+CONFIG_LEDS_MLXREG=m
+CONFIG_LEDS_MT6323=m
+CONFIG_LEDS_MT6370_FLASH=m
+CONFIG_LEDS_MT6370_RGB=m
+CONFIG_LEDS_NCP5623=m
+CONFIG_LEDS_NIC78BX=m
+CONFIG_LEDS_PCA9532_GPIO=y
+CONFIG_LEDS_PCA9532=m
+CONFIG_LEDS_PCA955X=m
+CONFIG_LEDS_PCA963X=m
+CONFIG_LEDS_PCA995X=m
+CONFIG_LEDS_PWM=m
+CONFIG_LEDS_PWM_MULTICOLOR=m
+CONFIG_LEDS_REGULATOR=m
+CONFIG_LEDS_RT8515=m
+CONFIG_LEDS_SGM3140=m
+CONFIG_LEDS_SIEMENS_SIMATIC_IPC_APOLLOLAKE=m
+CONFIG_LEDS_SIEMENS_SIMATIC_IPC_ELKHARTLAKE=m
+CONFIG_LEDS_SIEMENS_SIMATIC_IPC_F7188X=m
+CONFIG_LEDS_SIEMENS_SIMATIC_IPC=m
+CONFIG_LEDS_SPI_BYTE=m
+CONFIG_LEDS_ST1202=m
+CONFIG_LEDS_SUN50I_A100=m
+CONFIG_LEDS_SY7802=m
+CONFIG_LEDS_TCA6507=m
+CONFIG_LEDS_TI_LMU_COMMON=m
+CONFIG_LEDS_TLC591XX=m
+CONFIG_LEDS_TPS6105X=m
+CONFIG_LEDS_TRIGGER_ACTIVITY=m
+CONFIG_LEDS_TRIGGER_AUDIO=m
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_CAMERA=m
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_GPIO=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_NETDEV=m
+CONFIG_LEDS_TRIGGER_ONESHOT=m
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEDS_TRIGGER_PATTERN=m
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_TRANSIENT=m
+CONFIG_LEDS_TRIGGER_TTY=m
+CONFIG_LEDS_UPBOARD=m
+CONFIG_LEDS_USER=m
+CONFIG_LEDS_WM831X_STATUS=m
+CONFIG_LENOVO_SE10_WDT=m
+CONFIG_LENOVO_SE30_WDT=m
+CONFIG_LENOVO_WMI_CAMERA=m
+CONFIG_LENOVO_WMI_GAMEZONE=m
+CONFIG_LENOVO_WMI_HOTKEY_UTILITIES=m
+CONFIG_LENOVO_YMC=m
+CONFIG_LG_LAPTOP=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211=m
+CONFIG_LIBCRC32C=m
+CONFIG_LIBERTAS_CS=m
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_MESH=y
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+CONFIG_LIBERTAS_THINFIRM=m
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBFC=m
+CONFIG_LIBFCOE=m
+CONFIG_LIBIPW=m
+CONFIG_LIBNVDIMM=m
+CONFIG_LIDAR_LITE_V2=m
+CONFIG_LINEAR_RANGES=y
+CONFIG_LINEDISP=m
+CONFIG_LIRC=y
+CONFIG_LLD_VERSION=160006
+CONFIG_LMK04832=m
+CONFIG_LMP91000=m
+CONFIG_LOCK_MM_AND_FIND_VMA=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_LOOPBACK_TARGET=m
+CONFIG_LPC_ICH=m
+CONFIG_LP_CONSOLE=y
+CONFIG_LPC_SCH=m
+CONFIG_LRU_CACHE=m
+CONFIG_LRU_GEN_ENABLED=y
+CONFIG_LRU_GEN=y
+CONFIG_LSI_ET1011C_PHY=m
+CONFIG_LSM="yama,loadpin,safesetid,integrity,bpf"
+CONFIG_LTC1660=m
+CONFIG_LTC2309=m
 CONFIG_LTC2471=m
 CONFIG_LTC2485=m
 CONFIG_LTC2496=m
 CONFIG_LTC2497=m
+CONFIG_LTC2632=m
+CONFIG_LTC2664=m
+CONFIG_LTC2688=m
+CONFIG_LTC2983=m
+CONFIG_LTE_GDM724X=m
+CONFIG_LTO_CLANG_THIN=y
+CONFIG_LTO_CLANG=y
+CONFIG_LTO=y
+CONFIG_LTR390=m
+CONFIG_LTR501=m
+CONFIG_LTRF216A=m
+CONFIG_LV0104CS=m
+CONFIG_LWTUNNEL_BPF=y
+CONFIG_LWTUNNEL=y
+CONFIG_LXT_PHY=m
+CONFIG_LZ4_COMPRESS=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_LZ4HC_COMPRESS=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_M62332=m
+CONFIG_M686=y
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_MAC80211=m
+CONFIG_MAC80211_MESH=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC_EMUMOUSEBTN=m
+CONFIG_MACHZ_WDT=m
+CONFIG_MACINTOSH_DRIVERS=y
+CONFIG_MAC_PARTITION=y
+CONFIG_MACSEC=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_MADERA_IRQ=m
+CONFIG_MAG3110=m
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
+CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAILBOX=y
+CONFIG_MANAGER_SBS=m
+CONFIG_MANTIS_CORE=m
+CONFIG_MAPPING_DIRTY_HELPERS=y
+CONFIG_MARVELL_10G_PHY=m
+CONFIG_MARVELL_88Q2XXX_PHY=m
+CONFIG_MARVELL_88X2222_PHY=m
+CONFIG_MARVELL_GTI_WDT=m
+CONFIG_MARVELL_PHY=m
 CONFIG_MAX1027=m
 CONFIG_MAX11100=m
 CONFIG_MAX1118=m
 CONFIG_MAX11205=m
+CONFIG_MAX11410=m
 CONFIG_MAX1241=m
 CONFIG_MAX1363=m
+CONFIG_MAX30100=m
+CONFIG_MAX30102=m
+CONFIG_MAX30208=m
+CONFIG_MAX31856=m
+CONFIG_MAX31865=m
+CONFIG_MAX34408=m
+CONFIG_MAX44000=m
+CONFIG_MAX44009=m
+CONFIG_MAX517=m
+CONFIG_MAX5432=m
+CONFIG_MAX5481=m
+CONFIG_MAX5487=m
+CONFIG_MAX5522=m
+CONFIG_MAX5821=m
+CONFIG_MAX63XX_WATCHDOG=m
+CONFIG_MAX6959=m
 CONFIG_MAX9611=m
+CONFIG_MAXIM_THERMOCOUPLE=m
+CONFIG_MAXLINEAR_GPHY=m
+CONFIG_MB1232=m
+CONFIG_MC3230=m
+CONFIG_MCB_LPC=m
+CONFIG_MCB=m
+CONFIG_MCB_PCI=m
 CONFIG_MCP320X=m
 CONFIG_MCP3422=m
+CONFIG_MCP3564=m
 CONFIG_MCP3911=m
-CONFIG_MEDIATEK_MT6360_ADC=m
-CONFIG_MEN_Z188_ADC=m
-CONFIG_MP2629_ADC=m
-CONFIG_NAU7802=m
-CONFIG_QCOM_VADC_COMMON=m
-CONFIG_QCOM_SPMI_IADC=m
-CONFIG_QCOM_SPMI_VADC=m
-CONFIG_QCOM_SPMI_ADC5=m
-CONFIG_RICHTEK_RTQ6056=m
-CONFIG_SD_ADC_MODULATOR=m
-CONFIG_TI_ADC081C=m
-CONFIG_TI_ADC0832=m
-CONFIG_TI_ADC084S021=m
-CONFIG_TI_ADC12138=m
-CONFIG_TI_ADC108S102=m
-CONFIG_TI_ADC128S052=m
-CONFIG_TI_ADC161S626=m
-CONFIG_TI_ADS1015=m
-CONFIG_TI_ADS7950=m
-CONFIG_TI_ADS8344=m
-CONFIG_TI_ADS8688=m
-CONFIG_TI_ADS124S08=m
-CONFIG_TI_AM335X_ADC=m
-CONFIG_TI_TLC4541=m
-CONFIG_TI_TSC2046=m
-CONFIG_VF610_ADC=m
-CONFIG_VIPERBOARD_ADC=m
-CONFIG_XILINX_XADC=m
-CONFIG_XILINX_AMS=m
-CONFIG_IIO_SCMI=m
-CONFIG_CROS_EC_MKBP_PROXIMITY=m
-# end of Analog to digital converters
-
-#
-# Analog Front Ends
-#
-# end of Analog Front Ends
-
-#
-# Amplifiers
-#
-CONFIG_AD8366=m
-CONFIG_ADA4250=m
-CONFIG_HMC425=m
-# end of Amplifiers
-
-#
-# Chemical Sensors
-#
-CONFIG_ATLAS_PH_SENSOR=m
-CONFIG_ATLAS_EZO_SENSOR=m
-CONFIG_BME680=m
-CONFIG_BME680_I2C=m
-CONFIG_BME680_SPI=m
-CONFIG_CCS811=m
-CONFIG_IAQCORE=m
-CONFIG_PMS7003=m
-CONFIG_SCD30_CORE=m
-CONFIG_SCD30_I2C=m
-CONFIG_SCD30_SERIAL=m
-CONFIG_SENSIRION_SGP30=m
-CONFIG_SPS30_I2C=m
-CONFIG_SPS30_SERIAL=m
-CONFIG_SPS30=m
-CONFIG_VZ89X=m
-# end of Chemical Sensors
-
-CONFIG_IIO_CROS_EC_SENSORS_CORE=m
-CONFIG_IIO_CROS_EC_SENSORS=m
-CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m
-
-#
-# Hid Sensor IIO Common
-#
-CONFIG_HID_SENSOR_IIO_COMMON=m
-CONFIG_HID_SENSOR_IIO_TRIGGER=m
-# end of Hid Sensor IIO Common
-
-CONFIG_IIO_MS_SENSORS_I2C=m
-
-#
-# SSP Sensor Common
-#
-CONFIG_IIO_SSP_SENSORS_COMMONS=m
-CONFIG_IIO_SSP_SENSORHUB=m
-# end of SSP Sensor Common
-
-CONFIG_IIO_ST_SENSORS_I2C=m
-CONFIG_IIO_ST_SENSORS_SPI=m
-CONFIG_IIO_ST_SENSORS_CORE=m
-
-#
-# Digital to analog converters
-#
-CONFIG_AD5064=m
-CONFIG_AD5360=m
-CONFIG_AD5380=m
-CONFIG_AD5421=m
-CONFIG_AD5446=m
-CONFIG_AD5449=m
-CONFIG_AD5592R_BASE=m
-CONFIG_AD5592R=m
-CONFIG_AD5593R=m
-CONFIG_AD5504=m
-CONFIG_AD5624R_SPI=m
-CONFIG_LTC2688=m
-CONFIG_AD5686=m
-CONFIG_AD5686_SPI=m
-CONFIG_AD5696_I2C=m
-CONFIG_AD5755=m
-CONFIG_AD5758=m
-CONFIG_AD5761=m
-CONFIG_AD5764=m
-CONFIG_AD5766=m
-CONFIG_AD5770R=m
-CONFIG_AD5791=m
-CONFIG_AD7303=m
-CONFIG_AD8801=m
-CONFIG_DS4424=m
-CONFIG_LTC1660=m
-CONFIG_LTC2632=m
-CONFIG_M62332=m
-CONFIG_MAX517=m
-CONFIG_MAX5821=m
+CONFIG_MCP4018=m
+CONFIG_MCP41010=m
+CONFIG_MCP4131=m
+CONFIG_MCP4531=m
 CONFIG_MCP4725=m
+CONFIG_MCP4728=m
+CONFIG_MCP4821=m
 CONFIG_MCP4922=m
-CONFIG_TI_DAC082S085=m
-CONFIG_TI_DAC5571=m
-CONFIG_TI_DAC7311=m
-CONFIG_TI_DAC7612=m
-# end of Digital to analog converters
-
-#
-# IIO dummy driver
-#
-# CONFIG_IIO_SIMPLE_DUMMY is not set
-# end of IIO dummy driver
-
-#
-# Frequency Synthesizers DDS/PLL
-#
-
-#
-# Clock Generator/Distribution
-#
-CONFIG_AD9523=m
-# end of Clock Generator/Distribution
-
-#
-# Phase-Locked Loop (PLL) frequency synthesizers
-#
-CONFIG_ADF4350=m
-CONFIG_ADF4371=m
-# end of Phase-Locked Loop (PLL) frequency synthesizers
-# end of Frequency Synthesizers DDS/PLL
-
-#
-# Digital gyroscope sensors
-#
-CONFIG_ADIS16080=m
-CONFIG_ADIS16130=m
-CONFIG_ADIS16136=m
-CONFIG_ADIS16260=m
-CONFIG_ADXRS290=m
-CONFIG_ADXRS450=m
-CONFIG_BMG160=m
-CONFIG_BMG160_I2C=m
-CONFIG_BMG160_SPI=m
-CONFIG_FXAS21002C=m
-CONFIG_FXAS21002C_I2C=m
-CONFIG_FXAS21002C_SPI=m
-CONFIG_HID_SENSOR_GYRO_3D=m
-CONFIG_MPU3050=m
-CONFIG_MPU3050_I2C=m
-CONFIG_IIO_ST_GYRO_3AXIS=m
-CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
-CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
-CONFIG_ITG3200=m
-# end of Digital gyroscope sensors
-
-#
-# Health Sensors
-#
-
-#
-# Heart Rate Monitors
-#
-CONFIG_AFE4403=m
-CONFIG_AFE4404=m
-CONFIG_MAX30100=m
-CONFIG_MAX30102=m
-# end of Heart Rate Monitors
-# end of Health Sensors
-
-#
-# Humidity sensors
-#
-CONFIG_AM2315=m
-CONFIG_DHT11=m
-CONFIG_HDC100X=m
-CONFIG_HDC2010=m
-CONFIG_HID_SENSOR_HUMIDITY=m
-CONFIG_HTS221=m
-CONFIG_HTS221_I2C=m
-CONFIG_HTS221_SPI=m
-CONFIG_HTU21=m
-CONFIG_SI7005=m
-CONFIG_SI7020=m
-# end of Humidity sensors
-
-#
-# Inertial measurement units
-#
-CONFIG_ADIS16400=m
-CONFIG_ADIS16460=m
-CONFIG_ADIS16475=m
-CONFIG_ADIS16480=m
-CONFIG_BMI160=m
-CONFIG_BMI160_I2C=m
-CONFIG_BMI160_SPI=m
-CONFIG_BOSCH_BNO055_SERIAL=m
-CONFIG_BOSCH_BNO055_I2C=m
-CONFIG_FXOS8700=m
-CONFIG_FXOS8700_I2C=m
-CONFIG_FXOS8700_SPI=m
-CONFIG_KMX61=m
-CONFIG_INV_ICM42600=m
-CONFIG_INV_ICM42600_I2C=m
-CONFIG_INV_ICM42600_SPI=m
-CONFIG_INV_MPU6050_IIO=m
-CONFIG_INV_MPU6050_I2C=m
-CONFIG_INV_MPU6050_SPI=m
-CONFIG_IIO_ST_LSM6DSX=m
-CONFIG_IIO_ST_LSM9DS0=m
-CONFIG_IIO_ST_LSM9DS0_I2C=m
-CONFIG_IIO_ST_LSM9DS0_SPI=m
-CONFIG_IIO_ST_LSM6DSX_I2C=m
-CONFIG_IIO_ST_LSM6DSX_SPI=m
-CONFIG_IIO_ST_LSM6DSX_I3C=m
-# end of Inertial measurement units
-
-CONFIG_IIO_ADIS_LIB=m
-CONFIG_IIO_ADIS_LIB_BUFFER=y
-
-#
-# Light sensors
-#
-# CONFIG_ACPI_ALS is not set
-CONFIG_ADJD_S311=m
-CONFIG_ADUX1020=m
-CONFIG_AL3010=m
-CONFIG_AL3320A=m
-CONFIG_APDS9300=m
-CONFIG_APDS9960=m
-CONFIG_AS73211=m
-CONFIG_BH1750=m
-CONFIG_BH1780=m
-CONFIG_CM32181=m
-CONFIG_CM3232=m
-CONFIG_CM3323=m
-CONFIG_CM36651=m
-CONFIG_IIO_CROS_EC_LIGHT_PROX=m
-CONFIG_GP2AP002=m
-CONFIG_GP2AP020A00F=m
-CONFIG_IQS621_ALS=m
-CONFIG_SENSORS_ISL29018=m
-CONFIG_SENSORS_ISL29028=m
-CONFIG_ISL29125=m
-CONFIG_HID_SENSOR_ALS=m
-CONFIG_HID_SENSOR_PROX=m
-CONFIG_JSA1212=m
-CONFIG_RPR0521=m
-CONFIG_SENSORS_LM3533=m
-CONFIG_LTR501=m
-CONFIG_LTRF216A=m
-CONFIG_LV0104CS=m
-CONFIG_MAX44000=m
-CONFIG_MAX44009=m
+CONFIG_MCP9600=m
+CONFIG_MCTP_FLOWS=y
+CONFIG_MCTP_SERIAL=m
+CONFIG_MCTP_TRANSPORT_I2C=m
+CONFIG_MCTP_TRANSPORT_I3C=m
+CONFIG_MCTP_TRANSPORT_USB=m
+CONFIG_MCTP=y
+CONFIG_MD_CLUSTER=m
+CONFIG_MD_FAULTY=m
+CONFIG_MDIO_BCM_UNIMAC=m
+CONFIG_MDIO_BITBANG=m
+CONFIG_MDIO_BUS=m
+CONFIG_MDIO_DEVICE=m
+CONFIG_MDIO_DEVRES=m
+CONFIG_MDIO_GPIO=m
+CONFIG_MDIO_I2C=m
+CONFIG_MDIO_MSCC_MIIM=m
+CONFIG_MDIO_MVUSB=m
+CONFIG_MDIO_REGMAP=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID456=m
+CONFIG_MEDIA_ALTERA_CI=m
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CEC_RC=y
+CONFIG_MEDIA_CEC_SUPPORT=y
+CONFIG_MEDIA_COMMON_OPTIONS=y
+CONFIG_MEDIA_CONTROLLER_DVB=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_PCI_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIATEK_GE_PHY=m
+CONFIG_MEDIATEK_MT6359_AUXADC=m
+CONFIG_MEDIATEK_MT6360_ADC=m
+CONFIG_MEDIATEK_MT6370_ADC=m
+CONFIG_MEDIA_TUNER_AV201X=m
+CONFIG_MEDIA_TUNER_E4000=m
+CONFIG_MEDIA_TUNER_FC0011=m
+CONFIG_MEDIA_TUNER_FC0012=m
+CONFIG_MEDIA_TUNER_FC0013=m
+CONFIG_MEDIA_TUNER_FC2580=m
+CONFIG_MEDIA_TUNER_IT913X=m
+CONFIG_MEDIA_TUNER=m
+CONFIG_MEDIA_TUNER_M88RS6000T=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MSI001=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2063=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2131=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_MXL301RF=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_QM1D1B0004=m
+CONFIG_MEDIA_TUNER_QM1D1C0042=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_R820T=m
+CONFIG_MEDIA_TUNER_SI2157=m
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_STV6120=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TDA18250=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_MEEGOPAD_ANX7428=m
+CONFIG_MEGARAID_LEGACY=m
+CONFIG_MEGARAID_MAILBOX=m
+CONFIG_MEGARAID_MM=m
+CONFIG_MEGARAID_NEWGEN=y
+CONFIG_MEGARAID_SAS=m
+CONFIG_MELLANOX_PLATFORM=y
+CONFIG_MEMCG_KMEM=y
+CONFIG_MEMORY_FAILURE=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MEMORY=y
+CONFIG_MEMREGION=y
+CONFIG_MEMSTICK_JMICRON_38X=m
+CONFIG_MEMSTICK=m
+CONFIG_MEMSTICK_R592=m
+CONFIG_MEMSTICK_REALTEK_PCI=m
+CONFIG_MEMSTICK_REALTEK_USB=m
+CONFIG_MEMSTICK_TIFM_MS=m
+CONFIG_MEN_A21_WDT=m
+CONFIG_MENF21BMC_WATCHDOG=m
+CONFIG_MENZ069_WATCHDOG=m
+CONFIG_MEN_Z188_ADC=m
+CONFIG_MERAKI_MX100=m
+CONFIG_MFD_88PM800=m
+CONFIG_MFD_88PM805=m
+CONFIG_MFD_ARIZONA_I2C=m
+CONFIG_MFD_ARIZONA=m
+CONFIG_MFD_ARIZONA_SPI=m
+CONFIG_MFD_ATC260X_I2C=m
+CONFIG_MFD_ATC260X=m
+CONFIG_MFD_AXP20X_I2C=m
+CONFIG_MFD_AXP20X=m
+CONFIG_MFD_BCM590XX=m
+CONFIG_MFD_BD9571MWV=m
+CONFIG_MFD_CORE=y
+CONFIG_MFD_CROS_EC_DEV=m
+CONFIG_MFD_CS42L43_I2C=m
+CONFIG_MFD_CS42L43_SDW=m
+CONFIG_MFD_CS47L15=y
+CONFIG_MFD_CS47L24=y
+CONFIG_MFD_CS47L35=y
+CONFIG_MFD_CS47L85=y
+CONFIG_MFD_CS47L90=y
+CONFIG_MFD_CS47L92=y
+CONFIG_MFD_DA9052_SPI=y
+CONFIG_MFD_DA9062=m
+CONFIG_MFD_DA9063=m
+CONFIG_MFD_DA9150=m
+CONFIG_MFD_DLN2=m
+CONFIG_MFD_INTEL_LPSS_ACPI=m
+CONFIG_MFD_INTEL_LPSS=m
+CONFIG_MFD_INTEL_LPSS_PCI=m
+CONFIG_MFD_INTEL_M10_BMC_CORE=m
+CONFIG_MFD_INTEL_M10_BMC_PMCI=m
+CONFIG_MFD_INTEL_M10_BMC_SPI=m
+CONFIG_MFD_INTEL_PMC_BXT=m
+CONFIG_MFD_INTEL_QUARK_I2C_GPIO=m
+CONFIG_MFD_IQS62X=m
+CONFIG_MFD_JANZ_CMODIO=m
+CONFIG_MFD_KEMPLD=m
+CONFIG_MFD_LM3533=m
+CONFIG_MFD_LP3943=m
+CONFIG_MFD_MADERA_I2C=m
+CONFIG_MFD_MADERA=m
+CONFIG_MFD_MADERA_SPI=m
+CONFIG_MFD_MAX14577=m
+CONFIG_MFD_MAX7360=m
+CONFIG_MFD_MAX77693=m
+CONFIG_MFD_MAX8907=m
+CONFIG_MFD_MC13XXX_I2C=m
+CONFIG_MFD_MC13XXX=m
+CONFIG_MFD_MC13XXX_SPI=m
+CONFIG_MFD_MENF21BMC=m
+CONFIG_MFD_MP2629=m
+CONFIG_MFD_MT6360=m
+CONFIG_MFD_MT6370=m
+CONFIG_MFD_MT6397=m
+CONFIG_MFD_OCELOT=m
+CONFIG_MFD_PCF50633=m
+CONFIG_MFD_QNAP_MCU=m
+CONFIG_MFD_RDC321X=m
+CONFIG_MFD_RETU=m
+CONFIG_MFD_RT4831=m
+CONFIG_MFD_RT5033=m
+CONFIG_MFD_RT5120=m
+CONFIG_MFD_SI476X_CORE=m
+CONFIG_MFD_SIMPLE_MFD_I2C=m
+CONFIG_MFD_SKY81452=m
+CONFIG_MFD_SM501_GPIO=y
+CONFIG_MFD_SM501=m
+CONFIG_MFD_SMPRO=m
+CONFIG_MFD_SY7636A=m
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_TI_AM335X_TSCADC=m
+CONFIG_MFD_TI_LMU=m
+CONFIG_MFD_TI_LP873X=m
+CONFIG_MFD_TPS65086=m
+CONFIG_MFD_TPS65912_I2C=m
+CONFIG_MFD_TPS65912_SPI=y
+CONFIG_MFD_TPS65912=y
+CONFIG_MFD_TPS6594_I2C=m
+CONFIG_MFD_TPS6594=m
+CONFIG_MFD_TPS6594_SPI=m
+CONFIG_MFD_TQMX86=m
+CONFIG_MFD_UPBOARD_FPGA=m
+CONFIG_MFD_VIPERBOARD=m
+CONFIG_MFD_VX855=m
+CONFIG_MFD_WCD934X=m
+CONFIG_MFD_WL1273_CORE=m
+CONFIG_MFD_WM5102=y
+CONFIG_MFD_WM5110=y
+CONFIG_MFD_WM831X_SPI=y
+CONFIG_MFD_WM831X=y
+CONFIG_MFD_WM8994=m
+CONFIG_MFD_WM8997=y
+CONFIG_MFD_WM8998=y
+CONFIG_MHI_BUS_DEBUG=y
+CONFIG_MHI_BUS_EP=m
+CONFIG_MHI_BUS=m
+CONFIG_MHI_BUS_PCI_GENERIC=m
+CONFIG_MHI_NET=m
+CONFIG_MHI_WWAN_CTRL=m
+CONFIG_MHI_WWAN_MBIM=m
+CONFIG_MICREL_KS8995MA=m
+CONFIG_MICREL_PHY=m
+CONFIG_MICROCHIP_PHY=m
+CONFIG_MICROCHIP_T1_PHY=m
+CONFIG_MICROCHIP_T1S_PHY=m
+CONFIG_MICROCODE_AMD=y
+CONFIG_MICROCODE_INTEL=y
+CONFIG_MICROCODE=y
+CONFIG_MICROSEMI_PHY=m
+CONFIG_MII=m
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_MIPI_I3C_HCI=m
+CONFIG_MIPI_I3C_HCI_PCI=m
+CONFIG_MISC_ALCOR_PCI=m
+CONFIG_MISC_RTSX=m
+CONFIG_MISC_RTSX_PCI=m
+CONFIG_MISC_RTSX_USB=m
+CONFIG_MISDN_AVMFRITZ=m
+CONFIG_MISDN_DSP=m
+CONFIG_MISDN_HDLC=m
+CONFIG_MISDN_HFCMULTI=m
+CONFIG_MISDN_HFCPCI=m
+CONFIG_MISDN_HFCUSB=m
+CONFIG_MISDN_INFINEON=m
+CONFIG_MISDN_IPAC=m
+CONFIG_MISDN_ISAR=m
+CONFIG_MISDN_L1OIP=m
+CONFIG_MISDN=m
+CONFIG_MISDN_NETJET=m
+CONFIG_MISDN_SPEEDFAX=m
+CONFIG_MISDN_W6692=m
+CONFIG_MITIGATION_ITS=y
+CONFIG_MITIGATION_L1TF=y
+CONFIG_MITIGATION_MDS=y
+CONFIG_MITIGATION_MMIO_STALE_DATA=y
+CONFIG_MITIGATION_PAGE_TABLE_ISOLATION=y
+CONFIG_MITIGATION_RETBLEED=y
+CONFIG_MITIGATION_RETHUNK=y
+CONFIG_MITIGATION_RETPOLINE=y
+CONFIG_MITIGATION_RFDS=y
+CONFIG_MITIGATION_SPECTRE_BHI=y
+CONFIG_MITIGATION_SPECTRE_V1=y
+CONFIG_MITIGATION_SPECTRE_V2=y
+CONFIG_MITIGATION_SRBDS=y
+CONFIG_MITIGATION_SSB=y
+CONFIG_MITIGATION_TAA=y
+CONFIG_MITIGATION_TSA=y
+CONFIG_MITIGATION_VMSCAPE=y
+CONFIG_MLX4_INFINIBAND=m
+CONFIG_MLX5_INFINIBAND=m
+CONFIG_MLX5_VDPA_NET=m
+CONFIG_MLX5_VDPA=y
+CONFIG_MLX5_VFIO_PCI=m
+CONFIG_MLX90614=m
+CONFIG_MLX90632=m
+CONFIG_MLX90635=m
+CONFIG_MLX_PLATFORM=m
+CONFIG_MLXREG_DPU=m
+CONFIG_MLXREG_HOTPLUG=m
+CONFIG_MLXREG_IO=m
+CONFIG_MLXREG_LC=m
+CONFIG_MLX_WDT=m
+CONFIG_MMA7455_I2C=m
+CONFIG_MMA7455=m
+CONFIG_MMA7455_SPI=m
+CONFIG_MMA7660=m
+CONFIG_MMA8452=m
+CONFIG_MMA9551_CORE=m
+CONFIG_MMA9551=m
+CONFIG_MMA9553=m
+CONFIG_MMC35240=m
+CONFIG_MMC_ALCOR=m
+CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_CB710=m
+CONFIG_MMC_CQHCI=m
+CONFIG_MMC_HSQ=m
+CONFIG_MMC=m
+CONFIG_MMC_MTK=m
+CONFIG_MMC_REALTEK_PCI=m
+CONFIG_MMC_REALTEK_USB=m
+CONFIG_MMC_RICOH_MMC=y
+CONFIG_MMC_SDHCI_ACPI=m
+CONFIG_MMC_SDHCI_F_SDH30=m
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI=m
+CONFIG_MMC_SDHCI_PCI=m
+CONFIG_MMC_SDHCI_PLTFM=m
+CONFIG_MMC_SDHCI_XENON=m
+CONFIG_MMC_SDRICOH_CS=m
+CONFIG_MMC_SPI=m
+CONFIG_MMC_TIFM_SD=m
+CONFIG_MMC_USDHI6ROL0=m
+CONFIG_MMC_USHC=m
+CONFIG_MMC_VIA_SDMMC=m
+CONFIG_MMC_VUB300=m
+CONFIG_MMC_WBSD=m
+CONFIG_MMU_GATHER_MERGE_VMAS=y
+CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
+CONFIG_MMU_GATHER_TABLE_FREE=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODIFY_LDT_SYSCALL=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MOST_CDEV=m
+CONFIG_MOST_COMPONENTS=m
+CONFIG_MOST_I2C=m
+CONFIG_MOST=m
+CONFIG_MOST_NET=m
+CONFIG_MOST_SND=m
+CONFIG_MOST_USB_HDM=m
+CONFIG_MOST_VIDEO=m
+CONFIG_MOTORCOMM_PHY=m
+CONFIG_MOUSE_APPLETOUCH=m
+CONFIG_MOUSE_BCM5974=m
+CONFIG_MOUSE_CYAPA=m
+CONFIG_MOUSE_ELAN_I2C_I2C=y
+CONFIG_MOUSE_ELAN_I2C=m
+CONFIG_MOUSE_ELAN_I2C_SMBUS=y
+CONFIG_MOUSE_GPIO=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_PIXART=y
+CONFIG_MOUSE_PS2_SENTELIC=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TOUCHKIT=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+CONFIG_MOUSE_PS2_VMMOUSE=y
+CONFIG_MOUSE_SERIAL=m
+CONFIG_MOUSE_SYNAPTICS_I2C=m
+CONFIG_MOUSE_SYNAPTICS_USB=m
+CONFIG_MOUSE_VSXXXAA=m
+CONFIG_MOXA_INTELLIO=m
+CONFIG_MOXA_SMARTIO=m
+CONFIG_MP2629_ADC=m
+CONFIG_MPL115_I2C=m
+CONFIG_MPL115=m
+CONFIG_MPL115_SPI=m
+CONFIG_MPL3115=m
+CONFIG_MPRLS0025PA=m
+CONFIG_MPU3050_I2C=m
+CONFIG_MPU3050=m
+CONFIG_MQ_IOSCHED_KYBER=m
+CONFIG_MS5611_I2C=m
+CONFIG_MS5611=m
+CONFIG_MS5611_SPI=m
+CONFIG_MS5637=m
+CONFIG_MSA311=m
+CONFIG_MS_BLOCK=m
+CONFIG_MSHV_ROOT=m
+CONFIG_MSI_EC=m
+CONFIG_MSI_LAPTOP=m
+CONFIG_MSI_WMI=m
+CONFIG_MSI_WMI_PLATFORM=m
+CONFIG_MSPRO_BLOCK=m
+CONFIG_MT7601U=m
+CONFIG_MT7603E=m
+CONFIG_MT7615_COMMON=m
+CONFIG_MT7615E=m
+CONFIG_MT7663S=m
+CONFIG_MT7663U=m
+CONFIG_MT7663_USB_SDIO_COMMON=m
+CONFIG_MT76_CONNAC_LIB=m
+CONFIG_MT76_CORE=m
+CONFIG_MT76_LEDS=y
+CONFIG_MT76_SDIO=m
+CONFIG_MT76_USB=m
+CONFIG_MT76x02_LIB=m
+CONFIG_MT76x02_USB=m
+CONFIG_MT76x0_COMMON=m
+CONFIG_MT76x0E=m
+CONFIG_MT76x0U=m
+CONFIG_MT76x2_COMMON=m
+CONFIG_MT76x2E=m
+CONFIG_MT76x2U=m
+CONFIG_MT7915E=m
+CONFIG_MT7921_COMMON=m
+CONFIG_MT7921E=m
+CONFIG_MT7921S=m
+CONFIG_MT7921U=m
+CONFIG_MT7925E=m
+CONFIG_MT7925U=m
+CONFIG_MT798X_WMAC=y
+CONFIG_MT7996E=m
+CONFIG_MTD_ABSENT=m
+CONFIG_MTD_AMD76XROM=m
+CONFIG_MTD_AR7_PARTS=m
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK2MTD=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_BLOCK_RO=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI=m
+CONFIG_MTD_CFI_STAA=m
+CONFIG_MTD_CFI_UTIL=m
+CONFIG_MTD_CK804XROM=m
+CONFIG_MTD_CMDLINE_PARTS=m
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_DATAFLASH=m
+CONFIG_MTD_DATAFLASH_OTP=y
+CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
+CONFIG_MTD_DOCG3=m
+CONFIG_MTD_ESB2ROM=m
+CONFIG_MTD_GEN_PROBE=m
+CONFIG_MTD_HYPERBUS=m
+CONFIG_MTD_ICHXROM=m
+CONFIG_MTD_INTEL_DG=m
+CONFIG_MTD_INTEL_VR_NOR=m
+CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_L440GX=m
+CONFIG_MTD_LPDDR=m
+CONFIG_MTD=m
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_MCHP23K256=m
+CONFIG_MTD_MCHP48L640=m
+CONFIG_MTD_MTDRAM=m
+CONFIG_MTD_NAND_ARASAN=m
+CONFIG_MTD_NAND_CAFE=m
+CONFIG_MTD_NAND_CORE=m
+CONFIG_MTD_NAND_DENALI=m
+CONFIG_MTD_NAND_DENALI_PCI=m
+CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
+CONFIG_MTD_NAND_DISKONCHIP=m
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
+CONFIG_MTD_NAND_ECC_MXIC=y
+CONFIG_MTD_NAND_ECC_SW_BCH=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_GPIO=m
+CONFIG_MTD_NAND_MXIC=m
+CONFIG_MTD_NAND_NANDSIM=m
+CONFIG_MTD_NAND_PLATFORM=m
+CONFIG_MTD_NAND_RICOH=m
+CONFIG_MTD_NETtel=m
+CONFIG_MTD_ONENAND_2X_PROGRAM=y
+CONFIG_MTD_ONENAND_GENERIC=m
+CONFIG_MTD_ONENAND=m
+CONFIG_MTD_ONENAND_OTP=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+CONFIG_MTD_OOPS=m
+CONFIG_MTD_PCI=m
+CONFIG_MTD_PCMCIA=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PLATRAM=m
+CONFIG_MTD_PMC551_BUGFIX=y
+CONFIG_MTD_PMC551=m
+CONFIG_MTD_PSTORE=m
+CONFIG_MTD_QINFO_PROBE=m
+CONFIG_MTDRAM_ERASE_SIZE=128
+CONFIG_MTD_RAM=m
+CONFIG_MTDRAM_TOTAL_SIZE=4096
+CONFIG_MTD_RAW_NAND=m
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+CONFIG_MTD_REDBOOT_PARTS=m
+CONFIG_MTD_REDBOOT_PARTS_READONLY=y
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+CONFIG_MTD_ROM=m
+CONFIG_MTD_SBC_GXX=m
+CONFIG_MTD_SCB2_FLASH=m
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_SM_COMMON=m
+CONFIG_MTD_SPI_NAND=m
+CONFIG_MTD_SPI_NOR=m
+CONFIG_MTD_SPI_NOR_SWP_DISABLE=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SST25L=m
+CONFIG_MTD_SWAP=m
+CONFIG_MTD_TESTS=m
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI=m
+CONFIG_MTD_UBI_NVMEM=m
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTK_T7XX=m
+CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0
+CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
+CONFIG_MTRR_SANITIZER=y
+CONFIG_MTRR=y
+CONFIG_MULTIPLEXER=m
+CONFIG_MUSB_PIO_ONLY=y
+CONFIG_MUX_ADG792A=m
+CONFIG_MUX_ADGS1408=m
+CONFIG_MUX_GPIO=m
+CONFIG_MWAVE=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_PCIE=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
+CONFIG_MWL8K=m
+CONFIG_MXC4005=m
+CONFIG_MXC6255=m
+CONFIG_MXM_WMI=m
+CONFIG_NATIONAL_PHY=m
+CONFIG_NAU7802=m
+CONFIG_NCN26000_PHY=m
+CONFIG_ND_BTT=m
+CONFIG_ND_CLAIM=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_NEED_SG_DMA_FLAGS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_9P_FD=m
+CONFIG_NET_9P=m
+CONFIG_NET_9P_RDMA=m
+CONFIG_NET_9P_USBG=y
+CONFIG_NET_9P_VIRTIO=m
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETCONSOLE_EXTENDED_LOG=y
+CONFIG_NETCONSOLE=m
+CONFIG_NETDEV_LEGACY_INIT=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NETDEVSIM=m
+CONFIG_NET_FAILOVER=m
+CONFIG_NET_FC=y
+CONFIG_NET_IFE=m
+CONFIG_NETKIT=y
+CONFIG_NET_POLL_CONTROLLER=y
+CONFIG_NETPOLL=y
+CONFIG_NET_SELFTESTS=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_NET_TEAM_MODE_RANDOM=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NEW_LEDS=y
+CONFIG_NFC_DIGITAL=m
+CONFIG_NFC_FDP_I2C=m
+CONFIG_NFC_FDP=m
+CONFIG_NFC_HCI=m
+CONFIG_NFC=m
+CONFIG_NFC_MEI_PHY=m
+CONFIG_NFC_MICROREAD_I2C=m
+CONFIG_NFC_MICROREAD=m
+CONFIG_NFC_MICROREAD_MEI=m
+CONFIG_NFC_MRVL_I2C=m
+CONFIG_NFC_MRVL=m
+CONFIG_NFC_MRVL_SPI=m
+CONFIG_NFC_MRVL_UART=m
+CONFIG_NFC_MRVL_USB=m
+CONFIG_NFC_NCI=m
+CONFIG_NFC_NCI_SPI=m
+CONFIG_NFC_NCI_UART=m
+CONFIG_NFC_NXP_NCI_I2C=m
+CONFIG_NFC_NXP_NCI=m
+CONFIG_NFC_PN532_UART=m
+CONFIG_NFC_PN533_I2C=m
+CONFIG_NFC_PN533=m
+CONFIG_NFC_PN533_USB=m
+CONFIG_NFC_PN544_I2C=m
+CONFIG_NFC_PN544=m
+CONFIG_NFC_PN544_MEI=m
+CONFIG_NFC_PORT100=m
+CONFIG_NFC_S3FWRN5_I2C=m
+CONFIG_NFC_S3FWRN5=m
+CONFIG_NFC_S3FWRN82_UART=m
+CONFIG_NFC_SHDLC=y
+CONFIG_NFC_SIM=m
+CONFIG_NFC_ST21NFCA_I2C=m
+CONFIG_NFC_ST21NFCA=m
+CONFIG_NFC_ST95HF=m
+CONFIG_NFC_ST_NCI_I2C=m
+CONFIG_NFC_ST_NCI=m
+CONFIG_NFC_ST_NCI_SPI=m
+CONFIG_NFC_TRF7970A=m
+CONFIG_NFC_VIRTUAL_NCI=m
+CONFIG_NFTL=m
+CONFIG_NFTL_RW=y
+CONFIG_N_GSM=m
+CONFIG_N_HDLC=m
+CONFIG_NI903X_WDT=m
+CONFIG_NIC7018_WDT=m
+CONFIG_NITRO_ENCLAVES=m
+CONFIG_NL80211_TESTMODE=y
+CONFIG_NLMON=m
 CONFIG_NOA1305=m
+CONFIG_NODES_SHIFT=10
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NO_HZ=y
+CONFIG_NOP_USB_XCEIV=m
+CONFIG_NORTEL_HERMES=m
+CONFIG_NOUVEAU_DEBUG=3
+CONFIG_NOUVEAU_DEBUG_DEFAULT=1
+CONFIG_NOZOMI=m
+CONFIG_NR_CPUS=32
+CONFIG_NR_CPUS_DEFAULT=32
+CONFIG_NR_CPUS_RANGE_BEGIN=2
+CONFIG_NR_CPUS_RANGE_END=64
+CONFIG_NSM=m
+CONFIG_NTB_EPF=m
+CONFIG_NTB_IDT=m
+CONFIG_NTB=m
+CONFIG_NTB_MSI_TEST=m
+CONFIG_NTB_MSI=y
+CONFIG_NTB_NETDEV=m
+CONFIG_NTB_PERF=m
+CONFIG_NTB_PINGPONG=m
+CONFIG_NTB_SWITCHTEC=m
+CONFIG_NTB_TOOL=m
+CONFIG_NTB_TRANSPORT=m
+CONFIG_NULL_TTY=m
+CONFIG_NUMA_KEEP_MEMINFO=y
+CONFIG_NUMA=y
+CONFIG_NVDIMM_KEYS=y
+CONFIG_NVGRACE_GPU_VFIO_PCI=m
+CONFIG_NVIDIA_WMI_EC_BACKLIGHT=m
+CONFIG_NVMEM_LAYOUT_ONIE_TLV=m
+CONFIG_NVMEM_LAYOUT_SL28_VPD=m
+CONFIG_NVMEM_RAVE_SP_EEPROM=m
+CONFIG_NVMEM_RMEM=m
+CONFIG_NVMEM_SPMI_SDAM=m
+CONFIG_NVRAM=m
+CONFIG_NVSW_SN2201=m
+CONFIG_NV_TCO=m
+CONFIG_NXP_C45_TJA11XX_PHY=m
+CONFIG_NXP_CBTX_PHY=m
+CONFIG_NXP_TJA11XX_PHY=m
+CONFIG_OBJAGG=m
+CONFIG_OCTEONEP_VDPA=m
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
 CONFIG_OPT3001=m
+CONFIG_OPT4001=m
+CONFIG_OPT4060=m
+CONFIG_OPTPROBES=y
+CONFIG_ORINOCO_USB=m
+CONFIG_OSF_PARTITION=y
+CONFIG_OUTPUT_FORMAT="elf32-i386"
+CONFIG_OVPN=m
+CONFIG_OXP_EC=m
+CONFIG_P2SB=y
+CONFIG_P54_COMMON=m
+CONFIG_P54_LEDS=y
+CONFIG_P54_PCI=m
+CONFIG_P54_SPI_DEFAULT_EEPROM=y
+CONFIG_P54_SPI=m
+CONFIG_P54_USB=m
 CONFIG_PA12203001=m
-CONFIG_SI1133=m
-CONFIG_SI1145=m
-CONFIG_STK3310=m
-CONFIG_ST_UVIS25=m
-CONFIG_ST_UVIS25_I2C=m
-CONFIG_ST_UVIS25_SPI=m
-CONFIG_TCS3414=m
-CONFIG_TCS3472=m
-CONFIG_SENSORS_TSL2563=m
-CONFIG_TSL2583=m
-CONFIG_TSL2591=m
-CONFIG_TSL2772=m
-CONFIG_TSL4531=m
-CONFIG_US5182D=m
-CONFIG_VCNL4000=m
-CONFIG_VCNL4035=m
-CONFIG_VEML6030=m
-CONFIG_VEML6070=m
-CONFIG_VL6180=m
-CONFIG_ZOPT2201=m
-# end of Light sensors
-
-#
-# Magnetometer sensors
-#
-CONFIG_AK8975=m
-CONFIG_AK09911=m
-CONFIG_BMC150_MAGN=m
-CONFIG_BMC150_MAGN_I2C=m
-CONFIG_BMC150_MAGN_SPI=m
-CONFIG_MAG3110=m
-CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
-CONFIG_MMC35240=m
-CONFIG_IIO_ST_MAGN_3AXIS=m
-CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
-CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
-CONFIG_SENSORS_HMC5843=m
-CONFIG_SENSORS_HMC5843_I2C=m
-CONFIG_SENSORS_HMC5843_SPI=m
-CONFIG_SENSORS_RM3100=m
-CONFIG_SENSORS_RM3100_I2C=m
-CONFIG_SENSORS_RM3100_SPI=m
-CONFIG_YAMAHA_YAS530=m
-# end of Magnetometer sensors
-
-#
-# Multiplexers
-#
-# end of Multiplexers
-
-#
-# Inclinometer sensors
-#
-CONFIG_HID_SENSOR_INCLINOMETER_3D=m
-CONFIG_HID_SENSOR_DEVICE_ROTATION=m
-# end of Inclinometer sensors
-
-#
-# Triggers - standalone
-#
-CONFIG_IIO_HRTIMER_TRIGGER=m
-CONFIG_IIO_INTERRUPT_TRIGGER=m
-CONFIG_IIO_TIGHTLOOP_TRIGGER=m
-CONFIG_IIO_SYSFS_TRIGGER=m
-# end of Triggers - standalone
-
-#
-# Linear and angular position sensors
-#
-CONFIG_IQS624_POS=m
-CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
-# end of Linear and angular position sensors
-
-#
-# Digital potentiometers
-#
-CONFIG_AD5272=m
-CONFIG_DS1803=m
-CONFIG_MAX5432=m
-CONFIG_MAX5481=m
-CONFIG_MAX5487=m
-CONFIG_MCP4018=m
-CONFIG_MCP4131=m
-CONFIG_MCP4531=m
-CONFIG_MCP41010=m
-CONFIG_TPL0102=m
-# end of Digital potentiometers
-
-#
-# Digital potentiostats
-#
-CONFIG_LMP91000=m
-# end of Digital potentiostats
-
-#
-# Pressure sensors
-#
-CONFIG_ABP060MG=m
-CONFIG_BMP280=m
-CONFIG_BMP280_I2C=m
-CONFIG_BMP280_SPI=m
-CONFIG_IIO_CROS_EC_BARO=m
-CONFIG_DLHL60D=m
-CONFIG_DPS310=m
-CONFIG_HID_SENSOR_PRESS=m
-CONFIG_HP03=m
-CONFIG_ICP10100=m
-CONFIG_MPL115=m
-CONFIG_MPL115_I2C=m
-CONFIG_MPL115_SPI=m
-CONFIG_MPL3115=m
-CONFIG_MS5611=m
-CONFIG_MS5611_I2C=m
-CONFIG_MS5611_SPI=m
-CONFIG_MS5637=m
-CONFIG_IIO_ST_PRESS=m
-CONFIG_IIO_ST_PRESS_I2C=m
-CONFIG_IIO_ST_PRESS_SPI=m
-CONFIG_T5403=m
-CONFIG_HP206C=m
-CONFIG_ZPA2326=m
-CONFIG_ZPA2326_I2C=m
-CONFIG_ZPA2326_SPI=m
-# end of Pressure sensors
-
-#
-# Lightning sensors
-#
-CONFIG_AS3935=m
-# end of Lightning sensors
-
-#
-# Proximity and distance sensors
-#
-CONFIG_ISL29501=m
-CONFIG_LIDAR_LITE_V2=m
-CONFIG_MB1232=m
+CONFIG_PAC1921=m
+CONFIG_PAC1934=m
+CONFIG_PACKING=y
+CONFIG_PADATA=y
+CONFIG_PAGE_BLOCK_MAX_ORDER=10
+CONFIG_PAGE_BLOCK_ORDER=10
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_TABLE_ISOLATION=y
+CONFIG_PAHOLE_VERSION=125
+CONFIG_PANASONIC_LAPTOP=m
+CONFIG_PANEL=m
+CONFIG_PANEL_PARPORT=0
+CONFIG_PANEL_PROFILE=5
+CONFIG_PANIC_TIMEOUT=60
+CONFIG_PARAVIRT_CLOCK=y
+CONFIG_PARAVIRT=y
+CONFIG_PARMAN=m
+CONFIG_PARPORT_1284=y
+CONFIG_PARPORT=m
+CONFIG_PARPORT_NOT_PC=y
+CONFIG_PARPORT_PANEL=m
+CONFIG_PARPORT_PC_FIFO=y
+CONFIG_PARPORT_PC=m
+CONFIG_PARPORT_PC_PCMCIA=m
+CONFIG_PARPORT_PC_SUPERIO=y
+CONFIG_PARPORT_SERIAL=m
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PATA_ACPI=m
+CONFIG_PATA_ALI=m
+CONFIG_PATA_AMD=m
+CONFIG_PATA_ARTOP=m
+CONFIG_PATA_ATIIXP=m
+CONFIG_PATA_ATP867X=m
+CONFIG_PATA_CMD640_PCI=m
+CONFIG_PATA_CMD64X=m
+CONFIG_PATA_CS5520=m
+CONFIG_PATA_CS5530=m
+CONFIG_PATA_CS5535=m
+CONFIG_PATA_CS5536=m
+CONFIG_PATA_CYPRESS=m
+CONFIG_PATA_EFAR=m
+CONFIG_PATA_HPT366=m
+CONFIG_PATA_HPT37X=m
+CONFIG_PATA_HPT3X2N=m
+CONFIG_PATA_HPT3X3_DMA=y
+CONFIG_PATA_HPT3X3=m
+CONFIG_PATA_IT8213=m
+CONFIG_PATA_IT821X=m
+CONFIG_PATA_JMICRON=m
+CONFIG_PATA_LEGACY=m
+CONFIG_PATA_MARVELL=m
+CONFIG_PATA_MPIIX=m
+CONFIG_PATA_NETCELL=m
+CONFIG_PATA_NINJA32=m
+CONFIG_PATA_NS87410=m
+CONFIG_PATA_NS87415=m
+CONFIG_PATA_OLDPIIX=m
+CONFIG_PATA_OPTIDMA=m
+CONFIG_PATA_OPTI=m
+CONFIG_PATA_PARPORT_ATEN=m
+CONFIG_PATA_PARPORT_BPCK6=m
+CONFIG_PATA_PARPORT_BPCK=m
+CONFIG_PATA_PARPORT_COMM=m
+CONFIG_PATA_PARPORT_DSTR=m
+CONFIG_PATA_PARPORT_EPATC8=y
+CONFIG_PATA_PARPORT_EPAT=m
+CONFIG_PATA_PARPORT_EPIA=m
+CONFIG_PATA_PARPORT_FIT2=m
+CONFIG_PATA_PARPORT_FIT3=m
+CONFIG_PATA_PARPORT_FRIQ=m
+CONFIG_PATA_PARPORT_FRPW=m
+CONFIG_PATA_PARPORT_KBIC=m
+CONFIG_PATA_PARPORT_KTTI=m
+CONFIG_PATA_PARPORT=m
+CONFIG_PATA_PARPORT_ON20=m
+CONFIG_PATA_PARPORT_ON26=m
+CONFIG_PATA_PCMCIA=m
+CONFIG_PATA_PDC2027X=m
+CONFIG_PATA_PDC_OLD=m
+CONFIG_PATA_QDI=m
+CONFIG_PATA_RADISYS=m
+CONFIG_PATA_RDC=m
+CONFIG_PATA_RZ1000=m
+CONFIG_PATA_SC1200=m
+CONFIG_PATA_SCH=m
+CONFIG_PATA_SERVERWORKS=m
+CONFIG_PATA_SIL680=m
+CONFIG_PATA_SIS=m
+CONFIG_PATA_TIMINGS=y
+CONFIG_PATA_TOSHIBA=m
+CONFIG_PATA_TRIFLEX=m
+CONFIG_PATA_VIA=m
+CONFIG_PATA_WINBOND=m
+CONFIG_PATA_WINBOND_VLB=m
+CONFIG_PC300TOO=m
+CONFIG_PC87413_WDT=m
+CONFIG_PCCARD=m
+CONFIG_PCCARD_NONSTATIC=y
+CONFIG_PCC=y
+CONFIG_PCENGINES_APU2=m
+CONFIG_PCF50633_ADC=m
+CONFIG_PCF50633_GPIO=m
+CONFIG_PCH_PHUB=m
+CONFIG_PCI200SYN=m
+CONFIG_PCI_ATMEL=m
+CONFIG_PCI_ATS=y
+CONFIG_PCI_BIOS=y
+CONFIG_PCI_DIRECT=y
+CONFIG_PCI_DOE=y
+CONFIG_PCI_DYNAMIC_OF_NODES=y
+CONFIG_PCIEAER_CXL=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM_DEFAULT=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIE_BUS_DEFAULT=y
+CONFIG_PCIE_DPC=y
+CONFIG_PCIE_ECRC=y
+CONFIG_PCIE_EDR=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_ENDPOINT_MSI_DOORBELL=y
+CONFIG_PCI_ENDPOINT_TEST=m
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_EPF_MHI=m
+CONFIG_PCI_EPF_NTB=m
+CONFIG_PCI_EPF_VNTB=m
+CONFIG_PCIE_PME=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_PTM=y
+CONFIG_PCI_GOANY=y
+CONFIG_PCI_HERMES=m
+CONFIG_PCI_IOV=y
+CONFIG_PCI_LABEL=y
+CONFIG_PCI_LOCKLESS_CONFIG=y
+CONFIG_PCI_MMCONFIG=y
+CONFIG_PCI_PASID=y
+CONFIG_PCIPCWATCHDOG=m
+CONFIG_PCI_PF_STUB=m
+CONFIG_PCI_PRI=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCI_STUB=m
+CONFIG_PCI_SW_SWITCHTEC=m
+CONFIG_PCMCIA_AHA152X=m
+CONFIG_PCMCIA_ATMEL=m
+CONFIG_PCMCIA_FDOMAIN=m
+CONFIG_PCMCIA_HERMES=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_NINJA_SCSI=m
+CONFIG_PCMCIA_PROBE=y
+CONFIG_PCMCIA_QLOGIC=m
+CONFIG_PCMCIA_RAYCS=m
+CONFIG_PCMCIA_SPECTRUM=m
+CONFIG_PCMCIA_SYM53C500=m
+CONFIG_PCMCIA_WL3501=m
+CONFIG_PCS_LYNX=m
+CONFIG_PCS_MTK_LYNXI=m
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_PCS_XPCS=m
+CONFIG_PD6729=m
+CONFIG_PDC_ADMA=m
+CONFIG_PDS_VFIO_PCI=m
+CONFIG_PECI_CPU=m
+CONFIG_PECI=m
+CONFIG_PECI_NPCM=m
+CONFIG_PERF_EVENTS_AMD_BRS=y
+CONFIG_PERF_EVENTS_AMD_POWER=m
+CONFIG_PERF_EVENTS_AMD_UNCORE=m
+CONFIG_PERF_EVENTS_INTEL_CSTATE=m
+CONFIG_PERF_EVENTS_INTEL_RAPL=m
+CONFIG_PERF_EVENTS_INTEL_UNCORE=m
+CONFIG_PERSISTENT_KEYRINGS=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHANTOM=m
+CONFIG_PHY_CAN_TRANSCEIVER=m
+CONFIG_PHY_CPCAP_USB=m
+CONFIG_PHY_INTEL_LGM_EMMC=m
+CONFIG_PHY_PXA_28NM_HSIC=m
+CONFIG_PHY_PXA_28NM_USB2=m
+CONFIG_PHY_QCOM_USB_HSIC=m
+CONFIG_PHY_QCOM_USB_HS=m
+CONFIG_PHY_RTK_RTD_USB2PHY=m
+CONFIG_PHY_RTK_RTD_USB3PHY=m
+CONFIG_PHY_SAMSUNG_USB2=m
+CONFIG_PHYSICAL_ALIGN=0x1000000
+CONFIG_PHYSICAL_START=0x1000000
+CONFIG_PHY_TUSB1210=m
+CONFIG_PI433=m
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_ALDERLAKE=m
+CONFIG_PINCTRL_AMDISP=m
+CONFIG_PINCTRL_AMD=y
+CONFIG_PINCTRL_BAYTRAIL=y
+CONFIG_PINCTRL_BROXTON=m
+CONFIG_PINCTRL_CANNONLAKE=m
+CONFIG_PINCTRL_CEDARFORK=m
+CONFIG_PINCTRL_CHERRYVIEW=m
+CONFIG_PINCTRL_CS42L43=m
+CONFIG_PINCTRL_CS47L15=y
+CONFIG_PINCTRL_CS47L35=y
+CONFIG_PINCTRL_CS47L85=y
+CONFIG_PINCTRL_CS47L90=y
+CONFIG_PINCTRL_CS47L92=y
+CONFIG_PINCTRL_CY8C95X0=m
+CONFIG_PINCTRL_DA9062=m
+CONFIG_PINCTRL_DENVERTON=m
+CONFIG_PINCTRL_ELKHARTLAKE=m
+CONFIG_PINCTRL_EMMITSBURG=m
+CONFIG_PINCTRL_GEMINILAKE=m
+CONFIG_PINCTRL_ICELAKE=m
+CONFIG_PINCTRL_IMX_SCMI=m
+CONFIG_PINCTRL_INTEL_PLATFORM=m
+CONFIG_PINCTRL_INTEL=y
+CONFIG_PINCTRL_JASPERLAKE=m
+CONFIG_PINCTRL_LAKEFIELD=m
+CONFIG_PINCTRL_LEWISBURG=m
+CONFIG_PINCTRL_LYNXPOINT=m
+CONFIG_PINCTRL_MADERA=m
+CONFIG_PINCTRL_MAX7360=m
+CONFIG_PINCTRL_MCP23S08_I2C=m
+CONFIG_PINCTRL_MCP23S08=m
+CONFIG_PINCTRL_MCP23S08_SPI=m
+CONFIG_PINCTRL_METEORLAKE=m
+CONFIG_PINCTRL_METEORPOINT=m
+CONFIG_PINCTRL_SUNRISEPOINT=m
+CONFIG_PINCTRL_TIGERLAKE=m
+CONFIG_PINCTRL_UPBOARD=m
+CONFIG_PINCTRL=y
 CONFIG_PING=m
-CONFIG_RFD77402=m
-CONFIG_SRF04=m
-CONFIG_SX9310=m
-CONFIG_SX9324=m
-CONFIG_SX9360=m
-CONFIG_SX9500=m
-CONFIG_SRF08=m
-CONFIG_VCNL3020=m
-CONFIG_VL53L0X_I2C=m
-# end of Proximity and distance sensors
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S90=m
-CONFIG_AD2S1200=m
-# end of Resolver to digital converters
-
-#
-# Temperature sensors
-#
-CONFIG_IQS620AT_TEMP=m
-CONFIG_LTC2983=m
-CONFIG_MAXIM_THERMOCOUPLE=m
-CONFIG_HID_SENSOR_TEMP=m
-CONFIG_MLX90614=m
-CONFIG_MLX90632=m
-CONFIG_TMP006=m
-CONFIG_TMP007=m
-CONFIG_TMP117=m
-CONFIG_TSYS01=m
-CONFIG_TSYS02D=m
-CONFIG_MAX31856=m
-# end of Temperature sensors
-
-CONFIG_NTB=m
-CONFIG_NTB_MSI=y
-CONFIG_NTB_IDT=m
-CONFIG_NTB_EPF=m
-CONFIG_NTB_SWITCHTEC=m
-CONFIG_NTB_PINGPONG=m
-CONFIG_NTB_TOOL=m
-CONFIG_NTB_PERF=m
-CONFIG_NTB_MSI_TEST=m
-CONFIG_NTB_TRANSPORT=m
-CONFIG_VME_BUS=y
-
-#
-# VME Bridge Drivers
-#
-CONFIG_VME_CA91CX42=m
-CONFIG_VME_TSI148=m
-CONFIG_VME_FAKE=m
-
-#
-# VME Board Drivers
-#
-CONFIG_VMIVME_7805=m
-
-#
-# VME Device Drivers
-#
-CONFIG_VME_USER=m
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_PWM_DEBUG is not set
+CONFIG_PINMUX=y
+CONFIG_PKCS7_TEST_KEY=m
+CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
+CONFIG_PLATFORM_SI4713=m
+CONFIG_PLDMFW=y
+CONFIG_PLFXLC=m
+CONFIG_PLIP=m
+CONFIG_PLX_DMA=m
+CONFIG_PLX_HERMES=m
+CONFIG_PM_AUTOSLEEP=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PMIC_DA9052=y
+CONFIG_PMIC_OPREGION=y
+CONFIG_PM_OPP=y
+CONFIG_PMS7003=m
+CONFIG_PM_STD_PARTITION=""
+CONFIG_PM_WAKELOCKS_GC=y
+CONFIG_PM_WAKELOCKS_LIMIT=100
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PNPACPI=y
+CONFIG_PNPBIOS_PROC_FS=y
+CONFIG_PNPBIOS=y
+CONFIG_PNP=y
+CONFIG_POLYNOMIAL=m
+CONFIG_PORTWELL_EC=m
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWERCAP=y
+CONFIG_POWER_RESET_ATC260X=m
+CONFIG_POWER_RESET_MT6323=y
+CONFIG_POWER_RESET_TPS65086=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPDEV=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOATM=m
+CONFIG_PPPOE_HASH_BITS=4
+CONFIG_PPPOE_HASH_BITS_4=y
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPS_CLIENT_GPIO=m
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PPS_CLIENT_PARPORT=m
+CONFIG_PPS_GENERATOR_TIO=m
+CONFIG_PPS=y
+CONFIG_PPTP=m
+CONFIG_PREEMPT_BUILD=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_PREEMPT_DYNAMIC=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_PREEMPT_RCU=y
+CONFIG_PREEMPT=y
+CONFIG_PRIME_NUMBERS=m
+CONFIG_PRINTER=m
+CONFIG_PRINTK_INDEX=y
+CONFIG_PRISM2_USB=m
+CONFIG_PROCESSOR_SELECT=y
+CONFIG_PSAMPLE=m
+CONFIG_PSE_CONTROLLER=y
+CONFIG_PSE_PD692X0=m
+CONFIG_PSE_REGULATOR=m
+CONFIG_PSE_SI3474=m
+CONFIG_PSE_TPS23881=m
+CONFIG_PSI=y
+CONFIG_PTDUMP_CORE=y
+CONFIG_PTP_1588_CLOCK_FC3W=m
+CONFIG_PTP_1588_CLOCK_IDT82P33=m
+CONFIG_PTP_1588_CLOCK_IDTCM=m
+CONFIG_PTP_1588_CLOCK_INES=m
+CONFIG_PTP_1588_CLOCK_KVM=m
+CONFIG_PTP_1588_CLOCK_MOCK=m
+CONFIG_PTP_1588_CLOCK_OCP=m
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PTP_1588_CLOCK_QORIQ=m
+CONFIG_PTP_1588_CLOCK_VMW=m
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_DFL_TOD=m
+CONFIG_PTP_NETC_V4_TIMER=m
+CONFIG_PVH=y
+CONFIG_PVPANIC_MMIO=m
+CONFIG_PVPANIC_PCI=m
+CONFIG_PVPANIC=y
 CONFIG_PWM_CLK=m
 CONFIG_PWM_CROS_EC=m
 CONFIG_PWM_DWC=m
+CONFIG_PWM_GPIO=m
 CONFIG_PWM_IQS620A=m
 CONFIG_PWM_LP3943=m
 CONFIG_PWM_LPSS=m
 CONFIG_PWM_LPSS_PCI=m
 CONFIG_PWM_LPSS_PLATFORM=m
+CONFIG_PWM_MAX7360=m
 CONFIG_PWM_PCA9685=m
-CONFIG_PWM_SL28CPLD=m
-
-#
-# IRQ chip support
-#
-CONFIG_MADERA_IRQ=m
-CONFIG_MST_IRQ=y
-# end of IRQ chip support
-
-CONFIG_IPACK_BUS=m
-CONFIG_BOARD_TPCI200=m
-CONFIG_SERIAL_IPOCTAL=m
+CONFIG_PWM_PROVIDE_GPIO=y
+CONFIG_PWM_SYSFS=y
+CONFIG_PWM=y
+CONFIG_QAT_VFIO_PCI=m
+CONFIG_QCA807X_PHY=m
+CONFIG_QCA808X_PHY=m
+CONFIG_QCA83XX_PHY=m
+CONFIG_QCOM_HIDMA=m
+CONFIG_QCOM_HIDMA_MGMT=m
+CONFIG_QCOM_PBS=m
+CONFIG_QCOM_QMI_HELPERS=m
+CONFIG_QCOM_SPMI_ADC5=m
+CONFIG_QCOM_SPMI_IADC=m
+CONFIG_QCOM_SPMI_VADC=m
+CONFIG_QCOMTEE=m
+CONFIG_QCOM_TZMEM_MODE_GENERIC=y
+CONFIG_QCOM_VADC_COMMON=m
+CONFIG_QEDF=m
+CONFIG_QLGE=m
+CONFIG_QSEMI_PHY=m
+CONFIG_QTNFMAC=m
+CONFIG_QTNFMAC_PCIE=m
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_R8712U=m
+CONFIG_RADIO_ADAPTERS=m
+CONFIG_RADIO_MAXIRADIO=m
+CONFIG_RADIO_SAA7706H=m
+CONFIG_RADIO_SHARK2=m
+CONFIG_RADIO_SHARK=m
+CONFIG_RADIO_SI470X=m
+CONFIG_RADIO_SI4713=m
+CONFIG_RADIO_SI476X=m
+CONFIG_RADIO_TEA575X=m
+CONFIG_RADIO_TEA5764=m
+CONFIG_RADIO_TEF6862=m
+CONFIG_RADIO_WL1273=m
+CONFIG_RADIO_WL128X=m
+CONFIG_RAID6_PQ_BENCHMARK=y
+CONFIG_RAID6_PQ=m
+CONFIG_RAID_ATTRS=m
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y
+CONFIG_RAPIDIO_CHMAN=m
+CONFIG_RAPIDIO_CPS_GEN2=m
+CONFIG_RAPIDIO_CPS_XX=m
+CONFIG_RAPIDIO_DISC_TIMEOUT=30
+CONFIG_RAPIDIO_DMA_ENGINE=y
+CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y
+CONFIG_RAPIDIO_ENUM_BASIC=m
+CONFIG_RAPIDIO=m
+CONFIG_RAPIDIO_MPORT_CDEV=m
+CONFIG_RAPIDIO_RXS_GEN3=m
+CONFIG_RAPIDIO_TSI721=m
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RAVE_SP_CORE=m
+CONFIG_RAVE_SP_WATCHDOG=m
+CONFIG_RC_ATI_REMOTE=m
+CONFIG_RC_CORE=m
+CONFIG_RC_DECODERS=y
+CONFIG_RC_DEVICES=y
+CONFIG_RC_LOOPBACK=m
+CONFIG_RC_MAP=m
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RC_XBOX_DVD=m
+CONFIG_RD_BZIP2=y
+CONFIG_RDMA_RXE=m
+CONFIG_RDMA_SIW=m
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_REALTEK_PHY=m
+CONFIG_REDMI_WMI=m
+CONFIG_REED_SOLOMON_DEC16=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REED_SOLOMON=m
+CONFIG_REGMAP_I2C=m
+CONFIG_REGMAP_I3C=m
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SCCB=m
+CONFIG_REGMAP_SLIMBUS=m
+CONFIG_REGMAP_SOUNDWIRE=m
+CONFIG_REGMAP_SOUNDWIRE_MBQ=m
+CONFIG_REGMAP_SPI_AVMM=m
+CONFIG_REGMAP_SPI=y
+CONFIG_REGMAP_SPMI=m
+CONFIG_REGMAP_W1=m
+CONFIG_REGULATOR_88PG86X=m
+CONFIG_REGULATOR_88PM800=m
+CONFIG_REGULATOR_88PM886=m
+CONFIG_REGULATOR_ACT8865=m
+CONFIG_REGULATOR_AD5398=m
+CONFIG_REGULATOR_ADP5055=m
+CONFIG_REGULATOR_ARIZONA_LDO1=m
+CONFIG_REGULATOR_ARIZONA_MICSUPP=m
+CONFIG_REGULATOR_ATC260X=m
+CONFIG_REGULATOR_AW37503=m
+CONFIG_REGULATOR_AXP20X=m
+CONFIG_REGULATOR_BCM590XX=m
+CONFIG_REGULATOR_BD9571MWV=m
+CONFIG_REGULATOR_DA9052=m
+CONFIG_REGULATOR_DA9062=m
+CONFIG_REGULATOR_DA9210=m
+CONFIG_REGULATOR_DA9211=m
+CONFIG_REGULATOR_FAN53555=m
+CONFIG_REGULATOR_FIXED_VOLTAGE=m
+CONFIG_REGULATOR_GPIO=m
+CONFIG_REGULATOR_ISL6271A=m
+CONFIG_REGULATOR_ISL9305=m
+CONFIG_REGULATOR_LM363X=m
+CONFIG_REGULATOR_LP3971=m
+CONFIG_REGULATOR_LP3972=m
+CONFIG_REGULATOR_LP872X=m
+CONFIG_REGULATOR_LP8755=m
+CONFIG_REGULATOR_LTC3589=m
+CONFIG_REGULATOR_LTC3676=m
+CONFIG_REGULATOR_MAX14577=m
+CONFIG_REGULATOR_MAX1586=m
+CONFIG_REGULATOR_MAX20086=m
+CONFIG_REGULATOR_MAX20411=m
+CONFIG_REGULATOR_MAX5970=m
+CONFIG_REGULATOR_MAX77503=m
+CONFIG_REGULATOR_MAX77693=m
+CONFIG_REGULATOR_MAX77826=m
+CONFIG_REGULATOR_MAX77838=m
+CONFIG_REGULATOR_MAX77857=m
+CONFIG_REGULATOR_MAX8649=m
+CONFIG_REGULATOR_MAX8660=m
+CONFIG_REGULATOR_MAX8893=m
+CONFIG_REGULATOR_MAX8907=m
+CONFIG_REGULATOR_MAX8952=m
+CONFIG_REGULATOR_MC13783=m
+CONFIG_REGULATOR_MC13892=m
+CONFIG_REGULATOR_MC13XXX_CORE=m
+CONFIG_REGULATOR_MP8859=m
+CONFIG_REGULATOR_MT6311=m
+CONFIG_REGULATOR_MT6315=m
+CONFIG_REGULATOR_MT6323=m
+CONFIG_REGULATOR_MT6331=m
+CONFIG_REGULATOR_MT6332=m
+CONFIG_REGULATOR_MT6357=m
+CONFIG_REGULATOR_MT6358=m
+CONFIG_REGULATOR_MT6359=m
+CONFIG_REGULATOR_MT6360=m
+CONFIG_REGULATOR_MT6370=m
+CONFIG_REGULATOR_MT6397=m
+CONFIG_REGULATOR_NETLINK_EVENTS=y
+CONFIG_REGULATOR_PCA9450=m
+CONFIG_REGULATOR_PCAP=m
+CONFIG_REGULATOR_PCF50633=m
+CONFIG_REGULATOR_PF0900=m
+CONFIG_REGULATOR_PF530X=m
+CONFIG_REGULATOR_PF9453=m
+CONFIG_REGULATOR_PV88060=m
+CONFIG_REGULATOR_PV88080=m
+CONFIG_REGULATOR_PV88090=m
+CONFIG_REGULATOR_PWM=m
+CONFIG_REGULATOR_QCOM_LABIBB=m
+CONFIG_REGULATOR_QCOM_PM8008=m
+CONFIG_REGULATOR_QCOM_REFGEN=m
+CONFIG_REGULATOR_QCOM_SPMI=m
+CONFIG_REGULATOR_QCOM_USB_VBUS=m
+CONFIG_REGULATOR_RAA215300=m
+CONFIG_REGULATOR_RT4801=m
+CONFIG_REGULATOR_RT4803=m
+CONFIG_REGULATOR_RT4831=m
+CONFIG_REGULATOR_RT5033=m
+CONFIG_REGULATOR_RT5120=m
+CONFIG_REGULATOR_RT5133=m
+CONFIG_REGULATOR_RT5190A=m
+CONFIG_REGULATOR_RT5739=m
+CONFIG_REGULATOR_RT5759=m
+CONFIG_REGULATOR_RT6160=m
+CONFIG_REGULATOR_RT6190=m
+CONFIG_REGULATOR_RT6245=m
+CONFIG_REGULATOR_RTMV20=m
+CONFIG_REGULATOR_RTQ2134=m
+CONFIG_REGULATOR_RTQ2208=m
+CONFIG_REGULATOR_RTQ6752=m
+CONFIG_REGULATOR_S2DOS05=m
+CONFIG_REGULATOR_SKY81452=m
+CONFIG_REGULATOR_SLG51000=m
+CONFIG_REGULATOR_SY7636A=m
+CONFIG_REGULATOR_TPS51632=m
+CONFIG_REGULATOR_TPS6105X=m
+CONFIG_REGULATOR_TPS62360=m
+CONFIG_REGULATOR_TPS65023=m
+CONFIG_REGULATOR_TPS6507X=m
+CONFIG_REGULATOR_TPS65086=m
+CONFIG_REGULATOR_TPS65132=m
+CONFIG_REGULATOR_TPS6524X=m
+CONFIG_REGULATOR_TPS65912=m
+CONFIG_REGULATOR_TPS68470=m
+CONFIG_REGULATOR_USERSPACE_CONSUMER=m
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
+CONFIG_REGULATOR_WM831X=m
+CONFIG_REGULATOR_WM8994=m
+CONFIG_REGULATOR=y
+CONFIG_RELAY=y
+CONFIG_RELOCATABLE=y
+CONFIG_REMOTE_TARGET=m
+CONFIG_RENESAS_PHY=m
+CONFIG_RESET_ATTACK_MITIGATION=y
 CONFIG_RESET_CONTROLLER=y
 CONFIG_RESET_SIMPLE=y
-CONFIG_RESET_MCHP_SPARX5=y
-CONFIG_RESET_A10SR=m
-# CONFIG_RESET_BRCMSTB_RESCAL is not set
 CONFIG_RESET_TI_SYSCON=m
 CONFIG_RESET_TI_TPS380X=m
-
-#
-# PHY Subsystem
-#
-CONFIG_GENERIC_PHY=y
-CONFIG_PHY_CAN_TRANSCEIVER=m
-CONFIG_USB_LGM_PHY=m
-CONFIG_BCM_KONA_USB2_PHY=m
-CONFIG_PHY_PXA_28NM_HSIC=m
-CONFIG_PHY_PXA_28NM_USB2=m
-CONFIG_PHY_CPCAP_USB=m
-CONFIG_PHY_QCOM_USB_HS=m
-CONFIG_PHY_QCOM_USB_HSIC=m
-CONFIG_PHY_SAMSUNG_USB2=m
-CONFIG_PHY_TUSB1210=m
-CONFIG_PHY_INTEL_LGM_EMMC=m
-# end of PHY Subsystem
-
-CONFIG_POWERCAP=y
-CONFIG_INTEL_RAPL_CORE=m
-CONFIG_INTEL_RAPL=m
-# CONFIG_IDLE_INJECT is not set
-CONFIG_PECI=m
-CONFIG_PECI_CPU=m
-CONFIG_PECI_ASPEED=m
-CONFIG_SENSORS_PECI_CPUTEMP=m
-CONFIG_SENSORS_PECI_DIMMTEMP=m
-CONFIG_DTPM=y
-CONFIG_DTPM_CPU=y
-CONFIG_DTPM_DEVFREQ=y
-CONFIG_MCB=m
-CONFIG_MCB_PCI=m
-CONFIG_MCB_LPC=m
-
-#
-# Performance monitor support
-#
-# end of Performance monitor support
-
-CONFIG_RAS=y
-CONFIG_USB4=m
-# CONFIG_USB4_DEBUGFS_WRITE is not set
-# CONFIG_USB4_DMA_TEST is not set
-
-#
-# Android
-#
-# CONFIG_ANDROID is not set
-# end of Android
-
-CONFIG_LIBNVDIMM=m
-CONFIG_BLK_DEV_PMEM=m
-CONFIG_ND_BLK=m
-CONFIG_ND_CLAIM=y
-CONFIG_ND_BTT=m
-CONFIG_BTT=y
-CONFIG_NVDIMM_KEYS=y
-CONFIG_DAX_DRIVER=y
-CONFIG_DAX=y
-CONFIG_DEV_DAX=m
-CONFIG_DEV_DAX_HMEM=m
-CONFIG_DEV_DAX_HMEM_DEVICES=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_RAVE_SP_EEPROM=m
-CONFIG_NVMEM_SPMI_SDAM=m
-CONFIG_RAVE_SP_EEPROM=m
-CONFIG_NVMEM_RMEM=m
-CONFIG_NVMEM_LAYERSCAPE_SFP=m
-CONFIG_NVMEM_MESON_EFUSE=m
-CONFIG_NVMEM_SPRD_EFUSE=m
-
-#
-# HW tracing support
-#
-CONFIG_STM=m
-CONFIG_STM_PROTO_BASIC=m
-CONFIG_STM_PROTO_SYS_T=m
-# CONFIG_STM_DUMMY is not set
-CONFIG_STM_SOURCE_CONSOLE=m
-CONFIG_STM_SOURCE_HEARTBEAT=m
-# CONFIG_STM_SOURCE_FTRACE is not set
-CONFIG_INTEL_TH=m
-CONFIG_INTEL_TH_PCI=m
-CONFIG_INTEL_TH_ACPI=m
-CONFIG_INTEL_TH_GTH=m
-CONFIG_INTEL_TH_STH=m
-CONFIG_INTEL_TH_MSU=m
-CONFIG_INTEL_TH_PTI=m
-CONFIG_HISI_PTT=m
-# CONFIG_INTEL_TH_DEBUG is not set
-# end of HW tracing support
-
-CONFIG_FPGA=m
-CONFIG_FPGA_MGR_SOCFPGA=m
-CONFIG_FPGA_MGR_SOCFPGA_A10=m
-CONFIG_ALTERA_PR_IP_CORE=m
-CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
-CONFIG_FPGA_MGR_ALTERA_CVP=m
-CONFIG_FPGA_MGR_XILINX_SPI=m
-CONFIG_FPGA_MGR_MACHXO2_SPI=m
-CONFIG_FPGA_BRIDGE=m
-CONFIG_ALTERA_FREEZE_BRIDGE=m
-CONFIG_XILINX_PR_DECOUPLER=m
-CONFIG_FPGA_REGION=m
-CONFIG_FPGA_DFL=m
-CONFIG_FPGA_DFL_FME=m
-CONFIG_FPGA_DFL_FME_MGR=m
-CONFIG_FPGA_DFL_FME_BRIDGE=m
-CONFIG_FPGA_DFL_FME_REGION=m
-CONFIG_FPGA_DFL_AFU=m
-CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
-CONFIG_FPGA_DFL_PCI=m
-CONFIG_FPGA_M10_BMC_SEC_UPDATE=m
-CONFIG_FPGA_MGR_MICROCHIP_SPI=m
-CONFIG_TEE=m
-
-#
-# TEE drivers
-#
-# end of TEE drivers
-
-CONFIG_MULTIPLEXER=m
-
-#
-# Multiplexer drivers
-#
-CONFIG_MUX_ADG792A=m
-CONFIG_MUX_ADGS1408=m
-CONFIG_MUX_GPIO=m
-# end of Multiplexer drivers
-
-CONFIG_PM_OPP=y
-CONFIG_SIOX=m
+CONFIG_RETHOOK=y
+CONFIG_RETHUNK=y
+CONFIG_RETPOLINE=y
+CONFIG_RETU_WATCHDOG=m
+CONFIG_RFD77402=m
+CONFIG_RFD_FTL=m
+CONFIG_RFKILL_GPIO=m
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL=m
+CONFIG_RICHTEK_RTQ6056=m
+CONFIG_RIONET=m
+CONFIG_RIONET_RX_SIZE=128
+CONFIG_RIONET_TX_SIZE=128
+CONFIG_ROCKCHIP_PHY=m
+CONFIG_ROHM_BM1390=m
+CONFIG_ROHM_BU27008=m
+CONFIG_ROHM_BU27034=m
+CONFIG_RPMSG_CHAR=m
+CONFIG_RPMSG_CTRL=m
+CONFIG_RPMSG=m
+CONFIG_RPMSG_NS=m
+CONFIG_RPMSG_QCOM_GLINK=m
+CONFIG_RPMSG_QCOM_GLINK_RPM=m
+CONFIG_RPMSG_TTY=m
+CONFIG_RPMSG_VIRTIO=m
+CONFIG_RPMSG_WWAN_CTRL=m
+CONFIG_RPR0521=m
+CONFIG_RSI_91X=m
+CONFIG_RSI_COEX=y
+CONFIG_RSI_SDIO=m
+CONFIG_RSI_USB=m
+CONFIG_RT2400PCI=m
+CONFIG_RT2500PCI=m
+CONFIG_RT2500USB=m
+CONFIG_RT2800_LIB=m
+CONFIG_RT2800_LIB_MMIO=m
+CONFIG_RT2800PCI=m
+CONFIG_RT2800PCI_RT3290=y
+CONFIG_RT2800PCI_RT33XX=y
+CONFIG_RT2800PCI_RT35XX=y
+CONFIG_RT2800PCI_RT53XX=y
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT3573=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_LEDS=y
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_MMIO=m
+CONFIG_RT2X00_LIB_PCI=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00=m
+CONFIG_RT61PCI=m
+CONFIG_RT73USB=m
+CONFIG_RTC_DRV_88PM80X=m
+CONFIG_RTC_DRV_ABB5ZES3=m
+CONFIG_RTC_DRV_ABEOZ9=m
+CONFIG_RTC_DRV_ABX80X=m
+CONFIG_RTC_DRV_BQ32K=m
+CONFIG_RTC_DRV_BQ4802=m
+CONFIG_RTC_DRV_CMOS=y
+CONFIG_RTC_DRV_DA9052=m
+CONFIG_RTC_DRV_DA9063=m
+CONFIG_RTC_DRV_DS1286=m
+CONFIG_RTC_DRV_DS1302=m
+CONFIG_RTC_DRV_DS1305=m
+CONFIG_RTC_DRV_DS1307=m
+CONFIG_RTC_DRV_DS1343=m
+CONFIG_RTC_DRV_DS1347=m
+CONFIG_RTC_DRV_DS1374=m
+CONFIG_RTC_DRV_DS1374_WDT=y
+CONFIG_RTC_DRV_DS1390=m
+CONFIG_RTC_DRV_DS1511=m
+CONFIG_RTC_DRV_DS1553=m
+CONFIG_RTC_DRV_DS1672=m
+CONFIG_RTC_DRV_DS1685_FAMILY=m
+CONFIG_RTC_DRV_DS1685=y
+CONFIG_RTC_DRV_DS1742=m
+CONFIG_RTC_DRV_DS2404=m
+CONFIG_RTC_DRV_DS3232_HWMON=y
+CONFIG_RTC_DRV_DS3232=m
+CONFIG_RTC_DRV_EM3027=m
+CONFIG_RTC_DRV_FM3130=m
+CONFIG_RTC_DRV_FTRTC010=m
+CONFIG_RTC_DRV_GOLDFISH=m
+CONFIG_RTC_DRV_HID_SENSOR_TIME=m
+CONFIG_RTC_DRV_ISL12022=m
+CONFIG_RTC_DRV_ISL1208=m
+CONFIG_RTC_DRV_M41T80=m
+CONFIG_RTC_DRV_M41T80_WDT=y
+CONFIG_RTC_DRV_M41T93=m
+CONFIG_RTC_DRV_M41T94=m
+CONFIG_RTC_DRV_M48T35=m
+CONFIG_RTC_DRV_M48T59=m
+CONFIG_RTC_DRV_M48T86=m
+CONFIG_RTC_DRV_MAX31335=m
+CONFIG_RTC_DRV_MAX6900=m
+CONFIG_RTC_DRV_MAX6902=m
+CONFIG_RTC_DRV_MAX6916=m
+CONFIG_RTC_DRV_MAX8907=m
+CONFIG_RTC_DRV_MC13XXX=m
+CONFIG_RTC_DRV_MCP795=m
+CONFIG_RTC_DRV_MSM6242=m
+CONFIG_RTC_DRV_MT6397=m
+CONFIG_RTC_DRV_PCAP=m
+CONFIG_RTC_DRV_PCF2123=m
+CONFIG_RTC_DRV_PCF2127=m
+CONFIG_RTC_DRV_PCF50633=m
+CONFIG_RTC_DRV_PCF85063=m
+CONFIG_RTC_DRV_PCF8523=m
+CONFIG_RTC_DRV_PCF85363=m
+CONFIG_RTC_DRV_PCF8563=m
+CONFIG_RTC_DRV_PCF8583=m
+CONFIG_RTC_DRV_R9701=m
+CONFIG_RTC_DRV_RP5C01=m
+CONFIG_RTC_DRV_RS5C348=m
+CONFIG_RTC_DRV_RS5C372=m
+CONFIG_RTC_DRV_RV3028=m
+CONFIG_RTC_DRV_RV3029C2=m
+CONFIG_RTC_DRV_RV3029_HWMON=y
+CONFIG_RTC_DRV_RV3032=m
+CONFIG_RTC_DRV_RV8803=m
+CONFIG_RTC_DRV_RX4581=m
+CONFIG_RTC_DRV_RX6110=m
+CONFIG_RTC_DRV_RX8010=m
+CONFIG_RTC_DRV_RX8025=m
+CONFIG_RTC_DRV_RX8581=m
+CONFIG_RTC_DRV_S35390A=m
+CONFIG_RTC_DRV_SD3078=m
+CONFIG_RTC_DRV_STK17TA8=m
+CONFIG_RTC_DRV_TPS6594=m
+CONFIG_RTC_DRV_WILCO_EC=m
+CONFIG_RTC_DRV_WM831X=m
+CONFIG_RTC_DRV_X1205=m
+CONFIG_RTC_I2C_AND_SPI=m
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RTL8180=m
+CONFIG_RTL8187_LEDS=y
+CONFIG_RTL8187=m
+CONFIG_RTL8188EE=m
+CONFIG_RTL8192C_COMMON=m
+CONFIG_RTL8192CE=m
+CONFIG_RTL8192CU=m
+CONFIG_RTL8192DE=m
+CONFIG_RTL8192DU=m
+CONFIG_RTL8192EE=m
+CONFIG_RTL8192E=m
+CONFIG_RTL8192SE=m
+CONFIG_RTL8192U=m
+CONFIG_RTL8723AE=m
+CONFIG_RTL8723BE=m
+CONFIG_RTL8723BS=m
+CONFIG_RTL8723_COMMON=m
+CONFIG_RTL8821AE=m
+CONFIG_RTL8XXXU=m
+CONFIG_RTL8XXXU_UNTESTED=y
+CONFIG_RTLBTCOEXIST=m
+CONFIG_RTL_CARDS=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+CONFIG_RTLLIB=m
+CONFIG_RTLWIFI=m
+CONFIG_RTLWIFI_PCI=m
+CONFIG_RTLWIFI_USB=m
+CONFIG_RTS5208=m
+CONFIG_RTW88_8723CS=m
+CONFIG_RTW88_8723DE=m
+CONFIG_RTW88_8723D=m
+CONFIG_RTW88_8723DS=m
+CONFIG_RTW88_8723DU=m
+CONFIG_RTW88_8821CE=m
+CONFIG_RTW88_8821C=m
+CONFIG_RTW88_8821CS=m
+CONFIG_RTW88_8821CU=m
+CONFIG_RTW88_8822BE=m
+CONFIG_RTW88_8822B=m
+CONFIG_RTW88_8822BS=m
+CONFIG_RTW88_8822BU=m
+CONFIG_RTW88_8822CE=m
+CONFIG_RTW88_8822C=m
+CONFIG_RTW88_8822CS=m
+CONFIG_RTW88_8822CU=m
+CONFIG_RTW88_CORE=m
+CONFIG_RTW88=m
+CONFIG_RTW88_PCI=m
+CONFIG_RTW88_SDIO=m
+CONFIG_RTW88_USB=m
+CONFIG_RTW89_8851BE=m
+CONFIG_RTW89_8851B=m
+CONFIG_RTW89_8852AE=m
+CONFIG_RTW89_8852A=m
+CONFIG_RTW89_8852BE=m
+CONFIG_RTW89_8852B=m
+CONFIG_RTW89_8852BTE=m
+CONFIG_RTW89_8852CE=m
+CONFIG_RTW89_8852C=m
+CONFIG_RTW89_8922AE=m
+CONFIG_RTW89_CORE=m
+CONFIG_RTW89_DEBUGFS=y
+CONFIG_RTW89_DEBUG=y
+CONFIG_RTW89=m
+CONFIG_RTW89_PCI=m
+CONFIG_SAMSUNG_GALAXYBOOK=m
+CONFIG_SAMSUNG_LAPTOP=m
+CONFIG_SAMSUNG_Q10=m
+CONFIG_SATA_ACARD_AHCI=m
+CONFIG_SATA_AHCI=m
+CONFIG_SATA_AHCI_PLATFORM=m
+CONFIG_SATA_DWC=m
+CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MV=m
+CONFIG_SATA_NV=m
+CONFIG_SATA_PROMISE=m
+CONFIG_SATA_QSTOR=m
+CONFIG_SATA_SIL24=m
+CONFIG_SATA_SIL=m
+CONFIG_SATA_SIS=m
+CONFIG_SATA_SVW=m
+CONFIG_SATA_SX4=m
+CONFIG_SATA_ULI=m
+CONFIG_SATA_VIA=m
+CONFIG_SATA_VITESSE=m
+CONFIG_SATA_ZPODD=y
+CONFIG_SBC_EPX_C3_WATCHDOG=m
+CONFIG_SBC_FITPC2_WATCHDOG=m
+CONFIG_SBP_TARGET=m
+CONFIG_SC1200_WDT=m
+CONFIG_SCA3000=m
+CONFIG_SCA3300=m
+CONFIG_SCD30_CORE=m
+CONFIG_SCD30_I2C=m
+CONFIG_SCD30_SERIAL=m
+CONFIG_SCD4X=m
+CONFIG_SCF_TORTURE_TEST=m
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SCHED_CLUSTER=y
+CONFIG_SCHED_CORE=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHED_MC_PRIO=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_MM_CID=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_SCHED_SMT=y
+CONFIG_SCHEDSTATS=y
+CONFIG_SCSI_3W_9XXX=m
+CONFIG_SCSI_3W_SAS=m
+CONFIG_SCSI_AACRAID=m
+CONFIG_SCSI_ACARD=m
+CONFIG_SCSI_ADVANSYS=m
+CONFIG_SCSI_AHA152X=m
+CONFIG_SCSI_AHA1542=m
+CONFIG_SCSI_AIC79XX=m
+CONFIG_SCSI_AIC7XXX=m
+CONFIG_SCSI_AIC94XX=m
+CONFIG_SCSI_AM53C974=m
+CONFIG_SCSI_ARCMSR=m
+CONFIG_SCSI_BFA_FC=m
+CONFIG_SCSI_BNX2_ISCSI=m
+CONFIG_SCSI_BNX2X_FCOE=m
+CONFIG_SCSI_BUSLOGIC=m
+CONFIG_SCSI_CHELSIO_FCOE=m
+CONFIG_SCSI_COMMON=m
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_CXGB3_ISCSI=m
+CONFIG_SCSI_CXGB4_ISCSI=m
+CONFIG_SCSI_DC395x=m
+CONFIG_SCSI_DH_ALUA=m
+CONFIG_SCSI_DH_EMC=m
+CONFIG_SCSI_DH_HP_SW=m
+CONFIG_SCSI_DH_RDAC=m
+CONFIG_SCSI_DH=y
+CONFIG_SCSI_DMX3191D=m
+CONFIG_SCSI_EFCT=m
+CONFIG_SCSI_ENCLOSURE=m
+CONFIG_SCSI_ESAS2R=m
+CONFIG_SCSI_FC_ATTRS=m
+CONFIG_SCSI_FDOMAIN_ISA=m
+CONFIG_SCSI_FDOMAIN=m
+CONFIG_SCSI_FDOMAIN_PCI=m
+CONFIG_SCSI_FLASHPOINT=y
+CONFIG_SCSI_GENERIC_NCR5380=m
+CONFIG_SCSI_HPSA=m
+CONFIG_SCSI_HPTIOP=m
+CONFIG_SCSI_IMM=m
+CONFIG_SCSI_INIA100=m
+CONFIG_SCSI_INITIO=m
+CONFIG_SCSI_IPR=m
+CONFIG_SCSI_IPS=m
+CONFIG_SCSI_ISCI=m
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_LOWLEVEL_PCMCIA=y
+CONFIG_SCSI_LPFC=m
+CONFIG_SCSI=m
+CONFIG_SCSI_MOD=m
+CONFIG_SCSI_MPI3MR=m
+CONFIG_SCSI_MPT2SAS=m
+CONFIG_SCSI_MPT2SAS_MAX_SGE=128
+CONFIG_SCSI_MPT3SAS=m
+CONFIG_SCSI_MPT3SAS_MAX_SGE=128
+CONFIG_SCSI_MVSAS=m
+CONFIG_SCSI_MVSAS_TASKLET=y
+CONFIG_SCSI_MVUMI=m
+CONFIG_SCSI_MYRB=m
+CONFIG_SCSI_MYRS=m
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_NSP32=m
+CONFIG_SCSI_PM8001=m
+CONFIG_SCSI_PMCRAID=m
+CONFIG_SCSI_PPA=m
+CONFIG_SCSI_PROC_FS=y
+CONFIG_SCSI_QLA_FC=m
+CONFIG_SCSI_QLA_ISCSI=m
+CONFIG_SCSI_QLOGIC_1280=m
+CONFIG_SCSI_QLOGIC_FAS=m
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_SMARTPQI=m
+CONFIG_SCSI_SNIC=m
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_STEX=m
+CONFIG_SCSI_SYM53C8XX_2=m
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+CONFIG_SCSI_SYM53C8XX_MMIO=y
+CONFIG_SCSI_UFS_CDNS_PLATFORM=m
+CONFIG_SCSI_UFS_DWC_TC_PCI=m
+CONFIG_SCSI_UFSHCD=m
+CONFIG_SCSI_UFSHCD_PCI=m
+CONFIG_SCSI_UFSHCD_PLATFORM=m
+CONFIG_SCSI_UFS_HPB=y
+CONFIG_SCSI_UFS_HWMON=y
+CONFIG_SCSI_VIRTIO=m
+CONFIG_SCSI_WD719X=m
+CONFIG_SD_ADC_MODULATOR=m
+CONFIG_SDIO_UART=m
+CONFIG_SDP500=m
+CONFIG_SDR_PLATFORM_DRIVERS=y
+CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN=y
+CONFIG_SECONDARY_TRUSTED_KEYRING=y
+CONFIG_SECRETMEM=y
+CONFIG_SEG_LED_GPIO=m
+CONFIG_SEL3350_PLATFORM=m
+CONFIG_SENSEAIR_SUNRISE_CO2=m
+CONFIG_SENSIRION_SGP30=m
+CONFIG_SENSIRION_SGP40=m
+CONFIG_SENSORS_ABITUGURU3=m
+CONFIG_SENSORS_ABITUGURU=m
+CONFIG_SENSORS_ACPI_POWER=m
+CONFIG_SENSORS_APPLESMC=m
+CONFIG_SENSORS_ASB100=m
+CONFIG_SENSORS_ASUS_EC=m
+CONFIG_SENSORS_ASUS_WMI=m
+CONFIG_SENSORS_ATK0110=m
+CONFIG_SENSORS_CORETEMP=m
+CONFIG_SENSORS_DELL_SMM=m
+CONFIG_SENSORS_FAM15H_POWER=m
+CONFIG_SENSORS_FSCHMD=m
+CONFIG_SENSORS_HDAPS=m
+CONFIG_SENSORS_HP_WMI=m
+CONFIG_SENSORS_I5500=m
+CONFIG_SENSORS_K10TEMP=m
+CONFIG_SENSORS_K8TEMP=m
+CONFIG_SENSORS_LENOVO_EC=m
+CONFIG_SENSORS_VIA_CPUTEMP=m
+CONFIG_SENSORS_XGENE=m
+CONFIG_SERIAL_8250_CS=m
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_DFL=m
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_DW=m
+CONFIG_SERIAL_8250_EXAR=m
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FINTEK=y
+CONFIG_SERIAL_8250_LPSS=m
+CONFIG_SERIAL_8250=m
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_MEN_MCB=m
+CONFIG_SERIAL_8250_MID=m
+CONFIG_SERIAL_8250_NI=m
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI1XXXX=m
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_PCI=m
+CONFIG_SERIAL_8250_PERICOM=m
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_ALTERA_JTAGUART=m
+CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
+CONFIG_SERIAL_ALTERA_UART=m
+CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
+CONFIG_SERIAL_ARC=m
+CONFIG_SERIAL_ARC_NR_PORTS=1
+CONFIG_SERIAL_DEV_BUS=m
+CONFIG_SERIAL_FSL_LINFLEXUART=m
+CONFIG_SERIAL_FSL_LPUART=m
+CONFIG_SERIAL_IPOCTAL=m
+CONFIG_SERIAL_JSM=m
+CONFIG_SERIAL_LANTIQ=m
+CONFIG_SERIAL_MAX3100=m
+CONFIG_SERIAL_MAX310X=y
+CONFIG_SERIAL_MCTRL_GPIO=m
+CONFIG_SERIAL_MEN_Z135=m
+CONFIG_SERIAL_MULTI_INSTANTIATE=m
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_RP2=m
+CONFIG_SERIAL_RP2_NR_UARTS=32
+CONFIG_SERIAL_SC16IS7XX_CORE=m
+CONFIG_SERIAL_SC16IS7XX_I2C=y
+CONFIG_SERIAL_SC16IS7XX=m
+CONFIG_SERIAL_SC16IS7XX_SPI=y
+CONFIG_SERIAL_SCCNXP=m
+CONFIG_SERIAL_SPRD=m
+CONFIG_SERIAL_UARTLITE=m
+CONFIG_SERIAL_UARTLITE_NR_UARTS=1
+CONFIG_SERIO_ALTERA_PS2=m
+CONFIG_SERIO_ARC_PS2=m
+CONFIG_SERIO_CT82C710=m
+CONFIG_SERIO_GPIO_PS2=m
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO=m
+CONFIG_SERIO_PARKBD=m
+CONFIG_SERIO_PCIPS2=m
+CONFIG_SERIO_PS2MULT=m
+CONFIG_SERIO_RAW=m
+CONFIG_SERIO_SERPORT=m
+CONFIG_SF_PDMA=m
+CONFIG_SGETMASK_SYSCALL=y
+CONFIG_SGI_PARTITION=y
+CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
+CONFIG_SI1133=m
+CONFIG_SI1145=m
+CONFIG_SI7005=m
+CONFIG_SI7020=m
+CONFIG_SIEMENS_SIMATIC_IPC_BATT_APOLLOLAKE=m
+CONFIG_SIEMENS_SIMATIC_IPC_BATT_ELKHARTLAKE=m
+CONFIG_SIEMENS_SIMATIC_IPC_BATT_F7188X=m
+CONFIG_SIEMENS_SIMATIC_IPC_BATT=m
+CONFIG_SIEMENS_SIMATIC_IPC=m
+CONFIG_SIEMENS_SIMATIC_IPC_WDT=m
+CONFIG_SIGNED_PE_FILE_VERIFICATION=y
+CONFIG_SILICOM_PLATFORM=m
 CONFIG_SIOX_BUS_GPIO=m
+CONFIG_SIOX=m
+CONFIG_SLAB_FREELIST_HARDENED=y
+CONFIG_SLAB_FREELIST_RANDOM=y
+CONFIG_SLAB_MERGE_DEFAULT=y
+CONFIG_SLHC=m
 CONFIG_SLIMBUS=m
 CONFIG_SLIM_QCOM_CTRL=m
-# CONFIG_INTERCONNECT is not set
-CONFIG_COUNTER=m
-CONFIG_INTERRUPT_CNT=m
-CONFIG_INTEL_QEP=m
-CONFIG_TI_ECAP_CAPTURE=m
-CONFIG_MOST=m
-CONFIG_MOST_USB_HDM=m
-CONFIG_MOST_CDEV=m
-CONFIG_MOST_SND=m
-CONFIG_NETFS_SUPPORT=m
-CONFIG_NETFS_STATS=y
-# end of Device Drivers
-
-#
-# File systems
-#
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_VALIDATE_FS_PARSER=y
-CONFIG_FS_IOMAP=y
-# CONFIG_EXT2_FS is not set
-# CONFIG_EXT3_FS is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_USE_FOR_EXT2=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD2=m
-# CONFIG_JBD2_DEBUG is not set
-CONFIG_FS_MBCACHE=m
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-CONFIG_REISERFS_PROC_INFO=y
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_SECURITY=y
-# CONFIG_JFS_DEBUG is not set
-CONFIG_JFS_STATISTICS=y
-CONFIG_XFS_FS=m
-# CONFIG_XFS_SUPPORT_V4 is not set
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_XFS_ONLINE_SCRUB=y
-# CONFIG_XFS_ONLINE_REPAIR is not set
-# CONFIG_XFS_WARN is not set
-# CONFIG_XFS_DEBUG is not set
-CONFIG_GFS2_FS=m
-CONFIG_GFS2_FS_LOCKING_DLM=y
-CONFIG_OCFS2_FS=m
-CONFIG_OCFS2_FS_O2CB=m
-CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
-CONFIG_OCFS2_FS_STATS=y
-CONFIG_OCFS2_DEBUG_MASKLOG=y
-CONFIG_OCFS2_DEBUG_FS=y
-CONFIG_BTRFS_FS=m
-CONFIG_BTRFS_FS_POSIX_ACL=y
-# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
-# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
-# CONFIG_BTRFS_DEBUG is not set
-# CONFIG_BTRFS_ASSERT is not set
-# CONFIG_BTRFS_FS_REF_VERIFY is not set
-CONFIG_NILFS2_FS=m
-CONFIG_F2FS_FS=m
-CONFIG_F2FS_STAT_FS=y
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_FS_POSIX_ACL=y
-CONFIG_F2FS_FS_SECURITY=y
-# CONFIG_F2FS_CHECK_FS is not set
-# CONFIG_F2FS_IO_TRACE is not set
-# CONFIG_F2FS_FAULT_INJECTION is not set
-CONFIG_F2FS_FS_COMPRESSION=y
-CONFIG_F2FS_FS_LZO=y
-CONFIG_F2FS_FS_LZ4=y
-CONFIG_F2FS_FS_LZ4HC=y
-CONFIG_F2FS_FS_ZSTD=y
-CONFIG_F2FS_FS_LZORLE=y
-CONFIG_ZONEFS_FS=m
-CONFIG_FS_DAX=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_EXPORTFS=y
-CONFIG_EXPORTFS_BLOCK_OPS=y
-CONFIG_FILE_LOCKING=y
-CONFIG_MANDATORY_FILE_LOCKING=y
-CONFIG_FS_ENCRYPTION=y
-CONFIG_FS_ENCRYPTION_ALGS=m
-# CONFIG_FS_VERITY is not set
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY_USER=y
-CONFIG_FANOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-# CONFIG_QUOTA_DEBUG is not set
-CONFIG_QUOTA_TREE=m
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=m
-CONFIG_QUOTACTL=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_AUTOFS_FS=y
-CONFIG_FUSE_FS=m
-CONFIG_CUSE=m
-CONFIG_VIRTIO_FS=m
-CONFIG_FUSE_DAX=y
-CONFIG_OVERLAY_FS=m
-CONFIG_OVERLAY_FS_REDIRECT_DIR=y
-CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
-CONFIG_OVERLAY_FS_INDEX=y
-CONFIG_OVERLAY_FS_NFS_EXPORT=y
-# CONFIG_OVERLAY_FS_METACOPY is not set
-
-#
-# Caches
-#
-CONFIG_FSCACHE=m
-CONFIG_FSCACHE_STATS=y
-# CONFIG_FSCACHE_HISTOGRAM is not set
-# CONFIG_FSCACHE_DEBUG is not set
-# CONFIG_FSCACHE_OBJECT_LIST is not set
-CONFIG_CACHEFILES=m
-# CONFIG_CACHEFILES_DEBUG is not set
-# CONFIG_CACHEFILES_HISTOGRAM is not set
-# end of Caches
-
-#
-# CD-ROM/DVD Filesystems
-#
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-# end of CD-ROM/DVD Filesystems
-
-#
-# DOS/FAT/EXFAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
-# CONFIG_FAT_DEFAULT_UTF8 is not set
-CONFIG_EXFAT_FS=m
-CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-CONFIG_NTFS_RW=y
-CONFIG_NTFS3_FS=m
-CONFIG_NTFS3_LZX_XPRESS=y
-CONFIG_NTFS3_FS_POSIX_ACL=y
-# CONFIG_NTFS3_64BIT_CLUSTER is not set
-# end of DOS/FAT/EXFAT/NT Filesystems
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_CHILDREN=y
-CONFIG_PROC_PID_ARCH_STATUS=y
-CONFIG_PROC_CPU_RESCTRL=y
-CONFIG_KERNFS=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TMPFS_XATTR=y
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE_FREE_VMEMMAP_DEFAULT_ON=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_EFIVAR_FS=m
-# end of Pseudo filesystems
-
-CONFIG_MISC_FILESYSTEMS=y
-CONFIG_ORANGEFS_FS=m
-CONFIG_ADFS_FS=m
-# CONFIG_ADFS_FS_RW is not set
-CONFIG_AFFS_FS=m
-CONFIG_ECRYPT_FS=m
-CONFIG_ECRYPT_FS_MESSAGING=y
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-# CONFIG_BEFS_DEBUG is not set
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RTIME=y
-CONFIG_JFFS2_RUBIN=y
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-CONFIG_UBIFS_FS=m
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UBIFS_FS_ZSTD=y
-CONFIG_UBIFS_ATIME_SUPPORT=y
-CONFIG_UBIFS_FS_XATTR=y
-CONFIG_UBIFS_FS_SECURITY=y
-# CONFIG_UBIFS_FS_AUTHENTICATION is not set
-CONFIG_CRAMFS=m
-CONFIG_CRAMFS_BLOCKDEV=y
-CONFIG_CRAMFS_MTD=y
-CONFIG_SQUASHFS=m
-# CONFIG_SQUASHFS_FILE_CACHE is not set
-CONFIG_SQUASHFS_FILE_DIRECT=y
-# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
-CONFIG_SQUASHFS_DECOMP_MULTI=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_XATTR=y
-CONFIG_SQUASHFS_ZLIB=y
-CONFIG_SQUASHFS_LZ4=y
-CONFIG_SQUASHFS_LZO=y
-CONFIG_SQUASHFS_XZ=y
-CONFIG_SQUASHFS_ZSTD=y
-CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
-CONFIG_SQUASHFS_EMBEDDED=y
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_OMFS_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_QNX6FS_FS=m
-# CONFIG_QNX6FS_DEBUG is not set
-CONFIG_ROMFS_FS=m
-# CONFIG_ROMFS_BACKED_BY_BLOCK is not set
-# CONFIG_ROMFS_BACKED_BY_MTD is not set
-CONFIG_ROMFS_BACKED_BY_BOTH=y
-CONFIG_ROMFS_ON_BLOCK=y
-CONFIG_ROMFS_ON_MTD=y
-CONFIG_PSTORE=m
-CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_LZO_COMPRESS=y
-CONFIG_PSTORE_LZ4_COMPRESS=y
-CONFIG_PSTORE_LZ4HC_COMPRESS=y
-CONFIG_PSTORE_842_COMPRESS=y
-CONFIG_PSTORE_ZSTD_COMPRESS=y
-CONFIG_PSTORE_COMPRESS=y
-# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
-CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="zstd"
-# CONFIG_PSTORE_CONSOLE is not set
-CONFIG_PSTORE_PMSG=y
-# CONFIG_PSTORE_FTRACE is not set
-CONFIG_PSTORE_RAM=m
-CONFIG_PSTORE_ZONE=m
-CONFIG_PSTORE_BLK=m
-CONFIG_PSTORE_BLK_BLKDEV=""
-CONFIG_PSTORE_BLK_KMSG_SIZE=64
-CONFIG_PSTORE_BLK_MAX_REASON=2
-CONFIG_PSTORE_BLK_PMSG_SIZE=64
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-# CONFIG_UFS_FS_WRITE is not set
-# CONFIG_UFS_DEBUG is not set
-CONFIG_EROFS_FS=m
-# CONFIG_EROFS_FS_DEBUG is not set
-CONFIG_EROFS_FS_XATTR=y
-CONFIG_EROFS_FS_POSIX_ACL=y
-# CONFIG_EROFS_FS_SECURITY is not set
-# CONFIG_EROFS_FS_ZIP is not set
-CONFIG_VBOXSF_FS=m
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V2=m
-CONFIG_NFS_V3=m
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=m
-CONFIG_NFS_SWAP=y
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_V4_2=y
-CONFIG_PNFS_FILE_LAYOUT=m
-CONFIG_PNFS_BLOCK=m
-CONFIG_PNFS_FLEXFILE_LAYOUT=m
-CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
-CONFIG_NFS_V4_1_MIGRATION=y
-CONFIG_NFS_FSCACHE=y
-# CONFIG_NFS_USE_LEGACY_DNS is not set
-CONFIG_NFS_USE_KERNEL_DNS=y
-CONFIG_NFS_DISABLE_UDP_SUPPORT=y
-CONFIG_NFS_V4_2_READ_PLUS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V2_ACL=y
-CONFIG_NFSD_V3=y
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_PNFS=y
-CONFIG_NFSD_BLOCKLAYOUT=y
-CONFIG_NFSD_SCSILAYOUT=y
-CONFIG_NFSD_FLEXFILELAYOUT=y
-CONFIG_NFSD_V4_2_INTER_SSC=y
-CONFIG_GRACE_PERIOD=m
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_ACL_SUPPORT=m
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_SUNRPC_BACKCHANNEL=y
-CONFIG_SUNRPC_SWAP=y
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
-# CONFIG_SUNRPC_DEBUG is not set
-CONFIG_SUNRPC_XPRT_RDMA=m
-CONFIG_CEPH_FS=m
-CONFIG_CEPH_FSCACHE=y
-CONFIG_CEPH_FS_POSIX_ACL=y
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS2=y
-CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
-CONFIG_CIFS_WEAK_PW_HASH=y
-CONFIG_CIFS_UPCALL=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-# CONFIG_CIFS_DEBUG is not set
-CONFIG_CIFS_DFS_UPCALL=y
-CONFIG_CIFS_SWN_UPCALL=y
-# CONFIG_CIFS_SMB_DIRECT is not set
-CONFIG_CIFS_FSCACHE=y
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-# CONFIG_AFS_DEBUG is not set
-CONFIG_AFS_FSCACHE=y
-# CONFIG_AFS_DEBUG_CURSOR is not set
-CONFIG_9P_FS=m
-CONFIG_9P_FSCACHE=y
-CONFIG_9P_FS_POSIX_ACL=y
-CONFIG_9P_FS_SECURITY=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_MAC_ROMAN=m
-CONFIG_NLS_MAC_CELTIC=m
-CONFIG_NLS_MAC_CENTEURO=m
-CONFIG_NLS_MAC_CROATIAN=m
-CONFIG_NLS_MAC_CYRILLIC=m
-CONFIG_NLS_MAC_GAELIC=m
-CONFIG_NLS_MAC_GREEK=m
-CONFIG_NLS_MAC_ICELAND=m
-CONFIG_NLS_MAC_INUIT=m
-CONFIG_NLS_MAC_ROMANIAN=m
-CONFIG_NLS_MAC_TURKISH=m
-CONFIG_NLS_UTF8=m
-CONFIG_DLM=m
-# CONFIG_DLM_DEPRECATED_API is not set
-# CONFIG_DLM_DEBUG is not set
-CONFIG_UNICODE=y
-CONFIG_UNICODE_NORMALIZATION_SELFTEST=m
-CONFIG_IO_WQ=y
-# end of File systems
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-# CONFIG_KEYS_REQUEST_CACHE is not set
-CONFIG_PERSISTENT_KEYRINGS=y
-CONFIG_TRUSTED_KEYS=m
-CONFIG_ENCRYPTED_KEYS=m
-CONFIG_USER_DECRYPTED_DATA=y
-# CONFIG_KEY_DH_OPERATIONS is not set
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-# CONFIG_SECURITY is not set
-CONFIG_SECURITYFS=y
-CONFIG_PAGE_TABLE_ISOLATION=y
-CONFIG_INTEL_TXT=y
-CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
-CONFIG_HARDENED_USERCOPY=y
-CONFIG_HARDENED_USERCOPY_FALLBACK=y
-# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
-CONFIG_FORTIFY_SOURCE=y
-# CONFIG_STATIC_USERMODEHELPER is not set
-# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_LSM="yama,loadpin,safesetid,integrity,bpf"
-
-#
-# Kernel hardening options
-#
-
-#
-# Memory initialization
-#
-CONFIG_INIT_STACK_NONE=y
-# CONFIG_INIT_STACK_ALL_PATTERN is not set
-# CONFIG_INIT_STACK_ALL_ZERO is not set
-# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
-# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
-# end of Memory initialization
-# end of Kernel hardening options
-# end of Security options
-
-CONFIG_XOR_BLOCKS=m
-CONFIG_ASYNC_CORE=m
-CONFIG_ASYNC_MEMCPY=m
-CONFIG_ASYNC_XOR=m
-CONFIG_ASYNC_PQ=m
-CONFIG_ASYNC_RAID6_RECOV=m
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=m
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_SKCIPHER=y
-CONFIG_CRYPTO_SKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG=m
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=m
-CONFIG_CRYPTO_AKCIPHER2=y
-CONFIG_CRYPTO_AKCIPHER=y
-CONFIG_CRYPTO_KPP2=y
-CONFIG_CRYPTO_KPP=m
-CONFIG_CRYPTO_ACOMP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_USER=m
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_PCRYPT=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_SIMD=m
-CONFIG_CRYPTO_ENGINE=m
-
-#
-# Public-key cryptography
-#
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_DH=m
-CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
-CONFIG_CRYPTO_ECC=m
-CONFIG_CRYPTO_ECDH=m
-CONFIG_CRYPTO_ECDSA=m
-CONFIG_CRYPTO_ECRDSA=m
-CONFIG_CRYPTO_SM2=m
-CONFIG_CRYPTO_CURVE25519=m
-
-#
-# Authenticated Encryption with Associated Data
-#
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_GCM=m
-CONFIG_CRYPTO_CHACHA20POLY1305=m
-CONFIG_CRYPTO_AEGIS128=m
-CONFIG_CRYPTO_SEQIV=m
-CONFIG_CRYPTO_ECHAINIV=m
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CFB=m
-CONFIG_CRYPTO_CTR=m
-CONFIG_CRYPTO_CTS=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_OFB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_KEYWRAP=m
-CONFIG_CRYPTO_NHPOLY1305=m
-CONFIG_CRYPTO_ADIANTUM=m
-CONFIG_CRYPTO_HCTR2=m
-CONFIG_CRYPTO_ARIA=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
-CONFIG_CRYPTO_DEV_QAT_C3XXX=m
-CONFIG_CRYPTO_DEV_QAT_C62X=m
-CONFIG_CRYPTO_DEV_QAT_4XXX=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
-CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
-CONFIG_CRYPTO_DEV_QAT_C62XVF=m
-CONFIG_CRYPTO_ESSIV=m
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_CMAC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CRC32C_INTEL=m
-CONFIG_CRYPTO_CRC32=m
-CONFIG_CRYPTO_CRC32_PCLMUL=m
-CONFIG_CRYPTO_XXHASH=m
-CONFIG_CRYPTO_BLAKE2B=m
-CONFIG_CRYPTO_BLAKE2S=m
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_GHASH=m
-CONFIG_CRYPTO_POLYVAL_CLMUL_NI=m
-CONFIG_CRYPTO_POLY1305=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_RMD128=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_RMD256=m
-CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SHA3=m
-CONFIG_CRYPTO_SM3=m
-CONFIG_CRYPTO_SM3_AVX_X86_64=m
-# CONFIG_CRYPTO_STREEBOG is not set
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_AES_TI=m
-CONFIG_CRYPTO_AES_NI_INTEL=m
-CONFIG_CRYPTO_ANUBIS=m
-# CONFIG_CRYPTO_ARC4 is not set
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_BLOWFISH_COMMON=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST_COMMON=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SALSA20=m
-CONFIG_CRYPTO_CHACHA20=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-# CONFIG_CRYPTO_SERPENT_SSE2_586 is not set
-CONFIG_CRYPTO_SM4=m
-CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64=m
-CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-# CONFIG_CRYPTO_TWOFISH_586 is not set
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_842=y
-CONFIG_CRYPTO_LZ4=y
-CONFIG_CRYPTO_LZ4HC=y
-CONFIG_CRYPTO_ZSTD=y
-
-#
-# Random Number Generation
-#
-CONFIG_CRYPTO_ANSI_CPRNG=m
-CONFIG_CRYPTO_DRBG_MENU=m
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_HASH=y
-CONFIG_CRYPTO_DRBG_CTR=y
-CONFIG_CRYPTO_DRBG=m
-CONFIG_CRYPTO_JITTERENTROPY=m
-CONFIG_CRYPTO_USER_API=m
-CONFIG_CRYPTO_USER_API_HASH=y
-CONFIG_CRYPTO_USER_API_SKCIPHER=m
-CONFIG_CRYPTO_USER_API_RNG=m
-CONFIG_CRYPTO_USER_API_RNG_CAVP=y
-CONFIG_CRYPTO_USER_API_AEAD=m
-CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
-# CONFIG_CRYPTO_STATS is not set
-CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=m
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
-CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_DEV_PADLOCK=m
-CONFIG_CRYPTO_DEV_PADLOCK_AES=m
-CONFIG_CRYPTO_DEV_PADLOCK_SHA=m
-# CONFIG_CRYPTO_DEV_GEODE is not set
-CONFIG_CRYPTO_DEV_ATMEL_I2C=m
-CONFIG_CRYPTO_DEV_ATMEL_ECC=m
-CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
-CONFIG_CRYPTO_DEV_CCP=y
-CONFIG_CRYPTO_DEV_CCP_DD=m
-CONFIG_CRYPTO_DEV_SP_CCP=y
-CONFIG_CRYPTO_DEV_CCP_CRYPTO=m
-# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set
-CONFIG_CRYPTO_DEV_QAT=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
-CONFIG_CRYPTO_DEV_QAT_C3XXX=m
-CONFIG_CRYPTO_DEV_QAT_C62X=m
-CONFIG_CRYPTO_DEV_QAT_4XXX=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
-CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
-CONFIG_CRYPTO_DEV_QAT_C62XVF=m
-CONFIG_CRYPTO_DEV_CHELSIO=m
-CONFIG_CRYPTO_DEV_VIRTIO=m
-CONFIG_CRYPTO_DEV_SAFEXCEL=m
-CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
-CONFIG_CRYPTO_DEV_ASPEED=m
-# CONFIG_CRYPTO_DEV_ASPEED_DEBUG is not set
-CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH=y
-CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO=y
-# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set
-CONFIG_ASYMMETRIC_KEY_TYPE=y
-CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
-CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE=m
-CONFIG_X509_CERTIFICATE_PARSER=y
-CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
-CONFIG_TPM_KEY_PARSER=m
-CONFIG_PKCS7_MESSAGE_PARSER=y
-CONFIG_PKCS7_TEST_KEY=m
-CONFIG_SIGNED_PE_FILE_VERIFICATION=y
-
-#
-# Certificates for signature checking
-#
-CONFIG_SYSTEM_TRUSTED_KEYRING=y
-CONFIG_SYSTEM_TRUSTED_KEYS=""
-# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
-CONFIG_SECONDARY_TRUSTED_KEYRING=y
-CONFIG_SYSTEM_BLACKLIST_KEYRING=y
-# CONFIG_SYSTEM_REVOCATION_LIST is not set
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLIP=m
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_SLIP_SMART=y
+CONFIG_SM_FTL=m
+CONFIG_SMPRO_ERRMON=m
+CONFIG_SMPRO_MISC=m
+CONFIG_SMSC37B787_WDT=m
+CONFIG_SMSC_PHY=m
+CONFIG_SMSC_SCH311X_WDT=m
+CONFIG_SMS_SDIO_DRV=m
+CONFIG_SMS_SIANO_MDTV=m
+CONFIG_SMS_SIANO_RC=y
+CONFIG_SMS_USB_DRV=m
+CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
+CONFIG_SND_AC97_POWER_SAVE=y
+CONFIG_SND_AD1889=m
+CONFIG_SND_ALI5451=m
+CONFIG_SND_ALOOP=m
+CONFIG_SND_ALS300=m
+CONFIG_SND_ALS4000=m
+CONFIG_SND_AMD_ACP_CONFIG=m
+CONFIG_SND_AMD_ASOC_ACP63=m
+CONFIG_SND_AMD_ASOC_ACP70=m
+CONFIG_SND_AMD_ASOC_REMBRANDT=m
+CONFIG_SND_AMD_ASOC_RENOIR=m
+CONFIG_SND_ASIHPI=m
+CONFIG_SND_ATIIXP=m
+CONFIG_SND_ATIIXP_MODEM=m
+CONFIG_SND_ATMEL_SOC=m
+CONFIG_SND_AU8810=m
+CONFIG_SND_AU8820=m
+CONFIG_SND_AU8830=m
+CONFIG_SND_AW2=m
+CONFIG_SND_AZT3328=m
+CONFIG_SND_BCD2000=m
+CONFIG_SND_BCM63XX_I2S_WHISTLER=m
+CONFIG_SND_BEBOB=m
+CONFIG_SND_BT87X=m
+CONFIG_SND_BT87X_OVERCLOCK=y
+CONFIG_SND_CA0106=m
+CONFIG_SND_CMIPCI=m
+CONFIG_SND_COMPRESS_OFFLOAD=m
+CONFIG_SND_CS4281=m
+CONFIG_SND_CS46XX=m
+CONFIG_SND_CS46XX_NEW_DSP=y
+CONFIG_SND_CTL_FAST_LOOKUP=y
+CONFIG_SND_CTL_INPUT_VALIDATION=y
+CONFIG_SND_CTL_LED=m
+CONFIG_SND_CTXFI=m
+CONFIG_SND_DARLA20=m
+CONFIG_SND_DARLA24=m
+CONFIG_SND_DESIGNWARE_I2S=m
+CONFIG_SND_DESIGNWARE_PCM=y
+CONFIG_SND_DICE=m
+CONFIG_SND_DMAENGINE_PCM=m
+CONFIG_SND_DMA_SGBUF=y
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_DUMMY=m
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_ECHO3G=m
+CONFIG_SND_EMU10K1=m
+CONFIG_SND_EMU10K1_SEQ=m
+CONFIG_SND_EMU10K1X=m
+CONFIG_SND_ENS1370=m
+CONFIG_SND_ENS1371=m
+CONFIG_SND_ES1938=m
+CONFIG_SND_ES1968_INPUT=y
+CONFIG_SND_ES1968=m
+CONFIG_SND_ES1968_RADIO=y
+CONFIG_SND_FIREFACE=m
+CONFIG_SND_FIREWIRE_DIGI00X=m
+CONFIG_SND_FIREWIRE_LIB=m
+CONFIG_SND_FIREWIRE_MOTU=m
+CONFIG_SND_FIREWIRE_TASCAM=m
+CONFIG_SND_FIREWIRE=y
+CONFIG_SND_FIREWORKS=m
+CONFIG_SND_FM801=m
+CONFIG_SND_FM801_TEA575X_BOOL=y
+CONFIG_SND_GINA20=m
+CONFIG_SND_GINA24=m
+CONFIG_SND_HDA_CODEC_ALC260=m
+CONFIG_SND_HDA_CODEC_ALC262=m
+CONFIG_SND_HDA_CODEC_ALC268=m
+CONFIG_SND_HDA_CODEC_ALC269=m
+CONFIG_SND_HDA_CODEC_ALC662=m
+CONFIG_SND_HDA_CODEC_ALC680=m
+CONFIG_SND_HDA_CODEC_ALC861=m
+CONFIG_SND_HDA_CODEC_ALC861VD=m
+CONFIG_SND_HDA_CODEC_ALC880=m
+CONFIG_SND_HDA_CODEC_ALC882=m
+CONFIG_SND_HDA_CODEC_ANALOG=m
+CONFIG_SND_HDA_CODEC_CA0110=m
+CONFIG_SND_HDA_CODEC_CA0132_DSP=y
+CONFIG_SND_HDA_CODEC_CA0132=m
+CONFIG_SND_HDA_CODEC_CIRRUS=m
+CONFIG_SND_HDA_CODEC_CM9825=m
+CONFIG_SND_HDA_CODEC_CMEDIA=m
+CONFIG_SND_HDA_CODEC_CONEXANT=m
+CONFIG_SND_HDA_CODEC_CS420X=m
+CONFIG_SND_HDA_CODEC_CS421X=m
+CONFIG_SND_HDA_CODEC_CS8409=m
+CONFIG_SND_HDA_CODEC_HDMI_ATI=m
+CONFIG_SND_HDA_CODEC_HDMI_INTEL=m
+CONFIG_SND_HDA_CODEC_HDMI=m
+CONFIG_SND_HDA_CODEC_HDMI_NVIDIA=m
+CONFIG_SND_HDA_CODEC_HDMI_NVIDIA_MCP=m
+CONFIG_SND_HDA_CODEC_HDMI_TEGRA=m
+CONFIG_SND_HDA_CODEC_REALTEK=m
+CONFIG_SND_HDA_CODEC_SENARYTECH=m
+CONFIG_SND_HDA_CODEC_SI3054=m
+CONFIG_SND_HDA_CODEC_SIGMATEL=m
+CONFIG_SND_HDA_CODEC_VIA=m
+CONFIG_SND_HDA_COMPONENT=y
+CONFIG_SND_HDA_CORE=m
+CONFIG_SND_HDA_CS_DSP_CONTROLS=m
+CONFIG_SND_HDA_DSP_LOADER=y
+CONFIG_SND_HDA_EXT_CORE=m
+CONFIG_SND_HDA_GENERIC_LEDS=y
+CONFIG_SND_HDA_GENERIC=m
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_I915=y
+CONFIG_SND_HDA_INPUT_BEEP_MODE=1
+CONFIG_SND_HDA_INPUT_BEEP=y
+CONFIG_SND_HDA_INTEL=m
+CONFIG_SND_HDA=m
+CONFIG_SND_HDA_PATCH_LOADER=y
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
+CONFIG_SND_HDA_PREALLOC_SIZE=0
+CONFIG_SND_HDA_RECONFIG=y
+CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m
+CONFIG_SND_HDA_SCODEC_CS35L41=m
+CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m
+CONFIG_SND_HDA_SCODEC_CS35L56_I2C=m
+CONFIG_SND_HDA_SCODEC_CS35L56_SPI=m
+CONFIG_SND_HDA_SCODEC_TAS2781_I2C=m
+CONFIG_SND_HDA_SCODEC_TAS2781_SPI=m
+CONFIG_SND_HDSP=m
+CONFIG_SND_HDSPM=m
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_I2S_HI6210_I2S=m
+CONFIG_SND_ICE1712=m
+CONFIG_SND_ICE1724=m
+CONFIG_SND_INDIGODJ=m
+CONFIG_SND_INDIGODJX=m
+CONFIG_SND_INDIGOIO=m
+CONFIG_SND_INDIGOIOX=m
+CONFIG_SND_INDIGO=m
+CONFIG_SND_INTEL8X0=m
+CONFIG_SND_INTEL8X0M=m
+CONFIG_SND_INTEL_BYT_PREFER_SOF=y
+CONFIG_SND_INTEL_DSP_CONFIG=m
+CONFIG_SND_INTEL_NHLT=y
+CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m
+CONFIG_SND_ISA=y
+CONFIG_SND_ISIGHT=m
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_JACK=y
+CONFIG_SND_KORG1212=m
+CONFIG_SND_LAYLA20=m
+CONFIG_SND_LAYLA24=m
+CONFIG_SND_LOLA=m
+CONFIG_SND_LX6464ES=m
+CONFIG_SND=m
+CONFIG_SND_MAESTRO3_INPUT=y
+CONFIG_SND_MAESTRO3=m
+CONFIG_SND_MAX_CARDS=32
+CONFIG_SND_MIA=m
+CONFIG_SND_MIXART=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_MONA=m
+CONFIG_SND_MPU401=m
+CONFIG_SND_MPU401_UART=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_MTS64=m
+CONFIG_SND_NM256=m
+CONFIG_SND_OPL3_LIB=m
+CONFIG_SND_OPL3_LIB_SEQ=m
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_OXFW=m
+CONFIG_SND_OXYGEN_LIB=m
+CONFIG_SND_OXYGEN=m
+CONFIG_SND_PCI=y
+CONFIG_SND_PCMCIA=y
+CONFIG_SND_PCM_ELD=y
+CONFIG_SND_PCM_IEC958=y
+CONFIG_SND_PCM=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_PCMTEST=m
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_PCXHR=m
+CONFIG_SND_PDAUDIOCF=m
+CONFIG_SND_PORTMAN2X4=m
+CONFIG_SND_PROC_FS=y
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_RIPTIDE=m
+CONFIG_SND_RME32=m
+CONFIG_SND_RME9652=m
+CONFIG_SND_RME96=m
+CONFIG_SND_SB_COMMON=m
+CONFIG_SND_SEQ_DEVICE=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+CONFIG_SND_SEQ_MIDI_EMUL=m
+CONFIG_SND_SEQ_MIDI_EVENT=m
+CONFIG_SND_SEQ_MIDI=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQUENCER_OSS=m
+CONFIG_SND_SEQ_UMP_CLIENT=m
+CONFIG_SND_SEQ_UMP=y
+CONFIG_SND_SEQ_VIRMIDI=m
+CONFIG_SND_SERIAL_U16550=m
+CONFIG_SND_SIMPLE_CARD=m
+CONFIG_SND_SIMPLE_CARD_UTILS=m
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AC97_CODEC=m
+CONFIG_SND_SOC_ACPI_INTEL_MATCH=m
+CONFIG_SND_SOC_ACPI=m
+CONFIG_SND_SOC_ADAU1372_I2C=m
+CONFIG_SND_SOC_ADAU1372=m
+CONFIG_SND_SOC_ADAU1372_SPI=m
+CONFIG_SND_SOC_ADAU1701=m
+CONFIG_SND_SOC_ADAU1761_I2C=m
+CONFIG_SND_SOC_ADAU1761=m
+CONFIG_SND_SOC_ADAU1761_SPI=m
+CONFIG_SND_SOC_ADAU17X1=m
+CONFIG_SND_SOC_ADAU7002=m
+CONFIG_SND_SOC_ADAU7118_HW=m
+CONFIG_SND_SOC_ADAU7118_I2C=m
+CONFIG_SND_SOC_ADAU7118=m
+CONFIG_SND_SOC_ADAU_UTILS=m
+CONFIG_SND_SOC_ADI_AXI_I2S=m
+CONFIG_SND_SOC_ADI_AXI_SPDIF=m
+CONFIG_SND_SOC_ADI=m
+CONFIG_SND_SOC_AK4104=m
+CONFIG_SND_SOC_AK4118=m
+CONFIG_SND_SOC_AK4375=m
+CONFIG_SND_SOC_AK4458=m
+CONFIG_SND_SOC_AK4554=m
+CONFIG_SND_SOC_AK4613=m
+CONFIG_SND_SOC_AK4619=m
+CONFIG_SND_SOC_AK4642=m
+CONFIG_SND_SOC_AK5386=m
+CONFIG_SND_SOC_AK5558=m
+CONFIG_SND_SOC_ALC5623=m
+CONFIG_SND_SOC_AMD_ACP3x=m
+CONFIG_SND_SOC_AMD_ACP5x=m
+CONFIG_SND_SOC_AMD_ACP63_TOPLEVEL=m
+CONFIG_SND_SOC_AMD_ACP6x=m
+CONFIG_SND_SOC_AMD_ACP_COMMON=m
+CONFIG_SND_SOC_AMD_ACP_I2S=m
+CONFIG_SND_SOC_AMD_ACP=m
+CONFIG_SND_SOC_AMD_ACP_PCI=m
+CONFIG_SND_SOC_AMD_ACP_PCM=m
+CONFIG_SND_SOC_AMD_ACP_PDM=m
+CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m
+CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
+CONFIG_SND_SOC_AMD_LEGACY_MACH=m
+CONFIG_SND_SOC_AMD_MACH_COMMON=m
+CONFIG_SND_SOC_AMD_PS=m
+CONFIG_SND_SOC_AMD_PS_MACH=m
+CONFIG_SND_SOC_AMD_RENOIR=m
+CONFIG_SND_SOC_AMD_RENOIR_MACH=m
+CONFIG_SND_SOC_AMD_RPL_ACP6x=m
+CONFIG_SND_SOC_AMD_RV_RT5682_MACH=m
+CONFIG_SND_SOC_AMD_SOF_MACH=m
+CONFIG_SND_SOC_AMD_SOF_SDW_MACH=m
+CONFIG_SND_SOC_AMD_SOUNDWIRE=m
+CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m
+CONFIG_SND_SOC_AMD_VANGOGH_MACH=m
+CONFIG_SND_SOC_AMD_YC_MACH=m
+CONFIG_SND_SOC_ARIZONA=m
+CONFIG_SND_SOC_AUDIO_IIO_AUX=m
+CONFIG_SND_SOC_AW8738=m
+CONFIG_SND_SOC_AW87390=m
+CONFIG_SND_SOC_AW88166=m
+CONFIG_SND_SOC_AW88261=m
+CONFIG_SND_SOC_AW88395_LIB=m
+CONFIG_SND_SOC_AW88395=m
+CONFIG_SND_SOC_AW88399=m
+CONFIG_SND_SOC_BD28623=m
+CONFIG_SND_SOC_CHV3_CODEC=m
+CONFIG_SND_SOC_CHV3_I2S=m
+CONFIG_SND_SOC_COMPRESS=y
+CONFIG_SND_SOC_CROS_EC_CODEC=m
+CONFIG_SND_SOC_CS35L32=m
+CONFIG_SND_SOC_CS35L33=m
+CONFIG_SND_SOC_CS35L34=m
+CONFIG_SND_SOC_CS35L35=m
+CONFIG_SND_SOC_CS35L36=m
+CONFIG_SND_SOC_CS35L41_I2C=m
+CONFIG_SND_SOC_CS35L41_LIB=m
+CONFIG_SND_SOC_CS35L41=m
+CONFIG_SND_SOC_CS35L41_SPI=m
+CONFIG_SND_SOC_CS35L45_I2C=m
+CONFIG_SND_SOC_CS35L45=m
+CONFIG_SND_SOC_CS35L45_SPI=m
+CONFIG_SND_SOC_CS35L56_I2C=m
+CONFIG_SND_SOC_CS35L56=m
+CONFIG_SND_SOC_CS35L56_SDW=m
+CONFIG_SND_SOC_CS35L56_SHARED=m
+CONFIG_SND_SOC_CS35L56_SPI=m
+CONFIG_SND_SOC_CS40L50=m
+CONFIG_SND_SOC_CS4234=m
+CONFIG_SND_SOC_CS4265=m
+CONFIG_SND_SOC_CS4270=m
+CONFIG_SND_SOC_CS4271_I2C=m
+CONFIG_SND_SOC_CS4271=m
+CONFIG_SND_SOC_CS4271_SPI=m
+CONFIG_SND_SOC_CS42L42_CORE=m
+CONFIG_SND_SOC_CS42L42=m
+CONFIG_SND_SOC_CS42L42_SDW=m
+CONFIG_SND_SOC_CS42L43=m
+CONFIG_SND_SOC_CS42L43_SDW=m
+CONFIG_SND_SOC_CS42L51_I2C=m
+CONFIG_SND_SOC_CS42L51=m
+CONFIG_SND_SOC_CS42L52=m
+CONFIG_SND_SOC_CS42L56=m
+CONFIG_SND_SOC_CS42L73=m
+CONFIG_SND_SOC_CS42L83=m
+CONFIG_SND_SOC_CS42XX8_I2C=m
+CONFIG_SND_SOC_CS42XX8=m
+CONFIG_SND_SOC_CS43130=m
+CONFIG_SND_SOC_CS4341=m
+CONFIG_SND_SOC_CS4349=m
+CONFIG_SND_SOC_CS530X_I2C=m
+CONFIG_SND_SOC_CS53L30=m
+CONFIG_SND_SOC_CX2072X=m
+CONFIG_SND_SOC_DA7213=m
+CONFIG_SND_SOC_DA7219=m
+CONFIG_SND_SOC_DMIC=m
+CONFIG_SND_SOC_ES7134=m
+CONFIG_SND_SOC_ES7241=m
+CONFIG_SND_SOC_ES8311=m
+CONFIG_SND_SOC_ES8316=m
+CONFIG_SND_SOC_ES8326=m
+CONFIG_SND_SOC_ES8328_I2C=m
+CONFIG_SND_SOC_ES8328=m
+CONFIG_SND_SOC_ES8328_SPI=m
+CONFIG_SND_SOC_FRAMER=m
+CONFIG_SND_SOC_FS210X=m
+CONFIG_SND_SOC_FSL_ASRC=m
+CONFIG_SND_SOC_FSL_AUDMIX=m
+CONFIG_SND_SOC_FSL_EASRC=m
+CONFIG_SND_SOC_FSL_ESAI=m
+CONFIG_SND_SOC_FSL_MICFIL=m
+CONFIG_SND_SOC_FSL_MQS=m
+CONFIG_SND_SOC_FSL_RPMSG=m
+CONFIG_SND_SOC_FSL_SAI=m
+CONFIG_SND_SOC_FSL_SPDIF=m
+CONFIG_SND_SOC_FSL_SSI=m
+CONFIG_SND_SOC_FSL_UTILS=m
+CONFIG_SND_SOC_FSL_XCVR=m
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_GTM601=m
+CONFIG_SND_SOC_HDAC_HDA=m
+CONFIG_SND_SOC_HDAC_HDMI=m
+CONFIG_SND_SOC_HDA=m
+CONFIG_SND_SOC_HDMI_CODEC=m
+CONFIG_SND_SOC_I2C_AND_SPI=m
+CONFIG_SND_SOC_ICS43432=m
+CONFIG_SND_SOC_IDT821034=m
+CONFIG_SND_SOC_IMG_I2S_IN=m
+CONFIG_SND_SOC_IMG_I2S_OUT=m
+CONFIG_SND_SOC_IMG_PARALLEL_OUT=m
+CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m
+CONFIG_SND_SOC_IMG_SPDIF_IN=m
+CONFIG_SND_SOC_IMG_SPDIF_OUT=m
+CONFIG_SND_SOC_IMG=y
+CONFIG_SND_SOC_IMX_AUDMUX=m
+CONFIG_SND_SOC_INNO_RK3036=m
+CONFIG_SND_SOC_INTEL_APL=m
+CONFIG_SND_SOC_INTEL_AVS=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_ES8336=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98927=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_PCM3168A=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_PROBE=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_RT274=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_RT286=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_RT298=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_RT5514=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_RT5640=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_RT5663=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567=m
+CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH=m
+CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=m
+CONFIG_SND_SOC_INTEL_BROADWELL_MACH=m
+CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_COMMON=m
+CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH=m
+CONFIG_SND_SOC_INTEL_BXT_RT298_MACH=m
+CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH=m
+CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH=m
+CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH=m
+CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH=m
+CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=m
+CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH=m
+CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH=m
+CONFIG_SND_SOC_INTEL_CATPT=m
+CONFIG_SND_SOC_INTEL_CFL=m
+CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH=m
+CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH=m
+CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH=m
+CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=m
+CONFIG_SND_SOC_INTEL_CML_H=m
+CONFIG_SND_SOC_INTEL_CML_LP_DA7219_MAX98357A_MACH=m
+CONFIG_SND_SOC_INTEL_CML_LP=m
+CONFIG_SND_SOC_INTEL_CNL=m
+CONFIG_SND_SOC_INTEL_DA7219_MAX98357A_GENERIC=m
+CONFIG_SND_SOC_INTEL_EHL_RT5660_MACH=m
+CONFIG_SND_SOC_INTEL_GLK_DA7219_MAX98357A_MACH=m
+CONFIG_SND_SOC_INTEL_GLK=m
+CONFIG_SND_SOC_INTEL_GLK_RT5682_MAX98357A_MACH=m
+CONFIG_SND_SOC_INTEL_HASWELL_MACH=m
+CONFIG_SND_SOC_INTEL_HDA_DSP_COMMON=m
+CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98357A_MACH=m
+CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98927_MACH=m
+CONFIG_SND_SOC_INTEL_KBL=m
+CONFIG_SND_SOC_INTEL_KBL_RT5660_MACH=m
+CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH=m
+CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH=m
+CONFIG_SND_SOC_INTEL_MACH=y
+CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH=m
+CONFIG_SND_SOC_INTEL_SKL=m
+CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH=m
+CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH=m
+CONFIG_SND_SOC_INTEL_SKL_RT286_MACH=m
+CONFIG_SND_SOC_INTEL_SKYLAKE_COMMON=m
+CONFIG_SND_SOC_INTEL_SKYLAKE_FAMILY=m
+CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC=y
+CONFIG_SND_SOC_INTEL_SKYLAKE=m
+CONFIG_SND_SOC_INTEL_SKYLAKE_SSP_CLK=m
+CONFIG_SND_SOC_INTEL_SOF_CIRRUS_COMMON=m
+CONFIG_SND_SOC_INTEL_SOF_CML_RT1011_RT5682_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_CS42L42_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_DA7219_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_DA7219_MAX98373_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_ES8336_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_MAXIM_COMMON=m
+CONFIG_SND_SOC_INTEL_SOF_NAU8825_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_REALTEK_COMMON=m
+CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_SSP_AMP_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH=m
+CONFIG_SND_SOC_INTEL_SST=m
+CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y
+CONFIG_SND_SOC_LPASS_MACRO_COMMON=m
+CONFIG_SND_SOC_LPASS_RX_MACRO=m
+CONFIG_SND_SOC_LPASS_TX_MACRO=m
+CONFIG_SND_SOC_LPASS_VA_MACRO=m
+CONFIG_SND_SOC_LPASS_WSA_MACRO=m
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_MAX9759=m
+CONFIG_SND_SOC_MAX98088=m
+CONFIG_SND_SOC_MAX98090=m
+CONFIG_SND_SOC_MAX98357A=m
+CONFIG_SND_SOC_MAX98363=m
+CONFIG_SND_SOC_MAX98373_I2C=m
+CONFIG_SND_SOC_MAX98373=m
+CONFIG_SND_SOC_MAX98373_SDW=m
+CONFIG_SND_SOC_MAX98388=m
+CONFIG_SND_SOC_MAX98390=m
+CONFIG_SND_SOC_MAX98396=m
+CONFIG_SND_SOC_MAX98504=m
+CONFIG_SND_SOC_MAX98520=m
+CONFIG_SND_SOC_MAX9860=m
+CONFIG_SND_SOC_MAX9867=m
+CONFIG_SND_SOC_MAX98927=m
+CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
+CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
+CONFIG_SND_SOC_MT6351=m
+CONFIG_SND_SOC_MT6357=m
+CONFIG_SND_SOC_MT6358=m
+CONFIG_SND_SOC_MT6660=m
+CONFIG_SND_SOC_MTK_BTCVSD=m
+CONFIG_SND_SOC_NAU8315=m
+CONFIG_SND_SOC_NAU8540=m
+CONFIG_SND_SOC_NAU8810=m
+CONFIG_SND_SOC_NAU8821=m
+CONFIG_SND_SOC_NAU8822=m
+CONFIG_SND_SOC_NAU8824=m
+CONFIG_SND_SOC_NAU8825=m
+CONFIG_SND_SOC_PCM1681=m
+CONFIG_SND_SOC_PCM1754=m
+CONFIG_SND_SOC_PCM1789_I2C=m
+CONFIG_SND_SOC_PCM1789=m
+CONFIG_SND_SOC_PCM179X_I2C=m
+CONFIG_SND_SOC_PCM179X=m
+CONFIG_SND_SOC_PCM179X_SPI=m
+CONFIG_SND_SOC_PCM186X_I2C=m
+CONFIG_SND_SOC_PCM186X=m
+CONFIG_SND_SOC_PCM186X_SPI=m
+CONFIG_SND_SOC_PCM3060_I2C=m
+CONFIG_SND_SOC_PCM3060=m
+CONFIG_SND_SOC_PCM3060_SPI=m
+CONFIG_SND_SOC_PCM3168A_I2C=m
+CONFIG_SND_SOC_PCM3168A=m
+CONFIG_SND_SOC_PCM3168A_SPI=m
+CONFIG_SND_SOC_PCM5102A=m
+CONFIG_SND_SOC_PCM512x_I2C=m
+CONFIG_SND_SOC_PCM512x=m
+CONFIG_SND_SOC_PCM512x_SPI=m
+CONFIG_SND_SOC_PCM6240=m
+CONFIG_SND_SOC_PEB2466=m
+CONFIG_SND_SOC_PM4125_SDW=m
+CONFIG_SND_SOC_RK3328=m
+CONFIG_SND_SOC_RL6231=m
+CONFIG_SND_SOC_RL6347A=m
+CONFIG_SND_SOC_RT1011=m
+CONFIG_SND_SOC_RT1015=m
+CONFIG_SND_SOC_RT1015P=m
+CONFIG_SND_SOC_RT1017_SDCA_SDW=m
+CONFIG_SND_SOC_RT1019=m
+CONFIG_SND_SOC_RT1308=m
+CONFIG_SND_SOC_RT1308_SDW=m
+CONFIG_SND_SOC_RT1316_SDW=m
+CONFIG_SND_SOC_RT1318_SDW=m
+CONFIG_SND_SOC_RT1320_SDW=m
+CONFIG_SND_SOC_RT274=m
+CONFIG_SND_SOC_RT286=m
+CONFIG_SND_SOC_RT298=m
+CONFIG_SND_SOC_RT5514=m
+CONFIG_SND_SOC_RT5514_SPI=m
+CONFIG_SND_SOC_RT5616=m
+CONFIG_SND_SOC_RT5631=m
+CONFIG_SND_SOC_RT5640=m
+CONFIG_SND_SOC_RT5645=m
+CONFIG_SND_SOC_RT5651=m
+CONFIG_SND_SOC_RT5659=m
+CONFIG_SND_SOC_RT5660=m
+CONFIG_SND_SOC_RT5663=m
+CONFIG_SND_SOC_RT5670=m
+CONFIG_SND_SOC_RT5677=m
+CONFIG_SND_SOC_RT5677_SPI=m
+CONFIG_SND_SOC_RT5682_I2C=m
+CONFIG_SND_SOC_RT5682=m
+CONFIG_SND_SOC_RT5682_SDW=m
+CONFIG_SND_SOC_RT5682S=m
+CONFIG_SND_SOC_RT700=m
+CONFIG_SND_SOC_RT700_SDW=m
+CONFIG_SND_SOC_RT711=m
+CONFIG_SND_SOC_RT711_SDCA_SDW=m
+CONFIG_SND_SOC_RT711_SDW=m
+CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW=m
+CONFIG_SND_SOC_RT712_SDCA_SDW=m
+CONFIG_SND_SOC_RT715=m
+CONFIG_SND_SOC_RT715_SDCA_SDW=m
+CONFIG_SND_SOC_RT715_SDW=m
+CONFIG_SND_SOC_RT722_SDCA_SDW=m
+CONFIG_SND_SOC_RT9120=m
+CONFIG_SND_SOC_RTQ9128=m
+CONFIG_SND_SOC_SDCA_HID=y
+CONFIG_SND_SOC_SDCA_IRQ=y
+CONFIG_SND_SOC_SDW_MOCKUP=m
+CONFIG_SND_SOC_SGTL5000=m
+CONFIG_SND_SOC_SI476X=m
+CONFIG_SND_SOC_SIGMADSP_I2C=m
+CONFIG_SND_SOC_SIGMADSP=m
+CONFIG_SND_SOC_SIGMADSP_REGMAP=m
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+CONFIG_SND_SOC_SIMPLE_MUX=m
+CONFIG_SND_SOC_SMA1303=m
+CONFIG_SND_SOC_SOF_ACPI_DEV=m
+CONFIG_SND_SOC_SOF_ACPI=m
+CONFIG_SND_SOC_SOF_ALDERLAKE=m
+CONFIG_SND_SOC_SOF_AMD_ACP63=m
+CONFIG_SND_SOC_SOF_AMD_ACP70=m
+CONFIG_SND_SOC_SOF_AMD_COMMON=m
+CONFIG_SND_SOC_SOF_AMD_REMBRANDT=m
+CONFIG_SND_SOC_SOF_AMD_RENOIR=m
+CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE=m
+CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m
+CONFIG_SND_SOC_SOF_AMD_VANGOGH=m
+CONFIG_SND_SOC_SOF_APOLLOLAKE=m
+CONFIG_SND_SOC_SOF_BAYTRAIL=m
+CONFIG_SND_SOC_SOF_BROADWELL=m
+CONFIG_SND_SOC_SOF_CANNONLAKE=m
+CONFIG_SND_SOC_SOF_CLIENT=m
+CONFIG_SND_SOC_SOF_COFFEELAKE=m
+CONFIG_SND_SOC_SOF_COMETLAKE=m
+CONFIG_SND_SOC_SOF_DEBUG_PROBES=m
+CONFIG_SND_SOC_SOF_ELKHARTLAKE=m
+CONFIG_SND_SOC_SOF_GEMINILAKE=m
+CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC=y
+CONFIG_SND_SOC_SOF_HDA_COMMON=m
+CONFIG_SND_SOC_SOF_HDA_LINK_BASELINE=m
+CONFIG_SND_SOC_SOF_HDA_LINK=y
+CONFIG_SND_SOC_SOF_HDA=m
+CONFIG_SND_SOC_SOF_HDA_MLINK=m
+CONFIG_SND_SOC_SOF_HDA_PROBES=m
+CONFIG_SND_SOC_SOF_ICELAKE=m
+CONFIG_SND_SOC_SOF_INTEL_APL=m
+CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP=m
+CONFIG_SND_SOC_SOF_INTEL_CNL=m
+CONFIG_SND_SOC_SOF_INTEL_COMMON=m
+CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC=m
+CONFIG_SND_SOC_SOF_INTEL_ICL=m
+CONFIG_SND_SOC_SOF_INTEL_IPC4=y
+CONFIG_SND_SOC_SOF_INTEL_MTL=m
+CONFIG_SND_SOC_SOF_INTEL_SKL=m
+CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE=m
+CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE=m
+CONFIG_SND_SOC_SOF_INTEL_TGL=m
+CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL=y
+CONFIG_SND_SOC_SOF_IPC3=y
+CONFIG_SND_SOC_SOF_JASPERLAKE=m
+CONFIG_SND_SOC_SOF_KABYLAKE=m
+CONFIG_SND_SOC_SOF_LUNARLAKE=m
+CONFIG_SND_SOC_SOF=m
+CONFIG_SND_SOC_SOF_MERRIFIELD=m
+CONFIG_SND_SOC_SOF_METEORLAKE=m
+CONFIG_SND_SOC_SOF_PANTHERLAKE=m
+CONFIG_SND_SOC_SOF_PCI_DEV=m
+CONFIG_SND_SOC_SOF_PCI=m
+CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE=y
+CONFIG_SND_SOC_SOF_SKYLAKE=m
+CONFIG_SND_SOC_SOF_TIGERLAKE=m
+CONFIG_SND_SOC_SOF_TOPLEVEL=y
+CONFIG_SND_SOC_SOF_XTENSA=m
+CONFIG_SND_SOC_SPDIF=m
+CONFIG_SND_SOC_SRC4XXX_I2C=m
+CONFIG_SND_SOC_SRC4XXX=m
+CONFIG_SND_SOC_SSM2305=m
+CONFIG_SND_SOC_SSM2518=m
+CONFIG_SND_SOC_SSM2602_I2C=m
+CONFIG_SND_SOC_SSM2602=m
+CONFIG_SND_SOC_SSM2602_SPI=m
+CONFIG_SND_SOC_SSM4567=m
+CONFIG_SND_SOC_STA32X=m
+CONFIG_SND_SOC_STA350=m
+CONFIG_SND_SOC_STI_SAS=m
+CONFIG_SND_SOC_TAS2552=m
+CONFIG_SND_SOC_TAS2562=m
+CONFIG_SND_SOC_TAS2764=m
+CONFIG_SND_SOC_TAS2770=m
+CONFIG_SND_SOC_TAS2780=m
+CONFIG_SND_SOC_TAS2781_COMLIB=m
+CONFIG_SND_SOC_TAS2781_FMWLIB=m
+CONFIG_SND_SOC_TAS2781_I2C=m
+CONFIG_SND_SOC_TAS2783_SDW=m
+CONFIG_SND_SOC_TAS5086=m
+CONFIG_SND_SOC_TAS571X=m
+CONFIG_SND_SOC_TAS5720=m
+CONFIG_SND_SOC_TAS5805M=m
+CONFIG_SND_SOC_TAS6424=m
+CONFIG_SND_SOC_TDA7419=m
+CONFIG_SND_SOC_TFA9879=m
+CONFIG_SND_SOC_TFA989X=m
+CONFIG_SND_SOC_TLV320ADC3XXX=m
+CONFIG_SND_SOC_TLV320ADCX140=m
+CONFIG_SND_SOC_TLV320AIC23_I2C=m
+CONFIG_SND_SOC_TLV320AIC23=m
+CONFIG_SND_SOC_TLV320AIC23_SPI=m
+CONFIG_SND_SOC_TLV320AIC31XX=m
+CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
+CONFIG_SND_SOC_TLV320AIC32X4=m
+CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
+CONFIG_SND_SOC_TLV320AIC3X_I2C=m
+CONFIG_SND_SOC_TLV320AIC3X=m
+CONFIG_SND_SOC_TLV320AIC3X_SPI=m
+CONFIG_SND_SOC_TOPOLOGY=y
+CONFIG_SND_SOC_TPA6130A2=m
+CONFIG_SND_SOC_TS3A227E=m
+CONFIG_SND_SOC_TSCS42XX=m
+CONFIG_SND_SOC_TSCS454=m
+CONFIG_SND_SOC_UDA1334=m
+CONFIG_SND_SOC_WCD9335=m
+CONFIG_SND_SOC_WCD934X=m
+CONFIG_SND_SOC_WCD937X_SDW=m
+CONFIG_SND_SOC_WCD938X=m
+CONFIG_SND_SOC_WCD938X_SDW=m
+CONFIG_SND_SOC_WCD939X_SDW=m
+CONFIG_SND_SOC_WCD_MBHC=m
+CONFIG_SND_SOC_WM5102=m
+CONFIG_SND_SOC_WM8510=m
+CONFIG_SND_SOC_WM8523=m
+CONFIG_SND_SOC_WM8524=m
+CONFIG_SND_SOC_WM8580=m
+CONFIG_SND_SOC_WM8711=m
+CONFIG_SND_SOC_WM8728=m
+CONFIG_SND_SOC_WM8731_I2C=m
+CONFIG_SND_SOC_WM8731=m
+CONFIG_SND_SOC_WM8731_SPI=m
+CONFIG_SND_SOC_WM8737=m
+CONFIG_SND_SOC_WM8741=m
+CONFIG_SND_SOC_WM8750=m
+CONFIG_SND_SOC_WM8753=m
+CONFIG_SND_SOC_WM8770=m
+CONFIG_SND_SOC_WM8776=m
+CONFIG_SND_SOC_WM8782=m
+CONFIG_SND_SOC_WM8804_I2C=m
+CONFIG_SND_SOC_WM8804=m
+CONFIG_SND_SOC_WM8804_SPI=m
+CONFIG_SND_SOC_WM8903=m
+CONFIG_SND_SOC_WM8904=m
+CONFIG_SND_SOC_WM8940=m
+CONFIG_SND_SOC_WM8960=m
+CONFIG_SND_SOC_WM8961=m
+CONFIG_SND_SOC_WM8962=m
+CONFIG_SND_SOC_WM8974=m
+CONFIG_SND_SOC_WM8978=m
+CONFIG_SND_SOC_WM8985=m
+CONFIG_SND_SOC_WM_ADSP=m
+CONFIG_SND_SOC_WSA881X=m
+CONFIG_SND_SOC_WSA883X=m
+CONFIG_SND_SOC_WSA884X=m
+CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
+CONFIG_SND_SOC_XILINX_I2S=m
+CONFIG_SND_SOC_XILINX_SPDIF=m
+CONFIG_SND_SOC_XTFPGA_I2S=m
+CONFIG_SND_SOC_ZL38060=m
+CONFIG_SND_SONICVIBES=m
+CONFIG_SND_SPI=y
+CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI=m
+CONFIG_SND_SST_ATOM_HIFI2_PLATFORM=m
+CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI=m
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_SYNTH_EMUX=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_TRIDENT=m
+CONFIG_SND_UMP_LEGACY_RAWMIDI=y
+CONFIG_SND_UMP=m
+CONFIG_SND_USB_6FIRE=m
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_AUDIO_MIDI_V2=y
+CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_HIFACE=m
+CONFIG_SND_USB_LINE6=m
+CONFIG_SND_USB_PODHD=m
+CONFIG_SND_USB_POD=m
+CONFIG_SND_USB_TONEPORT=m
+CONFIG_SND_USB_UA101=m
+CONFIG_SND_USB_US122L=m
+CONFIG_SND_USB_US144MKII=m
+CONFIG_SND_USB_USX2Y=m
+CONFIG_SND_USB_VARIAX=m
+CONFIG_SND_USB=y
+CONFIG_SND_UTIMER=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VIA82XX=m
+CONFIG_SND_VIA82XX_MODEM=m
+CONFIG_SND_VIRMIDI=m
+CONFIG_SND_VIRTIO=m
+CONFIG_SND_VIRTUOSO=m
+CONFIG_SND_VMASTER=y
+CONFIG_SND_VX222=m
+CONFIG_SND_VX_LIB=m
+CONFIG_SND_VXPOCKET=m
+CONFIG_SND_X86=y
+CONFIG_SND_YMFPCI=m
+CONFIG_SNET_VDPA=m
+CONFIG_SOC_BUS=y
+CONFIG_SOCK_CGROUP_DATA=y
+CONFIG_SOCK_VALIDATE_XMIT=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOFT_WATCHDOG=m
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_SONY_LAPTOP=m
+CONFIG_SONYPI_COMPAT=y
+CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUNDWIRE_AMD=m
+CONFIG_SOUNDWIRE_CADENCE=m
+CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=m
+CONFIG_SOUNDWIRE_INTEL=m
+CONFIG_SOUNDWIRE_QCOM=m
+CONFIG_SOUNDWIRE=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_SPECULATION_MITIGATIONS=y
+CONFIG_SPI_ALTERA_CORE=m
+CONFIG_SPI_ALTERA_DFL=m
+CONFIG_SPI_ALTERA=m
+CONFIG_SPI_AMD=m
+CONFIG_SPI_AXI_SPI_ENGINE=m
+CONFIG_SPI_BITBANG=m
+CONFIG_SPI_BUTTERFLY=m
+CONFIG_SPI_CADENCE=m
+CONFIG_SPI_CH341=m
+CONFIG_SPI_CS42L43=m
+CONFIG_SPI_DESIGNWARE=m
+CONFIG_SPI_DLN2=m
+CONFIG_SPI_DW_MMIO=m
+CONFIG_SPI_DW_PCI=m
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_GPIO=m
+CONFIG_SPI_INTEL=m
+CONFIG_SPI_INTEL_PCI=m
+CONFIG_SPI_INTEL_PLATFORM=m
+CONFIG_SPI_LANTIQ_SSC=m
+CONFIG_SPI_LJCA=m
+CONFIG_SPI_LM70_LLP=m
+CONFIG_SPI_LOOPBACK_TEST=m
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_MICROCHIP_CORE=m
+CONFIG_SPI_MICROCHIP_CORE_QSPI=m
+CONFIG_SPI_MUX=m
+CONFIG_SPI_MXIC=m
+CONFIG_SPI_OC_TINY=m
+CONFIG_SPI_OFFLOAD_TRIGGER_ADI_UTIL_SD=m
+CONFIG_SPI_OFFLOAD_TRIGGER_PWM=m
+CONFIG_SPI_PCI1XXXX=m
+CONFIG_SPI_PXA2XX=m
+CONFIG_SPI_PXA2XX_PCI=m
+CONFIG_SPI_SC18IS602=m
+CONFIG_SPI_SIFIVE=m
+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
+CONFIG_SPI_SLAVE_TIME=m
+CONFIG_SPI_SLAVE=y
+CONFIG_SPI_SPIDEV=m
+CONFIG_SPI_TLE62X0=m
+CONFIG_SPI_VIRTIO=m
+CONFIG_SPI_XCOMM=m
+CONFIG_SPI_XILINX=m
+CONFIG_SPI=y
+CONFIG_SPI_ZYNQMP_GQSPI=m
+CONFIG_SPMI_HISI3670=m
+CONFIG_SPMI=m
+CONFIG_SPS30_I2C=m
+CONFIG_SPS30=m
+CONFIG_SPS30_SERIAL=m
+CONFIG_SRAM=y
+CONFIG_SRF04=m
+CONFIG_SRF08=m
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_BLOCKIO=y
+CONFIG_SSB_DRIVER_GPIO=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB=m
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+CONFIG_SSB_PCMCIAHOST=y
+CONFIG_SSB_SDIOHOST_POSSIBLE=y
+CONFIG_SSB_SDIOHOST=y
+CONFIG_SSB_SPROM=y
+CONFIG_SSFDC=m
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKTRACE=y
+CONFIG_STAGING_MEDIA_DEPRECATED=y
+CONFIG_STAGING_MEDIA=y
+CONFIG_STAGING=y
+CONFIG_STANDALONE=y
+CONFIG_STE10XP=m
+CONFIG_STK3310=m
+CONFIG_STK8312=m
+CONFIG_STK8BA50=m
+CONFIG_STM=m
+CONFIG_STM_PROTO_BASIC=m
+CONFIG_STM_PROTO_SYS_T=m
+CONFIG_STM_SOURCE_CONSOLE=m
+CONFIG_STM_SOURCE_HEARTBEAT=m
+CONFIG_STREAM_PARSER=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+CONFIG_ST_UVIS25_I2C=m
+CONFIG_ST_UVIS25=m
+CONFIG_ST_UVIS25_SPI=m
+CONFIG_SUNGEM_PHY=m
+CONFIG_SUN_PARTITION=y
+CONFIG_SURFACE_3_POWER_OPREGION=m
+CONFIG_SURFACE3_WMI=m
+CONFIG_SURFACE_ACPI_NOTIFY=m
+CONFIG_SURFACE_AGGREGATOR_BUS=y
+CONFIG_SURFACE_AGGREGATOR_CDEV=m
+CONFIG_SURFACE_AGGREGATOR_HUB=m
+CONFIG_SURFACE_AGGREGATOR=m
+CONFIG_SURFACE_AGGREGATOR_REGISTRY=m
+CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m
+CONFIG_SURFACE_DTX=m
+CONFIG_SURFACE_GPE=m
+CONFIG_SURFACE_HOTPLUG=m
+CONFIG_SURFACE_KBD=m
+CONFIG_SURFACE_PLATFORM_PROFILE=m
+CONFIG_SURFACE_PLATFORMS=y
+CONFIG_SURFACE_PRO3_BUTTON=m
+CONFIG_SVC_I3C_MASTER=m
+CONFIG_SX9310=m
+CONFIG_SX9324=m
+CONFIG_SX9360=m
+CONFIG_SX9500=m
+CONFIG_SX_COMMON=m
+CONFIG_SYNC_FILE=y
+CONFIG_SYNCLINK_GT=m
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFB_SIMPLEFB=y
+CONFIG_SYSFB=y
+CONFIG_SYSTEM76_ACPI=m
+CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y
 CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
-# end of Certificates for signature checking
-
-CONFIG_BINARY_PRINTF=y
-
-#
-# Library routines
-#
-CONFIG_RAID6_PQ=m
-CONFIG_RAID6_PQ_BENCHMARK=y
-CONFIG_LINEAR_RANGES=y
-CONFIG_PACKING=y
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_CORDIC=m
-CONFIG_PRIME_NUMBERS=m
-CONFIG_RATIONAL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
-CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC64_ROCKSOFT=m
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC32_SELFTEST is not set
-CONFIG_CRC32_SLICEBY8=y
-# CONFIG_CRC32_SLICEBY4 is not set
-# CONFIG_CRC32_SARWATE is not set
-# CONFIG_CRC32_BIT is not set
-CONFIG_CRC64=m
-CONFIG_CRC4=m
-CONFIG_CRC7=m
-CONFIG_LIBCRC32C=m
-CONFIG_CRC8=m
-CONFIG_XXHASH=y
-# CONFIG_RANDOM32_SELFTEST is not set
-CONFIG_842_COMPRESS=y
-CONFIG_842_DECOMPRESS=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_LZ4_COMPRESS=y
-CONFIG_LZ4HC_COMPRESS=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
-CONFIG_XZ_DEC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_BCJ=y
-# CONFIG_XZ_DEC_TEST is not set
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_LZ4=y
-CONFIG_DECOMPRESS_ZSTD=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_REED_SOLOMON=m
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_DEC16=y
-CONFIG_BCH=m
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
+CONFIG_SYSTEM_BLACKLIST_KEYRING=y
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSV68_PARTITION=y
+CONFIG_T5403=m
+CONFIG_TABLET_SERIAL_WACOM4=m
+CONFIG_TABLET_USB_ACECAD=m
+CONFIG_TABLET_USB_AIPTEK=m
+CONFIG_TABLET_USB_HANWANG=m
+CONFIG_TABLET_USB_KBTAB=m
+CONFIG_TABLET_USB_PEGASUS=m
+CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y
+CONFIG_TAHVO_USB=m
+CONFIG_TAP=m
+CONFIG_TARGET_CORE=m
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASKS_RCU=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_XACCT=y
+CONFIG_TCG_ATMEL=m
+CONFIG_TCG_CRB=m
+CONFIG_TCG_INFINEON=m
+CONFIG_TCG_NSC=m
+CONFIG_TCG_TIS_CORE=m
+CONFIG_TCG_TIS_I2C_ATMEL=m
+CONFIG_TCG_TIS_I2C_CR50=m
+CONFIG_TCG_TIS_I2C_INFINEON=m
+CONFIG_TCG_TIS_I2C=m
+CONFIG_TCG_TIS_I2C_NUVOTON=m
+CONFIG_TCG_TIS=m
+CONFIG_TCG_TIS_SPI=m
+CONFIG_TCG_TIS_ST33ZP24_I2C=m
+CONFIG_TCG_TIS_ST33ZP24=m
+CONFIG_TCG_TIS_ST33ZP24_SPI=m
+CONFIG_TCG_TPM=m
+CONFIG_TCG_VTPM_PROXY=m
+CONFIG_TCM_FC=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_PSCSI=m
+CONFIG_TCM_QLA2XXX=m
+CONFIG_TCM_USER2=m
+CONFIG_TCS3414=m
+CONFIG_TCS3472=m
+CONFIG_TEE=m
+CONFIG_TELCLOCK=m
+CONFIG_TERANETICS_PHY=m
+CONFIG_TEST_ASYNC_DRIVER_PROBE=m
+CONFIG_TEST_LOCKUP=m
 CONFIG_TEXTSEARCH_BM=m
 CONFIG_TEXTSEARCH_FSM=m
-CONFIG_BTREE=y
-CONFIG_INTERVAL_TREE=y
-CONFIG_XARRAY_MULTI=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAS_DMA=y
-CONFIG_DMA_OPS=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_DMA_VIRT_OPS=y
-CONFIG_SWIOTLB=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_PERNUMA_CMA=y
-
-#
-# Default contiguous memory area size:
-#
-CONFIG_CMA_SIZE_MBYTES=0
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_ALIGNMENT=8
-# CONFIG_DMA_API_DEBUG is not set
-# CONFIG_DMA_MAP_BENCHMARK is not set
-CONFIG_SGL_ALLOC=y
-CONFIG_CHECK_SIGNATURE=y
-CONFIG_CPU_RMAP=y
-CONFIG_DQL=y
-CONFIG_GLOB=y
-# CONFIG_GLOB_SELFTEST is not set
-CONFIG_NLATTR=y
-CONFIG_LRU_CACHE=m
-CONFIG_CLZ_TAB=y
-CONFIG_IRQ_POLL=y
-CONFIG_MPILIB=y
-CONFIG_DIMLIB=y
-CONFIG_OID_REGISTRY=y
-CONFIG_UCS2_STRING=y
-CONFIG_HAVE_GENERIC_VDSO=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GENERIC_VDSO_TIME_NS=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_6x10 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-CONFIG_FONT_TER16x32=y
-CONFIG_FONT_6x8=y
-CONFIG_STACK_HASH_ORDER=16
-CONFIG_SG_POOL=y
-CONFIG_MEMREGION=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_SBITMAP=y
-CONFIG_PARMAN=m
-CONFIG_OBJAGG=m
-# CONFIG_STRING_SELFTEST is not set
-# end of Library routines
-
-CONFIG_PLDMFW=y
-
-#
-# Kernel hacking
-#
-
-#
-# printk and dmesg options
-#
-# CONFIG_PRINTK_TIME is not set
-# CONFIG_PRINTK_CALLER is not set
-CONFIG_STACKTRACE_BUILD_ID=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
-CONFIG_CONSOLE_LOGLEVEL_QUIET=4
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_DYNAMIC_DEBUG_CORE is not set
-CONFIG_SYMBOLIC_ERRNAME=y
-CONFIG_DEBUG_BUGVERBOSE=y
-# end of printk and dmesg options
-
-#
-# Compile-time checks and compiler options
-#
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_INFO_REDUCED is not set
-CONFIG_DEBUG_INFO_COMPRESSED=y
-# CONFIG_DEBUG_INFO_SPLIT is not set
-# CONFIG_DEBUG_INFO_NONE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-# CONFIG_DEBUG_INFO_DWARF4 is not set
-# CONFIG_DEBUG_INFO_DWARF5 is not set
-CONFIG_DEBUG_INFO_BTF=y
-CONFIG_MODULE_ALLOW_BTF_MISMATCH=y
-# CONFIG_GDB_SCRIPTS is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_FRAME_WARN=0
-CONFIG_STRIP_ASM_SYMS=y
-# CONFIG_READABLE_ASM is not set
-# CONFIG_HEADERS_INSTALL is not set
-# CONFIG_DEBUG_SECTION_MISMATCH is not set
-CONFIG_SECTION_MISMATCH_WARN_ONLY=y
-# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set
-# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
-CONFIG_VMLINUX_MAP=y
-CONFIG_FRAME_POINTER=y
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# end of Compile-time checks and compiler options
-
-#
-# Generic Kernel Debugging Instruments
-#
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
-CONFIG_MAGIC_SYSRQ_SERIAL=y
-CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_FS_ALLOW_ALL is not set
-# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
-# CONFIG_DEBUG_FS_ALLOW_NONE is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
-# CONFIG_UBSAN is not set
-# end of Generic Kernel Debugging Instruments
-
-# CONFIG_DEBUG_KERNEL is not set
-# CONFIG_DEBUG_MISC is not set
-
-#
-# Memory Debugging
-#
-# CONFIG_PAGE_EXTENSION is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
-# CONFIG_PAGE_OWNER is not set
-# CONFIG_PAGE_TABLE_CHECK is not set
-# CONFIG_PAGE_POISONING is not set
-# CONFIG_DEBUG_PAGE_REF is not set
-# CONFIG_DEBUG_RODATA_TEST is not set
-CONFIG_ARCH_HAS_DEBUG_WX=y
-CONFIG_DEBUG_WX=y
-CONFIG_GENERIC_PTDUMP=y
-CONFIG_PTDUMP_CORE=y
-# CONFIG_PTDUMP_DEBUGFS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SHRINKER_DEBUG is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_HAVE_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_SCHED_STACK_END_CHECK is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_ARCH_HAS_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_PER_CPU_MAPS is not set
-# CONFIG_DEBUG_KMAP_LOCAL is not set
-# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set
-# CONFIG_DEBUG_HIGHMEM is not set
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-# CONFIG_DEBUG_STACKOVERFLOW is not set
-CONFIG_CC_HAS_KASAN_GENERIC=y
-CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
-# CONFIG_KASAN is not set
-# end of Memory Debugging
-
-# CONFIG_DEBUG_SHIRQ is not set
-
-#
-# Debug Oops, Lockups and Hangs
-#
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=60
-# CONFIG_SOFTLOCKUP_DETECTOR is not set
-# CONFIG_HARDLOCKUP_DETECTOR is not set
-# CONFIG_DETECT_HUNG_TASK is not set
-# CONFIG_WQ_WATCHDOG is not set
-CONFIG_TEST_LOCKUP=m
-# end of Debug Oops, Lockups and Hangs
-
-#
-# Scheduler Debugging
-#
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHED_INFO=y
-CONFIG_SCHEDSTATS=y
-# end of Scheduler Debugging
-
-# CONFIG_DEBUG_TIMEKEEPING is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_IRQFLAGS is not set
-
-#
-# Lock Debugging (spinlocks, mutexes, etc...)
-#
-# CONFIG_LOCK_DEBUGGING_SUPPORT is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
-# CONFIG_DEBUG_RWSEMS is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_DEBUG_ATOMIC_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_LOCK_TORTURE_TEST is not set
-# CONFIG_WW_MUTEX_SELFTEST is not set
-CONFIG_SCF_TORTURE_TEST=m
-# end of Lock Debugging (spinlocks, mutexes, etc...)
-
-CONFIG_STACKTRACE=y
-# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
-# CONFIG_DEBUG_KOBJECT is not set
-
-#
-# Debug kernel data structures
-#
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_PLIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BUG_ON_DATA_CORRUPTION is not set
-# end of Debug kernel data structures
-
-# CONFIG_DEBUG_CREDENTIALS is not set
-
-#
-# RCU Debugging
-#
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH=y
+CONFIG_THERMAL_ACPI=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=100
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_NETLINK=y
+CONFIG_THERMAL_STATISTICS=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL=y
+CONFIG_THINKPAD_ACPI_ALSA_SUPPORT=y
+CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y
+CONFIG_THINKPAD_ACPI=m
+CONFIG_THINKPAD_ACPI_VIDEO=y
+CONFIG_THINKPAD_LMI=m
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TI_ADC081C=m
+CONFIG_TI_ADC0832=m
+CONFIG_TI_ADC084S021=m
+CONFIG_TI_ADC108S102=m
+CONFIG_TI_ADC12138=m
+CONFIG_TI_ADC128S052=m
+CONFIG_TI_ADC161S626=m
+CONFIG_TI_ADS1015=m
+CONFIG_TI_ADS1100=m
+CONFIG_TI_ADS1119=m
+CONFIG_TI_ADS124S08=m
+CONFIG_TI_ADS1298=m
+CONFIG_TI_ADS131E08=m
+CONFIG_TI_ADS7138=m
+CONFIG_TI_ADS7924=m
+CONFIG_TI_ADS7950=m
+CONFIG_TI_ADS8344=m
+CONFIG_TI_ADS8688=m
+CONFIG_TI_AM335X_ADC=m
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TI_DAC082S085=m
+CONFIG_TI_DAC5571=m
+CONFIG_TI_DAC7311=m
+CONFIG_TI_DAC7612=m
+CONFIG_TIFM_7XX1=m
+CONFIG_TIFM_CORE=m
+CONFIG_TI_LMP92064=m
+CONFIG_TINYDRM_HX8357D=m
+CONFIG_TINYDRM_ILI9163=m
+CONFIG_TINYDRM_ILI9225=m
+CONFIG_TINYDRM_ILI9341=m
+CONFIG_TINYDRM_ILI9486=m
+CONFIG_TINYDRM_MI0283QT=m
+CONFIG_TINYDRM_REPAPER=m
+CONFIG_TINYDRM_ST7586=m
+CONFIG_TINYDRM_ST7735R=m
+CONFIG_TI_ST=m
+CONFIG_TI_TLC4541=m
+CONFIG_TI_TMAG5273=m
+CONFIG_TI_TSC2046=m
+CONFIG_TMD_HERMES=m
+CONFIG_TMP006=m
+CONFIG_TMP007=m
+CONFIG_TMP117=m
+CONFIG_TOOLS_SUPPORT_RELR=y
+CONFIG_TOPSTAR_LAPTOP=m
 CONFIG_TORTURE_TEST=m
-CONFIG_RCU_SCALE_TEST=m
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_REF_SCALE_TEST=m
-CONFIG_RCU_CPU_STALL_TIMEOUT=60
-# CONFIG_RCU_TRACE is not set
-# CONFIG_RCU_EQS_DEBUG is not set
-# end of RCU Debugging
-
-# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-CONFIG_LATENCYTOP=y
+CONFIG_TOSHIBA_BT_RFKILL=m
+CONFIG_TOSHIBA_HAPS=m
+CONFIG_TOSHIBA=m
+CONFIG_TOSHIBA_WMI=m
+CONFIG_TOUCHSCREEN_AD7877=m
+CONFIG_TOUCHSCREEN_AD7879_I2C=m
+CONFIG_TOUCHSCREEN_AD7879=m
+CONFIG_TOUCHSCREEN_AD7879_SPI=m
+CONFIG_TOUCHSCREEN_ADC=m
+CONFIG_TOUCHSCREEN_ADS7846=m
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
+CONFIG_TOUCHSCREEN_BU21013=m
+CONFIG_TOUCHSCREEN_BU21029=m
+CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
+CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
+CONFIG_TOUCHSCREEN_CY8CTMA140=m
+CONFIG_TOUCHSCREEN_CY8CTMG110=m
+CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
+CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
+CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
+CONFIG_TOUCHSCREEN_CYTTSP5=m
+CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
+CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
+CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
+CONFIG_TOUCHSCREEN_DA9052=m
+CONFIG_TOUCHSCREEN_DYNAPRO=m
+CONFIG_TOUCHSCREEN_EDT_FT5X06=m
+CONFIG_TOUCHSCREEN_EETI=m
+CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
+CONFIG_TOUCHSCREEN_EKTF2127=m
+CONFIG_TOUCHSCREEN_ELAN=m
+CONFIG_TOUCHSCREEN_ELO=m
+CONFIG_TOUCHSCREEN_EXC3000=m
+CONFIG_TOUCHSCREEN_FUJITSU=m
+CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C=m
+CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI=m
+CONFIG_TOUCHSCREEN_GOODIX=m
+CONFIG_TOUCHSCREEN_GUNZE=m
+CONFIG_TOUCHSCREEN_HAMPSHIRE=m
+CONFIG_TOUCHSCREEN_HIDEEP=m
+CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m
+CONFIG_TOUCHSCREEN_HIMAX_HX852X=m
+CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
+CONFIG_TOUCHSCREEN_HYNITRON_CST816X=m
+CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=m
+CONFIG_TOUCHSCREEN_ILI210X=m
+CONFIG_TOUCHSCREEN_ILITEK=m
+CONFIG_TOUCHSCREEN_IMAGIS=m
+CONFIG_TOUCHSCREEN_INEXIO=m
+CONFIG_TOUCHSCREEN_IQS5XX=m
+CONFIG_TOUCHSCREEN_IQS7211=m
+CONFIG_TOUCHSCREEN_MAX11801=m
+CONFIG_TOUCHSCREEN_MC13783=m
+CONFIG_TOUCHSCREEN_MCS5000=m
+CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
+CONFIG_TOUCHSCREEN_MK712=m
+CONFIG_TOUCHSCREEN_MMS114=m
+CONFIG_TOUCHSCREEN_MSG2638=m
+CONFIG_TOUCHSCREEN_MTOUCH=m
+CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS=m
+CONFIG_TOUCHSCREEN_PCAP=m
+CONFIG_TOUCHSCREEN_PENMOUNT=m
+CONFIG_TOUCHSCREEN_PIXCIR=m
+CONFIG_TOUCHSCREEN_RM_TS=m
+CONFIG_TOUCHSCREEN_ROHM_BU21023=m
+CONFIG_TOUCHSCREEN_S6SY761=m
+CONFIG_TOUCHSCREEN_SILEAD=m
+CONFIG_TOUCHSCREEN_SIS_I2C=m
+CONFIG_TOUCHSCREEN_ST1232=m
+CONFIG_TOUCHSCREEN_STMFTS=m
+CONFIG_TOUCHSCREEN_SUR40=m
+CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
+CONFIG_TOUCHSCREEN_SX8654=m
+CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m
+CONFIG_TOUCHSCREEN_TOUCHIT213=m
+CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
+CONFIG_TOUCHSCREEN_TOUCHWIN=m
+CONFIG_TOUCHSCREEN_TPS6507X=m
+CONFIG_TOUCHSCREEN_TSC2004=m
+CONFIG_TOUCHSCREEN_TSC2005=m
+CONFIG_TOUCHSCREEN_TSC2007_IIO=y
+CONFIG_TOUCHSCREEN_TSC2007=m
+CONFIG_TOUCHSCREEN_TSC200X_CORE=m
+CONFIG_TOUCHSCREEN_TSC_SERIO=m
+CONFIG_TOUCHSCREEN_USB_3M=y
+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
+CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
+CONFIG_TOUCHSCREEN_USB_E2I=y
+CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
+CONFIG_TOUCHSCREEN_USB_EGALAX=y
+CONFIG_TOUCHSCREEN_USB_ELO=y
+CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
+CONFIG_TOUCHSCREEN_USB_ETURBO=y
+CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
+CONFIG_TOUCHSCREEN_USB_GOTOP=y
+CONFIG_TOUCHSCREEN_USB_GUNZE=y
+CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
+CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
+CONFIG_TOUCHSCREEN_USB_ITM=y
+CONFIG_TOUCHSCREEN_USB_JASTEC=y
+CONFIG_TOUCHSCREEN_USB_NEXIO=y
+CONFIG_TOUCHSCREEN_USB_PANJIT=y
+CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
+CONFIG_TOUCHSCREEN_WACOM_I2C=m
+CONFIG_TOUCHSCREEN_WACOM_W8001=m
+CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
+CONFIG_TOUCHSCREEN_WM831X=m
+CONFIG_TOUCHSCREEN_WM9705=y
+CONFIG_TOUCHSCREEN_WM9712=y
+CONFIG_TOUCHSCREEN_WM9713=y
+CONFIG_TOUCHSCREEN_WM97XX=m
+CONFIG_TOUCHSCREEN_ZET6223=m
+CONFIG_TOUCHSCREEN_ZFORCE=m
+CONFIG_TOUCHSCREEN_ZINITIX=m
+CONFIG_TPL0102=m
+CONFIG_TPS6105X=m
+CONFIG_TPS65010=m
+CONFIG_TPS6507X=m
+CONFIG_TPS6594_ESM=m
+CONFIG_TPS6594_PFSM=m
+CONFIG_TPS68470_PMIC_OPREGION=y
+CONFIG_TP_SMAPI=m
+CONFIG_TQMX86_WDT=m
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRUSTED_KEYS=m
+CONFIG_TRUSTED_KEYS_TEE=y
+CONFIG_TRUSTED_KEYS_TPM=y
+CONFIG_TSL2583=m
+CONFIG_TSL2591=m
+CONFIG_TSL2772=m
+CONFIG_TSL4531=m
+CONFIG_TSYS01=m
+CONFIG_TSYS02D=m
+CONFIG_TTPCI_EEPROM=m
+CONFIG_TUN=m
+CONFIG_TUXEDO_NB04_WMI_AB=m
+CONFIG_TYPEC_ANX7411=m
+CONFIG_TYPEC_DP_ALTMODE=m
+CONFIG_TYPEC_FUSB302=m
+CONFIG_TYPEC_HD3SS3220=m
+CONFIG_TYPEC=m
+CONFIG_TYPEC_MT6360=m
+CONFIG_TYPEC_MUX_FSA4480=m
+CONFIG_TYPEC_MUX_GPIO_SBU=m
+CONFIG_TYPEC_MUX_INTEL_PMC=m
+CONFIG_TYPEC_MUX_IT5205=m
+CONFIG_TYPEC_MUX_NB7VPQ904M=m
+CONFIG_TYPEC_MUX_PI3USB30532=m
+CONFIG_TYPEC_MUX_PS883X=m
+CONFIG_TYPEC_MUX_PTN36502=m
+CONFIG_TYPEC_MUX_WCD939X_USBSS=m
+CONFIG_TYPEC_NVIDIA_ALTMODE=m
+CONFIG_TYPEC_RT1711H=m
+CONFIG_TYPEC_RT1719=m
+CONFIG_TYPEC_STUSB160X=m
+CONFIG_TYPEC_TBT_ALTMODE=m
+CONFIG_TYPEC_TCPCI=m
+CONFIG_TYPEC_TCPCI_MAXIM=m
+CONFIG_TYPEC_TCPCI_MT6370=m
+CONFIG_TYPEC_TCPM=m
+CONFIG_TYPEC_TPS6598X=m
+CONFIG_TYPEC_UCSI=m
+CONFIG_TYPEC_WUSB3801=m
+CONFIG_UACCE=m
+CONFIG_UCS2_STRING=y
+CONFIG_UCSI_ACPI=m
+CONFIG_UCSI_CCG=m
+CONFIG_UCSI_STM32G0=m
+CONFIG_UEFI_CPER_X86=y
+CONFIG_UEFI_CPER=y
+CONFIG_UID16=y
+CONFIG_UIO_AEC=m
+CONFIG_UIO_CIF=m
+CONFIG_UIO_DFL=m
+CONFIG_UIO_DMEM_GENIRQ=m
+CONFIG_UIO_HV_GENERIC=m
+CONFIG_UIO_MF624=m
+CONFIG_UIO_NETX=m
+CONFIG_UIO_PCI_GENERIC=m
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_UIO_PRUSS=m
+CONFIG_UIO_SERCOS3=m
+CONFIG_ULTRIX_PARTITION=y
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_UNWINDER_FRAME_POINTER=y
+CONFIG_US5182D=m
+CONFIG_USB4=m
+CONFIG_USB4_NET=m
+CONFIG_USB_ACM=m
+CONFIG_USB_ADUTUX=m
+CONFIG_USB_AIRSPY=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AMD5536UDC=m
+CONFIG_USB_AN2720=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_APPLEDISPLAY=m
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_ATM=m
+CONFIG_USB_AUDIO=m
+CONFIG_USB_BDC_UDC=m
+CONFIG_USB_BELKIN=y
+CONFIG_USB_C67X00_HCD=m
+CONFIG_USB_CATC=m
+CONFIG_USB_CDC_COMPOSITE=m
+CONFIG_USB_CDC_PHONET=m
+CONFIG_USB_CDNS2_UDC=m
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_USB_CDNS3=m
+CONFIG_USB_CDNS3_PCI_WRAP=m
+CONFIG_USB_CDNS_HOST=y
+CONFIG_USB_CDNSP_GADGET=y
+CONFIG_USB_CDNSP_HOST=y
+CONFIG_USB_CDNSP_PCI=m
+CONFIG_USB_CDNS_SUPPORT=m
+CONFIG_USB_CHAOSKEY=m
+CONFIG_USB_CHIPIDEA_GENERIC=m
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA=m
+CONFIG_USB_CHIPIDEA_MSM=m
+CONFIG_USB_CHIPIDEA_NPCM=m
+CONFIG_USB_CHIPIDEA_PCI=m
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=m
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_MIDI2=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_USB_CONFIGFS_F_PRINTER=y
+CONFIG_USB_CONFIGFS_F_TCM=y
+CONFIG_USB_CONFIGFS_F_UAC1=y
+CONFIG_USB_CONFIGFS_F_UAC2=y
+CONFIG_USB_CONFIGFS_F_UVC=y
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_PHONET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONN_GPIO=m
+CONFIG_USB_CXACRU=m
+CONFIG_USB_CYPRESS_CY7C63=m
+CONFIG_USB_CYTHERM=m
+CONFIG_USB_DSBR=m
+CONFIG_USB_DWC2_DUAL_ROLE=y
+CONFIG_USB_DWC2=m
+CONFIG_USB_DWC2_PCI=m
+CONFIG_USB_DWC3_DUAL_ROLE=y
+CONFIG_USB_DWC3_HAPS=m
+CONFIG_USB_DWC3=m
+CONFIG_USB_DWC3_PCI=m
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_EG20T=m
+CONFIG_USB_EHCI_FSL=m
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_EHCI_HCD_PLATFORM=m
+CONFIG_USB_EHCI_PCI=m
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHSET_TEST_FIXTURE=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_EMI62=m
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_ETH_EEM=y
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_EZUSB_FX2=m
+CONFIG_USB_F_ACM=m
+CONFIG_USB_F_ECM=m
+CONFIG_USB_F_EEM=m
+CONFIG_USB_FEW_INIT_RETRIES=y
+CONFIG_USB_F_FS=m
+CONFIG_USB_F_HID=m
+CONFIG_USB_F_MASS_STORAGE=m
+CONFIG_USB_F_MIDI=m
+CONFIG_USB_F_NCM=m
+CONFIG_USB_F_OBEX=m
+CONFIG_USB_F_PHONET=m
+CONFIG_USB_F_PRINTER=m
+CONFIG_USB_F_RNDIS=m
+CONFIG_USB_F_SERIAL=m
+CONFIG_USB_F_SS_LB=m
+CONFIG_USB_F_SUBSET=m
+CONFIG_USB_F_TCM=m
+CONFIG_USB_F_UAC1=m
+CONFIG_USB_F_UAC2=m
+CONFIG_USB_FUNCTIONFS_ETH=y
+CONFIG_USB_FUNCTIONFS_GENERIC=y
+CONFIG_USB_FUNCTIONFS=m
+CONFIG_USB_FUNCTIONFS_RNDIS=y
+CONFIG_USB_F_UVC=m
+CONFIG_USB_G_ACM_MS=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_GADGET=m
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+CONFIG_USB_GADGET_TARGET=m
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_G_HID=m
+CONFIG_USB_GL860=m
+CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_RNDIS=y
+CONFIG_USB_G_NCM=m
+CONFIG_USB_G_NOKIA=m
+CONFIG_USB_GOKU=m
+CONFIG_USB_GPIO_VBUS=m
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_GR_UDC=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_GSPCA_BENQ=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_CPIA1=m
+CONFIG_USB_GSPCA_DTCS033=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_JEILINJ=m
+CONFIG_USB_GSPCA_JL2005BCD=m
+CONFIG_USB_GSPCA_KINECT=m
+CONFIG_USB_GSPCA_KONICA=m
+CONFIG_USB_GSPCA=m
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_MR97310A=m
+CONFIG_USB_GSPCA_NW80X=m
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534_9=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7302=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SE401=m
+CONFIG_USB_GSPCA_SN9C2028=m
+CONFIG_USB_GSPCA_SN9C20X=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA1528=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+CONFIG_USB_GSPCA_SQ905C=m
+CONFIG_USB_GSPCA_SQ905=m
+CONFIG_USB_GSPCA_SQ930X=m
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_STK1135=m
+CONFIG_USB_GSPCA_STV0680=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TOPRO=m
+CONFIG_USB_GSPCA_TOUPTEK=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+CONFIG_USB_GSPCA_VICAM=m
+CONFIG_USB_GSPCA_XIRLINK_CIT=m
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_USB_G_WEBCAM=m
+CONFIG_USB_HACKRF=m
+CONFIG_USB_HCD_BCMA=m
+CONFIG_USB_HCD_SSB=m
+CONFIG_USB_HSIC_USB3503=m
+CONFIG_USB_HSIC_USB4604=m
+CONFIG_USB_HSO=m
+CONFIG_USB_HUB_USB251XB=m
+CONFIG_USB_IDMOUSE=m
+CONFIG_USB_IOWARRIOR=m
+CONFIG_USBIP_CORE=m
+CONFIG_USB_IPHETH=m
+CONFIG_USBIP_HOST=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_VHCI_HC_PORTS=8
+CONFIG_USBIP_VHCI_NR_HCS=1
+CONFIG_USBIP_VUDC=m
+CONFIG_USB_ISIGHTFW=m
+CONFIG_USB_ISP116X_HCD=m
+CONFIG_USB_ISP1301=m
+CONFIG_USB_ISP1760_DUAL_ROLE=y
+CONFIG_USB_ISP1760_HCD=y
+CONFIG_USB_ISP1760=m
+CONFIG_USB_ISP1761_UDC=y
+CONFIG_USB_KAWETH=m
+CONFIG_USB_KC2190=y
+CONFIG_USB_KEENE=m
+CONFIG_USB_LAN78XX=m
+CONFIG_USB_LCD=m
+CONFIG_USB_LD=m
+CONFIG_USB_LEDS_TRIGGER_USBPORT=m
+CONFIG_USB_LED_TRIG=y
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LGM_PHY=m
+CONFIG_USB_LIBCOMPOSITE=m
+CONFIG_USB_LINK_LAYER_TEST=m
+CONFIG_USB_LJCA=m
+CONFIG_USB=m
+CONFIG_USB_M5602=m
+CONFIG_USB_M66592=m
+CONFIG_USB_MA901=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_MAX3420_UDC=m
+CONFIG_USB_MAX3421_HCD=m
+CONFIG_USB_MDC800=m
+CONFIG_USB_MICROTEK=m
+CONFIG_USB_MIDI_GADGET=m
+CONFIG_USB_MON=m
+CONFIG_USB_MR800=m
+CONFIG_USB_MSI2500=m
+CONFIG_USB_MUSB_DUAL_ROLE=y
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MV_U3D=m
+CONFIG_USB_MV_UDC=m
+CONFIG_USB_NET2272_DMA=y
+CONFIG_USB_NET2272=m
+CONFIG_USB_NET2280=m
+CONFIG_USB_NET_AQC111=m
+CONFIG_USB_NET_AX88179_178A=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_MBIM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_NET_CH9200=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_DRIVERS=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_SR9700=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_OHCI_HCD_PCI=m
+CONFIG_USB_OHCI_HCD_PLATFORM=m
+CONFIG_USB_OHCI_HCD_SSB=y
+CONFIG_USB_OTG_FSM=m
+CONFIG_USB_OTG=y
+CONFIG_USB_OXU210HP_HCD=m
+CONFIG_USBPCWATCHDOG=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_PHY=y
+CONFIG_USB_PRINTER=m
+CONFIG_USB_PULSE8_CEC=m
+CONFIG_USB_PWC_INPUT_EVDEV=y
+CONFIG_USB_PWC=m
+CONFIG_USB_PXA27X=m
+CONFIG_USB_R8A66597_HCD=m
+CONFIG_USB_R8A66597=m
+CONFIG_USB_RAINSHADOW_CEC=m
+CONFIG_USB_RAREMONO=m
+CONFIG_USB_RAW_GADGET=m
+CONFIG_USB_ROLES_INTEL_XHCI=m
+CONFIG_USB_ROLE_SWITCH=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_RTL8153_ECM=m
+CONFIG_USB_S2255=m
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_F8153X=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_METRO=m
+CONFIG_USB_SERIAL_MOS7715_PARPORT=y
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MXUPORT=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QT2=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SAFE=m
+CONFIG_USB_SERIAL_SAFE_PADDED=y
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SIMPLE=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_WISHBONE=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_XR=m
+CONFIG_USB_SERIAL_XSENS_MT=m
+CONFIG_USB_SEVSEG=m
+CONFIG_USB_SI470X=m
+CONFIG_USB_SI4713=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_SL811_CS=m
+CONFIG_USB_SL811_HCD=m
+CONFIG_USB_SNP_CORE=m
+CONFIG_USB_SPEEDTOUCH=m
+CONFIG_USB_STORAGE_ALAUDA=m
+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_ENE_UB6250=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_KARMA=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_STORAGE_ONETOUCH=m
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STV06XX=m
+CONFIG_USB_TEST=m
+CONFIG_USB_TMC=m
+CONFIG_USB_TRANCEVIBRATOR=m
+CONFIG_USB_UAS=m
+CONFIG_USB_U_AUDIO=m
+CONFIG_USB_UEAGLEATM=m
+CONFIG_USB_U_ETHER=m
+CONFIG_USB_UHCI_HCD=m
+CONFIG_USB_ULPI_BUS=m
+CONFIG_USB_USBIO=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_U_SERIAL=m
+CONFIG_USB_USS720=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VL600=m
+CONFIG_USB_WDM=m
+CONFIG_USB_XHCI_DBGCAP=y
+CONFIG_USB_XHCI_HCD=m
+CONFIG_USB_XHCI_PCI=m
+CONFIG_USB_XHCI_PCI_RENESAS=m
+CONFIG_USB_XHCI_PLATFORM=m
+CONFIG_USB_XUSBATM=m
+CONFIG_USB_YUREX=m
+CONFIG_USB_ZD1201=m
+CONFIG_USB_ZERO_HNPTEST=y
+CONFIG_USB_ZERO=m
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+CONFIG_USER_DECRYPTED_DATA=y
+CONFIG_USERFAULTFD=y
+CONFIG_U_SERIAL_CONSOLE=y
+CONFIG_USERIO=m
+CONFIG_USER_RETURN_NOTIFIER=y
 CONFIG_USER_STACKTRACE_SUPPORT=y
-CONFIG_NOP_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_FENTRY=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_RING_BUFFER=y
-CONFIG_EVENT_TRACING=y
-CONFIG_CONTEXT_SWITCH_TRACER=y
-CONFIG_TRACING=y
-CONFIG_GENERIC_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-CONFIG_FTRACE=y
-CONFIG_BOOTTIME_TRACING=y
-CONFIG_FUNCTION_TRACER=y
-# CONFIG_FUNCTION_GRAPH_TRACER is not set
-CONFIG_DYNAMIC_FTRACE=y
-CONFIG_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
-# CONFIG_FPROBE is not set
-CONFIG_FTRACE_RECORD_RECURSION=y
-CONFIG_FTRACE_RECORD_RECURSION_SIZE=128
-CONFIG_RING_BUFFER_RECORD_RECURSION=y
-# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
-CONFIG_FUNCTION_PROFILER=y
-CONFIG_STACK_TRACER=y
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_HWLAT_TRACER is not set
-# CONFIG_OSNOISE_TRACER is not set
-# CONFIG_TIMERLAT_TRACER is not set
-# CONFIG_MMIOTRACE is not set
-CONFIG_FTRACE_SYSCALLS=y
-# CONFIG_TRACER_SNAPSHOT is not set
-CONFIG_BRANCH_PROFILE_NONE=y
-# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
-# CONFIG_PROFILE_ALL_BRANCHES is not set
-CONFIG_BLK_DEV_IO_TRACE=y
-CONFIG_KPROBE_EVENTS=y
-# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set
-# CONFIG_UPROBE_EVENTS is not set
-CONFIG_BPF_EVENTS=y
-CONFIG_DYNAMIC_EVENTS=y
-CONFIG_PROBE_EVENTS=y
-CONFIG_BPF_KPROBE_OVERRIDE=y
-CONFIG_FTRACE_MCOUNT_RECORD=y
-# CONFIG_SYNTH_EVENTS is not set
-# CONFIG_HIST_TRIGGERS is not set
-# CONFIG_HIST_TRIGGERS is not set
-# CONFIG_TRACE_EVENT_INJECT is not set
-# CONFIG_TRACEPOINT_BENCHMARK is not set
-# CONFIG_RING_BUFFER_BENCHMARK is not set
-# CONFIG_TRACE_EVAL_MAP_FILE is not set
-# CONFIG_FTRACE_STARTUP_TEST is not set
-# CONFIG_RING_BUFFER_STARTUP_TEST is not set
-CONFIG_PREEMPTIRQ_DELAY_TEST=m
-CONFIG_KPROBE_EVENT_GEN_TEST=m
-# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
-# CONFIG_SAMPLES is not set
-CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
-CONFIG_STRICT_DEVMEM=y
-# CONFIG_IO_STRICT_DEVMEM is not set
-
-#
-# x86 Debugging
-#
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-# CONFIG_EARLY_PRINTK_USB is not set
+CONFIG_UVC_COMMON=m
+CONFIG_V4L2_ASYNC=m
+CONFIG_V4L2_FLASH_LED_CLASS=m
+CONFIG_V4L2_FWNODE=m
+CONFIG_V4L2_LOOPBACK=m
+CONFIG_V4L2_MEM2MEM_DEV=m
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VBOXGUEST=m
+CONFIG_VCNL3020=m
+CONFIG_VCNL4000=m
+CONFIG_VCNL4035=m
+CONFIG_VDPA=m
+CONFIG_VDPA_USER=m
+CONFIG_VEML6030=m
+CONFIG_VEML6040=m
+CONFIG_VEML6046X00=m
+CONFIG_VEML6070=m
+CONFIG_VEML6075=m
+CONFIG_VETH=m
+CONFIG_VF610_ADC=m
+CONFIG_VF610_DAC=m
+CONFIG_VFIO_CONTAINER=y
+CONFIG_VFIO_DEVICE_CDEV=y
+CONFIG_VFIO_GROUP=y
+CONFIG_VFIO_IOMMU_TYPE1=m
+CONFIG_VFIO=m
+CONFIG_VFIO_PCI_CORE=m
+CONFIG_VFIO_PCI_IGD=y
+CONFIG_VFIO_PCI_INTX=y
+CONFIG_VFIO_PCI=m
+CONFIG_VFIO_PCI_MMAP=y
+CONFIG_VFIO_PCI_VGA=y
+CONFIG_VFIO_VIRQFD=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VGA_CONSOLE=y
+CONFIG_VGASTATE=m
+CONFIG_VGA_SWITCHEROO=y
+CONFIG_VHOST_IOTLB=m
+CONFIG_VHOST=m
+CONFIG_VHOST_RING=m
+CONFIG_VHOST_SCSI=m
+CONFIG_VHOST_TASK=y
+CONFIG_VHOST_VDPA=m
+CONFIG_VIA_WDT=m
+CONFIG_VIDEO_AD5820=m
+CONFIG_VIDEO_ADP1653=m
+CONFIG_VIDEO_ADV7170=m
+CONFIG_VIDEO_ADV7175=m
+CONFIG_VIDEO_AK7375=m
+CONFIG_VIDEO_ALVIUM_CSI2=m
+CONFIG_VIDEO_APTINA_PLL=m
+CONFIG_VIDEO_AR0521=m
+CONFIG_VIDEO_ATOMISP_GC0310=m
+CONFIG_VIDEO_ATOMISP_GC2235=m
+CONFIG_VIDEO_ATOMISP_ISP2401=y
+CONFIG_VIDEO_ATOMISP_LM3554=m
+CONFIG_VIDEO_ATOMISP=m
+CONFIG_VIDEO_ATOMISP_MSRLIST_HELPER=m
+CONFIG_VIDEO_ATOMISP_MT9M114=m
+CONFIG_VIDEO_ATOMISP_OV2680=m
+CONFIG_VIDEO_ATOMISP_OV2722=m
+CONFIG_VIDEO_ATOMISP_OV5693=m
+CONFIG_VIDEO_AU0828=m
+CONFIG_VIDEO_AU0828_RC=y
+CONFIG_VIDEO_AU0828_V4L2=y
+CONFIG_VIDEO_BT819=m
+CONFIG_VIDEO_BT848=m
+CONFIG_VIDEO_BT856=m
+CONFIG_VIDEO_BT866=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_DMA_CONTIG=m
+CONFIG_VIDEOBUF2_DMA_SG=m
+CONFIG_VIDEOBUF2_DVB=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_V4L2=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEOBUF_DMA_SG=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEO_CADENCE_CSI2RX=m
+CONFIG_VIDEO_CADENCE_CSI2TX=m
+CONFIG_VIDEO_CAFE_CCIC=m
+CONFIG_VIDEO_CAMERA_SENSOR=y
+CONFIG_VIDEO_CCS=m
+CONFIG_VIDEO_CCS_PLL=m
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEO_CS3308=m
+CONFIG_VIDEO_CS5345=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_CX18_ALSA=m
+CONFIG_VIDEO_CX18=m
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX2341X=m
+CONFIG_VIDEO_CX23885=m
+CONFIG_VIDEO_CX25821_ALSA=m
+CONFIG_VIDEO_CX25821=m
+CONFIG_VIDEO_CX25840=m
+CONFIG_VIDEO_CX88_ALSA=m
+CONFIG_VIDEO_CX88_BLACKBIRD=m
+CONFIG_VIDEO_CX88_DVB=m
+CONFIG_VIDEO_CX88_ENABLE_VP3054=y
+CONFIG_VIDEO_CX88=m
+CONFIG_VIDEO_CX88_MPEG=m
+CONFIG_VIDEO_CX88_VP3054=m
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_DS90UB913=m
+CONFIG_VIDEO_DS90UB953=m
+CONFIG_VIDEO_DS90UB960=m
+CONFIG_VIDEO_DT3155=m
+CONFIG_VIDEO_DW9714=m
+CONFIG_VIDEO_DW9719=m
+CONFIG_VIDEO_DW9768=m
+CONFIG_VIDEO_DW9807_VCM=m
+CONFIG_VIDEO_E5010_JPEG_ENC=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_RC=m
+CONFIG_VIDEO_EM28XX_V4L2=m
+CONFIG_VIDEO_ET8EK8=m
+CONFIG_VIDEO_FB_IVTV=m
+CONFIG_VIDEO_GC0308=m
+CONFIG_VIDEO_GC0310=m
+CONFIG_VIDEO_GC05A2=m
+CONFIG_VIDEO_GC08A3=m
+CONFIG_VIDEO_GC2145=m
+CONFIG_VIDEO_GO7007_LOADER=m
+CONFIG_VIDEO_GO7007=m
+CONFIG_VIDEO_GO7007_USB=m
+CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_HEXIUM_GEMINI=m
+CONFIG_VIDEO_HEXIUM_ORION=m
+CONFIG_VIDEO_HI556=m
+CONFIG_VIDEO_HI846=m
+CONFIG_VIDEO_HI847=m
+CONFIG_VIDEO_IMX208=m
+CONFIG_VIDEO_IMX214=m
+CONFIG_VIDEO_IMX219=m
+CONFIG_VIDEO_IMX258=m
+CONFIG_VIDEO_IMX274=m
+CONFIG_VIDEO_IMX283=m
+CONFIG_VIDEO_IMX290=m
+CONFIG_VIDEO_IMX296=m
+CONFIG_VIDEO_IMX319=m
+CONFIG_VIDEO_IMX355=m
+CONFIG_VIDEO_INTEL_IPU7=m
+CONFIG_VIDEO_IPU3_CIO2=m
+CONFIG_VIDEO_IPU3_IMGU=m
+CONFIG_VIDEO_IR_I2C=m
+CONFIG_VIDEO_IVTV_ALSA=m
+CONFIG_VIDEO_IVTV=m
+CONFIG_VIDEO_KS0127=m
+CONFIG_VIDEO_LM3560=m
+CONFIG_VIDEO_LM3646=m
+CONFIG_VIDEO_M52790=m
+CONFIG_VIDEO_MAX9271_LIB=m
+CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
+CONFIG_VIDEO_MGB4=m
+CONFIG_VIDEO_MMP_CAMERA=m
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_MT9M001=m
+CONFIG_VIDEO_MT9M111=m
+CONFIG_VIDEO_MT9M114=m
+CONFIG_VIDEO_MT9P031=m
+CONFIG_VIDEO_MT9T112=m
+CONFIG_VIDEO_MT9V011=m
+CONFIG_VIDEO_MT9V032=m
+CONFIG_VIDEO_MT9V111=m
+CONFIG_VIDEO_MXB=m
+CONFIG_VIDEO_NOMODESET=y
+CONFIG_VIDEO_OG01A1B=m
+CONFIG_VIDEO_OG0VE1B=m
+CONFIG_VIDEO_OV01A10=m
+CONFIG_VIDEO_OV02A10=m
+CONFIG_VIDEO_OV08D10=m
+CONFIG_VIDEO_OV08X40=m
+CONFIG_VIDEO_OV13858=m
+CONFIG_VIDEO_OV13B10=m
+CONFIG_VIDEO_OV2640=m
+CONFIG_VIDEO_OV2659=m
+CONFIG_VIDEO_OV2680=m
+CONFIG_VIDEO_OV2685=m
+CONFIG_VIDEO_OV2735=m
+CONFIG_VIDEO_OV2740=m
+CONFIG_VIDEO_OV4689=m
+CONFIG_VIDEO_OV5647=m
+CONFIG_VIDEO_OV5648=m
+CONFIG_VIDEO_OV5670=m
+CONFIG_VIDEO_OV5675=m
+CONFIG_VIDEO_OV5693=m
+CONFIG_VIDEO_OV5695=m
+CONFIG_VIDEO_OV6211=m
+CONFIG_VIDEO_OV64A40=m
+CONFIG_VIDEO_OV6650=m
+CONFIG_VIDEO_OV7251=m
+CONFIG_VIDEO_OV7640=m
+CONFIG_VIDEO_OV7670=m
+CONFIG_VIDEO_OV772X=m
+CONFIG_VIDEO_OV7740=m
+CONFIG_VIDEO_OV8856=m
+CONFIG_VIDEO_OV8858=m
+CONFIG_VIDEO_OV8865=m
+CONFIG_VIDEO_OV9640=m
+CONFIG_VIDEO_OV9650=m
+CONFIG_VIDEO_OV9734=m
+CONFIG_VIDEO_PVRUSB2_DVB=y
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m
+CONFIG_VIDEO_RDACM20=m
+CONFIG_VIDEO_RDACM21=m
+CONFIG_VIDEO_RJ54N1=m
+CONFIG_VIDEO_S5C73M3=m
+CONFIG_VIDEO_S5K5BAF=m
+CONFIG_VIDEO_S5K6A3=m
+CONFIG_VIDEO_SAA6588=m
+CONFIG_VIDEO_SAA6752HS=m
+CONFIG_VIDEO_SAA7110=m
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_SAA7127=m
+CONFIG_VIDEO_SAA7134_ALSA=m
+CONFIG_VIDEO_SAA7134_DVB=m
+CONFIG_VIDEO_SAA7134_GO7007=m
+CONFIG_VIDEO_SAA7134=m
+CONFIG_VIDEO_SAA7134_RC=y
+CONFIG_VIDEO_SAA7146=m
+CONFIG_VIDEO_SAA7146_VV=m
+CONFIG_VIDEO_SAA7164=m
+CONFIG_VIDEO_SAA717X=m
+CONFIG_VIDEO_SAA7185=m
+CONFIG_VIDEO_SOLO6X10=m
+CONFIG_VIDEO_SONY_BTF_MPX=m
+CONFIG_VIDEO_STK1160=m
+CONFIG_VIDEO_TC358746=m
+CONFIG_VIDEO_TDA7432=m
+CONFIG_VIDEO_TDA9840=m
+CONFIG_VIDEO_TEA6415C=m
+CONFIG_VIDEO_TEA6420=m
+CONFIG_VIDEO_THP7312=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_TVAUDIO=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TVP5150=m
+CONFIG_VIDEO_TW2804=m
+CONFIG_VIDEO_TW5864=m
+CONFIG_VIDEO_TW686X=m
+CONFIG_VIDEO_TW68=m
+CONFIG_VIDEO_TW9900=m
+CONFIG_VIDEO_TW9903=m
+CONFIG_VIDEO_TW9906=m
+CONFIG_VIDEO_UDA1342=m
+CONFIG_VIDEO_UPD64031A=m
+CONFIG_VIDEO_UPD64083=m
+CONFIG_VIDEO_USBTV=m
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_VIDEO_VIA_CAMERA=m
+CONFIG_VIDEO_VP27SMPX=m
+CONFIG_VIDEO_VPX3220=m
+CONFIG_VIDEO_WM8739=m
+CONFIG_VIDEO_WM8775=m
+CONFIG_VIDEO_ZORAN_AVS6EYES=y
+CONFIG_VIDEO_ZORAN_BUZ=y
+CONFIG_VIDEO_ZORAN_DC10=y
+CONFIG_VIDEO_ZORAN_DC30=y
+CONFIG_VIDEO_ZORAN_LML33R10=y
+CONFIG_VIDEO_ZORAN_LML33=y
+CONFIG_VIDEO_ZORAN=m
+CONFIG_VIDEO_ZORAN_ZR36060=y
+CONFIG_VIPERBOARD_ADC=m
+CONFIG_VIRT_DRIVERS=y
+CONFIG_VIRTIO_ANCHOR=y
+CONFIG_VIRTIO_BALLOON=m
+CONFIG_VIRTIO_BLK=m
+CONFIG_VIRTIO_CONSOLE=m
+CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
+CONFIG_VIRTIO_INPUT=m
+CONFIG_VIRTIO_IOMMU=m
+CONFIG_VIRTIO=m
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_VIRTIO_MMIO=m
+CONFIG_VIRTIO_NET=m
+CONFIG_VIRTIO_PCI_LIB_LEGACY=m
+CONFIG_VIRTIO_PCI_LIB=m
+CONFIG_VIRTIO_PCI=m
+CONFIG_VIRTIO_PMEM=m
+CONFIG_VIRTIO_VDPA=m
+CONFIG_VIRTIO_VFIO_PCI=m
+CONFIG_VIRTUALIZATION=y
+CONFIG_VIRT_WIFI=m
+CONFIG_VITESSE_PHY=m
+CONFIG_VL53L0X_I2C=m
+CONFIG_VL6180=m
+CONFIG_VM86=y
+CONFIG_VMAP_PFN=y
+CONFIG_VME_BUS=y
+CONFIG_VME_FAKE=m
+CONFIG_VME_TSI148=m
+CONFIG_VME_USER=m
+CONFIG_VMGENID=m
+CONFIG_VMSPLIT_3G=y
+CONFIG_VMWARE_BALLOON=m
+CONFIG_VMWARE_PVSCSI=m
+CONFIG_VMWARE_VMCI=m
+CONFIG_VMXNET3=m
+CONFIG_VP_VDPA=m
+CONFIG_VSOCKMON=m
+CONFIG_VT6655=m
+CONFIG_VT6656=m
+CONFIG_VXLAN=m
+CONFIG_VZ89X=m
+CONFIG_W1_CON=y
+CONFIG_W1=m
+CONFIG_W1_MASTER_AMD_AXI=m
+CONFIG_W1_MASTER_DS2482=m
+CONFIG_W1_MASTER_DS2490=m
+CONFIG_W1_MASTER_GPIO=m
+CONFIG_W1_MASTER_MATROX=m
+CONFIG_W1_MASTER_SGI=m
+CONFIG_W1_MASTER_UART=m
+CONFIG_W1_SLAVE_DS2406=m
+CONFIG_W1_SLAVE_DS2408=m
+CONFIG_W1_SLAVE_DS2413=m
+CONFIG_W1_SLAVE_DS2423=m
+CONFIG_W1_SLAVE_DS2430=m
+CONFIG_W1_SLAVE_DS2431=m
+CONFIG_W1_SLAVE_DS2433_CRC=y
+CONFIG_W1_SLAVE_DS2433=m
+CONFIG_W1_SLAVE_DS2438=m
+CONFIG_W1_SLAVE_DS250X=m
+CONFIG_W1_SLAVE_DS2780=m
+CONFIG_W1_SLAVE_DS2781=m
+CONFIG_W1_SLAVE_DS2805=m
+CONFIG_W1_SLAVE_DS28E04=m
+CONFIG_W1_SLAVE_DS28E17=m
+CONFIG_W1_SLAVE_SMEM=m
+CONFIG_W1_SLAVE_THERM=m
+CONFIG_W83627HF_WDT=m
+CONFIG_W83877F_WDT=m
+CONFIG_W83977F_WDT=m
+CONFIG_WAFER_WDT=m
+CONFIG_WANT_DEV_COREDUMP=y
+CONFIG_WANXL=m
+CONFIG_WAN=y
+CONFIG_WATCHDOG_CORE=m
+CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=0
+CONFIG_WATCHDOG=y
+CONFIG_WCN36XX=m
+CONFIG_WDAT_WDT=m
+CONFIG_WDTPCI=m
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PRIV=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_WFX=m
+CONFIG_WIL6210_DEBUGFS=y
+CONFIG_WIL6210_ISR_COR=y
+CONFIG_WIL6210=m
+CONFIG_WILC1000=m
+CONFIG_WILC1000_SDIO=m
+CONFIG_WILC1000_SPI=m
+CONFIG_WILCO_EC_DEBUGFS=m
+CONFIG_WILCO_EC_EVENTS=m
+CONFIG_WILCO_EC=m
+CONFIG_WILCO_EC_TELEMETRY=m
+CONFIG_WINMATE_FM07_KEYS=m
+CONFIG_WIREGUARD=m
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_HOTKEY=m
+CONFIG_WL1251=m
+CONFIG_WL1251_SDIO=m
+CONFIG_WL1251_SPI=m
+CONFIG_WL12XX=m
+CONFIG_WL18XX=m
+CONFIG_WLAN_VENDOR_CISCO=y
+CONFIG_WLCORE=m
+CONFIG_WLCORE_SDIO=m
+CONFIG_WM831X_BACKUP=m
+CONFIG_WM831X_POWER=m
+CONFIG_WM831X_WATCHDOG=m
+CONFIG_WMI_BMOF=m
+CONFIG_WPCM450_SOC=m
+CONFIG_WWAN_HWSIM=m
+CONFIG_WWAN=y
+CONFIG_X86_16BIT=y
+CONFIG_X86_32_IRIS=m
+CONFIG_X86_32_SMP=y
+CONFIG_X86_32=y
+CONFIG_X86_ACPI_CPUFREQ_CPB=y
+CONFIG_X86_ACPI_CPUFREQ=m
+CONFIG_X86_AMD_FREQ_SENSITIVITY=m
+CONFIG_X86_AMD_PLATFORM_DEVICE=y
+CONFIG_X86_AMD_PSTATE_DEFAULT_MODE=3
+CONFIG_X86_AMD_PSTATE_UT=m
+CONFIG_X86_AMD_PSTATE=y
+CONFIG_X86_ANCIENT_MCE=y
+CONFIG_X86_ANDROID_TABLETS=m
+CONFIG_X86_APM_BOOT=y
+CONFIG_X86_BIGSMP=y
+CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y
+CONFIG_X86_CHECK_BIOS_CORRUPTION=y
+CONFIG_X86_CMOV=y
+CONFIG_X86_CMPXCHG64=y
+CONFIG_X86_CPUFREQ_NFORCE2=m
+CONFIG_X86_CPUID=m
+CONFIG_X86_CPU_RESCTRL=y
+CONFIG_X86_DEBUGCTLMSR=y
+CONFIG_X86_E_POWERSAVER=m
+CONFIG_X86_ESPFIX32=y
+CONFIG_X86_GENERIC=y
+CONFIG_X86_GX_SUSPMOD=m
+CONFIG_X86_HV_CALLBACK_VECTOR=y
+CONFIG_X86_INTEL_LPSS=y
+CONFIG_X86_INTEL_PSTATE=y
+CONFIG_X86_INTEL_TSX_MODE_OFF=y
+CONFIG_X86_INTEL_USERCOPY=y
+CONFIG_X86_INTERNODE_CACHE_SHIFT=6
+CONFIG_X86_IO_APIC=y
+CONFIG_X86_IOPL_IOPERM=y
+CONFIG_X86_L1_CACHE_SHIFT=6
+CONFIG_X86_LEGACY_VM86=y
+CONFIG_X86_LOCAL_APIC=y
+CONFIG_X86_LONGHAUL=m
+CONFIG_X86_LONGRUN=m
+CONFIG_X86_MCE_AMD=y
+CONFIG_X86_MCE_INTEL=y
+CONFIG_X86_MCE_THRESHOLD=y
+CONFIG_X86_MCE=y
+CONFIG_X86_MINIMUM_CPU_FAMILY=6
+CONFIG_X86_MPPARSE=y
+CONFIG_X86_MSR=m
+CONFIG_X86_NEED_RELOCS=y
+CONFIG_X86_PAE=y
+CONFIG_X86_PAT=y
+CONFIG_X86_PCC_CPUFREQ=m
+CONFIG_X86_PKG_TEMP_THERMAL=m
+CONFIG_X86_PLATFORM_DEVICES=y
+CONFIG_X86_PLATFORM_DRIVERS_DELL=y
+CONFIG_X86_PLATFORM_DRIVERS_HP=y
+CONFIG_X86_PMEM_LEGACY_DEVICE=y
+CONFIG_X86_PMEM_LEGACY=m
+CONFIG_X86_PM_TIMER=y
+CONFIG_X86_POWERNOW_K6=m
+CONFIG_X86_POWERNOW_K7_ACPI=y
+CONFIG_X86_POWERNOW_K7=m
+CONFIG_X86_POWERNOW_K8=m
+CONFIG_X86_REBOOTFIXUPS=y
+CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
+CONFIG_X86_SPEEDSTEP_ICH=m
+CONFIG_X86_SPEEDSTEP_LIB=m
+CONFIG_X86_SPEEDSTEP_SMI=m
+CONFIG_X86_THERMAL_VECTOR=y
+CONFIG_X86_TSC=y
+CONFIG_X86_UMIP=y
+CONFIG_X86_USE_PPRO_CHECKSUM=y
 CONFIG_X86_VERBOSE_BOOTUP=y
-# CONFIG_EARLY_PRINTK is not set
-# CONFIG_EARLY_PRINTK_DBGP is not set
-# CONFIG_EARLY_PRINTK_USB_XDBC is not set
-# CONFIG_EFI_PGT_DUMP is not set
-# CONFIG_DEBUG_TLBFLUSH is not set
-CONFIG_HAVE_MMIOTRACE_SUPPORT=y
-# CONFIG_X86_DECODER_SELFTEST is not set
-CONFIG_IO_DELAY_0X80=y
-# CONFIG_IO_DELAY_0XED is not set
-# CONFIG_IO_DELAY_UDELAY is not set
-# CONFIG_IO_DELAY_NONE is not set
-# CONFIG_DEBUG_BOOT_PARAMS is not set
-# CONFIG_CPA_DEBUG is not set
-# CONFIG_DEBUG_ENTRY is not set
-# CONFIG_DEBUG_NMI_SELFTEST is not set
-# CONFIG_X86_DEBUG_FPU is not set
-# CONFIG_PUNIT_ATOM_DEBUG is not set
-CONFIG_UNWINDER_FRAME_POINTER=y
-# CONFIG_UNWINDER_GUESS is not set
-# end of x86 Debugging
-
-#
-# Kernel Testing and Coverage
-#
-# CONFIG_KUNIT is not set
-# CONFIG_NOTIFIER_ERROR_INJECTION is not set
-CONFIG_FUNCTION_ERROR_INJECTION=y
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_MEMTEST=y
-# CONFIG_HYPERV_TESTING is not set
-# end of Kernel Testing and Coverage
-# end of Kernel hacking
-CONFIG_SURFACE_PLATFORMS=y
-CONFIG_SURFACE_GPE=m
-CONFIG_SURFACE_HOTPLUG=m
-CONFIG_SURFACE_PLATFORM_PROFILE=m
-CONFIG_SURFACE_AGGREGATOR=m
-CONFIG_SURFACE_AGGREGATOR_BUS=y
-# CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION is not set
-CONFIG_LITEX_SOC_CONTROLLER=m
-CONFIG_LITEX_SUBREG_SIZE=4
-# CONFIG_KFENCE is not set
-
-# CONFIG_WERROR is not set
-CONFIG_PRINTK_INDEX=y
-CONFIG_SOC_SAMA7G5=y
-CONFIG_SOC_LAN966=y
-CONFIG_DAMON=y
-CONFIG_DAMON_SYSFS=y
-CONFIG_DAMON_VADDR=y
-CONFIG_DAMON_PADDR=y
-CONFIG_DAMON_DBGFS=y
-CONFIG_DAMON_RECLAIM=y
-CONFIG_IPV6_IOAM6_LWTUNNEL=y
-CONFIG_NETFILTER_EGRESS=y
-CONFIG_MCTP=y
-CONFIG_PCIE_QCOM_EP=m
-CONFIG_PCIE_ROCKCHIP_DW_HOST=y
-CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
-CONFIG_ARM_SCMI_TRANSPORT_SMC=y
-# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
-CONFIG_HI6421V600_IRQ=m
-CONFIG_SCSI_UFS_HPB=y
-CONFIG_SCSI_UFS_HWMON=y
-CONFIG_AMT=m
-CONFIG_NET_VENDOR_ASIX=y
-CONFIG_SPI_AX88796C=m
-CONFIG_SPI_AX88796C_COMPRESSION=y
-CONFIG_CS89x0_PLATFORM=m
-CONFIG_ICE_SWITCHDEV=y
-CONFIG_ICE_HWTS=y
-CONFIG_NET_VENDOR_LITEX=y
-CONFIG_LITEX_LITEETH=m
-CONFIG_MAXLINEAR_GPHY=m
-CONFIG_MT7921S=m
-CONFIG_MT7921U=m
-CONFIG_RTW89=m
-CONFIG_RTW89_8852AE=m
-# CONFIG_RTW89_DEBUGMSG is not set
-CONFIG_RTW89_DEBUGFS=y
-CONFIG_MHI_WWAN_MBIM=m
-CONFIG_QCOM_BAM_DMUX=m
-CONFIG_KEYBOARD_CYPRESS_SF=m
-CONFIG_RPMSG_TTY=m
-CONFIG_IPMI_IPMB=m
-CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
-CONFIG_HW_RANDOM_CN10K=m
-CONFIG_I2C_VIRTIO=m
-CONFIG_SPI_CADENCE_XSPI=m
-CONFIG_SPI_ROCKCHIP_SFC=m
-CONFIG_PINCTRL_IMX8ULP=m
-CONFIG_PINCTRL_MDM9607=m
-CONFIG_PINCTRL_QCM2290=m
-CONFIG_PINCTRL_SM6115=m
-CONFIG_PINCTRL_SM6350=m
-CONFIG_PINCTRL_UNIPHIER_NX1=y
-CONFIG_GPIO_ROCKCHIP=m
-CONFIG_GPIO_VIRTIO=m
-CONFIG_POWER_RESET_TPS65086=y
-CONFIG_CHARGER_MT6360=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_CHARGER_CROS_PCHG=m
-CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m
-CONFIG_SENSORS_MAX6620=m
-CONFIG_SENSORS_SBRMI=m
-CONFIG_QCOM_LMH=m
-CONFIG_DB500_WATCHDOG=m
-CONFIG_MFD_RSMU_I2C=m
-CONFIG_MFD_RSMU_SPI=m
-CONFIG_REGULATOR_RTQ2134=m
-CONFIG_REGULATOR_RTQ6752=m
-CONFIG_IR_MESON_TX=m
-CONFIG_VIDEO_RCAR_ISP=m
-# CONFIG_VIDEO_ROCKCHIP_IEP is not set
-CONFIG_VIDEO_STKWEBCAM=m
-CONFIG_VIDEO_HI846=m
-CONFIG_VIDEO_HI847=m
-CONFIG_VIDEO_IMX335=m
-CONFIG_VIDEO_IMX412=m
-CONFIG_VIDEO_OV9282=m
-CONFIG_VIDEO_OV13B10=m
-# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
-CONFIG_DRM_PANEL_EDP=m
-CONFIG_DRM_PANEL_ILITEK_ILI9341=m
-CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
-CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
-CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
-CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
-CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
-CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
-CONFIG_SND_HDA_CODEC_CS8409=m
-CONFIG_SND_SOC_MT8195=m
-CONFIG_SND_SOC_CS35L41_SPI=m
-CONFIG_SND_SOC_CS35L41_I2C=m
-CONFIG_SND_SOC_ICS43432=m
-CONFIG_SND_SOC_MAX98520=m
-CONFIG_SND_SOC_RT9120=m
-CONFIG_SND_SOC_SDW_MOCKUP=m
-CONFIG_SND_SOC_NAU8821=m
-CONFIG_SND_AUDIO_GRAPH_CARD2=m
-CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
-CONFIG_SND_TEST_COMPONENT=m
-CONFIG_HID_XIAOMI=m
-CONFIG_HID_NINTENDO=m
-CONFIG_NINTENDO_FF=y
-CONFIG_RTC_DRV_MSC313=m
-# CONFIG_DMABUF_SYSFS_STATS is not set
-CONFIG_VDPA_USER=m
-CONFIG_COMMON_CLK_XLNX_CLKWZRD=m
-CONFIG_CLK_IMX8ULP=m
-CONFIG_CLK_IMX93=m
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_ASPEED_UART_ROUTING=m
-CONFIG_QCOM_SPM=m
-CONFIG_ADXL313_I2C=m
-CONFIG_ADXL313_SPI=m
-CONFIG_ADXL355_I2C=m
-CONFIG_ADXL355_SPI=m
-CONFIG_ADXL367_SPI=m
-CONFIG_ADXL367_I2C=m
-CONFIG_SCD4X=m
-CONFIG_SENSIRION_SGP40=m
-CONFIG_SENSEAIR_SUNRISE_CO2=m
-CONFIG_ADRF6780=m
-CONFIG_AD5110=m
-CONFIG_MAX31865=m
-CONFIG_MCHP_EIC=y
-# CONFIG_F2FS_IOSTAT is not set
-# CONFIG_F2FS_UNFAIR_RWSEM is not set
-CONFIG_SMB_SERVER=m
-CONFIG_SMB_SERVER_SMBDIRECT=y
-CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
-CONFIG_SMB_SERVER_KERBEROS5=y
-# CONFIG_ZERO_CALL_USED_REGS is not set
+CONFIG_X86_VMX_FEATURE_NAMES=y
+CONFIG_X86=y
+CONFIG_X9250=m
+CONFIG_XARRAY_MULTI=y
+CONFIG_XIAOMI_WMI=m
+CONFIG_XILINX_DMA=m
+CONFIG_XILINX_GMII2RGMII=m
+CONFIG_XILINX_PR_DECOUPLER=m
+CONFIG_XILINX_SDFEC=m
+CONFIG_XILINX_WATCHDOG=m
+CONFIG_XILINX_XADC=m
+CONFIG_XILINX_XDMA=m
+CONFIG_XILLYBUS_CLASS=m
+CONFIG_XILLYBUS=m
+CONFIG_XILLYBUS_PCIE=m
+CONFIG_XILLYUSB=m
+CONFIG_XOR_BLOCKS=m
+CONFIG_XZ_DEC_IA64=y
 CONFIG_XZ_DEC_MICROLZMA=y
-CONFIG_DMA_RESTRICTED_POOL=y
-# CONFIG_ANON_VMA_NAME is not set
-CONFIG_NET_9P_FD=m
-CONFIG_DEVTMPFS_SAFE=y
-CONFIG_GNSS_USB=m
-CONFIG_MTD_NAND_RENESAS=m
-CONFIG_NET_VENDOR_ENGLEDER=y
-CONFIG_TSNEP=m
-# CONFIG_TSNEP_SELFTESTS is not set
-CONFIG_LAN966X_SWITCH=m
-CONFIG_NET_VENDOR_VERTEXCOM=y
-CONFIG_MSE102X=m
-CONFIG_MCTP_SERIAL=m
-CONFIG_MCTP_TRANSPORT_I2C=m
-# CONFIG_WWAN_DEBUGFS is not set
-CONFIG_SERIAL_8250_PERICOM=m
-CONFIG_SPMI_MTK_PMIF=m
-CONFIG_PINCTRL_IMXRT1050=y
-CONFIG_PINCTRL_IMX93=m
-CONFIG_PINCTRL_SDX65=m
-CONFIG_PINCTRL_SM8450=m
-CONFIG_PINCTRL_SM8450_LPASS_LPI=m
-CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
-CONFIG_PINCTRL_SM8280XP_LPASS_LPI=m
-CONFIG_GPIO_SIM=m
-CONFIG_CHARGER_MAX77976=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_SENSORS_NZXT_SMART2=m
-CONFIG_SENSORS_DELTA_AHE50DC_FAN=m
-CONFIG_SENSORS_IR38064_REGULATOR=y
-CONFIG_SENSORS_MP5023=m
-CONFIG_SENSORS_INA238=m
-CONFIG_RZG2L_THERMAL=m
-CONFIG_RENESAS_RZG2LWDT=m
-CONFIG_REGULATOR_MAX20086=m
-CONFIG_VIDEO_STM32_DMA2D=m
-CONFIG_VIDEO_OV5693=m
-CONFIG_DRM_RCAR_USE_LVDS=y
-CONFIG_DRM_RCAR_USE_MIPI_DSI=y
-CONFIG_DRM_RCAR_MIPI_DSI=m
-CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
-CONFIG_DRM_PANEL_JDI_R63452=m
-CONFIG_DRM_PANEL_NOVATEK_NT35950=m
-CONFIG_DRM_PANEL_NOVATEK_NT35560=m
-CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
-CONFIG_TINYDRM_ILI9163=m
-CONFIG_SND_AMD_ACP_CONFIG=m
-CONFIG_SND_SOC_APPLE_MCA=m
-CONFIG_SND_SOC_AK4375=m
-CONFIG_SND_SOC_TLV320ADC3XXX=m
-CONFIG_HID_LETSKETCH=m
-CONFIG_LEDS_MT6360=m
-CONFIG_VIDEO_MAX96712=m
-CONFIG_COMMON_CLK_LAN966X=y
-CONFIG_COMMON_CLK_MT7986=y
-CONFIG_COMMON_CLK_MT7986_ETHSYS=y
-CONFIG_RENESAS_OSTM=y
-CONFIG_EXYNOS_USI=m
-CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
-CONFIG_AD74413R=m
-CONFIG_AD3552R=m
-CONFIG_AD7293=m
-CONFIG_ADMV1013=m
-CONFIG_ADMV1014=m
-CONFIG_ADMV4420=m
-CONFIG_PHY_MESON8_HDMI_TX=m
-CONFIG_PHY_FSL_IMX8M_PCIE=m
-CONFIG_PHY_FSL_LYNX_28G=m
-CONFIG_PHY_LAN966X_SERDES=m
-CONFIG_PHY_QCOM_EDP=m
-# CONFIG_CACHEFILES_ERROR_INJECTION is not set
-CONFIG_UNICODE_UTF8_DATA=m
-# CONFIG_NET_DEV_REFCNT_TRACKER is not set
-# CONFIG_NET_NS_REFCNT_TRACKER is not set
-# CONFIG_KFENCE is not set
-# CONFIG_FTRACE_SORT_STARTUP_TEST is not set
-CONFIG_BACKTRACE_VERBOSE=y
-CONFIG_ADMV8818=m
-CONFIG_MARVELL_CN10K_TAD_PMU=m
-# CONFIG_KCSAN is not set
-# CONFIG_BOOT_CONFIG_EMBED is not set
-CONFIG_INITRAMFS_PRESERVE_MTIME=y
-CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y
-CONFIG_ARCH_BCMBCA=y
-CONFIG_ARCH_HPE=y
-CONFIG_ARCH_HPE_GXP=y
-CONFIG_ARM_ERRATA_764319=y
-# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
-CONFIG_CAN_CTUCANFD_PCI=m
-CONFIG_CAN_CTUCANFD_PLATFORM=m
-CONFIG_FW_LOADER_COMPRESS_XZ=y
-CONFIG_FW_LOADER_COMPRESS_ZSTD=y
-CONFIG_FW_UPLOAD=y
-CONFIG_QCOM_SSC_BLOCK_BUS=y
-CONFIG_MHI_BUS_EP=m
-CONFIG_MTK_ADSP_IPC=m
-CONFIG_EFI_COCO_SECRET=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=m
-CONFIG_SFC_SIENA=m
-CONFIG_SFC_SIENA_MTD=y
-CONFIG_SFC_SIENA_MCDI_MON=y
-CONFIG_SFC_SIENA_SRIOV=y
-# CONFIG_SFC_SIENA_MCDI_LOGGING is not set
-CONFIG_ADIN1100_PHY=m
-CONFIG_DP83TD510_PHY=m
-CONFIG_WLAN_VENDOR_PURELIFI=y
-CONFIG_PLFXLC=m
-CONFIG_RTW89_8852CE=m
-CONFIG_WLAN_VENDOR_SILABS=y
-CONFIG_MTK_T7XX=m
-CONFIG_JOYSTICK_SENSEHAT=m
-CONFIG_INPUT_IQS7222=m
-# CONFIG_HVC_DCC_SERIALIZE_SMP is not set
-CONFIG_SPI_MTK_SNFI=m
-CONFIG_PINCTRL_IMXRT1170=y
-CONFIG_PINCTRL_SC7280_LPASS_LPI=m
-CONFIG_PINCTRL_SM8250_LPASS_LPI=m
-CONFIG_SENSORS_LAN966X=m
-CONFIG_SENSORS_NCT6775_I2C=m
-CONFIG_SENSORS_XDPE152=m
-CONFIG_RENESAS_RZN1WDT=m
-CONFIG_GXP_WATCHDOG=m
-CONFIG_REGULATOR_RT5759=m
-CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
-CONFIG_DRM_FSL_LDB=m
-CONFIG_DRM_LONTIUM_LT9211=m
-CONFIG_DRM_DW_HDMI_GP_AUDIO=m
-CONFIG_DRM_SSD130X_SPI=m
-CONFIG_SND_SERIAL_GENERIC=m
-CONFIG_SND_SOC_CS35L45_SPI=m
-CONFIG_SND_SOC_CS35L45_I2C=m
-CONFIG_SND_SOC_MAX98396=m
-CONFIG_SND_SOC_WM8731_I2C=m
-CONFIG_SND_SOC_WM8731_SPI=m
-CONFIG_SND_SOC_WM8940=m
-CONFIG_HID_MEGAWORLD_FF=m
-CONFIG_TYPEC_MUX_FSA4480=m
-CONFIG_LEDS_PWM_MULTICOLOR=m
-CONFIG_LEDS_QCOM_LPG=m
-CONFIG_TEGRA186_GPC_DMA=m
-# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set
-CONFIG_PWM_XILINX=m
-CONFIG_HTE=y
-# CONFIG_CACHEFILES_ONDEMAND is not set
-CONFIG_TRUSTED_KEYS_TPM=y
-CONFIG_TRUSTED_KEYS_TEE=y
-CONFIG_CRYPTO_SM3_GENERIC=m
-CONFIG_CRYPTO_SM4_GENERIC=m
-# CONFIG_FIPS_SIGNATURE_SELFTEST is not set
-CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y
-# CONFIG_DEBUG_NET is not set
-CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
-CONFIG_SPECULATION_MITIGATIONS=y
-CONFIG_EFI_DXE_MEM_ATTRIBUTES=y
-CONFIG_INTEL_MEI_GSC=m
-CONFIG_PINCTRL_AMD=y
-CONFIG_WINMATE_FM07_KEYS=m
-CONFIG_CHROMEOS_ACPI=m
-CONFIG_NVSW_SN2201=m
-CONFIG_DMARD06=m
-CONFIG_IIO_RESCALE=m
-CONFIG_DPOT_DAC=m
-CONFIG_VF610_DAC=m
-CONFIG_CM3605=m
-CONFIG_AK8974=m
-CONFIG_IIO_MUX=m
-# CONFIG_CGROUP_FAVOR_DYNMODS is not set
-CONFIG_ARCH_BCMBCA_CORTEXA7=y
-CONFIG_ARCH_BCMBCA_CORTEXA9=y
-CONFIG_ARCH_BCMBCA_BRAHMAB15=y
-CONFIG_ARCH_MSM8909=y
-CONFIG_ARCH_SUNPLUS=y
-CONFIG_SOC_SP7021=y
-# CONFIG_UNUSED_BOARD_FILES is not set
-# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
-CONFIG_DAMON_LRU_SORT=y
-CONFIG_NF_FLOW_TABLE_PROCFS=y
-CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
-CONFIG_PCI_EPF_VNTB=m
-CONFIG_ARM_SCMI_POWER_CONTROL=m
-CONFIG_BLK_DEV_UBLK=m
-CONFIG_NVME_AUTH=y
-CONFIG_NVME_TARGET_AUTH=y
-CONFIG_VCPU_STALL_DETECTOR=m
-CONFIG_SCSI_BUSLOGIC=m
-CONFIG_SCSI_FLASHPOINT=y
-CONFIG_AHCI_BRCM=m
-CONFIG_AHCI_DWC=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
-CONFIG_NET_VENDOR_WANGXUN=y
-CONFIG_NET_VENDOR_ADI=y
-CONFIG_ADIN1110=m
-CONFIG_NGBE=m
-CONFIG_TXGBE=m
-CONFIG_NET_VENDOR_SUNPLUS=y
-CONFIG_SP7021_EMAC=m
-CONFIG_CAN_NETLINK=y
-CONFIG_CAN_CAN327=m
-CONFIG_CAN_ESD_USB=m
-CONFIG_HW_RANDOM_BCM2835=m
-CONFIG_TCG_TIS_I2C=m
-# CONFIG_RANDOM_TRUST_CPU is not set
-CONFIG_I2C_BRCMSTB=m
-CONFIG_I2C_NPCM=m
-CONFIG_I2C_RZV2M=m
-CONFIG_SPI_BCM63XX_HSSPI=m
-CONFIG_SPI_GXP=m
-CONFIG_SPI_MICROCHIP_CORE=m
-CONFIG_SPI_MICROCHIP_CORE_QSPI=m
-CONFIG_SPI_SUNPLUS_SP7021=m
-CONFIG_PINCTRL_MSM8909=m
-CONFIG_PINCTRL_SM6375=m
-CONFIG_PINCTRL_SUN20I_D1=y
-CONFIG_SENSORS_LT7182S=m
-CONFIG_SUNPLUS_WATCHDOG=m
-CONFIG_VIDEO_SUN6I_MIPI_CSI2=m
-CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m
-CONFIG_VIDEO_AR0521=m
-CONFIG_DRM_PANEL_EBBG_FT8719=m
-CONFIG_DRM_TI_DLPC3433=m
-CONFIG_DRM_IMX8QM_LDB=m
-# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set
-CONFIG_RCU_NOCB_CPU_DEFAULT_ALL=y
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-# CONFIG_RV is not set
-CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT274=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT286=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT298=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567=m
-CONFIG_ANDROID_BINDER_IPC=m
-CONFIG_ANDROID_BINDERFS=y
-CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
-# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
-CONFIG_RANDSTRUCT_NONE=y
-# CONFIG_RANDSTRUCT_FULL is not set
-# Ethernet Power Sourcing Equipment Support
-CONFIG_PSE_CONTROLLER=y
-CONFIG_PSE_REGULATOR=m
-CONFIG_STAGING_MEDIA_DEPRECATED=y
-# CONFIG_FORCE_NR_CPUS is not set
-# CONFIG_DEBUG_MAPLE_TREE is not set
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_KERNEL_ZSTD=y
-# CONFIG_KMSAN is not set
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_YAMAHA_YAS530=m
+CONFIG_YENTA_ENE_TUNE=y
+CONFIG_YENTA=m
+CONFIG_YENTA_O2=y
+CONFIG_YENTA_RICOH=y
+CONFIG_YENTA_TI=y
+CONFIG_YENTA_TOSHIBA=y
+CONFIG_YOGABOOK=m
+CONFIG_YT2_1380=m
+CONFIG_ZD1211RW=m
+CONFIG_ZIIRAVE_WATCHDOG=m
+CONFIG_ZL3073X_SPI=m
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZONE_DMA=y
+CONFIG_ZOPT2201=m
+CONFIG_ZPA2326_I2C=m
+CONFIG_ZPA2326=m
+CONFIG_ZPA2326_SPI=m
+CONFIG_ZPOOL=y
+CONFIG_ZRAM_DEF_COMP="zstd"
+CONFIG_ZRAM_MULTI_COMP=y
+CONFIG_ZRAM_TRACK_ENTRY_ACTIME=y
+CONFIG_ZRAM_WRITEBACK=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_NEXUS=m
diff --git a/i686-server-gcc-omv-defconfig b/i686-server-gcc-omv-defconfig
deleted file mode 100644
index 55cabac..0000000
--- a/i686-server-gcc-omv-defconfig
+++ /dev/null
@@ -1,11575 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# Linux/i386 5.10.0-rc1 Kernel Configuration
-#
-CONFIG_CC_VERSION_TEXT="gcc (GCC) 10.2.0 20200723 (OpenMandriva)"
-CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=100200
-CONFIG_LD_VERSION=235010000
-CONFIG_CLANG_VERSION=0
-CONFIG_CC_CAN_LINK=y
-CONFIG_CC_CAN_LINK_STATIC=y
-CONFIG_CC_HAS_ASM_GOTO=y
-CONFIG_CC_HAS_ASM_INLINE=y
-CONFIG_IRQ_WORK=y
-CONFIG_BUILDTIME_TABLE_SORT=y
-CONFIG_THREAD_INFO_IN_TASK=y
-
-#
-# General setup
-#
-CONFIG_INIT_ENV_ARG_LIMIT=32
-# CONFIG_COMPILE_TEST is not set
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_BUILD_SALT="446a9ec207f4ea875f9fa389eff48c51dfa904e7"
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_BZIP2=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_ZSTD=y
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_BZIP2 is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_KERNEL_ZSTD=y
-CONFIG_DEFAULT_INIT=""
-CONFIG_DEFAULT_HOSTNAME="omv"
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_POSIX_MQUEUE_SYSCTL=y
-# CONFIG_WATCH_QUEUE is not set
-CONFIG_CROSS_MEMORY_ATTACH=y
-# CONFIG_USELIB is not set
-# CONFIG_AUDIT is not set
-# CONFIG_HAVE_ARCH_AUDITSYSCALL is not set
-# CONFIG_AUDITSYSCALL is not set
-
-#
-# IRQ subsystem
-#
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_SIM=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
-CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_SPARSE_IRQ=y
-# CONFIG_GENERIC_IRQ_DEBUGFS is not set
-# end of IRQ subsystem
-
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-CONFIG_ARCH_CLOCKSOURCE_INIT=y
-CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-
-#
-# Timers subsystem
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ_COMMON=y
-# CONFIG_HZ_PERIODIC is not set
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
-# end of Timers subsystem
-
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-CONFIG_PREEMPT_DYNAMIC=y
-CONFIG_SCHED_CORE=y
-CONFIG_PREEMPT_DYNAMIC=y
-CONFIG_CPU_SUP_VORTEX_32=y
-
-#
-# CPU/Task time and stats accounting
-#
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_SCHED_AVG_IRQ=y
-CONFIG_BSD_PROCESS_ACCT=y
-# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_PSI=y
-# CONFIG_PSI_DEFAULT_DISABLED is not set
-# end of CPU/Task time and stats accounting
-
-CONFIG_CPU_ISOLATION=y
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_RCU_EXPERT is not set
-CONFIG_SRCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TASKS_RCU_GENERIC=y
-CONFIG_TASKS_RCU=y
-CONFIG_TASKS_RUDE_RCU=y
-CONFIG_TASKS_TRACE_RCU=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RCU_NEED_SEGCBLIST=y
-# end of RCU Subsystem
-
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-# CONFIG_IKHEADERS is not set
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
-CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
-CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
-
-#
-# Scheduler features
-#
-# CONFIG_UCLAMP_TASK is not set
-# end of Scheduler features
-
-CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
-CONFIG_CGROUPS=y
-CONFIG_PAGE_COUNTER=y
-CONFIG_MEMCG=y
-CONFIG_MEMCG_SWAP=y
-CONFIG_MEMCG_KMEM=y
-CONFIG_BLK_CGROUP=y
-CONFIG_CGROUP_WRITEBACK=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_CFS_BANDWIDTH=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_CGROUP_PIDS=y
-CONFIG_CGROUP_RDMA=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_HUGETLB=y
-CONFIG_CPUSETS=y
-CONFIG_PROC_PID_CPUSET=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_PERF=y
-CONFIG_CGROUP_BPF=y
-CONFIG_CGROUP_MISC=y
-# CONFIG_CGROUP_DEBUG is not set
-CONFIG_SOCK_CGROUP_DATA=y
-CONFIG_NAMESPACES=y
-CONFIG_UTS_NS=y
-CONFIG_TIME_NS=y
-CONFIG_IPC_NS=y
-CONFIG_USER_NS=y
-CONFIG_PID_NS=y
-CONFIG_NET_NS=y
-CONFIG_CHECKPOINT_RESTORE=y
-CONFIG_SCHED_AUTOGROUP=y
-# CONFIG_SYSFS_DEPRECATED is not set
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_XZ=y
-CONFIG_RD_LZO=y
-CONFIG_RD_LZ4=y
-CONFIG_RD_ZSTD=y
-CONFIG_BOOT_CONFIG=y
-# CONFIG_CC_OPTIMIZE_BASAL is not set
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_HAVE_UID16=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_HAVE_PCSPKR_PLATFORM=y
-CONFIG_BPF=y
-CONFIG_EXPERT=y
-CONFIG_UID16=y
-CONFIG_MULTIUSER=y
-CONFIG_SGETMASK_SYSCALL=y
-# CONFIG_SYSFS_SYSCALL is not set
-CONFIG_FHANDLE=y
-CONFIG_POSIX_TIMERS=y
-CONFIG_PRINTK=y
-CONFIG_PRINTK_NMI=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_PCSPKR_PLATFORM=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_FUTEX_PI=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_IO_URING=y
-CONFIG_ADVISE_SYSCALLS=y
-CONFIG_MEMBARRIER=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_BASE_RELATIVE=y
-CONFIG_BPF_SYSCALL=y
-CONFIG_BPF_JIT_ALWAYS_ON=y
-# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
-CONFIG_BPF_JIT_DEFAULT_ON=y
-CONFIG_USERMODE_DRIVER=y
-# CONFIG_BPF_PRELOAD is not set
-CONFIG_USERFAULTFD=y
-CONFIG_LRU_GEN=y
-CONFIG_LRU_GEN_ENABLED=y
-# CONFIG_LRU_GEN_STATS is not set
-CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
-CONFIG_RSEQ=y
-# CONFIG_DEBUG_RSEQ is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_HAVE_PERF_EVENTS=y
-# CONFIG_PC104 is not set
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_PERF_EVENTS=y
-# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
-# end of Kernel Performance Events And Counters
-
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_SLUB_MEMCG_SYSFS_ON is not set
-# CONFIG_COMPAT_BRK is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-CONFIG_SLAB_MERGE_DEFAULT=y
-CONFIG_SLAB_FREELIST_RANDOM=y
-CONFIG_SLAB_FREELIST_HARDENED=y
-CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
-CONFIG_SLUB_CPU_PARTIAL=y
-CONFIG_SYSTEM_DATA_VERIFICATION=y
-# CONFIG_PROFILING is not set
-CONFIG_TRACEPOINTS=y
-# end of General setup
-
-CONFIG_X86_32=y
-CONFIG_FORCE_DYNAMIC_FTRACE=y
-CONFIG_X86=y
-CONFIG_INSTRUCTION_DECODER=y
-CONFIG_OUTPUT_FORMAT="elf32-i386"
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_MMU=y
-CONFIG_ARCH_MMAP_RND_BITS_MIN=8
-CONFIG_ARCH_MMAP_RND_BITS_MAX=16
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_BUG=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_HAS_CPU_RELAX=y
-CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
-CONFIG_ARCH_HAS_FILTER_PGPROT=y
-CONFIG_HAVE_SETUP_PER_CPU_AREA=y
-CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
-CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-# CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC is not set
-CONFIG_HAVE_INTEL_TXT=y
-CONFIG_X86_32_SMP=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_CC_HAS_SANE_STACKPROTECTOR=y
-
-#
-# Processor type and features
-#
-CONFIG_ZONE_DMA=y
-CONFIG_SMP=y
-CONFIG_X86_FEATURE_NAMES=y
-CONFIG_X86_MPPARSE=y
-# CONFIG_GOLDFISH is not set
-CONFIG_RETPOLINE=y
-CONFIG_RETHUNK=y
-CONFIG_SLS=y
-CONFIG_X86_CPU_RESCTRL=y
-CONFIG_X86_BIGSMP=y
-# CONFIG_X86_EXTENDED_PLATFORM is not set
-CONFIG_X86_INTEL_LPSS=y
-CONFIG_X86_AMD_PLATFORM_DEVICE=y
-CONFIG_IOSF_MBI=y
-# CONFIG_IOSF_MBI_DEBUG is not set
-CONFIG_X86_32_IRIS=m
-CONFIG_SCHED_OMIT_FRAME_POINTER=y
-CONFIG_HYPERVISOR_GUEST=y
-CONFIG_PARAVIRT=y
-# CONFIG_PARAVIRT_DEBUG is not set
-# CONFIG_PARAVIRT_SPINLOCKS is not set
-CONFIG_X86_HV_CALLBACK_VECTOR=y
-# CONFIG_XEN is not set
-CONFIG_KVM_GUEST=y
-CONFIG_ARCH_CPUIDLE_HALTPOLL=y
-CONFIG_PVH=y
-# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
-CONFIG_PARAVIRT_CLOCK=y
-# CONFIG_M486SX is not set
-# CONFIG_M486 is not set
-# CONFIG_M586 is not set
-# CONFIG_M586TSC is not set
-# CONFIG_M586MMX is not set
-CONFIG_M686=y
-# CONFIG_MPENTIUMII is not set
-# CONFIG_MPENTIUMIII is not set
-# CONFIG_MPENTIUMM is not set
-# CONFIG_MPENTIUM4 is not set
-# CONFIG_MK6 is not set
-# CONFIG_MK7 is not set
-# CONFIG_MK8 is not set
-# CONFIG_MK8SSE3 is not set
-# CONFIG_MK10 is not set
-# CONFIG_MBARCELONA is not set
-# CONFIG_MBOBCAT is not set
-# CONFIG_MJAGUAR is not set
-# CONFIG_MBULLDOZER is not set
-# CONFIG_MPILEDRIVER is not set
-# CONFIG_MSTEAMROLLER is not set
-# CONFIG_MEXCAVATOR is not set
-# CONFIG_MZEN is not set
-# CONFIG_MZEN2 is not set
-# CONFIG_MZEN3 is not set
-# CONFIG_MCRUSOE is not set
-# CONFIG_MEFFICEON is not set
-# CONFIG_MWINCHIPC6 is not set
-# CONFIG_MWINCHIP3D is not set
-# CONFIG_MELAN is not set
-# CONFIG_MGEODEGX1 is not set
-# CONFIG_MGEODE_LX is not set
-# CONFIG_MCYRIXIII is not set
-# CONFIG_MVIAC3_2 is not set
-# CONFIG_MVIAC7 is not set
-# CONFIG_MATOM is not set
-# CONFIG_MCORE2 is not set
-# CONFIG_MNEHALEM is not set
-# CONFIG_MWESTMERE is not set
-# CONFIG_MSILVERMONT is not set
-# CONFIG_MGOLDMONT is not set
-# CONFIG_MGOLDMONTPLUS is not set
-# CONFIG_MSANDYBRIDGE is not set
-# CONFIG_MIVYBRIDGE is not set
-# CONFIG_MHASWELL is not set
-# CONFIG_MBROADWELL is not set
-# CONFIG_MSKYLAKE is not set
-# CONFIG_MSKYLAKEX is not set
-# CONFIG_MCANNONLAKE is not set
-# CONFIG_MICELAKE is not set
-# CONFIG_MCASCADELAKE is not set
-# CONFIG_MCOOPERLAKE is not set
-# CONFIG_MTIGERLAKE is not set
-# CONFIG_MSAPPHIRERAPIDS is not set
-# CONFIG_MROCKETLAKE is not set
-# CONFIG_MALDERLAKE is not set
-# CONFIG_MNATIVE_INTEL is not set
-# CONFIG_MNATIVE_AMD is not set
-# CONFIG_MNATIVE is not set
-# CONFIG_GENERIC_CPU2 is not set
-# CONFIG_GENERIC_CPU3 is not set
-# CONFIG_GENERIC_CPU4 is not set
-CONFIG_X86_GENERIC=y
-CONFIG_X86_INTERNODE_CACHE_SHIFT=6
-CONFIG_X86_L1_CACHE_SHIFT=6
-CONFIG_X86_INTEL_USERCOPY=y
-CONFIG_X86_USE_PPRO_CHECKSUM=y
-CONFIG_X86_TSC=y
-CONFIG_X86_CMPXCHG64=y
-CONFIG_X86_CMOV=y
-CONFIG_X86_MINIMUM_CPU_FAMILY=6
-CONFIG_X86_DEBUGCTLMSR=y
-CONFIG_IA32_FEAT_CTL=y
-CONFIG_X86_VMX_FEATURE_NAMES=y
-CONFIG_PROCESSOR_SELECT=y
-CONFIG_CPU_SUP_INTEL=y
-CONFIG_CPU_SUP_CYRIX_32=y
-CONFIG_CPU_SUP_AMD=y
-CONFIG_CPU_SUP_HYGON=y
-CONFIG_CPU_SUP_CENTAUR=y
-CONFIG_CPU_SUP_TRANSMETA_32=y
-CONFIG_CPU_SUP_UMC_32=y
-CONFIG_CPU_SUP_ZHAOXIN=y
-CONFIG_HPET_TIMER=y
-CONFIG_HPET_EMULATE_RTC=y
-CONFIG_DMI=y
-CONFIG_NR_CPUS_RANGE_BEGIN=2
-CONFIG_NR_CPUS_RANGE_END=64
-CONFIG_NR_CPUS_DEFAULT=32
-CONFIG_NR_CPUS=32
-CONFIG_SCHED_CLUSTER=y
-CONFIG_SCHED_SMT=y
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_MC_PRIO=y
-CONFIG_X86_LOCAL_APIC=y
-CONFIG_X86_IO_APIC=y
-CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
-CONFIG_X86_MCE=y
-# CONFIG_X86_MCELOG_LEGACY is not set
-CONFIG_X86_MCE_INTEL=y
-CONFIG_X86_MCE_AMD=y
-CONFIG_X86_ANCIENT_MCE=y
-CONFIG_X86_MCE_THRESHOLD=y
-# CONFIG_X86_MCE_INJECT is not set
-CONFIG_X86_THERMAL_VECTOR=y
-
-#
-# Performance monitoring
-#
-CONFIG_PERF_EVENTS_INTEL_UNCORE=m
-CONFIG_PERF_EVENTS_INTEL_RAPL=m
-CONFIG_PERF_EVENTS_INTEL_CSTATE=m
-CONFIG_PERF_EVENTS_AMD_POWER=m
-CONFIG_PERF_EVENTS_AMD_BRS=y
-CONFIG_PERF_EVENTS_AMD_UNCORE=m
-# end of Performance monitoring
-
-CONFIG_X86_LEGACY_VM86=y
-CONFIG_VM86=y
-CONFIG_X86_16BIT=y
-CONFIG_X86_ESPFIX32=y
-CONFIG_X86_IOPL_IOPERM=y
-CONFIG_TOSHIBA=m
-CONFIG_I8K=m
-CONFIG_X86_REBOOTFIXUPS=y
-CONFIG_MICROCODE=y
-CONFIG_MICROCODE_INTEL=y
-CONFIG_MICROCODE_AMD=y
-# CONFIG_MICROCODE_LATE_LOADING is not set
-# CONFIG_MICROCODE_OLD_INTERFACE is not set
-CONFIG_X86_MSR=m
-CONFIG_X86_CPUID=m
-# CONFIG_NOHIGHMEM is not set
-# CONFIG_HIGHMEM4G is not set
-CONFIG_HIGHMEM64G=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_HIGHMEM=y
-CONFIG_X86_PAE=y
-# CONFIG_X86_CPA_STATISTICS is not set
-CONFIG_NUMA=y
-# CONFIG_NUMA_EMU is not set
-CONFIG_NODES_SHIFT=10
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ILLEGAL_POINTER_VALUE=0
-CONFIG_X86_PMEM_LEGACY_DEVICE=y
-CONFIG_X86_PMEM_LEGACY=m
-CONFIG_HIGHPTE=y
-CONFIG_X86_CHECK_BIOS_CORRUPTION=y
-CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y
-CONFIG_X86_RESERVE_LOW=64
-CONFIG_MTRR=y
-CONFIG_MTRR_SANITIZER=y
-CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0
-CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
-CONFIG_X86_PAT=y
-CONFIG_ARCH_USES_PG_UNCACHED=y
-CONFIG_ARCH_RANDOM=y
-CONFIG_X86_SMAP=y
-CONFIG_X86_UMIP=y
-CONFIG_X86_KERNEL_IBT=y
-CONFIG_X86_INTEL_TSX_MODE_OFF=y
-# CONFIG_X86_INTEL_TSX_MODE_ON is not set
-# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set
-CONFIG_EFI=y
-CONFIG_EFI_STUB=y
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_250 is not set
-CONFIG_HZ_300=y
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=300
-CONFIG_ARCH_FORCE_MAX_ORDER=12
-CONFIG_SCHED_HRTICK=y
-CONFIG_KEXEC=y
-# CONFIG_CRASH_DUMP is not set
-CONFIG_KEXEC_JUMP=y
-CONFIG_PHYSICAL_START=0x1000000
-CONFIG_RELOCATABLE=y
-CONFIG_RANDOMIZE_BASE=y
-CONFIG_X86_NEED_RELOCS=y
-CONFIG_PHYSICAL_ALIGN=0x1000000
-CONFIG_HOTPLUG_CPU=y
-CONFIG_BOOTPARAM_HOTPLUG_CPU0=y
-# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
-# CONFIG_COMPAT_VDSO is not set
-# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
-# CONFIG_CMDLINE_BOOL is not set
-CONFIG_MODIFY_LDT_SYSCALL=y
-# CONFIG_STRICT_SIGALTSTACK_SIZE is not set
-# end of Processor type and features
-
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_USE_PERCPU_NUMA_NODE_ID=y
-CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
-
-#
-# Power management and ACPI options
-#
-CONFIG_ARCH_HIBERNATION_HEADER=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_SUSPEND_SKIP_SYNC is not set
-CONFIG_HIBERNATE_CALLBACKS=y
-CONFIG_HIBERNATION=y
-CONFIG_HIBERNATION_SNAPSHOT_DEV=y
-CONFIG_PM_STD_PARTITION=""
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_PM_AUTOSLEEP=y
-CONFIG_PM_WAKELOCKS=y
-CONFIG_PM_WAKELOCKS_LIMIT=100
-CONFIG_PM_WAKELOCKS_GC=y
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_ENERGY_MODEL=y
-CONFIG_ARCH_SUPPORTS_ACPI=y
-CONFIG_ACPI=y
-CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
-CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
-CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
-# CONFIG_ACPI_DEBUGGER is not set
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_FPDT=y
-CONFIG_ACPI_SLEEP=y
-CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
-# CONFIG_ACPI_EC_DEBUGFS is not set
-CONFIG_ACPI_AC=m
-CONFIG_ACPI_BATTERY=m
-CONFIG_ACPI_BUTTON=m
-CONFIG_ACPI_VIDEO=m
-CONFIG_ACPI_TINY_POWER_BUTTON=m
-CONFIG_ACPI_TINY_POWER_BUTTON_SIGNAL=38
-CONFIG_ACPI_VIDEO=m
-CONFIG_ACPI_FAN=m
-CONFIG_ACPI_TAD=m
-CONFIG_ACPI_DOCK=y
-CONFIG_ACPI_CPU_FREQ_PSS=y
-CONFIG_ACPI_PROCESSOR_CSTATE=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
-CONFIG_ACPI_PROCESSOR=y
-CONFIG_ACPI_IPMI=m
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_PROCESSOR_AGGREGATOR=m
-CONFIG_ACPI_THERMAL=m
-CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
-CONFIG_ACPI_TABLE_UPGRADE=y
-# CONFIG_ACPI_DEBUG is not set
-CONFIG_ACPI_PCI_SLOT=y
-CONFIG_ACPI_CONTAINER=y
-CONFIG_ACPI_HOTPLUG_IOAPIC=y
-CONFIG_ACPI_SBS=m
-CONFIG_ACPI_HED=y
-# CONFIG_ACPI_CUSTOM_METHOD is not set
-CONFIG_ACPI_BGRT=y
-# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
-CONFIG_ACPI_NUMA=y
-CONFIG_ACPI_HMAT=y
-CONFIG_HAVE_ACPI_APEI=y
-CONFIG_HAVE_ACPI_APEI_NMI=y
-CONFIG_ACPI_APEI=y
-CONFIG_ACPI_APEI_GHES=y
-CONFIG_ACPI_APEI_PCIEAER=y
-# CONFIG_ACPI_APEI_EINJ is not set
-# CONFIG_ACPI_APEI_ERST_DEBUG is not set
-CONFIG_ACPI_DPTF=y
-CONFIG_DPTF_POWER=m
-CONFIG_DPTF_PCH_FIVR=m
-CONFIG_ACPI_WATCHDOG=y
-CONFIG_ACPI_EXTLOG=m
-CONFIG_ACPI_CONFIGFS=m
-CONFIG_ACPI_PFRUT=m
-CONFIG_ACPI_PCC=y
-CONFIG_ACPI_PRMT=y
-CONFIG_TPS68470_PMIC_OPREGION=y
-CONFIG_PMIC_OPREGION=y
-# CONFIG_XPOWER_PMIC_OPREGION is not set
-# CONFIG_BXT_WC_PMIC_OPREGION is not set
-CONFIG_CHT_DC_TI_PMIC_OPREGION=y
-CONFIG_X86_PM_TIMER=y
-CONFIG_ACPI_PRMT=y
-CONFIG_SFI=y
-CONFIG_X86_APM_BOOT=y
-CONFIG_APM=m
-# CONFIG_APM_IGNORE_USER_SUSPEND is not set
-# CONFIG_APM_DO_ENABLE is not set
-# CONFIG_APM_CPU_IDLE is not set
-# CONFIG_APM_DISPLAY_BLANK is not set
-# CONFIG_APM_ALLOW_INTS is not set
-
-#
-# CPU Frequency scaling
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-
-#
-# CPU frequency scaling drivers
-#
-CONFIG_X86_INTEL_PSTATE=y
-CONFIG_X86_PCC_CPUFREQ=m
-CONFIG_X86_AMD_PSTATE=y
-CONFIG_X86_AMD_PSTATE_UT=m
-CONFIG_X86_ACPI_CPUFREQ=m
-CONFIG_X86_ACPI_CPUFREQ_CPB=y
-CONFIG_X86_POWERNOW_K6=m
-CONFIG_X86_POWERNOW_K7=m
-CONFIG_X86_POWERNOW_K7_ACPI=y
-CONFIG_X86_POWERNOW_K8=m
-CONFIG_X86_AMD_FREQ_SENSITIVITY=m
-CONFIG_X86_GX_SUSPMOD=m
-# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
-CONFIG_X86_SPEEDSTEP_ICH=m
-CONFIG_X86_SPEEDSTEP_SMI=m
-# CONFIG_X86_P4_CLOCKMOD is not set
-CONFIG_X86_CPUFREQ_NFORCE2=m
-CONFIG_X86_LONGRUN=m
-CONFIG_X86_LONGHAUL=m
-CONFIG_X86_E_POWERSAVER=m
-
-#
-# shared options
-#
-CONFIG_X86_SPEEDSTEP_LIB=m
-# CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK is not set
-# end of CPU Frequency scaling
-
-#
-# CPU Idle
-#
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-# CONFIG_CPU_IDLE_GOV_TEO is not set
-# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set
-CONFIG_HALTPOLL_CPUIDLE=y
-# end of CPU Idle
-
-CONFIG_INTEL_IDLE=y
-# end of Power management and ACPI options
-
-#
-# Bus options (PCI etc.)
-#
-# CONFIG_PCI_GOBIOS is not set
-# CONFIG_PCI_GOMMCONFIG is not set
-# CONFIG_PCI_GODIRECT is not set
-CONFIG_PCI_GOANY=y
-CONFIG_PCI_BIOS=y
-CONFIG_PCI_DIRECT=y
-CONFIG_PCI_MMCONFIG=y
-# CONFIG_PCI_CNB20LE_QUIRK is not set
-# CONFIG_ISA_BUS is not set
-CONFIG_ISA_DMA_API=y
-CONFIG_ISA=y
-# CONFIG_SCx200 is not set
-# CONFIG_ALIX is not set
-# CONFIG_NET5501 is not set
-# CONFIG_GEOS is not set
-CONFIG_AMD_NB=y
-CONFIG_X86_SYSFB=y
-# end of Bus options (PCI etc.)
-
-#
-# Binary Emulations
-#
-CONFIG_COMPAT_32=y
-# end of Binary Emulations
-
-CONFIG_HAVE_ATOMIC_IOMAP=y
-
-#
-# Firmware Drivers
-#
-CONFIG_EDD=m
-# CONFIG_EDD_OFF is not set
-CONFIG_FIRMWARE_MEMMAP=y
-CONFIG_DMIID=y
-CONFIG_DMI_SYSFS=m
-CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
-CONFIG_ISCSI_IBFT_FIND=y
-CONFIG_ISCSI_IBFT=m
-CONFIG_FW_CFG_SYSFS=m
-CONFIG_SYSFB_SIMPLEFB=y
-# CONFIG_FW_CFG_SYSFS_CMDLINE is not set
-CONFIG_GOOGLE_FIRMWARE=y
-CONFIG_GOOGLE_SMI=m
-CONFIG_GOOGLE_COREBOOT_TABLE=m
-CONFIG_GOOGLE_MEMCONSOLE=m
-CONFIG_GOOGLE_MEMCONSOLE_X86_LEGACY=m
-CONFIG_GOOGLE_FRAMEBUFFER_COREBOOT=m
-CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m
-CONFIG_GOOGLE_VPD=m
-
-#
-# EFI (Extensible Firmware Interface) Support
-#
-CONFIG_EFI_VARS=m
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_VARS_PSTORE=m
-CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
-CONFIG_EFI_RUNTIME_MAP=y
-# CONFIG_EFI_FAKE_MEMMAP is not set
-CONFIG_EFI_SOFT_RESERVE=y
-CONFIG_EFI_ZBOOT=y
-# CONFIG_EFI_ZBOOT_SIGNING is not set
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
-CONFIG_EFI_BOOTLOADER_CONTROL=m
-CONFIG_EFI_CAPSULE_LOADER=y
-CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH=y
-CONFIG_EFI_TEST=m
-CONFIG_APPLE_PROPERTIES=y
-CONFIG_RESET_ATTACK_MITIGATION=y
-CONFIG_EFI_RCI2_TABLE=y
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# end of EFI (Extensible Firmware Interface) Support
-
-CONFIG_UEFI_CPER=y
-CONFIG_UEFI_CPER_X86=y
-CONFIG_EFI_DEV_PATH_PARSER=y
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-
-#
-# Tegra firmware driver
-#
-# end of Tegra firmware driver
-# end of Firmware Drivers
-
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_KVM_IRQCHIP=y
-CONFIG_HAVE_KVM_IRQFD=y
-CONFIG_HAVE_KVM_IRQ_ROUTING=y
-CONFIG_HAVE_KVM_EVENTFD=y
-CONFIG_KVM_MMIO=y
-CONFIG_KVM_ASYNC_PF=y
-CONFIG_HAVE_KVM_MSI=y
-CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
-CONFIG_KVM_VFIO=y
-CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
-CONFIG_HAVE_KVM_IRQ_BYPASS=y
-CONFIG_HAVE_KVM_NO_POLL=y
-CONFIG_KVM_XFER_TO_GUEST_WORK=y
-CONFIG_VIRTUALIZATION=y
-CONFIG_KVM=m
-CONFIG_KVM_WERROR=y
-CONFIG_KVM_INTEL=m
-CONFIG_X86_SGX_KVM=y
-CONFIG_KVM_AMD=m
-CONFIG_KVM_XEN=y
-# CONFIG_KVM_MMU_AUDIT is not set
-CONFIG_AS_AVX512=y
-CONFIG_AS_SHA1_NI=y
-CONFIG_AS_SHA256_NI=y
-CONFIG_AS_TPAUSE=y
-
-#
-# General architecture-dependent options
-#
-CONFIG_CRASH_CORE=y
-CONFIG_KEXEC_CORE=y
-CONFIG_HOTPLUG_SMT=y
-CONFIG_GENERIC_ENTRY=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_OPROFILE_NMI_TIMER=y
-CONFIG_KPROBES=y
-CONFIG_JUMP_LABEL=y
-# CONFIG_STATIC_KEYS_SELFTEST is not set
-# CONFIG_STATIC_CALL_SELFTEST is not set
-CONFIG_OPTPROBES=y
-CONFIG_KPROBES_ON_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_KRETPROBES=y
-CONFIG_USER_RETURN_NOTIFIER=y
-CONFIG_HAVE_IOREMAP_PROT=y
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_KPROBES_ON_FTRACE=y
-CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
-CONFIG_HAVE_NMI=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
-CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
-CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_HAVE_ASM_MODVERSIONS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
-CONFIG_HAVE_USER_RETURN_NOTIFIER=y
-CONFIG_HAVE_PERF_EVENTS_NMI=y
-CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
-CONFIG_MMU_GATHER_TABLE_FREE=y
-CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
-CONFIG_HAVE_CMPXCHG_LOCAL=y
-CONFIG_HAVE_CMPXCHG_DOUBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_HAVE_ARCH_SECCOMP=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_SECCOMP=y
-# CONFIG_SECCOMP_CACHE_DEBUG is not set
-CONFIG_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_STACKLEAK=y
-CONFIG_HAVE_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR_STRONG=y
-CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MOVE_PMD=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-CONFIG_HAVE_ARCH_HUGE_VMAP=y
-CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
-CONFIG_HAVE_EXIT_THREAD=y
-CONFIG_ARCH_MMAP_RND_BITS=8
-CONFIG_ISA_BUS_API=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_VMAP_STACK=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_STRICT_MODULE_RWX=y
-CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
-CONFIG_ARCH_USE_MEMREMAP_PROT=y
-# CONFIG_LOCK_EVENT_COUNTS is not set
-CONFIG_X86_PLATFORM_DRIVERS_INTEL=y
-CONFIG_INTEL_SKL_INT3472=m
-# CONFIG_KCSAN is not set
-CONFIG_ARCH_HAS_MEM_ENCRYPT=y
-CONFIG_HAVE_STATIC_CALL=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-# end of GCOV-based kernel profiling
-
-CONFIG_HAVE_GCC_PLUGINS=y
-# CONFIG_GCC_PLUGINS is not set
-# end of General architecture-dependent options
-
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_ASM_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_MODULE_SIG is not set
-CONFIG_MODULE_COMPRESS_NONE=y
-# CONFIG_MODULE_COMPRESS_GZIP is not set
-# CONFIG_MODULE_COMPRESS_XZ is not set
-# CONFIG_MODULE_COMPRESS_ZSTD is not set
-# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
-CONFIG_MODPROBE_PATH="/sbin/modprobe"
-# CONFIG_TRIM_UNUSED_KSYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_TRIM_UNUSED_KSYMS is not set
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_BLOCK=y
-# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set
-CONFIG_BLK_SCSI_REQUEST=y
-CONFIG_BLK_CGROUP_RWSTAT=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=m
-CONFIG_BLK_DEV_ZONED=y
-CONFIG_BLK_DEV_THROTTLING=y
-# CONFIG_BLK_DEV_THROTTLING_LOW is not set
-CONFIG_BLK_CMDLINE_PARSER=y
-CONFIG_BLK_WBT=y
-CONFIG_BLK_CGROUP_IOLATENCY=y
-# CONFIG_BLK_CGROUP_FC_APPID is not set
-# CONFIG_BLK_CGROUP_IOCOST is not set
-# CONFIG_BLK_CGROUP_IOPRIO is not set
-CONFIG_BLK_WBT_MQ=y
-# CONFIG_BLK_DEBUG_FS is not set
-CONFIG_BLK_DEBUG_FS_ZONED=y
-# CONFIG_BLK_SED_OPAL is not set
-# CONFIG_BLK_INLINE_ENCRYPTION is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_ACORN_PARTITION=y
-CONFIG_ACORN_PARTITION_CUMANA=y
-CONFIG_ACORN_PARTITION_EESOX=y
-CONFIG_ACORN_PARTITION_ICS=y
-CONFIG_ACORN_PARTITION_ADFS=y
-CONFIG_ACORN_PARTITION_POWERTEC=y
-CONFIG_ACORN_PARTITION_RISCIX=y
-CONFIG_AIX_PARTITION=y
-CONFIG_OSF_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_ATARI_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_MSDOS_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_LDM_DEBUG=y
-CONFIG_SGI_PARTITION=y
-CONFIG_ULTRIX_PARTITION=y
-CONFIG_SUN_PARTITION=y
-CONFIG_KARMA_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_SYSV68_PARTITION=y
-CONFIG_CMDLINE_PARTITION=y
-# end of Partition Types
-
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_MQ_RDMA=y
-CONFIG_BLK_PM=y
-
-#
-# IO Schedulers
-#
-CONFIG_MQ_IOSCHED_DEADLINE=y
-CONFIG_MQ_IOSCHED_KYBER=m
-CONFIG_IOSCHED_BFQ=y
-CONFIG_BFQ_GROUP_IOSCHED=y
-# CONFIG_BFQ_CGROUP_DEBUG is not set
-# end of IO Schedulers
-
-CONFIG_PREEMPT_NOTIFIERS=y
-CONFIG_PADATA=y
-CONFIG_ASN1=y
-CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
-CONFIG_INLINE_READ_UNLOCK=y
-CONFIG_INLINE_READ_UNLOCK_IRQ=y
-CONFIG_INLINE_WRITE_UNLOCK=y
-CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
-CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y
-CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
-CONFIG_FREEZER=y
-
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_ELFCORE=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_BINFMT_SCRIPT=y
-CONFIG_BINFMT_MISC=m
-CONFIG_COREDUMP=y
-# end of Executable file formats
-
-#
-# Memory Management options
-#
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM=y
-CONFIG_NEED_MULTIPLE_NODES=y
-CONFIG_SPARSEMEM_STATIC=y
-CONFIG_HAVE_FAST_GUP=y
-CONFIG_NUMA_KEEP_MEMINFO=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_MEMORY_BALLOON=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_COMPACTION=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_MIGRATION=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_BOUNCE=y
-CONFIG_VIRT_TO_BUS=y
-CONFIG_MMU_NOTIFIER=y
-CONFIG_KSM=y
-CONFIG_UKSM=y
-# CONFIG_KSM_LEGACY is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
-CONFIG_TRANSPARENT_HUGEPAGE=y
-CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
-# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-CONFIG_CLEANCACHE=y
-CONFIG_FRONTSWAP=y
-CONFIG_CMA=y
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SYSFS=y
-CONFIG_CMA_AREAS=7
-CONFIG_ZSWAP=y
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
-CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
-CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
-# CONFIG_ZSWAP_DEFAULT_ON is not set
-CONFIG_ZPOOL=y
-CONFIG_ZBUD=y
-CONFIG_Z3FOLD=m
-CONFIG_ZSMALLOC=y
-# CONFIG_ZSMALLOC_PGTABLE_MAPPING is not set
-# CONFIG_ZSMALLOC_STAT is not set
-CONFIG_GENERIC_EARLY_IOREMAP=y
-# CONFIG_IDLE_PAGE_TRACKING is not set
-CONFIG_HMM_MIRROR=y
-CONFIG_VMAP_PFN=y
-CONFIG_FRAME_VECTOR=y
-# CONFIG_PERCPU_STATS is not set
-# CONFIG_GUP_TEST is not set
-# CONFIG_GUP_BENCHMARK is not set
-CONFIG_GUP_GET_PTE_LOW_HIGH=y
-# CONFIG_READ_ONLY_THP_FOR_FS is not set
-CONFIG_ARCH_HAS_PTE_SPECIAL=y
-CONFIG_MAPPING_DIRTY_HELPERS=y
-# end of Memory Management options
-
-CONFIG_NET=y
-CONFIG_NET_INGRESS=y
-CONFIG_NET_EGRESS=y
-CONFIG_NET_REDIRECT=y
-CONFIG_SKB_EXTENSIONS=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=m
-CONFIG_PACKET_DIAG=m
-CONFIG_UNIX=y
-CONFIG_UNIX_SCM=y
-CONFIG_UNIX_DIAG=m
-CONFIG_TLS=m
-# CONFIG_TLS_DEVICE is not set
-# CONFIG_TLS_TOE is not set
-CONFIG_XFRM=y
-CONFIG_XFRM_OFFLOAD=y
-CONFIG_XFRM_ALGO=m
-CONFIG_XFRM_USER=m
-CONFIG_XFRM_INTERFACE=m
-CONFIG_XFRM_SUB_POLICY=y
-CONFIG_XFRM_MIGRATE=y
-CONFIG_XFRM_STATISTICS=y
-CONFIG_XFRM_AH=m
-CONFIG_XFRM_ESP=m
-CONFIG_XFRM_IPCOMP=m
-CONFIG_NET_KEY=m
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_XFRM_ESPINTCP=y
-CONFIG_SMC=m
-CONFIG_SMC_DIAG=m
-CONFIG_XDP_SOCKETS=y
-CONFIG_XDP_SOCKETS_DIAG=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_FIB_TRIE_STATS=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-# CONFIG_IP_ROUTE_VERBOSE is not set
-CONFIG_IP_ROUTE_CLASSID=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE_DEMUX=m
-CONFIG_NET_IP_TUNNEL=m
-CONFIG_NET_IPGRE=m
-CONFIG_NET_IPGRE_BROADCAST=y
-CONFIG_IP_MROUTE_COMMON=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_NET_IPVTI=m
-CONFIG_NET_UDP_TUNNEL=m
-CONFIG_NET_FOU=m
-CONFIG_NET_FOU_IP_TUNNELS=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_ESP_OFFLOAD=m
-CONFIG_INET_ESPINTCP=y
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_TABLE_PERTURB_ORDER=16
-CONFIG_INET_XFRM_TUNNEL=m
-CONFIG_INET_TUNNEL=m
-CONFIG_INET_DIAG=m
-CONFIG_INET_TCP_DIAG=m
-CONFIG_INET_UDP_DIAG=m
-CONFIG_INET_RAW_DIAG=m
-CONFIG_INET_DIAG_DESTROY=y
-CONFIG_TCP_CONG_ADVANCED=y
-CONFIG_TCP_CONG_BIC=m
-CONFIG_TCP_CONG_CUBIC=m
-CONFIG_TCP_CONG_WESTWOOD=m
-CONFIG_TCP_CONG_HTCP=m
-CONFIG_TCP_CONG_HSTCP=m
-CONFIG_TCP_CONG_HYBLA=m
-CONFIG_TCP_CONG_VEGAS=m
-CONFIG_TCP_CONG_NV=m
-CONFIG_TCP_CONG_SCALABLE=m
-CONFIG_TCP_CONG_LP=m
-CONFIG_TCP_CONG_VENO=m
-CONFIG_TCP_CONG_YEAH=m
-CONFIG_TCP_CONG_ILLINOIS=m
-CONFIG_TCP_CONG_DCTCP=m
-# CONFIG_TCP_CONG_CDG is not set
-CONFIG_TCP_CONG_BBR=m
-CONFIG_DEFAULT_RENO=y
-CONFIG_DEFAULT_TCP_CONG="reno"
-CONFIG_TCP_MD5SIG=y
-CONFIG_IPV6=m
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_ESP_OFFLOAD=m
-# CONFIG_INET6_ESPINTCP is not set
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_IPV6_ILA=m
-CONFIG_INET6_XFRM_TUNNEL=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_IPV6_VTI=m
-CONFIG_IPV6_SIT=m
-CONFIG_IPV6_SIT_6RD=y
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_GRE=m
-CONFIG_IPV6_FOU=m
-CONFIG_IPV6_FOU_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-CONFIG_IPV6_MROUTE=y
-CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IPV6_PIMSM_V2=y
-CONFIG_IPV6_SEG6_LWTUNNEL=y
-CONFIG_IPV6_SEG6_HMAC=y
-CONFIG_IPV6_RPL_LWTUNNEL=y
-CONFIG_MPTCP=y
-CONFIG_INET_MPTCP_DIAG=m
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NETWORK_PHY_TIMESTAMPING=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_ADVANCED=y
-CONFIG_BRIDGE_NETFILTER=m
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_INGRESS=y
-CONFIG_NETFILTER_NETLINK_HOOK=m
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_FAMILY_BRIDGE=y
-CONFIG_NETFILTER_FAMILY_ARP=y
-CONFIG_NETFILTER_NETLINK_ACCT=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NETFILTER_NETLINK_OSF=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_LOG_SYSLOG=m
-CONFIG_NF_LOG_COMMON=m
-CONFIG_NF_LOG_NETDEV=m
-CONFIG_NETFILTER_CONNCOUNT=m
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_ZONES=y
-CONFIG_NF_CONNTRACK_PROCFS=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CONNTRACK_TIMEOUT=y
-CONFIG_NF_CONNTRACK_TIMESTAMP=y
-CONFIG_NF_CONNTRACK_LABELS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_GRE=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_BROADCAST=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_SNMP=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NF_CT_NETLINK_TIMEOUT=m
-CONFIG_NF_CT_NETLINK_HELPER=m
-CONFIG_NETFILTER_NETLINK_GLUE_CT=y
-CONFIG_NF_NAT=m
-CONFIG_NF_NAT_AMANDA=m
-CONFIG_NF_NAT_FTP=m
-CONFIG_NF_NAT_IRC=m
-CONFIG_NF_NAT_SIP=m
-CONFIG_NF_NAT_TFTP=m
-CONFIG_NF_NAT_REDIRECT=y
-CONFIG_NF_NAT_MASQUERADE=y
-CONFIG_NETFILTER_SYNPROXY=m
-CONFIG_NF_TABLES=m
-CONFIG_NF_TABLES_INET=y
-CONFIG_NF_TABLES_NETDEV=y
-CONFIG_NFT_NUMGEN=m
-CONFIG_NFT_CT=m
-CONFIG_NFT_FLOW_OFFLOAD=m
-CONFIG_NFT_COUNTER=m
-CONFIG_NFT_CONNLIMIT=m
-CONFIG_NFT_LOG=m
-CONFIG_NFT_LIMIT=m
-CONFIG_NFT_MASQ=m
-CONFIG_NFT_REDIR=m
-CONFIG_NFT_NAT=m
-CONFIG_NFT_TUNNEL=m
-CONFIG_NFT_OBJREF=m
-CONFIG_NFT_QUEUE=m
-CONFIG_NFT_QUOTA=m
-CONFIG_NFT_REJECT=m
-CONFIG_NFT_REJECT_INET=m
-CONFIG_NFT_COMPAT=m
-CONFIG_NFT_HASH=m
-CONFIG_NFT_FIB_INET=m
-CONFIG_NFT_FIB=m
-CONFIG_NFT_FIB_INET=m
-CONFIG_NFT_XFRM=m
-CONFIG_NFT_SOCKET=m
-CONFIG_NFT_OSF=m
-CONFIG_NFT_TPROXY=m
-CONFIG_NFT_SYNPROXY=m
-CONFIG_NF_DUP_NETDEV=m
-CONFIG_NFT_DUP_NETDEV=m
-CONFIG_NFT_FWD_NETDEV=m
-CONFIG_NFT_FIB_NETDEV=m
-CONFIG_NFT_REJECT_NETDEV=m
-CONFIG_NF_FLOW_TABLE_INET=m
-CONFIG_NF_FLOW_TABLE=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XTABLES_COMPAT=y
-
-#
-# Xtables combined modules
-#
-CONFIG_NETFILTER_XT_MARK=m
-CONFIG_NETFILTER_XT_CONNMARK=m
-CONFIG_NETFILTER_XT_SET=m
-
-#
-# Xtables targets
-#
-CONFIG_NETFILTER_XT_TARGET_AUDIT=m
-CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CT=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_HL=m
-CONFIG_NETFILTER_XT_TARGET_HMARK=m
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
-CONFIG_NETFILTER_XT_TARGET_LOG=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_NAT=m
-CONFIG_NETFILTER_XT_TARGET_NETMAP=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-CONFIG_NETFILTER_XT_TARGET_RATEEST=m
-CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
-CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
-CONFIG_NETFILTER_XT_TARGET_TEE=m
-CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-CONFIG_NETFILTER_XT_TARGET_TRACE=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-
-#
-# Xtables matches
-#
-CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
-CONFIG_NETFILTER_XT_MATCH_BPF=m
-CONFIG_NETFILTER_XT_MATCH_CGROUP=m
-CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_CPU=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ECN=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_HL=m
-CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_IPVS=m
-CONFIG_NETFILTER_XT_MATCH_L2TP=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-CONFIG_NETFILTER_XT_MATCH_OSF=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-# end of Core Netfilter Configuration
-
-CONFIG_IP_SET=m
-CONFIG_IP_SET_MAX=256
-CONFIG_IP_SET_BITMAP_IP=m
-CONFIG_IP_SET_BITMAP_IPMAC=m
-CONFIG_IP_SET_BITMAP_PORT=m
-CONFIG_IP_SET_HASH_IP=m
-CONFIG_IP_SET_HASH_IPMARK=m
-CONFIG_IP_SET_HASH_IPPORT=m
-CONFIG_IP_SET_HASH_IPPORTIP=m
-CONFIG_IP_SET_HASH_IPPORTNET=m
-CONFIG_IP_SET_HASH_IPMAC=m
-CONFIG_IP_SET_HASH_MAC=m
-CONFIG_IP_SET_HASH_NETPORTNET=m
-CONFIG_IP_SET_HASH_NET=m
-CONFIG_IP_SET_HASH_NETNET=m
-CONFIG_IP_SET_HASH_NETPORT=m
-CONFIG_IP_SET_HASH_NETIFACE=m
-CONFIG_IP_SET_LIST_SET=m
-CONFIG_IP_VS=m
-CONFIG_IP_VS_IPV6=y
-# CONFIG_IP_VS_DEBUG is not set
-CONFIG_IP_VS_TAB_BITS=12
-
-#
-# IPVS transport protocol load balancing support
-#
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_AH_ESP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_PROTO_SCTP=y
-
-#
-# IPVS scheduler
-#
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_FO=m
-CONFIG_IP_VS_OVF=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_MH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_TWOS=m
-
-#
-# IPVS SH scheduler
-#
-CONFIG_IP_VS_SH_TAB_BITS=8
-
-#
-# IPVS MH scheduler
-#
-CONFIG_IP_VS_MH_TAB_INDEX=12
-
-#
-# IPVS application helper
-#
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_VS_NFCT=y
-CONFIG_IP_VS_PE_SIP=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_DEFRAG_IPV4=m
-CONFIG_NF_SOCKET_IPV4=m
-CONFIG_NF_TPROXY_IPV4=m
-CONFIG_NF_TABLES_IPV4=y
-CONFIG_NFT_REJECT_IPV4=m
-CONFIG_NFT_DUP_IPV4=m
-CONFIG_NFT_FIB_IPV4=m
-CONFIG_NF_TABLES_ARP=y
-CONFIG_NF_FLOW_TABLE_IPV4=m
-CONFIG_NF_DUP_IPV4=m
-CONFIG_NF_LOG_ARP=m
-CONFIG_NF_LOG_IPV4=m
-CONFIG_NF_REJECT_IPV4=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_NF_NAT_PPTP=m
-CONFIG_NF_NAT_H323=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_RPFILTER=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_SYNPROXY=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-# end of IP: Netfilter Configuration
-
-#
-# IPv6: Netfilter Configuration
-#
-CONFIG_NF_SOCKET_IPV6=m
-CONFIG_NF_TPROXY_IPV6=m
-CONFIG_NF_TABLES_IPV6=y
-CONFIG_NFT_REJECT_IPV6=m
-CONFIG_NFT_DUP_IPV6=m
-CONFIG_NFT_FIB_IPV6=m
-CONFIG_NF_FLOW_TABLE_IPV6=m
-CONFIG_NF_DUP_IPV6=m
-CONFIG_NF_REJECT_IPV6=m
-CONFIG_NF_LOG_IPV6=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RPFILTER=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_MATCH_SRH=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_TARGET_SYNPROXY=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_IP6_NF_NAT=m
-CONFIG_IP6_NF_TARGET_MASQUERADE=m
-CONFIG_IP6_NF_TARGET_NPT=m
-# end of IPv6: Netfilter Configuration
-
-CONFIG_NF_DEFRAG_IPV6=m
-
-#
-# DECnet: Netfilter Configuration
-#
-CONFIG_DECNET_NF_GRABULATOR=m
-# end of DECnet: Netfilter Configuration
-
-CONFIG_NF_TABLES_BRIDGE=m
-CONFIG_NFT_BRIDGE_META=m
-CONFIG_NFT_BRIDGE_REJECT=m
-CONFIG_NF_LOG_BRIDGE=m
-CONFIG_NF_CONNTRACK_BRIDGE=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_IP6=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_BRIDGE_EBT_NFLOG=m
-# CONFIG_BPFILTER is not set
-CONFIG_IP_DCCP=m
-CONFIG_INET_DCCP_DIAG=m
-
-#
-# DCCP CCIDs Configuration
-#
-# CONFIG_IP_DCCP_CCID2_DEBUG is not set
-CONFIG_IP_DCCP_CCID3=y
-# CONFIG_IP_DCCP_CCID3_DEBUG is not set
-CONFIG_IP_DCCP_TFRC_LIB=y
-# end of DCCP CCIDs Configuration
-
-#
-# DCCP Kernel Hacking
-#
-# CONFIG_IP_DCCP_DEBUG is not set
-# end of DCCP Kernel Hacking
-
-CONFIG_IP_SCTP=m
-# CONFIG_SCTP_DBG_OBJCNT is not set
-CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
-CONFIG_SCTP_COOKIE_HMAC_MD5=y
-CONFIG_SCTP_COOKIE_HMAC_SHA1=y
-CONFIG_INET_SCTP_DIAG=m
-CONFIG_RDS=m
-CONFIG_RDS_RDMA=m
-CONFIG_RDS_TCP=m
-# CONFIG_RDS_DEBUG is not set
-CONFIG_TIPC=m
-CONFIG_TIPC_MEDIA_IB=y
-CONFIG_TIPC_MEDIA_UDP=y
-CONFIG_TIPC_CRYPTO=y
-CONFIG_TIPC_DIAG=m
-CONFIG_ATM=m
-CONFIG_ATM_CLIP=m
-# CONFIG_ATM_CLIP_NO_ICMP is not set
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-# CONFIG_ATM_BR2684_IPFILTER is not set
-CONFIG_L2TP=m
-# CONFIG_L2TP_DEBUGFS is not set
-CONFIG_L2TP_V3=y
-CONFIG_L2TP_IP=m
-CONFIG_L2TP_ETH=m
-CONFIG_STP=m
-CONFIG_GARP=m
-CONFIG_MRP=m
-CONFIG_BRIDGE=m
-CONFIG_BRIDGE_IGMP_SNOOPING=y
-CONFIG_BRIDGE_VLAN_FILTERING=y
-# CONFIG_BRIDGE_MRP is not set
-# CONFIG_BRIDGE_CFM is not set
-CONFIG_HAVE_NET_DSA=y
-CONFIG_NET_DSA=m
-CONFIG_NET_DSA_TAG_8021Q=m
-CONFIG_NET_DSA_TAG_AR9331=m
-CONFIG_NET_DSA_TAG_BRCM_COMMON=m
-CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
-CONFIG_NET_DSA_TAG_BRCM=m
-CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
-CONFIG_NET_DSA_TAG_HELLCREEK=m
-CONFIG_NET_DSA_TAG_GSWIP=m
-CONFIG_NET_DSA_TAG_DSA=m
-CONFIG_NET_DSA_TAG_EDSA=m
-CONFIG_NET_DSA_TAG_MTK=m
-CONFIG_NET_DSA_TAG_KSZ=m
-CONFIG_NET_DSA_TAG_RTL4_A=m
-CONFIG_NET_DSA_TAG_RTL8_4=m
-CONFIG_NET_DSA_TAG_OCELOT=m
-CONFIG_NET_DSA_TAG_QCA=m
-CONFIG_NET_DSA_TAG_LAN9303=m
-CONFIG_NET_DSA_TAG_SJA1105=m
-CONFIG_NET_DSA_TAG_TRAILER=m
-CONFIG_NET_DSA_TAG_XRS700X=m
-CONFIG_NET_DSA_REALTEK=m
-CONFIG_NET_DSA_REALTEK_MDIO=m
-CONFIG_NET_DSA_REALTEK_RTL8365MB=m
-CONFIG_NET_DSA_REALTEK_RTL8366RB=m
-CONFIG_VLAN_8021Q=m
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_VLAN_8021Q_MVRP=y
-CONFIG_DECNET=m
-CONFIG_DECNET_ROUTER=y
-CONFIG_LLC=m
-CONFIG_LLC2=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-# CONFIG_LTPC is not set
-# CONFIG_COPS is not set
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_PHONET=m
-CONFIG_6LOWPAN=m
-# CONFIG_6LOWPAN_DEBUGFS is not set
-CONFIG_6LOWPAN_NHC=m
-CONFIG_6LOWPAN_NHC_DEST=m
-CONFIG_6LOWPAN_NHC_FRAGMENT=m
-CONFIG_6LOWPAN_NHC_HOP=m
-CONFIG_6LOWPAN_NHC_IPV6=m
-CONFIG_6LOWPAN_NHC_MOBILITY=m
-CONFIG_6LOWPAN_NHC_ROUTING=m
-CONFIG_6LOWPAN_NHC_UDP=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
-CONFIG_6LOWPAN_GHC_UDP=m
-CONFIG_6LOWPAN_GHC_ICMPV6=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
-CONFIG_IEEE802154=m
-CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
-CONFIG_IEEE802154_SOCKET=m
-CONFIG_IEEE802154_6LOWPAN=m
-CONFIG_MAC802154=m
-CONFIG_NET_SCHED=y
-
-#
-# Queueing/Scheduling
-#
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_MULTIQ=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFB=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_CBS=m
-CONFIG_NET_SCH_ETF=m
-CONFIG_NET_SCH_TAPRIO=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_DRR=m
-CONFIG_NET_SCH_MQPRIO=m
-CONFIG_NET_SCH_SKBPRIO=m
-CONFIG_NET_SCH_CHOKE=m
-CONFIG_NET_SCH_QFQ=m
-CONFIG_NET_SCH_CODEL=m
-CONFIG_NET_SCH_FQ_CODEL=y
-CONFIG_NET_SCH_CAKE=m
-CONFIG_NET_SCH_FQ=m
-CONFIG_NET_SCH_HHF=m
-CONFIG_NET_SCH_PIE=m
-CONFIG_NET_SCH_FQ_PIE=m
-CONFIG_NET_SCH_INGRESS=m
-CONFIG_NET_SCH_PLUG=m
-CONFIG_NET_SCH_ETS=m
-# CONFIG_NET_SCH_DEFAULT is not set
-
-#
-# Classification
-#
-CONFIG_NET_CLS=y
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_CLS_U32_PERF=y
-CONFIG_CLS_U32_MARK=y
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_CLS_FLOW=m
-CONFIG_NET_CLS_CGROUP=m
-CONFIG_NET_CLS_BPF=m
-CONFIG_NET_CLS_FLOWER=m
-CONFIG_NET_CLS_MATCHALL=m
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_STACK=32
-CONFIG_NET_EMATCH_CMP=m
-CONFIG_NET_EMATCH_NBYTE=m
-CONFIG_NET_EMATCH_U32=m
-CONFIG_NET_EMATCH_META=m
-CONFIG_NET_EMATCH_TEXT=m
-CONFIG_NET_EMATCH_CANID=m
-CONFIG_NET_EMATCH_IPSET=m
-CONFIG_NET_EMATCH_IPT=m
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=m
-CONFIG_NET_ACT_GACT=m
-CONFIG_GACT_PROB=y
-CONFIG_NET_ACT_MIRRED=m
-CONFIG_NET_ACT_SAMPLE=m
-CONFIG_NET_ACT_IPT=m
-CONFIG_NET_ACT_NAT=m
-CONFIG_NET_ACT_PEDIT=m
-# CONFIG_NET_ACT_SIMP is not set
-CONFIG_NET_ACT_SKBEDIT=m
-CONFIG_NET_ACT_CSUM=m
-CONFIG_NET_ACT_MPLS=m
-CONFIG_NET_ACT_VLAN=m
-CONFIG_NET_ACT_BPF=m
-CONFIG_NET_ACT_CONNMARK=m
-CONFIG_NET_ACT_CTINFO=m
-CONFIG_NET_ACT_SKBMOD=m
-CONFIG_NET_ACT_IFE=m
-CONFIG_NET_ACT_TUNNEL_KEY=m
-CONFIG_NET_ACT_CT=m
-CONFIG_NET_ACT_GATE=m
-CONFIG_NET_IFE_SKBMARK=m
-CONFIG_NET_IFE_SKBPRIO=m
-CONFIG_NET_IFE_SKBTCINDEX=m
-# CONFIG_NET_TC_SKB_EXT is not set
-CONFIG_NET_SCH_FIFO=y
-CONFIG_DCB=y
-CONFIG_DNS_RESOLVER=y
-CONFIG_BATMAN_ADV=m
-# CONFIG_BATMAN_ADV_BATMAN_V is not set
-CONFIG_BATMAN_ADV_BLA=y
-CONFIG_BATMAN_ADV_DAT=y
-CONFIG_BATMAN_ADV_NC=y
-CONFIG_BATMAN_ADV_MCAST=y
-CONFIG_BATMAN_ADV_DEBUGFS=y
-# CONFIG_BATMAN_ADV_DEBUG is not set
-CONFIG_BATMAN_ADV_SYSFS=y
-# CONFIG_BATMAN_ADV_TRACING is not set
-CONFIG_OPENVSWITCH=m
-CONFIG_OPENVSWITCH_GRE=m
-CONFIG_OPENVSWITCH_VXLAN=m
-CONFIG_OPENVSWITCH_GENEVE=m
-CONFIG_VSOCKETS=m
-CONFIG_VSOCKETS_DIAG=m
-CONFIG_VSOCKETS_LOOPBACK=m
-CONFIG_VMWARE_VMCI_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS_COMMON=m
-CONFIG_HYPERV_VSOCKETS=m
-CONFIG_NETLINK_DIAG=m
-CONFIG_MPLS=y
-CONFIG_NET_MPLS_GSO=m
-CONFIG_MPLS_ROUTING=m
-CONFIG_MPLS_IPTUNNEL=m
-CONFIG_NET_NSH=m
-CONFIG_HSR=m
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_L3_MASTER_DEV=y
-CONFIG_QRTR=m
-CONFIG_QRTR_SMD=m
-CONFIG_QRTR_TUN=m
-CONFIG_QRTR_MHI=m
-# CONFIG_NET_NCSI is not set
-CONFIG_PCPU_DEV_REFCNT=y
-CONFIG_RPS=y
-CONFIG_RFS_ACCEL=y
-CONFIG_XPS=y
-CONFIG_CGROUP_NET_PRIO=y
-CONFIG_CGROUP_NET_CLASSID=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_BQL=y
-CONFIG_BPF_JIT=y
-CONFIG_BPF_STREAM_PARSER=y
-CONFIG_NET_FLOW_LIMIT=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NET_DROP_MONITOR is not set
-# end of Network testing
-# end of Networking options
-
-CONFIG_HAMRADIO=y
-
-#
-# Packet Radio protocols
-#
-CONFIG_AX25=m
-CONFIG_AX25_DAMA_SLAVE=y
-CONFIG_NETROM=m
-CONFIG_ROSE=m
-
-#
-# AX.25 network device drivers
-#
-CONFIG_MKISS=m
-CONFIG_6PACK=m
-CONFIG_BPQETHER=m
-# CONFIG_SCC is not set
-CONFIG_BAYCOM_SER_FDX=m
-CONFIG_BAYCOM_SER_HDX=m
-CONFIG_BAYCOM_PAR=m
-# CONFIG_BAYCOM_EPP is not set
-CONFIG_YAM=m
-# end of AX.25 network device drivers
-
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_GW=m
-CONFIG_CAN_J1939=m
-CONFIG_CAN_ISOTP=m
-CONFIG_CAN_ETAS_ES58X=m
-
-#
-# CAN Device Drivers
-#
-CONFIG_CAN_VCAN=m
-CONFIG_CAN_VXCAN=m
-CONFIG_CAN_SLCAN=m
-CONFIG_CAN_DEV=m
-CONFIG_CAN_CALC_BITTIMING=y
-CONFIG_CAN_JANZ_ICAN3=m
-CONFIG_CAN_KVASER_PCIEFD=m
-CONFIG_PCH_CAN=m
-CONFIG_CAN_C_CAN=m
-CONFIG_CAN_C_CAN_PLATFORM=m
-CONFIG_CAN_C_CAN_PCI=m
-CONFIG_CAN_CC770=m
-CONFIG_CAN_CC770_ISA=m
-CONFIG_CAN_CC770_PLATFORM=m
-CONFIG_CAN_IFI_CANFD=m
-CONFIG_CAN_M_CAN=m
-CONFIG_CAN_M_CAN_PCI=m
-CONFIG_CAN_M_CAN_PLATFORM=m
-CONFIG_CAN_M_CAN_TCAN4X5X=m
-CONFIG_CAN_PEAK_PCIEFD=m
-CONFIG_CAN_SJA1000=m
-CONFIG_CAN_EMS_PCI=m
-CONFIG_CAN_EMS_PCMCIA=m
-CONFIG_CAN_F81601=m
-CONFIG_CAN_KVASER_PCI=m
-CONFIG_CAN_PEAK_PCI=m
-CONFIG_CAN_PEAK_PCIEC=y
-CONFIG_CAN_PEAK_PCMCIA=m
-CONFIG_CAN_PLX_PCI=m
-CONFIG_CAN_SJA1000_ISA=m
-CONFIG_CAN_SJA1000_PLATFORM=m
-# CONFIG_CAN_TSCAN1 is not set
-CONFIG_CAN_SOFTING=m
-CONFIG_CAN_SOFTING_CS=m
-
-#
-# CAN SPI interfaces
-#
-CONFIG_CAN_HI311X=m
-CONFIG_CAN_MCP251X=m
-CONFIG_CAN_MCP251XFD=m
-# CONFIG_CAN_MCP251XFD_SANITY is not set
-# end of CAN SPI interfaces
-
-#
-# CAN USB interfaces
-#
-CONFIG_CAN_8DEV_USB=m
-CONFIG_CAN_EMS_USB=m
-CONFIG_CAN_ESD_USB2=m
-CONFIG_CAN_GS_USB=m
-CONFIG_CAN_KVASER_USB=m
-CONFIG_CAN_MCBA_USB=m
-CONFIG_CAN_PEAK_USB=m
-CONFIG_CAN_UCAN=m
-# end of CAN USB interfaces
-
-# CONFIG_CAN_DEBUG_DEVICES is not set
-# end of CAN Device Drivers
-
-CONFIG_BT=m
-CONFIG_BT_BREDR=y
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_CMTP=m
-CONFIG_BT_HIDP=m
-CONFIG_BT_HS=y
-CONFIG_BT_LE=y
-CONFIG_BT_6LOWPAN=m
-CONFIG_BT_LEDS=y
-CONFIG_BT_MSFTEXT=y
-CONFIG_BT_AOSPEXT=y
-CONFIG_BT_DEBUGFS=y
-# CONFIG_BT_SELFTEST is not set
-# CONFIG_BT_FEATURE_DEBUG is not set
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_INTEL=m
-CONFIG_BT_BCM=m
-CONFIG_BT_RTL=m
-CONFIG_BT_QCA=m
-CONFIG_BT_HCIBTUSB=m
-# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
-CONFIG_BT_HCIBTUSB_BCM=y
-CONFIG_BT_HCIBTUSB_MTK=y
-CONFIG_BT_HCIBTUSB_RTL=y
-CONFIG_BT_HCIBTSDIO=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_SERDEV=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_NOKIA=m
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_ATH3K=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIUART_3WIRE=y
-CONFIG_BT_HCIUART_INTEL=y
-CONFIG_BT_HCIUART_RTL=y
-CONFIG_BT_HCIUART_QCA=y
-CONFIG_BT_HCIUART_AG6XX=y
-CONFIG_BT_HCIUART_MRVL=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIDTL1=m
-CONFIG_BT_HCIBT3C=m
-CONFIG_BT_HCIBLUECARD=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_BT_MRVL=m
-CONFIG_BT_MRVL_SDIO=m
-CONFIG_BT_ATH3K=m
-CONFIG_BT_MTKSDIO=m
-CONFIG_BT_MTKUART=m
-CONFIG_BT_VIRTIO=m
-CONFIG_BT_HCIRSI=m
-# end of Bluetooth device drivers
-
-CONFIG_AF_RXRPC=m
-CONFIG_AF_RXRPC_IPV6=y
-# CONFIG_AF_RXRPC_INJECT_LOSS is not set
-# CONFIG_AF_RXRPC_DEBUG is not set
-# CONFIG_RXKAD is not set
-CONFIG_AF_KCM=m
-CONFIG_STREAM_PARSER=y
-CONFIG_FIB_RULES=y
-CONFIG_WIRELESS=y
-CONFIG_WIRELESS_EXT=y
-# CONFIG_WEXT_CORE is not set
-# CONFIG_WEXT_PROC is not set
-# CONFIG_WEXT_SPY is not set
-# CONFIG_WEXT_PRIV is not set
-CONFIG_CFG80211=m
-CONFIG_NL80211_TESTMODE=y
-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
-CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
-CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
-CONFIG_CFG80211_DEFAULT_PS=y
-# CONFIG_CFG80211_DEBUGFS is not set
-CONFIG_CFG80211_CRDA_SUPPORT=y
-# CONFIG_CFG80211_WEXT is not set
-# CONFIG_CFG80211_WEXT_EXPORT is not set
-CONFIG_LIB80211=m
-CONFIG_LIB80211_CRYPT_WEP=m
-CONFIG_LIB80211_CRYPT_CCMP=m
-CONFIG_LIB80211_CRYPT_TKIP=m
-# CONFIG_LIB80211_DEBUG is not set
-CONFIG_MAC80211=m
-CONFIG_MAC80211_HAS_RC=y
-CONFIG_MAC80211_RC_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
-CONFIG_MAC80211_MESH=y
-CONFIG_MAC80211_LEDS=y
-# CONFIG_MAC80211_DEBUGFS is not set
-# CONFIG_MAC80211_MESSAGE_TRACING is not set
-# CONFIG_MAC80211_DEBUG_MENU is not set
-CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
-CONFIG_WIMAX=m
-CONFIG_WIMAX_DEBUG_LEVEL=8
-CONFIG_RFKILL=m
-CONFIG_RFKILL_LEDS=y
-# CONFIG_RFKILL_INPUT is not set
-CONFIG_RFKILL_GPIO=m
-CONFIG_NET_9P=m
-CONFIG_NET_9P_VIRTIO=m
-CONFIG_NET_9P_RDMA=m
-# CONFIG_NET_9P_DEBUG is not set
-CONFIG_CAIF=m
-# CONFIG_CAIF_DEBUG is not set
-CONFIG_CAIF_NETDEV=m
-CONFIG_CAIF_USB=m
-CONFIG_CEPH_LIB=m
-# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
-CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
-CONFIG_NFC=m
-CONFIG_NFC_DIGITAL=m
-CONFIG_NFC_NCI=m
-CONFIG_NFC_NCI_SPI=m
-CONFIG_NFC_NCI_UART=m
-CONFIG_NFC_HCI=m
-CONFIG_NFC_SHDLC=y
-
-#
-# Near Field Communication (NFC) devices
-#
-CONFIG_NFC_TRF7970A=m
-CONFIG_NFC_MEI_PHY=m
-CONFIG_NFC_SIM=m
-CONFIG_NFC_PORT100=m
-CONFIG_NFC_VIRTUAL_NCI=m
-CONFIG_NFC_FDP=m
-CONFIG_NFC_FDP_I2C=m
-CONFIG_NFC_PN544=m
-CONFIG_NFC_PN544_I2C=m
-CONFIG_NFC_PN544_MEI=m
-CONFIG_NFC_PN533=m
-CONFIG_NFC_PN533_USB=m
-CONFIG_NFC_PN533_I2C=m
-CONFIG_NFC_PN532_UART=m
-CONFIG_NFC_MICROREAD=m
-CONFIG_NFC_MICROREAD_I2C=m
-CONFIG_NFC_MICROREAD_MEI=m
-CONFIG_NFC_MRVL=m
-CONFIG_NFC_MRVL_USB=m
-CONFIG_NFC_MRVL_UART=m
-CONFIG_NFC_MRVL_I2C=m
-CONFIG_NFC_MRVL_SPI=m
-CONFIG_NFC_ST21NFCA=m
-CONFIG_NFC_ST21NFCA_I2C=m
-CONFIG_NFC_ST_NCI=m
-CONFIG_NFC_ST_NCI_I2C=m
-CONFIG_NFC_ST_NCI_SPI=m
-CONFIG_NFC_NXP_NCI=m
-CONFIG_NFC_NXP_NCI_I2C=m
-CONFIG_NFC_S3FWRN5=m
-CONFIG_NFC_S3FWRN5_I2C=m
-CONFIG_NFC_S3FWRN82_UART=m
-CONFIG_NFC_ST95HF=m
-# end of Near Field Communication (NFC) devices
-
-CONFIG_PSAMPLE=m
-CONFIG_NET_IFE=m
-CONFIG_LWTUNNEL=y
-CONFIG_LWTUNNEL_BPF=y
-# CONFIG_PAGE_POOL_STATS is not set
-CONFIG_DST_CACHE=y
-CONFIG_GRO_CELLS=y
-CONFIG_NET_SOCK_MSG=y
-CONFIG_NET_DEVLINK=y
-CONFIG_PAGE_POOL=y
-CONFIG_FAILOVER=m
-CONFIG_ETHTOOL_NETLINK=y
-CONFIG_HAVE_EBPF_JIT=y
-
-#
-# Device Drivers
-#
-CONFIG_HAVE_EISA=y
-# CONFIG_EISA is not set
-CONFIG_HAVE_PCI=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_HOTPLUG_PCI_PCIE=y
-CONFIG_PCIEAER=y
-# CONFIG_PCIEAER_INJECT is not set
-CONFIG_PCIE_ECRC=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-CONFIG_PCIE_PME=y
-CONFIG_PCIE_DPC=y
-CONFIG_PCIE_PTM=y
-# CONFIG_PCIE_BW is not set
-CONFIG_PCIE_EDR=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_QUIRKS=y
-# CONFIG_PCI_DEBUG is not set
-CONFIG_PCI_REALLOC_ENABLE_AUTO=y
-CONFIG_PCI_STUB=m
-CONFIG_PCI_PF_STUB=m
-CONFIG_PCI_ATS=y
-CONFIG_PCI_LOCKLESS_CONFIG=y
-CONFIG_PCI_IOV=y
-CONFIG_PCI_PRI=y
-CONFIG_PCI_PASID=y
-CONFIG_PCI_LABEL=y
-# CONFIG_PCIE_BUS_TUNE_OFF is not set
-CONFIG_PCIE_BUS_DEFAULT=y
-# CONFIG_PCIE_BUS_SAFE is not set
-# CONFIG_PCIE_BUS_PERFORMANCE is not set
-# CONFIG_PCIE_BUS_PEER2PEER is not set
-CONFIG_HOTPLUG_PCI=y
-# CONFIG_HOTPLUG_PCI_COMPAQ is not set
-# CONFIG_HOTPLUG_PCI_IBM is not set
-CONFIG_HOTPLUG_PCI_ACPI=y
-CONFIG_HOTPLUG_PCI_ACPI_IBM=m
-CONFIG_HOTPLUG_PCI_CPCI=y
-CONFIG_HOTPLUG_PCI_CPCI_ZT5550=m
-CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m
-CONFIG_HOTPLUG_PCI_SHPC=y
-
-#
-# PCI controller drivers
-#
-
-#
-# DesignWare PCI Core Support
-#
-# CONFIG_PCIE_DW_PLAT_HOST is not set
-# CONFIG_PCIE_DW_PLAT_EP is not set
-# CONFIG_PCI_MESON is not set
-# end of DesignWare PCI Core Support
-
-#
-# Mobiveil PCIe Core Support
-#
-# end of Mobiveil PCIe Core Support
-
-#
-# Cadence PCIe controllers support
-#
-# end of Cadence PCIe controllers support
-# end of PCI controller drivers
-
-#
-# PCI Endpoint
-#
-CONFIG_PCI_ENDPOINT=y
-CONFIG_PCI_ENDPOINT_CONFIGFS=y
-# CONFIG_PCI_EPF_TEST is not set
-CONFIG_PCI_EPF_NTB=m
-# end of PCI Endpoint
-CONFIG_CXL_BUS=m
-CONFIG_CXL_PCI=m
-CONFIG_CXL_MEM=m
-CONFIG_CXL_MEM_RAW_COMMANDS=y
-CONFIG_CXL_ACPI=m
-CONFIG_CXL_PMEM=m
-
-#
-# PCI switch controller drivers
-#
-CONFIG_PCI_SW_SWITCHTEC=m
-# end of PCI switch controller drivers
-
-CONFIG_PCCARD=m
-CONFIG_PCMCIA=m
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_CARDBUS=y
-
-#
-# PC-card bridges
-#
-CONFIG_YENTA=m
-CONFIG_YENTA_O2=y
-CONFIG_YENTA_RICOH=y
-CONFIG_YENTA_TI=y
-CONFIG_YENTA_ENE_TUNE=y
-CONFIG_YENTA_TOSHIBA=y
-CONFIG_PD6729=m
-CONFIG_I82092=m
-# CONFIG_I82365 is not set
-# CONFIG_TCIC is not set
-CONFIG_PCMCIA_PROBE=y
-CONFIG_PCCARD_NONSTATIC=y
-CONFIG_RAPIDIO=m
-CONFIG_RAPIDIO_TSI721=m
-CONFIG_RAPIDIO_DISC_TIMEOUT=30
-CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y
-CONFIG_RAPIDIO_DMA_ENGINE=y
-# CONFIG_RAPIDIO_DEBUG is not set
-CONFIG_RAPIDIO_ENUM_BASIC=m
-CONFIG_RAPIDIO_CHMAN=m
-CONFIG_RAPIDIO_MPORT_CDEV=m
-
-#
-# RapidIO Switch drivers
-#
-CONFIG_RAPIDIO_TSI57X=m
-CONFIG_RAPIDIO_CPS_XX=m
-CONFIG_RAPIDIO_TSI568=m
-CONFIG_RAPIDIO_CPS_GEN2=m
-CONFIG_RAPIDIO_RXS_GEN3=m
-# end of RapidIO Switch drivers
-
-#
-# Generic Driver Options
-#
-# CONFIG_UEVENT_HELPER is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-
-#
-# Firmware loader
-#
-CONFIG_FW_LOADER=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_FW_LOADER_USER_HELPER is not set
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_FW_LOADER_COMPRESS=y
-CONFIG_FW_CACHE=y
-# end of Firmware loader
-
-CONFIG_WANT_DEV_COREDUMP=y
-CONFIG_ALLOW_DEV_COREDUMP=y
-CONFIG_DEV_COREDUMP=y
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
-CONFIG_HMEM_REPORTING=y
-CONFIG_TEST_ASYNC_DRIVER_PROBE=m
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=m
-CONFIG_REGMAP_SLIMBUS=m
-CONFIG_REGMAP_SPI=y
-CONFIG_REGMAP_SPMI=m
-CONFIG_REGMAP_W1=m
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_SOUNDWIRE=m
-CONFIG_REGMAP_SCCB=m
-CONFIG_REGMAP_I3C=m
-CONFIG_REGMAP_SPI_AVMM=m
-CONFIG_DMA_SHARED_BUFFER=y
-# CONFIG_DMA_FENCE_TRACE is not set
-# end of Generic Driver Options
-
-#
-# Bus devices
-#
-CONFIG_MHI_BUS=m
-CONFIG_MHI_BUS_DEBUG=y
-CONFIG_MHI_BUS_PCI_GENERIC=m
-# end of Bus devices
-
-CONFIG_CONNECTOR=m
-CONFIG_GNSS=m
-CONFIG_GNSS_SERIAL=m
-CONFIG_GNSS_MTK_SERIAL=m
-CONFIG_GNSS_SIRF_SERIAL=m
-CONFIG_GNSS_UBX_SERIAL=m
-CONFIG_MTD=m
-CONFIG_MTD_TESTS=m
-
-#
-# Partition parsers
-#
-CONFIG_MTD_AR7_PARTS=m
-CONFIG_MTD_CMDLINE_PARTS=m
-CONFIG_MTD_REDBOOT_PARTS=m
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-CONFIG_MTD_QCOMSMEM_PARTS=m
-# end of Partition parsers
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
-CONFIG_MTD_BLOCK_RO=m
-CONFIG_FTL=m
-CONFIG_NFTL=m
-CONFIG_NFTL_RW=y
-CONFIG_INFTL=m
-CONFIG_RFD_FTL=m
-CONFIG_SSFDC=m
-CONFIG_SM_FTL=m
-CONFIG_MTD_OOPS=m
-CONFIG_MTD_PSTORE=m
-CONFIG_MTD_SWAP=m
-# CONFIG_MTD_PARTITIONED_MASTER is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_GEN_PROBE=m
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-CONFIG_MTD_CFI_INTELEXT=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_CFI_STAA=m
-CONFIG_MTD_CFI_UTIL=m
-CONFIG_MTD_RAM=m
-CONFIG_MTD_ROM=m
-CONFIG_MTD_ABSENT=m
-# end of RAM/ROM/Flash chip drivers
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=m
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-# CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set
-CONFIG_MTD_SBC_GXX=m
-CONFIG_MTD_AMD76XROM=m
-CONFIG_MTD_ICHXROM=m
-CONFIG_MTD_ESB2ROM=m
-CONFIG_MTD_CK804XROM=m
-CONFIG_MTD_SCB2_FLASH=m
-CONFIG_MTD_NETtel=m
-CONFIG_MTD_L440GX=m
-CONFIG_MTD_PCI=m
-CONFIG_MTD_PCMCIA=m
-# CONFIG_MTD_PCMCIA_ANONYMOUS is not set
-CONFIG_MTD_INTEL_VR_NOR=m
-CONFIG_MTD_PLATRAM=m
-# end of Mapping drivers for chip access
-
-#
-# Self-contained MTD device drivers
-#
-CONFIG_MTD_PMC551=m
-CONFIG_MTD_PMC551_BUGFIX=y
-# CONFIG_MTD_PMC551_DEBUG is not set
-CONFIG_MTD_DATAFLASH=m
-CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
-CONFIG_MTD_DATAFLASH_OTP=y
-CONFIG_MTD_MCHP23K256=m
-CONFIG_MTD_MCHP48L640=m
-CONFIG_MTD_SST25L=m
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTDRAM_TOTAL_SIZE=4096
-CONFIG_MTDRAM_ERASE_SIZE=128
-CONFIG_MTD_BLOCK2MTD=m
-
-#
-# Disk-On-Chip Device Drivers
-#
-CONFIG_MTD_DOCG3=m
-CONFIG_BCH_CONST_M=14
-CONFIG_BCH_CONST_T=4
-# end of Self-contained MTD device drivers
-
-#
-# NAND
-#
-CONFIG_MTD_NAND_CORE=m
-CONFIG_MTD_ONENAND=m
-CONFIG_MTD_ONENAND_VERIFY_WRITE=y
-CONFIG_MTD_ONENAND_GENERIC=m
-CONFIG_MTD_ONENAND_OTP=y
-CONFIG_MTD_ONENAND_2X_PROGRAM=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=m
-# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
-CONFIG_MTD_RAW_NAND=m
-CONFIG_MTD_NAND_ECC_SW_BCH=y
-CONFIG_MTD_NAND_ECC_MXIC=y
-
-#
-# Raw/parallel NAND flash controllers
-#
-CONFIG_MTD_NAND_DENALI=m
-CONFIG_MTD_NAND_DENALI_PCI=m
-CONFIG_MTD_NAND_CAFE=m
-# CONFIG_MTD_NAND_CS553X is not set
-CONFIG_MTD_NAND_MXIC=m
-CONFIG_MTD_NAND_GPIO=m
-CONFIG_MTD_NAND_PLATFORM=m
-CONFIG_MTD_NAND_ARASAN=m
-CONFIG_MTD_NAND_INTEL_LGM=m
-CONFIG_MTD_NAND_ROCKCHIP=m
-CONFIG_MTD_NAND_PL35X=m
-
-#
-# Misc
-#
-CONFIG_MTD_SM_COMMON=m
-CONFIG_MTD_NAND_NANDSIM=m
-CONFIG_MTD_NAND_RICOH=m
-CONFIG_MTD_NAND_DISKONCHIP=m
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
-CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
-CONFIG_MTD_SPI_NAND=m
-
-#
-# ECC engine support
-#
-CONFIG_MTD_NAND_ECC=y
-# end of ECC engine support
-# end of NAND
-
-#
-# LPDDR & LPDDR2 PCM memory drivers
-#
-CONFIG_MTD_LPDDR=m
-CONFIG_MTD_QINFO_PROBE=m
-# end of LPDDR & LPDDR2 PCM memory drivers
-
-CONFIG_MTD_SPI_NOR=m
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SPI_NOR_SWP_DISABLE=y
-# CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE is not set
-# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
-CONFIG_SPI_INTEL_SPI=m
-CONFIG_SPI_INTEL_SPI_PCI=m
-CONFIG_SPI_INTEL_SPI_PLATFORM=m
-CONFIG_MTD_UBI=m
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_FASTMAP=y
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_HYPERBUS=m
-# CONFIG_OF is not set
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_PARPORT=m
-CONFIG_PARPORT_PC=m
-CONFIG_PARPORT_SERIAL=m
-CONFIG_PARPORT_PC_FIFO=y
-CONFIG_PARPORT_PC_SUPERIO=y
-CONFIG_PARPORT_PC_PCMCIA=m
-CONFIG_PARPORT_AX88796=m
-CONFIG_PARPORT_1284=y
-CONFIG_PARPORT_NOT_PC=y
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG_MESSAGES is not set
-
-#
-# Protocols
-#
-CONFIG_ISAPNP=y
-CONFIG_PNPBIOS=y
-CONFIG_PNPBIOS_PROC_FS=y
-CONFIG_PNPACPI=y
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_NULL_BLK is not set
-CONFIG_BLK_DEV_FD=m
-CONFIG_BLK_DEV_FD_RAWCMD=y
-CONFIG_CDROM=m
-# CONFIG_PARIDE is not set
-CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
-CONFIG_ZRAM=m
-# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
-CONFIG_ZRAM_DEF_COMP_ZSTD=y
-# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
-# CONFIG_ZRAM_DEF_COMP_LZO is not set
-# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
-# CONFIG_ZRAM_DEF_COMP_842 is not set
-CONFIG_ZRAM_WRITEBACK=y
-# CONFIG_ZRAM_MEMORY_TRACKING is not set
-CONFIG_BLK_DEV_UMEM=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_DRBD=m
-# CONFIG_DRBD_FAULT_INJECTION is not set
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_SX8=m
-CONFIG_BLK_DEV_RAM=m
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-CONFIG_CDROM_PKTCDVD_WCACHE=y
-CONFIG_ATA_OVER_ETH=m
-CONFIG_VIRTIO_BLK=m
-CONFIG_BLK_DEV_RBD=m
-CONFIG_BLK_DEV_RSXX=m
-CONFIG_BLK_DEV_RNBD=y
-CONFIG_BLK_DEV_RNBD_CLIENT=m
-CONFIG_BLK_DEV_RNBD_SERVER=m
-
-#
-# NVME Support
-#
-CONFIG_NVME_CORE=m
-CONFIG_BLK_DEV_NVME=m
-# CONFIG_NVME_MULTIPATH is not set
-CONFIG_NVME_VERBOSE_ERRORS=y
-CONFIG_NVME_HWMON=y
-CONFIG_NVME_FABRICS=m
-CONFIG_NVME_RDMA=m
-CONFIG_NVME_FC=m
-CONFIG_NVME_TCP=m
-CONFIG_NVME_TARGET=m
-CONFIG_NVME_TARGET_PASSTHRU=y
-CONFIG_NVME_TARGET_LOOP=m
-CONFIG_NVME_TARGET_RDMA=m
-CONFIG_NVME_TARGET_FC=m
-CONFIG_NVME_TARGET_FCLOOP=m
-CONFIG_NVME_TARGET_TCP=m
-# end of NVME Support
-
-#
-# Misc devices
-#
-CONFIG_SENSORS_LIS3LV02D=m
-CONFIG_AD525X_DPOT=m
-CONFIG_AD525X_DPOT_I2C=m
-CONFIG_AD525X_DPOT_SPI=m
-# CONFIG_DUMMY_IRQ is not set
-CONFIG_IBM_ASM=m
-CONFIG_PHANTOM=m
-CONFIG_TIFM_CORE=m
-CONFIG_TIFM_7XX1=m
-CONFIG_ICS932S401=m
-CONFIG_ENCLOSURE_SERVICES=m
-CONFIG_HP_ILO=m
-CONFIG_APDS9802ALS=m
-CONFIG_ISL29003=m
-CONFIG_ISL29020=m
-CONFIG_SENSORS_TSL2550=m
-CONFIG_SENSORS_BH1770=m
-CONFIG_SENSORS_APDS990X=m
-CONFIG_HMC6352=m
-CONFIG_DS1682=m
-CONFIG_VMWARE_BALLOON=m
-CONFIG_PCH_PHUB=m
-CONFIG_LATTICE_ECP3_CONFIG=m
-CONFIG_SRAM=y
-CONFIG_DW_XDATA_PCIE=m
-CONFIG_PCI_ENDPOINT_TEST=m
-CONFIG_XILINX_SDFEC=m
-CONFIG_MISC_RTSX=m
-CONFIG_PVPANIC=m
-CONFIG_GP_PCI1XXXX=m
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-CONFIG_EEPROM_AT24=m
-CONFIG_EEPROM_AT25=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_EEPROM_MAX6875=m
-CONFIG_EEPROM_93CX6=m
-CONFIG_EEPROM_93XX46=m
-CONFIG_EEPROM_IDT_89HPESX=m
-CONFIG_EEPROM_EE1004=m
-# end of EEPROM support
-
-CONFIG_CB710_CORE=m
-# CONFIG_CB710_DEBUG is not set
-CONFIG_CB710_DEBUG_ASSUMPTIONS=y
-
-#
-# Texas Instruments shared transport line discipline
-#
-CONFIG_TI_ST=m
-# end of Texas Instruments shared transport line discipline
-
-CONFIG_SENSORS_LIS3_I2C=m
-
-#
-# Altera FPGA firmware download module (requires I2C)
-#
-CONFIG_ALTERA_STAPL=m
-CONFIG_INTEL_MEI=y
-CONFIG_INTEL_MEI_ME=y
-CONFIG_INTEL_MEI_TXE=m
-CONFIG_INTEL_MEI_VIRTIO=m
-CONFIG_INTEL_MEI_HDCP=m
-CONFIG_INTEL_MEI_PXP=m
-CONFIG_VMWARE_VMCI=m
-
-#
-# Intel MIC & related support
-#
-CONFIG_VOP_BUS=m
-CONFIG_VOP=m
-# end of Intel MIC & related support
-
-CONFIG_ECHO=m
-CONFIG_BCM_VK=m
-CONFIG_BCM_VK_TTY=y
-CONFIG_MISC_ALCOR_PCI=m
-CONFIG_MISC_RTSX_PCI=m
-CONFIG_MISC_RTSX_USB=m
-CONFIG_HABANA_AI=m
-CONFIG_UACCE=m
-CONFIG_PVPANIC=y
-CONFIG_PVPANIC_MMIO=m
-CONFIG_PVPANIC_PCI=m
-# end of Misc devices
-
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=m
-CONFIG_RAID_ATTRS=m
-CONFIG_SCSI=m
-CONFIG_SCSI_DMA=y
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_ENCLOSURE=m
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_ISCSI_ATTRS=m
-CONFIG_SCSI_SAS_ATTRS=m
-CONFIG_SCSI_SAS_LIBSAS=m
-CONFIG_SCSI_SAS_ATA=y
-CONFIG_SCSI_SAS_HOST_SMP=y
-CONFIG_SCSI_SRP_ATTRS=m
-# end of SCSI Transports
-
-CONFIG_SCSI_LOWLEVEL=y
-CONFIG_ISCSI_TCP=m
-CONFIG_ISCSI_BOOT_SYSFS=m
-CONFIG_SCSI_CXGB3_ISCSI=m
-CONFIG_SCSI_CXGB4_ISCSI=m
-CONFIG_SCSI_BNX2_ISCSI=m
-CONFIG_SCSI_BNX2X_FCOE=m
-CONFIG_BE2ISCSI=m
-CONFIG_BLK_DEV_3W_XXXX_RAID=m
-CONFIG_SCSI_HPSA=m
-CONFIG_SCSI_3W_9XXX=m
-CONFIG_SCSI_3W_SAS=m
-CONFIG_SCSI_ACARD=m
-CONFIG_SCSI_AHA152X=m
-CONFIG_SCSI_AHA1542=m
-CONFIG_SCSI_AACRAID=m
-CONFIG_SCSI_AIC7XXX=m
-CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
-CONFIG_AIC7XXX_RESET_DELAY_MS=15000
-# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
-CONFIG_AIC7XXX_DEBUG_MASK=0
-# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC79XX=m
-CONFIG_AIC79XX_CMDS_PER_DEVICE=4
-CONFIG_AIC79XX_RESET_DELAY_MS=15000
-# CONFIG_AIC79XX_DEBUG_ENABLE is not set
-CONFIG_AIC79XX_DEBUG_MASK=0
-# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC94XX=m
-# CONFIG_AIC94XX_DEBUG is not set
-CONFIG_SCSI_MVSAS=m
-# CONFIG_SCSI_MVSAS_DEBUG is not set
-CONFIG_SCSI_MVSAS_TASKLET=y
-CONFIG_SCSI_MVUMI=m
-CONFIG_SCSI_DPT_I2O=m
-CONFIG_SCSI_ADVANSYS=m
-CONFIG_SCSI_ARCMSR=m
-CONFIG_SCSI_ESAS2R=m
-CONFIG_MEGARAID_NEWGEN=y
-CONFIG_MEGARAID_MM=m
-CONFIG_MEGARAID_MAILBOX=m
-CONFIG_MEGARAID_LEGACY=m
-CONFIG_MEGARAID_SAS=m
-CONFIG_SCSI_MPT3SAS=m
-CONFIG_SCSI_MPT2SAS_MAX_SGE=128
-CONFIG_SCSI_MPT3SAS_MAX_SGE=128
-CONFIG_SCSI_MPT2SAS=m
-CONFIG_SCSI_MPI3MR=m
-CONFIG_SCSI_SMARTPQI=m
-CONFIG_SCSI_UFSHCD=m
-CONFIG_SCSI_UFSHCD_PCI=m
-CONFIG_SCSI_UFS_DWC_TC_PCI=m
-CONFIG_SCSI_UFSHCD_PLATFORM=m
-CONFIG_SCSI_UFS_CDNS_PLATFORM=m
-CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m
-# CONFIG_SCSI_UFS_BSG is not set
-CONFIG_SCSI_HPTIOP=m
-CONFIG_SCSI_BUSLOGIC=m
-CONFIG_SCSI_FLASHPOINT=y
-CONFIG_SCSI_MYRB=m
-CONFIG_SCSI_MYRS=m
-CONFIG_VMWARE_PVSCSI=m
-CONFIG_HYPERV_STORAGE=m
-CONFIG_LIBFC=m
-CONFIG_LIBFCOE=m
-CONFIG_FCOE=m
-CONFIG_FCOE_FNIC=m
-CONFIG_SCSI_SNIC=m
-# CONFIG_SCSI_SNIC_DEBUG_FS is not set
-CONFIG_SCSI_DMX3191D=m
-CONFIG_SCSI_FDOMAIN=m
-CONFIG_SCSI_FDOMAIN_PCI=m
-CONFIG_SCSI_FDOMAIN_ISA=m
-CONFIG_SCSI_GDTH=m
-CONFIG_SCSI_ISCI=m
-CONFIG_SCSI_GENERIC_NCR5380=m
-CONFIG_SCSI_IPS=m
-CONFIG_SCSI_INITIO=m
-CONFIG_SCSI_INIA100=m
-CONFIG_SCSI_PPA=m
-CONFIG_SCSI_IMM=m
-# CONFIG_SCSI_IZIP_EPP16 is not set
-# CONFIG_SCSI_IZIP_SLOW_CTR is not set
-CONFIG_SCSI_STEX=m
-CONFIG_SCSI_SYM53C8XX_2=m
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_IPR=m
-# CONFIG_SCSI_IPR_TRACE is not set
-# CONFIG_SCSI_IPR_DUMP is not set
-CONFIG_SCSI_QLOGIC_FAS=m
-CONFIG_SCSI_QLOGIC_1280=m
-CONFIG_SCSI_QLA_FC=m
-CONFIG_TCM_QLA2XXX=m
-# CONFIG_TCM_QLA2XXX_DEBUG is not set
-CONFIG_SCSI_QLA_ISCSI=m
-CONFIG_QEDI=m
-CONFIG_QEDF=m
-CONFIG_SCSI_LPFC=m
-CONFIG_SCSI_EFCT=m
-# CONFIG_SCSI_LPFC_DEBUG_FS is not set
-CONFIG_SCSI_DC395x=m
-CONFIG_SCSI_AM53C974=m
-CONFIG_SCSI_NSP32=m
-CONFIG_SCSI_WD719X=m
-# CONFIG_SCSI_DEBUG is not set
-CONFIG_SCSI_PMCRAID=m
-CONFIG_SCSI_PM8001=m
-CONFIG_SCSI_BFA_FC=m
-CONFIG_SCSI_VIRTIO=m
-CONFIG_SCSI_CHELSIO_FCOE=m
-CONFIG_SCSI_LOWLEVEL_PCMCIA=y
-CONFIG_PCMCIA_AHA152X=m
-CONFIG_PCMCIA_FDOMAIN=m
-CONFIG_PCMCIA_NINJA_SCSI=m
-CONFIG_PCMCIA_QLOGIC=m
-CONFIG_PCMCIA_SYM53C500=m
-CONFIG_SCSI_DH=y
-CONFIG_SCSI_DH_RDAC=m
-CONFIG_SCSI_DH_HP_SW=m
-CONFIG_SCSI_DH_EMC=m
-CONFIG_SCSI_DH_ALUA=m
-# end of SCSI device support
-
-CONFIG_ATA=m
-CONFIG_SATA_HOST=y
-CONFIG_PATA_TIMINGS=y
-# CONFIG_ATA_VERBOSE_ERROR is not set
-CONFIG_ATA_FORCE=y
-CONFIG_ATA_ACPI=y
-CONFIG_SATA_ZPODD=y
-CONFIG_SATA_PMP=y
-
-#
-# Controllers with non-SFF native interface
-#
-CONFIG_SATA_AHCI=m
-CONFIG_SATA_MOBILE_LPM_POLICY=0
-CONFIG_SATA_AHCI_PLATFORM=m
-CONFIG_SATA_INIC162X=m
-CONFIG_SATA_ACARD_AHCI=m
-CONFIG_SATA_SIL24=m
-CONFIG_ATA_SFF=y
-
-#
-# SFF controllers with custom DMA interface
-#
-CONFIG_PDC_ADMA=m
-CONFIG_SATA_QSTOR=m
-CONFIG_SATA_SX4=m
-CONFIG_ATA_BMDMA=y
-
-#
-# SATA SFF controllers with BMDMA
-#
-CONFIG_ATA_PIIX=m
-CONFIG_SATA_DWC=m
-# CONFIG_SATA_DWC_OLD_DMA is not set
-# CONFIG_SATA_DWC_DEBUG is not set
-CONFIG_SATA_MV=m
-CONFIG_SATA_NV=m
-CONFIG_SATA_PROMISE=m
-CONFIG_SATA_SIL=m
-CONFIG_SATA_SIS=m
-CONFIG_SATA_SVW=m
-CONFIG_SATA_ULI=m
-CONFIG_SATA_VIA=m
-CONFIG_SATA_VITESSE=m
-
-#
-# PATA SFF controllers with BMDMA
-#
-CONFIG_PATA_ALI=m
-CONFIG_PATA_AMD=m
-CONFIG_PATA_ARTOP=m
-CONFIG_PATA_ATIIXP=m
-CONFIG_PATA_ATP867X=m
-CONFIG_PATA_CMD64X=m
-CONFIG_PATA_CS5520=m
-CONFIG_PATA_CS5530=m
-CONFIG_PATA_CS5535=m
-CONFIG_PATA_CS5536=m
-CONFIG_PATA_CYPRESS=m
-CONFIG_PATA_EFAR=m
-CONFIG_PATA_HPT366=m
-CONFIG_PATA_HPT37X=m
-CONFIG_PATA_HPT3X2N=m
-CONFIG_PATA_HPT3X3=m
-CONFIG_PATA_HPT3X3_DMA=y
-CONFIG_PATA_IT8213=m
-CONFIG_PATA_IT821X=m
-CONFIG_PATA_JMICRON=m
-CONFIG_PATA_MARVELL=m
-CONFIG_PATA_NETCELL=m
-CONFIG_PATA_NINJA32=m
-CONFIG_PATA_NS87415=m
-CONFIG_PATA_OLDPIIX=m
-CONFIG_PATA_OPTIDMA=m
-CONFIG_PATA_PDC2027X=m
-CONFIG_PATA_PDC_OLD=m
-CONFIG_PATA_RADISYS=m
-CONFIG_PATA_RDC=m
-CONFIG_PATA_SC1200=m
-CONFIG_PATA_SCH=m
-CONFIG_PATA_SERVERWORKS=m
-CONFIG_PATA_SIL680=m
-CONFIG_PATA_SIS=m
-CONFIG_PATA_TOSHIBA=m
-CONFIG_PATA_TRIFLEX=m
-CONFIG_PATA_VIA=m
-CONFIG_PATA_WINBOND=m
-
-#
-# PIO-only SFF controllers
-#
-CONFIG_PATA_CMD640_PCI=m
-# CONFIG_PATA_ISAPNP is not set
-CONFIG_PATA_MPIIX=m
-CONFIG_PATA_NS87410=m
-CONFIG_PATA_OPTI=m
-CONFIG_PATA_PCMCIA=m
-# CONFIG_PATA_PLATFORM is not set
-CONFIG_PATA_OF_PLATFORM=m
-CONFIG_PATA_QDI=m
-CONFIG_PATA_RZ1000=m
-CONFIG_PATA_WINBOND_VLB=m
-
-#
-# Generic fallback / legacy drivers
-#
-CONFIG_PATA_ACPI=m
-CONFIG_ATA_GENERIC=m
-CONFIG_PATA_LEGACY=m
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID456=m
-CONFIG_MD_MULTIPATH=m
-CONFIG_MD_FAULTY=m
-CONFIG_MD_CLUSTER=m
-CONFIG_BCACHE=m
-# CONFIG_BCACHE_DEBUG is not set
-# CONFIG_BCACHE_CLOSURES_DEBUG is not set
-CONFIG_BCACHE_ASYNC_REGISTRATION=y
-CONFIG_BLK_DEV_DM_BUILTIN=y
-CONFIG_BLK_DEV_DM=m
-# CONFIG_DM_DEBUG is not set
-CONFIG_DM_BUFIO=m
-# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
-CONFIG_DM_BIO_PRISON=m
-CONFIG_DM_PERSISTENT_DATA=m
-CONFIG_DM_UNSTRIPED=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_THIN_PROVISIONING=m
-CONFIG_DM_CACHE=m
-CONFIG_DM_CACHE_SMQ=m
-CONFIG_DM_WRITECACHE=m
-# CONFIG_DM_EBS is not set
-CONFIG_DM_ERA=m
-CONFIG_DM_CLONE=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_LOG_USERSPACE=m
-CONFIG_DM_RAID=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_QL=m
-CONFIG_DM_MULTIPATH_ST=m
-CONFIG_DM_MULTIPATH_HST=m
-CONFIG_DM_MULTIPATH_IOA=m
-CONFIG_DM_DELAY=m
-CONFIG_DM_DUST=m
-CONFIG_DM_UEVENT=y
-CONFIG_DM_FLAKEY=m
-CONFIG_DM_VERITY=m
-CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
-# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING is not set
-# CONFIG_DM_VERITY_FEC is not set
-CONFIG_DM_SWITCH=m
-CONFIG_DM_LOG_WRITES=m
-CONFIG_DM_INTEGRITY=m
-CONFIG_DM_ZONED=m
-CONFIG_TARGET_CORE=m
-CONFIG_TCM_IBLOCK=m
-CONFIG_TCM_FILEIO=m
-CONFIG_TCM_PSCSI=m
-CONFIG_TCM_USER2=m
-CONFIG_LOOPBACK_TARGET=m
-CONFIG_TCM_FC=m
-CONFIG_ISCSI_TARGET=m
-CONFIG_ISCSI_TARGET_CXGB4=m
-CONFIG_SBP_TARGET=m
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=m
-CONFIG_FUSION_FC=m
-CONFIG_FUSION_SAS=m
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_CTL=m
-CONFIG_FUSION_LAN=m
-CONFIG_FUSION_LOGGING=y
-
-#
-# IEEE 1394 (FireWire) support
-#
-CONFIG_FIREWIRE=m
-CONFIG_FIREWIRE_OHCI=m
-CONFIG_FIREWIRE_SBP2=m
-CONFIG_FIREWIRE_NET=m
-CONFIG_FIREWIRE_NOSY=m
-# end of IEEE 1394 (FireWire) support
-
-CONFIG_MACINTOSH_DRIVERS=y
-CONFIG_MAC_EMUMOUSEBTN=m
-CONFIG_NETDEVICES=y
-CONFIG_MII=m
-CONFIG_NET_CORE=y
-CONFIG_BONDING=m
-CONFIG_DUMMY=m
-CONFIG_WIREGUARD=m
-# CONFIG_WIREGUARD_DEBUG is not set
-CONFIG_EQUALIZER=m
-CONFIG_NET_FC=y
-CONFIG_IFB=m
-CONFIG_NET_TEAM=m
-CONFIG_NET_TEAM_MODE_BROADCAST=m
-CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
-CONFIG_NET_TEAM_MODE_RANDOM=m
-CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
-CONFIG_NET_TEAM_MODE_LOADBALANCE=m
-CONFIG_MACVLAN=m
-CONFIG_MACVTAP=m
-CONFIG_IPVLAN_L3S=y
-CONFIG_IPVLAN=m
-CONFIG_IPVTAP=m
-CONFIG_VXLAN=m
-CONFIG_GENEVE=m
-CONFIG_BAREUDP=m
-CONFIG_GTP=m
-CONFIG_MACSEC=m
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_NETPOLL=y
-CONFIG_NET_POLL_CONTROLLER=y
-CONFIG_NTB_NETDEV=m
-CONFIG_RIONET=m
-CONFIG_RIONET_TX_SIZE=128
-CONFIG_RIONET_RX_SIZE=128
-CONFIG_TUN=m
-CONFIG_TAP=m
-# CONFIG_TUN_VNET_CROSS_LE is not set
-CONFIG_VETH=m
-CONFIG_VIRTIO_NET=m
-CONFIG_NLMON=m
-CONFIG_NET_VRF=m
-CONFIG_VSOCKMON=m
-CONFIG_MHI_NET=m
-CONFIG_SUNGEM_PHY=m
-CONFIG_ARCNET=m
-CONFIG_ARCNET_1201=m
-CONFIG_ARCNET_1051=m
-CONFIG_ARCNET_RAW=m
-CONFIG_ARCNET_CAP=m
-CONFIG_ARCNET_COM90xx=m
-CONFIG_ARCNET_COM90xxIO=m
-CONFIG_ARCNET_RIM_I=m
-CONFIG_ARCNET_COM20020=m
-CONFIG_ARCNET_COM20020_ISA=m
-CONFIG_ARCNET_COM20020_PCI=m
-CONFIG_ARCNET_COM20020_CS=m
-CONFIG_ATM_DRIVERS=y
-# CONFIG_ATM_DUMMY is not set
-CONFIG_ATM_TCP=m
-CONFIG_ATM_LANAI=m
-CONFIG_ATM_ENI=m
-# CONFIG_ATM_ENI_DEBUG is not set
-# CONFIG_ATM_ENI_TUNE_BURST is not set
-CONFIG_ATM_FIRESTREAM=m
-CONFIG_ATM_ZATM=m
-# CONFIG_ATM_ZATM_DEBUG is not set
-CONFIG_ATM_NICSTAR=m
-CONFIG_ATM_NICSTAR_USE_SUNI=y
-CONFIG_ATM_NICSTAR_USE_IDT77105=y
-CONFIG_ATM_IDT77252=m
-# CONFIG_ATM_IDT77252_DEBUG is not set
-# CONFIG_ATM_IDT77252_RCV_ALL is not set
-CONFIG_ATM_IDT77252_USE_SUNI=y
-CONFIG_ATM_AMBASSADOR=m
-# CONFIG_ATM_AMBASSADOR_DEBUG is not set
-CONFIG_ATM_HORIZON=m
-# CONFIG_ATM_HORIZON_DEBUG is not set
-CONFIG_ATM_IA=m
-# CONFIG_ATM_IA_DEBUG is not set
-CONFIG_ATM_FORE200E=m
-CONFIG_ATM_FORE200E_USE_TASKLET=y
-CONFIG_ATM_FORE200E_TX_RETRY=16
-CONFIG_ATM_FORE200E_DEBUG=0
-CONFIG_ATM_HE=m
-CONFIG_ATM_HE_USE_SUNI=y
-CONFIG_ATM_SOLOS=m
-# CONFIG_CAIF_DRIVERS is not set
-
-#
-# Distributed Switch Architecture drivers
-#
-CONFIG_B53=m
-CONFIG_B53_SPI_DRIVER=m
-CONFIG_B53_MDIO_DRIVER=m
-CONFIG_B53_MMAP_DRIVER=m
-CONFIG_B53_SRAB_DRIVER=m
-CONFIG_B53_SERDES=m
-CONFIG_NET_DSA_BCM_SF2=m
-CONFIG_NET_DSA_LOOP=m
-CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
-CONFIG_NET_DSA_LANTIQ_GSWIP=m
-CONFIG_NET_DSA_MT7530=m
-CONFIG_NET_DSA_MV88E6060=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-CONFIG_NET_DSA_MV88E6XXX=m
-CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
-CONFIG_NET_DSA_MV88E6XXX_PTP=y
-CONFIG_NET_DSA_MSCC_SEVILLE=m
-CONFIG_NET_DSA_AR9331=m
-CONFIG_NET_DSA_SJA1105=m
-CONFIG_NET_DSA_SJA1105_PTP=y
-CONFIG_NET_DSA_SJA1105_TAS=y
-# CONFIG_NET_DSA_SJA1105_VL is not set
-CONFIG_NET_DSA_XRS700X_I2C=m
-CONFIG_NET_DSA_XRS700X_MDIO=m
-CONFIG_NET_DSA_QCA8K=m
-CONFIG_NET_DSA_REALTEK_SMI=m
-CONFIG_NET_DSA_SMSC_LAN9303=m
-CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
-CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
-CONFIG_NET_DSA_VITESSE_VSC73XX=m
-CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
-CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
-# end of Distributed Switch Architecture drivers
-
-CONFIG_ETHERNET=y
-CONFIG_MDIO=m
-CONFIG_NET_VENDOR_3COM=y
-CONFIG_NET_VENDOR_ACTIONS=y
-CONFIG_OWL_EMAC=m
-CONFIG_EL3=m
-CONFIG_3C515=m
-CONFIG_PCMCIA_3C574=m
-CONFIG_PCMCIA_3C589=m
-CONFIG_VORTEX=m
-CONFIG_TYPHOON=m
-CONFIG_NET_VENDOR_ADAPTEC=y
-CONFIG_ADAPTEC_STARFIRE=m
-CONFIG_NET_VENDOR_AGERE=y
-CONFIG_ET131X=m
-CONFIG_NET_VENDOR_ALACRITECH=y
-CONFIG_SLICOSS=m
-CONFIG_NET_VENDOR_ALTEON=y
-CONFIG_ACENIC=m
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
-CONFIG_ALTERA_TSE=m
-CONFIG_NET_VENDOR_AMAZON=y
-CONFIG_ENA_ETHERNET=m
-CONFIG_NET_VENDOR_AMD=y
-CONFIG_AMD8111_ETH=m
-CONFIG_LANCE=m
-CONFIG_PCNET32=m
-CONFIG_PCMCIA_NMCLAN=m
-CONFIG_NI65=m
-CONFIG_AMD_XGBE=m
-CONFIG_AMD_XGBE_DCB=y
-CONFIG_AMD_XGBE_HAVE_ECC=y
-CONFIG_NET_VENDOR_AQUANTIA=y
-CONFIG_AQTION=m
-CONFIG_NET_VENDOR_ARC=y
-CONFIG_NET_VENDOR_ATHEROS=y
-CONFIG_ATL2=m
-CONFIG_ATL1=m
-CONFIG_ATL1E=m
-CONFIG_ATL1C=m
-CONFIG_ALX=m
-CONFIG_NET_VENDOR_AURORA=y
-CONFIG_AURORA_NB8800=m
-CONFIG_NET_VENDOR_BROADCOM=y
-CONFIG_B44=m
-CONFIG_BCM4908_ENET=m
-CONFIG_B44_PCI_AUTOSELECT=y
-CONFIG_B44_PCICORE_AUTOSELECT=y
-CONFIG_B44_PCI=y
-CONFIG_BCMGENET=m
-CONFIG_BNX2=m
-CONFIG_CNIC=m
-CONFIG_TIGON3=m
-CONFIG_TIGON3_HWMON=y
-CONFIG_BNX2X=m
-CONFIG_BNX2X_SRIOV=y
-CONFIG_SYSTEMPORT=m
-CONFIG_BNXT=m
-CONFIG_BNXT_SRIOV=y
-CONFIG_BNXT_FLOWER_OFFLOAD=y
-CONFIG_BNXT_DCB=y
-CONFIG_BNXT_HWMON=y
-CONFIG_NET_VENDOR_BROCADE=y
-CONFIG_BNA=m
-CONFIG_NET_VENDOR_CADENCE=y
-CONFIG_MACB=m
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MACB_PCI=m
-CONFIG_NET_VENDOR_CAVIUM=y
-CONFIG_NET_VENDOR_CHELSIO=y
-CONFIG_CHELSIO_T1=m
-CONFIG_CHELSIO_T1_1G=y
-CONFIG_CHELSIO_T3=m
-CONFIG_CHELSIO_T4=m
-CONFIG_CHELSIO_T4_DCB=y
-# CONFIG_CHELSIO_T4_FCOE is not set
-CONFIG_CHELSIO_T4VF=m
-CONFIG_CHELSIO_LIB=m
-CONFIG_CHELSIO_INLINE_CRYPTO=y
-CONFIG_CHELSIO_IPSEC_INLINE=m
-CONFIG_NET_VENDOR_CIRRUS=y
-# CONFIG_CS89x0 is not set
-CONFIG_CS89x0_ISA=m
-CONFIG_NET_VENDOR_CISCO=y
-CONFIG_ENIC=m
-# CONFIG_NET_VENDOR_CORTINA is not set
-CONFIG_NET_VENDOR_DAVICOM=y
-CONFIG_DM9051=m
-CONFIG_CX_ECAT=m
-CONFIG_DNET=m
-CONFIG_NET_VENDOR_DEC=y
-CONFIG_NET_TULIP=y
-CONFIG_DE2104X=m
-CONFIG_DE2104X_DSL=0
-CONFIG_TULIP=m
-CONFIG_TULIP_MWI=y
-CONFIG_TULIP_MMIO=y
-CONFIG_TULIP_NAPI=y
-CONFIG_TULIP_NAPI_HW_MITIGATION=y
-CONFIG_DE4X5=m
-CONFIG_WINBOND_840=m
-CONFIG_DM9102=m
-CONFIG_ULI526X=m
-CONFIG_PCMCIA_XIRCOM=m
-CONFIG_NET_VENDOR_DLINK=y
-CONFIG_DL2K=m
-CONFIG_SUNDANCE=m
-# CONFIG_SUNDANCE_MMIO is not set
-CONFIG_NET_VENDOR_EMULEX=y
-CONFIG_BE2NET=m
-CONFIG_BE2NET_HWMON=y
-CONFIG_BE2NET_BE2=y
-CONFIG_BE2NET_BE3=y
-CONFIG_BE2NET_LANCER=y
-CONFIG_BE2NET_SKYHAWK=y
-CONFIG_NET_VENDOR_EZCHIP=y
-CONFIG_NET_VENDOR_FUJITSU=y
-CONFIG_NET_VENDOR_FUNGIBLE=y
-CONFIG_FUN_ETH=m
-CONFIG_PCMCIA_FMVJ18X=m
-CONFIG_NET_VENDOR_GOOGLE=y
-CONFIG_GVE=m
-CONFIG_NET_VENDOR_HUAWEI=y
-CONFIG_HINIC=m
-CONFIG_NET_VENDOR_I825XX=y
-CONFIG_NET_VENDOR_INTEL=y
-CONFIG_E100=m
-CONFIG_E1000=m
-CONFIG_E1000E=m
-CONFIG_E1000E_HWTS=y
-CONFIG_IGB=m
-CONFIG_IGB_HWMON=y
-CONFIG_IGBVF=m
-CONFIG_IXGB=m
-CONFIG_IXGBE=m
-CONFIG_IXGBE_HWMON=y
-CONFIG_IXGBE_DCB=y
-CONFIG_IXGBE_IPSEC=y
-CONFIG_IXGBEVF=m
-CONFIG_IXGBEVF_IPSEC=y
-CONFIG_I40E=m
-CONFIG_I40E_DCB=y
-CONFIG_IAVF=m
-CONFIG_I40EVF=m
-CONFIG_ICE=m
-CONFIG_FM10K=m
-CONFIG_IGC=m
-CONFIG_NET_VENDOR_MICROSOFT=y
-CONFIG_MICROSOFT_MANA=m
-CONFIG_JME=m
-CONFIG_NET_VENDOR_MARVELL=y
-CONFIG_MVMDIO=m
-CONFIG_SKGE=m
-# CONFIG_SKGE_DEBUG is not set
-CONFIG_SKGE_GENESIS=y
-CONFIG_SKY2=m
-# CONFIG_SKY2_DEBUG is not set
-CONFIG_PRESTERA=m
-CONFIG_PRESTERA_PCI=m
-CONFIG_NET_VENDOR_MELLANOX=y
-CONFIG_MLX4_EN=m
-CONFIG_MLX4_EN_DCB=y
-CONFIG_MLX4_CORE=m
-# CONFIG_MLX4_DEBUG is not set
-CONFIG_MLX4_CORE_GEN2=y
-CONFIG_MLX5_CORE=m
-CONFIG_MLX5_ACCEL=y
-CONFIG_MLX5_FPGA=y
-# CONFIG_MLX5_CORE_EN is not set
-CONFIG_MLX5_FPGA_IPSEC=y
-CONFIG_MLXSW_CORE=m
-CONFIG_MLXSW_CORE_HWMON=y
-CONFIG_MLXSW_CORE_THERMAL=y
-CONFIG_MLXSW_PCI=m
-CONFIG_MLXSW_I2C=m
-CONFIG_MLXSW_SWITCHIB=m
-CONFIG_MLXSW_SWITCHX2=m
-CONFIG_MLXSW_SPECTRUM=m
-CONFIG_MLXSW_SPECTRUM_DCB=y
-CONFIG_MLXSW_MINIMAL=m
-CONFIG_MLXFW=m
-CONFIG_MLXFW_GIGE=m
-CONFIG_MLXBF_GIGE=m
-CONFIG_NET_VENDOR_MICREL=y
-CONFIG_KS8842=m
-CONFIG_KS8851=m
-CONFIG_KS8851_MLL=m
-CONFIG_KSZ884X_PCI=m
-CONFIG_NET_VENDOR_MICROCHIP=y
-CONFIG_ENC28J60=m
-# CONFIG_ENC28J60_WRITEVERIFY is not set
-CONFIG_ENCX24J600=m
-CONFIG_LAN743X=m
-CONFIG_SPARX5_SWITCH=m
-CONFIG_NET_VENDOR_MICROSEMI=y
-CONFIG_MSCC_OCELOT_SWITCH_LIB=m
-CONFIG_NET_VENDOR_MYRI=y
-CONFIG_MYRI10GE=m
-CONFIG_FEALNX=m
-CONFIG_NET_VENDOR_NATSEMI=y
-CONFIG_NATSEMI=m
-CONFIG_NS83820=m
-CONFIG_NET_VENDOR_NETERION=y
-CONFIG_S2IO=m
-CONFIG_VXGE=m
-# CONFIG_VXGE_DEBUG_TRACE_ALL is not set
-CONFIG_NET_VENDOR_NETRONOME=y
-CONFIG_NFP=m
-# CONFIG_NFP_APP_FLOWER is not set
-CONFIG_NFP_APP_ABM_NIC=y
-# CONFIG_NFP_DEBUG is not set
-CONFIG_NET_VENDOR_NI=y
-CONFIG_NI_XGE_MANAGEMENT_ENET=m
-CONFIG_NET_VENDOR_8390=y
-CONFIG_PCMCIA_AXNET=m
-# CONFIG_NE2000 is not set
-CONFIG_NE2K_PCI=m
-CONFIG_PCMCIA_PCNET=m
-# CONFIG_ULTRA is not set
-# CONFIG_WD80x3 is not set
-CONFIG_NET_VENDOR_NVIDIA=y
-CONFIG_FORCEDETH=m
-CONFIG_NET_VENDOR_OKI=y
-# CONFIG_PCH_GBE is not set
-CONFIG_ETHOC=m
-CONFIG_NET_VENDOR_PACKET_ENGINES=y
-CONFIG_HAMACHI=m
-CONFIG_YELLOWFIN=m
-CONFIG_NET_VENDOR_PENSANDO=y
-CONFIG_NET_VENDOR_QLOGIC=y
-CONFIG_QLA3XXX=m
-CONFIG_QLCNIC=m
-CONFIG_QLCNIC_SRIOV=y
-CONFIG_QLCNIC_DCB=y
-CONFIG_QLCNIC_HWMON=y
-CONFIG_NETXEN_NIC=m
-CONFIG_QED=m
-CONFIG_QED_LL2=y
-CONFIG_QED_SRIOV=y
-CONFIG_QEDE=m
-CONFIG_QED_ISCSI=y
-CONFIG_QED_FCOE=y
-CONFIG_QED_OOO=y
-CONFIG_NET_VENDOR_QUALCOMM=y
-CONFIG_QCOM_EMAC=m
-CONFIG_RMNET=m
-CONFIG_NET_VENDOR_RDC=y
-CONFIG_R6040=m
-CONFIG_NET_VENDOR_REALTEK=y
-CONFIG_ATP=m
-CONFIG_8139CP=m
-CONFIG_8139TOO=m
-# CONFIG_8139TOO_PIO is not set
-CONFIG_8139TOO_TUNE_TWISTER=y
-CONFIG_8139TOO_8129=y
-# CONFIG_8139_OLD_RX_RESET is not set
-CONFIG_R8169=m
-CONFIG_NET_VENDOR_RENESAS=y
-CONFIG_NET_VENDOR_ROCKER=y
-CONFIG_ROCKER=m
-CONFIG_NET_VENDOR_SAMSUNG=y
-CONFIG_SXGBE_ETH=m
-CONFIG_NET_VENDOR_SEEQ=y
-CONFIG_NET_VENDOR_SOLARFLARE=y
-CONFIG_SFC=m
-CONFIG_SFC_MTD=y
-CONFIG_SFC_MCDI_MON=y
-CONFIG_SFC_SRIOV=y
-CONFIG_SFC_MCDI_LOGGING=y
-CONFIG_SFC_FALCON=m
-CONFIG_SFC_FALCON_MTD=y
-CONFIG_NET_VENDOR_SILAN=y
-CONFIG_SC92031=m
-CONFIG_NET_VENDOR_SIS=y
-CONFIG_SIS900=m
-CONFIG_SIS190=m
-CONFIG_NET_VENDOR_SMSC=y
-# CONFIG_SMC9194 is not set
-CONFIG_PCMCIA_SMC91C92=m
-CONFIG_EPIC100=m
-CONFIG_SMSC911X=m
-CONFIG_SMSC9420=m
-# CONFIG_NET_VENDOR_SOCIONEXT is not set
-CONFIG_NET_VENDOR_STMICRO=y
-CONFIG_STMMAC_ETH=m
-# CONFIG_STMMAC_SELFTESTS is not set
-CONFIG_STMMAC_PLATFORM=m
-CONFIG_DWMAC_LOONGSON=m
-CONFIG_DWMAC_GENERIC=m
-CONFIG_DWMAC_INTEL=m
-CONFIG_STMMAC_PCI=m
-CONFIG_NET_VENDOR_SUN=y
-CONFIG_HAPPYMEAL=m
-CONFIG_SUNGEM=m
-CONFIG_CASSINI=m
-CONFIG_NIU=m
-CONFIG_NET_VENDOR_SYNOPSYS=y
-CONFIG_DWC_XLGMAC=m
-CONFIG_DWC_XLGMAC_PCI=m
-CONFIG_NET_VENDOR_TEHUTI=y
-CONFIG_TEHUTI=m
-CONFIG_NET_VENDOR_TI=y
-# CONFIG_TI_CPSW_PHY_SEL is not set
-CONFIG_TLAN=m
-CONFIG_NET_VENDOR_VIA=y
-CONFIG_VIA_RHINE=m
-CONFIG_VIA_RHINE_MMIO=y
-CONFIG_VIA_VELOCITY=m
-CONFIG_NET_VENDOR_WIZNET=y
-CONFIG_WIZNET_W5100=m
-CONFIG_WIZNET_W5300=m
-# CONFIG_WIZNET_BUS_DIRECT is not set
-# CONFIG_WIZNET_BUS_INDIRECT is not set
-CONFIG_WIZNET_BUS_ANY=y
-CONFIG_WIZNET_W5100_SPI=m
-CONFIG_NET_VENDOR_XILINX=y
-CONFIG_XILINX_EMACLITE=m
-CONFIG_XILINX_AXI_EMAC=m
-CONFIG_XILINX_LL_TEMAC=m
-CONFIG_NET_VENDOR_XIRCOM=y
-CONFIG_PCMCIA_XIRC2PS=m
-CONFIG_FDDI=m
-CONFIG_DEFXX=m
-# CONFIG_DEFXX_MMIO is not set
-CONFIG_SKFP=m
-CONFIG_HIPPI=y
-CONFIG_ROADRUNNER=m
-CONFIG_ROADRUNNER_LARGE_RINGS=y
-CONFIG_NET_SB1000=m
-CONFIG_PHYLINK=m
-CONFIG_PHYLIB=m
-CONFIG_SWPHY=y
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_FIXED_PHY=m
-CONFIG_SFP=m
-
-#
-# MII PHY device drivers
-#
-CONFIG_AMD_PHY=m
-CONFIG_ADIN_PHY=m
-CONFIG_AQUANTIA_PHY=m
-CONFIG_AX88796B_PHY=m
-CONFIG_BROADCOM_PHY=m
-CONFIG_BCM54140_PHY=m
-CONFIG_BCM7XXX_PHY=m
-CONFIG_BCM84881_PHY=m
-CONFIG_BCM87XX_PHY=m
-CONFIG_BCM_NET_PHYLIB=m
-CONFIG_CICADA_PHY=m
-CONFIG_CORTINA_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_ICPLUS_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_INTEL_XWAY_PHY=m
-CONFIG_LSI_ET1011C_PHY=m
-CONFIG_MARVELL_PHY=m
-CONFIG_MARVELL_10G_PHY=m
-CONFIG_MARVELL_88X2222_PHY=m
-CONFIG_MEDIATEK_GE_PHY=m
-CONFIG_MICREL_PHY=m
-CONFIG_MICROCHIP_PHY=m
-CONFIG_MICROCHIP_T1_PHY=m
-CONFIG_MICROSEMI_PHY=m
-CONFIG_MOTORCOMM_PHY=m
-CONFIG_NATIONAL_PHY=m
-CONFIG_NXP_C45_TJA11XX_PHY=m
-CONFIG_NXP_TJA11XX_PHY=m
-CONFIG_AT803X_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_REALTEK_PHY=m
-CONFIG_RENESAS_PHY=m
-CONFIG_ROCKCHIP_PHY=m
-CONFIG_SMSC_PHY=m
-CONFIG_STE10XP=m
-CONFIG_TERANETICS_PHY=m
-CONFIG_DP83822_PHY=m
-CONFIG_DP83TC811_PHY=m
-CONFIG_DP83848_PHY=m
-CONFIG_DP83867_PHY=m
-CONFIG_DP83869_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_XILINX_GMII2RGMII=m
-CONFIG_WWAN=y
-CONFIG_WWAN_HWSIM=m
-CONFIG_WWAN_CORE=m
-CONFIG_RPMSG_WWAN_CTRL=m
-# CONFIG_TEST_MAPLE_TREE is not set
-CONFIG_IOSM=m
-CONFIG_MHI_WWAN_CTRL=m
-CONFIG_MICREL_KS8995MA=m
-CONFIG_MDIO_DEVICE=m
-CONFIG_MDIO_BUS=m
-CONFIG_MDIO_DEVRES=m
-CONFIG_MDIO_BITBANG=m
-CONFIG_MDIO_BCM_UNIMAC=m
-CONFIG_MDIO_GPIO=m
-CONFIG_MDIO_I2C=m
-CONFIG_MDIO_MVUSB=m
-CONFIG_MDIO_MSCC_MIIM=m
-
-#
-# MDIO Multiplexers
-#
-
-#
-# PCS device drivers
-#
-CONFIG_PCS_XPCS=m
-CONFIG_PCS_LYNX=m
-# end of PCS device drivers
-
-CONFIG_PLIP=m
-CONFIG_PPP=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_MPPE=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPPOATM=m
-CONFIG_PPPOE=m
-CONFIG_PPTP=m
-CONFIG_PPPOL2TP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_SLIP=m
-CONFIG_SLHC=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-
-#
-# Host-side USB support is needed for USB Network Adapter support
-#
-CONFIG_USB_NET_DRIVERS=m
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_RTL8152=m
-CONFIG_USB_LAN78XX=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_AX8817X=m
-CONFIG_USB_NET_AX88179_178A=m
-CONFIG_USB_NET_CDCETHER=m
-CONFIG_USB_NET_CDC_EEM=m
-CONFIG_USB_NET_CDC_NCM=m
-CONFIG_USB_NET_HUAWEI_CDC_NCM=m
-CONFIG_USB_NET_CDC_MBIM=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_SR9700=m
-CONFIG_USB_NET_SR9800=m
-CONFIG_USB_NET_SMSC75XX=m
-CONFIG_USB_NET_SMSC95XX=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_NET1080=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_MCS7830=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
-CONFIG_USB_NET_CDC_SUBSET=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_BELKIN=y
-CONFIG_USB_ARMLINUX=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-CONFIG_USB_NET_ZAURUS=m
-CONFIG_USB_NET_CX82310_ETH=m
-CONFIG_USB_NET_KALMIA=m
-CONFIG_USB_NET_QMI_WWAN=m
-CONFIG_USB_HSO=m
-CONFIG_USB_NET_INT51X1=m
-CONFIG_USB_CDC_PHONET=m
-CONFIG_USB_IPHETH=m
-CONFIG_USB_SIERRA_NET=m
-CONFIG_USB_VL600=m
-CONFIG_USB_NET_CH9200=m
-CONFIG_USB_NET_AQC111=m
-CONFIG_USB_RTL8153_ECM=m
-CONFIG_WLAN=y
-# CONFIG_WIRELESS_WDS is not set
-CONFIG_WLAN_VENDOR_ADMTEK=y
-CONFIG_ADM8211=m
-CONFIG_ATH_COMMON=m
-CONFIG_WLAN_VENDOR_ATH=y
-# CONFIG_ATH_DEBUG is not set
-CONFIG_ATH5K=m
-# CONFIG_ATH5K_DEBUG is not set
-# CONFIG_ATH5K_TRACER is not set
-CONFIG_ATH5K_PCI=y
-CONFIG_ATH9K_HW=m
-CONFIG_ATH9K_COMMON=m
-CONFIG_ATH9K_BTCOEX_SUPPORT=y
-CONFIG_ATH9K=m
-CONFIG_ATH9K_PCI=y
-CONFIG_ATH9K_AHB=y
-# CONFIG_ATH9K_DEBUGFS is not set
-CONFIG_ATH9K_DYNACK=y
-CONFIG_ATH9K_WOW=y
-CONFIG_ATH9K_RFKILL=y
-CONFIG_ATH9K_CHANNEL_CONTEXT=y
-CONFIG_ATH9K_PCOEM=y
-CONFIG_ATH9K_PCI_NO_EEPROM=m
-CONFIG_ATH9K_HTC=m
-# CONFIG_ATH9K_HTC_DEBUGFS is not set
-CONFIG_ATH9K_HWRNG=y
-CONFIG_CARL9170=m
-CONFIG_CARL9170_LEDS=y
-CONFIG_CARL9170_WPC=y
-# CONFIG_CARL9170_HWRNG is not set
-CONFIG_ATH6KL=m
-CONFIG_ATH6KL_SDIO=m
-CONFIG_ATH6KL_USB=m
-# CONFIG_ATH6KL_DEBUG is not set
-# CONFIG_ATH6KL_TRACING is not set
-CONFIG_AR5523=m
-CONFIG_WIL6210=m
-CONFIG_WIL6210_ISR_COR=y
-CONFIG_WIL6210_TRACING=y
-CONFIG_WIL6210_DEBUGFS=y
-CONFIG_ATH10K=m
-CONFIG_ATH10K_CE=y
-CONFIG_ATH10K_PCI=m
-CONFIG_ATH10K_SDIO=m
-CONFIG_ATH10K_USB=m
-# CONFIG_ATH10K_DEBUG is not set
-# CONFIG_ATH10K_DEBUGFS is not set
-# CONFIG_ATH10K_TRACING is not set
-CONFIG_WCN36XX=m
-# CONFIG_WCN36XX_DEBUGFS is not set
-CONFIG_ATH11K=m
-CONFIG_ATH11K_PCI=m
-# CONFIG_ATH11K_DEBUG is not set
-# CONFIG_ATH11K_TRACING is not set
-CONFIG_WLAN_VENDOR_ATMEL=y
-CONFIG_ATMEL=m
-CONFIG_PCI_ATMEL=m
-CONFIG_PCMCIA_ATMEL=m
-CONFIG_AT76C50X_USB=m
-CONFIG_WLAN_VENDOR_BROADCOM=y
-CONFIG_B43=m
-CONFIG_B43_BCMA=y
-CONFIG_B43_SSB=y
-CONFIG_B43_BUSES_BCMA_AND_SSB=y
-# CONFIG_B43_BUSES_BCMA is not set
-# CONFIG_B43_BUSES_SSB is not set
-CONFIG_B43_PCI_AUTOSELECT=y
-CONFIG_B43_PCICORE_AUTOSELECT=y
-CONFIG_B43_SDIO=y
-CONFIG_B43_BCMA_PIO=y
-CONFIG_B43_PIO=y
-CONFIG_B43_PHY_G=y
-CONFIG_B43_PHY_N=y
-CONFIG_B43_PHY_LP=y
-CONFIG_B43_PHY_HT=y
-CONFIG_B43_LEDS=y
-CONFIG_B43_HWRNG=y
-# CONFIG_B43_DEBUG is not set
-CONFIG_B43LEGACY=m
-CONFIG_B43LEGACY_PCI_AUTOSELECT=y
-CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
-CONFIG_B43LEGACY_LEDS=y
-CONFIG_B43LEGACY_HWRNG=y
-# CONFIG_B43LEGACY_DEBUG is not set
-CONFIG_B43LEGACY_DMA=y
-CONFIG_B43LEGACY_PIO=y
-CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
-# CONFIG_B43LEGACY_DMA_MODE is not set
-# CONFIG_B43LEGACY_PIO_MODE is not set
-CONFIG_BRCMUTIL=m
-CONFIG_BRCMSMAC=m
-CONFIG_BRCMFMAC=m
-CONFIG_BRCMFMAC_PROTO_BCDC=y
-CONFIG_BRCMFMAC_PROTO_MSGBUF=y
-CONFIG_BRCMFMAC_SDIO=y
-CONFIG_BRCMFMAC_USB=y
-CONFIG_BRCMFMAC_PCIE=y
-CONFIG_BRCM_TRACING=y
-# CONFIG_BRCMDBG is not set
-CONFIG_WLAN_VENDOR_CISCO=y
-CONFIG_AIRO=m
-CONFIG_AIRO_CS=m
-CONFIG_WLAN_VENDOR_INTEL=y
-CONFIG_IPW2100=m
-CONFIG_IPW2100_MONITOR=y
-# CONFIG_IPW2100_DEBUG is not set
-CONFIG_IPW2200=m
-CONFIG_IPW2200_MONITOR=y
-CONFIG_IPW2200_RADIOTAP=y
-CONFIG_IPW2200_PROMISCUOUS=y
-CONFIG_IPW2200_QOS=y
-# CONFIG_IPW2200_DEBUG is not set
-CONFIG_LIBIPW=m
-# CONFIG_LIBIPW_DEBUG is not set
-CONFIG_IWLEGACY=m
-CONFIG_IWL4965=m
-CONFIG_IWL3945=m
-
-#
-# iwl3945 / iwl4965 Debugging Options
-#
-# CONFIG_IWLEGACY_DEBUG is not set
-# end of iwl3945 / iwl4965 Debugging Options
-
-CONFIG_IWLWIFI=m
-CONFIG_IWLWIFI_LEDS=y
-CONFIG_IWLDVM=m
-CONFIG_IWLMVM=m
-CONFIG_IWLWIFI_OPMODE_MODULAR=y
-# CONFIG_IWLWIFI_BCAST_FILTERING is not set
-CONFIG_IWLMEI=m
-
-#
-# Debugging Options
-#
-# CONFIG_IWLWIFI_DEBUG is not set
-CONFIG_IWLWIFI_DEVICE_TRACING=y
-# end of Debugging Options
-
-CONFIG_WLAN_VENDOR_INTERSIL=y
-CONFIG_HOSTAP=m
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_HOSTAP_PLX=m
-CONFIG_HOSTAP_PCI=m
-CONFIG_HOSTAP_CS=m
-CONFIG_HERMES=m
-CONFIG_HERMES_PRISM=y
-CONFIG_HERMES_CACHE_FW_ON_INIT=y
-CONFIG_PLX_HERMES=m
-CONFIG_TMD_HERMES=m
-CONFIG_NORTEL_HERMES=m
-CONFIG_PCI_HERMES=m
-CONFIG_PCMCIA_HERMES=m
-CONFIG_PCMCIA_SPECTRUM=m
-CONFIG_ORINOCO_USB=m
-CONFIG_P54_COMMON=m
-CONFIG_P54_USB=m
-CONFIG_P54_PCI=m
-CONFIG_P54_SPI=m
-CONFIG_P54_SPI_DEFAULT_EEPROM=y
-CONFIG_P54_LEDS=y
-CONFIG_PRISM54=m
-CONFIG_WLAN_VENDOR_MARVELL=y
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_USB=m
-CONFIG_LIBERTAS_CS=m
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_LIBERTAS_SPI=m
-# CONFIG_LIBERTAS_DEBUG is not set
-CONFIG_LIBERTAS_MESH=y
-CONFIG_LIBERTAS_THINFIRM=m
-# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
-CONFIG_LIBERTAS_THINFIRM_USB=m
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
-CONFIG_MWIFIEX_PCIE=m
-CONFIG_MWIFIEX_USB=m
-CONFIG_MWL8K=m
-CONFIG_WLAN_VENDOR_MEDIATEK=y
-CONFIG_MT7601U=m
-CONFIG_MT76_CORE=m
-CONFIG_MT76_LEDS=y
-CONFIG_MT76_USB=m
-CONFIG_MT76_SDIO=m
-CONFIG_MT76x02_LIB=m
-CONFIG_MT76x02_USB=m
-CONFIG_MT76x0_COMMON=m
-CONFIG_MT76x0U=m
-CONFIG_MT76x0E=m
-CONFIG_MT76x2_COMMON=m
-CONFIG_MT76x2E=m
-CONFIG_MT76x2U=m
-CONFIG_MT7603E=m
-CONFIG_MT7615_COMMON=m
-CONFIG_MT7615E=m
-CONFIG_MT7663_USB_SDIO_COMMON=m
-CONFIG_MT7663U=m
-CONFIG_MT7663S=m
-CONFIG_MT7915E=m
-CONFIG_MT7986_WMAC=y
-CONFIG_MT7921E=m
-CONFIG_WLAN_VENDOR_MICROCHIP=y
-CONFIG_WILC1000=m
-CONFIG_WILC1000_SDIO=m
-CONFIG_WILC1000_SPI=m
-# CONFIG_WILC1000_HW_OOB_INTR is not set
-CONFIG_WLAN_VENDOR_RALINK=y
-CONFIG_RT2X00=m
-CONFIG_RT2400PCI=m
-CONFIG_RT2500PCI=m
-CONFIG_RT61PCI=m
-CONFIG_RT2800PCI=m
-CONFIG_RT2800PCI_RT33XX=y
-CONFIG_RT2800PCI_RT35XX=y
-CONFIG_RT2800PCI_RT53XX=y
-CONFIG_RT2800PCI_RT3290=y
-CONFIG_RT2500USB=m
-CONFIG_RT73USB=m
-CONFIG_RT2800USB=m
-CONFIG_RT2800USB_RT33XX=y
-CONFIG_RT2800USB_RT35XX=y
-CONFIG_RT2800USB_RT3573=y
-CONFIG_RT2800USB_RT53XX=y
-CONFIG_RT2800USB_RT55XX=y
-CONFIG_RT2800USB_UNKNOWN=y
-CONFIG_RT2800_LIB=m
-CONFIG_RT2800_LIB_MMIO=m
-CONFIG_RT2X00_LIB_MMIO=m
-CONFIG_RT2X00_LIB_PCI=m
-CONFIG_RT2X00_LIB_USB=m
-CONFIG_RT2X00_LIB=m
-CONFIG_RT2X00_LIB_FIRMWARE=y
-CONFIG_RT2X00_LIB_CRYPTO=y
-CONFIG_RT2X00_LIB_LEDS=y
-# CONFIG_RT2X00_DEBUG is not set
-CONFIG_WLAN_VENDOR_REALTEK=y
-CONFIG_RTL8180=m
-CONFIG_RTL8187=m
-CONFIG_RTL8187_LEDS=y
-CONFIG_RTL_CARDS=m
-CONFIG_RTL8192CE=m
-CONFIG_RTL8192SE=m
-CONFIG_RTL8192DE=m
-CONFIG_RTL8723AE=m
-CONFIG_RTL8723BE=m
-CONFIG_RTL8188EE=m
-CONFIG_RTL8192EE=m
-CONFIG_RTL8821AE=m
-CONFIG_RTL8192CU=m
-CONFIG_RTLWIFI=m
-CONFIG_RTLWIFI_PCI=m
-CONFIG_RTLWIFI_USB=m
-# CONFIG_RTLWIFI_DEBUG is not set
-CONFIG_RTL8192C_COMMON=m
-CONFIG_RTL8723_COMMON=m
-CONFIG_RTLBTCOEXIST=m
-CONFIG_RTL8XXXU=m
-CONFIG_RTL8XXXU_UNTESTED=y
-CONFIG_RTW88=m
-CONFIG_RTW88_CORE=m
-CONFIG_RTW88_PCI=m
-CONFIG_RTW88_8822B=m
-CONFIG_RTW88_8822C=m
-CONFIG_RTW88_8723D=m
-CONFIG_RTW88_8821C=m
-CONFIG_RTW88_8822BE=m
-CONFIG_RTW88_8822CE=m
-CONFIG_RTW88_8723DE=m
-CONFIG_RTW88_8821CE=m
-# CONFIG_RTW88_DEBUG is not set
-# CONFIG_RTW88_DEBUGFS is not set
-CONFIG_WLAN_VENDOR_RSI=y
-CONFIG_RSI_91X=m
-# CONFIG_RSI_DEBUGFS is not set
-CONFIG_RSI_SDIO=m
-CONFIG_RSI_USB=m
-CONFIG_RSI_COEX=y
-CONFIG_WLAN_VENDOR_ST=y
-CONFIG_CW1200=m
-CONFIG_CW1200_WLAN_SDIO=m
-CONFIG_CW1200_WLAN_SPI=m
-CONFIG_WLAN_VENDOR_TI=y
-CONFIG_WL1251=m
-CONFIG_WL1251_SPI=m
-CONFIG_WL1251_SDIO=m
-CONFIG_WL12XX=m
-CONFIG_WL18XX=m
-CONFIG_WLCORE=m
-CONFIG_WLCORE_SDIO=m
-CONFIG_WILINK_PLATFORM_DATA=y
-CONFIG_WLAN_VENDOR_ZYDAS=y
-CONFIG_USB_ZD1201=m
-CONFIG_ZD1211RW=m
-# CONFIG_ZD1211RW_DEBUG is not set
-CONFIG_WLAN_VENDOR_QUANTENNA=y
-CONFIG_QTNFMAC=m
-CONFIG_QTNFMAC_PCIE=m
-CONFIG_PCMCIA_RAYCS=m
-CONFIG_PCMCIA_WL3501=m
-# CONFIG_MAC80211_HWSIM is not set
-CONFIG_USB_NET_RNDIS_WLAN=m
-CONFIG_VIRT_WIFI=m
-
-#
-# WiMAX Wireless Broadband devices
-#
-CONFIG_WIMAX_I2400M=m
-CONFIG_WIMAX_I2400M_USB=m
-CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8
-# end of WiMAX Wireless Broadband devices
-
-CONFIG_WAN=y
-# CONFIG_HOSTESS_SV11 is not set
-# CONFIG_COSA is not set
-CONFIG_LANMEDIA=m
-# CONFIG_SEALEVEL_4021 is not set
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_PCI200SYN=m
-CONFIG_WANXL=m
-CONFIG_PC300TOO=m
-# CONFIG_N2 is not set
-# CONFIG_C101 is not set
-CONFIG_FARSYNC=m
-CONFIG_DLCI=m
-CONFIG_DLCI_MAX=8
-# CONFIG_SDLA is not set
-CONFIG_LAPBETHER=m
-CONFIG_X25_ASY=m
-CONFIG_SBNI=m
-CONFIG_SBNI_MULTILINE=y
-CONFIG_IEEE802154_DRIVERS=m
-CONFIG_IEEE802154_FAKELB=m
-CONFIG_IEEE802154_AT86RF230=m
-# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set
-CONFIG_IEEE802154_MRF24J40=m
-CONFIG_IEEE802154_CC2520=m
-CONFIG_IEEE802154_ATUSB=m
-CONFIG_IEEE802154_ADF7242=m
-CONFIG_IEEE802154_CA8210=m
-# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
-CONFIG_IEEE802154_MCR20A=m
-CONFIG_IEEE802154_HWSIM=m
-CONFIG_VMXNET3=m
-CONFIG_FUJITSU_ES=m
-CONFIG_USB4_NET=m
-CONFIG_HYPERV_NET=m
-CONFIG_NETDEVSIM=m
-CONFIG_NET_FAILOVER=m
-CONFIG_ISDN=y
-CONFIG_ISDN_CAPI=m
-CONFIG_CAPI_TRACE=y
-CONFIG_ISDN_CAPI_MIDDLEWARE=m
-CONFIG_MISDN=m
-CONFIG_MISDN_DSP=m
-CONFIG_MISDN_L1OIP=m
-
-#
-# mISDN hardware drivers
-#
-CONFIG_MISDN_HFCPCI=m
-CONFIG_MISDN_HFCMULTI=m
-CONFIG_MISDN_HFCUSB=m
-CONFIG_MISDN_AVMFRITZ=m
-CONFIG_MISDN_SPEEDFAX=m
-CONFIG_MISDN_INFINEON=m
-CONFIG_MISDN_W6692=m
-CONFIG_MISDN_NETJET=m
-CONFIG_MISDN_HDLC=m
-CONFIG_MISDN_IPAC=m
-CONFIG_MISDN_ISAR=m
-CONFIG_NVM=y
-CONFIG_NVM_PBLK=m
-# CONFIG_NVM_PBLK_DEBUG is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_LEDS=m
-CONFIG_INPUT_FF_MEMLESS=m
-CONFIG_INPUT_POLLDEV=m
-CONFIG_INPUT_SPARSEKMAP=m
-CONFIG_INPUT_MATRIXKMAP=m
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ADC=m
-CONFIG_KEYBOARD_ADP5588=m
-CONFIG_KEYBOARD_ADP5589=m
-CONFIG_KEYBOARD_APPLESPI=m
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_KEYBOARD_QT1050=m
-CONFIG_KEYBOARD_QT1070=m
-CONFIG_KEYBOARD_QT2160=m
-CONFIG_KEYBOARD_DLINK_DIR685=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_GPIO=m
-CONFIG_KEYBOARD_GPIO_POLLED=m
-CONFIG_KEYBOARD_TCA6416=m
-CONFIG_KEYBOARD_TCA8418=m
-CONFIG_KEYBOARD_MATRIX=m
-CONFIG_KEYBOARD_LM8323=m
-CONFIG_KEYBOARD_LM8333=m
-CONFIG_KEYBOARD_MAX7359=m
-CONFIG_KEYBOARD_MCS=m
-CONFIG_KEYBOARD_MPR121=m
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_OPENCORES=m
-CONFIG_KEYBOARD_PINEPHONE=m
-CONFIG_KEYBOARD_SAMSUNG=m
-CONFIG_KEYBOARD_STOWAWAY=m
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_IQS62X=m
-CONFIG_KEYBOARD_TM2_TOUCHKEY=m
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_KEYBOARD_CROS_EC=m
-CONFIG_KEYBOARD_MTK_PMIC=m
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_BYD=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
-CONFIG_MOUSE_PS2_CYPRESS=y
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-CONFIG_MOUSE_PS2_ELANTECH=y
-CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
-CONFIG_MOUSE_PS2_SENTELIC=y
-CONFIG_MOUSE_PS2_TOUCHKIT=y
-CONFIG_MOUSE_PS2_FOCALTECH=y
-# CONFIG_MOUSE_PS2_VMMOUSE is not set
-CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_APPLETOUCH=m
-CONFIG_MOUSE_BCM5974=m
-CONFIG_MOUSE_CYAPA=m
-CONFIG_MOUSE_ELAN_I2C=m
-CONFIG_MOUSE_ELAN_I2C_I2C=y
-CONFIG_MOUSE_ELAN_I2C_SMBUS=y
-# CONFIG_MOUSE_INPORT is not set
-# CONFIG_MOUSE_LOGIBM is not set
-# CONFIG_MOUSE_PC110PAD is not set
-CONFIG_MOUSE_VSXXXAA=m
-CONFIG_MOUSE_GPIO=m
-CONFIG_MOUSE_SYNAPTICS_I2C=m
-CONFIG_MOUSE_SYNAPTICS_USB=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADC=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=m
-CONFIG_JOYSTICK_IFORCE_232=m
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_TWIDJOY=m
-CONFIG_JOYSTICK_ZHENHUA=m
-CONFIG_JOYSTICK_DB9=m
-CONFIG_JOYSTICK_GAMECON=m
-CONFIG_JOYSTICK_TURBOGRAFX=m
-CONFIG_JOYSTICK_AS5011=m
-# CONFIG_JOYSTICK_JOYDUMP is not set
-CONFIG_JOYSTICK_XPAD=m
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_JOYSTICK_WALKERA0701=m
-CONFIG_JOYSTICK_PSXPAD_SPI=m
-CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
-CONFIG_JOYSTICK_PXRC=m
-CONFIG_JOYSTICK_QWIIC=m
-CONFIG_JOYSTICK_FSIA6B=m
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=m
-CONFIG_TABLET_USB_AIPTEK=m
-CONFIG_TABLET_USB_GTCO=m
-CONFIG_TABLET_USB_HANWANG=m
-CONFIG_TABLET_USB_KBTAB=m
-CONFIG_TABLET_USB_PEGASUS=m
-CONFIG_TABLET_SERIAL_WACOM4=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_PROPERTIES=y
-CONFIG_TOUCHSCREEN_ADS7846=m
-CONFIG_TOUCHSCREEN_AD7877=m
-CONFIG_TOUCHSCREEN_AD7879=m
-CONFIG_TOUCHSCREEN_AD7879_I2C=m
-CONFIG_TOUCHSCREEN_AD7879_SPI=m
-CONFIG_TOUCHSCREEN_ADC=m
-CONFIG_TOUCHSCREEN_ATMEL_MXT=m
-# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set
-CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
-CONFIG_TOUCHSCREEN_BU21013=m
-CONFIG_TOUCHSCREEN_BU21029=m
-CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
-CONFIG_TOUCHSCREEN_CY8CTMA140=m
-CONFIG_TOUCHSCREEN_CY8CTMG110=m
-CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
-CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
-CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
-CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
-CONFIG_TOUCHSCREEN_DA9052=m
-CONFIG_TOUCHSCREEN_DYNAPRO=m
-CONFIG_TOUCHSCREEN_HAMPSHIRE=m
-CONFIG_TOUCHSCREEN_EETI=m
-CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
-CONFIG_TOUCHSCREEN_EXC3000=m
-CONFIG_TOUCHSCREEN_FUJITSU=m
-CONFIG_TOUCHSCREEN_GOODIX=m
-CONFIG_TOUCHSCREEN_HIDEEP=m
-CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
-CONFIG_TOUCHSCREEN_ILI210X=m
-CONFIG_TOUCHSCREEN_ILITEK=m
-CONFIG_TOUCHSCREEN_S6SY761=m
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_TOUCHSCREEN_EKTF2127=m
-CONFIG_TOUCHSCREEN_ELAN=m
-CONFIG_TOUCHSCREEN_ELO=m
-CONFIG_TOUCHSCREEN_WACOM_W8001=m
-CONFIG_TOUCHSCREEN_WACOM_I2C=m
-CONFIG_TOUCHSCREEN_MAX11801=m
-CONFIG_TOUCHSCREEN_MCS5000=m
-CONFIG_TOUCHSCREEN_MMS114=m
-CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
-CONFIG_TOUCHSCREEN_MSG2638=m
-CONFIG_TOUCHSCREEN_MTOUCH=m
-CONFIG_TOUCHSCREEN_IMAGIS=m
-CONFIG_TOUCHSCREEN_INEXIO=m
-CONFIG_TOUCHSCREEN_MK712=m
-# CONFIG_TOUCHSCREEN_HTCPEN is not set
-CONFIG_TOUCHSCREEN_PENMOUNT=m
-CONFIG_TOUCHSCREEN_EDT_FT5X06=m
-CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
-CONFIG_TOUCHSCREEN_TOUCHWIN=m
-CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m
-CONFIG_TOUCHSCREEN_UCB1400=m
-CONFIG_TOUCHSCREEN_PIXCIR=m
-CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
-CONFIG_TOUCHSCREEN_WM831X=m
-CONFIG_TOUCHSCREEN_WM97XX=m
-CONFIG_TOUCHSCREEN_WM9705=y
-CONFIG_TOUCHSCREEN_WM9712=y
-CONFIG_TOUCHSCREEN_WM9713=y
-CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-CONFIG_TOUCHSCREEN_MC13783=m
-CONFIG_TOUCHSCREEN_USB_EGALAX=y
-CONFIG_TOUCHSCREEN_USB_PANJIT=y
-CONFIG_TOUCHSCREEN_USB_3M=y
-CONFIG_TOUCHSCREEN_USB_ITM=y
-CONFIG_TOUCHSCREEN_USB_ETURBO=y
-CONFIG_TOUCHSCREEN_USB_GUNZE=y
-CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
-CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
-CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
-CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
-CONFIG_TOUCHSCREEN_USB_GOTOP=y
-CONFIG_TOUCHSCREEN_USB_JASTEC=y
-CONFIG_TOUCHSCREEN_USB_ELO=y
-CONFIG_TOUCHSCREEN_USB_E2I=y
-CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
-CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
-CONFIG_TOUCHSCREEN_USB_NEXIO=y
-CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
-CONFIG_TOUCHSCREEN_TOUCHIT213=m
-CONFIG_TOUCHSCREEN_TSC_SERIO=m
-CONFIG_TOUCHSCREEN_TSC200X_CORE=m
-CONFIG_TOUCHSCREEN_TSC2004=m
-CONFIG_TOUCHSCREEN_TSC2005=m
-CONFIG_TOUCHSCREEN_TSC2007=m
-CONFIG_TOUCHSCREEN_TSC2007_IIO=y
-CONFIG_TOUCHSCREEN_PCAP=m
-CONFIG_TOUCHSCREEN_RM_TS=m
-CONFIG_TOUCHSCREEN_SILEAD=m
-CONFIG_TOUCHSCREEN_SIS_I2C=m
-CONFIG_TOUCHSCREEN_ST1232=m
-CONFIG_TOUCHSCREEN_STMFTS=m
-CONFIG_TOUCHSCREEN_SUR40=m
-CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
-CONFIG_TOUCHSCREEN_SX8654=m
-CONFIG_TOUCHSCREEN_TPS6507X=m
-CONFIG_TOUCHSCREEN_ZET6223=m
-CONFIG_TOUCHSCREEN_ZFORCE=m
-CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
-CONFIG_TOUCHSCREEN_ROHM_BU21023=m
-CONFIG_TOUCHSCREEN_IQS5XX=m
-CONFIG_TOUCHSCREEN_ZINITIX=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_ATC260X_ONKEY=m
-CONFIG_INPUT_88PM80X_ONKEY=m
-CONFIG_INPUT_AD714X=m
-CONFIG_INPUT_AD714X_I2C=m
-CONFIG_INPUT_AD714X_SPI=m
-CONFIG_INPUT_ARIZONA_HAPTICS=m
-CONFIG_INPUT_BMA150=m
-CONFIG_INPUT_E3X0_BUTTON=m
-CONFIG_INPUT_PCSPKR=m
-CONFIG_INPUT_MAX77693_HAPTIC=m
-CONFIG_INPUT_MC13783_PWRBUTTON=m
-CONFIG_INPUT_MMA8450=m
-CONFIG_INPUT_APANEL=m
-CONFIG_INPUT_GPIO_BEEPER=m
-CONFIG_INPUT_GPIO_DECODER=m
-CONFIG_INPUT_GPIO_VIBRA=m
-# CONFIG_INPUT_WISTRON_BTNS is not set
-CONFIG_INPUT_ATLAS_BTNS=m
-CONFIG_INPUT_ATI_REMOTE2=m
-CONFIG_INPUT_KEYSPAN_REMOTE=m
-CONFIG_INPUT_KXTJ9=m
-CONFIG_INPUT_POWERMATE=m
-CONFIG_INPUT_YEALINK=m
-CONFIG_INPUT_CM109=m
-CONFIG_INPUT_REGULATOR_HAPTIC=m
-CONFIG_INPUT_RETU_PWRBUTTON=m
-CONFIG_INPUT_AXP20X_PEK=m
-CONFIG_INPUT_UINPUT=m
-CONFIG_INPUT_PCF50633_PMU=m
-CONFIG_INPUT_PCF8574=m
-CONFIG_INPUT_PWM_BEEPER=m
-CONFIG_INPUT_PWM_VIBRA=m
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-CONFIG_INPUT_DA7280_HAPTICS=m
-CONFIG_INPUT_DA9052_ONKEY=m
-CONFIG_INPUT_DA9063_ONKEY=m
-CONFIG_INPUT_WM831X_ON=m
-CONFIG_INPUT_PCAP=m
-CONFIG_INPUT_ADXL34X=m
-CONFIG_INPUT_IBM_PANEL=m
-CONFIG_INPUT_ADXL34X_I2C=m
-CONFIG_INPUT_ADXL34X_SPI=m
-CONFIG_INPUT_IMS_PCU=m
-CONFIG_INPUT_IQS269A=m
-CONFIG_INPUT_IQS626A=m
-CONFIG_INPUT_CMA3000=m
-CONFIG_INPUT_CMA3000_I2C=m
-CONFIG_INPUT_IDEAPAD_SLIDEBAR=m
-CONFIG_INPUT_SOC_BUTTON_ARRAY=m
-CONFIG_INPUT_DRV260X_HAPTICS=m
-CONFIG_INPUT_DRV2665_HAPTICS=m
-CONFIG_INPUT_DRV2667_HAPTICS=m
-CONFIG_INPUT_RAVE_SP_PWRBUTTON=m
-CONFIG_INPUT_RT5120_PWRKEY=m
-CONFIG_RMI4_CORE=m
-CONFIG_RMI4_I2C=m
-CONFIG_RMI4_SPI=m
-CONFIG_RMI4_SMB=m
-CONFIG_RMI4_F03=y
-CONFIG_RMI4_F03_SERIO=m
-CONFIG_RMI4_2D_SENSOR=y
-CONFIG_RMI4_F11=y
-CONFIG_RMI4_F12=y
-CONFIG_RMI4_F30=y
-CONFIG_RMI4_F34=y
-CONFIG_RMI4_F3A=y
-CONFIG_RMI4_F54=y
-CONFIG_RMI4_F55=y
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=m
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_SERIO_I8042=y
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_CT82C710=m
-CONFIG_SERIO_PARKBD=m
-CONFIG_SERIO_PCIPS2=m
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_RAW=m
-CONFIG_SERIO_ALTERA_PS2=m
-CONFIG_SERIO_PS2MULT=m
-CONFIG_SERIO_ARC_PS2=m
-CONFIG_HYPERV_KEYBOARD=m
-CONFIG_SERIO_GPIO_PS2=m
-CONFIG_USERIO=m
-CONFIG_GAMEPORT=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_GAMEPORT_EMU10K1=m
-CONFIG_GAMEPORT_FM801=m
-# end of Hardware I/O ports
-# end of Input device support
-
-#
-# Character devices
-#
-CONFIG_TTY=y
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LDISC_AUTOLOAD=y
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_EARLYCON=y
-CONFIG_SERIAL_8250=y
-# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-CONFIG_SERIAL_8250_PNP=y
-# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
-CONFIG_SERIAL_8250_FINTEK=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_DMA=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_CS=m
-CONFIG_SERIAL_8250_MEN_MCB=m
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-# CONFIG_SERIAL_8250_FOURPORT is not set
-# CONFIG_SERIAL_8250_ACCENT is not set
-# CONFIG_SERIAL_8250_BOCA is not set
-# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
-# CONFIG_SERIAL_8250_HUB6 is not set
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_DW=m
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_8250_LPSS=y
-CONFIG_SERIAL_8250_MID=y
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_MAX3100=m
-CONFIG_SERIAL_MAX310X=y
-CONFIG_SERIAL_UARTLITE=m
-CONFIG_SERIAL_UARTLITE_NR_UARTS=1
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_JSM=m
-CONFIG_SERIAL_LANTIQ=m
-CONFIG_SERIAL_SCCNXP=m
-CONFIG_SERIAL_SC16IS7XX_CORE=m
-CONFIG_SERIAL_SC16IS7XX=m
-CONFIG_SERIAL_SC16IS7XX_I2C=y
-CONFIG_SERIAL_SC16IS7XX_SPI=y
-# CONFIG_SERIAL_TIMBERDALE is not set
-CONFIG_SERIAL_BCM63XX=m
-CONFIG_SERIAL_ALTERA_JTAGUART=m
-CONFIG_SERIAL_ALTERA_UART=m
-CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
-CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
-CONFIG_SERIAL_IFX6X60=m
-# CONFIG_SERIAL_PCH_UART is not set
-CONFIG_SERIAL_ARC=m
-CONFIG_SERIAL_ARC_NR_PORTS=1
-CONFIG_SERIAL_RP2=m
-CONFIG_SERIAL_RP2_NR_UARTS=32
-CONFIG_SERIAL_FSL_LPUART=m
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_FSL_LINFLEXUART=m
-CONFIG_SERIAL_MEN_Z135=m
-CONFIG_SERIAL_SPRD=m
-# end of Serial drivers
-
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_ROCKETPORT=m
-CONFIG_CYCLADES=m
-CONFIG_CYZ_INTR=y
-CONFIG_MOXA_INTELLIO=m
-CONFIG_MOXA_SMARTIO=m
-CONFIG_SYNCLINK=m
-CONFIG_SYNCLINKMP=m
-CONFIG_SYNCLINK_GT=m
-CONFIG_ISI=m
-CONFIG_N_HDLC=m
-CONFIG_N_GSM=m
-CONFIG_NOZOMI=m
-CONFIG_NULL_TTY=m
-CONFIG_TRACE_ROUTER=m
-CONFIG_TRACE_SINK=m
-CONFIG_HVC_DRIVER=y
-CONFIG_SERIAL_DEV_BUS=m
-# CONFIG_TTY_PRINTK is not set
-CONFIG_PRINTER=m
-CONFIG_LP_CONSOLE=y
-CONFIG_PPDEV=m
-CONFIG_VIRTIO_CONSOLE=m
-CONFIG_IPMI_HANDLER=m
-CONFIG_IPMI_DMI_DECODE=y
-CONFIG_IPMI_PLAT_DATA=y
-CONFIG_IPMI_PANIC_EVENT=y
-CONFIG_IPMI_PANIC_STRING=y
-CONFIG_IPMI_DEVICE_INTERFACE=m
-CONFIG_IPMI_SI=m
-CONFIG_IPMI_SSIF=m
-CONFIG_IPMI_WATCHDOG=m
-CONFIG_IPMI_POWEROFF=m
-CONFIG_NPCM7XX_KCS_IPMI_BMC=m
-CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m
-CONFIG_IPMI_KCS_BMC_SERIO=m
-CONFIG_IPMB_DEVICE_INTERFACE=m
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=y
-CONFIG_HW_RANDOM_INTEL=y
-CONFIG_HW_RANDOM_AMD=y
-CONFIG_HW_RANDOM_BA431=y
-CONFIG_HW_RANDOM_GEODE=y
-CONFIG_HW_RANDOM_VIA=y
-# CONFIG_HW_RANDOM_VIRTIO is not set
-CONFIG_HW_RANDOM_XIPHERA=m
-# CONFIG_DTLK is not set
-CONFIG_APPLICOM=m
-# CONFIG_SONYPI is not set
-
-#
-# PCMCIA character devices
-#
-CONFIG_SYNCLINK_CS=m
-CONFIG_CARDMAN_4000=m
-CONFIG_CARDMAN_4040=m
-CONFIG_SCR24X=m
-CONFIG_IPWIRELESS=m
-# end of PCMCIA character devices
-
-CONFIG_MWAVE=m
-# CONFIG_PC8736x_GPIO is not set
-# CONFIG_NSC_GPIO is not set
-CONFIG_DEVMEM=y
-# CONFIG_DEVKMEM is not set
-CONFIG_NVRAM=m
-CONFIG_RAW_DRIVER=m
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_DEVPORT=y
-CONFIG_HPET=y
-CONFIG_HPET_MMAP=y
-CONFIG_HPET_MMAP_DEFAULT=y
-CONFIG_HANGCHECK_TIMER=m
-CONFIG_TCG_TPM=m
-CONFIG_HW_RANDOM_TPM=y
-CONFIG_TCG_TIS_CORE=m
-CONFIG_TCG_TIS=m
-CONFIG_TCG_TIS_SPI=m
-# CONFIG_TCG_TIS_SPI_CR50 is not set
-CONFIG_TCG_TIS_I2C_CR50=m
-CONFIG_TCG_TIS_I2C_ATMEL=m
-CONFIG_TCG_TIS_I2C_INFINEON=m
-CONFIG_TCG_TIS_I2C_NUVOTON=m
-CONFIG_TCG_NSC=m
-CONFIG_TCG_ATMEL=m
-CONFIG_TCG_INFINEON=m
-CONFIG_TCG_CRB=m
-CONFIG_TCG_VTPM_PROXY=m
-CONFIG_TCG_TIS_ST33ZP24=m
-CONFIG_TCG_TIS_ST33ZP24_I2C=m
-CONFIG_TCG_TIS_ST33ZP24_SPI=m
-CONFIG_TELCLOCK=m
-CONFIG_XILLYBUS=m
-CONFIG_XILLYBUS_PCIE=m
-CONFIG_XILLYUSB=m
-# end of Character devices
-
-CONFIG_RANDOM_TRUST_CPU=y
-CONFIG_RANDOM_TRUST_BOOTLOADER=y
-
-#
-# I2C support
-#
-CONFIG_I2C=m
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_MUX=m
-
-#
-# Multiplexer I2C Chip support
-#
-CONFIG_I2C_MUX_GPIO=m
-CONFIG_I2C_MUX_LTC4306=m
-CONFIG_I2C_MUX_PCA9541=m
-CONFIG_I2C_MUX_PCA954x=m
-CONFIG_I2C_MUX_REG=m
-CONFIG_I2C_MUX_MLXCPLD=m
-# end of Multiplexer I2C Chip support
-
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_SMBUS=m
-CONFIG_I2C_ALGOBIT=m
-CONFIG_I2C_ALGOPCA=m
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# PC SMBus host controller drivers
-#
-CONFIG_I2C_ALI1535=m
-CONFIG_I2C_ALI1563=m
-CONFIG_I2C_ALI15X3=m
-CONFIG_I2C_AMD756=m
-CONFIG_I2C_AMD756_S4882=m
-CONFIG_I2C_AMD8111=m
-CONFIG_I2C_AMD_MP2=m
-CONFIG_I2C_I801=m
-CONFIG_I2C_ISCH=m
-CONFIG_I2C_ISMT=m
-CONFIG_I2C_PIIX4=m
-CONFIG_I2C_NFORCE2=m
-CONFIG_I2C_NFORCE2_S4985=m
-CONFIG_I2C_NVIDIA_GPU=m
-CONFIG_I2C_SIS5595=m
-CONFIG_I2C_SIS630=m
-CONFIG_I2C_SIS96X=m
-CONFIG_I2C_VIA=m
-CONFIG_I2C_VIAPRO=m
-
-#
-# ACPI drivers
-#
-CONFIG_I2C_SCMI=m
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-CONFIG_I2C_CBUS_GPIO=m
-CONFIG_I2C_DESIGNWARE_CORE=m
-# CONFIG_I2C_DESIGNWARE_SLAVE is not set
-CONFIG_I2C_DESIGNWARE_PLATFORM=m
-CONFIG_I2C_DESIGNWARE_AMDPSP=y
-# CONFIG_I2C_DESIGNWARE_BAYTRAIL is not set
-CONFIG_I2C_DESIGNWARE_PCI=m
-# CONFIG_I2C_EG20T is not set
-CONFIG_I2C_EMEV2=m
-CONFIG_I2C_GPIO=m
-CONFIG_I2C_HISI=m
-# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
-CONFIG_I2C_KEMPLD=m
-CONFIG_I2C_OCORES=m
-CONFIG_I2C_PCA_PLATFORM=m
-CONFIG_I2C_SIMTEC=m
-CONFIG_I2C_XILINX=m
-
-#
-# External I2C/SMBus adapter drivers
-#
-CONFIG_I2C_DIOLAN_U2C=m
-CONFIG_I2C_CP2615=m
-CONFIG_I2C_DLN2=m
-CONFIG_I2C_PARPORT=m
-CONFIG_I2C_PCI1XXXX=m
-CONFIG_I2C_ROBOTFUZZ_OSIF=m
-CONFIG_I2C_TAOS_EVM=m
-CONFIG_I2C_TINY_USB=m
-CONFIG_I2C_VIPERBOARD=m
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_ISA is not set
-CONFIG_I2C_CROS_EC_TUNNEL=m
-# CONFIG_SCx200_ACB is not set
-# end of I2C Hardware Bus support
-
-# CONFIG_I2C_STUB is not set
-CONFIG_I2C_SLAVE=y
-CONFIG_I2C_SLAVE_EEPROM=m
-CONFIG_I2C_SLAVE_TESTUNIT=m
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# end of I2C support
-
-CONFIG_I3C=m
-CONFIG_CDNS_I3C_MASTER=m
-CONFIG_DW_I3C_MASTER=m
-CONFIG_SVC_I3C_MASTER=m
-CONFIG_MIPI_I3C_HCI=m
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-
-#
-# SPI Master Controller Drivers
-#
-CONFIG_SPI_ALTERA=m
-CONFIG_SPI_ALTERA_CORE=m
-CONFIG_SPI_ALTERA_DFL=m
-CONFIG_SPI_AXI_SPI_ENGINE=m
-CONFIG_SPI_BITBANG=m
-CONFIG_SPI_BUTTERFLY=m
-CONFIG_SPI_CADENCE=m
-CONFIG_SPI_DESIGNWARE=m
-# CONFIG_SPI_DW_DMA is not set
-CONFIG_SPI_DW_PCI=m
-CONFIG_SPI_DW_MMIO=m
-CONFIG_SPI_DLN2=m
-CONFIG_SPI_NXP_FLEXSPI=m
-CONFIG_SPI_GPIO=m
-CONFIG_SPI_INTEL_PCI=m
-CONFIG_SPI_INTEL_PLATFORM=m
-CONFIG_SPI_LM70_LLP=m
-CONFIG_SPI_LANTIQ_SSC=m
-CONFIG_SPI_OC_TINY=m
-CONFIG_SPI_PXA2XX=m
-CONFIG_SPI_PXA2XX_PCI=m
-# CONFIG_SPI_ROCKCHIP is not set
-CONFIG_SPI_SC18IS602=m
-CONFIG_SPI_SIFIVE=m
-CONFIG_SPI_MXIC=m
-CONFIG_SPI_TEGRA210_QUAD=m
-# CONFIG_SPI_TOPCLIFF_PCH is not set
-CONFIG_SPI_XCOMM=m
-CONFIG_SPI_XILINX=m
-CONFIG_SPI_ZYNQMP_GQSPI=m
-CONFIG_SPI_AMD=m
-
-#
-# SPI Multiplexer support
-#
-CONFIG_SPI_MUX=m
-
-#
-# SPI Protocol Masters
-#
-CONFIG_SPI_SPIDEV=m
-CONFIG_SPI_LOOPBACK_TEST=m
-CONFIG_SPI_TLE62X0=m
-CONFIG_SPI_SLAVE=y
-CONFIG_SPI_SLAVE_TIME=m
-CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPMI=m
-CONFIG_HSI=m
-CONFIG_HSI_BOARDINFO=y
-
-#
-# HSI controllers
-#
-
-#
-# HSI clients
-#
-CONFIG_HSI_CHAR=m
-CONFIG_PPS=y
-# CONFIG_PPS_DEBUG is not set
-
-#
-# PPS clients support
-#
-# CONFIG_PPS_CLIENT_KTIMER is not set
-CONFIG_PPS_CLIENT_LDISC=m
-CONFIG_PPS_CLIENT_PARPORT=m
-CONFIG_PPS_CLIENT_GPIO=m
-
-#
-# PPS generators support
-#
-
-#
-# PTP clock support
-#
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_DP83640_PHY=m
-CONFIG_PTP_1588_CLOCK_INES=m
-CONFIG_PTP_1588_CLOCK_KVM=m
-# CONFIG_PTP_1588_CLOCK_PCH is not set
-CONFIG_PTP_1588_CLOCK_KVM=m
-CONFIG_PTP_1588_CLOCK_IDT82P33=m
-CONFIG_PTP_1588_CLOCK_IDTCM=m
-CONFIG_PTP_1588_CLOCK_OCP=m
-CONFIG_PTP_1588_CLOCK_VMW=m
-# end of PTP clock support
-
-CONFIG_PINCTRL=y
-CONFIG_PINMUX=y
-CONFIG_PINCONF=y
-CONFIG_GENERIC_PINCONF=y
-# CONFIG_DEBUG_PINCTRL is not set
-CONFIG_PINCTRL_AMD=m
-CONFIG_PINCTRL_CY8C95X0=m
-CONFIG_PINCTRL_DA9062=m
-CONFIG_PINCTRL_MCP23S08_I2C=m
-CONFIG_PINCTRL_MCP23S08_SPI=m
-CONFIG_PINCTRL_MCP23S08=m
-CONFIG_PINCTRL_BAYTRAIL=y
-CONFIG_PINCTRL_CHERRYVIEW=m
-CONFIG_PINCTRL_LYNXPOINT=m
-CONFIG_PINCTRL_ALDERLAKE=m
-CONFIG_PINCTRL_INTEL=y
-CONFIG_PINCTRL_BROXTON=m
-CONFIG_PINCTRL_CANNONLAKE=m
-CONFIG_PINCTRL_CEDARFORK=m
-CONFIG_PINCTRL_DENVERTON=m
-CONFIG_PINCTRL_ELKHARTLAKE=m
-CONFIG_PINCTRL_EMMITSBURG=m
-CONFIG_PINCTRL_GEMINILAKE=m
-CONFIG_PINCTRL_ICELAKE=m
-CONFIG_PINCTRL_JASPERLAKE=m
-CONFIG_PINCTRL_LAKEFIELD=m
-CONFIG_PINCTRL_LEWISBURG=m
-CONFIG_PINCTRL_METEORLAKE=m
-CONFIG_PINCTRL_SUNRISEPOINT=m
-CONFIG_PINCTRL_TIGERLAKE=m
-
-#
-# Renesas pinctrl drivers
-#
-# end of Renesas pinctrl drivers
-
-CONFIG_PINCTRL_MADERA=m
-CONFIG_PINCTRL_CS47L15=y
-CONFIG_PINCTRL_CS47L35=y
-CONFIG_PINCTRL_CS47L85=y
-CONFIG_PINCTRL_CS47L90=y
-CONFIG_PINCTRL_CS47L92=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_FASTPATH_LIMIT=512
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIOLIB_IRQCHIP=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_CDEV=y
-# CONFIG_GPIO_CDEV_V1 is not set
-CONFIG_GPIO_GENERIC=m
-CONFIG_GPIO_REGMAP=m
-CONFIG_GPIO_MAX730X=m
-
-#
-# Memory mapped GPIO drivers
-#
-CONFIG_GPIO_AMDPT=m
-CONFIG_GPIO_DWAPB=m
-CONFIG_GPIO_EXAR=m
-CONFIG_GPIO_GENERIC_PLATFORM=m
-CONFIG_GPIO_ICH=m
-CONFIG_GPIO_MB86S7X=m
-CONFIG_GPIO_MENZ127=m
-CONFIG_GPIO_SIOX=m
-CONFIG_GPIO_VX855=m
-CONFIG_GPIO_XILINX=m
-CONFIG_GPIO_AMD_FCH=m
-CONFIG_GPIO_MSC313=y
-# end of Memory mapped GPIO drivers
-
-#
-# Port-mapped I/O GPIO drivers
-#
-CONFIG_GPIO_F7188X=m
-CONFIG_GPIO_IT87=m
-CONFIG_GPIO_SCH=m
-CONFIG_GPIO_SCH311X=m
-CONFIG_GPIO_WINBOND=m
-CONFIG_GPIO_WS16C48=m
-# end of Port-mapped I/O GPIO drivers
-
-#
-# I2C GPIO expanders
-#
-CONFIG_GPIO_ADP5588=m
-CONFIG_GPIO_MAX7300=m
-CONFIG_GPIO_MAX732X=m
-CONFIG_GPIO_PCA953X=m
-# CONFIG_GPIO_PCA953X_IRQ is not set
-CONFIG_GPIO_PCA9570=m
-CONFIG_GPIO_PCF857X=m
-CONFIG_GPIO_TPIC2810=m
-# end of I2C GPIO expanders
-
-#
-# MFD GPIO expanders
-#
-CONFIG_GPIO_ARIZONA=m
-CONFIG_GPIO_BD9571MWV=m
-CONFIG_GPIO_DA9052=m
-CONFIG_GPIO_DLN2=m
-CONFIG_GPIO_JANZ_TTL=m
-CONFIG_GPIO_KEMPLD=m
-CONFIG_GPIO_LP3943=m
-CONFIG_GPIO_LP873X=m
-CONFIG_GPIO_MADERA=m
-CONFIG_GPIO_SL28CPLD=m
-CONFIG_GPIO_TPS65086=m
-CONFIG_GPIO_TPS65912=m
-CONFIG_GPIO_TPS68470=y
-CONFIG_GPIO_TQMX86=m
-CONFIG_GPIO_UCB1400=m
-CONFIG_GPIO_WHISKEY_COVE=m
-CONFIG_GPIO_WM831X=m
-CONFIG_GPIO_WM8994=m
-# end of MFD GPIO expanders
-
-#
-# PCI GPIO expanders
-#
-CONFIG_GPIO_AMD8111=m
-CONFIG_GPIO_ML_IOH=m
-# CONFIG_GPIO_PCH is not set
-CONFIG_GPIO_PCI_IDIO_16=m
-CONFIG_GPIO_PCIE_IDIO_24=m
-CONFIG_GPIO_RDC321X=m
-# end of PCI GPIO expanders
-
-#
-# SPI GPIO expanders
-#
-CONFIG_GPIO_MAX3191X=m
-CONFIG_GPIO_MAX7301=m
-CONFIG_GPIO_MC33880=m
-CONFIG_GPIO_PISOSR=m
-CONFIG_GPIO_XRA1403=m
-# end of SPI GPIO expanders
-
-#
-# USB GPIO expanders
-#
-CONFIG_GPIO_VIPERBOARD=m
-# end of USB GPIO expanders
-
-CONFIG_GPIO_AGGREGATOR=m
-CONFIG_GPIO_MOCKUP=m
-CONFIG_W1=m
-CONFIG_W1_CON=y
-
-#
-# 1-wire Bus Masters
-#
-CONFIG_W1_MASTER_MATROX=m
-CONFIG_W1_MASTER_DS2490=m
-CONFIG_W1_MASTER_DS2482=m
-CONFIG_W1_MASTER_DS1WM=m
-CONFIG_W1_MASTER_GPIO=m
-CONFIG_W1_MASTER_SGI=m
-# end of 1-wire Bus Masters
-
-#
-# 1-wire Slaves
-#
-CONFIG_W1_SLAVE_THERM=m
-CONFIG_W1_SLAVE_SMEM=m
-# CONFIG_W1_SLAVE_DS2405 is not set
-CONFIG_W1_SLAVE_DS2408=m
-# CONFIG_W1_SLAVE_DS2408_READBACK is not set
-CONFIG_W1_SLAVE_DS2413=m
-CONFIG_W1_SLAVE_DS2406=m
-CONFIG_W1_SLAVE_DS2423=m
-CONFIG_W1_SLAVE_DS2805=m
-CONFIG_W1_SLAVE_DS2430=m
-CONFIG_W1_SLAVE_DS2431=m
-CONFIG_W1_SLAVE_DS2433=m
-CONFIG_W1_SLAVE_DS2433_CRC=y
-CONFIG_W1_SLAVE_DS2438=m
-CONFIG_W1_SLAVE_DS250X=m
-CONFIG_W1_SLAVE_DS2780=m
-CONFIG_W1_SLAVE_DS2781=m
-CONFIG_W1_SLAVE_DS28E04=m
-CONFIG_W1_SLAVE_DS28E17=m
-# end of 1-wire Slaves
-
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_MT6323=y
-CONFIG_POWER_RESET_ATC260X=m
-# CONFIG_POWER_RESET_RESTART is not set
-CONFIG_POWER_RESET_REGULATOR=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PDA_POWER=m
-CONFIG_GENERIC_ADC_BATTERY=m
-CONFIG_IP5XXX_POWER=m
-CONFIG_WM831X_BACKUP=m
-CONFIG_WM831X_POWER=m
-# CONFIG_TEST_POWER is not set
-CONFIG_CHARGER_ADP5061=m
-CONFIG_BATTERY_CW2015=m
-CONFIG_BATTERY_DS2760=m
-CONFIG_BATTERY_DS2780=m
-CONFIG_BATTERY_DS2781=m
-CONFIG_BATTERY_DS2782=m
-# CONFIG_BATTERY_SAMSUNG_SDI is not set
-CONFIG_BATTERY_SBS=m
-CONFIG_CHARGER_SBS=m
-CONFIG_MANAGER_SBS=m
-CONFIG_BATTERY_BQ27XXX=m
-CONFIG_BATTERY_BQ27XXX_I2C=m
-CONFIG_BATTERY_BQ27XXX_HDQ=m
-# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set
-CONFIG_BATTERY_DA9052=m
-CONFIG_CHARGER_DA9150=m
-CONFIG_BATTERY_DA9150=m
-CONFIG_CHARGER_AXP20X=m
-CONFIG_BATTERY_AXP20X=m
-CONFIG_AXP20X_POWER=m
-CONFIG_AXP288_CHARGER=m
-CONFIG_AXP288_FUEL_GAUGE=m
-CONFIG_BATTERY_MAX17040=m
-CONFIG_BATTERY_MAX17042=m
-CONFIG_BATTERY_MAX1721X=m
-CONFIG_CHARGER_PCF50633=m
-CONFIG_CHARGER_ISP1704=m
-CONFIG_CHARGER_MAX8903=m
-CONFIG_CHARGER_LP8727=m
-CONFIG_CHARGER_GPIO=m
-CONFIG_CHARGER_MANAGER=y
-CONFIG_CHARGER_LT3651=m
-CONFIG_CHARGER_LTC4162L=m
-CONFIG_CHARGER_MAX14577=m
-CONFIG_CHARGER_MAX77693=m
-CONFIG_CHARGER_MP2629=m
-CONFIG_CHARGER_BQ2415X=m
-CONFIG_CHARGER_BQ24190=m
-CONFIG_CHARGER_BQ24257=m
-CONFIG_CHARGER_BQ24735=m
-CONFIG_CHARGER_BQ2515X=m
-CONFIG_CHARGER_BQ25890=m
-CONFIG_CHARGER_BQ25980=m
-CONFIG_CHARGER_BQ256XX=m
-CONFIG_CHARGER_RK817=m
-CONFIG_CHARGER_SMB347=m
-CONFIG_BATTERY_GAUGE_LTC2941=m
-CONFIG_BATTERY_GOLDFISH=m
-CONFIG_BATTERY_RT5033=m
-CONFIG_CHARGER_RT9455=m
-CONFIG_CHARGER_CROS_USBPD=m
-CONFIG_CHARGER_BD99954=m
-CONFIG_BATTERY_UG3105=m
-CONFIG_CHARGER_SURFACE=m
-CONFIG_SURFACE_HID=m
-CONFIG_BATTERY_SURFACE=m
-CONFIG_CHARGER_WILCO=m
-CONFIG_HWMON=y
-CONFIG_HWMON_VID=m
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Native drivers
-#
-CONFIG_SENSORS_ABITUGURU=m
-CONFIG_SENSORS_ABITUGURU3=m
-CONFIG_SENSORS_AD7314=m
-CONFIG_SENSORS_AD7414=m
-CONFIG_SENSORS_AD7418=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1026=m
-CONFIG_SENSORS_ADM1029=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_ADM1177=m
-CONFIG_SENSORS_ADM9240=m
-CONFIG_SENSORS_ADT7X10=m
-CONFIG_SENSORS_ADT7310=m
-CONFIG_SENSORS_ADT7410=m
-CONFIG_SENSORS_ADT7411=m
-CONFIG_SENSORS_ADT7462=m
-CONFIG_SENSORS_ADT7470=m
-CONFIG_SENSORS_ADT7475=m
-CONFIG_SENSORS_AHT10=m
-CONFIG_SENSORS_AS370=m
-CONFIG_SENSORS_ASC7621=m
-CONFIG_SENSORS_AXI_FAN_CONTROL=m
-CONFIG_SENSORS_K8TEMP=m
-CONFIG_SENSORS_K10TEMP=m
-CONFIG_SENSORS_FAM15H_POWER=m
-CONFIG_SENSORS_AMD_ENERGY=m
-CONFIG_SENSORS_APPLESMC=m
-CONFIG_SENSORS_ASB100=m
-CONFIG_SENSORS_ASPEED=m
-CONFIG_SENSORS_ATXP1=m
-CONFIG_SENSORS_CORSAIR_CPRO=m
-CONFIG_SENSORS_CORSAIR_PSU=m
-CONFIG_SENSORS_DRIVETEMP=m
-CONFIG_SENSORS_DS620=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_DELL_SMM=m
-# CONFIG_I8K is not set
-CONFIG_SENSORS_DA9052_ADC=m
-CONFIG_SENSORS_I5K_AMB=m
-CONFIG_SENSORS_F71805F=m
-CONFIG_SENSORS_F71882FG=m
-CONFIG_SENSORS_F75375S=m
-CONFIG_SENSORS_MC13783_ADC=m
-CONFIG_SENSORS_FSCHMD=m
-CONFIG_SENSORS_FTSTEUTATES=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_GL520SM=m
-CONFIG_SENSORS_G760A=m
-CONFIG_SENSORS_G762=m
-CONFIG_SENSORS_HIH6130=m
-CONFIG_SENSORS_IBMAEM=m
-CONFIG_SENSORS_IBMPEX=m
-CONFIG_SENSORS_IIO_HWMON=m
-CONFIG_SENSORS_I5500=m
-CONFIG_SENSORS_CORETEMP=m
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_JC42=m
-CONFIG_SENSORS_POWR1220=m
-CONFIG_SENSORS_LINEAGE=m
-CONFIG_SENSORS_LTC2945=m
-CONFIG_SENSORS_LTC2947=m
-CONFIG_SENSORS_LTC2947_I2C=m
-CONFIG_SENSORS_LTC2947_SPI=m
-CONFIG_SENSORS_LTC2990=m
-CONFIG_SENSORS_LTC2992=m
-CONFIG_SENSORS_LTC4151=m
-CONFIG_SENSORS_LTC4215=m
-CONFIG_SENSORS_LTC4222=m
-CONFIG_SENSORS_LTC4245=m
-CONFIG_SENSORS_LTC4260=m
-CONFIG_SENSORS_LTC4261=m
-CONFIG_SENSORS_MAX1111=m
-CONFIG_SENSORS_MAX127=m
-CONFIG_SENSORS_MAX16065=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_MAX1668=m
-CONFIG_SENSORS_MAX197=m
-CONFIG_SENSORS_MAX31722=m
-CONFIG_SENSORS_MAX31730=m
-CONFIG_SENSORS_MAX31760=m
-CONFIG_SENSORS_MAX6621=m
-CONFIG_SENSORS_MAX6639=m
-CONFIG_SENSORS_MAX6642=m
-CONFIG_SENSORS_MAX6650=m
-CONFIG_SENSORS_MAX6697=m
-CONFIG_SENSORS_MAX31790=m
-CONFIG_SENSORS_PM6764TR=m
-CONFIG_SENSORS_Q54SJ108A2=m
-CONFIG_SENSORS_STPDDC60=m
-CONFIG_SENSORS_MCP3021=m
-CONFIG_SENSORS_MLXREG_FAN=m
-CONFIG_SENSORS_TC654=m
-CONFIG_SENSORS_TPS23861=m
-CONFIG_SENSORS_MENF21BMC_HWMON=m
-CONFIG_SENSORS_MR75203=m
-CONFIG_SENSORS_ADCXX=m
-CONFIG_SENSORS_LM63=m
-CONFIG_SENSORS_LM70=m
-CONFIG_SENSORS_LM73=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM87=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_LM92=m
-CONFIG_SENSORS_LM93=m
-CONFIG_SENSORS_LM95234=m
-CONFIG_SENSORS_LM95241=m
-CONFIG_SENSORS_LM95245=m
-CONFIG_SENSORS_PC87360=m
-CONFIG_SENSORS_PC87427=m
-CONFIG_SENSORS_NTC_THERMISTOR=m
-CONFIG_SENSORS_NCT6683=m
-CONFIG_SENSORS_NCT6775=m
-CONFIG_SENSORS_NCT7802=m
-CONFIG_SENSORS_NCT7904=m
-CONFIG_SENSORS_NPCM7XX=m
-CONFIG_SENSORS_NZXT_KRAKEN2=m
-CONFIG_SENSORS_BPA_RS600=m
-CONFIG_SENSORS_FSP_3Y=m
-CONFIG_SENSORS_PCF8591=m
-CONFIG_PMBUS=m
-CONFIG_SENSORS_PMBUS=m
-CONFIG_SENSORS_ADM1266=m
-CONFIG_SENSORS_ADM1275=m
-CONFIG_SENSORS_BEL_PFE=m
-CONFIG_SENSORS_IBM_CFFPS=m
-CONFIG_SENSORS_DPS920AB=m
-CONFIG_SENSORS_INSPUR_IPSPS=m
-CONFIG_SENSORS_IR35221=m
-CONFIG_SENSORS_IR36021=m
-CONFIG_SENSORS_IR38064=m
-CONFIG_SENSORS_IRPS5401=m
-CONFIG_SENSORS_ISL68137=m
-CONFIG_SENSORS_LM25066=m
-CONFIG_SENSORS_LM25066_REGULATOR=y
-CONFIG_SENSORS_LTC2978=m
-CONFIG_SENSORS_LTC2978_REGULATOR=y
-CONFIG_SENSORS_LTC3815=m
-CONFIG_SENSORS_MAX15301=m
-CONFIG_SENSORS_MAX16064=m
-CONFIG_SENSORS_MAX16601=m
-CONFIG_SENSORS_MAX20730=m
-CONFIG_SENSORS_MAX20751=m
-CONFIG_SENSORS_MAX31785=m
-CONFIG_SENSORS_MAX34440=m
-CONFIG_SENSORS_MAX8688=m
-CONFIG_SENSORS_MP2888=m
-CONFIG_SENSORS_MP2975=m
-CONFIG_SENSORS_PIM4328=m
-CONFIG_SENSORS_PLI1209BC=m
-CONFIG_SENSORS_PLI1209BC_REGULATOR=y
-CONFIG_SENSORS_PXE1610=m
-CONFIG_SENSORS_TPS40422=m
-CONFIG_SENSORS_TPS53679=m
-CONFIG_SENSORS_TPS546D24=m
-CONFIG_SENSORS_UCD9000=m
-CONFIG_SENSORS_UCD9200=m
-CONFIG_SENSORS_XDPE122=m
-CONFIG_SENSORS_XDPE122_REGULATOR=y
-CONFIG_SENSORS_ZL6100=m
-CONFIG_SENSORS_SL28CPLD=m
-CONFIG_SENSORS_SBTSI=m
-CONFIG_AMD_SFH_HID=m
-CONFIG_SENSORS_SHT15=m
-CONFIG_SENSORS_SHT21=m
-CONFIG_SENSORS_SHT3x=m
-CONFIG_SENSORS_SHT4x=m
-CONFIG_SENSORS_SHTC1=m
-CONFIG_SENSORS_SIS5595=m
-CONFIG_SENSORS_SY7636A=m
-CONFIG_SENSORS_DME1737=m
-CONFIG_SENSORS_EMC1403=m
-CONFIG_SENSORS_EMC2103=m
-CONFIG_SENSORS_EMC2305=m
-CONFIG_SENSORS_EMC6W201=m
-CONFIG_SENSORS_SMSC47M1=m
-CONFIG_SENSORS_SMSC47M192=m
-CONFIG_SENSORS_SMSC47B397=m
-CONFIG_SENSORS_SCH56XX_COMMON=m
-CONFIG_SENSORS_SCH5627=m
-CONFIG_SENSORS_SCH5636=m
-CONFIG_SENSORS_STTS751=m
-CONFIG_SENSORS_SMM665=m
-CONFIG_SENSORS_ADC128D818=m
-CONFIG_SENSORS_ADS7828=m
-CONFIG_SENSORS_ADS7871=m
-CONFIG_SENSORS_AMC6821=m
-CONFIG_SENSORS_INA209=m
-CONFIG_SENSORS_INA2XX=m
-CONFIG_SENSORS_INA3221=m
-CONFIG_SENSORS_TC74=m
-CONFIG_SENSORS_THMC50=m
-CONFIG_SENSORS_TMP102=m
-CONFIG_SENSORS_TMP103=m
-CONFIG_SENSORS_TMP108=m
-CONFIG_SENSORS_TMP401=m
-CONFIG_SENSORS_TMP421=m
-CONFIG_SENSORS_TMP464=m
-CONFIG_SENSORS_TMP513=m
-CONFIG_SENSORS_VIA_CPUTEMP=m
-CONFIG_SENSORS_VIA686A=m
-CONFIG_SENSORS_VT1211=m
-CONFIG_SENSORS_VT8231=m
-CONFIG_SENSORS_W83773G=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83791D=m
-CONFIG_SENSORS_W83792D=m
-CONFIG_SENSORS_W83793=m
-CONFIG_SENSORS_W83795=m
-CONFIG_SENSORS_W83795_FANCTRL=y
-CONFIG_SENSORS_W83L785TS=m
-CONFIG_SENSORS_W83L786NG=m
-CONFIG_SENSORS_W83627HF=m
-CONFIG_SENSORS_W83627EHF=m
-CONFIG_SENSORS_WM831X=m
-CONFIG_SENSORS_XGENE=m
-CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m
-CONFIG_QCOM_SPMI_ADC_TM5=m
-
-#
-# ACPI drivers
-#
-CONFIG_SENSORS_ACPI_POWER=m
-CONFIG_SENSORS_ATK0110=m
-CONFIG_SENSORS_ASUS_WMI_EC=m
-CONFIG_SENSORS_ASUS_EC=m
-CONFIG_SENSORS_ASUS_WMI=m
-CONFIG_THERMAL=y
-CONFIG_THERMAL_NETLINK=y
-CONFIG_THERMAL_STATISTICS=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=100
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
-CONFIG_DEVFREQ_THERMAL=y
-# CONFIG_THERMAL_EMULATION is not set
-
-#
-# Intel thermal drivers
-#
-CONFIG_INTEL_POWERCLAMP=m
-CONFIG_X86_PKG_TEMP_THERMAL=m
-CONFIG_INTEL_SOC_DTS_IOSF_CORE=m
-CONFIG_INTEL_SOC_DTS_THERMAL=m
-
-#
-# ACPI INT340X thermal drivers
-#
-CONFIG_INT340X_THERMAL=m
-CONFIG_ACPI_THERMAL_REL=m
-CONFIG_INT3406_THERMAL=m
-# end of ACPI INT340X thermal drivers
-
-CONFIG_INTEL_BXT_PMIC_THERMAL=m
-CONFIG_INTEL_PCH_THERMAL=m
-CONFIG_INTEL_TCC_COOLING=m
-# end of Intel thermal drivers
-
-CONFIG_GENERIC_ADC_THERMAL=m
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_CORE=m
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
-CONFIG_WATCHDOG_OPEN_TIMEOUT=0
-# CONFIG_WATCHDOG_SYSFS is not set
-# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
-
-#
-# Watchdog Pretimeout Governors
-#
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-
-#
-# Watchdog Device Drivers
-#
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_BD957XMUF_WATCHDOG=m
-# CONFIG_SOFT_WATCHDOG_PRETIMEOUT is not set
-CONFIG_DA9052_WATCHDOG=m
-CONFIG_DA9063_WATCHDOG=m
-CONFIG_DA9062_WATCHDOG=m
-CONFIG_MENF21BMC_WATCHDOG=m
-CONFIG_MENZ069_WATCHDOG=m
-CONFIG_WDAT_WDT=m
-CONFIG_WM831X_WATCHDOG=m
-CONFIG_XILINX_WATCHDOG=m
-CONFIG_ZIIRAVE_WATCHDOG=m
-CONFIG_RAVE_SP_WATCHDOG=m
-CONFIG_MLX_WDT=m
-CONFIG_SL28CPLD_WATCHDOG=m
-CONFIG_CADENCE_WATCHDOG=m
-CONFIG_DW_WATCHDOG=m
-CONFIG_MAX63XX_WATCHDOG=m
-CONFIG_MAX77620_WATCHDOG=m
-CONFIG_RETU_WATCHDOG=m
-CONFIG_ACQUIRE_WDT=m
-CONFIG_ADVANTECH_WDT=m
-CONFIG_ALIM1535_WDT=m
-CONFIG_ALIM7101_WDT=m
-CONFIG_EBC_C384_WDT=m
-CONFIG_EXAR_WDT=m
-CONFIG_F71808E_WDT=m
-# CONFIG_SP5100_TCO is not set
-CONFIG_SBC_FITPC2_WATCHDOG=m
-CONFIG_EUROTECH_WDT=m
-CONFIG_IB700_WDT=m
-CONFIG_IBMASR=m
-CONFIG_WAFER_WDT=m
-CONFIG_I6300ESB_WDT=m
-CONFIG_HP_WATCHDOG=m
-CONFIG_IE6XX_WDT=m
-CONFIG_ITCO_WDT=m
-CONFIG_ITCO_VENDOR_SUPPORT=y
-CONFIG_IT8712F_WDT=m
-CONFIG_IT87_WDT=m
-CONFIG_HP_WATCHDOG=m
-CONFIG_HPWDT_NMI_DECODING=y
-CONFIG_KEMPLD_WDT=m
-CONFIG_BCM7038_WDT=m
-CONFIG_SC1200_WDT=m
-CONFIG_PC87413_WDT=m
-CONFIG_NV_TCO=m
-CONFIG_60XX_WDT=m
-# CONFIG_SBC8360_WDT is not set
-# CONFIG_SBC7240_WDT is not set
-CONFIG_CPU5_WDT=m
-CONFIG_SMSC_SCH311X_WDT=m
-CONFIG_SMSC37B787_WDT=m
-CONFIG_TQMX86_WDT=m
-CONFIG_VIA_WDT=m
-CONFIG_W83627HF_WDT=m
-CONFIG_W83877F_WDT=m
-CONFIG_W83977F_WDT=m
-CONFIG_MACHZ_WDT=m
-CONFIG_SBC_EPX_C3_WATCHDOG=m
-CONFIG_INTEL_MEI_WDT=m
-CONFIG_NI903X_WDT=m
-CONFIG_NIC7018_WDT=m
-CONFIG_SIEMENS_SIMATIC_IPC_WDT=m
-CONFIG_MEN_A21_WDT=m
-
-#
-# ISA-based Watchdog Cards
-#
-# CONFIG_PCWATCHDOG is not set
-# CONFIG_MIXCOMWD is not set
-# CONFIG_WDT is not set
-
-#
-# PCI-based Watchdog Cards
-#
-CONFIG_PCIPCWATCHDOG=m
-CONFIG_WDTPCI=m
-
-#
-# USB-based Watchdog Cards
-#
-CONFIG_USBPCWATCHDOG=m
-CONFIG_KEEMBAY_WATCHDOG=m
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SSB=m
-CONFIG_SSB_SPROM=y
-CONFIG_SSB_BLOCKIO=y
-CONFIG_SSB_PCIHOST_POSSIBLE=y
-CONFIG_SSB_PCIHOST=y
-CONFIG_SSB_B43_PCI_BRIDGE=y
-CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
-CONFIG_SSB_PCMCIAHOST=y
-CONFIG_SSB_SDIOHOST_POSSIBLE=y
-CONFIG_SSB_SDIOHOST=y
-CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
-CONFIG_SSB_DRIVER_PCICORE=y
-CONFIG_SSB_DRIVER_GPIO=y
-CONFIG_BCMA_POSSIBLE=y
-CONFIG_BCMA=m
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_SOC=y
-CONFIG_BCMA_DRIVER_PCI=y
-CONFIG_BCMA_SFLASH=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_DRIVER_GPIO=y
-# CONFIG_BCMA_DEBUG is not set
-
-#
-# Multifunction device drivers
-#
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_CS5535 is not set
-CONFIG_MFD_BCM590XX=m
-CONFIG_MFD_BD9571MWV=m
-CONFIG_MFD_AXP20X=m
-CONFIG_MFD_AXP20X_I2C=m
-CONFIG_MFD_CROS_EC_DEV=m
-CONFIG_MFD_MADERA=m
-CONFIG_MFD_MADERA_I2C=m
-CONFIG_MFD_MADERA_SPI=m
-CONFIG_MFD_CS47L15=y
-CONFIG_MFD_CS47L35=y
-CONFIG_MFD_CS47L85=y
-CONFIG_MFD_CS47L90=y
-CONFIG_MFD_CS47L92=y
-CONFIG_PMIC_DA9052=y
-CONFIG_MFD_DA9052_SPI=y
-CONFIG_MFD_DA9062=m
-CONFIG_MFD_DA9063=m
-CONFIG_MFD_DA9150=m
-CONFIG_MFD_DLN2=m
-CONFIG_MFD_MC13XXX=m
-CONFIG_MFD_MC13XXX_SPI=m
-CONFIG_MFD_MC13XXX_I2C=m
-CONFIG_MFD_MP2629=m
-CONFIG_HTC_PASIC3=m
-CONFIG_MFD_INTEL_QUARK_I2C_GPIO=m
-CONFIG_LPC_ICH=m
-CONFIG_LPC_SCH=m
-CONFIG_MFD_INTEL_PMT=m
-CONFIG_INTEL_SOC_PMIC_BXTWC=m
-CONFIG_INTEL_SOC_PMIC_CHTDC_TI=m
-CONFIG_INTEL_SOC_PMIC_MRFLD=m
-CONFIG_MFD_INTEL_LPSS=m
-CONFIG_MFD_INTEL_LPSS_ACPI=m
-CONFIG_MFD_INTEL_LPSS_PCI=m
-# CONFIG_MFD_INTEL_MSIC is not set
-CONFIG_MFD_INTEL_PMC_BXT=m
-CONFIG_MFD_IQS62X=m
-CONFIG_MFD_JANZ_CMODIO=m
-CONFIG_MFD_KEMPLD=m
-CONFIG_MFD_88PM800=m
-CONFIG_MFD_88PM805=m
-CONFIG_MFD_MAX14577=m
-CONFIG_MFD_MAX77693=m
-CONFIG_MFD_MAX77714=m
-CONFIG_MFD_MAX8907=m
-CONFIG_MFD_MT6360=m
-CONFIG_MFD_MT6370=m
-CONFIG_MFD_MT6397=m
-CONFIG_MFD_MENF21BMC=m
-CONFIG_MFD_OCELOT=m
-CONFIG_EZX_PCAP=y
-CONFIG_MFD_VIPERBOARD=m
-CONFIG_MFD_NTXEC=m
-CONFIG_MFD_ROHM_BD957XMUF=m
-CONFIG_MFD_RETU=m
-CONFIG_MFD_PCF50633=m
-CONFIG_PCF50633_ADC=m
-CONFIG_PCF50633_GPIO=m
-CONFIG_UCB1400_CORE=m
-CONFIG_MFD_SY7636A=m
-CONFIG_MFD_RDC321X=m
-CONFIG_MFD_RT4831=m
-CONFIG_MFD_RT5033=m
-CONFIG_MFD_RT5120=m
-CONFIG_MFD_SI476X_CORE=m
-CONFIG_MFD_SIMPLE_MFD_I2C=m
-CONFIG_MFD_SL28CPLD=m
-CONFIG_MFD_SM501=m
-CONFIG_MFD_SM501_GPIO=y
-CONFIG_MFD_SKY81452=m
-CONFIG_ABX500_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MFD_TI_AM335X_TSCADC=m
-CONFIG_MFD_LP3943=m
-CONFIG_MFD_TI_LMU=m
-CONFIG_TPS6105X=m
-CONFIG_TPS65010=m
-CONFIG_TPS6507X=m
-CONFIG_MFD_TPS65086=m
-CONFIG_MFD_TI_LP873X=m
-CONFIG_MFD_TPS65912=y
-CONFIG_MFD_TPS65912_I2C=m
-CONFIG_MFD_TPS65912_SPI=y
-CONFIG_MFD_WL1273_CORE=m
-CONFIG_MFD_LM3533=m
-# CONFIG_MFD_TIMBERDALE is not set
-CONFIG_MFD_TQMX86=m
-CONFIG_MFD_VX855=m
-CONFIG_MFD_ARIZONA=y
-CONFIG_MFD_ARIZONA_I2C=m
-CONFIG_MFD_ARIZONA_SPI=m
-CONFIG_MFD_CS47L24=y
-CONFIG_MFD_WM5102=y
-CONFIG_MFD_WM5110=y
-CONFIG_MFD_WM8997=y
-CONFIG_MFD_WM8998=y
-CONFIG_MFD_WM831X=y
-CONFIG_MFD_WM831X_SPI=y
-CONFIG_MFD_WM8994=m
-CONFIG_MFD_WCD934X=m
-CONFIG_MFD_ATC260X_I2C=m
-CONFIG_RAVE_SP_CORE=m
-CONFIG_MFD_INTEL_M10_BMC=m
-# end of Multifunction device drivers
-
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=m
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
-CONFIG_REGULATOR_USERSPACE_CONSUMER=m
-CONFIG_REGULATOR_88PG86X=m
-CONFIG_REGULATOR_88PM800=m
-CONFIG_REGULATOR_ACT8865=m
-CONFIG_REGULATOR_AD5398=m
-CONFIG_REGULATOR_ARIZONA_LDO1=m
-CONFIG_REGULATOR_ATC260X=m
-CONFIG_REGULATOR_ARIZONA_MICSUPP=m
-CONFIG_REGULATOR_AXP20X=m
-CONFIG_REGULATOR_BCM590XX=m
-CONFIG_REGULATOR_BD9571MWV=m
-CONFIG_REGULATOR_BD957XMUF=m
-CONFIG_REGULATOR_DA9052=m
-CONFIG_REGULATOR_DA9062=m
-CONFIG_REGULATOR_DA9210=m
-CONFIG_REGULATOR_DA9211=m
-CONFIG_REGULATOR_DA9121=m
-CONFIG_REGULATOR_FAN53555=m
-CONFIG_REGULATOR_GPIO=m
-CONFIG_REGULATOR_ISL9305=m
-CONFIG_REGULATOR_ISL6271A=m
-CONFIG_REGULATOR_LM363X=m
-CONFIG_REGULATOR_LP3971=m
-CONFIG_REGULATOR_LP3972=m
-CONFIG_REGULATOR_LP872X=m
-CONFIG_REGULATOR_LP8755=m
-CONFIG_REGULATOR_LTC3589=m
-CONFIG_REGULATOR_LTC3676=m
-CONFIG_REGULATOR_MAX14577=m
-CONFIG_REGULATOR_MAX1586=m
-CONFIG_REGULATOR_MAX8649=m
-CONFIG_REGULATOR_MAX8660=m
-CONFIG_REGULATOR_MAX8893=m
-CONFIG_REGULATOR_MAX8907=m
-CONFIG_REGULATOR_MAX8952=m
-CONFIG_REGULATOR_MAX77693=m
-CONFIG_REGULATOR_MAX77826=m
-CONFIG_REGULATOR_MC13XXX_CORE=m
-CONFIG_REGULATOR_MC13783=m
-CONFIG_REGULATOR_MC13892=m
-CONFIG_REGULATOR_MP8859=m
-CONFIG_REGULATOR_MT6311=m
-CONFIG_REGULATOR_MT6315=m
-CONFIG_REGULATOR_MT6370=m
-CONFIG_REGULATOR_MT6323=m
-CONFIG_REGULATOR_MT6331=m
-CONFIG_REGULATOR_MT6332=m
-CONFIG_REGULATOR_MT6358=m
-CONFIG_REGULATOR_MT6359=m
-CONFIG_REGULATOR_MT6360=m
-CONFIG_REGULATOR_MT6370=m
-CONFIG_REGULATOR_MT6397=m
-CONFIG_REGULATOR_PCA9450=m
-CONFIG_REGULATOR_PF8X00=m
-CONFIG_REGULATOR_PCAP=m
-CONFIG_REGULATOR_PCF50633=m
-CONFIG_REGULATOR_PFUZE100=m
-CONFIG_REGULATOR_PV88060=m
-CONFIG_REGULATOR_PV88080=m
-CONFIG_REGULATOR_PV88090=m
-CONFIG_REGULATOR_PWM=m
-CONFIG_REGULATOR_QCOM_SPMI=m
-CONFIG_REGULATOR_QCOM_USB_VBUS=m
-CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
-CONFIG_REGULATOR_RT4801=m
-CONFIG_REGULATOR_RT4831=m
-CONFIG_REGULATOR_RT5120=m
-CONFIG_REGULATOR_RT5190A=m
-CONFIG_REGULATOR_RT6160=m
-CONFIG_REGULATOR_RT6245=m
-CONFIG_REGULATOR_RT5033=m
-CONFIG_REGULATOR_RT5120=m
-CONFIG_REGULATOR_RT5190A=m
-CONFIG_REGULATOR_RT6245=m
-CONFIG_REGULATOR_RT6160=m
-CONFIG_REGULATOR_RTMV20=m
-CONFIG_REGULATOR_SKY81452=m
-CONFIG_REGULATOR_SLG51000=m
-CONFIG_REGULATOR_SY7636A=m
-CONFIG_REGULATOR_TPS51632=m
-CONFIG_REGULATOR_TPS6105X=m
-CONFIG_REGULATOR_TPS62360=m
-CONFIG_REGULATOR_TPS6286X=m
-CONFIG_REGULATOR_TPS65023=m
-CONFIG_REGULATOR_TPS6507X=m
-CONFIG_REGULATOR_TPS65086=m
-CONFIG_REGULATOR_TPS65132=m
-CONFIG_REGULATOR_TPS6524X=m
-CONFIG_REGULATOR_TPS65912=m
-CONFIG_REGULATOR_TPS68470=m
-CONFIG_REGULATOR_WM831X=m
-CONFIG_REGULATOR_WM8994=m
-CONFIG_REGULATOR_QCOM_LABIBB=m
-CONFIG_RC_CORE=m
-CONFIG_RC_MAP=m
-CONFIG_LIRC=y
-CONFIG_RC_DECODERS=y
-CONFIG_IR_NEC_DECODER=m
-CONFIG_IR_RC5_DECODER=m
-CONFIG_IR_RC6_DECODER=m
-CONFIG_IR_JVC_DECODER=m
-CONFIG_IR_SONY_DECODER=m
-CONFIG_IR_SANYO_DECODER=m
-CONFIG_IR_SHARP_DECODER=m
-CONFIG_IR_MCE_KBD_DECODER=m
-CONFIG_IR_XMP_DECODER=m
-CONFIG_IR_IMON_DECODER=m
-CONFIG_IR_RCMM_DECODER=m
-CONFIG_RC_DEVICES=y
-CONFIG_RC_ATI_REMOTE=m
-CONFIG_IR_ENE=m
-CONFIG_IR_IMON=m
-CONFIG_IR_IMON_RAW=m
-CONFIG_IR_MCEUSB=m
-CONFIG_IR_ITE_CIR=m
-CONFIG_IR_FINTEK=m
-CONFIG_IR_NUVOTON=m
-CONFIG_IR_REDRAT3=m
-CONFIG_IR_STREAMZAP=m
-CONFIG_IR_WINBOND_CIR=m
-CONFIG_IR_IGORPLUGUSB=m
-CONFIG_IR_IGUANA=m
-CONFIG_IR_TTUSBIR=m
-CONFIG_RC_LOOPBACK=m
-CONFIG_IR_SERIAL=m
-CONFIG_IR_SERIAL_TRANSMITTER=y
-CONFIG_IR_SIR=m
-CONFIG_RC_XBOX_DVD=m
-CONFIG_IR_TOY=m
-CONFIG_CEC_CORE=m
-CONFIG_CEC_NOTIFIER=y
-CONFIG_MEDIA_CEC_RC=y
-# CONFIG_CEC_PIN_ERROR_INJ is not set
-CONFIG_MEDIA_CEC_SUPPORT=y
-CONFIG_CEC_CH7322=m
-CONFIG_CEC_CROS_EC=m
-CONFIG_CEC_GPIO=m
-CONFIG_CEC_SECO=m
-CONFIG_CEC_SECO_RC=y
-CONFIG_USB_PULSE8_CEC=m
-CONFIG_USB_RAINSHADOW_CEC=m
-CONFIG_MEDIA_SUPPORT=m
-CONFIG_MEDIA_SUPPORT_FILTER=y
-CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
-
-#
-# Media device types
-#
-CONFIG_MEDIA_PLATFORM_DRIVERS=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_SDR_SUPPORT=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-# CONFIG_MEDIA_TEST_SUPPORT is not set
-# end of Media device types
-
-CONFIG_VIDEO_DEV=m
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_DVB_CORE=m
-
-#
-# Video4Linux options
-#
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L2_I2C=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_TUNER=m
-CONFIG_V4L2_MEM2MEM_DEV=m
-CONFIG_V4L2_FLASH_LED_CLASS=m
-CONFIG_V4L2_FWNODE=m
-CONFIG_VIDEOBUF_GEN=m
-CONFIG_VIDEOBUF_DMA_SG=m
-CONFIG_VIDEOBUF_VMALLOC=m
-# end of Video4Linux options
-
-#
-# Media controller options
-#
-CONFIG_MEDIA_CONTROLLER_DVB=y
-# end of Media controller options
-
-#
-# Digital TV options
-#
-# CONFIG_DVB_MMAP is not set
-CONFIG_DVB_NET=y
-CONFIG_DVB_MAX_ADAPTERS=8
-CONFIG_DVB_DYNAMIC_MINORS=y
-# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
-# CONFIG_DVB_ULE_DEBUG is not set
-# end of Digital TV options
-
-#
-# Media drivers
-#
-
-#
-# Drivers filtered as selected at 'Filter media drivers'
-#
-CONFIG_TTPCI_EEPROM=m
-CONFIG_MEDIA_USB_SUPPORT=y
-
-#
-# Webcam devices
-#
-CONFIG_USB_VIDEO_CLASS=m
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-CONFIG_USB_M5602=m
-CONFIG_USB_STV06XX=m
-CONFIG_USB_GL860=m
-CONFIG_USB_GSPCA_BENQ=m
-CONFIG_USB_GSPCA_CONEX=m
-CONFIG_USB_GSPCA_CPIA1=m
-CONFIG_USB_GSPCA_DTCS033=m
-CONFIG_USB_GSPCA_ETOMS=m
-CONFIG_USB_GSPCA_FINEPIX=m
-CONFIG_USB_GSPCA_JEILINJ=m
-CONFIG_USB_GSPCA_JL2005BCD=m
-CONFIG_USB_GSPCA_KINECT=m
-CONFIG_USB_GSPCA_KONICA=m
-CONFIG_USB_GSPCA_MARS=m
-CONFIG_USB_GSPCA_MR97310A=m
-CONFIG_USB_GSPCA_NW80X=m
-CONFIG_USB_GSPCA_OV519=m
-CONFIG_USB_GSPCA_OV534=m
-CONFIG_USB_GSPCA_OV534_9=m
-CONFIG_USB_GSPCA_PAC207=m
-CONFIG_USB_GSPCA_PAC7302=m
-CONFIG_USB_GSPCA_PAC7311=m
-CONFIG_USB_GSPCA_SE401=m
-CONFIG_USB_GSPCA_SN9C2028=m
-CONFIG_USB_GSPCA_SN9C20X=m
-CONFIG_USB_GSPCA_SONIXB=m
-CONFIG_USB_GSPCA_SONIXJ=m
-CONFIG_USB_GSPCA_SPCA500=m
-CONFIG_USB_GSPCA_SPCA501=m
-CONFIG_USB_GSPCA_SPCA505=m
-CONFIG_USB_GSPCA_SPCA506=m
-CONFIG_USB_GSPCA_SPCA508=m
-CONFIG_USB_GSPCA_SPCA561=m
-CONFIG_USB_GSPCA_SPCA1528=m
-CONFIG_USB_GSPCA_SQ905=m
-CONFIG_USB_GSPCA_SQ905C=m
-CONFIG_USB_GSPCA_SQ930X=m
-CONFIG_USB_GSPCA_STK014=m
-CONFIG_USB_GSPCA_STK1135=m
-CONFIG_USB_GSPCA_STV0680=m
-CONFIG_USB_GSPCA_SUNPLUS=m
-CONFIG_USB_GSPCA_T613=m
-CONFIG_USB_GSPCA_TOPRO=m
-CONFIG_USB_GSPCA_TOUPTEK=m
-CONFIG_USB_GSPCA_TV8532=m
-CONFIG_USB_GSPCA_VC032X=m
-CONFIG_USB_GSPCA_VICAM=m
-CONFIG_USB_GSPCA_XIRLINK_CIT=m
-CONFIG_USB_GSPCA_ZC3XX=m
-CONFIG_USB_PWC=m
-# CONFIG_USB_PWC_DEBUG is not set
-CONFIG_USB_PWC_INPUT_EVDEV=y
-CONFIG_VIDEO_CPIA2=m
-CONFIG_USB_ZR364XX=m
-CONFIG_USB_STKWEBCAM=m
-CONFIG_USB_S2255=m
-CONFIG_VIDEO_USBTV=m
-
-#
-# Analog TV USB devices
-#
-CONFIG_VIDEO_PVRUSB2=m
-CONFIG_VIDEO_PVRUSB2_SYSFS=y
-CONFIG_VIDEO_PVRUSB2_DVB=y
-# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
-CONFIG_VIDEO_HDPVR=m
-CONFIG_VIDEO_STK1160_COMMON=m
-CONFIG_VIDEO_STK1160=m
-CONFIG_VIDEO_GO7007=m
-CONFIG_VIDEO_GO7007_USB=m
-CONFIG_VIDEO_GO7007_LOADER=m
-CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
-
-#
-# Analog/digital TV USB devices
-#
-CONFIG_VIDEO_AU0828=m
-CONFIG_VIDEO_AU0828_V4L2=y
-CONFIG_VIDEO_AU0828_RC=y
-CONFIG_VIDEO_CX231XX=m
-CONFIG_VIDEO_CX231XX_RC=y
-CONFIG_VIDEO_CX231XX_ALSA=m
-CONFIG_VIDEO_CX231XX_DVB=m
-CONFIG_VIDEO_TM6000=m
-CONFIG_VIDEO_TM6000_ALSA=m
-CONFIG_VIDEO_TM6000_DVB=m
-
-#
-# Digital TV USB devices
-#
-CONFIG_DVB_USB=m
-# CONFIG_DVB_USB_DEBUG is not set
-CONFIG_DVB_USB_DIB3000MC=m
-CONFIG_DVB_USB_A800=m
-CONFIG_DVB_USB_DIBUSB_MB=m
-CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
-CONFIG_DVB_USB_DIBUSB_MC=m
-CONFIG_DVB_USB_DIB0700=m
-CONFIG_DVB_USB_UMT_010=m
-CONFIG_DVB_USB_CXUSB=m
-CONFIG_DVB_USB_CXUSB_ANALOG=y
-CONFIG_DVB_USB_M920X=m
-CONFIG_DVB_USB_DIGITV=m
-CONFIG_DVB_USB_VP7045=m
-CONFIG_DVB_USB_VP702X=m
-CONFIG_DVB_USB_GP8PSK=m
-CONFIG_DVB_USB_NOVA_T_USB2=m
-CONFIG_DVB_USB_TTUSB2=m
-CONFIG_DVB_USB_DTT200U=m
-CONFIG_DVB_USB_OPERA1=m
-CONFIG_DVB_USB_AF9005=m
-CONFIG_DVB_USB_AF9005_REMOTE=m
-CONFIG_DVB_USB_PCTV452E=m
-CONFIG_DVB_USB_DW2102=m
-CONFIG_DVB_USB_CINERGY_T2=m
-CONFIG_DVB_USB_DTV5100=m
-CONFIG_DVB_USB_AZ6027=m
-CONFIG_DVB_USB_TECHNISAT_USB2=m
-CONFIG_DVB_USB_V2=m
-CONFIG_DVB_USB_AF9015=m
-CONFIG_DVB_USB_AF9035=m
-CONFIG_DVB_USB_ANYSEE=m
-CONFIG_DVB_USB_AU6610=m
-CONFIG_DVB_USB_AZ6007=m
-CONFIG_DVB_USB_CE6230=m
-CONFIG_DVB_USB_EC168=m
-CONFIG_DVB_USB_GL861=m
-CONFIG_DVB_USB_LME2510=m
-CONFIG_DVB_USB_MXL111SF=m
-CONFIG_DVB_USB_RTL28XXU=m
-CONFIG_DVB_USB_DVBSKY=m
-CONFIG_DVB_USB_ZD1301=m
-CONFIG_DVB_TTUSB_BUDGET=m
-CONFIG_DVB_TTUSB_DEC=m
-CONFIG_SMS_USB_DRV=m
-CONFIG_DVB_B2C2_FLEXCOP_USB=m
-# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
-CONFIG_DVB_AS102=m
-
-#
-# Webcam, TV (analog/digital) USB devices
-#
-CONFIG_VIDEO_EM28XX=m
-CONFIG_VIDEO_EM28XX_V4L2=m
-CONFIG_VIDEO_EM28XX_ALSA=m
-CONFIG_VIDEO_EM28XX_DVB=m
-CONFIG_VIDEO_EM28XX_RC=m
-
-#
-# Software defined radio USB devices
-#
-CONFIG_USB_AIRSPY=m
-CONFIG_USB_HACKRF=m
-CONFIG_USB_MSI2500=m
-CONFIG_MEDIA_PCI_SUPPORT=y
-
-#
-# Media capture support
-#
-CONFIG_VIDEO_MEYE=m
-CONFIG_VIDEO_SOLO6X10=m
-CONFIG_VIDEO_TW5864=m
-CONFIG_VIDEO_TW68=m
-CONFIG_VIDEO_TW686X=m
-
-#
-# Media capture/analog TV support
-#
-CONFIG_VIDEO_IVTV=m
-# CONFIG_VIDEO_IVTV_DEPRECATED_IOCTLS is not set
-CONFIG_VIDEO_IVTV_ALSA=m
-CONFIG_VIDEO_FB_IVTV=m
-# CONFIG_VIDEO_FB_IVTV_FORCE_PAT is not set
-CONFIG_VIDEO_HEXIUM_GEMINI=m
-CONFIG_VIDEO_HEXIUM_ORION=m
-CONFIG_VIDEO_MXB=m
-CONFIG_VIDEO_DT3155=m
-
-#
-# Media capture/analog/hybrid TV support
-#
-CONFIG_VIDEO_CX18=m
-CONFIG_VIDEO_CX18_ALSA=m
-CONFIG_VIDEO_CX23885=m
-CONFIG_MEDIA_ALTERA_CI=m
-CONFIG_VIDEO_CX25821=m
-CONFIG_VIDEO_CX25821_ALSA=m
-CONFIG_VIDEO_CX88=m
-CONFIG_VIDEO_CX88_ALSA=m
-CONFIG_VIDEO_CX88_BLACKBIRD=m
-CONFIG_VIDEO_CX88_DVB=m
-CONFIG_VIDEO_CX88_ENABLE_VP3054=y
-CONFIG_VIDEO_CX88_VP3054=m
-CONFIG_VIDEO_CX88_MPEG=m
-CONFIG_VIDEO_BT848=m
-CONFIG_DVB_BT8XX=m
-CONFIG_VIDEO_SAA7134=m
-CONFIG_VIDEO_SAA7134_ALSA=m
-CONFIG_VIDEO_SAA7134_RC=y
-CONFIG_VIDEO_SAA7134_DVB=m
-CONFIG_VIDEO_SAA7134_GO7007=m
-CONFIG_VIDEO_SAA7164=m
-# CONFIG_VIDEO_COBALT is not set
-
-#
-# Media digital TV PCI Adapters
-#
-CONFIG_DVB_AV7110_IR=y
-CONFIG_DVB_AV7110=m
-CONFIG_DVB_AV7110_OSD=y
-CONFIG_DVB_BUDGET_CORE=m
-CONFIG_DVB_BUDGET=m
-CONFIG_DVB_BUDGET_CI=m
-CONFIG_DVB_BUDGET_AV=m
-CONFIG_DVB_BUDGET_PATCH=m
-CONFIG_DVB_B2C2_FLEXCOP_PCI=m
-# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
-CONFIG_DVB_PLUTO2=m
-CONFIG_DVB_DM1105=m
-CONFIG_DVB_PT1=m
-CONFIG_DVB_PT3=m
-CONFIG_MANTIS_CORE=m
-CONFIG_DVB_MANTIS=m
-CONFIG_DVB_HOPPER=m
-CONFIG_DVB_NGENE=m
-CONFIG_DVB_DDBRIDGE=m
-# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set
-CONFIG_DVB_SMIPCIE=m
-CONFIG_DVB_NETUP_UNIDVB=m
-CONFIG_VIDEO_IPU3_CIO2=m
-CONFIG_CIO2_BRIDGE=y
-CONFIG_RADIO_ADAPTERS=y
-CONFIG_RADIO_TEA575X=m
-CONFIG_RADIO_SI470X=m
-CONFIG_USB_SI470X=m
-CONFIG_I2C_SI470X=m
-CONFIG_RADIO_SI4713=m
-CONFIG_USB_SI4713=m
-CONFIG_PLATFORM_SI4713=m
-CONFIG_I2C_SI4713=m
-CONFIG_RADIO_SI476X=m
-CONFIG_USB_MR800=m
-CONFIG_USB_DSBR=m
-CONFIG_RADIO_MAXIRADIO=m
-CONFIG_RADIO_SHARK=m
-CONFIG_RADIO_SHARK2=m
-CONFIG_USB_KEENE=m
-CONFIG_USB_RAREMONO=m
-CONFIG_USB_MA901=m
-CONFIG_RADIO_TEA5764=m
-CONFIG_RADIO_SAA7706H=m
-CONFIG_RADIO_TEF6862=m
-CONFIG_RADIO_WL1273=m
-CONFIG_RADIO_WL128X=m
-# CONFIG_V4L_RADIO_ISA_DRIVERS is not set
-CONFIG_MEDIA_COMMON_OPTIONS=y
-
-#
-# common driver options
-#
-CONFIG_VIDEO_CX2341X=m
-CONFIG_VIDEO_TVEEPROM=m
-CONFIG_CYPRESS_FIRMWARE=m
-CONFIG_VIDEOBUF2_CORE=m
-CONFIG_VIDEOBUF2_V4L2=m
-CONFIG_VIDEOBUF2_MEMOPS=m
-CONFIG_VIDEOBUF2_DMA_CONTIG=m
-CONFIG_VIDEOBUF2_VMALLOC=m
-CONFIG_VIDEOBUF2_DMA_SG=m
-CONFIG_VIDEOBUF2_DVB=m
-CONFIG_DVB_B2C2_FLEXCOP=m
-CONFIG_VIDEO_SAA7146=m
-CONFIG_VIDEO_SAA7146_VV=m
-CONFIG_SMS_SIANO_MDTV=m
-CONFIG_SMS_SIANO_RC=y
-# CONFIG_SMS_SIANO_DEBUGFS is not set
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_CAFE_CCIC=m
-CONFIG_VIDEO_VIA_CAMERA=m
-CONFIG_VIDEO_CADENCE=y
-CONFIG_VIDEO_CADENCE_CSI2RX=m
-CONFIG_VIDEO_CADENCE_CSI2TX=m
-CONFIG_VIDEO_ASPEED=m
-CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_VIDEO_ALLEGRO_DVT=m
-CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
-CONFIG_VIDEO_MESON_GE2D=m
-CONFIG_VIDEO_AMPHION_VPU=m
-CONFIG_DVB_PLATFORM_DRIVERS=y
-CONFIG_SDR_PLATFORM_DRIVERS=y
-
-#
-# MMC/SDIO DVB adapters
-#
-CONFIG_SMS_SDIO_DRV=m
-
-#
-# FireWire (IEEE 1394) Adapters
-#
-CONFIG_DVB_FIREDTV=m
-CONFIG_DVB_FIREDTV_INPUT=y
-# end of Media drivers
-
-#
-# Media ancillary drivers
-#
-CONFIG_MEDIA_ATTACH=y
-
-#
-# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
-#
-CONFIG_VIDEO_IR_I2C=m
-
-#
-# Audio decoders, processors and mixers
-#
-CONFIG_VIDEO_TVAUDIO=m
-CONFIG_VIDEO_TDA7432=m
-CONFIG_VIDEO_TDA9840=m
-# CONFIG_VIDEO_TDA1997X is not set
-CONFIG_VIDEO_TEA6415C=m
-CONFIG_VIDEO_TEA6420=m
-CONFIG_VIDEO_MSP3400=m
-CONFIG_VIDEO_CS3308=m
-CONFIG_VIDEO_CS5345=m
-CONFIG_VIDEO_CS53L32A=m
-# CONFIG_VIDEO_TLV320AIC23B is not set
-CONFIG_VIDEO_UDA1342=m
-CONFIG_VIDEO_WM8775=m
-CONFIG_VIDEO_WM8739=m
-CONFIG_VIDEO_VP27SMPX=m
-CONFIG_VIDEO_SONY_BTF_MPX=m
-# end of Audio decoders, processors and mixers
-
-#
-# RDS decoders
-#
-CONFIG_VIDEO_SAA6588=m
-# end of RDS decoders
-
-#
-# Video decoders
-#
-# CONFIG_VIDEO_ADV7180 is not set
-# CONFIG_VIDEO_ADV7183 is not set
-# CONFIG_VIDEO_ADV7604 is not set
-# CONFIG_VIDEO_ADV7842 is not set
-CONFIG_VIDEO_BT819=m
-CONFIG_VIDEO_BT856=m
-CONFIG_VIDEO_BT866=m
-CONFIG_VIDEO_ISL7998X=m
-CONFIG_VIDEO_KS0127=m
-# CONFIG_VIDEO_ML86V7667 is not set
-CONFIG_VIDEO_SAA7110=m
-CONFIG_VIDEO_SAA711X=m
-# CONFIG_VIDEO_TC358743 is not set
-# CONFIG_VIDEO_TVP514X is not set
-CONFIG_VIDEO_TVP5150=m
-# CONFIG_VIDEO_TVP7002 is not set
-CONFIG_VIDEO_TW2804=m
-CONFIG_VIDEO_TW9903=m
-CONFIG_VIDEO_TW9906=m
-# CONFIG_VIDEO_TW9910 is not set
-CONFIG_VIDEO_VPX3220=m
-
-#
-# Video and audio decoders
-#
-CONFIG_VIDEO_SAA717X=m
-CONFIG_VIDEO_CX25840=m
-# end of Video decoders
-
-#
-# Video encoders
-#
-CONFIG_VIDEO_SAA7127=m
-CONFIG_VIDEO_SAA7185=m
-CONFIG_VIDEO_ADV7170=m
-CONFIG_VIDEO_ADV7175=m
-# CONFIG_VIDEO_ADV7343 is not set
-# CONFIG_VIDEO_ADV7393 is not set
-# CONFIG_VIDEO_ADV7511 is not set
-# CONFIG_VIDEO_AD9389B is not set
-# CONFIG_VIDEO_AK881X is not set
-# CONFIG_VIDEO_THS8200 is not set
-# end of Video encoders
-
-#
-# Video improvement chips
-#
-CONFIG_VIDEO_UPD64031A=m
-CONFIG_VIDEO_UPD64083=m
-# end of Video improvement chips
-
-#
-# Audio/Video compression chips
-#
-CONFIG_VIDEO_SAA6752HS=m
-# end of Audio/Video compression chips
-
-#
-# SDR tuner chips
-#
-# CONFIG_SDR_MAX2175 is not set
-# end of SDR tuner chips
-
-#
-# Miscellaneous helper chips
-#
-# CONFIG_VIDEO_THS7303 is not set
-CONFIG_VIDEO_M52790=m
-# CONFIG_VIDEO_I2C is not set
-# CONFIG_VIDEO_ST_MIPID02 is not set
-# end of Miscellaneous helper chips
-
-#
-# Camera sensor devices
-#
-CONFIG_VIDEO_APTINA_PLL=m
-CONFIG_VIDEO_SMIAPP_PLL=m
-CONFIG_VIDEO_HI556=m
-CONFIG_VIDEO_IMX208=m
-CONFIG_VIDEO_IMX214=m
-CONFIG_VIDEO_IMX219=m
-CONFIG_VIDEO_IMX258=m
-CONFIG_VIDEO_IMX274=m
-CONFIG_VIDEO_IMX290=m
-CONFIG_VIDEO_IMX319=m
-CONFIG_VIDEO_IMX334=m
-CONFIG_VIDEO_IMX355=m
-CONFIG_VIDEO_OV02A10=m
-CONFIG_VIDEO_OV08D10=m
-CONFIG_VIDEO_OV2640=m
-CONFIG_VIDEO_OV2659=m
-CONFIG_VIDEO_OV2680=m
-CONFIG_VIDEO_OV2685=m
-CONFIG_VIDEO_OV2740=m
-CONFIG_VIDEO_OV5647=m
-CONFIG_VIDEO_OV5648=m
-CONFIG_VIDEO_OV6650=m
-CONFIG_VIDEO_OV5670=m
-CONFIG_VIDEO_OV5675=m
-CONFIG_VIDEO_OV5695=m
-CONFIG_VIDEO_OV7251=m
-CONFIG_VIDEO_OV772X=m
-CONFIG_VIDEO_OV7640=m
-CONFIG_VIDEO_OV7670=m
-CONFIG_VIDEO_OV7740=m
-CONFIG_VIDEO_OV8856=m
-CONFIG_VIDEO_OV8865=m
-CONFIG_VIDEO_OV9640=m
-CONFIG_VIDEO_OV9650=m
-CONFIG_VIDEO_OV9734=m
-CONFIG_VIDEO_OV13858=m
-CONFIG_VIDEO_VS6624=m
-CONFIG_VIDEO_MT9M001=m
-CONFIG_VIDEO_MT9M032=m
-CONFIG_VIDEO_MT9M111=m
-CONFIG_VIDEO_MT9P031=m
-CONFIG_VIDEO_MT9T001=m
-CONFIG_VIDEO_MT9T112=m
-CONFIG_VIDEO_MT9V011=m
-CONFIG_VIDEO_MT9V032=m
-CONFIG_VIDEO_MT9V111=m
-CONFIG_VIDEO_SR030PC30=m
-CONFIG_VIDEO_NOON010PC30=m
-CONFIG_VIDEO_OG01A1B=m
-CONFIG_VIDEO_M5MOLS=m
-CONFIG_VIDEO_RDACM20=m
-CONFIG_VIDEO_RDACM21=m
-CONFIG_VIDEO_RJ54N1=m
-CONFIG_VIDEO_S5K6AA=m
-CONFIG_VIDEO_S5K6A3=m
-CONFIG_VIDEO_S5K4ECGX=m
-CONFIG_VIDEO_S5K5BAF=m
-CONFIG_VIDEO_CCS=m
-CONFIG_VIDEO_SMIAPP=m
-CONFIG_VIDEO_ET8EK8=m
-CONFIG_VIDEO_S5C73M3=m
-# end of Camera sensor devices
-
-#
-# Lens drivers
-#
-CONFIG_VIDEO_AD5820=m
-CONFIG_VIDEO_AK7375=m
-CONFIG_VIDEO_DW9714=m
-CONFIG_VIDEO_DW9768=m
-CONFIG_VIDEO_DW9807_VCM=m
-# end of Lens drivers
-
-#
-# Flash devices
-#
-CONFIG_VIDEO_ADP1653=m
-CONFIG_VIDEO_LM3560=m
-CONFIG_VIDEO_LM3646=m
-# end of Flash devices
-
-#
-# SPI helper chips
-#
-# CONFIG_VIDEO_GS1662 is not set
-# end of SPI helper chips
-
-#
-# Media SPI Adapters
-#
-CONFIG_CXD2880_SPI_DRV=m
-# end of Media SPI Adapters
-
-CONFIG_MEDIA_TUNER=m
-
-#
-# Customize TV tuners
-#
-CONFIG_MEDIA_TUNER_SIMPLE=m
-CONFIG_MEDIA_TUNER_TDA18250=m
-CONFIG_MEDIA_TUNER_TDA8290=m
-CONFIG_MEDIA_TUNER_TDA827X=m
-CONFIG_MEDIA_TUNER_TDA18271=m
-CONFIG_MEDIA_TUNER_TDA9887=m
-CONFIG_MEDIA_TUNER_TEA5761=m
-CONFIG_MEDIA_TUNER_TEA5767=m
-CONFIG_MEDIA_TUNER_MSI001=m
-CONFIG_MEDIA_TUNER_MT20XX=m
-CONFIG_MEDIA_TUNER_MT2060=m
-CONFIG_MEDIA_TUNER_MT2063=m
-CONFIG_MEDIA_TUNER_MT2266=m
-CONFIG_MEDIA_TUNER_MT2131=m
-CONFIG_MEDIA_TUNER_QT1010=m
-CONFIG_MEDIA_TUNER_XC2028=m
-CONFIG_MEDIA_TUNER_XC5000=m
-CONFIG_MEDIA_TUNER_XC4000=m
-CONFIG_MEDIA_TUNER_MXL5005S=m
-CONFIG_MEDIA_TUNER_MXL5007T=m
-CONFIG_MEDIA_TUNER_MC44S803=m
-CONFIG_MEDIA_TUNER_MAX2165=m
-CONFIG_MEDIA_TUNER_TDA18218=m
-CONFIG_MEDIA_TUNER_FC0011=m
-CONFIG_MEDIA_TUNER_FC0012=m
-CONFIG_MEDIA_TUNER_FC0013=m
-CONFIG_MEDIA_TUNER_TDA18212=m
-CONFIG_MEDIA_TUNER_E4000=m
-CONFIG_MEDIA_TUNER_FC2580=m
-CONFIG_MEDIA_TUNER_M88RS6000T=m
-CONFIG_MEDIA_TUNER_TUA9001=m
-CONFIG_MEDIA_TUNER_SI2157=m
-CONFIG_MEDIA_TUNER_IT913X=m
-CONFIG_MEDIA_TUNER_R820T=m
-CONFIG_MEDIA_TUNER_MXL301RF=m
-CONFIG_MEDIA_TUNER_QM1D1C0042=m
-CONFIG_MEDIA_TUNER_QM1D1B0004=m
-CONFIG_MEDIA_TUNER_AV201X=m
-CONFIG_MEDIA_TUNER_STV6120=m
-# end of Customize TV tuners
-
-#
-# Customise DVB Frontends
-#
-
-#
-# Multistandard (satellite) frontends
-#
-CONFIG_DVB_STB0899=m
-CONFIG_DVB_STB6100=m
-CONFIG_DVB_STV090x=m
-CONFIG_DVB_STV0910=m
-CONFIG_DVB_STV6110x=m
-CONFIG_DVB_STV6111=m
-CONFIG_DVB_MXL5XX=m
-CONFIG_DVB_M88DS3103=m
-
-#
-# Multistandard (cable + terrestrial) frontends
-#
-CONFIG_DVB_DRXK=m
-CONFIG_DVB_TDA18271C2DD=m
-CONFIG_DVB_SI2165=m
-CONFIG_DVB_MN88472=m
-CONFIG_DVB_MN88473=m
-
-#
-# DVB-S (satellite) frontends
-#
-CONFIG_DVB_CX24110=m
-CONFIG_DVB_CX24123=m
-CONFIG_DVB_MT312=m
-CONFIG_DVB_ZL10036=m
-CONFIG_DVB_ZL10039=m
-CONFIG_DVB_S5H1420=m
-CONFIG_DVB_STV0288=m
-CONFIG_DVB_STB6000=m
-CONFIG_DVB_STV0299=m
-CONFIG_DVB_STV6110=m
-CONFIG_DVB_STV0900=m
-CONFIG_DVB_TDA8083=m
-CONFIG_DVB_TDA10086=m
-CONFIG_DVB_TDA8261=m
-CONFIG_DVB_VES1X93=m
-CONFIG_DVB_TUNER_ITD1000=m
-CONFIG_DVB_TUNER_CX24113=m
-CONFIG_DVB_TDA826X=m
-CONFIG_DVB_TUA6100=m
-CONFIG_DVB_CX24116=m
-CONFIG_DVB_CX24117=m
-CONFIG_DVB_CX24120=m
-CONFIG_DVB_SI21XX=m
-CONFIG_DVB_TS2020=m
-CONFIG_DVB_DS3000=m
-CONFIG_DVB_MB86A16=m
-CONFIG_DVB_TDA10071=m
-
-#
-# DVB-T (terrestrial) frontends
-#
-CONFIG_DVB_SP8870=m
-CONFIG_DVB_SP887X=m
-CONFIG_DVB_CX22700=m
-CONFIG_DVB_CX22702=m
-# CONFIG_DVB_S5H1432 is not set
-CONFIG_DVB_DRXD=m
-CONFIG_DVB_L64781=m
-CONFIG_DVB_TDA1004X=m
-CONFIG_DVB_NXT6000=m
-CONFIG_DVB_MT352=m
-CONFIG_DVB_ZL10353=m
-CONFIG_DVB_DIB3000MB=m
-CONFIG_DVB_DIB3000MC=m
-CONFIG_DVB_DIB7000M=m
-CONFIG_DVB_DIB7000P=m
-# CONFIG_DVB_DIB9000 is not set
-CONFIG_DVB_TDA10048=m
-CONFIG_DVB_AF9013=m
-CONFIG_DVB_EC100=m
-CONFIG_DVB_STV0367=m
-CONFIG_DVB_CXD2820R=m
-CONFIG_DVB_CXD2841ER=m
-CONFIG_DVB_RTL2830=m
-CONFIG_DVB_RTL2832=m
-CONFIG_DVB_RTL2832_SDR=m
-CONFIG_DVB_SI2168=m
-CONFIG_DVB_AS102_FE=m
-CONFIG_DVB_ZD1301_DEMOD=m
-CONFIG_DVB_GP8PSK_FE=m
-# CONFIG_DVB_CXD2880 is not set
-
-#
-# DVB-C (cable) frontends
-#
-CONFIG_DVB_VES1820=m
-CONFIG_DVB_TDA10021=m
-CONFIG_DVB_TDA10023=m
-CONFIG_DVB_STV0297=m
-
-#
-# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
-#
-CONFIG_DVB_NXT200X=m
-CONFIG_DVB_OR51211=m
-CONFIG_DVB_OR51132=m
-CONFIG_DVB_BCM3510=m
-CONFIG_DVB_LGDT330X=m
-CONFIG_DVB_LGDT3305=m
-CONFIG_DVB_LGDT3306A=m
-CONFIG_DVB_LG2160=m
-CONFIG_DVB_S5H1409=m
-CONFIG_DVB_AU8522=m
-CONFIG_DVB_AU8522_DTV=m
-CONFIG_DVB_AU8522_V4L=m
-CONFIG_DVB_S5H1411=m
-
-#
-# ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_S921=m
-CONFIG_DVB_DIB8000=m
-CONFIG_DVB_MB86A20S=m
-
-#
-# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_TC90522=m
-# CONFIG_DVB_MN88443X is not set
-
-#
-# Digital terrestrial only tuners/PLL
-#
-CONFIG_DVB_PLL=m
-CONFIG_DVB_TUNER_DIB0070=m
-CONFIG_DVB_TUNER_DIB0090=m
-
-#
-# SEC control devices for DVB-S
-#
-CONFIG_DVB_DRX39XYJ=m
-CONFIG_DVB_LNBH25=m
-# CONFIG_DVB_LNBH29 is not set
-CONFIG_DVB_LNBP21=m
-CONFIG_DVB_LNBP22=m
-CONFIG_DVB_ISL6405=m
-CONFIG_DVB_ISL6421=m
-CONFIG_DVB_ISL6422=m
-CONFIG_DVB_ISL6423=m
-CONFIG_DVB_A8293=m
-# CONFIG_DVB_LGS8GL5 is not set
-CONFIG_DVB_LGS8GXX=m
-CONFIG_DVB_ATBM8830=m
-CONFIG_DVB_TDA665x=m
-CONFIG_DVB_IX2505V=m
-CONFIG_DVB_M88RS2000=m
-CONFIG_DVB_AF9033=m
-CONFIG_DVB_TAS2101=m
-CONFIG_DVB_HORUS3A=m
-CONFIG_DVB_ASCOT2E=m
-CONFIG_DVB_HELENE=m
-
-#
-# Common Interface (EN50221) controller drivers
-#
-CONFIG_DVB_CXD2099=m
-CONFIG_DVB_SP2=m
-# end of Customise DVB Frontends
-# end of Media ancillary drivers
-
-#
-# Graphics support
-#
-CONFIG_AGP=m
-# CONFIG_AGP_ALI is not set
-# CONFIG_AGP_ATI is not set
-# CONFIG_AGP_AMD is not set
-CONFIG_AGP_AMD64=m
-CONFIG_AGP_INTEL=m
-# CONFIG_AGP_NVIDIA is not set
-CONFIG_AGP_SIS=m
-# CONFIG_AGP_SWORKS is not set
-CONFIG_AGP_VIA=m
-# CONFIG_AGP_EFFICEON is not set
-CONFIG_INTEL_GTT=m
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-CONFIG_VGA_SWITCHEROO=y
-CONFIG_BOOTSPLASH=y
-CONFIG_DRM=m
-CONFIG_DRM_GUD=m
-CONFIG_DRM_SSD130X=m
-CONFIG_DRM_SSD130X_I2C=m
-CONFIG_DRM_SPRD=m
-CONFIG_DRM_HYPERV=m
-CONFIG_DRM_MIPI_DBI=m
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_DP_AUX_CHARDEV=y
-# CONFIG_DRM_DEBUG_MM is not set
-# CONFIG_DRM_DEBUG_SELFTEST is not set
-CONFIG_DRM_KMS_HELPER=m
-CONFIG_DRM_KMS_FB_HELPER=y
-# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
-# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
-# CONFIG_DRM_DP_CEC is not set
-CONFIG_DRM_TTM=m
-CONFIG_DRM_TTM_DMA_PAGE_POOL=y
-CONFIG_DRM_VRAM_HELPER=m
-CONFIG_DRM_TTM_HELPER=m
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-CONFIG_DRM_VM=y
-CONFIG_DRM_SCHED=m
-
-#
-# I2C encoder or helper chips
-#
-CONFIG_DRM_I2C_CH7006=m
-CONFIG_DRM_I2C_SIL164=m
-CONFIG_DRM_I2C_NXP_TDA998X=m
-CONFIG_DRM_I2C_NXP_TDA9950=m
-# end of I2C encoder or helper chips
-
-#
-# ARM devices
-#
-# end of ARM devices
-
-CONFIG_DRM_RADEON=m
-# CONFIG_DRM_RADEON_USERPTR is not set
-CONFIG_DRM_AMDGPU=m
-CONFIG_DRM_AMDGPU_SI=y
-CONFIG_DRM_AMDGPU_CIK=y
-# CONFIG_DRM_AMDGPU_USERPTR is not set
-# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set
-
-#
-# ACP (Audio CoProcessor) Configuration
-#
-CONFIG_DRM_AMD_ACP=y
-# end of ACP (Audio CoProcessor) Configuration
-
-#
-# Display Engine Configuration
-#
-CONFIG_DRM_AMD_DC=y
-CONFIG_DRM_AMD_DC_DCN=y
-CONFIG_DRM_AMD_DC_DCN3_0=y
-CONFIG_DRM_AMD_DC_HDCP=y
-CONFIG_DRM_AMD_DC_SI=y
-CONFIG_DRM_AMD_SECURE_DISPLAY=y
-CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
-# CONFIG_DEBUG_KERNEL_DC is not set
-# end of Display Engine Configuration
-
-CONFIG_DRM_NOUVEAU=m
-CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT=y
-CONFIG_NOUVEAU_DEBUG=5
-CONFIG_NOUVEAU_DEBUG_DEFAULT=3
-# CONFIG_NOUVEAU_DEBUG_MMU is not set
-# CONFIG_NOUVEAU_DEBUG_PUSH is not set
-CONFIG_DRM_NOUVEAU_BACKLIGHT=y
-CONFIG_DRM_I915=m
-CONFIG_DRM_I915_FORCE_PROBE=""
-CONFIG_DRM_I915_CAPTURE_ERROR=y
-CONFIG_DRM_I915_COMPRESS_ERROR=y
-CONFIG_DRM_I915_USERPTR=y
-CONFIG_DRM_I915_PXP=y
-
-#
-# drm/i915 Debugging
-#
-# CONFIG_DRM_I915_WERROR is not set
-# CONFIG_DRM_I915_DEBUG is not set
-# CONFIG_DRM_I915_DEBUG_MMIO is not set
-# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
-# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
-# CONFIG_DRM_I915_DEBUG_GUC is not set
-# CONFIG_DRM_I915_SELFTEST is not set
-# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
-# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
-# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set
-# end of drm/i915 Debugging
-
-#
-# drm/i915 Profile Guided Optimisation
-#
-CONFIG_DRM_I915_FENCE_TIMEOUT=10000
-CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
-CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
-CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
-CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
-CONFIG_DRM_I915_STOP_TIMEOUT=100
-CONFIG_DRM_I915_TIMESLICE_DURATION=1
-# end of drm/i915 Profile Guided Optimisation
-
-CONFIG_DRM_VGEM=m
-CONFIG_DRM_VKMS=m
-CONFIG_DRM_VMWGFX=m
-CONFIG_DRM_VMWGFX_FBCON=y
-CONFIG_DRM_VMWGFX_MKSSTATS=y
-CONFIG_DRM_GMA500=m
-CONFIG_DRM_PANEL_MIPI_DBI=m
-CONFIG_DRM_GMA600=y
-CONFIG_DRM_GMA3600=y
-CONFIG_DRM_UDL=m
-CONFIG_DRM_AST=m
-CONFIG_DRM_MGAG200=m
-CONFIG_DRM_QXL=m
-CONFIG_DRM_BOCHS=m
-CONFIG_DRM_VIRTIO_GPU=m
-CONFIG_DRM_PANEL=y
-
-#
-# Display Panels
-#
-CONFIG_DRM_PANEL_ABT_Y030XX067A=m
-CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
-# end of Display Panels
-
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_PANEL_BRIDGE=y
-
-#
-# Display Interface Bridges
-#
-CONFIG_DRM_ANALOGIX_ANX78XX=m
-CONFIG_DRM_ANALOGIX_ANX7625=m
-CONFIG_DRM_ANALOGIX_DP=m
-# end of Display Interface Bridges
-
-CONFIG_DRM_ETNAVIV=m
-CONFIG_DRM_ETNAVIV_THERMAL=y
-CONFIG_DRM_CIRRUS_QEMU=m
-CONFIG_DRM_GM12U320=m
-CONFIG_DRM_SIMPLEDRM=y
-CONFIG_TINYDRM_HX8357D=m
-CONFIG_TINYDRM_ILI9225=m
-CONFIG_TINYDRM_ILI9341=m
-CONFIG_TINYDRM_ILI9486=m
-CONFIG_TINYDRM_MI0283QT=m
-CONFIG_TINYDRM_REPAPER=m
-CONFIG_TINYDRM_ST7586=m
-CONFIG_TINYDRM_ST7735R=m
-CONFIG_DRM_VBOXVIDEO=m
-CONFIG_DRM_LEGACY=y
-CONFIG_DRM_TDFX=m
-CONFIG_DRM_R128=m
-# CONFIG_DRM_I810 is not set
-CONFIG_DRM_MGA=m
-CONFIG_DRM_SIS=m
-CONFIG_DRM_VIA=m
-CONFIG_DRM_SAVAGE=m
-CONFIG_DRM_EXPORT_FOR_TESTS=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_LIB_RANDOM=y
-
-#
-# Frame buffer Devices
-#
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_NOTIFY=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_DDC=m
-CONFIG_FB_BOOT_VESA_SUPPORT=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SYS_FILLRECT=m
-CONFIG_FB_SYS_COPYAREA=m
-CONFIG_FB_SYS_IMAGEBLIT=m
-CONFIG_FB_FOREIGN_ENDIAN=y
-CONFIG_FB_BOTH_ENDIAN=y
-# CONFIG_FB_BIG_ENDIAN is not set
-# CONFIG_FB_LITTLE_ENDIAN is not set
-CONFIG_FB_SYS_FOPS=m
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_HECUBA=m
-CONFIG_FB_SVGALIB=m
-CONFIG_FB_BACKLIGHT=m
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
-
-#
-# Frame buffer hardware drivers
-#
-CONFIG_FB_CIRRUS=m
-CONFIG_FB_PM2=m
-CONFIG_FB_PM2_FIFO_DISCONNECT=y
-CONFIG_FB_CYBER2000=m
-CONFIG_FB_CYBER2000_DDC=y
-CONFIG_FB_ARC=m
-CONFIG_FB_ASILIANT=y
-CONFIG_FB_IMSTT=y
-CONFIG_FB_VGA16=m
-CONFIG_FB_UVESA=m
-CONFIG_FB_VESA=y
-CONFIG_FB_EFI=y
-CONFIG_FB_N411=m
-# CONFIG_FB_HGA is not set
-CONFIG_FB_OPENCORES=m
-CONFIG_FB_S1D13XXX=m
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-CONFIG_FB_I740=m
-# CONFIG_FB_I810 is not set
-CONFIG_FB_LE80578=m
-CONFIG_FB_CARILLO_RANCH=m
-# CONFIG_FB_INTEL is not set
-CONFIG_FB_MATROX=m
-CONFIG_FB_MATROX_MILLENIUM=y
-CONFIG_FB_MATROX_MYSTIQUE=y
-CONFIG_FB_MATROX_G=y
-CONFIG_FB_MATROX_I2C=m
-CONFIG_FB_MATROX_MAVEN=m
-CONFIG_FB_RADEON=m
-CONFIG_FB_RADEON_I2C=y
-CONFIG_FB_RADEON_BACKLIGHT=y
-# CONFIG_FB_RADEON_DEBUG is not set
-CONFIG_FB_ATY128=m
-CONFIG_FB_ATY128_BACKLIGHT=y
-CONFIG_FB_ATY=m
-CONFIG_FB_ATY_CT=y
-CONFIG_FB_ATY_GENERIC_LCD=y
-CONFIG_FB_ATY_GX=y
-CONFIG_FB_ATY_BACKLIGHT=y
-CONFIG_FB_S3=m
-CONFIG_FB_S3_DDC=y
-CONFIG_FB_SAVAGE=m
-CONFIG_FB_SAVAGE_I2C=y
-CONFIG_FB_SAVAGE_ACCEL=y
-CONFIG_FB_SIS=m
-CONFIG_FB_SIS_300=y
-CONFIG_FB_SIS_315=y
-CONFIG_FB_VIA=m
-# CONFIG_FB_VIA_DIRECT_PROCFS is not set
-CONFIG_FB_VIA_X_COMPATIBILITY=y
-CONFIG_FB_NEOMAGIC=m
-CONFIG_FB_KYRO=m
-CONFIG_FB_3DFX=m
-CONFIG_FB_3DFX_ACCEL=y
-CONFIG_FB_3DFX_I2C=y
-CONFIG_FB_VOODOO1=m
-CONFIG_FB_VT8623=m
-CONFIG_FB_TRIDENT=m
-CONFIG_FB_ARK=m
-CONFIG_FB_PM3=m
-CONFIG_FB_CARMINE=m
-CONFIG_FB_CARMINE_DRAM_EVAL=y
-# CONFIG_CARMINE_DRAM_CUSTOM is not set
-# CONFIG_FB_GEODE is not set
-CONFIG_FB_SM501=m
-CONFIG_FB_SMSCUFX=m
-CONFIG_FB_UDL=m
-CONFIG_FB_IBM_GXT4500=m
-CONFIG_FB_VIRTUAL=m
-CONFIG_FB_METRONOME=m
-CONFIG_FB_MB862XX=m
-CONFIG_FB_MB862XX_PCI_GDC=y
-CONFIG_FB_MB862XX_I2C=y
-CONFIG_FB_HYPERV=m
-CONFIG_FB_SIMPLE=y
-CONFIG_FB_SSD1307=m
-CONFIG_FB_SM712=m
-# end of Frame buffer Devices
-
-#
-# Backlight & LCD device support
-#
-CONFIG_LCD_CLASS_DEVICE=m
-CONFIG_LCD_L4F00242T03=m
-CONFIG_LCD_LMS283GF05=m
-CONFIG_LCD_LTV350QV=m
-CONFIG_LCD_ILI922X=m
-CONFIG_LCD_ILI9320=m
-CONFIG_LCD_TDO24M=m
-CONFIG_LCD_VGG2432A4=m
-CONFIG_LCD_PLATFORM=m
-CONFIG_LCD_AMS369FG06=m
-CONFIG_LCD_LMS501KF03=m
-CONFIG_LCD_HX8357=m
-CONFIG_LCD_OTM3225A=m
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_KTD253=m
-CONFIG_BACKLIGHT_LM3533=m
-CONFIG_BACKLIGHT_CARILLO_RANCH=m
-CONFIG_BACKLIGHT_PWM=m
-CONFIG_BACKLIGHT_MT6370=m
-CONFIG_BACKLIGHT_DA9052=m
-CONFIG_BACKLIGHT_MT6370=m
-CONFIG_BACKLIGHT_APPLE=m
-CONFIG_BACKLIGHT_QCOM_WLED=m
-CONFIG_BACKLIGHT_RT4831=m
-CONFIG_BACKLIGHT_SAHARA=m
-CONFIG_BACKLIGHT_WM831X=m
-CONFIG_BACKLIGHT_ADP8860=m
-CONFIG_BACKLIGHT_ADP8870=m
-CONFIG_BACKLIGHT_PCF50633=m
-CONFIG_BACKLIGHT_LM3630A=m
-CONFIG_BACKLIGHT_LM3639=m
-CONFIG_BACKLIGHT_LP855X=m
-CONFIG_BACKLIGHT_SKY81452=m
-CONFIG_BACKLIGHT_GPIO=m
-CONFIG_BACKLIGHT_LV5207LP=m
-CONFIG_BACKLIGHT_BD6107=m
-CONFIG_BACKLIGHT_ARCXCNN=m
-CONFIG_BACKLIGHT_RAVE_SP=m
-# end of Backlight & LCD device support
-
-CONFIG_VGASTATE=m
-CONFIG_HDMI=y
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-# CONFIG_MDA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DUMMY_CONSOLE_COLUMNS=80
-CONFIG_DUMMY_CONSOLE_ROWS=25
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
-# end of Console display driver support
-
-# CONFIG_LOGO is not set
-# end of Graphics support
-
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_PCM_ELD=y
-CONFIG_SND_PCM_IEC958=y
-CONFIG_SND_DMAENGINE_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_SEQ_DEVICE=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_COMPRESS_OFFLOAD=m
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_PCM_TIMER=y
-CONFIG_SND_HRTIMER=m
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_MAX_CARDS=32
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_PROC_FS=y
-CONFIG_SND_VERBOSE_PROCFS=y
-CONFIG_SND_CTL_FAST_LOOKUP=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_CTL_INPUT_VALIDATION=y
-CONFIG_SND_VMASTER=y
-CONFIG_SND_DMA_SGBUF=y
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_SEQUENCER_OSS=m
-CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
-CONFIG_SND_SEQ_MIDI_EVENT=m
-CONFIG_SND_SEQ_MIDI=m
-CONFIG_SND_SEQ_MIDI_EMUL=m
-CONFIG_SND_SEQ_VIRMIDI=m
-CONFIG_SND_MPU401_UART=m
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_OPL3_LIB_SEQ=m
-CONFIG_SND_VX_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_PCSP is not set
-CONFIG_SND_DUMMY=m
-CONFIG_SND_ALOOP=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_MTS64=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_PORTMAN2X4=m
-CONFIG_SND_AC97_POWER_SAVE=y
-CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
-CONFIG_SND_SB_COMMON=m
-CONFIG_SND_ISA=y
-# CONFIG_SND_ADLIB is not set
-# CONFIG_SND_AD1816A is not set
-# CONFIG_SND_AD1848 is not set
-# CONFIG_SND_ALS100 is not set
-# CONFIG_SND_AZT1605 is not set
-# CONFIG_SND_AZT2316 is not set
-# CONFIG_SND_AZT2320 is not set
-# CONFIG_SND_CMI8328 is not set
-# CONFIG_SND_CMI8330 is not set
-# CONFIG_SND_CS4231 is not set
-# CONFIG_SND_CS4236 is not set
-# CONFIG_SND_ES1688 is not set
-# CONFIG_SND_ES18XX is not set
-# CONFIG_SND_SC6000 is not set
-# CONFIG_SND_GUSCLASSIC is not set
-# CONFIG_SND_GUSEXTREME is not set
-# CONFIG_SND_GUSMAX is not set
-# CONFIG_SND_INTERWAVE is not set
-# CONFIG_SND_INTERWAVE_STB is not set
-# CONFIG_SND_JAZZ16 is not set
-# CONFIG_SND_OPL3SA2 is not set
-# CONFIG_SND_OPTI92X_AD1848 is not set
-# CONFIG_SND_OPTI92X_CS4231 is not set
-# CONFIG_SND_OPTI93X is not set
-# CONFIG_SND_MIRO is not set
-# CONFIG_SND_SB8 is not set
-# CONFIG_SND_SB16 is not set
-# CONFIG_SND_SBAWE is not set
-# CONFIG_SND_SSCAPE is not set
-# CONFIG_SND_WAVEFRONT is not set
-# CONFIG_SND_MSND_PINNACLE is not set
-# CONFIG_SND_MSND_CLASSIC is not set
-CONFIG_SND_PCI=y
-CONFIG_SND_AD1889=m
-CONFIG_SND_ALS300=m
-CONFIG_SND_ALS4000=m
-CONFIG_SND_ALI5451=m
-CONFIG_SND_ASIHPI=m
-CONFIG_SND_ATIIXP=m
-CONFIG_SND_ATIIXP_MODEM=m
-CONFIG_SND_AU8810=m
-CONFIG_SND_AU8820=m
-CONFIG_SND_AU8830=m
-CONFIG_SND_AW2=m
-CONFIG_SND_AZT3328=m
-CONFIG_SND_BT87X=m
-CONFIG_SND_BT87X_OVERCLOCK=y
-CONFIG_SND_CA0106=m
-CONFIG_SND_CMIPCI=m
-CONFIG_SND_OXYGEN_LIB=m
-CONFIG_SND_OXYGEN=m
-CONFIG_SND_CS4281=m
-CONFIG_SND_CS46XX=m
-CONFIG_SND_CS46XX_NEW_DSP=y
-# CONFIG_SND_CS5530 is not set
-# CONFIG_SND_CS5535AUDIO is not set
-CONFIG_SND_CTXFI=m
-CONFIG_SND_DARLA20=m
-CONFIG_SND_GINA20=m
-CONFIG_SND_LAYLA20=m
-CONFIG_SND_DARLA24=m
-CONFIG_SND_GINA24=m
-CONFIG_SND_LAYLA24=m
-CONFIG_SND_MONA=m
-CONFIG_SND_MIA=m
-CONFIG_SND_ECHO3G=m
-CONFIG_SND_INDIGO=m
-CONFIG_SND_INDIGOIO=m
-CONFIG_SND_INDIGODJ=m
-CONFIG_SND_INDIGOIOX=m
-CONFIG_SND_INDIGODJX=m
-CONFIG_SND_EMU10K1=m
-CONFIG_SND_EMU10K1_SEQ=m
-CONFIG_SND_EMU10K1X=m
-CONFIG_SND_ENS1370=m
-CONFIG_SND_ENS1371=m
-CONFIG_SND_ES1938=m
-CONFIG_SND_ES1968=m
-CONFIG_SND_ES1968_INPUT=y
-CONFIG_SND_ES1968_RADIO=y
-CONFIG_SND_FM801=m
-CONFIG_SND_FM801_TEA575X_BOOL=y
-CONFIG_SND_HDSP=m
-CONFIG_SND_HDSPM=m
-CONFIG_SND_ICE1712=m
-CONFIG_SND_ICE1724=m
-CONFIG_SND_INTEL8X0=m
-CONFIG_SND_INTEL8X0M=m
-CONFIG_SND_KORG1212=m
-CONFIG_SND_LOLA=m
-CONFIG_SND_LX6464ES=m
-CONFIG_SND_MAESTRO3=m
-CONFIG_SND_MAESTRO3_INPUT=y
-CONFIG_SND_MIXART=m
-CONFIG_SND_NM256=m
-CONFIG_SND_PCXHR=m
-CONFIG_SND_RIPTIDE=m
-CONFIG_SND_RME32=m
-CONFIG_SND_RME96=m
-CONFIG_SND_RME9652=m
-# CONFIG_SND_SIS7019 is not set
-CONFIG_SND_SONICVIBES=m
-CONFIG_SND_TRIDENT=m
-CONFIG_SND_VIA82XX=m
-CONFIG_SND_VIA82XX_MODEM=m
-CONFIG_SND_VIRTUOSO=m
-CONFIG_SND_VX222=m
-CONFIG_SND_YMFPCI=m
-
-#
-# HD-Audio
-#
-CONFIG_SND_HDA=m
-CONFIG_SND_HDA_GENERIC_LEDS=y
-CONFIG_SND_HDA_INTEL=m
-CONFIG_SND_HDA_HWDEP=y
-CONFIG_SND_HDA_RECONFIG=y
-CONFIG_SND_HDA_INPUT_BEEP=y
-CONFIG_SND_HDA_INPUT_BEEP_MODE=1
-CONFIG_SND_HDA_PATCH_LOADER=y
-CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m
-CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m
-CONFIG_SND_HDA_CODEC_REALTEK=m
-CONFIG_SND_HDA_CODEC_ANALOG=m
-CONFIG_SND_HDA_CODEC_SIGMATEL=m
-CONFIG_SND_HDA_CODEC_VIA=m
-CONFIG_SND_HDA_CODEC_HDMI=m
-CONFIG_SND_HDA_CODEC_CIRRUS=m
-CONFIG_SND_HDA_CODEC_CONEXANT=m
-CONFIG_SND_HDA_CODEC_CA0110=m
-CONFIG_SND_HDA_CODEC_CA0132=m
-CONFIG_SND_HDA_CODEC_CA0132_DSP=y
-CONFIG_SND_HDA_CODEC_CMEDIA=m
-CONFIG_SND_HDA_CODEC_SI3054=m
-CONFIG_SND_HDA_GENERIC=m
-CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
-# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
-# end of HD-Audio
-
-CONFIG_SND_HDA_CORE=m
-CONFIG_SND_HDA_DSP_LOADER=y
-CONFIG_SND_HDA_COMPONENT=y
-CONFIG_SND_HDA_I915=y
-CONFIG_SND_HDA_EXT_CORE=m
-CONFIG_SND_HDA_PREALLOC_SIZE=2048
-CONFIG_SND_VIRTIO=m
-CONFIG_SND_INTEL_BYT_PREFER_SOF=y
-CONFIG_SND_INTEL_NHLT=y
-CONFIG_SND_INTEL_DSP_CONFIG=m
-CONFIG_SND_SPI=y
-CONFIG_SND_USB=y
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
-CONFIG_SND_USB_UA101=m
-CONFIG_SND_USB_USX2Y=m
-CONFIG_SND_USB_CAIAQ=m
-CONFIG_SND_USB_CAIAQ_INPUT=y
-CONFIG_SND_USB_US122L=m
-CONFIG_SND_USB_6FIRE=m
-CONFIG_SND_USB_HIFACE=m
-CONFIG_SND_BCD2000=m
-CONFIG_SND_USB_LINE6=m
-CONFIG_SND_USB_POD=m
-CONFIG_SND_USB_PODHD=m
-CONFIG_SND_USB_TONEPORT=m
-CONFIG_SND_USB_VARIAX=m
-CONFIG_SND_FIREWIRE=y
-CONFIG_SND_FIREWIRE_LIB=m
-CONFIG_SND_DICE=m
-CONFIG_SND_OXFW=m
-CONFIG_SND_ISIGHT=m
-CONFIG_SND_FIREWORKS=m
-CONFIG_SND_BEBOB=m
-CONFIG_SND_FIREWIRE_DIGI00X=m
-CONFIG_SND_FIREWIRE_TASCAM=m
-CONFIG_SND_FIREWIRE_MOTU=m
-CONFIG_SND_FIREFACE=m
-CONFIG_SND_PCMCIA=y
-CONFIG_SND_VXPOCKET=m
-CONFIG_SND_PDAUDIOCF=m
-CONFIG_SND_SOC=m
-CONFIG_SND_SOC_ADI=m
-CONFIG_SND_SOC_ADI_AXI_I2S=m
-CONFIG_SND_SOC_ADI_AXI_SPDIF=m
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_COMPRESS=y
-CONFIG_SND_SOC_TOPOLOGY=y
-CONFIG_SND_SOC_ACPI=m
-CONFIG_SND_SOC_AMD_ACP=m
-CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m
-CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m
-CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
-CONFIG_SND_SOC_AMD_ACP3x=m
-CONFIG_SND_SOC_AMD_RV_RT5682_MACH=m
-CONFIG_SND_SOC_AMD_RENOIR=m
-CONFIG_SND_SOC_AMD_RENOIR_MACH=m
-CONFIG_SND_SOC_AMD_ACP5x=m
-CONFIG_SND_SOC_AMD_VANGOGH_MACH=m
-CONFIG_SND_SOC_AMD_ACP6x=m
-CONFIG_SND_SOC_AMD_YC_MACH=m
-CONFIG_SND_SOC_AMD_ACP_COMMON=m
-CONFIG_SND_SOC_AMD_ACP_PCI=m
-CONFIG_SND_AMD_ASOC_RENOIR=m
-CONFIG_SND_AMD_ASOC_REMBRANDT=m
-CONFIG_SND_SOC_AMD_LEGACY_MACH=m
-CONFIG_SND_SOC_AMD_SOF_MACH=m
-CONFIG_SND_SOC_AMD_RPL_ACP6x=m
-CONFIG_SND_SOC_AMD_PS=m
-CONFIG_SND_SOC_AMD_PS_MACH=m
-CONFIG_SND_ATMEL_SOC=m
-CONFIG_SND_BCM63XX_I2S_WHISTLER=m
-CONFIG_SND_DESIGNWARE_I2S=m
-CONFIG_SND_DESIGNWARE_PCM=y
-
-#
-# SoC Audio for Freescale CPUs
-#
-
-#
-# Common SoC Audio options for Freescale CPUs:
-#
-CONFIG_SND_SOC_FSL_ASRC=m
-CONFIG_SND_SOC_FSL_SAI=m
-CONFIG_SND_SOC_FSL_MQS=m
-CONFIG_SND_SOC_FSL_AUDMIX=m
-CONFIG_SND_SOC_FSL_SSI=m
-CONFIG_SND_SOC_FSL_SPDIF=m
-CONFIG_SND_SOC_FSL_ESAI=m
-CONFIG_SND_SOC_FSL_MICFIL=m
-CONFIG_SND_SOC_FSL_EASRC=m
-CONFIG_SND_SOC_FSL_XCVR=m
-CONFIG_SND_SOC_FSL_AUD2HTX=m
-CONFIG_SND_SOC_FSL_RPMSG=m
-CONFIG_SND_SOC_IMX_AUDMUX=m
-# end of SoC Audio for Freescale CPUs
-
-CONFIG_SND_I2S_HI6210_I2S=m
-CONFIG_SND_SOC_IMG=y
-CONFIG_SND_SOC_IMG_I2S_IN=m
-CONFIG_SND_SOC_IMG_I2S_OUT=m
-CONFIG_SND_SOC_IMG_PARALLEL_OUT=m
-CONFIG_SND_SOC_IMG_SPDIF_IN=m
-CONFIG_SND_SOC_IMG_SPDIF_OUT=m
-CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m
-CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y
-CONFIG_SND_SOC_INTEL_AVS=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=m
-CONFIG_SND_SST_IPC=m
-CONFIG_SND_SST_IPC_PCI=m
-CONFIG_SND_SST_IPC_ACPI=m
-CONFIG_SND_SOC_INTEL_SST=m
-CONFIG_SND_SOC_INTEL_CATPT=m
-CONFIG_SND_SST_ATOM_HIFI2_PLATFORM=m
-CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI=m
-CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI=m
-CONFIG_SND_SOC_INTEL_SKYLAKE=m
-CONFIG_SND_SOC_INTEL_SKL=m
-CONFIG_SND_SOC_INTEL_APL=m
-CONFIG_SND_SOC_INTEL_KBL=m
-CONFIG_SND_SOC_INTEL_GLK=m
-CONFIG_SND_SOC_INTEL_CNL=m
-CONFIG_SND_SOC_INTEL_CFL=m
-CONFIG_SND_SOC_INTEL_CML_H=m
-CONFIG_SND_SOC_INTEL_CML_LP=m
-CONFIG_SND_SOC_INTEL_SKYLAKE_FAMILY=m
-CONFIG_SND_SOC_INTEL_SKYLAKE_SSP_CLK=m
-CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC=y
-CONFIG_SND_SOC_INTEL_AVS=m
-CONFIG_SND_SOC_INTEL_SKYLAKE_COMMON=m
-CONFIG_SND_SOC_ACPI_INTEL_MATCH=m
-CONFIG_SND_SOC_INTEL_MACH=y
-# CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES is not set
-CONFIG_SND_SOC_INTEL_HASWELL_MACH=m
-CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH=m
-CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=m
-CONFIG_SND_SOC_INTEL_BROADWELL_MACH=m
-CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=m
-CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH=m
-CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH=m
-CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=m
-CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH=m
-CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH=m
-CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH=m
-CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH=m
-CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH=m
-CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH=m
-CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH=m
-CONFIG_SND_SOC_INTEL_SKL_RT286_MACH=m
-CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH=m
-CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_DA7219_MAX98357A_GENERIC=m
-CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_COMMON=m
-CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_BXT_RT298_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98927_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_RT5660_MACH=m
-CONFIG_SND_SOC_INTEL_GLK_DA7219_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_GLK_RT5682_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_CS42L42_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_ES8336_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_NAU8825_MACH=m
-CONFIG_SND_SOC_INTEL_CML_LP_DA7219_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_CML_RT1011_RT5682_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_DA7219_MAX98373_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_SSP_AMP_MACH=m
-CONFIG_SND_SOC_INTEL_EHL_RT5660_MACH=m
-CONFIG_SND_SOC_MTK_BTCVSD=m
-CONFIG_SND_SOC_MT8192=m
-CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682=m
-CONFIG_SND_SOC_SOF_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_PCI=m
-CONFIG_SND_SOC_SOF_ACPI=m
-# CONFIG_SND_SOC_SOF_DEBUG_PROBES is not set
-# CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT is not set
-CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m
-CONFIG_SND_SOC_SOF_AMD_RENOIR=m
-CONFIG_SND_SOC_SOF_AMD_REMBRANDT=m
-CONFIG_SND_SOC_SOF=m
-CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE=y
-CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_BAYTRAIL=m
-CONFIG_SND_SOC_SOF_BAYTRAIL_SUPPORT=y
-CONFIG_SND_SOC_SOF_INTEL_ACPI=m
-CONFIG_SND_SOC_SOF_INTEL_PCI=m
-CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC=m
-CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP=m
-CONFIG_SND_SOC_SOF_INTEL_COMMON=m
-CONFIG_SND_SOC_SOF_BROADWELL_SUPPORT=y
-CONFIG_SND_SOC_SOF_BROADWELL=m
-CONFIG_SND_SOC_SOF_MERRIFIELD_SUPPORT=y
-CONFIG_SND_SOC_SOF_SKYLAKE=m
-CONFIG_SND_SOC_SOF_MERRIFIELD=m
-CONFIG_SND_SOC_SOF_KABYLAKE=m
-CONFIG_SND_SOC_SOF_APOLLOLAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_APOLLOLAKE=m
-CONFIG_SND_SOC_SOF_GEMINILAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_GEMINILAKE=m
-CONFIG_SND_SOC_SOF_CANNONLAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_CANNONLAKE=m
-CONFIG_SND_SOC_SOF_COFFEELAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_COFFEELAKE=m
-CONFIG_SND_SOC_SOF_ICELAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_ICELAKE=m
-CONFIG_SND_SOC_SOF_COMETLAKE=m
-CONFIG_SND_SOC_SOF_COMETLAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_COMETLAKE_LP_SUPPORT=y
-CONFIG_SND_SOC_SOF_TIGERLAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_TIGERLAKE=m
-CONFIG_SND_SOC_SOF_ELKHARTLAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_ELKHARTLAKE=m
-CONFIG_SND_SOC_SOF_ALDERLAKE=m
-CONFIG_SND_SOC_SOF_METEORLAKE=m
-CONFIG_SND_SOC_SOF_JASPERLAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_JASPERLAKE=m
-CONFIG_SND_SOC_SOF_ALDERLAKE_SUPPORT=y
-CONFIG_SND_SOC_SOF_HDA_COMMON=m
-CONFIG_SND_SOC_SOF_HDA_LINK=y
-CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC=y
-CONFIG_SND_SOC_SOF_HDA_ALWAYS_ENABLE_DMI_L1=y
-CONFIG_SND_SOC_SOF_HDA_LINK_BASELINE=m
-CONFIG_SND_SOC_SOF_HDA=m
-CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK=y
-CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE=m
-CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE=m
-CONFIG_SND_SOC_SOF_XTENSA=m
-
-#
-# STMicroelectronics STM32 SOC audio support
-#
-# end of STMicroelectronics STM32 SOC audio support
-
-CONFIG_SND_SOC_XILINX_I2S=m
-CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
-CONFIG_SND_SOC_XILINX_SPDIF=m
-CONFIG_SND_SOC_XTFPGA_I2S=m
-CONFIG_ZX_TDM=m
-CONFIG_SND_SOC_I2C_AND_SPI=m
-
-#
-# CODEC drivers
-#
-CONFIG_SND_SOC_AC97_CODEC=m
-CONFIG_SND_SOC_ADAU1372_I2C=m
-CONFIG_SND_SOC_ADAU1372_SPI=m
-CONFIG_SND_SOC_ADAU_UTILS=m
-CONFIG_SND_SOC_ADAU1701=m
-CONFIG_SND_SOC_ADAU17X1=m
-CONFIG_SND_SOC_ADAU1761=m
-CONFIG_SND_SOC_ADAU1761_I2C=m
-CONFIG_SND_SOC_ADAU1761_SPI=m
-CONFIG_SND_SOC_ADAU7002=m
-CONFIG_SND_SOC_ADAU7118=m
-CONFIG_SND_SOC_ADAU7118_HW=m
-CONFIG_SND_SOC_ADAU7118_I2C=m
-CONFIG_SND_SOC_AK4104=m
-CONFIG_SND_SOC_AK4118=m
-CONFIG_SND_SOC_AK4458=m
-CONFIG_SND_SOC_AK4554=m
-CONFIG_SND_SOC_AK4613=m
-CONFIG_SND_SOC_AK4642=m
-CONFIG_SND_SOC_AK5386=m
-CONFIG_SND_SOC_AK5558=m
-CONFIG_SND_SOC_ALC5623=m
-CONFIG_SND_SOC_AW8738=m
-CONFIG_SND_SOC_BD28623=m
-# CONFIG_SND_SOC_BT_SCO is not set
-CONFIG_SND_SOC_CROS_EC_CODEC=m
-CONFIG_SND_SOC_CS35L32=m
-CONFIG_SND_SOC_CS35L33=m
-CONFIG_SND_SOC_CS35L34=m
-CONFIG_SND_SOC_CS35L35=m
-CONFIG_SND_SOC_CS35L36=m
-CONFIG_SND_SOC_CS42L42=m
-CONFIG_SND_SOC_CS42L51=m
-CONFIG_SND_SOC_CS42L51_I2C=m
-CONFIG_SND_SOC_CS42L52=m
-CONFIG_SND_SOC_CS42L56=m
-CONFIG_SND_SOC_CS42L73=m
-CONFIG_SND_SOC_CS42L83=m
-CONFIG_SND_SOC_CS4234=m
-CONFIG_SND_SOC_CS4265=m
-CONFIG_SND_SOC_CS4270=m
-CONFIG_SND_SOC_CS4271=m
-CONFIG_SND_SOC_CS4271_I2C=m
-CONFIG_SND_SOC_CS4271_SPI=m
-CONFIG_SND_SOC_CS42XX8=m
-CONFIG_SND_SOC_CS42XX8_I2C=m
-CONFIG_SND_SOC_CS43130=m
-CONFIG_SND_SOC_CS4341=m
-CONFIG_SND_SOC_CS4349=m
-CONFIG_SND_SOC_CS53L30=m
-CONFIG_SND_SOC_CX2072X=m
-CONFIG_SND_SOC_DA7213=m
-CONFIG_SND_SOC_DA7219=m
-CONFIG_SND_SOC_DMIC=m
-CONFIG_SND_SOC_HDMI_CODEC=m
-CONFIG_SND_SOC_ES7134=m
-CONFIG_SND_SOC_ES7241=m
-CONFIG_SND_SOC_ES8316=m
-CONFIG_SND_SOC_ES8326=m
-CONFIG_SND_SOC_ES8328=m
-CONFIG_SND_SOC_ES8328_I2C=m
-CONFIG_SND_SOC_ES8328_SPI=m
-CONFIG_SND_SOC_GTM601=m
-CONFIG_SND_SOC_HDA=m
-CONFIG_SND_SOC_HDAC_HDMI=m
-CONFIG_SND_SOC_HDAC_HDA=m
-CONFIG_SND_SOC_INNO_RK3036=m
-CONFIG_SND_SOC_MAX98088=m
-CONFIG_SND_SOC_MAX98090=m
-CONFIG_SND_SOC_MAX98357A=m
-CONFIG_SND_SOC_MAX98504=m
-CONFIG_SND_SOC_MAX9867=m
-CONFIG_SND_SOC_MAX98927=m
-CONFIG_SND_SOC_MAX98373=m
-CONFIG_SND_SOC_MAX98373_I2C=m
-CONFIG_SND_SOC_MAX98373_SDW=m
-CONFIG_SND_SOC_MAX98390=m
-CONFIG_SND_SOC_MAX9860=m
-CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
-CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
-CONFIG_SND_SOC_PCM1681=m
-CONFIG_SND_SOC_PCM1789=m
-CONFIG_SND_SOC_PCM1789_I2C=m
-CONFIG_SND_SOC_PCM179X=m
-CONFIG_SND_SOC_PCM179X_I2C=m
-CONFIG_SND_SOC_PCM179X_SPI=m
-CONFIG_SND_SOC_PCM186X=m
-CONFIG_SND_SOC_PCM186X_I2C=m
-CONFIG_SND_SOC_PCM186X_SPI=m
-CONFIG_SND_SOC_PCM3060=m
-CONFIG_SND_SOC_PCM3060_I2C=m
-CONFIG_SND_SOC_PCM3060_SPI=m
-CONFIG_SND_SOC_PCM3168A=m
-CONFIG_SND_SOC_PCM3168A_I2C=m
-CONFIG_SND_SOC_PCM3168A_SPI=m
-CONFIG_SND_SOC_PCM5102A=m
-CONFIG_SND_SOC_PCM512x=m
-CONFIG_SND_SOC_PCM512x_I2C=m
-CONFIG_SND_SOC_PCM512x_SPI=m
-CONFIG_SND_SOC_RK3328=m
-CONFIG_SND_SOC_RK817=m
-CONFIG_SND_SOC_RL6231=m
-CONFIG_SND_SOC_RL6347A=m
-CONFIG_SND_SOC_RT286=m
-CONFIG_SND_SOC_RT298=m
-CONFIG_SND_SOC_RT1011=m
-CONFIG_SND_SOC_RT1015=m
-CONFIG_SND_SOC_RT1308_SDW=m
-CONFIG_SND_SOC_RT1316_SDW=m
-CONFIG_SND_SOC_RT5514=m
-CONFIG_SND_SOC_RT5514_SPI=m
-CONFIG_SND_SOC_RT5616=m
-CONFIG_SND_SOC_RT5631=m
-CONFIG_SND_SOC_RT5640=m
-CONFIG_SND_SOC_RT5659=m
-CONFIG_SND_SOC_RT5640=m
-CONFIG_SND_SOC_RT5645=m
-CONFIG_SND_SOC_RT5651=m
-CONFIG_SND_SOC_RT5660=m
-CONFIG_SND_SOC_RT5663=m
-CONFIG_SND_SOC_RT5670=m
-CONFIG_SND_SOC_RT5677=m
-CONFIG_SND_SOC_RT5677_SPI=m
-CONFIG_SND_SOC_RT5682=m
-CONFIG_SND_SOC_RT5682_I2C=m
-CONFIG_SND_SOC_RT5682_SDW=m
-CONFIG_SND_SOC_RT700=m
-CONFIG_SND_SOC_RT700_SDW=m
-CONFIG_SND_SOC_RT711=m
-CONFIG_SND_SOC_RT711_SDW=m
-CONFIG_SND_SOC_RT711_SDCA_SDW=m
-CONFIG_SND_SOC_RT715=m
-CONFIG_SND_SOC_RT715_SDW=m
-CONFIG_SND_SOC_RT715_SDCA_SDW=m
-CONFIG_SND_SOC_SGTL5000=m
-CONFIG_SND_SOC_SI476X=m
-CONFIG_SND_SOC_SIGMADSP=m
-CONFIG_SND_SOC_SIGMADSP_I2C=m
-CONFIG_SND_SOC_SIGMADSP_REGMAP=m
-CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
-CONFIG_SND_SOC_SIMPLE_MUX=m
-CONFIG_SND_SOC_SIRF_AUDIO_CODEC=m
-CONFIG_SND_SOC_SPDIF=m
-CONFIG_SND_SOC_SRC4XXX_I2C=m
-CONFIG_SND_SOC_SSM2305=m
-CONFIG_SND_SOC_SSM2518=m
-CONFIG_SND_SOC_SSM2602=m
-CONFIG_SND_SOC_SSM2602_SPI=m
-CONFIG_SND_SOC_SSM2602_I2C=m
-CONFIG_SND_SOC_SSM4567=m
-CONFIG_SND_SOC_STA32X=m
-CONFIG_SND_SOC_STA350=m
-CONFIG_SND_SOC_STI_SAS=m
-CONFIG_SND_SOC_TAS2552=m
-CONFIG_SND_SOC_TAS2562=m
-CONFIG_SND_SOC_TAS2764=m
-CONFIG_SND_SOC_TAS2770=m
-CONFIG_SND_SOC_TAS2780=m
-CONFIG_SND_SOC_WSA883X=m
-CONFIG_SND_SOC_TAS5086=m
-CONFIG_SND_SOC_TAS571X=m
-CONFIG_SND_SOC_TAS5720=m
-CONFIG_SND_SOC_TAS5805M=m
-CONFIG_SND_SOC_TAS6424=m
-CONFIG_SND_SOC_TDA7419=m
-CONFIG_SND_SOC_TFA9879=m
-CONFIG_SND_SOC_TFA989X=m
-CONFIG_SND_SOC_TLV320AIC23=m
-CONFIG_SND_SOC_TLV320AIC23_I2C=m
-CONFIG_SND_SOC_TLV320AIC23_SPI=m
-CONFIG_SND_SOC_TLV320AIC31XX=m
-CONFIG_SND_SOC_TLV320AIC32X4=m
-CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
-CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
-CONFIG_SND_SOC_TLV320AIC3X_I2C=m
-CONFIG_SND_SOC_TLV320AIC3X_SPI=m
-CONFIG_SND_SOC_TLV320AIC3X=m
-CONFIG_SND_SOC_TLV320ADCX140=m
-CONFIG_SND_SOC_TS3A227E=m
-CONFIG_SND_SOC_TSCS42XX=m
-CONFIG_SND_SOC_TSCS454=m
-CONFIG_SND_SOC_UDA1334=m
-CONFIG_SND_SOC_WCD938X_SDW=m
-CONFIG_SND_SOC_WCD9335=m
-CONFIG_SND_SOC_WCD934X=m
-CONFIG_SND_SOC_WCD938X_SDW=m
-CONFIG_SND_SOC_WM8510=m
-CONFIG_SND_SOC_WM8523=m
-CONFIG_SND_SOC_WM8524=m
-CONFIG_SND_SOC_WM8580=m
-CONFIG_SND_SOC_WM8711=m
-CONFIG_SND_SOC_WM8728=m
-CONFIG_SND_SOC_WM8731=m
-CONFIG_SND_SOC_WM8737=m
-CONFIG_SND_SOC_WM8741=m
-CONFIG_SND_SOC_WM8750=m
-CONFIG_SND_SOC_WM8753=m
-CONFIG_SND_SOC_WM8770=m
-CONFIG_SND_SOC_WM8776=m
-CONFIG_SND_SOC_WM8782=m
-CONFIG_SND_SOC_WM8804=m
-CONFIG_SND_SOC_WM8804_I2C=m
-CONFIG_SND_SOC_WM8804_SPI=m
-CONFIG_SND_SOC_WM8903=m
-CONFIG_SND_SOC_WM8904=m
-CONFIG_SND_SOC_WM8960=m
-CONFIG_SND_SOC_WM8962=m
-CONFIG_SND_SOC_WM8974=m
-CONFIG_SND_SOC_WM8978=m
-CONFIG_SND_SOC_WM8985=m
-CONFIG_SND_SOC_WSA881X=m
-CONFIG_SND_SOC_ZL38060=m
-CONFIG_SND_SOC_ZX_AUD96P22=m
-CONFIG_SND_SOC_MAX9759=m
-CONFIG_SND_SOC_MT6351=m
-CONFIG_SND_SOC_MT6358=m
-CONFIG_SND_SOC_MT6660=m
-CONFIG_SND_SOC_NAU8315=m
-CONFIG_SND_SOC_NAU8540=m
-CONFIG_SND_SOC_NAU8810=m
-CONFIG_SND_SOC_NAU8822=m
-CONFIG_SND_SOC_NAU8824=m
-CONFIG_SND_SOC_NAU8825=m
-CONFIG_SND_SOC_TPA6130A2=m
-CONFIG_SND_SOC_LPASS_WSA_MACRO=m
-CONFIG_SND_SOC_LPASS_VA_MACRO=m
-CONFIG_SND_SOC_LPASS_RX_MACRO=m
-CONFIG_SND_SOC_LPASS_TX_MACRO=m
-# end of CODEC drivers
-
-CONFIG_SND_SIMPLE_CARD_UTILS=m
-CONFIG_SND_SIMPLE_CARD=m
-CONFIG_SND_X86=y
-CONFIG_HDMI_LPE_AUDIO=m
-CONFIG_SND_SYNTH_EMUX=m
-CONFIG_AC97_BUS=m
-
-#
-# HID support
-#
-CONFIG_HID=m
-CONFIG_HID_BATTERY_STRENGTH=y
-CONFIG_HIDRAW=y
-CONFIG_UHID=m
-CONFIG_HID_GENERIC=m
-
-#
-# Special HID drivers
-#
-CONFIG_HID_A4TECH=m
-CONFIG_HID_ACCUTOUCH=m
-CONFIG_HID_ACRUX=m
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=m
-CONFIG_HID_APPLEIR=m
-CONFIG_HID_ASUS=m
-CONFIG_HID_AUREAL=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_BETOP_FF=m
-CONFIG_HID_BIGBEN_FF=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CORSAIR=m
-CONFIG_HID_COUGAR=m
-CONFIG_HID_MACALLY=m
-CONFIG_HID_PRODIKEYS=m
-CONFIG_HID_CMEDIA=m
-CONFIG_HID_CP2112=m
-CONFIG_HID_CREATIVE_SB0540=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_DRAGONRISE=m
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=m
-CONFIG_HID_ELAN=m
-CONFIG_HID_ELECOM=m
-CONFIG_HID_ELO=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_FT260=m
-CONFIG_HID_GEMBIRD=m
-CONFIG_HID_GFRM=m
-CONFIG_HID_GLORIOUS=m
-CONFIG_HID_HOLTEK=m
-CONFIG_HOLTEK_FF=y
-CONFIG_HID_GOOGLE_HAMMER=m
-CONFIG_HID_VIVALDI=m
-CONFIG_HID_GT683R=m
-CONFIG_HID_KEYTOUCH=m
-CONFIG_HID_KYE=m
-CONFIG_HID_UCLOGIC=m
-CONFIG_HID_WALTOP=m
-CONFIG_HID_VIEWSONIC=m
-CONFIG_HID_VRC2=m
-CONFIG_HID_GYRATION=m
-CONFIG_HID_ICADE=m
-CONFIG_HID_ITE=m
-CONFIG_HID_JABRA=m
-CONFIG_HID_TWINHAN=m
-CONFIG_HID_KENSINGTON=m
-CONFIG_HID_LCPOWER=m
-CONFIG_HID_LED=m
-CONFIG_HID_LENOVO=m
-CONFIG_HID_LOGITECH=m
-CONFIG_HID_LOGITECH_DJ=m
-CONFIG_HID_LOGITECH_HIDPP=m
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWHEELS_FF=y
-CONFIG_HID_MAGICMOUSE=m
-CONFIG_HID_MALTRON=m
-CONFIG_HID_MAYFLASH=m
-CONFIG_HID_REDRAGON=m
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_MULTITOUCH=m
-CONFIG_HID_NTI=m
-CONFIG_HID_NTRIG=m
-CONFIG_HID_ORTEK=m
-CONFIG_HID_PANTHERLORD=m
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PENMOUNT=m
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_PICOLCD=m
-# CONFIG_HID_PICOLCD_FB is not set
-# CONFIG_HID_PICOLCD_BACKLIGHT is not set
-# CONFIG_HID_PICOLCD_LCD is not set
-# CONFIG_HID_PICOLCD_LEDS is not set
-# CONFIG_HID_PICOLCD_CIR is not set
-CONFIG_HID_PLANTRONICS=m
-CONFIG_HID_PLAYSTATION=m
-CONFIG_HID_PXRC=m
-CONFIG_HID_RAZER=m
-CONFIG_PLAYSTATION_FF=y
-CONFIG_HID_PRIMAX=m
-CONFIG_HID_RETRODE=m
-CONFIG_HID_ROCCAT=m
-CONFIG_HID_SAITEK=m
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SEMITEK=m
-CONFIG_HID_SIGMAMICRO=m
-CONFIG_HID_SONY=m
-CONFIG_SONY_FF=y
-CONFIG_HID_SPEEDLINK=m
-CONFIG_HID_STEAM=m
-CONFIG_HID_STEELSERIES=m
-CONFIG_HID_SUNPLUS=m
-CONFIG_HID_RMI=m
-CONFIG_HID_GREENASIA=m
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_HYPERV_MOUSE=m
-CONFIG_HID_SMARTJOYPLUS=m
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TIVO=m
-CONFIG_HID_TOPSEED=m
-CONFIG_HID_TOPRE=m
-CONFIG_HID_THINGM=m
-CONFIG_HID_THRUSTMASTER=m
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_UDRAW_PS3=m
-CONFIG_HID_U2FZERO=m
-CONFIG_HID_WACOM=m
-CONFIG_HID_WIIMOTE=m
-CONFIG_HID_XINMO=m
-CONFIG_HID_ZEROPLUS=m
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=m
-CONFIG_HID_SENSOR_HUB=m
-CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
-CONFIG_HID_ALPS=m
-CONFIG_HID_MCP2221=m
-# end of Special HID drivers
-
-#
-# USB HID support
-#
-CONFIG_USB_HID=m
-CONFIG_HID_PID=y
-CONFIG_USB_HIDDEV=y
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# end of USB HID Boot Protocol drivers
-# end of USB HID support
-
-#
-# I2C HID support
-#
-CONFIG_I2C_HID=m
-CONFIG_I2C_HID_OF=m
-CONFIG_I2C_HID_OF_ELAN=m
-CONFIG_USB_ONBOARD_HUB=m
-CONFIG_I2C_HID_OF_GOODIX=m
-CONFIG_I2C_HID_ACPI=m
-# end of I2C HID support
-# end of HID support
-
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_LED_TRIG=y
-CONFIG_USB_ULPI_BUS=m
-CONFIG_USB_CONN_GPIO=m
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB=m
-CONFIG_USB_PCI=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEFAULT_PERSIST=y
-CONFIG_USB_FEW_INIT_RETRIES=y
-CONFIG_USB_DYNAMIC_MINORS=y
-CONFIG_USB_OTG=y
-# CONFIG_USB_OTG_PRODUCTLIST is not set
-# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
-CONFIG_USB_OTG_FSM=m
-CONFIG_USB_LEDS_TRIGGER_USBPORT=m
-CONFIG_USB_AUTOSUSPEND_DELAY=2
-CONFIG_USB_MON=m
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_C67X00_HCD=m
-CONFIG_USB_XHCI_HCD=m
-CONFIG_USB_XHCI_DBGCAP=y
-CONFIG_USB_XHCI_PCI=m
-CONFIG_USB_XHCI_PCI_RENESAS=m
-CONFIG_USB_XHCI_PLATFORM=m
-CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-CONFIG_USB_EHCI_PCI=m
-CONFIG_USB_EHCI_FSL=m
-CONFIG_USB_EHCI_HCD_NPCM7XX=m
-CONFIG_USB_EHCI_HCD_PLATFORM=m
-CONFIG_USB_OXU210HP_HCD=m
-CONFIG_USB_ISP116X_HCD=m
-CONFIG_USB_FOTG210_HCD=m
-CONFIG_USB_MAX3421_HCD=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_OHCI_HCD_PCI=m
-CONFIG_USB_OHCI_HCD_SSB=y
-CONFIG_USB_OHCI_HCD_PLATFORM=m
-CONFIG_USB_UHCI_HCD=m
-CONFIG_USB_U132_HCD=m
-CONFIG_USB_SL811_HCD=m
-# CONFIG_USB_SL811_HCD_ISO is not set
-CONFIG_USB_SL811_CS=m
-CONFIG_USB_R8A66597_HCD=m
-CONFIG_USB_HCD_BCMA=m
-CONFIG_USB_HCD_SSB=m
-# CONFIG_USB_HCD_TEST_MODE is not set
-
-#
-# USB Device Class drivers
-#
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_WDM=m
-CONFIG_USB_TMC=m
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-CONFIG_USB_STORAGE_REALTEK=m
-CONFIG_REALTEK_AUTOPM=y
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_ISD200=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_STORAGE_ALAUDA=m
-CONFIG_USB_STORAGE_ONETOUCH=m
-CONFIG_USB_STORAGE_KARMA=m
-CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-CONFIG_USB_STORAGE_ENE_UB6250=m
-CONFIG_USB_UAS=m
-
-#
-# USB Imaging devices
-#
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USBIP_CORE=m
-CONFIG_USBIP_VHCI_HCD=m
-CONFIG_USBIP_VHCI_HC_PORTS=8
-CONFIG_USBIP_VHCI_NR_HCS=1
-CONFIG_USBIP_HOST=m
-CONFIG_USBIP_VUDC=m
-# CONFIG_USBIP_DEBUG is not set
-CONFIG_USB_CDNS_SUPPORT=m
-CONFIG_USB_CDNS3=m
-CONFIG_USB_CDNSP_PCI=m
-CONFIG_USB_CDNSP_GADGET=y
-CONFIG_USB_CDNSP_HOST=y
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_USB_CDNS3_HOST=y
-CONFIG_USB_CDNS3_PCI_WRAP=m
-CONFIG_USB_MUSB_HDRC=m
-# CONFIG_USB_MUSB_HOST is not set
-# CONFIG_USB_MUSB_GADGET is not set
-CONFIG_USB_MUSB_DUAL_ROLE=y
-
-#
-# Platform Glue Layer
-#
-
-#
-# MUSB DMA mode
-#
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_DWC3=m
-# CONFIG_USB_DWC3_ULPI is not set
-# CONFIG_USB_DWC3_HOST is not set
-# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_DUAL_ROLE=y
-
-#
-# Platform Glue Driver Support
-#
-CONFIG_USB_DWC3_PCI=m
-CONFIG_USB_DWC3_HAPS=m
-CONFIG_USB_DWC2=m
-# CONFIG_USB_DWC2_HOST is not set
-
-#
-# Gadget/Dual-role mode requires USB Gadget support to be enabled
-#
-# CONFIG_USB_DWC2_PERIPHERAL is not set
-CONFIG_USB_DWC2_DUAL_ROLE=y
-CONFIG_USB_DWC2_PCI=m
-# CONFIG_USB_DWC2_DEBUG is not set
-# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
-CONFIG_USB_CHIPIDEA=m
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_PCI=m
-CONFIG_USB_CHIPIDEA_MSM=m
-CONFIG_USB_CHIPIDEA_GENERIC=m
-CONFIG_USB_ISP1760=m
-CONFIG_USB_ISP1760_HCD=y
-CONFIG_USB_ISP1761_UDC=y
-# CONFIG_USB_ISP1760_HOST_ROLE is not set
-# CONFIG_USB_ISP1760_GADGET_ROLE is not set
-CONFIG_USB_ISP1760_DUAL_ROLE=y
-
-#
-# USB port drivers
-#
-CONFIG_USB_USS720=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_SIMPLE=m
-CONFIG_USB_SERIAL_AIRCABLE=m
-CONFIG_USB_SERIAL_ARK3116=m
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_CH341=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CP210X=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_F81232=m
-CONFIG_USB_SERIAL_F8153X=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_IUU=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_METRO=m
-CONFIG_USB_SERIAL_MOS7720=m
-CONFIG_USB_SERIAL_MOS7715_PARPORT=y
-CONFIG_USB_SERIAL_MOS7840=m
-CONFIG_USB_SERIAL_MXUPORT=m
-CONFIG_USB_SERIAL_NAVMAN=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_OTI6858=m
-CONFIG_USB_SERIAL_QCAUX=m
-CONFIG_USB_SERIAL_QUALCOMM=m
-CONFIG_USB_SERIAL_SPCP8X5=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_SAFE_PADDED=y
-CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-CONFIG_USB_SERIAL_SYMBOL=m
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-CONFIG_USB_SERIAL_WWAN=m
-CONFIG_USB_SERIAL_OPTION=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_SERIAL_OPTICON=m
-CONFIG_USB_SERIAL_XSENS_MT=m
-CONFIG_USB_SERIAL_WISHBONE=m
-CONFIG_USB_SERIAL_SSU100=m
-CONFIG_USB_SERIAL_QT2=m
-# CONFIG_USB_SERIAL_UPD78F0730 is not set
-CONFIG_USB_SERIAL_XR=m
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_ADUTUX=m
-CONFIG_USB_SEVSEG=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_CYPRESS_CY7C63=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_IDMOUSE=m
-CONFIG_USB_FTDI_ELAN=m
-CONFIG_USB_APPLEDISPLAY=m
-CONFIG_USB_QCOM_EUD=m
-CONFIG_APPLE_MFI_FASTCHARGE=m
-CONFIG_USB_SISUSBVGA=m
-CONFIG_USB_SISUSBVGA_CON=y
-CONFIG_USB_LD=m
-CONFIG_USB_TRANCEVIBRATOR=m
-CONFIG_USB_IOWARRIOR=m
-CONFIG_USB_TEST=m
-CONFIG_USB_EHSET_TEST_FIXTURE=m
-CONFIG_USB_ISIGHTFW=m
-CONFIG_USB_YUREX=m
-CONFIG_USB_EZUSB_FX2=m
-CONFIG_USB_HUB_USB251XB=m
-CONFIG_USB_HSIC_USB3503=m
-CONFIG_USB_HSIC_USB4604=m
-CONFIG_USB_LINK_LAYER_TEST=m
-CONFIG_USB_CHAOSKEY=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_CXACRU=m
-CONFIG_USB_UEAGLEATM=m
-CONFIG_USB_XUSBATM=m
-
-#
-# USB Physical Layer drivers
-#
-CONFIG_USB_PHY=y
-CONFIG_NOP_USB_XCEIV=m
-CONFIG_USB_GPIO_VBUS=m
-CONFIG_TAHVO_USB=m
-CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y
-CONFIG_USB_ISP1301=m
-# end of USB Physical Layer drivers
-
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
-CONFIG_U_SERIAL_CONSOLE=y
-
-#
-# USB Peripheral Controller
-#
-CONFIG_USB_FOTG210_UDC=m
-CONFIG_USB_GR_UDC=m
-CONFIG_USB_R8A66597=m
-CONFIG_USB_PXA27X=m
-CONFIG_USB_MV_UDC=m
-CONFIG_USB_MV_U3D=m
-CONFIG_USB_SNP_CORE=m
-CONFIG_USB_M66592=m
-CONFIG_USB_BDC_UDC=m
-
-#
-# Platform Support
-#
-CONFIG_USB_BDC_PCI=m
-CONFIG_USB_AMD5536UDC=m
-CONFIG_USB_NET2272=m
-CONFIG_USB_NET2272_DMA=y
-CONFIG_USB_NET2280=m
-CONFIG_USB_GOKU=m
-CONFIG_USB_EG20T=m
-CONFIG_USB_MAX3420_UDC=m
-# CONFIG_USB_DUMMY_HCD is not set
-# end of USB Peripheral Controller
-
-CONFIG_USB_LIBCOMPOSITE=m
-CONFIG_USB_F_ACM=m
-CONFIG_USB_F_SS_LB=m
-CONFIG_USB_U_SERIAL=m
-CONFIG_USB_U_ETHER=m
-CONFIG_USB_U_AUDIO=m
-CONFIG_USB_F_SERIAL=m
-CONFIG_USB_F_OBEX=m
-CONFIG_USB_F_NCM=m
-CONFIG_USB_F_ECM=m
-CONFIG_USB_F_PHONET=m
-CONFIG_USB_F_EEM=m
-CONFIG_USB_F_SUBSET=m
-CONFIG_USB_F_RNDIS=m
-CONFIG_USB_F_MASS_STORAGE=m
-CONFIG_USB_F_FS=m
-CONFIG_USB_F_UAC1=m
-CONFIG_USB_F_UAC2=m
-CONFIG_USB_F_UVC=m
-CONFIG_USB_F_MIDI=m
-CONFIG_USB_F_HID=m
-CONFIG_USB_F_PRINTER=m
-CONFIG_USB_F_TCM=m
-CONFIG_USB_CONFIGFS=m
-CONFIG_USB_CONFIGFS_SERIAL=y
-CONFIG_USB_CONFIGFS_ACM=y
-CONFIG_USB_CONFIGFS_OBEX=y
-CONFIG_USB_CONFIGFS_NCM=y
-CONFIG_USB_CONFIGFS_ECM=y
-CONFIG_USB_CONFIGFS_ECM_SUBSET=y
-CONFIG_USB_CONFIGFS_RNDIS=y
-CONFIG_USB_CONFIGFS_EEM=y
-CONFIG_USB_CONFIGFS_PHONET=y
-CONFIG_USB_CONFIGFS_MASS_STORAGE=y
-CONFIG_USB_CONFIGFS_F_LB_SS=y
-CONFIG_USB_CONFIGFS_F_FS=y
-CONFIG_USB_CONFIGFS_F_UAC1=y
-# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
-CONFIG_USB_CONFIGFS_F_UAC2=y
-CONFIG_USB_CONFIGFS_F_MIDI=y
-CONFIG_USB_CONFIGFS_F_HID=y
-CONFIG_USB_CONFIGFS_F_UVC=y
-CONFIG_USB_CONFIGFS_F_PRINTER=y
-CONFIG_USB_CONFIGFS_F_TCM=y
-
-#
-# USB Gadget precomposed configurations
-#
-CONFIG_USB_ZERO=m
-CONFIG_USB_ZERO_HNPTEST=y
-CONFIG_USB_AUDIO=m
-CONFIG_GADGET_UAC1=y
-# CONFIG_GADGET_UAC1_LEGACY is not set
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-CONFIG_USB_ETH_EEM=y
-CONFIG_USB_G_NCM=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FUNCTIONFS=m
-CONFIG_USB_FUNCTIONFS_ETH=y
-CONFIG_USB_FUNCTIONFS_RNDIS=y
-CONFIG_USB_FUNCTIONFS_GENERIC=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_GADGET_TARGET=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_MIDI_GADGET=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_NOKIA=m
-CONFIG_USB_G_ACM_MS=m
-CONFIG_USB_G_MULTI=m
-CONFIG_USB_G_MULTI_RNDIS=y
-CONFIG_USB_G_MULTI_CDC=y
-CONFIG_USB_G_HID=m
-# CONFIG_USB_G_DBGP is not set
-CONFIG_USB_G_WEBCAM=m
-CONFIG_USB_RAW_GADGET=m
-# end of USB Gadget precomposed configurations
-
-CONFIG_TYPEC=m
-CONFIG_TYPEC_TCPM=m
-CONFIG_TYPEC_TCPCI=m
-CONFIG_TYPEC_RT1711H=m
-CONFIG_TYPEC_TCPCI_MT6370=m
-CONFIG_TYPEC_MT6360=m
-CONFIG_TYPEC_TCPCI_MT6370=m
-CONFIG_TYPEC_TCPCI_MAXIM=m
-CONFIG_TYPEC_FUSB302=m
-CONFIG_TYPEC_UCSI=m
-CONFIG_UCSI_CCG=m
-CONFIG_UCSI_ACPI=m
-CONFIG_UCSI_STM32G0=m
-CONFIG_TYPEC_HD3SS3220=m
-CONFIG_TYPEC_TPS6598X=m
-CONFIG_TYPEC_ANX7411=m
-CONFIG_TYPEC_RT1719=m
-CONFIG_TYPEC_STUSB160X=m
-CONFIG_TYPEC_WUSB3801=m
-CONFIG_TYPEC_EXTCON=m
-
-#
-# USB Type-C Multiplexer/DeMultiplexer Switch support
-#
-CONFIG_TYPEC_MUX_PI3USB30532=m
-CONFIG_TYPEC_MUX_INTEL_PMC=m
-# end of USB Type-C Multiplexer/DeMultiplexer Switch support
-
-#
-# USB Type-C Alternate Mode drivers
-#
-CONFIG_TYPEC_DP_ALTMODE=m
-CONFIG_TYPEC_NVIDIA_ALTMODE=m
-# end of USB Type-C Alternate Mode drivers
-
-CONFIG_USB_ROLE_SWITCH=m
-CONFIG_USB_ROLES_INTEL_XHCI=m
-CONFIG_MMC=m
-CONFIG_MMC_BLOCK=m
-CONFIG_MMC_BLOCK_MINORS=8
-CONFIG_SDIO_UART=m
-# CONFIG_MMC_TEST is not set
-CONFIG_MMC_CRYPTO=y
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_SDHCI=m
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PCI=m
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI_ACPI=m
-CONFIG_MMC_SDHCI_PLTFM=m
-CONFIG_MMC_SDHCI_F_SDH30=m
-CONFIG_MMC_WBSD=m
-CONFIG_MMC_ALCOR=m
-CONFIG_MMC_TIFM_SD=m
-CONFIG_MMC_SPI=m
-CONFIG_MMC_SDRICOH_CS=m
-CONFIG_MMC_CB710=m
-CONFIG_MMC_VIA_SDMMC=m
-CONFIG_MMC_VUB300=m
-CONFIG_MMC_USHC=m
-CONFIG_MMC_USDHI6ROL0=m
-CONFIG_MMC_REALTEK_PCI=m
-CONFIG_MMC_REALTEK_USB=m
-CONFIG_MMC_CQHCI=m
-CONFIG_MMC_HSQ=m
-# CONFIG_MMC_TOSHIBA_PCI is not set
-CONFIG_MMC_MTK=m
-CONFIG_MMC_SDHCI_XENON=m
-CONFIG_MEMSTICK=m
-# CONFIG_MEMSTICK_DEBUG is not set
-
-#
-# MemoryStick drivers
-#
-# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
-CONFIG_MSPRO_BLOCK=m
-CONFIG_MS_BLOCK=m
-
-#
-# MemoryStick Host Controller Drivers
-#
-CONFIG_MEMSTICK_TIFM_MS=m
-CONFIG_MEMSTICK_JMICRON_38X=m
-CONFIG_MEMSTICK_R592=m
-CONFIG_MEMSTICK_REALTEK_PCI=m
-CONFIG_MEMSTICK_REALTEK_USB=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_RT4505=m
-CONFIG_LEDS_CLASS_FLASH=m
-CONFIG_LEDS_CLASS_MULTICOLOR=m
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-
-#
-# LED drivers
-#
-CONFIG_LEDS_APU=m
-CONFIG_LEDS_AS3645A=m
-CONFIG_LEDS_LM3530=m
-CONFIG_LEDS_LM3532=m
-CONFIG_LEDS_LM3533=m
-CONFIG_LEDS_LM3642=m
-CONFIG_LEDS_LM3601X=m
-CONFIG_LEDS_MT6323=m
-CONFIG_LEDS_PCA9532=m
-CONFIG_LEDS_PCA9532_GPIO=y
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_LP3944=m
-CONFIG_LEDS_LP3952=m
-CONFIG_LEDS_LP50XX=m
-CONFIG_LEDS_CLEVO_MAIL=m
-CONFIG_LEDS_PCA955X=m
-# CONFIG_LEDS_PCA955X_GPIO is not set
-CONFIG_LEDS_PCA963X=m
-CONFIG_LEDS_WM831X_STATUS=m
-CONFIG_LEDS_DA9052=m
-CONFIG_LEDS_DAC124S085=m
-CONFIG_LEDS_PWM=m
-CONFIG_LEDS_REGULATOR=m
-CONFIG_LEDS_BD2802=m
-CONFIG_LEDS_INTEL_SS4200=m
-CONFIG_LEDS_LT3593=m
-CONFIG_LEDS_MC13783=m
-CONFIG_LEDS_TCA6507=m
-CONFIG_LEDS_TLC591XX=m
-CONFIG_LEDS_LM355x=m
-# CONFIG_LEDS_OT200 is not set
-CONFIG_LEDS_MENF21BMC=m
-CONFIG_LEDS_IS31FL319X=m
-CONFIG_LEDS_RT8515=m
-
-#
-# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
-#
-CONFIG_LEDS_BLINKM=m
-CONFIG_LEDS_MLXCPLD=m
-CONFIG_LEDS_MLXREG=m
-CONFIG_LEDS_USER=m
-CONFIG_LEDS_NIC78BX=m
-CONFIG_LEDS_TI_LMU_COMMON=m
-CONFIG_LEDS_BCM63138=m
-CONFIG_LEDS_LM36274=m
-CONFIG_LEDS_TPS6105X=m
-CONFIG_LEDS_SGM3140=m
-CONFIG_LEDS_SIEMENS_SIMATIC_IPC=m
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_ONESHOT=m
-CONFIG_LEDS_TRIGGER_DISK=y
-# CONFIG_LEDS_TRIGGER_MTD is not set
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_LEDS_TRIGGER_BACKLIGHT=m
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_ACTIVITY=m
-CONFIG_LEDS_TRIGGER_GPIO=m
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-CONFIG_LEDS_TRIGGER_TRANSIENT=m
-CONFIG_LEDS_TRIGGER_CAMERA=m
-CONFIG_LEDS_TRIGGER_PANIC=y
-CONFIG_LEDS_TRIGGER_NETDEV=m
-CONFIG_LEDS_TRIGGER_PATTERN=m
-CONFIG_LEDS_TRIGGER_AUDIO=m
-CONFIG_LEDS_TRIGGER_TTY=m
-CONFIG_LEDS_BLINK=y
-CONFIG_LEDS_BLINK_LGM=m
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_A11Y_BRAILLE_CONSOLE=y
-
-#
-# Speakup console speech
-#
-CONFIG_SPEAKUP=m
-CONFIG_SPEAKUP_SERIALIO=y
-CONFIG_SPEAKUP_SYNTH_ACNTSA=m
-# CONFIG_SPEAKUP_SYNTH_ACNTPC is not set
-CONFIG_SPEAKUP_SYNTH_APOLLO=m
-CONFIG_SPEAKUP_SYNTH_AUDPTR=m
-CONFIG_SPEAKUP_SYNTH_BNS=m
-CONFIG_SPEAKUP_SYNTH_DECTLK=m
-CONFIG_SPEAKUP_SYNTH_DECEXT=m
-# CONFIG_SPEAKUP_SYNTH_DECPC is not set
-# CONFIG_SPEAKUP_SYNTH_DTLK is not set
-# CONFIG_SPEAKUP_SYNTH_KEYPC is not set
-CONFIG_SPEAKUP_SYNTH_LTLK=m
-CONFIG_SPEAKUP_SYNTH_SOFT=m
-CONFIG_SPEAKUP_SYNTH_SPKOUT=m
-CONFIG_SPEAKUP_SYNTH_TXPRT=m
-# CONFIG_SPEAKUP_SYNTH_DUMMY is not set
-# end of Speakup console speech
-
-CONFIG_INFINIBAND=m
-CONFIG_INFINIBAND_USER_MAD=m
-CONFIG_INFINIBAND_USER_ACCESS=m
-CONFIG_INFINIBAND_USER_MEM=y
-CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
-CONFIG_INFINIBAND_ADDR_TRANS=y
-CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
-CONFIG_INFINIBAND_MTHCA=m
-# CONFIG_INFINIBAND_MTHCA_DEBUG is not set
-CONFIG_INFINIBAND_CXGB4=m
-CONFIG_INFINIBAND_IRDMA=m
-CONFIG_INFINIBAND_I40IW=m
-CONFIG_MLX4_INFINIBAND=m
-CONFIG_MLX5_INFINIBAND=m
-CONFIG_INFINIBAND_OCRDMA=m
-CONFIG_INFINIBAND_VMWARE_PVRDMA=m
-CONFIG_INFINIBAND_USNIC=m
-CONFIG_RDMA_RXE=m
-CONFIG_RDMA_SIW=m
-CONFIG_INFINIBAND_IPOIB=m
-CONFIG_INFINIBAND_IPOIB_CM=y
-# CONFIG_INFINIBAND_IPOIB_DEBUG is not set
-# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set
-CONFIG_INFINIBAND_SRP=m
-CONFIG_INFINIBAND_SRPT=m
-CONFIG_INFINIBAND_ISER=m
-CONFIG_INFINIBAND_ISERT=m
-CONFIG_INFINIBAND_RTRS=m
-CONFIG_INFINIBAND_RTRS_CLIENT=m
-CONFIG_INFINIBAND_RTRS_SERVER=m
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EDAC=m
-CONFIG_EDAC_LEGACY_SYSFS=y
-# CONFIG_EDAC_DEBUG is not set
-CONFIG_EDAC_DECODE_MCE=m
-CONFIG_EDAC_GHES=y
-CONFIG_EDAC_AMD64=m
-CONFIG_EDAC_AMD64_ERROR_INJECTION=y
-# CONFIG_EDAC_AMD76X is not set
-# CONFIG_EDAC_E7XXX is not set
-CONFIG_EDAC_E752X=m
-# CONFIG_EDAC_I82875P is not set
-CONFIG_EDAC_I82975X=m
-CONFIG_EDAC_I3000=m
-CONFIG_EDAC_I3200=m
-CONFIG_EDAC_IE31200=m
-CONFIG_EDAC_X38=m
-CONFIG_EDAC_I5400=m
-CONFIG_EDAC_I7CORE=m
-# CONFIG_EDAC_I82860 is not set
-# CONFIG_EDAC_R82600 is not set
-CONFIG_EDAC_I5000=m
-CONFIG_EDAC_I5100=m
-CONFIG_EDAC_I7300=m
-CONFIG_RTC_LIB=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-CONFIG_RTC_SYSTOHC=y
-CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-CONFIG_RTC_NVMEM=y
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-CONFIG_RTC_DRV_88PM80X=m
-CONFIG_RTC_DRV_ABB5ZES3=m
-CONFIG_RTC_DRV_ABEOZ9=m
-CONFIG_RTC_DRV_ABX80X=m
-CONFIG_RTC_DRV_DS1307=m
-# CONFIG_RTC_DRV_DS1307_CENTURY is not set
-CONFIG_RTC_DRV_DS1374=m
-CONFIG_RTC_DRV_DS1374_WDT=y
-CONFIG_RTC_DRV_DS1672=m
-CONFIG_RTC_DRV_MAX6900=m
-CONFIG_RTC_DRV_MAX8907=m
-CONFIG_RTC_DRV_RS5C372=m
-CONFIG_RTC_DRV_ISL1208=m
-CONFIG_RTC_DRV_ISL12022=m
-CONFIG_RTC_DRV_X1205=m
-CONFIG_RTC_DRV_PCF8523=m
-CONFIG_RTC_DRV_PCF85063=m
-CONFIG_RTC_DRV_PCF85363=m
-CONFIG_RTC_DRV_PCF8563=m
-CONFIG_RTC_DRV_PCF8583=m
-CONFIG_RTC_DRV_M41T80=m
-CONFIG_RTC_DRV_M41T80_WDT=y
-CONFIG_RTC_DRV_BQ32K=m
-CONFIG_RTC_DRV_S35390A=m
-CONFIG_RTC_DRV_FM3130=m
-CONFIG_RTC_DRV_RX8010=m
-CONFIG_RTC_DRV_RX8581=m
-CONFIG_RTC_DRV_RX8025=m
-CONFIG_RTC_DRV_EM3027=m
-CONFIG_RTC_DRV_RV3028=m
-CONFIG_RTC_DRV_RV3032=m
-CONFIG_RTC_DRV_RV8803=m
-CONFIG_RTC_DRV_SD3078=m
-
-#
-# SPI RTC drivers
-#
-CONFIG_RTC_DRV_M41T93=m
-CONFIG_RTC_DRV_M41T94=m
-CONFIG_RTC_DRV_DS1302=m
-CONFIG_RTC_DRV_DS1305=m
-CONFIG_RTC_DRV_DS1343=m
-CONFIG_RTC_DRV_DS1347=m
-CONFIG_RTC_DRV_DS1390=m
-CONFIG_RTC_DRV_MAX6916=m
-CONFIG_RTC_DRV_R9701=m
-CONFIG_RTC_DRV_RX4581=m
-CONFIG_RTC_DRV_RX6110=m
-CONFIG_RTC_DRV_RS5C348=m
-CONFIG_RTC_DRV_MAX6902=m
-CONFIG_RTC_DRV_PCF2123=m
-CONFIG_RTC_DRV_MCP795=m
-CONFIG_RTC_I2C_AND_SPI=m
-
-#
-# SPI and I2C RTC drivers
-#
-CONFIG_RTC_DRV_DS3232=m
-CONFIG_RTC_DRV_DS3232_HWMON=y
-CONFIG_RTC_DRV_PCF2127=m
-CONFIG_RTC_DRV_RV3029C2=m
-CONFIG_RTC_DRV_RV3029_HWMON=y
-
-#
-# Platform RTC drivers
-#
-CONFIG_RTC_DRV_CMOS=y
-CONFIG_RTC_DRV_DS1286=m
-CONFIG_RTC_DRV_DS1511=m
-CONFIG_RTC_DRV_DS1553=m
-CONFIG_RTC_DRV_DS1685_FAMILY=m
-CONFIG_RTC_DRV_DS1685=y
-# CONFIG_RTC_DRV_DS1689 is not set
-# CONFIG_RTC_DRV_DS17285 is not set
-# CONFIG_RTC_DRV_DS17485 is not set
-# CONFIG_RTC_DRV_DS17885 is not set
-CONFIG_RTC_DRV_DS1742=m
-CONFIG_RTC_DRV_DS2404=m
-CONFIG_RTC_DRV_DA9052=m
-CONFIG_RTC_DRV_DA9063=m
-CONFIG_RTC_DRV_STK17TA8=m
-CONFIG_RTC_DRV_M48T86=m
-CONFIG_RTC_DRV_M48T35=m
-CONFIG_RTC_DRV_M48T59=m
-CONFIG_RTC_DRV_MSM6242=m
-CONFIG_RTC_DRV_BQ4802=m
-CONFIG_RTC_DRV_RP5C01=m
-CONFIG_RTC_DRV_V3020=m
-CONFIG_RTC_DRV_OPTEE=m
-CONFIG_RTC_DRV_WM831X=m
-CONFIG_RTC_DRV_PCF50633=m
-# CONFIG_RTC_DRV_CROS_EC is not set
-CONFIG_RTC_DRV_NTXEC=m
-
-#
-# on-CPU RTC drivers
-#
-CONFIG_RTC_DRV_FTRTC010=m
-CONFIG_RTC_DRV_PCAP=m
-CONFIG_RTC_DRV_MC13XXX=m
-CONFIG_RTC_DRV_MT6397=m
-
-#
-# HID Sensor RTC drivers
-#
-CONFIG_RTC_DRV_HID_SENSOR_TIME=m
-CONFIG_RTC_DRV_GOLDFISH=m
-CONFIG_RTC_DRV_WILCO_EC=m
-CONFIG_DMADEVICES=y
-# CONFIG_DMADEVICES_DEBUG is not set
-
-#
-# DMA Devices
-#
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DMA_ACPI=y
-CONFIG_ALTERA_MSGDMA=m
-CONFIG_INTEL_IDMA64=m
-# CONFIG_PCH_DMA is not set
-CONFIG_PLX_DMA=m
-CONFIG_AMD_PTDMA=m
-CONFIG_XILINX_ZYNQMP_DPDMA=m
-CONFIG_QCOM_HIDMA_MGMT=m
-CONFIG_QCOM_HIDMA=m
-CONFIG_DW_DMAC_CORE=y
-CONFIG_DW_DMAC=m
-CONFIG_DW_DMAC_PCI=y
-CONFIG_DW_EDMA=m
-CONFIG_DW_EDMA_PCIE=m
-CONFIG_HSU_DMA=y
-CONFIG_SF_PDMA=m
-CONFIG_INTEL_LDMA=y
-
-#
-# DMA Clients
-#
-CONFIG_ASYNC_TX_DMA=y
-# CONFIG_DMATEST is not set
-CONFIG_X86_PLATFORM_DRIVERS_DELL=y
-
-#
-# DMABUF options
-#
-CONFIG_SYNC_FILE=y
-# CONFIG_SW_SYNC is not set
-# CONFIG_UDMABUF is not set
-# CONFIG_DMABUF_MOVE_NOTIFY is not set
-# CONFIG_DMABUF_DEBUG is not set
-CONFIG_DMABUF_SELFTESTS=m
-# CONFIG_DMABUF_HEAPS is not set
-# end of DMABUF options
-
-CONFIG_AUXDISPLAY=y
-CONFIG_HD44780=m
-CONFIG_KS0108=m
-CONFIG_KS0108_PORT=0x378
-CONFIG_KS0108_DELAY=2
-CONFIG_CFAG12864B=m
-CONFIG_CFAG12864B_RATE=20
-CONFIG_IMG_ASCII_LCD=m
-CONFIG_HT16K33=m
-CONFIG_LCD2S=m
-CONFIG_PARPORT_PANEL=m
-CONFIG_PANEL_PARPORT=0
-CONFIG_PANEL_PROFILE=5
-# CONFIG_PANEL_CHANGE_MESSAGE is not set
-# CONFIG_CHARLCD_BL_OFF is not set
-# CONFIG_CHARLCD_BL_ON is not set
-CONFIG_CHARLCD_BL_FLASH=y
-CONFIG_PANEL=m
-CONFIG_CHARLCD=m
-CONFIG_UIO=m
-CONFIG_UIO_CIF=m
-CONFIG_UIO_PDRV_GENIRQ=m
-CONFIG_UIO_DMEM_GENIRQ=m
-CONFIG_UIO_AEC=m
-CONFIG_UIO_SERCOS3=m
-CONFIG_UIO_PCI_GENERIC=m
-CONFIG_UIO_NETX=m
-CONFIG_UIO_PRUSS=m
-CONFIG_UIO_MF624=m
-CONFIG_UIO_DFL=m
-CONFIG_UIO_HV_GENERIC=m
-CONFIG_VFIO_IOMMU_TYPE1=m
-CONFIG_VFIO_VIRQFD=m
-CONFIG_VFIO=m
-# CONFIG_VFIO_NOIOMMU is not set
-CONFIG_VFIO_PCI=m
-CONFIG_MLX5_VFIO_PCI=m
-CONFIG_HISI_ACC_VFIO_PCI=m
-CONFIG_VFIO_PCI_VGA=y
-CONFIG_VFIO_PCI_MMAP=y
-CONFIG_VFIO_PCI_INTX=y
-CONFIG_VFIO_PCI_IGD=y
-CONFIG_VFIO_MDEV=m
-CONFIG_VFIO_MDEV_DEVICE=m
-CONFIG_IRQ_BYPASS_MANAGER=m
-CONFIG_VIRT_DRIVERS=y
-CONFIG_VMGENID=m
-CONFIG_VBOXGUEST=m
-CONFIG_NITRO_ENCLAVES=m
-CONFIG_VIRTIO=m
-CONFIG_VIRTIO_MENU=y
-CONFIG_VIRTIO_PCI=m
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_VDPA=m
-CONFIG_VP_VDPA=m
-CONFIG_ALIBABA_ENI_VDPA=m
-CONFIG_VIRTIO_PMEM=m
-CONFIG_VIRTIO_BALLOON=m
-CONFIG_VIRTIO_MEM=m
-CONFIG_VIRTIO_INPUT=m
-CONFIG_VIRTIO_MMIO=m
-CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
-CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
-CONFIG_VDPA=m
-CONFIG_IFCVF=m
-CONFIG_MLX5_VDPA=y
-CONFIG_MLX5_VDPA_NET=m
-CONFIG_VHOST_IOTLB=m
-CONFIG_VHOST_RING=m
-CONFIG_VHOST=m
-CONFIG_VHOST_MENU=y
-CONFIG_VHOST_NET=m
-CONFIG_VHOST_SCSI=m
-CONFIG_VHOST_VSOCK=m
-CONFIG_VHOST_VDPA=m
-# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
-
-#
-# Microsoft Hyper-V guest support
-#
-CONFIG_HYPERV=m
-CONFIG_HYPERV_TIMER=y
-CONFIG_HYPERV_UTILS=m
-CONFIG_HYPERV_BALLOON=m
-# end of Microsoft Hyper-V guest support
-
-CONFIG_GREYBUS=m
-CONFIG_GREYBUS_ES2=m
-CONFIG_STAGING=y
-CONFIG_PRISM2_USB=m
-CONFIG_COMEDI=m
-CONFIG_COMEDI_TESTS=m
-CONFIG_COMEDI_TESTS_EXAMPLE=m
-CONFIG_COMEDI_TESTS_NI_ROUTES=m
-# CONFIG_COMEDI_DEBUG is not set
-CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
-CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
-CONFIG_COMEDI_MISC_DRIVERS=y
-CONFIG_COMEDI_BOND=m
-CONFIG_COMEDI_TEST=m
-CONFIG_COMEDI_PARPORT=m
-# CONFIG_COMEDI_SSV_DNP is not set
-CONFIG_COMEDI_ISA_DRIVERS=y
-CONFIG_COMEDI_PCL711=m
-CONFIG_COMEDI_PCL724=m
-CONFIG_COMEDI_PCL726=m
-CONFIG_COMEDI_PCL730=m
-CONFIG_COMEDI_PCL812=m
-CONFIG_COMEDI_PCL816=m
-CONFIG_COMEDI_PCL818=m
-CONFIG_COMEDI_PCM3724=m
-CONFIG_COMEDI_AMPLC_DIO200_ISA=m
-CONFIG_COMEDI_AMPLC_PC236_ISA=m
-CONFIG_COMEDI_AMPLC_PC263_ISA=m
-CONFIG_COMEDI_RTI800=m
-CONFIG_COMEDI_RTI802=m
-CONFIG_COMEDI_DAC02=m
-CONFIG_COMEDI_DAS16M1=m
-CONFIG_COMEDI_DAS08_ISA=m
-CONFIG_COMEDI_DAS16=m
-CONFIG_COMEDI_DAS800=m
-CONFIG_COMEDI_DAS1800=m
-CONFIG_COMEDI_DAS6402=m
-CONFIG_COMEDI_DT2801=m
-CONFIG_COMEDI_DT2811=m
-CONFIG_COMEDI_DT2814=m
-CONFIG_COMEDI_DT2815=m
-CONFIG_COMEDI_DT2817=m
-CONFIG_COMEDI_DT282X=m
-CONFIG_COMEDI_DMM32AT=m
-CONFIG_COMEDI_FL512=m
-CONFIG_COMEDI_AIO_AIO12_8=m
-CONFIG_COMEDI_AIO_IIRO_16=m
-CONFIG_COMEDI_II_PCI20KC=m
-CONFIG_COMEDI_C6XDIGIO=m
-CONFIG_COMEDI_MPC624=m
-CONFIG_COMEDI_ADQ12B=m
-CONFIG_COMEDI_NI_AT_A2150=m
-CONFIG_COMEDI_NI_AT_AO=m
-CONFIG_COMEDI_NI_ATMIO=m
-CONFIG_COMEDI_NI_ATMIO16D=m
-CONFIG_COMEDI_NI_LABPC_ISA=m
-CONFIG_COMEDI_PCMAD=m
-CONFIG_COMEDI_PCMDA12=m
-CONFIG_COMEDI_PCMMIO=m
-CONFIG_COMEDI_PCMUIO=m
-CONFIG_COMEDI_MULTIQ3=m
-CONFIG_COMEDI_S526=m
-CONFIG_COMEDI_PCI_DRIVERS=m
-CONFIG_COMEDI_8255_PCI=m
-CONFIG_COMEDI_ADDI_WATCHDOG=m
-CONFIG_COMEDI_ADDI_APCI_1032=m
-CONFIG_COMEDI_ADDI_APCI_1500=m
-CONFIG_COMEDI_ADDI_APCI_1516=m
-CONFIG_COMEDI_ADDI_APCI_1564=m
-CONFIG_COMEDI_ADDI_APCI_16XX=m
-CONFIG_COMEDI_ADDI_APCI_2032=m
-CONFIG_COMEDI_ADDI_APCI_2200=m
-CONFIG_COMEDI_ADDI_APCI_3120=m
-CONFIG_COMEDI_ADDI_APCI_3501=m
-CONFIG_COMEDI_ADDI_APCI_3XXX=m
-CONFIG_COMEDI_ADL_PCI6208=m
-CONFIG_COMEDI_ADL_PCI7X3X=m
-CONFIG_COMEDI_ADL_PCI8164=m
-CONFIG_COMEDI_ADL_PCI9111=m
-CONFIG_COMEDI_ADL_PCI9118=m
-CONFIG_COMEDI_ADV_PCI1710=m
-CONFIG_COMEDI_ADV_PCI1720=m
-CONFIG_COMEDI_ADV_PCI1723=m
-CONFIG_COMEDI_ADV_PCI1724=m
-CONFIG_COMEDI_ADV_PCI1760=m
-CONFIG_COMEDI_ADV_PCI_DIO=m
-CONFIG_COMEDI_AMPLC_DIO200_PCI=m
-CONFIG_COMEDI_AMPLC_PC236_PCI=m
-CONFIG_COMEDI_AMPLC_PC263_PCI=m
-CONFIG_COMEDI_AMPLC_PCI224=m
-CONFIG_COMEDI_AMPLC_PCI230=m
-CONFIG_COMEDI_CONTEC_PCI_DIO=m
-CONFIG_COMEDI_DAS08_PCI=m
-CONFIG_COMEDI_DT3000=m
-CONFIG_COMEDI_DYNA_PCI10XX=m
-CONFIG_COMEDI_GSC_HPDI=m
-CONFIG_COMEDI_MF6X4=m
-CONFIG_COMEDI_ICP_MULTI=m
-CONFIG_COMEDI_DAQBOARD2000=m
-CONFIG_COMEDI_JR3_PCI=m
-CONFIG_COMEDI_KE_COUNTER=m
-CONFIG_COMEDI_CB_PCIDAS64=m
-CONFIG_COMEDI_CB_PCIDAS=m
-CONFIG_COMEDI_CB_PCIDDA=m
-CONFIG_COMEDI_CB_PCIMDAS=m
-CONFIG_COMEDI_CB_PCIMDDA=m
-CONFIG_COMEDI_ME4000=m
-CONFIG_COMEDI_ME_DAQ=m
-CONFIG_COMEDI_NI_6527=m
-CONFIG_COMEDI_NI_65XX=m
-CONFIG_COMEDI_NI_660X=m
-CONFIG_COMEDI_NI_670X=m
-CONFIG_COMEDI_NI_LABPC_PCI=m
-CONFIG_COMEDI_NI_PCIDIO=m
-CONFIG_COMEDI_NI_PCIMIO=m
-CONFIG_COMEDI_RTD520=m
-CONFIG_COMEDI_S626=m
-CONFIG_COMEDI_MITE=m
-CONFIG_COMEDI_NI_TIOCMD=m
-CONFIG_COMEDI_PCMCIA_DRIVERS=m
-CONFIG_COMEDI_CB_DAS16_CS=m
-CONFIG_COMEDI_DAS08_CS=m
-CONFIG_COMEDI_NI_DAQ_700_CS=m
-CONFIG_COMEDI_NI_DAQ_DIO24_CS=m
-CONFIG_COMEDI_NI_LABPC_CS=m
-CONFIG_COMEDI_NI_MIO_CS=m
-CONFIG_COMEDI_QUATECH_DAQP_CS=m
-CONFIG_COMEDI_USB_DRIVERS=m
-CONFIG_COMEDI_DT9812=m
-CONFIG_COMEDI_NI_USB6501=m
-CONFIG_COMEDI_USBDUX=m
-CONFIG_COMEDI_USBDUXFAST=m
-CONFIG_COMEDI_USBDUXSIGMA=m
-CONFIG_COMEDI_VMK80XX=m
-CONFIG_COMEDI_8254=m
-CONFIG_COMEDI_8255=m
-CONFIG_COMEDI_8255_SA=m
-CONFIG_COMEDI_KCOMEDILIB=m
-CONFIG_COMEDI_AMPLC_DIO200=m
-CONFIG_COMEDI_AMPLC_PC236=m
-CONFIG_COMEDI_DAS08=m
-CONFIG_COMEDI_ISADMA=m
-CONFIG_COMEDI_NI_LABPC=m
-CONFIG_COMEDI_NI_LABPC_ISADMA=m
-CONFIG_COMEDI_NI_TIO=m
-CONFIG_COMEDI_NI_ROUTING=m
-CONFIG_RTL8192U=m
-CONFIG_RTLLIB=m
-CONFIG_RTLLIB_CRYPTO_CCMP=m
-CONFIG_RTLLIB_CRYPTO_TKIP=m
-CONFIG_RTLLIB_CRYPTO_WEP=m
-CONFIG_RTL8192E=m
-CONFIG_RTL8723BS=m
-CONFIG_R8712U=m
-CONFIG_R8188EU=m
-CONFIG_88EU_AP_MODE=y
-CONFIG_RTS5208=m
-CONFIG_VT6655=m
-CONFIG_VT6656=m
-
-#
-# IIO staging drivers
-#
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16203=m
-CONFIG_ADIS16240=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD7816=m
-CONFIG_AD7280=m
-# end of Analog to digital converters
-
-#
-# Analog digital bi-direction converters
-#
-CONFIG_ADT7316=m
-CONFIG_ADT7316_SPI=m
-CONFIG_ADT7316_I2C=m
-# end of Analog digital bi-direction converters
-
-#
-# Capacitance to digital converters
-#
-CONFIG_AD7150=m
-CONFIG_AD7746=m
-# end of Capacitance to digital converters
-
-#
-# Direct Digital Synthesis
-#
-CONFIG_AD9832=m
-CONFIG_AD9834=m
-# end of Direct Digital Synthesis
-
-#
-# Network Analyzer, Impedance Converters
-#
-CONFIG_AD5933=m
-# end of Network Analyzer, Impedance Converters
-
-#
-# Active energy metering IC
-#
-CONFIG_ADE7854=m
-CONFIG_ADE7854_I2C=m
-CONFIG_ADE7854_SPI=m
-# end of Active energy metering IC
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S1210=m
-# end of Resolver to digital converters
-# end of IIO staging drivers
-
-CONFIG_FB_SM750=m
-CONFIG_STAGING_MEDIA=y
-CONFIG_INTEL_ATOMISP=y
-CONFIG_VIDEO_ATOMISP=m
-CONFIG_VIDEO_ATOMISP_ISP2401=y
-CONFIG_VIDEO_ATOMISP_OV2722=m
-CONFIG_VIDEO_ATOMISP_GC2235=m
-CONFIG_VIDEO_ATOMISP_MSRLIST_HELPER=m
-CONFIG_VIDEO_ATOMISP_MT9M114=m
-CONFIG_VIDEO_ATOMISP_GC0310=m
-CONFIG_VIDEO_ATOMISP_OV2680=m
-CONFIG_VIDEO_ATOMISP_OV5693=m
-CONFIG_VIDEO_ATOMISP_LM3554=m
-CONFIG_VIDEO_ZORAN=m
-CONFIG_VIDEO_ZORAN_DC30=y
-CONFIG_VIDEO_ZORAN_ZR36060=y
-CONFIG_VIDEO_ZORAN_BUZ=y
-CONFIG_VIDEO_ZORAN_DC10=y
-CONFIG_VIDEO_ZORAN_LML33=y
-CONFIG_VIDEO_ZORAN_LML33R10=y
-CONFIG_VIDEO_ZORAN_AVS6EYES=y
-CONFIG_VIDEO_IPU3_IMGU=m
-
-#
-# Android
-#
-# end of Android
-
-CONFIG_LTE_GDM724X=m
-CONFIG_FIREWIRE_SERIAL=m
-CONFIG_FWTTY_MAX_TOTAL_PORTS=64
-CONFIG_FWTTY_MAX_CARD_PORTS=32
-CONFIG_GS_FPGABOOT=m
-CONFIG_UNISYSSPAR=y
-CONFIG_FB_TFT=m
-CONFIG_FB_TFT_AGM1264K_FL=m
-CONFIG_FB_TFT_BD663474=m
-CONFIG_FB_TFT_HX8340BN=m
-CONFIG_FB_TFT_HX8347D=m
-CONFIG_FB_TFT_HX8353D=m
-CONFIG_FB_TFT_HX8357D=m
-CONFIG_FB_TFT_ILI9163=m
-CONFIG_FB_TFT_ILI9320=m
-CONFIG_FB_TFT_ILI9325=m
-CONFIG_FB_TFT_ILI9340=m
-CONFIG_FB_TFT_ILI9341=m
-CONFIG_FB_TFT_ILI9481=m
-CONFIG_FB_TFT_ILI9486=m
-CONFIG_FB_TFT_PCD8544=m
-CONFIG_FB_TFT_RA8875=m
-CONFIG_FB_TFT_S6D02A1=m
-CONFIG_FB_TFT_S6D1121=m
-CONFIG_FB_TFT_SEPS525=m
-CONFIG_FB_TFT_SH1106=m
-CONFIG_FB_TFT_SSD1289=m
-CONFIG_FB_TFT_SSD1305=m
-CONFIG_FB_TFT_SSD1306=m
-CONFIG_FB_TFT_SSD1331=m
-CONFIG_FB_TFT_SSD1351=m
-# CONFIG_FB_TFT_ST7735R is not set
-CONFIG_FB_TFT_ST7789V=m
-CONFIG_FB_TFT_TINYLCD=m
-CONFIG_FB_TFT_TLS8204=m
-CONFIG_FB_TFT_UC1611=m
-CONFIG_FB_TFT_UC1701=m
-CONFIG_FB_TFT_UPD161704=m
-CONFIG_FB_TFT_WATTEROTT=m
-CONFIG_MOST_COMPONENTS=m
-CONFIG_MOST_NET=m
-CONFIG_MOST_SOUND=m
-CONFIG_MOST_VIDEO=m
-CONFIG_MOST_I2C=m
-CONFIG_KS7010=m
-CONFIG_GREYBUS_AUDIO=m
-CONFIG_GREYBUS_AUDIO_APB_CODEC=m
-CONFIG_GREYBUS_BOOTROM=m
-CONFIG_GREYBUS_FIRMWARE=m
-CONFIG_GREYBUS_HID=m
-CONFIG_GREYBUS_LIGHT=m
-CONFIG_GREYBUS_LOG=m
-CONFIG_GREYBUS_LOOPBACK=m
-CONFIG_GREYBUS_POWER=m
-CONFIG_GREYBUS_RAW=m
-CONFIG_GREYBUS_VIBRATOR=m
-CONFIG_GREYBUS_BRIDGED_PHY=m
-CONFIG_GREYBUS_GPIO=m
-CONFIG_GREYBUS_I2C=m
-CONFIG_GREYBUS_PWM=m
-CONFIG_GREYBUS_SDIO=m
-CONFIG_GREYBUS_SPI=m
-CONFIG_GREYBUS_UART=m
-CONFIG_GREYBUS_USB=m
-CONFIG_PI433=m
-
-#
-# Gasket devices
-#
-# end of Gasket devices
-
-CONFIG_FIELDBUS_DEV=m
-CONFIG_KPC2000=y
-CONFIG_KPC2000_CORE=m
-CONFIG_KPC2000_SPI=m
-CONFIG_KPC2000_I2C=m
-CONFIG_KPC2000_DMA=m
-CONFIG_QLGE=m
-CONFIG_WFX=m
-CONFIG_RTL8723CS=m
-CONFIG_SPMI_HISI3670=m
-CONFIG_RTL8723CS=m
-CONFIG_X86_PLATFORM_DEVICES=y
-CONFIG_ACPI_WMI=m
-CONFIG_WMI_BMOF=m
-CONFIG_ALIENWARE_WMI=m
-CONFIG_HUAWEI_WMI=m
-CONFIG_INTEL_WMI_SBL_FW_UPDATE=m
-CONFIG_INTEL_WMI_THUNDERBOLT=m
-CONFIG_MXM_WMI=m
-CONFIG_PEAQ_WMI=m
-CONFIG_NVIDIA_WMI_EC_BACKLIGHT=m
-CONFIG_XIAOMI_WMI=m
-CONFIG_GIGABYTE_WMI=m
-CONFIG_YOGABOOK_WMI=m
-CONFIG_ACERHDF=m
-CONFIG_ACER_WIRELESS=m
-CONFIG_ACER_WMI=m
-CONFIG_AMD_PMF=m
-CONFIG_AMD_PMC=m
-CONFIG_AMD_HSMP=m
-CONFIG_ADV_SWBUTTON=m
-CONFIG_APPLE_GMUX=m
-CONFIG_ASUS_LAPTOP=m
-CONFIG_ASUS_WIRELESS=m
-CONFIG_ASUS_WMI=m
-CONFIG_ASUS_NB_WMI=m
-CONFIG_ASUS_TF103C_DOCK=m
-CONFIG_MERAKI_MX100=m
-CONFIG_EEEPC_LAPTOP=m
-CONFIG_EEEPC_WMI=m
-CONFIG_DCDBAS=m
-CONFIG_DELL_SMBIOS=m
-CONFIG_DELL_SMBIOS_WMI=y
-CONFIG_DELL_SMBIOS_SMM=y
-CONFIG_DELL_LAPTOP=m
-CONFIG_DELL_RBTN=m
-CONFIG_DELL_RBU=m
-CONFIG_DELL_SMO8800=m
-CONFIG_DELL_WMI=m
-CONFIG_DELL_WMI_PRIVACY=y
-CONFIG_DELL_WMI_SYSMAN=m
-CONFIG_DELL_WMI_DESCRIPTOR=m
-CONFIG_DELL_WMI_AIO=m
-CONFIG_DELL_WMI_LED=m
-CONFIG_AMILO_RFKILL=m
-CONFIG_FUJITSU_LAPTOP=m
-CONFIG_FUJITSU_TABLET=m
-CONFIG_GPD_POCKET_FAN=m
-CONFIG_HP_ACCEL=m
-CONFIG_WIRELESS_HOTKEY=m
-CONFIG_HP_WIRELESS=m
-CONFIG_HP_WMI=m
-# CONFIG_TC1100_WMI is not set
-CONFIG_IBM_RTL=m
-CONFIG_IDEAPAD_LAPTOP=m
-CONFIG_SENSORS_HDAPS=m
-CONFIG_THINKPAD_ACPI=m
-CONFIG_THINKPAD_ACPI_ALSA_SUPPORT=y
-# CONFIG_THINKPAD_ACPI_DEBUGFACILITIES is not set
-# CONFIG_THINKPAD_ACPI_DEBUG is not set
-# CONFIG_THINKPAD_ACPI_UNSAFE_LEDS is not set
-CONFIG_THINKPAD_ACPI_VIDEO=y
-CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y
-CONFIG_THINKPAD_LMI=m
-CONFIG_INTEL_ATOMISP2_LED=m
-CONFIG_INTEL_SAR_INT1092=m
-CONFIG_INTEL_SKL_INT3472=m
-CONFIG_INTEL_CHT_INT33FE=m
-CONFIG_INTEL_HID_EVENT=m
-CONFIG_INTEL_INT0002_VGPIO=m
-CONFIG_INTEL_HFI_THERMAL=y
-CONFIG_INTEL_MENLOW=m
-CONFIG_INTEL_OAKTRAIL=m
-CONFIG_INTEL_VBTN=m
-CONFIG_SURFACE3_WMI=m
-CONFIG_SURFACE_KBD=m
-CONFIG_SURFACE_3_BUTTON=m
-CONFIG_SURFACE_3_POWER_OPREGION=m
-CONFIG_SURFACE_ACPI_NOTIFY=m
-CONFIG_SURFACE_AGGREGATOR_CDEV=m
-CONFIG_SURFACE_AGGREGATOR_HUB=m
-CONFIG_SURFACE_AGGREGATOR_REGISTRY=m
-CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m
-CONFIG_SURFACE_DTX=m
-CONFIG_SURFACE_PRO3_BUTTON=m
-CONFIG_MSI_LAPTOP=m
-CONFIG_MSI_WMI=m
-CONFIG_PCENGINES_APU2=m
-CONFIG_BARCO_P50_GPIO=m
-CONFIG_SAMSUNG_LAPTOP=m
-CONFIG_SAMSUNG_Q10=m
-CONFIG_ACPI_TOSHIBA=m
-CONFIG_TOSHIBA_BT_RFKILL=m
-CONFIG_TOSHIBA_HAPS=m
-CONFIG_TOSHIBA_WMI=m
-CONFIG_ACPI_CMPC=m
-CONFIG_COMPAL_LAPTOP=m
-CONFIG_LG_LAPTOP=m
-CONFIG_PANASONIC_LAPTOP=m
-CONFIG_SONY_LAPTOP=m
-CONFIG_SONYPI_COMPAT=y
-CONFIG_SYSTEM76_ACPI=m
-CONFIG_TOPSTAR_LAPTOP=m
-CONFIG_SERIAL_MULTI_INSTANTIATE=m
-CONFIG_I2C_MULTI_INSTANTIATE=m
-CONFIG_MLX_PLATFORM=m
-CONFIG_X86_ANDROID_TABLETS=m
-CONFIG_INTEL_IPS=m
-CONFIG_INTEL_RST=m
-CONFIG_INTEL_SDSI=m
-CONFIG_INTEL_SMARTCONNECT=m
-CONFIG_INTEL_VSEC=m
-CONFIG_INTEL_BXTWC_PMIC_TMU=m
-CONFIG_INTEL_CHTWC_INT33FE=m
-CONFIG_INTEL_CHTDC_TI_PWRBTN=m
-CONFIG_INTEL_ISHTP_ECLITE=m
-CONFIG_INTEL_MID_POWER_BUTTON=m
-CONFIG_INTEL_MRFLD_PWRBTN=m
-CONFIG_INTEL_PMC_CORE=y
-CONFIG_INTEL_PMT_CLASS=m
-CONFIG_INTEL_PMT_TELEMETRY=m
-CONFIG_INTEL_PMT_CRASHLOG=m
-CONFIG_INTEL_PUNIT_IPC=m
-CONFIG_INTEL_SCU_IPC=y
-CONFIG_SIEMENS_SIMATIC_IPC=m
-CONFIG_INTEL_SCU=y
-CONFIG_INTEL_SCU_PCI=y
-CONFIG_INTEL_SCU_PLATFORM=m
-CONFIG_INTEL_SCU_IPC_UTIL=m
-CONFIG_ICST=y
-CONFIG_CLK_SP810=y
-CONFIG_PMC_ATOM=y
-CONFIG_CHROME_PLATFORMS=y
-CONFIG_CHROMEOS_LAPTOP=m
-CONFIG_CHROMEOS_PSTORE=m
-CONFIG_CHROMEOS_TBMC=m
-CONFIG_CROS_EC=m
-CONFIG_CROS_EC_I2C=m
-CONFIG_CROS_EC_SPI=m
-CONFIG_CROS_EC_LPC=m
-CONFIG_CROS_EC_PROTO=y
-CONFIG_CROS_KBD_LED_BACKLIGHT=m
-CONFIG_CROS_EC_CHARDEV=m
-CONFIG_CROS_EC_LIGHTBAR=m
-CONFIG_CROS_EC_DEBUGFS=m
-CONFIG_CROS_EC_SENSORHUB=m
-CONFIG_CROS_EC_SYSFS=m
-CONFIG_CROS_EC_TYPEC=m
-CONFIG_CROS_USBPD_LOGGER=m
-CONFIG_CROS_USBPD_NOTIFY=m
-CONFIG_CHROMEOS_PRIVACY_SCREEN=m
-CONFIG_CROS_TYPEC_SWITCH=m
-CONFIG_WILCO_EC=m
-CONFIG_WILCO_EC_DEBUGFS=m
-CONFIG_WILCO_EC_EVENTS=m
-CONFIG_WILCO_EC_TELEMETRY=m
-CONFIG_MELLANOX_PLATFORM=y
-CONFIG_MLXREG_HOTPLUG=m
-CONFIG_MLXREG_IO=m
-CONFIG_MLXREG_LC=m
-CONFIG_HAVE_CLK=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_WM831X=m
-CONFIG_LMK04832=m
-CONFIG_COMMON_CLK_APPLE_NCO=m
-CONFIG_COMMON_CLK_MAX9485=m
-CONFIG_COMMON_CLK_SI5341=m
-CONFIG_COMMON_CLK_SI5351=m
-CONFIG_COMMON_CLK_SI544=m
-CONFIG_COMMON_CLK_CDCE706=m
-CONFIG_COMMON_CLK_TPS68470=m
-CONFIG_COMMON_CLK_CS2000_CP=m
-CONFIG_COMMON_CLK_PWM=m
-CONFIG_COMMON_CLK_RS9_PCIE=m
-CONFIG_HWSPINLOCK=y
-
-#
-# Clock Source drivers
-#
-CONFIG_CLKSRC_I8253=y
-CONFIG_CLKEVT_I8253=y
-CONFIG_I8253_LOCK=y
-CONFIG_CLKBLD_I8253=y
-# end of Clock Source drivers
-
-CONFIG_MAILBOX=y
-CONFIG_PCC=y
-CONFIG_ALTERA_MBOX=m
-CONFIG_IOMMU_IOVA=y
-CONFIG_IOASID=y
-CONFIG_IOMMU_API=y
-CONFIG_IOMMU_SUPPORT=y
-
-#
-# Generic IOMMU Pagetable Support
-#
-# end of Generic IOMMU Pagetable Support
-
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_DMAR_TABLE=y
-CONFIG_INTEL_IOMMU=y
-# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set
-CONFIG_INTEL_IOMMU_FLOPPY_WA=y
-# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set
-CONFIG_HYPERV_IOMMU=y
-CONFIG_VIRTIO_IOMMU=m
-
-#
-# Remoteproc drivers
-#
-# CONFIG_REMOTEPROC is not set
-# end of Remoteproc drivers
-
-#
-# Rpmsg drivers
-#
-CONFIG_RPMSG=m
-CONFIG_RPMSG_CHAR=m
-CONFIG_RPMSG_CTRL=m
-CONFIG_RPMSG_QCOM_GLINK=m
-CONFIG_RPMSG_QCOM_GLINK_RPM=m
-CONFIG_RPMSG_VIRTIO=m
-# end of Rpmsg drivers
-
-CONFIG_SOUNDWIRE=y
-
-#
-# SoundWire Devices
-#
-CONFIG_SOUNDWIRE_CADENCE=m
-CONFIG_SOUNDWIRE_INTEL=m
-CONFIG_SOUNDWIRE_QCOM=m
-CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=m
-
-#
-# SOC (System On Chip) specific Drivers
-#
-
-#
-# Amlogic SoC drivers
-#
-# end of Amlogic SoC drivers
-
-#
-# Aspeed SoC drivers
-#
-# end of Aspeed SoC drivers
-
-#
-# Broadcom SoC drivers
-#
-# end of Broadcom SoC drivers
-
-#
-# NXP/Freescale QorIQ SoC drivers
-#
-# end of NXP/Freescale QorIQ SoC drivers
-
-#
-# i.MX SoC drivers
-#
-# end of i.MX SoC drivers
-
-#
-# Qualcomm SoC drivers
-#
-CONFIG_QCOM_QMI_HELPERS=m
-# end of Qualcomm SoC drivers
-
-# CONFIG_SOC_TI is not set
-
-#
-# Xilinx SoC drivers
-#
-# CONFIG_XILINX_VCU is not set
-# end of Xilinx SoC drivers
-# end of SOC (System On Chip) specific Drivers
-
-CONFIG_PM_DEVFREQ=y
-
-#
-# DEVFREQ Governors
-#
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_PERFORMANCE=y
-CONFIG_DEVFREQ_GOV_POWERSAVE=y
-CONFIG_DEVFREQ_GOV_USERSPACE=y
-CONFIG_DEVFREQ_GOV_PASSIVE=m
-
-#
-# DEVFREQ Drivers
-#
-CONFIG_PM_DEVFREQ_EVENT=y
-CONFIG_EXTCON=y
-
-#
-# Extcon Device Drivers
-#
-CONFIG_EXTCON_ADC_JACK=m
-CONFIG_EXTCON_ARIZONA=m
-CONFIG_EXTCON_AXP288=m
-CONFIG_EXTCON_FSA9480=m
-CONFIG_EXTCON_GPIO=m
-CONFIG_EXTCON_INTEL_INT3496=m
-CONFIG_EXTCON_INTEL_MRFLD=m
-CONFIG_EXTCON_MAX14577=m
-CONFIG_EXTCON_MAX3355=m
-CONFIG_EXTCON_MAX77693=m
-CONFIG_EXTCON_PTN5150=m
-CONFIG_EXTCON_RT8973A=m
-CONFIG_EXTCON_SM5502=m
-CONFIG_EXTCON_USB_GPIO=m
-CONFIG_EXTCON_USBC_CROS_EC=m
-CONFIG_EXTCON_USBC_TUSB320=m
-CONFIG_MEMORY=y
-CONFIG_FPGA_DFL_EMIF=m
-CONFIG_IIO=m
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_BUFFER_CB=m
-CONFIG_IIO_BUFFER_DMA=m
-CONFIG_IIO_BUFFER_DMAENGINE=m
-CONFIG_IIO_BUFFER_HW_CONSUMER=m
-CONFIG_IIO_KFIFO_BUF=m
-CONFIG_IIO_TRIGGERED_BUFFER=m
-CONFIG_IIO_CONFIGFS=m
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
-CONFIG_IIO_SW_DEVICE=m
-CONFIG_IIO_SW_TRIGGER=m
-CONFIG_IIO_TRIGGERED_EVENT=m
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16201=m
-CONFIG_ADIS16209=m
-CONFIG_ADXL372=m
-CONFIG_ADXL372_SPI=m
-CONFIG_ADXL372_I2C=m
-CONFIG_BMA220=m
-CONFIG_BMA400=m
-CONFIG_BMA400_I2C=m
-CONFIG_BMA400_SPI=m
-CONFIG_BMC150_ACCEL=m
-CONFIG_BMI088_ACCEL=m
-CONFIG_TI_ADS131E08=m
-CONFIG_BMC150_ACCEL_I2C=m
-CONFIG_BMC150_ACCEL_SPI=m
-CONFIG_DA280=m
-CONFIG_DA311=m
-CONFIG_DMARD09=m
-CONFIG_DMARD10=m
-CONFIG_FXLS8962AF_SPI=m
-CONFIG_FXLS8962AF_I2C=m
-CONFIG_HID_SENSOR_ACCEL_3D=m
-CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
-CONFIG_IIO_ST_ACCEL_3AXIS=m
-CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
-CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
-CONFIG_KXSD9=m
-CONFIG_KXSD9_SPI=m
-CONFIG_KXSD9_I2C=m
-CONFIG_KXCJK1013=m
-CONFIG_MC3230=m
-CONFIG_MMA7455=m
-CONFIG_MMA7455_I2C=m
-CONFIG_MMA7455_SPI=m
-CONFIG_MMA7660=m
-CONFIG_MMA8452=m
-CONFIG_MMA9551_CORE=m
-CONFIG_MMA9551=m
-CONFIG_MMA9553=m
-CONFIG_MSA311=m
-CONFIG_MXC4005=m
-CONFIG_MXC6255=m
-CONFIG_SCA3000=m
-CONFIG_SCA3300=m
-CONFIG_STK8312=m
-CONFIG_STK8BA50=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD_SIGMA_DELTA=m
-CONFIG_AD7091R5=m
-CONFIG_AD7124=m
-CONFIG_AD7192=m
-CONFIG_AD7266=m
-CONFIG_AD7291=m
-CONFIG_AD7292=m
-CONFIG_AD7298=m
-CONFIG_AD7476=m
-CONFIG_AD7606=m
-CONFIG_AD7606_IFACE_PARALLEL=m
-CONFIG_AD7606_IFACE_SPI=m
-CONFIG_AD7766=m
-CONFIG_AD7768_1=m
-CONFIG_AD7780=m
-CONFIG_AD7791=m
-CONFIG_AD7793=m
-CONFIG_AD7887=m
-CONFIG_AD7923=m
-CONFIG_AD7949=m
-CONFIG_AD799X=m
-CONFIG_AD9467=m
-CONFIG_ADI_AXI_ADC=m
-CONFIG_AXP20X_ADC=m
-CONFIG_AXP288_ADC=m
-CONFIG_CC10001_ADC=m
-CONFIG_DA9150_GPADC=m
-CONFIG_DLN2_ADC=m
-CONFIG_ENVELOPE_DETECTOR=m
-CONFIG_HI8435=m
-CONFIG_HX711=m
-CONFIG_INA2XX_ADC=m
-CONFIG_INTEL_MRFLD_ADC=m
-CONFIG_LTC2471=m
-CONFIG_LTC2485=m
-CONFIG_LTC2496=m
-CONFIG_LTC2497=m
-CONFIG_MAX1027=m
-CONFIG_MAX11100=m
-CONFIG_MAX1118=m
-CONFIG_MAX11205=m
-CONFIG_MAX1241=m
-CONFIG_MAX1363=m
-CONFIG_MAX9611=m
-CONFIG_MCP320X=m
-CONFIG_MCP3422=m
-CONFIG_MCP3911=m
-CONFIG_MEDIATEK_MT6360_ADC=m
-CONFIG_MEN_Z188_ADC=m
-CONFIG_MP2629_ADC=m
-CONFIG_NAU7802=m
-CONFIG_QCOM_VADC_COMMON=m
-CONFIG_QCOM_SPMI_IADC=m
-CONFIG_QCOM_SPMI_VADC=m
-CONFIG_QCOM_SPMI_ADC5=m
-CONFIG_RICHTEK_RTQ6056=m
-CONFIG_SD_ADC_MODULATOR=m
-CONFIG_TI_ADC081C=m
-CONFIG_TI_ADC0832=m
-CONFIG_TI_ADC084S021=m
-CONFIG_TI_ADC12138=m
-CONFIG_TI_ADC108S102=m
-CONFIG_TI_ADC128S052=m
-CONFIG_TI_ADC161S626=m
-CONFIG_TI_ADS1015=m
-CONFIG_TI_ADS7950=m
-CONFIG_TI_ADS8344=m
-CONFIG_TI_ADS8688=m
-CONFIG_TI_ADS124S08=m
-CONFIG_TI_AM335X_ADC=m
-CONFIG_TI_TLC4541=m
-CONFIG_TI_TSC2046=m
-CONFIG_VF610_ADC=m
-CONFIG_VIPERBOARD_ADC=m
-CONFIG_XILINX_XADC=m
-CONFIG_XILINX_AMS=m
-CONFIG_IIO_SCMI=m
-CONFIG_CROS_EC_MKBP_PROXIMITY=m
-# end of Analog to digital converters
-
-#
-# Analog Front Ends
-#
-# end of Analog Front Ends
-
-#
-# Amplifiers
-#
-CONFIG_AD8366=m
-CONFIG_ADA4250=m
-CONFIG_HMC425=m
-# end of Amplifiers
-
-#
-# Chemical Sensors
-#
-CONFIG_ATLAS_PH_SENSOR=m
-CONFIG_ATLAS_EZO_SENSOR=m
-CONFIG_BME680=m
-CONFIG_BME680_I2C=m
-CONFIG_BME680_SPI=m
-CONFIG_CCS811=m
-CONFIG_IAQCORE=m
-CONFIG_PMS7003=m
-CONFIG_SCD30_CORE=m
-CONFIG_SCD30_I2C=m
-CONFIG_SCD30_SERIAL=m
-CONFIG_SENSIRION_SGP30=m
-CONFIG_SPS30_I2C=m
-CONFIG_SPS30_SERIAL=m
-CONFIG_SPS30=m
-CONFIG_VZ89X=m
-# end of Chemical Sensors
-
-CONFIG_IIO_CROS_EC_SENSORS_CORE=m
-CONFIG_IIO_CROS_EC_SENSORS=m
-CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m
-
-#
-# Hid Sensor IIO Common
-#
-CONFIG_HID_SENSOR_IIO_COMMON=m
-CONFIG_HID_SENSOR_IIO_TRIGGER=m
-# end of Hid Sensor IIO Common
-
-CONFIG_IIO_MS_SENSORS_I2C=m
-
-#
-# SSP Sensor Common
-#
-CONFIG_IIO_SSP_SENSORS_COMMONS=m
-CONFIG_IIO_SSP_SENSORHUB=m
-# end of SSP Sensor Common
-
-CONFIG_IIO_ST_SENSORS_I2C=m
-CONFIG_IIO_ST_SENSORS_SPI=m
-CONFIG_IIO_ST_SENSORS_CORE=m
-
-#
-# Digital to analog converters
-#
-CONFIG_AD5064=m
-CONFIG_AD5360=m
-CONFIG_AD5380=m
-CONFIG_AD5421=m
-CONFIG_AD5446=m
-CONFIG_AD5449=m
-CONFIG_AD5592R_BASE=m
-CONFIG_AD5592R=m
-CONFIG_AD5593R=m
-CONFIG_AD5504=m
-CONFIG_AD5624R_SPI=m
-CONFIG_LTC2688=m
-CONFIG_AD5686=m
-CONFIG_AD5686_SPI=m
-CONFIG_AD5696_I2C=m
-CONFIG_AD5755=m
-CONFIG_AD5758=m
-CONFIG_AD5761=m
-CONFIG_AD5764=m
-CONFIG_AD5766=m
-CONFIG_AD5770R=m
-CONFIG_AD5791=m
-CONFIG_AD7303=m
-CONFIG_AD8801=m
-CONFIG_DS4424=m
-CONFIG_LTC1660=m
-CONFIG_LTC2632=m
-CONFIG_M62332=m
-CONFIG_MAX517=m
-CONFIG_MAX5821=m
-CONFIG_MCP4725=m
-CONFIG_MCP4922=m
-CONFIG_TI_DAC082S085=m
-CONFIG_TI_DAC5571=m
-CONFIG_TI_DAC7311=m
-CONFIG_TI_DAC7612=m
-# end of Digital to analog converters
-
-#
-# IIO dummy driver
-#
-# CONFIG_IIO_SIMPLE_DUMMY is not set
-# end of IIO dummy driver
-
-#
-# Frequency Synthesizers DDS/PLL
-#
-
-#
-# Clock Generator/Distribution
-#
-CONFIG_AD9523=m
-# end of Clock Generator/Distribution
-
-#
-# Phase-Locked Loop (PLL) frequency synthesizers
-#
-CONFIG_ADF4350=m
-CONFIG_ADF4371=m
-# end of Phase-Locked Loop (PLL) frequency synthesizers
-# end of Frequency Synthesizers DDS/PLL
-
-#
-# Digital gyroscope sensors
-#
-CONFIG_ADIS16080=m
-CONFIG_ADIS16130=m
-CONFIG_ADIS16136=m
-CONFIG_ADIS16260=m
-CONFIG_ADXRS290=m
-CONFIG_ADXRS450=m
-CONFIG_BMG160=m
-CONFIG_BMG160_I2C=m
-CONFIG_BMG160_SPI=m
-CONFIG_FXAS21002C=m
-CONFIG_FXAS21002C_I2C=m
-CONFIG_FXAS21002C_SPI=m
-CONFIG_HID_SENSOR_GYRO_3D=m
-CONFIG_MPU3050=m
-CONFIG_MPU3050_I2C=m
-CONFIG_IIO_ST_GYRO_3AXIS=m
-CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
-CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
-CONFIG_ITG3200=m
-# end of Digital gyroscope sensors
-
-#
-# Health Sensors
-#
-
-#
-# Heart Rate Monitors
-#
-CONFIG_AFE4403=m
-CONFIG_AFE4404=m
-CONFIG_MAX30100=m
-CONFIG_MAX30102=m
-# end of Heart Rate Monitors
-# end of Health Sensors
-
-#
-# Humidity sensors
-#
-CONFIG_AM2315=m
-CONFIG_DHT11=m
-CONFIG_HDC100X=m
-CONFIG_HDC2010=m
-CONFIG_HID_SENSOR_HUMIDITY=m
-CONFIG_HTS221=m
-CONFIG_HTS221_I2C=m
-CONFIG_HTS221_SPI=m
-CONFIG_HTU21=m
-CONFIG_SI7005=m
-CONFIG_SI7020=m
-# end of Humidity sensors
-
-#
-# Inertial measurement units
-#
-CONFIG_ADIS16400=m
-CONFIG_ADIS16460=m
-CONFIG_ADIS16475=m
-CONFIG_ADIS16480=m
-CONFIG_BMI160=m
-CONFIG_BMI160_I2C=m
-CONFIG_BMI160_SPI=m
-CONFIG_BOSCH_BNO055_SERIAL=m
-CONFIG_BOSCH_BNO055_I2C=m
-CONFIG_FXOS8700=m
-CONFIG_FXOS8700_I2C=m
-CONFIG_FXOS8700_SPI=m
-CONFIG_KMX61=m
-CONFIG_INV_ICM42600=m
-CONFIG_INV_ICM42600_I2C=m
-CONFIG_INV_ICM42600_SPI=m
-CONFIG_INV_MPU6050_IIO=m
-CONFIG_INV_MPU6050_I2C=m
-CONFIG_INV_MPU6050_SPI=m
-CONFIG_IIO_ST_LSM6DSX=m
-CONFIG_IIO_ST_LSM9DS0=m
-CONFIG_IIO_ST_LSM9DS0_I2C=m
-CONFIG_IIO_ST_LSM9DS0_SPI=m
-CONFIG_IIO_ST_LSM6DSX_I2C=m
-CONFIG_IIO_ST_LSM6DSX_SPI=m
-CONFIG_IIO_ST_LSM6DSX_I3C=m
-# end of Inertial measurement units
-
-CONFIG_IIO_ADIS_LIB=m
-CONFIG_IIO_ADIS_LIB_BUFFER=y
-
-#
-# Light sensors
-#
-# CONFIG_ACPI_ALS is not set
-CONFIG_ADJD_S311=m
-CONFIG_ADUX1020=m
-CONFIG_AL3010=m
-CONFIG_AL3320A=m
-CONFIG_APDS9300=m
-CONFIG_APDS9960=m
-CONFIG_AS73211=m
-CONFIG_BH1750=m
-CONFIG_BH1780=m
-CONFIG_CM32181=m
-CONFIG_CM3232=m
-CONFIG_CM3323=m
-CONFIG_CM36651=m
-CONFIG_IIO_CROS_EC_LIGHT_PROX=m
-CONFIG_GP2AP002=m
-CONFIG_GP2AP020A00F=m
-CONFIG_IQS621_ALS=m
-CONFIG_SENSORS_ISL29018=m
-CONFIG_SENSORS_ISL29028=m
-CONFIG_ISL29125=m
-CONFIG_HID_SENSOR_ALS=m
-CONFIG_HID_SENSOR_PROX=m
-CONFIG_JSA1212=m
-CONFIG_RPR0521=m
-CONFIG_SENSORS_LM3533=m
-CONFIG_LTR501=m
-CONFIG_LTRF216A=m
-CONFIG_LV0104CS=m
-CONFIG_MAX44000=m
-CONFIG_MAX44009=m
-CONFIG_NOA1305=m
-CONFIG_OPT3001=m
-CONFIG_PA12203001=m
-CONFIG_SI1133=m
-CONFIG_SI1145=m
-CONFIG_STK3310=m
-CONFIG_ST_UVIS25=m
-CONFIG_ST_UVIS25_I2C=m
-CONFIG_ST_UVIS25_SPI=m
-CONFIG_TCS3414=m
-CONFIG_TCS3472=m
-CONFIG_SENSORS_TSL2563=m
-CONFIG_TSL2583=m
-CONFIG_TSL2591=m
-CONFIG_TSL2772=m
-CONFIG_TSL4531=m
-CONFIG_US5182D=m
-CONFIG_VCNL4000=m
-CONFIG_VCNL4035=m
-CONFIG_VEML6030=m
-CONFIG_VEML6070=m
-CONFIG_VL6180=m
-CONFIG_ZOPT2201=m
-# end of Light sensors
-
-#
-# Magnetometer sensors
-#
-CONFIG_AK8975=m
-CONFIG_AK09911=m
-CONFIG_BMC150_MAGN=m
-CONFIG_BMC150_MAGN_I2C=m
-CONFIG_BMC150_MAGN_SPI=m
-CONFIG_MAG3110=m
-CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
-CONFIG_MMC35240=m
-CONFIG_IIO_ST_MAGN_3AXIS=m
-CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
-CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
-CONFIG_SENSORS_HMC5843=m
-CONFIG_SENSORS_HMC5843_I2C=m
-CONFIG_SENSORS_HMC5843_SPI=m
-CONFIG_SENSORS_RM3100=m
-CONFIG_SENSORS_RM3100_I2C=m
-CONFIG_SENSORS_RM3100_SPI=m
-CONFIG_YAMAHA_YAS530=m
-# end of Magnetometer sensors
-
-#
-# Multiplexers
-#
-# end of Multiplexers
-
-#
-# Inclinometer sensors
-#
-CONFIG_HID_SENSOR_INCLINOMETER_3D=m
-CONFIG_HID_SENSOR_DEVICE_ROTATION=m
-# end of Inclinometer sensors
-
-#
-# Triggers - standalone
-#
-CONFIG_IIO_HRTIMER_TRIGGER=m
-CONFIG_IIO_INTERRUPT_TRIGGER=m
-CONFIG_IIO_TIGHTLOOP_TRIGGER=m
-CONFIG_IIO_SYSFS_TRIGGER=m
-# end of Triggers - standalone
-
-#
-# Linear and angular position sensors
-#
-CONFIG_IQS624_POS=m
-CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
-# end of Linear and angular position sensors
-
-#
-# Digital potentiometers
-#
-CONFIG_AD5272=m
-CONFIG_DS1803=m
-CONFIG_MAX5432=m
-CONFIG_MAX5481=m
-CONFIG_MAX5487=m
-CONFIG_MCP4018=m
-CONFIG_MCP4131=m
-CONFIG_MCP4531=m
-CONFIG_MCP41010=m
-CONFIG_TPL0102=m
-# end of Digital potentiometers
-
-#
-# Digital potentiostats
-#
-CONFIG_LMP91000=m
-# end of Digital potentiostats
-
-#
-# Pressure sensors
-#
-CONFIG_ABP060MG=m
-CONFIG_BMP280=m
-CONFIG_BMP280_I2C=m
-CONFIG_BMP280_SPI=m
-CONFIG_IIO_CROS_EC_BARO=m
-CONFIG_DLHL60D=m
-CONFIG_DPS310=m
-CONFIG_HID_SENSOR_PRESS=m
-CONFIG_HP03=m
-CONFIG_ICP10100=m
-CONFIG_MPL115=m
-CONFIG_MPL115_I2C=m
-CONFIG_MPL115_SPI=m
-CONFIG_MPL3115=m
-CONFIG_MS5611=m
-CONFIG_MS5611_I2C=m
-CONFIG_MS5611_SPI=m
-CONFIG_MS5637=m
-CONFIG_IIO_ST_PRESS=m
-CONFIG_IIO_ST_PRESS_I2C=m
-CONFIG_IIO_ST_PRESS_SPI=m
-CONFIG_T5403=m
-CONFIG_HP206C=m
-CONFIG_ZPA2326=m
-CONFIG_ZPA2326_I2C=m
-CONFIG_ZPA2326_SPI=m
-# end of Pressure sensors
-
-#
-# Lightning sensors
-#
-CONFIG_AS3935=m
-# end of Lightning sensors
-
-#
-# Proximity and distance sensors
-#
-CONFIG_ISL29501=m
-CONFIG_LIDAR_LITE_V2=m
-CONFIG_MB1232=m
-CONFIG_PING=m
-CONFIG_RFD77402=m
-CONFIG_SRF04=m
-CONFIG_SX9310=m
-CONFIG_SX9324=m
-CONFIG_SX9360=m
-CONFIG_SX9500=m
-CONFIG_SRF08=m
-CONFIG_VCNL3020=m
-CONFIG_VL53L0X_I2C=m
-# end of Proximity and distance sensors
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S90=m
-CONFIG_AD2S1200=m
-# end of Resolver to digital converters
-
-#
-# Temperature sensors
-#
-CONFIG_IQS620AT_TEMP=m
-CONFIG_LTC2983=m
-CONFIG_MAXIM_THERMOCOUPLE=m
-CONFIG_HID_SENSOR_TEMP=m
-CONFIG_MLX90614=m
-CONFIG_MLX90632=m
-CONFIG_TMP006=m
-CONFIG_TMP007=m
-CONFIG_TMP117=m
-CONFIG_TSYS01=m
-CONFIG_TSYS02D=m
-CONFIG_MAX31856=m
-# end of Temperature sensors
-
-CONFIG_NTB=m
-CONFIG_NTB_MSI=y
-CONFIG_NTB_IDT=m
-CONFIG_NTB_EPF=m
-CONFIG_NTB_SWITCHTEC=m
-CONFIG_NTB_PINGPONG=m
-CONFIG_NTB_TOOL=m
-CONFIG_NTB_PERF=m
-CONFIG_NTB_MSI_TEST=m
-CONFIG_NTB_TRANSPORT=m
-CONFIG_VME_BUS=y
-
-#
-# VME Bridge Drivers
-#
-CONFIG_VME_CA91CX42=m
-CONFIG_VME_TSI148=m
-CONFIG_VME_FAKE=m
-
-#
-# VME Board Drivers
-#
-CONFIG_VMIVME_7805=m
-
-#
-# VME Device Drivers
-#
-CONFIG_VME_USER=m
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_PWM_DEBUG is not set
-CONFIG_PWM_CLK=m
-CONFIG_PWM_CROS_EC=m
-CONFIG_PWM_DWC=m
-CONFIG_PWM_IQS620A=m
-CONFIG_PWM_LP3943=m
-CONFIG_PWM_LPSS=m
-CONFIG_PWM_LPSS_PCI=m
-CONFIG_PWM_LPSS_PLATFORM=m
-CONFIG_PWM_PCA9685=m
-CONFIG_PWM_SL28CPLD=m
-
-#
-# IRQ chip support
-#
-CONFIG_MADERA_IRQ=m
-CONFIG_MST_IRQ=y
-# end of IRQ chip support
-
-CONFIG_IPACK_BUS=m
-CONFIG_BOARD_TPCI200=m
-CONFIG_SERIAL_IPOCTAL=m
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_SIMPLE=y
-CONFIG_RESET_MCHP_SPARX5=y
-CONFIG_RESET_A10SR=m
-# CONFIG_RESET_BRCMSTB_RESCAL is not set
-CONFIG_RESET_TI_SYSCON=m
-CONFIG_RESET_TI_TPS380X=m
-
-#
-# PHY Subsystem
-#
-CONFIG_GENERIC_PHY=y
-CONFIG_PHY_CAN_TRANSCEIVER=m
-CONFIG_USB_LGM_PHY=m
-CONFIG_BCM_KONA_USB2_PHY=m
-CONFIG_PHY_PXA_28NM_HSIC=m
-CONFIG_PHY_PXA_28NM_USB2=m
-CONFIG_PHY_CPCAP_USB=m
-CONFIG_PHY_QCOM_USB_HS=m
-CONFIG_PHY_QCOM_USB_HSIC=m
-CONFIG_PHY_SAMSUNG_USB2=m
-CONFIG_PHY_TUSB1210=m
-CONFIG_PHY_INTEL_LGM_EMMC=m
-# end of PHY Subsystem
-
-CONFIG_POWERCAP=y
-CONFIG_INTEL_RAPL_CORE=m
-CONFIG_INTEL_RAPL=m
-# CONFIG_IDLE_INJECT is not set
-CONFIG_PECI=m
-CONFIG_PECI_CPU=m
-CONFIG_PECI_ASPEED=m
-CONFIG_SENSORS_PECI_CPUTEMP=m
-CONFIG_SENSORS_PECI_DIMMTEMP=m
-CONFIG_DTPM=y
-CONFIG_DTPM_CPU=y
-CONFIG_DTPM_DEVFREQ=y
-CONFIG_MCB=m
-CONFIG_MCB_PCI=m
-CONFIG_MCB_LPC=m
-
-#
-# Performance monitor support
-#
-# end of Performance monitor support
-
-CONFIG_RAS=y
-CONFIG_USB4=m
-# CONFIG_USB4_DEBUGFS_WRITE is not set
-# CONFIG_USB4_DMA_TEST is not set
-
-#
-# Android
-#
-# CONFIG_ANDROID is not set
-# end of Android
-
-CONFIG_LIBNVDIMM=m
-CONFIG_BLK_DEV_PMEM=m
-CONFIG_ND_BLK=m
-CONFIG_ND_CLAIM=y
-CONFIG_ND_BTT=m
-CONFIG_BTT=y
-CONFIG_NVDIMM_KEYS=y
-CONFIG_DAX_DRIVER=y
-CONFIG_DAX=y
-CONFIG_DEV_DAX=m
-CONFIG_DEV_DAX_HMEM=m
-CONFIG_DEV_DAX_HMEM_DEVICES=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_RAVE_SP_EEPROM=m
-CONFIG_NVMEM_SPMI_SDAM=m
-CONFIG_RAVE_SP_EEPROM=m
-CONFIG_NVMEM_RMEM=m
-CONFIG_NVMEM_LAYERSCAPE_SFP=m
-CONFIG_NVMEM_MESON_EFUSE=m
-CONFIG_NVMEM_SPRD_EFUSE=m
-
-#
-# HW tracing support
-#
-CONFIG_STM=m
-CONFIG_STM_PROTO_BASIC=m
-CONFIG_STM_PROTO_SYS_T=m
-# CONFIG_STM_DUMMY is not set
-CONFIG_STM_SOURCE_CONSOLE=m
-CONFIG_STM_SOURCE_HEARTBEAT=m
-# CONFIG_STM_SOURCE_FTRACE is not set
-CONFIG_INTEL_TH=m
-CONFIG_INTEL_TH_PCI=m
-CONFIG_INTEL_TH_ACPI=m
-CONFIG_INTEL_TH_GTH=m
-CONFIG_INTEL_TH_STH=m
-CONFIG_INTEL_TH_MSU=m
-CONFIG_INTEL_TH_PTI=m
-CONFIG_HISI_PTT=m
-# CONFIG_INTEL_TH_DEBUG is not set
-# end of HW tracing support
-
-CONFIG_FPGA=m
-CONFIG_FPGA_MGR_SOCFPGA=m
-CONFIG_FPGA_MGR_SOCFPGA_A10=m
-CONFIG_ALTERA_PR_IP_CORE=m
-CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
-CONFIG_FPGA_MGR_ALTERA_CVP=m
-CONFIG_FPGA_MGR_XILINX_SPI=m
-CONFIG_FPGA_MGR_MACHXO2_SPI=m
-CONFIG_FPGA_BRIDGE=m
-CONFIG_ALTERA_FREEZE_BRIDGE=m
-CONFIG_XILINX_PR_DECOUPLER=m
-CONFIG_FPGA_REGION=m
-CONFIG_FPGA_DFL=m
-CONFIG_FPGA_DFL_FME=m
-CONFIG_FPGA_DFL_FME_MGR=m
-CONFIG_FPGA_DFL_FME_BRIDGE=m
-CONFIG_FPGA_DFL_FME_REGION=m
-CONFIG_FPGA_DFL_AFU=m
-CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
-CONFIG_FPGA_DFL_PCI=m
-CONFIG_FPGA_MGR_MICROCHIP_SPI=m
-CONFIG_FPGA_M10_BMC_SEC_UPDATE=m
-CONFIG_TEE=m
-
-#
-# TEE drivers
-#
-# end of TEE drivers
-
-CONFIG_MULTIPLEXER=m
-
-#
-# Multiplexer drivers
-#
-CONFIG_MUX_ADG792A=m
-CONFIG_MUX_ADGS1408=m
-CONFIG_MUX_GPIO=m
-# end of Multiplexer drivers
-
-CONFIG_PM_OPP=y
-CONFIG_SIOX=m
-CONFIG_SIOX_BUS_GPIO=m
-CONFIG_SLIMBUS=m
-CONFIG_SLIM_QCOM_CTRL=m
-# CONFIG_INTERCONNECT is not set
-CONFIG_COUNTER=m
-CONFIG_INTERRUPT_CNT=m
-CONFIG_INTEL_QEP=m
-CONFIG_TI_ECAP_CAPTURE=m
-CONFIG_MOST=m
-CONFIG_MOST_USB_HDM=m
-CONFIG_MOST_CDEV=m
-CONFIG_MOST_SND=m
-CONFIG_NETFS_SUPPORT=m
-CONFIG_NETFS_STATS=y
-# end of Device Drivers
-
-#
-# File systems
-#
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_VALIDATE_FS_PARSER=y
-CONFIG_FS_IOMAP=y
-# CONFIG_EXT2_FS is not set
-# CONFIG_EXT3_FS is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_USE_FOR_EXT2=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD2=m
-# CONFIG_JBD2_DEBUG is not set
-CONFIG_FS_MBCACHE=m
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-CONFIG_REISERFS_PROC_INFO=y
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_SECURITY=y
-# CONFIG_JFS_DEBUG is not set
-CONFIG_JFS_STATISTICS=y
-CONFIG_XFS_FS=m
-# CONFIG_XFS_SUPPORT_V4 is not set
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_XFS_ONLINE_SCRUB=y
-# CONFIG_XFS_ONLINE_REPAIR is not set
-# CONFIG_XFS_WARN is not set
-# CONFIG_XFS_DEBUG is not set
-CONFIG_GFS2_FS=m
-CONFIG_GFS2_FS_LOCKING_DLM=y
-CONFIG_OCFS2_FS=m
-CONFIG_OCFS2_FS_O2CB=m
-CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
-CONFIG_OCFS2_FS_STATS=y
-CONFIG_OCFS2_DEBUG_MASKLOG=y
-CONFIG_OCFS2_DEBUG_FS=y
-CONFIG_BTRFS_FS=m
-CONFIG_BTRFS_FS_POSIX_ACL=y
-# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
-# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
-# CONFIG_BTRFS_DEBUG is not set
-# CONFIG_BTRFS_ASSERT is not set
-# CONFIG_BTRFS_FS_REF_VERIFY is not set
-CONFIG_NILFS2_FS=m
-CONFIG_F2FS_FS=m
-CONFIG_F2FS_STAT_FS=y
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_FS_POSIX_ACL=y
-CONFIG_F2FS_FS_SECURITY=y
-# CONFIG_F2FS_CHECK_FS is not set
-# CONFIG_F2FS_IO_TRACE is not set
-# CONFIG_F2FS_FAULT_INJECTION is not set
-CONFIG_F2FS_FS_COMPRESSION=y
-CONFIG_F2FS_FS_LZO=y
-CONFIG_F2FS_FS_LZ4=y
-CONFIG_F2FS_FS_LZ4HC=y
-CONFIG_F2FS_FS_ZSTD=y
-CONFIG_F2FS_FS_LZORLE=y
-CONFIG_ZONEFS_FS=m
-CONFIG_FS_DAX=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_EXPORTFS=y
-CONFIG_EXPORTFS_BLOCK_OPS=y
-CONFIG_FILE_LOCKING=y
-CONFIG_MANDATORY_FILE_LOCKING=y
-CONFIG_FS_ENCRYPTION=y
-CONFIG_FS_ENCRYPTION_ALGS=m
-# CONFIG_FS_VERITY is not set
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY_USER=y
-CONFIG_FANOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-# CONFIG_QUOTA_DEBUG is not set
-CONFIG_QUOTA_TREE=m
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=m
-CONFIG_QUOTACTL=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_AUTOFS_FS=y
-CONFIG_FUSE_FS=m
-CONFIG_CUSE=m
-CONFIG_VIRTIO_FS=m
-CONFIG_FUSE_DAX=y
-CONFIG_OVERLAY_FS=m
-CONFIG_OVERLAY_FS_REDIRECT_DIR=y
-CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
-CONFIG_OVERLAY_FS_INDEX=y
-CONFIG_OVERLAY_FS_NFS_EXPORT=y
-# CONFIG_OVERLAY_FS_METACOPY is not set
-
-#
-# Caches
-#
-CONFIG_FSCACHE=m
-CONFIG_FSCACHE_STATS=y
-# CONFIG_FSCACHE_HISTOGRAM is not set
-# CONFIG_FSCACHE_DEBUG is not set
-# CONFIG_FSCACHE_OBJECT_LIST is not set
-CONFIG_CACHEFILES=m
-# CONFIG_CACHEFILES_DEBUG is not set
-# CONFIG_CACHEFILES_HISTOGRAM is not set
-# end of Caches
-
-#
-# CD-ROM/DVD Filesystems
-#
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-# end of CD-ROM/DVD Filesystems
-
-#
-# DOS/FAT/EXFAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
-# CONFIG_FAT_DEFAULT_UTF8 is not set
-CONFIG_EXFAT_FS=m
-CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-CONFIG_NTFS_RW=y
-CONFIG_NTFS3_FS=m
-CONFIG_NTFS3_LZX_XPRESS=y
-CONFIG_NTFS3_FS_POSIX_ACL=y
-# CONFIG_NTFS3_64BIT_CLUSTER is not set
-# end of DOS/FAT/EXFAT/NT Filesystems
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_CHILDREN=y
-CONFIG_PROC_PID_ARCH_STATUS=y
-CONFIG_PROC_CPU_RESCTRL=y
-CONFIG_KERNFS=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TMPFS_XATTR=y
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE_FREE_VMEMMAP_DEFAULT_ON=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_EFIVAR_FS=m
-# end of Pseudo filesystems
-
-CONFIG_MISC_FILESYSTEMS=y
-CONFIG_ORANGEFS_FS=m
-CONFIG_ADFS_FS=m
-# CONFIG_ADFS_FS_RW is not set
-CONFIG_AFFS_FS=m
-CONFIG_ECRYPT_FS=m
-CONFIG_ECRYPT_FS_MESSAGING=y
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-# CONFIG_BEFS_DEBUG is not set
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RTIME=y
-CONFIG_JFFS2_RUBIN=y
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-CONFIG_UBIFS_FS=m
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UBIFS_FS_ZSTD=y
-CONFIG_UBIFS_ATIME_SUPPORT=y
-CONFIG_UBIFS_FS_XATTR=y
-CONFIG_UBIFS_FS_SECURITY=y
-# CONFIG_UBIFS_FS_AUTHENTICATION is not set
-CONFIG_CRAMFS=m
-CONFIG_CRAMFS_BLOCKDEV=y
-CONFIG_CRAMFS_MTD=y
-CONFIG_SQUASHFS=m
-# CONFIG_SQUASHFS_FILE_CACHE is not set
-CONFIG_SQUASHFS_FILE_DIRECT=y
-# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
-CONFIG_SQUASHFS_DECOMP_MULTI=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_XATTR=y
-CONFIG_SQUASHFS_ZLIB=y
-CONFIG_SQUASHFS_LZ4=y
-CONFIG_SQUASHFS_LZO=y
-CONFIG_SQUASHFS_XZ=y
-CONFIG_SQUASHFS_ZSTD=y
-CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
-CONFIG_SQUASHFS_EMBEDDED=y
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_OMFS_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_QNX6FS_FS=m
-# CONFIG_QNX6FS_DEBUG is not set
-CONFIG_ROMFS_FS=m
-# CONFIG_ROMFS_BACKED_BY_BLOCK is not set
-# CONFIG_ROMFS_BACKED_BY_MTD is not set
-CONFIG_ROMFS_BACKED_BY_BOTH=y
-CONFIG_ROMFS_ON_BLOCK=y
-CONFIG_ROMFS_ON_MTD=y
-CONFIG_PSTORE=m
-CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_LZO_COMPRESS=y
-CONFIG_PSTORE_LZ4_COMPRESS=y
-CONFIG_PSTORE_LZ4HC_COMPRESS=y
-CONFIG_PSTORE_842_COMPRESS=y
-CONFIG_PSTORE_ZSTD_COMPRESS=y
-CONFIG_PSTORE_COMPRESS=y
-# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
-CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="zstd"
-# CONFIG_PSTORE_CONSOLE is not set
-CONFIG_PSTORE_PMSG=y
-# CONFIG_PSTORE_FTRACE is not set
-CONFIG_PSTORE_RAM=m
-CONFIG_PSTORE_ZONE=m
-CONFIG_PSTORE_BLK=m
-CONFIG_PSTORE_BLK_BLKDEV=""
-CONFIG_PSTORE_BLK_KMSG_SIZE=64
-CONFIG_PSTORE_BLK_MAX_REASON=2
-CONFIG_PSTORE_BLK_PMSG_SIZE=64
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-# CONFIG_UFS_FS_WRITE is not set
-# CONFIG_UFS_DEBUG is not set
-CONFIG_EROFS_FS=m
-# CONFIG_EROFS_FS_DEBUG is not set
-CONFIG_EROFS_FS_XATTR=y
-CONFIG_EROFS_FS_POSIX_ACL=y
-# CONFIG_EROFS_FS_SECURITY is not set
-# CONFIG_EROFS_FS_ZIP is not set
-CONFIG_VBOXSF_FS=m
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V2=m
-CONFIG_NFS_V3=m
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=m
-CONFIG_NFS_SWAP=y
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_V4_2=y
-CONFIG_PNFS_FILE_LAYOUT=m
-CONFIG_PNFS_BLOCK=m
-CONFIG_PNFS_FLEXFILE_LAYOUT=m
-CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
-CONFIG_NFS_V4_1_MIGRATION=y
-CONFIG_NFS_FSCACHE=y
-# CONFIG_NFS_USE_LEGACY_DNS is not set
-CONFIG_NFS_USE_KERNEL_DNS=y
-CONFIG_NFS_DISABLE_UDP_SUPPORT=y
-CONFIG_NFS_V4_2_READ_PLUS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V2_ACL=y
-CONFIG_NFSD_V3=y
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_PNFS=y
-CONFIG_NFSD_BLOCKLAYOUT=y
-CONFIG_NFSD_SCSILAYOUT=y
-CONFIG_NFSD_FLEXFILELAYOUT=y
-CONFIG_NFSD_V4_2_INTER_SSC=y
-CONFIG_GRACE_PERIOD=m
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_ACL_SUPPORT=m
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_SUNRPC_BACKCHANNEL=y
-CONFIG_SUNRPC_SWAP=y
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
-# CONFIG_SUNRPC_DEBUG is not set
-CONFIG_SUNRPC_XPRT_RDMA=m
-CONFIG_CEPH_FS=m
-CONFIG_CEPH_FSCACHE=y
-CONFIG_CEPH_FS_POSIX_ACL=y
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS2=y
-CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
-CONFIG_CIFS_WEAK_PW_HASH=y
-CONFIG_CIFS_UPCALL=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-# CONFIG_CIFS_DEBUG is not set
-CONFIG_CIFS_DFS_UPCALL=y
-CONFIG_CIFS_SWN_UPCALL=y
-# CONFIG_CIFS_SMB_DIRECT is not set
-CONFIG_CIFS_FSCACHE=y
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-# CONFIG_AFS_DEBUG is not set
-CONFIG_AFS_FSCACHE=y
-# CONFIG_AFS_DEBUG_CURSOR is not set
-CONFIG_9P_FS=m
-CONFIG_9P_FSCACHE=y
-CONFIG_9P_FS_POSIX_ACL=y
-CONFIG_9P_FS_SECURITY=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_MAC_ROMAN=m
-CONFIG_NLS_MAC_CELTIC=m
-CONFIG_NLS_MAC_CENTEURO=m
-CONFIG_NLS_MAC_CROATIAN=m
-CONFIG_NLS_MAC_CYRILLIC=m
-CONFIG_NLS_MAC_GAELIC=m
-CONFIG_NLS_MAC_GREEK=m
-CONFIG_NLS_MAC_ICELAND=m
-CONFIG_NLS_MAC_INUIT=m
-CONFIG_NLS_MAC_ROMANIAN=m
-CONFIG_NLS_MAC_TURKISH=m
-CONFIG_NLS_UTF8=m
-CONFIG_DLM=m
-# CONFIG_DLM_DEPRECATED_API is not set
-# CONFIG_DLM_DEBUG is not set
-CONFIG_UNICODE=y
-CONFIG_UNICODE_NORMALIZATION_SELFTEST=m
-CONFIG_IO_WQ=y
-# end of File systems
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-# CONFIG_KEYS_REQUEST_CACHE is not set
-CONFIG_PERSISTENT_KEYRINGS=y
-CONFIG_TRUSTED_KEYS=m
-CONFIG_ENCRYPTED_KEYS=m
-CONFIG_USER_DECRYPTED_DATA=y
-# CONFIG_KEY_DH_OPERATIONS is not set
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-# CONFIG_SECURITY is not set
-CONFIG_SECURITYFS=y
-CONFIG_PAGE_TABLE_ISOLATION=y
-CONFIG_INTEL_TXT=y
-CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
-CONFIG_HARDENED_USERCOPY=y
-CONFIG_HARDENED_USERCOPY_FALLBACK=y
-# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
-CONFIG_FORTIFY_SOURCE=y
-# CONFIG_STATIC_USERMODEHELPER is not set
-# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_LSM="yama,loadpin,safesetid,integrity,bpf"
-
-#
-# Kernel hardening options
-#
-
-#
-# Memory initialization
-#
-CONFIG_INIT_STACK_NONE=y
-# CONFIG_INIT_STACK_ALL_PATTERN is not set
-# CONFIG_INIT_STACK_ALL_ZERO is not set
-# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
-# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
-# end of Memory initialization
-# end of Kernel hardening options
-# end of Security options
-
-CONFIG_XOR_BLOCKS=m
-CONFIG_ASYNC_CORE=m
-CONFIG_ASYNC_MEMCPY=m
-CONFIG_ASYNC_XOR=m
-CONFIG_ASYNC_PQ=m
-CONFIG_ASYNC_RAID6_RECOV=m
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=m
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_SKCIPHER=y
-CONFIG_CRYPTO_SKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG=m
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=m
-CONFIG_CRYPTO_AKCIPHER2=y
-CONFIG_CRYPTO_AKCIPHER=y
-CONFIG_CRYPTO_KPP2=y
-CONFIG_CRYPTO_KPP=m
-CONFIG_CRYPTO_ACOMP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_USER=m
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_PCRYPT=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_SIMD=m
-CONFIG_CRYPTO_ENGINE=m
-
-#
-# Public-key cryptography
-#
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_DH=m
-CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
-CONFIG_CRYPTO_ECC=m
-CONFIG_CRYPTO_ECDH=m
-CONFIG_CRYPTO_ECDSA=m
-CONFIG_CRYPTO_ECRDSA=m
-CONFIG_CRYPTO_SM2=m
-CONFIG_CRYPTO_CURVE25519=m
-
-#
-# Authenticated Encryption with Associated Data
-#
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_GCM=m
-CONFIG_CRYPTO_CHACHA20POLY1305=m
-CONFIG_CRYPTO_AEGIS128=m
-CONFIG_CRYPTO_SEQIV=m
-CONFIG_CRYPTO_ECHAINIV=m
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CFB=m
-CONFIG_CRYPTO_CTR=m
-CONFIG_CRYPTO_CTS=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_OFB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_KEYWRAP=m
-CONFIG_CRYPTO_NHPOLY1305=m
-CONFIG_CRYPTO_ADIANTUM=m
-CONFIG_CRYPTO_HCTR2=m
-CONFIG_CRYPTO_ARIA=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
-CONFIG_CRYPTO_DEV_QAT_C3XXX=m
-CONFIG_CRYPTO_DEV_QAT_C62X=m
-CONFIG_CRYPTO_DEV_QAT_4XXX=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
-CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
-CONFIG_CRYPTO_DEV_QAT_C62XVF=m
-CONFIG_CRYPTO_ESSIV=m
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_CMAC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CRC32C_INTEL=m
-CONFIG_CRYPTO_CRC32=m
-CONFIG_CRYPTO_CRC32_PCLMUL=m
-CONFIG_CRYPTO_XXHASH=m
-CONFIG_CRYPTO_BLAKE2B=m
-CONFIG_CRYPTO_BLAKE2S=m
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_GHASH=m
-CONFIG_CRYPTO_POLYVAL_CLMUL_NI=m
-CONFIG_CRYPTO_POLY1305=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_RMD128=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_RMD256=m
-CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SHA3=m
-CONFIG_CRYPTO_SM3=m
-CONFIG_CRYPTO_SM3_AVX_X86_64=m
-# CONFIG_CRYPTO_STREEBOG is not set
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_AES_TI=m
-CONFIG_CRYPTO_AES_NI_INTEL=m
-CONFIG_CRYPTO_ANUBIS=m
-# CONFIG_CRYPTO_ARC4 is not set
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_BLOWFISH_COMMON=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST_COMMON=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SALSA20=m
-CONFIG_CRYPTO_CHACHA20=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-# CONFIG_CRYPTO_SERPENT_SSE2_586 is not set
-CONFIG_CRYPTO_SM4=m
-CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64=m
-CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-# CONFIG_CRYPTO_TWOFISH_586 is not set
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_842=y
-CONFIG_CRYPTO_LZ4=y
-CONFIG_CRYPTO_LZ4HC=y
-CONFIG_CRYPTO_ZSTD=y
-
-#
-# Random Number Generation
-#
-CONFIG_CRYPTO_ANSI_CPRNG=m
-CONFIG_CRYPTO_DRBG_MENU=m
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_HASH=y
-CONFIG_CRYPTO_DRBG_CTR=y
-CONFIG_CRYPTO_DRBG=m
-CONFIG_CRYPTO_JITTERENTROPY=m
-CONFIG_CRYPTO_USER_API=m
-CONFIG_CRYPTO_USER_API_HASH=y
-CONFIG_CRYPTO_USER_API_SKCIPHER=m
-CONFIG_CRYPTO_USER_API_RNG=m
-# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
-CONFIG_CRYPTO_USER_API_AEAD=m
-CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
-# CONFIG_CRYPTO_STATS is not set
-CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=m
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
-CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_DEV_PADLOCK=m
-CONFIG_CRYPTO_DEV_PADLOCK_AES=m
-CONFIG_CRYPTO_DEV_PADLOCK_SHA=m
-# CONFIG_CRYPTO_DEV_GEODE is not set
-CONFIG_CRYPTO_DEV_ATMEL_I2C=m
-CONFIG_CRYPTO_DEV_ATMEL_ECC=m
-CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
-CONFIG_CRYPTO_DEV_CCP=y
-CONFIG_CRYPTO_DEV_CCP_DD=m
-CONFIG_CRYPTO_DEV_SP_CCP=y
-CONFIG_CRYPTO_DEV_CCP_CRYPTO=m
-# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set
-CONFIG_CRYPTO_DEV_QAT=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
-CONFIG_CRYPTO_DEV_QAT_C3XXX=m
-CONFIG_CRYPTO_DEV_QAT_C62X=m
-CONFIG_CRYPTO_DEV_QAT_4XXX=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
-CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
-CONFIG_CRYPTO_DEV_QAT_C62XVF=m
-CONFIG_CRYPTO_DEV_CHELSIO=m
-CONFIG_CRYPTO_DEV_VIRTIO=m
-CONFIG_CRYPTO_DEV_SAFEXCEL=m
-CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
-CONFIG_CRYPTO_DEV_ASPEED=m
-# CONFIG_CRYPTO_DEV_ASPEED_DEBUG is not set
-CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH=y
-CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO=y
-# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set
-CONFIG_ASYMMETRIC_KEY_TYPE=y
-CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
-CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE=m
-CONFIG_X509_CERTIFICATE_PARSER=y
-CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
-CONFIG_TPM_KEY_PARSER=m
-CONFIG_PKCS7_MESSAGE_PARSER=y
-CONFIG_PKCS7_TEST_KEY=m
-CONFIG_SIGNED_PE_FILE_VERIFICATION=y
-
-#
-# Certificates for signature checking
-#
-CONFIG_SYSTEM_TRUSTED_KEYRING=y
-CONFIG_SYSTEM_TRUSTED_KEYS=""
-# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
-CONFIG_SECONDARY_TRUSTED_KEYRING=y
-CONFIG_SYSTEM_BLACKLIST_KEYRING=y
-# CONFIG_SYSTEM_REVOCATION_LIST is not set
-CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
-# end of Certificates for signature checking
-
-CONFIG_BINARY_PRINTF=y
-
-#
-# Library routines
-#
-CONFIG_RAID6_PQ=m
-CONFIG_RAID6_PQ_BENCHMARK=y
-CONFIG_LINEAR_RANGES=y
-CONFIG_PACKING=y
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_CORDIC=m
-CONFIG_PRIME_NUMBERS=m
-CONFIG_RATIONAL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
-CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC64_ROCKSOFT=m
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC32_SELFTEST is not set
-CONFIG_CRC32_SLICEBY8=y
-# CONFIG_CRC32_SLICEBY4 is not set
-# CONFIG_CRC32_SARWATE is not set
-# CONFIG_CRC32_BIT is not set
-CONFIG_CRC64=m
-CONFIG_CRC4=m
-CONFIG_CRC7=m
-CONFIG_LIBCRC32C=m
-CONFIG_CRC8=m
-CONFIG_XXHASH=y
-# CONFIG_RANDOM32_SELFTEST is not set
-CONFIG_842_COMPRESS=y
-CONFIG_842_DECOMPRESS=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_LZ4_COMPRESS=y
-CONFIG_LZ4HC_COMPRESS=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
-CONFIG_XZ_DEC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_BCJ=y
-# CONFIG_XZ_DEC_TEST is not set
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_LZ4=y
-CONFIG_DECOMPRESS_ZSTD=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_REED_SOLOMON=m
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_DEC16=y
-CONFIG_BCH=m
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_BTREE=y
-CONFIG_INTERVAL_TREE=y
-CONFIG_XARRAY_MULTI=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAS_DMA=y
-CONFIG_DMA_OPS=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_DMA_VIRT_OPS=y
-CONFIG_SWIOTLB=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_PERNUMA_CMA=y
-
-#
-# Default contiguous memory area size:
-#
-CONFIG_CMA_SIZE_MBYTES=0
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_ALIGNMENT=8
-# CONFIG_DMA_API_DEBUG is not set
-# CONFIG_DMA_MAP_BENCHMARK is not set
-CONFIG_SGL_ALLOC=y
-CONFIG_CHECK_SIGNATURE=y
-CONFIG_CPU_RMAP=y
-CONFIG_DQL=y
-CONFIG_GLOB=y
-# CONFIG_GLOB_SELFTEST is not set
-CONFIG_NLATTR=y
-CONFIG_LRU_CACHE=m
-CONFIG_CLZ_TAB=y
-CONFIG_IRQ_POLL=y
-CONFIG_MPILIB=y
-CONFIG_DIMLIB=y
-CONFIG_OID_REGISTRY=y
-CONFIG_UCS2_STRING=y
-CONFIG_HAVE_GENERIC_VDSO=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GENERIC_VDSO_TIME_NS=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_6x10 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-CONFIG_FONT_TER16x32=y
-CONFIG_FONT_6x8=y
-CONFIG_STACK_HASH_ORDER=16
-CONFIG_SG_POOL=y
-CONFIG_MEMREGION=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_SBITMAP=y
-CONFIG_PARMAN=m
-CONFIG_OBJAGG=m
-# CONFIG_STRING_SELFTEST is not set
-# end of Library routines
-
-CONFIG_PLDMFW=y
-
-#
-# Kernel hacking
-#
-
-#
-# printk and dmesg options
-#
-# CONFIG_PRINTK_TIME is not set
-# CONFIG_PRINTK_CALLER is not set
-CONFIG_STACKTRACE_BUILD_ID=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
-CONFIG_CONSOLE_LOGLEVEL_QUIET=4
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_DYNAMIC_DEBUG_CORE is not set
-CONFIG_SYMBOLIC_ERRNAME=y
-CONFIG_DEBUG_BUGVERBOSE=y
-# end of printk and dmesg options
-
-#
-# Compile-time checks and compiler options
-#
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_INFO_REDUCED is not set
-CONFIG_DEBUG_INFO_COMPRESSED=y
-# CONFIG_DEBUG_INFO_SPLIT is not set
-# CONFIG_DEBUG_INFO_NONE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-# CONFIG_DEBUG_INFO_DWARF4 is not set
-# CONFIG_DEBUG_INFO_DWARF5 is not set
-CONFIG_DEBUG_INFO_BTF=y
-CONFIG_MODULE_ALLOW_BTF_MISMATCH=y
-# CONFIG_GDB_SCRIPTS is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_FRAME_WARN=0
-CONFIG_STRIP_ASM_SYMS=y
-# CONFIG_READABLE_ASM is not set
-# CONFIG_HEADERS_INSTALL is not set
-# CONFIG_DEBUG_SECTION_MISMATCH is not set
-CONFIG_SECTION_MISMATCH_WARN_ONLY=y
-# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set
-# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
-CONFIG_VMLINUX_MAP=y
-CONFIG_FRAME_POINTER=y
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# end of Compile-time checks and compiler options
-
-#
-# Generic Kernel Debugging Instruments
-#
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
-CONFIG_MAGIC_SYSRQ_SERIAL=y
-CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_FS_ALLOW_ALL is not set
-# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
-# CONFIG_DEBUG_FS_ALLOW_NONE is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
-# CONFIG_UBSAN is not set
-# end of Generic Kernel Debugging Instruments
-
-# CONFIG_DEBUG_KERNEL is not set
-# CONFIG_DEBUG_MISC is not set
-
-#
-# Memory Debugging
-#
-# CONFIG_PAGE_EXTENSION is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
-# CONFIG_PAGE_OWNER is not set
-# CONFIG_PAGE_TABLE_CHECK is not set
-# CONFIG_PAGE_POISONING is not set
-# CONFIG_DEBUG_PAGE_REF is not set
-# CONFIG_DEBUG_RODATA_TEST is not set
-CONFIG_ARCH_HAS_DEBUG_WX=y
-CONFIG_DEBUG_WX=y
-CONFIG_GENERIC_PTDUMP=y
-CONFIG_PTDUMP_CORE=y
-# CONFIG_PTDUMP_DEBUGFS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SHRINKER_DEBUG is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_HAVE_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_SCHED_STACK_END_CHECK is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_ARCH_HAS_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_PER_CPU_MAPS is not set
-# CONFIG_DEBUG_KMAP_LOCAL is not set
-# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set
-# CONFIG_DEBUG_HIGHMEM is not set
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-# CONFIG_DEBUG_STACKOVERFLOW is not set
-CONFIG_CC_HAS_KASAN_GENERIC=y
-CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
-# CONFIG_KASAN is not set
-# end of Memory Debugging
-
-# CONFIG_DEBUG_SHIRQ is not set
-
-#
-# Debug Oops, Lockups and Hangs
-#
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=60
-# CONFIG_SOFTLOCKUP_DETECTOR is not set
-# CONFIG_HARDLOCKUP_DETECTOR is not set
-# CONFIG_DETECT_HUNG_TASK is not set
-# CONFIG_WQ_WATCHDOG is not set
-CONFIG_TEST_LOCKUP=m
-# end of Debug Oops, Lockups and Hangs
-
-#
-# Scheduler Debugging
-#
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHED_INFO=y
-CONFIG_SCHEDSTATS=y
-# end of Scheduler Debugging
-
-# CONFIG_DEBUG_TIMEKEEPING is not set
-# CONFIG_DEBUG_PREEMPT is not set
-
-#
-# Lock Debugging (spinlocks, mutexes, etc...)
-#
-# CONFIG_LOCK_DEBUGGING_SUPPORT is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
-# CONFIG_DEBUG_RWSEMS is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_DEBUG_ATOMIC_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_LOCK_TORTURE_TEST is not set
-# CONFIG_WW_MUTEX_SELFTEST is not set
-CONFIG_SCF_TORTURE_TEST=m
-# end of Lock Debugging (spinlocks, mutexes, etc...)
-
-CONFIG_STACKTRACE=y
-# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
-# CONFIG_DEBUG_KOBJECT is not set
-
-#
-# Debug kernel data structures
-#
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_PLIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BUG_ON_DATA_CORRUPTION is not set
-# end of Debug kernel data structures
-
-# CONFIG_DEBUG_CREDENTIALS is not set
-
-#
-# RCU Debugging
-#
-CONFIG_TORTURE_TEST=m
-CONFIG_RCU_SCALE_TEST=m
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_REF_SCALE_TEST=m
-CONFIG_RCU_CPU_STALL_TIMEOUT=60
-# CONFIG_RCU_TRACE is not set
-# CONFIG_RCU_EQS_DEBUG is not set
-# end of RCU Debugging
-
-# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-CONFIG_LATENCYTOP=y
-CONFIG_USER_STACKTRACE_SUPPORT=y
-CONFIG_NOP_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_FENTRY=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_RING_BUFFER=y
-CONFIG_EVENT_TRACING=y
-CONFIG_CONTEXT_SWITCH_TRACER=y
-CONFIG_TRACING=y
-CONFIG_GENERIC_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-CONFIG_FTRACE=y
-CONFIG_BOOTTIME_TRACING=y
-CONFIG_FUNCTION_TRACER=y
-# CONFIG_FUNCTION_GRAPH_TRACER is not set
-CONFIG_DYNAMIC_FTRACE=y
-CONFIG_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
-# CONFIG_FPROBE is not set
-CONFIG_FTRACE_RECORD_RECURSION=y
-CONFIG_FTRACE_RECORD_RECURSION_SIZE=128
-CONFIG_RING_BUFFER_RECORD_RECURSION=y
-# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
-CONFIG_FUNCTION_PROFILER=y
-CONFIG_STACK_TRACER=y
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_HWLAT_TRACER is not set
-# CONFIG_OSNOISE_TRACER is not set
-# CONFIG_TIMERLAT_TRACER is not set
-# CONFIG_MMIOTRACE is not set
-CONFIG_FTRACE_SYSCALLS=y
-# CONFIG_TRACER_SNAPSHOT is not set
-CONFIG_BRANCH_PROFILE_NONE=y
-# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
-# CONFIG_PROFILE_ALL_BRANCHES is not set
-CONFIG_BLK_DEV_IO_TRACE=y
-CONFIG_KPROBE_EVENTS=y
-# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set
-# CONFIG_UPROBE_EVENTS is not set
-CONFIG_BPF_EVENTS=y
-CONFIG_DYNAMIC_EVENTS=y
-CONFIG_PROBE_EVENTS=y
-CONFIG_BPF_KPROBE_OVERRIDE=y
-CONFIG_FTRACE_MCOUNT_RECORD=y
-# CONFIG_SYNTH_EVENTS is not set
-# CONFIG_HIST_TRIGGERS is not set
-# CONFIG_TRACE_EVENT_INJECT is not set
-# CONFIG_TRACEPOINT_BENCHMARK is not set
-# CONFIG_RING_BUFFER_BENCHMARK is not set
-# CONFIG_TRACE_EVAL_MAP_FILE is not set
-# CONFIG_FTRACE_STARTUP_TEST is not set
-# CONFIG_RING_BUFFER_STARTUP_TEST is not set
-CONFIG_PREEMPTIRQ_DELAY_TEST=m
-CONFIG_KPROBE_EVENT_GEN_TEST=m
-# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
-# CONFIG_SAMPLES is not set
-CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
-CONFIG_STRICT_DEVMEM=y
-# CONFIG_IO_STRICT_DEVMEM is not set
-
-#
-# x86 Debugging
-#
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-# CONFIG_EARLY_PRINTK_USB is not set
-CONFIG_X86_VERBOSE_BOOTUP=y
-# CONFIG_EARLY_PRINTK is not set
-# CONFIG_EARLY_PRINTK_DBGP is not set
-# CONFIG_EARLY_PRINTK_USB_XDBC is not set
-# CONFIG_EFI_PGT_DUMP is not set
-# CONFIG_DEBUG_TLBFLUSH is not set
-CONFIG_HAVE_MMIOTRACE_SUPPORT=y
-# CONFIG_X86_DECODER_SELFTEST is not set
-CONFIG_IO_DELAY_0X80=y
-# CONFIG_IO_DELAY_0XED is not set
-# CONFIG_IO_DELAY_UDELAY is not set
-# CONFIG_IO_DELAY_NONE is not set
-# CONFIG_DEBUG_BOOT_PARAMS is not set
-# CONFIG_CPA_DEBUG is not set
-# CONFIG_DEBUG_ENTRY is not set
-# CONFIG_DEBUG_NMI_SELFTEST is not set
-# CONFIG_X86_DEBUG_FPU is not set
-# CONFIG_PUNIT_ATOM_DEBUG is not set
-CONFIG_UNWINDER_FRAME_POINTER=y
-# CONFIG_UNWINDER_GUESS is not set
-# end of x86 Debugging
-
-#
-# Kernel Testing and Coverage
-#
-# CONFIG_KUNIT is not set
-# CONFIG_NOTIFIER_ERROR_INJECTION is not set
-CONFIG_FUNCTION_ERROR_INJECTION=y
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_MEMTEST=y
-# CONFIG_HYPERV_TESTING is not set
-# end of Kernel Testing and Coverage
-# end of Kernel hacking
-CONFIG_SURFACE_PLATFORMS=y
-CONFIG_SURFACE_GPE=m
-CONFIG_SURFACE_HOTPLUG=m
-CONFIG_SURFACE_PLATFORM_PROFILE=m
-CONFIG_SURFACE_AGGREGATOR=m
-CONFIG_SURFACE_AGGREGATOR_BUS=y
-# CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION is not set
-CONFIG_LITEX_SOC_CONTROLLER=m
-CONFIG_LITEX_SUBREG_SIZE=4
-# CONFIG_KFENCE is not set
-# CONFIG_DEBUG_IRQFLAGS is not set
-
-# CONFIG_WERROR is not set
-CONFIG_PRINTK_INDEX=y
-CONFIG_SOC_SAMA7G5=y
-CONFIG_SOC_LAN966=y
-CONFIG_DAMON=y
-CONFIG_DAMON_SYSFS=y
-CONFIG_DAMON_VADDR=y
-CONFIG_DAMON_PADDR=y
-CONFIG_DAMON_DBGFS=y
-CONFIG_DAMON_RECLAIM=y
-CONFIG_IPV6_IOAM6_LWTUNNEL=y
-CONFIG_NETFILTER_EGRESS=y
-CONFIG_MCTP=y
-CONFIG_PCIE_QCOM_EP=m
-CONFIG_PCIE_ROCKCHIP_DW_HOST=y
-CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
-CONFIG_ARM_SCMI_TRANSPORT_SMC=y
-# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
-CONFIG_HI6421V600_IRQ=m
-CONFIG_SCSI_UFS_HPB=y
-CONFIG_SCSI_UFS_HWMON=y
-CONFIG_AMT=m
-CONFIG_NET_VENDOR_ASIX=y
-CONFIG_SPI_AX88796C=m
-CONFIG_SPI_AX88796C_COMPRESSION=y
-CONFIG_CS89x0_PLATFORM=m
-CONFIG_ICE_SWITCHDEV=y
-CONFIG_ICE_HWTS=y
-CONFIG_NET_VENDOR_LITEX=y
-CONFIG_LITEX_LITEETH=m
-CONFIG_MAXLINEAR_GPHY=m
-CONFIG_MT7921S=m
-CONFIG_MT7921U=m
-CONFIG_RTW89=m
-CONFIG_RTW89_8852AE=m
-# CONFIG_RTW89_DEBUGMSG is not set
-CONFIG_RTW89_DEBUGFS=y
-CONFIG_MHI_WWAN_MBIM=m
-CONFIG_QCOM_BAM_DMUX=m
-CONFIG_KEYBOARD_CYPRESS_SF=m
-CONFIG_RPMSG_TTY=m
-CONFIG_IPMI_IPMB=m
-CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
-CONFIG_HW_RANDOM_CN10K=m
-CONFIG_I2C_VIRTIO=m
-CONFIG_SPI_CADENCE_XSPI=m
-CONFIG_SPI_ROCKCHIP_SFC=m
-CONFIG_PINCTRL_IMX8ULP=m
-CONFIG_PINCTRL_MDM9607=m
-CONFIG_PINCTRL_QCM2290=m
-CONFIG_PINCTRL_SM6115=m
-CONFIG_PINCTRL_SM6350=m
-CONFIG_PINCTRL_UNIPHIER_NX1=y
-CONFIG_GPIO_ROCKCHIP=m
-CONFIG_GPIO_VIRTIO=m
-CONFIG_POWER_RESET_TPS65086=y
-CONFIG_CHARGER_MT6360=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_CHARGER_CROS_PCHG=m
-CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m
-CONFIG_SENSORS_MAX6620=m
-CONFIG_SENSORS_SBRMI=m
-CONFIG_QCOM_LMH=m
-CONFIG_DB500_WATCHDOG=m
-CONFIG_MFD_RSMU_I2C=m
-CONFIG_MFD_RSMU_SPI=m
-CONFIG_REGULATOR_RTQ2134=m
-CONFIG_REGULATOR_RTQ6752=m
-CONFIG_IR_MESON_TX=m
-CONFIG_VIDEO_RCAR_ISP=m
-# CONFIG_VIDEO_ROCKCHIP_IEP is not set
-CONFIG_VIDEO_STKWEBCAM=m
-CONFIG_VIDEO_HI846=m
-CONFIG_VIDEO_HI847=m
-CONFIG_VIDEO_IMX335=m
-CONFIG_VIDEO_IMX412=m
-CONFIG_VIDEO_OV9282=m
-CONFIG_VIDEO_OV13B10=m
-# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
-CONFIG_DRM_PANEL_EDP=m
-CONFIG_DRM_PANEL_ILITEK_ILI9341=m
-CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
-CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
-CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
-CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
-CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
-CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
-CONFIG_SND_HDA_CODEC_CS8409=m
-CONFIG_SND_SOC_MT8195=m
-CONFIG_SND_SOC_CS35L41_SPI=m
-CONFIG_SND_SOC_CS35L41_I2C=m
-CONFIG_SND_SOC_ICS43432=m
-CONFIG_SND_SOC_MAX98520=m
-CONFIG_SND_SOC_RT9120=m
-CONFIG_SND_SOC_SDW_MOCKUP=m
-CONFIG_SND_SOC_NAU8821=m
-CONFIG_SND_AUDIO_GRAPH_CARD2=m
-CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
-CONFIG_SND_TEST_COMPONENT=m
-CONFIG_HID_XIAOMI=m
-CONFIG_HID_NINTENDO=m
-CONFIG_NINTENDO_FF=y
-CONFIG_RTC_DRV_MSC313=m
-# CONFIG_DMABUF_SYSFS_STATS is not set
-CONFIG_VDPA_USER=m
-CONFIG_COMMON_CLK_XLNX_CLKWZRD=m
-CONFIG_CLK_IMX8ULP=m
-CONFIG_CLK_IMX93=m
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_ASPEED_UART_ROUTING=m
-CONFIG_QCOM_SPM=m
-CONFIG_ADXL313_I2C=m
-CONFIG_ADXL313_SPI=m
-CONFIG_ADXL355_I2C=m
-CONFIG_ADXL355_SPI=m
-CONFIG_ADXL367_SPI=m
-CONFIG_ADXL367_I2C=m
-CONFIG_SCD4X=m
-CONFIG_SENSIRION_SGP40=m
-CONFIG_SENSEAIR_SUNRISE_CO2=m
-CONFIG_ADRF6780=m
-CONFIG_AD5110=m
-CONFIG_MAX31865=m
-CONFIG_MCHP_EIC=y
-# CONFIG_F2FS_IOSTAT is not set
-# CONFIG_F2FS_UNFAIR_RWSEM is not set
-CONFIG_SMB_SERVER=m
-CONFIG_SMB_SERVER_SMBDIRECT=y
-CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
-CONFIG_SMB_SERVER_KERBEROS5=y
-# CONFIG_ZERO_CALL_USED_REGS is not set
-CONFIG_XZ_DEC_MICROLZMA=y
-CONFIG_DMA_RESTRICTED_POOL=y
-# CONFIG_ANON_VMA_NAME is not set
-CONFIG_NET_9P_FD=m
-CONFIG_DEVTMPFS_SAFE=y
-CONFIG_GNSS_USB=m
-CONFIG_MTD_NAND_RENESAS=m
-CONFIG_NET_VENDOR_ENGLEDER=y
-CONFIG_TSNEP=m
-# CONFIG_TSNEP_SELFTESTS is not set
-CONFIG_LAN966X_SWITCH=m
-CONFIG_NET_VENDOR_VERTEXCOM=y
-CONFIG_MSE102X=m
-CONFIG_MCTP_SERIAL=m
-CONFIG_MCTP_TRANSPORT_I2C=m
-# CONFIG_WWAN_DEBUGFS is not set
-CONFIG_SERIAL_8250_PERICOM=m
-CONFIG_SPMI_MTK_PMIF=m
-CONFIG_PINCTRL_IMXRT1050=y
-CONFIG_PINCTRL_IMX93=m
-CONFIG_PINCTRL_SDX65=m
-CONFIG_PINCTRL_SM8450=m
-CONFIG_PINCTRL_SM8450_LPASS_LPI=m
-CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
-CONFIG_PINCTRL_SM8280XP_LPASS_LPI=m
-CONFIG_GPIO_SIM=m
-CONFIG_CHARGER_MAX77976=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_SENSORS_NZXT_SMART2=m
-CONFIG_SENSORS_DELTA_AHE50DC_FAN=m
-CONFIG_SENSORS_IR38064_REGULATOR=y
-CONFIG_SENSORS_MP5023=m
-CONFIG_SENSORS_INA238=m
-CONFIG_RZG2L_THERMAL=m
-CONFIG_RENESAS_RZG2LWDT=m
-CONFIG_REGULATOR_MAX20086=m
-CONFIG_VIDEO_STM32_DMA2D=m
-CONFIG_VIDEO_OV5693=m
-CONFIG_DRM_RCAR_USE_LVDS=y
-CONFIG_DRM_RCAR_USE_MIPI_DSI=y
-CONFIG_DRM_RCAR_MIPI_DSI=m
-CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
-CONFIG_DRM_PANEL_JDI_R63452=m
-CONFIG_DRM_PANEL_NOVATEK_NT35950=m
-CONFIG_DRM_PANEL_NOVATEK_NT35560=m
-CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
-CONFIG_TINYDRM_ILI9163=m
-CONFIG_SND_AMD_ACP_CONFIG=m
-CONFIG_SND_SOC_APPLE_MCA=m
-CONFIG_SND_SOC_AK4375=m
-CONFIG_SND_SOC_TLV320ADC3XXX=m
-CONFIG_HID_LETSKETCH=m
-CONFIG_LEDS_MT6360=m
-CONFIG_VIDEO_MAX96712=m
-CONFIG_COMMON_CLK_LAN966X=y
-CONFIG_COMMON_CLK_MT7986=y
-CONFIG_COMMON_CLK_MT7986_ETHSYS=y
-CONFIG_RENESAS_OSTM=y
-CONFIG_EXYNOS_USI=m
-CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
-CONFIG_AD74413R=m
-CONFIG_AD3552R=m
-CONFIG_AD7293=m
-CONFIG_ADMV1013=m
-CONFIG_ADMV1014=m
-CONFIG_ADMV4420=m
-CONFIG_PHY_MESON8_HDMI_TX=m
-CONFIG_PHY_FSL_IMX8M_PCIE=m
-CONFIG_PHY_FSL_LYNX_28G=m
-CONFIG_PHY_LAN966X_SERDES=m
-CONFIG_PHY_QCOM_EDP=m
-# CONFIG_CACHEFILES_ERROR_INJECTION is not set
-CONFIG_UNICODE_UTF8_DATA=m
-# CONFIG_NET_DEV_REFCNT_TRACKER is not set
-# CONFIG_NET_NS_REFCNT_TRACKER is not set
-# CONFIG_KFENCE is not set
-# CONFIG_FTRACE_SORT_STARTUP_TEST is not set
-CONFIG_BACKTRACE_VERBOSE=y
-CONFIG_ADMV8818=m
-CONFIG_MARVELL_CN10K_TAD_PMU=m
-# CONFIG_KCSAN is not set
-# CONFIG_BOOT_CONFIG_EMBED is not set
-CONFIG_INITRAMFS_PRESERVE_MTIME=y
-CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y
-CONFIG_ARCH_BCMBCA=y
-CONFIG_ARCH_HPE=y
-CONFIG_ARCH_HPE_GXP=y
-CONFIG_ARM_ERRATA_764319=y
-# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
-CONFIG_CAN_CTUCANFD_PCI=m
-CONFIG_CAN_CTUCANFD_PLATFORM=m
-CONFIG_FW_LOADER_COMPRESS_XZ=y
-CONFIG_FW_LOADER_COMPRESS_ZSTD=y
-CONFIG_FW_UPLOAD=y
-CONFIG_QCOM_SSC_BLOCK_BUS=y
-CONFIG_MHI_BUS_EP=m
-CONFIG_MTK_ADSP_IPC=m
-CONFIG_EFI_COCO_SECRET=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=m
-CONFIG_SFC_SIENA=m
-CONFIG_SFC_SIENA_MTD=y
-CONFIG_SFC_SIENA_MCDI_MON=y
-CONFIG_SFC_SIENA_SRIOV=y
-# CONFIG_SFC_SIENA_MCDI_LOGGING is not set
-CONFIG_ADIN1100_PHY=m
-CONFIG_DP83TD510_PHY=m
-CONFIG_WLAN_VENDOR_PURELIFI=y
-CONFIG_PLFXLC=m
-CONFIG_RTW89_8852CE=m
-CONFIG_WLAN_VENDOR_SILABS=y
-CONFIG_MTK_T7XX=m
-CONFIG_JOYSTICK_SENSEHAT=m
-CONFIG_INPUT_IQS7222=m
-# CONFIG_HVC_DCC_SERIALIZE_SMP is not set
-CONFIG_SPI_MTK_SNFI=m
-CONFIG_PINCTRL_IMXRT1170=y
-CONFIG_PINCTRL_SC7280_LPASS_LPI=m
-CONFIG_PINCTRL_SM8250_LPASS_LPI=m
-CONFIG_SENSORS_LAN966X=m
-CONFIG_SENSORS_NCT6775_I2C=m
-CONFIG_SENSORS_XDPE152=m
-CONFIG_RENESAS_RZN1WDT=m
-CONFIG_GXP_WATCHDOG=m
-CONFIG_REGULATOR_RT5759=m
-CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
-CONFIG_DRM_FSL_LDB=m
-CONFIG_DRM_LONTIUM_LT9211=m
-CONFIG_DRM_DW_HDMI_GP_AUDIO=m
-CONFIG_DRM_SSD130X_SPI=m
-CONFIG_SND_SERIAL_GENERIC=m
-CONFIG_SND_SOC_CS35L45_SPI=m
-CONFIG_SND_SOC_CS35L45_I2C=m
-CONFIG_SND_SOC_MAX98396=m
-CONFIG_SND_SOC_WM8731_I2C=m
-CONFIG_SND_SOC_WM8731_SPI=m
-CONFIG_SND_SOC_WM8940=m
-CONFIG_HID_MEGAWORLD_FF=m
-CONFIG_TYPEC_MUX_FSA4480=m
-CONFIG_LEDS_PWM_MULTICOLOR=m
-CONFIG_LEDS_QCOM_LPG=m
-CONFIG_TEGRA186_GPC_DMA=m
-# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set
-CONFIG_PWM_XILINX=m
-CONFIG_HTE=y
-# CONFIG_CACHEFILES_ONDEMAND is not set
-CONFIG_TRUSTED_KEYS_TPM=y
-CONFIG_TRUSTED_KEYS_TEE=y
-CONFIG_CRYPTO_SM3_GENERIC=m
-CONFIG_CRYPTO_SM4_GENERIC=m
-# CONFIG_FIPS_SIGNATURE_SELFTEST is not set
-CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y
-# CONFIG_DEBUG_NET is not set
-CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
-CONFIG_SPECULATION_MITIGATIONS=y
-CONFIG_EFI_DXE_MEM_ATTRIBUTES=y
-CONFIG_INTEL_MEI_GSC=m
-CONFIG_PINCTRL_AMD=y
-CONFIG_WINMATE_FM07_KEYS=m
-CONFIG_CHROMEOS_ACPI=m
-CONFIG_NVSW_SN2201=m
-CONFIG_DMARD06=m
-CONFIG_IIO_RESCALE=m
-CONFIG_DPOT_DAC=m
-CONFIG_VF610_DAC=m
-CONFIG_CM3605=m
-CONFIG_AK8974=m
-CONFIG_IIO_MUX=m
-# CONFIG_CGROUP_FAVOR_DYNMODS is not set
-CONFIG_ARCH_BCMBCA_CORTEXA7=y
-CONFIG_ARCH_BCMBCA_CORTEXA9=y
-CONFIG_ARCH_BCMBCA_BRAHMAB15=y
-CONFIG_ARCH_MSM8909=y
-CONFIG_ARCH_SUNPLUS=y
-CONFIG_SOC_SP7021=y
-# CONFIG_UNUSED_BOARD_FILES is not set
-# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
-CONFIG_DAMON_LRU_SORT=y
-CONFIG_NF_FLOW_TABLE_PROCFS=y
-CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
-CONFIG_PCI_EPF_VNTB=m
-CONFIG_ARM_SCMI_POWER_CONTROL=m
-CONFIG_BLK_DEV_UBLK=m
-CONFIG_NVME_AUTH=y
-CONFIG_NVME_TARGET_AUTH=y
-CONFIG_VCPU_STALL_DETECTOR=m
-CONFIG_SCSI_BUSLOGIC=m
-CONFIG_SCSI_FLASHPOINT=y
-CONFIG_AHCI_BRCM=m
-CONFIG_AHCI_DWC=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
-CONFIG_NET_VENDOR_WANGXUN=y
-CONFIG_NET_VENDOR_ADI=y
-CONFIG_ADIN1110=m
-CONFIG_NGBE=m
-CONFIG_TXGBE=m
-CONFIG_NET_VENDOR_SUNPLUS=y
-CONFIG_SP7021_EMAC=m
-CONFIG_CAN_NETLINK=y
-CONFIG_CAN_CAN327=m
-CONFIG_CAN_ESD_USB=m
-CONFIG_HW_RANDOM_BCM2835=m
-CONFIG_TCG_TIS_I2C=m
-# CONFIG_RANDOM_TRUST_CPU is not set
-CONFIG_I2C_BRCMSTB=m
-CONFIG_I2C_NPCM=m
-CONFIG_I2C_RZV2M=m
-CONFIG_SPI_BCM63XX_HSSPI=m
-CONFIG_SPI_GXP=m
-CONFIG_SPI_MICROCHIP_CORE=m
-CONFIG_SPI_MICROCHIP_CORE_QSPI=m
-CONFIG_SPI_SUNPLUS_SP7021=m
-CONFIG_PINCTRL_MSM8909=m
-CONFIG_PINCTRL_SM6375=m
-CONFIG_PINCTRL_SUN20I_D1=y
-CONFIG_SENSORS_LT7182S=m
-CONFIG_SUNPLUS_WATCHDOG=m
-CONFIG_VIDEO_SUN6I_MIPI_CSI2=m
-CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m
-CONFIG_VIDEO_AR0521=m
-CONFIG_DRM_PANEL_EBBG_FT8719=m
-CONFIG_DRM_TI_DLPC3433=m
-CONFIG_DRM_IMX8QM_LDB=m
-# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set
-CONFIG_RCU_NOCB_CPU_DEFAULT_ALL=y
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-# CONFIG_RV is not set
-CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT274=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT286=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT298=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567=m
-CONFIG_ANDROID_BINDER_IPC=m
-CONFIG_ANDROID_BINDERFS=y
-CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
-# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
-CONFIG_RANDSTRUCT_NONE=y
-# CONFIG_RANDSTRUCT_FULL is not set
-# Ethernet Power Sourcing Equipment Support
-CONFIG_PSE_CONTROLLER=y
-CONFIG_PSE_REGULATOR=m
-CONFIG_STAGING_MEDIA_DEPRECATED=y
-# CONFIG_FORCE_NR_CPUS is not set
-# CONFIG_DEBUG_MAPLE_TREE is not set
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_KERNEL_ZSTD=y
-# CONFIG_KMSAN is not set
diff --git a/kernel-6.19.patch b/kernel-6.19.patch
new file mode 100644
index 0000000..ec5a2d4
--- /dev/null
+++ b/kernel-6.19.patch
@@ -0,0 +1,235 @@
+diff -Nurp ./VirtualBox-kmod-7.2.6-build.orig/VirtualBox-kmod-7.2.6/VirtualBox-kmod-7.2.6/vboxdrv/linux/SUPDrv-linux.c ./VirtualBox-kmod-7.2.6-build/VirtualBox-kmod-7.2.6/VirtualBox-kmod-7.2.6/vboxdrv/linux/SUPDrv-linux.c
+--- a/drivers/virt/vboxdrv/linux/SUPDrv-linux.c	2026-01-27 12:57:17.000000000 +0000
++++ b/drivers/virt/vboxdrv/linux/SUPDrv-linux.c	2026-02-19 19:16:01.449067282 +0000
+@@ -190,6 +190,12 @@ static bool                 g_fEnabledHw
+ static int                  (*g_pfnKvmEnableVirtualization)(void);
+ /** Function pointer to kvm_disable_virtualization(). */
+ static void                 (*g_pfnKvmDisableVirtualization)(void);
++# if RTLNX_VER_MIN(6,19,0)
++/** Function pointer to cr4_update_irqsoff(). */
++static void                 (*g_pfnCr4UpdateIrqsoff)(unsigned long set, unsigned long clear);
++/** Function pointer to cr4_read_shadow(). */
++static unsigned long        (*g_pfnCr4ReadShadow)(void);
++# endif
+ /** Pointer to the KVM hardware specific module. */
+ struct module               *g_pKvmHwvirtModule;
+ #endif
+@@ -395,6 +401,28 @@ static int supdrvLinuxInitKvmSymbols(voi
+         void *pfnDisable = __symbol_get("kvm_disable_virtualization");
+         if (pfnDisable)
+         {
++# if RTLNX_VER_MIN(6,19,0)
++            void *pfnCr4UpdateIrqsoff = __symbol_get("cr4_update_irqsoff");
++            void *pfnRr4ReadShadow = __symbol_get("cr4_read_shadow");
++
++            if (   pfnCr4UpdateIrqsoff
++                && pfnRr4ReadShadow)
++            {
++                g_pfnCr4UpdateIrqsoff   = pfnCr4UpdateIrqsoff;
++                g_pfnCr4ReadShadow      = pfnRr4ReadShadow;
++
++                printk(KERN_INFO "vboxdrv: Found extra KVM hardware-virtualization symbols\n");
++            }
++            else
++            {
++                printk(KERN_WARNING "vboxdrv: Failed to find extra KVM hardware-virtualization symbols\n");
++
++                if (pfnCr4UpdateIrqsoff)
++                    symbol_put_addr(pfnCr4UpdateIrqsoff);
++                if (pfnRr4ReadShadow)
++                    symbol_put_addr(pfnRr4ReadShadow);
++            }
++#endif
+             /*
+              * Try to obtain a reference to kvm_intel/kvm_amd module in addition to the
+              * reference to the kvm module. If we fail, we will not try to use KVM for
+@@ -466,6 +494,18 @@ static void supdrvLinuxTermKvmSymbols(vo
+         symbol_put_addr(g_pfnKvmDisableVirtualization);
+         g_pfnKvmDisableVirtualization = NULL;
+     }
++# if RTLNX_VER_MIN(6,19,0)
++    if (g_pfnCr4UpdateIrqsoff)
++    {
++        symbol_put_addr(g_pfnCr4UpdateIrqsoff);
++        g_pfnCr4UpdateIrqsoff = NULL;
++    }
++    if (g_pfnCr4ReadShadow)
++    {
++        symbol_put_addr(g_pfnCr4ReadShadow);
++        g_pfnCr4ReadShadow = NULL;
++    }
++#endif
+     if (g_pKvmHwvirtModule)
+     {
+         module_put(g_pKvmHwvirtModule);
+@@ -1146,6 +1186,37 @@ SUPR0DECL(int) SUPDrvLinuxLdrDeregisterW
+ }
+ EXPORT_SYMBOL(SUPDrvLinuxLdrDeregisterWrappedModule);
+ 
++#if RTLNX_VER_MIN(5,8,0)
++/**
++ * Wrapper function for cr4_update_irqsoff() which was
++ * exported only for KVM starting from kernel 6.19.
++ */
++static void supdrvLinux_cr4_update_irqsoff(unsigned long set, unsigned long clear)
++{
++# if RTLNX_VER_MIN(6,19,0) && defined(SUPDRV_LINUX_HAS_KVM_HWVIRT_API)
++    if (g_pfnCr4UpdateIrqsoff)
++        g_pfnCr4UpdateIrqsoff(set, clear);
++# else
++    cr4_update_irqsoff(set, clear);
++# endif
++}
++
++/**
++ * Wrapper function for supdrvLinux_cr4_read_shadow() which was
++ * exported only for KVM starting from kernel 6.19.
++ */
++static unsigned long supdrvLinux_cr4_read_shadow(void)
++{
++    unsigned long cr4 = 0;
++# if RTLNX_VER_MIN(6,19,0) && defined(SUPDRV_LINUX_HAS_KVM_HWVIRT_API)
++    if (g_pfnCr4ReadShadow)
++        cr4 = g_pfnCr4ReadShadow();
++# else
++    cr4 = cr4_read_shadow();
++# endif
++    return cr4;
++}
++#endif /* 5.8.0 */
+ 
+ #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
+ RTCCUINTREG VBOXCALL supdrvOSChangeCR4(RTCCUINTREG fOrMask, RTCCUINTREG fAndMask)
+@@ -1153,10 +1224,10 @@ RTCCUINTREG VBOXCALL supdrvOSChangeCR4(R
+ # if RTLNX_VER_MIN(5,8,0)
+     unsigned long fSavedFlags;
+     local_irq_save(fSavedFlags);
+-    RTCCUINTREG const uOld = cr4_read_shadow();
+-    cr4_update_irqsoff(fOrMask, ~fAndMask); /* Same as this function, only it is not returning the old value. */
+-    AssertMsg(cr4_read_shadow() == ((uOld & fAndMask) | fOrMask),
+-              ("fOrMask=%#RTreg fAndMask=%#RTreg uOld=%#RTreg; new cr4=%#llx\n", fOrMask, fAndMask, uOld, cr4_read_shadow()));
++    RTCCUINTREG const uOld = supdrvLinux_cr4_read_shadow();
++    supdrvLinux_cr4_update_irqsoff(fOrMask, ~fAndMask); /* Same as this function, only it is not returning the old value. */
++    AssertMsg(supdrvLinux_cr4_read_shadow() == ((uOld & fAndMask) | fOrMask),
++              ("fOrMask=%#RTreg fAndMask=%#RTreg uOld=%#RTreg; new cr4=%#llx\n", fOrMask, fAndMask, uOld, supdrvLinux_cr4_read_shadow()));
+     local_irq_restore(fSavedFlags);
+ # else
+ #  if RTLNX_VER_MIN(3,20,0)
+diff -Nurp ./VirtualBox-kmod-7.2.6-build.orig/VirtualBox-kmod-7.2.6/VirtualBox-kmod-7.2.6/vboxdrv/r0drv/linux/initterm-r0drv-linux.c ./VirtualBox-kmod-7.2.6-build/VirtualBox-kmod-7.2.6/VirtualBox-kmod-7.2.6/vboxdrv/r0drv/linux/initterm-r0drv-linux.c
+--- a/drivers/virt/vboxdrv/r0drv/linux/initterm-r0drv-linux.c	2026-01-27 12:58:09.000000000 +0000
++++ b/drivers/virt/vboxdrv/r0drv/linux/initterm-r0drv-linux.c	2026-02-19 19:16:01.449602585 +0000
+@@ -60,6 +60,11 @@ static DECLARE_TASK_QUEUE(g_rtR0LnxWorkQ
+  * This is a special mm structure used to manage the kernel address space. */
+ struct mm_struct *g_pLnxInitMm = NULL;
+ 
++#if RTLNX_VER_MIN(6,19,0)
++/** Pointer to __flush_tlb_all kernel symbol. */
++void (*g_pfnLinuxFlushTlbAll)(void);
++#endif
++
+ 
+ /**
+  * Pushes an item onto the IPRT work queue.
+@@ -136,6 +141,11 @@ DECLHIDDEN(int) rtR0InitNative(void)
+             printk("rtR0InitNative: g_pLnxInitMm=%p\n", g_pLnxInitMm);
+ 
+             RTR0DbgKrnlInfoRelease(hKrnlInfo);
++# if RTLNX_VER_MIN(6,19,0)
++            g_pfnLinuxFlushTlbAll = __symbol_get("__flush_tlb_all");
++            if (!RT_VALID_PTR(g_pfnLinuxFlushTlbAll))
++                printk("rtR0InitNative: can't load __flush_tlb_all\n");
++# endif
+         }
+         else
+             printk("rtR0InitNative: RTR0DbgKrnlInfoOpen failed: %d\n", rc);
+@@ -151,6 +161,12 @@ DECLHIDDEN(void) rtR0TermNative(void)
+ {
+     IPRT_LINUX_SAVE_EFL_AC();
+ 
++# if RTLNX_VER_MIN(6,19,0)
++    if (RT_VALID_PTR(g_pfnLinuxFlushTlbAll))
++        symbol_put_addr(g_pfnLinuxFlushTlbAll);
++    g_pfnLinuxFlushTlbAll = NULL;
++#endif
++
+     rtR0LnxWorkqueueFlush();
+ #if RTLNX_VER_MIN(2,5,41)
+     destroy_workqueue(g_prtR0LnxWorkQueue);
+diff -Nurp ./VirtualBox-kmod-7.2.6-build.orig/VirtualBox-kmod-7.2.6/VirtualBox-kmod-7.2.6/vboxdrv/r0drv/linux/memobj-r0drv-linux.c ./VirtualBox-kmod-7.2.6-build/VirtualBox-kmod-7.2.6/VirtualBox-kmod-7.2.6/vboxdrv/r0drv/linux/memobj-r0drv-linux.c
+--- a/drivers/virt/vboxdrv/r0drv/linux/memobj-r0drv-linux.c	2026-01-27 12:58:09.000000000 +0000
++++ b/drivers/virt/vboxdrv/r0drv/linux/memobj-r0drv-linux.c	2026-02-19 19:16:01.449726162 +0000
+@@ -2108,6 +2108,17 @@ DECLHIDDEN(int) rtR0MemObjNativeMapUser(
+     return rc;
+ }
+ 
++#if defined(IPRT_USE_ALLOC_VM_AREA_FOR_EXEC) || defined(IPRT_USE_APPLY_TO_PAGE_RANGE_FOR_EXEC)
++static void rtR0MemObjLinuxFlushTlbAll(void)
++{
++# if RTLNX_VER_MIN(6,19,0)
++    if (RT_LIKELY(RT_VALID_PTR(g_pfnLinuxFlushTlbAll)))
++        g_pfnLinuxFlushTlbAll();
++# else
++    __flush_tlb_all();
++# endif
++}
++#endif
+ 
+ DECLHIDDEN(int) rtR0MemObjNativeProtect(PRTR0MEMOBJINTERNAL pMem, size_t offSub, size_t cbSub, uint32_t fProt)
+ {
+@@ -2128,7 +2139,7 @@ DECLHIDDEN(int) rtR0MemObjNativeProtect(
+             set_pte(papPtes[i], mk_pte(pMemLnx->apPages[i], fPg));
+         }
+         preempt_disable();
+-        __flush_tlb_all();
++        rtR0MemObjLinuxFlushTlbAll();
+         preempt_enable();
+         return VINF_SUCCESS;
+     }
+@@ -2174,7 +2185,7 @@ DECLHIDDEN(int) rtR0MemObjNativeProtect(
+             flush_icache_range((uintptr_t)pMemLnx->Core.pv + offSub, cbSub);
+ #  if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86) /* flush_tlb_kernel_range is not exported, but __flush_tlb_all is. */
+         preempt_disable();
+-        __flush_tlb_all();
++        rtR0MemObjLinuxFlushTlbAll();
+         preempt_enable();
+ #  else
+         flush_tlb_kernel_range((uintptr_t)pMemLnx->Core.pv + offSub, cbSub);
+diff -Nurp ./VirtualBox-kmod-7.2.6-build.orig/VirtualBox-kmod-7.2.6/VirtualBox-kmod-7.2.6/vboxdrv/r0drv/linux/the-linux-kernel.h ./VirtualBox-kmod-7.2.6-build/VirtualBox-kmod-7.2.6/VirtualBox-kmod-7.2.6/vboxdrv/r0drv/linux/the-linux-kernel.h
+--- a/drivers/virt/vboxdrv/r0drv/linux/the-linux-kernel.h	2026-01-27 12:58:10.000000000 +0000
++++ b/drivers/virt/vboxdrv/r0drv/linux/the-linux-kernel.h	2026-02-19 19:19:49.998078501 +0000
+@@ -512,6 +512,9 @@ RTDECL(struct page *) rtR0MemObjLinuxVir
+ 
+ 
+ extern struct mm_struct *g_pLnxInitMm;
++#if RTLNX_VER_MIN(6,19,0)
++extern void (*g_pfnLinuxFlushTlbAll)(void);
++#endif
+ 
+ 
+ #endif /* !IPRT_INCLUDED_SRC_r0drv_linux_the_linux_kernel_h */
+diff -Nurp ./VirtualBox-kmod-7.2.6-build.orig/VirtualBox-kmod-7.2.6/VirtualBox-kmod-7.2.6/vboxnetadp/r0drv/linux/the-linux-kernel.h ./VirtualBox-kmod-7.2.6-build/VirtualBox-kmod-7.2.6/VirtualBox-kmod-7.2.6/vboxnetadp/r0drv/linux/the-linux-kernel.h
+--- a/drivers/net/vboxnetadp/r0drv/linux/the-linux-kernel.h	2026-01-27 12:58:10.000000000 +0000
++++ b/drivers/net/vboxnetadp/r0drv/linux/the-linux-kernel.h	2026-02-19 19:19:49.998078501 +0000
+@@ -512,6 +512,9 @@ RTDECL(struct page *) rtR0MemObjLinuxVir
+ 
+ 
+ extern struct mm_struct *g_pLnxInitMm;
++#if RTLNX_VER_MIN(6,19,0)
++extern void (*g_pfnLinuxFlushTlbAll)(void);
++#endif
+ 
+ 
+ #endif /* !IPRT_INCLUDED_SRC_r0drv_linux_the_linux_kernel_h */
+diff -Nurp ./VirtualBox-kmod-7.2.6-build.orig/VirtualBox-kmod-7.2.6/VirtualBox-kmod-7.2.6/vboxnetflt/r0drv/linux/the-linux-kernel.h ./VirtualBox-kmod-7.2.6-build/VirtualBox-kmod-7.2.6/VirtualBox-kmod-7.2.6/vboxnetflt/r0drv/linux/the-linux-kernel.h
+--- a/drivers/net/vboxnetflt/r0drv/linux/the-linux-kernel.h	2026-01-27 12:58:10.000000000 +0000
++++ b/drivers/net/vboxnetflt/r0drv/linux/the-linux-kernel.h	2026-02-19 19:19:49.998078501 +0000
+@@ -512,6 +512,9 @@ RTDECL(struct page *) rtR0MemObjLinuxVir
+ 
+ 
+ extern struct mm_struct *g_pLnxInitMm;
++#if RTLNX_VER_MIN(6,19,0)
++extern void (*g_pfnLinuxFlushTlbAll)(void);
++#endif
+ 
+ 
+ #endif /* !IPRT_INCLUDED_SRC_r0drv_linux_the_linux_kernel_h */
diff --git a/kernel.spec b/kernel.spec
index 7c9b790..8b06402 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -20,16 +20,17 @@
 ## STOP: Adding weird and unsupported upstream kernel C/LD flags of any sort
 ## yes , including ftlo . O3 and whatever else
 
-# (crazy) , well that new way of doing buil-id symlinks
-# does not seems to work, see:
-# https://issues.openmandriva.org/show_bug.cgi?id=2400
-# let us try *old* way for kernel package(s)
-%global _build_id_links alldebug
+# Disable useless debug rpms as we generate our own debug package
+%define _enable_debug_packages %{nil}
+%define debug_package %{nil}
+%global __debug_package %{nil}
+%global __debug_install_post %{nil}
+%global _build_id_links none
 
 # Work around incomplete debug packages
 %global _empty_manifest_terminate_build 0
 
-%global cross_header_archs aarch64-linux armv7hnl-linux i686-linux x86_64-linux x32-linux riscv32-linux riscv64-linux aarch64-linuxmusl armv7hnl-linuxmusl i686-linuxmusl x86_64-linuxmusl x32-linuxmusl riscv32-linuxmusl riscv64-linuxmusl aarch64-android armv7l-android armv8l-android x86_64-android aarch64-linuxuclibc armv7hnl-linuxuclibc i686-linuxuclibc x86_64-linuxuclibc x32-linuxuclibc riscv32-linuxuclibc riscv64-linuxuclibc ppc64le-linux ppc64-linux ppc64le-linuxmusl ppc64-linuxmusl ppc64le-linuxuclibc ppc64-linuxuclibc
+%global cross_header_archs aarch64-linux armv7hnl-linux i686-linux x86_64-linux x32-linux riscv32-linux riscv64-linux aarch64-linuxmusl armv7hnl-linuxmusl i686-linuxmusl x86_64-linuxmusl x32-linuxmusl riscv32-linuxmusl riscv64-linuxmusl aarch64-android armv7l-android armv8l-android x86_64-android aarch64-linuxuclibc armv7hnl-linuxuclibc i686-linuxuclibc x86_64-linuxuclibc x32-linuxuclibc riscv32-linuxuclibc riscv64-linuxuclibc ppc64le-linux ppc64-linux ppc64le-linuxmusl ppc64-linuxmusl ppc64le-linuxuclibc ppc64-linuxuclibc loongarch64-linux loongarch64-linuxmusl loongarch64-linuxuclibc
 %global long_cross_header_archs %(
     for i in %{cross_header_archs}; do
 	CPU=$(echo $i |cut -d- -f1)
@@ -43,30 +44,31 @@
     && RPM_BUILD_NCPUS="$(/usr/bin/getconf _NPROCESSORS_ONLN)"; \\\
     [ "$RPM_BUILD_NCPUS" -gt 1 ] && echo "-P $RPM_BUILD_NCPUS")
 
-%define target_arch %(echo %{_arch} | sed -e 's/mips.*/mips/' -e 's/arm.*/arm/' -e 's/aarch64/arm64/' -e 's/x86_64/x86/' -e 's/i.86/x86/' -e 's/znver1/x86/' -e 's/riscv.*/riscv/' -e 's/ppc.*/powerpc/')
-
+%define target_arch %(echo %{_arch} | sed -e 's/mips.*/mips/' -e 's/arm.*/arm/' -e 's/aarch64/arm64/' -e 's/x86_64/x86/' -e 's/i.86/x86/' -e 's/znver1/x86/' -e 's/riscv.*/riscv/' -e 's/ppc.*/powerpc/' -e 's/loongarch64/loongarch/')
 
 # (tpg) define here per arch which kernel flavours you would like to build
-%ifarch %{aarch64}
+# we don't currently have gcc on loongarch64, enable all kernels when we do
+%ifarch %{loongarch64}
 %define kernel_flavours desktop server
 %else
 %define kernel_flavours desktop server desktop-gcc server-gcc
 %endif
+# possible options are: desktop server desktop-gcc server-gcc
 
 # (tpg) package these kernel modules as subpackages
 %ifarch %{aarch64}
-%define modules_subpackages appletalk decnet fddi can
+%define modules_subpackages appletalk fddi can adfs affs afs bfs coda efs freevxfs hfs hfsplus hpfs jfs minix ocfs2 omfs orangefs qnx4 qnx6
 %else
-%define modules_subpackages appletalk arcnet infiniband isdn can
+%define modules_subpackages appletalk arcnet comedi infiniband isdn can adfs affs afs bfs coda efs freevxfs hfs hfsplus hpfs jfs minix ocfs2 omfs orangefs qnx4 qnx6
 %endif
 
 # IMPORTANT
 # This is the place where you set kernel version i.e 4.5.0
 # compose tar.xz name and release
-%define kernelversion 6
-%define patchlevel 1
-%define sublevel 4
-#define relc 1
+%define kernelversion 7
+%define patchlevel 0
+%define sublevel 3
+#define relc 7
 
 # Having different top level names for packges means that you have to remove
 # them by hard :(
@@ -89,22 +91,26 @@
 
 # Build defines
 %bcond_with build_doc
-%bcond_with uksm
 
 %bcond_without build_source
 %bcond_without build_devel
 %bcond_without cross_headers
 
-%bcond_with lazy_developer
-%bcond_without build_debug
-%bcond_without clr
+%bcond_with build_debug
+%bcond_without evdi
 %bcond_without vbox_orig_mods
+%bcond_without clr
 # FIXME re-enable by default when the patches have been adapted to 5.8
 %bcond_with saa716x
 %bcond_with rtl8821ce
 # build perf and cpupower tools
-%bcond_without perf
+%if %{cross_compiling}
+%bcond_with bpftool
+%bcond_with perf
+%else
 %bcond_without bpftool
+%bcond_with perf
+%endif
 %bcond_without build_x86_energy_perf_policy
 %bcond_without build_turbostat
 %ifarch %{ix86} %{x86_64} %{aarch64}
@@ -129,11 +135,11 @@ Summary:	Linux kernel built for %{distribution}
 Name:		kernel%{?relc:-rc}
 Version:	%{kernelversion}.%{patchlevel}%{?sublevel:.%{sublevel}}
 Release:	%{?relc:0.rc%{relc}.}1
-License:	GPLv2
+License:	GPL-2.0
 Group:		System/Kernel and hardware
-ExclusiveArch:	%{ix86} %{x86_64} %{armx} %{riscv}
+ExclusiveArch:	%{ix86} %{x86_64} %{armx} %{riscv} %{loongarch64}
 ExclusiveOS:	Linux
-URL:		http://www.kernel.org
+URL:		https://www.kernel.org
 
 ####################################################################
 #
@@ -146,24 +152,45 @@ Source0:	https://git.kernel.org/torvalds/t/linux-%{kernelversion}.%{patchlevel}-
 Source0:	http://www.kernel.org/pub/linux/kernel/v%{kernelversion}.x/linux-%{kernelversion}.%{patchlevel}.tar.xz
 Source1:	http://www.kernel.org/pub/linux/kernel/v%{kernelversion}.x/linux-%{kernelversion}.%{patchlevel}.tar.sign
 %endif
+Source2:	https://github.com/Kimplul/hid-tmff2/archive/refs/heads/master.tar.gz#/hid-tmff2-20260310.tar.gz
 ### This is for stripped SRC RPM
 %if %{with build_nosrc}
 NoSource:	0
 %endif
 Source3:	README.kernel-sources
 Source4:	%{name}.rpmlintrc
+Source5:	https://github.com/linux-thinkpad/tp_smapi/releases/download/tp-smapi%2F0.45/tp_smapi-0.45.tgz
 ## all in one configs for each kernel
-Source10:	x86_64-desktop-gcc-omv-defconfig
-Source11:	x86_64-server-gcc-omv-defconfig
-Source12:	i686-desktop-gcc-omv-defconfig
-Source13:	i686-server-gcc-omv-defconfig
-Source14:	armv7hnl-desktop-omv-defconfig
-Source15:	armv7hnl-server-omv-defconfig
-Source16:	aarch64-desktop-omv-defconfig
-Source17:	aarch64-server-omv-defconfig
+Source10:	x86-omv-defconfig
+Source11:	i386-omv-defconfig
+Source12:	arm-omv-defconfig
+Source13:	arm64-omv-defconfig
+Source14:	riscv-omv-defconfig
+Source15:	powerpc-omv-defconfig
+Source16:	loongarch-omv-defconfig
+Source17:	generic-omv-defconfig
+# Fragments to be used with all/multiple kernel types
+Source20:	filesystems.fragment
+Source21:	framer.fragment
+Source22:	debug.fragment
+Source23:	networking.fragment
+Source24:	bluetooth.fragment
+Source25:	sensors.fragment
+Source26:	hid.fragment
+Source27:	nvme.fragment
+Source28:	modules.fragment
+Source29:	gcc-plugins.fragment
+Source30:	pps.fragment
+Source31:	cgroups.fragment
+Source32:	firmware.fragment
+Source33:	security.fragment
+Source34:	trace.fragment
+# Overrides (highest priority) for configs
+Source200:	znver1.overrides
+Source201:	temporary-workarounds.overrides
 # config and systemd service file from fedora
-Source30:	cpupower.service
-Source31:	cpupower.config
+Source300:	cpupower.service
+Source301:	cpupower.config
 
 # Patches
 # Numbers 0 to 9 are reserved for upstream patches
@@ -184,15 +211,18 @@ Source1000:	https://cdn.kernel.org/pub/linux/kernel/v%(echo %{version}|cut -d. -
 
 # FIXME git bisect shows upstream commit
 # 7a8b64d17e35810dc3176fe61208b45c15d25402 breaks
-# booting SynQuacer from USB flash drives.
+# booting SynQuacer from USB flash drives on old firmware
 # 9d55bebd9816903b821a403a69a94190442ac043 builds on
 # 7a8b64d17e35810dc3176fe61208b45c15d25402.
 Source1001:	revert-7a8b64d17e35810dc3176fe61208b45c15d25402.patch
 Source1002:	revert-9d55bebd9816903b821a403a69a94190442ac043.patch
 
+# FIXME bring this back when it's ported to 6.15
+#Patch30:	https://gitweb.gentoo.org/proj/linux-patches.git/plain/5010_enable-cpu-optimizations-universal.patch?h=6.7#/cpu-optimizations.patch
 Patch31:	die-floppy-die.patch
 Patch32:	0001-Add-support-for-Acer-Predator-macro-keys.patch
 Patch34:	kernel-5.6-kvm-gcc10.patch
+Patch35:	linux-6.7-BTF-deps.patch
 # Work around rpm dependency generator screaming about
 # error: Illegal char ']' (0x5d) in: 1.2.1[50983]_custom
 # caused by aacraid versioning ("1.2.1[50983]-custom")
@@ -203,28 +233,25 @@ Patch37:	socket.h-include-bitsperlong.h.patch
 # FIXME this may need porting, not sure where WC is set in 5.10
 #Patch38:	kernel-5.8-nouveau-write-combining-only-on-x86.patch
 Patch40:	kernel-5.8-aarch64-gcc-10.2-workaround.patch
+#Patch41:	tp_smapi-clang.patch
 # (tpg) https://github.com/ClangBuiltLinux/linux/issues/1341
 Patch42:	linux-5.11-disable-ICF-for-CONFIG_UNWINDER_ORC.patch
-
-# (tpg)
-# The Ultra Kernel Same Page Deduplication
-# http://kerneldedup.org/en/projects/uksm/download/
-# sources can be found here https://github.com/dolohow/uksm
-# Usually faster ports to new kernel releases can be found at
-# https://github.com/sirlucjan/kernel-patches/tree/master/5.16/uksm-patches
-%if %{with uksm}
-Patch43:	https://raw.githubusercontent.com/sirlucjan/kernel-patches/master/5.18/uksm-patches/0001-UKSM-for-5.18.patch
-%endif
+# Disabling rdseed breaks starting Qt applications
+# https://github.com/qt/qtbase/blob/dev/src/corelib/global/qsimd.cpp#L662-L672
+# Users don't appreaciate not being able to boot to a desktop
+# from which they can download the required BIOS update!
+Patch43:	dont-disable-rdseed.patch
 
 # (crazy) see: https://forum.openmandriva.org/t/nvme-ssd-m2-not-seen-by-omlx-4-0/2407
 Patch45:	Unknow-SSD-HFM128GDHTNG-8310B-QUIRK_NO_APST.patch
 # Restore ACPI loglevels to sane values
 Patch46:	https://gitweb.frugalware.org/wip_kernel/raw/86234abea5e625043153f6b8295642fd9f42bff0/source/base/kernel/acpi-use-kern_warning_even_when_error.patch
 Patch47:	https://gitweb.frugalware.org/wip_kernel/raw/23f5e50042768b823e18613151cc81b4c0cf6e22/source/base/kernel/fix-acpi_dbg_level.patch
-Patch48:	linux-5.4.5-fix-build.patch
 Patch51:	linux-5.5-corsair-strafe-quirks.patch
 Patch52:	http://crazy.dev.frugalware.org/smpboot-no-stack-protector-for-gcc10.patch
 Patch55:	linux-5.16-clang-no-attribute-symver.patch
+Patch60:	linux-6.18-clang.patch
+Patch61:	linux-6.19-acpi-clang.patch
 
 ### Additional hardware support
 ### TV tuners:
@@ -238,7 +265,7 @@ Source1003:	saa716x-driver.tar.xz
 Patch200:	0023-tda18212-Added-2-extra-options.-Based-on-CrazyCat-re.patch
 Patch201:	0075-cx24117-Use-a-pointer-to-config-instead-of-storing-i.patch
 Patch202:	0076-cx24117-Add-LNB-power-down-callback.-TBS6984-uses-pc.patch
-Patch203:	0124-Extend-FEC-enum.patch
+#Patch203:	0124-Extend-FEC-enum.patch
 Patch204:	saa716x-driver-integration.patch
 Patch205:	saa716x-4.15.patch
 Patch206:	saa716x-linux-4.19.patch
@@ -256,19 +283,42 @@ Patch209:	extra-wifi-drivers-port-to-5.6.patch
 # VirtualBox patches -- added as Source: rather than Patch:
 # because they need to be applied after stuff from the
 # virtualbox-kernel-module-sources package is copied around
-Source1005:	vbox-6.1-fix-build-on-znver1-hosts.patch
+# Based on https://github.com/rpmfusion/VirtualBox-kmod/raw/refs/heads/master/kernel-6.19.patch
+Source1005:	vbox-kernel-7.0.patch
 Source1007:	vboxnet-clang.patch
+Source1008:	vbox-modules-7.1.6-compile.patch
+Source1009:	vbox-modules-6.15.patch
+
+# EVDI Extensible Virtual Display Interface
+# Needed by DisplayLink cruft
+%define evdi_version 1.14.15
+Source1010:	https://github.com/DisplayLink/evdi/archive/refs/tags/v%{evdi_version}.tar.gz
+
+# Nexus -- BeOS like IPC, named semaphores, SHM, thread messaging, filesystem event notifications
+# https://github.com/Numerio/Nexus
+# https://v-os.dev/
+Source1020:	https://github.com/Numerio/Nexus/archive/refs/heads/main.tar.gz#/nexus-20260415.tar.gz
+Patch1021:	nexus-compile.patch
 
 # Assorted fixes
 
+# https://github.com/Kicksecure/tirdad
+Patch100:	security_tirdad.patch
+
 # Bring back ashmem -- anbox and waydroid still need it
 Patch211:	revert-721412ed3d819e767cac2b06646bf03aa158aaec.patch
 # Modular binder and ashmem -- let's try to make anbox happy
 Patch212:	https://salsa.debian.org/kernel-team/linux/raw/master/debian/patches/debian/android-enable-building-ashmem-and-binder-as-modules.patch
 Patch213:	https://salsa.debian.org/kernel-team/linux/raw/master/debian/patches/debian/export-symbols-needed-by-android-drivers.patch
+Patch216:	restore-exporting-symbols-needed-by-binder.patch
 
-Patch215:	linux-5.19-prefer-amdgpu-over-radeon.patch
+Patch214:	ras-fix-build-without-debugfs.patch
 Patch217:	acpi-chipset-workarounds-shouldnt-be-necessary-on-non-x86.patch
+# Revert minimum power limit lock on amdgpu. If you bought a GPU, it means you own it at every level. That a power of Free Software,
+# AMD cannot limit the right to own and prohibit people under volting/under power when they need it or when AMD cards are poorly designed to the point that they heat up, restart and cause very noisy operation.
+Patch218:	amdgpu-ignore-min-pcap.patch
+# Imported from Nobara. Enable full AMD GPU controls like fan speed etc (needed for corectrl and others)
+Patch219:	https://raw.githubusercontent.com/Nobara-Project/rpm-sources/main/baseos/kernel/6.7.6/0001-Set-amdgpu.ppfeaturemask-0xffffffff-as-default.patch
 
 # Fix CPU frequency governor mess caused by recent Intel patches
 Patch225:	https://gitweb.frugalware.org/frugalware-current/raw/50690405717979871bb17b8e6b553799a203c6ae/source/base/kernel/0001-Revert-cpufreq-Avoid-configuring-old-governors-as-de.patch
@@ -279,24 +329,19 @@ Patch230:	linux-5.11-perf-compile.patch
 #Patch231:	ce71038e673ee8291c64631359e56c48c8616dc7.patch
 
 # (tpg) Armbian ARM Patches
+# https://github.com/armbian/build/tree/main/patch/kernel/archive/
 Patch240:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/board-rockpro64-fix-emmc.patch
-Patch241:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/board-rockpro64-fix-spi1-flash-speed.patch
 Patch242:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/board-rockpro64-work-led-heartbeat.patch
 Patch243:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/general-fix-mmc-signal-voltage-before-reboot.patch
-Patch244:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/general-fix-inno-usb2-phy-init.patch
-Patch245:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/rk3399-unlock-temperature.patch
+Patch245:	https://github.com/armbian/build/raw/refs/heads/main/patch/kernel/archive/rockchip64-6.11/rk3399-unlock-temperature.patch
 Patch246:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/general-increasing_DMA_block_memory_allocation_to_2048.patch
-Patch247:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/general-rk808-configurable-switch-voltage-steps.patch
+Patch247:	https://raw.githubusercontent.com/armbian/build/main/patch/kernel/archive/rockchip64-6.5/general-rk808-configurable-switch-voltage-steps.patch
 Patch248:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/rk3399-sd-drive-level-8ma.patch
-Patch249:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch
 Patch250:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch
-Patch251:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/add-rockchip-iep-driver.patch
-Patch252:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/general-legacy-rockchip-hwrng.patch
-Patch253:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/general-legacy-rockchip-hwrng_5.10.patch
 Patch254:	https://raw.githubusercontent.com/armbian/build/master/patch/kernel/archive/rockchip64-6.0/rk3399-rp64-rng.patch
 
 # (tpg) Manjaro ARM Patches
-Patch260:	https://gitlab.manjaro.org/manjaro-arm/packages/core/linux/-/raw/master/1005-panfrost-Silence-Panfrost-gem-shrinker-loggin.patch
+#Patch260:	https://gitlab.manjaro.org/manjaro-arm/packages/core/linux/-/raw/master/1005-panfrost-Silence-Panfrost-gem-shrinker-loggin.patch
 
 # Other ARM64 patches
 Patch261:	https://raw.githubusercontent.com/immortalwrt/immortalwrt/master/target/linux/rockchip/patches-5.15/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch
@@ -306,8 +351,13 @@ Patch300:	add-board-orangepi-4.patch
 Patch303:	rk3399-add-sclk-i2sout-src-clock.patch
 #Patch304:	rtl8723cs-compile.patch
 Patch305:	kernel-6.0-rc2-perf-x86-compile.patch
+#Patch306:	linux-6.1-binutils-2.40.patch
 
-Patch350:	rtla-5.17-fix-make-clean.patch
+# V4L2 loopback
+# https://github.com/umlaeute/v4l2loopback
+Source400:	https://raw.githubusercontent.com/umlaeute/v4l2loopback/main/v4l2loopback.c
+Source401:	https://raw.githubusercontent.com/umlaeute/v4l2loopback/main/v4l2loopback.h
+Source402:	https://raw.githubusercontent.com/umlaeute/v4l2loopback/main/v4l2loopback_formats.h
 
 # Patches to external modules
 # Marked SourceXXX instead of PatchXXX because the modules
@@ -319,18 +369,81 @@ Patch350:	rtla-5.17-fix-make-clean.patch
 # https://github.com/clearlinux-pkgs/linux/
 Patch900:	0101-i8042-decrease-debug-message-level-to-info.patch
 Patch901:	0102-increase-the-ext4-default-commit-age.patch
-Patch902:	0103-silence-rapl.patch
 Patch903:	0104-pci-pme-wakeups.patch
 Patch904:	0105-ksm-wakeups.patch
-#Patch905:	0106-intel_idle-tweak-cpuidle-cstates.patch
 Patch907:	0108-smpboot-reuse-timer-calibration.patch
 Patch908:	0109-initialize-ata-before-graphics.patch
 Patch910:	0111-ipv4-tcp-allow-the-memory-tuning-for-tcp-to-go-a-lit.patch
 Patch913:	0117-migrate-some-systemd-defaults-to-the-kernel-defaults.patch
-Patch914:	0120-use-lfence-instead-of-rep-and-nop.patch
 %endif
 
-Autoreqprov:	no
+# Rockchip 3588 HDMI audio support
+# from https://github.com/andyshrk/linux
+# rk3588-hdmi-dsi-upstream-linux-6.13-rc1-2024-12-05 branch
+# Patches of the series that are commented out don't apply anymore and
+# need rebasing.
+Patch950:	https://github.com/torvalds/linux/commit/e0c5c98b4558d336ecb6b5a3c174816b4ed41db2.patch
+Patch951:	https://github.com/torvalds/linux/commit/cd6e4f6d8babdb5e65525c6dd2d1e373558b38ab.patch
+Patch952:	https://github.com/torvalds/linux/commit/4071b7a0642a41773d61b16ae1d02218bc25345e.patch
+Patch953:	https://github.com/torvalds/linux/commit/6da0ae6e419442449ffa7778de518ca37292352b.patch
+Patch954:	https://github.com/torvalds/linux/commit/d6aa52f8a15e56737de5e73f4f2acbb2632f43c0.patch
+Patch955:	https://github.com/torvalds/linux/commit/250083364dc2764b6ae61a124dfb8afc575e565a.patch
+Patch956:	https://github.com/torvalds/linux/commit/146008b9d4241d4e14e5b173038aa78262c2bbcd.patch
+Patch957:	https://github.com/torvalds/linux/commit/dad4c5aac3a74cf3593fad9f7c7d0e83ae96bfa5.patch
+Patch958:	https://github.com/torvalds/linux/commit/6d478d25de6b7550769b77edcbf8d330238542a8.patch
+Patch959:	https://github.com/torvalds/linux/commit/cc17a3358bece56c8932b6a62da242f841feb2e2.patch
+Patch960:	https://github.com/torvalds/linux/commit/bc1d59cd423b4a327af19bcd726f108f0f5a5da5.patch
+Patch961:	https://github.com/torvalds/linux/commit/00e0ee4050216dc768704c503860ac4ec82e7e41.patch
+#Patch962:	https://github.com/torvalds/linux/commit/839301464ba91c64483923c9a2a344b1c28e56ed.patch
+Patch963:	https://github.com/torvalds/linux/commit/0b7853f3fa5807bfcc193af0ebe4174fb7df21f3.patch
+#Patch964:	https://github.com/torvalds/linux/commit/dd3ada12c3f671e92f67416ba9c267e1b12ed29d.patch
+Patch965:	https://github.com/torvalds/linux/commit/725cb07d90c7949a971378635e7755ff9a54d25d.patch
+Patch966:	https://github.com/torvalds/linux/commit/046fbc970839b287d29053c7a1083e78eecb5822.patch
+#Patch967:	https://github.com/torvalds/linux/commit/f45ac0c8b0145582ba277f149a39ad386b0627b1.patch
+# 516ae4f... has landed
+Patch975:	https://github.com/torvalds/linux/commit/cef2dc6b338e1349b2e9feda9bf41e88510aaf5a.patch
+Patch976:	https://github.com/torvalds/linux/commit/0f13fb4aa5e9aec8fcc30d4cd244a1c94a9ab01f.patch
+Patch979:	https://github.com/torvalds/linux/commit/beba499cda3702062e7708b6b402d07b26d090e5.patch
+Patch981:	https://github.com/torvalds/linux/commit/c8699f87d802bbb6e5aab8292f2e285c56976a35.patch
+Patch982:	https://github.com/torvalds/linux/commit/a7a7cf522d7636dc1280adb1b1de7fe45f9b3305.patch
+Patch983:	https://github.com/torvalds/linux/commit/f0118748bc1f791775c90c52791a1770f4429702.patch
+# 4940862... has landed
+# 1e51ce4... has landed
+# aa868c1... has landed
+# 9d85b74... has landed
+# 2bd8528... has landed
+# 92bd2d2... has landed
+#Patch990:	https://github.com/torvalds/linux/commit/d3fd937a73e239efaf1ced03a5a10637e5ae9a95.patch
+#Patch991:	https://github.com/torvalds/linux/commit/57c6d683477d619dab36bc39ca5b3c011f4a1dab.patch
+#Patch992:	https://github.com/torvalds/linux/commit/ea0dd2c5e19d4c5e8d5109d78ac0d3ef1461fe43.patch
+# bf10475... has landed
+#Patch994:	https://github.com/torvalds/linux/commit/c1cffe7e472cf58c948a52de76007117e7d550ae.patch
+# 0ab95ab... has landed
+# bc27ea8... has landed
+# 565e00d... has landed
+Patch998:	https://github.com/torvalds/linux/commit/899558f6782528d5324322ae6e4c270e150c3d6f.patch
+# b5fb817... has landed
+#Patch1000:	https://github.com/torvalds/linux/commit/b35059eb51972524e48f13d9a6c39448bcd0874b.patch
+#Patch1001:	https://github.com/torvalds/linux/commit/6f0311441ab7b53cdcdf71b10d8a8594f1a47ef1.patch
+#Patch1002:	https://github.com/torvalds/linux/commit/d41ae3d5aa30f6ad8229967e9f97f9cf9d8527f9.patch
+# 6ebd774... has landed
+#Patch1004:	https://github.com/torvalds/linux/commit/353e6fcd1cd010ce89dd90a8cc5bcb506c362025.patch
+#Patch1005:	https://github.com/torvalds/linux/commit/52a77da4f18b009c85fbfd30701b93e5fe5e715a.patch
+#Patch1006:	https://github.com/torvalds/linux/commit/06fb8acf220d3bd8d1bffe098c41fbe398b36d07.patch
+# 2108e09... has landed
+# b76b3fe... has landed
+# 7fd2c93... has landed
+# de56911... has landed
+# c75314e... has landed
+# 8571e14... has landed
+#Patch1015:	https://github.com/torvalds/linux/commit/ec744b5548e79d18670651113a5855fd31e7472e.patch
+#Patch1016:	https://github.com/torvalds/linux/commit/05a7eca409973abbc3d97a726b88b07d256859ae.patch
+# 406e4c9... has landed
+Patch1019:	https://github.com/torvalds/linux/commit/dfb6b6ac7b8403a37c94e5afb0b990643409cbed.patch
+Source2000:	7.0-rc1-compile.patch
+Source2001:	7.0-rc1-compile-x86.patch
+
+BuildRequires:	make
 BuildRequires:	zstd
 BuildRequires:	findutils
 BuildRequires:	bc
@@ -338,6 +451,7 @@ BuildRequires:	flex
 BuildRequires:	bison
 BuildRequires:	binutils
 BuildRequires:	hostname
+BuildRequires:	gnutar
 BuildRequires:	clang
 BuildRequires:	llvm
 BuildRequires:	lld
@@ -359,8 +473,12 @@ BuildRequires:	pkgconfig(numa)
 
 # for cpupower
 %if %{with build_cpupower}
+# As of 6.6-rc5, cpupower's FR translation uses iso-8859-1
+BuildRequires:	locales-extra-charsets
 BuildRequires:	pkgconfig(libpci)
 %endif
+# (Unconditional because it's small and may also be used by other tools)
+BuildRequires:	gettext
 
 %if %{with build_turbostat}
 BuildRequires:	pkgconfig(libpcap)
@@ -401,6 +519,7 @@ BuildRequires:	pkgconfig(babeltrace2)
 BuildRequires:	jdk-current
 BuildRequires:	perl-devel
 BuildRequires:	perl(ExtUtils::Embed)
+BuildRequires:	%mklibname pfm
 %endif
 
 %ifarch %{arm}
@@ -412,9 +531,9 @@ BuildRequires:	uboot-mkimage
 # so end users don't have to install compilers (and worse,
 # get compiler error messages on failures)
 %ifarch %{x86_64}
-BuildRequires:	virtualbox-kernel-module-sources >= 6.1.38
+BuildRequires:	virtualbox-kernel-module-sources >= 7.2.6
 %if %{with vbox_orig_mods}
-BuildRequires:	virtualbox-guest-kernel-module-sources >= 6.1.38
+BuildRequires:	virtualbox-guest-kernel-module-sources >= 7.2.6
 %endif
 %endif
 
@@ -424,7 +543,9 @@ The kernel package contains the Linux kernel (vmlinuz), the core of your
 of the operating system: memory allocation, process allocation, device
 input and output, etc.
 
+#
 # (tpg) generate subpackages for kernel flavours
+#
 %(for flavour in %{kernel_flavours}; do
 	cat <<EOF
 %package -n %{name}-${flavour}
@@ -440,7 +561,7 @@ Provides:	kernel-release-${flavour}-clang
 Provides:	kernel-release-${flavour}-clang-%{version}-%{release}%{disttag} = %{version}-%{release}
 Provides:	kernel-release-${flavour}-clang%_isa = %{version}-%{release}
 %endif
-Requires(pre):	kmod >= 27-3
+Requires(posttrans):	kmod >= 27-3
 Recommends:	kernel-firmware
 Provides:	kernel = %{kernelversion}.%{patchlevel}
 Provides:	%{name} = %{version}-%{release}
@@ -484,8 +605,14 @@ Suggests:	microcode-intel
 
 %files -n %{name}-${flavour} -f kernel_files.${flavour}
 EOF
+done
+)
 
+#
+# kernel-devel
+#
 %if %{with build_devel}
+%(for flavour in %{kernel_flavours}; do
 	cat <<EOF
 %package -n %{name}-${flavour}-devel
 Summary:	The kernel-devel files for %{name}-${flavour}-%{version}-%{release}%{disttag}
@@ -506,7 +633,6 @@ Obsoletes:	%{name}-${flavour}-devel-latest <= %{version}-%{release}
 Provides:	installonlypkg(kernel)
 Requires:	%{name}-${flavour} = %{version}-%{release}
 %rename kernel-release-${flavour}-devel
-AutoReqProv:	no
 %ifarch %{ix86}
 Conflicts:	arch(x86_64)
 Conflicts:	arch(znver1)
@@ -525,9 +651,16 @@ If you want to build your own kernel, you need to install the full
 
 %files -n %{name}-${flavour}-devel -f kernel_devel_files.${flavour}
 EOF
-%endif # end build_devel
+done
+)
+# end build_devel
+%endif
 
+#
+# kernel-debuginfo
+#
 %if %{with build_debug}
+%(for flavour in %{kernel_flavours}; do
 	cat <<EOF
 %package -n %{name}-${flavour}-debuginfo
 Summary:	Files with debuginfo for %{name}-${flavour}-%{version}-%{release}%{disttag}
@@ -539,7 +672,6 @@ Provides:	kernel-${flavour}-%{version}-%{release}%{disttag}-debuginfo
 Provides:	installonlypkg(kernel)
 Requires:	%{name}-${flavour} = %{version}-%{release}
 %rename kernel-release-${flavour}-debuginfo
-AutoReqProv:	no
 %ifarch %{ix86}
 Conflicts:	arch(x86_64)
 Conflicts:	arch(znver1)
@@ -553,12 +685,15 @@ needs debugging info from the kernel, this package may help.
 
 %files -n %{name}-${flavour}-debuginfo -f kernel_debug_files.${flavour}
 EOF
-%endif  # end build_debug
 done
 )
+# end build_debug
+%endif
 
-%(
-for modules in %{modules_subpackages}; do
+#
+# kernel extra modules
+#
+%(for modules in %{modules_subpackages}; do
     for flavour in %{kernel_flavours}; do
 	cat <<EOF
 %package -n %{name}-${flavour}-modules-${modules}
@@ -566,13 +701,22 @@ Summary:	 ${modules} for kernel %{name}-${flavour}
 Group:		System/Kernel and hardware
 Requires:	%{name}-${flavour} = %{version}-%{release}
 Provides:	installonlypkg(kernel-module)
-AutoReq:	no
-AutoProv:	yes
+Requires(posttrans,postun):	kmod
+EOF
 
+	if [ "$modules" = "hfs" -a "${flavour}" = "desktop" ]; then
+		echo "Obsoletes: hfsutils < 3.2.6-42"
+	fi
+
+	cat <<EOF
 %description -n %{name}-${flavour}-modules-${modules}
 %{modules} modules for kernel %{name}-${flavour} .
 
+%postun -n %{name}-${flavour}-modules-${modules}
+[ -x %{_bindir}/depmod ] && %{_bindir}/depmod -A %{version}-$flavour-%{release}%{disttag}
+
 %files -n %{name}-${flavour}-modules-${modules}
+%optional %{_modulesdir}/%{version}-${flavour}-%{release}%{disttag}/kernel/fs/${modules}
 %optional %{_modulesdir}/%{version}-${flavour}-%{release}%{disttag}/kernel/net/${modules}
 %optional %{_modulesdir}/%{version}-${flavour}-%{release}%{disttag}/kernel/drivers/${modules}
 %optional %{_modulesdir}/%{version}-${flavour}-%{release}%{disttag}/kernel/drivers/net/${modules}
@@ -597,7 +741,6 @@ Requires:	make
 Requires:	gcc >= 7.2.1_2017.11-3
 Requires:	perl
 Requires:	diffutils
-Autoreqprov:	no
 Provides:	kernel-source = %{version}-%{release}
 Provides:	kernel-source-%{version}-%{release}%{disttag}
 Provides:	installonlypkg(kernel)
@@ -709,7 +852,7 @@ Source7004:	https://src.fedoraproject.org/rpms/hyperv-daemons/raw/rawhide/f/hype
 Source7005:	https://src.fedoraproject.org/rpms/hyperv-daemons/raw/rawhide/f/hypervfcopy.rules
 
 %description -n hyperv-tools
-Tools needed to communicate with a Hyper-V host
+Tools needed to communicate with a Hyper-V host.
 
 %files -n hyperv-tools
 %{_sbindir}/hv_kvp_daemon
@@ -718,7 +861,9 @@ Tools needed to communicate with a Hyper-V host
 %{_sbindir}/hv_vss_daemon
 %{_unitdir}/hypervvssd.service
 %{_udevrulesdir}/70-hypervvss.rules
-%{_sbindir}/hv_fcopy_daemon
+%ifarch %{x86_64}
+%{_sbindir}/hv_fcopy_uio_daemon
+%endif
 %{_unitdir}/hypervfcopyd.service
 %{_udevrulesdir}/70-hypervfcopy.rules
 %{_sbindir}/lsvmbus
@@ -726,10 +871,6 @@ Tools needed to communicate with a Hyper-V host
 %endif
 
 %if %{with bpftool}
-%define bpf_major 1
-%define libbpf %mklibname bpf %{bpf_major}
-%define libbpfdevel %mklibname bpf -d
-
 %package -n bpftool
 Summary:	Inspection and simple manipulation of eBPF programs and maps
 Group:		System/Kernel and hardware
@@ -737,22 +878,6 @@ Group:		System/Kernel and hardware
 %description -n bpftool
 This package contains the bpftool, which allows inspection and simple
 manipulation of eBPF programs and maps.
-
-%package -n %{libbpf}
-Summary:	The bpf library from kernel source
-Group:		System/Libraries
-
-%description -n %{libbpf}
-This package contains the kernel source bpf library.
-
-%package -n %{libbpfdevel}
-Summary:	Developement files for the bpf library from kernel source
-Group:		Development/Kernel
-Requires:	%{libbpf} = %{EVRD}
-
-%description -n %{libbpfdevel}
-This package includes libraries and header files needed for development
-of applications which use bpf library from kernel sour
 %endif
 
 %package headers
@@ -820,14 +945,75 @@ done
 #
 %prep
 
-%setup -q -n linux-%{kernelversion}.%{patchlevel}%{?relc:-rc%{relc}} -a 1003 -a 1004
+%setup -q -n linux-%{kernelversion}.%{patchlevel}%{?relc:-rc%{relc}} -a 2 -a 5 -a 1003 -a 1004 -a 1020
+%if %{with evdi}
+tar xf %{S:1010}
+%endif
 %if 0%{?sublevel:%{sublevel}}
 [ -e .git ] || git init
 xzcat %{SOURCE1000} |git apply - || git apply %{SOURCE1000}
 rm -rf .git
 %endif
+
+mv Nexus-main/nexus drivers/nexus
+rm drivers/nexus/CMakeLists.txt
+cat >>drivers/Makefile <<'EOF'
+obj-$(CONFIG_NEXUS) += nexus/
+EOF
+sed -i -e '/endmenu/i config NEXUS\n	tristate "BeOS-like IPC etc."\n	help\n	  BeOS like IPC, named semaphores, SHM, thread messaging and FS event notifications' drivers/Kconfig
+sed -i -e 's,obj-m,obj-$(CONFIG_NEXUS),g' drivers/nexus/Makefile
+rm -rf Nexus-main
+
+# uses --sort=name and other gnutar specific options
+sed -i -e '/\${TAR}/iTAR=gtar' kernel/gen_kheaders.sh
+sed -i -e 's, tar , gtar ,g' scripts/Makefile.package
+
+mv tp_smapi-*/*.{c,h} drivers/platform/x86
+cat >>drivers/platform/x86/Kconfig <<EOF
+config THINKPAD_EC
+	tristate "ThinkPad LPC Embedded Controller"
+	depends on X86
+	help
+	  This is a low-level driver for accessing the ThinkPad H8S embedded
+	  controller over the LPC bus (not to be confused with the ACPI Embedded
+	  Controller interface).
+
+config TP_SMAPI
+	tristate "ThinkPad SMAPI Support"
+	depends on X86
+	select THINKPAD_EC
+	default n
+	help
+	  This adds SMAPI support on Lenovo/IBM ThinkPads, for features such
+	  as battery charging control. For more information about this driver
+	  see <http://www.thinkwiki.org/wiki/tp_smapi>.
+
+	  If you have a Lenovo/IBM ThinkPad laptop, say Y or M here.
+
+config SENSORS_HDAPS
+	tristate "Thinkpad HDAPS sensor support"
+	depends on X86
+	select THINKPAD_EC
+	default n
+	help
+	  ThinkPad HDAPS sensor
+EOF
+cat >>drivers/platform/x86/Makefile <<EOF
+obj-\$(CONFIG_THINKPAD_EC) += thinkpad_ec.o
+obj-\$(CONFIG_TP_SMAPI) += tp_smapi.o
+obj-\$(CONFIG_SENSORS_HDAPS) += hdaps.o
+EOF
+rm -rf tp_smapi-*
+
 %autopatch -p1
 
+# Apparently, vm_clean was added in tools/Makefile before tools/vm was added
+if [ -d tools/vm ]; then
+	echo "Remove the vm_clean workaround, it should work now"
+	exit 1
+fi
+sed -i -e 's,vm_clean ,,' tools/Makefile
+
 %if %{with saa716x}
 # merge SAA716x DVB driver from extra tarball
 sed -i -e '/saa7164/isource "drivers/media/pci/saa716x/Kconfig"' drivers/media/pci/Kconfig
@@ -835,6 +1021,41 @@ sed -i -e '/saa7164/iobj-$(CONFIG_SAA716X_CORE) += saa716x/' drivers/media/pci/M
 find drivers/media/tuners drivers/media/dvb-frontends -name "*.c" -o -name "*.h" -type f | xargs sed -i -e 's,"dvb_frontend.h",<media/dvb_frontend.h>,g'
 %endif
 
+%if %{with evdi}
+# Merge EVDI
+mv evdi-%{evdi_version}/module drivers/gpu/drm/evdi
+rm -rf evdi-%{evdi_version}
+sed -i -e '/imagination/isource "drivers/gpu/drm/evdi/Kconfig"' drivers/gpu/drm/Kconfig
+# The dkms makefile is not really useful for a proper in-tree build
+cat >drivers/gpu/drm/evdi/Makefile <<'EOF'
+evdi-y := evdi_platform_drv.o evdi_platform_dev.o evdi_sysfs.o evdi_modeset.o evdi_connector.o evdi_encoder.o evdi_drm_drv.o evdi_fb.o evdi_gem.o evdi_painter.o evdi_params.o evdi_cursor.o evdi_debug.o evdi_i2c.o
+evdi-$(CONFIG_COMPAT) += evdi_ioc32.o
+obj-$(CONFIG_DRM_EVDI) := evdi.o
+EOF
+echo 'obj-$(CONFIG_DRM_EVDI) += evdi/' >>drivers/gpu/drm/Makefile
+%endif
+
+# Merge TMFF2
+mv hid-tmff2-* drivers/hid/tmff-new
+cat >drivers/hid/tmff-new/Kconfig <<'EOF'
+config HID_TMFF_NEW
+	tristate "Thrustmaster T300RS, T248, TX, TS-XV wheel support"
+	help
+	  A Linux kernel module for Thrustmaster T300RS, T248, and
+	  (experimental support) TX, TS-PC and TS-XV wheels.
+
+EOF
+cat >drivers/hid/tmff-new/Makefile <<'EOF'
+hid-tmff-new-y := src/hid-tmff2.o src/tmt248/hid-tmt248.o src/tmt300rs/hid-tmt300rs.o src/tmtspc/hid-tmtspc.o src/tmtsxw/hid-tmtsxw.o src/tmtx/hid-tmtx.o
+obj-$(CONFIG_HID_TMFF_NEW) += hid-tmff-new.o
+EOF
+cat >>drivers/hid/Kconfig <<'EOF'
+source "drivers/hid/tmff-new/Kconfig"
+EOF
+cat >>drivers/hid/Makefile <<'EOF'
+obj-$(CONFIG_HID_TMFF_NEW) += tmff-new/
+EOF
+
 %if %{with rtl8821ce}
 # Merge RTL8723DE and RTL8821CE drivers
 cd drivers/net/wireless
@@ -877,6 +1098,7 @@ config DRM_VBOXVIDEO
 EOF
 sed -i -e 's,\$(KBUILD_EXTMOD),drivers/gpu/drm/vboxvideo,g' drivers/gpu/drm/vboxvideo/Makefile*
 sed -i -e "s,^KERN_DIR.*,KERN_DIR := $(pwd)," drivers/gpu/drm/vboxvideo/Makefile*
+patch -p1 -z .1008~ -b <%{S:1008}
 %endif
 
 # 800x600 is too small to be useful -- even calamares doesn't
@@ -891,17 +1113,17 @@ sed -i -e 's|800, 600|1024, 768|g' drivers/gpu/drm/vboxvideo/vbox_mode.c
 cp -a $(ls --sort=time -1d /usr/src/virtualbox-*|head -n1)/vboxdrv drivers/virt/
 sed -i -e 's,\$(VBOXDRV_DIR),drivers/virt/vboxdrv/,g' drivers/virt/vboxdrv/Makefile*
 sed -i -e "s,^KERN_DIR.*,KERN_DIR := $(pwd)," drivers/virt/vboxdrv/Makefile*
-echo 'obj-m += vboxdrv/' >>drivers/virt/Makefile
+echo 'obj-$(CONFIG_VBOXGUEST) += vboxdrv/' >>drivers/virt/Makefile
 # VirtualBox network adapter
 cp -a $(ls --sort=time -1d /usr/src/virtualbox-*|head -n1)/vboxnetadp drivers/net/
 sed -i -e 's,\$(VBOXNETADP_DIR),drivers/net/vboxnetadp/,g' drivers/net/vboxnetadp/Makefile*
 sed -i -e "s,^KERN_DIR.*,KERN_DIR := $(pwd)," drivers/net/vboxnetadp/Makefile*
-echo 'obj-m += vboxnetadp/' >>drivers/net/Makefile
+echo 'obj-$(CONFIG_VBOXGUEST) += vboxnetadp/' >>drivers/net/Makefile
 # VirtualBox network filter
 cp -a $(ls --sort=time -1d /usr/src/virtualbox-*|head -n1)/vboxnetflt drivers/net/
 sed -i -e 's,\$(VBOXNETFLT_DIR),drivers/net/vboxnetflt/,g' drivers/net/vboxnetflt/Makefile*
 sed -i -e "s,^KERN_DIR.*,KERN_DIR := $(pwd)," drivers/net/vboxnetflt/Makefile*
-echo 'obj-m += vboxnetflt/' >>drivers/net/Makefile
+echo 'obj-$(CONFIG_VBOXGUEST) += vboxnetflt/' >>drivers/net/Makefile
 %if 0
 # VirtualBox PCI
 # https://forums.gentoo.org/viewtopic-t-1105508-start-0.html -- not very
@@ -910,18 +1132,51 @@ echo 'obj-m += vboxnetflt/' >>drivers/net/Makefile
 cp -a $(ls --sort=time -1d /usr/src/virtualbox-*|head -n1)/vboxpci drivers/pci/
 sed -i -e 's,\$(VBOXPCI_DIR),drivers/pci/vboxpci/,g' drivers/pci/vboxpci/Makefile*
 sed -i -e "s,^KERN_DIR.*,KERN_DIR := $(pwd)," drivers/pci/vboxpci/Makefile*
-echo 'obj-m += vboxpci/' >>drivers/pci/Makefile
+echo 'obj-$(CONFIG_VBOXGUEST) += vboxpci/' >>drivers/pci/Makefile
 %endif
 patch -p1 -z .1005~ -b <%{S:1005}
 patch -p1 -z .1007~ -b <%{S:1007}
+#patch -p1 -z .1009~ -b <%{S:1009}
 %endif
 
+# V4L2 loopback support
+cp %{S:401} %{S:402} include/media
+sed -e 's,"v4l2loopback.h",<media/v4l2loopback.h>,g;s,"v4l2loopback_formats.h",<media/v4l2loopback_formats.h>,g' %{S:400} >drivers/media/v4l2-core/v4l2loopback.c
+cat >>drivers/media/v4l2-core/Kconfig <<'EOF'
+
+config V4L2_LOOPBACK
+	tristate "Video4Linux loopback support"
+	help
+	  This module allows you to create "virtual video devices". Normal (v4l2)
+	  applications will read these devices as if they were ordinary video devices,
+	  but the video will not be read from e.g. a capture card but instead it is
+	  generated by another application.
+EOF
+cat >>drivers/media/v4l2-core/Makefile <<'EOF'
+
+obj-$(CONFIG_V4L2_LOOPBACK) += v4l2loopback.o
+EOF
+
+# Port to 6.15 -- FIXME remove once these drivers have been ported upstream
+sed -i -e 's,del_timer_sync,timer_delete_sync,g' drivers/media/pci/saa716x/saa716x_ff_ir.c drivers/media/v4l2-core/v4l2loopback.c drivers/platform/x86/hdaps.c drivers/net/wireless/rtl8723de/include/osdep_service.h drivers/net/wireless/rtl8723de/include/osdep_service_linux.h
+[ -e drivers/virt/vboxdrv/r0drv/linux/timer-r0drv-linux.c ] && sed -i -e 's,del_timer_sync,timer_delete_sync,g' drivers/virt/vboxdrv/r0drv/linux/timer-r0drv-linux.c
+
 # get rid of unwanted files
 find . -name '*~' -o -name '*.orig' -o -name '*.append' -o -name '*.g*ignore' | %kxargs rm -f
 
 # fix missing exec flag on file introduced in 4.14.10-rc1
 chmod 755 tools/objtool/sync-check.sh
 
+%ifarch znver1 znver2 znver3
+# Workaround for https://github.com/llvm/llvm-project/issues/82431
+echo 'CFLAGS_ip6_input.o += -march=x86-64-v3' >>net/ipv6/Makefile
+%endif
+
+patch -p1 -z .2000~ -b <%{S:2000}
+%ifarch %{ix86} %{x86_64}
+patch -p1 -z .2001~ -b <%{S:2001}
+%endif
+
 %build
 %set_build_flags
 
@@ -929,29 +1184,23 @@ chmod 755 tools/objtool/sync-check.sh
 ### Functions definitions needed to build kernel
 ###
 
-CheckConfig() {
-
-    if [ ! -e $(pwd)/.config ]; then
-	printf '%s\n' "Kernel config in $(pwd) missing, killing the build."
-	exit 1
-    fi
-
-# (tpg) please add CONFIG that were carelessly enabled, while it is known these MUST be disabled
-    if grep -Fxq "CONFIG_RT_GROUP_SCHED=y" .config ; then
-	printf '%s\n' "Please stop enabling CONFIG_RT_GROUP_SCHED - this option is not recommended with systemd systemd/systemd#553, killing the build."
-	exit 1
-    fi
-# (tpg) kernel modules are compresed manually inside spec file
-    if ! grep -Fxq "CONFIG_MODULE_COMPRESS_NONE=y" .config ; then
-	printf '%s\n' "Please do not disable CONFIG_MODULE_COMPRESS_NONE=y or set any other module compression inside .config, as this will bloat main package instead of debuginfo subpackage, killing the build."
-	exit 1
-    fi
-# (tpg) stop enabling CONFIG_DEBUG_KERNEL
-    if grep -Fxq "CONFIG_DEBUG_KERNEL=y" .config ; then
-	printf '%s\n' "Please do not set CONFIG_DEBUG_KERNEL=y as this is relase build, and we are not developing kernel or its modules."
-	exit 1
-    fi
-}
+# (tpg) Please stop enabling CONFIG_RT_GROUP_SCHED - this option is not recommended with systemd systemd/systemd#553, killing the build."
+# (tpg) Please do not disable CONFIG_MODULE_COMPRESS_NONE=y or set any other module compression inside .config, as this will bloat main package instead of debuginfo subpackage, killing the build."
+# (tpg) Please do not set CONFIG_DEBUG_KERNEL=y as this is relase build, and we are not developing kernel or its modules."
+FIXED_CONFIGS=" --disable CONFIG_RT_GROUP_SCHED \
+%if %{without bpftool}
+	--disable CONFIG_DEBUG_INFO_BTF \
+	--disable CONFIG_DEBUG_INFO_BTF_MODULES \
+%endif
+%if %{with build_debug}
+	--disable CONFIG_DEBUG_INFO_NONE \
+	--enable CONFIG_DEBUG_INFO \
+%else
+	--enable CONFIG_DEBUG_INFO_NONE \
+	--disable CONFIG_DEBUG_INFO \
+%endif
+	--disable CONFIG_MODULE_COMPRESS_NONE \
+	--disable CONFIG_DEBUG_KERNEL "
 
 clangify() {
 	sed -i \
@@ -965,6 +1214,10 @@ clangify() {
 		-e '/^CONFIG_LD_IS_BFD=/d' \
 		-e '/^CONFIG_GCC_PLUGINS=/d' \
 		"$1"
+	# FIXME: CONFIG_CFI_CLANG and friends are turned off on x86_64
+	# because as of kernel 6.4.3 and VirtualBox 7.0, enabling any
+	# form of CFI breaks starting a VM in VirtualBox.
+	# If this ever gets fixed, CFI should be reenabled.
 	cat >>"$1" <<'EOF'
 CONFIG_CC_IS_CLANG=y
 CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
@@ -977,37 +1230,29 @@ CONFIG_INIT_STACK_NONE=y
 # CONFIG_LTO_NONE is not set
 # CONFIG_LTO_CLANG_FULL is not set
 CONFIG_LTO_CLANG_THIN=y
+%ifarch %{x86_64}
+# CONFIG_CFI_CLANG is not set
+# CONFIG_CFI_CLANG_SHADOW is not set
+# CONFIG_CFI_PERMISSIVE is not set
+%else
 CONFIG_CFI_CLANG=y
+CONFIG_CFI_ICALL_NORMALIZE_INTEGERS=y
+CONFIG_CFI_AUTO_DEFAULT=y
 CONFIG_CFI_CLANG_SHADOW=y
 CONFIG_CFI_PERMISSIVE=y
+%endif
 CONFIG_RELR=y
 EOF
 }
 
-amdify() {
-	# Yes, it is intentional that CONFIG_AMD_NUMA gets disabled
-	# for the AMD kernel -- AMD_NUMA is only for pre-ACPI systems
-	# such as initial Opterons. Not useful for current AMD boxes.
+serverize() {
 	sed -i -E \
-		-e 's/^CONFIG_GENERIC_CPU=y/# CONFIG_GENERIC_CPU is not set/' \
-		-e 's/^# CONFIG_MZEN is not set/CONFIG_MZEN=y/' \
-		-e '/CONFIG_HAVE_INTEL_TXT/d' \
-		-e 's/^CONFIG_X86_INTEL_LPSS=y/# CONFIG_X86_INTEL_LPSS is not set/' \
-		-e 's/^CONFIG_CPU_SUP_(INTEL|CENTAUR|ZHAOXIN)=y/# CONFIG_CPU_SUP_\1 is not set/' \
-		-e 's/^CONFIG_X86_MCE_INTEL=y/# CONFIG_X86_MCE_INTEL is not set/' \
-		-e 's/^CONFIG_MICROCODE_INTEL=y/# CONFIG_MICROCODE_INTEL is not set/' \
-		-e 's/^CONFIG_X86_INTEL_PSTATE=y/# CONFIG_X86_INTEL_PSTATE is not set/' \
-		-e 's/^CONFIG_INTEL_IDLE=y/# CONFIG_INTEL_IDLE is not set/' \
-		-e 's/^CONFIG_INTEL_WMI(.*)=(y|m)/# CONFIG_INTEL_WMI\1 is not set/' \
-		-e 's,^CONFIG_SND_SOC_INTEL(.*)=.*,# CONFIG_SND_SOC_INTEL\1 is not set,' \
-		-e 's,^CONFIG_SND_SOC_SOF_INTEL(.*)=.*,# CONFIG_SND_SOC_SOF_INTEL\1 is not set,' \
-		-e 's,^CONFIG_AMD_NUMA=y,# CONFIG_AMD_NUMA is not set,' \
-		-e 's,^CONFIG_KVM_INTEL=m,# CONFIG_KVM_INTEL is not set,' \
-		-e 's,^CONFIG_INTEL_SOC(.*)=(y|m),# CONFIG_INTEL_SOC\1 is not set,' \
-		-e 's,^CONFIG_AGP_(INTEL|SIS|VIA)=(y|m),# CONFIG_AGP_\1 is not set,' \
-		-e 's,^CONFIG_PECI=(y|m),# CONFIG_PECI is not set,' \
-		-e 's,^CONFIG_INTEL_TDX_GUEST=(y|m),# CONFIG_INTEL_TDX_GUEST is not set,' \
-		-e 's,^CONFIG_INTEL_IFS=(y|m),# CONFIG_INTEL_IFS is not set,' \
+		-e 's/^CONFIG_PREEMPT=y/# CONFIG_PREEMPT is not set/' \
+		-e 's/^# CONFIG_PREEMPT_NONE is not set/CONFIG_PREEMPT_NONE=y/' \
+		-e 's/CONFIG_HZ_1000=y/# CONFIG_HZ_1000 is not set/' \
+		-e 's/^CONFIG_HZ_100 is not set/CONFIG_HZ_100=y/' \
+		-e 's/^CONFIG_HZ=1000/CONFIG_HZ=100/' \
+		-e 's/^CONFIG_MODIFY_LDT_SYSCALL=y/# CONFIG_MODIFY_LDT_SYSCALL is not set/' \
 		"$1"
 }
 
@@ -1015,147 +1260,93 @@ CreateConfig() {
 	arch="$1"
 	type="$2"
 	config_dir=%{_sourcedir}
-	CONFIGS=""
 	rm -fv .config
 
 	printf '%s\n' "<-- Creating config for kernel type ${type} for ${arch}"
-	if echo $type |grep -qv gcc; then
-		CC=clang
-		CXX=clang++
-		BUILD_LD="ld.lld --icf=none --no-gc-sections"
-		BUILD_KBUILD_LDFLAGS="-Wl,--icf=none -Wl,--no-gc-sections"
-		BUILD_TOOLS='LLVM=1 LLVM_IAS=1'
-	else
+	if printf '%s' ${type} | grep -q gcc; then
+%if %{cross_compiling}
+		CC=%{_target_platform}-gcc
+		CXX=%{_target_platform}-g++
+%else
 		CC=gcc
 		CXX=g++
-		# force ld.bfd, Kbuild logic issues when ld is linked  to something else
+%endif
+		HCC=gcc
+		HCXX=g++
+		# force ld.bfd, Kbuild logic issues when ld is linked to something else
 		BUILD_LD="%{_target_platform}-ld.bfd"
 		BUILD_KBUILD_LDFLAGS="-fuse-ld=bfd"
 		BUILD_TOOLS=""
+	else
+		CC=clang
+		CXX=clang++
+		HCC=clang
+		HCXX=clang++
+		# Workaround for LLD 16 BTF generation problem
+		#BUILD_LD=ld.bfd
+		#BUILD_KBUILD_LDFLAGS="-fuse-ld=bfd"
+		BUILD_LD="ld.lld --icf=none --no-gc-sections"
+		BUILD_KBUILD_LDFLAGS="-Wl,--icf=none -Wl,--no-gc-sections"
+%ifarch %{aarch64}
+		# Using objcopy rather than llvm-objcopy is a workaround for a BTF
+		# generation problem on aarch64
+		BUILD_TOOLS='LLVM=1 LLVM_IAS=1 OBJCOPY=objcopy'
+%else
+		# Using objcopy rather than llvm-objcopy is a workaround for a BTF
+		# generation problem on aarch64
+		BUILD_TOOLS='LLVM=1 LLVM_IAS=1'
+%endif
 	fi
 
 # (crazy) do not use %{S:X} to copy, if someone messes up we end up with broken stuff again
-	case ${arch} in
-	i?86)
-		case ${type} in
-		desktop|desktop-gcc)
-			rm -rf .config
-			cp -v ${config_dir}/i686-desktop-gcc-omv-defconfig .config
-			echo ${type} |grep -qv gcc && clangify .config
-			;;
-		server|server-gcc)
-			rm -rf .config
-			cp -v ${config_dir}/i686-server-gcc-omv-defconfig .config
-			echo ${type} |grep -qv gcc && clangify .config
-			;;
-		*)
-			printf '%s\n' "ERROR: no such type ${type} for ${arch}"
-			exit 1
-			;;
-		esac
-		;;
-	x86_64|x86|znver1)
-		case ${type} in
-		desktop|desktop-gcc)
-			rm -rf .config
-			cp -v ${config_dir}/x86_64-desktop-gcc-omv-defconfig .config
-			[ "${arch}" = "znver1" ] && amdify .config
-			echo ${type} |grep -qv gcc && clangify .config
-			;;
-		server|server-gcc)
-			rm -rf .config
-			cp -v ${config_dir}/x86_64-server-gcc-omv-defconfig .config
-			[ "${arch}" = "znver1" ] && amdify .config
-			echo ${type} |grep -qv gcc && clangify .config
-			;;
-		*)
-			printf '%s\n' "ERROR: no such type ${type} for ${arch}"
-			exit 1
-			;;
-		esac
-		;;
-	arm)
-		case ${type} in
-		desktop|desktop-gcc)
-			rm -rf .config
-			cp -v ${config_dir}/armv7hnl-desktop-omv-defconfig .config
-			echo ${type} |grep -qv gcc && clangify .config
-			;;
-		server|server-gcc)
-			rm -rf .config
-			cp -v ${config_dir}/armv7hnl-desktop-omv-defconfig .config
-			echo ${type} |grep -qv gcc && clangify .config
-			;;
-		*)
-			printf '%s\n' "ERROR: no such type ${type} for ${arch}"
-			exit 1
-			;;
-		esac
-		;;
-	arm64)
-		case ${type} in
-		desktop|desktop-gcc)
-			rm -rf .config
-			cp -v ${config_dir}/aarch64-desktop-omv-defconfig .config
-			echo ${type} |grep -qv gcc && clangify .config
-			;;
-		server|server-gcc)
-			rm -rf .config
-			cp -v ${config_dir}/aarch64-server-omv-defconfig .config
-			echo ${type} |grep -qv gcc && clangify .config
-			;;
-		*)
-			printf '%s\n' "ERROR: no such type ${type} for ${arch}"
-			exit 1
-			;;
-		esac
+	EXTRAFRAGMENTS=""
+	cfgarch="${arch}"
+	case "${cfgarch}" in
+	x86_64|znver1)
+		arch=x86
 		;;
-	ppc64)
-		CONFIGS=pseries_defconfig
+	ppc*)
+		arch=powerpc
+		if echo %{_target_cpu} |grep -q le; then
+			EXTRAFRAGMENTS=arch/powerpc/configs/le.config
+		fi
 		;;
-	ppc64le)
-		CONFIGS="pseries_defconfig arch/powerpc/configs/le.config"
+	loongarch64)
+		arch=loongarch
 		;;
-	*)
-		CONFIGS=defconfig
+	i?86)
+		arch=i386
 		;;
 	esac
+	BASECONFIG=${config_dir}/${arch}-omv-defconfig
 
-# ( crazy) remove along with the old configs once ARM* and ppc* is finished
-	if [[ -n ${CONFIGS} ]]; then
-		for i in common common-${type}; do
-			[ -e kernel/configs/$i.config ] && CONFIGS="$CONFIGS $i.config"
-		done
-		for i in ${arch}-common ${arch}-${type}; do
-			[ -e kernel/configs/$i.config ] && CONFIGS="$CONFIGS $i.config"
-		done
+	if [ ! -e ${BASECONFIG} ]; then
+		echo "======= No defconfig for ${arch} found! Generating it, please edit and \"git add\" it! ======="
+		sleep 10m
+		make ARCH=${arch} defconfig
+		cp .config ${config_dir}/${arch}-omv-defconfig
 	fi
-
-	cfgarch=$arch
-	if [ "$arch" = "znver1" ] || [ "$arch" = "x86_64" ]; then
-		arch=x86
-	elif echo $arch |grep -q ^ppc; then
-		arch=powerpc
+	[ -e ${config_dir}/${arch}.overrides ] && EXTRAFRAGMENTS="$EXTRAFRAGMENTS ${config_dir}/${arch}.overrides"
+	[ -e ${config_dir}/${cfgarch}.overrides ] && EXTRAFRAGMENTS="$EXTRAFRAGMENTS ${config_dir}/${cfgarch}.overrides"
+	[ -e ${config_dir}/temporary-workarounds.overrides ] && EXTRAFRAGMENTS="$EXTRAFRAGMENTS ${config_dir}/temporary-workarounds.overrides"
+	rm -f .config
+	scripts/kconfig/merge_config.sh -m ${BASECONFIG} %{_sourcedir}/generic-omv-defconfig %{_sourcedir}/*.fragment $EXTRAFRAGMENTS
+	printf '%s' ${type} | grep -q gcc || clangify .config
+	printf '%s' ${type} | grep -q server && serverize .config
+
+	if [ ! -e $(pwd)/.config ]; then
+		printf '%s\n' "Kernel config in $(pwd) missing, killing the build."
+		exit 1
 	fi
 
-# ( crazy) remove along with the old configs once ARM* and ppc* is finished
-	if [[ -n ${CONFIGS} ]]; then
-		make ARCH="${arch}" CC="$CC" HOSTCC="$CC" CXX="$CXX" HOSTCXX="$CXX" LD="$BUILD_LD" HOSTLD="$BUILD_LD" $BUILD_TOOLS KBUILD_HOSTLDFLAGS="$BUILD_KBUILD_LDFLAGS" V=0 $CONFIGS
-	else
-%if %{without lazy_developer}
-## YES, intentionally, DIE on wrong config
-		CheckConfig
-		make ARCH="${arch}" CC="$CC" HOSTCC="$CC" CXX="$CXX" HOSTCXX="$CXX" LD="$BUILD_LD" HOSTLD="$BUILD_LD" $BUILD_TOOLS KBUILD_HOSTLDFLAGS="$BUILD_KBUILD_LDFLAGS" V=0 oldconfig
-%else
-		printf '%s\n' "Lazy developer option is enabled!!. Don't be lazy!."
-## that takes kernel defaults on missing or changed things
-## olddefconfig is similar to yes ... but not that verbose
-		CheckConfig
-		yes "" | make ARCH="${arch}" CC="$CC" HOSTCC="$CC" CXX="$CXX" HOSTCXX="$CXX" LD="$BUILD_LD" HOSTLD="$BUILD_LD" $BUILD_TOOLS KBUILD_HOSTLDFLAGS="$BUILD_KBUILD_LDFLAGS" oldconfig
-%endif
-	fi
+# (tpg) apply our dynamic configs
+	scripts/config $FIXED_CONFIGS
+
+	printf '%s\n' "=== Configuring ${arch} ${type} kernel ==="
+	make ARCH="${arch}" CC="$CC" HOSTCC="$HCC" CXX="$CXX" HOSTCXX="$HCXX" LD="$BUILD_LD" HOSTLD="$BUILD_LD" $BUILD_TOOLS KBUILD_HOSTLDFLAGS="$BUILD_KBUILD_LDFLAGS" V=0 olddefconfig
 
 	scripts/config --set-val BUILD_SALT \"$(echo "$arch-$type-%{EVRD}"|sha1sum|awk '{ print $1; }')\"
+
 # " <--- workaround for vim syntax highlighting bug, ignore
 	cp .config kernel/configs/omv-${cfgarch}-${type}.config
 }
@@ -1179,38 +1370,58 @@ BuildKernel() {
 	KernelVer=$1
 	printf '%s\n' "<--- Building kernel $KernelVer"
 
-	if echo $1 |grep -qv gcc; then
-		CC=clang
-		CXX=clang++
-		BUILD_OPT_CFLAGS="-O3 %{pollyflags}"
-		BUILD_LD="ld.lld --icf=none --no-gc-sections"
-		BUILD_KBUILD_LDFLAGS="-Wl,--icf=none -Wl,--no-gc-sections"
-		BUILD_TOOLS='LLVM=1 LLVM_IAS=1'
-	else
+	if printf '%s' ${KernelVer} | grep -q gcc; then
+%if %{cross_compiling}
+		CC=%{_target_platform}-gcc
+		CXX=%{_target_platform}-g++
+%else
 		CC=gcc
 		CXX=g++
+%endif
+		HCC=gcc
+		HCXX=g++
 		BUILD_OPT_CFLAGS="-O3"
 # force ld.bfd, Kbuild logic issues when ld is linked  to something else
 		BUILD_LD="%{_target_platform}-ld.bfd"
 		BUILD_KBUILD_LDFLAGS="-fuse-ld=bfd"
 		BUILD_TOOLS=""
+	else
+		CC=clang
+		CXX=clang++
+		HCC=clang
+		HCXX=clang++
+		BUILD_OPT_CFLAGS="-O3 -Wno-unknown-warning-option %{pollyflags}"
+		# Workaround for LLD 16 BTF generation problem
+		#BUILD_LD=ld.bfd
+		#BUILD_KBUILD_LDFLAGS="-fuse-ld=bfd"
+		BUILD_LD="ld.lld --icf=none --no-gc-sections"
+		BUILD_KBUILD_LDFLAGS="-Wl,--icf=none -Wl,--no-gc-sections"
+%ifarch %{aarch64}
+		# Using objcopy rather than llvm-objcopy is a workaround for a BTF
+		# generation problem on aarch64
+		BUILD_TOOLS='LLVM=1 LLVM_IAS=1 OBJCOPY=objcopy'
+%else
+		BUILD_TOOLS='LLVM=1 LLVM_IAS=1'
+%endif
 	fi
 
 %ifarch %{arm}
 	IMAGE=zImage
-	TARGETS="${IMAGE} modules"
 %else
-%ifarch %{aarch64}
+%ifarch %{aarch64} %{riscv}
 # (tpg) when booting with UEFI then uboot-tools is looking for a vmlinuz in PE-COFF format
 	IMAGE=Image
-	TARGETS="${IMAGE} modules dtbs"
+	DTBS="dtbs"
+%else
+%ifarch %{loongarch64}
+	IMAGE=vmlinux.efi
 %else
 	IMAGE=bzImage
-	TARGETS="${IMAGE} modules"
 %endif
 %endif
-	# FIXME add KBUILD_CFLAGS="$BUILD_OPT_CFLAGS" once that actually works
-	%make_build V=0 VERBOSE=0 ARCH=%{target_arch} CC="$CC" HOSTCC="$CC" CXX="$CXX" HOSTCXX="$CXX" LD="$BUILD_LD" HOSTLD="$BUILD_LD" $BUILD_TOOLS KBUILD_HOSTLDFLAGS="$BUILD_KBUILD_LDFLAGS" $TARGETS
+%endif
+
+	%make_build V=0 VERBOSE=0 ARCH=%{target_arch} CC="$CC" HOSTCC="$HCC" CXX="$CXX" HOSTCXX="$HCXX" LD="$BUILD_LD" HOSTLD="$BUILD_LD" $BUILD_TOOLS KCFLAGS="$BUILD_OPT_CFLAGS" KBUILD_HOSTLDFLAGS="$BUILD_KBUILD_LDFLAGS" $IMAGE modules $DTBS
 
 # Start installing stuff
 	install -d %{temp_boot}
@@ -1225,18 +1436,35 @@ BuildKernel() {
 
 # modules
 	install -d %{temp_modules}/$KernelVer
-	%make_build V=0 VERBOSE=0 INSTALL_MOD_PATH=%{temp_root} ARCH=%{target_arch} SRCARCH=%{target_arch} KERNELRELEASE=$KernelVer CC="$CC" HOSTCC="$CC" CXX="$CXX" HOSTCXX="$CXX" LD="$BUILD_LD" HOSTLD="$BUILD_LD" $BUILD_TOOLS KBUILD_HOSTLDFLAGS="$BUILD_KBUILD_LDFLAGS" DEPMOD=/bin/true INSTALL_MOD_STRIP=1 modules_install
+	%make_build V=0 VERBOSE=0 INSTALL_MOD_PATH=%{temp_root} ARCH=%{target_arch} SRCARCH=%{target_arch} KERNELRELEASE=$KernelVer CC="$CC" HOSTCC="$HCC" CXX="$CXX" HOSTCXX="$HCXX" LD="$BUILD_LD" HOSTLD="$BUILD_LD" $BUILD_TOOLS KBUILD_HOSTLDFLAGS="$BUILD_KBUILD_LDFLAGS" DEPMOD=/bin/true INSTALL_MOD_STRIP=1 modules_install
 
 # headers
 	%make_build V=0 VERBOSE=0 INSTALL_HDR_PATH=%{temp_root}%{_prefix} KERNELRELEASE=$KernelVer ARCH=%{target_arch} SRCARCH=%{target_arch} headers_install
 
 %ifarch %{armx} %{ppc}
-	%make_build  V=0 VERBOSE=0 ARCH=%{target_arch} CC="$CC" HOSTCC="$CC" CXX="$CXX" HOSTCXX="$CXX" LD="$BUILD_LD" HOSTLD="$BUILD_LD" $BUILD_TOOLS KBUILD_HOSTLDFLAGS="$BUILD_KBUILD_LDFLAGS" INSTALL_DTBS_PATH=%{temp_modules}/$KernelVer/dtb dtbs_install
+	%make_build  V=0 VERBOSE=0 ARCH=%{target_arch} CC="$CC" HOSTCC="$HCC" CXX="$CXX" HOSTCXX="$HCXX" LD="$BUILD_LD" HOSTLD="$BUILD_LD" $BUILD_TOOLS KBUILD_HOSTLDFLAGS="$BUILD_KBUILD_LDFLAGS" INSTALL_DTBS_PATH=%{temp_modules}/$KernelVer/dtb dtbs_install
 	ln -s %{_modulesdir}/$KernelVer/dtb %{temp_boot}/dtb-$KernelVer
 %endif
 
 # remove /lib/firmware, we use a separate kernel-firmware
 	rm -rf %{temp_root}/lib/firmware
+
+# (tpg) strip modules out of debug bits
+	find %{temp_modules}/$KernelVer -name "*.ko" -type f > all_modules
+%if %{with build_debug}
+	cat all_modules | %kxargs -I '{}' objcopy --only-keep-debug '{}' '{}'.debug
+	cat all_modules | %kxargs -I '{}' sh -c 'cd $(dirname {}); objcopy --add-gnu-debuglink=$(basename {}).debug --strip-debug $(basename {})'
+%endif
+	cat all_modules | %kxargs -I '{}' strip --strip-debug {}
+
+# sign modules after stripping
+	cat all_modules | %kxargs -r -n16 sh -c "
+	    for mod; do
+		scripts/sign-file sha3-512 certs/signing_key.pem certs/signing_key.x509 \$mod
+		rm -f \$mod.sig \$mod.dig
+	    done
+	" DUMMYARG0
+	rm -rf all_modules
 }
 
 SaveDevel() {
@@ -1246,56 +1474,55 @@ SaveDevel() {
 	TempDevelRoot=%{temp_root}$DevelRoot
 
 	mkdir -p $TempDevelRoot
-	for i in $(find . -name 'Makefile*'); do cp -R --parents $i $TempDevelRoot;done
-	for i in $(find . -name 'Kconfig*' -o -name 'Kbuild*'); do cp -R --parents $i $TempDevelRoot;done
 	cp -fR include $TempDevelRoot
 	cp -fR scripts $TempDevelRoot
-	cp -fR kernel/time/timeconst.bc $TempDevelRoot/kernel/time/
-	cp -fR kernel/bounds.c $TempDevelRoot/kernel
-	cp -fR tools/include $TempDevelRoot/tools/
+	cp -fRu --parents $(find . -name 'Makefile*' -o -name 'Kconfig*' -o -name 'Kbuild*') $TempDevelRoot
+	cp -fRu kernel/time/timeconst.bc $TempDevelRoot/kernel/time/
+	cp -fRu kernel/bounds.c $TempDevelRoot/kernel
+	cp -fRu tools/include $TempDevelRoot/tools/
 %ifarch %{arm}
-	cp -fR arch/%{target_arch}/tools $TempDevelRoot/arch/%{target_arch}/
+	cp -fRu arch/%{target_arch}/tools $TempDevelRoot/arch/%{target_arch}/
 %endif
 
 %ifarch %{ix86} %{x86_64}
-	cp -fR arch/x86/kernel/asm-offsets.{c,s} $TempDevelRoot/arch/x86/kernel/
-	cp -fR arch/x86/kernel/asm-offsets_{32,64}.c $TempDevelRoot/arch/x86/kernel/
-	cp -fR arch/x86/purgatory/* $TempDevelRoot/arch/x86/purgatory/
-	cp -fR arch/x86/entry/syscalls/syscall* $TempDevelRoot/arch/x86/entry/syscalls/
-	cp -fR arch/x86/include $TempDevelRoot/arch/x86/
-	cp -fR arch/x86/tools $TempDevelRoot/arch/x86/
+	cp -fRu arch/x86/kernel/asm-offsets.{c,s} $TempDevelRoot/arch/x86/kernel/
+	cp -fRu arch/x86/kernel/asm-offsets_{32,64}.c $TempDevelRoot/arch/x86/kernel/
+	cp -fRu arch/x86/purgatory/* $TempDevelRoot/arch/x86/purgatory/
+	cp -fRu arch/x86/entry/syscalls/syscall* $TempDevelRoot/arch/x86/entry/syscalls/
+	cp -fRu arch/x86/include $TempDevelRoot/arch/x86/
+	cp -fRu arch/x86/tools $TempDevelRoot/arch/x86/
 %else
-	cp -fR arch/%{target_arch}/kernel/asm-offsets.{c,s} $TempDevelRoot/arch/%{target_arch}/kernel/
-	for f in $(find arch/%{target_arch} -name include); do cp -fR --parents $f $TempDevelRoot; done
+	cp -fRu arch/%{target_arch}/kernel/asm-offsets.{c,s} $TempDevelRoot/arch/%{target_arch}/kernel/
+	cp -fRu --parents $(find arch/%{target_arch} -name 'include') $TempDevelRoot;
 %endif
 
-	cp -fR .config Module.symvers $TempDevelRoot
+	cp -fRu .config Module.symvers $TempDevelRoot
 
 # Needed for truecrypt build (Danny)
-	cp -fR drivers/md/dm.h $TempDevelRoot/drivers/md/
+	cp -fRu drivers/md/dm.h $TempDevelRoot/drivers/md/
 
 # Needed for lirc_gpio (#39004)
-	cp -fR drivers/media/pci/bt8xx/bttv{,p}.h $TempDevelRoot/drivers/media/pci/bt8xx/
-	cp -fR drivers/media/pci/bt8xx/bt848.h $TempDevelRoot/drivers/media/pci/bt8xx/
-	cp -fR drivers/media/common/btcx-risc.h $TempDevelRoot/drivers/media/common/
+	cp -fRu drivers/media/pci/bt8xx/bttv{,p}.h $TempDevelRoot/drivers/media/pci/bt8xx/
+	cp -fRu drivers/media/pci/bt8xx/bt848.h $TempDevelRoot/drivers/media/pci/bt8xx/
+	cp -fRu drivers/media/pci/bt8xx/btcx-risc.h $TempDevelRoot/drivers/media/common/
 
 # Needed for external dvb tree (#41418)
-	cp -fR drivers/media/dvb-frontends/lgdt330x.h $TempDevelRoot/drivers/media/dvb-frontends/
+	cp -fRu drivers/media/dvb-frontends/lgdt330x.h $TempDevelRoot/drivers/media/dvb-frontends/
 
 # orc unwinder needs theese
-	cp -fR tools/build/Build{,.include} $TempDevelRoot/tools/build
-	cp -fR tools/build/fixdep.c $TempDevelRoot/tools/build
-	cp -fR tools/lib/{str_error_r.c,string.c} $TempDevelRoot/tools/lib
-	cp -fR tools/lib/subcmd/* $TempDevelRoot/tools/lib/subcmd
-	cp -fR tools/objtool/* $TempDevelRoot/tools/objtool
-	cp -fR tools/scripts/utilities.mak $TempDevelRoot/tools/scripts
+	cp -fRu tools/build/Build.include $TempDevelRoot/tools/build
+	cp -fRu tools/build/fixdep.c $TempDevelRoot/tools/build
+	cp -fRu tools/lib/{str_error_r.c,string.c} $TempDevelRoot/tools/lib
+	cp -fRu tools/lib/subcmd/* $TempDevelRoot/tools/lib/subcmd
+	cp -fRu tools/objtool/* $TempDevelRoot/tools/objtool
+	cp -fRu tools/scripts/utilities.mak $TempDevelRoot/tools/scripts
 
 # Make clean fails on the include statements in the Makefiles - and the drivers aren't relevant for -devel
 	rm -rf $TempDevelRoot/drivers/net/wireless/rtl8*
 	sed -i -e '/rtl8.*/d' $TempDevelRoot/drivers/net/wireless/{Makefile,Kconfig}
 	sed -i -e '/rtl8723cs.*/d' $TempDevelRoot/drivers/staging/{Makefile,Kconfig}
 
-	for i in alpha arc avr32 blackfin c6x cris csky frv h8300 hexagon ia64 loongarch m32r m68k m68knommu metag microblaze \
+	for i in alpha arc avr32 blackfin c6x cris csky frv h8300 hexagon ia64 m32r m68k m68knommu metag microblaze \
 		 mips mn10300 nds32 nios2 openrisc parisc s390 score sh sparc tile unicore32 xtensa; do
 		rm -rf $TempDevelRoot/arch/$i
 	done
@@ -1321,6 +1548,7 @@ SaveDevel() {
 $DevelRoot/Documentation
 $DevelRoot/arch/arm
 $DevelRoot/arch/arm64
+$DevelRoot/arch/loongarch
 $DevelRoot/arch/powerpc
 $DevelRoot/arch/riscv
 $DevelRoot/arch/um
@@ -1331,14 +1559,17 @@ $DevelRoot/crypto
 $DevelRoot/certs
 $DevelRoot/drivers
 $DevelRoot/fs
+$DevelRoot/include/Kbuild
 $DevelRoot/include/acpi
 $DevelRoot/include/asm-generic
 $DevelRoot/include/clocksource
 $DevelRoot/include/config
 $DevelRoot/include/crypto
+$DevelRoot/include/cxl
 $DevelRoot/include/drm
 $DevelRoot/include/dt-bindings
 $DevelRoot/include/generated
+%optional $DevelRoot/include/hyperv
 $DevelRoot/include/keys
 $DevelRoot/include/kunit
 $DevelRoot/include/kvm
@@ -1394,7 +1625,6 @@ if [ -d %{_modulesdir}/%{version}-$devel_flavour-%{release}%{disttag} ]; then
 fi
 EOF
 
-
 ### Create -devel Preun script on the fly
 cat > $kernel_devel_files-preun <<EOF
 if [ -L %{_modulesdir}/%{version}-$devel_flavour-%{release}%{disttag}/build ]; then
@@ -1418,18 +1648,7 @@ SaveDebug() {
 	install -m 644 vmlinux %{temp_boot}/vmlinux-%{version}-$debug_flavour-%{release}%{disttag}
 	kernel_debug_files=kernel_debug_files.$debug_flavour
 	printf '%s\n' "%{_bootdir}/vmlinux-%{version}-$debug_flavour-%{release}%{disttag}" >> $kernel_debug_files
-
-	find %{temp_modules}/%{version}-$debug_flavour-%{release}%{disttag}/kernel -name "*.ko" -type f | %kxargs -I '{}' objcopy --only-keep-debug '{}' '{}'.debug
-	find %{temp_modules}/%{version}-$debug_flavour-%{release}%{disttag}/kernel -name "*.ko" -type f | %kxargs -I '{}' sh -c 'cd $(dirname {}); objcopy --add-gnu-debuglink=$(basename {}).debug --strip-debug $(basename {})'
-	find %{temp_modules}/%{version}-$debug_flavour-%{release}%{disttag}/kernel -name "*.ko" -type f -exec strip --strip-debug {} +
-	find %{temp_modules}/%{version}-$debug_flavour-%{release}%{disttag}/kernel -name "*.ko" -type f |while read r; do
-# sign modules after stripping
-		scripts/sign-file sha1 certs/signing_key.pem certs/signing_key.x509 $r
-	done
-
-	cd %{temp_modules}
-	    find %{version}-$debug_flavour-%{release}%{disttag}/kernel -name "*.ko.debug" -type f > debug_module_list
-	cd -
+	find %{temp_modules}/%{version}-$debug_flavour-%{release}%{disttag}/kernel -name "*.ko.debug" -type f > %{temp_modules}/debug_module_list
 	cat %{temp_modules}/debug_module_list | sed 's|\(.*\)|%{_modulesdir}/\1|' >> $kernel_debug_files
 	cat %{temp_modules}/debug_module_list | sed 's|\(.*\)|%exclude %{_modulesdir}/\1|' >> ../kernel_exclude_debug_files.$debug_flavour
 	rm -f %{temp_modules}/debug_module_list
@@ -1449,9 +1668,26 @@ CreateFiles() {
 %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/config
 %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/vmlinuz
 %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/adfs
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/affs
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/afs
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/bfs
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/coda
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/efs
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/freevxfs
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/hfs
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/hfsplus
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/hpfs
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/jfs
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/minix
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/ocfs2
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/omfs
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/orangefs
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/qnx4
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/fs/qnx6
 %exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/net/appletalk
 %exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/net/can
-%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/net/decnet
+%exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/drivers/comedi
 %exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/drivers/infiniband
 %exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/drivers/isdn
 %exclude %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/kernel/drivers/net/arcnet
@@ -1466,7 +1702,7 @@ CreateFiles() {
 EOF
 
 %if %{with build_debug}
-    cat ../kernel_exclude_debug_files.$kernel_flavour >> $kernel_files
+cat ../kernel_exclude_debug_files.$kernel_flavour >> $kernel_files
 %endif
 
 ### Create kernel Posttrans script
@@ -1509,13 +1745,14 @@ EOF
 
 ### Create kernel Postun script on the fly
 cat > $kernel_files-postun <<EOF
-
+if [ "$1" = "0" ]; then
 [ -e %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag} ] && rm -rf %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag}/modules.{alias{,.bin},builtin.bin,dep{,.bin},devname,softdep,symbols{,.bin}} ||:
 [ -e /boot/vmlinuz-%{version}-$kernel_flavour-%{release}%{disttag} ] && rm -rf /boot/vmlinuz-%{version}-$kernel_flavour-%{release}%{disttag}
 [ -e /boot/initrd-%{version}-$kernel_flavour-%{release}%{disttag}.img ] && rm -rf /boot/initrd-%{version}-$kernel_flavour-%{release}%{disttag}.img
 [ -e /boot/System.map-%{version}-$kernel_flavour-%{release}%{disttag} ] && rm -rf /boot/System.map-%{version}-$kernel_flavour-%{release}%{disttag}
 [ -e /boot/config-%{version}-$kernel_flavour-%{release}%{disttag} ] && rm -rf /boot/config-%{version}-$kernel_flavour-%{release}%{disttag}
 [ -e /boot/dtb-%{version}-$kernel_flavour-%{release}%{disttag} ] && rm -rf /boot/dtb-%{version}-$kernel_flavour-%{release}%{disttag}
+fi
 
 %ifarch %{aarch64}
 if [ -d /boot/efi ] && [ -x %{_bindir}/kernel-install ]; then
@@ -1523,7 +1760,10 @@ if [ -d /boot/efi ] && [ -x %{_bindir}/kernel-install ]; then
 fi
 %endif
 
+if [ "$1" = "0" ]; then
 rm -rf %{_modulesdir}/%{version}-$kernel_flavour-%{release}%{disttag} >/dev/null
+fi
+
 if [ -d /var/lib/dkms ]; then
     rm -f /var/lib/dkms/*/kernel-%{version}-$devel_flavour-%{release}%{disttag}-%{_target_cpu} >/dev/null
     rm -rf /var/lib/dkms/*/*/%{version}-$devel_flavour-%{release}%{disttag} >/dev/null
@@ -1553,7 +1793,7 @@ install -d %{temp_root}
 
 # Build the configs for every arch we care about
 # that way, we can be sure all *.config files have the right additions
-for a in arm arm64 i386 x86_64 znver1 powerpc riscv; do
+for a in arm arm64 i386 x86_64 znver1 powerpc riscv loongarch64; do
 	for t in desktop server; do
 		CreateConfig $a $t
 		export ARCH=$a
@@ -1584,6 +1824,10 @@ for a in arm arm64 i386 x86_64 znver1 powerpc riscv; do
 					ARCH=x86
 					SARCH=x86
 					;;
+				loongarch64)
+					ARCH=loongarch
+					SARCH=loongarch
+					;;
 				x86_64|znver1)
 					[ "$a" != "x86_64" ] && continue
 					SARCH=x86
@@ -1631,42 +1875,39 @@ sed -ri "s|^(EXTRAVERSION =).*|\1 -%{release}|" Makefile
 %if %{with build_cpupower}
 # make sure version-gen.sh is executable.
 chmod +x tools/power/cpupower/utils/version-gen.sh
-%make_build -C tools/power/cpupower CPUFREQ_BENCH=false LDFLAGS="%{optflags}"
-%make_install -C tools/power/cpupower DESTDIR=%{temp_root} libdir=%{_libdir} mandir=%{_mandir} CPUFREQ_BENCH=false CC=%{__cc} LDFLAGS="%{optflags}"
+%make_build -C tools/power/cpupower CC=%{__cc} HOSTCC=%{__cc} LDFLAGS="%{optflags}" CPUFREQ_BENCH=false V=0 VERBOSE=0
+%make_install -C tools/power/cpupower CC=%{__cc} HOSTCC=%{__cc} LDFLAGS="%{optflags}" DESTDIR=%{temp_root} libdir=%{_libdir} mandir=%{_mandir} CPUFREQ_BENCH=false V=0 VERBOSE=0
 %endif
 
 %ifarch %{ix86} %{x86_64}
 %if %{with build_x86_energy_perf_policy}
-%make_build -C tools/power/x86/x86_energy_perf_policy CC=clang LDFLAGS="-Wl,--build-id=none"
+%make_build -C tools/power/x86/x86_energy_perf_policy CC=%{__cc} HOSTCC=%{__cc} LDFLAGS="-Wl,--build-id=none" V=0 VERBOSE=0
 mkdir -p %{temp_root}%{_bindir} %{temp_root}%{_mandir}/man8
-%make_install -C tools/power/x86/x86_energy_perf_policy DESTDIR="%{temp_root}"
+%make_install -C tools/power/x86/x86_energy_perf_policy DESTDIR="%{temp_root}" V=0 VERBOSE=0
 %endif
 
 %if %{with build_turbostat}
-%make_build -C tools/power/x86/turbostat CC=clang
+%make_build -C tools/power/x86/turbostat CC=%{__cc} HOSTCC=%{__cc} V=0 VERBOSE=0
 mkdir -p %{temp_root}%{_bindir} %{temp_root}%{_mandir}/man8
-%make_install -C tools/power/x86/turbostat DESTDIR="%{temp_root}"
+%make_install -C tools/power/x86/turbostat DESTDIR="%{temp_root}" V=0 VERBOSE=0
 %endif
 %endif
 
 %if %{with bpftool}
-# FIXME As of lld 12.0 and kernel 5.11, lld results in unresolved symbols, ld.bfd works
-%make_build -C tools/lib/bpf CC=clang LD=ld.bfd HOSTCC=clang HOSTLD=ld.bfd VMLINUX_BPF=%{temp_root}%{_bootdir}/vmlinuz-%{version}-desktop-%{release}%{disttag} libbpf.a libbpf.pc libbpf.so -j1
-%make_build -C tools/bpf/bpftool CC=clang LD=ld.bfd HOSTCC=clang HOSTLD=ld.bfd VMLINUX_BPF=%{temp_root}%{_bootdir}/vmlinuz-%{version}-desktop-%{release}%{disttag} bpftool -j1
-%make_install -C tools/lib/bpf install_headers DESTDIR=%{temp_root} prefix=%{_prefix} libdir=%{_libdir} CC=clang CXX=clang++ LD=ld.bfd HOSTLD=ld.bfd VMLINUX_BPF=%{temp_root}%{_bootdir}/vmlinuz-%{version}-desktop-%{release}%{disttag}
-%make_install -C tools/bpf/bpftool CC=clang CXX=clang++ LD=ld.bfd HOSTCC=clang HOSTLD=ld.bfd DESTDIR=%{temp_root} prefix=%{_prefix} bash_compdir=%{_sysconfdir}/bash_completion.d/ mandir=%{_mandir} VMLINUX_BPF=%{temp_root}%{_bootdir}/vmlinuz-%{version}-desktop-%{release}%{disttag}
+%make_build -C tools/bpf/bpftool CC=%{__cc} HOSTCC=%{__cc} ARCH=%{target_arch} LLVM=1 DESTDIR="%{temp_root}" V=0 VERBOSE=0
+%make_install -C tools/bpf/bpftool DESTDIR="%{temp_root}" prefix=%{_prefix} bash_compdir=%{_sysconfdir}/bash_completion.d/ mandir=%{_mandir} ARCH=%{target_arch} LLVM=1 install V=0 VERBOSE=0
 %endif
 
 %if %{with perf}
 [ -e %{_sysconfdir}/profile.d/90java.sh ] && . %{_sysconfdir}/profile.d/90java.sh
-%make_build -C tools/perf -s HAVE_CPLUS_DEMANGLE=1 CC=%{__cc} HOSTCC=%{__cc} LD=ld.bfd HOSTLD=ld.bfd WERROR=0 prefix=%{_prefix} all man
+%make_build -C tools/perf -s HAVE_CPLUS_DEMANGLE=1 NO_LIBTRACEEVENT=1 CC=%{__cc} HOSTCC=%{__cc} LD=ld.lld HOSTLD=ld.lld WERROR=0 prefix=%{_prefix} V=0 VERBOSE=0 all man
 # Not SMP safe
-make -C tools/perf -s HAVE_CPLUS_DEMANGLE=1 CC=%{__cc} HOSTCC=%{__cc} LD=ld.bfd HOSTLD=ld.bfd WERROR=0 prefix=%{_prefix} DESTDIR_SQ=%{temp_root} DESTDIR=%{temp_root} install install-man
+make -C tools/perf -s HAVE_CPLUS_DEMANGLE=1 NO_LIBTRACEEVENT=1 CC=%{__cc} HOSTCC=%{__cc} LD=ld.lld HOSTLD=ld.lld WERROR=0 prefix=%{_prefix} DESTDIR_SQ=%{temp_root} DESTDIR=%{temp_root} V=0 VERBOSE=0 install install-man
 %endif
 
 %if %{with hyperv}
-%make_build -C tools/hv -s CC=%{__cc} HOSTCC=%{__cc} prefix=%{_prefix} sbindir=%{_sbindir}
-%make_install -C tools/hv -s CC=%{__cc} HOSTCC=%{__cc} prefix=%{_prefix} sbindir=%{_sbindir} DESTDIR=%{temp_root}
+%make_build -C tools/hv -s CC=%{__cc} HOSTCC=%{__cc} prefix=%{_prefix} sbindir=%{_sbindir} V=0 VERBOSE=0
+%make_install -C tools/hv -s CC=%{__cc} HOSTCC=%{__cc} prefix=%{_prefix} sbindir=%{_sbindir} DESTDIR=%{temp_root} V=0 VERBOSE=0
 mkdir -p %{temp_root}%{_unitdir}
 install -c -m 644 %{S:7000} %{S:7002} %{S:7004} %{temp_root}%{_unitdir}/
 mkdir -p %{temp_root}%{_udevrulesdir}
@@ -1675,10 +1916,18 @@ install -c -m 644 %{S:7003} %{temp_root}%{_udevrulesdir}/70-hypervvss.rules
 install -c -m 644 %{S:7005} %{temp_root}%{_udevrulesdir}/70-hypervfcopy.rules
 %endif
 
+mkdir -p %{temp_root}%{_bindir}
+%if ! %{cross_compiling}
+cp tools/bpf/resolve_btfids/resolve_btfids %{temp_root}%{_bindir}/
+%endif
+
 # We don't make to repeat the depend code at the install phase
 %if %{with build_source}
 PrepareKernel "" %{release}custom
 %make_build -s mrproper
+%if ! %{cross_compiling}
+cp %{temp_root}%{_bindir}/resolve_btfids tools/bpf/resolve_btfids/
+%endif
 %endif
 
 ###
@@ -1686,47 +1935,38 @@ PrepareKernel "" %{release}custom
 ###
 
 %install
-# Directories definition needed for installing
-%define target_source %{buildroot}%{_kerneldir}
-%define target_boot %{buildroot}%{_bootdir}
-%define target_modules %{buildroot}%{_modulesdir}
-
 # We want to be able to test several times the install part
 rm -rf %{buildroot}
 cp -a %{temp_root} %{buildroot}
 
 # We used to have a copy of PrepareKernel here
 # Now, we make sure that the thing in the linux dir is what we want it to be
-for i in %{target_modules}/*; do
+for i in %{buildroot}%{_modulesdir}/*; do
     rm -f $i/build $i/source
 done
 
 # binmerge
 %if "%{_bindir}" == "%{_sbindir}"
-mv %{buildroot}%{_prefix}/sbin/* %{buildroot}%{_bindir}/
-rmdir %{buildroot}%{_prefix}/sbin
+[ -d %{buildroot}%{_prefix}/sbin ] && mv %{buildroot}%{_prefix}/sbin/* %{buildroot}%{_bindir}/
+[ -d %{buildroot}%{_prefix}/sbin ] && rmdir %{buildroot}%{_prefix}/sbin
 %endif
 
 # (tpg) let's compress all modules
-find %{target_modules} -name "*.ko" -type f | %kxargs zstd --format=zstd --ultra -22 -T0 --rm -f -q
+find %{buildroot}%{_modulesdir} -name "*.ko" -type f | %kxargs zstd --format=zstd --ultra -22 -T0 --rm -f -q
 
 # sniff, if we compressed all the modules, we change the stamp :(
 # we really need the depmod -ae here
-pushd %{target_modules}
-for i in *; do
-    %{_bindir}/depmod -ae -b %{buildroot} -F %{target_modules}/"$i"/System.map "$i"
+for i in $(ls -d %{buildroot}%{_modulesdir}/* ); do
+    KernelVer=$(basename "$i")
+# (tpg) this is needed workaround to not get wrong depmod output
+# unless somebody place vmlinuz into modulesdir and the copy it to bootdir on install
+    [ -L %{buildroot}%{_modulesdir}/$KernelVer/vmlinuz ] && rm -rf %{buildroot}%{_modulesdir}/$KernelVer/vmlinuz && cp -a %{buildroot}%{_bootdir}/vmlinuz-$KernelVer %{buildroot}%{_modulesdir}/$KernelVer/vmlinuz
+    %{_bindir}/depmod -ae -b %{buildroot} -F %{buildroot}%{_modulesdir}/$KernelVer/System.map $KernelVer
     echo $?
+# (tpg) see above workaround
+    [ -f %{buildroot}%{_modulesdir}/$KernelVer/vmlinuz ] && rm -rf %{buildroot}%{_modulesdir}/$KernelVer/vmlinuz && ln -sr %{_bootdir}/vmlinuz-$KernelVer %{buildroot}%{_modulesdir}/$KernelVer/vmlinuz
 done
 
-for i in *; do
-    pushd $i
-	printf '%s\n' "Creating modules.description for $i"
-	modules=$(find . -name "*.ko.[gxz]*[z|st]" -type f)
-	echo $modules | %kxargs %{_bindir}/modinfo | perl -lne 'print "$name\t$1" if $name && /^description:\s*(.*)/; $name = $1 if m!^filename:\s*(.*)\.k?o!; $name =~ s!.*/!!' > modules.description
-    popd
-done
-popd
-
 # need to set extraversion to match srpm again to avoid rebuild
 sed -ri "s|^(EXTRAVERSION =).*|\1 -%{release}|" Makefile
 
@@ -1735,48 +1975,59 @@ rm -f %{buildroot}%{_libdir}/*.{a,la}
 %find_lang cpupower
 chmod 0755 %{buildroot}%{_libdir}/libcpupower.so*
 mkdir -p %{buildroot}%{_unitdir} %{buildroot}%{_sysconfdir}/sysconfig
-install -m644 %{SOURCE30} %{buildroot}%{_unitdir}/cpupower.service
-install -m644 %{SOURCE31} %{buildroot}%{_sysconfdir}/sysconfig/cpupower
+install -m644 %{S:300} %{buildroot}%{_unitdir}/cpupower.service
+install -m644 %{S:301} %{buildroot}%{_sysconfdir}/sysconfig/cpupower
 %endif
 
 # Create directories infastructure
 %if %{with build_source}
-install -d %{target_source}
+install -d %{buildroot}%{_kerneldir}
 
 # Package what remains
-tar cf - . | tar xf - -C %{target_source}
-chmod -R a+rX %{target_source}
+tar cf - . | tar xf - -C %{buildroot}%{_kerneldir}
+chmod -R a+rX %{buildroot}%{_kerneldir}
 
-rm -f %{target_source}/*.lang
+rm -f %{buildroot}%{_kerneldir}/*.lang
 
 # File lists aren't needed
-rm -f %{target_source}/*_files.* %{target_source}/README.kernel-sources
+rm -f %{buildroot}%{_kerneldir}/*_files.* %{buildroot}%{_kerneldir}/README.kernel-sources
 
 # we remove all the source files that we don't ship
 # first architecture files
-for i in alpha arc avr32 blackfin c6x cris csky frv h8300 hexagon ia64 loongarch m32r m68k m68knommu metag microblaze \
+for i in alpha arc avr32 blackfin c6x cris csky frv h8300 hexagon ia64 m32r m68k m68knommu metag microblaze \
 	mips nds32 nios2 openrisc parisc s390 score sh sh64 sparc tile unicore32 v850 xtensa mn10300; do
-    rm -rf %{target_source}/arch/$i
-    rm -rf %{target_source}/scripts/dtc/include-prefixes/$i
-    rm -rf %{target_source}/tools/arch/$i
-    rm -rf %{target_source}/tools/testing/selftests/$i
+    rm -rf %{buildroot}%{_kerneldir}/arch/$i
+    rm -rf %{buildroot}%{_kerneldir}/scripts/dtc/include-prefixes/$i
+    rm -rf %{buildroot}%{_kerneldir}/tools/arch/$i
+    rm -rf %{buildroot}%{_kerneldir}/tools/testing/selftests/$i
+    sed -i -e "/source.*${i}/d" %{buildroot}%{_kerneldir}/crypto/Kconfig
 done
 
+%ifnarch %{armx}
+    rm -rf %{buildroot}%{_kerneldir}/include/kvm/arm*
+    rm -rf %{buildroot}%{_kerneldir}/scripts/dtc/include-prefixes/arm*
+%endif
+
 # other misc files
-rm -f %{target_source}/{.config.old,.config.cmd,.gitignore,.lst,.mailmap,.gitattributes,.get_maintainer.ignore}
-rm -f %{target_source}/{.missing-syscalls.d,arch/.gitignore,firmware/.gitignore,.gitattributes}
-rm -rf %{target_source}/.tmp_depmod/
-rm -rf %{buildroot}/usr/src/linux-*/uksm.txt
+rm -f %{buildroot}%{_kerneldir}/{.config.old,.config.cmd,.gitignore,.lst,.mailmap,.gitattributes,.get_maintainer.ignore}
+rm -f %{buildroot}%{_kerneldir}/{.missing-syscalls.d,arch/.gitignore,firmware/.gitignore,.gitattributes}
+rm -rf %{buildroot}%{_kerneldir}/.tmp_depmod/
 
 # more cleaning
-rm -f %{target_source}/arch/x86_64/boot/bzImage
-cd %{target_source}
+rm -f %{buildroot}%{_kerneldir}/arch/x86_64/boot/bzImage
+cd %{buildroot}%{_kerneldir}
 # lots of gitignore files
 find -iname ".gitignore" -delete
 # clean tools tree
-%make_build -C tools clean -j1 V=0 VERBOSE=0
+# (mkdir below is just so "make clean" can remove it again without erroring out)
+mkdir -p tools/counter/include/linux
+%make_build -C tools clean -j1 V=0 VERBOSE=0 || :
 %make_build -C tools/build clean -j1 V=0 VERBOSE=0
 %make_build -C tools/build/feature clean -j1 V=0 VERBOSE=0
+# dont ship generated vdso.so*
+%ifarch %{aarch64}
+rm -f arch/arm64/kernel/vdso/vdso.so*
+%endif
 rm -f .cache.mk
 
 # Drop script binaries that can be rebuilt
@@ -1787,21 +2038,28 @@ find tools scripts -executable |while read r; do
 done
 cd -
 
-#endif %{with build_source}
+# build_source
 %endif
 
 %if %{with build_source}
 %files -n %{name}-source
+%if ! %{cross_compiling}
+%{_bindir}/resolve_btfids
+%endif
 %dir %{_kerneldir}
 %dir %{_kerneldir}/arch
 %dir %{_kerneldir}/include
 %dir %{_kerneldir}/certs
 %{_kerneldir}/.clang-format
+%optional %{_kerneldir}/.clippy.toml
 %{_kerneldir}/.cocciconfig
+%{_kerneldir}/.editorconfig
+%{_kerneldir}/.pylintrc
 %{_kerneldir}/Documentation
 %{_kerneldir}/arch/Kconfig
 %{_kerneldir}/arch/arm
 %{_kerneldir}/arch/arm64
+%{_kerneldir}/arch/loongarch
 %{_kerneldir}/arch/powerpc
 %{_kerneldir}/arch/riscv
 %{_kerneldir}/arch/um
@@ -1811,12 +2069,15 @@ cd -
 %{_kerneldir}/drivers
 %{_kerneldir}/fs
 %{_kerneldir}/certs/*
+%{_kerneldir}/include/Kbuild
 %{_kerneldir}/include/acpi
 %{_kerneldir}/include/asm-generic
 %{_kerneldir}/include/clocksource
 %{_kerneldir}/include/crypto
+%{_kerneldir}/include/cxl
 %{_kerneldir}/include/drm
 %{_kerneldir}/include/dt-bindings
+%optional %{_kerneldir}/include/hyperv
 %{_kerneldir}/include/keys
 %{_kerneldir}/include/kunit
 %{_kerneldir}/include/kvm
@@ -1874,24 +2135,12 @@ cd -
 %if %{with perf}
 %files -n perf
 %{_bindir}/perf
-%ifarch %{x86_64}
 %optional %{_bindir}/perf-read-vdso32
-%endif
 %{_bindir}/trace
-%ifarch %{x86_64}
-%dir %{_libdir}/traceevent
-%dir %{_libdir}/traceevent/plugins
-%{_libdir}/traceevent/plugins/plugin_*
-%else
-%dir %{_prefix}/lib/traceevent
-%dir %{_prefix}/lib/traceevent/plugins
-%{_prefix}/lib/traceevent/plugins/plugin_*
-%endif
 %dir %{_prefix}/libexec/perf-core
 %{_prefix}/libexec/perf-core/*
 %doc %{_mandir}/man[1-8]/perf*
 %{_sysconfdir}/bash_completion.d/perf
-%{_prefix}/lib/perf
 %ifarch %{x86_64}
 %{_libdir}/libperf-jvmti.so
 %else
@@ -1904,12 +2153,14 @@ cd -
 %if %{with build_cpupower}
 %files -n cpupower -f cpupower.lang
 %{_bindir}/cpupower
-%{_libdir}/libcpupower.so.0
-%{_libdir}/libcpupower.so.0.0.1
+%{_libexecdir}/cpupower
+%{_libdir}/libcpupower.so.1
+%{_libdir}/libcpupower.so.1.0.1
 %{_unitdir}/cpupower.service
 %doc %{_mandir}/man[1-8]/cpupower*
 %{_datadir}/bash-completion/completions/cpupower
 %config(noreplace) %{_sysconfdir}/sysconfig/cpupower
+%config(noreplace) %{_sysconfdir}/cpupower-service.conf
 
 %files -n cpupower-devel
 %{_libdir}/libcpupower.so
@@ -1934,13 +2185,4 @@ cd -
 %files -n bpftool
 %{_bindir}/bpftool
 %{_sysconfdir}/bash_completion.d/bpftool
-
-%files -n %{libbpf}
-%{_libdir}/libbpf.so.%{bpf_major}*
-
-%files -n %{libbpfdevel}
-%{_libdir}/libbpf.so
-%{_libdir}/pkgconfig/*.pc
-%dir %{_includedir}/bpf
-%{_includedir}/bpf/*.h
 %endif
diff --git a/linux-2000-v4l-wip-rkvdec-vp9.patch b/linux-2000-v4l-wip-rkvdec-vp9.patch
deleted file mode 100644
index b0bc10c..0000000
--- a/linux-2000-v4l-wip-rkvdec-vp9.patch
+++ /dev/null
@@ -1,3674 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Boris Brezillon <boris.brezillon@collabora.com>
-Date: Mon, 2 Nov 2020 21:05:50 +0200
-Subject: [PATCH] media: uapi: Add VP9 stateless decoder controls
-
-Add the VP9 stateless decoder controls plus the documentation that goes
-with it.
-
-Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Adrian Ratiu <adrian.ratiu@collabora.com>
----
- .../userspace-api/media/v4l/biblio.rst        |   10 +
- .../media/v4l/ext-ctrls-codec.rst             | 1100 +++++++++++++++++
- drivers/media/v4l2-core/v4l2-ctrls-core.c     |  225 ++++
- drivers/media/v4l2-core/v4l2-ctrls-defs.c     |   14 +
- drivers/media/v4l2-core/v4l2-ioctl.c          |    1 +
- include/media/v4l2-ctrls.h                    |    5 +
- include/media/vp9-ctrls.h                     |  486 ++++++++
- 7 files changed, 1841 insertions(+)
- create mode 100644 include/media/vp9-ctrls.h
-
-diff --git a/Documentation/userspace-api/media/v4l/biblio.rst b/Documentation/userspace-api/media/v4l/biblio.rst
-index 7b8e6738ff9e..9cd18c153d19 100644
---- a/Documentation/userspace-api/media/v4l/biblio.rst
-+++ b/Documentation/userspace-api/media/v4l/biblio.rst
-@@ -417,3 +417,13 @@ VP8
- :title:     RFC 6386: "VP8 Data Format and Decoding Guide"
- 
- :author:    J. Bankoski et al.
-+
-+.. _vp9:
-+
-+VP9
-+===
-+
-+
-+:title:     VP9 Bitstream & Decoding Process Specification
-+
-+:author:    Adrian Grange (Google), Peter de Rivaz (Argon Design), Jonathan Hunt (Argon Design)
-diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
-index 8c6e2a11ed95..5dd4afc5f1fe 100644
---- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
-+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
-@@ -3106,6 +3106,556 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
-       - ``padding[2]``
-       - Applications and drivers must set this to zero.
- 
-+.. _v4l2-mpeg-vp9:
-+
-+``V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0..3) (struct)``
-+    Stores VP9 probabilities attached to a specific frame context. The VP9
-+    specification allows using a maximum of 4 contexts. Each frame being
-+    decoded refers to one of those context. See section '7.1.2 Refresh
-+    probs semantics' section of :ref:`vp9` for more details about these
-+    contexts.
-+
-+    This control is bi-directional:
-+
-+    * all 4 contexts must be initialized by userspace just after the
-+      stream is started and before the first decoding request is submitted.
-+    * the referenced context might be read by the kernel when a decoding
-+      request is submitted, and will be updated after the decoder is done
-+      decoding the frame if the `V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX` flag
-+      is set.
-+    * contexts will be read back by user space before each decoding request
-+      to retrieve the updated probabilities.
-+    * userspace will re-initialize the context to their default values when
-+      a reset context is required.
-+
-+    .. note::
-+
-+       This compound control is not yet part of the public kernel API and
-+       it is expected to change.
-+
-+.. c:type:: v4l2_ctrl_vp9_frame_ctx
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{5.8cm}|p{4.8cm}|p{6.6cm}|
-+
-+.. flat-table:: struct v4l2_ctrl_vp9_frame_ctx
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 1 2
-+
-+    * - struct :c:type:`v4l2_vp9_probabilities`
-+      - ``probs``
-+      - Structure with VP9 probabilities attached to the context.
-+
-+.. c:type:: v4l2_vp9_probabilities
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: struct v4l2_vp9_probabilities
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 1 2
-+
-+    * - __u8
-+      - ``tx8[2][1]``
-+      - TX 8x8 probabilities.
-+    * - __u8
-+      - ``tx16[2][2]``
-+      - TX 16x16 probabilities.
-+    * - __u8
-+      - ``tx32[2][3]``
-+      - TX 32x32 probabilities.
-+    * - __u8
-+      - ``coef[4][2][2][6][6][3]``
-+      - Coefficient probabilities.
-+    * - __u8
-+      - ``skip[3]``
-+      - Skip probabilities.
-+    * - __u8
-+      - ``inter_mode[7][3]``
-+      - Inter prediction mode probabilities.
-+    * - __u8
-+      - ``interp_filter[4][2]``
-+      - Interpolation filter probabilities.
-+    * - __u8
-+      - ``is_inter[4]``
-+      - Is inter-block probabilities.
-+    * - __u8
-+      - ``comp_mode[5]``
-+      - Compound prediction mode probabilities.
-+    * - __u8
-+      - ``single_ref[5][2]``
-+      - Single reference probabilities.
-+    * - __u8
-+      - ``comp_mode[5]``
-+      - Compound reference probabilities.
-+    * - __u8
-+      - ``y_mode[4][9]``
-+      - Y prediction mode probabilities.
-+    * - __u8
-+      - ``uv_mode[10][9]``
-+      - UV prediction mode probabilities.
-+    * - __u8
-+      - ``partition[16][3]``
-+      - Partition probabilities.
-+    * - __u8
-+      - ``mv.joint[3]``
-+      - Motion vector joint probabilities.
-+    * - __u8
-+      - ``mv.sign[2]``
-+      - Motion vector sign probabilities.
-+    * - __u8
-+      - ``mv.class[2][10]``
-+      - Motion vector class probabilities.
-+    * - __u8
-+      - ``mv.class0_bit[2]``
-+      - Motion vector class0 bit probabilities.
-+    * - __u8
-+      - ``mv.bits[2][10]``
-+      - Motion vector bits probabilities.
-+    * - __u8
-+      - ``mv.class0_fr[2][2][3]``
-+      - Motion vector class0 fractional bit probabilities.
-+    * - __u8
-+      - ``mv.fr[2][3]``
-+      - Motion vector fractional bit probabilities.
-+    * - __u8
-+      - ``mv.class0_hp[2]``
-+      - Motion vector class0 high precision fractional bit probabilities.
-+    * - __u8
-+      - ``mv.hp[2]``
-+      - Motion vector high precision fractional bit probabilities.
-+
-+``V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS (struct)``
-+    Specifies the frame parameters for the associated VP9 frame decode request.
-+    This includes the necessary parameters for configuring a stateless hardware
-+    decoding pipeline for VP9. The bitstream parameters are defined according
-+    to :ref:`vp9`.
-+
-+    .. note::
-+
-+       This compound control is not yet part of the public kernel API and
-+       it is expected to change.
-+
-+.. c:type:: v4l2_ctrl_vp9_frame_decode_params
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: struct v4l2_ctrl_vp9_frame_decode_params
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 1 2
-+
-+    * - __u32
-+      - ``flags``
-+      - Combination of V4L2_VP9_FRAME_FLAG_* flags. See
-+        :c:type:`v4l2_vp9_frame_flags`.
-+    * - __u16
-+      - ``compressed_header_size``
-+      - Compressed header size in bytes.
-+    * - __u16
-+      - ``uncompressed_header_size``
-+      - Uncompressed header size in bytes.
-+    * - __u8
-+      - ``profile``
-+      - VP9 profile. Can be 0, 1, 2 or 3.
-+    * - __u8
-+      - ``reset_frame_context``
-+      - Frame context that should be used/updated when decoding the frame.
-+    * - __u8
-+      - ``bit_depth``
-+      - Component depth in bits. Must be 8 for profile 0 and 1. Must 10 or 12
-+        for profile 2 and 3.
-+    * - __u8
-+      - ``interpolation_filter``
-+      - Specifies the filter selection used for performing inter prediction. See
-+        :c:type:`v4l2_vp9_interpolation_filter`.
-+    * - __u8
-+      - ``tile_cols_log2``
-+      - Specifies the base 2 logarithm of the width of each tile (where the
-+        width is measured in units of 8x8 blocks). Shall be less than or equal
-+        to 6.
-+    * - __u8
-+      - ``tile_rows_log2``
-+      - Specifies the base 2 logarithm of the height of each tile (where the
-+        height is measured in units of 8x8 blocks)
-+    * - __u8
-+      - ``tx_mode``
-+      - Specifies the TX mode. See :c:type:`v4l2_vp9_tx_mode`.
-+    * - __u8
-+      - ``reference_mode``
-+      - Specifies the type of inter prediction to be used. See
-+        :c:type:`v4l2_vp9_reference_mode`.
-+    * - __u8
-+      - ``padding[7]``
-+      - Needed to make this struct 64 bit aligned. Shall be filled with zeroes.
-+    * - __u16
-+      - ``frame_width_minus_1``
-+      - Add 1 to get the frame width expressed in pixels.
-+    * - __u16
-+      - ``frame_height_minus_1``
-+      - Add 1 to get the frame height expressed in pixels.
-+    * - __u16
-+      - ``frame_width_minus_1``
-+      - Add 1 to get the expected render width expressed in pixels. This is
-+        not used during the decoding process but might be used by HW scalers to
-+        prepare a frame that's ready for scanout.
-+    * - __u16
-+      - frame_height_minus_1
-+      - Add 1 to get the expected render height expressed in pixels. This is
-+        not used during the decoding process but might be used by HW scalers to
-+        prepare a frame that's ready for scanout.
-+    * - __u64
-+      - ``refs[3]``
-+      - Array of reference frame timestamps.
-+    * - struct :c:type:`v4l2_vp9_loop_filter`
-+      - ``lf``
-+      - Loop filter parameters. See struct :c:type:`v4l2_vp9_loop_filter`.
-+    * - struct :c:type:`v4l2_vp9_quantization`
-+      - ``quant``
-+      - Quantization parameters. See :c:type:`v4l2_vp9_quantization`.
-+    * - struct :c:type:`v4l2_vp9_segmentation`
-+      - ``seg``
-+      - Segmentation parameters. See :c:type:`v4l2_vp9_segmentation`.
-+    * - struct :c:type:`v4l2_vp9_probabilities`
-+      - ``probs``
-+      - Probabilities. See :c:type:`v4l2_vp9_probabilities`.
-+
-+.. c:type:: v4l2_vp9_frame_flags
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_frame_flags
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_FRAME_FLAG_KEY_FRAME``
-+      - The frame is a key frame.
-+    * - ``V4L2_VP9_FRAME_FLAG_SHOW_FRAME``
-+      - The frame should be displayed.
-+    * - ``V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT``
-+      - The decoding should be error resilient.
-+    * - ``V4L2_VP9_FRAME_FLAG_INTRA_ONLY``
-+      - The frame does not reference other frames.
-+    * - ``V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV``
-+      - the frame might can high precision motion vectors.
-+    * - ``V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX``
-+      - Frame context should be updated after decoding.
-+    * - ``V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE``
-+      - Parallel decoding is used.
-+    * - ``V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING``
-+      - Vertical subsampling is enabled.
-+    * - ``V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING``
-+      - Horizontal subsampling is enabled.
-+    * - ``V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING``
-+      - The full UV range is used.
-+
-+.. c:type:: v4l2_vp9_ref_id
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_ref_id
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_REF_ID_LAST``
-+      - Last reference frame.
-+    * - ``V4L2_REF_ID_GOLDEN``
-+      - Golden reference frame.
-+    * - ``V4L2_REF_ID_ALTREF``
-+      - Alternative reference frame.
-+    * - ``V4L2_REF_ID_CNT``
-+      - Number of reference frames.
-+
-+.. c:type:: v4l2_vp9_tx_mode
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_tx_mode
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_TX_MODE_ONLY_4X4``
-+      - Transform size is 4x4.
-+    * - ``V4L2_VP9_TX_MODE_ALLOW_8X8``
-+      - Transform size can be up to 8x8.
-+    * - ``V4L2_VP9_TX_MODE_ALLOW_16X16``
-+      - Transform size can be up to 16x16.
-+    * - ``V4L2_VP9_TX_MODE_ALLOW_32X32``
-+      - transform size can be up to 32x32.
-+    * - ``V4L2_VP9_TX_MODE_SELECT``
-+      - Bitstream contains transform size for each block.
-+
-+.. c:type:: v4l2_vp9_reference_mode
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_reference_mode
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_REF_MODE_SINGLE``
-+      - Indicates that all the inter blocks use only a single reference frame
-+        to generate motion compensated prediction.
-+    * - ``V4L2_VP9_REF_MODE_COMPOUND``
-+      - Requires all the inter blocks to use compound mode. Single reference
-+        frame prediction is not allowed.
-+    * - ``V4L2_VP9_REF_MODE_SELECT``
-+      - Allows each individual inter block to select between single and
-+        compound prediction modes.
-+
-+.. c:type:: v4l2_vp9_interpolation_filter
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_interpolation_filter
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_INTERP_FILTER_8TAP``
-+      - Height tap filter.
-+    * - ``V4L2_VP9_INTERP_FILTER_8TAP_SMOOTH``
-+      - Height tap smooth filter.
-+    * - ``V4L2_VP9_INTERP_FILTER_8TAP_SHARP``
-+      - Height tap sharp filter.
-+    * - ``V4L2_VP9_INTERP_FILTER_BILINEAR``
-+      - Bilinear filter.
-+    * - ``V4L2_VP9_INTERP_FILTER_SWITCHABLE``
-+      - Filter selection is signaled at the block level.
-+
-+.. c:type:: v4l2_vp9_reset_frame_context
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_reset_frame_context
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_RESET_FRAME_CTX_NONE``
-+      - Do not reset any frame context.
-+    * - ``V4L2_VP9_RESET_FRAME_CTX_SPEC``
-+      - Reset the frame context pointed by
-+        :c:type:`v4l2_ctrl_vp9_frame_decode_params`.frame_context_idx.
-+    * - ``V4L2_VP9_RESET_FRAME_CTX_ALL``
-+      - Reset all frame contexts.
-+
-+.. c:type:: v4l2_vp9_intra_prediction_mode
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_intra_prediction_mode
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_INTRA_PRED_DC``
-+      - DC intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_V``
-+      - Vertical intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_H``
-+      - Horizontal intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_D45``
-+      - D45 intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_D135``
-+      - D135 intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_D117``
-+      - D117 intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_D153``
-+      - D153 intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_D207``
-+      - D207 intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_D63``
-+      - D63 intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_TM``
-+      - True motion intra prediction.
-+
-+.. c:type:: v4l2_vp9_segmentation
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: struct v4l2_vp9_segmentation
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 1 2
-+
-+    * - __u8
-+      - ``flags``
-+      - Combination of V4L2_VP9_SEGMENTATION_FLAG_* flags. See
-+        :c:type:`v4l2_vp9_segmentation_flags`.
-+    * - __u8
-+      - ``tree_probs[7]``
-+      - Specifies the probability values to be used when decoding a Segment-ID.
-+        See '5.15. Segmentation map' section of :ref:`vp9` for more details.
-+    * - __u8
-+      - ``pred_prob[3]``
-+      - Specifies the probability values to be used when decoding a
-+        Predicted-Segment-ID. See '6.4.14. Get segment id syntax'
-+        section of :ref:`vp9` for more details.
-+    * - __u8
-+      - ``padding[5]``
-+      - Used to align this struct on 64 bit. Shall be filled with zeroes.
-+    * - __u8
-+      - ``feature_enabled[8]``
-+      - Bitmask defining which features are enabled in each segment.
-+    * - __u8
-+      - ``feature_data[8][4]``
-+      - Data attached to each feature. Data entry is only valid if the feature
-+        is enabled.
-+
-+.. c:type:: v4l2_vp9_segment_feature
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_segment_feature
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_SEGMENT_FEATURE_QP_DELTA``
-+      - QP delta segment feature.
-+    * - ``V4L2_VP9_SEGMENT_FEATURE_LF``
-+      - Loop filter segment feature.
-+    * - ``V4L2_VP9_SEGMENT_FEATURE_REF_FRAME``
-+      - Reference frame segment feature.
-+    * - ``V4L2_VP9_SEGMENT_FEATURE_SKIP``
-+      - Skip segment feature.
-+    * - ``V4L2_VP9_SEGMENT_FEATURE_CNT``
-+      - Number of segment features.
-+
-+.. c:type:: v4l2_vp9_segmentation_flags
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_segmentation_flags
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_SEGMENTATION_FLAG_ENABLED``
-+      - Indicates that this frame makes use of the segmentation tool.
-+    * - ``V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP``
-+      - Indicates that the segmentation map should be updated during the
-+        decoding of this frame.
-+    * - ``V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE``
-+      - Indicates that the updates to the segmentation map are coded
-+        relative to the existing segmentation map.
-+    * - ``V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA``
-+      - Indicates that new parameters are about to be specified for each
-+        segment.
-+    * - ``V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE``
-+      - Indicates that the segmentation parameters represent the actual values
-+        to be used.
-+
-+.. c:type:: v4l2_vp9_quantization
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: struct v4l2_vp9_quantization
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 1 2
-+
-+    * - __u8
-+      - ``base_q_idx``
-+      - Indicates the base frame qindex.
-+    * - __s8
-+      - ``delta_q_y_dc``
-+      - Indicates the Y DC quantizer relative to base_q_idx.
-+    * - __s8
-+      - ``delta_q_uv_dc``
-+      - Indicates the UV DC quantizer relative to base_q_idx.
-+    * - __s8
-+      - ``delta_q_uv_ac``
-+      - Indicates the UV AC quantizer relative to base_q_idx.
-+    * - __u8
-+      - ``padding[4]``
-+      - Padding bytes used to align this struct on 64 bit. Must be set to 0.
-+
-+.. c:type:: v4l2_vp9_loop_filter
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: struct v4l2_vp9_loop_filter
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 1 2
-+
-+    * - __u8
-+      - ``flags``
-+      - Combination of V4L2_VP9_LOOP_FILTER_FLAG_* flags.
-+        See :c:type:`v4l2_vp9_loop_filter_flags`.
-+    * - __u8
-+      - ``level``
-+      - Indicates the loop filter strength.
-+    * - __u8
-+      - ``sharpness``
-+      - Indicates the sharpness level.
-+    * - __s8
-+      - ``ref_deltas[4]``
-+      - Contains the adjustment needed for the filter level based on the chosen
-+        reference frame.
-+    * - __s8
-+      - ``mode_deltas[2]``
-+      - Contains the adjustment needed for the filter level based on the chosen
-+        mode
-+    * - __u8
-+      - ``level_lookup[8][4][2]``
-+      - Level lookup table.
-+
-+
-+.. c:type:: v4l2_vp9_loop_filter_flags
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_loop_filter_flags
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED``
-+      - When set, the filter level depends on the mode and reference frame used
-+        to predict a block.
-+    * - ``V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE``
-+      - When set, the bitstream contains additional syntax elements that
-+        specify which mode and reference frame deltas are to be updated.
-+
- .. raw:: latex
- 
-     \normalsize
-@@ -3157,6 +3707,556 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
-       - ``padding[6]``
-       - Applications and drivers must set this to zero.
- 
-+.. _v4l2-mpeg-vp9:
-+
-+``V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0..3) (struct)``
-+    Stores VP9 probabilities attached to a specific frame context. The VP9
-+    specification allows using a maximum of 4 contexts. Each frame being
-+    decoded refers to one of those context. See section '7.1.2 Refresh
-+    probs semantics' section of :ref:`vp9` for more details about these
-+    contexts.
-+
-+    This control is bi-directional:
-+
-+    * all 4 contexts must be initialized by userspace just after the
-+      stream is started and before the first decoding request is submitted.
-+    * the referenced context might be read by the kernel when a decoding
-+      request is submitted, and will be updated after the decoder is done
-+      decoding the frame if the `V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX` flag
-+      is set.
-+    * contexts will be read back by user space before each decoding request
-+      to retrieve the updated probabilities.
-+    * userspace will re-initialize the context to their default values when
-+      a reset context is required.
-+
-+    .. note::
-+
-+       This compound control is not yet part of the public kernel API and
-+       it is expected to change.
-+
-+.. c:type:: v4l2_ctrl_vp9_frame_ctx
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{5.8cm}|p{4.8cm}|p{6.6cm}|
-+
-+.. flat-table:: struct v4l2_ctrl_vp9_frame_ctx
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 1 2
-+
-+    * - struct :c:type:`v4l2_vp9_probabilities`
-+      - ``probs``
-+      - Structure with VP9 probabilities attached to the context.
-+
-+.. c:type:: v4l2_vp9_probabilities
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: struct v4l2_vp9_probabilities
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 1 2
-+
-+    * - __u8
-+      - ``tx8[2][1]``
-+      - TX 8x8 probabilities.
-+    * - __u8
-+      - ``tx16[2][2]``
-+      - TX 16x16 probabilities.
-+    * - __u8
-+      - ``tx32[2][3]``
-+      - TX 32x32 probabilities.
-+    * - __u8
-+      - ``coef[4][2][2][6][6][3]``
-+      - Coefficient probabilities.
-+    * - __u8
-+      - ``skip[3]``
-+      - Skip probabilities.
-+    * - __u8
-+      - ``inter_mode[7][3]``
-+      - Inter prediction mode probabilities.
-+    * - __u8
-+      - ``interp_filter[4][2]``
-+      - Interpolation filter probabilities.
-+    * - __u8
-+      - ``is_inter[4]``
-+      - Is inter-block probabilities.
-+    * - __u8
-+      - ``comp_mode[5]``
-+      - Compound prediction mode probabilities.
-+    * - __u8
-+      - ``single_ref[5][2]``
-+      - Single reference probabilities.
-+    * - __u8
-+      - ``comp_mode[5]``
-+      - Compound reference probabilities.
-+    * - __u8
-+      - ``y_mode[4][9]``
-+      - Y prediction mode probabilities.
-+    * - __u8
-+      - ``uv_mode[10][9]``
-+      - UV prediction mode probabilities.
-+    * - __u8
-+      - ``partition[16][3]``
-+      - Partition probabilities.
-+    * - __u8
-+      - ``mv.joint[3]``
-+      - Motion vector joint probabilities.
-+    * - __u8
-+      - ``mv.sign[2]``
-+      - Motion vector sign probabilities.
-+    * - __u8
-+      - ``mv.class[2][10]``
-+      - Motion vector class probabilities.
-+    * - __u8
-+      - ``mv.class0_bit[2]``
-+      - Motion vector class0 bit probabilities.
-+    * - __u8
-+      - ``mv.bits[2][10]``
-+      - Motion vector bits probabilities.
-+    * - __u8
-+      - ``mv.class0_fr[2][2][3]``
-+      - Motion vector class0 fractional bit probabilities.
-+    * - __u8
-+      - ``mv.fr[2][3]``
-+      - Motion vector fractional bit probabilities.
-+    * - __u8
-+      - ``mv.class0_hp[2]``
-+      - Motion vector class0 high precision fractional bit probabilities.
-+    * - __u8
-+      - ``mv.hp[2]``
-+      - Motion vector high precision fractional bit probabilities.
-+
-+``V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS (struct)``
-+    Specifies the frame parameters for the associated VP9 frame decode request.
-+    This includes the necessary parameters for configuring a stateless hardware
-+    decoding pipeline for VP9. The bitstream parameters are defined according
-+    to :ref:`vp9`.
-+
-+    .. note::
-+
-+       This compound control is not yet part of the public kernel API and
-+       it is expected to change.
-+
-+.. c:type:: v4l2_ctrl_vp9_frame_decode_params
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: struct v4l2_ctrl_vp9_frame_decode_params
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 1 2
-+
-+    * - __u32
-+      - ``flags``
-+      - Combination of V4L2_VP9_FRAME_FLAG_* flags. See
-+        :c:type:`v4l2_vp9_frame_flags`.
-+    * - __u16
-+      - ``compressed_header_size``
-+      - Compressed header size in bytes.
-+    * - __u16
-+      - ``uncompressed_header_size``
-+      - Uncompressed header size in bytes.
-+    * - __u8
-+      - ``profile``
-+      - VP9 profile. Can be 0, 1, 2 or 3.
-+    * - __u8
-+      - ``reset_frame_context``
-+      - Frame context that should be used/updated when decoding the frame.
-+    * - __u8
-+      - ``bit_depth``
-+      - Component depth in bits. Must be 8 for profile 0 and 1. Must 10 or 12
-+        for profile 2 and 3.
-+    * - __u8
-+      - ``interpolation_filter``
-+      - Specifies the filter selection used for performing inter prediction. See
-+        :c:type:`v4l2_vp9_interpolation_filter`.
-+    * - __u8
-+      - ``tile_cols_log2``
-+      - Specifies the base 2 logarithm of the width of each tile (where the
-+        width is measured in units of 8x8 blocks). Shall be less than or equal
-+        to 6.
-+    * - __u8
-+      - ``tile_rows_log2``
-+      - Specifies the base 2 logarithm of the height of each tile (where the
-+        height is measured in units of 8x8 blocks)
-+    * - __u8
-+      - ``tx_mode``
-+      - Specifies the TX mode. See :c:type:`v4l2_vp9_tx_mode`.
-+    * - __u8
-+      - ``reference_mode``
-+      - Specifies the type of inter prediction to be used. See
-+        :c:type:`v4l2_vp9_reference_mode`.
-+    * - __u8
-+      - ``padding[7]``
-+      - Needed to make this struct 64 bit aligned. Shall be filled with zeroes.
-+    * - __u16
-+      - ``frame_width_minus_1``
-+      - Add 1 to get the frame width expressed in pixels.
-+    * - __u16
-+      - ``frame_height_minus_1``
-+      - Add 1 to get the frame height expressed in pixels.
-+    * - __u16
-+      - ``frame_width_minus_1``
-+      - Add 1 to get the expected render width expressed in pixels. This is
-+        not used during the decoding process but might be used by HW scalers to
-+        prepare a frame that's ready for scanout.
-+    * - __u16
-+      - frame_height_minus_1
-+      - Add 1 to get the expected render height expressed in pixels. This is
-+        not used during the decoding process but might be used by HW scalers to
-+        prepare a frame that's ready for scanout.
-+    * - __u64
-+      - ``refs[3]``
-+      - Array of reference frame timestamps.
-+    * - struct :c:type:`v4l2_vp9_loop_filter`
-+      - ``lf``
-+      - Loop filter parameters. See struct :c:type:`v4l2_vp9_loop_filter`.
-+    * - struct :c:type:`v4l2_vp9_quantization`
-+      - ``quant``
-+      - Quantization parameters. See :c:type:`v4l2_vp9_quantization`.
-+    * - struct :c:type:`v4l2_vp9_segmentation`
-+      - ``seg``
-+      - Segmentation parameters. See :c:type:`v4l2_vp9_segmentation`.
-+    * - struct :c:type:`v4l2_vp9_probabilities`
-+      - ``probs``
-+      - Probabilities. See :c:type:`v4l2_vp9_probabilities`.
-+
-+.. c:type:: v4l2_vp9_frame_flags
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_frame_flags
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_FRAME_FLAG_KEY_FRAME``
-+      - The frame is a key frame.
-+    * - ``V4L2_VP9_FRAME_FLAG_SHOW_FRAME``
-+      - The frame should be displayed.
-+    * - ``V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT``
-+      - The decoding should be error resilient.
-+    * - ``V4L2_VP9_FRAME_FLAG_INTRA_ONLY``
-+      - The frame does not reference other frames.
-+    * - ``V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV``
-+      - the frame might can high precision motion vectors.
-+    * - ``V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX``
-+      - Frame context should be updated after decoding.
-+    * - ``V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE``
-+      - Parallel decoding is used.
-+    * - ``V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING``
-+      - Vertical subsampling is enabled.
-+    * - ``V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING``
-+      - Horizontal subsampling is enabled.
-+    * - ``V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING``
-+      - The full UV range is used.
-+
-+.. c:type:: v4l2_vp9_ref_id
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_ref_id
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_REF_ID_LAST``
-+      - Last reference frame.
-+    * - ``V4L2_REF_ID_GOLDEN``
-+      - Golden reference frame.
-+    * - ``V4L2_REF_ID_ALTREF``
-+      - Alternative reference frame.
-+    * - ``V4L2_REF_ID_CNT``
-+      - Number of reference frames.
-+
-+.. c:type:: v4l2_vp9_tx_mode
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_tx_mode
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_TX_MODE_ONLY_4X4``
-+      - Transform size is 4x4.
-+    * - ``V4L2_VP9_TX_MODE_ALLOW_8X8``
-+      - Transform size can be up to 8x8.
-+    * - ``V4L2_VP9_TX_MODE_ALLOW_16X16``
-+      - Transform size can be up to 16x16.
-+    * - ``V4L2_VP9_TX_MODE_ALLOW_32X32``
-+      - transform size can be up to 32x32.
-+    * - ``V4L2_VP9_TX_MODE_SELECT``
-+      - Bitstream contains transform size for each block.
-+
-+.. c:type:: v4l2_vp9_reference_mode
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_reference_mode
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_REF_MODE_SINGLE``
-+      - Indicates that all the inter blocks use only a single reference frame
-+        to generate motion compensated prediction.
-+    * - ``V4L2_VP9_REF_MODE_COMPOUND``
-+      - Requires all the inter blocks to use compound mode. Single reference
-+        frame prediction is not allowed.
-+    * - ``V4L2_VP9_REF_MODE_SELECT``
-+      - Allows each individual inter block to select between single and
-+        compound prediction modes.
-+
-+.. c:type:: v4l2_vp9_interpolation_filter
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_interpolation_filter
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_INTERP_FILTER_8TAP``
-+      - Height tap filter.
-+    * - ``V4L2_VP9_INTERP_FILTER_8TAP_SMOOTH``
-+      - Height tap smooth filter.
-+    * - ``V4L2_VP9_INTERP_FILTER_8TAP_SHARP``
-+      - Height tap sharp filter.
-+    * - ``V4L2_VP9_INTERP_FILTER_BILINEAR``
-+      - Bilinear filter.
-+    * - ``V4L2_VP9_INTERP_FILTER_SWITCHABLE``
-+      - Filter selection is signaled at the block level.
-+
-+.. c:type:: v4l2_vp9_reset_frame_context
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_reset_frame_context
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_RESET_FRAME_CTX_NONE``
-+      - Do not reset any frame context.
-+    * - ``V4L2_VP9_RESET_FRAME_CTX_SPEC``
-+      - Reset the frame context pointed by
-+        :c:type:`v4l2_ctrl_vp9_frame_decode_params`.frame_context_idx.
-+    * - ``V4L2_VP9_RESET_FRAME_CTX_ALL``
-+      - Reset all frame contexts.
-+
-+.. c:type:: v4l2_vp9_intra_prediction_mode
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_intra_prediction_mode
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_INTRA_PRED_DC``
-+      - DC intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_V``
-+      - Vertical intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_H``
-+      - Horizontal intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_D45``
-+      - D45 intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_D135``
-+      - D135 intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_D117``
-+      - D117 intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_D153``
-+      - D153 intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_D207``
-+      - D207 intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_D63``
-+      - D63 intra prediction.
-+    * - ``V4L2_VP9_INTRA_PRED_MODE_TM``
-+      - True motion intra prediction.
-+
-+.. c:type:: v4l2_vp9_segmentation
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: struct v4l2_vp9_segmentation
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 1 2
-+
-+    * - __u8
-+      - ``flags``
-+      - Combination of V4L2_VP9_SEGMENTATION_FLAG_* flags. See
-+        :c:type:`v4l2_vp9_segmentation_flags`.
-+    * - __u8
-+      - ``tree_probs[7]``
-+      - Specifies the probability values to be used when decoding a Segment-ID.
-+        See '5.15. Segmentation map' section of :ref:`vp9` for more details.
-+    * - __u8
-+      - ``pred_prob[3]``
-+      - Specifies the probability values to be used when decoding a
-+        Predicted-Segment-ID. See '6.4.14. Get segment id syntax'
-+        section of :ref:`vp9` for more details.
-+    * - __u8
-+      - ``padding[5]``
-+      - Used to align this struct on 64 bit. Shall be filled with zeroes.
-+    * - __u8
-+      - ``feature_enabled[8]``
-+      - Bitmask defining which features are enabled in each segment.
-+    * - __u8
-+      - ``feature_data[8][4]``
-+      - Data attached to each feature. Data entry is only valid if the feature
-+        is enabled.
-+
-+.. c:type:: v4l2_vp9_segment_feature
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_segment_feature
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_SEGMENT_FEATURE_QP_DELTA``
-+      - QP delta segment feature.
-+    * - ``V4L2_VP9_SEGMENT_FEATURE_LF``
-+      - Loop filter segment feature.
-+    * - ``V4L2_VP9_SEGMENT_FEATURE_REF_FRAME``
-+      - Reference frame segment feature.
-+    * - ``V4L2_VP9_SEGMENT_FEATURE_SKIP``
-+      - Skip segment feature.
-+    * - ``V4L2_VP9_SEGMENT_FEATURE_CNT``
-+      - Number of segment features.
-+
-+.. c:type:: v4l2_vp9_segmentation_flags
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_segmentation_flags
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_SEGMENTATION_FLAG_ENABLED``
-+      - Indicates that this frame makes use of the segmentation tool.
-+    * - ``V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP``
-+      - Indicates that the segmentation map should be updated during the
-+        decoding of this frame.
-+    * - ``V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE``
-+      - Indicates that the updates to the segmentation map are coded
-+        relative to the existing segmentation map.
-+    * - ``V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA``
-+      - Indicates that new parameters are about to be specified for each
-+        segment.
-+    * - ``V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE``
-+      - Indicates that the segmentation parameters represent the actual values
-+        to be used.
-+
-+.. c:type:: v4l2_vp9_quantization
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: struct v4l2_vp9_quantization
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 1 2
-+
-+    * - __u8
-+      - ``base_q_idx``
-+      - Indicates the base frame qindex.
-+    * - __s8
-+      - ``delta_q_y_dc``
-+      - Indicates the Y DC quantizer relative to base_q_idx.
-+    * - __s8
-+      - ``delta_q_uv_dc``
-+      - Indicates the UV DC quantizer relative to base_q_idx.
-+    * - __s8
-+      - ``delta_q_uv_ac``
-+      - Indicates the UV AC quantizer relative to base_q_idx.
-+    * - __u8
-+      - ``padding[4]``
-+      - Padding bytes used to align this struct on 64 bit. Must be set to 0.
-+
-+.. c:type:: v4l2_vp9_loop_filter
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: struct v4l2_vp9_loop_filter
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 1 2
-+
-+    * - __u8
-+      - ``flags``
-+      - Combination of V4L2_VP9_LOOP_FILTER_FLAG_* flags.
-+        See :c:type:`v4l2_vp9_loop_filter_flags`.
-+    * - __u8
-+      - ``level``
-+      - Indicates the loop filter strength.
-+    * - __u8
-+      - ``sharpness``
-+      - Indicates the sharpness level.
-+    * - __s8
-+      - ``ref_deltas[4]``
-+      - Contains the adjustment needed for the filter level based on the chosen
-+        reference frame.
-+    * - __s8
-+      - ``mode_deltas[2]``
-+      - Contains the adjustment needed for the filter level based on the chosen
-+        mode
-+    * - __u8
-+      - ``level_lookup[8][4][2]``
-+      - Level lookup table.
-+
-+
-+.. c:type:: v4l2_vp9_loop_filter_flags
-+
-+.. cssclass:: longtable
-+
-+.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}|
-+
-+.. flat-table:: enum v4l2_vp9_loop_filter_flags
-+    :header-rows:  0
-+    :stub-columns: 0
-+    :widths:       1 2
-+
-+    * - ``V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED``
-+      - When set, the filter level depends on the mode and reference frame used
-+        to predict a block.
-+    * - ``V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE``
-+      - When set, the bitstream contains additional syntax elements that
-+        specify which mode and reference frame deltas are to be updated.
-+
- .. raw:: latex
- 
-     \normalsize
-diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c
-index c4b5082849b6..b4802c9989fd 100644
---- a/drivers/media/v4l2-core/v4l2-ctrls-core.c
-+++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c
-@@ -289,6 +289,219 @@ static void std_log(const struct v4l2_ctrl *ctrl)
- 	}
- }
- 
-+static int
-+validate_vp9_lf_params(struct v4l2_vp9_loop_filter *lf)
-+{
-+	unsigned int i, j, k;
-+
-+	if (lf->flags &
-+	    ~(V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED |
-+	      V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE))
-+		return -EINVAL;
-+
-+	/*
-+	 * V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED implies
-+	 * V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE.
-+	 */
-+	if (lf->flags & V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE &&
-+	    !(lf->flags & V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED))
-+		return -EINVAL;
-+
-+	/* That all values are in the accepted range. */
-+	if (lf->level > GENMASK(5, 0))
-+		return -EINVAL;
-+
-+	if (lf->sharpness > GENMASK(2, 0))
-+		return -EINVAL;
-+
-+	for (i = 0; i < ARRAY_SIZE(lf->ref_deltas); i++) {
-+		if (lf->ref_deltas[i] < -63 || lf->ref_deltas[i] > 63)
-+			return -EINVAL;
-+	}
-+
-+	for (i = 0; i < ARRAY_SIZE(lf->mode_deltas); i++) {
-+		if (lf->mode_deltas[i] < -63 || lf->mode_deltas[i] > 63)
-+			return -EINVAL;
-+	}
-+
-+	for (i = 0; i < ARRAY_SIZE(lf->level_lookup); i++) {
-+		for (j = 0; j < ARRAY_SIZE(lf->level_lookup[0]); j++) {
-+			for (k = 0; k < ARRAY_SIZE(lf->level_lookup[0][0]); k++) {
-+				if (lf->level_lookup[i][j][k] > 63)
-+					return -EINVAL;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int
-+validate_vp9_quant_params(struct v4l2_vp9_quantization *quant)
-+{
-+	if (quant->delta_q_y_dc < -15 || quant->delta_q_y_dc > 15 ||
-+	    quant->delta_q_uv_dc < -15 || quant->delta_q_uv_dc > 15 ||
-+	    quant->delta_q_uv_ac < -15 || quant->delta_q_uv_ac > 15)
-+		return -EINVAL;
-+
-+	memset(quant->padding, 0, sizeof(quant->padding));
-+	return 0;
-+}
-+
-+static int
-+validate_vp9_seg_params(struct v4l2_vp9_segmentation *seg)
-+{
-+	unsigned int i, j;
-+
-+	if (seg->flags &
-+	    ~(V4L2_VP9_SEGMENTATION_FLAG_ENABLED |
-+	      V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP |
-+	      V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE |
-+	      V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA |
-+	      V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE))
-+		return -EINVAL;
-+
-+	/*
-+	 * V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP and
-+	 * V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA imply
-+	 * V4L2_VP9_SEGMENTATION_FLAG_ENABLED.
-+	 */
-+	if ((seg->flags &
-+	     (V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP |
-+	      V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA)) &&
-+	    !(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED))
-+		return -EINVAL;
-+
-+	/*
-+	 * V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE implies
-+	 * V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP.
-+	 */
-+	if (seg->flags & V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE &&
-+	    !(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP))
-+		return -EINVAL;
-+
-+	/*
-+	 * V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE implies
-+	 * V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA.
-+	 */
-+	if (seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE &&
-+	    !(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA))
-+		return -EINVAL;
-+
-+	for (i = 0; i < ARRAY_SIZE(seg->feature_enabled); i++) {
-+		if (seg->feature_enabled[i] &
-+		    ~(V4L2_VP9_SEGMENT_FEATURE_QP_DELTA |
-+		      V4L2_VP9_SEGMENT_FEATURE_LF |
-+		      V4L2_VP9_SEGMENT_FEATURE_REF_FRAME |
-+		      V4L2_VP9_SEGMENT_FEATURE_SKIP))
-+			return -EINVAL;
-+	}
-+
-+	for (i = 0; i < ARRAY_SIZE(seg->feature_data); i++) {
-+		const int range[] = {255, 63, 3, 0};
-+
-+		for (j = 0; j < ARRAY_SIZE(seg->feature_data[j]); j++) {
-+			if (seg->feature_data[i][j] < -range[j] ||
-+			    seg->feature_data[i][j] > range[j])
-+				return -EINVAL;
-+		}
-+	}
-+
-+	memset(seg->padding, 0, sizeof(seg->padding));
-+	return 0;
-+}
-+
-+static int
-+validate_vp9_frame_decode_params(struct v4l2_ctrl_vp9_frame_decode_params *dec_params)
-+{
-+	int ret;
-+
-+	/* Make sure we're not passed invalid flags. */
-+	if (dec_params->flags &
-+	    ~(V4L2_VP9_FRAME_FLAG_KEY_FRAME |
-+	      V4L2_VP9_FRAME_FLAG_SHOW_FRAME |
-+	      V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT |
-+	      V4L2_VP9_FRAME_FLAG_INTRA_ONLY |
-+	      V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV |
-+	      V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX |
-+	      V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE |
-+	      V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING |
-+	      V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING |
-+	      V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING))
-+		return -EINVAL;
-+
-+	/*
-+	 * The refresh context and error resilient flags are mutually exclusive.
-+	 * Same goes for parallel decoding and error resilient modes.
-+	 */
-+	if (dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT &&
-+	    dec_params->flags &
-+	    (V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX |
-+	     V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE))
-+		return -EINVAL;
-+
-+	if (dec_params->profile > V4L2_VP9_PROFILE_MAX)
-+		return -EINVAL;
-+
-+	if (dec_params->reset_frame_context > V4L2_VP9_RESET_FRAME_CTX_ALL)
-+		return -EINVAL;
-+
-+	if (dec_params->frame_context_idx >= V4L2_VP9_NUM_FRAME_CTX)
-+		return -EINVAL;
-+
-+	/*
-+	 * Profiles 0 and 1 only support 8-bit depth, profiles 2 and 3 only 10
-+	 * and 12 bit depths.
-+	 */
-+	if ((dec_params->profile < 2 && dec_params->bit_depth != 8) ||
-+	    (dec_params->profile >= 2 &&
-+	     (dec_params->bit_depth != 10 && dec_params->bit_depth != 12)))
-+		return -EINVAL;
-+
-+	/* Profile 0 and 2 only accept YUV 4:2:0. */
-+	if ((dec_params->profile == 0 || dec_params->profile == 2) &&
-+	    (!(dec_params->flags & V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING) ||
-+	     !(dec_params->flags & V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING)))
-+		return -EINVAL;
-+
-+	/* Profile 1 and 3 only accept YUV 4:2:2, 4:4:0 and 4:4:4. */
-+	if ((dec_params->profile == 1 || dec_params->profile == 3) &&
-+	    ((dec_params->flags & V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING) &&
-+	     (dec_params->flags & V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING)))
-+		return -EINVAL;
-+
-+	if (dec_params->interpolation_filter > V4L2_VP9_INTERP_FILTER_SWITCHABLE)
-+		return -EINVAL;
-+
-+	/*
-+	 * According to the spec, tile_cols_log2 shall be less than or equal
-+	 * to 6.
-+	 */
-+	if (dec_params->tile_cols_log2 > 6)
-+		return -EINVAL;
-+
-+	if (dec_params->tx_mode > V4L2_VP9_TX_MODE_SELECT)
-+		return -EINVAL;
-+
-+	if (dec_params->reference_mode > V4L2_VP9_REF_MODE_SELECT)
-+		return -EINVAL;
-+
-+	ret = validate_vp9_lf_params(&dec_params->lf);
-+	if (ret)
-+		return ret;
-+
-+	ret = validate_vp9_quant_params(&dec_params->quant);
-+	if (ret)
-+		return ret;
-+
-+	ret = validate_vp9_seg_params(&dec_params->seg);
-+	if (ret)
-+		return ret;
-+
-+	memset(dec_params->padding, 0, sizeof(dec_params->padding));
-+	return 0;
-+}
-+
- /*
-  * Round towards the closest legal value. Be careful when we are
-  * close to the maximum range of the control type to prevent
-@@ -574,6 +787,12 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx,
- 		zero_padding(p_vp8_frame->coder_state);
- 		break;
- 
-+	case V4L2_CTRL_TYPE_VP9_FRAME_DECODE_PARAMS:
-+		return validate_vp9_frame_decode_params(p);
-+
-+	case V4L2_CTRL_TYPE_VP9_FRAME_CONTEXT:
-+		break;
-+
- 	case V4L2_CTRL_TYPE_HEVC_SPS:
- 		p_hevc_sps = p;
- 
-@@ -1231,6 +1450,12 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl,
- 	case V4L2_CTRL_TYPE_VP8_FRAME:
- 		elem_size = sizeof(struct v4l2_ctrl_vp8_frame);
- 		break;
-+	case V4L2_CTRL_TYPE_VP9_FRAME_CONTEXT:
-+		elem_size = sizeof(struct v4l2_ctrl_vp9_frame_ctx);
-+		break;
-+	case V4L2_CTRL_TYPE_VP9_FRAME_DECODE_PARAMS:
-+		elem_size = sizeof(struct v4l2_ctrl_vp9_frame_decode_params);
-+		break;
- 	case V4L2_CTRL_TYPE_HEVC_SPS:
- 		elem_size = sizeof(struct v4l2_ctrl_hevc_sps);
- 		break;
-diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c
-index b6344bbf1e00..22a031e25499 100644
---- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c
-+++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c
-@@ -940,6 +940,11 @@ const char *v4l2_ctrl_get_name(u32 id)
- 	case V4L2_CID_MPEG_VIDEO_VP8_PROFILE:			return "VP8 Profile";
- 	case V4L2_CID_MPEG_VIDEO_VP9_PROFILE:			return "VP9 Profile";
- 	case V4L2_CID_MPEG_VIDEO_VP9_LEVEL:			return "VP9 Level";
-+	case V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS:	return "VP9 Frame Decode Parameters";
-+	case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0):		return "VP9 Frame Context 0";
-+	case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(1):		return "VP9 Frame Context 1";
-+	case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(2):		return "VP9 Frame Context 2";
-+	case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(3):		return "VP9 Frame Context 3";
- 
- 	/* HEVC controls */
- 	case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP:		return "HEVC I-Frame QP Value";
-@@ -1479,6 +1484,15 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
- 	case V4L2_CID_STATELESS_VP8_FRAME:
- 		*type = V4L2_CTRL_TYPE_VP8_FRAME;
- 		break;
-+	case V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS:
-+		*type = V4L2_CTRL_TYPE_VP9_FRAME_DECODE_PARAMS;
-+		break;
-+	case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0):
-+	case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(1):
-+	case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(2):
-+	case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(3):
-+		*type = V4L2_CTRL_TYPE_VP9_FRAME_CONTEXT;
-+		break;
- 	case V4L2_CID_MPEG_VIDEO_HEVC_SPS:
- 		*type = V4L2_CTRL_TYPE_HEVC_SPS;
- 		break;
-diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
-index fe43d785414c..47f812a081ca 100644
---- a/drivers/media/v4l2-core/v4l2-ioctl.c
-+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
-@@ -1394,6 +1394,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
- 		case V4L2_PIX_FMT_VP8:		descr = "VP8"; break;
- 		case V4L2_PIX_FMT_VP8_FRAME:    descr = "VP8 Frame"; break;
- 		case V4L2_PIX_FMT_VP9:		descr = "VP9"; break;
-+		case V4L2_PIX_FMT_VP9_FRAME:    descr = "VP9 Frame"; break;
- 		case V4L2_PIX_FMT_HEVC:		descr = "HEVC"; break; /* aka H.265 */
- 		case V4L2_PIX_FMT_HEVC_SLICE:	descr = "HEVC Parsed Slice Data"; break;
- 		case V4L2_PIX_FMT_FWHT:		descr = "FWHT"; break; /* used in vicodec */
-diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h
-index 575b59fbac77..f62c529b6a70 100644
---- a/include/media/v4l2-ctrls.h
-+++ b/include/media/v4l2-ctrls.h
-@@ -18,6 +18,7 @@
-  * This will move to the public headers once this API is fully stable.
-  */
- #include <media/hevc-ctrls.h>
-+#include <media/vp9-ctrls.h>
- 
- /* forward references */
- struct file;
-@@ -50,6 +51,8 @@ struct video_device;
-  * @p_h264_decode_params:	Pointer to a struct v4l2_ctrl_h264_decode_params.
-  * @p_h264_pred_weights:	Pointer to a struct v4l2_ctrl_h264_pred_weights.
-  * @p_vp8_frame:		Pointer to a VP8 frame params structure.
-+ * @p_vp9_frame_ctx:		Pointer to a VP9 frame context structure.
-+ * @p_vp9_frame_decode_params:	Pointer to a VP9 frame params structure.
-  * @p_hevc_sps:			Pointer to an HEVC sequence parameter set structure.
-  * @p_hevc_pps:			Pointer to an HEVC picture parameter set structure.
-  * @p_hevc_slice_params:	Pointer to an HEVC slice parameters structure.
-@@ -82,6 +85,8 @@ union v4l2_ctrl_ptr {
- 	struct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params;
- 	struct v4l2_ctrl_hdr10_cll_info *p_hdr10_cll;
- 	struct v4l2_ctrl_hdr10_mastering_display *p_hdr10_mastering;
-+	struct v4l2_ctrl_vp9_frame_ctx *p_vp9_frame_ctx;
-+	struct v4l2_ctrl_vp9_frame_decode_params *p_vp9_frame_decode_params;
- 	struct v4l2_area *p_area;
- 	void *p;
- 	const void *p_const;
-diff --git a/include/media/vp9-ctrls.h b/include/media/vp9-ctrls.h
-new file mode 100644
-index 000000000000..f62f528d4b39
---- /dev/null
-+++ b/include/media/vp9-ctrls.h
-@@ -0,0 +1,486 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * These are the VP9 state controls for use with stateless VP9
-+ * codec drivers.
-+ *
-+ * It turns out that these structs are not stable yet and will undergo
-+ * more changes. So keep them private until they are stable and ready to
-+ * become part of the official public API.
-+ */
-+
-+#ifndef _VP9_CTRLS_H_
-+#define _VP9_CTRLS_H_
-+
-+#include <linux/types.h>
-+
-+#define V4L2_PIX_FMT_VP9_FRAME v4l2_fourcc('V', 'P', '9', 'F')
-+
-+#define V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(i)	(V4L2_CID_CODEC_BASE + 4000 + (i))
-+#define V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS	(V4L2_CID_CODEC_BASE + 4004)
-+#define V4L2_CTRL_TYPE_VP9_FRAME_CONTEXT		0x400
-+#define V4L2_CTRL_TYPE_VP9_FRAME_DECODE_PARAMS		0x404
-+
-+/**
-+ * enum v4l2_vp9_loop_filter_flags - VP9 loop filter flags
-+ *
-+ * @V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED: the filter level depends on
-+ *					     the mode and reference frame used
-+ *					     to predict a block
-+ * @V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE: the bitstream contains additional
-+ *					    syntax elements that specify which
-+ *					    mode and reference frame deltas
-+ *					    are to be updated
-+ *
-+ * Those are the flags you should pass to &v4l2_vp9_loop_filter.flags. See
-+ * section '7.2.8 Loop filter semantics' of the VP9 specification for more
-+ * details.
-+ */
-+enum v4l2_vp9_loop_filter_flags {
-+	V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED = 1 << 0,
-+	V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE = 1 << 1,
-+};
-+
-+/**
-+ * struct v4l2_vp9_loop_filter - VP9 loop filter parameters
-+ *
-+ * @flags: combination of V4L2_VP9_LOOP_FILTER_FLAG_* flags
-+ * @level: indicates the loop filter strength
-+ * @sharpness: indicates the sharpness level
-+ * @ref_deltas: contains the adjustment needed for the filter level based on
-+ *		the chosen reference frame
-+ * @mode_deltas: contains the adjustment needed for the filter level based on
-+ *		 the chosen mode
-+ * @level_lookup: level lookup table
-+ *
-+ * This structure contains all loop filter related parameters. See sections
-+ * '7.2.8 Loop filter semantics' and '8.8.1 Loop filter frame init process'
-+ * of the VP9 specification for more details.
-+ */
-+struct v4l2_vp9_loop_filter {
-+	__u8 flags;
-+	__u8 level;
-+	__u8 sharpness;
-+	__s8 ref_deltas[4];
-+	__s8 mode_deltas[2];
-+	__u8 level_lookup[8][4][2];
-+	__u8 padding;
-+};
-+
-+/**
-+ * struct v4l2_vp9_quantization - VP9 quantization parameters
-+ *
-+ * @base_q_idx: indicates the base frame qindex
-+ * @delta_q_y_dc: indicates the Y DC quantizer relative to base_q_idx
-+ * @delta_q_uv_dc: indicates the UV DC quantizer relative to base_q_idx
-+ * @delta_q_uv_ac indicates the UV AC quantizer relative to base_q_idx
-+ * @padding: padding bytes to align things on 64 bits. Must be set to 0
-+ *
-+ * Encodes the quantization parameters. See section '7.2.9 Quantization params
-+ * syntax' of the VP9 specification for more details.
-+ */
-+struct v4l2_vp9_quantization {
-+	__u8 base_q_idx;
-+	__s8 delta_q_y_dc;
-+	__s8 delta_q_uv_dc;
-+	__s8 delta_q_uv_ac;
-+	__u8 padding[4];
-+};
-+
-+/**
-+ * enum v4l2_vp9_segmentation_flags - VP9 segmentation flags
-+ *
-+ * @V4L2_VP9_SEGMENTATION_FLAG_ENABLED: indicates that this frame makes use of
-+ *					the segmentation tool
-+ * @V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP: indicates that the segmentation map
-+ *					   should be updated during the
-+ *					   decoding of this frame
-+ * @V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE: indicates that the updates to
-+ *						the segmentation map are coded
-+ *						relative to the existing
-+ *						segmentation map
-+ * @V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA: indicates that new parameters are
-+ *					    about to be specified for each
-+ *					    segment
-+ * @V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE: indicates that the
-+ *						    segmentation parameters
-+ *						    represent the actual values
-+ *						    to be used
-+ *
-+ * Those are the flags you should pass to &v4l2_vp9_segmentation.flags. See
-+ * section '7.2.10 Segmentation params syntax' of the VP9 specification for
-+ * more details.
-+ */
-+enum v4l2_vp9_segmentation_flags {
-+	V4L2_VP9_SEGMENTATION_FLAG_ENABLED = 1 << 0,
-+	V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP = 1 << 1,
-+	V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE = 1 << 2,
-+	V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA = 1 << 3,
-+	V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE = 1 << 4,
-+};
-+
-+#define V4L2_VP9_SEGMENT_FEATURE_ENABLED(id)	(1 << (id))
-+#define V4L2_VP9_SEGMENT_FEATURE_ENABLED_MASK	0xf
-+
-+/**
-+ * enum v4l2_vp9_segment_feature - VP9 segment feature IDs
-+ *
-+ * @V4L2_VP9_SEGMENT_FEATURE_QP_DELTA: QP delta segment feature
-+ * @V4L2_VP9_SEGMENT_FEATURE_LF: loop filter segment feature
-+ * @V4L2_VP9_SEGMENT_FEATURE_REF_FRAME: reference frame segment feature
-+ * @V4L2_VP9_SEGMENT_FEATURE_SKIP: skip segment feature
-+ * @V4L2_VP9_SEGMENT_FEATURE_CNT: number of segment features
-+ *
-+ * Segment feature IDs. See section '7.2.10 Segmentation params syntax' of the
-+ * VP9 specification for more details.
-+ */
-+enum v4l2_vp9_segment_feature {
-+	V4L2_VP9_SEGMENT_FEATURE_QP_DELTA,
-+	V4L2_VP9_SEGMENT_FEATURE_LF,
-+	V4L2_VP9_SEGMENT_FEATURE_REF_FRAME,
-+	V4L2_VP9_SEGMENT_FEATURE_SKIP,
-+	V4L2_VP9_SEGMENT_FEATURE_CNT,
-+};
-+
-+/**
-+ * struct v4l2_vp9_segmentation - VP9 segmentation parameters
-+ *
-+ * @flags: combination of V4L2_VP9_SEGMENTATION_FLAG_* flags
-+ * @tree_probs: specifies the probability values to be used when
-+ *              decoding a Segment-ID. See '5.15. Segmentation map'
-+ *              section of the VP9 specification for more details.
-+ * @pred_prob: specifies the probability values to be used when decoding a
-+ *	       Predicted-Segment-ID. See '6.4.14. Get segment id syntax'
-+ *	       section of :ref:`vp9` for more details..
-+ * @padding: padding used to make things aligned on 64 bits. Shall be zero
-+ *	     filled
-+ * @feature_enabled: bitmask defining which features are enabled in each
-+ *		     segment
-+ * @feature_data: data attached to each feature. Data entry is only valid if
-+ *		  the feature is enabled
-+ *
-+ * Encodes the quantization parameters. See section '7.2.10 Segmentation
-+ * params syntax' of the VP9 specification for more details.
-+ */
-+struct v4l2_vp9_segmentation {
-+	__u8 flags;
-+	__u8 tree_probs[7];
-+	__u8 pred_probs[3];
-+	__u8 padding[5];
-+	__u8 feature_enabled[8];
-+	__s16 feature_data[8][4];
-+};
-+
-+/**
-+ * enum v4l2_vp9_intra_prediction_mode - VP9 Intra prediction modes
-+ *
-+ * @V4L2_VP9_INTRA_PRED_DC: DC intra prediction
-+ * @V4L2_VP9_INTRA_PRED_MODE_V: vertical intra prediction
-+ * @V4L2_VP9_INTRA_PRED_MODE_H: horizontal intra prediction
-+ * @V4L2_VP9_INTRA_PRED_MODE_D45: D45 intra prediction
-+ * @V4L2_VP9_INTRA_PRED_MODE_D135: D135 intra prediction
-+ * @V4L2_VP9_INTRA_PRED_MODE_D117: D117 intra prediction
-+ * @V4L2_VP9_INTRA_PRED_MODE_D153: D153 intra prediction
-+ * @V4L2_VP9_INTRA_PRED_MODE_D207: D207 intra prediction
-+ * @V4L2_VP9_INTRA_PRED_MODE_D63: D63 intra prediction
-+ * @V4L2_VP9_INTRA_PRED_MODE_TM: True Motion intra prediction
-+ *
-+ * See section '7.4.5 Intra frame mode info semantics' for more details.
-+ */
-+enum v4l2_vp9_intra_prediction_mode {
-+	V4L2_VP9_INTRA_PRED_MODE_DC,
-+	V4L2_VP9_INTRA_PRED_MODE_V,
-+	V4L2_VP9_INTRA_PRED_MODE_H,
-+	V4L2_VP9_INTRA_PRED_MODE_D45,
-+	V4L2_VP9_INTRA_PRED_MODE_D135,
-+	V4L2_VP9_INTRA_PRED_MODE_D117,
-+	V4L2_VP9_INTRA_PRED_MODE_D153,
-+	V4L2_VP9_INTRA_PRED_MODE_D207,
-+	V4L2_VP9_INTRA_PRED_MODE_D63,
-+	V4L2_VP9_INTRA_PRED_MODE_TM,
-+};
-+
-+/**
-+ * struct v4l2_vp9_mv_probabilities - VP9 Motion vector probabilities
-+ * @joint: motion vector joint probabilities
-+ * @sign: motion vector sign probabilities
-+ * @class: motion vector class probabilities
-+ * @class0_bit: motion vector class0 bit probabilities
-+ * @bits: motion vector bits probabilities
-+ * @class0_fr: motion vector class0 fractional bit probabilities
-+ * @fr: motion vector fractional bit probabilities
-+ * @class0_hp: motion vector class0 high precision fractional bit probabilities
-+ * @hp: motion vector high precision fractional bit probabilities
-+ */
-+struct v4l2_vp9_mv_probabilities {
-+	__u8 joint[3];
-+	__u8 sign[2];
-+	__u8 class[2][10];
-+	__u8 class0_bit[2];
-+	__u8 bits[2][10];
-+	__u8 class0_fr[2][2][3];
-+	__u8 fr[2][3];
-+	__u8 class0_hp[2];
-+	__u8 hp[2];
-+};
-+
-+/**
-+ * struct v4l2_vp9_probabilities - VP9 Probabilities
-+ *
-+ * @tx8: TX 8x8 probabilities
-+ * @tx16: TX 16x16 probabilities
-+ * @tx32: TX 32x32 probabilities
-+ * @coef: coefficient probabilities
-+ * @skip: skip probabilities
-+ * @inter_mode: inter mode probabilities
-+ * @interp_filter: interpolation filter probabilities
-+ * @is_inter: is inter-block probabilities
-+ * @comp_mode: compound prediction mode probabilities
-+ * @single_ref: single ref probabilities
-+ * @comp_ref: compound ref probabilities
-+ * @y_mode: Y prediction mode probabilities
-+ * @uv_mode: UV prediction mode probabilities
-+ * @partition: partition probabilities
-+ * @mv: motion vector probabilities
-+ *
-+ * Structure containing most VP9 probabilities. See the VP9 specification
-+ * for more details.
-+ */
-+struct v4l2_vp9_probabilities {
-+	__u8 tx8[2][1];
-+	__u8 tx16[2][2];
-+	__u8 tx32[2][3];
-+	__u8 coef[4][2][2][6][6][3];
-+	__u8 skip[3];
-+	__u8 inter_mode[7][3];
-+	__u8 interp_filter[4][2];
-+	__u8 is_inter[4];
-+	__u8 comp_mode[5];
-+	__u8 single_ref[5][2];
-+	__u8 comp_ref[5];
-+	__u8 y_mode[4][9];
-+	__u8 uv_mode[10][9];
-+	__u8 partition[16][3];
-+
-+	struct v4l2_vp9_mv_probabilities mv;
-+};
-+
-+/**
-+ * enum v4l2_vp9_reset_frame_context - Valid values for
-+ *			&v4l2_ctrl_vp9_frame_decode_params->reset_frame_context
-+ *
-+ * @V4L2_VP9_RESET_FRAME_CTX_NONE: don't reset any frame context
-+ * @V4L2_VP9_RESET_FRAME_CTX_SPEC: reset the frame context pointed by
-+ *			&v4l2_ctrl_vp9_frame_decode_params.frame_context_idx
-+ * @V4L2_VP9_RESET_FRAME_CTX_ALL: reset all frame contexts
-+ *
-+ * See section '7.2 Uncompressed header semantics' of the VP9 specification
-+ * for more details.
-+ */
-+enum v4l2_vp9_reset_frame_context {
-+	V4L2_VP9_RESET_FRAME_CTX_NONE,
-+	V4L2_VP9_RESET_FRAME_CTX_SPEC,
-+	V4L2_VP9_RESET_FRAME_CTX_ALL,
-+};
-+
-+/**
-+ * enum v4l2_vp9_interpolation_filter - VP9 interpolation filter types
-+ *
-+ * @V4L2_VP9_INTERP_FILTER_8TAP: height tap filter
-+ * @V4L2_VP9_INTERP_FILTER_8TAP_SMOOTH: height tap smooth filter
-+ * @V4L2_VP9_INTERP_FILTER_8TAP_SHARP: height tap sharp filter
-+ * @V4L2_VP9_INTERP_FILTER_BILINEAR: bilinear filter
-+ * @V4L2_VP9_INTERP_FILTER_SWITCHABLE: filter selection is signaled at the
-+ *				       block level
-+ *
-+ * See section '7.2.7 Interpolation filter semantics' of the VP9 specification
-+ * for more details.
-+ */
-+enum v4l2_vp9_interpolation_filter {
-+	V4L2_VP9_INTERP_FILTER_8TAP,
-+	V4L2_VP9_INTERP_FILTER_8TAP_SMOOTH,
-+	V4L2_VP9_INTERP_FILTER_8TAP_SHARP,
-+	V4L2_VP9_INTERP_FILTER_BILINEAR,
-+	V4L2_VP9_INTERP_FILTER_SWITCHABLE,
-+};
-+
-+/**
-+ * enum v4l2_vp9_reference_mode - VP9 reference modes
-+ *
-+ * @V4L2_VP9_REF_MODE_SINGLE: indicates that all the inter blocks use only a
-+ *			      single reference frame to generate motion
-+ *			      compensated prediction
-+ * @V4L2_VP9_REF_MODE_COMPOUND: requires all the inter blocks to use compound
-+ *				mode. Single reference frame prediction is not
-+ *				allowed
-+ * @V4L2_VP9_REF_MODE_SELECT: allows each individual inter block to select
-+ *			      between single and compound prediction modes
-+ *
-+ * See section '7.3.6 Frame reference mode semantics' of the VP9 specification
-+ * for more details.
-+ */
-+enum v4l2_vp9_reference_mode {
-+	V4L2_VP9_REF_MODE_SINGLE,
-+	V4L2_VP9_REF_MODE_COMPOUND,
-+	V4L2_VP9_REF_MODE_SELECT,
-+};
-+
-+/**
-+ * enum v4l2_vp9_tx_mode - VP9 TX modes
-+ *
-+ * @V4L2_VP9_TX_MODE_ONLY_4X4: transform size is 4x4
-+ * @V4L2_VP9_TX_MODE_ALLOW_8X8: transform size can be up to 8x8
-+ * @V4L2_VP9_TX_MODE_ALLOW_16X16: transform size can be up to 16x16
-+ * @V4L2_VP9_TX_MODE_ALLOW_32X32: transform size can be up to 32x32
-+ * @V4L2_VP9_TX_MODE_SELECT: bitstream contains transform size for each block
-+ *
-+ * See section '7.3.1 Tx mode semantics' of the VP9 specification for more
-+ * details.
-+ */
-+enum v4l2_vp9_tx_mode {
-+	V4L2_VP9_TX_MODE_ONLY_4X4,
-+	V4L2_VP9_TX_MODE_ALLOW_8X8,
-+	V4L2_VP9_TX_MODE_ALLOW_16X16,
-+	V4L2_VP9_TX_MODE_ALLOW_32X32,
-+	V4L2_VP9_TX_MODE_SELECT,
-+};
-+
-+/**
-+ * enum v4l2_vp9_ref_id - VP9 Reference frame IDs
-+ *
-+ * @V4L2_REF_ID_LAST: last reference frame
-+ * @V4L2_REF_ID_GOLDEN: golden reference frame
-+ * @V4L2_REF_ID_ALTREF: alternative reference frame
-+ * @V4L2_REF_ID_CNT: number of reference frames
-+ *
-+ * See section '7.4.12 Ref frames semantics' of the VP9 specification for more
-+ * details.
-+ */
-+enum v4l2_vp9_ref_id {
-+	V4L2_REF_ID_LAST,
-+	V4L2_REF_ID_GOLDEN,
-+	V4L2_REF_ID_ALTREF,
-+	V4L2_REF_ID_CNT,
-+};
-+
-+/**
-+ * enum v4l2_vp9_frame_flags - VP9 frame flags
-+ * @V4L2_VP9_FRAME_FLAG_KEY_FRAME: the frame is a key frame
-+ * @V4L2_VP9_FRAME_FLAG_SHOW_FRAME: the frame should be displayed
-+ * @V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT: the decoding should be error resilient
-+ * @V4L2_VP9_FRAME_FLAG_INTRA_ONLY: the frame does not reference other frames
-+ * @V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV: the frame might can high precision
-+ *					    motion vectors
-+ * @V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX: frame context should be updated
-+ *					   after decoding
-+ * @V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE: parallel decoding is used
-+ * @V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING: vertical subsampling is enabled
-+ * @V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING: horizontal subsampling is enabled
-+ * @V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING: full UV range is used
-+ *
-+ * Check the VP9 specification for more details.
-+ */
-+enum v4l2_vp9_frame_flags {
-+	V4L2_VP9_FRAME_FLAG_KEY_FRAME = 1 << 0,
-+	V4L2_VP9_FRAME_FLAG_SHOW_FRAME = 1 << 1,
-+	V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT = 1 << 2,
-+	V4L2_VP9_FRAME_FLAG_INTRA_ONLY = 1 << 3,
-+	V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV = 1 << 4,
-+	V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX = 1 << 5,
-+	V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE = 1 << 6,
-+	V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING = 1 << 7,
-+	V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING = 1 << 8,
-+	V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING = 1 << 9,
-+};
-+
-+#define V4L2_VP9_PROFILE_MAX		3
-+
-+/**
-+ * struct v4l2_ctrl_vp9_frame_decode_params - VP9 frame decoding control
-+ *
-+ * @flags: combination of V4L2_VP9_FRAME_FLAG_* flags
-+ * @compressed_header_size: compressed header size in bytes
-+ * @uncompressed_header_size: uncompressed header size in bytes
-+ * @profile: VP9 profile. Can be 0, 1, 2 or 3
-+ * @reset_frame_context: specifies whether the frame context should be reset
-+ *			 to default values. See &v4l2_vp9_reset_frame_context
-+ *			 for more details
-+ * @frame_context_idx: frame context that should be used/updated
-+ * @bit_depth: bits per components. Can be 8, 10 or 12. Note that not all
-+ *	       profiles support 10 and/or 12 bits depths
-+ * @interpolation_filter: specifies the filter selection used for performing
-+ *			  inter prediction. See &v4l2_vp9_interpolation_filter
-+ *			  for more details
-+ * @tile_cols_log2: specifies the base 2 logarithm of the width of each tile
-+ *		    (where the width is measured in units of 8x8 blocks).
-+ *		    Shall be less than or equal to 6
-+ * @tile_rows_log2: specifies the base 2 logarithm of the height of each tile
-+ *		    (where the height is measured in units of 8x8 blocks)
-+ * @tx_mode: specifies the TX mode. See &v4l2_vp9_tx_mode for more details
-+ * @reference_mode: specifies the type of inter prediction to be used. See
-+ *		    &v4l2_vp9_reference_mode for more details
-+ * @padding: needed to make this struct 64 bit aligned. Shall be filled with
-+ *	     zeros
-+ * @frame_width_minus_1: add 1 to it and you'll get the frame width expressed
-+ *			 in pixels
-+ * @frame_height_minus_1: add 1 to it and you'll get the frame height expressed
-+ *			  in pixels
-+ * @frame_width_minus_1: add 1 to it and you'll get the expected render width
-+ *			 expressed in pixels. This is not used during the
-+ *			 decoding process but might be used by HW scalers to
-+ *			 prepare a frame that's ready for scanout
-+ * @frame_height_minus_1: add 1 to it and you'll get the expected render height
-+ *			 expressed in pixels. This is not used during the
-+ *			 decoding process but might be used by HW scalers to
-+ *			 prepare a frame that's ready for scanout
-+ * @refs: array of ref frames timestamps. See &v4l2_vp9_ref_id for more details
-+ * @lf: loop filter parameters. See &v4l2_vp9_loop_filter for more details
-+ * @quant: quantization parameters. See &v4l2_vp9_quantization for more details
-+ * @seg: segmentation parameters. See &v4l2_vp9_segmentation for more details
-+ * @probs: probabilities. See &v4l2_vp9_probabilities for more details
-+ */
-+struct v4l2_ctrl_vp9_frame_decode_params {
-+	__u32 flags;
-+	__u16 compressed_header_size;
-+	__u16 uncompressed_header_size;
-+	__u8 profile;
-+	__u8 reset_frame_context;
-+	__u8 frame_context_idx;
-+	__u8 bit_depth;
-+	__u8 interpolation_filter;
-+	__u8 tile_cols_log2;
-+	__u8 tile_rows_log2;
-+	__u8 tx_mode;
-+	__u8 reference_mode;
-+	__u8 padding[7];
-+	__u16 frame_width_minus_1;
-+	__u16 frame_height_minus_1;
-+	__u16 render_width_minus_1;
-+	__u16 render_height_minus_1;
-+	__u64 refs[V4L2_REF_ID_CNT];
-+	struct v4l2_vp9_loop_filter lf;
-+	struct v4l2_vp9_quantization quant;
-+	struct v4l2_vp9_segmentation seg;
-+	struct v4l2_vp9_probabilities probs;
-+};
-+
-+#define V4L2_VP9_NUM_FRAME_CTX	4
-+
-+/**
-+ * struct v4l2_ctrl_vp9_frame_ctx - VP9 frame context control
-+ *
-+ * @probs: VP9 probabilities
-+ *
-+ * This control is accessed in both direction. The user should initialize the
-+ * 4 contexts with default values just after starting the stream. Then before
-+ * decoding a frame it should query the current frame context (the one passed
-+ * through &v4l2_ctrl_vp9_frame_decode_params.frame_context_idx) to initialize
-+ * &v4l2_ctrl_vp9_frame_decode_params.probs. The probs are then adjusted based
-+ * on the bitstream info and passed to the kernel. The codec should update
-+ * the frame context after the frame has been decoded, so that next time
-+ * userspace query this context it contains the updated probabilities.
-+ */
-+struct v4l2_ctrl_vp9_frame_ctx {
-+	struct v4l2_vp9_probabilities probs;
-+};
-+
-+#endif /* _VP9_CTRLS_H_ */
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Boris Brezillon <boris.brezillon@collabora.com>
-Date: Mon, 2 Nov 2020 21:05:51 +0200
-Subject: [PATCH] media: rkvdec: Add the VP9 backend
-
-The Rockchip VDEC supports VP9 profile 0 up to 4096x2304@30fps. Add
-a backend for this new format.
-
-Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Adrian Ratiu <adrian.ratiu@collabora.com>
----
- drivers/staging/media/rkvdec/Makefile     |    2 +-
- drivers/staging/media/rkvdec/rkvdec-vp9.c | 1577 +++++++++++++++++++++
- drivers/staging/media/rkvdec/rkvdec.c     |   59 +-
- drivers/staging/media/rkvdec/rkvdec.h     |    6 +
- 4 files changed, 1642 insertions(+), 2 deletions(-)
- create mode 100644 drivers/staging/media/rkvdec/rkvdec-vp9.c
-
-diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile
-index c08fed0a39f9..cb86b429cfaa 100644
---- a/drivers/staging/media/rkvdec/Makefile
-+++ b/drivers/staging/media/rkvdec/Makefile
-@@ -1,3 +1,3 @@
- obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o
- 
--rockchip-vdec-y += rkvdec.o rkvdec-h264.o
-+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o
-diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c
-new file mode 100644
-index 000000000000..8b443ed511c9
---- /dev/null
-+++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c
-@@ -0,0 +1,1577 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Rockchip Video Decoder VP9 backend
-+ *
-+ * Copyright (C) 2019 Collabora, Ltd.
-+ *	Boris Brezillon <boris.brezillon@collabora.com>
-+ *
-+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
-+ *	Alpha Lin <Alpha.Lin@rock-chips.com>
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/vmalloc.h>
-+#include <media/v4l2-mem2mem.h>
-+
-+#include "rkvdec.h"
-+#include "rkvdec-regs.h"
-+
-+#define RKVDEC_VP9_PROBE_SIZE		4864
-+#define RKVDEC_VP9_COUNT_SIZE		13232
-+#define RKVDEC_VP9_MAX_SEGMAP_SIZE	73728
-+
-+struct rkvdec_vp9_intra_mode_probs {
-+	u8 y_mode[105];
-+	u8 uv_mode[23];
-+};
-+
-+struct rkvdec_vp9_intra_only_frame_probs {
-+	u8 coef_intra[4][2][128];
-+	struct rkvdec_vp9_intra_mode_probs intra_mode[10];
-+};
-+
-+struct rkvdec_vp9_inter_frame_probs {
-+	u8 y_mode[4][9];
-+	u8 comp_mode[5];
-+	u8 comp_ref[5];
-+	u8 single_ref[5][2];
-+	u8 inter_mode[7][3];
-+	u8 interp_filter[4][2];
-+	u8 padding0[11];
-+	u8 coef[2][4][2][128];
-+	u8 uv_mode_0_2[3][9];
-+	u8 padding1[5];
-+	u8 uv_mode_3_5[3][9];
-+	u8 padding2[5];
-+	u8 uv_mode_6_8[3][9];
-+	u8 padding3[5];
-+	u8 uv_mode_9[9];
-+	u8 padding4[7];
-+	u8 padding5[16];
-+	struct {
-+		u8 joint[3];
-+		u8 sign[2];
-+		u8 class[2][10];
-+		u8 class0_bit[2];
-+		u8 bits[2][10];
-+		u8 class0_fr[2][2][3];
-+		u8 fr[2][3];
-+		u8 class0_hp[2];
-+		u8 hp[2];
-+	} mv;
-+};
-+
-+struct rkvdec_vp9_probs {
-+	u8 partition[16][3];
-+	u8 pred[3];
-+	u8 tree[7];
-+	u8 skip[3];
-+	u8 tx32[2][3];
-+	u8 tx16[2][2];
-+	u8 tx8[2][1];
-+	u8 is_inter[4];
-+	/* 128 bit alignment */
-+	u8 padding0[3];
-+	union {
-+		struct rkvdec_vp9_inter_frame_probs inter;
-+		struct rkvdec_vp9_intra_only_frame_probs intra_only;
-+	};
-+};
-+
-+/* Data structure describing auxiliary buffer format. */
-+struct rkvdec_vp9_priv_tbl {
-+	struct rkvdec_vp9_probs probs;
-+	u8 segmap[2][RKVDEC_VP9_MAX_SEGMAP_SIZE];
-+};
-+
-+struct rkvdec_vp9_refs_counts {
-+	u32 eob[2];
-+	u32 coeff[3];
-+};
-+
-+struct rkvdec_vp9_inter_frame_symbol_counts {
-+	u32 partition[16][4];
-+	u32 skip[3][2];
-+	u32 inter[4][2];
-+	u32 tx32p[2][4];
-+	u32 tx16p[2][4];
-+	u32 tx8p[2][2];
-+	u32 y_mode[4][10];
-+	u32 uv_mode[10][10];
-+	u32 comp[5][2];
-+	u32 comp_ref[5][2];
-+	u32 single_ref[5][2][2];
-+	u32 mv_mode[7][4];
-+	u32 filter[4][3];
-+	u32 mv_joint[4];
-+	u32 sign[2][2];
-+	/* add 1 element for align */
-+	u32 classes[2][11 + 1];
-+	u32 class0[2][2];
-+	u32 bits[2][10][2];
-+	u32 class0_fp[2][2][4];
-+	u32 fp[2][4];
-+	u32 class0_hp[2][2];
-+	u32 hp[2][2];
-+	struct rkvdec_vp9_refs_counts ref_cnt[2][4][2][6][6];
-+};
-+
-+struct rkvdec_vp9_intra_frame_symbol_counts {
-+	u32 partition[4][4][4];
-+	u32 skip[3][2];
-+	u32 intra[4][2];
-+	u32 tx32p[2][4];
-+	u32 tx16p[2][4];
-+	u32 tx8p[2][2];
-+	struct rkvdec_vp9_refs_counts ref_cnt[2][4][2][6][6];
-+};
-+
-+struct rkvdec_vp9_run {
-+	struct rkvdec_run base;
-+	const struct v4l2_ctrl_vp9_frame_decode_params *decode_params;
-+};
-+
-+struct rkvdec_vp9_frame_info {
-+	u32 valid : 1;
-+	u32 segmapid : 1;
-+	u32 frame_context_idx : 2;
-+	u32 reference_mode : 2;
-+	u32 tx_mode : 3;
-+	u32 interpolation_filter : 3;
-+	u32 flags;
-+	u64 timestamp;
-+	struct v4l2_vp9_segmentation seg;
-+	struct v4l2_vp9_loop_filter lf;
-+};
-+
-+struct rkvdec_vp9_ctx {
-+	struct rkvdec_aux_buf priv_tbl;
-+	struct rkvdec_aux_buf count_tbl;
-+	struct v4l2_ctrl_vp9_frame_ctx frame_context;
-+	struct rkvdec_vp9_frame_info cur;
-+	struct rkvdec_vp9_frame_info last;
-+};
-+
-+static u32 rkvdec_fastdiv(u32 dividend, u16 divisor)
-+{
-+#define DIV_INV(d)	((u32)(((1ULL << 32) + ((d) - 1)) / (d)))
-+#define DIVS_INV(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9)	\
-+	DIV_INV(d0), DIV_INV(d1), DIV_INV(d2), DIV_INV(d3),	\
-+	DIV_INV(d4), DIV_INV(d5), DIV_INV(d6), DIV_INV(d7),	\
-+	DIV_INV(d8), DIV_INV(d9)
-+
-+	static const u32 inv[] = {
-+		DIV_INV(2), DIV_INV(3), DIV_INV(4), DIV_INV(5),
-+		DIV_INV(6), DIV_INV(7), DIV_INV(8), DIV_INV(9),
-+		DIVS_INV(10, 11, 12, 13, 14, 15, 16, 17, 18, 19),
-+		DIVS_INV(20, 21, 22, 23, 24, 25, 26, 27, 28, 29),
-+		DIVS_INV(30, 31, 32, 33, 34, 35, 36, 37, 38, 39),
-+		DIVS_INV(40, 41, 42, 43, 44, 45, 46, 47, 48, 49),
-+		DIVS_INV(50, 51, 52, 53, 54, 55, 56, 57, 58, 59),
-+		DIVS_INV(60, 61, 62, 63, 64, 65, 66, 67, 68, 69),
-+		DIVS_INV(70, 71, 72, 73, 74, 75, 76, 77, 78, 79),
-+		DIVS_INV(80, 81, 82, 83, 84, 85, 86, 87, 88, 89),
-+		DIVS_INV(90, 91, 92, 93, 94, 95, 96, 97, 98, 99),
-+		DIVS_INV(100, 101, 102, 103, 104, 105, 106, 107, 108, 109),
-+		DIVS_INV(110, 111, 112, 113, 114, 115, 116, 117, 118, 119),
-+		DIVS_INV(120, 121, 122, 123, 124, 125, 126, 127, 128, 129),
-+		DIVS_INV(130, 131, 132, 133, 134, 135, 136, 137, 138, 139),
-+		DIVS_INV(140, 141, 142, 143, 144, 145, 146, 147, 148, 149),
-+		DIVS_INV(150, 151, 152, 153, 154, 155, 156, 157, 158, 159),
-+		DIVS_INV(160, 161, 162, 163, 164, 165, 166, 167, 168, 169),
-+		DIVS_INV(170, 171, 172, 173, 174, 175, 176, 177, 178, 179),
-+		DIVS_INV(180, 181, 182, 183, 184, 185, 186, 187, 188, 189),
-+		DIVS_INV(190, 191, 192, 193, 194, 195, 196, 197, 198, 199),
-+		DIVS_INV(200, 201, 202, 203, 204, 205, 206, 207, 208, 209),
-+		DIVS_INV(210, 211, 212, 213, 214, 215, 216, 217, 218, 219),
-+		DIVS_INV(220, 221, 222, 223, 224, 225, 226, 227, 228, 229),
-+		DIVS_INV(230, 231, 232, 233, 234, 235, 236, 237, 238, 239),
-+		DIVS_INV(240, 241, 242, 243, 244, 245, 246, 247, 248, 249),
-+		DIV_INV(250), DIV_INV(251), DIV_INV(252), DIV_INV(253),
-+		DIV_INV(254), DIV_INV(255), DIV_INV(256),
-+	};
-+
-+	if (divisor == 0)
-+		return 0;
-+	else if (divisor == 1)
-+		return dividend;
-+
-+	if (WARN_ON(divisor - 2 >= ARRAY_SIZE(inv)))
-+		return dividend;
-+
-+	return ((u64)dividend * inv[divisor - 2]) >> 32;
-+}
-+
-+static const u8 vp9_kf_y_mode_prob[10][10][9] = {
-+	{
-+		/* above = dc */
-+		{ 137,  30,  42, 148, 151, 207,  70,  52,  91 },/*left = dc  */
-+		{  92,  45, 102, 136, 116, 180,  74,  90, 100 },/*left = v   */
-+		{  73,  32,  19, 187, 222, 215,  46,  34, 100 },/*left = h   */
-+		{  91,  30,  32, 116, 121, 186,  93,  86,  94 },/*left = d45 */
-+		{  72,  35,  36, 149,  68, 206,  68,  63, 105 },/*left = d135*/
-+		{  73,  31,  28, 138,  57, 124,  55, 122, 151 },/*left = d117*/
-+		{  67,  23,  21, 140, 126, 197,  40,  37, 171 },/*left = d153*/
-+		{  86,  27,  28, 128, 154, 212,  45,  43,  53 },/*left = d207*/
-+		{  74,  32,  27, 107,  86, 160,  63, 134, 102 },/*left = d63 */
-+		{  59,  67,  44, 140, 161, 202,  78,  67, 119 } /*left = tm  */
-+	}, {  /* above = v */
-+		{  63,  36, 126, 146, 123, 158,  60,  90,  96 },/*left = dc  */
-+		{  43,  46, 168, 134, 107, 128,  69, 142,  92 },/*left = v   */
-+		{  44,  29,  68, 159, 201, 177,  50,  57,  77 },/*left = h   */
-+		{  58,  38,  76, 114,  97, 172,  78, 133,  92 },/*left = d45 */
-+		{  46,  41,  76, 140,  63, 184,  69, 112,  57 },/*left = d135*/
-+		{  38,  32,  85, 140,  46, 112,  54, 151, 133 },/*left = d117*/
-+		{  39,  27,  61, 131, 110, 175,  44,  75, 136 },/*left = d153*/
-+		{  52,  30,  74, 113, 130, 175,  51,  64,  58 },/*left = d207*/
-+		{  47,  35,  80, 100,  74, 143,  64, 163,  74 },/*left = d63 */
-+		{  36,  61, 116, 114, 128, 162,  80, 125,  82 } /*left = tm  */
-+	}, {  /* above = h */
-+		{  82,  26,  26, 171, 208, 204,  44,  32, 105 },/*left = dc  */
-+		{  55,  44,  68, 166, 179, 192,  57,  57, 108 },/*left = v   */
-+		{  42,  26,  11, 199, 241, 228,  23,  15,  85 },/*left = h   */
-+		{  68,  42,  19, 131, 160, 199,  55,  52,  83 },/*left = d45 */
-+		{  58,  50,  25, 139, 115, 232,  39,  52, 118 },/*left = d135*/
-+		{  50,  35,  33, 153, 104, 162,  64,  59, 131 },/*left = d117*/
-+		{  44,  24,  16, 150, 177, 202,  33,  19, 156 },/*left = d153*/
-+		{  55,  27,  12, 153, 203, 218,  26,  27,  49 },/*left = d207*/
-+		{  53,  49,  21, 110, 116, 168,  59,  80,  76 },/*left = d63 */
-+		{  38,  72,  19, 168, 203, 212,  50,  50, 107 } /*left = tm  */
-+	}, {  /* above = d45 */
-+		{ 103,  26,  36, 129, 132, 201,  83,  80,  93 },/*left = dc  */
-+		{  59,  38,  83, 112, 103, 162,  98, 136,  90 },/*left = v   */
-+		{  62,  30,  23, 158, 200, 207,  59,  57,  50 },/*left = h   */
-+		{  67,  30,  29,  84,  86, 191, 102,  91,  59 },/*left = d45 */
-+		{  60,  32,  33, 112,  71, 220,  64,  89, 104 },/*left = d135*/
-+		{  53,  26,  34, 130,  56, 149,  84, 120, 103 },/*left = d117*/
-+		{  53,  21,  23, 133, 109, 210,  56,  77, 172 },/*left = d153*/
-+		{  77,  19,  29, 112, 142, 228,  55,  66,  36 },/*left = d207*/
-+		{  61,  29,  29,  93,  97, 165,  83, 175, 162 },/*left = d63 */
-+		{  47,  47,  43, 114, 137, 181, 100,  99,  95 } /*left = tm  */
-+	}, {  /* above = d135 */
-+		{  69,  23,  29, 128,  83, 199,  46,  44, 101 },/*left = dc  */
-+		{  53,  40,  55, 139,  69, 183,  61,  80, 110 },/*left = v   */
-+		{  40,  29,  19, 161, 180, 207,  43,  24,  91 },/*left = h   */
-+		{  60,  34,  19, 105,  61, 198,  53,  64,  89 },/*left = d45 */
-+		{  52,  31,  22, 158,  40, 209,  58,  62,  89 },/*left = d135*/
-+		{  44,  31,  29, 147,  46, 158,  56, 102, 198 },/*left = d117*/
-+		{  35,  19,  12, 135,  87, 209,  41,  45, 167 },/*left = d153*/
-+		{  55,  25,  21, 118,  95, 215,  38,  39,  66 },/*left = d207*/
-+		{  51,  38,  25, 113,  58, 164,  70,  93,  97 },/*left = d63 */
-+		{  47,  54,  34, 146, 108, 203,  72, 103, 151 } /*left = tm  */
-+	}, {  /* above = d117 */
-+		{  64,  19,  37, 156,  66, 138,  49,  95, 133 },/*left = dc  */
-+		{  46,  27,  80, 150,  55, 124,  55, 121, 135 },/*left = v   */
-+		{  36,  23,  27, 165, 149, 166,  54,  64, 118 },/*left = h   */
-+		{  53,  21,  36, 131,  63, 163,  60, 109,  81 },/*left = d45 */
-+		{  40,  26,  35, 154,  40, 185,  51,  97, 123 },/*left = d135*/
-+		{  35,  19,  34, 179,  19,  97,  48, 129, 124 },/*left = d117*/
-+		{  36,  20,  26, 136,  62, 164,  33,  77, 154 },/*left = d153*/
-+		{  45,  18,  32, 130,  90, 157,  40,  79,  91 },/*left = d207*/
-+		{  45,  26,  28, 129,  45, 129,  49, 147, 123 },/*left = d63 */
-+		{  38,  44,  51, 136,  74, 162,  57,  97, 121 } /*left = tm  */
-+	}, {  /* above = d153 */
-+		{  75,  17,  22, 136, 138, 185,  32,  34, 166 },/*left = dc  */
-+		{  56,  39,  58, 133, 117, 173,  48,  53, 187 },/*left = v   */
-+		{  35,  21,  12, 161, 212, 207,  20,  23, 145 },/*left = h   */
-+		{  56,  29,  19, 117, 109, 181,  55,  68, 112 },/*left = d45 */
-+		{  47,  29,  17, 153,  64, 220,  59,  51, 114 },/*left = d135*/
-+		{  46,  16,  24, 136,  76, 147,  41,  64, 172 },/*left = d117*/
-+		{  34,  17,  11, 108, 152, 187,  13,  15, 209 },/*left = d153*/
-+		{  51,  24,  14, 115, 133, 209,  32,  26, 104 },/*left = d207*/
-+		{  55,  30,  18, 122,  79, 179,  44,  88, 116 },/*left = d63 */
-+		{  37,  49,  25, 129, 168, 164,  41,  54, 148 } /*left = tm  */
-+	}, {  /* above = d207 */
-+		{  82,  22,  32, 127, 143, 213,  39,  41,  70 },/*left = dc  */
-+		{  62,  44,  61, 123, 105, 189,  48,  57,  64 },/*left = v   */
-+		{  47,  25,  17, 175, 222, 220,  24,  30,  86 },/*left = h   */
-+		{  68,  36,  17, 106, 102, 206,  59,  74,  74 },/*left = d45 */
-+		{  57,  39,  23, 151,  68, 216,  55,  63,  58 },/*left = d135*/
-+		{  49,  30,  35, 141,  70, 168,  82,  40, 115 },/*left = d117*/
-+		{  51,  25,  15, 136, 129, 202,  38,  35, 139 },/*left = d153*/
-+		{  68,  26,  16, 111, 141, 215,  29,  28,  28 },/*left = d207*/
-+		{  59,  39,  19, 114,  75, 180,  77, 104,  42 },/*left = d63 */
-+		{  40,  61,  26, 126, 152, 206,  61,  59,  93 } /*left = tm  */
-+	}, {  /* above = d63 */
-+		{  78,  23,  39, 111, 117, 170,  74, 124,  94 },/*left = dc  */
-+		{  48,  34,  86, 101,  92, 146,  78, 179, 134 },/*left = v   */
-+		{  47,  22,  24, 138, 187, 178,  68,  69,  59 },/*left = h   */
-+		{  56,  25,  33, 105, 112, 187,  95, 177, 129 },/*left = d45 */
-+		{  48,  31,  27, 114,  63, 183,  82, 116,  56 },/*left = d135*/
-+		{  43,  28,  37, 121,  63, 123,  61, 192, 169 },/*left = d117*/
-+		{  42,  17,  24, 109,  97, 177,  56,  76, 122 },/*left = d153*/
-+		{  58,  18,  28, 105, 139, 182,  70,  92,  63 },/*left = d207*/
-+		{  46,  23,  32,  74,  86, 150,  67, 183,  88 },/*left = d63 */
-+		{  36,  38,  48,  92, 122, 165,  88, 137,  91 } /*left = tm  */
-+	}, {  /* above = tm */
-+		{  65,  70,  60, 155, 159, 199,  61,  60,  81 },/*left = dc  */
-+		{  44,  78, 115, 132, 119, 173,  71, 112,  93 },/*left = v   */
-+		{  39,  38,  21, 184, 227, 206,  42,  32,  64 },/*left = h   */
-+		{  58,  47,  36, 124, 137, 193,  80,  82,  78 },/*left = d45 */
-+		{  49,  50,  35, 144,  95, 205,  63,  78,  59 },/*left = d135*/
-+		{  41,  53,  52, 148,  71, 142,  65, 128,  51 },/*left = d117*/
-+		{  40,  36,  28, 143, 143, 202,  40,  55, 137 },/*left = d153*/
-+		{  52,  34,  29, 129, 183, 227,  42,  35,  43 },/*left = d207*/
-+		{  42,  44,  44, 104, 105, 164,  64, 130,  80 },/*left = d63 */
-+		{  43,  81,  53, 140, 169, 204,  68,  84,  72 } /*left = tm  */
-+	}
-+};
-+
-+static const u8 kf_partition_probs[16][3] = {
-+	/* 8x8 -> 4x4 */
-+	{ 158,  97,  94 },	/* a/l both not split   */
-+	{  93,  24,  99 },	/* a split, l not split */
-+	{  85, 119,  44 },	/* l split, a not split */
-+	{  62,  59,  67 },	/* a/l both split       */
-+	/* 16x16 -> 8x8 */
-+	{ 149,  53,  53 },	/* a/l both not split   */
-+	{  94,  20,  48 },	/* a split, l not split */
-+	{  83,  53,  24 },	/* l split, a not split */
-+	{  52,  18,  18 },	/* a/l both split       */
-+	/* 32x32 -> 16x16 */
-+	{ 150,  40,  39 },	/* a/l both not split   */
-+	{  78,  12,  26 },	/* a split, l not split */
-+	{  67,  33,  11 },	/* l split, a not split */
-+	{  24,   7,   5 },	/* a/l both split       */
-+	/* 64x64 -> 32x32 */
-+	{ 174,  35,  49 },	/* a/l both not split   */
-+	{  68,  11,  27 },	/* a split, l not split */
-+	{  57,  15,   9 },	/* l split, a not split */
-+	{  12,   3,   3 },	/* a/l both split       */
-+};
-+
-+static const u8 kf_uv_mode_prob[10][9] = {
-+	{ 144,  11,  54, 157, 195, 130,  46,  58, 108 },  /* y = dc   */
-+	{ 118,  15, 123, 148, 131, 101,  44,  93, 131 },  /* y = v    */
-+	{ 113,  12,  23, 188, 226, 142,  26,  32, 125 },  /* y = h    */
-+	{ 120,  11,  50, 123, 163, 135,  64,  77, 103 },  /* y = d45  */
-+	{ 113,   9,  36, 155, 111, 157,  32,  44, 161 },  /* y = d135 */
-+	{ 116,   9,  55, 176,  76,  96,  37,  61, 149 },  /* y = d117 */
-+	{ 115,   9,  28, 141, 161, 167,  21,  25, 193 },  /* y = d153 */
-+	{ 120,  12,  32, 145, 195, 142,  32,  38,  86 },  /* y = d207 */
-+	{ 116,  12,  64, 120, 140, 125,  49, 115, 121 },  /* y = d63  */
-+	{ 102,  19,  66, 162, 182, 122,  35,  59, 128 }   /* y = tm   */
-+};
-+
-+static void write_coeff_plane(const u8 coef[6][6][3], u8 *coeff_plane)
-+{
-+	unsigned int idx = 0;
-+	u8 byte_count = 0, p;
-+	s32 k, m, n;
-+
-+	for (k = 0; k < 6; k++) {
-+		for (m = 0; m < 6; m++) {
-+			for (n = 0; n < 3; n++) {
-+				p = coef[k][m][n];
-+				coeff_plane[idx++] = p;
-+				byte_count++;
-+				if (byte_count == 27) {
-+					idx += 5;
-+					byte_count = 0;
-+				}
-+			}
-+		}
-+	}
-+}
-+
-+static void init_intra_only_probs(struct rkvdec_ctx *ctx,
-+				  const struct rkvdec_vp9_run *run)
-+{
-+	const struct v4l2_ctrl_vp9_frame_decode_params *dec_params;
-+	struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;
-+	struct rkvdec_vp9_priv_tbl *tbl = vp9_ctx->priv_tbl.cpu;
-+	struct rkvdec_vp9_intra_only_frame_probs *rkprobs;
-+	const struct v4l2_vp9_probabilities *probs;
-+	unsigned int i, j, k, m;
-+
-+	rkprobs = &tbl->probs.intra_only;
-+	dec_params = run->decode_params;
-+	probs = &dec_params->probs;
-+
-+	/*
-+	 * intra only 149 x 128 bits ,aligned to 152 x 128 bits coeff related
-+	 * prob 64 x 128 bits
-+	 */
-+	for (i = 0; i < ARRAY_SIZE(probs->coef); i++) {
-+		for (j = 0; j < ARRAY_SIZE(probs->coef[0]); j++)
-+			write_coeff_plane(probs->coef[i][j][0],
-+					  rkprobs->coef_intra[i][j]);
-+	}
-+
-+	/* intra mode prob  80 x 128 bits */
-+	for (i = 0; i < ARRAY_SIZE(vp9_kf_y_mode_prob); i++) {
-+		u32 byte_count = 0;
-+		int idx = 0;
-+
-+		/* vp9_kf_y_mode_prob */
-+		for (j = 0; j < ARRAY_SIZE(vp9_kf_y_mode_prob[0]); j++) {
-+			for (k = 0; k < ARRAY_SIZE(vp9_kf_y_mode_prob[0][0]);
-+			     k++) {
-+				u8 val = vp9_kf_y_mode_prob[i][j][k];
-+
-+				rkprobs->intra_mode[i].y_mode[idx++] = val;
-+				byte_count++;
-+				if (byte_count == 27) {
-+					byte_count = 0;
-+					idx += 5;
-+				}
-+			}
-+		}
-+
-+		idx = 0;
-+		if (i < 4) {
-+			for (m = 0; m < (i < 3 ? 23 : 21); m++) {
-+				const u8 *ptr = (const u8 *)kf_uv_mode_prob;
-+
-+				rkprobs->intra_mode[i].uv_mode[idx++] = ptr[i * 23 + m];
-+			}
-+		}
-+	}
-+}
-+
-+static void init_inter_probs(struct rkvdec_ctx *ctx,
-+			     const struct rkvdec_vp9_run *run)
-+{
-+	const struct v4l2_ctrl_vp9_frame_decode_params *dec_params;
-+	struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;
-+	struct rkvdec_vp9_priv_tbl *tbl = vp9_ctx->priv_tbl.cpu;
-+	struct rkvdec_vp9_inter_frame_probs *rkprobs;
-+	const struct v4l2_vp9_probabilities *probs;
-+	unsigned int i, j, k;
-+
-+	rkprobs = &tbl->probs.inter;
-+	dec_params = run->decode_params;
-+	probs = &dec_params->probs;
-+
-+	/*
-+	 * inter probs
-+	 * 151 x 128 bits, aligned to 152 x 128 bits
-+	 * inter only
-+	 * intra_y_mode & inter_block info 6 x 128 bits
-+	 */
-+
-+	memcpy(rkprobs->y_mode, probs->y_mode, sizeof(rkprobs->y_mode));
-+	memcpy(rkprobs->comp_mode, probs->comp_mode,
-+	       sizeof(rkprobs->comp_mode));
-+	memcpy(rkprobs->comp_ref, probs->comp_ref,
-+	       sizeof(rkprobs->comp_ref));
-+	memcpy(rkprobs->single_ref, probs->single_ref,
-+	       sizeof(rkprobs->single_ref));
-+	memcpy(rkprobs->inter_mode, probs->inter_mode,
-+	       sizeof(rkprobs->inter_mode));
-+	memcpy(rkprobs->interp_filter, probs->interp_filter,
-+	       sizeof(rkprobs->interp_filter));
-+
-+	/* 128 x 128 bits coeff related */
-+	for (i = 0; i < ARRAY_SIZE(probs->coef); i++) {
-+		for (j = 0; j < ARRAY_SIZE(probs->coef[0]); j++) {
-+			for (k = 0; k < ARRAY_SIZE(probs->coef[0][0]); k++)
-+				write_coeff_plane(probs->coef[i][j][k],
-+						  rkprobs->coef[k][i][j]);
-+		}
-+	}
-+
-+	/* intra uv mode 6 x 128 */
-+	memcpy(rkprobs->uv_mode_0_2, &probs->uv_mode[0],
-+	       sizeof(rkprobs->uv_mode_0_2));
-+	memcpy(rkprobs->uv_mode_3_5, &probs->uv_mode[3],
-+	       sizeof(rkprobs->uv_mode_3_5));
-+	memcpy(rkprobs->uv_mode_6_8, &probs->uv_mode[6],
-+	       sizeof(rkprobs->uv_mode_6_8));
-+	memcpy(rkprobs->uv_mode_9, &probs->uv_mode[9],
-+	       sizeof(rkprobs->uv_mode_9));
-+
-+	/* mv related 6 x 128 */
-+	memcpy(rkprobs->mv.joint, probs->mv.joint,
-+	       sizeof(rkprobs->mv.joint));
-+	memcpy(rkprobs->mv.sign, probs->mv.sign,
-+	       sizeof(rkprobs->mv.sign));
-+	memcpy(rkprobs->mv.class, probs->mv.class,
-+	       sizeof(rkprobs->mv.class));
-+	memcpy(rkprobs->mv.class0_bit, probs->mv.class0_bit,
-+	       sizeof(rkprobs->mv.class0_bit));
-+	memcpy(rkprobs->mv.bits, probs->mv.bits,
-+	       sizeof(rkprobs->mv.bits));
-+	memcpy(rkprobs->mv.class0_fr, probs->mv.class0_fr,
-+	       sizeof(rkprobs->mv.class0_fr));
-+	memcpy(rkprobs->mv.fr, probs->mv.fr,
-+	       sizeof(rkprobs->mv.fr));
-+	memcpy(rkprobs->mv.class0_hp, probs->mv.class0_hp,
-+	       sizeof(rkprobs->mv.class0_hp));
-+	memcpy(rkprobs->mv.hp, probs->mv.hp,
-+	       sizeof(rkprobs->mv.hp));
-+}
-+
-+static void init_probs(struct rkvdec_ctx *ctx,
-+		       const struct rkvdec_vp9_run *run)
-+{
-+	const struct v4l2_ctrl_vp9_frame_decode_params *dec_params;
-+	struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;
-+	struct rkvdec_vp9_priv_tbl *tbl = vp9_ctx->priv_tbl.cpu;
-+	struct rkvdec_vp9_probs *rkprobs = &tbl->probs;
-+	const struct v4l2_vp9_segmentation *seg;
-+	const struct v4l2_vp9_probabilities *probs;
-+	bool intra_only;
-+
-+	dec_params = run->decode_params;
-+	probs = &dec_params->probs;
-+	seg = &dec_params->seg;
-+
-+	memset(rkprobs, 0, sizeof(*rkprobs));
-+
-+	intra_only = !!(dec_params->flags &
-+			(V4L2_VP9_FRAME_FLAG_KEY_FRAME |
-+			 V4L2_VP9_FRAME_FLAG_INTRA_ONLY));
-+
-+	/* sb info  5 x 128 bit */
-+	memcpy(rkprobs->partition,
-+	       intra_only ? kf_partition_probs : probs->partition,
-+	       sizeof(rkprobs->partition));
-+
-+	memcpy(rkprobs->pred, seg->pred_probs, sizeof(rkprobs->pred));
-+	memcpy(rkprobs->tree, seg->tree_probs, sizeof(rkprobs->tree));
-+	memcpy(rkprobs->skip, probs->skip, sizeof(rkprobs->skip));
-+	memcpy(rkprobs->tx32, probs->tx32, sizeof(rkprobs->tx32));
-+	memcpy(rkprobs->tx16, probs->tx16, sizeof(rkprobs->tx16));
-+	memcpy(rkprobs->tx8, probs->tx8, sizeof(rkprobs->tx8));
-+	memcpy(rkprobs->is_inter, probs->is_inter, sizeof(rkprobs->is_inter));
-+
-+	if (intra_only)
-+		init_intra_only_probs(ctx, run);
-+	else
-+		init_inter_probs(ctx, run);
-+}
-+
-+struct vp9d_ref_config {
-+	u32 reg_frm_size;
-+	u32 reg_hor_stride;
-+	u32 reg_y_stride;
-+	u32 reg_yuv_stride;
-+	u32 reg_ref_base;
-+};
-+
-+static struct vp9d_ref_config ref_config[3] = {
-+	{
-+		.reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(0),
-+		.reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(0),
-+		.reg_y_stride = RKVDEC_VP9_LAST_FRAME_YSTRIDE,
-+		.reg_yuv_stride = RKVDEC_VP9_LAST_FRAME_YUVSTRIDE,
-+		.reg_ref_base = RKVDEC_REG_VP9_LAST_FRAME_BASE,
-+	},
-+	{
-+		.reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(1),
-+		.reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(1),
-+		.reg_y_stride = RKVDEC_VP9_GOLDEN_FRAME_YSTRIDE,
-+		.reg_yuv_stride = 0,
-+		.reg_ref_base = RKVDEC_REG_VP9_GOLDEN_FRAME_BASE,
-+	},
-+	{
-+		.reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(2),
-+		.reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(2),
-+		.reg_y_stride = RKVDEC_VP9_ALTREF_FRAME_YSTRIDE,
-+		.reg_yuv_stride = 0,
-+		.reg_ref_base = RKVDEC_REG_VP9_ALTREF_FRAME_BASE,
-+	}
-+};
-+
-+static struct rkvdec_decoded_buffer *
-+get_ref_buf(struct rkvdec_ctx *ctx, struct vb2_v4l2_buffer *dst, u64 timestamp)
-+{
-+	struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
-+	struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q;
-+	int buf_idx;
-+
-+	/*
-+	 * If a ref is unused or invalid, address of current destination
-+	 * buffer is returned.
-+	 */
-+	buf_idx = vb2_find_timestamp(cap_q, timestamp, 0);
-+	if (buf_idx < 0)
-+		return vb2_to_rkvdec_decoded_buf(&dst->vb2_buf);
-+
-+	return vb2_to_rkvdec_decoded_buf(vb2_get_buffer(cap_q, buf_idx));
-+}
-+
-+static dma_addr_t get_mv_base_addr(struct rkvdec_decoded_buffer *buf)
-+{
-+	u32 aligned_pitch, aligned_height, yuv_len;
-+
-+	aligned_height = round_up(buf->vp9.height, 64);
-+	aligned_pitch = round_up(buf->vp9.width * buf->vp9.bit_depth, 512) / 8;
-+	yuv_len = (aligned_height * aligned_pitch * 3) / 2;
-+
-+	return vb2_dma_contig_plane_dma_addr(&buf->base.vb.vb2_buf, 0) +
-+	       yuv_len;
-+}
-+
-+static void
-+config_ref_registers(struct rkvdec_ctx *ctx,
-+		     const struct rkvdec_vp9_run *run,
-+		     struct rkvdec_decoded_buffer **ref_bufs,
-+		     enum v4l2_vp9_ref_id id)
-+{
-+	u32 aligned_pitch, aligned_height, y_len, yuv_len;
-+	struct rkvdec_decoded_buffer *buf = ref_bufs[id];
-+	struct rkvdec_dev *rkvdec = ctx->dev;
-+
-+	aligned_height = round_up(buf->vp9.height, 64);
-+	writel_relaxed(RKVDEC_VP9_FRAMEWIDTH(buf->vp9.width) |
-+		       RKVDEC_VP9_FRAMEHEIGHT(buf->vp9.height),
-+		       rkvdec->regs + ref_config[id].reg_frm_size);
-+
-+	writel_relaxed(vb2_dma_contig_plane_dma_addr(&buf->base.vb.vb2_buf, 0),
-+		       rkvdec->regs + ref_config[id].reg_ref_base);
-+
-+	if (&buf->base.vb == run->base.bufs.dst)
-+		return;
-+
-+	aligned_pitch = round_up(buf->vp9.width * buf->vp9.bit_depth, 512) / 8;
-+	y_len = aligned_height * aligned_pitch;
-+	yuv_len = (y_len * 3) / 2;
-+
-+	writel_relaxed(RKVDEC_HOR_Y_VIRSTRIDE(aligned_pitch / 16) |
-+		       RKVDEC_HOR_UV_VIRSTRIDE(aligned_pitch / 16),
-+		       rkvdec->regs + ref_config[id].reg_hor_stride);
-+	writel_relaxed(RKVDEC_VP9_REF_YSTRIDE(y_len / 16),
-+		       rkvdec->regs + ref_config[id].reg_y_stride);
-+
-+	if (!ref_config[id].reg_yuv_stride)
-+		return;
-+
-+	writel_relaxed(RKVDEC_VP9_REF_YUVSTRIDE(yuv_len / 16),
-+		       rkvdec->regs + ref_config[id].reg_yuv_stride);
-+}
-+
-+static bool seg_featured_enabled(const struct v4l2_vp9_segmentation *seg,
-+				 enum v4l2_vp9_segment_feature feature,
-+				 unsigned int segid)
-+{
-+	u8 mask = V4L2_VP9_SEGMENT_FEATURE_ENABLED(feature);
-+
-+	return !!(seg->feature_enabled[segid] & mask);
-+}
-+
-+static void
-+config_seg_registers(struct rkvdec_ctx *ctx,
-+		     unsigned int segid)
-+{
-+	struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;
-+	const struct v4l2_vp9_segmentation *seg;
-+	struct rkvdec_dev *rkvdec = ctx->dev;
-+	s16 feature_val;
-+	u8 feature_id;
-+	u32 val = 0;
-+
-+	seg = vp9_ctx->last.valid ? &vp9_ctx->last.seg : &vp9_ctx->cur.seg;
-+	feature_id = V4L2_VP9_SEGMENT_FEATURE_QP_DELTA;
-+	if (seg_featured_enabled(seg, feature_id, segid)) {
-+		feature_val = seg->feature_data[segid][feature_id];
-+		val |= RKVDEC_SEGID_FRAME_QP_DELTA_EN(1) |
-+		       RKVDEC_SEGID_FRAME_QP_DELTA(feature_val);
-+	}
-+
-+	feature_id = V4L2_VP9_SEGMENT_FEATURE_LF;
-+	if (seg_featured_enabled(seg, feature_id, segid)) {
-+		feature_val = seg->feature_data[segid][feature_id];
-+		val |= RKVDEC_SEGID_FRAME_LOOPFILTER_VALUE_EN(1) |
-+		       RKVDEC_SEGID_FRAME_LOOPFILTER_VALUE(feature_val);
-+	}
-+
-+	feature_id = V4L2_VP9_SEGMENT_FEATURE_REF_FRAME;
-+	if (seg_featured_enabled(seg, feature_id, segid)) {
-+		feature_val = seg->feature_data[segid][feature_id];
-+		val |= RKVDEC_SEGID_REFERINFO_EN(1) |
-+		       RKVDEC_SEGID_REFERINFO(feature_val);
-+	}
-+
-+	feature_id = V4L2_VP9_SEGMENT_FEATURE_SKIP;
-+	if (seg_featured_enabled(seg, feature_id, segid))
-+		val |= RKVDEC_SEGID_FRAME_SKIP_EN(1);
-+
-+	if (!segid &&
-+	    (seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE))
-+		val |= RKVDEC_SEGID_ABS_DELTA(1);
-+
-+	writel_relaxed(val, rkvdec->regs + RKVDEC_VP9_SEGID_GRP(segid));
-+}
-+
-+static void
-+update_dec_buf_info(struct rkvdec_decoded_buffer *buf,
-+		    const struct v4l2_ctrl_vp9_frame_decode_params *dec_params)
-+{
-+	buf->vp9.width = dec_params->frame_width_minus_1 + 1;
-+	buf->vp9.height = dec_params->frame_height_minus_1 + 1;
-+	buf->vp9.bit_depth = dec_params->bit_depth;
-+}
-+
-+static void
-+update_ctx_cur_info(struct rkvdec_vp9_ctx *vp9_ctx,
-+		struct rkvdec_decoded_buffer *buf,
-+		const struct v4l2_ctrl_vp9_frame_decode_params *dec_params)
-+{
-+	vp9_ctx->cur.valid = true;
-+	vp9_ctx->cur.frame_context_idx = dec_params->frame_context_idx;
-+	vp9_ctx->cur.reference_mode = dec_params->reference_mode;
-+	vp9_ctx->cur.tx_mode = dec_params->tx_mode;
-+	vp9_ctx->cur.interpolation_filter = dec_params->interpolation_filter;
-+	vp9_ctx->cur.flags = dec_params->flags;
-+	vp9_ctx->cur.timestamp = buf->base.vb.vb2_buf.timestamp;
-+	vp9_ctx->cur.seg = dec_params->seg;
-+	vp9_ctx->cur.lf = dec_params->lf;
-+}
-+
-+static void
-+update_ctx_last_info(struct rkvdec_vp9_ctx *vp9_ctx)
-+{
-+	vp9_ctx->last = vp9_ctx->cur;
-+}
-+
-+static void config_registers(struct rkvdec_ctx *ctx,
-+			     const struct rkvdec_vp9_run *run)
-+{
-+	u32 y_len, uv_len, yuv_len, bit_depth, aligned_height, aligned_pitch;
-+	const struct v4l2_ctrl_vp9_frame_decode_params *dec_params;
-+	struct rkvdec_decoded_buffer *ref_bufs[V4L2_REF_ID_CNT];
-+	struct rkvdec_decoded_buffer *dst, *last, *mv_ref;
-+	struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;
-+	u32 val, stream_len, last_frame_info = 0;
-+	const struct v4l2_vp9_segmentation *seg;
-+	struct rkvdec_dev *rkvdec = ctx->dev;
-+	dma_addr_t addr;
-+	bool intra_only;
-+	unsigned int i;
-+
-+	dec_params = run->decode_params;
-+	dst = vb2_to_rkvdec_decoded_buf(&run->base.bufs.dst->vb2_buf);
-+	for (i = 0; i < ARRAY_SIZE(ref_bufs); i++)
-+		ref_bufs[i] = get_ref_buf(ctx, &dst->base.vb,
-+					  dec_params->refs[i]);
-+
-+	if (vp9_ctx->last.valid)
-+		last = get_ref_buf(ctx, &dst->base.vb, vp9_ctx->last.timestamp);
-+	else
-+		last = dst;
-+
-+	update_dec_buf_info(dst, dec_params);
-+	update_ctx_cur_info(vp9_ctx, dst, dec_params);
-+	seg = &dec_params->seg;
-+
-+	intra_only = !!(dec_params->flags &
-+			(V4L2_VP9_FRAME_FLAG_KEY_FRAME |
-+			 V4L2_VP9_FRAME_FLAG_INTRA_ONLY));
-+
-+	writel_relaxed(RKVDEC_MODE(RKVDEC_MODE_VP9),
-+		       rkvdec->regs + RKVDEC_REG_SYSCTRL);
-+
-+	bit_depth = dec_params->bit_depth;
-+	aligned_height = round_up(ctx->decoded_fmt.fmt.pix_mp.height, 64);
-+
-+	aligned_pitch = round_up(ctx->decoded_fmt.fmt.pix_mp.width *
-+				 bit_depth,
-+				 512) / 8;
-+	y_len = aligned_height * aligned_pitch;
-+	uv_len = y_len / 2;
-+	yuv_len = y_len + uv_len;
-+
-+	writel_relaxed(RKVDEC_Y_HOR_VIRSTRIDE(aligned_pitch / 16) |
-+		       RKVDEC_UV_HOR_VIRSTRIDE(aligned_pitch / 16),
-+		       rkvdec->regs + RKVDEC_REG_PICPAR);
-+	writel_relaxed(RKVDEC_Y_VIRSTRIDE(y_len / 16),
-+		       rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
-+	writel_relaxed(RKVDEC_YUV_VIRSTRIDE(yuv_len / 16),
-+		       rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
-+
-+	stream_len = vb2_get_plane_payload(&run->base.bufs.src->vb2_buf, 0);
-+	writel_relaxed(RKVDEC_STRM_LEN(stream_len),
-+		       rkvdec->regs + RKVDEC_REG_STRM_LEN);
-+
-+	/*
-+	 * Reset count buffer, because decoder only output intra related syntax
-+	 * counts when decoding intra frame, but update entropy need to update
-+	 * all the probabilities.
-+	 */
-+	if (intra_only)
-+		memset(vp9_ctx->count_tbl.cpu, 0, vp9_ctx->count_tbl.size);
-+
-+	vp9_ctx->cur.segmapid = vp9_ctx->last.segmapid;
-+	if (!intra_only &&
-+	    !(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) &&
-+	    (!(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED) ||
-+	     (seg->flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP)))
-+		vp9_ctx->cur.segmapid++;
-+
-+	for (i = 0; i < ARRAY_SIZE(ref_bufs); i++)
-+		config_ref_registers(ctx, run, ref_bufs, i);
-+
-+	for (i = 0; i < 8; i++)
-+		config_seg_registers(ctx, i);
-+
-+	writel_relaxed(RKVDEC_VP9_TX_MODE(dec_params->tx_mode) |
-+		       RKVDEC_VP9_FRAME_REF_MODE(dec_params->reference_mode),
-+		       rkvdec->regs + RKVDEC_VP9_CPRHEADER_CONFIG);
-+
-+	if (!intra_only) {
-+		const struct v4l2_vp9_loop_filter *lf;
-+		s8 delta;
-+
-+		if (vp9_ctx->last.valid)
-+			lf = &vp9_ctx->last.lf;
-+		else
-+			lf = &vp9_ctx->cur.lf;
-+
-+		val = 0;
-+		for (i = 0; i < ARRAY_SIZE(lf->ref_deltas); i++) {
-+			delta = lf->ref_deltas[i];
-+			val |= RKVDEC_REF_DELTAS_LASTFRAME(i, delta);
-+		}
-+
-+		writel_relaxed(val,
-+			       rkvdec->regs + RKVDEC_VP9_REF_DELTAS_LASTFRAME);
-+
-+		for (i = 0; i < ARRAY_SIZE(lf->mode_deltas); i++) {
-+			delta = lf->mode_deltas[i];
-+			last_frame_info |= RKVDEC_MODE_DELTAS_LASTFRAME(i,
-+									delta);
-+		}
-+	}
-+
-+	if (vp9_ctx->last.valid && !intra_only &&
-+	    vp9_ctx->last.seg.flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED)
-+		last_frame_info |= RKVDEC_SEG_EN_LASTFRAME;
-+
-+	if (vp9_ctx->last.valid &&
-+	    vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_SHOW_FRAME)
-+		last_frame_info |= RKVDEC_LAST_SHOW_FRAME;
-+
-+	if (vp9_ctx->last.valid &&
-+	    vp9_ctx->last.flags &
-+	    (V4L2_VP9_FRAME_FLAG_KEY_FRAME | V4L2_VP9_FRAME_FLAG_INTRA_ONLY))
-+		last_frame_info |= RKVDEC_LAST_INTRA_ONLY;
-+
-+	if (vp9_ctx->last.valid &&
-+	    last->vp9.width == dst->vp9.width &&
-+	    last->vp9.height == dst->vp9.height)
-+		last_frame_info |= RKVDEC_LAST_WIDHHEIGHT_EQCUR;
-+
-+	writel_relaxed(last_frame_info,
-+		       rkvdec->regs + RKVDEC_VP9_INFO_LASTFRAME);
-+
-+	writel_relaxed(stream_len - dec_params->compressed_header_size -
-+		       dec_params->uncompressed_header_size,
-+		       rkvdec->regs + RKVDEC_VP9_LASTTILE_SIZE);
-+
-+	for (i = 0; !intra_only && i < ARRAY_SIZE(ref_bufs); i++) {
-+		u32 refw = ref_bufs[i]->vp9.width;
-+		u32 refh = ref_bufs[i]->vp9.height;
-+		u32 hscale, vscale;
-+
-+		hscale = (refw << 14) /	dst->vp9.width;
-+		vscale = (refh << 14) / dst->vp9.height;
-+		writel_relaxed(RKVDEC_VP9_REF_HOR_SCALE(hscale) |
-+			       RKVDEC_VP9_REF_VER_SCALE(vscale),
-+			       rkvdec->regs + RKVDEC_VP9_REF_SCALE(i));
-+	}
-+
-+	addr = vb2_dma_contig_plane_dma_addr(&dst->base.vb.vb2_buf, 0);
-+	writel_relaxed(addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
-+	addr = vb2_dma_contig_plane_dma_addr(&run->base.bufs.src->vb2_buf, 0);
-+	writel_relaxed(addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
-+	writel_relaxed(vp9_ctx->priv_tbl.dma +
-+		       offsetof(struct rkvdec_vp9_priv_tbl, probs),
-+		       rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE);
-+	writel_relaxed(vp9_ctx->count_tbl.dma,
-+		       rkvdec->regs + RKVDEC_REG_VP9COUNT_BASE);
-+
-+	writel_relaxed(vp9_ctx->priv_tbl.dma +
-+		       offsetof(struct rkvdec_vp9_priv_tbl, segmap) +
-+		       (RKVDEC_VP9_MAX_SEGMAP_SIZE * vp9_ctx->cur.segmapid),
-+		       rkvdec->regs + RKVDEC_REG_VP9_SEGIDCUR_BASE);
-+	writel_relaxed(vp9_ctx->priv_tbl.dma +
-+		       offsetof(struct rkvdec_vp9_priv_tbl, segmap) +
-+		       (RKVDEC_VP9_MAX_SEGMAP_SIZE * (!vp9_ctx->cur.segmapid)),
-+		       rkvdec->regs + RKVDEC_REG_VP9_SEGIDLAST_BASE);
-+
-+	if (!intra_only &&
-+	    !(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) &&
-+	    vp9_ctx->last.valid)
-+		mv_ref = last;
-+	else
-+		mv_ref = dst;
-+
-+	writel_relaxed(get_mv_base_addr(mv_ref),
-+		       rkvdec->regs + RKVDEC_VP9_REF_COLMV_BASE);
-+
-+	writel_relaxed(ctx->decoded_fmt.fmt.pix_mp.width |
-+		       (ctx->decoded_fmt.fmt.pix_mp.height << 16),
-+		       rkvdec->regs + RKVDEC_REG_PERFORMANCE_CYCLE);
-+}
-+
-+static int
-+validate_dec_params(struct rkvdec_ctx *ctx,
-+	const struct v4l2_ctrl_vp9_frame_decode_params *dec_params)
-+{
-+	unsigned int aligned_width, aligned_height;
-+
-+	/* We only support profile 0. */
-+	if (dec_params->profile != 0) {
-+		dev_err(ctx->dev->dev, "unsupported profile %d\n",
-+			dec_params->profile);
-+		return -EINVAL;
-+	}
-+
-+	aligned_width = round_up(dec_params->frame_width_minus_1 + 1, 64);
-+	aligned_height = round_up(dec_params->frame_height_minus_1 + 1, 64);
-+
-+	/*
-+	 * Userspace should update the capture/decoded format when the
-+	 * resolution changes.
-+	 */
-+	if (aligned_width != ctx->decoded_fmt.fmt.pix_mp.width ||
-+	    aligned_height != ctx->decoded_fmt.fmt.pix_mp.height) {
-+		dev_err(ctx->dev->dev,
-+			"unexpected bitstream resolution %dx%d\n",
-+			dec_params->frame_width_minus_1 + 1,
-+			dec_params->frame_height_minus_1 +1);
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int rkvdec_vp9_run_preamble(struct rkvdec_ctx *ctx,
-+				   struct rkvdec_vp9_run *run)
-+{
-+	const struct v4l2_ctrl_vp9_frame_decode_params *dec_params;
-+	const struct v4l2_ctrl_vp9_frame_ctx *fctx = NULL;
-+	struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;
-+	struct v4l2_ctrl *ctrl;
-+	u8 frm_ctx;
-+	int ret;
-+
-+	rkvdec_run_preamble(ctx, &run->base);
-+
-+	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
-+			       V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS);
-+	WARN_ON(!ctrl);
-+
-+	dec_params = ctrl ? ctrl->p_cur.p : NULL;
-+	if (WARN_ON(!dec_params))
-+		return -EINVAL;
-+
-+	ret = validate_dec_params(ctx, dec_params);
-+	if (ret)
-+		return ret;
-+
-+	run->decode_params = dec_params;
-+
-+	/* No need to load the frame context if we don't need to update it. */
-+	if (!(dec_params->flags & V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX))
-+		return 0;
-+
-+	/*
-+	 * When a refresh context is requested in parallel mode, we should just
-+	 * update the context with the probs passed in the decode parameters.
-+	 */
-+	if (dec_params->flags & V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE) {
-+		vp9_ctx->frame_context.probs = dec_params->probs;
-+		return 0;
-+	}
-+
-+	frm_ctx = run->decode_params->frame_context_idx;
-+	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
-+			      V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(frm_ctx));
-+	if (WARN_ON(!ctrl))
-+		return 0;
-+
-+	fctx = ctrl->p_cur.p;
-+	vp9_ctx->frame_context = *fctx;
-+
-+	/*
-+	 * For intra-only frames, we must update the context TX and skip probs
-+	 * with the value passed in the decode params.
-+	 */
-+	if (dec_params->flags &
-+	    (V4L2_VP9_FRAME_FLAG_KEY_FRAME | V4L2_VP9_FRAME_FLAG_INTRA_ONLY)) {
-+		struct v4l2_vp9_probabilities *probs;
-+
-+		probs =  &vp9_ctx->frame_context.probs;
-+		memcpy(probs->skip, dec_params->probs.skip,
-+		       sizeof(probs->skip));
-+		memcpy(probs->tx8, dec_params->probs.tx8,
-+		       sizeof(probs->tx8));
-+		memcpy(probs->tx16, dec_params->probs.tx16,
-+		       sizeof(probs->tx16));
-+		memcpy(probs->tx32, dec_params->probs.tx32,
-+		       sizeof(probs->tx32));
-+	}
-+
-+	return 0;
-+}
-+
-+static int rkvdec_vp9_run(struct rkvdec_ctx *ctx)
-+{
-+	struct rkvdec_dev *rkvdec = ctx->dev;
-+	struct rkvdec_vp9_run run = { };
-+	int ret;
-+
-+	ret = rkvdec_vp9_run_preamble(ctx, &run);
-+	if (ret) {
-+		rkvdec_run_postamble(ctx, &run.base);
-+		return ret;
-+	}
-+
-+	/* Prepare probs. */
-+	init_probs(ctx, &run);
-+
-+	/* Configure hardware registers. */
-+	config_registers(ctx, &run);
-+
-+	rkvdec_run_postamble(ctx, &run.base);
-+
-+	schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000));
-+
-+	writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
-+	writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
-+
-+	writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
-+	/* Start decoding! */
-+	writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
-+	       RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
-+	       rkvdec->regs + RKVDEC_REG_INTERRUPT);
-+
-+	return 0;
-+}
-+
-+static u8 adapt_prob(u8 p1, u32 ct0, u32 ct1, u16 max_count, u32 update_factor)
-+{
-+	u32 ct = ct0 + ct1, p2;
-+	u32 lo = 1;
-+	u32 hi = 255;
-+
-+	if (!ct)
-+		return p1;
-+
-+	p2 = ((ct0 << 8) + (ct >> 1)) / ct;
-+	p2 = clamp(p2, lo, hi);
-+	ct = min_t(u32, ct, max_count);
-+
-+	if (WARN_ON(max_count >= 257))
-+		return p1;
-+
-+	update_factor = rkvdec_fastdiv(update_factor * ct, max_count);
-+
-+	return p1 + (((p2 - p1) * update_factor + 128) >> 8);
-+}
-+
-+#define BAND_6(band) ((band) == 0 ? 3 : 6)
-+
-+static void adapt_coeff(u8 coef[6][6][3],
-+			const struct rkvdec_vp9_refs_counts ref_cnt[6][6],
-+			u32 uf)
-+{
-+	s32 l, m, n;
-+
-+	for (l = 0; l < 6; l++) {
-+		for (m = 0; m < BAND_6(l); m++) {
-+			u8 *p = coef[l][m];
-+			const u32 n0 = ref_cnt[l][m].coeff[0];
-+			const u32 n1 = ref_cnt[l][m].coeff[1];
-+			const u32 n2 = ref_cnt[l][m].coeff[2];
-+			const u32 neob = ref_cnt[l][m].eob[1];
-+			const u32 eob_count = ref_cnt[l][m].eob[0];
-+			const u32 branch_ct[3][2] = {
-+				{ neob, eob_count - neob },
-+				{ n0, n1 + n2 },
-+				{ n1, n2 }
-+			};
-+
-+			for (n = 0; n < 3; n++)
-+				p[n] = adapt_prob(p[n], branch_ct[n][0],
-+						  branch_ct[n][1], 24, uf);
-+		}
-+	}
-+}
-+
-+static void
-+adapt_coef_probs(struct v4l2_vp9_probabilities *probs,
-+		 const struct rkvdec_vp9_refs_counts ref_cnt[2][4][2][6][6],
-+		 unsigned int uf)
-+{
-+	unsigned int i, j, k;
-+
-+	for (i = 0; i < ARRAY_SIZE(probs->coef); i++) {
-+		for (j = 0; j < ARRAY_SIZE(probs->coef[0]); j++) {
-+			for (k = 0; k < ARRAY_SIZE(probs->coef[0][0]);
-+			     k++) {
-+				adapt_coeff(probs->coef[i][j][k],
-+					    ref_cnt[k][i][j],
-+					    uf);
-+			}
-+		}
-+	}
-+}
-+
-+static void adapt_intra_frame_probs(struct rkvdec_ctx *ctx)
-+{
-+	struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;
-+	struct v4l2_vp9_probabilities *probs = &vp9_ctx->frame_context.probs;
-+	const struct rkvdec_vp9_intra_frame_symbol_counts *sym_cnts;
-+
-+	sym_cnts = vp9_ctx->count_tbl.cpu;
-+	adapt_coef_probs(probs, sym_cnts->ref_cnt, 112);
-+}
-+
-+static void
-+adapt_skip_probs(struct v4l2_vp9_probabilities *probs,
-+		 const struct rkvdec_vp9_inter_frame_symbol_counts *sym_cnts)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(probs->skip); i++)
-+		probs->skip[i] = adapt_prob(probs->skip[i],
-+					    sym_cnts->skip[i][0],
-+					    sym_cnts->skip[i][1],
-+					    20, 128);
-+}
-+
-+static void
-+adapt_is_inter_probs(struct v4l2_vp9_probabilities *probs,
-+		const struct rkvdec_vp9_inter_frame_symbol_counts *sym_cnts)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(probs->is_inter); i++)
-+		probs->is_inter[i] = adapt_prob(probs->is_inter[i],
-+						sym_cnts->inter[i][0],
-+						sym_cnts->inter[i][1],
-+						20, 128);
-+}
-+
-+static void
-+adapt_comp_mode_probs(struct v4l2_vp9_probabilities *probs,
-+		const struct rkvdec_vp9_inter_frame_symbol_counts *sym_cnts)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(probs->comp_mode); i++)
-+		probs->comp_mode[i] = adapt_prob(probs->comp_mode[i],
-+						 sym_cnts->comp[i][0],
-+						 sym_cnts->comp[i][1],
-+						 20, 128);
-+}
-+
-+static void
-+adapt_comp_ref_probs(struct v4l2_vp9_probabilities *probs,
-+		const struct rkvdec_vp9_inter_frame_symbol_counts *sym_cnts)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(probs->comp_ref); i++)
-+		probs->comp_ref[i] = adapt_prob(probs->comp_ref[i],
-+						sym_cnts->comp_ref[i][0],
-+						sym_cnts->comp_ref[i][1],
-+						20, 128);
-+}
-+
-+static void
-+adapt_single_ref_probs(struct v4l2_vp9_probabilities *probs,
-+		const struct rkvdec_vp9_inter_frame_symbol_counts *sym_cnts)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(probs->single_ref); i++) {
-+		u8 *p = probs->single_ref[i];
-+
-+		p[0] = adapt_prob(p[0], sym_cnts->single_ref[i][0][0],
-+				  sym_cnts->single_ref[i][0][1], 20, 128);
-+		p[1] = adapt_prob(p[1], sym_cnts->single_ref[i][1][0],
-+				  sym_cnts->single_ref[i][1][1], 20, 128);
-+	}
-+}
-+
-+static void
-+adapt_partition_probs(struct v4l2_vp9_probabilities *probs,
-+		const struct rkvdec_vp9_inter_frame_symbol_counts *sym_cnts)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(probs->partition); i++) {
-+		const u32 *c = sym_cnts->partition[i];
-+		u8 *p = probs->partition[i];
-+
-+		p[0] = adapt_prob(p[0], c[0], c[1] + c[2] + c[3], 20, 128);
-+		p[1] = adapt_prob(p[1], c[1], c[2] + c[3], 20, 128);
-+		p[2] = adapt_prob(p[2], c[2], c[3], 20, 128);
-+	}
-+}
-+
-+static void
-+adapt_tx_probs(struct v4l2_vp9_probabilities *probs,
-+	       const struct rkvdec_vp9_inter_frame_symbol_counts *sym_cnts)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(probs->tx8); i++) {
-+		u8 *p16x16 = probs->tx16[i];
-+		u8 *p32x32 = probs->tx32[i];
-+		const u32 *c16 = sym_cnts->tx16p[i];
-+		const u32 *c32 = sym_cnts->tx32p[i];
-+		const u32 *c8 = sym_cnts->tx8p[i];
-+		u8 *p8x8 = probs->tx8[i];
-+
-+		p8x8[0] = adapt_prob(p8x8[0], c8[0], c8[1], 20, 128);
-+		p16x16[0] = adapt_prob(p16x16[0], c16[0], c16[1] + c16[2],
-+				       20, 128);
-+		p16x16[1] = adapt_prob(p16x16[1], c16[1], c16[2], 20, 128);
-+		p32x32[0] = adapt_prob(p32x32[0], c32[0],
-+				       c32[1] + c32[2] + c32[3], 20, 128);
-+		p32x32[1] = adapt_prob(p32x32[1], c32[1], c32[2] + c32[3],
-+				       20, 128);
-+		p32x32[2] = adapt_prob(p32x32[2], c32[2], c32[3], 20, 128);
-+	}
-+}
-+
-+static void
-+adapt_interp_filter_probs(struct v4l2_vp9_probabilities *probs,
-+		const struct rkvdec_vp9_inter_frame_symbol_counts *sym_cnts)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(probs->interp_filter); i++) {
-+		u8 *p = probs->interp_filter[i];
-+		const u32 *c = sym_cnts->filter[i];
-+
-+		p[0] = adapt_prob(p[0], c[0], c[1] + c[2], 20, 128);
-+		p[1] = adapt_prob(p[1], c[1], c[2], 20, 128);
-+	}
-+}
-+
-+static void
-+adapt_inter_mode_probs(struct v4l2_vp9_probabilities *probs,
-+		const struct rkvdec_vp9_inter_frame_symbol_counts *sym_cnts)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(probs->inter_mode); i++) {
-+		const u32 *c = sym_cnts->mv_mode[i];
-+		u8 *p = probs->inter_mode[i];
-+
-+		p[0] = adapt_prob(p[0], c[2], c[1] + c[0] + c[3], 20, 128);
-+		p[1] = adapt_prob(p[1], c[0], c[1] + c[3], 20, 128);
-+		p[2] = adapt_prob(p[2], c[1], c[3], 20, 128);
-+	}
-+}
-+
-+static void
-+adapt_mv_probs(struct v4l2_vp9_probabilities *probs,
-+	       const struct rkvdec_vp9_inter_frame_symbol_counts *sym_cnts,
-+	       bool high_prec_mv)
-+{
-+	const u32 *c = sym_cnts->mv_joint;
-+	u8 *p = probs->mv.joint;
-+	unsigned int i, j;
-+	u32 sum;
-+
-+	p[0] = adapt_prob(p[0], c[0], c[1] + c[2] + c[3], 20, 128);
-+	p[1] = adapt_prob(p[1], c[1], c[2] + c[3], 20, 128);
-+	p[2] = adapt_prob(p[2], c[2], c[3], 20, 128);
-+
-+	for (i = 0; i < ARRAY_SIZE(probs->mv.sign); i++) {
-+		p = probs->mv.sign;
-+
-+		p[i] = adapt_prob(p[i], sym_cnts->sign[i][0],
-+				  sym_cnts->sign[i][1], 20, 128);
-+
-+		p = probs->mv.class[i];
-+		c = sym_cnts->classes[i];
-+		sum = c[1] + c[2] + c[3] + c[4] + c[5] + c[6] + c[7] + c[8] +
-+		      c[9] + c[10];
-+		p[0] = adapt_prob(p[0], c[0], sum, 20, 128);
-+		sum -= c[1];
-+		p[1] = adapt_prob(p[1], c[1], sum, 20, 128);
-+		sum -= c[2] + c[3];
-+		p[2] = adapt_prob(p[2], c[2] + c[3], sum, 20, 128);
-+		p[3] = adapt_prob(p[3], c[2], c[3], 20, 128);
-+		sum -= c[4] + c[5];
-+		p[4] = adapt_prob(p[4], c[4] + c[5], sum, 20, 128);
-+		p[5] = adapt_prob(p[5], c[4], c[5], 20, 128);
-+		sum -= c[6];
-+		p[6] = adapt_prob(p[6], c[6], sum, 20, 128);
-+		p[7] = adapt_prob(p[7], c[7] + c[8], c[9] + c[10], 20, 128);
-+		p[8] = adapt_prob(p[8], c[7], c[8], 20, 128);
-+		p[9] = adapt_prob(p[9], c[9], c[10], 20, 128);
-+
-+		p = probs->mv.class0_bit;
-+		p[i] = adapt_prob(p[i],
-+				  sym_cnts->class0[i][0],
-+				  sym_cnts->class0[i][1], 20, 128);
-+
-+		p = probs->mv.bits[i];
-+		for (j = 0; j < 10; j++)
-+			p[j] = adapt_prob(p[j], sym_cnts->bits[i][j][0],
-+					  sym_cnts->bits[i][j][1], 20, 128);
-+
-+		for (j = 0; j < 2; j++) {
-+			p = probs->mv.class0_fr[i][j];
-+			c = sym_cnts->class0_fp[i][j];
-+			p[0] = adapt_prob(p[0], c[0], c[1] + c[2] + c[3],
-+					  20, 128);
-+			p[1] = adapt_prob(p[1], c[1], c[2] + c[3], 20, 128);
-+			p[2] = adapt_prob(p[2], c[2], c[3], 20, 128);
-+		}
-+
-+		p = probs->mv.fr[i];
-+		c = sym_cnts->fp[i];
-+		p[0] = adapt_prob(p[0], c[0], c[1] + c[2] + c[3], 20, 128);
-+		p[1] = adapt_prob(p[1], c[1], c[2] + c[3], 20, 128);
-+		p[2] = adapt_prob(p[2], c[2], c[3], 20, 128);
-+
-+		if (!high_prec_mv)
-+			continue;
-+
-+		p = probs->mv.class0_hp;
-+		p[i] = adapt_prob(p[i], sym_cnts->class0_hp[i][0],
-+				  sym_cnts->class0_hp[i][1], 20, 128);
-+
-+		p = probs->mv.hp;
-+		p[i] = adapt_prob(p[i], sym_cnts->hp[i][0],
-+				  sym_cnts->hp[i][1], 20, 128);
-+	}
-+}
-+
-+static void
-+adapt_intra_mode_probs(u8 *p, const u32 *c)
-+{
-+	u32 sum = 0, s2;
-+	unsigned int i;
-+
-+	for (i = V4L2_VP9_INTRA_PRED_MODE_V; i <= V4L2_VP9_INTRA_PRED_MODE_TM;
-+	     i++)
-+		sum += c[i];
-+
-+	p[0] = adapt_prob(p[0], c[V4L2_VP9_INTRA_PRED_MODE_DC], sum, 20, 128);
-+	sum -= c[V4L2_VP9_INTRA_PRED_MODE_TM];
-+	p[1] = adapt_prob(p[1], c[V4L2_VP9_INTRA_PRED_MODE_TM], sum, 20, 128);
-+	sum -= c[V4L2_VP9_INTRA_PRED_MODE_V];
-+	p[2] = adapt_prob(p[2], c[V4L2_VP9_INTRA_PRED_MODE_V], sum, 20, 128);
-+	s2 = c[V4L2_VP9_INTRA_PRED_MODE_H] + c[V4L2_VP9_INTRA_PRED_MODE_D135] +
-+	     c[V4L2_VP9_INTRA_PRED_MODE_D117];
-+	sum -= s2;
-+	p[3] = adapt_prob(p[3], s2, sum, 20, 128);
-+	s2 -= c[V4L2_VP9_INTRA_PRED_MODE_H];
-+	p[4] = adapt_prob(p[4], c[V4L2_VP9_INTRA_PRED_MODE_H], s2, 20, 128);
-+	p[5] = adapt_prob(p[5], c[V4L2_VP9_INTRA_PRED_MODE_D135],
-+			  c[V4L2_VP9_INTRA_PRED_MODE_D117], 20, 128);
-+	sum -= c[V4L2_VP9_INTRA_PRED_MODE_D45];
-+	p[6] = adapt_prob(p[6], c[V4L2_VP9_INTRA_PRED_MODE_D45],
-+			  sum, 20, 128);
-+	sum -= c[V4L2_VP9_INTRA_PRED_MODE_D63];
-+	p[7] = adapt_prob(p[7], c[V4L2_VP9_INTRA_PRED_MODE_D63], sum,
-+			  20, 128);
-+	p[8] = adapt_prob(p[8], c[V4L2_VP9_INTRA_PRED_MODE_D153],
-+			  c[V4L2_VP9_INTRA_PRED_MODE_D207], 20, 128);
-+}
-+
-+static void
-+adapt_y_intra_mode_probs(struct v4l2_vp9_probabilities *probs,
-+		const struct rkvdec_vp9_inter_frame_symbol_counts *sym_cnts)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(probs->y_mode); i++)
-+		adapt_intra_mode_probs(probs->y_mode[i], sym_cnts->y_mode[i]);
-+}
-+
-+static void
-+adapt_uv_intra_mode_probs(struct v4l2_vp9_probabilities *probs,
-+		const struct rkvdec_vp9_inter_frame_symbol_counts *sym_cnts)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(probs->uv_mode); i++)
-+		adapt_intra_mode_probs(probs->uv_mode[i],
-+				       sym_cnts->uv_mode[i]);
-+}
-+
-+static void
-+adapt_inter_frame_probs(struct rkvdec_ctx *ctx)
-+{
-+	struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;
-+	struct v4l2_vp9_probabilities *probs = &vp9_ctx->frame_context.probs;
-+	const struct rkvdec_vp9_inter_frame_symbol_counts *sym_cnts;
-+
-+	sym_cnts = vp9_ctx->count_tbl.cpu;
-+	/* coefficients */
-+	if (vp9_ctx->last.valid &&
-+	    !(vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME))
-+		adapt_coef_probs(probs, sym_cnts->ref_cnt, 112);
-+	else
-+		adapt_coef_probs(probs, sym_cnts->ref_cnt, 128);
-+
-+	/* skip flag */
-+	adapt_skip_probs(probs, sym_cnts);
-+
-+	/* intra/inter flag */
-+	adapt_is_inter_probs(probs, sym_cnts);
-+
-+	/* comppred flag */
-+	adapt_comp_mode_probs(probs, sym_cnts);
-+
-+	/* reference frames */
-+	adapt_comp_ref_probs(probs, sym_cnts);
-+
-+	if (vp9_ctx->cur.reference_mode != V4L2_VP9_REF_MODE_COMPOUND)
-+		adapt_single_ref_probs(probs, sym_cnts);
-+
-+	/* block partitioning */
-+	adapt_partition_probs(probs, sym_cnts);
-+
-+	/* tx size */
-+	if (vp9_ctx->cur.tx_mode == V4L2_VP9_TX_MODE_SELECT)
-+		adapt_tx_probs(probs, sym_cnts);
-+
-+	/* interpolation filter */
-+	if (vp9_ctx->cur.interpolation_filter == V4L2_VP9_INTERP_FILTER_SWITCHABLE)
-+		adapt_interp_filter_probs(probs, sym_cnts);
-+
-+	/* inter modes */
-+	adapt_inter_mode_probs(probs, sym_cnts);
-+
-+	/* mv probs */
-+	adapt_mv_probs(probs, sym_cnts,
-+		       !!(vp9_ctx->cur.flags &
-+			  V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV));
-+
-+	/* y intra modes */
-+	adapt_y_intra_mode_probs(probs, sym_cnts);
-+
-+	/* uv intra modes */
-+	adapt_uv_intra_mode_probs(probs, sym_cnts);
-+}
-+
-+static void adapt_probs(struct rkvdec_ctx *ctx)
-+{
-+	struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;
-+	bool intra_only;
-+
-+	intra_only = !!(vp9_ctx->cur.flags &
-+			(V4L2_VP9_FRAME_FLAG_KEY_FRAME |
-+			 V4L2_VP9_FRAME_FLAG_INTRA_ONLY));
-+
-+	if (intra_only)
-+		adapt_intra_frame_probs(ctx);
-+	else
-+		adapt_inter_frame_probs(ctx);
-+}
-+
-+static void rkvdec_vp9_done(struct rkvdec_ctx *ctx,
-+			    struct vb2_v4l2_buffer *src_buf,
-+			    struct vb2_v4l2_buffer *dst_buf,
-+			    enum vb2_buffer_state result)
-+{
-+	struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;
-+	struct v4l2_ctrl *ctrl;
-+	unsigned int fctx_idx;
-+
-+	if (result == VB2_BUF_STATE_ERROR)
-+		goto out_update_last;
-+
-+	if (!(vp9_ctx->cur.flags & V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX))
-+		goto out_update_last;
-+
-+	fctx_idx = vp9_ctx->cur.frame_context_idx;
-+
-+	if (!(vp9_ctx->cur.flags &
-+	      (V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT |
-+	       V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE)))
-+		adapt_probs(ctx);
-+
-+	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
-+			      V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(fctx_idx));
-+	if (WARN_ON(!ctrl))
-+		goto out_update_last;
-+
-+	v4l2_ctrl_s_ctrl_compound(ctrl, V4L2_CTRL_TYPE_VP9_FRAME_CONTEXT,
-+				  &vp9_ctx->frame_context);
-+
-+out_update_last:
-+	update_ctx_last_info(vp9_ctx);
-+}
-+
-+static int rkvdec_vp9_start(struct rkvdec_ctx *ctx)
-+{
-+	struct rkvdec_dev *rkvdec = ctx->dev;
-+	struct rkvdec_vp9_priv_tbl *priv_tbl;
-+	struct rkvdec_vp9_ctx *vp9_ctx;
-+	u8 *count_tbl;
-+	int ret;
-+
-+	vp9_ctx = kzalloc(sizeof(*vp9_ctx), GFP_KERNEL);
-+	if (!vp9_ctx)
-+		return -ENOMEM;
-+
-+	ctx->priv = vp9_ctx;
-+
-+	priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
-+				      &vp9_ctx->priv_tbl.dma, GFP_KERNEL);
-+	if (!priv_tbl) {
-+		ret = -ENOMEM;
-+		goto err_free_ctx;
-+	}
-+
-+	vp9_ctx->priv_tbl.size = sizeof(*priv_tbl);
-+	vp9_ctx->priv_tbl.cpu = priv_tbl;
-+	memset(priv_tbl, 0, sizeof(*priv_tbl));
-+
-+	count_tbl = dma_alloc_coherent(rkvdec->dev, RKVDEC_VP9_COUNT_SIZE,
-+				       &vp9_ctx->count_tbl.dma, GFP_KERNEL);
-+	if (!count_tbl) {
-+		ret = -ENOMEM;
-+		goto err_free_priv_tbl;
-+	}
-+
-+	vp9_ctx->count_tbl.size = RKVDEC_VP9_COUNT_SIZE;
-+	vp9_ctx->count_tbl.cpu = count_tbl;
-+	memset(count_tbl, 0, sizeof(*count_tbl));
-+
-+	return 0;
-+
-+err_free_priv_tbl:
-+	dma_free_coherent(rkvdec->dev, vp9_ctx->priv_tbl.size,
-+			  vp9_ctx->priv_tbl.cpu, vp9_ctx->priv_tbl.dma);
-+
-+err_free_ctx:
-+	kfree(vp9_ctx);
-+	return ret;
-+}
-+
-+static void rkvdec_vp9_stop(struct rkvdec_ctx *ctx)
-+{
-+	struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv;
-+	struct rkvdec_dev *rkvdec = ctx->dev;
-+
-+	dma_free_coherent(rkvdec->dev, vp9_ctx->count_tbl.size,
-+			  vp9_ctx->count_tbl.cpu, vp9_ctx->count_tbl.dma);
-+	dma_free_coherent(rkvdec->dev, vp9_ctx->priv_tbl.size,
-+			  vp9_ctx->priv_tbl.cpu, vp9_ctx->priv_tbl.dma);
-+	kfree(vp9_ctx);
-+}
-+
-+static int rkvdec_vp9_adjust_fmt(struct rkvdec_ctx *ctx,
-+				 struct v4l2_format *f)
-+{
-+	struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp;
-+
-+	fmt->num_planes = 1;
-+	if (!fmt->plane_fmt[0].sizeimage)
-+		fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * 2;
-+	return 0;
-+}
-+
-+const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops = {
-+	.adjust_fmt = rkvdec_vp9_adjust_fmt,
-+	.start = rkvdec_vp9_start,
-+	.stop = rkvdec_vp9_stop,
-+	.run = rkvdec_vp9_run,
-+	.done = rkvdec_vp9_done,
-+};
-diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
-index fbaf0303f7c2..2c0c6dcbd066 100644
---- a/drivers/staging/media/rkvdec/rkvdec.c
-+++ b/drivers/staging/media/rkvdec/rkvdec.c
-@@ -159,6 +159,39 @@ static const u32 rkvdec_h264_decoded_fmts[] = {
- 	V4L2_PIX_FMT_NV20,
- };
- 
-+static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = {
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS,
-+	},
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0),
-+	},
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(1),
-+	},
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(2),
-+	},
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(3),
-+	},
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_VP9_PROFILE,
-+		.cfg.min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
-+		.cfg.max = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
-+		.cfg.def = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
-+	},
-+};
-+
-+static const struct rkvdec_ctrls rkvdec_vp9_ctrls = {
-+	.ctrls = rkvdec_vp9_ctrl_descs,
-+	.num_ctrls = ARRAY_SIZE(rkvdec_vp9_ctrl_descs),
-+};
-+
-+static const u32 rkvdec_vp9_decoded_fmts[] = {
-+	V4L2_PIX_FMT_NV12,
-+};
-+
- static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
- 	{
- 		.fourcc = V4L2_PIX_FMT_H264_SLICE,
-@@ -174,6 +207,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
- 		.ops = &rkvdec_h264_fmt_ops,
- 		.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
- 		.decoded_fmts = rkvdec_h264_decoded_fmts,
-+	},
-+	{
-+		.fourcc = V4L2_PIX_FMT_VP9_FRAME,
-+		.frmsize = {
-+			.min_width = 64,
-+			.max_width = 4096,
-+			.step_width = 64,
-+			.min_height = 64,
-+			.max_height = 2304,
-+			.step_height = 64,
-+		},
-+		.ctrls = &rkvdec_vp9_ctrls,
-+		.ops = &rkvdec_vp9_fmt_ops,
-+		.num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts),
-+		.decoded_fmts = rkvdec_vp9_decoded_fmts,
- 	}
- };
- 
-diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
-index fa24bcb6ff42..18dd721172d8 100644
---- a/drivers/staging/media/rkvdec/rkvdec.h
-+++ b/drivers/staging/media/rkvdec/rkvdec.h
-@@ -57,6 +57,10 @@ struct rkvdec_vp9_decoded_buffer_info {
- struct rkvdec_decoded_buffer {
- 	/* Must be the first field in this struct. */
- 	struct v4l2_m2m_buffer base;
-+
-+	union {
-+		struct rkvdec_vp9_decoded_buffer_info vp9;
-+	};
- };
- 
- static inline struct rkvdec_decoded_buffer *
-@@ -127,4 +131,6 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
- void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
- 
- extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops;
-+extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops;
-+
- #endif /* RKVDEC_H_ */
diff --git a/linux-2001-v4l-wip-rkvdec-hevc.patch b/linux-2001-v4l-wip-rkvdec-hevc.patch
deleted file mode 100644
index dcf2fd5..0000000
--- a/linux-2001-v4l-wip-rkvdec-hevc.patch
+++ /dev/null
@@ -1,3472 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Sat, 23 May 2020 15:03:46 +0000
-Subject: [PATCH] WIP: media: uapi: hevc: add fields needed for rkvdec
-
-NOTE: these fields are used by rkvdec hevc backend
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- include/media/hevc-ctrls.h | 12 ++++++++++--
- 1 file changed, 10 insertions(+), 2 deletions(-)
-
-diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h
-index ef63bc205756..a808894e8c76 100644
---- a/include/media/hevc-ctrls.h
-+++ b/include/media/hevc-ctrls.h
-@@ -58,6 +58,8 @@ enum v4l2_mpeg_video_hevc_start_code {
- /* The controls are not stable at the moment and will likely be reworked. */
- struct v4l2_ctrl_hevc_sps {
- 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */
-+	__u8	video_parameter_set_id;
-+	__u8	seq_parameter_set_id;
- 	__u16	pic_width_in_luma_samples;
- 	__u16	pic_height_in_luma_samples;
- 	__u8	bit_depth_luma_minus8;
-@@ -81,6 +83,8 @@ struct v4l2_ctrl_hevc_sps {
- 	__u8	chroma_format_idc;
- 	__u8	sps_max_sub_layers_minus1;
- 
-+	__u8	padding[6];
-+
- 	__u64	flags;
- };
- 
-@@ -108,6 +112,7 @@ struct v4l2_ctrl_hevc_sps {
- 
- struct v4l2_ctrl_hevc_pps {
- 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */
-+	__u8	pic_parameter_set_id;
- 	__u8	num_extra_slice_header_bits;
- 	__u8	num_ref_idx_l0_default_active_minus1;
- 	__u8	num_ref_idx_l1_default_active_minus1;
-@@ -123,7 +128,7 @@ struct v4l2_ctrl_hevc_pps {
- 	__s8	pps_tc_offset_div2;
- 	__u8	log2_parallel_merge_level_minus2;
- 
--	__u8	padding[4];
-+	__u8	padding;
- 	__u64	flags;
- };
- 
-@@ -202,7 +207,10 @@ struct v4l2_ctrl_hevc_slice_params {
- 	__u8	ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
- 	__u8	ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
- 
--	__u8	padding;
-+	__u16	short_term_ref_pic_set_size;
-+	__u16	long_term_ref_pic_set_size;
-+
-+	__u8	padding[4];
- 
- 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */
- 	struct v4l2_hevc_pred_weight_table pred_weight_table;
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Sat, 23 May 2020 15:07:15 +0000
-Subject: [PATCH] HACK: media: uapi: hevc: tiles and num_slices
-
----
- include/media/hevc-ctrls.h | 7 +++++--
- 1 file changed, 5 insertions(+), 2 deletions(-)
-
-diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h
-index a808894e8c76..f1b8756521b9 100644
---- a/include/media/hevc-ctrls.h
-+++ b/include/media/hevc-ctrls.h
-@@ -83,7 +83,8 @@ struct v4l2_ctrl_hevc_sps {
- 	__u8	chroma_format_idc;
- 	__u8	sps_max_sub_layers_minus1;
- 
--	__u8	padding[6];
-+	__u8	num_slices;
-+	__u8	padding[5];
- 
- 	__u64	flags;
- };
-@@ -210,7 +211,9 @@ struct v4l2_ctrl_hevc_slice_params {
- 	__u16	short_term_ref_pic_set_size;
- 	__u16	long_term_ref_pic_set_size;
- 
--	__u8	padding[4];
-+	__u32	num_entry_point_offsets;
-+	__u32	entry_point_offset_minus1[256];
-+	__u8	padding[8];
- 
- 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */
- 	struct v4l2_hevc_pred_weight_table pred_weight_table;
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Sat, 23 May 2020 15:17:45 +0000
-Subject: [PATCH] WIP: media: rkvdec: add HEVC backend
-
-NOTE: cabac table and scailing list code is copied 1:1 from mpp
-TODO: fix lowdelay flag and rework the scaling list part
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/staging/media/rkvdec/Makefile      |    2 +-
- drivers/staging/media/rkvdec/rkvdec-hevc.c | 2522 ++++++++++++++++++++
- drivers/staging/media/rkvdec/rkvdec-regs.h |    1 +
- drivers/staging/media/rkvdec/rkvdec.c      |   67 +
- drivers/staging/media/rkvdec/rkvdec.h      |    1 +
- 5 files changed, 2592 insertions(+), 1 deletion(-)
- create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c
-
-diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile
-index cb86b429cfaa..a77122641d14 100644
---- a/drivers/staging/media/rkvdec/Makefile
-+++ b/drivers/staging/media/rkvdec/Makefile
-@@ -1,3 +1,3 @@
- obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o
- 
--rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o
-+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o
-diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
-new file mode 100644
-index 000000000000..c3cceba837c2
---- /dev/null
-+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
-@@ -0,0 +1,2522 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Rockchip Video Decoder HEVC backend
-+ *
-+ * Copyright (C) 2019 Collabora, Ltd.
-+ *	Boris Brezillon <boris.brezillon@collabora.com>
-+ *
-+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
-+ *	Jeffy Chen <jeffy.chen@rock-chips.com>
-+ */
-+
-+#include <media/v4l2-mem2mem.h>
-+
-+#include "rkvdec.h"
-+#include "rkvdec-regs.h"
-+
-+/* Size in u8/u32 units. */
-+#define RKV_CABAC_TABLE_SIZE		27456
-+#define RKV_SCALING_LIST_SIZE		1360
-+#define RKV_PPS_SIZE			(80 / 4)
-+#define RKV_PPS_LEN			64
-+#define RKV_RPS_SIZE			(32 / 4)
-+#define RKV_RPS_LEN			600
-+
-+struct rkvdec_sps_pps_packet {
-+	u32 info[RKV_PPS_SIZE];
-+};
-+
-+struct rkvdec_rps_packet {
-+	u32 info[RKV_RPS_SIZE];
-+};
-+
-+struct rkvdec_ps_field {
-+	u16 offset;
-+	u8 len;
-+};
-+
-+#define PS_FIELD(_offset, _len) \
-+	((struct rkvdec_ps_field){ _offset, _len })
-+
-+/* SPS */
-+#define VIDEO_PARAMETER_SET_ID				PS_FIELD(0, 4)
-+#define SEQ_PARAMETER_SET_ID				PS_FIELD(4, 4)
-+#define CHROMA_FORMAT_IDC				PS_FIELD(8, 2)
-+#define PIC_WIDTH_IN_LUMA_SAMPLES			PS_FIELD(10, 13)
-+#define PIC_HEIGHT_IN_LUMA_SAMPLES			PS_FIELD(23, 13)
-+#define BIT_DEPTH_LUMA					PS_FIELD(36, 4)
-+#define BIT_DEPTH_CHROMA				PS_FIELD(40, 4)
-+#define LOG2_MAX_PIC_ORDER_CNT_LSB			PS_FIELD(44, 5)
-+#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE	PS_FIELD(49, 2)
-+#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE			PS_FIELD(51, 3)
-+#define LOG2_MIN_TRANSFORM_BLOCK_SIZE			PS_FIELD(54, 3)
-+#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE	PS_FIELD(57, 2)
-+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER		PS_FIELD(59, 3)
-+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA		PS_FIELD(62, 3)
-+#define SCALING_LIST_ENABLED_FLAG			PS_FIELD(65, 1)
-+#define AMP_ENABLED_FLAG				PS_FIELD(66, 1)
-+#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG		PS_FIELD(67, 1)
-+#define PCM_ENABLED_FLAG				PS_FIELD(68, 1)
-+#define PCM_SAMPLE_BIT_DEPTH_LUMA			PS_FIELD(69, 4)
-+#define PCM_SAMPLE_BIT_DEPTH_CHROMA			PS_FIELD(73, 4)
-+#define PCM_LOOP_FILTER_DISABLED_FLAG			PS_FIELD(77, 1)
-+#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE	PS_FIELD(78, 3)
-+#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE		PS_FIELD(81, 3)
-+#define NUM_SHORT_TERM_REF_PIC_SETS			PS_FIELD(84, 7)
-+#define LONG_TERM_REF_PICS_PRESENT_FLAG			PS_FIELD(91, 1)
-+#define NUM_LONG_TERM_REF_PICS_SPS			PS_FIELD(92, 6)
-+#define SPS_TEMPORAL_MVP_ENABLED_FLAG			PS_FIELD(98, 1)
-+#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG		PS_FIELD(99, 1)
-+/* PPS */
-+#define PIC_PARAMETER_SET_ID				PS_FIELD(128, 6)
-+#define PPS_SEQ_PARAMETER_SET_ID			PS_FIELD(134, 4)
-+#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG		PS_FIELD(138, 1)
-+#define OUTPUT_FLAG_PRESENT_FLAG			PS_FIELD(139, 1)
-+#define NUM_EXTRA_SLICE_HEADER_BITS			PS_FIELD(140, 13)
-+#define SIGN_DATA_HIDING_ENABLED_FLAG			PS_FIELD(153, 1)
-+#define CABAC_INIT_PRESENT_FLAG				PS_FIELD(154, 1)
-+#define NUM_REF_IDX_L0_DEFAULT_ACTIVE			PS_FIELD(155, 4)
-+#define NUM_REF_IDX_L1_DEFAULT_ACTIVE			PS_FIELD(159, 4)
-+#define INIT_QP_MINUS26					PS_FIELD(163, 7)
-+#define CONSTRAINED_INTRA_PRED_FLAG			PS_FIELD(170, 1)
-+#define TRANSFORM_SKIP_ENABLED_FLAG			PS_FIELD(171, 1)
-+#define CU_QP_DELTA_ENABLED_FLAG			PS_FIELD(172, 1)
-+#define LOG2_MIN_CU_QP_DELTA_SIZE			PS_FIELD(173, 3)
-+#define PPS_CB_QP_OFFSET				PS_FIELD(176, 5)
-+#define PPS_CR_QP_OFFSET				PS_FIELD(181, 5)
-+#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG	PS_FIELD(186, 1)
-+#define WEIGHTED_PRED_FLAG				PS_FIELD(187, 1)
-+#define WEIGHTED_BIPRED_FLAG				PS_FIELD(188, 1)
-+#define TRANSQUANT_BYPASS_ENABLED_FLAG			PS_FIELD(189, 1)
-+#define TILES_ENABLED_FLAG				PS_FIELD(190, 1)
-+#define ENTROPY_CODING_SYNC_ENABLED_FLAG		PS_FIELD(191, 1)
-+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG	PS_FIELD(192, 1)
-+#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG		PS_FIELD(193, 1)
-+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG		PS_FIELD(194, 1)
-+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG		PS_FIELD(195, 1)
-+#define PPS_BETA_OFFSET_DIV2				PS_FIELD(196, 4)
-+#define PPS_TC_OFFSET_DIV2				PS_FIELD(200, 4)
-+#define LISTS_MODIFICATION_PRESENT_FLAG			PS_FIELD(204, 1)
-+#define LOG2_PARALLEL_MERGE_LEVEL			PS_FIELD(205, 3)
-+#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG	PS_FIELD(208, 1)
-+#define NUM_TILE_COLUMNS				PS_FIELD(212, 5)
-+#define NUM_TILE_ROWS					PS_FIELD(217, 5)
-+#define COLUMN_WIDTH(i)					PS_FIELD(256 + (i * 8), 8)
-+#define ROW_HEIGHT(i)					PS_FIELD(416 + (i * 8), 8)
-+#define SCALING_LIST_ADDRESS				PS_FIELD(592, 32)
-+
-+/* Data structure describing auxiliary buffer format. */
-+struct rkvdec_hevc_priv_tbl {
-+	u8 cabac_table[RKV_CABAC_TABLE_SIZE];
-+	u8 scaling_list[RKV_SCALING_LIST_SIZE];
-+	struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN];
-+	struct rkvdec_rps_packet rps[RKV_RPS_LEN];
-+};
-+
-+struct rkvdec_hevc_run {
-+	struct rkvdec_run base;
-+	const struct v4l2_ctrl_hevc_slice_params *slices_params;
-+	const struct v4l2_ctrl_hevc_sps *sps;
-+	const struct v4l2_ctrl_hevc_pps *pps;
-+	const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix;
-+	int num_slices;
-+};
-+
-+struct rkvdec_hevc_ctx {
-+	struct rkvdec_aux_buf priv_tbl;
-+	struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache;
-+};
-+
-+// TODO: refactor scaling list code, was copied 1:1 from mpp
-+
-+typedef struct ScalingList {
-+    /* This is a little wasteful, since sizeID 0 only needs 8 coeffs,
-+     * and size ID 3 only has 2 arrays, not 6. */
-+    u8 sl[4][6][64];
-+    u8 sl_dc[2][6];
-+} scalingList_t;
-+
-+typedef struct ScalingFactor_Model {
-+    u8 scalingfactor0[1248];
-+    u8 scalingfactor1[96];     /*4X4 TU Rotate, total 16X4*/
-+    u8 scalingdc[12];          /*N1005 Vienna Meeting*/
-+    u8 reserverd[4];           /*16Bytes align*/
-+} scalingFactor_t;
-+
-+#define SCALING_LIST_SIZE_NUM 4
-+
-+static void
-+hal_record_scaling_list(scalingFactor_t *pScalingFactor_out,
-+                        scalingList_t *pScalingList)
-+{
-+    int i;
-+    u32 g_scalingListNum_model[SCALING_LIST_SIZE_NUM] = {6, 6, 6, 2}; // from C Model
-+    u32 nIndex = 0;
-+    u32 sizeId, matrixId, listId;
-+    u8 *p = pScalingFactor_out->scalingfactor0;
-+    u8 tmpBuf[8 * 8];
-+
-+    //output non-default scalingFactor Table (1248 BYTES)
-+    for (sizeId = 0; sizeId < SCALING_LIST_SIZE_NUM; sizeId++) {
-+        for (listId = 0; listId < g_scalingListNum_model[sizeId]; listId++) {
-+            if (sizeId < 3) {
-+                for (i = 0; i < (sizeId == 0 ? 16 : 64); i++) {
-+                    pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i];
-+                }
-+            } else {
-+                for (i = 0; i < 64; i ++) {
-+                    pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i];
-+                }
-+                for (i = 0; i < 128; i ++) {
-+                    pScalingFactor_out->scalingfactor0[nIndex++] = 0;
-+                }
-+            }
-+        }
-+    }
-+    //output non-default scalingFactor Table Rotation(96 Bytes)
-+    nIndex = 0;
-+    for (listId = 0; listId < g_scalingListNum_model[0]; listId++) {
-+        u8 temp16[16] = {0};
-+        for (i = 0; i < 16; i ++) {
-+            temp16[i] = (u8)pScalingList->sl[0][listId][i];
-+        }
-+        for (i = 0; i < 4; i ++) {
-+            pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i];
-+            pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 4];
-+            pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 8];
-+            pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 12];
-+        }
-+    }
-+    //output non-default ScalingList_DC_Coeff (12 BYTES)
-+    nIndex = 0;
-+    for (listId = 0; listId < g_scalingListNum_model[2]; listId++) { //sizeId = 2
-+        pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[0][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC
-+    }
-+    for (listId = 0; listId < g_scalingListNum_model[3]; listId++) { //sizeId = 3
-+        pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[1][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC
-+        pScalingFactor_out->scalingdc[nIndex++] = 0;
-+        pScalingFactor_out->scalingdc[nIndex++] = 0;
-+    }
-+
-+    //align 16X address
-+    nIndex = 0;
-+    for (i = 0; i < 4; i ++) {
-+        pScalingFactor_out->reserverd[nIndex++] = 0;
-+    }
-+
-+    //----------------------All above code show the normal store way in HM--------------------------
-+    //--------from now on, the scalingfactor0 is rotated 90', the scalingfactor1 is also rotated 90'
-+
-+    //sizeId == 0
-+    for (matrixId = 0; matrixId < 6; matrixId++) {
-+        p = pScalingFactor_out->scalingfactor0 + matrixId * 16;
-+
-+        for (i = 0; i < 4; i++) {
-+            tmpBuf[4 * 0 + i] = p[i * 4 + 0];
-+            tmpBuf[4 * 1 + i] = p[i * 4 + 1];
-+            tmpBuf[4 * 2 + i] = p[i * 4 + 2];
-+            tmpBuf[4 * 3 + i] = p[i * 4 + 3];
-+        }
-+        memcpy(p, tmpBuf, 4 * 4 * sizeof(u8));
-+    }
-+    //sizeId == 1
-+    for (matrixId = 0; matrixId < 6; matrixId++) {
-+        p = pScalingFactor_out->scalingfactor0 + 6 * 16 + matrixId * 64;
-+
-+        for (i = 0; i < 8; i++) {
-+            tmpBuf[8 * 0 + i] = p[i * 8 + 0];
-+            tmpBuf[8 * 1 + i] = p[i * 8 + 1];
-+            tmpBuf[8 * 2 + i] = p[i * 8 + 2];
-+            tmpBuf[8 * 3 + i] = p[i * 8 + 3];
-+            tmpBuf[8 * 4 + i] = p[i * 8 + 4];
-+            tmpBuf[8 * 5 + i] = p[i * 8 + 5];
-+            tmpBuf[8 * 6 + i] = p[i * 8 + 6];
-+            tmpBuf[8 * 7 + i] = p[i * 8 + 7];
-+        }
-+        memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
-+    }
-+    //sizeId == 2
-+    for (matrixId = 0; matrixId < 6; matrixId++) {
-+        p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + matrixId * 64;
-+
-+        for (i = 0; i < 8; i++) {
-+            tmpBuf[8 * 0 + i] = p[i * 8 + 0];
-+            tmpBuf[8 * 1 + i] = p[i * 8 + 1];
-+            tmpBuf[8 * 2 + i] = p[i * 8 + 2];
-+            tmpBuf[8 * 3 + i] = p[i * 8 + 3];
-+            tmpBuf[8 * 4 + i] = p[i * 8 + 4];
-+            tmpBuf[8 * 5 + i] = p[i * 8 + 5];
-+            tmpBuf[8 * 6 + i] = p[i * 8 + 6];
-+            tmpBuf[8 * 7 + i] = p[i * 8 + 7];
-+        }
-+        memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
-+    }
-+    //sizeId == 3
-+    for (matrixId = 0; matrixId < 6; matrixId++) {
-+        p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + 6 * 64 + matrixId * 64;
-+
-+        for (i = 0; i < 8; i++) {
-+            tmpBuf[8 * 0 + i] = p[i * 8 + 0];
-+            tmpBuf[8 * 1 + i] = p[i * 8 + 1];
-+            tmpBuf[8 * 2 + i] = p[i * 8 + 2];
-+            tmpBuf[8 * 3 + i] = p[i * 8 + 3];
-+            tmpBuf[8 * 4 + i] = p[i * 8 + 4];
-+            tmpBuf[8 * 5 + i] = p[i * 8 + 5];
-+            tmpBuf[8 * 6 + i] = p[i * 8 + 6];
-+            tmpBuf[8 * 7 + i] = p[i * 8 + 7];
-+        }
-+        memcpy(p, tmpBuf, 8 * 8 * sizeof(u8));
-+    }
-+
-+    //sizeId == 0
-+    for (matrixId = 0; matrixId < 6; matrixId++) {
-+        p = pScalingFactor_out->scalingfactor1 + matrixId * 16;
-+
-+        for (i = 0; i < 4; i++) {
-+            tmpBuf[4 * 0 + i] = p[i * 4 + 0];
-+            tmpBuf[4 * 1 + i] = p[i * 4 + 1];
-+            tmpBuf[4 * 2 + i] = p[i * 4 + 2];
-+            tmpBuf[4 * 3 + i] = p[i * 4 + 3];
-+        }
-+        memcpy(p, tmpBuf, 4 * 4 * sizeof(u8));
-+    }
-+}
-+
-+static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = {
-+    0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x68,
-+    0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x68,
-+    0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, 0x60, 0x50, 0x58,
-+    0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, 0x60, 0x60,
-+    0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68,
-+    0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60, 0x50, 0x50, 0x50, 0x48, 0x58, 0x58,
-+    0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50,
-+    0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07, 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40,
-+    0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40, 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f,
-+    0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37, 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x0f, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66,
-+    0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67,
-+    0x57, 0x5e, 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57,
-+    0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f,
-+    0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66,
-+    0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47, 0x57, 0x57,
-+    0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x4f,
-+    0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10, 0x47, 0x67, 0x40, 0x40,
-+    0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27, 0x4e, 0x47, 0x47, 0x00, 0x0f,
-+    0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x0e, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x64,
-+    0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x66,
-+    0x57, 0x5d, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5e, 0x5e, 0x4e, 0x56,
-+    0x4f, 0x07, 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x5e, 0x5e,
-+    0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64,
-+    0x45, 0x48, 0x20, 0x57, 0x66, 0x66, 0x56, 0x5e, 0x5e, 0x5d, 0x4e, 0x4e, 0x4e, 0x46, 0x56, 0x57,
-+    0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f,
-+    0x47, 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x66, 0x10, 0x47, 0x66, 0x40, 0x40,
-+    0x4f, 0x4d, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x03, 0x27, 0x4d, 0x47, 0x46, 0x01, 0x0f,
-+    0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x34, 0x01, 0x26, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x0d, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x62,
-+    0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x65,
-+    0x57, 0x5c, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5d, 0x5d, 0x4e, 0x56,
-+    0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, 0x65, 0x67, 0x66, 0x65, 0x63, 0x4d, 0x46, 0x62, 0x5d, 0x5d,
-+    0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, 0x65, 0x67, 0x66, 0x65, 0x63, 0x4d, 0x46, 0x62,
-+    0x44, 0x48, 0x20, 0x57, 0x65, 0x65, 0x56, 0x5d, 0x5d, 0x5c, 0x4e, 0x4d, 0x4e, 0x45, 0x56, 0x57,
-+    0x36, 0x07, 0x56, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f,
-+    0x47, 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x65, 0x10, 0x47, 0x65, 0x40, 0x40,
-+    0x4f, 0x4c, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x04, 0x27, 0x4c, 0x47, 0x45, 0x01, 0x0f,
-+    0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x33, 0x01, 0x25, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x0c, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0d, 0x40, 0x40, 0x40, 0x0d, 0x60,
-+    0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x64,
-+    0x56, 0x5b, 0x01, 0x1d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5c, 0x5c, 0x4d, 0x55,
-+    0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, 0x61, 0x4c, 0x45, 0x60, 0x5c, 0x5c,
-+    0x4d, 0x55, 0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, 0x61, 0x4c, 0x45, 0x60,
-+    0x43, 0x49, 0x21, 0x56, 0x64, 0x64, 0x55, 0x5c, 0x5c, 0x5b, 0x4d, 0x4c, 0x4d, 0x44, 0x55, 0x56,
-+    0x35, 0x07, 0x55, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x4e,
-+    0x46, 0x1d, 0x1d, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x64, 0x11, 0x46, 0x64, 0x40, 0x40,
-+    0x4e, 0x4b, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x06, 0x27, 0x4b, 0x46, 0x44, 0x02, 0x0f,
-+    0x4e, 0x35, 0x1e, 0x1d, 0x4e, 0x31, 0x02, 0x24, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x0b, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0c, 0x40, 0x40, 0x40, 0x0c, 0x5e,
-+    0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x63,
-+    0x56, 0x59, 0x01, 0x1c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5b, 0x5b, 0x4c, 0x54,
-+    0x4e, 0x07, 0x54, 0x64, 0x4e, 0x53, 0x63, 0x66, 0x64, 0x63, 0x60, 0x4b, 0x44, 0x5e, 0x5b, 0x5b,
-+    0x4c, 0x54, 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x53, 0x63, 0x66, 0x64, 0x63, 0x60, 0x4b, 0x44, 0x5e,
-+    0x41, 0x49, 0x21, 0x56, 0x63, 0x63, 0x54, 0x5b, 0x5b, 0x59, 0x4c, 0x4b, 0x4c, 0x43, 0x54, 0x56,
-+    0x34, 0x07, 0x54, 0x43, 0x54, 0x56, 0x34, 0x07, 0x54, 0x43, 0x54, 0x56, 0x34, 0x07, 0x54, 0x4e,
-+    0x46, 0x1c, 0x1c, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x63, 0x11, 0x46, 0x63, 0x40, 0x40,
-+    0x4e, 0x49, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x07, 0x27, 0x49, 0x46, 0x43, 0x03, 0x0f,
-+    0x4e, 0x34, 0x1e, 0x1c, 0x4e, 0x30, 0x03, 0x23, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x0a, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0c, 0x40, 0x40, 0x40, 0x0c, 0x5c,
-+    0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x62,
-+    0x56, 0x58, 0x01, 0x1c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5a, 0x5a, 0x4c, 0x54,
-+    0x4e, 0x07, 0x54, 0x64, 0x4e, 0x52, 0x62, 0x66, 0x64, 0x62, 0x5e, 0x4a, 0x44, 0x5c, 0x5a, 0x5a,
-+    0x4c, 0x54, 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x52, 0x62, 0x66, 0x64, 0x62, 0x5e, 0x4a, 0x44, 0x5c,
-+    0x40, 0x49, 0x21, 0x56, 0x62, 0x62, 0x54, 0x5a, 0x5a, 0x58, 0x4c, 0x4a, 0x4c, 0x42, 0x54, 0x56,
-+    0x34, 0x07, 0x54, 0x42, 0x54, 0x56, 0x34, 0x07, 0x54, 0x42, 0x54, 0x56, 0x34, 0x07, 0x54, 0x4e,
-+    0x46, 0x1c, 0x1c, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x62, 0x11, 0x46, 0x62, 0x40, 0x40,
-+    0x4e, 0x48, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x09, 0x27, 0x48, 0x46, 0x42, 0x03, 0x0f,
-+    0x4e, 0x34, 0x1e, 0x1c, 0x4e, 0x2e, 0x03, 0x22, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x09, 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0b, 0x40, 0x40, 0x40, 0x0b, 0x5a,
-+    0x45, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x61,
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-+    0x40, 0x07, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x1a,
-+    0x45, 0x1a, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x20, 0x0a, 0x2d, 0x20, 0x20, 0x0a, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x3e, 0x21, 0x05, 0x44, 0x40, 0x41, 0x53, 0x61, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x43, 0x0f,
-+    0x05, 0x1c, 0x40, 0x15, 0x0e, 0x1c, 0x2a, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0b, 0x0a, 0x1b, 0x07,
-+    0x01, 0x27, 0x26, 0x0a, 0x40, 0x45, 0x49, 0x40, 0x40, 0x40, 0x05, 0x05, 0x03, 0x09, 0x0b, 0x09,
-+    0x0e, 0x16, 0x03, 0x01, 0x01, 0x1c, 0x03, 0x44, 0x01, 0x01, 0x1c, 0x19, 0x13, 0x1e, 0x03, 0x09,
-+    0x0b, 0x09, 0x0e, 0x16, 0x03, 0x01, 0x01, 0x1c, 0x03, 0x44, 0x01, 0x01, 0x1c, 0x19, 0x13, 0x1e,
-+    0x23, 0x42, 0x3a, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x13, 0x13, 0x2a, 0x0b, 0x12, 0x43, 0x42,
-+    0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x4d,
-+    0x07, 0x0d, 0x0d, 0x1b, 0x23, 0x1b, 0x23, 0x0a, 0x17, 0x43, 0x42, 0x17, 0x43, 0x42, 0x40, 0x40,
-+    0x40, 0x06, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x04, 0x2d, 0x27, 0x1d, 0x07, 0x23, 0x1d, 0x1b,
-+    0x45, 0x18, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x21, 0x0a, 0x2e, 0x21, 0x21, 0x0a, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x3e, 0x22, 0x06, 0x43, 0x40, 0x42, 0x54, 0x62, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x44, 0x0f,
-+    0x06, 0x1e, 0x40, 0x16, 0x10, 0x1e, 0x2c, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x09, 0x09, 0x1c, 0x07,
-+    0x02, 0x27, 0x28, 0x09, 0x40, 0x46, 0x4a, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0a, 0x0c, 0x0a,
-+    0x10, 0x18, 0x04, 0x02, 0x02, 0x1e, 0x04, 0x43, 0x02, 0x02, 0x1e, 0x1a, 0x14, 0x20, 0x04, 0x0a,
-+    0x0c, 0x0a, 0x10, 0x18, 0x04, 0x02, 0x02, 0x1e, 0x04, 0x43, 0x02, 0x02, 0x1e, 0x1a, 0x14, 0x20,
-+    0x24, 0x41, 0x3c, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2c, 0x0c, 0x11, 0x44, 0x41,
-+    0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e,
-+    0x07, 0x0e, 0x0e, 0x1c, 0x24, 0x1c, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40,
-+    0x40, 0x05, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x1c,
-+    0x46, 0x17, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x22, 0x09, 0x30, 0x22, 0x22, 0x09, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x3e, 0x23, 0x06, 0x43, 0x40, 0x43, 0x54, 0x63, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x44, 0x0f,
-+    0x06, 0x1f, 0x40, 0x16, 0x11, 0x1f, 0x2e, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x08, 0x09, 0x1c, 0x07,
-+    0x03, 0x27, 0x29, 0x09, 0x40, 0x46, 0x4b, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0b, 0x0c, 0x0b,
-+    0x11, 0x19, 0x04, 0x03, 0x03, 0x1f, 0x04, 0x43, 0x03, 0x03, 0x1f, 0x1b, 0x14, 0x21, 0x04, 0x0b,
-+    0x0c, 0x0b, 0x11, 0x19, 0x04, 0x03, 0x03, 0x1f, 0x04, 0x43, 0x03, 0x03, 0x1f, 0x1b, 0x14, 0x21,
-+    0x24, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2e, 0x0c, 0x11, 0x44, 0x41,
-+    0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e,
-+    0x07, 0x0e, 0x0e, 0x1c, 0x24, 0x1c, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40,
-+    0x40, 0x04, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x1c,
-+    0x46, 0x16, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x23, 0x09, 0x31, 0x23, 0x23, 0x09, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x3e, 0x24, 0x06, 0x42, 0x40, 0x44, 0x55, 0x64, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x45, 0x0f,
-+    0x06, 0x21, 0x40, 0x16, 0x12, 0x21, 0x30, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x06, 0x09, 0x1d, 0x07,
-+    0x04, 0x27, 0x2a, 0x09, 0x40, 0x46, 0x4c, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c,
-+    0x12, 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, 0x22, 0x05, 0x0c,
-+    0x0d, 0x0c, 0x12, 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, 0x22,
-+    0x25, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x30, 0x0d, 0x11, 0x45, 0x41,
-+    0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x4e,
-+    0x07, 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x09, 0x17, 0x45, 0x41, 0x17, 0x45, 0x41, 0x40, 0x40,
-+    0x40, 0x03, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x02, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x1d,
-+    0x46, 0x15, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x24, 0x09, 0x32, 0x24, 0x24, 0x09, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x3e, 0x24, 0x06, 0x42, 0x40, 0x45, 0x56, 0x65, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x46, 0x0f,
-+    0x06, 0x22, 0x40, 0x16, 0x13, 0x22, 0x31, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x04, 0x08, 0x1d, 0x07,
-+    0x04, 0x27, 0x2b, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c,
-+    0x13, 0x1b, 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23, 0x05, 0x0c,
-+    0x0d, 0x0c, 0x13, 0x1b, 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23,
-+    0x25, 0x41, 0x3e, 0x40, 0x4f, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x31, 0x0d, 0x10, 0x46, 0x41,
-+    0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x4f,
-+    0x07, 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x08, 0x17, 0x46, 0x41, 0x17, 0x46, 0x41, 0x40, 0x40,
-+    0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x1d,
-+    0x47, 0x13, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x24, 0x08, 0x33, 0x24, 0x24, 0x08, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x3e, 0x25, 0x07, 0x41, 0x40, 0x45, 0x56, 0x65, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x46, 0x0f,
-+    0x07, 0x24, 0x40, 0x17, 0x15, 0x24, 0x33, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x03, 0x08, 0x1e, 0x07,
-+    0x05, 0x27, 0x2d, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, 0x07, 0x07, 0x06, 0x0d, 0x0e, 0x0d,
-+    0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25, 0x06, 0x0d,
-+    0x0e, 0x0d, 0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25,
-+    0x26, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x16, 0x16, 0x33, 0x0e, 0x10, 0x46, 0x40,
-+    0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x4f,
-+    0x07, 0x0f, 0x0f, 0x1e, 0x26, 0x1e, 0x26, 0x08, 0x17, 0x46, 0x40, 0x17, 0x46, 0x40, 0x40, 0x40,
-+    0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2f, 0x27, 0x1f, 0x07, 0x26, 0x1f, 0x1e,
-+    0x47, 0x12, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x25, 0x08, 0x35, 0x25, 0x25, 0x08, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x3e, 0x26, 0x07, 0x40, 0x40, 0x46, 0x57, 0x66, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f,
-+    0x07, 0x26, 0x40, 0x17, 0x16, 0x26, 0x35, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x01, 0x08, 0x1f, 0x07,
-+    0x06, 0x27, 0x2e, 0x08, 0x40, 0x47, 0x4e, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0e, 0x0f, 0x0e,
-+    0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, 0x26, 0x07, 0x0e,
-+    0x0f, 0x0e, 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, 0x26,
-+    0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x35, 0x0f, 0x10, 0x47, 0x40,
-+    0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f,
-+    0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40,
-+    0x40, 0x01, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f,
-+    0x47, 0x11, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x26, 0x08, 0x36, 0x26, 0x26, 0x08, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+    0x07, 0x3e, 0x27, 0x07, 0x40, 0x40, 0x47, 0x57, 0x67, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f,
-+    0x07, 0x27, 0x40, 0x17, 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07,
-+    0x07, 0x27, 0x2f, 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f,
-+    0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f,
-+    0x0f, 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27,
-+    0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47, 0x40,
-+    0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f,
-+    0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40,
-+    0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f,
-+    0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37, 0x27, 0x27, 0x08, 0x40, 0x40,
-+    0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-+};
-+
-+static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value)
-+{
-+	u8 bit = field.offset % 32, word = field.offset / 32;
-+	u64 mask = GENMASK_ULL(bit + field.len - 1, bit);
-+	u64 val = ((u64)value << bit) & mask;
-+
-+	buf[word] &= ~mask;
-+	buf[word] |= val;
-+	if (bit + field.len > 32) {
-+		buf[word + 1] &= ~(mask >> 32);
-+		buf[word + 1] |= val >> 32;
-+	}
-+}
-+
-+static void assemble_hw_pps(struct rkvdec_ctx *ctx,
-+			    struct rkvdec_hevc_run *run)
-+{
-+	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
-+	const struct v4l2_ctrl_hevc_sps *sps = run->sps;
-+	const struct v4l2_ctrl_hevc_pps *pps = run->pps;
-+	struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
-+	struct rkvdec_sps_pps_packet *hw_ps;
-+	u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y;
-+	u32 log2_min_cu_qp_delta_size;
-+	dma_addr_t scaling_list_address;
-+	u32 scaling_distance;
-+	int i;
-+
-+	/*
-+	 * HW read the SPS/PPS information from PPS packet index by PPS id.
-+	 * offset from the base can be calculated by PPS_id * 80 (size per PPS
-+	 * packet unit). so the driver copy SPS/PPS information to the exact PPS
-+	 * packet unit for HW accessing.
-+	 */
-+	hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
-+	memset(hw_ps, 0, sizeof(*hw_ps));
-+
-+	min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3;
-+	ctb_log2_size_y = min_cb_log2_size_y +
-+	    sps->log2_diff_max_min_luma_coding_block_size;
-+	ctb_size_y = 1 << ctb_log2_size_y;
-+
-+#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
-+	/* write sps */
-+	WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID);
-+	WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
-+	WRITE_PPS(1, CHROMA_FORMAT_IDC);
-+	WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES);
-+	WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES);
-+	WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
-+	WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
-+	WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4,
-+		  LOG2_MAX_PIC_ORDER_CNT_LSB);
-+	WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size,
-+		  LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE);
-+	WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3,
-+		  LOG2_MIN_LUMA_CODING_BLOCK_SIZE);
-+	WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2,
-+		  LOG2_MIN_TRANSFORM_BLOCK_SIZE);
-+	WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size,
-+		  LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE);
-+	WRITE_PPS(sps->max_transform_hierarchy_depth_inter,
-+		  MAX_TRANSFORM_HIERARCHY_DEPTH_INTER);
-+	WRITE_PPS(sps->max_transform_hierarchy_depth_intra,
-+		  MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA);
-+	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED),
-+		  SCALING_LIST_ENABLED_FLAG);
-+	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED),
-+		  AMP_ENABLED_FLAG);
-+	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET),
-+		  SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG);
-+	if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) {
-+		WRITE_PPS(1, PCM_ENABLED_FLAG);
-+		WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1,
-+			  PCM_SAMPLE_BIT_DEPTH_LUMA);
-+		WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1,
-+			  PCM_SAMPLE_BIT_DEPTH_CHROMA);
-+		WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED),
-+			  PCM_LOOP_FILTER_DISABLED_FLAG);
-+		WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size,
-+			  LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
-+		WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3,
-+			  LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
-+	}
-+	WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS);
-+	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT),
-+		  LONG_TERM_REF_PICS_PRESENT_FLAG);
-+	WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS);
-+	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED),
-+		  SPS_TEMPORAL_MVP_ENABLED_FLAG);
-+	WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED),
-+		  STRONG_INTRA_SMOOTHING_ENABLED_FLAG);
-+	//WRITE_PPS(0, PS_FIELD(100, 7));
-+	//WRITE_PPS(0x1fffff, PS_FIELD(107, 21));
-+
-+	/* write pps */
-+	WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
-+	WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED),
-+		  DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT),
-+		  OUTPUT_FLAG_PRESENT_FLAG);
-+	WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED),
-+		  SIGN_DATA_HIDING_ENABLED_FLAG);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT),
-+		  CABAC_INIT_PRESENT_FLAG);
-+	WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1,
-+		  NUM_REF_IDX_L0_DEFAULT_ACTIVE);
-+	WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1,
-+		  NUM_REF_IDX_L1_DEFAULT_ACTIVE);
-+	WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED),
-+		  CONSTRAINED_INTRA_PRED_FLAG);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED),
-+		  TRANSFORM_SKIP_ENABLED_FLAG);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED),
-+		  CU_QP_DELTA_ENABLED_FLAG);
-+
-+	log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth;
-+	WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE);
-+
-+	WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET);
-+	WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT),
-+		  PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED),
-+		  WEIGHTED_PRED_FLAG);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED),
-+		  WEIGHTED_BIPRED_FLAG);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED),
-+		  TRANSQUANT_BYPASS_ENABLED_FLAG);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED),
-+		  TILES_ENABLED_FLAG);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED),
-+		  ENTROPY_CODING_SYNC_ENABLED_FLAG);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED),
-+		  PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED),
-+		  LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED),
-+		  DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER),
-+		  PPS_DEBLOCKING_FILTER_DISABLED_FLAG);
-+	WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2);
-+	WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT),
-+		  LISTS_MODIFICATION_PRESENT_FLAG);
-+	WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL);
-+	WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT),
-+		  SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG);
-+	//WRITE_PPS(0, PS_FIELD(209, 3));
-+	WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS);
-+	WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS);
-+	//WRITE_PPS(0x2, PS_FIELD(222, 2));
-+	//WRITE_PPS(0xffffffff, PS_FIELD(224, 32));
-+
-+	if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) {
-+		for (i = 0; i <= pps->num_tile_columns_minus1; i++)
-+			WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i));
-+		for (i = 0; i <= pps->num_tile_rows_minus1; i++)
-+			WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i));
-+	} else {
-+		WRITE_PPS(round_up(sps->pic_width_in_luma_samples, ctb_size_y) - 1,
-+			  COLUMN_WIDTH(0));
-+		WRITE_PPS(round_up(sps->pic_height_in_luma_samples, ctb_size_y) - 1,
-+			  ROW_HEIGHT(0));
-+	}
-+
-+	scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list);
-+	scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance;
-+	WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS);
-+	//WRITE_PPS(0xffff, PS_FIELD(624, 16));
-+}
-+
-+static void assemble_hw_rps(struct rkvdec_ctx *ctx,
-+			    struct rkvdec_hevc_run *run)
-+{
-+	const struct v4l2_ctrl_hevc_slice_params *sl_params;
-+	const struct v4l2_hevc_dpb_entry *dpb;
-+	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
-+	struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
-+	struct rkvdec_rps_packet *hw_ps;
-+	int i, j;
-+
-+#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value)
-+
-+#define REF_PIC_LONG_TERM_L0(i)			PS_FIELD(i * 5, 1)
-+#define REF_PIC_IDX_L0(i)			PS_FIELD(1 + (i * 5), 4)
-+#define REF_PIC_LONG_TERM_L1(i)			PS_FIELD((i < 5 ? 75 : 132) + (i * 5), 1)
-+#define REF_PIC_IDX_L1(i)			PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4)
-+
-+#define LOWDELAY				PS_FIELD(182, 1)
-+#define SHORT_TERM_REF_PIC_SET_SIZE		PS_FIELD(183, 10)
-+#define LONG_TERM_REF_PIC_SET_SIZE		PS_FIELD(193, 9)
-+#define NUM_RPS_POC				PS_FIELD(202, 4)
-+
-+	for (j = 0; j < run->num_slices; j++) {
-+		sl_params = &run->slices_params[j];
-+		dpb = sl_params->dpb;
-+
-+		hw_ps = &priv_tbl->rps[j];
-+		memset(hw_ps, 0, sizeof(*hw_ps));
-+
-+		for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) {
-+			WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR),
-+				  REF_PIC_LONG_TERM_L0(i));
-+			WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
-+		}
-+
-+		for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) {
-+			WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR),
-+				  REF_PIC_LONG_TERM_L1(i));
-+			WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
-+		}
-+
-+		//WRITE_RPS(0xffffffff, PS_FIELD(96, 32));
-+
-+		// TODO: lowdelay
-+		WRITE_RPS(0, LOWDELAY);
-+
-+		// NOTE: these two differs from mpp
-+		WRITE_RPS(sl_params->short_term_ref_pic_set_size,
-+			  SHORT_TERM_REF_PIC_SET_SIZE);
-+		WRITE_RPS(sl_params->long_term_ref_pic_set_size,
-+			  LONG_TERM_REF_PIC_SET_SIZE);
-+
-+		WRITE_RPS(sl_params->num_rps_poc_st_curr_before +
-+			  sl_params->num_rps_poc_st_curr_after +
-+			  sl_params->num_rps_poc_lt_curr,
-+			  NUM_RPS_POC);
-+
-+		//WRITE_RPS(0x3ffff, PS_FIELD(206, 18));
-+		//WRITE_RPS(0xffffffff, PS_FIELD(224, 32));
-+	}
-+}
-+
-+static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx,
-+				     struct rkvdec_hevc_run *run)
-+{
-+	const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix;
-+	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
-+	struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu;
-+	u8 *dst;
-+	scalingList_t sl;
-+	int i, j;
-+
-+	if (!memcmp((void*)&hevc_ctx->scaling_matrix_cache, scaling,
-+		    sizeof(struct v4l2_ctrl_hevc_scaling_matrix)))
-+		return;
-+
-+	memset(&sl, 0, sizeof(scalingList_t));
-+
-+	for (i = 0; i < 6; i++) {
-+		for (j = 0; j < 16; j++)
-+			sl.sl[0][i][j] = scaling->scaling_list_4x4[i][j];
-+		for (j = 0; j < 64; j++) {
-+			sl.sl[1][i][j] = scaling->scaling_list_8x8[i][j];
-+			sl.sl[2][i][j] = scaling->scaling_list_16x16[i][j];
-+		if (i < 2)
-+			sl.sl[3][i][j] = scaling->scaling_list_32x32[i][j];
-+		}
-+		sl.sl_dc[0][i] = scaling->scaling_list_dc_coef_16x16[i];
-+		if (i < 2)
-+			sl.sl_dc[1][i] = scaling->scaling_list_dc_coef_32x32[i];
-+	}
-+
-+	dst = tbl->scaling_list;
-+	hal_record_scaling_list((scalingFactor_t *)dst, &sl);
-+
-+	memcpy((void*)&hevc_ctx->scaling_matrix_cache, scaling,
-+	       sizeof(struct v4l2_ctrl_hevc_scaling_matrix));
-+}
-+
-+static struct vb2_buffer *
-+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run,
-+	    unsigned int dpb_idx)
-+{
-+	struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
-+	const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
-+	const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb;
-+	struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q;
-+	int buf_idx = -1;
-+
-+	if (dpb_idx < sl_params->num_active_dpb_entries)
-+		buf_idx = vb2_find_timestamp(cap_q,
-+					     dpb[dpb_idx].timestamp, 0);
-+
-+	/*
-+	 * If a DPB entry is unused or invalid, address of current destination
-+	 * buffer is returned.
-+	 */
-+	if (buf_idx < 0)
-+		return &run->base.bufs.dst->vb2_buf;
-+
-+	return vb2_get_buffer(cap_q, buf_idx);
-+}
-+
-+static void config_registers(struct rkvdec_ctx *ctx,
-+			     struct rkvdec_hevc_run *run)
-+{
-+	struct rkvdec_dev *rkvdec = ctx->dev;
-+	const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
-+	const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb;
-+	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
-+	dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma;
-+	const struct v4l2_pix_format_mplane *dst_fmt;
-+	struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
-+	struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
-+	const struct v4l2_format *f;
-+	dma_addr_t rlc_addr;
-+	dma_addr_t refer_addr;
-+	u32 rlc_len;
-+	u32 hor_virstride;
-+	u32 ver_virstride;
-+	u32 y_virstride;
-+	u32 uv_virstride;
-+	u32 yuv_virstride;
-+	u32 offset;
-+	dma_addr_t dst_addr;
-+	u32 reg, i;
-+
-+	reg = RKVDEC_MODE(RKVDEC_MODE_HEVC);
-+	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL);
-+
-+	f = &ctx->decoded_fmt;
-+	dst_fmt = &f->fmt.pix_mp;
-+	hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
-+	ver_virstride = dst_fmt->height;
-+	y_virstride = hor_virstride * ver_virstride;
-+	uv_virstride = y_virstride / 2;
-+	yuv_virstride = y_virstride + uv_virstride;
-+
-+	reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) |
-+	      RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) |
-+	      RKVDEC_SLICE_NUM_LOWBITS(run->num_slices);
-+	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR);
-+
-+	/* config rlc base address */
-+	rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
-+	writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
-+
-+	rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
-+	reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64);
-+	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN);
-+
-+	/* config cabac table */
-+	offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table);
-+	writel_relaxed(priv_start_addr + offset,
-+		       rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE);
-+
-+	/* config output base address */
-+	dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
-+	writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
-+
-+	reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16);
-+	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
-+
-+	reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16);
-+	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
-+
-+	/* config ref pic address */
-+	for (i = 0; i < 15; i++) {
-+		struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i);
-+
-+		if (i < 4 && sl_params->num_active_dpb_entries) {
-+			reg = GENMASK(sl_params->num_active_dpb_entries - 1, 0);
-+			reg = (reg >> (i * 4)) & 0xf;
-+		} else
-+			reg = 0;
-+
-+		refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
-+		writel_relaxed(refer_addr | reg,
-+			       rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i));
-+
-+		reg = RKVDEC_POC_REFER(i < sl_params->num_active_dpb_entries ? dpb[i].pic_order_cnt[0] : 0);
-+		writel_relaxed(reg,
-+			       rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i));
-+	}
-+
-+	reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt);
-+	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0);
-+
-+	/* config hw pps address */
-+	offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set);
-+	writel_relaxed(priv_start_addr + offset,
-+		       rkvdec->regs + RKVDEC_REG_PPS_BASE);
-+
-+	/* config hw rps address */
-+	offset = offsetof(struct rkvdec_hevc_priv_tbl, rps);
-+	writel_relaxed(priv_start_addr + offset,
-+		       rkvdec->regs + RKVDEC_REG_RPS_BASE);
-+
-+	reg = RKVDEC_AXI_DDR_RDATA(0);
-+	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA);
-+
-+	reg = RKVDEC_AXI_DDR_WDATA(0);
-+	writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA);
-+}
-+
-+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES		2
-+
-+static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx,
-+				  struct v4l2_format *f)
-+{
-+	struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp;
-+
-+	fmt->num_planes = 1;
-+	if (!fmt->plane_fmt[0].sizeimage)
-+		fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height *
-+					      RKVDEC_HEVC_MAX_DEPTH_IN_BYTES;
-+	return 0;
-+}
-+
-+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
-+{
-+	struct rkvdec_dev *rkvdec = ctx->dev;
-+	struct rkvdec_hevc_priv_tbl *priv_tbl;
-+	struct rkvdec_hevc_ctx *hevc_ctx;
-+	int ret;
-+
-+	hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL);
-+	if (!hevc_ctx)
-+		return -ENOMEM;
-+
-+	priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
-+				      &hevc_ctx->priv_tbl.dma, GFP_KERNEL);
-+	if (!priv_tbl) {
-+		ret = -ENOMEM;
-+		goto err_free_ctx;
-+	}
-+
-+	hevc_ctx->priv_tbl.size = sizeof(*priv_tbl);
-+	hevc_ctx->priv_tbl.cpu = priv_tbl;
-+	memset(priv_tbl, 0, sizeof(*priv_tbl));
-+	memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table,
-+	       sizeof(rkvdec_hevc_cabac_table));
-+
-+	ctx->priv = hevc_ctx;
-+	return 0;
-+
-+err_free_ctx:
-+	kfree(hevc_ctx);
-+	return ret;
-+}
-+
-+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx)
-+{
-+	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
-+	struct rkvdec_dev *rkvdec = ctx->dev;
-+
-+	dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size,
-+			  hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma);
-+	kfree(hevc_ctx);
-+}
-+
-+static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx,
-+				     struct rkvdec_hevc_run *run)
-+{
-+	struct v4l2_ctrl *ctrl;
-+
-+	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
-+			      V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS);
-+	run->slices_params = ctrl ? ctrl->p_cur.p : NULL;
-+	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
-+			      V4L2_CID_MPEG_VIDEO_HEVC_SPS);
-+	run->sps = ctrl ? ctrl->p_cur.p : NULL;
-+	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
-+			      V4L2_CID_MPEG_VIDEO_HEVC_PPS);
-+	run->pps = ctrl ? ctrl->p_cur.p : NULL;
-+	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
-+			      V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX);
-+	run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL;
-+
-+	rkvdec_run_preamble(ctx, &run->base);
-+
-+	// HACK: we need num slices from somewhere
-+	run->num_slices = run->sps->num_slices;
-+}
-+
-+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
-+{
-+	struct rkvdec_dev *rkvdec = ctx->dev;
-+	struct rkvdec_hevc_run run;
-+
-+	rkvdec_hevc_run_preamble(ctx, &run);
-+
-+	assemble_hw_scaling_list(ctx, &run);
-+	assemble_hw_pps(ctx, &run);
-+	assemble_hw_rps(ctx, &run);
-+	config_registers(ctx, &run);
-+
-+	rkvdec_run_postamble(ctx, &run.base);
-+
-+	// sw_cabac_error_e - cabac error enable
-+	writel_relaxed(0xfdfffffd, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
-+	// slice end error enable = BIT(28)
-+	// frame end error enable = BIT(29)
-+	writel_relaxed(0x30000000, rkvdec->regs + RKVDEC_REG_H264_ERR_E);
-+
-+	schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000));
-+
-+	writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
-+	writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
-+
-+	/* Start decoding! */
-+	writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
-+	       RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
-+	       rkvdec->regs + RKVDEC_REG_INTERRUPT);
-+
-+	return 0;
-+}
-+
-+const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = {
-+	.adjust_fmt = rkvdec_hevc_adjust_fmt,
-+	.start = rkvdec_hevc_start,
-+	.stop = rkvdec_hevc_stop,
-+	.run = rkvdec_hevc_run,
-+};
-diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
-index 3acc914888f6..4addfaefdfb4 100644
---- a/drivers/staging/media/rkvdec/rkvdec-regs.h
-+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
-@@ -48,6 +48,7 @@
- #define RKVDEC_RLC_MODE					BIT(11)
- #define RKVDEC_STRM_START_BIT(x)			(((x) & 0x7f) << 12)
- #define RKVDEC_MODE(x)					(((x) & 0x03) << 20)
-+#define RKVDEC_MODE_HEVC				0
- #define RKVDEC_MODE_H264				1
- #define RKVDEC_MODE_VP9					2
- #define RKVDEC_RPS_MODE					BIT(24)
-diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
-index 2c0c6dcbd066..c269e4a21a29 100644
---- a/drivers/staging/media/rkvdec/rkvdec.c
-+++ b/drivers/staging/media/rkvdec/rkvdec.c
-@@ -147,6 +147,58 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
- 	},
- };
- 
-+static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = {
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS,
-+		// HACK: match ffmpeg v4l2 request api hwaccel size,
-+		//       we should support variable length up to 600 slices
-+		.cfg.dims = { 32 },
-+	},
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS,
-+	},
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PPS,
-+	},
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX,
-+	},
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE,
-+		.cfg.min = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
-+		.cfg.max = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
-+		.cfg.def = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
-+	},
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_START_CODE,
-+		.cfg.min = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
-+		.cfg.def = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
-+		.cfg.max = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
-+	},
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
-+		.cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
-+		.cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
-+		.cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
-+	},
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
-+		.cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
-+		.cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
-+	},
-+};
-+
-+static const struct rkvdec_ctrls rkvdec_hevc_ctrls = {
-+	.ctrls = rkvdec_hevc_ctrl_descs,
-+	.num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs),
-+};
-+
-+static const u32 rkvdec_hevc_decoded_fmts[] = {
-+	V4L2_PIX_FMT_NV12,
-+	V4L2_PIX_FMT_NV15,
-+};
-+
-+
- static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
- 	.ctrls = rkvdec_h264_ctrl_descs,
- 	.num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs),
-@@ -208,6 +260,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
- 		.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
- 		.decoded_fmts = rkvdec_h264_decoded_fmts,
- 	},
-+	{
-+		.fourcc = V4L2_PIX_FMT_HEVC_SLICE,
-+		.frmsize = {
-+			.min_width = 64,
-+			.max_width = 4096,
-+			.step_width = 64,
-+			.min_height = 64,
-+			.max_height = 2304,
-+			.step_height = 16,
-+		},
-+		.ctrls = &rkvdec_hevc_ctrls,
-+		.ops = &rkvdec_hevc_fmt_ops,
-+		.num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
-+		.decoded_fmts = rkvdec_hevc_decoded_fmts,
-+	},
- 	{
- 		.fourcc = V4L2_PIX_FMT_VP9_FRAME,
- 		.frmsize = {
-diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
-index 18dd721172d8..d60840c179a4 100644
---- a/drivers/staging/media/rkvdec/rkvdec.h
-+++ b/drivers/staging/media/rkvdec/rkvdec.h
-@@ -131,6 +131,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
- void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
- 
- extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops;
-+extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops;
- extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops;
- 
- #endif /* RKVDEC_H_ */
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Sat, 21 Aug 2021 16:01:43 +0200
-Subject: [PATCH] media: rkvdec: hevc: adapt for 5.14 uAPI
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- drivers/staging/media/rkvdec/rkvdec-hevc.c | 29 +++++++++++++---------
- drivers/staging/media/rkvdec/rkvdec.c      |  3 +++
- 2 files changed, 20 insertions(+), 12 deletions(-)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
-index c3cceba837c2..5c341b5fa534 100644
---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
-+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
-@@ -116,6 +116,7 @@ struct rkvdec_hevc_priv_tbl {
- struct rkvdec_hevc_run {
- 	struct rkvdec_run base;
- 	const struct v4l2_ctrl_hevc_slice_params *slices_params;
-+	const struct v4l2_ctrl_hevc_decode_params *decode_params;
- 	const struct v4l2_ctrl_hevc_sps *sps;
- 	const struct v4l2_ctrl_hevc_pps *pps;
- 	const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix;
-@@ -2179,6 +2180,7 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
- static void assemble_hw_rps(struct rkvdec_ctx *ctx,
- 			    struct rkvdec_hevc_run *run)
- {
-+	const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
- 	const struct v4l2_ctrl_hevc_slice_params *sl_params;
- 	const struct v4l2_hevc_dpb_entry *dpb;
- 	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
-@@ -2200,7 +2202,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
- 
- 	for (j = 0; j < run->num_slices; j++) {
- 		sl_params = &run->slices_params[j];
--		dpb = sl_params->dpb;
-+		dpb = decode_params->dpb;
- 
- 		hw_ps = &priv_tbl->rps[j];
- 		memset(hw_ps, 0, sizeof(*hw_ps));
-@@ -2228,9 +2230,9 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
- 		WRITE_RPS(sl_params->long_term_ref_pic_set_size,
- 			  LONG_TERM_REF_PIC_SET_SIZE);
- 
--		WRITE_RPS(sl_params->num_rps_poc_st_curr_before +
--			  sl_params->num_rps_poc_st_curr_after +
--			  sl_params->num_rps_poc_lt_curr,
-+		WRITE_RPS(decode_params->num_poc_st_curr_before +
-+			  decode_params->num_poc_st_curr_after +
-+			  decode_params->num_poc_lt_curr,
- 			  NUM_RPS_POC);
- 
- 		//WRITE_RPS(0x3ffff, PS_FIELD(206, 18));
-@@ -2280,12 +2282,12 @@ get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run,
- 	    unsigned int dpb_idx)
- {
- 	struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
--	const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
--	const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb;
-+	const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
-+	const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
- 	struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q;
- 	int buf_idx = -1;
- 
--	if (dpb_idx < sl_params->num_active_dpb_entries)
-+	if (dpb_idx < decode_params->num_active_dpb_entries)
- 		buf_idx = vb2_find_timestamp(cap_q,
- 					     dpb[dpb_idx].timestamp, 0);
- 
-@@ -2303,8 +2305,9 @@ static void config_registers(struct rkvdec_ctx *ctx,
- 			     struct rkvdec_hevc_run *run)
- {
- 	struct rkvdec_dev *rkvdec = ctx->dev;
-+	const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
- 	const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
--	const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb;
-+	const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
- 	struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
- 	dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma;
- 	const struct v4l2_pix_format_mplane *dst_fmt;
-@@ -2366,8 +2369,8 @@ static void config_registers(struct rkvdec_ctx *ctx,
- 	for (i = 0; i < 15; i++) {
- 		struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i);
- 
--		if (i < 4 && sl_params->num_active_dpb_entries) {
--			reg = GENMASK(sl_params->num_active_dpb_entries - 1, 0);
-+		if (i < 4 && decode_params->num_active_dpb_entries) {
-+			reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0);
- 			reg = (reg >> (i * 4)) & 0xf;
- 		} else
- 			reg = 0;
-@@ -2376,7 +2379,7 @@ static void config_registers(struct rkvdec_ctx *ctx,
- 		writel_relaxed(refer_addr | reg,
- 			       rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i));
- 
--		reg = RKVDEC_POC_REFER(i < sl_params->num_active_dpb_entries ? dpb[i].pic_order_cnt[0] : 0);
-+		reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt[0] : 0);
- 		writel_relaxed(reg,
- 			       rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i));
- 	}
-@@ -2461,7 +2464,9 @@ static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx,
- 				     struct rkvdec_hevc_run *run)
- {
- 	struct v4l2_ctrl *ctrl;
--
-+	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
-+			      V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS);
-+	run->decode_params = ctrl ? ctrl->p_cur.p : NULL;
- 	ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
- 			      V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS);
- 	run->slices_params = ctrl ? ctrl->p_cur.p : NULL;
-diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
-index c269e4a21a29..e91c2b3e9fd9 100644
---- a/drivers/staging/media/rkvdec/rkvdec.c
-+++ b/drivers/staging/media/rkvdec/rkvdec.c
-@@ -163,6 +163,9 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = {
- 	{
- 		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX,
- 	},
-+	{
-+		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS,
-+	},
- 	{
- 		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE,
- 		.cfg.min = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Sat, 1 Aug 2020 12:24:58 +0000
-Subject: [PATCH] WIP: media: rkvdec: add HEVC format validation
-
----
- drivers/staging/media/rkvdec/rkvdec-hevc.c | 11 +++++++++++
- drivers/staging/media/rkvdec/rkvdec.c      | 23 +++++++++++++++++++++-
- 2 files changed, 33 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
-index 5c341b5fa534..8ea2ad9f4f3a 100644
---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
-+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
-@@ -2418,6 +2418,16 @@ static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx,
- 	return 0;
- }
- 
-+static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
-+{
-+	const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
-+
-+	if (sps->bit_depth_luma_minus8 == 2)
-+		return V4L2_PIX_FMT_NV15;
-+	else
-+		return V4L2_PIX_FMT_NV12;
-+}
-+
- static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
- {
- 	struct rkvdec_dev *rkvdec = ctx->dev;
-@@ -2521,6 +2531,7 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
- 
- const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = {
- 	.adjust_fmt = rkvdec_hevc_adjust_fmt,
-+	.valid_fmt = rkvdec_hevc_valid_fmt,
- 	.start = rkvdec_hevc_start,
- 	.stop = rkvdec_hevc_stop,
- 	.run = rkvdec_hevc_run,
-diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
-index e91c2b3e9fd9..da32a6350344 100644
---- a/drivers/staging/media/rkvdec/rkvdec.c
-+++ b/drivers/staging/media/rkvdec/rkvdec.c
-@@ -79,6 +79,26 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
- 		if (width > ctx->coded_fmt.fmt.pix_mp.width ||
- 		    height > ctx->coded_fmt.fmt.pix_mp.height)
- 			return -EINVAL;
-+	} else if (ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_SPS) {
-+		const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
-+
-+		if (sps->chroma_format_idc > 1)
-+			/* Only 4:0:0 and 4:2:0 are supported */
-+			return -EINVAL;
-+		if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
-+			/* Luma and chroma bit depth mismatch */
-+			return -EINVAL;
-+		if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
-+			/* Only 8-bit and 10-bit is supported */
-+			return -EINVAL;
-+
-+		if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl))
-+			/* Only current valid format */
-+			return -EINVAL;
-+
-+		if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width ||
-+		    sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height)
-+			return -EINVAL;
- 	}
- 	return 0;
- }
-@@ -87,7 +107,7 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
- {
- 	struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
- 
--	if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) {
-+	if (!ctx->valid_fmt) {
- 		ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl);
- 		if (ctx->valid_fmt) {
- 			struct v4l2_pix_format_mplane *pix_mp;
-@@ -156,6 +176,7 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = {
- 	},
- 	{
- 		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS,
-+		.cfg.ops = &rkvdec_ctrl_ops,
- 	},
- 	{
- 		.cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PPS,
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Wed, 14 Apr 2021 18:01:21 +0200
-Subject: [PATCH] WIP: media: rkvdec: hevc: Fix column width / row height
- calculation for no-tiled case
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- drivers/staging/media/rkvdec/rkvdec-hevc.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
-index 8ea2ad9f4f3a..58ae8a1a4ff3 100644
---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
-+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
-@@ -2165,9 +2165,9 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
- 		for (i = 0; i <= pps->num_tile_rows_minus1; i++)
- 			WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i));
- 	} else {
--		WRITE_PPS(round_up(sps->pic_width_in_luma_samples, ctb_size_y) - 1,
-+		WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1,
- 			  COLUMN_WIDTH(0));
--		WRITE_PPS(round_up(sps->pic_height_in_luma_samples, ctb_size_y) - 1,
-+		WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1,
- 			  ROW_HEIGHT(0));
- 	}
- 
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Wed, 14 Apr 2021 17:26:43 +0200
-Subject: [PATCH] WIP: media: rkvdec: hevc: fix long ref decoding
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- drivers/staging/media/rkvdec/rkvdec-hevc.c | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
-index 58ae8a1a4ff3..55bf61a84165 100644
---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
-+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
-@@ -2196,8 +2196,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
- #define REF_PIC_IDX_L1(i)			PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4)
- 
- #define LOWDELAY				PS_FIELD(182, 1)
--#define SHORT_TERM_REF_PIC_SET_SIZE		PS_FIELD(183, 10)
--#define LONG_TERM_REF_PIC_SET_SIZE		PS_FIELD(193, 9)
-+#define LONG_TERM_RPS_BIT_OFFSET		PS_FIELD(183, 10)
-+#define SHORT_TERM_RPS_BIT_OFFSET		PS_FIELD(193, 9)
- #define NUM_RPS_POC				PS_FIELD(202, 4)
- 
- 	for (j = 0; j < run->num_slices; j++) {
-@@ -2224,11 +2224,11 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
- 		// TODO: lowdelay
- 		WRITE_RPS(0, LOWDELAY);
- 
--		// NOTE: these two differs from mpp
-+		WRITE_RPS(sl_params->long_term_ref_pic_set_size +
-+			  sl_params->short_term_ref_pic_set_size,
-+			  LONG_TERM_RPS_BIT_OFFSET);
- 		WRITE_RPS(sl_params->short_term_ref_pic_set_size,
--			  SHORT_TERM_REF_PIC_SET_SIZE);
--		WRITE_RPS(sl_params->long_term_ref_pic_set_size,
--			  LONG_TERM_REF_PIC_SET_SIZE);
-+			  SHORT_TERM_RPS_BIT_OFFSET);
- 
- 		WRITE_RPS(decode_params->num_poc_st_curr_before +
- 			  decode_params->num_poc_st_curr_after +
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Thu, 15 Apr 2021 20:22:54 +0200
-Subject: [PATCH] WIP: media: rkvdec: hevc: implement lowdelay
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- drivers/staging/media/rkvdec/rkvdec-hevc.c | 11 +++++++++--
- 1 file changed, 9 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
-index 55bf61a84165..db33f9d357cf 100644
---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
-+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
-@@ -2187,6 +2187,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
- 	struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
- 	struct rkvdec_rps_packet *hw_ps;
- 	int i, j;
-+	unsigned int lowdelay;
- 
- #define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value)
- 
-@@ -2203,6 +2204,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
- 	for (j = 0; j < run->num_slices; j++) {
- 		sl_params = &run->slices_params[j];
- 		dpb = decode_params->dpb;
-+		lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1;
- 
- 		hw_ps = &priv_tbl->rps[j];
- 		memset(hw_ps, 0, sizeof(*hw_ps));
-@@ -2211,18 +2213,23 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
- 			WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR),
- 				  REF_PIC_LONG_TERM_L0(i));
- 			WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
-+
-+			if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt[0] > sl_params->slice_pic_order_cnt)
-+				lowdelay = 0;
- 		}
- 
- 		for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) {
- 			WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR),
- 				  REF_PIC_LONG_TERM_L1(i));
- 			WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
-+
-+			if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt[0] > sl_params->slice_pic_order_cnt)
-+				lowdelay = 0;
- 		}
- 
- 		//WRITE_RPS(0xffffffff, PS_FIELD(96, 32));
- 
--		// TODO: lowdelay
--		WRITE_RPS(0, LOWDELAY);
-+		WRITE_RPS(lowdelay, LOWDELAY);
- 
- 		WRITE_RPS(sl_params->long_term_ref_pic_set_size +
- 			  sl_params->short_term_ref_pic_set_size,
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Sat, 30 Jan 2021 18:16:39 +0100
-Subject: [PATCH] media: rkvdec: add variants support
-
-rkvdec IP has different versions which among others differ in
-the supported decoding formats.
-This adds an variant implementation in order support other
-than the currently supported RK3399 version.
-
-Note: Since matching of supported codecs is index-based the
-available codec options have been reordered here: from
-supported by all versions to not commonly supported. This seems
-the better soultion than duplicatiing code for every newly added IP.
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- drivers/staging/media/rkvdec/rkvdec.c | 104 ++++++++++++++++++--------
- drivers/staging/media/rkvdec/rkvdec.h |  10 +++
- 2 files changed, 84 insertions(+), 30 deletions(-)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
-index da32a6350344..4fb05e8b5a54 100644
---- a/drivers/staging/media/rkvdec/rkvdec.c
-+++ b/drivers/staging/media/rkvdec/rkvdec.c
-@@ -14,6 +14,7 @@
- #include <linux/interrupt.h>
- #include <linux/module.h>
- #include <linux/of.h>
-+#include <linux/of_device.h>
- #include <linux/platform_device.h>
- #include <linux/pm.h>
- #include <linux/pm_runtime.h>
-@@ -269,21 +270,6 @@ static const u32 rkvdec_vp9_decoded_fmts[] = {
- };
- 
- static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
--	{
--		.fourcc = V4L2_PIX_FMT_H264_SLICE,
--		.frmsize = {
--			.min_width = 48,
--			.max_width = 4096,
--			.step_width = 16,
--			.min_height = 48,
--			.max_height = 2304,
--			.step_height = 16,
--		},
--		.ctrls = &rkvdec_h264_ctrls,
--		.ops = &rkvdec_h264_fmt_ops,
--		.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
--		.decoded_fmts = rkvdec_h264_decoded_fmts,
--	},
- 	{
- 		.fourcc = V4L2_PIX_FMT_HEVC_SLICE,
- 		.frmsize = {
-@@ -298,6 +284,23 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
- 		.ops = &rkvdec_hevc_fmt_ops,
- 		.num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
- 		.decoded_fmts = rkvdec_hevc_decoded_fmts,
-+		.capability = RKVDEC_CAPABILITY_HEVC,
-+	},
-+	{
-+		.fourcc = V4L2_PIX_FMT_H264_SLICE,
-+		.frmsize = {
-+			.min_width = 48,
-+			.max_width = 4096,
-+			.step_width = 16,
-+			.min_height = 48,
-+			.max_height = 2304,
-+			.step_height = 16,
-+		},
-+		.ctrls = &rkvdec_h264_ctrls,
-+		.ops = &rkvdec_h264_fmt_ops,
-+		.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
-+		.decoded_fmts = rkvdec_h264_decoded_fmts,
-+		.capability = RKVDEC_CAPABILITY_H264,
- 	},
- 	{
- 		.fourcc = V4L2_PIX_FMT_VP9_FRAME,
-@@ -313,16 +316,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
- 		.ops = &rkvdec_vp9_fmt_ops,
- 		.num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts),
- 		.decoded_fmts = rkvdec_vp9_decoded_fmts,
--	}
-+		.capability = RKVDEC_CAPABILITY_VP9,
-+	},
- };
- 
- static const struct rkvdec_coded_fmt_desc *
--rkvdec_find_coded_fmt_desc(u32 fourcc)
-+rkvdec_default_coded_fmt_desc(unsigned int capabilities)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
-+		if (rkvdec_coded_fmts[i].capability & capabilities)
-+			return &rkvdec_coded_fmts[i];
-+	}
-+
-+	return NULL;
-+}
-+
-+static const struct rkvdec_coded_fmt_desc *
-+rkvdec_find_coded_fmt_desc(u32 fourcc, unsigned int capabilities)
- {
- 	unsigned int i;
- 
- 	for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
--		if (rkvdec_coded_fmts[i].fourcc == fourcc)
-+		if (rkvdec_coded_fmts[i].fourcc == fourcc &&
-+		    (rkvdec_coded_fmts[i].capability & capabilities))
- 			return &rkvdec_coded_fmts[i];
- 	}
- 
-@@ -345,7 +363,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx)
- {
- 	struct v4l2_format *f = &ctx->coded_fmt;
- 
--	ctx->coded_fmt_desc = &rkvdec_coded_fmts[0];
-+	ctx->coded_fmt_desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities);
- 	rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc);
- 
- 	f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
-@@ -372,11 +390,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv,
- 				  struct v4l2_frmsizeenum *fsize)
- {
- 	const struct rkvdec_coded_fmt_desc *fmt;
-+	struct rkvdec_dev *rkvdec = video_drvdata(file);
- 
- 	if (fsize->index != 0)
- 		return -EINVAL;
- 
--	fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format);
-+	fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format,
-+					 rkvdec->capabilities);
- 	if (!fmt)
- 		return -EINVAL;
- 
-@@ -447,10 +467,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv,
- 	struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
- 	const struct rkvdec_coded_fmt_desc *desc;
- 
--	desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat);
-+	desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat,
-+					  ctx->dev->capabilities);
- 	if (!desc) {
--		pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc;
--		desc = &rkvdec_coded_fmts[0];
-+		desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities);
-+		pix_mp->pixelformat = desc->fourcc;
- 	}
- 
- 	v4l2_apply_frmsize_constraints(&pix_mp->width,
-@@ -537,7 +558,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv,
- 	if (ret)
- 		return ret;
- 
--	desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat);
-+	desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat,
-+					  ctx->dev->capabilities);
- 	if (!desc)
- 		return -EINVAL;
- 	ctx->coded_fmt_desc = desc;
-@@ -585,7 +607,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv,
- static int rkvdec_enum_output_fmt(struct file *file, void *priv,
- 				  struct v4l2_fmtdesc *f)
- {
--	if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts))
-+	struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
-+
-+	if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts) ||
-+	    !(ctx->dev->capabilities & rkvdec_coded_fmts[f->index].capability))
- 		return -EINVAL;
- 
- 	f->pixelformat = rkvdec_coded_fmts[f->index].fourcc;
-@@ -993,14 +1018,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx)
- 	int ret;
- 
- 	for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++)
--		nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls;
-+		if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities)
-+			nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls;
- 
- 	v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls);
- 
- 	for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
--		ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls);
--		if (ret)
--			goto err_free_handler;
-+		if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) {
-+			ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls);
-+			if (ret)
-+				goto err_free_handler;
-+		}
- 	}
- 
- 	ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl);
-@@ -1204,8 +1232,17 @@ static void rkvdec_watchdog_func(struct work_struct *work)
- 	}
- }
- 
-+static const struct rkvdec_variant rk3399_rkvdec_variant = {
-+        .capabilities   = RKVDEC_CAPABILITY_H264 |
-+		           RKVDEC_CAPABILITY_HEVC |
-+			   RKVDEC_CAPABILITY_VP9
-+};
-+
- static const struct of_device_id of_rkvdec_match[] = {
--	{ .compatible = "rockchip,rk3399-vdec" },
-+	{
-+		.compatible = "rockchip,rk3399-vdec",
-+		.data = &rk3399_rkvdec_variant,
-+	},
- 	{ /* sentinel */ }
- };
- MODULE_DEVICE_TABLE(of, of_rkvdec_match);
-@@ -1218,6 +1255,7 @@ static int rkvdec_probe(struct platform_device *pdev)
- static int rkvdec_probe(struct platform_device *pdev)
- {
- 	struct rkvdec_dev *rkvdec;
-+	const struct rkvdec_variant *variant;
- 	unsigned int i;
- 	int ret, irq;
- 
-@@ -1243,6 +1281,12 @@ static int rkvdec_probe(struct platform_device *pdev)
- 	if (ret)
- 		return ret;
- 
-+	variant = of_device_get_match_data(rkvdec->dev);
-+	if (!variant)
-+		return -EINVAL;
-+
-+	rkvdec->capabilities = variant->capabilities;
-+
- 	/*
- 	 * Don't bump ACLK to max. possible freq. (500 MHz) to improve performance,
- 	 * since it will lead to non-recoverable decoder lockups in case of decoding
-diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
-index d60840c179a4..ac1e7d053f62 100644
---- a/drivers/staging/media/rkvdec/rkvdec.h
-+++ b/drivers/staging/media/rkvdec/rkvdec.h
-@@ -29,6 +29,10 @@
- 
- #define RKVDEC_RESET_DELAY	5
- 
-+#define RKVDEC_CAPABILITY_H264	BIT(0)
-+#define RKVDEC_CAPABILITY_HEVC	BIT(1)
-+#define RKVDEC_CAPABILITY_VP9	BIT(2)
-+
- struct rkvdec_ctx;
- 
- struct rkvdec_ctrl_desc {
-@@ -70,6 +74,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
- 			    base.vb.vb2_buf);
- }
- 
-+struct rkvdec_variant {
-+        unsigned int capabilities;
-+};
-+
- struct rkvdec_coded_fmt_ops {
- 	int (*adjust_fmt)(struct rkvdec_ctx *ctx,
- 			  struct v4l2_format *f);
-@@ -89,6 +97,7 @@ struct rkvdec_coded_fmt_desc {
- 	const struct rkvdec_coded_fmt_ops *ops;
- 	unsigned int num_decoded_fmts;
- 	const u32 *decoded_fmts;
-+	unsigned int capability;
- };
- 
- struct rkvdec_dev {
-@@ -103,6 +112,7 @@ struct rkvdec_dev {
- 	struct delayed_work watchdog_work;
- 	struct reset_control *rstc;
- 	u8 reset_mask;
-+	unsigned int capabilities;
- };
- 
- struct rkvdec_ctx {
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Sat, 30 Jan 2021 18:21:59 +0100
-Subject: [PATCH] media: rkvdec: add RK3288 variant
-
-This adds RK3288 variant to rkvdec driver. In this earlier version
-of the IP only HEVC decoding is supported.
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- drivers/staging/media/rkvdec/rkvdec.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
-index 4fb05e8b5a54..8767b1149009 100644
---- a/drivers/staging/media/rkvdec/rkvdec.c
-+++ b/drivers/staging/media/rkvdec/rkvdec.c
-@@ -1238,11 +1238,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = {
- 			   RKVDEC_CAPABILITY_VP9
- };
- 
-+static const struct rkvdec_variant rk3288_hevc_variant = {
-+        .capabilities   = RKVDEC_CAPABILITY_HEVC
-+};
-+
- static const struct of_device_id of_rkvdec_match[] = {
- 	{
- 		.compatible = "rockchip,rk3399-vdec",
- 		.data = &rk3399_rkvdec_variant,
- 	},
-+	{
-+		.compatible = "rockchip,rk3288-hevc",
-+		.data = &rk3288_hevc_variant,
-+	},
- 	{ /* sentinel */ }
- };
- MODULE_DEVICE_TABLE(of, of_rkvdec_match);
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Sat, 30 Jan 2021 18:27:30 +0100
-Subject: [PATCH] ARM: dts: RK3288: add hevc node
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- arch/arm/boot/dts/rk3288.dtsi | 21 ++++++++++++++++++++-
- 1 file changed, 20 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
-index 831484253e27..64b36cc8ef94 100644
---- a/arch/arm/boot/dts/rk3288.dtsi
-+++ b/arch/arm/boot/dts/rk3288.dtsi
-@@ -1252,6 +1252,25 @@ vpu_mmu: iommu@ff9a0800 {
- 		power-domains = <&power RK3288_PD_VIDEO>;
- 	};
- 
-+	hevc: hevc@ff9c0000 {
-+		compatible = "rockchip,rk3288-hevc";
-+		reg = <0x0 0xff9c0000 0x0 0x400>;
-+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-names = "irq_dec";
-+		clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CABAC>,
-+			 <&cru SCLK_HEVC_CORE>;
-+		clock-names = "axi", "ahb", "cabac", "core";
-+		assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
-+				   <&cru SCLK_HEVC_CORE>,
-+				   <&cru SCLK_HEVC_CABAC>;
-+		assigned-clock-rates = <400000000>, <100000000>,
-+				       <300000000>, <300000000>;
-+		iommus = <&hevc_mmu>;
-+		power-domains = <&power RK3288_PD_HEVC>;
-+		resets =  <&cru SRST_HEVC>;
-+		reset-names = "video_core";
-+	};
-+
- 	hevc_mmu: iommu@ff9c0440 {
- 		compatible = "rockchip,iommu";
- 		reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
-@@ -1260,7 +1279,7 @@ hevc_mmu: iommu@ff9c0440 {
- 		clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
- 		clock-names = "aclk", "iface";
- 		#iommu-cells = <0>;
--		status = "disabled";
-+		power-domains = <&power RK3288_PD_HEVC>;
- 	};
- 
- 	gpu: gpu@ffa30000 {
diff --git a/linux-4.7-intel-dvi-duallink.patch b/linux-4.7-intel-dvi-duallink.patch
deleted file mode 100644
index d02a9ad..0000000
--- a/linux-4.7-intel-dvi-duallink.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-diff -up linux-5.17/drivers/gpu/drm/i915/display/intel_hdmi.c.4~ linux-5.17/drivers/gpu/drm/i915/display/intel_hdmi.c
---- linux-5.17/drivers/gpu/drm/i915/display/intel_hdmi.c.4~	2022-03-26 17:10:30.108800943 +0100
-+++ linux-5.17/drivers/gpu/drm/i915/display/intel_hdmi.c	2022-03-26 17:12:42.514427378 +0100
-@@ -1939,14 +1939,14 @@ intel_hdmi_mode_clock_valid(struct drm_c
- 
- 	/* check if we can do 8bpc */
- 	status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 8, ycbcr420_output),
--				       true, has_hdmi_sink);
-+				       false, has_hdmi_sink);
- 
- 	/* if we can't do 8bpc we may still be able to do 12bpc */
- 	if (status != MODE_OK &&
- 	    intel_hdmi_source_bpc_possible(i915, 12) &&
- 	    intel_hdmi_sink_bpc_possible(connector, 12, has_hdmi_sink, ycbcr420_output))
- 		status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 12, ycbcr420_output),
--					       true, has_hdmi_sink);
-+					       false, has_hdmi_sink);
- 
- 	/* if we can't do 8,12bpc we may still be able to do 10bpc */
- 	if (status != MODE_OK &&
diff --git a/linux-5.11-arm64-lld-no-gc-sections.patch b/linux-5.11-arm64-lld-no-gc-sections.patch
deleted file mode 100644
index 09c53db..0000000
--- a/linux-5.11-arm64-lld-no-gc-sections.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- linux-5.11/arch/arm64/Makefile.21~	2021-02-14 22:32:24.000000000 +0000
-+++ linux-5.11/arch/arm64/Makefile	2021-03-30 11:40:06.453377536 +0000
-@@ -127,6 +127,7 @@
- 
- ifeq ($(CONFIG_LD_IS_LLD), y)
- KBUILD_LDFLAGS	+= -z norelro
-+KBUILD_LDFLAGS	+= --no-gc-sections
- endif
- 
- CHECKFLAGS	+= -D__aarch64__
diff --git a/linux-5.11-disable-ICF-for-CONFIG_UNWINDER_ORC.patch b/linux-5.11-disable-ICF-for-CONFIG_UNWINDER_ORC.patch
index 55eb035..ad7d26e 100644
--- a/linux-5.11-disable-ICF-for-CONFIG_UNWINDER_ORC.patch
+++ b/linux-5.11-disable-ICF-for-CONFIG_UNWINDER_ORC.patch
@@ -1,8 +1,8 @@
-diff -up linux-5.19/scripts/Makefile.8~ linux-5.19/scripts/Makefile
---- linux-5.19/scripts/Makefile.8~	2022-08-01 21:19:18.131885545 +0200
-+++ linux-5.19/scripts/Makefile	2022-08-01 21:22:58.109685458 +0200
-@@ -13,6 +13,7 @@ hostprogs-always-$(CONFIG_SYSTEM_EXTRA_C
- 
+diff -up linux-6.19-rc4/scripts/Makefile.9~ linux-6.19-rc4/scripts/Makefile
+--- linux-6.19-rc4/scripts/Makefile.9~	2026-01-04 23:41:55.000000000 +0100
++++ linux-6.19-rc4/scripts/Makefile	2026-01-10 15:37:32.024037877 +0100
+@@ -33,6 +33,7 @@ HOSTCFLAGS_tracepoint-update.o = -I$(src
+ HOSTCFLAGS_elf-parse.o = -I$(srctree)/tools/include
  HOSTCFLAGS_sorttable.o = -I$(srctree)/tools/include
  HOSTLDLIBS_sorttable = -lpthread
 +HOSTLDFLAGS_sorttable = --icf=none
diff --git a/linux-5.11-perf-compile.patch b/linux-5.11-perf-compile.patch
index cf27bbb..26e0d56 100644
--- a/linux-5.11-perf-compile.patch
+++ b/linux-5.11-perf-compile.patch
@@ -1,37 +1,28 @@
-diff -up linux-6.0-rc1/tools/build/feature/test-libcrypto.c.27~ linux-6.0-rc1/tools/build/feature/test-libcrypto.c
---- linux-6.0-rc1/tools/build/feature/test-libcrypto.c.27~	2022-08-15 14:13:01.431464502 +0200
-+++ linux-6.0-rc1/tools/build/feature/test-libcrypto.c	2022-08-15 14:13:45.940978564 +0200
-@@ -1,4 +1,5 @@
- // SPDX-License-Identifier: GPL-2.0
-+#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
- #include <openssl/evp.h>
- #include <openssl/sha.h>
- #include <openssl/md5.h>
-diff -up linux-6.0-rc1/tools/build/feature/test-libperl.c.27~ linux-6.0-rc1/tools/build/feature/test-libperl.c
---- linux-6.0-rc1/tools/build/feature/test-libperl.c.27~	2022-08-15 00:50:18.000000000 +0200
-+++ linux-6.0-rc1/tools/build/feature/test-libperl.c	2022-08-15 14:13:01.431464502 +0200
+diff -up linux-6.14-rc2/tools/build/feature/test-libperl.c.35~ linux-6.14-rc2/tools/build/feature/test-libperl.c
+--- linux-6.14-rc2/tools/build/feature/test-libperl.c.35~	2025-02-09 21:45:03.000000000 +0100
++++ linux-6.14-rc2/tools/build/feature/test-libperl.c	2025-02-15 02:48:04.730592736 +0100
 @@ -1,4 +1,5 @@
  // SPDX-License-Identifier: GPL-2.0
 +#pragma GCC diagnostic ignored "-Wcompound-token-split-by-macro"
  #include <EXTERN.h>
  #include <perl.h>
  
-diff -up linux-6.0-rc1/tools/perf/Makefile.config.27~ linux-6.0-rc1/tools/perf/Makefile.config
---- linux-6.0-rc1/tools/perf/Makefile.config.27~	2022-08-15 00:50:18.000000000 +0200
-+++ linux-6.0-rc1/tools/perf/Makefile.config	2022-08-15 14:13:01.432464491 +0200
-@@ -126,6 +126,11 @@ ifdef LIBUNWIND_DIR
+diff -up linux-6.14-rc2/tools/perf/Makefile.config.35~ linux-6.14-rc2/tools/perf/Makefile.config
+--- linux-6.14-rc2/tools/perf/Makefile.config.35~	2025-02-09 21:45:03.000000000 +0100
++++ linux-6.14-rc2/tools/perf/Makefile.config	2025-02-15 02:51:40.247270425 +0100
+@@ -114,6 +114,11 @@ ifdef LIBUNWIND_DIR
    LIBUNWIND_LDFLAGS = -L$(LIBUNWIND_DIR)/lib
-   LIBUNWIND_ARCHS = x86 x86_64 arm aarch64 debug-frame-arm debug-frame-aarch64
+   LIBUNWIND_ARCHS = x86 x86_64 arm aarch64 debug-frame-arm debug-frame-aarch64 loongarch
    $(foreach libunwind_arch,$(LIBUNWIND_ARCHS),$(call libunwind_arch_set_flags,$(libunwind_arch)))
 +else
 +  LIBUNWIND_CFLAGS  = -I/usr/include/libunwind
 +  LIBUNWIND_LDFLAGS = -L/usr/lib64/libunwind
-+  LIBUNWIND_ARCHS = x86 x86_64 arm aarch64 debug-frame-arm debug-frame-aarch64
++  LIBUNWIND_ARCHS = x86 x86_64 arm aarch64 debug-frame-arm debug-frame-aarch64 loongarch
 +  $(foreach libunwind_arch,$(LIBUNWIND_ARCHS),$(call libunwind_arch_set_flags,$(libunwind_arch)))
  endif
  
- # Set per-feature check compilation flags
-@@ -1099,11 +1104,15 @@ ifndef NO_AUXTRACE
+ ifndef NO_LIBUNWIND
+@@ -1115,11 +1120,15 @@ ifdef EXTRA_TESTS
  endif
  
  ifndef NO_JVMTI
@@ -51,11 +42,11 @@ diff -up linux-6.0-rc1/tools/perf/Makefile.config.27~ linux-6.0-rc1/tools/perf/M
      endif
    endif
    ifndef JDIR
-diff -up linux-6.0-rc1/tools/perf/Makefile.perf.27~ linux-6.0-rc1/tools/perf/Makefile.perf
---- linux-6.0-rc1/tools/perf/Makefile.perf.27~	2022-08-15 00:50:18.000000000 +0200
-+++ linux-6.0-rc1/tools/perf/Makefile.perf	2022-08-15 14:13:01.432464491 +0200
-@@ -444,6 +444,11 @@ arch_asm_uapi_dir := $(srctree)/tools/ar
- x86_arch_asm_uapi_dir := $(srctree)/tools/arch/x86/include/uapi/asm/
+diff -up linux-6.14-rc2/tools/perf/Makefile.perf.35~ linux-6.14-rc2/tools/perf/Makefile.perf
+--- linux-6.14-rc2/tools/perf/Makefile.perf.35~	2025-02-09 21:45:03.000000000 +0100
++++ linux-6.14-rc2/tools/perf/Makefile.perf	2025-02-15 02:48:04.730786222 +0100
+@@ -553,6 +553,11 @@ asm_generic_uapi_dir := $(srctree)/tools
+ arch_asm_uapi_dir := $(srctree)/tools/arch/$(SRCARCH)/include/uapi/asm/
  x86_arch_asm_dir := $(srctree)/tools/arch/x86/include/asm/
  
 +ifeq ($(ARCH),x86)
@@ -65,4 +56,4 @@ diff -up linux-6.0-rc1/tools/perf/Makefile.perf.27~ linux-6.0-rc1/tools/perf/Mak
 +
  beauty_outdir := $(OUTPUT)trace/beauty/generated
  beauty_ioctl_outdir := $(beauty_outdir)/ioctl
- drm_ioctl_array := $(beauty_ioctl_outdir)/drm_ioctl_array.c
+ 
diff --git a/linux-5.19-prefer-amdgpu-over-radeon.patch b/linux-5.19-prefer-amdgpu-over-radeon.patch
index 3b2640e..d77eb8b 100644
--- a/linux-5.19-prefer-amdgpu-over-radeon.patch
+++ b/linux-5.19-prefer-amdgpu-over-radeon.patch
@@ -1,19 +1,18 @@
-diff -up linux-5.19/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.omv~ linux-5.19/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
---- linux-5.19/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.omv~	2022-09-10 21:20:04.053588398 +0200
-+++ linux-5.19/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c	2022-09-10 23:22:04.094361596 +0200
-@@ -558,18 +558,13 @@ module_param_named(timeout_period, amdgp
+diff -up linux-6.9-rc1/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.28~ linux-6.9-rc1/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+--- linux-6.9-rc1/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.28~	2024-03-25 12:27:48.258221857 +0100
++++ linux-6.9-rc1/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c	2024-03-25 12:29:26.903747981 +0100
+@@ -589,18 +589,12 @@ module_param_named(timeout_period, amdgp
  /**
   * DOC: si_support (int)
   * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
 - * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
 - * otherwise using amdgpu driver.
-+ * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using
-+ * the amdgpu driver.
++ * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using amdgpu driver.
   */
  #ifdef CONFIG_DRM_AMDGPU_SI
  
--#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
--int amdgpu_si_support = 0;
+-#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
+-int amdgpu_si_support;
 -MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
 -#else
  int amdgpu_si_support = 1;
@@ -22,19 +21,18 @@ diff -up linux-5.19/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.omv~ linux-5.19/driv
  
  module_param_named(si_support, amdgpu_si_support, int, 0444);
  #endif
-@@ -577,18 +572,13 @@ module_param_named(si_support, amdgpu_si
+@@ -608,18 +602,12 @@ module_param_named(si_support, amdgpu_si
  /**
   * DOC: cik_support (int)
   * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
 - * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
 - * otherwise using amdgpu driver.
-+ * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using
-+ * the amdgpu driver.
++ * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using amdgpu driver.
   */
  #ifdef CONFIG_DRM_AMDGPU_CIK
  
--#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
--int amdgpu_cik_support = 0;
+-#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
+-int amdgpu_cik_support;
 -MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
 -#else
  int amdgpu_cik_support = 1;
@@ -43,10 +41,10 @@ diff -up linux-5.19/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.omv~ linux-5.19/driv
  
  module_param_named(cik_support, amdgpu_cik_support, int, 0444);
  #endif
-diff -up linux-5.19/drivers/gpu/drm/radeon/radeon_drv.c.omv~ linux-5.19/drivers/gpu/drm/radeon/radeon_drv.c
---- linux-5.19/drivers/gpu/drm/radeon/radeon_drv.c.omv~	2022-09-10 23:22:12.934195195 +0200
-+++ linux-5.19/drivers/gpu/drm/radeon/radeon_drv.c	2022-09-10 23:22:29.469884268 +0200
-@@ -272,11 +272,11 @@ module_param_named(uvd, radeon_uvd, int,
+diff -up linux-6.9-rc1/drivers/gpu/drm/radeon/radeon_drv.c.28~ linux-6.9-rc1/drivers/gpu/drm/radeon/radeon_drv.c
+--- linux-6.9-rc1/drivers/gpu/drm/radeon/radeon_drv.c.28~	2024-03-24 22:10:05.000000000 +0100
++++ linux-6.9-rc1/drivers/gpu/drm/radeon/radeon_drv.c	2024-03-25 12:27:48.258221857 +0100
+@@ -239,11 +239,11 @@ module_param_named(uvd, radeon_uvd, int,
  MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
  module_param_named(vce, radeon_vce, int, 0444);
  
diff --git a/linux-5.2.9-riscv-compile.patch b/linux-5.2.9-riscv-compile.patch
deleted file mode 100644
index fb95ed9..0000000
--- a/linux-5.2.9-riscv-compile.patch
+++ /dev/null
@@ -1,12 +0,0 @@
-diff -up linux-5.2/kernel/sched/idle.c.omv~ linux-5.2/kernel/sched/idle.c
---- linux-5.2/kernel/sched/idle.c.omv~	2019-08-25 02:14:47.476014750 +0000
-+++ linux-5.2/kernel/sched/idle.c	2019-08-25 02:15:21.765410702 +0000
-@@ -8,6 +8,8 @@
-  */
- #include "sched.h"
- 
-+#include <asm/pgalloc.h>
-+
- #include <trace/events/power.h>
- 
- /* Linker adds these: start and end of __cpuidle functions */
diff --git a/linux-5.4.5-fix-build.patch b/linux-5.4.5-fix-build.patch
deleted file mode 100644
index 8eec13d..0000000
--- a/linux-5.4.5-fix-build.patch
+++ /dev/null
@@ -1,9 +0,0 @@
-diff -up linux-5.4/include/linux/sched/deadline.h.omv~ linux-5.4/include/linux/sched/deadline.h
---- linux-5.4/include/linux/sched/deadline.h.omv~	2019-12-19 00:17:43.772470648 +0100
-+++ linux-5.4/include/linux/sched/deadline.h	2019-12-19 00:20:27.757462692 +0100
-@@ -1,4 +1,5 @@
- /* SPDX-License-Identifier: GPL-2.0 */
-+#pragma once
- 
- /*
-  * SCHED_DEADLINE tasks has negative priorities, reflecting
diff --git a/linux-5.5-corsair-strafe-quirks.patch b/linux-5.5-corsair-strafe-quirks.patch
index 56d9ffe..c98bb61 100644
--- a/linux-5.5-corsair-strafe-quirks.patch
+++ b/linux-5.5-corsair-strafe-quirks.patch
@@ -1,7 +1,7 @@
-diff -up linux-5.5/drivers/hid/hid-ids.h.omv~ linux-5.5/drivers/hid/hid-ids.h
---- linux-5.5/drivers/hid/hid-ids.h.omv~	2020-02-13 15:44:42.401817937 +0100
-+++ linux-5.5/drivers/hid/hid-ids.h	2020-02-13 15:45:29.512814852 +0100
-@@ -310,6 +310,7 @@
+diff -up linux-6.7-rc1/drivers/hid/hid-ids.h.12~ linux-6.7-rc1/drivers/hid/hid-ids.h
+--- linux-6.7-rc1/drivers/hid/hid-ids.h.12~	2023-11-13 01:19:07.000000000 +0100
++++ linux-6.7-rc1/drivers/hid/hid-ids.h	2023-11-13 02:08:19.372320145 +0100
+@@ -326,6 +326,7 @@
  #define USB_DEVICE_ID_CORSAIR_K70RGB_RAPIDFIRE  0x1b38
  #define USB_DEVICE_ID_CORSAIR_K65RGB_RAPIDFIRE  0x1b39
  #define USB_DEVICE_ID_CORSAIR_SCIMITAR_PRO_RGB  0x1b3e
@@ -9,9 +9,9 @@ diff -up linux-5.5/drivers/hid/hid-ids.h.omv~ linux-5.5/drivers/hid/hid-ids.h
  
  #define USB_VENDOR_ID_CREATIVELABS	0x041e
  #define USB_DEVICE_ID_CREATIVE_SB_OMNI_SURROUND_51	0x322c
-diff -up linux-5.5/drivers/hid/hid-quirks.c.omv~ linux-5.5/drivers/hid/hid-quirks.c
---- linux-5.5/drivers/hid/hid-quirks.c.omv~	2020-02-13 15:46:19.977811548 +0100
-+++ linux-5.5/drivers/hid/hid-quirks.c	2020-02-13 15:46:22.903811356 +0100
+diff -up linux-6.7-rc1/drivers/hid/hid-quirks.c.12~ linux-6.7-rc1/drivers/hid/hid-quirks.c
+--- linux-6.7-rc1/drivers/hid/hid-quirks.c.12~	2023-11-13 02:08:19.372320145 +0100
++++ linux-6.7-rc1/drivers/hid/hid-quirks.c	2023-11-13 02:09:09.127748719 +0100
 @@ -64,6 +64,7 @@ static const struct hid_device_id hid_qu
  	{ HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_GLAIVE_RGB), HID_QUIRK_NO_INIT_REPORTS | HID_QUIRK_ALWAYS_POLL },
  	{ HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_SCIMITAR_PRO_RGB), HID_QUIRK_NO_INIT_REPORTS | HID_QUIRK_ALWAYS_POLL },
@@ -19,4 +19,4 @@ diff -up linux-5.5/drivers/hid/hid-quirks.c.omv~ linux-5.5/drivers/hid/hid-quirk
 +	{ HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_STRAFE_2), HID_QUIRK_NO_INIT_REPORTS | HID_QUIRK_ALWAYS_POLL },
  	{ HID_USB_DEVICE(USB_VENDOR_ID_CREATIVELABS, USB_DEVICE_ID_CREATIVE_SB_OMNI_SURROUND_51), HID_QUIRK_NOGET },
  	{ HID_USB_DEVICE(USB_VENDOR_ID_DELL, USB_DEVICE_ID_DELL_PIXART_USB_OPTICAL_MOUSE), HID_QUIRK_ALWAYS_POLL },
- 	{ HID_USB_DEVICE(USB_VENDOR_ID_DMI, USB_DEVICE_ID_DMI_ENC), HID_QUIRK_NOGET },
+ 	{ HID_USB_DEVICE(USB_VENDOR_ID_DELL, USB_DEVICE_ID_DELL_PRO_WIRELESS_KM5221W), HID_QUIRK_ALWAYS_POLL },
diff --git a/linux-5.6-fix-disassembler-4args-detection.patch b/linux-5.6-fix-disassembler-4args-detection.patch
deleted file mode 100644
index 36aa382..0000000
--- a/linux-5.6-fix-disassembler-4args-detection.patch
+++ /dev/null
@@ -1,13 +0,0 @@
-diff -up linux-5.6/tools/bpf/bpftool/jit_disasm.c.omv~ linux-5.6/tools/bpf/bpftool/jit_disasm.c
-diff -up linux-5.6/tools/build/feature/Makefile.omv~ linux-5.6/tools/build/feature/Makefile
---- linux-5.6/tools/build/feature/Makefile.omv~	2020-04-02 06:07:08.488570621 +0200
-+++ linux-5.6/tools/build/feature/Makefile	2020-04-02 06:07:19.983631490 +0200
-@@ -224,7 +224,7 @@ $(OUTPUT)test-libbfd.bin:
- 	$(BUILD) -DPACKAGE='"perf"' -lbfd -ldl
- 
- $(OUTPUT)test-disassembler-four-args.bin:
--	$(BUILD) -DPACKAGE='"perf"' -lbfd -lopcodes
-+	$(BUILD) -DPACKAGE='"perf"' -lbfd -ldl -lopcodes
- 
- $(OUTPUT)test-reallocarray.bin:
- 	$(BUILD)
diff --git a/linux-6.1-binutils-2.40.patch b/linux-6.1-binutils-2.40.patch
new file mode 100644
index 0000000..4ac9b0b
--- /dev/null
+++ b/linux-6.1-binutils-2.40.patch
@@ -0,0 +1,12 @@
+diff -up linux-6.1/scripts/pahole-flags.sh.omv~ linux-6.1/scripts/pahole-flags.sh
+--- linux-6.1/scripts/pahole-flags.sh.omv~	2023-01-27 22:34:46.096264581 +0100
++++ linux-6.1/scripts/pahole-flags.sh	2023-01-27 22:34:55.373347079 +0100
+@@ -19,5 +19,8 @@ fi
+ if [ "${pahole_ver}" -ge "122" ]; then
+ 	extra_paholeopt="${extra_paholeopt} -j"
+ fi
++if [ "${pahole_ver}" -ge "124" ]; then
++	extra_paholeopt="${extra_paholeopt} --lang_exclude asm"
++fi
+ 
+ echo ${extra_paholeopt}
diff --git a/linux-6.18-clang.patch b/linux-6.18-clang.patch
new file mode 100644
index 0000000..c1273b2
--- /dev/null
+++ b/linux-6.18-clang.patch
@@ -0,0 +1,12 @@
+diff -up linux-6.18-rc3/drivers/acpi/acpica/tbprint.c.omv~ linux-6.18-rc3/drivers/acpi/acpica/tbprint.c
+--- linux-6.18-rc3/drivers/acpi/acpica/tbprint.c.omv~	2025-10-30 05:35:41.759465914 +0100
++++ linux-6.18-rc3/drivers/acpi/acpica/tbprint.c	2025-10-30 05:35:48.494365250 +0100
+@@ -96,7 +96,7 @@ acpi_tb_print_table_header(acpi_physical
+ 	struct acpi_table_header local_header;
+ 
+ #pragma GCC diagnostic push
+-#if defined(__GNUC__) && __GNUC__ >= 11
++#if defined(__GNUC__) && __GNUC__ >= 11 && !defined(__clang__)
+ #pragma GCC diagnostic ignored "-Wstringop-overread"
+ #endif
+ 
diff --git a/linux-6.19-acpi-clang.patch b/linux-6.19-acpi-clang.patch
new file mode 100644
index 0000000..3621fb4
--- /dev/null
+++ b/linux-6.19-acpi-clang.patch
@@ -0,0 +1,21 @@
+diff -up linux-6.19/drivers/acpi/acpica/utdebug.c.omv~ linux-6.19/drivers/acpi/acpica/utdebug.c
+--- linux-6.19/drivers/acpi/acpica/utdebug.c.omv~	2026-02-09 22:31:03.977397827 +0000
++++ linux-6.19/drivers/acpi/acpica/utdebug.c	2026-02-09 22:31:19.617460291 +0000
+@@ -38,7 +38,7 @@ void acpi_ut_init_stack_ptr_trace(void)
+ 	acpi_size current_sp;
+ 
+ #pragma GCC diagnostic push
+-#if defined(__GNUC__) && __GNUC__ >= 12
++#if defined(__GNUC__) && __GNUC__ >= 12 && !defined(__clang__)
+ #pragma GCC diagnostic ignored "-Wdangling-pointer="
+ #endif
+ 	acpi_gbl_entry_stack_pointer = &current_sp;
+@@ -63,7 +63,7 @@ void acpi_ut_track_stack_ptr(void)
+ 
+ 	if (&current_sp < acpi_gbl_lowest_stack_pointer) {
+ #pragma GCC diagnostic push
+-#if defined(__GNUC__) && __GNUC__ >= 12
++#if defined(__GNUC__) && __GNUC__ >= 12 && !defined(__clang__)
+ #pragma GCC diagnostic ignored "-Wdangling-pointer="
+ #endif
+ 		acpi_gbl_lowest_stack_pointer = &current_sp;
diff --git a/linux-6.7-BTF-deps.patch b/linux-6.7-BTF-deps.patch
new file mode 100644
index 0000000..764a4ea
--- /dev/null
+++ b/linux-6.7-BTF-deps.patch
@@ -0,0 +1,11 @@
+diff -up linux-7.0-rc1/lib/Kconfig.debug.4~ linux-7.0-rc1/lib/Kconfig.debug
+--- linux-7.0-rc1/lib/Kconfig.debug.4~	2026-02-22 22:18:59.000000000 +0100
++++ linux-7.0-rc1/lib/Kconfig.debug	2026-02-23 04:38:47.136227200 +0100
+@@ -398,7 +398,6 @@ config DEBUG_INFO_SPLIT
+ config DEBUG_INFO_BTF
+ 	bool "Generate BTF type information"
+ 	depends on !DEBUG_INFO_SPLIT && !DEBUG_INFO_REDUCED
+-	depends on !GCC_PLUGIN_RANDSTRUCT || COMPILE_TEST
+ 	depends on BPF_SYSCALL
+ 	depends on PAHOLE_VERSION >= 122
+ 	# pahole uses elfutils, which does not have support for Hexagon relocations
diff --git a/linux-7.0.tar.sign b/linux-7.0.tar.sign
new file mode 100644
index 0000000..1213294
--- /dev/null
+++ b/linux-7.0.tar.sign
@@ -0,0 +1,19 @@
+-----BEGIN PGP SIGNATURE-----
+Comment: This signature is for the .tar version of the archive
+Comment: git archive --format tar --prefix=linux-7.0/ v7.0
+Comment: git version 2.53.0
+
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+IX+p1Icb/3qvrV0wZeYehq7vJWetWwBUVjcL/sNX4wktY+GFQoNGXCmqDXXhxNOl
+9uXK+qkg34tWHCz01yAwPwBmRcbfh6TMMhIYbDxG7wtJazntc4i7LUeh7+T7mbs9
+Gdi9xn3wO8LHOoyJUC7zt+hG0E2TAtfalxSAqHYo7/pqVNi/IFFrvU8Rd9kJNFNj
+xJ5mVSN3RTSzvExg1KTLDmxJ2AY+Uq2HvM5OOHyDq/mgZqdl+TXXcnOhcA6b5GPx
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+e2yj3jYqgwealcvO2UzgHv9ZWlyt2hw/U2hA/UJvyfvGRBFPvzM=
+=Z8As
+-----END PGP SIGNATURE-----
diff --git a/loongarch-omv-defconfig b/loongarch-omv-defconfig
new file mode 100644
index 0000000..4aba62d
--- /dev/null
+++ b/loongarch-omv-defconfig
@@ -0,0 +1,2237 @@
+CONFIG_16KB_3LEVEL=y
+CONFIG_64BIT=y
+CONFIG_8139CP=m
+CONFIG_8139TOO=m
+CONFIG_8139TOO_PIO=y
+CONFIG_842_COMPRESS=m
+CONFIG_842_DECOMPRESS=m
+CONFIG_9P_FS=y
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_BATTERY=y
+CONFIG_ACPI_BGRT=y
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_CONTAINER=y
+CONFIG_ACPI_CPU_FREQ_PSS=y
+CONFIG_ACPI_DOCK=y
+CONFIG_ACPI_FAN=y
+CONFIG_ACPI_GENERIC_GSI=y
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_HOTPLUG_MEMORY=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_ACPI_IPMI=m
+CONFIG_ACPI_MCFG=y
+CONFIG_ACPI_MDIO=y
+CONFIG_ACPI_NUMA=y
+CONFIG_ACPI_PCI_SLOT=y
+CONFIG_ACPI_PPTT=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_SLEEP=y
+CONFIG_ACPI_SPCR_TABLE=y
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+CONFIG_ACPI_TABLE_UPGRADE=y
+CONFIG_ACPI_TAD=y
+CONFIG_ACPI_THERMAL_LIB=y
+CONFIG_ACPI_THERMAL=y
+CONFIG_ACPI_VIDEO=y
+CONFIG_ACPI=y
+CONFIG_AF_UNIX_OOB=y
+CONFIG_AHCI_DWC=y
+CONFIG_ALLOW_DEV_COREDUMP=y
+CONFIG_AMD_QDMA=m
+CONFIG_APERTURE_HELPERS=y
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_DISABLE_KASAN_INLINE=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_ARCH_ENABLE_THP_MIGRATION=y
+CONFIG_ARCH_FORCE_MAX_ORDER=11
+CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
+CONFIG_ARCH_HAS_CPU_FINALIZE_INIT=y
+CONFIG_ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION=y
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MEMORY_PROBE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS=12
+CONFIG_ARCH_MMAP_RND_BITS_MAX=18
+CONFIG_ARCH_MMAP_RND_BITS_MIN=12
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SELECTS_CRASH_DUMP=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_STRICT_ALIGN=y
+CONFIG_ARCH_SUPPORTS_ACPI=y
+CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y
+CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
+CONFIG_ARCH_SUPPORTS_KEXEC=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_USE_MEMREMAP_PROT=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
+CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP=y
+CONFIG_ARCH_WANT_PMD_MKWRITE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_AS_HAS_NON_CONST_ULEB128=y
+CONFIG_AS_IS_GNU=y
+CONFIG_AS_VERSION=24200
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_ASYNC_XOR=m
+CONFIG_ATA_ACPI=y
+CONFIG_ATA_FORCE=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_ATA=y
+CONFIG_ATH9K_BTCOEX_SUPPORT=y
+CONFIG_ATH9K_COMMON=m
+CONFIG_ATH9K_HTC=m
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K=m
+CONFIG_ATH9K_PCI=y
+CONFIG_ATH9K_PCOEM=y
+CONFIG_ATH9K_RFKILL=y
+CONFIG_ATH_COMMON=m
+CONFIG_AUDIT_GENERIC=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT=y
+CONFIG_AUTOFS_FS=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BCACHE=m
+CONFIG_BCM2712_MIP=m
+CONFIG_BFQ_GROUP_IOSCHED=y
+CONFIG_BINFMT_MISC=m
+CONFIG_BLK_CGROUP_FC_APPID=y
+CONFIG_BLK_CGROUP_IOCOST=y
+CONFIG_BLK_CGROUP_IOLATENCY=y
+CONFIG_BLK_CGROUP_IOPRIO=y
+CONFIG_BLK_CGROUP_PUNT_BIO=y
+CONFIG_BLK_CGROUP_RWSTAT=y
+CONFIG_BLK_CGROUP=y
+CONFIG_BLK_DEBUG_FS=y
+CONFIG_BLK_DEBUG_FS_ZONED=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_BLK_DEV_DRBD=m
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RBD=m
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_THROTTLING_LOW=y
+CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BLK_DEV_ZONED_LOOP=m
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_ICQ=y
+CONFIG_BLK_MQ_STACKING=y
+CONFIG_BLK_RQ_ALLOC_TIME=y
+CONFIG_BLK_WBT_MQ=y
+CONFIG_BLK_WBT=y
+CONFIG_BLOCK_HOLDER_DEPRECATED=y
+CONFIG_BLOCK_LEGACY_AUTOLOAD=y
+CONFIG_BNX2=y
+CONFIG_BONDING=m
+CONFIG_BPF_STREAM_PARSER=y
+CONFIG_BPF_UNPRIV_DEFAULT_OFF=y
+CONFIG_BQL=y
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_IP6=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_NETFILTER=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BSD_DISKLABEL=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BTREE=y
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_BTRFS_FS=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUG=y
+CONFIG_BUILD_SALT=""
+CONFIG_CACHEFILES=m
+CONFIG_CARDBUS=y
+CONFIG_CC_CAN_LINK_STATIC=y
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
+CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
+CONFIG_CC_HAS_INT128=y
+CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
+CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_IS_GCC=y
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CC_NO_STRINGOP_OVERFLOW=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+CONFIG_CC_VERSION_TEXT="gcc (GCC) 13.2.1 20240330 (OpenMandriva)"
+CONFIG_CDROM=y
+CONFIG_CEC_NXP_TDA9950=m
+CONFIG_CEPH_FSCACHE=y
+CONFIG_CEPH_FS=m
+CONFIG_CEPH_FS_POSIX_ACL=y
+CONFIG_CEPH_FS_SECURITY_LABEL=y
+CONFIG_CEPH_LIB=m
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_CFG80211=m
+CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
+CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CGROUP_MISC=y
+CONFIG_CGROUP_NET_CLASSID=y
+CONFIG_CGROUP_NET_PRIO=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_RDMA=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_WRITEBACK=y
+CONFIG_CHARGER_BQ24190=m
+CONFIG_CHELSIO_INLINE_CRYPTO=y
+CONFIG_CHELSIO_T1_1G=y
+CONFIG_CHELSIO_T1=m
+CONFIG_CHELSIO_T3=m
+CONFIG_CHELSIO_T4=m
+CONFIG_CHR_DEV_SCH=m
+CONFIG_CHR_DEV_SG=y
+CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
+CONFIG_CIFS=m
+CONFIG_CIFS_STATS2=y
+CONFIG_CLANG_VERSION=0
+CONFIG_CLOSURES=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=19
+CONFIG_CMA_SIZE_MBYTES=0
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+CONFIG_CMA_SYSFS=y
+CONFIG_CMA=y
+CONFIG_CMDLINE=""
+CONFIG_CMDLINE_BOOTLOADER=y
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_COMEDI_8254=m
+CONFIG_COMEDI_8255=m
+CONFIG_COMEDI_8255_PCI=m
+CONFIG_COMEDI_ADL_PCI6208=m
+CONFIG_COMEDI_ADL_PCI7250=m
+CONFIG_COMEDI_ADL_PCI7X3X=m
+CONFIG_COMEDI_ADL_PCI8164=m
+CONFIG_COMEDI_ADL_PCI9111=m
+CONFIG_COMEDI_ADL_PCI9118=m
+CONFIG_COMEDI_ADV_PCI1710=m
+CONFIG_COMEDI_ADV_PCI1720=m
+CONFIG_COMEDI_ADV_PCI1723=m
+CONFIG_COMEDI_ADV_PCI1724=m
+CONFIG_COMEDI_ADV_PCI1760=m
+CONFIG_COMEDI_ADV_PCI_DIO=m
+CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
+CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
+CONFIG_COMEDI=m
+CONFIG_COMEDI_MITE=m
+CONFIG_COMEDI_NI_LABPC=m
+CONFIG_COMEDI_NI_LABPC_PCI=m
+CONFIG_COMEDI_NI_PCIDIO=m
+CONFIG_COMEDI_NI_PCIMIO=m
+CONFIG_COMEDI_NI_ROUTING=m
+CONFIG_COMEDI_NI_TIOCMD=m
+CONFIG_COMEDI_NI_TIO=m
+CONFIG_COMEDI_PCI_DRIVERS=m
+CONFIG_COMMON_CLK_LOONGSON2=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPUFREQ_DT=m
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_HAS_FPU=y
+CONFIG_CPU_HAS_LASX=y
+CONFIG_CPU_HAS_LBT=y
+CONFIG_CPU_HAS_LSX=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_PM=y
+CONFIG_CRAMFS_BLOCKDEV=y
+CONFIG_CRAMFS=m
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DM_CRYPT=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC64=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRYPTO_842=m
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_BLAKE2B=y
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_CAST_COMMON=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CHACHA20=m
+CONFIG_CRYPTO_CHACHA20POLY1305=m
+CONFIG_CRYPTO_CMAC=m
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32_LOONGARCH=m
+CONFIG_CRYPTO_CRC32=m
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_DEV_LOONGSON_RNG=m
+CONFIG_CRYPTO_DEV_VIRTIO=m
+CONFIG_CRYPTO_DH=y
+CONFIG_CRYPTO_DRBG=m
+CONFIG_CRYPTO_DRBG_MENU=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECC=m
+CONFIG_CRYPTO_ECDH=m
+CONFIG_CRYPTO_ECHAINIV=m
+CONFIG_CRYPTO_ENGINE=m
+CONFIG_CRYPTO_ESSIV=m
+CONFIG_CRYPTO_GENIV=m
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY=m
+CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64
+CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32
+CONFIG_CRYPTO_JITTERENTROPY_OSR=1
+CONFIG_CRYPTO_KDF800108_CTR=y
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_KPP=y
+CONFIG_CRYPTO_LIB_AES=m
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_GF128MUL=m
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZ4HC=m
+CONFIG_CRYPTO_LZ4=m
+CONFIG_CRYPTO_LZO=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_NULL2=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_PCRYPT=m
+CONFIG_CRYPTO_POLY1305=m
+CONFIG_CRYPTO_RNG_DEFAULT=m
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA3=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_SIG2=y
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_USER_API_AEAD=m
+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API=m
+CONFIG_CRYPTO_USER_API_RNG=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_XXHASH=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CUSE=m
+CONFIG_CXD2880_SPI_DRV=m
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_FS_ALLOW_ALL=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_INFO_NONE=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MISC=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DEFAULT_CUBIC=y
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_DEV_COREDUMP=y
+CONFIG_DEV_DAX_KMEM=m
+CONFIG_DEV_DAX=m
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+CONFIG_DEVICE_PRIVATE=y
+CONFIG_DIMLIB=y
+CONFIG_DLM=m
+CONFIG_DMA_ACPI=y
+CONFIG_DMABUF_HEAPS_CMA_LEGACY=y
+CONFIG_DMABUF_HEAPS_CMA=y
+CONFIG_DMABUF_HEAPS_SYSTEM=y
+CONFIG_DMABUF_HEAPS=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_NUMA_CMA=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DM_CACHE=m
+CONFIG_DM_CACHE_SMQ=m
+CONFIG_DM_CRYPT=m
+CONFIG_DMIID=y
+CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
+CONFIG_DMI=y
+CONFIG_DM_MIRROR=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_PCACHE=m
+CONFIG_DM_RAID=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_WRITECACHE=m
+CONFIG_DM_ZERO=m
+CONFIG_DNOTIFY=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_DRM_AMD_DC_FP=y
+CONFIG_DRM_AMD_DC=y
+CONFIG_DRM_AMDGPU_CIK=y
+CONFIG_DRM_AMDGPU=m
+CONFIG_DRM_AMDGPU_SI=y
+CONFIG_DRM_AMDGPU_USERPTR=y
+CONFIG_DRM_AMD_ISP=y
+CONFIG_DRM_APPLETBDRM=m
+CONFIG_DRM_AST=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_BUDDY=m
+CONFIG_DRM_CLIENT_DEFAULT_FBDEV=y
+CONFIG_DRM_DISPLAY_DP_AUX_CEC=y
+CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV=y
+CONFIG_DRM_DISPLAY_DP_HELPER=y
+CONFIG_DRM_DISPLAY_HDCP_HELPER=y
+CONFIG_DRM_DISPLAY_HDMI_HELPER=y
+CONFIG_DRM_DISPLAY_HELPER=m
+CONFIG_DRM_EFIDRM=m
+CONFIG_DRM_EXEC=m
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_GEM_SHMEM_HELPER=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_LOONGSON=y
+CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER=m
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_HIMAX_HX83102=m
+CONFIG_DRM_PANEL_LG_SW43408=m
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01=m
+CONFIG_DRM_PANEL_SITRONIX_ST7701=m
+CONFIG_DRM_PANEL_SUMMIT=m
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANIC_BACKGROUND_COLOR=0x000000
+CONFIG_DRM_PANIC_FOREGROUND_COLOR=0xa0a0a0
+CONFIG_DRM_PANIC_SCREEN="user"
+CONFIG_DRM_PANIC=y
+CONFIG_DRM_PIXPAPER=m
+CONFIG_DRM_QXL=m
+CONFIG_DRM_RADEON=m
+CONFIG_DRM_RADEON_USERPTR=y
+CONFIG_DRM_SCHED=m
+CONFIG_DRM_SOLOMON_SSD2825=m
+CONFIG_DRM_SUBALLOC_HELPER=m
+CONFIG_DRM_TTM_HELPER=m
+CONFIG_DRM_TTM=y
+CONFIG_DRM_VIRTIO_GPU_KMS=y
+CONFIG_DRM_VIRTIO_GPU=m
+CONFIG_DRM_WAVESHARE_BRIDGE=m
+CONFIG_DRM=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE_ROWS=25
+CONFIG_DUMMY=y
+CONFIG_DVB_A8293=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_AF9033=m
+CONFIG_DVB_ASCOT2E=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_AU8522_DTV=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_AU8522_V4L=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_BT8XX=m
+CONFIG_DVB_CORE=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_CX24117=m
+CONFIG_DVB_CX24120=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_CXD2099=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_CXD2841ER=m
+CONFIG_DVB_CXD2880=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_DIB9000=m
+CONFIG_DVB_DRX39XYJ=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_DYNAMIC_MINORS=y
+CONFIG_DVB_EC100=m
+CONFIG_DVB_HELENE=m
+CONFIG_DVB_HORUS3A=m
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6422=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_LG2160=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_LGDT3306A=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGS8GL5=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_LNBH25=m
+CONFIG_DVB_LNBH29=m
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_M88DS3103=m
+CONFIG_DVB_M88RS2000=m
+CONFIG_DVB_MAX_ADAPTERS=16
+CONFIG_DVB_MB86A16=m
+CONFIG_DVB_MB86A20S=m
+CONFIG_DVB_MN88443X=m
+CONFIG_DVB_MN88472=m
+CONFIG_DVB_MN88473=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_MXL5XX=m
+CONFIG_DVB_MXL692=m
+CONFIG_DVB_NET=y
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_PLL=m
+CONFIG_DVB_RTL2830=m
+CONFIG_DVB_RTL2832=m
+CONFIG_DVB_RTL2832_SDR=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_S5H1411=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_S5H1432=m
+CONFIG_DVB_S921=m
+CONFIG_DVB_SI2165=m
+CONFIG_DVB_SI2168=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_SP2=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STV0297=m
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV0910=m
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV6110x=m
+CONFIG_DVB_STV6111=m
+CONFIG_DVB_TAS2101=m
+CONFIG_DVB_TC90522=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_TDA10071=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA18271C2DD=m
+CONFIG_DVB_TDA665x=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TS2020=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_ZD1301_DEMOD=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_LOONGSON=y
+CONFIG_E1000E=y
+CONFIG_E1000=y
+CONFIG_ECRYPT_FS=m
+CONFIG_ECRYPT_FS_MESSAGING=y
+CONFIG_EDAC_ECS=y
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC_LOONGSON=m
+CONFIG_EDAC=m
+CONFIG_EDAC_MEM_REPAIR=y
+CONFIG_EDAC_SCRUB=y
+CONFIG_EEPROM_AT24=m
+CONFIG_EFI_BOOTLOADER_CONTROL=m
+CONFIG_EFI_CAPSULE_LOADER=m
+CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_GENERIC_STUB=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_SBAT_FILE=""
+CONFIG_EFI_STUB=y
+CONFIG_EFI_TEST=m
+CONFIG_EFIVAR_FS=m
+CONFIG_EFI_VARS_PSTORE=m
+CONFIG_EFI=y
+CONFIG_EFI_ZBOOT=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_EROFS_FS=m
+CONFIG_EROFS_FS_PCPU_KTHREAD_HIPRI=y
+CONFIG_EROFS_FS_PCPU_KTHREAD=y
+CONFIG_EROFS_FS_POSIX_ACL=y
+CONFIG_EROFS_FS_SECURITY=y
+CONFIG_EROFS_FS_XATTR=y
+CONFIG_EROFS_FS_ZIP_LZMA=y
+CONFIG_EROFS_FS_ZIP=y
+CONFIG_ETHERNET=y
+CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
+CONFIG_EXFAT_FS=m
+CONFIG_EXPERT=y
+CONFIG_EXPORTFS_BLOCK_OPS=y
+CONFIG_EXPORTFS=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON_FSA9480=m
+CONFIG_EXTCON_GPIO=m
+CONFIG_EXTCON_LC824206XA=m
+CONFIG_EXTCON_MAX14526=m
+CONFIG_EXTCON_MAX3355=m
+CONFIG_EXTCON_PTN5150=m
+CONFIG_EXTCON_RT8973A=m
+CONFIG_EXTCON_SM5502=m
+CONFIG_EXTCON_USBC_TUSB320=m
+CONFIG_EXTCON_USB_GPIO=m
+CONFIG_F2FS_CHECK_FS=y
+CONFIG_F2FS_FS_COMPRESSION=y
+CONFIG_F2FS_FS_LZ4HC=y
+CONFIG_F2FS_FS_LZ4=y
+CONFIG_F2FS_FS_LZORLE=y
+CONFIG_F2FS_FS_LZO=y
+CONFIG_F2FS_FS=m
+CONFIG_F2FS_FS_POSIX_ACL=y
+CONFIG_F2FS_FS_SECURITY=y
+CONFIG_F2FS_FS_XATTR=y
+CONFIG_F2FS_FS_ZSTD=y
+CONFIG_F2FS_IOSTAT=y
+CONFIG_F2FS_STAT_FS=y
+CONFIG_FAILOVER=m
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_FANOTIFY=y
+CONFIG_FAT_DEFAULT_CODEPAGE=936
+CONFIG_FAT_DEFAULT_IOCHARSET="gb2312"
+CONFIG_FAT_FS=m
+CONFIG_FB_BACKLIGHT=y
+CONFIG_FB_CORE=y
+CONFIG_FB_DDC=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DEVICE=y
+CONFIG_FB_EFI=y
+CONFIG_FB_IOMEM_FOPS=y
+CONFIG_FB_IOMEM_HELPERS=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_RADEON_BACKLIGHT=y
+CONFIG_FB_RADEON_I2C=y
+CONFIG_FB_RADEON=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FB_SYSMEM_FOPS=y
+CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
+CONFIG_FB_SYSMEM_HELPERS=y
+CONFIG_FCOE=m
+CONFIG_FIB_RULES=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FIRMWARE_TABLE=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FRAME_WARN=2048
+CONFIG_FSCACHE=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FSNOTIFY=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FS_STACK=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FUSE_FS=m
+CONFIG_FW_LOADER_COMPRESS_XZ=y
+CONFIG_FW_LOADER_COMPRESS=y
+CONFIG_FW_LOADER_COMPRESS_ZSTD=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_GARP=m
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GCC_NO_STRINGOP_OVERFLOW=y
+CONFIG_GCC_VERSION=130201
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_DEVICES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_ENTRY=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_VDSO_TIME_NS=y
+CONFIG_GFS2_FS_LOCKING_DLM=y
+CONFIG_GFS2_FS=m
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIO_ADP5585=m
+CONFIG_GPIO_CDEV_V1=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_LOONGSON_64BIT=y
+CONFIG_GPIO_SYSFS_LEGACY=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GRACE_PERIOD=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HDMI=y
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION_COMP_LZ4=y
+CONFIG_HIBERNATION_SNAPSHOT_DEV=y
+CONFIG_HIBERNATION=y
+CONFIG_HMM_MIRROR=y
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_HOTPLUG_PCI_SHPC=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HSA_AMD_SVM=y
+CONFIG_HSA_AMD=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HWMON_VID=m
+CONFIG_HW_RANDOM_VIRTIO=m
+CONFIG_HW_RANDOM=y
+CONFIG_HZ=250
+CONFIG_HZ_250=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_ARB_GPIO_CHALLENGE=m
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DEMUX_PINCTRL=m
+CONFIG_I2C_DESIGNWARE_CORE=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_LS2X=y
+CONFIG_I2C_MUX_GPIO=m
+CONFIG_I2C_MUX_GPMUX=m
+CONFIG_I2C_MUX_LTC4306=m
+CONFIG_I2C_MUX_MLXCPLD=m
+CONFIG_I2C_MUX_MULE=m
+CONFIG_I2C_MUX_PCA9541=m
+CONFIG_I2C_MUX_PCA954x=m
+CONFIG_I2C_MUX_PINCTRL=m
+CONFIG_I2C_MUX_REG=m
+CONFIG_I2C_PIIX4=y
+CONFIG_I2C_SLAVE_EEPROM=m
+CONFIG_I2C_SLAVE_TESTUNIT=m
+CONFIG_I2C_USBIO=m
+CONFIG_I2C=y
+CONFIG_I2C_ZHAOXIN=m
+CONFIG_IGB_HWMON=y
+CONFIG_IGB=y
+CONFIG_INET6_ESP=m
+CONFIG_INET_DIAG=y
+CONFIG_INET_ESP=m
+CONFIG_INET_MPTCP_DIAG=y
+CONFIG_INET_SCTP_DIAG=m
+CONFIG_INET_TABLE_PERTURB_ORDER=16
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_UDP_DIAG=y
+CONFIG_INET=y
+CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
+CONFIG_INFINIBAND_ADDR_TRANS=y
+CONFIG_INFINIBAND_BNXT_RE=m
+CONFIG_INFINIBAND_IONIC=m
+CONFIG_INFINIBAND_IRDMA=m
+CONFIG_INFINIBAND=m
+CONFIG_INFINIBAND_VIRT_DMA=y
+CONFIG_INIT_STACK_ALL_ZERO=y
+CONFIG_INOTIFY_USER=y
+CONFIG_INPUT_AW86927=m
+CONFIG_INPUT_CS40L50_VIBRA=m
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_IBM_PANEL=m
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_MAX7360_ROTARY=m
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_SPARSEKMAP=y
+CONFIG_INPUT_UINPUT=m
+CONFIG_INPUT_VIVALDIFMAP=y
+CONFIG_INTEGRITY_AUDIT=y
+CONFIG_INTEGRITY=y
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+CONFIG_IOSCHED_BFQ=y
+CONFIG_IO_WQ=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
+CONFIG_IP6_NF_NAT=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP6_NF_SECURITY=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_TARGET_SYNPROXY=m
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IPE_BOOT_POLICY=""
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_DMI_DECODE=y
+CONFIG_IPMI_HANDLER=m
+CONFIG_IPMI_IPMB=m
+CONFIG_IPMI_LS2K=y
+CONFIG_IPMI_PLAT_DATA=y
+CONFIG_IPMI_SI=m
+CONFIG_IP_MROUTE_COMMON=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_SECURITY=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_SYNPROXY=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_IP_PNP=y
+CONFIG_IP_ROUTE_CLASSID=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_SCTP=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_MAX=256
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_SIT=y
+CONFIG_IPV6=y
+CONFIG_IPVLAN_L3S=y
+CONFIG_IPVLAN=m
+CONFIG_IP_VS_IPV6=y
+CONFIG_IP_VS=m
+CONFIG_IP_VS_MH_TAB_INDEX=12
+CONFIG_IP_VS_NFCT=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_SCTP=y
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_SH_TAB_BITS=8
+CONFIG_IP_VS_TAB_BITS=12
+CONFIG_IP_VS_WRR=m
+CONFIG_IR_IMON_DECODER=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IRQ_BYPASS_MANAGER=m
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
+CONFIG_IRQ_LOONGARCH_CPU=y
+CONFIG_IRQ_POLL=y
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IR_SHARP_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_XMP_DECODER=m
+CONFIG_ISCSI_BOOT_SYSFS=m
+CONFIG_ISCSI_TARGET=m
+CONFIG_ISCSI_TCP=m
+CONFIG_ISO9660_FS=y
+CONFIG_IWLDVM=m
+CONFIG_IWLMLD=m
+CONFIG_IWLMVM=m
+CONFIG_IWLWIFI_LEDS=y
+CONFIG_IWLWIFI=m
+CONFIG_IWLWIFI_OPMODE_MODULAR=y
+CONFIG_IXGBE_HWMON=y
+CONFIG_IXGBE=y
+CONFIG_JBD2=y
+CONFIG_JFS_FS=m
+CONFIG_JFS_POSIX_ACL=y
+CONFIG_JFS_SECURITY=y
+CONFIG_JOLIET=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KCMP=y
+CONFIG_KERNEL_GZIP=y
+CONFIG_KERNFS=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEXEC_FILE=y
+CONFIG_KEXEC=y
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEY_DH_OPERATIONS=y
+CONFIG_KSM=y
+CONFIG_KVM=m
+CONFIG_L1_CACHE_SHIFT=6
+CONFIG_L2TP_ETH=m
+CONFIG_L2TP_IP=m
+CONFIG_L2TP=m
+CONFIG_L2TP_V3=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_PLATFORM=m
+CONFIG_LD_IS_LLD=y
+CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
+CONFIG_LD_ORPHAN_WARN=y
+CONFIG_LD_VERSION=0
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CROS_EC=m
+CONFIG_LEDS_LP8864=m
+CONFIG_LEDS_TRIGGER_AUDIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEGACY_DIRECT_IO=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_TIOCSTI=y
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFC=m
+CONFIG_LIBFCOE=m
+CONFIG_LIBFDT=y
+CONFIG_LIBWX=y
+CONFIG_LIRC=y
+CONFIG_LLC2=m
+CONFIG_LLC=m
+CONFIG_LLD_VERSION=180105
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCKD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCK_MM_AND_FIND_VMA=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO=y
+CONFIG_LOONGARCH_PLATFORM_DEVICES=y
+CONFIG_LOONGARCH=y
+CONFIG_LOONGSON2_APB_DMA=m
+CONFIG_LOONGSON2_GUTS=y
+CONFIG_LOONGSON2_PM=y
+CONFIG_LOONGSON2_THERMAL=m
+CONFIG_LOONGSON3_CPUFREQ=m
+CONFIG_LOONGSON_EIOINTC=y
+CONFIG_LOONGSON_HTVEC=y
+CONFIG_LOONGSON_LAPTOP=y
+CONFIG_LOONGSON_LIOINTC=y
+CONFIG_LOONGSON_PCH_LPC=y
+CONFIG_LOONGSON_PCH_MSI=y
+CONFIG_LOONGSON_PCH_PIC=y
+CONFIG_LOOPBACK_TARGET=m
+CONFIG_LRU_CACHE=m
+CONFIG_LS2X_APB_DMA=y
+CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,bpf"
+CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_LTO_NONE=y
+CONFIG_LZ4_COMPRESS=m
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_LZ4HC_COMPRESS=m
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_MAC80211=m
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MACH_LOONGSON64=y
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
+CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MANAGER_SBS=m
+CONFIG_MARVELL_10G_PHY=y
+CONFIG_MAX_SKB_FRAGS=17
+CONFIG_MD_BITMAP_FILE=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_GPIO=m
+CONFIG_MDIO_I2C=y
+CONFIG_MDIO=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID456=m
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CEC_RC=y
+CONFIG_MEDIA_CEC_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_PCI_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_TEST_SUPPORT=y
+CONFIG_MEDIA_TUNER_AV201X=m
+CONFIG_MEDIA_TUNER_E4000=m
+CONFIG_MEDIA_TUNER_FC0011=m
+CONFIG_MEDIA_TUNER_FC0012=m
+CONFIG_MEDIA_TUNER_FC0013=m
+CONFIG_MEDIA_TUNER_FC2580=m
+CONFIG_MEDIA_TUNER_IT913X=m
+CONFIG_MEDIA_TUNER=m
+CONFIG_MEDIA_TUNER_M88RS6000T=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MSI001=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2063=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2131=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_MXL301RF=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_QM1D1B0004=m
+CONFIG_MEDIA_TUNER_QM1D1C0042=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_R820T=m
+CONFIG_MEDIA_TUNER_SI2157=m
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_STV6120=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TDA18250=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_MEGARAID_LEGACY=y
+CONFIG_MEGARAID_MAILBOX=y
+CONFIG_MEGARAID_MM=y
+CONFIG_MEGARAID_NEWGEN=y
+CONFIG_MEGARAID_SAS=y
+CONFIG_MEMCG_KMEM=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y
+CONFIG_MEMORY_HOTPLUG=y
+CONFIG_MEMORY_HOTREMOVE=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_88PM886_PMIC=y
+CONFIG_MFD_LOONGSON_SE=m
+CONFIG_MFD_MAX7360=m
+CONFIG_MFD_MAX77759=m
+CONFIG_MFD_QNAP_MCU=m
+CONFIG_MFD_ROHM_BD96801=m
+CONFIG_MFD_SEC_ACPM=m
+CONFIG_MFD_SEC_I2C=m
+CONFIG_MFD_SYSCON=y
+CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO=y
+CONFIG_MII=y
+CONFIG_MINIX_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_MLX5_VFIO_PCI=m
+CONFIG_MMU_GATHER_MERGE_VMAS=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_PIXART=y
+CONFIG_MOUSE_PS2_SENTELIC=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_SERIAL=m
+CONFIG_MPLS=y
+CONFIG_MPTCP_IPV6=y
+CONFIG_MPTCP=y
+CONFIG_MQ_IOSCHED_KYBER=y
+CONFIG_MRP=m
+CONFIG_MSDOS_FS=m
+CONFIG_MT7601U=m
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI=m
+CONFIG_MTD_CFI_STAA=m
+CONFIG_MTD_CFI_UTIL=m
+CONFIG_MTD_GEN_PROBE=m
+CONFIG_MTD_INTEL_DG=m
+CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD=m
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_OF_PARTS=m
+CONFIG_MTD_PSTORE=m
+CONFIG_MTD_RAM=m
+CONFIG_MTD_ROM=m
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI=m
+CONFIG_MTD_UBI_NVMEM=m
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUX_ADG792A=m
+CONFIG_MUX_ADGS1408=m
+CONFIG_MUX_GPIO=m
+CONFIG_MUX_MMIO=m
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_NET_9P_FD=y
+CONFIG_NET_9P_USBG=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_NET_9P=y
+CONFIG_NET_ACT_BPF=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_NAT=m
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_BPF=m
+CONFIG_NET_CLS_CGROUP=m
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_NET_CLS=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FAILOVER=m
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_NETFILTER_BPF_LINK=y
+CONFIG_NETFILTER_CONNCOUNT=m
+CONFIG_NETFILTER_EGRESS=y
+CONFIG_NETFILTER_FAMILY_ARP=y
+CONFIG_NETFILTER_FAMILY_BRIDGE=y
+CONFIG_NETFILTER_INGRESS=y
+CONFIG_NETFILTER_NETLINK_ACCT=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_OSF=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_SKIP_EGRESS=y
+CONFIG_NETFILTER_SYNPROXY=m
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_CONNMARK=m
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
+CONFIG_NETFILTER_XT_MATCH_CGROUP=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_CPU=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ECN=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_IPVS=m
+CONFIG_NETFILTER_XT_MATCH_L2TP=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_NETFILTER_XT_NAT=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_AUDIT=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CT=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
+CONFIG_NETFILTER_XT_TARGET_NETMAP=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NETFS_SUPPORT=y
+CONFIG_NET_HANDSHAKE=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_NET_IPGRE_DEMUX=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPIP=m
+CONFIG_NET_IP_TUNNEL=y
+CONFIG_NET_KEY=y
+CONFIG_NET_L3_MASTER_DEV=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_NET_MPLS_GSO=m
+CONFIG_NET_NSH=m
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_FIFO=y
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_UDP_TUNNEL=y
+CONFIG_NET_VENDOR_ADI=y
+CONFIG_NET_VENDOR_ASIX=y
+CONFIG_NET_VENDOR_BROADCOM=y
+CONFIG_NET_VENDOR_CADENCE=y
+CONFIG_NET_VENDOR_CHELSIO=y
+CONFIG_NET_VENDOR_CORTINA=y
+CONFIG_NET_VENDOR_DAVICOM=y
+CONFIG_NET_VENDOR_ENGLEDER=y
+CONFIG_NET_VENDOR_FUJITSU=y
+CONFIG_NET_VENDOR_FUNGIBLE=y
+CONFIG_NET_VENDOR_GOOGLE=y
+CONFIG_NET_VENDOR_HUAWEI=y
+CONFIG_NET_VENDOR_INTEL=y
+CONFIG_NET_VENDOR_LITEX=y
+CONFIG_NET_VENDOR_MICROCHIP=y
+CONFIG_NET_VENDOR_MICROSEMI=y
+CONFIG_NET_VENDOR_MICROSOFT=y
+CONFIG_NET_VENDOR_NETERION=y
+CONFIG_NET_VENDOR_NI=y
+CONFIG_NET_VENDOR_PACKET_ENGINES=y
+CONFIG_NET_VENDOR_PENSANDO=y
+CONFIG_NET_VENDOR_REALTEK=y
+CONFIG_NET_VENDOR_SOCIONEXT=y
+CONFIG_NET_VENDOR_STMICRO=y
+CONFIG_NET_VENDOR_SYNOPSYS=y
+CONFIG_NET_VENDOR_VERTEXCOM=y
+CONFIG_NET_VENDOR_WANGXUN=y
+CONFIG_NET_VENDOR_XIRCOM=y
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NETWORK_PHY_TIMESTAMPING=y
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NET_XGRESS=y
+CONFIG_NET=y
+CONFIG_NEW_LEDS=y
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_LABELS=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_OVS=y
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_DUP_IPV4=m
+CONFIG_NF_LOG_IPV6=m
+CONFIG_NF_LOG_SYSLOG=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_MASQUERADE=y
+CONFIG_NF_NAT_OVS=y
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_REDIRECT=y
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_REJECT_IPV4=m
+CONFIG_NF_REJECT_IPV6=m
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_NFSD_BLOCKLAYOUT=y
+CONFIG_NFS_DISABLE_UDP_SUPPORT=y
+CONFIG_NFSD_PNFS=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4_DELEG_TIMESTAMPS=y
+CONFIG_NFSD_V4=y
+CONFIG_NFSD=y
+CONFIG_NFS_FS=y
+CONFIG_NF_SOCKET_IPV4=m
+CONFIG_NF_SOCKET_IPV6=m
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFS_V2=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2_READ_PLUS=y
+CONFIG_NFS_V4_2_SSC_HELPER=y
+CONFIG_NFS_V4_2=y
+CONFIG_NFS_V4_SECURITY_LABEL=y
+CONFIG_NFS_V4=y
+CONFIG_NF_TABLES_ARP=y
+CONFIG_NF_TABLES_BRIDGE=m
+CONFIG_NF_TABLES_IPV4=y
+CONFIG_NF_TABLES_IPV6=y
+CONFIG_NF_TABLES=m
+CONFIG_NFT_COMPAT=m
+CONFIG_NFT_CONNLIMIT=m
+CONFIG_NFT_DUP_IPV4=m
+CONFIG_NFT_FIB_IPV4=m
+CONFIG_NFT_FIB=m
+CONFIG_NFT_HASH=m
+CONFIG_NFT_LIMIT=m
+CONFIG_NFT_LOG=m
+CONFIG_NFT_MASQ=m
+CONFIG_NFT_NAT=m
+CONFIG_NFT_OSF=m
+CONFIG_NF_TPROXY_IPV4=m
+CONFIG_NF_TPROXY_IPV6=m
+CONFIG_NFT_QUEUE=m
+CONFIG_NFT_QUOTA=m
+CONFIG_NFT_REDIR=m
+CONFIG_NFT_REJECT_IPV4=m
+CONFIG_NFT_REJECT_IPV6=m
+CONFIG_NFT_REJECT=m
+CONFIG_NFT_SOCKET=m
+CONFIG_NFT_TPROXY=m
+CONFIG_NFT_TUNNEL=m
+CONFIG_NGBE=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_UCS2_UTILS=m
+CONFIG_NLS_UTF8=y
+CONFIG_NLS=y
+CONFIG_NODES_SHIFT=6
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NO_HZ=y
+CONFIG_NR_CPUS=256
+CONFIG_NTB_EPF=m
+CONFIG_NTB_IDT=m
+CONFIG_NTB=m
+CONFIG_NTB_MSI=y
+CONFIG_NTB_PERF=m
+CONFIG_NTB_SWITCHTEC=m
+CONFIG_NTB_TRANSPORT=m
+CONFIG_NTFS3_64BIT_CLUSTER=y
+CONFIG_NTFS3_FS=m
+CONFIG_NTFS3_LZX_XPRESS=y
+CONFIG_NTSYNC=m
+CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
+CONFIG_NUMA_BALANCING=y
+CONFIG_NUMA_KEEP_MEMINFO=y
+CONFIG_NUMA=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OCFS2_DEBUG_MASKLOG=y
+CONFIG_OCFS2_FS=m
+CONFIG_OCFS2_FS_O2CB=m
+CONFIG_OCFS2_FS_STATS=y
+CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OF=y
+CONFIG_OPENVSWITCH_GRE=m
+CONFIG_OPENVSWITCH=m
+CONFIG_OPENVSWITCH_VXLAN=m
+CONFIG_ORANGEFS_FS=m
+CONFIG_OVERLAY_FS_INDEX=y
+CONFIG_OVERLAY_FS_METACOPY=y
+CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
+CONFIG_OVERLAY_FS_REDIRECT_DIR=y
+CONFIG_OVERLAY_FS_XINO_AUTO=y
+CONFIG_OVERLAY_FS=y
+CONFIG_OVPN=m
+CONFIG_PACKET=y
+CONFIG_PADATA=y
+CONFIG_PAGE_BLOCK_MAX_ORDER=11
+CONFIG_PAGE_BLOCK_ORDER=11
+CONFIG_PAGE_SIZE_16KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_VERSION=125
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PARAVIRT=y
+CONFIG_PARPORT_PC_FIFO=y
+CONFIG_PARPORT_PC=y
+CONFIG_PARPORT_SERIAL=y
+CONFIG_PARPORT=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PATA_ATIIXP=y
+CONFIG_PATA_PCMCIA=m
+CONFIG_PATA_TIMINGS=y
+CONFIG_PCCARD=m
+CONFIG_PCCARD_NONSTATIC=y
+CONFIG_PCI_ATS=y
+CONFIG_PCI_DOE=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCIEAER=y
+CONFIG_PCIE_BUS_DEFAULT=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCIE_PME=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_LABEL=y
+CONFIG_PCI_LOONGSON=y
+CONFIG_PCI_MSI_ARCH_FALLBACKS=y
+CONFIG_PCI_P2PDMA=y
+CONFIG_PCI_SW_SWITCHTEC=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA=m
+CONFIG_PCPU_DEV_REFCNT=y
+CONFIG_PCS_XPCS=y
+CONFIG_PDS_VFIO_PCI=m
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_3LEVEL=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_AMDISP=m
+CONFIG_PINCTRL_LOONGSON2=y
+CONFIG_PINCTRL_MAX7360=m
+CONFIG_PINCTRL=y
+CONFIG_PINMUX=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_PM_OPP=y
+CONFIG_PM_STD_PARTITION=""
+CONFIG_PNFS_BLOCK=y
+CONFIG_PNFS_FILE_LAYOUT=y
+CONFIG_PNFS_FLEXFILE_LAYOUT=y
+CONFIG_PNPACPI=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+CONFIG_PNP=y
+CONFIG_POWER_RESET_RESTART=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOATM=m
+CONFIG_PPPOE_HASH_BITS=4
+CONFIG_PPPOE_HASH_BITS_4=y
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPS=y
+CONFIG_PPTP=m
+CONFIG_PREEMPT_BUILD=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_PREEMPT_DYNAMIC=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_RCU=y
+CONFIG_PREEMPT=y
+CONFIG_PRINTER=m
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PSTORE_COMPRESS=y
+CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
+CONFIG_PSTORE=m
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_NETC_V4_TIMER=m
+CONFIG_PWM_ADP5585=m
+CONFIG_PWM_AXI_PWMGEN=m
+CONFIG_PWM_GPIO=m
+CONFIG_PWM_LOONGSON=m
+CONFIG_PWM_MAX7360=m
+CONFIG_PWM_PROVIDE_GPIO=y
+CONFIG_PWM_SYSFS=y
+CONFIG_PWM=y
+CONFIG_QAT_VFIO_PCI=m
+CONFIG_QCA807X_PHY=m
+CONFIG_QCA808X_PHY=m
+CONFIG_QCA83XX_PHY=m
+CONFIG_QEDF=m
+CONFIG_QFMT_V1=m
+CONFIG_QFMT_V2=m
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTACTL=y
+CONFIG_QUOTA_TREE=m
+CONFIG_QUOTA=y
+CONFIG_R8169_LEDS=y
+CONFIG_R8169=y
+CONFIG_RADIO_ADAPTERS=m
+CONFIG_RADIO_TEA575X=m
+CONFIG_RAID6_PQ_BENCHMARK=y
+CONFIG_RAID6_PQ=y
+CONFIG_RAID_ATTRS=y
+CONFIG_RANDOMIZE_BASE_MAX_OFFSET=0x01000000
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y
+CONFIG_RAPIDIO_CHMAN=m
+CONFIG_RAPIDIO_DISC_TIMEOUT=30
+CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y
+CONFIG_RAPIDIO_ENUM_BASIC=m
+CONFIG_RAPIDIO_MPORT_CDEV=m
+CONFIG_RAPIDIO_TSI721=y
+CONFIG_RAPIDIO=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RC_CORE=m
+CONFIG_RC_DECODERS=y
+CONFIG_RC_MAP=m
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_RCU_TRACE=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RDS=y
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REBOOT_MODE=y
+CONFIG_REGMAP_I2C=m
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=m
+CONFIG_RELAY=y
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL=m
+CONFIG_RFS_ACCEL=y
+CONFIG_RIONET=m
+CONFIG_RIONET_RX_SIZE=128
+CONFIG_RIONET_TX_SIZE=128
+CONFIG_ROHM_BD79112=m
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+CONFIG_ROMFS_FS=m
+CONFIG_ROMFS_ON_BLOCK=y
+CONFIG_ROOT_NFS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+CONFIG_RPS=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_LEDS=y
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00=m
+CONFIG_RTC_DRV_EFI=y
+CONFIG_RTC_DRV_LOONGSON=y
+CONFIG_RTC_DRV_NCT6694=m
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_RTL8188EE=m
+CONFIG_RTL8192C_COMMON=m
+CONFIG_RTL8192CE=m
+CONFIG_RTL8192CU=m
+CONFIG_RTL8192DE=m
+CONFIG_RTL8192DU=m
+CONFIG_RTL8192EE=m
+CONFIG_RTL8192SE=m
+CONFIG_RTL8723AE=m
+CONFIG_RTL8723BE=m
+CONFIG_RTL8723_COMMON=m
+CONFIG_RTL8821AE=m
+CONFIG_RTL8XXXU=m
+CONFIG_RTLBTCOEXIST=m
+CONFIG_RTL_CARDS=m
+CONFIG_RTLWIFI=m
+CONFIG_RTLWIFI_PCI=m
+CONFIG_RTLWIFI_USB=m
+CONFIG_RTW88_8723DE=m
+CONFIG_RTW88_8723D=m
+CONFIG_RTW88_8821CE=m
+CONFIG_RTW88_8821C=m
+CONFIG_RTW88_8822BE=m
+CONFIG_RTW88_8822B=m
+CONFIG_RTW88_8822CE=m
+CONFIG_RTW88_8822C=m
+CONFIG_RTW88_CORE=m
+CONFIG_RTW88=m
+CONFIG_RTW88_PCI=m
+CONFIG_RTW89_8852AE=m
+CONFIG_RTW89_8852A=m
+CONFIG_RTW89_8852BTE=m
+CONFIG_RTW89_8852CE=m
+CONFIG_RTW89_8852C=m
+CONFIG_RTW89_8922AE=m
+CONFIG_RTW89_CORE=m
+CONFIG_RTW89=m
+CONFIG_RTW89_PCI=m
+CONFIG_RUNTIME_TESTING_MENU=y
+CONFIG_RXKAD=y
+CONFIG_RXPERF=m
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_AHCI=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SCHED_CORE=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_MM_CID=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_SCHED_SMT=y
+CONFIG_SCHEDSTATS=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_FC_ATTRS=m
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_LPFC=m
+CONFIG_SCSI_MOD=y
+CONFIG_SCSI_MPT2SAS_MAX_SGE=128
+CONFIG_SCSI_MPT2SAS=y
+CONFIG_SCSI_MPT3SAS_MAX_SGE=128
+CONFIG_SCSI_MPT3SAS=y
+CONFIG_SCSI_MVSAS_TASKLET=y
+CONFIG_SCSI_MVSAS=y
+CONFIG_SCSI_MVUMI=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+CONFIG_SCSI_QLA_FC=m
+CONFIG_SCSI_QLA_ISCSI=m
+CONFIG_SCSI_QLOGIC_1280=m
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=y
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_VIRTIO=m
+CONFIG_SCSI=y
+CONFIG_SCTP_COOKIE_HMAC_MD5=y
+CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
+CONFIG_SECRETMEM=y
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y
+CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
+CONFIG_SECURITY_APPARMOR_HASH=y
+CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y
+CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y
+CONFIG_SECURITY_APPARMOR=y
+CONFIG_SECURITY_IPE=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_SECURITY_PATH=y
+CONFIG_SECURITY_SELINUX_AVC_STATS=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_SELINUX_DEVELOP=y
+CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
+CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_YAMA=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_SERIAL_8250_16550A_VARIANTS=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_NR_UARTS=16
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PERICOM=y
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=16
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_RAW=m
+CONFIG_SERIO_SERPORT=m
+CONFIG_SERIO=y
+CONFIG_SFP=y
+CONFIG_SKB_EXTENSIONS=y
+CONFIG_SLAB_MERGE_DEFAULT=y
+CONFIG_SLHC=m
+CONFIG_SLUB_DEBUG=y
+CONFIG_SMBFS=m
+CONFIG_SND_BT87X=m
+CONFIG_SND_BT87X_OVERCLOCK=y
+CONFIG_SND_CTL_FAST_LOOKUP=y
+CONFIG_SND_CTL_LED=y
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_HDA_CODEC_ALC260=m
+CONFIG_SND_HDA_CODEC_ALC262=m
+CONFIG_SND_HDA_CODEC_ALC268=m
+CONFIG_SND_HDA_CODEC_ALC269=m
+CONFIG_SND_HDA_CODEC_ALC662=m
+CONFIG_SND_HDA_CODEC_ALC680=m
+CONFIG_SND_HDA_CODEC_ALC861=m
+CONFIG_SND_HDA_CODEC_ALC861VD=m
+CONFIG_SND_HDA_CODEC_ALC880=m
+CONFIG_SND_HDA_CODEC_ALC882=m
+CONFIG_SND_HDA_CODEC_CM9825=m
+CONFIG_SND_HDA_CODEC_CONEXANT=y
+CONFIG_SND_HDA_CODEC_CS420X=m
+CONFIG_SND_HDA_CODEC_CS421X=m
+CONFIG_SND_HDA_CODEC_HDMI_ATI=m
+CONFIG_SND_HDA_CODEC_HDMI_GENERIC=m
+CONFIG_SND_HDA_CODEC_HDMI_INTEL=m
+CONFIG_SND_HDA_CODEC_HDMI_NVIDIA=m
+CONFIG_SND_HDA_CODEC_HDMI_NVIDIA_MCP=m
+CONFIG_SND_HDA_CODEC_HDMI_SIMPLE=m
+CONFIG_SND_HDA_CODEC_HDMI_TEGRA=m
+CONFIG_SND_HDA_CODEC_HDMI=y
+CONFIG_SND_HDA_CODEC_REALTEK=y
+CONFIG_SND_HDA_CODEC_SENARYTECH=m
+CONFIG_SND_HDA_CODEC_SIGMATEL=y
+CONFIG_SND_HDA_COMPONENT=y
+CONFIG_SND_HDA_CORE=y
+CONFIG_SND_HDA_GENERIC_LEDS=y
+CONFIG_SND_HDA_GENERIC=y
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_INPUT_BEEP_MODE=1
+CONFIG_SND_HDA_INPUT_BEEP=y
+CONFIG_SND_HDA_INTEL=y
+CONFIG_SND_HDA_PATCH_LOADER=y
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
+CONFIG_SND_HDA_PREALLOC_SIZE=64
+CONFIG_SND_HDA_RECONFIG=y
+CONFIG_SND_HDA=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_INTEL_DSP_CONFIG=y
+CONFIG_SND_INTEL_NHLT=y
+CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_JACK=y
+CONFIG_SND_MAX_CARDS=32
+CONFIG_SND_PCI=y
+CONFIG_SND_PCMCIA=y
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_PROC_FS=y
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_SEQ_DEVICE=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQ_MIDI_EVENT=m
+CONFIG_SND_SEQ_MIDI=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SOC_ADI_AXI_I2S=m
+CONFIG_SND_SOC_ADI_AXI_SPDIF=m
+CONFIG_SND_SOC_AK4619=m
+CONFIG_SND_SOC_AW88166=m
+CONFIG_SND_SOC_CS40L50=m
+CONFIG_SND_SOC_CS530X_I2C=m
+CONFIG_SND_SOC_ES8311=m
+CONFIG_SND_SOC_FS210X=m
+CONFIG_SND_SOC_I2C_AND_SPI=m
+CONFIG_SND_SOC_LOONGSON_CARD=m
+CONFIG_SND_SOC_LOONGSON_I2S_PCI=m
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_MT6357=m
+CONFIG_SND_SOC_PCM1754=m
+CONFIG_SND_SOC_PCM6240=m
+CONFIG_SND_SOC_PM4125_SDW=m
+CONFIG_SND_SOC_TAS2783_SDW=m
+CONFIG_SND_SOC_WCD937X_SDW=m
+CONFIG_SND_SPI=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
+CONFIG_SND_USB=y
+CONFIG_SND_UTIMER=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VIRTIO=m
+CONFIG_SND_VMASTER=y
+CONFIG_SND=y
+CONFIG_SOC_BUS=y
+CONFIG_SOCK_CGROUP_DATA=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOCK_VALIDATE_XMIT=y
+CONFIG_SOUND=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPI_CH341=m
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_LOONGSON_CORE=m
+CONFIG_SPI_LOONGSON_PCI=m
+CONFIG_SPI_LOONGSON_PLATFORM=m
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_VIRTIO=m
+CONFIG_SPI=y
+CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_FILE_CACHE=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+CONFIG_SQUASHFS_LZ4=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SSB_DRIVER_GPIO=y
+CONFIG_STACKDEPOT_MAX_FRAMES=64
+CONFIG_STACKDEPOT=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKTRACE=y
+CONFIG_STAGING=y
+CONFIG_STANDALONE=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_STP=m
+CONFIG_STREAM_PARSER=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_SUNRPC_BACKCHANNEL=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_XPRT_RDMA=m
+CONFIG_SUNRPC=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYN_COOKIES=y
+CONFIG_SYSCON_REBOOT_MODE=y
+CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW=y
+CONFIG_SYSCTL_ARCH_UNALIGN_NO_WARN=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFB=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYSFS=y
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSV_FS=m
+CONFIG_TAP=m
+CONFIG_TARGET_CORE=m
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASKS_RCU=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_XACCT=y
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_PSCSI=m
+CONFIG_TCM_QLA2XXX=m
+CONFIG_TCM_USER2=m
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BBR=m
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_HTCP=m
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TLS_DEVICE=y
+CONFIG_TLS=m
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+CONFIG_TMPFS=y
+CONFIG_TOOLS_SUPPORT_RELR=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TUN=m
+CONFIG_TXGBE=y
+CONFIG_TYPEC_DP_ALTMODE=m
+CONFIG_TYPEC=m
+CONFIG_TYPEC_MUX_PS883X=m
+CONFIG_TYPEC_NVIDIA_ALTMODE=m
+CONFIG_TYPEC_TBT_ALTMODE=m
+CONFIG_TYPEC_TCPCI=m
+CONFIG_TYPEC_TCPM=m
+CONFIG_TYPEC_UCSI=m
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS=m
+CONFIG_UBIFS_FS_SECURITY=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UBIFS_FS_ZSTD=y
+CONFIG_UCLAMP_BUCKETS_COUNT=5
+CONFIG_UCLAMP_TASK_GROUP=y
+CONFIG_UCLAMP_TASK=y
+CONFIG_UCS2_STRING=y
+CONFIG_UCSI_ACPI=m
+CONFIG_UDF_FS=y
+CONFIG_UDMABUF=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UEVENT_HELPER=y
+CONFIG_UFS_FS=m
+CONFIG_UIO_DMEM_GENIRQ=m
+CONFIG_UIO_PCI_GENERIC=m
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNIX_SCM=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_UNIX=y
+CONFIG_UNWINDER_ORC=y
+CONFIG_USB4_NET=m
+CONFIG_USB4=y
+CONFIG_USB_ACM=m
+CONFIG_USB_ATM=m
+CONFIG_USB_COMMON=y
+CONFIG_USB_CXACRU=m
+CONFIG_USB_DWC2_HOST=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET=y
+CONFIG_USB_G_NOKIA=m
+CONFIG_USB_HCD_SSB=m
+CONFIG_USB_MON=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OTG=y
+CONFIG_USB_PCI_AMD=y
+CONFIG_USB_PRINTER=m
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SPEEDTOUCH=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_USB_UAS=m
+CONFIG_USB_UEAGLEATM=m
+CONFIG_USB_UHCI_HCD=m
+CONFIG_USB_USBIO=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_XUSBATM=m
+CONFIG_USB=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+CONFIG_USERFAULTFD=y
+CONFIG_U_SERIAL_CONSOLE=y
+CONFIG_USER_STACKTRACE_SUPPORT=y
+CONFIG_UVC_COMMON=m
+CONFIG_V4L2_ASYNC=m
+CONFIG_V4L2_FWNODE=m
+CONFIG_VETH=m
+CONFIG_VFAT_FS=m
+CONFIG_VFIO_CONTAINER=y
+CONFIG_VFIO_GROUP=y
+CONFIG_VFIO=m
+CONFIG_VFIO_PCI_CORE=m
+CONFIG_VFIO_PCI_INTX=y
+CONFIG_VFIO_PCI=m
+CONFIG_VFIO_PCI_MMAP=y
+CONFIG_VFIO_VIRQFD=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VHOST_IOTLB=m
+CONFIG_VHOST=m
+CONFIG_VHOST_SCSI=m
+CONFIG_VHOST_TASK=y
+CONFIG_VIDEO_BT848=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_DMA_SG=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_V4L2=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEO_CAMERA_SENSOR=y
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_E5010_JPEG_ENC=m
+CONFIG_VIDEO_GC0310=m
+CONFIG_VIDEO_GC05A2=m
+CONFIG_VIDEO_GC08A3=m
+CONFIG_VIDEO_IMX283=m
+CONFIG_VIDEO_IR_I2C=m
+CONFIG_VIDEO_LT6911UXE=m
+CONFIG_VIDEO_MAX9286=m
+CONFIG_VIDEO_MAX96714=m
+CONFIG_VIDEO_MAX96717=m
+CONFIG_VIDEO_NOMODESET=y
+CONFIG_VIDEO_OG0VE1B=m
+CONFIG_VIDEO_OV2735=m
+CONFIG_VIDEO_OV6211=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_VIDEO_VGXY61=m
+CONFIG_VIRTIO_ANCHOR=y
+CONFIG_VIRTIO_BALLOON=m
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
+CONFIG_VIRTIO_FS=m
+CONFIG_VIRTIO_INPUT=m
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_VIRTIO_MMIO=m
+CONFIG_VIRTIO_NET=m
+CONFIG_VIRTIO_PCI_LIB_LEGACY=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_VSOCKETS_COMMON=m
+CONFIG_VIRTIO_VSOCKETS=m
+CONFIG_VIRTIO=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_VSOCKETS_DIAG=m
+CONFIG_VSOCKETS_LOOPBACK=m
+CONFIG_VSOCKETS=m
+CONFIG_VXLAN=y
+CONFIG_WANT_DEV_COREDUMP=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WIREGUARD=m
+CONFIG_XARRAY_MULTI=y
+CONFIG_XDP_SOCKETS=y
+CONFIG_XFRM_ALGO=y
+CONFIG_XFRM_ESP=m
+CONFIG_XFRM_USER=y
+CONFIG_XFRM=y
+CONFIG_XFS_FS=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_XFS_QUOTA=y
+CONFIG_XFS_SUPPORT_ASCII_CI=y
+CONFIG_XFS_SUPPORT_V4=y
+CONFIG_XOR_BLOCKS=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_MICROLZMA=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_YENTA_ENE_TUNE=y
+CONFIG_YENTA=m
+CONFIG_YENTA_O2=y
+CONFIG_YENTA_RICOH=y
+CONFIG_YENTA_TI=y
+CONFIG_YENTA_TOSHIBA=y
+CONFIG_ZD1211RW=m
+CONFIG_ZISOFS=y
+CONFIG_ZL3073X_SPI=m
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZONE_DEVICE=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZPOOL=y
+CONFIG_ZRAM_DEF_COMP="zstd"
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+EXTCON_USBC_TUSB320=m
+EXTCON_USB_GPIO=m
+CONFIG_NEXUS=m
diff --git a/modules.fragment b/modules.fragment
new file mode 100644
index 0000000..64fb3ed
--- /dev/null
+++ b/modules.fragment
@@ -0,0 +1,39 @@
+CONFIG_MODULE_SIG_FORMAT=y
+CONFIG_MODULES=y
+# CONFIG_MODULE_DEBUG is not set
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
+CONFIG_MODVERSIONS=y
+CONFIG_GENKSYMS=y
+# CONFIG_GENDWARFKSYMS is not set
+# CONFIG_EXTENDED_MODVERSIONS is not set
+CONFIG_BASIC_MODVERSIONS=y
+CONFIG_ASM_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_MODULE_SIG=y
+# CONFIG_MODULE_SIG_FORCE is not set
+# CONFIG_MODULE_SIG_ALL is not set
+# CONFIG_MODULE_SIG_SHA1 is not set
+# CONFIG_MODULE_SIG_SHA256 is not set
+# CONFIG_MODULE_SIG_SHA384 is not set
+# CONFIG_MODULE_SIG_SHA512 is not set
+# CONFIG_MODULE_SIG_SHA3_256 is not set
+# CONFIG_MODULE_SIG_SHA3_384 is not set
+CONFIG_MODULE_SIG_SHA3_512=y
+CONFIG_MODULE_SIG_HASH="sha3-512"
+CONFIG_MODULE_SIG_KEY="certs/signing_key.pem"
+CONFIG_MODULE_SIG_KEY_TYPE_RSA=y
+# CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set
+CONFIG_MODULE_COMPRESS=y
+CONFIG_MODULE_COMPRESS_NONE=y
+# CONFIG_MODULE_COMPRESS_GZIP is not set
+# CONFIG_MODULE_COMPRESS_XZ is not set
+# CONFIG_MODULE_COMPRESS_ZSTD is not set
+# CONFIG_MODULE_COMPRESS_ALL is not set
+CONFIG_MODULE_DECOMPRESS=y
+# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
+CONFIG_MODPROBE_PATH="/sbin/modprobe"
+# CONFIG_TRIM_UNUSED_KSYMS is not set
+CONFIG_MODULES_TREE_LOOKUP=y
diff --git a/networking.fragment b/networking.fragment
new file mode 100644
index 0000000..b4f4b0b
--- /dev/null
+++ b/networking.fragment
@@ -0,0 +1,1359 @@
+CONFIG_NET=y
+CONFIG_WANT_COMPAT_NETLINK_MESSAGES=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_REDIRECT=y
+CONFIG_SKB_EXTENSIONS=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=m
+CONFIG_PACKET_DIAG=m
+CONFIG_INET_PSP=y
+CONFIG_UNIX=y
+CONFIG_UNIX_SCM=y
+CONFIG_AF_UNIX_OOB=y
+CONFIG_UNIX_DIAG=m
+CONFIG_TLS=m
+CONFIG_TLS_DEVICE=y
+# CONFIG_TLS_TOE is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_OFFLOAD=y
+CONFIG_XFRM_ALGO=m
+CONFIG_XFRM_USER=m
+CONFIG_XFRM_USER_COMPAT=m
+CONFIG_XFRM_INTERFACE=m
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_XFRM_AH=m
+CONFIG_XFRM_ESP=m
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_XFRM_IPTFS=m
+CONFIG_DIBS=m
+CONFIG_DIBS_LO=y
+CONFIG_XFRM_ESPINTCP=y
+CONFIG_SMC=m
+CONFIG_SMC_DIAG=m
+CONFIG_SMC_LO=y
+CONFIG_XDP_SOCKETS=y
+CONFIG_XDP_SOCKETS_DIAG=m
+CONFIG_NET_HANDSHAKE=y
+# CONFIG_NET_HANDSHAKE_KUNIT_TEST is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_FIB_TRIE_STATS=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_ROUTE_CLASSID=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
+CONFIG_NET_IP_TUNNEL=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE_COMMON=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
+CONFIG_NET_UDP_TUNNEL=m
+CONFIG_NET_FOU=m
+CONFIG_NET_FOU_IP_TUNNELS=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_ESP_OFFLOAD=m
+CONFIG_INET_ESPINTCP=y
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_TABLE_PERTURB_ORDER=16
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+CONFIG_INET_UDP_DIAG=m
+CONFIG_INET_RAW_DIAG=m
+CONFIG_INET_DIAG_DESTROY=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=m
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_VEGAS=m
+CONFIG_TCP_CONG_NV=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+CONFIG_TCP_CONG_DCTCP=m
+# CONFIG_TCP_CONG_CDG is not set
+CONFIG_TCP_CONG_BBR=m
+CONFIG_DEFAULT_RENO=y
+CONFIG_DEFAULT_TCP_CONG="reno"
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6=m
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_ESP_OFFLOAD=m
+# CONFIG_INET6_ESPINTCP is not set
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_IPV6_ILA=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_IPV6_VTI=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_SIT_6RD=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_GRE=m
+CONFIG_IPV6_FOU=m
+CONFIG_IPV6_FOU_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_IPV6_SEG6_LWTUNNEL=y
+CONFIG_IPV6_SEG6_HMAC=y
+CONFIG_IPV6_RPL_LWTUNNEL=y
+CONFIG_IPV6_IOAM6_LWTUNNEL=y
+CONFIG_MPTCP=y
+CONFIG_INET_MPTCP_DIAG=m
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NETWORK_PHY_TIMESTAMPING=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=m
+CONFIG_LWTUNNEL_BPF=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_INGRESS=y
+CONFIG_NETFILTER_EGRESS=y
+CONFIG_NETFILTER_SKIP_EGRESS=y
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_FAMILY_BRIDGE=y
+CONFIG_NETFILTER_FAMILY_ARP=y
+CONFIG_NETFILTER_BPF_LINK=y
+CONFIG_NETFILTER_NETLINK_HOOK=m
+CONFIG_NETFILTER_NETLINK_ACCT=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NETFILTER_NETLINK_OSF=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_LOG_SYSLOG=m
+CONFIG_NETFILTER_CONNCOUNT=m
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_ZONES=y
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+CONFIG_NF_CONNTRACK_TIMESTAMP=y
+CONFIG_NF_CONNTRACK_LABELS=y
+CONFIG_NF_CONNTRACK_OVS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_NETLINK_TIMEOUT=m
+CONFIG_NF_CT_NETLINK_HELPER=m
+CONFIG_NETFILTER_NETLINK_GLUE_CT=y
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_REDIRECT=y
+CONFIG_NF_NAT_MASQUERADE=y
+CONFIG_NF_NAT_OVS=y
+CONFIG_NETFILTER_SYNPROXY=m
+CONFIG_NF_TABLES=m
+CONFIG_NF_TABLES_INET=y
+CONFIG_NF_TABLES_NETDEV=y
+CONFIG_NFT_NUMGEN=m
+CONFIG_NFT_CT=m
+# CONFIG_NFT_EXTHDR_DCCP is not set
+CONFIG_NFT_FLOW_OFFLOAD=m
+CONFIG_NFT_CONNLIMIT=m
+CONFIG_NFT_LOG=m
+CONFIG_NFT_LIMIT=m
+CONFIG_NFT_MASQ=m
+CONFIG_NFT_REDIR=m
+CONFIG_NFT_NAT=m
+CONFIG_NFT_TUNNEL=m
+CONFIG_NFT_QUEUE=m
+CONFIG_NFT_QUOTA=m
+CONFIG_NFT_REJECT=m
+CONFIG_NFT_REJECT_INET=m
+CONFIG_NFT_COMPAT=m
+CONFIG_NFT_HASH=m
+CONFIG_NFT_FIB=m
+CONFIG_NFT_FIB_INET=m
+CONFIG_NFT_XFRM=m
+CONFIG_NFT_SOCKET=m
+CONFIG_NFT_OSF=m
+CONFIG_NFT_TPROXY=m
+CONFIG_NFT_SYNPROXY=m
+CONFIG_NF_DUP_NETDEV=m
+CONFIG_NFT_DUP_NETDEV=m
+CONFIG_NFT_FWD_NETDEV=m
+CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NFT_REJECT_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
+CONFIG_NF_FLOW_TABLE_PROCFS=y
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XTABLES_LEGACY=y
+CONFIG_NETFILTER_XTABLES_COMPAT=y
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+CONFIG_NETFILTER_XT_SET=m
+
+#
+# Xtables targets
+#
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
+CONFIG_NETFILTER_XT_TARGET_CT=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_NAT=m
+CONFIG_NETFILTER_XT_TARGET_NETMAP=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
+CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
+CONFIG_NETFILTER_XT_MATCH_CGROUP=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_CPU=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ECN=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_IPVS=m
+CONFIG_NETFILTER_XT_MATCH_L2TP=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+# end of Core Netfilter Configuration
+
+CONFIG_IP_SET=m
+CONFIG_IP_SET_MAX=256
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPMARK=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_IPMAC=m
+CONFIG_IP_SET_HASH_MAC=m
+CONFIG_IP_SET_HASH_NETPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETNET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
+CONFIG_IP_VS=m
+CONFIG_IP_VS_IPV6=y
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_PROTO_SCTP=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_FO=m
+CONFIG_IP_VS_OVF=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_MH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+CONFIG_IP_VS_TWOS=m
+
+#
+# IPVS SH scheduler
+#
+CONFIG_IP_VS_SH_TAB_BITS=8
+
+#
+# IPVS MH scheduler
+#
+CONFIG_IP_VS_MH_TAB_INDEX=12
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+CONFIG_IP_VS_NFCT=y
+CONFIG_IP_VS_PE_SIP=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_SOCKET_IPV4=m
+CONFIG_NF_TPROXY_IPV4=m
+CONFIG_NF_TABLES_IPV4=y
+CONFIG_NFT_REJECT_IPV4=m
+CONFIG_NFT_DUP_IPV4=m
+CONFIG_NFT_FIB_IPV4=m
+CONFIG_NF_TABLES_ARP=y
+CONFIG_NF_DUP_IPV4=m
+CONFIG_NF_LOG_ARP=m
+CONFIG_NF_LOG_IPV4=m
+CONFIG_NF_REJECT_IPV4=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_SYNPROXY=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+# end of IP: Netfilter Configuration
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_SOCKET_IPV6=m
+CONFIG_NF_TPROXY_IPV6=m
+CONFIG_NF_TABLES_IPV6=y
+CONFIG_NFT_REJECT_IPV6=m
+CONFIG_NFT_DUP_IPV6=m
+CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_DUP_IPV6=m
+CONFIG_NF_REJECT_IPV6=m
+CONFIG_NF_LOG_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_IPTABLES_LEGACY=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_TARGET_SYNPROXY=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP6_NF_NAT=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
+# end of IPv6: Netfilter Configuration
+
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_TABLES_BRIDGE=m
+CONFIG_NFT_BRIDGE_META=m
+CONFIG_NFT_BRIDGE_REJECT=m
+CONFIG_NF_CONNTRACK_BRIDGE=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_NF_EBTABLES_LEGACY=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_IP6=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_NFLOG=m
+CONFIG_BPFILTER=m
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+
+#
+# DCCP CCIDs Configuration
+#
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=y
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_TFRC_LIB=y
+# end of DCCP CCIDs Configuration
+
+#
+# DCCP Kernel Hacking
+#
+# CONFIG_IP_DCCP_DEBUG is not set
+# end of DCCP Kernel Hacking
+
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_OBJCNT is not set
+CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA256=y
+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
+CONFIG_SCTP_COOKIE_HMAC_MD5=y
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_INET_SCTP_DIAG=m
+CONFIG_RDS=m
+CONFIG_RDS_RDMA=m
+CONFIG_RDS_TCP=m
+# CONFIG_RDS_DEBUG is not set
+CONFIG_TIPC=m
+CONFIG_TIPC_MEDIA_IB=y
+CONFIG_TIPC_MEDIA_UDP=y
+CONFIG_TIPC_CRYPTO=y
+CONFIG_TIPC_DIAG=m
+CONFIG_ATM=m
+CONFIG_ATM_CLIP=m
+# CONFIG_ATM_CLIP_NO_ICMP is not set
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+# CONFIG_ATM_BR2684_IPFILTER is not set
+CONFIG_L2TP=m
+# CONFIG_L2TP_DEBUGFS is not set
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=m
+CONFIG_L2TP_ETH=m
+CONFIG_STP=m
+CONFIG_GARP=m
+CONFIG_MRP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+CONFIG_BRIDGE_VLAN_FILTERING=y
+# CONFIG_BRIDGE_MRP is not set
+# CONFIG_BRIDGE_CFM is not set
+CONFIG_NET_DSA=m
+CONFIG_NET_DSA_TAG_NONE=m
+CONFIG_NET_DSA_TAG_AR9331=m
+CONFIG_NET_DSA_TAG_BRCM_COMMON=m
+CONFIG_NET_DSA_TAG_BRCM=m
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
+CONFIG_NET_DSA_TAG_HELLCREEK=m
+CONFIG_NET_DSA_TAG_GSWIP=m
+CONFIG_NET_DSA_TAG_DSA_COMMON=m
+CONFIG_NET_DSA_TAG_DSA=m
+CONFIG_NET_DSA_TAG_EDSA=m
+CONFIG_NET_DSA_TAG_MTK=m
+CONFIG_NET_DSA_TAG_KSZ=m
+CONFIG_NET_DSA_TAG_OCELOT=m
+CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
+CONFIG_NET_DSA_TAG_QCA=m
+CONFIG_NET_DSA_TAG_RTL4_A=m
+CONFIG_NET_DSA_TAG_RTL8_4=m
+CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
+CONFIG_NET_DSA_TAG_LAN9303=m
+CONFIG_NET_DSA_TAG_SJA1105=m
+CONFIG_NET_DSA_TAG_TRAILER=m
+CONFIG_NET_DSA_TAG_XRS700X=m
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_LLC=m
+CONFIG_LLC2=m
+CONFIG_ATALK=m
+CONFIG_DEV_APPLETALK=m
+CONFIG_IPDDP=m
+CONFIG_IPDDP_ENCAP=y
+CONFIG_X25=m
+CONFIG_LAPB=m
+CONFIG_PHONET=m
+CONFIG_6LOWPAN=m
+# CONFIG_6LOWPAN_DEBUGFS is not set
+CONFIG_6LOWPAN_NHC=m
+CONFIG_6LOWPAN_NHC_DEST=m
+CONFIG_6LOWPAN_NHC_FRAGMENT=m
+CONFIG_6LOWPAN_NHC_HOP=m
+CONFIG_6LOWPAN_NHC_IPV6=m
+CONFIG_6LOWPAN_NHC_MOBILITY=m
+CONFIG_6LOWPAN_NHC_ROUTING=m
+CONFIG_6LOWPAN_NHC_UDP=m
+CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
+CONFIG_6LOWPAN_GHC_UDP=m
+CONFIG_6LOWPAN_GHC_ICMPV6=m
+CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
+CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
+CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
+CONFIG_IEEE802154=m
+CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
+CONFIG_IEEE802154_SOCKET=m
+CONFIG_IEEE802154_6LOWPAN=m
+CONFIG_MAC802154=m
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFB=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_CBS=m
+CONFIG_NET_SCH_ETF=m
+CONFIG_NET_SCH_MQPRIO_LIB=m
+CONFIG_NET_SCH_TAPRIO=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+CONFIG_NET_SCH_MQPRIO=m
+CONFIG_NET_SCH_SKBPRIO=m
+CONFIG_NET_SCH_CHOKE=m
+CONFIG_NET_SCH_QFQ=m
+CONFIG_NET_SCH_CODEL=m
+CONFIG_NET_SCH_FQ_CODEL=y
+CONFIG_NET_SCH_CAKE=m
+CONFIG_NET_SCH_FQ=m
+CONFIG_NET_SCH_HHF=m
+CONFIG_NET_SCH_PIE=m
+CONFIG_NET_SCH_FQ_PIE=m
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_SCH_PLUG=m
+CONFIG_NET_SCH_ETS=m
+CONFIG_NET_SCH_BPF=y
+CONFIG_NET_SCH_DUALPI2=m
+CONFIG_NET_SCH_DEFAULT=y
+# CONFIG_DEFAULT_FQ is not set
+# CONFIG_DEFAULT_CODEL is not set
+CONFIG_DEFAULT_FQ_CODEL=y
+# CONFIG_DEFAULT_FQ_PIE is not set
+# CONFIG_DEFAULT_SFQ is not set
+# CONFIG_DEFAULT_PFIFO_FAST is not set
+CONFIG_DEFAULT_NET_SCH="fq_codel"
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_FLOW=m
+CONFIG_NET_CLS_CGROUP=m
+CONFIG_NET_CLS_BPF=m
+CONFIG_NET_CLS_FLOWER=m
+CONFIG_NET_CLS_MATCHALL=m
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_EMATCH_CANID=m
+CONFIG_NET_EMATCH_IPSET=m
+CONFIG_NET_EMATCH_IPT=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_GACT_PROB=y
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_SAMPLE=m
+CONFIG_NET_ACT_IPT=m
+CONFIG_NET_ACT_NAT=m
+CONFIG_NET_ACT_PEDIT=m
+# CONFIG_NET_ACT_SIMP is not set
+CONFIG_NET_ACT_SKBEDIT=m
+CONFIG_NET_ACT_CSUM=m
+CONFIG_NET_ACT_MPLS=m
+CONFIG_NET_ACT_VLAN=m
+CONFIG_NET_ACT_BPF=m
+CONFIG_NET_ACT_CONNMARK=m
+CONFIG_NET_ACT_CTINFO=m
+CONFIG_NET_ACT_SKBMOD=m
+CONFIG_NET_ACT_IFE=m
+CONFIG_NET_ACT_TUNNEL_KEY=m
+CONFIG_NET_ACT_CT=m
+CONFIG_NET_ACT_GATE=m
+CONFIG_NET_IFE_SKBMARK=m
+CONFIG_NET_IFE_SKBPRIO=m
+CONFIG_NET_IFE_SKBTCINDEX=m
+# CONFIG_NET_TC_SKB_EXT is not set
+CONFIG_NET_SCH_FIFO=y
+CONFIG_DCB=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_BATMAN_ADV=m
+# CONFIG_BATMAN_ADV_BATMAN_V is not set
+CONFIG_BATMAN_ADV_BLA=y
+CONFIG_BATMAN_ADV_DAT=y
+CONFIG_BATMAN_ADV_NC=y
+CONFIG_BATMAN_ADV_MCAST=y
+# CONFIG_BATMAN_ADV_DEBUG is not set
+# CONFIG_BATMAN_ADV_TRACING is not set
+CONFIG_OPENVSWITCH=m
+CONFIG_OPENVSWITCH_GRE=m
+CONFIG_OPENVSWITCH_VXLAN=m
+CONFIG_OPENVSWITCH_GENEVE=m
+CONFIG_VSOCKETS=m
+CONFIG_VSOCKETS_DIAG=m
+CONFIG_VSOCKETS_LOOPBACK=m
+CONFIG_VMWARE_VMCI_VSOCKETS=m
+CONFIG_VIRTIO_VSOCKETS=m
+CONFIG_VIRTIO_VSOCKETS_COMMON=m
+CONFIG_HYPERV_VSOCKETS=m
+CONFIG_NETLINK_DIAG=m
+CONFIG_MPLS=y
+CONFIG_NET_MPLS_GSO=m
+CONFIG_MPLS_ROUTING=m
+CONFIG_MPLS_IPTUNNEL=m
+CONFIG_NET_NSH=m
+CONFIG_HSR=m
+CONFIG_PRP_DUP_DISCARD_KUNIT_TEST=m
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_L3_MASTER_DEV=y
+CONFIG_QRTR=m
+CONFIG_QRTR_SMD=m
+CONFIG_QRTR_TUN=m
+CONFIG_QRTR_MHI=m
+# CONFIG_NET_NCSI is not set
+CONFIG_PCPU_DEV_REFCNT=y
+CONFIG_MAX_SKB_FRAGS=17
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_XPS=y
+CONFIG_CGROUP_NET_PRIO=y
+CONFIG_CGROUP_NET_CLASSID=y
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+CONFIG_BPF_STREAM_PARSER=y
+CONFIG_NET_FLOW_LIMIT=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+CONFIG_NET_DROP_MONITOR=m
+# end of Network testing
+# end of Networking options
+
+#
+# Distributed Switch Architecture drivers
+#
+CONFIG_B53=m
+CONFIG_B53_SPI_DRIVER=m
+CONFIG_B53_MDIO_DRIVER=m
+CONFIG_B53_MMAP_DRIVER=m
+CONFIG_B53_SRAB_DRIVER=m
+CONFIG_B53_SERDES=m
+CONFIG_NET_DSA_BCM_SF2=m
+CONFIG_NET_DSA_LOOP=m
+CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
+CONFIG_NET_DSA_LANTIQ_GSWIP=m
+CONFIG_NET_DSA_MT7530=m
+CONFIG_NET_DSA_MT7530_MDIO=m
+CONFIG_NET_DSA_MT7530_MMIO=m
+CONFIG_NET_DSA_MV88E6060=m
+CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
+CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
+CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
+CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=y
+CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
+CONFIG_NET_DSA_MV88E6XXX=m
+CONFIG_NET_DSA_MV88E6XXX_PTP=y
+CONFIG_NET_DSA_MSCC_FELIX_DSA_LIB=m
+CONFIG_NET_DSA_MSCC_OCELOT_EXT=m
+CONFIG_NET_DSA_MSCC_FELIX=m
+CONFIG_NET_DSA_MSCC_SEVILLE=m
+CONFIG_NET_DSA_AR9331=m
+CONFIG_NET_DSA_QCA8K=m
+CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y
+CONFIG_NET_DSA_SJA1105=m
+CONFIG_NET_DSA_SJA1105_PTP=y
+CONFIG_NET_DSA_SJA1105_TAS=y
+# CONFIG_NET_DSA_SJA1105_VL is not set
+CONFIG_NET_DSA_XRS700X=m
+CONFIG_NET_DSA_XRS700X_I2C=m
+CONFIG_NET_DSA_XRS700X_MDIO=m
+CONFIG_NET_DSA_KS8995=m
+CONFIG_NET_DSA_REALTEK=m
+CONFIG_NET_DSA_REALTEK_MDIO=y
+CONFIG_NET_DSA_REALTEK_SMI=y
+CONFIG_NET_DSA_REALTEK_RTL8365MB=m
+CONFIG_NET_DSA_REALTEK_RTL8366RB=m
+CONFIG_NET_DSA_REALTEK_RTL8366RB_LEDS=y
+CONFIG_NET_DSA_SMSC_LAN9303=m
+CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
+CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
+CONFIG_NET_DSA_VITESSE_VSC73XX=m
+CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
+CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
+# end of Distributed Switch Architecture drivers
+
+CONFIG_ETHERNET=y
+CONFIG_MDIO=m
+CONFIG_NET_VENDOR_3COM=y
+CONFIG_EL3=m
+CONFIG_3C515=m
+CONFIG_PCMCIA_3C574=m
+CONFIG_PCMCIA_3C589=m
+CONFIG_VORTEX=m
+CONFIG_TYPHOON=m
+CONFIG_NET_VENDOR_ACTIONS=y
+CONFIG_OWL_EMAC=m
+CONFIG_NET_VENDOR_ADAPTEC=y
+CONFIG_ADAPTEC_STARFIRE=m
+CONFIG_NET_VENDOR_AGERE=y
+CONFIG_ET131X=m
+CONFIG_NET_VENDOR_AIROHA=y
+CONFIG_NET_AIROHA_FLOW_STATS=y
+CONFIG_NET_AIROHA_NPU=m
+CONFIG_NET_VENDOR_ALACRITECH=y
+CONFIG_SLICOSS=m
+CONFIG_NET_VENDOR_ALLWINNER=y
+CONFIG_SUN4I_EMAC=m
+CONFIG_NET_VENDOR_ALTEON=y
+CONFIG_ACENIC=m
+# CONFIG_ACENIC_OMIT_TIGON_I is not set
+CONFIG_ALTERA_TSE=m
+CONFIG_NET_VENDOR_AMAZON=y
+CONFIG_ENA_ETHERNET=m
+CONFIG_NET_VENDOR_AMD=y
+CONFIG_AMD8111_ETH=m
+CONFIG_LANCE=m
+CONFIG_PCNET32=m
+CONFIG_PCMCIA_NMCLAN=m
+CONFIG_AMD_XGBE=m
+CONFIG_AMD_XGBE_DCB=y
+CONFIG_AMD_XGBE_HAVE_ECC=y
+CONFIG_PDS_CORE=m
+CONFIG_NET_XGENE=m
+CONFIG_NET_XGENE_V2=m
+CONFIG_NET_VENDOR_AQUANTIA=y
+CONFIG_AQTION=m
+CONFIG_NET_VENDOR_ARC=y
+CONFIG_EMAC_ROCKCHIP=m
+CONFIG_NET_VENDOR_ASIX=y
+CONFIG_SPI_AX88796C=m
+CONFIG_SPI_AX88796C_COMPRESSION=y
+CONFIG_NET_VENDOR_ATHEROS=y
+CONFIG_ATL2=m
+CONFIG_ATL1=m
+CONFIG_ATL1E=m
+CONFIG_ATL1C=m
+CONFIG_ALX=m
+CONFIG_CX_ECAT=m
+CONFIG_NET_VENDOR_BROADCOM=y
+CONFIG_B44=m
+CONFIG_BCM4908_ENET=m
+CONFIG_B44_PCI_AUTOSELECT=y
+CONFIG_B44_PCICORE_AUTOSELECT=y
+CONFIG_B44_PCI=y
+CONFIG_BCMGENET=m
+CONFIG_BNX2=m
+CONFIG_CNIC=m
+CONFIG_TIGON3=m
+CONFIG_TIGON3_HWMON=y
+CONFIG_BNX2X=m
+CONFIG_BNX2X_SRIOV=y
+CONFIG_BGMAC_PLATFORM=m
+CONFIG_SYSTEMPORT=m
+CONFIG_BNXT=m
+CONFIG_BNXT_SRIOV=y
+CONFIG_BNXT_FLOWER_OFFLOAD=y
+CONFIG_BNXT_DCB=y
+CONFIG_BNXT_HWMON=y
+CONFIG_BNGE=m
+CONFIG_BCMASP=m
+CONFIG_NET_VENDOR_CADENCE=y
+CONFIG_MACB=m
+CONFIG_MACB_USE_HWSTAMP=y
+CONFIG_MACB_PCI=m
+CONFIG_NET_CALXEDA_XGMAC=m
+CONFIG_NET_VENDOR_CAVIUM=y
+CONFIG_THUNDER_NIC_PF=m
+CONFIG_THUNDER_NIC_VF=m
+CONFIG_THUNDER_NIC_BGX=m
+CONFIG_THUNDER_NIC_RGX=m
+CONFIG_CAVIUM_PTP=m
+CONFIG_LIQUIDIO_CORE=m
+CONFIG_LIQUIDIO=m
+CONFIG_LIQUIDIO_VF=m
+CONFIG_NET_VENDOR_CHELSIO=y
+CONFIG_CHELSIO_T1=m
+CONFIG_CHELSIO_T1_1G=y
+CONFIG_CHELSIO_T3=m
+CONFIG_CHELSIO_T4=m
+CONFIG_CHELSIO_T4_DCB=y
+# CONFIG_CHELSIO_T4_FCOE is not set
+CONFIG_CHELSIO_T4VF=m
+CONFIG_CHELSIO_LIB=m
+CONFIG_CHELSIO_INLINE_CRYPTO=y
+CONFIG_CHELSIO_IPSEC_INLINE=m
+CONFIG_CHELSIO_TLS_DEVICE=m
+CONFIG_NET_VENDOR_CIRRUS=y
+# CONFIG_CS89x0_ISA is not set
+CONFIG_NET_VENDOR_CISCO=y
+CONFIG_ENIC=m
+CONFIG_NET_VENDOR_CORTINA=y
+CONFIG_GEMINI_ETHERNET=m
+CONFIG_NET_VENDOR_DAVICOM=y
+CONFIG_DM9000=m
+# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
+CONFIG_DM9051=m
+CONFIG_DNET=m
+CONFIG_NET_VENDOR_DEC=y
+CONFIG_NET_TULIP=y
+CONFIG_DE2104X=m
+CONFIG_DE2104X_DSL=0
+CONFIG_TULIP=m
+CONFIG_TULIP_MWI=y
+CONFIG_TULIP_MMIO=y
+CONFIG_TULIP_NAPI=y
+CONFIG_TULIP_NAPI_HW_MITIGATION=y
+CONFIG_WINBOND_840=m
+CONFIG_DM9102=m
+CONFIG_ULI526X=m
+CONFIG_PCMCIA_XIRCOM=m
+CONFIG_NET_VENDOR_DLINK=y
+CONFIG_DL2K=m
+CONFIG_SUNDANCE=m
+# CONFIG_SUNDANCE_MMIO is not set
+CONFIG_NET_VENDOR_EMULEX=y
+CONFIG_BE2NET=m
+CONFIG_BE2NET_HWMON=y
+CONFIG_BE2NET_BE2=y
+CONFIG_BE2NET_BE3=y
+CONFIG_BE2NET_LANCER=y
+CONFIG_BE2NET_SKYHAWK=y
+CONFIG_NET_VENDOR_ENGLEDER=y
+CONFIG_TSNEP=m
+# CONFIG_TSNEP_SELFTESTS is not set
+CONFIG_NET_VENDOR_EZCHIP=y
+CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=m
+CONFIG_NET_VENDOR_FARADAY=y
+CONFIG_FTMAC100=m
+CONFIG_FTGMAC100=m
+CONFIG_NET_VENDOR_FREESCALE=y
+CONFIG_FEC=m
+CONFIG_FSL_FMAN=m
+CONFIG_FSL_PQ_MDIO=m
+CONFIG_FSL_XGMAC_MDIO=m
+CONFIG_GIANFAR=m
+CONFIG_FSL_DPAA2_SWITCH=m
+CONFIG_FSL_ENETC=m
+CONFIG_FSL_ENETC_VF=m
+CONFIG_FSL_ENETC_IERB=m
+CONFIG_FSL_ENETC_PTP_CLOCK=m
+CONFIG_FSL_ENETC_QOS=y
+CONFIG_NET_VENDOR_FUJITSU=y
+CONFIG_PCMCIA_FMVJ18X=m
+CONFIG_NET_VENDOR_FUNGIBLE=y
+CONFIG_FUN_CORE=m
+CONFIG_FUN_ETH=m
+CONFIG_NET_VENDOR_GOOGLE=y
+CONFIG_GVE=m
+CONFIG_NET_VENDOR_HISILICON=y
+CONFIG_HIX5HD2_GMAC=m
+CONFIG_HISI_FEMAC=m
+CONFIG_HIP04_ETH=m
+CONFIG_HI13X1_GMAC=y
+CONFIG_HNS_DSAF=m
+CONFIG_HNS_ENET=m
+CONFIG_HNS3=m
+CONFIG_HNS3_HCLGE=m
+CONFIG_HNS3_ENET=m
+CONFIG_HNS3_DCB=y
+CONFIG_HNS3_HCLGEVF=m
+CONFIG_NET_VENDOR_HUAWEI=y
+CONFIG_HINIC=m
+CONFIG_HINIC3=m
+CONFIG_NET_VENDOR_I825XX=y
+CONFIG_NET_VENDOR_INTEL=y
+CONFIG_E100=m
+CONFIG_E1000=m
+CONFIG_E1000E=m
+CONFIG_E1000E_HWTS=y
+CONFIG_IGB=m
+CONFIG_IGB_HWMON=y
+CONFIG_IGB_DCA=y
+CONFIG_IGBVF=m
+CONFIG_IXGBE=m
+CONFIG_IXGBE_HWMON=y
+CONFIG_IXGBE_DCA=y
+CONFIG_IXGBE_DCB=y
+CONFIG_IXGBE_IPSEC=y
+CONFIG_IXGBEVF=m
+CONFIG_IXGBEVF_IPSEC=y
+CONFIG_I40E=m
+CONFIG_I40E_DCB=y
+CONFIG_IAVF=m
+CONFIG_I40EVF=m
+CONFIG_ICE=m
+CONFIG_ICE_SWITCHDEV=y
+CONFIG_ICE_HWTS=y
+CONFIG_ICE_HWMON=y
+CONFIG_FM10K=m
+CONFIG_IGC=m
+CONFIG_IDPF=m
+CONFIG_IDPF_SINGLEQ=y
+CONFIG_JME=m
+CONFIG_NET_VENDOR_ADI=y
+CONFIG_ADIN1110=m
+CONFIG_NET_VENDOR_LITEX=y
+CONFIG_LITEX_LITEETH=m
+CONFIG_NET_VENDOR_MARVELL=y
+CONFIG_MV643XX_ETH=m
+CONFIG_MVMDIO=m
+CONFIG_MVNETA_BM_ENABLE=m
+CONFIG_MVNETA=m
+CONFIG_MVPP2=m
+CONFIG_MVPP2_PTP=y
+CONFIG_PXA168_ETH=m
+CONFIG_SKGE=m
+# CONFIG_SKGE_DEBUG is not set
+CONFIG_SKGE_GENESIS=y
+CONFIG_SKY2=m
+# CONFIG_SKY2_DEBUG is not set
+CONFIG_OCTEONTX2_AF=m
+# CONFIG_NDC_DIS_DYNAMIC_CACHING is not set
+CONFIG_OCTEONTX2_PF=m
+CONFIG_OCTEONTX2_VF=m
+CONFIG_OCTEON_EP=m
+CONFIG_OCTEON_EP_VF=m
+CONFIG_PRESTERA=m
+CONFIG_PRESTERA_PCI=m
+CONFIG_NET_VENDOR_MEDIATEK=y
+CONFIG_NET_AIROHA=m
+CONFIG_NET_MEDIATEK_SOC=m
+CONFIG_NET_MEDIATEK_STAR_EMAC=m
+CONFIG_NET_VENDOR_MELLANOX=y
+CONFIG_MLX4_EN=m
+CONFIG_MLX4_EN_DCB=y
+CONFIG_MLX4_CORE=m
+# CONFIG_MLX4_DEBUG is not set
+CONFIG_MLX4_CORE_GEN2=y
+CONFIG_MLX5_CORE=m
+CONFIG_MLX5_MACSEC=y
+CONFIG_MLX5_FPGA=y
+CONFIG_MLX5_CORE_EN=y
+CONFIG_MLX5_DPLL=m
+CONFIG_MLX5_EN_PSP=y
+CONFIG_MLX5_EN_ARFS=y
+CONFIG_MLX5_EN_RXNFC=y
+CONFIG_MLX5_MPFS=y
+CONFIG_MLX5_ESWITCH=y
+CONFIG_MLX5_BRIDGE=y
+CONFIG_MLX5_CORE_EN_DCB=y
+CONFIG_MLX5_CORE_IPOIB=y
+CONFIG_MLX5_EN_MACSEC=y
+CONFIG_MLX5_EN_IPSEC=y
+CONFIG_MLX5_EN_TLS=y
+CONFIG_MLX5_SW_STEERING=y
+CONFIG_MLX5_HW_STEERING=y
+CONFIG_MLX5_SF=y
+CONFIG_MLX5_SF_MANAGER=y
+CONFIG_MLXSW_CORE=m
+CONFIG_MLXSW_CORE_HWMON=y
+CONFIG_MLXSW_CORE_THERMAL=y
+CONFIG_MLXSW_PCI=m
+CONFIG_MLXSW_I2C=m
+CONFIG_MLXSW_SPECTRUM=m
+CONFIG_MLXSW_SPECTRUM_DCB=y
+CONFIG_MLXSW_MINIMAL=m
+CONFIG_MLXFW=m
+CONFIG_NET_VENDOR_META=y
+CONFIG_FBNIC=m
+CONFIG_MLXBF_GIGE=m
+CONFIG_NET_VENDOR_MICREL=y
+CONFIG_KS8842=m
+CONFIG_KS8851=m
+CONFIG_KS8851_MLL=m
+CONFIG_KSZ884X_PCI=m
+CONFIG_NET_VENDOR_MICROCHIP=y
+CONFIG_ENC28J60=m
+# CONFIG_ENC28J60_WRITEVERIFY is not set
+CONFIG_ENCX24J600=m
+CONFIG_LAN743X=m
+CONFIG_LAN865X=m
+CONFIG_LAN966X_SWITCH=m
+CONFIG_LAN966X_DCB=y
+CONFIG_SPARX5_SWITCH=m
+CONFIG_SPARX5_DCB=y
+CONFIG_VCAP=y
+CONFIG_FDMA=y
+CONFIG_NET_VENDOR_MICROSEMI=y
+CONFIG_MSCC_OCELOT_SWITCH=m
+CONFIG_MSCC_OCELOT_SWITCH_LIB=m
+CONFIG_NET_VENDOR_MICROSOFT=y
+CONFIG_MICROSOFT_MANA=m
+CONFIG_NET_VENDOR_MYRI=y
+CONFIG_MYRI10GE=m
+CONFIG_MYRI10GE_DCA=y
+CONFIG_FEALNX=m
+CONFIG_NET_VENDOR_NI=y
+CONFIG_NI_XGE_MANAGEMENT_ENET=m
+CONFIG_NET_VENDOR_NATSEMI=y
+CONFIG_NATSEMI=m
+CONFIG_NS83820=m
+CONFIG_NET_VENDOR_NETERION=y
+CONFIG_S2IO=m
+CONFIG_NET_VENDOR_NETRONOME=y
+CONFIG_NFP=m
+# CONFIG_NFP_APP_FLOWER is not set
+CONFIG_NFP_APP_ABM_NIC=y
+CONFIG_NFP_NET_IPSEC=y
+# CONFIG_NFP_DEBUG is not set
+CONFIG_NET_VENDOR_8390=y
+CONFIG_PCMCIA_AXNET=m
+CONFIG_NE2000=m
+CONFIG_ULTRA=m
+CONFIG_WD80x3=m
+CONFIG_AX88796=m
+CONFIG_AX88796_93CX6=y
+CONFIG_NE2K_PCI=m
+CONFIG_PCMCIA_PCNET=m
+CONFIG_NET_VENDOR_NVIDIA=y
+CONFIG_FORCEDETH=m
+CONFIG_NET_VENDOR_OKI=y
+CONFIG_PCH_GBE=m
+CONFIG_ETHOC=m
+CONFIG_OA_TC6=m
+CONFIG_NET_VENDOR_PACKET_ENGINES=y
+CONFIG_HAMACHI=m
+CONFIG_YELLOWFIN=m
+CONFIG_NET_VENDOR_PENSANDO=y
+CONFIG_IONIC=m
+CONFIG_NET_VENDOR_QLOGIC=y
+CONFIG_QLA3XXX=m
+CONFIG_QLCNIC=m
+CONFIG_QLCNIC_SRIOV=y
+CONFIG_QLCNIC_DCB=y
+CONFIG_QLCNIC_HWMON=y
+CONFIG_NETXEN_NIC=m
+CONFIG_QED=m
+CONFIG_QED_LL2=y
+CONFIG_QED_SRIOV=y
+CONFIG_QEDE=m
+CONFIG_QED_RDMA=y
+CONFIG_QED_ISCSI=y
+CONFIG_QED_FCOE=y
+CONFIG_QED_OOO=y
+CONFIG_NET_VENDOR_BROCADE=y
+CONFIG_BNA=m
+CONFIG_NET_VENDOR_QUALCOMM=y
+CONFIG_QCA7000_SPI=m
+CONFIG_QCA7000_UART=m
+CONFIG_QCOM_EMAC=m
+CONFIG_QCOM_PPE=m
+CONFIG_RMNET=m
+CONFIG_NET_VENDOR_RDC=y
+CONFIG_R6040=m
+CONFIG_NET_VENDOR_REALTEK=y
+CONFIG_ATP=m
+CONFIG_8139CP=m
+CONFIG_8139TOO=m
+# CONFIG_8139TOO_PIO is not set
+CONFIG_8139TOO_TUNE_TWISTER=y
+CONFIG_8139TOO_8129=y
+# CONFIG_8139_OLD_RX_RESET is not set
+CONFIG_R8169=m
+CONFIG_R8169_LEDS=y
+CONFIG_RTASE=m
+CONFIG_NET_VENDOR_RENESAS=y
+CONFIG_SH_ETH=m
+CONFIG_RAVB=m
+CONFIG_RENESAS_ETHER_SWITCH=m
+CONFIG_RTSN=m
+CONFIG_NET_VENDOR_ROCKER=y
+CONFIG_ROCKER=m
+CONFIG_NET_VENDOR_SAMSUNG=y
+CONFIG_SXGBE_ETH=m
+CONFIG_NET_VENDOR_SEEQ=y
+CONFIG_NET_VENDOR_SILAN=y
+CONFIG_SC92031=m
+CONFIG_NET_VENDOR_SIS=y
+CONFIG_SIS900=m
+CONFIG_SIS190=m
+CONFIG_NET_VENDOR_SOLARFLARE=y
+CONFIG_SFC=m
+CONFIG_SFC_MTD=y
+CONFIG_SFC_MCDI_MON=y
+CONFIG_SFC_SRIOV=y
+CONFIG_SFC_MCDI_LOGGING=y
+CONFIG_SFC_FALCON=m
+CONFIG_SFC_FALCON_MTD=y
+CONFIG_SFC_SIENA=m
+CONFIG_SFC_SIENA_MTD=y
+CONFIG_SFC_SIENA_MCDI_MON=y
+CONFIG_SFC_SIENA_SRIOV=y
+# CONFIG_SFC_SIENA_MCDI_LOGGING is not set
+CONFIG_NET_VENDOR_SMSC=y
+CONFIG_SMC9194=m
+CONFIG_SMC91X=m
+CONFIG_PCMCIA_SMC91C92=m
+CONFIG_EPIC100=m
+CONFIG_SMSC911X=m
+CONFIG_SMSC9420=m
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+CONFIG_NET_VENDOR_STMICRO=y
+CONFIG_STMMAC_ETH=m
+# CONFIG_STMMAC_SELFTESTS is not set
+CONFIG_STMMAC_PLATFORM=m
+CONFIG_DWMAC_DWC_QOS_ETH=m
+CONFIG_DWMAC_GENERIC=m
+CONFIG_DWMAC_IPQ806X=m
+CONFIG_DWMAC_MEDIATEK=m
+CONFIG_DWMAC_MESON=m
+CONFIG_DWMAC_QCOM_ETHQOS=m
+CONFIG_DWMAC_RENESAS_GBETH=m
+CONFIG_DWMAC_ROCKCHIP=m
+CONFIG_DWMAC_S32=m
+CONFIG_DWMAC_SOCFPGA=m
+CONFIG_DWMAC_SOPHGO=m
+CONFIG_DWMAC_STI=m
+CONFIG_DWMAC_STM32=m
+CONFIG_DWMAC_SUNXI=m
+CONFIG_DWMAC_SUN8I=m
+CONFIG_DWMAC_SUN55I=m
+CONFIG_DWMAC_IMX8=m
+CONFIG_DWMAC_INTEL_PLAT=m
+CONFIG_DWMAC_INTEL=m
+CONFIG_DWMAC_TEGRA=m
+CONFIG_DWMAC_VISCONTI=m
+CONFIG_DWMAC_LOONGSON=m
+CONFIG_STMMAC_PCI=m
+CONFIG_NET_VENDOR_SUN=y
+CONFIG_HAPPYMEAL=m
+CONFIG_SUNGEM=m
+CONFIG_CASSINI=m
+CONFIG_NIU=m
+CONFIG_NET_VENDOR_SYNOPSYS=y
+CONFIG_DWC_PCIE_PMU=m
+CONFIG_DWC_XLGMAC=m
+CONFIG_DWC_XLGMAC_PCI=m
+CONFIG_NET_VENDOR_TEHUTI=y
+CONFIG_TEHUTI=m
+CONFIG_TEHUTI_TN40=m
+CONFIG_NET_VENDOR_TI=y
+CONFIG_TI_DAVINCI_EMAC=m
+CONFIG_TI_DAVINCI_MDIO=m
+# CONFIG_TI_CPSW_PHY_SEL is not set
+CONFIG_TI_K3_AM65_CPTS=m
+CONFIG_TI_CPSW=m
+CONFIG_TI_CPSW_SWITCHDEV=m
+CONFIG_TI_CPTS=m
+CONFIG_TLAN=m
+CONFIG_TI_ICSS_IEP=m
+CONFIG_TI_PRUETH=m
+CONFIG_NET_VENDOR_VERTEXCOM=y
+CONFIG_MSE102X=m
+CONFIG_NET_VENDOR_VIA=y
+CONFIG_VIA_RHINE=m
+CONFIG_VIA_RHINE_MMIO=y
+CONFIG_VIA_VELOCITY=m
+CONFIG_NET_VENDOR_WANGXUN=y
+CONFIG_LIBWX=m
+CONFIG_NGBE=m
+CONFIG_TXGBE=m
+CONFIG_TXGBEVF=m
+CONFIG_NGBEVF=m
+CONFIG_NET_VENDOR_WIZNET=y
+CONFIG_WIZNET_W5100=m
+CONFIG_WIZNET_W5300=m
+# CONFIG_WIZNET_BUS_DIRECT is not set
+# CONFIG_WIZNET_BUS_INDIRECT is not set
+CONFIG_WIZNET_BUS_ANY=y
+CONFIG_WIZNET_W5100_SPI=m
+CONFIG_NET_VENDOR_XILINX=y
+CONFIG_XILINX_EMACLITE=m
+CONFIG_XILINX_AXI_EMAC=m
+CONFIG_XILINX_LL_TEMAC=m
+CONFIG_NET_VENDOR_XIRCOM=y
+CONFIG_PCMCIA_XIRC2PS=m
+CONFIG_RTW89=m
+CONFIG_RTW89_8851BE=m
+CONFIG_RTW89_8851BU=m
+CONFIG_RTW89_8852BE=m
+CONFIG_RTW89_8852BU=m
+CONFIG_FDDI=m
+CONFIG_DEFXX=m
+CONFIG_SKFP=m
+CONFIG_HIPPI=y
+CONFIG_ROADRUNNER=m
+CONFIG_ROADRUNNER_LARGE_RINGS=y
+CONFIG_QCOM_IPA=m
+CONFIG_NET_SB1000=m
+CONFIG_PHYLINK=m
+CONFIG_PHYLIB=m
+CONFIG_SWPHY=y
+CONFIG_LED_TRIGGER_PHY=y
+CONFIG_FIXED_PHY=m
+CONFIG_SFP=m
+CONFIG_AS21XXX_PHY=m
+CONFIG_NETLABEL=y
+# CONFIG_MPTCP_KUNIT_TEST is not set
+CONFIG_NETFILTER_XT_TARGET_AUDIT=m
+CONFIG_IP_NF_SECURITY=m
+CONFIG_IP6_NF_SECURITY=m
+CONFIG_ATM_DRIVERS=y
+CONFIG_ATM_DUMMY=m
+CONFIG_ATM_TCP=m
+CONFIG_ATM_LANAI=m
+CONFIG_ATM_ENI=m
+# CONFIG_ATM_ENI_DEBUG is not set
+# CONFIG_ATM_ENI_TUNE_BURST is not set
+CONFIG_ATM_NICSTAR=m
+CONFIG_ATM_NICSTAR_USE_SUNI=y
+CONFIG_ATM_NICSTAR_USE_IDT77105=y
+CONFIG_ATM_IDT77252=m
+# CONFIG_ATM_IDT77252_DEBUG is not set
+# CONFIG_ATM_IDT77252_RCV_ALL is not set
+CONFIG_ATM_IA=m
+# CONFIG_ATM_IA_DEBUG is not set
+CONFIG_ATM_FORE200E=m
+CONFIG_ATM_FORE200E_USE_TASKLET=y
+CONFIG_ATM_FORE200E_TX_RETRY=16
+CONFIG_ATM_FORE200E_DEBUG=0
+CONFIG_ATM_HE=m
+CONFIG_ATM_HE_USE_SUNI=y
+CONFIG_ATM_SOLOS=m
+CONFIG_IEEE802154_DRIVERS=m
+CONFIG_IEEE802154_FAKELB=m
+CONFIG_IEEE802154_AT86RF230=m
+CONFIG_IEEE802154_MRF24J40=m
+CONFIG_IEEE802154_CC2520=m
+CONFIG_IEEE802154_ATUSB=m
+CONFIG_IEEE802154_ADF7242=m
+CONFIG_IEEE802154_CA8210=m
+# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
+CONFIG_IEEE802154_MCR20A=m
+CONFIG_IEEE802154_HWSIM=m
+CONFIG_ATH12K_AHB=y
+CONFIG_CZNIC_PLATFORMS=y
diff --git a/nexus-compile.patch b/nexus-compile.patch
new file mode 100644
index 0000000..fb52d17
--- /dev/null
+++ b/nexus-compile.patch
@@ -0,0 +1,30 @@
+diff -up linux-7.0/drivers/nexus/nexus_core.c.omv~ linux-7.0/drivers/nexus/nexus_core.c
+--- linux-7.0/drivers/nexus/nexus_core.c.omv~	2026-04-19 19:38:01.566810321 +0200
++++ linux-7.0/drivers/nexus/nexus_core.c	2026-04-19 19:39:18.332054133 +0200
+@@ -30,6 +30,9 @@ static int major = -1;
+ static struct cdev nexus_cdev;
+ static struct class *nexus_class = NULL;
+ 
++struct nexus_thread* find_thread(struct nexus_team *team, const char *name);
++struct nexus_thread* find_thread_by_id(struct nexus_team *team, int32_t pid);
++
+ DEFINE_MUTEX(nexus_main_lock);
+ HLIST_HEAD(nexus_teams);
+ 
+@@ -79,7 +82,7 @@ static void nexus_thread_exit_work(struc
+ 	mutex_unlock(&nexus_main_lock);
+ }
+ 
+-struct nexus_team* nexus_team_init()
++struct nexus_team* nexus_team_init(void)
+ {
+ 	struct nexus_team* team = kzalloc(sizeof(struct nexus_team), GFP_KERNEL);
+ 	if (team != NULL) {
+@@ -759,7 +762,6 @@ static int nexus_open(struct inode *nodp
+ 
+ static int nexus_release(struct inode *nodp, struct file *filp)
+ {
+-	struct nexus_team *team = filp->private_data;
+ 	mutex_lock(&nexus_main_lock);
+ 	nexus_team_destroy((struct nexus_team*)filp->private_data);
+ 	mutex_unlock(&nexus_main_lock);
diff --git a/nvme.fragment b/nvme.fragment
new file mode 100644
index 0000000..3a46c1a
--- /dev/null
+++ b/nvme.fragment
@@ -0,0 +1,29 @@
+#
+# NVME Support
+#
+CONFIG_NVME_COMMON=m
+CONFIG_NVME_CORE=m
+CONFIG_BLK_DEV_NVME=m
+# CONFIG_NVME_MULTIPATH is not set
+CONFIG_NVME_VERBOSE_ERRORS=y
+CONFIG_NVME_HWMON=y
+CONFIG_NVME_FABRICS=m
+CONFIG_NVME_RDMA=m
+CONFIG_NVME_FC=m
+CONFIG_NVME_TCP=m
+CONFIG_NVME_TCP_TLS=y
+CONFIG_NVME_HOST_AUTH=y
+CONFIG_NVME_APPLE=m
+CONFIG_NVME_AUTH=y
+CONFIG_NVME_TARGET=m
+# CONFIG_NVME_TARGET_DEBUGFS is not set
+CONFIG_NVME_TARGET_PASSTHRU=y
+CONFIG_NVME_TARGET_LOOP=m
+CONFIG_NVME_TARGET_RDMA=m
+CONFIG_NVME_TARGET_FC=m
+CONFIG_NVME_TARGET_FCLOOP=m
+CONFIG_NVME_TARGET_TCP=m
+CONFIG_NVME_TARGET_TCP_TLS=y
+CONFIG_NVME_TARGET_AUTH=y
+CONFIG_NVME_TARGET_PCI_EPF=m
+# end of NVME Support
diff --git a/perf-5.19-binutils-2.39.patch b/perf-5.19-binutils-2.39.patch
deleted file mode 100644
index dcc893b..0000000
--- a/perf-5.19-binutils-2.39.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-diff -up linux-5.19/tools/perf/util/annotate.c.omv~ linux-5.19/tools/perf/util/annotate.c
---- linux-5.19/tools/perf/util/annotate.c.omv~	2022-08-15 00:35:15.350592278 +0200
-+++ linux-5.19/tools/perf/util/annotate.c	2022-08-15 00:36:05.070974048 +0200
-@@ -64,6 +64,21 @@ struct annotation_options annotation__de
- 	.percent_type	= PERCENT_PERIOD_LOCAL,
- };
- 
-+#include <dis-asm.h>
-+static int __attribute__ ((__format__ (__printf__, 3, 4))) __attribute__((__nonnull__ (3)))
-+fprintf_styled (FILE *f, enum disassembler_style style __attribute__((unused)),
-+                const char *fmt, ...)
-+{
-+	int res;
-+	va_list ap;
-+
-+	va_start (ap, fmt);
-+	res = vfprintf (f, fmt, ap);
-+	va_end (ap);
-+
-+	return res;
-+}
-+
- static regex_t	 file_lineno;
- 
- static struct ins_ops *ins__find(struct arch *arch, const char *name);
-@@ -1763,7 +1778,7 @@ static int symbol__disassemble_bpf(struc
- 		goto out;
- 	}
- 	init_disassemble_info(&info, s,
--			      (fprintf_ftype) fprintf);
-+			      (fprintf_ftype) fprintf, (fprintf_styled_ftype) fprintf_styled);
- 
- 	info.arch = bfd_get_arch(bfdf);
- 	info.mach = bfd_get_mach(bfdf);
diff --git a/powerpc-common.config b/powerpc-common.config
deleted file mode 100644
index 0fe6406..0000000
--- a/powerpc-common.config
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_PPC64=y
diff --git a/powerpc-omv-defconfig b/powerpc-omv-defconfig
new file mode 100644
index 0000000..adf1dff
--- /dev/null
+++ b/powerpc-omv-defconfig
@@ -0,0 +1,1445 @@
+CONFIG_64BIT=y
+CONFIG_842_DECOMPRESS=y
+CONFIG_ACENIC=m
+CONFIG_ACENIC_OMIT_TIGON_I=y
+CONFIG_ADB_PMU_EVENT=y
+CONFIG_ADB_PMU=y
+CONFIG_AF_RXRPC=m
+CONFIG_ALLOW_DEV_COREDUMP=y
+CONFIG_ALTIVEC=y
+CONFIG_APERTURE_HELPERS=y
+CONFIG_ARCH_CPU_PROBE_RELEASE=y
+CONFIG_ARCH_DISABLE_KASAN_INLINE=y
+CONFIG_ARCH_DMA_DEFAULT_COHERENT=y
+CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
+CONFIG_ARCH_ENABLE_THP_MIGRATION=y
+CONFIG_ARCH_FORCE_MAX_ORDER=8
+CONFIG_ARCH_HAS_ADD_PAGES=y
+CONFIG_ARCH_HAS_CC_PLATFORM=y
+CONFIG_ARCH_HAS_COPY_MC=y
+CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
+CONFIG_ARCH_HAS_DEBUG_WX=y
+CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
+CONFIG_ARCH_HAS_DMA_MAP_DIRECT=y
+CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_HUGEPD=y
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_ARCH_HAS_MEMBARRIER_CALLBACKS=y
+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
+CONFIG_ARCH_HAS_MEM_ENCRYPT=y
+CONFIG_ARCH_HAS_MEMREMAP_COMPAT_ALIGN=y
+CONFIG_ARCH_HAS_MMIOWB=y
+CONFIG_ARCH_HAS_PHYS_TO_DMA=y
+CONFIG_ARCH_HAS_PKEYS=y
+CONFIG_ARCH_HAS_PMEM_API=y
+CONFIG_ARCH_HAS_PTE_DEVMAP=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y
+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_ARCH_MEMORY_PROBE=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS=14
+CONFIG_ARCH_MMAP_RND_BITS_MAX=29
+CONFIG_ARCH_MMAP_RND_BITS_MIN=14
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=7
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=13
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=7
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SELECTS_CRASH_DUMP=y
+CONFIG_ARCH_SELECTS_KEXEC_FILE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y
+CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY=y
+CONFIG_ARCH_SUPPORTS_KEXEC=y
+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
+CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y
+CONFIG_ARCH_SUSPEND_NONZERO_CPU=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_USE_MEMTEST=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
+CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
+CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARCH_WANT_IRQS_OFF_ACTIVATE_MM=y
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
+CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y
+CONFIG_ARCH_WANT_OPTIMIZE_DAX_VMEMMAP=y
+CONFIG_ARCH_WANT_PMD_MKWRITE=y
+CONFIG_ARCH_WANTS_FREEZER_CONTROL=y
+CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y
+CONFIG_AS_IS_GNU=y
+CONFIG_AS_VERSION=24100
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_ASYNC_RAID6_TEST=m
+CONFIG_ASYNC_XOR=m
+CONFIG_ATA_FORCE=y
+CONFIG_ATA_GENERIC=y
+CONFIG_ATA_NONSTANDARD=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_ATA=y
+CONFIG_ATOMIC64_SELFTEST=m
+CONFIG_AUDIT_ARCH=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT=y
+CONFIG_AUXILIARY_BUS=y
+CONFIG_AXON_MSI=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKTRACE_SELF_TEST=m
+CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM=y
+CONFIG_BATTERY_BQ27XXX_HDQ=m
+CONFIG_BATTERY_BQ27XXX_I2C=m
+CONFIG_BATTERY_BQ27XXX=m
+CONFIG_BATTERY_CW2015=m
+CONFIG_BATTERY_DS2760=m
+CONFIG_BATTERY_DS2780=m
+CONFIG_BATTERY_DS2781=m
+CONFIG_BATTERY_DS2782=m
+CONFIG_BATTERY_GAUGE_LTC2941=m
+CONFIG_BATTERY_GOLDFISH=m
+CONFIG_BATTERY_MAX17042=m
+CONFIG_BATTERY_MAX1721X=m
+CONFIG_BATTERY_RT5033=m
+CONFIG_BATTERY_SAMSUNG_SDI=y
+CONFIG_BATTERY_SBS=m
+CONFIG_BATTERY_UG3105=m
+CONFIG_BCM2712_MIP=m
+CONFIG_BCM_NET_PHYLIB=m
+CONFIG_BE2ISCSI=m
+CONFIG_BE2NET_BE2=y
+CONFIG_BE2NET_BE3=y
+CONFIG_BE2NET_HWMON=y
+CONFIG_BE2NET_LANCER=y
+CONFIG_BE2NET=m
+CONFIG_BE2NET_SKYHAWK=y
+CONFIG_BINFMT_MISC=m
+CONFIG_BITFIELD_KUNIT=m
+CONFIG_BITS_TEST=m
+CONFIG_BLK_CGROUP_PUNT_BIO=y
+CONFIG_BLK_CGROUP=y
+CONFIG_BLK_DEBUG_FS=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_BLK_DEV_FD=y
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_BLK_DEV_MD=y
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_PMEM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_MQ_STACKING=y
+CONFIG_BLOCK_HOLDER_DEPRECATED=y
+CONFIG_BNX2=m
+CONFIG_BNX2X=m
+CONFIG_BONDING=m
+CONFIG_BOOTX_TEXT=y
+CONFIG_BPF_EVENTS=y
+CONFIG_BPF_JIT_DEFAULT_ON=y
+CONFIG_BPF_LSM=y
+CONFIG_BPF_UNPRIV_DEFAULT_OFF=y
+CONFIG_BRANCH_PROFILE_NONE=y
+CONFIG_BROADCOM_PHY=m
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BTREE=y
+CONFIG_BTT=y
+CONFIG_BUG_ON_DATA_CORRUPTION=y
+CONFIG_BUG=y
+CONFIG_BUILD_SALT=""
+CONFIG_CARDBUS=y
+CONFIG_CBE_CPUFREQ_SPU_GOVERNOR=m
+CONFIG_CBE_RAS=y
+CONFIG_CBE_THERM=m
+CONFIG_CC_CAN_LINK_STATIC=y
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
+CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
+CONFIG_CC_HAS_INT128=y
+CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
+CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_IS_GCC=y
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+CONFIG_CC_VERSION_TEXT="gcc (GCC) 13.1.1 20230722 (OpenMandriva)"
+CONFIG_CDROM=y
+CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CGROUP_MISC=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_WRITEBACK=y
+CONFIG_CHARGER_ADP5061=m
+CONFIG_CHARGER_BD99954=m
+CONFIG_CHARGER_BQ2415X=m
+CONFIG_CHARGER_BQ24257=m
+CONFIG_CHARGER_BQ24735=m
+CONFIG_CHARGER_BQ2515X=m
+CONFIG_CHARGER_BQ256XX=m
+CONFIG_CHARGER_BQ25890=m
+CONFIG_CHARGER_BQ25980=m
+CONFIG_CHARGER_DETECTOR_MAX14656=m
+CONFIG_CHARGER_GPIO=m
+CONFIG_CHARGER_LP8727=m
+CONFIG_CHARGER_LT3651=m
+CONFIG_CHARGER_LTC4162L=m
+CONFIG_CHARGER_MAX77976=m
+CONFIG_CHARGER_MAX8903=m
+CONFIG_CHARGER_RT9455=m
+CONFIG_CHARGER_SBS=m
+CONFIG_CHECKSUM_KUNIT=m
+CONFIG_CHELSIO_INLINE_CRYPTO=y
+CONFIG_CHELSIO_LIB=m
+CONFIG_CHELSIO_T1=m
+CONFIG_CHELSIO_T3=m
+CONFIG_CHELSIO_T4=m
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_CLANG_VERSION=0
+CONFIG_CLKBLD_I8253=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA_AREAS=19
+CONFIG_CMA=y
+CONFIG_CMDLINE=""
+CONFIG_CMDLINE_KUNIT_TEST=m
+CONFIG_CMM=y
+CONFIG_CNIC=m
+CONFIG_CODE_PATCHING_SELFTEST=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+CONFIG_COMPAT=y
+CONFIG_CONNECTOR=m
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTEXT_TRACKING_USER=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_FREQ_CBE=m
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_PMAC64=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPUMASK_KUNIT_TEST=m
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRASH_HOTPLUG=y
+CONFIG_CRASH_MAX_MEMORY_RANGES=8192
+CONFIG_CRC16=y
+CONFIG_CRC_BENCHMARK=y
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC_KUNIT_TEST=m
+CONFIG_CRC_T10DIF=m
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_BLAKE2B=m
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_CAST_COMMON=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CMAC=m
+CONFIG_CRYPTO_CRC32C_VPMSUM=m
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC64_ROCKSOFT=m
+CONFIG_CRYPTO_CRCT10DIF=m
+CONFIG_CRYPTO_CRCT10DIF_VPMSUM=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_DEV_NX_COMPRESS_POWERNV=y
+CONFIG_CRYPTO_DEV_NX_COMPRESS_PSERIES=y
+CONFIG_CRYPTO_DEV_NX_COMPRESS=y
+CONFIG_CRYPTO_DEV_NX_ENCRYPT=m
+CONFIG_CRYPTO_DEV_NX=y
+CONFIG_CRYPTO_DEV_VMX_ENCRYPT=m
+CONFIG_CRYPTO_DEV_VMX=y
+CONFIG_CRYPTO_DRBG=m
+CONFIG_CRYPTO_DRBG_MENU=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_ECHAINIV=m
+CONFIG_CRYPTO_ESSIV=m
+CONFIG_CRYPTO_GENIV=m
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY=m
+CONFIG_CRYPTO_LIB_AES=m
+CONFIG_CRYPTO_LIB_BENCHMARK=y
+CONFIG_CRYPTO_LIB_GF128MUL=m
+CONFIG_CRYPTO_LIB_POLY1305_KUNIT_TEST=m
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
+CONFIG_CRYPTO_LIB_SHA1_KUNIT_TEST=m
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256_KUNIT_TEST=m
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_SHA512_KUNIT_TEST=m
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_MD5=m
+CONFIG_CRYPTO_MD5_PPC=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_NULL2=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_RNG_DEFAULT=m
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_SHA1_PPC=m
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA3=m
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SIG2=y
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_VPMSUM_TESTER=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_XXHASH=m
+CONFIG_CXL_BASE=y
+CONFIG_CXLFLASH=m
+CONFIG_CXL=m
+CONFIG_DATA_SHIFT=24
+CONFIG_DAX=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_FS_ALLOW_ALL=y
+CONFIG_DEBUGGER=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_MISC=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_RODATA_TEST=y
+CONFIG_DEBUG_STACKOVERFLOW=y
+CONFIG_DEBUG_STACK_USAGE=y
+CONFIG_DEBUG_VM_IRQSOFF=y
+CONFIG_DEBUG_VM=y
+CONFIG_DEBUG_WX=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_DEFAULT_SECURITY_SELINUX=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEVICE_MIGRATION=y
+CONFIG_DIMLIB=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_DMA_OPS_BYPASS=y
+CONFIG_DMA_OPS=y
+CONFIG_DM_CACHE=m
+CONFIG_DM_CACHE_SMQ=m
+CONFIG_DM_CLONE=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_DELAY=m
+CONFIG_DM_DUST=m
+CONFIG_DM_EBS=m
+CONFIG_DM_ERA=m
+CONFIG_DM_INIT=y
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_MULTIPATH_HST=m
+CONFIG_DM_MULTIPATH_IOA=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_RAID=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_UEVENT=y
+CONFIG_DM_UNSTRIPED=m
+CONFIG_DM_WRITECACHE=m
+CONFIG_DM_ZERO=m
+CONFIG_DP83640_PHY=m
+CONFIG_DP83TG720_PHY=m
+CONFIG_DRM_PANEL_ILITEK_ILI9341=m
+CONFIG_DTC=y
+CONFIG_DTL=y
+CONFIG_DUMMY_CONSOLE_ROWS=30
+CONFIG_DUMMY=m
+CONFIG_DWC_PCIE_PMU=m
+CONFIG_DYNAMIC_EVENTS=y
+CONFIG_DYNAMIC_FTRACE=y
+CONFIG_E1000E=y
+CONFIG_E1000=y
+CONFIG_E100=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_ECS=y
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC_MEM_REPAIR=y
+CONFIG_EDAC_PASEMI=y
+CONFIG_EDAC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EDAC=y
+CONFIG_EEH=y
+CONFIG_EHEA=m
+CONFIG_ELECTRA_CF=y
+CONFIG_EPAPR_BOOT=y
+CONFIG_EPROBE_EVENTS=y
+CONFIG_ETHERNET=y
+CONFIG_EVENT_TRACING=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXTRA_TARGETS=""
+CONFIG_FA_DUMP=y
+CONFIG_FAILOVER=m
+CONFIG_FB_BACKLIGHT=y
+CONFIG_FB_CORE=y
+CONFIG_FB_DDC=y
+CONFIG_FB_DEVICE=y
+CONFIG_FB_IBM_GXT4500=y
+CONFIG_FB_IOMEM_HELPERS=y
+CONFIG_FB_LOGO_EXTRA=y
+CONFIG_FB_MACMODES=y
+CONFIG_FB_MATROX_G=y
+CONFIG_FB_MATROX_I2C=m
+CONFIG_FB_MATROX_MAVEN=m
+CONFIG_FB_MATROX_MILLENIUM=y
+CONFIG_FB_MATROX_MYSTIQUE=y
+CONFIG_FB_MATROX=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_OF=y
+CONFIG_FB_PS3_DEFAULT_SIZE_M=9
+CONFIG_FB_PS3=m
+CONFIG_FB_RADEON_BACKLIGHT=y
+CONFIG_FB_RADEON_I2C=y
+CONFIG_FB_RADEON=y
+CONFIG_FB_SYS_COPYAREA=m
+CONFIG_FB_SYS_FILLRECT=m
+CONFIG_FB_SYS_FOPS=m
+CONFIG_FB_SYS_IMAGEBLIT=m
+CONFIG_FB_TILEBLITTING=y
+CONFIG_FIND_BIT_BENCHMARK=m
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FIXED_PHY=y
+CONFIG_FORCE_PCI=y
+CONFIG_FORCE_SMP=y
+CONFIG_FTRACE_MCOUNT_RECORD=y
+CONFIG_FTRACE_MCOUNT_USE_CC=y
+CONFIG_FTRACE_SYSCALLS=y
+CONFIG_FTRACE=y
+CONFIG_FTR_FIXUP_SELFTEST=y
+CONFIG_FUEL_GAUGE_MM8013=m
+CONFIG_FUEL_GAUGE_STC3117=m
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FUNCTION_GRAPH_RETVAL=y
+CONFIG_FUNCTION_GRAPH_TRACER=y
+CONFIG_FUNCTION_TRACER=y
+CONFIG_FW_CS_DSP_KUNIT_TEST=m
+CONFIG_FWNODE_MDIO=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_VERSION=130101
+CONFIG_GELIC_NET=m
+CONFIG_GELIC_WIRELESS=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PTDUMP=y
+CONFIG_GENERIC_TBSYNC=y
+CONFIG_GENERIC_TRACER=y
+CONFIG_GENERIC_VDSO_TIME_NS=y
+CONFIG_GPIO_ADP5585=m
+CONFIG_GPIO_CROS_EC=m
+CONFIG_GP_PCI1XXXX=m
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HARDLOCKUP_DETECTOR_ARCH=y
+CONFIG_HARDLOCKUP_DETECTOR=y
+CONFIG_HASH_KUNIT_TEST=m
+CONFIG_HASHTABLE_KUNIT_TEST=m
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HIBERNATION_LZO=y
+CONFIG_HMM_MIRROR=y
+CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
+CONFIG_HOTPLUG_PCI_RPA=m
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_SMT=y
+CONFIG_HTMDUMP=m
+CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y
+CONFIG_HVC_CONSOLE=y
+CONFIG_HVC_IRQ=y
+CONFIG_HVC_OPAL=y
+CONFIG_HVC_RTAS=y
+CONFIG_HVCS=m
+CONFIG_HV_PERF_CTRS=y
+CONFIG_HW_RANDOM_AMD=m
+CONFIG_HW_RANDOM=m
+CONFIG_HW_RANDOM_PASEMI=m
+CONFIG_HW_RANDOM_POWERNV=m
+CONFIG_HW_RANDOM_PSERIES=m
+CONFIG_HZ=100
+CONFIG_HZ_100=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_AMD8111=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE_CORE=m
+CONFIG_I2C_DESIGNWARE_SLAVE=y
+CONFIG_I2C_LJCA=m
+CONFIG_I2C_NCT6694=m
+CONFIG_I2C_OPAL=y
+CONFIG_I2C_PASEMI=y
+CONFIG_I2C_POWERMAC=y
+CONFIG_I2C_SLAVE_EEPROM=m
+CONFIG_I2C=y
+CONFIG_I40E=m
+CONFIG_I8253_LOCK=y
+CONFIG_IBM_BSR=m
+CONFIG_IBMEBUS=y
+CONFIG_IBMVETH=m
+CONFIG_IBMVIO=y
+CONFIG_IBMVNIC=m
+CONFIG_ICE_HWMON=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
+CONFIG_ILLEGAL_POINTER_VALUE=0x5deadbeef0000000
+CONFIG_IMA_APPRAISE_BOOTPARAM=y
+CONFIG_IMA_APPRAISE_MODSIG=y
+CONFIG_IMA_APPRAISE=y
+CONFIG_IMA_ARCH_POLICY=y
+CONFIG_IMA_DEFAULT_HASH="sha256"
+CONFIG_IMA_DEFAULT_HASH_SHA256=y
+CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng"
+CONFIG_IMA_KEXEC_EXTRA_MEMORY_KB=0
+CONFIG_IMA_KEXEC=y
+CONFIG_IMA_LSM_RULES=y
+CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y
+CONFIG_IMA_MEASURE_PCR_IDX=10
+CONFIG_IMA_NG_TEMPLATE=y
+CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y
+CONFIG_IMA_READ_POLICY=y
+CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT=y
+CONFIG_IMA_WRITE_POLICY=y
+CONFIG_IMA=y
+CONFIG_INFINIBAND_ADDR_TRANS=y
+CONFIG_INFINIBAND_BNXT_RE=m
+CONFIG_INFINIBAND_CXGB4=m
+CONFIG_INFINIBAND_IONIC=m
+CONFIG_INFINIBAND_IPOIB_CM=y
+CONFIG_INFINIBAND_IPOIB_DEBUG=y
+CONFIG_INFINIBAND_IPOIB=m
+CONFIG_INFINIBAND_IRDMA=m
+CONFIG_INFINIBAND_ISER=m
+CONFIG_INFINIBAND=m
+CONFIG_INFINIBAND_MTHCA_DEBUG=y
+CONFIG_INFINIBAND_MTHCA=m
+CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
+CONFIG_INFINIBAND_QEDR=m
+CONFIG_INFINIBAND_SRP=m
+CONFIG_INFINIBAND_USER_ACCESS=m
+CONFIG_INFINIBAND_USER_MAD=m
+CONFIG_INFINIBAND_USER_MEM=y
+CONFIG_INFINIBAND_VIRT_DMA=y
+CONFIG_INIT_STACK_ALL_ZERO=y
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_INLINE_READ_UNLOCK=y
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK=y
+CONFIG_INPUT_AW86927=m
+CONFIG_INPUT_CS40L50_VIBRA=m
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_IBM_PANEL=m
+CONFIG_INPUT_KUNIT_TEST=m
+CONFIG_INPUT_LEDS=m
+CONFIG_INPUT_MAX7360_ROTARY=m
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_VIVALDIFMAP=y
+CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y
+CONFIG_INTEGRITY_AUDIT=y
+CONFIG_INTEGRITY_PLATFORM_KEYRING=y
+CONFIG_INTEGRITY_SIGNATURE=y
+CONFIG_INTEGRITY_TRUSTED_KEYRING=y
+CONFIG_INTEGRITY=y
+CONFIG_INTERVAL_TREE_TEST=m
+CONFIG_INT_SQRT_KUNIT_TEST=m
+CONFIG_IO_EVENT_IRQ=y
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+CONFIG_IOMMU_HELPER=y
+CONFIG_IO_STRICT_DEVMEM=y
+CONFIG_IP5XXX_POWER=m
+CONFIG_IPE_BOOT_POLICY=""
+CONFIG_IPE_POLICY_SIG_PLATFORM_KEYRING=y
+CONFIG_IRQ_ALL_CPUS=y
+CONFIG_IRQ_BYPASS_MANAGER=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN_NOMAP=y
+CONFIG_IRQ_EDGE_EOI_HANDLER=y
+CONFIG_IRQ_POLL=y
+CONFIG_ISA_DMA_API=y
+CONFIG_ISCSI_BOOT_SYSFS=m
+CONFIG_IS_SIGNED_TYPE_KUNIT_TEST=m
+CONFIG_IXGBE_HWMON=y
+CONFIG_IXGBE=m
+CONFIG_JUMP_LABEL_FEATURE_CHECKS=y
+CONFIG_KCMP=y
+CONFIG_KERNEL_GZIP=y
+CONFIG_KERNEL_START=0xc000000000000000
+CONFIG_KEXEC_CORE=y
+CONFIG_KEXEC_ELF=y
+CONFIG_KEXEC_FILE=y
+CONFIG_KEXEC_HANDOVER=y
+CONFIG_KEXEC=y
+CONFIG_KPROBE_EVENTS=y
+CONFIG_KPROBES_SANITY_TEST=m
+CONFIG_KRETPROBES=y
+CONFIG_KSM=y
+CONFIG_KUNIT_ALL_TESTS=m
+CONFIG_KUNIT_AUTORUN_ENABLED=y
+CONFIG_KUNIT_DEBUGFS=y
+CONFIG_KUNIT_DEFAULT_ENABLED=y
+CONFIG_KUNIT_DEFAULT_TIMEOUT=300
+CONFIG_KUNIT_EXAMPLE_TEST=m
+CONFIG_KUNIT=m
+CONFIG_KUNIT_TEST=m
+CONFIG_KVM_BOOK3S_64_HANDLER=y
+CONFIG_KVM_BOOK3S_64_HV=m
+CONFIG_KVM_BOOK3S_64=m
+CONFIG_KVM_BOOK3S_HANDLER=y
+CONFIG_KVM_BOOK3S_HV_NESTED_PMU_WORKAROUND=y
+CONFIG_KVM_BOOK3S_HV_POSSIBLE=y
+CONFIG_KVM_COMPAT=y
+CONFIG_KVM_VFIO=y
+CONFIG_KVM_XICS=y
+CONFIG_KVM_XIVE=y
+CONFIG_KVM=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LD_IS_LLD=y
+CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
+CONFIG_LD_ORPHAN_WARN=y
+CONFIG_LD_VERSION=0
+CONFIG_LEDS_CLASS=m
+CONFIG_LEDS_LP8864=m
+CONFIG_LEDS_POWERNV=m
+CONFIG_LEDS_TRIGGER_ACTIVITY=m
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_CAMERA=m
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_GPIO=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_NETDEV=m
+CONFIG_LEDS_TRIGGER_ONESHOT=m
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEDS_TRIGGER_PATTERN=m
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_TRANSIENT=m
+CONFIG_LEDS_TRIGGER_TTY=m
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_TIOCSTI=y
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFDT=y
+CONFIG_LIBNVDIMM=y
+CONFIG_LINEAR_RANGES=m
+CONFIG_LINEAR_RANGES_TEST=m
+CONFIG_LIST_HARDENED=y
+CONFIG_LIST_KUNIT_TEST=m
+CONFIG_LKDTM=m
+CONFIG_LLD_VERSION=160006
+CONFIG_LOAD_PPC_KEYS=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y
+CONFIG_LOCK_MM_AND_FIND_VMA=y
+CONFIG_LOCK_TORTURE_TEST=m
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=13
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO=y
+CONFIG_LPARCFG=y
+CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,selinux,smack,tomoyo,apparmor,bpf"
+CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_LTO_NONE=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACINTOSH_DRIVERS=y
+CONFIG_MAC_PARTITION=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
+CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MATH_EMULATION_HW_UNIMPLEMENTED=y
+CONFIG_MATH_EMULATION=y
+CONFIG_MD_AUTODETECT=y
+CONFIG_MD_BITMAP_FILE=y
+CONFIG_MD_CLUSTER=m
+CONFIG_MD_FAULTY=m
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO=m
+CONFIG_MDIO_MSCC_MIIM=m
+CONFIG_MD_LINEAR=y
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=y
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID1=y
+CONFIG_MD_RAID456=m
+CONFIG_MEMCG_KMEM=y
+CONFIG_MEMCPY_KUNIT_TEST=m
+CONFIG_MEMCPY_SLOW_KUNIT_TEST=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY_HOTPLUG=y
+CONFIG_MEMORY_HOTREMOVE=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MEMREGION=y
+CONFIG_MFD_88PM886_PMIC=y
+CONFIG_MFD_MAX77759=m
+CONFIG_MFD_ROHM_BD96801=m
+CONFIG_MFD_SEC_ACPM=m
+CONFIG_MFD_SEC_I2C=m
+CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO=y
+CONFIG_MHP_MEMMAP_ON_MEMORY=y
+CONFIG_MII=y
+CONFIG_MLX4_CORE_GEN2=y
+CONFIG_MLX4_CORE=m
+CONFIG_MLX4_DEBUG=y
+CONFIG_MLX4_EN=m
+CONFIG_MLX4_INFINIBAND=m
+CONFIG_MLX5_INFINIBAND=m
+CONFIG_MMIO_NVRAM=y
+CONFIG_MMIOWB=y
+CONFIG_MMU_GATHER_MERGE_VMAS=y
+CONFIG_MMU_GATHER_PAGE_SIZE=y
+CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
+CONFIG_MMU_GATHER_TABLE_FREE=y
+CONFIG_MMU_LAZY_TLB_SHOOTDOWN=y
+CONFIG_MODULE_SIG_FORMAT=y
+CONFIG_MODULE_SIG_KEY="certs/signing_key.pem"
+CONFIG_MODULE_SIG_KEY_TYPE_RSA=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOST_CDEV=m
+CONFIG_MOST=m
+CONFIG_MOST_SND=m
+CONFIG_MOST_USB_HDM=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_PIXART=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MPIC_BROKEN_REGREAD=y
+CONFIG_MPIC_U3_HT_IRQS=y
+CONFIG_MPIC=y
+CONFIG_MQ_IOSCHED_KYBER=y
+CONFIG_MSI_BITMAP_SELFTEST=y
+CONFIG_MYRI10GE=m
+CONFIG_ND_BTT=y
+CONFIG_ND_CLAIM=y
+CONFIG_ND_PFN=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETCONSOLE=y
+CONFIG_NETDEV_ADDR_LIST_TEST=m
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_FAILOVER=m
+CONFIG_NETKIT=y
+CONFIG_NET_POLL_CONTROLLER=y
+CONFIG_NETPOLL=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_VENDOR_3COM=y
+CONFIG_NET_VENDOR_8390=y
+CONFIG_NET_VENDOR_ADAPTEC=y
+CONFIG_NET_VENDOR_AGERE=y
+CONFIG_NET_VENDOR_ALACRITECH=y
+CONFIG_NET_VENDOR_ALTEON=y
+CONFIG_NET_VENDOR_AMAZON=y
+CONFIG_NET_VENDOR_AMD=y
+CONFIG_NET_VENDOR_AQUANTIA=y
+CONFIG_NET_VENDOR_ARC=y
+CONFIG_NET_VENDOR_ASIX=y
+CONFIG_NET_VENDOR_ATHEROS=y
+CONFIG_NET_VENDOR_BROADCOM=y
+CONFIG_NET_VENDOR_BROCADE=y
+CONFIG_NET_VENDOR_CADENCE=y
+CONFIG_NET_VENDOR_CAVIUM=y
+CONFIG_NET_VENDOR_CHELSIO=y
+CONFIG_NET_VENDOR_CISCO=y
+CONFIG_NET_VENDOR_CORTINA=y
+CONFIG_NET_VENDOR_DAVICOM=y
+CONFIG_NET_VENDOR_DEC=y
+CONFIG_NET_VENDOR_DLINK=y
+CONFIG_NET_VENDOR_EMULEX=y
+CONFIG_NET_VENDOR_ENGLEDER=y
+CONFIG_NET_VENDOR_EZCHIP=y
+CONFIG_NET_VENDOR_FUJITSU=y
+CONFIG_NET_VENDOR_FUNGIBLE=y
+CONFIG_NET_VENDOR_GOOGLE=y
+CONFIG_NET_VENDOR_HUAWEI=y
+CONFIG_NET_VENDOR_I825XX=y
+CONFIG_NET_VENDOR_IBM=y
+CONFIG_NET_VENDOR_INTEL=y
+CONFIG_NET_VENDOR_LITEX=y
+CONFIG_NET_VENDOR_MARVELL=y
+CONFIG_NET_VENDOR_MELLANOX=y
+CONFIG_NET_VENDOR_MICREL=y
+CONFIG_NET_VENDOR_MICROCHIP=y
+CONFIG_NET_VENDOR_MICROSEMI=y
+CONFIG_NET_VENDOR_MICROSOFT=y
+CONFIG_NET_VENDOR_MYRI=y
+CONFIG_NET_VENDOR_NATSEMI=y
+CONFIG_NET_VENDOR_NETERION=y
+CONFIG_NET_VENDOR_NETRONOME=y
+CONFIG_NET_VENDOR_NI=y
+CONFIG_NET_VENDOR_NVIDIA=y
+CONFIG_NET_VENDOR_OKI=y
+CONFIG_NET_VENDOR_PACKET_ENGINES=y
+CONFIG_NET_VENDOR_PASEMI=y
+CONFIG_NET_VENDOR_PENSANDO=y
+CONFIG_NET_VENDOR_QLOGIC=y
+CONFIG_NET_VENDOR_QUALCOMM=y
+CONFIG_NET_VENDOR_RDC=y
+CONFIG_NET_VENDOR_REALTEK=y
+CONFIG_NET_VENDOR_RENESAS=y
+CONFIG_NET_VENDOR_ROCKER=y
+CONFIG_NET_VENDOR_SAMSUNG=y
+CONFIG_NET_VENDOR_SEEQ=y
+CONFIG_NET_VENDOR_SILAN=y
+CONFIG_NET_VENDOR_SIS=y
+CONFIG_NET_VENDOR_SMSC=y
+CONFIG_NET_VENDOR_SOCIONEXT=y
+CONFIG_NET_VENDOR_SOLARFLARE=y
+CONFIG_NET_VENDOR_STMICRO=y
+CONFIG_NET_VENDOR_SUN=y
+CONFIG_NET_VENDOR_SYNOPSYS=y
+CONFIG_NET_VENDOR_TEHUTI=y
+CONFIG_NET_VENDOR_TI=y
+CONFIG_NET_VENDOR_TOSHIBA=y
+CONFIG_NET_VENDOR_VERTEXCOM=y
+CONFIG_NET_VENDOR_VIA=y
+CONFIG_NET_VENDOR_WANGXUN=y
+CONFIG_NET_VENDOR_WIZNET=y
+CONFIG_NET_VENDOR_XILINX=y
+CONFIG_NET_VENDOR_XIRCOM=y
+CONFIG_NETXEN_NIC=m
+CONFIG_NEW_LEDS=y
+CONFIG_NMI_IPI=y
+CONFIG_NODES_SHIFT=8
+CONFIG_NO_HZ_FULL=y
+CONFIG_NO_HZ=y
+CONFIG_NONSTATIC_KERNEL=y
+CONFIG_NOP_TRACER=y
+CONFIG_NR_CPUS=2048
+CONFIG_NR_IRQS=512
+CONFIG_NSM=m
+CONFIG_NTSYNC=m
+CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
+CONFIG_NUMA_BALANCING=y
+CONFIG_NUMA_KEEP_MEMINFO=y
+CONFIG_NUMA=y
+CONFIG_NVDIMM_DAX=y
+CONFIG_NVDIMM_PFN=y
+CONFIG_NVRAM=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_PMEM=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OF=y
+CONFIG_OLD_SIGSUSPEND=y
+CONFIG_OPTPROBES=y
+CONFIG_OVERFLOW_KUNIT_TEST=m
+CONFIG_PAGE_BLOCK_MAX_ORDER=8
+CONFIG_PAGE_BLOCK_ORDER=8
+CONFIG_PAGE_EXTENSION=y
+CONFIG_PAGE_OFFSET=0xc000000000000000
+CONFIG_PAGE_OWNER=y
+CONFIG_PAGE_POISONING=y
+CONFIG_PAGE_SIZE_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAHOLE_VERSION=125
+CONFIG_PANIC_TIMEOUT=180
+CONFIG_PAPR_SCM=m
+CONFIG_PARAVIRT_SPINLOCKS=y
+CONFIG_PARAVIRT_TIME_ACCOUNTING=y
+CONFIG_PARAVIRT=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PASEMI_MAC=y
+CONFIG_PATA_AMD=y
+CONFIG_PATA_MACIO=y
+CONFIG_PATA_TIMINGS=y
+CONFIG_PCCARD=y
+CONFIG_PCI_DOE=y
+CONFIG_PCIEASPM_DEFAULT=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIE_XILINX_DMA_PL=y
+CONFIG_PCI_MSI_ARCH_FALLBACKS=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA=y
+CONFIG_PCNET32=m
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_PCS_XPCS=m
+CONFIG_PERCPU_TEST=m
+CONFIG_PER_VMA_LOCK=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHY_LAN966X_SERDES=m
+CONFIG_PHYLIB=y
+CONFIG_PHY_MAPPHONE_MDM6600=m
+CONFIG_PHY_OCELOT_SERDES=m
+CONFIG_PHYSICAL_START=0x00000000
+CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
+CONFIG_PMAC_SMU=y
+CONFIG_PM_SLEEP_SMP_NONZERO_CPU=y
+CONFIG_POWERNV_CPUFREQ=y
+CONFIG_POWERNV_CPUIDLE=y
+CONFIG_POWERNV_OP_PANEL=m
+CONFIG_POWERPC64_CPU=y
+CONFIG_PPC64_ELF_ABI_V1=y
+CONFIG_PPC_64K_PAGES=y
+CONFIG_PPC_64S_HASH_MMU=y
+CONFIG_PPC64_SUPPORTS_MEMORY_FAILURE=y
+CONFIG_PPC64=y
+CONFIG_PPC_970_NAP=y
+CONFIG_PPC_BARRIER_NOSPEC=y
+CONFIG_PPC_BOOK3S_64=y
+CONFIG_PPC_BOOK3S_IDLE=y
+CONFIG_PPC_BOOK3S=y
+CONFIG_PPC_CELL_COMMON=y
+CONFIG_PPC_CELL_NATIVE=y
+CONFIG_PPC_CELL=y
+CONFIG_PPC_COPRO_BASE=y
+CONFIG_PPC_DAWR=y
+CONFIG_PPC_DCR_MMIO=y
+CONFIG_PPC_DCR=y
+CONFIG_PPC_DENORMALISATION=y
+CONFIG_PPC_DOORBELL=y
+CONFIG_PPC_DT_CPU_FTRS=y
+CONFIG_PPC_EMULATED_STATS=y
+CONFIG_PPC_FPU_REGS=y
+CONFIG_PPC_FPU=y
+CONFIG_PPC_HASH_MMU_NATIVE=y
+CONFIG_PPC_HAVE_PMU_SUPPORT=y
+CONFIG_PPC_I8259=y
+CONFIG_PPC_IBM_CELL_BLADE=y
+CONFIG_PPC_IBM_CELL_POWERBUTTON=m
+CONFIG_PPC_IBM_CELL_RESETBUTTON=y
+CONFIG_PPC_ICP_HV=y
+CONFIG_PPC_ICP_NATIVE=y
+CONFIG_PPC_ICS_RTAS=y
+CONFIG_PPC_INDIRECT_MMIO=y
+CONFIG_PPC_INDIRECT_PIO=y
+CONFIG_PPC_IO_WORKAROUNDS=y
+CONFIG_PPC_KUAP=y
+CONFIG_PPC_KUEP=y
+CONFIG_PPC_MAPLE=y
+CONFIG_PPC_MEM_KEYS=y
+CONFIG_PPC_MICROWATT=y
+CONFIG_PPC_MSI_BITMAP=y
+CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
+CONFIG_PPC_OF_PLATFORM_PCI=y
+CONFIG_PPC_P7_NAP=y
+CONFIG_PPC_PAGE_SHIFT=16
+CONFIG_PPC_PASEMI_CPUFREQ=y
+CONFIG_PPC_PASEMI_IOMMU=y
+CONFIG_PPC_PASEMI_MDIO=y
+CONFIG_PPC_PASEMI=y
+CONFIG_PPC_PERF_CTRS=y
+CONFIG_PPC_PKEY=y
+CONFIG_PPC_PMAC64=y
+CONFIG_PPC_PMAC=y
+CONFIG_PPC_PMI=m
+CONFIG_PPC_POWERNV=y
+CONFIG_PPC_PS3=y
+CONFIG_PPC_PSERIES=y
+CONFIG_PPC_QUEUED_SPINLOCKS=y
+CONFIG_PPC_RADIX_MMU_DEFAULT=y
+CONFIG_PPC_RADIX_MMU=y
+CONFIG_PPC_RTAS_DAEMON=y
+CONFIG_PPC_RTAS=y
+CONFIG_PPC_SECURE_BOOT=y
+CONFIG_PPC_SECVAR_SYSFS=y
+CONFIG_PPC_SMLPAR=y
+CONFIG_PPC_SMP_MUXED_IPI=y
+CONFIG_PPC_SPLPAR=y
+CONFIG_PPC_SVM=y
+CONFIG_PPC_TRANSACTIONAL_MEM=y
+CONFIG_PPC_UDBG_16550=y
+CONFIG_PPC_VAS=y
+CONFIG_PPC_WATCHDOG=y
+CONFIG_PPC_WERROR=y
+CONFIG_PPC_XICS=y
+CONFIG_PPC_XIVE_NATIVE=y
+CONFIG_PPC_XIVE_SPAPR=y
+CONFIG_PPC_XIVE=y
+CONFIG_PPC=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP=m
+CONFIG_PPPOATM=m
+CONFIG_PPPOE_HASH_BITS=4
+CONFIG_PPPOE_HASH_BITS_4=y
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPS=y
+CONFIG_PPTP=m
+CONFIG_PREEMPT_DYNAMIC=y
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_PREEMPT_VOLUNTARY_BUILD=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_PRINTK_CALLER=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PRINT_STACK_DEPTH=64
+CONFIG_PROBE_EVENTS=y
+CONFIG_PS3_DISK=m
+CONFIG_PS3_FLASH=m
+CONFIG_PS3_HTAB_SIZE=20
+CONFIG_PS3_LPM=m
+CONFIG_PS3_PS3AV=y
+CONFIG_PS3_ROM=m
+CONFIG_PS3_STORAGE=m
+CONFIG_PS3_SYS_MANAGER=y
+CONFIG_PS3_VUART=y
+CONFIG_PSERIES_CPUIDLE=y
+CONFIG_PSERIES_ENERGY=y
+CONFIG_PSERIES_PLPKS=y
+CONFIG_PSI=y
+CONFIG_PTDUMP_CORE=y
+CONFIG_PTP_1588_CLOCK_FC3W=m
+CONFIG_PTP_1588_CLOCK_INES=m
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PTP_1588_CLOCK_QORIQ=m
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_NETC_V4_TIMER=m
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_R8169_LEDS=y
+CONFIG_RAID6_PQ_BENCHMARK=y
+CONFIG_RAID6_PQ=m
+CONFIG_RAID_ATTRS=m
+CONFIG_RANDSTRUCT_KUNIT_TEST=m
+CONFIG_RAS=y
+CONFIG_RBTREE_TEST=m
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_TRACE=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_REED_SOLOMON_DEC16=y
+CONFIG_REED_SOLOMON_ENC16=y
+CONFIG_REED_SOLOMON=m
+CONFIG_REED_SOLOMON_TEST=m
+CONFIG_REF_TRACKER=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_KUNIT=m
+CONFIG_REGMAP_RAM=m
+CONFIG_RELAY=y
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_TI_SYSCON=m
+CONFIG_RESET_TI_TPS380X=m
+CONFIG_RESOURCE_KUNIT_TEST=m
+CONFIG_RING_BUFFER=y
+CONFIG_ROHM_BD79112=m
+CONFIG_RTAS_ERROR_LOGGING=y
+CONFIG_RTAS_FLASH=m
+CONFIG_RTAS_PROC=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_NCT6694=m
+CONFIG_RTC_DRV_OPAL=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_LIB_KUNIT_TEST=m
+CONFIG_RUNTIME_TESTING_MENU=y
+CONFIG_RXPERF=m
+CONFIG_S2IO=m
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_MV=y
+CONFIG_SATA_SIL24=y
+CONFIG_SATA_SVW=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHED_MM_CID=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_SCHED_SMT=y
+CONFIG_SCHEDSTATS=y
+CONFIG_SCHED_TRACER=y
+CONFIG_SCSI_BNX2_ISCSI=m
+CONFIG_SCSI_COMMON=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_CXGB3_ISCSI=m
+CONFIG_SCSI_CXGB4_ISCSI=m
+CONFIG_SCSI_DH_ALUA=m
+CONFIG_SCSI_DH_RDAC=m
+CONFIG_SCSI_DH=y
+CONFIG_SCSI_FC_ATTRS=y
+CONFIG_SCSI_IBMVFC=m
+CONFIG_SCSI_IBMVFC_TRACE=y
+CONFIG_SCSI_IBMVSCSI=y
+CONFIG_SCSI_IPR_DUMP=y
+CONFIG_SCSI_IPR_TRACE=y
+CONFIG_SCSI_IPR=y
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_LPFC=m
+CONFIG_SCSI_MOD=y
+CONFIG_SCSI_MPT2SAS=m
+CONFIG_SCSI_MPT2SAS_MAX_SGE=128
+CONFIG_SCSI_MPT3SAS=m
+CONFIG_SCSI_MPT3SAS_MAX_SGE=128
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+CONFIG_SCSI_QLA_FC=m
+CONFIG_SCSI_QLA_ISCSI=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_SRP_ATTRS=y
+CONFIG_SCSI_SYM53C8XX_2=m
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+CONFIG_SCSI_SYM53C8XX_MMIO=y
+CONFIG_SCSI_VIRTIO=m
+CONFIG_SCSI=y
+CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN=y
+CONFIG_SECURITY_IPE=y
+CONFIG_SECURITY_LANDLOCK=y
+CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y
+CONFIG_SECURITY_LOCKDOWN_LSM=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_SECURITY_PATH=y
+CONFIG_SECURITY_SELINUX_AVC_STATS=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_SELINUX_DEVELOP=y
+CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
+CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_YAMA=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_SENSORS_IBMPOWERNV=m
+CONFIG_SERIAL_8250_16550A_VARIANTS=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PERICOM=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_ICOM=m
+CONFIG_SERIAL_JSM=m
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_OLPC_APSP=m
+CONFIG_SERIO=y
+CONFIG_SGETMASK_SYSCALL=y
+CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
+CONFIG_SIGNATURE=y
+CONFIG_SIPHASH_KUNIT_TEST=m
+CONFIG_SLAB_FREELIST_HARDENED=y
+CONFIG_SLAB_FREELIST_RANDOM=y
+CONFIG_SLHC=m
+CONFIG_SLUB_DEBUG=y
+CONFIG_SLUB_KUNIT_TEST=m
+CONFIG_SMT_NUM_THREADS_DYNAMIC=y
+CONFIG_SND_AOA_FABRIC_LAYOUT=m
+CONFIG_SND_AOA=m
+CONFIG_SND_AOA_ONYX=m
+CONFIG_SND_AOA_SOUNDBUS_I2S=m
+CONFIG_SND_AOA_SOUNDBUS=m
+CONFIG_SND_AOA_TAS=m
+CONFIG_SND_AOA_TOONIE=m
+CONFIG_SND_CTL_FAST_LOOKUP=y
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_HDA_PREALLOC_SIZE=64
+CONFIG_SND=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_PCI=y
+CONFIG_SND_PCMCIA=y
+CONFIG_SND_PCM=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_POWERMAC_AUTO_DRC=y
+CONFIG_SND_POWERMAC=m
+CONFIG_SND_PPC=y
+CONFIG_SND_PROC_FS=y
+CONFIG_SND_PS3_DEFAULT_START_DELAY=2000
+CONFIG_SND_PS3=m
+CONFIG_SND_SEQ_DEVICE=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQ_MIDI_EVENT=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQUENCER_OSS=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_USB=y
+CONFIG_SND_UTIMER=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VMASTER=y
+CONFIG_SOCK_CGROUP_DATA=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SPAPR_TCE_IOMMU=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPIDER_NET=m
+CONFIG_SPU_BASE=y
+CONFIG_SPU_FS=m
+CONFIG_STACKDEPOT_MAX_FRAMES=64
+CONFIG_STACKDEPOT=y
+CONFIG_STACKINIT_KUNIT_TEST=m
+CONFIG_STACK_TRACER=y
+CONFIG_STACKTRACE=y
+CONFIG_STANDALONE=y
+CONFIG_STRCAT_KUNIT_TEST=m
+CONFIG_STRICT_DEVMEM=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+CONFIG_STRING_SELFTEST=m
+CONFIG_STRSCPY_KUNIT_TEST=m
+CONFIG_SUNGEM_PHY=y
+CONFIG_SUNGEM=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSCTL_KUNIT_TEST=m
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
+CONFIG_SYSTEM_BLACKLIST_KEYRING=y
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_TARGET_CPU_BOOL=y
+CONFIG_TARGET_CPU="power4"
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASKS_RUDE_RCU=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_XACCT=y
+CONFIG_TCG_IBMVTPM=y
+CONFIG_TCG_TPM=y
+CONFIG_TEST_BITMAP=m
+CONFIG_TEST_BITOPS=m
+CONFIG_TEST_BLACKHOLE_DEV=m
+CONFIG_TEST_BPF=m
+CONFIG_TEST_DIV64=m
+CONFIG_TEST_FIRMWARE=m
+CONFIG_TEST_FREE_PAGES=m
+CONFIG_TEST_HEXDUMP=m
+CONFIG_TEST_IDA=m
+CONFIG_TEST_IOV_ITER=m
+CONFIG_TEST_KMOD=m
+CONFIG_TEST_KSTRTOX=m
+CONFIG_TEST_LIST_SORT=m
+CONFIG_TEST_LKM=m
+CONFIG_TEST_MAPLE_TREE=m
+CONFIG_TEST_MEMCAT_P=m
+CONFIG_TEST_MEMINIT=m
+CONFIG_TEST_MIN_HEAP=m
+CONFIG_TEST_MISC_MINOR=m
+CONFIG_TEST_POWER=m
+CONFIG_TEST_PRINTF=m
+CONFIG_TEST_REF_TRACKER=m
+CONFIG_TEST_RHASHTABLE=m
+CONFIG_TEST_SCANF=m
+CONFIG_TEST_SORT=m
+CONFIG_TEST_STATIC_KEYS=m
+CONFIG_TEST_STRING_HELPERS=m
+CONFIG_TEST_SYSCTL=m
+CONFIG_TEST_UDELAY=m
+CONFIG_TEST_USER_COPY=m
+CONFIG_TEST_UUID=m
+CONFIG_TEST_VMALLOC=m
+CONFIG_TEST_XARRAY=m
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_THREAD_SHIFT=14
+CONFIG_TIGON3_HWMON=y
+CONFIG_TIGON3=y
+CONFIG_TIME_KUNIT_TEST=m
+CONFIG_TI_ST=m
+CONFIG_TOOLS_SUPPORT_RELR=y
+CONFIG_TORTURE_TEST=m
+CONFIG_TRACE_CLOCK=y
+CONFIG_TRACEPOINTS=y
+CONFIG_TRACER_MAX_TRACE=y
+CONFIG_TRACER_SNAPSHOT=y
+CONFIG_TRACING=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TUN=m
+CONFIG_U3_DART=y
+CONFIG_UDBG_RTAS_CONSOLE=y
+CONFIG_UPROBE_EVENTS=y
+CONFIG_UPROBES=y
+CONFIG_USB_APPLEDISPLAY=m
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_LEDS_TRIGGER_USBPORT=m
+CONFIG_USB_LED_TRIG=y
+CONFIG_USB_LJCA=m
+CONFIG_USB_MON=m
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_PCI_AMD=y
+CONFIG_USB_STORAGE=m
+CONFIG_USB=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+CONFIG_USERCOPY_KUNIT_TEST=m
+CONFIG_VDSO32=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VHOST_IOTLB=m
+CONFIG_VHOST=m
+CONFIG_VHOST_TASK=y
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEO_NOMODESET=y
+CONFIG_VIRT_CPU_ACCOUNTING=y
+CONFIG_VIRTIO_ANCHOR=y
+CONFIG_VIRTIO_BALLOON=m
+CONFIG_VIRTIO_BLK=m
+CONFIG_VIRTIO_CONSOLE=m
+CONFIG_VIRTIO=m
+CONFIG_VIRTIO_NET=m
+CONFIG_VIRTIO_PCI_LIB_LEGACY=m
+CONFIG_VIRTIO_PCI_LIB=m
+CONFIG_VIRTIO_PCI=m
+CONFIG_VIRTUALIZATION=y
+CONFIG_VORTEX=m
+CONFIG_VSX=y
+CONFIG_W1_CON=y
+CONFIG_W1_MASTER_AMD_AXI=m
+CONFIG_W1_MASTER_DS2482=m
+CONFIG_W1_MASTER_DS2490=m
+CONFIG_W1_MASTER_GPIO=m
+CONFIG_W1_MASTER_MATROX=m
+CONFIG_W1_MASTER_SGI=m
+CONFIG_W1_SLAVE_DS2405=m
+CONFIG_W1_SLAVE_DS2406=m
+CONFIG_W1_SLAVE_DS2408=m
+CONFIG_W1_SLAVE_DS2408_READBACK=y
+CONFIG_W1_SLAVE_DS2413=m
+CONFIG_W1_SLAVE_DS2423=m
+CONFIG_W1_SLAVE_DS2430=m
+CONFIG_W1_SLAVE_DS2431=m
+CONFIG_W1_SLAVE_DS2433_CRC=y
+CONFIG_W1_SLAVE_DS2433=m
+CONFIG_W1_SLAVE_DS2438=m
+CONFIG_W1_SLAVE_DS250X=m
+CONFIG_W1_SLAVE_DS2805=m
+CONFIG_W1_SLAVE_DS28E04=m
+CONFIG_W1_SLAVE_DS28E17=m
+CONFIG_W1_SLAVE_SMEM=m
+CONFIG_W1_SLAVE_THERM=m
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WINDFARM_PM112=y
+CONFIG_WINDFARM_PM121=y
+CONFIG_WINDFARM_PM81=y
+CONFIG_WINDFARM_PM91=y
+CONFIG_WINDFARM=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WLAN_VENDOR_CISCO=y
+CONFIG_XARRAY_MULTI=y
+CONFIG_XMON_DEFAULT_RO_MODE=y
+CONFIG_XMON_DISASSEMBLY=y
+CONFIG_XMON=y
+CONFIG_XOR_BLOCKS=m
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZONE_DEVICE=y
+CONFIG_ZPOOL=y
+CONFIG_ZRAM_DEF_COMP="zstd"
+CONFIG_ZRAM_TRACK_ENTRY_ACTIME=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=m
+CONFIG_NEXUS=m
diff --git a/pps.fragment b/pps.fragment
new file mode 100644
index 0000000..8a44503
--- /dev/null
+++ b/pps.fragment
@@ -0,0 +1,3 @@
+CONFIG_PPS_GENERATOR=m
+CONFIG_PPS_GENERATOR_DUMMY=m
+CONFIG_PPS_GENERATOR_TIO=m
diff --git a/ras-fix-build-without-debugfs.patch b/ras-fix-build-without-debugfs.patch
new file mode 100644
index 0000000..e62cd0d
--- /dev/null
+++ b/ras-fix-build-without-debugfs.patch
@@ -0,0 +1,19 @@
+diff -up linux-6.9-rc1/drivers/ras/amd/fmpm.c.omv~ linux-6.9-rc1/drivers/ras/amd/fmpm.c
+--- linux-6.9-rc1/drivers/ras/amd/fmpm.c.omv~	2024-03-25 17:12:09.673207097 +0100
++++ linux-6.9-rc1/drivers/ras/amd/fmpm.c	2024-03-25 17:12:39.892935870 +0100
+@@ -929,6 +929,7 @@ static const struct file_operations fmpm
+ 
+ static void setup_debugfs(void)
+ {
++#ifdef CONFIG_DEBUG_FS
+ 	struct dentry *dfs = ras_get_debugfs_root();
+ 
+ 	if (!dfs)
+@@ -941,6 +942,7 @@ static void setup_debugfs(void)
+ 	fmpm_dfs_entries = debugfs_create_file("entries", 0400, fmpm_dfs_dir, NULL, &fmpm_fops);
+ 	if (!fmpm_dfs_entries)
+ 		debugfs_remove(fmpm_dfs_dir);
++#endif
+ }
+ 
+ static const struct x86_cpu_id fmpm_cpuids[] = {
diff --git a/restore-exporting-symbols-needed-by-binder.patch b/restore-exporting-symbols-needed-by-binder.patch
new file mode 100644
index 0000000..39a3459
--- /dev/null
+++ b/restore-exporting-symbols-needed-by-binder.patch
@@ -0,0 +1,43 @@
+diff -up linux-6.14-rc2/mm/list_lru.c.omv~ linux-6.14-rc2/mm/list_lru.c
+--- linux-6.14-rc2/mm/list_lru.c.omv~	2025-02-16 13:08:32.776957448 +0000
++++ linux-6.14-rc2/mm/list_lru.c	2025-02-16 16:39:49.877465547 +0000
+@@ -175,6 +175,7 @@ bool list_lru_add(struct list_lru *lru,
+ 	unlock_list_lru(l, false);
+ 	return false;
+ }
++EXPORT_SYMBOL_GPL(list_lru_add); // still used by binder
+ 
+ bool list_lru_add_obj(struct list_lru *lru, struct list_head *item)
+ {
+@@ -212,6 +213,7 @@ bool list_lru_del(struct list_lru *lru,
+ 	unlock_list_lru(l, false);
+ 	return false;
+ }
++EXPORT_SYMBOL_GPL(list_lru_del); // Still used by binder
+ 
+ bool list_lru_del_obj(struct list_lru *lru, struct list_head *item)
+ {
+diff -up linux-6.18-rc3/drivers/android/binder.c.omv~ linux-6.18-rc3/drivers/android/binder.c
+--- linux-6.18-rc3/drivers/android/binder.c.omv~	2025-10-31 20:19:02.850251504 +0000
++++ linux-6.18-rc3/drivers/android/binder.c	2025-10-31 20:19:38.870370757 +0000
+@@ -6988,6 +6988,9 @@ DEFINE_SHOW_ATTRIBUTE(transactions);
+ DEFINE_SHOW_ATTRIBUTE(transactions_hashed);
+ DEFINE_SHOW_ATTRIBUTE(transaction_log);
+ 
++MODULE_DESCRIPTION("The binder IPC system");
++MODULE_LICENSE("GPL v2");
++
+ const struct binder_debugfs_entry binder_debugfs_entries[] = {
+ 	{
+ 		.name = "state",
+diff -up linux-6.18-rc3/mm/mmap_lock.c.omv~ linux-6.18-rc3/mm/mmap_lock.c
+--- linux-6.18-rc3/mm/mmap_lock.c.omv~	2025-10-31 21:10:47.923556571 +0000
++++ linux-6.18-rc3/mm/mmap_lock.c	2025-10-31 21:11:03.143628302 +0000
+@@ -267,6 +267,7 @@ inval:
+ 	count_vm_vma_lock_event(VMA_LOCK_ABORT);
+ 	return NULL;
+ }
++EXPORT_SYMBOL_GPL(lock_vma_under_rcu);
+ 
+ static struct vm_area_struct *lock_next_vma_under_mmap_lock(struct mm_struct *mm,
+ 							    struct vma_iterator *vmi,
diff --git a/revert-721412ed3d819e767cac2b06646bf03aa158aaec.patch b/revert-721412ed3d819e767cac2b06646bf03aa158aaec.patch
index 8ed9695..985d6ff 100644
--- a/revert-721412ed3d819e767cac2b06646bf03aa158aaec.patch
+++ b/revert-721412ed3d819e767cac2b06646bf03aa158aaec.patch
@@ -1,6 +1,72 @@
-diff -up linux-6.1-rc1/drivers/staging/android/ashmem.c.25~ linux-6.1-rc1/drivers/staging/android/ashmem.c
---- linux-6.1-rc1/drivers/staging/android/ashmem.c.25~	2022-10-17 16:30:02.355772882 +0200
-+++ linux-6.1-rc1/drivers/staging/android/ashmem.c	2022-10-17 16:30:02.355772882 +0200
+diff -up linux-6.13-rc1/drivers/staging/Kconfig.26~ linux-6.13-rc1/drivers/staging/Kconfig
+--- linux-6.13-rc1/drivers/staging/Kconfig.26~	2024-12-02 00:54:24.483099059 +0100
++++ linux-6.13-rc1/drivers/staging/Kconfig	2024-12-02 00:55:35.453942997 +0100
+@@ -36,6 +36,8 @@ source "drivers/staging/nvec/Kconfig"
+ 
+ source "drivers/staging/media/Kconfig"
+ 
++source "drivers/staging/android/Kconfig"
++
+ source "drivers/staging/fbtft/Kconfig"
+ 
+ source "drivers/staging/most/Kconfig"
+diff -up linux-6.13-rc1/drivers/staging/Makefile.26~ linux-6.13-rc1/drivers/staging/Makefile
+--- linux-6.13-rc1/drivers/staging/Makefile.26~	2024-12-02 00:54:24.483099059 +0100
++++ linux-6.13-rc1/drivers/staging/Makefile	2024-12-02 00:55:56.404192044 +0100
+@@ -7,6 +7,7 @@ obj-$(CONFIG_OCTEON_ETHERNET)	+= octeon/
+ obj-$(CONFIG_VME_BUS)		+= vme_user/
+ obj-$(CONFIG_IIO)		+= iio/
+ obj-$(CONFIG_FB_SM750)		+= sm750fb/
++obj-$(CONFIG_ANDROID)		+= android/
+ obj-$(CONFIG_MFD_NVEC)		+= nvec/
+ obj-$(CONFIG_FB_TFT)		+= fbtft/
+ obj-$(CONFIG_MOST)		+= most/
+diff -up linux-6.13-rc1/drivers/staging/android/Kconfig.26~ linux-6.13-rc1/drivers/staging/android/Kconfig
+--- linux-6.13-rc1/drivers/staging/android/Kconfig.26~	2024-12-02 00:54:24.483099059 +0100
++++ linux-6.13-rc1/drivers/staging/android/Kconfig	2024-12-02 00:54:24.483099059 +0100
+@@ -0,0 +1,19 @@
++# SPDX-License-Identifier: GPL-2.0
++menu "Android"
++
++if ANDROID
++
++config ASHMEM
++	bool "Enable the Anonymous Shared Memory Subsystem"
++	depends on SHMEM
++	help
++	  The ashmem subsystem is a new shared memory allocator, similar to
++	  POSIX SHM but with different behavior and sporting a simpler
++	  file-based API.
++
++	  It is, in theory, a good memory allocator for low-memory devices,
++	  because it can discard shared memory units when under memory pressure.
++
++endif # if ANDROID
++
++endmenu
+diff -up linux-6.13-rc1/drivers/staging/android/Makefile.26~ linux-6.13-rc1/drivers/staging/android/Makefile
+--- linux-6.13-rc1/drivers/staging/android/Makefile.26~	2024-12-02 00:54:24.483099059 +0100
++++ linux-6.13-rc1/drivers/staging/android/Makefile	2024-12-02 00:54:24.483099059 +0100
+@@ -0,0 +1,4 @@
++# SPDX-License-Identifier: GPL-2.0
++ccflags-y += -I$(src)			# needed for trace events
++
++obj-$(CONFIG_ASHMEM)			+= ashmem.o
+diff -up linux-6.13-rc1/drivers/staging/android/TODO.26~ linux-6.13-rc1/drivers/staging/android/TODO
+--- linux-6.13-rc1/drivers/staging/android/TODO.26~	2024-12-02 00:54:24.483099059 +0100
++++ linux-6.13-rc1/drivers/staging/android/TODO	2024-12-02 00:54:24.483099059 +0100
+@@ -0,0 +1,8 @@
++TODO:
++	- sparse fixes
++	- rename files to be not so "generic"
++	- add proper arch dependencies as needed
++	- audit userspace interfaces to make sure they are sane
++
++Please send patches to Greg Kroah-Hartman <greg@kroah.com> and Cc:
++Arve Hjønnevåg <arve@android.com> and Riley Andrews <riandrews@android.com>
+diff -up linux-6.13-rc1/drivers/staging/android/ashmem.c.26~ linux-6.13-rc1/drivers/staging/android/ashmem.c
+--- linux-6.13-rc1/drivers/staging/android/ashmem.c.26~	2024-12-02 00:54:24.483099059 +0100
++++ linux-6.13-rc1/drivers/staging/android/ashmem.c	2024-12-02 00:54:24.483099059 +0100
 @@ -0,0 +1,970 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/* mm/ashmem.c
@@ -972,9 +1038,9 @@ diff -up linux-6.1-rc1/drivers/staging/android/ashmem.c.25~ linux-6.1-rc1/driver
 +	return ret;
 +}
 +device_initcall(ashmem_init);
-diff -up linux-6.1-rc1/drivers/staging/android/ashmem.h.25~ linux-6.1-rc1/drivers/staging/android/ashmem.h
---- linux-6.1-rc1/drivers/staging/android/ashmem.h.25~	2022-10-17 16:30:02.356772887 +0200
-+++ linux-6.1-rc1/drivers/staging/android/ashmem.h	2022-10-17 16:30:02.356772887 +0200
+diff -up linux-6.13-rc1/drivers/staging/android/ashmem.h.26~ linux-6.13-rc1/drivers/staging/android/ashmem.h
+--- linux-6.13-rc1/drivers/staging/android/ashmem.h.26~	2024-12-02 00:54:24.483099059 +0100
++++ linux-6.13-rc1/drivers/staging/android/ashmem.h	2024-12-02 00:54:24.483099059 +0100
 @@ -0,0 +1,24 @@
 +/* SPDX-License-Identifier: GPL-2.0 OR Apache-2.0 */
 +/*
@@ -1000,52 +1066,9 @@ diff -up linux-6.1-rc1/drivers/staging/android/ashmem.h.25~ linux-6.1-rc1/driver
 +#endif
 +
 +#endif	/* _LINUX_ASHMEM_H */
-diff -up linux-6.1-rc1/drivers/staging/android/Kconfig.25~ linux-6.1-rc1/drivers/staging/android/Kconfig
---- linux-6.1-rc1/drivers/staging/android/Kconfig.25~	2022-10-17 16:30:02.355772882 +0200
-+++ linux-6.1-rc1/drivers/staging/android/Kconfig	2022-10-17 16:30:02.355772882 +0200
-@@ -0,0 +1,19 @@
-+# SPDX-License-Identifier: GPL-2.0
-+menu "Android"
-+
-+if ANDROID
-+
-+config ASHMEM
-+	bool "Enable the Anonymous Shared Memory Subsystem"
-+	depends on SHMEM
-+	help
-+	  The ashmem subsystem is a new shared memory allocator, similar to
-+	  POSIX SHM but with different behavior and sporting a simpler
-+	  file-based API.
-+
-+	  It is, in theory, a good memory allocator for low-memory devices,
-+	  because it can discard shared memory units when under memory pressure.
-+
-+endif # if ANDROID
-+
-+endmenu
-diff -up linux-6.1-rc1/drivers/staging/android/Makefile.25~ linux-6.1-rc1/drivers/staging/android/Makefile
---- linux-6.1-rc1/drivers/staging/android/Makefile.25~	2022-10-17 16:30:02.355772882 +0200
-+++ linux-6.1-rc1/drivers/staging/android/Makefile	2022-10-17 16:30:02.355772882 +0200
-@@ -0,0 +1,4 @@
-+# SPDX-License-Identifier: GPL-2.0
-+ccflags-y += -I$(src)			# needed for trace events
-+
-+obj-$(CONFIG_ASHMEM)			+= ashmem.o
-diff -up linux-6.1-rc1/drivers/staging/android/TODO.25~ linux-6.1-rc1/drivers/staging/android/TODO
---- linux-6.1-rc1/drivers/staging/android/TODO.25~	2022-10-17 16:30:02.355772882 +0200
-+++ linux-6.1-rc1/drivers/staging/android/TODO	2022-10-17 16:30:02.355772882 +0200
-@@ -0,0 +1,8 @@
-+TODO:
-+	- sparse fixes
-+	- rename files to be not so "generic"
-+	- add proper arch dependencies as needed
-+	- audit userspace interfaces to make sure they are sane
-+
-+Please send patches to Greg Kroah-Hartman <greg@kroah.com> and Cc:
-+Arve Hjønnevåg <arve@android.com> and Riley Andrews <riandrews@android.com>
-diff -up linux-6.1-rc1/drivers/staging/android/uapi/ashmem.h.25~ linux-6.1-rc1/drivers/staging/android/uapi/ashmem.h
---- linux-6.1-rc1/drivers/staging/android/uapi/ashmem.h.25~	2022-10-17 16:30:02.356772887 +0200
-+++ linux-6.1-rc1/drivers/staging/android/uapi/ashmem.h	2022-10-17 16:30:02.356772887 +0200
+diff -up linux-6.13-rc1/drivers/staging/android/uapi/ashmem.h.26~ linux-6.13-rc1/drivers/staging/android/uapi/ashmem.h
+--- linux-6.13-rc1/drivers/staging/android/uapi/ashmem.h.26~	2024-12-02 00:54:24.483099059 +0100
++++ linux-6.13-rc1/drivers/staging/android/uapi/ashmem.h	2024-12-02 00:54:24.483099059 +0100
 @@ -0,0 +1,43 @@
 +/* SPDX-License-Identifier: GPL-2.0 OR Apache-2.0 */
 +/*
@@ -1090,26 +1113,3 @@ diff -up linux-6.1-rc1/drivers/staging/android/uapi/ashmem.h.25~ linux-6.1-rc1/d
 +#define ASHMEM_PURGE_ALL_CACHES	_IO(__ASHMEMIOC, 10)
 +
 +#endif	/* _UAPI_LINUX_ASHMEM_H */
-diff -up linux-6.1-rc1/drivers/staging/Kconfig.25~ linux-6.1-rc1/drivers/staging/Kconfig
---- linux-6.1-rc1/drivers/staging/Kconfig.25~	2022-10-17 00:36:24.000000000 +0200
-+++ linux-6.1-rc1/drivers/staging/Kconfig	2022-10-17 16:30:02.349772850 +0200
-@@ -56,6 +56,8 @@ source "drivers/staging/nvec/Kconfig"
- 
- source "drivers/staging/media/Kconfig"
- 
-+source "drivers/staging/android/Kconfig"
-+
- source "drivers/staging/board/Kconfig"
- 
- source "drivers/staging/gdm724x/Kconfig"
-diff -up linux-6.1-rc1/drivers/staging/Makefile.25~ linux-6.1-rc1/drivers/staging/Makefile
---- linux-6.1-rc1/drivers/staging/Makefile.25~	2022-10-17 16:30:02.355772882 +0200
-+++ linux-6.1-rc1/drivers/staging/Makefile	2022-10-17 16:31:16.491173401 +0200
-@@ -18,6 +18,7 @@ obj-$(CONFIG_IIO)		+= iio/
- obj-$(CONFIG_FB_SM750)		+= sm750fb/
- obj-$(CONFIG_USB_EMXX)		+= emxx_udc/
- obj-$(CONFIG_MFD_NVEC)		+= nvec/
-+obj-$(CONFIG_ANDROID)		+= android/
- obj-$(CONFIG_STAGING_BOARD)	+= board/
- obj-$(CONFIG_LTE_GDM724X)	+= gdm724x/
- obj-$(CONFIG_FB_TFT)		+= fbtft/
diff --git a/revert-parts-of-a00ec3874e7d326ab2dffbed92faddf6a77a84e9-no-Intel-NO.patch b/revert-parts-of-a00ec3874e7d326ab2dffbed92faddf6a77a84e9-no-Intel-NO.patch
index dec5766..644036e 100644
--- a/revert-parts-of-a00ec3874e7d326ab2dffbed92faddf6a77a84e9-no-Intel-NO.patch
+++ b/revert-parts-of-a00ec3874e7d326ab2dffbed92faddf6a77a84e9-no-Intel-NO.patch
@@ -1,12 +1,11 @@
-diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
-index 85de313ddec2..1b2a7160981c 100644
---- a/drivers/cpufreq/Kconfig
-+++ b/drivers/cpufreq/Kconfig
+diff -up linux-6.5-rc1/drivers/cpufreq/Kconfig.30~ linux-6.5-rc1/drivers/cpufreq/Kconfig
+--- linux-6.5-rc1/drivers/cpufreq/Kconfig.30~	2023-07-11 11:43:14.274842995 +0200
++++ linux-6.5-rc1/drivers/cpufreq/Kconfig	2023-07-11 11:45:19.299344290 +0200
 @@ -38,7 +38,6 @@ choice
  	prompt "Default CPUFreq governor"
- 	default CPU_FREQ_DEFAULT_GOV_USERSPACE if ARM_SA1100_CPUFREQ || ARM_SA1110_CPUFREQ
+ 	default CPU_FREQ_DEFAULT_GOV_USERSPACE if ARM_SA1110_CPUFREQ
  	default CPU_FREQ_DEFAULT_GOV_SCHEDUTIL if ARM64 || ARM
--	default CPU_FREQ_DEFAULT_GOV_SCHEDUTIL if X86_INTEL_PSTATE && SMP
+-	default CPU_FREQ_DEFAULT_GOV_SCHEDUTIL if (X86_INTEL_PSTATE || X86_AMD_PSTATE) && SMP
  	default CPU_FREQ_DEFAULT_GOV_PERFORMANCE
  	help
  	  This option sets which CPUFreq governor shall be loaded at
diff --git a/riscv-omv-defconfig b/riscv-omv-defconfig
new file mode 100644
index 0000000..79eb5c9
--- /dev/null
+++ b/riscv-omv-defconfig
@@ -0,0 +1,1458 @@
+CONFIG_64BIT=y
+CONFIG_ACLINT_SSWI=y
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_BATTERY=y
+CONFIG_ACPI_BGRT=y
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_CPPC_CPUFREQ_FIE=y
+CONFIG_ACPI_CPPC_CPUFREQ=m
+CONFIG_ACPI_FAN=y
+CONFIG_ACPI_GENERIC_GSI=y
+CONFIG_ACPI_HOTPLUG_MEMORY=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_ACPI_MDIO=y
+CONFIG_ACPI_PCC=y
+CONFIG_ACPI_PROCESSOR=m
+CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
+CONFIG_ACPI_THERMAL=m
+CONFIG_ACPI_VIDEO=m
+CONFIG_ACPI=y
+CONFIG_AF_RXRPC=m
+CONFIG_ALLOW_DEV_COREDUMP=y
+CONFIG_AMBA_PL08X=y
+CONFIG_AMD_QDMA=m
+CONFIG_ANDES_CUSTOM_PMU=y
+CONFIG_APERTURE_HELPERS=y
+CONFIG_ARCH_ANDES=y
+CONFIG_ARCH_CANAAN=y
+CONFIG_ARCH_DMA_DEFAULT_COHERENT=y
+CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
+CONFIG_ARCH_ESWIN=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_HAS_BINFMT_FLAT=y
+CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
+CONFIG_ARCH_HAS_DEBUG_WX=y
+CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_ARCH_HAS_MMIOWB=y
+CONFIG_ARCH_HAS_PMEM_API=y
+CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
+CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
+CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
+CONFIG_ARCH_HAS_VDSO_DATA=y
+CONFIG_ARCH_MICROCHIP_POLARFIRE=y
+CONFIG_ARCH_MICROCHIP=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_R9A07G043=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_RV64I=y
+CONFIG_ARCH_RZG2L=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SIFIVE=y
+CONFIG_ARCH_SOPHGO=y
+CONFIG_ARCH_SPACEMIT=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_STARFIVE=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_SUPPORTS_ACPI=y
+CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
+CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_ARCH_SUPPORTS_INT128=y
+CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y
+CONFIG_ARCH_SUPPORTS_KEXEC=y
+CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
+CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y
+CONFIG_ARCH_THEAD=y
+CONFIG_ARCH_USE_MEMREMAP_PROT=y
+CONFIG_ARCH_USE_MEMTEST=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_ARCH_VIRT=y
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
+CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_AS_IS_GNU=y
+CONFIG_AS_VERSION=24100
+CONFIG_ASYMMETRIC_KEY_SUBTYPE=y
+CONFIG_ATA_ACPI=y
+CONFIG_ATA_FORCE=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_ATA=y
+CONFIG_AT_XDMAC=m
+CONFIG_AUDIT_GENERIC=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT=y
+CONFIG_AUXILIARY_BUS=y
+CONFIG_AX45MP_L2_CACHE=y
+CONFIG_BACKLIGHT_88PM860X=m
+CONFIG_BACKLIGHT_AAT2870=m
+CONFIG_BACKLIGHT_ADP5520=m
+CONFIG_BACKLIGHT_AS3711=m
+CONFIG_BACKLIGHT_CLASS_DEVICE=m
+CONFIG_BACKLIGHT_DA903X=m
+CONFIG_BACKLIGHT_DA9052=m
+CONFIG_BACKLIGHT_KTD2801=m
+CONFIG_BACKLIGHT_LED=m
+CONFIG_BACKLIGHT_MAX8925=m
+CONFIG_BACKLIGHT_PANDORA=m
+CONFIG_BACKLIGHT_WM831X=m
+CONFIG_BATTERY_88PM860X=m
+CONFIG_BATTERY_DA9030=m
+CONFIG_BATTERY_DA9052=m
+CONFIG_BCM2712_MIP=m
+CONFIG_BD957XMUF_WATCHDOG=m
+CONFIG_BD96801_WATCHDOG=m
+CONFIG_BFQ_GROUP_IOSCHED=y
+CONFIG_BLK_CGROUP_PUNT_BIO=y
+CONFIG_BLK_DEBUG_FS=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_DM=m
+CONFIG_BLK_DEV_PMEM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_ICQ=y
+CONFIG_BLK_MQ_STACKING=y
+CONFIG_BLOCK_HOLDER_DEPRECATED=y
+CONFIG_BPF_UNPRIV_DEFAULT_OFF=y
+CONFIG_BTT=y
+CONFIG_BUG=y
+CONFIG_BUILD_SALT=""
+CONFIG_CC_CAN_LINK_STATIC=y
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
+CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
+CONFIG_CC_HAS_INT128=y
+CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
+CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_IS_GCC=y
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+CONFIG_CC_VERSION_TEXT="gcc (GCC) 13.1.1 20230722 (OpenMandriva)"
+CONFIG_CDROM=y
+CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUPS=y
+CONFIG_CHARGER_88PM860X=m
+CONFIG_CHARGER_MAX8997=m
+CONFIG_CHARGER_MAX8998=m
+CONFIG_CHARGER_TPS65090=m
+CONFIG_CLANG_VERSION=0
+CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y
+CONFIG_CLK_R9A07G043=y
+CONFIG_CLK_RENESAS=y
+CONFIG_CLK_RZG2L=y
+CONFIG_CLK_SIFIVE_PRCI=y
+CONFIG_CLK_SIFIVE=y
+CONFIG_CLK_SOPHGO_CV1800=m
+CONFIG_CLK_SOPHGO_SG2042_CLKGEN=m
+CONFIG_CLK_SOPHGO_SG2042_PLL=m
+CONFIG_CLK_SOPHGO_SG2042_RPGATE=m
+CONFIG_CLK_SOPHGO_SG2044=m
+CONFIG_CLK_SOPHGO_SG2044_PLL=m
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_STARFIVE_JH7100_AUDIO=m
+CONFIG_CLK_STARFIVE_JH7100=y
+CONFIG_CLK_STARFIVE_JH7110_AON=m
+CONFIG_CLK_STARFIVE_JH7110_ISP=m
+CONFIG_CLK_STARFIVE_JH7110_PLL=y
+CONFIG_CLK_STARFIVE_JH7110_STG=m
+CONFIG_CLK_STARFIVE_JH7110_SYS=y
+CONFIG_CLK_STARFIVE_JH7110_VOUT=m
+CONFIG_CLK_STARFIVE_JH71X0=y
+CONFIG_CLK_THEAD_TH1520_AP=y
+CONFIG_CLK_TWL6040=m
+CONFIG_CLK_TWL=m
+CONFIG_CLK_WM831X=m
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE=""
+CONFIG_CMODEL_MEDANY=y
+CONFIG_COMMON_CLK_BD718XX=m
+CONFIG_COMMON_CLK_LOCHNAGAR=m
+CONFIG_COMMON_CLK_MAX77686=m
+CONFIG_COMMON_CLK_PALMAS=m
+CONFIG_COMMON_CLK_RPMI=m
+CONFIG_COMMON_CLK_S2MPS11=m
+CONFIG_COMMON_CLK_WM831X=m
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_COMPAT_BRK=y
+CONFIG_COMPAT=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_PM=y
+CONFIG_CRC16=y
+CONFIG_CRC7=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CROS_EC_WATCHDOG=m
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_AES_RISCV64=m
+CONFIG_CRYPTO_BLAKE2B=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_CHACHA_RISCV64=m
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC64_ROCKSOFT=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_DEV_ALLWINNER=y
+CONFIG_CRYPTO_DEV_ATMEL_AES=m
+CONFIG_CRYPTO_DEV_CHELSIO=m
+CONFIG_CRYPTO_DEV_QAT_420XX=m
+CONFIG_CRYPTO_DEV_VIRTIO=y
+CONFIG_CRYPTO_DRBG=m
+CONFIG_CRYPTO_DRBG_MENU=m
+CONFIG_CRYPTO_ECHAINIV=m
+CONFIG_CRYPTO_ENGINE=y
+CONFIG_CRYPTO_GENIV=m
+CONFIG_CRYPTO_GHASH_RISCV64=m
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_JITTERENTROPY=m
+CONFIG_CRYPTO_LIB_AES=m
+CONFIG_CRYPTO_LIB_GF128MUL=m
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=m
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_NULL2=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_RNG_DEFAULT=m
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA256_RISCV64=m
+CONFIG_CRYPTO_SHA3=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_SHA512_RISCV64=m
+CONFIG_CRYPTO_SIG2=y
+CONFIG_CRYPTO_SM3_RISCV64=m
+CONFIG_CRYPTO_SM4_RISCV64=m
+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API=y
+CONFIG_CRYPTO_XXHASH=m
+CONFIG_CV1800_MBOX=m
+CONFIG_DA9052_WATCHDOG=m
+CONFIG_DA9055_WATCHDOG=m
+CONFIG_DA9062_THERMAL=m
+CONFIG_DA9062_WATCHDOG=m
+CONFIG_DAX=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_FS_ALLOW_ALL=y
+CONFIG_DEBUG_LIST=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_MISC=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_PAGEALLOC=y
+CONFIG_DEBUG_PER_CPU_MAPS=y
+CONFIG_DEBUG_PLIST=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_RWSEMS=y
+CONFIG_DEBUG_SG=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_TIMEKEEPING=y
+CONFIG_DEBUG_VM_IRQSOFF=y
+CONFIG_DEBUG_VM_PGFLAGS=y
+CONFIG_DEBUG_VM_PGTABLE=y
+CONFIG_DEBUG_VM=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DETECT_HUNG_TASK_BLOCKER=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEVICE_PRIVATE=y
+CONFIG_DMA_ACPI=y
+CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
+CONFIG_DMA_COHERENT_POOL=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_GLOBAL_POOL=y
+CONFIG_DMA_NONCOHERENT_MMAP=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_SUN6I=m
+CONFIG_DMA_VIRTUAL_CHANNELS=m
+CONFIG_DMIID=y
+CONFIG_DMI_SYSFS=m
+CONFIG_DMI=y
+CONFIG_DP83640_PHY=m
+CONFIG_DP83TG720_PHY=m
+CONFIG_DRM_AMD_ACP=y
+CONFIG_DRM_AMD_DC_SI=y
+CONFIG_DRM_AMD_DC=y
+CONFIG_DRM_AMDGPU_CIK=y
+CONFIG_DRM_AMDGPU=m
+CONFIG_DRM_AMDGPU_SI=y
+CONFIG_DRM_AMDGPU_USERPTR=y
+CONFIG_DRM_AMD_ISP=y
+CONFIG_DRM_APPLETBDRM=m
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_CLIENT_DEFAULT_FBDEV=y
+CONFIG_DRM_DISPLAY_DP_AUX_CEC=y
+CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV=y
+CONFIG_DRM_DISPLAY_DP_HELPER=y
+CONFIG_DRM_DISPLAY_HDMI_HELPER=y
+CONFIG_DRM_DISPLAY_HELPER=m
+CONFIG_DRM_DW_HDMI=m
+CONFIG_DRM_EFIDRM=m
+CONFIG_DRM_EXEC=m
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_GEM_DMA_HELPER=m
+CONFIG_DRM_GEM_SHMEM_HELPER=m
+CONFIG_DRM_I2C_CH7006=m
+CONFIG_DRM_I2C_SIL164=m
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER=m
+CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_NOUVEAU_BACKLIGHT=y
+CONFIG_DRM_NOUVEAU_CH7006=m
+CONFIG_DRM_NOUVEAU_GSP_DEFAULT=y
+CONFIG_DRM_NOUVEAU=m
+CONFIG_DRM_NOUVEAU_SIL164=m
+CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A=m
+CONFIG_DRM_PANEL_BOE_TV101WUM_LL2=m
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_HIMAX_HX83102=m
+CONFIG_DRM_PANEL_HIMAX_HX83112A=m
+CONFIG_DRM_PANEL_HIMAX_HX83112B=m
+CONFIG_DRM_PANEL_HYDIS_HV101HD1=m
+CONFIG_DRM_PANEL_ILITEK_ILI9341=m
+CONFIG_DRM_PANEL_ILITEK_ILI9805=m
+CONFIG_DRM_PANEL_ILITEK_ILI9806E=m
+CONFIG_DRM_PANEL_ILITEK_ILI9882T=m
+CONFIG_DRM_PANEL_JDI_LPM102A188A=m
+CONFIG_DRM_PANEL_LG_SW43408=m
+CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m
+CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m
+CONFIG_DRM_PANEL_RAYDIUM_RM67200=m
+CONFIG_DRM_PANEL_RAYDIUM_RM692E5=m
+CONFIG_DRM_PANEL_RAYDIUM_RM69380=m
+CONFIG_DRM_PANEL_RENESAS_R61307=m
+CONFIG_DRM_PANEL_RENESAS_R69328=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7=m
+CONFIG_DRM_PANEL_SAMSUNG_S6E8AA5X01_AMS561RA01=m
+CONFIG_DRM_PANEL_SUMMIT=m
+CONFIG_DRM_PANEL_SYNAPTICS_R63353=m
+CONFIG_DRM_PANEL_VISIONOX_RM692E5=m
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANIC_BACKGROUND_COLOR=0x000000
+CONFIG_DRM_PANIC_FOREGROUND_COLOR=0xa0a0a0
+CONFIG_DRM_PANIC_SCREEN="user"
+CONFIG_DRM_PANIC=y
+CONFIG_DRM_PIXPAPER=m
+CONFIG_DRM_POWERVR=m
+CONFIG_DRM_RADEON=m
+CONFIG_DRM_RADEON_USERPTR=y
+CONFIG_DRM_RZG2L_DU=m
+CONFIG_DRM_SCHED=m
+CONFIG_DRM_SOLOMON_SSD2825=m
+CONFIG_DRM_SUBALLOC_HELPER=m
+CONFIG_DRM_SUN4I=m
+CONFIG_DRM_SUN6I_DSI=m
+CONFIG_DRM_SUN8I_DW_HDMI=m
+CONFIG_DRM_SUN8I_MIXER=m
+CONFIG_DRM_SUN8I_TCON_TOP=m
+CONFIG_DRM_TTM_HELPER=m
+CONFIG_DRM_TTM=m
+CONFIG_DRM_VIRTIO_GPU_KMS=y
+CONFIG_DRM_VIRTIO_GPU=m
+CONFIG_DRM_WAVESHARE_BRIDGE=m
+CONFIG_DRM_XE_DEVMEM_MIRROR=y
+CONFIG_DRM_XE_DISPLAY=y
+CONFIG_DRM_XE_DP_TUNNEL=y
+CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT=y
+CONFIG_DRM_XE_FORCE_PROBE=""
+CONFIG_DRM_XE_GPUSVM=y
+CONFIG_DRM_XE_JOB_TIMEOUT_MAX=10000
+CONFIG_DRM_XE_JOB_TIMEOUT_MIN=1
+CONFIG_DRM_XE=m
+CONFIG_DRM_XE_PAGEMAP=y
+CONFIG_DRM_XE_PREEMPT_TIMEOUT=640000
+CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX=10000000
+CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN=1
+CONFIG_DRM_XE_TIMESLICE_MAX=10000000
+CONFIG_DRM_XE_TIMESLICE_MIN=1
+CONFIG_DRM=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_GENPD=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE_ROWS=30
+CONFIG_DUMMY=m
+CONFIG_DWC_PCIE_PMU=m
+CONFIG_DWMAC_GENERIC=m
+CONFIG_DWMAC_SOPHGO=m
+CONFIG_DWMAC_STARFIVE=m
+CONFIG_DWMAC_SUN8I=m
+CONFIG_DWMAC_SUNXI=m
+CONFIG_DWMAC_THEAD=m
+CONFIG_E1000E=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_GENERIC_STUB=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+CONFIG_EFI_VARS_PSTORE=m
+CONFIG_EFI=y
+CONFIG_ERRATA_ANDES_CMO=y
+CONFIG_ERRATA_ANDES=y
+CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE=y
+CONFIG_ERRATA_MIPS=y
+CONFIG_ERRATA_SIFIVE_CIP_1200=y
+CONFIG_ERRATA_SIFIVE_CIP_453=y
+CONFIG_ERRATA_SIFIVE=y
+CONFIG_ERRATA_THEAD_CMO=y
+CONFIG_ERRATA_THEAD_GHOSTWRITE=y
+CONFIG_ERRATA_THEAD_MAE=y
+CONFIG_ERRATA_THEAD_PBMT=y
+CONFIG_ERRATA_THEAD_PMU=y
+CONFIG_ERRATA_THEAD=y
+CONFIG_ETHERNET=y
+CONFIG_EXPERT=y
+CONFIG_EXTCON_LC824206XA=m
+CONFIG_EXTCON_MAX14526=m
+CONFIG_EXTCON_MAX77843=m
+CONFIG_EXTCON_MAX8997=m
+CONFIG_EXTCON_PALMAS=m
+CONFIG_EXTCON=y
+CONFIG_EXYNOS_MBOX=m
+CONFIG_FAILOVER=y
+CONFIG_FB_CORE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DEVICE=y
+CONFIG_FB_DMAMEM_HELPERS=y
+CONFIG_FB_IOMEM_HELPERS=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
+CONFIG_FB_SYSMEM_HELPERS=y
+CONFIG_FIPS_SIGNATURE_SELFTEST=m
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FPU=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FUEL_GAUGE_MM8013=m
+CONFIG_FUEL_GAUGE_STC3117=m
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FW_CFG_SYSFS_CMDLINE=y
+CONFIG_FW_CFG_SYSFS=m
+CONFIG_FWNODE_MDIO=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE=y
+CONFIG_GCC_VERSION=130101
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_ENTRY=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_IPI_MUX=y
+CONFIG_GENERIC_IRQ_IPI=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PHY_MIPI_DPHY=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_PTDUMP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_VDSO_TIME_NS=y
+CONFIG_GOLDFISH=y
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIO_ADP5520=m
+CONFIG_GPIO_ADP5585=m
+CONFIG_GPIO_BD71815=m
+CONFIG_GPIO_BD71828=m
+CONFIG_GPIO_CDEV_V1=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CROS_EC=m
+CONFIG_GPIO_DA9052=m
+CONFIG_GPIO_DA9055=m
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_LJCA=m
+CONFIG_GPIO_MAX77620=m
+CONFIG_GPIO_PALMAS=y
+CONFIG_GPIO_PL061=m
+CONFIG_GPIO_RC5T583=y
+CONFIG_GPIO_SIFIVE=y
+CONFIG_GPIO_SPACEMIT_K1=m
+CONFIG_GPIO_TC3589X=y
+CONFIG_GPIO_TPS6586X=y
+CONFIG_GPIO_TPS65910=y
+CONFIG_GPIO_TWL4030=m
+CONFIG_GPIO_TWL6040=m
+CONFIG_GPIO_WM831X=m
+CONFIG_GPIO_WM8350=m
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HDMI=y
+CONFIG_HIBERNATION_SNAPSHOT_DEV=y
+CONFIG_HIBERNATION=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HSA_AMD_SVM=y
+CONFIG_HSA_AMD=y
+CONFIG_HVC_RISCV_SBI=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ=250
+CONFIG_HZ_250=y
+CONFIG_I2C_ALGOBIT=m
+CONFIG_I2C_AT91=m
+CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL=y
+CONFIG_I2C_CADENCE=m
+CONFIG_I2C_DESIGNWARE_CORE=m
+CONFIG_I2C_DESIGNWARE_SLAVE=y
+CONFIG_I2C_K1=m
+CONFIG_I2C_LJCA=m
+CONFIG_I2C=m
+CONFIG_I2C_MUX_GPIO=m
+CONFIG_I2C_MUX_LTC4306=m
+CONFIG_I2C_MUX_MLXCPLD=m
+CONFIG_I2C_MUX_MULE=m
+CONFIG_I2C_MUX_PCA9541=m
+CONFIG_I2C_MUX_PCA954x=m
+CONFIG_I2C_MUX_REG=m
+CONFIG_I2C_MV64XXX=m
+CONFIG_I2C_NCT6694=m
+CONFIG_I2C_NOMADIK=m
+CONFIG_I2C_SLAVE_EEPROM=m
+CONFIG_I2C_SLAVE_TESTUNIT=m
+CONFIG_I2C_USBIO=m
+CONFIG_ICE_HWMON=y
+CONFIG_ICE=m
+CONFIG_IFB=m
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
+CONFIG_INIT_STACK_ALL_ZERO=y
+CONFIG_INPUT_LEDS=m
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_VIVALDIFMAP=y
+CONFIG_INTEGRITY_AUDIT=y
+CONFIG_INTEGRITY=y
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+CONFIG_IOSCHED_BFQ=y
+CONFIG_IPE_BOOT_POLICY=""
+CONFIG_IPE_POLICY_SIG_SECONDARY_KEYRING=y
+CONFIG_IPVLAN_L3S=y
+CONFIG_IPVLAN=m
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_STACKS=y
+CONFIG_JH71XX_PMU=y
+CONFIG_KCMP=y
+CONFIG_KERNEL_ZSTD=y
+CONFIG_KEXEC_HANDOVER=y
+CONFIG_KEYBOARD_ADP5520=m
+CONFIG_KEYBOARD_SUN4I_LRADC=m
+CONFIG_KEYBOARD_TC3589X=m
+CONFIG_KEYBOARD_TM2_TOUCHKEY=m
+CONFIG_KEYBOARD_TWL4030=m
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_XFER_TO_GUEST_WORK=y
+CONFIG_KVM=y
+CONFIG_LD_IS_LLD=y
+CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
+CONFIG_LD_ORPHAN_WARN=y
+CONFIG_LD_VERSION=0
+CONFIG_LEDS_88PM860X=m
+CONFIG_LEDS_AAT1290=m
+CONFIG_LEDS_ADP5520=m
+CONFIG_LEDS_AN30259A=m
+CONFIG_LEDS_AS3645A=m
+CONFIG_LEDS_AW200XX=m
+CONFIG_LEDS_AW2013=m
+CONFIG_LEDS_BCM6328=m
+CONFIG_LEDS_BCM6358=m
+CONFIG_LEDS_BD2606MVV=m
+CONFIG_LEDS_BD2802=m
+CONFIG_LEDS_BLINKM=m
+CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y
+CONFIG_LEDS_CLASS_FLASH=m
+CONFIG_LEDS_CLASS=m
+CONFIG_LEDS_CLASS_MULTICOLOR=m
+CONFIG_LEDS_CR0014114=m
+CONFIG_LEDS_CROS_EC=m
+CONFIG_LEDS_DA903X=m
+CONFIG_LEDS_DA9052=m
+CONFIG_LEDS_DAC124S085=m
+CONFIG_LEDS_EL15203000=m
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_GROUP_MULTICOLOR=m
+CONFIG_LEDS_IS31FL319X=m
+CONFIG_LEDS_IS31FL32XX=m
+CONFIG_LEDS_KTD202X=m
+CONFIG_LEDS_KTD2692=m
+CONFIG_LEDS_LM3530=m
+CONFIG_LEDS_LM3532=m
+CONFIG_LEDS_LM355x=m
+CONFIG_LEDS_LM3601X=m
+CONFIG_LEDS_LM3642=m
+CONFIG_LEDS_LM3692X=m
+CONFIG_LEDS_LM3697=m
+CONFIG_LEDS_LP3944=m
+CONFIG_LEDS_LP3952=m
+CONFIG_LEDS_LP50XX=m
+CONFIG_LEDS_LP5521=m
+CONFIG_LEDS_LP5523=m
+CONFIG_LEDS_LP5562=m
+CONFIG_LEDS_LP5569=m
+CONFIG_LEDS_LP55XX_COMMON=m
+CONFIG_LEDS_LP8501=m
+CONFIG_LEDS_LP8788=m
+CONFIG_LEDS_LP8860=m
+CONFIG_LEDS_LP8864=m
+CONFIG_LEDS_LT3593=m
+CONFIG_LEDS_MAX5970=m
+CONFIG_LEDS_MAX8997=m
+CONFIG_LEDS_MLXREG=m
+CONFIG_LEDS_NCP5623=m
+CONFIG_LEDS_PCA9532_GPIO=y
+CONFIG_LEDS_PCA9532=m
+CONFIG_LEDS_PCA955X_GPIO=y
+CONFIG_LEDS_PCA955X=m
+CONFIG_LEDS_PCA963X=m
+CONFIG_LEDS_PCA995X=m
+CONFIG_LEDS_REGULATOR=m
+CONFIG_LEDS_RT4505=m
+CONFIG_LEDS_RT8515=m
+CONFIG_LEDS_SGM3140=m
+CONFIG_LEDS_SPI_BYTE=m
+CONFIG_LEDS_ST1202=m
+CONFIG_LEDS_SUN50I_A100=m
+CONFIG_LEDS_SY7802=m
+CONFIG_LEDS_TCA6507=m
+CONFIG_LEDS_TLC591XX=m
+CONFIG_LEDS_TRIGGER_ACTIVITY=m
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_CAMERA=m
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_GPIO=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_NETDEV=m
+CONFIG_LEDS_TRIGGER_ONESHOT=m
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEDS_TRIGGER_PATTERN=m
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_TRANSIENT=m
+CONFIG_LEDS_TRIGGER_TTY=m
+CONFIG_LEDS_USER=m
+CONFIG_LEDS_WM831X_STATUS=m
+CONFIG_LEDS_WM8350=m
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_TIOCSTI=y
+CONFIG_LIBCRC32C=m
+CONFIG_LIBFDT=y
+CONFIG_LIBNVDIMM=y
+CONFIG_LINEAR_RANGES=y
+CONFIG_LIST_HARDENED=y
+CONFIG_LLD_VERSION=160006
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_MM_AND_FIND_VMA=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO=y
+CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,bpf"
+CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_LTO_NONE=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACB=y
+CONFIG_MACVLAN=m
+CONFIG_MAILBOX=y
+CONFIG_MANAGER_SBS=m
+CONFIG_MAX77620_THERMAL=m
+CONFIG_MAX77620_WATCHDOG=m
+CONFIG_MAX8925_POWER=m
+CONFIG_MCHP_CLK_MPFS=y
+CONFIG_MCHP_SBI_IPC_MBOX=m
+CONFIG_MD_BITMAP_FILE=y
+CONFIG_MDIO_BUS_MUX=m
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_GPIO=m
+CONFIG_MEMCG_KMEM=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y
+CONFIG_MEMORY_HOTPLUG=y
+CONFIG_MEMORY_HOTREMOVE=y
+CONFIG_MEMREGION=y
+CONFIG_MFD_88PM860X=y
+CONFIG_MFD_88PM886_PMIC=y
+CONFIG_MFD_AAT2870_CORE=y
+CONFIG_MFD_AAT2870_CORE=Y
+CONFIG_MFD_ADP5520=y
+CONFIG_MFD_AS3711=y
+CONFIG_MFD_AS3722=m
+CONFIG_MFD_DA9052_I2C=y
+CONFIG_MFD_DA9055=y
+CONFIG_MFD_DA9062=m
+CONFIG_MFD_LOCHNAGAR=y
+CONFIG_MFD_LP8788=y
+CONFIG_MFD_MAX7360=m
+CONFIG_MFD_MAX77541=m
+CONFIG_MFD_MAX77620=y
+CONFIG_MFD_MAX77759=m
+CONFIG_MFD_MAX77843=y
+CONFIG_MFD_MAX8925=y
+CONFIG_MFD_MAX8997=y
+CONFIG_MFD_MAX8998=y
+CONFIG_MFD_PALMAS=m
+CONFIG_MFD_QNAP_MCU=m
+CONFIG_MFD_RC5T583=y
+CONFIG_MFD_ROHM_BD71828=m
+CONFIG_MFD_ROHM_BD718XX=m
+CONFIG_MFD_ROHM_BD957XMUF=m
+CONFIG_MFD_ROHM_BD96801=m
+CONFIG_MFD_SEC_ACPM=m
+CONFIG_MFD_SEC_CORE=m
+CONFIG_MFD_SEC_I2C=m
+CONFIG_MFD_SPACEMIT_P1=m
+CONFIG_MFD_STPMIC1=m
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_TC3589X=y
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
+CONFIG_MFD_TWL4030_AUDIO=y
+CONFIG_MFD_WM831X_I2C=y
+CONFIG_MFD_WM8350_I2C=y
+CONFIG_MFD_WM8400=y
+CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO=y
+CONFIG_MICROSEMI_PHY=y
+CONFIG_MII=m
+CONFIG_MMC_ARMMMCI=m
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_NPCM=m
+CONFIG_MMC_SDHCI_OF_K1=m
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SPI=y
+CONFIG_MMC_STM32_SDMMC=y
+CONFIG_MMC_SUNXI=y
+CONFIG_MMC=y
+CONFIG_MMIOWB=y
+CONFIG_MMP_PDMA=m
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULE_SECTIONS=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOST_CDEV=m
+CONFIG_MOST=m
+CONFIG_MOST_SND=m
+CONFIG_MOST_USB_HDM=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_PIXART=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MQ_IOSCHED_KYBER=y
+CONFIG_MUX_ADG792A=m
+CONFIG_MUX_ADGS1408=m
+CONFIG_MUX_GPIO=m
+CONFIG_NCT6694_WATCHDOG=m
+CONFIG_ND_BTT=y
+CONFIG_ND_CLAIM=y
+CONFIG_NET_9P_FD=y
+CONFIG_NET_9P_USBG=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_NET_9P=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NETKIT=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_VENDOR_3COM=y
+CONFIG_NET_VENDOR_8390=y
+CONFIG_NET_VENDOR_ADAPTEC=y
+CONFIG_NET_VENDOR_ADI=y
+CONFIG_NET_VENDOR_AGERE=y
+CONFIG_NET_VENDOR_ALACRITECH=y
+CONFIG_NET_VENDOR_ALLWINNER=y
+CONFIG_NET_VENDOR_ALTEON=y
+CONFIG_NET_VENDOR_AMAZON=y
+CONFIG_NET_VENDOR_AMD=y
+CONFIG_NET_VENDOR_AQUANTIA=y
+CONFIG_NET_VENDOR_ARC=y
+CONFIG_NET_VENDOR_ASIX=y
+CONFIG_NET_VENDOR_ATHEROS=y
+CONFIG_NET_VENDOR_BROADCOM=y
+CONFIG_NET_VENDOR_BROCADE=y
+CONFIG_NET_VENDOR_CADENCE=y
+CONFIG_NET_VENDOR_CAVIUM=y
+CONFIG_NET_VENDOR_CHELSIO=y
+CONFIG_NET_VENDOR_CISCO=y
+CONFIG_NET_VENDOR_CORTINA=y
+CONFIG_NET_VENDOR_DAVICOM=y
+CONFIG_NET_VENDOR_DEC=y
+CONFIG_NET_VENDOR_DLINK=y
+CONFIG_NET_VENDOR_EMULEX=y
+CONFIG_NET_VENDOR_ENGLEDER=y
+CONFIG_NET_VENDOR_EZCHIP=y
+CONFIG_NET_VENDOR_FUNGIBLE=y
+CONFIG_NET_VENDOR_GOOGLE=y
+CONFIG_NET_VENDOR_HUAWEI=y
+CONFIG_NET_VENDOR_I825XX=y
+CONFIG_NET_VENDOR_INTEL=y
+CONFIG_NET_VENDOR_LITEX=y
+CONFIG_NET_VENDOR_MARVELL=y
+CONFIG_NET_VENDOR_MELLANOX=y
+CONFIG_NET_VENDOR_MICREL=y
+CONFIG_NET_VENDOR_MICROCHIP=y
+CONFIG_NET_VENDOR_MICROSEMI=y
+CONFIG_NET_VENDOR_MICROSOFT=y
+CONFIG_NET_VENDOR_MYRI=y
+CONFIG_NET_VENDOR_NATSEMI=y
+CONFIG_NET_VENDOR_NETERION=y
+CONFIG_NET_VENDOR_NETRONOME=y
+CONFIG_NET_VENDOR_NI=y
+CONFIG_NET_VENDOR_NVIDIA=y
+CONFIG_NET_VENDOR_OKI=y
+CONFIG_NET_VENDOR_PACKET_ENGINES=y
+CONFIG_NET_VENDOR_PENSANDO=y
+CONFIG_NET_VENDOR_QLOGIC=y
+CONFIG_NET_VENDOR_QUALCOMM=y
+CONFIG_NET_VENDOR_RDC=y
+CONFIG_NET_VENDOR_REALTEK=y
+CONFIG_NET_VENDOR_RENESAS=y
+CONFIG_NET_VENDOR_ROCKER=y
+CONFIG_NET_VENDOR_SAMSUNG=y
+CONFIG_NET_VENDOR_SEEQ=y
+CONFIG_NET_VENDOR_SILAN=y
+CONFIG_NET_VENDOR_SIS=y
+CONFIG_NET_VENDOR_SMSC=y
+CONFIG_NET_VENDOR_SOCIONEXT=y
+CONFIG_NET_VENDOR_SOLARFLARE=y
+CONFIG_NET_VENDOR_SPACEMIT=y
+CONFIG_NET_VENDOR_STMICRO=y
+CONFIG_NET_VENDOR_SUN=y
+CONFIG_NET_VENDOR_SYNOPSYS=y
+CONFIG_NET_VENDOR_TEHUTI=y
+CONFIG_NET_VENDOR_TI=y
+CONFIG_NET_VENDOR_VERTEXCOM=y
+CONFIG_NET_VENDOR_VIA=y
+CONFIG_NET_VENDOR_WANGXUN=y
+CONFIG_NET_VENDOR_WIZNET=y
+CONFIG_NET_VENDOR_XILINX=y
+CONFIG_NIC7018_WDT=m
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NOP_USB_XCEIV=m
+CONFIG_NOUVEAU_DEBUG=5
+CONFIG_NOUVEAU_DEBUG_DEFAULT=3
+CONFIG_NR_CPUS=64
+CONFIG_NSM=m
+CONFIG_NTSYNC=m
+CONFIG_NVDIMM_DAX=y
+CONFIG_NVDIMM_PFN=y
+CONFIG_NVMEM_SUNXI_SID=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_PMEM=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OF=y
+CONFIG_OVPN=m
+CONFIG_PAGE_BLOCK_MAX_ORDER=10
+CONFIG_PAGE_BLOCK_ORDER=10
+CONFIG_PAGE_OFFSET=0xff60000000000000
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_VERSION=125
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PARAVIRT=y
+CONFIG_PATA_TIMINGS=y
+CONFIG_PCC=y
+CONFIG_PCI_DOE=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCIEASPM_DEFAULT=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIE_BUS_DEFAULT=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_FU740=y
+CONFIG_PCIE_PME=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_RCAR_GEN4_HOST=m
+CONFIG_PCIE_SG2042_HOST=m
+CONFIG_PCIE_SOPHGO_DW=y
+CONFIG_PCIE_STARFIVE_HOST=m
+CONFIG_PCIE_XILINX_DMA_PL=y
+CONFIG_PCIE_XILINX=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_LABEL=y
+CONFIG_PCI_P2PDMA=y
+CONFIG_PCS_XPCS=m
+CONFIG_PER_VMA_LOCK=y
+CONFIG_PGTABLE_LEVELS=5
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHY_SOPHGO_CV1800_USB2=m
+CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m
+CONFIG_PHY_STARFIVE_JH7110_DPHY_TX=m
+CONFIG_PHY_STARFIVE_JH7110_PCIE=m
+CONFIG_PHY_STARFIVE_JH7110_USB=m
+CONFIG_PHY_SUN4I_USB=m
+CONFIG_PHY_SUN6I_MIPI_DPHY=m
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_AMDISP=m
+CONFIG_PINCTRL_AS3722=m
+CONFIG_PINCTRL_AW9523=m
+CONFIG_PINCTRL_DA9062=m
+CONFIG_PINCTRL_EIC7700=m
+CONFIG_PINCTRL_K230=y
+CONFIG_PINCTRL_LOCHNAGAR=m
+CONFIG_PINCTRL_MAX7360=m
+CONFIG_PINCTRL_MAX77620=m
+CONFIG_PINCTRL_PALMAS=m
+CONFIG_PINCTRL_PEF2256=m
+CONFIG_PINCTRL_RENESAS=y
+CONFIG_PINCTRL_RZG2L=y
+CONFIG_PINCTRL_SOPHGO_CV1800B=m
+CONFIG_PINCTRL_SOPHGO_CV1812H=m
+CONFIG_PINCTRL_SOPHGO_SG2000=m
+CONFIG_PINCTRL_SOPHGO_SG2002=m
+CONFIG_PINCTRL_SOPHGO_SG2042=m
+CONFIG_PINCTRL_SOPHGO_SG2044=m
+CONFIG_PINCTRL_SPACEMIT_K1=y
+CONFIG_PINCTRL_STARFIVE_JH7100=y
+CONFIG_PINCTRL_STARFIVE_JH7110_AON=y
+CONFIG_PINCTRL_STARFIVE_JH7110_SYS=y
+CONFIG_PINCTRL_STARFIVE_JH7110=y
+CONFIG_PINCTRL_SUN20I_D1=y
+CONFIG_PINCTRL_SUNXI=y
+CONFIG_PINCTRL_SX150X=y
+CONFIG_PINCTRL_TH1520=m
+CONFIG_PINCTRL_TPS6594=m
+CONFIG_PINCTRL=y
+CONFIG_PINMUX=y
+CONFIG_PKCS7_TEST_KEY=m
+CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
+CONFIG_PL330_DMA=m
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PMIC_ADP5520=y
+CONFIG_PMIC_DA903X=y
+CONFIG_PM_STD_PARTITION=""
+CONFIG_PNPACPI=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+CONFIG_PNP=y
+CONFIG_POLARFIRE_SOC_MAILBOX=m
+CONFIG_PORTABLE=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET_AS3722=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_TH1520_AON=m
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PREEMPT_NONE=y
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK_INES=m
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PTP_1588_CLOCK_QORIQ=m
+CONFIG_PWRSEQ_EMMC=y
+CONFIG_PWRSEQ_SD8787=m
+CONFIG_PWRSEQ_SIMPLE=y
+CONFIG_QCA807X_PHY=m
+CONFIG_QCA808X_PHY=m
+CONFIG_QCA83XX_PHY=m
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_R8169_LEDS=y
+CONFIG_R8169=y
+CONFIG_RAID6_PQ_BENCHMARK=y
+CONFIG_RAID6_PQ=m
+CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_EQS_DEBUG=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGUALTOR_STPMIC1=m
+CONFIG_REGULATOR_88PM8607=m
+CONFIG_REGULATOR_88PM886=m
+CONFIG_REGULATOR_AAT2870=m
+CONFIG_REGULATOR_ADP5055=m
+CONFIG_REGULATOR_AS3711=m
+CONFIG_REGULATOR_AS3722=m
+CONFIG_REGULATOR_BD71815=m
+CONFIG_REGULATOR_BD71828=m
+CONFIG_REGULATOR_BD718XX=m
+CONFIG_REGULATOR_BD957XMUF=m
+CONFIG_REGULATOR_BD96801=m
+CONFIG_REGULATOR_BQ257XX=m
+CONFIG_REGULATOR_DA9052=m
+CONFIG_REGULATOR_DA9055=m
+CONFIG_REGULATOR_DA9062=m
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_LOCHNAGAR=m
+CONFIG_REGULATOR_LP8788=m
+CONFIG_REGULATOR_MAX5970=m
+CONFIG_REGULATOR_MAX77503=m
+CONFIG_REGULATOR_MAX77541=m
+CONFIG_REGULATOR_MAX77620=m
+CONFIG_REGULATOR_MAX77693=m
+CONFIG_REGULATOR_MAX77838=m
+CONFIG_REGULATOR_MAX8925=m
+CONFIG_REGULATOR_MAX8997=m
+CONFIG_REGULATOR_MAX8998=m
+CONFIG_REGULATOR_NETLINK_EVENTS=y
+CONFIG_REGULATOR_PALMAS=m
+CONFIG_REGULATOR_PF0900=m
+CONFIG_REGULATOR_PF530X=m
+CONFIG_REGULATOR_PF9453=m
+CONFIG_REGULATOR_QCOM_PM8008=m
+CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
+CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2=m
+CONFIG_REGULATOR_RC5T583=m
+CONFIG_REGULATOR_RT5133=m
+CONFIG_REGULATOR_S2DOS05=m
+CONFIG_REGULATOR_S2MPA01=m
+CONFIG_REGULATOR_S2MPS11=m
+CONFIG_REGULATOR_S5M8767=m
+CONFIG_REGULATOR_SPACEMIT_P1=m
+CONFIG_REGULATOR_STPMIC1=m
+CONFIG_REGULATOR_TPS65090=m
+CONFIG_REGULATOR_TPS6586X=m
+CONFIG_REGULATOR_TPS65910=m
+CONFIG_REGULATOR_TWL4030=m
+CONFIG_REGULATOR_WM831X=m
+CONFIG_REGULATOR_WM8350=m
+CONFIG_REGULATOR_WM8400=m
+CONFIG_REGULATOR=y
+CONFIG_RENESAS_RZG2L_IRQC=y
+CONFIG_RENESAS_RZV2HWDT=m
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_K230=m
+CONFIG_RESET_POLARFIRE_SOC=y
+CONFIG_RESET_SIMPLE=y
+CONFIG_RESET_SPACEMIT=m
+CONFIG_RESET_STARFIVE_JH7100=y
+CONFIG_RESET_STARFIVE_JH7110=y
+CONFIG_RESET_STARFIVE_JH71X0=y
+CONFIG_RESET_SUNXI=y
+CONFIG_RESET_TH1520=m
+CONFIG_RISCV_ALTERNATIVE_EARLY=y
+CONFIG_RISCV_ALTERNATIVE=y
+CONFIG_RISCV_COMBO_SPINLOCKS=y
+CONFIG_RISCV_DMA_NONCOHERENT=y
+CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS=y
+CONFIG_RISCV_INTC=y
+CONFIG_RISCV_IOMMU=y
+CONFIG_RISCV_ISA_C=y
+CONFIG_RISCV_ISA_FALLBACK=y
+CONFIG_RISCV_ISA_SUPM=y
+CONFIG_RISCV_ISA_SVNAPOT=y
+CONFIG_RISCV_ISA_SVPBMT=y
+CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y
+CONFIG_RISCV_ISA_VENDOR_EXT_ANDES=y
+CONFIG_RISCV_ISA_VENDOR_EXT_MIPS=y
+CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE=y
+CONFIG_RISCV_ISA_VENDOR_EXT_THEAD=y
+CONFIG_RISCV_ISA_V_PREEMPTIVE=y
+CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD=768
+CONFIG_RISCV_ISA_V=y
+CONFIG_RISCV_ISA_XTHEADVECTOR=y
+CONFIG_RISCV_ISA_ZABHA=y
+CONFIG_RISCV_ISA_ZACAS=y
+CONFIG_RISCV_ISA_ZAWRS=y
+CONFIG_RISCV_ISA_ZBA=y
+CONFIG_RISCV_ISA_ZBB=y
+CONFIG_RISCV_ISA_ZBC=y
+CONFIG_RISCV_ISA_ZBKB=y
+CONFIG_RISCV_ISA_ZICBOM=y
+CONFIG_RISCV_ISA_ZICBOP=y
+CONFIG_RISCV_ISA_ZICBOZ=y
+CONFIG_RISCV_MISALIGNED=y
+CONFIG_RISCV_NONSTANDARD_CACHE_OPS=y
+CONFIG_RISCV_PMU_LEGACY=y
+CONFIG_RISCV_PMU_SBI=y
+CONFIG_RISCV_PMU=y
+CONFIG_RISCV_SBI_CPUIDLE=y
+CONFIG_RISCV_SBI_MPXY_MBOX=m
+CONFIG_RISCV_SBI=y
+CONFIG_RISCV_TIMER=y
+CONFIG_RISCV=y
+CONFIG_ROHM_BD79112=m
+CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_CTRL=y
+CONFIG_RPMSG_NS=y
+CONFIG_RPMSG_QCOM_GLINK_RPM=m
+CONFIG_RPMSG_VIRTIO=y
+CONFIG_RPMSG=y
+CONFIG_RTC_DRV_88PM860X=m
+CONFIG_RTC_DRV_AS3722=m
+CONFIG_RTC_DRV_BD70528=m
+CONFIG_RTC_DRV_CV1800=m
+CONFIG_RTC_DRV_DA9052=m
+CONFIG_RTC_DRV_DA9055=m
+CONFIG_RTC_DRV_DA9063=m
+CONFIG_RTC_DRV_GOLDFISH=y
+CONFIG_RTC_DRV_LP8788=m
+CONFIG_RTC_DRV_MAX31335=m
+CONFIG_RTC_DRV_MAX77686=m
+CONFIG_RTC_DRV_MAX8925=m
+CONFIG_RTC_DRV_MAX8997=m
+CONFIG_RTC_DRV_MAX8998=m
+CONFIG_RTC_DRV_NCT6694=m
+CONFIG_RTC_DRV_PALMAS=m
+CONFIG_RTC_DRV_PL030=m
+CONFIG_RTC_DRV_PL031=m
+CONFIG_RTC_DRV_RC5T583=m
+CONFIG_RTC_DRV_S5M=m
+CONFIG_RTC_DRV_SPACEMIT_P1=m
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_RTC_DRV_TPS6586X=m
+CONFIG_RTC_DRV_TPS65910=m
+CONFIG_RTC_DRV_TPS6594=m
+CONFIG_RTC_DRV_TWL4030=m
+CONFIG_RTC_DRV_WM831X=m
+CONFIG_RTC_DRV_WM8350=m
+CONFIG_RTC_I2C_AND_SPI=m
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_RXPERF=m
+CONFIG_RZG3E_THERMAL=m
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_AHCI=y
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHED_MM_CID=y
+CONFIG_SCHED_STACK_END_CHECK=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SCSI_MOD=y
+CONFIG_SCSI_PROC_FS=y
+CONFIG_SCSI_VIRTIO=y
+CONFIG_SCSI=y
+CONFIG_SECONDARY_TRUSTED_KEYRING=y
+CONFIG_SECRETMEM=y
+CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y
+CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
+CONFIG_SECURITY_APPARMOR_HASH=y
+CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y
+CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y
+CONFIG_SECURITY_APPARMOR=y
+CONFIG_SECURITY_IPE=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_SECURITY_PATH=y
+CONFIG_SECURITY_SELINUX_AVC_STATS=y
+CONFIG_SECURITY_SELINUX_DEVELOP=y
+CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256
+CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_SENSORS_DA9055=m
+CONFIG_SENSORS_LOCHNAGAR=m
+CONFIG_SENSORS_SFCTEMP=m
+CONFIG_SENSORS_SG2042_MCU=m
+CONFIG_SENSORS_WM8350=m
+CONFIG_SENSORS_XGENE=m
+CONFIG_SERIAL_8250_16550A_VARIANTS=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PERICOM=y
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_AMBA_PL010=m
+CONFIG_SERIAL_AMBA_PL011=m
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_RSCI=m
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_SH_SCI_DMA=y
+CONFIG_SERIAL_SH_SCI_EARLYCON=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=18
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SIFIVE_CONSOLE=y
+CONFIG_SERIAL_SIFIVE=y
+CONFIG_SERIO_AMBAKMI=m
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO=y
+CONFIG_SIFIVE_PLIC=y
+CONFIG_SIGNED_PE_FILE_VERIFICATION=y
+CONFIG_SLAB_MERGE_DEFAULT=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SOC_BUS=y
+CONFIG_SOCK_CGROUP_DATA=y
+CONFIG_SOC_MICROCHIP_POLARFIRE=y
+CONFIG_SOC_RENESAS=y
+CONFIG_SOC_SIFIVE=y
+CONFIG_SOC_STARFIVE=y
+CONFIG_SOC_VIRT=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_SOPHGO_CV1800B_DMAMUX=m
+CONFIG_SOPHGO_CV1800_RTCSYS=m
+CONFIG_SOPHGO_SG2042_MSI=y
+CONFIG_SOPHGO_SG2044_TOPSYS=m
+CONFIG_SPACEMIT_CCU=m
+CONFIG_SPACEMIT_K1_CCU=m
+CONFIG_SPACEMIT_K1_EMAC=m
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPI_ATMEL=m
+CONFIG_SPI_CH341=m
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_LJCA=m
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_PL022=m
+CONFIG_SPI_RZV2H_RSPI=m
+CONFIG_SPI_SG2044_NOR=m
+CONFIG_SPI_SIFIVE=y
+CONFIG_SPI_SUN6I=y
+CONFIG_SPI_VIRTIO=m
+CONFIG_SPI=y
+CONFIG_SSB_DRIVER_GPIO=y
+CONFIG_SSB=m
+CONFIG_SSB_SDIOHOST=y
+CONFIG_STACKDEPOT_MAX_FRAMES=64
+CONFIG_STACKDEPOT=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKTRACE=y
+CONFIG_STANDALONE=y
+CONFIG_STARFIVE_JH8100_INTC=y
+CONFIG_STARFIVE_STARLINK_CACHE=y
+CONFIG_STARFIVE_STARLINK_PMU=y
+CONFIG_STARFIVE_WATCHDOG=y
+CONFIG_STMMAC_ETH=m
+CONFIG_STMMAC_PLATFORM=m
+CONFIG_STPMIC1_WATCHDOG=m
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+CONFIG_SUN20I_D1_CCU=y
+CONFIG_SUN20I_D1_R_CCU=y
+CONFIG_SUN4I_TIMER=y
+CONFIG_SUN50I_IOMMU=y
+CONFIG_SUN6I_MSGBOX=m
+CONFIG_SUN6I_RTC_CCU=y
+CONFIG_SUN8I_DE2_CCU=m
+CONFIG_SUNXI_CCU=y
+CONFIG_SUNXI_SRAM=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096
+CONFIG_SYSTEM_EXTRA_CERTIFICATE=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_TH1520_AON_PROTOCOL=m
+CONFIG_TH1520_PM_DOMAINS=m
+CONFIG_THEAD_C900_ACLINT_SSWI=y
+CONFIG_THEAD_TH1520_MBOX=m
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_THREAD_SIZE_ORDER=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y
+CONFIG_TOOLS_SUPPORT_RELR=y
+CONFIG_TPS65090=y
+CONFIG_TUNE_GENERIC=y
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_WATCHDOG=m
+CONFIG_TWL6040_CORE=y
+CONFIG_UCS2_STRING=y
+CONFIG_UIO_AEC=m
+CONFIG_UIO_CIF=m
+CONFIG_UIO_DMEM_GENIRQ=m
+CONFIG_UIO_MF624=m
+CONFIG_UIO_NETX=m
+CONFIG_UIO_PCI_GENERIC=m
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_UIO_PRUSS=m
+CONFIG_UIO_SERCOS3=m
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_USB_ATM=m
+CONFIG_USB_COMMON=y
+CONFIG_USB_CXACRU=m
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_HCD_SSB=m
+CONFIG_USB_LEDS_TRIGGER_USBPORT=m
+CONFIG_USB_LED_TRIG=y
+CONFIG_USB_LJCA=m
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_SUNXI=m
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_PHY=y
+CONFIG_USB_SPEEDTOUCH=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_UAS=y
+CONFIG_USB_UEAGLEATM=m
+CONFIG_USB_USBIO=m
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_XHCI_RCAR=y
+CONFIG_USB_XUSBATM=m
+CONFIG_USB=y
+CONFIG_VETH=m
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VGA_CONSOLE=y
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIDEO_NOMODESET=y
+CONFIG_VIRTIO_ANCHOR=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
+CONFIG_VIRTIO_INPUT=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_PCI_LIB_LEGACY=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_VMAP_STACK=y
+CONFIG_VSOCKMON=m
+CONFIG_VXLAN=m
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=0
+CONFIG_WATCHDOG=y
+CONFIG_WLAN_VENDOR_CISCO=y
+CONFIG_WM831X_BACKUP=m
+CONFIG_WM831X_POWER=m
+CONFIG_WM831X_WATCHDOG=m
+CONFIG_WM8350_POWER=m
+CONFIG_WM8350_WATCHDOG=m
+CONFIG_WQ_WATCHDOG=y
+CONFIG_XOR_BLOCKS=m
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_ZL3073X_SPI=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_ZONE_DEVICE=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZRAM_MEMORY_TRACKING=y
+CONFIG_ZRAM_MULTI_COMP=y
+CONFIG_ZRAM_TRACK_ENTRY_ACTIME=y
+CONFIG_ZRAM_WRITEBACK=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_NEXUS=m
diff --git a/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch b/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch
index 8ca2079..ccfb978 100644
--- a/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch
+++ b/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch
@@ -1,7 +1,7 @@
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
 index bcd31e9d6..91f1aa809 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
 @@ -396,6 +396,7 @@ usbdrd_dwc3_0: usb@fe800000 {
  			snps,dis_u2_susphy_quirk;
  			snps,dis-del-phy-power-chg-quirk;
diff --git a/rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch b/rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch
deleted file mode 100644
index 662969f..0000000
--- a/rk3399-pci-rockchip-support-ep-gpio-undefined-case.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 9de42a7ce7b821596a151cfaa0aca79d53c2170f Mon Sep 17 00:00:00 2001
-From: Igor Pecovnik <igor.pecovnik@gmail.com>
-Date: Sun, 7 Mar 2021 15:24:02 +0100
-Subject: [PATCH] oo
-
-Signed-off-by: Aditya Prayoga <aditya@kobol.io>
-Changed by: Igor Pecovnik <igor.pecovnik@gmail.com>
----
- drivers/pci/controller/pcie-rockchip.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
-index 990a00e08..193d26562 100644
---- a/drivers/pci/controller/pcie-rockchip.c
-+++ b/drivers/pci/controller/pcie-rockchip.c
-@@ -118,8 +118,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
- 	}
- 
- 	if (rockchip->is_rc) {
--		rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",
--							    GPIOD_OUT_HIGH);
-+		rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep", GPIOD_OUT_HIGH);
- 		if (IS_ERR(rockchip->ep_gpio))
- 			return dev_err_probe(dev, PTR_ERR(rockchip->ep_gpio),
- 					     "failed to get ep GPIO\n");
--- 
-Created with Armbian build tools https://github.com/armbian/build
-
diff --git a/rk3399-rp64-rng.patch b/rk3399-rp64-rng.patch
index 3871bc4..c8a71e6 100644
--- a/rk3399-rp64-rng.patch
+++ b/rk3399-rp64-rng.patch
@@ -8,10 +8,10 @@ Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++++++++++
  1 file changed, 10 insertions(+)
 
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
 index a75abfa5c..58592da35 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
 @@ -2057,6 +2057,16 @@ edp_in_vopl: endpoint@1 {
  		};
  	};
diff --git a/rk3399-sd-drive-level-8ma.patch b/rk3399-sd-drive-level-8ma.patch
index cac129a..61f32a9 100644
--- a/rk3399-sd-drive-level-8ma.patch
+++ b/rk3399-sd-drive-level-8ma.patch
@@ -1,7 +1,7 @@
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
 index 6eb9dda..d6fc676 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
 @@ -2285,35 +2285,35 @@
  		sdmmc {
  			sdmmc_bus1: sdmmc-bus1 {
diff --git a/rk3399-unlock-temperature.patch b/rk3399-unlock-temperature.patch
index c1c2196..688b0fd 100644
--- a/rk3399-unlock-temperature.patch
+++ b/rk3399-unlock-temperature.patch
@@ -1,8 +1,107 @@
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-index 8a8cf0e..6cef1e3 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -722,17 +722,17 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: ThomasKaiser <github@kaiser-edv.de>
+Date: Sat, 13 Oct 2018 16:35:07 +0200
+Subject: [ARCHEOLOGY] Increase performance with rk3399-dev
+
+> X-Git-Archeology: - Revision b28fa47aa8b9864ccae8b90ebb3d46ae55103d6e: https://github.com/armbian/build/commit/b28fa47aa8b9864ccae8b90ebb3d46ae55103d6e
+> X-Git-Archeology:   Date: Sat, 13 Oct 2018 16:35:07 +0200
+> X-Git-Archeology:   From: ThomasKaiser <github@kaiser-edv.de>
+> X-Git-Archeology:   Subject: Increase performance with rk3399-dev
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision f18360d1ef5d6487392ff4079301bca97945e704: https://github.com/armbian/build/commit/f18360d1ef5d6487392ff4079301bca97945e704
+> X-Git-Archeology:   Date: Wed, 24 Oct 2018 17:03:35 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igor.pecovnik@gmail.com>
+> X-Git-Archeology:   Subject: [rk3399-dev] Merging rk3399-DEV with rockchip64-DEV on sources, patches and config level. Leave family intact, add 1.5 OPP for RK3328, add upstream patch for rk3399-default
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 150ac0c2afa147d9e3b036c8ecd8238fe5648cf3: https://github.com/armbian/build/commit/150ac0c2afa147d9e3b036c8ecd8238fe5648cf3
+> X-Git-Archeology:   Date: Tue, 19 Nov 2019 23:25:39 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Remove K<4, change branches, new features (#1586)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dfd5cf9692e97774f7f0bfd72227144e36f58070: https://github.com/armbian/build/commit/dfd5cf9692e97774f7f0bfd72227144e36f58070
+> X-Git-Archeology:   Date: Sun, 13 Dec 2020 22:13:03 -0500
+> X-Git-Archeology:   From: tonymac32 <tonymckahan@gmail.com>
+> X-Git-Archeology:   Subject: [ rockchip64 ] Clean up patchset
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153
+> X-Git-Archeology:   Date: Wed, 24 Mar 2021 19:01:53 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Renaming DEV branch to EDGE (#2704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0
+> X-Git-Archeology:   Date: Thu, 22 Jul 2021 00:15:54 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Second part of EDGE bumping to 5.13.y (#3045)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39
+> X-Git-Archeology:   Date: Wed, 08 Sep 2021 17:51:34 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bumping EDGE kernel to 5.14.y (#3125)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e
+> X-Git-Archeology:   Date: Tue, 09 Nov 2021 18:06:34 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4
+> X-Git-Archeology:   Date: Tue, 11 Jan 2022 15:26:11 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel edge to 5.16 (#3387)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d
+> X-Git-Archeology:   Date: Sat, 26 Feb 2022 07:46:44 +0100
+> X-Git-Archeology:   From: Piotr Szczepanik <piter75@gmail.com>
+> X-Git-Archeology:   Subject: Switch rockchip64 current to linux 5.15.y (#3489)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision f52a4193d02ef88333ba117c68d49486dfd7ff41: https://github.com/armbian/build/commit/f52a4193d02ef88333ba117c68d49486dfd7ff41
+> X-Git-Archeology:   Date: Sun, 20 Mar 2022 22:58:21 +0100
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: Adding Pine64 Quartz64a as WIP target (#3539)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 0afe24c95729044910e0b3f84dc5500bcdc6524c: https://github.com/armbian/build/commit/0afe24c95729044910e0b3f84dc5500bcdc6524c
+> X-Git-Archeology:   Date: Sun, 24 Apr 2022 22:33:47 +0200
+> X-Git-Archeology:   From: Oleg <balbes-150@yandex.ru>
+> X-Git-Archeology:   Subject: move kernel media edge to 5.17 (#3704)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f
+> X-Git-Archeology:   Date: Tue, 03 May 2022 08:27:32 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump and freeze kernel at last known working versions (#3736)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3
+> X-Git-Archeology:   Date: Sat, 28 May 2022 07:56:22 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64-edge to 5.18 (#3814)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0
+> X-Git-Archeology:   Date: Wed, 03 Aug 2022 22:22:55 +0200
+> X-Git-Archeology:   From: Jianfeng Liu <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: update rockchip64 edge to 5.19 (#4039)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6
+> X-Git-Archeology:   Date: Tue, 25 Oct 2022 11:26:51 +0200
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Bump rockchip64 edge to 6.0.y (#4337)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7
+> X-Git-Archeology:   Date: Fri, 16 Dec 2022 13:38:13 +0100
+> X-Git-Archeology:   From: Igor Pecovnik <igorpecovnik@users.noreply.github.com>
+> X-Git-Archeology:   Subject: Re-add rockchip64 6.0 patches (#4575)
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245
+> X-Git-Archeology:   Date: Fri, 05 May 2023 14:22:00 +0200
+> X-Git-Archeology:   From: amazingfate <liujianfeng1994@gmail.com>
+> X-Git-Archeology:   Subject: bump rockchip64 edge to v6.3
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
+@@ -928,17 +928,17 @@ cpu_thermal: cpu-thermal {
  
  			trips {
  				cpu_alert0: cpu_alert0 {
@@ -23,3 +122,6 @@ index 8a8cf0e..6cef1e3 100644
  					hysteresis = <2000>;
  					type = "critical";
  				};
+-- 
+Armbian
+
diff --git a/rtla-5.17-fix-make-clean.patch b/rtla-5.17-fix-make-clean.patch
deleted file mode 100644
index 20269b3..0000000
--- a/rtla-5.17-fix-make-clean.patch
+++ /dev/null
@@ -1,13 +0,0 @@
-diff -up linux-5.17/tools/tracing/rtla/Makefile.omv~ linux-5.17/tools/tracing/rtla/Makefile
---- linux-5.17/tools/tracing/rtla/Makefile.omv~	2022-03-26 21:48:35.505914845 +0100
-+++ linux-5.17/tools/tracing/rtla/Makefile	2022-03-26 21:48:42.262956229 +0100
-@@ -81,8 +81,6 @@ clean: doc_clean
- 	@test ! -f rtla || rm rtla
- 	@test ! -f rtla-static || rm rtla-static
- 	@test ! -f src/rtla.o || rm src/rtla.o
--	@test ! -f $(TARBALL) || rm -f $(TARBALL)
--	@rm -rf *~ $(OBJ) *.tar.$(CEXT)
- 
- tarball: clean
- 	rm -rf $(NAME)-$(VERSION) && mkdir $(NAME)-$(VERSION)
-diff -up linux-5.17/tools/tracing/rtla/.omv~ linux-5.17/tools/tracing/rtla/
diff --git a/security.fragment b/security.fragment
new file mode 100644
index 0000000..baa7da8
--- /dev/null
+++ b/security.fragment
@@ -0,0 +1,3 @@
+CONFIG_SECURITY=y
+CONFIG_SECURITY_LANDLOCK=y
+CONFIG_SECURITY_DMESG_RESTRICT=y
diff --git a/security_tirdad.patch b/security_tirdad.patch
new file mode 100644
index 0000000..f983387
--- /dev/null
+++ b/security_tirdad.patch
@@ -0,0 +1,46 @@
+diff -up linux-7.0-rc3/net/core/secure_seq.c.28~ linux-7.0-rc3/net/core/secure_seq.c
+--- linux-7.0-rc3/net/core/secure_seq.c.28~	2026-03-09 00:56:54.000000000 +0100
++++ linux-7.0-rc3/net/core/secure_seq.c	2026-03-10 16:48:48.988208563 +0100
+@@ -51,26 +51,11 @@ union tcp_seq_and_ts_off
+ secure_tcpv6_seq_and_ts_off(const struct net *net, const __be32 *saddr,
+ 			    const __be32 *daddr, __be16 sport, __be16 dport)
+ {
+-	const struct {
+-		struct in6_addr saddr;
+-		struct in6_addr daddr;
+-		__be16 sport;
+-		__be16 dport;
+-	} __aligned(SIPHASH_ALIGNMENT) combined = {
+-		.saddr = *(struct in6_addr *)saddr,
+-		.daddr = *(struct in6_addr *)daddr,
+-		.sport = sport,
+-		.dport = dport
+-	};
+ 	union tcp_seq_and_ts_off st;
+ 
+-	net_secret_init();
+-
+-	st.hash64 = siphash(&combined, offsetofend(typeof(combined), dport),
+-			    &net_secret);
+-
+ 	if (READ_ONCE(net->ipv4.sysctl_tcp_timestamps) != 1)
+ 		st.ts_off = 0;
++	get_random_bytes(((char*)&st.hash64), sizeof(st.hash64));
+ 
+ 	st.seq = seq_scale(st.seq);
+ 	return st;
+@@ -108,13 +93,9 @@ union tcp_seq_and_ts_off
+ secure_tcp_seq_and_ts_off(const struct net *net, __be32 saddr, __be32 daddr,
+ 			  __be16 sport, __be16 dport)
+ {
+-	u32 ports = (__force u32)sport << 16 | (__force u32)dport;
+ 	union tcp_seq_and_ts_off st;
+ 
+-	net_secret_init();
+-
+-	st.hash64 = siphash_3u32((__force u32)saddr, (__force u32)daddr,
+-				 ports, &net_secret);
++	get_random_bytes(((char *)&st.hash64), sizeof(st.hash64));
+ 
+ 	if (READ_ONCE(net->ipv4.sysctl_tcp_timestamps) != 1)
+ 		st.ts_off = 0;
diff --git a/sensors.fragment b/sensors.fragment
new file mode 100644
index 0000000..f285134
--- /dev/null
+++ b/sensors.fragment
@@ -0,0 +1,308 @@
+#
+# Native drivers
+#
+CONFIG_SENSORS_AD7314=m
+CONFIG_SENSORS_AD7414=m
+CONFIG_SENSORS_AD7418=m
+CONFIG_SENSORS_ADM1021=m
+CONFIG_SENSORS_ADM1025=m
+CONFIG_SENSORS_ADM1026=m
+CONFIG_SENSORS_ADM1029=m
+CONFIG_SENSORS_ADM1031=m
+CONFIG_SENSORS_ADM1177=m
+CONFIG_SENSORS_ADM9240=m
+CONFIG_SENSORS_ADT7X10=m
+CONFIG_SENSORS_ADT7310=m
+CONFIG_SENSORS_ADT7410=m
+CONFIG_SENSORS_ADT7411=m
+CONFIG_SENSORS_ADT7462=m
+CONFIG_SENSORS_ADT7470=m
+CONFIG_SENSORS_ADT7475=m
+CONFIG_SENSORS_AHT10=m
+CONFIG_SENSORS_AS370=m
+CONFIG_SENSORS_ASC7621=m
+CONFIG_SENSORS_ASUS_ROG_RYUJIN=m
+CONFIG_SENSORS_AXI_FAN_CONTROL=m
+CONFIG_SENSORS_ARM_SCMI=m
+CONFIG_SENSORS_ARM_SCMI=m
+CONFIG_SENSORS_ARM_SCPI=m
+CONFIG_SENSORS_ASPEED=m
+CONFIG_SENSORS_ASPEED_G6=m
+CONFIG_SENSORS_ATXP1=m
+CONFIG_SENSORS_CGBC=m
+CONFIG_SENSORS_CHIPCAP2=m
+CONFIG_SENSORS_CORSAIR_CPRO=m
+CONFIG_SENSORS_CORSAIR_PSU=m
+CONFIG_SENSORS_CROS_EC=m
+CONFIG_SENSORS_DRIVETEMP=m
+CONFIG_SENSORS_DS620=m
+CONFIG_SENSORS_DS1621=m
+CONFIG_SENSORS_DA9052_ADC=m
+CONFIG_SENSORS_I5K_AMB=m
+CONFIG_SENSORS_SPARX5=m
+CONFIG_SENSORS_F71805F=m
+CONFIG_SENSORS_F71882FG=m
+CONFIG_SENSORS_F75375S=m
+# CONFIG_SENSORS_GSC is not set
+CONFIG_SENSORS_MC13783_ADC=m
+CONFIG_SENSORS_MC33XS2410=m
+CONFIG_SENSORS_FTSTEUTATES=m
+CONFIG_SENSORS_GIGABYTE_WATERFORCE=m
+CONFIG_SENSORS_GL518SM=m
+CONFIG_SENSORS_GL520SM=m
+CONFIG_SENSORS_GPD=m
+CONFIG_SENSORS_G760A=m
+CONFIG_SENSORS_G762=m
+CONFIG_SENSORS_GPIO_FAN=m
+CONFIG_SENSORS_GXP_FAN_CTRL=m
+CONFIG_SENSORS_HIH6130=m
+CONFIG_SENSORS_HS3001=m
+CONFIG_SENSORS_HTU31=m
+CONFIG_SENSORS_IBMAEM=m
+CONFIG_SENSORS_IBMPEX=m
+CONFIG_SENSORS_IIO_HWMON=m
+CONFIG_SENSORS_IT87=m
+CONFIG_SENSORS_JC42=m
+CONFIG_SENSORS_POWERZ=m
+CONFIG_SENSORS_POWR1220=m
+CONFIG_SENSORS_LINEAGE=m
+CONFIG_SENSORS_LTC2945=m
+CONFIG_SENSORS_LTC2947=m
+CONFIG_SENSORS_LTC2947_I2C=m
+CONFIG_SENSORS_LTC2947_SPI=m
+CONFIG_SENSORS_LTC2990=m
+CONFIG_SENSORS_LTC2991=m
+CONFIG_SENSORS_LTC2992=m
+CONFIG_SENSORS_LTC4151=m
+CONFIG_SENSORS_LTC4215=m
+CONFIG_SENSORS_LTC4222=m
+CONFIG_SENSORS_LTC4245=m
+CONFIG_SENSORS_LTC4260=m
+CONFIG_SENSORS_LTC4261=m
+CONFIG_SENSORS_LTC4282=m
+CONFIG_SENSORS_MAX1111=m
+CONFIG_SENSORS_MAX127=m
+CONFIG_SENSORS_MAX16065=m
+CONFIG_SENSORS_MAX1619=m
+CONFIG_SENSORS_MAX1668=m
+CONFIG_SENSORS_MAX197=m
+CONFIG_SENSORS_MAX31722=m
+CONFIG_SENSORS_MAX31730=m
+CONFIG_SENSORS_MAX31760=m
+CONFIG_MAX31827=m
+CONFIG_SENSORS_MAX31827=m
+CONFIG_SENSORS_MAX6621=m
+CONFIG_SENSORS_MAX6639=m
+CONFIG_SENSORS_MAX6642=m
+CONFIG_SENSORS_MAX6650=m
+CONFIG_SENSORS_MAX6697=m
+CONFIG_SENSORS_MAX31790=m
+CONFIG_SENSORS_MAX77705=m
+CONFIG_SENSORS_MC34VR500=m
+CONFIG_SENSORS_PM6764TR=m
+CONFIG_SENSORS_Q54SJ108A2=m
+CONFIG_SENSORS_STPDDC60=m
+CONFIG_SENSORS_TDA38640=m
+CONFIG_SENSORS_TDA38640_REGULATOR=y
+CONFIG_SENSORS_TPS25990=m
+CONFIG_SENSORS_TPS25990_REGULATOR=y
+CONFIG_SENSORS_SMPRO=m
+CONFIG_SENSORS_MCP3021=m
+CONFIG_SENSORS_MLXREG_FAN=m
+CONFIG_SENSORS_TC654=m
+CONFIG_SENSORS_TPS23861=m
+CONFIG_SENSORS_MENF21BMC_HWMON=m
+CONFIG_SENSORS_MR75203=m
+CONFIG_SENSORS_ADCXX=m
+CONFIG_SENSORS_LM63=m
+CONFIG_SENSORS_LM70=m
+CONFIG_SENSORS_LM73=m
+CONFIG_SENSORS_LM75=m
+CONFIG_SENSORS_LM77=m
+CONFIG_SENSORS_LM78=m
+CONFIG_SENSORS_LM80=m
+CONFIG_SENSORS_LM83=m
+CONFIG_SENSORS_LM85=m
+CONFIG_SENSORS_LM87=m
+CONFIG_SENSORS_LM90=m
+CONFIG_SENSORS_LM92=m
+CONFIG_SENSORS_LM93=m
+CONFIG_SENSORS_LM95234=m
+CONFIG_SENSORS_LM95241=m
+CONFIG_SENSORS_LM95245=m
+CONFIG_SENSORS_PC87360=m
+CONFIG_SENSORS_PC87427=m
+CONFIG_SENSORS_NTC_THERMISTOR=m
+CONFIG_SENSORS_NCT6683=m
+CONFIG_SENSORS_NCT6694=m
+CONFIG_SENSORS_NCT6775=m
+CONFIG_SENSORS_NCT7802=m
+CONFIG_SENSORS_NCT7904=m
+CONFIG_SENSORS_NPCM7XX=m
+CONFIG_SENSORS_NZXT_KRAKEN2=m
+CONFIG_SENSORS_NZXT_KRAKEN3=m
+CONFIG_SENSORS_BPA_RS600=m
+CONFIG_SENSORS_CRPS=m
+CONFIG_SENSORS_FSP_3Y=m
+# CONFIG_SENSORS_OCC_P8_I2C is not set
+CONFIG_SENSORS_PCF8591=m
+CONFIG_PMBUS=m
+CONFIG_SENSORS_PMBUS=m
+CONFIG_SENSORS_ACBEL_FSG032=m
+CONFIG_SENSORS_ACBEL_FSG03=m
+CONFIG_SENSORS_ADM1266=m
+CONFIG_SENSORS_ADM1275=m
+CONFIG_SENSORS_ADP1050=m
+CONFIG_SENSORS_ADP1050_REGULATOR=y
+CONFIG_SENSORS_BEL_PFE=m
+CONFIG_SENSORS_IBM_CFFPS=m
+CONFIG_SENSORS_DPS920AB=m
+CONFIG_SENSORS_INA233=m
+CONFIG_SENSORS_INSPUR_IPSPS=m
+CONFIG_SENSORS_IR35221=m
+CONFIG_SENSORS_IR36021=m
+CONFIG_SENSORS_IR38064=m
+CONFIG_SENSORS_IRPS5401=m
+CONFIG_SENSORS_ISL68137=m
+CONFIG_SENSORS_LM25066=m
+CONFIG_SENSORS_LM25066_REGULATOR=y
+CONFIG_SENSORS_LT3074=m
+CONFIG_SENSORS_LT3074_REGULATOR=m
+CONFIG_SENSORS_LTC2978=m
+CONFIG_SENSORS_LTC2978_REGULATOR=y
+CONFIG_SENSORS_LTC3815=m
+CONFIG_SENSORS_LTC4286=y
+CONFIG_SENSORS_MAX15301=m
+CONFIG_SENSORS_MAX16064=m
+CONFIG_SENSORS_MAX16601=m
+CONFIG_SENSORS_MAX20730=m
+CONFIG_SENSORS_MAX20751=m
+CONFIG_SENSORS_MAX31785=m
+CONFIG_SENSORS_MAX34440=m
+CONFIG_SENSORS_MAX8688=m
+CONFIG_SENSORS_MP2856=m
+CONFIG_SENSORS_MP2869=m
+CONFIG_SENSORS_MP2888=m
+CONFIG_SENSORS_MP2891=m
+CONFIG_SENSORS_MP29502=m
+CONFIG_SENSORS_MP2975=m
+CONFIG_SENSORS_MP2993=m
+CONFIG_SENSORS_MP2975_REGULATOR=y
+CONFIG_SENSORS_PIM4328=m
+CONFIG_SENSORS_PLI1209BC_REGULATOR=y
+CONFIG_SENSORS_PLI1209BC=m
+CONFIG_SENSORS_PXE1610=m
+CONFIG_SENSORS_TPS40422=m
+CONFIG_SENSORS_TPS53679=m
+CONFIG_SENSORS_TPS546D24=m
+CONFIG_SENSORS_UCD9000=m
+CONFIG_SENSORS_UCD9200=m
+CONFIG_SENSORS_XDP710=m
+CONFIG_SENSORS_XDPE122=m
+CONFIG_SENSORS_XDPE122_REGULATOR=y
+CONFIG_SENSORS_ZL6100=m
+CONFIG_SENSORS_PT5161L=m
+CONFIG_SENSORS_PWM_FAN=m
+CONFIG_SENSORS_QNAP_MCU_HWMON=m
+CONFIG_SENSORS_SL28CPLD=m
+# CONFIG_SENSORS_SBTSI is not set
+# CONFIG_AMD_SFH_HID is not set
+CONFIG_SENSORS_SHT15=m
+CONFIG_SENSORS_SHT21=m
+CONFIG_SENSORS_SHT3x=m
+CONFIG_SENSORS_SHT4x=m
+CONFIG_SENSORS_SHTC1=m
+CONFIG_SENSORS_SIS5595=m
+CONFIG_SENSORS_SY7636A=m
+CONFIG_SENSORS_DME1737=m
+CONFIG_SENSORS_EMC1403=m
+CONFIG_SENSORS_EMC2103=m
+CONFIG_SENSORS_EMC2305=m
+CONFIG_SENSORS_EMC6W201=m
+CONFIG_SENSORS_SMSC47M1=m
+CONFIG_SENSORS_SMSC47M192=m
+CONFIG_SENSORS_SMSC47B397=m
+CONFIG_SENSORS_SCH56XX_COMMON=m
+CONFIG_SENSORS_SCH5627=m
+CONFIG_SENSORS_SCH5636=m
+CONFIG_SENSORS_STTS751=m
+CONFIG_SENSORS_SG2042_MCU=m
+CONFIG_SENSORS_SURFACE_FAN=m
+CONFIG_SENSORS_SURFACE_TEMP=m
+CONFIG_SENSORS_SMM665=m
+CONFIG_SENSORS_ADC128D818=m
+CONFIG_SENSORS_ADS7828=m
+CONFIG_SENSORS_ADS7871=m
+CONFIG_SENSORS_AMC6821=m
+CONFIG_SENSORS_INA209=m
+CONFIG_SENSORS_INA2XX=m
+CONFIG_SENSORS_INA3221=m
+CONFIG_SENSORS_SPD5118=m
+CONFIG_SENSORS_SPD5118_DETECT=y
+CONFIG_SENSORS_TC74=m
+CONFIG_SENSORS_THMC50=m
+CONFIG_SENSORS_TMP102=m
+CONFIG_SENSORS_TMP103=m
+CONFIG_SENSORS_TMP108=m
+CONFIG_SENSORS_TMP401=m
+CONFIG_SENSORS_TMP421=m
+CONFIG_SENSORS_TMP464=m
+CONFIG_SENSORS_TMP513=m
+CONFIG_SENSORS_VEXPRESS=m
+CONFIG_SENSORS_VIA686A=m
+CONFIG_SENSORS_VT1211=m
+CONFIG_SENSORS_VT8231=m
+CONFIG_SENSORS_W83773G=m
+CONFIG_SENSORS_W83781D=m
+CONFIG_SENSORS_W83791D=m
+CONFIG_SENSORS_W83792D=m
+CONFIG_SENSORS_W83793=m
+CONFIG_SENSORS_W83795=m
+CONFIG_SENSORS_W83795_FANCTRL=y
+CONFIG_SENSORS_W83L785TS=m
+CONFIG_SENSORS_W83L786NG=m
+CONFIG_SENSORS_W83627HF=m
+CONFIG_SENSORS_W83627EHF=m
+CONFIG_SENSORS_WM831X=m
+CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m
+CONFIG_SENSORS_ISL29018=m
+CONFIG_SENSORS_ISL29028=m
+CONFIG_SENSORS_LM3533=m
+CONFIG_SENSORS_TSL2563=m
+CONFIG_SENSORS_HMC5843=m
+CONFIG_SENSORS_HMC5843_I2C=m
+CONFIG_SENSORS_HMC5843_SPI=m
+CONFIG_SENSORS_RM3100=m
+CONFIG_SENSORS_RM3100_I2C=m
+CONFIG_SENSORS_RM3100_SPI=m
+CONFIG_SI7210=m
+CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m
+CONFIG_SENSORS_MAX6620=m
+CONFIG_SENSORS_SBRMI=m
+CONFIG_SENSORS_NZXT_SMART2=m
+CONFIG_SENSORS_OCC_P8_I2C=m
+CONFIG_SENSORS_OXP=m 
+CONFIG_SENSORS_DELTA_AHE50DC_FAN=m
+CONFIG_SENSORS_IR38064_REGULATOR=y
+CONFIG_SENSORS_MP5023=m
+CONFIG_SENSORS_MP5920=m
+CONFIG_SENSORS_MP5990=m
+CONFIG_SENSORS_MP9941=m
+CONFIG_SENSORS_MPQ7932_REGULATOR=y
+CONFIG_SENSORS_MPQ8785=m
+CONFIG_SENSORS_MPQ7932=m
+CONFIG_SENSORS_INA238=m
+CONFIG_SENSORS_PECI_CPUTEMP=m
+CONFIG_SENSORS_PECI_DIMMTEMP=m
+CONFIG_SENSORS_PT5161L=m
+CONFIG_SENSORS_LAN966X=m
+CONFIG_SENSORS_NCT6775_I2C=m
+CONFIG_SENSORS_XDPE152=m
+CONFIG_SENSORS_LT7182S=m
+CONFIG_SENSORS_LIS3LV02D=m
+CONFIG_SENSORS_TSL2550=m
+CONFIG_SENSORS_BH1770=m  
+CONFIG_SENSORS_APDS990X=m
+CONFIG_SENSORS_LIS3_SPI=m
+CONFIG_SENSORS_LIS3_I2C=m
+CONFIG_D3323AA=m
diff --git a/temporary-workarounds.overrides b/temporary-workarounds.overrides
new file mode 100644
index 0000000..92da9ce
--- /dev/null
+++ b/temporary-workarounds.overrides
@@ -0,0 +1,5 @@
+# This file is for temporary workarounds (e.g. disabling 3rd party
+# modules until they've been ported). Keeping them in a separate
+# file rather than modifying the original configs makes it easier to
+# keep track of what needs to be fixed and to restore the original
+# functionality.
diff --git a/tp_smapi-clang.patch b/tp_smapi-clang.patch
new file mode 100644
index 0000000..3b5aefd
--- /dev/null
+++ b/tp_smapi-clang.patch
@@ -0,0 +1,20 @@
+diff -up linux-6.13/drivers/platform/x86/tp_smapi.c.omv~ linux-6.13/drivers/platform/x86/tp_smapi.c
+--- linux-6.13/drivers/platform/x86/tp_smapi.c.omv~	2025-02-25 23:45:13.343835575 +0100
++++ linux-6.13/drivers/platform/x86/tp_smapi.c	2025-02-25 23:46:19.764377673 +0100
+@@ -178,6 +178,7 @@ static int smapi_request(u32 inEBX, u32
+ 		if (ret)
+ 			return ret;
+ 
++		const u16 sp = smapi_port;
+ 		__asm__ __volatile__(
+ 			"movl  $0x00005380,%%eax\n\t"
+ 			"movl  %6,%%ebx\n\t"
+@@ -201,7 +202,7 @@ static int smapi_request(u32 inEBX, u32
+ 			 "=m"(tmpEDI),
+ 			 "=m"(tmpESI)
+ 			:"m"(inEBX), "m"(inECX), "m"(inEDI), "m"(inESI),
+-			 "m"((u16)smapi_port)
++			 "m"(sp)
+ 			:"%eax", "%ebx", "%ecx", "%edx", "%edi",
+ 			 "%esi");
+ 
diff --git a/trace.fragment b/trace.fragment
new file mode 100644
index 0000000..d1977ef
--- /dev/null
+++ b/trace.fragment
@@ -0,0 +1 @@
+CONFIG_FUNCTION_TRACER=y
diff --git a/v4l2loopback.c b/v4l2loopback.c
new file mode 100644
index 0000000..483b5ad
--- /dev/null
+++ b/v4l2loopback.c
@@ -0,0 +1,3322 @@
+/* -*- c-file-style: "linux" -*- */
+/*
+ * v4l2loopback.c  --  video4linux2 loopback driver
+ *
+ * Copyright (C) 2005-2009 Vasily Levin (vasaka@gmail.com)
+ * Copyright (C) 2010-2023 IOhannes m zmoelnig (zmoelnig@iem.at)
+ * Copyright (C) 2011 Stefan Diewald (stefan.diewald@mytum.de)
+ * Copyright (C) 2012 Anton Novikov (random.plant@gmail.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/mm.h>
+#include <linux/time.h>
+#include <linux/module.h>
+#include <linux/videodev2.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/fs.h>
+#include <linux/capability.h>
+#include <linux/timer.h>
+#include <linux/eventpoll.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-event.h>
+
+#include <linux/miscdevice.h>
+#include "v4l2loopback.h"
+
+#define V4L2LOOPBACK_CTL_ADD_legacy 0x4C80
+#define V4L2LOOPBACK_CTL_REMOVE_legacy 0x4C81
+#define V4L2LOOPBACK_CTL_QUERY_legacy 0x4C82
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0)
+#error This module is not supported on kernels before 4.0.0.
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 3, 0)
+#define strscpy strlcpy
+#endif
+
+#if defined(timer_setup)
+#define HAVE_TIMER_SETUP
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 7, 0)
+#define VFL_TYPE_VIDEO VFL_TYPE_GRABBER
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0)
+#define timer_delete_sync del_timer_sync
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 18, 0)
+#define v4l2_fh_add(fh, filp) v4l2_fh_add(fh)
+#define v4l2_fh_del(fh, filp) v4l2_fh_del(fh)
+#endif
+
+#define V4L2LOOPBACK_VERSION_CODE                                              \
+	KERNEL_VERSION(V4L2LOOPBACK_VERSION_MAJOR, V4L2LOOPBACK_VERSION_MINOR, \
+		       V4L2LOOPBACK_VERSION_BUGFIX)
+
+MODULE_DESCRIPTION("V4L2 loopback video device");
+MODULE_AUTHOR("Vasily Levin, "
+	      "IOhannes m zmoelnig <zmoelnig@iem.at>,"
+	      "Stefan Diewald,"
+	      "Anton Novikov"
+	      "et al.");
+#ifdef SNAPSHOT_VERSION
+MODULE_VERSION(__stringify(SNAPSHOT_VERSION));
+#else
+MODULE_VERSION("" __stringify(V4L2LOOPBACK_VERSION_MAJOR) "." __stringify(
+	V4L2LOOPBACK_VERSION_MINOR) "." __stringify(V4L2LOOPBACK_VERSION_BUGFIX));
+#endif
+MODULE_LICENSE("GPL");
+
+/*
+ * helpers
+ */
+#define dprintk(fmt, args...)                                          \
+	do {                                                           \
+		if (debug > 0) {                                       \
+			printk(KERN_INFO "v4l2-loopback[" __stringify( \
+				       __LINE__) "], pid(%d):  " fmt,  \
+			       task_pid_nr(current), ##args);          \
+		}                                                      \
+	} while (0)
+
+#define MARK()                                                             \
+	do {                                                               \
+		if (debug > 1) {                                           \
+			printk(KERN_INFO "%s:%d[%s], pid(%d)\n", __FILE__, \
+			       __LINE__, __func__, task_pid_nr(current));  \
+		}                                                          \
+	} while (0)
+
+#define dprintkrw(fmt, args...)                                        \
+	do {                                                           \
+		if (debug > 2) {                                       \
+			printk(KERN_INFO "v4l2-loopback[" __stringify( \
+				       __LINE__) "], pid(%d): " fmt,   \
+			       task_pid_nr(current), ##args);          \
+		}                                                      \
+	} while (0)
+
+static inline void v4l2l_get_timestamp(struct v4l2_buffer *b)
+{
+	struct timespec64 ts;
+	ktime_get_ts64(&ts);
+
+	b->timestamp.tv_sec = ts.tv_sec;
+	b->timestamp.tv_usec = (ts.tv_nsec / NSEC_PER_USEC);
+	b->flags |= V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+	b->flags &= ~V4L2_BUF_FLAG_TIMESTAMP_COPY;
+}
+
+#if BITS_PER_LONG == 32
+#include <asm/div64.h> /* do_div() for 64bit division */
+static inline int v4l2l_mod64(const s64 A, const u32 B)
+{
+	u64 a = (u64)A;
+	u32 b = B;
+
+	if (A > 0)
+		return do_div(a, b);
+	a = -A;
+	return -do_div(a, b);
+}
+#else
+static inline int v4l2l_mod64(const s64 A, const u32 B)
+{
+	return A % B;
+}
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0)
+typedef unsigned __poll_t;
+#endif
+
+/* module constants
+ *  can be overridden during he build process using something like
+ *	make KCPPFLAGS="-DMAX_DEVICES=100"
+ */
+
+/* maximum number of v4l2loopback devices that can be created */
+#ifndef MAX_DEVICES
+#define MAX_DEVICES 8
+#endif
+
+/* whether the default is to announce capabilities exclusively or not */
+#ifndef V4L2LOOPBACK_DEFAULT_EXCLUSIVECAPS
+#define V4L2LOOPBACK_DEFAULT_EXCLUSIVECAPS 0
+#endif
+
+/* when a producer is considered to have gone stale */
+#ifndef MAX_TIMEOUT
+#define MAX_TIMEOUT (100 * 1000) /* in msecs */
+#endif
+
+/* max buffers that can be mapped, actually they
+ * are all mapped to max_buffers buffers */
+#ifndef MAX_BUFFERS
+#define MAX_BUFFERS 32
+#endif
+
+/* module parameters */
+static int debug = 0;
+module_param(debug, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(debug, "debugging level (higher values == more verbose)");
+
+#define V4L2LOOPBACK_DEFAULT_MAX_BUFFERS 2
+static int max_buffers = V4L2LOOPBACK_DEFAULT_MAX_BUFFERS;
+module_param(max_buffers, int, S_IRUGO);
+MODULE_PARM_DESC(max_buffers,
+		 "how many buffers should be allocated [DEFAULT: " __stringify(
+			 V4L2LOOPBACK_DEFAULT_MAX_BUFFERS) "]");
+
+/* how many times a device can be opened
+ * the per-module default value can be overridden on a per-device basis using
+ * the /sys/devices interface
+ *
+ * note that max_openers should be at least 2 in order to get a working system:
+ *   one opener for the producer and one opener for the consumer
+ *   however, we leave that to the user
+ */
+#define V4L2LOOPBACK_DEFAULT_MAX_OPENERS 10
+static int max_openers = V4L2LOOPBACK_DEFAULT_MAX_OPENERS;
+module_param(max_openers, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(
+	max_openers,
+	"how many users can open the loopback device [DEFAULT: " __stringify(
+		V4L2LOOPBACK_DEFAULT_MAX_OPENERS) "]");
+
+static int devices = -1;
+module_param(devices, int, 0);
+MODULE_PARM_DESC(devices, "how many devices should be created");
+
+static int video_nr[MAX_DEVICES] = { [0 ...(MAX_DEVICES - 1)] = -1 };
+module_param_array(video_nr, int, NULL, 0444);
+MODULE_PARM_DESC(video_nr,
+		 "video device numbers (-1=auto, 0=/dev/video0, etc.)");
+
+static char *card_label[MAX_DEVICES];
+module_param_array(card_label, charp, NULL, 0000);
+MODULE_PARM_DESC(card_label, "card labels for each device");
+
+static bool exclusive_caps[MAX_DEVICES] = {
+	[0 ...(MAX_DEVICES - 1)] = V4L2LOOPBACK_DEFAULT_EXCLUSIVECAPS
+};
+module_param_array(exclusive_caps, bool, NULL, 0444);
+/* FIXXME: wording */
+MODULE_PARM_DESC(
+	exclusive_caps,
+	"whether to announce OUTPUT/CAPTURE capabilities exclusively or not  [DEFAULT: " __stringify(
+		V4L2LOOPBACK_DEFAULT_EXCLUSIVECAPS) "]");
+
+/* format specifications */
+#define V4L2LOOPBACK_SIZE_MIN_WIDTH 2
+#define V4L2LOOPBACK_SIZE_MIN_HEIGHT 1
+#define V4L2LOOPBACK_SIZE_DEFAULT_MAX_WIDTH 8192
+#define V4L2LOOPBACK_SIZE_DEFAULT_MAX_HEIGHT 8192
+
+#define V4L2LOOPBACK_SIZE_DEFAULT_WIDTH 640
+#define V4L2LOOPBACK_SIZE_DEFAULT_HEIGHT 480
+
+static int max_width = V4L2LOOPBACK_SIZE_DEFAULT_MAX_WIDTH;
+module_param(max_width, int, S_IRUGO);
+MODULE_PARM_DESC(max_width,
+		 "maximum allowed frame width [DEFAULT: " __stringify(
+			 V4L2LOOPBACK_SIZE_DEFAULT_MAX_WIDTH) "]");
+static int max_height = V4L2LOOPBACK_SIZE_DEFAULT_MAX_HEIGHT;
+module_param(max_height, int, S_IRUGO);
+MODULE_PARM_DESC(max_height,
+		 "maximum allowed frame height [DEFAULT: " __stringify(
+			 V4L2LOOPBACK_SIZE_DEFAULT_MAX_HEIGHT) "]");
+
+static DEFINE_IDR(v4l2loopback_index_idr);
+static DEFINE_MUTEX(v4l2loopback_ctl_mutex);
+
+/* frame intervals */
+#define V4L2LOOPBACK_FRAME_INTERVAL_MAX __UINT32_MAX__
+#define V4L2LOOPBACK_FPS_DEFAULT 30
+#define V4L2LOOPBACK_FPS_MAX 1000
+
+/* control IDs */
+#define V4L2LOOPBACK_CID_BASE (V4L2_CID_USER_BASE | 0xf000)
+#define CID_KEEP_FORMAT (V4L2LOOPBACK_CID_BASE + 0)
+#define CID_SUSTAIN_FRAMERATE (V4L2LOOPBACK_CID_BASE + 1)
+#define CID_TIMEOUT (V4L2LOOPBACK_CID_BASE + 2)
+#define CID_TIMEOUT_IMAGE_IO (V4L2LOOPBACK_CID_BASE + 3)
+
+static int v4l2loopback_s_ctrl(struct v4l2_ctrl *ctrl);
+static const struct v4l2_ctrl_ops v4l2loopback_ctrl_ops = {
+	.s_ctrl = v4l2loopback_s_ctrl,
+};
+static const struct v4l2_ctrl_config v4l2loopback_ctrl_keepformat = {
+	// clang-format off
+	.ops	= &v4l2loopback_ctrl_ops,
+	.id	= CID_KEEP_FORMAT,
+	.name	= "keep_format",
+	.type	= V4L2_CTRL_TYPE_BOOLEAN,
+	.min	= 0,
+	.max	= 1,
+	.step	= 1,
+	.def	= 0,
+	// clang-format on
+};
+static const struct v4l2_ctrl_config v4l2loopback_ctrl_sustainframerate = {
+	// clang-format off
+	.ops	= &v4l2loopback_ctrl_ops,
+	.id	= CID_SUSTAIN_FRAMERATE,
+	.name	= "sustain_framerate",
+	.type	= V4L2_CTRL_TYPE_BOOLEAN,
+	.min	= 0,
+	.max	= 1,
+	.step	= 1,
+	.def	= 0,
+	// clang-format on
+};
+static const struct v4l2_ctrl_config v4l2loopback_ctrl_timeout = {
+	// clang-format off
+	.ops	= &v4l2loopback_ctrl_ops,
+	.id	= CID_TIMEOUT,
+	.name	= "timeout",
+	.type	= V4L2_CTRL_TYPE_INTEGER,
+	.min	= 0,
+	.max	= MAX_TIMEOUT,
+	.step	= 1,
+	.def	= 0,
+	// clang-format on
+};
+static const struct v4l2_ctrl_config v4l2loopback_ctrl_timeoutimageio = {
+	// clang-format off
+	.ops	= &v4l2loopback_ctrl_ops,
+	.id	= CID_TIMEOUT_IMAGE_IO,
+	.name	= "timeout_image_io",
+	.type	= V4L2_CTRL_TYPE_BUTTON,
+	.min	= 0,
+	.max	= 0,
+	.step	= 0,
+	.def	= 0,
+	// clang-format on
+};
+
+/* module structures */
+struct v4l2loopback_private {
+	int device_nr;
+};
+
+/* TODO(vasaka) use typenames which are common to kernel, but first find out if
+ * it is needed */
+/* struct keeping state and settings of loopback device */
+
+struct v4l2l_buffer {
+	struct v4l2_buffer buffer;
+	struct list_head list_head;
+	atomic_t use_count;
+};
+
+struct v4l2_loopback_device {
+	struct v4l2_device v4l2_dev;
+	struct v4l2_ctrl_handler ctrl_handler;
+	struct video_device *vdev;
+
+	/* loopback device-specific parameters */
+	char card_label[32];
+	bool announce_all_caps; /* announce both OUTPUT and CAPTURE capabilities
+				 * when true; else announce OUTPUT when no
+				 * writer is streaming, otherwise CAPTURE. */
+	int max_openers; /* how many times can this device be opened */
+	int min_width, max_width;
+	int min_height, max_height;
+
+	/* pixel and stream format */
+	struct v4l2_pix_format pix_format;
+	bool pix_format_has_valid_sizeimage;
+	struct v4l2_captureparm capture_param;
+	unsigned long frame_jiffies;
+
+	/* ctrls */
+	int keep_format; /* CID_KEEP_FORMAT; lock the format, do not free
+			  * on close(), and when `!announce_all_caps` do NOT
+			  * fall back to OUTPUT when no writers attached (clear
+			  * `keep_format` to attach a new writer) */
+	int sustain_framerate; /* CID_SUSTAIN_FRAMERATE; duplicate frames to maintain
+				  (close to) nominal framerate */
+	unsigned long timeout_jiffies; /* CID_TIMEOUT; 0 means disabled */
+	int timeout_image_io; /* CID_TIMEOUT_IMAGE_IO; next opener will
+			       * queue/dequeue the timeout image buffer */
+
+	/* buffers for OUTPUT and CAPTURE */
+	u8 *image; /* pointer to actual buffers data */
+	unsigned long image_size; /* number of bytes alloc'd for all buffers */
+	struct v4l2l_buffer buffers[MAX_BUFFERS]; /* inner driver buffers */
+	u32 buffer_count; /* should not be big, 4 is a good choice */
+	u32 buffer_size; /* number of bytes alloc'd per buffer */
+	u32 used_buffer_count; /* number of buffers allocated to openers */
+	struct list_head outbufs_list; /* FIFO queue for OUTPUT buffers */
+	u32 bufpos2index[MAX_BUFFERS]; /* mapping of `(position % used_buffers)`
+					* to `buffers[index]` */
+	s64 write_position; /* sequence number of last 'displayed' buffer plus
+			     * one */
+
+	/* synchronization between openers */
+	atomic_t open_count;
+	struct mutex image_mutex; /* mutex for allocating image(s) and
+				   * exchanging format tokens */
+	spinlock_t lock; /* lock for the timeout and framerate timers */
+	spinlock_t list_lock; /* lock for the OUTPUT buffer queue */
+	wait_queue_head_t read_event;
+	u32 format_tokens; /* tokens to 'set format' for OUTPUT, CAPTURE, or
+			    * timeout buffers */
+	u32 stream_tokens; /* tokens to 'start' OUTPUT, CAPTURE, or timeout
+			    * stream */
+
+	/* sustain framerate */
+	struct timer_list sustain_timer;
+	unsigned int reread_count;
+
+	/* timeout */
+	u8 *timeout_image; /* copied to outgoing buffers when timeout passes */
+	struct v4l2l_buffer timeout_buffer;
+	u32 timeout_buffer_size; /* number bytes alloc'd for timeout buffer */
+	struct timer_list timeout_timer;
+	int timeout_happened;
+};
+
+enum v4l2l_io_method {
+	V4L2L_IO_NONE = 0,
+	V4L2L_IO_MMAP = 1,
+	V4L2L_IO_FILE = 2,
+	V4L2L_IO_TIMEOUT = 3,
+};
+
+/* struct keeping state and type of opener */
+struct v4l2_loopback_opener {
+	u32 format_token; /* token (if any) for type used in call to S_FMT or
+			   * REQBUFS */
+	u32 stream_token; /* token (if any) for type used in call to STREAMON */
+	u32 buffer_count; /* number of buffers (if any) that opener acquired via
+			   * REQBUFS */
+	s64 read_position; /* sequence number of the next 'captured' frame */
+	unsigned int reread_count;
+	enum v4l2l_io_method io_method;
+
+	struct v4l2_fh fh;
+};
+
+#define fh_to_opener(ptr) container_of((ptr), struct v4l2_loopback_opener, fh)
+
+/* this is heavily inspired by the bttv driver found in the linux kernel */
+struct v4l2l_format {
+	char *name;
+	int fourcc; /* video4linux 2 */
+	int depth; /* bit/pixel */
+	int flags;
+};
+/* set the v4l2l_format.flags to PLANAR for non-packed formats */
+#define FORMAT_FLAGS_PLANAR 0x01
+#define FORMAT_FLAGS_COMPRESSED 0x02
+
+#include "v4l2loopback_formats.h"
+
+#ifndef V4L2_TYPE_IS_CAPTURE
+#define V4L2_TYPE_IS_CAPTURE(type)                \
+	((type) == V4L2_BUF_TYPE_VIDEO_CAPTURE || \
+	 (type) == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+#endif /* V4L2_TYPE_IS_CAPTURE */
+#ifndef V4L2_TYPE_IS_OUTPUT
+#define V4L2_TYPE_IS_OUTPUT(type)                \
+	((type) == V4L2_BUF_TYPE_VIDEO_OUTPUT || \
+	 (type) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+#endif /* V4L2_TYPE_IS_OUTPUT */
+
+/* token values for privilege to set format or start/stop stream */
+#define V4L2L_TOKEN_CAPTURE 0x01
+#define V4L2L_TOKEN_OUTPUT 0x02
+#define V4L2L_TOKEN_TIMEOUT 0x04
+#define V4L2L_TOKEN_MASK \
+	(V4L2L_TOKEN_CAPTURE | V4L2L_TOKEN_OUTPUT | V4L2L_TOKEN_TIMEOUT)
+
+/* helpers for token exchange and token status */
+#define token_from_type(type) \
+	(V4L2_TYPE_IS_CAPTURE(type) ? V4L2L_TOKEN_CAPTURE : V4L2L_TOKEN_OUTPUT)
+#define acquire_token(dev, opener, label, token) \
+	do {                                     \
+		(opener)->label##_token = token; \
+		(dev)->label##_tokens &= ~token; \
+	} while (0)
+#define release_token(dev, opener, label)                         \
+	do {                                                      \
+		(dev)->label##_tokens |= (opener)->label##_token; \
+		(opener)->label##_token = 0;                      \
+	} while (0)
+#define has_output_token(token) (token & V4L2L_TOKEN_OUTPUT)
+#define has_capture_token(token) (token & V4L2L_TOKEN_CAPTURE)
+#define has_no_owners(dev) ((~((dev)->format_tokens) & V4L2L_TOKEN_MASK) == 0)
+#define has_other_owners(opener, dev) \
+	(~((dev)->format_tokens ^ (opener)->format_token) & V4L2L_TOKEN_MASK)
+#define need_timeout_buffer(dev, token) \
+	((dev)->timeout_jiffies > 0 || (token) & V4L2L_TOKEN_TIMEOUT)
+
+static const unsigned int FORMATS = ARRAY_SIZE(formats);
+
+static char *fourcc2str(unsigned int fourcc, char buf[5])
+{
+	buf[0] = (fourcc >> 0) & 0xFF;
+	buf[1] = (fourcc >> 8) & 0xFF;
+	buf[2] = (fourcc >> 16) & 0xFF;
+	buf[3] = (fourcc >> 24) & 0xFF;
+	buf[4] = 0;
+
+	return buf;
+}
+
+static const struct v4l2l_format *format_by_fourcc(int fourcc)
+{
+	unsigned int i;
+	char buf[5];
+
+	for (i = 0; i < FORMATS; i++) {
+		if (formats[i].fourcc == fourcc)
+			return formats + i;
+	}
+
+	dprintk("unsupported format '%4s'\n", fourcc2str(fourcc, buf));
+	return NULL;
+}
+
+static void pix_format_set_size(struct v4l2_pix_format *f,
+				const struct v4l2l_format *fmt,
+				unsigned int width, unsigned int height)
+{
+	f->width = width;
+	f->height = height;
+
+	if (fmt->flags & FORMAT_FLAGS_PLANAR) {
+		f->bytesperline = width; /* Y plane */
+		f->sizeimage = (width * height * fmt->depth) >> 3;
+	} else if (fmt->flags & FORMAT_FLAGS_COMPRESSED) {
+		/* doesn't make sense for compressed formats */
+		f->bytesperline = 0;
+		f->sizeimage = (width * height * fmt->depth) >> 3;
+	} else {
+		f->bytesperline = (width * fmt->depth) >> 3;
+		f->sizeimage = height * f->bytesperline;
+	}
+}
+
+static int v4l2l_fill_format(struct v4l2_format *fmt, const u32 minwidth,
+			     const u32 maxwidth, const u32 minheight,
+			     const u32 maxheight)
+{
+	u32 width = fmt->fmt.pix.width, height = fmt->fmt.pix.height;
+	u32 pixelformat = fmt->fmt.pix.pixelformat;
+	struct v4l2_format fmt0 = *fmt;
+	u32 bytesperline = 0, sizeimage = 0;
+
+	if (!width)
+		width = V4L2LOOPBACK_SIZE_DEFAULT_WIDTH;
+	if (!height)
+		height = V4L2LOOPBACK_SIZE_DEFAULT_HEIGHT;
+	width = clamp_val(width, minwidth, maxwidth);
+	height = clamp_val(height, minheight, maxheight);
+
+	/* sets: width,height,pixelformat,bytesperline,sizeimage */
+	if (!(V4L2_TYPE_IS_MULTIPLANAR(fmt0.type))) {
+		fmt0.fmt.pix.bytesperline = 0;
+		fmt0.fmt.pix.sizeimage = 0;
+	}
+
+	if (0) {
+		;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0)
+	} else if (!v4l2_fill_pixfmt(&fmt0.fmt.pix, pixelformat, width,
+				     height)) {
+		;
+	} else if (!v4l2_fill_pixfmt_mp(&fmt0.fmt.pix_mp, pixelformat, width,
+					height)) {
+		;
+#endif
+	} else {
+		const struct v4l2l_format *format =
+			format_by_fourcc(pixelformat);
+		if (!format)
+			return -EINVAL;
+		pix_format_set_size(&fmt0.fmt.pix, format, width, height);
+		fmt0.fmt.pix.pixelformat = format->fourcc;
+	}
+
+	if (V4L2_TYPE_IS_MULTIPLANAR(fmt0.type)) {
+		*fmt = fmt0;
+
+		if ((fmt->fmt.pix_mp.colorspace == V4L2_COLORSPACE_DEFAULT) ||
+		    (fmt->fmt.pix_mp.colorspace > V4L2_COLORSPACE_DCI_P3))
+			fmt->fmt.pix_mp.colorspace = V4L2_COLORSPACE_SRGB;
+		if (V4L2_FIELD_ANY == fmt->fmt.pix_mp.field)
+			fmt->fmt.pix_mp.field = V4L2_FIELD_NONE;
+	} else {
+		bytesperline = fmt->fmt.pix.bytesperline;
+		sizeimage = fmt->fmt.pix.sizeimage;
+
+		*fmt = fmt0;
+
+		if (!fmt->fmt.pix.bytesperline)
+			fmt->fmt.pix.bytesperline = bytesperline;
+		if (!fmt->fmt.pix.sizeimage)
+			fmt->fmt.pix.sizeimage = sizeimage;
+
+		if ((fmt->fmt.pix.colorspace == V4L2_COLORSPACE_DEFAULT) ||
+		    (fmt->fmt.pix.colorspace > V4L2_COLORSPACE_DCI_P3))
+			fmt->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
+		if (V4L2_FIELD_ANY == fmt->fmt.pix.field)
+			fmt->fmt.pix.field = V4L2_FIELD_NONE;
+	}
+
+	return 0;
+}
+
+/* Checks if v4l2l_fill_format() has set a valid, fixed sizeimage val. */
+static bool v4l2l_pix_format_has_valid_sizeimage(struct v4l2_format *fmt)
+{
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0)
+	const struct v4l2_format_info *info;
+
+	info = v4l2_format_info(fmt->fmt.pix.pixelformat);
+	if (info && info->mem_planes == 1)
+		return true;
+#endif
+
+	return false;
+}
+
+static int pix_format_eq(const struct v4l2_pix_format *ref,
+			 const struct v4l2_pix_format *tgt, int strict)
+{
+	/* check if the two formats are equivalent.
+	 * ANY fields are handled gracefully
+	 */
+#define _pix_format_eq0(x)    \
+	if (ref->x != tgt->x) \
+	result = 0
+#define _pix_format_eq1(x, def)                              \
+	do {                                                 \
+		if ((def != tgt->x) && (ref->x != tgt->x)) { \
+			printk(KERN_INFO #x " failed");      \
+			result = 0;                          \
+		}                                            \
+	} while (0)
+	int result = 1;
+	_pix_format_eq0(width);
+	_pix_format_eq0(height);
+	_pix_format_eq0(pixelformat);
+	if (!strict)
+		return result;
+	_pix_format_eq1(field, V4L2_FIELD_ANY);
+	_pix_format_eq0(bytesperline);
+	_pix_format_eq0(sizeimage);
+	_pix_format_eq1(colorspace, V4L2_COLORSPACE_DEFAULT);
+	return result;
+}
+
+static void set_timeperframe(struct v4l2_loopback_device *dev,
+			     struct v4l2_fract *tpf)
+{
+	if (!tpf->denominator && !tpf->numerator) {
+		tpf->numerator = 1;
+		tpf->denominator = V4L2LOOPBACK_FPS_DEFAULT;
+	} else if (tpf->numerator >
+		   V4L2LOOPBACK_FRAME_INTERVAL_MAX * tpf->denominator) {
+		/* divide-by-zero or greater than maximum interval => min FPS */
+		tpf->numerator = V4L2LOOPBACK_FRAME_INTERVAL_MAX;
+		tpf->denominator = 1;
+	} else if (tpf->numerator * V4L2LOOPBACK_FPS_MAX < tpf->denominator) {
+		/* zero or lower than minimum interval => max FPS */
+		tpf->numerator = 1;
+		tpf->denominator = V4L2LOOPBACK_FPS_MAX;
+	}
+
+	dev->capture_param.timeperframe = *tpf;
+	dev->frame_jiffies =
+		max(1UL, (msecs_to_jiffies(1000) * tpf->numerator) /
+				 tpf->denominator);
+}
+
+static struct v4l2_loopback_device *v4l2loopback_cd2dev(struct device *cd);
+
+/* device attributes */
+/* available via sysfs: /sys/devices/virtual/video4linux/video* */
+
+static ssize_t attr_show_format(struct device *cd,
+				struct device_attribute *attr, char *buf)
+{
+	/* gets the current format as "FOURCC:WxH@f/s", e.g. "YUYV:320x240@1000/30" */
+	struct v4l2_loopback_device *dev = v4l2loopback_cd2dev(cd);
+	const struct v4l2_fract *tpf;
+	char buf4cc[5], buf_fps[32];
+
+	if (!dev || (has_no_owners(dev) && !dev->keep_format))
+		return 0;
+	tpf = &dev->capture_param.timeperframe;
+
+	fourcc2str(dev->pix_format.pixelformat, buf4cc);
+	if (tpf->numerator == 1)
+		snprintf(buf_fps, sizeof(buf_fps), "%u", tpf->denominator);
+	else
+		snprintf(buf_fps, sizeof(buf_fps), "%u/%u", tpf->denominator,
+			 tpf->numerator);
+	return sprintf(buf, "%4s:%ux%u@%s\n", buf4cc, dev->pix_format.width,
+		       dev->pix_format.height, buf_fps);
+}
+
+static ssize_t attr_store_format(struct device *cd,
+				 struct device_attribute *attr, const char *buf,
+				 size_t len)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_cd2dev(cd);
+	int fps_num = 0, fps_den = 1;
+
+	if (!dev)
+		return -ENODEV;
+
+	/* only fps changing is supported */
+	if (sscanf(buf, "@%u/%u", &fps_num, &fps_den) > 0) {
+		struct v4l2_fract f = { .numerator = fps_den,
+					.denominator = fps_num };
+		set_timeperframe(dev, &f);
+		return len;
+	}
+	return -EINVAL;
+}
+
+static DEVICE_ATTR(format, S_IRUGO | S_IWUSR, attr_show_format,
+		   attr_store_format);
+
+static ssize_t attr_show_buffers(struct device *cd,
+				 struct device_attribute *attr, char *buf)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_cd2dev(cd);
+
+	if (!dev)
+		return -ENODEV;
+
+	return sprintf(buf, "%u\n", dev->used_buffer_count);
+}
+
+static DEVICE_ATTR(buffers, S_IRUGO, attr_show_buffers, NULL);
+
+static ssize_t attr_show_maxopeners(struct device *cd,
+				    struct device_attribute *attr, char *buf)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_cd2dev(cd);
+
+	if (!dev)
+		return -ENODEV;
+
+	return sprintf(buf, "%d\n", dev->max_openers);
+}
+
+static ssize_t attr_store_maxopeners(struct device *cd,
+				     struct device_attribute *attr,
+				     const char *buf, size_t len)
+{
+	struct v4l2_loopback_device *dev = NULL;
+	unsigned long curr = 0;
+
+	if (kstrtoul(buf, 0, &curr))
+		return -EINVAL;
+
+	dev = v4l2loopback_cd2dev(cd);
+	if (!dev)
+		return -ENODEV;
+
+	if (dev->max_openers == curr)
+		return len;
+
+	if (curr > __INT_MAX__ || dev->open_count.counter > curr) {
+		/* request to limit to less openers as are currently attached to us */
+		return -EINVAL;
+	}
+
+	dev->max_openers = (int)curr;
+
+	return len;
+}
+
+static DEVICE_ATTR(max_openers, S_IRUGO | S_IWUSR, attr_show_maxopeners,
+		   attr_store_maxopeners);
+
+static ssize_t attr_show_state(struct device *cd, struct device_attribute *attr,
+			       char *buf)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_cd2dev(cd);
+
+	if (!dev)
+		return -ENODEV;
+
+	if (!has_output_token(dev->stream_tokens) || dev->keep_format) {
+		return sprintf(buf, "capture\n");
+	} else
+		return sprintf(buf, "output\n");
+
+	return -EAGAIN;
+}
+
+static DEVICE_ATTR(state, S_IRUGO, attr_show_state, NULL);
+
+static void v4l2loopback_remove_sysfs(struct video_device *vdev)
+{
+#define V4L2_SYSFS_DESTROY(x) device_remove_file(&vdev->dev, &dev_attr_##x)
+
+	if (vdev) {
+		V4L2_SYSFS_DESTROY(format);
+		V4L2_SYSFS_DESTROY(buffers);
+		V4L2_SYSFS_DESTROY(max_openers);
+		V4L2_SYSFS_DESTROY(state);
+		/* ... */
+	}
+}
+
+static void v4l2loopback_create_sysfs(struct video_device *vdev)
+{
+	int res = 0;
+
+#define V4L2_SYSFS_CREATE(x)                                 \
+	res = device_create_file(&vdev->dev, &dev_attr_##x); \
+	if (res < 0)                                         \
+	break
+	if (!vdev)
+		return;
+	do {
+		V4L2_SYSFS_CREATE(format);
+		V4L2_SYSFS_CREATE(buffers);
+		V4L2_SYSFS_CREATE(max_openers);
+		V4L2_SYSFS_CREATE(state);
+		/* ... */
+	} while (0);
+
+	if (res >= 0)
+		return;
+	dev_err(&vdev->dev, "%s error: %d\n", __func__, res);
+}
+
+/* Event APIs */
+
+#define V4L2LOOPBACK_EVENT_BASE (V4L2_EVENT_PRIVATE_START)
+#define V4L2LOOPBACK_EVENT_OFFSET 0x08E00000
+#define V4L2_EVENT_PRI_CLIENT_USAGE \
+	(V4L2LOOPBACK_EVENT_BASE + V4L2LOOPBACK_EVENT_OFFSET + 1)
+
+struct v4l2_event_client_usage {
+	__u32 count;
+};
+
+/* global module data */
+/* find a device based on it's device-number (e.g. '3' for /dev/video3) */
+struct v4l2loopback_lookup_cb_data {
+	int device_nr;
+	struct v4l2_loopback_device *device;
+};
+static int v4l2loopback_lookup_cb(int id, void *ptr, void *data)
+{
+	struct v4l2_loopback_device *device = ptr;
+	struct v4l2loopback_lookup_cb_data *cbdata = data;
+	if (cbdata && device && device->vdev) {
+		if (device->vdev->num == cbdata->device_nr) {
+			cbdata->device = device;
+			cbdata->device_nr = id;
+			return 1;
+		}
+	}
+	return 0;
+}
+static int v4l2loopback_lookup(int device_nr,
+			       struct v4l2_loopback_device **device)
+{
+	struct v4l2loopback_lookup_cb_data data = {
+		.device_nr = device_nr,
+		.device = NULL,
+	};
+	int err = idr_for_each(&v4l2loopback_index_idr, &v4l2loopback_lookup_cb,
+			       &data);
+	if (1 == err) {
+		if (device)
+			*device = data.device;
+		return data.device_nr;
+	}
+	return -ENODEV;
+}
+#define v4l2loopback_get_vdev_nr(vdev) \
+	((struct v4l2loopback_private *)video_get_drvdata(vdev))->device_nr
+static struct v4l2_loopback_device *v4l2loopback_cd2dev(struct device *cd)
+{
+	struct video_device *loopdev = to_video_device(cd);
+	int device_nr = v4l2loopback_get_vdev_nr(loopdev);
+
+	return idr_find(&v4l2loopback_index_idr, device_nr);
+}
+
+static struct v4l2_loopback_device *v4l2loopback_getdevice(struct file *f)
+{
+	struct v4l2loopback_private *ptr = video_drvdata(f);
+	int nr = ptr->device_nr;
+
+	return idr_find(&v4l2loopback_index_idr, nr);
+}
+
+/* forward declarations */
+static void client_usage_queue_event(struct video_device *vdev);
+static bool any_buffers_mapped(struct v4l2_loopback_device *dev);
+static int allocate_buffers(struct v4l2_loopback_device *dev,
+			    struct v4l2_pix_format *pix_format);
+static void init_buffers(struct v4l2_loopback_device *dev, u32 bytes_used,
+			 u32 buffer_size);
+static void free_buffers(struct v4l2_loopback_device *dev);
+static int allocate_timeout_buffer(struct v4l2_loopback_device *dev);
+static void free_timeout_buffer(struct v4l2_loopback_device *dev);
+static void check_timers(struct v4l2_loopback_device *dev);
+static const struct v4l2_file_operations v4l2_loopback_fops;
+static const struct v4l2_ioctl_ops v4l2_loopback_ioctl_ops;
+
+/* V4L2 ioctl caps and params calls */
+/* returns device capabilities
+ * called on VIDIOC_QUERYCAP
+ */
+static int vidioc_querycap(struct file *file, void *fh,
+			   struct v4l2_capability *cap)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	int device_nr = v4l2loopback_get_vdev_nr(dev->vdev);
+	__u32 capabilities = V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
+
+	strscpy(cap->driver, "v4l2 loopback", sizeof(cap->driver));
+	snprintf(cap->card, sizeof(cap->card), "%s", dev->card_label);
+	snprintf(cap->bus_info, sizeof(cap->bus_info),
+		 "platform:v4l2loopback-%03d", device_nr);
+
+	if (dev->announce_all_caps) {
+		capabilities |= V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT;
+	} else {
+		if (opener->io_method == V4L2L_IO_TIMEOUT ||
+		    (has_output_token(dev->stream_tokens) &&
+		     !dev->keep_format)) {
+			capabilities |= V4L2_CAP_VIDEO_OUTPUT;
+		} else
+			capabilities |= V4L2_CAP_VIDEO_CAPTURE;
+	}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)
+	dev->vdev->device_caps =
+#endif /* >=linux-4.7.0 */
+		cap->device_caps = cap->capabilities = capabilities;
+
+	cap->capabilities |= V4L2_CAP_DEVICE_CAPS;
+
+	memset(cap->reserved, 0, sizeof(cap->reserved));
+	return 0;
+}
+
+static int vidioc_enum_framesizes(struct file *file, void *fh,
+				  struct v4l2_frmsizeenum *argp)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+
+	/* there can be only one... */
+	if (argp->index)
+		return -EINVAL;
+
+	if (dev->keep_format || has_other_owners(opener, dev)) {
+		/* only current frame size supported */
+		if (argp->pixel_format != dev->pix_format.pixelformat)
+			return -EINVAL;
+
+		argp->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+
+		argp->discrete.width = dev->pix_format.width;
+		argp->discrete.height = dev->pix_format.height;
+	} else {
+		/* return continuous sizes if pixel format is supported */
+		if (NULL == format_by_fourcc(argp->pixel_format))
+			return -EINVAL;
+
+		if (dev->min_width == dev->max_width &&
+		    dev->min_height == dev->max_height) {
+			argp->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+
+			argp->discrete.width = dev->min_width;
+			argp->discrete.height = dev->min_height;
+		} else {
+			argp->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
+
+			argp->stepwise.min_width = dev->min_width;
+			argp->stepwise.min_height = dev->min_height;
+
+			argp->stepwise.max_width = dev->max_width;
+			argp->stepwise.max_height = dev->max_height;
+
+			argp->stepwise.step_width = 1;
+			argp->stepwise.step_height = 1;
+		}
+	}
+	return 0;
+}
+
+/* Test if the device is currently 'capable' of the buffer (stream) type when
+ * the `exclusive_caps` parameter is set. `keep_format` should lock the format
+ * and prevent free of buffers */
+static int check_buffer_capability(struct v4l2_loopback_device *dev,
+				   struct v4l2_loopback_opener *opener,
+				   enum v4l2_buf_type type)
+{
+	/* short-circuit for (non-compliant) timeout image mode */
+	if (opener->io_method == V4L2L_IO_TIMEOUT)
+		return 0;
+	if (dev->announce_all_caps)
+		return (type == V4L2_BUF_TYPE_VIDEO_CAPTURE ||
+			type == V4L2_BUF_TYPE_VIDEO_OUTPUT) ?
+			       0 :
+			       -EINVAL;
+	/* CAPTURE if opener has a capture format or a writer is streaming;
+	 * else OUTPUT. */
+	switch (type) {
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		if (!(has_capture_token(opener->format_token) ||
+		      !has_output_token(dev->stream_tokens)))
+			return -EINVAL;
+		break;
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+		if (!(has_output_token(opener->format_token) ||
+		      has_output_token(dev->stream_tokens)))
+			return -EINVAL;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+/* returns frameinterval (fps) for the set resolution
+ * called on VIDIOC_ENUM_FRAMEINTERVALS
+ */
+static int vidioc_enum_frameintervals(struct file *file, void *fh,
+				      struct v4l2_frmivalenum *argp)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+
+	/* there can be only one... */
+	if (argp->index)
+		return -EINVAL;
+
+	if (dev->keep_format || has_other_owners(opener, dev)) {
+		/* keep_format also locks the frame rate */
+		if (argp->width != dev->pix_format.width ||
+		    argp->height != dev->pix_format.height ||
+		    argp->pixel_format != dev->pix_format.pixelformat)
+			return -EINVAL;
+
+		argp->type = V4L2_FRMIVAL_TYPE_DISCRETE;
+		argp->discrete = dev->capture_param.timeperframe;
+	} else {
+		if (argp->width < dev->min_width ||
+		    argp->width > dev->max_width ||
+		    argp->height < dev->min_height ||
+		    argp->height > dev->max_height ||
+		    !format_by_fourcc(argp->pixel_format))
+			return -EINVAL;
+
+		argp->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
+		argp->stepwise.min.numerator = 1;
+		argp->stepwise.min.denominator = V4L2LOOPBACK_FPS_MAX;
+		argp->stepwise.max.numerator = V4L2LOOPBACK_FRAME_INTERVAL_MAX;
+		argp->stepwise.max.denominator = 1;
+		argp->stepwise.step.numerator = 1;
+		argp->stepwise.step.denominator = 1;
+	}
+
+	return 0;
+}
+
+/* Enumerate device formats
+ * Returns:
+ * -   EINVAL the index is out of bounds; or if non-zero when format is fixed
+ * -   EFAULT unexpected null pointer */
+static int vidioc_enum_fmt_vid(struct file *file, void *fh,
+			       struct v4l2_fmtdesc *f)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	int fixed = dev->keep_format || has_other_owners(opener, dev);
+	const struct v4l2l_format *fmt;
+
+	if (check_buffer_capability(dev, opener, f->type) < 0)
+		return -EINVAL;
+
+	if (!(f->index < FORMATS))
+		return -EINVAL;
+	/* TODO: Support 6.14 V4L2_FMTDESC_FLAG_ENUM_ALL */
+	if (fixed && f->index)
+		return -EINVAL;
+
+	fmt = fixed ? format_by_fourcc(dev->pix_format.pixelformat) :
+		      &formats[f->index];
+	if (!fmt)
+		return -EFAULT;
+
+	f->flags = 0;
+	if (fmt->flags & FORMAT_FLAGS_COMPRESSED)
+		f->flags |= V4L2_FMT_FLAG_COMPRESSED;
+	snprintf(f->description, sizeof(f->description), fmt->name);
+	f->pixelformat = fmt->fourcc;
+	return 0;
+}
+
+/* Tests (or tries) the format.
+ * Returns:
+ * -   EINVAL if the buffer type or format is not supported
+ */
+static int vidioc_try_fmt_vid(struct file *file, void *fh,
+			      struct v4l2_format *f)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+
+	if (check_buffer_capability(dev, opener, f->type) < 0)
+		return -EINVAL;
+	if (v4l2l_fill_format(f, dev->min_width, dev->max_width,
+			      dev->min_height, dev->max_height) != 0)
+		return -EINVAL;
+	if (dev->keep_format || has_other_owners(opener, dev))
+		/* use existing format - including colorspace info */
+		f->fmt.pix = dev->pix_format;
+
+	return 0;
+}
+
+/* Sets new format. Fills 'f' argument with the requested or existing format.
+ * Side-effect: buffers are allocated for the (returned) format.
+ * Returns:
+ * -   EINVAL if the type is not supported
+ * -   EBUSY if buffers are already allocated
+ * TODO: (vasaka) set subregions of input
+ */
+static int vidioc_s_fmt_vid(struct file *file, void *fh, struct v4l2_format *f)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	u32 token = opener->io_method == V4L2L_IO_TIMEOUT ?
+			    V4L2L_TOKEN_TIMEOUT :
+			    token_from_type(f->type);
+	int changed, result;
+	char buf[5];
+
+	result = vidioc_try_fmt_vid(file, fh, f);
+	if (result < 0)
+		return result;
+
+	if (opener->buffer_count > 0)
+		/* must free buffers before format can be set */
+		return -EBUSY;
+
+	result = mutex_lock_killable(&dev->image_mutex);
+	if (result < 0)
+		return result;
+
+	if (opener->format_token)
+		release_token(dev, opener, format);
+	if (!(dev->format_tokens & token)) {
+		result = -EBUSY;
+		goto exit_s_fmt_unlock;
+	}
+
+	dprintk("S_FMT[%s] %4s:%ux%u size=%u\n",
+		V4L2_TYPE_IS_CAPTURE(f->type) ? "CAPTURE" : "OUTPUT",
+		fourcc2str(f->fmt.pix.pixelformat, buf), f->fmt.pix.width,
+		f->fmt.pix.height, f->fmt.pix.sizeimage);
+	changed = !pix_format_eq(&dev->pix_format, &f->fmt.pix, 0);
+	if (changed || has_no_owners(dev)) {
+		result = allocate_buffers(dev, &f->fmt.pix);
+		if (result < 0)
+			goto exit_s_fmt_unlock;
+	}
+	if ((dev->timeout_image && changed) ||
+	    (!dev->timeout_image && need_timeout_buffer(dev, token))) {
+		result = allocate_timeout_buffer(dev);
+		if (result < 0)
+			goto exit_s_fmt_free;
+	}
+	if (changed) {
+		dev->pix_format = f->fmt.pix;
+		dev->pix_format_has_valid_sizeimage =
+			v4l2l_pix_format_has_valid_sizeimage(f);
+	}
+	acquire_token(dev, opener, format, token);
+	if (opener->io_method == V4L2L_IO_TIMEOUT)
+		dev->timeout_image_io = 0;
+	goto exit_s_fmt_unlock;
+exit_s_fmt_free:
+	free_buffers(dev);
+exit_s_fmt_unlock:
+	mutex_unlock(&dev->image_mutex);
+	return result;
+}
+
+/* ------------------ CAPTURE ----------------------- */
+/* ioctl for VIDIOC_ENUM_FMT, _G_FMT, _S_FMT, and _TRY_FMT when buffer type
+ * is V4L2_BUF_TYPE_VIDEO_CAPTURE */
+
+static int vidioc_enum_fmt_cap(struct file *file, void *fh,
+			       struct v4l2_fmtdesc *f)
+{
+	return vidioc_enum_fmt_vid(file, fh, f);
+}
+
+static int vidioc_g_fmt_cap(struct file *file, void *fh, struct v4l2_format *f)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	if (check_buffer_capability(dev, opener, f->type) < 0)
+		return -EINVAL;
+	f->fmt.pix = dev->pix_format;
+	return 0;
+}
+
+static int vidioc_try_fmt_cap(struct file *file, void *fh,
+			      struct v4l2_format *f)
+{
+	return vidioc_try_fmt_vid(file, fh, f);
+}
+
+static int vidioc_s_fmt_cap(struct file *file, void *fh, struct v4l2_format *f)
+{
+	return vidioc_s_fmt_vid(file, fh, f);
+}
+
+/* ------------------ OUTPUT ----------------------- */
+/* ioctl for VIDIOC_ENUM_FMT, _G_FMT, _S_FMT, and _TRY_FMT when buffer type
+ * is V4L2_BUF_TYPE_VIDEO_OUTPUT */
+
+static int vidioc_enum_fmt_out(struct file *file, void *fh,
+			       struct v4l2_fmtdesc *f)
+{
+	return vidioc_enum_fmt_vid(file, fh, f);
+}
+
+static int vidioc_g_fmt_out(struct file *file, void *fh, struct v4l2_format *f)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	if (check_buffer_capability(dev, opener, f->type) < 0)
+		return -EINVAL;
+	/*
+	 * LATER: this should return the currently valid format
+	 * gstreamer doesn't like it, if this returns -EINVAL, as it
+	 * then concludes that there is _no_ valid format
+	 * CHECK whether this assumption is wrong,
+	 * or whether we have to always provide a valid format
+	 */
+	f->fmt.pix = dev->pix_format;
+	return 0;
+}
+
+static int vidioc_try_fmt_out(struct file *file, void *fh,
+			      struct v4l2_format *f)
+{
+	return vidioc_try_fmt_vid(file, fh, f);
+}
+
+static int vidioc_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f)
+{
+	return vidioc_s_fmt_vid(file, fh, f);
+}
+
+// #define V4L2L_OVERLAY
+#ifdef V4L2L_OVERLAY
+/* ------------------ OVERLAY ----------------------- */
+/* currently unsupported */
+/* GSTreamer's v4l2sink is buggy, as it requires the overlay to work
+ * while it should only require it, if overlay is requested
+ * once the gstreamer element is fixed, remove the overlay dummies
+ */
+#warning OVERLAY dummies
+static int vidioc_g_fmt_overlay(struct file *file, void *priv,
+				struct v4l2_format *fmt)
+{
+	return 0;
+}
+
+static int vidioc_s_fmt_overlay(struct file *file, void *priv,
+				struct v4l2_format *fmt)
+{
+	return 0;
+}
+#endif /* V4L2L_OVERLAY */
+
+/* ------------------ PARAMs ----------------------- */
+
+/* get some data flow parameters, only capability, fps and readbuffers has
+ * effect on this driver
+ * called on VIDIOC_G_PARM
+ */
+static int vidioc_g_parm(struct file *file, void *fh,
+			 struct v4l2_streamparm *parm)
+{
+	/* do not care about type of opener, hope these enums would always be
+	 * compatible */
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	if (check_buffer_capability(dev, opener, parm->type) < 0)
+		return -EINVAL;
+	parm->parm.capture = dev->capture_param;
+	return 0;
+}
+
+/* get some data flow parameters, only capability, fps and readbuffers has
+ * effect on this driver
+ * called on VIDIOC_S_PARM
+ */
+static int vidioc_s_parm(struct file *file, void *fh,
+			 struct v4l2_streamparm *parm)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+
+	dprintk("S_PARM(frame-time=%u/%u)\n",
+		parm->parm.capture.timeperframe.numerator,
+		parm->parm.capture.timeperframe.denominator);
+	if (check_buffer_capability(dev, opener, parm->type) < 0)
+		return -EINVAL;
+
+	switch (parm->type) {
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		set_timeperframe(dev, &parm->parm.capture.timeperframe);
+		break;
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+		set_timeperframe(dev, &parm->parm.output.timeperframe);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	parm->parm.capture = dev->capture_param;
+	return 0;
+}
+
+#ifdef V4L2LOOPBACK_WITH_STD
+/* sets a tv standard, actually we do not need to handle this any special way
+ * added to support effecttv
+ * called on VIDIOC_S_STD
+ */
+static int vidioc_s_std(struct file *file, void *fh, v4l2_std_id *_std)
+{
+	v4l2_std_id req_std = 0, supported_std = 0;
+	const v4l2_std_id all_std = V4L2_STD_ALL, no_std = 0;
+
+	if (_std) {
+		req_std = *_std;
+		*_std = all_std;
+	}
+
+	/* we support everything in V4L2_STD_ALL, but not more... */
+	supported_std = (all_std & req_std);
+	if (no_std == supported_std)
+		return -EINVAL;
+
+	return 0;
+}
+
+/* gets a fake video standard
+ * called on VIDIOC_G_STD
+ */
+static int vidioc_g_std(struct file *file, void *fh, v4l2_std_id *norm)
+{
+	if (norm)
+		*norm = V4L2_STD_ALL;
+	return 0;
+}
+/* gets a fake video standard
+ * called on VIDIOC_QUERYSTD
+ */
+static int vidioc_querystd(struct file *file, void *fh, v4l2_std_id *norm)
+{
+	if (norm)
+		*norm = V4L2_STD_ALL;
+	return 0;
+}
+#endif /* V4L2LOOPBACK_WITH_STD */
+
+static int v4l2loopback_set_ctrl(struct v4l2_loopback_device *dev, u32 id,
+				 s64 val)
+{
+	int result = 0;
+	switch (id) {
+	case CID_KEEP_FORMAT:
+		if (val < 0 || val > 1)
+			return -EINVAL;
+		dev->keep_format = val;
+		result = mutex_lock_killable(&dev->image_mutex);
+		if (result < 0)
+			return result;
+		if (!dev->keep_format) {
+			if (has_no_owners(dev) && !any_buffers_mapped(dev))
+				free_buffers(dev);
+		}
+		mutex_unlock(&dev->image_mutex);
+		break;
+	case CID_SUSTAIN_FRAMERATE:
+		if (val < 0 || val > 1)
+			return -EINVAL;
+		spin_lock_bh(&dev->lock);
+		dev->sustain_framerate = val;
+		check_timers(dev);
+		spin_unlock_bh(&dev->lock);
+		break;
+	case CID_TIMEOUT:
+		if (val < 0 || val > MAX_TIMEOUT)
+			return -EINVAL;
+		if (val > 0) {
+			result = mutex_lock_killable(&dev->image_mutex);
+			if (result < 0)
+				return result;
+			/* on-the-fly allocate if device is owned; else
+			 * allocate occurs on next S_FMT or REQBUFS */
+			if (!has_no_owners(dev))
+				result = allocate_timeout_buffer(dev);
+			mutex_unlock(&dev->image_mutex);
+			if (result < 0) {
+				/* disable timeout as buffer not alloc'd */
+				spin_lock_bh(&dev->lock);
+				dev->timeout_jiffies = 0;
+				spin_unlock_bh(&dev->lock);
+				return result;
+			}
+		}
+		spin_lock_bh(&dev->lock);
+		dev->timeout_jiffies = msecs_to_jiffies(val);
+		check_timers(dev);
+		spin_unlock_bh(&dev->lock);
+		break;
+	case CID_TIMEOUT_IMAGE_IO:
+		dev->timeout_image_io = 1;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int v4l2loopback_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+	struct v4l2_loopback_device *dev = container_of(
+		ctrl->handler, struct v4l2_loopback_device, ctrl_handler);
+	return v4l2loopback_set_ctrl(dev, ctrl->id, ctrl->val);
+}
+
+/* returns set of device outputs, in our case there is only one
+ * called on VIDIOC_ENUMOUTPUT
+ */
+static int vidioc_enum_output(struct file *file, void *fh,
+			      struct v4l2_output *outp)
+{
+	__u32 index = outp->index;
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+
+	if (check_buffer_capability(dev, opener, V4L2_BUF_TYPE_VIDEO_OUTPUT))
+		return -ENOTTY;
+	if (index)
+		return -EINVAL;
+
+	/* clear all data (including the reserved fields) */
+	memset(outp, 0, sizeof(*outp));
+
+	outp->index = index;
+	strscpy(outp->name, "loopback in", sizeof(outp->name));
+	outp->type = V4L2_OUTPUT_TYPE_ANALOG;
+	outp->audioset = 0;
+	outp->modulator = 0;
+#ifdef V4L2LOOPBACK_WITH_STD
+	outp->std = V4L2_STD_ALL;
+#ifdef V4L2_OUT_CAP_STD
+	outp->capabilities |= V4L2_OUT_CAP_STD;
+#endif /*  V4L2_OUT_CAP_STD */
+#endif /* V4L2LOOPBACK_WITH_STD */
+
+	return 0;
+}
+
+/* which output is currently active,
+ * called on VIDIOC_G_OUTPUT
+ */
+static int vidioc_g_output(struct file *file, void *fh, unsigned int *index)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	if (check_buffer_capability(dev, opener, V4L2_BUF_TYPE_VIDEO_OUTPUT))
+		return -ENOTTY;
+	if (index)
+		*index = 0;
+	return 0;
+}
+
+/* set output, can make sense if we have more than one video src,
+ * called on VIDIOC_S_OUTPUT
+ */
+static int vidioc_s_output(struct file *file, void *fh, unsigned int index)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	if (check_buffer_capability(dev, opener, V4L2_BUF_TYPE_VIDEO_OUTPUT))
+		return -ENOTTY;
+	return index == 0 ? index : -EINVAL;
+}
+
+/* returns set of device inputs, in our case there is only one,
+ * but later I may add more
+ * called on VIDIOC_ENUMINPUT
+ */
+static int vidioc_enum_input(struct file *file, void *fh,
+			     struct v4l2_input *inp)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	__u32 index = inp->index;
+
+	if (check_buffer_capability(dev, opener, V4L2_BUF_TYPE_VIDEO_CAPTURE))
+		return -ENOTTY;
+	if (index)
+		return -EINVAL;
+
+	/* clear all data (including the reserved fields) */
+	memset(inp, 0, sizeof(*inp));
+
+	inp->index = index;
+	strscpy(inp->name, "loopback", sizeof(inp->name));
+	inp->type = V4L2_INPUT_TYPE_CAMERA;
+	inp->audioset = 0;
+	inp->tuner = 0;
+	inp->status = 0;
+
+#ifdef V4L2LOOPBACK_WITH_STD
+	inp->std = V4L2_STD_ALL;
+#ifdef V4L2_IN_CAP_STD
+	inp->capabilities |= V4L2_IN_CAP_STD;
+#endif
+#endif /* V4L2LOOPBACK_WITH_STD */
+
+	if (has_output_token(dev->stream_tokens) && !dev->keep_format)
+		/* if no outputs attached; pretend device is powered off */
+		inp->status |= V4L2_IN_ST_NO_SIGNAL;
+
+	return 0;
+}
+
+/* which input is currently active,
+ * called on VIDIOC_G_INPUT
+ */
+static int vidioc_g_input(struct file *file, void *fh, unsigned int *index)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	if (check_buffer_capability(dev, opener, V4L2_BUF_TYPE_VIDEO_CAPTURE))
+		return -ENOTTY; /* NOTE: -EAGAIN might be more informative */
+	if (index)
+		*index = 0;
+	return 0;
+}
+
+/* set input, can make sense if we have more than one video src,
+ * called on VIDIOC_S_INPUT
+ */
+static int vidioc_s_input(struct file *file, void *fh, unsigned int index)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	if (index != 0)
+		return -EINVAL;
+	if (check_buffer_capability(dev, opener, V4L2_BUF_TYPE_VIDEO_CAPTURE))
+		return -ENOTTY; /* NOTE: -EAGAIN might be more informative */
+	return 0;
+}
+
+/* --------------- V4L2 ioctl buffer related calls ----------------- */
+
+#define is_allocated(opener, type, index)                                \
+	(opener->format_token & (opener->io_method == V4L2L_IO_TIMEOUT ? \
+					 V4L2L_TOKEN_TIMEOUT :           \
+					 token_from_type(type)) &&       \
+	 (index) < (opener)->buffer_count)
+#define BUFFER_DEBUG_FMT_STR                                      \
+	"buffer#%u @ %p type=%u bytesused=%u length=%u flags=%x " \
+	"field=%u timestamp= %lld.%06lldsequence=%u\n"
+#define BUFFER_DEBUG_FMT_ARGS(buf)                                         \
+	(buf)->index, (buf), (buf)->type, (buf)->bytesused, (buf)->length, \
+		(buf)->flags, (buf)->field,                                \
+		(long long)(buf)->timestamp.tv_sec,                        \
+		(long long)(buf)->timestamp.tv_usec, (buf)->sequence
+/* Buffer flag helpers */
+#define unset_flags(flags)                      \
+	do {                                    \
+		flags &= ~V4L2_BUF_FLAG_QUEUED; \
+		flags &= ~V4L2_BUF_FLAG_DONE;   \
+	} while (0)
+#define set_queued(flags)                      \
+	do {                                   \
+		flags |= V4L2_BUF_FLAG_QUEUED; \
+		flags &= ~V4L2_BUF_FLAG_DONE;  \
+	} while (0)
+#define set_done(flags)                         \
+	do {                                    \
+		flags &= ~V4L2_BUF_FLAG_QUEUED; \
+		flags |= V4L2_BUF_FLAG_DONE;    \
+	} while (0)
+
+static bool any_buffers_mapped(struct v4l2_loopback_device *dev)
+{
+	u32 index;
+	for (index = 0; index < dev->buffer_count; ++index)
+		if (dev->buffers[index].buffer.flags & V4L2_BUF_FLAG_MAPPED)
+			return true;
+	return false;
+}
+
+static void prepare_buffer_queue(struct v4l2_loopback_device *dev, int count)
+{
+	struct v4l2l_buffer *bufd, *n;
+	u32 pos;
+
+	spin_lock_bh(&dev->list_lock);
+
+	/* ensure sufficient number of buffers in queue */
+	for (pos = 0; pos < count; ++pos) {
+		bufd = &dev->buffers[pos];
+		if (list_empty(&bufd->list_head))
+			list_add_tail(&bufd->list_head, &dev->outbufs_list);
+	}
+	if (list_empty(&dev->outbufs_list))
+		goto exit_prepare_queue_unlock;
+
+	/* remove any excess buffers */
+	list_for_each_entry_safe(bufd, n, &dev->outbufs_list, list_head) {
+		if (bufd->buffer.index >= count)
+			list_del_init(&bufd->list_head);
+	}
+
+	/* buffers are no longer queued; and `write_position` will correspond
+	 * to the first item of `outbufs_list`. */
+	pos = v4l2l_mod64(dev->write_position, count);
+	list_for_each_entry(bufd, &dev->outbufs_list, list_head) {
+		unset_flags(bufd->buffer.flags);
+		dev->bufpos2index[pos % count] = bufd->buffer.index;
+		++pos;
+	}
+exit_prepare_queue_unlock:
+	spin_unlock_bh(&dev->list_lock);
+}
+
+/* forward declaration */
+static int vidioc_streamoff(struct file *file, void *fh,
+			    enum v4l2_buf_type type);
+/* negotiate buffer type
+ * only mmap streaming supported
+ * called on VIDIOC_REQBUFS
+ */
+static int vidioc_reqbufs(struct file *file, void *fh,
+			  struct v4l2_requestbuffers *reqbuf)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	u32 token = opener->io_method == V4L2L_IO_TIMEOUT ?
+			    V4L2L_TOKEN_TIMEOUT :
+			    token_from_type(reqbuf->type);
+	u32 req_count = reqbuf->count;
+	int result = 0;
+
+	dprintk("REQBUFS(memory=%u, req_count=%u) and device-bufs=%u/%u "
+		"[used/max]\n",
+		reqbuf->memory, req_count, dev->used_buffer_count,
+		dev->buffer_count);
+
+	switch (reqbuf->memory) {
+	case V4L2_MEMORY_MMAP:
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)
+		reqbuf->capabilities = 0; /* only guarantee MMAP support */
+#endif
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 16, 0)
+		reqbuf->flags = 0; /* no memory consistency support */
+#endif
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (opener->format_token & ~token)
+		/* different (buffer) type already assigned to descriptor by
+		 * S_FMT or REQBUFS */
+		return -EINVAL;
+
+	MARK();
+	result = mutex_lock_killable(&dev->image_mutex);
+	if (result < 0)
+		return result; /* -EINTR */
+
+	/* CASE queue/dequeue timeout-buffer only: */
+	if (opener->format_token & V4L2L_TOKEN_TIMEOUT) {
+		opener->buffer_count = req_count;
+		if (req_count == 0)
+			release_token(dev, opener, format);
+		goto exit_reqbufs_unlock;
+	}
+
+	MARK();
+	/* CASE count is zero: streamoff, free buffers, release their token */
+	if (req_count == 0) {
+		if (dev->format_tokens & token) {
+			acquire_token(dev, opener, format, token);
+			opener->io_method = V4L2L_IO_MMAP;
+		}
+		result = vidioc_streamoff(file, fh, reqbuf->type);
+		opener->buffer_count = 0;
+		/* undocumented requirement - REQBUFS with count zero should
+		 * ALSO release lock on logical stream */
+		if (opener->format_token)
+			release_token(dev, opener, format);
+		if (has_no_owners(dev))
+			dev->used_buffer_count = 0;
+		goto exit_reqbufs_unlock;
+	}
+
+	/* CASE count non-zero: allocate buffers and acquire token for them */
+	MARK();
+	switch (reqbuf->type) {
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+		if (!(dev->format_tokens & token ||
+		      opener->format_token & token))
+			/* only exclusive ownership for each stream */
+			result = -EBUSY;
+		break;
+	default:
+		result = -EINVAL;
+	}
+	if (result < 0)
+		goto exit_reqbufs_unlock;
+
+	if (has_other_owners(opener, dev) && dev->used_buffer_count > 0) {
+		/* allow 'allocation' of existing number of buffers */
+		req_count = dev->used_buffer_count;
+	} else if (any_buffers_mapped(dev)) {
+		/* do not allow re-allocation if buffers are mapped */
+		result = -EBUSY;
+		goto exit_reqbufs_unlock;
+	}
+
+	MARK();
+	opener->buffer_count = 0;
+
+	if (req_count > dev->buffer_count)
+		req_count = dev->buffer_count;
+
+	if (has_no_owners(dev)) {
+		result = allocate_buffers(dev, &dev->pix_format);
+		if (result < 0)
+			goto exit_reqbufs_unlock;
+	}
+	if (!dev->timeout_image && need_timeout_buffer(dev, token)) {
+		result = allocate_timeout_buffer(dev);
+		if (result < 0)
+			goto exit_reqbufs_unlock;
+	}
+	acquire_token(dev, opener, format, token);
+
+	MARK();
+	switch (opener->io_method) {
+	case V4L2L_IO_TIMEOUT:
+		dev->timeout_image_io = 0;
+		opener->buffer_count = req_count;
+		break;
+	default:
+		opener->io_method = V4L2L_IO_MMAP;
+		prepare_buffer_queue(dev, req_count);
+		dev->used_buffer_count = opener->buffer_count = req_count;
+	}
+exit_reqbufs_unlock:
+	mutex_unlock(&dev->image_mutex);
+	reqbuf->count = opener->buffer_count;
+	return result;
+}
+
+/* returns buffer asked for;
+ * give app as many buffers as it wants, if it less than MAX,
+ * but map them in our inner buffers
+ * called on VIDIOC_QUERYBUF
+ */
+static int vidioc_querybuf(struct file *file, void *fh, struct v4l2_buffer *buf)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	u32 type = buf->type;
+	u32 index = buf->index;
+
+	if ((type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
+	    (type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
+		return -EINVAL;
+	if (!is_allocated(opener, type, index))
+		return -EINVAL;
+
+	if (opener->format_token & V4L2L_TOKEN_TIMEOUT) {
+		*buf = dev->timeout_buffer.buffer;
+		buf->index = index;
+	} else
+		*buf = dev->buffers[index].buffer;
+
+	buf->type = type;
+
+	if (!(buf->flags & (V4L2_BUF_FLAG_DONE | V4L2_BUF_FLAG_QUEUED))) {
+		/* v4l2-compliance requires these to be zero */
+		buf->sequence = 0;
+		buf->timestamp.tv_sec = buf->timestamp.tv_usec = 0;
+	} else if (V4L2_TYPE_IS_CAPTURE(type)) {
+		/* guess flags based on sequence values */
+		if (buf->sequence >= opener->read_position) {
+			set_done(buf->flags);
+		} else if (buf->flags & V4L2_BUF_FLAG_DONE) {
+			set_queued(buf->flags);
+		}
+	}
+	dprintkrw("QUERYBUF(%s, index=%u) -> " BUFFER_DEBUG_FMT_STR,
+		  V4L2_TYPE_IS_CAPTURE(type) ? "CAPTURE" : "OUTPUT", index,
+		  BUFFER_DEBUG_FMT_ARGS(buf));
+	return 0;
+}
+
+static void buffer_written(struct v4l2_loopback_device *dev,
+			   struct v4l2l_buffer *buf)
+{
+	timer_delete_sync(&dev->sustain_timer);
+	timer_delete_sync(&dev->timeout_timer);
+
+	spin_lock_bh(&dev->list_lock);
+	list_move_tail(&buf->list_head, &dev->outbufs_list);
+	spin_unlock_bh(&dev->list_lock);
+
+	spin_lock_bh(&dev->lock);
+	dev->bufpos2index[v4l2l_mod64(dev->write_position,
+				      dev->used_buffer_count)] =
+		buf->buffer.index;
+	++dev->write_position;
+	dev->reread_count = 0;
+
+	check_timers(dev);
+	spin_unlock_bh(&dev->lock);
+}
+
+/* put buffer to queue
+ * called on VIDIOC_QBUF
+ */
+static int vidioc_qbuf(struct file *file, void *fh, struct v4l2_buffer *buf)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	struct v4l2l_buffer *bufd;
+	u32 index = buf->index;
+	u32 type = buf->type;
+
+	if (!is_allocated(opener, type, index))
+		return -EINVAL;
+	bufd = &dev->buffers[index];
+
+	switch (buf->memory) {
+	case V4L2_MEMORY_MMAP:
+		if (!(bufd->buffer.flags & V4L2_BUF_FLAG_MAPPED))
+			dprintkrw("QBUF() unmapped buffer [index=%u]\n", index);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (opener->format_token & V4L2L_TOKEN_TIMEOUT) {
+		set_queued(buf->flags);
+		return 0;
+	}
+
+	switch (type) {
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		dprintkrw("QBUF(CAPTURE, index=%u) -> " BUFFER_DEBUG_FMT_STR,
+			  index, BUFFER_DEBUG_FMT_ARGS(buf));
+		set_queued(buf->flags);
+		break;
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+		dprintkrw("QBUF(OUTPUT, index=%u) -> " BUFFER_DEBUG_FMT_STR,
+			  index, BUFFER_DEBUG_FMT_ARGS(buf));
+		if (!(bufd->buffer.flags & V4L2_BUF_FLAG_TIMESTAMP_COPY) &&
+		    (buf->timestamp.tv_sec == 0 &&
+		     buf->timestamp.tv_usec == 0)) {
+			v4l2l_get_timestamp(&bufd->buffer);
+		} else {
+			bufd->buffer.timestamp = buf->timestamp;
+			bufd->buffer.flags |= V4L2_BUF_FLAG_TIMESTAMP_COPY;
+			bufd->buffer.flags &=
+				~V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+		}
+		if (dev->pix_format_has_valid_sizeimage) {
+			if (buf->bytesused >= dev->pix_format.sizeimage) {
+				bufd->buffer.bytesused =
+					dev->pix_format.sizeimage;
+			} else {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
+				dev_warn_ratelimited(
+					&dev->vdev->dev,
+#else
+				dprintkrw(
+#endif
+					"warning queued output buffer bytesused too small %u < %u\n",
+					buf->bytesused,
+					dev->pix_format.sizeimage);
+				bufd->buffer.bytesused = buf->bytesused;
+			}
+		} else {
+			bufd->buffer.bytesused = buf->bytesused;
+		}
+		bufd->buffer.sequence = dev->write_position;
+		set_queued(bufd->buffer.flags);
+		*buf = bufd->buffer;
+		buffer_written(dev, bufd);
+		set_done(bufd->buffer.flags);
+		wake_up_all(&dev->read_event);
+		break;
+	default:
+		return -EINVAL;
+	}
+	buf->type = type;
+	return 0;
+}
+
+static int can_read(struct v4l2_loopback_device *dev,
+		    struct v4l2_loopback_opener *opener)
+{
+	int ret;
+
+	spin_lock_bh(&dev->lock);
+	check_timers(dev);
+	ret = dev->write_position > opener->read_position ||
+	      dev->reread_count > opener->reread_count || dev->timeout_happened;
+	spin_unlock_bh(&dev->lock);
+	return ret;
+}
+
+static int get_capture_buffer(struct file *file)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(file->private_data);
+	int pos, timeout_happened;
+	u32 index;
+
+	if ((file->f_flags & O_NONBLOCK) &&
+	    (dev->write_position <= opener->read_position &&
+	     dev->reread_count <= opener->reread_count &&
+	     !dev->timeout_happened))
+		return -EAGAIN;
+	wait_event_interruptible(dev->read_event, can_read(dev, opener));
+
+	spin_lock_bh(&dev->lock);
+	if (dev->write_position == opener->read_position) {
+		if (dev->reread_count > opener->reread_count + 2)
+			opener->reread_count = dev->reread_count - 1;
+		++opener->reread_count;
+		pos = v4l2l_mod64(opener->read_position +
+					  dev->used_buffer_count - 1,
+				  dev->used_buffer_count);
+	} else {
+		opener->reread_count = 0;
+		if (dev->write_position >
+		    opener->read_position + dev->used_buffer_count)
+			opener->read_position = dev->write_position - 1;
+		pos = v4l2l_mod64(opener->read_position,
+				  dev->used_buffer_count);
+		++opener->read_position;
+	}
+	timeout_happened = dev->timeout_happened && (dev->timeout_jiffies > 0);
+	dev->timeout_happened = 0;
+	spin_unlock_bh(&dev->lock);
+
+	index = dev->bufpos2index[pos];
+	if (timeout_happened) {
+		if (index >= dev->used_buffer_count) {
+			dprintkrw("get_capture_buffer() read position is at "
+				  "an unallocated buffer [index=%u]\n",
+				  index);
+			return -EFAULT;
+		}
+		/* although allocated on-demand, timeout_image is freed only
+		 * in free_buffers(), so we don't need to worry about it being
+		 * deallocated suddenly */
+		memcpy(dev->image + dev->buffers[index].buffer.m.offset,
+		       dev->timeout_image, dev->buffer_size);
+	}
+	return (int)index;
+}
+
+/* put buffer to dequeue
+ * called on VIDIOC_DQBUF
+ */
+static int vidioc_dqbuf(struct file *file, void *fh, struct v4l2_buffer *buf)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	u32 type = buf->type;
+	int index;
+	struct v4l2l_buffer *bufd;
+
+	if (buf->memory != V4L2_MEMORY_MMAP)
+		return -EINVAL;
+	if (opener->format_token & V4L2L_TOKEN_TIMEOUT) {
+		*buf = dev->timeout_buffer.buffer;
+		buf->type = type;
+		unset_flags(buf->flags);
+		return 0;
+	}
+	if ((opener->buffer_count == 0) ||
+	    !(opener->format_token & token_from_type(type)))
+		return -EINVAL;
+
+	switch (type) {
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		index = get_capture_buffer(file);
+		if (index < 0)
+			return index;
+		*buf = dev->buffers[index].buffer;
+		unset_flags(buf->flags);
+		break;
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+		spin_lock_bh(&dev->list_lock);
+
+		bufd = list_first_entry_or_null(&dev->outbufs_list,
+						struct v4l2l_buffer, list_head);
+		if (bufd)
+			list_move_tail(&bufd->list_head, &dev->outbufs_list);
+
+		spin_unlock_bh(&dev->list_lock);
+		if (!bufd)
+			return -EFAULT;
+		unset_flags(bufd->buffer.flags);
+		*buf = bufd->buffer;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	buf->type = type;
+	dprintkrw("DQBUF(%s, index=%u) -> " BUFFER_DEBUG_FMT_STR,
+		  V4L2_TYPE_IS_CAPTURE(type) ? "CAPTURE" : "OUTPUT", index,
+		  BUFFER_DEBUG_FMT_ARGS(buf));
+	return 0;
+}
+
+/* ------------- STREAMING ------------------- */
+
+/* start streaming
+ * called on VIDIOC_STREAMON
+ */
+static int vidioc_streamon(struct file *file, void *fh, enum v4l2_buf_type type)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	u32 token = token_from_type(type);
+
+	/* short-circuit when using timeout buffer set */
+	if (opener->format_token & V4L2L_TOKEN_TIMEOUT)
+		return 0;
+	/* opener must have claimed (same) buffer set via REQBUFS */
+	if (!opener->buffer_count || !(opener->format_token & token))
+		return -EINVAL;
+
+	switch (type) {
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		if (has_output_token(dev->stream_tokens) && !dev->keep_format)
+			return -EIO;
+		if (dev->stream_tokens & token) {
+			acquire_token(dev, opener, stream, token);
+			client_usage_queue_event(dev->vdev);
+		}
+		return 0;
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+		if (dev->stream_tokens & token)
+			acquire_token(dev, opener, stream, token);
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+/* stop streaming
+ * called on VIDIOC_STREAMOFF
+ */
+static int vidioc_streamoff(struct file *file, void *fh,
+			    enum v4l2_buf_type type)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	u32 token = token_from_type(type);
+
+	/* short-circuit when using timeout buffer set */
+	if (opener->format_token & V4L2L_TOKEN_TIMEOUT)
+		return 0;
+	/* short-circuit when buffer set has no owner */
+	if (dev->format_tokens & token)
+		return 0;
+	/* opener needs a claim to buffer set */
+	if (!opener->format_token)
+		return -EBUSY;
+	if (opener->format_token & ~token)
+		return -EINVAL;
+
+	switch (type) {
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+		if (opener->stream_token & token)
+			release_token(dev, opener, stream);
+		/* reset output queue */
+		if (dev->used_buffer_count > 0)
+			prepare_buffer_queue(dev, dev->used_buffer_count);
+		return 0;
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		if (opener->stream_token & token) {
+			release_token(dev, opener, stream);
+			client_usage_queue_event(dev->vdev);
+		}
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+#ifdef CONFIG_VIDEO_V4L1_COMPAT
+static int vidiocgmbuf(struct file *file, void *fh, struct video_mbuf *p)
+{
+	struct v4l2_loopback_device *dev;
+	MARK();
+
+	dev = v4l2loopback_getdevice(file);
+	p->frames = dev->buffer_count;
+	p->offsets[0] = 0;
+	p->offsets[1] = 0;
+	p->size = dev->buffer_size;
+	return 0;
+}
+#endif
+
+static void client_usage_queue_event(struct video_device *vdev)
+{
+	struct v4l2_event ev;
+	struct v4l2_loopback_device *dev;
+
+	dev = container_of(vdev->v4l2_dev, struct v4l2_loopback_device,
+			   v4l2_dev);
+
+	memset(&ev, 0, sizeof(ev));
+	ev.type = V4L2_EVENT_PRI_CLIENT_USAGE;
+	((struct v4l2_event_client_usage *)&ev.u)->count =
+		!has_capture_token(dev->stream_tokens);
+
+	v4l2_event_queue(vdev, &ev);
+}
+
+static int client_usage_ops_add(struct v4l2_subscribed_event *sev,
+				unsigned elems)
+{
+	if (!(sev->flags & V4L2_EVENT_SUB_FL_SEND_INITIAL))
+		return 0;
+
+	client_usage_queue_event(sev->fh->vdev);
+	return 0;
+}
+
+static void client_usage_ops_replace(struct v4l2_event *old,
+				     const struct v4l2_event *new)
+{
+	*((struct v4l2_event_client_usage *)&old->u) =
+		*((struct v4l2_event_client_usage *)&new->u);
+}
+
+static void client_usage_ops_merge(const struct v4l2_event *old,
+				   struct v4l2_event *new)
+{
+	*((struct v4l2_event_client_usage *)&new->u) =
+		*((struct v4l2_event_client_usage *)&old->u);
+}
+
+const struct v4l2_subscribed_event_ops client_usage_ops = {
+	.add = client_usage_ops_add,
+	.replace = client_usage_ops_replace,
+	.merge = client_usage_ops_merge,
+};
+
+static int vidioc_subscribe_event(struct v4l2_fh *fh,
+				  const struct v4l2_event_subscription *sub)
+{
+	switch (sub->type) {
+	case V4L2_EVENT_CTRL:
+		return v4l2_ctrl_subscribe_event(fh, sub);
+	case V4L2_EVENT_PRI_CLIENT_USAGE:
+		return v4l2_event_subscribe(fh, sub, 0, &client_usage_ops);
+	}
+
+	return -EINVAL;
+}
+
+/* file operations */
+static void vm_open(struct vm_area_struct *vma)
+{
+	struct v4l2l_buffer *buf;
+	MARK();
+
+	buf = vma->vm_private_data;
+	atomic_inc(&buf->use_count);
+	buf->buffer.flags |= V4L2_BUF_FLAG_MAPPED;
+}
+
+static void vm_close(struct vm_area_struct *vma)
+{
+	struct v4l2l_buffer *buf;
+	MARK();
+
+	buf = vma->vm_private_data;
+	if (atomic_dec_and_test(&buf->use_count))
+		buf->buffer.flags &= ~V4L2_BUF_FLAG_MAPPED;
+}
+
+static struct vm_operations_struct vm_ops = {
+	.open = vm_open,
+	.close = vm_close,
+};
+
+static int v4l2_loopback_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	u8 *addr;
+	unsigned long start, size, offset;
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(file->private_data);
+	struct v4l2l_buffer *buffer = NULL;
+	int result = 0;
+	MARK();
+
+	offset = (unsigned long)vma->vm_pgoff << PAGE_SHIFT;
+	start = (unsigned long)vma->vm_start;
+	size = (unsigned long)(vma->vm_end - vma->vm_start); /* always != 0 */
+
+	/* ensure buffer size, count, and allocated image(s) are not altered by
+	 * other file descriptors */
+	result = mutex_lock_killable(&dev->image_mutex);
+	if (result < 0)
+		return result;
+
+	if (size > dev->buffer_size) {
+		dprintk("mmap() attempt to map %lubytes when %ubytes are "
+			"allocated to buffers\n",
+			size, dev->buffer_size);
+		result = -EINVAL;
+		goto exit_mmap_unlock;
+	}
+	if (offset % dev->buffer_size != 0) {
+		dprintk("mmap() offset does not match start of any buffer\n");
+		result = -EINVAL;
+		goto exit_mmap_unlock;
+	}
+	switch (opener->format_token) {
+	case V4L2L_TOKEN_TIMEOUT:
+		if (offset != (unsigned long)dev->buffer_size * MAX_BUFFERS) {
+			dprintk("mmap() incorrect offset for timeout image\n");
+			result = -EINVAL;
+			goto exit_mmap_unlock;
+		}
+		buffer = &dev->timeout_buffer;
+		addr = dev->timeout_image;
+		break;
+	default:
+		if (offset >= dev->image_size) {
+			dprintk("mmap() attempt to map beyond all buffers\n");
+			result = -EINVAL;
+			goto exit_mmap_unlock;
+		}
+		u32 index = offset / dev->buffer_size;
+		buffer = &dev->buffers[index];
+		addr = dev->image + offset;
+		break;
+	}
+
+	while (size > 0) {
+		struct page *page = vmalloc_to_page(addr);
+
+		result = vm_insert_page(vma, start, page);
+		if (result < 0)
+			goto exit_mmap_unlock;
+
+		start += PAGE_SIZE;
+		addr += PAGE_SIZE;
+		size -= PAGE_SIZE;
+	}
+
+	vma->vm_ops = &vm_ops;
+	vma->vm_private_data = buffer;
+
+	vm_open(vma);
+exit_mmap_unlock:
+	mutex_unlock(&dev->image_mutex);
+	return result;
+}
+
+static unsigned int v4l2_loopback_poll(struct file *file,
+				       struct poll_table_struct *pts)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(file->private_data);
+	__poll_t req_events = poll_requested_events(pts);
+	int ret_mask = 0;
+
+	/* call poll_wait in first call, regardless, to ensure that the
+	 * wait-queue is not null */
+	poll_wait(file, &dev->read_event, pts);
+	poll_wait(file, &opener->fh.wait, pts);
+
+	if (req_events & POLLPRI) {
+		if (v4l2_event_pending(&opener->fh)) {
+			ret_mask |= POLLPRI;
+			if (!(req_events & DEFAULT_POLLMASK))
+				return ret_mask;
+		}
+	}
+
+	switch (opener->format_token) {
+	case V4L2L_TOKEN_OUTPUT:
+		if (opener->stream_token != 0 ||
+		    opener->io_method == V4L2L_IO_NONE)
+			ret_mask |= POLLOUT | POLLWRNORM;
+		break;
+	case V4L2L_TOKEN_CAPTURE:
+		if ((opener->io_method == V4L2L_IO_NONE ||
+		     opener->stream_token != 0) &&
+		    can_read(dev, opener))
+			ret_mask |= POLLIN | POLLWRNORM;
+		break;
+	case V4L2L_TOKEN_TIMEOUT:
+		ret_mask |= POLLOUT | POLLWRNORM;
+		break;
+	default:
+		break;
+	}
+
+	return ret_mask;
+}
+
+/* do not want to limit device opens, it can be as many readers as user want,
+ * writers are limited by means of setting writer field */
+static int v4l2_loopback_open(struct file *file)
+{
+	struct v4l2_loopback_device *dev;
+	struct v4l2_loopback_opener *opener;
+
+	dev = v4l2loopback_getdevice(file);
+	if (dev->open_count.counter >= dev->max_openers)
+		return -EBUSY;
+	/* kfree on close */
+	opener = kzalloc(sizeof(*opener), GFP_KERNEL);
+	if (opener == NULL)
+		return -ENOMEM;
+
+	atomic_inc(&dev->open_count);
+	if (dev->timeout_image_io && dev->format_tokens & V4L2L_TOKEN_TIMEOUT)
+		/* will clear timeout_image_io once buffer set acquired */
+		opener->io_method = V4L2L_IO_TIMEOUT;
+
+	v4l2_fh_init(&opener->fh, video_devdata(file));
+	file->private_data = &opener->fh;
+
+	v4l2_fh_add(&opener->fh, file);
+	dprintk("open() -> dev@%p with image@%p\n", dev,
+		dev ? dev->image : NULL);
+	return 0;
+}
+
+static int v4l2_loopback_close(struct file *file)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(file->private_data);
+	int result = 0;
+	dprintk("close() -> dev@%p with image@%p\n", dev,
+		dev ? dev->image : NULL);
+
+	if (opener->format_token) {
+		struct v4l2_requestbuffers reqbuf = {
+			.count = 0, .memory = V4L2_MEMORY_MMAP, .type = 0
+		};
+		switch (opener->format_token) {
+		case V4L2L_TOKEN_CAPTURE:
+			reqbuf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+			break;
+		case V4L2L_TOKEN_OUTPUT:
+		case V4L2L_TOKEN_TIMEOUT:
+			reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
+			break;
+		}
+		if (reqbuf.type)
+			result = vidioc_reqbufs(file, file->private_data,
+						&reqbuf);
+		if (result < 0)
+			dprintk("failed to free buffers REQBUFS(count=0) "
+				" returned %d\n",
+				result);
+		mutex_lock(&dev->image_mutex);
+		release_token(dev, opener, format);
+		mutex_unlock(&dev->image_mutex);
+	}
+
+	if (atomic_dec_and_test(&dev->open_count)) {
+		timer_delete_sync(&dev->sustain_timer);
+		timer_delete_sync(&dev->timeout_timer);
+		if (!dev->keep_format) {
+			mutex_lock(&dev->image_mutex);
+			free_buffers(dev);
+			mutex_unlock(&dev->image_mutex);
+		}
+	}
+
+	v4l2_fh_del(&opener->fh, file);
+	v4l2_fh_exit(&opener->fh);
+
+	kfree(opener);
+	return 0;
+}
+
+static int start_fileio(struct file *file, void *fh, enum v4l2_buf_type type)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_loopback_opener *opener = fh_to_opener(fh);
+	struct v4l2_requestbuffers reqbuf = { .count = dev->buffer_count,
+					      .memory = V4L2_MEMORY_MMAP,
+					      .type = type };
+	int token = token_from_type(type);
+	int result;
+
+	if (opener->format_token & V4L2L_TOKEN_TIMEOUT ||
+	    opener->format_token & ~token)
+		return -EBUSY; /* NOTE: -EBADF might be more informative */
+
+	/* short-circuit if already have stream token */
+	if (opener->stream_token && opener->io_method == V4L2L_IO_FILE)
+		return 0;
+
+	/* otherwise attempt to acquire stream token and assign IO method */
+	if (!(dev->stream_tokens & token) || opener->io_method != V4L2L_IO_NONE)
+		return -EBUSY;
+
+	result = vidioc_reqbufs(file, fh, &reqbuf);
+	if (result < 0)
+		return result;
+	result = vidioc_streamon(file, fh, type);
+	if (result < 0)
+		return result;
+
+	opener->io_method = V4L2L_IO_FILE;
+	return 0;
+}
+
+static ssize_t v4l2_loopback_read(struct file *file, char __user *buf,
+				  size_t count, loff_t *ppos)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_buffer *b;
+	int index, result;
+
+	dprintkrw("read() %zu bytes\n", count);
+	result = start_fileio(file, file->private_data,
+			      V4L2_BUF_TYPE_VIDEO_CAPTURE);
+	if (result < 0)
+		return result;
+
+	index = get_capture_buffer(file);
+	if (index < 0)
+		return index;
+	b = &dev->buffers[index].buffer;
+	if (count > b->bytesused)
+		count = b->bytesused;
+	if (copy_to_user((void *)buf, (void *)(dev->image + b->m.offset),
+			 count)) {
+		printk(KERN_ERR "v4l2-loopback read() failed copy_to_user()\n");
+		return -EFAULT;
+	}
+	return count;
+}
+
+static ssize_t v4l2_loopback_write(struct file *file, const char __user *buf,
+				   size_t count, loff_t *ppos)
+{
+	struct v4l2_loopback_device *dev = v4l2loopback_getdevice(file);
+	struct v4l2_buffer *b;
+	int index, result;
+
+	dprintkrw("write() %zu bytes\n", count);
+	result = start_fileio(file, file->private_data,
+			      V4L2_BUF_TYPE_VIDEO_OUTPUT);
+	if (result < 0)
+		return result;
+
+	if (count > dev->buffer_size)
+		count = dev->buffer_size;
+	index = v4l2l_mod64(dev->write_position, dev->used_buffer_count);
+	b = &dev->buffers[index].buffer;
+
+	if (copy_from_user((void *)(dev->image + b->m.offset), (void *)buf,
+			   count)) {
+		printk(KERN_ERR
+		       "v4l2-loopback write() failed copy_from_user()\n");
+		return -EFAULT;
+	}
+	b->bytesused = count;
+
+	v4l2l_get_timestamp(b);
+	b->sequence = dev->write_position;
+	set_queued(b->flags);
+	buffer_written(dev, &dev->buffers[index]);
+	set_done(b->flags);
+	wake_up_all(&dev->read_event);
+
+	return count;
+}
+
+/* init functions */
+/* frees buffers, if allocated */
+static void free_buffers(struct v4l2_loopback_device *dev)
+{
+	dprintk("free_buffers() with image@%p\n", dev->image);
+	if (!dev->image)
+		return;
+	if (!has_no_owners(dev) || any_buffers_mapped(dev))
+		/* maybe an opener snuck in before image_mutex was acquired */
+		printk(KERN_WARNING
+		       "v4l2-loopback free_buffers() buffers of video device "
+		       "#%u freed while still mapped to userspace\n",
+		       dev->vdev->num);
+	vfree(dev->image);
+	dev->image = NULL;
+	dev->image_size = 0;
+	dev->buffer_size = 0;
+}
+
+static void free_timeout_buffer(struct v4l2_loopback_device *dev)
+{
+	dprintk("free_timeout_buffer() with timeout_image@%p\n",
+		dev->timeout_image);
+	if (!dev->timeout_image)
+		return;
+
+	if ((dev->timeout_jiffies > 0 && !has_no_owners(dev)) ||
+	    dev->timeout_buffer.buffer.flags & V4L2_BUF_FLAG_MAPPED)
+		printk(KERN_WARNING
+		       "v4l2-loopback free_timeout_buffer() timeout image "
+		       "of device #%u freed while still mapped to userspace\n",
+		       dev->vdev->num);
+
+	vfree(dev->timeout_image);
+	dev->timeout_image = NULL;
+	dev->timeout_buffer_size = 0;
+}
+/* allocates buffers if no (other) openers are already using them */
+static int allocate_buffers(struct v4l2_loopback_device *dev,
+			    struct v4l2_pix_format *pix_format)
+{
+	u32 buffer_size = PAGE_ALIGN(pix_format->sizeimage);
+	unsigned long image_size =
+		(unsigned long)buffer_size * (unsigned long)dev->buffer_count;
+	/* vfree on close file operation in case no open handles left */
+
+	if (buffer_size == 0 || dev->buffer_count == 0 ||
+	    buffer_size < pix_format->sizeimage)
+		return -EINVAL;
+
+	if ((__LONG_MAX__ / buffer_size) < dev->buffer_count)
+		return -ENOSPC;
+
+	dprintk("allocate_buffers() size %lubytes = %ubytes x %ubuffers\n",
+		image_size, buffer_size, dev->buffer_count);
+	if (dev->image) {
+		/* check that no buffers are expected in user-space */
+		if (!has_no_owners(dev) || any_buffers_mapped(dev))
+			return -EBUSY;
+		dprintk("allocate_buffers() existing size=%lubytes\n",
+			dev->image_size);
+		/* FIXME: prevent double allocation more intelligently! */
+		if (image_size == dev->image_size) {
+			dprintk("allocate_buffers() keep existing\n");
+			return 0;
+		}
+		free_buffers(dev);
+	}
+
+	/* FIXME: set buffers to 0 */
+	dev->image = vmalloc(image_size);
+	if (dev->image == NULL) {
+		dev->buffer_size = dev->image_size = 0;
+		return -ENOMEM;
+	}
+	init_buffers(dev, pix_format->sizeimage, buffer_size);
+	dev->buffer_size = buffer_size;
+	dev->image_size = image_size;
+	dprintk("allocate_buffers() -> vmalloc'd %lubytes\n", dev->image_size);
+	return 0;
+}
+static int allocate_timeout_buffer(struct v4l2_loopback_device *dev)
+{
+	/* device's `buffer_size` and `buffers` must be initialised in
+	 * allocate_buffers() */
+
+	dprintk("allocate_timeout_buffer() size %ubytes\n", dev->buffer_size);
+	if (dev->buffer_size == 0)
+		return -EINVAL;
+
+	if (dev->timeout_image) {
+		if (dev->timeout_buffer.buffer.flags & V4L2_BUF_FLAG_MAPPED)
+			return -EBUSY;
+		if (dev->buffer_size == dev->timeout_buffer_size)
+			return 0;
+		free_timeout_buffer(dev);
+	}
+
+	dev->timeout_image = vzalloc(dev->buffer_size);
+	if (!dev->timeout_image) {
+		dev->timeout_buffer_size = 0;
+		return -ENOMEM;
+	}
+	dev->timeout_buffer_size = dev->buffer_size;
+	return 0;
+}
+/* init inner buffers, they are capture mode and flags are set as for capture
+ * mode buffers */
+static void init_buffers(struct v4l2_loopback_device *dev, u32 bytes_used,
+			 u32 buffer_size)
+{
+	u32 i;
+
+	for (i = 0; i < dev->buffer_count; ++i) {
+		struct v4l2_buffer *b = &dev->buffers[i].buffer;
+		b->index = i;
+		b->bytesused = bytes_used;
+		b->length = buffer_size;
+		b->field = V4L2_FIELD_NONE;
+		b->flags = 0;
+		b->m.offset = i * buffer_size;
+		b->memory = V4L2_MEMORY_MMAP;
+		b->sequence = 0;
+		b->timestamp.tv_sec = 0;
+		b->timestamp.tv_usec = 0;
+		b->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+
+		v4l2l_get_timestamp(b);
+	}
+	dev->timeout_buffer = dev->buffers[0];
+	dev->timeout_buffer.buffer.m.offset = MAX_BUFFERS * buffer_size;
+}
+
+/* fills and register video device */
+static void init_vdev(struct video_device *vdev, int nr)
+{
+#ifdef V4L2LOOPBACK_WITH_STD
+	vdev->tvnorms = V4L2_STD_ALL;
+#endif /* V4L2LOOPBACK_WITH_STD */
+
+	vdev->vfl_type = VFL_TYPE_VIDEO;
+	vdev->fops = &v4l2_loopback_fops;
+	vdev->ioctl_ops = &v4l2_loopback_ioctl_ops;
+	vdev->release = &video_device_release;
+	vdev->minor = -1;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)
+	vdev->device_caps = V4L2_CAP_DEVICE_CAPS | V4L2_CAP_VIDEO_CAPTURE |
+			    V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_READWRITE |
+			    V4L2_CAP_STREAMING;
+#endif
+
+	if (debug > 1)
+		vdev->dev_debug = V4L2_DEV_DEBUG_IOCTL |
+				  V4L2_DEV_DEBUG_IOCTL_ARG;
+
+	vdev->vfl_dir = VFL_DIR_M2M;
+}
+
+/* init default capture parameters, only fps may be changed in future */
+static void init_capture_param(struct v4l2_captureparm *capture_param)
+{
+	capture_param->capability = V4L2_CAP_TIMEPERFRAME; /* since 2.16 */
+	capture_param->capturemode = 0;
+	capture_param->extendedmode = 0;
+	capture_param->readbuffers = max_buffers;
+	capture_param->timeperframe.numerator = 1;
+	capture_param->timeperframe.denominator = V4L2LOOPBACK_FPS_DEFAULT;
+}
+
+static void check_timers(struct v4l2_loopback_device *dev)
+{
+	if (has_output_token(dev->stream_tokens))
+		return;
+
+	if (dev->timeout_jiffies > 0 && !timer_pending(&dev->timeout_timer))
+		mod_timer(&dev->timeout_timer, jiffies + dev->timeout_jiffies);
+	if (dev->sustain_framerate && !timer_pending(&dev->sustain_timer))
+		mod_timer(&dev->sustain_timer,
+			  jiffies + dev->frame_jiffies * 3 / 2);
+}
+#ifdef HAVE_TIMER_SETUP
+static void sustain_timer_clb(struct timer_list *t)
+{
+	struct v4l2_loopback_device *dev =
+		container_of(t, struct v4l2_loopback_device, sustain_timer);
+#else
+static void sustain_timer_clb(unsigned long nr)
+{
+	struct v4l2_loopback_device *dev =
+		idr_find(&v4l2loopback_index_idr, nr);
+#endif
+	spin_lock(&dev->lock);
+	if (dev->sustain_framerate) {
+		dev->reread_count++;
+		dprintkrw("sustain_timer_clb() write_pos=%lld reread=%u\n",
+			  (long long)dev->write_position, dev->reread_count);
+		if (dev->reread_count == 1)
+			mod_timer(&dev->sustain_timer,
+				  jiffies + max(1UL, dev->frame_jiffies / 2));
+		else
+			mod_timer(&dev->sustain_timer,
+				  jiffies + dev->frame_jiffies);
+		wake_up_all(&dev->read_event);
+	}
+	spin_unlock(&dev->lock);
+}
+#ifdef HAVE_TIMER_SETUP
+static void timeout_timer_clb(struct timer_list *t)
+{
+	struct v4l2_loopback_device *dev =
+		container_of(t, struct v4l2_loopback_device, timeout_timer);
+#else
+static void timeout_timer_clb(unsigned long nr)
+{
+	struct v4l2_loopback_device *dev =
+		idr_find(&v4l2loopback_index_idr, nr);
+#endif
+	spin_lock(&dev->lock);
+	if (dev->timeout_jiffies > 0) {
+		dev->timeout_happened = 1;
+		mod_timer(&dev->timeout_timer, jiffies + dev->timeout_jiffies);
+		wake_up_all(&dev->read_event);
+	}
+	spin_unlock(&dev->lock);
+}
+
+/* init loopback main structure */
+#define DEFAULT_FROM_CONF(confmember, default_condition, default_value)        \
+	((conf) ?                                                              \
+		 ((conf->confmember default_condition) ? (default_value) :     \
+							 (conf->confmember)) : \
+		 default_value)
+
+static int v4l2_loopback_add(struct v4l2_loopback_config *conf, int *ret_nr)
+{
+	struct v4l2_loopback_device *dev;
+	struct v4l2_ctrl_handler *hdl;
+	struct v4l2loopback_private *vdev_priv = NULL;
+	int err;
+
+	u32 _width = V4L2LOOPBACK_SIZE_DEFAULT_WIDTH;
+	u32 _height = V4L2LOOPBACK_SIZE_DEFAULT_HEIGHT;
+
+	u32 _min_width = DEFAULT_FROM_CONF(min_width,
+					   < V4L2LOOPBACK_SIZE_MIN_WIDTH,
+					   V4L2LOOPBACK_SIZE_MIN_WIDTH);
+	u32 _min_height = DEFAULT_FROM_CONF(min_height,
+					    < V4L2LOOPBACK_SIZE_MIN_HEIGHT,
+					    V4L2LOOPBACK_SIZE_MIN_HEIGHT);
+	u32 _max_width = DEFAULT_FROM_CONF(max_width, < _min_width, max_width);
+	u32 _max_height =
+		DEFAULT_FROM_CONF(max_height, < _min_height, max_height);
+	bool _announce_all_caps = (conf && conf->announce_all_caps >= 0) ?
+					  (bool)(conf->announce_all_caps) :
+					  !(V4L2LOOPBACK_DEFAULT_EXCLUSIVECAPS);
+	int _max_buffers = DEFAULT_FROM_CONF(max_buffers, <= 0, max_buffers);
+	int _max_openers = DEFAULT_FROM_CONF(max_openers, <= 0, max_openers);
+	struct v4l2_format _fmt;
+
+	int nr = -1;
+
+	if (conf) {
+		const int output_nr = conf->output_nr;
+#ifdef SPLIT_DEVICES
+		const int capture_nr = conf->capture_nr;
+#else
+		const int capture_nr = output_nr;
+#endif
+		if (capture_nr >= 0 && output_nr == capture_nr) {
+			nr = output_nr;
+		} else if (capture_nr < 0 && output_nr < 0) {
+			nr = -1;
+		} else if (capture_nr < 0) {
+			nr = output_nr;
+		} else if (output_nr < 0) {
+			nr = capture_nr;
+		} else {
+			printk(KERN_ERR
+			       "v4l2-loopback add() split OUTPUT and CAPTURE "
+			       "devices not yet supported.\n");
+			printk(KERN_INFO
+			       "v4l2-loopback add() both devices must have the "
+			       "same number (%d != %d).\n",
+			       output_nr, capture_nr);
+			return -EINVAL;
+		}
+	}
+
+	if (idr_find(&v4l2loopback_index_idr, nr))
+		return -EEXIST;
+
+	/* initialisation of a new device */
+	dprintk("add() creating device #%d\n", nr);
+	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+
+	/* allocate id, if @id >= 0, we're requesting that specific id */
+	if (nr >= 0) {
+		err = idr_alloc(&v4l2loopback_index_idr, dev, nr, nr + 1,
+				GFP_KERNEL);
+		if (err == -ENOSPC)
+			err = -EEXIST;
+	} else {
+		err = idr_alloc(&v4l2loopback_index_idr, dev, 0, 0, GFP_KERNEL);
+	}
+	if (err < 0)
+		goto out_free_dev;
+
+	/* register new device */
+	MARK();
+	nr = err;
+
+	if (conf && conf->card_label[0]) {
+		snprintf(dev->card_label, sizeof(dev->card_label), "%s",
+			 conf->card_label);
+	} else {
+		snprintf(dev->card_label, sizeof(dev->card_label),
+			 "Dummy video device (0x%04X)", nr);
+	}
+	snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name),
+		 "v4l2loopback-%03d", nr);
+
+	err = v4l2_device_register(NULL, &dev->v4l2_dev);
+	if (err)
+		goto out_free_idr;
+
+	/* initialise the _video_ device */
+	MARK();
+	err = -ENOMEM;
+	dev->vdev = video_device_alloc();
+	if (dev->vdev == NULL)
+		goto out_unregister;
+
+	vdev_priv = kzalloc(sizeof(struct v4l2loopback_private), GFP_KERNEL);
+	if (vdev_priv == NULL)
+		goto out_unregister;
+
+	video_set_drvdata(dev->vdev, vdev_priv);
+	if (video_get_drvdata(dev->vdev) == NULL)
+		goto out_unregister;
+
+	snprintf(dev->vdev->name, sizeof(dev->vdev->name), "%s",
+		 dev->card_label);
+	vdev_priv->device_nr = nr;
+	init_vdev(dev->vdev, nr);
+	dev->vdev->v4l2_dev = &dev->v4l2_dev;
+
+	/* initialise v4l2-loopback specific parameters */
+	MARK();
+	dev->announce_all_caps = _announce_all_caps;
+	dev->min_width = _min_width;
+	dev->min_height = _min_height;
+	dev->max_width = _max_width;
+	dev->max_height = _max_height;
+	dev->max_openers = _max_openers;
+
+	/* set (initial) pixel and stream format */
+	_width = clamp_val(_width, _min_width, _max_width);
+	_height = clamp_val(_height, _min_height, _max_height);
+	_fmt = (struct v4l2_format){
+		.type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
+		.fmt.pix = { .width = _width,
+			     .height = _height,
+			     .pixelformat = formats[0].fourcc,
+			     .colorspace = V4L2_COLORSPACE_DEFAULT,
+			     .field = V4L2_FIELD_NONE }
+	};
+
+	err = v4l2l_fill_format(&_fmt, _min_width, _max_width, _min_height,
+				_max_height);
+	if (err)
+		/* highly unexpected failure to assign default format */
+		goto out_unregister;
+	dev->pix_format = _fmt.fmt.pix;
+	init_capture_param(&dev->capture_param);
+	set_timeperframe(dev, &dev->capture_param.timeperframe);
+
+	/* ctrls parameters */
+	dev->keep_format = 0;
+	dev->sustain_framerate = 0;
+	dev->timeout_jiffies = 0;
+	dev->timeout_image_io = 0;
+
+	/* initialise OUTPUT and CAPTURE buffer values */
+	dev->image = NULL;
+	dev->image_size = 0;
+	dev->buffer_count = _max_buffers;
+	dev->buffer_size = 0;
+	dev->used_buffer_count = 0;
+	INIT_LIST_HEAD(&dev->outbufs_list);
+	do {
+		u32 index;
+		for (index = 0; index < dev->buffer_count; ++index)
+			INIT_LIST_HEAD(&dev->buffers[index].list_head);
+
+	} while (0);
+	memset(dev->bufpos2index, 0, sizeof(dev->bufpos2index));
+	dev->write_position = 0;
+
+	/* initialise synchronisation data */
+	atomic_set(&dev->open_count, 0);
+	mutex_init(&dev->image_mutex);
+	spin_lock_init(&dev->lock);
+	spin_lock_init(&dev->list_lock);
+	init_waitqueue_head(&dev->read_event);
+	dev->format_tokens = V4L2L_TOKEN_MASK;
+	dev->stream_tokens = V4L2L_TOKEN_MASK;
+
+	/* initialise sustain frame rate and timeout parameters, and timers */
+	dev->reread_count = 0;
+	dev->timeout_image = NULL;
+	dev->timeout_happened = 0;
+#ifdef HAVE_TIMER_SETUP
+	timer_setup(&dev->sustain_timer, sustain_timer_clb, 0);
+	timer_setup(&dev->timeout_timer, timeout_timer_clb, 0);
+#else
+	setup_timer(&dev->sustain_timer, sustain_timer_clb, nr);
+	setup_timer(&dev->timeout_timer, timeout_timer_clb, nr);
+#endif
+
+	/* initialise the control handler and add controls */
+	MARK();
+	hdl = &dev->ctrl_handler;
+	err = v4l2_ctrl_handler_init(hdl, 4);
+	if (err)
+		goto out_unregister;
+	v4l2_ctrl_new_custom(hdl, &v4l2loopback_ctrl_keepformat, NULL);
+	v4l2_ctrl_new_custom(hdl, &v4l2loopback_ctrl_sustainframerate, NULL);
+	v4l2_ctrl_new_custom(hdl, &v4l2loopback_ctrl_timeout, NULL);
+	v4l2_ctrl_new_custom(hdl, &v4l2loopback_ctrl_timeoutimageio, NULL);
+	if (hdl->error) {
+		err = hdl->error;
+		goto out_free_handler;
+	}
+	dev->v4l2_dev.ctrl_handler = hdl;
+
+	err = v4l2_ctrl_handler_setup(hdl);
+	if (err)
+		goto out_free_handler;
+
+	/* register the device (creates /dev/video*) */
+	MARK();
+	if (video_register_device(dev->vdev, VFL_TYPE_VIDEO, nr) < 0) {
+		printk(KERN_ERR
+		       "v4l2-loopback add() failed video_register_device()\n");
+		err = -EFAULT;
+		goto out_free_device;
+	}
+	v4l2loopback_create_sysfs(dev->vdev);
+	/* NOTE: ambivalent if sysfs entries fail */
+
+	if (ret_nr)
+		*ret_nr = dev->vdev->num;
+	return 0;
+
+out_free_device:
+out_free_handler:
+	v4l2_ctrl_handler_free(&dev->ctrl_handler);
+out_unregister:
+	if (dev->vdev)
+		video_set_drvdata(dev->vdev, NULL);
+	video_device_release(dev->vdev);
+	if (vdev_priv != NULL)
+		kfree(vdev_priv);
+	v4l2_device_unregister(&dev->v4l2_dev);
+out_free_idr:
+	idr_remove(&v4l2loopback_index_idr, nr);
+out_free_dev:
+	kfree(dev);
+	return err;
+}
+
+static void v4l2_loopback_remove(struct v4l2_loopback_device *dev)
+{
+	int device_nr = v4l2loopback_get_vdev_nr(dev->vdev);
+	mutex_lock(&dev->image_mutex);
+	free_buffers(dev);
+	free_timeout_buffer(dev);
+	mutex_unlock(&dev->image_mutex);
+	v4l2loopback_remove_sysfs(dev->vdev);
+	v4l2_ctrl_handler_free(&dev->ctrl_handler);
+	kfree(video_get_drvdata(dev->vdev));
+	video_unregister_device(dev->vdev);
+	v4l2_device_unregister(&dev->v4l2_dev);
+	idr_remove(&v4l2loopback_index_idr, device_nr);
+	kfree(dev);
+}
+
+static long v4l2loopback_control_ioctl(struct file *file, unsigned int cmd,
+				       unsigned long parm)
+{
+	struct v4l2_loopback_device *dev;
+	struct v4l2_loopback_config conf;
+	struct v4l2_loopback_config *confptr = &conf;
+	int device_nr, capture_nr, output_nr;
+	int ret;
+	const __u32 version = V4L2LOOPBACK_VERSION_CODE;
+
+	ret = mutex_lock_killable(&v4l2loopback_ctl_mutex);
+	if (ret)
+		return ret;
+
+	ret = -EINVAL;
+	switch (cmd) {
+	default:
+		ret = -ENOSYS;
+		break;
+		/* add a v4l2loopback device (pair), based on the user-provided specs */
+	case V4L2LOOPBACK_CTL_ADD:
+	case V4L2LOOPBACK_CTL_ADD_legacy:
+		if (parm) {
+			if ((ret = copy_from_user(&conf, (void *)parm,
+						  sizeof(conf))) < 0)
+				break;
+		} else
+			confptr = NULL;
+		ret = v4l2_loopback_add(confptr, &device_nr);
+		if (ret >= 0)
+			ret = device_nr;
+		break;
+		/* remove a v4l2loopback device (both capture and output) */
+	case V4L2LOOPBACK_CTL_REMOVE:
+	case V4L2LOOPBACK_CTL_REMOVE_legacy:
+		ret = v4l2loopback_lookup((__u32)parm, &dev);
+		if (ret >= 0 && dev) {
+			ret = -EBUSY;
+			if (dev->open_count.counter > 0)
+				break;
+			v4l2_loopback_remove(dev);
+			ret = 0;
+		};
+		break;
+		/* get information for a loopback device.
+		 * this is mostly about limits (which cannot be queried directly with  VIDIOC_G_FMT and friends
+		 */
+	case V4L2LOOPBACK_CTL_QUERY:
+	case V4L2LOOPBACK_CTL_QUERY_legacy:
+		if (!parm)
+			break;
+		if ((ret = copy_from_user(&conf, (void *)parm, sizeof(conf))) <
+		    0)
+			break;
+		capture_nr = output_nr = conf.output_nr;
+#ifdef SPLIT_DEVICES
+		capture_nr = conf.capture_nr;
+#endif
+		device_nr = (output_nr < 0) ? capture_nr : output_nr;
+		MARK();
+		/* get the device from either capture_nr or output_nr (whatever is valid) */
+		if ((ret = v4l2loopback_lookup(device_nr, &dev)) < 0)
+			break;
+		MARK();
+		/* if we got the device from output_nr and there is a valid capture_nr,
+		 * make sure that both refer to the same device (or bail out)
+		 */
+		if ((device_nr != capture_nr) && (capture_nr >= 0) &&
+		    ((ret = v4l2loopback_lookup(capture_nr, 0)) < 0))
+			break;
+		MARK();
+		/* if otoh, we got the device from capture_nr and there is a valid output_nr,
+		 * make sure that both refer to the same device (or bail out)
+		 */
+		if ((device_nr != output_nr) && (output_nr >= 0) &&
+		    ((ret = v4l2loopback_lookup(output_nr, 0)) < 0))
+			break;
+
+		/* v4l2_loopback_config identified a single device, so fetch the data */
+		snprintf(conf.card_label, sizeof(conf.card_label), "%s",
+			 dev->card_label);
+
+		conf.output_nr = dev->vdev->num;
+#ifdef SPLIT_DEVICES
+		conf.capture_nr = dev->vdev->num;
+#endif
+		conf.min_width = dev->min_width;
+		conf.min_height = dev->min_height;
+		conf.max_width = dev->max_width;
+		conf.max_height = dev->max_height;
+		conf.announce_all_caps = dev->announce_all_caps;
+		conf.max_buffers = dev->buffer_count;
+		conf.max_openers = dev->max_openers;
+		conf.debug = debug;
+		MARK();
+		if (copy_to_user((void *)parm, &conf, sizeof(conf))) {
+			ret = -EFAULT;
+			break;
+		}
+		ret = 0;
+		break;
+	case V4L2LOOPBACK_CTL_VERSION:
+		if (!parm)
+			break;
+		if (copy_to_user((void *)parm, &version, sizeof(version))) {
+			ret = -EFAULT;
+			break;
+		}
+		ret = 0;
+		break;
+	}
+
+	mutex_unlock(&v4l2loopback_ctl_mutex);
+	MARK();
+	return ret;
+}
+
+/* LINUX KERNEL */
+
+static const struct file_operations v4l2loopback_ctl_fops = {
+	// clang-format off
+	.owner		= THIS_MODULE,
+	.open		= nonseekable_open,
+	.unlocked_ioctl	= v4l2loopback_control_ioctl,
+	.compat_ioctl	= v4l2loopback_control_ioctl,
+	.llseek		= noop_llseek,
+	// clang-format on
+};
+
+static struct miscdevice v4l2loopback_misc = {
+	// clang-format off
+	.minor		= MISC_DYNAMIC_MINOR,
+	.name		= "v4l2loopback",
+	.fops		= &v4l2loopback_ctl_fops,
+	// clang-format on
+};
+
+static const struct v4l2_file_operations v4l2_loopback_fops = {
+	// clang-format off
+	.owner		= THIS_MODULE,
+	.open		= v4l2_loopback_open,
+	.release	= v4l2_loopback_close,
+	.read		= v4l2_loopback_read,
+	.write		= v4l2_loopback_write,
+	.poll		= v4l2_loopback_poll,
+	.mmap		= v4l2_loopback_mmap,
+	.unlocked_ioctl	= video_ioctl2,
+	// clang-format on
+};
+
+static const struct v4l2_ioctl_ops v4l2_loopback_ioctl_ops = {
+	// clang-format off
+	.vidioc_querycap		= &vidioc_querycap,
+	.vidioc_enum_framesizes		= &vidioc_enum_framesizes,
+	.vidioc_enum_frameintervals	= &vidioc_enum_frameintervals,
+
+	.vidioc_enum_output		= &vidioc_enum_output,
+	.vidioc_g_output		= &vidioc_g_output,
+	.vidioc_s_output		= &vidioc_s_output,
+
+	.vidioc_enum_input		= &vidioc_enum_input,
+	.vidioc_g_input			= &vidioc_g_input,
+	.vidioc_s_input			= &vidioc_s_input,
+
+	.vidioc_enum_fmt_vid_cap	= &vidioc_enum_fmt_cap,
+	.vidioc_g_fmt_vid_cap		= &vidioc_g_fmt_cap,
+	.vidioc_s_fmt_vid_cap		= &vidioc_s_fmt_cap,
+	.vidioc_try_fmt_vid_cap		= &vidioc_try_fmt_cap,
+
+	.vidioc_enum_fmt_vid_out	= &vidioc_enum_fmt_out,
+	.vidioc_s_fmt_vid_out		= &vidioc_s_fmt_out,
+	.vidioc_g_fmt_vid_out		= &vidioc_g_fmt_out,
+	.vidioc_try_fmt_vid_out		= &vidioc_try_fmt_out,
+
+#ifdef V4L2L_OVERLAY
+	.vidioc_s_fmt_vid_overlay	= &vidioc_s_fmt_overlay,
+	.vidioc_g_fmt_vid_overlay	= &vidioc_g_fmt_overlay,
+#endif
+
+#ifdef V4L2LOOPBACK_WITH_STD
+	.vidioc_s_std			= &vidioc_s_std,
+	.vidioc_g_std			= &vidioc_g_std,
+	.vidioc_querystd		= &vidioc_querystd,
+#endif /* V4L2LOOPBACK_WITH_STD */
+
+	.vidioc_g_parm			= &vidioc_g_parm,
+	.vidioc_s_parm			= &vidioc_s_parm,
+
+	.vidioc_reqbufs			= &vidioc_reqbufs,
+	.vidioc_querybuf		= &vidioc_querybuf,
+	.vidioc_qbuf			= &vidioc_qbuf,
+	.vidioc_dqbuf			= &vidioc_dqbuf,
+
+	.vidioc_streamon		= &vidioc_streamon,
+	.vidioc_streamoff		= &vidioc_streamoff,
+
+#ifdef CONFIG_VIDEO_V4L1_COMPAT
+	.vidiocgmbuf			= &vidiocgmbuf,
+#endif
+
+	.vidioc_subscribe_event		= &vidioc_subscribe_event,
+	.vidioc_unsubscribe_event	= &v4l2_event_unsubscribe,
+	// clang-format on
+};
+
+static int free_device_cb(int id, void *ptr, void *data)
+{
+	struct v4l2_loopback_device *dev = ptr;
+	v4l2_loopback_remove(dev);
+	return 0;
+}
+static void free_devices(void)
+{
+	idr_for_each(&v4l2loopback_index_idr, &free_device_cb, NULL);
+	idr_destroy(&v4l2loopback_index_idr);
+}
+
+static int __init v4l2loopback_init_module(void)
+{
+	const u32 min_width = V4L2LOOPBACK_SIZE_MIN_WIDTH;
+	const u32 min_height = V4L2LOOPBACK_SIZE_MIN_HEIGHT;
+	int err;
+	int i;
+	MARK();
+
+	err = misc_register(&v4l2loopback_misc);
+	if (err < 0)
+		return err;
+
+	if (devices < 0) {
+		devices = 1;
+
+		/* try guessing the devices from the "video_nr" parameter */
+		for (i = MAX_DEVICES - 1; i >= 0; i--) {
+			if (video_nr[i] >= 0) {
+				devices = i + 1;
+				break;
+			}
+		}
+	}
+
+	if (devices > MAX_DEVICES) {
+		devices = MAX_DEVICES;
+		printk(KERN_INFO
+		       "v4l2-loopback init() number of initial devices is "
+		       "limited to: %d\n",
+		       MAX_DEVICES);
+	}
+
+	if (max_buffers > MAX_BUFFERS) {
+		max_buffers = MAX_BUFFERS;
+		printk(KERN_INFO
+		       "v4l2-loopback init() number of buffers is limited "
+		       "to: %d\n",
+		       MAX_BUFFERS);
+	}
+
+	if (max_openers < 0) {
+		printk(KERN_INFO
+		       "v4l2-loopback init() allowing %d openers rather "
+		       "than %d\n",
+		       2, max_openers);
+		max_openers = 2;
+	}
+
+	if (max_width < min_width) {
+		max_width = V4L2LOOPBACK_SIZE_DEFAULT_MAX_WIDTH;
+		printk(KERN_INFO "v4l2-loopback init() using max_width %d\n",
+		       max_width);
+	}
+	if (max_height < min_height) {
+		max_height = V4L2LOOPBACK_SIZE_DEFAULT_MAX_HEIGHT;
+		printk(KERN_INFO "v4l2-loopback init() using max_height %d\n",
+		       max_height);
+	}
+
+	for (i = 0; i < devices; i++) {
+		struct v4l2_loopback_config cfg = {
+			// clang-format off
+			.output_nr		= video_nr[i],
+#ifdef SPLIT_DEVICES
+			.capture_nr		= video_nr[i],
+#endif
+			.min_width		= min_width,
+			.min_height		= min_height,
+			.max_width		= max_width,
+			.max_height		= max_height,
+			.announce_all_caps	= (!exclusive_caps[i]),
+			.max_buffers		= max_buffers,
+			.max_openers		= max_openers,
+			.debug			= debug,
+			// clang-format on
+		};
+		cfg.card_label[0] = 0;
+		if (card_label[i])
+			snprintf(cfg.card_label, sizeof(cfg.card_label), "%s",
+				 card_label[i]);
+		err = v4l2_loopback_add(&cfg, 0);
+		if (err) {
+			free_devices();
+			goto error;
+		}
+	}
+
+	dprintk("module installed\n");
+
+	printk(KERN_INFO "v4l2-loopback driver version %d.%d.%d%s loaded\n",
+	       // clang-format off
+	       (V4L2LOOPBACK_VERSION_CODE >> 16) & 0xff,
+	       (V4L2LOOPBACK_VERSION_CODE >>  8) & 0xff,
+	       (V4L2LOOPBACK_VERSION_CODE      ) & 0xff,
+#ifdef SNAPSHOT_VERSION
+	       " (" __stringify(SNAPSHOT_VERSION) ")"
+#else
+	       ""
+#endif
+	       );
+	// clang-format on
+
+	return 0;
+error:
+	misc_deregister(&v4l2loopback_misc);
+	return err;
+}
+
+static void v4l2loopback_cleanup_module(void)
+{
+	MARK();
+	/* unregister the device -> it deletes /dev/video* */
+	free_devices();
+	/* and get rid of /dev/v4l2loopback */
+	misc_deregister(&v4l2loopback_misc);
+	dprintk("module removed\n");
+}
+
+MODULE_ALIAS_MISCDEV(MISC_DYNAMIC_MINOR);
+
+module_init(v4l2loopback_init_module);
+module_exit(v4l2loopback_cleanup_module);
diff --git a/v4l2loopback.h b/v4l2loopback.h
new file mode 100644
index 0000000..189a776
--- /dev/null
+++ b/v4l2loopback.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
+/*
+ * v4l2loopback.h
+ *
+ * Written by IOhannes m zmölnig, 7/1/20.
+ *
+ * Copyright 2020 by IOhannes m zmölnig.  Redistribution of this file is
+ * permitted under the GNU General Public License.
+ */
+#ifndef _V4L2LOOPBACK_H
+#define _V4L2LOOPBACK_H
+
+#define V4L2LOOPBACK_VERSION_MAJOR 0
+#define V4L2LOOPBACK_VERSION_MINOR 15
+#define V4L2LOOPBACK_VERSION_BUGFIX 2
+
+/* /dev/v4l2loopback interface */
+
+struct v4l2_loopback_config {
+	/**
+         * the device-number (/dev/video<nr>)
+         * V4L2LOOPBACK_CTL_ADD:
+         * setting this to a value<0, will allocate an available one
+         * if nr>=0 and the device already exists, the ioctl will EEXIST
+         * if output_nr and capture_nr are the same, only a single device will be created
+	 * NOTE: currently split-devices (where output_nr and capture_nr differ)
+	 *   are not implemented yet.
+	 *   until then, requesting different device-IDs will result in EINVAL.
+         *
+         * V4L2LOOPBACK_CTL_QUERY:
+         * either both output_nr and capture_nr must refer to the same loopback,
+         * or one (and only one) of them must be -1
+         *
+         */
+	__s32 output_nr;
+	__s32 unused; /*capture_nr;*/
+
+	/**
+         * a nice name for your device
+         * if (*card_label)==0, an automatic name is assigned
+         */
+	char card_label[32];
+
+	/**
+         * allowed frame size
+         * if too low, default values are used
+         */
+	__u32 min_width;
+	__u32 max_width;
+	__u32 min_height;
+	__u32 max_height;
+
+	/**
+         * number of buffers to allocate for the queue
+         * if set to <=0, default values are used
+         */
+	__s32 max_buffers;
+
+	/**
+         * how many consumers are allowed to open this device concurrently
+         * if set to <=0, default values are used
+         */
+	__s32 max_openers;
+
+	/**
+         * set the debugging level for this device
+         */
+	__s32 debug;
+
+	/**
+         * whether to announce OUTPUT/CAPTURE capabilities exclusively
+         * for this device or not
+         * (!exclusive_caps)
+	 * NOTE: this is going to be removed once separate output/capture
+	 *       devices are implemented
+         */
+	__s32 announce_all_caps;
+};
+
+#define V4L2LOOPBACK_CTL_IOCTLMAGIC '~'
+
+/* a pointer to an (unsigned int) that - on success - will hold
+ * the version code of the v4l2loopback module
+ * as returned by KERNEL_VERSION(MAJOR, MINOR, BUGFIX)
+ */
+#define V4L2LOOPBACK_CTL_VERSION _IOR(V4L2LOOPBACK_CTL_IOCTLMAGIC, 0, __u32)
+
+/* a pointer to a (struct v4l2_loopback_config) that has all values you wish to impose on the
+ * to-be-created device set.
+ * if the ptr is NULL, a new device is created with default values at the driver's discretion.
+ *
+ * returns the device_nr of the OUTPUT device (which can be used with V4L2LOOPBACK_CTL_QUERY,
+ * to get more information on the device)
+ */
+#define V4L2LOOPBACK_CTL_ADD \
+	_IOW(V4L2LOOPBACK_CTL_IOCTLMAGIC, 1, struct v4l2_loopback_config)
+
+/* the device-number (either CAPTURE or OUTPUT) associated with the loopback-device */
+#define V4L2LOOPBACK_CTL_REMOVE _IOW(V4L2LOOPBACK_CTL_IOCTLMAGIC, 2, __u32)
+
+/* a pointer to a (struct v4l2_loopback_config) that has output_nr and/or capture_nr set
+ * (the two values must either refer to video-devices associated with the same loopback device
+ *  or exactly one of them must be <0
+ */
+#define V4L2LOOPBACK_CTL_QUERY \
+	_IOWR(V4L2LOOPBACK_CTL_IOCTLMAGIC, 3, struct v4l2_loopback_config)
+
+#endif /* _V4L2LOOPBACK_H */
diff --git a/v4l2loopback_formats.h b/v4l2loopback_formats.h
new file mode 100644
index 0000000..ac2f1cb
--- /dev/null
+++ b/v4l2loopback_formats.h
@@ -0,0 +1,453 @@
+static const struct v4l2l_format formats[] = {
+#ifndef V4L2_PIX_FMT_VP9
+#define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0')
+#endif
+#ifndef V4L2_PIX_FMT_HEVC
+#define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C')
+#endif
+
+	/* here come the packed formats */
+	{
+		.name = "32 bpp RGB, le",
+		.fourcc = V4L2_PIX_FMT_BGR32,
+		.depth = 32,
+		.flags = 0,
+	},
+	{
+		.name = "32 bpp RGB, be",
+		.fourcc = V4L2_PIX_FMT_RGB32,
+		.depth = 32,
+		.flags = 0,
+	},
+	{
+		.name = "24 bpp RGB, le",
+		.fourcc = V4L2_PIX_FMT_BGR24,
+		.depth = 24,
+		.flags = 0,
+	},
+	{
+		.name = "24 bpp RGB, be",
+		.fourcc = V4L2_PIX_FMT_RGB24,
+		.depth = 24,
+		.flags = 0,
+	},
+#ifdef V4L2_PIX_FMT_ABGR32
+	{
+		.name = "32 bpp RGBA, le",
+		.fourcc = V4L2_PIX_FMT_ABGR32,
+		.depth = 32,
+		.flags = 0,
+	},
+#endif
+#ifdef V4L2_PIX_FMT_XBGR32
+	{
+		.name = "32 bpp BGRX-8-8-8-8",
+		.fourcc = V4L2_PIX_FMT_XBGR32,
+		.depth = 32,
+		.flags = 0,
+	},
+#endif
+#ifdef V4L2_PIX_FMT_RGBA32
+	{
+		.name = "32 bpp RGBA",
+		.fourcc = V4L2_PIX_FMT_RGBA32,
+		.depth = 32,
+		.flags = 0,
+	},
+#endif
+#ifdef V4L2_PIX_FMT_RGB332
+	{
+		.name = "8 bpp RGB-3-3-2",
+		.fourcc = V4L2_PIX_FMT_RGB332,
+		.depth = 8,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_RGB332 */
+#ifdef V4L2_PIX_FMT_RGB444
+	{
+		.name = "16 bpp RGB (xxxxrrrr ggggbbbb)",
+		.fourcc = V4L2_PIX_FMT_RGB444,
+		.depth = 16,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_RGB444 */
+#ifdef V4L2_PIX_FMT_RGB555
+	{
+		.name = "16 bpp RGB-5-5-5",
+		.fourcc = V4L2_PIX_FMT_RGB555,
+		.depth = 16,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_RGB555 */
+#ifdef V4L2_PIX_FMT_RGB565
+	{
+		.name = "16 bpp RGB-5-6-5",
+		.fourcc = V4L2_PIX_FMT_RGB565,
+		.depth = 16,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_RGB565 */
+#ifdef V4L2_PIX_FMT_RGB555X
+	{
+		.name = "16 bpp RGB-5-5-5 BE",
+		.fourcc = V4L2_PIX_FMT_RGB555X,
+		.depth = 16,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_RGB555X */
+#ifdef V4L2_PIX_FMT_RGB565X
+	{
+		.name = "16 bpp RGB-5-6-5 BE",
+		.fourcc = V4L2_PIX_FMT_RGB565X,
+		.depth = 16,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_RGB565X */
+#ifdef V4L2_PIX_FMT_BGR666
+	{
+		.name = "18 bpp BGR-6-6-6",
+		.fourcc = V4L2_PIX_FMT_BGR666,
+		.depth = 18,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_BGR666 */
+	{
+		.name = "4:2:2, packed, YUYV",
+		.fourcc = V4L2_PIX_FMT_YUYV,
+		.depth = 16,
+		.flags = 0,
+	},
+	{
+		.name = "4:2:2, packed, UYVY",
+		.fourcc = V4L2_PIX_FMT_UYVY,
+		.depth = 16,
+		.flags = 0,
+	},
+#ifdef V4L2_PIX_FMT_YVYU
+	{
+		.name = "4:2:2, packed YVYU",
+		.fourcc = V4L2_PIX_FMT_YVYU,
+		.depth = 16,
+		.flags = 0,
+	},
+#endif
+#ifdef V4L2_PIX_FMT_VYUY
+	{
+		.name = "4:2:2, packed VYUY",
+		.fourcc = V4L2_PIX_FMT_VYUY,
+		.depth = 16,
+		.flags = 0,
+	},
+#endif
+	{
+		.name = "4:2:2, packed YYUV",
+		.fourcc = V4L2_PIX_FMT_YYUV,
+		.depth = 16,
+		.flags = 0,
+	},
+	{
+		.name = "YUV-8-8-8-8",
+		.fourcc = V4L2_PIX_FMT_YUV32,
+		.depth = 32,
+		.flags = 0,
+	},
+	{
+		.name = "8 bpp, Greyscale",
+		.fourcc = V4L2_PIX_FMT_GREY,
+		.depth = 8,
+		.flags = 0,
+	},
+#ifdef V4L2_PIX_FMT_Y4
+	{
+		.name = "4 bpp Greyscale",
+		.fourcc = V4L2_PIX_FMT_Y4,
+		.depth = 4,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_Y4 */
+#ifdef V4L2_PIX_FMT_Y6
+	{
+		.name = "6 bpp Greyscale",
+		.fourcc = V4L2_PIX_FMT_Y6,
+		.depth = 6,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_Y6 */
+#ifdef V4L2_PIX_FMT_Y10
+	{
+		.name = "10 bpp Greyscale",
+		.fourcc = V4L2_PIX_FMT_Y10,
+		.depth = 10,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_Y10 */
+#ifdef V4L2_PIX_FMT_Y12
+	{
+		.name = "12 bpp Greyscale",
+		.fourcc = V4L2_PIX_FMT_Y12,
+		.depth = 12,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_Y12 */
+	{
+		.name = "16 bpp, Greyscale",
+		.fourcc = V4L2_PIX_FMT_Y16,
+		.depth = 16,
+		.flags = 0,
+	},
+#ifdef V4L2_PIX_FMT_YUV444
+	{
+		.name = "16 bpp xxxxyyyy uuuuvvvv",
+		.fourcc = V4L2_PIX_FMT_YUV444,
+		.depth = 16,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_YUV444 */
+#ifdef V4L2_PIX_FMT_YUV555
+	{
+		.name = "16 bpp YUV-5-5-5",
+		.fourcc = V4L2_PIX_FMT_YUV555,
+		.depth = 16,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_YUV555 */
+#ifdef V4L2_PIX_FMT_YUV565
+	{
+		.name = "16 bpp YUV-5-6-5",
+		.fourcc = V4L2_PIX_FMT_YUV565,
+		.depth = 16,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_YUV565 */
+
+/* bayer formats */
+#ifdef V4L2_PIX_FMT_SRGGB8
+	{
+		.name = "Bayer RGGB 8bit",
+		.fourcc = V4L2_PIX_FMT_SRGGB8,
+		.depth = 8,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_SRGGB8 */
+#ifdef V4L2_PIX_FMT_SGRBG8
+	{
+		.name = "Bayer GRBG 8bit",
+		.fourcc = V4L2_PIX_FMT_SGRBG8,
+		.depth = 8,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_SGRBG8 */
+#ifdef V4L2_PIX_FMT_SGBRG8
+	{
+		.name = "Bayer GBRG 8bit",
+		.fourcc = V4L2_PIX_FMT_SGBRG8,
+		.depth = 8,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_SGBRG8 */
+#ifdef V4L2_PIX_FMT_SBGGR8
+	{
+		.name = "Bayer BA81 8bit",
+		.fourcc = V4L2_PIX_FMT_SBGGR8,
+		.depth = 8,
+		.flags = 0,
+	},
+#endif /* V4L2_PIX_FMT_SBGGR8 */
+
+	/* here come the planar formats */
+	{
+		.name = "4:1:0, planar, Y-Cr-Cb",
+		.fourcc = V4L2_PIX_FMT_YVU410,
+		.depth = 9,
+		.flags = FORMAT_FLAGS_PLANAR,
+	},
+	{
+		.name = "4:2:0, planar, Y-Cr-Cb",
+		.fourcc = V4L2_PIX_FMT_YVU420,
+		.depth = 12,
+		.flags = FORMAT_FLAGS_PLANAR,
+	},
+	{
+		.name = "4:1:0, planar, Y-Cb-Cr",
+		.fourcc = V4L2_PIX_FMT_YUV410,
+		.depth = 9,
+		.flags = FORMAT_FLAGS_PLANAR,
+	},
+	{
+		.name = "4:2:0, planar, Y-Cb-Cr",
+		.fourcc = V4L2_PIX_FMT_YUV420,
+		.depth = 12,
+		.flags = FORMAT_FLAGS_PLANAR,
+	},
+#ifdef V4L2_PIX_FMT_YUV422P
+	{
+		.name = "16 bpp YVU422 planar",
+		.fourcc = V4L2_PIX_FMT_YUV422P,
+		.depth = 16,
+		.flags = FORMAT_FLAGS_PLANAR,
+	},
+#endif /* V4L2_PIX_FMT_YUV422P */
+#ifdef V4L2_PIX_FMT_YUV411P
+	{
+		.name = "16 bpp YVU411 planar",
+		.fourcc = V4L2_PIX_FMT_YUV411P,
+		.depth = 16,
+		.flags = FORMAT_FLAGS_PLANAR,
+	},
+#endif /* V4L2_PIX_FMT_YUV411P */
+#ifdef V4L2_PIX_FMT_Y41P
+	{
+		.name = "12 bpp YUV 4:1:1",
+		.fourcc = V4L2_PIX_FMT_Y41P,
+		.depth = 12,
+		.flags = FORMAT_FLAGS_PLANAR,
+	},
+#endif /* V4L2_PIX_FMT_Y41P */
+#ifdef V4L2_PIX_FMT_NV12
+	{
+		.name = "12 bpp Y/CbCr 4:2:0 ",
+		.fourcc = V4L2_PIX_FMT_NV12,
+		.depth = 12,
+		.flags = FORMAT_FLAGS_PLANAR,
+	},
+#endif /* V4L2_PIX_FMT_NV12 */
+
+/* here come the compressed formats */
+
+#ifdef V4L2_PIX_FMT_MJPEG
+	{
+		.name = "Motion-JPEG",
+		.fourcc = V4L2_PIX_FMT_MJPEG,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_MJPEG */
+#ifdef V4L2_PIX_FMT_JPEG
+	{
+		.name = "JFIF JPEG",
+		.fourcc = V4L2_PIX_FMT_JPEG,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_JPEG */
+#ifdef V4L2_PIX_FMT_DV
+	{
+		.name = "DV1394",
+		.fourcc = V4L2_PIX_FMT_DV,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_DV */
+#ifdef V4L2_PIX_FMT_MPEG
+	{
+		.name = "MPEG-1/2/4 Multiplexed",
+		.fourcc = V4L2_PIX_FMT_MPEG,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_MPEG */
+#ifdef V4L2_PIX_FMT_H264
+	{
+		.name = "H264 with start codes",
+		.fourcc = V4L2_PIX_FMT_H264,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_H264 */
+#ifdef V4L2_PIX_FMT_H264_NO_SC
+	{
+		.name = "H264 without start codes",
+		.fourcc = V4L2_PIX_FMT_H264_NO_SC,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_H264_NO_SC */
+#ifdef V4L2_PIX_FMT_H264_MVC
+	{
+		.name = "H264 MVC",
+		.fourcc = V4L2_PIX_FMT_H264_MVC,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_H264_MVC */
+#ifdef V4L2_PIX_FMT_H263
+	{
+		.name = "H263",
+		.fourcc = V4L2_PIX_FMT_H263,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_H263 */
+#ifdef V4L2_PIX_FMT_MPEG1
+	{
+		.name = "MPEG-1 ES",
+		.fourcc = V4L2_PIX_FMT_MPEG1,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_MPEG1 */
+#ifdef V4L2_PIX_FMT_MPEG2
+	{
+		.name = "MPEG-2 ES",
+		.fourcc = V4L2_PIX_FMT_MPEG2,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_MPEG2 */
+#ifdef V4L2_PIX_FMT_MPEG4
+	{
+		.name = "MPEG-4 part 2 ES",
+		.fourcc = V4L2_PIX_FMT_MPEG4,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_MPEG4 */
+#ifdef V4L2_PIX_FMT_XVID
+	{
+		.name = "Xvid",
+		.fourcc = V4L2_PIX_FMT_XVID,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_XVID */
+#ifdef V4L2_PIX_FMT_VC1_ANNEX_G
+	{
+		.name = "SMPTE 421M Annex G compliant stream",
+		.fourcc = V4L2_PIX_FMT_VC1_ANNEX_G,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_VC1_ANNEX_G */
+#ifdef V4L2_PIX_FMT_VC1_ANNEX_L
+	{
+		.name = "SMPTE 421M Annex L compliant stream",
+		.fourcc = V4L2_PIX_FMT_VC1_ANNEX_L,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_VC1_ANNEX_L */
+#ifdef V4L2_PIX_FMT_VP8
+	{
+		.name = "VP8",
+		.fourcc = V4L2_PIX_FMT_VP8,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_VP8 */
+#ifdef V4L2_PIX_FMT_VP9
+	{
+		.name = "VP9",
+		.fourcc = V4L2_PIX_FMT_VP9,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_VP9 */
+#ifdef V4L2_PIX_FMT_HEVC
+	{
+		.name = "HEVC",
+		.fourcc = V4L2_PIX_FMT_HEVC,
+		.depth = 32,
+		.flags = FORMAT_FLAGS_COMPRESSED,
+	},
+#endif /* V4L2_PIX_FMT_HEVC */
+};
diff --git a/vbox-6.1-fix-build-on-znver1-hosts.patch b/vbox-6.1-fix-build-on-znver1-hosts.patch
deleted file mode 100644
index e3ac678..0000000
--- a/vbox-6.1-fix-build-on-znver1-hosts.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-diff -up linux-5.19/drivers/net/vboxnetadp/Makefile-header.gmk.1005~ linux-5.19/drivers/net/vboxnetadp/Makefile-header.gmk
---- linux-5.19/drivers/net/vboxnetadp/Makefile-header.gmk.1005~	2022-08-03 19:04:38.657271905 +0200
-+++ linux-5.19/drivers/net/vboxnetadp/Makefile-header.gmk	2022-08-03 19:10:42.930549625 +0200
-@@ -50,7 +50,7 @@
- #
- 
- # VBOX_KBUILD_TARGET_ARCH = amd64|x86
--ifeq ($(filter-out x86_64 amd64 AMD64,$(shell rpm --eval %_target_cpu)),)
-+ifeq ($(filter-out x86_64 znver1 amd64 AMD64,$(shell rpm --eval %_target_cpu)),)
-  VBOX_KBUILD_TARGET_ARCH_DEFAULT := amd64
- else
-  VBOX_KBUILD_TARGET_ARCH_DEFAULT := x86
-diff -up linux-5.19/drivers/net/vboxnetflt/Makefile-header.gmk.1005~ linux-5.19/drivers/net/vboxnetflt/Makefile-header.gmk
---- linux-5.19/drivers/net/vboxnetflt/Makefile-header.gmk.1005~	2022-08-03 19:04:38.658271914 +0200
-+++ linux-5.19/drivers/net/vboxnetflt/Makefile-header.gmk	2022-08-03 19:10:55.337660864 +0200
-@@ -50,7 +50,7 @@
- #
- 
- # VBOX_KBUILD_TARGET_ARCH = amd64|x86
--ifeq ($(filter-out x86_64 amd64 AMD64,$(shell rpm --eval %_target_cpu)),)
-+ifeq ($(filter-out x86_64 znver1 amd64 AMD64,$(shell rpm --eval %_target_cpu)),)
-  VBOX_KBUILD_TARGET_ARCH_DEFAULT := amd64
- else
-  VBOX_KBUILD_TARGET_ARCH_DEFAULT := x86
-diff -up linux-5.19/drivers/virt/vboxdrv/Makefile-header.gmk.1005~ linux-5.19/drivers/virt/vboxdrv/Makefile-header.gmk
---- linux-5.19/drivers/virt/vboxdrv/Makefile-header.gmk.1005~	2022-08-03 19:04:38.658271914 +0200
-+++ linux-5.19/drivers/virt/vboxdrv/Makefile-header.gmk	2022-08-03 19:11:13.765826050 +0200
-@@ -50,7 +50,7 @@
- #
- 
- # VBOX_KBUILD_TARGET_ARCH = amd64|x86
--ifeq ($(filter-out x86_64 amd64 AMD64,$(shell rpm --eval %_target_cpu)),)
-+ifeq ($(filter-out x86_64 znver1 amd64 AMD64,$(shell rpm --eval %_target_cpu)),)
-  VBOX_KBUILD_TARGET_ARCH_DEFAULT := amd64
- else
-  VBOX_KBUILD_TARGET_ARCH_DEFAULT := x86
diff --git a/vbox-clang12.patch b/vbox-clang12.patch
deleted file mode 100644
index 6606ca1..0000000
--- a/vbox-clang12.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-diff -up linux-5.13/drivers/net/vboxnetadp/r0drv/linux/the-linux-kernel.h.omv~ linux-5.13/drivers/net/vboxnetadp/r0drv/linux/the-linux-kernel.h
---- linux-5.13/drivers/net/vboxnetadp/r0drv/linux/the-linux-kernel.h.omv~	2021-07-09 05:06:23.643468874 +0200
-+++ linux-5.13/drivers/net/vboxnetadp/r0drv/linux/the-linux-kernel.h	2021-07-09 05:06:36.147112574 +0200
-@@ -42,7 +42,7 @@
- #endif
- #if RT_GNUC_PREREQ(4, 2)
- # pragma GCC diagnostic ignored "-Wunused-parameter"
--# if !defined(__cplusplus) && RT_GNUC_PREREQ(4, 3)
-+# if !defined(__cplusplus) && RT_GNUC_PREREQ(4, 3) && !defined(__clang__)
- #  pragma GCC diagnostic ignored "-Wold-style-declaration" /* 2.6.18-411.0.0.0.1.el5/build/include/asm/apic.h:110: warning: 'inline' is not at beginning of declaration [-Wold-style-declaration] */
- # endif
- #endif
-diff -up linux-5.13/drivers/virt/vboxdrv/r0drv/linux/the-linux-kernel.h.omv~ linux-5.13/drivers/virt/vboxdrv/r0drv/linux/the-linux-kernel.h
---- linux-5.13/drivers/virt/vboxdrv/r0drv/linux/the-linux-kernel.h.omv~	2021-07-09 16:52:13.756938396 +0200
-+++ linux-5.13/drivers/virt/vboxdrv/r0drv/linux/the-linux-kernel.h	2021-07-09 16:52:23.253681655 +0200
-@@ -42,7 +42,7 @@
- #endif
- #if RT_GNUC_PREREQ(4, 2)
- # pragma GCC diagnostic ignored "-Wunused-parameter"
--# if !defined(__cplusplus) && RT_GNUC_PREREQ(4, 3)
-+# if !defined(__cplusplus) && RT_GNUC_PREREQ(4, 3) && !defined(__clang__)
- #  pragma GCC diagnostic ignored "-Wold-style-declaration" /* 2.6.18-411.0.0.0.1.el5/build/include/asm/apic.h:110: warning: 'inline' is not at beginning of declaration [-Wold-style-declaration] */
- # endif
- #endif
-diff -up linux-5.13/drivers/net/vboxnetflt/r0drv/linux/the-linux-kernel.h.omv~ linux-5.13/drivers/net/vboxnetflt/r0drv/linux/the-linux-kernel.h
---- linux-5.13/drivers/net/vboxnetflt/r0drv/linux/the-linux-kernel.h.omv~	2021-07-09 17:22:34.984140145 +0200
-+++ linux-5.13/drivers/net/vboxnetflt/r0drv/linux/the-linux-kernel.h	2021-07-09 17:22:42.934198757 +0200
-@@ -42,7 +42,7 @@
- #endif
- #if RT_GNUC_PREREQ(4, 2)
- # pragma GCC diagnostic ignored "-Wunused-parameter"
--# if !defined(__cplusplus) && RT_GNUC_PREREQ(4, 3)
-+# if !defined(__cplusplus) && RT_GNUC_PREREQ(4, 3) && !defined(__clang__)
- #  pragma GCC diagnostic ignored "-Wold-style-declaration" /* 2.6.18-411.0.0.0.1.el5/build/include/asm/apic.h:110: warning: 'inline' is not at beginning of declaration [-Wold-style-declaration] */
- # endif
- #endif
diff --git a/vbox-kernel-7.0.patch b/vbox-kernel-7.0.patch
new file mode 100644
index 0000000..4efd2df
--- /dev/null
+++ b/vbox-kernel-7.0.patch
@@ -0,0 +1,12 @@
+diff -up linux-7.0/drivers/virt/vboxdrv/linux/SUPDrv-linux.c.omv~ linux-7.0/drivers/virt/vboxdrv/linux/SUPDrv-linux.c
+--- linux-7.0/drivers/virt/vboxdrv/linux/SUPDrv-linux.c.omv~	2026-04-19 22:24:48.972985841 +0200
++++ linux-7.0/drivers/virt/vboxdrv/linux/SUPDrv-linux.c	2026-04-19 22:26:53.225276734 +0200
+@@ -504,7 +504,7 @@ static int __init supdrvLinuxInitKvmSymb
+                 RTThreadPreemptDisable(&Preempt);
+                 if (   uLeaves >= 7
+                     && RTX86IsValidStdRange(uLeaves)
+-                    && (ASMCpuIdEx_EDX(7, 0) & X86_CPUID_STEXT_FEATURE_EDX_CET_IBT))
++                    && (VBoxHost_ASMCpuId_EDX(7) & X86_CPUID_STEXT_FEATURE_EDX_CET_IBT))
+                 {
+                     uint64_t const fSupCet = ASMRdMsr(MSR_IA32_S_CET);
+                     ASMWrMsr(MSR_IA32_S_CET, fSupCet & ~MSR_IA32_CET_ENDBR_EN);
diff --git a/vbox-modules-6.15.patch b/vbox-modules-6.15.patch
new file mode 100644
index 0000000..2ccd42b
--- /dev/null
+++ b/vbox-modules-6.15.patch
@@ -0,0 +1,59 @@
+diff -up linux-6.15-rc1/drivers/net/vboxnetadp/Makefile-footer.gmk.omv~ linux-6.15-rc1/drivers/net/vboxnetadp/Makefile-footer.gmk
+--- linux-6.15-rc1/drivers/net/vboxnetadp/Makefile-footer.gmk.omv~	2025-04-10 21:58:54.267848342 +0200
++++ linux-6.15-rc1/drivers/net/vboxnetadp/Makefile-footer.gmk	2025-04-10 21:58:59.564243071 +0200
+@@ -114,7 +114,7 @@ else  # VBOX_KERN_GROKS_EXTMOD
+ VBOXMOD_EXT := ko
+ 
+ # build defs
+-EXTRA_CFLAGS += $(VBOXMOD_CFLAGS) $(addprefix -I,$(KERN_INCL) $(VBOXMOD_INCL)) $(VBOXMOD_0_KFLAGS) $(KDEBUG)
++ccflags-y += $(VBOXMOD_CFLAGS) $(addprefix -I,$(KERN_INCL) $(VBOXMOD_INCL)) $(VBOXMOD_0_KFLAGS) $(KDEBUG)
+ $(VBOXMOD_0_TARGET)-y := $(VBOXMOD_OBJS)
+ obj-m += $(VBOXMOD_0_TARGET).o
+ 
+diff -up linux-6.15-rc1/drivers/net/vboxnetadp/Makefile.omv~ linux-6.15-rc1/drivers/net/vboxnetadp/Makefile
+diff -up linux-6.15-rc1/drivers/net/vboxnetflt/Makefile-footer.gmk.omv~ linux-6.15-rc1/drivers/net/vboxnetflt/Makefile-footer.gmk
+--- linux-6.15-rc1/drivers/net/vboxnetflt/Makefile-footer.gmk.omv~	2025-04-10 21:59:12.120376408 +0200
++++ linux-6.15-rc1/drivers/net/vboxnetflt/Makefile-footer.gmk	2025-04-10 21:59:16.671451608 +0200
+@@ -114,7 +114,7 @@ else  # VBOX_KERN_GROKS_EXTMOD
+ VBOXMOD_EXT := ko
+ 
+ # build defs
+-EXTRA_CFLAGS += $(VBOXMOD_CFLAGS) $(addprefix -I,$(KERN_INCL) $(VBOXMOD_INCL)) $(VBOXMOD_0_KFLAGS) $(KDEBUG)
++ccflags-y += $(VBOXMOD_CFLAGS) $(addprefix -I,$(KERN_INCL) $(VBOXMOD_INCL)) $(VBOXMOD_0_KFLAGS) $(KDEBUG)
+ $(VBOXMOD_0_TARGET)-y := $(VBOXMOD_OBJS)
+ obj-m += $(VBOXMOD_0_TARGET).o
+ 
+diff -up linux-6.15-rc1/drivers/virt/vboxdrv/Makefile-footer.gmk.omv~ linux-6.15-rc1/drivers/virt/vboxdrv/Makefile-footer.gmk
+--- linux-6.15-rc1/drivers/virt/vboxdrv/Makefile-footer.gmk.omv~	2025-04-10 21:58:37.929294067 +0200
++++ linux-6.15-rc1/drivers/virt/vboxdrv/Makefile-footer.gmk	2025-04-10 21:58:44.664063880 +0200
+@@ -114,7 +114,7 @@ else  # VBOX_KERN_GROKS_EXTMOD
+ VBOXMOD_EXT := ko
+ 
+ # build defs
+-EXTRA_CFLAGS += $(VBOXMOD_CFLAGS) $(addprefix -I,$(KERN_INCL) $(VBOXMOD_INCL)) $(VBOXMOD_0_KFLAGS) $(KDEBUG)
++ccflags-y += $(VBOXMOD_CFLAGS) $(addprefix -I,$(KERN_INCL) $(VBOXMOD_INCL)) $(VBOXMOD_0_KFLAGS) $(KDEBUG)
+ $(VBOXMOD_0_TARGET)-y := $(VBOXMOD_OBJS)
+ obj-m += $(VBOXMOD_0_TARGET).o
+ 
+diff -up linux-6.15-rc1/drivers/virt/vboxdrv/r0drv/linux/timer-r0drv-linux.c.omv~ linux-6.15-rc1/drivers/virt/vboxdrv/r0drv/linux/timer-r0drv-linux.c
+--- linux-6.15-rc1/drivers/virt/vboxdrv/r0drv/linux/timer-r0drv-linux.c.omv~	2025-04-10 22:52:47.513132293 +0200
++++ linux-6.15-rc1/drivers/virt/vboxdrv/r0drv/linux/timer-r0drv-linux.c	2025-04-10 22:56:34.286807003 +0200
+@@ -422,7 +422,7 @@ static void rtTimerLnxStopSubTimer(PRTTI
+     }
+     else
+ #endif
+-        del_timer(&pSubTimer->u.Std.LnxTimer);
++        timer_delete(&pSubTimer->u.Std.LnxTimer);
+ 
+     rtTimerLnxSetState(&pSubTimer->enmState, RTTIMERLNXSTATE_STOPPED);
+ }
+@@ -1626,8 +1626,7 @@ RTDECL(int) RTTimerCreateEx(PRTTIMER *pp
+ #ifdef RTTIMER_LINUX_WITH_HRTIMER
+         if (pTimer->fHighRes)
+         {
+-            hrtimer_init(&pTimer->aSubTimers[iCpu].u.Hr.LnxTimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
+-            pTimer->aSubTimers[iCpu].u.Hr.LnxTimer.function     = rtTimerLinuxHrCallback;
++            hrtimer_setup(&pTimer->aSubTimers[iCpu].u.Hr.LnxTimer, rtTimerLinuxHrCallback, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
+         }
+         else
+ #endif
diff --git a/vbox-modules-7.1.6-compile.patch b/vbox-modules-7.1.6-compile.patch
new file mode 100644
index 0000000..95f701d
--- /dev/null
+++ b/vbox-modules-7.1.6-compile.patch
@@ -0,0 +1,12 @@
+diff -up linux-6.14/drivers/gpu/drm/vboxvideo/vbox_drv.c.omv~ linux-6.14/drivers/gpu/drm/vboxvideo/vbox_drv.c
+--- linux-6.14/drivers/gpu/drm/vboxvideo/vbox_drv.c.omv~	2025-03-25 22:37:45.825536280 +0100
++++ linux-6.14/drivers/gpu/drm/vboxvideo/vbox_drv.c	2025-03-25 22:38:13.661512603 +0100
+@@ -59,7 +59,7 @@
+ # define VBOX_VIDEO_NOMODESET() 0
+ #endif /* !CONFIG_VGA_CONSOLE */
+ 
+-#include <VBox/VBoxLnxModInline.h>
++#include "VBox/VBoxLnxModInline.h"
+ 
+ static int vbox_modeset = -1;
+ 
diff --git a/vboxvideo-kernel-6.3.patch b/vboxvideo-kernel-6.3.patch
new file mode 100644
index 0000000..92eb1c4
--- /dev/null
+++ b/vboxvideo-kernel-6.3.patch
@@ -0,0 +1,90 @@
+diff -up linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_drv.h.omv~ linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_drv.h
+--- linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_drv.h.omv~	2023-03-14 05:47:42.731608382 +0100
++++ linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_drv.h	2023-03-14 05:47:52.964779554 +0100
+@@ -167,8 +167,7 @@
+ # include <drm/drm_gem.h>
+ #endif
+ 
+-#include <drm/ttm/ttm_bo_api.h>
+-#include <drm/ttm/ttm_bo_driver.h>
++#include <drm/ttm/ttm_bo.h>
+ #include <drm/ttm/ttm_placement.h>
+ #if RTLNX_VER_MAX(5,13,0) && !RTLNX_RHEL_RANGE(8,6, 8,99)
+ # include <drm/ttm/ttm_memory.h>
+diff -up linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_fb.c.omv~ linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_fb.c
+--- linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_fb.c.omv~	2023-03-14 05:48:01.068916725 +0100
++++ linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_fb.c	2023-03-14 05:50:03.912119725 +0100
+@@ -340,13 +340,6 @@ static int vboxfb_create(struct drm_fb_h
+ 	info->flags = FBINFO_DEFAULT | FBINFO_MISC_ALWAYS_SETPAR;
+ 	info->fbops = &vboxfb_ops;
+ 
+-	/*
+-	 * This seems to be done for safety checking that the framebuffer
+-	 * is not registered twice by different drivers.
+-	 */
+-	info->apertures->ranges[0].base = pci_resource_start(VBOX_DRM_TO_PCI_DEV(dev), 0);
+-	info->apertures->ranges[0].size = pci_resource_len(VBOX_DRM_TO_PCI_DEV(dev), 0);
+-
+ #if RTLNX_VER_MIN(5,2,0) || RTLNX_RHEL_MAJ_PREREQ(8,2)
+ 		/*
+ 		 * The corresponding 5.2-rc1 Linux DRM kernel changes have been
+@@ -455,7 +448,7 @@ int vbox_fbdev_init(struct drm_device *d
+ #if RTLNX_VER_MAX(3,17,0) && !RTLNX_RHEL_MAJ_PREREQ(7,2)
+ 	fbdev->helper.funcs = &vbox_fb_helper_funcs;
+ #else
+-	drm_fb_helper_prepare(dev, &fbdev->helper, &vbox_fb_helper_funcs);
++	drm_fb_helper_prepare(dev, &fbdev->helper, 32, &vbox_fb_helper_funcs);
+ #endif
+ #if RTLNX_VER_MIN(5,7,0) || RTLNX_RHEL_MIN(8,4) || RTLNX_SUSE_MAJ_PREREQ(15,3)
+ 		ret = drm_fb_helper_init(dev, &fbdev->helper);
+@@ -478,7 +471,7 @@ int vbox_fbdev_init(struct drm_device *d
+ 	/* disable all the possible outputs/crtcs before entering KMS mode */
+ 	drm_helper_disable_unused_functions(dev);
+ 
+-	ret = drm_fb_helper_initial_config(&fbdev->helper, 32);
++	ret = drm_fb_helper_initial_config(&fbdev->helper);
+ 	if (ret)
+ 		goto err_fini;
+ 
+@@ -493,6 +486,6 @@ void vbox_fbdev_set_base(struct vbox_pri
+ {
+ 	struct fb_info *fbdev = VBOX_FBDEV_INFO(vbox->fbdev->helper);
+ 
+-	fbdev->fix.smem_start = fbdev->apertures->ranges[0].base + gpu_addr;
++	fbdev->fix.smem_start = pci_resource_start(VBOX_DRM_TO_PCI_DEV(vbox->fbdev->helper.dev), 0) + gpu_addr;
+ 	fbdev->fix.smem_len = vbox->available_vram_size - gpu_addr;
+ }
+diff -up linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_main.c.omv~ linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_main.c
+--- linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_main.c.omv~	2023-03-14 05:50:14.681320519 +0100
++++ linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_main.c	2023-03-14 05:50:26.079533935 +0100
+@@ -30,6 +30,7 @@
+ #include "vbox_drv.h"
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_crtc_helper.h>
++#include <drm/drm_modeset_helper.h>
+ 
+ #include "vboxvideo_guest.h"
+ #include "vboxvideo_vbe.h"
+diff -up linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_mode.c.omv~ linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_mode.c
+--- linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_mode.c.omv~	2023-03-14 05:50:29.463597463 +0100
++++ linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_mode.c	2023-03-14 05:50:58.487145096 +0100
+@@ -34,6 +34,8 @@
+ #include "vbox_drv.h"
+ #include <linux/export.h>
+ #include <drm/drm_crtc_helper.h>
++#include <drm/drm_modeset_helper_vtables.h>
++#include <drm/drm_modeset_helper.h>
+ #if RTLNX_VER_MIN(3,18,0) || RTLNX_RHEL_MAJ_PREREQ(7,2)
+ # include <drm/drm_plane_helper.h>
+ #endif
+diff -up linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_ttm.c.omv~ linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_ttm.c
+--- linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_ttm.c.omv~	2023-03-14 05:51:02.316217683 +0100
++++ linux-6.3-rc2/drivers/gpu/drm/vboxvideo/vbox_ttm.c	2023-03-14 05:51:25.480658264 +0100
+@@ -28,6 +28,7 @@
+  *          Michael Thayer <michael.thayer@oracle.com>
+  */
+ #include "vbox_drv.h"
++#include <drm/ttm/ttm_tt.h>
+ #if RTLNX_VER_MIN(5,11,0) || RTLNX_RHEL_MAJ_PREREQ(8,5)
+ # include <drm/drm_gem.h>
+ # include <drm/drm_gem_ttm_helper.h>
diff --git a/x86_64-desktop-gcc-omv-defconfig b/x86-omv-defconfig
similarity index 54%
rename from x86_64-desktop-gcc-omv-defconfig
rename to x86-omv-defconfig
index ac36633..d86160b 100644
--- a/x86_64-desktop-gcc-omv-defconfig
+++ b/x86-omv-defconfig
@@ -1,11492 +1,6954 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# Linux/x86 5.16.1-desktop-clang-1omv4050 Kernel Configuration
-#
-CONFIG_CC_VERSION_TEXT="gcc (GCC) 11.2.0 20210728 (OpenMandriva)"
-CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=110200
-CONFIG_CLANG_VERSION=0
-CONFIG_AS_IS_GNU=y
-CONFIG_AS_VERSION=23700
-CONFIG_LD_VERSION=0
-CONFIG_LD_IS_LLD=y
-CONFIG_LLD_VERSION=130000
-CONFIG_CC_CAN_LINK=y
-CONFIG_CC_CAN_LINK_STATIC=y
-CONFIG_CC_HAS_ASM_GOTO=y
-CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
-CONFIG_TOOLS_SUPPORT_RELR=y
-CONFIG_CC_HAS_ASM_INLINE=y
-CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
-CONFIG_IRQ_WORK=y
-CONFIG_BUILDTIME_TABLE_SORT=y
-CONFIG_THREAD_INFO_IN_TASK=y
-
-#
-# General setup
-#
-CONFIG_INIT_ENV_ARG_LIMIT=32
-# CONFIG_COMPILE_TEST is not set
-# CONFIG_WERROR is not set
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_BUILD_SALT="154da4f1b3ac5bfe04b8a09af50ebcb55dbc157d"
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_BZIP2=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_ZSTD=y
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_BZIP2 is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_KERNEL_ZSTD=y
-CONFIG_DEFAULT_INIT=""
-CONFIG_DEFAULT_HOSTNAME="omv"
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_POSIX_MQUEUE_SYSCTL=y
-# CONFIG_WATCH_QUEUE is not set
-CONFIG_CROSS_MEMORY_ATTACH=y
-# CONFIG_USELIB is not set
-# CONFIG_AUDIT is not set
-# CONFIG_HAVE_ARCH_AUDITSYSCALL is not set
-# CONFIG_AUDITSYSCALL is not set
-
-#
-# IRQ subsystem
-#
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_SIM=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_IRQ_MSI_IOMMU=y
-CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
-CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_SPARSE_IRQ=y
-# CONFIG_GENERIC_IRQ_DEBUGFS is not set
-# end of IRQ subsystem
-
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-CONFIG_ARCH_CLOCKSOURCE_INIT=y
-CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-
-#
-# Timers subsystem
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ_COMMON=y
-# CONFIG_HZ_PERIODIC is not set
-CONFIG_NO_HZ_IDLE=y
-# CONFIG_NO_HZ_FULL is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
-# end of Timers subsystem
-
-CONFIG_BPF=y
-CONFIG_HAVE_EBPF_JIT=y
-CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
-
-#
-# BPF subsystem
-#
-CONFIG_BPF_SYSCALL=y
-CONFIG_BPF_JIT=y
-CONFIG_BPF_JIT_ALWAYS_ON=y
-CONFIG_BPF_JIT_DEFAULT_ON=y
-# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
-# CONFIG_BPF_PRELOAD is not set
-# end of BPF subsystem
-
-CONFIG_PREEMPT_BUILD=y
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_PREEMPT_COUNT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_DYNAMIC=y
-CONFIG_SCHED_CORE=y
-
-#
-# CPU/Task time and stats accounting
-#
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_SCHED_AVG_IRQ=y
-CONFIG_BSD_PROCESS_ACCT=y
-# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_PSI=y
-# CONFIG_PSI_DEFAULT_DISABLED is not set
-# end of CPU/Task time and stats accounting
-
-CONFIG_CPU_ISOLATION=y
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-CONFIG_PREEMPT_RCU=y
-# CONFIG_RCU_EXPERT is not set
-CONFIG_SRCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TASKS_RCU_GENERIC=y
-CONFIG_TASKS_RCU=y
-CONFIG_TASKS_RUDE_RCU=y
-CONFIG_TASKS_TRACE_RCU=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RCU_NEED_SEGCBLIST=y
-# end of RCU Subsystem
-
-CONFIG_BUILD_BIN2C=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-# CONFIG_IKHEADERS is not set
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
-CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
-CONFIG_PRINTK_INDEX=y
-CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
-
-#
-# Scheduler features
-#
-# CONFIG_UCLAMP_TASK is not set
-# end of Scheduler features
-
-CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
-CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
-CONFIG_CC_HAS_INT128=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_ARCH_SUPPORTS_INT128=y
-CONFIG_NUMA_BALANCING=y
-CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
-CONFIG_CGROUPS=y
-CONFIG_PAGE_COUNTER=y
-CONFIG_MEMCG=y
-CONFIG_MEMCG_SWAP=y
-CONFIG_MEMCG_KMEM=y
-CONFIG_BLK_CGROUP=y
-CONFIG_CGROUP_WRITEBACK=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_CFS_BANDWIDTH=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_CGROUP_PIDS=y
-CONFIG_CGROUP_RDMA=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_HUGETLB=y
-CONFIG_CPUSETS=y
-CONFIG_PROC_PID_CPUSET=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_PERF=y
-CONFIG_CGROUP_BPF=y
-CONFIG_CGROUP_MISC=y
-# CONFIG_CGROUP_DEBUG is not set
-CONFIG_SOCK_CGROUP_DATA=y
-CONFIG_NAMESPACES=y
-CONFIG_UTS_NS=y
-CONFIG_TIME_NS=y
-CONFIG_IPC_NS=y
-CONFIG_USER_NS=y
-CONFIG_PID_NS=y
-CONFIG_NET_NS=y
-CONFIG_CHECKPOINT_RESTORE=y
-CONFIG_SCHED_AUTOGROUP=y
-# CONFIG_SYSFS_DEPRECATED is not set
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_XZ=y
-CONFIG_RD_LZO=y
-CONFIG_RD_LZ4=y
-CONFIG_RD_ZSTD=y
-CONFIG_BOOT_CONFIG=y
-# CONFIG_CC_OPTIMIZE_BASAL is not set
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_LD_ORPHAN_WARN=y
-CONFIG_SYSCTL=y
-CONFIG_HAVE_UID16=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_HAVE_PCSPKR_PLATFORM=y
-CONFIG_EXPERT=y
-CONFIG_UID16=y
-CONFIG_MULTIUSER=y
-CONFIG_SGETMASK_SYSCALL=y
-# CONFIG_SYSFS_SYSCALL is not set
-CONFIG_FHANDLE=y
-CONFIG_POSIX_TIMERS=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_PCSPKR_PLATFORM=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_FUTEX_PI=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_IO_URING=y
-CONFIG_ADVISE_SYSCALLS=y
-CONFIG_HAVE_ARCH_USERFAULTFD_WP=y
-CONFIG_LRU_GEN=y
-CONFIG_LRU_GEN_ENABLED=y
-# CONFIG_LRU_GEN_STATS is not set
-CONFIG_HAVE_ARCH_USERFAULTFD_MINOR=y
-CONFIG_MEMBARRIER=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y
-CONFIG_KALLSYMS_BASE_RELATIVE=y
-CONFIG_USERFAULTFD=y
-CONFIG_PTE_MARKER_UFFD_WP=y
-CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
-CONFIG_KCMP=y
-CONFIG_RSEQ=y
-# CONFIG_DEBUG_RSEQ is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_HAVE_PERF_EVENTS=y
-# CONFIG_PC104 is not set
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_PERF_EVENTS=y
-# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
-# end of Kernel Performance Events And Counters
-
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-CONFIG_SLAB_MERGE_DEFAULT=y
-CONFIG_SLAB_FREELIST_RANDOM=y
-CONFIG_SLAB_FREELIST_HARDENED=y
-CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
-CONFIG_SLUB_CPU_PARTIAL=y
-CONFIG_SYSTEM_DATA_VERIFICATION=y
-# CONFIG_PROFILING is not set
-CONFIG_TRACEPOINTS=y
-# end of General setup
-
+CONFIG_60XX_WDT=m
 CONFIG_64BIT=y
-CONFIG_X86_64=y
-CONFIG_X86=y
-CONFIG_INSTRUCTION_DECODER=y
-CONFIG_OUTPUT_FORMAT="elf64-x86-64"
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_MMU=y
-CONFIG_ARCH_MMAP_RND_BITS_MIN=28
-CONFIG_ARCH_MMAP_RND_BITS_MAX=32
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_HAS_CPU_RELAX=y
-CONFIG_ARCH_HAS_FILTER_PGPROT=y
-CONFIG_HAVE_SETUP_PER_CPU_AREA=y
-CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
-CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_NR_GPIO=1024
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-# CONFIG_AUDIT_ARCH is not set
-CONFIG_HAVE_INTEL_TXT=y
-CONFIG_X86_64_SMP=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_DYNAMIC_PHYSICAL_MASK=y
-CONFIG_PGTABLE_LEVELS=4
-CONFIG_CC_HAS_SANE_STACKPROTECTOR=y
-
-#
-# Processor type and features
-#
-CONFIG_SMP=y
-CONFIG_X86_FEATURE_NAMES=y
-CONFIG_X86_X2APIC=y
-CONFIG_X86_MPPARSE=y
-# CONFIG_GOLDFISH is not set
-CONFIG_RETPOLINE=y
-CONFIG_RETHUNK=y
-CONFIG_CPU_IBPB_ENTRY=y
-CONFIG_CPU_IBRS_ENTRY=y
-CONFIG_SLS=y
-CONFIG_X86_CPU_RESCTRL=y
-# CONFIG_X86_EXTENDED_PLATFORM is not set
-CONFIG_X86_INTEL_LPSS=y
-CONFIG_X86_AMD_PLATFORM_DEVICE=y
-CONFIG_IOSF_MBI=y
-# CONFIG_IOSF_MBI_DEBUG is not set
-CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
-CONFIG_SCHED_OMIT_FRAME_POINTER=y
-CONFIG_HYPERVISOR_GUEST=y
-CONFIG_PARAVIRT=y
-# CONFIG_PARAVIRT_DEBUG is not set
-# CONFIG_PARAVIRT_SPINLOCKS is not set
-CONFIG_X86_HV_CALLBACK_VECTOR=y
-# CONFIG_XEN is not set
-CONFIG_KVM_GUEST=y
-CONFIG_ARCH_CPUIDLE_HALTPOLL=y
-CONFIG_PVH=y
-# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
-CONFIG_PARAVIRT_CLOCK=y
-CONFIG_JAILHOUSE_GUEST=y
-# CONFIG_ACRN_GUEST is not set
-CONFIG_INTEL_TDX_GUEST=y
-# CONFIG_MK8 is not set
-# CONFIG_MK8SSE3 is not set
-# CONFIG_MK10 is not set
-# CONFIG_MBARCELONA is not set
-# CONFIG_MBOBCAT is not set
-# CONFIG_MJAGUAR is not set
-# CONFIG_MBULLDOZER is not set
-# CONFIG_MPILEDRIVER is not set
-# CONFIG_MSTEAMROLLER is not set
-# CONFIG_MEXCAVATOR is not set
-# CONFIG_MZEN is not set
-# CONFIG_MZEN2 is not set
-# CONFIG_MZEN3 is not set
-# CONFIG_MPSC is not set
-# CONFIG_MATOM is not set
-# CONFIG_MCORE2 is not set
-# CONFIG_MNEHALEM is not set
-# CONFIG_MWESTMERE is not set
-# CONFIG_MSILVERMONT is not set
-# CONFIG_MGOLDMONT is not set
-# CONFIG_MGOLDMONTPLUS is not set
-# CONFIG_MSANDYBRIDGE is not set
-# CONFIG_MIVYBRIDGE is not set
-# CONFIG_MHASWELL is not set
-# CONFIG_MBROADWELL is not set
-# CONFIG_MSKYLAKE is not set
-# CONFIG_MSKYLAKEX is not set
-# CONFIG_MCANNONLAKE is not set
-# CONFIG_MICELAKE is not set
-# CONFIG_MCASCADELAKE is not set
-# CONFIG_MCOOPERLAKE is not set
-# CONFIG_MTIGERLAKE is not set
-# CONFIG_MSAPPHIRERAPIDS is not set
-# CONFIG_MROCKETLAKE is not set
-# CONFIG_MALDERLAKE is not set
-# CONFIG_MNATIVE_INTEL is not set
-# CONFIG_MNATIVE_AMD is not set
-# CONFIG_GENERIC_CPU2 is not set
-# CONFIG_GENERIC_CPU3 is not set
-# CONFIG_GENERIC_CPU4 is not set
-CONFIG_GENERIC_CPU=y
-# CONFIG_MNATIVE is not set
-CONFIG_X86_INTERNODE_CACHE_SHIFT=6
-CONFIG_X86_L1_CACHE_SHIFT=6
-CONFIG_X86_TSC=y
-CONFIG_X86_CMPXCHG64=y
-CONFIG_X86_CMOV=y
-CONFIG_X86_MINIMUM_CPU_FAMILY=64
-CONFIG_X86_DEBUGCTLMSR=y
-CONFIG_IA32_FEAT_CTL=y
-CONFIG_X86_VMX_FEATURE_NAMES=y
-CONFIG_PROCESSOR_SELECT=y
-CONFIG_CPU_SUP_INTEL=y
-CONFIG_CPU_SUP_AMD=y
-CONFIG_CPU_SUP_HYGON=y
-CONFIG_CPU_SUP_CENTAUR=y
-CONFIG_CPU_SUP_ZHAOXIN=y
-CONFIG_HPET_TIMER=y
-CONFIG_HPET_EMULATE_RTC=y
-CONFIG_DMI=y
-CONFIG_GART_IOMMU=y
-CONFIG_MAXSMP=y
-CONFIG_NR_CPUS_RANGE_BEGIN=8192
-CONFIG_NR_CPUS_RANGE_END=8192
-CONFIG_NR_CPUS_DEFAULT=8192
-CONFIG_NR_CPUS=8192
-CONFIG_SCHED_CLUSTER=y
-CONFIG_SCHED_SMT=y
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_MC_PRIO=y
-CONFIG_X86_LOCAL_APIC=y
-CONFIG_X86_IO_APIC=y
-CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
-CONFIG_X86_MCE=y
-# CONFIG_X86_MCELOG_LEGACY is not set
-CONFIG_X86_MCE_INTEL=y
-CONFIG_X86_MCE_AMD=y
-CONFIG_X86_MCE_THRESHOLD=y
-# CONFIG_X86_MCE_INJECT is not set
-
-#
-# Performance monitoring
-#
-CONFIG_PERF_EVENTS_INTEL_UNCORE=m
-CONFIG_PERF_EVENTS_INTEL_RAPL=m
-CONFIG_PERF_EVENTS_INTEL_CSTATE=m
-CONFIG_PERF_EVENTS_AMD_POWER=m
-CONFIG_PERF_EVENTS_AMD_UNCORE=m
-CONFIG_PERF_EVENTS_AMD_BRS=y
-# end of Performance monitoring
-
-CONFIG_X86_16BIT=y
-CONFIG_X86_ESPFIX64=y
-CONFIG_X86_VSYSCALL_EMULATION=y
-CONFIG_X86_IOPL_IOPERM=y
-CONFIG_I8K=m
-CONFIG_MICROCODE=y
-CONFIG_MICROCODE_INTEL=y
-CONFIG_MICROCODE_AMD=y
-# CONFIG_MICROCODE_LATE_LOADING is not set
-# CONFIG_MICROCODE_OLD_INTERFACE is not set
-CONFIG_X86_MSR=m
-CONFIG_X86_CPUID=m
-# CONFIG_X86_5LEVEL is not set
-CONFIG_X86_DIRECT_GBPAGES=y
-# CONFIG_X86_CPA_STATISTICS is not set
-CONFIG_AMD_MEM_ENCRYPT=y
-# CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT is not set
-CONFIG_NUMA=y
-CONFIG_AMD_NUMA=y
-CONFIG_X86_64_ACPI_NUMA=y
-# CONFIG_NUMA_EMU is not set
-CONFIG_NODES_SHIFT=10
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_MEMORY_PROBE=y
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_X86_PMEM_LEGACY_DEVICE=y
-CONFIG_X86_PMEM_LEGACY=m
-CONFIG_X86_CHECK_BIOS_CORRUPTION=y
-CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y
-CONFIG_MTRR=y
-CONFIG_MTRR_SANITIZER=y
-CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0
-CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
-CONFIG_X86_PAT=y
-CONFIG_ARCH_USES_PG_UNCACHED=y
-CONFIG_ARCH_RANDOM=y
-CONFIG_X86_SMAP=y
-CONFIG_X86_UMIP=y
-CONFIG_X86_KERNEL_IBT=y
-CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y
-CONFIG_X86_INTEL_TSX_MODE_OFF=y
-# CONFIG_X86_INTEL_TSX_MODE_ON is not set
-# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set
-CONFIG_X86_SGX=y
-CONFIG_EFI=y
-CONFIG_EFI_STUB=y
-CONFIG_EFI_MIXED=y
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_250 is not set
-# CONFIG_HZ_300 is not set
-CONFIG_HZ_1000=y
-CONFIG_HZ=1000
-CONFIG_ARCH_FORCE_MAX_ORDER=12
-CONFIG_SCHED_HRTICK=y
-CONFIG_KEXEC=y
-CONFIG_KEXEC_FILE=y
-CONFIG_ARCH_HAS_KEXEC_PURGATORY=y
-# CONFIG_KEXEC_SIG is not set
-# CONFIG_CRASH_DUMP is not set
-CONFIG_KEXEC_JUMP=y
-CONFIG_PHYSICAL_START=0x1000000
-CONFIG_RELOCATABLE=y
-CONFIG_RANDOMIZE_BASE=y
-CONFIG_X86_NEED_RELOCS=y
-CONFIG_PHYSICAL_ALIGN=0x1000000
-CONFIG_DYNAMIC_MEMORY_LAYOUT=y
-CONFIG_RANDOMIZE_MEMORY=y
-CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa
-CONFIG_HOTPLUG_CPU=y
-CONFIG_BOOTPARAM_HOTPLUG_CPU0=y
-# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
-# CONFIG_COMPAT_VDSO is not set
-# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
-# CONFIG_LEGACY_VSYSCALL_EMULATE is not set
-CONFIG_LEGACY_VSYSCALL_XONLY=y
-# CONFIG_LEGACY_VSYSCALL_NONE is not set
-# CONFIG_CMDLINE_BOOL is not set
-CONFIG_MODIFY_LDT_SYSCALL=y
-# CONFIG_STRICT_SIGALTSTACK_SIZE is not set
-CONFIG_HAVE_LIVEPATCH=y
-CONFIG_LIVEPATCH=y
-# end of Processor type and features
-
-CONFIG_ARCH_HAS_ADD_PAGES=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_USE_PERCPU_NUMA_NODE_ID=y
-
-#
-# Power management and ACPI options
-#
-CONFIG_ARCH_HIBERNATION_HEADER=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_SUSPEND_SKIP_SYNC is not set
-CONFIG_HIBERNATE_CALLBACKS=y
-CONFIG_HIBERNATION=y
-CONFIG_HIBERNATION_SNAPSHOT_DEV=y
-CONFIG_PM_STD_PARTITION=""
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_PM_AUTOSLEEP=y
-CONFIG_PM_WAKELOCKS=y
-CONFIG_PM_WAKELOCKS_LIMIT=100
-CONFIG_PM_WAKELOCKS_GC=y
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_ENERGY_MODEL=y
-CONFIG_ARCH_SUPPORTS_ACPI=y
-CONFIG_ACPI=y
-CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
-CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
-CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
-# CONFIG_ACPI_DEBUGGER is not set
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_FPDT=y
-CONFIG_ACPI_LPIT=y
-CONFIG_ACPI_SLEEP=y
-CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
-# CONFIG_ACPI_EC_DEBUGFS is not set
-CONFIG_ACPI_AC=m
-CONFIG_ACPI_BATTERY=m
+CONFIG_842_COMPRESS=y
+CONFIG_842_DECOMPRESS=y
+CONFIG_88PM886_GPADC=m
+CONFIG_ABP060MG=m
+CONFIG_AC97_BUS=m
+CONFIG_ACERHDF=m
+CONFIG_ACER_WIRELESS=m
+CONFIG_ACER_WMI=m
+CONFIG_ACORN_PARTITION_ADFS=y
+CONFIG_ACORN_PARTITION_CUMANA=y
+CONFIG_ACORN_PARTITION_EESOX=y
+CONFIG_ACORN_PARTITION_ICS=y
+CONFIG_ACORN_PARTITION_POWERTEC=y
+CONFIG_ACORN_PARTITION_RISCIX=y
+CONFIG_ACORN_PARTITION=y
+CONFIG_ACPI_AC=m
+CONFIG_ACPI_ADXL=y
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_PCIEAER=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_BATTERY=m
+CONFIG_ACPI_BGRT=y
 CONFIG_ACPI_BUTTON=m
-CONFIG_ACPI_VIDEO=m
-CONFIG_ACPI_TINY_POWER_BUTTON=m
-CONFIG_ACPI_TINY_POWER_BUTTON_SIGNAL=38
-CONFIG_ACPI_VIDEO=m
-CONFIG_ACPI_FAN=m
-CONFIG_ACPI_TAD=m
-CONFIG_ACPI_DOCK=y
-CONFIG_ACPI_CPU_FREQ_PSS=y
-CONFIG_ACPI_PROCESSOR_CSTATE=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_CMPC=m
+CONFIG_ACPI_CONFIGFS=m
+CONFIG_ACPI_CONTAINER=y
 CONFIG_ACPI_CPPC_LIB=y
-CONFIG_ACPI_PROCESSOR=y
-CONFIG_ACPI_IPMI=m
+CONFIG_ACPI_CPU_FREQ_PSS=y
+CONFIG_ACPI_DOCK=y
+CONFIG_ACPI_DPTF=y
+CONFIG_ACPI_EXTLOG=m
+CONFIG_ACPI_FAN=m
+CONFIG_ACPI_FFH=y
+CONFIG_ACPI_FPDT=y
+CONFIG_ACPI_HED=y
+CONFIG_ACPI_HMAT=y
 CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_PROCESSOR_AGGREGATOR=m
-CONFIG_ACPI_THERMAL=m
-CONFIG_ACPI_PLATFORM_PROFILE=m
-CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
-CONFIG_ACPI_TABLE_UPGRADE=y
-# CONFIG_ACPI_DEBUG is not set
-CONFIG_ACPI_PCI_SLOT=y
-CONFIG_ACPI_CONTAINER=y
-CONFIG_ACPI_HOTPLUG_MEMORY=y
 CONFIG_ACPI_HOTPLUG_IOAPIC=y
-CONFIG_ACPI_SBS=m
-CONFIG_ACPI_HED=y
-# CONFIG_ACPI_CUSTOM_METHOD is not set
-CONFIG_ACPI_BGRT=y
-# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
+CONFIG_ACPI_HOTPLUG_MEMORY=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_ACPI_IPMI=m
+CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
+CONFIG_ACPI_LPIT=y
+CONFIG_ACPI_MDIO=m
 CONFIG_ACPI_NFIT=m
-# CONFIG_NFIT_SECURITY_DEBUG is not set
 CONFIG_ACPI_NUMA=y
-CONFIG_ACPI_HMAT=y
-CONFIG_HAVE_ACPI_APEI=y
-CONFIG_HAVE_ACPI_APEI_NMI=y
-CONFIG_ACPI_APEI=y
-CONFIG_ACPI_APEI_GHES=y
-CONFIG_ACPI_APEI_PCIEAER=y
-CONFIG_ACPI_APEI_MEMORY_FAILURE=y
-# CONFIG_ACPI_APEI_EINJ is not set
-# CONFIG_ACPI_APEI_ERST_DEBUG is not set
-CONFIG_ACPI_DPTF=y
-CONFIG_DPTF_POWER=m
-CONFIG_DPTF_PCH_FIVR=m
-CONFIG_ACPI_WATCHDOG=y
-CONFIG_ACPI_EXTLOG=m
-CONFIG_ACPI_ADXL=y
-CONFIG_ACPI_CONFIGFS=m
-CONFIG_ACPI_PFRUT=m
 CONFIG_ACPI_PCC=y
+CONFIG_ACPI_PCI_SLOT=y
+CONFIG_ACPI_PFRUT=m
+CONFIG_ACPI_PLATFORM_PROFILE=m
 CONFIG_ACPI_PRMT=y
-CONFIG_PMIC_OPREGION=y
-# CONFIG_XPOWER_PMIC_OPREGION is not set
-# CONFIG_BXT_WC_PMIC_OPREGION is not set
-CONFIG_CHT_DC_TI_PMIC_OPREGION=y
-CONFIG_TPS68470_PMIC_OPREGION=y
+CONFIG_ACPI_PROCESSOR_AGGREGATOR=m
+CONFIG_ACPI_PROCESSOR_CSTATE=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_QUICKSTART=m
+CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
+CONFIG_ACPI_SBS=m
+CONFIG_ACPI_SLEEP=y
+CONFIG_ACPI_SPCR_TABLE=y
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+CONFIG_ACPI_TABLE_LIB=y
+CONFIG_ACPI_TABLE_UPGRADE=y
+CONFIG_ACPI_TAD=m
+CONFIG_ACPI_THERMAL=m
+CONFIG_ACPI_THERMAL_REL=m
+CONFIG_ACPI_TINY_POWER_BUTTON=m
+CONFIG_ACPI_TINY_POWER_BUTTON_SIGNAL=38
+CONFIG_ACPI_TOSHIBA=m
+CONFIG_ACPI_VIDEO=m
 CONFIG_ACPI_VIOT=y
-CONFIG_X86_PM_TIMER=y
-CONFIG_ACPI_PRMT=y
-
-#
-# CPU Frequency scaling
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-
-#
-# CPU frequency scaling drivers
-#
-CONFIG_X86_INTEL_PSTATE=y
-CONFIG_X86_PCC_CPUFREQ=m
-CONFIG_X86_AMD_PSTATE=y
-CONFIG_X86_AMD_PSTATE_UT=m
-CONFIG_X86_ACPI_CPUFREQ=m
-CONFIG_X86_ACPI_CPUFREQ_CPB=y
-CONFIG_X86_POWERNOW_K8=m
-CONFIG_X86_AMD_FREQ_SENSITIVITY=m
-# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
-# CONFIG_X86_P4_CLOCKMOD is not set
-
-#
-# shared options
-#
-# end of CPU Frequency scaling
-
-#
-# CPU Idle
-#
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-# CONFIG_CPU_IDLE_GOV_TEO is not set
-# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set
-CONFIG_HALTPOLL_CPUIDLE=y
-# end of CPU Idle
-
-CONFIG_INTEL_IDLE=y
-# end of Power management and ACPI options
-
-#
-# Bus options (PCI etc.)
-#
-CONFIG_PCI_DIRECT=y
-CONFIG_PCI_MMCONFIG=y
-CONFIG_MMCONF_FAM10H=y
-# CONFIG_PCI_CNB20LE_QUIRK is not set
-# CONFIG_ISA_BUS is not set
-CONFIG_ISA_DMA_API=y
-CONFIG_AMD_NB=y
-# end of Bus options (PCI etc.)
-
-#
-# Binary Emulations
-#
-CONFIG_IA32_EMULATION=y
-CONFIG_X86_X32_ABI=y
-# CONFIG_X86_X32 is not set
-CONFIG_COMPAT_32=y
-CONFIG_COMPAT=y
-CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
-CONFIG_SYSVIPC_COMPAT=y
-# end of Binary Emulations
-
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_KVM_IRQCHIP=y
-CONFIG_HAVE_KVM_IRQFD=y
-CONFIG_HAVE_KVM_IRQ_ROUTING=y
-CONFIG_HAVE_KVM_EVENTFD=y
-CONFIG_KVM_MMIO=y
-CONFIG_KVM_ASYNC_PF=y
-CONFIG_HAVE_KVM_MSI=y
-CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
-CONFIG_KVM_VFIO=y
-CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
-CONFIG_KVM_COMPAT=y
-CONFIG_HAVE_KVM_IRQ_BYPASS=y
-CONFIG_HAVE_KVM_NO_POLL=y
-CONFIG_KVM_XFER_TO_GUEST_WORK=y
-CONFIG_HAVE_KVM_PM_NOTIFIER=y
-CONFIG_VIRTUALIZATION=y
-CONFIG_KVM=m
-CONFIG_KVM_WERROR=y
-CONFIG_KVM_INTEL=m
-CONFIG_X86_SGX_KVM=y
-CONFIG_KVM_AMD=m
-CONFIG_KVM_AMD_SEV=y
-CONFIG_KVM_XEN=y
-# CONFIG_KVM_MMU_AUDIT is not set
-CONFIG_KVM_EXTERNAL_WRITE_TRACKING=y
-CONFIG_AS_AVX512=y
-CONFIG_AS_SHA1_NI=y
-CONFIG_AS_SHA256_NI=y
-CONFIG_AS_TPAUSE=y
-
-#
-# General architecture-dependent options
-#
-CONFIG_CRASH_CORE=y
-CONFIG_KEXEC_CORE=y
-CONFIG_HOTPLUG_SMT=y
-CONFIG_GENERIC_ENTRY=y
-CONFIG_KPROBES=y
-CONFIG_JUMP_LABEL=y
-# CONFIG_STATIC_KEYS_SELFTEST is not set
-# CONFIG_STATIC_CALL_SELFTEST is not set
-CONFIG_OPTPROBES=y
-CONFIG_KPROBES_ON_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_KRETPROBES=y
-CONFIG_USER_RETURN_NOTIFIER=y
-CONFIG_HAVE_IOREMAP_PROT=y
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_KPROBES_ON_FTRACE=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
-CONFIG_HAVE_NMI=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
-CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
-CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_HAVE_ASM_MODVERSIONS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
-CONFIG_HAVE_USER_RETURN_NOTIFIER=y
-CONFIG_HAVE_PERF_EVENTS_NMI=y
-CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
-CONFIG_MMU_GATHER_TABLE_FREE=y
-CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
-CONFIG_HAVE_CMPXCHG_LOCAL=y
-CONFIG_HAVE_CMPXCHG_DOUBLE=y
-CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y
-CONFIG_HAVE_ARCH_SECCOMP=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_SECCOMP=y
-CONFIG_SECCOMP_FILTER=y
-# CONFIG_SECCOMP_CACHE_DEBUG is not set
-CONFIG_HAVE_ARCH_STACKLEAK=y
-CONFIG_HAVE_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR_STRONG=y
-CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
-CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
-CONFIG_LTO_NONE=y
-CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MOVE_PUD=y
-CONFIG_HAVE_MOVE_PMD=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y
-CONFIG_HAVE_ARCH_HUGE_VMAP=y
-CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
-CONFIG_HAVE_ARCH_SOFT_DIRTY=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
-CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
-CONFIG_HAVE_EXIT_THREAD=y
-CONFIG_ARCH_MMAP_RND_BITS=28
-CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8
-CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_HAVE_STACK_VALIDATION=y
-CONFIG_HAVE_RELIABLE_STACKTRACE=y
-CONFIG_ISA_BUS_API=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_COMPAT_OLD_SIGACTION=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_HAVE_ARCH_VMAP_STACK=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET=y
-CONFIG_VMAP_STACK=y
-CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_STRICT_MODULE_RWX=y
-CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
-CONFIG_ARCH_USE_MEMREMAP_PROT=y
-# CONFIG_LOCK_EVENT_COUNTS is not set
-CONFIG_ARCH_HAS_MEM_ENCRYPT=y
-CONFIG_ARCH_HAS_CC_PLATFORM=y
-CONFIG_HAVE_STATIC_CALL=y
-CONFIG_HAVE_STATIC_CALL_INLINE=y
-CONFIG_HAVE_PREEMPT_DYNAMIC=y
-CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
-# CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC is not set
-CONFIG_ARCH_HAS_ELFCORE_COMPAT=y
-CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y
-CONFIG_DYNAMIC_SIGFRAME=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-# end of GCOV-based kernel profiling
-
-CONFIG_HAVE_GCC_PLUGINS=y
-CONFIG_GCC_PLUGINS=y
-# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
-# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
-# end of General architecture-dependent options
-CONFIG_RANDSTRUCT_NONE=y
-# CONFIG_RANDSTRUCT_FULL is not set
-# CONFIG_RANDSTRUCT_PERFORMANCE is not set
-
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULE_SIG_FORMAT=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_ASM_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_MODULE_SIG=y
-# CONFIG_MODULE_SIG_FORCE is not set
-# CONFIG_MODULE_SIG_ALL is not set
-CONFIG_MODULE_SIG_SHA1=y
-# CONFIG_MODULE_SIG_SHA224 is not set
-# CONFIG_MODULE_SIG_SHA256 is not set
-# CONFIG_MODULE_SIG_SHA384 is not set
-# CONFIG_MODULE_SIG_SHA512 is not set
-CONFIG_MODULE_SIG_HASH="sha1"
-CONFIG_MODULE_COMPRESS_NONE=y
-# CONFIG_MODULE_COMPRESS_GZIP is not set
-# CONFIG_MODULE_COMPRESS_XZ is not set
-# CONFIG_MODULE_COMPRESS_ZSTD is not set
-# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
-CONFIG_MODPROBE_PATH="/sbin/modprobe"
-# CONFIG_TRIM_UNUSED_KSYMS is not set
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_BLOCK=y
-# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set
-CONFIG_BLK_CGROUP_RWSTAT=y
-CONFIG_BLK_DEV_BSG_COMMON=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=m
-CONFIG_BLK_DEV_ZONED=y
-CONFIG_BLK_DEV_THROTTLING=y
-# CONFIG_BLK_DEV_THROTTLING_LOW is not set
-CONFIG_BLK_WBT=y
-CONFIG_BLK_WBT_MQ=y
-CONFIG_BLK_CGROUP_IOLATENCY=y
-# CONFIG_BLK_CGROUP_FC_APPID is not set
-# CONFIG_BLK_CGROUP_IOCOST is not set
-# CONFIG_BLK_CGROUP_IOPRIO is not set
-# CONFIG_BLK_DEBUG_FS is not set
-# CONFIG_BLK_SED_OPAL is not set
-# CONFIG_BLK_INLINE_ENCRYPTION is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_ACORN_PARTITION=y
-CONFIG_ACORN_PARTITION_CUMANA=y
-CONFIG_ACORN_PARTITION_EESOX=y
-CONFIG_ACORN_PARTITION_ICS=y
-CONFIG_ACORN_PARTITION_ADFS=y
-CONFIG_ACORN_PARTITION_POWERTEC=y
-CONFIG_ACORN_PARTITION_RISCIX=y
-CONFIG_AIX_PARTITION=y
-CONFIG_OSF_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_ATARI_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_MSDOS_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_LDM_DEBUG=y
-CONFIG_SGI_PARTITION=y
-CONFIG_ULTRIX_PARTITION=y
-CONFIG_SUN_PARTITION=y
-CONFIG_KARMA_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_SYSV68_PARTITION=y
-CONFIG_CMDLINE_PARTITION=y
-# end of Partition Types
-
-CONFIG_BLOCK_COMPAT=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_MQ_RDMA=y
-CONFIG_BLK_PM=y
-CONFIG_BLOCK_HOLDER_DEPRECATED=y
-
-#
-# IO Schedulers
-#
-CONFIG_MQ_IOSCHED_DEADLINE=y
-CONFIG_MQ_IOSCHED_KYBER=m
-CONFIG_IOSCHED_BFQ=y
-CONFIG_BFQ_GROUP_IOSCHED=y
-# CONFIG_BFQ_CGROUP_DEBUG is not set
-# end of IO Schedulers
-
-CONFIG_PREEMPT_NOTIFIERS=y
-CONFIG_PADATA=y
-CONFIG_ASN1=y
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
-CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y
-CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
-CONFIG_FREEZER=y
-
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_COMPAT_BINFMT_ELF=y
-CONFIG_ELFCORE=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_BINFMT_SCRIPT=y
-CONFIG_BINFMT_MISC=m
-CONFIG_COREDUMP=y
-# end of Executable file formats
-
-#
-# Memory Management options
-#
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_HAVE_FAST_GUP=y
-CONFIG_NUMA_KEEP_MEMINFO=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_HAVE_BOOTMEM_INFO_NODE=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_MEMORY_HOTPLUG=y
-# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set
+CONFIG_ACPI_WATCHDOG=y
+CONFIG_ACPI_WMI=m
+CONFIG_ACPI=y
+CONFIG_ACQUIRE_WDT=m
+CONFIG_AD2S1200=m
+CONFIG_AD2S1210=m
+CONFIG_AD2S90=m
+CONFIG_AD3552R=m
+CONFIG_AD4000=m
+CONFIG_AD4030=m
+CONFIG_AD4080=m
+CONFIG_AD4130=m
+CONFIG_AD4170_4=m
+CONFIG_AD4695=m
+CONFIG_AD4851=m
+CONFIG_AD5064=m
+CONFIG_AD5110=m
+CONFIG_AD525X_DPOT_I2C=m
+CONFIG_AD525X_DPOT=m
+CONFIG_AD525X_DPOT_SPI=m
+CONFIG_AD5272=m
+CONFIG_AD5360=m
+CONFIG_AD5380=m
+CONFIG_AD5421=m
+CONFIG_AD5446=m
+CONFIG_AD5449=m
+CONFIG_AD5504=m
+CONFIG_AD5592R_BASE=m
+CONFIG_AD5592R=m
+CONFIG_AD5593R=m
+CONFIG_AD5624R_SPI=m
+CONFIG_AD5686=m
+CONFIG_AD5686_SPI=m
+CONFIG_AD5696_I2C=m
+CONFIG_AD5755=m
+CONFIG_AD5758=m
+CONFIG_AD5761=m
+CONFIG_AD5764=m
+CONFIG_AD5766=m
+CONFIG_AD5770R=m
+CONFIG_AD5791=m
+CONFIG_AD5933=m
+CONFIG_AD7091R5=m
+CONFIG_AD7091R8=m
+CONFIG_AD7124=m
+CONFIG_AD7150=m
+CONFIG_AD7173=m
+CONFIG_AD7191=m
+CONFIG_AD7192=m
+CONFIG_AD7266=m
+CONFIG_AD7280=m
+CONFIG_AD7291=m
+CONFIG_AD7292=m
+CONFIG_AD7293=m
+CONFIG_AD7298=m
+CONFIG_AD7303=m
+CONFIG_AD7380=m
+CONFIG_AD7405=m
+CONFIG_AD74115=m
+CONFIG_AD74413R=m
+CONFIG_AD7476=m
+CONFIG_AD7606_IFACE_PARALLEL=m
+CONFIG_AD7606_IFACE_SPI=m
+CONFIG_AD7606=m
+CONFIG_AD7746=m
+CONFIG_AD7766=m
+CONFIG_AD7768_1=m
+CONFIG_AD7780=m
+CONFIG_AD7791=m
+CONFIG_AD7793=m
+CONFIG_AD7816=m
+CONFIG_AD7887=m
+CONFIG_AD7923=m
+CONFIG_AD7944=m
+CONFIG_AD7949=m
+CONFIG_AD799X=m
+CONFIG_AD8366=m
+CONFIG_AD8801=m
+CONFIG_AD9467=m
+CONFIG_AD9523=m
+CONFIG_AD9739A=m
+CONFIG_AD9832=m
+CONFIG_AD9834=m
+CONFIG_ADA4250=m
+CONFIG_ADDRESS_MASKING=y
+CONFIG_ADE9000=m
+CONFIG_ADF4350=m
+CONFIG_ADF4371=m
+CONFIG_ADF4377=m
+CONFIG_ADI_AXI_ADC=m
+CONFIG_ADI_AXI_DAC=m
+CONFIG_ADI_I3C_MASTER=m
+CONFIG_ADIN1100_PHY=m
+CONFIG_ADIN_PHY=m
+CONFIG_ADIS16080=m
+CONFIG_ADIS16130=m
+CONFIG_ADIS16136=m
+CONFIG_ADIS16201=m
+CONFIG_ADIS16203=m
+CONFIG_ADIS16209=m
+CONFIG_ADIS16240=m
+CONFIG_ADIS16260=m
+CONFIG_ADIS16400=m
+CONFIG_ADIS16460=m
+CONFIG_ADIS16475=m
+CONFIG_ADIS16480=m
+CONFIG_ADIS16550=m
+CONFIG_ADJD_S311=m
+CONFIG_ADM8211=m
+CONFIG_ADMFM2000=m
+CONFIG_ADMV1013=m
+CONFIG_ADMV1014=m
+CONFIG_ADMV4420=m
+CONFIG_ADMV8818=m
+CONFIG_ADRF6780=m
+CONFIG_AD_SIGMA_DELTA=m
+CONFIG_ADT7316_I2C=m
+CONFIG_ADT7316=m
+CONFIG_ADT7316_SPI=m
+CONFIG_ADUX1020=m
+CONFIG_ADVANTECH_EC_WDT=m
+CONFIG_ADVANTECH_WDT=m
+CONFIG_ADV_SWBUTTON=m
+CONFIG_ADXL313_I2C=m
+CONFIG_ADXL313=m
+CONFIG_ADXL313_SPI=m
+CONFIG_ADXL355_I2C=m
+CONFIG_ADXL355=m
+CONFIG_ADXL355_SPI=m
+CONFIG_ADXL367_I2C=m
+CONFIG_ADXL367=m
+CONFIG_ADXL367_SPI=m
+CONFIG_ADXL372_I2C=m
+CONFIG_ADXL372=m
+CONFIG_ADXL372_SPI=m
+CONFIG_ADXL380_I2C=m
+CONFIG_ADXL380_SPI=m
+CONFIG_ADXRS290=m
+CONFIG_ADXRS450=m
+CONFIG_AF8133J=m
+CONFIG_AFE4403=m
+CONFIG_AFE4404=m
+CONFIG_AF_KCM=m
+CONFIG_AF_RXRPC=m
+CONFIG_AGP_AMD64=m
+CONFIG_AGP_INTEL=m
+CONFIG_AGP=m
+CONFIG_AGP_SIS=m
+CONFIG_AGP_VIA=m
+CONFIG_AHCI_DWC=m
+CONFIG_AIC79XX_CMDS_PER_DEVICE=4
+CONFIG_AIC79XX_DEBUG_MASK=0
+CONFIG_AIC79XX_RESET_DELAY_MS=15000
+CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
+CONFIG_AIC7XXX_DEBUG_MASK=0
+CONFIG_AIC7XXX_RESET_DELAY_MS=15000
+CONFIG_AIRO_CS=m
+CONFIG_AIRO=m
+CONFIG_AIX_PARTITION=y
+CONFIG_AK09911=m
+CONFIG_AK8974=m
+CONFIG_AK8975=m
+CONFIG_AL3000A=m
+CONFIG_AL3010=m
+CONFIG_AL3320A=m
+CONFIG_ALIBABA_ENI_VDPA=m
+CONFIG_ALIENWARE_WMI_LEGACY=y
+CONFIG_ALIENWARE_WMI=m
+CONFIG_ALIENWARE_WMI_WMAX=y
+CONFIG_ALIM1535_WDT=m
+CONFIG_ALIM7101_WDT=m
+CONFIG_ALTERA_FREEZE_BRIDGE=m
+CONFIG_ALTERA_MBOX=m
+CONFIG_ALTERA_MSGDMA=m
+CONFIG_ALTERA_PR_IP_CORE=m
+CONFIG_ALTERA_STAPL=m
+CONFIG_AM2315=m
+CONFIG_AMD_AE4DMA=m
+CONFIG_AMD_ATL=m
+CONFIG_AMD_HFI=y
+CONFIG_AMD_HSMP=m
+CONFIG_AMD_IOMMU_V2=m
+CONFIG_AMD_IOMMU=y
+CONFIG_AMD_ISP_PLATFORM=m
+CONFIG_AMD_MEM_ENCRYPT=y
+CONFIG_AMD_MP2_STB=y
+CONFIG_AMD_NB=y
+CONFIG_AMD_NUMA=y
+CONFIG_AMD_PHY=m
+CONFIG_AMD_PMC=m
+CONFIG_AMD_PMF=m
+CONFIG_AMD_PTDMA=m
+CONFIG_AMD_QDMA=m
+CONFIG_AMDTEE=m
+CONFIG_AMD_WBRF=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_AMILO_RFKILL=m
+CONFIG_AMT=m
+CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
+CONFIG_ANDROID_BINDERFS=y
+CONFIG_ANDROID_BINDER_IPC=m
+CONFIG_AOSONG_AGS02MA=m
+CONFIG_APDS9160=m
+CONFIG_APDS9300=m
+CONFIG_APDS9306=m
+CONFIG_APDS9802ALS=m
+CONFIG_APDS9960=m
+CONFIG_APERTURE_HELPERS=y
+CONFIG_APPLE_GMUX=m
+CONFIG_APPLE_MFI_FASTCHARGE=m
+CONFIG_APPLE_PROPERTIES=y
+CONFIG_APPLICOM=m
+CONFIG_AQUANTIA_PHY=m
+CONFIG_AR5523=m
+CONFIG_ARCH_CLOCKSOURCE_INIT=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_ARCH_CPUIDLE_HALTPOLL=y
+CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
 CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-CONFIG_MEMORY_HOTREMOVE=y
-CONFIG_MHP_MEMMAP_ON_MEMORY=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
-CONFIG_MEMORY_BALLOON=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_COMPACTION=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_MIGRATION=y
-CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
 CONFIG_ARCH_ENABLE_THP_MIGRATION=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_VIRT_TO_BUS=y
-CONFIG_MMU_NOTIFIER=y
-CONFIG_KSM=y
-CONFIG_UKSM=y
-# CONFIG_KSM_LEGACY is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
-CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
-CONFIG_MEMORY_FAILURE=y
-# CONFIG_HWPOISON_INJECT is not set
-CONFIG_TRANSPARENT_HUGEPAGE=y
-CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
-# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_THP_SWAP=y
-CONFIG_CLEANCACHE=y
-CONFIG_FRONTSWAP=y
-CONFIG_CMA=y
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SYSFS=y
-CONFIG_CMA_AREAS=7
-# CONFIG_MEM_SOFT_DIRTY is not set
-CONFIG_ZSWAP=y
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
-CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
-CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
-# CONFIG_ZSWAP_DEFAULT_ON is not set
-CONFIG_ZPOOL=y
-CONFIG_ZBUD=y
-CONFIG_Z3FOLD=m
-CONFIG_ZSMALLOC=y
-# CONFIG_ZSMALLOC_STAT is not set
-CONFIG_GENERIC_EARLY_IOREMAP=y
-# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
-CONFIG_PAGE_IDLE_FLAG=y
-# CONFIG_IDLE_PAGE_TRACKING is not set
+CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
+CONFIG_ARCH_HAS_ADD_PAGES=y
 CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_ARCH_HAS_CC_PLATFORM=y
+CONFIG_ARCH_HAS_COPY_MC=y
+CONFIG_ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION=y
+CONFIG_ARCH_HAS_CPU_FINALIZE_INIT=y
+CONFIG_ARCH_HAS_CPU_RELAX=y
+CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
+CONFIG_ARCH_HAS_DEBUG_WX=y
+CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
+CONFIG_ARCH_HAS_ELFCORE_COMPAT=y
+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
+CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_ARCH_HAS_KEXEC_PURGATORY=y
+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
+CONFIG_ARCH_HAS_MEM_ENCRYPT=y
+CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
+CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG=y
+CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y
+CONFIG_ARCH_HAS_PKEYS=y
+CONFIG_ARCH_HAS_PMEM_API=y
 CONFIG_ARCH_HAS_PTE_DEVMAP=y
+CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y
+CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
+CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y
+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
 CONFIG_ARCH_HAS_ZONE_DMA_SET=y
-CONFIG_ZONE_DMA=y
-CONFIG_ZONE_DMA32=y
-# CONFIG_ZONE_DEVICE is not set
-CONFIG_HMM_MIRROR=y
-CONFIG_VMAP_PFN=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
+CONFIG_ARCH_HIBERNATION_HEADER=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_ARCH_MEMORY_PROBE=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS=28
+CONFIG_ARCH_MMAP_RND_BITS_MAX=32
+CONFIG_ARCH_MMAP_RND_BITS_MIN=28
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUPPORTS_ACPI=y
+CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_ARCH_SUPPORTS_INT128=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
+CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
+CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_USE_MEMREMAP_PROT=y
+CONFIG_ARCH_USE_MEMTEST=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
 CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
-CONFIG_ARCH_HAS_PKEYS=y
-# CONFIG_PERCPU_STATS is not set
-# CONFIG_GUP_TEST is not set
-# CONFIG_READ_ONLY_THP_FOR_FS is not set
-CONFIG_ARCH_HAS_PTE_SPECIAL=y
-CONFIG_MAPPING_DIRTY_HELPERS=y
-CONFIG_SECRETMEM=y
-
-#
-# Data Access Monitoring
-#
-CONFIG_DAMON=y
-CONFIG_DAMON_SYSFS=y
-CONFIG_DAMON_VADDR=y
-CONFIG_DAMON_PADDR=y
-CONFIG_DAMON_DBGFS=y
-CONFIG_DAMON_RECLAIM=y
-# end of Data Access Monitoring
-# end of Memory Management options
-
-CONFIG_NET=y
-CONFIG_WANT_COMPAT_NETLINK_MESSAGES=y
-CONFIG_COMPAT_NETLINK_MESSAGES=y
-CONFIG_NET_INGRESS=y
-CONFIG_NET_EGRESS=y
-CONFIG_NET_REDIRECT=y
-CONFIG_SKB_EXTENSIONS=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=m
-CONFIG_PACKET_DIAG=m
-CONFIG_UNIX=y
-CONFIG_UNIX_SCM=y
-CONFIG_AF_UNIX_OOB=y
-CONFIG_UNIX_DIAG=m
-CONFIG_TLS=m
-# CONFIG_TLS_DEVICE is not set
-# CONFIG_TLS_TOE is not set
-CONFIG_XFRM=y
-CONFIG_XFRM_OFFLOAD=y
-CONFIG_XFRM_ALGO=m
-CONFIG_XFRM_USER=m
-CONFIG_XFRM_USER_COMPAT=m
-CONFIG_XFRM_INTERFACE=m
-CONFIG_XFRM_SUB_POLICY=y
-CONFIG_XFRM_MIGRATE=y
-CONFIG_XFRM_STATISTICS=y
-CONFIG_XFRM_AH=m
-CONFIG_XFRM_ESP=m
-CONFIG_XFRM_IPCOMP=m
-CONFIG_NET_KEY=m
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_XFRM_ESPINTCP=y
-CONFIG_SMC=m
-CONFIG_SMC_DIAG=m
-CONFIG_XDP_SOCKETS=y
-CONFIG_XDP_SOCKETS_DIAG=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_FIB_TRIE_STATS=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-# CONFIG_IP_ROUTE_VERBOSE is not set
-CONFIG_IP_ROUTE_CLASSID=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE_DEMUX=m
-CONFIG_NET_IP_TUNNEL=m
-CONFIG_NET_IPGRE=m
-CONFIG_NET_IPGRE_BROADCAST=y
-CONFIG_IP_MROUTE_COMMON=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_NET_IPVTI=m
-CONFIG_NET_UDP_TUNNEL=m
-CONFIG_NET_FOU=m
-CONFIG_NET_FOU_IP_TUNNELS=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_ESP_OFFLOAD=m
-CONFIG_INET_ESPINTCP=y
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_TABLE_PERTURB_ORDER=16
-CONFIG_INET_XFRM_TUNNEL=m
-CONFIG_INET_TUNNEL=m
-CONFIG_INET_DIAG=m
-CONFIG_INET_TCP_DIAG=m
-CONFIG_INET_UDP_DIAG=m
-CONFIG_INET_RAW_DIAG=m
-CONFIG_INET_DIAG_DESTROY=y
-CONFIG_TCP_CONG_ADVANCED=y
-CONFIG_TCP_CONG_BIC=m
-CONFIG_TCP_CONG_CUBIC=m
-CONFIG_TCP_CONG_WESTWOOD=m
-CONFIG_TCP_CONG_HTCP=m
-CONFIG_TCP_CONG_HSTCP=m
-CONFIG_TCP_CONG_HYBLA=m
-CONFIG_TCP_CONG_VEGAS=m
-CONFIG_TCP_CONG_NV=m
-CONFIG_TCP_CONG_SCALABLE=m
-CONFIG_TCP_CONG_LP=m
-CONFIG_TCP_CONG_VENO=m
-CONFIG_TCP_CONG_YEAH=m
-CONFIG_TCP_CONG_ILLINOIS=m
-CONFIG_TCP_CONG_DCTCP=m
-# CONFIG_TCP_CONG_CDG is not set
-CONFIG_TCP_CONG_BBR=m
-CONFIG_DEFAULT_RENO=y
-CONFIG_DEFAULT_TCP_CONG="reno"
-CONFIG_TCP_MD5SIG=y
-CONFIG_IPV6=m
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_ESP_OFFLOAD=m
-# CONFIG_INET6_ESPINTCP is not set
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_IPV6_ILA=m
-CONFIG_INET6_XFRM_TUNNEL=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_IPV6_VTI=m
-CONFIG_IPV6_SIT=m
-CONFIG_IPV6_SIT_6RD=y
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_GRE=m
-CONFIG_IPV6_FOU=m
-CONFIG_IPV6_FOU_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-CONFIG_IPV6_MROUTE=y
-CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IPV6_PIMSM_V2=y
-CONFIG_IPV6_SEG6_LWTUNNEL=y
-CONFIG_IPV6_SEG6_HMAC=y
-CONFIG_IPV6_RPL_LWTUNNEL=y
-CONFIG_IPV6_IOAM6_LWTUNNEL=y
-CONFIG_MPTCP=y
-CONFIG_INET_MPTCP_DIAG=m
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NETWORK_PHY_TIMESTAMPING=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_ADVANCED=y
-CONFIG_BRIDGE_NETFILTER=m
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_INGRESS=y
-CONFIG_NETFILTER_EGRESS=y
-CONFIG_NETFILTER_SKIP_EGRESS=y
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_FAMILY_BRIDGE=y
-CONFIG_NETFILTER_FAMILY_ARP=y
-CONFIG_NETFILTER_NETLINK_HOOK=m
-CONFIG_NETFILTER_NETLINK_ACCT=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NETFILTER_NETLINK_OSF=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_LOG_SYSLOG=m
-CONFIG_NETFILTER_CONNCOUNT=m
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_ZONES=y
-CONFIG_NF_CONNTRACK_PROCFS=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CONNTRACK_TIMEOUT=y
-CONFIG_NF_CONNTRACK_TIMESTAMP=y
-CONFIG_NF_CONNTRACK_LABELS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_GRE=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_BROADCAST=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_SNMP=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NF_CT_NETLINK_TIMEOUT=m
-CONFIG_NF_CT_NETLINK_HELPER=m
-CONFIG_NETFILTER_NETLINK_GLUE_CT=y
-CONFIG_NF_NAT=m
-CONFIG_NF_NAT_AMANDA=m
-CONFIG_NF_NAT_FTP=m
-CONFIG_NF_NAT_IRC=m
-CONFIG_NF_NAT_SIP=m
-CONFIG_NF_NAT_TFTP=m
-CONFIG_NF_NAT_REDIRECT=y
-CONFIG_NF_NAT_MASQUERADE=y
-CONFIG_NETFILTER_SYNPROXY=m
-CONFIG_NF_TABLES=m
-CONFIG_NF_TABLES_INET=y
-CONFIG_NF_TABLES_NETDEV=y
-CONFIG_NFT_NUMGEN=m
-CONFIG_NFT_CT=m
-CONFIG_NFT_FLOW_OFFLOAD=m
-CONFIG_NFT_COUNTER=m
-CONFIG_NFT_CONNLIMIT=m
-CONFIG_NFT_LOG=m
-CONFIG_NFT_LIMIT=m
-CONFIG_NFT_MASQ=m
-CONFIG_NFT_REDIR=m
-CONFIG_NFT_NAT=m
-CONFIG_NFT_TUNNEL=m
-CONFIG_NFT_OBJREF=m
-CONFIG_NFT_QUEUE=m
-CONFIG_NFT_QUOTA=m
-CONFIG_NFT_REJECT=m
-CONFIG_NFT_REJECT_INET=m
-CONFIG_NFT_COMPAT=m
-CONFIG_NFT_HASH=m
-CONFIG_NFT_FIB=m
-CONFIG_NFT_FIB_INET=m
-CONFIG_NFT_XFRM=m
-CONFIG_NFT_SOCKET=m
-CONFIG_NFT_OSF=m
-CONFIG_NFT_TPROXY=m
-CONFIG_NFT_SYNPROXY=m
-CONFIG_NF_DUP_NETDEV=m
-CONFIG_NFT_DUP_NETDEV=m
-CONFIG_NFT_FWD_NETDEV=m
-CONFIG_NFT_FIB_NETDEV=m
-CONFIG_NFT_REJECT_NETDEV=m
-CONFIG_NF_FLOW_TABLE_INET=m
-CONFIG_NF_FLOW_TABLE=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XTABLES_COMPAT=y
-
-#
-# Xtables combined modules
-#
-CONFIG_NETFILTER_XT_MARK=m
-CONFIG_NETFILTER_XT_CONNMARK=m
-CONFIG_NETFILTER_XT_SET=m
-
-#
-# Xtables targets
-#
-CONFIG_NETFILTER_XT_TARGET_AUDIT=m
-CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CT=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_HL=m
-CONFIG_NETFILTER_XT_TARGET_HMARK=m
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
-CONFIG_NETFILTER_XT_TARGET_LOG=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_NAT=m
-CONFIG_NETFILTER_XT_TARGET_NETMAP=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-CONFIG_NETFILTER_XT_TARGET_RATEEST=m
-CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
-CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
-CONFIG_NETFILTER_XT_TARGET_TEE=m
-CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-CONFIG_NETFILTER_XT_TARGET_TRACE=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-
-#
-# Xtables matches
-#
-CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
-CONFIG_NETFILTER_XT_MATCH_BPF=m
-CONFIG_NETFILTER_XT_MATCH_CGROUP=m
-CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_CPU=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ECN=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_HL=m
-CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_IPVS=m
-CONFIG_NETFILTER_XT_MATCH_L2TP=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-CONFIG_NETFILTER_XT_MATCH_OSF=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-# end of Core Netfilter Configuration
-
-CONFIG_IP_SET=m
-CONFIG_IP_SET_MAX=256
-CONFIG_IP_SET_BITMAP_IP=m
-CONFIG_IP_SET_BITMAP_IPMAC=m
-CONFIG_IP_SET_BITMAP_PORT=m
-CONFIG_IP_SET_HASH_IP=m
-CONFIG_IP_SET_HASH_IPMARK=m
-CONFIG_IP_SET_HASH_IPPORT=m
-CONFIG_IP_SET_HASH_IPPORTIP=m
-CONFIG_IP_SET_HASH_IPPORTNET=m
-CONFIG_IP_SET_HASH_IPMAC=m
-CONFIG_IP_SET_HASH_MAC=m
-CONFIG_IP_SET_HASH_NETPORTNET=m
-CONFIG_IP_SET_HASH_NET=m
-CONFIG_IP_SET_HASH_NETNET=m
-CONFIG_IP_SET_HASH_NETPORT=m
-CONFIG_IP_SET_HASH_NETIFACE=m
-CONFIG_IP_SET_LIST_SET=m
-CONFIG_IP_VS=m
-CONFIG_IP_VS_IPV6=y
-# CONFIG_IP_VS_DEBUG is not set
-CONFIG_IP_VS_TAB_BITS=12
-
-#
-# IPVS transport protocol load balancing support
-#
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_AH_ESP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_PROTO_SCTP=y
-
-#
-# IPVS scheduler
-#
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_FO=m
-CONFIG_IP_VS_OVF=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_MH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_TWOS=m
-
-#
-# IPVS SH scheduler
-#
-CONFIG_IP_VS_SH_TAB_BITS=8
-
-#
-# IPVS MH scheduler
-#
-CONFIG_IP_VS_MH_TAB_INDEX=12
-
-#
-# IPVS application helper
-#
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_VS_NFCT=y
-CONFIG_IP_VS_PE_SIP=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_DEFRAG_IPV4=m
-CONFIG_NF_SOCKET_IPV4=m
-CONFIG_NF_TPROXY_IPV4=m
-CONFIG_NF_TABLES_IPV4=y
-CONFIG_NFT_REJECT_IPV4=m
-CONFIG_NFT_DUP_IPV4=m
-CONFIG_NFT_FIB_IPV4=m
-CONFIG_NF_TABLES_ARP=y
-CONFIG_NF_FLOW_TABLE_IPV4=m
-CONFIG_NF_DUP_IPV4=m
-CONFIG_NF_LOG_ARP=m
-CONFIG_NF_LOG_IPV4=m
-CONFIG_NF_REJECT_IPV4=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_NF_NAT_PPTP=m
-CONFIG_NF_NAT_H323=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_RPFILTER=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_SYNPROXY=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-# end of IP: Netfilter Configuration
-
-#
-# IPv6: Netfilter Configuration
-#
-CONFIG_NF_SOCKET_IPV6=m
-CONFIG_NF_TPROXY_IPV6=m
-CONFIG_NF_TABLES_IPV6=y
-CONFIG_NFT_REJECT_IPV6=m
-CONFIG_NFT_DUP_IPV6=m
-CONFIG_NFT_FIB_IPV6=m
-CONFIG_NF_FLOW_TABLE_IPV6=m
-CONFIG_NF_DUP_IPV6=m
-CONFIG_NF_REJECT_IPV6=m
-CONFIG_NF_LOG_IPV6=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RPFILTER=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_MATCH_SRH=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_TARGET_SYNPROXY=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_IP6_NF_NAT=m
-CONFIG_IP6_NF_TARGET_MASQUERADE=m
-CONFIG_IP6_NF_TARGET_NPT=m
-# end of IPv6: Netfilter Configuration
-
-CONFIG_NF_DEFRAG_IPV6=m
-
-#
-# DECnet: Netfilter Configuration
-#
-CONFIG_DECNET_NF_GRABULATOR=m
-# end of DECnet: Netfilter Configuration
-
-CONFIG_NF_TABLES_BRIDGE=m
-CONFIG_NFT_BRIDGE_META=m
-CONFIG_NFT_BRIDGE_REJECT=m
-CONFIG_NF_CONNTRACK_BRIDGE=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_IP6=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_BRIDGE_EBT_NFLOG=m
-# CONFIG_BPFILTER is not set
-CONFIG_IP_DCCP=m
-CONFIG_INET_DCCP_DIAG=m
-
-#
-# DCCP CCIDs Configuration
-#
-# CONFIG_IP_DCCP_CCID2_DEBUG is not set
-CONFIG_IP_DCCP_CCID3=y
-# CONFIG_IP_DCCP_CCID3_DEBUG is not set
-CONFIG_IP_DCCP_TFRC_LIB=y
-# end of DCCP CCIDs Configuration
-
-#
-# DCCP Kernel Hacking
-#
-# CONFIG_IP_DCCP_DEBUG is not set
-# end of DCCP Kernel Hacking
-
-CONFIG_IP_SCTP=m
-# CONFIG_SCTP_DBG_OBJCNT is not set
-CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
-CONFIG_SCTP_COOKIE_HMAC_MD5=y
-CONFIG_SCTP_COOKIE_HMAC_SHA1=y
-CONFIG_INET_SCTP_DIAG=m
-CONFIG_RDS=m
-CONFIG_RDS_RDMA=m
-CONFIG_RDS_TCP=m
-# CONFIG_RDS_DEBUG is not set
-CONFIG_TIPC=m
-CONFIG_TIPC_MEDIA_IB=y
-CONFIG_TIPC_MEDIA_UDP=y
-CONFIG_TIPC_CRYPTO=y
-CONFIG_TIPC_DIAG=m
-CONFIG_ATM=m
-CONFIG_ATM_CLIP=m
-# CONFIG_ATM_CLIP_NO_ICMP is not set
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-# CONFIG_ATM_BR2684_IPFILTER is not set
-CONFIG_L2TP=m
-# CONFIG_L2TP_DEBUGFS is not set
-CONFIG_L2TP_V3=y
-CONFIG_L2TP_IP=m
-CONFIG_L2TP_ETH=m
-CONFIG_STP=m
-CONFIG_GARP=m
-CONFIG_MRP=m
-CONFIG_BRIDGE=m
-CONFIG_BRIDGE_IGMP_SNOOPING=y
-CONFIG_BRIDGE_VLAN_FILTERING=y
-# CONFIG_BRIDGE_MRP is not set
-# CONFIG_BRIDGE_CFM is not set
-CONFIG_NET_DSA=m
-CONFIG_NET_DSA_TAG_AR9331=m
-CONFIG_NET_DSA_TAG_BRCM_COMMON=m
-CONFIG_NET_DSA_TAG_BRCM=m
-CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
-CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
-CONFIG_NET_DSA_TAG_HELLCREEK=m
-CONFIG_NET_DSA_TAG_GSWIP=m
-CONFIG_NET_DSA_TAG_DSA_COMMON=m
-CONFIG_NET_DSA_TAG_DSA=m
-CONFIG_NET_DSA_TAG_EDSA=m
-CONFIG_NET_DSA_TAG_MTK=m
-CONFIG_NET_DSA_TAG_KSZ=m
-CONFIG_NET_DSA_TAG_OCELOT=m
-CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
-CONFIG_NET_DSA_TAG_QCA=m
-CONFIG_NET_DSA_TAG_RTL4_A=m
-CONFIG_NET_DSA_TAG_RTL8_4=m
-CONFIG_NET_DSA_TAG_LAN9303=m
-CONFIG_NET_DSA_TAG_SJA1105=m
-CONFIG_NET_DSA_TAG_TRAILER=m
-CONFIG_NET_DSA_TAG_XRS700X=m
-CONFIG_NET_DSA_REALTEK=m
-CONFIG_NET_DSA_REALTEK_MDIO=m
-CONFIG_NET_DSA_REALTEK_RTL8365MB=m
-CONFIG_NET_DSA_REALTEK_RTL8366RB=m
-CONFIG_VLAN_8021Q=m
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_VLAN_8021Q_MVRP=y
-CONFIG_DECNET=m
-CONFIG_DECNET_ROUTER=y
-CONFIG_LLC=m
-CONFIG_LLC2=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_PHONET=m
-CONFIG_6LOWPAN=m
-# CONFIG_6LOWPAN_DEBUGFS is not set
-CONFIG_6LOWPAN_NHC=m
-CONFIG_6LOWPAN_NHC_DEST=m
-CONFIG_6LOWPAN_NHC_FRAGMENT=m
-CONFIG_6LOWPAN_NHC_HOP=m
-CONFIG_6LOWPAN_NHC_IPV6=m
-CONFIG_6LOWPAN_NHC_MOBILITY=m
-CONFIG_6LOWPAN_NHC_ROUTING=m
-CONFIG_6LOWPAN_NHC_UDP=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
-CONFIG_6LOWPAN_GHC_UDP=m
-CONFIG_6LOWPAN_GHC_ICMPV6=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
-CONFIG_IEEE802154=m
-CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
-CONFIG_IEEE802154_SOCKET=m
-CONFIG_IEEE802154_6LOWPAN=m
-CONFIG_MAC802154=m
-CONFIG_NET_SCHED=y
-
-#
-# Queueing/Scheduling
-#
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_MULTIQ=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFB=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_CBS=m
-CONFIG_NET_SCH_ETF=m
-CONFIG_NET_SCH_TAPRIO=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_DRR=m
-CONFIG_NET_SCH_MQPRIO=m
-CONFIG_NET_SCH_SKBPRIO=m
-CONFIG_NET_SCH_CHOKE=m
-CONFIG_NET_SCH_QFQ=m
-CONFIG_NET_SCH_CODEL=m
-CONFIG_NET_SCH_FQ_CODEL=y
-CONFIG_NET_SCH_CAKE=m
-CONFIG_NET_SCH_FQ=m
-CONFIG_NET_SCH_HHF=m
-CONFIG_NET_SCH_PIE=m
-CONFIG_NET_SCH_FQ_PIE=m
-CONFIG_NET_SCH_INGRESS=m
-CONFIG_NET_SCH_PLUG=m
-CONFIG_NET_SCH_ETS=m
-# CONFIG_NET_SCH_DEFAULT is not set
-
-#
-# Classification
-#
-CONFIG_NET_CLS=y
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_CLS_U32_PERF=y
-CONFIG_CLS_U32_MARK=y
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_CLS_FLOW=m
-CONFIG_NET_CLS_CGROUP=m
-CONFIG_NET_CLS_BPF=m
-CONFIG_NET_CLS_FLOWER=m
-CONFIG_NET_CLS_MATCHALL=m
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_STACK=32
-CONFIG_NET_EMATCH_CMP=m
-CONFIG_NET_EMATCH_NBYTE=m
-CONFIG_NET_EMATCH_U32=m
-CONFIG_NET_EMATCH_META=m
-CONFIG_NET_EMATCH_TEXT=m
-CONFIG_NET_EMATCH_CANID=m
-CONFIG_NET_EMATCH_IPSET=m
-CONFIG_NET_EMATCH_IPT=m
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=m
-CONFIG_NET_ACT_GACT=m
-CONFIG_GACT_PROB=y
-CONFIG_NET_ACT_MIRRED=m
-CONFIG_NET_ACT_SAMPLE=m
-CONFIG_NET_ACT_IPT=m
-CONFIG_NET_ACT_NAT=m
-CONFIG_NET_ACT_PEDIT=m
-# CONFIG_NET_ACT_SIMP is not set
-CONFIG_NET_ACT_SKBEDIT=m
-CONFIG_NET_ACT_CSUM=m
-CONFIG_NET_ACT_MPLS=m
-CONFIG_NET_ACT_VLAN=m
-CONFIG_NET_ACT_BPF=m
-CONFIG_NET_ACT_CONNMARK=m
-CONFIG_NET_ACT_CTINFO=m
-CONFIG_NET_ACT_SKBMOD=m
-CONFIG_NET_ACT_IFE=m
-CONFIG_NET_ACT_TUNNEL_KEY=m
-CONFIG_NET_ACT_CT=m
-CONFIG_NET_ACT_GATE=m
-CONFIG_NET_IFE_SKBMARK=m
-CONFIG_NET_IFE_SKBPRIO=m
-CONFIG_NET_IFE_SKBTCINDEX=m
-# CONFIG_NET_TC_SKB_EXT is not set
-CONFIG_NET_SCH_FIFO=y
-CONFIG_DCB=y
-CONFIG_DNS_RESOLVER=y
-CONFIG_BATMAN_ADV=m
-# CONFIG_BATMAN_ADV_BATMAN_V is not set
-CONFIG_BATMAN_ADV_BLA=y
-CONFIG_BATMAN_ADV_DAT=y
-CONFIG_BATMAN_ADV_NC=y
-CONFIG_BATMAN_ADV_MCAST=y
-# CONFIG_BATMAN_ADV_DEBUG is not set
-# CONFIG_BATMAN_ADV_TRACING is not set
-CONFIG_OPENVSWITCH=m
-CONFIG_OPENVSWITCH_GRE=m
-CONFIG_OPENVSWITCH_VXLAN=m
-CONFIG_OPENVSWITCH_GENEVE=m
-CONFIG_VSOCKETS=m
-CONFIG_VSOCKETS_DIAG=m
-CONFIG_VSOCKETS_LOOPBACK=m
-CONFIG_VMWARE_VMCI_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS_COMMON=m
-CONFIG_HYPERV_VSOCKETS=m
-CONFIG_NETLINK_DIAG=m
-CONFIG_MPLS=y
-CONFIG_NET_MPLS_GSO=m
-CONFIG_MPLS_ROUTING=m
-CONFIG_MPLS_IPTUNNEL=m
-CONFIG_NET_NSH=m
-CONFIG_HSR=m
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_L3_MASTER_DEV=y
-CONFIG_QRTR=m
-CONFIG_QRTR_SMD=m
-CONFIG_QRTR_TUN=m
-CONFIG_QRTR_MHI=m
-# CONFIG_NET_NCSI is not set
-CONFIG_PCPU_DEV_REFCNT=y
-CONFIG_RPS=y
-CONFIG_RFS_ACCEL=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_XPS=y
-CONFIG_CGROUP_NET_PRIO=y
-CONFIG_CGROUP_NET_CLASSID=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_BQL=y
-CONFIG_BPF_STREAM_PARSER=y
-CONFIG_NET_FLOW_LIMIT=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NET_DROP_MONITOR is not set
-# end of Network testing
-# end of Networking options
-
-CONFIG_HAMRADIO=y
-
-#
-# Packet Radio protocols
-#
-CONFIG_AX25=m
-CONFIG_AX25_DAMA_SLAVE=y
-CONFIG_NETROM=m
-CONFIG_ROSE=m
-
-#
-# AX.25 network device drivers
-#
-CONFIG_MKISS=m
-CONFIG_6PACK=m
-CONFIG_BPQETHER=m
-CONFIG_BAYCOM_SER_FDX=m
-CONFIG_BAYCOM_SER_HDX=m
-CONFIG_BAYCOM_PAR=m
-CONFIG_YAM=m
-# end of AX.25 network device drivers
-
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_GW=m
-CONFIG_CAN_J1939=m
-CONFIG_CAN_ISOTP=m
-
-#
-# CAN Device Drivers
-#
-CONFIG_CAN_VCAN=m
-CONFIG_CAN_VXCAN=m
-CONFIG_CAN_SLCAN=m
-CONFIG_CAN_DEV=m
-CONFIG_CAN_CALC_BITTIMING=y
-CONFIG_CAN_JANZ_ICAN3=m
-CONFIG_CAN_KVASER_PCIEFD=m
-CONFIG_CAN_C_CAN=m
-CONFIG_CAN_C_CAN_PLATFORM=m
-CONFIG_CAN_C_CAN_PCI=m
-CONFIG_CAN_CC770=m
-CONFIG_CAN_CC770_ISA=m
-CONFIG_CAN_CC770_PLATFORM=m
-CONFIG_CAN_IFI_CANFD=m
-CONFIG_CAN_M_CAN=m
-CONFIG_CAN_M_CAN_PCI=m
-CONFIG_CAN_M_CAN_PLATFORM=m
-CONFIG_CAN_M_CAN_TCAN4X5X=m
-CONFIG_CAN_PEAK_PCIEFD=m
-CONFIG_CAN_SJA1000=m
-CONFIG_CAN_EMS_PCI=m
-CONFIG_CAN_EMS_PCMCIA=m
-CONFIG_CAN_F81601=m
-CONFIG_CAN_KVASER_PCI=m
-CONFIG_CAN_PEAK_PCI=m
-CONFIG_CAN_PEAK_PCIEC=y
-CONFIG_CAN_PEAK_PCMCIA=m
-CONFIG_CAN_PLX_PCI=m
-CONFIG_CAN_SJA1000_ISA=m
-CONFIG_CAN_SJA1000_PLATFORM=m
-CONFIG_CAN_SOFTING=m
-CONFIG_CAN_SOFTING_CS=m
-
-#
-# CAN SPI interfaces
-#
-CONFIG_CAN_HI311X=m
-CONFIG_CAN_MCP251X=m
-CONFIG_CAN_MCP251XFD=m
-# CONFIG_CAN_MCP251XFD_SANITY is not set
-# end of CAN SPI interfaces
-
-#
-# CAN USB interfaces
-#
-CONFIG_CAN_8DEV_USB=m
-CONFIG_CAN_EMS_USB=m
-CONFIG_CAN_ESD_USB2=m
-CONFIG_CAN_ETAS_ES58X=m
-CONFIG_CAN_GS_USB=m
-CONFIG_CAN_KVASER_USB=m
-CONFIG_CAN_MCBA_USB=m
-CONFIG_CAN_PEAK_USB=m
-CONFIG_CAN_UCAN=m
-# end of CAN USB interfaces
-
-# CONFIG_CAN_DEBUG_DEVICES is not set
-# end of CAN Device Drivers
-
-CONFIG_BT=m
-CONFIG_BT_BREDR=y
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_CMTP=m
-CONFIG_BT_HIDP=m
-CONFIG_BT_HS=y
-CONFIG_BT_LE=y
-CONFIG_BT_6LOWPAN=m
-CONFIG_BT_LEDS=y
-CONFIG_BT_MSFTEXT=y
-CONFIG_BT_AOSPEXT=y
-CONFIG_BT_DEBUGFS=y
-# CONFIG_BT_SELFTEST is not set
-# CONFIG_BT_FEATURE_DEBUG is not set
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_INTEL=m
-CONFIG_BT_BCM=m
-CONFIG_BT_RTL=m
-CONFIG_BT_QCA=m
-CONFIG_BT_HCIBTUSB=m
-# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
-CONFIG_BT_HCIBTUSB_BCM=y
-CONFIG_BT_HCIBTUSB_MTK=y
-CONFIG_BT_HCIBTUSB_RTL=y
-CONFIG_BT_HCIBTSDIO=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_SERDEV=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_NOKIA=m
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_ATH3K=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIUART_3WIRE=y
-CONFIG_BT_HCIUART_INTEL=y
-CONFIG_BT_HCIUART_RTL=y
-CONFIG_BT_HCIUART_QCA=y
-CONFIG_BT_HCIUART_AG6XX=y
-CONFIG_BT_HCIUART_MRVL=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIDTL1=m
-CONFIG_BT_HCIBT3C=m
-CONFIG_BT_HCIBLUECARD=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_BT_MRVL=m
-CONFIG_BT_MRVL_SDIO=m
-CONFIG_BT_ATH3K=m
-CONFIG_BT_MTKSDIO=m
-CONFIG_BT_MTKUART=m
-CONFIG_BT_HCIRSI=m
-CONFIG_BT_VIRTIO=m
-# end of Bluetooth device drivers
-
-CONFIG_AF_RXRPC=m
-CONFIG_AF_RXRPC_IPV6=y
-# CONFIG_AF_RXRPC_INJECT_LOSS is not set
-# CONFIG_AF_RXRPC_DEBUG is not set
-# CONFIG_RXKAD is not set
-CONFIG_AF_KCM=m
-CONFIG_STREAM_PARSER=y
-CONFIG_MCTP=y
-CONFIG_FIB_RULES=y
-CONFIG_WIRELESS=y
-CONFIG_WIRELESS_EXT=y
-# CONFIG_WEXT_CORE is not set
-# CONFIG_WEXT_PROC is not set
-# CONFIG_WEXT_SPY is not set
-# CONFIG_WEXT_PRIV is not set
-CONFIG_CFG80211=m
-CONFIG_NL80211_TESTMODE=y
-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
-CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
-CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
-CONFIG_CFG80211_DEFAULT_PS=y
-# CONFIG_CFG80211_DEBUGFS is not set
-CONFIG_CFG80211_CRDA_SUPPORT=y
-# CONFIG_CFG80211_WEXT is not set
-# CONFIG_CFG80211_WEXT_EXPORT is not set
-CONFIG_LIB80211=m
-CONFIG_LIB80211_CRYPT_WEP=m
-CONFIG_LIB80211_CRYPT_CCMP=m
-CONFIG_LIB80211_CRYPT_TKIP=m
-# CONFIG_LIB80211_DEBUG is not set
-CONFIG_MAC80211=m
-CONFIG_MAC80211_HAS_RC=y
-CONFIG_MAC80211_RC_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
-CONFIG_MAC80211_MESH=y
-CONFIG_MAC80211_LEDS=y
-# CONFIG_MAC80211_DEBUGFS is not set
-# CONFIG_MAC80211_MESSAGE_TRACING is not set
-# CONFIG_MAC80211_DEBUG_MENU is not set
-CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
-CONFIG_RFKILL=m
-CONFIG_RFKILL_LEDS=y
-CONFIG_RFKILL_INPUT=y
-CONFIG_RFKILL_GPIO=m
-CONFIG_NET_9P=m
-CONFIG_NET_9P_VIRTIO=m
-CONFIG_NET_9P_RDMA=m
-# CONFIG_NET_9P_DEBUG is not set
-CONFIG_CAIF=m
-# CONFIG_CAIF_DEBUG is not set
-CONFIG_CAIF_NETDEV=m
-CONFIG_CAIF_USB=m
-CONFIG_CEPH_LIB=m
-# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
-CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
-CONFIG_NFC=m
-CONFIG_NFC_DIGITAL=m
-CONFIG_NFC_NCI=m
-CONFIG_NFC_NCI_SPI=m
-CONFIG_NFC_NCI_UART=m
-CONFIG_NFC_HCI=m
-CONFIG_NFC_SHDLC=y
-
-#
-# Near Field Communication (NFC) devices
-#
-CONFIG_NFC_TRF7970A=m
-CONFIG_NFC_MEI_PHY=m
-CONFIG_NFC_SIM=m
-CONFIG_NFC_PORT100=m
-CONFIG_NFC_VIRTUAL_NCI=m
-CONFIG_NFC_FDP=m
-CONFIG_NFC_FDP_I2C=m
-CONFIG_NFC_PN544=m
-CONFIG_NFC_PN544_I2C=m
-CONFIG_NFC_PN544_MEI=m
-CONFIG_NFC_PN533=m
-CONFIG_NFC_PN533_USB=m
-CONFIG_NFC_PN533_I2C=m
-CONFIG_NFC_PN532_UART=m
-CONFIG_NFC_MICROREAD=m
-CONFIG_NFC_MICROREAD_I2C=m
-CONFIG_NFC_MICROREAD_MEI=m
-CONFIG_NFC_MRVL=m
-CONFIG_NFC_MRVL_USB=m
-CONFIG_NFC_MRVL_UART=m
-CONFIG_NFC_MRVL_I2C=m
-CONFIG_NFC_MRVL_SPI=m
-CONFIG_NFC_ST21NFCA=m
-CONFIG_NFC_ST21NFCA_I2C=m
-CONFIG_NFC_ST_NCI=m
-CONFIG_NFC_ST_NCI_I2C=m
-CONFIG_NFC_ST_NCI_SPI=m
-CONFIG_NFC_NXP_NCI=m
-CONFIG_NFC_NXP_NCI_I2C=m
-CONFIG_NFC_S3FWRN5=m
-CONFIG_NFC_S3FWRN5_I2C=m
-CONFIG_NFC_S3FWRN82_UART=m
-CONFIG_NFC_ST95HF=m
-# end of Near Field Communication (NFC) devices
-
-CONFIG_PSAMPLE=m
-CONFIG_NET_IFE=m
-CONFIG_LWTUNNEL=y
-CONFIG_LWTUNNEL_BPF=y
-# CONFIG_PAGE_POOL_STATS is not set
-CONFIG_DST_CACHE=y
-CONFIG_GRO_CELLS=y
-CONFIG_NET_SELFTESTS=m
-CONFIG_NET_SOCK_MSG=y
-CONFIG_NET_DEVLINK=y
-CONFIG_PAGE_POOL=y
-CONFIG_FAILOVER=m
-CONFIG_ETHTOOL_NETLINK=y
-
-#
-# Device Drivers
-#
-CONFIG_HAVE_EISA=y
-# CONFIG_EISA is not set
-CONFIG_HAVE_PCI=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_HOTPLUG_PCI_PCIE=y
-CONFIG_PCIEAER=y
-# CONFIG_PCIEAER_INJECT is not set
-CONFIG_PCIE_ECRC=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-CONFIG_PCIE_PME=y
-CONFIG_PCIE_DPC=y
-CONFIG_PCIE_PTM=y
-CONFIG_PCIE_EDR=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_QUIRKS=y
-# CONFIG_PCI_DEBUG is not set
-CONFIG_PCI_REALLOC_ENABLE_AUTO=y
-CONFIG_PCI_STUB=m
-CONFIG_PCI_PF_STUB=m
-CONFIG_PCI_ATS=y
-CONFIG_PCI_LOCKLESS_CONFIG=y
-CONFIG_PCI_IOV=y
-CONFIG_PCI_PRI=y
-CONFIG_PCI_PASID=y
-CONFIG_PCI_LABEL=y
-CONFIG_PCI_HYPERV=m
-# CONFIG_PCIE_BUS_TUNE_OFF is not set
-CONFIG_PCIE_BUS_DEFAULT=y
-# CONFIG_PCIE_BUS_SAFE is not set
-# CONFIG_PCIE_BUS_PERFORMANCE is not set
-# CONFIG_PCIE_BUS_PEER2PEER is not set
-CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_ACPI=y
-CONFIG_HOTPLUG_PCI_ACPI_IBM=m
-CONFIG_HOTPLUG_PCI_CPCI=y
-CONFIG_HOTPLUG_PCI_CPCI_ZT5550=m
-CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m
-CONFIG_HOTPLUG_PCI_SHPC=y
-
-#
-# PCI controller drivers
-#
-CONFIG_VMD=m
-CONFIG_PCI_HYPERV_INTERFACE=m
-
-#
-# DesignWare PCI Core Support
-#
-# CONFIG_PCIE_DW_PLAT_HOST is not set
-# CONFIG_PCIE_DW_PLAT_EP is not set
-# CONFIG_PCI_MESON is not set
-# end of DesignWare PCI Core Support
-
-#
-# Mobiveil PCIe Core Support
-#
-# end of Mobiveil PCIe Core Support
-
-#
-# Cadence PCIe controllers support
-#
-# end of Cadence PCIe controllers support
-# end of PCI controller drivers
-
-#
-# PCI Endpoint
-#
-CONFIG_PCI_ENDPOINT=y
-CONFIG_PCI_ENDPOINT_CONFIGFS=y
-# CONFIG_PCI_EPF_TEST is not set
-CONFIG_PCI_EPF_NTB=m
-# end of PCI Endpoint
-
-#
-# PCI switch controller drivers
-#
-CONFIG_PCI_SW_SWITCHTEC=m
-# end of PCI switch controller drivers
-
-CONFIG_CXL_BUS=m
-CONFIG_CXL_PCI=m
-CONFIG_CXL_MEM=m
-CONFIG_CXL_MEM_RAW_COMMANDS=y
-CONFIG_CXL_ACPI=m
-CONFIG_CXL_PMEM=m
-CONFIG_PCCARD=m
-CONFIG_PCMCIA=m
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_CARDBUS=y
-
-#
-# PC-card bridges
-#
-CONFIG_YENTA=m
-CONFIG_YENTA_O2=y
-CONFIG_YENTA_RICOH=y
-CONFIG_YENTA_TI=y
-CONFIG_YENTA_ENE_TUNE=y
-CONFIG_YENTA_TOSHIBA=y
-CONFIG_PD6729=m
-CONFIG_I82092=m
-CONFIG_PCCARD_NONSTATIC=y
-CONFIG_RAPIDIO=m
-CONFIG_RAPIDIO_TSI721=m
-CONFIG_RAPIDIO_DISC_TIMEOUT=30
-CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y
-CONFIG_RAPIDIO_DMA_ENGINE=y
-# CONFIG_RAPIDIO_DEBUG is not set
-CONFIG_RAPIDIO_ENUM_BASIC=m
-CONFIG_RAPIDIO_CHMAN=m
-CONFIG_RAPIDIO_MPORT_CDEV=m
-
-#
-# RapidIO Switch drivers
-#
-CONFIG_RAPIDIO_TSI57X=m
-CONFIG_RAPIDIO_CPS_XX=m
-CONFIG_RAPIDIO_TSI568=m
-CONFIG_RAPIDIO_CPS_GEN2=m
-CONFIG_RAPIDIO_RXS_GEN3=m
-# end of RapidIO Switch drivers
-
-#
-# Generic Driver Options
-#
-CONFIG_AUXILIARY_BUS=y
-# CONFIG_UEVENT_HELPER is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-
-#
-# Firmware loader
-#
-CONFIG_FW_LOADER=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_FW_LOADER_USER_HELPER is not set
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_FW_LOADER_COMPRESS=y
-CONFIG_FW_CACHE=y
-# end of Firmware loader
-
-CONFIG_WANT_DEV_COREDUMP=y
-CONFIG_ALLOW_DEV_COREDUMP=y
-CONFIG_DEV_COREDUMP=y
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
-CONFIG_HMEM_REPORTING=y
-CONFIG_TEST_ASYNC_DRIVER_PROBE=m
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=m
-CONFIG_REGMAP_SLIMBUS=m
-CONFIG_REGMAP_SPI=y
-CONFIG_REGMAP_SPMI=m
-CONFIG_REGMAP_W1=m
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_SOUNDWIRE=m
-CONFIG_REGMAP_SOUNDWIRE_MBQ=m
-CONFIG_REGMAP_SCCB=m
-CONFIG_REGMAP_I3C=m
-CONFIG_REGMAP_SPI_AVMM=m
-CONFIG_DMA_SHARED_BUFFER=y
-# CONFIG_DMA_FENCE_TRACE is not set
-# end of Generic Driver Options
-
-#
-# Bus devices
-#
-CONFIG_MHI_BUS=m
-# CONFIG_MHI_BUS_DEBUG is not set
-CONFIG_MHI_BUS_PCI_GENERIC=m
-# end of Bus devices
-
-CONFIG_CONNECTOR=m
-
-#
-# Firmware Drivers
-#
-
-#
-# ARM System Control and Management Interface Protocol
-#
-# end of ARM System Control and Management Interface Protocol
-
-CONFIG_EDD=m
-# CONFIG_EDD_OFF is not set
-CONFIG_FIRMWARE_MEMMAP=y
-CONFIG_DMIID=y
-CONFIG_DMI_SYSFS=m
-CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
-CONFIG_ISCSI_IBFT_FIND=y
-CONFIG_ISCSI_IBFT=m
-CONFIG_FW_CFG_SYSFS=m
-# CONFIG_FW_CFG_SYSFS_CMDLINE is not set
-CONFIG_SYSFB=y
-CONFIG_SYSFB_SIMPLEFB=y
-CONFIG_CS_DSP=m
-CONFIG_GOOGLE_FIRMWARE=y
-CONFIG_GOOGLE_SMI=m
-CONFIG_GOOGLE_COREBOOT_TABLE=m
-CONFIG_GOOGLE_MEMCONSOLE=m
-CONFIG_GOOGLE_MEMCONSOLE_X86_LEGACY=m
-CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m
-CONFIG_GOOGLE_VPD=m
-
-#
-# EFI (Extensible Firmware Interface) Support
-#
-CONFIG_EFI_VARS=m
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_VARS_PSTORE=m
-CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
-CONFIG_EFI_RUNTIME_MAP=y
-# CONFIG_EFI_FAKE_MEMMAP is not set
-CONFIG_EFI_SOFT_RESERVE=y
-CONFIG_EFI_ZBOOT=y
-# CONFIG_EFI_ZBOOT_SIGNING is not set
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
-CONFIG_EFI_BOOTLOADER_CONTROL=m
-CONFIG_EFI_CAPSULE_LOADER=m
-CONFIG_EFI_TEST=m
-CONFIG_APPLE_PROPERTIES=y
-CONFIG_RESET_ATTACK_MITIGATION=y
-CONFIG_EFI_RCI2_TABLE=y
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# end of EFI (Extensible Firmware Interface) Support
-
-CONFIG_UEFI_CPER=y
-CONFIG_UEFI_CPER_X86=y
-CONFIG_EFI_DEV_PATH_PARSER=y
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-
-#
-# Tegra firmware driver
-#
-# end of Tegra firmware driver
-# end of Firmware Drivers
-
-CONFIG_GNSS=m
-CONFIG_GNSS_SERIAL=m
-CONFIG_GNSS_MTK_SERIAL=m
-CONFIG_GNSS_SIRF_SERIAL=m
-CONFIG_GNSS_UBX_SERIAL=m
-CONFIG_MTD=m
-CONFIG_MTD_TESTS=m
-
-#
-# Partition parsers
-#
-CONFIG_MTD_AR7_PARTS=m
-CONFIG_MTD_CMDLINE_PARTS=m
-CONFIG_MTD_REDBOOT_PARTS=m
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-# end of Partition parsers
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
-CONFIG_MTD_BLOCK_RO=m
-
-#
-# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
-#
-CONFIG_FTL=m
-CONFIG_NFTL=m
-CONFIG_NFTL_RW=y
-CONFIG_INFTL=m
-CONFIG_RFD_FTL=m
-CONFIG_SSFDC=m
-CONFIG_SM_FTL=m
-CONFIG_MTD_OOPS=m
-CONFIG_MTD_PSTORE=m
-CONFIG_MTD_SWAP=m
-# CONFIG_MTD_PARTITIONED_MASTER is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_GEN_PROBE=m
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-CONFIG_MTD_CFI_INTELEXT=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_CFI_STAA=m
-CONFIG_MTD_CFI_UTIL=m
-CONFIG_MTD_RAM=m
-CONFIG_MTD_ROM=m
-CONFIG_MTD_ABSENT=m
-# end of RAM/ROM/Flash chip drivers
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=m
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-# CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set
-CONFIG_MTD_SBC_GXX=m
-CONFIG_MTD_AMD76XROM=m
-CONFIG_MTD_ICHXROM=m
-CONFIG_MTD_ESB2ROM=m
-CONFIG_MTD_CK804XROM=m
-CONFIG_MTD_SCB2_FLASH=m
-CONFIG_MTD_NETtel=m
-CONFIG_MTD_L440GX=m
-CONFIG_MTD_PCI=m
-CONFIG_MTD_PCMCIA=m
-# CONFIG_MTD_PCMCIA_ANONYMOUS is not set
-CONFIG_MTD_INTEL_VR_NOR=m
-CONFIG_MTD_PLATRAM=m
-# end of Mapping drivers for chip access
-
-#
-# Self-contained MTD device drivers
-#
-CONFIG_MTD_PMC551=m
-CONFIG_MTD_PMC551_BUGFIX=y
-# CONFIG_MTD_PMC551_DEBUG is not set
-CONFIG_MTD_DATAFLASH=m
-CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
-CONFIG_MTD_DATAFLASH_OTP=y
-CONFIG_MTD_MCHP23K256=m
-CONFIG_MTD_MCHP48L640=m
-CONFIG_MTD_SST25L=m
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTDRAM_TOTAL_SIZE=4096
-CONFIG_MTDRAM_ERASE_SIZE=128
-CONFIG_MTD_BLOCK2MTD=m
-
-#
-# Disk-On-Chip Device Drivers
-#
-CONFIG_MTD_DOCG3=m
-CONFIG_BCH_CONST_M=14
-CONFIG_BCH_CONST_T=4
-# end of Self-contained MTD device drivers
-
-#
-# NAND
-#
-CONFIG_MTD_NAND_CORE=m
-CONFIG_MTD_ONENAND=m
-CONFIG_MTD_ONENAND_VERIFY_WRITE=y
-CONFIG_MTD_ONENAND_GENERIC=m
-CONFIG_MTD_ONENAND_OTP=y
-CONFIG_MTD_ONENAND_2X_PROGRAM=y
-CONFIG_MTD_RAW_NAND=m
-
-#
-# Raw/parallel NAND flash controllers
-#
-CONFIG_MTD_NAND_DENALI=m
-CONFIG_MTD_NAND_DENALI_PCI=m
-CONFIG_MTD_NAND_CAFE=m
-CONFIG_MTD_NAND_MXIC=m
-CONFIG_MTD_NAND_GPIO=m
-CONFIG_MTD_NAND_PLATFORM=m
-CONFIG_MTD_NAND_ARASAN=m
-
-#
-# Misc
-#
-CONFIG_MTD_SM_COMMON=m
-CONFIG_MTD_NAND_NANDSIM=m
-CONFIG_MTD_NAND_RICOH=m
-CONFIG_MTD_NAND_DISKONCHIP=m
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
-CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
-CONFIG_MTD_SPI_NAND=m
-
-#
-# ECC engine support
-#
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
-CONFIG_MTD_NAND_ECC_SW_BCH=y
-CONFIG_MTD_NAND_ECC_MXIC=y
-# end of ECC engine support
-# end of NAND
-
-#
-# LPDDR & LPDDR2 PCM memory drivers
-#
-CONFIG_MTD_LPDDR=m
-CONFIG_MTD_QINFO_PROBE=m
-# end of LPDDR & LPDDR2 PCM memory drivers
-
-CONFIG_MTD_SPI_NOR=m
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SPI_NOR_SWP_DISABLE=y
-# CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE is not set
-# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
-CONFIG_SPI_INTEL_SPI=m
-CONFIG_SPI_INTEL_SPI_PCI=m
-CONFIG_SPI_INTEL_SPI_PLATFORM=m
-CONFIG_MTD_UBI=m
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_FASTMAP=y
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_HYPERBUS=m
-# CONFIG_OF is not set
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_PARPORT=m
-CONFIG_PARPORT_PC=m
-CONFIG_PARPORT_SERIAL=m
-CONFIG_PARPORT_PC_FIFO=y
-CONFIG_PARPORT_PC_SUPERIO=y
-CONFIG_PARPORT_PC_PCMCIA=m
-CONFIG_PARPORT_AX88796=m
-CONFIG_PARPORT_1284=y
-CONFIG_PARPORT_NOT_PC=y
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG_MESSAGES is not set
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_NULL_BLK is not set
-CONFIG_BLK_DEV_FD=m
-CONFIG_BLK_DEV_FD_RAWCMD=y
-CONFIG_CDROM=m
-# CONFIG_PARIDE is not set
-CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
-CONFIG_ZRAM=m
-# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
-CONFIG_ZRAM_DEF_COMP_ZSTD=y
-# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
-# CONFIG_ZRAM_DEF_COMP_LZO is not set
-# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
-# CONFIG_ZRAM_DEF_COMP_842 is not set
-CONFIG_ZRAM_DEF_COMP="zstd"
-CONFIG_ZRAM_WRITEBACK=y
-# CONFIG_ZRAM_MEMORY_TRACKING is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
-CONFIG_BLK_DEV_DRBD=m
-# CONFIG_DRBD_FAULT_INJECTION is not set
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_SX8=m
-CONFIG_BLK_DEV_RAM=m
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-CONFIG_CDROM_PKTCDVD_WCACHE=y
-CONFIG_ATA_OVER_ETH=m
-CONFIG_VIRTIO_BLK=m
-CONFIG_BLK_DEV_RBD=m
-CONFIG_BLK_DEV_RSXX=m
-CONFIG_BLK_DEV_RNBD=y
-CONFIG_BLK_DEV_RNBD_CLIENT=m
-CONFIG_BLK_DEV_RNBD_SERVER=m
-
-#
-# NVME Support
-#
-CONFIG_NVME_CORE=m
-CONFIG_BLK_DEV_NVME=m
-# CONFIG_NVME_MULTIPATH is not set
-CONFIG_NVME_VERBOSE_ERRORS=y
-CONFIG_NVME_HWMON=y
-CONFIG_NVME_FABRICS=m
-CONFIG_NVME_RDMA=m
-CONFIG_NVME_FC=m
-CONFIG_NVME_TCP=m
-CONFIG_NVME_TARGET=m
-CONFIG_NVME_TARGET_PASSTHRU=y
-CONFIG_NVME_TARGET_LOOP=m
-CONFIG_NVME_TARGET_RDMA=m
-CONFIG_NVME_TARGET_FC=m
-CONFIG_NVME_TARGET_FCLOOP=m
-CONFIG_NVME_TARGET_TCP=m
-# end of NVME Support
-
-#
-# Misc devices
-#
-CONFIG_SENSORS_LIS3LV02D=m
-CONFIG_AD525X_DPOT=m
-CONFIG_AD525X_DPOT_I2C=m
-CONFIG_AD525X_DPOT_SPI=m
-# CONFIG_DUMMY_IRQ is not set
-CONFIG_IBM_ASM=m
-CONFIG_PHANTOM=m
-CONFIG_TIFM_CORE=m
-CONFIG_TIFM_7XX1=m
-CONFIG_ICS932S401=m
-CONFIG_ENCLOSURE_SERVICES=m
-CONFIG_HP_ILO=m
-CONFIG_APDS9802ALS=m
-CONFIG_ISL29003=m
-CONFIG_ISL29020=m
-CONFIG_SENSORS_TSL2550=m
-CONFIG_SENSORS_BH1770=m
-CONFIG_SENSORS_APDS990X=m
-CONFIG_HMC6352=m
-CONFIG_DS1682=m
-CONFIG_VMWARE_BALLOON=m
-CONFIG_LATTICE_ECP3_CONFIG=m
-CONFIG_SRAM=y
-CONFIG_DW_XDATA_PCIE=m
-CONFIG_PCI_ENDPOINT_TEST=m
-CONFIG_XILINX_SDFEC=m
-CONFIG_MISC_RTSX=m
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-CONFIG_EEPROM_AT24=m
-CONFIG_EEPROM_AT25=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_EEPROM_MAX6875=m
-CONFIG_EEPROM_93CX6=m
-CONFIG_EEPROM_93XX46=m
-CONFIG_EEPROM_IDT_89HPESX=m
-CONFIG_EEPROM_EE1004=m
-# end of EEPROM support
-
-CONFIG_CB710_CORE=m
-# CONFIG_CB710_DEBUG is not set
-CONFIG_CB710_DEBUG_ASSUMPTIONS=y
-
-#
-# Texas Instruments shared transport line discipline
-#
-CONFIG_TI_ST=m
-# end of Texas Instruments shared transport line discipline
-
-CONFIG_SENSORS_LIS3_I2C=m
-
-#
-# Altera FPGA firmware download module (requires I2C)
-#
-CONFIG_ALTERA_STAPL=m
-CONFIG_INTEL_MEI=y
-CONFIG_INTEL_MEI_ME=y
-CONFIG_INTEL_MEI_TXE=m
-CONFIG_INTEL_MEI_HDCP=m
-CONFIG_INTEL_MEI_PXP=m
-CONFIG_VMWARE_VMCI=m
-CONFIG_GENWQE=m
-CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0
-CONFIG_ECHO=m
-CONFIG_BCM_VK=m
-CONFIG_BCM_VK_TTY=y
-CONFIG_MISC_ALCOR_PCI=m
-CONFIG_MISC_RTSX_PCI=m
-CONFIG_MISC_RTSX_USB=m
-CONFIG_HABANA_AI=m
-CONFIG_UACCE=m
-CONFIG_PVPANIC=y
-CONFIG_PVPANIC_MMIO=m
-CONFIG_PVPANIC_PCI=m
-CONFIG_GP_PCI1XXXX=m
-# end of Misc devices
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=m
-CONFIG_RAID_ATTRS=m
-CONFIG_SCSI_COMMON=m
-CONFIG_SCSI=m
-CONFIG_SCSI_DMA=y
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_BLK_DEV_BSG=y
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_ENCLOSURE=m
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_ISCSI_ATTRS=m
-CONFIG_SCSI_SAS_ATTRS=m
-CONFIG_SCSI_SAS_LIBSAS=m
-CONFIG_SCSI_SAS_ATA=y
-CONFIG_SCSI_SAS_HOST_SMP=y
-CONFIG_SCSI_SRP_ATTRS=m
-# end of SCSI Transports
-
-CONFIG_SCSI_LOWLEVEL=y
-CONFIG_ISCSI_TCP=m
-CONFIG_ISCSI_BOOT_SYSFS=m
-CONFIG_SCSI_CXGB3_ISCSI=m
-CONFIG_SCSI_CXGB4_ISCSI=m
-CONFIG_SCSI_BNX2_ISCSI=m
-CONFIG_SCSI_BNX2X_FCOE=m
-CONFIG_BE2ISCSI=m
-CONFIG_BLK_DEV_3W_XXXX_RAID=m
-CONFIG_SCSI_HPSA=m
-CONFIG_SCSI_3W_9XXX=m
-CONFIG_SCSI_3W_SAS=m
-CONFIG_SCSI_ACARD=m
-CONFIG_SCSI_AACRAID=m
-CONFIG_SCSI_AIC7XXX=m
-CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
-CONFIG_AIC7XXX_RESET_DELAY_MS=15000
-# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
-CONFIG_AIC7XXX_DEBUG_MASK=0
-# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC79XX=m
-CONFIG_AIC79XX_CMDS_PER_DEVICE=4
-CONFIG_AIC79XX_RESET_DELAY_MS=15000
-# CONFIG_AIC79XX_DEBUG_ENABLE is not set
-CONFIG_AIC79XX_DEBUG_MASK=0
-# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC94XX=m
-# CONFIG_AIC94XX_DEBUG is not set
-CONFIG_SCSI_MVSAS=m
-# CONFIG_SCSI_MVSAS_DEBUG is not set
-CONFIG_SCSI_MVSAS_TASKLET=y
-CONFIG_SCSI_MVUMI=m
-CONFIG_SCSI_DPT_I2O=m
-CONFIG_SCSI_ADVANSYS=m
-CONFIG_SCSI_ARCMSR=m
-CONFIG_SCSI_ESAS2R=m
-CONFIG_MEGARAID_NEWGEN=y
-CONFIG_MEGARAID_MM=m
-CONFIG_MEGARAID_MAILBOX=m
-CONFIG_MEGARAID_LEGACY=m
-CONFIG_MEGARAID_SAS=m
-CONFIG_SCSI_MPT3SAS=m
-CONFIG_SCSI_MPT2SAS_MAX_SGE=128
-CONFIG_SCSI_MPT3SAS_MAX_SGE=128
-CONFIG_SCSI_MPT2SAS=m
-CONFIG_SCSI_MPI3MR=m
-CONFIG_SCSI_SMARTPQI=m
-CONFIG_SCSI_UFSHCD=m
-CONFIG_SCSI_UFSHCD_PCI=m
-CONFIG_SCSI_UFS_DWC_TC_PCI=m
-CONFIG_SCSI_UFSHCD_PLATFORM=m
-CONFIG_SCSI_UFS_CDNS_PLATFORM=m
-CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m
-# CONFIG_SCSI_UFS_BSG is not set
-CONFIG_SCSI_UFS_HPB=y
-CONFIG_SCSI_UFS_HWMON=y
-CONFIG_SCSI_HPTIOP=m
-CONFIG_SCSI_BUSLOGIC=m
-CONFIG_SCSI_FLASHPOINT=y
-CONFIG_SCSI_MYRB=m
-CONFIG_SCSI_MYRS=m
-CONFIG_VMWARE_PVSCSI=m
-CONFIG_HYPERV_STORAGE=m
-CONFIG_LIBFC=m
-CONFIG_LIBFCOE=m
-CONFIG_FCOE=m
-CONFIG_FCOE_FNIC=m
-CONFIG_SCSI_SNIC=m
-# CONFIG_SCSI_SNIC_DEBUG_FS is not set
-CONFIG_SCSI_DMX3191D=m
-CONFIG_SCSI_FDOMAIN=m
-CONFIG_SCSI_FDOMAIN_PCI=m
-CONFIG_SCSI_ISCI=m
-CONFIG_SCSI_IPS=m
-CONFIG_SCSI_INITIO=m
-CONFIG_SCSI_INIA100=m
-CONFIG_SCSI_PPA=m
-CONFIG_SCSI_IMM=m
-# CONFIG_SCSI_IZIP_EPP16 is not set
-# CONFIG_SCSI_IZIP_SLOW_CTR is not set
-CONFIG_SCSI_STEX=m
-CONFIG_SCSI_SYM53C8XX_2=m
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_IPR=m
-# CONFIG_SCSI_IPR_TRACE is not set
-# CONFIG_SCSI_IPR_DUMP is not set
-CONFIG_SCSI_QLOGIC_1280=m
-CONFIG_SCSI_QLA_FC=m
-CONFIG_TCM_QLA2XXX=m
-# CONFIG_TCM_QLA2XXX_DEBUG is not set
-CONFIG_SCSI_QLA_ISCSI=m
-CONFIG_QEDI=m
-CONFIG_QEDF=m
-CONFIG_SCSI_LPFC=m
-# CONFIG_SCSI_LPFC_DEBUG_FS is not set
-CONFIG_SCSI_EFCT=m
-CONFIG_SCSI_DC395x=m
-CONFIG_SCSI_AM53C974=m
-CONFIG_SCSI_WD719X=m
-# CONFIG_SCSI_DEBUG is not set
-CONFIG_SCSI_PMCRAID=m
-CONFIG_SCSI_PM8001=m
-CONFIG_SCSI_BFA_FC=m
-CONFIG_SCSI_VIRTIO=m
-CONFIG_SCSI_CHELSIO_FCOE=m
-CONFIG_SCSI_LOWLEVEL_PCMCIA=y
-CONFIG_PCMCIA_AHA152X=m
-CONFIG_PCMCIA_FDOMAIN=m
-CONFIG_PCMCIA_QLOGIC=m
-CONFIG_PCMCIA_SYM53C500=m
-CONFIG_SCSI_DH=y
-CONFIG_SCSI_DH_RDAC=m
-CONFIG_SCSI_DH_HP_SW=m
-CONFIG_SCSI_DH_EMC=m
-CONFIG_SCSI_DH_ALUA=m
-# end of SCSI device support
-
-CONFIG_ATA=m
-CONFIG_SATA_HOST=y
-CONFIG_PATA_TIMINGS=y
-# CONFIG_ATA_VERBOSE_ERROR is not set
-CONFIG_ATA_FORCE=y
-CONFIG_ATA_ACPI=y
-CONFIG_SATA_ZPODD=y
-CONFIG_SATA_PMP=y
-
-#
-# Controllers with non-SFF native interface
-#
-CONFIG_SATA_AHCI=m
-CONFIG_SATA_MOBILE_LPM_POLICY=0
-CONFIG_SATA_AHCI_PLATFORM=m
-CONFIG_SATA_INIC162X=m
-CONFIG_SATA_ACARD_AHCI=m
-CONFIG_SATA_SIL24=m
-CONFIG_ATA_SFF=y
-
-#
-# SFF controllers with custom DMA interface
-#
-CONFIG_PDC_ADMA=m
-CONFIG_SATA_QSTOR=m
-CONFIG_SATA_SX4=m
-CONFIG_ATA_BMDMA=y
-
-#
-# SATA SFF controllers with BMDMA
-#
-CONFIG_ATA_PIIX=m
-CONFIG_SATA_DWC=m
-# CONFIG_SATA_DWC_OLD_DMA is not set
-# CONFIG_SATA_DWC_DEBUG is not set
-CONFIG_SATA_MV=m
-CONFIG_SATA_NV=m
-CONFIG_SATA_PROMISE=m
-CONFIG_SATA_SIL=m
-CONFIG_SATA_SIS=m
-CONFIG_SATA_SVW=m
-CONFIG_SATA_ULI=m
-CONFIG_SATA_VIA=m
-CONFIG_SATA_VITESSE=m
-
-#
-# PATA SFF controllers with BMDMA
-#
-CONFIG_PATA_ALI=m
-CONFIG_PATA_AMD=m
-CONFIG_PATA_ARTOP=m
-CONFIG_PATA_ATIIXP=m
-CONFIG_PATA_ATP867X=m
-CONFIG_PATA_CMD64X=m
-CONFIG_PATA_CYPRESS=m
-CONFIG_PATA_EFAR=m
-CONFIG_PATA_HPT366=m
-CONFIG_PATA_HPT37X=m
-CONFIG_PATA_HPT3X2N=m
-CONFIG_PATA_HPT3X3=m
-CONFIG_PATA_HPT3X3_DMA=y
-CONFIG_PATA_IT8213=m
-CONFIG_PATA_IT821X=m
-CONFIG_PATA_JMICRON=m
-CONFIG_PATA_MARVELL=m
-CONFIG_PATA_NETCELL=m
-CONFIG_PATA_NINJA32=m
-CONFIG_PATA_NS87415=m
-CONFIG_PATA_OLDPIIX=m
-CONFIG_PATA_OPTIDMA=m
-CONFIG_PATA_PDC2027X=m
-CONFIG_PATA_PDC_OLD=m
-CONFIG_PATA_RADISYS=m
-CONFIG_PATA_RDC=m
-CONFIG_PATA_SCH=m
-CONFIG_PATA_SERVERWORKS=m
-CONFIG_PATA_SIL680=m
-CONFIG_PATA_SIS=m
-CONFIG_PATA_TOSHIBA=m
-CONFIG_PATA_TRIFLEX=m
-CONFIG_PATA_VIA=m
-CONFIG_PATA_WINBOND=m
-
-#
-# PIO-only SFF controllers
-#
-CONFIG_PATA_CMD640_PCI=m
-CONFIG_PATA_MPIIX=m
-CONFIG_PATA_NS87410=m
-CONFIG_PATA_OPTI=m
-CONFIG_PATA_PCMCIA=m
-# CONFIG_PATA_PLATFORM is not set
-CONFIG_PATA_OF_PLATFORM=m
-CONFIG_PATA_RZ1000=m
-
-#
-# Generic fallback / legacy drivers
-#
-CONFIG_PATA_ACPI=m
-CONFIG_ATA_GENERIC=m
-CONFIG_PATA_LEGACY=m
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID456=m
-CONFIG_MD_MULTIPATH=m
-CONFIG_MD_FAULTY=m
-CONFIG_MD_CLUSTER=m
-CONFIG_BCACHE=m
-# CONFIG_BCACHE_DEBUG is not set
-# CONFIG_BCACHE_CLOSURES_DEBUG is not set
-CONFIG_BCACHE_ASYNC_REGISTRATION=y
-CONFIG_BLK_DEV_DM_BUILTIN=y
-CONFIG_BLK_DEV_DM=m
-# CONFIG_DM_DEBUG is not set
-CONFIG_DM_BUFIO=m
-# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
-CONFIG_DM_BIO_PRISON=m
-CONFIG_DM_PERSISTENT_DATA=m
-CONFIG_DM_UNSTRIPED=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_THIN_PROVISIONING=m
-CONFIG_DM_CACHE=m
-CONFIG_DM_CACHE_SMQ=m
-CONFIG_DM_WRITECACHE=m
-# CONFIG_DM_EBS is not set
-CONFIG_DM_ERA=m
-CONFIG_DM_CLONE=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_LOG_USERSPACE=m
-CONFIG_DM_RAID=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_QL=m
-CONFIG_DM_MULTIPATH_ST=m
-CONFIG_DM_MULTIPATH_HST=m
-CONFIG_DM_MULTIPATH_IOA=m
-CONFIG_DM_DELAY=m
-CONFIG_DM_DUST=m
-CONFIG_DM_UEVENT=y
-CONFIG_DM_FLAKEY=m
-CONFIG_DM_VERITY=m
-CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
-# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING is not set
-# CONFIG_DM_VERITY_FEC is not set
-CONFIG_DM_SWITCH=m
-CONFIG_DM_LOG_WRITES=m
-CONFIG_DM_INTEGRITY=m
-CONFIG_DM_ZONED=m
-CONFIG_DM_AUDIT=y
-CONFIG_TARGET_CORE=m
-CONFIG_TCM_IBLOCK=m
-CONFIG_TCM_FILEIO=m
-CONFIG_TCM_PSCSI=m
-CONFIG_TCM_USER2=m
-CONFIG_LOOPBACK_TARGET=m
-CONFIG_TCM_FC=m
-CONFIG_ISCSI_TARGET=m
-CONFIG_ISCSI_TARGET_CXGB4=m
-CONFIG_SBP_TARGET=m
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=m
-CONFIG_FUSION_FC=m
-CONFIG_FUSION_SAS=m
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_CTL=m
-CONFIG_FUSION_LAN=m
-CONFIG_FUSION_LOGGING=y
-
-#
-# IEEE 1394 (FireWire) support
-#
-CONFIG_FIREWIRE=m
-CONFIG_FIREWIRE_OHCI=m
-CONFIG_FIREWIRE_SBP2=m
-CONFIG_FIREWIRE_NET=m
-CONFIG_FIREWIRE_NOSY=m
-# end of IEEE 1394 (FireWire) support
-
-CONFIG_MACINTOSH_DRIVERS=y
-CONFIG_MAC_EMUMOUSEBTN=m
-CONFIG_NETDEVICES=y
-CONFIG_MII=m
-CONFIG_NET_CORE=y
-CONFIG_BONDING=m
-CONFIG_DUMMY=m
-CONFIG_WIREGUARD=m
-# CONFIG_WIREGUARD_DEBUG is not set
-CONFIG_EQUALIZER=m
-CONFIG_NET_FC=y
-CONFIG_IFB=m
-CONFIG_NET_TEAM=m
-CONFIG_NET_TEAM_MODE_BROADCAST=m
-CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
-CONFIG_NET_TEAM_MODE_RANDOM=m
-CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
-CONFIG_NET_TEAM_MODE_LOADBALANCE=m
-CONFIG_MACVLAN=m
-CONFIG_MACVTAP=m
-CONFIG_IPVLAN_L3S=y
-CONFIG_IPVLAN=m
-CONFIG_IPVTAP=m
-CONFIG_VXLAN=m
-CONFIG_GENEVE=m
-CONFIG_BAREUDP=m
-CONFIG_GTP=m
-CONFIG_AMT=m
-CONFIG_MACSEC=m
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_NETPOLL=y
-CONFIG_NET_POLL_CONTROLLER=y
-CONFIG_NTB_NETDEV=m
-CONFIG_RIONET=m
-CONFIG_RIONET_TX_SIZE=128
-CONFIG_RIONET_RX_SIZE=128
-CONFIG_TUN=m
-CONFIG_TAP=m
-# CONFIG_TUN_VNET_CROSS_LE is not set
-CONFIG_VETH=m
-CONFIG_VIRTIO_NET=m
-CONFIG_NLMON=m
-CONFIG_NET_VRF=m
-CONFIG_VSOCKMON=m
-CONFIG_MHI_NET=m
-CONFIG_SUNGEM_PHY=m
-CONFIG_ARCNET=m
-CONFIG_ARCNET_1201=m
-CONFIG_ARCNET_1051=m
-CONFIG_ARCNET_RAW=m
-CONFIG_ARCNET_CAP=m
-CONFIG_ARCNET_COM90xx=m
-CONFIG_ARCNET_COM90xxIO=m
-CONFIG_ARCNET_RIM_I=m
-CONFIG_ARCNET_COM20020=m
-CONFIG_ARCNET_COM20020_PCI=m
-CONFIG_ARCNET_COM20020_CS=m
-CONFIG_ATM_DRIVERS=y
-# CONFIG_ATM_DUMMY is not set
-CONFIG_ATM_TCP=m
-CONFIG_ATM_LANAI=m
-CONFIG_ATM_ENI=m
-# CONFIG_ATM_ENI_DEBUG is not set
-# CONFIG_ATM_ENI_TUNE_BURST is not set
-CONFIG_ATM_FIRESTREAM=m
-CONFIG_ATM_ZATM=m
-# CONFIG_ATM_ZATM_DEBUG is not set
-CONFIG_ATM_NICSTAR=m
-CONFIG_ATM_NICSTAR_USE_SUNI=y
-CONFIG_ATM_NICSTAR_USE_IDT77105=y
-CONFIG_ATM_IDT77252=m
-# CONFIG_ATM_IDT77252_DEBUG is not set
-# CONFIG_ATM_IDT77252_RCV_ALL is not set
-CONFIG_ATM_IDT77252_USE_SUNI=y
-CONFIG_ATM_AMBASSADOR=m
-# CONFIG_ATM_AMBASSADOR_DEBUG is not set
-CONFIG_ATM_HORIZON=m
-# CONFIG_ATM_HORIZON_DEBUG is not set
-CONFIG_ATM_IA=m
-# CONFIG_ATM_IA_DEBUG is not set
-CONFIG_ATM_FORE200E=m
-CONFIG_ATM_FORE200E_USE_TASKLET=y
-CONFIG_ATM_FORE200E_TX_RETRY=16
-CONFIG_ATM_FORE200E_DEBUG=0
-CONFIG_ATM_HE=m
-CONFIG_ATM_HE_USE_SUNI=y
-CONFIG_ATM_SOLOS=m
-# CONFIG_CAIF_DRIVERS is not set
-
-#
-# Distributed Switch Architecture drivers
-#
-CONFIG_B53=m
-CONFIG_B53_SPI_DRIVER=m
-CONFIG_B53_MDIO_DRIVER=m
-CONFIG_B53_MMAP_DRIVER=m
-CONFIG_B53_SRAB_DRIVER=m
-CONFIG_B53_SERDES=m
-CONFIG_NET_DSA_BCM_SF2=m
-CONFIG_NET_DSA_LOOP=m
-CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
-CONFIG_NET_DSA_LANTIQ_GSWIP=m
-CONFIG_NET_DSA_MT7530=m
-CONFIG_NET_DSA_MV88E6060=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-CONFIG_NET_DSA_MV88E6XXX=m
-CONFIG_NET_DSA_MV88E6XXX_PTP=y
-CONFIG_NET_DSA_MSCC_SEVILLE=m
-CONFIG_NET_DSA_AR9331=m
-CONFIG_NET_DSA_SJA1105=m
-CONFIG_NET_DSA_SJA1105_PTP=y
-CONFIG_NET_DSA_SJA1105_TAS=y
-# CONFIG_NET_DSA_SJA1105_VL is not set
-CONFIG_NET_DSA_XRS700X=m
-CONFIG_NET_DSA_XRS700X_I2C=m
-CONFIG_NET_DSA_XRS700X_MDIO=m
-CONFIG_NET_DSA_QCA8K=m
-CONFIG_NET_DSA_REALTEK_SMI=m
-CONFIG_NET_DSA_SMSC_LAN9303=m
-CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
-CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
-CONFIG_NET_DSA_VITESSE_VSC73XX=m
-CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
-CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
-# end of Distributed Switch Architecture drivers
-
-CONFIG_ETHERNET=y
-CONFIG_MDIO=m
-CONFIG_NET_VENDOR_3COM=y
-CONFIG_PCMCIA_3C574=m
-CONFIG_PCMCIA_3C589=m
-CONFIG_VORTEX=m
-CONFIG_TYPHOON=m
-CONFIG_NET_VENDOR_ADAPTEC=y
-CONFIG_ADAPTEC_STARFIRE=m
-CONFIG_NET_VENDOR_AGERE=y
-CONFIG_ET131X=m
-CONFIG_NET_VENDOR_ALACRITECH=y
-CONFIG_SLICOSS=m
-CONFIG_NET_VENDOR_ALTEON=y
-CONFIG_ACENIC=m
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
-CONFIG_ALTERA_TSE=m
-CONFIG_NET_VENDOR_AMAZON=y
-CONFIG_ENA_ETHERNET=m
-CONFIG_NET_VENDOR_AMD=y
-CONFIG_AMD8111_ETH=m
-CONFIG_PCNET32=m
-CONFIG_PCMCIA_NMCLAN=m
-CONFIG_AMD_XGBE=m
-CONFIG_AMD_XGBE_DCB=y
-CONFIG_AMD_XGBE_HAVE_ECC=y
-CONFIG_NET_VENDOR_AQUANTIA=y
-CONFIG_AQTION=m
-CONFIG_NET_VENDOR_ARC=y
-CONFIG_NET_VENDOR_ASIX=y
-CONFIG_SPI_AX88796C=m
-CONFIG_SPI_AX88796C_COMPRESSION=y
-CONFIG_NET_VENDOR_ATHEROS=y
-CONFIG_ATL2=m
-CONFIG_ATL1=m
-CONFIG_ATL1E=m
-CONFIG_ATL1C=m
-CONFIG_ALX=m
-CONFIG_NET_VENDOR_BROADCOM=y
-CONFIG_B44=m
-CONFIG_B44_PCI_AUTOSELECT=y
-CONFIG_B44_PCICORE_AUTOSELECT=y
-CONFIG_B44_PCI=y
-CONFIG_BCMGENET=m
-CONFIG_BNX2=m
-CONFIG_CNIC=m
-CONFIG_TIGON3=m
-CONFIG_TIGON3_HWMON=y
-CONFIG_BNX2X=m
-CONFIG_BNX2X_SRIOV=y
-CONFIG_SYSTEMPORT=m
-CONFIG_BNXT=m
-CONFIG_BNXT_SRIOV=y
-CONFIG_BNXT_FLOWER_OFFLOAD=y
-CONFIG_BNXT_DCB=y
-CONFIG_BNXT_HWMON=y
-CONFIG_NET_VENDOR_BROCADE=y
-CONFIG_BNA=m
-CONFIG_NET_VENDOR_CADENCE=y
-CONFIG_MACB=m
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MACB_PCI=m
-CONFIG_NET_VENDOR_CAVIUM=y
-CONFIG_THUNDER_NIC_PF=m
-CONFIG_THUNDER_NIC_VF=m
-CONFIG_THUNDER_NIC_BGX=m
-CONFIG_THUNDER_NIC_RGX=m
-CONFIG_CAVIUM_PTP=m
-CONFIG_LIQUIDIO=m
-CONFIG_LIQUIDIO_VF=m
-CONFIG_NET_VENDOR_CHELSIO=y
-CONFIG_CHELSIO_T1=m
-CONFIG_CHELSIO_T1_1G=y
-CONFIG_CHELSIO_T3=m
-CONFIG_CHELSIO_T4=m
-CONFIG_CHELSIO_T4_DCB=y
-# CONFIG_CHELSIO_T4_FCOE is not set
-CONFIG_CHELSIO_T4VF=m
-CONFIG_CHELSIO_LIB=m
-CONFIG_CHELSIO_INLINE_CRYPTO=y
-CONFIG_CHELSIO_IPSEC_INLINE=m
-CONFIG_NET_VENDOR_CISCO=y
-CONFIG_ENIC=m
-# CONFIG_NET_VENDOR_CORTINA is not set
-CONFIG_NET_VENDOR_DAVICOM=y
-CONFIG_DM9051=m
-CONFIG_CX_ECAT=m
-CONFIG_DNET=m
-CONFIG_NET_VENDOR_DEC=y
-CONFIG_NET_TULIP=y
-CONFIG_DE2104X=m
-CONFIG_DE2104X_DSL=0
-CONFIG_TULIP=m
-CONFIG_TULIP_MWI=y
-CONFIG_TULIP_MMIO=y
-CONFIG_TULIP_NAPI=y
-CONFIG_TULIP_NAPI_HW_MITIGATION=y
-CONFIG_DE4X5=m
-CONFIG_WINBOND_840=m
-CONFIG_DM9102=m
-CONFIG_ULI526X=m
-CONFIG_PCMCIA_XIRCOM=m
-CONFIG_NET_VENDOR_DLINK=y
-CONFIG_DL2K=m
-CONFIG_SUNDANCE=m
-# CONFIG_SUNDANCE_MMIO is not set
-CONFIG_NET_VENDOR_EMULEX=y
-CONFIG_BE2NET=m
-CONFIG_BE2NET_HWMON=y
-CONFIG_BE2NET_BE2=y
-CONFIG_BE2NET_BE3=y
-CONFIG_BE2NET_LANCER=y
-CONFIG_BE2NET_SKYHAWK=y
-CONFIG_NET_VENDOR_EZCHIP=y
-CONFIG_NET_VENDOR_FUJITSU=y
-CONFIG_NET_VENDOR_FUNGIBLE=y
-CONFIG_FUN_ETH=m
-CONFIG_PCMCIA_FMVJ18X=m
-CONFIG_NET_VENDOR_GOOGLE=y
-CONFIG_GVE=m
-CONFIG_NET_VENDOR_HUAWEI=y
-CONFIG_HINIC=m
-CONFIG_NET_VENDOR_I825XX=y
-CONFIG_NET_VENDOR_INTEL=y
-CONFIG_E100=m
-CONFIG_E1000=m
-CONFIG_E1000E=m
-CONFIG_E1000E_HWTS=y
-CONFIG_IGB=m
-CONFIG_IGB_HWMON=y
-CONFIG_IGB_DCA=y
-CONFIG_IGBVF=m
-CONFIG_IXGB=m
-CONFIG_IXGBE=m
-CONFIG_IXGBE_HWMON=y
-CONFIG_IXGBE_DCA=y
-CONFIG_IXGBE_DCB=y
-CONFIG_IXGBE_IPSEC=y
-CONFIG_IXGBEVF=m
-CONFIG_IXGBEVF_IPSEC=y
-CONFIG_I40E=m
-CONFIG_I40E_DCB=y
-CONFIG_IAVF=m
-CONFIG_I40EVF=m
-CONFIG_ICE=m
-CONFIG_ICE_SWITCHDEV=y
-CONFIG_ICE_HWTS=y
-CONFIG_FM10K=m
-CONFIG_IGC=m
-CONFIG_NET_VENDOR_MICROSOFT=y
-CONFIG_MICROSOFT_MANA=m
-CONFIG_JME=m
-CONFIG_NET_VENDOR_LITEX=y
-CONFIG_NET_VENDOR_MARVELL=y
-CONFIG_MVMDIO=m
-CONFIG_SKGE=m
-# CONFIG_SKGE_DEBUG is not set
-CONFIG_SKGE_GENESIS=y
-CONFIG_SKY2=m
-# CONFIG_SKY2_DEBUG is not set
-CONFIG_OCTEON_EP=m
-CONFIG_PRESTERA=m
-CONFIG_PRESTERA_PCI=m
-CONFIG_NET_VENDOR_MELLANOX=y
-CONFIG_MLX4_EN=m
-CONFIG_MLX4_EN_DCB=y
-CONFIG_MLX4_CORE=m
-# CONFIG_MLX4_DEBUG is not set
-CONFIG_MLX4_CORE_GEN2=y
-CONFIG_MLX5_CORE=m
-CONFIG_MLX5_ACCEL=y
-CONFIG_MLX5_FPGA=y
-CONFIG_MLX5_CORE_EN=y
-CONFIG_MLX5_EN_ARFS=y
-CONFIG_MLX5_EN_RXNFC=y
-CONFIG_MLX5_MPFS=y
-CONFIG_MLX5_ESWITCH=y
-CONFIG_MLX5_CLS_ACT=y
-CONFIG_MLX5_TC_SAMPLE=y
-CONFIG_MLX5_CORE_EN_DCB=y
-CONFIG_MLX5_CORE_IPOIB=y
-CONFIG_MLX5_EN_MACSEC=y
-CONFIG_MLX5_IPSEC=y
-CONFIG_MLX5_EN_IPSEC=y
-CONFIG_MLX5_SW_STEERING=y
-CONFIG_MLX5_SF=y
-CONFIG_MLX5_FPGA_IPSEC=y
-CONFIG_MLXSW_CORE=m
-CONFIG_MLXSW_CORE_HWMON=y
-CONFIG_MLXSW_CORE_THERMAL=y
-CONFIG_MLXSW_PCI=m
-CONFIG_MLXSW_I2C=m
-CONFIG_MLXSW_SPECTRUM=m
-CONFIG_MLXSW_SPECTRUM_DCB=y
-CONFIG_MLXSW_MINIMAL=m
-CONFIG_MLXFW=m
-CONFIG_NET_VENDOR_MICREL=y
-CONFIG_KS8842=m
-CONFIG_KS8851=m
-CONFIG_KS8851_MLL=m
-CONFIG_KSZ884X_PCI=m
-CONFIG_NET_VENDOR_MICROCHIP=y
-CONFIG_ENC28J60=m
-# CONFIG_ENC28J60_WRITEVERIFY is not set
-CONFIG_ENCX24J600=m
-CONFIG_LAN743X=m
-CONFIG_NET_VENDOR_MICROSEMI=y
-CONFIG_MSCC_OCELOT_SWITCH_LIB=m
-CONFIG_NET_VENDOR_MYRI=y
-CONFIG_MYRI10GE=m
-CONFIG_MYRI10GE_DCA=y
-CONFIG_FEALNX=m
-CONFIG_NET_VENDOR_NATSEMI=y
-CONFIG_NATSEMI=m
-CONFIG_NS83820=m
-CONFIG_NET_VENDOR_NETERION=y
-CONFIG_S2IO=m
-CONFIG_VXGE=m
-# CONFIG_VXGE_DEBUG_TRACE_ALL is not set
-CONFIG_NET_VENDOR_NETRONOME=y
-CONFIG_NFP=m
-# CONFIG_NFP_APP_FLOWER is not set
-CONFIG_NFP_APP_ABM_NIC=y
-# CONFIG_NFP_DEBUG is not set
-CONFIG_NET_VENDOR_NI=y
-CONFIG_NI_XGE_MANAGEMENT_ENET=m
-CONFIG_NET_VENDOR_8390=y
-CONFIG_PCMCIA_AXNET=m
-CONFIG_NE2K_PCI=m
-CONFIG_PCMCIA_PCNET=m
-CONFIG_NET_VENDOR_NVIDIA=y
-CONFIG_FORCEDETH=m
-CONFIG_NET_VENDOR_OKI=y
-CONFIG_ETHOC=m
-CONFIG_NET_VENDOR_PACKET_ENGINES=y
-CONFIG_HAMACHI=m
-CONFIG_YELLOWFIN=m
-CONFIG_NET_VENDOR_PENSANDO=y
-CONFIG_IONIC=m
-CONFIG_NET_VENDOR_QLOGIC=y
-CONFIG_QLA3XXX=m
-CONFIG_QLCNIC=m
-CONFIG_QLCNIC_SRIOV=y
-CONFIG_QLCNIC_DCB=y
-CONFIG_QLCNIC_HWMON=y
-CONFIG_NETXEN_NIC=m
-CONFIG_QED=m
-CONFIG_QED_LL2=y
-CONFIG_QED_SRIOV=y
-CONFIG_QEDE=m
-CONFIG_QED_RDMA=y
-CONFIG_QED_ISCSI=y
-CONFIG_QED_FCOE=y
-CONFIG_QED_OOO=y
-CONFIG_NET_VENDOR_QUALCOMM=y
-CONFIG_QCOM_EMAC=m
-CONFIG_RMNET=m
-CONFIG_NET_VENDOR_RDC=y
-CONFIG_R6040=m
-CONFIG_NET_VENDOR_REALTEK=y
-CONFIG_ATP=m
-CONFIG_8139CP=m
-CONFIG_8139TOO=m
-# CONFIG_8139TOO_PIO is not set
-CONFIG_8139TOO_TUNE_TWISTER=y
-CONFIG_8139TOO_8129=y
-# CONFIG_8139_OLD_RX_RESET is not set
-CONFIG_R8169=m
-CONFIG_NET_VENDOR_RENESAS=y
-CONFIG_NET_VENDOR_ROCKER=y
-CONFIG_ROCKER=m
-CONFIG_NET_VENDOR_SAMSUNG=y
-CONFIG_SXGBE_ETH=m
-CONFIG_NET_VENDOR_SEEQ=y
-CONFIG_NET_VENDOR_SOLARFLARE=y
-CONFIG_SFC=m
-CONFIG_SFC_MTD=y
-CONFIG_SFC_MCDI_MON=y
-CONFIG_SFC_SRIOV=y
-CONFIG_SFC_MCDI_LOGGING=y
-CONFIG_SFC_FALCON=m
-CONFIG_SFC_FALCON_MTD=y
-CONFIG_NET_VENDOR_SILAN=y
-CONFIG_SC92031=m
-CONFIG_NET_VENDOR_SIS=y
-CONFIG_SIS900=m
-CONFIG_SIS190=m
-CONFIG_NET_VENDOR_SMSC=y
-CONFIG_PCMCIA_SMC91C92=m
-CONFIG_EPIC100=m
-CONFIG_SMSC911X=m
-CONFIG_SMSC9420=m
-# CONFIG_NET_VENDOR_SOCIONEXT is not set
-CONFIG_NET_VENDOR_STMICRO=y
-CONFIG_STMMAC_ETH=m
-# CONFIG_STMMAC_SELFTESTS is not set
-CONFIG_STMMAC_PLATFORM=m
-CONFIG_DWMAC_GENERIC=m
-CONFIG_DWMAC_INTEL=m
-CONFIG_DWMAC_LOONGSON=m
-CONFIG_STMMAC_PCI=m
-CONFIG_NET_VENDOR_SUN=y
-CONFIG_HAPPYMEAL=m
-CONFIG_SUNGEM=m
-CONFIG_CASSINI=m
-CONFIG_NIU=m
-CONFIG_NET_VENDOR_SYNOPSYS=y
-CONFIG_DWC_XLGMAC=m
-CONFIG_DWC_XLGMAC_PCI=m
-CONFIG_NET_VENDOR_TEHUTI=y
-CONFIG_TEHUTI=m
-CONFIG_NET_VENDOR_TI=y
-# CONFIG_TI_CPSW_PHY_SEL is not set
-CONFIG_TLAN=m
-CONFIG_NET_VENDOR_VIA=y
-CONFIG_VIA_RHINE=m
-CONFIG_VIA_RHINE_MMIO=y
-CONFIG_VIA_VELOCITY=m
-CONFIG_NET_VENDOR_WIZNET=y
-CONFIG_WIZNET_W5100=m
-CONFIG_WIZNET_W5300=m
-# CONFIG_WIZNET_BUS_DIRECT is not set
-# CONFIG_WIZNET_BUS_INDIRECT is not set
-CONFIG_WIZNET_BUS_ANY=y
-CONFIG_WIZNET_W5100_SPI=m
-CONFIG_NET_VENDOR_XILINX=y
-CONFIG_XILINX_EMACLITE=m
-CONFIG_XILINX_AXI_EMAC=m
-CONFIG_XILINX_LL_TEMAC=m
-CONFIG_NET_VENDOR_XIRCOM=y
-CONFIG_PCMCIA_XIRC2PS=m
-CONFIG_FDDI=m
-CONFIG_DEFXX=m
-CONFIG_SKFP=m
-CONFIG_HIPPI=y
-CONFIG_ROADRUNNER=m
-CONFIG_ROADRUNNER_LARGE_RINGS=y
-CONFIG_NET_SB1000=m
-CONFIG_PHYLINK=m
-CONFIG_PHYLIB=m
-CONFIG_SWPHY=y
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_FIXED_PHY=m
-CONFIG_SFP=m
-
-#
-# MII PHY device drivers
-#
-CONFIG_AMD_PHY=m
-CONFIG_ADIN_PHY=m
-CONFIG_AQUANTIA_PHY=m
-CONFIG_AX88796B_PHY=m
-CONFIG_BROADCOM_PHY=m
-CONFIG_BCM54140_PHY=m
-CONFIG_BCM7XXX_PHY=m
-CONFIG_BCM84881_PHY=m
-CONFIG_BCM87XX_PHY=m
-CONFIG_BCM_NET_PHYLIB=m
-CONFIG_CICADA_PHY=m
-CONFIG_CORTINA_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_ICPLUS_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_INTEL_XWAY_PHY=m
-CONFIG_LSI_ET1011C_PHY=m
-CONFIG_MARVELL_PHY=m
-CONFIG_MARVELL_10G_PHY=m
-CONFIG_MARVELL_88X2222_PHY=m
-CONFIG_MAXLINEAR_GPHY=m
-CONFIG_MEDIATEK_GE_PHY=m
-CONFIG_MICREL_PHY=m
-CONFIG_MICROCHIP_PHY=m
-CONFIG_MICROCHIP_T1_PHY=m
-CONFIG_MICROSEMI_PHY=m
-CONFIG_MOTORCOMM_PHY=m
-CONFIG_NATIONAL_PHY=m
-CONFIG_NXP_C45_TJA11XX_PHY=m
-CONFIG_NXP_TJA11XX_PHY=m
-CONFIG_AT803X_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_REALTEK_PHY=m
-CONFIG_RENESAS_PHY=m
-# CONFIG_ROCKCHIP_PHY is not set
-CONFIG_SMSC_PHY=m
-CONFIG_STE10XP=m
-CONFIG_TERANETICS_PHY=m
-CONFIG_DP83822_PHY=m
-CONFIG_DP83TC811_PHY=m
-CONFIG_DP83848_PHY=m
-CONFIG_DP83867_PHY=m
-CONFIG_DP83869_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_XILINX_GMII2RGMII=m
-CONFIG_MICREL_KS8995MA=m
-
-#
-# MCTP Device Drivers
-#
-CONFIG_MDIO_DEVICE=m
-CONFIG_MDIO_BUS=m
-CONFIG_FWNODE_MDIO=m
-CONFIG_ACPI_MDIO=m
-CONFIG_MDIO_DEVRES=m
-CONFIG_MDIO_BITBANG=m
-CONFIG_MDIO_BCM_UNIMAC=m
-CONFIG_MDIO_CAVIUM=m
-CONFIG_MDIO_GPIO=m
-CONFIG_MDIO_I2C=m
-CONFIG_MDIO_MVUSB=m
-CONFIG_MDIO_MSCC_MIIM=m
-CONFIG_MDIO_THUNDER=m
-
-#
-# MDIO Multiplexers
-#
-
-#
-# PCS device drivers
-#
-CONFIG_PCS_XPCS=m
-CONFIG_PCS_LYNX=m
-# end of PCS device drivers
-
-CONFIG_PLIP=m
-CONFIG_PPP=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_MPPE=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPPOATM=m
-CONFIG_PPPOE=m
-CONFIG_PPTP=m
-CONFIG_PPPOL2TP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_SLIP=m
-CONFIG_SLHC=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-
-#
-# Host-side USB support is needed for USB Network Adapter support
-#
-CONFIG_USB_NET_DRIVERS=m
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_RTL8152=m
-CONFIG_USB_LAN78XX=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_AX8817X=m
-CONFIG_USB_NET_AX88179_178A=m
-CONFIG_USB_NET_CDCETHER=m
-CONFIG_USB_NET_CDC_EEM=m
-CONFIG_USB_NET_CDC_NCM=m
-CONFIG_USB_NET_HUAWEI_CDC_NCM=m
-CONFIG_USB_NET_CDC_MBIM=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_SR9700=m
-CONFIG_USB_NET_SR9800=m
-CONFIG_USB_NET_SMSC75XX=m
-CONFIG_USB_NET_SMSC95XX=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_NET1080=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_MCS7830=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
-CONFIG_USB_NET_CDC_SUBSET=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_BELKIN=y
-CONFIG_USB_ARMLINUX=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-CONFIG_USB_NET_ZAURUS=m
-CONFIG_USB_NET_CX82310_ETH=m
-CONFIG_USB_NET_KALMIA=m
-CONFIG_USB_NET_QMI_WWAN=m
-CONFIG_USB_HSO=m
-CONFIG_USB_NET_INT51X1=m
-CONFIG_USB_CDC_PHONET=m
-CONFIG_USB_IPHETH=m
-CONFIG_USB_SIERRA_NET=m
-CONFIG_USB_VL600=m
-CONFIG_USB_NET_CH9200=m
-CONFIG_USB_NET_AQC111=m
-CONFIG_USB_RTL8153_ECM=m
-CONFIG_WLAN=y
-CONFIG_WLAN_VENDOR_ADMTEK=y
-CONFIG_ADM8211=m
-CONFIG_ATH_COMMON=m
-CONFIG_WLAN_VENDOR_ATH=y
-# CONFIG_ATH_DEBUG is not set
-CONFIG_ATH5K=m
-# CONFIG_ATH5K_DEBUG is not set
-# CONFIG_ATH5K_TRACER is not set
-CONFIG_ATH5K_PCI=y
-CONFIG_ATH9K_HW=m
-CONFIG_ATH9K_COMMON=m
-CONFIG_ATH9K_BTCOEX_SUPPORT=y
-CONFIG_ATH9K=m
-CONFIG_ATH9K_PCI=y
-CONFIG_ATH9K_AHB=y
-# CONFIG_ATH9K_DEBUGFS is not set
-CONFIG_ATH9K_DYNACK=y
-CONFIG_ATH9K_WOW=y
-CONFIG_ATH9K_RFKILL=y
-CONFIG_ATH9K_CHANNEL_CONTEXT=y
-CONFIG_ATH9K_PCOEM=y
-CONFIG_ATH9K_PCI_NO_EEPROM=m
-CONFIG_ATH9K_HTC=m
-# CONFIG_ATH9K_HTC_DEBUGFS is not set
-CONFIG_ATH9K_HWRNG=y
-CONFIG_CARL9170=m
-CONFIG_CARL9170_LEDS=y
-CONFIG_CARL9170_WPC=y
-# CONFIG_CARL9170_HWRNG is not set
-CONFIG_ATH6KL=m
-CONFIG_ATH6KL_SDIO=m
-CONFIG_ATH6KL_USB=m
-# CONFIG_ATH6KL_DEBUG is not set
-# CONFIG_ATH6KL_TRACING is not set
-CONFIG_AR5523=m
-CONFIG_WIL6210=m
-CONFIG_WIL6210_ISR_COR=y
-CONFIG_WIL6210_TRACING=y
-CONFIG_WIL6210_DEBUGFS=y
-CONFIG_ATH10K=m
-CONFIG_ATH10K_CE=y
-CONFIG_ATH10K_PCI=m
-CONFIG_ATH10K_SDIO=m
-CONFIG_ATH10K_USB=m
-# CONFIG_ATH10K_DEBUG is not set
-# CONFIG_ATH10K_DEBUGFS is not set
-# CONFIG_ATH10K_TRACING is not set
-CONFIG_WCN36XX=m
-# CONFIG_WCN36XX_DEBUGFS is not set
-CONFIG_ATH11K=m
-CONFIG_ATH11K_PCI=m
-# CONFIG_ATH11K_DEBUG is not set
-# CONFIG_ATH11K_TRACING is not set
-CONFIG_WLAN_VENDOR_ATMEL=y
-CONFIG_ATMEL=m
-CONFIG_PCI_ATMEL=m
-CONFIG_PCMCIA_ATMEL=m
-CONFIG_AT76C50X_USB=m
-CONFIG_WLAN_VENDOR_BROADCOM=y
-CONFIG_B43=m
-CONFIG_B43_BCMA=y
-CONFIG_B43_SSB=y
-CONFIG_B43_BUSES_BCMA_AND_SSB=y
-# CONFIG_B43_BUSES_BCMA is not set
-# CONFIG_B43_BUSES_SSB is not set
-CONFIG_B43_PCI_AUTOSELECT=y
-CONFIG_B43_PCICORE_AUTOSELECT=y
-CONFIG_B43_SDIO=y
-CONFIG_B43_BCMA_PIO=y
-CONFIG_B43_PIO=y
-CONFIG_B43_PHY_G=y
-CONFIG_B43_PHY_N=y
-CONFIG_B43_PHY_LP=y
-CONFIG_B43_PHY_HT=y
-CONFIG_B43_LEDS=y
-CONFIG_B43_HWRNG=y
-# CONFIG_B43_DEBUG is not set
-CONFIG_B43LEGACY=m
-CONFIG_B43LEGACY_PCI_AUTOSELECT=y
-CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
-CONFIG_B43LEGACY_LEDS=y
-CONFIG_B43LEGACY_HWRNG=y
-# CONFIG_B43LEGACY_DEBUG is not set
-CONFIG_B43LEGACY_DMA=y
-CONFIG_B43LEGACY_PIO=y
-CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
-# CONFIG_B43LEGACY_DMA_MODE is not set
-# CONFIG_B43LEGACY_PIO_MODE is not set
-CONFIG_BRCMUTIL=m
-CONFIG_BRCMSMAC=m
-CONFIG_BRCMSMAC_LEDS=y
-CONFIG_BRCMFMAC=m
-CONFIG_BRCMFMAC_PROTO_BCDC=y
-CONFIG_BRCMFMAC_PROTO_MSGBUF=y
-CONFIG_BRCMFMAC_SDIO=y
-CONFIG_BRCMFMAC_USB=y
-CONFIG_BRCMFMAC_PCIE=y
-CONFIG_BRCM_TRACING=y
-# CONFIG_BRCMDBG is not set
-CONFIG_WLAN_VENDOR_CISCO=y
-CONFIG_AIRO=m
-CONFIG_AIRO_CS=m
-CONFIG_WLAN_VENDOR_INTEL=y
-CONFIG_IPW2100=m
-CONFIG_IPW2100_MONITOR=y
-# CONFIG_IPW2100_DEBUG is not set
-CONFIG_IPW2200=m
-CONFIG_IPW2200_MONITOR=y
-CONFIG_IPW2200_RADIOTAP=y
-CONFIG_IPW2200_PROMISCUOUS=y
-CONFIG_IPW2200_QOS=y
-# CONFIG_IPW2200_DEBUG is not set
-CONFIG_LIBIPW=m
-# CONFIG_LIBIPW_DEBUG is not set
-CONFIG_IWLEGACY=m
-CONFIG_IWL4965=m
-CONFIG_IWL3945=m
-
-#
-# iwl3945 / iwl4965 Debugging Options
-#
-# CONFIG_IWLEGACY_DEBUG is not set
-# end of iwl3945 / iwl4965 Debugging Options
-
-CONFIG_IWLWIFI=m
-CONFIG_IWLWIFI_LEDS=y
-CONFIG_IWLDVM=m
-CONFIG_IWLMVM=m
-CONFIG_IWLWIFI_OPMODE_MODULAR=y
-# CONFIG_IWLWIFI_BCAST_FILTERING is not set
-CONFIG_IWLMEI=m
-
-#
-# Debugging Options
-#
-# CONFIG_IWLWIFI_DEBUG is not set
-CONFIG_IWLWIFI_DEVICE_TRACING=y
-# end of Debugging Options
-
-CONFIG_WLAN_VENDOR_INTERSIL=y
-CONFIG_HOSTAP=m
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_HOSTAP_PLX=m
-CONFIG_HOSTAP_PCI=m
-CONFIG_HOSTAP_CS=m
-CONFIG_HERMES=m
-CONFIG_HERMES_PRISM=y
-CONFIG_HERMES_CACHE_FW_ON_INIT=y
-CONFIG_PLX_HERMES=m
-CONFIG_TMD_HERMES=m
-CONFIG_NORTEL_HERMES=m
-CONFIG_PCI_HERMES=m
-CONFIG_PCMCIA_HERMES=m
-CONFIG_PCMCIA_SPECTRUM=m
-CONFIG_ORINOCO_USB=m
-CONFIG_P54_COMMON=m
-CONFIG_P54_USB=m
-CONFIG_P54_PCI=m
-CONFIG_P54_SPI=m
-CONFIG_P54_SPI_DEFAULT_EEPROM=y
-CONFIG_P54_LEDS=y
-CONFIG_WLAN_VENDOR_MARVELL=y
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_USB=m
-CONFIG_LIBERTAS_CS=m
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_LIBERTAS_SPI=m
-# CONFIG_LIBERTAS_DEBUG is not set
-CONFIG_LIBERTAS_MESH=y
-CONFIG_LIBERTAS_THINFIRM=m
-# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
-CONFIG_LIBERTAS_THINFIRM_USB=m
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
-CONFIG_MWIFIEX_PCIE=m
-CONFIG_MWIFIEX_USB=m
-CONFIG_MWL8K=m
-CONFIG_WLAN_VENDOR_MEDIATEK=y
-CONFIG_MT7601U=m
-CONFIG_MT76_CORE=m
-CONFIG_MT76_LEDS=y
-CONFIG_MT76_USB=m
-CONFIG_MT76_SDIO=m
-CONFIG_MT76x02_LIB=m
-CONFIG_MT76x02_USB=m
-CONFIG_MT76_CONNAC_LIB=m
-CONFIG_MT76x0_COMMON=m
-CONFIG_MT76x0U=m
-CONFIG_MT76x0E=m
-CONFIG_MT76x2_COMMON=m
-CONFIG_MT76x2E=m
-CONFIG_MT76x2U=m
-CONFIG_MT7603E=m
-CONFIG_MT7615_COMMON=m
-CONFIG_MT7615E=m
-CONFIG_MT7663_USB_SDIO_COMMON=m
-CONFIG_MT7663U=m
-CONFIG_MT7663S=m
-CONFIG_MT7915E=m
-CONFIG_MT7986_WMAC=y
-CONFIG_MT7921_COMMON=m
-CONFIG_MT7921E=m
-CONFIG_MT7921S=m
-CONFIG_MT7921U=m
-CONFIG_WLAN_VENDOR_MICROCHIP=y
-CONFIG_WILC1000=m
-CONFIG_WILC1000_SDIO=m
-CONFIG_WILC1000_SPI=m
-# CONFIG_WILC1000_HW_OOB_INTR is not set
-CONFIG_WLAN_VENDOR_RALINK=y
-CONFIG_RT2X00=m
-CONFIG_RT2400PCI=m
-CONFIG_RT2500PCI=m
-CONFIG_RT61PCI=m
-CONFIG_RT2800PCI=m
-CONFIG_RT2800PCI_RT33XX=y
-CONFIG_RT2800PCI_RT35XX=y
-CONFIG_RT2800PCI_RT53XX=y
-CONFIG_RT2800PCI_RT3290=y
-CONFIG_RT2500USB=m
-CONFIG_RT73USB=m
-CONFIG_RT2800USB=m
-CONFIG_RT2800USB_RT33XX=y
-CONFIG_RT2800USB_RT35XX=y
-CONFIG_RT2800USB_RT3573=y
-CONFIG_RT2800USB_RT53XX=y
-CONFIG_RT2800USB_RT55XX=y
-CONFIG_RT2800USB_UNKNOWN=y
-CONFIG_RT2800_LIB=m
-CONFIG_RT2800_LIB_MMIO=m
-CONFIG_RT2X00_LIB_MMIO=m
-CONFIG_RT2X00_LIB_PCI=m
-CONFIG_RT2X00_LIB_USB=m
-CONFIG_RT2X00_LIB=m
-CONFIG_RT2X00_LIB_FIRMWARE=y
-CONFIG_RT2X00_LIB_CRYPTO=y
-CONFIG_RT2X00_LIB_LEDS=y
-# CONFIG_RT2X00_DEBUG is not set
-CONFIG_WLAN_VENDOR_REALTEK=y
-CONFIG_RTL8180=m
-CONFIG_RTL8187=m
-CONFIG_RTL8187_LEDS=y
-CONFIG_RTL_CARDS=m
-CONFIG_RTL8192CE=m
-CONFIG_RTL8192SE=m
-CONFIG_RTL8192DE=m
-CONFIG_RTL8723AE=m
-CONFIG_RTL8723BE=m
-CONFIG_RTL8188EE=m
-CONFIG_RTL8192EE=m
-CONFIG_RTL8821AE=m
-CONFIG_RTL8192CU=m
-CONFIG_RTLWIFI=m
-CONFIG_RTLWIFI_PCI=m
-CONFIG_RTLWIFI_USB=m
-# CONFIG_RTLWIFI_DEBUG is not set
-CONFIG_RTL8192C_COMMON=m
-CONFIG_RTL8723_COMMON=m
-CONFIG_RTLBTCOEXIST=m
-CONFIG_RTL8XXXU=m
-CONFIG_RTL8XXXU_UNTESTED=y
-CONFIG_RTW88=m
-CONFIG_RTW88_CORE=m
-CONFIG_RTW88_PCI=m
-CONFIG_RTW88_8822B=m
-CONFIG_RTW88_8822C=m
-CONFIG_RTW88_8723D=m
-CONFIG_RTW88_8821C=m
-CONFIG_RTW88_8822BE=m
-CONFIG_RTW88_8822CE=m
-CONFIG_RTW88_8723DE=m
-CONFIG_RTW88_8821CE=m
-# CONFIG_RTW88_DEBUG is not set
-# CONFIG_RTW88_DEBUGFS is not set
-CONFIG_RTW89=m
-CONFIG_RTW89_CORE=m
-CONFIG_RTW89_PCI=m
-CONFIG_RTW89_8852AE=m
-CONFIG_RTW89_DEBUG=y
-# CONFIG_RTW89_DEBUGMSG is not set
-CONFIG_RTW89_DEBUGFS=y
-CONFIG_WLAN_VENDOR_RSI=y
-CONFIG_RSI_91X=m
-# CONFIG_RSI_DEBUGFS is not set
-CONFIG_RSI_SDIO=m
-CONFIG_RSI_USB=m
-CONFIG_RSI_COEX=y
-CONFIG_WLAN_VENDOR_ST=y
-CONFIG_CW1200=m
-CONFIG_CW1200_WLAN_SDIO=m
-CONFIG_CW1200_WLAN_SPI=m
-CONFIG_WLAN_VENDOR_TI=y
-CONFIG_WL1251=m
-CONFIG_WL1251_SPI=m
-CONFIG_WL1251_SDIO=m
-CONFIG_WL12XX=m
-CONFIG_WL18XX=m
-CONFIG_WLCORE=m
-CONFIG_WLCORE_SDIO=m
-CONFIG_WILINK_PLATFORM_DATA=y
-CONFIG_WLAN_VENDOR_ZYDAS=y
-CONFIG_USB_ZD1201=m
-CONFIG_ZD1211RW=m
-# CONFIG_ZD1211RW_DEBUG is not set
-CONFIG_WLAN_VENDOR_QUANTENNA=y
-CONFIG_QTNFMAC=m
-CONFIG_QTNFMAC_PCIE=m
-CONFIG_PCMCIA_RAYCS=m
-CONFIG_PCMCIA_WL3501=m
-# CONFIG_MAC80211_HWSIM is not set
-CONFIG_USB_NET_RNDIS_WLAN=m
-CONFIG_VIRT_WIFI=m
-CONFIG_WAN=y
-CONFIG_LANMEDIA=m
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_PCI200SYN=m
-CONFIG_WANXL=m
-CONFIG_PC300TOO=m
-CONFIG_FARSYNC=m
-CONFIG_LAPBETHER=m
-CONFIG_IEEE802154_DRIVERS=m
-CONFIG_IEEE802154_FAKELB=m
-CONFIG_IEEE802154_AT86RF230=m
-# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set
-CONFIG_IEEE802154_MRF24J40=m
-CONFIG_IEEE802154_CC2520=m
-CONFIG_IEEE802154_ATUSB=m
-CONFIG_IEEE802154_ADF7242=m
-CONFIG_IEEE802154_CA8210=m
-# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
-CONFIG_IEEE802154_MCR20A=m
-CONFIG_IEEE802154_HWSIM=m
-
-#
-# Wireless WAN
-#
-CONFIG_WWAN=y
-CONFIG_WWAN_HWSIM=m
-CONFIG_MHI_WWAN_CTRL=m
-# CONFIG_TEST_MAPLE_TREE is not set
-CONFIG_MHI_WWAN_MBIM=m
-CONFIG_QCOM_BAM_DMUX=m
-CONFIG_RPMSG_WWAN_CTRL=m
-CONFIG_IOSM=m
-# end of Wireless WAN
-
-CONFIG_VMXNET3=m
-CONFIG_FUJITSU_ES=m
-CONFIG_USB4_NET=m
-CONFIG_HYPERV_NET=m
-CONFIG_NETDEVSIM=m
-CONFIG_NET_FAILOVER=m
-CONFIG_ISDN=y
-CONFIG_ISDN_CAPI=y
-CONFIG_CAPI_TRACE=y
-CONFIG_ISDN_CAPI_MIDDLEWARE=y
-CONFIG_MISDN=m
-CONFIG_MISDN_DSP=m
-CONFIG_MISDN_L1OIP=m
-
-#
-# mISDN hardware drivers
-#
-CONFIG_MISDN_HFCPCI=m
-CONFIG_MISDN_HFCMULTI=m
-CONFIG_MISDN_HFCUSB=m
-CONFIG_MISDN_AVMFRITZ=m
-CONFIG_MISDN_SPEEDFAX=m
-CONFIG_MISDN_INFINEON=m
-CONFIG_MISDN_W6692=m
-CONFIG_MISDN_NETJET=m
-CONFIG_MISDN_HDLC=m
-CONFIG_MISDN_IPAC=m
-CONFIG_MISDN_ISAR=m
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_LEDS=m
-CONFIG_INPUT_FF_MEMLESS=m
-CONFIG_INPUT_SPARSEKMAP=m
-CONFIG_INPUT_MATRIXKMAP=m
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ADC=m
-CONFIG_KEYBOARD_ADP5588=m
-CONFIG_KEYBOARD_ADP5589=m
-CONFIG_KEYBOARD_APPLESPI=m
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_KEYBOARD_QT1050=m
-CONFIG_KEYBOARD_QT1070=m
-CONFIG_KEYBOARD_QT2160=m
-CONFIG_KEYBOARD_DLINK_DIR685=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_GPIO=m
-CONFIG_KEYBOARD_GPIO_POLLED=m
-CONFIG_KEYBOARD_TCA6416=m
-CONFIG_KEYBOARD_TCA8418=m
-CONFIG_KEYBOARD_MATRIX=m
-CONFIG_KEYBOARD_LM8323=m
-CONFIG_KEYBOARD_LM8333=m
-CONFIG_KEYBOARD_MAX7359=m
-CONFIG_KEYBOARD_MCS=m
-CONFIG_KEYBOARD_MPR121=m
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_OPENCORES=m
-CONFIG_KEYBOARD_PINEPHONE=m
-CONFIG_KEYBOARD_SAMSUNG=m
-CONFIG_KEYBOARD_STOWAWAY=m
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_IQS62X=m
-CONFIG_KEYBOARD_TM2_TOUCHKEY=m
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_KEYBOARD_CROS_EC=m
-CONFIG_KEYBOARD_MTK_PMIC=m
-CONFIG_KEYBOARD_CYPRESS_SF=m
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_BYD=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
-CONFIG_MOUSE_PS2_CYPRESS=y
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-CONFIG_MOUSE_PS2_ELANTECH=y
-CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
-CONFIG_MOUSE_PS2_SENTELIC=y
-CONFIG_MOUSE_PS2_TOUCHKIT=y
-CONFIG_MOUSE_PS2_FOCALTECH=y
-# CONFIG_MOUSE_PS2_VMMOUSE is not set
-CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_APPLETOUCH=m
-CONFIG_MOUSE_BCM5974=m
-CONFIG_MOUSE_CYAPA=m
-CONFIG_MOUSE_ELAN_I2C=m
-CONFIG_MOUSE_ELAN_I2C_I2C=y
-CONFIG_MOUSE_ELAN_I2C_SMBUS=y
-CONFIG_MOUSE_VSXXXAA=m
-CONFIG_MOUSE_GPIO=m
-CONFIG_MOUSE_SYNAPTICS_I2C=m
-CONFIG_MOUSE_SYNAPTICS_USB=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADC=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=m
-CONFIG_JOYSTICK_IFORCE_232=m
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_TWIDJOY=m
-CONFIG_JOYSTICK_ZHENHUA=m
-CONFIG_JOYSTICK_DB9=m
-CONFIG_JOYSTICK_GAMECON=m
-CONFIG_JOYSTICK_TURBOGRAFX=m
-CONFIG_JOYSTICK_AS5011=m
-# CONFIG_JOYSTICK_JOYDUMP is not set
-CONFIG_JOYSTICK_XPAD=m
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_JOYSTICK_WALKERA0701=m
-CONFIG_JOYSTICK_PSXPAD_SPI=m
-CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
-CONFIG_JOYSTICK_PXRC=m
-CONFIG_JOYSTICK_QWIIC=m
-CONFIG_JOYSTICK_FSIA6B=m
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=m
-CONFIG_TABLET_USB_AIPTEK=m
-CONFIG_TABLET_USB_HANWANG=m
-CONFIG_TABLET_USB_KBTAB=m
-CONFIG_TABLET_USB_PEGASUS=m
-CONFIG_TABLET_SERIAL_WACOM4=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=m
-CONFIG_TOUCHSCREEN_AD7877=m
-CONFIG_TOUCHSCREEN_AD7879=m
-CONFIG_TOUCHSCREEN_AD7879_I2C=m
-CONFIG_TOUCHSCREEN_AD7879_SPI=m
-CONFIG_TOUCHSCREEN_ADC=m
-CONFIG_TOUCHSCREEN_ATMEL_MXT=m
-# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set
-CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
-CONFIG_TOUCHSCREEN_BU21013=m
-CONFIG_TOUCHSCREEN_BU21029=m
-CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
-CONFIG_TOUCHSCREEN_CY8CTMA140=m
-CONFIG_TOUCHSCREEN_CY8CTMG110=m
-CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
-CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
-CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
-CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
-CONFIG_TOUCHSCREEN_DA9052=m
-CONFIG_TOUCHSCREEN_DYNAPRO=m
-CONFIG_TOUCHSCREEN_HAMPSHIRE=m
-CONFIG_TOUCHSCREEN_EETI=m
-CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
-CONFIG_TOUCHSCREEN_EXC3000=m
-CONFIG_TOUCHSCREEN_FUJITSU=m
-CONFIG_TOUCHSCREEN_GOODIX=m
-CONFIG_TOUCHSCREEN_HIDEEP=m
-CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
-CONFIG_TOUCHSCREEN_ILI210X=m
-CONFIG_TOUCHSCREEN_ILITEK=m
-CONFIG_TOUCHSCREEN_S6SY761=m
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_TOUCHSCREEN_EKTF2127=m
-CONFIG_TOUCHSCREEN_ELAN=m
-CONFIG_TOUCHSCREEN_ELO=m
-CONFIG_TOUCHSCREEN_WACOM_W8001=m
-CONFIG_TOUCHSCREEN_WACOM_I2C=m
-CONFIG_TOUCHSCREEN_MAX11801=m
-CONFIG_TOUCHSCREEN_MCS5000=m
-CONFIG_TOUCHSCREEN_MMS114=m
-CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
-CONFIG_TOUCHSCREEN_MSG2638=m
-CONFIG_TOUCHSCREEN_MTOUCH=m
-CONFIG_TOUCHSCREEN_IMAGIS=m
-CONFIG_TOUCHSCREEN_INEXIO=m
-CONFIG_TOUCHSCREEN_MK712=m
-CONFIG_TOUCHSCREEN_PENMOUNT=m
-CONFIG_TOUCHSCREEN_EDT_FT5X06=m
-CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
-CONFIG_TOUCHSCREEN_TOUCHWIN=m
-CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m
-CONFIG_TOUCHSCREEN_UCB1400=m
-CONFIG_TOUCHSCREEN_PIXCIR=m
-CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
-CONFIG_TOUCHSCREEN_WM831X=m
-CONFIG_TOUCHSCREEN_WM97XX=m
-CONFIG_TOUCHSCREEN_WM9705=y
-CONFIG_TOUCHSCREEN_WM9712=y
-CONFIG_TOUCHSCREEN_WM9713=y
-CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-CONFIG_TOUCHSCREEN_MC13783=m
-CONFIG_TOUCHSCREEN_USB_EGALAX=y
-CONFIG_TOUCHSCREEN_USB_PANJIT=y
-CONFIG_TOUCHSCREEN_USB_3M=y
-CONFIG_TOUCHSCREEN_USB_ITM=y
-CONFIG_TOUCHSCREEN_USB_ETURBO=y
-CONFIG_TOUCHSCREEN_USB_GUNZE=y
-CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
-CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
-CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
-CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
-CONFIG_TOUCHSCREEN_USB_GOTOP=y
-CONFIG_TOUCHSCREEN_USB_JASTEC=y
-CONFIG_TOUCHSCREEN_USB_ELO=y
-CONFIG_TOUCHSCREEN_USB_E2I=y
-CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
-CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
-CONFIG_TOUCHSCREEN_USB_NEXIO=y
-CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
-CONFIG_TOUCHSCREEN_TOUCHIT213=m
-CONFIG_TOUCHSCREEN_TSC_SERIO=m
-CONFIG_TOUCHSCREEN_TSC200X_CORE=m
-CONFIG_TOUCHSCREEN_TSC2004=m
-CONFIG_TOUCHSCREEN_TSC2005=m
-CONFIG_TOUCHSCREEN_TSC2007=m
-CONFIG_TOUCHSCREEN_TSC2007_IIO=y
-CONFIG_TOUCHSCREEN_PCAP=m
-CONFIG_TOUCHSCREEN_RM_TS=m
-CONFIG_TOUCHSCREEN_SILEAD=m
-CONFIG_TOUCHSCREEN_SIS_I2C=m
-CONFIG_TOUCHSCREEN_ST1232=m
-CONFIG_TOUCHSCREEN_STMFTS=m
-CONFIG_TOUCHSCREEN_SUR40=m
-CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
-CONFIG_TOUCHSCREEN_SX8654=m
-CONFIG_TOUCHSCREEN_TPS6507X=m
-CONFIG_TOUCHSCREEN_ZET6223=m
-CONFIG_TOUCHSCREEN_ZFORCE=m
-CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
-CONFIG_TOUCHSCREEN_ROHM_BU21023=m
-CONFIG_TOUCHSCREEN_IQS5XX=m
-CONFIG_TOUCHSCREEN_ZINITIX=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_88PM80X_ONKEY=m
-CONFIG_INPUT_AD714X=m
-CONFIG_INPUT_AD714X_I2C=m
-CONFIG_INPUT_AD714X_SPI=m
-CONFIG_INPUT_ARIZONA_HAPTICS=m
-CONFIG_INPUT_ATC260X_ONKEY=m
-CONFIG_INPUT_BMA150=m
-CONFIG_INPUT_E3X0_BUTTON=m
-CONFIG_INPUT_PCSPKR=m
-CONFIG_INPUT_MAX77693_HAPTIC=m
-CONFIG_INPUT_MC13783_PWRBUTTON=m
-CONFIG_INPUT_MMA8450=m
-CONFIG_INPUT_APANEL=m
-CONFIG_INPUT_GPIO_BEEPER=m
-CONFIG_INPUT_GPIO_DECODER=m
-CONFIG_INPUT_GPIO_VIBRA=m
-CONFIG_INPUT_ATLAS_BTNS=m
-CONFIG_INPUT_ATI_REMOTE2=m
-CONFIG_INPUT_KEYSPAN_REMOTE=m
-CONFIG_INPUT_KXTJ9=m
-CONFIG_INPUT_POWERMATE=m
-CONFIG_INPUT_YEALINK=m
-CONFIG_INPUT_CM109=m
-CONFIG_INPUT_REGULATOR_HAPTIC=m
-CONFIG_INPUT_RETU_PWRBUTTON=m
-CONFIG_INPUT_AXP20X_PEK=m
-CONFIG_INPUT_UINPUT=m
-CONFIG_INPUT_PCF50633_PMU=m
-CONFIG_INPUT_PCF8574=m
-CONFIG_INPUT_PWM_BEEPER=m
-CONFIG_INPUT_PWM_VIBRA=m
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-CONFIG_INPUT_DA7280_HAPTICS=m
-CONFIG_INPUT_DA9052_ONKEY=m
-CONFIG_INPUT_DA9063_ONKEY=m
-CONFIG_INPUT_WM831X_ON=m
-CONFIG_INPUT_PCAP=m
-CONFIG_INPUT_ADXL34X=m
-CONFIG_INPUT_IBM_PANEL=m
-CONFIG_INPUT_ADXL34X_I2C=m
-CONFIG_INPUT_ADXL34X_SPI=m
-CONFIG_INPUT_IMS_PCU=m
-CONFIG_INPUT_IQS269A=m
-CONFIG_INPUT_IQS626A=m
-CONFIG_INPUT_CMA3000=m
-CONFIG_INPUT_CMA3000_I2C=m
-CONFIG_INPUT_IDEAPAD_SLIDEBAR=m
-CONFIG_INPUT_SOC_BUTTON_ARRAY=m
-CONFIG_INPUT_DRV260X_HAPTICS=m
-CONFIG_INPUT_DRV2665_HAPTICS=m
-CONFIG_INPUT_DRV2667_HAPTICS=m
-CONFIG_INPUT_RAVE_SP_PWRBUTTON=m
-CONFIG_INPUT_RT5120_PWRKEY=m
-CONFIG_RMI4_CORE=m
-CONFIG_RMI4_I2C=m
-CONFIG_RMI4_SPI=m
-CONFIG_RMI4_SMB=m
-CONFIG_RMI4_F03=y
-CONFIG_RMI4_F03_SERIO=m
-CONFIG_RMI4_2D_SENSOR=y
-CONFIG_RMI4_F11=y
-CONFIG_RMI4_F12=y
-CONFIG_RMI4_F30=y
-CONFIG_RMI4_F34=y
-CONFIG_RMI4_F3A=y
-CONFIG_RMI4_F54=y
-CONFIG_RMI4_F55=y
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=m
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_SERIO_I8042=y
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_CT82C710=m
-CONFIG_SERIO_PARKBD=m
-CONFIG_SERIO_PCIPS2=m
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_RAW=m
-CONFIG_SERIO_ALTERA_PS2=m
-CONFIG_SERIO_PS2MULT=m
-CONFIG_SERIO_ARC_PS2=m
-CONFIG_HYPERV_KEYBOARD=m
-CONFIG_SERIO_GPIO_PS2=m
-CONFIG_USERIO=m
-CONFIG_GAMEPORT=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_GAMEPORT_EMU10K1=m
-CONFIG_GAMEPORT_FM801=m
-# end of Hardware I/O ports
-# end of Input device support
-
-#
-# Character devices
-#
-CONFIG_TTY=y
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LDISC_AUTOLOAD=y
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_EARLYCON=y
-CONFIG_SERIAL_8250=y
-# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-CONFIG_SERIAL_8250_PNP=y
-# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
-CONFIG_SERIAL_8250_FINTEK=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_DMA=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_CS=m
-CONFIG_SERIAL_8250_MEN_MCB=m
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_DW=m
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_8250_LPSS=y
-CONFIG_SERIAL_8250_MID=y
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_MAX3100=m
-CONFIG_SERIAL_MAX310X=y
-CONFIG_SERIAL_UARTLITE=m
-CONFIG_SERIAL_UARTLITE_NR_UARTS=1
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_JSM=m
-CONFIG_SERIAL_LANTIQ=m
-CONFIG_SERIAL_SCCNXP=m
-CONFIG_SERIAL_SC16IS7XX_CORE=m
-CONFIG_SERIAL_SC16IS7XX=m
-CONFIG_SERIAL_SC16IS7XX_I2C=y
-CONFIG_SERIAL_SC16IS7XX_SPI=y
-CONFIG_SERIAL_BCM63XX=m
-CONFIG_SERIAL_ALTERA_JTAGUART=m
-CONFIG_SERIAL_ALTERA_UART=m
-CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
-CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
-CONFIG_SERIAL_ARC=m
-CONFIG_SERIAL_ARC_NR_PORTS=1
-CONFIG_SERIAL_RP2=m
-CONFIG_SERIAL_RP2_NR_UARTS=32
-CONFIG_SERIAL_FSL_LPUART=m
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_FSL_LINFLEXUART=m
-CONFIG_SERIAL_MEN_Z135=m
-CONFIG_SERIAL_SPRD=m
-# end of Serial drivers
-
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_MOXA_INTELLIO=m
-CONFIG_MOXA_SMARTIO=m
-CONFIG_SYNCLINK_GT=m
-CONFIG_N_HDLC=m
-CONFIG_N_GSM=m
-CONFIG_NOZOMI=m
-CONFIG_NULL_TTY=m
-CONFIG_HVC_DRIVER=y
-CONFIG_RPMSG_TTY=m
-CONFIG_SERIAL_DEV_BUS=m
-# CONFIG_TTY_PRINTK is not set
-CONFIG_PRINTER=m
-CONFIG_LP_CONSOLE=y
-CONFIG_PPDEV=m
-CONFIG_VIRTIO_CONSOLE=m
-CONFIG_IPMI_HANDLER=m
-CONFIG_IPMI_DMI_DECODE=y
-CONFIG_IPMI_PLAT_DATA=y
-CONFIG_IPMI_PANIC_EVENT=y
-CONFIG_IPMI_PANIC_STRING=y
-CONFIG_IPMI_DEVICE_INTERFACE=m
-CONFIG_IPMI_SI=m
-CONFIG_IPMI_SSIF=m
-CONFIG_IPMI_IPMB=m
-CONFIG_IPMI_WATCHDOG=m
-CONFIG_IPMI_POWEROFF=m
-CONFIG_NPCM7XX_KCS_IPMI_BMC=m
-CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m
-CONFIG_IPMI_KCS_BMC_SERIO=m
-CONFIG_IPMB_DEVICE_INTERFACE=m
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=y
-CONFIG_HW_RANDOM_INTEL=y
-CONFIG_HW_RANDOM_AMD=y
-CONFIG_HW_RANDOM_BA431=y
-CONFIG_HW_RANDOM_VIA=y
-# CONFIG_HW_RANDOM_VIRTIO is not set
-CONFIG_HW_RANDOM_XIPHERA=m
-CONFIG_APPLICOM=m
-
-#
-# PCMCIA character devices
-#
-CONFIG_SYNCLINK_CS=m
-CONFIG_CARDMAN_4000=m
-CONFIG_CARDMAN_4040=m
-CONFIG_SCR24X=m
-CONFIG_IPWIRELESS=m
-# end of PCMCIA character devices
-
-CONFIG_MWAVE=m
-CONFIG_DEVMEM=y
-CONFIG_NVRAM=m
-CONFIG_DEVPORT=y
-CONFIG_HPET=y
-CONFIG_HPET_MMAP=y
-CONFIG_HPET_MMAP_DEFAULT=y
-CONFIG_HANGCHECK_TIMER=m
-CONFIG_TCG_TPM=m
-CONFIG_HW_RANDOM_TPM=y
-CONFIG_TCG_TIS_CORE=m
-CONFIG_TCG_TIS=m
-CONFIG_TCG_TIS_SPI=m
-# CONFIG_TCG_TIS_SPI_CR50 is not set
-CONFIG_TCG_TIS_I2C_CR50=m
-CONFIG_TCG_TIS_I2C_ATMEL=m
-CONFIG_TCG_TIS_I2C_INFINEON=m
-CONFIG_TCG_TIS_I2C_NUVOTON=m
-CONFIG_TCG_NSC=m
-CONFIG_TCG_ATMEL=m
-CONFIG_TCG_INFINEON=m
-CONFIG_TCG_CRB=m
-CONFIG_TCG_VTPM_PROXY=m
-CONFIG_TCG_TIS_ST33ZP24=m
-CONFIG_TCG_TIS_ST33ZP24_I2C=m
-CONFIG_TCG_TIS_ST33ZP24_SPI=m
-CONFIG_TELCLOCK=m
-CONFIG_XILLYBUS_CLASS=m
-CONFIG_XILLYBUS=m
-CONFIG_XILLYBUS_PCIE=m
-CONFIG_XILLYUSB=m
-CONFIG_RANDOM_TRUST_CPU=y
-CONFIG_RANDOM_TRUST_BOOTLOADER=y
-# end of Character devices
-
-#
-# I2C support
-#
-CONFIG_I2C=m
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_MUX=m
-
-#
-# Multiplexer I2C Chip support
-#
-CONFIG_I2C_MUX_GPIO=m
-CONFIG_I2C_MUX_LTC4306=m
-CONFIG_I2C_MUX_PCA9541=m
-CONFIG_I2C_MUX_PCA954x=m
-CONFIG_I2C_MUX_REG=m
-CONFIG_I2C_MUX_MLXCPLD=m
-# end of Multiplexer I2C Chip support
-
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_SMBUS=m
-CONFIG_I2C_ALGOBIT=m
-CONFIG_I2C_ALGOPCA=m
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# PC SMBus host controller drivers
-#
-CONFIG_I2C_ALI1535=m
-CONFIG_I2C_ALI1563=m
-CONFIG_I2C_ALI15X3=m
-CONFIG_I2C_AMD756=m
-CONFIG_I2C_AMD756_S4882=m
-CONFIG_I2C_AMD8111=m
-CONFIG_I2C_AMD_MP2=m
-CONFIG_I2C_I801=m
-CONFIG_I2C_ISCH=m
-CONFIG_I2C_ISMT=m
-CONFIG_I2C_PIIX4=m
-CONFIG_I2C_NFORCE2=m
-CONFIG_I2C_NFORCE2_S4985=m
-CONFIG_I2C_NVIDIA_GPU=m
-CONFIG_I2C_SIS5595=m
-CONFIG_I2C_SIS630=m
-CONFIG_I2C_SIS96X=m
-CONFIG_I2C_VIA=m
-CONFIG_I2C_VIAPRO=m
-
-#
-# ACPI drivers
-#
-CONFIG_I2C_SCMI=m
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-CONFIG_I2C_CBUS_GPIO=m
-CONFIG_I2C_DESIGNWARE_CORE=m
-# CONFIG_I2C_DESIGNWARE_SLAVE is not set
-CONFIG_I2C_DESIGNWARE_PLATFORM=m
-CONFIG_I2C_DESIGNWARE_AMDPSP=y
-# CONFIG_I2C_DESIGNWARE_BAYTRAIL is not set
-CONFIG_I2C_DESIGNWARE_PCI=m
-CONFIG_I2C_EMEV2=m
-CONFIG_I2C_GPIO=m
-# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
-CONFIG_I2C_KEMPLD=m
-CONFIG_I2C_OCORES=m
-CONFIG_I2C_PCA_PLATFORM=m
-CONFIG_I2C_SIMTEC=m
-CONFIG_I2C_XILINX=m
-
-#
-# External I2C/SMBus adapter drivers
-#
-CONFIG_I2C_DIOLAN_U2C=m
-CONFIG_I2C_DLN2=m
-CONFIG_I2C_CP2615=m
-CONFIG_I2C_PARPORT=m
-CONFIG_I2C_PCI1XXXX=m
-CONFIG_I2C_ROBOTFUZZ_OSIF=m
-CONFIG_I2C_TAOS_EVM=m
-CONFIG_I2C_TINY_USB=m
-CONFIG_I2C_VIPERBOARD=m
-
-#
-# Other I2C/SMBus bus drivers
-#
-CONFIG_I2C_MLXCPLD=m
-CONFIG_I2C_CROS_EC_TUNNEL=m
-CONFIG_I2C_VIRTIO=m
-# end of I2C Hardware Bus support
-
-# CONFIG_I2C_STUB is not set
-CONFIG_I2C_SLAVE=y
-CONFIG_I2C_SLAVE_EEPROM=m
-CONFIG_I2C_SLAVE_TESTUNIT=m
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# end of I2C support
-
-CONFIG_I3C=m
-CONFIG_CDNS_I3C_MASTER=m
-CONFIG_DW_I3C_MASTER=m
-CONFIG_SVC_I3C_MASTER=m
-CONFIG_MIPI_I3C_HCI=m
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-
-#
-# SPI Master Controller Drivers
-#
-CONFIG_SPI_ALTERA=m
-CONFIG_SPI_ALTERA_CORE=m
-CONFIG_SPI_ALTERA_DFL=m
-CONFIG_SPI_AXI_SPI_ENGINE=m
-CONFIG_SPI_BITBANG=m
-CONFIG_SPI_BUTTERFLY=m
-CONFIG_SPI_CADENCE=m
-CONFIG_SPI_DESIGNWARE=m
-# CONFIG_SPI_DW_DMA is not set
-CONFIG_SPI_DW_PCI=m
-CONFIG_SPI_DW_MMIO=m
-CONFIG_SPI_DLN2=m
-CONFIG_SPI_NXP_FLEXSPI=m
-CONFIG_SPI_GPIO=m
-CONFIG_SPI_INTEL_PCI=m
-CONFIG_SPI_INTEL_PLATFORM=m
-CONFIG_SPI_LM70_LLP=m
-CONFIG_SPI_LANTIQ_SSC=m
-CONFIG_SPI_OC_TINY=m
-CONFIG_SPI_PXA2XX=m
-CONFIG_SPI_PXA2XX_PCI=m
-# CONFIG_SPI_ROCKCHIP is not set
-CONFIG_SPI_SC18IS602=m
-CONFIG_SPI_SIFIVE=m
-CONFIG_SPI_MXIC=m
-CONFIG_SPI_XCOMM=m
-CONFIG_SPI_XILINX=m
-CONFIG_SPI_ZYNQMP_GQSPI=m
-CONFIG_SPI_AMD=m
-
-#
-# SPI Multiplexer support
-#
-CONFIG_SPI_MUX=m
-
-#
-# SPI Protocol Masters
-#
-CONFIG_SPI_SPIDEV=m
-CONFIG_SPI_LOOPBACK_TEST=m
-CONFIG_SPI_TLE62X0=m
-CONFIG_SPI_SLAVE=y
-CONFIG_SPI_SLAVE_TIME=m
-CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPMI=m
-CONFIG_SPMI_HISI3670=m
-CONFIG_HSI=m
-CONFIG_HSI_BOARDINFO=y
-
-#
-# HSI controllers
-#
-
-#
-# HSI clients
-#
-CONFIG_HSI_CHAR=m
-CONFIG_PPS=y
-# CONFIG_PPS_DEBUG is not set
-
-#
-# PPS clients support
-#
-# CONFIG_PPS_CLIENT_KTIMER is not set
-CONFIG_PPS_CLIENT_LDISC=m
-CONFIG_PPS_CLIENT_PARPORT=m
-CONFIG_PPS_CLIENT_GPIO=m
-
-#
-# PPS generators support
-#
-
-#
-# PTP clock support
-#
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_DP83640_PHY=m
-CONFIG_PTP_1588_CLOCK_INES=m
-CONFIG_PTP_1588_CLOCK_KVM=m
-CONFIG_PTP_1588_CLOCK_IDT82P33=m
-CONFIG_PTP_1588_CLOCK_IDTCM=m
-CONFIG_PTP_1588_CLOCK_VMW=m
-CONFIG_PTP_1588_CLOCK_OCP=m
-# end of PTP clock support
-
-CONFIG_PINCTRL=y
-CONFIG_PINMUX=y
-CONFIG_PINCONF=y
-CONFIG_GENERIC_PINCONF=y
-# CONFIG_DEBUG_PINCTRL is not set
-CONFIG_PINCTRL_AMD=m
-CONFIG_PINCTRL_CY8C95X0=m
-CONFIG_PINCTRL_DA9062=m
-CONFIG_PINCTRL_MCP23S08_I2C=m
-CONFIG_PINCTRL_MCP23S08_SPI=m
-CONFIG_PINCTRL_MCP23S08=m
-
-#
-# Intel pinctrl drivers
-#
-CONFIG_PINCTRL_BAYTRAIL=y
-CONFIG_PINCTRL_CHERRYVIEW=m
-CONFIG_PINCTRL_LYNXPOINT=m
-CONFIG_PINCTRL_INTEL=y
-CONFIG_PINCTRL_ALDERLAKE=m
-CONFIG_PINCTRL_BROXTON=m
-CONFIG_PINCTRL_CANNONLAKE=m
-CONFIG_PINCTRL_CEDARFORK=m
-CONFIG_PINCTRL_DENVERTON=m
-CONFIG_PINCTRL_ELKHARTLAKE=m
-CONFIG_PINCTRL_EMMITSBURG=m
-CONFIG_PINCTRL_GEMINILAKE=m
-CONFIG_PINCTRL_ICELAKE=m
-CONFIG_PINCTRL_JASPERLAKE=m
-CONFIG_PINCTRL_LAKEFIELD=m
-CONFIG_PINCTRL_LEWISBURG=m
-CONFIG_PINCTRL_METEORLAKE=m
-CONFIG_PINCTRL_SUNRISEPOINT=m
-CONFIG_PINCTRL_TIGERLAKE=m
-# end of Intel pinctrl drivers
-
-#
-# Renesas pinctrl drivers
-#
-# end of Renesas pinctrl drivers
-
-CONFIG_PINCTRL_MADERA=m
-CONFIG_PINCTRL_CS47L15=y
-CONFIG_PINCTRL_CS47L35=y
-CONFIG_PINCTRL_CS47L85=y
-CONFIG_PINCTRL_CS47L90=y
-CONFIG_PINCTRL_CS47L92=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_FASTPATH_LIMIT=512
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIOLIB_IRQCHIP=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_CDEV=y
-# CONFIG_GPIO_CDEV_V1 is not set
-CONFIG_GPIO_GENERIC=m
-CONFIG_GPIO_MAX730X=m
-
-#
-# Memory mapped GPIO drivers
-#
-CONFIG_GPIO_AMDPT=m
-CONFIG_GPIO_DWAPB=m
-CONFIG_GPIO_EXAR=m
-CONFIG_GPIO_GENERIC_PLATFORM=m
-CONFIG_GPIO_ICH=m
-CONFIG_GPIO_MB86S7X=m
-CONFIG_GPIO_MENZ127=m
-CONFIG_GPIO_SIOX=m
-CONFIG_GPIO_VX855=m
-CONFIG_GPIO_AMD_FCH=m
-# end of Memory mapped GPIO drivers
-
-#
-# Port-mapped I/O GPIO drivers
-#
-CONFIG_GPIO_F7188X=m
-CONFIG_GPIO_IT87=m
-CONFIG_GPIO_SCH=m
-CONFIG_GPIO_SCH311X=m
-CONFIG_GPIO_WINBOND=m
-CONFIG_GPIO_WS16C48=m
-# end of Port-mapped I/O GPIO drivers
-
-#
-# I2C GPIO expanders
-#
-CONFIG_GPIO_ADP5588=m
-CONFIG_GPIO_MAX7300=m
-CONFIG_GPIO_MAX732X=m
-CONFIG_GPIO_PCA953X=m
-# CONFIG_GPIO_PCA953X_IRQ is not set
-CONFIG_GPIO_PCA9570=m
-CONFIG_GPIO_PCF857X=m
-CONFIG_GPIO_TPIC2810=m
-# end of I2C GPIO expanders
-
-#
-# MFD GPIO expanders
-#
-CONFIG_GPIO_ARIZONA=m
-CONFIG_GPIO_BD9571MWV=m
-CONFIG_GPIO_DA9052=m
-CONFIG_GPIO_DLN2=m
-CONFIG_GPIO_JANZ_TTL=m
-CONFIG_GPIO_KEMPLD=m
-CONFIG_GPIO_LP3943=m
-CONFIG_GPIO_LP873X=m
-CONFIG_GPIO_MADERA=m
-CONFIG_GPIO_TPS65086=m
-CONFIG_GPIO_TPS65912=m
-CONFIG_GPIO_TPS68470=y
-CONFIG_GPIO_TQMX86=m
-CONFIG_GPIO_UCB1400=m
-CONFIG_GPIO_WHISKEY_COVE=m
-CONFIG_GPIO_WM831X=m
-CONFIG_GPIO_WM8994=m
-# end of MFD GPIO expanders
-
-#
-# PCI GPIO expanders
-#
-CONFIG_GPIO_AMD8111=m
-CONFIG_GPIO_ML_IOH=m
-CONFIG_GPIO_PCI_IDIO_16=m
-CONFIG_GPIO_PCIE_IDIO_24=m
-CONFIG_GPIO_RDC321X=m
-# end of PCI GPIO expanders
-
-#
-# SPI GPIO expanders
-#
-CONFIG_GPIO_MAX3191X=m
-CONFIG_GPIO_MAX7301=m
-CONFIG_GPIO_MC33880=m
-CONFIG_GPIO_PISOSR=m
-CONFIG_GPIO_XRA1403=m
-# end of SPI GPIO expanders
-
-#
-# USB GPIO expanders
-#
-CONFIG_GPIO_VIPERBOARD=m
-# end of USB GPIO expanders
-
-#
-# Virtual GPIO drivers
-#
-CONFIG_GPIO_AGGREGATOR=m
-CONFIG_GPIO_MOCKUP=m
-CONFIG_GPIO_VIRTIO=m
-# end of Virtual GPIO drivers
-
-CONFIG_W1=m
-CONFIG_W1_CON=y
-
-#
-# 1-wire Bus Masters
-#
-CONFIG_W1_MASTER_MATROX=m
-CONFIG_W1_MASTER_DS2490=m
-CONFIG_W1_MASTER_DS2482=m
-CONFIG_W1_MASTER_DS1WM=m
-CONFIG_W1_MASTER_GPIO=m
-CONFIG_W1_MASTER_SGI=m
-# end of 1-wire Bus Masters
-
-#
-# 1-wire Slaves
-#
-CONFIG_W1_SLAVE_THERM=m
-CONFIG_W1_SLAVE_SMEM=m
-# CONFIG_W1_SLAVE_DS2405 is not set
-CONFIG_W1_SLAVE_DS2408=m
-# CONFIG_W1_SLAVE_DS2408_READBACK is not set
-CONFIG_W1_SLAVE_DS2413=m
-CONFIG_W1_SLAVE_DS2406=m
-CONFIG_W1_SLAVE_DS2423=m
-CONFIG_W1_SLAVE_DS2805=m
-CONFIG_W1_SLAVE_DS2430=m
-CONFIG_W1_SLAVE_DS2431=m
-CONFIG_W1_SLAVE_DS2433=m
-CONFIG_W1_SLAVE_DS2433_CRC=y
-CONFIG_W1_SLAVE_DS2438=m
-CONFIG_W1_SLAVE_DS250X=m
-CONFIG_W1_SLAVE_DS2780=m
-CONFIG_W1_SLAVE_DS2781=m
-CONFIG_W1_SLAVE_DS28E04=m
-CONFIG_W1_SLAVE_DS28E17=m
-# end of 1-wire Slaves
-
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_ATC260X=m
-CONFIG_POWER_RESET_MT6323=y
-# CONFIG_POWER_RESET_RESTART is not set
-CONFIG_POWER_RESET_TPS65086=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PDA_POWER=m
-CONFIG_GENERIC_ADC_BATTERY=m
-CONFIG_IP5XXX_POWER=m
-CONFIG_WM831X_BACKUP=m
-CONFIG_WM831X_POWER=m
-# CONFIG_TEST_POWER is not set
-CONFIG_CHARGER_ADP5061=m
-CONFIG_BATTERY_CW2015=m
-CONFIG_BATTERY_DS2760=m
-CONFIG_BATTERY_DS2780=m
-CONFIG_BATTERY_DS2781=m
-CONFIG_BATTERY_DS2782=m
-# CONFIG_BATTERY_SAMSUNG_SDI is not set
-CONFIG_BATTERY_SBS=m
-CONFIG_CHARGER_SBS=m
-CONFIG_MANAGER_SBS=m
-CONFIG_BATTERY_BQ27XXX=m
-CONFIG_BATTERY_BQ27XXX_I2C=m
-CONFIG_BATTERY_BQ27XXX_HDQ=m
-# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set
-CONFIG_BATTERY_DA9052=m
-CONFIG_CHARGER_DA9150=m
-CONFIG_BATTERY_DA9150=m
-CONFIG_CHARGER_AXP20X=m
-CONFIG_BATTERY_AXP20X=m
-CONFIG_AXP20X_POWER=m
-CONFIG_AXP288_CHARGER=m
-CONFIG_AXP288_FUEL_GAUGE=m
-CONFIG_BATTERY_MAX17040=m
-CONFIG_BATTERY_MAX17042=m
-CONFIG_BATTERY_MAX1721X=m
-CONFIG_CHARGER_PCF50633=m
-CONFIG_CHARGER_ISP1704=m
-CONFIG_CHARGER_MAX8903=m
-CONFIG_CHARGER_LP8727=m
-CONFIG_CHARGER_GPIO=m
-CONFIG_CHARGER_MANAGER=y
-CONFIG_CHARGER_LT3651=m
-CONFIG_CHARGER_LTC4162L=m
-CONFIG_CHARGER_MAX14577=m
-CONFIG_CHARGER_MAX77693=m
-CONFIG_CHARGER_MP2629=m
-CONFIG_CHARGER_MT6360=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_CHARGER_BQ2415X=m
-CONFIG_CHARGER_BQ24190=m
-CONFIG_CHARGER_BQ24257=m
-CONFIG_CHARGER_BQ24735=m
-CONFIG_CHARGER_BQ2515X=m
-CONFIG_CHARGER_BQ25890=m
-CONFIG_CHARGER_BQ25980=m
-CONFIG_CHARGER_BQ256XX=m
-CONFIG_CHARGER_SMB347=m
-CONFIG_BATTERY_GAUGE_LTC2941=m
-CONFIG_BATTERY_GOLDFISH=m
-CONFIG_BATTERY_RT5033=m
-CONFIG_CHARGER_RT9455=m
-CONFIG_CHARGER_CROS_USBPD=m
-CONFIG_CHARGER_CROS_PCHG=m
-CONFIG_CHARGER_BD99954=m
-CONFIG_BATTERY_UG3105=m
-CONFIG_CHARGER_WILCO=m
-CONFIG_BATTERY_SURFACE=m
-CONFIG_CHARGER_SURFACE=m
-CONFIG_HWMON=y
-CONFIG_HWMON_VID=m
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Native drivers
-#
-CONFIG_SENSORS_ABITUGURU=m
-CONFIG_SENSORS_ABITUGURU3=m
-CONFIG_SENSORS_AD7314=m
-CONFIG_SENSORS_AD7414=m
-CONFIG_SENSORS_AD7418=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1026=m
-CONFIG_SENSORS_ADM1029=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_ADM1177=m
-CONFIG_SENSORS_ADM9240=m
-CONFIG_SENSORS_ADT7X10=m
-CONFIG_SENSORS_ADT7310=m
-CONFIG_SENSORS_ADT7410=m
-CONFIG_SENSORS_ADT7411=m
-CONFIG_SENSORS_ADT7462=m
-CONFIG_SENSORS_ADT7470=m
-CONFIG_SENSORS_ADT7475=m
-CONFIG_SENSORS_AHT10=m
-CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m
-CONFIG_SENSORS_AS370=m
-CONFIG_SENSORS_ASC7621=m
-CONFIG_SENSORS_AXI_FAN_CONTROL=m
-CONFIG_SENSORS_K8TEMP=m
-CONFIG_SENSORS_K10TEMP=m
-CONFIG_SENSORS_FAM15H_POWER=m
-CONFIG_SENSORS_APPLESMC=m
-CONFIG_SENSORS_ASB100=m
-CONFIG_SENSORS_ASPEED=m
-CONFIG_SENSORS_ATXP1=m
-CONFIG_SENSORS_CORSAIR_CPRO=m
-CONFIG_SENSORS_CORSAIR_PSU=m
-CONFIG_SENSORS_DRIVETEMP=m
-CONFIG_SENSORS_DS620=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_DELL_SMM=m
-# CONFIG_I8K is not set
-CONFIG_SENSORS_DA9052_ADC=m
-CONFIG_SENSORS_I5K_AMB=m
-CONFIG_SENSORS_F71805F=m
-CONFIG_SENSORS_F71882FG=m
-CONFIG_SENSORS_F75375S=m
-CONFIG_SENSORS_MC13783_ADC=m
-CONFIG_SENSORS_FSCHMD=m
-CONFIG_SENSORS_FTSTEUTATES=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_GL520SM=m
-CONFIG_SENSORS_G760A=m
-CONFIG_SENSORS_G762=m
-CONFIG_SENSORS_HIH6130=m
-CONFIG_SENSORS_IBMAEM=m
-CONFIG_SENSORS_IBMPEX=m
-CONFIG_SENSORS_IIO_HWMON=m
-CONFIG_SENSORS_I5500=m
-CONFIG_SENSORS_CORETEMP=m
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_JC42=m
-CONFIG_SENSORS_POWR1220=m
-CONFIG_SENSORS_LINEAGE=m
-CONFIG_SENSORS_LTC2945=m
-CONFIG_SENSORS_LTC2947=m
-CONFIG_SENSORS_LTC2947_I2C=m
-CONFIG_SENSORS_LTC2947_SPI=m
-CONFIG_SENSORS_LTC2990=m
-CONFIG_SENSORS_LTC2992=m
-CONFIG_SENSORS_LTC4151=m
-CONFIG_SENSORS_LTC4215=m
-CONFIG_SENSORS_LTC4222=m
-CONFIG_SENSORS_LTC4245=m
-CONFIG_SENSORS_LTC4260=m
-CONFIG_SENSORS_LTC4261=m
-CONFIG_SENSORS_MAX1111=m
-CONFIG_SENSORS_MAX127=m
-CONFIG_SENSORS_MAX16065=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_MAX1668=m
-CONFIG_SENSORS_MAX197=m
-CONFIG_SENSORS_MAX31722=m
-CONFIG_SENSORS_MAX31730=m
-CONFIG_SENSORS_MAX31760=m
-CONFIG_SENSORS_MAX6620=m
-CONFIG_SENSORS_MAX6621=m
-CONFIG_SENSORS_MAX6639=m
-CONFIG_SENSORS_MAX6642=m
-CONFIG_SENSORS_MAX6650=m
-CONFIG_SENSORS_MAX6697=m
-CONFIG_SENSORS_MAX31790=m
-CONFIG_SENSORS_MCP3021=m
-CONFIG_SENSORS_MLXREG_FAN=m
-CONFIG_SENSORS_TC654=m
-CONFIG_SENSORS_TPS23861=m
-CONFIG_SENSORS_MENF21BMC_HWMON=m
-CONFIG_SENSORS_MR75203=m
-CONFIG_SENSORS_ADCXX=m
-CONFIG_SENSORS_LM63=m
-CONFIG_SENSORS_LM70=m
-CONFIG_SENSORS_LM73=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM87=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_LM92=m
-CONFIG_SENSORS_LM93=m
-CONFIG_SENSORS_LM95234=m
-CONFIG_SENSORS_LM95241=m
-CONFIG_SENSORS_LM95245=m
-CONFIG_SENSORS_PC87360=m
-CONFIG_SENSORS_PC87427=m
-CONFIG_SENSORS_NTC_THERMISTOR=m
-CONFIG_SENSORS_NCT6683=m
-CONFIG_SENSORS_NCT6775=m
-CONFIG_SENSORS_NCT7802=m
-CONFIG_SENSORS_NCT7904=m
-CONFIG_SENSORS_NPCM7XX=m
-CONFIG_SENSORS_NZXT_KRAKEN2=m
-CONFIG_SENSORS_PCF8591=m
-CONFIG_PMBUS=m
-CONFIG_SENSORS_PMBUS=m
-CONFIG_SENSORS_ADM1266=m
-CONFIG_SENSORS_ADM1275=m
-CONFIG_SENSORS_BEL_PFE=m
-CONFIG_SENSORS_BPA_RS600=m
-CONFIG_SENSORS_FSP_3Y=m
-CONFIG_SENSORS_IBM_CFFPS=m
-CONFIG_SENSORS_DPS920AB=m
-CONFIG_SENSORS_INSPUR_IPSPS=m
-CONFIG_SENSORS_IR35221=m
-CONFIG_SENSORS_IR36021=m
-CONFIG_SENSORS_IR38064=m
-CONFIG_SENSORS_IRPS5401=m
-CONFIG_SENSORS_ISL68137=m
-CONFIG_SENSORS_LM25066=m
-CONFIG_SENSORS_LM25066_REGULATOR=y
-CONFIG_SENSORS_LTC2978=m
-CONFIG_SENSORS_LTC2978_REGULATOR=y
-CONFIG_SENSORS_LTC3815=m
-CONFIG_SENSORS_MAX15301=m
-CONFIG_SENSORS_MAX16064=m
-CONFIG_SENSORS_MAX16601=m
-CONFIG_SENSORS_MAX20730=m
-CONFIG_SENSORS_MAX20751=m
-CONFIG_SENSORS_MAX31785=m
-CONFIG_SENSORS_MAX34440=m
-CONFIG_SENSORS_MAX8688=m
-CONFIG_SENSORS_MP2888=m
-CONFIG_SENSORS_MP2975=m
-CONFIG_SENSORS_PIM4328=m
-CONFIG_SENSORS_PLI1209BC=m
-CONFIG_SENSORS_PLI1209BC_REGULATOR=y
-CONFIG_SENSORS_PM6764TR=m
-CONFIG_SENSORS_PXE1610=m
-CONFIG_SENSORS_Q54SJ108A2=m
-CONFIG_SENSORS_STPDDC60=m
-CONFIG_SENSORS_TPS40422=m
-CONFIG_SENSORS_TPS53679=m
-CONFIG_SENSORS_TPS546D24=m
-CONFIG_SENSORS_UCD9000=m
-CONFIG_SENSORS_UCD9200=m
-CONFIG_SENSORS_XDPE122=m
-CONFIG_SENSORS_XDPE122_REGULATOR=y
-CONFIG_SENSORS_ZL6100=m
-CONFIG_SENSORS_SBTSI=m
-CONFIG_SENSORS_SBRMI=m
-CONFIG_SENSORS_SHT15=m
-CONFIG_SENSORS_SHT21=m
-CONFIG_SENSORS_SHT3x=m
-CONFIG_SENSORS_SHT4x=m
-CONFIG_SENSORS_SHTC1=m
-CONFIG_SENSORS_SIS5595=m
-CONFIG_SENSORS_SY7636A=m
-CONFIG_SENSORS_DME1737=m
-CONFIG_SENSORS_EMC1403=m
-CONFIG_SENSORS_EMC2103=m
-CONFIG_SENSORS_EMC2305=m
-CONFIG_SENSORS_EMC6W201=m
-CONFIG_SENSORS_SMSC47M1=m
-CONFIG_SENSORS_SMSC47M192=m
-CONFIG_SENSORS_SMSC47B397=m
-CONFIG_SENSORS_SCH56XX_COMMON=m
-CONFIG_SENSORS_SCH5627=m
-CONFIG_SENSORS_SCH5636=m
-CONFIG_SENSORS_STTS751=m
-CONFIG_SENSORS_SMM665=m
-CONFIG_SENSORS_ADC128D818=m
-CONFIG_SENSORS_ADS7828=m
-CONFIG_SENSORS_ADS7871=m
-CONFIG_SENSORS_AMC6821=m
-CONFIG_SENSORS_INA209=m
-CONFIG_SENSORS_INA2XX=m
-CONFIG_SENSORS_INA3221=m
-CONFIG_SENSORS_TC74=m
-CONFIG_SENSORS_THMC50=m
-CONFIG_SENSORS_TMP102=m
-CONFIG_SENSORS_TMP103=m
-CONFIG_SENSORS_TMP108=m
-CONFIG_SENSORS_TMP401=m
-CONFIG_SENSORS_TMP421=m
-CONFIG_SENSORS_TMP464=m
-CONFIG_SENSORS_TMP513=m
-CONFIG_SENSORS_VIA_CPUTEMP=m
-CONFIG_SENSORS_VIA686A=m
-CONFIG_SENSORS_VT1211=m
-CONFIG_SENSORS_VT8231=m
-CONFIG_SENSORS_W83773G=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83791D=m
-CONFIG_SENSORS_W83792D=m
-CONFIG_SENSORS_W83793=m
-CONFIG_SENSORS_W83795=m
-CONFIG_SENSORS_W83795_FANCTRL=y
-CONFIG_SENSORS_W83L785TS=m
-CONFIG_SENSORS_W83L786NG=m
-CONFIG_SENSORS_W83627HF=m
-CONFIG_SENSORS_W83627EHF=m
-CONFIG_SENSORS_WM831X=m
-CONFIG_SENSORS_XGENE=m
-CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m
-
-#
-# ACPI drivers
-#
-CONFIG_SENSORS_ACPI_POWER=m
-CONFIG_SENSORS_ATK0110=m
-CONFIG_SENSORS_ASUS_WMI_EC=m
-CONFIG_SENSORS_ASUS_EC=m
-CONFIG_SENSORS_ASUS_WMI=m
-CONFIG_THERMAL=y
-CONFIG_THERMAL_NETLINK=y
-CONFIG_THERMAL_STATISTICS=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=100
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
-CONFIG_DEVFREQ_THERMAL=y
-# CONFIG_THERMAL_EMULATION is not set
-
-#
-# Intel thermal drivers
-#
-CONFIG_INTEL_POWERCLAMP=m
-CONFIG_X86_THERMAL_VECTOR=y
-CONFIG_X86_PKG_TEMP_THERMAL=m
-CONFIG_INTEL_SOC_DTS_IOSF_CORE=m
-CONFIG_INTEL_SOC_DTS_THERMAL=m
-
-#
-# ACPI INT340X thermal drivers
-#
-CONFIG_INT340X_THERMAL=m
-CONFIG_ACPI_THERMAL_REL=m
-CONFIG_INT3406_THERMAL=m
-CONFIG_PROC_THERMAL_MMIO_RAPL=m
-# end of ACPI INT340X thermal drivers
-
-CONFIG_INTEL_BXT_PMIC_THERMAL=m
-CONFIG_INTEL_PCH_THERMAL=m
-CONFIG_INTEL_TCC_COOLING=m
-CONFIG_INTEL_MENLOW=m
-CONFIG_INTEL_HFI_THERMAL=y
-# end of Intel thermal drivers
-
-CONFIG_GENERIC_ADC_THERMAL=m
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_CORE=m
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
-CONFIG_WATCHDOG_OPEN_TIMEOUT=0
-# CONFIG_WATCHDOG_SYSFS is not set
-# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
-
-#
-# Watchdog Pretimeout Governors
-#
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-
-#
-# Watchdog Device Drivers
-#
-CONFIG_SOFT_WATCHDOG=m
-# CONFIG_SOFT_WATCHDOG_PRETIMEOUT is not set
-CONFIG_DA9052_WATCHDOG=m
-CONFIG_DA9063_WATCHDOG=m
-CONFIG_DA9062_WATCHDOG=m
-CONFIG_MENF21BMC_WATCHDOG=m
-CONFIG_MENZ069_WATCHDOG=m
-CONFIG_WDAT_WDT=m
-CONFIG_WM831X_WATCHDOG=m
-CONFIG_XILINX_WATCHDOG=m
-CONFIG_ZIIRAVE_WATCHDOG=m
-CONFIG_RAVE_SP_WATCHDOG=m
-CONFIG_MLX_WDT=m
-CONFIG_CADENCE_WATCHDOG=m
-CONFIG_DW_WATCHDOG=m
-CONFIG_MAX63XX_WATCHDOG=m
-CONFIG_MAX77620_WATCHDOG=m
-CONFIG_RETU_WATCHDOG=m
-CONFIG_ACQUIRE_WDT=m
-CONFIG_ADVANTECH_WDT=m
-CONFIG_ALIM1535_WDT=m
-CONFIG_ALIM7101_WDT=m
-CONFIG_EBC_C384_WDT=m
-CONFIG_EXAR_WDT=m
-CONFIG_F71808E_WDT=m
-# CONFIG_SP5100_TCO is not set
-CONFIG_SBC_FITPC2_WATCHDOG=m
-CONFIG_EUROTECH_WDT=m
-CONFIG_IB700_WDT=m
-CONFIG_IBMASR=m
-CONFIG_WAFER_WDT=m
-CONFIG_I6300ESB_WDT=m
-CONFIG_HP_WATCHDOG=m
-CONFIG_IE6XX_WDT=m
-CONFIG_ITCO_WDT=m
-CONFIG_ITCO_VENDOR_SUPPORT=y
-CONFIG_IT8712F_WDT=m
-CONFIG_IT87_WDT=m
-CONFIG_HP_WATCHDOG=m
-CONFIG_HPWDT_NMI_DECODING=y
-CONFIG_KEMPLD_WDT=m
-CONFIG_BCM7038_WDT=m
-CONFIG_SC1200_WDT=m
-CONFIG_PC87413_WDT=m
-CONFIG_NV_TCO=m
-CONFIG_60XX_WDT=m
-CONFIG_CPU5_WDT=m
-CONFIG_SMSC_SCH311X_WDT=m
-CONFIG_SMSC37B787_WDT=m
-CONFIG_TQMX86_WDT=m
-CONFIG_VIA_WDT=m
-CONFIG_W83627HF_WDT=m
-CONFIG_W83877F_WDT=m
-CONFIG_W83977F_WDT=m
-CONFIG_MACHZ_WDT=m
-CONFIG_SBC_EPX_C3_WATCHDOG=m
-CONFIG_INTEL_MEI_WDT=m
-CONFIG_NI903X_WDT=m
-CONFIG_NIC7018_WDT=m
-CONFIG_SIEMENS_SIMATIC_IPC_WDT=m
-CONFIG_MEN_A21_WDT=m
-
-#
-# PCI-based Watchdog Cards
-#
-CONFIG_PCIPCWATCHDOG=m
-CONFIG_WDTPCI=m
-
-#
-# USB-based Watchdog Cards
-#
-CONFIG_USBPCWATCHDOG=m
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SSB=m
-CONFIG_SSB_SPROM=y
-CONFIG_SSB_BLOCKIO=y
-CONFIG_SSB_PCIHOST_POSSIBLE=y
-CONFIG_SSB_PCIHOST=y
-CONFIG_SSB_B43_PCI_BRIDGE=y
-CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
-CONFIG_SSB_PCMCIAHOST=y
-CONFIG_SSB_SDIOHOST_POSSIBLE=y
-CONFIG_SSB_SDIOHOST=y
-CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
-CONFIG_SSB_DRIVER_PCICORE=y
-CONFIG_SSB_DRIVER_GPIO=y
-CONFIG_BCMA_POSSIBLE=y
-CONFIG_BCMA=m
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_SOC=y
-CONFIG_BCMA_DRIVER_PCI=y
-CONFIG_BCMA_SFLASH=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_DRIVER_GPIO=y
-# CONFIG_BCMA_DEBUG is not set
-
-#
-# Multifunction device drivers
-#
-CONFIG_MFD_CORE=y
-CONFIG_MFD_BCM590XX=m
-CONFIG_MFD_BD9571MWV=m
-CONFIG_MFD_AXP20X=m
-CONFIG_MFD_AXP20X_I2C=m
-CONFIG_MFD_CROS_EC_DEV=m
-CONFIG_MFD_MADERA=m
-CONFIG_MFD_MADERA_I2C=m
-CONFIG_MFD_MADERA_SPI=m
-CONFIG_MFD_CS47L15=y
-CONFIG_MFD_CS47L35=y
-CONFIG_MFD_CS47L85=y
-CONFIG_MFD_CS47L90=y
-CONFIG_MFD_CS47L92=y
-CONFIG_PMIC_DA9052=y
-CONFIG_MFD_DA9052_SPI=y
-CONFIG_MFD_DA9062=m
-CONFIG_MFD_DA9063=m
-CONFIG_MFD_DA9150=m
-CONFIG_MFD_DLN2=m
-CONFIG_MFD_MC13XXX=m
-CONFIG_MFD_MC13XXX_SPI=m
-CONFIG_MFD_MC13XXX_I2C=m
-CONFIG_MFD_MP2629=m
-CONFIG_HTC_PASIC3=m
-CONFIG_MFD_INTEL_QUARK_I2C_GPIO=m
-CONFIG_LPC_ICH=m
-CONFIG_LPC_SCH=m
-CONFIG_INTEL_SOC_PMIC_BXTWC=m
-CONFIG_INTEL_SOC_PMIC_CHTDC_TI=m
-CONFIG_INTEL_SOC_PMIC_MRFLD=m
-CONFIG_MFD_INTEL_LPSS=m
-CONFIG_MFD_INTEL_LPSS_ACPI=m
-CONFIG_MFD_INTEL_LPSS_PCI=m
-CONFIG_MFD_INTEL_PMC_BXT=m
-CONFIG_MFD_INTEL_PMT=m
-CONFIG_MFD_IQS62X=m
-CONFIG_MFD_JANZ_CMODIO=m
-CONFIG_MFD_KEMPLD=m
-CONFIG_MFD_88PM800=m
-CONFIG_MFD_88PM805=m
-CONFIG_MFD_MAX14577=m
-CONFIG_MFD_MAX77693=m
-CONFIG_MFD_MAX77714=m
-CONFIG_MFD_MAX8907=m
-CONFIG_MFD_MT6360=m
-CONFIG_MFD_MT6370=m
-CONFIG_MFD_MT6397=m
-CONFIG_MFD_MENF21BMC=m
-CONFIG_MFD_OCELOT=m
-CONFIG_EZX_PCAP=y
-CONFIG_MFD_VIPERBOARD=m
-CONFIG_MFD_RETU=m
-CONFIG_MFD_PCF50633=m
-CONFIG_PCF50633_ADC=m
-CONFIG_PCF50633_GPIO=m
-CONFIG_UCB1400_CORE=m
-CONFIG_MFD_SY7636A=m
-CONFIG_MFD_RDC321X=m
-CONFIG_MFD_RT4831=m
-CONFIG_MFD_RT5033=m
-CONFIG_MFD_RT5120=m
-CONFIG_MFD_SI476X_CORE=m
-CONFIG_MFD_SIMPLE_MFD_I2C=m
-CONFIG_MFD_SM501=m
-CONFIG_MFD_SM501_GPIO=y
-CONFIG_MFD_SKY81452=m
-CONFIG_MFD_SYSCON=y
-CONFIG_MFD_TI_AM335X_TSCADC=m
-CONFIG_MFD_LP3943=m
-CONFIG_MFD_TI_LMU=m
-CONFIG_TPS6105X=m
-CONFIG_TPS65010=m
-CONFIG_TPS6507X=m
-CONFIG_MFD_TPS65086=m
-CONFIG_MFD_TI_LP873X=m
-CONFIG_MFD_TPS65912=y
-CONFIG_MFD_TPS65912_I2C=m
-CONFIG_MFD_TPS65912_SPI=y
-CONFIG_MFD_WL1273_CORE=m
-CONFIG_MFD_LM3533=m
-CONFIG_MFD_TQMX86=m
-CONFIG_MFD_VX855=m
-CONFIG_MFD_ARIZONA=m
-CONFIG_MFD_ARIZONA_I2C=m
-CONFIG_MFD_ARIZONA_SPI=m
-CONFIG_MFD_CS47L24=y
-CONFIG_MFD_WM5102=y
-CONFIG_MFD_WM5110=y
-CONFIG_MFD_WM8997=y
-CONFIG_MFD_WM8998=y
-CONFIG_MFD_WM831X=y
-CONFIG_MFD_WM831X_SPI=y
-CONFIG_MFD_WM8994=m
-CONFIG_MFD_WCD934X=m
-CONFIG_MFD_ATC260X=m
-CONFIG_MFD_ATC260X_I2C=m
-CONFIG_RAVE_SP_CORE=m
-CONFIG_MFD_INTEL_M10_BMC=m
-# end of Multifunction device drivers
-
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=m
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
-CONFIG_REGULATOR_USERSPACE_CONSUMER=m
-CONFIG_REGULATOR_88PG86X=m
-CONFIG_REGULATOR_88PM800=m
-CONFIG_REGULATOR_ACT8865=m
-CONFIG_REGULATOR_AD5398=m
-CONFIG_REGULATOR_ARIZONA_LDO1=m
-CONFIG_REGULATOR_ARIZONA_MICSUPP=m
-CONFIG_REGULATOR_ATC260X=m
-CONFIG_REGULATOR_AXP20X=m
-CONFIG_REGULATOR_BCM590XX=m
-CONFIG_REGULATOR_BD9571MWV=m
-CONFIG_REGULATOR_DA9052=m
-CONFIG_REGULATOR_DA9062=m
-CONFIG_REGULATOR_DA9210=m
-CONFIG_REGULATOR_DA9211=m
-CONFIG_REGULATOR_FAN53555=m
-CONFIG_REGULATOR_GPIO=m
-CONFIG_REGULATOR_ISL9305=m
-CONFIG_REGULATOR_ISL6271A=m
-CONFIG_REGULATOR_LM363X=m
-CONFIG_REGULATOR_LP3971=m
-CONFIG_REGULATOR_LP3972=m
-CONFIG_REGULATOR_LP872X=m
-CONFIG_REGULATOR_LP8755=m
-CONFIG_REGULATOR_LTC3589=m
-CONFIG_REGULATOR_LTC3676=m
-CONFIG_REGULATOR_MAX14577=m
-CONFIG_REGULATOR_MAX1586=m
-CONFIG_REGULATOR_MAX8649=m
-CONFIG_REGULATOR_MAX8660=m
-CONFIG_REGULATOR_MAX8893=m
-CONFIG_REGULATOR_MAX8907=m
-CONFIG_REGULATOR_MAX8952=m
-CONFIG_REGULATOR_MAX77693=m
-CONFIG_REGULATOR_MAX77826=m
-CONFIG_REGULATOR_MC13XXX_CORE=m
-CONFIG_REGULATOR_MC13783=m
-CONFIG_REGULATOR_MC13892=m
-CONFIG_REGULATOR_MP8859=m
-CONFIG_REGULATOR_MT6311=m
-CONFIG_REGULATOR_MT6315=m
-CONFIG_REGULATOR_MT6370=m
-CONFIG_REGULATOR_MT6323=m
-CONFIG_REGULATOR_MT6331=m
-CONFIG_REGULATOR_MT6332=m
-CONFIG_REGULATOR_MT6358=m
-CONFIG_REGULATOR_MT6359=m
-CONFIG_REGULATOR_MT6360=m
-CONFIG_REGULATOR_MT6370=m
-CONFIG_REGULATOR_MT6397=m
-CONFIG_REGULATOR_PCA9450=m
-CONFIG_REGULATOR_PCAP=m
-CONFIG_REGULATOR_PCF50633=m
-CONFIG_REGULATOR_PV88060=m
-CONFIG_REGULATOR_PV88080=m
-CONFIG_REGULATOR_PV88090=m
-CONFIG_REGULATOR_PWM=m
-CONFIG_REGULATOR_QCOM_SPMI=m
-CONFIG_REGULATOR_QCOM_USB_VBUS=m
-CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
-CONFIG_REGULATOR_RT4801=m
-CONFIG_REGULATOR_RT4831=m
-CONFIG_REGULATOR_RT5120=m
-CONFIG_REGULATOR_RT5190A=m
-CONFIG_REGULATOR_RT5033=m
-CONFIG_REGULATOR_RT5120=m
-CONFIG_REGULATOR_RT5190A=m
-CONFIG_REGULATOR_RT6160=m
-CONFIG_REGULATOR_RT6245=m
-CONFIG_REGULATOR_RTQ2134=m
-CONFIG_REGULATOR_RTMV20=m
-CONFIG_REGULATOR_RTQ6752=m
-CONFIG_REGULATOR_SKY81452=m
-CONFIG_REGULATOR_SLG51000=m
-CONFIG_REGULATOR_SY7636A=m
-CONFIG_REGULATOR_TPS51632=m
-CONFIG_REGULATOR_TPS6105X=m
-CONFIG_REGULATOR_TPS62360=m
-CONFIG_REGULATOR_TPS6286X=m
-CONFIG_REGULATOR_TPS65023=m
-CONFIG_REGULATOR_TPS6507X=m
-CONFIG_REGULATOR_TPS65086=m
-CONFIG_REGULATOR_TPS65132=m
-CONFIG_REGULATOR_TPS6524X=m
-CONFIG_REGULATOR_TPS65912=m
-CONFIG_REGULATOR_TPS68470=m
-CONFIG_REGULATOR_WM831X=m
-CONFIG_REGULATOR_WM8994=m
-CONFIG_REGULATOR_QCOM_LABIBB=m
-CONFIG_RC_CORE=m
-CONFIG_RC_MAP=m
-CONFIG_LIRC=y
-CONFIG_RC_DECODERS=y
-CONFIG_IR_NEC_DECODER=m
-CONFIG_IR_RC5_DECODER=m
-CONFIG_IR_RC6_DECODER=m
-CONFIG_IR_JVC_DECODER=m
-CONFIG_IR_SONY_DECODER=m
-CONFIG_IR_SANYO_DECODER=m
-CONFIG_IR_SHARP_DECODER=m
-CONFIG_IR_MCE_KBD_DECODER=m
-CONFIG_IR_XMP_DECODER=m
-CONFIG_IR_IMON_DECODER=m
-CONFIG_IR_RCMM_DECODER=m
-CONFIG_RC_DEVICES=y
-CONFIG_RC_ATI_REMOTE=m
-CONFIG_IR_ENE=m
-CONFIG_IR_IMON=m
-CONFIG_IR_IMON_RAW=m
-CONFIG_IR_MCEUSB=m
-CONFIG_IR_ITE_CIR=m
-CONFIG_IR_FINTEK=m
-CONFIG_IR_NUVOTON=m
-CONFIG_IR_REDRAT3=m
-CONFIG_IR_STREAMZAP=m
-CONFIG_IR_WINBOND_CIR=m
-CONFIG_IR_IGORPLUGUSB=m
-CONFIG_IR_IGUANA=m
-CONFIG_IR_TTUSBIR=m
-CONFIG_RC_LOOPBACK=m
-CONFIG_IR_SERIAL=m
-CONFIG_IR_SERIAL_TRANSMITTER=y
-CONFIG_RC_XBOX_DVD=m
-CONFIG_IR_TOY=m
-CONFIG_CEC_CORE=m
-CONFIG_CEC_NOTIFIER=y
-CONFIG_CEC_PIN=y
-
-#
-# CEC support
-#
-CONFIG_MEDIA_CEC_RC=y
-# CONFIG_CEC_PIN_ERROR_INJ is not set
-CONFIG_MEDIA_CEC_SUPPORT=y
-CONFIG_CEC_CH7322=m
-CONFIG_CEC_CROS_EC=m
-CONFIG_CEC_GPIO=m
-CONFIG_CEC_SECO=m
-CONFIG_CEC_SECO_RC=y
-CONFIG_USB_PULSE8_CEC=m
-CONFIG_USB_RAINSHADOW_CEC=m
-# end of CEC support
-
-CONFIG_MEDIA_SUPPORT=m
-CONFIG_MEDIA_SUPPORT_FILTER=y
-CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
-
-#
-# Media device types
-#
-CONFIG_MEDIA_PLATFORM_DRIVERS=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_SDR_SUPPORT=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-# CONFIG_MEDIA_TEST_SUPPORT is not set
-# end of Media device types
-
-CONFIG_VIDEO_DEV=m
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_DVB_CORE=m
-
-#
-# Video4Linux options
-#
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L2_I2C=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_TUNER=m
-CONFIG_V4L2_MEM2MEM_DEV=m
-CONFIG_V4L2_FLASH_LED_CLASS=m
-CONFIG_V4L2_FWNODE=m
-CONFIG_V4L2_ASYNC=m
-CONFIG_VIDEOBUF_GEN=m
-CONFIG_VIDEOBUF_DMA_SG=m
-CONFIG_VIDEOBUF_VMALLOC=m
-# end of Video4Linux options
-
-#
-# Media controller options
-#
-CONFIG_MEDIA_CONTROLLER_DVB=y
-# end of Media controller options
-
-#
-# Digital TV options
-#
-# CONFIG_DVB_MMAP is not set
-CONFIG_DVB_NET=y
-CONFIG_DVB_MAX_ADAPTERS=8
-CONFIG_DVB_DYNAMIC_MINORS=y
-# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
-# CONFIG_DVB_ULE_DEBUG is not set
-# end of Digital TV options
-
-#
-# Media drivers
-#
-
-#
-# Drivers filtered as selected at 'Filter media drivers'
-#
-CONFIG_MEDIA_USB_SUPPORT=y
-
-#
-# Webcam devices
-#
-CONFIG_USB_VIDEO_CLASS=m
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-CONFIG_USB_M5602=m
-CONFIG_USB_STV06XX=m
-CONFIG_USB_GL860=m
-CONFIG_USB_GSPCA_BENQ=m
-CONFIG_USB_GSPCA_CONEX=m
-CONFIG_USB_GSPCA_CPIA1=m
-CONFIG_USB_GSPCA_DTCS033=m
-CONFIG_USB_GSPCA_ETOMS=m
-CONFIG_USB_GSPCA_FINEPIX=m
-CONFIG_USB_GSPCA_JEILINJ=m
-CONFIG_USB_GSPCA_JL2005BCD=m
-CONFIG_USB_GSPCA_KINECT=m
-CONFIG_USB_GSPCA_KONICA=m
-CONFIG_USB_GSPCA_MARS=m
-CONFIG_USB_GSPCA_MR97310A=m
-CONFIG_USB_GSPCA_NW80X=m
-CONFIG_USB_GSPCA_OV519=m
-CONFIG_USB_GSPCA_OV534=m
-CONFIG_USB_GSPCA_OV534_9=m
-CONFIG_USB_GSPCA_PAC207=m
-CONFIG_USB_GSPCA_PAC7302=m
-CONFIG_USB_GSPCA_PAC7311=m
-CONFIG_USB_GSPCA_SE401=m
-CONFIG_USB_GSPCA_SN9C2028=m
-CONFIG_USB_GSPCA_SN9C20X=m
-CONFIG_USB_GSPCA_SONIXB=m
-CONFIG_USB_GSPCA_SONIXJ=m
-CONFIG_USB_GSPCA_SPCA500=m
-CONFIG_USB_GSPCA_SPCA501=m
-CONFIG_USB_GSPCA_SPCA505=m
-CONFIG_USB_GSPCA_SPCA506=m
-CONFIG_USB_GSPCA_SPCA508=m
-CONFIG_USB_GSPCA_SPCA561=m
-CONFIG_USB_GSPCA_SPCA1528=m
-CONFIG_USB_GSPCA_SQ905=m
-CONFIG_USB_GSPCA_SQ905C=m
-CONFIG_USB_GSPCA_SQ930X=m
-CONFIG_USB_GSPCA_STK014=m
-CONFIG_USB_GSPCA_STK1135=m
-CONFIG_USB_GSPCA_STV0680=m
-CONFIG_USB_GSPCA_SUNPLUS=m
-CONFIG_USB_GSPCA_T613=m
-CONFIG_USB_GSPCA_TOPRO=m
-CONFIG_USB_GSPCA_TOUPTEK=m
-CONFIG_USB_GSPCA_TV8532=m
-CONFIG_USB_GSPCA_VC032X=m
-CONFIG_USB_GSPCA_VICAM=m
-CONFIG_USB_GSPCA_XIRLINK_CIT=m
-CONFIG_USB_GSPCA_ZC3XX=m
-CONFIG_USB_PWC=m
-# CONFIG_USB_PWC_DEBUG is not set
-CONFIG_USB_PWC_INPUT_EVDEV=y
-CONFIG_VIDEO_CPIA2=m
-CONFIG_USB_ZR364XX=m
-CONFIG_USB_STKWEBCAM=m
-CONFIG_USB_S2255=m
-CONFIG_VIDEO_USBTV=m
-
-#
-# Analog TV USB devices
-#
-CONFIG_VIDEO_PVRUSB2=m
-CONFIG_VIDEO_PVRUSB2_SYSFS=y
-CONFIG_VIDEO_PVRUSB2_DVB=y
-# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
-CONFIG_VIDEO_HDPVR=m
-CONFIG_VIDEO_STK1160_COMMON=m
-CONFIG_VIDEO_STK1160=m
-CONFIG_VIDEO_GO7007=m
-CONFIG_VIDEO_GO7007_USB=m
-CONFIG_VIDEO_GO7007_LOADER=m
-CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
-
-#
-# Analog/digital TV USB devices
-#
-CONFIG_VIDEO_AU0828=m
-CONFIG_VIDEO_AU0828_V4L2=y
-CONFIG_VIDEO_AU0828_RC=y
-CONFIG_VIDEO_CX231XX=m
-CONFIG_VIDEO_CX231XX_RC=y
-CONFIG_VIDEO_CX231XX_ALSA=m
-CONFIG_VIDEO_CX231XX_DVB=m
-CONFIG_VIDEO_TM6000=m
-CONFIG_VIDEO_TM6000_ALSA=m
-CONFIG_VIDEO_TM6000_DVB=m
-
-#
-# Digital TV USB devices
-#
-CONFIG_DVB_USB=m
-# CONFIG_DVB_USB_DEBUG is not set
-CONFIG_DVB_USB_DIB3000MC=m
-CONFIG_DVB_USB_A800=m
-CONFIG_DVB_USB_DIBUSB_MB=m
-CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
-CONFIG_DVB_USB_DIBUSB_MC=m
-CONFIG_DVB_USB_DIB0700=m
-CONFIG_DVB_USB_UMT_010=m
-CONFIG_DVB_USB_CXUSB=m
-CONFIG_DVB_USB_CXUSB_ANALOG=y
-CONFIG_DVB_USB_M920X=m
-CONFIG_DVB_USB_DIGITV=m
-CONFIG_DVB_USB_VP7045=m
-CONFIG_DVB_USB_VP702X=m
-CONFIG_DVB_USB_GP8PSK=m
-CONFIG_DVB_USB_NOVA_T_USB2=m
-CONFIG_DVB_USB_TTUSB2=m
-CONFIG_DVB_USB_DTT200U=m
-CONFIG_DVB_USB_OPERA1=m
-CONFIG_DVB_USB_AF9005=m
-CONFIG_DVB_USB_AF9005_REMOTE=m
-CONFIG_DVB_USB_PCTV452E=m
-CONFIG_DVB_USB_DW2102=m
-CONFIG_DVB_USB_CINERGY_T2=m
-CONFIG_DVB_USB_DTV5100=m
-CONFIG_DVB_USB_AZ6027=m
-CONFIG_DVB_USB_TECHNISAT_USB2=m
-CONFIG_DVB_USB_V2=m
-CONFIG_DVB_USB_AF9015=m
-CONFIG_DVB_USB_AF9035=m
-CONFIG_DVB_USB_ANYSEE=m
-CONFIG_DVB_USB_AU6610=m
-CONFIG_DVB_USB_AZ6007=m
-CONFIG_DVB_USB_CE6230=m
-CONFIG_DVB_USB_EC168=m
-CONFIG_DVB_USB_GL861=m
-CONFIG_DVB_USB_LME2510=m
-CONFIG_DVB_USB_MXL111SF=m
-CONFIG_DVB_USB_RTL28XXU=m
-CONFIG_DVB_USB_DVBSKY=m
-CONFIG_DVB_USB_ZD1301=m
-CONFIG_DVB_TTUSB_BUDGET=m
-CONFIG_DVB_TTUSB_DEC=m
-CONFIG_SMS_USB_DRV=m
-CONFIG_DVB_B2C2_FLEXCOP_USB=m
-# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
-CONFIG_DVB_AS102=m
-
-#
-# Webcam, TV (analog/digital) USB devices
-#
-CONFIG_VIDEO_EM28XX=m
-CONFIG_VIDEO_EM28XX_V4L2=m
-CONFIG_VIDEO_EM28XX_ALSA=m
-CONFIG_VIDEO_EM28XX_DVB=m
-CONFIG_VIDEO_EM28XX_RC=m
-
-#
-# Software defined radio USB devices
-#
-CONFIG_USB_AIRSPY=m
-CONFIG_USB_HACKRF=m
-CONFIG_USB_MSI2500=m
-CONFIG_MEDIA_PCI_SUPPORT=y
-
-#
-# Media capture support
-#
-CONFIG_VIDEO_MEYE=m
-CONFIG_VIDEO_SOLO6X10=m
-CONFIG_VIDEO_TW5864=m
-CONFIG_VIDEO_TW68=m
-CONFIG_VIDEO_TW686X=m
-
-#
-# Media capture/analog TV support
-#
-CONFIG_VIDEO_IVTV=m
-CONFIG_VIDEO_IVTV_ALSA=m
-CONFIG_VIDEO_FB_IVTV=m
-# CONFIG_VIDEO_FB_IVTV_FORCE_PAT is not set
-CONFIG_VIDEO_HEXIUM_GEMINI=m
-CONFIG_VIDEO_HEXIUM_ORION=m
-CONFIG_VIDEO_MXB=m
-CONFIG_VIDEO_DT3155=m
-
-#
-# Media capture/analog/hybrid TV support
-#
-CONFIG_VIDEO_CX18=m
-CONFIG_VIDEO_CX18_ALSA=m
-CONFIG_VIDEO_CX23885=m
-CONFIG_MEDIA_ALTERA_CI=m
-CONFIG_VIDEO_CX25821=m
-CONFIG_VIDEO_CX25821_ALSA=m
-CONFIG_VIDEO_CX88=m
-CONFIG_VIDEO_CX88_ALSA=m
-CONFIG_VIDEO_CX88_BLACKBIRD=m
-CONFIG_VIDEO_CX88_DVB=m
-CONFIG_VIDEO_CX88_ENABLE_VP3054=y
-CONFIG_VIDEO_CX88_VP3054=m
-CONFIG_VIDEO_CX88_MPEG=m
-CONFIG_VIDEO_BT848=m
-CONFIG_DVB_BT8XX=m
-CONFIG_VIDEO_SAA7134=m
-CONFIG_VIDEO_SAA7134_ALSA=m
-CONFIG_VIDEO_SAA7134_RC=y
-CONFIG_VIDEO_SAA7134_DVB=m
-CONFIG_VIDEO_SAA7134_GO7007=m
-CONFIG_VIDEO_SAA7164=m
-# CONFIG_VIDEO_COBALT is not set
-
-#
-# Media digital TV PCI Adapters
-#
-CONFIG_DVB_BUDGET_CORE=m
-CONFIG_DVB_BUDGET=m
-CONFIG_DVB_BUDGET_CI=m
-CONFIG_DVB_BUDGET_AV=m
-CONFIG_DVB_B2C2_FLEXCOP_PCI=m
-# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
-CONFIG_DVB_PLUTO2=m
-CONFIG_DVB_DM1105=m
-CONFIG_DVB_PT1=m
-CONFIG_DVB_PT3=m
-CONFIG_MANTIS_CORE=m
-CONFIG_DVB_MANTIS=m
-CONFIG_DVB_HOPPER=m
-CONFIG_DVB_NGENE=m
-CONFIG_DVB_DDBRIDGE=m
-# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set
-CONFIG_DVB_SMIPCIE=m
-CONFIG_DVB_NETUP_UNIDVB=m
-CONFIG_VIDEO_IPU3_CIO2=m
-CONFIG_CIO2_BRIDGE=y
-CONFIG_RADIO_ADAPTERS=y
-CONFIG_RADIO_TEA575X=m
-CONFIG_RADIO_SI470X=m
-CONFIG_USB_SI470X=m
-CONFIG_I2C_SI470X=m
-CONFIG_RADIO_SI4713=m
-CONFIG_USB_SI4713=m
-CONFIG_PLATFORM_SI4713=m
-CONFIG_I2C_SI4713=m
-CONFIG_RADIO_SI476X=m
-CONFIG_USB_MR800=m
-CONFIG_USB_DSBR=m
-CONFIG_RADIO_MAXIRADIO=m
-CONFIG_RADIO_SHARK=m
-CONFIG_RADIO_SHARK2=m
-CONFIG_USB_KEENE=m
-CONFIG_USB_RAREMONO=m
-CONFIG_USB_MA901=m
-CONFIG_RADIO_TEA5764=m
-CONFIG_RADIO_SAA7706H=m
-CONFIG_RADIO_TEF6862=m
-CONFIG_RADIO_WL1273=m
-CONFIG_RADIO_WL128X=m
-CONFIG_MEDIA_COMMON_OPTIONS=y
-
-#
-# common driver options
-#
-CONFIG_VIDEO_CX2341X=m
-CONFIG_VIDEO_TVEEPROM=m
-CONFIG_TTPCI_EEPROM=m
-CONFIG_CYPRESS_FIRMWARE=m
-CONFIG_VIDEOBUF2_CORE=m
-CONFIG_VIDEOBUF2_V4L2=m
-CONFIG_VIDEOBUF2_MEMOPS=m
-CONFIG_VIDEOBUF2_DMA_CONTIG=m
-CONFIG_VIDEOBUF2_VMALLOC=m
-CONFIG_VIDEOBUF2_DMA_SG=m
-CONFIG_VIDEOBUF2_DVB=m
-CONFIG_DVB_B2C2_FLEXCOP=m
-CONFIG_VIDEO_SAA7146=m
-CONFIG_VIDEO_SAA7146_VV=m
-CONFIG_SMS_SIANO_MDTV=m
-CONFIG_SMS_SIANO_RC=y
-# CONFIG_SMS_SIANO_DEBUGFS is not set
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_CAFE_CCIC=m
-CONFIG_VIDEO_CADENCE=y
-CONFIG_VIDEO_CADENCE_CSI2RX=m
-CONFIG_VIDEO_CADENCE_CSI2TX=m
-CONFIG_VIDEO_ASPEED=m
-CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
-CONFIG_DVB_PLATFORM_DRIVERS=y
-CONFIG_SDR_PLATFORM_DRIVERS=y
-
-#
-# MMC/SDIO DVB adapters
-#
-CONFIG_SMS_SDIO_DRV=m
-
-#
-# FireWire (IEEE 1394) Adapters
-#
-CONFIG_DVB_FIREDTV=m
-CONFIG_DVB_FIREDTV_INPUT=y
-# end of Media drivers
-
-#
-# Media ancillary drivers
-#
-CONFIG_MEDIA_ATTACH=y
-
-#
-# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
-#
-CONFIG_VIDEO_IR_I2C=m
-
-#
-# Audio decoders, processors and mixers
-#
-CONFIG_VIDEO_TVAUDIO=m
-CONFIG_VIDEO_TDA7432=m
-CONFIG_VIDEO_TDA9840=m
-# CONFIG_VIDEO_TDA1997X is not set
-CONFIG_VIDEO_TEA6415C=m
-CONFIG_VIDEO_TEA6420=m
-CONFIG_VIDEO_MSP3400=m
-CONFIG_VIDEO_CS3308=m
-CONFIG_VIDEO_CS5345=m
-CONFIG_VIDEO_CS53L32A=m
-# CONFIG_VIDEO_TLV320AIC23B is not set
-CONFIG_VIDEO_UDA1342=m
-CONFIG_VIDEO_WM8775=m
-CONFIG_VIDEO_WM8739=m
-CONFIG_VIDEO_VP27SMPX=m
-CONFIG_VIDEO_SONY_BTF_MPX=m
-# end of Audio decoders, processors and mixers
-
-#
-# RDS decoders
-#
-CONFIG_VIDEO_SAA6588=m
-# end of RDS decoders
-
-#
-# Video decoders
-#
-# CONFIG_VIDEO_ADV7180 is not set
-# CONFIG_VIDEO_ADV7183 is not set
-# CONFIG_VIDEO_ADV7604 is not set
-# CONFIG_VIDEO_ADV7842 is not set
-CONFIG_VIDEO_BT819=m
-CONFIG_VIDEO_BT856=m
-CONFIG_VIDEO_BT866=m
-CONFIG_VIDEO_ISL7998X=m
-CONFIG_VIDEO_KS0127=m
-# CONFIG_VIDEO_ML86V7667 is not set
-CONFIG_VIDEO_SAA7110=m
-CONFIG_VIDEO_SAA711X=m
-# CONFIG_VIDEO_TC358743 is not set
-# CONFIG_VIDEO_TVP514X is not set
-CONFIG_VIDEO_TVP5150=m
-# CONFIG_VIDEO_TVP7002 is not set
-CONFIG_VIDEO_TW2804=m
-CONFIG_VIDEO_TW9903=m
-CONFIG_VIDEO_TW9906=m
-# CONFIG_VIDEO_TW9910 is not set
-CONFIG_VIDEO_VPX3220=m
-
-#
-# Video and audio decoders
-#
-CONFIG_VIDEO_SAA717X=m
-CONFIG_VIDEO_CX25840=m
-# end of Video decoders
-
-#
-# Video encoders
-#
-CONFIG_VIDEO_SAA7127=m
-CONFIG_VIDEO_SAA7185=m
-CONFIG_VIDEO_ADV7170=m
-CONFIG_VIDEO_ADV7175=m
-# CONFIG_VIDEO_ADV7343 is not set
-# CONFIG_VIDEO_ADV7393 is not set
-# CONFIG_VIDEO_ADV7511 is not set
-# CONFIG_VIDEO_AD9389B is not set
-# CONFIG_VIDEO_AK881X is not set
-# CONFIG_VIDEO_THS8200 is not set
-# end of Video encoders
-
-#
-# Video improvement chips
-#
-CONFIG_VIDEO_UPD64031A=m
-CONFIG_VIDEO_UPD64083=m
-# end of Video improvement chips
-
-#
-# Audio/Video compression chips
-#
-CONFIG_VIDEO_SAA6752HS=m
-# end of Audio/Video compression chips
-
-#
-# SDR tuner chips
-#
-# CONFIG_SDR_MAX2175 is not set
-# end of SDR tuner chips
-
-#
-# Miscellaneous helper chips
-#
-# CONFIG_VIDEO_THS7303 is not set
-CONFIG_VIDEO_M52790=m
-# CONFIG_VIDEO_I2C is not set
-# CONFIG_VIDEO_ST_MIPID02 is not set
-# end of Miscellaneous helper chips
-
-#
-# Camera sensor devices
-#
-CONFIG_VIDEO_APTINA_PLL=m
-CONFIG_VIDEO_CCS_PLL=m
-CONFIG_VIDEO_HI556=m
-CONFIG_VIDEO_HI846=m
-CONFIG_VIDEO_HI847=m
-CONFIG_VIDEO_IMX208=m
-CONFIG_VIDEO_IMX214=m
-CONFIG_VIDEO_IMX219=m
-CONFIG_VIDEO_IMX258=m
-CONFIG_VIDEO_IMX274=m
-CONFIG_VIDEO_IMX290=m
-CONFIG_VIDEO_IMX319=m
-CONFIG_VIDEO_IMX355=m
-CONFIG_VIDEO_OV02A10=m
-CONFIG_VIDEO_OV08D10=m
-CONFIG_VIDEO_OV2640=m
-CONFIG_VIDEO_OV2659=m
-CONFIG_VIDEO_OV2680=m
-CONFIG_VIDEO_OV2685=m
-CONFIG_VIDEO_OV2740=m
-CONFIG_VIDEO_OV5647=m
-CONFIG_VIDEO_OV5648=m
-CONFIG_VIDEO_OV6650=m
-CONFIG_VIDEO_OV5670=m
-CONFIG_VIDEO_OV5675=m
-CONFIG_VIDEO_OV5695=m
-CONFIG_VIDEO_OV7251=m
-CONFIG_VIDEO_OV772X=m
-CONFIG_VIDEO_OV7640=m
-CONFIG_VIDEO_OV7670=m
-CONFIG_VIDEO_OV7740=m
-CONFIG_VIDEO_OV8856=m
-CONFIG_VIDEO_OV8865=m
-CONFIG_VIDEO_OV9640=m
-CONFIG_VIDEO_OV9650=m
-CONFIG_VIDEO_OV9734=m
-CONFIG_VIDEO_OV13858=m
-CONFIG_VIDEO_OV13B10=m
-CONFIG_VIDEO_VS6624=m
-CONFIG_VIDEO_MT9M001=m
-CONFIG_VIDEO_MT9M032=m
-CONFIG_VIDEO_MT9M111=m
-CONFIG_VIDEO_MT9P031=m
-CONFIG_VIDEO_MT9T001=m
-CONFIG_VIDEO_MT9T112=m
-CONFIG_VIDEO_MT9V011=m
-CONFIG_VIDEO_MT9V032=m
-CONFIG_VIDEO_MT9V111=m
-CONFIG_VIDEO_SR030PC30=m
-CONFIG_VIDEO_NOON010PC30=m
-CONFIG_VIDEO_OG01A1B=m
-CONFIG_VIDEO_M5MOLS=m
-CONFIG_VIDEO_MAX9271_LIB=m
-CONFIG_VIDEO_RDACM20=m
-CONFIG_VIDEO_RDACM21=m
-CONFIG_VIDEO_RJ54N1=m
-CONFIG_VIDEO_S5K6AA=m
-CONFIG_VIDEO_S5K6A3=m
-CONFIG_VIDEO_S5K4ECGX=m
-CONFIG_VIDEO_S5K5BAF=m
-CONFIG_VIDEO_CCS=m
-CONFIG_VIDEO_ET8EK8=m
-CONFIG_VIDEO_S5C73M3=m
-# end of Camera sensor devices
-
-#
-# Lens drivers
-#
-CONFIG_VIDEO_AD5820=m
-CONFIG_VIDEO_AK7375=m
-CONFIG_VIDEO_DW9714=m
-CONFIG_VIDEO_DW9768=m
-CONFIG_VIDEO_DW9807_VCM=m
-# end of Lens drivers
-
-#
-# Flash devices
-#
-CONFIG_VIDEO_ADP1653=m
-CONFIG_VIDEO_LM3560=m
-CONFIG_VIDEO_LM3646=m
-# end of Flash devices
-
-#
-# SPI helper chips
-#
-# CONFIG_VIDEO_GS1662 is not set
-# end of SPI helper chips
-
-#
-# Media SPI Adapters
-#
-CONFIG_CXD2880_SPI_DRV=m
-# end of Media SPI Adapters
-
-CONFIG_MEDIA_TUNER=m
-
-#
-# Customize TV tuners
-#
-CONFIG_MEDIA_TUNER_SIMPLE=m
-CONFIG_MEDIA_TUNER_TDA18250=m
-CONFIG_MEDIA_TUNER_TDA8290=m
-CONFIG_MEDIA_TUNER_TDA827X=m
-CONFIG_MEDIA_TUNER_TDA18271=m
-CONFIG_MEDIA_TUNER_TDA9887=m
-CONFIG_MEDIA_TUNER_TEA5761=m
-CONFIG_MEDIA_TUNER_TEA5767=m
-CONFIG_MEDIA_TUNER_MSI001=m
-CONFIG_MEDIA_TUNER_MT20XX=m
-CONFIG_MEDIA_TUNER_MT2060=m
-CONFIG_MEDIA_TUNER_MT2063=m
-CONFIG_MEDIA_TUNER_MT2266=m
-CONFIG_MEDIA_TUNER_MT2131=m
-CONFIG_MEDIA_TUNER_QT1010=m
-CONFIG_MEDIA_TUNER_XC2028=m
-CONFIG_MEDIA_TUNER_XC5000=m
-CONFIG_MEDIA_TUNER_XC4000=m
-CONFIG_MEDIA_TUNER_MXL5005S=m
-CONFIG_MEDIA_TUNER_MXL5007T=m
-CONFIG_MEDIA_TUNER_MC44S803=m
-CONFIG_MEDIA_TUNER_MAX2165=m
-CONFIG_MEDIA_TUNER_TDA18218=m
-CONFIG_MEDIA_TUNER_FC0011=m
-CONFIG_MEDIA_TUNER_FC0012=m
-CONFIG_MEDIA_TUNER_FC0013=m
-CONFIG_MEDIA_TUNER_TDA18212=m
-CONFIG_MEDIA_TUNER_E4000=m
-CONFIG_MEDIA_TUNER_FC2580=m
-CONFIG_MEDIA_TUNER_M88RS6000T=m
-CONFIG_MEDIA_TUNER_TUA9001=m
-CONFIG_MEDIA_TUNER_SI2157=m
-CONFIG_MEDIA_TUNER_IT913X=m
-CONFIG_MEDIA_TUNER_R820T=m
-CONFIG_MEDIA_TUNER_MXL301RF=m
-CONFIG_MEDIA_TUNER_QM1D1C0042=m
-CONFIG_MEDIA_TUNER_QM1D1B0004=m
-CONFIG_MEDIA_TUNER_AV201X=m
-CONFIG_MEDIA_TUNER_STV6120=m
-# end of Customize TV tuners
-
-#
-# Customise DVB Frontends
-#
-
-#
-# Multistandard (satellite) frontends
-#
-CONFIG_DVB_STB0899=m
-CONFIG_DVB_STB6100=m
-CONFIG_DVB_STV090x=m
-CONFIG_DVB_STV0910=m
-CONFIG_DVB_STV6110x=m
-CONFIG_DVB_STV6111=m
-CONFIG_DVB_MXL5XX=m
-CONFIG_DVB_M88DS3103=m
-
-#
-# Multistandard (cable + terrestrial) frontends
-#
-CONFIG_DVB_DRXK=m
-CONFIG_DVB_TDA18271C2DD=m
-CONFIG_DVB_SI2165=m
-CONFIG_DVB_MN88472=m
-CONFIG_DVB_MN88473=m
-
-#
-# DVB-S (satellite) frontends
-#
-CONFIG_DVB_CX24110=m
-CONFIG_DVB_CX24123=m
-CONFIG_DVB_MT312=m
-CONFIG_DVB_ZL10036=m
-CONFIG_DVB_ZL10039=m
-CONFIG_DVB_S5H1420=m
-CONFIG_DVB_STV0288=m
-CONFIG_DVB_STB6000=m
-CONFIG_DVB_STV0299=m
-CONFIG_DVB_STV6110=m
-CONFIG_DVB_STV0900=m
-CONFIG_DVB_TDA8083=m
-CONFIG_DVB_TDA10086=m
-CONFIG_DVB_TDA8261=m
-CONFIG_DVB_VES1X93=m
-CONFIG_DVB_TUNER_ITD1000=m
-CONFIG_DVB_TUNER_CX24113=m
-CONFIG_DVB_TDA826X=m
-CONFIG_DVB_TUA6100=m
-CONFIG_DVB_CX24116=m
-CONFIG_DVB_CX24117=m
-CONFIG_DVB_CX24120=m
-CONFIG_DVB_SI21XX=m
-CONFIG_DVB_TS2020=m
-CONFIG_DVB_DS3000=m
-CONFIG_DVB_MB86A16=m
-CONFIG_DVB_TDA10071=m
-
-#
-# DVB-T (terrestrial) frontends
-#
-CONFIG_DVB_SP887X=m
-CONFIG_DVB_CX22700=m
-CONFIG_DVB_CX22702=m
-# CONFIG_DVB_S5H1432 is not set
-CONFIG_DVB_DRXD=m
-CONFIG_DVB_L64781=m
-CONFIG_DVB_TDA1004X=m
-CONFIG_DVB_NXT6000=m
-CONFIG_DVB_MT352=m
-CONFIG_DVB_ZL10353=m
-CONFIG_DVB_DIB3000MB=m
-CONFIG_DVB_DIB3000MC=m
-CONFIG_DVB_DIB7000M=m
-CONFIG_DVB_DIB7000P=m
-# CONFIG_DVB_DIB9000 is not set
-CONFIG_DVB_TDA10048=m
-CONFIG_DVB_AF9013=m
-CONFIG_DVB_EC100=m
-CONFIG_DVB_STV0367=m
-CONFIG_DVB_CXD2820R=m
-CONFIG_DVB_CXD2841ER=m
-CONFIG_DVB_RTL2830=m
-CONFIG_DVB_RTL2832=m
-CONFIG_DVB_RTL2832_SDR=m
-CONFIG_DVB_SI2168=m
-CONFIG_DVB_AS102_FE=m
-CONFIG_DVB_ZD1301_DEMOD=m
-CONFIG_DVB_GP8PSK_FE=m
-# CONFIG_DVB_CXD2880 is not set
-
-#
-# DVB-C (cable) frontends
-#
-CONFIG_DVB_VES1820=m
-CONFIG_DVB_TDA10021=m
-CONFIG_DVB_TDA10023=m
-CONFIG_DVB_STV0297=m
-
-#
-# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
-#
-CONFIG_DVB_NXT200X=m
-CONFIG_DVB_OR51211=m
-CONFIG_DVB_OR51132=m
-CONFIG_DVB_BCM3510=m
-CONFIG_DVB_LGDT330X=m
-CONFIG_DVB_LGDT3305=m
-CONFIG_DVB_LGDT3306A=m
-CONFIG_DVB_LG2160=m
-CONFIG_DVB_S5H1409=m
-CONFIG_DVB_AU8522=m
-CONFIG_DVB_AU8522_DTV=m
-CONFIG_DVB_AU8522_V4L=m
-CONFIG_DVB_S5H1411=m
-CONFIG_DVB_MXL692=m
-
-#
-# ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_S921=m
-CONFIG_DVB_DIB8000=m
-CONFIG_DVB_MB86A20S=m
-
-#
-# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_TC90522=m
-# CONFIG_DVB_MN88443X is not set
-
-#
-# Digital terrestrial only tuners/PLL
-#
-CONFIG_DVB_PLL=m
-CONFIG_DVB_TUNER_DIB0070=m
-CONFIG_DVB_TUNER_DIB0090=m
-
-#
-# SEC control devices for DVB-S
-#
-CONFIG_DVB_DRX39XYJ=m
-CONFIG_DVB_LNBH25=m
-# CONFIG_DVB_LNBH29 is not set
-CONFIG_DVB_LNBP21=m
-CONFIG_DVB_LNBP22=m
-CONFIG_DVB_ISL6405=m
-CONFIG_DVB_ISL6421=m
-CONFIG_DVB_ISL6422=m
-CONFIG_DVB_ISL6423=m
-CONFIG_DVB_A8293=m
-# CONFIG_DVB_LGS8GL5 is not set
-CONFIG_DVB_LGS8GXX=m
-CONFIG_DVB_ATBM8830=m
-CONFIG_DVB_TDA665x=m
-CONFIG_DVB_IX2505V=m
-CONFIG_DVB_M88RS2000=m
-CONFIG_DVB_AF9033=m
-CONFIG_DVB_TAS2101=m
-CONFIG_DVB_HORUS3A=m
-CONFIG_DVB_ASCOT2E=m
-CONFIG_DVB_HELENE=m
-
-#
-# Common Interface (EN50221) controller drivers
-#
-CONFIG_DVB_CXD2099=m
-CONFIG_DVB_SP2=m
-# end of Customise DVB Frontends
-# end of Media ancillary drivers
-
-#
-# Graphics support
-#
-CONFIG_AGP=m
-CONFIG_AGP_AMD64=m
-CONFIG_AGP_INTEL=m
-CONFIG_AGP_SIS=m
-CONFIG_AGP_VIA=m
-CONFIG_INTEL_GTT=m
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-CONFIG_VGA_SWITCHEROO=y
-CONFIG_DRM=m
-CONFIG_DRM_MIPI_DBI=m
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_DP_AUX_CHARDEV=y
-# CONFIG_DRM_DEBUG_SELFTEST is not set
-CONFIG_DRM_KMS_HELPER=m
-# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
-# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
-# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
-# CONFIG_DRM_DP_CEC is not set
-CONFIG_DRM_TTM=m
-CONFIG_DRM_VRAM_HELPER=m
-CONFIG_DRM_TTM_HELPER=m
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-CONFIG_DRM_SCHED=m
-
-#
-# I2C encoder or helper chips
-#
-CONFIG_DRM_I2C_CH7006=m
-CONFIG_DRM_I2C_SIL164=m
-CONFIG_DRM_I2C_NXP_TDA998X=m
-CONFIG_DRM_I2C_NXP_TDA9950=m
-# end of I2C encoder or helper chips
-
-#
-# ARM devices
-#
-# end of ARM devices
-
-CONFIG_DRM_RADEON=m
-# CONFIG_DRM_RADEON_USERPTR is not set
-CONFIG_DRM_AMDGPU=m
-CONFIG_DRM_AMDGPU_SI=y
-CONFIG_DRM_AMDGPU_CIK=y
-CONFIG_DRM_AMDGPU_USERPTR=y
-
-#
-# ACP (Audio CoProcessor) Configuration
-#
-CONFIG_DRM_AMD_ACP=y
-# end of ACP (Audio CoProcessor) Configuration
-
-#
-# Display Engine Configuration
-#
-CONFIG_DRM_AMD_DC=y
-CONFIG_DRM_AMD_DC_DCN=y
-CONFIG_DRM_AMD_DC_HDCP=y
-CONFIG_DRM_AMD_DC_SI=y
-CONFIG_DRM_AMD_SECURE_DISPLAY=y
-# end of Display Engine Configuration
-
-CONFIG_HSA_AMD=y
-CONFIG_DRM_NOUVEAU=m
-CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT=y
-CONFIG_NOUVEAU_DEBUG=5
-CONFIG_NOUVEAU_DEBUG_DEFAULT=3
-# CONFIG_NOUVEAU_DEBUG_MMU is not set
-# CONFIG_NOUVEAU_DEBUG_PUSH is not set
-CONFIG_DRM_NOUVEAU_BACKLIGHT=y
-CONFIG_DRM_I915=m
-CONFIG_DRM_I915_FORCE_PROBE=""
-CONFIG_DRM_I915_CAPTURE_ERROR=y
-CONFIG_DRM_I915_COMPRESS_ERROR=y
-CONFIG_DRM_I915_USERPTR=y
-CONFIG_DRM_I915_GVT=y
-CONFIG_DRM_I915_GVT_KVMGT=m
-CONFIG_DRM_I915_PXP=y
-
-#
-# drm/i915 Debugging
-#
-# CONFIG_DRM_I915_WERROR is not set
-# CONFIG_DRM_I915_DEBUG is not set
-# CONFIG_DRM_I915_DEBUG_MMIO is not set
-# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
-# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
-# CONFIG_DRM_I915_DEBUG_GUC is not set
-# CONFIG_DRM_I915_SELFTEST is not set
-# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
-# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
-# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set
-# end of drm/i915 Debugging
-
-#
-# drm/i915 Profile Guided Optimisation
-#
-CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
-CONFIG_DRM_I915_FENCE_TIMEOUT=10000
-CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
-CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
-CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
-CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
-CONFIG_DRM_I915_STOP_TIMEOUT=100
-CONFIG_DRM_I915_TIMESLICE_DURATION=1
-# end of drm/i915 Profile Guided Optimisation
-
-CONFIG_DRM_VGEM=m
-CONFIG_DRM_VKMS=m
-CONFIG_DRM_VMWGFX=m
-CONFIG_DRM_VMWGFX_FBCON=y
-CONFIG_DRM_VMWGFX_MKSSTATS=y
-CONFIG_DRM_GMA500=m
-CONFIG_DRM_PANEL_MIPI_DBI=m
-CONFIG_DRM_UDL=m
-CONFIG_DRM_AST=m
-CONFIG_DRM_MGAG200=m
-CONFIG_DRM_QXL=m
-CONFIG_DRM_VIRTIO_GPU=m
-CONFIG_DRM_PANEL=y
-
-#
-# Display Panels
-#
-CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
-CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
-# end of Display Panels
-
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_PANEL_BRIDGE=y
-
-#
-# Display Interface Bridges
-#
-CONFIG_DRM_ANALOGIX_ANX78XX=m
-CONFIG_DRM_ANALOGIX_DP=m
-# end of Display Interface Bridges
-
-CONFIG_DRM_ETNAVIV=m
-CONFIG_DRM_ETNAVIV_THERMAL=y
-CONFIG_DRM_BOCHS=m
-CONFIG_DRM_CIRRUS_QEMU=m
-CONFIG_DRM_GM12U320=m
-CONFIG_DRM_SIMPLEDRM=y
-CONFIG_TINYDRM_HX8357D=m
-CONFIG_TINYDRM_ILI9225=m
-CONFIG_TINYDRM_ILI9341=m
-CONFIG_TINYDRM_ILI9486=m
-CONFIG_TINYDRM_MI0283QT=m
-CONFIG_TINYDRM_REPAPER=m
-CONFIG_TINYDRM_ST7586=m
-CONFIG_TINYDRM_ST7735R=m
-CONFIG_DRM_VBOXVIDEO=m
-CONFIG_DRM_GUD=m
-CONFIG_DRM_SSD130X=m
-CONFIG_DRM_SSD130X_I2C=m
-CONFIG_DRM_SPRD=m
-CONFIG_DRM_HYPERV=m
-CONFIG_DRM_LEGACY=y
-CONFIG_DRM_TDFX=m
-CONFIG_DRM_R128=m
-CONFIG_DRM_MGA=m
-CONFIG_DRM_SIS=m
-CONFIG_DRM_VIA=m
-CONFIG_DRM_SAVAGE=m
-CONFIG_DRM_EXPORT_FOR_TESTS=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m
-CONFIG_DRM_LIB_RANDOM=y
-
-#
-# Frame buffer Devices
-#
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_NOTIFY=y
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-CONFIG_FB_BOOT_VESA_SUPPORT=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SYS_FILLRECT=m
-CONFIG_FB_SYS_COPYAREA=m
-CONFIG_FB_SYS_IMAGEBLIT=m
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-CONFIG_FB_SYS_FOPS=m
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_BACKLIGHT=m
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_CIRRUS is not set
-# CONFIG_FB_PM2 is not set
-# CONFIG_FB_CYBER2000 is not set
-# CONFIG_FB_ARC is not set
-# CONFIG_FB_ASILIANT is not set
-# CONFIG_FB_IMSTT is not set
-# CONFIG_FB_VGA16 is not set
-# CONFIG_FB_UVESA is not set
-CONFIG_FB_VESA=y
-# CONFIG_FB_EFI is not set
-# CONFIG_FB_N411 is not set
-# CONFIG_FB_HGA is not set
-# CONFIG_FB_OPENCORES is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-# CONFIG_FB_I740 is not set
-# CONFIG_FB_LE80578 is not set
-# CONFIG_FB_INTEL is not set
-# CONFIG_FB_MATROX is not set
-# CONFIG_FB_RADEON is not set
-# CONFIG_FB_ATY128 is not set
-# CONFIG_FB_ATY is not set
-# CONFIG_FB_S3 is not set
-# CONFIG_FB_SAVAGE is not set
-# CONFIG_FB_SIS is not set
-# CONFIG_FB_VIA is not set
-# CONFIG_FB_NEOMAGIC is not set
-# CONFIG_FB_KYRO is not set
-# CONFIG_FB_3DFX is not set
-# CONFIG_FB_VOODOO1 is not set
-# CONFIG_FB_VT8623 is not set
-# CONFIG_FB_TRIDENT is not set
-# CONFIG_FB_ARK is not set
-# CONFIG_FB_PM3 is not set
-# CONFIG_FB_CARMINE is not set
-# CONFIG_FB_SM501 is not set
-# CONFIG_FB_SMSCUFX is not set
-# CONFIG_FB_UDL is not set
-# CONFIG_FB_IBM_GXT4500 is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-# CONFIG_FB_HYPERV is not set
-# CONFIG_FB_SIMPLE is not set
-# CONFIG_FB_SSD1307 is not set
-# CONFIG_FB_SM712 is not set
-# end of Frame buffer Devices
-
-#
-# Backlight & LCD device support
-#
-CONFIG_LCD_CLASS_DEVICE=m
-CONFIG_LCD_L4F00242T03=m
-CONFIG_LCD_LMS283GF05=m
-CONFIG_LCD_LTV350QV=m
-CONFIG_LCD_ILI922X=m
-CONFIG_LCD_ILI9320=m
-CONFIG_LCD_TDO24M=m
-CONFIG_LCD_VGG2432A4=m
-CONFIG_LCD_PLATFORM=m
-CONFIG_LCD_AMS369FG06=m
-CONFIG_LCD_LMS501KF03=m
-CONFIG_LCD_HX8357=m
-CONFIG_LCD_OTM3225A=m
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_KTD253=m
-CONFIG_BACKLIGHT_LM3533=m
-CONFIG_BACKLIGHT_PWM=m
-CONFIG_BACKLIGHT_MT6370=m
-CONFIG_BACKLIGHT_DA9052=m
-CONFIG_BACKLIGHT_MT6370=m
-CONFIG_BACKLIGHT_APPLE=m
-CONFIG_BACKLIGHT_QCOM_WLED=m
-CONFIG_BACKLIGHT_RT4831=m
-CONFIG_BACKLIGHT_SAHARA=m
-CONFIG_BACKLIGHT_WM831X=m
-CONFIG_BACKLIGHT_ADP8860=m
-CONFIG_BACKLIGHT_ADP8870=m
-CONFIG_BACKLIGHT_PCF50633=m
-CONFIG_BACKLIGHT_LM3630A=m
-CONFIG_BACKLIGHT_LM3639=m
-CONFIG_BACKLIGHT_LP855X=m
-CONFIG_BACKLIGHT_SKY81452=m
-CONFIG_BACKLIGHT_GPIO=m
-CONFIG_BACKLIGHT_LV5207LP=m
-CONFIG_BACKLIGHT_BD6107=m
-CONFIG_BACKLIGHT_ARCXCNN=m
-CONFIG_BACKLIGHT_RAVE_SP=m
-# end of Backlight & LCD device support
-
-CONFIG_HDMI=y
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DUMMY_CONSOLE_COLUMNS=80
-CONFIG_DUMMY_CONSOLE_ROWS=25
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
-# end of Console display driver support
-
-# CONFIG_LOGO is not set
-# end of Graphics support
-
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_PCM_ELD=y
-CONFIG_SND_PCM_IEC958=y
-CONFIG_SND_DMAENGINE_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_SEQ_DEVICE=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_COMPRESS_OFFLOAD=m
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_PCM_TIMER=y
-CONFIG_SND_HRTIMER=m
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_MAX_CARDS=32
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_PROC_FS=y
-CONFIG_SND_VERBOSE_PROCFS=y
-CONFIG_SND_CTL_FAST_LOOKUP=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_CTL_INPUT_VALIDATION=y
-CONFIG_SND_VMASTER=y
-CONFIG_SND_DMA_SGBUF=y
-CONFIG_SND_CTL_LED=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_SEQUENCER_OSS=m
-CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
-CONFIG_SND_SEQ_MIDI_EVENT=m
-CONFIG_SND_SEQ_MIDI=m
-CONFIG_SND_SEQ_MIDI_EMUL=m
-CONFIG_SND_SEQ_VIRMIDI=m
-CONFIG_SND_MPU401_UART=m
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_OPL3_LIB_SEQ=m
-CONFIG_SND_VX_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_PCSP is not set
-CONFIG_SND_DUMMY=m
-CONFIG_SND_ALOOP=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_MTS64=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_PORTMAN2X4=m
-CONFIG_SND_AC97_POWER_SAVE=y
-CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
-CONFIG_SND_SB_COMMON=m
-CONFIG_SND_PCI=y
-CONFIG_SND_AD1889=m
-CONFIG_SND_ALS300=m
-CONFIG_SND_ALS4000=m
-CONFIG_SND_ALI5451=m
-CONFIG_SND_ASIHPI=m
-CONFIG_SND_ATIIXP=m
-CONFIG_SND_ATIIXP_MODEM=m
-CONFIG_SND_AU8810=m
-CONFIG_SND_AU8820=m
-CONFIG_SND_AU8830=m
-CONFIG_SND_AW2=m
-CONFIG_SND_AZT3328=m
-CONFIG_SND_BT87X=m
-CONFIG_SND_BT87X_OVERCLOCK=y
-CONFIG_SND_CA0106=m
-CONFIG_SND_CMIPCI=m
-CONFIG_SND_OXYGEN_LIB=m
-CONFIG_SND_OXYGEN=m
-CONFIG_SND_CS4281=m
-CONFIG_SND_CS46XX=m
-CONFIG_SND_CS46XX_NEW_DSP=y
-CONFIG_SND_CTXFI=m
-CONFIG_SND_DARLA20=m
-CONFIG_SND_GINA20=m
-CONFIG_SND_LAYLA20=m
-CONFIG_SND_DARLA24=m
-CONFIG_SND_GINA24=m
-CONFIG_SND_LAYLA24=m
-CONFIG_SND_MONA=m
-CONFIG_SND_MIA=m
-CONFIG_SND_ECHO3G=m
-CONFIG_SND_INDIGO=m
-CONFIG_SND_INDIGOIO=m
-CONFIG_SND_INDIGODJ=m
-CONFIG_SND_INDIGOIOX=m
-CONFIG_SND_INDIGODJX=m
-CONFIG_SND_EMU10K1=m
-CONFIG_SND_EMU10K1_SEQ=m
-CONFIG_SND_EMU10K1X=m
-CONFIG_SND_ENS1370=m
-CONFIG_SND_ENS1371=m
-CONFIG_SND_ES1938=m
-CONFIG_SND_ES1968=m
-CONFIG_SND_ES1968_INPUT=y
-CONFIG_SND_ES1968_RADIO=y
-CONFIG_SND_FM801=m
-CONFIG_SND_FM801_TEA575X_BOOL=y
-CONFIG_SND_HDSP=m
-CONFIG_SND_HDSPM=m
-CONFIG_SND_ICE1712=m
-CONFIG_SND_ICE1724=m
-CONFIG_SND_INTEL8X0=m
-CONFIG_SND_INTEL8X0M=m
-CONFIG_SND_KORG1212=m
-CONFIG_SND_LOLA=m
-CONFIG_SND_LX6464ES=m
-CONFIG_SND_MAESTRO3=m
-CONFIG_SND_MAESTRO3_INPUT=y
-CONFIG_SND_MIXART=m
-CONFIG_SND_NM256=m
-CONFIG_SND_PCXHR=m
-CONFIG_SND_RIPTIDE=m
-CONFIG_SND_RME32=m
-CONFIG_SND_RME96=m
-CONFIG_SND_RME9652=m
-CONFIG_SND_SONICVIBES=m
-CONFIG_SND_TRIDENT=m
-CONFIG_SND_VIA82XX=m
-CONFIG_SND_VIA82XX_MODEM=m
-CONFIG_SND_VIRTUOSO=m
-CONFIG_SND_VX222=m
-CONFIG_SND_YMFPCI=m
-
-#
-# HD-Audio
-#
-CONFIG_SND_HDA=m
-CONFIG_SND_HDA_GENERIC_LEDS=y
-CONFIG_SND_HDA_INTEL=m
-CONFIG_SND_HDA_HWDEP=y
-CONFIG_SND_HDA_RECONFIG=y
-CONFIG_SND_HDA_INPUT_BEEP=y
-CONFIG_SND_HDA_INPUT_BEEP_MODE=1
-CONFIG_SND_HDA_PATCH_LOADER=y
-CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m
-CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m
-CONFIG_SND_HDA_CODEC_REALTEK=m
-CONFIG_SND_HDA_CODEC_ANALOG=m
-CONFIG_SND_HDA_CODEC_SIGMATEL=m
-CONFIG_SND_HDA_CODEC_VIA=m
-CONFIG_SND_HDA_CODEC_HDMI=m
-CONFIG_SND_HDA_CODEC_CIRRUS=m
-CONFIG_SND_HDA_CODEC_CS8409=m
-CONFIG_SND_HDA_CODEC_CONEXANT=m
-CONFIG_SND_HDA_CODEC_CA0110=m
-CONFIG_SND_HDA_CODEC_CA0132=m
-CONFIG_SND_HDA_CODEC_CA0132_DSP=y
-CONFIG_SND_HDA_CODEC_CMEDIA=m
-CONFIG_SND_HDA_CODEC_SI3054=m
-CONFIG_SND_HDA_GENERIC=m
-CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
-# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
-# end of HD-Audio
-
-CONFIG_SND_HDA_CORE=m
-CONFIG_SND_HDA_DSP_LOADER=y
-CONFIG_SND_HDA_COMPONENT=y
-CONFIG_SND_HDA_I915=y
-CONFIG_SND_HDA_EXT_CORE=m
-CONFIG_SND_HDA_PREALLOC_SIZE=0
-CONFIG_SND_INTEL_NHLT=y
-CONFIG_SND_INTEL_DSP_CONFIG=m
-CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m
-CONFIG_SND_INTEL_BYT_PREFER_SOF=y
-CONFIG_SND_SPI=y
-CONFIG_SND_USB=y
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
-CONFIG_SND_USB_UA101=m
-CONFIG_SND_USB_USX2Y=m
-CONFIG_SND_USB_CAIAQ=m
-CONFIG_SND_USB_CAIAQ_INPUT=y
-CONFIG_SND_USB_US122L=m
-CONFIG_SND_USB_6FIRE=m
-CONFIG_SND_USB_HIFACE=m
-CONFIG_SND_BCD2000=m
-CONFIG_SND_USB_LINE6=m
-CONFIG_SND_USB_POD=m
-CONFIG_SND_USB_PODHD=m
-CONFIG_SND_USB_TONEPORT=m
-CONFIG_SND_USB_VARIAX=m
-CONFIG_SND_FIREWIRE=y
-CONFIG_SND_FIREWIRE_LIB=m
-CONFIG_SND_DICE=m
-CONFIG_SND_OXFW=m
-CONFIG_SND_ISIGHT=m
-CONFIG_SND_FIREWORKS=m
-CONFIG_SND_BEBOB=m
-CONFIG_SND_FIREWIRE_DIGI00X=m
-CONFIG_SND_FIREWIRE_TASCAM=m
-CONFIG_SND_FIREWIRE_MOTU=m
-CONFIG_SND_FIREFACE=m
-CONFIG_SND_PCMCIA=y
-CONFIG_SND_VXPOCKET=m
-CONFIG_SND_PDAUDIOCF=m
-CONFIG_SND_SOC=m
-CONFIG_SND_SOC_AC97_BUS=y
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_COMPRESS=y
-CONFIG_SND_SOC_TOPOLOGY=y
-CONFIG_SND_SOC_ACPI=m
-CONFIG_SND_SOC_ADI=m
-CONFIG_SND_SOC_ADI_AXI_I2S=m
-CONFIG_SND_SOC_ADI_AXI_SPDIF=m
-CONFIG_SND_SOC_AMD_ACP=m
-CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m
-CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m
-CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
-CONFIG_SND_SOC_AMD_ACP3x=m
-CONFIG_SND_SOC_AMD_RV_RT5682_MACH=m
-CONFIG_SND_SOC_AMD_RENOIR=m
-CONFIG_SND_SOC_AMD_RENOIR_MACH=m
-CONFIG_SND_SOC_AMD_ACP5x=m
-CONFIG_SND_SOC_AMD_VANGOGH_MACH=m
-CONFIG_SND_SOC_AMD_ACP6x=m
-CONFIG_SND_SOC_AMD_YC_MACH=m
-CONFIG_SND_SOC_AMD_ACP_COMMON=m
-CONFIG_SND_SOC_AMD_ACP_PCI=m
-CONFIG_SND_SOC_AMD_ACP_I2S=m
-CONFIG_SND_SOC_AMD_ACP_PCM=m
-CONFIG_SND_AMD_ASOC_RENOIR=m
-CONFIG_SND_AMD_ASOC_REMBRANDT=m
-CONFIG_SND_SOC_AMD_MACH_COMMON=m
-CONFIG_SND_SOC_AMD_LEGACY_MACH=m
-CONFIG_SND_SOC_AMD_SOF_MACH=m
-CONFIG_SND_SOC_AMD_RPL_ACP6x=m
-CONFIG_SND_SOC_AMD_PS=m
-CONFIG_SND_SOC_AMD_PS_MACH=m
-CONFIG_SND_ATMEL_SOC=m
-CONFIG_SND_BCM63XX_I2S_WHISTLER=m
-CONFIG_SND_DESIGNWARE_I2S=m
-CONFIG_SND_DESIGNWARE_PCM=y
-
-#
-# SoC Audio for Freescale CPUs
-#
-
-#
-# Common SoC Audio options for Freescale CPUs:
-#
-CONFIG_SND_SOC_FSL_ASRC=m
-CONFIG_SND_SOC_FSL_SAI=m
-CONFIG_SND_SOC_FSL_MQS=m
-CONFIG_SND_SOC_FSL_AUDMIX=m
-CONFIG_SND_SOC_FSL_SSI=m
-CONFIG_SND_SOC_FSL_SPDIF=m
-CONFIG_SND_SOC_FSL_ESAI=m
-CONFIG_SND_SOC_FSL_MICFIL=m
-CONFIG_SND_SOC_FSL_EASRC=m
-CONFIG_SND_SOC_FSL_XCVR=m
-CONFIG_SND_SOC_FSL_RPMSG=m
-CONFIG_SND_SOC_IMX_AUDMUX=m
-# end of SoC Audio for Freescale CPUs
-
-CONFIG_SND_I2S_HI6210_I2S=m
-CONFIG_SND_SOC_IMG=y
-CONFIG_SND_SOC_IMG_I2S_IN=m
-CONFIG_SND_SOC_IMG_I2S_OUT=m
-CONFIG_SND_SOC_IMG_PARALLEL_OUT=m
-CONFIG_SND_SOC_IMG_SPDIF_IN=m
-CONFIG_SND_SOC_IMG_SPDIF_OUT=m
-CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m
-CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y
-CONFIG_SND_SOC_INTEL_AVS=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=m
-CONFIG_SND_SOC_INTEL_SST=m
-CONFIG_SND_SOC_INTEL_CATPT=m
-CONFIG_SND_SST_ATOM_HIFI2_PLATFORM=m
-CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI=m
-CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI=m
-CONFIG_SND_SOC_INTEL_SKYLAKE=m
-CONFIG_SND_SOC_INTEL_SKL=m
-CONFIG_SND_SOC_INTEL_APL=m
-CONFIG_SND_SOC_INTEL_KBL=m
-CONFIG_SND_SOC_INTEL_GLK=m
-CONFIG_SND_SOC_INTEL_CNL=m
-CONFIG_SND_SOC_INTEL_CFL=m
-CONFIG_SND_SOC_INTEL_CML_H=m
-CONFIG_SND_SOC_INTEL_CML_LP=m
-CONFIG_SND_SOC_INTEL_SKYLAKE_FAMILY=m
-CONFIG_SND_SOC_INTEL_SKYLAKE_SSP_CLK=m
-CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC=y
-CONFIG_SND_SOC_INTEL_AVS=m
-CONFIG_SND_SOC_INTEL_SKYLAKE_COMMON=m
-CONFIG_SND_SOC_ACPI_INTEL_MATCH=m
-CONFIG_SND_SOC_INTEL_MACH=y
-# CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES is not set
-CONFIG_SND_SOC_INTEL_HDA_DSP_COMMON=m
-CONFIG_SND_SOC_INTEL_SOF_MAXIM_COMMON=m
-CONFIG_SND_SOC_INTEL_HASWELL_MACH=m
-CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH=m
-CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=m
-CONFIG_SND_SOC_INTEL_BROADWELL_MACH=m
-CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=m
-CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH=m
-CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH=m
-CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=m
-CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH=m
-CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH=m
-CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH=m
-CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH=m
-CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH=m
-CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH=m
-CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH=m
-CONFIG_SND_SOC_INTEL_SKL_RT286_MACH=m
-CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH=m
-CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_DA7219_MAX98357A_GENERIC=m
-CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_COMMON=m
-CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_BXT_RT298_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98927_MACH=m
-CONFIG_SND_SOC_INTEL_KBL_RT5660_MACH=m
-CONFIG_SND_SOC_INTEL_GLK_DA7219_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_GLK_RT5682_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_CS42L42_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_ES8336_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_NAU8825_MACH=m
-CONFIG_SND_SOC_INTEL_CML_LP_DA7219_MAX98357A_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_CML_RT1011_RT5682_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_DA7219_MAX98373_MACH=m
-CONFIG_SND_SOC_INTEL_SOF_SSP_AMP_MACH=m
-CONFIG_SND_SOC_INTEL_EHL_RT5660_MACH=m
-CONFIG_SND_SOC_MTK_BTCVSD=m
-CONFIG_SND_SOC_SOF_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_PCI_DEV=m
-CONFIG_SND_SOC_SOF_PCI=m
-CONFIG_SND_SOC_SOF_ACPI=m
-CONFIG_SND_SOC_SOF_ACPI_DEV=m
-# CONFIG_SND_SOC_SOF_DEBUG_PROBES is not set
-# CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT is not set
-CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m
-CONFIG_SND_SOC_SOF_AMD_RENOIR=m
-CONFIG_SND_SOC_SOF_AMD_REMBRANDT=m
-CONFIG_SND_SOC_SOF=m
-CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE=y
-CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC=m
-CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP=m
-CONFIG_SND_SOC_SOF_INTEL_COMMON=m
-CONFIG_SND_SOC_SOF_BAYTRAIL=m
-CONFIG_SND_SOC_SOF_BROADWELL=m
-CONFIG_SND_SOC_SOF_MERRIFIELD=m
-CONFIG_SND_SOC_SOF_SKYLAKE=m
-CONFIG_SND_SOC_SOF_KABYLAKE=m
-CONFIG_SND_SOC_SOF_INTEL_APL=m
-CONFIG_SND_SOC_SOF_APOLLOLAKE=m
-CONFIG_SND_SOC_SOF_GEMINILAKE=m
-CONFIG_SND_SOC_SOF_INTEL_CNL=m
-CONFIG_SND_SOC_SOF_CANNONLAKE=m
-CONFIG_SND_SOC_SOF_COFFEELAKE=m
-CONFIG_SND_SOC_SOF_COMETLAKE=m
-CONFIG_SND_SOC_SOF_INTEL_ICL=m
-CONFIG_SND_SOC_SOF_ICELAKE=m
-CONFIG_SND_SOC_SOF_JASPERLAKE=m
-CONFIG_SND_SOC_SOF_INTEL_TGL=m
-CONFIG_SND_SOC_SOF_TIGERLAKE=m
-CONFIG_SND_SOC_SOF_ELKHARTLAKE=m
-CONFIG_SND_SOC_SOF_ALDERLAKE=m
-CONFIG_SND_SOC_SOF_METEORLAKE=m
-CONFIG_SND_SOC_SOF_HDA_COMMON=m
-CONFIG_SND_SOC_SOF_HDA_LINK=y
-CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC=y
-CONFIG_SND_SOC_SOF_HDA_LINK_BASELINE=m
-CONFIG_SND_SOC_SOF_HDA=m
-CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE=m
-CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE=m
-CONFIG_SND_SOC_SOF_XTENSA=m
-
-#
-# STMicroelectronics STM32 SOC audio support
-#
-# end of STMicroelectronics STM32 SOC audio support
-
-CONFIG_SND_SOC_XILINX_I2S=m
-CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
-CONFIG_SND_SOC_XILINX_SPDIF=m
-CONFIG_SND_SOC_XTFPGA_I2S=m
-CONFIG_SND_SOC_I2C_AND_SPI=m
-
-#
-# CODEC drivers
-#
-CONFIG_SND_SOC_ARIZONA=m
-CONFIG_SND_SOC_WM_ADSP=m
-CONFIG_SND_SOC_AC97_CODEC=m
-CONFIG_SND_SOC_ADAU_UTILS=m
-CONFIG_SND_SOC_ADAU1372=m
-CONFIG_SND_SOC_ADAU1372_I2C=m
-CONFIG_SND_SOC_ADAU1372_SPI=m
-CONFIG_SND_SOC_ADAU1701=m
-CONFIG_SND_SOC_ADAU17X1=m
-CONFIG_SND_SOC_ADAU1761=m
-CONFIG_SND_SOC_ADAU1761_I2C=m
-CONFIG_SND_SOC_ADAU1761_SPI=m
-CONFIG_SND_SOC_ADAU7002=m
-CONFIG_SND_SOC_ADAU7118=m
-CONFIG_SND_SOC_ADAU7118_HW=m
-CONFIG_SND_SOC_ADAU7118_I2C=m
-CONFIG_SND_SOC_AK4104=m
-CONFIG_SND_SOC_AK4118=m
-CONFIG_SND_SOC_AK4458=m
-CONFIG_SND_SOC_AK4554=m
-CONFIG_SND_SOC_AK4613=m
-CONFIG_SND_SOC_AK4642=m
-CONFIG_SND_SOC_AK5386=m
-CONFIG_SND_SOC_AK5558=m
-CONFIG_SND_SOC_ALC5623=m
-CONFIG_SND_SOC_AW8738=m
-CONFIG_SND_SOC_BD28623=m
-# CONFIG_SND_SOC_BT_SCO is not set
-CONFIG_SND_SOC_CROS_EC_CODEC=m
-CONFIG_SND_SOC_CS35L32=m
-CONFIG_SND_SOC_CS35L33=m
-CONFIG_SND_SOC_CS35L34=m
-CONFIG_SND_SOC_CS35L35=m
-CONFIG_SND_SOC_CS35L36=m
-CONFIG_SND_SOC_CS35L41_SPI=m
-CONFIG_SND_SOC_CS35L41_I2C=m
-CONFIG_SND_SOC_CS42L42=m
-CONFIG_SND_SOC_CS42L51=m
-CONFIG_SND_SOC_CS42L51_I2C=m
-CONFIG_SND_SOC_CS42L52=m
-CONFIG_SND_SOC_CS42L56=m
-CONFIG_SND_SOC_CS42L73=m
-CONFIG_SND_SOC_CS42L83=m
-CONFIG_SND_SOC_CS4234=m
-CONFIG_SND_SOC_CS4265=m
-CONFIG_SND_SOC_CS4270=m
-CONFIG_SND_SOC_CS4271=m
-CONFIG_SND_SOC_CS4271_I2C=m
-CONFIG_SND_SOC_CS4271_SPI=m
-CONFIG_SND_SOC_CS42XX8=m
-CONFIG_SND_SOC_CS42XX8_I2C=m
-CONFIG_SND_SOC_CS43130=m
-CONFIG_SND_SOC_CS4341=m
-CONFIG_SND_SOC_CS4349=m
-CONFIG_SND_SOC_CS53L30=m
-CONFIG_SND_SOC_CX2072X=m
-CONFIG_SND_SOC_DA7213=m
-CONFIG_SND_SOC_DA7219=m
-CONFIG_SND_SOC_DMIC=m
-CONFIG_SND_SOC_HDMI_CODEC=m
-CONFIG_SND_SOC_ES7134=m
-CONFIG_SND_SOC_ES7241=m
-CONFIG_SND_SOC_ES8316=m
-CONFIG_SND_SOC_ES8326=m
-CONFIG_SND_SOC_ES8328=m
-CONFIG_SND_SOC_ES8328_I2C=m
-CONFIG_SND_SOC_ES8328_SPI=m
-CONFIG_SND_SOC_GTM601=m
-CONFIG_SND_SOC_HDA=m
-CONFIG_SND_SOC_HDAC_HDMI=m
-CONFIG_SND_SOC_HDAC_HDA=m
-CONFIG_SND_SOC_ICS43432=m
-CONFIG_SND_SOC_INNO_RK3036=m
-CONFIG_SND_SOC_MAX98088=m
-CONFIG_SND_SOC_MAX98090=m
-CONFIG_SND_SOC_MAX98357A=m
-CONFIG_SND_SOC_MAX98504=m
-CONFIG_SND_SOC_MAX9867=m
-CONFIG_SND_SOC_MAX98927=m
-CONFIG_SND_SOC_MAX98520=m
-CONFIG_SND_SOC_MAX98373=m
-CONFIG_SND_SOC_MAX98373_I2C=m
-CONFIG_SND_SOC_MAX98373_SDW=m
-CONFIG_SND_SOC_MAX98390=m
-CONFIG_SND_SOC_MAX9860=m
-CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
-CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
-CONFIG_SND_SOC_PCM1681=m
-CONFIG_SND_SOC_PCM1789=m
-CONFIG_SND_SOC_PCM1789_I2C=m
-CONFIG_SND_SOC_PCM179X=m
-CONFIG_SND_SOC_PCM179X_I2C=m
-CONFIG_SND_SOC_PCM179X_SPI=m
-CONFIG_SND_SOC_PCM186X=m
-CONFIG_SND_SOC_PCM186X_I2C=m
-CONFIG_SND_SOC_PCM186X_SPI=m
-CONFIG_SND_SOC_PCM3060=m
-CONFIG_SND_SOC_PCM3060_I2C=m
-CONFIG_SND_SOC_PCM3060_SPI=m
-CONFIG_SND_SOC_PCM3168A=m
-CONFIG_SND_SOC_PCM3168A_I2C=m
-CONFIG_SND_SOC_PCM3168A_SPI=m
-CONFIG_SND_SOC_PCM5102A=m
-CONFIG_SND_SOC_PCM512x=m
-CONFIG_SND_SOC_PCM512x_I2C=m
-CONFIG_SND_SOC_PCM512x_SPI=m
-CONFIG_SND_SOC_RK3328=m
-CONFIG_SND_SOC_RL6231=m
-CONFIG_SND_SOC_RL6347A=m
-CONFIG_SND_SOC_RT286=m
-CONFIG_SND_SOC_RT298=m
-CONFIG_SND_SOC_RT1011=m
-CONFIG_SND_SOC_RT1015=m
-CONFIG_SND_SOC_RT1015P=m
-CONFIG_SND_SOC_RT1019=m
-CONFIG_SND_SOC_RT1308_SDW=m
-CONFIG_SND_SOC_RT1316_SDW=m
-CONFIG_SND_SOC_RT5514=m
-CONFIG_SND_SOC_RT5514_SPI=m
-CONFIG_SND_SOC_RT5616=m
-CONFIG_SND_SOC_RT5631=m
-CONFIG_SND_SOC_RT5640=m
-CONFIG_SND_SOC_RT5645=m
-CONFIG_SND_SOC_RT5651=m
-CONFIG_SND_SOC_RT5659=m
-CONFIG_SND_SOC_RT5660=m
-CONFIG_SND_SOC_RT5663=m
-CONFIG_SND_SOC_RT5670=m
-CONFIG_SND_SOC_RT5677=m
-CONFIG_SND_SOC_RT5677_SPI=m
-CONFIG_SND_SOC_RT5682=m
-CONFIG_SND_SOC_RT5682_I2C=m
-CONFIG_SND_SOC_RT5682_SDW=m
-CONFIG_SND_SOC_RT5682S=m
-CONFIG_SND_SOC_RT700=m
-CONFIG_SND_SOC_RT700_SDW=m
-CONFIG_SND_SOC_RT711=m
-CONFIG_SND_SOC_RT711_SDW=m
-CONFIG_SND_SOC_RT711_SDCA_SDW=m
-CONFIG_SND_SOC_RT715=m
-CONFIG_SND_SOC_RT715_SDW=m
-CONFIG_SND_SOC_RT715_SDCA_SDW=m
-CONFIG_SND_SOC_RT9120=m
-CONFIG_SND_SOC_SDW_MOCKUP=m
-CONFIG_SND_SOC_SGTL5000=m
-CONFIG_SND_SOC_SI476X=m
-CONFIG_SND_SOC_SIGMADSP=m
-CONFIG_SND_SOC_SIGMADSP_I2C=m
-CONFIG_SND_SOC_SIGMADSP_REGMAP=m
-CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
-CONFIG_SND_SOC_SIMPLE_MUX=m
-CONFIG_SND_SOC_SPDIF=m
-CONFIG_SND_SOC_SRC4XXX_I2C=m
-CONFIG_SND_SOC_SSM2305=m
-CONFIG_SND_SOC_SSM2518=m
-CONFIG_SND_SOC_SSM2602=m
-CONFIG_SND_SOC_SSM2602_SPI=m
-CONFIG_SND_SOC_SSM2602_I2C=m
-CONFIG_SND_SOC_SSM4567=m
-CONFIG_SND_SOC_STA32X=m
-CONFIG_SND_SOC_STA350=m
-CONFIG_SND_SOC_STI_SAS=m
-CONFIG_SND_SOC_TAS2552=m
-CONFIG_SND_SOC_TAS2562=m
-CONFIG_SND_SOC_TAS2764=m
-CONFIG_SND_SOC_TAS2770=m
-CONFIG_SND_SOC_TAS2780=m
-CONFIG_SND_SOC_WSA883X=m
-CONFIG_USB_ONBOARD_HUB=m
-CONFIG_SND_SOC_TAS5086=m
-CONFIG_SND_SOC_TAS571X=m
-CONFIG_SND_SOC_TAS5720=m
-CONFIG_SND_SOC_TAS5805M=m
-CONFIG_SND_SOC_TAS6424=m
-CONFIG_SND_SOC_TDA7419=m
-CONFIG_SND_SOC_TFA9879=m
-CONFIG_SND_SOC_TFA989X=m
-CONFIG_SND_SOC_TLV320AIC23=m
-CONFIG_SND_SOC_TLV320AIC23_I2C=m
-CONFIG_SND_SOC_TLV320AIC23_SPI=m
-CONFIG_SND_SOC_TLV320AIC31XX=m
-CONFIG_SND_SOC_TLV320AIC32X4=m
-CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
-CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
-CONFIG_SND_SOC_TLV320AIC3X=m
-CONFIG_SND_SOC_TLV320AIC3X_I2C=m
-CONFIG_SND_SOC_TLV320AIC3X_SPI=m
-CONFIG_SND_SOC_TLV320ADCX140=m
-CONFIG_SND_SOC_TS3A227E=m
-CONFIG_SND_SOC_TSCS42XX=m
-CONFIG_SND_SOC_TSCS454=m
-CONFIG_SND_SOC_UDA1334=m
-CONFIG_SND_SOC_WCD9335=m
-CONFIG_SND_SOC_WCD_MBHC=m
-CONFIG_SND_SOC_WCD934X=m
-CONFIG_SND_SOC_WCD938X=m
-CONFIG_SND_SOC_WCD938X_SDW=m
-CONFIG_SND_SOC_WM5102=m
-CONFIG_SND_SOC_WM8510=m
-CONFIG_SND_SOC_WM8523=m
-CONFIG_SND_SOC_WM8524=m
-CONFIG_SND_SOC_WM8580=m
-CONFIG_SND_SOC_WM8711=m
-CONFIG_SND_SOC_WM8728=m
-CONFIG_SND_SOC_WM8731=m
-CONFIG_SND_SOC_WM8737=m
-CONFIG_SND_SOC_WM8741=m
-CONFIG_SND_SOC_WM8750=m
-CONFIG_SND_SOC_WM8753=m
-CONFIG_SND_SOC_WM8770=m
-CONFIG_SND_SOC_WM8776=m
-CONFIG_SND_SOC_WM8782=m
-CONFIG_SND_SOC_WM8804=m
-CONFIG_SND_SOC_WM8804_I2C=m
-CONFIG_SND_SOC_WM8804_SPI=m
-CONFIG_SND_SOC_WM8903=m
-CONFIG_SND_SOC_WM8904=m
-CONFIG_SND_SOC_WM8960=m
-CONFIG_SND_SOC_WM8962=m
-CONFIG_SND_SOC_WM8974=m
-CONFIG_SND_SOC_WM8978=m
-CONFIG_SND_SOC_WM8985=m
-CONFIG_SND_SOC_WSA881X=m
-CONFIG_SND_SOC_ZL38060=m
-CONFIG_SND_SOC_MAX9759=m
-CONFIG_SND_SOC_MT6351=m
-CONFIG_SND_SOC_MT6358=m
-CONFIG_SND_SOC_MT6660=m
-CONFIG_SND_SOC_NAU8315=m
-CONFIG_SND_SOC_NAU8540=m
-CONFIG_SND_SOC_NAU8810=m
-CONFIG_SND_SOC_NAU8821=m
-CONFIG_SND_SOC_NAU8822=m
-CONFIG_SND_SOC_NAU8824=m
-CONFIG_SND_SOC_NAU8825=m
-CONFIG_SND_SOC_TPA6130A2=m
-CONFIG_SND_SOC_LPASS_WSA_MACRO=m
-CONFIG_SND_SOC_LPASS_VA_MACRO=m
-CONFIG_SND_SOC_LPASS_RX_MACRO=m
-CONFIG_SND_SOC_LPASS_TX_MACRO=m
-# end of CODEC drivers
-
-CONFIG_SND_SIMPLE_CARD_UTILS=m
-CONFIG_SND_SIMPLE_CARD=m
-CONFIG_SND_X86=y
-CONFIG_HDMI_LPE_AUDIO=m
-CONFIG_SND_SYNTH_EMUX=m
-CONFIG_SND_VIRTIO=m
-CONFIG_AC97_BUS=m
-
-#
-# HID support
-#
-CONFIG_HID=m
-CONFIG_HID_BATTERY_STRENGTH=y
-CONFIG_HIDRAW=y
-CONFIG_UHID=m
-CONFIG_HID_GENERIC=m
-
-#
-# Special HID drivers
-#
-CONFIG_HID_A4TECH=m
-CONFIG_HID_ACCUTOUCH=m
-CONFIG_HID_ACRUX=m
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=m
-CONFIG_HID_APPLEIR=m
-CONFIG_HID_ASUS=m
-CONFIG_HID_AUREAL=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_BETOP_FF=m
-CONFIG_HID_BIGBEN_FF=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CORSAIR=m
-CONFIG_HID_COUGAR=m
-CONFIG_HID_MACALLY=m
-CONFIG_HID_PRODIKEYS=m
-CONFIG_HID_CMEDIA=m
-CONFIG_HID_CP2112=m
-CONFIG_HID_CREATIVE_SB0540=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_DRAGONRISE=m
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=m
-CONFIG_HID_ELAN=m
-CONFIG_HID_ELECOM=m
-CONFIG_HID_ELO=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_FT260=m
-CONFIG_HID_GEMBIRD=m
-CONFIG_HID_GFRM=m
-CONFIG_HID_GLORIOUS=m
-CONFIG_HID_HOLTEK=m
-CONFIG_HOLTEK_FF=y
-CONFIG_HID_GOOGLE_HAMMER=m
-CONFIG_HID_VIVALDI=m
-CONFIG_HID_GT683R=m
-CONFIG_HID_KEYTOUCH=m
-CONFIG_HID_KYE=m
-CONFIG_HID_UCLOGIC=m
-CONFIG_HID_WALTOP=m
-CONFIG_HID_VIEWSONIC=m
-CONFIG_HID_VRC2=m
-CONFIG_HID_XIAOMI=m
-CONFIG_HID_GYRATION=m
-CONFIG_HID_ICADE=m
-CONFIG_HID_ITE=m
-CONFIG_HID_JABRA=m
-CONFIG_HID_TWINHAN=m
-CONFIG_HID_KENSINGTON=m
-CONFIG_HID_LCPOWER=m
-CONFIG_HID_LED=m
-CONFIG_HID_LENOVO=m
-CONFIG_HID_LOGITECH=m
-CONFIG_HID_LOGITECH_DJ=m
-CONFIG_HID_LOGITECH_HIDPP=m
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWHEELS_FF=y
-CONFIG_HID_MAGICMOUSE=m
-CONFIG_HID_MALTRON=m
-CONFIG_HID_MAYFLASH=m
-CONFIG_HID_REDRAGON=m
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_MULTITOUCH=m
-CONFIG_HID_NINTENDO=m
-CONFIG_NINTENDO_FF=y
-CONFIG_HID_NTI=m
-CONFIG_HID_NTRIG=m
-CONFIG_HID_ORTEK=m
-CONFIG_HID_PANTHERLORD=m
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PENMOUNT=m
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_PICOLCD=m
-# CONFIG_HID_PICOLCD_FB is not set
-# CONFIG_HID_PICOLCD_BACKLIGHT is not set
-# CONFIG_HID_PICOLCD_LCD is not set
-# CONFIG_HID_PICOLCD_LEDS is not set
-# CONFIG_HID_PICOLCD_CIR is not set
-CONFIG_HID_PLANTRONICS=m
-CONFIG_HID_PLAYSTATION=m
-CONFIG_HID_PXRC=m
-CONFIG_HID_RAZER=m
-CONFIG_PLAYSTATION_FF=y
-CONFIG_HID_PRIMAX=m
-CONFIG_HID_RETRODE=m
-CONFIG_HID_ROCCAT=m
-CONFIG_HID_SAITEK=m
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SEMITEK=m
-CONFIG_HID_SIGMAMICRO=m
-CONFIG_HID_SONY=m
-CONFIG_SONY_FF=y
-CONFIG_HID_SPEEDLINK=m
-CONFIG_HID_STEAM=m
-CONFIG_HID_STEELSERIES=m
-CONFIG_HID_SUNPLUS=m
-CONFIG_HID_RMI=m
-CONFIG_HID_GREENASIA=m
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_HYPERV_MOUSE=m
-CONFIG_HID_SMARTJOYPLUS=m
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TIVO=m
-CONFIG_HID_TOPSEED=m
-CONFIG_HID_TOPRE=m
-CONFIG_HID_THINGM=m
-CONFIG_HID_THRUSTMASTER=m
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_UDRAW_PS3=m
-CONFIG_HID_U2FZERO=m
-CONFIG_HID_WACOM=m
-CONFIG_HID_WIIMOTE=m
-CONFIG_HID_XINMO=m
-CONFIG_HID_ZEROPLUS=m
-CONFIG_ZEROPLUS_FF=y
-CONFIG_HID_ZYDACRON=m
-CONFIG_HID_SENSOR_HUB=m
-CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
-CONFIG_HID_ALPS=m
-CONFIG_HID_MCP2221=m
-# end of Special HID drivers
-
-#
-# USB HID support
-#
-CONFIG_USB_HID=m
-CONFIG_HID_PID=y
-CONFIG_USB_HIDDEV=y
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# end of USB HID Boot Protocol drivers
-# end of USB HID support
-
-#
-# I2C HID support
-#
-CONFIG_I2C_HID_ACPI=m
-# end of I2C HID support
-
-CONFIG_I2C_HID_CORE=m
-
-#
-# Intel ISH HID support
-#
-CONFIG_INTEL_ISH_HID=m
-CONFIG_INTEL_ISH_FIRMWARE_DOWNLOADER=m
-# end of Intel ISH HID support
-
-#
-# AMD SFH HID Support
-#
-CONFIG_AMD_SFH_HID=m
-# end of AMD SFH HID Support
-
-#
-# Surface System Aggregator Module HID support
-#
-CONFIG_SURFACE_HID=m
-CONFIG_SURFACE_KBD=m
-# end of Surface System Aggregator Module HID support
-
-CONFIG_SURFACE_HID_CORE=m
-# end of HID support
-
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_COMMON=m
-CONFIG_USB_LED_TRIG=y
-CONFIG_USB_ULPI_BUS=m
-CONFIG_USB_CONN_GPIO=m
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB=m
-CONFIG_USB_PCI=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEFAULT_PERSIST=y
-CONFIG_USB_FEW_INIT_RETRIES=y
-CONFIG_USB_DYNAMIC_MINORS=y
-CONFIG_USB_OTG=y
-# CONFIG_USB_OTG_PRODUCTLIST is not set
-# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
-CONFIG_USB_OTG_FSM=m
-CONFIG_USB_LEDS_TRIGGER_USBPORT=m
-CONFIG_USB_AUTOSUSPEND_DELAY=2
-CONFIG_USB_MON=m
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_C67X00_HCD=m
-CONFIG_USB_XHCI_HCD=m
-CONFIG_USB_XHCI_DBGCAP=y
-CONFIG_USB_XHCI_PCI=m
-CONFIG_USB_XHCI_PCI_RENESAS=m
-CONFIG_USB_XHCI_PLATFORM=m
-CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-CONFIG_USB_EHCI_PCI=m
-CONFIG_USB_EHCI_FSL=m
-CONFIG_USB_EHCI_HCD_NPCM7XX=m
-CONFIG_USB_EHCI_HCD_PLATFORM=m
-CONFIG_USB_OXU210HP_HCD=m
-CONFIG_USB_ISP116X_HCD=m
-CONFIG_USB_FOTG210_HCD=m
-CONFIG_USB_MAX3421_HCD=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_OHCI_HCD_PCI=m
-CONFIG_USB_OHCI_HCD_SSB=y
-CONFIG_USB_OHCI_HCD_PLATFORM=m
-CONFIG_USB_UHCI_HCD=m
-CONFIG_USB_U132_HCD=m
-CONFIG_USB_SL811_HCD=m
-# CONFIG_USB_SL811_HCD_ISO is not set
-CONFIG_USB_SL811_CS=m
-CONFIG_USB_R8A66597_HCD=m
-CONFIG_USB_HCD_BCMA=m
-CONFIG_USB_HCD_SSB=m
-# CONFIG_USB_HCD_TEST_MODE is not set
-
-#
-# USB Device Class drivers
-#
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_WDM=m
-CONFIG_USB_TMC=m
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-CONFIG_USB_STORAGE_REALTEK=m
-CONFIG_REALTEK_AUTOPM=y
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_ISD200=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_STORAGE_ALAUDA=m
-CONFIG_USB_STORAGE_ONETOUCH=m
-CONFIG_USB_STORAGE_KARMA=m
-CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-CONFIG_USB_STORAGE_ENE_UB6250=m
-CONFIG_USB_UAS=m
-
-#
-# USB Imaging devices
-#
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USBIP_CORE=m
-CONFIG_USBIP_VHCI_HCD=m
-CONFIG_USBIP_VHCI_HC_PORTS=8
-CONFIG_USBIP_VHCI_NR_HCS=1
-CONFIG_USBIP_HOST=m
-CONFIG_USBIP_VUDC=m
-# CONFIG_USBIP_DEBUG is not set
-CONFIG_USB_CDNS_SUPPORT=m
-CONFIG_USB_CDNS_HOST=y
-CONFIG_USB_CDNS3=m
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_USB_CDNS3_HOST=y
-CONFIG_USB_CDNS3_PCI_WRAP=m
-CONFIG_USB_CDNSP_PCI=m
-CONFIG_USB_CDNSP_GADGET=y
-CONFIG_USB_CDNSP_HOST=y
-CONFIG_USB_MUSB_HDRC=m
-# CONFIG_USB_MUSB_HOST is not set
-# CONFIG_USB_MUSB_GADGET is not set
-CONFIG_USB_MUSB_DUAL_ROLE=y
-
-#
-# Platform Glue Layer
-#
-
-#
-# MUSB DMA mode
-#
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_DWC3=m
-# CONFIG_USB_DWC3_ULPI is not set
-# CONFIG_USB_DWC3_HOST is not set
-# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_DUAL_ROLE=y
-
-#
-# Platform Glue Driver Support
-#
-CONFIG_USB_DWC3_PCI=m
-CONFIG_USB_DWC3_HAPS=m
-CONFIG_USB_DWC2=m
-# CONFIG_USB_DWC2_HOST is not set
-
-#
-# Gadget/Dual-role mode requires USB Gadget support to be enabled
-#
-# CONFIG_USB_DWC2_PERIPHERAL is not set
-CONFIG_USB_DWC2_DUAL_ROLE=y
-CONFIG_USB_DWC2_PCI=m
-# CONFIG_USB_DWC2_DEBUG is not set
-# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
-CONFIG_USB_CHIPIDEA=m
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_PCI=m
-CONFIG_USB_CHIPIDEA_MSM=m
-CONFIG_USB_CHIPIDEA_GENERIC=m
-CONFIG_USB_ISP1760=m
-CONFIG_USB_ISP1760_HCD=y
-CONFIG_USB_ISP1761_UDC=y
-# CONFIG_USB_ISP1760_HOST_ROLE is not set
-# CONFIG_USB_ISP1760_GADGET_ROLE is not set
-CONFIG_USB_ISP1760_DUAL_ROLE=y
-
-#
-# USB port drivers
-#
-CONFIG_USB_USS720=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_SIMPLE=m
-CONFIG_USB_SERIAL_AIRCABLE=m
-CONFIG_USB_SERIAL_ARK3116=m
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_CH341=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CP210X=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_F81232=m
-CONFIG_USB_SERIAL_F8153X=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_IUU=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_METRO=m
-CONFIG_USB_SERIAL_MOS7720=m
-CONFIG_USB_SERIAL_MOS7715_PARPORT=y
-CONFIG_USB_SERIAL_MOS7840=m
-CONFIG_USB_SERIAL_MXUPORT=m
-CONFIG_USB_SERIAL_NAVMAN=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_OTI6858=m
-CONFIG_USB_SERIAL_QCAUX=m
-CONFIG_USB_SERIAL_QUALCOMM=m
-CONFIG_USB_SERIAL_SPCP8X5=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_SAFE_PADDED=y
-CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-CONFIG_USB_SERIAL_SYMBOL=m
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_WWAN=m
-CONFIG_USB_SERIAL_OPTION=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_SERIAL_OPTICON=m
-CONFIG_USB_SERIAL_XSENS_MT=m
-CONFIG_USB_SERIAL_WISHBONE=m
-CONFIG_USB_SERIAL_SSU100=m
-CONFIG_USB_SERIAL_QT2=m
-# CONFIG_USB_SERIAL_UPD78F0730 is not set
-CONFIG_USB_SERIAL_XR=m
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_ADUTUX=m
-CONFIG_USB_SEVSEG=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_CYPRESS_CY7C63=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_IDMOUSE=m
-CONFIG_USB_FTDI_ELAN=m
-CONFIG_USB_APPLEDISPLAY=m
-CONFIG_USB_QCOM_EUD=m
-CONFIG_APPLE_MFI_FASTCHARGE=m
-CONFIG_USB_SISUSBVGA=m
-CONFIG_USB_LD=m
-CONFIG_USB_TRANCEVIBRATOR=m
-CONFIG_USB_IOWARRIOR=m
-CONFIG_USB_TEST=m
-CONFIG_USB_EHSET_TEST_FIXTURE=m
-CONFIG_USB_ISIGHTFW=m
-CONFIG_USB_YUREX=m
-CONFIG_USB_EZUSB_FX2=m
-CONFIG_USB_HUB_USB251XB=m
-CONFIG_USB_HSIC_USB3503=m
-CONFIG_USB_HSIC_USB4604=m
-CONFIG_USB_LINK_LAYER_TEST=m
-CONFIG_USB_CHAOSKEY=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_CXACRU=m
-CONFIG_USB_UEAGLEATM=m
-CONFIG_USB_XUSBATM=m
-
-#
-# USB Physical Layer drivers
-#
-CONFIG_USB_PHY=y
-CONFIG_NOP_USB_XCEIV=m
-CONFIG_USB_GPIO_VBUS=m
-CONFIG_TAHVO_USB=m
-CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y
-CONFIG_USB_ISP1301=m
-# end of USB Physical Layer drivers
-
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
-CONFIG_U_SERIAL_CONSOLE=y
-
-#
-# USB Peripheral Controller
-#
-CONFIG_USB_FOTG210_UDC=m
-CONFIG_USB_GR_UDC=m
-CONFIG_USB_R8A66597=m
-CONFIG_USB_PXA27X=m
-CONFIG_USB_MV_UDC=m
-CONFIG_USB_MV_U3D=m
-CONFIG_USB_SNP_CORE=m
-CONFIG_USB_M66592=m
-CONFIG_USB_BDC_UDC=m
-CONFIG_USB_AMD5536UDC=m
-CONFIG_USB_NET2272=m
-CONFIG_USB_NET2272_DMA=y
-CONFIG_USB_NET2280=m
-CONFIG_USB_GOKU=m
-CONFIG_USB_EG20T=m
-CONFIG_USB_MAX3420_UDC=m
-# CONFIG_USB_DUMMY_HCD is not set
-# end of USB Peripheral Controller
-
-CONFIG_USB_LIBCOMPOSITE=m
-CONFIG_USB_F_ACM=m
-CONFIG_USB_F_SS_LB=m
-CONFIG_USB_U_SERIAL=m
-CONFIG_USB_U_ETHER=m
-CONFIG_USB_U_AUDIO=m
-CONFIG_USB_F_SERIAL=m
-CONFIG_USB_F_OBEX=m
-CONFIG_USB_F_NCM=m
-CONFIG_USB_F_ECM=m
-CONFIG_USB_F_PHONET=m
-CONFIG_USB_F_EEM=m
-CONFIG_USB_F_SUBSET=m
-CONFIG_USB_F_RNDIS=m
-CONFIG_USB_F_MASS_STORAGE=m
-CONFIG_USB_F_FS=m
-CONFIG_USB_F_UAC1=m
-CONFIG_USB_F_UAC2=m
-CONFIG_USB_F_UVC=m
-CONFIG_USB_F_MIDI=m
-CONFIG_USB_F_HID=m
-CONFIG_USB_F_PRINTER=m
-CONFIG_USB_F_TCM=m
-CONFIG_USB_CONFIGFS=m
-CONFIG_USB_CONFIGFS_SERIAL=y
-CONFIG_USB_CONFIGFS_ACM=y
-CONFIG_USB_CONFIGFS_OBEX=y
-CONFIG_USB_CONFIGFS_NCM=y
-CONFIG_USB_CONFIGFS_ECM=y
-CONFIG_USB_CONFIGFS_ECM_SUBSET=y
-CONFIG_USB_CONFIGFS_RNDIS=y
-CONFIG_USB_CONFIGFS_EEM=y
-CONFIG_USB_CONFIGFS_PHONET=y
-CONFIG_USB_CONFIGFS_MASS_STORAGE=y
-CONFIG_USB_CONFIGFS_F_LB_SS=y
-CONFIG_USB_CONFIGFS_F_FS=y
-CONFIG_USB_CONFIGFS_F_UAC1=y
-# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
-CONFIG_USB_CONFIGFS_F_UAC2=y
-CONFIG_USB_CONFIGFS_F_MIDI=y
-CONFIG_USB_CONFIGFS_F_HID=y
-CONFIG_USB_CONFIGFS_F_UVC=y
-CONFIG_USB_CONFIGFS_F_PRINTER=y
-CONFIG_USB_CONFIGFS_F_TCM=y
-
-#
-# USB Gadget precomposed configurations
-#
-CONFIG_USB_ZERO=m
-CONFIG_USB_ZERO_HNPTEST=y
-CONFIG_USB_AUDIO=m
-CONFIG_GADGET_UAC1=y
-# CONFIG_GADGET_UAC1_LEGACY is not set
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-CONFIG_USB_ETH_EEM=y
-CONFIG_USB_G_NCM=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FUNCTIONFS=m
-CONFIG_USB_FUNCTIONFS_ETH=y
-CONFIG_USB_FUNCTIONFS_RNDIS=y
-CONFIG_USB_FUNCTIONFS_GENERIC=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_GADGET_TARGET=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_MIDI_GADGET=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_NOKIA=m
-CONFIG_USB_G_ACM_MS=m
-CONFIG_USB_G_MULTI=m
-CONFIG_USB_G_MULTI_RNDIS=y
-CONFIG_USB_G_MULTI_CDC=y
-CONFIG_USB_G_HID=m
-# CONFIG_USB_G_DBGP is not set
-CONFIG_USB_G_WEBCAM=m
-CONFIG_USB_RAW_GADGET=m
-# end of USB Gadget precomposed configurations
-
-CONFIG_TYPEC=m
-CONFIG_TYPEC_TCPM=m
-CONFIG_TYPEC_TCPCI=m
-CONFIG_TYPEC_RT1711H=m
-CONFIG_TYPEC_MT6360=m
-CONFIG_TYPEC_TCPCI_MT6370=m
-CONFIG_TYPEC_TCPCI_MAXIM=m
-CONFIG_TYPEC_FUSB302=m
-CONFIG_TYPEC_UCSI=m
-CONFIG_UCSI_CCG=m
-CONFIG_UCSI_ACPI=m
-CONFIG_UCSI_STM32G0=m
-CONFIG_TYPEC_TPS6598X=m
-CONFIG_TYPEC_ANX7411=m
-CONFIG_TYPEC_RT1719=m
-CONFIG_TYPEC_HD3SS3220=m
-CONFIG_TYPEC_STUSB160X=m
-CONFIG_TYPEC_WUSB3801=m
-CONFIG_TYPEC_EXTCON=m
-
-#
-# USB Type-C Multiplexer/DeMultiplexer Switch support
-#
-CONFIG_TYPEC_MUX_PI3USB30532=m
-CONFIG_TYPEC_MUX_INTEL_PMC=m
-# end of USB Type-C Multiplexer/DeMultiplexer Switch support
-
-#
-# USB Type-C Alternate Mode drivers
-#
-CONFIG_TYPEC_DP_ALTMODE=m
-CONFIG_TYPEC_NVIDIA_ALTMODE=m
-# end of USB Type-C Alternate Mode drivers
-
-CONFIG_USB_ROLE_SWITCH=m
-CONFIG_USB_ROLES_INTEL_XHCI=m
-CONFIG_MMC=m
-CONFIG_MMC_BLOCK=m
-CONFIG_MMC_BLOCK_MINORS=8
-CONFIG_SDIO_UART=m
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_SDHCI=m
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PCI=m
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI_ACPI=m
-CONFIG_MMC_SDHCI_PLTFM=m
-CONFIG_MMC_SDHCI_F_SDH30=m
-CONFIG_MMC_WBSD=m
-CONFIG_MMC_ALCOR=m
-CONFIG_MMC_TIFM_SD=m
-CONFIG_MMC_SPI=m
-CONFIG_MMC_SDRICOH_CS=m
-CONFIG_MMC_CB710=m
-CONFIG_MMC_VIA_SDMMC=m
-CONFIG_MMC_VUB300=m
-CONFIG_MMC_USHC=m
-CONFIG_MMC_USDHI6ROL0=m
-CONFIG_MMC_REALTEK_PCI=m
-CONFIG_MMC_REALTEK_USB=m
-CONFIG_MMC_CQHCI=m
-CONFIG_MMC_HSQ=m
-# CONFIG_MMC_TOSHIBA_PCI is not set
-CONFIG_MMC_MTK=m
-CONFIG_MMC_SDHCI_XENON=m
-CONFIG_MEMSTICK=m
-# CONFIG_MEMSTICK_DEBUG is not set
-
-#
-# MemoryStick drivers
-#
-# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
-CONFIG_MSPRO_BLOCK=m
-CONFIG_MS_BLOCK=m
-
-#
-# MemoryStick Host Controller Drivers
-#
-CONFIG_MEMSTICK_TIFM_MS=m
-CONFIG_MEMSTICK_JMICRON_38X=m
-CONFIG_MEMSTICK_R592=m
-CONFIG_MEMSTICK_REALTEK_PCI=m
-CONFIG_MEMSTICK_REALTEK_USB=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_CLASS_FLASH=m
-CONFIG_LEDS_CLASS_MULTICOLOR=m
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-
-#
-# LED drivers
-#
-CONFIG_LEDS_APU=m
-CONFIG_LEDS_LM3530=m
-CONFIG_LEDS_LM3532=m
-CONFIG_LEDS_LM3533=m
-CONFIG_LEDS_LM3642=m
-CONFIG_LEDS_MT6323=m
-CONFIG_LEDS_PCA9532=m
-CONFIG_LEDS_PCA9532_GPIO=y
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_LP3944=m
-CONFIG_LEDS_LP3952=m
-CONFIG_LEDS_LP50XX=m
-CONFIG_LEDS_CLEVO_MAIL=m
-CONFIG_LEDS_PCA955X=m
-# CONFIG_LEDS_PCA955X_GPIO is not set
-CONFIG_LEDS_PCA963X=m
-CONFIG_LEDS_WM831X_STATUS=m
-CONFIG_LEDS_DA9052=m
-CONFIG_LEDS_DAC124S085=m
-CONFIG_LEDS_PWM=m
-CONFIG_LEDS_REGULATOR=m
-CONFIG_LEDS_BD2802=m
-CONFIG_LEDS_INTEL_SS4200=m
-CONFIG_LEDS_LT3593=m
-CONFIG_LEDS_MC13783=m
-CONFIG_LEDS_TCA6507=m
-CONFIG_LEDS_TLC591XX=m
-CONFIG_LEDS_LM355x=m
-CONFIG_LEDS_MENF21BMC=m
-CONFIG_LEDS_IS31FL319X=m
-
-#
-# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
-#
-CONFIG_LEDS_BLINKM=m
-CONFIG_LEDS_MLXCPLD=m
-CONFIG_LEDS_MLXREG=m
-CONFIG_LEDS_USER=m
-CONFIG_LEDS_NIC78BX=m
-CONFIG_LEDS_TI_LMU_COMMON=m
-CONFIG_LEDS_BCM63138=m
-CONFIG_LEDS_LM36274=m
-CONFIG_LEDS_TPS6105X=m
-
-#
-# Flash and Torch LED drivers
-#
-CONFIG_LEDS_AS3645A=m
-CONFIG_LEDS_LM3601X=m
-CONFIG_LEDS_RT8515=m
-CONFIG_LEDS_SGM3140=m
-CONFIG_LEDS_SIEMENS_SIMATIC_IPC=m
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_ONESHOT=m
-CONFIG_LEDS_TRIGGER_DISK=y
-# CONFIG_LEDS_TRIGGER_MTD is not set
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_LEDS_TRIGGER_BACKLIGHT=m
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_ACTIVITY=m
-CONFIG_LEDS_TRIGGER_GPIO=m
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-CONFIG_LEDS_TRIGGER_TRANSIENT=m
-CONFIG_LEDS_TRIGGER_CAMERA=m
-CONFIG_LEDS_TRIGGER_PANIC=y
-CONFIG_LEDS_TRIGGER_NETDEV=m
-CONFIG_LEDS_TRIGGER_PATTERN=m
-CONFIG_LEDS_TRIGGER_AUDIO=m
-CONFIG_LEDS_TRIGGER_TTY=m
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_A11Y_BRAILLE_CONSOLE=y
-
-#
-# Speakup console speech
-#
-CONFIG_SPEAKUP=m
-CONFIG_SPEAKUP_SYNTH_ACNTSA=m
-CONFIG_SPEAKUP_SYNTH_APOLLO=m
-CONFIG_SPEAKUP_SYNTH_AUDPTR=m
-CONFIG_SPEAKUP_SYNTH_BNS=m
-CONFIG_SPEAKUP_SYNTH_DECTLK=m
-CONFIG_SPEAKUP_SYNTH_DECEXT=m
-CONFIG_SPEAKUP_SYNTH_LTLK=m
-CONFIG_SPEAKUP_SYNTH_SOFT=m
-CONFIG_SPEAKUP_SYNTH_SPKOUT=m
-CONFIG_SPEAKUP_SYNTH_TXPRT=m
-# CONFIG_SPEAKUP_SYNTH_DUMMY is not set
-# end of Speakup console speech
-
-CONFIG_INFINIBAND=m
-CONFIG_INFINIBAND_USER_MAD=m
-CONFIG_INFINIBAND_USER_ACCESS=m
-CONFIG_INFINIBAND_USER_MEM=y
-CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
-CONFIG_INFINIBAND_ADDR_TRANS=y
-CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
-CONFIG_INFINIBAND_VIRT_DMA=y
-CONFIG_INFINIBAND_MTHCA=m
-# CONFIG_INFINIBAND_MTHCA_DEBUG is not set
-CONFIG_INFINIBAND_QIB=m
-CONFIG_INFINIBAND_QIB_DCA=y
-CONFIG_INFINIBAND_CXGB4=m
-CONFIG_INFINIBAND_EFA=m
-CONFIG_INFINIBAND_ERDMA=m
-CONFIG_VIDEO_STKWEBCAM=m
-CONFIG_INFINIBAND_IRDMA=m
-CONFIG_MLX4_INFINIBAND=m
-CONFIG_MLX5_INFINIBAND=m
-CONFIG_INFINIBAND_OCRDMA=m
-CONFIG_INFINIBAND_VMWARE_PVRDMA=m
-CONFIG_INFINIBAND_USNIC=m
-CONFIG_INFINIBAND_BNXT_RE=m
-CONFIG_INFINIBAND_HFI1=m
-# CONFIG_HFI1_DEBUG_SDMA_ORDER is not set
-# CONFIG_SDMA_VERBOSITY is not set
-CONFIG_INFINIBAND_QEDR=m
-CONFIG_INFINIBAND_RDMAVT=m
-CONFIG_RDMA_RXE=m
-CONFIG_RDMA_SIW=m
-CONFIG_INFINIBAND_IPOIB=m
-CONFIG_INFINIBAND_IPOIB_CM=y
-# CONFIG_INFINIBAND_IPOIB_DEBUG is not set
-CONFIG_INFINIBAND_SRP=m
-CONFIG_INFINIBAND_SRPT=m
-CONFIG_INFINIBAND_ISER=m
-CONFIG_INFINIBAND_ISERT=m
-CONFIG_INFINIBAND_RTRS=m
-CONFIG_INFINIBAND_RTRS_CLIENT=m
-CONFIG_INFINIBAND_RTRS_SERVER=m
-CONFIG_INFINIBAND_OPA_VNIC=m
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EDAC=m
-CONFIG_EDAC_LEGACY_SYSFS=y
-# CONFIG_EDAC_DEBUG is not set
-CONFIG_EDAC_DECODE_MCE=m
-CONFIG_EDAC_GHES=y
-CONFIG_EDAC_AMD64=m
-CONFIG_EDAC_E752X=m
-CONFIG_EDAC_I82975X=m
-CONFIG_EDAC_I3000=m
-CONFIG_EDAC_I3200=m
-CONFIG_EDAC_IE31200=m
-CONFIG_EDAC_X38=m
-CONFIG_EDAC_I5400=m
-CONFIG_EDAC_I7CORE=m
-CONFIG_EDAC_I5000=m
-CONFIG_EDAC_I5100=m
-CONFIG_EDAC_I7300=m
-CONFIG_EDAC_SBRIDGE=m
-CONFIG_EDAC_SKX=m
-CONFIG_EDAC_I10NM=m
-CONFIG_EDAC_PND2=m
-CONFIG_EDAC_IGEN6=m
-CONFIG_RTC_LIB=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-CONFIG_RTC_SYSTOHC=y
-CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-CONFIG_RTC_NVMEM=y
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-CONFIG_RTC_DRV_88PM80X=m
-CONFIG_RTC_DRV_ABB5ZES3=m
-CONFIG_RTC_DRV_ABEOZ9=m
-CONFIG_RTC_DRV_ABX80X=m
-CONFIG_RTC_DRV_DS1307=m
-# CONFIG_RTC_DRV_DS1307_CENTURY is not set
-CONFIG_RTC_DRV_DS1374=m
-CONFIG_RTC_DRV_DS1374_WDT=y
-CONFIG_RTC_DRV_DS1672=m
-CONFIG_RTC_DRV_MAX6900=m
-CONFIG_RTC_DRV_MAX8907=m
-CONFIG_RTC_DRV_RS5C372=m
-CONFIG_RTC_DRV_ISL1208=m
-CONFIG_RTC_DRV_ISL12022=m
-CONFIG_RTC_DRV_X1205=m
-CONFIG_RTC_DRV_PCF8523=m
-CONFIG_RTC_DRV_PCF85063=m
-CONFIG_RTC_DRV_PCF85363=m
-CONFIG_RTC_DRV_PCF8563=m
-CONFIG_RTC_DRV_PCF8583=m
-CONFIG_RTC_DRV_M41T80=m
-CONFIG_RTC_DRV_M41T80_WDT=y
-CONFIG_RTC_DRV_BQ32K=m
-CONFIG_RTC_DRV_S35390A=m
-CONFIG_RTC_DRV_FM3130=m
-CONFIG_RTC_DRV_RX8010=m
-CONFIG_RTC_DRV_RX8581=m
-CONFIG_RTC_DRV_RX8025=m
-CONFIG_RTC_DRV_EM3027=m
-CONFIG_RTC_DRV_RV3028=m
-CONFIG_RTC_DRV_RV3032=m
-CONFIG_RTC_DRV_RV8803=m
-CONFIG_RTC_DRV_SD3078=m
-
-#
-# SPI RTC drivers
-#
-CONFIG_RTC_DRV_M41T93=m
-CONFIG_RTC_DRV_M41T94=m
-CONFIG_RTC_DRV_DS1302=m
-CONFIG_RTC_DRV_DS1305=m
-CONFIG_RTC_DRV_DS1343=m
-CONFIG_RTC_DRV_DS1347=m
-CONFIG_RTC_DRV_DS1390=m
-CONFIG_RTC_DRV_MAX6916=m
-CONFIG_RTC_DRV_R9701=m
-CONFIG_RTC_DRV_RX4581=m
-CONFIG_RTC_DRV_RS5C348=m
-CONFIG_RTC_DRV_MAX6902=m
-CONFIG_RTC_DRV_PCF2123=m
-CONFIG_RTC_DRV_MCP795=m
-CONFIG_RTC_I2C_AND_SPI=m
-
-#
-# SPI and I2C RTC drivers
-#
-CONFIG_RTC_DRV_DS3232=m
-CONFIG_RTC_DRV_DS3232_HWMON=y
-CONFIG_RTC_DRV_PCF2127=m
-CONFIG_RTC_DRV_RV3029C2=m
-CONFIG_RTC_DRV_RV3029_HWMON=y
-CONFIG_RTC_DRV_RX6110=m
-
-#
-# Platform RTC drivers
-#
-CONFIG_RTC_DRV_CMOS=y
-CONFIG_RTC_DRV_DS1286=m
-CONFIG_RTC_DRV_DS1511=m
-CONFIG_RTC_DRV_DS1553=m
-CONFIG_RTC_DRV_DS1685_FAMILY=m
-CONFIG_RTC_DRV_DS1685=y
-# CONFIG_RTC_DRV_DS1689 is not set
-# CONFIG_RTC_DRV_DS17285 is not set
-# CONFIG_RTC_DRV_DS17485 is not set
-# CONFIG_RTC_DRV_DS17885 is not set
-CONFIG_RTC_DRV_DS1742=m
-CONFIG_RTC_DRV_DS2404=m
-CONFIG_RTC_DRV_DA9052=m
-CONFIG_RTC_DRV_DA9063=m
-CONFIG_RTC_DRV_STK17TA8=m
-CONFIG_RTC_DRV_M48T86=m
-CONFIG_RTC_DRV_M48T35=m
-CONFIG_RTC_DRV_M48T59=m
-CONFIG_RTC_DRV_MSM6242=m
-CONFIG_RTC_DRV_BQ4802=m
-CONFIG_RTC_DRV_RP5C01=m
-CONFIG_RTC_DRV_V3020=m
-CONFIG_RTC_DRV_OPTEE=m
-CONFIG_RTC_DRV_WM831X=m
-CONFIG_RTC_DRV_PCF50633=m
-# CONFIG_RTC_DRV_CROS_EC is not set
-
-#
-# on-CPU RTC drivers
-#
-CONFIG_RTC_DRV_FTRTC010=m
-CONFIG_RTC_DRV_PCAP=m
-CONFIG_RTC_DRV_MC13XXX=m
-CONFIG_RTC_DRV_MT6397=m
-
-#
-# HID Sensor RTC drivers
-#
-CONFIG_RTC_DRV_HID_SENSOR_TIME=m
-CONFIG_RTC_DRV_GOLDFISH=m
-CONFIG_RTC_DRV_WILCO_EC=m
+CONFIG_ARCH_USES_PG_UNCACHED=y
+CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
+CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
+CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
+CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
+CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y
+CONFIG_ARCH_WANT_OPTIMIZE_VMEMMAP=y
+CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ARCNET_1051=m
+CONFIG_ARCNET_1201=m
+CONFIG_ARCNET_CAP=m
+CONFIG_ARCNET_COM20020_CS=m
+CONFIG_ARCNET_COM20020=m
+CONFIG_ARCNET_COM20020_PCI=m
+CONFIG_ARCNET_COM90xxIO=m
+CONFIG_ARCNET_COM90xx=m
+CONFIG_ARCNET=m
+CONFIG_ARCNET_RAW=m
+CONFIG_ARCNET_RIM_I=m
+CONFIG_AS3935=m
+CONFIG_AS73211=m
+CONFIG_AS_AVX512=y
+CONFIG_AS_GFNI=y
+CONFIG_AS_IS_LLVM=y
+CONFIG_ASN1_ENCODER=m
+CONFIG_AS_SHA1_NI=y
+CONFIG_AS_SHA256_NI=y
+CONFIG_AS_TPAUSE=y
+CONFIG_ASUS_LAPTOP=m
+CONFIG_ASUS_NB_WMI=m
+CONFIG_ASUS_TF103C_DOCK=m
+CONFIG_ASUS_WIRELESS=m
+CONFIG_ASUS_WMI=m
+CONFIG_AS_VERSION=160006
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_ASYNC_TX_DMA=y
+CONFIG_ASYNC_XOR=m
+CONFIG_AT76C50X_USB=m
+CONFIG_AT803X_PHY=m
+CONFIG_ATA_ACPI=y
+CONFIG_ATA_GENERIC=m
+CONFIG_ATA=m
+CONFIG_ATA_OVER_ETH=m
+CONFIG_ATA_PIIX=m
+CONFIG_ATARI_PARTITION=y
+CONFIG_ATH10K_CE=y
+CONFIG_ATH10K=m
+CONFIG_ATH10K_PCI=m
+CONFIG_ATH10K_SDIO=m
+CONFIG_ATH10K_USB=m
+CONFIG_ATH11K=m
+CONFIG_ATH11K_PCI=m
+CONFIG_ATH12K=m
+CONFIG_ATH5K=m
+CONFIG_ATH5K_PCI=y
+CONFIG_ATH6KL=m
+CONFIG_ATH6KL_SDIO=m
+CONFIG_ATH6KL_USB=m
+CONFIG_ATH9K_AHB=y
+CONFIG_ATH9K_BTCOEX_SUPPORT=y
+CONFIG_ATH9K_CHANNEL_CONTEXT=y
+CONFIG_ATH9K_COMMON=m
+CONFIG_ATH9K_DYNACK=y
+CONFIG_ATH9K_HTC=m
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_HWRNG=y
+CONFIG_ATH9K=m
+CONFIG_ATH9K_PCI_NO_EEPROM=m
+CONFIG_ATH9K_PCI=y
+CONFIG_ATH9K_PCOEM=y
+CONFIG_ATH9K_RFKILL=y
+CONFIG_ATH9K_WOW=y
+CONFIG_ATH_COMMON=m
+CONFIG_ATLAS_EZO_SENSOR=m
+CONFIG_ATLAS_PH_SENSOR=m
+CONFIG_ATMEL=m
+CONFIG_AUDIT_ARCH=y
+CONFIG_AUXDISPLAY=y
+CONFIG_AUXILIARY_BUS=y
+CONFIG_AW96103=m
+CONFIG_AX88796B_PHY=m
+CONFIG_AXP20X_ADC=m
+CONFIG_AXP20X_POWER=m
+CONFIG_AXP288_ADC=m
+CONFIG_AXP288_CHARGER=m
+CONFIG_AXP288_FUEL_GAUGE=m
+CONFIG_B43_BCMA_PIO=y
+CONFIG_B43_BCMA=y
+CONFIG_B43_BUSES_BCMA_AND_SSB=y
+CONFIG_B43_HWRNG=y
+CONFIG_B43_LEDS=y
+CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
+CONFIG_B43LEGACY_DMA=y
+CONFIG_B43LEGACY_HWRNG=y
+CONFIG_B43LEGACY_LEDS=y
+CONFIG_B43LEGACY=m
+CONFIG_B43LEGACY_PCI_AUTOSELECT=y
+CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
+CONFIG_B43LEGACY_PIO=y
+CONFIG_B43=m
+CONFIG_B43_PCI_AUTOSELECT=y
+CONFIG_B43_PCICORE_AUTOSELECT=y
+CONFIG_B43_PHY_G=y
+CONFIG_B43_PHY_HT=y
+CONFIG_B43_PHY_LP=y
+CONFIG_B43_PHY_N=y
+CONFIG_B43_PIO=y
+CONFIG_B43_SDIO=y
+CONFIG_B43_SSB=y
+CONFIG_BACKLIGHT_88PM860X=m
+CONFIG_BACKLIGHT_AAT2870=m
+CONFIG_BACKLIGHT_ADP5520=m
+CONFIG_BACKLIGHT_ADP8860=m
+CONFIG_BACKLIGHT_ADP8870=m
+CONFIG_BACKLIGHT_APPLE=m
+CONFIG_BACKLIGHT_ARCXCNN=m
+CONFIG_BACKLIGHT_AS3711=m
+CONFIG_BACKLIGHT_BD6107=m
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_DA903X=m
+CONFIG_BACKLIGHT_DA9052=m
+CONFIG_BACKLIGHT_GPIO=m
+CONFIG_BACKLIGHT_KTD253=m
+CONFIG_BACKLIGHT_KTD2801=m
+CONFIG_BACKLIGHT_KTZ8866=m
+CONFIG_BACKLIGHT_LM3533=m
+CONFIG_BACKLIGHT_LM3630A=m
+CONFIG_BACKLIGHT_LM3639=m
+CONFIG_BACKLIGHT_LP855X=m
+CONFIG_BACKLIGHT_LP8788=m
+CONFIG_BACKLIGHT_LV5207LP=m
+CONFIG_BACKLIGHT_MAX8925=m
+CONFIG_BACKLIGHT_MP3309C=m
+CONFIG_BACKLIGHT_MT6370=m
+CONFIG_BACKLIGHT_PANDORA=m
+CONFIG_BACKLIGHT_PCF50633=m
+CONFIG_BACKLIGHT_PWM=m
+CONFIG_BACKLIGHT_QCOM_WLED=m
+CONFIG_BACKLIGHT_RAVE_SP=m
+CONFIG_BACKLIGHT_RT4831=m
+CONFIG_BACKLIGHT_SAHARA=m
+CONFIG_BACKLIGHT_SKY81452=m
+CONFIG_BACKLIGHT_WM831X=m
+CONFIG_BARCO_P50_GPIO=m
+CONFIG_BAREUDP=m
+CONFIG_BATTERY_88PM860X=m
+CONFIG_BATTERY_AXP20X=m
+CONFIG_BATTERY_BQ27XXX_HDQ=m
+CONFIG_BATTERY_BQ27XXX_I2C=m
+CONFIG_BATTERY_BQ27XXX=m
+CONFIG_BATTERY_CW2015=m
+CONFIG_BATTERY_DA9030=m
+CONFIG_BATTERY_DA9052=m
+CONFIG_BATTERY_DA9150=m
+CONFIG_BATTERY_DS2760=m
+CONFIG_BATTERY_DS2780=m
+CONFIG_BATTERY_DS2781=m
+CONFIG_BATTERY_DS2782=m
+CONFIG_BATTERY_GAUGE_LTC2941=m
+CONFIG_BATTERY_GOLDFISH=m
+CONFIG_BATTERY_MAX17040=m
+CONFIG_BATTERY_MAX17042=m
+CONFIG_BATTERY_MAX1721X=m
+CONFIG_BATTERY_RT5033=m
+CONFIG_BATTERY_RX51=m
+CONFIG_BATTERY_SBS=m
+CONFIG_BATTERY_SURFACE=m
+CONFIG_BATTERY_TWL4030_MADC=m
+CONFIG_BATTERY_UG3105=m
+CONFIG_BCACHE_ASYNC_REGISTRATION=y
+CONFIG_BCACHE=m
+CONFIG_BCH_CONST_M=14
+CONFIG_BCH_CONST_T=4
+CONFIG_BCH=m
+CONFIG_BCM54140_PHY=m
+CONFIG_BCM7XXX_PHY=m
+CONFIG_BCM84881_PHY=m
+CONFIG_BCM87XX_PHY=m
+CONFIG_BCMA_BLOCKIO=y
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
+CONFIG_BCMA_DRIVER_GPIO=y
+CONFIG_BCMA_DRIVER_PCI=y
+CONFIG_BCMA_HOST_PCI_POSSIBLE=y
+CONFIG_BCMA_HOST_PCI=y
+CONFIG_BCMA_HOST_SOC=y
+CONFIG_BCMA=m
+CONFIG_BCMA_SFLASH=y
+CONFIG_BCM_KONA_USB2_PHY=m
+CONFIG_BCM_NET_PHYLIB=m
+CONFIG_BCM_NET_PHYPTP=m
+CONFIG_BCM_VK=m
+CONFIG_BCM_VK_TTY=y
+CONFIG_BD79703=m
+CONFIG_BE2ISCSI=m
+CONFIG_BFQ_GROUP_IOSCHED=y
+CONFIG_BH1745=m
+CONFIG_BH1750=m
+CONFIG_BH1780=m
+CONFIG_BHYVE_GUEST=y
+CONFIG_BINFMT_MISC=m
+CONFIG_BLK_CGROUP_IOLATENCY=y
+CONFIG_BLK_CGROUP_PUNT_BIO=y
+CONFIG_BLK_CGROUP_RWSTAT=y
+CONFIG_BLK_DEV_3W_XXXX_RAID=m
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_DM=m
+CONFIG_BLK_DEV_DRBD=m
+CONFIG_BLK_DEV_FD=m
+CONFIG_BLK_DEV_FD_RAWCMD=y
+CONFIG_BLK_DEV_INTEGRITY_T10=m
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
+CONFIG_BLK_DEV_PMEM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_RBD=m
+CONFIG_BLK_DEV_RNBD_CLIENT=m
+CONFIG_BLK_DEV_RNBD_SERVER=m
+CONFIG_BLK_DEV_RNBD=y
+CONFIG_BLK_DEV_SD=m
+CONFIG_BLK_DEV_SR=m
+CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BLK_DEV_UBLK=m
+CONFIG_BLK_DEV_ZONED_LOOP=m
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_ICQ=y
+CONFIG_BLK_MQ_STACKING=y
+CONFIG_BLK_WBT_MQ=y
+CONFIG_BLK_WBT=y
+CONFIG_BLOCK_HOLDER_DEPRECATED=y
+CONFIG_BMA220=m
+CONFIG_BMA400_I2C=m
+CONFIG_BMA400=m
+CONFIG_BMA400_SPI=m
+CONFIG_BMC150_ACCEL_I2C=m
+CONFIG_BMC150_ACCEL=m
+CONFIG_BMC150_ACCEL_SPI=m
+CONFIG_BMC150_MAGN_I2C=m
+CONFIG_BMC150_MAGN=m
+CONFIG_BMC150_MAGN_SPI=m
+CONFIG_BME680_I2C=m
+CONFIG_BME680=m
+CONFIG_BME680_SPI=m
+CONFIG_BMG160_I2C=m
+CONFIG_BMG160=m
+CONFIG_BMG160_SPI=m
+CONFIG_BMI088_ACCEL=m
+CONFIG_BMI088_ACCEL_SPI=m
+CONFIG_BMI160_I2C=m
+CONFIG_BMI160=m
+CONFIG_BMI160_SPI=m
+CONFIG_BMI323_I2C=m
+CONFIG_BMI323_SPI=m
+CONFIG_BMP280_I2C=m
+CONFIG_BMP280=m
+CONFIG_BMP280_SPI=m
+CONFIG_BOARD_TPCI200=m
+CONFIG_BONDING=m
+CONFIG_BOOT_CONFIG=y
+CONFIG_BOOT_VESA_SUPPORT=y
+CONFIG_BOSCH_BNO055_I2C=m
+CONFIG_BOSCH_BNO055=m
+CONFIG_BOSCH_BNO055_SERIAL=m
+CONFIG_BPF_JIT_DEFAULT_ON=y
+CONFIG_BRCMFMAC=m
+CONFIG_BRCMFMAC_PCIE=y
+CONFIG_BRCMFMAC_PROTO_BCDC=y
+CONFIG_BRCMFMAC_PROTO_MSGBUF=y
+CONFIG_BRCMFMAC_SDIO=y
+CONFIG_BRCMFMAC_USB=y
+CONFIG_BRCMSMAC_LEDS=y
+CONFIG_BRCMSMAC=m
+CONFIG_BRCM_TRACING=y
+CONFIG_BRCMUTIL=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_BSD_DISKLABEL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BTREE=y
+CONFIG_BTT=y
+CONFIG_BUG=y
+CONFIG_BUILD_SALT="1fdd9952ce8bea62b1aa13a9cc79a1af2635f2ec"
+CONFIG_CADENCE_WATCHDOG=m
+CONFIG_CAIF=m
+CONFIG_CAIF_NETDEV=m
+CONFIG_CAIF_USB=m
+CONFIG_CALL_DEPTH_TRACKING=y
+CONFIG_CALL_PADDING=y
+CONFIG_CALL_THUNKS=y
+CONFIG_CAN_8DEV_USB=m
+CONFIG_CAN_BCM=m
+CONFIG_CAN_CALC_BITTIMING=y
+CONFIG_CAN_CAN327=m
+CONFIG_CAN_CC770_ISA=m
+CONFIG_CAN_CC770=m
+CONFIG_CAN_CC770_PLATFORM=m
+CONFIG_CAN_C_CAN=m
+CONFIG_CAN_C_CAN_PCI=m
+CONFIG_CAN_C_CAN_PLATFORM=m
+CONFIG_CAN_CTUCANFD=m
+CONFIG_CAN_CTUCANFD_PCI=m
+CONFIG_CAN_DEV=m
+CONFIG_CAN_EMS_PCI=m
+CONFIG_CAN_EMS_PCMCIA=m
+CONFIG_CAN_EMS_USB=m
+CONFIG_CAN_ESD_402_PCI=m
+CONFIG_CAN_ESD_USB=m
+CONFIG_CAN_ETAS_ES58X=m
+CONFIG_CAN_F81601=m
+CONFIG_CAN_F81604=m
+CONFIG_CAN_GS_USB=m
+CONFIG_CAN_GW=m
+CONFIG_CAN_HI311X=m
+CONFIG_CAN_IFI_CANFD=m
+CONFIG_CAN_ISOTP=m
+CONFIG_CAN_J1939=m
+CONFIG_CAN_JANZ_ICAN3=m
+CONFIG_CAN_KVASER_PCIEFD=m
+CONFIG_CAN_KVASER_PCI=m
+CONFIG_CAN_KVASER_USB=m
+CONFIG_CAN=m
+CONFIG_CAN_M_CAN=m
+CONFIG_CAN_M_CAN_PCI=m
+CONFIG_CAN_M_CAN_PLATFORM=m
+CONFIG_CAN_M_CAN_TCAN4X5X=m
+CONFIG_CAN_MCBA_USB=m
+CONFIG_CAN_MCP251XFD=m
+CONFIG_CAN_MCP251X=m
+CONFIG_CAN_NCT6694=m
+CONFIG_CAN_NETLINK=y
+CONFIG_CAN_PEAK_PCIEC=y
+CONFIG_CAN_PEAK_PCIEFD=m
+CONFIG_CAN_PEAK_PCI=m
+CONFIG_CAN_PEAK_PCMCIA=m
+CONFIG_CAN_PEAK_USB=m
+CONFIG_CAN_PLX_PCI=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_RX_OFFLOAD=y
+CONFIG_CAN_SJA1000_ISA=m
+CONFIG_CAN_SJA1000=m
+CONFIG_CAN_SJA1000_PLATFORM=m
+CONFIG_CAN_SLCAN=m
+CONFIG_CAN_SOFTING_CS=m
+CONFIG_CAN_SOFTING=m
+CONFIG_CAN_UCAN=m
+CONFIG_CAN_VCAN=m
+CONFIG_CAN_VXCAN=m
+CONFIG_CAPI_TRACE=y
+CONFIG_CARDBUS=y
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170=m
+CONFIG_CARL9170_WPC=y
+CONFIG_CB710_CORE=m
+CONFIG_CB710_DEBUG_ASSUMPTIONS=y
+CONFIG_CC10001_ADC=m
+CONFIG_CC_CAN_LINK_STATIC=y
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
+CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
+CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
+CONFIG_CC_HAS_ENTRY_PADDING=y
+CONFIG_CC_HAS_IBT=y
+CONFIG_CC_HAS_INT128=y
+CONFIG_CC_HAS_KASAN_SW_TAGS=y
+CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
+CONFIG_CC_HAS_RANDSTRUCT=y
+CONFIG_CC_HAS_RETURN_THUNK=y
+CONFIG_CC_HAS_SANE_STACKPROTECTOR=y
+CONFIG_CC_HAS_SLS=y
+CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough"
+CONFIG_CC_IS_CLANG=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+CONFIG_CCS811=m
+CONFIG_CC_VERSION_TEXT="OpenMandriva 16.0.6-3 clang version 16.0.6 (/builddir/build/BUILD/llvm-project-16.0.6.src/clang 2d21ec58bba683586362941f17e8179860b49206)"
+CONFIG_CDNS_I3C_MASTER=m
+CONFIG_CDROM=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_WCACHE=y
+CONFIG_CEC_CH7322=m
+CONFIG_CEC_CORE=m
+CONFIG_CEC_CROS_EC=m
+CONFIG_CEC_GPIO=m
+CONFIG_CEC_NOTIFIER=y
+CONFIG_CEC_NXP_TDA9950=m
+CONFIG_CEC_PIN=y
+CONFIG_CEC_SECO=m
+CONFIG_CEC_SECO_RC=y
+CONFIG_CEPH_LIB=m
+CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
+CONFIG_CFAG12864B=m
+CONFIG_CFAG12864B_RATE=20
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_CFG80211=m
+CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
+CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
+CONFIG_CFG80211_WEXT_EXPORT=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CGROUP_MISC=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CHARGER_88PM860X=m
+CONFIG_CHARGER_ADP5061=m
+CONFIG_CHARGER_AXP20X=m
+CONFIG_CHARGER_BD99954=m
+CONFIG_CHARGER_BQ2415X=m
+CONFIG_CHARGER_BQ24190=m
+CONFIG_CHARGER_BQ24257=m
+CONFIG_CHARGER_BQ24735=m
+CONFIG_CHARGER_BQ2515X=m
+CONFIG_CHARGER_BQ256XX=m
+CONFIG_CHARGER_BQ25890=m
+CONFIG_CHARGER_BQ25980=m
+CONFIG_CHARGER_CROS_CONTROL=m
+CONFIG_CHARGER_CROS_PCHG=m
+CONFIG_CHARGER_CROS_USBPD=m
+CONFIG_CHARGER_DA9150=m
+CONFIG_CHARGER_GPIO=m
+CONFIG_CHARGER_ISP1704=m
+CONFIG_CHARGER_LP8727=m
+CONFIG_CHARGER_LP8788=m
+CONFIG_CHARGER_LT3651=m
+CONFIG_CHARGER_LTC4162L=m
+CONFIG_CHARGER_MANAGER=y
+CONFIG_CHARGER_MAX14577=m
+CONFIG_CHARGER_MAX77693=m
+CONFIG_CHARGER_MAX77705=m
+CONFIG_CHARGER_MAX77976=m
+CONFIG_CHARGER_MAX8903=m
+CONFIG_CHARGER_MAX8997=m
+CONFIG_CHARGER_MAX8998=m
+CONFIG_CHARGER_MP2629=m
+CONFIG_CHARGER_MT6360=m
+CONFIG_CHARGER_MT6370=m
+CONFIG_CHARGER_PCF50633=m
+CONFIG_CHARGER_RT5033=m
+CONFIG_CHARGER_RT9455=m
+CONFIG_CHARGER_RT9467=m
+CONFIG_CHARGER_RT9471=m
+CONFIG_CHARGER_SBS=m
+CONFIG_CHARGER_SMB347=m
+CONFIG_CHARGER_SURFACE=m
+CONFIG_CHARGER_TPS65090=m
+CONFIG_CHARGER_TWL4030=m
+CONFIG_CHARGER_WILCO=m
+CONFIG_CHARLCD_BL_FLASH=y
+CONFIG_CHARLCD=m
+CONFIG_CHECK_SIGNATURE=y
+CONFIG_CHR_DEV_SCH=m
+CONFIG_CHR_DEV_SG=m
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHROMEOS_ACPI=m
+CONFIG_CHROMEOS_LAPTOP=m
+CONFIG_CHROMEOS_PRIVACY_SCREEN=m
+CONFIG_CHROMEOS_PSTORE=m
+CONFIG_CHROMEOS_TBMC=m
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CICADA_PHY=m
+CONFIG_CIO2_BRIDGE=y
+CONFIG_CLANG_VERSION=160006
+CONFIG_CLKBLD_I8253=y
+CONFIG_CLKEVT_I8253=y
+CONFIG_CLK_TWL6040=m
+CONFIG_CLK_TWL=m
+CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
+CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+CONFIG_CM32181=m
+CONFIG_CM3232=m
+CONFIG_CM3323=m
+CONFIG_CM3605=m
+CONFIG_CM36651=m
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+CONFIG_CMA_SIZE_MBYTES=0
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+CONFIG_CMA_SYSFS=y
+CONFIG_CMA=y
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_COMEDI_8255=m
+CONFIG_COMEDI_8255_PCI=m
+CONFIG_COMEDI_8255_SA=m
+CONFIG_COMEDI_ADDI_APCI_1032=m
+CONFIG_COMEDI_ADDI_APCI_1500=m
+CONFIG_COMEDI_ADDI_APCI_1516=m
+CONFIG_COMEDI_ADDI_APCI_1564=m
+CONFIG_COMEDI_ADDI_APCI_16XX=m
+CONFIG_COMEDI_ADDI_APCI_2032=m
+CONFIG_COMEDI_ADDI_APCI_2200=m
+CONFIG_COMEDI_ADDI_APCI_3120=m
+CONFIG_COMEDI_ADDI_APCI_3501=m
+CONFIG_COMEDI_ADDI_APCI_3XXX=m
+CONFIG_COMEDI_ADDI_WATCHDOG=m
+CONFIG_COMEDI_ADL_PCI6208=m
+CONFIG_COMEDI_ADL_PCI7250=m
+CONFIG_COMEDI_ADL_PCI7X3X=m
+CONFIG_COMEDI_ADL_PCI8164=m
+CONFIG_COMEDI_ADL_PCI9111=m
+CONFIG_COMEDI_ADL_PCI9118=m
+CONFIG_COMEDI_ADQ12B=m
+CONFIG_COMEDI_ADV_PCI1710=m
+CONFIG_COMEDI_ADV_PCI1720=m
+CONFIG_COMEDI_ADV_PCI1723=m
+CONFIG_COMEDI_ADV_PCI1724=m
+CONFIG_COMEDI_ADV_PCI1760=m
+CONFIG_COMEDI_ADV_PCI_DIO=m
+CONFIG_COMEDI_AIO_AIO12_8=m
+CONFIG_COMEDI_AIO_IIRO_16=m
+CONFIG_COMEDI_AMPLC_DIO200_ISA=m
+CONFIG_COMEDI_AMPLC_DIO200_PCI=m
+CONFIG_COMEDI_AMPLC_PC236_ISA=m
+CONFIG_COMEDI_AMPLC_PC236=m
+CONFIG_COMEDI_AMPLC_PC236_PCI=m
+CONFIG_COMEDI_AMPLC_PC263_ISA=m
+CONFIG_COMEDI_AMPLC_PC263_PCI=m
+CONFIG_COMEDI_AMPLC_PCI224=m
+CONFIG_COMEDI_AMPLC_PCI230=m
+CONFIG_COMEDI_BOND=m
+CONFIG_COMEDI_C6XDIGIO=m
+CONFIG_COMEDI_CB_DAS16_CS=m
+CONFIG_COMEDI_CB_PCIDAS64=m
+CONFIG_COMEDI_CB_PCIDAS=m
+CONFIG_COMEDI_CB_PCIDDA=m
+CONFIG_COMEDI_CB_PCIMDAS=m
+CONFIG_COMEDI_CB_PCIMDDA=m
+CONFIG_COMEDI_CONTEC_PCI_DIO=m
+CONFIG_COMEDI_DAC02=m
+CONFIG_COMEDI_DAQBOARD2000=m
+CONFIG_COMEDI_DAS08_CS=m
+CONFIG_COMEDI_DAS08_ISA=m
+CONFIG_COMEDI_DAS08_PCI=m
+CONFIG_COMEDI_DAS16=m
+CONFIG_COMEDI_DAS16M1=m
+CONFIG_COMEDI_DAS1800=m
+CONFIG_COMEDI_DAS6402=m
+CONFIG_COMEDI_DAS800=m
+CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
+CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
+CONFIG_COMEDI_DMM32AT=m
+CONFIG_COMEDI_DT2801=m
+CONFIG_COMEDI_DT2811=m
+CONFIG_COMEDI_DT2814=m
+CONFIG_COMEDI_DT2815=m
+CONFIG_COMEDI_DT2817=m
+CONFIG_COMEDI_DT282X=m
+CONFIG_COMEDI_DT3000=m
+CONFIG_COMEDI_DT9812=m
+CONFIG_COMEDI_DYNA_PCI10XX=m
+CONFIG_COMEDI_FL512=m
+CONFIG_COMEDI_GSC_HPDI=m
+CONFIG_COMEDI_ICP_MULTI=m
+CONFIG_COMEDI_II_PCI20KC=m
+CONFIG_COMEDI_ISA_DRIVERS=y
+CONFIG_COMEDI_JR3_PCI=m
+CONFIG_COMEDI_KCOMEDILIB=m
+CONFIG_COMEDI_KE_COUNTER=m
+CONFIG_COMEDI=m
+CONFIG_COMEDI_ME4000=m
+CONFIG_COMEDI_ME_DAQ=m
+CONFIG_COMEDI_MF6X4=m
+CONFIG_COMEDI_MISC_DRIVERS=y
+CONFIG_COMEDI_MITE=m
+CONFIG_COMEDI_MPC624=m
+CONFIG_COMEDI_MULTIQ3=m
+CONFIG_COMEDI_NI_6527=m
+CONFIG_COMEDI_NI_65XX=m
+CONFIG_COMEDI_NI_660X=m
+CONFIG_COMEDI_NI_670X=m
+CONFIG_COMEDI_NI_AT_A2150=m
+CONFIG_COMEDI_NI_AT_AO=m
+CONFIG_COMEDI_NI_ATMIO16D=m
+CONFIG_COMEDI_NI_ATMIO=m
+CONFIG_COMEDI_NI_DAQ_700_CS=m
+CONFIG_COMEDI_NI_DAQ_DIO24_CS=m
+CONFIG_COMEDI_NI_LABPC_CS=m
+CONFIG_COMEDI_NI_LABPC_ISA=m
+CONFIG_COMEDI_NI_LABPC_PCI=m
+CONFIG_COMEDI_NI_MIO_CS=m
+CONFIG_COMEDI_NI_PCIDIO=m
+CONFIG_COMEDI_NI_PCIMIO=m
+CONFIG_COMEDI_NI_ROUTING=m
+CONFIG_COMEDI_NI_TIOCMD=m
+CONFIG_COMEDI_NI_TIO=m
+CONFIG_COMEDI_NI_USB6501=m
+CONFIG_COMEDI_PARPORT=m
+CONFIG_COMEDI_PCI_DRIVERS=m
+CONFIG_COMEDI_PCL711=m
+CONFIG_COMEDI_PCL724=m
+CONFIG_COMEDI_PCL726=m
+CONFIG_COMEDI_PCL730=m
+CONFIG_COMEDI_PCL812=m
+CONFIG_COMEDI_PCL816=m
+CONFIG_COMEDI_PCL818=m
+CONFIG_COMEDI_PCM3724=m
+CONFIG_COMEDI_PCMAD=m
+CONFIG_COMEDI_PCMCIA_DRIVERS=m
+CONFIG_COMEDI_PCMDA12=m
+CONFIG_COMEDI_PCMMIO=m
+CONFIG_COMEDI_PCMUIO=m
+CONFIG_COMEDI_QUATECH_DAQP_CS=m
+CONFIG_COMEDI_RTD520=m
+CONFIG_COMEDI_RTI800=m
+CONFIG_COMEDI_RTI802=m
+CONFIG_COMEDI_S526=m
+CONFIG_COMEDI_S626=m
+CONFIG_COMEDI_TEST=m
+CONFIG_COMEDI_TESTS_EXAMPLE=m
+CONFIG_COMEDI_TESTS=m
+CONFIG_COMEDI_TESTS_NI_ROUTES=m
+CONFIG_COMEDI_USB_DRIVERS=m
+CONFIG_COMEDI_USBDUXFAST=m
+CONFIG_COMEDI_USBDUX=m
+CONFIG_COMEDI_USBDUXSIGMA=m
+CONFIG_COMEDI_VMK80XX=m
+CONFIG_COMMON_CLK_CDCE706=m
+CONFIG_COMMON_CLK_CS2000_CP=m
+CONFIG_COMMON_CLK_MAX9485=m
+CONFIG_COMMON_CLK_PALMAS=m
+CONFIG_COMMON_CLK_PWM=m
+CONFIG_COMMON_CLK_SI5341=m
+CONFIG_COMMON_CLK_SI5351=m
+CONFIG_COMMON_CLK_SI544=m
+CONFIG_COMMON_CLK_TPS68470=m
+CONFIG_COMMON_CLK_WM831X=m
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAL_LAPTOP=m
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_COMPAT_32=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+CONFIG_COMPAT=y
+CONFIG_CONNECTOR=m
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTEXT_TRACKING_USER=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CORDIC=m
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CORTINA_PHY=m
+CONFIG_COUNTER=m
+CONFIG_CPU5_WDT=m
+CONFIG_CPUFREQ_ARCH_CUR_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_IBPB_ENTRY=y
+CONFIG_CPU_IBRS_ENTRY=y
+CONFIG_CPU_IDLE_GOV_HALTPOLL=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPUMASK_OFFSTACK=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_SRSO=y
+CONFIG_CPU_SUP_AMD=y
+CONFIG_CPU_SUP_CENTAUR=y
+CONFIG_CPU_SUP_HYGON=y
+CONFIG_CPU_SUP_INTEL=y
+CONFIG_CPU_SUP_ZHAOXIN=y
+CONFIG_CPU_UNRET_ENTRY=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_HOTPLUG=y
+CONFIG_CRASH_MAX_MEMORY_RANGES=8192
+CONFIG_CRC16=y
+CONFIG_CRC4=m
+CONFIG_CRC64=m
+CONFIG_CRC64_ROCKSOFT=m
+CONFIG_CRC7=m
+CONFIG_CRC8=m
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CROS_EC_CHARDEV=m
+CONFIG_CROS_EC_DEBUGFS=m
+CONFIG_CROS_EC_I2C=m
+CONFIG_CROS_EC_ISHTP=m
+CONFIG_CROS_EC_LIGHTBAR=m
+CONFIG_CROS_EC_LPC=m
+CONFIG_CROS_EC=m
+CONFIG_CROS_EC_MKBP_PROXIMITY=m
+CONFIG_CROS_EC_PROTO=y
+CONFIG_CROS_EC_SENSORHUB=m
+CONFIG_CROS_EC_SPI=m
+CONFIG_CROS_EC_SYSFS=m
+CONFIG_CROS_EC_TYPEC=m
+CONFIG_CROS_EC_UART=m
+CONFIG_CROS_EC_WATCHDOG=m
+CONFIG_CROS_HPS_I2C=m
+CONFIG_CROS_KBD_LED_BACKLIGHT=m
+CONFIG_CROS_TYPEC_SWITCH=m
+CONFIG_CROS_USBPD_LOGGER=m
+CONFIG_CROS_USBPD_NOTIFY=m
+CONFIG_CRYPTO_842=y
+CONFIG_CRYPTO_ADIANTUM=m
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEGIS128_AESNI_SSE2=m
+CONFIG_CRYPTO_AEGIS128=m
+CONFIG_CRYPTO_AES_NI_INTEL=m
+CONFIG_CRYPTO_AES_TI=m
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
+CONFIG_CRYPTO_ARIA_AESNI_AVX2_X86_64=m
+CONFIG_CRYPTO_ARIA_AESNI_AVX_X86_64=m
+CONFIG_CRYPTO_ARIA_GFNI_AVX512_X86_64=m
+CONFIG_CRYPTO_ARIA=m
+CONFIG_CRYPTO_BLAKE2B=m
+CONFIG_CRYPTO_BLAKE2S_X86=y
+CONFIG_CRYPTO_BLOWFISH_COMMON=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_BLOWFISH_X86_64=m
+CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=m
+CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAMELLIA_X86_64=m
+CONFIG_CRYPTO_CAST5_AVX_X86_64=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6_AVX_X86_64=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_CAST_COMMON=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_CFB=m
+CONFIG_CRYPTO_CHACHA20=m
+CONFIG_CRYPTO_CHACHA20POLY1305=m
+CONFIG_CRYPTO_CHACHA20_X86_64=m
+CONFIG_CRYPTO_CMAC=m
+CONFIG_CRYPTO_CRC32C_INTEL=m
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32=m
+CONFIG_CRYPTO_CRC32_PCLMUL=m
+CONFIG_CRYPTO_CRC64_ROCKSOFT=m
+CONFIG_CRYPTO_CRCT10DIF_PCLMUL=m
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_CURVE25519=m
+CONFIG_CRYPTO_CURVE25519_X86=m
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES3_EDE_X86_64=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
+CONFIG_CRYPTO_DEV_ATMEL_ECC=m
+CONFIG_CRYPTO_DEV_ATMEL_I2C=m
+CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
+CONFIG_CRYPTO_DEV_CCP_CRYPTO=m
+CONFIG_CRYPTO_DEV_CCP_DD=m
+CONFIG_CRYPTO_DEV_CCP=y
+CONFIG_CRYPTO_DEV_CHELSIO=m
+CONFIG_CRYPTO_DEV_IAA_CRYPTO=m
+CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m
+CONFIG_CRYPTO_DEV_NITROX=m
+CONFIG_CRYPTO_DEV_PADLOCK_AES=m
+CONFIG_CRYPTO_DEV_PADLOCK=m
+CONFIG_CRYPTO_DEV_PADLOCK_SHA=m
+CONFIG_CRYPTO_DEV_QAT_420XX=m
+CONFIG_CRYPTO_DEV_QAT_4XXX=m
+CONFIG_CRYPTO_DEV_QAT_6XXX=m
+CONFIG_CRYPTO_DEV_QAT_C3XXX=m
+CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
+CONFIG_CRYPTO_DEV_QAT_C62X=m
+CONFIG_CRYPTO_DEV_QAT_C62XVF=m
+CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
+CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
+CONFIG_CRYPTO_DEV_QAT=m
+CONFIG_CRYPTO_DEV_SAFEXCEL=m
+CONFIG_CRYPTO_DEV_SP_CCP=y
+CONFIG_CRYPTO_DEV_SP_PSP=y
+CONFIG_CRYPTO_DEV_VIRTIO=m
+CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
+CONFIG_CRYPTO_DH=y
+CONFIG_CRYPTO_DRBG_CTR=y
+CONFIG_CRYPTO_DRBG_HASH=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECC=m
+CONFIG_CRYPTO_ECDH=m
+CONFIG_CRYPTO_ECDSA=m
+CONFIG_CRYPTO_ECHAINIV=m
+CONFIG_CRYPTO_ECRDSA=m
+CONFIG_CRYPTO_ENGINE=m
+CONFIG_CRYPTO_ESSIV=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_GENIV=m
+CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HCTR2=m
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_KDF800108_CTR=y
+CONFIG_CRYPTO_KEYWRAP=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_KPP=y
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_GF128MUL=m
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_LZ4HC=y
+CONFIG_CRYPTO_LZ4=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_NHPOLY1305_AVX2=m
+CONFIG_CRYPTO_NHPOLY1305=m
+CONFIG_CRYPTO_NHPOLY1305_SSE2=m
+CONFIG_CRYPTO_NULL2=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_OFB=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_PCRYPT=m
+CONFIG_CRYPTO_POLY1305=m
+CONFIG_CRYPTO_POLY1305_X86_64=m
+CONFIG_CRYPTO_POLYVAL_CLMUL_NI=m
+CONFIG_CRYPTO_POLYVAL=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m
+CONFIG_CRYPTO_SERPENT_AVX_X86_64=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_SERPENT_SSE2_X86_64=m
+CONFIG_CRYPTO_SHA1_SSSE3=m
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256_SSSE3=m
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SHA512_SSSE3=m
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SIG2=y
+CONFIG_CRYPTO_SIMD=m
+CONFIG_CRYPTO_SM2=m
+CONFIG_CRYPTO_SM3_AVX_X86_64=m
+CONFIG_CRYPTO_SM3_GENERIC=m
+CONFIG_CRYPTO_SM3=m
+CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64=m
+CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64=m
+CONFIG_CRYPTO_SM4_GENERIC=m
+CONFIG_CRYPTO_SM4=m
+CONFIG_CRYPTO_STREEBOG=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=m
+CONFIG_CRYPTO_TWOFISH_X86_64=m
+CONFIG_CRYPTO_USER_API_AEAD=m
+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_RNG=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_USER_API=y
+CONFIG_CRYPTO_USER=m
+CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_XCTR=m
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_XXHASH=m
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CW1200=m
+CONFIG_CW1200_WLAN_SDIO=m
+CONFIG_CW1200_WLAN_SPI=m
+CONFIG_CXD2880_SPI_DRV=m
+CONFIG_CXL_ACPI=m
+CONFIG_CXL_BUS=m
+CONFIG_CXL_FEATURES=y
+CONFIG_CXL_MEM=m
+CONFIG_CXL_MEM_RAW_COMMANDS=y
+CONFIG_CXL_PCI=m
+CONFIG_CXL_PMEM=m
+CONFIG_CXL_PMU=m
+CONFIG_CXL_PORT=m
+CONFIG_CXL_REGION=y
+CONFIG_CXL_SUSPEND=y
+CONFIG_CYPRESS_FIRMWARE=m
+CONFIG_DA280=m
+CONFIG_DA311=m
+CONFIG_DA9052_WATCHDOG=m
+CONFIG_DA9055_WATCHDOG=m
+CONFIG_DA9062_WATCHDOG=m
+CONFIG_DA9063_WATCHDOG=m
+CONFIG_DA9150_GPADC=m
+CONFIG_DASHARO_ACPI=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_DAX=y
+CONFIG_DCA=m
+CONFIG_DCDBAS=m
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_WX=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DEFAULT_HOSTNAME="omv"
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DELL_LAPTOP=m
+CONFIG_DELL_PC=m
+CONFIG_DELL_RBTN=m
+CONFIG_DELL_RBU=m
+CONFIG_DELL_SMBIOS=m
+CONFIG_DELL_SMBIOS_SMM=y
+CONFIG_DELL_SMBIOS_WMI=y
+CONFIG_DELL_SMO8800=m
+CONFIG_DELL_UART_BACKLIGHT=m
+CONFIG_DELL_WMI_AIO=m
+CONFIG_DELL_WMI_DDV=m
+CONFIG_DELL_WMI_DESCRIPTOR=m
+CONFIG_DELL_WMI_LED=m
+CONFIG_DELL_WMI=m
+CONFIG_DELL_WMI_PRIVACY=y
+CONFIG_DELL_WMI_SYSMAN=m
+CONFIG_DEV_DAX_CXL=m
+CONFIG_DEV_DAX_HMEM_DEVICES=y
+CONFIG_DEV_DAX_HMEM=m
+CONFIG_DEV_DAX_KMEM=m
+CONFIG_DEV_DAX=m
+CONFIG_DEVFREQ_GOV_PASSIVE=m
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_DEVTMPFS_SAFE=y
+CONFIG_DHT11=m
+CONFIG_DIMLIB=y
+CONFIG_DLHL60D=m
+CONFIG_DLN2_ADC=m
+CONFIG_DMA_ACPI=y
+CONFIG_DMABUF_SELFTESTS=m
+CONFIG_DMA_CMA=y
+CONFIG_DMA_COHERENT_POOL=y
 CONFIG_DMADEVICES=y
-# CONFIG_DMADEVICES_DEBUG is not set
-
-#
-# DMA Devices
-#
+CONFIG_DMA_ENGINE_RAID=y
 CONFIG_DMA_ENGINE=y
+CONFIG_DMA_NUMA_CMA=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_PERNUMA_CMA=y
+CONFIG_DMARD06=m
+CONFIG_DMARD09=m
+CONFIG_DMARD10=m
+CONFIG_DMAR_TABLE=y
 CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DMA_ACPI=y
-CONFIG_ALTERA_MSGDMA=m
-CONFIG_INTEL_IDMA64=m
-CONFIG_INTEL_IDXD_BUS=m
-CONFIG_INTEL_IDXD=m
-# CONFIG_INTEL_IDXD_COMPAT is not set
-CONFIG_INTEL_IDXD_SVM=y
-CONFIG_INTEL_IDXD_PERFMON=y
-CONFIG_INTEL_IOATDMA=m
-CONFIG_PLX_DMA=m
-CONFIG_AMD_PTDMA=m
-CONFIG_QCOM_HIDMA_MGMT=m
-CONFIG_QCOM_HIDMA=m
+CONFIG_DM_CACHE=m
+CONFIG_DM_CACHE_SMQ=m
+CONFIG_DM_CLONE=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_DELAY=m
+CONFIG_DM_DUST=m
+CONFIG_DM_ERA=m
+CONFIG_DM_FLAKEY=m
+CONFIG_DMIID=y
+CONFIG_DM_INTEGRITY=m
+CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
+CONFIG_DMI_SYSFS=m
+CONFIG_DMI=y
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_LOG_WRITES=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_MULTIPATH_HST=m
+CONFIG_DM_MULTIPATH_IOA=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_PCACHE=m
+CONFIG_DM_RAID=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_SWITCH=m
+CONFIG_DM_UEVENT=y
+CONFIG_DM_UNSTRIPED=m
+CONFIG_DM_VERITY=m
+CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
+CONFIG_DM_WRITECACHE=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_ZONED=m
+CONFIG_DP83640_PHY=m
+CONFIG_DP83822_PHY=m
+CONFIG_DP83848_PHY=m
+CONFIG_DP83867_PHY=m
+CONFIG_DP83869_PHY=m
+CONFIG_DP83TC811_PHY=m
+CONFIG_DP83TD510_PHY=m
+CONFIG_DP83TG720_PHY=m
+CONFIG_DPOT_DAC=m
+CONFIG_DPS310=m
+CONFIG_DPTF_PCH_FIVR=m
+CONFIG_DPTF_POWER=m
+CONFIG_DRM_ACCEL_AMDXDNA=m
+CONFIG_DRM_ACCEL_HABANALABS=m
+CONFIG_DRM_ACCEL_IVPU=m
+CONFIG_DRM_ACCEL_QAIC=m
+CONFIG_DRM_ACCEL=y
+CONFIG_DRM_AMD_ACP=y
+CONFIG_DRM_AMD_DC_FP=y
+CONFIG_DRM_AMD_DC_SI=y
+CONFIG_DRM_AMD_DC=y
+CONFIG_DRM_AMDGPU_CIK=y
+CONFIG_DRM_AMDGPU=m
+CONFIG_DRM_AMDGPU_SI=y
+CONFIG_DRM_AMDGPU_USERPTR=y
+CONFIG_DRM_AMD_ISP=y
+CONFIG_DRM_AMD_SECURE_DISPLAY=y
+CONFIG_DRM_ANALOGIX_ANX78XX=m
+CONFIG_DRM_ANALOGIX_DP=m
+CONFIG_DRM_APPLETBDRM=m
+CONFIG_DRM_AST=m
+CONFIG_DRM_BOCHS=m
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_BUDDY=m
+CONFIG_DRM_CIRRUS_QEMU=m
+CONFIG_DRM_CLIENT_DEFAULT_FBDEV=y
+CONFIG_DRM_DISPLAY_DP_AUX_CEC=y
+CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV=y
+CONFIG_DRM_DISPLAY_DP_HELPER=y
+CONFIG_DRM_DISPLAY_HDCP_HELPER=y
+CONFIG_DRM_DISPLAY_HDMI_HELPER=y
+CONFIG_DRM_DISPLAY_HELPER=m
+CONFIG_DRM_DP_AUX_CHARDEV=y
+CONFIG_DRM_ETNAVIV=m
+CONFIG_DRM_ETNAVIV_THERMAL=y
+CONFIG_DRM_EVDI=m
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_GEM_DMA_HELPER=m
+CONFIG_DRM_GEM_SHMEM_HELPER=m
+CONFIG_DRM_GM12U320=m
+CONFIG_DRM_GMA500=m
+CONFIG_DRM_GUD=m
+CONFIG_DRM_HISI_HIBMC=m
+CONFIG_DRM_HYPERV=m
+CONFIG_DRM_I2C_CH7006=m
+CONFIG_DRM_I2C_NXP_TDA9950=m
+CONFIG_DRM_I2C_NXP_TDA998X=m
+CONFIG_DRM_I2C_SIL164=m
+CONFIG_DRM_I915_CAPTURE_ERROR=y
+CONFIG_DRM_I915_COMPRESS_ERROR=y
+CONFIG_DRM_I915_DP_TUNNEL=y
+CONFIG_DRM_I915_FENCE_TIMEOUT=10000
+CONFIG_DRM_I915_FORCE_PROBE=""
+CONFIG_DRM_I915_GVT_KVMGT=m
+CONFIG_DRM_I915_GVT=y
+CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
+CONFIG_DRM_I915=m
+CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
+CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
+CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE=7500
+CONFIG_DRM_I915_PXP=y
+CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
+CONFIG_DRM_I915_STOP_TIMEOUT=100
+CONFIG_DRM_I915_TIMESLICE_DURATION=1
+CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
+CONFIG_DRM_I915_USERPTR=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_LEGACY=y
+CONFIG_DRM_LOONGSON=m
+CONFIG_DRM_MGAG200=m
+CONFIG_DRM_MIPI_DBI=m
+CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_NOUVEAU_BACKLIGHT=y
+CONFIG_DRM_NOUVEAU_CH7006=m
+CONFIG_DRM_NOUVEAU_GSP_DEFAULT=y
+CONFIG_DRM_NOUVEAU=m
+CONFIG_DRM_NOUVEAU_SIL164=m
+CONFIG_DRM_PANEL_AUO_A030JTN01=m
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ILITEK_ILI9341=m
+CONFIG_DRM_PANEL_MIPI_DBI=m
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m
+CONFIG_DRM_PANEL_ORISETECH_OTA5601A=m
+CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
+CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANIC_BACKGROUND_COLOR=0x000000
+CONFIG_DRM_PANIC_FOREGROUND_COLOR=0xa0a0a0
+CONFIG_DRM_PANIC_SCREEN="user"
+CONFIG_DRM_PANIC=y
+CONFIG_DRM_PIXPAPER=m
+CONFIG_DRM_POWERVR=m
+CONFIG_DRM_PRIVACY_SCREEN=y
+CONFIG_DRM_QXL=m
+CONFIG_DRM_RADEON=m
+CONFIG_DRM_RADEON_USERPTR=y
+CONFIG_DRM_SCHED=m
+CONFIG_DRM_SIMPLEDRM=y
+CONFIG_DRM_SSD130X_I2C=m
+CONFIG_DRM_SSD130X=m
+CONFIG_DRM_SSD130X_SPI=m
+CONFIG_DRM_SUBALLOC_HELPER=m
+CONFIG_DRM_TTM_HELPER=m
+CONFIG_DRM_TTM=m
+CONFIG_DRM_UDL=m
+CONFIG_DRM_VBOXVIDEO=m
+CONFIG_DRM_VGEM=m
+CONFIG_DRM_VIRTIO_GPU_KMS=y
+CONFIG_DRM_VIRTIO_GPU=m
+CONFIG_DRM_VKMS=m
+CONFIG_DRM_VMWGFX=m
+CONFIG_DRM_VMWGFX_MKSSTATS=y
+CONFIG_DRM_VRAM_HELPER=m
+CONFIG_DRM_XE_DEVMEM_MIRROR=y
+CONFIG_DRM_XE_DISPLAY=y
+CONFIG_DRM_XE_DP_TUNNEL=y
+CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT=y
+CONFIG_DRM_XE_FORCE_PROBE=""
+CONFIG_DRM_XE_JOB_TIMEOUT_MAX=10000
+CONFIG_DRM_XE_JOB_TIMEOUT_MIN=1
+CONFIG_DRM_XE=m
+CONFIG_DRM_XE_PREEMPT_TIMEOUT=640000
+CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX=10000000
+CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN=1
+CONFIG_DRM_XE_TIMESLICE_MAX=10000000
+CONFIG_DRM_XE_TIMESLICE_MIN=1
+CONFIG_DRM=y
+CONFIG_DS1682=m
+CONFIG_DS1803=m
+CONFIG_DS4424=m
+CONFIG_DUMMY_CONSOLE_ROWS=30
+CONFIG_DUMMY=m
+CONFIG_DVB_A8293=m
+CONFIG_DVB_AF9013=m
+CONFIG_DVB_AF9033=m
+CONFIG_DVB_AS102_FE=m
+CONFIG_DVB_AS102=m
+CONFIG_DVB_ASCOT2E=m
+CONFIG_DVB_ATBM8830=m
+CONFIG_DVB_AU8522_DTV=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_AU8522_V4L=m
+CONFIG_DVB_AV7110_IR=y
+CONFIG_DVB_AV7110=m
+CONFIG_DVB_AV7110_OSD=y
+CONFIG_DVB_B2C2_FLEXCOP=m
+CONFIG_DVB_B2C2_FLEXCOP_PCI=m
+CONFIG_DVB_B2C2_FLEXCOP_USB=m
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_BT8XX=m
+CONFIG_DVB_BUDGET_AV=m
+CONFIG_DVB_BUDGET_CI=m
+CONFIG_DVB_BUDGET_CORE=m
+CONFIG_DVB_BUDGET=m
+CONFIG_DVB_BUDGET_PATCH=m
+CONFIG_DVB_CORE=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24116=m
+CONFIG_DVB_CX24117=m
+CONFIG_DVB_CX24120=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_CXD2099=m
+CONFIG_DVB_CXD2820R=m
+CONFIG_DVB_CXD2841ER=m
+CONFIG_DVB_DDBRIDGE=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_DIB8000=m
+CONFIG_DVB_DM1105=m
+CONFIG_DVB_DRX39XYJ=m
+CONFIG_DVB_DRXD=m
+CONFIG_DVB_DRXK=m
+CONFIG_DVB_DS3000=m
+CONFIG_DVB_DYNAMIC_MINORS=y
+CONFIG_DVB_EC100=m
+CONFIG_DVB_FIREDTV_INPUT=y
+CONFIG_DVB_FIREDTV=m
+CONFIG_DVB_GP8PSK_FE=m
+CONFIG_DVB_HELENE=m
+CONFIG_DVB_HOPPER=m
+CONFIG_DVB_HORUS3A=m
+CONFIG_DVB_ISL6405=m
+CONFIG_DVB_ISL6421=m
+CONFIG_DVB_ISL6422=m
+CONFIG_DVB_ISL6423=m
+CONFIG_DVB_IX2505V=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_LG2160=m
+CONFIG_DVB_LGDT3305=m
+CONFIG_DVB_LGDT3306A=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_LGS8GXX=m
+CONFIG_DVB_LNBH25=m
+CONFIG_DVB_LNBP21=m
+CONFIG_DVB_LNBP22=m
+CONFIG_DVB_M88DS3103=m
+CONFIG_DVB_M88RS2000=m
+CONFIG_DVB_MANTIS=m
+CONFIG_DVB_MAX_ADAPTERS=8
+CONFIG_DVB_MB86A16=m
+CONFIG_DVB_MB86A20S=m
+CONFIG_DVB_MN88472=m
+CONFIG_DVB_MN88473=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_MXL5XX=m
+CONFIG_DVB_MXL692=m
+CONFIG_DVB_NETUP_UNIDVB=m
+CONFIG_DVB_NET=y
+CONFIG_DVB_NGENE=m
+CONFIG_DVB_NXT200X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_OR51132=m
+CONFIG_DVB_OR51211=m
+CONFIG_DVB_PLATFORM_DRIVERS=y
+CONFIG_DVB_PLL=m
+CONFIG_DVB_PLUTO2=m
+CONFIG_DVB_PT1=m
+CONFIG_DVB_PT3=m
+CONFIG_DVB_RTL2830=m
+CONFIG_DVB_RTL2832=m
+CONFIG_DVB_RTL2832_SDR=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_S5H1411=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_S921=m
+CONFIG_DVB_SI2165=m
+CONFIG_DVB_SI2168=m
+CONFIG_DVB_SI21XX=m
+CONFIG_DVB_SMIPCIE=m
+CONFIG_DVB_SP2=m
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_STB0899=m
+CONFIG_DVB_STB6000=m
+CONFIG_DVB_STB6100=m
+CONFIG_DVB_STV0288=m
+CONFIG_DVB_STV0297=m
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_STV0367=m
+CONFIG_DVB_STV0900=m
+CONFIG_DVB_STV090x=m
+CONFIG_DVB_STV0910=m
+CONFIG_DVB_STV6110=m
+CONFIG_DVB_STV6110x=m
+CONFIG_DVB_STV6111=m
+CONFIG_DVB_TAS2101=m
+CONFIG_DVB_TC90522=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_TDA10048=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_TDA10071=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_TDA18271C2DD=m
+CONFIG_DVB_TDA665x=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA8261=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TS2020=m
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+CONFIG_DVB_TUA6100=m
+CONFIG_DVB_TUNER_CX24113=m
+CONFIG_DVB_TUNER_DIB0070=m
+CONFIG_DVB_TUNER_DIB0090=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_USB_AF9015=m
+CONFIG_DVB_USB_AF9035=m
+CONFIG_DVB_USB_ANYSEE=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_AZ6007=m
+CONFIG_DVB_USB_AZ6027=m
+CONFIG_DVB_USB_CE6230=m
+CONFIG_DVB_USB_CINERGY_T2=m
+CONFIG_DVB_USB_CXUSB_ANALOG=y
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_DIB3000MC=m
+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
+CONFIG_DVB_USB_DIBUSB_MB=m
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_DTV5100=m
+CONFIG_DVB_USB_DVBSKY=m
+CONFIG_DVB_USB_DW2102=m
+CONFIG_DVB_USB_EC168=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_LME2510=m
+CONFIG_DVB_USB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_MXL111SF=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_PCTV452E=m
+CONFIG_DVB_USB_RTL28XXU=m
+CONFIG_DVB_USB_TECHNISAT_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_V2=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_ZD1301=m
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_ZD1301_DEMOD=m
+CONFIG_DVB_ZL10036=m
+CONFIG_DVB_ZL10039=m
+CONFIG_DVB_ZL10353=m
 CONFIG_DW_DMAC_CORE=y
 CONFIG_DW_DMAC=m
 CONFIG_DW_DMAC_PCI=y
 CONFIG_DW_EDMA=m
-CONFIG_DW_EDMA_PCIE=m
-CONFIG_HSU_DMA=y
-CONFIG_SF_PDMA=m
-CONFIG_INTEL_LDMA=y
-
-#
-# DMA Clients
-#
-CONFIG_ASYNC_TX_DMA=y
-# CONFIG_DMATEST is not set
-CONFIG_DMA_ENGINE_RAID=y
-
-#
-# DMABUF options
-#
-CONFIG_SYNC_FILE=y
-# CONFIG_SW_SYNC is not set
-# CONFIG_UDMABUF is not set
-# CONFIG_DMABUF_MOVE_NOTIFY is not set
-# CONFIG_DMABUF_DEBUG is not set
-CONFIG_DMABUF_SELFTESTS=m
-# CONFIG_DMABUF_HEAPS is not set
-# CONFIG_DMABUF_SYSFS_STATS is not set
-# end of DMABUF options
-
-CONFIG_DCA=m
-CONFIG_AUXDISPLAY=y
-CONFIG_CHARLCD=m
-CONFIG_LINEDISP=m
+CONFIG_DW_EDMA_PCIE=m
+CONFIG_DW_I3C_MASTER=m
+CONFIG_DW_WATCHDOG=m
+CONFIG_DW_XDATA_PCIE=m
+CONFIG_DYNAMIC_MEMORY_LAYOUT=y
+CONFIG_DYNAMIC_PHYSICAL_MASK=y
+CONFIG_DYNAMIC_SIGFRAME=y
+CONFIG_EBC_C384_WDT=m
+CONFIG_ECHO=m
+CONFIG_EDAC_AMD64=m
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_DECODE_MCE=m
+CONFIG_EDAC_E752X=m
+CONFIG_EDAC_ECS=y
+CONFIG_EDAC_GHES=m
+CONFIG_EDAC_I10NM=m
+CONFIG_EDAC_I3000=m
+CONFIG_EDAC_I3200=m
+CONFIG_EDAC_I5100=m
+CONFIG_EDAC_I5400=m
+CONFIG_EDAC_I7300=m
+CONFIG_EDAC_I7CORE=m
+CONFIG_EDAC_I82975X=m
+CONFIG_EDAC_IE31200=m
+CONFIG_EDAC_IGEN6=m
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC=m
+CONFIG_EDAC_MEM_REPAIR=y
+CONFIG_EDAC_PND2=m
+CONFIG_EDAC_SBRIDGE=m
+CONFIG_EDAC_SCRUB=y
+CONFIG_EDAC_SKX=m
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EDAC_X38=m
+CONFIG_EDD=m
+CONFIG_EEEPC_LAPTOP=m
+CONFIG_EEEPC_WMI=m
+CONFIG_EEPROM_93CX6=m
+CONFIG_EEPROM_93XX46=m
+CONFIG_EEPROM_AT24=m
+CONFIG_EEPROM_AT25=m
+CONFIG_EEPROM_EE1004=m
+CONFIG_EEPROM_IDT_89HPESX=m
+CONFIG_EEPROM_LEGACY=m
+CONFIG_EEPROM_MAX6875=m
+CONFIG_EFI_BOOTLOADER_CONTROL=m
+CONFIG_EFI_CAPSULE_LOADER=m
+CONFIG_EFI_COCO_SECRET=y
+CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
+CONFIG_EFI_DEV_PATH_PARSER=y
+CONFIG_EFI_DXE_MEM_ATTRIBUTES=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_HANDOVER_PROTOCOL=y
+CONFIG_EFI_MIXED=y
+CONFIG_EFI_RCI2_TABLE=y
+CONFIG_EFI_RUNTIME_MAP=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_SBAT_FILE=""
+CONFIG_EFI_SECRET=m
+CONFIG_EFI_SOFT_RESERVE=y
+CONFIG_EFI_STUB=y
+CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
+CONFIG_EFI_VARS_PSTORE=m
+CONFIG_EFI=y
+CONFIG_ENCLOSURE_SERVICES=m
+CONFIG_ENCRYPTED_KEYS=m
+CONFIG_ENERGY_MODEL=y
+CONFIG_ENS160=m
+CONFIG_ENS210=m
+CONFIG_ENVELOPE_DETECTOR=m
+CONFIG_EQUALIZER=m
+CONFIG_EUROTECH_WDT=m
+CONFIG_EXAR_WDT=m
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXPERT=y
+CONFIG_EXTCON_ADC_JACK=m
+CONFIG_EXTCON_AXP288=m
+CONFIG_EXTCON_FSA9480=m
+CONFIG_EXTCON_GPIO=m
+CONFIG_EXTCON_INTEL_INT3496=m
+CONFIG_EXTCON_INTEL_MRFLD=m
+CONFIG_EXTCON_LC824206XA=m
+CONFIG_EXTCON_MAX14526=m
+CONFIG_EXTCON_MAX14577=m
+CONFIG_EXTCON_MAX3355=m
+CONFIG_EXTCON_MAX77693=m
+CONFIG_EXTCON_MAX77843=m
+CONFIG_EXTCON_MAX8997=m
+CONFIG_EXTCON_PALMAS=m
+CONFIG_EXTCON_PTN5150=m
+CONFIG_EXTCON_RT8973A=m
+CONFIG_EXTCON_RTK_TYPE_C=m
+CONFIG_EXTCON_SM5502=m
+CONFIG_EXTCON_USBC_CROS_EC=m
+CONFIG_EXTCON_USBC_TUSB320=m
+CONFIG_EXTCON_USB_GPIO=m
+CONFIG_EXTCON=y
+CONFIG_EZX_PCAP=y
+CONFIG_F71808E_WDT=m
+CONFIG_FAILOVER=m
+CONFIG_FARSYNC=m
+CONFIG_FB_BACKLIGHT=m
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_IO_HELPERS=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_HELPERS_DEFERRED=y
+CONFIG_FB_SYS_HELPERS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FB_TFT_AGM1264K_FL=m
+CONFIG_FB_TFT_BD663474=m
+CONFIG_FB_TFT_HX8340BN=m
+CONFIG_FB_TFT_HX8347D=m
+CONFIG_FB_TFT_HX8353D=m
+CONFIG_FB_TFT_HX8357D=m
+CONFIG_FB_TFT_ILI9163=m
+CONFIG_FB_TFT_ILI9320=m
+CONFIG_FB_TFT_ILI9325=m
+CONFIG_FB_TFT_ILI9340=m
+CONFIG_FB_TFT_ILI9341=m
+CONFIG_FB_TFT_ILI9481=m
+CONFIG_FB_TFT_ILI9486=m
+CONFIG_FB_TFT=m
+CONFIG_FB_TFT_PCD8544=m
+CONFIG_FB_TFT_RA8875=m
+CONFIG_FB_TFT_S6D02A1=m
+CONFIG_FB_TFT_S6D1121=m
+CONFIG_FB_TFT_SEPS525=m
+CONFIG_FB_TFT_SH1106=m
+CONFIG_FB_TFT_SSD1289=m
+CONFIG_FB_TFT_SSD1305=m
+CONFIG_FB_TFT_SSD1306=m
+CONFIG_FB_TFT_SSD1331=m
+CONFIG_FB_TFT_SSD1351=m
+CONFIG_FB_TFT_ST7735R=m
+CONFIG_FB_TFT_ST7789V=m
+CONFIG_FB_TFT_TINYLCD=m
+CONFIG_FB_TFT_TLS8204=m
+CONFIG_FB_TFT_UC1611=m
+CONFIG_FB_TFT_UC1701=m
+CONFIG_FB_TFT_UPD161704=m
+CONFIG_FCOE_FNIC=m
+CONFIG_FCOE=m
+CONFIG_FIB_RULES=y
+CONFIG_FIELDBUS_DEV=m
+CONFIG_FIREWIRE=m
+CONFIG_FIREWIRE_NET=m
+CONFIG_FIREWIRE_NOSY=m
+CONFIG_FIREWIRE_OHCI=m
+CONFIG_FIREWIRE_SBP2=m
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_6x8=y
+CONFIG_FONTS=y
+CONFIG_FONT_TER16x32=y
+CONFIG_FORTIFY_SOURCE=y
+CONFIG_FPGA_BRIDGE=m
+CONFIG_FPGA_DFL_AFU=m
+CONFIG_FPGA_DFL_EMIF=m
+CONFIG_FPGA_DFL_FME_BRIDGE=m
+CONFIG_FPGA_DFL_FME=m
+CONFIG_FPGA_DFL_FME_MGR=m
+CONFIG_FPGA_DFL_FME_REGION=m
+CONFIG_FPGA_DFL=m
+CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
+CONFIG_FPGA_DFL_PCI=m
+CONFIG_FPGA=m
+CONFIG_FPGA_M10_BMC_SEC_UPDATE=m
+CONFIG_FPGA_MGR_ALTERA_CVP=m
+CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
+CONFIG_FPGA_MGR_LATTICE_SYSCONFIG=m
+CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=m
+CONFIG_FPGA_MGR_MACHXO2_SPI=m
+CONFIG_FPGA_MGR_MICROCHIP_SPI=m
+CONFIG_FPGA_MGR_XILINX_SELECTMAP=m
+CONFIG_FPGA_MGR_XILINX_SPI=m
+CONFIG_FPGA_REGION=m
+CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FRONTSWAP=y
+CONFIG_FTL=m
+CONFIG_FUEL_GAUGE_MM8013=m
+CONFIG_FUEL_GAUGE_STC3117=m
+CONFIG_FUJITSU_ES=m
+CONFIG_FUJITSU_LAPTOP=m
+CONFIG_FUJITSU_TABLET=m
+CONFIG_FUNCTION_ALIGNMENT=16
+CONFIG_FUNCTION_ALIGNMENT_16B=y
+CONFIG_FUNCTION_ALIGNMENT_4B=y
+CONFIG_FUNCTION_PADDING_BYTES=16
+CONFIG_FUNCTION_PADDING_CFI=11
+CONFIG_FUSION_CTL=m
+CONFIG_FUSION_FC=m
+CONFIG_FUSION_LAN=m
+CONFIG_FUSION_LOGGING=y
+CONFIG_FUSION_MAX_SGE=128
+CONFIG_FUSION_SAS=m
+CONFIG_FUSION_SPI=m
+CONFIG_FUSION=y
+CONFIG_FW_ATTR_CLASS=m
+CONFIG_FW_CFG_SYSFS_CMDLINE=y
+CONFIG_FW_CFG_SYSFS=m
+CONFIG_FW_CS_DSP=m
+CONFIG_FW_LOADER_COMPRESS_XZ=y
+CONFIG_FW_LOADER_COMPRESS=y
+CONFIG_FW_LOADER_COMPRESS_ZSTD=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_FWNODE_MDIO=m
+CONFIG_FW_UPLOAD=y
+CONFIG_FXAS21002C_I2C=m
+CONFIG_FXAS21002C=m
+CONFIG_FXAS21002C_SPI=m
+CONFIG_FXLS8962AF_I2C=m
+CONFIG_FXLS8962AF=m
+CONFIG_FXLS8962AF_SPI=m
+CONFIG_FXOS8700_I2C=m
+CONFIG_FXOS8700=m
+CONFIG_FXOS8700_SPI=m
+CONFIG_GADGET_UAC1=y
+CONFIG_GAMEPORT_EMU10K1=m
+CONFIG_GAMEPORT_FM801=m
+CONFIG_GAMEPORT_L4=m
+CONFIG_GAMEPORT=m
+CONFIG_GAMEPORT_NS558=m
+CONFIG_GART_IOMMU=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y
+CONFIG_GCC_VERSION=0
+CONFIG_GENERIC_ADC_BATTERY=m
+CONFIG_GENERIC_ADC_THERMAL=m
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CPU=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_ENTRY=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_PENDING_IRQ=y
+CONFIG_GENERIC_PHY_MIPI_DPHY=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PTDUMP=y
+CONFIG_GENERIC_VDSO_TIME_NS=y
+CONFIG_GENEVE=m
+CONFIG_GENWQE=m
+CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0
+CONFIG_GET_FREE_REGION=y
+CONFIG_GIGABYTE_WMI=m
+CONFIG_GNSS=m
+CONFIG_GNSS_MTK_SERIAL=m
+CONFIG_GNSS_SERIAL=m
+CONFIG_GNSS_SIRF_SERIAL=m
+CONFIG_GNSS_UBX_SERIAL=m
+CONFIG_GNSS_USB=m
+CONFIG_GOOGLE_CBMEM=m
+CONFIG_GOOGLE_COREBOOT_TABLE=m
+CONFIG_GOOGLE_FIRMWARE=y
+CONFIG_GOOGLE_FRAMEBUFFER_COREBOOT=m
+CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m
+CONFIG_GOOGLE_MEMCONSOLE=m
+CONFIG_GOOGLE_MEMCONSOLE_X86_LEGACY=m
+CONFIG_GOOGLE_SMI=m
+CONFIG_GOOGLE_VPD=m
+CONFIG_GP2AP002=m
+CONFIG_GP2AP020A00F=m
+CONFIG_GPD_POCKET_FAN=m
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIO_ADP5520=m
+CONFIG_GPIO_ADP5585=m
+CONFIG_GPIO_AGGREGATOR=m
+CONFIG_GPIO_AMD8111=m
+CONFIG_GPIO_AMD_FCH=m
+CONFIG_GPIO_AMDPT=m
+CONFIG_GPIO_ARIZONA=m
+CONFIG_GPIO_BD9571MWV=m
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CROS_EC=m
+CONFIG_GPIO_DA9052=m
+CONFIG_GPIO_DA9055=m
+CONFIG_GPIO_DLN2=m
+CONFIG_GPIO_DS4520=m
+CONFIG_GPIO_DWAPB=m
+CONFIG_GPIO_ELKHARTLAKE=m
+CONFIG_GPIO_EXAR=m
+CONFIG_GPIO_F7188X=m
+CONFIG_GPIO_FXL6408=m
+CONFIG_GPIO_GENERIC=m
+CONFIG_GPIO_GENERIC_PLATFORM=m
+CONFIG_GPIO_GRANITERAPIDS=m
+CONFIG_GPIO_ICH=m
+CONFIG_GPIO_IDIO_16=m
+CONFIG_GPIO_IT87=m
+CONFIG_GPIO_JANZ_TTL=m
+CONFIG_GPIO_KEMPLD=m
+CONFIG_GPIO_LATCH=m
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_LJCA=m
+CONFIG_GPIO_LP3943=m
+CONFIG_GPIO_LP873X=m
+CONFIG_GPIO_MADERA=m
+CONFIG_GPIO_MAX3191X=m
+CONFIG_GPIO_MAX7300=m
+CONFIG_GPIO_MAX7301=m
+CONFIG_GPIO_MAX730X=m
+CONFIG_GPIO_MAX732X=m
+CONFIG_GPIO_MB86S7X=m
+CONFIG_GPIO_MC33880=m
+CONFIG_GPIO_MENZ127=m
+CONFIG_GPIO_ML_IOH=m
+CONFIG_GPIO_MOCKUP=m
+CONFIG_GPIO_PALMAS=y
+CONFIG_GPIO_PCA953X=m
+CONFIG_GPIO_PCA9570=m
+CONFIG_GPIO_PCF857X=m
+CONFIG_GPIO_PCIE_IDIO_24=m
+CONFIG_GPIO_PCI_IDIO_16=m
+CONFIG_GPIO_PISOSR=m
+CONFIG_GPIO_RC5T583=y
+CONFIG_GPIO_RDC321X=m
+CONFIG_GPIO_REGMAP=m
+CONFIG_GPIO_SCH311X=m
+CONFIG_GPIO_SCH=m
+CONFIG_GPIO_SIM=m
+CONFIG_GPIO_SIOX=m
+CONFIG_GPIO_SYSFS_LEGACY=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_TANGIER=m
+CONFIG_GPIO_TPIC2810=m
+CONFIG_GPIO_TPS65086=m
+CONFIG_GPIO_TPS6586X=y
+CONFIG_GPIO_TPS65910=y
+CONFIG_GPIO_TPS65912=m
+CONFIG_GPIO_TPS68470=m
+CONFIG_GPIO_TQMX86=m
+CONFIG_GPIO_TWL4030=m
+CONFIG_GPIO_TWL6040=m
+CONFIG_GPIO_VIPERBOARD=m
+CONFIG_GPIO_VIRTIO=m
+CONFIG_GPIO_VX855=m
+CONFIG_GPIO_WHISKEY_COVE=m
+CONFIG_GPIO_WINBOND=m
+CONFIG_GPIO_WM831X=m
+CONFIG_GPIO_WM8350=m
+CONFIG_GPIO_WM8994=m
+CONFIG_GPIO_WS16C48=m
+CONFIG_GPIO_XRA1403=m
+CONFIG_GP_PCI1XXXX=m
+CONFIG_GREYBUS_AUDIO_APB_CODEC=m
+CONFIG_GREYBUS_AUDIO=m
+CONFIG_GREYBUS_BEAGLEPLAY=m
+CONFIG_GREYBUS_BOOTROM=m
+CONFIG_GREYBUS_BRIDGED_PHY=m
+CONFIG_GREYBUS_ES2=m
+CONFIG_GREYBUS_FIRMWARE=m
+CONFIG_GREYBUS_GPIO=m
+CONFIG_GREYBUS_HID=m
+CONFIG_GREYBUS_I2C=m
+CONFIG_GREYBUS_LIGHT=m
+CONFIG_GREYBUS_LOG=m
+CONFIG_GREYBUS_LOOPBACK=m
+CONFIG_GREYBUS=m
+CONFIG_GREYBUS_POWER=m
+CONFIG_GREYBUS_PWM=m
+CONFIG_GREYBUS_RAW=m
+CONFIG_GREYBUS_SDIO=m
+CONFIG_GREYBUS_SPI=m
+CONFIG_GREYBUS_UART=m
+CONFIG_GREYBUS_USB=m
+CONFIG_GREYBUS_VIBRATOR=m
+CONFIG_GTP=m
+CONFIG_GUEST_PERF_EVENTS=y
+CONFIG_HALTPOLL_CPUIDLE=y
+CONFIG_HANGCHECK_TIMER=m
+CONFIG_HARDENED_USERCOPY=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_LTO_CLANG=y
 CONFIG_HD44780_COMMON=m
 CONFIG_HD44780=m
-CONFIG_KS0108=m
-CONFIG_KS0108_PORT=0x378
-CONFIG_KS0108_DELAY=2
-CONFIG_CFAG12864B=m
-CONFIG_CFAG12864B_RATE=20
-CONFIG_IMG_ASCII_LCD=m
+CONFIG_HDC100X=m
+CONFIG_HDC2010=m
+CONFIG_HDC3020=m
+CONFIG_HDLC_CISCO=m
+CONFIG_HDLC_FR=m
+CONFIG_HDLC=m
+CONFIG_HDLC_PPP=m
+CONFIG_HDLC_RAW_ETH=m
+CONFIG_HDLC_RAW=m
+CONFIG_HDLC_X25=m
+CONFIG_HDMI_LPE_AUDIO=m
+CONFIG_HDMI=y
+CONFIG_HERMES_CACHE_FW_ON_INIT=y
+CONFIG_HERMES=m
+CONFIG_HERMES_PRISM=y
+CONFIG_HI8435=m
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION_COMP_LZO=y
+CONFIG_HIBERNATION_SNAPSHOT_DEV=y
+CONFIG_HIBERNATION=y
+CONFIG_HID_SENSOR_ACCEL_3D=m
+CONFIG_HID_SENSOR_ALS=m
+CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
+CONFIG_HID_SENSOR_DEVICE_ROTATION=m
+CONFIG_HID_SENSOR_GYRO_3D=m
+CONFIG_HID_SENSOR_HUMIDITY=m
+CONFIG_HID_SENSOR_IIO_COMMON=m
+CONFIG_HID_SENSOR_IIO_TRIGGER=m
+CONFIG_HID_SENSOR_INCLINOMETER_3D=m
+CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
+CONFIG_HID_SENSOR_PRESS=m
+CONFIG_HID_SENSOR_PROX=m
+CONFIG_HID_SENSOR_TEMP=m
+CONFIG_HMC425=m
+CONFIG_HMC6352=m
+CONFIG_HMEM_REPORTING=y
+CONFIG_HMM_MIRROR=y
+CONFIG_HOSTAP_CS=m
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_PCI=m
+CONFIG_HOSTAP_PLX=m
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CORE_SYNC_FULL=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_PARALLEL=y
+CONFIG_HOTPLUG_PCI_ACPI_IBM=m
+CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m
+CONFIG_HOTPLUG_PCI_CPCI=y
+CONFIG_HOTPLUG_PCI_CPCI_ZT5550=m
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_HOTPLUG_PCI_SHPC=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_SMT=y
+CONFIG_HOTPLUG_SPLIT_STARTUP=y
+CONFIG_HP03=m
+CONFIG_HP206C=m
+CONFIG_HP_ACCEL=m
+CONFIG_HP_BIOSCFG=m
+CONFIG_HPET_EMULATE_RTC=y
+CONFIG_HPET_MMAP_DEFAULT=y
+CONFIG_HPET_MMAP=y
+CONFIG_HPET_TIMER=y
+CONFIG_HPET=y
+CONFIG_HP_ILO=m
+CONFIG_HP_WATCHDOG=m
+CONFIG_HPWDT_NMI_DECODING=y
+CONFIG_HP_WMI=m
+CONFIG_HSA_AMD=y
+CONFIG_HSC030PA=m
+CONFIG_HSI_BOARDINFO=y
+CONFIG_HSI_CHAR=m
+CONFIG_HSI=m
+CONFIG_HSU_DMA=m
 CONFIG_HT16K33=m
-CONFIG_LCD2S=m
-CONFIG_PARPORT_PANEL=m
-CONFIG_PANEL_PARPORT=0
-CONFIG_PANEL_PROFILE=5
-# CONFIG_PANEL_CHANGE_MESSAGE is not set
-# CONFIG_CHARLCD_BL_OFF is not set
-# CONFIG_CHARLCD_BL_ON is not set
-CONFIG_CHARLCD_BL_FLASH=y
-CONFIG_PANEL=m
-CONFIG_UIO=m
-CONFIG_UIO_CIF=m
-CONFIG_UIO_PDRV_GENIRQ=m
-CONFIG_UIO_DMEM_GENIRQ=m
-CONFIG_UIO_AEC=m
-CONFIG_UIO_SERCOS3=m
-CONFIG_UIO_PCI_GENERIC=m
-CONFIG_UIO_NETX=m
-CONFIG_UIO_PRUSS=m
-CONFIG_UIO_MF624=m
-CONFIG_UIO_HV_GENERIC=m
-CONFIG_UIO_DFL=m
-CONFIG_VFIO=m
-CONFIG_VFIO_IOMMU_TYPE1=m
-CONFIG_VFIO_VIRQFD=m
-# CONFIG_VFIO_NOIOMMU is not set
-CONFIG_VFIO_PCI_CORE=m
-CONFIG_VFIO_PCI_MMAP=y
-CONFIG_VFIO_PCI_INTX=y
-CONFIG_VFIO_PCI=m
-CONFIG_MLX5_VFIO_PCI=m
-CONFIG_HISI_ACC_VFIO_PCI=m
-CONFIG_VFIO_PCI_VGA=y
-CONFIG_VFIO_PCI_IGD=y
-CONFIG_VFIO_MDEV=m
-CONFIG_IRQ_BYPASS_MANAGER=m
-CONFIG_VIRT_DRIVERS=y
-CONFIG_VMGENID=m
-CONFIG_VBOXGUEST=m
-CONFIG_NITRO_ENCLAVES=m
-CONFIG_EFI_SECRET=m
-CONFIG_SEV_GUEST=m
-CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON=y
-CONFIG_VIRTIO=m
-CONFIG_ARCH_HAS_RESTRICTED_VIRTIO_MEMORY_ACCESS=y
-CONFIG_VIRTIO_PCI_LIB=m
-CONFIG_VIRTIO_PCI_LIB_LEGACY=m
-CONFIG_VIRTIO_MENU=y
-CONFIG_VIRTIO_PCI=m
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_VDPA=m
-CONFIG_VIRTIO_PMEM=m
-CONFIG_VIRTIO_BALLOON=m
-CONFIG_VIRTIO_MEM=m
-CONFIG_VIRTIO_INPUT=m
-CONFIG_VIRTIO_MMIO=m
-CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
-CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
-CONFIG_VDPA=m
-CONFIG_VDPA_USER=m
+CONFIG_HTE=y
+CONFIG_HTS221_I2C=m
+CONFIG_HTS221=m
+CONFIG_HTS221_SPI=m
+CONFIG_HTU21=m
+CONFIG_HUAWEI_WMI=m
+CONFIG_HWMON_VID=m
+CONFIG_HW_RANDOM_AMD=y
+CONFIG_HW_RANDOM_BA431=y
+CONFIG_HW_RANDOM_INTEL=y
+CONFIG_HW_RANDOM_TIMERIOMEM=y
+CONFIG_HW_RANDOM_TPM=y
+CONFIG_HW_RANDOM_VIA=y
+CONFIG_HW_RANDOM_XIPHERA=m
+CONFIG_HW_RANDOM=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HX711=m
+CONFIG_HX9023S=m
+CONFIG_HYPERV_BALLOON=m
+CONFIG_HYPERV_IOMMU=y
+CONFIG_HYPERVISOR_GUEST=y
+CONFIG_HYPERV_KEYBOARD=m
+CONFIG_HYPERV_NET=m
+CONFIG_HYPERV_STORAGE=m
+CONFIG_HYPERV_TIMER=y
+CONFIG_HYPERV_UTILS=m
+CONFIG_HYPERV_VMBUS=m
+CONFIG_HYPERV=y
+CONFIG_HZ=1000
+CONFIG_HZ_1000=y
+CONFIG_I2C_ALGOBIT=m
+CONFIG_I2C_ALGOPCA=m
+CONFIG_I2C_ALI1535=m
+CONFIG_I2C_ALI1563=m
+CONFIG_I2C_ALI15X3=m
+CONFIG_I2C_AMD756=m
+CONFIG_I2C_AMD756_S4882=m
+CONFIG_I2C_AMD8111=m
+CONFIG_I2C_AMD_MP2=m
+CONFIG_I2C_ATR=m
+CONFIG_I2C_CBUS_GPIO=m
+CONFIG_I2C_CCGX_UCSI=m
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_CP2615=m
+CONFIG_I2C_CROS_EC_TUNNEL=m
+CONFIG_I2C_DESIGNWARE_AMDPSP=y
+CONFIG_I2C_DESIGNWARE_CORE=m
+CONFIG_I2C_DESIGNWARE_PCI=m
+CONFIG_I2C_DESIGNWARE_PLATFORM=m
+CONFIG_I2C_DIOLAN_U2C=m
+CONFIG_I2C_DLN2=m
+CONFIG_I2C_EMEV2=m
+CONFIG_I2C_GPIO=m
+CONFIG_I2C_I801=m
+CONFIG_I2C_ISCH=m
+CONFIG_I2C_ISMT=m
+CONFIG_I2C_KEMPLD=m
+CONFIG_I2C_LJCA=m
+CONFIG_I2C=m
+CONFIG_I2C_MLXCPLD=m
+CONFIG_I2C_MUX_GPIO=m
+CONFIG_I2C_MUX_LTC4306=m
+CONFIG_I2C_MUX=m
+CONFIG_I2C_MUX_MLXCPLD=m
+CONFIG_I2C_MUX_MULE=m
+CONFIG_I2C_MUX_PCA9541=m
+CONFIG_I2C_MUX_PCA954x=m
+CONFIG_I2C_MUX_REG=m
+CONFIG_I2C_NCT6694=m
+CONFIG_I2C_NFORCE2=m
+CONFIG_I2C_NFORCE2_S4985=m
+CONFIG_I2C_NVIDIA_GPU=m
+CONFIG_I2C_OCORES=m
+CONFIG_I2C_PARPORT=m
+CONFIG_I2C_PCA_PLATFORM=m
+CONFIG_I2C_PCI1XXXX=m
+CONFIG_I2C_PIIX4=m
+CONFIG_I2C_ROBOTFUZZ_OSIF=m
+CONFIG_I2C_SCMI=m
+CONFIG_I2C_SI470X=m
+CONFIG_I2C_SI4713=m
+CONFIG_I2C_SIMTEC=m
+CONFIG_I2C_SIS5595=m
+CONFIG_I2C_SIS630=m
+CONFIG_I2C_SIS96X=m
+CONFIG_I2C_SLAVE_EEPROM=m
+CONFIG_I2C_SLAVE_TESTUNIT=m
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SMBUS=m
+CONFIG_I2C_TAOS_EVM=m
+CONFIG_I2C_TINY_USB=m
+CONFIG_I2C_USBIO=m
+CONFIG_I2C_VIA=m
+CONFIG_I2C_VIAPRO=m
+CONFIG_I2C_VIPERBOARD=m
+CONFIG_I2C_VIRTIO=m
+CONFIG_I2C_XILINX=m
+CONFIG_I2C_ZHAOXIN=m
+CONFIG_I3C=m
+CONFIG_I6300ESB_WDT=m
+CONFIG_I82092=m
+CONFIG_I8253_LOCK=y
+CONFIG_IA32_EMULATION=y
+CONFIG_IA32_FEAT_CTL=y
+CONFIG_IAQCORE=m
+CONFIG_IB700_WDT=m
+CONFIG_IBM_ASM=m
+CONFIG_IBMASR=m
+CONFIG_IBM_RTL=m
+CONFIG_ICP10100=m
+CONFIG_ICPLUS_PHY=m
+CONFIG_ICS932S401=m
+CONFIG_IDEAPAD_LAPTOP=m
+CONFIG_IDLE_INJECT=y
+CONFIG_IE6XX_WDT=m
+CONFIG_IFB=m
 CONFIG_IFCVF=m
-CONFIG_MLX5_VDPA=y
-CONFIG_MLX5_VDPA_NET=m
-CONFIG_VP_VDPA=m
-CONFIG_ALIBABA_ENI_VDPA=m
-CONFIG_VHOST_IOTLB=m
-CONFIG_VHOST_RING=m
-CONFIG_VHOST=m
-CONFIG_VHOST_MENU=y
-CONFIG_VHOST_NET=m
-CONFIG_VHOST_SCSI=m
-CONFIG_VHOST_VSOCK=m
-CONFIG_VHOST_VDPA=m
-# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
-
-#
-# Microsoft Hyper-V guest support
-#
-CONFIG_HYPERV=m
-CONFIG_HYPERV_TIMER=y
-CONFIG_HYPERV_UTILS=m
-CONFIG_HYPERV_BALLOON=m
-# end of Microsoft Hyper-V guest support
-
-CONFIG_GREYBUS=m
-CONFIG_GREYBUS_ES2=m
-CONFIG_COMEDI=m
-# CONFIG_COMEDI_DEBUG is not set
-CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
-CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
-CONFIG_COMEDI_MISC_DRIVERS=y
-CONFIG_COMEDI_BOND=m
-CONFIG_COMEDI_TEST=m
-CONFIG_COMEDI_PARPORT=m
-CONFIG_COMEDI_ISA_DRIVERS=y
-CONFIG_COMEDI_PCL711=m
-CONFIG_COMEDI_PCL724=m
-CONFIG_COMEDI_PCL726=m
-CONFIG_COMEDI_PCL730=m
-CONFIG_COMEDI_PCL812=m
-CONFIG_COMEDI_PCL816=m
-CONFIG_COMEDI_PCL818=m
-CONFIG_COMEDI_PCM3724=m
-CONFIG_COMEDI_AMPLC_DIO200_ISA=m
-CONFIG_COMEDI_AMPLC_PC236_ISA=m
-CONFIG_COMEDI_AMPLC_PC263_ISA=m
-CONFIG_COMEDI_RTI800=m
-CONFIG_COMEDI_RTI802=m
-CONFIG_COMEDI_DAC02=m
-CONFIG_COMEDI_DAS16M1=m
-CONFIG_COMEDI_DAS08_ISA=m
-CONFIG_COMEDI_DAS16=m
-CONFIG_COMEDI_DAS800=m
-CONFIG_COMEDI_DAS1800=m
-CONFIG_COMEDI_DAS6402=m
-CONFIG_COMEDI_DT2801=m
-CONFIG_COMEDI_DT2811=m
-CONFIG_COMEDI_DT2814=m
-CONFIG_COMEDI_DT2815=m
-CONFIG_COMEDI_DT2817=m
-CONFIG_COMEDI_DT282X=m
-CONFIG_COMEDI_DMM32AT=m
-CONFIG_COMEDI_FL512=m
-CONFIG_COMEDI_AIO_AIO12_8=m
-CONFIG_COMEDI_AIO_IIRO_16=m
-CONFIG_COMEDI_II_PCI20KC=m
-CONFIG_COMEDI_C6XDIGIO=m
-CONFIG_COMEDI_MPC624=m
-CONFIG_COMEDI_ADQ12B=m
-CONFIG_COMEDI_NI_AT_A2150=m
-CONFIG_COMEDI_NI_AT_AO=m
-CONFIG_COMEDI_NI_ATMIO=m
-CONFIG_COMEDI_NI_ATMIO16D=m
-CONFIG_COMEDI_NI_LABPC_ISA=m
-CONFIG_COMEDI_PCMAD=m
-CONFIG_COMEDI_PCMDA12=m
-CONFIG_COMEDI_PCMMIO=m
-CONFIG_COMEDI_PCMUIO=m
-CONFIG_COMEDI_MULTIQ3=m
-CONFIG_COMEDI_S526=m
-CONFIG_COMEDI_PCI_DRIVERS=m
-CONFIG_COMEDI_8255_PCI=m
-CONFIG_COMEDI_ADDI_WATCHDOG=m
-CONFIG_COMEDI_ADDI_APCI_1032=m
-CONFIG_COMEDI_ADDI_APCI_1500=m
-CONFIG_COMEDI_ADDI_APCI_1516=m
-CONFIG_COMEDI_ADDI_APCI_1564=m
-CONFIG_COMEDI_ADDI_APCI_16XX=m
-CONFIG_COMEDI_ADDI_APCI_2032=m
-CONFIG_COMEDI_ADDI_APCI_2200=m
-CONFIG_COMEDI_ADDI_APCI_3120=m
-CONFIG_COMEDI_ADDI_APCI_3501=m
-CONFIG_COMEDI_ADDI_APCI_3XXX=m
-CONFIG_COMEDI_ADL_PCI6208=m
-CONFIG_COMEDI_ADL_PCI7X3X=m
-CONFIG_COMEDI_ADL_PCI8164=m
-CONFIG_COMEDI_ADL_PCI9111=m
-CONFIG_COMEDI_ADL_PCI9118=m
-CONFIG_COMEDI_ADV_PCI1710=m
-CONFIG_COMEDI_ADV_PCI1720=m
-CONFIG_COMEDI_ADV_PCI1723=m
-CONFIG_COMEDI_ADV_PCI1724=m
-CONFIG_COMEDI_ADV_PCI1760=m
-CONFIG_COMEDI_ADV_PCI_DIO=m
-CONFIG_COMEDI_AMPLC_DIO200_PCI=m
-CONFIG_COMEDI_AMPLC_PC236_PCI=m
-CONFIG_COMEDI_AMPLC_PC263_PCI=m
-CONFIG_COMEDI_AMPLC_PCI224=m
-CONFIG_COMEDI_AMPLC_PCI230=m
-CONFIG_COMEDI_CONTEC_PCI_DIO=m
-CONFIG_COMEDI_DAS08_PCI=m
-CONFIG_COMEDI_DT3000=m
-CONFIG_COMEDI_DYNA_PCI10XX=m
-CONFIG_COMEDI_GSC_HPDI=m
-CONFIG_COMEDI_MF6X4=m
-CONFIG_COMEDI_ICP_MULTI=m
-CONFIG_COMEDI_DAQBOARD2000=m
-CONFIG_COMEDI_JR3_PCI=m
-CONFIG_COMEDI_KE_COUNTER=m
-CONFIG_COMEDI_CB_PCIDAS64=m
-CONFIG_COMEDI_CB_PCIDAS=m
-CONFIG_COMEDI_CB_PCIDDA=m
-CONFIG_COMEDI_CB_PCIMDAS=m
-CONFIG_COMEDI_CB_PCIMDDA=m
-CONFIG_COMEDI_ME4000=m
-CONFIG_COMEDI_ME_DAQ=m
-CONFIG_COMEDI_NI_6527=m
-CONFIG_COMEDI_NI_65XX=m
-CONFIG_COMEDI_NI_660X=m
-CONFIG_COMEDI_NI_670X=m
-CONFIG_COMEDI_NI_LABPC_PCI=m
-CONFIG_COMEDI_NI_PCIDIO=m
-CONFIG_COMEDI_NI_PCIMIO=m
-CONFIG_COMEDI_RTD520=m
-CONFIG_COMEDI_S626=m
-CONFIG_COMEDI_MITE=m
-CONFIG_COMEDI_NI_TIOCMD=m
-CONFIG_COMEDI_PCMCIA_DRIVERS=m
-CONFIG_COMEDI_CB_DAS16_CS=m
-CONFIG_COMEDI_DAS08_CS=m
-CONFIG_COMEDI_NI_DAQ_700_CS=m
-CONFIG_COMEDI_NI_DAQ_DIO24_CS=m
-CONFIG_COMEDI_NI_LABPC_CS=m
-CONFIG_COMEDI_NI_MIO_CS=m
-CONFIG_COMEDI_QUATECH_DAQP_CS=m
-CONFIG_COMEDI_USB_DRIVERS=m
-CONFIG_COMEDI_DT9812=m
-CONFIG_COMEDI_NI_USB6501=m
-CONFIG_COMEDI_USBDUX=m
-CONFIG_COMEDI_USBDUXFAST=m
-CONFIG_COMEDI_USBDUXSIGMA=m
-CONFIG_COMEDI_VMK80XX=m
-CONFIG_COMEDI_8254=m
-CONFIG_COMEDI_8255=m
-CONFIG_COMEDI_8255_SA=m
-CONFIG_COMEDI_KCOMEDILIB=m
-CONFIG_COMEDI_AMPLC_DIO200=m
-CONFIG_COMEDI_AMPLC_PC236=m
-CONFIG_COMEDI_DAS08=m
-CONFIG_COMEDI_ISADMA=m
-CONFIG_COMEDI_NI_LABPC=m
-CONFIG_COMEDI_NI_LABPC_ISADMA=m
-CONFIG_COMEDI_NI_TIO=m
-CONFIG_COMEDI_NI_ROUTING=m
-CONFIG_COMEDI_TESTS=m
-CONFIG_COMEDI_TESTS_EXAMPLE=m
-CONFIG_COMEDI_TESTS_NI_ROUTES=m
-CONFIG_STAGING=y
-CONFIG_PRISM2_USB=m
-CONFIG_RTL8192U=m
-CONFIG_RTLLIB=m
-CONFIG_RTLLIB_CRYPTO_CCMP=m
-CONFIG_RTLLIB_CRYPTO_TKIP=m
-CONFIG_RTLLIB_CRYPTO_WEP=m
-CONFIG_RTL8192E=m
-CONFIG_RTL8723BS=m
-CONFIG_R8712U=m
-CONFIG_R8188EU=m
-CONFIG_RTS5208=m
-CONFIG_VT6655=m
-CONFIG_VT6656=m
-
-#
-# IIO staging drivers
-#
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16203=m
-CONFIG_ADIS16240=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD7816=m
-CONFIG_AD7280=m
-# end of Analog to digital converters
-
-#
-# Analog digital bi-direction converters
-#
-CONFIG_ADT7316=m
-CONFIG_ADT7316_SPI=m
-CONFIG_ADT7316_I2C=m
-# end of Analog digital bi-direction converters
-
-#
-# Capacitance to digital converters
-#
-CONFIG_AD7746=m
-# end of Capacitance to digital converters
-
-#
-# Direct Digital Synthesis
-#
-CONFIG_AD9832=m
-CONFIG_AD9834=m
-# end of Direct Digital Synthesis
-
-#
-# Network Analyzer, Impedance Converters
-#
-CONFIG_AD5933=m
-# end of Network Analyzer, Impedance Converters
-
-#
-# Active energy metering IC
-#
-CONFIG_ADE7854=m
-CONFIG_ADE7854_I2C=m
-CONFIG_ADE7854_SPI=m
-# end of Active energy metering IC
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S1210=m
-# end of Resolver to digital converters
-# end of IIO staging drivers
-
-# CONFIG_FB_SM750 is not set
-CONFIG_STAGING_MEDIA=y
+CONFIG_IIO_ADIS_LIB_BUFFER=y
+CONFIG_IIO_ADIS_LIB=m
+CONFIG_IIO_BUFFER_CB=m
+CONFIG_IIO_BUFFER_DMAENGINE=m
+CONFIG_IIO_BUFFER_DMA=m
+CONFIG_IIO_BUFFER_HW_CONSUMER=m
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_CONFIGFS=m
+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
+CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
+CONFIG_IIO_CROS_EC_ACTIVITY=m
+CONFIG_IIO_CROS_EC_BARO=m
+CONFIG_IIO_CROS_EC_LIGHT_PROX=m
+CONFIG_IIO_CROS_EC_SENSORS_CORE=m
+CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m
+CONFIG_IIO_CROS_EC_SENSORS=m
+CONFIG_IIO_GTS_HELPER=m
+CONFIG_IIO_HRTIMER_TRIGGER=m
+CONFIG_IIO_INTERRUPT_TRIGGER=m
+CONFIG_IIO_KFIFO_BUF=m
+CONFIG_IIO_KX022A_I2C=m
+CONFIG_IIO_KX022A=m
+CONFIG_IIO_KX022A_SPI=m
+CONFIG_IIO=m
+CONFIG_IIO_MS_SENSORS_I2C=m
+CONFIG_IIO_MUX=m
+CONFIG_IIO_RESCALE=m
+CONFIG_IIO_SSP_SENSORHUB=m
+CONFIG_IIO_SSP_SENSORS_COMMONS=m
+CONFIG_IIO_ST_ACCEL_3AXIS=m
+CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
+CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
+CONFIG_IIO_ST_GYRO_3AXIS=m
+CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
+CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
+CONFIG_IIO_ST_LSM6DSX_I2C=m
+CONFIG_IIO_ST_LSM6DSX_I3C=m
+CONFIG_IIO_ST_LSM6DSX=m
+CONFIG_IIO_ST_LSM6DSX_SPI=m
+CONFIG_IIO_ST_LSM9DS0_I2C=m
+CONFIG_IIO_ST_LSM9DS0=m
+CONFIG_IIO_ST_LSM9DS0_SPI=m
+CONFIG_IIO_ST_MAGN_3AXIS=m
+CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
+CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
+CONFIG_IIO_ST_PRESS_I2C=m
+CONFIG_IIO_ST_PRESS=m
+CONFIG_IIO_ST_PRESS_SPI=m
+CONFIG_IIO_ST_SENSORS_CORE=m
+CONFIG_IIO_ST_SENSORS_I2C=m
+CONFIG_IIO_ST_SENSORS_SPI=m
+CONFIG_IIO_SW_DEVICE=m
+CONFIG_IIO_SW_TRIGGER=m
+CONFIG_IIO_SYSFS_TRIGGER=m
+CONFIG_IIO_TIGHTLOOP_TRIGGER=m
+CONFIG_IIO_TRIGGERED_BUFFER=m
+CONFIG_IIO_TRIGGERED_EVENT=m
+CONFIG_IIO_TRIGGER=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_IMG_ASCII_LCD=m
+CONFIG_INA2XX_ADC=m
+CONFIG_INFINEON_TLV493D=m
+CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
+CONFIG_INFINIBAND_ADDR_TRANS=y
+CONFIG_INFINIBAND_BNXT_RE=m
+CONFIG_INFINIBAND_CXGB4=m
+CONFIG_INFINIBAND_EFA=m
+CONFIG_INFINIBAND_ERDMA=m
+CONFIG_INFINIBAND_HFI1=m
+CONFIG_INFINIBAND_IONIC=m
+CONFIG_INFINIBAND_IPOIB_CM=y
+CONFIG_INFINIBAND_IPOIB=m
+CONFIG_INFINIBAND_IRDMA=m
+CONFIG_INFINIBAND_ISER=m
+CONFIG_INFINIBAND_ISERT=m
+CONFIG_INFINIBAND=m
+CONFIG_INFINIBAND_MTHCA=m
+CONFIG_INFINIBAND_OCRDMA=m
+CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
+CONFIG_INFINIBAND_OPA_VNIC=m
+CONFIG_INFINIBAND_QEDR=m
+CONFIG_INFINIBAND_QIB_DCA=y
+CONFIG_INFINIBAND_QIB=m
+CONFIG_INFINIBAND_RDMAVT=m
+CONFIG_INFINIBAND_RTRS_CLIENT=m
+CONFIG_INFINIBAND_RTRS=m
+CONFIG_INFINIBAND_RTRS_SERVER=m
+CONFIG_INFINIBAND_SRP=m
+CONFIG_INFINIBAND_SRPT=m
+CONFIG_INFINIBAND_USER_ACCESS=m
+CONFIG_INFINIBAND_USER_MAD=m
+CONFIG_INFINIBAND_USER_MEM=y
+CONFIG_INFINIBAND_USNIC=m
+CONFIG_INFINIBAND_VIRT_DMA=y
+CONFIG_INFINIBAND_VMWARE_PVRDMA=m
+CONFIG_INFTL=m
+CONFIG_INIT_STACK_NONE=y
+CONFIG_INPUT_88PM80X_ONKEY=m
+CONFIG_INPUT_88PM860X_ONKEY=m
+CONFIG_INPUT_AD714X_I2C=m
+CONFIG_INPUT_AD714X=m
+CONFIG_INPUT_AD714X_SPI=m
+CONFIG_INPUT_ADXL34X_I2C=m
+CONFIG_INPUT_ADXL34X=m
+CONFIG_INPUT_ADXL34X_SPI=m
+CONFIG_INPUT_APANEL=m
+CONFIG_INPUT_ARIZONA_HAPTICS=m
+CONFIG_INPUT_ATC260X_ONKEY=m
+CONFIG_INPUT_ATI_REMOTE2=m
+CONFIG_INPUT_ATLAS_BTNS=m
+CONFIG_INPUT_AXP20X_PEK=m
+CONFIG_INPUT_BMA150=m
+CONFIG_INPUT_CM109=m
+CONFIG_INPUT_CMA3000_I2C=m
+CONFIG_INPUT_CMA3000=m
+CONFIG_INPUT_CS40L50_VIBRA=m
+CONFIG_INPUT_DA7280_HAPTICS=m
+CONFIG_INPUT_DA9052_ONKEY=m
+CONFIG_INPUT_DA9055_ONKEY=m
+CONFIG_INPUT_DA9063_ONKEY=m
+CONFIG_INPUT_DRV260X_HAPTICS=m
+CONFIG_INPUT_DRV2665_HAPTICS=m
+CONFIG_INPUT_DRV2667_HAPTICS=m
+CONFIG_INPUT_E3X0_BUTTON=m
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_GPIO_BEEPER=m
+CONFIG_INPUT_GPIO_DECODER=m
+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
+CONFIG_INPUT_GPIO_VIBRA=m
+CONFIG_INPUT_IBM_PANEL=m
+CONFIG_INPUT_IDEAPAD_SLIDEBAR=m
+CONFIG_INPUT_IMS_PCU=m
+CONFIG_INPUT_IQS269A=m
+CONFIG_INPUT_IQS626A=m
+CONFIG_INPUT_IQS7222=m
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_INPUT_KEYSPAN_REMOTE=m
+CONFIG_INPUT_KXTJ9=m
+CONFIG_INPUT_LEDS=m
+CONFIG_INPUT_MATRIXKMAP=m
+CONFIG_INPUT_MAX7360_ROTARY=m
+CONFIG_INPUT_MAX77693_HAPTIC=m
+CONFIG_INPUT_MAX8925_ONKEY=m
+CONFIG_INPUT_MAX8997_HAPTIC=m
+CONFIG_INPUT_MC13783_PWRBUTTON=m
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MMA8450=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_PALMAS_PWRBUTTON=m
+CONFIG_INPUT_PCAP=m
+CONFIG_INPUT_PCF50633_PMU=m
+CONFIG_INPUT_PCF8574=m
+CONFIG_INPUT_PCSPKR=m
+CONFIG_INPUT_POWERMATE=m
+CONFIG_INPUT_PWM_BEEPER=m
+CONFIG_INPUT_PWM_VIBRA=m
+CONFIG_INPUT_QNAP_MCU=m
+CONFIG_INPUT_RAVE_SP_PWRBUTTON=m
+CONFIG_INPUT_REGULATOR_HAPTIC=m
+CONFIG_INPUT_RETU_PWRBUTTON=m
+CONFIG_INPUT_RT5120_PWRKEY=m
+CONFIG_INPUT_SOC_BUTTON_ARRAY=m
+CONFIG_INPUT_SPARSEKMAP=m
+CONFIG_INPUT_TABLET=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_TWL4030_PWRBUTTON=m
+CONFIG_INPUT_TWL4030_VIBRA=m
+CONFIG_INPUT_TWL6040_VIBRA=m
+CONFIG_INPUT_UINPUT=m
+CONFIG_INPUT_VIVALDIFMAP=y
+CONFIG_INPUT_WM831X_ON=m
+CONFIG_INPUT_YEALINK=m
+CONFIG_INSPUR_PLATFORM_PROFILE=m
+CONFIG_INSTRUCTION_DECODER=y
+CONFIG_INT3406_THERMAL=m
+CONFIG_INT340X_THERMAL=m
+CONFIG_INTEL_ATOMISP2_LED=m
+CONFIG_INTEL_ATOMISP2_PDX86=y
 CONFIG_INTEL_ATOMISP=y
-CONFIG_VIDEO_ATOMISP=m
-CONFIG_VIDEO_ATOMISP_ISP2401=y
-CONFIG_VIDEO_ATOMISP_OV2722=m
-CONFIG_VIDEO_ATOMISP_GC2235=m
-CONFIG_VIDEO_ATOMISP_MSRLIST_HELPER=m
-CONFIG_VIDEO_ATOMISP_MT9M114=m
-CONFIG_VIDEO_ATOMISP_GC0310=m
-CONFIG_VIDEO_ATOMISP_OV2680=m
-CONFIG_VIDEO_ATOMISP_OV5693=m
-CONFIG_VIDEO_ATOMISP_LM3554=m
-CONFIG_VIDEO_ZORAN=m
-CONFIG_VIDEO_ZORAN_DC30=y
-CONFIG_VIDEO_ZORAN_ZR36060=y
-CONFIG_VIDEO_ZORAN_BUZ=y
-CONFIG_VIDEO_ZORAN_DC10=y
-CONFIG_VIDEO_ZORAN_LML33=y
-CONFIG_VIDEO_ZORAN_LML33R10=y
-CONFIG_VIDEO_ZORAN_AVS6EYES=y
-CONFIG_VIDEO_IPU3_IMGU=m
-CONFIG_DVB_AV7110_IR=y
-CONFIG_DVB_AV7110=m
-CONFIG_DVB_AV7110_OSD=y
-CONFIG_DVB_BUDGET_PATCH=m
-CONFIG_DVB_SP8870=m
-
-#
-# Android
-#
-CONFIG_ASHMEM=m
-# end of Android
-
+CONFIG_INTEL_BXT_PMIC_THERMAL=m
+CONFIG_INTEL_BXTWC_PMIC_TMU=m
+CONFIG_INTEL_CHTWC_INT33FE=m
+CONFIG_INTEL_GTT=m
+CONFIG_INTEL_HFI_THERMAL=y
+CONFIG_INTEL_HID_EVENT=m
+CONFIG_INTEL_IDLE=y
+CONFIG_INTEL_IDMA64=m
+CONFIG_INTEL_IDXD_BUS=m
+CONFIG_INTEL_IDXD=m
+CONFIG_INTEL_IDXD_PERFMON=y
+CONFIG_INTEL_IDXD_SVM=y
+CONFIG_INTEL_IFS=m
+CONFIG_INTEL_INT0002_VGPIO=m
+CONFIG_INTEL_IOATDMA=m
+CONFIG_INTEL_IOMMU_FLOPPY_WA=y
+CONFIG_INTEL_IOMMU_PERF_EVENTS=y
+CONFIG_INTEL_IOMMU_SVM=y
+CONFIG_INTEL_IOMMU=y
+CONFIG_INTEL_IPS=m
+CONFIG_INTEL_ISH_FIRMWARE_DOWNLOADER=m
+CONFIG_INTEL_ISH_HID=m
+CONFIG_INTEL_ISHTP_ECLITE=m
+CONFIG_INTEL_LDMA=y
+CONFIG_INTEL_MEI_GSC=m
+CONFIG_INTEL_MEI_GSC_PROXY=m
+CONFIG_INTEL_MEI_HDCP=m
+CONFIG_INTEL_MEI_LB=m
+CONFIG_INTEL_MEI_ME=y
+CONFIG_INTEL_MEI_PXP=m
+CONFIG_INTEL_MEI_TXE=m
+CONFIG_INTEL_MEI_VSC_HW=m
+CONFIG_INTEL_MEI_VSC=m
+CONFIG_INTEL_MEI_WDT=m
+CONFIG_INTEL_MEI=y
+CONFIG_INTEL_MRFLD_ADC=m
+CONFIG_INTEL_MRFLD_PWRBTN=m
+CONFIG_INTEL_OAKTRAIL=m
+CONFIG_INTEL_OC_WATCHDOG=m
+CONFIG_INTEL_PCH_THERMAL=m
+CONFIG_INTEL_PLR_TPMI=m
+CONFIG_INTEL_PMC_CORE=y
+CONFIG_INTEL_PMT_CLASS=m
+CONFIG_INTEL_PMT_CRASHLOG=m
+CONFIG_INTEL_PMT_TELEMETRY=m
+CONFIG_INTEL_POWERCLAMP=m
+CONFIG_INTEL_PUNIT_IPC=m
+CONFIG_INTEL_QEP=m
+CONFIG_INTEL_QUICKI2C=m
+CONFIG_INTEL_QUICKSPI=m
+CONFIG_INTEL_RAPL_CORE=m
+CONFIG_INTEL_RAPL=m
+CONFIG_INTEL_RAPL_TPMI=m
+CONFIG_INTEL_RST=m
+CONFIG_INTEL_SAR_INT1092=m
+CONFIG_INTEL_SCU_IPC_UTIL=m
+CONFIG_INTEL_SCU_IPC=y
+CONFIG_INTEL_SCU_PCI=y
+CONFIG_INTEL_SCU_PLATFORM=m
+CONFIG_INTEL_SCU=y
+CONFIG_INTEL_SDSI=m
+CONFIG_INTEL_SKL_INT3472=m
+CONFIG_INTEL_SMARTCONNECT=m
+CONFIG_INTEL_SOC_DTS_IOSF_CORE=m
+CONFIG_INTEL_SOC_DTS_THERMAL=m
+CONFIG_INTEL_SOC_PMIC_BXTWC=m
+CONFIG_INTEL_SOC_PMIC_MRFLD=m
+CONFIG_INTEL_SPEED_SELECT_INTERFACE=m
+CONFIG_INTEL_SPEED_SELECT_TPMI=m
+CONFIG_INTEL_TCC_COOLING=m
+CONFIG_INTEL_TCC=y
+CONFIG_INTEL_TDX_GUEST=y
+CONFIG_INTEL_TDX_HOST=y
+CONFIG_INTEL_TELEMETRY=m
+CONFIG_INTEL_TH_ACPI=m
+CONFIG_INTEL_THC_HID=m
+CONFIG_INTEL_TH_GTH=m
+CONFIG_INTEL_TH=m
+CONFIG_INTEL_TH_MSU=m
+CONFIG_INTEL_TH_PCI=m
+CONFIG_INTEL_TH_PTI=m
+CONFIG_INTEL_TH_STH=m
+CONFIG_INTEL_TPMI=m
+CONFIG_INTEL_TURBO_MAX_3=y
+CONFIG_INTEL_TXT=y
+CONFIG_INTEL_UNCORE_FREQ_CONTROL=m
+CONFIG_INTEL_UNCORE_FREQ_CONTROL_TPMI=m
+CONFIG_INTEL_VBTN=m
+CONFIG_INTEL_VSC=m
+CONFIG_INTEL_VSEC=m
+CONFIG_INTEL_WMI_SBL_FW_UPDATE=m
+CONFIG_INTEL_WMI_THUNDERBOLT=m
+CONFIG_INTEL_WMI=y
+CONFIG_INTEL_XWAY_PHY=m
+CONFIG_INTERRUPT_CNT=m
+CONFIG_INTERVAL_TREE_SPAN_ITER=y
+CONFIG_INV_ICM42600_I2C=m
+CONFIG_INV_ICM42600=m
+CONFIG_INV_ICM42600_SPI=m
+CONFIG_INV_MPU6050_I2C=m
+CONFIG_INV_MPU6050_IIO=m
+CONFIG_INV_MPU6050_SPI=m
+CONFIG_IO_DELAY_0X80=y
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMUFD=m
+CONFIG_IOMMU_HELPER=y
+CONFIG_IOMMU_IO_PGTABLE=y
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_SVA=y
+CONFIG_IOSCHED_BFQ=y
+CONFIG_IOSF_MBI=y
+CONFIG_IOSM=m
+CONFIG_IP5XXX_POWER=m
+CONFIG_IPACK_BUS=m
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_DMI_DECODE=y
+CONFIG_IPMI_HANDLER=m
+CONFIG_IPMI_IPMB=m
+CONFIG_IPMI_PANIC_EVENT=y
+CONFIG_IPMI_PANIC_STRING=y
+CONFIG_IPMI_PLAT_DATA=y
+CONFIG_IPMI_POWEROFF=m
+CONFIG_IPMI_SI=m
+CONFIG_IPMI_SSIF=m
+CONFIG_IPMI_WATCHDOG=m
+CONFIG_IPU_BRIDGE=m
+CONFIG_IPVLAN_L3S=y
+CONFIG_IPVLAN=m
+CONFIG_IPVTAP=m
+CONFIG_IPW2100=m
+CONFIG_IPW2100_MONITOR=y
+CONFIG_IPW2200=m
+CONFIG_IPW2200_MONITOR=y
+CONFIG_IPW2200_PROMISCUOUS=y
+CONFIG_IPW2200_QOS=y
+CONFIG_IPW2200_RADIOTAP=y
+CONFIG_IPWIRELESS=m
+CONFIG_IQS620AT_TEMP=m
+CONFIG_IQS621_ALS=m
+CONFIG_IQS624_POS=m
+CONFIG_IR_ENE=m
+CONFIG_IR_FINTEK=m
+CONFIG_IR_IGORPLUGUSB=m
+CONFIG_IR_IGUANA=m
+CONFIG_IR_IMON_DECODER=m
+CONFIG_IR_IMON=m
+CONFIG_IR_IMON_RAW=m
+CONFIG_IR_ITE_CIR=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_MCE_KBD_DECODER=m
+CONFIG_IR_MCEUSB=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_NUVOTON=m
+CONFIG_IRQ_BYPASS_MANAGER=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_POLL=y
+CONFIG_IRQ_REMAP=y
+CONFIG_IRQ_SIM=y
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_RCMM_DECODER=m
+CONFIG_IR_REDRAT3=m
+CONFIG_IR_SANYO_DECODER=m
+CONFIG_IRSD200=m
+CONFIG_IR_SERIAL=m
+CONFIG_IR_SERIAL_TRANSMITTER=y
+CONFIG_IR_SHARP_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_STREAMZAP=m
+CONFIG_IR_TOY=m
+CONFIG_IR_TTUSBIR=m
+CONFIG_IR_WINBOND_CIR=m
+CONFIG_IR_XMP_DECODER=m
+CONFIG_ISA_BUS_API=y
+CONFIG_ISA_DMA_API=y
+CONFIG_ISCSI_BOOT_SYSFS=m
+CONFIG_ISCSI_IBFT_FIND=y
+CONFIG_ISCSI_IBFT=m
+CONFIG_ISCSI_TARGET_CXGB4=m
+CONFIG_ISCSI_TARGET=m
+CONFIG_ISCSI_TCP=m
+CONFIG_ISDN_CAPI_MIDDLEWARE=y
+CONFIG_ISDN_CAPI=y
+CONFIG_ISDN=y
+CONFIG_ISL29003=m
+CONFIG_ISL29020=m
+CONFIG_ISL29125=m
+CONFIG_ISL29501=m
+CONFIG_ISL76682=m
+CONFIG_IT8712F_WDT=m
+CONFIG_IT87_WDT=m
+CONFIG_ITCO_VENDOR_SUPPORT=y
+CONFIG_ITCO_WDT=m
+CONFIG_ITG3200=m
+CONFIG_IWL3945=m
+CONFIG_IWL4965=m
+CONFIG_IWLDVM=m
+CONFIG_IWLEGACY=m
+CONFIG_IWLMLD=m
+CONFIG_IWLMVM=m
+CONFIG_IWLWIFI_LEDS=y
+CONFIG_IWLWIFI=m
+CONFIG_IWLWIFI_OPMODE_MODULAR=y
+CONFIG_JAILHOUSE_GUEST=y
+CONFIG_JOYSTICK_A3D=m
+CONFIG_JOYSTICK_ADC=m
+CONFIG_JOYSTICK_ADI=m
+CONFIG_JOYSTICK_ANALOG=m
+CONFIG_JOYSTICK_AS5011=m
+CONFIG_JOYSTICK_COBRA=m
+CONFIG_JOYSTICK_DB9=m
+CONFIG_JOYSTICK_FSIA6B=m
+CONFIG_JOYSTICK_GAMECON=m
+CONFIG_JOYSTICK_GF2K=m
+CONFIG_JOYSTICK_GRIP=m
+CONFIG_JOYSTICK_GRIP_MP=m
+CONFIG_JOYSTICK_GUILLEMOT=m
+CONFIG_JOYSTICK_IFORCE_232=m
+CONFIG_JOYSTICK_IFORCE=m
+CONFIG_JOYSTICK_IFORCE_USB=m
+CONFIG_JOYSTICK_INTERACT=m
+CONFIG_JOYSTICK_MAGELLAN=m
+CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
+CONFIG_JOYSTICK_PSXPAD_SPI=m
+CONFIG_JOYSTICK_PXRC=m
+CONFIG_JOYSTICK_QWIIC=m
+CONFIG_JOYSTICK_SEESAW=m
+CONFIG_JOYSTICK_SENSEHAT=m
+CONFIG_JOYSTICK_SIDEWINDER=m
+CONFIG_JOYSTICK_SPACEBALL=m
+CONFIG_JOYSTICK_SPACEORB=m
+CONFIG_JOYSTICK_STINGER=m
+CONFIG_JOYSTICK_TMDC=m
+CONFIG_JOYSTICK_TURBOGRAFX=m
+CONFIG_JOYSTICK_TWIDJOY=m
+CONFIG_JOYSTICK_WALKERA0701=m
+CONFIG_JOYSTICK_WARRIOR=m
+CONFIG_JOYSTICK_XPAD_FF=y
+CONFIG_JOYSTICK_XPAD_LEDS=y
+CONFIG_JOYSTICK_XPAD=m
+CONFIG_JOYSTICK_ZHENHUA=m
+CONFIG_JSA1212=m
+CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KARMA_PARTITION=y
+CONFIG_KCMP=y
+CONFIG_KEMPLD_WDT=m
+CONFIG_KERNEL_ZSTD=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEXEC_FILE=y
+CONFIG_KEXEC_HANDOVER=y
+CONFIG_KEXEC_JUMP=y
+CONFIG_KEXEC=y
+CONFIG_KEYBOARD_ADC=m
+CONFIG_KEYBOARD_ADP5520=m
+CONFIG_KEYBOARD_ADP5588=m
+CONFIG_KEYBOARD_ADP5589=m
+CONFIG_KEYBOARD_APPLESPI=m
+CONFIG_KEYBOARD_CROS_EC=m
+CONFIG_KEYBOARD_CYPRESS_SF=m
+CONFIG_KEYBOARD_DLINK_DIR685=m
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_KEYBOARD_GPIO_POLLED=m
+CONFIG_KEYBOARD_IQS62X=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_LM8323=m
+CONFIG_KEYBOARD_LM8333=m
+CONFIG_KEYBOARD_MATRIX=m
+CONFIG_KEYBOARD_MAX7359=m
+CONFIG_KEYBOARD_MCS=m
+CONFIG_KEYBOARD_MPR121=m
+CONFIG_KEYBOARD_MTK_PMIC=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_OPENCORES=m
+CONFIG_KEYBOARD_PINEPHONE=m
+CONFIG_KEYBOARD_QT1050=m
+CONFIG_KEYBOARD_QT1070=m
+CONFIG_KEYBOARD_QT2160=m
+CONFIG_KEYBOARD_SAMSUNG=m
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_TCA6416=m
+CONFIG_KEYBOARD_TCA8418=m
+CONFIG_KEYBOARD_TM2_TOUCHKEY=m
+CONFIG_KEYBOARD_TWL4030=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEY_DH_OPERATIONS=y
+CONFIG_KEYS_REQUEST_CACHE=y
+CONFIG_KMX61=m
+CONFIG_KRETPROBE_ON_RETHOOK=y
+CONFIG_KRETPROBES=y
+CONFIG_KS0108_DELAY=2
+CONFIG_KS0108=m
+CONFIG_KS0108_PORT=0x378
+CONFIG_KS7010=m
+CONFIG_KSM=y
+CONFIG_KUNPENG_HCCS=m
+CONFIG_KVM_AMD=m
+CONFIG_KVM_AMD_SEV=y
+CONFIG_KVM_ASYNC_PF=y
+CONFIG_KVM_COMPAT=y
+CONFIG_KVM_EXTERNAL_WRITE_TRACKING=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y
+CONFIG_KVM_GUEST=y
+CONFIG_KVM_HYPERV=y
+CONFIG_KVM_INTEL=m
+CONFIG_KVM_INTEL_TDX=y
+CONFIG_KVM_IOAPIC=y
+CONFIG_KVM=m
+CONFIG_KVM_MAX_NR_VCPUS=4096
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_PROVE_MMU=y
+CONFIG_KVM_SMM=y
+CONFIG_KVM_SW_PROTECTED_VM=y
+CONFIG_KVM_VFIO=y
+CONFIG_KVM_WERROR=y
+CONFIG_KVM_XEN=y
+CONFIG_KVM_XFER_TO_GUEST_WORK=y
+CONFIG_KXCJK1013=m
+CONFIG_KXSD9_I2C=m
+CONFIG_KXSD9=m
+CONFIG_KXSD9_SPI=m
+CONFIG_LAPBETHER=m
+CONFIG_LATENCYTOP=y
+CONFIG_LATTICE_ECP3_CONFIG=m
+CONFIG_LCD2S=m
+CONFIG_LCD_AMS369FG06=m
+CONFIG_LCD_CLASS_DEVICE=m
+CONFIG_LCD_HX8357=m
+CONFIG_LCD_ILI922X=m
+CONFIG_LCD_ILI9320=m
+CONFIG_LCD_L4F00242T03=m
+CONFIG_LCD_LMS283GF05=m
+CONFIG_LCD_LMS501KF03=m
+CONFIG_LCD_LTV350QV=m
+CONFIG_LCD_OTM3225A=m
+CONFIG_LCD_PLATFORM=m
+CONFIG_LCD_TDO24M=m
+CONFIG_LCD_VGG2432A4=m
+CONFIG_LD_IS_LLD=y
+CONFIG_LDM_DEBUG=y
+CONFIG_LDM_PARTITION=y
+CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
+CONFIG_LD_ORPHAN_WARN=y
+CONFIG_LD_VERSION=0
+CONFIG_LEDS_88PM860X=m
+CONFIG_LEDS_ADP5520=m
+CONFIG_LEDS_APU=m
+CONFIG_LEDS_AS3645A=m
+CONFIG_LEDS_AW200XX=m
+CONFIG_LEDS_BD2606MVV=m
+CONFIG_LEDS_BD2802=m
+CONFIG_LEDS_BLINKM=m
+CONFIG_LEDS_CLASS_FLASH=m
+CONFIG_LEDS_CLASS_MULTICOLOR=m
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CROS_EC=m
+CONFIG_LEDS_DA903X=m
+CONFIG_LEDS_DA9052=m
+CONFIG_LEDS_DAC124S085=m
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_GROUP_MULTICOLOR=m
+CONFIG_LEDS_INTEL_SS4200=m
+CONFIG_LEDS_IS31FL319X=m
+CONFIG_LEDS_KTD202X=m
+CONFIG_LEDS_LM3530=m
+CONFIG_LEDS_LM3532=m
+CONFIG_LEDS_LM3533=m
+CONFIG_LEDS_LM355x=m
+CONFIG_LEDS_LM3601X=m
+CONFIG_LEDS_LM36274=m
+CONFIG_LEDS_LM3642=m
+CONFIG_LEDS_LP3944=m
+CONFIG_LEDS_LP3952=m
+CONFIG_LEDS_LP50XX=m
+CONFIG_LEDS_LP8788=m
+CONFIG_LEDS_LT3593=m
+CONFIG_LEDS_MAX5970=m
+CONFIG_LEDS_MAX8997=m
+CONFIG_LEDS_MC13783=m
+CONFIG_LEDS_MENF21BMC=m
+CONFIG_LEDS_MLXCPLD=m
+CONFIG_LEDS_MLXREG=m
+CONFIG_LEDS_MT6323=m
+CONFIG_LEDS_MT6370_FLASH=m
+CONFIG_LEDS_MT6370_RGB=m
+CONFIG_LEDS_NCP5623=m
+CONFIG_LEDS_NIC78BX=m
+CONFIG_LEDS_PCA9532_GPIO=y
+CONFIG_LEDS_PCA9532=m
+CONFIG_LEDS_PCA955X=m
+CONFIG_LEDS_PCA963X=m
+CONFIG_LEDS_PCA995X=m
+CONFIG_LEDS_PWM=m
+CONFIG_LEDS_PWM_MULTICOLOR=m
+CONFIG_LEDS_REGULATOR=m
+CONFIG_LEDS_RT8515=m
+CONFIG_LEDS_SGM3140=m
+CONFIG_LEDS_SIEMENS_SIMATIC_IPC_APOLLOLAKE=m
+CONFIG_LEDS_SIEMENS_SIMATIC_IPC_ELKHARTLAKE=m
+CONFIG_LEDS_SIEMENS_SIMATIC_IPC_F7188X=m
+CONFIG_LEDS_SIEMENS_SIMATIC_IPC=m
+CONFIG_LEDS_SPI_BYTE=m
+CONFIG_LEDS_ST1202=m
+CONFIG_LEDS_SUN50I_A100=m
+CONFIG_LEDS_SY7802=m
+CONFIG_LEDS_TCA6507=m
+CONFIG_LEDS_TI_LMU_COMMON=m
+CONFIG_LEDS_TLC591XX=m
+CONFIG_LEDS_TPS6105X=m
+CONFIG_LEDS_TRIGGER_ACTIVITY=m
+CONFIG_LEDS_TRIGGER_AUDIO=m
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_CAMERA=m
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_GPIO=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_NETDEV=m
+CONFIG_LEDS_TRIGGER_ONESHOT=m
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEDS_TRIGGER_PATTERN=m
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_TRANSIENT=m
+CONFIG_LEDS_TRIGGER_TTY=m
+CONFIG_LEDS_UPBOARD=m
+CONFIG_LEDS_USER=m
+CONFIG_LEDS_WM831X_STATUS=m
+CONFIG_LEDS_WM8350=m
+CONFIG_LEGACY_VSYSCALL_XONLY=y
+CONFIG_LENOVO_SE10_WDT=m
+CONFIG_LENOVO_SE30_WDT=m
+CONFIG_LENOVO_WMI_CAMERA=m
+CONFIG_LENOVO_WMI_GAMEZONE=m
+CONFIG_LENOVO_WMI_HOTKEY_UTILITIES=m
+CONFIG_LENOVO_YMC=m
+CONFIG_LG_LAPTOP=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211=m
+CONFIG_LIBCRC32C=m
+CONFIG_LIBERTAS_CS=m
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_MESH=y
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+CONFIG_LIBERTAS_THINFIRM=m
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBFC=m
+CONFIG_LIBFCOE=m
+CONFIG_LIBIPW=m
+CONFIG_LIBNVDIMM=m
+CONFIG_LIDAR_LITE_V2=m
+CONFIG_LINEAR_RANGES=y
+CONFIG_LINEDISP=m
+CONFIG_LIRC=y
+CONFIG_LLD_VERSION=160006
+CONFIG_LMK04832=m
+CONFIG_LMP91000=m
+CONFIG_LOCK_MM_AND_FIND_VMA=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO=y
+CONFIG_LOOPBACK_TARGET=m
+CONFIG_LP8788_ADC=m
+CONFIG_LPC_ICH=m
+CONFIG_LP_CONSOLE=y
+CONFIG_LPC_SCH=m
+CONFIG_LRU_CACHE=m
+CONFIG_LRU_GEN_ENABLED=y
+CONFIG_LRU_GEN=y
+CONFIG_LSI_ET1011C_PHY=m
+CONFIG_LSM="landlock,yama,loadpin,safesetid,integrity,bpf"
+CONFIG_LTC1660=m
+CONFIG_LTC2309=m
+CONFIG_LTC2471=m
+CONFIG_LTC2485=m
+CONFIG_LTC2496=m
+CONFIG_LTC2497=m
+CONFIG_LTC2632=m
+CONFIG_LTC2664=m
+CONFIG_LTC2688=m
+CONFIG_LTC2983=m
 CONFIG_LTE_GDM724X=m
-CONFIG_FIREWIRE_SERIAL=m
-CONFIG_FWTTY_MAX_TOTAL_PORTS=64
-CONFIG_FWTTY_MAX_CARD_PORTS=32
-CONFIG_GS_FPGABOOT=m
-CONFIG_UNISYSSPAR=y
-# CONFIG_UNISYS_VISORNIC is not set
-# CONFIG_UNISYS_VISORINPUT is not set
-# CONFIG_UNISYS_VISORHBA is not set
-CONFIG_FB_TFT=m
-CONFIG_FB_TFT_AGM1264K_FL=m
-CONFIG_FB_TFT_BD663474=m
-CONFIG_FB_TFT_HX8340BN=m
-CONFIG_FB_TFT_HX8347D=m
-CONFIG_FB_TFT_HX8353D=m
-CONFIG_FB_TFT_HX8357D=m
-CONFIG_FB_TFT_ILI9163=m
-CONFIG_FB_TFT_ILI9320=m
-CONFIG_FB_TFT_ILI9325=m
-CONFIG_FB_TFT_ILI9340=m
-CONFIG_FB_TFT_ILI9341=m
-CONFIG_FB_TFT_ILI9481=m
-CONFIG_FB_TFT_ILI9486=m
-CONFIG_FB_TFT_PCD8544=m
-CONFIG_FB_TFT_RA8875=m
-CONFIG_FB_TFT_S6D02A1=m
-CONFIG_FB_TFT_S6D1121=m
-CONFIG_FB_TFT_SEPS525=m
-CONFIG_FB_TFT_SH1106=m
-CONFIG_FB_TFT_SSD1289=m
-CONFIG_FB_TFT_SSD1305=m
-CONFIG_FB_TFT_SSD1306=m
-CONFIG_FB_TFT_SSD1331=m
-CONFIG_FB_TFT_SSD1351=m
-CONFIG_FB_TFT_ST7735R=m
-CONFIG_FB_TFT_ST7789V=m
-CONFIG_FB_TFT_TINYLCD=m
-CONFIG_FB_TFT_TLS8204=m
-CONFIG_FB_TFT_UC1611=m
-CONFIG_FB_TFT_UC1701=m
-CONFIG_FB_TFT_UPD161704=m
-CONFIG_FB_TFT_WATTEROTT=m
+CONFIG_LTO_CLANG_THIN=y
+CONFIG_LTO_CLANG=y
+CONFIG_LTO=y
+CONFIG_LTR390=m
+CONFIG_LTR501=m
+CONFIG_LTRF216A=m
+CONFIG_LV0104CS=m
+CONFIG_LWTUNNEL_BPF=y
+CONFIG_LWTUNNEL=y
+CONFIG_LXT_PHY=m
+CONFIG_LZ4_COMPRESS=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_LZ4HC_COMPRESS=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_M62332=m
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_MAC80211=m
+CONFIG_MAC80211_MESH=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC_EMUMOUSEBTN=m
+CONFIG_MACHZ_WDT=m
+CONFIG_MACINTOSH_DRIVERS=y
+CONFIG_MAC_PARTITION=y
+CONFIG_MACSEC=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_MADERA_IRQ=m
+CONFIG_MAG3110=m
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
+CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAILBOX=y
+CONFIG_MANAGER_SBS=m
+CONFIG_MANA_INFINIBAND=m
+CONFIG_MANTIS_CORE=m
+CONFIG_MAPPING_DIRTY_HELPERS=y
+CONFIG_MARVELL_10G_PHY=m
+CONFIG_MARVELL_88Q2XXX_PHY=m
+CONFIG_MARVELL_88X2222_PHY=m
+CONFIG_MARVELL_GTI_WDT=m
+CONFIG_MARVELL_PHY=m
+CONFIG_MAX1027=m
+CONFIG_MAX11100=m
+CONFIG_MAX1118=m
+CONFIG_MAX11205=m
+CONFIG_MAX11410=m
+CONFIG_MAX1241=m
+CONFIG_MAX1363=m
+CONFIG_MAX30100=m
+CONFIG_MAX30102=m
+CONFIG_MAX30208=m
+CONFIG_MAX31856=m
+CONFIG_MAX31865=m
+CONFIG_MAX34408=m
+CONFIG_MAX44000=m
+CONFIG_MAX44009=m
+CONFIG_MAX517=m
+CONFIG_MAX5432=m
+CONFIG_MAX5481=m
+CONFIG_MAX5487=m
+CONFIG_MAX5522=m
+CONFIG_MAX5821=m
+CONFIG_MAX63XX_WATCHDOG=m
+CONFIG_MAX6959=m
+CONFIG_MAX77541_ADC=m
+CONFIG_MAX8925_POWER=m
+CONFIG_MAX9611=m
+CONFIG_MAXIM_THERMOCOUPLE=m
+CONFIG_MAXLINEAR_GPHY=m
+CONFIG_MAXSMP=y
+CONFIG_MB1232=m
+CONFIG_MC3230=m
+CONFIG_MCB_LPC=m
+CONFIG_MCB=m
+CONFIG_MCB_PCI=m
+CONFIG_MCP320X=m
+CONFIG_MCP3422=m
+CONFIG_MCP3564=m
+CONFIG_MCP3911=m
+CONFIG_MCP4018=m
+CONFIG_MCP41010=m
+CONFIG_MCP4131=m
+CONFIG_MCP4531=m
+CONFIG_MCP4725=m
+CONFIG_MCP4728=m
+CONFIG_MCP4821=m
+CONFIG_MCP4922=m
+CONFIG_MCP9600=m
+CONFIG_MCTP_FLOWS=y
+CONFIG_MCTP_SERIAL=m
+CONFIG_MCTP_TRANSPORT_I2C=m
+CONFIG_MCTP_TRANSPORT_I3C=m
+CONFIG_MCTP_TRANSPORT_USB=m
+CONFIG_MCTP=y
+CONFIG_MD_CLUSTER=m
+CONFIG_MD_FAULTY=m
+CONFIG_MDIO_BCM_UNIMAC=m
+CONFIG_MDIO_BITBANG=m
+CONFIG_MDIO_BUS=m
+CONFIG_MDIO_CAVIUM=m
+CONFIG_MDIO_DEVICE=m
+CONFIG_MDIO_DEVRES=m
+CONFIG_MDIO_GPIO=m
+CONFIG_MDIO_I2C=m
+CONFIG_MDIO_MSCC_MIIM=m
+CONFIG_MDIO_MVUSB=m
+CONFIG_MDIO_REGMAP=m
+CONFIG_MDIO_THUNDER=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID456=m
+CONFIG_MEDIA_ALTERA_CI=m
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CEC_RC=y
+CONFIG_MEDIA_CEC_SUPPORT=y
+CONFIG_MEDIA_COMMON_OPTIONS=y
+CONFIG_MEDIA_CONTROLLER_DVB=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_PCI_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIATEK_GE_PHY=m
+CONFIG_MEDIATEK_MT6359_AUXADC=m
+CONFIG_MEDIATEK_MT6360_ADC=m
+CONFIG_MEDIATEK_MT6370_ADC=m
+CONFIG_MEDIA_TUNER_AV201X=m
+CONFIG_MEDIA_TUNER_E4000=m
+CONFIG_MEDIA_TUNER_FC0011=m
+CONFIG_MEDIA_TUNER_FC0012=m
+CONFIG_MEDIA_TUNER_FC0013=m
+CONFIG_MEDIA_TUNER_FC2580=m
+CONFIG_MEDIA_TUNER_IT913X=m
+CONFIG_MEDIA_TUNER=m
+CONFIG_MEDIA_TUNER_M88RS6000T=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MSI001=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2063=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2131=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_MXL301RF=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_QM1D1B0004=m
+CONFIG_MEDIA_TUNER_QM1D1C0042=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_R820T=m
+CONFIG_MEDIA_TUNER_SI2157=m
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_STV6120=m
+CONFIG_MEDIA_TUNER_TDA18212=m
+CONFIG_MEDIA_TUNER_TDA18218=m
+CONFIG_MEDIA_TUNER_TDA18250=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_TUA9001=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC4000=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_MEEGOPAD_ANX7428=m
+CONFIG_MEGARAID_LEGACY=m
+CONFIG_MEGARAID_MAILBOX=m
+CONFIG_MEGARAID_MM=m
+CONFIG_MEGARAID_NEWGEN=y
+CONFIG_MEGARAID_SAS=m
+CONFIG_MELLANOX_PLATFORM=y
+CONFIG_MEMORY_FAILURE=y
+CONFIG_MEMORY_HOTPLUG=y
+CONFIG_MEMORY_HOTREMOVE=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MEMORY=y
+CONFIG_MEMREGION=y
+CONFIG_MEMSTICK_JMICRON_38X=m
+CONFIG_MEMSTICK=m
+CONFIG_MEMSTICK_R592=m
+CONFIG_MEMSTICK_REALTEK_PCI=m
+CONFIG_MEMSTICK_REALTEK_USB=m
+CONFIG_MEMSTICK_TIFM_MS=m
+CONFIG_MEN_A21_WDT=m
+CONFIG_MENF21BMC_WATCHDOG=m
+CONFIG_MENZ069_WATCHDOG=m
+CONFIG_MEN_Z188_ADC=m
+CONFIG_MERAKI_MX100=m
+CONFIG_MFD_88PM800=m
+CONFIG_MFD_88PM805=m
+CONFIG_MFD_88PM860X=y
+CONFIG_MFD_88PM886_PMIC=y
+CONFIG_MFD_AAT2870_CORE=y
+CONFIG_MFD_ARIZONA_I2C=m
+CONFIG_MFD_ARIZONA=m
+CONFIG_MFD_ARIZONA_SPI=m
+CONFIG_MFD_AS3711=y
+CONFIG_MFD_ATC260X_I2C=m
+CONFIG_MFD_ATC260X=m
+CONFIG_MFD_AXP20X_I2C=m
+CONFIG_MFD_AXP20X=m
+CONFIG_MFD_BCM590XX=m
+CONFIG_MFD_BD9571MWV=m
+CONFIG_MFD_CORE=y
+CONFIG_MFD_CROS_EC_DEV=m
+CONFIG_MFD_CS42L43_I2C=m
+CONFIG_MFD_CS42L43_SDW=m
+CONFIG_MFD_CS47L15=y
+CONFIG_MFD_CS47L24=y
+CONFIG_MFD_CS47L35=y
+CONFIG_MFD_CS47L85=y
+CONFIG_MFD_CS47L90=y
+CONFIG_MFD_CS47L92=y
+CONFIG_MFD_DA9052_I2C=y
+CONFIG_MFD_DA9052_SPI=y
+CONFIG_MFD_DA9055=y
+CONFIG_MFD_DA9062=m
+CONFIG_MFD_DA9063=m
+CONFIG_MFD_DA9150=m
+CONFIG_MFD_DLN2=m
+CONFIG_MFD_INTEL_LPSS_ACPI=m
+CONFIG_MFD_INTEL_LPSS=m
+CONFIG_MFD_INTEL_LPSS_PCI=m
+CONFIG_MFD_INTEL_M10_BMC_CORE=m
+CONFIG_MFD_INTEL_M10_BMC_PMCI=m
+CONFIG_MFD_INTEL_M10_BMC_SPI=m
+CONFIG_MFD_INTEL_PMC_BXT=m
+CONFIG_MFD_INTEL_QUARK_I2C_GPIO=m
+CONFIG_MFD_IQS62X=m
+CONFIG_MFD_JANZ_CMODIO=m
+CONFIG_MFD_KEMPLD=m
+CONFIG_MFD_LM3533=m
+CONFIG_MFD_LP3943=m
+CONFIG_MFD_LP8788=y
+CONFIG_MFD_MADERA_I2C=m
+CONFIG_MFD_MADERA=m
+CONFIG_MFD_MADERA_SPI=m
+CONFIG_MFD_MAX14577=m
+CONFIG_MFD_MAX77541=m
+CONFIG_MFD_MAX77693=m
+CONFIG_MFD_MAX77843=y
+CONFIG_MFD_MAX8907=m
+CONFIG_MFD_MAX8925=y
+CONFIG_MFD_MAX8997=y
+CONFIG_MFD_MAX8998=y
+CONFIG_MFD_MC13XXX_I2C=m
+CONFIG_MFD_MC13XXX=m
+CONFIG_MFD_MC13XXX_SPI=m
+CONFIG_MFD_MENF21BMC=m
+CONFIG_MFD_MP2629=m
+CONFIG_MFD_MT6360=m
+CONFIG_MFD_MT6370=m
+CONFIG_MFD_MT6397=m
+CONFIG_MFD_OCELOT=m
+CONFIG_MFD_PALMAS=m
+CONFIG_MFD_PCF50633=m
+CONFIG_MFD_QNAP_MCU=m
+CONFIG_MFD_RC5T583=y
+CONFIG_MFD_RDC321X=m
+CONFIG_MFD_RETU=m
+CONFIG_MFD_RT4831=m
+CONFIG_MFD_RT5033=m
+CONFIG_MFD_RT5120=m
+CONFIG_MFD_SI476X_CORE=m
+CONFIG_MFD_SIMPLE_MFD_I2C=m
+CONFIG_MFD_SKY81452=m
+CONFIG_MFD_SM501_GPIO=y
+CONFIG_MFD_SM501=m
+CONFIG_MFD_SMPRO=m
+CONFIG_MFD_SY7636A=m
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_TI_AM335X_TSCADC=m
+CONFIG_MFD_TI_LMU=m
+CONFIG_MFD_TI_LP873X=m
+CONFIG_MFD_TPS65086=m
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
+CONFIG_MFD_TPS65912_I2C=m
+CONFIG_MFD_TPS65912_SPI=y
+CONFIG_MFD_TPS65912=y
+CONFIG_MFD_TPS6594_I2C=m
+CONFIG_MFD_TPS6594=m
+CONFIG_MFD_TPS6594_SPI=m
+CONFIG_MFD_TQMX86=m
+CONFIG_MFD_TWL4030_AUDIO=y
+CONFIG_MFD_TWL4030_CORE=y
+CONFIG_MFD_UPBOARD_FPGA=m
+CONFIG_MFD_VIPERBOARD=m
+CONFIG_MFD_VX855=m
+CONFIG_MFD_WCD934X=m
+CONFIG_MFD_WL1273_CORE=m
+CONFIG_MFD_WM5102=y
+CONFIG_MFD_WM5110=y
+CONFIG_MFD_WM831X_I2C=y
+CONFIG_MFD_WM831X_SPI=y
+CONFIG_MFD_WM831X=y
+CONFIG_MFD_WM8350_I2C=y
+CONFIG_MFD_WM8400=y
+CONFIG_MFD_WM8994=m
+CONFIG_MFD_WM8997=y
+CONFIG_MFD_WM8998=y
+CONFIG_MHI_BUS_EP=m
+CONFIG_MHI_BUS=m
+CONFIG_MHI_BUS_PCI_GENERIC=m
+CONFIG_MHI_NET=m
+CONFIG_MHI_WWAN_CTRL=m
+CONFIG_MHI_WWAN_MBIM=m
+CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO=y
+CONFIG_MHP_MEMMAP_ON_MEMORY=y
+CONFIG_MICREL_KS8995MA=m
+CONFIG_MICREL_PHY=m
+CONFIG_MICROCHIP_PHY=m
+CONFIG_MICROCHIP_T1_PHY=m
+CONFIG_MICROCHIP_T1S_PHY=m
+CONFIG_MICROCODE_AMD=y
+CONFIG_MICROCODE_INTEL=y
+CONFIG_MICROCODE=y
+CONFIG_MICROSEMI_PHY=m
+CONFIG_MII=m
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_MIPI_I3C_HCI=m
+CONFIG_MIPI_I3C_HCI_PCI=m
+CONFIG_MISC_ALCOR_PCI=m
+CONFIG_MISC_RTSX=m
+CONFIG_MISC_RTSX_PCI=m
+CONFIG_MISC_RTSX_USB=m
+CONFIG_MISDN_AVMFRITZ=m
+CONFIG_MISDN_DSP=m
+CONFIG_MISDN_HDLC=m
+CONFIG_MISDN_HFCMULTI=m
+CONFIG_MISDN_HFCPCI=m
+CONFIG_MISDN_HFCUSB=m
+CONFIG_MISDN_INFINEON=m
+CONFIG_MISDN_IPAC=m
+CONFIG_MISDN_ISAR=m
+CONFIG_MISDN_L1OIP=m
+CONFIG_MISDN=m
+CONFIG_MISDN_NETJET=m
+CONFIG_MISDN_SPEEDFAX=m
+CONFIG_MISDN_W6692=m
+CONFIG_MITIGATION_CALL_DEPTH_TRACKING=y
+CONFIG_MITIGATION_IBPB_ENTRY=y
+CONFIG_MITIGATION_IBRS_ENTRY=y
+CONFIG_MITIGATION_ITS=y
+CONFIG_MITIGATION_L1TF=y
+CONFIG_MITIGATION_MDS=y
+CONFIG_MITIGATION_MMIO_STALE_DATA=y
+CONFIG_MITIGATION_PAGE_TABLE_ISOLATION=y
+CONFIG_MITIGATION_RETBLEED=y
+CONFIG_MITIGATION_RETHUNK=y
+CONFIG_MITIGATION_RETPOLINE=y
+CONFIG_MITIGATION_RFDS=y
+CONFIG_MITIGATION_SLS=y
+CONFIG_MITIGATION_SPECTRE_BHI=y
+CONFIG_MITIGATION_SPECTRE_V1=y
+CONFIG_MITIGATION_SPECTRE_V2=y
+CONFIG_MITIGATION_SRBDS=y
+CONFIG_MITIGATION_SRSO=y
+CONFIG_MITIGATION_SSB=y
+CONFIG_MITIGATION_TAA=y
+CONFIG_MITIGATION_TSA=y
+CONFIG_MITIGATION_UNRET_ENTRY=y
+CONFIG_MITIGATION_VMSCAPE=y
+CONFIG_MLX4_INFINIBAND=m
+CONFIG_MLX5_INFINIBAND=m
+CONFIG_MLX5_VDPA_NET=m
+CONFIG_MLX5_VDPA=y
+CONFIG_MLX5_VFIO_PCI=m
+CONFIG_MLX90614=m
+CONFIG_MLX90632=m
+CONFIG_MLX90635=m
+CONFIG_MLX_PLATFORM=m
+CONFIG_MLXREG_DPU=m
+CONFIG_MLXREG_HOTPLUG=m
+CONFIG_MLXREG_IO=m
+CONFIG_MLXREG_LC=m
+CONFIG_MLX_WDT=m
+CONFIG_MMA7455_I2C=m
+CONFIG_MMA7455=m
+CONFIG_MMA7455_SPI=m
+CONFIG_MMA7660=m
+CONFIG_MMA8452=m
+CONFIG_MMA9551_CORE=m
+CONFIG_MMA9551=m
+CONFIG_MMA9553=m
+CONFIG_MMC35240=m
+CONFIG_MMC_ALCOR=m
+CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_CB710=m
+CONFIG_MMC_CQHCI=m
+CONFIG_MMC_HSQ=m
+CONFIG_MMC=m
+CONFIG_MMC_MTK=m
+CONFIG_MMCONF_FAM10H=y
+CONFIG_MMC_REALTEK_PCI=m
+CONFIG_MMC_REALTEK_USB=m
+CONFIG_MMC_RICOH_MMC=y
+CONFIG_MMC_SDHCI_ACPI=m
+CONFIG_MMC_SDHCI_F_SDH30=m
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI=m
+CONFIG_MMC_SDHCI_PCI=m
+CONFIG_MMC_SDHCI_PLTFM=m
+CONFIG_MMC_SDHCI_XENON=m
+CONFIG_MMC_SDRICOH_CS=m
+CONFIG_MMC_SPI=m
+CONFIG_MMC_TIFM_SD=m
+CONFIG_MMC_USDHI6ROL0=m
+CONFIG_MMC_USHC=m
+CONFIG_MMC_VIA_SDMMC=m
+CONFIG_MMC_VUB300=m
+CONFIG_MMC_WBSD=m
+CONFIG_MMU_GATHER_MERGE_VMAS=y
+CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
+CONFIG_MMU_GATHER_TABLE_FREE=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODIFY_LDT_SYSCALL=y
+CONFIG_MODULE_SIG_KEY="certs/signing_key.pem"
+CONFIG_MODULE_SIG_KEY_TYPE_RSA=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOST_CDEV=m
 CONFIG_MOST_COMPONENTS=m
+CONFIG_MOST_I2C=m
+CONFIG_MOST=m
 CONFIG_MOST_NET=m
+CONFIG_MOST_SND=m
+CONFIG_MOST_USB_HDM=m
 CONFIG_MOST_VIDEO=m
-CONFIG_MOST_I2C=m
-CONFIG_KS7010=m
-CONFIG_GREYBUS_AUDIO=m
-CONFIG_GREYBUS_AUDIO_APB_CODEC=m
-CONFIG_GREYBUS_BOOTROM=m
-CONFIG_GREYBUS_FIRMWARE=m
-CONFIG_GREYBUS_HID=m
-CONFIG_GREYBUS_LIGHT=m
-CONFIG_GREYBUS_LOG=m
-CONFIG_GREYBUS_LOOPBACK=m
-CONFIG_GREYBUS_POWER=m
-CONFIG_GREYBUS_RAW=m
-CONFIG_GREYBUS_VIBRATOR=m
-CONFIG_GREYBUS_BRIDGED_PHY=m
-CONFIG_GREYBUS_GPIO=m
-CONFIG_GREYBUS_I2C=m
-CONFIG_GREYBUS_PWM=m
-CONFIG_GREYBUS_SDIO=m
-CONFIG_GREYBUS_SPI=m
-CONFIG_GREYBUS_UART=m
-CONFIG_GREYBUS_USB=m
+CONFIG_MOTORCOMM_PHY=m
+CONFIG_MOUSE_APPLETOUCH=m
+CONFIG_MOUSE_BCM5974=m
+CONFIG_MOUSE_CYAPA=m
+CONFIG_MOUSE_ELAN_I2C_I2C=y
+CONFIG_MOUSE_ELAN_I2C=m
+CONFIG_MOUSE_ELAN_I2C_SMBUS=y
+CONFIG_MOUSE_GPIO=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_PIXART=y
+CONFIG_MOUSE_PS2_SENTELIC=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TOUCHKIT=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+CONFIG_MOUSE_PS2_VMMOUSE=y
+CONFIG_MOUSE_SERIAL=m
+CONFIG_MOUSE_SYNAPTICS_I2C=m
+CONFIG_MOUSE_SYNAPTICS_USB=m
+CONFIG_MOUSE_VSXXXAA=m
+CONFIG_MOXA_INTELLIO=m
+CONFIG_MOXA_SMARTIO=m
+CONFIG_MP2629_ADC=m
+CONFIG_MPL115_I2C=m
+CONFIG_MPL115=m
+CONFIG_MPL115_SPI=m
+CONFIG_MPL3115=m
+CONFIG_MPRLS0025PA=m
+CONFIG_MPU3050_I2C=m
+CONFIG_MPU3050=m
+CONFIG_MQ_IOSCHED_KYBER=m
+CONFIG_MS5611_I2C=m
+CONFIG_MS5611=m
+CONFIG_MS5611_SPI=m
+CONFIG_MS5637=m
+CONFIG_MSA311=m
+CONFIG_MS_BLOCK=m
+CONFIG_MSHV_ROOT=m
+CONFIG_MSI_EC=m
+CONFIG_MSI_LAPTOP=m
+CONFIG_MSI_WMI=m
+CONFIG_MSI_WMI_PLATFORM=m
+CONFIG_MSPRO_BLOCK=m
+CONFIG_MT7601U=m
+CONFIG_MT7603E=m
+CONFIG_MT7615_COMMON=m
+CONFIG_MT7615E=m
+CONFIG_MT7663S=m
+CONFIG_MT7663U=m
+CONFIG_MT7663_USB_SDIO_COMMON=m
+CONFIG_MT76_CONNAC_LIB=m
+CONFIG_MT76_CORE=m
+CONFIG_MT76_LEDS=y
+CONFIG_MT76_SDIO=m
+CONFIG_MT76_USB=m
+CONFIG_MT76x02_LIB=m
+CONFIG_MT76x02_USB=m
+CONFIG_MT76x0_COMMON=m
+CONFIG_MT76x0E=m
+CONFIG_MT76x0U=m
+CONFIG_MT76x2_COMMON=m
+CONFIG_MT76x2E=m
+CONFIG_MT76x2U=m
+CONFIG_MT7915E=m
+CONFIG_MT7921_COMMON=m
+CONFIG_MT7921E=m
+CONFIG_MT7921S=m
+CONFIG_MT7921U=m
+CONFIG_MT7925E=m
+CONFIG_MT7925U=m
+CONFIG_MT798X_WMAC=y
+CONFIG_MT7996E=m
+CONFIG_MTD_ABSENT=m
+CONFIG_MTD_AMD76XROM=m
+CONFIG_MTD_AR7_PARTS=m
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK2MTD=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_BLOCK_RO=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI=m
+CONFIG_MTD_CFI_STAA=m
+CONFIG_MTD_CFI_UTIL=m
+CONFIG_MTD_CK804XROM=m
+CONFIG_MTD_CMDLINE_PARTS=m
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_DATAFLASH=m
+CONFIG_MTD_DATAFLASH_OTP=y
+CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
+CONFIG_MTD_DOCG3=m
+CONFIG_MTD_ESB2ROM=m
+CONFIG_MTD_GEN_PROBE=m
+CONFIG_MTD_HYPERBUS=m
+CONFIG_MTD_ICHXROM=m
+CONFIG_MTD_INTEL_DG=m
+CONFIG_MTD_INTEL_VR_NOR=m
+CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_L440GX=m
+CONFIG_MTD_LPDDR=m
+CONFIG_MTD=m
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_MCHP23K256=m
+CONFIG_MTD_MCHP48L640=m
+CONFIG_MTD_MTDRAM=m
+CONFIG_MTD_NAND_ARASAN=m
+CONFIG_MTD_NAND_CAFE=m
+CONFIG_MTD_NAND_CORE=m
+CONFIG_MTD_NAND_DENALI=m
+CONFIG_MTD_NAND_DENALI_PCI=m
+CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
+CONFIG_MTD_NAND_DISKONCHIP=m
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
+CONFIG_MTD_NAND_ECC_MXIC=y
+CONFIG_MTD_NAND_ECC_SW_BCH=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_GPIO=m
+CONFIG_MTD_NAND_MXIC=m
+CONFIG_MTD_NAND_NANDSIM=m
+CONFIG_MTD_NAND_PLATFORM=m
+CONFIG_MTD_NAND_RICOH=m
+CONFIG_MTD_NETtel=m
+CONFIG_MTD_ONENAND_2X_PROGRAM=y
+CONFIG_MTD_ONENAND_GENERIC=m
+CONFIG_MTD_ONENAND=m
+CONFIG_MTD_ONENAND_OTP=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+CONFIG_MTD_OOPS=m
+CONFIG_MTD_PCI=m
+CONFIG_MTD_PCMCIA=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PLATRAM=m
+CONFIG_MTD_PMC551_BUGFIX=y
+CONFIG_MTD_PMC551=m
+CONFIG_MTD_PSTORE=m
+CONFIG_MTD_QINFO_PROBE=m
+CONFIG_MTDRAM_ERASE_SIZE=128
+CONFIG_MTD_RAM=m
+CONFIG_MTDRAM_TOTAL_SIZE=4096
+CONFIG_MTD_RAW_NAND=m
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+CONFIG_MTD_REDBOOT_PARTS=m
+CONFIG_MTD_REDBOOT_PARTS_READONLY=y
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+CONFIG_MTD_ROM=m
+CONFIG_MTD_SBC_GXX=m
+CONFIG_MTD_SCB2_FLASH=m
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_SM_COMMON=m
+CONFIG_MTD_SPI_NAND=m
+CONFIG_MTD_SPI_NOR=m
+CONFIG_MTD_SPI_NOR_SWP_DISABLE=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SST25L=m
+CONFIG_MTD_SWAP=m
+CONFIG_MTD_TESTS=m
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI=m
+CONFIG_MTD_UBI_NVMEM=m
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTK_T7XX=m
+CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0
+CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
+CONFIG_MTRR_SANITIZER=y
+CONFIG_MTRR=y
+CONFIG_MULTIPLEXER=m
+CONFIG_MUSB_PIO_ONLY=y
+CONFIG_MUX_ADG792A=m
+CONFIG_MUX_ADGS1408=m
+CONFIG_MUX_GPIO=m
+CONFIG_MWAVE=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_PCIE=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
+CONFIG_MWL8K=m
+CONFIG_MXC4005=m
+CONFIG_MXC6255=m
+CONFIG_MXM_WMI=m
+CONFIG_NATIONAL_PHY=m
+CONFIG_NAU7802=m
+CONFIG_NCN26000_PHY=m
+CONFIG_ND_BTT=m
+CONFIG_ND_CLAIM=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_NEED_SG_DMA_FLAGS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_9P_FD=m
+CONFIG_NET_9P=m
+CONFIG_NET_9P_RDMA=m
+CONFIG_NET_9P_USBG=y
+CONFIG_NET_9P_VIRTIO=m
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETCONSOLE_EXTENDED_LOG=y
+CONFIG_NETCONSOLE=m
+CONFIG_NET_DEVLINK=y
+CONFIG_NETDEVSIM=m
+CONFIG_NET_FAILOVER=m
+CONFIG_NET_FC=y
+CONFIG_NET_IFE=m
+CONFIG_NETKIT=y
+CONFIG_NET_POLL_CONTROLLER=y
+CONFIG_NETPOLL=y
+CONFIG_NET_SELFTESTS=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_NET_TEAM_MODE_RANDOM=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NEW_LEDS=y
+CONFIG_NFC_DIGITAL=m
+CONFIG_NFC_FDP_I2C=m
+CONFIG_NFC_FDP=m
+CONFIG_NFC_HCI=m
+CONFIG_NFC=m
+CONFIG_NFC_MEI_PHY=m
+CONFIG_NFC_MICROREAD_I2C=m
+CONFIG_NFC_MICROREAD=m
+CONFIG_NFC_MICROREAD_MEI=m
+CONFIG_NFC_MRVL_I2C=m
+CONFIG_NFC_MRVL=m
+CONFIG_NFC_MRVL_SPI=m
+CONFIG_NFC_MRVL_UART=m
+CONFIG_NFC_MRVL_USB=m
+CONFIG_NFC_NCI=m
+CONFIG_NFC_NCI_SPI=m
+CONFIG_NFC_NCI_UART=m
+CONFIG_NFC_NXP_NCI_I2C=m
+CONFIG_NFC_NXP_NCI=m
+CONFIG_NFC_PN532_UART=m
+CONFIG_NFC_PN533_I2C=m
+CONFIG_NFC_PN533=m
+CONFIG_NFC_PN533_USB=m
+CONFIG_NFC_PN544_I2C=m
+CONFIG_NFC_PN544=m
+CONFIG_NFC_PN544_MEI=m
+CONFIG_NFC_PORT100=m
+CONFIG_NFC_S3FWRN5_I2C=m
+CONFIG_NFC_S3FWRN5=m
+CONFIG_NFC_S3FWRN82_UART=m
+CONFIG_NFC_SHDLC=y
+CONFIG_NFC_SIM=m
+CONFIG_NFC_ST21NFCA_I2C=m
+CONFIG_NFC_ST21NFCA=m
+CONFIG_NFC_ST95HF=m
+CONFIG_NFC_ST_NCI_I2C=m
+CONFIG_NFC_ST_NCI=m
+CONFIG_NFC_ST_NCI_SPI=m
+CONFIG_NFC_TRF7970A=m
+CONFIG_NFC_VIRTUAL_NCI=m
+CONFIG_NFTL=m
+CONFIG_NFTL_RW=y
+CONFIG_N_GSM=m
+CONFIG_N_HDLC=m
+CONFIG_NI903X_WDT=m
+CONFIG_NIC7018_WDT=m
+CONFIG_NITRO_ENCLAVES=m
+CONFIG_NL80211_TESTMODE=y
+CONFIG_NLMON=m
+CONFIG_NOA1305=m
+CONFIG_NODES_SHIFT=10
+CONFIG_NO_HZ_FULL=y
+CONFIG_NO_HZ=y
+CONFIG_NOP_USB_XCEIV=m
+CONFIG_NORTEL_HERMES=m
+CONFIG_NOUVEAU_DEBUG=3
+CONFIG_NOUVEAU_DEBUG_DEFAULT=1
+CONFIG_NOZOMI=m
+CONFIG_NR_CPUS=8192
+CONFIG_NR_CPUS_DEFAULT=8192
+CONFIG_NR_CPUS_RANGE_BEGIN=8192
+CONFIG_NR_CPUS_RANGE_END=8192
+CONFIG_NSM=m
+CONFIG_NTB_AMD=m
+CONFIG_NTB_EPF=m
+CONFIG_NTB_IDT=m
+CONFIG_NTB_INTEL=m
+CONFIG_NTB=m
+CONFIG_NTB_MSI_TEST=m
+CONFIG_NTB_MSI=y
+CONFIG_NTB_NETDEV=m
+CONFIG_NTB_PERF=m
+CONFIG_NTB_PINGPONG=m
+CONFIG_NTB_SWITCHTEC=m
+CONFIG_NTB_TOOL=m
+CONFIG_NTB_TRANSPORT=m
+CONFIG_NULL_TTY=m
+CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
+CONFIG_NUMA_BALANCING=y
+CONFIG_NUMA_KEEP_MEMINFO=y
+CONFIG_NUMA=y
+CONFIG_NVDIMM_KEYS=y
+CONFIG_NVGRACE_GPU_VFIO_PCI=m
+CONFIG_NVIDIA_WMI_EC_BACKLIGHT=m
+CONFIG_NVMEM_LAYOUT_ONIE_TLV=m
+CONFIG_NVMEM_LAYOUT_SL28_VPD=m
+CONFIG_NVMEM_RAVE_SP_EEPROM=m
+CONFIG_NVMEM_RMEM=m
+CONFIG_NVMEM_SPMI_SDAM=m
+CONFIG_NVRAM=m
+CONFIG_NVSW_SN2201=m
+CONFIG_NV_TCO=m
+CONFIG_NXP_C45_TJA11XX_PHY=m
+CONFIG_NXP_CBTX_PHY=m
+CONFIG_NXP_TJA11XX_PHY=m
+CONFIG_OBJAGG=m
+CONFIG_OCTEONEP_VDPA=m
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OPT3001=m
+CONFIG_OPT4001=m
+CONFIG_OPT4060=m
+CONFIG_OPTPROBES=y
+CONFIG_ORINOCO_USB=m
+CONFIG_OSF_PARTITION=y
+CONFIG_OUTPUT_FORMAT="elf64-x86-64"
+CONFIG_OVPN=m
+CONFIG_OXP_EC=m
+CONFIG_P2SB=y
+CONFIG_P54_COMMON=m
+CONFIG_P54_LEDS=y
+CONFIG_P54_PCI=m
+CONFIG_P54_SPI_DEFAULT_EEPROM=y
+CONFIG_P54_SPI=m
+CONFIG_P54_USB=m
+CONFIG_PA12203001=m
+CONFIG_PAC1921=m
+CONFIG_PAC1934=m
+CONFIG_PACKING=y
+CONFIG_PADATA=y
+CONFIG_PAGE_BLOCK_MAX_ORDER=10
+CONFIG_PAGE_BLOCK_ORDER=10
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_TABLE_ISOLATION=y
+CONFIG_PAHOLE_VERSION=125
+CONFIG_PALMAS_GPADC=m
+CONFIG_PANASONIC_LAPTOP=m
+CONFIG_PANEL=m
+CONFIG_PANEL_PARPORT=0
+CONFIG_PANEL_PROFILE=5
+CONFIG_PANIC_TIMEOUT=60
+CONFIG_PARAVIRT_CLOCK=y
+CONFIG_PARAVIRT=y
+CONFIG_PARMAN=m
+CONFIG_PARPORT_1284=y
+CONFIG_PARPORT=m
+CONFIG_PARPORT_NOT_PC=y
+CONFIG_PARPORT_PANEL=m
+CONFIG_PARPORT_PC_FIFO=y
+CONFIG_PARPORT_PC=m
+CONFIG_PARPORT_PC_PCMCIA=m
+CONFIG_PARPORT_PC_SUPERIO=y
+CONFIG_PARPORT_SERIAL=m
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PATA_ACPI=m
+CONFIG_PATA_ALI=m
+CONFIG_PATA_AMD=m
+CONFIG_PATA_ARTOP=m
+CONFIG_PATA_ATIIXP=m
+CONFIG_PATA_ATP867X=m
+CONFIG_PATA_CMD640_PCI=m
+CONFIG_PATA_CMD64X=m
+CONFIG_PATA_CYPRESS=m
+CONFIG_PATA_EFAR=m
+CONFIG_PATA_HPT366=m
+CONFIG_PATA_HPT37X=m
+CONFIG_PATA_HPT3X2N=m
+CONFIG_PATA_HPT3X3_DMA=y
+CONFIG_PATA_HPT3X3=m
+CONFIG_PATA_IT8213=m
+CONFIG_PATA_IT821X=m
+CONFIG_PATA_JMICRON=m
+CONFIG_PATA_LEGACY=m
+CONFIG_PATA_MARVELL=m
+CONFIG_PATA_MPIIX=m
+CONFIG_PATA_NETCELL=m
+CONFIG_PATA_NINJA32=m
+CONFIG_PATA_NS87410=m
+CONFIG_PATA_NS87415=m
+CONFIG_PATA_OLDPIIX=m
+CONFIG_PATA_OPTIDMA=m
+CONFIG_PATA_OPTI=m
+CONFIG_PATA_PARPORT_ATEN=m
+CONFIG_PATA_PARPORT_BPCK6=m
+CONFIG_PATA_PARPORT_BPCK=m
+CONFIG_PATA_PARPORT_COMM=m
+CONFIG_PATA_PARPORT_DSTR=m
+CONFIG_PATA_PARPORT_EPATC8=y
+CONFIG_PATA_PARPORT_EPAT=m
+CONFIG_PATA_PARPORT_EPIA=m
+CONFIG_PATA_PARPORT_FIT2=m
+CONFIG_PATA_PARPORT_FIT3=m
+CONFIG_PATA_PARPORT_FRIQ=m
+CONFIG_PATA_PARPORT_FRPW=m
+CONFIG_PATA_PARPORT_KBIC=m
+CONFIG_PATA_PARPORT_KTTI=m
+CONFIG_PATA_PARPORT=m
+CONFIG_PATA_PARPORT_ON20=m
+CONFIG_PATA_PARPORT_ON26=m
+CONFIG_PATA_PCMCIA=m
+CONFIG_PATA_PDC2027X=m
+CONFIG_PATA_PDC_OLD=m
+CONFIG_PATA_RADISYS=m
+CONFIG_PATA_RDC=m
+CONFIG_PATA_RZ1000=m
+CONFIG_PATA_SCH=m
+CONFIG_PATA_SERVERWORKS=m
+CONFIG_PATA_SIL680=m
+CONFIG_PATA_SIS=m
+CONFIG_PATA_TIMINGS=y
+CONFIG_PATA_TOSHIBA=m
+CONFIG_PATA_TRIFLEX=m
+CONFIG_PATA_VIA=m
+CONFIG_PATA_WINBOND=m
+CONFIG_PC300TOO=m
+CONFIG_PC87413_WDT=m
+CONFIG_PCCARD=m
+CONFIG_PCCARD_NONSTATIC=y
+CONFIG_PCC=y
+CONFIG_PCENGINES_APU2=m
+CONFIG_PCF50633_ADC=m
+CONFIG_PCF50633_GPIO=m
+CONFIG_PCI200SYN=m
+CONFIG_PCI_ATMEL=m
+CONFIG_PCI_ATS=y
+CONFIG_PCI_DIRECT=y
+CONFIG_PCI_DOE=y
+CONFIG_PCI_DYNAMIC_OF_NODES=y
+CONFIG_PCIEAER_CXL=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM_DEFAULT=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIE_BUS_DEFAULT=y
+CONFIG_PCIE_DPC=y
+CONFIG_PCIE_ECRC=y
+CONFIG_PCIE_EDR=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_ENDPOINT_MSI_DOORBELL=y
+CONFIG_PCI_ENDPOINT_TEST=m
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_EPF_MHI=m
+CONFIG_PCI_EPF_NTB=m
+CONFIG_PCI_EPF_VNTB=m
+CONFIG_PCIE_PME=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_PTM=y
+CONFIG_PCI_HERMES=m
+CONFIG_PCI_HYPERV_INTERFACE=m
+CONFIG_PCI_HYPERV=m
+CONFIG_PCI_IOV=y
+CONFIG_PCI_LABEL=y
+CONFIG_PCI_LOCKLESS_CONFIG=y
+CONFIG_PCI_MMCONFIG=y
+CONFIG_PCI_PASID=y
+CONFIG_PCIPCWATCHDOG=m
+CONFIG_PCI_PF_STUB=m
+CONFIG_PCI_PRI=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCI_STUB=m
+CONFIG_PCI_SW_SWITCHTEC=m
+CONFIG_PCMCIA_AHA152X=m
+CONFIG_PCMCIA_ATMEL=m
+CONFIG_PCMCIA_FDOMAIN=m
+CONFIG_PCMCIA_HERMES=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_QLOGIC=m
+CONFIG_PCMCIA_RAYCS=m
+CONFIG_PCMCIA_SPECTRUM=m
+CONFIG_PCMCIA_SYM53C500=m
+CONFIG_PCMCIA_WL3501=m
+CONFIG_PCS_LYNX=m
+CONFIG_PCS_MTK_LYNXI=m
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_PCS_XPCS=m
+CONFIG_PD6729=m
+CONFIG_PDC_ADMA=m
+CONFIG_PDS_VDPA=m
+CONFIG_PDS_VFIO_PCI=m
+CONFIG_PECI_CPU=m
+CONFIG_PECI=m
+CONFIG_PECI_NPCM=m
+CONFIG_PERF_EVENTS_AMD_BRS=y
+CONFIG_PERF_EVENTS_AMD_POWER=m
+CONFIG_PERF_EVENTS_AMD_UNCORE=m
+CONFIG_PERF_EVENTS_INTEL_CSTATE=m
+CONFIG_PERF_EVENTS_INTEL_RAPL=m
+CONFIG_PERF_EVENTS_INTEL_UNCORE=m
+CONFIG_PERSISTENT_KEYRINGS=y
+CONFIG_PER_VMA_LOCK=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHANTOM=m
+CONFIG_PHY_CAN_TRANSCEIVER=m
+CONFIG_PHY_CPCAP_USB=m
+CONFIG_PHY_INTEL_LGM_EMMC=m
+CONFIG_PHY_PXA_28NM_HSIC=m
+CONFIG_PHY_PXA_28NM_USB2=m
+CONFIG_PHY_QCOM_USB_HSIC=m
+CONFIG_PHY_QCOM_USB_HS=m
+CONFIG_PHY_RTK_RTD_USB2PHY=m
+CONFIG_PHY_RTK_RTD_USB3PHY=m
+CONFIG_PHY_SAMSUNG_USB2=m
+CONFIG_PHYSICAL_ALIGN=0x1000000
+CONFIG_PHYSICAL_START=0x1000000
+CONFIG_PHY_TUSB1210=m
 CONFIG_PI433=m
-CONFIG_FIELDBUS_DEV=m
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_ALDERLAKE=m
+CONFIG_PINCTRL_AMDISP=m
+CONFIG_PINCTRL_AMD=y
+CONFIG_PINCTRL_BAYTRAIL=y
+CONFIG_PINCTRL_BROXTON=m
+CONFIG_PINCTRL_CANNONLAKE=m
+CONFIG_PINCTRL_CEDARFORK=m
+CONFIG_PINCTRL_CHERRYVIEW=m
+CONFIG_PINCTRL_CS42L43=m
+CONFIG_PINCTRL_CS47L15=y
+CONFIG_PINCTRL_CS47L35=y
+CONFIG_PINCTRL_CS47L85=y
+CONFIG_PINCTRL_CS47L90=y
+CONFIG_PINCTRL_CS47L92=y
+CONFIG_PINCTRL_CY8C95X0=m
+CONFIG_PINCTRL_DA9062=m
+CONFIG_PINCTRL_DENVERTON=m
+CONFIG_PINCTRL_ELKHARTLAKE=m
+CONFIG_PINCTRL_EMMITSBURG=m
+CONFIG_PINCTRL_GEMINILAKE=m
+CONFIG_PINCTRL_ICELAKE=m
+CONFIG_PINCTRL_IMX_SCMI=m
+CONFIG_PINCTRL_INTEL_PLATFORM=m
+CONFIG_PINCTRL_INTEL=y
+CONFIG_PINCTRL_JASPERLAKE=m
+CONFIG_PINCTRL_LAKEFIELD=m
+CONFIG_PINCTRL_LEWISBURG=m
+CONFIG_PINCTRL_LYNXPOINT=m
+CONFIG_PINCTRL_MADERA=m
+CONFIG_PINCTRL_MAX7360=m
+CONFIG_PINCTRL_MCP23S08_I2C=m
+CONFIG_PINCTRL_MCP23S08=m
+CONFIG_PINCTRL_MCP23S08_SPI=m
+CONFIG_PINCTRL_METEORLAKE=m
+CONFIG_PINCTRL_METEORPOINT=m
+CONFIG_PINCTRL_SUNRISEPOINT=m
+CONFIG_PINCTRL_SX150X=y
+CONFIG_PINCTRL_TIGERLAKE=m
+CONFIG_PINCTRL_TPS6594=m
+CONFIG_PINCTRL_UPBOARD=m
+CONFIG_PINCTRL=y
+CONFIG_PING=m
+CONFIG_PINMUX=y
+CONFIG_PKCS7_TEST_KEY=m
+CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
+CONFIG_PLATFORM_SI4713=m
+CONFIG_PLDMFW=y
+CONFIG_PLFXLC=m
+CONFIG_PLIP=m
+CONFIG_PLX_DMA=m
+CONFIG_PLX_HERMES=m
+CONFIG_PM_AUTOSLEEP=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PMIC_ADP5520=y
+CONFIG_PMIC_DA903X=y
+CONFIG_PMIC_DA9052=y
+CONFIG_PMIC_OPREGION=y
+CONFIG_PM_OPP=y
+CONFIG_PMS7003=m
+CONFIG_PM_STD_PARTITION=""
+CONFIG_PM_WAKELOCKS_GC=y
+CONFIG_PM_WAKELOCKS_LIMIT=100
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PNPACPI=y
+CONFIG_PNP=y
+CONFIG_POLYNOMIAL=m
+CONFIG_PORTWELL_EC=m
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWERCAP=y
+CONFIG_POWER_RESET_ATC260X=m
+CONFIG_POWER_RESET_MT6323=y
+CONFIG_POWER_RESET_TPS65086=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPDEV=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOATM=m
+CONFIG_PPPOE_HASH_BITS=4
+CONFIG_PPPOE_HASH_BITS_4=y
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPS_CLIENT_GPIO=m
+CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PPS_CLIENT_PARPORT=m
+CONFIG_PPS=y
+CONFIG_PPTP=m
+CONFIG_PREEMPT_BUILD=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_PREEMPT_DYNAMIC=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_PREEMPT_RCU=y
+CONFIG_PREEMPT=y
+CONFIG_PREFIX_SYMBOLS=y
+CONFIG_PRIME_NUMBERS=m
+CONFIG_PRINTER=m
+CONFIG_PRINTK_INDEX=y
+CONFIG_PRISM2_USB=m
+CONFIG_PROCESSOR_SELECT=y
+CONFIG_PROC_THERMAL_MMIO_RAPL=m
+CONFIG_PSAMPLE=m
+CONFIG_PSE_CONTROLLER=y
+CONFIG_PSE_PD692X0=m
+CONFIG_PSE_REGULATOR=m
+CONFIG_PSE_SI3474=m
+CONFIG_PSE_TPS23881=m
+CONFIG_PSI=y
+CONFIG_PTDUMP_CORE=y
+CONFIG_PTE_MARKER_UFFD_WP=y
+CONFIG_PTP_1588_CLOCK_FC3W=m
+CONFIG_PTP_1588_CLOCK_IDT82P33=m
+CONFIG_PTP_1588_CLOCK_IDTCM=m
+CONFIG_PTP_1588_CLOCK_INES=m
+CONFIG_PTP_1588_CLOCK_KVM=m
+CONFIG_PTP_1588_CLOCK_MOCK=m
+CONFIG_PTP_1588_CLOCK_OCP=m
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PTP_1588_CLOCK_QORIQ=m
+CONFIG_PTP_1588_CLOCK_VMW=m
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_DFL_TOD=m
+CONFIG_PTP_NETC_V4_TIMER=m
+CONFIG_PT_RECLAIM=y
+CONFIG_PVH=y
+CONFIG_PVPANIC_MMIO=m
+CONFIG_PVPANIC_PCI=m
+CONFIG_PVPANIC=y
+CONFIG_PWM_CLK=m
+CONFIG_PWM_CROS_EC=m
+CONFIG_PWM_DWC=m
+CONFIG_PWM_GPIO=m
+CONFIG_PWM_IQS620A=m
+CONFIG_PWM_LP3943=m
+CONFIG_PWM_LPSS=m
+CONFIG_PWM_LPSS_PCI=m
+CONFIG_PWM_LPSS_PLATFORM=m
+CONFIG_PWM_MAX7360=m
+CONFIG_PWM_PCA9685=m
+CONFIG_PWM_PROVIDE_GPIO=y
+CONFIG_PWM_SYSFS=y
+CONFIG_PWM_TWL_LED=m
+CONFIG_PWM_TWL=m
+CONFIG_PWM=y
+CONFIG_QAT_VFIO_PCI=m
+CONFIG_QCA807X_PHY=m
+CONFIG_QCA808X_PHY=m
+CONFIG_QCA83XX_PHY=m
+CONFIG_QCOM_HIDMA=m
+CONFIG_QCOM_HIDMA_MGMT=m
+CONFIG_QCOM_PBS=m
+CONFIG_QCOM_QMI_HELPERS=m
+CONFIG_QCOM_SPMI_ADC5=m
+CONFIG_QCOM_SPMI_IADC=m
+CONFIG_QCOM_SPMI_VADC=m
+CONFIG_QCOMTEE=m
+CONFIG_QCOM_TZMEM_MODE_GENERIC=y
+CONFIG_QCOM_VADC_COMMON=m
+CONFIG_QEDF=m
 CONFIG_QLGE=m
-CONFIG_WFX=m
-CONFIG_RTL8723CS=m
-CONFIG_X86_PLATFORM_DEVICES=y
-CONFIG_ACPI_WMI=m
-CONFIG_WMI_BMOF=m
-CONFIG_HUAWEI_WMI=m
-CONFIG_MXM_WMI=m
-CONFIG_PEAQ_WMI=m
-CONFIG_NVIDIA_WMI_EC_BACKLIGHT=m
-CONFIG_XIAOMI_WMI=m
-CONFIG_GIGABYTE_WMI=m
-CONFIG_YOGABOOK_WMI=m
-CONFIG_ACERHDF=m
-CONFIG_ACER_WIRELESS=m
-CONFIG_ACER_WMI=m
-CONFIG_AMD_PMF=m
-CONFIG_AMD_PMC=m
-CONFIG_AMD_HSMP=m
-CONFIG_ADV_SWBUTTON=m
-CONFIG_APPLE_GMUX=m
-CONFIG_ASUS_LAPTOP=m
-CONFIG_ASUS_WIRELESS=m
-CONFIG_ASUS_WMI=m
-CONFIG_ASUS_NB_WMI=m
-CONFIG_ASUS_TF103C_DOCK=m
-CONFIG_MERAKI_MX100=m
-CONFIG_EEEPC_LAPTOP=m
-CONFIG_EEEPC_WMI=m
-CONFIG_X86_PLATFORM_DRIVERS_DELL=y
-CONFIG_ALIENWARE_WMI=m
-CONFIG_DCDBAS=m
-CONFIG_DELL_LAPTOP=m
-CONFIG_DELL_RBU=m
-CONFIG_DELL_RBTN=m
-CONFIG_DELL_SMBIOS=m
-CONFIG_DELL_SMBIOS_WMI=y
-CONFIG_DELL_SMBIOS_SMM=y
-CONFIG_DELL_SMO8800=m
-CONFIG_DELL_WMI=m
-CONFIG_DELL_WMI_PRIVACY=y
-CONFIG_DELL_WMI_AIO=m
-CONFIG_DELL_WMI_DESCRIPTOR=m
-CONFIG_DELL_WMI_LED=m
-CONFIG_DELL_WMI_SYSMAN=m
-CONFIG_AMILO_RFKILL=m
-CONFIG_FUJITSU_LAPTOP=m
-CONFIG_FUJITSU_TABLET=m
-CONFIG_GPD_POCKET_FAN=m
-CONFIG_HP_ACCEL=m
-CONFIG_WIRELESS_HOTKEY=m
-CONFIG_HP_WMI=m
-CONFIG_IBM_RTL=m
-CONFIG_IDEAPAD_LAPTOP=m
-CONFIG_SENSORS_HDAPS=m
-CONFIG_THINKPAD_ACPI=m
-CONFIG_THINKPAD_ACPI_ALSA_SUPPORT=y
-# CONFIG_THINKPAD_ACPI_DEBUGFACILITIES is not set
-# CONFIG_THINKPAD_ACPI_DEBUG is not set
-# CONFIG_THINKPAD_ACPI_UNSAFE_LEDS is not set
-CONFIG_THINKPAD_ACPI_VIDEO=y
-CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y
-CONFIG_THINKPAD_LMI=m
-CONFIG_INTEL_ATOMISP2_PDX86=y
-CONFIG_INTEL_ATOMISP2_LED=m
-CONFIG_INTEL_SAR_INT1092=m
-CONFIG_INTEL_CHT_INT33FE=m
-CONFIG_INTEL_SKL_INT3472=m
-CONFIG_INTEL_PMC_CORE=y
-CONFIG_INTEL_PMT_CLASS=m
-CONFIG_INTEL_PMT_TELEMETRY=m
-CONFIG_INTEL_PMT_CRASHLOG=m
-
-#
-# Intel Speed Select Technology interface support
-#
-CONFIG_INTEL_SPEED_SELECT_INTERFACE=m
-# end of Intel Speed Select Technology interface support
-
-CONFIG_INTEL_TELEMETRY=m
-CONFIG_INTEL_WMI=y
-CONFIG_INTEL_WMI_SBL_FW_UPDATE=m
-CONFIG_INTEL_WMI_THUNDERBOLT=m
-CONFIG_INTEL_HID_EVENT=m
-CONFIG_INTEL_VBTN=m
-CONFIG_INTEL_INT0002_VGPIO=m
-CONFIG_INTEL_OAKTRAIL=m
-CONFIG_INTEL_BXTWC_PMIC_TMU=m
-CONFIG_INTEL_CHTWC_INT33FE=m
-CONFIG_INTEL_CHTDC_TI_PWRBTN=m
-CONFIG_INTEL_ISHTP_ECLITE=m
-CONFIG_INTEL_MRFLD_PWRBTN=m
-CONFIG_INTEL_PUNIT_IPC=m
-CONFIG_INTEL_RST=m
-CONFIG_INTEL_SDSI=m
-CONFIG_INTEL_SMARTCONNECT=m
-CONFIG_INTEL_VSEC=m
-CONFIG_INTEL_TURBO_MAX_3=y
-CONFIG_INTEL_UNCORE_FREQ_CONTROL=m
-CONFIG_MSI_LAPTOP=m
-CONFIG_MSI_WMI=m
-CONFIG_PCENGINES_APU2=m
-CONFIG_BARCO_P50_GPIO=m
-CONFIG_SAMSUNG_LAPTOP=m
-CONFIG_SAMSUNG_Q10=m
-CONFIG_ACPI_TOSHIBA=m
-CONFIG_TOSHIBA_BT_RFKILL=m
-CONFIG_TOSHIBA_HAPS=m
-CONFIG_TOSHIBA_WMI=m
-CONFIG_ACPI_CMPC=m
-CONFIG_COMPAL_LAPTOP=m
-CONFIG_LG_LAPTOP=m
-CONFIG_PANASONIC_LAPTOP=m
-CONFIG_SONY_LAPTOP=m
-CONFIG_SONYPI_COMPAT=y
-CONFIG_SYSTEM76_ACPI=m
-CONFIG_TOPSTAR_LAPTOP=m
-CONFIG_SERIAL_MULTI_INSTANTIATE=m
-CONFIG_I2C_MULTI_INSTANTIATE=m
-CONFIG_MLX_PLATFORM=m
-CONFIG_X86_ANDROID_TABLETS=m
-CONFIG_FW_ATTR_CLASS=m
-CONFIG_INTEL_IPS=m
-CONFIG_INTEL_SCU_IPC=y
-CONFIG_SIEMENS_SIMATIC_IPC=m
-CONFIG_INTEL_SCU=y
-CONFIG_INTEL_SCU_PCI=y
-CONFIG_INTEL_SCU_PLATFORM=m
-CONFIG_INTEL_SCU_IPC_UTIL=m
-CONFIG_PMC_ATOM=y
-CONFIG_CHROME_PLATFORMS=y
-CONFIG_CHROMEOS_LAPTOP=m
-CONFIG_CHROMEOS_PSTORE=m
-CONFIG_CHROMEOS_TBMC=m
-CONFIG_CROS_EC=m
-CONFIG_CROS_EC_I2C=m
-CONFIG_CROS_EC_ISHTP=m
-CONFIG_CROS_EC_SPI=m
-CONFIG_CROS_EC_LPC=m
-CONFIG_CROS_EC_PROTO=y
-CONFIG_CROS_KBD_LED_BACKLIGHT=m
-CONFIG_CROS_EC_CHARDEV=m
-CONFIG_CROS_EC_LIGHTBAR=m
-CONFIG_CROS_EC_DEBUGFS=m
-CONFIG_CROS_EC_SENSORHUB=m
-CONFIG_CROS_EC_SYSFS=m
-CONFIG_CROS_EC_TYPEC=m
-CONFIG_CROS_USBPD_LOGGER=m
-CONFIG_CROS_USBPD_NOTIFY=m
-CONFIG_CHROMEOS_PRIVACY_SCREEN=m
-CONFIG_CROS_TYPEC_SWITCH=m
-CONFIG_WILCO_EC=m
-CONFIG_WILCO_EC_DEBUGFS=m
-CONFIG_WILCO_EC_EVENTS=m
-CONFIG_WILCO_EC_TELEMETRY=m
-CONFIG_MELLANOX_PLATFORM=y
-CONFIG_MLXREG_HOTPLUG=m
-CONFIG_MLXREG_IO=m
-CONFIG_MLXREG_LC=m
-CONFIG_SURFACE_PLATFORMS=y
-CONFIG_SURFACE3_WMI=m
-CONFIG_SURFACE_3_BUTTON=m
-CONFIG_SURFACE_3_POWER_OPREGION=m
-CONFIG_SURFACE_ACPI_NOTIFY=m
-CONFIG_SURFACE_AGGREGATOR_CDEV=m
-CONFIG_SURFACE_AGGREGATOR_HUB=m
-CONFIG_SURFACE_AGGREGATOR_REGISTRY=m
-CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m
-CONFIG_SURFACE_DTX=m
-CONFIG_SURFACE_GPE=m
-CONFIG_SURFACE_HOTPLUG=m
-CONFIG_SURFACE_PLATFORM_PROFILE=m
-CONFIG_SURFACE_PRO3_BUTTON=m
-CONFIG_SURFACE_AGGREGATOR=m
-CONFIG_SURFACE_AGGREGATOR_BUS=y
-# CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION is not set
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_WM831X=m
-CONFIG_LMK04832=m
-CONFIG_COMMON_CLK_APPLE_NCO=m
-CONFIG_COMMON_CLK_MAX9485=m
-CONFIG_COMMON_CLK_SI5341=m
-CONFIG_COMMON_CLK_SI5351=m
-CONFIG_COMMON_CLK_SI544=m
-CONFIG_COMMON_CLK_CDCE706=m
-CONFIG_COMMON_CLK_TPS68470=m
-CONFIG_COMMON_CLK_CS2000_CP=m
-CONFIG_COMMON_CLK_PWM=m
-CONFIG_COMMON_CLK_RS9_PCIE=m
-# CONFIG_XILINX_VCU is not set
-CONFIG_HWSPINLOCK=y
-
-#
-# Clock Source drivers
-#
-CONFIG_CLKEVT_I8253=y
-CONFIG_I8253_LOCK=y
-CONFIG_CLKBLD_I8253=y
-# end of Clock Source drivers
-
-CONFIG_MAILBOX=y
-CONFIG_PCC=y
-CONFIG_ALTERA_MBOX=m
-CONFIG_IOMMU_IOVA=y
-CONFIG_IOASID=y
-CONFIG_IOMMU_API=y
-CONFIG_IOMMU_SUPPORT=y
-
-#
-# Generic IOMMU Pagetable Support
-#
-CONFIG_IOMMU_IO_PGTABLE=y
-# end of Generic IOMMU Pagetable Support
-
-# CONFIG_IOMMU_DEBUGFS is not set
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_IOMMU_DMA=y
-CONFIG_IOMMU_SVA_LIB=y
-CONFIG_AMD_IOMMU=y
-CONFIG_AMD_IOMMU_V2=m
-CONFIG_DMAR_TABLE=y
-CONFIG_INTEL_IOMMU=y
-CONFIG_INTEL_IOMMU_SVM=y
-# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set
-CONFIG_INTEL_IOMMU_FLOPPY_WA=y
-# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set
-CONFIG_IRQ_REMAP=y
-CONFIG_HYPERV_IOMMU=y
-CONFIG_VIRTIO_IOMMU=m
-
-#
-# Remoteproc drivers
-#
-# CONFIG_REMOTEPROC is not set
-# end of Remoteproc drivers
-
-#
-# Rpmsg drivers
-#
-CONFIG_RPMSG=m
+CONFIG_QSEMI_PHY=m
+CONFIG_QTNFMAC=m
+CONFIG_QTNFMAC_PCIE=m
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_R8712U=m
+CONFIG_RADIO_ADAPTERS=m
+CONFIG_RADIO_MAXIRADIO=m
+CONFIG_RADIO_SAA7706H=m
+CONFIG_RADIO_SHARK2=m
+CONFIG_RADIO_SHARK=m
+CONFIG_RADIO_SI470X=m
+CONFIG_RADIO_SI4713=m
+CONFIG_RADIO_SI476X=m
+CONFIG_RADIO_TEA575X=m
+CONFIG_RADIO_TEA5764=m
+CONFIG_RADIO_TEF6862=m
+CONFIG_RADIO_WL1273=m
+CONFIG_RADIO_WL128X=m
+CONFIG_RAID6_PQ_BENCHMARK=y
+CONFIG_RAID6_PQ=m
+CONFIG_RAID_ATTRS=m
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y
+CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa
+CONFIG_RANDOMIZE_MEMORY=y
+CONFIG_RAPIDIO_CHMAN=m
+CONFIG_RAPIDIO_CPS_GEN2=m
+CONFIG_RAPIDIO_CPS_XX=m
+CONFIG_RAPIDIO_DISC_TIMEOUT=30
+CONFIG_RAPIDIO_DMA_ENGINE=y
+CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y
+CONFIG_RAPIDIO_ENUM_BASIC=m
+CONFIG_RAPIDIO=m
+CONFIG_RAPIDIO_MPORT_CDEV=m
+CONFIG_RAPIDIO_RXS_GEN3=m
+CONFIG_RAPIDIO_TSI721=m
+CONFIG_RAS_FMPM=m
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RAVE_SP_CORE=m
+CONFIG_RAVE_SP_WATCHDOG=m
+CONFIG_RC_ATI_REMOTE=m
+CONFIG_RC_CORE=m
+CONFIG_RC_DECODERS=y
+CONFIG_RC_DEVICES=y
+CONFIG_RC_LOOPBACK=m
+CONFIG_RC_MAP=m
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_LAZY=y
+CONFIG_RC_XBOX_DVD=m
+CONFIG_RD_BZIP2=y
+CONFIG_RDMA_RXE=m
+CONFIG_RDMA_SIW=m
+CONFIG_REALTEK_AUTOPM=y
+CONFIG_REALTEK_PHY=m
+CONFIG_REDMI_WMI=m
+CONFIG_REED_SOLOMON_DEC16=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REED_SOLOMON=m
+CONFIG_REGMAP_I2C=m
+CONFIG_REGMAP_I3C=m
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SCCB=m
+CONFIG_REGMAP_SLIMBUS=m
+CONFIG_REGMAP_SOUNDWIRE=m
+CONFIG_REGMAP_SOUNDWIRE_MBQ=m
+CONFIG_REGMAP_SPI_AVMM=m
+CONFIG_REGMAP_SPI=y
+CONFIG_REGMAP_SPMI=m
+CONFIG_REGMAP_W1=m
+CONFIG_REGULATOR_88PG86X=m
+CONFIG_REGULATOR_88PM800=m
+CONFIG_REGULATOR_88PM8607=m
+CONFIG_REGULATOR_88PM886=m
+CONFIG_REGULATOR_AAT2870=m
+CONFIG_REGULATOR_ACT8865=m
+CONFIG_REGULATOR_AD5398=m
+CONFIG_REGULATOR_ADP5055=m
+CONFIG_REGULATOR_ARIZONA_LDO1=m
+CONFIG_REGULATOR_ARIZONA_MICSUPP=m
+CONFIG_REGULATOR_AS3711=m
+CONFIG_REGULATOR_ATC260X=m
+CONFIG_REGULATOR_AW37503=m
+CONFIG_REGULATOR_AXP20X=m
+CONFIG_REGULATOR_BCM590XX=m
+CONFIG_REGULATOR_BD9571MWV=m
+CONFIG_REGULATOR_DA903X=m
+CONFIG_REGULATOR_DA9052=m
+CONFIG_REGULATOR_DA9055=m
+CONFIG_REGULATOR_DA9062=m
+CONFIG_REGULATOR_DA9210=m
+CONFIG_REGULATOR_DA9211=m
+CONFIG_REGULATOR_FAN53555=m
+CONFIG_REGULATOR_FIXED_VOLTAGE=m
+CONFIG_REGULATOR_GPIO=m
+CONFIG_REGULATOR_ISL6271A=m
+CONFIG_REGULATOR_ISL9305=m
+CONFIG_REGULATOR_LM363X=m
+CONFIG_REGULATOR_LP3971=m
+CONFIG_REGULATOR_LP3972=m
+CONFIG_REGULATOR_LP872X=m
+CONFIG_REGULATOR_LP8755=m
+CONFIG_REGULATOR_LP8788=m
+CONFIG_REGULATOR_LTC3589=m
+CONFIG_REGULATOR_LTC3676=m
+CONFIG_REGULATOR_MAX14577=m
+CONFIG_REGULATOR_MAX1586=m
+CONFIG_REGULATOR_MAX20086=m
+CONFIG_REGULATOR_MAX20411=m
+CONFIG_REGULATOR_MAX5970=m
+CONFIG_REGULATOR_MAX77503=m
+CONFIG_REGULATOR_MAX77541=m
+CONFIG_REGULATOR_MAX77693=m
+CONFIG_REGULATOR_MAX77826=m
+CONFIG_REGULATOR_MAX77838=m
+CONFIG_REGULATOR_MAX77857=m
+CONFIG_REGULATOR_MAX8649=m
+CONFIG_REGULATOR_MAX8660=m
+CONFIG_REGULATOR_MAX8893=m
+CONFIG_REGULATOR_MAX8907=m
+CONFIG_REGULATOR_MAX8925=m
+CONFIG_REGULATOR_MAX8952=m
+CONFIG_REGULATOR_MAX8997=m
+CONFIG_REGULATOR_MAX8998=m
+CONFIG_REGULATOR_MC13783=m
+CONFIG_REGULATOR_MC13892=m
+CONFIG_REGULATOR_MC13XXX_CORE=m
+CONFIG_REGULATOR_MP8859=m
+CONFIG_REGULATOR_MT6311=m
+CONFIG_REGULATOR_MT6315=m
+CONFIG_REGULATOR_MT6323=m
+CONFIG_REGULATOR_MT6331=m
+CONFIG_REGULATOR_MT6332=m
+CONFIG_REGULATOR_MT6357=m
+CONFIG_REGULATOR_MT6358=m
+CONFIG_REGULATOR_MT6359=m
+CONFIG_REGULATOR_MT6360=m
+CONFIG_REGULATOR_MT6370=m
+CONFIG_REGULATOR_MT6397=m
+CONFIG_REGULATOR_NETLINK_EVENTS=y
+CONFIG_REGULATOR_PALMAS=m
+CONFIG_REGULATOR_PCA9450=m
+CONFIG_REGULATOR_PCAP=m
+CONFIG_REGULATOR_PCF50633=m
+CONFIG_REGULATOR_PF0900=m
+CONFIG_REGULATOR_PF530X=m
+CONFIG_REGULATOR_PF9453=m
+CONFIG_REGULATOR_PV88060=m
+CONFIG_REGULATOR_PV88080=m
+CONFIG_REGULATOR_PV88090=m
+CONFIG_REGULATOR_PWM=m
+CONFIG_REGULATOR_QCOM_LABIBB=m
+CONFIG_REGULATOR_QCOM_PM8008=m
+CONFIG_REGULATOR_QCOM_REFGEN=m
+CONFIG_REGULATOR_QCOM_SPMI=m
+CONFIG_REGULATOR_QCOM_USB_VBUS=m
+CONFIG_REGULATOR_RAA215300=m
+CONFIG_REGULATOR_RC5T583=m
+CONFIG_REGULATOR_RT4801=m
+CONFIG_REGULATOR_RT4803=m
+CONFIG_REGULATOR_RT4831=m
+CONFIG_REGULATOR_RT5033=m
+CONFIG_REGULATOR_RT5120=m
+CONFIG_REGULATOR_RT5133=m
+CONFIG_REGULATOR_RT5190A=m
+CONFIG_REGULATOR_RT5739=m
+CONFIG_REGULATOR_RT5759=m
+CONFIG_REGULATOR_RT6160=m
+CONFIG_REGULATOR_RT6190=m
+CONFIG_REGULATOR_RT6245=m
+CONFIG_REGULATOR_RTMV20=m
+CONFIG_REGULATOR_RTQ2134=m
+CONFIG_REGULATOR_RTQ2208=m
+CONFIG_REGULATOR_RTQ6752=m
+CONFIG_REGULATOR_S2DOS05=m
+CONFIG_REGULATOR_SKY81452=m
+CONFIG_REGULATOR_SLG51000=m
+CONFIG_REGULATOR_SY7636A=m
+CONFIG_REGULATOR_TPS51632=m
+CONFIG_REGULATOR_TPS6105X=m
+CONFIG_REGULATOR_TPS62360=m
+CONFIG_REGULATOR_TPS65023=m
+CONFIG_REGULATOR_TPS6507X=m
+CONFIG_REGULATOR_TPS65086=m
+CONFIG_REGULATOR_TPS65090=m
+CONFIG_REGULATOR_TPS65132=m
+CONFIG_REGULATOR_TPS6524X=m
+CONFIG_REGULATOR_TPS6586X=m
+CONFIG_REGULATOR_TPS65910=m
+CONFIG_REGULATOR_TPS65912=m
+CONFIG_REGULATOR_TPS68470=m
+CONFIG_REGULATOR_TWL4030=m
+CONFIG_REGULATOR_USERSPACE_CONSUMER=m
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
+CONFIG_REGULATOR_WM831X=m
+CONFIG_REGULATOR_WM8350=m
+CONFIG_REGULATOR_WM8400=m
+CONFIG_REGULATOR_WM8994=m
+CONFIG_REGULATOR=y
+CONFIG_RELAY=y
+CONFIG_RELOCATABLE=y
+CONFIG_REMOTE_TARGET=m
+CONFIG_RENESAS_PHY=m
+CONFIG_RESET_ATTACK_MITIGATION=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SIMPLE=y
+CONFIG_RESET_TI_SYSCON=m
+CONFIG_RESET_TI_TPS380X=m
+CONFIG_RETHOOK=y
+CONFIG_RETHUNK=y
+CONFIG_RETPOLINE=y
+CONFIG_RETU_WATCHDOG=m
+CONFIG_RFD77402=m
+CONFIG_RFD_FTL=m
+CONFIG_RFKILL_GPIO=m
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL=m
+CONFIG_RICHTEK_RTQ6056=m
+CONFIG_RIONET=m
+CONFIG_RIONET_RX_SIZE=128
+CONFIG_RIONET_TX_SIZE=128
+CONFIG_ROHM_BM1390=m
+CONFIG_ROHM_BU27008=m
+CONFIG_ROHM_BU27034=m
 CONFIG_RPMSG_CHAR=m
 CONFIG_RPMSG_CTRL=m
+CONFIG_RPMSG=m
 CONFIG_RPMSG_NS=m
 CONFIG_RPMSG_QCOM_GLINK=m
 CONFIG_RPMSG_QCOM_GLINK_RPM=m
+CONFIG_RPMSG_TTY=m
 CONFIG_RPMSG_VIRTIO=m
-# end of Rpmsg drivers
-
-CONFIG_SOUNDWIRE=y
-
-#
-# SoundWire Devices
-#
-CONFIG_SOUNDWIRE_CADENCE=m
-CONFIG_SOUNDWIRE_INTEL=m
-CONFIG_SOUNDWIRE_QCOM=m
-CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=m
-
-#
-# SOC (System On Chip) specific Drivers
-#
-
-#
-# Amlogic SoC drivers
-#
-# end of Amlogic SoC drivers
-
-#
-# Broadcom SoC drivers
-#
-# end of Broadcom SoC drivers
-
-#
-# NXP/Freescale QorIQ SoC drivers
-#
-# end of NXP/Freescale QorIQ SoC drivers
-
-#
-# i.MX SoC drivers
-#
-# end of i.MX SoC drivers
-
-#
-# Enable LiteX SoC Builder specific drivers
-#
-# end of Enable LiteX SoC Builder specific drivers
-
-#
-# Qualcomm SoC drivers
-#
-CONFIG_QCOM_QMI_HELPERS=m
-# end of Qualcomm SoC drivers
-
-# CONFIG_SOC_TI is not set
-
-#
-# Xilinx SoC drivers
-#
-# end of Xilinx SoC drivers
-# end of SOC (System On Chip) specific Drivers
-
-CONFIG_PM_DEVFREQ=y
-
-#
-# DEVFREQ Governors
-#
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_PERFORMANCE=y
-CONFIG_DEVFREQ_GOV_POWERSAVE=y
-CONFIG_DEVFREQ_GOV_USERSPACE=y
-CONFIG_DEVFREQ_GOV_PASSIVE=m
-
-#
-# DEVFREQ Drivers
-#
-CONFIG_PM_DEVFREQ_EVENT=y
-CONFIG_EXTCON=y
-
-#
-# Extcon Device Drivers
-#
-CONFIG_EXTCON_ADC_JACK=m
-CONFIG_EXTCON_AXP288=m
-CONFIG_EXTCON_FSA9480=m
-CONFIG_EXTCON_GPIO=m
-CONFIG_EXTCON_INTEL_INT3496=m
-CONFIG_EXTCON_INTEL_MRFLD=m
-CONFIG_EXTCON_MAX14577=m
-CONFIG_EXTCON_MAX3355=m
-CONFIG_EXTCON_MAX77693=m
-CONFIG_EXTCON_PTN5150=m
-CONFIG_EXTCON_RT8973A=m
-CONFIG_EXTCON_SM5502=m
-CONFIG_EXTCON_USB_GPIO=m
-CONFIG_EXTCON_USBC_CROS_EC=m
-CONFIG_EXTCON_USBC_TUSB320=m
-CONFIG_MEMORY=y
-CONFIG_FPGA_DFL_EMIF=m
-CONFIG_IIO=m
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_BUFFER_CB=m
-CONFIG_IIO_BUFFER_DMA=m
-CONFIG_IIO_BUFFER_DMAENGINE=m
-CONFIG_IIO_BUFFER_HW_CONSUMER=m
-CONFIG_IIO_KFIFO_BUF=m
-CONFIG_IIO_TRIGGERED_BUFFER=m
-CONFIG_IIO_CONFIGFS=m
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
-CONFIG_IIO_SW_DEVICE=m
-CONFIG_IIO_SW_TRIGGER=m
-CONFIG_IIO_TRIGGERED_EVENT=m
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16201=m
-CONFIG_ADIS16209=m
-CONFIG_ADXL313=m
-CONFIG_ADXL313_I2C=m
-CONFIG_ADXL313_SPI=m
-CONFIG_ADXL355=m
-CONFIG_ADXL355_I2C=m
-CONFIG_ADXL355_SPI=m
-CONFIG_ADXL367_SPI=m
-CONFIG_ADXL367_I2C=m
-CONFIG_ADXL372=m
-CONFIG_ADXL372_SPI=m
-CONFIG_ADXL372_I2C=m
-CONFIG_BMA220=m
-CONFIG_BMA400=m
-CONFIG_BMA400_I2C=m
-CONFIG_BMA400_SPI=m
-CONFIG_BMC150_ACCEL=m
-CONFIG_BMC150_ACCEL_I2C=m
-CONFIG_BMC150_ACCEL_SPI=m
-CONFIG_BMI088_ACCEL=m
-CONFIG_BMI088_ACCEL_SPI=m
-CONFIG_DA280=m
-CONFIG_DA311=m
-CONFIG_DMARD09=m
-CONFIG_DMARD10=m
-CONFIG_FXLS8962AF=m
-CONFIG_FXLS8962AF_I2C=m
-CONFIG_FXLS8962AF_SPI=m
-CONFIG_HID_SENSOR_ACCEL_3D=m
-CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
-CONFIG_IIO_ST_ACCEL_3AXIS=m
-CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
-CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
-CONFIG_KXSD9=m
-CONFIG_KXSD9_SPI=m
-CONFIG_KXSD9_I2C=m
-CONFIG_KXCJK1013=m
-CONFIG_MC3230=m
-CONFIG_MMA7455=m
-CONFIG_MMA7455_I2C=m
-CONFIG_MMA7455_SPI=m
-CONFIG_MMA7660=m
-CONFIG_MMA8452=m
-CONFIG_MMA9551_CORE=m
-CONFIG_MMA9551=m
-CONFIG_MMA9553=m
-CONFIG_MSA311=m
-CONFIG_MXC4005=m
-CONFIG_MXC6255=m
+CONFIG_RPMSG_WWAN_CTRL=m
+CONFIG_RPR0521=m
+CONFIG_RSI_91X=m
+CONFIG_RSI_COEX=y
+CONFIG_RSI_SDIO=m
+CONFIG_RSI_USB=m
+CONFIG_RT2400PCI=m
+CONFIG_RT2500PCI=m
+CONFIG_RT2500USB=m
+CONFIG_RT2800_LIB=m
+CONFIG_RT2800_LIB_MMIO=m
+CONFIG_RT2800PCI=m
+CONFIG_RT2800PCI_RT3290=y
+CONFIG_RT2800PCI_RT33XX=y
+CONFIG_RT2800PCI_RT35XX=y
+CONFIG_RT2800PCI_RT53XX=y
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT3573=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_LEDS=y
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_MMIO=m
+CONFIG_RT2X00_LIB_PCI=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00=m
+CONFIG_RT61PCI=m
+CONFIG_RT73USB=m
+CONFIG_RTC_DRV_88PM80X=m
+CONFIG_RTC_DRV_88PM860X=m
+CONFIG_RTC_DRV_ABB5ZES3=m
+CONFIG_RTC_DRV_ABEOZ9=m
+CONFIG_RTC_DRV_ABX80X=m
+CONFIG_RTC_DRV_BQ32K=m
+CONFIG_RTC_DRV_BQ4802=m
+CONFIG_RTC_DRV_CMOS=y
+CONFIG_RTC_DRV_DA9052=m
+CONFIG_RTC_DRV_DA9055=m
+CONFIG_RTC_DRV_DA9063=m
+CONFIG_RTC_DRV_DS1286=m
+CONFIG_RTC_DRV_DS1302=m
+CONFIG_RTC_DRV_DS1305=m
+CONFIG_RTC_DRV_DS1307=m
+CONFIG_RTC_DRV_DS1343=m
+CONFIG_RTC_DRV_DS1347=m
+CONFIG_RTC_DRV_DS1374=m
+CONFIG_RTC_DRV_DS1374_WDT=y
+CONFIG_RTC_DRV_DS1390=m
+CONFIG_RTC_DRV_DS1511=m
+CONFIG_RTC_DRV_DS1553=m
+CONFIG_RTC_DRV_DS1672=m
+CONFIG_RTC_DRV_DS1685_FAMILY=m
+CONFIG_RTC_DRV_DS1685=y
+CONFIG_RTC_DRV_DS1742=m
+CONFIG_RTC_DRV_DS2404=m
+CONFIG_RTC_DRV_DS3232_HWMON=y
+CONFIG_RTC_DRV_DS3232=m
+CONFIG_RTC_DRV_EM3027=m
+CONFIG_RTC_DRV_FM3130=m
+CONFIG_RTC_DRV_FTRTC010=m
+CONFIG_RTC_DRV_GOLDFISH=m
+CONFIG_RTC_DRV_HID_SENSOR_TIME=m
+CONFIG_RTC_DRV_ISL12022=m
+CONFIG_RTC_DRV_ISL1208=m
+CONFIG_RTC_DRV_LP8788=m
+CONFIG_RTC_DRV_M41T80=m
+CONFIG_RTC_DRV_M41T80_WDT=y
+CONFIG_RTC_DRV_M41T93=m
+CONFIG_RTC_DRV_M41T94=m
+CONFIG_RTC_DRV_M48T35=m
+CONFIG_RTC_DRV_M48T59=m
+CONFIG_RTC_DRV_M48T86=m
+CONFIG_RTC_DRV_MAX31335=m
+CONFIG_RTC_DRV_MAX6900=m
+CONFIG_RTC_DRV_MAX6902=m
+CONFIG_RTC_DRV_MAX6916=m
+CONFIG_RTC_DRV_MAX8907=m
+CONFIG_RTC_DRV_MAX8925=m
+CONFIG_RTC_DRV_MAX8997=m
+CONFIG_RTC_DRV_MAX8998=m
+CONFIG_RTC_DRV_MC13XXX=m
+CONFIG_RTC_DRV_MCP795=m
+CONFIG_RTC_DRV_MSM6242=m
+CONFIG_RTC_DRV_MT6397=m
+CONFIG_RTC_DRV_PALMAS=m
+CONFIG_RTC_DRV_PCAP=m
+CONFIG_RTC_DRV_PCF2123=m
+CONFIG_RTC_DRV_PCF2127=m
+CONFIG_RTC_DRV_PCF50633=m
+CONFIG_RTC_DRV_PCF85063=m
+CONFIG_RTC_DRV_PCF8523=m
+CONFIG_RTC_DRV_PCF85363=m
+CONFIG_RTC_DRV_PCF8563=m
+CONFIG_RTC_DRV_PCF8583=m
+CONFIG_RTC_DRV_R9701=m
+CONFIG_RTC_DRV_RC5T583=m
+CONFIG_RTC_DRV_RP5C01=m
+CONFIG_RTC_DRV_RS5C348=m
+CONFIG_RTC_DRV_RS5C372=m
+CONFIG_RTC_DRV_RV3028=m
+CONFIG_RTC_DRV_RV3029C2=m
+CONFIG_RTC_DRV_RV3029_HWMON=y
+CONFIG_RTC_DRV_RV3032=m
+CONFIG_RTC_DRV_RV8803=m
+CONFIG_RTC_DRV_RX4581=m
+CONFIG_RTC_DRV_RX6110=m
+CONFIG_RTC_DRV_RX8010=m
+CONFIG_RTC_DRV_RX8025=m
+CONFIG_RTC_DRV_RX8581=m
+CONFIG_RTC_DRV_S35390A=m
+CONFIG_RTC_DRV_SD3078=m
+CONFIG_RTC_DRV_STK17TA8=m
+CONFIG_RTC_DRV_TPS6586X=m
+CONFIG_RTC_DRV_TPS65910=m
+CONFIG_RTC_DRV_TPS6594=m
+CONFIG_RTC_DRV_WILCO_EC=m
+CONFIG_RTC_DRV_WM831X=m
+CONFIG_RTC_DRV_WM8350=m
+CONFIG_RTC_DRV_X1205=m
+CONFIG_RTC_I2C_AND_SPI=m
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RTL8180=m
+CONFIG_RTL8187_LEDS=y
+CONFIG_RTL8187=m
+CONFIG_RTL8188EE=m
+CONFIG_RTL8192C_COMMON=m
+CONFIG_RTL8192CE=m
+CONFIG_RTL8192CU=m
+CONFIG_RTL8192DE=m
+CONFIG_RTL8192DU=m
+CONFIG_RTL8192EE=m
+CONFIG_RTL8192E=m
+CONFIG_RTL8192SE=m
+CONFIG_RTL8192U=m
+CONFIG_RTL8723AE=m
+CONFIG_RTL8723BE=m
+CONFIG_RTL8723BS=m
+CONFIG_RTL8723_COMMON=m
+CONFIG_RTL8821AE=m
+CONFIG_RTL8XXXU=m
+CONFIG_RTL8XXXU_UNTESTED=y
+CONFIG_RTLBTCOEXIST=m
+CONFIG_RTL_CARDS=m
+CONFIG_RTLLIB_CRYPTO_CCMP=m
+CONFIG_RTLLIB_CRYPTO_TKIP=m
+CONFIG_RTLLIB_CRYPTO_WEP=m
+CONFIG_RTLLIB=m
+CONFIG_RTLWIFI=m
+CONFIG_RTLWIFI_PCI=m
+CONFIG_RTLWIFI_USB=m
+CONFIG_RTS5208=m
+CONFIG_RTW88_8723CS=m
+CONFIG_RTW88_8723DE=m
+CONFIG_RTW88_8723D=m
+CONFIG_RTW88_8723DS=m
+CONFIG_RTW88_8723DU=m
+CONFIG_RTW88_8821CE=m
+CONFIG_RTW88_8821C=m
+CONFIG_RTW88_8821CS=m
+CONFIG_RTW88_8821CU=m
+CONFIG_RTW88_8822BE=m
+CONFIG_RTW88_8822B=m
+CONFIG_RTW88_8822BS=m
+CONFIG_RTW88_8822BU=m
+CONFIG_RTW88_8822CE=m
+CONFIG_RTW88_8822C=m
+CONFIG_RTW88_8822CS=m
+CONFIG_RTW88_8822CU=m
+CONFIG_RTW88_CORE=m
+CONFIG_RTW88=m
+CONFIG_RTW88_PCI=m
+CONFIG_RTW88_SDIO=m
+CONFIG_RTW88_USB=m
+CONFIG_RTW89_8851BE=m
+CONFIG_RTW89_8851B=m
+CONFIG_RTW89_8852AE=m
+CONFIG_RTW89_8852A=m
+CONFIG_RTW89_8852BE=m
+CONFIG_RTW89_8852B=m
+CONFIG_RTW89_8852BTE=m
+CONFIG_RTW89_8852CE=m
+CONFIG_RTW89_8852C=m
+CONFIG_RTW89_8922AE=m
+CONFIG_RTW89_CORE=m
+CONFIG_RTW89_DEBUGFS=y
+CONFIG_RTW89_DEBUG=y
+CONFIG_RTW89=m
+CONFIG_RTW89_PCI=m
+CONFIG_SAMSUNG_GALAXYBOOK=m
+CONFIG_SAMSUNG_LAPTOP=m
+CONFIG_SAMSUNG_Q10=m
+CONFIG_SATA_ACARD_AHCI=m
+CONFIG_SATA_AHCI=m
+CONFIG_SATA_AHCI_PLATFORM=m
+CONFIG_SATA_DWC=m
+CONFIG_SATA_INIC162X=m
+CONFIG_SATA_MV=m
+CONFIG_SATA_NV=m
+CONFIG_SATA_PROMISE=m
+CONFIG_SATA_QSTOR=m
+CONFIG_SATA_SIL24=m
+CONFIG_SATA_SIL=m
+CONFIG_SATA_SIS=m
+CONFIG_SATA_SVW=m
+CONFIG_SATA_SX4=m
+CONFIG_SATA_ULI=m
+CONFIG_SATA_VIA=m
+CONFIG_SATA_VITESSE=m
+CONFIG_SATA_ZPODD=y
+CONFIG_SBC_EPX_C3_WATCHDOG=m
+CONFIG_SBC_FITPC2_WATCHDOG=m
+CONFIG_SBP_TARGET=m
+CONFIG_SC1200_WDT=m
 CONFIG_SCA3000=m
 CONFIG_SCA3300=m
-CONFIG_STK8312=m
-CONFIG_STK8BA50=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD_SIGMA_DELTA=m
-CONFIG_AD7091R5=m
-CONFIG_AD7124=m
-CONFIG_AD7192=m
-CONFIG_AD7266=m
-CONFIG_AD7291=m
-CONFIG_AD7292=m
-CONFIG_AD7298=m
-CONFIG_AD7476=m
-CONFIG_AD7606=m
-CONFIG_AD7606_IFACE_PARALLEL=m
-CONFIG_AD7606_IFACE_SPI=m
-CONFIG_AD7766=m
-CONFIG_AD7768_1=m
-CONFIG_AD7780=m
-CONFIG_AD7791=m
-CONFIG_AD7793=m
-CONFIG_AD7887=m
-CONFIG_AD7923=m
-CONFIG_AD7949=m
-CONFIG_AD799X=m
-CONFIG_AXP20X_ADC=m
-CONFIG_AXP288_ADC=m
-CONFIG_CC10001_ADC=m
-CONFIG_DA9150_GPADC=m
-CONFIG_DLN2_ADC=m
-CONFIG_ENVELOPE_DETECTOR=m
-CONFIG_HI8435=m
-CONFIG_HX711=m
-CONFIG_INA2XX_ADC=m
-CONFIG_INTEL_MRFLD_ADC=m
-CONFIG_LTC2471=m
-CONFIG_LTC2485=m
-CONFIG_LTC2496=m
-CONFIG_LTC2497=m
-CONFIG_MAX1027=m
-CONFIG_MAX11100=m
-CONFIG_MAX1118=m
-CONFIG_MAX11205=m
-CONFIG_MAX1241=m
-CONFIG_MAX1363=m
-CONFIG_MAX9611=m
-CONFIG_MCP320X=m
-CONFIG_MCP3422=m
-CONFIG_MCP3911=m
-CONFIG_MEDIATEK_MT6360_ADC=m
-CONFIG_MEN_Z188_ADC=m
-CONFIG_MP2629_ADC=m
-CONFIG_NAU7802=m
-CONFIG_QCOM_VADC_COMMON=m
-CONFIG_QCOM_SPMI_IADC=m
-CONFIG_QCOM_SPMI_VADC=m
-CONFIG_QCOM_SPMI_ADC5=m
-CONFIG_RICHTEK_RTQ6056=m
+CONFIG_SCD30_CORE=m
+CONFIG_SCD30_I2C=m
+CONFIG_SCD30_SERIAL=m
+CONFIG_SCD4X=m
+CONFIG_SCF_TORTURE_TEST=m
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SCHED_CLUSTER=y
+CONFIG_SCHED_CORE=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHED_MC_PRIO=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_MM_CID=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_SCHED_SMT=y
+CONFIG_SCHEDSTATS=y
+CONFIG_SCSI_3W_9XXX=m
+CONFIG_SCSI_3W_SAS=m
+CONFIG_SCSI_AACRAID=m
+CONFIG_SCSI_ACARD=m
+CONFIG_SCSI_ADVANSYS=m
+CONFIG_SCSI_AIC79XX=m
+CONFIG_SCSI_AIC7XXX=m
+CONFIG_SCSI_AIC94XX=m
+CONFIG_SCSI_AM53C974=m
+CONFIG_SCSI_ARCMSR=m
+CONFIG_SCSI_BFA_FC=m
+CONFIG_SCSI_BNX2_ISCSI=m
+CONFIG_SCSI_BNX2X_FCOE=m
+CONFIG_SCSI_BUSLOGIC=m
+CONFIG_SCSI_CHELSIO_FCOE=m
+CONFIG_SCSI_COMMON=m
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_CXGB3_ISCSI=m
+CONFIG_SCSI_CXGB4_ISCSI=m
+CONFIG_SCSI_DC395x=m
+CONFIG_SCSI_DH_ALUA=m
+CONFIG_SCSI_DH_EMC=m
+CONFIG_SCSI_DH_HP_SW=m
+CONFIG_SCSI_DH_RDAC=m
+CONFIG_SCSI_DH=y
+CONFIG_SCSI_DMX3191D=m
+CONFIG_SCSI_EFCT=m
+CONFIG_SCSI_ENCLOSURE=m
+CONFIG_SCSI_ESAS2R=m
+CONFIG_SCSI_FC_ATTRS=m
+CONFIG_SCSI_FDOMAIN=m
+CONFIG_SCSI_FDOMAIN_PCI=m
+CONFIG_SCSI_FLASHPOINT=y
+CONFIG_SCSI_HPSA=m
+CONFIG_SCSI_HPTIOP=m
+CONFIG_SCSI_IMM=m
+CONFIG_SCSI_INIA100=m
+CONFIG_SCSI_INITIO=m
+CONFIG_SCSI_IPR=m
+CONFIG_SCSI_IPS=m
+CONFIG_SCSI_ISCI=m
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_LOWLEVEL_PCMCIA=y
+CONFIG_SCSI_LPFC=m
+CONFIG_SCSI=m
+CONFIG_SCSI_MOD=m
+CONFIG_SCSI_MPI3MR=m
+CONFIG_SCSI_MPT2SAS=m
+CONFIG_SCSI_MPT2SAS_MAX_SGE=128
+CONFIG_SCSI_MPT3SAS=m
+CONFIG_SCSI_MPT3SAS_MAX_SGE=128
+CONFIG_SCSI_MVSAS=m
+CONFIG_SCSI_MVSAS_TASKLET=y
+CONFIG_SCSI_MVUMI=m
+CONFIG_SCSI_MYRB=m
+CONFIG_SCSI_MYRS=m
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PM8001=m
+CONFIG_SCSI_PMCRAID=m
+CONFIG_SCSI_PPA=m
+CONFIG_SCSI_PROC_FS=y
+CONFIG_SCSI_QLA_FC=m
+CONFIG_SCSI_QLA_ISCSI=m
+CONFIG_SCSI_QLOGIC_1280=m
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_SMARTPQI=m
+CONFIG_SCSI_SNIC=m
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_STEX=m
+CONFIG_SCSI_SYM53C8XX_2=m
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+CONFIG_SCSI_SYM53C8XX_MMIO=y
+CONFIG_SCSI_UFS_CDNS_PLATFORM=m
+CONFIG_SCSI_UFS_DWC_TC_PCI=m
+CONFIG_SCSI_UFSHCD=m
+CONFIG_SCSI_UFSHCD_PCI=m
+CONFIG_SCSI_UFSHCD_PLATFORM=m
+CONFIG_SCSI_UFS_HPB=y
+CONFIG_SCSI_UFS_HWMON=y
+CONFIG_SCSI_VIRTIO=m
+CONFIG_SCSI_WD719X=m
 CONFIG_SD_ADC_MODULATOR=m
-CONFIG_TI_ADC081C=m
-CONFIG_TI_ADC0832=m
-CONFIG_TI_ADC084S021=m
-CONFIG_TI_ADC12138=m
-CONFIG_TI_ADC108S102=m
-CONFIG_TI_ADC128S052=m
-CONFIG_TI_ADC161S626=m
-CONFIG_TI_ADS1015=m
-CONFIG_TI_ADS7950=m
-CONFIG_TI_ADS8344=m
-CONFIG_TI_ADS8688=m
-CONFIG_TI_ADS124S08=m
-CONFIG_TI_ADS131E08=m
-CONFIG_TI_AM335X_ADC=m
-CONFIG_TI_TLC4541=m
-CONFIG_TI_TSC2046=m
-CONFIG_VF610_ADC=m
-CONFIG_VIPERBOARD_ADC=m
-CONFIG_XILINX_XADC=m
-CONFIG_XILINX_AMS=m
-# end of Analog to digital converters
-
-#
-# Analog Front Ends
-#
-# end of Analog Front Ends
-
-#
-# Amplifiers
-#
-CONFIG_AD8366=m
-CONFIG_ADA4250=m
-CONFIG_HMC425=m
-# end of Amplifiers
-
-#
-# Capacitance to digital converters
-#
-CONFIG_AD7150=m
-# end of Capacitance to digital converters
-
-#
-# Chemical Sensors
-#
-CONFIG_ATLAS_PH_SENSOR=m
-CONFIG_ATLAS_EZO_SENSOR=m
-CONFIG_BME680=m
-CONFIG_BME680_I2C=m
-CONFIG_BME680_SPI=m
-CONFIG_CCS811=m
-CONFIG_IAQCORE=m
-CONFIG_PMS7003=m
-CONFIG_SCD30_CORE=m
-CONFIG_SCD30_I2C=m
-CONFIG_SCD30_SERIAL=m
-CONFIG_SCD4X=m
+CONFIG_SDIO_UART=m
+CONFIG_SDP500=m
+CONFIG_SDR_PLATFORM_DRIVERS=y
+CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN=y
+CONFIG_SECONDARY_TRUSTED_KEYRING=y
+CONFIG_SECRETMEM=y
+CONFIG_SEG_LED_GPIO=m
+CONFIG_SEL3350_PLATFORM=m
+CONFIG_SENSEAIR_SUNRISE_CO2=m
 CONFIG_SENSIRION_SGP30=m
 CONFIG_SENSIRION_SGP40=m
-CONFIG_SPS30=m
-CONFIG_SPS30_I2C=m
-CONFIG_SPS30_SERIAL=m
-CONFIG_SENSEAIR_SUNRISE_CO2=m
-CONFIG_VZ89X=m
-# end of Chemical Sensors
-
-CONFIG_IIO_CROS_EC_SENSORS_CORE=m
-CONFIG_IIO_CROS_EC_SENSORS=m
-CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m
-
-#
-# Hid Sensor IIO Common
-#
-CONFIG_HID_SENSOR_IIO_COMMON=m
-CONFIG_HID_SENSOR_IIO_TRIGGER=m
-# end of Hid Sensor IIO Common
-
-CONFIG_IIO_MS_SENSORS_I2C=m
-
-#
-# IIO SCMI Sensors
-#
-# end of IIO SCMI Sensors
-
-#
-# SSP Sensor Common
-#
-CONFIG_IIO_SSP_SENSORS_COMMONS=m
-CONFIG_IIO_SSP_SENSORHUB=m
-# end of SSP Sensor Common
-
-CONFIG_IIO_ST_SENSORS_I2C=m
-CONFIG_IIO_ST_SENSORS_SPI=m
-CONFIG_IIO_ST_SENSORS_CORE=m
-
-#
-# Digital to analog converters
-#
-CONFIG_AD5064=m
-CONFIG_AD5360=m
-CONFIG_AD5380=m
-CONFIG_AD5421=m
-CONFIG_AD5446=m
-CONFIG_AD5449=m
-CONFIG_AD5592R_BASE=m
-CONFIG_AD5592R=m
-CONFIG_AD5593R=m
-CONFIG_AD5504=m
-CONFIG_AD5624R_SPI=m
-CONFIG_LTC2688=m
-CONFIG_AD5686=m
-CONFIG_AD5686_SPI=m
-CONFIG_AD5696_I2C=m
-CONFIG_AD5755=m
-CONFIG_AD5758=m
-CONFIG_AD5761=m
-CONFIG_AD5764=m
-CONFIG_AD5766=m
-CONFIG_AD5770R=m
-CONFIG_AD5791=m
-CONFIG_AD7303=m
-CONFIG_AD8801=m
-CONFIG_DS4424=m
-CONFIG_LTC1660=m
-CONFIG_LTC2632=m
-CONFIG_M62332=m
-CONFIG_MAX517=m
-CONFIG_MAX5821=m
-CONFIG_MCP4725=m
-CONFIG_MCP4922=m
-CONFIG_TI_DAC082S085=m
-CONFIG_TI_DAC5571=m
-CONFIG_TI_DAC7311=m
-CONFIG_TI_DAC7612=m
-# end of Digital to analog converters
-
-#
-# IIO dummy driver
-#
-# CONFIG_IIO_SIMPLE_DUMMY is not set
-# end of IIO dummy driver
-
-#
-# Frequency Synthesizers DDS/PLL
-#
-
-#
-# Clock Generator/Distribution
-#
-CONFIG_AD9523=m
-# end of Clock Generator/Distribution
-
-#
-# Phase-Locked Loop (PLL) frequency synthesizers
-#
-CONFIG_ADF4350=m
-CONFIG_ADF4371=m
-CONFIG_ADRF6780=m
-# end of Phase-Locked Loop (PLL) frequency synthesizers
-# end of Frequency Synthesizers DDS/PLL
-
-#
-# Digital gyroscope sensors
-#
-CONFIG_ADIS16080=m
-CONFIG_ADIS16130=m
-CONFIG_ADIS16136=m
-CONFIG_ADIS16260=m
-CONFIG_ADXRS290=m
-CONFIG_ADXRS450=m
-CONFIG_BMG160=m
-CONFIG_BMG160_I2C=m
-CONFIG_BMG160_SPI=m
-CONFIG_FXAS21002C=m
-CONFIG_FXAS21002C_I2C=m
-CONFIG_FXAS21002C_SPI=m
-CONFIG_HID_SENSOR_GYRO_3D=m
-CONFIG_MPU3050=m
-CONFIG_MPU3050_I2C=m
-CONFIG_IIO_ST_GYRO_3AXIS=m
-CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
-CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
-CONFIG_ITG3200=m
-# end of Digital gyroscope sensors
-
-#
-# Health Sensors
-#
-
-#
-# Heart Rate Monitors
-#
-CONFIG_AFE4403=m
-CONFIG_AFE4404=m
-CONFIG_MAX30100=m
-CONFIG_MAX30102=m
-# end of Heart Rate Monitors
-# end of Health Sensors
-
-#
-# Humidity sensors
-#
-CONFIG_AM2315=m
-CONFIG_DHT11=m
-CONFIG_HDC100X=m
-CONFIG_HDC2010=m
-CONFIG_HID_SENSOR_HUMIDITY=m
-CONFIG_HTS221=m
-CONFIG_HTS221_I2C=m
-CONFIG_HTS221_SPI=m
-CONFIG_HTU21=m
-CONFIG_SI7005=m
-CONFIG_SI7020=m
-# end of Humidity sensors
-
-#
-# Inertial measurement units
-#
-CONFIG_ADIS16400=m
-CONFIG_ADIS16460=m
-CONFIG_ADIS16475=m
-CONFIG_ADIS16480=m
-CONFIG_BMI160=m
-CONFIG_BMI160_I2C=m
-CONFIG_BMI160_SPI=m
-CONFIG_BOSCH_BNO055_SERIAL=m
-CONFIG_BOSCH_BNO055_I2C=m
-CONFIG_FXOS8700=m
-CONFIG_FXOS8700_I2C=m
-CONFIG_FXOS8700_SPI=m
-CONFIG_KMX61=m
-CONFIG_INV_ICM42600=m
-CONFIG_INV_ICM42600_I2C=m
-CONFIG_INV_ICM42600_SPI=m
-CONFIG_INV_MPU6050_IIO=m
-CONFIG_INV_MPU6050_I2C=m
-CONFIG_INV_MPU6050_SPI=m
-CONFIG_IIO_ST_LSM6DSX=m
-CONFIG_IIO_ST_LSM6DSX_I2C=m
-CONFIG_IIO_ST_LSM6DSX_SPI=m
-CONFIG_IIO_ST_LSM6DSX_I3C=m
-CONFIG_IIO_ST_LSM9DS0=m
-CONFIG_IIO_ST_LSM9DS0_I2C=m
-CONFIG_IIO_ST_LSM9DS0_SPI=m
-# end of Inertial measurement units
-
-CONFIG_IIO_ADIS_LIB=m
-CONFIG_IIO_ADIS_LIB_BUFFER=y
-
-#
-# Light sensors
-#
-# CONFIG_ACPI_ALS is not set
-CONFIG_ADJD_S311=m
-CONFIG_ADUX1020=m
-CONFIG_AL3010=m
-CONFIG_AL3320A=m
-CONFIG_APDS9300=m
-CONFIG_APDS9960=m
-CONFIG_AS73211=m
-CONFIG_BH1750=m
-CONFIG_BH1780=m
-CONFIG_CM32181=m
-CONFIG_CM3232=m
-CONFIG_CM3323=m
-CONFIG_CM36651=m
-CONFIG_IIO_CROS_EC_LIGHT_PROX=m
-CONFIG_GP2AP002=m
-CONFIG_GP2AP020A00F=m
-CONFIG_IQS621_ALS=m
-CONFIG_SENSORS_ISL29018=m
-CONFIG_SENSORS_ISL29028=m
-CONFIG_ISL29125=m
-CONFIG_HID_SENSOR_ALS=m
-CONFIG_HID_SENSOR_PROX=m
-CONFIG_JSA1212=m
-CONFIG_RPR0521=m
-CONFIG_SENSORS_LM3533=m
-CONFIG_LTR501=m
-CONFIG_LTRF216A=m
-CONFIG_LV0104CS=m
-CONFIG_MAX44000=m
-CONFIG_MAX44009=m
-CONFIG_NOA1305=m
-CONFIG_OPT3001=m
-CONFIG_PA12203001=m
+CONFIG_SENSORS_ABITUGURU3=m
+CONFIG_SENSORS_ABITUGURU=m
+CONFIG_SENSORS_ACPI_POWER=m
+CONFIG_SENSORS_APPLESMC=m
+CONFIG_SENSORS_ASB100=m
+CONFIG_SENSORS_ASUS_EC=m
+CONFIG_SENSORS_ASUS_WMI=m
+CONFIG_SENSORS_ATK0110=m
+CONFIG_SENSORS_CORETEMP=m
+CONFIG_SENSORS_DA9055=m
+CONFIG_SENSORS_DELL_SMM=m
+CONFIG_SENSORS_FAM15H_POWER=m
+CONFIG_SENSORS_FSCHMD=m
+CONFIG_SENSORS_HDAPS=m
+CONFIG_SENSORS_HP_WMI=m
+CONFIG_SENSORS_I5500=m
+CONFIG_SENSORS_K10TEMP=m
+CONFIG_SENSORS_K8TEMP=m
+CONFIG_SENSORS_LENOVO_EC=m
+CONFIG_SENSORS_VIA_CPUTEMP=m
+CONFIG_SENSORS_WM8350=m
+CONFIG_SENSORS_XGENE=m
+CONFIG_SERIAL_8250_CS=m
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_DFL=m
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_DW=m
+CONFIG_SERIAL_8250_EXAR=m
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FINTEK=y
+CONFIG_SERIAL_8250_LPSS=m
+CONFIG_SERIAL_8250=m
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_MEN_MCB=m
+CONFIG_SERIAL_8250_MID=m
+CONFIG_SERIAL_8250_NI=m
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI1XXXX=m
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_PCI=m
+CONFIG_SERIAL_8250_PERICOM=m
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_ALTERA_JTAGUART=m
+CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
+CONFIG_SERIAL_ALTERA_UART=m
+CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
+CONFIG_SERIAL_ARC=m
+CONFIG_SERIAL_ARC_NR_PORTS=1
+CONFIG_SERIAL_DEV_BUS=m
+CONFIG_SERIAL_FSL_LINFLEXUART=m
+CONFIG_SERIAL_FSL_LPUART=m
+CONFIG_SERIAL_IPOCTAL=m
+CONFIG_SERIAL_JSM=m
+CONFIG_SERIAL_LANTIQ=m
+CONFIG_SERIAL_MAX3100=m
+CONFIG_SERIAL_MAX310X=y
+CONFIG_SERIAL_MCTRL_GPIO=m
+CONFIG_SERIAL_MEN_Z135=m
+CONFIG_SERIAL_MULTI_INSTANTIATE=m
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_RP2=m
+CONFIG_SERIAL_RP2_NR_UARTS=32
+CONFIG_SERIAL_SC16IS7XX_CORE=m
+CONFIG_SERIAL_SC16IS7XX_I2C=y
+CONFIG_SERIAL_SC16IS7XX=m
+CONFIG_SERIAL_SC16IS7XX_SPI=y
+CONFIG_SERIAL_SCCNXP=m
+CONFIG_SERIAL_SPRD=m
+CONFIG_SERIAL_UARTLITE=m
+CONFIG_SERIAL_UARTLITE_NR_UARTS=1
+CONFIG_SERIO_ALTERA_PS2=m
+CONFIG_SERIO_ARC_PS2=m
+CONFIG_SERIO_CT82C710=m
+CONFIG_SERIO_GPIO_PS2=m
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO=m
+CONFIG_SERIO_PARKBD=m
+CONFIG_SERIO_PCIPS2=m
+CONFIG_SERIO_PS2MULT=m
+CONFIG_SERIO_RAW=m
+CONFIG_SERIO_SERPORT=m
+CONFIG_SEV_GUEST=m
+CONFIG_SF_PDMA=m
+CONFIG_SGETMASK_SYSCALL=y
+CONFIG_SGI_PARTITION=y
+CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
 CONFIG_SI1133=m
 CONFIG_SI1145=m
+CONFIG_SI7005=m
+CONFIG_SI7020=m
+CONFIG_SIEMENS_SIMATIC_IPC_BATT_APOLLOLAKE=m
+CONFIG_SIEMENS_SIMATIC_IPC_BATT_ELKHARTLAKE=m
+CONFIG_SIEMENS_SIMATIC_IPC_BATT_F7188X=m
+CONFIG_SIEMENS_SIMATIC_IPC_BATT=m
+CONFIG_SIEMENS_SIMATIC_IPC=m
+CONFIG_SIEMENS_SIMATIC_IPC_WDT=m
+CONFIG_SIGNED_PE_FILE_VERIFICATION=y
+CONFIG_SILICOM_PLATFORM=m
+CONFIG_SIOX_BUS_GPIO=m
+CONFIG_SIOX=m
+CONFIG_SLAB_FREELIST_HARDENED=y
+CONFIG_SLAB_FREELIST_RANDOM=y
+CONFIG_SLAB_MERGE_DEFAULT=y
+CONFIG_SLHC=m
+CONFIG_SLIMBUS=m
+CONFIG_SLIM_QCOM_CTRL=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLIP=m
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_SLIP_SMART=y
+CONFIG_SLS=y
+CONFIG_SM_FTL=m
+CONFIG_SMPRO_ERRMON=m
+CONFIG_SMPRO_MISC=m
+CONFIG_SMSC37B787_WDT=m
+CONFIG_SMSC_PHY=m
+CONFIG_SMSC_SCH311X_WDT=m
+CONFIG_SMS_SDIO_DRV=m
+CONFIG_SMS_SIANO_MDTV=m
+CONFIG_SMS_SIANO_RC=y
+CONFIG_SMS_USB_DRV=m
+CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
+CONFIG_SND_AC97_POWER_SAVE=y
+CONFIG_SND_AD1889=m
+CONFIG_SND_ALI5451=m
+CONFIG_SND_ALOOP=m
+CONFIG_SND_ALS300=m
+CONFIG_SND_ALS4000=m
+CONFIG_SND_AMD_ACP_CONFIG=m
+CONFIG_SND_AMD_ASOC_ACP63=m
+CONFIG_SND_AMD_ASOC_ACP70=m
+CONFIG_SND_AMD_ASOC_REMBRANDT=m
+CONFIG_SND_AMD_ASOC_RENOIR=m
+CONFIG_SND_ASIHPI=m
+CONFIG_SND_ATIIXP=m
+CONFIG_SND_ATIIXP_MODEM=m
+CONFIG_SND_ATMEL_SOC=m
+CONFIG_SND_AU8810=m
+CONFIG_SND_AU8820=m
+CONFIG_SND_AU8830=m
+CONFIG_SND_AW2=m
+CONFIG_SND_AZT3328=m
+CONFIG_SND_BCD2000=m
+CONFIG_SND_BCM63XX_I2S_WHISTLER=m
+CONFIG_SND_BEBOB=m
+CONFIG_SND_BT87X=m
+CONFIG_SND_BT87X_OVERCLOCK=y
+CONFIG_SND_CA0106=m
+CONFIG_SND_CMIPCI=m
+CONFIG_SND_COMPRESS_OFFLOAD=m
+CONFIG_SND_CS4281=m
+CONFIG_SND_CS46XX=m
+CONFIG_SND_CS46XX_NEW_DSP=y
+CONFIG_SND_CTL_FAST_LOOKUP=y
+CONFIG_SND_CTL_INPUT_VALIDATION=y
+CONFIG_SND_CTL_LED=m
+CONFIG_SND_CTXFI=m
+CONFIG_SND_DARLA20=m
+CONFIG_SND_DARLA24=m
+CONFIG_SND_DESIGNWARE_I2S=m
+CONFIG_SND_DESIGNWARE_PCM=y
+CONFIG_SND_DICE=m
+CONFIG_SND_DMAENGINE_PCM=m
+CONFIG_SND_DMA_SGBUF=y
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_DUMMY=m
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_ECHO3G=m
+CONFIG_SND_EMU10K1=m
+CONFIG_SND_EMU10K1_SEQ=m
+CONFIG_SND_EMU10K1X=m
+CONFIG_SND_ENS1370=m
+CONFIG_SND_ENS1371=m
+CONFIG_SND_ES1938=m
+CONFIG_SND_ES1968_INPUT=y
+CONFIG_SND_ES1968=m
+CONFIG_SND_ES1968_RADIO=y
+CONFIG_SND_FIREFACE=m
+CONFIG_SND_FIREWIRE_DIGI00X=m
+CONFIG_SND_FIREWIRE_LIB=m
+CONFIG_SND_FIREWIRE_MOTU=m
+CONFIG_SND_FIREWIRE_TASCAM=m
+CONFIG_SND_FIREWIRE=y
+CONFIG_SND_FIREWORKS=m
+CONFIG_SND_FM801=m
+CONFIG_SND_FM801_TEA575X_BOOL=y
+CONFIG_SND_GINA20=m
+CONFIG_SND_GINA24=m
+CONFIG_SND_HDA_CODEC_ALC260=m
+CONFIG_SND_HDA_CODEC_ALC262=m
+CONFIG_SND_HDA_CODEC_ALC268=m
+CONFIG_SND_HDA_CODEC_ALC269=m
+CONFIG_SND_HDA_CODEC_ALC662=m
+CONFIG_SND_HDA_CODEC_ALC680=m
+CONFIG_SND_HDA_CODEC_ALC861=m
+CONFIG_SND_HDA_CODEC_ALC861VD=m
+CONFIG_SND_HDA_CODEC_ALC880=m
+CONFIG_SND_HDA_CODEC_ALC882=m
+CONFIG_SND_HDA_CODEC_ANALOG=m
+CONFIG_SND_HDA_CODEC_CA0110=m
+CONFIG_SND_HDA_CODEC_CA0132_DSP=y
+CONFIG_SND_HDA_CODEC_CA0132=m
+CONFIG_SND_HDA_CODEC_CIRRUS=m
+CONFIG_SND_HDA_CODEC_CM9825=m
+CONFIG_SND_HDA_CODEC_CMEDIA=m
+CONFIG_SND_HDA_CODEC_CONEXANT=m
+CONFIG_SND_HDA_CODEC_CS420X=m
+CONFIG_SND_HDA_CODEC_CS421X=m
+CONFIG_SND_HDA_CODEC_CS8409=m
+CONFIG_SND_HDA_CODEC_HDMI_ATI=m
+CONFIG_SND_HDA_CODEC_HDMI_INTEL=m
+CONFIG_SND_HDA_CODEC_HDMI=m
+CONFIG_SND_HDA_CODEC_HDMI_NVIDIA=m
+CONFIG_SND_HDA_CODEC_HDMI_NVIDIA_MCP=m
+CONFIG_SND_HDA_CODEC_HDMI_TEGRA=m
+CONFIG_SND_HDA_CODEC_REALTEK=m
+CONFIG_SND_HDA_CODEC_SENARYTECH=m
+CONFIG_SND_HDA_CODEC_SI3054=m
+CONFIG_SND_HDA_CODEC_SIGMATEL=m
+CONFIG_SND_HDA_CODEC_VIA=m
+CONFIG_SND_HDA_COMPONENT=y
+CONFIG_SND_HDA_CORE=m
+CONFIG_SND_HDA_CS_DSP_CONTROLS=m
+CONFIG_SND_HDA_DSP_LOADER=y
+CONFIG_SND_HDA_EXT_CORE=m
+CONFIG_SND_HDA_GENERIC_LEDS=y
+CONFIG_SND_HDA_GENERIC=m
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_I915=y
+CONFIG_SND_HDA_INPUT_BEEP_MODE=1
+CONFIG_SND_HDA_INPUT_BEEP=y
+CONFIG_SND_HDA_INTEL=m
+CONFIG_SND_HDA=m
+CONFIG_SND_HDA_PATCH_LOADER=y
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
+CONFIG_SND_HDA_PREALLOC_SIZE=0
+CONFIG_SND_HDA_RECONFIG=y
+CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m
+CONFIG_SND_HDA_SCODEC_CS35L41=m
+CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m
+CONFIG_SND_HDA_SCODEC_CS35L56_I2C=m
+CONFIG_SND_HDA_SCODEC_CS35L56_SPI=m
+CONFIG_SND_HDA_SCODEC_TAS2781_I2C=m
+CONFIG_SND_HDA_SCODEC_TAS2781_SPI=m
+CONFIG_SND_HDSP=m
+CONFIG_SND_HDSPM=m
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_I2S_HI6210_I2S=m
+CONFIG_SND_ICE1712=m
+CONFIG_SND_ICE1724=m
+CONFIG_SND_INDIGODJ=m
+CONFIG_SND_INDIGODJX=m
+CONFIG_SND_INDIGOIO=m
+CONFIG_SND_INDIGOIOX=m
+CONFIG_SND_INDIGO=m
+CONFIG_SND_INTEL8X0=m
+CONFIG_SND_INTEL8X0M=m
+CONFIG_SND_INTEL_BYT_PREFER_SOF=y
+CONFIG_SND_INTEL_DSP_CONFIG=m
+CONFIG_SND_INTEL_NHLT=y
+CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m
+CONFIG_SND_ISIGHT=m
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_JACK=y
+CONFIG_SND_KORG1212=m
+CONFIG_SND_LAYLA20=m
+CONFIG_SND_LAYLA24=m
+CONFIG_SND_LOLA=m
+CONFIG_SND_LX6464ES=m
+CONFIG_SND=m
+CONFIG_SND_MAESTRO3_INPUT=y
+CONFIG_SND_MAESTRO3=m
+CONFIG_SND_MAX_CARDS=32
+CONFIG_SND_MIA=m
+CONFIG_SND_MIXART=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_MONA=m
+CONFIG_SND_MPU401=m
+CONFIG_SND_MPU401_UART=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_MTS64=m
+CONFIG_SND_NM256=m
+CONFIG_SND_OPL3_LIB=m
+CONFIG_SND_OPL3_LIB_SEQ=m
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_OXFW=m
+CONFIG_SND_OXYGEN_LIB=m
+CONFIG_SND_OXYGEN=m
+CONFIG_SND_PCI=y
+CONFIG_SND_PCMCIA=y
+CONFIG_SND_PCM_ELD=y
+CONFIG_SND_PCM_IEC958=y
+CONFIG_SND_PCM=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_PCMTEST=m
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_PCXHR=m
+CONFIG_SND_PDAUDIOCF=m
+CONFIG_SND_PORTMAN2X4=m
+CONFIG_SND_PROC_FS=y
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_RIPTIDE=m
+CONFIG_SND_RME32=m
+CONFIG_SND_RME9652=m
+CONFIG_SND_RME96=m
+CONFIG_SND_SB_COMMON=m
+CONFIG_SND_SEQ_DEVICE=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+CONFIG_SND_SEQ_MIDI_EMUL=m
+CONFIG_SND_SEQ_MIDI_EVENT=m
+CONFIG_SND_SEQ_MIDI=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQUENCER_OSS=m
+CONFIG_SND_SEQ_UMP_CLIENT=m
+CONFIG_SND_SEQ_UMP=y
+CONFIG_SND_SEQ_VIRMIDI=m
+CONFIG_SND_SERIAL_U16550=m
+CONFIG_SND_SIMPLE_CARD=m
+CONFIG_SND_SIMPLE_CARD_UTILS=m
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AC97_CODEC=m
+CONFIG_SND_SOC_ACPI_INTEL_MATCH=m
+CONFIG_SND_SOC_ACPI=m
+CONFIG_SND_SOC_ADAU1372_I2C=m
+CONFIG_SND_SOC_ADAU1372=m
+CONFIG_SND_SOC_ADAU1372_SPI=m
+CONFIG_SND_SOC_ADAU1701=m
+CONFIG_SND_SOC_ADAU1761_I2C=m
+CONFIG_SND_SOC_ADAU1761=m
+CONFIG_SND_SOC_ADAU1761_SPI=m
+CONFIG_SND_SOC_ADAU17X1=m
+CONFIG_SND_SOC_ADAU7002=m
+CONFIG_SND_SOC_ADAU7118_HW=m
+CONFIG_SND_SOC_ADAU7118_I2C=m
+CONFIG_SND_SOC_ADAU7118=m
+CONFIG_SND_SOC_ADAU_UTILS=m
+CONFIG_SND_SOC_ADI_AXI_I2S=m
+CONFIG_SND_SOC_ADI_AXI_SPDIF=m
+CONFIG_SND_SOC_ADI=m
+CONFIG_SND_SOC_AK4104=m
+CONFIG_SND_SOC_AK4118=m
+CONFIG_SND_SOC_AK4375=m
+CONFIG_SND_SOC_AK4458=m
+CONFIG_SND_SOC_AK4554=m
+CONFIG_SND_SOC_AK4613=m
+CONFIG_SND_SOC_AK4619=m
+CONFIG_SND_SOC_AK4642=m
+CONFIG_SND_SOC_AK5386=m
+CONFIG_SND_SOC_AK5558=m
+CONFIG_SND_SOC_ALC5623=m
+CONFIG_SND_SOC_AMD_ACP3x=m
+CONFIG_SND_SOC_AMD_ACP5x=m
+CONFIG_SND_SOC_AMD_ACP63_TOPLEVEL=m
+CONFIG_SND_SOC_AMD_ACP6x=m
+CONFIG_SND_SOC_AMD_ACP_COMMON=m
+CONFIG_SND_SOC_AMD_ACP_I2S=m
+CONFIG_SND_SOC_AMD_ACP=m
+CONFIG_SND_SOC_AMD_ACP_PCI=m
+CONFIG_SND_SOC_AMD_ACP_PCM=m
+CONFIG_SND_SOC_AMD_ACP_PDM=m
+CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m
+CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
+CONFIG_SND_SOC_AMD_LEGACY_MACH=m
+CONFIG_SND_SOC_AMD_MACH_COMMON=m
+CONFIG_SND_SOC_AMD_PS=m
+CONFIG_SND_SOC_AMD_PS_MACH=m
+CONFIG_SND_SOC_AMD_RENOIR=m
+CONFIG_SND_SOC_AMD_RENOIR_MACH=m
+CONFIG_SND_SOC_AMD_RPL_ACP6x=m
+CONFIG_SND_SOC_AMD_RV_RT5682_MACH=m
+CONFIG_SND_SOC_AMD_SOF_MACH=m
+CONFIG_SND_SOC_AMD_SOF_SDW_MACH=m
+CONFIG_SND_SOC_AMD_SOUNDWIRE=m
+CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m
+CONFIG_SND_SOC_AMD_VANGOGH_MACH=m
+CONFIG_SND_SOC_AMD_YC_MACH=m
+CONFIG_SND_SOC_ARIZONA=m
+CONFIG_SND_SOC_AUDIO_IIO_AUX=m
+CONFIG_SND_SOC_AW8738=m
+CONFIG_SND_SOC_AW87390=m
+CONFIG_SND_SOC_AW88166=m
+CONFIG_SND_SOC_AW88261=m
+CONFIG_SND_SOC_AW88395_LIB=m
+CONFIG_SND_SOC_AW88395=m
+CONFIG_SND_SOC_AW88399=m
+CONFIG_SND_SOC_BD28623=m
+CONFIG_SND_SOC_CHV3_CODEC=m
+CONFIG_SND_SOC_CHV3_I2S=m
+CONFIG_SND_SOC_COMPRESS=y
+CONFIG_SND_SOC_CROS_EC_CODEC=m
+CONFIG_SND_SOC_CS35L32=m
+CONFIG_SND_SOC_CS35L33=m
+CONFIG_SND_SOC_CS35L34=m
+CONFIG_SND_SOC_CS35L35=m
+CONFIG_SND_SOC_CS35L36=m
+CONFIG_SND_SOC_CS35L41_I2C=m
+CONFIG_SND_SOC_CS35L41_LIB=m
+CONFIG_SND_SOC_CS35L41=m
+CONFIG_SND_SOC_CS35L41_SPI=m
+CONFIG_SND_SOC_CS35L45_I2C=m
+CONFIG_SND_SOC_CS35L45=m
+CONFIG_SND_SOC_CS35L45_SPI=m
+CONFIG_SND_SOC_CS35L56_I2C=m
+CONFIG_SND_SOC_CS35L56=m
+CONFIG_SND_SOC_CS35L56_SDW=m
+CONFIG_SND_SOC_CS35L56_SHARED=m
+CONFIG_SND_SOC_CS35L56_SPI=m
+CONFIG_SND_SOC_CS40L50=m
+CONFIG_SND_SOC_CS4234=m
+CONFIG_SND_SOC_CS4265=m
+CONFIG_SND_SOC_CS4270=m
+CONFIG_SND_SOC_CS4271_I2C=m
+CONFIG_SND_SOC_CS4271=m
+CONFIG_SND_SOC_CS4271_SPI=m
+CONFIG_SND_SOC_CS42L42_CORE=m
+CONFIG_SND_SOC_CS42L42=m
+CONFIG_SND_SOC_CS42L42_SDW=m
+CONFIG_SND_SOC_CS42L43=m
+CONFIG_SND_SOC_CS42L43_SDW=m
+CONFIG_SND_SOC_CS42L51_I2C=m
+CONFIG_SND_SOC_CS42L51=m
+CONFIG_SND_SOC_CS42L52=m
+CONFIG_SND_SOC_CS42L56=m
+CONFIG_SND_SOC_CS42L73=m
+CONFIG_SND_SOC_CS42L83=m
+CONFIG_SND_SOC_CS42XX8_I2C=m
+CONFIG_SND_SOC_CS42XX8=m
+CONFIG_SND_SOC_CS43130=m
+CONFIG_SND_SOC_CS4341=m
+CONFIG_SND_SOC_CS4349=m
+CONFIG_SND_SOC_CS530X_I2C=m
+CONFIG_SND_SOC_CS53L30=m
+CONFIG_SND_SOC_CX2072X=m
+CONFIG_SND_SOC_DA7213=m
+CONFIG_SND_SOC_DA7219=m
+CONFIG_SND_SOC_DMIC=m
+CONFIG_SND_SOC_ES7134=m
+CONFIG_SND_SOC_ES7241=m
+CONFIG_SND_SOC_ES8311=m
+CONFIG_SND_SOC_ES8316=m
+CONFIG_SND_SOC_ES8326=m
+CONFIG_SND_SOC_ES8328_I2C=m
+CONFIG_SND_SOC_ES8328=m
+CONFIG_SND_SOC_ES8328_SPI=m
+CONFIG_SND_SOC_FRAMER=m
+CONFIG_SND_SOC_FS210X=m
+CONFIG_SND_SOC_FSL_ASRC=m
+CONFIG_SND_SOC_FSL_AUDMIX=m
+CONFIG_SND_SOC_FSL_EASRC=m
+CONFIG_SND_SOC_FSL_ESAI=m
+CONFIG_SND_SOC_FSL_MICFIL=m
+CONFIG_SND_SOC_FSL_MQS=m
+CONFIG_SND_SOC_FSL_RPMSG=m
+CONFIG_SND_SOC_FSL_SAI=m
+CONFIG_SND_SOC_FSL_SPDIF=m
+CONFIG_SND_SOC_FSL_SSI=m
+CONFIG_SND_SOC_FSL_UTILS=m
+CONFIG_SND_SOC_FSL_XCVR=m
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_GTM601=m
+CONFIG_SND_SOC_HDAC_HDA=m
+CONFIG_SND_SOC_HDAC_HDMI=m
+CONFIG_SND_SOC_HDA=m
+CONFIG_SND_SOC_HDMI_CODEC=m
+CONFIG_SND_SOC_I2C_AND_SPI=m
+CONFIG_SND_SOC_ICS43432=m
+CONFIG_SND_SOC_IDT821034=m
+CONFIG_SND_SOC_IMG_I2S_IN=m
+CONFIG_SND_SOC_IMG_I2S_OUT=m
+CONFIG_SND_SOC_IMG_PARALLEL_OUT=m
+CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m
+CONFIG_SND_SOC_IMG_SPDIF_IN=m
+CONFIG_SND_SOC_IMG_SPDIF_OUT=m
+CONFIG_SND_SOC_IMG=y
+CONFIG_SND_SOC_IMX_AUDMUX=m
+CONFIG_SND_SOC_INNO_RK3036=m
+CONFIG_SND_SOC_INTEL_APL=m
+CONFIG_SND_SOC_INTEL_AVS=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_ES8336=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98927=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_PCM3168A=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_PROBE=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_RT274=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_RT286=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_RT298=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_RT5514=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_RT5640=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_RT5663=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682=m
+CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567=m
+CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH=m
+CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH=m
+CONFIG_SND_SOC_INTEL_BROADWELL_MACH=m
+CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_COMMON=m
+CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH=m
+CONFIG_SND_SOC_INTEL_BXT_RT298_MACH=m
+CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH=m
+CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH=m
+CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH=m
+CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH=m
+CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=m
+CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH=m
+CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH=m
+CONFIG_SND_SOC_INTEL_CATPT=m
+CONFIG_SND_SOC_INTEL_CFL=m
+CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH=m
+CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH=m
+CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH=m
+CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=m
+CONFIG_SND_SOC_INTEL_CML_H=m
+CONFIG_SND_SOC_INTEL_CML_LP_DA7219_MAX98357A_MACH=m
+CONFIG_SND_SOC_INTEL_CML_LP=m
+CONFIG_SND_SOC_INTEL_CNL=m
+CONFIG_SND_SOC_INTEL_DA7219_MAX98357A_GENERIC=m
+CONFIG_SND_SOC_INTEL_EHL_RT5660_MACH=m
+CONFIG_SND_SOC_INTEL_GLK_DA7219_MAX98357A_MACH=m
+CONFIG_SND_SOC_INTEL_GLK=m
+CONFIG_SND_SOC_INTEL_GLK_RT5682_MAX98357A_MACH=m
+CONFIG_SND_SOC_INTEL_HASWELL_MACH=m
+CONFIG_SND_SOC_INTEL_HDA_DSP_COMMON=m
+CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98357A_MACH=m
+CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98927_MACH=m
+CONFIG_SND_SOC_INTEL_KBL=m
+CONFIG_SND_SOC_INTEL_KBL_RT5660_MACH=m
+CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH=m
+CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH=m
+CONFIG_SND_SOC_INTEL_MACH=y
+CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH=m
+CONFIG_SND_SOC_INTEL_SKL=m
+CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH=m
+CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH=m
+CONFIG_SND_SOC_INTEL_SKL_RT286_MACH=m
+CONFIG_SND_SOC_INTEL_SKYLAKE_COMMON=m
+CONFIG_SND_SOC_INTEL_SKYLAKE_FAMILY=m
+CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC=y
+CONFIG_SND_SOC_INTEL_SKYLAKE=m
+CONFIG_SND_SOC_INTEL_SKYLAKE_SSP_CLK=m
+CONFIG_SND_SOC_INTEL_SOF_CIRRUS_COMMON=m
+CONFIG_SND_SOC_INTEL_SOF_CML_RT1011_RT5682_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_CS42L42_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_DA7219_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_DA7219_MAX98373_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_ES8336_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_MAXIM_COMMON=m
+CONFIG_SND_SOC_INTEL_SOF_NAU8825_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_REALTEK_COMMON=m
+CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_SSP_AMP_MACH=m
+CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH=m
+CONFIG_SND_SOC_INTEL_SST=m
+CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y
+CONFIG_SND_SOC_LPASS_MACRO_COMMON=m
+CONFIG_SND_SOC_LPASS_RX_MACRO=m
+CONFIG_SND_SOC_LPASS_TX_MACRO=m
+CONFIG_SND_SOC_LPASS_VA_MACRO=m
+CONFIG_SND_SOC_LPASS_WSA_MACRO=m
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_MAX9759=m
+CONFIG_SND_SOC_MAX98088=m
+CONFIG_SND_SOC_MAX98090=m
+CONFIG_SND_SOC_MAX98357A=m
+CONFIG_SND_SOC_MAX98363=m
+CONFIG_SND_SOC_MAX98373_I2C=m
+CONFIG_SND_SOC_MAX98373=m
+CONFIG_SND_SOC_MAX98373_SDW=m
+CONFIG_SND_SOC_MAX98388=m
+CONFIG_SND_SOC_MAX98390=m
+CONFIG_SND_SOC_MAX98396=m
+CONFIG_SND_SOC_MAX98504=m
+CONFIG_SND_SOC_MAX98520=m
+CONFIG_SND_SOC_MAX9860=m
+CONFIG_SND_SOC_MAX9867=m
+CONFIG_SND_SOC_MAX98927=m
+CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
+CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
+CONFIG_SND_SOC_MT6351=m
+CONFIG_SND_SOC_MT6357=m
+CONFIG_SND_SOC_MT6358=m
+CONFIG_SND_SOC_MT6660=m
+CONFIG_SND_SOC_MTK_BTCVSD=m
+CONFIG_SND_SOC_NAU8315=m
+CONFIG_SND_SOC_NAU8540=m
+CONFIG_SND_SOC_NAU8810=m
+CONFIG_SND_SOC_NAU8821=m
+CONFIG_SND_SOC_NAU8822=m
+CONFIG_SND_SOC_NAU8824=m
+CONFIG_SND_SOC_NAU8825=m
+CONFIG_SND_SOC_PCM1681=m
+CONFIG_SND_SOC_PCM1754=m
+CONFIG_SND_SOC_PCM1789_I2C=m
+CONFIG_SND_SOC_PCM1789=m
+CONFIG_SND_SOC_PCM179X_I2C=m
+CONFIG_SND_SOC_PCM179X=m
+CONFIG_SND_SOC_PCM179X_SPI=m
+CONFIG_SND_SOC_PCM186X_I2C=m
+CONFIG_SND_SOC_PCM186X=m
+CONFIG_SND_SOC_PCM186X_SPI=m
+CONFIG_SND_SOC_PCM3060_I2C=m
+CONFIG_SND_SOC_PCM3060=m
+CONFIG_SND_SOC_PCM3060_SPI=m
+CONFIG_SND_SOC_PCM3168A_I2C=m
+CONFIG_SND_SOC_PCM3168A=m
+CONFIG_SND_SOC_PCM3168A_SPI=m
+CONFIG_SND_SOC_PCM5102A=m
+CONFIG_SND_SOC_PCM512x_I2C=m
+CONFIG_SND_SOC_PCM512x=m
+CONFIG_SND_SOC_PCM512x_SPI=m
+CONFIG_SND_SOC_PCM6240=m
+CONFIG_SND_SOC_PEB2466=m
+CONFIG_SND_SOC_PM4125_SDW=m
+CONFIG_SND_SOC_RK3328=m
+CONFIG_SND_SOC_RL6231=m
+CONFIG_SND_SOC_RL6347A=m
+CONFIG_SND_SOC_RT1011=m
+CONFIG_SND_SOC_RT1015=m
+CONFIG_SND_SOC_RT1015P=m
+CONFIG_SND_SOC_RT1017_SDCA_SDW=m
+CONFIG_SND_SOC_RT1019=m
+CONFIG_SND_SOC_RT1308=m
+CONFIG_SND_SOC_RT1308_SDW=m
+CONFIG_SND_SOC_RT1316_SDW=m
+CONFIG_SND_SOC_RT1318_SDW=m
+CONFIG_SND_SOC_RT1320_SDW=m
+CONFIG_SND_SOC_RT274=m
+CONFIG_SND_SOC_RT286=m
+CONFIG_SND_SOC_RT298=m
+CONFIG_SND_SOC_RT5514=m
+CONFIG_SND_SOC_RT5514_SPI=m
+CONFIG_SND_SOC_RT5616=m
+CONFIG_SND_SOC_RT5631=m
+CONFIG_SND_SOC_RT5640=m
+CONFIG_SND_SOC_RT5645=m
+CONFIG_SND_SOC_RT5651=m
+CONFIG_SND_SOC_RT5659=m
+CONFIG_SND_SOC_RT5660=m
+CONFIG_SND_SOC_RT5663=m
+CONFIG_SND_SOC_RT5670=m
+CONFIG_SND_SOC_RT5677=m
+CONFIG_SND_SOC_RT5677_SPI=m
+CONFIG_SND_SOC_RT5682_I2C=m
+CONFIG_SND_SOC_RT5682=m
+CONFIG_SND_SOC_RT5682_SDW=m
+CONFIG_SND_SOC_RT5682S=m
+CONFIG_SND_SOC_RT700=m
+CONFIG_SND_SOC_RT700_SDW=m
+CONFIG_SND_SOC_RT711=m
+CONFIG_SND_SOC_RT711_SDCA_SDW=m
+CONFIG_SND_SOC_RT711_SDW=m
+CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW=m
+CONFIG_SND_SOC_RT712_SDCA_SDW=m
+CONFIG_SND_SOC_RT715=m
+CONFIG_SND_SOC_RT715_SDCA_SDW=m
+CONFIG_SND_SOC_RT715_SDW=m
+CONFIG_SND_SOC_RT722_SDCA_SDW=m
+CONFIG_SND_SOC_RT9120=m
+CONFIG_SND_SOC_RTQ9128=m
+CONFIG_SND_SOC_SDCA_HID=y
+CONFIG_SND_SOC_SDCA_IRQ=y
+CONFIG_SND_SOC_SDW_MOCKUP=m
+CONFIG_SND_SOC_SGTL5000=m
+CONFIG_SND_SOC_SI476X=m
+CONFIG_SND_SOC_SIGMADSP_I2C=m
+CONFIG_SND_SOC_SIGMADSP=m
+CONFIG_SND_SOC_SIGMADSP_REGMAP=m
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
+CONFIG_SND_SOC_SIMPLE_MUX=m
+CONFIG_SND_SOC_SMA1303=m
+CONFIG_SND_SOC_SOF_ACPI_DEV=m
+CONFIG_SND_SOC_SOF_ACPI=m
+CONFIG_SND_SOC_SOF_ALDERLAKE=m
+CONFIG_SND_SOC_SOF_AMD_ACP63=m
+CONFIG_SND_SOC_SOF_AMD_ACP70=m
+CONFIG_SND_SOC_SOF_AMD_COMMON=m
+CONFIG_SND_SOC_SOF_AMD_REMBRANDT=m
+CONFIG_SND_SOC_SOF_AMD_RENOIR=m
+CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE=m
+CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m
+CONFIG_SND_SOC_SOF_AMD_VANGOGH=m
+CONFIG_SND_SOC_SOF_APOLLOLAKE=m
+CONFIG_SND_SOC_SOF_BAYTRAIL=m
+CONFIG_SND_SOC_SOF_BROADWELL=m
+CONFIG_SND_SOC_SOF_CANNONLAKE=m
+CONFIG_SND_SOC_SOF_CLIENT=m
+CONFIG_SND_SOC_SOF_COFFEELAKE=m
+CONFIG_SND_SOC_SOF_COMETLAKE=m
+CONFIG_SND_SOC_SOF_DEBUG_PROBES=m
+CONFIG_SND_SOC_SOF_ELKHARTLAKE=m
+CONFIG_SND_SOC_SOF_GEMINILAKE=m
+CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC=y
+CONFIG_SND_SOC_SOF_HDA_COMMON=m
+CONFIG_SND_SOC_SOF_HDA_LINK_BASELINE=m
+CONFIG_SND_SOC_SOF_HDA_LINK=y
+CONFIG_SND_SOC_SOF_HDA=m
+CONFIG_SND_SOC_SOF_HDA_MLINK=m
+CONFIG_SND_SOC_SOF_HDA_PROBES=m
+CONFIG_SND_SOC_SOF_ICELAKE=m
+CONFIG_SND_SOC_SOF_INTEL_APL=m
+CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP=m
+CONFIG_SND_SOC_SOF_INTEL_CNL=m
+CONFIG_SND_SOC_SOF_INTEL_COMMON=m
+CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC=m
+CONFIG_SND_SOC_SOF_INTEL_ICL=m
+CONFIG_SND_SOC_SOF_INTEL_IPC4=y
+CONFIG_SND_SOC_SOF_INTEL_MTL=m
+CONFIG_SND_SOC_SOF_INTEL_SKL=m
+CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE_LINK_BASELINE=m
+CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE=m
+CONFIG_SND_SOC_SOF_INTEL_TGL=m
+CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL=y
+CONFIG_SND_SOC_SOF_IPC3=y
+CONFIG_SND_SOC_SOF_JASPERLAKE=m
+CONFIG_SND_SOC_SOF_KABYLAKE=m
+CONFIG_SND_SOC_SOF_LUNARLAKE=m
+CONFIG_SND_SOC_SOF=m
+CONFIG_SND_SOC_SOF_MERRIFIELD=m
+CONFIG_SND_SOC_SOF_METEORLAKE=m
+CONFIG_SND_SOC_SOF_PANTHERLAKE=m
+CONFIG_SND_SOC_SOF_PCI_DEV=m
+CONFIG_SND_SOC_SOF_PCI=m
+CONFIG_SND_SOC_SOF_PROBE_WORK_QUEUE=y
+CONFIG_SND_SOC_SOF_SKYLAKE=m
+CONFIG_SND_SOC_SOF_TIGERLAKE=m
+CONFIG_SND_SOC_SOF_TOPLEVEL=y
+CONFIG_SND_SOC_SOF_XTENSA=m
+CONFIG_SND_SOC_SPDIF=m
+CONFIG_SND_SOC_SRC4XXX_I2C=m
+CONFIG_SND_SOC_SRC4XXX=m
+CONFIG_SND_SOC_SSM2305=m
+CONFIG_SND_SOC_SSM2518=m
+CONFIG_SND_SOC_SSM2602_I2C=m
+CONFIG_SND_SOC_SSM2602=m
+CONFIG_SND_SOC_SSM2602_SPI=m
+CONFIG_SND_SOC_SSM4567=m
+CONFIG_SND_SOC_STA32X=m
+CONFIG_SND_SOC_STA350=m
+CONFIG_SND_SOC_STI_SAS=m
+CONFIG_SND_SOC_TAS2552=m
+CONFIG_SND_SOC_TAS2562=m
+CONFIG_SND_SOC_TAS2764=m
+CONFIG_SND_SOC_TAS2770=m
+CONFIG_SND_SOC_TAS2780=m
+CONFIG_SND_SOC_TAS2781_COMLIB=m
+CONFIG_SND_SOC_TAS2781_FMWLIB=m
+CONFIG_SND_SOC_TAS2781_I2C=m
+CONFIG_SND_SOC_TAS2783_SDW=m
+CONFIG_SND_SOC_TAS5086=m
+CONFIG_SND_SOC_TAS571X=m
+CONFIG_SND_SOC_TAS5720=m
+CONFIG_SND_SOC_TAS5805M=m
+CONFIG_SND_SOC_TAS6424=m
+CONFIG_SND_SOC_TDA7419=m
+CONFIG_SND_SOC_TFA9879=m
+CONFIG_SND_SOC_TFA989X=m
+CONFIG_SND_SOC_TLV320ADC3XXX=m
+CONFIG_SND_SOC_TLV320ADCX140=m
+CONFIG_SND_SOC_TLV320AIC23_I2C=m
+CONFIG_SND_SOC_TLV320AIC23=m
+CONFIG_SND_SOC_TLV320AIC23_SPI=m
+CONFIG_SND_SOC_TLV320AIC31XX=m
+CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
+CONFIG_SND_SOC_TLV320AIC32X4=m
+CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
+CONFIG_SND_SOC_TLV320AIC3X_I2C=m
+CONFIG_SND_SOC_TLV320AIC3X=m
+CONFIG_SND_SOC_TLV320AIC3X_SPI=m
+CONFIG_SND_SOC_TOPOLOGY=y
+CONFIG_SND_SOC_TPA6130A2=m
+CONFIG_SND_SOC_TS3A227E=m
+CONFIG_SND_SOC_TSCS42XX=m
+CONFIG_SND_SOC_TSCS454=m
+CONFIG_SND_SOC_UDA1334=m
+CONFIG_SND_SOC_WCD9335=m
+CONFIG_SND_SOC_WCD934X=m
+CONFIG_SND_SOC_WCD937X_SDW=m
+CONFIG_SND_SOC_WCD938X=m
+CONFIG_SND_SOC_WCD938X_SDW=m
+CONFIG_SND_SOC_WCD939X_SDW=m
+CONFIG_SND_SOC_WCD_MBHC=m
+CONFIG_SND_SOC_WM5102=m
+CONFIG_SND_SOC_WM8510=m
+CONFIG_SND_SOC_WM8523=m
+CONFIG_SND_SOC_WM8524=m
+CONFIG_SND_SOC_WM8580=m
+CONFIG_SND_SOC_WM8711=m
+CONFIG_SND_SOC_WM8728=m
+CONFIG_SND_SOC_WM8731_I2C=m
+CONFIG_SND_SOC_WM8731=m
+CONFIG_SND_SOC_WM8731_SPI=m
+CONFIG_SND_SOC_WM8737=m
+CONFIG_SND_SOC_WM8741=m
+CONFIG_SND_SOC_WM8750=m
+CONFIG_SND_SOC_WM8753=m
+CONFIG_SND_SOC_WM8770=m
+CONFIG_SND_SOC_WM8776=m
+CONFIG_SND_SOC_WM8782=m
+CONFIG_SND_SOC_WM8804_I2C=m
+CONFIG_SND_SOC_WM8804=m
+CONFIG_SND_SOC_WM8804_SPI=m
+CONFIG_SND_SOC_WM8903=m
+CONFIG_SND_SOC_WM8904=m
+CONFIG_SND_SOC_WM8940=m
+CONFIG_SND_SOC_WM8960=m
+CONFIG_SND_SOC_WM8961=m
+CONFIG_SND_SOC_WM8962=m
+CONFIG_SND_SOC_WM8974=m
+CONFIG_SND_SOC_WM8978=m
+CONFIG_SND_SOC_WM8985=m
+CONFIG_SND_SOC_WM_ADSP=m
+CONFIG_SND_SOC_WSA881X=m
+CONFIG_SND_SOC_WSA883X=m
+CONFIG_SND_SOC_WSA884X=m
+CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
+CONFIG_SND_SOC_XILINX_I2S=m
+CONFIG_SND_SOC_XILINX_SPDIF=m
+CONFIG_SND_SOC_XTFPGA_I2S=m
+CONFIG_SND_SOC_ZL38060=m
+CONFIG_SND_SONICVIBES=m
+CONFIG_SND_SPI=y
+CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI=m
+CONFIG_SND_SST_ATOM_HIFI2_PLATFORM=m
+CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI=m
+CONFIG_SND_SYNTH_EMUX=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_TRIDENT=m
+CONFIG_SND_UMP_LEGACY_RAWMIDI=y
+CONFIG_SND_UMP=m
+CONFIG_SND_USB_6FIRE=m
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_AUDIO_MIDI_V2=y
+CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_HIFACE=m
+CONFIG_SND_USB_LINE6=m
+CONFIG_SND_USB_PODHD=m
+CONFIG_SND_USB_POD=m
+CONFIG_SND_USB_TONEPORT=m
+CONFIG_SND_USB_UA101=m
+CONFIG_SND_USB_US122L=m
+CONFIG_SND_USB_US144MKII=m
+CONFIG_SND_USB_USX2Y=m
+CONFIG_SND_USB_VARIAX=m
+CONFIG_SND_USB=y
+CONFIG_SND_UTIMER=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VIA82XX=m
+CONFIG_SND_VIA82XX_MODEM=m
+CONFIG_SND_VIRMIDI=m
+CONFIG_SND_VIRTIO=m
+CONFIG_SND_VIRTUOSO=m
+CONFIG_SND_VMASTER=y
+CONFIG_SND_VX222=m
+CONFIG_SND_VX_LIB=m
+CONFIG_SND_VXPOCKET=m
+CONFIG_SND_X86=y
+CONFIG_SND_YMFPCI=m
+CONFIG_SNET_VDPA=m
+CONFIG_SOC_BUS=y
+CONFIG_SOCK_CGROUP_DATA=y
+CONFIG_SOCK_VALIDATE_XMIT=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOFT_WATCHDOG=m
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_SONY_LAPTOP=m
+CONFIG_SONYPI_COMPAT=y
+CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUNDWIRE_AMD=m
+CONFIG_SOUNDWIRE_CADENCE=m
+CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=m
+CONFIG_SOUNDWIRE_INTEL=m
+CONFIG_SOUNDWIRE_QCOM=m
+CONFIG_SOUNDWIRE=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPECULATION_MITIGATIONS=y
+CONFIG_SPI_ALTERA_CORE=m
+CONFIG_SPI_ALTERA_DFL=m
+CONFIG_SPI_ALTERA=m
+CONFIG_SPI_AMD=m
+CONFIG_SPI_AXI_SPI_ENGINE=m
+CONFIG_SPI_BITBANG=m
+CONFIG_SPI_BUTTERFLY=m
+CONFIG_SPI_CADENCE=m
+CONFIG_SPI_CH341=m
+CONFIG_SPI_CS42L43=m
+CONFIG_SPI_DESIGNWARE=m
+CONFIG_SPI_DLN2=m
+CONFIG_SPI_DW_MMIO=m
+CONFIG_SPI_DW_PCI=m
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_GPIO=m
+CONFIG_SPI_INTEL=m
+CONFIG_SPI_INTEL_PCI=m
+CONFIG_SPI_INTEL_PLATFORM=m
+CONFIG_SPI_KSPI2=m
+CONFIG_SPI_LANTIQ_SSC=m
+CONFIG_SPI_LJCA=m
+CONFIG_SPI_LM70_LLP=m
+CONFIG_SPI_LOOPBACK_TEST=m
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_MICROCHIP_CORE=m
+CONFIG_SPI_MICROCHIP_CORE_QSPI=m
+CONFIG_SPI_MUX=m
+CONFIG_SPI_MXIC=m
+CONFIG_SPI_OC_TINY=m
+CONFIG_SPI_OFFLOAD_TRIGGER_ADI_UTIL_SD=m
+CONFIG_SPI_OFFLOAD_TRIGGER_PWM=m
+CONFIG_SPI_PCI1XXXX=m
+CONFIG_SPI_PXA2XX=m
+CONFIG_SPI_PXA2XX_PCI=m
+CONFIG_SPI_SC18IS602=m
+CONFIG_SPI_SIFIVE=m
+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
+CONFIG_SPI_SLAVE_TIME=m
+CONFIG_SPI_SLAVE=y
+CONFIG_SPI_SPIDEV=m
+CONFIG_SPI_TLE62X0=m
+CONFIG_SPI_VIRTIO=m
+CONFIG_SPI_XCOMM=m
+CONFIG_SPI_XILINX=m
+CONFIG_SPI=y
+CONFIG_SPI_ZYNQMP_GQSPI=m
+CONFIG_SPMI_HISI3670=m
+CONFIG_SPMI=m
+CONFIG_SPS30_I2C=m
+CONFIG_SPS30=m
+CONFIG_SPS30_SERIAL=m
+CONFIG_SRAM=y
+CONFIG_SRF04=m
+CONFIG_SRF08=m
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_BLOCKIO=y
+CONFIG_SSB_DRIVER_GPIO=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB=m
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
+CONFIG_SSB_PCMCIAHOST=y
+CONFIG_SSB_SDIOHOST_POSSIBLE=y
+CONFIG_SSB_SDIOHOST=y
+CONFIG_SSB_SPROM=y
+CONFIG_SSFDC=m
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKTRACE=y
+CONFIG_STAGING_MEDIA_DEPRECATED=y
+CONFIG_STAGING_MEDIA=y
+CONFIG_STAGING=y
+CONFIG_STANDALONE=y
+CONFIG_STE10XP=m
 CONFIG_STK3310=m
-CONFIG_ST_UVIS25=m
+CONFIG_STK8312=m
+CONFIG_STK8BA50=m
+CONFIG_STM=m
+CONFIG_STM_PROTO_BASIC=m
+CONFIG_STM_PROTO_SYS_T=m
+CONFIG_STM_SOURCE_CONSOLE=m
+CONFIG_STM_SOURCE_HEARTBEAT=m
+CONFIG_STREAM_PARSER=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
 CONFIG_ST_UVIS25_I2C=m
+CONFIG_ST_UVIS25=m
 CONFIG_ST_UVIS25_SPI=m
-CONFIG_TCS3414=m
-CONFIG_TCS3472=m
-CONFIG_SENSORS_TSL2563=m
-CONFIG_TSL2583=m
-CONFIG_TSL2591=m
-CONFIG_TSL2772=m
-CONFIG_TSL4531=m
-CONFIG_US5182D=m
-CONFIG_VCNL4000=m
-CONFIG_VCNL4035=m
-CONFIG_VEML6030=m
-CONFIG_VEML6070=m
-CONFIG_VL6180=m
-CONFIG_ZOPT2201=m
-# end of Light sensors
-
-#
-# Magnetometer sensors
-#
-CONFIG_AK8975=m
-CONFIG_AK09911=m
-CONFIG_BMC150_MAGN=m
-CONFIG_BMC150_MAGN_I2C=m
-CONFIG_BMC150_MAGN_SPI=m
-CONFIG_MAG3110=m
-CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
-CONFIG_MMC35240=m
-CONFIG_IIO_ST_MAGN_3AXIS=m
-CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
-CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
-CONFIG_SENSORS_HMC5843=m
-CONFIG_SENSORS_HMC5843_I2C=m
-CONFIG_SENSORS_HMC5843_SPI=m
-CONFIG_SENSORS_RM3100=m
-CONFIG_SENSORS_RM3100_I2C=m
-CONFIG_SENSORS_RM3100_SPI=m
-CONFIG_YAMAHA_YAS530=m
-# end of Magnetometer sensors
-
-#
-# Multiplexers
-#
-# end of Multiplexers
-
-#
-# Inclinometer sensors
-#
-CONFIG_HID_SENSOR_INCLINOMETER_3D=m
-CONFIG_HID_SENSOR_DEVICE_ROTATION=m
-# end of Inclinometer sensors
-
-#
-# Triggers - standalone
-#
-CONFIG_IIO_HRTIMER_TRIGGER=m
-CONFIG_IIO_INTERRUPT_TRIGGER=m
-CONFIG_IIO_TIGHTLOOP_TRIGGER=m
-CONFIG_IIO_SYSFS_TRIGGER=m
-# end of Triggers - standalone
-
-#
-# Linear and angular position sensors
-#
-CONFIG_IQS624_POS=m
-CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
-# end of Linear and angular position sensors
-
-#
-# Digital potentiometers
-#
-CONFIG_AD5110=m
-CONFIG_AD5272=m
-CONFIG_DS1803=m
-CONFIG_MAX5432=m
-CONFIG_MAX5481=m
-CONFIG_MAX5487=m
-CONFIG_MCP4018=m
-CONFIG_MCP4131=m
-CONFIG_MCP4531=m
-CONFIG_MCP41010=m
-CONFIG_TPL0102=m
-# end of Digital potentiometers
-
-#
-# Digital potentiostats
-#
-CONFIG_LMP91000=m
-# end of Digital potentiostats
-
-#
-# Pressure sensors
-#
-CONFIG_ABP060MG=m
-CONFIG_BMP280=m
-CONFIG_BMP280_I2C=m
-CONFIG_BMP280_SPI=m
-CONFIG_IIO_CROS_EC_BARO=m
-CONFIG_DLHL60D=m
-CONFIG_DPS310=m
-CONFIG_HID_SENSOR_PRESS=m
-CONFIG_HP03=m
-CONFIG_ICP10100=m
-CONFIG_MPL115=m
-CONFIG_MPL115_I2C=m
-CONFIG_MPL115_SPI=m
-CONFIG_MPL3115=m
-CONFIG_MS5611=m
-CONFIG_MS5611_I2C=m
-CONFIG_MS5611_SPI=m
-CONFIG_MS5637=m
-CONFIG_IIO_ST_PRESS=m
-CONFIG_IIO_ST_PRESS_I2C=m
-CONFIG_IIO_ST_PRESS_SPI=m
-CONFIG_T5403=m
-CONFIG_HP206C=m
-CONFIG_ZPA2326=m
-CONFIG_ZPA2326_I2C=m
-CONFIG_ZPA2326_SPI=m
-# end of Pressure sensors
-
-#
-# Lightning sensors
-#
-CONFIG_AS3935=m
-# end of Lightning sensors
-
-#
-# Proximity and distance sensors
-#
-CONFIG_CROS_EC_MKBP_PROXIMITY=m
-CONFIG_ISL29501=m
-CONFIG_LIDAR_LITE_V2=m
-CONFIG_MB1232=m
-CONFIG_PING=m
-CONFIG_RFD77402=m
-CONFIG_SRF04=m
+CONFIG_SUNGEM_PHY=m
+CONFIG_SUN_PARTITION=y
+CONFIG_SURFACE_3_POWER_OPREGION=m
+CONFIG_SURFACE3_WMI=m
+CONFIG_SURFACE_ACPI_NOTIFY=m
+CONFIG_SURFACE_AGGREGATOR_BUS=y
+CONFIG_SURFACE_AGGREGATOR_CDEV=m
+CONFIG_SURFACE_AGGREGATOR_HUB=m
+CONFIG_SURFACE_AGGREGATOR=m
+CONFIG_SURFACE_AGGREGATOR_REGISTRY=m
+CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m
+CONFIG_SURFACE_DTX=m
+CONFIG_SURFACE_GPE=m
+CONFIG_SURFACE_HOTPLUG=m
+CONFIG_SURFACE_KBD=m
+CONFIG_SURFACE_PLATFORM_PROFILE=m
+CONFIG_SURFACE_PLATFORMS=y
+CONFIG_SURFACE_PRO3_BUTTON=m
+CONFIG_SVC_I3C_MASTER=m
 CONFIG_SX9310=m
 CONFIG_SX9324=m
 CONFIG_SX9360=m
 CONFIG_SX9500=m
-CONFIG_SRF08=m
-CONFIG_VCNL3020=m
-CONFIG_VL53L0X_I2C=m
-# end of Proximity and distance sensors
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S90=m
-CONFIG_AD2S1200=m
-# end of Resolver to digital converters
-
-#
-# Temperature sensors
-#
-CONFIG_IQS620AT_TEMP=m
-CONFIG_LTC2983=m
-CONFIG_MAXIM_THERMOCOUPLE=m
-CONFIG_HID_SENSOR_TEMP=m
-CONFIG_MLX90614=m
-CONFIG_MLX90632=m
+CONFIG_SX_COMMON=m
+CONFIG_SYNC_FILE=y
+CONFIG_SYNCLINK_GT=m
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFB_SIMPLEFB=y
+CONFIG_SYSFB=y
+CONFIG_SYSTEM76_ACPI=m
+CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y
+CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
+CONFIG_SYSTEM_BLACKLIST_KEYRING=y
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSV68_PARTITION=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_T5403=m
+CONFIG_TABLET_SERIAL_WACOM4=m
+CONFIG_TABLET_USB_ACECAD=m
+CONFIG_TABLET_USB_AIPTEK=m
+CONFIG_TABLET_USB_HANWANG=m
+CONFIG_TABLET_USB_KBTAB=m
+CONFIG_TABLET_USB_PEGASUS=m
+CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y
+CONFIG_TAHVO_USB=m
+CONFIG_TAP=m
+CONFIG_TARGET_CORE=m
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASKS_RCU=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_XACCT=y
+CONFIG_TCG_ATMEL=m
+CONFIG_TCG_CRB=m
+CONFIG_TCG_INFINEON=m
+CONFIG_TCG_NSC=m
+CONFIG_TCG_SVSM=m
+CONFIG_TCG_TIS_CORE=m
+CONFIG_TCG_TIS_I2C_ATMEL=m
+CONFIG_TCG_TIS_I2C_CR50=m
+CONFIG_TCG_TIS_I2C_INFINEON=m
+CONFIG_TCG_TIS_I2C=m
+CONFIG_TCG_TIS_I2C_NUVOTON=m
+CONFIG_TCG_TIS=m
+CONFIG_TCG_TIS_SPI=m
+CONFIG_TCG_TIS_ST33ZP24_I2C=m
+CONFIG_TCG_TIS_ST33ZP24=m
+CONFIG_TCG_TIS_ST33ZP24_SPI=m
+CONFIG_TCG_TPM=m
+CONFIG_TCG_VTPM_PROXY=m
+CONFIG_TCM_FC=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_PSCSI=m
+CONFIG_TCM_QLA2XXX=m
+CONFIG_TCM_USER2=m
+CONFIG_TCS3414=m
+CONFIG_TCS3472=m
+CONFIG_TDX_GUEST_DRIVER=m
+CONFIG_TEE=m
+CONFIG_TELCLOCK=m
+CONFIG_TERANETICS_PHY=m
+CONFIG_TEST_ASYNC_DRIVER_PROBE=m
+CONFIG_TEST_LOCKUP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH=y
+CONFIG_THERMAL_ACPI=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=100
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_NETLINK=y
+CONFIG_THERMAL_STATISTICS=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL=y
+CONFIG_THINKPAD_ACPI_ALSA_SUPPORT=y
+CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y
+CONFIG_THINKPAD_ACPI=m
+CONFIG_THINKPAD_ACPI_VIDEO=y
+CONFIG_THINKPAD_LMI=m
+CONFIG_THP_SWAP=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TI_ADC081C=m
+CONFIG_TI_ADC0832=m
+CONFIG_TI_ADC084S021=m
+CONFIG_TI_ADC108S102=m
+CONFIG_TI_ADC12138=m
+CONFIG_TI_ADC128S052=m
+CONFIG_TI_ADC161S626=m
+CONFIG_TI_ADS1015=m
+CONFIG_TI_ADS1100=m
+CONFIG_TI_ADS1119=m
+CONFIG_TI_ADS124S08=m
+CONFIG_TI_ADS1298=m
+CONFIG_TI_ADS131E08=m
+CONFIG_TI_ADS7138=m
+CONFIG_TI_ADS7924=m
+CONFIG_TI_ADS7950=m
+CONFIG_TI_ADS8344=m
+CONFIG_TI_ADS8688=m
+CONFIG_TI_AM335X_ADC=m
+CONFIG_TI_DAC082S085=m
+CONFIG_TI_DAC5571=m
+CONFIG_TI_DAC7311=m
+CONFIG_TI_DAC7612=m
+CONFIG_TIFM_7XX1=m
+CONFIG_TIFM_CORE=m
+CONFIG_TI_LMP92064=m
+CONFIG_TINYDRM_HX8357D=m
+CONFIG_TINYDRM_ILI9163=m
+CONFIG_TINYDRM_ILI9225=m
+CONFIG_TINYDRM_ILI9341=m
+CONFIG_TINYDRM_ILI9486=m
+CONFIG_TINYDRM_MI0283QT=m
+CONFIG_TINYDRM_REPAPER=m
+CONFIG_TINYDRM_ST7586=m
+CONFIG_TINYDRM_ST7735R=m
+CONFIG_TI_ST=m
+CONFIG_TI_TLC4541=m
+CONFIG_TI_TMAG5273=m
+CONFIG_TI_TSC2046=m
+CONFIG_TMD_HERMES=m
 CONFIG_TMP006=m
 CONFIG_TMP007=m
 CONFIG_TMP117=m
-CONFIG_TSYS01=m
-CONFIG_TSYS02D=m
-CONFIG_MAX31856=m
-CONFIG_MAX31865=m
-# end of Temperature sensors
-
-CONFIG_NTB=m
-CONFIG_NTB_MSI=y
-CONFIG_NTB_AMD=m
-CONFIG_NTB_IDT=m
-CONFIG_NTB_INTEL=m
-CONFIG_NTB_EPF=m
-CONFIG_NTB_SWITCHTEC=m
-CONFIG_NTB_PINGPONG=m
-CONFIG_NTB_TOOL=m
-CONFIG_NTB_PERF=m
-CONFIG_NTB_MSI_TEST=m
-CONFIG_NTB_TRANSPORT=m
-CONFIG_VME_BUS=y
-
-#
-# VME Bridge Drivers
-#
-CONFIG_VME_CA91CX42=m
-CONFIG_VME_TSI148=m
-CONFIG_VME_FAKE=m
-
-#
-# VME Board Drivers
-#
-CONFIG_VMIVME_7805=m
-
-#
-# VME Device Drivers
-#
-CONFIG_VME_USER=m
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_PWM_DEBUG is not set
-CONFIG_PWM_CLK=m
-CONFIG_PWM_CROS_EC=m
-CONFIG_PWM_DWC=m
-CONFIG_PWM_IQS620A=m
-CONFIG_PWM_LP3943=m
-CONFIG_PWM_LPSS=m
-CONFIG_PWM_LPSS_PCI=m
-CONFIG_PWM_LPSS_PLATFORM=m
-CONFIG_PWM_PCA9685=m
-
-#
-# IRQ chip support
-#
-CONFIG_MADERA_IRQ=m
-# end of IRQ chip support
-
-CONFIG_IPACK_BUS=m
-CONFIG_BOARD_TPCI200=m
-CONFIG_SERIAL_IPOCTAL=m
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_SIMPLE=y
-CONFIG_RESET_TI_SYSCON=m
-CONFIG_RESET_TI_TPS380X=m
-
-#
-# PHY Subsystem
-#
-CONFIG_GENERIC_PHY=y
-CONFIG_USB_LGM_PHY=m
-CONFIG_PHY_CAN_TRANSCEIVER=m
-
-#
-# PHY drivers for Broadcom platforms
-#
-CONFIG_BCM_KONA_USB2_PHY=m
-# end of PHY drivers for Broadcom platforms
-
-CONFIG_PHY_PXA_28NM_HSIC=m
-CONFIG_PHY_PXA_28NM_USB2=m
-CONFIG_PHY_CPCAP_USB=m
-CONFIG_PHY_QCOM_USB_HS=m
-CONFIG_PHY_QCOM_USB_HSIC=m
-CONFIG_PHY_SAMSUNG_USB2=m
-CONFIG_PHY_TUSB1210=m
-CONFIG_PHY_INTEL_LGM_EMMC=m
-# end of PHY Subsystem
-
-CONFIG_POWERCAP=y
-CONFIG_INTEL_RAPL_CORE=m
-CONFIG_INTEL_RAPL=m
-# CONFIG_IDLE_INJECT is not set
-CONFIG_PECI=m
-CONFIG_PECI_CPU=m
-CONFIG_PECI_ASPEED=m
-CONFIG_SENSORS_PECI_CPUTEMP=m
-CONFIG_SENSORS_PECI_DIMMTEMP=m
-CONFIG_DTPM=y
-CONFIG_DTPM_CPU=y
-CONFIG_DTPM_DEVFREQ=y
-CONFIG_MCB=m
-CONFIG_MCB_PCI=m
-CONFIG_MCB_LPC=m
-
-#
-# Performance monitor support
-#
-# end of Performance monitor support
-
-CONFIG_RAS=y
-CONFIG_RAS_CEC=y
-# CONFIG_RAS_CEC_DEBUG is not set
-CONFIG_USB4=m
-# CONFIG_USB4_DEBUGFS_WRITE is not set
-# CONFIG_USB4_DMA_TEST is not set
-
-#
-# Android
-#
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=m
-CONFIG_ANDROID_BINDERFS=y
-CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
-# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
-# end of Android
-
-CONFIG_LIBNVDIMM=m
-CONFIG_BLK_DEV_PMEM=m
-CONFIG_ND_BLK=m
-CONFIG_ND_CLAIM=y
-CONFIG_ND_BTT=m
-CONFIG_BTT=y
-CONFIG_NVDIMM_KEYS=y
-CONFIG_DAX_DRIVER=y
-CONFIG_DAX=y
-CONFIG_DEV_DAX=m
-CONFIG_DEV_DAX_HMEM=m
-CONFIG_DEV_DAX_HMEM_DEVICES=y
-CONFIG_DEV_DAX_KMEM=m
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_RAVE_SP_EEPROM=m
-CONFIG_NVMEM_SPMI_SDAM=m
-CONFIG_RAVE_SP_EEPROM=m
-CONFIG_NVMEM_RMEM=m
-CONFIG_NVMEM_LAYERSCAPE_SFP=m
-CONFIG_NVMEM_MESON_EFUSE=m
-CONFIG_NVMEM_SPRD_EFUSE=m
-
-#
-# HW tracing support
-#
-CONFIG_STM=m
-CONFIG_STM_PROTO_BASIC=m
-CONFIG_STM_PROTO_SYS_T=m
-# CONFIG_STM_DUMMY is not set
-CONFIG_STM_SOURCE_CONSOLE=m
-CONFIG_STM_SOURCE_HEARTBEAT=m
-# CONFIG_STM_SOURCE_FTRACE is not set
-CONFIG_INTEL_TH=m
-CONFIG_INTEL_TH_PCI=m
-CONFIG_INTEL_TH_ACPI=m
-CONFIG_INTEL_TH_GTH=m
-CONFIG_INTEL_TH_STH=m
-CONFIG_INTEL_TH_MSU=m
-CONFIG_INTEL_TH_PTI=m
-CONFIG_HISI_PTT=m
-# CONFIG_INTEL_TH_DEBUG is not set
-# end of HW tracing support
-
-CONFIG_FPGA=m
-CONFIG_ALTERA_PR_IP_CORE=m
-CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
-CONFIG_FPGA_MGR_ALTERA_CVP=m
-CONFIG_FPGA_MGR_XILINX_SPI=m
-CONFIG_FPGA_MGR_MACHXO2_SPI=m
-CONFIG_FPGA_BRIDGE=m
-CONFIG_ALTERA_FREEZE_BRIDGE=m
-CONFIG_XILINX_PR_DECOUPLER=m
-CONFIG_FPGA_REGION=m
-CONFIG_FPGA_DFL=m
-CONFIG_FPGA_DFL_FME=m
-CONFIG_FPGA_DFL_FME_MGR=m
-CONFIG_FPGA_DFL_FME_BRIDGE=m
-CONFIG_FPGA_DFL_FME_REGION=m
-CONFIG_FPGA_DFL_AFU=m
-CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
-CONFIG_FPGA_DFL_PCI=m
-CONFIG_FPGA_M10_BMC_SEC_UPDATE=m
-CONFIG_FPGA_MGR_MICROCHIP_SPI=m
-CONFIG_TEE=m
-
-#
-# TEE drivers
-#
-CONFIG_AMDTEE=m
-# end of TEE drivers
-
-CONFIG_MULTIPLEXER=m
-
-#
-# Multiplexer drivers
-#
-CONFIG_MUX_ADG792A=m
-CONFIG_MUX_ADGS1408=m
-CONFIG_MUX_GPIO=m
-# end of Multiplexer drivers
-
-CONFIG_PM_OPP=y
-CONFIG_UNISYS_VISORBUS=m
-CONFIG_SIOX=m
-CONFIG_SIOX_BUS_GPIO=m
-CONFIG_SLIMBUS=m
-CONFIG_SLIM_QCOM_CTRL=m
-# CONFIG_INTERCONNECT is not set
-CONFIG_COUNTER=m
-CONFIG_INTERRUPT_CNT=m
-CONFIG_INTEL_QEP=m
-CONFIG_TI_ECAP_CAPTURE=m
-CONFIG_MOST=m
-CONFIG_MOST_USB_HDM=m
-CONFIG_MOST_CDEV=m
-CONFIG_MOST_SND=m
-# end of Device Drivers
-
-#
-# File systems
-#
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_VALIDATE_FS_PARSER=y
-CONFIG_FS_IOMAP=y
-# CONFIG_EXT2_FS is not set
-# CONFIG_EXT3_FS is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_USE_FOR_EXT2=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD2=m
-# CONFIG_JBD2_DEBUG is not set
-CONFIG_FS_MBCACHE=m
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-CONFIG_REISERFS_PROC_INFO=y
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_SECURITY=y
-# CONFIG_JFS_DEBUG is not set
-CONFIG_JFS_STATISTICS=y
-CONFIG_XFS_FS=m
-# CONFIG_XFS_SUPPORT_V4 is not set
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_XFS_ONLINE_SCRUB=y
-# CONFIG_XFS_ONLINE_REPAIR is not set
-# CONFIG_XFS_WARN is not set
-# CONFIG_XFS_DEBUG is not set
-CONFIG_GFS2_FS=m
-CONFIG_GFS2_FS_LOCKING_DLM=y
-CONFIG_OCFS2_FS=m
-CONFIG_OCFS2_FS_O2CB=m
-CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
-CONFIG_OCFS2_FS_STATS=y
-CONFIG_OCFS2_DEBUG_MASKLOG=y
-CONFIG_OCFS2_DEBUG_FS=y
-CONFIG_BTRFS_FS=m
-CONFIG_BTRFS_FS_POSIX_ACL=y
-# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
-# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
-# CONFIG_BTRFS_DEBUG is not set
-# CONFIG_BTRFS_ASSERT is not set
-# CONFIG_BTRFS_FS_REF_VERIFY is not set
-CONFIG_NILFS2_FS=m
-CONFIG_F2FS_FS=m
-CONFIG_F2FS_STAT_FS=y
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_FS_POSIX_ACL=y
-CONFIG_F2FS_FS_SECURITY=y
-# CONFIG_F2FS_CHECK_FS is not set
-# CONFIG_F2FS_FAULT_INJECTION is not set
-CONFIG_F2FS_FS_COMPRESSION=y
-CONFIG_F2FS_FS_LZO=y
-CONFIG_F2FS_FS_LZORLE=y
-CONFIG_F2FS_FS_LZ4=y
-CONFIG_F2FS_FS_LZ4HC=y
-CONFIG_F2FS_FS_ZSTD=y
-# CONFIG_F2FS_IOSTAT is not set
-# CONFIG_F2FS_UNFAIR_RWSEM is not set
-CONFIG_ZONEFS_FS=m
-CONFIG_FS_DAX=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_EXPORTFS=y
-CONFIG_EXPORTFS_BLOCK_OPS=y
-CONFIG_FILE_LOCKING=y
-CONFIG_FS_ENCRYPTION=y
-CONFIG_FS_ENCRYPTION_ALGS=m
-# CONFIG_FS_VERITY is not set
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY_USER=y
-CONFIG_FANOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-# CONFIG_QUOTA_DEBUG is not set
-CONFIG_QUOTA_TREE=m
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=m
-CONFIG_QUOTACTL=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_AUTOFS_FS=y
-CONFIG_FUSE_FS=m
-CONFIG_CUSE=m
-CONFIG_VIRTIO_FS=m
-CONFIG_FUSE_DAX=y
-CONFIG_OVERLAY_FS=m
-CONFIG_OVERLAY_FS_REDIRECT_DIR=y
-CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
-CONFIG_OVERLAY_FS_INDEX=y
-CONFIG_OVERLAY_FS_NFS_EXPORT=y
-CONFIG_OVERLAY_FS_XINO_AUTO=y
-# CONFIG_OVERLAY_FS_METACOPY is not set
-
-#
-# Caches
-#
-CONFIG_NETFS_SUPPORT=m
-CONFIG_NETFS_STATS=y
-CONFIG_FSCACHE=m
-CONFIG_FSCACHE_STATS=y
-# CONFIG_FSCACHE_DEBUG is not set
-CONFIG_CACHEFILES=m
-# CONFIG_CACHEFILES_DEBUG is not set
-# end of Caches
-
-#
-# CD-ROM/DVD Filesystems
-#
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-# end of CD-ROM/DVD Filesystems
-
-#
-# DOS/FAT/EXFAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
-# CONFIG_FAT_DEFAULT_UTF8 is not set
-CONFIG_EXFAT_FS=m
-CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-CONFIG_NTFS_RW=y
-CONFIG_NTFS3_FS=m
-# CONFIG_NTFS3_64BIT_CLUSTER is not set
-CONFIG_NTFS3_LZX_XPRESS=y
-CONFIG_NTFS3_FS_POSIX_ACL=y
-# end of DOS/FAT/EXFAT/NT Filesystems
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_CHILDREN=y
-CONFIG_PROC_PID_ARCH_STATUS=y
-CONFIG_PROC_CPU_RESCTRL=y
-CONFIG_KERNFS=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TMPFS_XATTR=y
-CONFIG_TMPFS_INODE64=y
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_HUGETLB_PAGE_FREE_VMEMMAP=y
-CONFIG_HUGETLB_PAGE_FREE_VMEMMAP_DEFAULT_ON=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_EFIVAR_FS=m
-# end of Pseudo filesystems
-
-CONFIG_MISC_FILESYSTEMS=y
-CONFIG_ORANGEFS_FS=m
-CONFIG_ADFS_FS=m
-# CONFIG_ADFS_FS_RW is not set
-CONFIG_AFFS_FS=m
-CONFIG_ECRYPT_FS=m
-CONFIG_ECRYPT_FS_MESSAGING=y
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-# CONFIG_BEFS_DEBUG is not set
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RTIME=y
-CONFIG_JFFS2_RUBIN=y
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-CONFIG_UBIFS_FS=m
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UBIFS_FS_ZSTD=y
-CONFIG_UBIFS_ATIME_SUPPORT=y
-CONFIG_UBIFS_FS_XATTR=y
-CONFIG_UBIFS_FS_SECURITY=y
-# CONFIG_UBIFS_FS_AUTHENTICATION is not set
-CONFIG_CRAMFS=m
-CONFIG_CRAMFS_BLOCKDEV=y
-CONFIG_CRAMFS_MTD=y
-CONFIG_SQUASHFS=m
-# CONFIG_SQUASHFS_FILE_CACHE is not set
-CONFIG_SQUASHFS_FILE_DIRECT=y
-# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
-CONFIG_SQUASHFS_DECOMP_MULTI=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_XATTR=y
-CONFIG_SQUASHFS_ZLIB=y
-CONFIG_SQUASHFS_LZ4=y
-CONFIG_SQUASHFS_LZO=y
-CONFIG_SQUASHFS_XZ=y
-CONFIG_SQUASHFS_ZSTD=y
-CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
-CONFIG_SQUASHFS_EMBEDDED=y
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_OMFS_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_QNX6FS_FS=m
-# CONFIG_QNX6FS_DEBUG is not set
-CONFIG_ROMFS_FS=m
-# CONFIG_ROMFS_BACKED_BY_BLOCK is not set
-# CONFIG_ROMFS_BACKED_BY_MTD is not set
-CONFIG_ROMFS_BACKED_BY_BOTH=y
-CONFIG_ROMFS_ON_BLOCK=y
-CONFIG_ROMFS_ON_MTD=y
-CONFIG_PSTORE=m
-CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_LZO_COMPRESS=y
-CONFIG_PSTORE_LZ4_COMPRESS=y
-CONFIG_PSTORE_LZ4HC_COMPRESS=y
-CONFIG_PSTORE_842_COMPRESS=y
-CONFIG_PSTORE_ZSTD_COMPRESS=y
-CONFIG_PSTORE_COMPRESS=y
-# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
-CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="zstd"
-# CONFIG_PSTORE_CONSOLE is not set
-CONFIG_PSTORE_PMSG=y
-# CONFIG_PSTORE_FTRACE is not set
-CONFIG_PSTORE_RAM=m
-CONFIG_PSTORE_ZONE=m
-CONFIG_PSTORE_BLK=m
-CONFIG_PSTORE_BLK_BLKDEV=""
-CONFIG_PSTORE_BLK_KMSG_SIZE=64
-CONFIG_PSTORE_BLK_MAX_REASON=2
-CONFIG_PSTORE_BLK_PMSG_SIZE=64
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-# CONFIG_UFS_FS_WRITE is not set
-# CONFIG_UFS_DEBUG is not set
-CONFIG_EROFS_FS=m
-# CONFIG_EROFS_FS_DEBUG is not set
-CONFIG_EROFS_FS_XATTR=y
-CONFIG_EROFS_FS_POSIX_ACL=y
-# CONFIG_EROFS_FS_SECURITY is not set
-# CONFIG_EROFS_FS_ZIP is not set
-CONFIG_VBOXSF_FS=m
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V2=m
-CONFIG_NFS_V3=m
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=m
-CONFIG_NFS_SWAP=y
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_V4_2=y
-CONFIG_PNFS_FILE_LAYOUT=m
-CONFIG_PNFS_BLOCK=m
-CONFIG_PNFS_FLEXFILE_LAYOUT=m
-CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
-CONFIG_NFS_V4_1_MIGRATION=y
-CONFIG_NFS_FSCACHE=y
-# CONFIG_NFS_USE_LEGACY_DNS is not set
-CONFIG_NFS_USE_KERNEL_DNS=y
-CONFIG_NFS_DISABLE_UDP_SUPPORT=y
-CONFIG_NFS_V4_2_READ_PLUS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V2_ACL=y
-CONFIG_NFSD_V3=y
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_PNFS=y
-CONFIG_NFSD_BLOCKLAYOUT=y
-CONFIG_NFSD_SCSILAYOUT=y
-CONFIG_NFSD_FLEXFILELAYOUT=y
-CONFIG_NFSD_V4_2_INTER_SSC=y
-CONFIG_GRACE_PERIOD=m
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_ACL_SUPPORT=m
-CONFIG_NFS_COMMON=y
-CONFIG_NFS_V4_2_SSC_HELPER=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_SUNRPC_BACKCHANNEL=y
-CONFIG_SUNRPC_SWAP=y
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
-# CONFIG_SUNRPC_DEBUG is not set
-CONFIG_SUNRPC_XPRT_RDMA=m
-CONFIG_CEPH_FS=m
-CONFIG_CEPH_FSCACHE=y
-CONFIG_CEPH_FS_POSIX_ACL=y
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS2=y
-CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
-CONFIG_CIFS_UPCALL=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-# CONFIG_CIFS_DEBUG is not set
-CONFIG_CIFS_DFS_UPCALL=y
-CONFIG_CIFS_SWN_UPCALL=y
-# CONFIG_CIFS_SMB_DIRECT is not set
-CONFIG_CIFS_FSCACHE=y
-CONFIG_SMB_SERVER=m
-CONFIG_SMB_SERVER_SMBDIRECT=y
-CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
-CONFIG_SMB_SERVER_KERBEROS5=y
-CONFIG_SMBFS_COMMON=m
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-# CONFIG_AFS_DEBUG is not set
-CONFIG_AFS_FSCACHE=y
-# CONFIG_AFS_DEBUG_CURSOR is not set
-CONFIG_9P_FS=m
-CONFIG_9P_FSCACHE=y
-CONFIG_9P_FS_POSIX_ACL=y
-CONFIG_9P_FS_SECURITY=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_MAC_ROMAN=m
-CONFIG_NLS_MAC_CELTIC=m
-CONFIG_NLS_MAC_CENTEURO=m
-CONFIG_NLS_MAC_CROATIAN=m
-CONFIG_NLS_MAC_CYRILLIC=m
-CONFIG_NLS_MAC_GAELIC=m
-CONFIG_NLS_MAC_GREEK=m
-CONFIG_NLS_MAC_ICELAND=m
-CONFIG_NLS_MAC_INUIT=m
-CONFIG_NLS_MAC_ROMANIAN=m
-CONFIG_NLS_MAC_TURKISH=m
-CONFIG_NLS_UTF8=m
-CONFIG_DLM=m
-# CONFIG_DLM_DEPRECATED_API is not set
-# CONFIG_DLM_DEBUG is not set
-CONFIG_UNICODE=y
-CONFIG_UNICODE_NORMALIZATION_SELFTEST=m
-CONFIG_IO_WQ=y
-# end of File systems
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-# CONFIG_KEYS_REQUEST_CACHE is not set
-CONFIG_PERSISTENT_KEYRINGS=y
+CONFIG_TOOLS_SUPPORT_RELR=y
+CONFIG_TOPSTAR_LAPTOP=m
+CONFIG_TORTURE_TEST=m
+CONFIG_TOSHIBA_BT_RFKILL=m
+CONFIG_TOSHIBA_HAPS=m
+CONFIG_TOSHIBA_WMI=m
+CONFIG_TOUCHSCREEN_88PM860X=m
+CONFIG_TOUCHSCREEN_AD7877=m
+CONFIG_TOUCHSCREEN_AD7879_I2C=m
+CONFIG_TOUCHSCREEN_AD7879=m
+CONFIG_TOUCHSCREEN_AD7879_SPI=m
+CONFIG_TOUCHSCREEN_ADC=m
+CONFIG_TOUCHSCREEN_ADS7846=m
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
+CONFIG_TOUCHSCREEN_BU21013=m
+CONFIG_TOUCHSCREEN_BU21029=m
+CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
+CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
+CONFIG_TOUCHSCREEN_CY8CTMA140=m
+CONFIG_TOUCHSCREEN_CY8CTMG110=m
+CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
+CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
+CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
+CONFIG_TOUCHSCREEN_CYTTSP5=m
+CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
+CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
+CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
+CONFIG_TOUCHSCREEN_DA9034=m
+CONFIG_TOUCHSCREEN_DA9052=m
+CONFIG_TOUCHSCREEN_DMI=y
+CONFIG_TOUCHSCREEN_DYNAPRO=m
+CONFIG_TOUCHSCREEN_EDT_FT5X06=m
+CONFIG_TOUCHSCREEN_EETI=m
+CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
+CONFIG_TOUCHSCREEN_EKTF2127=m
+CONFIG_TOUCHSCREEN_ELAN=m
+CONFIG_TOUCHSCREEN_ELO=m
+CONFIG_TOUCHSCREEN_EXC3000=m
+CONFIG_TOUCHSCREEN_FUJITSU=m
+CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C=m
+CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI=m
+CONFIG_TOUCHSCREEN_GOODIX=m
+CONFIG_TOUCHSCREEN_GUNZE=m
+CONFIG_TOUCHSCREEN_HAMPSHIRE=m
+CONFIG_TOUCHSCREEN_HIDEEP=m
+CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m
+CONFIG_TOUCHSCREEN_HIMAX_HX852X=m
+CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
+CONFIG_TOUCHSCREEN_HYNITRON_CST816X=m
+CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=m
+CONFIG_TOUCHSCREEN_ILI210X=m
+CONFIG_TOUCHSCREEN_ILITEK=m
+CONFIG_TOUCHSCREEN_IMAGIS=m
+CONFIG_TOUCHSCREEN_INEXIO=m
+CONFIG_TOUCHSCREEN_IQS5XX=m
+CONFIG_TOUCHSCREEN_IQS7211=m
+CONFIG_TOUCHSCREEN_MAX11801=m
+CONFIG_TOUCHSCREEN_MC13783=m
+CONFIG_TOUCHSCREEN_MCS5000=m
+CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
+CONFIG_TOUCHSCREEN_MMS114=m
+CONFIG_TOUCHSCREEN_MSG2638=m
+CONFIG_TOUCHSCREEN_MTOUCH=m
+CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS=m
+CONFIG_TOUCHSCREEN_PCAP=m
+CONFIG_TOUCHSCREEN_PENMOUNT=m
+CONFIG_TOUCHSCREEN_PIXCIR=m
+CONFIG_TOUCHSCREEN_RM_TS=m
+CONFIG_TOUCHSCREEN_ROHM_BU21023=m
+CONFIG_TOUCHSCREEN_S6SY761=m
+CONFIG_TOUCHSCREEN_SILEAD=m
+CONFIG_TOUCHSCREEN_SIS_I2C=m
+CONFIG_TOUCHSCREEN_ST1232=m
+CONFIG_TOUCHSCREEN_STMFTS=m
+CONFIG_TOUCHSCREEN_SUR40=m
+CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
+CONFIG_TOUCHSCREEN_SX8654=m
+CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m
+CONFIG_TOUCHSCREEN_TOUCHIT213=m
+CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
+CONFIG_TOUCHSCREEN_TOUCHWIN=m
+CONFIG_TOUCHSCREEN_TPS6507X=m
+CONFIG_TOUCHSCREEN_TSC2004=m
+CONFIG_TOUCHSCREEN_TSC2005=m
+CONFIG_TOUCHSCREEN_TSC2007_IIO=y
+CONFIG_TOUCHSCREEN_TSC2007=m
+CONFIG_TOUCHSCREEN_TSC200X_CORE=m
+CONFIG_TOUCHSCREEN_TSC_SERIO=m
+CONFIG_TOUCHSCREEN_USB_3M=y
+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
+CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
+CONFIG_TOUCHSCREEN_USB_E2I=y
+CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
+CONFIG_TOUCHSCREEN_USB_EGALAX=y
+CONFIG_TOUCHSCREEN_USB_ELO=y
+CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
+CONFIG_TOUCHSCREEN_USB_ETURBO=y
+CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
+CONFIG_TOUCHSCREEN_USB_GOTOP=y
+CONFIG_TOUCHSCREEN_USB_GUNZE=y
+CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
+CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
+CONFIG_TOUCHSCREEN_USB_ITM=y
+CONFIG_TOUCHSCREEN_USB_JASTEC=y
+CONFIG_TOUCHSCREEN_USB_NEXIO=y
+CONFIG_TOUCHSCREEN_USB_PANJIT=y
+CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
+CONFIG_TOUCHSCREEN_WACOM_I2C=m
+CONFIG_TOUCHSCREEN_WACOM_W8001=m
+CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
+CONFIG_TOUCHSCREEN_WM831X=m
+CONFIG_TOUCHSCREEN_WM9705=y
+CONFIG_TOUCHSCREEN_WM9712=y
+CONFIG_TOUCHSCREEN_WM9713=y
+CONFIG_TOUCHSCREEN_WM97XX=m
+CONFIG_TOUCHSCREEN_ZET6223=m
+CONFIG_TOUCHSCREEN_ZFORCE=m
+CONFIG_TOUCHSCREEN_ZINITIX=m
+CONFIG_TPL0102=m
+CONFIG_TPS6105X=m
+CONFIG_TPS65010=m
+CONFIG_TPS6507X=m
+CONFIG_TPS6594_ESM=m
+CONFIG_TPS6594_PFSM=m
+CONFIG_TPS68470_PMIC_OPREGION=y
+CONFIG_TP_SMAPI=m
+CONFIG_TQMX86_WDT=m
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_TRUSTED_KEYS=m
-CONFIG_ENCRYPTED_KEYS=m
-CONFIG_USER_DECRYPTED_DATA=y
-CONFIG_KEY_DH_OPERATIONS=y
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-# CONFIG_SECURITY is not set
-CONFIG_SECURITYFS=y
-CONFIG_PAGE_TABLE_ISOLATION=y
-CONFIG_INTEL_TXT=y
-CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
-CONFIG_HARDENED_USERCOPY=y
-# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
-CONFIG_FORTIFY_SOURCE=y
-# CONFIG_STATIC_USERMODEHELPER is not set
-# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_LSM="yama,loadpin,safesetid,integrity,bpf"
-
-#
-# Kernel hardening options
-#
-
-#
-# Memory initialization
-#
-CONFIG_INIT_STACK_NONE=y
-# CONFIG_INIT_STACK_ALL_PATTERN is not set
-# CONFIG_INIT_STACK_ALL_ZERO is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
-# CONFIG_GCC_PLUGIN_STACKLEAK is not set
-# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
-# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
-CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
-CONFIG_CC_USING_FENTRY=y
-# CONFIG_ZERO_CALL_USED_REGS is not set
-# end of Memory initialization
-# end of Kernel hardening options
-# end of Security options
-
-CONFIG_XOR_BLOCKS=m
-CONFIG_ASYNC_CORE=m
-CONFIG_ASYNC_MEMCPY=m
-CONFIG_ASYNC_XOR=m
-CONFIG_ASYNC_PQ=m
-CONFIG_ASYNC_RAID6_RECOV=m
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=m
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_SKCIPHER=y
-CONFIG_CRYPTO_SKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG=m
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=m
-CONFIG_CRYPTO_AKCIPHER2=y
-CONFIG_CRYPTO_AKCIPHER=y
-CONFIG_CRYPTO_KPP2=y
-CONFIG_CRYPTO_KPP=m
-CONFIG_CRYPTO_ACOMP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_USER=m
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_PCRYPT=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_SIMD=m
-CONFIG_CRYPTO_ENGINE=m
-
-#
-# Public-key cryptography
-#
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_DH=m
-CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
-CONFIG_CRYPTO_ECC=m
-CONFIG_CRYPTO_ECDH=m
-CONFIG_CRYPTO_ECDSA=m
-CONFIG_CRYPTO_ECRDSA=m
-CONFIG_CRYPTO_SM2=m
-CONFIG_CRYPTO_CURVE25519=m
-CONFIG_CRYPTO_CURVE25519_X86=m
-
-#
-# Authenticated Encryption with Associated Data
-#
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_GCM=m
-CONFIG_CRYPTO_CHACHA20POLY1305=m
-CONFIG_CRYPTO_AEGIS128=m
-CONFIG_CRYPTO_AEGIS128_AESNI_SSE2=m
-CONFIG_CRYPTO_SEQIV=m
-CONFIG_CRYPTO_ECHAINIV=m
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CFB=m
-CONFIG_CRYPTO_CTR=m
-CONFIG_CRYPTO_CTS=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_OFB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_KEYWRAP=m
-CONFIG_CRYPTO_NHPOLY1305=m
-CONFIG_CRYPTO_NHPOLY1305_SSE2=m
-CONFIG_CRYPTO_NHPOLY1305_AVX2=m
-CONFIG_CRYPTO_ADIANTUM=m
-CONFIG_CRYPTO_HCTR2=m
-CONFIG_CRYPTO_ARIA=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
-CONFIG_CRYPTO_DEV_QAT_C3XXX=m
-CONFIG_CRYPTO_DEV_QAT_C62X=m
-CONFIG_CRYPTO_DEV_QAT_4XXX=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
-CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
-CONFIG_CRYPTO_DEV_QAT_C62XVF=m
-CONFIG_CRYPTO_ESSIV=m
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_CMAC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CRC32C_INTEL=m
-CONFIG_CRYPTO_CRC32=m
-CONFIG_CRYPTO_CRC32_PCLMUL=m
-CONFIG_CRYPTO_XXHASH=m
-CONFIG_CRYPTO_BLAKE2B=m
-CONFIG_CRYPTO_BLAKE2S=m
-CONFIG_CRYPTO_BLAKE2S_X86=m
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_CRCT10DIF_PCLMUL=m
-CONFIG_CRYPTO_GHASH=m
-CONFIG_CRYPTO_POLYVAL_CLMUL_NI=m
-CONFIG_CRYPTO_POLY1305=m
-CONFIG_CRYPTO_POLY1305_X86_64=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_SSSE3=m
-CONFIG_CRYPTO_SHA256_SSSE3=m
-CONFIG_CRYPTO_SHA512_SSSE3=m
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SHA3=m
-CONFIG_CRYPTO_SM3=m
-CONFIG_CRYPTO_SM3_AVX_X86_64=m
-CONFIG_CRYPTO_STREEBOG=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_AES_TI=m
-CONFIG_CRYPTO_AES_NI_INTEL=m
-CONFIG_CRYPTO_ANUBIS=m
-# CONFIG_CRYPTO_ARC4 is not set
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_BLOWFISH_COMMON=m
-CONFIG_CRYPTO_BLOWFISH_X86_64=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAMELLIA_X86_64=m
-CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64=m
-CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=m
-CONFIG_CRYPTO_CAST_COMMON=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST5_AVX_X86_64=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_CAST6_AVX_X86_64=m
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DES3_EDE_X86_64=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_CHACHA20=m
-CONFIG_CRYPTO_CHACHA20_X86_64=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_SERPENT_SSE2_X86_64=m
-CONFIG_CRYPTO_SERPENT_AVX_X86_64=m
-CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m
-CONFIG_CRYPTO_SM4=m
-CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64=m
-CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-CONFIG_CRYPTO_TWOFISH_X86_64=m
-CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=m
-CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m
-CONFIG_CRYPTO_ARIA_AESNI_AVX_X86_64=m
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_842=y
-CONFIG_CRYPTO_LZ4=y
-CONFIG_CRYPTO_LZ4HC=y
-CONFIG_CRYPTO_ZSTD=y
-
-#
-# Random Number Generation
-#
-CONFIG_CRYPTO_ANSI_CPRNG=m
-CONFIG_CRYPTO_DRBG_MENU=m
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_HASH=y
-CONFIG_CRYPTO_DRBG_CTR=y
-CONFIG_CRYPTO_DRBG=m
-CONFIG_CRYPTO_JITTERENTROPY=m
-CONFIG_CRYPTO_USER_API=m
-CONFIG_CRYPTO_USER_API_HASH=y
-CONFIG_CRYPTO_USER_API_SKCIPHER=m
-CONFIG_CRYPTO_USER_API_RNG=m
-# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
-CONFIG_CRYPTO_USER_API_AEAD=m
-CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
-# CONFIG_CRYPTO_STATS is not set
-CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=m
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_SM4=m
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_DEV_PADLOCK=m
-CONFIG_CRYPTO_DEV_PADLOCK_AES=m
-CONFIG_CRYPTO_DEV_PADLOCK_SHA=m
-CONFIG_CRYPTO_DEV_ATMEL_I2C=m
-CONFIG_CRYPTO_DEV_ATMEL_ECC=m
-CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
-CONFIG_CRYPTO_DEV_CCP=y
-CONFIG_CRYPTO_DEV_CCP_DD=m
-CONFIG_CRYPTO_DEV_SP_CCP=y
-CONFIG_CRYPTO_DEV_CCP_CRYPTO=m
-CONFIG_CRYPTO_DEV_SP_PSP=y
-# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set
-CONFIG_CRYPTO_DEV_QAT=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
-CONFIG_CRYPTO_DEV_QAT_C3XXX=m
-CONFIG_CRYPTO_DEV_QAT_C62X=m
-CONFIG_CRYPTO_DEV_QAT_4XXX=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
-CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
-CONFIG_CRYPTO_DEV_QAT_C62XVF=m
-CONFIG_CRYPTO_DEV_NITROX=m
-CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m
-CONFIG_CRYPTO_DEV_CHELSIO=m
-CONFIG_CRYPTO_DEV_VIRTIO=m
-CONFIG_CRYPTO_DEV_SAFEXCEL=m
-CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
-CONFIG_CRYPTO_DEV_ASPEED=m
-# CONFIG_CRYPTO_DEV_ASPEED_DEBUG is not set
-CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH=y
-CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO=y
-# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set
-CONFIG_ASYMMETRIC_KEY_TYPE=y
-CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
-CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE=m
-CONFIG_X509_CERTIFICATE_PARSER=y
-CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
-CONFIG_TPM_KEY_PARSER=m
-CONFIG_PKCS7_MESSAGE_PARSER=y
-CONFIG_PKCS7_TEST_KEY=m
-CONFIG_SIGNED_PE_FILE_VERIFICATION=y
-
-#
-# Certificates for signature checking
-#
-CONFIG_MODULE_SIG_KEY="certs/signing_key.pem"
-CONFIG_MODULE_SIG_KEY_TYPE_RSA=y
-# CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set
-CONFIG_SYSTEM_TRUSTED_KEYRING=y
-CONFIG_SYSTEM_TRUSTED_KEYS=""
-# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
-CONFIG_SECONDARY_TRUSTED_KEYRING=y
-CONFIG_SYSTEM_BLACKLIST_KEYRING=y
-CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
-# CONFIG_SYSTEM_REVOCATION_LIST is not set
-# end of Certificates for signature checking
-
-CONFIG_BINARY_PRINTF=y
-
-#
-# Library routines
-#
-CONFIG_RAID6_PQ=m
-CONFIG_RAID6_PQ_BENCHMARK=y
-CONFIG_LINEAR_RANGES=y
-CONFIG_PACKING=y
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_CORDIC=m
-CONFIG_PRIME_NUMBERS=m
-CONFIG_RATIONAL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
-CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC64_ROCKSOFT=m
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC32_SELFTEST is not set
-CONFIG_CRC32_SLICEBY8=y
-# CONFIG_CRC32_SLICEBY4 is not set
-# CONFIG_CRC32_SARWATE is not set
-# CONFIG_CRC32_BIT is not set
-CONFIG_CRC64=m
-CONFIG_CRC4=m
-CONFIG_CRC7=m
-CONFIG_LIBCRC32C=m
-CONFIG_CRC8=m
-CONFIG_XXHASH=y
-# CONFIG_RANDOM32_SELFTEST is not set
-CONFIG_842_COMPRESS=y
-CONFIG_842_DECOMPRESS=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_LZ4_COMPRESS=y
-CONFIG_LZ4HC_COMPRESS=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
-CONFIG_XZ_DEC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_XZ_DEC_POWERPC=y
+CONFIG_TRUSTED_KEYS_TEE=y
+CONFIG_TRUSTED_KEYS_TPM=y
+CONFIG_TSL2583=m
+CONFIG_TSL2591=m
+CONFIG_TSL2772=m
+CONFIG_TSL4531=m
+CONFIG_TSYS01=m
+CONFIG_TSYS02D=m
+CONFIG_TTPCI_EEPROM=m
+CONFIG_TUN=m
+CONFIG_TUXEDO_NB04_WMI_AB=m
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_MADC=m
+CONFIG_TWL4030_WATCHDOG=m
+CONFIG_TWL6030_GPADC=m
+CONFIG_TWL6040_CORE=y
+CONFIG_TYPEC_ANX7411=m
+CONFIG_TYPEC_DP_ALTMODE=m
+CONFIG_TYPEC_FUSB302=m
+CONFIG_TYPEC_HD3SS3220=m
+CONFIG_TYPEC=m
+CONFIG_TYPEC_MT6360=m
+CONFIG_TYPEC_MUX_FSA4480=m
+CONFIG_TYPEC_MUX_GPIO_SBU=m
+CONFIG_TYPEC_MUX_INTEL_PMC=m
+CONFIG_TYPEC_MUX_IT5205=m
+CONFIG_TYPEC_MUX_NB7VPQ904M=m
+CONFIG_TYPEC_MUX_PI3USB30532=m
+CONFIG_TYPEC_MUX_PS883X=m
+CONFIG_TYPEC_MUX_PTN36502=m
+CONFIG_TYPEC_MUX_WCD939X_USBSS=m
+CONFIG_TYPEC_NVIDIA_ALTMODE=m
+CONFIG_TYPEC_RT1711H=m
+CONFIG_TYPEC_RT1719=m
+CONFIG_TYPEC_STUSB160X=m
+CONFIG_TYPEC_TBT_ALTMODE=m
+CONFIG_TYPEC_TCPCI=m
+CONFIG_TYPEC_TCPCI_MAXIM=m
+CONFIG_TYPEC_TCPCI_MT6370=m
+CONFIG_TYPEC_TCPM=m
+CONFIG_TYPEC_TPS6598X=m
+CONFIG_TYPEC_UCSI=m
+CONFIG_TYPEC_WUSB3801=m
+CONFIG_UACCE=m
+CONFIG_UCS2_STRING=y
+CONFIG_UCSI_ACPI=m
+CONFIG_UCSI_CCG=m
+CONFIG_UCSI_STM32G0=m
+CONFIG_UEFI_CPER_X86=y
+CONFIG_UEFI_CPER=y
+CONFIG_UID16=y
+CONFIG_UIO_AEC=m
+CONFIG_UIO_CIF=m
+CONFIG_UIO_DFL=m
+CONFIG_UIO_DMEM_GENIRQ=m
+CONFIG_UIO_HV_GENERIC=m
+CONFIG_UIO_MF624=m
+CONFIG_UIO_NETX=m
+CONFIG_UIO_PCI_GENERIC=m
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_UIO_PRUSS=m
+CONFIG_UIO_SERCOS3=m
+CONFIG_ULTRIX_PARTITION=y
+CONFIG_UNACCEPTED_MEMORY=y
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_UNWINDER_ORC=y
+CONFIG_US5182D=m
+CONFIG_USB4=m
+CONFIG_USB4_NET=m
+CONFIG_USB_ACM=m
+CONFIG_USB_ADUTUX=m
+CONFIG_USB_AIRSPY=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AMD5536UDC=m
+CONFIG_USB_AN2720=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_APPLEDISPLAY=m
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_ATM=m
+CONFIG_USB_AUDIO=m
+CONFIG_USB_BDC_UDC=m
+CONFIG_USB_BELKIN=y
+CONFIG_USB_C67X00_HCD=m
+CONFIG_USB_CATC=m
+CONFIG_USB_CDC_COMPOSITE=m
+CONFIG_USB_CDC_PHONET=m
+CONFIG_USB_CDNS2_UDC=m
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_USB_CDNS3=m
+CONFIG_USB_CDNS3_PCI_WRAP=m
+CONFIG_USB_CDNS_HOST=y
+CONFIG_USB_CDNSP_GADGET=y
+CONFIG_USB_CDNSP_HOST=y
+CONFIG_USB_CDNSP_PCI=m
+CONFIG_USB_CDNS_SUPPORT=m
+CONFIG_USB_CHAOSKEY=m
+CONFIG_USB_CHIPIDEA_GENERIC=m
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA=m
+CONFIG_USB_CHIPIDEA_MSM=m
+CONFIG_USB_CHIPIDEA_NPCM=m
+CONFIG_USB_CHIPIDEA_PCI=m
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=m
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_MIDI2=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_USB_CONFIGFS_F_PRINTER=y
+CONFIG_USB_CONFIGFS_F_TCM=y
+CONFIG_USB_CONFIGFS_F_UAC1=y
+CONFIG_USB_CONFIGFS_F_UAC2=y
+CONFIG_USB_CONFIGFS_F_UVC=y
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_PHONET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONN_GPIO=m
+CONFIG_USB_CXACRU=m
+CONFIG_USB_CYPRESS_CY7C63=m
+CONFIG_USB_CYTHERM=m
+CONFIG_USB_DSBR=m
+CONFIG_USB_DWC2_DUAL_ROLE=y
+CONFIG_USB_DWC2=m
+CONFIG_USB_DWC2_PCI=m
+CONFIG_USB_DWC3_DUAL_ROLE=y
+CONFIG_USB_DWC3_HAPS=m
+CONFIG_USB_DWC3=m
+CONFIG_USB_DWC3_PCI=m
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_EG20T=m
+CONFIG_USB_EHCI_FSL=m
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_EHCI_HCD_PLATFORM=m
+CONFIG_USB_EHCI_PCI=m
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHSET_TEST_FIXTURE=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_EMI62=m
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_ETH_EEM=y
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_EZUSB_FX2=m
+CONFIG_USB_F_ACM=m
+CONFIG_USB_F_ECM=m
+CONFIG_USB_F_EEM=m
+CONFIG_USB_FEW_INIT_RETRIES=y
+CONFIG_USB_F_FS=m
+CONFIG_USB_F_HID=m
+CONFIG_USB_F_MASS_STORAGE=m
+CONFIG_USB_F_MIDI=m
+CONFIG_USB_F_NCM=m
+CONFIG_USB_F_OBEX=m
+CONFIG_USB_F_PHONET=m
+CONFIG_USB_F_PRINTER=m
+CONFIG_USB_F_RNDIS=m
+CONFIG_USB_F_SERIAL=m
+CONFIG_USB_F_SS_LB=m
+CONFIG_USB_F_SUBSET=m
+CONFIG_USB_F_TCM=m
+CONFIG_USB_F_UAC1=m
+CONFIG_USB_F_UAC2=m
+CONFIG_USB_FUNCTIONFS_ETH=y
+CONFIG_USB_FUNCTIONFS_GENERIC=y
+CONFIG_USB_FUNCTIONFS=m
+CONFIG_USB_FUNCTIONFS_RNDIS=y
+CONFIG_USB_F_UVC=m
+CONFIG_USB_G_ACM_MS=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_GADGET=m
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+CONFIG_USB_GADGET_TARGET=m
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_G_HID=m
+CONFIG_USB_GL860=m
+CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_RNDIS=y
+CONFIG_USB_G_NCM=m
+CONFIG_USB_G_NOKIA=m
+CONFIG_USB_GOKU=m
+CONFIG_USB_GPIO_VBUS=m
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_GR_UDC=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_GSPCA_BENQ=m
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_CPIA1=m
+CONFIG_USB_GSPCA_DTCS033=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
+CONFIG_USB_GSPCA_JEILINJ=m
+CONFIG_USB_GSPCA_JL2005BCD=m
+CONFIG_USB_GSPCA_KINECT=m
+CONFIG_USB_GSPCA_KONICA=m
+CONFIG_USB_GSPCA=m
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_MR97310A=m
+CONFIG_USB_GSPCA_NW80X=m
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534_9=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_PAC207=m
+CONFIG_USB_GSPCA_PAC7302=m
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SE401=m
+CONFIG_USB_GSPCA_SN9C2028=m
+CONFIG_USB_GSPCA_SN9C20X=m
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA1528=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+CONFIG_USB_GSPCA_SQ905C=m
+CONFIG_USB_GSPCA_SQ905=m
+CONFIG_USB_GSPCA_SQ930X=m
+CONFIG_USB_GSPCA_STK014=m
+CONFIG_USB_GSPCA_STK1135=m
+CONFIG_USB_GSPCA_STV0680=m
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TOPRO=m
+CONFIG_USB_GSPCA_TOUPTEK=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+CONFIG_USB_GSPCA_VICAM=m
+CONFIG_USB_GSPCA_XIRLINK_CIT=m
+CONFIG_USB_GSPCA_ZC3XX=m
+CONFIG_USB_G_WEBCAM=m
+CONFIG_USB_HACKRF=m
+CONFIG_USB_HCD_BCMA=m
+CONFIG_USB_HCD_SSB=m
+CONFIG_USB_HSIC_USB3503=m
+CONFIG_USB_HSIC_USB4604=m
+CONFIG_USB_HSO=m
+CONFIG_USB_HUB_USB251XB=m
+CONFIG_USB_IDMOUSE=m
+CONFIG_USB_IOWARRIOR=m
+CONFIG_USBIP_CORE=m
+CONFIG_USB_IPHETH=m
+CONFIG_USBIP_HOST=m
+CONFIG_USBIP_VHCI_HCD=m
+CONFIG_USBIP_VHCI_HC_PORTS=8
+CONFIG_USBIP_VHCI_NR_HCS=1
+CONFIG_USBIP_VUDC=m
+CONFIG_USB_ISIGHTFW=m
+CONFIG_USB_ISP116X_HCD=m
+CONFIG_USB_ISP1301=m
+CONFIG_USB_ISP1760_DUAL_ROLE=y
+CONFIG_USB_ISP1760_HCD=y
+CONFIG_USB_ISP1760=m
+CONFIG_USB_ISP1761_UDC=y
+CONFIG_USB_KAWETH=m
+CONFIG_USB_KC2190=y
+CONFIG_USB_KEENE=m
+CONFIG_USB_LAN78XX=m
+CONFIG_USB_LCD=m
+CONFIG_USB_LD=m
+CONFIG_USB_LEDS_TRIGGER_USBPORT=m
+CONFIG_USB_LED_TRIG=y
+CONFIG_USB_LEGOTOWER=m
+CONFIG_USB_LGM_PHY=m
+CONFIG_USB_LIBCOMPOSITE=m
+CONFIG_USB_LINK_LAYER_TEST=m
+CONFIG_USB_LJCA=m
+CONFIG_USB=m
+CONFIG_USB_M5602=m
+CONFIG_USB_M66592=m
+CONFIG_USB_MA901=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_MAX3420_UDC=m
+CONFIG_USB_MAX3421_HCD=m
+CONFIG_USB_MDC800=m
+CONFIG_USB_MICROTEK=m
+CONFIG_USB_MIDI_GADGET=m
+CONFIG_USB_MON=m
+CONFIG_USB_MR800=m
+CONFIG_USB_MSI2500=m
+CONFIG_USB_MUSB_DUAL_ROLE=y
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MV_U3D=m
+CONFIG_USB_MV_UDC=m
+CONFIG_USB_NET2272_DMA=y
+CONFIG_USB_NET2272=m
+CONFIG_USB_NET2280=m
+CONFIG_USB_NET_AQC111=m
+CONFIG_USB_NET_AX88179_178A=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDC_EEM=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_MBIM=m
+CONFIG_USB_NET_CDC_NCM=m
+CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_NET_CH9200=m
+CONFIG_USB_NET_CX82310_ETH=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_DRIVERS=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
+CONFIG_USB_NET_INT51X1=m
+CONFIG_USB_NET_KALMIA=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_QMI_WWAN=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_SR9700=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_ZAURUS=m
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_OHCI_HCD_PCI=m
+CONFIG_USB_OHCI_HCD_PLATFORM=m
+CONFIG_USB_OHCI_HCD_SSB=y
+CONFIG_USB_OTG_FSM=m
+CONFIG_USB_OTG=y
+CONFIG_USB_OXU210HP_HCD=m
+CONFIG_USB_PCI_AMD=y
+CONFIG_USBPCWATCHDOG=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_PHY=y
+CONFIG_USB_PRINTER=m
+CONFIG_USB_PULSE8_CEC=m
+CONFIG_USB_PWC_INPUT_EVDEV=y
+CONFIG_USB_PWC=m
+CONFIG_USB_PXA27X=m
+CONFIG_USB_R8A66597_HCD=m
+CONFIG_USB_R8A66597=m
+CONFIG_USB_RAINSHADOW_CEC=m
+CONFIG_USB_RAREMONO=m
+CONFIG_USB_RAW_GADGET=m
+CONFIG_USB_ROLES_INTEL_XHCI=m
+CONFIG_USB_ROLE_SWITCH=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=m
+CONFIG_USB_RTL8153_ECM=m
+CONFIG_USB_S2255=m
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_CP210X=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_F81232=m
+CONFIG_USB_SERIAL_F8153X=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_METRO=m
+CONFIG_USB_SERIAL_MOS7715_PARPORT=y
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MXUPORT=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OTI6858=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QT2=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SAFE=m
+CONFIG_USB_SERIAL_SAFE_PADDED=y
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_SIMPLE=m
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_SSU100=m
+CONFIG_USB_SERIAL_SYMBOL=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_WISHBONE=m
+CONFIG_USB_SERIAL_WWAN=m
+CONFIG_USB_SERIAL_XR=m
+CONFIG_USB_SERIAL_XSENS_MT=m
+CONFIG_USB_SEVSEG=m
+CONFIG_USB_SI470X=m
+CONFIG_USB_SI4713=m
+CONFIG_USB_SIERRA_NET=m
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_SL811_CS=m
+CONFIG_USB_SL811_HCD=m
+CONFIG_USB_SNP_CORE=m
+CONFIG_USB_SPEEDTOUCH=m
+CONFIG_USB_STORAGE_ALAUDA=m
+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_ENE_UB6250=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_KARMA=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_STORAGE_ONETOUCH=m
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STV06XX=m
+CONFIG_USB_TEST=m
+CONFIG_USB_TMC=m
+CONFIG_USB_TRANCEVIBRATOR=m
+CONFIG_USB_UAS=m
+CONFIG_USB_U_AUDIO=m
+CONFIG_USB_UEAGLEATM=m
+CONFIG_USB_U_ETHER=m
+CONFIG_USB_UHCI_HCD=m
+CONFIG_USB_ULPI_BUS=m
+CONFIG_USB_USBIO=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_U_SERIAL=m
+CONFIG_USB_USS720=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VL600=m
+CONFIG_USB_WDM=m
+CONFIG_USB_XHCI_DBGCAP=y
+CONFIG_USB_XHCI_HCD=m
+CONFIG_USB_XHCI_PCI=m
+CONFIG_USB_XHCI_PCI_RENESAS=m
+CONFIG_USB_XHCI_PLATFORM=m
+CONFIG_USB_XUSBATM=m
+CONFIG_USB_YUREX=m
+CONFIG_USB_ZD1201=m
+CONFIG_USB_ZERO_HNPTEST=y
+CONFIG_USB_ZERO=m
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+CONFIG_USER_DECRYPTED_DATA=y
+CONFIG_USERFAULTFD=y
+CONFIG_U_SERIAL_CONSOLE=y
+CONFIG_USERIO=m
+CONFIG_USER_RETURN_NOTIFIER=y
+CONFIG_USER_STACKTRACE_SUPPORT=y
+CONFIG_UVC_COMMON=m
+CONFIG_V4L2_ASYNC=m
+CONFIG_V4L2_FLASH_LED_CLASS=m
+CONFIG_V4L2_FWNODE=m
+CONFIG_V4L2_LOOPBACK=m
+CONFIG_V4L2_MEM2MEM_DEV=m
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VBOXGUEST=m
+CONFIG_VCNL3020=m
+CONFIG_VCNL4000=m
+CONFIG_VCNL4035=m
+CONFIG_VDPA=m
+CONFIG_VDPA_USER=m
+CONFIG_VEML6030=m
+CONFIG_VEML6040=m
+CONFIG_VEML6046X00=m
+CONFIG_VEML6070=m
+CONFIG_VEML6075=m
+CONFIG_VETH=m
+CONFIG_VF610_ADC=m
+CONFIG_VF610_DAC=m
+CONFIG_VFIO_CONTAINER=y
+CONFIG_VFIO_DEVICE_CDEV=y
+CONFIG_VFIO_GROUP=y
+CONFIG_VFIO_IOMMU_TYPE1=m
+CONFIG_VFIO=m
+CONFIG_VFIO_MDEV=m
+CONFIG_VFIO_PCI_CORE=m
+CONFIG_VFIO_PCI_IGD=y
+CONFIG_VFIO_PCI_INTX=y
+CONFIG_VFIO_PCI=m
+CONFIG_VFIO_PCI_MMAP=y
+CONFIG_VFIO_PCI_VGA=y
+CONFIG_VFIO_VIRQFD=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VGA_CONSOLE=y
+CONFIG_VGA_SWITCHEROO=y
+CONFIG_VHOST_IOTLB=m
+CONFIG_VHOST=m
+CONFIG_VHOST_RING=m
+CONFIG_VHOST_SCSI=m
+CONFIG_VHOST_TASK=y
+CONFIG_VHOST_VDPA=m
+CONFIG_VIA_WDT=m
+CONFIG_VIDEO_AD5820=m
+CONFIG_VIDEO_ADP1653=m
+CONFIG_VIDEO_ADV7170=m
+CONFIG_VIDEO_ADV7175=m
+CONFIG_VIDEO_AK7375=m
+CONFIG_VIDEO_ALVIUM_CSI2=m
+CONFIG_VIDEO_APTINA_PLL=m
+CONFIG_VIDEO_AR0521=m
+CONFIG_VIDEO_ATOMISP_GC0310=m
+CONFIG_VIDEO_ATOMISP_GC2235=m
+CONFIG_VIDEO_ATOMISP_ISP2401=y
+CONFIG_VIDEO_ATOMISP_LM3554=m
+CONFIG_VIDEO_ATOMISP=m
+CONFIG_VIDEO_ATOMISP_MSRLIST_HELPER=m
+CONFIG_VIDEO_ATOMISP_MT9M114=m
+CONFIG_VIDEO_ATOMISP_OV2680=m
+CONFIG_VIDEO_ATOMISP_OV2722=m
+CONFIG_VIDEO_ATOMISP_OV5693=m
+CONFIG_VIDEO_AU0828=m
+CONFIG_VIDEO_AU0828_RC=y
+CONFIG_VIDEO_AU0828_V4L2=y
+CONFIG_VIDEO_BT819=m
+CONFIG_VIDEO_BT848=m
+CONFIG_VIDEO_BT856=m
+CONFIG_VIDEO_BT866=m
+CONFIG_VIDEOBUF2_CORE=m
+CONFIG_VIDEOBUF2_DMA_CONTIG=m
+CONFIG_VIDEOBUF2_DMA_SG=m
+CONFIG_VIDEOBUF2_DVB=m
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_V4L2=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEOBUF_DMA_SG=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEO_CADENCE_CSI2RX=m
+CONFIG_VIDEO_CADENCE_CSI2TX=m
+CONFIG_VIDEO_CAFE_CCIC=m
+CONFIG_VIDEO_CAMERA_SENSOR=y
+CONFIG_VIDEO_CCS=m
+CONFIG_VIDEO_CCS_PLL=m
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEO_CS3308=m
+CONFIG_VIDEO_CS5345=m
+CONFIG_VIDEO_CS53L32A=m
+CONFIG_VIDEO_CX18_ALSA=m
+CONFIG_VIDEO_CX18=m
+CONFIG_VIDEO_CX231XX_ALSA=m
+CONFIG_VIDEO_CX231XX_DVB=m
+CONFIG_VIDEO_CX231XX=m
+CONFIG_VIDEO_CX231XX_RC=y
+CONFIG_VIDEO_CX2341X=m
+CONFIG_VIDEO_CX23885=m
+CONFIG_VIDEO_CX25821_ALSA=m
+CONFIG_VIDEO_CX25821=m
+CONFIG_VIDEO_CX25840=m
+CONFIG_VIDEO_CX88_ALSA=m
+CONFIG_VIDEO_CX88_BLACKBIRD=m
+CONFIG_VIDEO_CX88_DVB=m
+CONFIG_VIDEO_CX88_ENABLE_VP3054=y
+CONFIG_VIDEO_CX88=m
+CONFIG_VIDEO_CX88_MPEG=m
+CONFIG_VIDEO_CX88_VP3054=m
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_DS90UB913=m
+CONFIG_VIDEO_DS90UB953=m
+CONFIG_VIDEO_DS90UB960=m
+CONFIG_VIDEO_DT3155=m
+CONFIG_VIDEO_DW9714=m
+CONFIG_VIDEO_DW9719=m
+CONFIG_VIDEO_DW9768=m
+CONFIG_VIDEO_DW9807_VCM=m
+CONFIG_VIDEO_E5010_JPEG_ENC=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_RC=m
+CONFIG_VIDEO_EM28XX_V4L2=m
+CONFIG_VIDEO_ET8EK8=m
+CONFIG_VIDEO_FB_IVTV=m
+CONFIG_VIDEO_GC0308=m
+CONFIG_VIDEO_GC0310=m
+CONFIG_VIDEO_GC05A2=m
+CONFIG_VIDEO_GC08A3=m
+CONFIG_VIDEO_GC2145=m
+CONFIG_VIDEO_GO7007_LOADER=m
+CONFIG_VIDEO_GO7007=m
+CONFIG_VIDEO_GO7007_USB=m
+CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
+CONFIG_VIDEO_HDPVR=m
+CONFIG_VIDEO_HEXIUM_GEMINI=m
+CONFIG_VIDEO_HEXIUM_ORION=m
+CONFIG_VIDEO_HI556=m
+CONFIG_VIDEO_HI846=m
+CONFIG_VIDEO_HI847=m
+CONFIG_VIDEO_IMX208=m
+CONFIG_VIDEO_IMX214=m
+CONFIG_VIDEO_IMX219=m
+CONFIG_VIDEO_IMX258=m
+CONFIG_VIDEO_IMX274=m
+CONFIG_VIDEO_IMX283=m
+CONFIG_VIDEO_IMX290=m
+CONFIG_VIDEO_IMX296=m
+CONFIG_VIDEO_IMX319=m
+CONFIG_VIDEO_IMX355=m
+CONFIG_VIDEO_INTEL_IPU6=m
+CONFIG_VIDEO_INTEL_IPU7=m
+CONFIG_VIDEO_IPU3_CIO2=m
+CONFIG_VIDEO_IPU3_IMGU=m
+CONFIG_VIDEO_IR_I2C=m
+CONFIG_VIDEO_IVTV_ALSA=m
+CONFIG_VIDEO_IVTV=m
+CONFIG_VIDEO_KS0127=m
+CONFIG_VIDEO_LM3560=m
+CONFIG_VIDEO_LM3646=m
+CONFIG_VIDEO_M52790=m
+CONFIG_VIDEO_MAX9271_LIB=m
+CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
+CONFIG_VIDEO_MGB4=m
+CONFIG_VIDEO_MMP_CAMERA=m
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIDEO_MSP3400=m
+CONFIG_VIDEO_MT9M001=m
+CONFIG_VIDEO_MT9M111=m
+CONFIG_VIDEO_MT9M114=m
+CONFIG_VIDEO_MT9P031=m
+CONFIG_VIDEO_MT9T112=m
+CONFIG_VIDEO_MT9V011=m
+CONFIG_VIDEO_MT9V032=m
+CONFIG_VIDEO_MT9V111=m
+CONFIG_VIDEO_MXB=m
+CONFIG_VIDEO_NOMODESET=y
+CONFIG_VIDEO_OG01A1B=m
+CONFIG_VIDEO_OG0VE1B=m
+CONFIG_VIDEO_OV01A10=m
+CONFIG_VIDEO_OV02A10=m
+CONFIG_VIDEO_OV08D10=m
+CONFIG_VIDEO_OV08X40=m
+CONFIG_VIDEO_OV13858=m
+CONFIG_VIDEO_OV13B10=m
+CONFIG_VIDEO_OV2640=m
+CONFIG_VIDEO_OV2659=m
+CONFIG_VIDEO_OV2680=m
+CONFIG_VIDEO_OV2685=m
+CONFIG_VIDEO_OV2735=m
+CONFIG_VIDEO_OV2740=m
+CONFIG_VIDEO_OV4689=m
+CONFIG_VIDEO_OV5647=m
+CONFIG_VIDEO_OV5648=m
+CONFIG_VIDEO_OV5670=m
+CONFIG_VIDEO_OV5675=m
+CONFIG_VIDEO_OV5693=m
+CONFIG_VIDEO_OV5695=m
+CONFIG_VIDEO_OV6211=m
+CONFIG_VIDEO_OV64A40=m
+CONFIG_VIDEO_OV6650=m
+CONFIG_VIDEO_OV7251=m
+CONFIG_VIDEO_OV7640=m
+CONFIG_VIDEO_OV7670=m
+CONFIG_VIDEO_OV772X=m
+CONFIG_VIDEO_OV7740=m
+CONFIG_VIDEO_OV8856=m
+CONFIG_VIDEO_OV8858=m
+CONFIG_VIDEO_OV8865=m
+CONFIG_VIDEO_OV9640=m
+CONFIG_VIDEO_OV9650=m
+CONFIG_VIDEO_OV9734=m
+CONFIG_VIDEO_PVRUSB2_DVB=y
+CONFIG_VIDEO_PVRUSB2=m
+CONFIG_VIDEO_PVRUSB2_SYSFS=y
+CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m
+CONFIG_VIDEO_RDACM20=m
+CONFIG_VIDEO_RDACM21=m
+CONFIG_VIDEO_RJ54N1=m
+CONFIG_VIDEO_S5C73M3=m
+CONFIG_VIDEO_S5K5BAF=m
+CONFIG_VIDEO_S5K6A3=m
+CONFIG_VIDEO_SAA6588=m
+CONFIG_VIDEO_SAA6752HS=m
+CONFIG_VIDEO_SAA7110=m
+CONFIG_VIDEO_SAA711X=m
+CONFIG_VIDEO_SAA7127=m
+CONFIG_VIDEO_SAA7134_ALSA=m
+CONFIG_VIDEO_SAA7134_DVB=m
+CONFIG_VIDEO_SAA7134_GO7007=m
+CONFIG_VIDEO_SAA7134=m
+CONFIG_VIDEO_SAA7134_RC=y
+CONFIG_VIDEO_SAA7146=m
+CONFIG_VIDEO_SAA7146_VV=m
+CONFIG_VIDEO_SAA7164=m
+CONFIG_VIDEO_SAA717X=m
+CONFIG_VIDEO_SAA7185=m
+CONFIG_VIDEO_SOLO6X10=m
+CONFIG_VIDEO_SONY_BTF_MPX=m
+CONFIG_VIDEO_STK1160=m
+CONFIG_VIDEO_TC358746=m
+CONFIG_VIDEO_TDA7432=m
+CONFIG_VIDEO_TDA9840=m
+CONFIG_VIDEO_TEA6415C=m
+CONFIG_VIDEO_TEA6420=m
+CONFIG_VIDEO_THP7312=m
+CONFIG_VIDEO_TUNER=m
+CONFIG_VIDEO_TVAUDIO=m
+CONFIG_VIDEO_TVEEPROM=m
+CONFIG_VIDEO_TVP5150=m
+CONFIG_VIDEO_TW2804=m
+CONFIG_VIDEO_TW5864=m
+CONFIG_VIDEO_TW686X=m
+CONFIG_VIDEO_TW68=m
+CONFIG_VIDEO_TW9900=m
+CONFIG_VIDEO_TW9903=m
+CONFIG_VIDEO_TW9906=m
+CONFIG_VIDEO_UDA1342=m
+CONFIG_VIDEO_UPD64031A=m
+CONFIG_VIDEO_UPD64083=m
+CONFIG_VIDEO_USBTV=m
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_VIDEO_VP27SMPX=m
+CONFIG_VIDEO_VPX3220=m
+CONFIG_VIDEO_WM8739=m
+CONFIG_VIDEO_WM8775=m
+CONFIG_VIDEO_ZORAN_AVS6EYES=y
+CONFIG_VIDEO_ZORAN_BUZ=y
+CONFIG_VIDEO_ZORAN_DC10=y
+CONFIG_VIDEO_ZORAN_DC30=y
+CONFIG_VIDEO_ZORAN_LML33R10=y
+CONFIG_VIDEO_ZORAN_LML33=y
+CONFIG_VIDEO_ZORAN=m
+CONFIG_VIDEO_ZORAN_ZR36060=y
+CONFIG_VIPERBOARD_ADC=m
+CONFIG_VIRT_CPU_ACCOUNTING=y
+CONFIG_VIRT_DRIVERS=y
+CONFIG_VIRTIO_ANCHOR=y
+CONFIG_VIRTIO_BALLOON=m
+CONFIG_VIRTIO_BLK=m
+CONFIG_VIRTIO_CONSOLE=m
+CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
+CONFIG_VIRTIO_INPUT=m
+CONFIG_VIRTIO_IOMMU=m
+CONFIG_VIRTIO=m
+CONFIG_VIRTIO_MEM=m
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_VIRTIO_MMIO=m
+CONFIG_VIRTIO_NET=m
+CONFIG_VIRTIO_PCI_LIB_LEGACY=m
+CONFIG_VIRTIO_PCI_LIB=m
+CONFIG_VIRTIO_PCI=m
+CONFIG_VIRTIO_PMEM=m
+CONFIG_VIRTIO_VDPA=m
+CONFIG_VIRTIO_VFIO_PCI=m
+CONFIG_VIRTUALIZATION=y
+CONFIG_VIRT_WIFI=m
+CONFIG_VITESSE_PHY=m
+CONFIG_VL53L0X_I2C=m
+CONFIG_VL6180=m
+CONFIG_VMAP_PFN=y
+CONFIG_VMAP_STACK=y
+CONFIG_VMD=m
+CONFIG_VME_BUS=y
+CONFIG_VME_FAKE=m
+CONFIG_VME_TSI148=m
+CONFIG_VME_USER=m
+CONFIG_VMGENID=m
+CONFIG_VMWARE_BALLOON=m
+CONFIG_VMWARE_PVSCSI=m
+CONFIG_VMWARE_VMCI=m
+CONFIG_VMXNET3=m
+CONFIG_VP_VDPA=m
+CONFIG_VSOCKMON=m
+CONFIG_VT6655=m
+CONFIG_VT6656=m
+CONFIG_VXLAN=m
+CONFIG_VZ89X=m
+CONFIG_W1_CON=y
+CONFIG_W1=m
+CONFIG_W1_MASTER_AMD_AXI=m
+CONFIG_W1_MASTER_DS2482=m
+CONFIG_W1_MASTER_DS2490=m
+CONFIG_W1_MASTER_GPIO=m
+CONFIG_W1_MASTER_MATROX=m
+CONFIG_W1_MASTER_SGI=m
+CONFIG_W1_MASTER_UART=m
+CONFIG_W1_SLAVE_DS2406=m
+CONFIG_W1_SLAVE_DS2408=m
+CONFIG_W1_SLAVE_DS2413=m
+CONFIG_W1_SLAVE_DS2423=m
+CONFIG_W1_SLAVE_DS2430=m
+CONFIG_W1_SLAVE_DS2431=m
+CONFIG_W1_SLAVE_DS2433_CRC=y
+CONFIG_W1_SLAVE_DS2433=m
+CONFIG_W1_SLAVE_DS2438=m
+CONFIG_W1_SLAVE_DS250X=m
+CONFIG_W1_SLAVE_DS2780=m
+CONFIG_W1_SLAVE_DS2781=m
+CONFIG_W1_SLAVE_DS2805=m
+CONFIG_W1_SLAVE_DS28E04=m
+CONFIG_W1_SLAVE_DS28E17=m
+CONFIG_W1_SLAVE_SMEM=m
+CONFIG_W1_SLAVE_THERM=m
+CONFIG_W83627HF_WDT=m
+CONFIG_W83877F_WDT=m
+CONFIG_W83977F_WDT=m
+CONFIG_WAFER_WDT=m
+CONFIG_WANT_DEV_COREDUMP=y
+CONFIG_WANXL=m
+CONFIG_WAN=y
+CONFIG_WATCHDOG_CORE=m
+CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=0
+CONFIG_WATCHDOG=y
+CONFIG_WCN36XX=m
+CONFIG_WDAT_WDT=m
+CONFIG_WDTPCI=m
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PRIV=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_WFX=m
+CONFIG_WIL6210_DEBUGFS=y
+CONFIG_WIL6210_ISR_COR=y
+CONFIG_WIL6210=m
+CONFIG_WILC1000=m
+CONFIG_WILC1000_SDIO=m
+CONFIG_WILC1000_SPI=m
+CONFIG_WILCO_EC_DEBUGFS=m
+CONFIG_WILCO_EC_EVENTS=m
+CONFIG_WILCO_EC=m
+CONFIG_WILCO_EC_TELEMETRY=m
+CONFIG_WINMATE_FM07_KEYS=m
+CONFIG_WIREGUARD=m
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_HOTKEY=m
+CONFIG_WL1251=m
+CONFIG_WL1251_SDIO=m
+CONFIG_WL1251_SPI=m
+CONFIG_WL12XX=m
+CONFIG_WL18XX=m
+CONFIG_WLAN_VENDOR_CISCO=y
+CONFIG_WLCORE=m
+CONFIG_WLCORE_SDIO=m
+CONFIG_WM831X_BACKUP=m
+CONFIG_WM831X_POWER=m
+CONFIG_WM831X_WATCHDOG=m
+CONFIG_WM8350_POWER=m
+CONFIG_WM8350_WATCHDOG=m
+CONFIG_WMI_BMOF=m
+CONFIG_WPCM450_SOC=m
+CONFIG_WWAN_HWSIM=m
+CONFIG_WWAN=y
+CONFIG_X86_16BIT=y
+CONFIG_X86_64_ACPI_NUMA=y
+CONFIG_X86_64_SMP=y
+CONFIG_X86_64=y
+CONFIG_X86_ACPI_CPUFREQ_CPB=y
+CONFIG_X86_ACPI_CPUFREQ=m
+CONFIG_X86_AMD_FREQ_SENSITIVITY=m
+CONFIG_X86_AMD_PLATFORM_DEVICE=y
+CONFIG_X86_AMD_PSTATE_DEFAULT_MODE=3
+CONFIG_X86_AMD_PSTATE_UT=m
+CONFIG_X86_AMD_PSTATE=y
+CONFIG_X86_ANDROID_TABLETS=m
+CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y
+CONFIG_X86_CHECK_BIOS_CORRUPTION=y
+CONFIG_X86_CMOV=y
+CONFIG_X86_CMPXCHG64=y
+CONFIG_X86_CPUID=m
+CONFIG_X86_CPU_RESCTRL=y
+CONFIG_X86_DEBUGCTLMSR=y
+CONFIG_X86_DIRECT_GBPAGES=y
+CONFIG_X86_ESPFIX64=y
+CONFIG_X86_FRED=y
+CONFIG_X86_HV_CALLBACK_VECTOR=y
+CONFIG_X86_INTEL_LPSS=y
+CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y
+CONFIG_X86_INTEL_PSTATE=y
+CONFIG_X86_INTEL_TSX_MODE_OFF=y
+CONFIG_X86_INTERNODE_CACHE_SHIFT=6
+CONFIG_X86_IO_APIC=y
+CONFIG_X86_IOPL_IOPERM=y
+CONFIG_X86_KERNEL_IBT=y
+CONFIG_X86_L1_CACHE_SHIFT=6
+CONFIG_X86_LOCAL_APIC=y
+CONFIG_X86_MCE_AMD=y
+CONFIG_X86_MCE_INTEL=y
+CONFIG_X86_MCE_THRESHOLD=y
+CONFIG_X86_MCE=y
+CONFIG_X86_MEM_ENCRYPT=y
+CONFIG_X86_MINIMUM_CPU_FAMILY=64
+CONFIG_X86_MPPARSE=y
+CONFIG_X86_MSR=m
+CONFIG_X86_NEED_RELOCS=y
+CONFIG_X86_PAT=y
+CONFIG_X86_PCC_CPUFREQ=m
+CONFIG_X86_PKG_TEMP_THERMAL=m
+CONFIG_X86_PLATFORM_DEVICES=y
+CONFIG_X86_PLATFORM_DRIVERS_DELL=y
+CONFIG_X86_PLATFORM_DRIVERS_HP=y
+CONFIG_X86_PMEM_LEGACY_DEVICE=y
+CONFIG_X86_PMEM_LEGACY=m
+CONFIG_X86_PM_TIMER=y
+CONFIG_X86_POWERNOW_K8=m
+CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
+CONFIG_X86_SGX_KVM=y
+CONFIG_X86_SGX=y
+CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
+CONFIG_X86_THERMAL_VECTOR=y
+CONFIG_X86_TSC=y
+CONFIG_X86_UMIP=y
+CONFIG_X86_USER_SHADOW_STACK=y
+CONFIG_X86_VERBOSE_BOOTUP=y
+CONFIG_X86_VMX_FEATURE_NAMES=y
+CONFIG_X86_VSYSCALL_EMULATION=y
+CONFIG_X86_X2APIC=y
+CONFIG_X86_X32_ABI=y
+CONFIG_X86=y
+CONFIG_X9250=m
+CONFIG_XARRAY_MULTI=y
+CONFIG_XIAOMI_WMI=m
+CONFIG_XILINX_DMA=m
+CONFIG_XILINX_GMII2RGMII=m
+CONFIG_XILINX_PR_DECOUPLER=m
+CONFIG_XILINX_SDFEC=m
+CONFIG_XILINX_WATCHDOG=m
+CONFIG_XILINX_XADC=m
+CONFIG_XILINX_XDMA=m
+CONFIG_XILLYBUS_CLASS=m
+CONFIG_XILLYBUS=m
+CONFIG_XILLYBUS_PCIE=m
+CONFIG_XILLYUSB=m
+CONFIG_XOR_BLOCKS=m
 CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_SPARC=y
 CONFIG_XZ_DEC_MICROLZMA=y
-CONFIG_XZ_DEC_BCJ=y
-# CONFIG_XZ_DEC_TEST is not set
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_LZ4=y
-CONFIG_DECOMPRESS_ZSTD=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_REED_SOLOMON=m
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_DEC16=y
-CONFIG_BCH=m
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_BTREE=y
-CONFIG_INTERVAL_TREE=y
-CONFIG_XARRAY_MULTI=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAS_DMA=y
-CONFIG_DMA_OPS=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED=y
-CONFIG_SWIOTLB=y
-CONFIG_DMA_COHERENT_POOL=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_PERNUMA_CMA=y
-
-#
-# Default contiguous memory area size:
-#
-CONFIG_CMA_SIZE_MBYTES=0
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_ALIGNMENT=8
-# CONFIG_DMA_API_DEBUG is not set
-# CONFIG_DMA_MAP_BENCHMARK is not set
-CONFIG_SGL_ALLOC=y
-CONFIG_IOMMU_HELPER=y
-CONFIG_CHECK_SIGNATURE=y
-CONFIG_CPUMASK_OFFSTACK=y
-CONFIG_CPU_RMAP=y
-CONFIG_DQL=y
-CONFIG_GLOB=y
-# CONFIG_GLOB_SELFTEST is not set
-CONFIG_NLATTR=y
-CONFIG_LRU_CACHE=m
-CONFIG_CLZ_TAB=y
-CONFIG_IRQ_POLL=y
-CONFIG_MPILIB=y
-CONFIG_DIMLIB=y
-CONFIG_OID_REGISTRY=y
-CONFIG_UCS2_STRING=y
-CONFIG_HAVE_GENERIC_VDSO=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_VDSO_TIME_NS=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_6x10 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-CONFIG_FONT_TER16x32=y
-CONFIG_FONT_6x8=y
-CONFIG_SG_POOL=y
-CONFIG_ARCH_HAS_PMEM_API=y
-CONFIG_MEMREGION=y
-CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y
-CONFIG_ARCH_HAS_COPY_MC=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_SBITMAP=y
-CONFIG_PARMAN=m
-CONFIG_OBJAGG=m
-# end of Library routines
-
-CONFIG_PLDMFW=y
-CONFIG_ASN1_ENCODER=m
-
-#
-# Kernel hacking
-#
-
-#
-# printk and dmesg options
-#
-# CONFIG_PRINTK_TIME is not set
-# CONFIG_PRINTK_CALLER is not set
-CONFIG_STACKTRACE_BUILD_ID=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
-CONFIG_CONSOLE_LOGLEVEL_QUIET=4
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_DYNAMIC_DEBUG_CORE is not set
-CONFIG_SYMBOLIC_ERRNAME=y
-CONFIG_DEBUG_BUGVERBOSE=y
-# end of printk and dmesg options
-
-#
-# Compile-time checks and compiler options
-#
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_INFO_REDUCED is not set
-# CONFIG_DEBUG_INFO_COMPRESSED is not set
-# CONFIG_DEBUG_INFO_SPLIT is not set
-# CONFIG_DEBUG_INFO_NONE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-# CONFIG_DEBUG_INFO_DWARF4 is not set
-# CONFIG_DEBUG_INFO_DWARF5 is not set
-CONFIG_DEBUG_INFO_BTF=y
-CONFIG_MODULE_ALLOW_BTF_MISMATCH=y
-CONFIG_PAHOLE_HAS_SPLIT_BTF=y
-CONFIG_DEBUG_INFO_BTF_MODULES=y
-# CONFIG_GDB_SCRIPTS is not set
-CONFIG_FRAME_WARN=0
-CONFIG_STRIP_ASM_SYMS=y
-# CONFIG_READABLE_ASM is not set
-# CONFIG_HEADERS_INSTALL is not set
-# CONFIG_DEBUG_SECTION_MISMATCH is not set
-CONFIG_SECTION_MISMATCH_WARN_ONLY=y
-# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
-CONFIG_STACK_VALIDATION=y
-CONFIG_VMLINUX_MAP=y
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# end of Compile-time checks and compiler options
-
-#
-# Generic Kernel Debugging Instruments
-#
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
-CONFIG_MAGIC_SYSRQ_SERIAL=y
-CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_FS_ALLOW_ALL is not set
-# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
-# CONFIG_DEBUG_FS_ALLOW_NONE is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ARCH_KCSAN=y
-CONFIG_HAVE_KCSAN_COMPILER=y
-# CONFIG_KCSAN is not set
-# end of Generic Kernel Debugging Instruments
-
-# CONFIG_DEBUG_KERNEL is not set
-# CONFIG_DEBUG_MISC is not set
-
-#
-# Memory Debugging
-#
-# CONFIG_PAGE_EXTENSION is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
-# CONFIG_PAGE_OWNER is not set
-# CONFIG_PAGE_TABLE_CHECK is not set
-# CONFIG_PAGE_POISONING is not set
-# CONFIG_DEBUG_PAGE_REF is not set
-# CONFIG_DEBUG_RODATA_TEST is not set
-CONFIG_ARCH_HAS_DEBUG_WX=y
-CONFIG_DEBUG_WX=y
-CONFIG_GENERIC_PTDUMP=y
-CONFIG_PTDUMP_CORE=y
-# CONFIG_PTDUMP_DEBUGFS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SHRINKER_DEBUG is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_HAVE_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_SCHED_STACK_END_CHECK is not set
-# CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_VM_PGTABLE is not set
-# CONFIG_ARCH_HAS_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_PER_CPU_MAPS is not set
-CONFIG_HAVE_ARCH_KASAN=y
-CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
-CONFIG_CC_HAS_KASAN_GENERIC=y
-CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
-# CONFIG_KASAN is not set
-CONFIG_HAVE_ARCH_KFENCE=y
-# CONFIG_KFENCE is not set
-# end of Memory Debugging
-
-# CONFIG_DEBUG_SHIRQ is not set
-
-#
-# Debug Oops, Lockups and Hangs
-#
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=60
-# CONFIG_SOFTLOCKUP_DETECTOR is not set
-CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y
-# CONFIG_HARDLOCKUP_DETECTOR is not set
-# CONFIG_DETECT_HUNG_TASK is not set
-# CONFIG_WQ_WATCHDOG is not set
-CONFIG_TEST_LOCKUP=m
-# end of Debug Oops, Lockups and Hangs
-
-#
-# Scheduler Debugging
-#
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHED_INFO=y
-CONFIG_SCHEDSTATS=y
-# end of Scheduler Debugging
-
-# CONFIG_DEBUG_TIMEKEEPING is not set
-# CONFIG_DEBUG_PREEMPT is not set
-
-#
-# Lock Debugging (spinlocks, mutexes, etc...)
-#
-# CONFIG_LOCK_DEBUGGING_SUPPORT is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
-# CONFIG_DEBUG_RWSEMS is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_DEBUG_ATOMIC_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_LOCK_TORTURE_TEST is not set
-# CONFIG_WW_MUTEX_SELFTEST is not set
-CONFIG_SCF_TORTURE_TEST=m
-# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
-# end of Lock Debugging (spinlocks, mutexes, etc...)
-
-# CONFIG_DEBUG_IRQFLAGS is not set
-CONFIG_STACKTRACE=y
-# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
-# CONFIG_DEBUG_KOBJECT is not set
-
-#
-# Debug kernel data structures
-#
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_PLIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BUG_ON_DATA_CORRUPTION is not set
-# end of Debug kernel data structures
-
-# CONFIG_DEBUG_CREDENTIALS is not set
-
-#
-# RCU Debugging
-#
-CONFIG_TORTURE_TEST=m
-CONFIG_RCU_SCALE_TEST=m
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_REF_SCALE_TEST=m
-CONFIG_RCU_CPU_STALL_TIMEOUT=60
-# CONFIG_RCU_TRACE is not set
-# CONFIG_RCU_EQS_DEBUG is not set
-# end of RCU Debugging
-
-# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-CONFIG_LATENCYTOP=y
-CONFIG_USER_STACKTRACE_SUPPORT=y
-CONFIG_NOP_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_FENTRY=y
-CONFIG_HAVE_OBJTOOL_MCOUNT=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_RING_BUFFER=y
-CONFIG_EVENT_TRACING=y
-CONFIG_CONTEXT_SWITCH_TRACER=y
-CONFIG_TRACING=y
-CONFIG_GENERIC_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-CONFIG_FTRACE=y
-CONFIG_BOOTTIME_TRACING=y
-CONFIG_FUNCTION_TRACER=y
-# CONFIG_FUNCTION_GRAPH_TRACER is not set
-CONFIG_DYNAMIC_FTRACE=y
-CONFIG_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
-CONFIG_DYNAMIC_FTRACE_WITH_ARGS=y
-# CONFIG_FPROBE is not set
-CONFIG_FUNCTION_PROFILER=y
-CONFIG_STACK_TRACER=y
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_HWLAT_TRACER is not set
-# CONFIG_OSNOISE_TRACER is not set
-# CONFIG_TIMERLAT_TRACER is not set
-# CONFIG_MMIOTRACE is not set
-CONFIG_FTRACE_SYSCALLS=y
-# CONFIG_TRACER_SNAPSHOT is not set
-CONFIG_BRANCH_PROFILE_NONE=y
-# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
-# CONFIG_PROFILE_ALL_BRANCHES is not set
-CONFIG_BLK_DEV_IO_TRACE=y
-CONFIG_KPROBE_EVENTS=y
-# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set
-# CONFIG_UPROBE_EVENTS is not set
-CONFIG_BPF_EVENTS=y
-CONFIG_DYNAMIC_EVENTS=y
-CONFIG_PROBE_EVENTS=y
-CONFIG_BPF_KPROBE_OVERRIDE=y
-CONFIG_FTRACE_MCOUNT_RECORD=y
-CONFIG_FTRACE_MCOUNT_USE_CC=y
-# CONFIG_SYNTH_EVENTS is not set
-# CONFIG_HIST_TRIGGERS is not set
-# CONFIG_TRACE_EVENT_INJECT is not set
-# CONFIG_TRACEPOINT_BENCHMARK is not set
-# CONFIG_RING_BUFFER_BENCHMARK is not set
-# CONFIG_TRACE_EVAL_MAP_FILE is not set
-CONFIG_FTRACE_RECORD_RECURSION=y
-CONFIG_FTRACE_RECORD_RECURSION_SIZE=128
-CONFIG_RING_BUFFER_RECORD_RECURSION=y
-# CONFIG_FTRACE_STARTUP_TEST is not set
-# CONFIG_RING_BUFFER_STARTUP_TEST is not set
-# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
-CONFIG_PREEMPTIRQ_DELAY_TEST=m
-CONFIG_KPROBE_EVENT_GEN_TEST=m
-# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y
-CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y
-CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
-CONFIG_STRICT_DEVMEM=y
-# CONFIG_IO_STRICT_DEVMEM is not set
-
-#
-# x86 Debugging
-#
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_X86_VERBOSE_BOOTUP=y
-# CONFIG_EARLY_PRINTK is not set
-# CONFIG_EFI_PGT_DUMP is not set
-# CONFIG_DEBUG_TLBFLUSH is not set
-# CONFIG_IOMMU_DEBUG is not set
-CONFIG_HAVE_MMIOTRACE_SUPPORT=y
-# CONFIG_X86_DECODER_SELFTEST is not set
-CONFIG_IO_DELAY_0X80=y
-# CONFIG_IO_DELAY_0XED is not set
-# CONFIG_IO_DELAY_UDELAY is not set
-# CONFIG_IO_DELAY_NONE is not set
-# CONFIG_DEBUG_BOOT_PARAMS is not set
-# CONFIG_CPA_DEBUG is not set
-# CONFIG_DEBUG_ENTRY is not set
-# CONFIG_DEBUG_NMI_SELFTEST is not set
-# CONFIG_X86_DEBUG_FPU is not set
-# CONFIG_PUNIT_ATOM_DEBUG is not set
-CONFIG_UNWINDER_ORC=y
-# CONFIG_UNWINDER_FRAME_POINTER is not set
-# CONFIG_UNWINDER_GUESS is not set
-# end of x86 Debugging
-
-#
-# Kernel Testing and Coverage
-#
-# CONFIG_KUNIT is not set
-# CONFIG_NOTIFIER_ERROR_INJECTION is not set
-CONFIG_FUNCTION_ERROR_INJECTION=y
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_ARCH_HAS_KCOV=y
-CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-# CONFIG_KCOV is not set
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_ARCH_USE_MEMTEST=y
-CONFIG_MEMTEST=y
-# CONFIG_HYPERV_TESTING is not set
-# end of Kernel Testing and Coverage
-# end of Kernel hacking
-# CONFIG_ANON_VMA_NAME is not set
-CONFIG_NET_9P_FD=m
-CONFIG_DEVTMPFS_SAFE=y
-CONFIG_GNSS_USB=m
-CONFIG_MTD_NAND_RENESAS=m
-CONFIG_NET_VENDOR_ENGLEDER=y
-CONFIG_TSNEP=m
-# CONFIG_TSNEP_SELFTESTS is not set
-CONFIG_LAN966X_SWITCH=m
-CONFIG_NET_VENDOR_VERTEXCOM=y
-CONFIG_MSE102X=m
-CONFIG_MCTP_SERIAL=m
-CONFIG_MCTP_TRANSPORT_I2C=m
-# CONFIG_WWAN_DEBUGFS is not set
-CONFIG_SERIAL_8250_PERICOM=m
-CONFIG_SPMI_MTK_PMIF=m
-CONFIG_PINCTRL_IMXRT1050=y
-CONFIG_PINCTRL_IMX93=m
-CONFIG_PINCTRL_SDX65=m
-CONFIG_PINCTRL_SM8450=m
-CONFIG_PINCTRL_SM8450_LPASS_LPI=m
-CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
-CONFIG_PINCTRL_SM8280XP_LPASS_LPI=m
-CONFIG_GPIO_SIM=m
-CONFIG_CHARGER_MAX77976=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_SENSORS_NZXT_SMART2=m
-CONFIG_SENSORS_DELTA_AHE50DC_FAN=m
-CONFIG_SENSORS_IR38064_REGULATOR=y
-CONFIG_SENSORS_MP5023=m
-CONFIG_SENSORS_INA238=m
-CONFIG_RZG2L_THERMAL=m
-CONFIG_RENESAS_RZG2LWDT=m
-CONFIG_REGULATOR_MAX20086=m
-CONFIG_VIDEO_STM32_DMA2D=m
-CONFIG_VIDEO_OV5693=m
-CONFIG_DRM_RCAR_USE_LVDS=y
-CONFIG_DRM_RCAR_USE_MIPI_DSI=y
-CONFIG_DRM_RCAR_MIPI_DSI=m
-CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
-CONFIG_DRM_PANEL_JDI_R63452=m
-CONFIG_DRM_PANEL_NOVATEK_NT35950=m
-CONFIG_DRM_PANEL_NOVATEK_NT35560=m
-CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
-CONFIG_TINYDRM_ILI9163=m
-CONFIG_SND_AMD_ACP_CONFIG=m
-CONFIG_SND_SOC_APPLE_MCA=m
-CONFIG_SND_SOC_AK4375=m
-CONFIG_SND_SOC_TLV320ADC3XXX=m
-CONFIG_HID_LETSKETCH=m
-CONFIG_LEDS_MT6360=m
-CONFIG_VIDEO_MAX96712=m
-CONFIG_COMMON_CLK_LAN966X=y
-CONFIG_COMMON_CLK_MT7986=y
-CONFIG_COMMON_CLK_MT7986_ETHSYS=y
-CONFIG_RENESAS_OSTM=y
-CONFIG_EXYNOS_USI=m
-CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
-CONFIG_AD74413R=m
-CONFIG_AD3552R=m
-CONFIG_AD7293=m
-CONFIG_ADMV1013=m
-CONFIG_ADMV1014=m
-CONFIG_ADMV4420=m
-CONFIG_PHY_MESON8_HDMI_TX=m
-CONFIG_PHY_FSL_IMX8M_PCIE=m
-CONFIG_PHY_FSL_LYNX_28G=m
-CONFIG_PHY_LAN966X_SERDES=m
-CONFIG_PHY_QCOM_EDP=m
-# CONFIG_CACHEFILES_ERROR_INJECTION is not set
-CONFIG_UNICODE_UTF8_DATA=m
-# CONFIG_NET_DEV_REFCNT_TRACKER is not set
-# CONFIG_NET_NS_REFCNT_TRACKER is not set
-# CONFIG_KFENCE is not set
-# CONFIG_FTRACE_SORT_STARTUP_TEST is not set
-CONFIG_BACKTRACE_VERBOSE=y
-CONFIG_ADMV8818=m
-CONFIG_MARVELL_CN10K_TAD_PMU=m
-# CONFIG_KCSAN is not set
-# CONFIG_BOOT_CONFIG_EMBED is not set
-CONFIG_INITRAMFS_PRESERVE_MTIME=y
-CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y
-CONFIG_ARCH_BCMBCA=y
-CONFIG_ARCH_HPE=y
-CONFIG_ARCH_HPE_GXP=y
-CONFIG_ARM_ERRATA_764319=y
-# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
-CONFIG_CAN_CTUCANFD_PCI=m
-CONFIG_CAN_CTUCANFD_PLATFORM=m
-CONFIG_FW_LOADER_COMPRESS_XZ=y
-CONFIG_FW_LOADER_COMPRESS_ZSTD=y
-CONFIG_FW_UPLOAD=y
-CONFIG_QCOM_SSC_BLOCK_BUS=y
-CONFIG_MHI_BUS_EP=m
-CONFIG_MTK_ADSP_IPC=m
-CONFIG_EFI_COCO_SECRET=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=m
-CONFIG_SFC_SIENA=m
-CONFIG_SFC_SIENA_MTD=y
-CONFIG_SFC_SIENA_MCDI_MON=y
-CONFIG_SFC_SIENA_SRIOV=y
-# CONFIG_SFC_SIENA_MCDI_LOGGING is not set
-CONFIG_ADIN1100_PHY=m
-CONFIG_DP83TD510_PHY=m
-CONFIG_WLAN_VENDOR_PURELIFI=y
-CONFIG_PLFXLC=m
-CONFIG_RTW89_8852CE=m
-CONFIG_WLAN_VENDOR_SILABS=y
-CONFIG_MTK_T7XX=m
-CONFIG_JOYSTICK_SENSEHAT=m
-CONFIG_INPUT_IQS7222=m
-# CONFIG_HVC_DCC_SERIALIZE_SMP is not set
-CONFIG_SPI_MTK_SNFI=m
-CONFIG_PINCTRL_IMXRT1170=y
-CONFIG_PINCTRL_SC7280_LPASS_LPI=m
-CONFIG_PINCTRL_SM8250_LPASS_LPI=m
-CONFIG_SENSORS_LAN966X=m
-CONFIG_SENSORS_NCT6775_I2C=m
-CONFIG_SENSORS_XDPE152=m
-CONFIG_RENESAS_RZN1WDT=m
-CONFIG_GXP_WATCHDOG=m
-CONFIG_REGULATOR_RT5759=m
-CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
-CONFIG_DRM_FSL_LDB=m
-CONFIG_DRM_LONTIUM_LT9211=m
-CONFIG_DRM_DW_HDMI_GP_AUDIO=m
-CONFIG_DRM_SSD130X_SPI=m
-CONFIG_SND_SERIAL_GENERIC=m
-CONFIG_SND_SOC_CS35L45_SPI=m
-CONFIG_SND_SOC_CS35L45_I2C=m
-CONFIG_SND_SOC_MAX98396=m
-CONFIG_SND_SOC_WM8731_I2C=m
-CONFIG_SND_SOC_WM8731_SPI=m
-CONFIG_SND_SOC_WM8940=m
-CONFIG_HID_MEGAWORLD_FF=m
-CONFIG_TYPEC_MUX_FSA4480=m
-CONFIG_LEDS_PWM_MULTICOLOR=m
-CONFIG_LEDS_QCOM_LPG=m
-CONFIG_TEGRA186_GPC_DMA=m
-# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set
-CONFIG_PWM_XILINX=m
-CONFIG_HTE=y
-# CONFIG_CACHEFILES_ONDEMAND is not set
-CONFIG_TRUSTED_KEYS_TPM=y
-CONFIG_TRUSTED_KEYS_TEE=y
-CONFIG_CRYPTO_SM3_GENERIC=m
-CONFIG_CRYPTO_SM4_GENERIC=m
-# CONFIG_FIPS_SIGNATURE_SELFTEST is not set
-CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y
-# CONFIG_DEBUG_NET is not set
-CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
-CONFIG_SPECULATION_MITIGATIONS=y
-CONFIG_EFI_DXE_MEM_ATTRIBUTES=y
-CONFIG_INTEL_MEI_GSC=m
-CONFIG_PINCTRL_AMD=y
-CONFIG_WINMATE_FM07_KEYS=m
-CONFIG_CHROMEOS_ACPI=m
-CONFIG_NVSW_SN2201=m
-CONFIG_DMARD06=m
-CONFIG_IIO_RESCALE=m
-CONFIG_DPOT_DAC=m
-CONFIG_VF610_DAC=m
-CONFIG_CM3605=m
-CONFIG_AK8974=m
-CONFIG_IIO_MUX=m
-CONFIG_RETHUNK=y
-CONFIG_CPU_UNRET_ENTRY=y
-# CONFIG_CGROUP_FAVOR_DYNMODS is not set
-CONFIG_ARCH_BCMBCA_CORTEXA7=y
-CONFIG_ARCH_BCMBCA_CORTEXA9=y
-CONFIG_ARCH_BCMBCA_BRAHMAB15=y
-CONFIG_ARCH_MSM8909=y
-CONFIG_ARCH_SUNPLUS=y
-CONFIG_SOC_SP7021=y
-# CONFIG_UNUSED_BOARD_FILES is not set
-# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
-CONFIG_DAMON_LRU_SORT=y
-CONFIG_NF_FLOW_TABLE_PROCFS=y
-CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
-CONFIG_PCI_EPF_VNTB=m
-CONFIG_ARM_SCMI_POWER_CONTROL=m
-CONFIG_BLK_DEV_UBLK=m
-CONFIG_NVME_AUTH=y
-CONFIG_NVME_TARGET_AUTH=y
-CONFIG_VCPU_STALL_DETECTOR=m
-CONFIG_SCSI_BUSLOGIC=m
-CONFIG_SCSI_FLASHPOINT=y
-CONFIG_AHCI_BRCM=m
-CONFIG_AHCI_DWC=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
-CONFIG_NET_VENDOR_WANGXUN=y
-CONFIG_NET_VENDOR_ADI=y
-CONFIG_ADIN1110=m
-CONFIG_NGBE=m
-CONFIG_TXGBE=m
-CONFIG_NET_VENDOR_SUNPLUS=y
-CONFIG_SP7021_EMAC=m
-CONFIG_CAN_NETLINK=y
-CONFIG_CAN_CAN327=m
-CONFIG_CAN_ESD_USB=m
-CONFIG_HW_RANDOM_BCM2835=m
-CONFIG_TCG_TIS_I2C=m
-# CONFIG_RANDOM_TRUST_CPU is not set
-CONFIG_I2C_BRCMSTB=m
-CONFIG_I2C_NPCM=m
-CONFIG_I2C_RZV2M=m
-CONFIG_SPI_BCM63XX_HSSPI=m
-CONFIG_SPI_GXP=m
-CONFIG_SPI_MICROCHIP_CORE=m
-CONFIG_SPI_MICROCHIP_CORE_QSPI=m
-CONFIG_SPI_SUNPLUS_SP7021=m
-CONFIG_PINCTRL_MSM8909=m
-CONFIG_PINCTRL_SM6375=m
-CONFIG_PINCTRL_SUN20I_D1=y
-CONFIG_SENSORS_LT7182S=m
-CONFIG_SUNPLUS_WATCHDOG=m
-CONFIG_VIDEO_SUN6I_MIPI_CSI2=m
-CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m
-CONFIG_VIDEO_AR0521=m
-CONFIG_DRM_PANEL_EBBG_FT8719=m
-CONFIG_DRM_TI_DLPC3433=m
-CONFIG_DRM_IMX8QM_LDB=m
-# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set
-CONFIG_RCU_NOCB_CPU_DEFAULT_ALL=y
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-# CONFIG_RV is not set
-CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT274=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT286=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT298=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567=m
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_BINDERFS=y
-CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
-# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
-# Ethernet Power Sourcing Equipment Support
-CONFIG_PSE_CONTROLLER=y
-CONFIG_PSE_REGULATOR=m
-CONFIG_STAGING_MEDIA_DEPRECATED=y
-# CONFIG_FORCE_NR_CPUS is not set
-# CONFIG_DEBUG_MAPLE_TREE is not set
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_KERNEL_ZSTD=y
-# CONFIG_KMSAN is not set
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_YAMAHA_YAS530=m
+CONFIG_YENTA_ENE_TUNE=y
+CONFIG_YENTA=m
+CONFIG_YENTA_O2=y
+CONFIG_YENTA_RICOH=y
+CONFIG_YENTA_TI=y
+CONFIG_YENTA_TOSHIBA=y
+CONFIG_YOGABOOK=m
+CONFIG_YT2_1380=m
+CONFIG_ZD1211RW=m
+CONFIG_ZIIRAVE_WATCHDOG=m
+CONFIG_ZL3073X_SPI=m
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZONE_DMA=y
+CONFIG_ZOPT2201=m
+CONFIG_ZPA2326_I2C=m
+CONFIG_ZPA2326=m
+CONFIG_ZPA2326_SPI=m
+CONFIG_ZPOOL=y
+CONFIG_ZRAM_DEF_COMP="zstd"
+CONFIG_ZRAM_MULTI_COMP=y
+CONFIG_ZRAM_TRACK_ENTRY_ACTIME=y
+CONFIG_ZRAM_WRITEBACK=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_NEXUS=m
diff --git a/x86_64-server-gcc-omv-defconfig b/x86_64-server-gcc-omv-defconfig
deleted file mode 100644
index 065a264..0000000
--- a/x86_64-server-gcc-omv-defconfig
+++ /dev/null
@@ -1,11246 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# Linux/x86 5.16.1-desktop-clang-1omv4050 Kernel Configuration
-#
-CONFIG_CC_VERSION_TEXT="gcc (GCC) 11.2.0 20210728 (OpenMandriva)"
-CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=110200
-CONFIG_CLANG_VERSION=0
-CONFIG_AS_IS_GNU=y
-CONFIG_AS_VERSION=23700
-CONFIG_LD_VERSION=0
-CONFIG_LD_IS_LLD=y
-CONFIG_LLD_VERSION=130000
-CONFIG_CC_CAN_LINK=y
-CONFIG_CC_CAN_LINK_STATIC=y
-CONFIG_CC_HAS_ASM_GOTO=y
-CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
-CONFIG_TOOLS_SUPPORT_RELR=y
-CONFIG_CC_HAS_ASM_INLINE=y
-CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
-CONFIG_IRQ_WORK=y
-CONFIG_BUILDTIME_TABLE_SORT=y
-CONFIG_THREAD_INFO_IN_TASK=y
-
-#
-# General setup
-#
-CONFIG_INIT_ENV_ARG_LIMIT=32
-# CONFIG_COMPILE_TEST is not set
-# CONFIG_WERROR is not set
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_BUILD_SALT="128d12afcb8aebec973186c3f254745b9d073bf5"
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_BZIP2=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_XZ=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_HAVE_KERNEL_LZ4=y
-CONFIG_HAVE_KERNEL_ZSTD=y
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_BZIP2 is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_KERNEL_ZSTD=y
-CONFIG_DEFAULT_INIT=""
-CONFIG_DEFAULT_HOSTNAME="omv"
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_POSIX_MQUEUE_SYSCTL=y
-# CONFIG_WATCH_QUEUE is not set
-CONFIG_CROSS_MEMORY_ATTACH=y
-# CONFIG_USELIB is not set
-# CONFIG_AUDIT is not set
-# CONFIG_HAVE_ARCH_AUDITSYSCALL is not set
-# CONFIG_AUDITSYSCALL is not set
-
-#
-# IRQ subsystem
-#
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_SIM=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_IRQ_MSI_IOMMU=y
-CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
-CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_SPARSE_IRQ=y
-# CONFIG_GENERIC_IRQ_DEBUGFS is not set
-# end of IRQ subsystem
-
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-CONFIG_ARCH_CLOCKSOURCE_INIT=y
-CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-
-#
-# Timers subsystem
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ_COMMON=y
-# CONFIG_HZ_PERIODIC is not set
-CONFIG_NO_HZ_IDLE=y
-# CONFIG_NO_HZ_FULL is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
-# end of Timers subsystem
-
-CONFIG_BPF=y
-CONFIG_HAVE_EBPF_JIT=y
-CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
-
-#
-# BPF subsystem
-#
-CONFIG_BPF_SYSCALL=y
-CONFIG_BPF_JIT=y
-CONFIG_BPF_JIT_ALWAYS_ON=y
-CONFIG_BPF_JIT_DEFAULT_ON=y
-# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
-# CONFIG_BPF_PRELOAD is not set
-# end of BPF subsystem
-
-CONFIG_PREEMPT_BUILD=y
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-CONFIG_PREEMPT_COUNT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_DYNAMIC=y
-CONFIG_SCHED_CORE=y
-
-#
-# CPU/Task time and stats accounting
-#
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_SCHED_AVG_IRQ=y
-CONFIG_BSD_PROCESS_ACCT=y
-# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_PSI=y
-# CONFIG_PSI_DEFAULT_DISABLED is not set
-# end of CPU/Task time and stats accounting
-
-CONFIG_CPU_ISOLATION=y
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-CONFIG_PREEMPT_RCU=y
-# CONFIG_RCU_EXPERT is not set
-CONFIG_SRCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TASKS_RCU_GENERIC=y
-CONFIG_TASKS_RCU=y
-CONFIG_TASKS_RUDE_RCU=y
-CONFIG_TASKS_TRACE_RCU=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RCU_NEED_SEGCBLIST=y
-# end of RCU Subsystem
-
-CONFIG_BUILD_BIN2C=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-# CONFIG_IKHEADERS is not set
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
-CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
-CONFIG_PRINTK_INDEX=y
-CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
-
-#
-# Scheduler features
-#
-# CONFIG_UCLAMP_TASK is not set
-# end of Scheduler features
-
-CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
-CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
-CONFIG_CC_HAS_INT128=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_ARCH_SUPPORTS_INT128=y
-CONFIG_NUMA_BALANCING=y
-CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
-CONFIG_CGROUPS=y
-CONFIG_PAGE_COUNTER=y
-CONFIG_MEMCG=y
-CONFIG_MEMCG_SWAP=y
-CONFIG_MEMCG_KMEM=y
-CONFIG_BLK_CGROUP=y
-CONFIG_CGROUP_WRITEBACK=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_CFS_BANDWIDTH=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_CGROUP_PIDS=y
-CONFIG_CGROUP_RDMA=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_HUGETLB=y
-CONFIG_CPUSETS=y
-CONFIG_PROC_PID_CPUSET=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_PERF=y
-CONFIG_CGROUP_BPF=y
-CONFIG_CGROUP_MISC=y
-# CONFIG_CGROUP_DEBUG is not set
-CONFIG_SOCK_CGROUP_DATA=y
-CONFIG_NAMESPACES=y
-CONFIG_UTS_NS=y
-CONFIG_TIME_NS=y
-CONFIG_IPC_NS=y
-CONFIG_USER_NS=y
-CONFIG_PID_NS=y
-CONFIG_NET_NS=y
-CONFIG_CHECKPOINT_RESTORE=y
-CONFIG_SCHED_AUTOGROUP=y
-# CONFIG_SYSFS_DEPRECATED is not set
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_XZ=y
-CONFIG_RD_LZO=y
-CONFIG_RD_LZ4=y
-CONFIG_RD_ZSTD=y
-CONFIG_BOOT_CONFIG=y
-# CONFIG_CC_OPTIMIZE_BASAL is not set
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
-CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_LD_ORPHAN_WARN=y
-CONFIG_SYSCTL=y
-CONFIG_HAVE_UID16=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_HAVE_PCSPKR_PLATFORM=y
-CONFIG_EXPERT=y
-CONFIG_UID16=y
-CONFIG_MULTIUSER=y
-CONFIG_SGETMASK_SYSCALL=y
-# CONFIG_SYSFS_SYSCALL is not set
-CONFIG_FHANDLE=y
-CONFIG_POSIX_TIMERS=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_PCSPKR_PLATFORM=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_FUTEX_PI=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_IO_URING=y
-CONFIG_ADVISE_SYSCALLS=y
-CONFIG_HAVE_ARCH_USERFAULTFD_WP=y
-CONFIG_LRU_GEN=y
-CONFIG_LRU_GEN_ENABLED=y
-# CONFIG_LRU_GEN_STATS is not set
-CONFIG_HAVE_ARCH_USERFAULTFD_MINOR=y
-CONFIG_MEMBARRIER=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y
-CONFIG_KALLSYMS_BASE_RELATIVE=y
-CONFIG_USERFAULTFD=y
-CONFIG_PTE_MARKER_UFFD_WP=y
-CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
-CONFIG_KCMP=y
-CONFIG_RSEQ=y
-# CONFIG_DEBUG_RSEQ is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_HAVE_PERF_EVENTS=y
-# CONFIG_PC104 is not set
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_PERF_EVENTS=y
-# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
-# end of Kernel Performance Events And Counters
-
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-CONFIG_SLAB_MERGE_DEFAULT=y
-CONFIG_SLAB_FREELIST_RANDOM=y
-CONFIG_SLAB_FREELIST_HARDENED=y
-CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
-CONFIG_SLUB_CPU_PARTIAL=y
-CONFIG_SYSTEM_DATA_VERIFICATION=y
-# CONFIG_PROFILING is not set
-CONFIG_TRACEPOINTS=y
-# end of General setup
-
-CONFIG_64BIT=y
-CONFIG_X86_64=y
-CONFIG_X86=y
-CONFIG_INSTRUCTION_DECODER=y
-CONFIG_OUTPUT_FORMAT="elf64-x86-64"
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_MMU=y
-CONFIG_ARCH_MMAP_RND_BITS_MIN=28
-CONFIG_ARCH_MMAP_RND_BITS_MAX=32
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_HAS_CPU_RELAX=y
-CONFIG_ARCH_HAS_FILTER_PGPROT=y
-CONFIG_HAVE_SETUP_PER_CPU_AREA=y
-CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
-CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_NR_GPIO=1024
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-# CONFIG_AUDIT_ARCH is not set
-CONFIG_X86_64_SMP=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_DYNAMIC_PHYSICAL_MASK=y
-CONFIG_PGTABLE_LEVELS=4
-CONFIG_CC_HAS_SANE_STACKPROTECTOR=y
-
-#
-# Processor type and features
-#
-CONFIG_SMP=y
-CONFIG_X86_FEATURE_NAMES=y
-CONFIG_X86_X2APIC=y
-CONFIG_X86_MPPARSE=y
-# CONFIG_GOLDFISH is not set
-CONFIG_RETPOLINE=y
-CONFIG_RETHUNK=y
-CONFIG_CPU_IBPB_ENTRY=y
-CONFIG_CPU_IBRS_ENTRY=y
-CONFIG_SLS=y
-CONFIG_X86_CPU_RESCTRL=y
-# CONFIG_X86_EXTENDED_PLATFORM is not set
-# CONFIG_X86_INTEL_LPSS is not set
-CONFIG_X86_AMD_PLATFORM_DEVICE=y
-CONFIG_IOSF_MBI=m
-# CONFIG_IOSF_MBI_DEBUG is not set
-CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
-CONFIG_SCHED_OMIT_FRAME_POINTER=y
-CONFIG_HYPERVISOR_GUEST=y
-CONFIG_PARAVIRT=y
-# CONFIG_PARAVIRT_DEBUG is not set
-# CONFIG_PARAVIRT_SPINLOCKS is not set
-CONFIG_X86_HV_CALLBACK_VECTOR=y
-# CONFIG_XEN is not set
-CONFIG_KVM_GUEST=y
-CONFIG_ARCH_CPUIDLE_HALTPOLL=y
-CONFIG_PVH=y
-# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
-CONFIG_PARAVIRT_CLOCK=y
-CONFIG_JAILHOUSE_GUEST=y
-# CONFIG_ACRN_GUEST is not set
-CONFIG_INTEL_TDX_GUEST=y
-# CONFIG_MK8 is not set
-# CONFIG_MK8SSE3 is not set
-# CONFIG_MK10 is not set
-# CONFIG_MBARCELONA is not set
-# CONFIG_MBOBCAT is not set
-# CONFIG_MJAGUAR is not set
-# CONFIG_MBULLDOZER is not set
-# CONFIG_MPILEDRIVER is not set
-# CONFIG_MSTEAMROLLER is not set
-# CONFIG_MEXCAVATOR is not set
-# CONFIG_MZEN is not set
-# CONFIG_MZEN2 is not set
-# CONFIG_MZEN3 is not set
-# CONFIG_MPSC is not set
-# CONFIG_MATOM is not set
-# CONFIG_MCORE2 is not set
-# CONFIG_MNEHALEM is not set
-# CONFIG_MWESTMERE is not set
-# CONFIG_MSILVERMONT is not set
-# CONFIG_MGOLDMONT is not set
-# CONFIG_MGOLDMONTPLUS is not set
-# CONFIG_MSANDYBRIDGE is not set
-# CONFIG_MIVYBRIDGE is not set
-# CONFIG_MHASWELL is not set
-# CONFIG_MBROADWELL is not set
-# CONFIG_MSKYLAKE is not set
-# CONFIG_MSKYLAKEX is not set
-# CONFIG_MCANNONLAKE is not set
-# CONFIG_MICELAKE is not set
-# CONFIG_MCASCADELAKE is not set
-# CONFIG_MCOOPERLAKE is not set
-# CONFIG_MTIGERLAKE is not set
-# CONFIG_MSAPPHIRERAPIDS is not set
-# CONFIG_MROCKETLAKE is not set
-# CONFIG_MALDERLAKE is not set
-# CONFIG_MNATIVE_INTEL is not set
-# CONFIG_MNATIVE_AMD is not set
-CONFIG_GENERIC_CPU=y
-# CONFIG_GENERIC_CPU2 is not set
-# CONFIG_GENERIC_CPU3 is not set
-# CONFIG_GENERIC_CPU4 is not set
-# CONFIG_MNATIVE is not set
-CONFIG_X86_INTERNODE_CACHE_SHIFT=6
-CONFIG_X86_L1_CACHE_SHIFT=6
-CONFIG_X86_TSC=y
-CONFIG_X86_CMPXCHG64=y
-CONFIG_X86_CMOV=y
-CONFIG_X86_MINIMUM_CPU_FAMILY=64
-CONFIG_X86_DEBUGCTLMSR=y
-CONFIG_PROCESSOR_SELECT=y
-CONFIG_CPU_SUP_INTEL=y
-CONFIG_CPU_SUP_AMD=y
-CONFIG_CPU_SUP_HYGON=y
-CONFIG_CPU_SUP_CENTAUR=y
-CONFIG_CPU_SUP_ZHAOXIN=y
-CONFIG_HPET_TIMER=y
-CONFIG_HPET_EMULATE_RTC=y
-CONFIG_DMI=y
-# CONFIG_GART_IOMMU is not set
-CONFIG_MAXSMP=y
-CONFIG_NR_CPUS_RANGE_BEGIN=8192
-CONFIG_NR_CPUS_RANGE_END=8192
-CONFIG_NR_CPUS_DEFAULT=8192
-CONFIG_NR_CPUS=8192
-CONFIG_SCHED_CLUSTER=y
-CONFIG_SCHED_SMT=y
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_MC_PRIO=y
-CONFIG_X86_LOCAL_APIC=y
-CONFIG_X86_IO_APIC=y
-CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
-CONFIG_X86_MCE=y
-# CONFIG_X86_MCELOG_LEGACY is not set
-# CONFIG_X86_MCE_INTEL is not set
-CONFIG_X86_MCE_AMD=y
-CONFIG_X86_MCE_THRESHOLD=y
-# CONFIG_X86_MCE_INJECT is not set
-CONFIG_PERF_EVENTS_INTEL_UNCORE=m
-
-#
-# Performance monitoring
-#
-CONFIG_PERF_EVENTS_INTEL_RAPL=m
-CONFIG_PERF_EVENTS_INTEL_CSTATE=m
-CONFIG_PERF_EVENTS_AMD_POWER=m
-CONFIG_PERF_EVENTS_AMD_UNCORE=m
-CONFIG_PERF_EVENTS_AMD_BRS=y
-# end of Performance monitoring
-
-CONFIG_X86_16BIT=y
-CONFIG_X86_ESPFIX64=y
-CONFIG_X86_VSYSCALL_EMULATION=y
-CONFIG_X86_IOPL_IOPERM=y
-# CONFIG_I8K is not set
-CONFIG_MICROCODE=y
-CONFIG_MICROCODE_INTEL=y
-CONFIG_MICROCODE_AMD=y
-# CONFIG_MICROCODE_LATE_LOADING is not set
-# CONFIG_MICROCODE_OLD_INTERFACE is not set
-CONFIG_X86_MSR=m
-CONFIG_X86_CPUID=m
-# CONFIG_X86_5LEVEL is not set
-CONFIG_X86_DIRECT_GBPAGES=y
-# CONFIG_X86_CPA_STATISTICS is not set
-CONFIG_AMD_MEM_ENCRYPT=y
-# CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT is not set
-CONFIG_NUMA=y
-# CONFIG_AMD_NUMA is not set
-CONFIG_X86_64_ACPI_NUMA=y
-# CONFIG_NUMA_EMU is not set
-CONFIG_NODES_SHIFT=10
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_MEMORY_PROBE=y
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_X86_PMEM_LEGACY_DEVICE=y
-CONFIG_X86_PMEM_LEGACY=m
-CONFIG_X86_CHECK_BIOS_CORRUPTION=y
-CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y
-CONFIG_MTRR=y
-CONFIG_MTRR_SANITIZER=y
-CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0
-CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
-CONFIG_X86_PAT=y
-CONFIG_ARCH_USES_PG_UNCACHED=y
-CONFIG_ARCH_RANDOM=y
-CONFIG_X86_SMAP=y
-CONFIG_X86_UMIP=y
-CONFIG_X86_KERNEL_IBT=y
-# CONFIG_X86_INTEL_TSX_MODE_OFF is not set
-# CONFIG_X86_INTEL_TSX_MODE_ON is not set
-CONFIG_X86_INTEL_TSX_MODE_AUTO=y
-# CONFIG_X86_SGX is not set
-CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y
-CONFIG_EFI=y
-CONFIG_EFI_STUB=y
-CONFIG_EFI_MIXED=y
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_250 is not set
-CONFIG_HZ_300=y
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=300
-CONFIG_ARCH_FORCE_MAX_ORDER=12
-CONFIG_SCHED_HRTICK=y
-CONFIG_KEXEC=y
-CONFIG_KEXEC_FILE=y
-CONFIG_ARCH_HAS_KEXEC_PURGATORY=y
-# CONFIG_KEXEC_SIG is not set
-# CONFIG_CRASH_DUMP is not set
-CONFIG_KEXEC_JUMP=y
-CONFIG_PHYSICAL_START=0x1000000
-CONFIG_RELOCATABLE=y
-CONFIG_RANDOMIZE_BASE=y
-CONFIG_X86_NEED_RELOCS=y
-CONFIG_PHYSICAL_ALIGN=0x1000000
-CONFIG_DYNAMIC_MEMORY_LAYOUT=y
-CONFIG_RANDOMIZE_MEMORY=y
-CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa
-CONFIG_HOTPLUG_CPU=y
-CONFIG_BOOTPARAM_HOTPLUG_CPU0=y
-# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
-# CONFIG_COMPAT_VDSO is not set
-# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
-# CONFIG_LEGACY_VSYSCALL_EMULATE is not set
-CONFIG_LEGACY_VSYSCALL_XONLY=y
-# CONFIG_LEGACY_VSYSCALL_NONE is not set
-# CONFIG_CMDLINE_BOOL is not set
-CONFIG_MODIFY_LDT_SYSCALL=y
-# CONFIG_STRICT_SIGALTSTACK_SIZE is not set
-CONFIG_HAVE_LIVEPATCH=y
-CONFIG_LIVEPATCH=y
-# end of Processor type and features
-
-CONFIG_ARCH_HAS_ADD_PAGES=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_USE_PERCPU_NUMA_NODE_ID=y
-
-#
-# Power management and ACPI options
-#
-CONFIG_ARCH_HIBERNATION_HEADER=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_SUSPEND_SKIP_SYNC is not set
-CONFIG_HIBERNATE_CALLBACKS=y
-CONFIG_HIBERNATION=y
-CONFIG_HIBERNATION_SNAPSHOT_DEV=y
-CONFIG_PM_STD_PARTITION=""
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_PM_AUTOSLEEP=y
-CONFIG_PM_WAKELOCKS=y
-CONFIG_PM_WAKELOCKS_LIMIT=100
-CONFIG_PM_WAKELOCKS_GC=y
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_ENERGY_MODEL=y
-CONFIG_ARCH_SUPPORTS_ACPI=y
-CONFIG_ACPI=y
-CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
-CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
-CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
-# CONFIG_ACPI_DEBUGGER is not set
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_FPDT=y
-CONFIG_ACPI_LPIT=y
-CONFIG_ACPI_SLEEP=y
-CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
-# CONFIG_ACPI_EC_DEBUGFS is not set
-CONFIG_ACPI_AC=m
-CONFIG_ACPI_BATTERY=m
-CONFIG_ACPI_BUTTON=m
-CONFIG_ACPI_VIDEO=m
-CONFIG_ACPI_TINY_POWER_BUTTON=m
-CONFIG_ACPI_TINY_POWER_BUTTON_SIGNAL=38
-CONFIG_ACPI_VIDEO=m
-CONFIG_ACPI_FAN=m
-CONFIG_ACPI_TAD=m
-CONFIG_ACPI_DOCK=y
-CONFIG_ACPI_CPU_FREQ_PSS=y
-CONFIG_ACPI_PROCESSOR_CSTATE=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
-CONFIG_ACPI_PROCESSOR=y
-CONFIG_ACPI_IPMI=m
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_PROCESSOR_AGGREGATOR=m
-CONFIG_ACPI_THERMAL=m
-CONFIG_ACPI_PLATFORM_PROFILE=m
-CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
-CONFIG_ACPI_TABLE_UPGRADE=y
-# CONFIG_ACPI_DEBUG is not set
-CONFIG_ACPI_PCI_SLOT=y
-CONFIG_ACPI_CONTAINER=y
-CONFIG_ACPI_HOTPLUG_MEMORY=y
-CONFIG_ACPI_HOTPLUG_IOAPIC=y
-CONFIG_ACPI_SBS=m
-CONFIG_ACPI_HED=y
-# CONFIG_ACPI_CUSTOM_METHOD is not set
-CONFIG_ACPI_BGRT=y
-# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
-CONFIG_ACPI_NFIT=m
-# CONFIG_NFIT_SECURITY_DEBUG is not set
-CONFIG_ACPI_NUMA=y
-CONFIG_ACPI_HMAT=y
-CONFIG_HAVE_ACPI_APEI=y
-CONFIG_HAVE_ACPI_APEI_NMI=y
-CONFIG_ACPI_APEI=y
-CONFIG_ACPI_APEI_GHES=y
-CONFIG_ACPI_APEI_PCIEAER=y
-CONFIG_ACPI_APEI_MEMORY_FAILURE=y
-# CONFIG_ACPI_APEI_EINJ is not set
-# CONFIG_ACPI_APEI_ERST_DEBUG is not set
-CONFIG_ACPI_DPTF=y
-CONFIG_DPTF_POWER=m
-CONFIG_DPTF_PCH_FIVR=m
-CONFIG_ACPI_WATCHDOG=y
-CONFIG_ACPI_EXTLOG=m
-CONFIG_ACPI_CONFIGFS=m
-CONFIG_ACPI_PFRUT=m
-CONFIG_ACPI_PCC=y
-CONFIG_ACPI_PRMT=y
-CONFIG_PMIC_OPREGION=y
-# CONFIG_BXT_WC_PMIC_OPREGION is not set
-CONFIG_CHT_DC_TI_PMIC_OPREGION=y
-CONFIG_TPS68470_PMIC_OPREGION=y
-CONFIG_ACPI_VIOT=y
-CONFIG_X86_PM_TIMER=y
-CONFIG_ACPI_PRMT=y
-CONFIG_INTEL_IDLE=y
-
-#
-# CPU Frequency scaling
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-
-#
-# CPU frequency scaling drivers
-#
-# CONFIG_X86_INTEL_PSTATE is not set
-CONFIG_X86_PCC_CPUFREQ=m
-CONFIG_X86_AMD_PSTATE=y
-CONFIG_X86_AMD_PSTATE_UT=m
-CONFIG_X86_ACPI_CPUFREQ=m
-CONFIG_X86_ACPI_CPUFREQ_CPB=y
-# CONFIG_X86_POWERNOW_K8 is not set
-CONFIG_X86_AMD_FREQ_SENSITIVITY=m
-# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
-# CONFIG_X86_P4_CLOCKMOD is not set
-
-#
-# shared options
-#
-# end of CPU Frequency scaling
-
-#
-# CPU Idle
-#
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-# CONFIG_CPU_IDLE_GOV_TEO is not set
-# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set
-CONFIG_HALTPOLL_CPUIDLE=y
-# end of CPU Idle
-# end of Power management and ACPI options
-
-#
-# Bus options (PCI etc.)
-#
-CONFIG_PCI_DIRECT=y
-CONFIG_PCI_MMCONFIG=y
-CONFIG_MMCONF_FAM10H=y
-# CONFIG_PCI_CNB20LE_QUIRK is not set
-# CONFIG_ISA_BUS is not set
-CONFIG_ISA_DMA_API=y
-CONFIG_AMD_NB=y
-# end of Bus options (PCI etc.)
-
-#
-# Binary Emulations
-#
-CONFIG_IA32_EMULATION=y
-CONFIG_X86_X32_ABI=y
-# CONFIG_X86_X32 is not set
-CONFIG_COMPAT_32=y
-CONFIG_COMPAT=y
-CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
-CONFIG_SYSVIPC_COMPAT=y
-# end of Binary Emulations
-
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_KVM_IRQCHIP=y
-CONFIG_HAVE_KVM_IRQFD=y
-CONFIG_HAVE_KVM_IRQ_ROUTING=y
-CONFIG_HAVE_KVM_EVENTFD=y
-CONFIG_KVM_MMIO=y
-CONFIG_KVM_ASYNC_PF=y
-CONFIG_HAVE_KVM_MSI=y
-CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
-CONFIG_KVM_VFIO=y
-CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
-CONFIG_KVM_COMPAT=y
-CONFIG_HAVE_KVM_IRQ_BYPASS=y
-CONFIG_HAVE_KVM_NO_POLL=y
-CONFIG_KVM_XFER_TO_GUEST_WORK=y
-CONFIG_HAVE_KVM_PM_NOTIFIER=y
-CONFIG_VIRTUALIZATION=y
-CONFIG_KVM=m
-CONFIG_KVM_WERROR=y
-CONFIG_KVM_INTEL=m
-CONFIG_KVM_AMD=m
-CONFIG_KVM_AMD_SEV=y
-CONFIG_KVM_XEN=y
-CONFIG_INTEL_POWERCLAMP=m
-CONFIG_X86_PKG_TEMP_THERMAL=m
-# CONFIG_KVM_MMU_AUDIT is not set
-CONFIG_AS_AVX512=y
-CONFIG_AS_SHA1_NI=y
-CONFIG_AS_SHA256_NI=y
-CONFIG_AS_TPAUSE=y
-
-#
-# General architecture-dependent options
-#
-CONFIG_CRASH_CORE=y
-CONFIG_KEXEC_CORE=y
-CONFIG_HOTPLUG_SMT=y
-CONFIG_GENERIC_ENTRY=y
-CONFIG_KPROBES=y
-CONFIG_JUMP_LABEL=y
-# CONFIG_STATIC_KEYS_SELFTEST is not set
-# CONFIG_STATIC_CALL_SELFTEST is not set
-CONFIG_OPTPROBES=y
-CONFIG_KPROBES_ON_FTRACE=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_KRETPROBES=y
-CONFIG_USER_RETURN_NOTIFIER=y
-CONFIG_HAVE_IOREMAP_PROT=y
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_KPROBES_ON_FTRACE=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
-CONFIG_HAVE_NMI=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
-CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
-CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_HAVE_ASM_MODVERSIONS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
-CONFIG_HAVE_USER_RETURN_NOTIFIER=y
-CONFIG_HAVE_PERF_EVENTS_NMI=y
-CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
-CONFIG_MMU_GATHER_TABLE_FREE=y
-CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
-CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
-CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
-CONFIG_HAVE_CMPXCHG_LOCAL=y
-CONFIG_HAVE_CMPXCHG_DOUBLE=y
-CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y
-CONFIG_HAVE_ARCH_SECCOMP=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_SECCOMP=y
-CONFIG_SECCOMP_FILTER=y
-# CONFIG_SECCOMP_CACHE_DEBUG is not set
-CONFIG_HAVE_ARCH_STACKLEAK=y
-CONFIG_HAVE_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR_STRONG=y
-CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
-CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
-CONFIG_LTO_NONE=y
-CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MOVE_PUD=y
-CONFIG_HAVE_MOVE_PMD=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y
-CONFIG_HAVE_ARCH_HUGE_VMAP=y
-CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
-CONFIG_HAVE_ARCH_SOFT_DIRTY=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
-CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
-CONFIG_HAVE_EXIT_THREAD=y
-CONFIG_ARCH_MMAP_RND_BITS=28
-CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8
-CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_HAVE_STACK_VALIDATION=y
-CONFIG_HAVE_RELIABLE_STACKTRACE=y
-CONFIG_ISA_BUS_API=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_COMPAT_OLD_SIGACTION=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_HAVE_ARCH_VMAP_STACK=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET=y
-CONFIG_VMAP_STACK=y
-CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
-CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_STRICT_MODULE_RWX=y
-CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
-CONFIG_ARCH_USE_MEMREMAP_PROT=y
-# CONFIG_LOCK_EVENT_COUNTS is not set
-CONFIG_ARCH_HAS_MEM_ENCRYPT=y
-CONFIG_ARCH_HAS_CC_PLATFORM=y
-CONFIG_HAVE_STATIC_CALL=y
-CONFIG_HAVE_STATIC_CALL_INLINE=y
-CONFIG_HAVE_PREEMPT_DYNAMIC=y
-CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
-# CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC is not set
-CONFIG_ARCH_HAS_ELFCORE_COMPAT=y
-CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y
-CONFIG_DYNAMIC_SIGFRAME=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-# end of GCOV-based kernel profiling
-
-CONFIG_HAVE_GCC_PLUGINS=y
-CONFIG_GCC_PLUGINS=y
-# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
-# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
-# end of General architecture-dependent options
-CONFIG_RANDSTRUCT_NONE=y
-# CONFIG_RANDSTRUCT_FULL is not set
-# CONFIG_RANDSTRUCT_PERFORMANCE is not set
-
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULE_SIG_FORMAT=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_ASM_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_MODULE_SIG=y
-# CONFIG_MODULE_SIG_FORCE is not set
-# CONFIG_MODULE_SIG_ALL is not set
-CONFIG_MODULE_SIG_SHA1=y
-# CONFIG_MODULE_SIG_SHA224 is not set
-# CONFIG_MODULE_SIG_SHA256 is not set
-# CONFIG_MODULE_SIG_SHA384 is not set
-# CONFIG_MODULE_SIG_SHA512 is not set
-CONFIG_MODULE_SIG_HASH="sha1"
-CONFIG_MODULE_COMPRESS_NONE=y
-# CONFIG_MODULE_COMPRESS_GZIP is not set
-# CONFIG_MODULE_COMPRESS_XZ is not set
-# CONFIG_MODULE_COMPRESS_ZSTD is not set
-# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
-CONFIG_MODPROBE_PATH="/sbin/modprobe"
-# CONFIG_TRIM_UNUSED_KSYMS is not set
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_BLOCK=y
-# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set
-CONFIG_BLK_CGROUP_RWSTAT=y
-CONFIG_BLK_DEV_BSG_COMMON=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=m
-CONFIG_BLK_DEV_ZONED=y
-CONFIG_BLK_DEV_THROTTLING=y
-# CONFIG_BLK_DEV_THROTTLING_LOW is not set
-CONFIG_BLK_WBT=y
-CONFIG_BLK_WBT_MQ=y
-CONFIG_BLK_CGROUP_IOLATENCY=y
-# CONFIG_BLK_CGROUP_FC_APPID is not set
-# CONFIG_BLK_CGROUP_IOCOST is not set
-# CONFIG_BLK_CGROUP_IOPRIO is not set
-# CONFIG_BLK_DEBUG_FS is not set
-# CONFIG_BLK_SED_OPAL is not set
-# CONFIG_BLK_INLINE_ENCRYPTION is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_ACORN_PARTITION=y
-CONFIG_ACORN_PARTITION_CUMANA=y
-CONFIG_ACORN_PARTITION_EESOX=y
-CONFIG_ACORN_PARTITION_ICS=y
-CONFIG_ACORN_PARTITION_ADFS=y
-CONFIG_ACORN_PARTITION_POWERTEC=y
-CONFIG_ACORN_PARTITION_RISCIX=y
-CONFIG_AIX_PARTITION=y
-CONFIG_OSF_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_ATARI_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_MSDOS_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_LDM_DEBUG=y
-CONFIG_SGI_PARTITION=y
-CONFIG_ULTRIX_PARTITION=y
-CONFIG_SUN_PARTITION=y
-CONFIG_KARMA_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_SYSV68_PARTITION=y
-CONFIG_CMDLINE_PARTITION=y
-# end of Partition Types
-
-CONFIG_BLOCK_COMPAT=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_MQ_RDMA=y
-CONFIG_BLK_PM=y
-CONFIG_BLOCK_HOLDER_DEPRECATED=y
-
-#
-# IO Schedulers
-#
-CONFIG_MQ_IOSCHED_DEADLINE=y
-CONFIG_MQ_IOSCHED_KYBER=m
-CONFIG_IOSCHED_BFQ=y
-CONFIG_BFQ_GROUP_IOSCHED=y
-# CONFIG_BFQ_CGROUP_DEBUG is not set
-# end of IO Schedulers
-
-CONFIG_PREEMPT_NOTIFIERS=y
-CONFIG_PADATA=y
-CONFIG_ASN1=y
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
-CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y
-CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
-CONFIG_FREEZER=y
-
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_COMPAT_BINFMT_ELF=y
-CONFIG_ELFCORE=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_BINFMT_SCRIPT=y
-CONFIG_BINFMT_MISC=m
-CONFIG_COREDUMP=y
-# end of Executable file formats
-
-#
-# Memory Management options
-#
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_HAVE_FAST_GUP=y
-CONFIG_NUMA_KEEP_MEMINFO=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_HAVE_BOOTMEM_INFO_NODE=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_MEMORY_HOTPLUG=y
-# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set
-CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-CONFIG_MEMORY_HOTREMOVE=y
-CONFIG_MHP_MEMMAP_ON_MEMORY=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
-CONFIG_MEMORY_BALLOON=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_COMPACTION=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_MIGRATION=y
-CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
-CONFIG_ARCH_ENABLE_THP_MIGRATION=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_VIRT_TO_BUS=y
-CONFIG_MMU_NOTIFIER=y
-CONFIG_KSM=y
-CONFIG_UKSM=y
-# CONFIG_KSM_LEGACY is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
-CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
-CONFIG_MEMORY_FAILURE=y
-# CONFIG_HWPOISON_INJECT is not set
-CONFIG_TRANSPARENT_HUGEPAGE=y
-CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
-# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_THP_SWAP=y
-CONFIG_CLEANCACHE=y
-CONFIG_FRONTSWAP=y
-CONFIG_CMA=y
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SYSFS=y
-CONFIG_CMA_AREAS=7
-# CONFIG_MEM_SOFT_DIRTY is not set
-CONFIG_ZSWAP=y
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set
-# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y
-CONFIG_ZSWAP_COMPRESSOR_DEFAULT="zstd"
-CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set
-# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set
-CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud"
-# CONFIG_ZSWAP_DEFAULT_ON is not set
-CONFIG_ZPOOL=y
-CONFIG_ZBUD=y
-CONFIG_Z3FOLD=m
-CONFIG_ZSMALLOC=y
-# CONFIG_ZSMALLOC_STAT is not set
-CONFIG_GENERIC_EARLY_IOREMAP=y
-# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
-CONFIG_PAGE_IDLE_FLAG=y
-# CONFIG_IDLE_PAGE_TRACKING is not set
-CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
-CONFIG_ARCH_HAS_PTE_DEVMAP=y
-CONFIG_ARCH_HAS_ZONE_DMA_SET=y
-CONFIG_ZONE_DMA=y
-CONFIG_ZONE_DMA32=y
-# CONFIG_ZONE_DEVICE is not set
-CONFIG_HMM_MIRROR=y
-CONFIG_VMAP_PFN=y
-CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
-CONFIG_ARCH_HAS_PKEYS=y
-# CONFIG_PERCPU_STATS is not set
-# CONFIG_GUP_TEST is not set
-# CONFIG_READ_ONLY_THP_FOR_FS is not set
-CONFIG_ARCH_HAS_PTE_SPECIAL=y
-CONFIG_MAPPING_DIRTY_HELPERS=y
-CONFIG_SECRETMEM=y
-
-#
-# Data Access Monitoring
-#
-CONFIG_DAMON=y
-CONFIG_DAMON_SYSFS=y
-CONFIG_DAMON_VADDR=y
-CONFIG_DAMON_PADDR=y
-CONFIG_DAMON_DBGFS=y
-CONFIG_DAMON_RECLAIM=y
-# end of Data Access Monitoring
-# end of Memory Management options
-
-CONFIG_NET=y
-CONFIG_WANT_COMPAT_NETLINK_MESSAGES=y
-CONFIG_COMPAT_NETLINK_MESSAGES=y
-CONFIG_NET_INGRESS=y
-CONFIG_NET_EGRESS=y
-CONFIG_NET_REDIRECT=y
-CONFIG_SKB_EXTENSIONS=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=m
-CONFIG_PACKET_DIAG=m
-CONFIG_UNIX=y
-CONFIG_UNIX_SCM=y
-CONFIG_AF_UNIX_OOB=y
-CONFIG_UNIX_DIAG=m
-CONFIG_TLS=m
-# CONFIG_TLS_DEVICE is not set
-# CONFIG_TLS_TOE is not set
-CONFIG_XFRM=y
-CONFIG_XFRM_OFFLOAD=y
-CONFIG_XFRM_ALGO=m
-CONFIG_XFRM_USER=m
-CONFIG_XFRM_USER_COMPAT=m
-CONFIG_XFRM_INTERFACE=m
-CONFIG_XFRM_SUB_POLICY=y
-CONFIG_XFRM_MIGRATE=y
-CONFIG_XFRM_STATISTICS=y
-CONFIG_XFRM_AH=m
-CONFIG_XFRM_ESP=m
-CONFIG_XFRM_IPCOMP=m
-CONFIG_NET_KEY=m
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_XFRM_ESPINTCP=y
-CONFIG_SMC=m
-CONFIG_SMC_DIAG=m
-CONFIG_XDP_SOCKETS=y
-CONFIG_XDP_SOCKETS_DIAG=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_FIB_TRIE_STATS=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-# CONFIG_IP_ROUTE_VERBOSE is not set
-CONFIG_IP_ROUTE_CLASSID=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE_DEMUX=m
-CONFIG_NET_IP_TUNNEL=m
-CONFIG_NET_IPGRE=m
-CONFIG_NET_IPGRE_BROADCAST=y
-CONFIG_IP_MROUTE_COMMON=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_NET_IPVTI=m
-CONFIG_NET_UDP_TUNNEL=m
-CONFIG_NET_FOU=m
-CONFIG_NET_FOU_IP_TUNNELS=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_ESP_OFFLOAD=m
-CONFIG_INET_ESPINTCP=y
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_TABLE_PERTURB_ORDER=16
-CONFIG_INET_XFRM_TUNNEL=m
-CONFIG_INET_TUNNEL=m
-CONFIG_INET_DIAG=m
-CONFIG_INET_TCP_DIAG=m
-CONFIG_INET_UDP_DIAG=m
-CONFIG_INET_RAW_DIAG=m
-CONFIG_INET_DIAG_DESTROY=y
-CONFIG_TCP_CONG_ADVANCED=y
-CONFIG_TCP_CONG_BIC=m
-CONFIG_TCP_CONG_CUBIC=m
-CONFIG_TCP_CONG_WESTWOOD=m
-CONFIG_TCP_CONG_HTCP=m
-CONFIG_TCP_CONG_HSTCP=m
-CONFIG_TCP_CONG_HYBLA=m
-CONFIG_TCP_CONG_VEGAS=m
-CONFIG_TCP_CONG_NV=m
-CONFIG_TCP_CONG_SCALABLE=m
-CONFIG_TCP_CONG_LP=m
-CONFIG_TCP_CONG_VENO=m
-CONFIG_TCP_CONG_YEAH=m
-CONFIG_TCP_CONG_ILLINOIS=m
-CONFIG_TCP_CONG_DCTCP=m
-# CONFIG_TCP_CONG_CDG is not set
-CONFIG_TCP_CONG_BBR=m
-CONFIG_DEFAULT_RENO=y
-CONFIG_DEFAULT_TCP_CONG="reno"
-CONFIG_TCP_MD5SIG=y
-CONFIG_IPV6=m
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_ESP_OFFLOAD=m
-# CONFIG_INET6_ESPINTCP is not set
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_IPV6_ILA=m
-CONFIG_INET6_XFRM_TUNNEL=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_IPV6_VTI=m
-CONFIG_IPV6_SIT=m
-CONFIG_IPV6_SIT_6RD=y
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_GRE=m
-CONFIG_IPV6_FOU=m
-CONFIG_IPV6_FOU_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-CONFIG_IPV6_MROUTE=y
-CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-CONFIG_IPV6_PIMSM_V2=y
-CONFIG_IPV6_SEG6_LWTUNNEL=y
-CONFIG_IPV6_SEG6_HMAC=y
-CONFIG_IPV6_RPL_LWTUNNEL=y
-CONFIG_IPV6_IOAM6_LWTUNNEL=y
-CONFIG_MPTCP=y
-CONFIG_INET_MPTCP_DIAG=m
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NETWORK_PHY_TIMESTAMPING=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_ADVANCED=y
-CONFIG_BRIDGE_NETFILTER=m
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_INGRESS=y
-CONFIG_NETFILTER_EGRESS=y
-CONFIG_NETFILTER_SKIP_EGRESS=y
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_FAMILY_BRIDGE=y
-CONFIG_NETFILTER_FAMILY_ARP=y
-CONFIG_NETFILTER_NETLINK_HOOK=m
-CONFIG_NETFILTER_NETLINK_ACCT=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NETFILTER_NETLINK_OSF=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_LOG_SYSLOG=m
-CONFIG_NETFILTER_CONNCOUNT=m
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_ZONES=y
-CONFIG_NF_CONNTRACK_PROCFS=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CONNTRACK_TIMEOUT=y
-CONFIG_NF_CONNTRACK_TIMESTAMP=y
-CONFIG_NF_CONNTRACK_LABELS=y
-CONFIG_NF_CT_PROTO_DCCP=y
-CONFIG_NF_CT_PROTO_GRE=y
-CONFIG_NF_CT_PROTO_SCTP=y
-CONFIG_NF_CT_PROTO_UDPLITE=y
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_BROADCAST=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_SNMP=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NF_CT_NETLINK_TIMEOUT=m
-CONFIG_NF_CT_NETLINK_HELPER=m
-CONFIG_NETFILTER_NETLINK_GLUE_CT=y
-CONFIG_NF_NAT=m
-CONFIG_NF_NAT_AMANDA=m
-CONFIG_NF_NAT_FTP=m
-CONFIG_NF_NAT_IRC=m
-CONFIG_NF_NAT_SIP=m
-CONFIG_NF_NAT_TFTP=m
-CONFIG_NF_NAT_REDIRECT=y
-CONFIG_NF_NAT_MASQUERADE=y
-CONFIG_NETFILTER_SYNPROXY=m
-CONFIG_NF_TABLES=m
-CONFIG_NF_TABLES_INET=y
-CONFIG_NF_TABLES_NETDEV=y
-CONFIG_NFT_NUMGEN=m
-CONFIG_NFT_CT=m
-CONFIG_NFT_FLOW_OFFLOAD=m
-CONFIG_NFT_COUNTER=m
-CONFIG_NFT_CONNLIMIT=m
-CONFIG_NFT_LOG=m
-CONFIG_NFT_LIMIT=m
-CONFIG_NFT_MASQ=m
-CONFIG_NFT_REDIR=m
-CONFIG_NFT_NAT=m
-CONFIG_NFT_TUNNEL=m
-CONFIG_NFT_OBJREF=m
-CONFIG_NFT_QUEUE=m
-CONFIG_NFT_QUOTA=m
-CONFIG_NFT_REJECT=m
-CONFIG_NFT_REJECT_INET=m
-CONFIG_NFT_COMPAT=m
-CONFIG_NFT_HASH=m
-CONFIG_NFT_FIB=m
-CONFIG_NFT_FIB_INET=m
-CONFIG_NFT_XFRM=m
-CONFIG_NFT_SOCKET=m
-CONFIG_NFT_OSF=m
-CONFIG_NFT_TPROXY=m
-CONFIG_NFT_SYNPROXY=m
-CONFIG_NF_DUP_NETDEV=m
-CONFIG_NFT_DUP_NETDEV=m
-CONFIG_NFT_FWD_NETDEV=m
-CONFIG_NFT_FIB_NETDEV=m
-CONFIG_NFT_REJECT_NETDEV=m
-CONFIG_NF_FLOW_TABLE_INET=m
-CONFIG_NF_FLOW_TABLE=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XTABLES_COMPAT=y
-
-#
-# Xtables combined modules
-#
-CONFIG_NETFILTER_XT_MARK=m
-CONFIG_NETFILTER_XT_CONNMARK=m
-CONFIG_NETFILTER_XT_SET=m
-
-#
-# Xtables targets
-#
-CONFIG_NETFILTER_XT_TARGET_AUDIT=m
-CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CT=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_HL=m
-CONFIG_NETFILTER_XT_TARGET_HMARK=m
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
-CONFIG_NETFILTER_XT_TARGET_LOG=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_NAT=m
-CONFIG_NETFILTER_XT_TARGET_NETMAP=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-CONFIG_NETFILTER_XT_TARGET_RATEEST=m
-CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
-CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m
-CONFIG_NETFILTER_XT_TARGET_TEE=m
-CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-CONFIG_NETFILTER_XT_TARGET_TRACE=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-
-#
-# Xtables matches
-#
-CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
-CONFIG_NETFILTER_XT_MATCH_BPF=m
-CONFIG_NETFILTER_XT_MATCH_CGROUP=m
-CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_CPU=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ECN=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_HL=m
-CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_IPVS=m
-CONFIG_NETFILTER_XT_MATCH_L2TP=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-CONFIG_NETFILTER_XT_MATCH_OSF=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-# end of Core Netfilter Configuration
-
-CONFIG_IP_SET=m
-CONFIG_IP_SET_MAX=256
-CONFIG_IP_SET_BITMAP_IP=m
-CONFIG_IP_SET_BITMAP_IPMAC=m
-CONFIG_IP_SET_BITMAP_PORT=m
-CONFIG_IP_SET_HASH_IP=m
-CONFIG_IP_SET_HASH_IPMARK=m
-CONFIG_IP_SET_HASH_IPPORT=m
-CONFIG_IP_SET_HASH_IPPORTIP=m
-CONFIG_IP_SET_HASH_IPPORTNET=m
-CONFIG_IP_SET_HASH_IPMAC=m
-CONFIG_IP_SET_HASH_MAC=m
-CONFIG_IP_SET_HASH_NETPORTNET=m
-CONFIG_IP_SET_HASH_NET=m
-CONFIG_IP_SET_HASH_NETNET=m
-CONFIG_IP_SET_HASH_NETPORT=m
-CONFIG_IP_SET_HASH_NETIFACE=m
-CONFIG_IP_SET_LIST_SET=m
-CONFIG_IP_VS=m
-CONFIG_IP_VS_IPV6=y
-# CONFIG_IP_VS_DEBUG is not set
-CONFIG_IP_VS_TAB_BITS=12
-
-#
-# IPVS transport protocol load balancing support
-#
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_AH_ESP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_PROTO_SCTP=y
-
-#
-# IPVS scheduler
-#
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_FO=m
-CONFIG_IP_VS_OVF=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_MH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_TWOS=m
-
-#
-# IPVS SH scheduler
-#
-CONFIG_IP_VS_SH_TAB_BITS=8
-
-#
-# IPVS MH scheduler
-#
-CONFIG_IP_VS_MH_TAB_INDEX=12
-
-#
-# IPVS application helper
-#
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_VS_NFCT=y
-CONFIG_IP_VS_PE_SIP=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_DEFRAG_IPV4=m
-CONFIG_NF_SOCKET_IPV4=m
-CONFIG_NF_TPROXY_IPV4=m
-CONFIG_NF_TABLES_IPV4=y
-CONFIG_NFT_REJECT_IPV4=m
-CONFIG_NFT_DUP_IPV4=m
-CONFIG_NFT_FIB_IPV4=m
-CONFIG_NF_TABLES_ARP=y
-CONFIG_NF_FLOW_TABLE_IPV4=m
-CONFIG_NF_DUP_IPV4=m
-CONFIG_NF_LOG_ARP=m
-CONFIG_NF_LOG_IPV4=m
-CONFIG_NF_REJECT_IPV4=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_NF_NAT_PPTP=m
-CONFIG_NF_NAT_H323=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_RPFILTER=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_SYNPROXY=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-# end of IP: Netfilter Configuration
-
-#
-# IPv6: Netfilter Configuration
-#
-CONFIG_NF_SOCKET_IPV6=m
-CONFIG_NF_TPROXY_IPV6=m
-CONFIG_NF_TABLES_IPV6=y
-CONFIG_NFT_REJECT_IPV6=m
-CONFIG_NFT_DUP_IPV6=m
-CONFIG_NFT_FIB_IPV6=m
-CONFIG_NF_FLOW_TABLE_IPV6=m
-CONFIG_NF_DUP_IPV6=m
-CONFIG_NF_REJECT_IPV6=m
-CONFIG_NF_LOG_IPV6=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RPFILTER=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_MATCH_SRH=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_TARGET_SYNPROXY=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_IP6_NF_NAT=m
-CONFIG_IP6_NF_TARGET_MASQUERADE=m
-CONFIG_IP6_NF_TARGET_NPT=m
-# end of IPv6: Netfilter Configuration
-
-CONFIG_NF_DEFRAG_IPV6=m
-
-#
-# DECnet: Netfilter Configuration
-#
-CONFIG_DECNET_NF_GRABULATOR=m
-# end of DECnet: Netfilter Configuration
-
-CONFIG_NF_TABLES_BRIDGE=m
-CONFIG_NFT_BRIDGE_META=m
-CONFIG_NFT_BRIDGE_REJECT=m
-CONFIG_NF_CONNTRACK_BRIDGE=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_IP6=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_BRIDGE_EBT_NFLOG=m
-# CONFIG_BPFILTER is not set
-CONFIG_IP_DCCP=m
-CONFIG_INET_DCCP_DIAG=m
-
-#
-# DCCP CCIDs Configuration
-#
-# CONFIG_IP_DCCP_CCID2_DEBUG is not set
-CONFIG_IP_DCCP_CCID3=y
-# CONFIG_IP_DCCP_CCID3_DEBUG is not set
-CONFIG_IP_DCCP_TFRC_LIB=y
-# end of DCCP CCIDs Configuration
-
-#
-# DCCP Kernel Hacking
-#
-# CONFIG_IP_DCCP_DEBUG is not set
-# end of DCCP Kernel Hacking
-
-CONFIG_IP_SCTP=m
-# CONFIG_SCTP_DBG_OBJCNT is not set
-CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
-# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
-CONFIG_SCTP_COOKIE_HMAC_MD5=y
-CONFIG_SCTP_COOKIE_HMAC_SHA1=y
-CONFIG_INET_SCTP_DIAG=m
-CONFIG_RDS=m
-CONFIG_RDS_RDMA=m
-CONFIG_RDS_TCP=m
-# CONFIG_RDS_DEBUG is not set
-CONFIG_TIPC=m
-CONFIG_TIPC_MEDIA_IB=y
-CONFIG_TIPC_MEDIA_UDP=y
-CONFIG_TIPC_CRYPTO=y
-CONFIG_TIPC_DIAG=m
-CONFIG_ATM=m
-CONFIG_ATM_CLIP=m
-# CONFIG_ATM_CLIP_NO_ICMP is not set
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-# CONFIG_ATM_BR2684_IPFILTER is not set
-CONFIG_L2TP=m
-# CONFIG_L2TP_DEBUGFS is not set
-CONFIG_L2TP_V3=y
-CONFIG_L2TP_IP=m
-CONFIG_L2TP_ETH=m
-CONFIG_STP=m
-CONFIG_GARP=m
-CONFIG_MRP=m
-CONFIG_BRIDGE=m
-CONFIG_BRIDGE_IGMP_SNOOPING=y
-CONFIG_BRIDGE_VLAN_FILTERING=y
-# CONFIG_BRIDGE_MRP is not set
-# CONFIG_BRIDGE_CFM is not set
-CONFIG_NET_DSA=m
-CONFIG_NET_DSA_TAG_AR9331=m
-CONFIG_NET_DSA_TAG_BRCM_COMMON=m
-CONFIG_NET_DSA_TAG_BRCM=m
-CONFIG_NET_DSA_TAG_BRCM_LEGACY=m
-CONFIG_NET_DSA_TAG_BRCM_PREPEND=m
-CONFIG_NET_DSA_TAG_HELLCREEK=m
-CONFIG_NET_DSA_TAG_GSWIP=m
-CONFIG_NET_DSA_TAG_DSA_COMMON=m
-CONFIG_NET_DSA_TAG_DSA=m
-CONFIG_NET_DSA_TAG_EDSA=m
-CONFIG_NET_DSA_TAG_MTK=m
-CONFIG_NET_DSA_TAG_KSZ=m
-CONFIG_NET_DSA_TAG_OCELOT=m
-CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
-CONFIG_NET_DSA_TAG_QCA=m
-CONFIG_NET_DSA_TAG_RTL4_A=m
-CONFIG_NET_DSA_TAG_RTL8_4=m
-CONFIG_NET_DSA_TAG_LAN9303=m
-CONFIG_NET_DSA_TAG_SJA1105=m
-CONFIG_NET_DSA_TAG_TRAILER=m
-CONFIG_NET_DSA_TAG_XRS700X=m
-CONFIG_NET_DSA_REALTEK=m
-CONFIG_NET_DSA_REALTEK_MDIO=m
-CONFIG_NET_DSA_REALTEK_RTL8365MB=m
-CONFIG_NET_DSA_REALTEK_RTL8366RB=m
-CONFIG_VLAN_8021Q=m
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_VLAN_8021Q_MVRP=y
-CONFIG_DECNET=m
-CONFIG_DECNET_ROUTER=y
-CONFIG_LLC=m
-CONFIG_LLC2=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_PHONET=m
-CONFIG_6LOWPAN=m
-# CONFIG_6LOWPAN_DEBUGFS is not set
-CONFIG_6LOWPAN_NHC=m
-CONFIG_6LOWPAN_NHC_DEST=m
-CONFIG_6LOWPAN_NHC_FRAGMENT=m
-CONFIG_6LOWPAN_NHC_HOP=m
-CONFIG_6LOWPAN_NHC_IPV6=m
-CONFIG_6LOWPAN_NHC_MOBILITY=m
-CONFIG_6LOWPAN_NHC_ROUTING=m
-CONFIG_6LOWPAN_NHC_UDP=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m
-CONFIG_6LOWPAN_GHC_UDP=m
-CONFIG_6LOWPAN_GHC_ICMPV6=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m
-CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m
-CONFIG_IEEE802154=m
-CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y
-CONFIG_IEEE802154_SOCKET=m
-CONFIG_IEEE802154_6LOWPAN=m
-CONFIG_MAC802154=m
-CONFIG_NET_SCHED=y
-
-#
-# Queueing/Scheduling
-#
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_MULTIQ=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFB=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_CBS=m
-CONFIG_NET_SCH_ETF=m
-CONFIG_NET_SCH_TAPRIO=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_DRR=m
-CONFIG_NET_SCH_MQPRIO=m
-CONFIG_NET_SCH_SKBPRIO=m
-CONFIG_NET_SCH_CHOKE=m
-CONFIG_NET_SCH_QFQ=m
-CONFIG_NET_SCH_CODEL=m
-CONFIG_NET_SCH_FQ_CODEL=y
-CONFIG_NET_SCH_CAKE=m
-CONFIG_NET_SCH_FQ=m
-CONFIG_NET_SCH_HHF=m
-CONFIG_NET_SCH_PIE=m
-CONFIG_NET_SCH_FQ_PIE=m
-CONFIG_NET_SCH_INGRESS=m
-CONFIG_NET_SCH_PLUG=m
-CONFIG_NET_SCH_ETS=m
-# CONFIG_NET_SCH_DEFAULT is not set
-
-#
-# Classification
-#
-CONFIG_NET_CLS=y
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_CLS_U32_PERF=y
-CONFIG_CLS_U32_MARK=y
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_CLS_FLOW=m
-CONFIG_NET_CLS_CGROUP=m
-CONFIG_NET_CLS_BPF=m
-CONFIG_NET_CLS_FLOWER=m
-CONFIG_NET_CLS_MATCHALL=m
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_STACK=32
-CONFIG_NET_EMATCH_CMP=m
-CONFIG_NET_EMATCH_NBYTE=m
-CONFIG_NET_EMATCH_U32=m
-CONFIG_NET_EMATCH_META=m
-CONFIG_NET_EMATCH_TEXT=m
-CONFIG_NET_EMATCH_CANID=m
-CONFIG_NET_EMATCH_IPSET=m
-CONFIG_NET_EMATCH_IPT=m
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=m
-CONFIG_NET_ACT_GACT=m
-CONFIG_GACT_PROB=y
-CONFIG_NET_ACT_MIRRED=m
-CONFIG_NET_ACT_SAMPLE=m
-CONFIG_NET_ACT_IPT=m
-CONFIG_NET_ACT_NAT=m
-CONFIG_NET_ACT_PEDIT=m
-# CONFIG_NET_ACT_SIMP is not set
-CONFIG_NET_ACT_SKBEDIT=m
-CONFIG_NET_ACT_CSUM=m
-CONFIG_NET_ACT_MPLS=m
-CONFIG_NET_ACT_VLAN=m
-CONFIG_NET_ACT_BPF=m
-CONFIG_NET_ACT_CONNMARK=m
-CONFIG_NET_ACT_CTINFO=m
-CONFIG_NET_ACT_SKBMOD=m
-CONFIG_NET_ACT_IFE=m
-CONFIG_NET_ACT_TUNNEL_KEY=m
-CONFIG_NET_ACT_CT=m
-CONFIG_NET_ACT_GATE=m
-CONFIG_NET_IFE_SKBMARK=m
-CONFIG_NET_IFE_SKBPRIO=m
-CONFIG_NET_IFE_SKBTCINDEX=m
-# CONFIG_NET_TC_SKB_EXT is not set
-CONFIG_NET_SCH_FIFO=y
-CONFIG_DCB=y
-CONFIG_DNS_RESOLVER=y
-CONFIG_BATMAN_ADV=m
-# CONFIG_BATMAN_ADV_BATMAN_V is not set
-CONFIG_BATMAN_ADV_BLA=y
-CONFIG_BATMAN_ADV_DAT=y
-CONFIG_BATMAN_ADV_NC=y
-CONFIG_BATMAN_ADV_MCAST=y
-# CONFIG_BATMAN_ADV_DEBUG is not set
-# CONFIG_BATMAN_ADV_TRACING is not set
-CONFIG_OPENVSWITCH=m
-CONFIG_OPENVSWITCH_GRE=m
-CONFIG_OPENVSWITCH_VXLAN=m
-CONFIG_OPENVSWITCH_GENEVE=m
-CONFIG_VSOCKETS=m
-CONFIG_VSOCKETS_DIAG=m
-CONFIG_VSOCKETS_LOOPBACK=m
-CONFIG_VMWARE_VMCI_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS=m
-CONFIG_VIRTIO_VSOCKETS_COMMON=m
-CONFIG_HYPERV_VSOCKETS=m
-CONFIG_NETLINK_DIAG=m
-CONFIG_MPLS=y
-CONFIG_NET_MPLS_GSO=m
-CONFIG_MPLS_ROUTING=m
-CONFIG_MPLS_IPTUNNEL=m
-CONFIG_NET_NSH=m
-CONFIG_HSR=m
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_L3_MASTER_DEV=y
-CONFIG_QRTR=m
-CONFIG_QRTR_SMD=m
-CONFIG_QRTR_TUN=m
-CONFIG_QRTR_MHI=m
-# CONFIG_NET_NCSI is not set
-CONFIG_PCPU_DEV_REFCNT=y
-CONFIG_RPS=y
-CONFIG_RFS_ACCEL=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_XPS=y
-CONFIG_CGROUP_NET_PRIO=y
-CONFIG_CGROUP_NET_CLASSID=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_BQL=y
-CONFIG_BPF_STREAM_PARSER=y
-CONFIG_NET_FLOW_LIMIT=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NET_DROP_MONITOR is not set
-# end of Network testing
-# end of Networking options
-
-CONFIG_HAMRADIO=y
-
-#
-# Packet Radio protocols
-#
-CONFIG_AX25=m
-CONFIG_AX25_DAMA_SLAVE=y
-CONFIG_NETROM=m
-CONFIG_ROSE=m
-
-#
-# AX.25 network device drivers
-#
-CONFIG_MKISS=m
-CONFIG_6PACK=m
-CONFIG_BPQETHER=m
-CONFIG_BAYCOM_SER_FDX=m
-CONFIG_BAYCOM_SER_HDX=m
-CONFIG_BAYCOM_PAR=m
-CONFIG_YAM=m
-# end of AX.25 network device drivers
-
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_GW=m
-CONFIG_CAN_J1939=m
-CONFIG_CAN_ISOTP=m
-
-#
-# CAN Device Drivers
-#
-CONFIG_CAN_VCAN=m
-CONFIG_CAN_VXCAN=m
-CONFIG_CAN_SLCAN=m
-CONFIG_CAN_DEV=m
-CONFIG_CAN_CALC_BITTIMING=y
-CONFIG_CAN_JANZ_ICAN3=m
-CONFIG_CAN_KVASER_PCIEFD=m
-CONFIG_CAN_C_CAN=m
-CONFIG_CAN_C_CAN_PLATFORM=m
-CONFIG_CAN_C_CAN_PCI=m
-CONFIG_CAN_CC770=m
-CONFIG_CAN_CC770_ISA=m
-CONFIG_CAN_CC770_PLATFORM=m
-CONFIG_CAN_IFI_CANFD=m
-CONFIG_CAN_M_CAN=m
-CONFIG_CAN_M_CAN_PCI=m
-CONFIG_CAN_M_CAN_PLATFORM=m
-CONFIG_CAN_M_CAN_TCAN4X5X=m
-CONFIG_CAN_PEAK_PCIEFD=m
-CONFIG_CAN_SJA1000=m
-CONFIG_CAN_EMS_PCI=m
-CONFIG_CAN_EMS_PCMCIA=m
-CONFIG_CAN_F81601=m
-CONFIG_CAN_KVASER_PCI=m
-CONFIG_CAN_PEAK_PCI=m
-CONFIG_CAN_PEAK_PCIEC=y
-CONFIG_CAN_PEAK_PCMCIA=m
-CONFIG_CAN_PLX_PCI=m
-CONFIG_CAN_SJA1000_ISA=m
-CONFIG_CAN_SJA1000_PLATFORM=m
-CONFIG_CAN_SOFTING=m
-CONFIG_CAN_SOFTING_CS=m
-
-#
-# CAN SPI interfaces
-#
-CONFIG_CAN_HI311X=m
-CONFIG_CAN_MCP251X=m
-CONFIG_CAN_MCP251XFD=m
-# CONFIG_CAN_MCP251XFD_SANITY is not set
-# end of CAN SPI interfaces
-
-#
-# CAN USB interfaces
-#
-CONFIG_CAN_8DEV_USB=m
-CONFIG_CAN_EMS_USB=m
-CONFIG_CAN_ESD_USB2=m
-CONFIG_CAN_ETAS_ES58X=m
-CONFIG_CAN_GS_USB=m
-CONFIG_CAN_KVASER_USB=m
-CONFIG_CAN_MCBA_USB=m
-CONFIG_CAN_PEAK_USB=m
-CONFIG_CAN_UCAN=m
-# end of CAN USB interfaces
-
-# CONFIG_CAN_DEBUG_DEVICES is not set
-# end of CAN Device Drivers
-
-CONFIG_BT=m
-CONFIG_BT_BREDR=y
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_CMTP=m
-CONFIG_BT_HIDP=m
-CONFIG_BT_HS=y
-CONFIG_BT_LE=y
-CONFIG_BT_6LOWPAN=m
-CONFIG_BT_LEDS=y
-CONFIG_BT_MSFTEXT=y
-CONFIG_BT_AOSPEXT=y
-CONFIG_BT_DEBUGFS=y
-# CONFIG_BT_SELFTEST is not set
-# CONFIG_BT_FEATURE_DEBUG is not set
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_INTEL=m
-CONFIG_BT_BCM=m
-CONFIG_BT_RTL=m
-CONFIG_BT_QCA=m
-CONFIG_BT_HCIBTUSB=m
-# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
-CONFIG_BT_HCIBTUSB_BCM=y
-CONFIG_BT_HCIBTUSB_MTK=y
-CONFIG_BT_HCIBTUSB_RTL=y
-CONFIG_BT_HCIBTSDIO=m
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_SERDEV=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_NOKIA=m
-CONFIG_BT_HCIUART_BCSP=y
-CONFIG_BT_HCIUART_ATH3K=y
-CONFIG_BT_HCIUART_LL=y
-CONFIG_BT_HCIUART_3WIRE=y
-CONFIG_BT_HCIUART_INTEL=y
-CONFIG_BT_HCIUART_RTL=y
-CONFIG_BT_HCIUART_QCA=y
-CONFIG_BT_HCIUART_AG6XX=y
-CONFIG_BT_HCIUART_MRVL=y
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIDTL1=m
-CONFIG_BT_HCIBT3C=m
-CONFIG_BT_HCIBLUECARD=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_BT_MRVL=m
-CONFIG_BT_MRVL_SDIO=m
-CONFIG_BT_ATH3K=m
-CONFIG_BT_MTKSDIO=m
-CONFIG_BT_MTKUART=m
-CONFIG_BT_HCIRSI=m
-CONFIG_BT_VIRTIO=m
-# end of Bluetooth device drivers
-
-CONFIG_AF_RXRPC=m
-CONFIG_AF_RXRPC_IPV6=y
-# CONFIG_AF_RXRPC_INJECT_LOSS is not set
-# CONFIG_AF_RXRPC_DEBUG is not set
-# CONFIG_RXKAD is not set
-CONFIG_AF_KCM=m
-CONFIG_STREAM_PARSER=y
-CONFIG_MCTP=y
-CONFIG_FIB_RULES=y
-CONFIG_WIRELESS=y
-CONFIG_WIRELESS_EXT=y
-# CONFIG_WEXT_CORE is not set
-# CONFIG_WEXT_PROC is not set
-# CONFIG_WEXT_SPY is not set
-# CONFIG_WEXT_PRIV is not set
-CONFIG_CFG80211=m
-CONFIG_NL80211_TESTMODE=y
-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
-CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
-CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
-CONFIG_CFG80211_DEFAULT_PS=y
-# CONFIG_CFG80211_DEBUGFS is not set
-CONFIG_CFG80211_CRDA_SUPPORT=y
-# CONFIG_CFG80211_WEXT is not set
-# CONFIG_CFG80211_WEXT_EXPORT is not set
-CONFIG_LIB80211=m
-CONFIG_LIB80211_CRYPT_WEP=m
-CONFIG_LIB80211_CRYPT_CCMP=m
-CONFIG_LIB80211_CRYPT_TKIP=m
-# CONFIG_LIB80211_DEBUG is not set
-CONFIG_MAC80211=m
-CONFIG_MAC80211_HAS_RC=y
-CONFIG_MAC80211_RC_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
-CONFIG_MAC80211_MESH=y
-CONFIG_MAC80211_LEDS=y
-# CONFIG_MAC80211_DEBUGFS is not set
-# CONFIG_MAC80211_MESSAGE_TRACING is not set
-# CONFIG_MAC80211_DEBUG_MENU is not set
-CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
-CONFIG_RFKILL=m
-CONFIG_RFKILL_LEDS=y
-# CONFIG_RFKILL_INPUT is not set
-CONFIG_RFKILL_GPIO=m
-CONFIG_NET_9P=m
-CONFIG_NET_9P_VIRTIO=m
-CONFIG_NET_9P_RDMA=m
-# CONFIG_NET_9P_DEBUG is not set
-CONFIG_CAIF=m
-# CONFIG_CAIF_DEBUG is not set
-CONFIG_CAIF_NETDEV=m
-CONFIG_CAIF_USB=m
-CONFIG_CEPH_LIB=m
-# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
-CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
-CONFIG_NFC=m
-CONFIG_NFC_DIGITAL=m
-CONFIG_NFC_NCI=m
-CONFIG_NFC_NCI_SPI=m
-CONFIG_NFC_NCI_UART=m
-CONFIG_NFC_HCI=m
-CONFIG_NFC_SHDLC=y
-
-#
-# Near Field Communication (NFC) devices
-#
-CONFIG_NFC_TRF7970A=m
-CONFIG_NFC_MEI_PHY=m
-CONFIG_NFC_SIM=m
-CONFIG_NFC_PORT100=m
-CONFIG_NFC_VIRTUAL_NCI=m
-CONFIG_NFC_FDP=m
-CONFIG_NFC_FDP_I2C=m
-CONFIG_NFC_PN544=m
-CONFIG_NFC_PN544_I2C=m
-CONFIG_NFC_PN544_MEI=m
-CONFIG_NFC_PN533=m
-CONFIG_NFC_PN533_USB=m
-CONFIG_NFC_PN533_I2C=m
-CONFIG_NFC_PN532_UART=m
-CONFIG_NFC_MICROREAD=m
-CONFIG_NFC_MICROREAD_I2C=m
-CONFIG_NFC_MICROREAD_MEI=m
-CONFIG_NFC_MRVL=m
-CONFIG_NFC_MRVL_USB=m
-CONFIG_NFC_MRVL_UART=m
-CONFIG_NFC_MRVL_I2C=m
-CONFIG_NFC_MRVL_SPI=m
-CONFIG_NFC_ST21NFCA=m
-CONFIG_NFC_ST21NFCA_I2C=m
-CONFIG_NFC_ST_NCI=m
-CONFIG_NFC_ST_NCI_I2C=m
-CONFIG_NFC_ST_NCI_SPI=m
-CONFIG_NFC_NXP_NCI=m
-CONFIG_NFC_NXP_NCI_I2C=m
-CONFIG_NFC_S3FWRN5=m
-CONFIG_NFC_S3FWRN5_I2C=m
-CONFIG_NFC_S3FWRN82_UART=m
-CONFIG_NFC_ST95HF=m
-# end of Near Field Communication (NFC) devices
-
-CONFIG_PSAMPLE=m
-CONFIG_NET_IFE=m
-CONFIG_LWTUNNEL=y
-CONFIG_LWTUNNEL_BPF=y
-# CONFIG_PAGE_POOL_STATS is not set
-CONFIG_DST_CACHE=y
-CONFIG_GRO_CELLS=y
-CONFIG_NET_SELFTESTS=m
-CONFIG_NET_SOCK_MSG=y
-CONFIG_NET_DEVLINK=y
-CONFIG_PAGE_POOL=y
-CONFIG_FAILOVER=m
-CONFIG_ETHTOOL_NETLINK=y
-
-#
-# Device Drivers
-#
-CONFIG_HAVE_EISA=y
-# CONFIG_EISA is not set
-CONFIG_HAVE_PCI=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_HOTPLUG_PCI_PCIE=y
-CONFIG_PCIEAER=y
-# CONFIG_PCIEAER_INJECT is not set
-CONFIG_PCIE_ECRC=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-CONFIG_PCIE_PME=y
-CONFIG_PCIE_DPC=y
-CONFIG_PCIE_PTM=y
-CONFIG_PCIE_EDR=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_QUIRKS=y
-# CONFIG_PCI_DEBUG is not set
-CONFIG_PCI_REALLOC_ENABLE_AUTO=y
-CONFIG_PCI_STUB=m
-CONFIG_PCI_PF_STUB=m
-CONFIG_PCI_ATS=y
-CONFIG_PCI_LOCKLESS_CONFIG=y
-CONFIG_PCI_IOV=y
-CONFIG_PCI_PRI=y
-CONFIG_PCI_PASID=y
-CONFIG_PCI_LABEL=y
-CONFIG_PCI_HYPERV=m
-# CONFIG_PCIE_BUS_TUNE_OFF is not set
-CONFIG_PCIE_BUS_DEFAULT=y
-# CONFIG_PCIE_BUS_SAFE is not set
-# CONFIG_PCIE_BUS_PERFORMANCE is not set
-# CONFIG_PCIE_BUS_PEER2PEER is not set
-CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_ACPI=y
-CONFIG_HOTPLUG_PCI_ACPI_IBM=m
-CONFIG_HOTPLUG_PCI_CPCI=y
-CONFIG_HOTPLUG_PCI_CPCI_ZT5550=m
-CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m
-CONFIG_HOTPLUG_PCI_SHPC=y
-
-#
-# PCI controller drivers
-#
-# CONFIG_VMD is not set
-CONFIG_PCI_HYPERV_INTERFACE=m
-
-#
-# DesignWare PCI Core Support
-#
-# CONFIG_PCIE_DW_PLAT_HOST is not set
-# CONFIG_PCIE_DW_PLAT_EP is not set
-# CONFIG_PCI_MESON is not set
-# end of DesignWare PCI Core Support
-
-#
-# Mobiveil PCIe Core Support
-#
-# end of Mobiveil PCIe Core Support
-
-#
-# Cadence PCIe controllers support
-#
-# end of Cadence PCIe controllers support
-# end of PCI controller drivers
-
-#
-# PCI Endpoint
-#
-CONFIG_PCI_ENDPOINT=y
-CONFIG_PCI_ENDPOINT_CONFIGFS=y
-# CONFIG_PCI_EPF_TEST is not set
-CONFIG_PCI_EPF_NTB=m
-# end of PCI Endpoint
-
-#
-# PCI switch controller drivers
-#
-CONFIG_PCI_SW_SWITCHTEC=m
-# end of PCI switch controller drivers
-
-CONFIG_CXL_BUS=m
-CONFIG_CXL_PCI=m
-CONFIG_CXL_MEM=m
-CONFIG_CXL_MEM_RAW_COMMANDS=y
-CONFIG_CXL_ACPI=m
-CONFIG_CXL_PMEM=m
-CONFIG_PCCARD=m
-CONFIG_PCMCIA=m
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_CARDBUS=y
-
-#
-# PC-card bridges
-#
-CONFIG_YENTA=m
-CONFIG_YENTA_O2=y
-CONFIG_YENTA_RICOH=y
-CONFIG_YENTA_TI=y
-CONFIG_YENTA_ENE_TUNE=y
-CONFIG_YENTA_TOSHIBA=y
-CONFIG_PD6729=m
-CONFIG_I82092=m
-CONFIG_PCCARD_NONSTATIC=y
-CONFIG_RAPIDIO=m
-CONFIG_RAPIDIO_TSI721=m
-CONFIG_RAPIDIO_DISC_TIMEOUT=30
-CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y
-CONFIG_RAPIDIO_DMA_ENGINE=y
-# CONFIG_RAPIDIO_DEBUG is not set
-CONFIG_RAPIDIO_ENUM_BASIC=m
-CONFIG_RAPIDIO_CHMAN=m
-CONFIG_RAPIDIO_MPORT_CDEV=m
-
-#
-# RapidIO Switch drivers
-#
-CONFIG_RAPIDIO_TSI57X=m
-CONFIG_RAPIDIO_CPS_XX=m
-CONFIG_RAPIDIO_TSI568=m
-CONFIG_RAPIDIO_CPS_GEN2=m
-CONFIG_RAPIDIO_RXS_GEN3=m
-# end of RapidIO Switch drivers
-
-#
-# Generic Driver Options
-#
-CONFIG_AUXILIARY_BUS=y
-# CONFIG_UEVENT_HELPER is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-
-#
-# Firmware loader
-#
-CONFIG_FW_LOADER=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_FW_LOADER_USER_HELPER is not set
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_FW_LOADER_COMPRESS=y
-CONFIG_FW_CACHE=y
-# end of Firmware loader
-
-CONFIG_WANT_DEV_COREDUMP=y
-CONFIG_ALLOW_DEV_COREDUMP=y
-CONFIG_DEV_COREDUMP=y
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
-CONFIG_HMEM_REPORTING=y
-CONFIG_TEST_ASYNC_DRIVER_PROBE=m
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=m
-CONFIG_REGMAP_SLIMBUS=m
-CONFIG_REGMAP_SPI=y
-CONFIG_REGMAP_SPMI=m
-CONFIG_REGMAP_W1=m
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_SOUNDWIRE=m
-CONFIG_REGMAP_SOUNDWIRE_MBQ=m
-CONFIG_REGMAP_SCCB=m
-CONFIG_REGMAP_I3C=m
-CONFIG_REGMAP_SPI_AVMM=m
-CONFIG_DMA_SHARED_BUFFER=y
-# CONFIG_DMA_FENCE_TRACE is not set
-# end of Generic Driver Options
-
-#
-# Bus devices
-#
-CONFIG_MHI_BUS=m
-# CONFIG_MHI_BUS_DEBUG is not set
-CONFIG_MHI_BUS_PCI_GENERIC=m
-# end of Bus devices
-
-CONFIG_CONNECTOR=m
-
-#
-# Firmware Drivers
-#
-
-#
-# ARM System Control and Management Interface Protocol
-#
-# end of ARM System Control and Management Interface Protocol
-
-CONFIG_EDD=m
-# CONFIG_EDD_OFF is not set
-CONFIG_FIRMWARE_MEMMAP=y
-CONFIG_DMIID=y
-CONFIG_DMI_SYSFS=m
-CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
-CONFIG_ISCSI_IBFT_FIND=y
-CONFIG_ISCSI_IBFT=m
-CONFIG_FW_CFG_SYSFS=m
-# CONFIG_FW_CFG_SYSFS_CMDLINE is not set
-CONFIG_SYSFB=y
-CONFIG_SYSFB_SIMPLEFB=y
-CONFIG_GOOGLE_FIRMWARE=y
-CONFIG_GOOGLE_SMI=m
-CONFIG_GOOGLE_COREBOOT_TABLE=m
-CONFIG_GOOGLE_MEMCONSOLE=m
-CONFIG_GOOGLE_MEMCONSOLE_X86_LEGACY=m
-CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m
-CONFIG_GOOGLE_VPD=m
-
-#
-# EFI (Extensible Firmware Interface) Support
-#
-CONFIG_EFI_VARS=m
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_VARS_PSTORE=m
-CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
-CONFIG_EFI_RUNTIME_MAP=y
-# CONFIG_EFI_FAKE_MEMMAP is not set
-CONFIG_EFI_SOFT_RESERVE=y
-CONFIG_EFI_ZBOOT=y
-# CONFIG_EFI_ZBOOT_SIGNING is not set
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
-CONFIG_EFI_BOOTLOADER_CONTROL=m
-CONFIG_EFI_CAPSULE_LOADER=m
-CONFIG_EFI_TEST=m
-CONFIG_APPLE_PROPERTIES=y
-CONFIG_RESET_ATTACK_MITIGATION=y
-CONFIG_EFI_RCI2_TABLE=y
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# end of EFI (Extensible Firmware Interface) Support
-
-CONFIG_UEFI_CPER=y
-CONFIG_UEFI_CPER_X86=y
-CONFIG_EFI_DEV_PATH_PARSER=y
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-
-#
-# Tegra firmware driver
-#
-# end of Tegra firmware driver
-# end of Firmware Drivers
-
-CONFIG_GNSS=m
-CONFIG_GNSS_SERIAL=m
-CONFIG_GNSS_MTK_SERIAL=m
-CONFIG_GNSS_SIRF_SERIAL=m
-CONFIG_GNSS_UBX_SERIAL=m
-CONFIG_MTD=m
-CONFIG_MTD_TESTS=m
-
-#
-# Partition parsers
-#
-CONFIG_MTD_AR7_PARTS=m
-CONFIG_MTD_CMDLINE_PARTS=m
-CONFIG_MTD_REDBOOT_PARTS=m
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-# end of Partition parsers
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
-CONFIG_MTD_BLOCK_RO=m
-
-#
-# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
-#
-CONFIG_FTL=m
-CONFIG_NFTL=m
-CONFIG_NFTL_RW=y
-CONFIG_INFTL=m
-CONFIG_RFD_FTL=m
-CONFIG_SSFDC=m
-CONFIG_SM_FTL=m
-CONFIG_MTD_OOPS=m
-CONFIG_MTD_PSTORE=m
-CONFIG_MTD_SWAP=m
-# CONFIG_MTD_PARTITIONED_MASTER is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_GEN_PROBE=m
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-CONFIG_MTD_CFI_INTELEXT=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_CFI_STAA=m
-CONFIG_MTD_CFI_UTIL=m
-CONFIG_MTD_RAM=m
-CONFIG_MTD_ROM=m
-CONFIG_MTD_ABSENT=m
-# end of RAM/ROM/Flash chip drivers
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=m
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-# CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set
-CONFIG_MTD_SBC_GXX=m
-CONFIG_MTD_AMD76XROM=m
-CONFIG_MTD_ICHXROM=m
-CONFIG_MTD_ESB2ROM=m
-CONFIG_MTD_CK804XROM=m
-CONFIG_MTD_SCB2_FLASH=m
-CONFIG_MTD_NETtel=m
-CONFIG_MTD_L440GX=m
-CONFIG_MTD_PCI=m
-CONFIG_MTD_PCMCIA=m
-# CONFIG_MTD_PCMCIA_ANONYMOUS is not set
-CONFIG_MTD_INTEL_VR_NOR=m
-CONFIG_MTD_PLATRAM=m
-# end of Mapping drivers for chip access
-
-#
-# Self-contained MTD device drivers
-#
-CONFIG_MTD_PMC551=m
-CONFIG_MTD_PMC551_BUGFIX=y
-# CONFIG_MTD_PMC551_DEBUG is not set
-CONFIG_MTD_DATAFLASH=m
-CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
-CONFIG_MTD_DATAFLASH_OTP=y
-CONFIG_MTD_MCHP23K256=m
-CONFIG_MTD_MCHP48L640=m
-CONFIG_MTD_SST25L=m
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTDRAM_TOTAL_SIZE=4096
-CONFIG_MTDRAM_ERASE_SIZE=128
-CONFIG_MTD_BLOCK2MTD=m
-
-#
-# Disk-On-Chip Device Drivers
-#
-CONFIG_MTD_DOCG3=m
-CONFIG_BCH_CONST_M=14
-CONFIG_BCH_CONST_T=4
-# end of Self-contained MTD device drivers
-
-#
-# NAND
-#
-CONFIG_MTD_NAND_CORE=m
-CONFIG_MTD_ONENAND=m
-CONFIG_MTD_ONENAND_VERIFY_WRITE=y
-CONFIG_MTD_ONENAND_GENERIC=m
-CONFIG_MTD_ONENAND_OTP=y
-CONFIG_MTD_ONENAND_2X_PROGRAM=y
-CONFIG_MTD_RAW_NAND=m
-
-#
-# Raw/parallel NAND flash controllers
-#
-CONFIG_MTD_NAND_DENALI=m
-CONFIG_MTD_NAND_DENALI_PCI=m
-CONFIG_MTD_NAND_CAFE=m
-CONFIG_MTD_NAND_MXIC=m
-CONFIG_MTD_NAND_GPIO=m
-CONFIG_MTD_NAND_PLATFORM=m
-CONFIG_MTD_NAND_ARASAN=m
-
-#
-# Misc
-#
-CONFIG_MTD_SM_COMMON=m
-CONFIG_MTD_NAND_NANDSIM=m
-CONFIG_MTD_NAND_RICOH=m
-CONFIG_MTD_NAND_DISKONCHIP=m
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
-CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
-CONFIG_MTD_SPI_NAND=m
-
-#
-# ECC engine support
-#
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
-CONFIG_MTD_NAND_ECC_SW_BCH=y
-CONFIG_MTD_NAND_ECC_MXIC=y
-# end of ECC engine support
-# end of NAND
-
-#
-# LPDDR & LPDDR2 PCM memory drivers
-#
-CONFIG_MTD_LPDDR=m
-CONFIG_MTD_QINFO_PROBE=m
-# end of LPDDR & LPDDR2 PCM memory drivers
-
-CONFIG_MTD_SPI_NOR=m
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SPI_NOR_SWP_DISABLE=y
-# CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE is not set
-# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set
-CONFIG_SPI_INTEL_SPI=m
-CONFIG_SPI_INTEL_SPI_PCI=m
-CONFIG_SPI_INTEL_SPI_PLATFORM=m
-CONFIG_MTD_UBI=m
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_FASTMAP=y
-# CONFIG_MTD_UBI_GLUEBI is not set
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_HYPERBUS=m
-# CONFIG_OF is not set
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_PARPORT=m
-CONFIG_PARPORT_PC=m
-CONFIG_PARPORT_SERIAL=m
-CONFIG_PARPORT_PC_FIFO=y
-CONFIG_PARPORT_PC_SUPERIO=y
-CONFIG_PARPORT_PC_PCMCIA=m
-CONFIG_PARPORT_AX88796=m
-CONFIG_PARPORT_1284=y
-CONFIG_PARPORT_NOT_PC=y
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG_MESSAGES is not set
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_NULL_BLK is not set
-CONFIG_BLK_DEV_FD=m
-CONFIG_BLK_DEV_FD_RAWCMD=y
-CONFIG_CDROM=m
-# CONFIG_PARIDE is not set
-CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
-CONFIG_ZRAM=m
-# CONFIG_ZRAM_DEF_COMP_LZORLE is not set
-CONFIG_ZRAM_DEF_COMP_ZSTD=y
-# CONFIG_ZRAM_DEF_COMP_LZ4 is not set
-# CONFIG_ZRAM_DEF_COMP_LZO is not set
-# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set
-# CONFIG_ZRAM_DEF_COMP_842 is not set
-CONFIG_ZRAM_DEF_COMP="zstd"
-CONFIG_ZRAM_WRITEBACK=y
-# CONFIG_ZRAM_MEMORY_TRACKING is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
-CONFIG_BLK_DEV_DRBD=m
-# CONFIG_DRBD_FAULT_INJECTION is not set
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_SX8=m
-CONFIG_BLK_DEV_RAM=m
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-CONFIG_CDROM_PKTCDVD_WCACHE=y
-CONFIG_ATA_OVER_ETH=m
-CONFIG_VIRTIO_BLK=m
-CONFIG_BLK_DEV_RBD=m
-CONFIG_BLK_DEV_RSXX=m
-CONFIG_BLK_DEV_RNBD=y
-CONFIG_BLK_DEV_RNBD_CLIENT=m
-CONFIG_BLK_DEV_RNBD_SERVER=m
-
-#
-# NVME Support
-#
-CONFIG_NVME_CORE=m
-CONFIG_BLK_DEV_NVME=m
-# CONFIG_NVME_MULTIPATH is not set
-CONFIG_NVME_VERBOSE_ERRORS=y
-CONFIG_NVME_HWMON=y
-CONFIG_NVME_FABRICS=m
-CONFIG_NVME_RDMA=m
-CONFIG_NVME_FC=m
-CONFIG_NVME_TCP=m
-CONFIG_NVME_TARGET=m
-CONFIG_NVME_TARGET_PASSTHRU=y
-CONFIG_NVME_TARGET_LOOP=m
-CONFIG_NVME_TARGET_RDMA=m
-CONFIG_NVME_TARGET_FC=m
-CONFIG_NVME_TARGET_FCLOOP=m
-CONFIG_NVME_TARGET_TCP=m
-# end of NVME Support
-
-#
-# Misc devices
-#
-CONFIG_SENSORS_LIS3LV02D=m
-CONFIG_AD525X_DPOT=m
-CONFIG_AD525X_DPOT_I2C=m
-CONFIG_AD525X_DPOT_SPI=m
-# CONFIG_DUMMY_IRQ is not set
-CONFIG_IBM_ASM=m
-CONFIG_PHANTOM=m
-CONFIG_TIFM_CORE=m
-CONFIG_TIFM_7XX1=m
-CONFIG_ICS932S401=m
-CONFIG_ENCLOSURE_SERVICES=m
-CONFIG_HP_ILO=m
-CONFIG_APDS9802ALS=m
-CONFIG_ISL29003=m
-CONFIG_ISL29020=m
-CONFIG_SENSORS_TSL2550=m
-CONFIG_SENSORS_BH1770=m
-CONFIG_SENSORS_APDS990X=m
-CONFIG_HMC6352=m
-CONFIG_DS1682=m
-CONFIG_VMWARE_BALLOON=m
-CONFIG_LATTICE_ECP3_CONFIG=m
-CONFIG_SRAM=y
-CONFIG_DW_XDATA_PCIE=m
-CONFIG_PCI_ENDPOINT_TEST=m
-CONFIG_XILINX_SDFEC=m
-CONFIG_MISC_RTSX=m
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-CONFIG_EEPROM_AT24=m
-CONFIG_EEPROM_AT25=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_EEPROM_MAX6875=m
-CONFIG_EEPROM_93CX6=m
-CONFIG_EEPROM_93XX46=m
-CONFIG_EEPROM_IDT_89HPESX=m
-CONFIG_EEPROM_EE1004=m
-# end of EEPROM support
-
-CONFIG_CB710_CORE=m
-# CONFIG_CB710_DEBUG is not set
-CONFIG_CB710_DEBUG_ASSUMPTIONS=y
-
-#
-# Texas Instruments shared transport line discipline
-#
-CONFIG_TI_ST=m
-# end of Texas Instruments shared transport line discipline
-
-CONFIG_SENSORS_LIS3_I2C=m
-
-#
-# Altera FPGA firmware download module (requires I2C)
-#
-CONFIG_ALTERA_STAPL=m
-CONFIG_INTEL_MEI=m
-# CONFIG_INTEL_MEI_ME is not set
-# CONFIG_INTEL_MEI_TXE is not set
-CONFIG_VMWARE_VMCI=m
-CONFIG_GENWQE=m
-CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0
-CONFIG_ECHO=m
-CONFIG_BCM_VK=m
-CONFIG_BCM_VK_TTY=y
-CONFIG_MISC_ALCOR_PCI=m
-CONFIG_MISC_RTSX_PCI=m
-CONFIG_MISC_RTSX_USB=m
-CONFIG_HABANA_AI=m
-CONFIG_UACCE=m
-CONFIG_PVPANIC=y
-CONFIG_PVPANIC_MMIO=m
-CONFIG_PVPANIC_PCI=m
-CONFIG_GP_PCI1XXXX=m
-# end of Misc devices
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=m
-CONFIG_RAID_ATTRS=m
-CONFIG_SCSI_COMMON=m
-CONFIG_SCSI=m
-CONFIG_SCSI_DMA=y
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_BLK_DEV_BSG=y
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_ENCLOSURE=m
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_ISCSI_ATTRS=m
-CONFIG_SCSI_SAS_ATTRS=m
-CONFIG_SCSI_SAS_LIBSAS=m
-CONFIG_SCSI_SAS_ATA=y
-CONFIG_SCSI_SAS_HOST_SMP=y
-CONFIG_SCSI_SRP_ATTRS=m
-# end of SCSI Transports
-
-CONFIG_SCSI_LOWLEVEL=y
-CONFIG_ISCSI_TCP=m
-CONFIG_ISCSI_BOOT_SYSFS=m
-CONFIG_SCSI_CXGB3_ISCSI=m
-CONFIG_SCSI_CXGB4_ISCSI=m
-CONFIG_SCSI_BNX2_ISCSI=m
-CONFIG_SCSI_BNX2X_FCOE=m
-CONFIG_BE2ISCSI=m
-CONFIG_BLK_DEV_3W_XXXX_RAID=m
-CONFIG_SCSI_HPSA=m
-CONFIG_SCSI_3W_9XXX=m
-CONFIG_SCSI_3W_SAS=m
-CONFIG_SCSI_ACARD=m
-CONFIG_SCSI_AACRAID=m
-CONFIG_SCSI_AIC7XXX=m
-CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
-CONFIG_AIC7XXX_RESET_DELAY_MS=15000
-# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
-CONFIG_AIC7XXX_DEBUG_MASK=0
-# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC79XX=m
-CONFIG_AIC79XX_CMDS_PER_DEVICE=4
-CONFIG_AIC79XX_RESET_DELAY_MS=15000
-# CONFIG_AIC79XX_DEBUG_ENABLE is not set
-CONFIG_AIC79XX_DEBUG_MASK=0
-# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
-CONFIG_SCSI_AIC94XX=m
-# CONFIG_AIC94XX_DEBUG is not set
-CONFIG_SCSI_MVSAS=m
-# CONFIG_SCSI_MVSAS_DEBUG is not set
-CONFIG_SCSI_MVSAS_TASKLET=y
-CONFIG_SCSI_MVUMI=m
-CONFIG_SCSI_DPT_I2O=m
-CONFIG_SCSI_ADVANSYS=m
-CONFIG_SCSI_ARCMSR=m
-CONFIG_SCSI_ESAS2R=m
-CONFIG_MEGARAID_NEWGEN=y
-CONFIG_MEGARAID_MM=m
-CONFIG_MEGARAID_MAILBOX=m
-CONFIG_MEGARAID_LEGACY=m
-CONFIG_MEGARAID_SAS=m
-CONFIG_SCSI_MPT3SAS=m
-CONFIG_SCSI_MPT2SAS_MAX_SGE=128
-CONFIG_SCSI_MPT3SAS_MAX_SGE=128
-CONFIG_SCSI_MPT2SAS=m
-CONFIG_SCSI_MPI3MR=m
-CONFIG_SCSI_SMARTPQI=m
-CONFIG_SCSI_UFSHCD=m
-CONFIG_SCSI_UFSHCD_PCI=m
-CONFIG_SCSI_UFS_DWC_TC_PCI=m
-CONFIG_SCSI_UFSHCD_PLATFORM=m
-CONFIG_SCSI_UFS_CDNS_PLATFORM=m
-CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m
-# CONFIG_SCSI_UFS_BSG is not set
-CONFIG_SCSI_UFS_HPB=y
-CONFIG_SCSI_UFS_HWMON=y
-CONFIG_SCSI_HPTIOP=m
-CONFIG_SCSI_BUSLOGIC=m
-CONFIG_SCSI_FLASHPOINT=y
-CONFIG_SCSI_MYRB=m
-CONFIG_SCSI_MYRS=m
-CONFIG_VMWARE_PVSCSI=m
-CONFIG_HYPERV_STORAGE=m
-CONFIG_LIBFC=m
-CONFIG_LIBFCOE=m
-CONFIG_FCOE=m
-CONFIG_FCOE_FNIC=m
-CONFIG_SCSI_SNIC=m
-# CONFIG_SCSI_SNIC_DEBUG_FS is not set
-CONFIG_SCSI_DMX3191D=m
-CONFIG_SCSI_FDOMAIN=m
-CONFIG_SCSI_FDOMAIN_PCI=m
-CONFIG_SCSI_ISCI=m
-CONFIG_SCSI_IPS=m
-CONFIG_SCSI_INITIO=m
-CONFIG_SCSI_INIA100=m
-CONFIG_SCSI_PPA=m
-CONFIG_SCSI_IMM=m
-# CONFIG_SCSI_IZIP_EPP16 is not set
-# CONFIG_SCSI_IZIP_SLOW_CTR is not set
-CONFIG_SCSI_STEX=m
-CONFIG_SCSI_SYM53C8XX_2=m
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_IPR=m
-# CONFIG_SCSI_IPR_TRACE is not set
-# CONFIG_SCSI_IPR_DUMP is not set
-CONFIG_SCSI_QLOGIC_1280=m
-CONFIG_SCSI_QLA_FC=m
-CONFIG_TCM_QLA2XXX=m
-# CONFIG_TCM_QLA2XXX_DEBUG is not set
-CONFIG_SCSI_QLA_ISCSI=m
-CONFIG_QEDI=m
-CONFIG_QEDF=m
-CONFIG_SCSI_LPFC=m
-# CONFIG_SCSI_LPFC_DEBUG_FS is not set
-CONFIG_SCSI_EFCT=m
-CONFIG_SCSI_DC395x=m
-CONFIG_SCSI_AM53C974=m
-CONFIG_SCSI_WD719X=m
-# CONFIG_SCSI_DEBUG is not set
-CONFIG_SCSI_PMCRAID=m
-CONFIG_SCSI_PM8001=m
-CONFIG_SCSI_BFA_FC=m
-CONFIG_SCSI_VIRTIO=m
-CONFIG_SCSI_CHELSIO_FCOE=m
-CONFIG_SCSI_LOWLEVEL_PCMCIA=y
-CONFIG_PCMCIA_AHA152X=m
-CONFIG_PCMCIA_FDOMAIN=m
-CONFIG_PCMCIA_QLOGIC=m
-CONFIG_PCMCIA_SYM53C500=m
-CONFIG_SCSI_DH=y
-CONFIG_SCSI_DH_RDAC=m
-CONFIG_SCSI_DH_HP_SW=m
-CONFIG_SCSI_DH_EMC=m
-CONFIG_SCSI_DH_ALUA=m
-# end of SCSI device support
-
-CONFIG_ATA=m
-CONFIG_SATA_HOST=y
-CONFIG_PATA_TIMINGS=y
-# CONFIG_ATA_VERBOSE_ERROR is not set
-CONFIG_ATA_FORCE=y
-CONFIG_ATA_ACPI=y
-CONFIG_SATA_ZPODD=y
-CONFIG_SATA_PMP=y
-
-#
-# Controllers with non-SFF native interface
-#
-CONFIG_SATA_AHCI=m
-CONFIG_SATA_MOBILE_LPM_POLICY=0
-CONFIG_SATA_AHCI_PLATFORM=m
-CONFIG_SATA_INIC162X=m
-CONFIG_SATA_ACARD_AHCI=m
-CONFIG_SATA_SIL24=m
-CONFIG_ATA_SFF=y
-
-#
-# SFF controllers with custom DMA interface
-#
-CONFIG_PDC_ADMA=m
-CONFIG_SATA_QSTOR=m
-CONFIG_SATA_SX4=m
-CONFIG_ATA_BMDMA=y
-
-#
-# SATA SFF controllers with BMDMA
-#
-CONFIG_ATA_PIIX=m
-CONFIG_SATA_DWC=m
-# CONFIG_SATA_DWC_OLD_DMA is not set
-# CONFIG_SATA_DWC_DEBUG is not set
-CONFIG_SATA_MV=m
-CONFIG_SATA_NV=m
-CONFIG_SATA_PROMISE=m
-CONFIG_SATA_SIL=m
-CONFIG_SATA_SIS=m
-CONFIG_SATA_SVW=m
-CONFIG_SATA_ULI=m
-CONFIG_SATA_VIA=m
-CONFIG_SATA_VITESSE=m
-
-#
-# PATA SFF controllers with BMDMA
-#
-CONFIG_PATA_ALI=m
-CONFIG_PATA_AMD=m
-CONFIG_PATA_ARTOP=m
-CONFIG_PATA_ATIIXP=m
-CONFIG_PATA_ATP867X=m
-CONFIG_PATA_CMD64X=m
-CONFIG_PATA_CYPRESS=m
-CONFIG_PATA_EFAR=m
-CONFIG_PATA_HPT366=m
-CONFIG_PATA_HPT37X=m
-CONFIG_PATA_HPT3X2N=m
-CONFIG_PATA_HPT3X3=m
-CONFIG_PATA_HPT3X3_DMA=y
-CONFIG_PATA_IT8213=m
-CONFIG_PATA_IT821X=m
-CONFIG_PATA_JMICRON=m
-CONFIG_PATA_MARVELL=m
-CONFIG_PATA_NETCELL=m
-CONFIG_PATA_NINJA32=m
-CONFIG_PATA_NS87415=m
-CONFIG_PATA_OLDPIIX=m
-CONFIG_PATA_OPTIDMA=m
-CONFIG_PATA_PDC2027X=m
-CONFIG_PATA_PDC_OLD=m
-CONFIG_PATA_RADISYS=m
-CONFIG_PATA_RDC=m
-CONFIG_PATA_SCH=m
-CONFIG_PATA_SERVERWORKS=m
-CONFIG_PATA_SIL680=m
-CONFIG_PATA_SIS=m
-CONFIG_PATA_TOSHIBA=m
-CONFIG_PATA_TRIFLEX=m
-CONFIG_PATA_VIA=m
-CONFIG_PATA_WINBOND=m
-
-#
-# PIO-only SFF controllers
-#
-CONFIG_PATA_CMD640_PCI=m
-CONFIG_PATA_MPIIX=m
-CONFIG_PATA_NS87410=m
-CONFIG_PATA_OPTI=m
-CONFIG_PATA_PCMCIA=m
-# CONFIG_PATA_PLATFORM is not set
-CONFIG_PATA_OF_PLATFORM=m
-CONFIG_PATA_RZ1000=m
-
-#
-# Generic fallback / legacy drivers
-#
-CONFIG_PATA_ACPI=m
-CONFIG_ATA_GENERIC=m
-CONFIG_PATA_LEGACY=m
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID456=m
-CONFIG_MD_MULTIPATH=m
-CONFIG_MD_FAULTY=m
-CONFIG_MD_CLUSTER=m
-CONFIG_BCACHE=m
-# CONFIG_BCACHE_DEBUG is not set
-# CONFIG_BCACHE_CLOSURES_DEBUG is not set
-CONFIG_BCACHE_ASYNC_REGISTRATION=y
-CONFIG_BLK_DEV_DM_BUILTIN=y
-CONFIG_BLK_DEV_DM=m
-# CONFIG_DM_DEBUG is not set
-CONFIG_DM_BUFIO=m
-# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set
-CONFIG_DM_BIO_PRISON=m
-CONFIG_DM_PERSISTENT_DATA=m
-CONFIG_DM_UNSTRIPED=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_THIN_PROVISIONING=m
-CONFIG_DM_CACHE=m
-CONFIG_DM_CACHE_SMQ=m
-CONFIG_DM_WRITECACHE=m
-# CONFIG_DM_EBS is not set
-CONFIG_DM_ERA=m
-CONFIG_DM_CLONE=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_LOG_USERSPACE=m
-CONFIG_DM_RAID=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_QL=m
-CONFIG_DM_MULTIPATH_ST=m
-CONFIG_DM_MULTIPATH_HST=m
-CONFIG_DM_MULTIPATH_IOA=m
-CONFIG_DM_DELAY=m
-CONFIG_DM_DUST=m
-CONFIG_DM_UEVENT=y
-CONFIG_DM_FLAKEY=m
-CONFIG_DM_VERITY=m
-CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y
-# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING is not set
-# CONFIG_DM_VERITY_FEC is not set
-CONFIG_DM_SWITCH=m
-CONFIG_DM_LOG_WRITES=m
-CONFIG_DM_INTEGRITY=m
-CONFIG_DM_ZONED=m
-CONFIG_DM_AUDIT=y
-CONFIG_TARGET_CORE=m
-CONFIG_TCM_IBLOCK=m
-CONFIG_TCM_FILEIO=m
-CONFIG_TCM_PSCSI=m
-CONFIG_TCM_USER2=m
-CONFIG_LOOPBACK_TARGET=m
-CONFIG_TCM_FC=m
-CONFIG_ISCSI_TARGET=m
-CONFIG_ISCSI_TARGET_CXGB4=m
-CONFIG_SBP_TARGET=m
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=m
-CONFIG_FUSION_FC=m
-CONFIG_FUSION_SAS=m
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_CTL=m
-CONFIG_FUSION_LAN=m
-CONFIG_FUSION_LOGGING=y
-
-#
-# IEEE 1394 (FireWire) support
-#
-CONFIG_FIREWIRE=m
-CONFIG_FIREWIRE_OHCI=m
-CONFIG_FIREWIRE_SBP2=m
-CONFIG_FIREWIRE_NET=m
-CONFIG_FIREWIRE_NOSY=m
-# end of IEEE 1394 (FireWire) support
-
-# CONFIG_MACINTOSH_DRIVERS is not set
-CONFIG_NETDEVICES=y
-CONFIG_MII=m
-CONFIG_NET_CORE=y
-CONFIG_BONDING=m
-CONFIG_DUMMY=m
-CONFIG_WIREGUARD=m
-# CONFIG_WIREGUARD_DEBUG is not set
-CONFIG_EQUALIZER=m
-CONFIG_NET_FC=y
-CONFIG_IFB=m
-CONFIG_NET_TEAM=m
-CONFIG_NET_TEAM_MODE_BROADCAST=m
-CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
-CONFIG_NET_TEAM_MODE_RANDOM=m
-CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
-CONFIG_NET_TEAM_MODE_LOADBALANCE=m
-CONFIG_MACVLAN=m
-CONFIG_MACVTAP=m
-CONFIG_IPVLAN_L3S=y
-CONFIG_IPVLAN=m
-CONFIG_IPVTAP=m
-CONFIG_VXLAN=m
-CONFIG_GENEVE=m
-CONFIG_BAREUDP=m
-CONFIG_GTP=m
-CONFIG_AMT=m
-CONFIG_MACSEC=m
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_NETPOLL=y
-CONFIG_NET_POLL_CONTROLLER=y
-CONFIG_NTB_NETDEV=m
-CONFIG_RIONET=m
-CONFIG_RIONET_TX_SIZE=128
-CONFIG_RIONET_RX_SIZE=128
-CONFIG_TUN=m
-CONFIG_TAP=m
-# CONFIG_TUN_VNET_CROSS_LE is not set
-CONFIG_VETH=m
-CONFIG_VIRTIO_NET=m
-CONFIG_NLMON=m
-CONFIG_NET_VRF=m
-CONFIG_VSOCKMON=m
-CONFIG_MHI_NET=m
-CONFIG_SUNGEM_PHY=m
-CONFIG_ARCNET=m
-CONFIG_ARCNET_1201=m
-CONFIG_ARCNET_1051=m
-CONFIG_ARCNET_RAW=m
-CONFIG_ARCNET_CAP=m
-CONFIG_ARCNET_COM90xx=m
-CONFIG_ARCNET_COM90xxIO=m
-CONFIG_ARCNET_RIM_I=m
-CONFIG_ARCNET_COM20020=m
-CONFIG_ARCNET_COM20020_PCI=m
-CONFIG_ARCNET_COM20020_CS=m
-CONFIG_ATM_DRIVERS=y
-# CONFIG_ATM_DUMMY is not set
-CONFIG_ATM_TCP=m
-CONFIG_ATM_LANAI=m
-CONFIG_ATM_ENI=m
-# CONFIG_ATM_ENI_DEBUG is not set
-# CONFIG_ATM_ENI_TUNE_BURST is not set
-CONFIG_ATM_FIRESTREAM=m
-CONFIG_ATM_ZATM=m
-# CONFIG_ATM_ZATM_DEBUG is not set
-CONFIG_ATM_NICSTAR=m
-CONFIG_ATM_NICSTAR_USE_SUNI=y
-CONFIG_ATM_NICSTAR_USE_IDT77105=y
-CONFIG_ATM_IDT77252=m
-# CONFIG_ATM_IDT77252_DEBUG is not set
-# CONFIG_ATM_IDT77252_RCV_ALL is not set
-CONFIG_ATM_IDT77252_USE_SUNI=y
-CONFIG_ATM_AMBASSADOR=m
-# CONFIG_ATM_AMBASSADOR_DEBUG is not set
-CONFIG_ATM_HORIZON=m
-# CONFIG_ATM_HORIZON_DEBUG is not set
-CONFIG_ATM_IA=m
-# CONFIG_ATM_IA_DEBUG is not set
-CONFIG_ATM_FORE200E=m
-CONFIG_ATM_FORE200E_USE_TASKLET=y
-CONFIG_ATM_FORE200E_TX_RETRY=16
-CONFIG_ATM_FORE200E_DEBUG=0
-CONFIG_ATM_HE=m
-CONFIG_ATM_HE_USE_SUNI=y
-CONFIG_ATM_SOLOS=m
-# CONFIG_CAIF_DRIVERS is not set
-
-#
-# Distributed Switch Architecture drivers
-#
-CONFIG_B53=m
-CONFIG_B53_SPI_DRIVER=m
-CONFIG_B53_MDIO_DRIVER=m
-CONFIG_B53_MMAP_DRIVER=m
-CONFIG_B53_SRAB_DRIVER=m
-CONFIG_B53_SERDES=m
-CONFIG_NET_DSA_BCM_SF2=m
-CONFIG_NET_DSA_LOOP=m
-CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m
-CONFIG_NET_DSA_LANTIQ_GSWIP=m
-CONFIG_NET_DSA_MT7530=m
-CONFIG_NET_DSA_MV88E6060=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8795=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-CONFIG_NET_DSA_MV88E6XXX=m
-CONFIG_NET_DSA_MV88E6XXX_PTP=y
-CONFIG_NET_DSA_MSCC_SEVILLE=m
-CONFIG_NET_DSA_AR9331=m
-CONFIG_NET_DSA_SJA1105=m
-CONFIG_NET_DSA_SJA1105_PTP=y
-CONFIG_NET_DSA_SJA1105_TAS=y
-# CONFIG_NET_DSA_SJA1105_VL is not set
-CONFIG_NET_DSA_XRS700X=m
-CONFIG_NET_DSA_XRS700X_I2C=m
-CONFIG_NET_DSA_XRS700X_MDIO=m
-CONFIG_NET_DSA_QCA8K=m
-CONFIG_NET_DSA_REALTEK_SMI=m
-CONFIG_NET_DSA_SMSC_LAN9303=m
-CONFIG_NET_DSA_SMSC_LAN9303_I2C=m
-CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m
-CONFIG_NET_DSA_VITESSE_VSC73XX=m
-CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m
-CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m
-# end of Distributed Switch Architecture drivers
-
-CONFIG_ETHERNET=y
-CONFIG_MDIO=m
-CONFIG_NET_VENDOR_3COM=y
-CONFIG_PCMCIA_3C574=m
-CONFIG_PCMCIA_3C589=m
-CONFIG_VORTEX=m
-CONFIG_TYPHOON=m
-CONFIG_NET_VENDOR_ADAPTEC=y
-CONFIG_ADAPTEC_STARFIRE=m
-CONFIG_NET_VENDOR_AGERE=y
-CONFIG_ET131X=m
-CONFIG_NET_VENDOR_ALACRITECH=y
-CONFIG_SLICOSS=m
-CONFIG_NET_VENDOR_ALTEON=y
-CONFIG_ACENIC=m
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
-CONFIG_ALTERA_TSE=m
-CONFIG_NET_VENDOR_AMAZON=y
-CONFIG_ENA_ETHERNET=m
-CONFIG_NET_VENDOR_AMD=y
-CONFIG_AMD8111_ETH=m
-CONFIG_PCNET32=m
-CONFIG_PCMCIA_NMCLAN=m
-CONFIG_AMD_XGBE=m
-CONFIG_AMD_XGBE_DCB=y
-CONFIG_AMD_XGBE_HAVE_ECC=y
-CONFIG_NET_VENDOR_AQUANTIA=y
-CONFIG_AQTION=m
-CONFIG_NET_VENDOR_ARC=y
-CONFIG_NET_VENDOR_ASIX=y
-CONFIG_SPI_AX88796C=m
-CONFIG_SPI_AX88796C_COMPRESSION=y
-CONFIG_NET_VENDOR_ATHEROS=y
-CONFIG_ATL2=m
-CONFIG_ATL1=m
-CONFIG_ATL1E=m
-CONFIG_ATL1C=m
-CONFIG_ALX=m
-CONFIG_NET_VENDOR_BROADCOM=y
-CONFIG_B44=m
-CONFIG_B44_PCI_AUTOSELECT=y
-CONFIG_B44_PCICORE_AUTOSELECT=y
-CONFIG_B44_PCI=y
-CONFIG_BCMGENET=m
-CONFIG_BNX2=m
-CONFIG_CNIC=m
-CONFIG_TIGON3=m
-CONFIG_TIGON3_HWMON=y
-CONFIG_BNX2X=m
-CONFIG_BNX2X_SRIOV=y
-CONFIG_SYSTEMPORT=m
-CONFIG_BNXT=m
-CONFIG_BNXT_SRIOV=y
-CONFIG_BNXT_FLOWER_OFFLOAD=y
-CONFIG_BNXT_DCB=y
-CONFIG_BNXT_HWMON=y
-CONFIG_NET_VENDOR_BROCADE=y
-CONFIG_BNA=m
-CONFIG_NET_VENDOR_CADENCE=y
-CONFIG_MACB=m
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MACB_PCI=m
-CONFIG_NET_VENDOR_CAVIUM=y
-CONFIG_THUNDER_NIC_PF=m
-CONFIG_THUNDER_NIC_VF=m
-CONFIG_THUNDER_NIC_BGX=m
-CONFIG_THUNDER_NIC_RGX=m
-CONFIG_CAVIUM_PTP=m
-CONFIG_LIQUIDIO=m
-CONFIG_LIQUIDIO_VF=m
-CONFIG_NET_VENDOR_CHELSIO=y
-CONFIG_CHELSIO_T1=m
-CONFIG_CHELSIO_T1_1G=y
-CONFIG_CHELSIO_T3=m
-CONFIG_CHELSIO_T4=m
-CONFIG_CHELSIO_T4_DCB=y
-# CONFIG_CHELSIO_T4_FCOE is not set
-CONFIG_CHELSIO_T4VF=m
-CONFIG_CHELSIO_LIB=m
-CONFIG_CHELSIO_INLINE_CRYPTO=y
-CONFIG_CHELSIO_IPSEC_INLINE=m
-CONFIG_NET_VENDOR_CISCO=y
-CONFIG_ENIC=m
-# CONFIG_NET_VENDOR_CORTINA is not set
-CONFIG_NET_VENDOR_DAVICOM=y
-CONFIG_DM9051=m
-CONFIG_CX_ECAT=m
-CONFIG_DNET=m
-CONFIG_NET_VENDOR_DEC=y
-CONFIG_NET_TULIP=y
-CONFIG_DE2104X=m
-CONFIG_DE2104X_DSL=0
-CONFIG_TULIP=m
-CONFIG_TULIP_MWI=y
-CONFIG_TULIP_MMIO=y
-CONFIG_TULIP_NAPI=y
-CONFIG_TULIP_NAPI_HW_MITIGATION=y
-CONFIG_DE4X5=m
-CONFIG_WINBOND_840=m
-CONFIG_DM9102=m
-CONFIG_ULI526X=m
-CONFIG_PCMCIA_XIRCOM=m
-CONFIG_NET_VENDOR_DLINK=y
-CONFIG_DL2K=m
-CONFIG_SUNDANCE=m
-# CONFIG_SUNDANCE_MMIO is not set
-CONFIG_NET_VENDOR_EMULEX=y
-CONFIG_BE2NET=m
-CONFIG_BE2NET_HWMON=y
-CONFIG_BE2NET_BE2=y
-CONFIG_BE2NET_BE3=y
-CONFIG_BE2NET_LANCER=y
-CONFIG_BE2NET_SKYHAWK=y
-CONFIG_NET_VENDOR_EZCHIP=y
-CONFIG_NET_VENDOR_FUJITSU=y
-CONFIG_NET_VENDOR_FUNGIBLE=y
-CONFIG_FUN_ETH=m
-CONFIG_PCMCIA_FMVJ18X=m
-CONFIG_NET_VENDOR_GOOGLE=y
-CONFIG_GVE=m
-CONFIG_NET_VENDOR_HUAWEI=y
-CONFIG_HINIC=m
-CONFIG_NET_VENDOR_I825XX=y
-CONFIG_NET_VENDOR_INTEL=y
-CONFIG_E100=m
-CONFIG_E1000=m
-CONFIG_E1000E=m
-CONFIG_E1000E_HWTS=y
-CONFIG_IGB=m
-CONFIG_IGB_HWMON=y
-CONFIG_IGBVF=m
-CONFIG_IXGB=m
-CONFIG_IXGBE=m
-CONFIG_IXGBE_HWMON=y
-CONFIG_IXGBE_DCB=y
-CONFIG_IXGBE_IPSEC=y
-CONFIG_IXGBEVF=m
-CONFIG_IXGBEVF_IPSEC=y
-CONFIG_I40E=m
-CONFIG_I40E_DCB=y
-CONFIG_IAVF=m
-CONFIG_I40EVF=m
-CONFIG_ICE=m
-CONFIG_ICE_SWITCHDEV=y
-CONFIG_ICE_HWTS=y
-CONFIG_FM10K=m
-CONFIG_IGC=m
-CONFIG_NET_VENDOR_MICROSOFT=y
-CONFIG_MICROSOFT_MANA=m
-CONFIG_JME=m
-CONFIG_NET_VENDOR_LITEX=y
-CONFIG_NET_VENDOR_MARVELL=y
-CONFIG_MVMDIO=m
-CONFIG_SKGE=m
-# CONFIG_SKGE_DEBUG is not set
-CONFIG_SKGE_GENESIS=y
-CONFIG_SKY2=m
-# CONFIG_SKY2_DEBUG is not set
-CONFIG_OCTEON_EP=m
-CONFIG_PRESTERA=m
-CONFIG_PRESTERA_PCI=m
-CONFIG_NET_VENDOR_MELLANOX=y
-CONFIG_MLX4_EN=m
-CONFIG_MLX4_EN_DCB=y
-CONFIG_MLX4_CORE=m
-# CONFIG_MLX4_DEBUG is not set
-CONFIG_MLX4_CORE_GEN2=y
-CONFIG_MLX5_CORE=m
-CONFIG_MLX5_ACCEL=y
-CONFIG_MLX5_FPGA=y
-CONFIG_MLX5_CORE_EN=y
-CONFIG_MLX5_EN_ARFS=y
-CONFIG_MLX5_EN_RXNFC=y
-CONFIG_MLX5_MPFS=y
-CONFIG_MLX5_ESWITCH=y
-CONFIG_MLX5_CLS_ACT=y
-CONFIG_MLX5_TC_SAMPLE=y
-CONFIG_MLX5_CORE_EN_DCB=y
-CONFIG_MLX5_CORE_IPOIB=y
-CONFIG_MLX5_EN_MACSEC=y
-CONFIG_MLX5_IPSEC=y
-CONFIG_MLX5_EN_IPSEC=y
-CONFIG_MLX5_SW_STEERING=y
-CONFIG_MLX5_SF=y
-CONFIG_MLX5_FPGA_IPSEC=y
-CONFIG_MLXSW_CORE=m
-CONFIG_MLXSW_CORE_HWMON=y
-CONFIG_MLXSW_CORE_THERMAL=y
-CONFIG_MLXSW_PCI=m
-CONFIG_MLXSW_I2C=m
-CONFIG_MLXSW_SPECTRUM=m
-CONFIG_MLXSW_SPECTRUM_DCB=y
-CONFIG_MLXSW_MINIMAL=m
-CONFIG_MLXFW=m
-CONFIG_NET_VENDOR_MICREL=y
-CONFIG_KS8842=m
-CONFIG_KS8851=m
-CONFIG_KS8851_MLL=m
-CONFIG_KSZ884X_PCI=m
-CONFIG_NET_VENDOR_MICROCHIP=y
-CONFIG_ENC28J60=m
-# CONFIG_ENC28J60_WRITEVERIFY is not set
-CONFIG_ENCX24J600=m
-CONFIG_LAN743X=m
-CONFIG_NET_VENDOR_MICROSEMI=y
-CONFIG_MSCC_OCELOT_SWITCH_LIB=m
-CONFIG_NET_VENDOR_MYRI=y
-CONFIG_MYRI10GE=m
-CONFIG_FEALNX=m
-CONFIG_NET_VENDOR_NATSEMI=y
-CONFIG_NATSEMI=m
-CONFIG_NS83820=m
-CONFIG_NET_VENDOR_NETERION=y
-CONFIG_S2IO=m
-CONFIG_VXGE=m
-# CONFIG_VXGE_DEBUG_TRACE_ALL is not set
-CONFIG_NET_VENDOR_NETRONOME=y
-CONFIG_NFP=m
-# CONFIG_NFP_APP_FLOWER is not set
-CONFIG_NFP_APP_ABM_NIC=y
-# CONFIG_NFP_DEBUG is not set
-CONFIG_NET_VENDOR_NI=y
-CONFIG_NI_XGE_MANAGEMENT_ENET=m
-CONFIG_NET_VENDOR_8390=y
-CONFIG_PCMCIA_AXNET=m
-CONFIG_NE2K_PCI=m
-CONFIG_PCMCIA_PCNET=m
-CONFIG_NET_VENDOR_NVIDIA=y
-CONFIG_FORCEDETH=m
-CONFIG_NET_VENDOR_OKI=y
-CONFIG_ETHOC=m
-CONFIG_NET_VENDOR_PACKET_ENGINES=y
-CONFIG_HAMACHI=m
-CONFIG_YELLOWFIN=m
-CONFIG_NET_VENDOR_PENSANDO=y
-CONFIG_IONIC=m
-CONFIG_NET_VENDOR_QLOGIC=y
-CONFIG_QLA3XXX=m
-CONFIG_QLCNIC=m
-CONFIG_QLCNIC_SRIOV=y
-CONFIG_QLCNIC_DCB=y
-CONFIG_QLCNIC_HWMON=y
-CONFIG_NETXEN_NIC=m
-CONFIG_QED=m
-CONFIG_QED_LL2=y
-CONFIG_QED_SRIOV=y
-CONFIG_QEDE=m
-CONFIG_QED_RDMA=y
-CONFIG_QED_ISCSI=y
-CONFIG_QED_FCOE=y
-CONFIG_QED_OOO=y
-CONFIG_NET_VENDOR_QUALCOMM=y
-CONFIG_QCOM_EMAC=m
-CONFIG_RMNET=m
-CONFIG_NET_VENDOR_RDC=y
-CONFIG_R6040=m
-CONFIG_NET_VENDOR_REALTEK=y
-CONFIG_ATP=m
-CONFIG_8139CP=m
-CONFIG_8139TOO=m
-# CONFIG_8139TOO_PIO is not set
-CONFIG_8139TOO_TUNE_TWISTER=y
-CONFIG_8139TOO_8129=y
-# CONFIG_8139_OLD_RX_RESET is not set
-CONFIG_R8169=m
-CONFIG_NET_VENDOR_RENESAS=y
-CONFIG_NET_VENDOR_ROCKER=y
-CONFIG_ROCKER=m
-CONFIG_NET_VENDOR_SAMSUNG=y
-CONFIG_SXGBE_ETH=m
-CONFIG_NET_VENDOR_SEEQ=y
-CONFIG_NET_VENDOR_SOLARFLARE=y
-CONFIG_SFC=m
-CONFIG_SFC_MTD=y
-CONFIG_SFC_MCDI_MON=y
-CONFIG_SFC_SRIOV=y
-CONFIG_SFC_MCDI_LOGGING=y
-CONFIG_SFC_FALCON=m
-CONFIG_SFC_FALCON_MTD=y
-CONFIG_NET_VENDOR_SILAN=y
-CONFIG_SC92031=m
-CONFIG_NET_VENDOR_SIS=y
-CONFIG_SIS900=m
-CONFIG_SIS190=m
-CONFIG_NET_VENDOR_SMSC=y
-CONFIG_PCMCIA_SMC91C92=m
-CONFIG_EPIC100=m
-CONFIG_SMSC911X=m
-CONFIG_SMSC9420=m
-# CONFIG_NET_VENDOR_SOCIONEXT is not set
-CONFIG_NET_VENDOR_STMICRO=y
-CONFIG_STMMAC_ETH=m
-# CONFIG_STMMAC_SELFTESTS is not set
-CONFIG_STMMAC_PLATFORM=m
-CONFIG_DWMAC_GENERIC=m
-CONFIG_DWMAC_INTEL=m
-CONFIG_DWMAC_LOONGSON=m
-CONFIG_STMMAC_PCI=m
-CONFIG_NET_VENDOR_SUN=y
-CONFIG_HAPPYMEAL=m
-CONFIG_SUNGEM=m
-CONFIG_CASSINI=m
-CONFIG_NIU=m
-CONFIG_NET_VENDOR_SYNOPSYS=y
-CONFIG_DWC_XLGMAC=m
-CONFIG_DWC_XLGMAC_PCI=m
-CONFIG_NET_VENDOR_TEHUTI=y
-CONFIG_TEHUTI=m
-CONFIG_NET_VENDOR_TI=y
-# CONFIG_TI_CPSW_PHY_SEL is not set
-CONFIG_TLAN=m
-CONFIG_NET_VENDOR_VIA=y
-CONFIG_VIA_RHINE=m
-CONFIG_VIA_RHINE_MMIO=y
-CONFIG_VIA_VELOCITY=m
-CONFIG_NET_VENDOR_WIZNET=y
-CONFIG_WIZNET_W5100=m
-CONFIG_WIZNET_W5300=m
-# CONFIG_WIZNET_BUS_DIRECT is not set
-# CONFIG_WIZNET_BUS_INDIRECT is not set
-CONFIG_WIZNET_BUS_ANY=y
-CONFIG_WIZNET_W5100_SPI=m
-CONFIG_NET_VENDOR_XILINX=y
-CONFIG_XILINX_EMACLITE=m
-CONFIG_XILINX_AXI_EMAC=m
-CONFIG_XILINX_LL_TEMAC=m
-CONFIG_NET_VENDOR_XIRCOM=y
-CONFIG_PCMCIA_XIRC2PS=m
-CONFIG_FDDI=m
-CONFIG_DEFXX=m
-CONFIG_SKFP=m
-CONFIG_HIPPI=y
-CONFIG_ROADRUNNER=m
-CONFIG_ROADRUNNER_LARGE_RINGS=y
-CONFIG_NET_SB1000=m
-CONFIG_PHYLINK=m
-CONFIG_PHYLIB=m
-CONFIG_SWPHY=y
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_FIXED_PHY=m
-CONFIG_SFP=m
-
-#
-# MII PHY device drivers
-#
-CONFIG_AMD_PHY=m
-CONFIG_ADIN_PHY=m
-CONFIG_AQUANTIA_PHY=m
-CONFIG_AX88796B_PHY=m
-CONFIG_BROADCOM_PHY=m
-CONFIG_BCM54140_PHY=m
-CONFIG_BCM7XXX_PHY=m
-CONFIG_BCM84881_PHY=m
-CONFIG_BCM87XX_PHY=m
-CONFIG_BCM_NET_PHYLIB=m
-CONFIG_CICADA_PHY=m
-CONFIG_CORTINA_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_ICPLUS_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_INTEL_XWAY_PHY=m
-CONFIG_LSI_ET1011C_PHY=m
-CONFIG_MARVELL_PHY=m
-CONFIG_MARVELL_10G_PHY=m
-CONFIG_MARVELL_88X2222_PHY=m
-CONFIG_MAXLINEAR_GPHY=m
-CONFIG_MEDIATEK_GE_PHY=m
-CONFIG_MICREL_PHY=m
-CONFIG_MICROCHIP_PHY=m
-CONFIG_MICROCHIP_T1_PHY=m
-CONFIG_MICROSEMI_PHY=m
-CONFIG_MOTORCOMM_PHY=m
-CONFIG_NATIONAL_PHY=m
-CONFIG_NXP_C45_TJA11XX_PHY=m
-CONFIG_NXP_TJA11XX_PHY=m
-CONFIG_AT803X_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_REALTEK_PHY=m
-CONFIG_RENESAS_PHY=m
-# CONFIG_ROCKCHIP_PHY is not set
-CONFIG_SMSC_PHY=m
-CONFIG_STE10XP=m
-CONFIG_TERANETICS_PHY=m
-CONFIG_DP83822_PHY=m
-CONFIG_DP83TC811_PHY=m
-CONFIG_DP83848_PHY=m
-CONFIG_DP83867_PHY=m
-CONFIG_DP83869_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_XILINX_GMII2RGMII=m
-CONFIG_MICREL_KS8995MA=m
-
-#
-# MCTP Device Drivers
-#
-CONFIG_MDIO_DEVICE=m
-CONFIG_MDIO_BUS=m
-CONFIG_FWNODE_MDIO=m
-CONFIG_ACPI_MDIO=m
-CONFIG_MDIO_DEVRES=m
-CONFIG_MDIO_BITBANG=m
-CONFIG_MDIO_BCM_UNIMAC=m
-CONFIG_MDIO_CAVIUM=m
-CONFIG_MDIO_GPIO=m
-CONFIG_MDIO_I2C=m
-CONFIG_MDIO_MVUSB=m
-CONFIG_MDIO_MSCC_MIIM=m
-CONFIG_MDIO_THUNDER=m
-
-#
-# MDIO Multiplexers
-#
-
-#
-# PCS device drivers
-#
-CONFIG_PCS_XPCS=m
-CONFIG_PCS_LYNX=m
-# end of PCS device drivers
-
-CONFIG_PLIP=m
-CONFIG_PPP=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_MPPE=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPPOATM=m
-CONFIG_PPPOE=m
-CONFIG_PPTP=m
-CONFIG_PPPOL2TP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_SLIP=m
-CONFIG_SLHC=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-
-#
-# Host-side USB support is needed for USB Network Adapter support
-#
-CONFIG_USB_NET_DRIVERS=m
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_RTL8152=m
-CONFIG_USB_LAN78XX=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_AX8817X=m
-CONFIG_USB_NET_AX88179_178A=m
-CONFIG_USB_NET_CDCETHER=m
-CONFIG_USB_NET_CDC_EEM=m
-CONFIG_USB_NET_CDC_NCM=m
-CONFIG_USB_NET_HUAWEI_CDC_NCM=m
-CONFIG_USB_NET_CDC_MBIM=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_SR9700=m
-CONFIG_USB_NET_SR9800=m
-CONFIG_USB_NET_SMSC75XX=m
-CONFIG_USB_NET_SMSC95XX=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_NET1080=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_MCS7830=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
-CONFIG_USB_NET_CDC_SUBSET=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_BELKIN=y
-CONFIG_USB_ARMLINUX=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-CONFIG_USB_NET_ZAURUS=m
-CONFIG_USB_NET_CX82310_ETH=m
-CONFIG_USB_NET_KALMIA=m
-CONFIG_USB_NET_QMI_WWAN=m
-CONFIG_USB_HSO=m
-CONFIG_USB_NET_INT51X1=m
-CONFIG_USB_CDC_PHONET=m
-CONFIG_USB_IPHETH=m
-CONFIG_USB_SIERRA_NET=m
-CONFIG_USB_VL600=m
-CONFIG_USB_NET_CH9200=m
-CONFIG_USB_NET_AQC111=m
-CONFIG_USB_RTL8153_ECM=m
-CONFIG_WLAN=y
-CONFIG_WLAN_VENDOR_ADMTEK=y
-CONFIG_ADM8211=m
-CONFIG_ATH_COMMON=m
-CONFIG_WLAN_VENDOR_ATH=y
-# CONFIG_ATH_DEBUG is not set
-CONFIG_ATH5K=m
-# CONFIG_ATH5K_DEBUG is not set
-# CONFIG_ATH5K_TRACER is not set
-CONFIG_ATH5K_PCI=y
-CONFIG_ATH9K_HW=m
-CONFIG_ATH9K_COMMON=m
-CONFIG_ATH9K_BTCOEX_SUPPORT=y
-CONFIG_ATH9K=m
-CONFIG_ATH9K_PCI=y
-CONFIG_ATH9K_AHB=y
-# CONFIG_ATH9K_DEBUGFS is not set
-CONFIG_ATH9K_DYNACK=y
-CONFIG_ATH9K_WOW=y
-CONFIG_ATH9K_RFKILL=y
-CONFIG_ATH9K_CHANNEL_CONTEXT=y
-CONFIG_ATH9K_PCOEM=y
-CONFIG_ATH9K_PCI_NO_EEPROM=m
-CONFIG_ATH9K_HTC=m
-# CONFIG_ATH9K_HTC_DEBUGFS is not set
-CONFIG_ATH9K_HWRNG=y
-CONFIG_CARL9170=m
-CONFIG_CARL9170_LEDS=y
-CONFIG_CARL9170_WPC=y
-# CONFIG_CARL9170_HWRNG is not set
-CONFIG_ATH6KL=m
-CONFIG_ATH6KL_SDIO=m
-CONFIG_ATH6KL_USB=m
-# CONFIG_ATH6KL_DEBUG is not set
-# CONFIG_ATH6KL_TRACING is not set
-CONFIG_AR5523=m
-CONFIG_WIL6210=m
-CONFIG_WIL6210_ISR_COR=y
-CONFIG_WIL6210_TRACING=y
-CONFIG_WIL6210_DEBUGFS=y
-CONFIG_ATH10K=m
-CONFIG_ATH10K_CE=y
-CONFIG_ATH10K_PCI=m
-CONFIG_ATH10K_SDIO=m
-CONFIG_ATH10K_USB=m
-# CONFIG_ATH10K_DEBUG is not set
-# CONFIG_ATH10K_DEBUGFS is not set
-# CONFIG_ATH10K_TRACING is not set
-CONFIG_WCN36XX=m
-# CONFIG_WCN36XX_DEBUGFS is not set
-CONFIG_ATH11K=m
-CONFIG_ATH11K_PCI=m
-# CONFIG_ATH11K_DEBUG is not set
-# CONFIG_ATH11K_TRACING is not set
-CONFIG_WLAN_VENDOR_ATMEL=y
-CONFIG_ATMEL=m
-CONFIG_PCI_ATMEL=m
-CONFIG_PCMCIA_ATMEL=m
-CONFIG_AT76C50X_USB=m
-CONFIG_WLAN_VENDOR_BROADCOM=y
-CONFIG_B43=m
-CONFIG_B43_BCMA=y
-CONFIG_B43_SSB=y
-CONFIG_B43_BUSES_BCMA_AND_SSB=y
-# CONFIG_B43_BUSES_BCMA is not set
-# CONFIG_B43_BUSES_SSB is not set
-CONFIG_B43_PCI_AUTOSELECT=y
-CONFIG_B43_PCICORE_AUTOSELECT=y
-CONFIG_B43_SDIO=y
-CONFIG_B43_BCMA_PIO=y
-CONFIG_B43_PIO=y
-CONFIG_B43_PHY_G=y
-CONFIG_B43_PHY_N=y
-CONFIG_B43_PHY_LP=y
-CONFIG_B43_PHY_HT=y
-CONFIG_B43_LEDS=y
-CONFIG_B43_HWRNG=y
-# CONFIG_B43_DEBUG is not set
-CONFIG_B43LEGACY=m
-CONFIG_B43LEGACY_PCI_AUTOSELECT=y
-CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
-CONFIG_B43LEGACY_LEDS=y
-CONFIG_B43LEGACY_HWRNG=y
-# CONFIG_B43LEGACY_DEBUG is not set
-CONFIG_B43LEGACY_DMA=y
-CONFIG_B43LEGACY_PIO=y
-CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
-# CONFIG_B43LEGACY_DMA_MODE is not set
-# CONFIG_B43LEGACY_PIO_MODE is not set
-CONFIG_BRCMUTIL=m
-CONFIG_BRCMSMAC=m
-CONFIG_BRCMSMAC_LEDS=y
-CONFIG_BRCMFMAC=m
-CONFIG_BRCMFMAC_PROTO_BCDC=y
-CONFIG_BRCMFMAC_PROTO_MSGBUF=y
-CONFIG_BRCMFMAC_SDIO=y
-CONFIG_BRCMFMAC_USB=y
-CONFIG_BRCMFMAC_PCIE=y
-CONFIG_BRCM_TRACING=y
-# CONFIG_BRCMDBG is not set
-CONFIG_WLAN_VENDOR_CISCO=y
-CONFIG_AIRO=m
-CONFIG_AIRO_CS=m
-CONFIG_WLAN_VENDOR_INTEL=y
-CONFIG_IPW2100=m
-CONFIG_IPW2100_MONITOR=y
-# CONFIG_IPW2100_DEBUG is not set
-CONFIG_IPW2200=m
-CONFIG_IPW2200_MONITOR=y
-CONFIG_IPW2200_RADIOTAP=y
-CONFIG_IPW2200_PROMISCUOUS=y
-CONFIG_IPW2200_QOS=y
-# CONFIG_IPW2200_DEBUG is not set
-CONFIG_LIBIPW=m
-# CONFIG_LIBIPW_DEBUG is not set
-CONFIG_IWLEGACY=m
-CONFIG_IWL4965=m
-CONFIG_IWL3945=m
-
-#
-# iwl3945 / iwl4965 Debugging Options
-#
-# CONFIG_IWLEGACY_DEBUG is not set
-# end of iwl3945 / iwl4965 Debugging Options
-
-CONFIG_IWLWIFI=m
-CONFIG_IWLWIFI_LEDS=y
-CONFIG_IWLDVM=m
-CONFIG_IWLMVM=m
-CONFIG_IWLWIFI_OPMODE_MODULAR=y
-# CONFIG_IWLWIFI_BCAST_FILTERING is not set
-CONFIG_IWLMEI=m
-
-#
-# Debugging Options
-#
-# CONFIG_IWLWIFI_DEBUG is not set
-CONFIG_IWLWIFI_DEVICE_TRACING=y
-# end of Debugging Options
-
-CONFIG_WLAN_VENDOR_INTERSIL=y
-CONFIG_HOSTAP=m
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_HOSTAP_PLX=m
-CONFIG_HOSTAP_PCI=m
-CONFIG_HOSTAP_CS=m
-CONFIG_HERMES=m
-CONFIG_HERMES_PRISM=y
-CONFIG_HERMES_CACHE_FW_ON_INIT=y
-CONFIG_PLX_HERMES=m
-CONFIG_TMD_HERMES=m
-CONFIG_NORTEL_HERMES=m
-CONFIG_PCI_HERMES=m
-CONFIG_PCMCIA_HERMES=m
-CONFIG_PCMCIA_SPECTRUM=m
-CONFIG_ORINOCO_USB=m
-CONFIG_P54_COMMON=m
-CONFIG_P54_USB=m
-CONFIG_P54_PCI=m
-CONFIG_P54_SPI=m
-CONFIG_P54_SPI_DEFAULT_EEPROM=y
-CONFIG_P54_LEDS=y
-CONFIG_WLAN_VENDOR_MARVELL=y
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_USB=m
-CONFIG_LIBERTAS_CS=m
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_LIBERTAS_SPI=m
-# CONFIG_LIBERTAS_DEBUG is not set
-CONFIG_LIBERTAS_MESH=y
-CONFIG_LIBERTAS_THINFIRM=m
-# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
-CONFIG_LIBERTAS_THINFIRM_USB=m
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
-CONFIG_MWIFIEX_PCIE=m
-CONFIG_MWIFIEX_USB=m
-CONFIG_MWL8K=m
-CONFIG_WLAN_VENDOR_MEDIATEK=y
-CONFIG_MT7601U=m
-CONFIG_MT76_CORE=m
-CONFIG_MT76_LEDS=y
-CONFIG_MT76_USB=m
-CONFIG_MT76_SDIO=m
-CONFIG_MT76x02_LIB=m
-CONFIG_MT76x02_USB=m
-CONFIG_MT76_CONNAC_LIB=m
-CONFIG_MT76x0_COMMON=m
-CONFIG_MT76x0U=m
-CONFIG_MT76x0E=m
-CONFIG_MT76x2_COMMON=m
-CONFIG_MT76x2E=m
-CONFIG_MT76x2U=m
-CONFIG_MT7603E=m
-CONFIG_MT7615_COMMON=m
-CONFIG_MT7615E=m
-CONFIG_MT7663_USB_SDIO_COMMON=m
-CONFIG_MT7663U=m
-CONFIG_MT7663S=m
-CONFIG_MT7915E=m
-CONFIG_MT7986_WMAC=y
-CONFIG_MT7921_COMMON=m
-CONFIG_MT7921E=m
-CONFIG_MT7921S=m
-CONFIG_MT7921U=m
-CONFIG_WLAN_VENDOR_MICROCHIP=y
-CONFIG_WILC1000=m
-CONFIG_WILC1000_SDIO=m
-CONFIG_WILC1000_SPI=m
-# CONFIG_WILC1000_HW_OOB_INTR is not set
-CONFIG_WLAN_VENDOR_RALINK=y
-CONFIG_RT2X00=m
-CONFIG_RT2400PCI=m
-CONFIG_RT2500PCI=m
-CONFIG_RT61PCI=m
-CONFIG_RT2800PCI=m
-CONFIG_RT2800PCI_RT33XX=y
-CONFIG_RT2800PCI_RT35XX=y
-CONFIG_RT2800PCI_RT53XX=y
-CONFIG_RT2800PCI_RT3290=y
-CONFIG_RT2500USB=m
-CONFIG_RT73USB=m
-CONFIG_RT2800USB=m
-CONFIG_RT2800USB_RT33XX=y
-CONFIG_RT2800USB_RT35XX=y
-CONFIG_RT2800USB_RT3573=y
-CONFIG_RT2800USB_RT53XX=y
-CONFIG_RT2800USB_RT55XX=y
-CONFIG_RT2800USB_UNKNOWN=y
-CONFIG_RT2800_LIB=m
-CONFIG_RT2800_LIB_MMIO=m
-CONFIG_RT2X00_LIB_MMIO=m
-CONFIG_RT2X00_LIB_PCI=m
-CONFIG_RT2X00_LIB_USB=m
-CONFIG_RT2X00_LIB=m
-CONFIG_RT2X00_LIB_FIRMWARE=y
-CONFIG_RT2X00_LIB_CRYPTO=y
-CONFIG_RT2X00_LIB_LEDS=y
-# CONFIG_RT2X00_DEBUG is not set
-CONFIG_WLAN_VENDOR_REALTEK=y
-CONFIG_RTL8180=m
-CONFIG_RTL8187=m
-CONFIG_RTL8187_LEDS=y
-CONFIG_RTL_CARDS=m
-CONFIG_RTL8192CE=m
-CONFIG_RTL8192SE=m
-CONFIG_RTL8192DE=m
-CONFIG_RTL8723AE=m
-CONFIG_RTL8723BE=m
-CONFIG_RTL8188EE=m
-CONFIG_RTL8192EE=m
-CONFIG_RTL8821AE=m
-CONFIG_RTL8192CU=m
-CONFIG_RTLWIFI=m
-CONFIG_RTLWIFI_PCI=m
-CONFIG_RTLWIFI_USB=m
-# CONFIG_RTLWIFI_DEBUG is not set
-CONFIG_RTL8192C_COMMON=m
-CONFIG_RTL8723_COMMON=m
-CONFIG_RTLBTCOEXIST=m
-CONFIG_RTL8XXXU=m
-CONFIG_RTL8XXXU_UNTESTED=y
-CONFIG_RTW88=m
-CONFIG_RTW88_CORE=m
-CONFIG_RTW88_PCI=m
-CONFIG_RTW88_8822B=m
-CONFIG_RTW88_8822C=m
-CONFIG_RTW88_8723D=m
-CONFIG_RTW88_8821C=m
-CONFIG_RTW88_8822BE=m
-CONFIG_RTW88_8822CE=m
-CONFIG_RTW88_8723DE=m
-CONFIG_RTW88_8821CE=m
-# CONFIG_RTW88_DEBUG is not set
-# CONFIG_RTW88_DEBUGFS is not set
-CONFIG_RTW89=m
-CONFIG_RTW89_CORE=m
-CONFIG_RTW89_PCI=m
-CONFIG_RTW89_8852AE=m
-CONFIG_RTW89_DEBUG=y
-# CONFIG_RTW89_DEBUGMSG is not set
-CONFIG_RTW89_DEBUGFS=y
-CONFIG_WLAN_VENDOR_RSI=y
-CONFIG_RSI_91X=m
-# CONFIG_RSI_DEBUGFS is not set
-CONFIG_RSI_SDIO=m
-CONFIG_RSI_USB=m
-CONFIG_RSI_COEX=y
-CONFIG_WLAN_VENDOR_ST=y
-CONFIG_CW1200=m
-CONFIG_CW1200_WLAN_SDIO=m
-CONFIG_CW1200_WLAN_SPI=m
-CONFIG_WLAN_VENDOR_TI=y
-CONFIG_WL1251=m
-CONFIG_WL1251_SPI=m
-CONFIG_WL1251_SDIO=m
-CONFIG_WL12XX=m
-CONFIG_WL18XX=m
-CONFIG_WLCORE=m
-CONFIG_WLCORE_SDIO=m
-CONFIG_WILINK_PLATFORM_DATA=y
-CONFIG_WLAN_VENDOR_ZYDAS=y
-CONFIG_USB_ZD1201=m
-CONFIG_ZD1211RW=m
-# CONFIG_ZD1211RW_DEBUG is not set
-CONFIG_WLAN_VENDOR_QUANTENNA=y
-CONFIG_QTNFMAC=m
-CONFIG_QTNFMAC_PCIE=m
-CONFIG_PCMCIA_RAYCS=m
-CONFIG_PCMCIA_WL3501=m
-# CONFIG_MAC80211_HWSIM is not set
-CONFIG_USB_NET_RNDIS_WLAN=m
-CONFIG_VIRT_WIFI=m
-CONFIG_WAN=y
-CONFIG_LANMEDIA=m
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_PCI200SYN=m
-CONFIG_WANXL=m
-CONFIG_PC300TOO=m
-CONFIG_FARSYNC=m
-CONFIG_LAPBETHER=m
-CONFIG_IEEE802154_DRIVERS=m
-CONFIG_IEEE802154_FAKELB=m
-CONFIG_IEEE802154_AT86RF230=m
-# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set
-CONFIG_IEEE802154_MRF24J40=m
-CONFIG_IEEE802154_CC2520=m
-CONFIG_IEEE802154_ATUSB=m
-CONFIG_IEEE802154_ADF7242=m
-CONFIG_IEEE802154_CA8210=m
-# CONFIG_IEEE802154_CA8210_DEBUGFS is not set
-CONFIG_IEEE802154_MCR20A=m
-CONFIG_IEEE802154_HWSIM=m
-
-#
-# Wireless WAN
-#
-CONFIG_WWAN=y
-CONFIG_WWAN_HWSIM=m
-CONFIG_MHI_WWAN_CTRL=m
-CONFIG_IOSM=m
-# CONFIG_TEST_MAPLE_TREE is not set
-CONFIG_MHI_WWAN_MBIM=m
-CONFIG_QCOM_BAM_DMUX=m
-CONFIG_RPMSG_WWAN_CTRL=m
-# end of Wireless WAN
-
-CONFIG_VMXNET3=m
-CONFIG_FUJITSU_ES=m
-CONFIG_USB4_NET=m
-CONFIG_HYPERV_NET=m
-CONFIG_NETDEVSIM=m
-CONFIG_NET_FAILOVER=m
-CONFIG_ISDN=y
-CONFIG_ISDN_CAPI=y
-CONFIG_CAPI_TRACE=y
-CONFIG_ISDN_CAPI_MIDDLEWARE=y
-CONFIG_MISDN=m
-CONFIG_MISDN_DSP=m
-CONFIG_MISDN_L1OIP=m
-
-#
-# mISDN hardware drivers
-#
-CONFIG_MISDN_HFCPCI=m
-CONFIG_MISDN_HFCMULTI=m
-CONFIG_MISDN_HFCUSB=m
-CONFIG_MISDN_AVMFRITZ=m
-CONFIG_MISDN_SPEEDFAX=m
-CONFIG_MISDN_INFINEON=m
-CONFIG_MISDN_W6692=m
-CONFIG_MISDN_NETJET=m
-CONFIG_MISDN_HDLC=m
-CONFIG_MISDN_IPAC=m
-CONFIG_MISDN_ISAR=m
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_LEDS=m
-CONFIG_INPUT_FF_MEMLESS=m
-CONFIG_INPUT_SPARSEKMAP=m
-CONFIG_INPUT_MATRIXKMAP=m
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ADC=m
-CONFIG_KEYBOARD_ADP5588=m
-CONFIG_KEYBOARD_ADP5589=m
-CONFIG_KEYBOARD_APPLESPI=m
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_KEYBOARD_QT1050=m
-CONFIG_KEYBOARD_QT1070=m
-CONFIG_KEYBOARD_QT2160=m
-CONFIG_KEYBOARD_DLINK_DIR685=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_GPIO=m
-CONFIG_KEYBOARD_GPIO_POLLED=m
-CONFIG_KEYBOARD_TCA6416=m
-CONFIG_KEYBOARD_TCA8418=m
-CONFIG_KEYBOARD_MATRIX=m
-CONFIG_KEYBOARD_LM8323=m
-CONFIG_KEYBOARD_LM8333=m
-CONFIG_KEYBOARD_MAX7359=m
-CONFIG_KEYBOARD_MCS=m
-CONFIG_KEYBOARD_MPR121=m
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_OPENCORES=m
-CONFIG_KEYBOARD_PINEPHONE=m
-CONFIG_KEYBOARD_SAMSUNG=m
-CONFIG_KEYBOARD_STOWAWAY=m
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_IQS62X=m
-CONFIG_KEYBOARD_TM2_TOUCHKEY=m
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_KEYBOARD_CROS_EC=m
-CONFIG_KEYBOARD_MTK_PMIC=m
-CONFIG_KEYBOARD_CYPRESS_SF=m
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_BYD=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
-CONFIG_MOUSE_PS2_CYPRESS=y
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-CONFIG_MOUSE_PS2_ELANTECH=y
-CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y
-CONFIG_MOUSE_PS2_SENTELIC=y
-CONFIG_MOUSE_PS2_TOUCHKIT=y
-CONFIG_MOUSE_PS2_FOCALTECH=y
-# CONFIG_MOUSE_PS2_VMMOUSE is not set
-CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_APPLETOUCH=m
-CONFIG_MOUSE_BCM5974=m
-CONFIG_MOUSE_CYAPA=m
-CONFIG_MOUSE_ELAN_I2C=m
-CONFIG_MOUSE_ELAN_I2C_I2C=y
-CONFIG_MOUSE_ELAN_I2C_SMBUS=y
-CONFIG_MOUSE_VSXXXAA=m
-CONFIG_MOUSE_GPIO=m
-CONFIG_MOUSE_SYNAPTICS_I2C=m
-CONFIG_MOUSE_SYNAPTICS_USB=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADC=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=m
-CONFIG_JOYSTICK_IFORCE_232=m
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_TWIDJOY=m
-CONFIG_JOYSTICK_ZHENHUA=m
-CONFIG_JOYSTICK_DB9=m
-CONFIG_JOYSTICK_GAMECON=m
-CONFIG_JOYSTICK_TURBOGRAFX=m
-CONFIG_JOYSTICK_AS5011=m
-# CONFIG_JOYSTICK_JOYDUMP is not set
-CONFIG_JOYSTICK_XPAD=m
-CONFIG_JOYSTICK_XPAD_FF=y
-CONFIG_JOYSTICK_XPAD_LEDS=y
-CONFIG_JOYSTICK_WALKERA0701=m
-CONFIG_JOYSTICK_PSXPAD_SPI=m
-CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
-CONFIG_JOYSTICK_PXRC=m
-CONFIG_JOYSTICK_QWIIC=m
-CONFIG_JOYSTICK_FSIA6B=m
-CONFIG_INPUT_TABLET=y
-CONFIG_TABLET_USB_ACECAD=m
-CONFIG_TABLET_USB_AIPTEK=m
-CONFIG_TABLET_USB_HANWANG=m
-CONFIG_TABLET_USB_KBTAB=m
-CONFIG_TABLET_USB_PEGASUS=m
-CONFIG_TABLET_SERIAL_WACOM4=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=m
-CONFIG_TOUCHSCREEN_AD7877=m
-CONFIG_TOUCHSCREEN_AD7879=m
-CONFIG_TOUCHSCREEN_AD7879_I2C=m
-CONFIG_TOUCHSCREEN_AD7879_SPI=m
-CONFIG_TOUCHSCREEN_ADC=m
-CONFIG_TOUCHSCREEN_ATMEL_MXT=m
-# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set
-CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
-CONFIG_TOUCHSCREEN_BU21013=m
-CONFIG_TOUCHSCREEN_BU21029=m
-CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m
-CONFIG_TOUCHSCREEN_CY8CTMA140=m
-CONFIG_TOUCHSCREEN_CY8CTMG110=m
-CONFIG_TOUCHSCREEN_CYTTSP_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP_I2C=m
-CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
-CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
-CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
-CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
-CONFIG_TOUCHSCREEN_DA9052=m
-CONFIG_TOUCHSCREEN_DYNAPRO=m
-CONFIG_TOUCHSCREEN_HAMPSHIRE=m
-CONFIG_TOUCHSCREEN_EETI=m
-CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m
-CONFIG_TOUCHSCREEN_EXC3000=m
-CONFIG_TOUCHSCREEN_FUJITSU=m
-CONFIG_TOUCHSCREEN_GOODIX=m
-CONFIG_TOUCHSCREEN_HIDEEP=m
-CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
-CONFIG_TOUCHSCREEN_ILI210X=m
-CONFIG_TOUCHSCREEN_ILITEK=m
-CONFIG_TOUCHSCREEN_S6SY761=m
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_TOUCHSCREEN_EKTF2127=m
-CONFIG_TOUCHSCREEN_ELAN=m
-CONFIG_TOUCHSCREEN_ELO=m
-CONFIG_TOUCHSCREEN_WACOM_W8001=m
-CONFIG_TOUCHSCREEN_WACOM_I2C=m
-CONFIG_TOUCHSCREEN_MAX11801=m
-CONFIG_TOUCHSCREEN_MCS5000=m
-CONFIG_TOUCHSCREEN_MMS114=m
-CONFIG_TOUCHSCREEN_MELFAS_MIP4=m
-CONFIG_TOUCHSCREEN_MSG2638=m
-CONFIG_TOUCHSCREEN_MTOUCH=m
-CONFIG_TOUCHSCREEN_IMAGIS=m
-CONFIG_TOUCHSCREEN_INEXIO=m
-CONFIG_TOUCHSCREEN_MK712=m
-CONFIG_TOUCHSCREEN_PENMOUNT=m
-CONFIG_TOUCHSCREEN_EDT_FT5X06=m
-CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
-CONFIG_TOUCHSCREEN_TOUCHWIN=m
-CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m
-CONFIG_TOUCHSCREEN_UCB1400=m
-CONFIG_TOUCHSCREEN_PIXCIR=m
-CONFIG_TOUCHSCREEN_WDT87XX_I2C=m
-CONFIG_TOUCHSCREEN_WM831X=m
-CONFIG_TOUCHSCREEN_WM97XX=m
-CONFIG_TOUCHSCREEN_WM9705=y
-CONFIG_TOUCHSCREEN_WM9712=y
-CONFIG_TOUCHSCREEN_WM9713=y
-CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-CONFIG_TOUCHSCREEN_MC13783=m
-CONFIG_TOUCHSCREEN_USB_EGALAX=y
-CONFIG_TOUCHSCREEN_USB_PANJIT=y
-CONFIG_TOUCHSCREEN_USB_3M=y
-CONFIG_TOUCHSCREEN_USB_ITM=y
-CONFIG_TOUCHSCREEN_USB_ETURBO=y
-CONFIG_TOUCHSCREEN_USB_GUNZE=y
-CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y
-CONFIG_TOUCHSCREEN_USB_IRTOUCH=y
-CONFIG_TOUCHSCREEN_USB_IDEALTEK=y
-CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y
-CONFIG_TOUCHSCREEN_USB_GOTOP=y
-CONFIG_TOUCHSCREEN_USB_JASTEC=y
-CONFIG_TOUCHSCREEN_USB_ELO=y
-CONFIG_TOUCHSCREEN_USB_E2I=y
-CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y
-CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y
-CONFIG_TOUCHSCREEN_USB_NEXIO=y
-CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y
-CONFIG_TOUCHSCREEN_TOUCHIT213=m
-CONFIG_TOUCHSCREEN_TSC_SERIO=m
-CONFIG_TOUCHSCREEN_TSC200X_CORE=m
-CONFIG_TOUCHSCREEN_TSC2004=m
-CONFIG_TOUCHSCREEN_TSC2005=m
-CONFIG_TOUCHSCREEN_TSC2007=m
-CONFIG_TOUCHSCREEN_TSC2007_IIO=y
-CONFIG_TOUCHSCREEN_PCAP=m
-CONFIG_TOUCHSCREEN_RM_TS=m
-CONFIG_TOUCHSCREEN_SILEAD=m
-CONFIG_TOUCHSCREEN_SIS_I2C=m
-CONFIG_TOUCHSCREEN_ST1232=m
-CONFIG_TOUCHSCREEN_STMFTS=m
-CONFIG_TOUCHSCREEN_SUR40=m
-CONFIG_TOUCHSCREEN_SURFACE3_SPI=m
-CONFIG_TOUCHSCREEN_SX8654=m
-CONFIG_TOUCHSCREEN_TPS6507X=m
-CONFIG_TOUCHSCREEN_ZET6223=m
-CONFIG_TOUCHSCREEN_ZFORCE=m
-CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
-CONFIG_TOUCHSCREEN_ROHM_BU21023=m
-CONFIG_TOUCHSCREEN_IQS5XX=m
-CONFIG_TOUCHSCREEN_ZINITIX=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_88PM80X_ONKEY=m
-CONFIG_INPUT_AD714X=m
-CONFIG_INPUT_AD714X_I2C=m
-CONFIG_INPUT_AD714X_SPI=m
-CONFIG_INPUT_ARIZONA_HAPTICS=m
-CONFIG_INPUT_ATC260X_ONKEY=m
-CONFIG_INPUT_BMA150=m
-CONFIG_INPUT_E3X0_BUTTON=m
-CONFIG_INPUT_PCSPKR=m
-CONFIG_INPUT_MAX77693_HAPTIC=m
-CONFIG_INPUT_MC13783_PWRBUTTON=m
-CONFIG_INPUT_MMA8450=m
-CONFIG_INPUT_APANEL=m
-CONFIG_INPUT_GPIO_BEEPER=m
-CONFIG_INPUT_GPIO_DECODER=m
-CONFIG_INPUT_GPIO_VIBRA=m
-CONFIG_INPUT_ATLAS_BTNS=m
-CONFIG_INPUT_ATI_REMOTE2=m
-CONFIG_INPUT_KEYSPAN_REMOTE=m
-CONFIG_INPUT_KXTJ9=m
-CONFIG_INPUT_POWERMATE=m
-CONFIG_INPUT_YEALINK=m
-CONFIG_INPUT_CM109=m
-CONFIG_INPUT_REGULATOR_HAPTIC=m
-CONFIG_INPUT_RETU_PWRBUTTON=m
-CONFIG_INPUT_AXP20X_PEK=m
-CONFIG_INPUT_UINPUT=m
-CONFIG_INPUT_PCF50633_PMU=m
-CONFIG_INPUT_PCF8574=m
-CONFIG_INPUT_PWM_BEEPER=m
-CONFIG_INPUT_PWM_VIBRA=m
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-CONFIG_INPUT_DA7280_HAPTICS=m
-CONFIG_INPUT_DA9052_ONKEY=m
-CONFIG_INPUT_DA9063_ONKEY=m
-CONFIG_INPUT_WM831X_ON=m
-CONFIG_INPUT_PCAP=m
-CONFIG_INPUT_ADXL34X=m
-CONFIG_INPUT_IBM_PANEL=m
-CONFIG_INPUT_ADXL34X_I2C=m
-CONFIG_INPUT_ADXL34X_SPI=m
-CONFIG_INPUT_IMS_PCU=m
-CONFIG_INPUT_IQS269A=m
-CONFIG_INPUT_IQS626A=m
-CONFIG_INPUT_CMA3000=m
-CONFIG_INPUT_CMA3000_I2C=m
-CONFIG_INPUT_IDEAPAD_SLIDEBAR=m
-CONFIG_INPUT_SOC_BUTTON_ARRAY=m
-CONFIG_INPUT_DRV260X_HAPTICS=m
-CONFIG_INPUT_DRV2665_HAPTICS=m
-CONFIG_INPUT_DRV2667_HAPTICS=m
-CONFIG_INPUT_RAVE_SP_PWRBUTTON=m
-CONFIG_INPUT_RT5120_PWRKEY=m
-CONFIG_RMI4_CORE=m
-CONFIG_RMI4_I2C=m
-CONFIG_RMI4_SPI=m
-CONFIG_RMI4_SMB=m
-CONFIG_RMI4_F03=y
-CONFIG_RMI4_F03_SERIO=m
-CONFIG_RMI4_2D_SENSOR=y
-CONFIG_RMI4_F11=y
-CONFIG_RMI4_F12=y
-CONFIG_RMI4_F30=y
-CONFIG_RMI4_F34=y
-CONFIG_RMI4_F3A=y
-CONFIG_RMI4_F54=y
-CONFIG_RMI4_F55=y
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=m
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_SERIO_I8042=y
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_CT82C710=m
-CONFIG_SERIO_PARKBD=m
-CONFIG_SERIO_PCIPS2=m
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_RAW=m
-CONFIG_SERIO_ALTERA_PS2=m
-CONFIG_SERIO_PS2MULT=m
-CONFIG_SERIO_ARC_PS2=m
-CONFIG_HYPERV_KEYBOARD=m
-CONFIG_SERIO_GPIO_PS2=m
-CONFIG_USERIO=m
-CONFIG_GAMEPORT=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_GAMEPORT_EMU10K1=m
-CONFIG_GAMEPORT_FM801=m
-# end of Hardware I/O ports
-# end of Input device support
-
-#
-# Character devices
-#
-CONFIG_TTY=y
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LDISC_AUTOLOAD=y
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_EARLYCON=y
-CONFIG_SERIAL_8250=y
-# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-CONFIG_SERIAL_8250_PNP=y
-# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
-CONFIG_SERIAL_8250_FINTEK=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_DMA=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_CS=m
-CONFIG_SERIAL_8250_MEN_MCB=m
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_DETECT_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_DW=m
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_8250_LPSS=y
-CONFIG_SERIAL_8250_MID=y
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_MAX3100=m
-CONFIG_SERIAL_MAX310X=y
-CONFIG_SERIAL_UARTLITE=m
-CONFIG_SERIAL_UARTLITE_NR_UARTS=1
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_JSM=m
-CONFIG_SERIAL_LANTIQ=m
-CONFIG_SERIAL_SCCNXP=m
-CONFIG_SERIAL_SC16IS7XX_CORE=m
-CONFIG_SERIAL_SC16IS7XX=m
-CONFIG_SERIAL_SC16IS7XX_I2C=y
-CONFIG_SERIAL_SC16IS7XX_SPI=y
-CONFIG_SERIAL_BCM63XX=m
-CONFIG_SERIAL_ALTERA_JTAGUART=m
-CONFIG_SERIAL_ALTERA_UART=m
-CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
-CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
-CONFIG_SERIAL_ARC=m
-CONFIG_SERIAL_ARC_NR_PORTS=1
-CONFIG_SERIAL_RP2=m
-CONFIG_SERIAL_RP2_NR_UARTS=32
-CONFIG_SERIAL_FSL_LPUART=m
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_FSL_LINFLEXUART=m
-CONFIG_SERIAL_MEN_Z135=m
-CONFIG_SERIAL_SPRD=m
-# end of Serial drivers
-
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_MOXA_INTELLIO=m
-CONFIG_MOXA_SMARTIO=m
-CONFIG_SYNCLINK_GT=m
-CONFIG_N_HDLC=m
-CONFIG_N_GSM=m
-CONFIG_NOZOMI=m
-CONFIG_NULL_TTY=m
-CONFIG_HVC_DRIVER=y
-CONFIG_RPMSG_TTY=m
-CONFIG_SERIAL_DEV_BUS=m
-# CONFIG_TTY_PRINTK is not set
-CONFIG_PRINTER=m
-CONFIG_LP_CONSOLE=y
-CONFIG_PPDEV=m
-CONFIG_VIRTIO_CONSOLE=m
-CONFIG_IPMI_HANDLER=m
-CONFIG_IPMI_DMI_DECODE=y
-CONFIG_IPMI_PLAT_DATA=y
-CONFIG_IPMI_PANIC_EVENT=y
-CONFIG_IPMI_PANIC_STRING=y
-CONFIG_IPMI_DEVICE_INTERFACE=m
-CONFIG_IPMI_SI=m
-CONFIG_IPMI_SSIF=m
-CONFIG_IPMI_IPMB=m
-CONFIG_IPMI_WATCHDOG=m
-CONFIG_IPMI_POWEROFF=m
-CONFIG_NPCM7XX_KCS_IPMI_BMC=m
-CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m
-CONFIG_IPMI_KCS_BMC_SERIO=m
-CONFIG_IPMB_DEVICE_INTERFACE=m
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=y
-CONFIG_HW_RANDOM_INTEL=y
-CONFIG_HW_RANDOM_AMD=y
-CONFIG_HW_RANDOM_BA431=y
-CONFIG_HW_RANDOM_VIA=y
-# CONFIG_HW_RANDOM_VIRTIO is not set
-CONFIG_HW_RANDOM_XIPHERA=m
-CONFIG_APPLICOM=m
-
-#
-# PCMCIA character devices
-#
-CONFIG_SYNCLINK_CS=m
-CONFIG_CARDMAN_4000=m
-CONFIG_CARDMAN_4040=m
-CONFIG_SCR24X=m
-CONFIG_IPWIRELESS=m
-# end of PCMCIA character devices
-
-CONFIG_MWAVE=m
-CONFIG_DEVMEM=y
-CONFIG_NVRAM=m
-CONFIG_DEVPORT=y
-CONFIG_HPET=y
-CONFIG_HPET_MMAP=y
-CONFIG_HPET_MMAP_DEFAULT=y
-CONFIG_HANGCHECK_TIMER=m
-CONFIG_TCG_TPM=m
-CONFIG_HW_RANDOM_TPM=y
-CONFIG_TCG_TIS_CORE=m
-CONFIG_TCG_TIS=m
-CONFIG_TCG_TIS_SPI=m
-# CONFIG_TCG_TIS_SPI_CR50 is not set
-CONFIG_TCG_TIS_I2C_CR50=m
-CONFIG_TCG_TIS_I2C_ATMEL=m
-CONFIG_TCG_TIS_I2C_INFINEON=m
-CONFIG_TCG_TIS_I2C_NUVOTON=m
-CONFIG_TCG_NSC=m
-CONFIG_TCG_ATMEL=m
-CONFIG_TCG_INFINEON=m
-CONFIG_TCG_CRB=m
-CONFIG_TCG_VTPM_PROXY=m
-CONFIG_TCG_TIS_ST33ZP24=m
-CONFIG_TCG_TIS_ST33ZP24_I2C=m
-CONFIG_TCG_TIS_ST33ZP24_SPI=m
-CONFIG_TELCLOCK=m
-CONFIG_XILLYBUS_CLASS=m
-CONFIG_XILLYBUS=m
-CONFIG_XILLYBUS_PCIE=m
-CONFIG_XILLYUSB=m
-CONFIG_RANDOM_TRUST_CPU=y
-CONFIG_RANDOM_TRUST_BOOTLOADER=y
-# end of Character devices
-
-#
-# I2C support
-#
-CONFIG_I2C=m
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_MUX=m
-
-#
-# Multiplexer I2C Chip support
-#
-CONFIG_I2C_MUX_GPIO=m
-CONFIG_I2C_MUX_LTC4306=m
-CONFIG_I2C_MUX_PCA9541=m
-CONFIG_I2C_MUX_PCA954x=m
-CONFIG_I2C_MUX_REG=m
-CONFIG_I2C_MUX_MLXCPLD=m
-# end of Multiplexer I2C Chip support
-
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_SMBUS=m
-CONFIG_I2C_ALGOBIT=m
-CONFIG_I2C_ALGOPCA=m
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# PC SMBus host controller drivers
-#
-CONFIG_I2C_ALI1535=m
-CONFIG_I2C_ALI1563=m
-CONFIG_I2C_ALI15X3=m
-CONFIG_I2C_AMD756=m
-CONFIG_I2C_AMD756_S4882=m
-CONFIG_I2C_AMD8111=m
-CONFIG_I2C_AMD_MP2=m
-CONFIG_I2C_I801=m
-CONFIG_I2C_ISCH=m
-CONFIG_I2C_ISMT=m
-CONFIG_I2C_PIIX4=m
-CONFIG_I2C_NFORCE2=m
-CONFIG_I2C_NFORCE2_S4985=m
-CONFIG_I2C_NVIDIA_GPU=m
-CONFIG_I2C_SIS5595=m
-CONFIG_I2C_SIS630=m
-CONFIG_I2C_SIS96X=m
-CONFIG_I2C_VIA=m
-CONFIG_I2C_VIAPRO=m
-
-#
-# ACPI drivers
-#
-CONFIG_I2C_SCMI=m
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-CONFIG_I2C_CBUS_GPIO=m
-CONFIG_I2C_DESIGNWARE_CORE=m
-# CONFIG_I2C_DESIGNWARE_SLAVE is not set
-CONFIG_I2C_DESIGNWARE_PLATFORM=m
-CONFIG_I2C_DESIGNWARE_AMDPSP=y
-# CONFIG_I2C_DESIGNWARE_BAYTRAIL is not set
-CONFIG_I2C_DESIGNWARE_PCI=m
-CONFIG_I2C_EMEV2=m
-CONFIG_I2C_GPIO=m
-# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
-CONFIG_I2C_KEMPLD=m
-CONFIG_I2C_OCORES=m
-CONFIG_I2C_PCA_PLATFORM=m
-CONFIG_I2C_SIMTEC=m
-CONFIG_I2C_XILINX=m
-
-#
-# External I2C/SMBus adapter drivers
-#
-CONFIG_I2C_DIOLAN_U2C=m
-CONFIG_I2C_DLN2=m
-CONFIG_I2C_CP2615=m
-CONFIG_I2C_PARPORT=m
-CONFIG_I2C_PCI1XXXX=m
-CONFIG_I2C_ROBOTFUZZ_OSIF=m
-CONFIG_I2C_TAOS_EVM=m
-CONFIG_I2C_TINY_USB=m
-CONFIG_I2C_VIPERBOARD=m
-
-#
-# Other I2C/SMBus bus drivers
-#
-CONFIG_I2C_MLXCPLD=m
-CONFIG_I2C_CROS_EC_TUNNEL=m
-CONFIG_I2C_VIRTIO=m
-# end of I2C Hardware Bus support
-
-# CONFIG_I2C_STUB is not set
-CONFIG_I2C_SLAVE=y
-CONFIG_I2C_SLAVE_EEPROM=m
-CONFIG_I2C_SLAVE_TESTUNIT=m
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# end of I2C support
-
-CONFIG_I3C=m
-CONFIG_CDNS_I3C_MASTER=m
-CONFIG_DW_I3C_MASTER=m
-CONFIG_SVC_I3C_MASTER=m
-CONFIG_MIPI_I3C_HCI=m
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-
-#
-# SPI Master Controller Drivers
-#
-CONFIG_SPI_ALTERA=m
-CONFIG_SPI_ALTERA_CORE=m
-CONFIG_SPI_ALTERA_DFL=m
-CONFIG_SPI_AXI_SPI_ENGINE=m
-CONFIG_SPI_BITBANG=m
-CONFIG_SPI_BUTTERFLY=m
-CONFIG_SPI_CADENCE=m
-CONFIG_SPI_DESIGNWARE=m
-# CONFIG_SPI_DW_DMA is not set
-CONFIG_SPI_DW_PCI=m
-CONFIG_SPI_DW_MMIO=m
-CONFIG_SPI_DLN2=m
-CONFIG_SPI_NXP_FLEXSPI=m
-CONFIG_SPI_GPIO=m
-CONFIG_SPI_INTEL_PCI=m
-CONFIG_SPI_INTEL_PLATFORM=m
-CONFIG_SPI_LM70_LLP=m
-CONFIG_SPI_LANTIQ_SSC=m
-CONFIG_SPI_OC_TINY=m
-CONFIG_SPI_PXA2XX=m
-CONFIG_SPI_PXA2XX_PCI=m
-# CONFIG_SPI_ROCKCHIP is not set
-CONFIG_SPI_SC18IS602=m
-CONFIG_SPI_SIFIVE=m
-CONFIG_SPI_MXIC=m
-CONFIG_SPI_XCOMM=m
-CONFIG_SPI_XILINX=m
-CONFIG_SPI_ZYNQMP_GQSPI=m
-CONFIG_SPI_AMD=m
-
-#
-# SPI Multiplexer support
-#
-CONFIG_SPI_MUX=m
-
-#
-# SPI Protocol Masters
-#
-CONFIG_SPI_SPIDEV=m
-CONFIG_SPI_LOOPBACK_TEST=m
-CONFIG_SPI_TLE62X0=m
-CONFIG_SPI_SLAVE=y
-CONFIG_SPI_SLAVE_TIME=m
-CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPMI=m
-CONFIG_SPMI_HISI3670=m
-CONFIG_HSI=m
-CONFIG_HSI_BOARDINFO=y
-
-#
-# HSI controllers
-#
-
-#
-# HSI clients
-#
-CONFIG_HSI_CHAR=m
-CONFIG_PPS=y
-# CONFIG_PPS_DEBUG is not set
-
-#
-# PPS clients support
-#
-# CONFIG_PPS_CLIENT_KTIMER is not set
-CONFIG_PPS_CLIENT_LDISC=m
-CONFIG_PPS_CLIENT_PARPORT=m
-CONFIG_PPS_CLIENT_GPIO=m
-
-#
-# PPS generators support
-#
-
-#
-# PTP clock support
-#
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_DP83640_PHY=m
-CONFIG_PTP_1588_CLOCK_INES=m
-CONFIG_PTP_1588_CLOCK_KVM=m
-CONFIG_PTP_1588_CLOCK_IDT82P33=m
-CONFIG_PTP_1588_CLOCK_IDTCM=m
-CONFIG_PTP_1588_CLOCK_VMW=m
-CONFIG_PTP_1588_CLOCK_OCP=m
-# end of PTP clock support
-
-CONFIG_PINCTRL=y
-CONFIG_PINMUX=y
-CONFIG_PINCONF=y
-CONFIG_GENERIC_PINCONF=y
-# CONFIG_DEBUG_PINCTRL is not set
-CONFIG_PINCTRL_AMD=m
-CONFIG_PINCTRL_CY8C95X0=m
-CONFIG_PINCTRL_DA9062=m
-CONFIG_PINCTRL_MCP23S08_I2C=m
-CONFIG_PINCTRL_MCP23S08_SPI=m
-CONFIG_PINCTRL_MCP23S08=m
-
-#
-# Intel pinctrl drivers
-#
-CONFIG_PINCTRL_BAYTRAIL=y
-CONFIG_PINCTRL_CHERRYVIEW=m
-CONFIG_PINCTRL_LYNXPOINT=m
-CONFIG_PINCTRL_INTEL=y
-CONFIG_PINCTRL_ALDERLAKE=m
-CONFIG_PINCTRL_BROXTON=m
-CONFIG_PINCTRL_CANNONLAKE=m
-CONFIG_PINCTRL_CEDARFORK=m
-CONFIG_PINCTRL_DENVERTON=m
-CONFIG_PINCTRL_ELKHARTLAKE=m
-CONFIG_PINCTRL_EMMITSBURG=m
-CONFIG_PINCTRL_GEMINILAKE=m
-CONFIG_PINCTRL_ICELAKE=m
-CONFIG_PINCTRL_JASPERLAKE=m
-CONFIG_PINCTRL_LAKEFIELD=m
-CONFIG_PINCTRL_LEWISBURG=m
-CONFIG_PINCTRL_METEORLAKE=m
-CONFIG_PINCTRL_SUNRISEPOINT=m
-CONFIG_PINCTRL_TIGERLAKE=m
-# end of Intel pinctrl drivers
-
-#
-# Renesas pinctrl drivers
-#
-# end of Renesas pinctrl drivers
-
-CONFIG_PINCTRL_MADERA=m
-CONFIG_PINCTRL_CS47L15=y
-CONFIG_PINCTRL_CS47L35=y
-CONFIG_PINCTRL_CS47L85=y
-CONFIG_PINCTRL_CS47L90=y
-CONFIG_PINCTRL_CS47L92=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_FASTPATH_LIMIT=512
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIOLIB_IRQCHIP=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_CDEV=y
-# CONFIG_GPIO_CDEV_V1 is not set
-CONFIG_GPIO_GENERIC=m
-CONFIG_GPIO_MAX730X=m
-
-#
-# Memory mapped GPIO drivers
-#
-CONFIG_GPIO_AMDPT=m
-CONFIG_GPIO_DWAPB=m
-CONFIG_GPIO_EXAR=m
-CONFIG_GPIO_GENERIC_PLATFORM=m
-CONFIG_GPIO_ICH=m
-CONFIG_GPIO_MB86S7X=m
-CONFIG_GPIO_MENZ127=m
-CONFIG_GPIO_SIOX=m
-CONFIG_GPIO_VX855=m
-CONFIG_GPIO_AMD_FCH=m
-# end of Memory mapped GPIO drivers
-
-#
-# Port-mapped I/O GPIO drivers
-#
-CONFIG_GPIO_F7188X=m
-CONFIG_GPIO_IT87=m
-CONFIG_GPIO_SCH=m
-CONFIG_GPIO_SCH311X=m
-CONFIG_GPIO_WINBOND=m
-CONFIG_GPIO_WS16C48=m
-# end of Port-mapped I/O GPIO drivers
-
-#
-# I2C GPIO expanders
-#
-CONFIG_GPIO_ADP5588=m
-CONFIG_GPIO_MAX7300=m
-CONFIG_GPIO_MAX732X=m
-CONFIG_GPIO_PCA953X=m
-# CONFIG_GPIO_PCA953X_IRQ is not set
-CONFIG_GPIO_PCA9570=m
-CONFIG_GPIO_PCF857X=m
-CONFIG_GPIO_TPIC2810=m
-# end of I2C GPIO expanders
-
-#
-# MFD GPIO expanders
-#
-CONFIG_GPIO_ARIZONA=m
-CONFIG_GPIO_BD9571MWV=m
-CONFIG_GPIO_DA9052=m
-CONFIG_GPIO_DLN2=m
-CONFIG_GPIO_JANZ_TTL=m
-CONFIG_GPIO_KEMPLD=m
-CONFIG_GPIO_LP3943=m
-CONFIG_GPIO_LP873X=m
-CONFIG_GPIO_MADERA=m
-CONFIG_GPIO_TPS65086=m
-CONFIG_GPIO_TPS65912=m
-CONFIG_GPIO_TPS68470=y
-CONFIG_GPIO_TQMX86=m
-CONFIG_GPIO_UCB1400=m
-CONFIG_GPIO_WHISKEY_COVE=m
-CONFIG_GPIO_WM831X=m
-CONFIG_GPIO_WM8994=m
-# end of MFD GPIO expanders
-
-#
-# PCI GPIO expanders
-#
-CONFIG_GPIO_AMD8111=m
-CONFIG_GPIO_ML_IOH=m
-CONFIG_GPIO_PCI_IDIO_16=m
-CONFIG_GPIO_PCIE_IDIO_24=m
-CONFIG_GPIO_RDC321X=m
-# end of PCI GPIO expanders
-
-#
-# SPI GPIO expanders
-#
-CONFIG_GPIO_MAX3191X=m
-CONFIG_GPIO_MAX7301=m
-CONFIG_GPIO_MC33880=m
-CONFIG_GPIO_PISOSR=m
-CONFIG_GPIO_XRA1403=m
-# end of SPI GPIO expanders
-
-#
-# USB GPIO expanders
-#
-CONFIG_GPIO_VIPERBOARD=m
-# end of USB GPIO expanders
-
-#
-# Virtual GPIO drivers
-#
-CONFIG_GPIO_AGGREGATOR=m
-CONFIG_GPIO_MOCKUP=m
-CONFIG_GPIO_VIRTIO=m
-# end of Virtual GPIO drivers
-
-CONFIG_W1=m
-# CONFIG_W1_CON is not set
-
-#
-# 1-wire Bus Masters
-#
-# CONFIG_W1_MASTER_MATROX is not set
-# CONFIG_W1_MASTER_DS2490 is not set
-# CONFIG_W1_MASTER_DS2482 is not set
-# CONFIG_W1_MASTER_DS1WM is not set
-# CONFIG_W1_MASTER_GPIO is not set
-# CONFIG_W1_MASTER_SGI is not set
-# end of 1-wire Bus Masters
-
-#
-# 1-wire Slaves
-#
-# CONFIG_W1_SLAVE_THERM is not set
-# CONFIG_W1_SLAVE_SMEM is not set
-# CONFIG_W1_SLAVE_DS2405 is not set
-# CONFIG_W1_SLAVE_DS2408 is not set
-# CONFIG_W1_SLAVE_DS2413 is not set
-# CONFIG_W1_SLAVE_DS2406 is not set
-# CONFIG_W1_SLAVE_DS2423 is not set
-# CONFIG_W1_SLAVE_DS2805 is not set
-# CONFIG_W1_SLAVE_DS2430 is not set
-# CONFIG_W1_SLAVE_DS2431 is not set
-# CONFIG_W1_SLAVE_DS2433 is not set
-# CONFIG_W1_SLAVE_DS2438 is not set
-# CONFIG_W1_SLAVE_DS250X is not set
-CONFIG_W1_SLAVE_DS2780=m
-CONFIG_W1_SLAVE_DS2781=m
-# CONFIG_W1_SLAVE_DS28E04 is not set
-# CONFIG_W1_SLAVE_DS28E17 is not set
-# end of 1-wire Slaves
-
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_ATC260X=m
-CONFIG_POWER_RESET_MT6323=y
-# CONFIG_POWER_RESET_RESTART is not set
-CONFIG_POWER_RESET_TPS65086=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PDA_POWER=m
-CONFIG_GENERIC_ADC_BATTERY=m
-CONFIG_IP5XXX_POWER=m
-CONFIG_WM831X_BACKUP=m
-CONFIG_WM831X_POWER=m
-# CONFIG_TEST_POWER is not set
-CONFIG_CHARGER_ADP5061=m
-CONFIG_BATTERY_CW2015=m
-CONFIG_BATTERY_DS2760=m
-CONFIG_BATTERY_DS2780=m
-CONFIG_BATTERY_DS2781=m
-CONFIG_BATTERY_DS2782=m
-# CONFIG_BATTERY_SAMSUNG_SDI is not set
-CONFIG_BATTERY_SBS=m
-CONFIG_CHARGER_SBS=m
-CONFIG_MANAGER_SBS=m
-CONFIG_BATTERY_BQ27XXX=m
-CONFIG_BATTERY_BQ27XXX_I2C=m
-CONFIG_BATTERY_BQ27XXX_HDQ=m
-# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set
-CONFIG_BATTERY_DA9052=m
-CONFIG_CHARGER_DA9150=m
-CONFIG_BATTERY_DA9150=m
-CONFIG_CHARGER_AXP20X=m
-CONFIG_BATTERY_AXP20X=m
-CONFIG_AXP20X_POWER=m
-CONFIG_AXP288_CHARGER=m
-CONFIG_AXP288_FUEL_GAUGE=m
-CONFIG_BATTERY_MAX17040=m
-CONFIG_BATTERY_MAX17042=m
-CONFIG_BATTERY_MAX1721X=m
-CONFIG_CHARGER_PCF50633=m
-CONFIG_CHARGER_ISP1704=m
-CONFIG_CHARGER_MAX8903=m
-CONFIG_CHARGER_LP8727=m
-CONFIG_CHARGER_GPIO=m
-CONFIG_CHARGER_MANAGER=y
-CONFIG_CHARGER_LT3651=m
-CONFIG_CHARGER_LTC4162L=m
-CONFIG_CHARGER_MAX14577=m
-CONFIG_CHARGER_MAX77693=m
-CONFIG_CHARGER_MP2629=m
-CONFIG_CHARGER_MT6360=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_CHARGER_BQ2415X=m
-CONFIG_CHARGER_BQ24190=m
-CONFIG_CHARGER_BQ24257=m
-CONFIG_CHARGER_BQ24735=m
-CONFIG_CHARGER_BQ2515X=m
-CONFIG_CHARGER_BQ25890=m
-CONFIG_CHARGER_BQ25980=m
-CONFIG_CHARGER_BQ256XX=m
-CONFIG_CHARGER_SMB347=m
-CONFIG_BATTERY_GAUGE_LTC2941=m
-CONFIG_BATTERY_GOLDFISH=m
-CONFIG_BATTERY_RT5033=m
-CONFIG_CHARGER_RT9455=m
-CONFIG_CHARGER_CROS_USBPD=m
-CONFIG_CHARGER_CROS_PCHG=m
-CONFIG_CHARGER_BD99954=m
-CONFIG_BATTERY_UG3105=m
-CONFIG_CHARGER_WILCO=m
-CONFIG_BATTERY_SURFACE=m
-CONFIG_CHARGER_SURFACE=m
-CONFIG_HWMON=y
-CONFIG_HWMON_VID=m
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Native drivers
-#
-CONFIG_SENSORS_ABITUGURU=m
-CONFIG_SENSORS_ABITUGURU3=m
-CONFIG_SENSORS_AD7314=m
-CONFIG_SENSORS_AD7414=m
-CONFIG_SENSORS_AD7418=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1026=m
-CONFIG_SENSORS_ADM1029=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_ADM1177=m
-CONFIG_SENSORS_ADM9240=m
-CONFIG_SENSORS_ADT7X10=m
-CONFIG_SENSORS_ADT7310=m
-CONFIG_SENSORS_ADT7410=m
-CONFIG_SENSORS_ADT7411=m
-CONFIG_SENSORS_ADT7462=m
-CONFIG_SENSORS_ADT7470=m
-CONFIG_SENSORS_ADT7475=m
-CONFIG_SENSORS_AHT10=m
-CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m
-CONFIG_SENSORS_AS370=m
-CONFIG_SENSORS_ASC7621=m
-CONFIG_SENSORS_AXI_FAN_CONTROL=m
-# CONFIG_SENSORS_K8TEMP is not set
-CONFIG_SENSORS_K10TEMP=m
-# CONFIG_SENSORS_FAM15H_POWER is not set
-CONFIG_SENSORS_APPLESMC=m
-CONFIG_SENSORS_ASB100=m
-CONFIG_SENSORS_ASPEED=m
-CONFIG_SENSORS_ATXP1=m
-CONFIG_SENSORS_CORSAIR_CPRO=m
-CONFIG_SENSORS_CORSAIR_PSU=m
-CONFIG_SENSORS_DRIVETEMP=m
-CONFIG_SENSORS_DS620=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_DELL_SMM=m
-# CONFIG_I8K is not set
-CONFIG_SENSORS_DA9052_ADC=m
-CONFIG_SENSORS_I5K_AMB=m
-CONFIG_SENSORS_F71805F=m
-CONFIG_SENSORS_F71882FG=m
-CONFIG_SENSORS_F75375S=m
-CONFIG_SENSORS_MC13783_ADC=m
-CONFIG_SENSORS_FSCHMD=m
-CONFIG_SENSORS_FTSTEUTATES=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_GL520SM=m
-CONFIG_SENSORS_G760A=m
-CONFIG_SENSORS_G762=m
-CONFIG_SENSORS_HIH6130=m
-CONFIG_SENSORS_IBMAEM=m
-CONFIG_SENSORS_IBMPEX=m
-CONFIG_SENSORS_IIO_HWMON=m
-# CONFIG_SENSORS_I5500 is not set
-# CONFIG_SENSORS_CORETEMP is not set
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_JC42=m
-CONFIG_SENSORS_POWR1220=m
-CONFIG_SENSORS_LINEAGE=m
-CONFIG_SENSORS_LTC2945=m
-CONFIG_SENSORS_LTC2947=m
-CONFIG_SENSORS_LTC2947_I2C=m
-CONFIG_SENSORS_LTC2947_SPI=m
-CONFIG_SENSORS_LTC2990=m
-CONFIG_SENSORS_LTC2992=m
-CONFIG_SENSORS_LTC4151=m
-CONFIG_SENSORS_LTC4215=m
-CONFIG_SENSORS_LTC4222=m
-CONFIG_SENSORS_LTC4245=m
-CONFIG_SENSORS_LTC4260=m
-CONFIG_SENSORS_LTC4261=m
-CONFIG_SENSORS_MAX1111=m
-CONFIG_SENSORS_MAX127=m
-CONFIG_SENSORS_MAX16065=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_MAX1668=m
-CONFIG_SENSORS_MAX197=m
-CONFIG_SENSORS_MAX31722=m
-CONFIG_SENSORS_MAX31730=m
-CONFIG_SENSORS_MAX31760=m
-CONFIG_SENSORS_MAX6620=m
-CONFIG_SENSORS_MAX6621=m
-CONFIG_SENSORS_MAX6639=m
-CONFIG_SENSORS_MAX6642=m
-CONFIG_SENSORS_MAX6650=m
-CONFIG_SENSORS_MAX6697=m
-CONFIG_SENSORS_MAX31790=m
-CONFIG_SENSORS_MCP3021=m
-CONFIG_SENSORS_MLXREG_FAN=m
-CONFIG_SENSORS_TC654=m
-CONFIG_SENSORS_TPS23861=m
-CONFIG_SENSORS_MENF21BMC_HWMON=m
-CONFIG_SENSORS_MR75203=m
-CONFIG_SENSORS_ADCXX=m
-CONFIG_SENSORS_LM63=m
-CONFIG_SENSORS_LM70=m
-CONFIG_SENSORS_LM73=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM87=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_LM92=m
-CONFIG_SENSORS_LM93=m
-CONFIG_SENSORS_LM95234=m
-CONFIG_SENSORS_LM95241=m
-CONFIG_SENSORS_LM95245=m
-CONFIG_SENSORS_PC87360=m
-CONFIG_SENSORS_PC87427=m
-CONFIG_SENSORS_NTC_THERMISTOR=m
-CONFIG_SENSORS_NCT6683=m
-CONFIG_SENSORS_NCT6775=m
-CONFIG_SENSORS_NCT7802=m
-CONFIG_SENSORS_NCT7904=m
-CONFIG_SENSORS_NPCM7XX=m
-CONFIG_SENSORS_NZXT_KRAKEN2=m
-CONFIG_SENSORS_PCF8591=m
-CONFIG_PMBUS=m
-CONFIG_SENSORS_PMBUS=m
-CONFIG_SENSORS_ADM1266=m
-CONFIG_SENSORS_ADM1275=m
-CONFIG_SENSORS_BEL_PFE=m
-CONFIG_SENSORS_BPA_RS600=m
-CONFIG_SENSORS_FSP_3Y=m
-CONFIG_SENSORS_IBM_CFFPS=m
-CONFIG_SENSORS_DPS920AB=m
-CONFIG_SENSORS_INSPUR_IPSPS=m
-CONFIG_SENSORS_IR35221=m
-CONFIG_SENSORS_IR36021=m
-CONFIG_SENSORS_IR38064=m
-CONFIG_SENSORS_IRPS5401=m
-CONFIG_SENSORS_ISL68137=m
-CONFIG_SENSORS_LM25066=m
-CONFIG_SENSORS_LM25066_REGULATOR=y
-CONFIG_SENSORS_LTC2978=m
-CONFIG_SENSORS_LTC2978_REGULATOR=y
-CONFIG_SENSORS_LTC3815=m
-CONFIG_SENSORS_MAX15301=m
-CONFIG_SENSORS_MAX16064=m
-CONFIG_SENSORS_MAX16601=m
-CONFIG_SENSORS_MAX20730=m
-CONFIG_SENSORS_MAX20751=m
-CONFIG_SENSORS_MAX31785=m
-CONFIG_SENSORS_MAX34440=m
-CONFIG_SENSORS_MAX8688=m
-CONFIG_SENSORS_MP2888=m
-CONFIG_SENSORS_MP2975=m
-CONFIG_SENSORS_PIM4328=m
-CONFIG_SENSORS_PLI1209BC=m
-CONFIG_SENSORS_PLI1209BC_REGULATOR=y
-CONFIG_SENSORS_PM6764TR=m
-CONFIG_SENSORS_PXE1610=m
-CONFIG_SENSORS_Q54SJ108A2=m
-CONFIG_SENSORS_STPDDC60=m
-CONFIG_SENSORS_TPS40422=m
-CONFIG_SENSORS_TPS53679=m
-CONFIG_SENSORS_TPS546D24=m
-CONFIG_SENSORS_UCD9000=m
-CONFIG_SENSORS_UCD9200=m
-CONFIG_SENSORS_XDPE122=m
-CONFIG_SENSORS_XDPE122_REGULATOR=y
-CONFIG_SENSORS_ZL6100=m
-CONFIG_SENSORS_SBTSI=m
-CONFIG_SENSORS_SBRMI=m
-CONFIG_SENSORS_SHT15=m
-CONFIG_SENSORS_SHT21=m
-CONFIG_SENSORS_SHT3x=m
-CONFIG_SENSORS_SHT4x=m
-CONFIG_SENSORS_SHTC1=m
-CONFIG_SENSORS_SIS5595=m
-CONFIG_SENSORS_SY7636A=m
-CONFIG_SENSORS_DME1737=m
-CONFIG_SENSORS_EMC1403=m
-CONFIG_SENSORS_EMC2103=m
-CONFIG_SENSORS_EMC2305=m
-CONFIG_SENSORS_EMC6W201=m
-CONFIG_SENSORS_SMSC47M1=m
-CONFIG_SENSORS_SMSC47M192=m
-CONFIG_SENSORS_SMSC47B397=m
-CONFIG_SENSORS_SCH56XX_COMMON=m
-CONFIG_SENSORS_SCH5627=m
-CONFIG_SENSORS_SCH5636=m
-CONFIG_SENSORS_STTS751=m
-CONFIG_SENSORS_SMM665=m
-CONFIG_SENSORS_ADC128D818=m
-CONFIG_SENSORS_ADS7828=m
-CONFIG_SENSORS_ADS7871=m
-CONFIG_SENSORS_AMC6821=m
-CONFIG_SENSORS_INA209=m
-CONFIG_SENSORS_INA2XX=m
-CONFIG_SENSORS_INA3221=m
-CONFIG_SENSORS_TC74=m
-CONFIG_SENSORS_THMC50=m
-CONFIG_SENSORS_TMP102=m
-CONFIG_SENSORS_TMP103=m
-CONFIG_SENSORS_TMP108=m
-CONFIG_SENSORS_TMP401=m
-CONFIG_SENSORS_TMP421=m
-CONFIG_SENSORS_TMP464=m
-CONFIG_SENSORS_TMP513=m
-CONFIG_SENSORS_VIA_CPUTEMP=m
-CONFIG_SENSORS_VIA686A=m
-CONFIG_SENSORS_VT1211=m
-CONFIG_SENSORS_VT8231=m
-CONFIG_SENSORS_W83773G=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83791D=m
-CONFIG_SENSORS_W83792D=m
-CONFIG_SENSORS_W83793=m
-CONFIG_SENSORS_W83795=m
-CONFIG_SENSORS_W83795_FANCTRL=y
-CONFIG_SENSORS_W83L785TS=m
-CONFIG_SENSORS_W83L786NG=m
-CONFIG_SENSORS_W83627HF=m
-CONFIG_SENSORS_W83627EHF=m
-CONFIG_SENSORS_WM831X=m
-CONFIG_SENSORS_XGENE=m
-CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m
-
-#
-# ACPI drivers
-#
-CONFIG_SENSORS_ACPI_POWER=m
-CONFIG_SENSORS_ATK0110=m
-CONFIG_SENSORS_ASUS_WMI_EC=m
-CONFIG_SENSORS_ASUS_EC=m
-CONFIG_SENSORS_ASUS_WMI=m
-CONFIG_THERMAL=y
-CONFIG_THERMAL_NETLINK=y
-CONFIG_THERMAL_STATISTICS=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=100
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
-# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
-CONFIG_DEVFREQ_THERMAL=y
-# CONFIG_THERMAL_EMULATION is not set
-
-#
-# Intel thermal drivers
-#
-CONFIG_INTEL_SOC_DTS_IOSF_CORE=m
-# CONFIG_INTEL_SOC_DTS_THERMAL is not set
-
-#
-# ACPI INT340X thermal drivers
-#
-CONFIG_INT340X_THERMAL=m
-CONFIG_ACPI_THERMAL_REL=m
-CONFIG_INT3406_THERMAL=m
-CONFIG_PROC_THERMAL_MMIO_RAPL=m
-# end of ACPI INT340X thermal drivers
-
-# CONFIG_INTEL_BXT_PMIC_THERMAL is not set
-# CONFIG_INTEL_PCH_THERMAL is not set
-CONFIG_INTEL_TCC_COOLING=m
-CONFIG_INTEL_MENLOW=m
-CONFIG_INTEL_HFI_THERMAL=y
-# end of Intel thermal drivers
-
-CONFIG_GENERIC_ADC_THERMAL=m
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_CORE=m
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
-CONFIG_WATCHDOG_OPEN_TIMEOUT=0
-# CONFIG_WATCHDOG_SYSFS is not set
-# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set
-
-#
-# Watchdog Pretimeout Governors
-#
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=m
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-
-#
-# Watchdog Device Drivers
-#
-CONFIG_SOFT_WATCHDOG=m
-# CONFIG_SOFT_WATCHDOG_PRETIMEOUT is not set
-CONFIG_DA9052_WATCHDOG=m
-CONFIG_DA9063_WATCHDOG=m
-CONFIG_DA9062_WATCHDOG=m
-CONFIG_MENF21BMC_WATCHDOG=m
-CONFIG_MENZ069_WATCHDOG=m
-CONFIG_WDAT_WDT=m
-CONFIG_WM831X_WATCHDOG=m
-CONFIG_XILINX_WATCHDOG=m
-CONFIG_ZIIRAVE_WATCHDOG=m
-CONFIG_RAVE_SP_WATCHDOG=m
-CONFIG_MLX_WDT=m
-CONFIG_CADENCE_WATCHDOG=m
-CONFIG_DW_WATCHDOG=m
-CONFIG_MAX77620_WATCHDOG=m
-CONFIG_MAX63XX_WATCHDOG=m
-CONFIG_RETU_WATCHDOG=m
-CONFIG_ACQUIRE_WDT=m
-CONFIG_ADVANTECH_WDT=m
-CONFIG_ALIM1535_WDT=m
-CONFIG_ALIM7101_WDT=m
-CONFIG_EBC_C384_WDT=m
-CONFIG_EXAR_WDT=m
-CONFIG_F71808E_WDT=m
-# CONFIG_SP5100_TCO is not set
-CONFIG_SBC_FITPC2_WATCHDOG=m
-CONFIG_EUROTECH_WDT=m
-CONFIG_IB700_WDT=m
-CONFIG_IBMASR=m
-CONFIG_WAFER_WDT=m
-CONFIG_I6300ESB_WDT=m
-CONFIG_HP_WATCHDOG=m
-CONFIG_IE6XX_WDT=m
-CONFIG_ITCO_WDT=m
-CONFIG_ITCO_VENDOR_SUPPORT=y
-CONFIG_IT8712F_WDT=m
-CONFIG_IT87_WDT=m
-CONFIG_HP_WATCHDOG=m
-CONFIG_HPWDT_NMI_DECODING=y
-CONFIG_KEMPLD_WDT=m
-CONFIG_BCM7038_WDT=m
-CONFIG_SC1200_WDT=m
-CONFIG_PC87413_WDT=m
-CONFIG_NV_TCO=m
-CONFIG_60XX_WDT=m
-CONFIG_CPU5_WDT=m
-CONFIG_SMSC_SCH311X_WDT=m
-CONFIG_SMSC37B787_WDT=m
-CONFIG_TQMX86_WDT=m
-CONFIG_VIA_WDT=m
-CONFIG_W83627HF_WDT=m
-CONFIG_W83877F_WDT=m
-CONFIG_W83977F_WDT=m
-CONFIG_MACHZ_WDT=m
-CONFIG_SBC_EPX_C3_WATCHDOG=m
-CONFIG_INTEL_MEI_WDT=m
-CONFIG_NI903X_WDT=m
-CONFIG_NIC7018_WDT=m
-CONFIG_SIEMENS_SIMATIC_IPC_WDT=m
-CONFIG_MEN_A21_WDT=m
-
-#
-# PCI-based Watchdog Cards
-#
-CONFIG_PCIPCWATCHDOG=m
-CONFIG_WDTPCI=m
-
-#
-# USB-based Watchdog Cards
-#
-CONFIG_USBPCWATCHDOG=m
-CONFIG_SSB_POSSIBLE=y
-CONFIG_SSB=m
-CONFIG_SSB_SPROM=y
-CONFIG_SSB_BLOCKIO=y
-CONFIG_SSB_PCIHOST_POSSIBLE=y
-CONFIG_SSB_PCIHOST=y
-CONFIG_SSB_B43_PCI_BRIDGE=y
-CONFIG_SSB_PCMCIAHOST_POSSIBLE=y
-CONFIG_SSB_PCMCIAHOST=y
-CONFIG_SSB_SDIOHOST_POSSIBLE=y
-CONFIG_SSB_SDIOHOST=y
-CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
-CONFIG_SSB_DRIVER_PCICORE=y
-CONFIG_SSB_DRIVER_GPIO=y
-CONFIG_BCMA_POSSIBLE=y
-CONFIG_BCMA=m
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_SOC=y
-CONFIG_BCMA_DRIVER_PCI=y
-CONFIG_BCMA_SFLASH=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_DRIVER_GPIO=y
-# CONFIG_BCMA_DEBUG is not set
-
-#
-# Multifunction device drivers
-#
-CONFIG_MFD_CORE=y
-CONFIG_MFD_BCM590XX=m
-CONFIG_MFD_BD9571MWV=m
-CONFIG_MFD_AXP20X=m
-CONFIG_MFD_AXP20X_I2C=m
-CONFIG_MFD_CROS_EC_DEV=m
-CONFIG_MFD_MADERA=m
-CONFIG_MFD_MADERA_I2C=m
-CONFIG_MFD_MADERA_SPI=m
-CONFIG_MFD_CS47L15=y
-CONFIG_MFD_CS47L35=y
-CONFIG_MFD_CS47L85=y
-CONFIG_MFD_CS47L90=y
-CONFIG_MFD_CS47L92=y
-CONFIG_PMIC_DA9052=y
-CONFIG_MFD_DA9052_SPI=y
-CONFIG_MFD_DA9062=m
-CONFIG_MFD_DA9063=m
-CONFIG_MFD_DA9150=m
-CONFIG_MFD_DLN2=m
-CONFIG_MFD_MC13XXX=m
-CONFIG_MFD_MC13XXX_SPI=m
-CONFIG_MFD_MC13XXX_I2C=m
-CONFIG_MFD_MP2629=m
-CONFIG_HTC_PASIC3=m
-CONFIG_MFD_INTEL_QUARK_I2C_GPIO=m
-CONFIG_LPC_ICH=m
-CONFIG_LPC_SCH=m
-CONFIG_INTEL_SOC_PMIC_BXTWC=m
-CONFIG_INTEL_SOC_PMIC_CHTDC_TI=m
-CONFIG_MFD_INTEL_LPSS=m
-CONFIG_MFD_INTEL_LPSS_ACPI=m
-CONFIG_MFD_INTEL_LPSS_PCI=m
-CONFIG_MFD_INTEL_PMC_BXT=m
-CONFIG_MFD_INTEL_PMT=m
-CONFIG_MFD_IQS62X=m
-CONFIG_MFD_JANZ_CMODIO=m
-CONFIG_MFD_KEMPLD=m
-CONFIG_MFD_88PM800=m
-CONFIG_MFD_88PM805=m
-CONFIG_MFD_MAX14577=m
-CONFIG_MFD_MAX77693=m
-CONFIG_MFD_MAX77714=m
-CONFIG_MFD_MAX8907=m
-CONFIG_MFD_MT6360=m
-CONFIG_MFD_MT6370=m
-CONFIG_MFD_MT6397=m
-CONFIG_MFD_MENF21BMC=m
-CONFIG_MFD_OCELOT=m
-CONFIG_EZX_PCAP=y
-CONFIG_MFD_VIPERBOARD=m
-CONFIG_MFD_RETU=m
-CONFIG_MFD_PCF50633=m
-CONFIG_PCF50633_ADC=m
-CONFIG_PCF50633_GPIO=m
-CONFIG_UCB1400_CORE=m
-CONFIG_MFD_SY7636A=m
-CONFIG_MFD_RDC321X=m
-CONFIG_MFD_RT4831=m
-CONFIG_MFD_RT5033=m
-CONFIG_MFD_RT5120=m
-CONFIG_MFD_SI476X_CORE=m
-CONFIG_MFD_SIMPLE_MFD_I2C=m
-CONFIG_MFD_SM501=m
-CONFIG_MFD_SM501_GPIO=y
-CONFIG_MFD_SKY81452=m
-CONFIG_MFD_SYSCON=y
-CONFIG_MFD_TI_AM335X_TSCADC=m
-CONFIG_MFD_LP3943=m
-CONFIG_MFD_TI_LMU=m
-CONFIG_TPS6105X=m
-CONFIG_TPS65010=m
-CONFIG_TPS6507X=m
-CONFIG_MFD_TPS65086=m
-CONFIG_MFD_TI_LP873X=m
-CONFIG_MFD_TPS65912=y
-CONFIG_MFD_TPS65912_I2C=m
-CONFIG_MFD_TPS65912_SPI=y
-CONFIG_MFD_WL1273_CORE=m
-CONFIG_MFD_LM3533=m
-CONFIG_MFD_TQMX86=m
-CONFIG_MFD_VX855=m
-CONFIG_MFD_ARIZONA=m
-CONFIG_MFD_ARIZONA_I2C=m
-CONFIG_MFD_ARIZONA_SPI=m
-CONFIG_MFD_CS47L24=y
-CONFIG_MFD_WM5102=y
-CONFIG_MFD_WM5110=y
-CONFIG_MFD_WM8997=y
-CONFIG_MFD_WM8998=y
-CONFIG_MFD_WM831X=y
-CONFIG_MFD_WM831X_SPI=y
-CONFIG_MFD_WM8994=m
-CONFIG_MFD_WCD934X=m
-CONFIG_MFD_ATC260X=m
-CONFIG_MFD_ATC260X_I2C=m
-CONFIG_RAVE_SP_CORE=m
-CONFIG_MFD_INTEL_M10_BMC=m
-# end of Multifunction device drivers
-
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=m
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
-CONFIG_REGULATOR_USERSPACE_CONSUMER=m
-CONFIG_REGULATOR_88PG86X=m
-CONFIG_REGULATOR_88PM800=m
-CONFIG_REGULATOR_ACT8865=m
-CONFIG_REGULATOR_AD5398=m
-CONFIG_REGULATOR_ARIZONA_LDO1=m
-CONFIG_REGULATOR_ARIZONA_MICSUPP=m
-CONFIG_REGULATOR_ATC260X=m
-CONFIG_REGULATOR_AXP20X=m
-CONFIG_REGULATOR_BCM590XX=m
-CONFIG_REGULATOR_BD9571MWV=m
-CONFIG_REGULATOR_DA9052=m
-CONFIG_REGULATOR_DA9062=m
-CONFIG_REGULATOR_DA9210=m
-CONFIG_REGULATOR_DA9211=m
-CONFIG_REGULATOR_FAN53555=m
-CONFIG_REGULATOR_GPIO=m
-CONFIG_REGULATOR_ISL9305=m
-CONFIG_REGULATOR_ISL6271A=m
-CONFIG_REGULATOR_LM363X=m
-CONFIG_REGULATOR_LP3971=m
-CONFIG_REGULATOR_LP3972=m
-CONFIG_REGULATOR_LP872X=m
-CONFIG_REGULATOR_LP8755=m
-CONFIG_REGULATOR_LTC3589=m
-CONFIG_REGULATOR_LTC3676=m
-CONFIG_REGULATOR_MAX14577=m
-CONFIG_REGULATOR_MAX1586=m
-CONFIG_REGULATOR_MAX8649=m
-CONFIG_REGULATOR_MAX8660=m
-CONFIG_REGULATOR_MAX8893=m
-CONFIG_REGULATOR_MAX8907=m
-CONFIG_REGULATOR_MAX8952=m
-CONFIG_REGULATOR_MAX77693=m
-CONFIG_REGULATOR_MAX77826=m
-CONFIG_REGULATOR_MC13XXX_CORE=m
-CONFIG_REGULATOR_MC13783=m
-CONFIG_REGULATOR_MC13892=m
-CONFIG_REGULATOR_MP8859=m
-CONFIG_REGULATOR_MT6311=m
-CONFIG_REGULATOR_MT6315=m
-CONFIG_REGULATOR_MT6323=m
-CONFIG_REGULATOR_MT6331=m
-CONFIG_REGULATOR_MT6332=m
-CONFIG_REGULATOR_MT6358=m
-CONFIG_REGULATOR_MT6359=m
-CONFIG_REGULATOR_MT6360=m
-CONFIG_REGULATOR_MT6370=m
-CONFIG_REGULATOR_MT6397=m
-CONFIG_REGULATOR_PCA9450=m
-CONFIG_REGULATOR_PCAP=m
-CONFIG_REGULATOR_PCF50633=m
-CONFIG_REGULATOR_PV88060=m
-CONFIG_REGULATOR_PV88080=m
-CONFIG_REGULATOR_PV88090=m
-CONFIG_REGULATOR_PWM=m
-CONFIG_REGULATOR_QCOM_SPMI=m
-CONFIG_REGULATOR_QCOM_USB_VBUS=m
-CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
-CONFIG_REGULATOR_RT4801=m
-CONFIG_REGULATOR_RT4831=m
-CONFIG_REGULATOR_RT5120=m
-CONFIG_REGULATOR_RT5190A=m
-CONFIG_REGULATOR_RT5033=m
-CONFIG_REGULATOR_RT5120=m
-CONFIG_REGULATOR_RT5190A=m
-CONFIG_REGULATOR_RT6160=m
-CONFIG_REGULATOR_RT6245=m
-CONFIG_REGULATOR_RTQ2134=m
-CONFIG_REGULATOR_RTMV20=m
-CONFIG_REGULATOR_RTQ6752=m
-CONFIG_REGULATOR_SKY81452=m
-CONFIG_REGULATOR_SLG51000=m
-CONFIG_REGULATOR_SY7636A=m
-CONFIG_REGULATOR_TPS51632=m
-CONFIG_REGULATOR_TPS6105X=m
-CONFIG_REGULATOR_TPS62360=m
-CONFIG_REGULATOR_TPS6286X=m
-CONFIG_REGULATOR_TPS65023=m
-CONFIG_REGULATOR_TPS6507X=m
-CONFIG_REGULATOR_TPS65086=m
-CONFIG_REGULATOR_TPS65132=m
-CONFIG_REGULATOR_TPS6524X=m
-CONFIG_REGULATOR_TPS65912=m
-CONFIG_REGULATOR_TPS68470=m
-CONFIG_REGULATOR_WM831X=m
-CONFIG_REGULATOR_WM8994=m
-CONFIG_REGULATOR_QCOM_LABIBB=m
-CONFIG_RC_CORE=m
-CONFIG_RC_MAP=m
-CONFIG_LIRC=y
-CONFIG_RC_DECODERS=y
-CONFIG_IR_NEC_DECODER=m
-CONFIG_IR_RC5_DECODER=m
-CONFIG_IR_RC6_DECODER=m
-CONFIG_IR_JVC_DECODER=m
-CONFIG_IR_SONY_DECODER=m
-CONFIG_IR_SANYO_DECODER=m
-CONFIG_IR_SHARP_DECODER=m
-CONFIG_IR_MCE_KBD_DECODER=m
-CONFIG_IR_XMP_DECODER=m
-CONFIG_IR_IMON_DECODER=m
-CONFIG_IR_RCMM_DECODER=m
-CONFIG_RC_DEVICES=y
-CONFIG_RC_ATI_REMOTE=m
-CONFIG_IR_ENE=m
-CONFIG_IR_IMON=m
-CONFIG_IR_IMON_RAW=m
-CONFIG_IR_MCEUSB=m
-CONFIG_IR_ITE_CIR=m
-CONFIG_IR_FINTEK=m
-CONFIG_IR_NUVOTON=m
-CONFIG_IR_REDRAT3=m
-CONFIG_IR_STREAMZAP=m
-CONFIG_IR_WINBOND_CIR=m
-CONFIG_IR_IGORPLUGUSB=m
-CONFIG_IR_IGUANA=m
-CONFIG_IR_TTUSBIR=m
-CONFIG_RC_LOOPBACK=m
-CONFIG_IR_SERIAL=m
-CONFIG_IR_SERIAL_TRANSMITTER=y
-CONFIG_RC_XBOX_DVD=m
-CONFIG_IR_TOY=m
-CONFIG_CEC_CORE=m
-CONFIG_CEC_NOTIFIER=y
-CONFIG_CEC_PIN=y
-
-#
-# CEC support
-#
-CONFIG_MEDIA_CEC_RC=y
-# CONFIG_CEC_PIN_ERROR_INJ is not set
-CONFIG_MEDIA_CEC_SUPPORT=y
-CONFIG_CEC_CH7322=m
-CONFIG_CEC_CROS_EC=m
-CONFIG_CEC_GPIO=m
-CONFIG_CEC_SECO=m
-CONFIG_CEC_SECO_RC=y
-CONFIG_USB_PULSE8_CEC=m
-CONFIG_USB_RAINSHADOW_CEC=m
-# end of CEC support
-
-CONFIG_MEDIA_SUPPORT=m
-CONFIG_MEDIA_SUPPORT_FILTER=y
-CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
-
-#
-# Media device types
-#
-CONFIG_MEDIA_PLATFORM_DRIVERS=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_SDR_SUPPORT=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-# CONFIG_MEDIA_TEST_SUPPORT is not set
-# end of Media device types
-
-CONFIG_VIDEO_DEV=m
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_DVB_CORE=m
-
-#
-# Video4Linux options
-#
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L2_I2C=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_TUNER=m
-CONFIG_V4L2_MEM2MEM_DEV=m
-CONFIG_V4L2_FLASH_LED_CLASS=m
-CONFIG_V4L2_FWNODE=m
-CONFIG_V4L2_ASYNC=m
-CONFIG_VIDEOBUF_GEN=m
-CONFIG_VIDEOBUF_DMA_SG=m
-CONFIG_VIDEOBUF_VMALLOC=m
-# end of Video4Linux options
-
-#
-# Media controller options
-#
-CONFIG_MEDIA_CONTROLLER_DVB=y
-# end of Media controller options
-
-#
-# Digital TV options
-#
-# CONFIG_DVB_MMAP is not set
-CONFIG_DVB_NET=y
-CONFIG_DVB_MAX_ADAPTERS=8
-CONFIG_DVB_DYNAMIC_MINORS=y
-# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set
-# CONFIG_DVB_ULE_DEBUG is not set
-# end of Digital TV options
-
-#
-# Media drivers
-#
-
-#
-# Drivers filtered as selected at 'Filter media drivers'
-#
-CONFIG_MEDIA_USB_SUPPORT=y
-
-#
-# Webcam devices
-#
-CONFIG_USB_VIDEO_CLASS=m
-CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
-CONFIG_USB_GSPCA=m
-CONFIG_USB_M5602=m
-CONFIG_USB_STV06XX=m
-CONFIG_USB_GL860=m
-CONFIG_USB_GSPCA_BENQ=m
-CONFIG_USB_GSPCA_CONEX=m
-CONFIG_USB_GSPCA_CPIA1=m
-CONFIG_USB_GSPCA_DTCS033=m
-CONFIG_USB_GSPCA_ETOMS=m
-CONFIG_USB_GSPCA_FINEPIX=m
-CONFIG_USB_GSPCA_JEILINJ=m
-CONFIG_USB_GSPCA_JL2005BCD=m
-CONFIG_USB_GSPCA_KINECT=m
-CONFIG_USB_GSPCA_KONICA=m
-CONFIG_USB_GSPCA_MARS=m
-CONFIG_USB_GSPCA_MR97310A=m
-CONFIG_USB_GSPCA_NW80X=m
-CONFIG_USB_GSPCA_OV519=m
-CONFIG_USB_GSPCA_OV534=m
-CONFIG_USB_GSPCA_OV534_9=m
-CONFIG_USB_GSPCA_PAC207=m
-CONFIG_USB_GSPCA_PAC7302=m
-CONFIG_USB_GSPCA_PAC7311=m
-CONFIG_USB_GSPCA_SE401=m
-CONFIG_USB_GSPCA_SN9C2028=m
-CONFIG_USB_GSPCA_SN9C20X=m
-CONFIG_USB_GSPCA_SONIXB=m
-CONFIG_USB_GSPCA_SONIXJ=m
-CONFIG_USB_GSPCA_SPCA500=m
-CONFIG_USB_GSPCA_SPCA501=m
-CONFIG_USB_GSPCA_SPCA505=m
-CONFIG_USB_GSPCA_SPCA506=m
-CONFIG_USB_GSPCA_SPCA508=m
-CONFIG_USB_GSPCA_SPCA561=m
-CONFIG_USB_GSPCA_SPCA1528=m
-CONFIG_USB_GSPCA_SQ905=m
-CONFIG_USB_GSPCA_SQ905C=m
-CONFIG_USB_GSPCA_SQ930X=m
-CONFIG_USB_GSPCA_STK014=m
-CONFIG_USB_GSPCA_STK1135=m
-CONFIG_USB_GSPCA_STV0680=m
-CONFIG_USB_GSPCA_SUNPLUS=m
-CONFIG_USB_GSPCA_T613=m
-CONFIG_USB_GSPCA_TOPRO=m
-CONFIG_USB_GSPCA_TOUPTEK=m
-CONFIG_USB_GSPCA_TV8532=m
-CONFIG_USB_GSPCA_VC032X=m
-CONFIG_USB_GSPCA_VICAM=m
-CONFIG_USB_GSPCA_XIRLINK_CIT=m
-CONFIG_USB_GSPCA_ZC3XX=m
-CONFIG_USB_PWC=m
-# CONFIG_USB_PWC_DEBUG is not set
-CONFIG_USB_PWC_INPUT_EVDEV=y
-CONFIG_VIDEO_CPIA2=m
-CONFIG_USB_ZR364XX=m
-CONFIG_USB_STKWEBCAM=m
-CONFIG_USB_S2255=m
-CONFIG_VIDEO_USBTV=m
-
-#
-# Analog TV USB devices
-#
-CONFIG_VIDEO_PVRUSB2=m
-CONFIG_VIDEO_PVRUSB2_SYSFS=y
-CONFIG_VIDEO_PVRUSB2_DVB=y
-# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
-CONFIG_VIDEO_HDPVR=m
-CONFIG_VIDEO_STK1160_COMMON=m
-CONFIG_VIDEO_STK1160=m
-CONFIG_VIDEO_GO7007=m
-CONFIG_VIDEO_GO7007_USB=m
-CONFIG_VIDEO_GO7007_LOADER=m
-CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
-
-#
-# Analog/digital TV USB devices
-#
-CONFIG_VIDEO_AU0828=m
-CONFIG_VIDEO_AU0828_V4L2=y
-CONFIG_VIDEO_AU0828_RC=y
-CONFIG_VIDEO_CX231XX=m
-CONFIG_VIDEO_CX231XX_RC=y
-CONFIG_VIDEO_CX231XX_ALSA=m
-CONFIG_VIDEO_CX231XX_DVB=m
-CONFIG_VIDEO_TM6000=m
-CONFIG_VIDEO_TM6000_ALSA=m
-CONFIG_VIDEO_TM6000_DVB=m
-
-#
-# Digital TV USB devices
-#
-CONFIG_DVB_USB=m
-# CONFIG_DVB_USB_DEBUG is not set
-CONFIG_DVB_USB_DIB3000MC=m
-CONFIG_DVB_USB_A800=m
-CONFIG_DVB_USB_DIBUSB_MB=m
-CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
-CONFIG_DVB_USB_DIBUSB_MC=m
-CONFIG_DVB_USB_DIB0700=m
-CONFIG_DVB_USB_UMT_010=m
-CONFIG_DVB_USB_CXUSB=m
-CONFIG_DVB_USB_CXUSB_ANALOG=y
-CONFIG_DVB_USB_M920X=m
-CONFIG_DVB_USB_DIGITV=m
-CONFIG_DVB_USB_VP7045=m
-CONFIG_DVB_USB_VP702X=m
-CONFIG_DVB_USB_GP8PSK=m
-CONFIG_DVB_USB_NOVA_T_USB2=m
-CONFIG_DVB_USB_TTUSB2=m
-CONFIG_DVB_USB_DTT200U=m
-CONFIG_DVB_USB_OPERA1=m
-CONFIG_DVB_USB_AF9005=m
-CONFIG_DVB_USB_AF9005_REMOTE=m
-CONFIG_DVB_USB_PCTV452E=m
-CONFIG_DVB_USB_DW2102=m
-CONFIG_DVB_USB_CINERGY_T2=m
-CONFIG_DVB_USB_DTV5100=m
-CONFIG_DVB_USB_AZ6027=m
-CONFIG_DVB_USB_TECHNISAT_USB2=m
-CONFIG_DVB_USB_V2=m
-CONFIG_DVB_USB_AF9015=m
-CONFIG_DVB_USB_AF9035=m
-CONFIG_DVB_USB_ANYSEE=m
-CONFIG_DVB_USB_AU6610=m
-CONFIG_DVB_USB_AZ6007=m
-CONFIG_DVB_USB_CE6230=m
-CONFIG_DVB_USB_EC168=m
-CONFIG_DVB_USB_GL861=m
-CONFIG_DVB_USB_LME2510=m
-CONFIG_DVB_USB_MXL111SF=m
-CONFIG_DVB_USB_RTL28XXU=m
-CONFIG_DVB_USB_DVBSKY=m
-CONFIG_DVB_USB_ZD1301=m
-CONFIG_DVB_TTUSB_BUDGET=m
-CONFIG_DVB_TTUSB_DEC=m
-CONFIG_SMS_USB_DRV=m
-CONFIG_DVB_B2C2_FLEXCOP_USB=m
-# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
-CONFIG_DVB_AS102=m
-
-#
-# Webcam, TV (analog/digital) USB devices
-#
-CONFIG_VIDEO_EM28XX=m
-CONFIG_VIDEO_EM28XX_V4L2=m
-CONFIG_VIDEO_EM28XX_ALSA=m
-CONFIG_VIDEO_EM28XX_DVB=m
-CONFIG_VIDEO_EM28XX_RC=m
-
-#
-# Software defined radio USB devices
-#
-CONFIG_USB_AIRSPY=m
-CONFIG_USB_HACKRF=m
-CONFIG_USB_MSI2500=m
-CONFIG_MEDIA_PCI_SUPPORT=y
-
-#
-# Media capture support
-#
-CONFIG_VIDEO_MEYE=m
-CONFIG_VIDEO_SOLO6X10=m
-CONFIG_VIDEO_TW5864=m
-CONFIG_VIDEO_TW68=m
-CONFIG_VIDEO_TW686X=m
-
-#
-# Media capture/analog TV support
-#
-CONFIG_VIDEO_IVTV=m
-CONFIG_VIDEO_IVTV_ALSA=m
-CONFIG_VIDEO_FB_IVTV=m
-# CONFIG_VIDEO_FB_IVTV_FORCE_PAT is not set
-CONFIG_VIDEO_HEXIUM_GEMINI=m
-CONFIG_VIDEO_HEXIUM_ORION=m
-CONFIG_VIDEO_MXB=m
-CONFIG_VIDEO_DT3155=m
-
-#
-# Media capture/analog/hybrid TV support
-#
-CONFIG_VIDEO_CX18=m
-CONFIG_VIDEO_CX18_ALSA=m
-CONFIG_VIDEO_CX23885=m
-CONFIG_MEDIA_ALTERA_CI=m
-CONFIG_VIDEO_CX25821=m
-CONFIG_VIDEO_CX25821_ALSA=m
-CONFIG_VIDEO_CX88=m
-CONFIG_VIDEO_CX88_ALSA=m
-CONFIG_VIDEO_CX88_BLACKBIRD=m
-CONFIG_VIDEO_CX88_DVB=m
-CONFIG_VIDEO_CX88_ENABLE_VP3054=y
-CONFIG_VIDEO_CX88_VP3054=m
-CONFIG_VIDEO_CX88_MPEG=m
-CONFIG_VIDEO_BT848=m
-CONFIG_DVB_BT8XX=m
-CONFIG_VIDEO_SAA7134=m
-CONFIG_VIDEO_SAA7134_ALSA=m
-CONFIG_VIDEO_SAA7134_RC=y
-CONFIG_VIDEO_SAA7134_DVB=m
-CONFIG_VIDEO_SAA7134_GO7007=m
-CONFIG_VIDEO_SAA7164=m
-# CONFIG_VIDEO_COBALT is not set
-
-#
-# Media digital TV PCI Adapters
-#
-CONFIG_DVB_BUDGET_CORE=m
-CONFIG_DVB_BUDGET=m
-CONFIG_DVB_BUDGET_CI=m
-CONFIG_DVB_BUDGET_AV=m
-CONFIG_DVB_B2C2_FLEXCOP_PCI=m
-# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
-CONFIG_DVB_PLUTO2=m
-CONFIG_DVB_DM1105=m
-CONFIG_DVB_PT1=m
-CONFIG_DVB_PT3=m
-CONFIG_MANTIS_CORE=m
-CONFIG_DVB_MANTIS=m
-CONFIG_DVB_HOPPER=m
-CONFIG_DVB_NGENE=m
-CONFIG_DVB_DDBRIDGE=m
-# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set
-CONFIG_DVB_SMIPCIE=m
-CONFIG_DVB_NETUP_UNIDVB=m
-CONFIG_VIDEO_IPU3_CIO2=m
-CONFIG_CIO2_BRIDGE=y
-CONFIG_RADIO_ADAPTERS=y
-CONFIG_RADIO_TEA575X=m
-CONFIG_RADIO_SI470X=m
-CONFIG_USB_SI470X=m
-CONFIG_I2C_SI470X=m
-CONFIG_RADIO_SI4713=m
-CONFIG_USB_SI4713=m
-CONFIG_PLATFORM_SI4713=m
-CONFIG_I2C_SI4713=m
-CONFIG_RADIO_SI476X=m
-CONFIG_USB_MR800=m
-CONFIG_USB_DSBR=m
-CONFIG_RADIO_MAXIRADIO=m
-CONFIG_RADIO_SHARK=m
-CONFIG_RADIO_SHARK2=m
-CONFIG_USB_KEENE=m
-CONFIG_USB_RAREMONO=m
-CONFIG_USB_MA901=m
-CONFIG_RADIO_TEA5764=m
-CONFIG_RADIO_SAA7706H=m
-CONFIG_RADIO_TEF6862=m
-CONFIG_RADIO_WL1273=m
-CONFIG_RADIO_WL128X=m
-CONFIG_MEDIA_COMMON_OPTIONS=y
-
-#
-# common driver options
-#
-CONFIG_VIDEO_CX2341X=m
-CONFIG_VIDEO_TVEEPROM=m
-CONFIG_TTPCI_EEPROM=m
-CONFIG_CYPRESS_FIRMWARE=m
-CONFIG_VIDEOBUF2_CORE=m
-CONFIG_VIDEOBUF2_V4L2=m
-CONFIG_VIDEOBUF2_MEMOPS=m
-CONFIG_VIDEOBUF2_DMA_CONTIG=m
-CONFIG_VIDEOBUF2_VMALLOC=m
-CONFIG_VIDEOBUF2_DMA_SG=m
-CONFIG_VIDEOBUF2_DVB=m
-CONFIG_DVB_B2C2_FLEXCOP=m
-CONFIG_VIDEO_SAA7146=m
-CONFIG_VIDEO_SAA7146_VV=m
-CONFIG_SMS_SIANO_MDTV=m
-CONFIG_SMS_SIANO_RC=y
-# CONFIG_SMS_SIANO_DEBUGFS is not set
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_CAFE_CCIC=m
-CONFIG_VIDEO_CADENCE=y
-CONFIG_VIDEO_CADENCE_CSI2RX=m
-CONFIG_VIDEO_CADENCE_CSI2TX=m
-CONFIG_VIDEO_ASPEED=m
-CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
-CONFIG_DVB_PLATFORM_DRIVERS=y
-CONFIG_SDR_PLATFORM_DRIVERS=y
-
-#
-# MMC/SDIO DVB adapters
-#
-CONFIG_SMS_SDIO_DRV=m
-
-#
-# FireWire (IEEE 1394) Adapters
-#
-CONFIG_DVB_FIREDTV=m
-CONFIG_DVB_FIREDTV_INPUT=y
-# end of Media drivers
-
-#
-# Media ancillary drivers
-#
-CONFIG_MEDIA_ATTACH=y
-
-#
-# IR I2C driver auto-selected by 'Autoselect ancillary drivers'
-#
-CONFIG_VIDEO_IR_I2C=m
-
-#
-# Audio decoders, processors and mixers
-#
-CONFIG_VIDEO_TVAUDIO=m
-CONFIG_VIDEO_TDA7432=m
-CONFIG_VIDEO_TDA9840=m
-# CONFIG_VIDEO_TDA1997X is not set
-CONFIG_VIDEO_TEA6415C=m
-CONFIG_VIDEO_TEA6420=m
-CONFIG_VIDEO_MSP3400=m
-CONFIG_VIDEO_CS3308=m
-CONFIG_VIDEO_CS5345=m
-CONFIG_VIDEO_CS53L32A=m
-# CONFIG_VIDEO_TLV320AIC23B is not set
-CONFIG_VIDEO_UDA1342=m
-CONFIG_VIDEO_WM8775=m
-CONFIG_VIDEO_WM8739=m
-CONFIG_VIDEO_VP27SMPX=m
-CONFIG_VIDEO_SONY_BTF_MPX=m
-# end of Audio decoders, processors and mixers
-
-#
-# RDS decoders
-#
-CONFIG_VIDEO_SAA6588=m
-# end of RDS decoders
-
-#
-# Video decoders
-#
-# CONFIG_VIDEO_ADV7180 is not set
-# CONFIG_VIDEO_ADV7183 is not set
-# CONFIG_VIDEO_ADV7604 is not set
-# CONFIG_VIDEO_ADV7842 is not set
-CONFIG_VIDEO_BT819=m
-CONFIG_VIDEO_BT856=m
-CONFIG_VIDEO_BT866=m
-CONFIG_VIDEO_ISL7998X=m
-CONFIG_VIDEO_KS0127=m
-# CONFIG_VIDEO_ML86V7667 is not set
-CONFIG_VIDEO_SAA7110=m
-CONFIG_VIDEO_SAA711X=m
-# CONFIG_VIDEO_TC358743 is not set
-# CONFIG_VIDEO_TVP514X is not set
-CONFIG_VIDEO_TVP5150=m
-# CONFIG_VIDEO_TVP7002 is not set
-CONFIG_VIDEO_TW2804=m
-CONFIG_VIDEO_TW9903=m
-CONFIG_VIDEO_TW9906=m
-# CONFIG_VIDEO_TW9910 is not set
-CONFIG_VIDEO_VPX3220=m
-
-#
-# Video and audio decoders
-#
-CONFIG_VIDEO_SAA717X=m
-CONFIG_VIDEO_CX25840=m
-# end of Video decoders
-
-#
-# Video encoders
-#
-CONFIG_VIDEO_SAA7127=m
-CONFIG_VIDEO_SAA7185=m
-CONFIG_VIDEO_ADV7170=m
-CONFIG_VIDEO_ADV7175=m
-# CONFIG_VIDEO_ADV7343 is not set
-# CONFIG_VIDEO_ADV7393 is not set
-# CONFIG_VIDEO_ADV7511 is not set
-# CONFIG_VIDEO_AD9389B is not set
-# CONFIG_VIDEO_AK881X is not set
-# CONFIG_VIDEO_THS8200 is not set
-# end of Video encoders
-
-#
-# Video improvement chips
-#
-CONFIG_VIDEO_UPD64031A=m
-CONFIG_VIDEO_UPD64083=m
-# end of Video improvement chips
-
-#
-# Audio/Video compression chips
-#
-CONFIG_VIDEO_SAA6752HS=m
-# end of Audio/Video compression chips
-
-#
-# SDR tuner chips
-#
-# CONFIG_SDR_MAX2175 is not set
-# end of SDR tuner chips
-
-#
-# Miscellaneous helper chips
-#
-# CONFIG_VIDEO_THS7303 is not set
-CONFIG_VIDEO_M52790=m
-# CONFIG_VIDEO_I2C is not set
-# CONFIG_VIDEO_ST_MIPID02 is not set
-# end of Miscellaneous helper chips
-
-#
-# Camera sensor devices
-#
-CONFIG_VIDEO_APTINA_PLL=m
-CONFIG_VIDEO_CCS_PLL=m
-CONFIG_VIDEO_HI556=m
-CONFIG_VIDEO_HI846=m
-CONFIG_VIDEO_HI847=m
-CONFIG_VIDEO_IMX208=m
-CONFIG_VIDEO_IMX214=m
-CONFIG_VIDEO_IMX219=m
-CONFIG_VIDEO_IMX258=m
-CONFIG_VIDEO_IMX274=m
-CONFIG_VIDEO_IMX290=m
-CONFIG_VIDEO_IMX319=m
-CONFIG_VIDEO_IMX355=m
-CONFIG_VIDEO_OV02A10=m
-CONFIG_VIDEO_OV08D10=m
-CONFIG_VIDEO_OV2640=m
-CONFIG_VIDEO_OV2659=m
-CONFIG_VIDEO_OV2680=m
-CONFIG_VIDEO_OV2685=m
-CONFIG_VIDEO_OV2740=m
-CONFIG_VIDEO_OV5647=m
-CONFIG_VIDEO_OV5648=m
-CONFIG_VIDEO_OV6650=m
-CONFIG_VIDEO_OV5670=m
-CONFIG_VIDEO_OV5675=m
-CONFIG_VIDEO_OV5695=m
-CONFIG_VIDEO_OV7251=m
-CONFIG_VIDEO_OV772X=m
-CONFIG_VIDEO_OV7640=m
-CONFIG_VIDEO_OV7670=m
-CONFIG_VIDEO_OV7740=m
-CONFIG_VIDEO_OV8856=m
-CONFIG_VIDEO_OV8865=m
-CONFIG_VIDEO_OV9640=m
-CONFIG_VIDEO_OV9650=m
-CONFIG_VIDEO_OV9734=m
-CONFIG_VIDEO_OV13858=m
-CONFIG_VIDEO_OV13B10=m
-CONFIG_VIDEO_VS6624=m
-CONFIG_VIDEO_MT9M001=m
-CONFIG_VIDEO_MT9M032=m
-CONFIG_VIDEO_MT9M111=m
-CONFIG_VIDEO_MT9P031=m
-CONFIG_VIDEO_MT9T001=m
-CONFIG_VIDEO_MT9T112=m
-CONFIG_VIDEO_MT9V011=m
-CONFIG_VIDEO_MT9V032=m
-CONFIG_VIDEO_MT9V111=m
-CONFIG_VIDEO_SR030PC30=m
-CONFIG_VIDEO_NOON010PC30=m
-CONFIG_VIDEO_OG01A1B=m
-CONFIG_VIDEO_M5MOLS=m
-CONFIG_VIDEO_MAX9271_LIB=m
-CONFIG_VIDEO_RDACM20=m
-CONFIG_VIDEO_RDACM21=m
-CONFIG_VIDEO_RJ54N1=m
-CONFIG_VIDEO_S5K6AA=m
-CONFIG_VIDEO_S5K6A3=m
-CONFIG_VIDEO_S5K4ECGX=m
-CONFIG_VIDEO_S5K5BAF=m
-CONFIG_VIDEO_CCS=m
-CONFIG_VIDEO_ET8EK8=m
-CONFIG_VIDEO_S5C73M3=m
-# end of Camera sensor devices
-
-#
-# Lens drivers
-#
-CONFIG_VIDEO_AD5820=m
-CONFIG_VIDEO_AK7375=m
-CONFIG_VIDEO_DW9714=m
-CONFIG_VIDEO_DW9768=m
-CONFIG_VIDEO_DW9807_VCM=m
-# end of Lens drivers
-
-#
-# Flash devices
-#
-CONFIG_VIDEO_ADP1653=m
-CONFIG_VIDEO_LM3560=m
-CONFIG_VIDEO_LM3646=m
-# end of Flash devices
-
-#
-# SPI helper chips
-#
-# CONFIG_VIDEO_GS1662 is not set
-# end of SPI helper chips
-
-#
-# Media SPI Adapters
-#
-CONFIG_CXD2880_SPI_DRV=m
-# end of Media SPI Adapters
-
-CONFIG_MEDIA_TUNER=m
-
-#
-# Customize TV tuners
-#
-CONFIG_MEDIA_TUNER_SIMPLE=m
-CONFIG_MEDIA_TUNER_TDA18250=m
-CONFIG_MEDIA_TUNER_TDA8290=m
-CONFIG_MEDIA_TUNER_TDA827X=m
-CONFIG_MEDIA_TUNER_TDA18271=m
-CONFIG_MEDIA_TUNER_TDA9887=m
-CONFIG_MEDIA_TUNER_TEA5761=m
-CONFIG_MEDIA_TUNER_TEA5767=m
-CONFIG_MEDIA_TUNER_MSI001=m
-CONFIG_MEDIA_TUNER_MT20XX=m
-CONFIG_MEDIA_TUNER_MT2060=m
-CONFIG_MEDIA_TUNER_MT2063=m
-CONFIG_MEDIA_TUNER_MT2266=m
-CONFIG_MEDIA_TUNER_MT2131=m
-CONFIG_MEDIA_TUNER_QT1010=m
-CONFIG_MEDIA_TUNER_XC2028=m
-CONFIG_MEDIA_TUNER_XC5000=m
-CONFIG_MEDIA_TUNER_XC4000=m
-CONFIG_MEDIA_TUNER_MXL5005S=m
-CONFIG_MEDIA_TUNER_MXL5007T=m
-CONFIG_MEDIA_TUNER_MC44S803=m
-CONFIG_MEDIA_TUNER_MAX2165=m
-CONFIG_MEDIA_TUNER_TDA18218=m
-CONFIG_MEDIA_TUNER_FC0011=m
-CONFIG_MEDIA_TUNER_FC0012=m
-CONFIG_MEDIA_TUNER_FC0013=m
-CONFIG_MEDIA_TUNER_TDA18212=m
-CONFIG_MEDIA_TUNER_E4000=m
-CONFIG_MEDIA_TUNER_FC2580=m
-CONFIG_MEDIA_TUNER_M88RS6000T=m
-CONFIG_MEDIA_TUNER_TUA9001=m
-CONFIG_MEDIA_TUNER_SI2157=m
-CONFIG_MEDIA_TUNER_IT913X=m
-CONFIG_MEDIA_TUNER_R820T=m
-CONFIG_MEDIA_TUNER_MXL301RF=m
-CONFIG_MEDIA_TUNER_QM1D1C0042=m
-CONFIG_MEDIA_TUNER_QM1D1B0004=m
-CONFIG_MEDIA_TUNER_AV201X=m
-CONFIG_MEDIA_TUNER_STV6120=m
-# end of Customize TV tuners
-
-#
-# Customise DVB Frontends
-#
-
-#
-# Multistandard (satellite) frontends
-#
-CONFIG_DVB_STB0899=m
-CONFIG_DVB_STB6100=m
-CONFIG_DVB_STV090x=m
-CONFIG_DVB_STV0910=m
-CONFIG_DVB_STV6110x=m
-CONFIG_DVB_STV6111=m
-CONFIG_DVB_MXL5XX=m
-CONFIG_DVB_M88DS3103=m
-
-#
-# Multistandard (cable + terrestrial) frontends
-#
-CONFIG_DVB_DRXK=m
-CONFIG_DVB_TDA18271C2DD=m
-CONFIG_DVB_SI2165=m
-CONFIG_DVB_MN88472=m
-CONFIG_DVB_MN88473=m
-
-#
-# DVB-S (satellite) frontends
-#
-CONFIG_DVB_CX24110=m
-CONFIG_DVB_CX24123=m
-CONFIG_DVB_MT312=m
-CONFIG_DVB_ZL10036=m
-CONFIG_DVB_ZL10039=m
-CONFIG_DVB_S5H1420=m
-CONFIG_DVB_STV0288=m
-CONFIG_DVB_STB6000=m
-CONFIG_DVB_STV0299=m
-CONFIG_DVB_STV6110=m
-CONFIG_DVB_STV0900=m
-CONFIG_DVB_TDA8083=m
-CONFIG_DVB_TDA10086=m
-CONFIG_DVB_TDA8261=m
-CONFIG_DVB_VES1X93=m
-CONFIG_DVB_TUNER_ITD1000=m
-CONFIG_DVB_TUNER_CX24113=m
-CONFIG_DVB_TDA826X=m
-CONFIG_DVB_TUA6100=m
-CONFIG_DVB_CX24116=m
-CONFIG_DVB_CX24117=m
-CONFIG_DVB_CX24120=m
-CONFIG_DVB_SI21XX=m
-CONFIG_DVB_TS2020=m
-CONFIG_DVB_DS3000=m
-CONFIG_DVB_MB86A16=m
-CONFIG_DVB_TDA10071=m
-
-#
-# DVB-T (terrestrial) frontends
-#
-CONFIG_DVB_SP887X=m
-CONFIG_DVB_CX22700=m
-CONFIG_DVB_CX22702=m
-# CONFIG_DVB_S5H1432 is not set
-CONFIG_DVB_DRXD=m
-CONFIG_DVB_L64781=m
-CONFIG_DVB_TDA1004X=m
-CONFIG_DVB_NXT6000=m
-CONFIG_DVB_MT352=m
-CONFIG_DVB_ZL10353=m
-CONFIG_DVB_DIB3000MB=m
-CONFIG_DVB_DIB3000MC=m
-CONFIG_DVB_DIB7000M=m
-CONFIG_DVB_DIB7000P=m
-# CONFIG_DVB_DIB9000 is not set
-CONFIG_DVB_TDA10048=m
-CONFIG_DVB_AF9013=m
-CONFIG_DVB_EC100=m
-CONFIG_DVB_STV0367=m
-CONFIG_DVB_CXD2820R=m
-CONFIG_DVB_CXD2841ER=m
-CONFIG_DVB_RTL2830=m
-CONFIG_DVB_RTL2832=m
-CONFIG_DVB_RTL2832_SDR=m
-CONFIG_DVB_SI2168=m
-CONFIG_DVB_AS102_FE=m
-CONFIG_DVB_ZD1301_DEMOD=m
-CONFIG_DVB_GP8PSK_FE=m
-# CONFIG_DVB_CXD2880 is not set
-
-#
-# DVB-C (cable) frontends
-#
-CONFIG_DVB_VES1820=m
-CONFIG_DVB_TDA10021=m
-CONFIG_DVB_TDA10023=m
-CONFIG_DVB_STV0297=m
-
-#
-# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
-#
-CONFIG_DVB_NXT200X=m
-CONFIG_DVB_OR51211=m
-CONFIG_DVB_OR51132=m
-CONFIG_DVB_BCM3510=m
-CONFIG_DVB_LGDT330X=m
-CONFIG_DVB_LGDT3305=m
-CONFIG_DVB_LGDT3306A=m
-CONFIG_DVB_LG2160=m
-CONFIG_DVB_S5H1409=m
-CONFIG_DVB_AU8522=m
-CONFIG_DVB_AU8522_DTV=m
-CONFIG_DVB_AU8522_V4L=m
-CONFIG_DVB_S5H1411=m
-CONFIG_DVB_MXL692=m
-
-#
-# ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_S921=m
-CONFIG_DVB_DIB8000=m
-CONFIG_DVB_MB86A20S=m
-
-#
-# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
-#
-CONFIG_DVB_TC90522=m
-# CONFIG_DVB_MN88443X is not set
-
-#
-# Digital terrestrial only tuners/PLL
-#
-CONFIG_DVB_PLL=m
-CONFIG_DVB_TUNER_DIB0070=m
-CONFIG_DVB_TUNER_DIB0090=m
-
-#
-# SEC control devices for DVB-S
-#
-CONFIG_DVB_DRX39XYJ=m
-CONFIG_DVB_LNBH25=m
-# CONFIG_DVB_LNBH29 is not set
-CONFIG_DVB_LNBP21=m
-CONFIG_DVB_LNBP22=m
-CONFIG_DVB_ISL6405=m
-CONFIG_DVB_ISL6421=m
-CONFIG_DVB_ISL6422=m
-CONFIG_DVB_ISL6423=m
-CONFIG_DVB_A8293=m
-# CONFIG_DVB_LGS8GL5 is not set
-CONFIG_DVB_LGS8GXX=m
-CONFIG_DVB_ATBM8830=m
-CONFIG_DVB_TDA665x=m
-CONFIG_DVB_IX2505V=m
-CONFIG_DVB_M88RS2000=m
-CONFIG_DVB_AF9033=m
-CONFIG_DVB_TAS2101=m
-CONFIG_DVB_HORUS3A=m
-CONFIG_DVB_ASCOT2E=m
-CONFIG_DVB_HELENE=m
-
-#
-# Common Interface (EN50221) controller drivers
-#
-CONFIG_DVB_CXD2099=m
-CONFIG_DVB_SP2=m
-# end of Customise DVB Frontends
-# end of Media ancillary drivers
-
-#
-# Graphics support
-#
-CONFIG_AGP=m
-CONFIG_AGP_AMD64=m
-CONFIG_AGP_INTEL=m
-CONFIG_AGP_SIS=m
-CONFIG_AGP_VIA=m
-CONFIG_INTEL_GTT=m
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-CONFIG_VGA_SWITCHEROO=y
-CONFIG_DRM=m
-CONFIG_DRM_MIPI_DBI=m
-CONFIG_DRM_DP_AUX_CHARDEV=y
-# CONFIG_DRM_DEBUG_SELFTEST is not set
-CONFIG_DRM_KMS_HELPER=m
-# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
-# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
-# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
-# CONFIG_DRM_DP_CEC is not set
-CONFIG_DRM_TTM=m
-CONFIG_DRM_VRAM_HELPER=m
-CONFIG_DRM_TTM_HELPER=m
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-CONFIG_DRM_SCHED=m
-
-#
-# I2C encoder or helper chips
-#
-CONFIG_DRM_I2C_CH7006=m
-CONFIG_DRM_I2C_SIL164=m
-CONFIG_DRM_I2C_NXP_TDA998X=m
-CONFIG_DRM_I2C_NXP_TDA9950=m
-# end of I2C encoder or helper chips
-
-#
-# ARM devices
-#
-# end of ARM devices
-
-CONFIG_DRM_RADEON=m
-# CONFIG_DRM_RADEON_USERPTR is not set
-CONFIG_DRM_AMDGPU=m
-CONFIG_DRM_AMDGPU_SI=y
-CONFIG_DRM_AMDGPU_CIK=y
-CONFIG_DRM_AMDGPU_USERPTR=y
-
-#
-# ACP (Audio CoProcessor) Configuration
-#
-CONFIG_DRM_AMD_ACP=y
-# end of ACP (Audio CoProcessor) Configuration
-
-#
-# Display Engine Configuration
-#
-CONFIG_DRM_AMD_DC=y
-CONFIG_DRM_AMD_DC_DCN=y
-CONFIG_DRM_AMD_DC_HDCP=y
-CONFIG_DRM_AMD_DC_SI=y
-CONFIG_DRM_AMD_SECURE_DISPLAY=y
-# end of Display Engine Configuration
-
-CONFIG_HSA_AMD=y
-CONFIG_DRM_NOUVEAU=m
-CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT=y
-CONFIG_NOUVEAU_DEBUG=5
-CONFIG_NOUVEAU_DEBUG_DEFAULT=3
-# CONFIG_NOUVEAU_DEBUG_MMU is not set
-# CONFIG_NOUVEAU_DEBUG_PUSH is not set
-CONFIG_DRM_NOUVEAU_BACKLIGHT=y
-# CONFIG_DRM_I915 is not set
-CONFIG_DRM_VGEM=m
-CONFIG_DRM_VKMS=m
-CONFIG_DRM_VMWGFX=m
-CONFIG_DRM_VMWGFX_FBCON=y
-CONFIG_DRM_VMWGFX_MKSSTATS=y
-# CONFIG_DRM_GMA500 is not set
-CONFIG_DRM_PANEL_MIPI_DBI=m
-CONFIG_DRM_UDL=m
-CONFIG_DRM_AST=m
-# CONFIG_DRM_MGAG200 is not set
-CONFIG_DRM_QXL=m
-CONFIG_DRM_VIRTIO_GPU=m
-CONFIG_DRM_PANEL=y
-
-#
-# Display Panels
-#
-CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m
-# end of Display Panels
-
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_PANEL_BRIDGE=y
-
-#
-# Display Interface Bridges
-#
-CONFIG_DRM_ANALOGIX_ANX78XX=m
-CONFIG_DRM_ANALOGIX_DP=m
-# end of Display Interface Bridges
-
-CONFIG_DRM_ETNAVIV=m
-CONFIG_DRM_ETNAVIV_THERMAL=y
-CONFIG_DRM_BOCHS=m
-CONFIG_DRM_CIRRUS_QEMU=m
-CONFIG_DRM_GM12U320=m
-CONFIG_DRM_SIMPLEDRM=y
-CONFIG_TINYDRM_HX8357D=m
-CONFIG_TINYDRM_ILI9225=m
-CONFIG_TINYDRM_ILI9341=m
-CONFIG_TINYDRM_ILI9486=m
-CONFIG_TINYDRM_MI0283QT=m
-CONFIG_TINYDRM_REPAPER=m
-CONFIG_TINYDRM_ST7586=m
-CONFIG_TINYDRM_ST7735R=m
-CONFIG_DRM_VBOXVIDEO=m
-CONFIG_DRM_GUD=m
-CONFIG_DRM_SSD130X=m
-CONFIG_DRM_SSD130X_I2C=m
-CONFIG_DRM_SPRD=m
-CONFIG_DRM_HYPERV=m
-CONFIG_DRM_LEGACY=y
-# CONFIG_DRM_TDFX is not set
-# CONFIG_DRM_R128 is not set
-# CONFIG_DRM_MGA is not set
-# CONFIG_DRM_SIS is not set
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-CONFIG_DRM_EXPORT_FOR_TESTS=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m
-CONFIG_DRM_LIB_RANDOM=y
-
-#
-# Frame buffer Devices
-#
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_NOTIFY=y
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-CONFIG_FB_BOOT_VESA_SUPPORT=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SYS_FILLRECT=m
-CONFIG_FB_SYS_COPYAREA=m
-CONFIG_FB_SYS_IMAGEBLIT=m
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-CONFIG_FB_SYS_FOPS=m
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_BACKLIGHT=m
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_CIRRUS is not set
-# CONFIG_FB_PM2 is not set
-# CONFIG_FB_CYBER2000 is not set
-# CONFIG_FB_ARC is not set
-# CONFIG_FB_ASILIANT is not set
-# CONFIG_FB_IMSTT is not set
-# CONFIG_FB_VGA16 is not set
-# CONFIG_FB_UVESA is not set
-CONFIG_FB_VESA=y
-# CONFIG_FB_EFI is not set
-# CONFIG_FB_N411 is not set
-# CONFIG_FB_HGA is not set
-# CONFIG_FB_OPENCORES is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-# CONFIG_FB_I740 is not set
-# CONFIG_FB_LE80578 is not set
-# CONFIG_FB_INTEL is not set
-# CONFIG_FB_MATROX is not set
-# CONFIG_FB_RADEON is not set
-# CONFIG_FB_ATY128 is not set
-# CONFIG_FB_ATY is not set
-# CONFIG_FB_S3 is not set
-# CONFIG_FB_SAVAGE is not set
-# CONFIG_FB_SIS is not set
-# CONFIG_FB_VIA is not set
-# CONFIG_FB_NEOMAGIC is not set
-# CONFIG_FB_KYRO is not set
-# CONFIG_FB_3DFX is not set
-# CONFIG_FB_VOODOO1 is not set
-# CONFIG_FB_VT8623 is not set
-# CONFIG_FB_TRIDENT is not set
-# CONFIG_FB_ARK is not set
-# CONFIG_FB_PM3 is not set
-# CONFIG_FB_CARMINE is not set
-# CONFIG_FB_SM501 is not set
-# CONFIG_FB_SMSCUFX is not set
-# CONFIG_FB_UDL is not set
-# CONFIG_FB_IBM_GXT4500 is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-# CONFIG_FB_HYPERV is not set
-# CONFIG_FB_SIMPLE is not set
-# CONFIG_FB_SSD1307 is not set
-# CONFIG_FB_SM712 is not set
-# end of Frame buffer Devices
-
-#
-# Backlight & LCD device support
-#
-CONFIG_LCD_CLASS_DEVICE=m
-CONFIG_LCD_L4F00242T03=m
-CONFIG_LCD_LMS283GF05=m
-CONFIG_LCD_LTV350QV=m
-CONFIG_LCD_ILI922X=m
-CONFIG_LCD_ILI9320=m
-CONFIG_LCD_TDO24M=m
-CONFIG_LCD_VGG2432A4=m
-CONFIG_LCD_PLATFORM=m
-CONFIG_LCD_AMS369FG06=m
-CONFIG_LCD_LMS501KF03=m
-CONFIG_LCD_HX8357=m
-CONFIG_LCD_OTM3225A=m
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_KTD253=m
-CONFIG_BACKLIGHT_LM3533=m
-CONFIG_BACKLIGHT_PWM=m
-CONFIG_BACKLIGHT_MT6370=m
-CONFIG_BACKLIGHT_DA9052=m
-CONFIG_BACKLIGHT_MT6370=m
-CONFIG_BACKLIGHT_APPLE=m
-CONFIG_BACKLIGHT_QCOM_WLED=m
-CONFIG_BACKLIGHT_RT4831=m
-CONFIG_BACKLIGHT_SAHARA=m
-CONFIG_BACKLIGHT_WM831X=m
-CONFIG_BACKLIGHT_ADP8860=m
-CONFIG_BACKLIGHT_ADP8870=m
-CONFIG_BACKLIGHT_PCF50633=m
-CONFIG_BACKLIGHT_LM3630A=m
-CONFIG_BACKLIGHT_LM3639=m
-CONFIG_BACKLIGHT_LP855X=m
-CONFIG_BACKLIGHT_SKY81452=m
-CONFIG_BACKLIGHT_GPIO=m
-CONFIG_BACKLIGHT_LV5207LP=m
-CONFIG_BACKLIGHT_BD6107=m
-CONFIG_BACKLIGHT_ARCXCNN=m
-CONFIG_BACKLIGHT_RAVE_SP=m
-# end of Backlight & LCD device support
-
-CONFIG_HDMI=y
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DUMMY_CONSOLE_COLUMNS=80
-CONFIG_DUMMY_CONSOLE_ROWS=25
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
-# end of Console display driver support
-
-# CONFIG_LOGO is not set
-# end of Graphics support
-
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_PCM_ELD=y
-CONFIG_SND_PCM_IEC958=y
-CONFIG_SND_DMAENGINE_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_SEQ_DEVICE=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_PCM_TIMER=y
-CONFIG_SND_HRTIMER=m
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_MAX_CARDS=32
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_PROC_FS=y
-CONFIG_SND_VERBOSE_PROCFS=y
-CONFIG_SND_CTL_FAST_LOOKUP=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_CTL_INPUT_VALIDATION=y
-CONFIG_SND_VMASTER=y
-CONFIG_SND_DMA_SGBUF=y
-CONFIG_SND_CTL_LED=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_SEQUENCER_OSS=m
-CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
-CONFIG_SND_SEQ_MIDI_EVENT=m
-CONFIG_SND_SEQ_MIDI=m
-CONFIG_SND_SEQ_MIDI_EMUL=m
-CONFIG_SND_SEQ_VIRMIDI=m
-CONFIG_SND_MPU401_UART=m
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_OPL3_LIB_SEQ=m
-CONFIG_SND_VX_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_PCSP is not set
-CONFIG_SND_DUMMY=m
-CONFIG_SND_ALOOP=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_MTS64=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_PORTMAN2X4=m
-CONFIG_SND_AC97_POWER_SAVE=y
-CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
-CONFIG_SND_SB_COMMON=m
-CONFIG_SND_PCI=y
-CONFIG_SND_AD1889=m
-CONFIG_SND_ALS300=m
-CONFIG_SND_ALS4000=m
-CONFIG_SND_ALI5451=m
-CONFIG_SND_ASIHPI=m
-CONFIG_SND_ATIIXP=m
-CONFIG_SND_ATIIXP_MODEM=m
-CONFIG_SND_AU8810=m
-CONFIG_SND_AU8820=m
-CONFIG_SND_AU8830=m
-CONFIG_SND_AW2=m
-CONFIG_SND_AZT3328=m
-CONFIG_SND_BT87X=m
-CONFIG_SND_BT87X_OVERCLOCK=y
-CONFIG_SND_CA0106=m
-CONFIG_SND_CMIPCI=m
-CONFIG_SND_OXYGEN_LIB=m
-CONFIG_SND_OXYGEN=m
-CONFIG_SND_CS4281=m
-CONFIG_SND_CS46XX=m
-CONFIG_SND_CS46XX_NEW_DSP=y
-CONFIG_SND_CTXFI=m
-CONFIG_SND_DARLA20=m
-CONFIG_SND_GINA20=m
-CONFIG_SND_LAYLA20=m
-CONFIG_SND_DARLA24=m
-CONFIG_SND_GINA24=m
-CONFIG_SND_LAYLA24=m
-CONFIG_SND_MONA=m
-CONFIG_SND_MIA=m
-CONFIG_SND_ECHO3G=m
-CONFIG_SND_INDIGO=m
-CONFIG_SND_INDIGOIO=m
-CONFIG_SND_INDIGODJ=m
-CONFIG_SND_INDIGOIOX=m
-CONFIG_SND_INDIGODJX=m
-CONFIG_SND_EMU10K1=m
-CONFIG_SND_EMU10K1_SEQ=m
-CONFIG_SND_EMU10K1X=m
-CONFIG_SND_ENS1370=m
-CONFIG_SND_ENS1371=m
-CONFIG_SND_ES1938=m
-CONFIG_SND_ES1968=m
-CONFIG_SND_ES1968_INPUT=y
-CONFIG_SND_ES1968_RADIO=y
-CONFIG_SND_FM801=m
-CONFIG_SND_FM801_TEA575X_BOOL=y
-CONFIG_SND_HDSP=m
-CONFIG_SND_HDSPM=m
-CONFIG_SND_ICE1712=m
-CONFIG_SND_ICE1724=m
-CONFIG_SND_INTEL8X0=m
-CONFIG_SND_INTEL8X0M=m
-CONFIG_SND_KORG1212=m
-CONFIG_SND_LOLA=m
-CONFIG_SND_LX6464ES=m
-CONFIG_SND_MAESTRO3=m
-CONFIG_SND_MAESTRO3_INPUT=y
-CONFIG_SND_MIXART=m
-CONFIG_SND_NM256=m
-CONFIG_SND_PCXHR=m
-CONFIG_SND_RIPTIDE=m
-CONFIG_SND_RME32=m
-CONFIG_SND_RME96=m
-CONFIG_SND_RME9652=m
-CONFIG_SND_SONICVIBES=m
-CONFIG_SND_TRIDENT=m
-CONFIG_SND_VIA82XX=m
-CONFIG_SND_VIA82XX_MODEM=m
-CONFIG_SND_VIRTUOSO=m
-CONFIG_SND_VX222=m
-CONFIG_SND_YMFPCI=m
-
-#
-# HD-Audio
-#
-CONFIG_SND_HDA=m
-CONFIG_SND_HDA_GENERIC_LEDS=y
-CONFIG_SND_HDA_INTEL=m
-CONFIG_SND_HDA_HWDEP=y
-CONFIG_SND_HDA_RECONFIG=y
-CONFIG_SND_HDA_INPUT_BEEP=y
-CONFIG_SND_HDA_INPUT_BEEP_MODE=1
-CONFIG_SND_HDA_PATCH_LOADER=y
-CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m
-CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m
-CONFIG_SND_HDA_CODEC_REALTEK=m
-CONFIG_SND_HDA_CODEC_ANALOG=m
-CONFIG_SND_HDA_CODEC_SIGMATEL=m
-CONFIG_SND_HDA_CODEC_VIA=m
-CONFIG_SND_HDA_CODEC_HDMI=m
-CONFIG_SND_HDA_CODEC_CIRRUS=m
-CONFIG_SND_HDA_CODEC_CS8409=m
-CONFIG_SND_HDA_CODEC_CONEXANT=m
-CONFIG_SND_HDA_CODEC_CA0110=m
-CONFIG_SND_HDA_CODEC_CA0132=m
-CONFIG_SND_HDA_CODEC_CA0132_DSP=y
-CONFIG_SND_HDA_CODEC_CMEDIA=m
-CONFIG_SND_HDA_CODEC_SI3054=m
-CONFIG_SND_HDA_GENERIC=m
-CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
-# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
-# end of HD-Audio
-
-CONFIG_SND_HDA_CORE=m
-CONFIG_SND_HDA_DSP_LOADER=y
-CONFIG_SND_HDA_COMPONENT=y
-CONFIG_SND_HDA_PREALLOC_SIZE=0
-CONFIG_SND_INTEL_NHLT=y
-CONFIG_SND_INTEL_DSP_CONFIG=m
-CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m
-CONFIG_SND_SPI=y
-CONFIG_SND_USB=y
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
-CONFIG_SND_USB_UA101=m
-CONFIG_SND_USB_USX2Y=m
-CONFIG_SND_USB_CAIAQ=m
-CONFIG_SND_USB_CAIAQ_INPUT=y
-CONFIG_SND_USB_US122L=m
-CONFIG_SND_USB_6FIRE=m
-CONFIG_SND_USB_HIFACE=m
-CONFIG_SND_BCD2000=m
-CONFIG_SND_USB_LINE6=m
-CONFIG_SND_USB_POD=m
-CONFIG_SND_USB_PODHD=m
-CONFIG_SND_USB_TONEPORT=m
-CONFIG_SND_USB_VARIAX=m
-CONFIG_SND_FIREWIRE=y
-CONFIG_SND_FIREWIRE_LIB=m
-CONFIG_SND_DICE=m
-CONFIG_SND_OXFW=m
-CONFIG_SND_ISIGHT=m
-CONFIG_SND_FIREWORKS=m
-CONFIG_SND_BEBOB=m
-CONFIG_SND_FIREWIRE_DIGI00X=m
-CONFIG_SND_FIREWIRE_TASCAM=m
-CONFIG_SND_FIREWIRE_MOTU=m
-CONFIG_SND_FIREFACE=m
-CONFIG_SND_PCMCIA=y
-CONFIG_SND_VXPOCKET=m
-CONFIG_SND_PDAUDIOCF=m
-CONFIG_SND_SOC=m
-CONFIG_SND_SOC_AC97_BUS=y
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_ACPI=m
-CONFIG_SND_SOC_ADI=m
-CONFIG_SND_SOC_ADI_AXI_I2S=m
-CONFIG_SND_SOC_ADI_AXI_SPDIF=m
-CONFIG_SND_SOC_AMD_ACP=m
-CONFIG_SND_SOC_AMD_ST_ES8336_MACH=m
-CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m
-CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m
-CONFIG_SND_SOC_AMD_ACP3x=m
-CONFIG_SND_SOC_AMD_RV_RT5682_MACH=m
-CONFIG_SND_SOC_AMD_RENOIR=m
-CONFIG_SND_SOC_AMD_RENOIR_MACH=m
-CONFIG_SND_SOC_AMD_ACP5x=m
-CONFIG_SND_SOC_AMD_VANGOGH_MACH=m
-CONFIG_SND_SOC_AMD_ACP6x=m
-CONFIG_SND_SOC_AMD_YC_MACH=m
-CONFIG_SND_SOC_AMD_ACP_COMMON=m
-CONFIG_SND_SOC_AMD_ACP_PCI=m
-CONFIG_SND_SOC_AMD_ACP_I2S=m
-CONFIG_SND_SOC_AMD_ACP_PCM=m
-CONFIG_SND_AMD_ASOC_RENOIR=m
-CONFIG_SND_AMD_ASOC_REMBRANDT=m
-CONFIG_SND_SOC_AMD_MACH_COMMON=m
-CONFIG_SND_SOC_AMD_LEGACY_MACH=m
-CONFIG_SND_SOC_AMD_SOF_MACH=m
-CONFIG_SND_SOC_AMD_RPL_ACP6x=m
-CONFIG_SND_SOC_AMD_PS_MACH=m
-CONFIG_SND_SOC_AMD_PS=m
-CONFIG_SND_ATMEL_SOC=m
-CONFIG_SND_BCM63XX_I2S_WHISTLER=m
-CONFIG_SND_DESIGNWARE_I2S=m
-CONFIG_SND_DESIGNWARE_PCM=y
-
-#
-# SoC Audio for Freescale CPUs
-#
-
-#
-# Common SoC Audio options for Freescale CPUs:
-#
-CONFIG_SND_SOC_FSL_ASRC=m
-CONFIG_SND_SOC_FSL_SAI=m
-CONFIG_SND_SOC_FSL_MQS=m
-CONFIG_SND_SOC_FSL_AUDMIX=m
-CONFIG_SND_SOC_FSL_SSI=m
-CONFIG_SND_SOC_FSL_SPDIF=m
-CONFIG_SND_SOC_FSL_ESAI=m
-CONFIG_SND_SOC_FSL_MICFIL=m
-CONFIG_SND_SOC_FSL_EASRC=m
-CONFIG_SND_SOC_FSL_XCVR=m
-CONFIG_SND_SOC_FSL_RPMSG=m
-CONFIG_SND_SOC_IMX_AUDMUX=m
-# end of SoC Audio for Freescale CPUs
-
-CONFIG_SND_I2S_HI6210_I2S=m
-CONFIG_SND_SOC_IMG=y
-CONFIG_SND_SOC_IMG_I2S_IN=m
-CONFIG_SND_SOC_IMG_I2S_OUT=m
-CONFIG_SND_SOC_IMG_PARALLEL_OUT=m
-CONFIG_SND_SOC_IMG_SPDIF_IN=m
-CONFIG_SND_SOC_IMG_SPDIF_OUT=m
-CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m
-# CONFIG_SND_SOC_INTEL_SST_TOPLEVEL is not set
-CONFIG_SND_SOC_INTEL_AVS=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=m
-CONFIG_SND_SOC_MTK_BTCVSD=m
-CONFIG_SND_SOC_SOF_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_PCI=m
-CONFIG_SND_SOC_SOF_ACPI=m
-# CONFIG_SND_SOC_SOF_DEBUG_PROBES is not set
-# CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT is not set
-CONFIG_SND_SOC_SOF_AMD_TOPLEVEL=m
-CONFIG_SND_SOC_SOF_AMD_RENOIR=m
-CONFIG_SND_SOC_SOF_AMD_REMBRANDT=m
-# CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL is not set
-
-#
-# STMicroelectronics STM32 SOC audio support
-#
-# end of STMicroelectronics STM32 SOC audio support
-
-CONFIG_SND_SOC_XILINX_I2S=m
-CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
-CONFIG_SND_SOC_XILINX_SPDIF=m
-CONFIG_SND_SOC_XTFPGA_I2S=m
-CONFIG_SND_SOC_I2C_AND_SPI=m
-
-#
-# CODEC drivers
-#
-CONFIG_SND_SOC_AC97_CODEC=m
-CONFIG_SND_SOC_ADAU_UTILS=m
-CONFIG_SND_SOC_ADAU1372=m
-CONFIG_SND_SOC_ADAU1372_I2C=m
-CONFIG_SND_SOC_ADAU1372_SPI=m
-CONFIG_SND_SOC_ADAU1701=m
-CONFIG_SND_SOC_ADAU17X1=m
-CONFIG_SND_SOC_ADAU1761=m
-CONFIG_SND_SOC_ADAU1761_I2C=m
-CONFIG_SND_SOC_ADAU1761_SPI=m
-CONFIG_SND_SOC_ADAU7002=m
-CONFIG_SND_SOC_ADAU7118=m
-CONFIG_SND_SOC_ADAU7118_HW=m
-CONFIG_SND_SOC_ADAU7118_I2C=m
-CONFIG_SND_SOC_AK4104=m
-CONFIG_SND_SOC_AK4118=m
-CONFIG_SND_SOC_AK4458=m
-CONFIG_SND_SOC_AK4554=m
-CONFIG_SND_SOC_AK4613=m
-CONFIG_SND_SOC_AK4642=m
-CONFIG_SND_SOC_AK5386=m
-CONFIG_SND_SOC_AK5558=m
-CONFIG_SND_SOC_ALC5623=m
-CONFIG_SND_SOC_AW8738=m
-CONFIG_SND_SOC_BD28623=m
-# CONFIG_SND_SOC_BT_SCO is not set
-CONFIG_SND_SOC_CROS_EC_CODEC=m
-CONFIG_SND_SOC_CS35L32=m
-CONFIG_SND_SOC_CS35L33=m
-CONFIG_SND_SOC_CS35L34=m
-CONFIG_SND_SOC_CS35L35=m
-CONFIG_SND_SOC_CS35L36=m
-CONFIG_SND_SOC_CS35L41_SPI=m
-CONFIG_SND_SOC_CS35L41_I2C=m
-CONFIG_SND_SOC_CS42L42=m
-CONFIG_SND_SOC_CS42L51=m
-CONFIG_SND_SOC_CS42L51_I2C=m
-CONFIG_SND_SOC_CS42L52=m
-CONFIG_SND_SOC_CS42L56=m
-CONFIG_SND_SOC_CS42L73=m
-CONFIG_SND_SOC_CS42L83=m
-CONFIG_SND_SOC_CS4234=m
-CONFIG_SND_SOC_CS4265=m
-CONFIG_SND_SOC_CS4270=m
-CONFIG_SND_SOC_CS4271=m
-CONFIG_SND_SOC_CS4271_I2C=m
-CONFIG_SND_SOC_CS4271_SPI=m
-CONFIG_SND_SOC_CS42XX8=m
-CONFIG_SND_SOC_CS42XX8_I2C=m
-CONFIG_SND_SOC_CS43130=m
-CONFIG_SND_SOC_CS4341=m
-CONFIG_SND_SOC_CS4349=m
-CONFIG_SND_SOC_CS53L30=m
-CONFIG_SND_SOC_CX2072X=m
-CONFIG_SND_SOC_DA7213=m
-CONFIG_SND_SOC_DA7219=m
-CONFIG_SND_SOC_DMIC=m
-CONFIG_SND_SOC_HDMI_CODEC=m
-CONFIG_SND_SOC_ES7134=m
-CONFIG_SND_SOC_ES7241=m
-CONFIG_SND_SOC_ES8316=m
-CONFIG_SND_SOC_ES8326=m
-CONFIG_SND_SOC_ES8328=m
-CONFIG_SND_SOC_ES8328_I2C=m
-CONFIG_SND_SOC_ES8328_SPI=m
-CONFIG_SND_SOC_GTM601=m
-CONFIG_SND_SOC_HDA=m
-CONFIG_SND_SOC_ICS43432=m
-CONFIG_SND_SOC_INNO_RK3036=m
-CONFIG_SND_SOC_MAX98088=m
-CONFIG_SND_SOC_MAX98357A=m
-CONFIG_SND_SOC_MAX98504=m
-CONFIG_SND_SOC_MAX9867=m
-CONFIG_SND_SOC_MAX98927=m
-CONFIG_SND_SOC_MAX98520=m
-CONFIG_SND_SOC_MAX98373=m
-CONFIG_SND_SOC_MAX98373_I2C=m
-CONFIG_SND_SOC_MAX98373_SDW=m
-CONFIG_SND_SOC_MAX98390=m
-CONFIG_SND_SOC_MAX9860=m
-CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
-CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
-CONFIG_SND_SOC_PCM1681=m
-CONFIG_SND_SOC_PCM1789=m
-CONFIG_SND_SOC_PCM1789_I2C=m
-CONFIG_SND_SOC_PCM179X=m
-CONFIG_SND_SOC_PCM179X_I2C=m
-CONFIG_SND_SOC_PCM179X_SPI=m
-CONFIG_SND_SOC_PCM186X=m
-CONFIG_SND_SOC_PCM186X_I2C=m
-CONFIG_SND_SOC_PCM186X_SPI=m
-CONFIG_SND_SOC_PCM3060=m
-CONFIG_SND_SOC_PCM3060_I2C=m
-CONFIG_SND_SOC_PCM3060_SPI=m
-CONFIG_SND_SOC_PCM3168A=m
-CONFIG_SND_SOC_PCM3168A_I2C=m
-CONFIG_SND_SOC_PCM3168A_SPI=m
-CONFIG_SND_SOC_PCM5102A=m
-CONFIG_SND_SOC_PCM512x=m
-CONFIG_SND_SOC_PCM512x_I2C=m
-CONFIG_SND_SOC_PCM512x_SPI=m
-CONFIG_SND_SOC_RK3328=m
-CONFIG_SND_SOC_RL6231=m
-CONFIG_SND_SOC_RT1015=m
-CONFIG_SND_SOC_RT1015P=m
-CONFIG_SND_SOC_RT1019=m
-CONFIG_SND_SOC_RT1308_SDW=m
-CONFIG_SND_SOC_RT1316_SDW=m
-CONFIG_SND_SOC_RT5616=m
-CONFIG_SND_SOC_RT5631=m
-CONFIG_SND_SOC_RT5640=m
-CONFIG_SND_SOC_RT5645=m
-CONFIG_SND_SOC_RT5659=m
-CONFIG_SND_SOC_RT5682=m
-CONFIG_SND_SOC_RT5682_I2C=m
-CONFIG_SND_SOC_RT5682_SDW=m
-CONFIG_SND_SOC_RT5682S=m
-CONFIG_SND_SOC_RT700=m
-CONFIG_SND_SOC_RT700_SDW=m
-CONFIG_SND_SOC_RT711=m
-CONFIG_SND_SOC_RT711_SDW=m
-CONFIG_SND_SOC_RT711_SDCA_SDW=m
-CONFIG_SND_SOC_RT715=m
-CONFIG_SND_SOC_RT715_SDW=m
-CONFIG_SND_SOC_RT715_SDCA_SDW=m
-CONFIG_SND_SOC_RT9120=m
-CONFIG_SND_SOC_SDW_MOCKUP=m
-CONFIG_SND_SOC_SGTL5000=m
-CONFIG_SND_SOC_SI476X=m
-CONFIG_SND_SOC_SIGMADSP=m
-CONFIG_SND_SOC_SIGMADSP_I2C=m
-CONFIG_SND_SOC_SIGMADSP_REGMAP=m
-CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
-CONFIG_SND_SOC_SIMPLE_MUX=m
-CONFIG_SND_SOC_SPDIF=m
-CONFIG_SND_SOC_SRC4XXX_I2C=m
-CONFIG_SND_SOC_SSM2305=m
-CONFIG_SND_SOC_SSM2518=m
-CONFIG_SND_SOC_SSM2602=m
-CONFIG_SND_SOC_SSM2602_SPI=m
-CONFIG_SND_SOC_SSM2602_I2C=m
-CONFIG_SND_SOC_SSM4567=m
-CONFIG_SND_SOC_STA32X=m
-CONFIG_SND_SOC_STA350=m
-CONFIG_SND_SOC_STI_SAS=m
-CONFIG_SND_SOC_TAS2552=m
-CONFIG_SND_SOC_TAS2562=m
-CONFIG_SND_SOC_TAS2764=m
-CONFIG_SND_SOC_TAS2770=m
-CONFIG_SND_SOC_TAS2780=m
-CONFIG_USB_ONBOARD_HUB=m
-CONFIG_SND_SOC_WSA883X=m
-CONFIG_SND_SOC_TAS5086=m
-CONFIG_SND_SOC_TAS571X=m
-CONFIG_SND_SOC_TAS5720=m
-CONFIG_SND_SOC_TAS5805M=m
-CONFIG_SND_SOC_TAS6424=m
-CONFIG_SND_SOC_TDA7419=m
-CONFIG_SND_SOC_TFA9879=m
-CONFIG_SND_SOC_TFA989X=m
-CONFIG_SND_SOC_TLV320AIC23=m
-CONFIG_SND_SOC_TLV320AIC23_I2C=m
-CONFIG_SND_SOC_TLV320AIC23_SPI=m
-CONFIG_SND_SOC_TLV320AIC31XX=m
-CONFIG_SND_SOC_TLV320AIC32X4=m
-CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
-CONFIG_SND_SOC_TLV320AIC32X4_SPI=m
-CONFIG_SND_SOC_TLV320AIC3X=m
-CONFIG_SND_SOC_TLV320AIC3X_I2C=m
-CONFIG_SND_SOC_TLV320AIC3X_SPI=m
-CONFIG_SND_SOC_TLV320ADCX140=m
-CONFIG_SND_SOC_TS3A227E=m
-CONFIG_SND_SOC_TSCS42XX=m
-CONFIG_SND_SOC_TSCS454=m
-CONFIG_SND_SOC_UDA1334=m
-CONFIG_SND_SOC_WCD9335=m
-CONFIG_SND_SOC_WCD_MBHC=m
-CONFIG_SND_SOC_WCD934X=m
-CONFIG_SND_SOC_WCD938X=m
-CONFIG_SND_SOC_WCD938X_SDW=m
-CONFIG_SND_SOC_WM8510=m
-CONFIG_SND_SOC_WM8523=m
-CONFIG_SND_SOC_WM8524=m
-CONFIG_SND_SOC_WM8580=m
-CONFIG_SND_SOC_WM8711=m
-CONFIG_SND_SOC_WM8728=m
-CONFIG_SND_SOC_WM8731=m
-CONFIG_SND_SOC_WM8737=m
-CONFIG_SND_SOC_WM8741=m
-CONFIG_SND_SOC_WM8750=m
-CONFIG_SND_SOC_WM8753=m
-CONFIG_SND_SOC_WM8770=m
-CONFIG_SND_SOC_WM8776=m
-CONFIG_SND_SOC_WM8782=m
-CONFIG_SND_SOC_WM8804=m
-CONFIG_SND_SOC_WM8804_I2C=m
-CONFIG_SND_SOC_WM8804_SPI=m
-CONFIG_SND_SOC_WM8903=m
-CONFIG_SND_SOC_WM8904=m
-CONFIG_SND_SOC_WM8960=m
-CONFIG_SND_SOC_WM8962=m
-CONFIG_SND_SOC_WM8974=m
-CONFIG_SND_SOC_WM8978=m
-CONFIG_SND_SOC_WM8985=m
-CONFIG_SND_SOC_WSA881X=m
-CONFIG_SND_SOC_ZL38060=m
-CONFIG_SND_SOC_MAX9759=m
-CONFIG_SND_SOC_MT6351=m
-CONFIG_SND_SOC_MT6358=m
-CONFIG_SND_SOC_MT6660=m
-CONFIG_SND_SOC_NAU8315=m
-CONFIG_SND_SOC_NAU8540=m
-CONFIG_SND_SOC_NAU8810=m
-CONFIG_SND_SOC_NAU8821=m
-CONFIG_SND_SOC_NAU8822=m
-CONFIG_SND_SOC_NAU8824=m
-CONFIG_SND_SOC_TPA6130A2=m
-CONFIG_SND_SOC_LPASS_WSA_MACRO=m
-CONFIG_SND_SOC_LPASS_VA_MACRO=m
-CONFIG_SND_SOC_LPASS_RX_MACRO=m
-CONFIG_SND_SOC_LPASS_TX_MACRO=m
-# end of CODEC drivers
-
-CONFIG_SND_SIMPLE_CARD_UTILS=m
-CONFIG_SND_SIMPLE_CARD=m
-CONFIG_SND_X86=y
-CONFIG_SND_SYNTH_EMUX=m
-CONFIG_SND_VIRTIO=m
-CONFIG_AC97_BUS=m
-
-#
-# HID support
-#
-CONFIG_HID=m
-CONFIG_HID_BATTERY_STRENGTH=y
-CONFIG_HIDRAW=y
-CONFIG_UHID=m
-CONFIG_HID_GENERIC=m
-
-#
-# Special HID drivers
-#
-CONFIG_HID_A4TECH=m
-CONFIG_HID_ACCUTOUCH=m
-CONFIG_HID_ACRUX=m
-CONFIG_HID_ACRUX_FF=y
-CONFIG_HID_APPLE=m
-CONFIG_HID_APPLEIR=m
-CONFIG_HID_ASUS=m
-CONFIG_HID_AUREAL=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_BETOP_FF=m
-CONFIG_HID_BIGBEN_FF=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CORSAIR=m
-CONFIG_HID_COUGAR=m
-CONFIG_HID_MACALLY=m
-CONFIG_HID_PRODIKEYS=m
-CONFIG_HID_CMEDIA=m
-CONFIG_HID_CP2112=m
-CONFIG_HID_CREATIVE_SB0540=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_DRAGONRISE=m
-CONFIG_DRAGONRISE_FF=y
-CONFIG_HID_EMS_FF=m
-CONFIG_HID_ELAN=m
-CONFIG_HID_ELECOM=m
-CONFIG_HID_ELO=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_FT260=m
-CONFIG_HID_GEMBIRD=m
-CONFIG_HID_GFRM=m
-CONFIG_HID_GLORIOUS=m
-CONFIG_HID_HOLTEK=m
-CONFIG_HOLTEK_FF=y
-CONFIG_HID_GOOGLE_HAMMER=m
-CONFIG_HID_VIVALDI=m
-CONFIG_HID_GT683R=m
-CONFIG_HID_KEYTOUCH=m
-CONFIG_HID_KYE=m
-CONFIG_HID_UCLOGIC=m
-CONFIG_HID_WALTOP=m
-CONFIG_HID_VIEWSONIC=m
-CONFIG_HID_VRC2=m
-CONFIG_HID_XIAOMI=m
-CONFIG_HID_GYRATION=m
-CONFIG_HID_ICADE=m
-CONFIG_HID_ITE=m
-CONFIG_HID_JABRA=m
-CONFIG_HID_TWINHAN=m
-CONFIG_HID_KENSINGTON=m
-CONFIG_HID_LCPOWER=m
-CONFIG_HID_LED=m
-CONFIG_HID_LENOVO=m
-CONFIG_HID_LOGITECH=m
-CONFIG_HID_LOGITECH_DJ=m
-CONFIG_HID_LOGITECH_HIDPP=m
-CONFIG_LOGITECH_FF=y
-CONFIG_LOGIRUMBLEPAD2_FF=y
-CONFIG_LOGIG940_FF=y
-CONFIG_LOGIWHEELS_FF=y
-CONFIG_HID_MAGICMOUSE=m
-CONFIG_HID_MALTRON=m
-CONFIG_HID_MAYFLASH=m
-CONFIG_HID_REDRAGON=m
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_MULTITOUCH=m
-CONFIG_HID_NINTENDO=m
-CONFIG_NINTENDO_FF=y
-CONFIG_HID_NTI=m
-CONFIG_HID_NTRIG=m
-CONFIG_HID_ORTEK=m
-CONFIG_HID_PANTHERLORD=m
-CONFIG_PANTHERLORD_FF=y
-CONFIG_HID_PENMOUNT=m
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_PICOLCD=m
-# CONFIG_HID_PICOLCD_FB is not set
-# CONFIG_HID_PICOLCD_BACKLIGHT is not set
-# CONFIG_HID_PICOLCD_LCD is not set
-# CONFIG_HID_PICOLCD_LEDS is not set
-# CONFIG_HID_PICOLCD_CIR is not set
-CONFIG_HID_PLANTRONICS=m
-CONFIG_HID_PLAYSTATION=m
-CONFIG_HID_PXRC=m
-CONFIG_HID_RAZER=m
-CONFIG_PLAYSTATION_FF=y
-CONFIG_HID_PRIMAX=m
-CONFIG_HID_RETRODE=m
-CONFIG_HID_ROCCAT=m
-CONFIG_HID_SAITEK=m
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SEMITEK=m
-CONFIG_HID_SIGMAMICRO=m
-CONFIG_HID_SONY=m
-CONFIG_SONY_FF=y
-CONFIG_HID_SPEEDLINK=m
-CONFIG_HID_STEAM=m
-CONFIG_HID_STEELSERIES=m
-CONFIG_HID_SUNPLUS=m
-CONFIG_HID_RMI=m
-CONFIG_HID_GREENASIA=m
-CONFIG_GREENASIA_FF=y
-CONFIG_HID_HYPERV_MOUSE=m
-CONFIG_HID_SMARTJOYPLUS=m
-CONFIG_SMARTJOYPLUS_FF=y
-CONFIG_HID_TIVO=m
-CONFIG_HID_TOPSEED=m
-CONFIG_HID_TOPRE=m
-CONFIG_HID_THINGM=m
-CONFIG_HID_THRUSTMASTER=m
-CONFIG_THRUSTMASTER_FF=y
-CONFIG_HID_UDRAW_PS3=m
-CONFIG_HID_U2FZERO=m
-CONFIG_HID_WACOM=m
-# CONFIG_HID_WIIMOTE is not set
-# CONFIG_HID_XINMO is not set
-# CONFIG_HID_ZEROPLUS is not set
-# CONFIG_HID_ZYDACRON is not set
-CONFIG_HID_SENSOR_HUB=m
-CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
-CONFIG_HID_ALPS=m
-CONFIG_HID_MCP2221=m
-# end of Special HID drivers
-
-#
-# USB HID support
-#
-CONFIG_USB_HID=m
-CONFIG_HID_PID=y
-CONFIG_USB_HIDDEV=y
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# end of USB HID Boot Protocol drivers
-# end of USB HID support
-
-#
-# I2C HID support
-#
-CONFIG_I2C_HID_ACPI=m
-# end of I2C HID support
-
-CONFIG_I2C_HID_CORE=m
-
-#
-# Intel ISH HID support
-#
-# CONFIG_INTEL_ISH_HID is not set
-# end of Intel ISH HID support
-
-#
-# AMD SFH HID Support
-#
-CONFIG_AMD_SFH_HID=m
-# end of AMD SFH HID Support
-
-#
-# Surface System Aggregator Module HID support
-#
-CONFIG_SURFACE_HID=m
-CONFIG_SURFACE_KBD=m
-# end of Surface System Aggregator Module HID support
-
-CONFIG_SURFACE_HID_CORE=m
-# end of HID support
-
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_COMMON=m
-CONFIG_USB_LED_TRIG=y
-CONFIG_USB_ULPI_BUS=m
-CONFIG_USB_CONN_GPIO=m
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB=m
-CONFIG_USB_PCI=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEFAULT_PERSIST=y
-CONFIG_USB_FEW_INIT_RETRIES=y
-CONFIG_USB_DYNAMIC_MINORS=y
-CONFIG_USB_OTG=y
-# CONFIG_USB_OTG_PRODUCTLIST is not set
-# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
-CONFIG_USB_OTG_FSM=m
-CONFIG_USB_LEDS_TRIGGER_USBPORT=m
-CONFIG_USB_AUTOSUSPEND_DELAY=2
-CONFIG_USB_MON=m
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_C67X00_HCD=m
-CONFIG_USB_XHCI_HCD=m
-CONFIG_USB_XHCI_DBGCAP=y
-CONFIG_USB_XHCI_PCI=m
-CONFIG_USB_XHCI_PCI_RENESAS=m
-CONFIG_USB_XHCI_PLATFORM=m
-CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-CONFIG_USB_EHCI_PCI=m
-CONFIG_USB_EHCI_FSL=m
-CONFIG_USB_EHCI_HCD_NPCM7XX=m
-CONFIG_USB_EHCI_HCD_PLATFORM=m
-CONFIG_USB_OXU210HP_HCD=m
-CONFIG_USB_ISP116X_HCD=m
-CONFIG_USB_FOTG210_HCD=m
-CONFIG_USB_MAX3421_HCD=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_OHCI_HCD_PCI=m
-CONFIG_USB_OHCI_HCD_SSB=y
-CONFIG_USB_OHCI_HCD_PLATFORM=m
-CONFIG_USB_UHCI_HCD=m
-CONFIG_USB_U132_HCD=m
-CONFIG_USB_SL811_HCD=m
-# CONFIG_USB_SL811_HCD_ISO is not set
-CONFIG_USB_SL811_CS=m
-CONFIG_USB_R8A66597_HCD=m
-CONFIG_USB_HCD_BCMA=m
-CONFIG_USB_HCD_SSB=m
-# CONFIG_USB_HCD_TEST_MODE is not set
-
-#
-# USB Device Class drivers
-#
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_WDM=m
-CONFIG_USB_TMC=m
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-CONFIG_USB_STORAGE_REALTEK=m
-CONFIG_REALTEK_AUTOPM=y
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_ISD200=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_STORAGE_ALAUDA=m
-CONFIG_USB_STORAGE_ONETOUCH=m
-CONFIG_USB_STORAGE_KARMA=m
-CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-CONFIG_USB_STORAGE_ENE_UB6250=m
-CONFIG_USB_UAS=m
-
-#
-# USB Imaging devices
-#
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USBIP_CORE=m
-CONFIG_USBIP_VHCI_HCD=m
-CONFIG_USBIP_VHCI_HC_PORTS=8
-CONFIG_USBIP_VHCI_NR_HCS=1
-CONFIG_USBIP_HOST=m
-CONFIG_USBIP_VUDC=m
-# CONFIG_USBIP_DEBUG is not set
-CONFIG_USB_CDNS_SUPPORT=m
-CONFIG_USB_CDNS_HOST=y
-CONFIG_USB_CDNS3=m
-CONFIG_USB_CDNS3_GADGET=y
-CONFIG_USB_CDNS3_HOST=y
-CONFIG_USB_CDNS3_PCI_WRAP=m
-CONFIG_USB_CDNSP_PCI=m
-CONFIG_USB_CDNSP_GADGET=y
-CONFIG_USB_CDNSP_HOST=y
-CONFIG_USB_MUSB_HDRC=m
-# CONFIG_USB_MUSB_HOST is not set
-# CONFIG_USB_MUSB_GADGET is not set
-CONFIG_USB_MUSB_DUAL_ROLE=y
-
-#
-# Platform Glue Layer
-#
-
-#
-# MUSB DMA mode
-#
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_DWC3=m
-# CONFIG_USB_DWC3_ULPI is not set
-# CONFIG_USB_DWC3_HOST is not set
-# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_DUAL_ROLE=y
-
-#
-# Platform Glue Driver Support
-#
-CONFIG_USB_DWC3_PCI=m
-CONFIG_USB_DWC3_HAPS=m
-CONFIG_USB_DWC2=m
-# CONFIG_USB_DWC2_HOST is not set
-
-#
-# Gadget/Dual-role mode requires USB Gadget support to be enabled
-#
-# CONFIG_USB_DWC2_PERIPHERAL is not set
-CONFIG_USB_DWC2_DUAL_ROLE=y
-CONFIG_USB_DWC2_PCI=m
-# CONFIG_USB_DWC2_DEBUG is not set
-# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
-CONFIG_USB_CHIPIDEA=m
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_PCI=m
-CONFIG_USB_CHIPIDEA_MSM=m
-CONFIG_USB_CHIPIDEA_GENERIC=m
-CONFIG_USB_ISP1760=m
-CONFIG_USB_ISP1760_HCD=y
-CONFIG_USB_ISP1761_UDC=y
-# CONFIG_USB_ISP1760_HOST_ROLE is not set
-# CONFIG_USB_ISP1760_GADGET_ROLE is not set
-CONFIG_USB_ISP1760_DUAL_ROLE=y
-
-#
-# USB port drivers
-#
-CONFIG_USB_USS720=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_SIMPLE=m
-CONFIG_USB_SERIAL_AIRCABLE=m
-CONFIG_USB_SERIAL_ARK3116=m
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_CH341=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CP210X=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_F81232=m
-CONFIG_USB_SERIAL_F8153X=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_IUU=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_METRO=m
-CONFIG_USB_SERIAL_MOS7720=m
-CONFIG_USB_SERIAL_MOS7715_PARPORT=y
-CONFIG_USB_SERIAL_MOS7840=m
-CONFIG_USB_SERIAL_MXUPORT=m
-CONFIG_USB_SERIAL_NAVMAN=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_OTI6858=m
-CONFIG_USB_SERIAL_QCAUX=m
-CONFIG_USB_SERIAL_QUALCOMM=m
-CONFIG_USB_SERIAL_SPCP8X5=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_SAFE_PADDED=y
-CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-CONFIG_USB_SERIAL_SYMBOL=m
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_WWAN=m
-CONFIG_USB_SERIAL_OPTION=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_SERIAL_OPTICON=m
-CONFIG_USB_SERIAL_XSENS_MT=m
-CONFIG_USB_SERIAL_WISHBONE=m
-CONFIG_USB_SERIAL_SSU100=m
-CONFIG_USB_SERIAL_QT2=m
-# CONFIG_USB_SERIAL_UPD78F0730 is not set
-CONFIG_USB_SERIAL_XR=m
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_ADUTUX=m
-CONFIG_USB_SEVSEG=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_CYPRESS_CY7C63=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_IDMOUSE=m
-CONFIG_USB_FTDI_ELAN=m
-CONFIG_USB_APPLEDISPLAY=m
-CONFIG_USB_QCOM_EUD=m
-CONFIG_APPLE_MFI_FASTCHARGE=m
-CONFIG_USB_SISUSBVGA=m
-CONFIG_USB_LD=m
-CONFIG_USB_TRANCEVIBRATOR=m
-CONFIG_USB_IOWARRIOR=m
-CONFIG_USB_TEST=m
-CONFIG_USB_EHSET_TEST_FIXTURE=m
-CONFIG_USB_ISIGHTFW=m
-CONFIG_USB_YUREX=m
-CONFIG_USB_EZUSB_FX2=m
-CONFIG_USB_HUB_USB251XB=m
-CONFIG_USB_HSIC_USB3503=m
-CONFIG_USB_HSIC_USB4604=m
-CONFIG_USB_LINK_LAYER_TEST=m
-CONFIG_USB_CHAOSKEY=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_CXACRU=m
-CONFIG_USB_UEAGLEATM=m
-CONFIG_USB_XUSBATM=m
-
-#
-# USB Physical Layer drivers
-#
-CONFIG_USB_PHY=y
-CONFIG_NOP_USB_XCEIV=m
-CONFIG_USB_GPIO_VBUS=m
-CONFIG_TAHVO_USB=m
-CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y
-CONFIG_USB_ISP1301=m
-# end of USB Physical Layer drivers
-
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
-CONFIG_U_SERIAL_CONSOLE=y
-
-#
-# USB Peripheral Controller
-#
-CONFIG_USB_FOTG210_UDC=m
-CONFIG_USB_GR_UDC=m
-CONFIG_USB_R8A66597=m
-CONFIG_USB_PXA27X=m
-CONFIG_USB_MV_UDC=m
-CONFIG_USB_MV_U3D=m
-CONFIG_USB_SNP_CORE=m
-CONFIG_USB_M66592=m
-CONFIG_USB_BDC_UDC=m
-CONFIG_USB_AMD5536UDC=m
-CONFIG_USB_NET2272=m
-CONFIG_USB_NET2272_DMA=y
-CONFIG_USB_NET2280=m
-CONFIG_USB_GOKU=m
-CONFIG_USB_EG20T=m
-CONFIG_USB_MAX3420_UDC=m
-# CONFIG_USB_DUMMY_HCD is not set
-# end of USB Peripheral Controller
-
-CONFIG_USB_LIBCOMPOSITE=m
-CONFIG_USB_F_ACM=m
-CONFIG_USB_F_SS_LB=m
-CONFIG_USB_U_SERIAL=m
-CONFIG_USB_U_ETHER=m
-CONFIG_USB_U_AUDIO=m
-CONFIG_USB_F_SERIAL=m
-CONFIG_USB_F_OBEX=m
-CONFIG_USB_F_NCM=m
-CONFIG_USB_F_ECM=m
-CONFIG_USB_F_PHONET=m
-CONFIG_USB_F_EEM=m
-CONFIG_USB_F_SUBSET=m
-CONFIG_USB_F_RNDIS=m
-CONFIG_USB_F_MASS_STORAGE=m
-CONFIG_USB_F_FS=m
-CONFIG_USB_F_UAC1=m
-CONFIG_USB_F_UAC2=m
-CONFIG_USB_F_UVC=m
-CONFIG_USB_F_MIDI=m
-CONFIG_USB_F_HID=m
-CONFIG_USB_F_PRINTER=m
-CONFIG_USB_F_TCM=m
-CONFIG_USB_CONFIGFS=m
-CONFIG_USB_CONFIGFS_SERIAL=y
-CONFIG_USB_CONFIGFS_ACM=y
-CONFIG_USB_CONFIGFS_OBEX=y
-CONFIG_USB_CONFIGFS_NCM=y
-CONFIG_USB_CONFIGFS_ECM=y
-CONFIG_USB_CONFIGFS_ECM_SUBSET=y
-CONFIG_USB_CONFIGFS_RNDIS=y
-CONFIG_USB_CONFIGFS_EEM=y
-CONFIG_USB_CONFIGFS_PHONET=y
-CONFIG_USB_CONFIGFS_MASS_STORAGE=y
-CONFIG_USB_CONFIGFS_F_LB_SS=y
-CONFIG_USB_CONFIGFS_F_FS=y
-CONFIG_USB_CONFIGFS_F_UAC1=y
-# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
-CONFIG_USB_CONFIGFS_F_UAC2=y
-CONFIG_USB_CONFIGFS_F_MIDI=y
-CONFIG_USB_CONFIGFS_F_HID=y
-CONFIG_USB_CONFIGFS_F_UVC=y
-CONFIG_USB_CONFIGFS_F_PRINTER=y
-CONFIG_USB_CONFIGFS_F_TCM=y
-
-#
-# USB Gadget precomposed configurations
-#
-CONFIG_USB_ZERO=m
-CONFIG_USB_ZERO_HNPTEST=y
-CONFIG_USB_AUDIO=m
-CONFIG_GADGET_UAC1=y
-# CONFIG_GADGET_UAC1_LEGACY is not set
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-CONFIG_USB_ETH_EEM=y
-CONFIG_USB_G_NCM=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FUNCTIONFS=m
-CONFIG_USB_FUNCTIONFS_ETH=y
-CONFIG_USB_FUNCTIONFS_RNDIS=y
-CONFIG_USB_FUNCTIONFS_GENERIC=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_GADGET_TARGET=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_MIDI_GADGET=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_NOKIA=m
-CONFIG_USB_G_ACM_MS=m
-CONFIG_USB_G_MULTI=m
-CONFIG_USB_G_MULTI_RNDIS=y
-CONFIG_USB_G_MULTI_CDC=y
-CONFIG_USB_G_HID=m
-# CONFIG_USB_G_DBGP is not set
-CONFIG_USB_G_WEBCAM=m
-CONFIG_USB_RAW_GADGET=m
-# end of USB Gadget precomposed configurations
-
-CONFIG_TYPEC=m
-CONFIG_TYPEC_TCPM=m
-CONFIG_TYPEC_TCPCI=m
-CONFIG_TYPEC_RT1711H=m
-CONFIG_TYPEC_MT6360=m
-CONFIG_TYPEC_TCPCI_MT6370=m
-CONFIG_TYPEC_TCPCI_MAXIM=m
-CONFIG_TYPEC_FUSB302=m
-CONFIG_TYPEC_UCSI=m
-CONFIG_UCSI_CCG=m
-CONFIG_UCSI_ACPI=m
-CONFIG_UCSI_STM32G0=m
-CONFIG_TYPEC_TPS6598X=m
-CONFIG_TYPEC_ANX7411=m
-CONFIG_TYPEC_RT1719=m
-CONFIG_TYPEC_HD3SS3220=m
-CONFIG_TYPEC_STUSB160X=m
-CONFIG_TYPEC_WUSB3801=m
-CONFIG_TYPEC_EXTCON=m
-
-#
-# USB Type-C Multiplexer/DeMultiplexer Switch support
-#
-CONFIG_TYPEC_MUX_PI3USB30532=m
-CONFIG_TYPEC_MUX_INTEL_PMC=m
-# end of USB Type-C Multiplexer/DeMultiplexer Switch support
-
-#
-# USB Type-C Alternate Mode drivers
-#
-CONFIG_TYPEC_DP_ALTMODE=m
-CONFIG_TYPEC_NVIDIA_ALTMODE=m
-# end of USB Type-C Alternate Mode drivers
-
-CONFIG_USB_ROLE_SWITCH=m
-# CONFIG_USB_ROLES_INTEL_XHCI is not set
-CONFIG_MMC=m
-CONFIG_MMC_BLOCK=m
-CONFIG_MMC_BLOCK_MINORS=8
-CONFIG_SDIO_UART=m
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_SDHCI=m
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PCI=m
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI_ACPI=m
-CONFIG_MMC_SDHCI_PLTFM=m
-CONFIG_MMC_SDHCI_F_SDH30=m
-CONFIG_MMC_WBSD=m
-CONFIG_MMC_ALCOR=m
-CONFIG_MMC_TIFM_SD=m
-CONFIG_MMC_SPI=m
-CONFIG_MMC_SDRICOH_CS=m
-CONFIG_MMC_CB710=m
-CONFIG_MMC_VIA_SDMMC=m
-CONFIG_MMC_VUB300=m
-CONFIG_MMC_USHC=m
-CONFIG_MMC_USDHI6ROL0=m
-CONFIG_MMC_REALTEK_PCI=m
-CONFIG_MMC_REALTEK_USB=m
-CONFIG_MMC_CQHCI=m
-CONFIG_MMC_HSQ=m
-# CONFIG_MMC_TOSHIBA_PCI is not set
-CONFIG_MMC_MTK=m
-CONFIG_MMC_SDHCI_XENON=m
-CONFIG_MEMSTICK=m
-# CONFIG_MEMSTICK_DEBUG is not set
-
-#
-# MemoryStick drivers
-#
-# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
-CONFIG_MSPRO_BLOCK=m
-CONFIG_MS_BLOCK=m
-
-#
-# MemoryStick Host Controller Drivers
-#
-CONFIG_MEMSTICK_TIFM_MS=m
-CONFIG_MEMSTICK_JMICRON_38X=m
-CONFIG_MEMSTICK_R592=m
-CONFIG_MEMSTICK_REALTEK_PCI=m
-CONFIG_MEMSTICK_REALTEK_USB=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_CLASS_FLASH=m
-CONFIG_LEDS_CLASS_MULTICOLOR=m
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-
-#
-# LED drivers
-#
-CONFIG_LEDS_APU=m
-CONFIG_LEDS_LM3530=m
-CONFIG_LEDS_LM3532=m
-CONFIG_LEDS_LM3533=m
-CONFIG_LEDS_LM3642=m
-CONFIG_LEDS_MT6323=m
-CONFIG_LEDS_PCA9532=m
-CONFIG_LEDS_PCA9532_GPIO=y
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_LP3944=m
-CONFIG_LEDS_LP3952=m
-CONFIG_LEDS_LP50XX=m
-CONFIG_LEDS_CLEVO_MAIL=m
-CONFIG_LEDS_PCA955X=m
-# CONFIG_LEDS_PCA955X_GPIO is not set
-CONFIG_LEDS_PCA963X=m
-CONFIG_LEDS_WM831X_STATUS=m
-CONFIG_LEDS_DA9052=m
-CONFIG_LEDS_DAC124S085=m
-CONFIG_LEDS_PWM=m
-CONFIG_LEDS_REGULATOR=m
-CONFIG_LEDS_BD2802=m
-CONFIG_LEDS_INTEL_SS4200=m
-CONFIG_LEDS_LT3593=m
-CONFIG_LEDS_MC13783=m
-CONFIG_LEDS_TCA6507=m
-CONFIG_LEDS_TLC591XX=m
-CONFIG_LEDS_LM355x=m
-CONFIG_LEDS_MENF21BMC=m
-CONFIG_LEDS_IS31FL319X=m
-
-#
-# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
-#
-CONFIG_LEDS_BLINKM=m
-CONFIG_LEDS_MLXCPLD=m
-CONFIG_LEDS_MLXREG=m
-CONFIG_LEDS_USER=m
-CONFIG_LEDS_NIC78BX=m
-CONFIG_LEDS_TI_LMU_COMMON=m
-CONFIG_LEDS_BCM63138=m
-CONFIG_LEDS_LM36274=m
-CONFIG_LEDS_TPS6105X=m
-
-#
-# Flash and Torch LED drivers
-#
-CONFIG_LEDS_AS3645A=m
-CONFIG_LEDS_LM3601X=m
-CONFIG_LEDS_RT8515=m
-CONFIG_LEDS_SGM3140=m
-CONFIG_LEDS_SIEMENS_SIMATIC_IPC=m
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_ONESHOT=m
-CONFIG_LEDS_TRIGGER_DISK=y
-# CONFIG_LEDS_TRIGGER_MTD is not set
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_LEDS_TRIGGER_BACKLIGHT=m
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_ACTIVITY=m
-CONFIG_LEDS_TRIGGER_GPIO=m
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-CONFIG_LEDS_TRIGGER_TRANSIENT=m
-CONFIG_LEDS_TRIGGER_CAMERA=m
-CONFIG_LEDS_TRIGGER_PANIC=y
-CONFIG_LEDS_TRIGGER_NETDEV=m
-CONFIG_LEDS_TRIGGER_PATTERN=m
-CONFIG_LEDS_TRIGGER_AUDIO=m
-CONFIG_LEDS_TRIGGER_TTY=m
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_A11Y_BRAILLE_CONSOLE=y
-
-#
-# Speakup console speech
-#
-CONFIG_SPEAKUP=m
-CONFIG_SPEAKUP_SYNTH_ACNTSA=m
-CONFIG_SPEAKUP_SYNTH_APOLLO=m
-CONFIG_SPEAKUP_SYNTH_AUDPTR=m
-CONFIG_SPEAKUP_SYNTH_BNS=m
-CONFIG_SPEAKUP_SYNTH_DECTLK=m
-CONFIG_SPEAKUP_SYNTH_DECEXT=m
-CONFIG_SPEAKUP_SYNTH_LTLK=m
-CONFIG_SPEAKUP_SYNTH_SOFT=m
-CONFIG_SPEAKUP_SYNTH_SPKOUT=m
-CONFIG_SPEAKUP_SYNTH_TXPRT=m
-# CONFIG_SPEAKUP_SYNTH_DUMMY is not set
-# end of Speakup console speech
-
-CONFIG_INFINIBAND=m
-CONFIG_INFINIBAND_USER_MAD=m
-CONFIG_INFINIBAND_USER_ACCESS=m
-CONFIG_INFINIBAND_USER_MEM=y
-CONFIG_INFINIBAND_ON_DEMAND_PAGING=y
-CONFIG_INFINIBAND_ADDR_TRANS=y
-CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y
-CONFIG_INFINIBAND_VIRT_DMA=y
-CONFIG_INFINIBAND_MTHCA=m
-# CONFIG_INFINIBAND_MTHCA_DEBUG is not set
-CONFIG_INFINIBAND_QIB=m
-CONFIG_INFINIBAND_CXGB4=m
-CONFIG_INFINIBAND_EFA=m
-CONFIG_INFINIBAND_ERDMA=m
-CONFIG_VIDEO_STKWEBCAM=m
-CONFIG_INFINIBAND_IRDMA=m
-CONFIG_MLX4_INFINIBAND=m
-CONFIG_MLX5_INFINIBAND=m
-CONFIG_INFINIBAND_OCRDMA=m
-CONFIG_INFINIBAND_VMWARE_PVRDMA=m
-CONFIG_INFINIBAND_BNXT_RE=m
-CONFIG_INFINIBAND_HFI1=m
-# CONFIG_HFI1_DEBUG_SDMA_ORDER is not set
-# CONFIG_SDMA_VERBOSITY is not set
-CONFIG_INFINIBAND_QEDR=m
-CONFIG_INFINIBAND_RDMAVT=m
-CONFIG_RDMA_RXE=m
-CONFIG_RDMA_SIW=m
-CONFIG_INFINIBAND_IPOIB=m
-CONFIG_INFINIBAND_IPOIB_CM=y
-# CONFIG_INFINIBAND_IPOIB_DEBUG is not set
-CONFIG_INFINIBAND_SRP=m
-CONFIG_INFINIBAND_SRPT=m
-CONFIG_INFINIBAND_ISER=m
-CONFIG_INFINIBAND_ISERT=m
-CONFIG_INFINIBAND_RTRS=m
-CONFIG_INFINIBAND_RTRS_CLIENT=m
-CONFIG_INFINIBAND_RTRS_SERVER=m
-CONFIG_INFINIBAND_OPA_VNIC=m
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EDAC=m
-CONFIG_EDAC_LEGACY_SYSFS=y
-# CONFIG_EDAC_DEBUG is not set
-CONFIG_EDAC_DECODE_MCE=y
-CONFIG_EDAC_GHES=y
-CONFIG_EDAC_AMD64=m
-# CONFIG_EDAC_E752X is not set
-# CONFIG_EDAC_I82975X is not set
-# CONFIG_EDAC_I3000 is not set
-# CONFIG_EDAC_I3200 is not set
-# CONFIG_EDAC_IE31200 is not set
-# CONFIG_EDAC_X38 is not set
-# CONFIG_EDAC_I5400 is not set
-# CONFIG_EDAC_I5000 is not set
-# CONFIG_EDAC_I5100 is not set
-# CONFIG_EDAC_I7300 is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-CONFIG_RTC_SYSTOHC=y
-CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-CONFIG_RTC_NVMEM=y
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-CONFIG_RTC_DRV_88PM80X=m
-CONFIG_RTC_DRV_ABB5ZES3=m
-CONFIG_RTC_DRV_ABEOZ9=m
-CONFIG_RTC_DRV_ABX80X=m
-CONFIG_RTC_DRV_DS1307=m
-# CONFIG_RTC_DRV_DS1307_CENTURY is not set
-CONFIG_RTC_DRV_DS1374=m
-CONFIG_RTC_DRV_DS1374_WDT=y
-CONFIG_RTC_DRV_DS1672=m
-CONFIG_RTC_DRV_MAX6900=m
-CONFIG_RTC_DRV_MAX8907=m
-CONFIG_RTC_DRV_RS5C372=m
-CONFIG_RTC_DRV_ISL1208=m
-CONFIG_RTC_DRV_ISL12022=m
-CONFIG_RTC_DRV_X1205=m
-CONFIG_RTC_DRV_PCF8523=m
-CONFIG_RTC_DRV_PCF85063=m
-CONFIG_RTC_DRV_PCF85363=m
-CONFIG_RTC_DRV_PCF8563=m
-CONFIG_RTC_DRV_PCF8583=m
-CONFIG_RTC_DRV_M41T80=m
-CONFIG_RTC_DRV_M41T80_WDT=y
-CONFIG_RTC_DRV_BQ32K=m
-CONFIG_RTC_DRV_S35390A=m
-CONFIG_RTC_DRV_FM3130=m
-CONFIG_RTC_DRV_RX8010=m
-CONFIG_RTC_DRV_RX8581=m
-CONFIG_RTC_DRV_RX8025=m
-CONFIG_RTC_DRV_EM3027=m
-CONFIG_RTC_DRV_RV3028=m
-CONFIG_RTC_DRV_RV3032=m
-CONFIG_RTC_DRV_RV8803=m
-CONFIG_RTC_DRV_SD3078=m
-
-#
-# SPI RTC drivers
-#
-CONFIG_RTC_DRV_M41T93=m
-CONFIG_RTC_DRV_M41T94=m
-CONFIG_RTC_DRV_DS1302=m
-CONFIG_RTC_DRV_DS1305=m
-CONFIG_RTC_DRV_DS1343=m
-CONFIG_RTC_DRV_DS1347=m
-CONFIG_RTC_DRV_DS1390=m
-CONFIG_RTC_DRV_MAX6916=m
-CONFIG_RTC_DRV_R9701=m
-CONFIG_RTC_DRV_RX4581=m
-CONFIG_RTC_DRV_RS5C348=m
-CONFIG_RTC_DRV_MAX6902=m
-CONFIG_RTC_DRV_PCF2123=m
-CONFIG_RTC_DRV_MCP795=m
-CONFIG_RTC_I2C_AND_SPI=m
-
-#
-# SPI and I2C RTC drivers
-#
-CONFIG_RTC_DRV_DS3232=m
-CONFIG_RTC_DRV_DS3232_HWMON=y
-CONFIG_RTC_DRV_PCF2127=m
-CONFIG_RTC_DRV_RV3029C2=m
-CONFIG_RTC_DRV_RV3029_HWMON=y
-CONFIG_RTC_DRV_RX6110=m
-
-#
-# Platform RTC drivers
-#
-CONFIG_RTC_DRV_CMOS=y
-CONFIG_RTC_DRV_DS1286=m
-CONFIG_RTC_DRV_DS1511=m
-CONFIG_RTC_DRV_DS1553=m
-CONFIG_RTC_DRV_DS1685_FAMILY=m
-CONFIG_RTC_DRV_DS1685=y
-# CONFIG_RTC_DRV_DS1689 is not set
-# CONFIG_RTC_DRV_DS17285 is not set
-# CONFIG_RTC_DRV_DS17485 is not set
-# CONFIG_RTC_DRV_DS17885 is not set
-CONFIG_RTC_DRV_DS1742=m
-CONFIG_RTC_DRV_DS2404=m
-CONFIG_RTC_DRV_DA9052=m
-CONFIG_RTC_DRV_DA9063=m
-CONFIG_RTC_DRV_STK17TA8=m
-CONFIG_RTC_DRV_M48T86=m
-CONFIG_RTC_DRV_M48T35=m
-CONFIG_RTC_DRV_M48T59=m
-CONFIG_RTC_DRV_MSM6242=m
-CONFIG_RTC_DRV_BQ4802=m
-CONFIG_RTC_DRV_RP5C01=m
-CONFIG_RTC_DRV_V3020=m
-CONFIG_RTC_DRV_OPTEE=m
-CONFIG_RTC_DRV_WM831X=m
-CONFIG_RTC_DRV_PCF50633=m
-# CONFIG_RTC_DRV_CROS_EC is not set
-
-#
-# on-CPU RTC drivers
-#
-CONFIG_RTC_DRV_FTRTC010=m
-CONFIG_RTC_DRV_PCAP=m
-CONFIG_RTC_DRV_MC13XXX=m
-CONFIG_RTC_DRV_MT6397=m
-
-#
-# HID Sensor RTC drivers
-#
-CONFIG_RTC_DRV_HID_SENSOR_TIME=m
-CONFIG_RTC_DRV_GOLDFISH=m
-CONFIG_RTC_DRV_WILCO_EC=m
-CONFIG_DMADEVICES=y
-# CONFIG_DMADEVICES_DEBUG is not set
-
-#
-# DMA Devices
-#
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DMA_ACPI=y
-CONFIG_ALTERA_MSGDMA=m
-# CONFIG_INTEL_IDMA64 is not set
-# CONFIG_INTEL_IDXD is not set
-# CONFIG_INTEL_IDXD_COMPAT is not set
-# CONFIG_INTEL_IOATDMA is not set
-CONFIG_PLX_DMA=m
-CONFIG_AMD_PTDMA=m
-CONFIG_QCOM_HIDMA_MGMT=m
-CONFIG_QCOM_HIDMA=m
-CONFIG_DW_DMAC_CORE=y
-CONFIG_DW_DMAC=m
-CONFIG_DW_DMAC_PCI=y
-CONFIG_DW_EDMA=m
-CONFIG_DW_EDMA_PCIE=m
-CONFIG_HSU_DMA=y
-CONFIG_SF_PDMA=m
-CONFIG_INTEL_LDMA=y
-
-#
-# DMA Clients
-#
-CONFIG_ASYNC_TX_DMA=y
-# CONFIG_DMATEST is not set
-
-#
-# DMABUF options
-#
-CONFIG_SYNC_FILE=y
-# CONFIG_SW_SYNC is not set
-# CONFIG_UDMABUF is not set
-# CONFIG_DMABUF_MOVE_NOTIFY is not set
-# CONFIG_DMABUF_DEBUG is not set
-CONFIG_DMABUF_SELFTESTS=m
-# CONFIG_DMABUF_HEAPS is not set
-# CONFIG_DMABUF_SYSFS_STATS is not set
-# end of DMABUF options
-
-CONFIG_AUXDISPLAY=y
-CONFIG_CHARLCD=m
-CONFIG_LINEDISP=m
-CONFIG_HD44780_COMMON=m
-CONFIG_HD44780=m
-CONFIG_KS0108=m
-CONFIG_KS0108_PORT=0x378
-CONFIG_KS0108_DELAY=2
-CONFIG_CFAG12864B=m
-CONFIG_CFAG12864B_RATE=20
-CONFIG_IMG_ASCII_LCD=m
-CONFIG_HT16K33=m
-CONFIG_LCD2S=m
-CONFIG_PARPORT_PANEL=m
-CONFIG_PANEL_PARPORT=0
-CONFIG_PANEL_PROFILE=5
-# CONFIG_PANEL_CHANGE_MESSAGE is not set
-# CONFIG_CHARLCD_BL_OFF is not set
-# CONFIG_CHARLCD_BL_ON is not set
-CONFIG_CHARLCD_BL_FLASH=y
-CONFIG_PANEL=m
-CONFIG_UIO=m
-CONFIG_UIO_CIF=m
-CONFIG_UIO_PDRV_GENIRQ=m
-CONFIG_UIO_DMEM_GENIRQ=m
-CONFIG_UIO_AEC=m
-CONFIG_UIO_SERCOS3=m
-CONFIG_UIO_PCI_GENERIC=m
-CONFIG_UIO_NETX=m
-CONFIG_UIO_PRUSS=m
-CONFIG_UIO_MF624=m
-CONFIG_UIO_HV_GENERIC=m
-CONFIG_UIO_DFL=m
-CONFIG_VFIO=m
-CONFIG_VFIO_IOMMU_TYPE1=m
-CONFIG_VFIO_VIRQFD=m
-# CONFIG_VFIO_NOIOMMU is not set
-CONFIG_VFIO_PCI_CORE=m
-CONFIG_VFIO_PCI_MMAP=y
-CONFIG_VFIO_PCI_INTX=y
-CONFIG_VFIO_PCI=m
-CONFIG_MLX5_VFIO_PCI=m
-CONFIG_HISI_ACC_VFIO_PCI=m
-CONFIG_VFIO_PCI_VGA=y
-CONFIG_VFIO_PCI_IGD=y
-CONFIG_VFIO_MDEV=m
-CONFIG_IRQ_BYPASS_MANAGER=m
-CONFIG_VIRT_DRIVERS=y
-CONFIG_VMGENID=m
-CONFIG_VBOXGUEST=m
-CONFIG_NITRO_ENCLAVES=m
-CONFIG_EFI_SECRET=m
-CONFIG_SEV_GUEST=m
-CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON=y
-CONFIG_VIRTIO=m
-CONFIG_ARCH_HAS_RESTRICTED_VIRTIO_MEMORY_ACCESS=y
-CONFIG_VIRTIO_PCI_LIB=m
-CONFIG_VIRTIO_PCI_LIB_LEGACY=m
-CONFIG_VIRTIO_MENU=y
-CONFIG_VIRTIO_PCI=m
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_VDPA=m
-CONFIG_VIRTIO_PMEM=m
-CONFIG_VIRTIO_BALLOON=m
-CONFIG_VIRTIO_MEM=m
-CONFIG_VIRTIO_INPUT=m
-CONFIG_VIRTIO_MMIO=m
-CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
-CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
-CONFIG_VDPA=m
-CONFIG_VDPA_USER=m
-CONFIG_IFCVF=m
-CONFIG_MLX5_VDPA=y
-CONFIG_MLX5_VDPA_NET=m
-CONFIG_VP_VDPA=m
-CONFIG_ALIBABA_ENI_VDPA=m
-CONFIG_VHOST_IOTLB=m
-CONFIG_VHOST_RING=m
-CONFIG_VHOST=m
-CONFIG_VHOST_MENU=y
-CONFIG_VHOST_NET=m
-CONFIG_VHOST_SCSI=m
-CONFIG_VHOST_VSOCK=m
-CONFIG_VHOST_VDPA=m
-# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
-
-#
-# Microsoft Hyper-V guest support
-#
-CONFIG_HYPERV=m
-CONFIG_HYPERV_TIMER=y
-CONFIG_HYPERV_UTILS=m
-CONFIG_HYPERV_BALLOON=m
-# end of Microsoft Hyper-V guest support
-
-# CONFIG_GREYBUS is not set
-CONFIG_COMEDI=m
-# CONFIG_COMEDI_DEBUG is not set
-CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
-CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
-CONFIG_COMEDI_MISC_DRIVERS=y
-CONFIG_COMEDI_BOND=m
-CONFIG_COMEDI_TEST=m
-CONFIG_COMEDI_PARPORT=m
-CONFIG_COMEDI_ISA_DRIVERS=y
-CONFIG_COMEDI_PCL711=m
-CONFIG_COMEDI_PCL724=m
-CONFIG_COMEDI_PCL726=m
-CONFIG_COMEDI_PCL730=m
-CONFIG_COMEDI_PCL812=m
-CONFIG_COMEDI_PCL816=m
-CONFIG_COMEDI_PCL818=m
-CONFIG_COMEDI_PCM3724=m
-CONFIG_COMEDI_AMPLC_DIO200_ISA=m
-CONFIG_COMEDI_AMPLC_PC236_ISA=m
-CONFIG_COMEDI_AMPLC_PC263_ISA=m
-CONFIG_COMEDI_RTI800=m
-CONFIG_COMEDI_RTI802=m
-CONFIG_COMEDI_DAC02=m
-CONFIG_COMEDI_DAS16M1=m
-CONFIG_COMEDI_DAS08_ISA=m
-CONFIG_COMEDI_DAS16=m
-CONFIG_COMEDI_DAS800=m
-CONFIG_COMEDI_DAS1800=m
-CONFIG_COMEDI_DAS6402=m
-CONFIG_COMEDI_DT2801=m
-CONFIG_COMEDI_DT2811=m
-CONFIG_COMEDI_DT2814=m
-CONFIG_COMEDI_DT2815=m
-CONFIG_COMEDI_DT2817=m
-CONFIG_COMEDI_DT282X=m
-CONFIG_COMEDI_DMM32AT=m
-CONFIG_COMEDI_FL512=m
-CONFIG_COMEDI_AIO_AIO12_8=m
-CONFIG_COMEDI_AIO_IIRO_16=m
-CONFIG_COMEDI_II_PCI20KC=m
-CONFIG_COMEDI_C6XDIGIO=m
-CONFIG_COMEDI_MPC624=m
-CONFIG_COMEDI_ADQ12B=m
-CONFIG_COMEDI_NI_AT_A2150=m
-CONFIG_COMEDI_NI_AT_AO=m
-CONFIG_COMEDI_NI_ATMIO=m
-CONFIG_COMEDI_NI_ATMIO16D=m
-CONFIG_COMEDI_NI_LABPC_ISA=m
-CONFIG_COMEDI_PCMAD=m
-CONFIG_COMEDI_PCMDA12=m
-CONFIG_COMEDI_PCMMIO=m
-CONFIG_COMEDI_PCMUIO=m
-CONFIG_COMEDI_MULTIQ3=m
-CONFIG_COMEDI_S526=m
-CONFIG_COMEDI_PCI_DRIVERS=m
-CONFIG_COMEDI_8255_PCI=m
-CONFIG_COMEDI_ADDI_WATCHDOG=m
-CONFIG_COMEDI_ADDI_APCI_1032=m
-CONFIG_COMEDI_ADDI_APCI_1500=m
-CONFIG_COMEDI_ADDI_APCI_1516=m
-CONFIG_COMEDI_ADDI_APCI_1564=m
-CONFIG_COMEDI_ADDI_APCI_16XX=m
-CONFIG_COMEDI_ADDI_APCI_2032=m
-CONFIG_COMEDI_ADDI_APCI_2200=m
-CONFIG_COMEDI_ADDI_APCI_3120=m
-CONFIG_COMEDI_ADDI_APCI_3501=m
-CONFIG_COMEDI_ADDI_APCI_3XXX=m
-CONFIG_COMEDI_ADL_PCI6208=m
-CONFIG_COMEDI_ADL_PCI7X3X=m
-CONFIG_COMEDI_ADL_PCI8164=m
-CONFIG_COMEDI_ADL_PCI9111=m
-CONFIG_COMEDI_ADL_PCI9118=m
-CONFIG_COMEDI_ADV_PCI1710=m
-CONFIG_COMEDI_ADV_PCI1720=m
-CONFIG_COMEDI_ADV_PCI1723=m
-CONFIG_COMEDI_ADV_PCI1724=m
-CONFIG_COMEDI_ADV_PCI1760=m
-CONFIG_COMEDI_ADV_PCI_DIO=m
-CONFIG_COMEDI_AMPLC_DIO200_PCI=m
-CONFIG_COMEDI_AMPLC_PC236_PCI=m
-CONFIG_COMEDI_AMPLC_PC263_PCI=m
-CONFIG_COMEDI_AMPLC_PCI224=m
-CONFIG_COMEDI_AMPLC_PCI230=m
-CONFIG_COMEDI_CONTEC_PCI_DIO=m
-CONFIG_COMEDI_DAS08_PCI=m
-CONFIG_COMEDI_DT3000=m
-CONFIG_COMEDI_DYNA_PCI10XX=m
-CONFIG_COMEDI_GSC_HPDI=m
-CONFIG_COMEDI_MF6X4=m
-CONFIG_COMEDI_ICP_MULTI=m
-CONFIG_COMEDI_DAQBOARD2000=m
-CONFIG_COMEDI_JR3_PCI=m
-CONFIG_COMEDI_KE_COUNTER=m
-CONFIG_COMEDI_CB_PCIDAS64=m
-CONFIG_COMEDI_CB_PCIDAS=m
-CONFIG_COMEDI_CB_PCIDDA=m
-CONFIG_COMEDI_CB_PCIMDAS=m
-CONFIG_COMEDI_CB_PCIMDDA=m
-CONFIG_COMEDI_ME4000=m
-CONFIG_COMEDI_ME_DAQ=m
-CONFIG_COMEDI_NI_6527=m
-CONFIG_COMEDI_NI_65XX=m
-CONFIG_COMEDI_NI_660X=m
-CONFIG_COMEDI_NI_670X=m
-CONFIG_COMEDI_NI_LABPC_PCI=m
-CONFIG_COMEDI_NI_PCIDIO=m
-CONFIG_COMEDI_NI_PCIMIO=m
-CONFIG_COMEDI_RTD520=m
-CONFIG_COMEDI_S626=m
-CONFIG_COMEDI_MITE=m
-CONFIG_COMEDI_NI_TIOCMD=m
-CONFIG_COMEDI_PCMCIA_DRIVERS=m
-CONFIG_COMEDI_CB_DAS16_CS=m
-CONFIG_COMEDI_DAS08_CS=m
-CONFIG_COMEDI_NI_DAQ_700_CS=m
-CONFIG_COMEDI_NI_DAQ_DIO24_CS=m
-CONFIG_COMEDI_NI_LABPC_CS=m
-CONFIG_COMEDI_NI_MIO_CS=m
-CONFIG_COMEDI_QUATECH_DAQP_CS=m
-CONFIG_COMEDI_USB_DRIVERS=m
-CONFIG_COMEDI_DT9812=m
-CONFIG_COMEDI_NI_USB6501=m
-CONFIG_COMEDI_USBDUX=m
-CONFIG_COMEDI_USBDUXFAST=m
-CONFIG_COMEDI_USBDUXSIGMA=m
-CONFIG_COMEDI_VMK80XX=m
-CONFIG_COMEDI_8254=m
-CONFIG_COMEDI_8255=m
-CONFIG_COMEDI_8255_SA=m
-CONFIG_COMEDI_KCOMEDILIB=m
-CONFIG_COMEDI_AMPLC_DIO200=m
-CONFIG_COMEDI_AMPLC_PC236=m
-CONFIG_COMEDI_DAS08=m
-CONFIG_COMEDI_ISADMA=m
-CONFIG_COMEDI_NI_LABPC=m
-CONFIG_COMEDI_NI_LABPC_ISADMA=m
-CONFIG_COMEDI_NI_TIO=m
-CONFIG_COMEDI_NI_ROUTING=m
-CONFIG_COMEDI_TESTS=m
-CONFIG_COMEDI_TESTS_EXAMPLE=m
-CONFIG_COMEDI_TESTS_NI_ROUTES=m
-CONFIG_STAGING=y
-CONFIG_PRISM2_USB=m
-CONFIG_RTL8192U=m
-CONFIG_RTLLIB=m
-CONFIG_RTLLIB_CRYPTO_CCMP=m
-CONFIG_RTLLIB_CRYPTO_TKIP=m
-CONFIG_RTLLIB_CRYPTO_WEP=m
-CONFIG_RTL8192E=m
-CONFIG_RTL8723BS=m
-CONFIG_R8712U=m
-CONFIG_R8188EU=m
-CONFIG_RTS5208=m
-CONFIG_VT6655=m
-CONFIG_VT6656=m
-
-#
-# IIO staging drivers
-#
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16203=m
-CONFIG_ADIS16240=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD7816=m
-CONFIG_AD7280=m
-# end of Analog to digital converters
-
-#
-# Analog digital bi-direction converters
-#
-CONFIG_ADT7316=m
-CONFIG_ADT7316_SPI=m
-CONFIG_ADT7316_I2C=m
-# end of Analog digital bi-direction converters
-
-#
-# Capacitance to digital converters
-#
-CONFIG_AD7746=m
-# end of Capacitance to digital converters
-
-#
-# Direct Digital Synthesis
-#
-CONFIG_AD9832=m
-CONFIG_AD9834=m
-# end of Direct Digital Synthesis
-
-#
-# Network Analyzer, Impedance Converters
-#
-CONFIG_AD5933=m
-# end of Network Analyzer, Impedance Converters
-
-#
-# Active energy metering IC
-#
-CONFIG_ADE7854=m
-CONFIG_ADE7854_I2C=m
-CONFIG_ADE7854_SPI=m
-# end of Active energy metering IC
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S1210=m
-# end of Resolver to digital converters
-# end of IIO staging drivers
-
-# CONFIG_FB_SM750 is not set
-CONFIG_STAGING_MEDIA=y
-CONFIG_INTEL_ATOMISP=y
-CONFIG_VIDEO_ATOMISP=m
-CONFIG_VIDEO_ATOMISP_ISP2401=y
-CONFIG_VIDEO_ATOMISP_OV2722=m
-CONFIG_VIDEO_ATOMISP_GC2235=m
-CONFIG_VIDEO_ATOMISP_MSRLIST_HELPER=m
-CONFIG_VIDEO_ATOMISP_MT9M114=m
-CONFIG_VIDEO_ATOMISP_GC0310=m
-CONFIG_VIDEO_ATOMISP_OV2680=m
-CONFIG_VIDEO_ATOMISP_OV5693=m
-CONFIG_VIDEO_ATOMISP_LM3554=m
-CONFIG_VIDEO_ZORAN=m
-CONFIG_VIDEO_ZORAN_DC30=y
-CONFIG_VIDEO_ZORAN_ZR36060=y
-CONFIG_VIDEO_ZORAN_BUZ=y
-CONFIG_VIDEO_ZORAN_DC10=y
-CONFIG_VIDEO_ZORAN_LML33=y
-CONFIG_VIDEO_ZORAN_LML33R10=y
-CONFIG_VIDEO_ZORAN_AVS6EYES=y
-CONFIG_VIDEO_IPU3_IMGU=m
-CONFIG_DVB_AV7110_IR=y
-CONFIG_DVB_AV7110=m
-CONFIG_DVB_AV7110_OSD=y
-CONFIG_DVB_BUDGET_PATCH=m
-CONFIG_DVB_SP8870=m
-
-#
-# Android
-#
-CONFIG_ASHMEM=m
-# end of Android
-
-CONFIG_LTE_GDM724X=m
-CONFIG_FIREWIRE_SERIAL=m
-CONFIG_FWTTY_MAX_TOTAL_PORTS=64
-CONFIG_FWTTY_MAX_CARD_PORTS=32
-CONFIG_GS_FPGABOOT=m
-CONFIG_UNISYSSPAR=y
-# CONFIG_UNISYS_VISORNIC is not set
-# CONFIG_UNISYS_VISORINPUT is not set
-# CONFIG_UNISYS_VISORHBA is not set
-CONFIG_FB_TFT=m
-CONFIG_FB_TFT_AGM1264K_FL=m
-CONFIG_FB_TFT_BD663474=m
-CONFIG_FB_TFT_HX8340BN=m
-CONFIG_FB_TFT_HX8347D=m
-CONFIG_FB_TFT_HX8353D=m
-CONFIG_FB_TFT_HX8357D=m
-CONFIG_FB_TFT_ILI9163=m
-CONFIG_FB_TFT_ILI9320=m
-CONFIG_FB_TFT_ILI9325=m
-CONFIG_FB_TFT_ILI9340=m
-CONFIG_FB_TFT_ILI9341=m
-CONFIG_FB_TFT_ILI9481=m
-CONFIG_FB_TFT_ILI9486=m
-CONFIG_FB_TFT_PCD8544=m
-CONFIG_FB_TFT_RA8875=m
-CONFIG_FB_TFT_S6D02A1=m
-CONFIG_FB_TFT_S6D1121=m
-CONFIG_FB_TFT_SEPS525=m
-CONFIG_FB_TFT_SH1106=m
-CONFIG_FB_TFT_SSD1289=m
-CONFIG_FB_TFT_SSD1305=m
-CONFIG_FB_TFT_SSD1306=m
-CONFIG_FB_TFT_SSD1331=m
-CONFIG_FB_TFT_SSD1351=m
-CONFIG_FB_TFT_ST7735R=m
-CONFIG_FB_TFT_ST7789V=m
-CONFIG_FB_TFT_TINYLCD=m
-CONFIG_FB_TFT_TLS8204=m
-CONFIG_FB_TFT_UC1611=m
-CONFIG_FB_TFT_UC1701=m
-CONFIG_FB_TFT_UPD161704=m
-CONFIG_FB_TFT_WATTEROTT=m
-CONFIG_MOST_COMPONENTS=m
-CONFIG_MOST_NET=m
-CONFIG_MOST_VIDEO=m
-CONFIG_MOST_I2C=m
-CONFIG_KS7010=m
-CONFIG_PI433=m
-CONFIG_FIELDBUS_DEV=m
-CONFIG_QLGE=m
-CONFIG_WFX=m
-CONFIG_RTL8723CS=m
-CONFIG_X86_PLATFORM_DEVICES=y
-CONFIG_ACPI_WMI=m
-CONFIG_WMI_BMOF=m
-CONFIG_HUAWEI_WMI=m
-CONFIG_MXM_WMI=m
-CONFIG_PEAQ_WMI=m
-CONFIG_NVIDIA_WMI_EC_BACKLIGHT=m
-CONFIG_XIAOMI_WMI=m
-CONFIG_GIGABYTE_WMI=m
-CONFIG_YOGABOOK_WMI=m
-CONFIG_ACERHDF=m
-CONFIG_ACER_WIRELESS=m
-CONFIG_ACER_WMI=m
-CONFIG_AMD_PMF=m
-CONFIG_AMD_PMC=m
-CONFIG_AMD_HSMP=m
-CONFIG_ADV_SWBUTTON=m
-CONFIG_APPLE_GMUX=m
-CONFIG_ASUS_LAPTOP=m
-CONFIG_ASUS_WIRELESS=m
-CONFIG_ASUS_WMI=m
-CONFIG_ASUS_NB_WMI=m
-CONFIG_ASUS_TF103C_DOCK=m
-CONFIG_MERAKI_MX100=m
-# CONFIG_EEEPC_LAPTOP is not set
-# CONFIG_EEEPC_WMI is not set
-CONFIG_X86_PLATFORM_DRIVERS_DELL=y
-CONFIG_ALIENWARE_WMI=m
-CONFIG_DCDBAS=m
-CONFIG_DELL_LAPTOP=m
-CONFIG_DELL_RBU=m
-CONFIG_DELL_RBTN=m
-CONFIG_DELL_SMBIOS=m
-CONFIG_DELL_SMBIOS_WMI=y
-CONFIG_DELL_SMBIOS_SMM=y
-CONFIG_DELL_SMO8800=m
-CONFIG_DELL_WMI=m
-CONFIG_DELL_WMI_PRIVACY=y
-CONFIG_DELL_WMI_AIO=m
-CONFIG_DELL_WMI_DESCRIPTOR=m
-CONFIG_DELL_WMI_LED=m
-CONFIG_DELL_WMI_SYSMAN=m
-CONFIG_AMILO_RFKILL=m
-CONFIG_FUJITSU_LAPTOP=m
-CONFIG_FUJITSU_TABLET=m
-CONFIG_GPD_POCKET_FAN=m
-CONFIG_HP_ACCEL=m
-CONFIG_WIRELESS_HOTKEY=m
-CONFIG_HP_WMI=m
-CONFIG_IBM_RTL=m
-CONFIG_IDEAPAD_LAPTOP=m
-CONFIG_SENSORS_HDAPS=m
-CONFIG_THINKPAD_ACPI=m
-CONFIG_THINKPAD_ACPI_ALSA_SUPPORT=y
-# CONFIG_THINKPAD_ACPI_DEBUGFACILITIES is not set
-# CONFIG_THINKPAD_ACPI_DEBUG is not set
-# CONFIG_THINKPAD_ACPI_UNSAFE_LEDS is not set
-CONFIG_THINKPAD_ACPI_VIDEO=y
-CONFIG_THINKPAD_ACPI_HOTKEY_POLL=y
-CONFIG_THINKPAD_LMI=m
-CONFIG_INTEL_ATOMISP2_PDX86=y
-CONFIG_INTEL_ATOMISP2_LED=m
-CONFIG_INTEL_SAR_INT1092=m
-CONFIG_INTEL_SKL_INT3472=m
-# CONFIG_INTEL_PMC_CORE is not set
-CONFIG_INTEL_PMT_CLASS=m
-CONFIG_INTEL_PMT_TELEMETRY=m
-CONFIG_INTEL_PMT_CRASHLOG=m
-
-#
-# Intel Speed Select Technology interface support
-#
-# CONFIG_INTEL_SPEED_SELECT_INTERFACE is not set
-# end of Intel Speed Select Technology interface support
-
-CONFIG_INTEL_WMI=y
-# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
-CONFIG_INTEL_WMI_THUNDERBOLT=m
-CONFIG_INTEL_HID_EVENT=m
-# CONFIG_INTEL_VBTN is not set
-# CONFIG_INTEL_INT0002_VGPIO is not set
-CONFIG_INTEL_OAKTRAIL=m
-# CONFIG_INTEL_BXTWC_PMIC_TMU is not set
-CONFIG_INTEL_CHTWC_INT33FE=m
-# CONFIG_INTEL_CHTDC_TI_PWRBTN is not set
-# CONFIG_INTEL_PUNIT_IPC is not set
-# CONFIG_INTEL_RST is not set
-CONFIG_INTEL_SDSI=m
-CONFIG_INTEL_SMARTCONNECT=m
-CONFIG_INTEL_TURBO_MAX_3=y
-CONFIG_INTEL_VSEC=m
-# CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set
-CONFIG_MSI_LAPTOP=m
-CONFIG_MSI_WMI=m
-# CONFIG_PCENGINES_APU2 is not set
-CONFIG_BARCO_P50_GPIO=m
-CONFIG_SAMSUNG_LAPTOP=m
-# CONFIG_SAMSUNG_Q10 is not set
-CONFIG_ACPI_TOSHIBA=m
-CONFIG_TOSHIBA_BT_RFKILL=m
-CONFIG_TOSHIBA_HAPS=m
-CONFIG_TOSHIBA_WMI=m
-CONFIG_ACPI_CMPC=m
-CONFIG_COMPAL_LAPTOP=m
-CONFIG_LG_LAPTOP=m
-CONFIG_PANASONIC_LAPTOP=m
-CONFIG_SONY_LAPTOP=m
-CONFIG_SONYPI_COMPAT=y
-CONFIG_SYSTEM76_ACPI=m
-CONFIG_TOPSTAR_LAPTOP=m
-CONFIG_SERIAL_MULTI_INSTANTIATE=m
-CONFIG_I2C_MULTI_INSTANTIATE=m
-CONFIG_MLX_PLATFORM=m
-CONFIG_X86_ANDROID_TABLETS=m
-CONFIG_FW_ATTR_CLASS=m
-# CONFIG_INTEL_IPS is not set
-CONFIG_INTEL_SCU_IPC=y
-CONFIG_SIEMENS_SIMATIC_IPC=m
-# CONFIG_INTEL_SCU_PCI is not set
-# CONFIG_INTEL_SCU_PLATFORM is not set
-CONFIG_PMC_ATOM=y
-CONFIG_CHROME_PLATFORMS=y
-CONFIG_CHROMEOS_LAPTOP=m
-CONFIG_CHROMEOS_PSTORE=m
-CONFIG_CHROMEOS_TBMC=m
-CONFIG_CROS_EC=m
-CONFIG_CROS_EC_I2C=m
-CONFIG_CROS_EC_SPI=m
-CONFIG_CROS_EC_LPC=m
-CONFIG_CROS_EC_PROTO=y
-CONFIG_CROS_KBD_LED_BACKLIGHT=m
-CONFIG_CROS_EC_CHARDEV=m
-CONFIG_CROS_EC_LIGHTBAR=m
-CONFIG_CROS_EC_DEBUGFS=m
-CONFIG_CROS_EC_SENSORHUB=m
-CONFIG_CROS_EC_SYSFS=m
-CONFIG_CROS_EC_TYPEC=m
-CONFIG_CROS_USBPD_LOGGER=m
-CONFIG_CROS_USBPD_NOTIFY=m
-CONFIG_CHROMEOS_PRIVACY_SCREEN=m
-CONFIG_CROS_TYPEC_SWITCH=m
-CONFIG_WILCO_EC=m
-CONFIG_WILCO_EC_DEBUGFS=m
-CONFIG_WILCO_EC_EVENTS=m
-CONFIG_WILCO_EC_TELEMETRY=m
-CONFIG_MELLANOX_PLATFORM=y
-CONFIG_MLXREG_HOTPLUG=m
-CONFIG_MLXREG_IO=m
-CONFIG_MLXREG_LC=m
-CONFIG_SURFACE_PLATFORMS=y
-CONFIG_SURFACE3_WMI=m
-CONFIG_SURFACE_3_BUTTON=m
-CONFIG_SURFACE_3_POWER_OPREGION=m
-CONFIG_SURFACE_ACPI_NOTIFY=m
-CONFIG_SURFACE_AGGREGATOR_CDEV=m
-CONFIG_SURFACE_AGGREGATOR_HUB=m
-CONFIG_SURFACE_AGGREGATOR_REGISTRY=m
-CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m
-CONFIG_SURFACE_DTX=m
-CONFIG_SURFACE_GPE=m
-CONFIG_SURFACE_HOTPLUG=m
-CONFIG_SURFACE_PLATFORM_PROFILE=m
-CONFIG_SURFACE_PRO3_BUTTON=m
-CONFIG_SURFACE_AGGREGATOR=m
-CONFIG_SURFACE_AGGREGATOR_BUS=y
-# CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION is not set
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_WM831X=m
-CONFIG_LMK04832=m
-CONFIG_COMMON_CLK_APPLE_NCO=m
-CONFIG_COMMON_CLK_MAX9485=m
-CONFIG_COMMON_CLK_SI5341=m
-CONFIG_COMMON_CLK_SI5351=m
-CONFIG_COMMON_CLK_SI544=m
-CONFIG_COMMON_CLK_CDCE706=m
-CONFIG_COMMON_CLK_TPS68470=m
-CONFIG_COMMON_CLK_CS2000_CP=m
-CONFIG_COMMON_CLK_PWM=m
-CONFIG_COMMON_CLK_RS9_PCIE=m
-# CONFIG_XILINX_VCU is not set
-CONFIG_HWSPINLOCK=y
-
-#
-# Clock Source drivers
-#
-CONFIG_CLKEVT_I8253=y
-CONFIG_I8253_LOCK=y
-CONFIG_CLKBLD_I8253=y
-# end of Clock Source drivers
-
-CONFIG_MAILBOX=y
-CONFIG_PCC=y
-CONFIG_ALTERA_MBOX=m
-CONFIG_IOMMU_IOVA=y
-CONFIG_IOMMU_API=y
-CONFIG_IOMMU_SUPPORT=y
-
-#
-# Generic IOMMU Pagetable Support
-#
-CONFIG_IOMMU_IO_PGTABLE=y
-# end of Generic IOMMU Pagetable Support
-
-# CONFIG_IOMMU_DEBUGFS is not set
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_IOMMU_DMA=y
-CONFIG_AMD_IOMMU=y
-CONFIG_AMD_IOMMU_V2=m
-CONFIG_DMAR_TABLE=y
-# CONFIG_INTEL_IOMMU is not set
-CONFIG_IRQ_REMAP=y
-CONFIG_HYPERV_IOMMU=y
-CONFIG_VIRTIO_IOMMU=m
-
-#
-# Remoteproc drivers
-#
-# CONFIG_REMOTEPROC is not set
-# end of Remoteproc drivers
-
-#
-# Rpmsg drivers
-#
-CONFIG_RPMSG=m
-CONFIG_RPMSG_CHAR=m
-CONFIG_RPMSG_CTRL=m
-CONFIG_RPMSG_NS=m
-CONFIG_RPMSG_QCOM_GLINK=m
-CONFIG_RPMSG_QCOM_GLINK_RPM=m
-CONFIG_RPMSG_VIRTIO=m
-# end of Rpmsg drivers
-
-CONFIG_SOUNDWIRE=y
-
-#
-# SoundWire Devices
-#
-CONFIG_SOUNDWIRE_CADENCE=m
-CONFIG_SOUNDWIRE_INTEL=m
-CONFIG_SOUNDWIRE_QCOM=m
-CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=m
-
-#
-# SOC (System On Chip) specific Drivers
-#
-
-#
-# Amlogic SoC drivers
-#
-# end of Amlogic SoC drivers
-
-#
-# Broadcom SoC drivers
-#
-# end of Broadcom SoC drivers
-
-#
-# NXP/Freescale QorIQ SoC drivers
-#
-# end of NXP/Freescale QorIQ SoC drivers
-
-#
-# i.MX SoC drivers
-#
-# end of i.MX SoC drivers
-
-#
-# Enable LiteX SoC Builder specific drivers
-#
-# end of Enable LiteX SoC Builder specific drivers
-
-#
-# Qualcomm SoC drivers
-#
-CONFIG_QCOM_QMI_HELPERS=m
-# end of Qualcomm SoC drivers
-
-# CONFIG_SOC_TI is not set
-
-#
-# Xilinx SoC drivers
-#
-# end of Xilinx SoC drivers
-# end of SOC (System On Chip) specific Drivers
-
-CONFIG_PM_DEVFREQ=y
-
-#
-# DEVFREQ Governors
-#
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_PERFORMANCE=y
-CONFIG_DEVFREQ_GOV_POWERSAVE=y
-CONFIG_DEVFREQ_GOV_USERSPACE=y
-CONFIG_DEVFREQ_GOV_PASSIVE=m
-
-#
-# DEVFREQ Drivers
-#
-CONFIG_PM_DEVFREQ_EVENT=y
-CONFIG_EXTCON=y
-
-#
-# Extcon Device Drivers
-#
-CONFIG_EXTCON_ADC_JACK=m
-CONFIG_EXTCON_AXP288=m
-CONFIG_EXTCON_FSA9480=m
-CONFIG_EXTCON_GPIO=m
-CONFIG_EXTCON_INTEL_INT3496=m
-CONFIG_EXTCON_MAX14577=m
-CONFIG_EXTCON_MAX3355=m
-CONFIG_EXTCON_MAX77693=m
-CONFIG_EXTCON_PTN5150=m
-CONFIG_EXTCON_RT8973A=m
-CONFIG_EXTCON_SM5502=m
-CONFIG_EXTCON_USB_GPIO=m
-CONFIG_EXTCON_USBC_CROS_EC=m
-CONFIG_EXTCON_USBC_TUSB320=m
-CONFIG_MEMORY=y
-CONFIG_FPGA_DFL_EMIF=m
-CONFIG_IIO=m
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_BUFFER_CB=m
-CONFIG_IIO_BUFFER_DMA=m
-CONFIG_IIO_BUFFER_DMAENGINE=m
-CONFIG_IIO_BUFFER_HW_CONSUMER=m
-CONFIG_IIO_KFIFO_BUF=m
-CONFIG_IIO_TRIGGERED_BUFFER=m
-CONFIG_IIO_CONFIGFS=m
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
-CONFIG_IIO_SW_DEVICE=m
-CONFIG_IIO_SW_TRIGGER=m
-CONFIG_IIO_TRIGGERED_EVENT=m
-
-#
-# Accelerometers
-#
-CONFIG_ADIS16201=m
-CONFIG_ADIS16209=m
-CONFIG_ADXL313=m
-CONFIG_ADXL313_I2C=m
-CONFIG_ADXL313_SPI=m
-CONFIG_ADXL355=m
-CONFIG_ADXL355_I2C=m
-CONFIG_ADXL355_SPI=m
-CONFIG_ADXL367_SPI=m
-CONFIG_ADXL367_I2C=m
-CONFIG_ADXL372=m
-CONFIG_ADXL372_SPI=m
-CONFIG_ADXL372_I2C=m
-CONFIG_BMA220=m
-CONFIG_BMA400=m
-CONFIG_BMA400_I2C=m
-CONFIG_BMA400_SPI=m
-CONFIG_BMC150_ACCEL=m
-CONFIG_BMC150_ACCEL_I2C=m
-CONFIG_BMC150_ACCEL_SPI=m
-CONFIG_BMI088_ACCEL=m
-CONFIG_BMI088_ACCEL_SPI=m
-CONFIG_DA280=m
-CONFIG_DA311=m
-CONFIG_DMARD09=m
-CONFIG_DMARD10=m
-CONFIG_FXLS8962AF=m
-CONFIG_FXLS8962AF_I2C=m
-CONFIG_FXLS8962AF_SPI=m
-CONFIG_HID_SENSOR_ACCEL_3D=m
-CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
-CONFIG_IIO_ST_ACCEL_3AXIS=m
-CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
-CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
-CONFIG_KXSD9=m
-CONFIG_KXSD9_SPI=m
-CONFIG_KXSD9_I2C=m
-CONFIG_KXCJK1013=m
-CONFIG_MC3230=m
-CONFIG_MMA7455=m
-CONFIG_MMA7455_I2C=m
-CONFIG_MMA7455_SPI=m
-CONFIG_MMA7660=m
-CONFIG_MMA8452=m
-CONFIG_MMA9551_CORE=m
-CONFIG_MMA9551=m
-CONFIG_MMA9553=m
-CONFIG_MSA311=m
-CONFIG_MXC4005=m
-CONFIG_MXC6255=m
-CONFIG_SCA3000=m
-CONFIG_SCA3300=m
-CONFIG_STK8312=m
-CONFIG_STK8BA50=m
-# end of Accelerometers
-
-#
-# Analog to digital converters
-#
-CONFIG_AD_SIGMA_DELTA=m
-CONFIG_AD7091R5=m
-CONFIG_AD7124=m
-CONFIG_AD7192=m
-CONFIG_AD7266=m
-CONFIG_AD7291=m
-CONFIG_AD7292=m
-CONFIG_AD7298=m
-CONFIG_AD7476=m
-CONFIG_AD7606=m
-CONFIG_AD7606_IFACE_PARALLEL=m
-CONFIG_AD7606_IFACE_SPI=m
-CONFIG_AD7766=m
-CONFIG_AD7768_1=m
-CONFIG_AD7780=m
-CONFIG_AD7791=m
-CONFIG_AD7793=m
-CONFIG_AD7887=m
-CONFIG_AD7923=m
-CONFIG_AD7949=m
-CONFIG_AD799X=m
-CONFIG_AXP20X_ADC=m
-CONFIG_AXP288_ADC=m
-CONFIG_CC10001_ADC=m
-CONFIG_DA9150_GPADC=m
-CONFIG_DLN2_ADC=m
-CONFIG_ENVELOPE_DETECTOR=m
-CONFIG_HI8435=m
-CONFIG_HX711=m
-CONFIG_INA2XX_ADC=m
-CONFIG_LTC2471=m
-CONFIG_LTC2485=m
-CONFIG_LTC2496=m
-CONFIG_LTC2497=m
-CONFIG_MAX1027=m
-CONFIG_MAX11100=m
-CONFIG_MAX1118=m
-CONFIG_MAX11205=m
-CONFIG_MAX1241=m
-CONFIG_MAX1363=m
-CONFIG_MAX9611=m
-CONFIG_MCP320X=m
-CONFIG_MCP3422=m
-CONFIG_MCP3911=m
-CONFIG_MEDIATEK_MT6360_ADC=m
-CONFIG_MEN_Z188_ADC=m
-CONFIG_MP2629_ADC=m
-CONFIG_NAU7802=m
-CONFIG_QCOM_VADC_COMMON=m
-CONFIG_QCOM_SPMI_IADC=m
-CONFIG_QCOM_SPMI_VADC=m
-CONFIG_QCOM_SPMI_ADC5=m
-CONFIG_RICHTEK_RTQ6056=m
-CONFIG_SD_ADC_MODULATOR=m
-CONFIG_TI_ADC081C=m
-CONFIG_TI_ADC0832=m
-CONFIG_TI_ADC084S021=m
-CONFIG_TI_ADC12138=m
-CONFIG_TI_ADC108S102=m
-CONFIG_TI_ADC128S052=m
-CONFIG_TI_ADC161S626=m
-CONFIG_TI_ADS1015=m
-CONFIG_TI_ADS7950=m
-CONFIG_TI_ADS8344=m
-CONFIG_TI_ADS8688=m
-CONFIG_TI_ADS124S08=m
-CONFIG_TI_ADS131E08=m
-CONFIG_TI_AM335X_ADC=m
-CONFIG_TI_TLC4541=m
-CONFIG_TI_TSC2046=m
-CONFIG_VF610_ADC=m
-CONFIG_VIPERBOARD_ADC=m
-CONFIG_XILINX_XADC=m
-CONFIG_XILINX_AMS=m
-# end of Analog to digital converters
-
-#
-# Analog Front Ends
-#
-# end of Analog Front Ends
-
-#
-# Amplifiers
-#
-CONFIG_AD8366=m
-CONFIG_ADA4250=m
-CONFIG_HMC425=m
-# end of Amplifiers
-
-#
-# Capacitance to digital converters
-#
-CONFIG_AD7150=m
-# end of Capacitance to digital converters
-
-#
-# Chemical Sensors
-#
-CONFIG_ATLAS_PH_SENSOR=m
-CONFIG_ATLAS_EZO_SENSOR=m
-CONFIG_BME680=m
-CONFIG_BME680_I2C=m
-CONFIG_BME680_SPI=m
-CONFIG_CCS811=m
-CONFIG_IAQCORE=m
-CONFIG_PMS7003=m
-CONFIG_SCD30_CORE=m
-CONFIG_SCD30_I2C=m
-CONFIG_SCD30_SERIAL=m
-CONFIG_SCD4X=m
-CONFIG_SENSIRION_SGP30=m
-CONFIG_SENSIRION_SGP40=m
-CONFIG_SPS30=m
-CONFIG_SPS30_I2C=m
-CONFIG_SPS30_SERIAL=m
-CONFIG_SENSEAIR_SUNRISE_CO2=m
-CONFIG_VZ89X=m
-# end of Chemical Sensors
-
-CONFIG_IIO_CROS_EC_SENSORS_CORE=m
-CONFIG_IIO_CROS_EC_SENSORS=m
-CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m
-
-#
-# Hid Sensor IIO Common
-#
-CONFIG_HID_SENSOR_IIO_COMMON=m
-CONFIG_HID_SENSOR_IIO_TRIGGER=m
-# end of Hid Sensor IIO Common
-
-CONFIG_IIO_MS_SENSORS_I2C=m
-
-#
-# IIO SCMI Sensors
-#
-# end of IIO SCMI Sensors
-
-#
-# SSP Sensor Common
-#
-CONFIG_IIO_SSP_SENSORS_COMMONS=m
-CONFIG_IIO_SSP_SENSORHUB=m
-# end of SSP Sensor Common
-
-CONFIG_IIO_ST_SENSORS_I2C=m
-CONFIG_IIO_ST_SENSORS_SPI=m
-CONFIG_IIO_ST_SENSORS_CORE=m
-
-#
-# Digital to analog converters
-#
-CONFIG_AD5064=m
-CONFIG_AD5360=m
-CONFIG_AD5380=m
-CONFIG_AD5421=m
-CONFIG_AD5446=m
-CONFIG_AD5449=m
-CONFIG_AD5592R_BASE=m
-CONFIG_AD5592R=m
-CONFIG_AD5593R=m
-CONFIG_AD5504=m
-CONFIG_AD5624R_SPI=m
-CONFIG_LTC2688=m
-CONFIG_AD5686=m
-CONFIG_AD5686_SPI=m
-CONFIG_AD5696_I2C=m
-CONFIG_AD5755=m
-CONFIG_AD5758=m
-CONFIG_AD5761=m
-CONFIG_AD5764=m
-CONFIG_AD5766=m
-CONFIG_AD5770R=m
-CONFIG_AD5791=m
-CONFIG_AD7303=m
-CONFIG_AD8801=m
-CONFIG_DS4424=m
-CONFIG_LTC1660=m
-CONFIG_LTC2632=m
-CONFIG_M62332=m
-CONFIG_MAX517=m
-CONFIG_MAX5821=m
-CONFIG_MCP4725=m
-CONFIG_MCP4922=m
-CONFIG_TI_DAC082S085=m
-CONFIG_TI_DAC5571=m
-CONFIG_TI_DAC7311=m
-CONFIG_TI_DAC7612=m
-# end of Digital to analog converters
-
-#
-# IIO dummy driver
-#
-# CONFIG_IIO_SIMPLE_DUMMY is not set
-# end of IIO dummy driver
-
-#
-# Frequency Synthesizers DDS/PLL
-#
-
-#
-# Clock Generator/Distribution
-#
-CONFIG_AD9523=m
-# end of Clock Generator/Distribution
-
-#
-# Phase-Locked Loop (PLL) frequency synthesizers
-#
-CONFIG_ADF4350=m
-CONFIG_ADF4371=m
-CONFIG_ADRF6780=m
-# end of Phase-Locked Loop (PLL) frequency synthesizers
-# end of Frequency Synthesizers DDS/PLL
-
-#
-# Digital gyroscope sensors
-#
-CONFIG_ADIS16080=m
-CONFIG_ADIS16130=m
-CONFIG_ADIS16136=m
-CONFIG_ADIS16260=m
-CONFIG_ADXRS290=m
-CONFIG_ADXRS450=m
-CONFIG_BMG160=m
-CONFIG_BMG160_I2C=m
-CONFIG_BMG160_SPI=m
-CONFIG_FXAS21002C=m
-CONFIG_FXAS21002C_I2C=m
-CONFIG_FXAS21002C_SPI=m
-CONFIG_HID_SENSOR_GYRO_3D=m
-CONFIG_MPU3050=m
-CONFIG_MPU3050_I2C=m
-CONFIG_IIO_ST_GYRO_3AXIS=m
-CONFIG_IIO_ST_GYRO_I2C_3AXIS=m
-CONFIG_IIO_ST_GYRO_SPI_3AXIS=m
-CONFIG_ITG3200=m
-# end of Digital gyroscope sensors
-
-#
-# Health Sensors
-#
-
-#
-# Heart Rate Monitors
-#
-CONFIG_AFE4403=m
-CONFIG_AFE4404=m
-CONFIG_MAX30100=m
-CONFIG_MAX30102=m
-# end of Heart Rate Monitors
-# end of Health Sensors
-
-#
-# Humidity sensors
-#
-CONFIG_AM2315=m
-CONFIG_DHT11=m
-CONFIG_HDC100X=m
-CONFIG_HDC2010=m
-CONFIG_HID_SENSOR_HUMIDITY=m
-CONFIG_HTS221=m
-CONFIG_HTS221_I2C=m
-CONFIG_HTS221_SPI=m
-CONFIG_HTU21=m
-CONFIG_SI7005=m
-CONFIG_SI7020=m
-# end of Humidity sensors
-
-#
-# Inertial measurement units
-#
-CONFIG_ADIS16400=m
-CONFIG_ADIS16460=m
-CONFIG_ADIS16475=m
-CONFIG_ADIS16480=m
-CONFIG_BMI160=m
-CONFIG_BMI160_I2C=m
-CONFIG_BMI160_SPI=m
-CONFIG_BOSCH_BNO055_SERIAL=m
-CONFIG_BOSCH_BNO055_I2C=m
-CONFIG_FXOS8700=m
-CONFIG_FXOS8700_I2C=m
-CONFIG_FXOS8700_SPI=m
-CONFIG_KMX61=m
-CONFIG_INV_ICM42600=m
-CONFIG_INV_ICM42600_I2C=m
-CONFIG_INV_ICM42600_SPI=m
-CONFIG_INV_MPU6050_IIO=m
-CONFIG_INV_MPU6050_I2C=m
-CONFIG_INV_MPU6050_SPI=m
-CONFIG_IIO_ST_LSM6DSX=m
-CONFIG_IIO_ST_LSM6DSX_I2C=m
-CONFIG_IIO_ST_LSM6DSX_SPI=m
-CONFIG_IIO_ST_LSM6DSX_I3C=m
-CONFIG_IIO_ST_LSM9DS0=m
-CONFIG_IIO_ST_LSM9DS0_I2C=m
-CONFIG_IIO_ST_LSM9DS0_SPI=m
-# end of Inertial measurement units
-
-CONFIG_IIO_ADIS_LIB=m
-CONFIG_IIO_ADIS_LIB_BUFFER=y
-
-#
-# Light sensors
-#
-# CONFIG_ACPI_ALS is not set
-CONFIG_ADJD_S311=m
-CONFIG_ADUX1020=m
-CONFIG_AL3010=m
-CONFIG_AL3320A=m
-CONFIG_APDS9300=m
-CONFIG_APDS9960=m
-CONFIG_AS73211=m
-CONFIG_BH1750=m
-CONFIG_BH1780=m
-CONFIG_CM32181=m
-CONFIG_CM3232=m
-CONFIG_CM3323=m
-CONFIG_CM36651=m
-CONFIG_IIO_CROS_EC_LIGHT_PROX=m
-CONFIG_GP2AP002=m
-CONFIG_GP2AP020A00F=m
-CONFIG_IQS621_ALS=m
-CONFIG_SENSORS_ISL29018=m
-CONFIG_SENSORS_ISL29028=m
-CONFIG_ISL29125=m
-CONFIG_HID_SENSOR_ALS=m
-CONFIG_HID_SENSOR_PROX=m
-CONFIG_JSA1212=m
-CONFIG_RPR0521=m
-CONFIG_SENSORS_LM3533=m
-CONFIG_LTR501=m
-CONFIG_LTRF216A=m
-CONFIG_LV0104CS=m
-CONFIG_MAX44000=m
-CONFIG_MAX44009=m
-CONFIG_NOA1305=m
-CONFIG_OPT3001=m
-CONFIG_PA12203001=m
-CONFIG_SI1133=m
-CONFIG_SI1145=m
-CONFIG_STK3310=m
-CONFIG_ST_UVIS25=m
-CONFIG_ST_UVIS25_I2C=m
-CONFIG_ST_UVIS25_SPI=m
-CONFIG_TCS3414=m
-CONFIG_TCS3472=m
-CONFIG_SENSORS_TSL2563=m
-CONFIG_TSL2583=m
-CONFIG_TSL2591=m
-CONFIG_TSL2772=m
-CONFIG_TSL4531=m
-CONFIG_US5182D=m
-CONFIG_VCNL4000=m
-CONFIG_VCNL4035=m
-CONFIG_VEML6030=m
-CONFIG_VEML6070=m
-CONFIG_VL6180=m
-CONFIG_ZOPT2201=m
-# end of Light sensors
-
-#
-# Magnetometer sensors
-#
-CONFIG_AK8975=m
-CONFIG_AK09911=m
-CONFIG_BMC150_MAGN=m
-CONFIG_BMC150_MAGN_I2C=m
-CONFIG_BMC150_MAGN_SPI=m
-CONFIG_MAG3110=m
-CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
-CONFIG_MMC35240=m
-CONFIG_IIO_ST_MAGN_3AXIS=m
-CONFIG_IIO_ST_MAGN_I2C_3AXIS=m
-CONFIG_IIO_ST_MAGN_SPI_3AXIS=m
-CONFIG_SENSORS_HMC5843=m
-CONFIG_SENSORS_HMC5843_I2C=m
-CONFIG_SENSORS_HMC5843_SPI=m
-CONFIG_SENSORS_RM3100=m
-CONFIG_SENSORS_RM3100_I2C=m
-CONFIG_SENSORS_RM3100_SPI=m
-CONFIG_YAMAHA_YAS530=m
-# end of Magnetometer sensors
-
-#
-# Multiplexers
-#
-# end of Multiplexers
-
-#
-# Inclinometer sensors
-#
-CONFIG_HID_SENSOR_INCLINOMETER_3D=m
-CONFIG_HID_SENSOR_DEVICE_ROTATION=m
-# end of Inclinometer sensors
-
-#
-# Triggers - standalone
-#
-CONFIG_IIO_HRTIMER_TRIGGER=m
-CONFIG_IIO_INTERRUPT_TRIGGER=m
-CONFIG_IIO_TIGHTLOOP_TRIGGER=m
-CONFIG_IIO_SYSFS_TRIGGER=m
-# end of Triggers - standalone
-
-#
-# Linear and angular position sensors
-#
-CONFIG_IQS624_POS=m
-CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
-# end of Linear and angular position sensors
-
-#
-# Digital potentiometers
-#
-CONFIG_AD5110=m
-CONFIG_AD5272=m
-CONFIG_DS1803=m
-CONFIG_MAX5432=m
-CONFIG_MAX5481=m
-CONFIG_MAX5487=m
-CONFIG_MCP4018=m
-CONFIG_MCP4131=m
-CONFIG_MCP4531=m
-CONFIG_MCP41010=m
-CONFIG_TPL0102=m
-# end of Digital potentiometers
-
-#
-# Digital potentiostats
-#
-CONFIG_LMP91000=m
-# end of Digital potentiostats
-
-#
-# Pressure sensors
-#
-CONFIG_ABP060MG=m
-CONFIG_BMP280=m
-CONFIG_BMP280_I2C=m
-CONFIG_BMP280_SPI=m
-CONFIG_IIO_CROS_EC_BARO=m
-CONFIG_DLHL60D=m
-CONFIG_DPS310=m
-CONFIG_HID_SENSOR_PRESS=m
-CONFIG_HP03=m
-CONFIG_ICP10100=m
-CONFIG_MPL115=m
-CONFIG_MPL115_I2C=m
-CONFIG_MPL115_SPI=m
-CONFIG_MPL3115=m
-CONFIG_MS5611=m
-CONFIG_MS5611_I2C=m
-CONFIG_MS5611_SPI=m
-CONFIG_MS5637=m
-CONFIG_IIO_ST_PRESS=m
-CONFIG_IIO_ST_PRESS_I2C=m
-CONFIG_IIO_ST_PRESS_SPI=m
-CONFIG_T5403=m
-CONFIG_HP206C=m
-CONFIG_ZPA2326=m
-CONFIG_ZPA2326_I2C=m
-CONFIG_ZPA2326_SPI=m
-# end of Pressure sensors
-
-#
-# Lightning sensors
-#
-CONFIG_AS3935=m
-# end of Lightning sensors
-
-#
-# Proximity and distance sensors
-#
-CONFIG_CROS_EC_MKBP_PROXIMITY=m
-CONFIG_ISL29501=m
-CONFIG_LIDAR_LITE_V2=m
-CONFIG_MB1232=m
-CONFIG_PING=m
-CONFIG_RFD77402=m
-CONFIG_SRF04=m
-CONFIG_SX9310=m
-CONFIG_SX9324=m
-CONFIG_SX9360=m
-CONFIG_SX9500=m
-CONFIG_SRF08=m
-CONFIG_VCNL3020=m
-CONFIG_VL53L0X_I2C=m
-# end of Proximity and distance sensors
-
-#
-# Resolver to digital converters
-#
-CONFIG_AD2S90=m
-CONFIG_AD2S1200=m
-# end of Resolver to digital converters
-
-#
-# Temperature sensors
-#
-CONFIG_IQS620AT_TEMP=m
-CONFIG_LTC2983=m
-CONFIG_MAXIM_THERMOCOUPLE=m
-CONFIG_HID_SENSOR_TEMP=m
-CONFIG_MLX90614=m
-CONFIG_MLX90632=m
-CONFIG_TMP006=m
-CONFIG_TMP007=m
-CONFIG_TMP117=m
-CONFIG_TSYS01=m
-CONFIG_TSYS02D=m
-CONFIG_MAX31856=m
-CONFIG_MAX31865=m
-# end of Temperature sensors
-
-CONFIG_NTB=m
-CONFIG_NTB_MSI=y
-CONFIG_NTB_AMD=m
-CONFIG_NTB_IDT=m
-CONFIG_NTB_INTEL=m
-CONFIG_NTB_EPF=m
-CONFIG_NTB_SWITCHTEC=m
-CONFIG_NTB_PINGPONG=m
-CONFIG_NTB_TOOL=m
-CONFIG_NTB_PERF=m
-CONFIG_NTB_MSI_TEST=m
-CONFIG_NTB_TRANSPORT=m
-CONFIG_VME_BUS=y
-
-#
-# VME Bridge Drivers
-#
-CONFIG_VME_CA91CX42=m
-CONFIG_VME_TSI148=m
-CONFIG_VME_FAKE=m
-
-#
-# VME Board Drivers
-#
-CONFIG_VMIVME_7805=m
-
-#
-# VME Device Drivers
-#
-CONFIG_VME_USER=m
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_PWM_DEBUG is not set
-CONFIG_PWM_CLK=m
-CONFIG_PWM_CROS_EC=m
-CONFIG_PWM_DWC=m
-CONFIG_PWM_IQS620A=m
-CONFIG_PWM_LP3943=m
-CONFIG_PWM_LPSS=m
-CONFIG_PWM_LPSS_PCI=m
-CONFIG_PWM_LPSS_PLATFORM=m
-CONFIG_PWM_PCA9685=m
-
-#
-# IRQ chip support
-#
-CONFIG_MADERA_IRQ=m
-# end of IRQ chip support
-
-# CONFIG_IPACK_BUS is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_SIMPLE=y
-CONFIG_RESET_TI_SYSCON=m
-CONFIG_RESET_TI_TPS380X=m
-
-#
-# PHY Subsystem
-#
-CONFIG_GENERIC_PHY=y
-CONFIG_USB_LGM_PHY=m
-CONFIG_PHY_CAN_TRANSCEIVER=m
-
-#
-# PHY drivers for Broadcom platforms
-#
-CONFIG_BCM_KONA_USB2_PHY=m
-# end of PHY drivers for Broadcom platforms
-
-CONFIG_PHY_PXA_28NM_HSIC=m
-CONFIG_PHY_PXA_28NM_USB2=m
-CONFIG_PHY_CPCAP_USB=m
-CONFIG_PHY_QCOM_USB_HS=m
-CONFIG_PHY_QCOM_USB_HSIC=m
-CONFIG_PHY_SAMSUNG_USB2=m
-CONFIG_PHY_TUSB1210=m
-CONFIG_PHY_INTEL_LGM_EMMC=m
-# end of PHY Subsystem
-
-CONFIG_POWERCAP=y
-CONFIG_INTEL_RAPL_CORE=m
-CONFIG_INTEL_RAPL=m
-# CONFIG_IDLE_INJECT is not set
-CONFIG_PECI=m
-CONFIG_PECI_CPU=m
-CONFIG_PECI_ASPEED=m
-CONFIG_SENSORS_PECI_CPUTEMP=m
-CONFIG_SENSORS_PECI_DIMMTEMP=m
-CONFIG_DTPM=y
-CONFIG_DTPM_CPU=y
-CONFIG_DTPM_DEVFREQ=y
-CONFIG_MCB=m
-CONFIG_MCB_PCI=m
-CONFIG_MCB_LPC=m
-
-#
-# Performance monitor support
-#
-# end of Performance monitor support
-
-CONFIG_RAS=y
-CONFIG_RAS_CEC=y
-# CONFIG_RAS_CEC_DEBUG is not set
-CONFIG_USB4=m
-# CONFIG_USB4_DEBUGFS_WRITE is not set
-# CONFIG_USB4_DMA_TEST is not set
-
-#
-# Android
-#
-CONFIG_ANDROID=y
-CONFIG_ANDROID_BINDER_IPC=m
-CONFIG_ANDROID_BINDERFS=y
-CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
-# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
-# end of Android
-
-CONFIG_LIBNVDIMM=m
-CONFIG_BLK_DEV_PMEM=m
-CONFIG_ND_BLK=m
-CONFIG_ND_CLAIM=y
-CONFIG_ND_BTT=m
-CONFIG_BTT=y
-CONFIG_NVDIMM_KEYS=y
-CONFIG_DAX_DRIVER=y
-CONFIG_DAX=y
-CONFIG_DEV_DAX=m
-CONFIG_DEV_DAX_HMEM=m
-CONFIG_DEV_DAX_HMEM_DEVICES=y
-CONFIG_DEV_DAX_KMEM=m
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_RAVE_SP_EEPROM=m
-CONFIG_NVMEM_SPMI_SDAM=m
-CONFIG_RAVE_SP_EEPROM=m
-CONFIG_NVMEM_RMEM=m
-CONFIG_NVMEM_LAYERSCAPE_SFP=m
-CONFIG_NVMEM_MESON_EFUSE=m
-CONFIG_NVMEM_SPRD_EFUSE=m
-
-#
-# HW tracing support
-#
-CONFIG_STM=m
-CONFIG_STM_PROTO_BASIC=m
-CONFIG_STM_PROTO_SYS_T=m
-# CONFIG_STM_DUMMY is not set
-CONFIG_STM_SOURCE_CONSOLE=m
-CONFIG_STM_SOURCE_HEARTBEAT=m
-# CONFIG_STM_SOURCE_FTRACE is not set
-# CONFIG_INTEL_TH is not set
-CONFIG_HISI_PTT=m
-# end of HW tracing support
-
-CONFIG_FPGA=m
-CONFIG_ALTERA_PR_IP_CORE=m
-CONFIG_FPGA_MGR_ALTERA_PS_SPI=m
-CONFIG_FPGA_MGR_ALTERA_CVP=m
-CONFIG_FPGA_MGR_XILINX_SPI=m
-CONFIG_FPGA_MGR_MACHXO2_SPI=m
-CONFIG_FPGA_BRIDGE=m
-CONFIG_ALTERA_FREEZE_BRIDGE=m
-CONFIG_XILINX_PR_DECOUPLER=m
-CONFIG_FPGA_REGION=m
-CONFIG_FPGA_DFL=m
-CONFIG_FPGA_DFL_FME=m
-CONFIG_FPGA_DFL_FME_MGR=m
-CONFIG_FPGA_DFL_FME_BRIDGE=m
-CONFIG_FPGA_DFL_FME_REGION=m
-CONFIG_FPGA_DFL_AFU=m
-CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m
-CONFIG_FPGA_DFL_PCI=m
-CONFIG_FPGA_M10_BMC_SEC_UPDATE=m
-CONFIG_FPGA_MGR_MICROCHIP_SPI=m
-CONFIG_TEE=m
-
-#
-# TEE drivers
-#
-CONFIG_AMDTEE=m
-# end of TEE drivers
-
-CONFIG_MULTIPLEXER=m
-
-#
-# Multiplexer drivers
-#
-CONFIG_MUX_ADG792A=m
-CONFIG_MUX_ADGS1408=m
-CONFIG_MUX_GPIO=m
-# end of Multiplexer drivers
-
-CONFIG_PM_OPP=y
-CONFIG_UNISYS_VISORBUS=m
-CONFIG_SIOX=m
-CONFIG_SIOX_BUS_GPIO=m
-CONFIG_SLIMBUS=m
-CONFIG_SLIM_QCOM_CTRL=m
-# CONFIG_INTERCONNECT is not set
-CONFIG_COUNTER=m
-CONFIG_INTERRUPT_CNT=m
-CONFIG_INTEL_QEP=m
-CONFIG_TI_ECAP_CAPTURE=m
-CONFIG_MOST=m
-CONFIG_MOST_USB_HDM=m
-CONFIG_MOST_CDEV=m
-CONFIG_MOST_SND=m
-# end of Device Drivers
-
-#
-# File systems
-#
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_VALIDATE_FS_PARSER=y
-CONFIG_FS_IOMAP=y
-# CONFIG_EXT2_FS is not set
-# CONFIG_EXT3_FS is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_USE_FOR_EXT2=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-# CONFIG_EXT4_DEBUG is not set
-CONFIG_JBD2=m
-# CONFIG_JBD2_DEBUG is not set
-CONFIG_FS_MBCACHE=m
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-CONFIG_REISERFS_PROC_INFO=y
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_SECURITY=y
-# CONFIG_JFS_DEBUG is not set
-CONFIG_JFS_STATISTICS=y
-CONFIG_XFS_FS=m
-# CONFIG_XFS_SUPPORT_V4 is not set
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_XFS_ONLINE_SCRUB=y
-# CONFIG_XFS_ONLINE_REPAIR is not set
-# CONFIG_XFS_WARN is not set
-# CONFIG_XFS_DEBUG is not set
-CONFIG_GFS2_FS=m
-CONFIG_GFS2_FS_LOCKING_DLM=y
-CONFIG_OCFS2_FS=m
-CONFIG_OCFS2_FS_O2CB=m
-CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
-CONFIG_OCFS2_FS_STATS=y
-CONFIG_OCFS2_DEBUG_MASKLOG=y
-CONFIG_OCFS2_DEBUG_FS=y
-CONFIG_BTRFS_FS=m
-CONFIG_BTRFS_FS_POSIX_ACL=y
-# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
-# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
-# CONFIG_BTRFS_DEBUG is not set
-# CONFIG_BTRFS_ASSERT is not set
-# CONFIG_BTRFS_FS_REF_VERIFY is not set
-CONFIG_NILFS2_FS=m
-CONFIG_F2FS_FS=m
-CONFIG_F2FS_STAT_FS=y
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_FS_POSIX_ACL=y
-CONFIG_F2FS_FS_SECURITY=y
-# CONFIG_F2FS_CHECK_FS is not set
-# CONFIG_F2FS_FAULT_INJECTION is not set
-CONFIG_F2FS_FS_COMPRESSION=y
-CONFIG_F2FS_FS_LZO=y
-CONFIG_F2FS_FS_LZORLE=y
-CONFIG_F2FS_FS_LZ4=y
-CONFIG_F2FS_FS_LZ4HC=y
-CONFIG_F2FS_FS_ZSTD=y
-# CONFIG_F2FS_IOSTAT is not set
-# CONFIG_F2FS_UNFAIR_RWSEM is not set
-CONFIG_ZONEFS_FS=m
-CONFIG_FS_DAX=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_EXPORTFS=y
-CONFIG_EXPORTFS_BLOCK_OPS=y
-CONFIG_FILE_LOCKING=y
-CONFIG_FS_ENCRYPTION=y
-CONFIG_FS_ENCRYPTION_ALGS=m
-# CONFIG_FS_VERITY is not set
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY_USER=y
-CONFIG_FANOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-# CONFIG_QUOTA_DEBUG is not set
-CONFIG_QUOTA_TREE=m
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=m
-CONFIG_QUOTACTL=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_AUTOFS_FS=y
-CONFIG_FUSE_FS=m
-CONFIG_CUSE=m
-CONFIG_VIRTIO_FS=m
-CONFIG_FUSE_DAX=y
-CONFIG_OVERLAY_FS=m
-CONFIG_OVERLAY_FS_REDIRECT_DIR=y
-CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
-CONFIG_OVERLAY_FS_INDEX=y
-CONFIG_OVERLAY_FS_NFS_EXPORT=y
-CONFIG_OVERLAY_FS_XINO_AUTO=y
-# CONFIG_OVERLAY_FS_METACOPY is not set
-
-#
-# Caches
-#
-CONFIG_NETFS_SUPPORT=m
-CONFIG_NETFS_STATS=y
-CONFIG_FSCACHE=m
-CONFIG_FSCACHE_STATS=y
-# CONFIG_FSCACHE_DEBUG is not set
-CONFIG_CACHEFILES=m
-# CONFIG_CACHEFILES_DEBUG is not set
-# end of Caches
-
-#
-# CD-ROM/DVD Filesystems
-#
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-# end of CD-ROM/DVD Filesystems
-
-#
-# DOS/FAT/EXFAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
-# CONFIG_FAT_DEFAULT_UTF8 is not set
-CONFIG_EXFAT_FS=m
-CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-CONFIG_NTFS_RW=y
-CONFIG_NTFS3_FS=m
-# CONFIG_NTFS3_64BIT_CLUSTER is not set
-CONFIG_NTFS3_LZX_XPRESS=y
-CONFIG_NTFS3_FS_POSIX_ACL=y
-# end of DOS/FAT/EXFAT/NT Filesystems
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_CHILDREN=y
-CONFIG_PROC_PID_ARCH_STATUS=y
-CONFIG_PROC_CPU_RESCTRL=y
-CONFIG_KERNFS=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TMPFS_XATTR=y
-CONFIG_TMPFS_INODE64=y
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_HUGETLB_PAGE_FREE_VMEMMAP=y
-CONFIG_HUGETLB_PAGE_FREE_VMEMMAP_DEFAULT_ON=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_EFIVAR_FS=m
-# end of Pseudo filesystems
-
-CONFIG_MISC_FILESYSTEMS=y
-CONFIG_ORANGEFS_FS=m
-CONFIG_ADFS_FS=m
-# CONFIG_ADFS_FS_RW is not set
-CONFIG_AFFS_FS=m
-CONFIG_ECRYPT_FS=m
-CONFIG_ECRYPT_FS_MESSAGING=y
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-# CONFIG_BEFS_DEBUG is not set
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RTIME=y
-CONFIG_JFFS2_RUBIN=y
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-CONFIG_UBIFS_FS=m
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-CONFIG_UBIFS_FS_ZSTD=y
-CONFIG_UBIFS_ATIME_SUPPORT=y
-CONFIG_UBIFS_FS_XATTR=y
-CONFIG_UBIFS_FS_SECURITY=y
-# CONFIG_UBIFS_FS_AUTHENTICATION is not set
-CONFIG_CRAMFS=m
-CONFIG_CRAMFS_BLOCKDEV=y
-CONFIG_CRAMFS_MTD=y
-CONFIG_SQUASHFS=m
-# CONFIG_SQUASHFS_FILE_CACHE is not set
-CONFIG_SQUASHFS_FILE_DIRECT=y
-# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
-CONFIG_SQUASHFS_DECOMP_MULTI=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_XATTR=y
-CONFIG_SQUASHFS_ZLIB=y
-CONFIG_SQUASHFS_LZ4=y
-CONFIG_SQUASHFS_LZO=y
-CONFIG_SQUASHFS_XZ=y
-CONFIG_SQUASHFS_ZSTD=y
-CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
-CONFIG_SQUASHFS_EMBEDDED=y
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_OMFS_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_QNX6FS_FS=m
-# CONFIG_QNX6FS_DEBUG is not set
-CONFIG_ROMFS_FS=m
-# CONFIG_ROMFS_BACKED_BY_BLOCK is not set
-# CONFIG_ROMFS_BACKED_BY_MTD is not set
-CONFIG_ROMFS_BACKED_BY_BOTH=y
-CONFIG_ROMFS_ON_BLOCK=y
-CONFIG_ROMFS_ON_MTD=y
-CONFIG_PSTORE=m
-CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_LZO_COMPRESS=y
-CONFIG_PSTORE_LZ4_COMPRESS=y
-CONFIG_PSTORE_LZ4HC_COMPRESS=y
-CONFIG_PSTORE_842_COMPRESS=y
-CONFIG_PSTORE_ZSTD_COMPRESS=y
-CONFIG_PSTORE_COMPRESS=y
-# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
-# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
-CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="zstd"
-# CONFIG_PSTORE_CONSOLE is not set
-CONFIG_PSTORE_PMSG=y
-# CONFIG_PSTORE_FTRACE is not set
-CONFIG_PSTORE_RAM=m
-CONFIG_PSTORE_ZONE=m
-CONFIG_PSTORE_BLK=m
-CONFIG_PSTORE_BLK_BLKDEV=""
-CONFIG_PSTORE_BLK_KMSG_SIZE=64
-CONFIG_PSTORE_BLK_MAX_REASON=2
-CONFIG_PSTORE_BLK_PMSG_SIZE=64
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-# CONFIG_UFS_FS_WRITE is not set
-# CONFIG_UFS_DEBUG is not set
-CONFIG_EROFS_FS=m
-# CONFIG_EROFS_FS_DEBUG is not set
-CONFIG_EROFS_FS_XATTR=y
-CONFIG_EROFS_FS_POSIX_ACL=y
-# CONFIG_EROFS_FS_SECURITY is not set
-# CONFIG_EROFS_FS_ZIP is not set
-CONFIG_VBOXSF_FS=m
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V2=m
-CONFIG_NFS_V3=m
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=m
-CONFIG_NFS_SWAP=y
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_V4_2=y
-CONFIG_PNFS_FILE_LAYOUT=m
-CONFIG_PNFS_BLOCK=m
-CONFIG_PNFS_FLEXFILE_LAYOUT=m
-CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
-CONFIG_NFS_V4_1_MIGRATION=y
-CONFIG_NFS_FSCACHE=y
-# CONFIG_NFS_USE_LEGACY_DNS is not set
-CONFIG_NFS_USE_KERNEL_DNS=y
-CONFIG_NFS_DISABLE_UDP_SUPPORT=y
-CONFIG_NFS_V4_2_READ_PLUS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V2_ACL=y
-CONFIG_NFSD_V3=y
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_PNFS=y
-CONFIG_NFSD_BLOCKLAYOUT=y
-CONFIG_NFSD_SCSILAYOUT=y
-CONFIG_NFSD_FLEXFILELAYOUT=y
-CONFIG_NFSD_V4_2_INTER_SSC=y
-CONFIG_GRACE_PERIOD=m
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_ACL_SUPPORT=m
-CONFIG_NFS_COMMON=y
-CONFIG_NFS_V4_2_SSC_HELPER=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_SUNRPC_BACKCHANNEL=y
-CONFIG_SUNRPC_SWAP=y
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
-# CONFIG_SUNRPC_DEBUG is not set
-CONFIG_SUNRPC_XPRT_RDMA=m
-CONFIG_CEPH_FS=m
-CONFIG_CEPH_FSCACHE=y
-CONFIG_CEPH_FS_POSIX_ACL=y
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS2=y
-CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
-CONFIG_CIFS_UPCALL=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-# CONFIG_CIFS_DEBUG is not set
-CONFIG_CIFS_DFS_UPCALL=y
-CONFIG_CIFS_SWN_UPCALL=y
-# CONFIG_CIFS_SMB_DIRECT is not set
-CONFIG_CIFS_FSCACHE=y
-CONFIG_SMB_SERVER=m
-CONFIG_SMB_SERVER_SMBDIRECT=y
-CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
-CONFIG_SMB_SERVER_KERBEROS5=y
-CONFIG_SMBFS_COMMON=m
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-# CONFIG_AFS_DEBUG is not set
-CONFIG_AFS_FSCACHE=y
-# CONFIG_AFS_DEBUG_CURSOR is not set
-CONFIG_9P_FS=m
-CONFIG_9P_FSCACHE=y
-CONFIG_9P_FS_POSIX_ACL=y
-CONFIG_9P_FS_SECURITY=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_MAC_ROMAN=m
-CONFIG_NLS_MAC_CELTIC=m
-CONFIG_NLS_MAC_CENTEURO=m
-CONFIG_NLS_MAC_CROATIAN=m
-CONFIG_NLS_MAC_CYRILLIC=m
-CONFIG_NLS_MAC_GAELIC=m
-CONFIG_NLS_MAC_GREEK=m
-CONFIG_NLS_MAC_ICELAND=m
-CONFIG_NLS_MAC_INUIT=m
-CONFIG_NLS_MAC_ROMANIAN=m
-CONFIG_NLS_MAC_TURKISH=m
-CONFIG_NLS_UTF8=m
-CONFIG_DLM=m
-# CONFIG_DLM_DEPRECATED_API is not set
-# CONFIG_DLM_DEBUG is not set
-CONFIG_UNICODE=y
-CONFIG_UNICODE_NORMALIZATION_SELFTEST=m
-CONFIG_IO_WQ=y
-# end of File systems
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-# CONFIG_KEYS_REQUEST_CACHE is not set
-CONFIG_PERSISTENT_KEYRINGS=y
-CONFIG_TRUSTED_KEYS=m
-CONFIG_ENCRYPTED_KEYS=m
-CONFIG_USER_DECRYPTED_DATA=y
-CONFIG_KEY_DH_OPERATIONS=y
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-# CONFIG_SECURITY is not set
-CONFIG_SECURITYFS=y
-CONFIG_PAGE_TABLE_ISOLATION=y
-CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
-CONFIG_HARDENED_USERCOPY=y
-# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
-CONFIG_FORTIFY_SOURCE=y
-# CONFIG_STATIC_USERMODEHELPER is not set
-# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_LSM="yama,loadpin,safesetid,integrity,bpf"
-
-#
-# Kernel hardening options
-#
-
-#
-# Memory initialization
-#
-CONFIG_INIT_STACK_NONE=y
-# CONFIG_INIT_STACK_ALL_PATTERN is not set
-# CONFIG_INIT_STACK_ALL_ZERO is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
-# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
-# CONFIG_GCC_PLUGIN_STACKLEAK is not set
-# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
-# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
-CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
-CONFIG_CC_USING_FENTRY=y
-# CONFIG_ZERO_CALL_USED_REGS is not set
-# end of Memory initialization
-# end of Kernel hardening options
-# end of Security options
-
-CONFIG_XOR_BLOCKS=m
-CONFIG_ASYNC_CORE=m
-CONFIG_ASYNC_MEMCPY=m
-CONFIG_ASYNC_XOR=m
-CONFIG_ASYNC_PQ=m
-CONFIG_ASYNC_RAID6_RECOV=m
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD=m
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_SKCIPHER=y
-CONFIG_CRYPTO_SKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG=m
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=m
-CONFIG_CRYPTO_AKCIPHER2=y
-CONFIG_CRYPTO_AKCIPHER=y
-CONFIG_CRYPTO_KPP2=y
-CONFIG_CRYPTO_KPP=m
-CONFIG_CRYPTO_ACOMP2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_USER=m
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_PCRYPT=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_SIMD=m
-CONFIG_CRYPTO_ENGINE=m
-
-#
-# Public-key cryptography
-#
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_DH=m
-CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
-CONFIG_CRYPTO_ECC=m
-CONFIG_CRYPTO_ECDH=m
-CONFIG_CRYPTO_ECDSA=m
-CONFIG_CRYPTO_ECRDSA=m
-CONFIG_CRYPTO_SM2=m
-CONFIG_CRYPTO_CURVE25519=m
-CONFIG_CRYPTO_CURVE25519_X86=m
-
-#
-# Authenticated Encryption with Associated Data
-#
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_GCM=m
-CONFIG_CRYPTO_CHACHA20POLY1305=m
-CONFIG_CRYPTO_AEGIS128=m
-CONFIG_CRYPTO_AEGIS128_AESNI_SSE2=m
-CONFIG_CRYPTO_SEQIV=m
-CONFIG_CRYPTO_ECHAINIV=m
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CFB=m
-CONFIG_CRYPTO_CTR=m
-CONFIG_CRYPTO_CTS=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_OFB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_KEYWRAP=m
-CONFIG_CRYPTO_NHPOLY1305=m
-CONFIG_CRYPTO_NHPOLY1305_SSE2=m
-CONFIG_CRYPTO_NHPOLY1305_AVX2=m
-CONFIG_CRYPTO_ADIANTUM=m
-CONFIG_CRYPTO_HCTR2=m
-CONFIG_CRYPTO_ARIA=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
-CONFIG_CRYPTO_DEV_QAT_C3XXX=m
-CONFIG_CRYPTO_DEV_QAT_C62X=m
-CONFIG_CRYPTO_DEV_QAT_4XXX=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
-CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
-CONFIG_CRYPTO_DEV_QAT_C62XVF=m
-CONFIG_CRYPTO_ESSIV=m
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_CMAC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CRC32C_INTEL=m
-CONFIG_CRYPTO_CRC32=m
-CONFIG_CRYPTO_CRC32_PCLMUL=m
-CONFIG_CRYPTO_XXHASH=m
-CONFIG_CRYPTO_BLAKE2B=m
-CONFIG_CRYPTO_BLAKE2S=m
-CONFIG_CRYPTO_BLAKE2S_X86=m
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_CRCT10DIF_PCLMUL=m
-CONFIG_CRYPTO_GHASH=m
-CONFIG_CRYPTO_POLYVAL_CLMUL_NI=m
-CONFIG_CRYPTO_POLY1305=m
-CONFIG_CRYPTO_POLY1305_X86_64=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_SSSE3=m
-CONFIG_CRYPTO_SHA256_SSSE3=m
-CONFIG_CRYPTO_SHA512_SSSE3=m
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SHA3=m
-CONFIG_CRYPTO_SM3=m
-CONFIG_CRYPTO_SM3_AVX_X86_64=m
-CONFIG_CRYPTO_STREEBOG=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_AES_TI=m
-CONFIG_CRYPTO_AES_NI_INTEL=m
-CONFIG_CRYPTO_ANUBIS=m
-# CONFIG_CRYPTO_ARC4 is not set
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_BLOWFISH_COMMON=m
-CONFIG_CRYPTO_BLOWFISH_X86_64=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAMELLIA_X86_64=m
-CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64=m
-CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=m
-CONFIG_CRYPTO_CAST_COMMON=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST5_AVX_X86_64=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_CAST6_AVX_X86_64=m
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DES3_EDE_X86_64=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_CHACHA20=m
-CONFIG_CRYPTO_CHACHA20_X86_64=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_SERPENT_SSE2_X86_64=m
-CONFIG_CRYPTO_SERPENT_AVX_X86_64=m
-CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m
-CONFIG_CRYPTO_SM4=m
-CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64=m
-CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-CONFIG_CRYPTO_TWOFISH_X86_64=m
-CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=m
-CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m
-CONFIG_CRYPTO_ARIA_AESNI_AVX_X86_64=m
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_842=y
-CONFIG_CRYPTO_LZ4=y
-CONFIG_CRYPTO_LZ4HC=y
-CONFIG_CRYPTO_ZSTD=y
-
-#
-# Random Number Generation
-#
-CONFIG_CRYPTO_ANSI_CPRNG=m
-CONFIG_CRYPTO_DRBG_MENU=m
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_HASH=y
-CONFIG_CRYPTO_DRBG_CTR=y
-CONFIG_CRYPTO_DRBG=m
-CONFIG_CRYPTO_JITTERENTROPY=m
-CONFIG_CRYPTO_USER_API=m
-CONFIG_CRYPTO_USER_API_HASH=y
-CONFIG_CRYPTO_USER_API_SKCIPHER=m
-CONFIG_CRYPTO_USER_API_RNG=m
-# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
-CONFIG_CRYPTO_USER_API_AEAD=m
-CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
-# CONFIG_CRYPTO_STATS is not set
-CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=m
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_SM4=m
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_DEV_PADLOCK=m
-CONFIG_CRYPTO_DEV_PADLOCK_AES=m
-CONFIG_CRYPTO_DEV_PADLOCK_SHA=m
-CONFIG_CRYPTO_DEV_ATMEL_I2C=m
-CONFIG_CRYPTO_DEV_ATMEL_ECC=m
-CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m
-CONFIG_CRYPTO_DEV_CCP=y
-CONFIG_CRYPTO_DEV_CCP_DD=m
-CONFIG_CRYPTO_DEV_SP_CCP=y
-CONFIG_CRYPTO_DEV_CCP_CRYPTO=m
-CONFIG_CRYPTO_DEV_SP_PSP=y
-# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set
-CONFIG_CRYPTO_DEV_QAT=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCC=m
-CONFIG_CRYPTO_DEV_QAT_C3XXX=m
-CONFIG_CRYPTO_DEV_QAT_C62X=m
-CONFIG_CRYPTO_DEV_QAT_4XXX=m
-CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m
-CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m
-CONFIG_CRYPTO_DEV_QAT_C62XVF=m
-CONFIG_CRYPTO_DEV_NITROX=m
-CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m
-CONFIG_CRYPTO_DEV_CHELSIO=m
-CONFIG_CRYPTO_DEV_VIRTIO=m
-CONFIG_CRYPTO_DEV_SAFEXCEL=m
-CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
-CONFIG_CRYPTO_DEV_ASPEED=m
-# CONFIG_CRYPTO_DEV_ASPEED_DEBUG is not set
-CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH=y
-CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO=y
-# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set
-CONFIG_ASYMMETRIC_KEY_TYPE=y
-CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
-CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE=m
-CONFIG_X509_CERTIFICATE_PARSER=y
-CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
-CONFIG_TPM_KEY_PARSER=m
-CONFIG_PKCS7_MESSAGE_PARSER=y
-CONFIG_PKCS7_TEST_KEY=m
-CONFIG_SIGNED_PE_FILE_VERIFICATION=y
-
-#
-# Certificates for signature checking
-#
-CONFIG_MODULE_SIG_KEY="certs/signing_key.pem"
-CONFIG_MODULE_SIG_KEY_TYPE_RSA=y
-# CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set
-CONFIG_SYSTEM_TRUSTED_KEYRING=y
-CONFIG_SYSTEM_TRUSTED_KEYS=""
-# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
-CONFIG_SECONDARY_TRUSTED_KEYRING=y
-CONFIG_SYSTEM_BLACKLIST_KEYRING=y
-CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
-# CONFIG_SYSTEM_REVOCATION_LIST is not set
-# end of Certificates for signature checking
-
-CONFIG_BINARY_PRINTF=y
-
-#
-# Library routines
-#
-CONFIG_RAID6_PQ=m
-CONFIG_RAID6_PQ_BENCHMARK=y
-CONFIG_LINEAR_RANGES=y
-CONFIG_PACKING=y
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_CORDIC=m
-CONFIG_PRIME_NUMBERS=m
-CONFIG_RATIONAL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
-CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC64_ROCKSOFT=m
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC32_SELFTEST is not set
-CONFIG_CRC32_SLICEBY8=y
-# CONFIG_CRC32_SLICEBY4 is not set
-# CONFIG_CRC32_SARWATE is not set
-# CONFIG_CRC32_BIT is not set
-CONFIG_CRC64=m
-CONFIG_CRC4=m
-CONFIG_CRC7=m
-CONFIG_LIBCRC32C=m
-CONFIG_CRC8=m
-CONFIG_XXHASH=y
-# CONFIG_RANDOM32_SELFTEST is not set
-CONFIG_842_COMPRESS=y
-CONFIG_842_DECOMPRESS=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_LZ4_COMPRESS=y
-CONFIG_LZ4HC_COMPRESS=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
-CONFIG_XZ_DEC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_MICROLZMA=y
-CONFIG_XZ_DEC_BCJ=y
-# CONFIG_XZ_DEC_TEST is not set
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_LZ4=y
-CONFIG_DECOMPRESS_ZSTD=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_REED_SOLOMON=m
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_DEC16=y
-CONFIG_BCH=m
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_BTREE=y
-CONFIG_INTERVAL_TREE=y
-CONFIG_XARRAY_MULTI=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAS_DMA=y
-CONFIG_DMA_OPS=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED=y
-CONFIG_SWIOTLB=y
-CONFIG_DMA_COHERENT_POOL=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_PERNUMA_CMA=y
-
-#
-# Default contiguous memory area size:
-#
-CONFIG_CMA_SIZE_MBYTES=0
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_ALIGNMENT=8
-# CONFIG_DMA_API_DEBUG is not set
-# CONFIG_DMA_MAP_BENCHMARK is not set
-CONFIG_SGL_ALLOC=y
-CONFIG_CHECK_SIGNATURE=y
-CONFIG_CPUMASK_OFFSTACK=y
-CONFIG_CPU_RMAP=y
-CONFIG_DQL=y
-CONFIG_GLOB=y
-# CONFIG_GLOB_SELFTEST is not set
-CONFIG_NLATTR=y
-CONFIG_LRU_CACHE=m
-CONFIG_CLZ_TAB=y
-CONFIG_IRQ_POLL=y
-CONFIG_MPILIB=y
-CONFIG_DIMLIB=y
-CONFIG_OID_REGISTRY=y
-CONFIG_UCS2_STRING=y
-CONFIG_HAVE_GENERIC_VDSO=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_VDSO_TIME_NS=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_6x10 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-CONFIG_FONT_TER16x32=y
-CONFIG_FONT_6x8=y
-CONFIG_SG_POOL=y
-CONFIG_ARCH_HAS_PMEM_API=y
-CONFIG_MEMREGION=y
-CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y
-CONFIG_ARCH_HAS_COPY_MC=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_SBITMAP=y
-CONFIG_PARMAN=m
-CONFIG_OBJAGG=m
-# end of Library routines
-
-CONFIG_PLDMFW=y
-CONFIG_ASN1_ENCODER=m
-
-#
-# Kernel hacking
-#
-
-#
-# printk and dmesg options
-#
-# CONFIG_PRINTK_TIME is not set
-# CONFIG_PRINTK_CALLER is not set
-CONFIG_STACKTRACE_BUILD_ID=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
-CONFIG_CONSOLE_LOGLEVEL_QUIET=4
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_DYNAMIC_DEBUG_CORE is not set
-CONFIG_SYMBOLIC_ERRNAME=y
-CONFIG_DEBUG_BUGVERBOSE=y
-# end of printk and dmesg options
-
-#
-# Compile-time checks and compiler options
-#
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_INFO_REDUCED is not set
-# CONFIG_DEBUG_INFO_COMPRESSED is not set
-# CONFIG_DEBUG_INFO_SPLIT is not set
-# CONFIG_DEBUG_INFO_NONE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-# CONFIG_DEBUG_INFO_DWARF4 is not set
-# CONFIG_DEBUG_INFO_DWARF5 is not set
-CONFIG_DEBUG_INFO_BTF=y
-CONFIG_MODULE_ALLOW_BTF_MISMATCH=y
-CONFIG_PAHOLE_HAS_SPLIT_BTF=y
-CONFIG_DEBUG_INFO_BTF_MODULES=y
-# CONFIG_GDB_SCRIPTS is not set
-CONFIG_FRAME_WARN=0
-CONFIG_STRIP_ASM_SYMS=y
-# CONFIG_READABLE_ASM is not set
-# CONFIG_HEADERS_INSTALL is not set
-# CONFIG_DEBUG_SECTION_MISMATCH is not set
-CONFIG_SECTION_MISMATCH_WARN_ONLY=y
-# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
-CONFIG_STACK_VALIDATION=y
-CONFIG_VMLINUX_MAP=y
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# end of Compile-time checks and compiler options
-
-#
-# Generic Kernel Debugging Instruments
-#
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
-CONFIG_MAGIC_SYSRQ_SERIAL=y
-CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=""
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_FS_ALLOW_ALL is not set
-# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
-# CONFIG_DEBUG_FS_ALLOW_NONE is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ARCH_KCSAN=y
-CONFIG_HAVE_KCSAN_COMPILER=y
-# CONFIG_KCSAN is not set
-# end of Generic Kernel Debugging Instruments
-
-# CONFIG_DEBUG_KERNEL is not set
-# CONFIG_DEBUG_MISC is not set
-
-#
-# Memory Debugging
-#
-# CONFIG_PAGE_EXTENSION is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
-# CONFIG_PAGE_OWNER is not set
-# CONFIG_PAGE_TABLE_CHECK is not set
-# CONFIG_PAGE_POISONING is not set
-# CONFIG_DEBUG_PAGE_REF is not set
-# CONFIG_DEBUG_RODATA_TEST is not set
-CONFIG_ARCH_HAS_DEBUG_WX=y
-CONFIG_DEBUG_WX=y
-CONFIG_GENERIC_PTDUMP=y
-CONFIG_PTDUMP_CORE=y
-# CONFIG_PTDUMP_DEBUGFS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SHRINKER_DEBUG is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_HAVE_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_SCHED_STACK_END_CHECK is not set
-# CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_VM_PGTABLE is not set
-# CONFIG_ARCH_HAS_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_VIRTUAL is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_PER_CPU_MAPS is not set
-CONFIG_HAVE_ARCH_KASAN=y
-CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
-CONFIG_CC_HAS_KASAN_GENERIC=y
-CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
-# CONFIG_KASAN is not set
-CONFIG_HAVE_ARCH_KFENCE=y
-# CONFIG_KFENCE is not set
-# end of Memory Debugging
-
-# CONFIG_DEBUG_SHIRQ is not set
-
-#
-# Debug Oops, Lockups and Hangs
-#
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=60
-# CONFIG_SOFTLOCKUP_DETECTOR is not set
-CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y
-# CONFIG_HARDLOCKUP_DETECTOR is not set
-# CONFIG_DETECT_HUNG_TASK is not set
-# CONFIG_WQ_WATCHDOG is not set
-CONFIG_TEST_LOCKUP=m
-# end of Debug Oops, Lockups and Hangs
-
-#
-# Scheduler Debugging
-#
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHED_INFO=y
-CONFIG_SCHEDSTATS=y
-# end of Scheduler Debugging
-
-# CONFIG_DEBUG_TIMEKEEPING is not set
-# CONFIG_DEBUG_PREEMPT is not set
-
-#
-# Lock Debugging (spinlocks, mutexes, etc...)
-#
-# CONFIG_LOCK_DEBUGGING_SUPPORT is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
-# CONFIG_DEBUG_RWSEMS is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_DEBUG_ATOMIC_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_LOCK_TORTURE_TEST is not set
-# CONFIG_WW_MUTEX_SELFTEST is not set
-CONFIG_SCF_TORTURE_TEST=m
-# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
-# end of Lock Debugging (spinlocks, mutexes, etc...)
-
-# CONFIG_DEBUG_IRQFLAGS is not set
-CONFIG_STACKTRACE=y
-# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
-# CONFIG_DEBUG_KOBJECT is not set
-
-#
-# Debug kernel data structures
-#
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_PLIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BUG_ON_DATA_CORRUPTION is not set
-# end of Debug kernel data structures
-
-# CONFIG_DEBUG_CREDENTIALS is not set
-
-#
-# RCU Debugging
-#
-CONFIG_TORTURE_TEST=m
-CONFIG_RCU_SCALE_TEST=m
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_REF_SCALE_TEST=m
-CONFIG_RCU_CPU_STALL_TIMEOUT=60
-# CONFIG_RCU_TRACE is not set
-# CONFIG_RCU_EQS_DEBUG is not set
-# end of RCU Debugging
-
-# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-CONFIG_LATENCYTOP=y
-CONFIG_USER_STACKTRACE_SUPPORT=y
-CONFIG_NOP_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_FENTRY=y
-CONFIG_HAVE_OBJTOOL_MCOUNT=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_RING_BUFFER=y
-CONFIG_EVENT_TRACING=y
-CONFIG_CONTEXT_SWITCH_TRACER=y
-CONFIG_TRACING=y
-CONFIG_GENERIC_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-CONFIG_FTRACE=y
-CONFIG_BOOTTIME_TRACING=y
-CONFIG_FUNCTION_TRACER=y
-# CONFIG_FUNCTION_GRAPH_TRACER is not set
-CONFIG_DYNAMIC_FTRACE=y
-CONFIG_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
-CONFIG_DYNAMIC_FTRACE_WITH_ARGS=y
-# CONFIG_FPROBE is not set
-CONFIG_FUNCTION_PROFILER=y
-CONFIG_STACK_TRACER=y
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_HWLAT_TRACER is not set
-# CONFIG_OSNOISE_TRACER is not set
-# CONFIG_TIMERLAT_TRACER is not set
-# CONFIG_MMIOTRACE is not set
-CONFIG_FTRACE_SYSCALLS=y
-# CONFIG_TRACER_SNAPSHOT is not set
-CONFIG_BRANCH_PROFILE_NONE=y
-# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
-# CONFIG_PROFILE_ALL_BRANCHES is not set
-CONFIG_BLK_DEV_IO_TRACE=y
-CONFIG_KPROBE_EVENTS=y
-# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set
-# CONFIG_UPROBE_EVENTS is not set
-CONFIG_BPF_EVENTS=y
-CONFIG_DYNAMIC_EVENTS=y
-CONFIG_PROBE_EVENTS=y
-CONFIG_BPF_KPROBE_OVERRIDE=y
-CONFIG_FTRACE_MCOUNT_RECORD=y
-CONFIG_FTRACE_MCOUNT_USE_CC=y
-# CONFIG_SYNTH_EVENTS is not set
-# CONFIG_HIST_TRIGGERS is not set
-# CONFIG_TRACE_EVENT_INJECT is not set
-# CONFIG_TRACEPOINT_BENCHMARK is not set
-# CONFIG_RING_BUFFER_BENCHMARK is not set
-# CONFIG_TRACE_EVAL_MAP_FILE is not set
-CONFIG_FTRACE_RECORD_RECURSION=y
-CONFIG_FTRACE_RECORD_RECURSION_SIZE=128
-CONFIG_RING_BUFFER_RECORD_RECURSION=y
-# CONFIG_FTRACE_STARTUP_TEST is not set
-# CONFIG_RING_BUFFER_STARTUP_TEST is not set
-# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
-CONFIG_PREEMPTIRQ_DELAY_TEST=m
-CONFIG_KPROBE_EVENT_GEN_TEST=m
-# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y
-CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y
-CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
-CONFIG_STRICT_DEVMEM=y
-# CONFIG_IO_STRICT_DEVMEM is not set
-
-#
-# x86 Debugging
-#
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_X86_VERBOSE_BOOTUP=y
-# CONFIG_EARLY_PRINTK is not set
-# CONFIG_EFI_PGT_DUMP is not set
-# CONFIG_DEBUG_TLBFLUSH is not set
-CONFIG_HAVE_MMIOTRACE_SUPPORT=y
-# CONFIG_X86_DECODER_SELFTEST is not set
-CONFIG_IO_DELAY_0X80=y
-# CONFIG_IO_DELAY_0XED is not set
-# CONFIG_IO_DELAY_UDELAY is not set
-# CONFIG_IO_DELAY_NONE is not set
-# CONFIG_DEBUG_BOOT_PARAMS is not set
-# CONFIG_CPA_DEBUG is not set
-# CONFIG_DEBUG_ENTRY is not set
-# CONFIG_DEBUG_NMI_SELFTEST is not set
-# CONFIG_X86_DEBUG_FPU is not set
-# CONFIG_PUNIT_ATOM_DEBUG is not set
-CONFIG_UNWINDER_ORC=y
-# CONFIG_UNWINDER_FRAME_POINTER is not set
-# CONFIG_UNWINDER_GUESS is not set
-# end of x86 Debugging
-
-#
-# Kernel Testing and Coverage
-#
-# CONFIG_KUNIT is not set
-# CONFIG_NOTIFIER_ERROR_INJECTION is not set
-CONFIG_FUNCTION_ERROR_INJECTION=y
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_ARCH_HAS_KCOV=y
-CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-# CONFIG_KCOV is not set
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_ARCH_USE_MEMTEST=y
-CONFIG_MEMTEST=y
-# CONFIG_HYPERV_TESTING is not set
-# end of Kernel Testing and Coverage
-# end of Kernel hacking
-# CONFIG_ANON_VMA_NAME is not set
-CONFIG_NET_9P_FD=m
-CONFIG_DEVTMPFS_SAFE=y
-CONFIG_GNSS_USB=m
-CONFIG_MTD_NAND_RENESAS=m
-CONFIG_NET_VENDOR_ENGLEDER=y
-CONFIG_TSNEP=m
-# CONFIG_TSNEP_SELFTESTS is not set
-CONFIG_LAN966X_SWITCH=m
-CONFIG_NET_VENDOR_VERTEXCOM=y
-CONFIG_MSE102X=m
-CONFIG_MCTP_SERIAL=m
-CONFIG_MCTP_TRANSPORT_I2C=m
-# CONFIG_WWAN_DEBUGFS is not set
-CONFIG_SERIAL_8250_PERICOM=m
-CONFIG_SPMI_MTK_PMIF=m
-CONFIG_PINCTRL_IMXRT1050=y
-CONFIG_PINCTRL_IMX93=m
-CONFIG_PINCTRL_SDX65=m
-CONFIG_PINCTRL_SM8450=m
-CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
-CONFIG_PINCTRL_SM8450_LPASS_LPI=m
-CONFIG_PINCTRL_SM8280XP_LPASS_LPI=m
-CONFIG_GPIO_SIM=m
-CONFIG_CHARGER_MAX77976=m
-CONFIG_CHARGER_MT6370=m
-CONFIG_SENSORS_NZXT_SMART2=m
-CONFIG_SENSORS_DELTA_AHE50DC_FAN=m
-CONFIG_SENSORS_IR38064_REGULATOR=y
-CONFIG_SENSORS_MP5023=m
-CONFIG_SENSORS_INA238=m
-CONFIG_RZG2L_THERMAL=m
-CONFIG_RENESAS_RZG2LWDT=m
-CONFIG_REGULATOR_MAX20086=m
-CONFIG_VIDEO_STM32_DMA2D=m
-CONFIG_VIDEO_OV5693=m
-CONFIG_DRM_RCAR_USE_LVDS=y
-CONFIG_DRM_RCAR_USE_MIPI_DSI=y
-CONFIG_DRM_RCAR_MIPI_DSI=m
-CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m
-CONFIG_DRM_PANEL_JDI_R63452=m
-CONFIG_DRM_PANEL_NOVATEK_NT35950=m
-CONFIG_DRM_PANEL_NOVATEK_NT35560=m
-CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m
-CONFIG_TINYDRM_ILI9163=m
-CONFIG_SND_AMD_ACP_CONFIG=m
-CONFIG_SND_SOC_APPLE_MCA=m
-CONFIG_SND_SOC_AK4375=m
-CONFIG_SND_SOC_TLV320ADC3XXX=m
-CONFIG_HID_LETSKETCH=m
-CONFIG_LEDS_MT6360=m
-CONFIG_VIDEO_MAX96712=m
-CONFIG_COMMON_CLK_LAN966X=y
-CONFIG_COMMON_CLK_MT7986=y
-CONFIG_COMMON_CLK_MT7986_ETHSYS=y
-CONFIG_RENESAS_OSTM=y
-CONFIG_EXYNOS_USI=m
-CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
-CONFIG_AD74413R=m
-CONFIG_AD3552R=m
-CONFIG_AD7293=m
-CONFIG_ADMV1013=m
-CONFIG_ADMV1014=m
-CONFIG_ADMV4420=m
-CONFIG_PHY_MESON8_HDMI_TX=m
-CONFIG_PHY_FSL_IMX8M_PCIE=m
-CONFIG_PHY_FSL_LYNX_28G=m
-CONFIG_PHY_LAN966X_SERDES=m
-CONFIG_PHY_QCOM_EDP=m
-# CONFIG_CACHEFILES_ERROR_INJECTION is not set
-CONFIG_UNICODE_UTF8_DATA=m
-# CONFIG_NET_DEV_REFCNT_TRACKER is not set
-# CONFIG_NET_NS_REFCNT_TRACKER is not set
-# CONFIG_KFENCE is not set
-# CONFIG_FTRACE_SORT_STARTUP_TEST is not set
-CONFIG_BACKTRACE_VERBOSE=y
-CONFIG_ADMV8818=m
-CONFIG_MARVELL_CN10K_TAD_PMU=m
-# CONFIG_KCSAN is not set
-# CONFIG_BOOT_CONFIG_EMBED is not set
-CONFIG_INITRAMFS_PRESERVE_MTIME=y
-CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y
-CONFIG_ARCH_BCMBCA=y
-CONFIG_ARCH_HPE=y
-CONFIG_ARCH_HPE_GXP=y
-CONFIG_ARM_ERRATA_764319=y
-# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set
-CONFIG_CAN_CTUCANFD_PCI=m
-CONFIG_CAN_CTUCANFD_PLATFORM=m
-CONFIG_FW_LOADER_COMPRESS_XZ=y
-CONFIG_FW_LOADER_COMPRESS_ZSTD=y
-CONFIG_FW_UPLOAD=y
-CONFIG_QCOM_SSC_BLOCK_BUS=y
-CONFIG_MHI_BUS_EP=m
-CONFIG_MTK_ADSP_IPC=m
-CONFIG_EFI_COCO_SECRET=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=m
-CONFIG_SFC_SIENA=m
-CONFIG_SFC_SIENA_MTD=y
-CONFIG_SFC_SIENA_MCDI_MON=y
-CONFIG_SFC_SIENA_SRIOV=y
-# CONFIG_SFC_SIENA_MCDI_LOGGING is not set
-CONFIG_ADIN1100_PHY=m
-CONFIG_DP83TD510_PHY=m
-CONFIG_WLAN_VENDOR_PURELIFI=y
-CONFIG_PLFXLC=m
-CONFIG_RTW89_8852CE=m
-CONFIG_WLAN_VENDOR_SILABS=y
-CONFIG_MTK_T7XX=m
-CONFIG_JOYSTICK_SENSEHAT=m
-CONFIG_INPUT_IQS7222=m
-# CONFIG_HVC_DCC_SERIALIZE_SMP is not set
-CONFIG_SPI_MTK_SNFI=m
-CONFIG_PINCTRL_IMXRT1170=y
-CONFIG_PINCTRL_SC7280_LPASS_LPI=m
-CONFIG_PINCTRL_SM8250_LPASS_LPI=m
-CONFIG_SENSORS_LAN966X=m
-CONFIG_SENSORS_NCT6775_I2C=m
-CONFIG_SENSORS_XDPE152=m
-CONFIG_RENESAS_RZN1WDT=m
-CONFIG_GXP_WATCHDOG=m
-CONFIG_REGULATOR_RT5759=m
-CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
-CONFIG_DRM_FSL_LDB=m
-CONFIG_DRM_LONTIUM_LT9211=m
-CONFIG_DRM_DW_HDMI_GP_AUDIO=m
-CONFIG_DRM_SSD130X_SPI=m
-CONFIG_SND_SERIAL_GENERIC=m
-CONFIG_SND_SOC_CS35L45_SPI=m
-CONFIG_SND_SOC_CS35L45_I2C=m
-CONFIG_SND_SOC_MAX98396=m
-CONFIG_SND_SOC_WM8731_I2C=m
-CONFIG_SND_SOC_WM8731_SPI=m
-CONFIG_SND_SOC_WM8940=m
-CONFIG_HID_MEGAWORLD_FF=m
-CONFIG_TYPEC_MUX_FSA4480=m
-CONFIG_LEDS_PWM_MULTICOLOR=m
-CONFIG_LEDS_QCOM_LPG=m
-CONFIG_TEGRA186_GPC_DMA=m
-# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set
-CONFIG_PWM_XILINX=m
-CONFIG_HTE=y
-# CONFIG_CACHEFILES_ONDEMAND is not set
-CONFIG_TRUSTED_KEYS_TPM=y
-CONFIG_TRUSTED_KEYS_TEE=y
-CONFIG_CRYPTO_SM3_GENERIC=m
-CONFIG_CRYPTO_SM4_GENERIC=m
-# CONFIG_FIPS_SIGNATURE_SELFTEST is not set
-CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y
-# CONFIG_DEBUG_NET is not set
-CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
-CONFIG_SPECULATION_MITIGATIONS=y
-CONFIG_EFI_DXE_MEM_ATTRIBUTES=y
-CONFIG_INTEL_MEI_GSC=m
-CONFIG_PINCTRL_AMD=y
-CONFIG_WINMATE_FM07_KEYS=m
-CONFIG_CHROMEOS_ACPI=m
-CONFIG_NVSW_SN2201=m
-CONFIG_DMARD06=m
-CONFIG_IIO_RESCALE=m
-CONFIG_DPOT_DAC=m
-CONFIG_VF610_DAC=m
-CONFIG_CM3605=m
-CONFIG_AK8974=m
-CONFIG_IIO_MUX=m
-CONFIG_RETHUNK=y
-CONFIG_CPU_UNRET_ENTRY=y
-# CONFIG_CGROUP_FAVOR_DYNMODS is not set
-CONFIG_ARCH_BCMBCA_CORTEXA7=y
-CONFIG_ARCH_BCMBCA_CORTEXA9=y
-CONFIG_ARCH_BCMBCA_BRAHMAB15=y
-CONFIG_ARCH_MSM8909=y
-CONFIG_ARCH_SUNPLUS=y
-CONFIG_SOC_SP7021=y
-# CONFIG_UNUSED_BOARD_FILES is not set
-# CONFIG_PM_USERSPACE_AUTOSLEEP is not set
-CONFIG_DAMON_LRU_SORT=y
-CONFIG_NF_FLOW_TABLE_PROCFS=y
-CONFIG_NET_DSA_TAG_RZN1_A5PSW=m
-CONFIG_PCI_EPF_VNTB=m
-CONFIG_ARM_SCMI_POWER_CONTROL=m
-CONFIG_BLK_DEV_UBLK=m
-CONFIG_NVME_AUTH=y
-CONFIG_NVME_TARGET_AUTH=y
-CONFIG_VCPU_STALL_DETECTOR=m
-CONFIG_SCSI_BUSLOGIC=m
-CONFIG_SCSI_FLASHPOINT=y
-CONFIG_AHCI_BRCM=m
-CONFIG_AHCI_DWC=m
-CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
-CONFIG_NET_VENDOR_WANGXUN=y
-CONFIG_NET_VENDOR_ADI=y
-CONFIG_ADIN1110=m
-CONFIG_NGBE=m
-CONFIG_TXGBE=m
-CONFIG_NET_VENDOR_SUNPLUS=y
-CONFIG_SP7021_EMAC=m
-CONFIG_CAN_NETLINK=y
-CONFIG_CAN_CAN327=m
-CONFIG_CAN_ESD_USB=m
-CONFIG_HW_RANDOM_BCM2835=m
-CONFIG_TCG_TIS_I2C=m
-# CONFIG_RANDOM_TRUST_CPU is not set
-CONFIG_I2C_BRCMSTB=m
-CONFIG_I2C_NPCM=m
-CONFIG_I2C_RZV2M=m
-CONFIG_SPI_BCM63XX_HSSPI=m
-CONFIG_SPI_GXP=m
-CONFIG_SPI_MICROCHIP_CORE=m
-CONFIG_SPI_MICROCHIP_CORE_QSPI=m
-CONFIG_SPI_SUNPLUS_SP7021=m
-CONFIG_PINCTRL_MSM8909=m
-CONFIG_PINCTRL_SM6375=m
-CONFIG_PINCTRL_SUN20I_D1=y
-CONFIG_SENSORS_LT7182S=m
-CONFIG_SUNPLUS_WATCHDOG=m
-CONFIG_VIDEO_SUN6I_MIPI_CSI2=m
-CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m
-CONFIG_VIDEO_AR0521=m
-CONFIG_DRM_PANEL_EBBG_FT8719=m
-CONFIG_DRM_TI_DLPC3433=m
-CONFIG_DRM_IMX8QM_LDB=m
-# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set
-CONFIG_RCU_NOCB_CPU_DEFAULT_ALL=y
-CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
-CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m
-CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m
-# CONFIG_RV is not set
-CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219=m
-CONFIG_SND_SOC_SOF_METEORLAKE=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT274=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT286=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT298=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682=m
-CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567=m
-CONFIG_ANDROID_BINDER_IPC=y
-CONFIG_ANDROID_BINDERFS=y
-CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder"
-# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
-# Ethernet Power Sourcing Equipment Support
-CONFIG_PSE_CONTROLLER=y
-CONFIG_PSE_REGULATOR=m
-CONFIG_STAGING_MEDIA_DEPRECATED=y
-# CONFIG_FORCE_NR_CPUS is not set
-# CONFIG_DEBUG_MAPLE_TREE is not set
-# CONFIG_KERNEL_GZIP is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_KERNEL_LZO is not set
-# CONFIG_KERNEL_LZ4 is not set
-CONFIG_KERNEL_ZSTD=y
-# CONFIG_KMSAN is not set
diff --git a/znver1.overrides b/znver1.overrides
new file mode 100644
index 0000000..f891f6c
--- /dev/null
+++ b/znver1.overrides
@@ -0,0 +1,138 @@
+# Remove support for all non-znver1 CPUs
+# CONFIG_GENERIC_CPU is not set
+CONFIG_MZEN=y
+# CONFIG_HAVE_INTEL_TXT is not set
+# CONFIG_X86_INTEL_LPSS is not set
+# CONFIG_CPU_SUP_INTEL is not set
+# CONFIG_CPU_SUP_CENTAUR is not set
+# CONFIG_CPU_SUP_ZHAOXIN is not set
+# CONFIG_X86_MCE_INTEL is not set
+# CONFIG_MICROCODE_INTEL is not set
+# CONFIG_X86_INTEL_PSTATE is not set
+# CONFIG_INTEL_IDLE is not set
+# CONFIG_INTEL_WMI is not set
+# CONFIG_SND_SOC_INTEL_SST_TOPLEVEL is not set
+# CONFIG_SND_SOC_INTEL_SST is not set
+# CONFIG_SND_SOC_INTEL_CATPT is not set
+# CONFIG_SND_SOC_INTEL_SKYLAKE is not set
+# CONFIG_SND_SOC_INTEL_SKL is not set
+# CONFIG_SND_SOC_INTEL_APL is not set
+# CONFIG_SND_SOC_INTEL_KBL is not set
+# CONFIG_SND_SOC_INTEL_GLK is not set
+# CONFIG_SND_SOC_INTEL_CNL is not set
+# CONFIG_SND_SOC_INTEL_CFL is not set
+# CONFIG_SND_SOC_INTEL_CML_H is not set
+# CONFIG_SND_SOC_INTEL_CML_LP is not set
+# CONFIG_SND_SOC_INTEL_SKYLAKE_FAMILY is not set
+# CONFIG_SND_SOC_INTEL_SKYLAKE_SSP_CLK is not set
+# CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC is not set
+# CONFIG_SND_SOC_INTEL_SKYLAKE_COMMON is not set
+# CONFIG_SND_SOC_ACPI_INTEL_MATCH is not set
+# CONFIG_SND_SOC_INTEL_AVS is not set
+# CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL is not set
+# CONFIG_SND_SOC_SOF_INTEL_IPC4 is not set
+# CONFIG_SND_SOC_SOF_INTEL_HIFI_EP_IPC is not set
+# CONFIG_SND_SOC_SOF_INTEL_ATOM_HIFI_EP is not set
+# CONFIG_SND_SOC_SOF_INTEL_COMMON is not set
+# CONFIG_SND_SOC_SOF_BAYTRAIL is not set
+# CONFIG_SND_SOC_SOF_BROADWELL is not set
+# CONFIG_SND_SOC_SOF_MERRIFIELD is not set
+# CONFIG_SND_SOC_SOF_INTEL_SKL is not set
+# CONFIG_SND_SOC_SOF_SKYLAKE is not set
+# CONFIG_SND_SOC_SOF_KABYLAKE is not set
+# CONFIG_SND_SOC_SOF_INTEL_APL is not set
+# CONFIG_SND_SOC_SOF_APOLLOLAKE is not set
+# CONFIG_SND_SOC_SOF_GEMINILAKE is not set
+# CONFIG_SND_SOC_SOF_INTEL_CNL is not set
+# CONFIG_SND_SOC_SOF_CANNONLAKE is not set
+# CONFIG_SND_SOC_SOF_COFFEELAKE is not set
+# CONFIG_SND_SOC_SOF_COMETLAKE is not set
+# CONFIG_SND_SOC_SOF_INTEL_ICL is not set
+# CONFIG_SND_SOC_SOF_ICELAKE is not set
+# CONFIG_SND_SOC_SOF_JASPERLAKE is not set
+# CONFIG_SND_SOC_SOF_INTEL_TGL is not set
+# CONFIG_SND_SOC_SOF_TIGERLAKE is not set
+# CONFIG_SND_SOC_SOF_ELKHARTLAKE is not set
+# CONFIG_SND_SOC_SOF_ALDERLAKE is not set
+# CONFIG_SND_SOC_SOF_INTEL_MTL is not set
+# CONFIG_SND_SOC_SOF_METEORLAKE is not set
+# CONFIG_SND_SOC_SOF_LUNARLAKE is not set
+# Yes, the line below is correct -- AMD NUMA is for pre-ACPI systems, and
+# not useful on anything near current AMD CPUs.
+# CONFIG_AMD_NUMA is not set
+# CONFIG_KVM_INTEL is not set
+# CONFIG_AGP_INTEL is not set
+# CONFIG_AGP_SIS is not set
+# CONFIG_AGP_VIA is not set
+# CONFIG_PECI is not set
+# CONFIG_INTEL_TDX_GUEST is not set
+# CONFIG_INTEL_IFS is not set
+# CONFIG_INTEL_MEI is not set
+# CONFIG_INTEL_TCC is not set
+
+# Bus types etc. that have been obsolete before the first znver1 CPU appeared in 2017
+# CONFIG_AGP is not set
+# CONFIG_PCMCIA is not set
+# CONFIG_CARDBUS is not set
+# CONFIG_PCCARD is not set
+# CONFIG_PARPORT is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_HPT3X3_DMA is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PCMCIA is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_PARPORT is not set
+# CONFIG_PATA_PARPORT_ATEN is not set
+# CONFIG_PATA_PARPORT_BPCK is not set
+# CONFIG_PATA_PARPORT_BPCK6 is not set
+# CONFIG_PATA_PARPORT_COMM is not set
+# CONFIG_PATA_PARPORT_DSTR is not set
+# CONFIG_PATA_PARPORT_FIT2 is not set
+# CONFIG_PATA_PARPORT_FIT3 is not set
+# CONFIG_PATA_PARPORT_EPAT is not set
+# CONFIG_PATA_PARPORT_EPATC8 is not set
+# CONFIG_PATA_PARPORT_EPIA is not set
+# CONFIG_PATA_PARPORT_FRIQ is not set
+# CONFIG_PATA_PARPORT_FRPW is not set
+# CONFIG_PATA_PARPORT_KBIC is not set
+# CONFIG_PATA_PARPORT_KTTI is not set
+# CONFIG_PATA_PARPORT_ON20 is not set
+# CONFIG_PATA_PARPORT_ON26 is not set
+# CONFIG_PATA_ACPI is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_KVM_INTEL_TDX is not set
Not Available

369start [@T] proton.meNo Comment.38d 00hrs
369start [@T] proton.meNo Comment.38d 00hrs
369start [@T] proton.meNo Comment.38d 00hrs